2006.201.01:19:58.17;Log Opened: Mark IV Field System Version 9.7.7 2006.201.01:19:58.17;location,TSUKUB32,-140.09,36.10,61.0 2006.201.01:19:58.17;horizon1,0.,5.,360. 2006.201.01:19:58.17;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.201.01:19:58.17;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.201.01:19:58.17;drivev11,330,270,no 2006.201.01:19:58.17;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.201.01:19:58.17;drivev13,15.000,268,10.000,10.000,10.000 2006.201.01:19:58.17;drivev21,330,270,no 2006.201.01:19:58.17;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.201.01:19:58.17;drivev23,15.000,268,10.000,10.000,10.000 2006.201.01:19:58.17;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.201.01:19:58.17;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.201.01:19:58.17;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.201.01:19:58.17;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.201.01:19:58.17;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.201.01:19:58.17;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.201.01:19:58.17;time,-0.364,101.533,rate 2006.201.01:19:58.17;flagr,200 2006.201.01:19:58.17:" JD0607 2006 TSUKUB32 T Ts 2006.201.01:19:58.17:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.201.01:19:58.17:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.201.01:19:58.17:" 108 K4-TSUKB 0 9149 2006.201.01:19:58.17:" drudg version 050216 compiled under FS 9.7.07 2006.201.01:19:58.17:" Rack=K4-2/M4 Recorder 1=K4-2 Recorder 2=none 2006.201.01:19:58.17:exper_initi 2006.201.01:19:58.17&exper_initi/proc_library 2006.201.01:19:58.17&exper_initi/sched_initi 2006.201.01:19:58.17:scan_name=201-0200,jd0607,40 2006.201.01:19:58.17:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.201.01:19:58.17#antcn#PM 1 00019 2005 228 00 22 31 00 2006.201.01:19:58.17#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.201.01:19:58.17#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.201.01:19:58.17#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.201.01:19:58.17#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.201.01:19:58.17#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.201.01:19:59.14#trakl#Waiting at limit 2006.201.01:19:59.14:ready_k5 2006.201.01:19:59.14&ready_k5/obsinfo=st 2006.201.01:19:59.14&ready_k5/autoobs=1 2006.201.01:19:59.14&ready_k5/autoobs=2 2006.201.01:19:59.14&ready_k5/autoobs=3 2006.201.01:19:59.14&ready_k5/autoobs=4 2006.201.01:19:59.14&ready_k5/obsinfo 2006.201.01:19:59.14#flagr#flagr/antenna,new-source 2006.201.01:19:59.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.201.01:20:02.90/autoobs//k5ts1/ autoobs started! 2006.201.01:20:06.33/autoobs//k5ts2/ autoobs started! 2006.201.01:20:09.79/autoobs//k5ts3/ autoobs started! 2006.201.01:20:13.21/autoobs//k5ts4/ autoobs started! 2006.201.01:20:13.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.01:20:13.24:setupk4=1 2006.201.01:20:13.24&setupk4/xlog=on 2006.201.01:20:13.24&setupk4/echo=on 2006.201.01:20:13.24&setupk4/pcalon 2006.201.01:20:13.24&setupk4/"tpicd=stop 2006.201.01:20:13.24&setupk4/"rec=synch_on 2006.201.01:20:13.24&setupk4/"rec_mode=128 2006.201.01:20:13.24&setupk4/!* 2006.201.01:20:13.24&setupk4/recpk4 2006.201.01:20:13.24&setupk4/vck44 2006.201.01:20:13.24&setupk4/ifdk4 2006.201.01:20:13.24&setupk4/!*+20s 2006.201.01:20:13.24&setupk4/"tpicd 2006.201.01:20:13.24&setupk4/echo=off 2006.201.01:20:13.24&setupk4/xlog=off 2006.201.01:20:13.24$setupk4/echo=on 2006.201.01:20:13.24$setupk4/pcalon 2006.201.01:20:13.24&pcalon/"no phase cal control is implemented here 2006.201.01:20:13.24$pcalon/"no phase cal control is implemented here 2006.201.01:20:13.24$setupk4/"tpicd=stop 2006.201.01:20:13.24$setupk4/"rec=synch_on 2006.201.01:20:13.24$setupk4/"rec_mode=128 2006.201.01:20:13.24$setupk4/!* 2006.201.01:20:13.24$setupk4/recpk4 2006.201.01:20:13.24&recpk4/recpatch= 2006.201.01:20:13.24&recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.01:20:13.24&recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.01:20:13.24$recpk4/recpatch= 2006.201.01:20:13.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.01:20:13.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.01:20:13.28$setupk4/vck44 2006.201.01:20:13.28&vck44/valo=1,524.99 2006.201.01:20:13.28&vck44/va=1,8 2006.201.01:20:13.28&vck44/valo=2,534.99 2006.201.01:20:13.28&vck44/va=2,7 2006.201.01:20:13.28&vck44/valo=3,564.99 2006.201.01:20:13.28&vck44/va=3,8 2006.201.01:20:13.28&vck44/valo=4,624.99 2006.201.01:20:13.28&vck44/va=4,7 2006.201.01:20:13.28&vck44/valo=5,734.99 2006.201.01:20:13.28&vck44/va=5,4 2006.201.01:20:13.28&vck44/valo=6,814.99 2006.201.01:20:13.28&vck44/va=6,5 2006.201.01:20:13.28&vck44/valo=7,864.99 2006.201.01:20:13.28&vck44/va=7,5 2006.201.01:20:13.28&vck44/valo=8,884.99 2006.201.01:20:13.28&vck44/va=8,4 2006.201.01:20:13.28&vck44/vblo=1,629.99 2006.201.01:20:13.28&vck44/vb=1,4 2006.201.01:20:13.28&vck44/vblo=2,634.99 2006.201.01:20:13.28&vck44/vb=2,5 2006.201.01:20:13.28&vck44/vblo=3,649.99 2006.201.01:20:13.28&vck44/vb=3,4 2006.201.01:20:13.28&vck44/vblo=4,679.99 2006.201.01:20:13.28&vck44/vb=4,5 2006.201.01:20:13.28&vck44/vblo=5,709.99 2006.201.01:20:13.28&vck44/vb=5,4 2006.201.01:20:13.28&vck44/vblo=6,719.99 2006.201.01:20:13.28&vck44/vb=6,4 2006.201.01:20:13.28&vck44/vblo=7,734.99 2006.201.01:20:13.28&vck44/vb=7,4 2006.201.01:20:13.28&vck44/vblo=8,744.99 2006.201.01:20:13.28&vck44/vb=8,4 2006.201.01:20:13.28&vck44/vabw=wide 2006.201.01:20:13.28&vck44/vbbw=wide 2006.201.01:20:13.28$vck44/valo=1,524.99 2006.201.01:20:13.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.01:20:13.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:13.28#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:13.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:13.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:13.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:13.28#ibcon#enter wrdev, iclass 26, count 0 2006.201.01:20:13.28#ibcon#first serial, iclass 26, count 0 2006.201.01:20:13.28#ibcon#enter sib2, iclass 26, count 0 2006.201.01:20:13.28#ibcon#flushed, iclass 26, count 0 2006.201.01:20:13.28#ibcon#about to write, iclass 26, count 0 2006.201.01:20:13.28#ibcon#wrote, iclass 26, count 0 2006.201.01:20:13.28#ibcon#about to read 3, iclass 26, count 0 2006.201.01:20:13.30#ibcon#read 3, iclass 26, count 0 2006.201.01:20:13.30#ibcon#about to read 4, iclass 26, count 0 2006.201.01:20:13.30#ibcon#read 4, iclass 26, count 0 2006.201.01:20:13.30#ibcon#about to read 5, iclass 26, count 0 2006.201.01:20:13.30#ibcon#read 5, iclass 26, count 0 2006.201.01:20:13.30#ibcon#about to read 6, iclass 26, count 0 2006.201.01:20:13.30#ibcon#read 6, iclass 26, count 0 2006.201.01:20:13.30#ibcon#end of sib2, iclass 26, count 0 2006.201.01:20:13.30#ibcon#*mode == 0, iclass 26, count 0 2006.201.01:20:13.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.01:20:13.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.01:20:13.30#ibcon#*before write, iclass 26, count 0 2006.201.01:20:13.30#ibcon#enter sib2, iclass 26, count 0 2006.201.01:20:13.30#ibcon#flushed, iclass 26, count 0 2006.201.01:20:13.30#ibcon#about to write, iclass 26, count 0 2006.201.01:20:13.30#ibcon#wrote, iclass 26, count 0 2006.201.01:20:13.30#ibcon#about to read 3, iclass 26, count 0 2006.201.01:20:13.36#ibcon#read 3, iclass 26, count 0 2006.201.01:20:13.36#ibcon#about to read 4, iclass 26, count 0 2006.201.01:20:13.36#ibcon#read 4, iclass 26, count 0 2006.201.01:20:13.36#ibcon#about to read 5, iclass 26, count 0 2006.201.01:20:13.36#ibcon#read 5, iclass 26, count 0 2006.201.01:20:13.36#ibcon#about to read 6, iclass 26, count 0 2006.201.01:20:13.36#ibcon#read 6, iclass 26, count 0 2006.201.01:20:13.36#ibcon#end of sib2, iclass 26, count 0 2006.201.01:20:13.36#ibcon#*after write, iclass 26, count 0 2006.201.01:20:13.36#ibcon#*before return 0, iclass 26, count 0 2006.201.01:20:13.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:13.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:13.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.01:20:13.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.01:20:13.36$vck44/va=1,8 2006.201.01:20:13.36#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.01:20:13.36#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.01:20:13.36#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:13.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:13.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:13.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:13.36#ibcon#enter wrdev, iclass 28, count 2 2006.201.01:20:13.36#ibcon#first serial, iclass 28, count 2 2006.201.01:20:13.36#ibcon#enter sib2, iclass 28, count 2 2006.201.01:20:13.36#ibcon#flushed, iclass 28, count 2 2006.201.01:20:13.36#ibcon#about to write, iclass 28, count 2 2006.201.01:20:13.36#ibcon#wrote, iclass 28, count 2 2006.201.01:20:13.36#ibcon#about to read 3, iclass 28, count 2 2006.201.01:20:13.38#ibcon#read 3, iclass 28, count 2 2006.201.01:20:13.38#ibcon#about to read 4, iclass 28, count 2 2006.201.01:20:13.38#ibcon#read 4, iclass 28, count 2 2006.201.01:20:13.38#ibcon#about to read 5, iclass 28, count 2 2006.201.01:20:13.38#ibcon#read 5, iclass 28, count 2 2006.201.01:20:13.38#ibcon#about to read 6, iclass 28, count 2 2006.201.01:20:13.38#ibcon#read 6, iclass 28, count 2 2006.201.01:20:13.38#ibcon#end of sib2, iclass 28, count 2 2006.201.01:20:13.38#ibcon#*mode == 0, iclass 28, count 2 2006.201.01:20:13.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.01:20:13.38#ibcon#[25=AT01-08\r\n] 2006.201.01:20:13.38#ibcon#*before write, iclass 28, count 2 2006.201.01:20:13.38#ibcon#enter sib2, iclass 28, count 2 2006.201.01:20:13.38#ibcon#flushed, iclass 28, count 2 2006.201.01:20:13.38#ibcon#about to write, iclass 28, count 2 2006.201.01:20:13.38#ibcon#wrote, iclass 28, count 2 2006.201.01:20:13.38#ibcon#about to read 3, iclass 28, count 2 2006.201.01:20:13.41#ibcon#read 3, iclass 28, count 2 2006.201.01:20:13.41#ibcon#about to read 4, iclass 28, count 2 2006.201.01:20:13.41#ibcon#read 4, iclass 28, count 2 2006.201.01:20:13.41#ibcon#about to read 5, iclass 28, count 2 2006.201.01:20:13.41#ibcon#read 5, iclass 28, count 2 2006.201.01:20:13.41#ibcon#about to read 6, iclass 28, count 2 2006.201.01:20:13.41#ibcon#read 6, iclass 28, count 2 2006.201.01:20:13.41#ibcon#end of sib2, iclass 28, count 2 2006.201.01:20:13.41#ibcon#*after write, iclass 28, count 2 2006.201.01:20:13.41#ibcon#*before return 0, iclass 28, count 2 2006.201.01:20:13.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:13.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:13.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.01:20:13.41#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:13.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:13.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:13.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:13.53#ibcon#enter wrdev, iclass 28, count 0 2006.201.01:20:13.53#ibcon#first serial, iclass 28, count 0 2006.201.01:20:13.53#ibcon#enter sib2, iclass 28, count 0 2006.201.01:20:13.53#ibcon#flushed, iclass 28, count 0 2006.201.01:20:13.53#ibcon#about to write, iclass 28, count 0 2006.201.01:20:13.53#ibcon#wrote, iclass 28, count 0 2006.201.01:20:13.53#ibcon#about to read 3, iclass 28, count 0 2006.201.01:20:13.55#ibcon#read 3, iclass 28, count 0 2006.201.01:20:13.55#ibcon#about to read 4, iclass 28, count 0 2006.201.01:20:13.55#ibcon#read 4, iclass 28, count 0 2006.201.01:20:13.55#ibcon#about to read 5, iclass 28, count 0 2006.201.01:20:13.55#ibcon#read 5, iclass 28, count 0 2006.201.01:20:13.55#ibcon#about to read 6, iclass 28, count 0 2006.201.01:20:13.55#ibcon#read 6, iclass 28, count 0 2006.201.01:20:13.55#ibcon#end of sib2, iclass 28, count 0 2006.201.01:20:13.55#ibcon#*mode == 0, iclass 28, count 0 2006.201.01:20:13.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.01:20:13.55#ibcon#[25=USB\r\n] 2006.201.01:20:13.55#ibcon#*before write, iclass 28, count 0 2006.201.01:20:13.55#ibcon#enter sib2, iclass 28, count 0 2006.201.01:20:13.55#ibcon#flushed, iclass 28, count 0 2006.201.01:20:13.55#ibcon#about to write, iclass 28, count 0 2006.201.01:20:13.55#ibcon#wrote, iclass 28, count 0 2006.201.01:20:13.55#ibcon#about to read 3, iclass 28, count 0 2006.201.01:20:13.58#ibcon#read 3, iclass 28, count 0 2006.201.01:20:13.58#ibcon#about to read 4, iclass 28, count 0 2006.201.01:20:13.58#ibcon#read 4, iclass 28, count 0 2006.201.01:20:13.58#ibcon#about to read 5, iclass 28, count 0 2006.201.01:20:13.58#ibcon#read 5, iclass 28, count 0 2006.201.01:20:13.58#ibcon#about to read 6, iclass 28, count 0 2006.201.01:20:13.58#ibcon#read 6, iclass 28, count 0 2006.201.01:20:13.58#ibcon#end of sib2, iclass 28, count 0 2006.201.01:20:13.58#ibcon#*after write, iclass 28, count 0 2006.201.01:20:13.58#ibcon#*before return 0, iclass 28, count 0 2006.201.01:20:13.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:13.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:13.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.01:20:13.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.01:20:13.58$vck44/valo=2,534.99 2006.201.01:20:13.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.01:20:13.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:13.58#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:13.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:13.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:13.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:13.58#ibcon#enter wrdev, iclass 30, count 0 2006.201.01:20:13.58#ibcon#first serial, iclass 30, count 0 2006.201.01:20:13.58#ibcon#enter sib2, iclass 30, count 0 2006.201.01:20:13.58#ibcon#flushed, iclass 30, count 0 2006.201.01:20:13.58#ibcon#about to write, iclass 30, count 0 2006.201.01:20:13.58#ibcon#wrote, iclass 30, count 0 2006.201.01:20:13.58#ibcon#about to read 3, iclass 30, count 0 2006.201.01:20:13.60#ibcon#read 3, iclass 30, count 0 2006.201.01:20:13.60#ibcon#about to read 4, iclass 30, count 0 2006.201.01:20:13.60#ibcon#read 4, iclass 30, count 0 2006.201.01:20:13.60#ibcon#about to read 5, iclass 30, count 0 2006.201.01:20:13.60#ibcon#read 5, iclass 30, count 0 2006.201.01:20:13.60#ibcon#about to read 6, iclass 30, count 0 2006.201.01:20:13.60#ibcon#read 6, iclass 30, count 0 2006.201.01:20:13.60#ibcon#end of sib2, iclass 30, count 0 2006.201.01:20:13.60#ibcon#*mode == 0, iclass 30, count 0 2006.201.01:20:13.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.01:20:13.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.01:20:13.60#ibcon#*before write, iclass 30, count 0 2006.201.01:20:13.60#ibcon#enter sib2, iclass 30, count 0 2006.201.01:20:13.60#ibcon#flushed, iclass 30, count 0 2006.201.01:20:13.60#ibcon#about to write, iclass 30, count 0 2006.201.01:20:13.60#ibcon#wrote, iclass 30, count 0 2006.201.01:20:13.60#ibcon#about to read 3, iclass 30, count 0 2006.201.01:20:13.64#ibcon#read 3, iclass 30, count 0 2006.201.01:20:13.64#ibcon#about to read 4, iclass 30, count 0 2006.201.01:20:13.64#ibcon#read 4, iclass 30, count 0 2006.201.01:20:13.64#ibcon#about to read 5, iclass 30, count 0 2006.201.01:20:13.64#ibcon#read 5, iclass 30, count 0 2006.201.01:20:13.64#ibcon#about to read 6, iclass 30, count 0 2006.201.01:20:13.64#ibcon#read 6, iclass 30, count 0 2006.201.01:20:13.64#ibcon#end of sib2, iclass 30, count 0 2006.201.01:20:13.64#ibcon#*after write, iclass 30, count 0 2006.201.01:20:13.64#ibcon#*before return 0, iclass 30, count 0 2006.201.01:20:13.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:13.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:13.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.01:20:13.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.01:20:13.64$vck44/va=2,7 2006.201.01:20:13.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.01:20:13.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.01:20:13.64#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:13.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:13.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:13.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:13.70#ibcon#enter wrdev, iclass 32, count 2 2006.201.01:20:13.70#ibcon#first serial, iclass 32, count 2 2006.201.01:20:13.70#ibcon#enter sib2, iclass 32, count 2 2006.201.01:20:13.70#ibcon#flushed, iclass 32, count 2 2006.201.01:20:13.70#ibcon#about to write, iclass 32, count 2 2006.201.01:20:13.70#ibcon#wrote, iclass 32, count 2 2006.201.01:20:13.70#ibcon#about to read 3, iclass 32, count 2 2006.201.01:20:13.72#ibcon#read 3, iclass 32, count 2 2006.201.01:20:13.72#ibcon#about to read 4, iclass 32, count 2 2006.201.01:20:13.72#ibcon#read 4, iclass 32, count 2 2006.201.01:20:13.72#ibcon#about to read 5, iclass 32, count 2 2006.201.01:20:13.72#ibcon#read 5, iclass 32, count 2 2006.201.01:20:13.72#ibcon#about to read 6, iclass 32, count 2 2006.201.01:20:13.72#ibcon#read 6, iclass 32, count 2 2006.201.01:20:13.72#ibcon#end of sib2, iclass 32, count 2 2006.201.01:20:13.72#ibcon#*mode == 0, iclass 32, count 2 2006.201.01:20:13.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.01:20:13.72#ibcon#[25=AT02-07\r\n] 2006.201.01:20:13.72#ibcon#*before write, iclass 32, count 2 2006.201.01:20:13.72#ibcon#enter sib2, iclass 32, count 2 2006.201.01:20:13.72#ibcon#flushed, iclass 32, count 2 2006.201.01:20:13.72#ibcon#about to write, iclass 32, count 2 2006.201.01:20:13.72#ibcon#wrote, iclass 32, count 2 2006.201.01:20:13.72#ibcon#about to read 3, iclass 32, count 2 2006.201.01:20:13.75#ibcon#read 3, iclass 32, count 2 2006.201.01:20:13.75#ibcon#about to read 4, iclass 32, count 2 2006.201.01:20:13.75#ibcon#read 4, iclass 32, count 2 2006.201.01:20:13.75#ibcon#about to read 5, iclass 32, count 2 2006.201.01:20:13.75#ibcon#read 5, iclass 32, count 2 2006.201.01:20:13.75#ibcon#about to read 6, iclass 32, count 2 2006.201.01:20:13.75#ibcon#read 6, iclass 32, count 2 2006.201.01:20:13.75#ibcon#end of sib2, iclass 32, count 2 2006.201.01:20:13.75#ibcon#*after write, iclass 32, count 2 2006.201.01:20:13.75#ibcon#*before return 0, iclass 32, count 2 2006.201.01:20:13.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:13.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:13.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.01:20:13.75#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:13.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:13.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:13.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:13.87#ibcon#enter wrdev, iclass 32, count 0 2006.201.01:20:13.87#ibcon#first serial, iclass 32, count 0 2006.201.01:20:13.87#ibcon#enter sib2, iclass 32, count 0 2006.201.01:20:13.87#ibcon#flushed, iclass 32, count 0 2006.201.01:20:13.87#ibcon#about to write, iclass 32, count 0 2006.201.01:20:13.87#ibcon#wrote, iclass 32, count 0 2006.201.01:20:13.87#ibcon#about to read 3, iclass 32, count 0 2006.201.01:20:13.89#ibcon#read 3, iclass 32, count 0 2006.201.01:20:13.89#ibcon#about to read 4, iclass 32, count 0 2006.201.01:20:13.89#ibcon#read 4, iclass 32, count 0 2006.201.01:20:13.89#ibcon#about to read 5, iclass 32, count 0 2006.201.01:20:13.89#ibcon#read 5, iclass 32, count 0 2006.201.01:20:13.89#ibcon#about to read 6, iclass 32, count 0 2006.201.01:20:13.89#ibcon#read 6, iclass 32, count 0 2006.201.01:20:13.89#ibcon#end of sib2, iclass 32, count 0 2006.201.01:20:13.89#ibcon#*mode == 0, iclass 32, count 0 2006.201.01:20:13.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.01:20:13.89#ibcon#[25=USB\r\n] 2006.201.01:20:13.89#ibcon#*before write, iclass 32, count 0 2006.201.01:20:13.89#ibcon#enter sib2, iclass 32, count 0 2006.201.01:20:13.89#ibcon#flushed, iclass 32, count 0 2006.201.01:20:13.89#ibcon#about to write, iclass 32, count 0 2006.201.01:20:13.89#ibcon#wrote, iclass 32, count 0 2006.201.01:20:13.89#ibcon#about to read 3, iclass 32, count 0 2006.201.01:20:13.92#ibcon#read 3, iclass 32, count 0 2006.201.01:20:13.92#ibcon#about to read 4, iclass 32, count 0 2006.201.01:20:13.92#ibcon#read 4, iclass 32, count 0 2006.201.01:20:13.92#ibcon#about to read 5, iclass 32, count 0 2006.201.01:20:13.92#ibcon#read 5, iclass 32, count 0 2006.201.01:20:13.92#ibcon#about to read 6, iclass 32, count 0 2006.201.01:20:13.92#ibcon#read 6, iclass 32, count 0 2006.201.01:20:13.92#ibcon#end of sib2, iclass 32, count 0 2006.201.01:20:13.92#ibcon#*after write, iclass 32, count 0 2006.201.01:20:13.92#ibcon#*before return 0, iclass 32, count 0 2006.201.01:20:13.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:13.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:13.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.01:20:13.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.01:20:13.92$vck44/valo=3,564.99 2006.201.01:20:13.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.01:20:13.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:13.92#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:13.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:13.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:13.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:13.92#ibcon#enter wrdev, iclass 34, count 0 2006.201.01:20:13.92#ibcon#first serial, iclass 34, count 0 2006.201.01:20:13.92#ibcon#enter sib2, iclass 34, count 0 2006.201.01:20:13.92#ibcon#flushed, iclass 34, count 0 2006.201.01:20:13.92#ibcon#about to write, iclass 34, count 0 2006.201.01:20:13.92#ibcon#wrote, iclass 34, count 0 2006.201.01:20:13.92#ibcon#about to read 3, iclass 34, count 0 2006.201.01:20:13.94#ibcon#read 3, iclass 34, count 0 2006.201.01:20:13.94#ibcon#about to read 4, iclass 34, count 0 2006.201.01:20:13.94#ibcon#read 4, iclass 34, count 0 2006.201.01:20:13.94#ibcon#about to read 5, iclass 34, count 0 2006.201.01:20:13.94#ibcon#read 5, iclass 34, count 0 2006.201.01:20:13.94#ibcon#about to read 6, iclass 34, count 0 2006.201.01:20:13.94#ibcon#read 6, iclass 34, count 0 2006.201.01:20:13.94#ibcon#end of sib2, iclass 34, count 0 2006.201.01:20:13.94#ibcon#*mode == 0, iclass 34, count 0 2006.201.01:20:13.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.01:20:13.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.01:20:13.94#ibcon#*before write, iclass 34, count 0 2006.201.01:20:13.94#ibcon#enter sib2, iclass 34, count 0 2006.201.01:20:13.94#ibcon#flushed, iclass 34, count 0 2006.201.01:20:13.94#ibcon#about to write, iclass 34, count 0 2006.201.01:20:13.94#ibcon#wrote, iclass 34, count 0 2006.201.01:20:13.94#ibcon#about to read 3, iclass 34, count 0 2006.201.01:20:13.98#ibcon#read 3, iclass 34, count 0 2006.201.01:20:13.98#ibcon#about to read 4, iclass 34, count 0 2006.201.01:20:13.98#ibcon#read 4, iclass 34, count 0 2006.201.01:20:13.98#ibcon#about to read 5, iclass 34, count 0 2006.201.01:20:13.98#ibcon#read 5, iclass 34, count 0 2006.201.01:20:13.98#ibcon#about to read 6, iclass 34, count 0 2006.201.01:20:13.98#ibcon#read 6, iclass 34, count 0 2006.201.01:20:13.98#ibcon#end of sib2, iclass 34, count 0 2006.201.01:20:13.98#ibcon#*after write, iclass 34, count 0 2006.201.01:20:13.98#ibcon#*before return 0, iclass 34, count 0 2006.201.01:20:13.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:13.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:13.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.01:20:13.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.01:20:13.98$vck44/va=3,8 2006.201.01:20:13.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.01:20:13.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.01:20:13.98#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:13.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:14.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:14.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:14.04#ibcon#enter wrdev, iclass 36, count 2 2006.201.01:20:14.04#ibcon#first serial, iclass 36, count 2 2006.201.01:20:14.04#ibcon#enter sib2, iclass 36, count 2 2006.201.01:20:14.04#ibcon#flushed, iclass 36, count 2 2006.201.01:20:14.04#ibcon#about to write, iclass 36, count 2 2006.201.01:20:14.04#ibcon#wrote, iclass 36, count 2 2006.201.01:20:14.04#ibcon#about to read 3, iclass 36, count 2 2006.201.01:20:14.06#ibcon#read 3, iclass 36, count 2 2006.201.01:20:14.06#ibcon#about to read 4, iclass 36, count 2 2006.201.01:20:14.06#ibcon#read 4, iclass 36, count 2 2006.201.01:20:14.06#ibcon#about to read 5, iclass 36, count 2 2006.201.01:20:14.06#ibcon#read 5, iclass 36, count 2 2006.201.01:20:14.06#ibcon#about to read 6, iclass 36, count 2 2006.201.01:20:14.06#ibcon#read 6, iclass 36, count 2 2006.201.01:20:14.06#ibcon#end of sib2, iclass 36, count 2 2006.201.01:20:14.06#ibcon#*mode == 0, iclass 36, count 2 2006.201.01:20:14.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.01:20:14.06#ibcon#[25=AT03-08\r\n] 2006.201.01:20:14.06#ibcon#*before write, iclass 36, count 2 2006.201.01:20:14.06#ibcon#enter sib2, iclass 36, count 2 2006.201.01:20:14.06#ibcon#flushed, iclass 36, count 2 2006.201.01:20:14.06#ibcon#about to write, iclass 36, count 2 2006.201.01:20:14.06#ibcon#wrote, iclass 36, count 2 2006.201.01:20:14.06#ibcon#about to read 3, iclass 36, count 2 2006.201.01:20:14.09#ibcon#read 3, iclass 36, count 2 2006.201.01:20:14.09#ibcon#about to read 4, iclass 36, count 2 2006.201.01:20:14.09#ibcon#read 4, iclass 36, count 2 2006.201.01:20:14.09#ibcon#about to read 5, iclass 36, count 2 2006.201.01:20:14.09#ibcon#read 5, iclass 36, count 2 2006.201.01:20:14.09#ibcon#about to read 6, iclass 36, count 2 2006.201.01:20:14.09#ibcon#read 6, iclass 36, count 2 2006.201.01:20:14.09#ibcon#end of sib2, iclass 36, count 2 2006.201.01:20:14.09#ibcon#*after write, iclass 36, count 2 2006.201.01:20:14.09#ibcon#*before return 0, iclass 36, count 2 2006.201.01:20:14.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:14.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:14.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.01:20:14.09#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:14.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:14.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:14.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:14.21#ibcon#enter wrdev, iclass 36, count 0 2006.201.01:20:14.21#ibcon#first serial, iclass 36, count 0 2006.201.01:20:14.21#ibcon#enter sib2, iclass 36, count 0 2006.201.01:20:14.21#ibcon#flushed, iclass 36, count 0 2006.201.01:20:14.21#ibcon#about to write, iclass 36, count 0 2006.201.01:20:14.21#ibcon#wrote, iclass 36, count 0 2006.201.01:20:14.21#ibcon#about to read 3, iclass 36, count 0 2006.201.01:20:14.23#ibcon#read 3, iclass 36, count 0 2006.201.01:20:14.23#ibcon#about to read 4, iclass 36, count 0 2006.201.01:20:14.23#ibcon#read 4, iclass 36, count 0 2006.201.01:20:14.23#ibcon#about to read 5, iclass 36, count 0 2006.201.01:20:14.23#ibcon#read 5, iclass 36, count 0 2006.201.01:20:14.23#ibcon#about to read 6, iclass 36, count 0 2006.201.01:20:14.23#ibcon#read 6, iclass 36, count 0 2006.201.01:20:14.23#ibcon#end of sib2, iclass 36, count 0 2006.201.01:20:14.23#ibcon#*mode == 0, iclass 36, count 0 2006.201.01:20:14.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.01:20:14.23#ibcon#[25=USB\r\n] 2006.201.01:20:14.23#ibcon#*before write, iclass 36, count 0 2006.201.01:20:14.23#ibcon#enter sib2, iclass 36, count 0 2006.201.01:20:14.23#ibcon#flushed, iclass 36, count 0 2006.201.01:20:14.23#ibcon#about to write, iclass 36, count 0 2006.201.01:20:14.23#ibcon#wrote, iclass 36, count 0 2006.201.01:20:14.23#ibcon#about to read 3, iclass 36, count 0 2006.201.01:20:14.26#ibcon#read 3, iclass 36, count 0 2006.201.01:20:14.26#ibcon#about to read 4, iclass 36, count 0 2006.201.01:20:14.26#ibcon#read 4, iclass 36, count 0 2006.201.01:20:14.26#ibcon#about to read 5, iclass 36, count 0 2006.201.01:20:14.26#ibcon#read 5, iclass 36, count 0 2006.201.01:20:14.26#ibcon#about to read 6, iclass 36, count 0 2006.201.01:20:14.26#ibcon#read 6, iclass 36, count 0 2006.201.01:20:14.26#ibcon#end of sib2, iclass 36, count 0 2006.201.01:20:14.26#ibcon#*after write, iclass 36, count 0 2006.201.01:20:14.26#ibcon#*before return 0, iclass 36, count 0 2006.201.01:20:14.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:14.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:14.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.01:20:14.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.01:20:14.26$vck44/valo=4,624.99 2006.201.01:20:14.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.01:20:14.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:14.26#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:14.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:14.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:14.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:14.26#ibcon#enter wrdev, iclass 38, count 0 2006.201.01:20:14.26#ibcon#first serial, iclass 38, count 0 2006.201.01:20:14.26#ibcon#enter sib2, iclass 38, count 0 2006.201.01:20:14.26#ibcon#flushed, iclass 38, count 0 2006.201.01:20:14.26#ibcon#about to write, iclass 38, count 0 2006.201.01:20:14.26#ibcon#wrote, iclass 38, count 0 2006.201.01:20:14.26#ibcon#about to read 3, iclass 38, count 0 2006.201.01:20:14.28#ibcon#read 3, iclass 38, count 0 2006.201.01:20:14.28#ibcon#about to read 4, iclass 38, count 0 2006.201.01:20:14.28#ibcon#read 4, iclass 38, count 0 2006.201.01:20:14.28#ibcon#about to read 5, iclass 38, count 0 2006.201.01:20:14.28#ibcon#read 5, iclass 38, count 0 2006.201.01:20:14.28#ibcon#about to read 6, iclass 38, count 0 2006.201.01:20:14.28#ibcon#read 6, iclass 38, count 0 2006.201.01:20:14.28#ibcon#end of sib2, iclass 38, count 0 2006.201.01:20:14.28#ibcon#*mode == 0, iclass 38, count 0 2006.201.01:20:14.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.01:20:14.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.01:20:14.28#ibcon#*before write, iclass 38, count 0 2006.201.01:20:14.28#ibcon#enter sib2, iclass 38, count 0 2006.201.01:20:14.28#ibcon#flushed, iclass 38, count 0 2006.201.01:20:14.28#ibcon#about to write, iclass 38, count 0 2006.201.01:20:14.28#ibcon#wrote, iclass 38, count 0 2006.201.01:20:14.28#ibcon#about to read 3, iclass 38, count 0 2006.201.01:20:14.32#ibcon#read 3, iclass 38, count 0 2006.201.01:20:14.32#ibcon#about to read 4, iclass 38, count 0 2006.201.01:20:14.32#ibcon#read 4, iclass 38, count 0 2006.201.01:20:14.32#ibcon#about to read 5, iclass 38, count 0 2006.201.01:20:14.32#ibcon#read 5, iclass 38, count 0 2006.201.01:20:14.32#ibcon#about to read 6, iclass 38, count 0 2006.201.01:20:14.32#ibcon#read 6, iclass 38, count 0 2006.201.01:20:14.32#ibcon#end of sib2, iclass 38, count 0 2006.201.01:20:14.32#ibcon#*after write, iclass 38, count 0 2006.201.01:20:14.32#ibcon#*before return 0, iclass 38, count 0 2006.201.01:20:14.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:14.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:14.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.01:20:14.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.01:20:14.32$vck44/va=4,7 2006.201.01:20:14.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.01:20:14.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.01:20:14.32#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:14.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:14.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:14.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:14.38#ibcon#enter wrdev, iclass 40, count 2 2006.201.01:20:14.38#ibcon#first serial, iclass 40, count 2 2006.201.01:20:14.38#ibcon#enter sib2, iclass 40, count 2 2006.201.01:20:14.38#ibcon#flushed, iclass 40, count 2 2006.201.01:20:14.38#ibcon#about to write, iclass 40, count 2 2006.201.01:20:14.38#ibcon#wrote, iclass 40, count 2 2006.201.01:20:14.38#ibcon#about to read 3, iclass 40, count 2 2006.201.01:20:14.40#ibcon#read 3, iclass 40, count 2 2006.201.01:20:14.40#ibcon#about to read 4, iclass 40, count 2 2006.201.01:20:14.40#ibcon#read 4, iclass 40, count 2 2006.201.01:20:14.40#ibcon#about to read 5, iclass 40, count 2 2006.201.01:20:14.40#ibcon#read 5, iclass 40, count 2 2006.201.01:20:14.40#ibcon#about to read 6, iclass 40, count 2 2006.201.01:20:14.40#ibcon#read 6, iclass 40, count 2 2006.201.01:20:14.40#ibcon#end of sib2, iclass 40, count 2 2006.201.01:20:14.40#ibcon#*mode == 0, iclass 40, count 2 2006.201.01:20:14.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.01:20:14.40#ibcon#[25=AT04-07\r\n] 2006.201.01:20:14.40#ibcon#*before write, iclass 40, count 2 2006.201.01:20:14.40#ibcon#enter sib2, iclass 40, count 2 2006.201.01:20:14.40#ibcon#flushed, iclass 40, count 2 2006.201.01:20:14.40#ibcon#about to write, iclass 40, count 2 2006.201.01:20:14.40#ibcon#wrote, iclass 40, count 2 2006.201.01:20:14.40#ibcon#about to read 3, iclass 40, count 2 2006.201.01:20:14.43#ibcon#read 3, iclass 40, count 2 2006.201.01:20:14.43#ibcon#about to read 4, iclass 40, count 2 2006.201.01:20:14.43#ibcon#read 4, iclass 40, count 2 2006.201.01:20:14.43#ibcon#about to read 5, iclass 40, count 2 2006.201.01:20:14.43#ibcon#read 5, iclass 40, count 2 2006.201.01:20:14.43#ibcon#about to read 6, iclass 40, count 2 2006.201.01:20:14.43#ibcon#read 6, iclass 40, count 2 2006.201.01:20:14.43#ibcon#end of sib2, iclass 40, count 2 2006.201.01:20:14.43#ibcon#*after write, iclass 40, count 2 2006.201.01:20:14.43#ibcon#*before return 0, iclass 40, count 2 2006.201.01:20:14.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:14.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:14.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.01:20:14.43#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:14.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:14.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:14.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:14.55#ibcon#enter wrdev, iclass 40, count 0 2006.201.01:20:14.55#ibcon#first serial, iclass 40, count 0 2006.201.01:20:14.55#ibcon#enter sib2, iclass 40, count 0 2006.201.01:20:14.55#ibcon#flushed, iclass 40, count 0 2006.201.01:20:14.55#ibcon#about to write, iclass 40, count 0 2006.201.01:20:14.55#ibcon#wrote, iclass 40, count 0 2006.201.01:20:14.55#ibcon#about to read 3, iclass 40, count 0 2006.201.01:20:14.57#ibcon#read 3, iclass 40, count 0 2006.201.01:20:14.57#ibcon#about to read 4, iclass 40, count 0 2006.201.01:20:14.57#ibcon#read 4, iclass 40, count 0 2006.201.01:20:14.57#ibcon#about to read 5, iclass 40, count 0 2006.201.01:20:14.57#ibcon#read 5, iclass 40, count 0 2006.201.01:20:14.57#ibcon#about to read 6, iclass 40, count 0 2006.201.01:20:14.57#ibcon#read 6, iclass 40, count 0 2006.201.01:20:14.57#ibcon#end of sib2, iclass 40, count 0 2006.201.01:20:14.57#ibcon#*mode == 0, iclass 40, count 0 2006.201.01:20:14.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.01:20:14.57#ibcon#[25=USB\r\n] 2006.201.01:20:14.57#ibcon#*before write, iclass 40, count 0 2006.201.01:20:14.57#ibcon#enter sib2, iclass 40, count 0 2006.201.01:20:14.57#ibcon#flushed, iclass 40, count 0 2006.201.01:20:14.57#ibcon#about to write, iclass 40, count 0 2006.201.01:20:14.57#ibcon#wrote, iclass 40, count 0 2006.201.01:20:14.57#ibcon#about to read 3, iclass 40, count 0 2006.201.01:20:14.60#ibcon#read 3, iclass 40, count 0 2006.201.01:20:14.60#ibcon#about to read 4, iclass 40, count 0 2006.201.01:20:14.60#ibcon#read 4, iclass 40, count 0 2006.201.01:20:14.60#ibcon#about to read 5, iclass 40, count 0 2006.201.01:20:14.60#ibcon#read 5, iclass 40, count 0 2006.201.01:20:14.60#ibcon#about to read 6, iclass 40, count 0 2006.201.01:20:14.60#ibcon#read 6, iclass 40, count 0 2006.201.01:20:14.60#ibcon#end of sib2, iclass 40, count 0 2006.201.01:20:14.60#ibcon#*after write, iclass 40, count 0 2006.201.01:20:14.60#ibcon#*before return 0, iclass 40, count 0 2006.201.01:20:14.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:14.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:14.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.01:20:14.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.01:20:14.60$vck44/valo=5,734.99 2006.201.01:20:14.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.01:20:14.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:14.60#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:14.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:14.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:14.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:14.60#ibcon#enter wrdev, iclass 4, count 0 2006.201.01:20:14.60#ibcon#first serial, iclass 4, count 0 2006.201.01:20:14.60#ibcon#enter sib2, iclass 4, count 0 2006.201.01:20:14.60#ibcon#flushed, iclass 4, count 0 2006.201.01:20:14.60#ibcon#about to write, iclass 4, count 0 2006.201.01:20:14.60#ibcon#wrote, iclass 4, count 0 2006.201.01:20:14.60#ibcon#about to read 3, iclass 4, count 0 2006.201.01:20:14.62#ibcon#read 3, iclass 4, count 0 2006.201.01:20:14.62#ibcon#about to read 4, iclass 4, count 0 2006.201.01:20:14.62#ibcon#read 4, iclass 4, count 0 2006.201.01:20:14.62#ibcon#about to read 5, iclass 4, count 0 2006.201.01:20:14.62#ibcon#read 5, iclass 4, count 0 2006.201.01:20:14.62#ibcon#about to read 6, iclass 4, count 0 2006.201.01:20:14.62#ibcon#read 6, iclass 4, count 0 2006.201.01:20:14.62#ibcon#end of sib2, iclass 4, count 0 2006.201.01:20:14.62#ibcon#*mode == 0, iclass 4, count 0 2006.201.01:20:14.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.01:20:14.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.01:20:14.62#ibcon#*before write, iclass 4, count 0 2006.201.01:20:14.62#ibcon#enter sib2, iclass 4, count 0 2006.201.01:20:14.62#ibcon#flushed, iclass 4, count 0 2006.201.01:20:14.62#ibcon#about to write, iclass 4, count 0 2006.201.01:20:14.62#ibcon#wrote, iclass 4, count 0 2006.201.01:20:14.62#ibcon#about to read 3, iclass 4, count 0 2006.201.01:20:14.66#ibcon#read 3, iclass 4, count 0 2006.201.01:20:14.66#ibcon#about to read 4, iclass 4, count 0 2006.201.01:20:14.66#ibcon#read 4, iclass 4, count 0 2006.201.01:20:14.66#ibcon#about to read 5, iclass 4, count 0 2006.201.01:20:14.66#ibcon#read 5, iclass 4, count 0 2006.201.01:20:14.66#ibcon#about to read 6, iclass 4, count 0 2006.201.01:20:14.66#ibcon#read 6, iclass 4, count 0 2006.201.01:20:14.66#ibcon#end of sib2, iclass 4, count 0 2006.201.01:20:14.66#ibcon#*after write, iclass 4, count 0 2006.201.01:20:14.66#ibcon#*before return 0, iclass 4, count 0 2006.201.01:20:14.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:14.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:14.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.01:20:14.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.01:20:14.66$vck44/va=5,4 2006.201.01:20:14.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.01:20:14.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.01:20:14.66#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:14.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:14.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:14.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:14.72#ibcon#enter wrdev, iclass 6, count 2 2006.201.01:20:14.72#ibcon#first serial, iclass 6, count 2 2006.201.01:20:14.72#ibcon#enter sib2, iclass 6, count 2 2006.201.01:20:14.72#ibcon#flushed, iclass 6, count 2 2006.201.01:20:14.72#ibcon#about to write, iclass 6, count 2 2006.201.01:20:14.72#ibcon#wrote, iclass 6, count 2 2006.201.01:20:14.72#ibcon#about to read 3, iclass 6, count 2 2006.201.01:20:14.74#ibcon#read 3, iclass 6, count 2 2006.201.01:20:14.74#ibcon#about to read 4, iclass 6, count 2 2006.201.01:20:14.74#ibcon#read 4, iclass 6, count 2 2006.201.01:20:14.74#ibcon#about to read 5, iclass 6, count 2 2006.201.01:20:14.74#ibcon#read 5, iclass 6, count 2 2006.201.01:20:14.74#ibcon#about to read 6, iclass 6, count 2 2006.201.01:20:14.74#ibcon#read 6, iclass 6, count 2 2006.201.01:20:14.74#ibcon#end of sib2, iclass 6, count 2 2006.201.01:20:14.74#ibcon#*mode == 0, iclass 6, count 2 2006.201.01:20:14.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.01:20:14.74#ibcon#[25=AT05-04\r\n] 2006.201.01:20:14.74#ibcon#*before write, iclass 6, count 2 2006.201.01:20:14.74#ibcon#enter sib2, iclass 6, count 2 2006.201.01:20:14.74#ibcon#flushed, iclass 6, count 2 2006.201.01:20:14.74#ibcon#about to write, iclass 6, count 2 2006.201.01:20:14.74#ibcon#wrote, iclass 6, count 2 2006.201.01:20:14.74#ibcon#about to read 3, iclass 6, count 2 2006.201.01:20:14.77#ibcon#read 3, iclass 6, count 2 2006.201.01:20:14.77#ibcon#about to read 4, iclass 6, count 2 2006.201.01:20:14.77#ibcon#read 4, iclass 6, count 2 2006.201.01:20:14.77#ibcon#about to read 5, iclass 6, count 2 2006.201.01:20:14.77#ibcon#read 5, iclass 6, count 2 2006.201.01:20:14.77#ibcon#about to read 6, iclass 6, count 2 2006.201.01:20:14.77#ibcon#read 6, iclass 6, count 2 2006.201.01:20:14.77#ibcon#end of sib2, iclass 6, count 2 2006.201.01:20:14.77#ibcon#*after write, iclass 6, count 2 2006.201.01:20:14.77#ibcon#*before return 0, iclass 6, count 2 2006.201.01:20:14.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:14.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:14.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.01:20:14.77#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:14.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:14.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:14.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:14.89#ibcon#enter wrdev, iclass 6, count 0 2006.201.01:20:14.89#ibcon#first serial, iclass 6, count 0 2006.201.01:20:14.89#ibcon#enter sib2, iclass 6, count 0 2006.201.01:20:14.89#ibcon#flushed, iclass 6, count 0 2006.201.01:20:14.89#ibcon#about to write, iclass 6, count 0 2006.201.01:20:14.89#ibcon#wrote, iclass 6, count 0 2006.201.01:20:14.89#ibcon#about to read 3, iclass 6, count 0 2006.201.01:20:14.91#ibcon#read 3, iclass 6, count 0 2006.201.01:20:14.91#ibcon#about to read 4, iclass 6, count 0 2006.201.01:20:14.91#ibcon#read 4, iclass 6, count 0 2006.201.01:20:14.91#ibcon#about to read 5, iclass 6, count 0 2006.201.01:20:14.91#ibcon#read 5, iclass 6, count 0 2006.201.01:20:14.91#ibcon#about to read 6, iclass 6, count 0 2006.201.01:20:14.91#ibcon#read 6, iclass 6, count 0 2006.201.01:20:14.91#ibcon#end of sib2, iclass 6, count 0 2006.201.01:20:14.91#ibcon#*mode == 0, iclass 6, count 0 2006.201.01:20:14.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.01:20:14.91#ibcon#[25=USB\r\n] 2006.201.01:20:14.91#ibcon#*before write, iclass 6, count 0 2006.201.01:20:14.91#ibcon#enter sib2, iclass 6, count 0 2006.201.01:20:14.91#ibcon#flushed, iclass 6, count 0 2006.201.01:20:14.91#ibcon#about to write, iclass 6, count 0 2006.201.01:20:14.91#ibcon#wrote, iclass 6, count 0 2006.201.01:20:14.91#ibcon#about to read 3, iclass 6, count 0 2006.201.01:20:14.94#ibcon#read 3, iclass 6, count 0 2006.201.01:20:14.94#ibcon#about to read 4, iclass 6, count 0 2006.201.01:20:14.94#ibcon#read 4, iclass 6, count 0 2006.201.01:20:14.94#ibcon#about to read 5, iclass 6, count 0 2006.201.01:20:14.94#ibcon#read 5, iclass 6, count 0 2006.201.01:20:14.94#ibcon#about to read 6, iclass 6, count 0 2006.201.01:20:14.94#ibcon#read 6, iclass 6, count 0 2006.201.01:20:14.94#ibcon#end of sib2, iclass 6, count 0 2006.201.01:20:14.94#ibcon#*after write, iclass 6, count 0 2006.201.01:20:14.94#ibcon#*before return 0, iclass 6, count 0 2006.201.01:20:14.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:14.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:14.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.01:20:14.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.01:20:14.94$vck44/valo=6,814.99 2006.201.01:20:14.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.01:20:14.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.01:20:14.94#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:14.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:14.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:14.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:14.94#ibcon#enter wrdev, iclass 10, count 0 2006.201.01:20:14.94#ibcon#first serial, iclass 10, count 0 2006.201.01:20:14.94#ibcon#enter sib2, iclass 10, count 0 2006.201.01:20:14.94#ibcon#flushed, iclass 10, count 0 2006.201.01:20:14.94#ibcon#about to write, iclass 10, count 0 2006.201.01:20:14.94#ibcon#wrote, iclass 10, count 0 2006.201.01:20:14.94#ibcon#about to read 3, iclass 10, count 0 2006.201.01:20:14.96#ibcon#read 3, iclass 10, count 0 2006.201.01:20:14.96#ibcon#about to read 4, iclass 10, count 0 2006.201.01:20:14.96#ibcon#read 4, iclass 10, count 0 2006.201.01:20:14.96#ibcon#about to read 5, iclass 10, count 0 2006.201.01:20:14.96#ibcon#read 5, iclass 10, count 0 2006.201.01:20:14.96#ibcon#about to read 6, iclass 10, count 0 2006.201.01:20:14.96#ibcon#read 6, iclass 10, count 0 2006.201.01:20:14.96#ibcon#end of sib2, iclass 10, count 0 2006.201.01:20:14.96#ibcon#*mode == 0, iclass 10, count 0 2006.201.01:20:14.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.01:20:14.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.01:20:14.96#ibcon#*before write, iclass 10, count 0 2006.201.01:20:14.96#ibcon#enter sib2, iclass 10, count 0 2006.201.01:20:14.96#ibcon#flushed, iclass 10, count 0 2006.201.01:20:14.96#ibcon#about to write, iclass 10, count 0 2006.201.01:20:14.96#ibcon#wrote, iclass 10, count 0 2006.201.01:20:14.96#ibcon#about to read 3, iclass 10, count 0 2006.201.01:20:15.00#ibcon#read 3, iclass 10, count 0 2006.201.01:20:15.00#ibcon#about to read 4, iclass 10, count 0 2006.201.01:20:15.00#ibcon#read 4, iclass 10, count 0 2006.201.01:20:15.00#ibcon#about to read 5, iclass 10, count 0 2006.201.01:20:15.00#ibcon#read 5, iclass 10, count 0 2006.201.01:20:15.00#ibcon#about to read 6, iclass 10, count 0 2006.201.01:20:15.00#ibcon#read 6, iclass 10, count 0 2006.201.01:20:15.00#ibcon#end of sib2, iclass 10, count 0 2006.201.01:20:15.00#ibcon#*after write, iclass 10, count 0 2006.201.01:20:15.00#ibcon#*before return 0, iclass 10, count 0 2006.201.01:20:15.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:15.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:15.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.01:20:15.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.01:20:15.00$vck44/va=6,5 2006.201.01:20:15.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.01:20:15.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.01:20:15.00#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:15.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:15.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:15.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:15.06#ibcon#enter wrdev, iclass 12, count 2 2006.201.01:20:15.06#ibcon#first serial, iclass 12, count 2 2006.201.01:20:15.06#ibcon#enter sib2, iclass 12, count 2 2006.201.01:20:15.06#ibcon#flushed, iclass 12, count 2 2006.201.01:20:15.06#ibcon#about to write, iclass 12, count 2 2006.201.01:20:15.06#ibcon#wrote, iclass 12, count 2 2006.201.01:20:15.06#ibcon#about to read 3, iclass 12, count 2 2006.201.01:20:15.08#ibcon#read 3, iclass 12, count 2 2006.201.01:20:15.08#ibcon#about to read 4, iclass 12, count 2 2006.201.01:20:15.08#ibcon#read 4, iclass 12, count 2 2006.201.01:20:15.08#ibcon#about to read 5, iclass 12, count 2 2006.201.01:20:15.08#ibcon#read 5, iclass 12, count 2 2006.201.01:20:15.08#ibcon#about to read 6, iclass 12, count 2 2006.201.01:20:15.08#ibcon#read 6, iclass 12, count 2 2006.201.01:20:15.08#ibcon#end of sib2, iclass 12, count 2 2006.201.01:20:15.08#ibcon#*mode == 0, iclass 12, count 2 2006.201.01:20:15.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.01:20:15.08#ibcon#[25=AT06-05\r\n] 2006.201.01:20:15.08#ibcon#*before write, iclass 12, count 2 2006.201.01:20:15.08#ibcon#enter sib2, iclass 12, count 2 2006.201.01:20:15.08#ibcon#flushed, iclass 12, count 2 2006.201.01:20:15.08#ibcon#about to write, iclass 12, count 2 2006.201.01:20:15.08#ibcon#wrote, iclass 12, count 2 2006.201.01:20:15.08#ibcon#about to read 3, iclass 12, count 2 2006.201.01:20:15.11#ibcon#read 3, iclass 12, count 2 2006.201.01:20:15.11#ibcon#about to read 4, iclass 12, count 2 2006.201.01:20:15.11#ibcon#read 4, iclass 12, count 2 2006.201.01:20:15.11#ibcon#about to read 5, iclass 12, count 2 2006.201.01:20:15.11#ibcon#read 5, iclass 12, count 2 2006.201.01:20:15.11#ibcon#about to read 6, iclass 12, count 2 2006.201.01:20:15.11#ibcon#read 6, iclass 12, count 2 2006.201.01:20:15.11#ibcon#end of sib2, iclass 12, count 2 2006.201.01:20:15.11#ibcon#*after write, iclass 12, count 2 2006.201.01:20:15.11#ibcon#*before return 0, iclass 12, count 2 2006.201.01:20:15.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:15.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:15.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.01:20:15.11#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:15.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:15.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:15.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:15.23#ibcon#enter wrdev, iclass 12, count 0 2006.201.01:20:15.23#ibcon#first serial, iclass 12, count 0 2006.201.01:20:15.23#ibcon#enter sib2, iclass 12, count 0 2006.201.01:20:15.23#ibcon#flushed, iclass 12, count 0 2006.201.01:20:15.23#ibcon#about to write, iclass 12, count 0 2006.201.01:20:15.23#ibcon#wrote, iclass 12, count 0 2006.201.01:20:15.23#ibcon#about to read 3, iclass 12, count 0 2006.201.01:20:15.25#ibcon#read 3, iclass 12, count 0 2006.201.01:20:15.25#ibcon#about to read 4, iclass 12, count 0 2006.201.01:20:15.25#ibcon#read 4, iclass 12, count 0 2006.201.01:20:15.25#ibcon#about to read 5, iclass 12, count 0 2006.201.01:20:15.25#ibcon#read 5, iclass 12, count 0 2006.201.01:20:15.25#ibcon#about to read 6, iclass 12, count 0 2006.201.01:20:15.25#ibcon#read 6, iclass 12, count 0 2006.201.01:20:15.25#ibcon#end of sib2, iclass 12, count 0 2006.201.01:20:15.25#ibcon#*mode == 0, iclass 12, count 0 2006.201.01:20:15.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.01:20:15.25#ibcon#[25=USB\r\n] 2006.201.01:20:15.25#ibcon#*before write, iclass 12, count 0 2006.201.01:20:15.25#ibcon#enter sib2, iclass 12, count 0 2006.201.01:20:15.25#ibcon#flushed, iclass 12, count 0 2006.201.01:20:15.25#ibcon#about to write, iclass 12, count 0 2006.201.01:20:15.25#ibcon#wrote, iclass 12, count 0 2006.201.01:20:15.25#ibcon#about to read 3, iclass 12, count 0 2006.201.01:20:15.28#ibcon#read 3, iclass 12, count 0 2006.201.01:20:15.28#ibcon#about to read 4, iclass 12, count 0 2006.201.01:20:15.28#ibcon#read 4, iclass 12, count 0 2006.201.01:20:15.28#ibcon#about to read 5, iclass 12, count 0 2006.201.01:20:15.28#ibcon#read 5, iclass 12, count 0 2006.201.01:20:15.28#ibcon#about to read 6, iclass 12, count 0 2006.201.01:20:15.28#ibcon#read 6, iclass 12, count 0 2006.201.01:20:15.28#ibcon#end of sib2, iclass 12, count 0 2006.201.01:20:15.28#ibcon#*after write, iclass 12, count 0 2006.201.01:20:15.28#ibcon#*before return 0, iclass 12, count 0 2006.201.01:20:15.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:15.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:15.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.01:20:15.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.01:20:15.28$vck44/valo=7,864.99 2006.201.01:20:15.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.01:20:15.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.01:20:15.28#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:15.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:15.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:15.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:15.28#ibcon#enter wrdev, iclass 14, count 0 2006.201.01:20:15.28#ibcon#first serial, iclass 14, count 0 2006.201.01:20:15.28#ibcon#enter sib2, iclass 14, count 0 2006.201.01:20:15.28#ibcon#flushed, iclass 14, count 0 2006.201.01:20:15.28#ibcon#about to write, iclass 14, count 0 2006.201.01:20:15.28#ibcon#wrote, iclass 14, count 0 2006.201.01:20:15.28#ibcon#about to read 3, iclass 14, count 0 2006.201.01:20:15.30#ibcon#read 3, iclass 14, count 0 2006.201.01:20:15.30#ibcon#about to read 4, iclass 14, count 0 2006.201.01:20:15.30#ibcon#read 4, iclass 14, count 0 2006.201.01:20:15.30#ibcon#about to read 5, iclass 14, count 0 2006.201.01:20:15.30#ibcon#read 5, iclass 14, count 0 2006.201.01:20:15.30#ibcon#about to read 6, iclass 14, count 0 2006.201.01:20:15.30#ibcon#read 6, iclass 14, count 0 2006.201.01:20:15.30#ibcon#end of sib2, iclass 14, count 0 2006.201.01:20:15.30#ibcon#*mode == 0, iclass 14, count 0 2006.201.01:20:15.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.01:20:15.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.01:20:15.30#ibcon#*before write, iclass 14, count 0 2006.201.01:20:15.30#ibcon#enter sib2, iclass 14, count 0 2006.201.01:20:15.30#ibcon#flushed, iclass 14, count 0 2006.201.01:20:15.30#ibcon#about to write, iclass 14, count 0 2006.201.01:20:15.30#ibcon#wrote, iclass 14, count 0 2006.201.01:20:15.30#ibcon#about to read 3, iclass 14, count 0 2006.201.01:20:15.34#ibcon#read 3, iclass 14, count 0 2006.201.01:20:15.34#ibcon#about to read 4, iclass 14, count 0 2006.201.01:20:15.34#ibcon#read 4, iclass 14, count 0 2006.201.01:20:15.34#ibcon#about to read 5, iclass 14, count 0 2006.201.01:20:15.34#ibcon#read 5, iclass 14, count 0 2006.201.01:20:15.34#ibcon#about to read 6, iclass 14, count 0 2006.201.01:20:15.34#ibcon#read 6, iclass 14, count 0 2006.201.01:20:15.34#ibcon#end of sib2, iclass 14, count 0 2006.201.01:20:15.34#ibcon#*after write, iclass 14, count 0 2006.201.01:20:15.34#ibcon#*before return 0, iclass 14, count 0 2006.201.01:20:15.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:15.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:15.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.01:20:15.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.01:20:15.34$vck44/va=7,5 2006.201.01:20:15.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.01:20:15.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.01:20:15.34#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:15.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:15.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:15.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:15.40#ibcon#enter wrdev, iclass 16, count 2 2006.201.01:20:15.40#ibcon#first serial, iclass 16, count 2 2006.201.01:20:15.40#ibcon#enter sib2, iclass 16, count 2 2006.201.01:20:15.40#ibcon#flushed, iclass 16, count 2 2006.201.01:20:15.40#ibcon#about to write, iclass 16, count 2 2006.201.01:20:15.40#ibcon#wrote, iclass 16, count 2 2006.201.01:20:15.40#ibcon#about to read 3, iclass 16, count 2 2006.201.01:20:15.42#ibcon#read 3, iclass 16, count 2 2006.201.01:20:15.42#ibcon#about to read 4, iclass 16, count 2 2006.201.01:20:15.42#ibcon#read 4, iclass 16, count 2 2006.201.01:20:15.42#ibcon#about to read 5, iclass 16, count 2 2006.201.01:20:15.42#ibcon#read 5, iclass 16, count 2 2006.201.01:20:15.42#ibcon#about to read 6, iclass 16, count 2 2006.201.01:20:15.42#ibcon#read 6, iclass 16, count 2 2006.201.01:20:15.42#ibcon#end of sib2, iclass 16, count 2 2006.201.01:20:15.42#ibcon#*mode == 0, iclass 16, count 2 2006.201.01:20:15.42#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.01:20:15.42#ibcon#[25=AT07-05\r\n] 2006.201.01:20:15.42#ibcon#*before write, iclass 16, count 2 2006.201.01:20:15.42#ibcon#enter sib2, iclass 16, count 2 2006.201.01:20:15.42#ibcon#flushed, iclass 16, count 2 2006.201.01:20:15.42#ibcon#about to write, iclass 16, count 2 2006.201.01:20:15.42#ibcon#wrote, iclass 16, count 2 2006.201.01:20:15.42#ibcon#about to read 3, iclass 16, count 2 2006.201.01:20:15.45#ibcon#read 3, iclass 16, count 2 2006.201.01:20:15.45#ibcon#about to read 4, iclass 16, count 2 2006.201.01:20:15.45#ibcon#read 4, iclass 16, count 2 2006.201.01:20:15.45#ibcon#about to read 5, iclass 16, count 2 2006.201.01:20:15.45#ibcon#read 5, iclass 16, count 2 2006.201.01:20:15.45#ibcon#about to read 6, iclass 16, count 2 2006.201.01:20:15.45#ibcon#read 6, iclass 16, count 2 2006.201.01:20:15.45#ibcon#end of sib2, iclass 16, count 2 2006.201.01:20:15.45#ibcon#*after write, iclass 16, count 2 2006.201.01:20:15.45#ibcon#*before return 0, iclass 16, count 2 2006.201.01:20:15.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:15.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:15.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.01:20:15.45#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:15.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:15.57#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:15.57#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:15.57#ibcon#enter wrdev, iclass 16, count 0 2006.201.01:20:15.57#ibcon#first serial, iclass 16, count 0 2006.201.01:20:15.57#ibcon#enter sib2, iclass 16, count 0 2006.201.01:20:15.57#ibcon#flushed, iclass 16, count 0 2006.201.01:20:15.57#ibcon#about to write, iclass 16, count 0 2006.201.01:20:15.57#ibcon#wrote, iclass 16, count 0 2006.201.01:20:15.57#ibcon#about to read 3, iclass 16, count 0 2006.201.01:20:15.59#ibcon#read 3, iclass 16, count 0 2006.201.01:20:15.59#ibcon#about to read 4, iclass 16, count 0 2006.201.01:20:15.59#ibcon#read 4, iclass 16, count 0 2006.201.01:20:15.59#ibcon#about to read 5, iclass 16, count 0 2006.201.01:20:15.59#ibcon#read 5, iclass 16, count 0 2006.201.01:20:15.59#ibcon#about to read 6, iclass 16, count 0 2006.201.01:20:15.59#ibcon#read 6, iclass 16, count 0 2006.201.01:20:15.59#ibcon#end of sib2, iclass 16, count 0 2006.201.01:20:15.59#ibcon#*mode == 0, iclass 16, count 0 2006.201.01:20:15.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.01:20:15.59#ibcon#[25=USB\r\n] 2006.201.01:20:15.59#ibcon#*before write, iclass 16, count 0 2006.201.01:20:15.59#ibcon#enter sib2, iclass 16, count 0 2006.201.01:20:15.59#ibcon#flushed, iclass 16, count 0 2006.201.01:20:15.59#ibcon#about to write, iclass 16, count 0 2006.201.01:20:15.59#ibcon#wrote, iclass 16, count 0 2006.201.01:20:15.59#ibcon#about to read 3, iclass 16, count 0 2006.201.01:20:15.62#ibcon#read 3, iclass 16, count 0 2006.201.01:20:15.62#ibcon#about to read 4, iclass 16, count 0 2006.201.01:20:15.62#ibcon#read 4, iclass 16, count 0 2006.201.01:20:15.62#ibcon#about to read 5, iclass 16, count 0 2006.201.01:20:15.62#ibcon#read 5, iclass 16, count 0 2006.201.01:20:15.62#ibcon#about to read 6, iclass 16, count 0 2006.201.01:20:15.62#ibcon#read 6, iclass 16, count 0 2006.201.01:20:15.62#ibcon#end of sib2, iclass 16, count 0 2006.201.01:20:15.62#ibcon#*after write, iclass 16, count 0 2006.201.01:20:15.62#ibcon#*before return 0, iclass 16, count 0 2006.201.01:20:15.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:15.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:15.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.01:20:15.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.01:20:15.62$vck44/valo=8,884.99 2006.201.01:20:15.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.01:20:15.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:15.62#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:15.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:15.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:15.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:15.62#ibcon#enter wrdev, iclass 18, count 0 2006.201.01:20:15.62#ibcon#first serial, iclass 18, count 0 2006.201.01:20:15.62#ibcon#enter sib2, iclass 18, count 0 2006.201.01:20:15.62#ibcon#flushed, iclass 18, count 0 2006.201.01:20:15.62#ibcon#about to write, iclass 18, count 0 2006.201.01:20:15.62#ibcon#wrote, iclass 18, count 0 2006.201.01:20:15.62#ibcon#about to read 3, iclass 18, count 0 2006.201.01:20:15.64#ibcon#read 3, iclass 18, count 0 2006.201.01:20:15.64#ibcon#about to read 4, iclass 18, count 0 2006.201.01:20:15.64#ibcon#read 4, iclass 18, count 0 2006.201.01:20:15.64#ibcon#about to read 5, iclass 18, count 0 2006.201.01:20:15.64#ibcon#read 5, iclass 18, count 0 2006.201.01:20:15.64#ibcon#about to read 6, iclass 18, count 0 2006.201.01:20:15.64#ibcon#read 6, iclass 18, count 0 2006.201.01:20:15.64#ibcon#end of sib2, iclass 18, count 0 2006.201.01:20:15.64#ibcon#*mode == 0, iclass 18, count 0 2006.201.01:20:15.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.01:20:15.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.01:20:15.64#ibcon#*before write, iclass 18, count 0 2006.201.01:20:15.64#ibcon#enter sib2, iclass 18, count 0 2006.201.01:20:15.64#ibcon#flushed, iclass 18, count 0 2006.201.01:20:15.64#ibcon#about to write, iclass 18, count 0 2006.201.01:20:15.64#ibcon#wrote, iclass 18, count 0 2006.201.01:20:15.64#ibcon#about to read 3, iclass 18, count 0 2006.201.01:20:15.68#ibcon#read 3, iclass 18, count 0 2006.201.01:20:15.68#ibcon#about to read 4, iclass 18, count 0 2006.201.01:20:15.68#ibcon#read 4, iclass 18, count 0 2006.201.01:20:15.68#ibcon#about to read 5, iclass 18, count 0 2006.201.01:20:15.68#ibcon#read 5, iclass 18, count 0 2006.201.01:20:15.68#ibcon#about to read 6, iclass 18, count 0 2006.201.01:20:15.68#ibcon#read 6, iclass 18, count 0 2006.201.01:20:15.68#ibcon#end of sib2, iclass 18, count 0 2006.201.01:20:15.68#ibcon#*after write, iclass 18, count 0 2006.201.01:20:15.68#ibcon#*before return 0, iclass 18, count 0 2006.201.01:20:15.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:15.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:15.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.01:20:15.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.01:20:15.68$vck44/va=8,4 2006.201.01:20:15.68#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.01:20:15.68#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.01:20:15.68#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:15.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.01:20:15.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.01:20:15.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.01:20:15.74#ibcon#enter wrdev, iclass 20, count 2 2006.201.01:20:15.74#ibcon#first serial, iclass 20, count 2 2006.201.01:20:15.74#ibcon#enter sib2, iclass 20, count 2 2006.201.01:20:15.74#ibcon#flushed, iclass 20, count 2 2006.201.01:20:15.74#ibcon#about to write, iclass 20, count 2 2006.201.01:20:15.74#ibcon#wrote, iclass 20, count 2 2006.201.01:20:15.74#ibcon#about to read 3, iclass 20, count 2 2006.201.01:20:15.76#ibcon#read 3, iclass 20, count 2 2006.201.01:20:15.76#ibcon#about to read 4, iclass 20, count 2 2006.201.01:20:15.76#ibcon#read 4, iclass 20, count 2 2006.201.01:20:15.76#ibcon#about to read 5, iclass 20, count 2 2006.201.01:20:15.76#ibcon#read 5, iclass 20, count 2 2006.201.01:20:15.76#ibcon#about to read 6, iclass 20, count 2 2006.201.01:20:15.76#ibcon#read 6, iclass 20, count 2 2006.201.01:20:15.76#ibcon#end of sib2, iclass 20, count 2 2006.201.01:20:15.76#ibcon#*mode == 0, iclass 20, count 2 2006.201.01:20:15.76#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.01:20:15.76#ibcon#[25=AT08-04\r\n] 2006.201.01:20:15.76#ibcon#*before write, iclass 20, count 2 2006.201.01:20:15.76#ibcon#enter sib2, iclass 20, count 2 2006.201.01:20:15.76#ibcon#flushed, iclass 20, count 2 2006.201.01:20:15.76#ibcon#about to write, iclass 20, count 2 2006.201.01:20:15.76#ibcon#wrote, iclass 20, count 2 2006.201.01:20:15.76#ibcon#about to read 3, iclass 20, count 2 2006.201.01:20:15.79#ibcon#read 3, iclass 20, count 2 2006.201.01:20:15.79#ibcon#about to read 4, iclass 20, count 2 2006.201.01:20:15.79#ibcon#read 4, iclass 20, count 2 2006.201.01:20:15.79#ibcon#about to read 5, iclass 20, count 2 2006.201.01:20:15.79#ibcon#read 5, iclass 20, count 2 2006.201.01:20:15.79#ibcon#about to read 6, iclass 20, count 2 2006.201.01:20:15.79#ibcon#read 6, iclass 20, count 2 2006.201.01:20:15.79#ibcon#end of sib2, iclass 20, count 2 2006.201.01:20:15.79#ibcon#*after write, iclass 20, count 2 2006.201.01:20:15.79#ibcon#*before return 0, iclass 20, count 2 2006.201.01:20:15.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.01:20:15.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.01:20:15.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.01:20:15.79#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:15.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.01:20:15.91#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.01:20:15.91#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.01:20:15.91#ibcon#enter wrdev, iclass 20, count 0 2006.201.01:20:15.91#ibcon#first serial, iclass 20, count 0 2006.201.01:20:15.91#ibcon#enter sib2, iclass 20, count 0 2006.201.01:20:15.91#ibcon#flushed, iclass 20, count 0 2006.201.01:20:15.91#ibcon#about to write, iclass 20, count 0 2006.201.01:20:15.91#ibcon#wrote, iclass 20, count 0 2006.201.01:20:15.91#ibcon#about to read 3, iclass 20, count 0 2006.201.01:20:15.93#ibcon#read 3, iclass 20, count 0 2006.201.01:20:15.93#ibcon#about to read 4, iclass 20, count 0 2006.201.01:20:15.93#ibcon#read 4, iclass 20, count 0 2006.201.01:20:15.93#ibcon#about to read 5, iclass 20, count 0 2006.201.01:20:15.93#ibcon#read 5, iclass 20, count 0 2006.201.01:20:15.93#ibcon#about to read 6, iclass 20, count 0 2006.201.01:20:15.93#ibcon#read 6, iclass 20, count 0 2006.201.01:20:15.93#ibcon#end of sib2, iclass 20, count 0 2006.201.01:20:15.93#ibcon#*mode == 0, iclass 20, count 0 2006.201.01:20:15.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.01:20:15.93#ibcon#[25=USB\r\n] 2006.201.01:20:15.93#ibcon#*before write, iclass 20, count 0 2006.201.01:20:15.93#ibcon#enter sib2, iclass 20, count 0 2006.201.01:20:15.93#ibcon#flushed, iclass 20, count 0 2006.201.01:20:15.93#ibcon#about to write, iclass 20, count 0 2006.201.01:20:15.93#ibcon#wrote, iclass 20, count 0 2006.201.01:20:15.93#ibcon#about to read 3, iclass 20, count 0 2006.201.01:20:15.96#ibcon#read 3, iclass 20, count 0 2006.201.01:20:15.96#ibcon#about to read 4, iclass 20, count 0 2006.201.01:20:15.96#ibcon#read 4, iclass 20, count 0 2006.201.01:20:15.96#ibcon#about to read 5, iclass 20, count 0 2006.201.01:20:15.96#ibcon#read 5, iclass 20, count 0 2006.201.01:20:15.96#ibcon#about to read 6, iclass 20, count 0 2006.201.01:20:15.96#ibcon#read 6, iclass 20, count 0 2006.201.01:20:15.96#ibcon#end of sib2, iclass 20, count 0 2006.201.01:20:15.96#ibcon#*after write, iclass 20, count 0 2006.201.01:20:15.96#ibcon#*before return 0, iclass 20, count 0 2006.201.01:20:15.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.01:20:15.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.01:20:15.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.01:20:15.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.01:20:15.96$vck44/vblo=1,629.99 2006.201.01:20:15.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.01:20:15.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:15.96#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:15.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.01:20:15.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.01:20:15.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.01:20:15.96#ibcon#enter wrdev, iclass 22, count 0 2006.201.01:20:15.96#ibcon#first serial, iclass 22, count 0 2006.201.01:20:15.96#ibcon#enter sib2, iclass 22, count 0 2006.201.01:20:15.96#ibcon#flushed, iclass 22, count 0 2006.201.01:20:15.96#ibcon#about to write, iclass 22, count 0 2006.201.01:20:15.96#ibcon#wrote, iclass 22, count 0 2006.201.01:20:15.96#ibcon#about to read 3, iclass 22, count 0 2006.201.01:20:15.98#ibcon#read 3, iclass 22, count 0 2006.201.01:20:15.98#ibcon#about to read 4, iclass 22, count 0 2006.201.01:20:15.98#ibcon#read 4, iclass 22, count 0 2006.201.01:20:15.98#ibcon#about to read 5, iclass 22, count 0 2006.201.01:20:15.98#ibcon#read 5, iclass 22, count 0 2006.201.01:20:15.98#ibcon#about to read 6, iclass 22, count 0 2006.201.01:20:15.98#ibcon#read 6, iclass 22, count 0 2006.201.01:20:15.98#ibcon#end of sib2, iclass 22, count 0 2006.201.01:20:15.98#ibcon#*mode == 0, iclass 22, count 0 2006.201.01:20:15.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.01:20:15.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.01:20:15.98#ibcon#*before write, iclass 22, count 0 2006.201.01:20:15.98#ibcon#enter sib2, iclass 22, count 0 2006.201.01:20:15.98#ibcon#flushed, iclass 22, count 0 2006.201.01:20:15.98#ibcon#about to write, iclass 22, count 0 2006.201.01:20:15.98#ibcon#wrote, iclass 22, count 0 2006.201.01:20:15.98#ibcon#about to read 3, iclass 22, count 0 2006.201.01:20:16.04#ibcon#read 3, iclass 22, count 0 2006.201.01:20:16.04#ibcon#about to read 4, iclass 22, count 0 2006.201.01:20:16.04#ibcon#read 4, iclass 22, count 0 2006.201.01:20:16.04#ibcon#about to read 5, iclass 22, count 0 2006.201.01:20:16.04#ibcon#read 5, iclass 22, count 0 2006.201.01:20:16.04#ibcon#about to read 6, iclass 22, count 0 2006.201.01:20:16.04#ibcon#read 6, iclass 22, count 0 2006.201.01:20:16.04#ibcon#end of sib2, iclass 22, count 0 2006.201.01:20:16.04#ibcon#*after write, iclass 22, count 0 2006.201.01:20:16.04#ibcon#*before return 0, iclass 22, count 0 2006.201.01:20:16.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.01:20:16.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.01:20:16.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.01:20:16.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.01:20:16.04$vck44/vb=1,4 2006.201.01:20:16.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.01:20:16.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.01:20:16.04#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:16.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.01:20:16.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.01:20:16.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.01:20:16.04#ibcon#enter wrdev, iclass 24, count 2 2006.201.01:20:16.04#ibcon#first serial, iclass 24, count 2 2006.201.01:20:16.04#ibcon#enter sib2, iclass 24, count 2 2006.201.01:20:16.04#ibcon#flushed, iclass 24, count 2 2006.201.01:20:16.04#ibcon#about to write, iclass 24, count 2 2006.201.01:20:16.04#ibcon#wrote, iclass 24, count 2 2006.201.01:20:16.04#ibcon#about to read 3, iclass 24, count 2 2006.201.01:20:16.06#ibcon#read 3, iclass 24, count 2 2006.201.01:20:16.06#ibcon#about to read 4, iclass 24, count 2 2006.201.01:20:16.06#ibcon#read 4, iclass 24, count 2 2006.201.01:20:16.06#ibcon#about to read 5, iclass 24, count 2 2006.201.01:20:16.06#ibcon#read 5, iclass 24, count 2 2006.201.01:20:16.06#ibcon#about to read 6, iclass 24, count 2 2006.201.01:20:16.06#ibcon#read 6, iclass 24, count 2 2006.201.01:20:16.06#ibcon#end of sib2, iclass 24, count 2 2006.201.01:20:16.06#ibcon#*mode == 0, iclass 24, count 2 2006.201.01:20:16.06#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.01:20:16.06#ibcon#[27=AT01-04\r\n] 2006.201.01:20:16.06#ibcon#*before write, iclass 24, count 2 2006.201.01:20:16.06#ibcon#enter sib2, iclass 24, count 2 2006.201.01:20:16.06#ibcon#flushed, iclass 24, count 2 2006.201.01:20:16.06#ibcon#about to write, iclass 24, count 2 2006.201.01:20:16.06#ibcon#wrote, iclass 24, count 2 2006.201.01:20:16.06#ibcon#about to read 3, iclass 24, count 2 2006.201.01:20:16.09#ibcon#read 3, iclass 24, count 2 2006.201.01:20:16.09#ibcon#about to read 4, iclass 24, count 2 2006.201.01:20:16.09#ibcon#read 4, iclass 24, count 2 2006.201.01:20:16.09#ibcon#about to read 5, iclass 24, count 2 2006.201.01:20:16.09#ibcon#read 5, iclass 24, count 2 2006.201.01:20:16.09#ibcon#about to read 6, iclass 24, count 2 2006.201.01:20:16.09#ibcon#read 6, iclass 24, count 2 2006.201.01:20:16.09#ibcon#end of sib2, iclass 24, count 2 2006.201.01:20:16.09#ibcon#*after write, iclass 24, count 2 2006.201.01:20:16.09#ibcon#*before return 0, iclass 24, count 2 2006.201.01:20:16.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.01:20:16.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.01:20:16.09#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.01:20:16.09#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:16.09#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.01:20:16.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.01:20:16.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.01:20:16.21#ibcon#enter wrdev, iclass 24, count 0 2006.201.01:20:16.21#ibcon#first serial, iclass 24, count 0 2006.201.01:20:16.21#ibcon#enter sib2, iclass 24, count 0 2006.201.01:20:16.21#ibcon#flushed, iclass 24, count 0 2006.201.01:20:16.21#ibcon#about to write, iclass 24, count 0 2006.201.01:20:16.21#ibcon#wrote, iclass 24, count 0 2006.201.01:20:16.21#ibcon#about to read 3, iclass 24, count 0 2006.201.01:20:16.23#ibcon#read 3, iclass 24, count 0 2006.201.01:20:16.23#ibcon#about to read 4, iclass 24, count 0 2006.201.01:20:16.23#ibcon#read 4, iclass 24, count 0 2006.201.01:20:16.23#ibcon#about to read 5, iclass 24, count 0 2006.201.01:20:16.23#ibcon#read 5, iclass 24, count 0 2006.201.01:20:16.23#ibcon#about to read 6, iclass 24, count 0 2006.201.01:20:16.23#ibcon#read 6, iclass 24, count 0 2006.201.01:20:16.23#ibcon#end of sib2, iclass 24, count 0 2006.201.01:20:16.23#ibcon#*mode == 0, iclass 24, count 0 2006.201.01:20:16.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.01:20:16.23#ibcon#[27=USB\r\n] 2006.201.01:20:16.23#ibcon#*before write, iclass 24, count 0 2006.201.01:20:16.23#ibcon#enter sib2, iclass 24, count 0 2006.201.01:20:16.23#ibcon#flushed, iclass 24, count 0 2006.201.01:20:16.23#ibcon#about to write, iclass 24, count 0 2006.201.01:20:16.23#ibcon#wrote, iclass 24, count 0 2006.201.01:20:16.23#ibcon#about to read 3, iclass 24, count 0 2006.201.01:20:16.26#ibcon#read 3, iclass 24, count 0 2006.201.01:20:16.26#ibcon#about to read 4, iclass 24, count 0 2006.201.01:20:16.26#ibcon#read 4, iclass 24, count 0 2006.201.01:20:16.26#ibcon#about to read 5, iclass 24, count 0 2006.201.01:20:16.26#ibcon#read 5, iclass 24, count 0 2006.201.01:20:16.26#ibcon#about to read 6, iclass 24, count 0 2006.201.01:20:16.26#ibcon#read 6, iclass 24, count 0 2006.201.01:20:16.26#ibcon#end of sib2, iclass 24, count 0 2006.201.01:20:16.26#ibcon#*after write, iclass 24, count 0 2006.201.01:20:16.26#ibcon#*before return 0, iclass 24, count 0 2006.201.01:20:16.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.01:20:16.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.01:20:16.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.01:20:16.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.01:20:16.26$vck44/vblo=2,634.99 2006.201.01:20:16.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.01:20:16.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:16.26#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:16.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:16.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:16.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:16.26#ibcon#enter wrdev, iclass 26, count 0 2006.201.01:20:16.26#ibcon#first serial, iclass 26, count 0 2006.201.01:20:16.26#ibcon#enter sib2, iclass 26, count 0 2006.201.01:20:16.26#ibcon#flushed, iclass 26, count 0 2006.201.01:20:16.26#ibcon#about to write, iclass 26, count 0 2006.201.01:20:16.26#ibcon#wrote, iclass 26, count 0 2006.201.01:20:16.26#ibcon#about to read 3, iclass 26, count 0 2006.201.01:20:16.28#ibcon#read 3, iclass 26, count 0 2006.201.01:20:16.28#ibcon#about to read 4, iclass 26, count 0 2006.201.01:20:16.28#ibcon#read 4, iclass 26, count 0 2006.201.01:20:16.28#ibcon#about to read 5, iclass 26, count 0 2006.201.01:20:16.28#ibcon#read 5, iclass 26, count 0 2006.201.01:20:16.28#ibcon#about to read 6, iclass 26, count 0 2006.201.01:20:16.28#ibcon#read 6, iclass 26, count 0 2006.201.01:20:16.28#ibcon#end of sib2, iclass 26, count 0 2006.201.01:20:16.28#ibcon#*mode == 0, iclass 26, count 0 2006.201.01:20:16.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.01:20:16.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.01:20:16.28#ibcon#*before write, iclass 26, count 0 2006.201.01:20:16.28#ibcon#enter sib2, iclass 26, count 0 2006.201.01:20:16.28#ibcon#flushed, iclass 26, count 0 2006.201.01:20:16.28#ibcon#about to write, iclass 26, count 0 2006.201.01:20:16.28#ibcon#wrote, iclass 26, count 0 2006.201.01:20:16.28#ibcon#about to read 3, iclass 26, count 0 2006.201.01:20:16.32#ibcon#read 3, iclass 26, count 0 2006.201.01:20:16.32#ibcon#about to read 4, iclass 26, count 0 2006.201.01:20:16.32#ibcon#read 4, iclass 26, count 0 2006.201.01:20:16.32#ibcon#about to read 5, iclass 26, count 0 2006.201.01:20:16.32#ibcon#read 5, iclass 26, count 0 2006.201.01:20:16.32#ibcon#about to read 6, iclass 26, count 0 2006.201.01:20:16.32#ibcon#read 6, iclass 26, count 0 2006.201.01:20:16.32#ibcon#end of sib2, iclass 26, count 0 2006.201.01:20:16.32#ibcon#*after write, iclass 26, count 0 2006.201.01:20:16.32#ibcon#*before return 0, iclass 26, count 0 2006.201.01:20:16.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:16.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.01:20:16.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.01:20:16.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.01:20:16.32$vck44/vb=2,5 2006.201.01:20:16.32#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.01:20:16.32#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.01:20:16.32#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:16.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:16.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:16.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:16.38#ibcon#enter wrdev, iclass 28, count 2 2006.201.01:20:16.38#ibcon#first serial, iclass 28, count 2 2006.201.01:20:16.38#ibcon#enter sib2, iclass 28, count 2 2006.201.01:20:16.38#ibcon#flushed, iclass 28, count 2 2006.201.01:20:16.38#ibcon#about to write, iclass 28, count 2 2006.201.01:20:16.38#ibcon#wrote, iclass 28, count 2 2006.201.01:20:16.38#ibcon#about to read 3, iclass 28, count 2 2006.201.01:20:16.40#ibcon#read 3, iclass 28, count 2 2006.201.01:20:16.40#ibcon#about to read 4, iclass 28, count 2 2006.201.01:20:16.40#ibcon#read 4, iclass 28, count 2 2006.201.01:20:16.40#ibcon#about to read 5, iclass 28, count 2 2006.201.01:20:16.40#ibcon#read 5, iclass 28, count 2 2006.201.01:20:16.40#ibcon#about to read 6, iclass 28, count 2 2006.201.01:20:16.40#ibcon#read 6, iclass 28, count 2 2006.201.01:20:16.40#ibcon#end of sib2, iclass 28, count 2 2006.201.01:20:16.40#ibcon#*mode == 0, iclass 28, count 2 2006.201.01:20:16.40#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.01:20:16.40#ibcon#[27=AT02-05\r\n] 2006.201.01:20:16.40#ibcon#*before write, iclass 28, count 2 2006.201.01:20:16.40#ibcon#enter sib2, iclass 28, count 2 2006.201.01:20:16.40#ibcon#flushed, iclass 28, count 2 2006.201.01:20:16.40#ibcon#about to write, iclass 28, count 2 2006.201.01:20:16.40#ibcon#wrote, iclass 28, count 2 2006.201.01:20:16.40#ibcon#about to read 3, iclass 28, count 2 2006.201.01:20:16.43#ibcon#read 3, iclass 28, count 2 2006.201.01:20:16.43#ibcon#about to read 4, iclass 28, count 2 2006.201.01:20:16.43#ibcon#read 4, iclass 28, count 2 2006.201.01:20:16.43#ibcon#about to read 5, iclass 28, count 2 2006.201.01:20:16.43#ibcon#read 5, iclass 28, count 2 2006.201.01:20:16.43#ibcon#about to read 6, iclass 28, count 2 2006.201.01:20:16.43#ibcon#read 6, iclass 28, count 2 2006.201.01:20:16.43#ibcon#end of sib2, iclass 28, count 2 2006.201.01:20:16.43#ibcon#*after write, iclass 28, count 2 2006.201.01:20:16.43#ibcon#*before return 0, iclass 28, count 2 2006.201.01:20:16.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:16.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:16.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.01:20:16.43#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:16.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:16.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:16.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:16.55#ibcon#enter wrdev, iclass 28, count 0 2006.201.01:20:16.55#ibcon#first serial, iclass 28, count 0 2006.201.01:20:16.55#ibcon#enter sib2, iclass 28, count 0 2006.201.01:20:16.55#ibcon#flushed, iclass 28, count 0 2006.201.01:20:16.55#ibcon#about to write, iclass 28, count 0 2006.201.01:20:16.55#ibcon#wrote, iclass 28, count 0 2006.201.01:20:16.55#ibcon#about to read 3, iclass 28, count 0 2006.201.01:20:16.57#ibcon#read 3, iclass 28, count 0 2006.201.01:20:16.57#ibcon#about to read 4, iclass 28, count 0 2006.201.01:20:16.57#ibcon#read 4, iclass 28, count 0 2006.201.01:20:16.57#ibcon#about to read 5, iclass 28, count 0 2006.201.01:20:16.57#ibcon#read 5, iclass 28, count 0 2006.201.01:20:16.57#ibcon#about to read 6, iclass 28, count 0 2006.201.01:20:16.57#ibcon#read 6, iclass 28, count 0 2006.201.01:20:16.57#ibcon#end of sib2, iclass 28, count 0 2006.201.01:20:16.57#ibcon#*mode == 0, iclass 28, count 0 2006.201.01:20:16.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.01:20:16.57#ibcon#[27=USB\r\n] 2006.201.01:20:16.57#ibcon#*before write, iclass 28, count 0 2006.201.01:20:16.57#ibcon#enter sib2, iclass 28, count 0 2006.201.01:20:16.57#ibcon#flushed, iclass 28, count 0 2006.201.01:20:16.57#ibcon#about to write, iclass 28, count 0 2006.201.01:20:16.57#ibcon#wrote, iclass 28, count 0 2006.201.01:20:16.57#ibcon#about to read 3, iclass 28, count 0 2006.201.01:20:16.60#ibcon#read 3, iclass 28, count 0 2006.201.01:20:16.60#ibcon#about to read 4, iclass 28, count 0 2006.201.01:20:16.60#ibcon#read 4, iclass 28, count 0 2006.201.01:20:16.60#ibcon#about to read 5, iclass 28, count 0 2006.201.01:20:16.60#ibcon#read 5, iclass 28, count 0 2006.201.01:20:16.60#ibcon#about to read 6, iclass 28, count 0 2006.201.01:20:16.60#ibcon#read 6, iclass 28, count 0 2006.201.01:20:16.60#ibcon#end of sib2, iclass 28, count 0 2006.201.01:20:16.60#ibcon#*after write, iclass 28, count 0 2006.201.01:20:16.60#ibcon#*before return 0, iclass 28, count 0 2006.201.01:20:16.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:16.60#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.01:20:16.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.01:20:16.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.01:20:16.60$vck44/vblo=3,649.99 2006.201.01:20:16.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.01:20:16.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:16.60#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:16.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:16.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:16.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:16.60#ibcon#enter wrdev, iclass 30, count 0 2006.201.01:20:16.60#ibcon#first serial, iclass 30, count 0 2006.201.01:20:16.60#ibcon#enter sib2, iclass 30, count 0 2006.201.01:20:16.60#ibcon#flushed, iclass 30, count 0 2006.201.01:20:16.60#ibcon#about to write, iclass 30, count 0 2006.201.01:20:16.60#ibcon#wrote, iclass 30, count 0 2006.201.01:20:16.60#ibcon#about to read 3, iclass 30, count 0 2006.201.01:20:16.62#ibcon#read 3, iclass 30, count 0 2006.201.01:20:16.62#ibcon#about to read 4, iclass 30, count 0 2006.201.01:20:16.62#ibcon#read 4, iclass 30, count 0 2006.201.01:20:16.62#ibcon#about to read 5, iclass 30, count 0 2006.201.01:20:16.62#ibcon#read 5, iclass 30, count 0 2006.201.01:20:16.62#ibcon#about to read 6, iclass 30, count 0 2006.201.01:20:16.62#ibcon#read 6, iclass 30, count 0 2006.201.01:20:16.62#ibcon#end of sib2, iclass 30, count 0 2006.201.01:20:16.62#ibcon#*mode == 0, iclass 30, count 0 2006.201.01:20:16.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.01:20:16.62#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.01:20:16.62#ibcon#*before write, iclass 30, count 0 2006.201.01:20:16.62#ibcon#enter sib2, iclass 30, count 0 2006.201.01:20:16.62#ibcon#flushed, iclass 30, count 0 2006.201.01:20:16.62#ibcon#about to write, iclass 30, count 0 2006.201.01:20:16.62#ibcon#wrote, iclass 30, count 0 2006.201.01:20:16.62#ibcon#about to read 3, iclass 30, count 0 2006.201.01:20:16.66#ibcon#read 3, iclass 30, count 0 2006.201.01:20:16.66#ibcon#about to read 4, iclass 30, count 0 2006.201.01:20:16.66#ibcon#read 4, iclass 30, count 0 2006.201.01:20:16.66#ibcon#about to read 5, iclass 30, count 0 2006.201.01:20:16.66#ibcon#read 5, iclass 30, count 0 2006.201.01:20:16.66#ibcon#about to read 6, iclass 30, count 0 2006.201.01:20:16.66#ibcon#read 6, iclass 30, count 0 2006.201.01:20:16.66#ibcon#end of sib2, iclass 30, count 0 2006.201.01:20:16.66#ibcon#*after write, iclass 30, count 0 2006.201.01:20:16.66#ibcon#*before return 0, iclass 30, count 0 2006.201.01:20:16.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:16.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.01:20:16.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.01:20:16.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.01:20:16.66$vck44/vb=3,4 2006.201.01:20:16.66#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.01:20:16.66#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.01:20:16.66#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:16.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:16.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:16.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:16.72#ibcon#enter wrdev, iclass 32, count 2 2006.201.01:20:16.72#ibcon#first serial, iclass 32, count 2 2006.201.01:20:16.72#ibcon#enter sib2, iclass 32, count 2 2006.201.01:20:16.72#ibcon#flushed, iclass 32, count 2 2006.201.01:20:16.72#ibcon#about to write, iclass 32, count 2 2006.201.01:20:16.72#ibcon#wrote, iclass 32, count 2 2006.201.01:20:16.72#ibcon#about to read 3, iclass 32, count 2 2006.201.01:20:16.74#ibcon#read 3, iclass 32, count 2 2006.201.01:20:16.74#ibcon#about to read 4, iclass 32, count 2 2006.201.01:20:16.74#ibcon#read 4, iclass 32, count 2 2006.201.01:20:16.74#ibcon#about to read 5, iclass 32, count 2 2006.201.01:20:16.74#ibcon#read 5, iclass 32, count 2 2006.201.01:20:16.74#ibcon#about to read 6, iclass 32, count 2 2006.201.01:20:16.74#ibcon#read 6, iclass 32, count 2 2006.201.01:20:16.74#ibcon#end of sib2, iclass 32, count 2 2006.201.01:20:16.74#ibcon#*mode == 0, iclass 32, count 2 2006.201.01:20:16.74#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.01:20:16.74#ibcon#[27=AT03-04\r\n] 2006.201.01:20:16.74#ibcon#*before write, iclass 32, count 2 2006.201.01:20:16.74#ibcon#enter sib2, iclass 32, count 2 2006.201.01:20:16.74#ibcon#flushed, iclass 32, count 2 2006.201.01:20:16.74#ibcon#about to write, iclass 32, count 2 2006.201.01:20:16.74#ibcon#wrote, iclass 32, count 2 2006.201.01:20:16.74#ibcon#about to read 3, iclass 32, count 2 2006.201.01:20:16.77#ibcon#read 3, iclass 32, count 2 2006.201.01:20:16.77#ibcon#about to read 4, iclass 32, count 2 2006.201.01:20:16.77#ibcon#read 4, iclass 32, count 2 2006.201.01:20:16.77#ibcon#about to read 5, iclass 32, count 2 2006.201.01:20:16.77#ibcon#read 5, iclass 32, count 2 2006.201.01:20:16.77#ibcon#about to read 6, iclass 32, count 2 2006.201.01:20:16.77#ibcon#read 6, iclass 32, count 2 2006.201.01:20:16.77#ibcon#end of sib2, iclass 32, count 2 2006.201.01:20:16.77#ibcon#*after write, iclass 32, count 2 2006.201.01:20:16.77#ibcon#*before return 0, iclass 32, count 2 2006.201.01:20:16.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:16.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:16.77#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.01:20:16.77#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:16.77#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:16.89#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:16.89#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:16.89#ibcon#enter wrdev, iclass 32, count 0 2006.201.01:20:16.89#ibcon#first serial, iclass 32, count 0 2006.201.01:20:16.89#ibcon#enter sib2, iclass 32, count 0 2006.201.01:20:16.89#ibcon#flushed, iclass 32, count 0 2006.201.01:20:16.89#ibcon#about to write, iclass 32, count 0 2006.201.01:20:16.89#ibcon#wrote, iclass 32, count 0 2006.201.01:20:16.89#ibcon#about to read 3, iclass 32, count 0 2006.201.01:20:16.91#ibcon#read 3, iclass 32, count 0 2006.201.01:20:16.91#ibcon#about to read 4, iclass 32, count 0 2006.201.01:20:16.91#ibcon#read 4, iclass 32, count 0 2006.201.01:20:16.91#ibcon#about to read 5, iclass 32, count 0 2006.201.01:20:16.91#ibcon#read 5, iclass 32, count 0 2006.201.01:20:16.91#ibcon#about to read 6, iclass 32, count 0 2006.201.01:20:16.91#ibcon#read 6, iclass 32, count 0 2006.201.01:20:16.91#ibcon#end of sib2, iclass 32, count 0 2006.201.01:20:16.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.01:20:16.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.01:20:16.91#ibcon#[27=USB\r\n] 2006.201.01:20:16.91#ibcon#*before write, iclass 32, count 0 2006.201.01:20:16.91#ibcon#enter sib2, iclass 32, count 0 2006.201.01:20:16.91#ibcon#flushed, iclass 32, count 0 2006.201.01:20:16.91#ibcon#about to write, iclass 32, count 0 2006.201.01:20:16.91#ibcon#wrote, iclass 32, count 0 2006.201.01:20:16.91#ibcon#about to read 3, iclass 32, count 0 2006.201.01:20:16.94#ibcon#read 3, iclass 32, count 0 2006.201.01:20:16.94#ibcon#about to read 4, iclass 32, count 0 2006.201.01:20:16.94#ibcon#read 4, iclass 32, count 0 2006.201.01:20:16.94#ibcon#about to read 5, iclass 32, count 0 2006.201.01:20:16.94#ibcon#read 5, iclass 32, count 0 2006.201.01:20:16.94#ibcon#about to read 6, iclass 32, count 0 2006.201.01:20:16.94#ibcon#read 6, iclass 32, count 0 2006.201.01:20:16.94#ibcon#end of sib2, iclass 32, count 0 2006.201.01:20:16.94#ibcon#*after write, iclass 32, count 0 2006.201.01:20:16.94#ibcon#*before return 0, iclass 32, count 0 2006.201.01:20:16.94#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:16.94#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.01:20:16.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.01:20:16.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.01:20:16.94$vck44/vblo=4,679.99 2006.201.01:20:16.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.01:20:16.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:16.94#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:16.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:16.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:16.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:16.94#ibcon#enter wrdev, iclass 34, count 0 2006.201.01:20:16.94#ibcon#first serial, iclass 34, count 0 2006.201.01:20:16.94#ibcon#enter sib2, iclass 34, count 0 2006.201.01:20:16.94#ibcon#flushed, iclass 34, count 0 2006.201.01:20:16.94#ibcon#about to write, iclass 34, count 0 2006.201.01:20:16.94#ibcon#wrote, iclass 34, count 0 2006.201.01:20:16.94#ibcon#about to read 3, iclass 34, count 0 2006.201.01:20:16.96#ibcon#read 3, iclass 34, count 0 2006.201.01:20:16.96#ibcon#about to read 4, iclass 34, count 0 2006.201.01:20:16.96#ibcon#read 4, iclass 34, count 0 2006.201.01:20:16.96#ibcon#about to read 5, iclass 34, count 0 2006.201.01:20:16.96#ibcon#read 5, iclass 34, count 0 2006.201.01:20:16.96#ibcon#about to read 6, iclass 34, count 0 2006.201.01:20:16.96#ibcon#read 6, iclass 34, count 0 2006.201.01:20:16.96#ibcon#end of sib2, iclass 34, count 0 2006.201.01:20:16.96#ibcon#*mode == 0, iclass 34, count 0 2006.201.01:20:16.96#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.01:20:16.96#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.01:20:16.96#ibcon#*before write, iclass 34, count 0 2006.201.01:20:16.96#ibcon#enter sib2, iclass 34, count 0 2006.201.01:20:16.96#ibcon#flushed, iclass 34, count 0 2006.201.01:20:16.96#ibcon#about to write, iclass 34, count 0 2006.201.01:20:16.96#ibcon#wrote, iclass 34, count 0 2006.201.01:20:16.96#ibcon#about to read 3, iclass 34, count 0 2006.201.01:20:17.00#ibcon#read 3, iclass 34, count 0 2006.201.01:20:17.00#ibcon#about to read 4, iclass 34, count 0 2006.201.01:20:17.00#ibcon#read 4, iclass 34, count 0 2006.201.01:20:17.00#ibcon#about to read 5, iclass 34, count 0 2006.201.01:20:17.00#ibcon#read 5, iclass 34, count 0 2006.201.01:20:17.00#ibcon#about to read 6, iclass 34, count 0 2006.201.01:20:17.00#ibcon#read 6, iclass 34, count 0 2006.201.01:20:17.00#ibcon#end of sib2, iclass 34, count 0 2006.201.01:20:17.00#ibcon#*after write, iclass 34, count 0 2006.201.01:20:17.00#ibcon#*before return 0, iclass 34, count 0 2006.201.01:20:17.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:17.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.01:20:17.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.01:20:17.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.01:20:17.00$vck44/vb=4,5 2006.201.01:20:17.00#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.01:20:17.00#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.01:20:17.00#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:17.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:17.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:17.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:17.06#ibcon#enter wrdev, iclass 36, count 2 2006.201.01:20:17.06#ibcon#first serial, iclass 36, count 2 2006.201.01:20:17.06#ibcon#enter sib2, iclass 36, count 2 2006.201.01:20:17.06#ibcon#flushed, iclass 36, count 2 2006.201.01:20:17.06#ibcon#about to write, iclass 36, count 2 2006.201.01:20:17.06#ibcon#wrote, iclass 36, count 2 2006.201.01:20:17.06#ibcon#about to read 3, iclass 36, count 2 2006.201.01:20:17.08#ibcon#read 3, iclass 36, count 2 2006.201.01:20:17.08#ibcon#about to read 4, iclass 36, count 2 2006.201.01:20:17.08#ibcon#read 4, iclass 36, count 2 2006.201.01:20:17.08#ibcon#about to read 5, iclass 36, count 2 2006.201.01:20:17.08#ibcon#read 5, iclass 36, count 2 2006.201.01:20:17.08#ibcon#about to read 6, iclass 36, count 2 2006.201.01:20:17.08#ibcon#read 6, iclass 36, count 2 2006.201.01:20:17.08#ibcon#end of sib2, iclass 36, count 2 2006.201.01:20:17.08#ibcon#*mode == 0, iclass 36, count 2 2006.201.01:20:17.08#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.01:20:17.08#ibcon#[27=AT04-05\r\n] 2006.201.01:20:17.08#ibcon#*before write, iclass 36, count 2 2006.201.01:20:17.08#ibcon#enter sib2, iclass 36, count 2 2006.201.01:20:17.08#ibcon#flushed, iclass 36, count 2 2006.201.01:20:17.08#ibcon#about to write, iclass 36, count 2 2006.201.01:20:17.08#ibcon#wrote, iclass 36, count 2 2006.201.01:20:17.08#ibcon#about to read 3, iclass 36, count 2 2006.201.01:20:17.11#ibcon#read 3, iclass 36, count 2 2006.201.01:20:17.11#ibcon#about to read 4, iclass 36, count 2 2006.201.01:20:17.11#ibcon#read 4, iclass 36, count 2 2006.201.01:20:17.11#ibcon#about to read 5, iclass 36, count 2 2006.201.01:20:17.11#ibcon#read 5, iclass 36, count 2 2006.201.01:20:17.11#ibcon#about to read 6, iclass 36, count 2 2006.201.01:20:17.11#ibcon#read 6, iclass 36, count 2 2006.201.01:20:17.11#ibcon#end of sib2, iclass 36, count 2 2006.201.01:20:17.11#ibcon#*after write, iclass 36, count 2 2006.201.01:20:17.11#ibcon#*before return 0, iclass 36, count 2 2006.201.01:20:17.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:17.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:17.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.01:20:17.11#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:17.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:17.23#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:17.23#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:17.23#ibcon#enter wrdev, iclass 36, count 0 2006.201.01:20:17.23#ibcon#first serial, iclass 36, count 0 2006.201.01:20:17.23#ibcon#enter sib2, iclass 36, count 0 2006.201.01:20:17.23#ibcon#flushed, iclass 36, count 0 2006.201.01:20:17.23#ibcon#about to write, iclass 36, count 0 2006.201.01:20:17.23#ibcon#wrote, iclass 36, count 0 2006.201.01:20:17.23#ibcon#about to read 3, iclass 36, count 0 2006.201.01:20:17.25#ibcon#read 3, iclass 36, count 0 2006.201.01:20:17.25#ibcon#about to read 4, iclass 36, count 0 2006.201.01:20:17.25#ibcon#read 4, iclass 36, count 0 2006.201.01:20:17.25#ibcon#about to read 5, iclass 36, count 0 2006.201.01:20:17.25#ibcon#read 5, iclass 36, count 0 2006.201.01:20:17.25#ibcon#about to read 6, iclass 36, count 0 2006.201.01:20:17.25#ibcon#read 6, iclass 36, count 0 2006.201.01:20:17.25#ibcon#end of sib2, iclass 36, count 0 2006.201.01:20:17.25#ibcon#*mode == 0, iclass 36, count 0 2006.201.01:20:17.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.01:20:17.25#ibcon#[27=USB\r\n] 2006.201.01:20:17.25#ibcon#*before write, iclass 36, count 0 2006.201.01:20:17.25#ibcon#enter sib2, iclass 36, count 0 2006.201.01:20:17.25#ibcon#flushed, iclass 36, count 0 2006.201.01:20:17.25#ibcon#about to write, iclass 36, count 0 2006.201.01:20:17.25#ibcon#wrote, iclass 36, count 0 2006.201.01:20:17.25#ibcon#about to read 3, iclass 36, count 0 2006.201.01:20:17.28#ibcon#read 3, iclass 36, count 0 2006.201.01:20:17.28#ibcon#about to read 4, iclass 36, count 0 2006.201.01:20:17.28#ibcon#read 4, iclass 36, count 0 2006.201.01:20:17.28#ibcon#about to read 5, iclass 36, count 0 2006.201.01:20:17.28#ibcon#read 5, iclass 36, count 0 2006.201.01:20:17.28#ibcon#about to read 6, iclass 36, count 0 2006.201.01:20:17.28#ibcon#read 6, iclass 36, count 0 2006.201.01:20:17.28#ibcon#end of sib2, iclass 36, count 0 2006.201.01:20:17.28#ibcon#*after write, iclass 36, count 0 2006.201.01:20:17.28#ibcon#*before return 0, iclass 36, count 0 2006.201.01:20:17.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:17.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.01:20:17.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.01:20:17.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.01:20:17.28$vck44/vblo=5,709.99 2006.201.01:20:17.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.01:20:17.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:17.28#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:17.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:17.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:17.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:17.28#ibcon#enter wrdev, iclass 38, count 0 2006.201.01:20:17.28#ibcon#first serial, iclass 38, count 0 2006.201.01:20:17.28#ibcon#enter sib2, iclass 38, count 0 2006.201.01:20:17.28#ibcon#flushed, iclass 38, count 0 2006.201.01:20:17.28#ibcon#about to write, iclass 38, count 0 2006.201.01:20:17.28#ibcon#wrote, iclass 38, count 0 2006.201.01:20:17.28#ibcon#about to read 3, iclass 38, count 0 2006.201.01:20:17.30#ibcon#read 3, iclass 38, count 0 2006.201.01:20:17.30#ibcon#about to read 4, iclass 38, count 0 2006.201.01:20:17.30#ibcon#read 4, iclass 38, count 0 2006.201.01:20:17.30#ibcon#about to read 5, iclass 38, count 0 2006.201.01:20:17.30#ibcon#read 5, iclass 38, count 0 2006.201.01:20:17.30#ibcon#about to read 6, iclass 38, count 0 2006.201.01:20:17.30#ibcon#read 6, iclass 38, count 0 2006.201.01:20:17.30#ibcon#end of sib2, iclass 38, count 0 2006.201.01:20:17.30#ibcon#*mode == 0, iclass 38, count 0 2006.201.01:20:17.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.01:20:17.30#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.01:20:17.30#ibcon#*before write, iclass 38, count 0 2006.201.01:20:17.30#ibcon#enter sib2, iclass 38, count 0 2006.201.01:20:17.30#ibcon#flushed, iclass 38, count 0 2006.201.01:20:17.30#ibcon#about to write, iclass 38, count 0 2006.201.01:20:17.30#ibcon#wrote, iclass 38, count 0 2006.201.01:20:17.30#ibcon#about to read 3, iclass 38, count 0 2006.201.01:20:17.34#ibcon#read 3, iclass 38, count 0 2006.201.01:20:17.34#ibcon#about to read 4, iclass 38, count 0 2006.201.01:20:17.34#ibcon#read 4, iclass 38, count 0 2006.201.01:20:17.34#ibcon#about to read 5, iclass 38, count 0 2006.201.01:20:17.34#ibcon#read 5, iclass 38, count 0 2006.201.01:20:17.34#ibcon#about to read 6, iclass 38, count 0 2006.201.01:20:17.34#ibcon#read 6, iclass 38, count 0 2006.201.01:20:17.34#ibcon#end of sib2, iclass 38, count 0 2006.201.01:20:17.34#ibcon#*after write, iclass 38, count 0 2006.201.01:20:17.34#ibcon#*before return 0, iclass 38, count 0 2006.201.01:20:17.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:17.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.01:20:17.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.01:20:17.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.01:20:17.34$vck44/vb=5,4 2006.201.01:20:17.34#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.01:20:17.34#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.01:20:17.34#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:17.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:17.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:17.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:17.40#ibcon#enter wrdev, iclass 40, count 2 2006.201.01:20:17.40#ibcon#first serial, iclass 40, count 2 2006.201.01:20:17.40#ibcon#enter sib2, iclass 40, count 2 2006.201.01:20:17.40#ibcon#flushed, iclass 40, count 2 2006.201.01:20:17.40#ibcon#about to write, iclass 40, count 2 2006.201.01:20:17.40#ibcon#wrote, iclass 40, count 2 2006.201.01:20:17.40#ibcon#about to read 3, iclass 40, count 2 2006.201.01:20:17.42#ibcon#read 3, iclass 40, count 2 2006.201.01:20:17.42#ibcon#about to read 4, iclass 40, count 2 2006.201.01:20:17.42#ibcon#read 4, iclass 40, count 2 2006.201.01:20:17.42#ibcon#about to read 5, iclass 40, count 2 2006.201.01:20:17.42#ibcon#read 5, iclass 40, count 2 2006.201.01:20:17.42#ibcon#about to read 6, iclass 40, count 2 2006.201.01:20:17.42#ibcon#read 6, iclass 40, count 2 2006.201.01:20:17.42#ibcon#end of sib2, iclass 40, count 2 2006.201.01:20:17.42#ibcon#*mode == 0, iclass 40, count 2 2006.201.01:20:17.42#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.01:20:17.42#ibcon#[27=AT05-04\r\n] 2006.201.01:20:17.42#ibcon#*before write, iclass 40, count 2 2006.201.01:20:17.42#ibcon#enter sib2, iclass 40, count 2 2006.201.01:20:17.42#ibcon#flushed, iclass 40, count 2 2006.201.01:20:17.42#ibcon#about to write, iclass 40, count 2 2006.201.01:20:17.42#ibcon#wrote, iclass 40, count 2 2006.201.01:20:17.42#ibcon#about to read 3, iclass 40, count 2 2006.201.01:20:17.45#ibcon#read 3, iclass 40, count 2 2006.201.01:20:17.45#ibcon#about to read 4, iclass 40, count 2 2006.201.01:20:17.45#ibcon#read 4, iclass 40, count 2 2006.201.01:20:17.45#ibcon#about to read 5, iclass 40, count 2 2006.201.01:20:17.45#ibcon#read 5, iclass 40, count 2 2006.201.01:20:17.45#ibcon#about to read 6, iclass 40, count 2 2006.201.01:20:17.45#ibcon#read 6, iclass 40, count 2 2006.201.01:20:17.45#ibcon#end of sib2, iclass 40, count 2 2006.201.01:20:17.45#ibcon#*after write, iclass 40, count 2 2006.201.01:20:17.45#ibcon#*before return 0, iclass 40, count 2 2006.201.01:20:17.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:17.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:17.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.01:20:17.45#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:17.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:17.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:17.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:17.57#ibcon#enter wrdev, iclass 40, count 0 2006.201.01:20:17.57#ibcon#first serial, iclass 40, count 0 2006.201.01:20:17.57#ibcon#enter sib2, iclass 40, count 0 2006.201.01:20:17.57#ibcon#flushed, iclass 40, count 0 2006.201.01:20:17.57#ibcon#about to write, iclass 40, count 0 2006.201.01:20:17.57#ibcon#wrote, iclass 40, count 0 2006.201.01:20:17.57#ibcon#about to read 3, iclass 40, count 0 2006.201.01:20:17.59#ibcon#read 3, iclass 40, count 0 2006.201.01:20:17.59#ibcon#about to read 4, iclass 40, count 0 2006.201.01:20:17.59#ibcon#read 4, iclass 40, count 0 2006.201.01:20:17.59#ibcon#about to read 5, iclass 40, count 0 2006.201.01:20:17.59#ibcon#read 5, iclass 40, count 0 2006.201.01:20:17.59#ibcon#about to read 6, iclass 40, count 0 2006.201.01:20:17.59#ibcon#read 6, iclass 40, count 0 2006.201.01:20:17.59#ibcon#end of sib2, iclass 40, count 0 2006.201.01:20:17.59#ibcon#*mode == 0, iclass 40, count 0 2006.201.01:20:17.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.01:20:17.59#ibcon#[27=USB\r\n] 2006.201.01:20:17.59#ibcon#*before write, iclass 40, count 0 2006.201.01:20:17.59#ibcon#enter sib2, iclass 40, count 0 2006.201.01:20:17.59#ibcon#flushed, iclass 40, count 0 2006.201.01:20:17.59#ibcon#about to write, iclass 40, count 0 2006.201.01:20:17.59#ibcon#wrote, iclass 40, count 0 2006.201.01:20:17.59#ibcon#about to read 3, iclass 40, count 0 2006.201.01:20:17.62#ibcon#read 3, iclass 40, count 0 2006.201.01:20:17.62#ibcon#about to read 4, iclass 40, count 0 2006.201.01:20:17.62#ibcon#read 4, iclass 40, count 0 2006.201.01:20:17.62#ibcon#about to read 5, iclass 40, count 0 2006.201.01:20:17.62#ibcon#read 5, iclass 40, count 0 2006.201.01:20:17.62#ibcon#about to read 6, iclass 40, count 0 2006.201.01:20:17.62#ibcon#read 6, iclass 40, count 0 2006.201.01:20:17.62#ibcon#end of sib2, iclass 40, count 0 2006.201.01:20:17.62#ibcon#*after write, iclass 40, count 0 2006.201.01:20:17.62#ibcon#*before return 0, iclass 40, count 0 2006.201.01:20:17.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:17.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.01:20:17.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.01:20:17.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.01:20:17.62$vck44/vblo=6,719.99 2006.201.01:20:17.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.01:20:17.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:17.62#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:17.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:17.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:17.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:17.62#ibcon#enter wrdev, iclass 4, count 0 2006.201.01:20:17.62#ibcon#first serial, iclass 4, count 0 2006.201.01:20:17.62#ibcon#enter sib2, iclass 4, count 0 2006.201.01:20:17.62#ibcon#flushed, iclass 4, count 0 2006.201.01:20:17.62#ibcon#about to write, iclass 4, count 0 2006.201.01:20:17.62#ibcon#wrote, iclass 4, count 0 2006.201.01:20:17.62#ibcon#about to read 3, iclass 4, count 0 2006.201.01:20:17.64#ibcon#read 3, iclass 4, count 0 2006.201.01:20:17.64#ibcon#about to read 4, iclass 4, count 0 2006.201.01:20:17.64#ibcon#read 4, iclass 4, count 0 2006.201.01:20:17.64#ibcon#about to read 5, iclass 4, count 0 2006.201.01:20:17.64#ibcon#read 5, iclass 4, count 0 2006.201.01:20:17.64#ibcon#about to read 6, iclass 4, count 0 2006.201.01:20:17.64#ibcon#read 6, iclass 4, count 0 2006.201.01:20:17.64#ibcon#end of sib2, iclass 4, count 0 2006.201.01:20:17.64#ibcon#*mode == 0, iclass 4, count 0 2006.201.01:20:17.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.01:20:17.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.01:20:17.64#ibcon#*before write, iclass 4, count 0 2006.201.01:20:17.64#ibcon#enter sib2, iclass 4, count 0 2006.201.01:20:17.64#ibcon#flushed, iclass 4, count 0 2006.201.01:20:17.64#ibcon#about to write, iclass 4, count 0 2006.201.01:20:17.64#ibcon#wrote, iclass 4, count 0 2006.201.01:20:17.64#ibcon#about to read 3, iclass 4, count 0 2006.201.01:20:17.68#ibcon#read 3, iclass 4, count 0 2006.201.01:20:17.68#ibcon#about to read 4, iclass 4, count 0 2006.201.01:20:17.68#ibcon#read 4, iclass 4, count 0 2006.201.01:20:17.68#ibcon#about to read 5, iclass 4, count 0 2006.201.01:20:17.68#ibcon#read 5, iclass 4, count 0 2006.201.01:20:17.68#ibcon#about to read 6, iclass 4, count 0 2006.201.01:20:17.68#ibcon#read 6, iclass 4, count 0 2006.201.01:20:17.68#ibcon#end of sib2, iclass 4, count 0 2006.201.01:20:17.68#ibcon#*after write, iclass 4, count 0 2006.201.01:20:17.68#ibcon#*before return 0, iclass 4, count 0 2006.201.01:20:17.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:17.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.01:20:17.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.01:20:17.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.01:20:17.68$vck44/vb=6,4 2006.201.01:20:17.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.01:20:17.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.01:20:17.68#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:17.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:17.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:17.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:17.74#ibcon#enter wrdev, iclass 6, count 2 2006.201.01:20:17.74#ibcon#first serial, iclass 6, count 2 2006.201.01:20:17.74#ibcon#enter sib2, iclass 6, count 2 2006.201.01:20:17.74#ibcon#flushed, iclass 6, count 2 2006.201.01:20:17.74#ibcon#about to write, iclass 6, count 2 2006.201.01:20:17.74#ibcon#wrote, iclass 6, count 2 2006.201.01:20:17.74#ibcon#about to read 3, iclass 6, count 2 2006.201.01:20:17.76#ibcon#read 3, iclass 6, count 2 2006.201.01:20:17.76#ibcon#about to read 4, iclass 6, count 2 2006.201.01:20:17.76#ibcon#read 4, iclass 6, count 2 2006.201.01:20:17.76#ibcon#about to read 5, iclass 6, count 2 2006.201.01:20:17.76#ibcon#read 5, iclass 6, count 2 2006.201.01:20:17.76#ibcon#about to read 6, iclass 6, count 2 2006.201.01:20:17.76#ibcon#read 6, iclass 6, count 2 2006.201.01:20:17.76#ibcon#end of sib2, iclass 6, count 2 2006.201.01:20:17.76#ibcon#*mode == 0, iclass 6, count 2 2006.201.01:20:17.76#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.01:20:17.76#ibcon#[27=AT06-04\r\n] 2006.201.01:20:17.76#ibcon#*before write, iclass 6, count 2 2006.201.01:20:17.76#ibcon#enter sib2, iclass 6, count 2 2006.201.01:20:17.76#ibcon#flushed, iclass 6, count 2 2006.201.01:20:17.76#ibcon#about to write, iclass 6, count 2 2006.201.01:20:17.76#ibcon#wrote, iclass 6, count 2 2006.201.01:20:17.76#ibcon#about to read 3, iclass 6, count 2 2006.201.01:20:17.79#ibcon#read 3, iclass 6, count 2 2006.201.01:20:17.79#ibcon#about to read 4, iclass 6, count 2 2006.201.01:20:17.79#ibcon#read 4, iclass 6, count 2 2006.201.01:20:17.79#ibcon#about to read 5, iclass 6, count 2 2006.201.01:20:17.79#ibcon#read 5, iclass 6, count 2 2006.201.01:20:17.79#ibcon#about to read 6, iclass 6, count 2 2006.201.01:20:17.79#ibcon#read 6, iclass 6, count 2 2006.201.01:20:17.79#ibcon#end of sib2, iclass 6, count 2 2006.201.01:20:17.79#ibcon#*after write, iclass 6, count 2 2006.201.01:20:17.79#ibcon#*before return 0, iclass 6, count 2 2006.201.01:20:17.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:17.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:17.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.01:20:17.79#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:17.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:17.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:17.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:17.91#ibcon#enter wrdev, iclass 6, count 0 2006.201.01:20:17.91#ibcon#first serial, iclass 6, count 0 2006.201.01:20:17.91#ibcon#enter sib2, iclass 6, count 0 2006.201.01:20:17.91#ibcon#flushed, iclass 6, count 0 2006.201.01:20:17.91#ibcon#about to write, iclass 6, count 0 2006.201.01:20:17.91#ibcon#wrote, iclass 6, count 0 2006.201.01:20:17.91#ibcon#about to read 3, iclass 6, count 0 2006.201.01:20:17.93#ibcon#read 3, iclass 6, count 0 2006.201.01:20:17.93#ibcon#about to read 4, iclass 6, count 0 2006.201.01:20:17.93#ibcon#read 4, iclass 6, count 0 2006.201.01:20:17.93#ibcon#about to read 5, iclass 6, count 0 2006.201.01:20:17.93#ibcon#read 5, iclass 6, count 0 2006.201.01:20:17.93#ibcon#about to read 6, iclass 6, count 0 2006.201.01:20:17.93#ibcon#read 6, iclass 6, count 0 2006.201.01:20:17.93#ibcon#end of sib2, iclass 6, count 0 2006.201.01:20:17.93#ibcon#*mode == 0, iclass 6, count 0 2006.201.01:20:17.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.01:20:17.93#ibcon#[27=USB\r\n] 2006.201.01:20:17.93#ibcon#*before write, iclass 6, count 0 2006.201.01:20:17.93#ibcon#enter sib2, iclass 6, count 0 2006.201.01:20:17.93#ibcon#flushed, iclass 6, count 0 2006.201.01:20:17.93#ibcon#about to write, iclass 6, count 0 2006.201.01:20:17.93#ibcon#wrote, iclass 6, count 0 2006.201.01:20:17.93#ibcon#about to read 3, iclass 6, count 0 2006.201.01:20:17.96#ibcon#read 3, iclass 6, count 0 2006.201.01:20:17.96#ibcon#about to read 4, iclass 6, count 0 2006.201.01:20:17.96#ibcon#read 4, iclass 6, count 0 2006.201.01:20:17.96#ibcon#about to read 5, iclass 6, count 0 2006.201.01:20:17.96#ibcon#read 5, iclass 6, count 0 2006.201.01:20:17.96#ibcon#about to read 6, iclass 6, count 0 2006.201.01:20:17.96#ibcon#read 6, iclass 6, count 0 2006.201.01:20:17.96#ibcon#end of sib2, iclass 6, count 0 2006.201.01:20:17.96#ibcon#*after write, iclass 6, count 0 2006.201.01:20:17.96#ibcon#*before return 0, iclass 6, count 0 2006.201.01:20:17.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:17.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.01:20:17.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.01:20:17.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.01:20:17.96$vck44/vblo=7,734.99 2006.201.01:20:17.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.01:20:17.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.01:20:17.96#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:17.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:17.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:17.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:17.96#ibcon#enter wrdev, iclass 10, count 0 2006.201.01:20:17.96#ibcon#first serial, iclass 10, count 0 2006.201.01:20:17.96#ibcon#enter sib2, iclass 10, count 0 2006.201.01:20:17.96#ibcon#flushed, iclass 10, count 0 2006.201.01:20:17.96#ibcon#about to write, iclass 10, count 0 2006.201.01:20:17.96#ibcon#wrote, iclass 10, count 0 2006.201.01:20:17.96#ibcon#about to read 3, iclass 10, count 0 2006.201.01:20:17.98#ibcon#read 3, iclass 10, count 0 2006.201.01:20:17.98#ibcon#about to read 4, iclass 10, count 0 2006.201.01:20:17.98#ibcon#read 4, iclass 10, count 0 2006.201.01:20:17.98#ibcon#about to read 5, iclass 10, count 0 2006.201.01:20:17.98#ibcon#read 5, iclass 10, count 0 2006.201.01:20:17.98#ibcon#about to read 6, iclass 10, count 0 2006.201.01:20:17.98#ibcon#read 6, iclass 10, count 0 2006.201.01:20:17.98#ibcon#end of sib2, iclass 10, count 0 2006.201.01:20:17.98#ibcon#*mode == 0, iclass 10, count 0 2006.201.01:20:17.98#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.01:20:17.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.01:20:17.98#ibcon#*before write, iclass 10, count 0 2006.201.01:20:17.98#ibcon#enter sib2, iclass 10, count 0 2006.201.01:20:17.98#ibcon#flushed, iclass 10, count 0 2006.201.01:20:17.98#ibcon#about to write, iclass 10, count 0 2006.201.01:20:17.98#ibcon#wrote, iclass 10, count 0 2006.201.01:20:17.98#ibcon#about to read 3, iclass 10, count 0 2006.201.01:20:18.02#ibcon#read 3, iclass 10, count 0 2006.201.01:20:18.02#ibcon#about to read 4, iclass 10, count 0 2006.201.01:20:18.02#ibcon#read 4, iclass 10, count 0 2006.201.01:20:18.02#ibcon#about to read 5, iclass 10, count 0 2006.201.01:20:18.02#ibcon#read 5, iclass 10, count 0 2006.201.01:20:18.02#ibcon#about to read 6, iclass 10, count 0 2006.201.01:20:18.02#ibcon#read 6, iclass 10, count 0 2006.201.01:20:18.02#ibcon#end of sib2, iclass 10, count 0 2006.201.01:20:18.02#ibcon#*after write, iclass 10, count 0 2006.201.01:20:18.02#ibcon#*before return 0, iclass 10, count 0 2006.201.01:20:18.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:18.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:18.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.01:20:18.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.01:20:18.02$vck44/vb=7,4 2006.201.01:20:18.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.01:20:18.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.01:20:18.02#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:18.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:18.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:18.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:18.08#ibcon#enter wrdev, iclass 12, count 2 2006.201.01:20:18.08#ibcon#first serial, iclass 12, count 2 2006.201.01:20:18.08#ibcon#enter sib2, iclass 12, count 2 2006.201.01:20:18.08#ibcon#flushed, iclass 12, count 2 2006.201.01:20:18.08#ibcon#about to write, iclass 12, count 2 2006.201.01:20:18.08#ibcon#wrote, iclass 12, count 2 2006.201.01:20:18.08#ibcon#about to read 3, iclass 12, count 2 2006.201.01:20:18.10#ibcon#read 3, iclass 12, count 2 2006.201.01:20:18.10#ibcon#about to read 4, iclass 12, count 2 2006.201.01:20:18.10#ibcon#read 4, iclass 12, count 2 2006.201.01:20:18.10#ibcon#about to read 5, iclass 12, count 2 2006.201.01:20:18.10#ibcon#read 5, iclass 12, count 2 2006.201.01:20:18.10#ibcon#about to read 6, iclass 12, count 2 2006.201.01:20:18.10#ibcon#read 6, iclass 12, count 2 2006.201.01:20:18.10#ibcon#end of sib2, iclass 12, count 2 2006.201.01:20:18.10#ibcon#*mode == 0, iclass 12, count 2 2006.201.01:20:18.10#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.01:20:18.10#ibcon#[27=AT07-04\r\n] 2006.201.01:20:18.10#ibcon#*before write, iclass 12, count 2 2006.201.01:20:18.10#ibcon#enter sib2, iclass 12, count 2 2006.201.01:20:18.10#ibcon#flushed, iclass 12, count 2 2006.201.01:20:18.10#ibcon#about to write, iclass 12, count 2 2006.201.01:20:18.10#ibcon#wrote, iclass 12, count 2 2006.201.01:20:18.10#ibcon#about to read 3, iclass 12, count 2 2006.201.01:20:18.13#ibcon#read 3, iclass 12, count 2 2006.201.01:20:18.13#ibcon#about to read 4, iclass 12, count 2 2006.201.01:20:18.13#ibcon#read 4, iclass 12, count 2 2006.201.01:20:18.13#ibcon#about to read 5, iclass 12, count 2 2006.201.01:20:18.13#ibcon#read 5, iclass 12, count 2 2006.201.01:20:18.13#ibcon#about to read 6, iclass 12, count 2 2006.201.01:20:18.13#ibcon#read 6, iclass 12, count 2 2006.201.01:20:18.13#ibcon#end of sib2, iclass 12, count 2 2006.201.01:20:18.13#ibcon#*after write, iclass 12, count 2 2006.201.01:20:18.13#ibcon#*before return 0, iclass 12, count 2 2006.201.01:20:18.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:18.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:18.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.01:20:18.13#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:18.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:18.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:18.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:18.25#ibcon#enter wrdev, iclass 12, count 0 2006.201.01:20:18.25#ibcon#first serial, iclass 12, count 0 2006.201.01:20:18.25#ibcon#enter sib2, iclass 12, count 0 2006.201.01:20:18.25#ibcon#flushed, iclass 12, count 0 2006.201.01:20:18.25#ibcon#about to write, iclass 12, count 0 2006.201.01:20:18.25#ibcon#wrote, iclass 12, count 0 2006.201.01:20:18.25#ibcon#about to read 3, iclass 12, count 0 2006.201.01:20:18.27#ibcon#read 3, iclass 12, count 0 2006.201.01:20:18.27#ibcon#about to read 4, iclass 12, count 0 2006.201.01:20:18.27#ibcon#read 4, iclass 12, count 0 2006.201.01:20:18.27#ibcon#about to read 5, iclass 12, count 0 2006.201.01:20:18.27#ibcon#read 5, iclass 12, count 0 2006.201.01:20:18.27#ibcon#about to read 6, iclass 12, count 0 2006.201.01:20:18.27#ibcon#read 6, iclass 12, count 0 2006.201.01:20:18.27#ibcon#end of sib2, iclass 12, count 0 2006.201.01:20:18.27#ibcon#*mode == 0, iclass 12, count 0 2006.201.01:20:18.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.01:20:18.27#ibcon#[27=USB\r\n] 2006.201.01:20:18.27#ibcon#*before write, iclass 12, count 0 2006.201.01:20:18.27#ibcon#enter sib2, iclass 12, count 0 2006.201.01:20:18.27#ibcon#flushed, iclass 12, count 0 2006.201.01:20:18.27#ibcon#about to write, iclass 12, count 0 2006.201.01:20:18.27#ibcon#wrote, iclass 12, count 0 2006.201.01:20:18.27#ibcon#about to read 3, iclass 12, count 0 2006.201.01:20:18.30#ibcon#read 3, iclass 12, count 0 2006.201.01:20:18.30#ibcon#about to read 4, iclass 12, count 0 2006.201.01:20:18.30#ibcon#read 4, iclass 12, count 0 2006.201.01:20:18.30#ibcon#about to read 5, iclass 12, count 0 2006.201.01:20:18.30#ibcon#read 5, iclass 12, count 0 2006.201.01:20:18.30#ibcon#about to read 6, iclass 12, count 0 2006.201.01:20:18.30#ibcon#read 6, iclass 12, count 0 2006.201.01:20:18.30#ibcon#end of sib2, iclass 12, count 0 2006.201.01:20:18.30#ibcon#*after write, iclass 12, count 0 2006.201.01:20:18.30#ibcon#*before return 0, iclass 12, count 0 2006.201.01:20:18.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:18.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.01:20:18.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.01:20:18.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.01:20:18.30$vck44/vblo=8,744.99 2006.201.01:20:18.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.01:20:18.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.01:20:18.30#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:18.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:18.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:18.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:18.30#ibcon#enter wrdev, iclass 14, count 0 2006.201.01:20:18.30#ibcon#first serial, iclass 14, count 0 2006.201.01:20:18.30#ibcon#enter sib2, iclass 14, count 0 2006.201.01:20:18.30#ibcon#flushed, iclass 14, count 0 2006.201.01:20:18.30#ibcon#about to write, iclass 14, count 0 2006.201.01:20:18.30#ibcon#wrote, iclass 14, count 0 2006.201.01:20:18.30#ibcon#about to read 3, iclass 14, count 0 2006.201.01:20:18.32#ibcon#read 3, iclass 14, count 0 2006.201.01:20:18.32#ibcon#about to read 4, iclass 14, count 0 2006.201.01:20:18.32#ibcon#read 4, iclass 14, count 0 2006.201.01:20:18.32#ibcon#about to read 5, iclass 14, count 0 2006.201.01:20:18.32#ibcon#read 5, iclass 14, count 0 2006.201.01:20:18.32#ibcon#about to read 6, iclass 14, count 0 2006.201.01:20:18.32#ibcon#read 6, iclass 14, count 0 2006.201.01:20:18.32#ibcon#end of sib2, iclass 14, count 0 2006.201.01:20:18.32#ibcon#*mode == 0, iclass 14, count 0 2006.201.01:20:18.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.01:20:18.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.01:20:18.32#ibcon#*before write, iclass 14, count 0 2006.201.01:20:18.32#ibcon#enter sib2, iclass 14, count 0 2006.201.01:20:18.32#ibcon#flushed, iclass 14, count 0 2006.201.01:20:18.32#ibcon#about to write, iclass 14, count 0 2006.201.01:20:18.32#ibcon#wrote, iclass 14, count 0 2006.201.01:20:18.32#ibcon#about to read 3, iclass 14, count 0 2006.201.01:20:18.36#ibcon#read 3, iclass 14, count 0 2006.201.01:20:18.36#ibcon#about to read 4, iclass 14, count 0 2006.201.01:20:18.36#ibcon#read 4, iclass 14, count 0 2006.201.01:20:18.36#ibcon#about to read 5, iclass 14, count 0 2006.201.01:20:18.36#ibcon#read 5, iclass 14, count 0 2006.201.01:20:18.36#ibcon#about to read 6, iclass 14, count 0 2006.201.01:20:18.36#ibcon#read 6, iclass 14, count 0 2006.201.01:20:18.36#ibcon#end of sib2, iclass 14, count 0 2006.201.01:20:18.36#ibcon#*after write, iclass 14, count 0 2006.201.01:20:18.36#ibcon#*before return 0, iclass 14, count 0 2006.201.01:20:18.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:18.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.01:20:18.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.01:20:18.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.01:20:18.36$vck44/vb=8,4 2006.201.01:20:18.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.01:20:18.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.01:20:18.36#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:18.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:18.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:18.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:18.42#ibcon#enter wrdev, iclass 16, count 2 2006.201.01:20:18.42#ibcon#first serial, iclass 16, count 2 2006.201.01:20:18.42#ibcon#enter sib2, iclass 16, count 2 2006.201.01:20:18.42#ibcon#flushed, iclass 16, count 2 2006.201.01:20:18.42#ibcon#about to write, iclass 16, count 2 2006.201.01:20:18.42#ibcon#wrote, iclass 16, count 2 2006.201.01:20:18.42#ibcon#about to read 3, iclass 16, count 2 2006.201.01:20:18.44#ibcon#read 3, iclass 16, count 2 2006.201.01:20:18.44#ibcon#about to read 4, iclass 16, count 2 2006.201.01:20:18.44#ibcon#read 4, iclass 16, count 2 2006.201.01:20:18.44#ibcon#about to read 5, iclass 16, count 2 2006.201.01:20:18.44#ibcon#read 5, iclass 16, count 2 2006.201.01:20:18.44#ibcon#about to read 6, iclass 16, count 2 2006.201.01:20:18.44#ibcon#read 6, iclass 16, count 2 2006.201.01:20:18.44#ibcon#end of sib2, iclass 16, count 2 2006.201.01:20:18.44#ibcon#*mode == 0, iclass 16, count 2 2006.201.01:20:18.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.01:20:18.44#ibcon#[27=AT08-04\r\n] 2006.201.01:20:18.44#ibcon#*before write, iclass 16, count 2 2006.201.01:20:18.44#ibcon#enter sib2, iclass 16, count 2 2006.201.01:20:18.44#ibcon#flushed, iclass 16, count 2 2006.201.01:20:18.44#ibcon#about to write, iclass 16, count 2 2006.201.01:20:18.44#ibcon#wrote, iclass 16, count 2 2006.201.01:20:18.44#ibcon#about to read 3, iclass 16, count 2 2006.201.01:20:18.47#ibcon#read 3, iclass 16, count 2 2006.201.01:20:18.47#ibcon#about to read 4, iclass 16, count 2 2006.201.01:20:18.47#ibcon#read 4, iclass 16, count 2 2006.201.01:20:18.47#ibcon#about to read 5, iclass 16, count 2 2006.201.01:20:18.47#ibcon#read 5, iclass 16, count 2 2006.201.01:20:18.47#ibcon#about to read 6, iclass 16, count 2 2006.201.01:20:18.47#ibcon#read 6, iclass 16, count 2 2006.201.01:20:18.47#ibcon#end of sib2, iclass 16, count 2 2006.201.01:20:18.47#ibcon#*after write, iclass 16, count 2 2006.201.01:20:18.47#ibcon#*before return 0, iclass 16, count 2 2006.201.01:20:18.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:18.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:18.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.01:20:18.47#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:18.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:18.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:18.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:18.59#ibcon#enter wrdev, iclass 16, count 0 2006.201.01:20:18.59#ibcon#first serial, iclass 16, count 0 2006.201.01:20:18.59#ibcon#enter sib2, iclass 16, count 0 2006.201.01:20:18.59#ibcon#flushed, iclass 16, count 0 2006.201.01:20:18.59#ibcon#about to write, iclass 16, count 0 2006.201.01:20:18.59#ibcon#wrote, iclass 16, count 0 2006.201.01:20:18.59#ibcon#about to read 3, iclass 16, count 0 2006.201.01:20:18.61#ibcon#read 3, iclass 16, count 0 2006.201.01:20:18.61#ibcon#about to read 4, iclass 16, count 0 2006.201.01:20:18.61#ibcon#read 4, iclass 16, count 0 2006.201.01:20:18.61#ibcon#about to read 5, iclass 16, count 0 2006.201.01:20:18.61#ibcon#read 5, iclass 16, count 0 2006.201.01:20:18.61#ibcon#about to read 6, iclass 16, count 0 2006.201.01:20:18.61#ibcon#read 6, iclass 16, count 0 2006.201.01:20:18.61#ibcon#end of sib2, iclass 16, count 0 2006.201.01:20:18.61#ibcon#*mode == 0, iclass 16, count 0 2006.201.01:20:18.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.01:20:18.61#ibcon#[27=USB\r\n] 2006.201.01:20:18.61#ibcon#*before write, iclass 16, count 0 2006.201.01:20:18.61#ibcon#enter sib2, iclass 16, count 0 2006.201.01:20:18.61#ibcon#flushed, iclass 16, count 0 2006.201.01:20:18.61#ibcon#about to write, iclass 16, count 0 2006.201.01:20:18.61#ibcon#wrote, iclass 16, count 0 2006.201.01:20:18.61#ibcon#about to read 3, iclass 16, count 0 2006.201.01:20:18.64#ibcon#read 3, iclass 16, count 0 2006.201.01:20:18.64#ibcon#about to read 4, iclass 16, count 0 2006.201.01:20:18.64#ibcon#read 4, iclass 16, count 0 2006.201.01:20:18.64#ibcon#about to read 5, iclass 16, count 0 2006.201.01:20:18.64#ibcon#read 5, iclass 16, count 0 2006.201.01:20:18.64#ibcon#about to read 6, iclass 16, count 0 2006.201.01:20:18.64#ibcon#read 6, iclass 16, count 0 2006.201.01:20:18.64#ibcon#end of sib2, iclass 16, count 0 2006.201.01:20:18.64#ibcon#*after write, iclass 16, count 0 2006.201.01:20:18.64#ibcon#*before return 0, iclass 16, count 0 2006.201.01:20:18.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:18.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.01:20:18.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.01:20:18.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.01:20:18.64$vck44/vabw=wide 2006.201.01:20:18.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.01:20:18.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:18.64#ibcon#ireg 8 cls_cnt 0 2006.201.01:20:18.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:18.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:18.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:18.64#ibcon#enter wrdev, iclass 18, count 0 2006.201.01:20:18.64#ibcon#first serial, iclass 18, count 0 2006.201.01:20:18.64#ibcon#enter sib2, iclass 18, count 0 2006.201.01:20:18.64#ibcon#flushed, iclass 18, count 0 2006.201.01:20:18.64#ibcon#about to write, iclass 18, count 0 2006.201.01:20:18.64#ibcon#wrote, iclass 18, count 0 2006.201.01:20:18.64#ibcon#about to read 3, iclass 18, count 0 2006.201.01:20:18.66#ibcon#read 3, iclass 18, count 0 2006.201.01:20:18.66#ibcon#about to read 4, iclass 18, count 0 2006.201.01:20:18.66#ibcon#read 4, iclass 18, count 0 2006.201.01:20:18.66#ibcon#about to read 5, iclass 18, count 0 2006.201.01:20:18.66#ibcon#read 5, iclass 18, count 0 2006.201.01:20:18.66#ibcon#about to read 6, iclass 18, count 0 2006.201.01:20:18.66#ibcon#read 6, iclass 18, count 0 2006.201.01:20:18.66#ibcon#end of sib2, iclass 18, count 0 2006.201.01:20:18.66#ibcon#*mode == 0, iclass 18, count 0 2006.201.01:20:18.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.01:20:18.66#ibcon#[25=BW32\r\n] 2006.201.01:20:18.66#ibcon#*before write, iclass 18, count 0 2006.201.01:20:18.66#ibcon#enter sib2, iclass 18, count 0 2006.201.01:20:18.66#ibcon#flushed, iclass 18, count 0 2006.201.01:20:18.66#ibcon#about to write, iclass 18, count 0 2006.201.01:20:18.66#ibcon#wrote, iclass 18, count 0 2006.201.01:20:18.66#ibcon#about to read 3, iclass 18, count 0 2006.201.01:20:18.69#ibcon#read 3, iclass 18, count 0 2006.201.01:20:18.69#ibcon#about to read 4, iclass 18, count 0 2006.201.01:20:18.69#ibcon#read 4, iclass 18, count 0 2006.201.01:20:18.69#ibcon#about to read 5, iclass 18, count 0 2006.201.01:20:18.69#ibcon#read 5, iclass 18, count 0 2006.201.01:20:18.69#ibcon#about to read 6, iclass 18, count 0 2006.201.01:20:18.69#ibcon#read 6, iclass 18, count 0 2006.201.01:20:18.69#ibcon#end of sib2, iclass 18, count 0 2006.201.01:20:18.69#ibcon#*after write, iclass 18, count 0 2006.201.01:20:18.69#ibcon#*before return 0, iclass 18, count 0 2006.201.01:20:18.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:18.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.01:20:18.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.01:20:18.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.01:20:18.69$vck44/vbbw=wide 2006.201.01:20:18.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.01:20:18.69#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.01:20:18.69#ibcon#ireg 8 cls_cnt 0 2006.201.01:20:18.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:18.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:18.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:18.76#ibcon#enter wrdev, iclass 20, count 0 2006.201.01:20:18.76#ibcon#first serial, iclass 20, count 0 2006.201.01:20:18.76#ibcon#enter sib2, iclass 20, count 0 2006.201.01:20:18.76#ibcon#flushed, iclass 20, count 0 2006.201.01:20:18.76#ibcon#about to write, iclass 20, count 0 2006.201.01:20:18.76#ibcon#wrote, iclass 20, count 0 2006.201.01:20:18.76#ibcon#about to read 3, iclass 20, count 0 2006.201.01:20:18.78#ibcon#read 3, iclass 20, count 0 2006.201.01:20:18.78#ibcon#about to read 4, iclass 20, count 0 2006.201.01:20:18.78#ibcon#read 4, iclass 20, count 0 2006.201.01:20:18.78#ibcon#about to read 5, iclass 20, count 0 2006.201.01:20:18.78#ibcon#read 5, iclass 20, count 0 2006.201.01:20:18.78#ibcon#about to read 6, iclass 20, count 0 2006.201.01:20:18.78#ibcon#read 6, iclass 20, count 0 2006.201.01:20:18.78#ibcon#end of sib2, iclass 20, count 0 2006.201.01:20:18.78#ibcon#*mode == 0, iclass 20, count 0 2006.201.01:20:18.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.01:20:18.78#ibcon#[27=BW32\r\n] 2006.201.01:20:18.78#ibcon#*before write, iclass 20, count 0 2006.201.01:20:18.78#ibcon#enter sib2, iclass 20, count 0 2006.201.01:20:18.78#ibcon#flushed, iclass 20, count 0 2006.201.01:20:18.78#ibcon#about to write, iclass 20, count 0 2006.201.01:20:18.78#ibcon#wrote, iclass 20, count 0 2006.201.01:20:18.78#ibcon#about to read 3, iclass 20, count 0 2006.201.01:20:18.81#ibcon#read 3, iclass 20, count 0 2006.201.01:20:18.81#ibcon#about to read 4, iclass 20, count 0 2006.201.01:20:18.81#ibcon#read 4, iclass 20, count 0 2006.201.01:20:18.81#ibcon#about to read 5, iclass 20, count 0 2006.201.01:20:18.81#ibcon#read 5, iclass 20, count 0 2006.201.01:20:18.81#ibcon#about to read 6, iclass 20, count 0 2006.201.01:20:18.81#ibcon#read 6, iclass 20, count 0 2006.201.01:20:18.81#ibcon#end of sib2, iclass 20, count 0 2006.201.01:20:18.81#ibcon#*after write, iclass 20, count 0 2006.201.01:20:18.81#ibcon#*before return 0, iclass 20, count 0 2006.201.01:20:18.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:18.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:18.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.01:20:18.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.01:20:18.81$setupk4/ifdk4 2006.201.01:20:18.81&ifdk4/lo= 2006.201.01:20:18.81&ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.01:20:18.81&ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.01:20:18.81&ifdk4/patch= 2006.201.01:20:18.81&ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.01:20:18.81&ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.01:20:18.81$ifdk4/lo= 2006.201.01:20:18.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.01:20:18.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.01:20:18.81$ifdk4/patch= 2006.201.01:20:18.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.01:20:18.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.01:20:18.81$setupk4/!*+20s 2006.201.01:20:18.81$exper_initi/proc_library 2006.201.01:20:18.81&proc_library/" jd0607 tsukub32 ts 2006.201.01:20:18.81&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.201.01:20:18.81&proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.201.01:20:18.81$proc_library/" jd0607 tsukub32 ts 2006.201.01:20:18.81$proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.201.01:20:18.81$proc_library/"< k4-2/m4 rack >< k4-2 recorder 1> 2006.201.01:20:18.81$exper_initi/sched_initi 2006.201.01:20:18.81&sched_initi/startcheck 2006.201.01:20:18.81$sched_initi/startcheck 2006.201.01:20:18.81&startcheck/sy=check_fsrun.pl & 2006.201.01:20:18.81&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.201.01:20:18.81$startcheck/sy=check_fsrun.pl & 2006.201.01:20:18.83$startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.201.01:20:20.49#abcon#<5=/03 2.2 5.1 23.34 931004.7\r\n> 2006.201.01:20:20.51#abcon#{5=INTERFACE CLEAR} 2006.201.01:20:20.59#abcon#[5=S1D000X0/0*\r\n] 2006.201.01:20:30.68#abcon#<5=/03 2.2 5.1 23.34 931004.7\r\n> 2006.201.01:20:30.70#abcon#{5=INTERFACE CLEAR} 2006.201.01:20:30.76#abcon#[5=S1D000X0/0*\r\n] 2006.201.01:20:31.14#trakl#Source acquired 2006.201.01:20:33.14#flagr#flagr/antenna,acquired 2006.201.01:20:33.25$setupk4/"tpicd 2006.201.01:20:33.25$setupk4/echo=off 2006.201.01:20:33.25$setupk4/xlog=off 2006.201.01:20:33.25:"ready=1 2006.201.01:20:33.25:setupk4=1 2006.201.01:20:33.25$setupk4/echo=on 2006.201.01:20:33.25$setupk4/pcalon 2006.201.01:20:33.25$pcalon/"no phase cal control is implemented here 2006.201.01:20:33.25$setupk4/"tpicd=stop 2006.201.01:20:33.25$setupk4/"rec=synch_on 2006.201.01:20:33.25$setupk4/"rec_mode=128 2006.201.01:20:33.25$setupk4/!* 2006.201.01:20:33.25$setupk4/recpk4 2006.201.01:20:33.25$recpk4/recpatch= 2006.201.01:20:33.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.01:20:33.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.01:20:33.25$setupk4/vck44 2006.201.01:20:33.25$vck44/valo=1,524.99 2006.201.01:20:33.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.01:20:33.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:33.25#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:33.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:33.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:33.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:33.25#ibcon#enter wrdev, iclass 16, count 0 2006.201.01:20:33.25#ibcon#first serial, iclass 16, count 0 2006.201.01:20:33.25#ibcon#enter sib2, iclass 16, count 0 2006.201.01:20:33.25#ibcon#flushed, iclass 16, count 0 2006.201.01:20:33.25#ibcon#about to write, iclass 16, count 0 2006.201.01:20:33.25#ibcon#wrote, iclass 16, count 0 2006.201.01:20:33.25#ibcon#about to read 3, iclass 16, count 0 2006.201.01:20:33.27#ibcon#read 3, iclass 16, count 0 2006.201.01:20:33.27#ibcon#about to read 4, iclass 16, count 0 2006.201.01:20:33.27#ibcon#read 4, iclass 16, count 0 2006.201.01:20:33.27#ibcon#about to read 5, iclass 16, count 0 2006.201.01:20:33.27#ibcon#read 5, iclass 16, count 0 2006.201.01:20:33.27#ibcon#about to read 6, iclass 16, count 0 2006.201.01:20:33.27#ibcon#read 6, iclass 16, count 0 2006.201.01:20:33.27#ibcon#end of sib2, iclass 16, count 0 2006.201.01:20:33.27#ibcon#*mode == 0, iclass 16, count 0 2006.201.01:20:33.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.01:20:33.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.01:20:33.27#ibcon#*before write, iclass 16, count 0 2006.201.01:20:33.27#ibcon#enter sib2, iclass 16, count 0 2006.201.01:20:33.27#ibcon#flushed, iclass 16, count 0 2006.201.01:20:33.27#ibcon#about to write, iclass 16, count 0 2006.201.01:20:33.27#ibcon#wrote, iclass 16, count 0 2006.201.01:20:33.27#ibcon#about to read 3, iclass 16, count 0 2006.201.01:20:33.31#ibcon#read 3, iclass 16, count 0 2006.201.01:20:33.31#ibcon#about to read 4, iclass 16, count 0 2006.201.01:20:33.31#ibcon#read 4, iclass 16, count 0 2006.201.01:20:33.31#ibcon#about to read 5, iclass 16, count 0 2006.201.01:20:33.31#ibcon#read 5, iclass 16, count 0 2006.201.01:20:33.31#ibcon#about to read 6, iclass 16, count 0 2006.201.01:20:33.31#ibcon#read 6, iclass 16, count 0 2006.201.01:20:33.31#ibcon#end of sib2, iclass 16, count 0 2006.201.01:20:33.31#ibcon#*after write, iclass 16, count 0 2006.201.01:20:33.31#ibcon#*before return 0, iclass 16, count 0 2006.201.01:20:33.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:33.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:33.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.01:20:33.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.01:20:33.31$vck44/va=1,8 2006.201.01:20:33.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.01:20:33.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.01:20:33.31#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:33.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:33.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:33.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:33.31#ibcon#enter wrdev, iclass 18, count 2 2006.201.01:20:33.31#ibcon#first serial, iclass 18, count 2 2006.201.01:20:33.31#ibcon#enter sib2, iclass 18, count 2 2006.201.01:20:33.31#ibcon#flushed, iclass 18, count 2 2006.201.01:20:33.31#ibcon#about to write, iclass 18, count 2 2006.201.01:20:33.31#ibcon#wrote, iclass 18, count 2 2006.201.01:20:33.31#ibcon#about to read 3, iclass 18, count 2 2006.201.01:20:33.33#ibcon#read 3, iclass 18, count 2 2006.201.01:20:33.33#ibcon#about to read 4, iclass 18, count 2 2006.201.01:20:33.33#ibcon#read 4, iclass 18, count 2 2006.201.01:20:33.33#ibcon#about to read 5, iclass 18, count 2 2006.201.01:20:33.33#ibcon#read 5, iclass 18, count 2 2006.201.01:20:33.33#ibcon#about to read 6, iclass 18, count 2 2006.201.01:20:33.33#ibcon#read 6, iclass 18, count 2 2006.201.01:20:33.33#ibcon#end of sib2, iclass 18, count 2 2006.201.01:20:33.33#ibcon#*mode == 0, iclass 18, count 2 2006.201.01:20:33.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.01:20:33.33#ibcon#[25=AT01-08\r\n] 2006.201.01:20:33.33#ibcon#*before write, iclass 18, count 2 2006.201.01:20:33.33#ibcon#enter sib2, iclass 18, count 2 2006.201.01:20:33.33#ibcon#flushed, iclass 18, count 2 2006.201.01:20:33.33#ibcon#about to write, iclass 18, count 2 2006.201.01:20:33.33#ibcon#wrote, iclass 18, count 2 2006.201.01:20:33.33#ibcon#about to read 3, iclass 18, count 2 2006.201.01:20:33.36#ibcon#read 3, iclass 18, count 2 2006.201.01:20:33.36#ibcon#about to read 4, iclass 18, count 2 2006.201.01:20:33.36#ibcon#read 4, iclass 18, count 2 2006.201.01:20:33.36#ibcon#about to read 5, iclass 18, count 2 2006.201.01:20:33.36#ibcon#read 5, iclass 18, count 2 2006.201.01:20:33.36#ibcon#about to read 6, iclass 18, count 2 2006.201.01:20:33.36#ibcon#read 6, iclass 18, count 2 2006.201.01:20:33.36#ibcon#end of sib2, iclass 18, count 2 2006.201.01:20:33.36#ibcon#*after write, iclass 18, count 2 2006.201.01:20:33.36#ibcon#*before return 0, iclass 18, count 2 2006.201.01:20:33.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:33.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:33.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.01:20:33.36#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:33.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:33.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:33.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:33.48#ibcon#enter wrdev, iclass 18, count 0 2006.201.01:20:33.48#ibcon#first serial, iclass 18, count 0 2006.201.01:20:33.48#ibcon#enter sib2, iclass 18, count 0 2006.201.01:20:33.48#ibcon#flushed, iclass 18, count 0 2006.201.01:20:33.48#ibcon#about to write, iclass 18, count 0 2006.201.01:20:33.48#ibcon#wrote, iclass 18, count 0 2006.201.01:20:33.48#ibcon#about to read 3, iclass 18, count 0 2006.201.01:20:33.50#ibcon#read 3, iclass 18, count 0 2006.201.01:20:33.50#ibcon#about to read 4, iclass 18, count 0 2006.201.01:20:33.50#ibcon#read 4, iclass 18, count 0 2006.201.01:20:33.50#ibcon#about to read 5, iclass 18, count 0 2006.201.01:20:33.50#ibcon#read 5, iclass 18, count 0 2006.201.01:20:33.50#ibcon#about to read 6, iclass 18, count 0 2006.201.01:20:33.50#ibcon#read 6, iclass 18, count 0 2006.201.01:20:33.50#ibcon#end of sib2, iclass 18, count 0 2006.201.01:20:33.50#ibcon#*mode == 0, iclass 18, count 0 2006.201.01:20:33.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.01:20:33.50#ibcon#[25=USB\r\n] 2006.201.01:20:33.50#ibcon#*before write, iclass 18, count 0 2006.201.01:20:33.50#ibcon#enter sib2, iclass 18, count 0 2006.201.01:20:33.50#ibcon#flushed, iclass 18, count 0 2006.201.01:20:33.50#ibcon#about to write, iclass 18, count 0 2006.201.01:20:33.50#ibcon#wrote, iclass 18, count 0 2006.201.01:20:33.50#ibcon#about to read 3, iclass 18, count 0 2006.201.01:20:33.53#ibcon#read 3, iclass 18, count 0 2006.201.01:20:33.53#ibcon#about to read 4, iclass 18, count 0 2006.201.01:20:33.53#ibcon#read 4, iclass 18, count 0 2006.201.01:20:33.53#ibcon#about to read 5, iclass 18, count 0 2006.201.01:20:33.53#ibcon#read 5, iclass 18, count 0 2006.201.01:20:33.53#ibcon#about to read 6, iclass 18, count 0 2006.201.01:20:33.53#ibcon#read 6, iclass 18, count 0 2006.201.01:20:33.53#ibcon#end of sib2, iclass 18, count 0 2006.201.01:20:33.53#ibcon#*after write, iclass 18, count 0 2006.201.01:20:33.53#ibcon#*before return 0, iclass 18, count 0 2006.201.01:20:33.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:33.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:33.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.01:20:33.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.01:20:33.53$vck44/valo=2,534.99 2006.201.01:20:33.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.01:20:33.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.01:20:33.53#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:33.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:33.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:33.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:33.53#ibcon#enter wrdev, iclass 20, count 0 2006.201.01:20:33.53#ibcon#first serial, iclass 20, count 0 2006.201.01:20:33.53#ibcon#enter sib2, iclass 20, count 0 2006.201.01:20:33.53#ibcon#flushed, iclass 20, count 0 2006.201.01:20:33.53#ibcon#about to write, iclass 20, count 0 2006.201.01:20:33.53#ibcon#wrote, iclass 20, count 0 2006.201.01:20:33.53#ibcon#about to read 3, iclass 20, count 0 2006.201.01:20:33.55#ibcon#read 3, iclass 20, count 0 2006.201.01:20:33.55#ibcon#about to read 4, iclass 20, count 0 2006.201.01:20:33.55#ibcon#read 4, iclass 20, count 0 2006.201.01:20:33.55#ibcon#about to read 5, iclass 20, count 0 2006.201.01:20:33.55#ibcon#read 5, iclass 20, count 0 2006.201.01:20:33.55#ibcon#about to read 6, iclass 20, count 0 2006.201.01:20:33.55#ibcon#read 6, iclass 20, count 0 2006.201.01:20:33.55#ibcon#end of sib2, iclass 20, count 0 2006.201.01:20:33.55#ibcon#*mode == 0, iclass 20, count 0 2006.201.01:20:33.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.01:20:33.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.01:20:33.55#ibcon#*before write, iclass 20, count 0 2006.201.01:20:33.55#ibcon#enter sib2, iclass 20, count 0 2006.201.01:20:33.55#ibcon#flushed, iclass 20, count 0 2006.201.01:20:33.55#ibcon#about to write, iclass 20, count 0 2006.201.01:20:33.55#ibcon#wrote, iclass 20, count 0 2006.201.01:20:33.55#ibcon#about to read 3, iclass 20, count 0 2006.201.01:20:33.59#ibcon#read 3, iclass 20, count 0 2006.201.01:20:33.59#ibcon#about to read 4, iclass 20, count 0 2006.201.01:20:33.59#ibcon#read 4, iclass 20, count 0 2006.201.01:20:33.59#ibcon#about to read 5, iclass 20, count 0 2006.201.01:20:33.59#ibcon#read 5, iclass 20, count 0 2006.201.01:20:33.59#ibcon#about to read 6, iclass 20, count 0 2006.201.01:20:33.59#ibcon#read 6, iclass 20, count 0 2006.201.01:20:33.59#ibcon#end of sib2, iclass 20, count 0 2006.201.01:20:33.59#ibcon#*after write, iclass 20, count 0 2006.201.01:20:33.59#ibcon#*before return 0, iclass 20, count 0 2006.201.01:20:33.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:33.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:33.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.01:20:33.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.01:20:33.59$vck44/va=2,7 2006.201.01:20:33.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.01:20:33.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.01:20:33.59#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:33.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:33.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:33.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:33.65#ibcon#enter wrdev, iclass 22, count 2 2006.201.01:20:33.65#ibcon#first serial, iclass 22, count 2 2006.201.01:20:33.65#ibcon#enter sib2, iclass 22, count 2 2006.201.01:20:33.65#ibcon#flushed, iclass 22, count 2 2006.201.01:20:33.65#ibcon#about to write, iclass 22, count 2 2006.201.01:20:33.65#ibcon#wrote, iclass 22, count 2 2006.201.01:20:33.65#ibcon#about to read 3, iclass 22, count 2 2006.201.01:20:33.67#ibcon#read 3, iclass 22, count 2 2006.201.01:20:33.67#ibcon#about to read 4, iclass 22, count 2 2006.201.01:20:33.67#ibcon#read 4, iclass 22, count 2 2006.201.01:20:33.67#ibcon#about to read 5, iclass 22, count 2 2006.201.01:20:33.67#ibcon#read 5, iclass 22, count 2 2006.201.01:20:33.67#ibcon#about to read 6, iclass 22, count 2 2006.201.01:20:33.67#ibcon#read 6, iclass 22, count 2 2006.201.01:20:33.67#ibcon#end of sib2, iclass 22, count 2 2006.201.01:20:33.67#ibcon#*mode == 0, iclass 22, count 2 2006.201.01:20:33.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.01:20:33.67#ibcon#[25=AT02-07\r\n] 2006.201.01:20:33.67#ibcon#*before write, iclass 22, count 2 2006.201.01:20:33.67#ibcon#enter sib2, iclass 22, count 2 2006.201.01:20:33.67#ibcon#flushed, iclass 22, count 2 2006.201.01:20:33.67#ibcon#about to write, iclass 22, count 2 2006.201.01:20:33.67#ibcon#wrote, iclass 22, count 2 2006.201.01:20:33.67#ibcon#about to read 3, iclass 22, count 2 2006.201.01:20:33.70#ibcon#read 3, iclass 22, count 2 2006.201.01:20:33.70#ibcon#about to read 4, iclass 22, count 2 2006.201.01:20:33.70#ibcon#read 4, iclass 22, count 2 2006.201.01:20:33.70#ibcon#about to read 5, iclass 22, count 2 2006.201.01:20:33.70#ibcon#read 5, iclass 22, count 2 2006.201.01:20:33.70#ibcon#about to read 6, iclass 22, count 2 2006.201.01:20:33.70#ibcon#read 6, iclass 22, count 2 2006.201.01:20:33.70#ibcon#end of sib2, iclass 22, count 2 2006.201.01:20:33.70#ibcon#*after write, iclass 22, count 2 2006.201.01:20:33.70#ibcon#*before return 0, iclass 22, count 2 2006.201.01:20:33.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:33.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:33.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.01:20:33.70#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:33.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:33.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:33.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:33.82#ibcon#enter wrdev, iclass 22, count 0 2006.201.01:20:33.82#ibcon#first serial, iclass 22, count 0 2006.201.01:20:33.82#ibcon#enter sib2, iclass 22, count 0 2006.201.01:20:33.82#ibcon#flushed, iclass 22, count 0 2006.201.01:20:33.82#ibcon#about to write, iclass 22, count 0 2006.201.01:20:33.82#ibcon#wrote, iclass 22, count 0 2006.201.01:20:33.82#ibcon#about to read 3, iclass 22, count 0 2006.201.01:20:33.84#ibcon#read 3, iclass 22, count 0 2006.201.01:20:33.84#ibcon#about to read 4, iclass 22, count 0 2006.201.01:20:33.84#ibcon#read 4, iclass 22, count 0 2006.201.01:20:33.84#ibcon#about to read 5, iclass 22, count 0 2006.201.01:20:33.84#ibcon#read 5, iclass 22, count 0 2006.201.01:20:33.84#ibcon#about to read 6, iclass 22, count 0 2006.201.01:20:33.84#ibcon#read 6, iclass 22, count 0 2006.201.01:20:33.84#ibcon#end of sib2, iclass 22, count 0 2006.201.01:20:33.84#ibcon#*mode == 0, iclass 22, count 0 2006.201.01:20:33.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.01:20:33.84#ibcon#[25=USB\r\n] 2006.201.01:20:33.84#ibcon#*before write, iclass 22, count 0 2006.201.01:20:33.84#ibcon#enter sib2, iclass 22, count 0 2006.201.01:20:33.84#ibcon#flushed, iclass 22, count 0 2006.201.01:20:33.84#ibcon#about to write, iclass 22, count 0 2006.201.01:20:33.84#ibcon#wrote, iclass 22, count 0 2006.201.01:20:33.84#ibcon#about to read 3, iclass 22, count 0 2006.201.01:20:33.87#ibcon#read 3, iclass 22, count 0 2006.201.01:20:33.87#ibcon#about to read 4, iclass 22, count 0 2006.201.01:20:33.87#ibcon#read 4, iclass 22, count 0 2006.201.01:20:33.87#ibcon#about to read 5, iclass 22, count 0 2006.201.01:20:33.87#ibcon#read 5, iclass 22, count 0 2006.201.01:20:33.87#ibcon#about to read 6, iclass 22, count 0 2006.201.01:20:33.87#ibcon#read 6, iclass 22, count 0 2006.201.01:20:33.87#ibcon#end of sib2, iclass 22, count 0 2006.201.01:20:33.87#ibcon#*after write, iclass 22, count 0 2006.201.01:20:33.87#ibcon#*before return 0, iclass 22, count 0 2006.201.01:20:33.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:33.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:33.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.01:20:33.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.01:20:33.87$vck44/valo=3,564.99 2006.201.01:20:33.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.01:20:33.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.01:20:33.87#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:33.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:33.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:33.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:33.87#ibcon#enter wrdev, iclass 24, count 0 2006.201.01:20:33.87#ibcon#first serial, iclass 24, count 0 2006.201.01:20:33.87#ibcon#enter sib2, iclass 24, count 0 2006.201.01:20:33.87#ibcon#flushed, iclass 24, count 0 2006.201.01:20:33.87#ibcon#about to write, iclass 24, count 0 2006.201.01:20:33.87#ibcon#wrote, iclass 24, count 0 2006.201.01:20:33.87#ibcon#about to read 3, iclass 24, count 0 2006.201.01:20:33.89#ibcon#read 3, iclass 24, count 0 2006.201.01:20:33.89#ibcon#about to read 4, iclass 24, count 0 2006.201.01:20:33.89#ibcon#read 4, iclass 24, count 0 2006.201.01:20:33.89#ibcon#about to read 5, iclass 24, count 0 2006.201.01:20:33.89#ibcon#read 5, iclass 24, count 0 2006.201.01:20:33.89#ibcon#about to read 6, iclass 24, count 0 2006.201.01:20:33.89#ibcon#read 6, iclass 24, count 0 2006.201.01:20:33.89#ibcon#end of sib2, iclass 24, count 0 2006.201.01:20:33.89#ibcon#*mode == 0, iclass 24, count 0 2006.201.01:20:33.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.01:20:33.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.01:20:33.89#ibcon#*before write, iclass 24, count 0 2006.201.01:20:33.89#ibcon#enter sib2, iclass 24, count 0 2006.201.01:20:33.89#ibcon#flushed, iclass 24, count 0 2006.201.01:20:33.89#ibcon#about to write, iclass 24, count 0 2006.201.01:20:33.89#ibcon#wrote, iclass 24, count 0 2006.201.01:20:33.89#ibcon#about to read 3, iclass 24, count 0 2006.201.01:20:33.93#ibcon#read 3, iclass 24, count 0 2006.201.01:20:33.93#ibcon#about to read 4, iclass 24, count 0 2006.201.01:20:33.93#ibcon#read 4, iclass 24, count 0 2006.201.01:20:33.93#ibcon#about to read 5, iclass 24, count 0 2006.201.01:20:33.93#ibcon#read 5, iclass 24, count 0 2006.201.01:20:33.93#ibcon#about to read 6, iclass 24, count 0 2006.201.01:20:33.93#ibcon#read 6, iclass 24, count 0 2006.201.01:20:33.93#ibcon#end of sib2, iclass 24, count 0 2006.201.01:20:33.93#ibcon#*after write, iclass 24, count 0 2006.201.01:20:33.93#ibcon#*before return 0, iclass 24, count 0 2006.201.01:20:33.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:33.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:33.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.01:20:33.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.01:20:33.93$vck44/va=3,8 2006.201.01:20:33.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.01:20:33.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.01:20:33.93#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:33.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:33.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:33.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:33.99#ibcon#enter wrdev, iclass 26, count 2 2006.201.01:20:33.99#ibcon#first serial, iclass 26, count 2 2006.201.01:20:33.99#ibcon#enter sib2, iclass 26, count 2 2006.201.01:20:33.99#ibcon#flushed, iclass 26, count 2 2006.201.01:20:33.99#ibcon#about to write, iclass 26, count 2 2006.201.01:20:33.99#ibcon#wrote, iclass 26, count 2 2006.201.01:20:33.99#ibcon#about to read 3, iclass 26, count 2 2006.201.01:20:34.01#ibcon#read 3, iclass 26, count 2 2006.201.01:20:34.01#ibcon#about to read 4, iclass 26, count 2 2006.201.01:20:34.01#ibcon#read 4, iclass 26, count 2 2006.201.01:20:34.01#ibcon#about to read 5, iclass 26, count 2 2006.201.01:20:34.01#ibcon#read 5, iclass 26, count 2 2006.201.01:20:34.01#ibcon#about to read 6, iclass 26, count 2 2006.201.01:20:34.01#ibcon#read 6, iclass 26, count 2 2006.201.01:20:34.01#ibcon#end of sib2, iclass 26, count 2 2006.201.01:20:34.01#ibcon#*mode == 0, iclass 26, count 2 2006.201.01:20:34.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.01:20:34.01#ibcon#[25=AT03-08\r\n] 2006.201.01:20:34.01#ibcon#*before write, iclass 26, count 2 2006.201.01:20:34.01#ibcon#enter sib2, iclass 26, count 2 2006.201.01:20:34.01#ibcon#flushed, iclass 26, count 2 2006.201.01:20:34.01#ibcon#about to write, iclass 26, count 2 2006.201.01:20:34.01#ibcon#wrote, iclass 26, count 2 2006.201.01:20:34.01#ibcon#about to read 3, iclass 26, count 2 2006.201.01:20:34.04#ibcon#read 3, iclass 26, count 2 2006.201.01:20:34.04#ibcon#about to read 4, iclass 26, count 2 2006.201.01:20:34.04#ibcon#read 4, iclass 26, count 2 2006.201.01:20:34.04#ibcon#about to read 5, iclass 26, count 2 2006.201.01:20:34.04#ibcon#read 5, iclass 26, count 2 2006.201.01:20:34.04#ibcon#about to read 6, iclass 26, count 2 2006.201.01:20:34.04#ibcon#read 6, iclass 26, count 2 2006.201.01:20:34.04#ibcon#end of sib2, iclass 26, count 2 2006.201.01:20:34.04#ibcon#*after write, iclass 26, count 2 2006.201.01:20:34.04#ibcon#*before return 0, iclass 26, count 2 2006.201.01:20:34.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:34.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:34.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.01:20:34.04#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:34.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:34.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:34.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:34.16#ibcon#enter wrdev, iclass 26, count 0 2006.201.01:20:34.16#ibcon#first serial, iclass 26, count 0 2006.201.01:20:34.16#ibcon#enter sib2, iclass 26, count 0 2006.201.01:20:34.16#ibcon#flushed, iclass 26, count 0 2006.201.01:20:34.16#ibcon#about to write, iclass 26, count 0 2006.201.01:20:34.16#ibcon#wrote, iclass 26, count 0 2006.201.01:20:34.16#ibcon#about to read 3, iclass 26, count 0 2006.201.01:20:34.18#ibcon#read 3, iclass 26, count 0 2006.201.01:20:34.18#ibcon#about to read 4, iclass 26, count 0 2006.201.01:20:34.18#ibcon#read 4, iclass 26, count 0 2006.201.01:20:34.18#ibcon#about to read 5, iclass 26, count 0 2006.201.01:20:34.18#ibcon#read 5, iclass 26, count 0 2006.201.01:20:34.18#ibcon#about to read 6, iclass 26, count 0 2006.201.01:20:34.18#ibcon#read 6, iclass 26, count 0 2006.201.01:20:34.18#ibcon#end of sib2, iclass 26, count 0 2006.201.01:20:34.18#ibcon#*mode == 0, iclass 26, count 0 2006.201.01:20:34.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.01:20:34.18#ibcon#[25=USB\r\n] 2006.201.01:20:34.18#ibcon#*before write, iclass 26, count 0 2006.201.01:20:34.18#ibcon#enter sib2, iclass 26, count 0 2006.201.01:20:34.18#ibcon#flushed, iclass 26, count 0 2006.201.01:20:34.18#ibcon#about to write, iclass 26, count 0 2006.201.01:20:34.18#ibcon#wrote, iclass 26, count 0 2006.201.01:20:34.18#ibcon#about to read 3, iclass 26, count 0 2006.201.01:20:34.21#ibcon#read 3, iclass 26, count 0 2006.201.01:20:34.21#ibcon#about to read 4, iclass 26, count 0 2006.201.01:20:34.21#ibcon#read 4, iclass 26, count 0 2006.201.01:20:34.21#ibcon#about to read 5, iclass 26, count 0 2006.201.01:20:34.21#ibcon#read 5, iclass 26, count 0 2006.201.01:20:34.21#ibcon#about to read 6, iclass 26, count 0 2006.201.01:20:34.21#ibcon#read 6, iclass 26, count 0 2006.201.01:20:34.21#ibcon#end of sib2, iclass 26, count 0 2006.201.01:20:34.21#ibcon#*after write, iclass 26, count 0 2006.201.01:20:34.21#ibcon#*before return 0, iclass 26, count 0 2006.201.01:20:34.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:34.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:34.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.01:20:34.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.01:20:34.21$vck44/valo=4,624.99 2006.201.01:20:34.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.01:20:34.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:34.21#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:34.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:34.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:34.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:34.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.01:20:34.21#ibcon#first serial, iclass 28, count 0 2006.201.01:20:34.21#ibcon#enter sib2, iclass 28, count 0 2006.201.01:20:34.21#ibcon#flushed, iclass 28, count 0 2006.201.01:20:34.21#ibcon#about to write, iclass 28, count 0 2006.201.01:20:34.21#ibcon#wrote, iclass 28, count 0 2006.201.01:20:34.21#ibcon#about to read 3, iclass 28, count 0 2006.201.01:20:34.23#ibcon#read 3, iclass 28, count 0 2006.201.01:20:34.23#ibcon#about to read 4, iclass 28, count 0 2006.201.01:20:34.23#ibcon#read 4, iclass 28, count 0 2006.201.01:20:34.23#ibcon#about to read 5, iclass 28, count 0 2006.201.01:20:34.23#ibcon#read 5, iclass 28, count 0 2006.201.01:20:34.23#ibcon#about to read 6, iclass 28, count 0 2006.201.01:20:34.23#ibcon#read 6, iclass 28, count 0 2006.201.01:20:34.23#ibcon#end of sib2, iclass 28, count 0 2006.201.01:20:34.23#ibcon#*mode == 0, iclass 28, count 0 2006.201.01:20:34.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.01:20:34.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.01:20:34.23#ibcon#*before write, iclass 28, count 0 2006.201.01:20:34.23#ibcon#enter sib2, iclass 28, count 0 2006.201.01:20:34.23#ibcon#flushed, iclass 28, count 0 2006.201.01:20:34.23#ibcon#about to write, iclass 28, count 0 2006.201.01:20:34.23#ibcon#wrote, iclass 28, count 0 2006.201.01:20:34.23#ibcon#about to read 3, iclass 28, count 0 2006.201.01:20:34.27#ibcon#read 3, iclass 28, count 0 2006.201.01:20:34.27#ibcon#about to read 4, iclass 28, count 0 2006.201.01:20:34.27#ibcon#read 4, iclass 28, count 0 2006.201.01:20:34.27#ibcon#about to read 5, iclass 28, count 0 2006.201.01:20:34.27#ibcon#read 5, iclass 28, count 0 2006.201.01:20:34.27#ibcon#about to read 6, iclass 28, count 0 2006.201.01:20:34.27#ibcon#read 6, iclass 28, count 0 2006.201.01:20:34.27#ibcon#end of sib2, iclass 28, count 0 2006.201.01:20:34.27#ibcon#*after write, iclass 28, count 0 2006.201.01:20:34.27#ibcon#*before return 0, iclass 28, count 0 2006.201.01:20:34.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:34.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:34.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.01:20:34.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.01:20:34.27$vck44/va=4,7 2006.201.01:20:34.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.01:20:34.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.01:20:34.27#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:34.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:34.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:34.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:34.33#ibcon#enter wrdev, iclass 30, count 2 2006.201.01:20:34.33#ibcon#first serial, iclass 30, count 2 2006.201.01:20:34.33#ibcon#enter sib2, iclass 30, count 2 2006.201.01:20:34.33#ibcon#flushed, iclass 30, count 2 2006.201.01:20:34.33#ibcon#about to write, iclass 30, count 2 2006.201.01:20:34.33#ibcon#wrote, iclass 30, count 2 2006.201.01:20:34.33#ibcon#about to read 3, iclass 30, count 2 2006.201.01:20:34.35#ibcon#read 3, iclass 30, count 2 2006.201.01:20:34.35#ibcon#about to read 4, iclass 30, count 2 2006.201.01:20:34.35#ibcon#read 4, iclass 30, count 2 2006.201.01:20:34.35#ibcon#about to read 5, iclass 30, count 2 2006.201.01:20:34.35#ibcon#read 5, iclass 30, count 2 2006.201.01:20:34.35#ibcon#about to read 6, iclass 30, count 2 2006.201.01:20:34.35#ibcon#read 6, iclass 30, count 2 2006.201.01:20:34.35#ibcon#end of sib2, iclass 30, count 2 2006.201.01:20:34.35#ibcon#*mode == 0, iclass 30, count 2 2006.201.01:20:34.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.01:20:34.35#ibcon#[25=AT04-07\r\n] 2006.201.01:20:34.35#ibcon#*before write, iclass 30, count 2 2006.201.01:20:34.35#ibcon#enter sib2, iclass 30, count 2 2006.201.01:20:34.35#ibcon#flushed, iclass 30, count 2 2006.201.01:20:34.35#ibcon#about to write, iclass 30, count 2 2006.201.01:20:34.35#ibcon#wrote, iclass 30, count 2 2006.201.01:20:34.35#ibcon#about to read 3, iclass 30, count 2 2006.201.01:20:34.38#ibcon#read 3, iclass 30, count 2 2006.201.01:20:34.38#ibcon#about to read 4, iclass 30, count 2 2006.201.01:20:34.38#ibcon#read 4, iclass 30, count 2 2006.201.01:20:34.38#ibcon#about to read 5, iclass 30, count 2 2006.201.01:20:34.38#ibcon#read 5, iclass 30, count 2 2006.201.01:20:34.38#ibcon#about to read 6, iclass 30, count 2 2006.201.01:20:34.38#ibcon#read 6, iclass 30, count 2 2006.201.01:20:34.38#ibcon#end of sib2, iclass 30, count 2 2006.201.01:20:34.38#ibcon#*after write, iclass 30, count 2 2006.201.01:20:34.38#ibcon#*before return 0, iclass 30, count 2 2006.201.01:20:34.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:34.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:34.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.01:20:34.38#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:34.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:34.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:34.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:34.50#ibcon#enter wrdev, iclass 30, count 0 2006.201.01:20:34.50#ibcon#first serial, iclass 30, count 0 2006.201.01:20:34.50#ibcon#enter sib2, iclass 30, count 0 2006.201.01:20:34.50#ibcon#flushed, iclass 30, count 0 2006.201.01:20:34.50#ibcon#about to write, iclass 30, count 0 2006.201.01:20:34.50#ibcon#wrote, iclass 30, count 0 2006.201.01:20:34.50#ibcon#about to read 3, iclass 30, count 0 2006.201.01:20:34.52#ibcon#read 3, iclass 30, count 0 2006.201.01:20:34.52#ibcon#about to read 4, iclass 30, count 0 2006.201.01:20:34.52#ibcon#read 4, iclass 30, count 0 2006.201.01:20:34.52#ibcon#about to read 5, iclass 30, count 0 2006.201.01:20:34.52#ibcon#read 5, iclass 30, count 0 2006.201.01:20:34.52#ibcon#about to read 6, iclass 30, count 0 2006.201.01:20:34.52#ibcon#read 6, iclass 30, count 0 2006.201.01:20:34.52#ibcon#end of sib2, iclass 30, count 0 2006.201.01:20:34.52#ibcon#*mode == 0, iclass 30, count 0 2006.201.01:20:34.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.01:20:34.52#ibcon#[25=USB\r\n] 2006.201.01:20:34.52#ibcon#*before write, iclass 30, count 0 2006.201.01:20:34.52#ibcon#enter sib2, iclass 30, count 0 2006.201.01:20:34.52#ibcon#flushed, iclass 30, count 0 2006.201.01:20:34.52#ibcon#about to write, iclass 30, count 0 2006.201.01:20:34.52#ibcon#wrote, iclass 30, count 0 2006.201.01:20:34.52#ibcon#about to read 3, iclass 30, count 0 2006.201.01:20:34.55#ibcon#read 3, iclass 30, count 0 2006.201.01:20:34.55#ibcon#about to read 4, iclass 30, count 0 2006.201.01:20:34.55#ibcon#read 4, iclass 30, count 0 2006.201.01:20:34.55#ibcon#about to read 5, iclass 30, count 0 2006.201.01:20:34.55#ibcon#read 5, iclass 30, count 0 2006.201.01:20:34.55#ibcon#about to read 6, iclass 30, count 0 2006.201.01:20:34.55#ibcon#read 6, iclass 30, count 0 2006.201.01:20:34.55#ibcon#end of sib2, iclass 30, count 0 2006.201.01:20:34.55#ibcon#*after write, iclass 30, count 0 2006.201.01:20:34.55#ibcon#*before return 0, iclass 30, count 0 2006.201.01:20:34.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:34.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:34.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.01:20:34.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.01:20:34.55$vck44/valo=5,734.99 2006.201.01:20:34.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.01:20:34.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:34.55#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:34.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:34.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:34.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:34.55#ibcon#enter wrdev, iclass 32, count 0 2006.201.01:20:34.55#ibcon#first serial, iclass 32, count 0 2006.201.01:20:34.55#ibcon#enter sib2, iclass 32, count 0 2006.201.01:20:34.55#ibcon#flushed, iclass 32, count 0 2006.201.01:20:34.55#ibcon#about to write, iclass 32, count 0 2006.201.01:20:34.55#ibcon#wrote, iclass 32, count 0 2006.201.01:20:34.55#ibcon#about to read 3, iclass 32, count 0 2006.201.01:20:34.57#ibcon#read 3, iclass 32, count 0 2006.201.01:20:34.57#ibcon#about to read 4, iclass 32, count 0 2006.201.01:20:34.57#ibcon#read 4, iclass 32, count 0 2006.201.01:20:34.57#ibcon#about to read 5, iclass 32, count 0 2006.201.01:20:34.57#ibcon#read 5, iclass 32, count 0 2006.201.01:20:34.57#ibcon#about to read 6, iclass 32, count 0 2006.201.01:20:34.57#ibcon#read 6, iclass 32, count 0 2006.201.01:20:34.57#ibcon#end of sib2, iclass 32, count 0 2006.201.01:20:34.57#ibcon#*mode == 0, iclass 32, count 0 2006.201.01:20:34.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.01:20:34.57#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.01:20:34.57#ibcon#*before write, iclass 32, count 0 2006.201.01:20:34.57#ibcon#enter sib2, iclass 32, count 0 2006.201.01:20:34.57#ibcon#flushed, iclass 32, count 0 2006.201.01:20:34.57#ibcon#about to write, iclass 32, count 0 2006.201.01:20:34.57#ibcon#wrote, iclass 32, count 0 2006.201.01:20:34.57#ibcon#about to read 3, iclass 32, count 0 2006.201.01:20:34.61#ibcon#read 3, iclass 32, count 0 2006.201.01:20:34.61#ibcon#about to read 4, iclass 32, count 0 2006.201.01:20:34.61#ibcon#read 4, iclass 32, count 0 2006.201.01:20:34.61#ibcon#about to read 5, iclass 32, count 0 2006.201.01:20:34.61#ibcon#read 5, iclass 32, count 0 2006.201.01:20:34.61#ibcon#about to read 6, iclass 32, count 0 2006.201.01:20:34.61#ibcon#read 6, iclass 32, count 0 2006.201.01:20:34.61#ibcon#end of sib2, iclass 32, count 0 2006.201.01:20:34.61#ibcon#*after write, iclass 32, count 0 2006.201.01:20:34.61#ibcon#*before return 0, iclass 32, count 0 2006.201.01:20:34.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:34.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:34.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.01:20:34.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.01:20:34.61$vck44/va=5,4 2006.201.01:20:34.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.01:20:34.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.01:20:34.61#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:34.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:34.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:34.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:34.67#ibcon#enter wrdev, iclass 34, count 2 2006.201.01:20:34.67#ibcon#first serial, iclass 34, count 2 2006.201.01:20:34.67#ibcon#enter sib2, iclass 34, count 2 2006.201.01:20:34.67#ibcon#flushed, iclass 34, count 2 2006.201.01:20:34.67#ibcon#about to write, iclass 34, count 2 2006.201.01:20:34.67#ibcon#wrote, iclass 34, count 2 2006.201.01:20:34.67#ibcon#about to read 3, iclass 34, count 2 2006.201.01:20:34.69#ibcon#read 3, iclass 34, count 2 2006.201.01:20:34.69#ibcon#about to read 4, iclass 34, count 2 2006.201.01:20:34.69#ibcon#read 4, iclass 34, count 2 2006.201.01:20:34.69#ibcon#about to read 5, iclass 34, count 2 2006.201.01:20:34.69#ibcon#read 5, iclass 34, count 2 2006.201.01:20:34.69#ibcon#about to read 6, iclass 34, count 2 2006.201.01:20:34.69#ibcon#read 6, iclass 34, count 2 2006.201.01:20:34.69#ibcon#end of sib2, iclass 34, count 2 2006.201.01:20:34.69#ibcon#*mode == 0, iclass 34, count 2 2006.201.01:20:34.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.01:20:34.69#ibcon#[25=AT05-04\r\n] 2006.201.01:20:34.69#ibcon#*before write, iclass 34, count 2 2006.201.01:20:34.69#ibcon#enter sib2, iclass 34, count 2 2006.201.01:20:34.69#ibcon#flushed, iclass 34, count 2 2006.201.01:20:34.69#ibcon#about to write, iclass 34, count 2 2006.201.01:20:34.69#ibcon#wrote, iclass 34, count 2 2006.201.01:20:34.69#ibcon#about to read 3, iclass 34, count 2 2006.201.01:20:34.72#ibcon#read 3, iclass 34, count 2 2006.201.01:20:34.72#ibcon#about to read 4, iclass 34, count 2 2006.201.01:20:34.72#ibcon#read 4, iclass 34, count 2 2006.201.01:20:34.72#ibcon#about to read 5, iclass 34, count 2 2006.201.01:20:34.72#ibcon#read 5, iclass 34, count 2 2006.201.01:20:34.72#ibcon#about to read 6, iclass 34, count 2 2006.201.01:20:34.72#ibcon#read 6, iclass 34, count 2 2006.201.01:20:34.72#ibcon#end of sib2, iclass 34, count 2 2006.201.01:20:34.72#ibcon#*after write, iclass 34, count 2 2006.201.01:20:34.72#ibcon#*before return 0, iclass 34, count 2 2006.201.01:20:34.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:34.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:34.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.01:20:34.72#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:34.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:34.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:34.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:34.84#ibcon#enter wrdev, iclass 34, count 0 2006.201.01:20:34.84#ibcon#first serial, iclass 34, count 0 2006.201.01:20:34.84#ibcon#enter sib2, iclass 34, count 0 2006.201.01:20:34.84#ibcon#flushed, iclass 34, count 0 2006.201.01:20:34.84#ibcon#about to write, iclass 34, count 0 2006.201.01:20:34.84#ibcon#wrote, iclass 34, count 0 2006.201.01:20:34.84#ibcon#about to read 3, iclass 34, count 0 2006.201.01:20:34.86#ibcon#read 3, iclass 34, count 0 2006.201.01:20:34.86#ibcon#about to read 4, iclass 34, count 0 2006.201.01:20:34.86#ibcon#read 4, iclass 34, count 0 2006.201.01:20:34.86#ibcon#about to read 5, iclass 34, count 0 2006.201.01:20:34.86#ibcon#read 5, iclass 34, count 0 2006.201.01:20:34.86#ibcon#about to read 6, iclass 34, count 0 2006.201.01:20:34.86#ibcon#read 6, iclass 34, count 0 2006.201.01:20:34.86#ibcon#end of sib2, iclass 34, count 0 2006.201.01:20:34.86#ibcon#*mode == 0, iclass 34, count 0 2006.201.01:20:34.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.01:20:34.86#ibcon#[25=USB\r\n] 2006.201.01:20:34.86#ibcon#*before write, iclass 34, count 0 2006.201.01:20:34.86#ibcon#enter sib2, iclass 34, count 0 2006.201.01:20:34.86#ibcon#flushed, iclass 34, count 0 2006.201.01:20:34.86#ibcon#about to write, iclass 34, count 0 2006.201.01:20:34.86#ibcon#wrote, iclass 34, count 0 2006.201.01:20:34.86#ibcon#about to read 3, iclass 34, count 0 2006.201.01:20:34.89#ibcon#read 3, iclass 34, count 0 2006.201.01:20:34.89#ibcon#about to read 4, iclass 34, count 0 2006.201.01:20:34.89#ibcon#read 4, iclass 34, count 0 2006.201.01:20:34.89#ibcon#about to read 5, iclass 34, count 0 2006.201.01:20:34.89#ibcon#read 5, iclass 34, count 0 2006.201.01:20:34.89#ibcon#about to read 6, iclass 34, count 0 2006.201.01:20:34.89#ibcon#read 6, iclass 34, count 0 2006.201.01:20:34.89#ibcon#end of sib2, iclass 34, count 0 2006.201.01:20:34.89#ibcon#*after write, iclass 34, count 0 2006.201.01:20:34.89#ibcon#*before return 0, iclass 34, count 0 2006.201.01:20:34.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:34.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:34.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.01:20:34.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.01:20:34.89$vck44/valo=6,814.99 2006.201.01:20:34.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.01:20:34.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:34.89#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:34.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:34.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:34.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:34.89#ibcon#enter wrdev, iclass 36, count 0 2006.201.01:20:34.89#ibcon#first serial, iclass 36, count 0 2006.201.01:20:34.89#ibcon#enter sib2, iclass 36, count 0 2006.201.01:20:34.89#ibcon#flushed, iclass 36, count 0 2006.201.01:20:34.89#ibcon#about to write, iclass 36, count 0 2006.201.01:20:34.89#ibcon#wrote, iclass 36, count 0 2006.201.01:20:34.89#ibcon#about to read 3, iclass 36, count 0 2006.201.01:20:34.91#ibcon#read 3, iclass 36, count 0 2006.201.01:20:34.91#ibcon#about to read 4, iclass 36, count 0 2006.201.01:20:34.91#ibcon#read 4, iclass 36, count 0 2006.201.01:20:34.91#ibcon#about to read 5, iclass 36, count 0 2006.201.01:20:34.91#ibcon#read 5, iclass 36, count 0 2006.201.01:20:34.91#ibcon#about to read 6, iclass 36, count 0 2006.201.01:20:34.91#ibcon#read 6, iclass 36, count 0 2006.201.01:20:34.91#ibcon#end of sib2, iclass 36, count 0 2006.201.01:20:34.91#ibcon#*mode == 0, iclass 36, count 0 2006.201.01:20:34.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.01:20:34.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.01:20:34.91#ibcon#*before write, iclass 36, count 0 2006.201.01:20:34.91#ibcon#enter sib2, iclass 36, count 0 2006.201.01:20:34.91#ibcon#flushed, iclass 36, count 0 2006.201.01:20:34.91#ibcon#about to write, iclass 36, count 0 2006.201.01:20:34.91#ibcon#wrote, iclass 36, count 0 2006.201.01:20:34.91#ibcon#about to read 3, iclass 36, count 0 2006.201.01:20:34.95#ibcon#read 3, iclass 36, count 0 2006.201.01:20:34.95#ibcon#about to read 4, iclass 36, count 0 2006.201.01:20:34.95#ibcon#read 4, iclass 36, count 0 2006.201.01:20:34.95#ibcon#about to read 5, iclass 36, count 0 2006.201.01:20:34.95#ibcon#read 5, iclass 36, count 0 2006.201.01:20:34.95#ibcon#about to read 6, iclass 36, count 0 2006.201.01:20:34.95#ibcon#read 6, iclass 36, count 0 2006.201.01:20:34.95#ibcon#end of sib2, iclass 36, count 0 2006.201.01:20:34.95#ibcon#*after write, iclass 36, count 0 2006.201.01:20:34.95#ibcon#*before return 0, iclass 36, count 0 2006.201.01:20:34.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:34.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:34.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.01:20:34.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.01:20:34.95$vck44/va=6,5 2006.201.01:20:34.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.01:20:34.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.01:20:34.95#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:34.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:35.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:35.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:35.01#ibcon#enter wrdev, iclass 38, count 2 2006.201.01:20:35.01#ibcon#first serial, iclass 38, count 2 2006.201.01:20:35.01#ibcon#enter sib2, iclass 38, count 2 2006.201.01:20:35.01#ibcon#flushed, iclass 38, count 2 2006.201.01:20:35.01#ibcon#about to write, iclass 38, count 2 2006.201.01:20:35.01#ibcon#wrote, iclass 38, count 2 2006.201.01:20:35.01#ibcon#about to read 3, iclass 38, count 2 2006.201.01:20:35.03#ibcon#read 3, iclass 38, count 2 2006.201.01:20:35.03#ibcon#about to read 4, iclass 38, count 2 2006.201.01:20:35.03#ibcon#read 4, iclass 38, count 2 2006.201.01:20:35.03#ibcon#about to read 5, iclass 38, count 2 2006.201.01:20:35.03#ibcon#read 5, iclass 38, count 2 2006.201.01:20:35.03#ibcon#about to read 6, iclass 38, count 2 2006.201.01:20:35.03#ibcon#read 6, iclass 38, count 2 2006.201.01:20:35.03#ibcon#end of sib2, iclass 38, count 2 2006.201.01:20:35.03#ibcon#*mode == 0, iclass 38, count 2 2006.201.01:20:35.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.01:20:35.03#ibcon#[25=AT06-05\r\n] 2006.201.01:20:35.03#ibcon#*before write, iclass 38, count 2 2006.201.01:20:35.03#ibcon#enter sib2, iclass 38, count 2 2006.201.01:20:35.03#ibcon#flushed, iclass 38, count 2 2006.201.01:20:35.03#ibcon#about to write, iclass 38, count 2 2006.201.01:20:35.03#ibcon#wrote, iclass 38, count 2 2006.201.01:20:35.03#ibcon#about to read 3, iclass 38, count 2 2006.201.01:20:35.06#ibcon#read 3, iclass 38, count 2 2006.201.01:20:35.06#ibcon#about to read 4, iclass 38, count 2 2006.201.01:20:35.06#ibcon#read 4, iclass 38, count 2 2006.201.01:20:35.06#ibcon#about to read 5, iclass 38, count 2 2006.201.01:20:35.06#ibcon#read 5, iclass 38, count 2 2006.201.01:20:35.06#ibcon#about to read 6, iclass 38, count 2 2006.201.01:20:35.06#ibcon#read 6, iclass 38, count 2 2006.201.01:20:35.06#ibcon#end of sib2, iclass 38, count 2 2006.201.01:20:35.06#ibcon#*after write, iclass 38, count 2 2006.201.01:20:35.06#ibcon#*before return 0, iclass 38, count 2 2006.201.01:20:35.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:35.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:35.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.01:20:35.06#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:35.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:35.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:35.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:35.18#ibcon#enter wrdev, iclass 38, count 0 2006.201.01:20:35.18#ibcon#first serial, iclass 38, count 0 2006.201.01:20:35.18#ibcon#enter sib2, iclass 38, count 0 2006.201.01:20:35.18#ibcon#flushed, iclass 38, count 0 2006.201.01:20:35.18#ibcon#about to write, iclass 38, count 0 2006.201.01:20:35.18#ibcon#wrote, iclass 38, count 0 2006.201.01:20:35.18#ibcon#about to read 3, iclass 38, count 0 2006.201.01:20:35.20#ibcon#read 3, iclass 38, count 0 2006.201.01:20:35.20#ibcon#about to read 4, iclass 38, count 0 2006.201.01:20:35.20#ibcon#read 4, iclass 38, count 0 2006.201.01:20:35.20#ibcon#about to read 5, iclass 38, count 0 2006.201.01:20:35.20#ibcon#read 5, iclass 38, count 0 2006.201.01:20:35.20#ibcon#about to read 6, iclass 38, count 0 2006.201.01:20:35.20#ibcon#read 6, iclass 38, count 0 2006.201.01:20:35.20#ibcon#end of sib2, iclass 38, count 0 2006.201.01:20:35.20#ibcon#*mode == 0, iclass 38, count 0 2006.201.01:20:35.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.01:20:35.20#ibcon#[25=USB\r\n] 2006.201.01:20:35.20#ibcon#*before write, iclass 38, count 0 2006.201.01:20:35.20#ibcon#enter sib2, iclass 38, count 0 2006.201.01:20:35.20#ibcon#flushed, iclass 38, count 0 2006.201.01:20:35.20#ibcon#about to write, iclass 38, count 0 2006.201.01:20:35.20#ibcon#wrote, iclass 38, count 0 2006.201.01:20:35.20#ibcon#about to read 3, iclass 38, count 0 2006.201.01:20:35.23#ibcon#read 3, iclass 38, count 0 2006.201.01:20:35.23#ibcon#about to read 4, iclass 38, count 0 2006.201.01:20:35.23#ibcon#read 4, iclass 38, count 0 2006.201.01:20:35.23#ibcon#about to read 5, iclass 38, count 0 2006.201.01:20:35.23#ibcon#read 5, iclass 38, count 0 2006.201.01:20:35.23#ibcon#about to read 6, iclass 38, count 0 2006.201.01:20:35.23#ibcon#read 6, iclass 38, count 0 2006.201.01:20:35.23#ibcon#end of sib2, iclass 38, count 0 2006.201.01:20:35.23#ibcon#*after write, iclass 38, count 0 2006.201.01:20:35.23#ibcon#*before return 0, iclass 38, count 0 2006.201.01:20:35.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:35.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:35.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.01:20:35.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.01:20:35.23$vck44/valo=7,864.99 2006.201.01:20:35.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.01:20:35.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:35.23#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:35.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:35.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:35.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:35.23#ibcon#enter wrdev, iclass 40, count 0 2006.201.01:20:35.23#ibcon#first serial, iclass 40, count 0 2006.201.01:20:35.23#ibcon#enter sib2, iclass 40, count 0 2006.201.01:20:35.23#ibcon#flushed, iclass 40, count 0 2006.201.01:20:35.23#ibcon#about to write, iclass 40, count 0 2006.201.01:20:35.23#ibcon#wrote, iclass 40, count 0 2006.201.01:20:35.23#ibcon#about to read 3, iclass 40, count 0 2006.201.01:20:35.25#ibcon#read 3, iclass 40, count 0 2006.201.01:20:35.25#ibcon#about to read 4, iclass 40, count 0 2006.201.01:20:35.25#ibcon#read 4, iclass 40, count 0 2006.201.01:20:35.25#ibcon#about to read 5, iclass 40, count 0 2006.201.01:20:35.25#ibcon#read 5, iclass 40, count 0 2006.201.01:20:35.25#ibcon#about to read 6, iclass 40, count 0 2006.201.01:20:35.25#ibcon#read 6, iclass 40, count 0 2006.201.01:20:35.25#ibcon#end of sib2, iclass 40, count 0 2006.201.01:20:35.25#ibcon#*mode == 0, iclass 40, count 0 2006.201.01:20:35.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.01:20:35.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.01:20:35.25#ibcon#*before write, iclass 40, count 0 2006.201.01:20:35.25#ibcon#enter sib2, iclass 40, count 0 2006.201.01:20:35.25#ibcon#flushed, iclass 40, count 0 2006.201.01:20:35.25#ibcon#about to write, iclass 40, count 0 2006.201.01:20:35.25#ibcon#wrote, iclass 40, count 0 2006.201.01:20:35.25#ibcon#about to read 3, iclass 40, count 0 2006.201.01:20:35.29#ibcon#read 3, iclass 40, count 0 2006.201.01:20:35.29#ibcon#about to read 4, iclass 40, count 0 2006.201.01:20:35.29#ibcon#read 4, iclass 40, count 0 2006.201.01:20:35.29#ibcon#about to read 5, iclass 40, count 0 2006.201.01:20:35.29#ibcon#read 5, iclass 40, count 0 2006.201.01:20:35.29#ibcon#about to read 6, iclass 40, count 0 2006.201.01:20:35.29#ibcon#read 6, iclass 40, count 0 2006.201.01:20:35.29#ibcon#end of sib2, iclass 40, count 0 2006.201.01:20:35.29#ibcon#*after write, iclass 40, count 0 2006.201.01:20:35.29#ibcon#*before return 0, iclass 40, count 0 2006.201.01:20:35.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:35.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:35.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.01:20:35.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.01:20:35.29$vck44/va=7,5 2006.201.01:20:35.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.01:20:35.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.01:20:35.29#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:35.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:35.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:35.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:35.35#ibcon#enter wrdev, iclass 4, count 2 2006.201.01:20:35.35#ibcon#first serial, iclass 4, count 2 2006.201.01:20:35.35#ibcon#enter sib2, iclass 4, count 2 2006.201.01:20:35.35#ibcon#flushed, iclass 4, count 2 2006.201.01:20:35.35#ibcon#about to write, iclass 4, count 2 2006.201.01:20:35.35#ibcon#wrote, iclass 4, count 2 2006.201.01:20:35.35#ibcon#about to read 3, iclass 4, count 2 2006.201.01:20:35.37#ibcon#read 3, iclass 4, count 2 2006.201.01:20:35.37#ibcon#about to read 4, iclass 4, count 2 2006.201.01:20:35.37#ibcon#read 4, iclass 4, count 2 2006.201.01:20:35.37#ibcon#about to read 5, iclass 4, count 2 2006.201.01:20:35.37#ibcon#read 5, iclass 4, count 2 2006.201.01:20:35.37#ibcon#about to read 6, iclass 4, count 2 2006.201.01:20:35.37#ibcon#read 6, iclass 4, count 2 2006.201.01:20:35.37#ibcon#end of sib2, iclass 4, count 2 2006.201.01:20:35.37#ibcon#*mode == 0, iclass 4, count 2 2006.201.01:20:35.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.01:20:35.37#ibcon#[25=AT07-05\r\n] 2006.201.01:20:35.37#ibcon#*before write, iclass 4, count 2 2006.201.01:20:35.37#ibcon#enter sib2, iclass 4, count 2 2006.201.01:20:35.37#ibcon#flushed, iclass 4, count 2 2006.201.01:20:35.37#ibcon#about to write, iclass 4, count 2 2006.201.01:20:35.37#ibcon#wrote, iclass 4, count 2 2006.201.01:20:35.37#ibcon#about to read 3, iclass 4, count 2 2006.201.01:20:35.40#ibcon#read 3, iclass 4, count 2 2006.201.01:20:35.40#ibcon#about to read 4, iclass 4, count 2 2006.201.01:20:35.40#ibcon#read 4, iclass 4, count 2 2006.201.01:20:35.40#ibcon#about to read 5, iclass 4, count 2 2006.201.01:20:35.40#ibcon#read 5, iclass 4, count 2 2006.201.01:20:35.40#ibcon#about to read 6, iclass 4, count 2 2006.201.01:20:35.40#ibcon#read 6, iclass 4, count 2 2006.201.01:20:35.40#ibcon#end of sib2, iclass 4, count 2 2006.201.01:20:35.40#ibcon#*after write, iclass 4, count 2 2006.201.01:20:35.40#ibcon#*before return 0, iclass 4, count 2 2006.201.01:20:35.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:35.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:35.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.01:20:35.40#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:35.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:35.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:35.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:35.52#ibcon#enter wrdev, iclass 4, count 0 2006.201.01:20:35.52#ibcon#first serial, iclass 4, count 0 2006.201.01:20:35.52#ibcon#enter sib2, iclass 4, count 0 2006.201.01:20:35.52#ibcon#flushed, iclass 4, count 0 2006.201.01:20:35.52#ibcon#about to write, iclass 4, count 0 2006.201.01:20:35.52#ibcon#wrote, iclass 4, count 0 2006.201.01:20:35.52#ibcon#about to read 3, iclass 4, count 0 2006.201.01:20:35.54#ibcon#read 3, iclass 4, count 0 2006.201.01:20:35.54#ibcon#about to read 4, iclass 4, count 0 2006.201.01:20:35.54#ibcon#read 4, iclass 4, count 0 2006.201.01:20:35.54#ibcon#about to read 5, iclass 4, count 0 2006.201.01:20:35.54#ibcon#read 5, iclass 4, count 0 2006.201.01:20:35.54#ibcon#about to read 6, iclass 4, count 0 2006.201.01:20:35.54#ibcon#read 6, iclass 4, count 0 2006.201.01:20:35.54#ibcon#end of sib2, iclass 4, count 0 2006.201.01:20:35.54#ibcon#*mode == 0, iclass 4, count 0 2006.201.01:20:35.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.01:20:35.54#ibcon#[25=USB\r\n] 2006.201.01:20:35.54#ibcon#*before write, iclass 4, count 0 2006.201.01:20:35.54#ibcon#enter sib2, iclass 4, count 0 2006.201.01:20:35.54#ibcon#flushed, iclass 4, count 0 2006.201.01:20:35.54#ibcon#about to write, iclass 4, count 0 2006.201.01:20:35.54#ibcon#wrote, iclass 4, count 0 2006.201.01:20:35.54#ibcon#about to read 3, iclass 4, count 0 2006.201.01:20:35.57#ibcon#read 3, iclass 4, count 0 2006.201.01:20:35.57#ibcon#about to read 4, iclass 4, count 0 2006.201.01:20:35.57#ibcon#read 4, iclass 4, count 0 2006.201.01:20:35.57#ibcon#about to read 5, iclass 4, count 0 2006.201.01:20:35.57#ibcon#read 5, iclass 4, count 0 2006.201.01:20:35.57#ibcon#about to read 6, iclass 4, count 0 2006.201.01:20:35.57#ibcon#read 6, iclass 4, count 0 2006.201.01:20:35.57#ibcon#end of sib2, iclass 4, count 0 2006.201.01:20:35.57#ibcon#*after write, iclass 4, count 0 2006.201.01:20:35.57#ibcon#*before return 0, iclass 4, count 0 2006.201.01:20:35.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:35.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:35.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.01:20:35.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.01:20:35.57$vck44/valo=8,884.99 2006.201.01:20:35.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.01:20:35.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:35.57#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:35.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:35.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:35.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:35.57#ibcon#enter wrdev, iclass 6, count 0 2006.201.01:20:35.57#ibcon#first serial, iclass 6, count 0 2006.201.01:20:35.57#ibcon#enter sib2, iclass 6, count 0 2006.201.01:20:35.57#ibcon#flushed, iclass 6, count 0 2006.201.01:20:35.57#ibcon#about to write, iclass 6, count 0 2006.201.01:20:35.57#ibcon#wrote, iclass 6, count 0 2006.201.01:20:35.57#ibcon#about to read 3, iclass 6, count 0 2006.201.01:20:35.59#ibcon#read 3, iclass 6, count 0 2006.201.01:20:35.59#ibcon#about to read 4, iclass 6, count 0 2006.201.01:20:35.59#ibcon#read 4, iclass 6, count 0 2006.201.01:20:35.59#ibcon#about to read 5, iclass 6, count 0 2006.201.01:20:35.59#ibcon#read 5, iclass 6, count 0 2006.201.01:20:35.59#ibcon#about to read 6, iclass 6, count 0 2006.201.01:20:35.59#ibcon#read 6, iclass 6, count 0 2006.201.01:20:35.59#ibcon#end of sib2, iclass 6, count 0 2006.201.01:20:35.59#ibcon#*mode == 0, iclass 6, count 0 2006.201.01:20:35.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.01:20:35.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.01:20:35.59#ibcon#*before write, iclass 6, count 0 2006.201.01:20:35.59#ibcon#enter sib2, iclass 6, count 0 2006.201.01:20:35.59#ibcon#flushed, iclass 6, count 0 2006.201.01:20:35.59#ibcon#about to write, iclass 6, count 0 2006.201.01:20:35.59#ibcon#wrote, iclass 6, count 0 2006.201.01:20:35.59#ibcon#about to read 3, iclass 6, count 0 2006.201.01:20:35.63#ibcon#read 3, iclass 6, count 0 2006.201.01:20:35.63#ibcon#about to read 4, iclass 6, count 0 2006.201.01:20:35.63#ibcon#read 4, iclass 6, count 0 2006.201.01:20:35.63#ibcon#about to read 5, iclass 6, count 0 2006.201.01:20:35.63#ibcon#read 5, iclass 6, count 0 2006.201.01:20:35.63#ibcon#about to read 6, iclass 6, count 0 2006.201.01:20:35.63#ibcon#read 6, iclass 6, count 0 2006.201.01:20:35.63#ibcon#end of sib2, iclass 6, count 0 2006.201.01:20:35.63#ibcon#*after write, iclass 6, count 0 2006.201.01:20:35.63#ibcon#*before return 0, iclass 6, count 0 2006.201.01:20:35.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:35.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:35.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.01:20:35.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.01:20:35.63$vck44/va=8,4 2006.201.01:20:35.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.01:20:35.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.01:20:35.63#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:35.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.01:20:35.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.01:20:35.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.01:20:35.69#ibcon#enter wrdev, iclass 10, count 2 2006.201.01:20:35.69#ibcon#first serial, iclass 10, count 2 2006.201.01:20:35.69#ibcon#enter sib2, iclass 10, count 2 2006.201.01:20:35.69#ibcon#flushed, iclass 10, count 2 2006.201.01:20:35.69#ibcon#about to write, iclass 10, count 2 2006.201.01:20:35.69#ibcon#wrote, iclass 10, count 2 2006.201.01:20:35.69#ibcon#about to read 3, iclass 10, count 2 2006.201.01:20:35.71#ibcon#read 3, iclass 10, count 2 2006.201.01:20:35.71#ibcon#about to read 4, iclass 10, count 2 2006.201.01:20:35.71#ibcon#read 4, iclass 10, count 2 2006.201.01:20:35.71#ibcon#about to read 5, iclass 10, count 2 2006.201.01:20:35.71#ibcon#read 5, iclass 10, count 2 2006.201.01:20:35.71#ibcon#about to read 6, iclass 10, count 2 2006.201.01:20:35.71#ibcon#read 6, iclass 10, count 2 2006.201.01:20:35.71#ibcon#end of sib2, iclass 10, count 2 2006.201.01:20:35.71#ibcon#*mode == 0, iclass 10, count 2 2006.201.01:20:35.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.01:20:35.71#ibcon#[25=AT08-04\r\n] 2006.201.01:20:35.71#ibcon#*before write, iclass 10, count 2 2006.201.01:20:35.71#ibcon#enter sib2, iclass 10, count 2 2006.201.01:20:35.71#ibcon#flushed, iclass 10, count 2 2006.201.01:20:35.71#ibcon#about to write, iclass 10, count 2 2006.201.01:20:35.71#ibcon#wrote, iclass 10, count 2 2006.201.01:20:35.71#ibcon#about to read 3, iclass 10, count 2 2006.201.01:20:35.74#ibcon#read 3, iclass 10, count 2 2006.201.01:20:35.74#ibcon#about to read 4, iclass 10, count 2 2006.201.01:20:35.74#ibcon#read 4, iclass 10, count 2 2006.201.01:20:35.74#ibcon#about to read 5, iclass 10, count 2 2006.201.01:20:35.74#ibcon#read 5, iclass 10, count 2 2006.201.01:20:35.74#ibcon#about to read 6, iclass 10, count 2 2006.201.01:20:35.74#ibcon#read 6, iclass 10, count 2 2006.201.01:20:35.74#ibcon#end of sib2, iclass 10, count 2 2006.201.01:20:35.74#ibcon#*after write, iclass 10, count 2 2006.201.01:20:35.74#ibcon#*before return 0, iclass 10, count 2 2006.201.01:20:35.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.01:20:35.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.01:20:35.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.01:20:35.74#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:35.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.01:20:35.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.01:20:35.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.01:20:35.86#ibcon#enter wrdev, iclass 10, count 0 2006.201.01:20:35.86#ibcon#first serial, iclass 10, count 0 2006.201.01:20:35.86#ibcon#enter sib2, iclass 10, count 0 2006.201.01:20:35.86#ibcon#flushed, iclass 10, count 0 2006.201.01:20:35.86#ibcon#about to write, iclass 10, count 0 2006.201.01:20:35.86#ibcon#wrote, iclass 10, count 0 2006.201.01:20:35.86#ibcon#about to read 3, iclass 10, count 0 2006.201.01:20:35.88#ibcon#read 3, iclass 10, count 0 2006.201.01:20:35.88#ibcon#about to read 4, iclass 10, count 0 2006.201.01:20:35.88#ibcon#read 4, iclass 10, count 0 2006.201.01:20:35.88#ibcon#about to read 5, iclass 10, count 0 2006.201.01:20:35.88#ibcon#read 5, iclass 10, count 0 2006.201.01:20:35.88#ibcon#about to read 6, iclass 10, count 0 2006.201.01:20:35.88#ibcon#read 6, iclass 10, count 0 2006.201.01:20:35.88#ibcon#end of sib2, iclass 10, count 0 2006.201.01:20:35.88#ibcon#*mode == 0, iclass 10, count 0 2006.201.01:20:35.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.01:20:35.88#ibcon#[25=USB\r\n] 2006.201.01:20:35.88#ibcon#*before write, iclass 10, count 0 2006.201.01:20:35.88#ibcon#enter sib2, iclass 10, count 0 2006.201.01:20:35.88#ibcon#flushed, iclass 10, count 0 2006.201.01:20:35.88#ibcon#about to write, iclass 10, count 0 2006.201.01:20:35.88#ibcon#wrote, iclass 10, count 0 2006.201.01:20:35.88#ibcon#about to read 3, iclass 10, count 0 2006.201.01:20:35.91#ibcon#read 3, iclass 10, count 0 2006.201.01:20:35.91#ibcon#about to read 4, iclass 10, count 0 2006.201.01:20:35.91#ibcon#read 4, iclass 10, count 0 2006.201.01:20:35.91#ibcon#about to read 5, iclass 10, count 0 2006.201.01:20:35.91#ibcon#read 5, iclass 10, count 0 2006.201.01:20:35.91#ibcon#about to read 6, iclass 10, count 0 2006.201.01:20:35.91#ibcon#read 6, iclass 10, count 0 2006.201.01:20:35.91#ibcon#end of sib2, iclass 10, count 0 2006.201.01:20:35.91#ibcon#*after write, iclass 10, count 0 2006.201.01:20:35.91#ibcon#*before return 0, iclass 10, count 0 2006.201.01:20:35.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.01:20:35.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.01:20:35.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.01:20:35.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.01:20:35.91$vck44/vblo=1,629.99 2006.201.01:20:35.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.01:20:35.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.01:20:35.91#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:35.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.01:20:35.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.01:20:35.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.01:20:35.91#ibcon#enter wrdev, iclass 12, count 0 2006.201.01:20:35.91#ibcon#first serial, iclass 12, count 0 2006.201.01:20:35.91#ibcon#enter sib2, iclass 12, count 0 2006.201.01:20:35.91#ibcon#flushed, iclass 12, count 0 2006.201.01:20:35.91#ibcon#about to write, iclass 12, count 0 2006.201.01:20:35.91#ibcon#wrote, iclass 12, count 0 2006.201.01:20:35.91#ibcon#about to read 3, iclass 12, count 0 2006.201.01:20:35.93#ibcon#read 3, iclass 12, count 0 2006.201.01:20:35.93#ibcon#about to read 4, iclass 12, count 0 2006.201.01:20:35.93#ibcon#read 4, iclass 12, count 0 2006.201.01:20:35.93#ibcon#about to read 5, iclass 12, count 0 2006.201.01:20:35.93#ibcon#read 5, iclass 12, count 0 2006.201.01:20:35.93#ibcon#about to read 6, iclass 12, count 0 2006.201.01:20:35.93#ibcon#read 6, iclass 12, count 0 2006.201.01:20:35.93#ibcon#end of sib2, iclass 12, count 0 2006.201.01:20:35.93#ibcon#*mode == 0, iclass 12, count 0 2006.201.01:20:35.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.01:20:35.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.01:20:35.93#ibcon#*before write, iclass 12, count 0 2006.201.01:20:35.93#ibcon#enter sib2, iclass 12, count 0 2006.201.01:20:35.93#ibcon#flushed, iclass 12, count 0 2006.201.01:20:35.93#ibcon#about to write, iclass 12, count 0 2006.201.01:20:35.93#ibcon#wrote, iclass 12, count 0 2006.201.01:20:35.93#ibcon#about to read 3, iclass 12, count 0 2006.201.01:20:35.97#ibcon#read 3, iclass 12, count 0 2006.201.01:20:35.97#ibcon#about to read 4, iclass 12, count 0 2006.201.01:20:35.97#ibcon#read 4, iclass 12, count 0 2006.201.01:20:35.97#ibcon#about to read 5, iclass 12, count 0 2006.201.01:20:35.97#ibcon#read 5, iclass 12, count 0 2006.201.01:20:35.97#ibcon#about to read 6, iclass 12, count 0 2006.201.01:20:35.97#ibcon#read 6, iclass 12, count 0 2006.201.01:20:35.97#ibcon#end of sib2, iclass 12, count 0 2006.201.01:20:35.97#ibcon#*after write, iclass 12, count 0 2006.201.01:20:35.97#ibcon#*before return 0, iclass 12, count 0 2006.201.01:20:35.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.01:20:35.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.01:20:35.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.01:20:35.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.01:20:35.97$vck44/vb=1,4 2006.201.01:20:35.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.01:20:35.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.01:20:35.97#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:35.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.01:20:35.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.01:20:35.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.01:20:35.97#ibcon#enter wrdev, iclass 14, count 2 2006.201.01:20:35.97#ibcon#first serial, iclass 14, count 2 2006.201.01:20:35.97#ibcon#enter sib2, iclass 14, count 2 2006.201.01:20:35.97#ibcon#flushed, iclass 14, count 2 2006.201.01:20:35.97#ibcon#about to write, iclass 14, count 2 2006.201.01:20:35.97#ibcon#wrote, iclass 14, count 2 2006.201.01:20:35.97#ibcon#about to read 3, iclass 14, count 2 2006.201.01:20:35.99#ibcon#read 3, iclass 14, count 2 2006.201.01:20:35.99#ibcon#about to read 4, iclass 14, count 2 2006.201.01:20:35.99#ibcon#read 4, iclass 14, count 2 2006.201.01:20:35.99#ibcon#about to read 5, iclass 14, count 2 2006.201.01:20:35.99#ibcon#read 5, iclass 14, count 2 2006.201.01:20:35.99#ibcon#about to read 6, iclass 14, count 2 2006.201.01:20:35.99#ibcon#read 6, iclass 14, count 2 2006.201.01:20:35.99#ibcon#end of sib2, iclass 14, count 2 2006.201.01:20:35.99#ibcon#*mode == 0, iclass 14, count 2 2006.201.01:20:35.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.01:20:35.99#ibcon#[27=AT01-04\r\n] 2006.201.01:20:35.99#ibcon#*before write, iclass 14, count 2 2006.201.01:20:35.99#ibcon#enter sib2, iclass 14, count 2 2006.201.01:20:35.99#ibcon#flushed, iclass 14, count 2 2006.201.01:20:35.99#ibcon#about to write, iclass 14, count 2 2006.201.01:20:35.99#ibcon#wrote, iclass 14, count 2 2006.201.01:20:35.99#ibcon#about to read 3, iclass 14, count 2 2006.201.01:20:36.02#ibcon#read 3, iclass 14, count 2 2006.201.01:20:36.02#ibcon#about to read 4, iclass 14, count 2 2006.201.01:20:36.02#ibcon#read 4, iclass 14, count 2 2006.201.01:20:36.02#ibcon#about to read 5, iclass 14, count 2 2006.201.01:20:36.02#ibcon#read 5, iclass 14, count 2 2006.201.01:20:36.02#ibcon#about to read 6, iclass 14, count 2 2006.201.01:20:36.02#ibcon#read 6, iclass 14, count 2 2006.201.01:20:36.02#ibcon#end of sib2, iclass 14, count 2 2006.201.01:20:36.02#ibcon#*after write, iclass 14, count 2 2006.201.01:20:36.02#ibcon#*before return 0, iclass 14, count 2 2006.201.01:20:36.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.01:20:36.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.01:20:36.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.01:20:36.02#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:36.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.01:20:36.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.01:20:36.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.01:20:36.14#ibcon#enter wrdev, iclass 14, count 0 2006.201.01:20:36.14#ibcon#first serial, iclass 14, count 0 2006.201.01:20:36.14#ibcon#enter sib2, iclass 14, count 0 2006.201.01:20:36.14#ibcon#flushed, iclass 14, count 0 2006.201.01:20:36.14#ibcon#about to write, iclass 14, count 0 2006.201.01:20:36.14#ibcon#wrote, iclass 14, count 0 2006.201.01:20:36.14#ibcon#about to read 3, iclass 14, count 0 2006.201.01:20:36.16#ibcon#read 3, iclass 14, count 0 2006.201.01:20:36.16#ibcon#about to read 4, iclass 14, count 0 2006.201.01:20:36.16#ibcon#read 4, iclass 14, count 0 2006.201.01:20:36.16#ibcon#about to read 5, iclass 14, count 0 2006.201.01:20:36.16#ibcon#read 5, iclass 14, count 0 2006.201.01:20:36.16#ibcon#about to read 6, iclass 14, count 0 2006.201.01:20:36.16#ibcon#read 6, iclass 14, count 0 2006.201.01:20:36.16#ibcon#end of sib2, iclass 14, count 0 2006.201.01:20:36.16#ibcon#*mode == 0, iclass 14, count 0 2006.201.01:20:36.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.01:20:36.16#ibcon#[27=USB\r\n] 2006.201.01:20:36.16#ibcon#*before write, iclass 14, count 0 2006.201.01:20:36.16#ibcon#enter sib2, iclass 14, count 0 2006.201.01:20:36.16#ibcon#flushed, iclass 14, count 0 2006.201.01:20:36.16#ibcon#about to write, iclass 14, count 0 2006.201.01:20:36.16#ibcon#wrote, iclass 14, count 0 2006.201.01:20:36.16#ibcon#about to read 3, iclass 14, count 0 2006.201.01:20:36.19#ibcon#read 3, iclass 14, count 0 2006.201.01:20:36.19#ibcon#about to read 4, iclass 14, count 0 2006.201.01:20:36.19#ibcon#read 4, iclass 14, count 0 2006.201.01:20:36.19#ibcon#about to read 5, iclass 14, count 0 2006.201.01:20:36.19#ibcon#read 5, iclass 14, count 0 2006.201.01:20:36.19#ibcon#about to read 6, iclass 14, count 0 2006.201.01:20:36.19#ibcon#read 6, iclass 14, count 0 2006.201.01:20:36.19#ibcon#end of sib2, iclass 14, count 0 2006.201.01:20:36.19#ibcon#*after write, iclass 14, count 0 2006.201.01:20:36.19#ibcon#*before return 0, iclass 14, count 0 2006.201.01:20:36.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.01:20:36.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.01:20:36.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.01:20:36.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.01:20:36.19$vck44/vblo=2,634.99 2006.201.01:20:36.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.01:20:36.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.01:20:36.19#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:36.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:36.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:36.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:36.19#ibcon#enter wrdev, iclass 16, count 0 2006.201.01:20:36.19#ibcon#first serial, iclass 16, count 0 2006.201.01:20:36.19#ibcon#enter sib2, iclass 16, count 0 2006.201.01:20:36.19#ibcon#flushed, iclass 16, count 0 2006.201.01:20:36.19#ibcon#about to write, iclass 16, count 0 2006.201.01:20:36.19#ibcon#wrote, iclass 16, count 0 2006.201.01:20:36.19#ibcon#about to read 3, iclass 16, count 0 2006.201.01:20:36.21#ibcon#read 3, iclass 16, count 0 2006.201.01:20:36.21#ibcon#about to read 4, iclass 16, count 0 2006.201.01:20:36.21#ibcon#read 4, iclass 16, count 0 2006.201.01:20:36.21#ibcon#about to read 5, iclass 16, count 0 2006.201.01:20:36.21#ibcon#read 5, iclass 16, count 0 2006.201.01:20:36.21#ibcon#about to read 6, iclass 16, count 0 2006.201.01:20:36.21#ibcon#read 6, iclass 16, count 0 2006.201.01:20:36.21#ibcon#end of sib2, iclass 16, count 0 2006.201.01:20:36.21#ibcon#*mode == 0, iclass 16, count 0 2006.201.01:20:36.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.01:20:36.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.01:20:36.21#ibcon#*before write, iclass 16, count 0 2006.201.01:20:36.21#ibcon#enter sib2, iclass 16, count 0 2006.201.01:20:36.21#ibcon#flushed, iclass 16, count 0 2006.201.01:20:36.21#ibcon#about to write, iclass 16, count 0 2006.201.01:20:36.21#ibcon#wrote, iclass 16, count 0 2006.201.01:20:36.21#ibcon#about to read 3, iclass 16, count 0 2006.201.01:20:36.25#ibcon#read 3, iclass 16, count 0 2006.201.01:20:36.25#ibcon#about to read 4, iclass 16, count 0 2006.201.01:20:36.25#ibcon#read 4, iclass 16, count 0 2006.201.01:20:36.25#ibcon#about to read 5, iclass 16, count 0 2006.201.01:20:36.25#ibcon#read 5, iclass 16, count 0 2006.201.01:20:36.25#ibcon#about to read 6, iclass 16, count 0 2006.201.01:20:36.25#ibcon#read 6, iclass 16, count 0 2006.201.01:20:36.25#ibcon#end of sib2, iclass 16, count 0 2006.201.01:20:36.25#ibcon#*after write, iclass 16, count 0 2006.201.01:20:36.25#ibcon#*before return 0, iclass 16, count 0 2006.201.01:20:36.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:36.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.01:20:36.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.01:20:36.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.01:20:36.25$vck44/vb=2,5 2006.201.01:20:36.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.01:20:36.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.01:20:36.25#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:36.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:36.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:36.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:36.31#ibcon#enter wrdev, iclass 18, count 2 2006.201.01:20:36.31#ibcon#first serial, iclass 18, count 2 2006.201.01:20:36.31#ibcon#enter sib2, iclass 18, count 2 2006.201.01:20:36.31#ibcon#flushed, iclass 18, count 2 2006.201.01:20:36.31#ibcon#about to write, iclass 18, count 2 2006.201.01:20:36.31#ibcon#wrote, iclass 18, count 2 2006.201.01:20:36.31#ibcon#about to read 3, iclass 18, count 2 2006.201.01:20:36.33#ibcon#read 3, iclass 18, count 2 2006.201.01:20:36.33#ibcon#about to read 4, iclass 18, count 2 2006.201.01:20:36.33#ibcon#read 4, iclass 18, count 2 2006.201.01:20:36.33#ibcon#about to read 5, iclass 18, count 2 2006.201.01:20:36.33#ibcon#read 5, iclass 18, count 2 2006.201.01:20:36.33#ibcon#about to read 6, iclass 18, count 2 2006.201.01:20:36.33#ibcon#read 6, iclass 18, count 2 2006.201.01:20:36.33#ibcon#end of sib2, iclass 18, count 2 2006.201.01:20:36.33#ibcon#*mode == 0, iclass 18, count 2 2006.201.01:20:36.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.01:20:36.33#ibcon#[27=AT02-05\r\n] 2006.201.01:20:36.33#ibcon#*before write, iclass 18, count 2 2006.201.01:20:36.33#ibcon#enter sib2, iclass 18, count 2 2006.201.01:20:36.33#ibcon#flushed, iclass 18, count 2 2006.201.01:20:36.33#ibcon#about to write, iclass 18, count 2 2006.201.01:20:36.33#ibcon#wrote, iclass 18, count 2 2006.201.01:20:36.33#ibcon#about to read 3, iclass 18, count 2 2006.201.01:20:36.36#ibcon#read 3, iclass 18, count 2 2006.201.01:20:36.36#ibcon#about to read 4, iclass 18, count 2 2006.201.01:20:36.36#ibcon#read 4, iclass 18, count 2 2006.201.01:20:36.36#ibcon#about to read 5, iclass 18, count 2 2006.201.01:20:36.36#ibcon#read 5, iclass 18, count 2 2006.201.01:20:36.36#ibcon#about to read 6, iclass 18, count 2 2006.201.01:20:36.36#ibcon#read 6, iclass 18, count 2 2006.201.01:20:36.36#ibcon#end of sib2, iclass 18, count 2 2006.201.01:20:36.36#ibcon#*after write, iclass 18, count 2 2006.201.01:20:36.36#ibcon#*before return 0, iclass 18, count 2 2006.201.01:20:36.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:36.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.01:20:36.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.01:20:36.36#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:36.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:36.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:36.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:36.48#ibcon#enter wrdev, iclass 18, count 0 2006.201.01:20:36.48#ibcon#first serial, iclass 18, count 0 2006.201.01:20:36.48#ibcon#enter sib2, iclass 18, count 0 2006.201.01:20:36.48#ibcon#flushed, iclass 18, count 0 2006.201.01:20:36.48#ibcon#about to write, iclass 18, count 0 2006.201.01:20:36.48#ibcon#wrote, iclass 18, count 0 2006.201.01:20:36.48#ibcon#about to read 3, iclass 18, count 0 2006.201.01:20:36.50#ibcon#read 3, iclass 18, count 0 2006.201.01:20:36.50#ibcon#about to read 4, iclass 18, count 0 2006.201.01:20:36.50#ibcon#read 4, iclass 18, count 0 2006.201.01:20:36.50#ibcon#about to read 5, iclass 18, count 0 2006.201.01:20:36.50#ibcon#read 5, iclass 18, count 0 2006.201.01:20:36.50#ibcon#about to read 6, iclass 18, count 0 2006.201.01:20:36.50#ibcon#read 6, iclass 18, count 0 2006.201.01:20:36.50#ibcon#end of sib2, iclass 18, count 0 2006.201.01:20:36.50#ibcon#*mode == 0, iclass 18, count 0 2006.201.01:20:36.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.01:20:36.50#ibcon#[27=USB\r\n] 2006.201.01:20:36.50#ibcon#*before write, iclass 18, count 0 2006.201.01:20:36.50#ibcon#enter sib2, iclass 18, count 0 2006.201.01:20:36.50#ibcon#flushed, iclass 18, count 0 2006.201.01:20:36.50#ibcon#about to write, iclass 18, count 0 2006.201.01:20:36.50#ibcon#wrote, iclass 18, count 0 2006.201.01:20:36.50#ibcon#about to read 3, iclass 18, count 0 2006.201.01:20:36.53#ibcon#read 3, iclass 18, count 0 2006.201.01:20:36.53#ibcon#about to read 4, iclass 18, count 0 2006.201.01:20:36.53#ibcon#read 4, iclass 18, count 0 2006.201.01:20:36.53#ibcon#about to read 5, iclass 18, count 0 2006.201.01:20:36.53#ibcon#read 5, iclass 18, count 0 2006.201.01:20:36.53#ibcon#about to read 6, iclass 18, count 0 2006.201.01:20:36.53#ibcon#read 6, iclass 18, count 0 2006.201.01:20:36.53#ibcon#end of sib2, iclass 18, count 0 2006.201.01:20:36.53#ibcon#*after write, iclass 18, count 0 2006.201.01:20:36.53#ibcon#*before return 0, iclass 18, count 0 2006.201.01:20:36.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:36.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.01:20:36.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.01:20:36.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.01:20:36.53$vck44/vblo=3,649.99 2006.201.01:20:36.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.01:20:36.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.01:20:36.53#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:36.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:36.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:36.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:36.53#ibcon#enter wrdev, iclass 20, count 0 2006.201.01:20:36.53#ibcon#first serial, iclass 20, count 0 2006.201.01:20:36.53#ibcon#enter sib2, iclass 20, count 0 2006.201.01:20:36.53#ibcon#flushed, iclass 20, count 0 2006.201.01:20:36.53#ibcon#about to write, iclass 20, count 0 2006.201.01:20:36.53#ibcon#wrote, iclass 20, count 0 2006.201.01:20:36.53#ibcon#about to read 3, iclass 20, count 0 2006.201.01:20:36.55#ibcon#read 3, iclass 20, count 0 2006.201.01:20:36.55#ibcon#about to read 4, iclass 20, count 0 2006.201.01:20:36.55#ibcon#read 4, iclass 20, count 0 2006.201.01:20:36.55#ibcon#about to read 5, iclass 20, count 0 2006.201.01:20:36.55#ibcon#read 5, iclass 20, count 0 2006.201.01:20:36.55#ibcon#about to read 6, iclass 20, count 0 2006.201.01:20:36.55#ibcon#read 6, iclass 20, count 0 2006.201.01:20:36.55#ibcon#end of sib2, iclass 20, count 0 2006.201.01:20:36.55#ibcon#*mode == 0, iclass 20, count 0 2006.201.01:20:36.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.01:20:36.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.01:20:36.55#ibcon#*before write, iclass 20, count 0 2006.201.01:20:36.55#ibcon#enter sib2, iclass 20, count 0 2006.201.01:20:36.55#ibcon#flushed, iclass 20, count 0 2006.201.01:20:36.55#ibcon#about to write, iclass 20, count 0 2006.201.01:20:36.55#ibcon#wrote, iclass 20, count 0 2006.201.01:20:36.55#ibcon#about to read 3, iclass 20, count 0 2006.201.01:20:36.59#ibcon#read 3, iclass 20, count 0 2006.201.01:20:36.59#ibcon#about to read 4, iclass 20, count 0 2006.201.01:20:36.59#ibcon#read 4, iclass 20, count 0 2006.201.01:20:36.59#ibcon#about to read 5, iclass 20, count 0 2006.201.01:20:36.59#ibcon#read 5, iclass 20, count 0 2006.201.01:20:36.59#ibcon#about to read 6, iclass 20, count 0 2006.201.01:20:36.59#ibcon#read 6, iclass 20, count 0 2006.201.01:20:36.59#ibcon#end of sib2, iclass 20, count 0 2006.201.01:20:36.59#ibcon#*after write, iclass 20, count 0 2006.201.01:20:36.59#ibcon#*before return 0, iclass 20, count 0 2006.201.01:20:36.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:36.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.01:20:36.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.01:20:36.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.01:20:36.59$vck44/vb=3,4 2006.201.01:20:36.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.01:20:36.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.01:20:36.59#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:36.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:36.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:36.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:36.65#ibcon#enter wrdev, iclass 22, count 2 2006.201.01:20:36.65#ibcon#first serial, iclass 22, count 2 2006.201.01:20:36.65#ibcon#enter sib2, iclass 22, count 2 2006.201.01:20:36.65#ibcon#flushed, iclass 22, count 2 2006.201.01:20:36.65#ibcon#about to write, iclass 22, count 2 2006.201.01:20:36.65#ibcon#wrote, iclass 22, count 2 2006.201.01:20:36.65#ibcon#about to read 3, iclass 22, count 2 2006.201.01:20:36.67#ibcon#read 3, iclass 22, count 2 2006.201.01:20:36.67#ibcon#about to read 4, iclass 22, count 2 2006.201.01:20:36.67#ibcon#read 4, iclass 22, count 2 2006.201.01:20:36.67#ibcon#about to read 5, iclass 22, count 2 2006.201.01:20:36.67#ibcon#read 5, iclass 22, count 2 2006.201.01:20:36.67#ibcon#about to read 6, iclass 22, count 2 2006.201.01:20:36.67#ibcon#read 6, iclass 22, count 2 2006.201.01:20:36.67#ibcon#end of sib2, iclass 22, count 2 2006.201.01:20:36.67#ibcon#*mode == 0, iclass 22, count 2 2006.201.01:20:36.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.01:20:36.67#ibcon#[27=AT03-04\r\n] 2006.201.01:20:36.67#ibcon#*before write, iclass 22, count 2 2006.201.01:20:36.67#ibcon#enter sib2, iclass 22, count 2 2006.201.01:20:36.67#ibcon#flushed, iclass 22, count 2 2006.201.01:20:36.67#ibcon#about to write, iclass 22, count 2 2006.201.01:20:36.67#ibcon#wrote, iclass 22, count 2 2006.201.01:20:36.67#ibcon#about to read 3, iclass 22, count 2 2006.201.01:20:36.70#ibcon#read 3, iclass 22, count 2 2006.201.01:20:36.70#ibcon#about to read 4, iclass 22, count 2 2006.201.01:20:36.70#ibcon#read 4, iclass 22, count 2 2006.201.01:20:36.70#ibcon#about to read 5, iclass 22, count 2 2006.201.01:20:36.70#ibcon#read 5, iclass 22, count 2 2006.201.01:20:36.70#ibcon#about to read 6, iclass 22, count 2 2006.201.01:20:36.70#ibcon#read 6, iclass 22, count 2 2006.201.01:20:36.70#ibcon#end of sib2, iclass 22, count 2 2006.201.01:20:36.70#ibcon#*after write, iclass 22, count 2 2006.201.01:20:36.70#ibcon#*before return 0, iclass 22, count 2 2006.201.01:20:36.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:36.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.01:20:36.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.01:20:36.70#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:36.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:36.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:36.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:36.82#ibcon#enter wrdev, iclass 22, count 0 2006.201.01:20:36.82#ibcon#first serial, iclass 22, count 0 2006.201.01:20:36.82#ibcon#enter sib2, iclass 22, count 0 2006.201.01:20:36.82#ibcon#flushed, iclass 22, count 0 2006.201.01:20:36.82#ibcon#about to write, iclass 22, count 0 2006.201.01:20:36.82#ibcon#wrote, iclass 22, count 0 2006.201.01:20:36.82#ibcon#about to read 3, iclass 22, count 0 2006.201.01:20:36.84#ibcon#read 3, iclass 22, count 0 2006.201.01:20:36.84#ibcon#about to read 4, iclass 22, count 0 2006.201.01:20:36.84#ibcon#read 4, iclass 22, count 0 2006.201.01:20:36.84#ibcon#about to read 5, iclass 22, count 0 2006.201.01:20:36.84#ibcon#read 5, iclass 22, count 0 2006.201.01:20:36.84#ibcon#about to read 6, iclass 22, count 0 2006.201.01:20:36.84#ibcon#read 6, iclass 22, count 0 2006.201.01:20:36.84#ibcon#end of sib2, iclass 22, count 0 2006.201.01:20:36.84#ibcon#*mode == 0, iclass 22, count 0 2006.201.01:20:36.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.01:20:36.84#ibcon#[27=USB\r\n] 2006.201.01:20:36.84#ibcon#*before write, iclass 22, count 0 2006.201.01:20:36.84#ibcon#enter sib2, iclass 22, count 0 2006.201.01:20:36.84#ibcon#flushed, iclass 22, count 0 2006.201.01:20:36.84#ibcon#about to write, iclass 22, count 0 2006.201.01:20:36.84#ibcon#wrote, iclass 22, count 0 2006.201.01:20:36.84#ibcon#about to read 3, iclass 22, count 0 2006.201.01:20:36.87#ibcon#read 3, iclass 22, count 0 2006.201.01:20:36.87#ibcon#about to read 4, iclass 22, count 0 2006.201.01:20:36.87#ibcon#read 4, iclass 22, count 0 2006.201.01:20:36.87#ibcon#about to read 5, iclass 22, count 0 2006.201.01:20:36.87#ibcon#read 5, iclass 22, count 0 2006.201.01:20:36.87#ibcon#about to read 6, iclass 22, count 0 2006.201.01:20:36.87#ibcon#read 6, iclass 22, count 0 2006.201.01:20:36.87#ibcon#end of sib2, iclass 22, count 0 2006.201.01:20:36.87#ibcon#*after write, iclass 22, count 0 2006.201.01:20:36.87#ibcon#*before return 0, iclass 22, count 0 2006.201.01:20:36.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:36.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.01:20:36.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.01:20:36.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.01:20:36.87$vck44/vblo=4,679.99 2006.201.01:20:36.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.01:20:36.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.01:20:36.87#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:36.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:36.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:36.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:36.87#ibcon#enter wrdev, iclass 24, count 0 2006.201.01:20:36.87#ibcon#first serial, iclass 24, count 0 2006.201.01:20:36.87#ibcon#enter sib2, iclass 24, count 0 2006.201.01:20:36.87#ibcon#flushed, iclass 24, count 0 2006.201.01:20:36.87#ibcon#about to write, iclass 24, count 0 2006.201.01:20:36.87#ibcon#wrote, iclass 24, count 0 2006.201.01:20:36.87#ibcon#about to read 3, iclass 24, count 0 2006.201.01:20:36.89#ibcon#read 3, iclass 24, count 0 2006.201.01:20:36.89#ibcon#about to read 4, iclass 24, count 0 2006.201.01:20:36.89#ibcon#read 4, iclass 24, count 0 2006.201.01:20:36.89#ibcon#about to read 5, iclass 24, count 0 2006.201.01:20:36.89#ibcon#read 5, iclass 24, count 0 2006.201.01:20:36.89#ibcon#about to read 6, iclass 24, count 0 2006.201.01:20:36.89#ibcon#read 6, iclass 24, count 0 2006.201.01:20:36.89#ibcon#end of sib2, iclass 24, count 0 2006.201.01:20:36.89#ibcon#*mode == 0, iclass 24, count 0 2006.201.01:20:36.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.01:20:36.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.01:20:36.89#ibcon#*before write, iclass 24, count 0 2006.201.01:20:36.89#ibcon#enter sib2, iclass 24, count 0 2006.201.01:20:36.89#ibcon#flushed, iclass 24, count 0 2006.201.01:20:36.89#ibcon#about to write, iclass 24, count 0 2006.201.01:20:36.89#ibcon#wrote, iclass 24, count 0 2006.201.01:20:36.89#ibcon#about to read 3, iclass 24, count 0 2006.201.01:20:36.93#ibcon#read 3, iclass 24, count 0 2006.201.01:20:36.93#ibcon#about to read 4, iclass 24, count 0 2006.201.01:20:36.93#ibcon#read 4, iclass 24, count 0 2006.201.01:20:36.93#ibcon#about to read 5, iclass 24, count 0 2006.201.01:20:36.93#ibcon#read 5, iclass 24, count 0 2006.201.01:20:36.93#ibcon#about to read 6, iclass 24, count 0 2006.201.01:20:36.93#ibcon#read 6, iclass 24, count 0 2006.201.01:20:36.93#ibcon#end of sib2, iclass 24, count 0 2006.201.01:20:36.93#ibcon#*after write, iclass 24, count 0 2006.201.01:20:36.93#ibcon#*before return 0, iclass 24, count 0 2006.201.01:20:36.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:36.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.01:20:36.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.01:20:36.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.01:20:36.93$vck44/vb=4,5 2006.201.01:20:36.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.01:20:36.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.01:20:36.93#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:36.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:36.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:36.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:36.99#ibcon#enter wrdev, iclass 26, count 2 2006.201.01:20:36.99#ibcon#first serial, iclass 26, count 2 2006.201.01:20:36.99#ibcon#enter sib2, iclass 26, count 2 2006.201.01:20:36.99#ibcon#flushed, iclass 26, count 2 2006.201.01:20:36.99#ibcon#about to write, iclass 26, count 2 2006.201.01:20:36.99#ibcon#wrote, iclass 26, count 2 2006.201.01:20:36.99#ibcon#about to read 3, iclass 26, count 2 2006.201.01:20:37.01#ibcon#read 3, iclass 26, count 2 2006.201.01:20:37.01#ibcon#about to read 4, iclass 26, count 2 2006.201.01:20:37.01#ibcon#read 4, iclass 26, count 2 2006.201.01:20:37.01#ibcon#about to read 5, iclass 26, count 2 2006.201.01:20:37.01#ibcon#read 5, iclass 26, count 2 2006.201.01:20:37.01#ibcon#about to read 6, iclass 26, count 2 2006.201.01:20:37.01#ibcon#read 6, iclass 26, count 2 2006.201.01:20:37.01#ibcon#end of sib2, iclass 26, count 2 2006.201.01:20:37.01#ibcon#*mode == 0, iclass 26, count 2 2006.201.01:20:37.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.01:20:37.01#ibcon#[27=AT04-05\r\n] 2006.201.01:20:37.01#ibcon#*before write, iclass 26, count 2 2006.201.01:20:37.01#ibcon#enter sib2, iclass 26, count 2 2006.201.01:20:37.01#ibcon#flushed, iclass 26, count 2 2006.201.01:20:37.01#ibcon#about to write, iclass 26, count 2 2006.201.01:20:37.01#ibcon#wrote, iclass 26, count 2 2006.201.01:20:37.01#ibcon#about to read 3, iclass 26, count 2 2006.201.01:20:37.04#ibcon#read 3, iclass 26, count 2 2006.201.01:20:37.04#ibcon#about to read 4, iclass 26, count 2 2006.201.01:20:37.04#ibcon#read 4, iclass 26, count 2 2006.201.01:20:37.04#ibcon#about to read 5, iclass 26, count 2 2006.201.01:20:37.04#ibcon#read 5, iclass 26, count 2 2006.201.01:20:37.04#ibcon#about to read 6, iclass 26, count 2 2006.201.01:20:37.04#ibcon#read 6, iclass 26, count 2 2006.201.01:20:37.04#ibcon#end of sib2, iclass 26, count 2 2006.201.01:20:37.04#ibcon#*after write, iclass 26, count 2 2006.201.01:20:37.04#ibcon#*before return 0, iclass 26, count 2 2006.201.01:20:37.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:37.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.01:20:37.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.01:20:37.04#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:37.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:37.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:37.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:37.16#ibcon#enter wrdev, iclass 26, count 0 2006.201.01:20:37.16#ibcon#first serial, iclass 26, count 0 2006.201.01:20:37.16#ibcon#enter sib2, iclass 26, count 0 2006.201.01:20:37.16#ibcon#flushed, iclass 26, count 0 2006.201.01:20:37.16#ibcon#about to write, iclass 26, count 0 2006.201.01:20:37.16#ibcon#wrote, iclass 26, count 0 2006.201.01:20:37.16#ibcon#about to read 3, iclass 26, count 0 2006.201.01:20:37.18#ibcon#read 3, iclass 26, count 0 2006.201.01:20:37.18#ibcon#about to read 4, iclass 26, count 0 2006.201.01:20:37.18#ibcon#read 4, iclass 26, count 0 2006.201.01:20:37.18#ibcon#about to read 5, iclass 26, count 0 2006.201.01:20:37.18#ibcon#read 5, iclass 26, count 0 2006.201.01:20:37.18#ibcon#about to read 6, iclass 26, count 0 2006.201.01:20:37.18#ibcon#read 6, iclass 26, count 0 2006.201.01:20:37.18#ibcon#end of sib2, iclass 26, count 0 2006.201.01:20:37.18#ibcon#*mode == 0, iclass 26, count 0 2006.201.01:20:37.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.01:20:37.18#ibcon#[27=USB\r\n] 2006.201.01:20:37.18#ibcon#*before write, iclass 26, count 0 2006.201.01:20:37.18#ibcon#enter sib2, iclass 26, count 0 2006.201.01:20:37.18#ibcon#flushed, iclass 26, count 0 2006.201.01:20:37.18#ibcon#about to write, iclass 26, count 0 2006.201.01:20:37.18#ibcon#wrote, iclass 26, count 0 2006.201.01:20:37.18#ibcon#about to read 3, iclass 26, count 0 2006.201.01:20:37.21#ibcon#read 3, iclass 26, count 0 2006.201.01:20:37.21#ibcon#about to read 4, iclass 26, count 0 2006.201.01:20:37.21#ibcon#read 4, iclass 26, count 0 2006.201.01:20:37.21#ibcon#about to read 5, iclass 26, count 0 2006.201.01:20:37.21#ibcon#read 5, iclass 26, count 0 2006.201.01:20:37.21#ibcon#about to read 6, iclass 26, count 0 2006.201.01:20:37.21#ibcon#read 6, iclass 26, count 0 2006.201.01:20:37.21#ibcon#end of sib2, iclass 26, count 0 2006.201.01:20:37.21#ibcon#*after write, iclass 26, count 0 2006.201.01:20:37.21#ibcon#*before return 0, iclass 26, count 0 2006.201.01:20:37.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:37.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.01:20:37.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.01:20:37.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.01:20:37.21$vck44/vblo=5,709.99 2006.201.01:20:37.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.01:20:37.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.01:20:37.21#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:37.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:37.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:37.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:37.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.01:20:37.21#ibcon#first serial, iclass 28, count 0 2006.201.01:20:37.21#ibcon#enter sib2, iclass 28, count 0 2006.201.01:20:37.21#ibcon#flushed, iclass 28, count 0 2006.201.01:20:37.21#ibcon#about to write, iclass 28, count 0 2006.201.01:20:37.21#ibcon#wrote, iclass 28, count 0 2006.201.01:20:37.21#ibcon#about to read 3, iclass 28, count 0 2006.201.01:20:37.23#ibcon#read 3, iclass 28, count 0 2006.201.01:20:37.23#ibcon#about to read 4, iclass 28, count 0 2006.201.01:20:37.23#ibcon#read 4, iclass 28, count 0 2006.201.01:20:37.23#ibcon#about to read 5, iclass 28, count 0 2006.201.01:20:37.23#ibcon#read 5, iclass 28, count 0 2006.201.01:20:37.23#ibcon#about to read 6, iclass 28, count 0 2006.201.01:20:37.23#ibcon#read 6, iclass 28, count 0 2006.201.01:20:37.23#ibcon#end of sib2, iclass 28, count 0 2006.201.01:20:37.23#ibcon#*mode == 0, iclass 28, count 0 2006.201.01:20:37.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.01:20:37.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.01:20:37.23#ibcon#*before write, iclass 28, count 0 2006.201.01:20:37.23#ibcon#enter sib2, iclass 28, count 0 2006.201.01:20:37.23#ibcon#flushed, iclass 28, count 0 2006.201.01:20:37.23#ibcon#about to write, iclass 28, count 0 2006.201.01:20:37.23#ibcon#wrote, iclass 28, count 0 2006.201.01:20:37.23#ibcon#about to read 3, iclass 28, count 0 2006.201.01:20:37.27#ibcon#read 3, iclass 28, count 0 2006.201.01:20:37.27#ibcon#about to read 4, iclass 28, count 0 2006.201.01:20:37.27#ibcon#read 4, iclass 28, count 0 2006.201.01:20:37.27#ibcon#about to read 5, iclass 28, count 0 2006.201.01:20:37.27#ibcon#read 5, iclass 28, count 0 2006.201.01:20:37.27#ibcon#about to read 6, iclass 28, count 0 2006.201.01:20:37.27#ibcon#read 6, iclass 28, count 0 2006.201.01:20:37.27#ibcon#end of sib2, iclass 28, count 0 2006.201.01:20:37.27#ibcon#*after write, iclass 28, count 0 2006.201.01:20:37.27#ibcon#*before return 0, iclass 28, count 0 2006.201.01:20:37.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:37.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.01:20:37.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.01:20:37.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.01:20:37.27$vck44/vb=5,4 2006.201.01:20:37.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.01:20:37.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.01:20:37.27#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:37.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:37.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:37.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:37.33#ibcon#enter wrdev, iclass 30, count 2 2006.201.01:20:37.33#ibcon#first serial, iclass 30, count 2 2006.201.01:20:37.33#ibcon#enter sib2, iclass 30, count 2 2006.201.01:20:37.33#ibcon#flushed, iclass 30, count 2 2006.201.01:20:37.33#ibcon#about to write, iclass 30, count 2 2006.201.01:20:37.33#ibcon#wrote, iclass 30, count 2 2006.201.01:20:37.33#ibcon#about to read 3, iclass 30, count 2 2006.201.01:20:37.35#ibcon#read 3, iclass 30, count 2 2006.201.01:20:37.35#ibcon#about to read 4, iclass 30, count 2 2006.201.01:20:37.35#ibcon#read 4, iclass 30, count 2 2006.201.01:20:37.35#ibcon#about to read 5, iclass 30, count 2 2006.201.01:20:37.35#ibcon#read 5, iclass 30, count 2 2006.201.01:20:37.35#ibcon#about to read 6, iclass 30, count 2 2006.201.01:20:37.35#ibcon#read 6, iclass 30, count 2 2006.201.01:20:37.35#ibcon#end of sib2, iclass 30, count 2 2006.201.01:20:37.35#ibcon#*mode == 0, iclass 30, count 2 2006.201.01:20:37.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.01:20:37.35#ibcon#[27=AT05-04\r\n] 2006.201.01:20:37.35#ibcon#*before write, iclass 30, count 2 2006.201.01:20:37.35#ibcon#enter sib2, iclass 30, count 2 2006.201.01:20:37.35#ibcon#flushed, iclass 30, count 2 2006.201.01:20:37.35#ibcon#about to write, iclass 30, count 2 2006.201.01:20:37.35#ibcon#wrote, iclass 30, count 2 2006.201.01:20:37.35#ibcon#about to read 3, iclass 30, count 2 2006.201.01:20:37.38#ibcon#read 3, iclass 30, count 2 2006.201.01:20:37.38#ibcon#about to read 4, iclass 30, count 2 2006.201.01:20:37.38#ibcon#read 4, iclass 30, count 2 2006.201.01:20:37.38#ibcon#about to read 5, iclass 30, count 2 2006.201.01:20:37.38#ibcon#read 5, iclass 30, count 2 2006.201.01:20:37.38#ibcon#about to read 6, iclass 30, count 2 2006.201.01:20:37.38#ibcon#read 6, iclass 30, count 2 2006.201.01:20:37.38#ibcon#end of sib2, iclass 30, count 2 2006.201.01:20:37.38#ibcon#*after write, iclass 30, count 2 2006.201.01:20:37.38#ibcon#*before return 0, iclass 30, count 2 2006.201.01:20:37.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:37.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.01:20:37.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.01:20:37.38#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:37.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:37.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:37.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:37.50#ibcon#enter wrdev, iclass 30, count 0 2006.201.01:20:37.50#ibcon#first serial, iclass 30, count 0 2006.201.01:20:37.50#ibcon#enter sib2, iclass 30, count 0 2006.201.01:20:37.50#ibcon#flushed, iclass 30, count 0 2006.201.01:20:37.50#ibcon#about to write, iclass 30, count 0 2006.201.01:20:37.50#ibcon#wrote, iclass 30, count 0 2006.201.01:20:37.50#ibcon#about to read 3, iclass 30, count 0 2006.201.01:20:37.52#ibcon#read 3, iclass 30, count 0 2006.201.01:20:37.52#ibcon#about to read 4, iclass 30, count 0 2006.201.01:20:37.52#ibcon#read 4, iclass 30, count 0 2006.201.01:20:37.52#ibcon#about to read 5, iclass 30, count 0 2006.201.01:20:37.52#ibcon#read 5, iclass 30, count 0 2006.201.01:20:37.52#ibcon#about to read 6, iclass 30, count 0 2006.201.01:20:37.52#ibcon#read 6, iclass 30, count 0 2006.201.01:20:37.52#ibcon#end of sib2, iclass 30, count 0 2006.201.01:20:37.52#ibcon#*mode == 0, iclass 30, count 0 2006.201.01:20:37.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.01:20:37.52#ibcon#[27=USB\r\n] 2006.201.01:20:37.52#ibcon#*before write, iclass 30, count 0 2006.201.01:20:37.52#ibcon#enter sib2, iclass 30, count 0 2006.201.01:20:37.52#ibcon#flushed, iclass 30, count 0 2006.201.01:20:37.52#ibcon#about to write, iclass 30, count 0 2006.201.01:20:37.52#ibcon#wrote, iclass 30, count 0 2006.201.01:20:37.52#ibcon#about to read 3, iclass 30, count 0 2006.201.01:20:37.55#ibcon#read 3, iclass 30, count 0 2006.201.01:20:37.55#ibcon#about to read 4, iclass 30, count 0 2006.201.01:20:37.55#ibcon#read 4, iclass 30, count 0 2006.201.01:20:37.55#ibcon#about to read 5, iclass 30, count 0 2006.201.01:20:37.55#ibcon#read 5, iclass 30, count 0 2006.201.01:20:37.55#ibcon#about to read 6, iclass 30, count 0 2006.201.01:20:37.55#ibcon#read 6, iclass 30, count 0 2006.201.01:20:37.55#ibcon#end of sib2, iclass 30, count 0 2006.201.01:20:37.55#ibcon#*after write, iclass 30, count 0 2006.201.01:20:37.55#ibcon#*before return 0, iclass 30, count 0 2006.201.01:20:37.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:37.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.01:20:37.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.01:20:37.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.01:20:37.55$vck44/vblo=6,719.99 2006.201.01:20:37.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.01:20:37.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.01:20:37.55#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:37.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:37.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:37.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:37.55#ibcon#enter wrdev, iclass 32, count 0 2006.201.01:20:37.55#ibcon#first serial, iclass 32, count 0 2006.201.01:20:37.55#ibcon#enter sib2, iclass 32, count 0 2006.201.01:20:37.55#ibcon#flushed, iclass 32, count 0 2006.201.01:20:37.55#ibcon#about to write, iclass 32, count 0 2006.201.01:20:37.55#ibcon#wrote, iclass 32, count 0 2006.201.01:20:37.55#ibcon#about to read 3, iclass 32, count 0 2006.201.01:20:37.57#ibcon#read 3, iclass 32, count 0 2006.201.01:20:37.57#ibcon#about to read 4, iclass 32, count 0 2006.201.01:20:37.57#ibcon#read 4, iclass 32, count 0 2006.201.01:20:37.57#ibcon#about to read 5, iclass 32, count 0 2006.201.01:20:37.57#ibcon#read 5, iclass 32, count 0 2006.201.01:20:37.57#ibcon#about to read 6, iclass 32, count 0 2006.201.01:20:37.57#ibcon#read 6, iclass 32, count 0 2006.201.01:20:37.57#ibcon#end of sib2, iclass 32, count 0 2006.201.01:20:37.57#ibcon#*mode == 0, iclass 32, count 0 2006.201.01:20:37.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.01:20:37.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.01:20:37.57#ibcon#*before write, iclass 32, count 0 2006.201.01:20:37.57#ibcon#enter sib2, iclass 32, count 0 2006.201.01:20:37.57#ibcon#flushed, iclass 32, count 0 2006.201.01:20:37.57#ibcon#about to write, iclass 32, count 0 2006.201.01:20:37.57#ibcon#wrote, iclass 32, count 0 2006.201.01:20:37.57#ibcon#about to read 3, iclass 32, count 0 2006.201.01:20:37.61#ibcon#read 3, iclass 32, count 0 2006.201.01:20:37.61#ibcon#about to read 4, iclass 32, count 0 2006.201.01:20:37.61#ibcon#read 4, iclass 32, count 0 2006.201.01:20:37.61#ibcon#about to read 5, iclass 32, count 0 2006.201.01:20:37.61#ibcon#read 5, iclass 32, count 0 2006.201.01:20:37.61#ibcon#about to read 6, iclass 32, count 0 2006.201.01:20:37.61#ibcon#read 6, iclass 32, count 0 2006.201.01:20:37.61#ibcon#end of sib2, iclass 32, count 0 2006.201.01:20:37.61#ibcon#*after write, iclass 32, count 0 2006.201.01:20:37.61#ibcon#*before return 0, iclass 32, count 0 2006.201.01:20:37.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:37.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.01:20:37.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.01:20:37.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.01:20:37.61$vck44/vb=6,4 2006.201.01:20:37.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.01:20:37.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.01:20:37.61#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:37.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:37.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:37.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:37.67#ibcon#enter wrdev, iclass 34, count 2 2006.201.01:20:37.67#ibcon#first serial, iclass 34, count 2 2006.201.01:20:37.67#ibcon#enter sib2, iclass 34, count 2 2006.201.01:20:37.67#ibcon#flushed, iclass 34, count 2 2006.201.01:20:37.67#ibcon#about to write, iclass 34, count 2 2006.201.01:20:37.67#ibcon#wrote, iclass 34, count 2 2006.201.01:20:37.67#ibcon#about to read 3, iclass 34, count 2 2006.201.01:20:37.69#ibcon#read 3, iclass 34, count 2 2006.201.01:20:37.69#ibcon#about to read 4, iclass 34, count 2 2006.201.01:20:37.69#ibcon#read 4, iclass 34, count 2 2006.201.01:20:37.69#ibcon#about to read 5, iclass 34, count 2 2006.201.01:20:37.69#ibcon#read 5, iclass 34, count 2 2006.201.01:20:37.69#ibcon#about to read 6, iclass 34, count 2 2006.201.01:20:37.69#ibcon#read 6, iclass 34, count 2 2006.201.01:20:37.69#ibcon#end of sib2, iclass 34, count 2 2006.201.01:20:37.69#ibcon#*mode == 0, iclass 34, count 2 2006.201.01:20:37.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.01:20:37.69#ibcon#[27=AT06-04\r\n] 2006.201.01:20:37.69#ibcon#*before write, iclass 34, count 2 2006.201.01:20:37.69#ibcon#enter sib2, iclass 34, count 2 2006.201.01:20:37.69#ibcon#flushed, iclass 34, count 2 2006.201.01:20:37.69#ibcon#about to write, iclass 34, count 2 2006.201.01:20:37.69#ibcon#wrote, iclass 34, count 2 2006.201.01:20:37.69#ibcon#about to read 3, iclass 34, count 2 2006.201.01:20:37.72#ibcon#read 3, iclass 34, count 2 2006.201.01:20:37.72#ibcon#about to read 4, iclass 34, count 2 2006.201.01:20:37.72#ibcon#read 4, iclass 34, count 2 2006.201.01:20:37.72#ibcon#about to read 5, iclass 34, count 2 2006.201.01:20:37.72#ibcon#read 5, iclass 34, count 2 2006.201.01:20:37.72#ibcon#about to read 6, iclass 34, count 2 2006.201.01:20:37.72#ibcon#read 6, iclass 34, count 2 2006.201.01:20:37.72#ibcon#end of sib2, iclass 34, count 2 2006.201.01:20:37.72#ibcon#*after write, iclass 34, count 2 2006.201.01:20:37.72#ibcon#*before return 0, iclass 34, count 2 2006.201.01:20:37.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:37.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.01:20:37.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.01:20:37.72#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:37.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:37.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:37.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:37.84#ibcon#enter wrdev, iclass 34, count 0 2006.201.01:20:37.84#ibcon#first serial, iclass 34, count 0 2006.201.01:20:37.84#ibcon#enter sib2, iclass 34, count 0 2006.201.01:20:37.84#ibcon#flushed, iclass 34, count 0 2006.201.01:20:37.84#ibcon#about to write, iclass 34, count 0 2006.201.01:20:37.84#ibcon#wrote, iclass 34, count 0 2006.201.01:20:37.84#ibcon#about to read 3, iclass 34, count 0 2006.201.01:20:37.86#ibcon#read 3, iclass 34, count 0 2006.201.01:20:37.86#ibcon#about to read 4, iclass 34, count 0 2006.201.01:20:37.86#ibcon#read 4, iclass 34, count 0 2006.201.01:20:37.86#ibcon#about to read 5, iclass 34, count 0 2006.201.01:20:37.86#ibcon#read 5, iclass 34, count 0 2006.201.01:20:37.86#ibcon#about to read 6, iclass 34, count 0 2006.201.01:20:37.86#ibcon#read 6, iclass 34, count 0 2006.201.01:20:37.86#ibcon#end of sib2, iclass 34, count 0 2006.201.01:20:37.86#ibcon#*mode == 0, iclass 34, count 0 2006.201.01:20:37.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.01:20:37.86#ibcon#[27=USB\r\n] 2006.201.01:20:37.86#ibcon#*before write, iclass 34, count 0 2006.201.01:20:37.86#ibcon#enter sib2, iclass 34, count 0 2006.201.01:20:37.86#ibcon#flushed, iclass 34, count 0 2006.201.01:20:37.86#ibcon#about to write, iclass 34, count 0 2006.201.01:20:37.86#ibcon#wrote, iclass 34, count 0 2006.201.01:20:37.86#ibcon#about to read 3, iclass 34, count 0 2006.201.01:20:37.89#ibcon#read 3, iclass 34, count 0 2006.201.01:20:37.89#ibcon#about to read 4, iclass 34, count 0 2006.201.01:20:37.89#ibcon#read 4, iclass 34, count 0 2006.201.01:20:37.89#ibcon#about to read 5, iclass 34, count 0 2006.201.01:20:37.89#ibcon#read 5, iclass 34, count 0 2006.201.01:20:37.89#ibcon#about to read 6, iclass 34, count 0 2006.201.01:20:37.89#ibcon#read 6, iclass 34, count 0 2006.201.01:20:37.89#ibcon#end of sib2, iclass 34, count 0 2006.201.01:20:37.89#ibcon#*after write, iclass 34, count 0 2006.201.01:20:37.89#ibcon#*before return 0, iclass 34, count 0 2006.201.01:20:37.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:37.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.01:20:37.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.01:20:37.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.01:20:37.89$vck44/vblo=7,734.99 2006.201.01:20:37.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.01:20:37.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.01:20:37.89#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:37.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:37.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:37.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:37.89#ibcon#enter wrdev, iclass 36, count 0 2006.201.01:20:37.89#ibcon#first serial, iclass 36, count 0 2006.201.01:20:37.89#ibcon#enter sib2, iclass 36, count 0 2006.201.01:20:37.89#ibcon#flushed, iclass 36, count 0 2006.201.01:20:37.89#ibcon#about to write, iclass 36, count 0 2006.201.01:20:37.89#ibcon#wrote, iclass 36, count 0 2006.201.01:20:37.89#ibcon#about to read 3, iclass 36, count 0 2006.201.01:20:37.91#ibcon#read 3, iclass 36, count 0 2006.201.01:20:37.91#ibcon#about to read 4, iclass 36, count 0 2006.201.01:20:37.91#ibcon#read 4, iclass 36, count 0 2006.201.01:20:37.91#ibcon#about to read 5, iclass 36, count 0 2006.201.01:20:37.91#ibcon#read 5, iclass 36, count 0 2006.201.01:20:37.91#ibcon#about to read 6, iclass 36, count 0 2006.201.01:20:37.91#ibcon#read 6, iclass 36, count 0 2006.201.01:20:37.91#ibcon#end of sib2, iclass 36, count 0 2006.201.01:20:37.91#ibcon#*mode == 0, iclass 36, count 0 2006.201.01:20:37.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.01:20:37.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.01:20:37.91#ibcon#*before write, iclass 36, count 0 2006.201.01:20:37.91#ibcon#enter sib2, iclass 36, count 0 2006.201.01:20:37.91#ibcon#flushed, iclass 36, count 0 2006.201.01:20:37.91#ibcon#about to write, iclass 36, count 0 2006.201.01:20:37.91#ibcon#wrote, iclass 36, count 0 2006.201.01:20:37.91#ibcon#about to read 3, iclass 36, count 0 2006.201.01:20:37.95#ibcon#read 3, iclass 36, count 0 2006.201.01:20:37.95#ibcon#about to read 4, iclass 36, count 0 2006.201.01:20:37.95#ibcon#read 4, iclass 36, count 0 2006.201.01:20:37.95#ibcon#about to read 5, iclass 36, count 0 2006.201.01:20:37.95#ibcon#read 5, iclass 36, count 0 2006.201.01:20:37.95#ibcon#about to read 6, iclass 36, count 0 2006.201.01:20:37.95#ibcon#read 6, iclass 36, count 0 2006.201.01:20:37.95#ibcon#end of sib2, iclass 36, count 0 2006.201.01:20:37.95#ibcon#*after write, iclass 36, count 0 2006.201.01:20:37.95#ibcon#*before return 0, iclass 36, count 0 2006.201.01:20:37.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:37.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.01:20:37.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.01:20:37.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.01:20:37.95$vck44/vb=7,4 2006.201.01:20:37.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.01:20:37.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.01:20:37.95#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:37.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:38.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:38.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:38.01#ibcon#enter wrdev, iclass 38, count 2 2006.201.01:20:38.01#ibcon#first serial, iclass 38, count 2 2006.201.01:20:38.01#ibcon#enter sib2, iclass 38, count 2 2006.201.01:20:38.01#ibcon#flushed, iclass 38, count 2 2006.201.01:20:38.01#ibcon#about to write, iclass 38, count 2 2006.201.01:20:38.01#ibcon#wrote, iclass 38, count 2 2006.201.01:20:38.01#ibcon#about to read 3, iclass 38, count 2 2006.201.01:20:38.03#ibcon#read 3, iclass 38, count 2 2006.201.01:20:38.03#ibcon#about to read 4, iclass 38, count 2 2006.201.01:20:38.03#ibcon#read 4, iclass 38, count 2 2006.201.01:20:38.03#ibcon#about to read 5, iclass 38, count 2 2006.201.01:20:38.03#ibcon#read 5, iclass 38, count 2 2006.201.01:20:38.03#ibcon#about to read 6, iclass 38, count 2 2006.201.01:20:38.03#ibcon#read 6, iclass 38, count 2 2006.201.01:20:38.03#ibcon#end of sib2, iclass 38, count 2 2006.201.01:20:38.03#ibcon#*mode == 0, iclass 38, count 2 2006.201.01:20:38.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.01:20:38.03#ibcon#[27=AT07-04\r\n] 2006.201.01:20:38.03#ibcon#*before write, iclass 38, count 2 2006.201.01:20:38.03#ibcon#enter sib2, iclass 38, count 2 2006.201.01:20:38.03#ibcon#flushed, iclass 38, count 2 2006.201.01:20:38.03#ibcon#about to write, iclass 38, count 2 2006.201.01:20:38.03#ibcon#wrote, iclass 38, count 2 2006.201.01:20:38.03#ibcon#about to read 3, iclass 38, count 2 2006.201.01:20:38.06#ibcon#read 3, iclass 38, count 2 2006.201.01:20:38.06#ibcon#about to read 4, iclass 38, count 2 2006.201.01:20:38.06#ibcon#read 4, iclass 38, count 2 2006.201.01:20:38.06#ibcon#about to read 5, iclass 38, count 2 2006.201.01:20:38.06#ibcon#read 5, iclass 38, count 2 2006.201.01:20:38.06#ibcon#about to read 6, iclass 38, count 2 2006.201.01:20:38.06#ibcon#read 6, iclass 38, count 2 2006.201.01:20:38.06#ibcon#end of sib2, iclass 38, count 2 2006.201.01:20:38.06#ibcon#*after write, iclass 38, count 2 2006.201.01:20:38.06#ibcon#*before return 0, iclass 38, count 2 2006.201.01:20:38.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:38.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.01:20:38.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.01:20:38.06#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:38.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:38.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:38.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:38.18#ibcon#enter wrdev, iclass 38, count 0 2006.201.01:20:38.18#ibcon#first serial, iclass 38, count 0 2006.201.01:20:38.18#ibcon#enter sib2, iclass 38, count 0 2006.201.01:20:38.18#ibcon#flushed, iclass 38, count 0 2006.201.01:20:38.18#ibcon#about to write, iclass 38, count 0 2006.201.01:20:38.18#ibcon#wrote, iclass 38, count 0 2006.201.01:20:38.18#ibcon#about to read 3, iclass 38, count 0 2006.201.01:20:38.20#ibcon#read 3, iclass 38, count 0 2006.201.01:20:38.20#ibcon#about to read 4, iclass 38, count 0 2006.201.01:20:38.20#ibcon#read 4, iclass 38, count 0 2006.201.01:20:38.20#ibcon#about to read 5, iclass 38, count 0 2006.201.01:20:38.20#ibcon#read 5, iclass 38, count 0 2006.201.01:20:38.20#ibcon#about to read 6, iclass 38, count 0 2006.201.01:20:38.20#ibcon#read 6, iclass 38, count 0 2006.201.01:20:38.20#ibcon#end of sib2, iclass 38, count 0 2006.201.01:20:38.20#ibcon#*mode == 0, iclass 38, count 0 2006.201.01:20:38.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.01:20:38.20#ibcon#[27=USB\r\n] 2006.201.01:20:38.20#ibcon#*before write, iclass 38, count 0 2006.201.01:20:38.20#ibcon#enter sib2, iclass 38, count 0 2006.201.01:20:38.20#ibcon#flushed, iclass 38, count 0 2006.201.01:20:38.20#ibcon#about to write, iclass 38, count 0 2006.201.01:20:38.20#ibcon#wrote, iclass 38, count 0 2006.201.01:20:38.20#ibcon#about to read 3, iclass 38, count 0 2006.201.01:20:38.23#ibcon#read 3, iclass 38, count 0 2006.201.01:20:38.23#ibcon#about to read 4, iclass 38, count 0 2006.201.01:20:38.23#ibcon#read 4, iclass 38, count 0 2006.201.01:20:38.23#ibcon#about to read 5, iclass 38, count 0 2006.201.01:20:38.23#ibcon#read 5, iclass 38, count 0 2006.201.01:20:38.23#ibcon#about to read 6, iclass 38, count 0 2006.201.01:20:38.23#ibcon#read 6, iclass 38, count 0 2006.201.01:20:38.23#ibcon#end of sib2, iclass 38, count 0 2006.201.01:20:38.23#ibcon#*after write, iclass 38, count 0 2006.201.01:20:38.23#ibcon#*before return 0, iclass 38, count 0 2006.201.01:20:38.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:38.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.01:20:38.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.01:20:38.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.01:20:38.23$vck44/vblo=8,744.99 2006.201.01:20:38.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.01:20:38.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.01:20:38.23#ibcon#ireg 17 cls_cnt 0 2006.201.01:20:38.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:38.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:38.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:38.23#ibcon#enter wrdev, iclass 40, count 0 2006.201.01:20:38.23#ibcon#first serial, iclass 40, count 0 2006.201.01:20:38.23#ibcon#enter sib2, iclass 40, count 0 2006.201.01:20:38.23#ibcon#flushed, iclass 40, count 0 2006.201.01:20:38.23#ibcon#about to write, iclass 40, count 0 2006.201.01:20:38.23#ibcon#wrote, iclass 40, count 0 2006.201.01:20:38.23#ibcon#about to read 3, iclass 40, count 0 2006.201.01:20:38.25#ibcon#read 3, iclass 40, count 0 2006.201.01:20:38.25#ibcon#about to read 4, iclass 40, count 0 2006.201.01:20:38.25#ibcon#read 4, iclass 40, count 0 2006.201.01:20:38.25#ibcon#about to read 5, iclass 40, count 0 2006.201.01:20:38.25#ibcon#read 5, iclass 40, count 0 2006.201.01:20:38.25#ibcon#about to read 6, iclass 40, count 0 2006.201.01:20:38.25#ibcon#read 6, iclass 40, count 0 2006.201.01:20:38.25#ibcon#end of sib2, iclass 40, count 0 2006.201.01:20:38.25#ibcon#*mode == 0, iclass 40, count 0 2006.201.01:20:38.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.01:20:38.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.01:20:38.25#ibcon#*before write, iclass 40, count 0 2006.201.01:20:38.25#ibcon#enter sib2, iclass 40, count 0 2006.201.01:20:38.25#ibcon#flushed, iclass 40, count 0 2006.201.01:20:38.25#ibcon#about to write, iclass 40, count 0 2006.201.01:20:38.25#ibcon#wrote, iclass 40, count 0 2006.201.01:20:38.25#ibcon#about to read 3, iclass 40, count 0 2006.201.01:20:38.29#ibcon#read 3, iclass 40, count 0 2006.201.01:20:38.29#ibcon#about to read 4, iclass 40, count 0 2006.201.01:20:38.29#ibcon#read 4, iclass 40, count 0 2006.201.01:20:38.29#ibcon#about to read 5, iclass 40, count 0 2006.201.01:20:38.29#ibcon#read 5, iclass 40, count 0 2006.201.01:20:38.29#ibcon#about to read 6, iclass 40, count 0 2006.201.01:20:38.29#ibcon#read 6, iclass 40, count 0 2006.201.01:20:38.29#ibcon#end of sib2, iclass 40, count 0 2006.201.01:20:38.29#ibcon#*after write, iclass 40, count 0 2006.201.01:20:38.29#ibcon#*before return 0, iclass 40, count 0 2006.201.01:20:38.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:38.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.01:20:38.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.01:20:38.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.01:20:38.29$vck44/vb=8,4 2006.201.01:20:38.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.01:20:38.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.01:20:38.29#ibcon#ireg 11 cls_cnt 2 2006.201.01:20:38.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:38.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:38.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:38.35#ibcon#enter wrdev, iclass 4, count 2 2006.201.01:20:38.35#ibcon#first serial, iclass 4, count 2 2006.201.01:20:38.35#ibcon#enter sib2, iclass 4, count 2 2006.201.01:20:38.35#ibcon#flushed, iclass 4, count 2 2006.201.01:20:38.35#ibcon#about to write, iclass 4, count 2 2006.201.01:20:38.35#ibcon#wrote, iclass 4, count 2 2006.201.01:20:38.35#ibcon#about to read 3, iclass 4, count 2 2006.201.01:20:38.37#ibcon#read 3, iclass 4, count 2 2006.201.01:20:38.37#ibcon#about to read 4, iclass 4, count 2 2006.201.01:20:38.37#ibcon#read 4, iclass 4, count 2 2006.201.01:20:38.37#ibcon#about to read 5, iclass 4, count 2 2006.201.01:20:38.37#ibcon#read 5, iclass 4, count 2 2006.201.01:20:38.37#ibcon#about to read 6, iclass 4, count 2 2006.201.01:20:38.37#ibcon#read 6, iclass 4, count 2 2006.201.01:20:38.37#ibcon#end of sib2, iclass 4, count 2 2006.201.01:20:38.37#ibcon#*mode == 0, iclass 4, count 2 2006.201.01:20:38.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.01:20:38.37#ibcon#[27=AT08-04\r\n] 2006.201.01:20:38.37#ibcon#*before write, iclass 4, count 2 2006.201.01:20:38.37#ibcon#enter sib2, iclass 4, count 2 2006.201.01:20:38.37#ibcon#flushed, iclass 4, count 2 2006.201.01:20:38.37#ibcon#about to write, iclass 4, count 2 2006.201.01:20:38.37#ibcon#wrote, iclass 4, count 2 2006.201.01:20:38.37#ibcon#about to read 3, iclass 4, count 2 2006.201.01:20:38.40#ibcon#read 3, iclass 4, count 2 2006.201.01:20:38.40#ibcon#about to read 4, iclass 4, count 2 2006.201.01:20:38.40#ibcon#read 4, iclass 4, count 2 2006.201.01:20:38.40#ibcon#about to read 5, iclass 4, count 2 2006.201.01:20:38.40#ibcon#read 5, iclass 4, count 2 2006.201.01:20:38.40#ibcon#about to read 6, iclass 4, count 2 2006.201.01:20:38.40#ibcon#read 6, iclass 4, count 2 2006.201.01:20:38.40#ibcon#end of sib2, iclass 4, count 2 2006.201.01:20:38.40#ibcon#*after write, iclass 4, count 2 2006.201.01:20:38.40#ibcon#*before return 0, iclass 4, count 2 2006.201.01:20:38.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:38.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.01:20:38.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.01:20:38.40#ibcon#ireg 7 cls_cnt 0 2006.201.01:20:38.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:38.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:38.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:38.52#ibcon#enter wrdev, iclass 4, count 0 2006.201.01:20:38.52#ibcon#first serial, iclass 4, count 0 2006.201.01:20:38.52#ibcon#enter sib2, iclass 4, count 0 2006.201.01:20:38.52#ibcon#flushed, iclass 4, count 0 2006.201.01:20:38.52#ibcon#about to write, iclass 4, count 0 2006.201.01:20:38.52#ibcon#wrote, iclass 4, count 0 2006.201.01:20:38.52#ibcon#about to read 3, iclass 4, count 0 2006.201.01:20:38.54#ibcon#read 3, iclass 4, count 0 2006.201.01:20:38.54#ibcon#about to read 4, iclass 4, count 0 2006.201.01:20:38.54#ibcon#read 4, iclass 4, count 0 2006.201.01:20:38.54#ibcon#about to read 5, iclass 4, count 0 2006.201.01:20:38.54#ibcon#read 5, iclass 4, count 0 2006.201.01:20:38.54#ibcon#about to read 6, iclass 4, count 0 2006.201.01:20:38.54#ibcon#read 6, iclass 4, count 0 2006.201.01:20:38.54#ibcon#end of sib2, iclass 4, count 0 2006.201.01:20:38.54#ibcon#*mode == 0, iclass 4, count 0 2006.201.01:20:38.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.01:20:38.54#ibcon#[27=USB\r\n] 2006.201.01:20:38.54#ibcon#*before write, iclass 4, count 0 2006.201.01:20:38.54#ibcon#enter sib2, iclass 4, count 0 2006.201.01:20:38.54#ibcon#flushed, iclass 4, count 0 2006.201.01:20:38.54#ibcon#about to write, iclass 4, count 0 2006.201.01:20:38.54#ibcon#wrote, iclass 4, count 0 2006.201.01:20:38.54#ibcon#about to read 3, iclass 4, count 0 2006.201.01:20:38.57#ibcon#read 3, iclass 4, count 0 2006.201.01:20:38.57#ibcon#about to read 4, iclass 4, count 0 2006.201.01:20:38.57#ibcon#read 4, iclass 4, count 0 2006.201.01:20:38.57#ibcon#about to read 5, iclass 4, count 0 2006.201.01:20:38.57#ibcon#read 5, iclass 4, count 0 2006.201.01:20:38.57#ibcon#about to read 6, iclass 4, count 0 2006.201.01:20:38.57#ibcon#read 6, iclass 4, count 0 2006.201.01:20:38.57#ibcon#end of sib2, iclass 4, count 0 2006.201.01:20:38.57#ibcon#*after write, iclass 4, count 0 2006.201.01:20:38.57#ibcon#*before return 0, iclass 4, count 0 2006.201.01:20:38.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:38.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.01:20:38.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.01:20:38.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.01:20:38.57$vck44/vabw=wide 2006.201.01:20:38.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.01:20:38.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.01:20:38.57#ibcon#ireg 8 cls_cnt 0 2006.201.01:20:38.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:38.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:38.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:38.57#ibcon#enter wrdev, iclass 6, count 0 2006.201.01:20:38.57#ibcon#first serial, iclass 6, count 0 2006.201.01:20:38.57#ibcon#enter sib2, iclass 6, count 0 2006.201.01:20:38.57#ibcon#flushed, iclass 6, count 0 2006.201.01:20:38.57#ibcon#about to write, iclass 6, count 0 2006.201.01:20:38.57#ibcon#wrote, iclass 6, count 0 2006.201.01:20:38.57#ibcon#about to read 3, iclass 6, count 0 2006.201.01:20:38.59#ibcon#read 3, iclass 6, count 0 2006.201.01:20:38.59#ibcon#about to read 4, iclass 6, count 0 2006.201.01:20:38.59#ibcon#read 4, iclass 6, count 0 2006.201.01:20:38.59#ibcon#about to read 5, iclass 6, count 0 2006.201.01:20:38.59#ibcon#read 5, iclass 6, count 0 2006.201.01:20:38.59#ibcon#about to read 6, iclass 6, count 0 2006.201.01:20:38.59#ibcon#read 6, iclass 6, count 0 2006.201.01:20:38.59#ibcon#end of sib2, iclass 6, count 0 2006.201.01:20:38.59#ibcon#*mode == 0, iclass 6, count 0 2006.201.01:20:38.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.01:20:38.59#ibcon#[25=BW32\r\n] 2006.201.01:20:38.59#ibcon#*before write, iclass 6, count 0 2006.201.01:20:38.59#ibcon#enter sib2, iclass 6, count 0 2006.201.01:20:38.59#ibcon#flushed, iclass 6, count 0 2006.201.01:20:38.59#ibcon#about to write, iclass 6, count 0 2006.201.01:20:38.59#ibcon#wrote, iclass 6, count 0 2006.201.01:20:38.59#ibcon#about to read 3, iclass 6, count 0 2006.201.01:20:38.62#ibcon#read 3, iclass 6, count 0 2006.201.01:20:38.62#ibcon#about to read 4, iclass 6, count 0 2006.201.01:20:38.62#ibcon#read 4, iclass 6, count 0 2006.201.01:20:38.62#ibcon#about to read 5, iclass 6, count 0 2006.201.01:20:38.62#ibcon#read 5, iclass 6, count 0 2006.201.01:20:38.62#ibcon#about to read 6, iclass 6, count 0 2006.201.01:20:38.62#ibcon#read 6, iclass 6, count 0 2006.201.01:20:38.62#ibcon#end of sib2, iclass 6, count 0 2006.201.01:20:38.62#ibcon#*after write, iclass 6, count 0 2006.201.01:20:38.62#ibcon#*before return 0, iclass 6, count 0 2006.201.01:20:38.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:38.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.01:20:38.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.01:20:38.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.01:20:38.62$vck44/vbbw=wide 2006.201.01:20:38.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.01:20:38.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.01:20:38.62#ibcon#ireg 8 cls_cnt 0 2006.201.01:20:38.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:38.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:38.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:38.69#ibcon#enter wrdev, iclass 10, count 0 2006.201.01:20:38.69#ibcon#first serial, iclass 10, count 0 2006.201.01:20:38.69#ibcon#enter sib2, iclass 10, count 0 2006.201.01:20:38.69#ibcon#flushed, iclass 10, count 0 2006.201.01:20:38.69#ibcon#about to write, iclass 10, count 0 2006.201.01:20:38.69#ibcon#wrote, iclass 10, count 0 2006.201.01:20:38.69#ibcon#about to read 3, iclass 10, count 0 2006.201.01:20:38.71#ibcon#read 3, iclass 10, count 0 2006.201.01:20:38.71#ibcon#about to read 4, iclass 10, count 0 2006.201.01:20:38.71#ibcon#read 4, iclass 10, count 0 2006.201.01:20:38.71#ibcon#about to read 5, iclass 10, count 0 2006.201.01:20:38.71#ibcon#read 5, iclass 10, count 0 2006.201.01:20:38.71#ibcon#about to read 6, iclass 10, count 0 2006.201.01:20:38.71#ibcon#read 6, iclass 10, count 0 2006.201.01:20:38.71#ibcon#end of sib2, iclass 10, count 0 2006.201.01:20:38.71#ibcon#*mode == 0, iclass 10, count 0 2006.201.01:20:38.71#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.01:20:38.71#ibcon#[27=BW32\r\n] 2006.201.01:20:38.71#ibcon#*before write, iclass 10, count 0 2006.201.01:20:38.71#ibcon#enter sib2, iclass 10, count 0 2006.201.01:20:38.71#ibcon#flushed, iclass 10, count 0 2006.201.01:20:38.71#ibcon#about to write, iclass 10, count 0 2006.201.01:20:38.71#ibcon#wrote, iclass 10, count 0 2006.201.01:20:38.71#ibcon#about to read 3, iclass 10, count 0 2006.201.01:20:38.74#ibcon#read 3, iclass 10, count 0 2006.201.01:20:38.74#ibcon#about to read 4, iclass 10, count 0 2006.201.01:20:38.74#ibcon#read 4, iclass 10, count 0 2006.201.01:20:38.74#ibcon#about to read 5, iclass 10, count 0 2006.201.01:20:38.74#ibcon#read 5, iclass 10, count 0 2006.201.01:20:38.74#ibcon#about to read 6, iclass 10, count 0 2006.201.01:20:38.74#ibcon#read 6, iclass 10, count 0 2006.201.01:20:38.74#ibcon#end of sib2, iclass 10, count 0 2006.201.01:20:38.74#ibcon#*after write, iclass 10, count 0 2006.201.01:20:38.74#ibcon#*before return 0, iclass 10, count 0 2006.201.01:20:38.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:38.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.01:20:38.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.01:20:38.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.01:20:38.74$setupk4/ifdk4 2006.201.01:20:38.74$ifdk4/lo= 2006.201.01:20:38.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.01:20:38.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.01:20:38.74$ifdk4/patch= 2006.201.01:20:38.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.01:20:38.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.01:20:38.74$setupk4/!*+20s 2006.201.01:20:40.85#abcon#<5=/03 2.2 5.1 23.34 931004.8\r\n> 2006.201.01:20:40.87#abcon#{5=INTERFACE CLEAR} 2006.201.01:20:40.93#abcon#[5=S1D000X0/0*\r\n] 2006.201.01:20:50.23;cable 2006.201.01:20:50.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.01:20:50.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.01:20:50.23#ibcon#ireg 4 cls_cnt 0 2006.201.01:20:50.34#ibcon#<3=T +6.4697E-03\r\n> 2006.201.01:20:50.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.01:20:50.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.01:20:50.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.01:20:50.34/cable/+6.4697E-03 2006.201.01:20:51.03#abcon#<5=/03 2.2 5.1 23.35 921004.8\r\n> 2006.201.01:20:51.05#abcon#{5=INTERFACE CLEAR} 2006.201.01:20:51.11#abcon#[5=S1D000X0/0*\r\n] 2006.201.01:20:53.26$setupk4/"tpicd 2006.201.01:20:53.26$setupk4/echo=off 2006.201.01:20:53.26$setupk4/xlog=off 2006.201.01:20:53.26:!2006.201.01:59:50 2006.201.01:21:41.38;cablelong 2006.201.01:21:41.59/cablelong/+7.0305E-03 2006.201.01:21:46.22;cablediff 2006.201.01:21:46.22/cablediff/560.8e-6,+ 2006.201.01:22:45.13;cable 2006.201.01:22:45.27/cable/+6.4689E-03 2006.201.01:23:28.34;wx 2006.201.01:23:28.34/wx/23.40,1004.9,93 2006.201.01:23:37.78;"Sky is cloudy. 2006.201.01:23:41.62;xfe 2006.201.01:23:41.71/xfe/off,on,15.0 2006.201.01:23:45.22;clockoff 2006.201.01:23:45.22&clockoff/"gps-fmout=1p 2006.201.01:23:45.22&clockoff/fmout-gps=1p 2006.201.01:23:46.04/fmout-gps/S +4.28E-07 2006.201.01:59:50.00:preob 2006.201.01:59:50.00&preob/onsource 2006.201.01:59:50.14/onsource/TRACKING 2006.201.01:59:50.14:!2006.201.02:00:00 2006.201.02:00:00.00:"tape 2006.201.02:00:00.00:"st=record 2006.201.02:00:00.00:data_valid=on 2006.201.02:00:00.00:midob 2006.201.02:00:00.00&midob/onsource 2006.201.02:00:00.00&midob/wx 2006.201.02:00:00.00&midob/cable 2006.201.02:00:00.00&midob/va 2006.201.02:00:00.00&midob/valo 2006.201.02:00:00.00&midob/vb 2006.201.02:00:00.00&midob/vblo 2006.201.02:00:00.00&midob/vabw 2006.201.02:00:00.00&midob/vbbw 2006.201.02:00:00.00&midob/"form 2006.201.02:00:00.00&midob/xfe 2006.201.02:00:00.00&midob/ifatt 2006.201.02:00:00.00&midob/clockoff 2006.201.02:00:00.00&midob/sy=logmail 2006.201.02:00:00.00&midob/"sy=run setcl adapt & 2006.201.02:00:00.14/onsource/TRACKING 2006.201.02:00:00.14/wx/22.92,1005.1,93 2006.201.02:00:00.23/cable/+6.4653E-03 2006.201.02:00:01.32/va/01,08,usb,yes,28,31 2006.201.02:00:01.32/va/02,07,usb,yes,31,31 2006.201.02:00:01.32/va/03,08,usb,yes,28,29 2006.201.02:00:01.32/va/04,07,usb,yes,32,33 2006.201.02:00:01.32/va/05,04,usb,yes,28,28 2006.201.02:00:01.32/va/06,05,usb,yes,28,28 2006.201.02:00:01.32/va/07,05,usb,yes,27,28 2006.201.02:00:01.32/va/08,04,usb,yes,27,32 2006.201.02:00:01.55/valo/01,524.99,yes,locked 2006.201.02:00:01.55/valo/02,534.99,yes,locked 2006.201.02:00:01.55/valo/03,564.99,yes,locked 2006.201.02:00:01.55/valo/04,624.99,yes,locked 2006.201.02:00:01.55/valo/05,734.99,yes,locked 2006.201.02:00:01.55/valo/06,814.99,yes,locked 2006.201.02:00:01.55/valo/07,864.99,yes,locked 2006.201.02:00:01.55/valo/08,884.99,yes,locked 2006.201.02:00:02.64/vb/01,04,usb,yes,29,27 2006.201.02:00:02.64/vb/02,05,usb,yes,27,27 2006.201.02:00:02.64/vb/03,04,usb,yes,28,31 2006.201.02:00:02.64/vb/04,05,usb,yes,28,27 2006.201.02:00:02.64/vb/05,04,usb,yes,25,27 2006.201.02:00:02.64/vb/06,04,usb,yes,29,26 2006.201.02:00:02.64/vb/07,04,usb,yes,29,29 2006.201.02:00:02.64/vb/08,04,usb,yes,27,30 2006.201.02:00:02.87/vblo/01,629.99,yes,locked 2006.201.02:00:02.87/vblo/02,634.99,yes,locked 2006.201.02:00:02.87/vblo/03,649.99,yes,locked 2006.201.02:00:02.87/vblo/04,679.99,yes,locked 2006.201.02:00:02.87/vblo/05,709.99,yes,locked 2006.201.02:00:02.87/vblo/06,719.99,yes,locked 2006.201.02:00:02.87/vblo/07,734.99,yes,locked 2006.201.02:00:02.87/vblo/08,744.99,yes,locked 2006.201.02:00:03.02/vabw/8 2006.201.02:00:03.17/vbbw/8 2006.201.02:00:03.26/xfe/off,on,16.0 2006.201.02:00:03.65/ifatt/23,28,28,28 2006.201.02:00:04.04/fmout-gps/S +4.42E-07 2006.201.02:00:04.12:!2006.201.02:00:40 2006.201.02:00:40.00:data_valid=off 2006.201.02:00:40.00:"et 2006.201.02:00:40.00:!+3s 2006.201.02:00:43.02:"tape 2006.201.02:00:43.02:postob 2006.201.02:00:43.02&postob/cable 2006.201.02:00:43.03&postob/wx 2006.201.02:00:43.03&postob/clockoff 2006.201.02:00:43.11/cable/+6.4664E-03 2006.201.02:00:43.11/wx/22.92,1005.1,92 2006.201.02:00:43.19/fmout-gps/S +4.42E-07 2006.201.02:00:43.19:scan_name=201-0203,jd0607,230 2006.201.02:00:43.20:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.201.02:00:45.14#flagr#flagr/antenna,new-source 2006.201.02:00:45.14:checkk5 2006.201.02:00:45.14&checkk5/chk_autoobs=1 2006.201.02:00:45.15&checkk5/chk_autoobs=2 2006.201.02:00:45.15&checkk5/chk_autoobs=3 2006.201.02:00:45.15&checkk5/chk_autoobs=4 2006.201.02:00:45.16&checkk5/chk_obsdata=1 2006.201.02:00:45.16&checkk5/chk_obsdata=2 2006.201.02:00:45.16&checkk5/chk_obsdata=3 2006.201.02:00:45.16&checkk5/chk_obsdata=4 2006.201.02:00:45.16&checkk5/k5log=1 2006.201.02:00:45.16&checkk5/k5log=2 2006.201.02:00:45.16&checkk5/k5log=3 2006.201.02:00:45.16&checkk5/k5log=4 2006.201.02:00:45.16&checkk5/obsinfo 2006.201.02:00:45.62/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:00:46.08/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:00:46.50/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:00:46.98/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:00:47.42/chk_obsdata//k5ts1/T2010200??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.02:00:47.86/chk_obsdata//k5ts2/T2010200??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.02:00:48.29/chk_obsdata//k5ts3/T2010200??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.02:00:48.69/chk_obsdata//k5ts4/T2010200??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.02:00:49.46/k5log//k5ts1_log_newline 2006.201.02:00:50.24/k5log//k5ts2_log_newline 2006.201.02:00:51.06/k5log//k5ts3_log_newline 2006.201.02:00:51.85/k5log//k5ts4_log_newline 2006.201.02:00:51.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:00:51.87:setupk4=1 2006.201.02:00:51.87$setupk4/echo=on 2006.201.02:00:51.87$setupk4/pcalon 2006.201.02:00:51.87$pcalon/"no phase cal control is implemented here 2006.201.02:00:51.87$setupk4/"tpicd=stop 2006.201.02:00:51.87$setupk4/"rec=synch_on 2006.201.02:00:51.87$setupk4/"rec_mode=128 2006.201.02:00:51.87$setupk4/!* 2006.201.02:00:51.87$setupk4/recpk4 2006.201.02:00:51.87$recpk4/recpatch= 2006.201.02:00:51.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:00:51.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:00:51.88$setupk4/vck44 2006.201.02:00:51.88$vck44/valo=1,524.99 2006.201.02:00:51.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.02:00:51.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.02:00:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:51.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:00:51.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:00:51.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:00:51.88#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:00:51.88#ibcon#first serial, iclass 11, count 0 2006.201.02:00:51.88#ibcon#enter sib2, iclass 11, count 0 2006.201.02:00:51.88#ibcon#flushed, iclass 11, count 0 2006.201.02:00:51.88#ibcon#about to write, iclass 11, count 0 2006.201.02:00:51.88#ibcon#wrote, iclass 11, count 0 2006.201.02:00:51.88#ibcon#about to read 3, iclass 11, count 0 2006.201.02:00:51.92#ibcon#read 3, iclass 11, count 0 2006.201.02:00:51.92#ibcon#about to read 4, iclass 11, count 0 2006.201.02:00:51.92#ibcon#read 4, iclass 11, count 0 2006.201.02:00:51.92#ibcon#about to read 5, iclass 11, count 0 2006.201.02:00:51.92#ibcon#read 5, iclass 11, count 0 2006.201.02:00:51.92#ibcon#about to read 6, iclass 11, count 0 2006.201.02:00:51.92#ibcon#read 6, iclass 11, count 0 2006.201.02:00:51.92#ibcon#end of sib2, iclass 11, count 0 2006.201.02:00:51.92#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:00:51.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:00:51.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:00:51.92#ibcon#*before write, iclass 11, count 0 2006.201.02:00:51.92#ibcon#enter sib2, iclass 11, count 0 2006.201.02:00:51.92#ibcon#flushed, iclass 11, count 0 2006.201.02:00:51.92#ibcon#about to write, iclass 11, count 0 2006.201.02:00:51.92#ibcon#wrote, iclass 11, count 0 2006.201.02:00:51.92#ibcon#about to read 3, iclass 11, count 0 2006.201.02:00:51.97#ibcon#read 3, iclass 11, count 0 2006.201.02:00:51.97#ibcon#about to read 4, iclass 11, count 0 2006.201.02:00:51.97#ibcon#read 4, iclass 11, count 0 2006.201.02:00:51.97#ibcon#about to read 5, iclass 11, count 0 2006.201.02:00:51.97#ibcon#read 5, iclass 11, count 0 2006.201.02:00:51.97#ibcon#about to read 6, iclass 11, count 0 2006.201.02:00:51.97#ibcon#read 6, iclass 11, count 0 2006.201.02:00:51.97#ibcon#end of sib2, iclass 11, count 0 2006.201.02:00:51.97#ibcon#*after write, iclass 11, count 0 2006.201.02:00:51.97#ibcon#*before return 0, iclass 11, count 0 2006.201.02:00:51.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:00:51.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:00:51.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:00:51.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:00:51.97$vck44/va=1,8 2006.201.02:00:51.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.02:00:51.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.02:00:51.97#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:51.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:51.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:51.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:51.97#ibcon#enter wrdev, iclass 13, count 2 2006.201.02:00:51.97#ibcon#first serial, iclass 13, count 2 2006.201.02:00:51.97#ibcon#enter sib2, iclass 13, count 2 2006.201.02:00:51.97#ibcon#flushed, iclass 13, count 2 2006.201.02:00:51.97#ibcon#about to write, iclass 13, count 2 2006.201.02:00:51.97#ibcon#wrote, iclass 13, count 2 2006.201.02:00:51.97#ibcon#about to read 3, iclass 13, count 2 2006.201.02:00:51.99#ibcon#read 3, iclass 13, count 2 2006.201.02:00:51.99#ibcon#about to read 4, iclass 13, count 2 2006.201.02:00:51.99#ibcon#read 4, iclass 13, count 2 2006.201.02:00:51.99#ibcon#about to read 5, iclass 13, count 2 2006.201.02:00:51.99#ibcon#read 5, iclass 13, count 2 2006.201.02:00:51.99#ibcon#about to read 6, iclass 13, count 2 2006.201.02:00:51.99#ibcon#read 6, iclass 13, count 2 2006.201.02:00:51.99#ibcon#end of sib2, iclass 13, count 2 2006.201.02:00:51.99#ibcon#*mode == 0, iclass 13, count 2 2006.201.02:00:51.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.02:00:51.99#ibcon#[25=AT01-08\r\n] 2006.201.02:00:51.99#ibcon#*before write, iclass 13, count 2 2006.201.02:00:51.99#ibcon#enter sib2, iclass 13, count 2 2006.201.02:00:51.99#ibcon#flushed, iclass 13, count 2 2006.201.02:00:51.99#ibcon#about to write, iclass 13, count 2 2006.201.02:00:51.99#ibcon#wrote, iclass 13, count 2 2006.201.02:00:51.99#ibcon#about to read 3, iclass 13, count 2 2006.201.02:00:52.02#ibcon#read 3, iclass 13, count 2 2006.201.02:00:52.02#ibcon#about to read 4, iclass 13, count 2 2006.201.02:00:52.02#ibcon#read 4, iclass 13, count 2 2006.201.02:00:52.02#ibcon#about to read 5, iclass 13, count 2 2006.201.02:00:52.02#ibcon#read 5, iclass 13, count 2 2006.201.02:00:52.02#ibcon#about to read 6, iclass 13, count 2 2006.201.02:00:52.02#ibcon#read 6, iclass 13, count 2 2006.201.02:00:52.02#ibcon#end of sib2, iclass 13, count 2 2006.201.02:00:52.02#ibcon#*after write, iclass 13, count 2 2006.201.02:00:52.02#ibcon#*before return 0, iclass 13, count 2 2006.201.02:00:52.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:52.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:52.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.02:00:52.02#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:52.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:52.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:52.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:52.14#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:00:52.14#ibcon#first serial, iclass 13, count 0 2006.201.02:00:52.14#ibcon#enter sib2, iclass 13, count 0 2006.201.02:00:52.14#ibcon#flushed, iclass 13, count 0 2006.201.02:00:52.14#ibcon#about to write, iclass 13, count 0 2006.201.02:00:52.14#ibcon#wrote, iclass 13, count 0 2006.201.02:00:52.14#ibcon#about to read 3, iclass 13, count 0 2006.201.02:00:52.16#ibcon#read 3, iclass 13, count 0 2006.201.02:00:52.16#ibcon#about to read 4, iclass 13, count 0 2006.201.02:00:52.16#ibcon#read 4, iclass 13, count 0 2006.201.02:00:52.16#ibcon#about to read 5, iclass 13, count 0 2006.201.02:00:52.16#ibcon#read 5, iclass 13, count 0 2006.201.02:00:52.16#ibcon#about to read 6, iclass 13, count 0 2006.201.02:00:52.16#ibcon#read 6, iclass 13, count 0 2006.201.02:00:52.16#ibcon#end of sib2, iclass 13, count 0 2006.201.02:00:52.16#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:00:52.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:00:52.16#ibcon#[25=USB\r\n] 2006.201.02:00:52.16#ibcon#*before write, iclass 13, count 0 2006.201.02:00:52.16#ibcon#enter sib2, iclass 13, count 0 2006.201.02:00:52.16#ibcon#flushed, iclass 13, count 0 2006.201.02:00:52.16#ibcon#about to write, iclass 13, count 0 2006.201.02:00:52.16#ibcon#wrote, iclass 13, count 0 2006.201.02:00:52.16#ibcon#about to read 3, iclass 13, count 0 2006.201.02:00:52.19#ibcon#read 3, iclass 13, count 0 2006.201.02:00:52.19#ibcon#about to read 4, iclass 13, count 0 2006.201.02:00:52.19#ibcon#read 4, iclass 13, count 0 2006.201.02:00:52.19#ibcon#about to read 5, iclass 13, count 0 2006.201.02:00:52.19#ibcon#read 5, iclass 13, count 0 2006.201.02:00:52.19#ibcon#about to read 6, iclass 13, count 0 2006.201.02:00:52.19#ibcon#read 6, iclass 13, count 0 2006.201.02:00:52.19#ibcon#end of sib2, iclass 13, count 0 2006.201.02:00:52.19#ibcon#*after write, iclass 13, count 0 2006.201.02:00:52.19#ibcon#*before return 0, iclass 13, count 0 2006.201.02:00:52.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:52.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:52.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:00:52.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:00:52.19$vck44/valo=2,534.99 2006.201.02:00:52.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.02:00:52.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.02:00:52.19#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:52.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:52.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:52.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:52.19#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:00:52.19#ibcon#first serial, iclass 15, count 0 2006.201.02:00:52.19#ibcon#enter sib2, iclass 15, count 0 2006.201.02:00:52.19#ibcon#flushed, iclass 15, count 0 2006.201.02:00:52.19#ibcon#about to write, iclass 15, count 0 2006.201.02:00:52.19#ibcon#wrote, iclass 15, count 0 2006.201.02:00:52.19#ibcon#about to read 3, iclass 15, count 0 2006.201.02:00:52.21#ibcon#read 3, iclass 15, count 0 2006.201.02:00:52.21#ibcon#about to read 4, iclass 15, count 0 2006.201.02:00:52.21#ibcon#read 4, iclass 15, count 0 2006.201.02:00:52.21#ibcon#about to read 5, iclass 15, count 0 2006.201.02:00:52.21#ibcon#read 5, iclass 15, count 0 2006.201.02:00:52.21#ibcon#about to read 6, iclass 15, count 0 2006.201.02:00:52.21#ibcon#read 6, iclass 15, count 0 2006.201.02:00:52.21#ibcon#end of sib2, iclass 15, count 0 2006.201.02:00:52.21#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:00:52.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:00:52.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:00:52.21#ibcon#*before write, iclass 15, count 0 2006.201.02:00:52.21#ibcon#enter sib2, iclass 15, count 0 2006.201.02:00:52.21#ibcon#flushed, iclass 15, count 0 2006.201.02:00:52.21#ibcon#about to write, iclass 15, count 0 2006.201.02:00:52.21#ibcon#wrote, iclass 15, count 0 2006.201.02:00:52.21#ibcon#about to read 3, iclass 15, count 0 2006.201.02:00:52.26#ibcon#read 3, iclass 15, count 0 2006.201.02:00:52.26#ibcon#about to read 4, iclass 15, count 0 2006.201.02:00:52.26#ibcon#read 4, iclass 15, count 0 2006.201.02:00:52.26#ibcon#about to read 5, iclass 15, count 0 2006.201.02:00:52.26#ibcon#read 5, iclass 15, count 0 2006.201.02:00:52.26#ibcon#about to read 6, iclass 15, count 0 2006.201.02:00:52.26#ibcon#read 6, iclass 15, count 0 2006.201.02:00:52.26#ibcon#end of sib2, iclass 15, count 0 2006.201.02:00:52.26#ibcon#*after write, iclass 15, count 0 2006.201.02:00:52.26#ibcon#*before return 0, iclass 15, count 0 2006.201.02:00:52.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:52.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:52.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:00:52.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:00:52.26$vck44/va=2,7 2006.201.02:00:52.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.02:00:52.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.02:00:52.26#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:52.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:52.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:52.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:52.31#ibcon#enter wrdev, iclass 17, count 2 2006.201.02:00:52.31#ibcon#first serial, iclass 17, count 2 2006.201.02:00:52.31#ibcon#enter sib2, iclass 17, count 2 2006.201.02:00:52.31#ibcon#flushed, iclass 17, count 2 2006.201.02:00:52.31#ibcon#about to write, iclass 17, count 2 2006.201.02:00:52.31#ibcon#wrote, iclass 17, count 2 2006.201.02:00:52.31#ibcon#about to read 3, iclass 17, count 2 2006.201.02:00:52.33#ibcon#read 3, iclass 17, count 2 2006.201.02:00:52.33#ibcon#about to read 4, iclass 17, count 2 2006.201.02:00:52.33#ibcon#read 4, iclass 17, count 2 2006.201.02:00:52.33#ibcon#about to read 5, iclass 17, count 2 2006.201.02:00:52.33#ibcon#read 5, iclass 17, count 2 2006.201.02:00:52.33#ibcon#about to read 6, iclass 17, count 2 2006.201.02:00:52.33#ibcon#read 6, iclass 17, count 2 2006.201.02:00:52.33#ibcon#end of sib2, iclass 17, count 2 2006.201.02:00:52.33#ibcon#*mode == 0, iclass 17, count 2 2006.201.02:00:52.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.02:00:52.33#ibcon#[25=AT02-07\r\n] 2006.201.02:00:52.33#ibcon#*before write, iclass 17, count 2 2006.201.02:00:52.33#ibcon#enter sib2, iclass 17, count 2 2006.201.02:00:52.33#ibcon#flushed, iclass 17, count 2 2006.201.02:00:52.33#ibcon#about to write, iclass 17, count 2 2006.201.02:00:52.33#ibcon#wrote, iclass 17, count 2 2006.201.02:00:52.33#ibcon#about to read 3, iclass 17, count 2 2006.201.02:00:52.36#ibcon#read 3, iclass 17, count 2 2006.201.02:00:52.36#ibcon#about to read 4, iclass 17, count 2 2006.201.02:00:52.36#ibcon#read 4, iclass 17, count 2 2006.201.02:00:52.36#ibcon#about to read 5, iclass 17, count 2 2006.201.02:00:52.36#ibcon#read 5, iclass 17, count 2 2006.201.02:00:52.36#ibcon#about to read 6, iclass 17, count 2 2006.201.02:00:52.36#ibcon#read 6, iclass 17, count 2 2006.201.02:00:52.36#ibcon#end of sib2, iclass 17, count 2 2006.201.02:00:52.36#ibcon#*after write, iclass 17, count 2 2006.201.02:00:52.36#ibcon#*before return 0, iclass 17, count 2 2006.201.02:00:52.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:52.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:52.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.02:00:52.36#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:52.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:52.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:52.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:52.48#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:00:52.48#ibcon#first serial, iclass 17, count 0 2006.201.02:00:52.48#ibcon#enter sib2, iclass 17, count 0 2006.201.02:00:52.48#ibcon#flushed, iclass 17, count 0 2006.201.02:00:52.48#ibcon#about to write, iclass 17, count 0 2006.201.02:00:52.48#ibcon#wrote, iclass 17, count 0 2006.201.02:00:52.48#ibcon#about to read 3, iclass 17, count 0 2006.201.02:00:52.50#ibcon#read 3, iclass 17, count 0 2006.201.02:00:52.50#ibcon#about to read 4, iclass 17, count 0 2006.201.02:00:52.50#ibcon#read 4, iclass 17, count 0 2006.201.02:00:52.50#ibcon#about to read 5, iclass 17, count 0 2006.201.02:00:52.50#ibcon#read 5, iclass 17, count 0 2006.201.02:00:52.50#ibcon#about to read 6, iclass 17, count 0 2006.201.02:00:52.50#ibcon#read 6, iclass 17, count 0 2006.201.02:00:52.50#ibcon#end of sib2, iclass 17, count 0 2006.201.02:00:52.50#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:00:52.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:00:52.50#ibcon#[25=USB\r\n] 2006.201.02:00:52.50#ibcon#*before write, iclass 17, count 0 2006.201.02:00:52.50#ibcon#enter sib2, iclass 17, count 0 2006.201.02:00:52.50#ibcon#flushed, iclass 17, count 0 2006.201.02:00:52.50#ibcon#about to write, iclass 17, count 0 2006.201.02:00:52.50#ibcon#wrote, iclass 17, count 0 2006.201.02:00:52.50#ibcon#about to read 3, iclass 17, count 0 2006.201.02:00:52.53#ibcon#read 3, iclass 17, count 0 2006.201.02:00:52.53#ibcon#about to read 4, iclass 17, count 0 2006.201.02:00:52.53#ibcon#read 4, iclass 17, count 0 2006.201.02:00:52.53#ibcon#about to read 5, iclass 17, count 0 2006.201.02:00:52.53#ibcon#read 5, iclass 17, count 0 2006.201.02:00:52.53#ibcon#about to read 6, iclass 17, count 0 2006.201.02:00:52.53#ibcon#read 6, iclass 17, count 0 2006.201.02:00:52.53#ibcon#end of sib2, iclass 17, count 0 2006.201.02:00:52.53#ibcon#*after write, iclass 17, count 0 2006.201.02:00:52.53#ibcon#*before return 0, iclass 17, count 0 2006.201.02:00:52.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:52.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:52.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:00:52.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:00:52.53$vck44/valo=3,564.99 2006.201.02:00:52.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.02:00:52.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.02:00:52.53#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:52.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:52.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:52.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:52.53#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:00:52.53#ibcon#first serial, iclass 19, count 0 2006.201.02:00:52.53#ibcon#enter sib2, iclass 19, count 0 2006.201.02:00:52.53#ibcon#flushed, iclass 19, count 0 2006.201.02:00:52.53#ibcon#about to write, iclass 19, count 0 2006.201.02:00:52.53#ibcon#wrote, iclass 19, count 0 2006.201.02:00:52.53#ibcon#about to read 3, iclass 19, count 0 2006.201.02:00:52.55#ibcon#read 3, iclass 19, count 0 2006.201.02:00:52.55#ibcon#about to read 4, iclass 19, count 0 2006.201.02:00:52.55#ibcon#read 4, iclass 19, count 0 2006.201.02:00:52.55#ibcon#about to read 5, iclass 19, count 0 2006.201.02:00:52.55#ibcon#read 5, iclass 19, count 0 2006.201.02:00:52.55#ibcon#about to read 6, iclass 19, count 0 2006.201.02:00:52.55#ibcon#read 6, iclass 19, count 0 2006.201.02:00:52.55#ibcon#end of sib2, iclass 19, count 0 2006.201.02:00:52.55#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:00:52.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:00:52.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:00:52.55#ibcon#*before write, iclass 19, count 0 2006.201.02:00:52.55#ibcon#enter sib2, iclass 19, count 0 2006.201.02:00:52.55#ibcon#flushed, iclass 19, count 0 2006.201.02:00:52.55#ibcon#about to write, iclass 19, count 0 2006.201.02:00:52.55#ibcon#wrote, iclass 19, count 0 2006.201.02:00:52.55#ibcon#about to read 3, iclass 19, count 0 2006.201.02:00:52.60#ibcon#read 3, iclass 19, count 0 2006.201.02:00:52.60#ibcon#about to read 4, iclass 19, count 0 2006.201.02:00:52.60#ibcon#read 4, iclass 19, count 0 2006.201.02:00:52.60#ibcon#about to read 5, iclass 19, count 0 2006.201.02:00:52.60#ibcon#read 5, iclass 19, count 0 2006.201.02:00:52.60#ibcon#about to read 6, iclass 19, count 0 2006.201.02:00:52.60#ibcon#read 6, iclass 19, count 0 2006.201.02:00:52.60#ibcon#end of sib2, iclass 19, count 0 2006.201.02:00:52.60#ibcon#*after write, iclass 19, count 0 2006.201.02:00:52.60#ibcon#*before return 0, iclass 19, count 0 2006.201.02:00:52.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:52.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:52.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:00:52.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:00:52.60$vck44/va=3,8 2006.201.02:00:52.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.02:00:52.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.02:00:52.60#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:52.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:52.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:52.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:52.65#ibcon#enter wrdev, iclass 21, count 2 2006.201.02:00:52.65#ibcon#first serial, iclass 21, count 2 2006.201.02:00:52.65#ibcon#enter sib2, iclass 21, count 2 2006.201.02:00:52.65#ibcon#flushed, iclass 21, count 2 2006.201.02:00:52.65#ibcon#about to write, iclass 21, count 2 2006.201.02:00:52.65#ibcon#wrote, iclass 21, count 2 2006.201.02:00:52.65#ibcon#about to read 3, iclass 21, count 2 2006.201.02:00:52.67#ibcon#read 3, iclass 21, count 2 2006.201.02:00:52.67#ibcon#about to read 4, iclass 21, count 2 2006.201.02:00:52.67#ibcon#read 4, iclass 21, count 2 2006.201.02:00:52.67#ibcon#about to read 5, iclass 21, count 2 2006.201.02:00:52.67#ibcon#read 5, iclass 21, count 2 2006.201.02:00:52.67#ibcon#about to read 6, iclass 21, count 2 2006.201.02:00:52.67#ibcon#read 6, iclass 21, count 2 2006.201.02:00:52.67#ibcon#end of sib2, iclass 21, count 2 2006.201.02:00:52.67#ibcon#*mode == 0, iclass 21, count 2 2006.201.02:00:52.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.02:00:52.67#ibcon#[25=AT03-08\r\n] 2006.201.02:00:52.67#ibcon#*before write, iclass 21, count 2 2006.201.02:00:52.67#ibcon#enter sib2, iclass 21, count 2 2006.201.02:00:52.67#ibcon#flushed, iclass 21, count 2 2006.201.02:00:52.67#ibcon#about to write, iclass 21, count 2 2006.201.02:00:52.67#ibcon#wrote, iclass 21, count 2 2006.201.02:00:52.67#ibcon#about to read 3, iclass 21, count 2 2006.201.02:00:52.70#ibcon#read 3, iclass 21, count 2 2006.201.02:00:52.70#ibcon#about to read 4, iclass 21, count 2 2006.201.02:00:52.70#ibcon#read 4, iclass 21, count 2 2006.201.02:00:52.70#ibcon#about to read 5, iclass 21, count 2 2006.201.02:00:52.70#ibcon#read 5, iclass 21, count 2 2006.201.02:00:52.70#ibcon#about to read 6, iclass 21, count 2 2006.201.02:00:52.70#ibcon#read 6, iclass 21, count 2 2006.201.02:00:52.70#ibcon#end of sib2, iclass 21, count 2 2006.201.02:00:52.70#ibcon#*after write, iclass 21, count 2 2006.201.02:00:52.70#ibcon#*before return 0, iclass 21, count 2 2006.201.02:00:52.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:52.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:52.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.02:00:52.70#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:52.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:52.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:52.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:52.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:00:52.82#ibcon#first serial, iclass 21, count 0 2006.201.02:00:52.82#ibcon#enter sib2, iclass 21, count 0 2006.201.02:00:52.82#ibcon#flushed, iclass 21, count 0 2006.201.02:00:52.82#ibcon#about to write, iclass 21, count 0 2006.201.02:00:52.82#ibcon#wrote, iclass 21, count 0 2006.201.02:00:52.82#ibcon#about to read 3, iclass 21, count 0 2006.201.02:00:52.84#ibcon#read 3, iclass 21, count 0 2006.201.02:00:52.84#ibcon#about to read 4, iclass 21, count 0 2006.201.02:00:52.84#ibcon#read 4, iclass 21, count 0 2006.201.02:00:52.84#ibcon#about to read 5, iclass 21, count 0 2006.201.02:00:52.84#ibcon#read 5, iclass 21, count 0 2006.201.02:00:52.84#ibcon#about to read 6, iclass 21, count 0 2006.201.02:00:52.84#ibcon#read 6, iclass 21, count 0 2006.201.02:00:52.84#ibcon#end of sib2, iclass 21, count 0 2006.201.02:00:52.84#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:00:52.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:00:52.84#ibcon#[25=USB\r\n] 2006.201.02:00:52.84#ibcon#*before write, iclass 21, count 0 2006.201.02:00:52.84#ibcon#enter sib2, iclass 21, count 0 2006.201.02:00:52.84#ibcon#flushed, iclass 21, count 0 2006.201.02:00:52.84#ibcon#about to write, iclass 21, count 0 2006.201.02:00:52.84#ibcon#wrote, iclass 21, count 0 2006.201.02:00:52.84#ibcon#about to read 3, iclass 21, count 0 2006.201.02:00:52.87#ibcon#read 3, iclass 21, count 0 2006.201.02:00:52.87#ibcon#about to read 4, iclass 21, count 0 2006.201.02:00:52.87#ibcon#read 4, iclass 21, count 0 2006.201.02:00:52.87#ibcon#about to read 5, iclass 21, count 0 2006.201.02:00:52.87#ibcon#read 5, iclass 21, count 0 2006.201.02:00:52.87#ibcon#about to read 6, iclass 21, count 0 2006.201.02:00:52.87#ibcon#read 6, iclass 21, count 0 2006.201.02:00:52.87#ibcon#end of sib2, iclass 21, count 0 2006.201.02:00:52.87#ibcon#*after write, iclass 21, count 0 2006.201.02:00:52.87#ibcon#*before return 0, iclass 21, count 0 2006.201.02:00:52.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:52.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:52.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:00:52.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:00:52.87$vck44/valo=4,624.99 2006.201.02:00:52.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.02:00:52.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.02:00:52.87#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:52.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:52.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:52.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:52.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:00:52.87#ibcon#first serial, iclass 23, count 0 2006.201.02:00:52.87#ibcon#enter sib2, iclass 23, count 0 2006.201.02:00:52.87#ibcon#flushed, iclass 23, count 0 2006.201.02:00:52.87#ibcon#about to write, iclass 23, count 0 2006.201.02:00:52.87#ibcon#wrote, iclass 23, count 0 2006.201.02:00:52.87#ibcon#about to read 3, iclass 23, count 0 2006.201.02:00:52.89#ibcon#read 3, iclass 23, count 0 2006.201.02:00:52.89#ibcon#about to read 4, iclass 23, count 0 2006.201.02:00:52.89#ibcon#read 4, iclass 23, count 0 2006.201.02:00:52.89#ibcon#about to read 5, iclass 23, count 0 2006.201.02:00:52.89#ibcon#read 5, iclass 23, count 0 2006.201.02:00:52.89#ibcon#about to read 6, iclass 23, count 0 2006.201.02:00:52.89#ibcon#read 6, iclass 23, count 0 2006.201.02:00:52.89#ibcon#end of sib2, iclass 23, count 0 2006.201.02:00:52.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:00:52.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:00:52.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:00:52.89#ibcon#*before write, iclass 23, count 0 2006.201.02:00:52.89#ibcon#enter sib2, iclass 23, count 0 2006.201.02:00:52.89#ibcon#flushed, iclass 23, count 0 2006.201.02:00:52.89#ibcon#about to write, iclass 23, count 0 2006.201.02:00:52.89#ibcon#wrote, iclass 23, count 0 2006.201.02:00:52.89#ibcon#about to read 3, iclass 23, count 0 2006.201.02:00:52.93#ibcon#read 3, iclass 23, count 0 2006.201.02:00:52.93#ibcon#about to read 4, iclass 23, count 0 2006.201.02:00:52.93#ibcon#read 4, iclass 23, count 0 2006.201.02:00:52.93#ibcon#about to read 5, iclass 23, count 0 2006.201.02:00:52.93#ibcon#read 5, iclass 23, count 0 2006.201.02:00:52.93#ibcon#about to read 6, iclass 23, count 0 2006.201.02:00:52.93#ibcon#read 6, iclass 23, count 0 2006.201.02:00:52.93#ibcon#end of sib2, iclass 23, count 0 2006.201.02:00:52.93#ibcon#*after write, iclass 23, count 0 2006.201.02:00:52.93#ibcon#*before return 0, iclass 23, count 0 2006.201.02:00:52.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:52.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:52.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:00:52.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:00:52.93$vck44/va=4,7 2006.201.02:00:52.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.02:00:52.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.02:00:52.93#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:52.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:52.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:52.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:52.99#ibcon#enter wrdev, iclass 25, count 2 2006.201.02:00:52.99#ibcon#first serial, iclass 25, count 2 2006.201.02:00:52.99#ibcon#enter sib2, iclass 25, count 2 2006.201.02:00:52.99#ibcon#flushed, iclass 25, count 2 2006.201.02:00:52.99#ibcon#about to write, iclass 25, count 2 2006.201.02:00:52.99#ibcon#wrote, iclass 25, count 2 2006.201.02:00:52.99#ibcon#about to read 3, iclass 25, count 2 2006.201.02:00:53.01#ibcon#read 3, iclass 25, count 2 2006.201.02:00:53.01#ibcon#about to read 4, iclass 25, count 2 2006.201.02:00:53.01#ibcon#read 4, iclass 25, count 2 2006.201.02:00:53.01#ibcon#about to read 5, iclass 25, count 2 2006.201.02:00:53.01#ibcon#read 5, iclass 25, count 2 2006.201.02:00:53.01#ibcon#about to read 6, iclass 25, count 2 2006.201.02:00:53.01#ibcon#read 6, iclass 25, count 2 2006.201.02:00:53.01#ibcon#end of sib2, iclass 25, count 2 2006.201.02:00:53.01#ibcon#*mode == 0, iclass 25, count 2 2006.201.02:00:53.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.02:00:53.01#ibcon#[25=AT04-07\r\n] 2006.201.02:00:53.01#ibcon#*before write, iclass 25, count 2 2006.201.02:00:53.01#ibcon#enter sib2, iclass 25, count 2 2006.201.02:00:53.01#ibcon#flushed, iclass 25, count 2 2006.201.02:00:53.01#ibcon#about to write, iclass 25, count 2 2006.201.02:00:53.01#ibcon#wrote, iclass 25, count 2 2006.201.02:00:53.01#ibcon#about to read 3, iclass 25, count 2 2006.201.02:00:53.04#ibcon#read 3, iclass 25, count 2 2006.201.02:00:53.04#ibcon#about to read 4, iclass 25, count 2 2006.201.02:00:53.04#ibcon#read 4, iclass 25, count 2 2006.201.02:00:53.04#ibcon#about to read 5, iclass 25, count 2 2006.201.02:00:53.04#ibcon#read 5, iclass 25, count 2 2006.201.02:00:53.04#ibcon#about to read 6, iclass 25, count 2 2006.201.02:00:53.04#ibcon#read 6, iclass 25, count 2 2006.201.02:00:53.04#ibcon#end of sib2, iclass 25, count 2 2006.201.02:00:53.04#ibcon#*after write, iclass 25, count 2 2006.201.02:00:53.04#ibcon#*before return 0, iclass 25, count 2 2006.201.02:00:53.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:53.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:53.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.02:00:53.04#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:53.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:53.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:53.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:53.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.02:00:53.16#ibcon#first serial, iclass 25, count 0 2006.201.02:00:53.16#ibcon#enter sib2, iclass 25, count 0 2006.201.02:00:53.16#ibcon#flushed, iclass 25, count 0 2006.201.02:00:53.16#ibcon#about to write, iclass 25, count 0 2006.201.02:00:53.16#ibcon#wrote, iclass 25, count 0 2006.201.02:00:53.16#ibcon#about to read 3, iclass 25, count 0 2006.201.02:00:53.18#ibcon#read 3, iclass 25, count 0 2006.201.02:00:53.18#ibcon#about to read 4, iclass 25, count 0 2006.201.02:00:53.18#ibcon#read 4, iclass 25, count 0 2006.201.02:00:53.18#ibcon#about to read 5, iclass 25, count 0 2006.201.02:00:53.18#ibcon#read 5, iclass 25, count 0 2006.201.02:00:53.18#ibcon#about to read 6, iclass 25, count 0 2006.201.02:00:53.18#ibcon#read 6, iclass 25, count 0 2006.201.02:00:53.18#ibcon#end of sib2, iclass 25, count 0 2006.201.02:00:53.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.02:00:53.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.02:00:53.18#ibcon#[25=USB\r\n] 2006.201.02:00:53.18#ibcon#*before write, iclass 25, count 0 2006.201.02:00:53.18#ibcon#enter sib2, iclass 25, count 0 2006.201.02:00:53.18#ibcon#flushed, iclass 25, count 0 2006.201.02:00:53.18#ibcon#about to write, iclass 25, count 0 2006.201.02:00:53.18#ibcon#wrote, iclass 25, count 0 2006.201.02:00:53.18#ibcon#about to read 3, iclass 25, count 0 2006.201.02:00:53.21#ibcon#read 3, iclass 25, count 0 2006.201.02:00:53.21#ibcon#about to read 4, iclass 25, count 0 2006.201.02:00:53.21#ibcon#read 4, iclass 25, count 0 2006.201.02:00:53.21#ibcon#about to read 5, iclass 25, count 0 2006.201.02:00:53.21#ibcon#read 5, iclass 25, count 0 2006.201.02:00:53.21#ibcon#about to read 6, iclass 25, count 0 2006.201.02:00:53.21#ibcon#read 6, iclass 25, count 0 2006.201.02:00:53.21#ibcon#end of sib2, iclass 25, count 0 2006.201.02:00:53.21#ibcon#*after write, iclass 25, count 0 2006.201.02:00:53.21#ibcon#*before return 0, iclass 25, count 0 2006.201.02:00:53.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:53.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:53.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.02:00:53.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.02:00:53.21$vck44/valo=5,734.99 2006.201.02:00:53.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.02:00:53.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.02:00:53.21#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:53.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:53.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:53.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:53.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:00:53.21#ibcon#first serial, iclass 27, count 0 2006.201.02:00:53.21#ibcon#enter sib2, iclass 27, count 0 2006.201.02:00:53.21#ibcon#flushed, iclass 27, count 0 2006.201.02:00:53.21#ibcon#about to write, iclass 27, count 0 2006.201.02:00:53.21#ibcon#wrote, iclass 27, count 0 2006.201.02:00:53.21#ibcon#about to read 3, iclass 27, count 0 2006.201.02:00:53.23#ibcon#read 3, iclass 27, count 0 2006.201.02:00:53.23#ibcon#about to read 4, iclass 27, count 0 2006.201.02:00:53.23#ibcon#read 4, iclass 27, count 0 2006.201.02:00:53.23#ibcon#about to read 5, iclass 27, count 0 2006.201.02:00:53.23#ibcon#read 5, iclass 27, count 0 2006.201.02:00:53.23#ibcon#about to read 6, iclass 27, count 0 2006.201.02:00:53.23#ibcon#read 6, iclass 27, count 0 2006.201.02:00:53.23#ibcon#end of sib2, iclass 27, count 0 2006.201.02:00:53.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:00:53.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:00:53.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:00:53.23#ibcon#*before write, iclass 27, count 0 2006.201.02:00:53.23#ibcon#enter sib2, iclass 27, count 0 2006.201.02:00:53.23#ibcon#flushed, iclass 27, count 0 2006.201.02:00:53.23#ibcon#about to write, iclass 27, count 0 2006.201.02:00:53.23#ibcon#wrote, iclass 27, count 0 2006.201.02:00:53.23#ibcon#about to read 3, iclass 27, count 0 2006.201.02:00:53.27#ibcon#read 3, iclass 27, count 0 2006.201.02:00:53.27#ibcon#about to read 4, iclass 27, count 0 2006.201.02:00:53.27#ibcon#read 4, iclass 27, count 0 2006.201.02:00:53.27#ibcon#about to read 5, iclass 27, count 0 2006.201.02:00:53.27#ibcon#read 5, iclass 27, count 0 2006.201.02:00:53.27#ibcon#about to read 6, iclass 27, count 0 2006.201.02:00:53.27#ibcon#read 6, iclass 27, count 0 2006.201.02:00:53.27#ibcon#end of sib2, iclass 27, count 0 2006.201.02:00:53.27#ibcon#*after write, iclass 27, count 0 2006.201.02:00:53.27#ibcon#*before return 0, iclass 27, count 0 2006.201.02:00:53.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:53.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:53.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:00:53.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:00:53.27$vck44/va=5,4 2006.201.02:00:53.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.02:00:53.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.02:00:53.27#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:53.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:53.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:53.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:53.33#ibcon#enter wrdev, iclass 29, count 2 2006.201.02:00:53.33#ibcon#first serial, iclass 29, count 2 2006.201.02:00:53.33#ibcon#enter sib2, iclass 29, count 2 2006.201.02:00:53.33#ibcon#flushed, iclass 29, count 2 2006.201.02:00:53.33#ibcon#about to write, iclass 29, count 2 2006.201.02:00:53.33#ibcon#wrote, iclass 29, count 2 2006.201.02:00:53.33#ibcon#about to read 3, iclass 29, count 2 2006.201.02:00:53.35#ibcon#read 3, iclass 29, count 2 2006.201.02:00:53.35#ibcon#about to read 4, iclass 29, count 2 2006.201.02:00:53.35#ibcon#read 4, iclass 29, count 2 2006.201.02:00:53.35#ibcon#about to read 5, iclass 29, count 2 2006.201.02:00:53.35#ibcon#read 5, iclass 29, count 2 2006.201.02:00:53.35#ibcon#about to read 6, iclass 29, count 2 2006.201.02:00:53.35#ibcon#read 6, iclass 29, count 2 2006.201.02:00:53.35#ibcon#end of sib2, iclass 29, count 2 2006.201.02:00:53.35#ibcon#*mode == 0, iclass 29, count 2 2006.201.02:00:53.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.02:00:53.35#ibcon#[25=AT05-04\r\n] 2006.201.02:00:53.35#ibcon#*before write, iclass 29, count 2 2006.201.02:00:53.35#ibcon#enter sib2, iclass 29, count 2 2006.201.02:00:53.35#ibcon#flushed, iclass 29, count 2 2006.201.02:00:53.35#ibcon#about to write, iclass 29, count 2 2006.201.02:00:53.35#ibcon#wrote, iclass 29, count 2 2006.201.02:00:53.35#ibcon#about to read 3, iclass 29, count 2 2006.201.02:00:53.38#ibcon#read 3, iclass 29, count 2 2006.201.02:00:53.38#ibcon#about to read 4, iclass 29, count 2 2006.201.02:00:53.38#ibcon#read 4, iclass 29, count 2 2006.201.02:00:53.38#ibcon#about to read 5, iclass 29, count 2 2006.201.02:00:53.38#ibcon#read 5, iclass 29, count 2 2006.201.02:00:53.38#ibcon#about to read 6, iclass 29, count 2 2006.201.02:00:53.38#ibcon#read 6, iclass 29, count 2 2006.201.02:00:53.38#ibcon#end of sib2, iclass 29, count 2 2006.201.02:00:53.38#ibcon#*after write, iclass 29, count 2 2006.201.02:00:53.38#ibcon#*before return 0, iclass 29, count 2 2006.201.02:00:53.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:53.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:53.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.02:00:53.38#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:53.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:53.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:53.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:53.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:00:53.50#ibcon#first serial, iclass 29, count 0 2006.201.02:00:53.50#ibcon#enter sib2, iclass 29, count 0 2006.201.02:00:53.50#ibcon#flushed, iclass 29, count 0 2006.201.02:00:53.50#ibcon#about to write, iclass 29, count 0 2006.201.02:00:53.50#ibcon#wrote, iclass 29, count 0 2006.201.02:00:53.50#ibcon#about to read 3, iclass 29, count 0 2006.201.02:00:53.52#ibcon#read 3, iclass 29, count 0 2006.201.02:00:53.52#ibcon#about to read 4, iclass 29, count 0 2006.201.02:00:53.52#ibcon#read 4, iclass 29, count 0 2006.201.02:00:53.52#ibcon#about to read 5, iclass 29, count 0 2006.201.02:00:53.52#ibcon#read 5, iclass 29, count 0 2006.201.02:00:53.52#ibcon#about to read 6, iclass 29, count 0 2006.201.02:00:53.52#ibcon#read 6, iclass 29, count 0 2006.201.02:00:53.52#ibcon#end of sib2, iclass 29, count 0 2006.201.02:00:53.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:00:53.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:00:53.52#ibcon#[25=USB\r\n] 2006.201.02:00:53.52#ibcon#*before write, iclass 29, count 0 2006.201.02:00:53.52#ibcon#enter sib2, iclass 29, count 0 2006.201.02:00:53.52#ibcon#flushed, iclass 29, count 0 2006.201.02:00:53.52#ibcon#about to write, iclass 29, count 0 2006.201.02:00:53.52#ibcon#wrote, iclass 29, count 0 2006.201.02:00:53.52#ibcon#about to read 3, iclass 29, count 0 2006.201.02:00:53.55#ibcon#read 3, iclass 29, count 0 2006.201.02:00:53.55#ibcon#about to read 4, iclass 29, count 0 2006.201.02:00:53.55#ibcon#read 4, iclass 29, count 0 2006.201.02:00:53.55#ibcon#about to read 5, iclass 29, count 0 2006.201.02:00:53.55#ibcon#read 5, iclass 29, count 0 2006.201.02:00:53.55#ibcon#about to read 6, iclass 29, count 0 2006.201.02:00:53.55#ibcon#read 6, iclass 29, count 0 2006.201.02:00:53.55#ibcon#end of sib2, iclass 29, count 0 2006.201.02:00:53.55#ibcon#*after write, iclass 29, count 0 2006.201.02:00:53.55#ibcon#*before return 0, iclass 29, count 0 2006.201.02:00:53.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:53.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:53.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:00:53.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:00:53.55$vck44/valo=6,814.99 2006.201.02:00:53.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.02:00:53.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.02:00:53.55#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:53.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:53.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:53.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:53.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:00:53.55#ibcon#first serial, iclass 31, count 0 2006.201.02:00:53.55#ibcon#enter sib2, iclass 31, count 0 2006.201.02:00:53.55#ibcon#flushed, iclass 31, count 0 2006.201.02:00:53.55#ibcon#about to write, iclass 31, count 0 2006.201.02:00:53.55#ibcon#wrote, iclass 31, count 0 2006.201.02:00:53.55#ibcon#about to read 3, iclass 31, count 0 2006.201.02:00:53.57#ibcon#read 3, iclass 31, count 0 2006.201.02:00:53.57#ibcon#about to read 4, iclass 31, count 0 2006.201.02:00:53.57#ibcon#read 4, iclass 31, count 0 2006.201.02:00:53.57#ibcon#about to read 5, iclass 31, count 0 2006.201.02:00:53.57#ibcon#read 5, iclass 31, count 0 2006.201.02:00:53.57#ibcon#about to read 6, iclass 31, count 0 2006.201.02:00:53.57#ibcon#read 6, iclass 31, count 0 2006.201.02:00:53.57#ibcon#end of sib2, iclass 31, count 0 2006.201.02:00:53.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:00:53.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:00:53.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:00:53.57#ibcon#*before write, iclass 31, count 0 2006.201.02:00:53.57#ibcon#enter sib2, iclass 31, count 0 2006.201.02:00:53.57#ibcon#flushed, iclass 31, count 0 2006.201.02:00:53.57#ibcon#about to write, iclass 31, count 0 2006.201.02:00:53.57#ibcon#wrote, iclass 31, count 0 2006.201.02:00:53.57#ibcon#about to read 3, iclass 31, count 0 2006.201.02:00:53.61#ibcon#read 3, iclass 31, count 0 2006.201.02:00:53.61#ibcon#about to read 4, iclass 31, count 0 2006.201.02:00:53.61#ibcon#read 4, iclass 31, count 0 2006.201.02:00:53.61#ibcon#about to read 5, iclass 31, count 0 2006.201.02:00:53.61#ibcon#read 5, iclass 31, count 0 2006.201.02:00:53.61#ibcon#about to read 6, iclass 31, count 0 2006.201.02:00:53.61#ibcon#read 6, iclass 31, count 0 2006.201.02:00:53.61#ibcon#end of sib2, iclass 31, count 0 2006.201.02:00:53.61#ibcon#*after write, iclass 31, count 0 2006.201.02:00:53.61#ibcon#*before return 0, iclass 31, count 0 2006.201.02:00:53.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:53.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:53.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:00:53.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:00:53.61$vck44/va=6,5 2006.201.02:00:53.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.02:00:53.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.02:00:53.61#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:53.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:53.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:53.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:53.67#ibcon#enter wrdev, iclass 33, count 2 2006.201.02:00:53.67#ibcon#first serial, iclass 33, count 2 2006.201.02:00:53.67#ibcon#enter sib2, iclass 33, count 2 2006.201.02:00:53.67#ibcon#flushed, iclass 33, count 2 2006.201.02:00:53.67#ibcon#about to write, iclass 33, count 2 2006.201.02:00:53.67#ibcon#wrote, iclass 33, count 2 2006.201.02:00:53.67#ibcon#about to read 3, iclass 33, count 2 2006.201.02:00:53.69#ibcon#read 3, iclass 33, count 2 2006.201.02:00:53.69#ibcon#about to read 4, iclass 33, count 2 2006.201.02:00:53.69#ibcon#read 4, iclass 33, count 2 2006.201.02:00:53.69#ibcon#about to read 5, iclass 33, count 2 2006.201.02:00:53.69#ibcon#read 5, iclass 33, count 2 2006.201.02:00:53.69#ibcon#about to read 6, iclass 33, count 2 2006.201.02:00:53.69#ibcon#read 6, iclass 33, count 2 2006.201.02:00:53.69#ibcon#end of sib2, iclass 33, count 2 2006.201.02:00:53.69#ibcon#*mode == 0, iclass 33, count 2 2006.201.02:00:53.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.02:00:53.69#ibcon#[25=AT06-05\r\n] 2006.201.02:00:53.69#ibcon#*before write, iclass 33, count 2 2006.201.02:00:53.69#ibcon#enter sib2, iclass 33, count 2 2006.201.02:00:53.69#ibcon#flushed, iclass 33, count 2 2006.201.02:00:53.69#ibcon#about to write, iclass 33, count 2 2006.201.02:00:53.69#ibcon#wrote, iclass 33, count 2 2006.201.02:00:53.69#ibcon#about to read 3, iclass 33, count 2 2006.201.02:00:53.72#ibcon#read 3, iclass 33, count 2 2006.201.02:00:53.72#ibcon#about to read 4, iclass 33, count 2 2006.201.02:00:53.72#ibcon#read 4, iclass 33, count 2 2006.201.02:00:53.72#ibcon#about to read 5, iclass 33, count 2 2006.201.02:00:53.72#ibcon#read 5, iclass 33, count 2 2006.201.02:00:53.72#ibcon#about to read 6, iclass 33, count 2 2006.201.02:00:53.72#ibcon#read 6, iclass 33, count 2 2006.201.02:00:53.72#ibcon#end of sib2, iclass 33, count 2 2006.201.02:00:53.72#ibcon#*after write, iclass 33, count 2 2006.201.02:00:53.72#ibcon#*before return 0, iclass 33, count 2 2006.201.02:00:53.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:53.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:53.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.02:00:53.72#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:53.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:53.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:53.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:53.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:00:53.84#ibcon#first serial, iclass 33, count 0 2006.201.02:00:53.84#ibcon#enter sib2, iclass 33, count 0 2006.201.02:00:53.84#ibcon#flushed, iclass 33, count 0 2006.201.02:00:53.84#ibcon#about to write, iclass 33, count 0 2006.201.02:00:53.84#ibcon#wrote, iclass 33, count 0 2006.201.02:00:53.84#ibcon#about to read 3, iclass 33, count 0 2006.201.02:00:53.86#ibcon#read 3, iclass 33, count 0 2006.201.02:00:53.86#ibcon#about to read 4, iclass 33, count 0 2006.201.02:00:53.86#ibcon#read 4, iclass 33, count 0 2006.201.02:00:53.86#ibcon#about to read 5, iclass 33, count 0 2006.201.02:00:53.86#ibcon#read 5, iclass 33, count 0 2006.201.02:00:53.86#ibcon#about to read 6, iclass 33, count 0 2006.201.02:00:53.86#ibcon#read 6, iclass 33, count 0 2006.201.02:00:53.86#ibcon#end of sib2, iclass 33, count 0 2006.201.02:00:53.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:00:53.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:00:53.86#ibcon#[25=USB\r\n] 2006.201.02:00:53.86#ibcon#*before write, iclass 33, count 0 2006.201.02:00:53.86#ibcon#enter sib2, iclass 33, count 0 2006.201.02:00:53.86#ibcon#flushed, iclass 33, count 0 2006.201.02:00:53.86#ibcon#about to write, iclass 33, count 0 2006.201.02:00:53.86#ibcon#wrote, iclass 33, count 0 2006.201.02:00:53.86#ibcon#about to read 3, iclass 33, count 0 2006.201.02:00:53.89#ibcon#read 3, iclass 33, count 0 2006.201.02:00:53.89#ibcon#about to read 4, iclass 33, count 0 2006.201.02:00:53.89#ibcon#read 4, iclass 33, count 0 2006.201.02:00:53.89#ibcon#about to read 5, iclass 33, count 0 2006.201.02:00:53.89#ibcon#read 5, iclass 33, count 0 2006.201.02:00:53.89#ibcon#about to read 6, iclass 33, count 0 2006.201.02:00:53.89#ibcon#read 6, iclass 33, count 0 2006.201.02:00:53.89#ibcon#end of sib2, iclass 33, count 0 2006.201.02:00:53.89#ibcon#*after write, iclass 33, count 0 2006.201.02:00:53.89#ibcon#*before return 0, iclass 33, count 0 2006.201.02:00:53.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:53.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:53.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:00:53.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:00:53.89$vck44/valo=7,864.99 2006.201.02:00:53.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.02:00:53.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.02:00:53.89#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:53.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:53.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:53.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:53.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:00:53.89#ibcon#first serial, iclass 35, count 0 2006.201.02:00:53.89#ibcon#enter sib2, iclass 35, count 0 2006.201.02:00:53.89#ibcon#flushed, iclass 35, count 0 2006.201.02:00:53.89#ibcon#about to write, iclass 35, count 0 2006.201.02:00:53.89#ibcon#wrote, iclass 35, count 0 2006.201.02:00:53.89#ibcon#about to read 3, iclass 35, count 0 2006.201.02:00:53.91#ibcon#read 3, iclass 35, count 0 2006.201.02:00:53.91#ibcon#about to read 4, iclass 35, count 0 2006.201.02:00:53.91#ibcon#read 4, iclass 35, count 0 2006.201.02:00:53.91#ibcon#about to read 5, iclass 35, count 0 2006.201.02:00:53.91#ibcon#read 5, iclass 35, count 0 2006.201.02:00:53.91#ibcon#about to read 6, iclass 35, count 0 2006.201.02:00:53.91#ibcon#read 6, iclass 35, count 0 2006.201.02:00:53.91#ibcon#end of sib2, iclass 35, count 0 2006.201.02:00:53.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:00:53.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:00:53.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:00:53.91#ibcon#*before write, iclass 35, count 0 2006.201.02:00:53.91#ibcon#enter sib2, iclass 35, count 0 2006.201.02:00:53.91#ibcon#flushed, iclass 35, count 0 2006.201.02:00:53.91#ibcon#about to write, iclass 35, count 0 2006.201.02:00:53.91#ibcon#wrote, iclass 35, count 0 2006.201.02:00:53.91#ibcon#about to read 3, iclass 35, count 0 2006.201.02:00:53.95#ibcon#read 3, iclass 35, count 0 2006.201.02:00:53.95#ibcon#about to read 4, iclass 35, count 0 2006.201.02:00:53.95#ibcon#read 4, iclass 35, count 0 2006.201.02:00:53.95#ibcon#about to read 5, iclass 35, count 0 2006.201.02:00:53.95#ibcon#read 5, iclass 35, count 0 2006.201.02:00:53.95#ibcon#about to read 6, iclass 35, count 0 2006.201.02:00:53.95#ibcon#read 6, iclass 35, count 0 2006.201.02:00:53.95#ibcon#end of sib2, iclass 35, count 0 2006.201.02:00:53.95#ibcon#*after write, iclass 35, count 0 2006.201.02:00:53.95#ibcon#*before return 0, iclass 35, count 0 2006.201.02:00:53.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:53.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:53.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:00:53.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:00:53.95$vck44/va=7,5 2006.201.02:00:53.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.02:00:53.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.02:00:53.95#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:53.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:54.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:54.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:54.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.02:00:54.01#ibcon#first serial, iclass 37, count 2 2006.201.02:00:54.01#ibcon#enter sib2, iclass 37, count 2 2006.201.02:00:54.01#ibcon#flushed, iclass 37, count 2 2006.201.02:00:54.01#ibcon#about to write, iclass 37, count 2 2006.201.02:00:54.01#ibcon#wrote, iclass 37, count 2 2006.201.02:00:54.01#ibcon#about to read 3, iclass 37, count 2 2006.201.02:00:54.03#ibcon#read 3, iclass 37, count 2 2006.201.02:00:54.03#ibcon#about to read 4, iclass 37, count 2 2006.201.02:00:54.03#ibcon#read 4, iclass 37, count 2 2006.201.02:00:54.03#ibcon#about to read 5, iclass 37, count 2 2006.201.02:00:54.03#ibcon#read 5, iclass 37, count 2 2006.201.02:00:54.03#ibcon#about to read 6, iclass 37, count 2 2006.201.02:00:54.03#ibcon#read 6, iclass 37, count 2 2006.201.02:00:54.03#ibcon#end of sib2, iclass 37, count 2 2006.201.02:00:54.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.02:00:54.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.02:00:54.03#ibcon#[25=AT07-05\r\n] 2006.201.02:00:54.03#ibcon#*before write, iclass 37, count 2 2006.201.02:00:54.03#ibcon#enter sib2, iclass 37, count 2 2006.201.02:00:54.03#ibcon#flushed, iclass 37, count 2 2006.201.02:00:54.03#ibcon#about to write, iclass 37, count 2 2006.201.02:00:54.03#ibcon#wrote, iclass 37, count 2 2006.201.02:00:54.03#ibcon#about to read 3, iclass 37, count 2 2006.201.02:00:54.06#ibcon#read 3, iclass 37, count 2 2006.201.02:00:54.06#ibcon#about to read 4, iclass 37, count 2 2006.201.02:00:54.06#ibcon#read 4, iclass 37, count 2 2006.201.02:00:54.06#ibcon#about to read 5, iclass 37, count 2 2006.201.02:00:54.06#ibcon#read 5, iclass 37, count 2 2006.201.02:00:54.06#ibcon#about to read 6, iclass 37, count 2 2006.201.02:00:54.06#ibcon#read 6, iclass 37, count 2 2006.201.02:00:54.06#ibcon#end of sib2, iclass 37, count 2 2006.201.02:00:54.06#ibcon#*after write, iclass 37, count 2 2006.201.02:00:54.06#ibcon#*before return 0, iclass 37, count 2 2006.201.02:00:54.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:54.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:54.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.02:00:54.06#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:54.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:54.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:54.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:54.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:00:54.18#ibcon#first serial, iclass 37, count 0 2006.201.02:00:54.18#ibcon#enter sib2, iclass 37, count 0 2006.201.02:00:54.18#ibcon#flushed, iclass 37, count 0 2006.201.02:00:54.18#ibcon#about to write, iclass 37, count 0 2006.201.02:00:54.18#ibcon#wrote, iclass 37, count 0 2006.201.02:00:54.18#ibcon#about to read 3, iclass 37, count 0 2006.201.02:00:54.21#ibcon#read 3, iclass 37, count 0 2006.201.02:00:54.21#ibcon#about to read 4, iclass 37, count 0 2006.201.02:00:54.21#ibcon#read 4, iclass 37, count 0 2006.201.02:00:54.21#ibcon#about to read 5, iclass 37, count 0 2006.201.02:00:54.21#ibcon#read 5, iclass 37, count 0 2006.201.02:00:54.21#ibcon#about to read 6, iclass 37, count 0 2006.201.02:00:54.21#ibcon#read 6, iclass 37, count 0 2006.201.02:00:54.21#ibcon#end of sib2, iclass 37, count 0 2006.201.02:00:54.21#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:00:54.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:00:54.21#ibcon#[25=USB\r\n] 2006.201.02:00:54.21#ibcon#*before write, iclass 37, count 0 2006.201.02:00:54.21#ibcon#enter sib2, iclass 37, count 0 2006.201.02:00:54.21#ibcon#flushed, iclass 37, count 0 2006.201.02:00:54.21#ibcon#about to write, iclass 37, count 0 2006.201.02:00:54.21#ibcon#wrote, iclass 37, count 0 2006.201.02:00:54.21#ibcon#about to read 3, iclass 37, count 0 2006.201.02:00:54.24#ibcon#read 3, iclass 37, count 0 2006.201.02:00:54.24#ibcon#about to read 4, iclass 37, count 0 2006.201.02:00:54.24#ibcon#read 4, iclass 37, count 0 2006.201.02:00:54.24#ibcon#about to read 5, iclass 37, count 0 2006.201.02:00:54.24#ibcon#read 5, iclass 37, count 0 2006.201.02:00:54.24#ibcon#about to read 6, iclass 37, count 0 2006.201.02:00:54.24#ibcon#read 6, iclass 37, count 0 2006.201.02:00:54.24#ibcon#end of sib2, iclass 37, count 0 2006.201.02:00:54.24#ibcon#*after write, iclass 37, count 0 2006.201.02:00:54.24#ibcon#*before return 0, iclass 37, count 0 2006.201.02:00:54.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:54.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:54.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:00:54.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:00:54.24$vck44/valo=8,884.99 2006.201.02:00:54.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.02:00:54.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.02:00:54.24#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:54.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:54.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:54.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:54.24#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:00:54.24#ibcon#first serial, iclass 39, count 0 2006.201.02:00:54.24#ibcon#enter sib2, iclass 39, count 0 2006.201.02:00:54.24#ibcon#flushed, iclass 39, count 0 2006.201.02:00:54.24#ibcon#about to write, iclass 39, count 0 2006.201.02:00:54.24#ibcon#wrote, iclass 39, count 0 2006.201.02:00:54.24#ibcon#about to read 3, iclass 39, count 0 2006.201.02:00:54.26#ibcon#read 3, iclass 39, count 0 2006.201.02:00:54.26#ibcon#about to read 4, iclass 39, count 0 2006.201.02:00:54.26#ibcon#read 4, iclass 39, count 0 2006.201.02:00:54.26#ibcon#about to read 5, iclass 39, count 0 2006.201.02:00:54.26#ibcon#read 5, iclass 39, count 0 2006.201.02:00:54.26#ibcon#about to read 6, iclass 39, count 0 2006.201.02:00:54.26#ibcon#read 6, iclass 39, count 0 2006.201.02:00:54.26#ibcon#end of sib2, iclass 39, count 0 2006.201.02:00:54.26#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:00:54.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:00:54.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:00:54.26#ibcon#*before write, iclass 39, count 0 2006.201.02:00:54.26#ibcon#enter sib2, iclass 39, count 0 2006.201.02:00:54.26#ibcon#flushed, iclass 39, count 0 2006.201.02:00:54.26#ibcon#about to write, iclass 39, count 0 2006.201.02:00:54.26#ibcon#wrote, iclass 39, count 0 2006.201.02:00:54.26#ibcon#about to read 3, iclass 39, count 0 2006.201.02:00:54.30#ibcon#read 3, iclass 39, count 0 2006.201.02:00:54.30#ibcon#about to read 4, iclass 39, count 0 2006.201.02:00:54.30#ibcon#read 4, iclass 39, count 0 2006.201.02:00:54.30#ibcon#about to read 5, iclass 39, count 0 2006.201.02:00:54.30#ibcon#read 5, iclass 39, count 0 2006.201.02:00:54.30#ibcon#about to read 6, iclass 39, count 0 2006.201.02:00:54.30#ibcon#read 6, iclass 39, count 0 2006.201.02:00:54.30#ibcon#end of sib2, iclass 39, count 0 2006.201.02:00:54.30#ibcon#*after write, iclass 39, count 0 2006.201.02:00:54.30#ibcon#*before return 0, iclass 39, count 0 2006.201.02:00:54.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:54.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:54.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:00:54.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:00:54.30$vck44/va=8,4 2006.201.02:00:54.30#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.02:00:54.30#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.02:00:54.30#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:54.30#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:54.36#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:54.36#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:54.36#ibcon#enter wrdev, iclass 2, count 2 2006.201.02:00:54.36#ibcon#first serial, iclass 2, count 2 2006.201.02:00:54.36#ibcon#enter sib2, iclass 2, count 2 2006.201.02:00:54.36#ibcon#flushed, iclass 2, count 2 2006.201.02:00:54.36#ibcon#about to write, iclass 2, count 2 2006.201.02:00:54.36#ibcon#wrote, iclass 2, count 2 2006.201.02:00:54.36#ibcon#about to read 3, iclass 2, count 2 2006.201.02:00:54.38#ibcon#read 3, iclass 2, count 2 2006.201.02:00:54.38#ibcon#about to read 4, iclass 2, count 2 2006.201.02:00:54.38#ibcon#read 4, iclass 2, count 2 2006.201.02:00:54.38#ibcon#about to read 5, iclass 2, count 2 2006.201.02:00:54.38#ibcon#read 5, iclass 2, count 2 2006.201.02:00:54.38#ibcon#about to read 6, iclass 2, count 2 2006.201.02:00:54.38#ibcon#read 6, iclass 2, count 2 2006.201.02:00:54.38#ibcon#end of sib2, iclass 2, count 2 2006.201.02:00:54.38#ibcon#*mode == 0, iclass 2, count 2 2006.201.02:00:54.38#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.02:00:54.38#ibcon#[25=AT08-04\r\n] 2006.201.02:00:54.38#ibcon#*before write, iclass 2, count 2 2006.201.02:00:54.38#ibcon#enter sib2, iclass 2, count 2 2006.201.02:00:54.38#ibcon#flushed, iclass 2, count 2 2006.201.02:00:54.38#ibcon#about to write, iclass 2, count 2 2006.201.02:00:54.38#ibcon#wrote, iclass 2, count 2 2006.201.02:00:54.38#ibcon#about to read 3, iclass 2, count 2 2006.201.02:00:54.41#ibcon#read 3, iclass 2, count 2 2006.201.02:00:54.41#ibcon#about to read 4, iclass 2, count 2 2006.201.02:00:54.41#ibcon#read 4, iclass 2, count 2 2006.201.02:00:54.41#ibcon#about to read 5, iclass 2, count 2 2006.201.02:00:54.41#ibcon#read 5, iclass 2, count 2 2006.201.02:00:54.41#ibcon#about to read 6, iclass 2, count 2 2006.201.02:00:54.41#ibcon#read 6, iclass 2, count 2 2006.201.02:00:54.41#ibcon#end of sib2, iclass 2, count 2 2006.201.02:00:54.41#ibcon#*after write, iclass 2, count 2 2006.201.02:00:54.41#ibcon#*before return 0, iclass 2, count 2 2006.201.02:00:54.41#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:54.41#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:54.41#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.02:00:54.41#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:54.41#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:54.53#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:54.53#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:54.53#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:00:54.53#ibcon#first serial, iclass 2, count 0 2006.201.02:00:54.53#ibcon#enter sib2, iclass 2, count 0 2006.201.02:00:54.53#ibcon#flushed, iclass 2, count 0 2006.201.02:00:54.53#ibcon#about to write, iclass 2, count 0 2006.201.02:00:54.53#ibcon#wrote, iclass 2, count 0 2006.201.02:00:54.53#ibcon#about to read 3, iclass 2, count 0 2006.201.02:00:54.55#ibcon#read 3, iclass 2, count 0 2006.201.02:00:54.55#ibcon#about to read 4, iclass 2, count 0 2006.201.02:00:54.55#ibcon#read 4, iclass 2, count 0 2006.201.02:00:54.55#ibcon#about to read 5, iclass 2, count 0 2006.201.02:00:54.55#ibcon#read 5, iclass 2, count 0 2006.201.02:00:54.55#ibcon#about to read 6, iclass 2, count 0 2006.201.02:00:54.55#ibcon#read 6, iclass 2, count 0 2006.201.02:00:54.55#ibcon#end of sib2, iclass 2, count 0 2006.201.02:00:54.55#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:00:54.55#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:00:54.55#ibcon#[25=USB\r\n] 2006.201.02:00:54.55#ibcon#*before write, iclass 2, count 0 2006.201.02:00:54.55#ibcon#enter sib2, iclass 2, count 0 2006.201.02:00:54.55#ibcon#flushed, iclass 2, count 0 2006.201.02:00:54.55#ibcon#about to write, iclass 2, count 0 2006.201.02:00:54.55#ibcon#wrote, iclass 2, count 0 2006.201.02:00:54.55#ibcon#about to read 3, iclass 2, count 0 2006.201.02:00:54.57#abcon#<5=/05 2.6 4.2 22.92 921005.1\r\n> 2006.201.02:00:54.58#ibcon#read 3, iclass 2, count 0 2006.201.02:00:54.58#ibcon#about to read 4, iclass 2, count 0 2006.201.02:00:54.58#ibcon#read 4, iclass 2, count 0 2006.201.02:00:54.58#ibcon#about to read 5, iclass 2, count 0 2006.201.02:00:54.58#ibcon#read 5, iclass 2, count 0 2006.201.02:00:54.58#ibcon#about to read 6, iclass 2, count 0 2006.201.02:00:54.58#ibcon#read 6, iclass 2, count 0 2006.201.02:00:54.58#ibcon#end of sib2, iclass 2, count 0 2006.201.02:00:54.58#ibcon#*after write, iclass 2, count 0 2006.201.02:00:54.58#ibcon#*before return 0, iclass 2, count 0 2006.201.02:00:54.58#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:54.58#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:54.58#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:00:54.58#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:00:54.58$vck44/vblo=1,629.99 2006.201.02:00:54.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.02:00:54.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.02:00:54.58#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:54.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:00:54.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:00:54.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:00:54.58#ibcon#enter wrdev, iclass 10, count 0 2006.201.02:00:54.58#ibcon#first serial, iclass 10, count 0 2006.201.02:00:54.58#ibcon#enter sib2, iclass 10, count 0 2006.201.02:00:54.58#ibcon#flushed, iclass 10, count 0 2006.201.02:00:54.58#ibcon#about to write, iclass 10, count 0 2006.201.02:00:54.58#ibcon#wrote, iclass 10, count 0 2006.201.02:00:54.58#ibcon#about to read 3, iclass 10, count 0 2006.201.02:00:54.59#abcon#{5=INTERFACE CLEAR} 2006.201.02:00:54.60#ibcon#read 3, iclass 10, count 0 2006.201.02:00:54.60#ibcon#about to read 4, iclass 10, count 0 2006.201.02:00:54.60#ibcon#read 4, iclass 10, count 0 2006.201.02:00:54.60#ibcon#about to read 5, iclass 10, count 0 2006.201.02:00:54.60#ibcon#read 5, iclass 10, count 0 2006.201.02:00:54.60#ibcon#about to read 6, iclass 10, count 0 2006.201.02:00:54.60#ibcon#read 6, iclass 10, count 0 2006.201.02:00:54.60#ibcon#end of sib2, iclass 10, count 0 2006.201.02:00:54.60#ibcon#*mode == 0, iclass 10, count 0 2006.201.02:00:54.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.02:00:54.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:00:54.60#ibcon#*before write, iclass 10, count 0 2006.201.02:00:54.60#ibcon#enter sib2, iclass 10, count 0 2006.201.02:00:54.60#ibcon#flushed, iclass 10, count 0 2006.201.02:00:54.60#ibcon#about to write, iclass 10, count 0 2006.201.02:00:54.60#ibcon#wrote, iclass 10, count 0 2006.201.02:00:54.60#ibcon#about to read 3, iclass 10, count 0 2006.201.02:00:54.64#ibcon#read 3, iclass 10, count 0 2006.201.02:00:54.64#ibcon#about to read 4, iclass 10, count 0 2006.201.02:00:54.64#ibcon#read 4, iclass 10, count 0 2006.201.02:00:54.64#ibcon#about to read 5, iclass 10, count 0 2006.201.02:00:54.64#ibcon#read 5, iclass 10, count 0 2006.201.02:00:54.64#ibcon#about to read 6, iclass 10, count 0 2006.201.02:00:54.64#ibcon#read 6, iclass 10, count 0 2006.201.02:00:54.64#ibcon#end of sib2, iclass 10, count 0 2006.201.02:00:54.64#ibcon#*after write, iclass 10, count 0 2006.201.02:00:54.64#ibcon#*before return 0, iclass 10, count 0 2006.201.02:00:54.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:00:54.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:00:54.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.02:00:54.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.02:00:54.64$vck44/vb=1,4 2006.201.02:00:54.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.02:00:54.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.02:00:54.64#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:54.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:54.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:54.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:54.64#ibcon#enter wrdev, iclass 13, count 2 2006.201.02:00:54.64#ibcon#first serial, iclass 13, count 2 2006.201.02:00:54.64#ibcon#enter sib2, iclass 13, count 2 2006.201.02:00:54.64#ibcon#flushed, iclass 13, count 2 2006.201.02:00:54.64#ibcon#about to write, iclass 13, count 2 2006.201.02:00:54.64#ibcon#wrote, iclass 13, count 2 2006.201.02:00:54.64#ibcon#about to read 3, iclass 13, count 2 2006.201.02:00:54.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:00:54.66#ibcon#read 3, iclass 13, count 2 2006.201.02:00:54.66#ibcon#about to read 4, iclass 13, count 2 2006.201.02:00:54.66#ibcon#read 4, iclass 13, count 2 2006.201.02:00:54.66#ibcon#about to read 5, iclass 13, count 2 2006.201.02:00:54.66#ibcon#read 5, iclass 13, count 2 2006.201.02:00:54.66#ibcon#about to read 6, iclass 13, count 2 2006.201.02:00:54.66#ibcon#read 6, iclass 13, count 2 2006.201.02:00:54.66#ibcon#end of sib2, iclass 13, count 2 2006.201.02:00:54.66#ibcon#*mode == 0, iclass 13, count 2 2006.201.02:00:54.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.02:00:54.66#ibcon#[27=AT01-04\r\n] 2006.201.02:00:54.66#ibcon#*before write, iclass 13, count 2 2006.201.02:00:54.66#ibcon#enter sib2, iclass 13, count 2 2006.201.02:00:54.66#ibcon#flushed, iclass 13, count 2 2006.201.02:00:54.66#ibcon#about to write, iclass 13, count 2 2006.201.02:00:54.66#ibcon#wrote, iclass 13, count 2 2006.201.02:00:54.66#ibcon#about to read 3, iclass 13, count 2 2006.201.02:00:54.69#ibcon#read 3, iclass 13, count 2 2006.201.02:00:54.69#ibcon#about to read 4, iclass 13, count 2 2006.201.02:00:54.69#ibcon#read 4, iclass 13, count 2 2006.201.02:00:54.69#ibcon#about to read 5, iclass 13, count 2 2006.201.02:00:54.69#ibcon#read 5, iclass 13, count 2 2006.201.02:00:54.69#ibcon#about to read 6, iclass 13, count 2 2006.201.02:00:54.69#ibcon#read 6, iclass 13, count 2 2006.201.02:00:54.69#ibcon#end of sib2, iclass 13, count 2 2006.201.02:00:54.69#ibcon#*after write, iclass 13, count 2 2006.201.02:00:54.69#ibcon#*before return 0, iclass 13, count 2 2006.201.02:00:54.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:54.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:00:54.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.02:00:54.69#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:54.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:54.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:54.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:54.81#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:00:54.81#ibcon#first serial, iclass 13, count 0 2006.201.02:00:54.81#ibcon#enter sib2, iclass 13, count 0 2006.201.02:00:54.81#ibcon#flushed, iclass 13, count 0 2006.201.02:00:54.81#ibcon#about to write, iclass 13, count 0 2006.201.02:00:54.81#ibcon#wrote, iclass 13, count 0 2006.201.02:00:54.81#ibcon#about to read 3, iclass 13, count 0 2006.201.02:00:54.83#ibcon#read 3, iclass 13, count 0 2006.201.02:00:54.83#ibcon#about to read 4, iclass 13, count 0 2006.201.02:00:54.83#ibcon#read 4, iclass 13, count 0 2006.201.02:00:54.83#ibcon#about to read 5, iclass 13, count 0 2006.201.02:00:54.83#ibcon#read 5, iclass 13, count 0 2006.201.02:00:54.83#ibcon#about to read 6, iclass 13, count 0 2006.201.02:00:54.83#ibcon#read 6, iclass 13, count 0 2006.201.02:00:54.83#ibcon#end of sib2, iclass 13, count 0 2006.201.02:00:54.83#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:00:54.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:00:54.83#ibcon#[27=USB\r\n] 2006.201.02:00:54.83#ibcon#*before write, iclass 13, count 0 2006.201.02:00:54.83#ibcon#enter sib2, iclass 13, count 0 2006.201.02:00:54.83#ibcon#flushed, iclass 13, count 0 2006.201.02:00:54.83#ibcon#about to write, iclass 13, count 0 2006.201.02:00:54.83#ibcon#wrote, iclass 13, count 0 2006.201.02:00:54.83#ibcon#about to read 3, iclass 13, count 0 2006.201.02:00:54.86#ibcon#read 3, iclass 13, count 0 2006.201.02:00:54.86#ibcon#about to read 4, iclass 13, count 0 2006.201.02:00:54.86#ibcon#read 4, iclass 13, count 0 2006.201.02:00:54.86#ibcon#about to read 5, iclass 13, count 0 2006.201.02:00:54.86#ibcon#read 5, iclass 13, count 0 2006.201.02:00:54.86#ibcon#about to read 6, iclass 13, count 0 2006.201.02:00:54.86#ibcon#read 6, iclass 13, count 0 2006.201.02:00:54.86#ibcon#end of sib2, iclass 13, count 0 2006.201.02:00:54.86#ibcon#*after write, iclass 13, count 0 2006.201.02:00:54.86#ibcon#*before return 0, iclass 13, count 0 2006.201.02:00:54.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:54.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:00:54.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:00:54.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:00:54.86$vck44/vblo=2,634.99 2006.201.02:00:54.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.02:00:54.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.02:00:54.86#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:54.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:54.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:54.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:54.86#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:00:54.86#ibcon#first serial, iclass 15, count 0 2006.201.02:00:54.86#ibcon#enter sib2, iclass 15, count 0 2006.201.02:00:54.86#ibcon#flushed, iclass 15, count 0 2006.201.02:00:54.86#ibcon#about to write, iclass 15, count 0 2006.201.02:00:54.86#ibcon#wrote, iclass 15, count 0 2006.201.02:00:54.86#ibcon#about to read 3, iclass 15, count 0 2006.201.02:00:54.88#ibcon#read 3, iclass 15, count 0 2006.201.02:00:54.88#ibcon#about to read 4, iclass 15, count 0 2006.201.02:00:54.88#ibcon#read 4, iclass 15, count 0 2006.201.02:00:54.88#ibcon#about to read 5, iclass 15, count 0 2006.201.02:00:54.88#ibcon#read 5, iclass 15, count 0 2006.201.02:00:54.88#ibcon#about to read 6, iclass 15, count 0 2006.201.02:00:54.88#ibcon#read 6, iclass 15, count 0 2006.201.02:00:54.88#ibcon#end of sib2, iclass 15, count 0 2006.201.02:00:54.88#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:00:54.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:00:54.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:00:54.88#ibcon#*before write, iclass 15, count 0 2006.201.02:00:54.88#ibcon#enter sib2, iclass 15, count 0 2006.201.02:00:54.88#ibcon#flushed, iclass 15, count 0 2006.201.02:00:54.88#ibcon#about to write, iclass 15, count 0 2006.201.02:00:54.88#ibcon#wrote, iclass 15, count 0 2006.201.02:00:54.88#ibcon#about to read 3, iclass 15, count 0 2006.201.02:00:54.92#ibcon#read 3, iclass 15, count 0 2006.201.02:00:54.92#ibcon#about to read 4, iclass 15, count 0 2006.201.02:00:54.92#ibcon#read 4, iclass 15, count 0 2006.201.02:00:54.92#ibcon#about to read 5, iclass 15, count 0 2006.201.02:00:54.92#ibcon#read 5, iclass 15, count 0 2006.201.02:00:54.92#ibcon#about to read 6, iclass 15, count 0 2006.201.02:00:54.92#ibcon#read 6, iclass 15, count 0 2006.201.02:00:54.92#ibcon#end of sib2, iclass 15, count 0 2006.201.02:00:54.92#ibcon#*after write, iclass 15, count 0 2006.201.02:00:54.92#ibcon#*before return 0, iclass 15, count 0 2006.201.02:00:54.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:54.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:00:54.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:00:54.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:00:54.92$vck44/vb=2,5 2006.201.02:00:54.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.02:00:54.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.02:00:54.92#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:54.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:54.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:54.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:54.98#ibcon#enter wrdev, iclass 17, count 2 2006.201.02:00:54.98#ibcon#first serial, iclass 17, count 2 2006.201.02:00:54.98#ibcon#enter sib2, iclass 17, count 2 2006.201.02:00:54.98#ibcon#flushed, iclass 17, count 2 2006.201.02:00:54.98#ibcon#about to write, iclass 17, count 2 2006.201.02:00:54.98#ibcon#wrote, iclass 17, count 2 2006.201.02:00:54.98#ibcon#about to read 3, iclass 17, count 2 2006.201.02:00:55.00#ibcon#read 3, iclass 17, count 2 2006.201.02:00:55.00#ibcon#about to read 4, iclass 17, count 2 2006.201.02:00:55.00#ibcon#read 4, iclass 17, count 2 2006.201.02:00:55.00#ibcon#about to read 5, iclass 17, count 2 2006.201.02:00:55.00#ibcon#read 5, iclass 17, count 2 2006.201.02:00:55.00#ibcon#about to read 6, iclass 17, count 2 2006.201.02:00:55.00#ibcon#read 6, iclass 17, count 2 2006.201.02:00:55.00#ibcon#end of sib2, iclass 17, count 2 2006.201.02:00:55.00#ibcon#*mode == 0, iclass 17, count 2 2006.201.02:00:55.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.02:00:55.00#ibcon#[27=AT02-05\r\n] 2006.201.02:00:55.00#ibcon#*before write, iclass 17, count 2 2006.201.02:00:55.00#ibcon#enter sib2, iclass 17, count 2 2006.201.02:00:55.00#ibcon#flushed, iclass 17, count 2 2006.201.02:00:55.00#ibcon#about to write, iclass 17, count 2 2006.201.02:00:55.00#ibcon#wrote, iclass 17, count 2 2006.201.02:00:55.00#ibcon#about to read 3, iclass 17, count 2 2006.201.02:00:55.03#ibcon#read 3, iclass 17, count 2 2006.201.02:00:55.03#ibcon#about to read 4, iclass 17, count 2 2006.201.02:00:55.03#ibcon#read 4, iclass 17, count 2 2006.201.02:00:55.03#ibcon#about to read 5, iclass 17, count 2 2006.201.02:00:55.03#ibcon#read 5, iclass 17, count 2 2006.201.02:00:55.03#ibcon#about to read 6, iclass 17, count 2 2006.201.02:00:55.03#ibcon#read 6, iclass 17, count 2 2006.201.02:00:55.03#ibcon#end of sib2, iclass 17, count 2 2006.201.02:00:55.03#ibcon#*after write, iclass 17, count 2 2006.201.02:00:55.03#ibcon#*before return 0, iclass 17, count 2 2006.201.02:00:55.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:55.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:00:55.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.02:00:55.03#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:55.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:55.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:55.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:55.15#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:00:55.15#ibcon#first serial, iclass 17, count 0 2006.201.02:00:55.15#ibcon#enter sib2, iclass 17, count 0 2006.201.02:00:55.15#ibcon#flushed, iclass 17, count 0 2006.201.02:00:55.15#ibcon#about to write, iclass 17, count 0 2006.201.02:00:55.15#ibcon#wrote, iclass 17, count 0 2006.201.02:00:55.15#ibcon#about to read 3, iclass 17, count 0 2006.201.02:00:55.17#ibcon#read 3, iclass 17, count 0 2006.201.02:00:55.17#ibcon#about to read 4, iclass 17, count 0 2006.201.02:00:55.17#ibcon#read 4, iclass 17, count 0 2006.201.02:00:55.17#ibcon#about to read 5, iclass 17, count 0 2006.201.02:00:55.17#ibcon#read 5, iclass 17, count 0 2006.201.02:00:55.17#ibcon#about to read 6, iclass 17, count 0 2006.201.02:00:55.17#ibcon#read 6, iclass 17, count 0 2006.201.02:00:55.17#ibcon#end of sib2, iclass 17, count 0 2006.201.02:00:55.17#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:00:55.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:00:55.17#ibcon#[27=USB\r\n] 2006.201.02:00:55.17#ibcon#*before write, iclass 17, count 0 2006.201.02:00:55.17#ibcon#enter sib2, iclass 17, count 0 2006.201.02:00:55.17#ibcon#flushed, iclass 17, count 0 2006.201.02:00:55.17#ibcon#about to write, iclass 17, count 0 2006.201.02:00:55.17#ibcon#wrote, iclass 17, count 0 2006.201.02:00:55.17#ibcon#about to read 3, iclass 17, count 0 2006.201.02:00:55.20#ibcon#read 3, iclass 17, count 0 2006.201.02:00:55.20#ibcon#about to read 4, iclass 17, count 0 2006.201.02:00:55.20#ibcon#read 4, iclass 17, count 0 2006.201.02:00:55.20#ibcon#about to read 5, iclass 17, count 0 2006.201.02:00:55.20#ibcon#read 5, iclass 17, count 0 2006.201.02:00:55.20#ibcon#about to read 6, iclass 17, count 0 2006.201.02:00:55.20#ibcon#read 6, iclass 17, count 0 2006.201.02:00:55.20#ibcon#end of sib2, iclass 17, count 0 2006.201.02:00:55.20#ibcon#*after write, iclass 17, count 0 2006.201.02:00:55.20#ibcon#*before return 0, iclass 17, count 0 2006.201.02:00:55.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:55.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:00:55.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:00:55.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:00:55.20$vck44/vblo=3,649.99 2006.201.02:00:55.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.02:00:55.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.02:00:55.20#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:55.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:55.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:55.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:55.20#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:00:55.20#ibcon#first serial, iclass 19, count 0 2006.201.02:00:55.20#ibcon#enter sib2, iclass 19, count 0 2006.201.02:00:55.20#ibcon#flushed, iclass 19, count 0 2006.201.02:00:55.20#ibcon#about to write, iclass 19, count 0 2006.201.02:00:55.20#ibcon#wrote, iclass 19, count 0 2006.201.02:00:55.20#ibcon#about to read 3, iclass 19, count 0 2006.201.02:00:55.22#ibcon#read 3, iclass 19, count 0 2006.201.02:00:55.22#ibcon#about to read 4, iclass 19, count 0 2006.201.02:00:55.22#ibcon#read 4, iclass 19, count 0 2006.201.02:00:55.22#ibcon#about to read 5, iclass 19, count 0 2006.201.02:00:55.22#ibcon#read 5, iclass 19, count 0 2006.201.02:00:55.22#ibcon#about to read 6, iclass 19, count 0 2006.201.02:00:55.22#ibcon#read 6, iclass 19, count 0 2006.201.02:00:55.22#ibcon#end of sib2, iclass 19, count 0 2006.201.02:00:55.22#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:00:55.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:00:55.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:00:55.22#ibcon#*before write, iclass 19, count 0 2006.201.02:00:55.22#ibcon#enter sib2, iclass 19, count 0 2006.201.02:00:55.22#ibcon#flushed, iclass 19, count 0 2006.201.02:00:55.22#ibcon#about to write, iclass 19, count 0 2006.201.02:00:55.22#ibcon#wrote, iclass 19, count 0 2006.201.02:00:55.22#ibcon#about to read 3, iclass 19, count 0 2006.201.02:00:55.26#ibcon#read 3, iclass 19, count 0 2006.201.02:00:55.26#ibcon#about to read 4, iclass 19, count 0 2006.201.02:00:55.26#ibcon#read 4, iclass 19, count 0 2006.201.02:00:55.26#ibcon#about to read 5, iclass 19, count 0 2006.201.02:00:55.26#ibcon#read 5, iclass 19, count 0 2006.201.02:00:55.26#ibcon#about to read 6, iclass 19, count 0 2006.201.02:00:55.26#ibcon#read 6, iclass 19, count 0 2006.201.02:00:55.26#ibcon#end of sib2, iclass 19, count 0 2006.201.02:00:55.26#ibcon#*after write, iclass 19, count 0 2006.201.02:00:55.26#ibcon#*before return 0, iclass 19, count 0 2006.201.02:00:55.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:55.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:00:55.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:00:55.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:00:55.26$vck44/vb=3,4 2006.201.02:00:55.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.02:00:55.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.02:00:55.26#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:55.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:55.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:55.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:55.32#ibcon#enter wrdev, iclass 21, count 2 2006.201.02:00:55.32#ibcon#first serial, iclass 21, count 2 2006.201.02:00:55.32#ibcon#enter sib2, iclass 21, count 2 2006.201.02:00:55.32#ibcon#flushed, iclass 21, count 2 2006.201.02:00:55.32#ibcon#about to write, iclass 21, count 2 2006.201.02:00:55.32#ibcon#wrote, iclass 21, count 2 2006.201.02:00:55.32#ibcon#about to read 3, iclass 21, count 2 2006.201.02:00:55.34#ibcon#read 3, iclass 21, count 2 2006.201.02:00:55.34#ibcon#about to read 4, iclass 21, count 2 2006.201.02:00:55.34#ibcon#read 4, iclass 21, count 2 2006.201.02:00:55.34#ibcon#about to read 5, iclass 21, count 2 2006.201.02:00:55.34#ibcon#read 5, iclass 21, count 2 2006.201.02:00:55.34#ibcon#about to read 6, iclass 21, count 2 2006.201.02:00:55.34#ibcon#read 6, iclass 21, count 2 2006.201.02:00:55.34#ibcon#end of sib2, iclass 21, count 2 2006.201.02:00:55.34#ibcon#*mode == 0, iclass 21, count 2 2006.201.02:00:55.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.02:00:55.34#ibcon#[27=AT03-04\r\n] 2006.201.02:00:55.34#ibcon#*before write, iclass 21, count 2 2006.201.02:00:55.34#ibcon#enter sib2, iclass 21, count 2 2006.201.02:00:55.34#ibcon#flushed, iclass 21, count 2 2006.201.02:00:55.34#ibcon#about to write, iclass 21, count 2 2006.201.02:00:55.34#ibcon#wrote, iclass 21, count 2 2006.201.02:00:55.34#ibcon#about to read 3, iclass 21, count 2 2006.201.02:00:55.37#ibcon#read 3, iclass 21, count 2 2006.201.02:00:55.37#ibcon#about to read 4, iclass 21, count 2 2006.201.02:00:55.37#ibcon#read 4, iclass 21, count 2 2006.201.02:00:55.37#ibcon#about to read 5, iclass 21, count 2 2006.201.02:00:55.37#ibcon#read 5, iclass 21, count 2 2006.201.02:00:55.37#ibcon#about to read 6, iclass 21, count 2 2006.201.02:00:55.37#ibcon#read 6, iclass 21, count 2 2006.201.02:00:55.37#ibcon#end of sib2, iclass 21, count 2 2006.201.02:00:55.37#ibcon#*after write, iclass 21, count 2 2006.201.02:00:55.37#ibcon#*before return 0, iclass 21, count 2 2006.201.02:00:55.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:55.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:00:55.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.02:00:55.37#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:55.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:55.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:55.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:55.49#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:00:55.49#ibcon#first serial, iclass 21, count 0 2006.201.02:00:55.49#ibcon#enter sib2, iclass 21, count 0 2006.201.02:00:55.49#ibcon#flushed, iclass 21, count 0 2006.201.02:00:55.49#ibcon#about to write, iclass 21, count 0 2006.201.02:00:55.49#ibcon#wrote, iclass 21, count 0 2006.201.02:00:55.49#ibcon#about to read 3, iclass 21, count 0 2006.201.02:00:55.51#ibcon#read 3, iclass 21, count 0 2006.201.02:00:55.51#ibcon#about to read 4, iclass 21, count 0 2006.201.02:00:55.51#ibcon#read 4, iclass 21, count 0 2006.201.02:00:55.51#ibcon#about to read 5, iclass 21, count 0 2006.201.02:00:55.51#ibcon#read 5, iclass 21, count 0 2006.201.02:00:55.51#ibcon#about to read 6, iclass 21, count 0 2006.201.02:00:55.51#ibcon#read 6, iclass 21, count 0 2006.201.02:00:55.51#ibcon#end of sib2, iclass 21, count 0 2006.201.02:00:55.51#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:00:55.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:00:55.51#ibcon#[27=USB\r\n] 2006.201.02:00:55.51#ibcon#*before write, iclass 21, count 0 2006.201.02:00:55.51#ibcon#enter sib2, iclass 21, count 0 2006.201.02:00:55.51#ibcon#flushed, iclass 21, count 0 2006.201.02:00:55.51#ibcon#about to write, iclass 21, count 0 2006.201.02:00:55.51#ibcon#wrote, iclass 21, count 0 2006.201.02:00:55.51#ibcon#about to read 3, iclass 21, count 0 2006.201.02:00:55.54#ibcon#read 3, iclass 21, count 0 2006.201.02:00:55.54#ibcon#about to read 4, iclass 21, count 0 2006.201.02:00:55.54#ibcon#read 4, iclass 21, count 0 2006.201.02:00:55.54#ibcon#about to read 5, iclass 21, count 0 2006.201.02:00:55.54#ibcon#read 5, iclass 21, count 0 2006.201.02:00:55.54#ibcon#about to read 6, iclass 21, count 0 2006.201.02:00:55.54#ibcon#read 6, iclass 21, count 0 2006.201.02:00:55.54#ibcon#end of sib2, iclass 21, count 0 2006.201.02:00:55.54#ibcon#*after write, iclass 21, count 0 2006.201.02:00:55.54#ibcon#*before return 0, iclass 21, count 0 2006.201.02:00:55.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:55.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:00:55.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:00:55.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:00:55.54$vck44/vblo=4,679.99 2006.201.02:00:55.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.02:00:55.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.02:00:55.54#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:55.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:55.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:55.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:55.54#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:00:55.54#ibcon#first serial, iclass 23, count 0 2006.201.02:00:55.54#ibcon#enter sib2, iclass 23, count 0 2006.201.02:00:55.54#ibcon#flushed, iclass 23, count 0 2006.201.02:00:55.54#ibcon#about to write, iclass 23, count 0 2006.201.02:00:55.54#ibcon#wrote, iclass 23, count 0 2006.201.02:00:55.54#ibcon#about to read 3, iclass 23, count 0 2006.201.02:00:55.56#ibcon#read 3, iclass 23, count 0 2006.201.02:00:55.56#ibcon#about to read 4, iclass 23, count 0 2006.201.02:00:55.56#ibcon#read 4, iclass 23, count 0 2006.201.02:00:55.56#ibcon#about to read 5, iclass 23, count 0 2006.201.02:00:55.56#ibcon#read 5, iclass 23, count 0 2006.201.02:00:55.56#ibcon#about to read 6, iclass 23, count 0 2006.201.02:00:55.56#ibcon#read 6, iclass 23, count 0 2006.201.02:00:55.56#ibcon#end of sib2, iclass 23, count 0 2006.201.02:00:55.56#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:00:55.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:00:55.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:00:55.56#ibcon#*before write, iclass 23, count 0 2006.201.02:00:55.56#ibcon#enter sib2, iclass 23, count 0 2006.201.02:00:55.56#ibcon#flushed, iclass 23, count 0 2006.201.02:00:55.56#ibcon#about to write, iclass 23, count 0 2006.201.02:00:55.56#ibcon#wrote, iclass 23, count 0 2006.201.02:00:55.56#ibcon#about to read 3, iclass 23, count 0 2006.201.02:00:55.60#ibcon#read 3, iclass 23, count 0 2006.201.02:00:55.60#ibcon#about to read 4, iclass 23, count 0 2006.201.02:00:55.60#ibcon#read 4, iclass 23, count 0 2006.201.02:00:55.60#ibcon#about to read 5, iclass 23, count 0 2006.201.02:00:55.60#ibcon#read 5, iclass 23, count 0 2006.201.02:00:55.60#ibcon#about to read 6, iclass 23, count 0 2006.201.02:00:55.60#ibcon#read 6, iclass 23, count 0 2006.201.02:00:55.60#ibcon#end of sib2, iclass 23, count 0 2006.201.02:00:55.60#ibcon#*after write, iclass 23, count 0 2006.201.02:00:55.60#ibcon#*before return 0, iclass 23, count 0 2006.201.02:00:55.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:55.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:00:55.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:00:55.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:00:55.60$vck44/vb=4,5 2006.201.02:00:55.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.02:00:55.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.02:00:55.60#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:55.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:55.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:55.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:55.66#ibcon#enter wrdev, iclass 25, count 2 2006.201.02:00:55.66#ibcon#first serial, iclass 25, count 2 2006.201.02:00:55.66#ibcon#enter sib2, iclass 25, count 2 2006.201.02:00:55.66#ibcon#flushed, iclass 25, count 2 2006.201.02:00:55.66#ibcon#about to write, iclass 25, count 2 2006.201.02:00:55.66#ibcon#wrote, iclass 25, count 2 2006.201.02:00:55.66#ibcon#about to read 3, iclass 25, count 2 2006.201.02:00:55.68#ibcon#read 3, iclass 25, count 2 2006.201.02:00:55.68#ibcon#about to read 4, iclass 25, count 2 2006.201.02:00:55.68#ibcon#read 4, iclass 25, count 2 2006.201.02:00:55.68#ibcon#about to read 5, iclass 25, count 2 2006.201.02:00:55.68#ibcon#read 5, iclass 25, count 2 2006.201.02:00:55.68#ibcon#about to read 6, iclass 25, count 2 2006.201.02:00:55.68#ibcon#read 6, iclass 25, count 2 2006.201.02:00:55.68#ibcon#end of sib2, iclass 25, count 2 2006.201.02:00:55.68#ibcon#*mode == 0, iclass 25, count 2 2006.201.02:00:55.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.02:00:55.68#ibcon#[27=AT04-05\r\n] 2006.201.02:00:55.68#ibcon#*before write, iclass 25, count 2 2006.201.02:00:55.68#ibcon#enter sib2, iclass 25, count 2 2006.201.02:00:55.68#ibcon#flushed, iclass 25, count 2 2006.201.02:00:55.68#ibcon#about to write, iclass 25, count 2 2006.201.02:00:55.68#ibcon#wrote, iclass 25, count 2 2006.201.02:00:55.68#ibcon#about to read 3, iclass 25, count 2 2006.201.02:00:55.72#ibcon#read 3, iclass 25, count 2 2006.201.02:00:55.72#ibcon#about to read 4, iclass 25, count 2 2006.201.02:00:55.72#ibcon#read 4, iclass 25, count 2 2006.201.02:00:55.72#ibcon#about to read 5, iclass 25, count 2 2006.201.02:00:55.72#ibcon#read 5, iclass 25, count 2 2006.201.02:00:55.72#ibcon#about to read 6, iclass 25, count 2 2006.201.02:00:55.72#ibcon#read 6, iclass 25, count 2 2006.201.02:00:55.72#ibcon#end of sib2, iclass 25, count 2 2006.201.02:00:55.72#ibcon#*after write, iclass 25, count 2 2006.201.02:00:55.72#ibcon#*before return 0, iclass 25, count 2 2006.201.02:00:55.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:55.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:00:55.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.02:00:55.72#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:55.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:55.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:55.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:55.84#ibcon#enter wrdev, iclass 25, count 0 2006.201.02:00:55.84#ibcon#first serial, iclass 25, count 0 2006.201.02:00:55.84#ibcon#enter sib2, iclass 25, count 0 2006.201.02:00:55.84#ibcon#flushed, iclass 25, count 0 2006.201.02:00:55.84#ibcon#about to write, iclass 25, count 0 2006.201.02:00:55.84#ibcon#wrote, iclass 25, count 0 2006.201.02:00:55.84#ibcon#about to read 3, iclass 25, count 0 2006.201.02:00:55.86#ibcon#read 3, iclass 25, count 0 2006.201.02:00:55.86#ibcon#about to read 4, iclass 25, count 0 2006.201.02:00:55.86#ibcon#read 4, iclass 25, count 0 2006.201.02:00:55.86#ibcon#about to read 5, iclass 25, count 0 2006.201.02:00:55.86#ibcon#read 5, iclass 25, count 0 2006.201.02:00:55.86#ibcon#about to read 6, iclass 25, count 0 2006.201.02:00:55.86#ibcon#read 6, iclass 25, count 0 2006.201.02:00:55.86#ibcon#end of sib2, iclass 25, count 0 2006.201.02:00:55.86#ibcon#*mode == 0, iclass 25, count 0 2006.201.02:00:55.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.02:00:55.86#ibcon#[27=USB\r\n] 2006.201.02:00:55.86#ibcon#*before write, iclass 25, count 0 2006.201.02:00:55.86#ibcon#enter sib2, iclass 25, count 0 2006.201.02:00:55.86#ibcon#flushed, iclass 25, count 0 2006.201.02:00:55.86#ibcon#about to write, iclass 25, count 0 2006.201.02:00:55.86#ibcon#wrote, iclass 25, count 0 2006.201.02:00:55.86#ibcon#about to read 3, iclass 25, count 0 2006.201.02:00:55.89#ibcon#read 3, iclass 25, count 0 2006.201.02:00:55.89#ibcon#about to read 4, iclass 25, count 0 2006.201.02:00:55.89#ibcon#read 4, iclass 25, count 0 2006.201.02:00:55.89#ibcon#about to read 5, iclass 25, count 0 2006.201.02:00:55.89#ibcon#read 5, iclass 25, count 0 2006.201.02:00:55.89#ibcon#about to read 6, iclass 25, count 0 2006.201.02:00:55.89#ibcon#read 6, iclass 25, count 0 2006.201.02:00:55.89#ibcon#end of sib2, iclass 25, count 0 2006.201.02:00:55.89#ibcon#*after write, iclass 25, count 0 2006.201.02:00:55.89#ibcon#*before return 0, iclass 25, count 0 2006.201.02:00:55.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:55.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:00:55.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.02:00:55.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.02:00:55.89$vck44/vblo=5,709.99 2006.201.02:00:55.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.02:00:55.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.02:00:55.89#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:55.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:55.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:55.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:55.89#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:00:55.89#ibcon#first serial, iclass 27, count 0 2006.201.02:00:55.89#ibcon#enter sib2, iclass 27, count 0 2006.201.02:00:55.89#ibcon#flushed, iclass 27, count 0 2006.201.02:00:55.89#ibcon#about to write, iclass 27, count 0 2006.201.02:00:55.89#ibcon#wrote, iclass 27, count 0 2006.201.02:00:55.89#ibcon#about to read 3, iclass 27, count 0 2006.201.02:00:55.91#ibcon#read 3, iclass 27, count 0 2006.201.02:00:55.91#ibcon#about to read 4, iclass 27, count 0 2006.201.02:00:55.91#ibcon#read 4, iclass 27, count 0 2006.201.02:00:55.91#ibcon#about to read 5, iclass 27, count 0 2006.201.02:00:55.91#ibcon#read 5, iclass 27, count 0 2006.201.02:00:55.91#ibcon#about to read 6, iclass 27, count 0 2006.201.02:00:55.91#ibcon#read 6, iclass 27, count 0 2006.201.02:00:55.91#ibcon#end of sib2, iclass 27, count 0 2006.201.02:00:55.91#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:00:55.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:00:55.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:00:55.91#ibcon#*before write, iclass 27, count 0 2006.201.02:00:55.91#ibcon#enter sib2, iclass 27, count 0 2006.201.02:00:55.91#ibcon#flushed, iclass 27, count 0 2006.201.02:00:55.91#ibcon#about to write, iclass 27, count 0 2006.201.02:00:55.91#ibcon#wrote, iclass 27, count 0 2006.201.02:00:55.91#ibcon#about to read 3, iclass 27, count 0 2006.201.02:00:55.95#ibcon#read 3, iclass 27, count 0 2006.201.02:00:55.95#ibcon#about to read 4, iclass 27, count 0 2006.201.02:00:55.95#ibcon#read 4, iclass 27, count 0 2006.201.02:00:55.95#ibcon#about to read 5, iclass 27, count 0 2006.201.02:00:55.95#ibcon#read 5, iclass 27, count 0 2006.201.02:00:55.95#ibcon#about to read 6, iclass 27, count 0 2006.201.02:00:55.95#ibcon#read 6, iclass 27, count 0 2006.201.02:00:55.95#ibcon#end of sib2, iclass 27, count 0 2006.201.02:00:55.95#ibcon#*after write, iclass 27, count 0 2006.201.02:00:55.95#ibcon#*before return 0, iclass 27, count 0 2006.201.02:00:55.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:55.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:00:55.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:00:55.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:00:55.95$vck44/vb=5,4 2006.201.02:00:55.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.02:00:55.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.02:00:55.95#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:55.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:56.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:56.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:56.01#ibcon#enter wrdev, iclass 29, count 2 2006.201.02:00:56.01#ibcon#first serial, iclass 29, count 2 2006.201.02:00:56.01#ibcon#enter sib2, iclass 29, count 2 2006.201.02:00:56.01#ibcon#flushed, iclass 29, count 2 2006.201.02:00:56.01#ibcon#about to write, iclass 29, count 2 2006.201.02:00:56.01#ibcon#wrote, iclass 29, count 2 2006.201.02:00:56.01#ibcon#about to read 3, iclass 29, count 2 2006.201.02:00:56.03#ibcon#read 3, iclass 29, count 2 2006.201.02:00:56.03#ibcon#about to read 4, iclass 29, count 2 2006.201.02:00:56.03#ibcon#read 4, iclass 29, count 2 2006.201.02:00:56.03#ibcon#about to read 5, iclass 29, count 2 2006.201.02:00:56.03#ibcon#read 5, iclass 29, count 2 2006.201.02:00:56.03#ibcon#about to read 6, iclass 29, count 2 2006.201.02:00:56.03#ibcon#read 6, iclass 29, count 2 2006.201.02:00:56.03#ibcon#end of sib2, iclass 29, count 2 2006.201.02:00:56.03#ibcon#*mode == 0, iclass 29, count 2 2006.201.02:00:56.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.02:00:56.03#ibcon#[27=AT05-04\r\n] 2006.201.02:00:56.03#ibcon#*before write, iclass 29, count 2 2006.201.02:00:56.03#ibcon#enter sib2, iclass 29, count 2 2006.201.02:00:56.03#ibcon#flushed, iclass 29, count 2 2006.201.02:00:56.03#ibcon#about to write, iclass 29, count 2 2006.201.02:00:56.03#ibcon#wrote, iclass 29, count 2 2006.201.02:00:56.03#ibcon#about to read 3, iclass 29, count 2 2006.201.02:00:56.06#ibcon#read 3, iclass 29, count 2 2006.201.02:00:56.06#ibcon#about to read 4, iclass 29, count 2 2006.201.02:00:56.06#ibcon#read 4, iclass 29, count 2 2006.201.02:00:56.06#ibcon#about to read 5, iclass 29, count 2 2006.201.02:00:56.06#ibcon#read 5, iclass 29, count 2 2006.201.02:00:56.06#ibcon#about to read 6, iclass 29, count 2 2006.201.02:00:56.06#ibcon#read 6, iclass 29, count 2 2006.201.02:00:56.06#ibcon#end of sib2, iclass 29, count 2 2006.201.02:00:56.06#ibcon#*after write, iclass 29, count 2 2006.201.02:00:56.06#ibcon#*before return 0, iclass 29, count 2 2006.201.02:00:56.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:56.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:00:56.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.02:00:56.06#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:56.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:56.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:56.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:56.18#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:00:56.18#ibcon#first serial, iclass 29, count 0 2006.201.02:00:56.18#ibcon#enter sib2, iclass 29, count 0 2006.201.02:00:56.18#ibcon#flushed, iclass 29, count 0 2006.201.02:00:56.18#ibcon#about to write, iclass 29, count 0 2006.201.02:00:56.18#ibcon#wrote, iclass 29, count 0 2006.201.02:00:56.18#ibcon#about to read 3, iclass 29, count 0 2006.201.02:00:56.20#ibcon#read 3, iclass 29, count 0 2006.201.02:00:56.20#ibcon#about to read 4, iclass 29, count 0 2006.201.02:00:56.20#ibcon#read 4, iclass 29, count 0 2006.201.02:00:56.20#ibcon#about to read 5, iclass 29, count 0 2006.201.02:00:56.20#ibcon#read 5, iclass 29, count 0 2006.201.02:00:56.20#ibcon#about to read 6, iclass 29, count 0 2006.201.02:00:56.20#ibcon#read 6, iclass 29, count 0 2006.201.02:00:56.20#ibcon#end of sib2, iclass 29, count 0 2006.201.02:00:56.20#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:00:56.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:00:56.20#ibcon#[27=USB\r\n] 2006.201.02:00:56.20#ibcon#*before write, iclass 29, count 0 2006.201.02:00:56.20#ibcon#enter sib2, iclass 29, count 0 2006.201.02:00:56.20#ibcon#flushed, iclass 29, count 0 2006.201.02:00:56.20#ibcon#about to write, iclass 29, count 0 2006.201.02:00:56.20#ibcon#wrote, iclass 29, count 0 2006.201.02:00:56.20#ibcon#about to read 3, iclass 29, count 0 2006.201.02:00:56.23#ibcon#read 3, iclass 29, count 0 2006.201.02:00:56.23#ibcon#about to read 4, iclass 29, count 0 2006.201.02:00:56.23#ibcon#read 4, iclass 29, count 0 2006.201.02:00:56.23#ibcon#about to read 5, iclass 29, count 0 2006.201.02:00:56.23#ibcon#read 5, iclass 29, count 0 2006.201.02:00:56.23#ibcon#about to read 6, iclass 29, count 0 2006.201.02:00:56.23#ibcon#read 6, iclass 29, count 0 2006.201.02:00:56.23#ibcon#end of sib2, iclass 29, count 0 2006.201.02:00:56.23#ibcon#*after write, iclass 29, count 0 2006.201.02:00:56.23#ibcon#*before return 0, iclass 29, count 0 2006.201.02:00:56.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:56.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:00:56.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:00:56.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:00:56.23$vck44/vblo=6,719.99 2006.201.02:00:56.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.02:00:56.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.02:00:56.23#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:56.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:56.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:56.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:56.23#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:00:56.23#ibcon#first serial, iclass 31, count 0 2006.201.02:00:56.23#ibcon#enter sib2, iclass 31, count 0 2006.201.02:00:56.23#ibcon#flushed, iclass 31, count 0 2006.201.02:00:56.23#ibcon#about to write, iclass 31, count 0 2006.201.02:00:56.23#ibcon#wrote, iclass 31, count 0 2006.201.02:00:56.23#ibcon#about to read 3, iclass 31, count 0 2006.201.02:00:56.25#ibcon#read 3, iclass 31, count 0 2006.201.02:00:56.25#ibcon#about to read 4, iclass 31, count 0 2006.201.02:00:56.25#ibcon#read 4, iclass 31, count 0 2006.201.02:00:56.25#ibcon#about to read 5, iclass 31, count 0 2006.201.02:00:56.25#ibcon#read 5, iclass 31, count 0 2006.201.02:00:56.25#ibcon#about to read 6, iclass 31, count 0 2006.201.02:00:56.25#ibcon#read 6, iclass 31, count 0 2006.201.02:00:56.25#ibcon#end of sib2, iclass 31, count 0 2006.201.02:00:56.25#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:00:56.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:00:56.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:00:56.25#ibcon#*before write, iclass 31, count 0 2006.201.02:00:56.25#ibcon#enter sib2, iclass 31, count 0 2006.201.02:00:56.25#ibcon#flushed, iclass 31, count 0 2006.201.02:00:56.25#ibcon#about to write, iclass 31, count 0 2006.201.02:00:56.25#ibcon#wrote, iclass 31, count 0 2006.201.02:00:56.25#ibcon#about to read 3, iclass 31, count 0 2006.201.02:00:56.29#ibcon#read 3, iclass 31, count 0 2006.201.02:00:56.29#ibcon#about to read 4, iclass 31, count 0 2006.201.02:00:56.29#ibcon#read 4, iclass 31, count 0 2006.201.02:00:56.29#ibcon#about to read 5, iclass 31, count 0 2006.201.02:00:56.29#ibcon#read 5, iclass 31, count 0 2006.201.02:00:56.29#ibcon#about to read 6, iclass 31, count 0 2006.201.02:00:56.29#ibcon#read 6, iclass 31, count 0 2006.201.02:00:56.29#ibcon#end of sib2, iclass 31, count 0 2006.201.02:00:56.29#ibcon#*after write, iclass 31, count 0 2006.201.02:00:56.29#ibcon#*before return 0, iclass 31, count 0 2006.201.02:00:56.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:56.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:00:56.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:00:56.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:00:56.29$vck44/vb=6,4 2006.201.02:00:56.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.02:00:56.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.02:00:56.29#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:56.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:56.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:56.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:56.35#ibcon#enter wrdev, iclass 33, count 2 2006.201.02:00:56.35#ibcon#first serial, iclass 33, count 2 2006.201.02:00:56.35#ibcon#enter sib2, iclass 33, count 2 2006.201.02:00:56.35#ibcon#flushed, iclass 33, count 2 2006.201.02:00:56.35#ibcon#about to write, iclass 33, count 2 2006.201.02:00:56.35#ibcon#wrote, iclass 33, count 2 2006.201.02:00:56.35#ibcon#about to read 3, iclass 33, count 2 2006.201.02:00:56.37#ibcon#read 3, iclass 33, count 2 2006.201.02:00:56.37#ibcon#about to read 4, iclass 33, count 2 2006.201.02:00:56.37#ibcon#read 4, iclass 33, count 2 2006.201.02:00:56.37#ibcon#about to read 5, iclass 33, count 2 2006.201.02:00:56.37#ibcon#read 5, iclass 33, count 2 2006.201.02:00:56.37#ibcon#about to read 6, iclass 33, count 2 2006.201.02:00:56.37#ibcon#read 6, iclass 33, count 2 2006.201.02:00:56.37#ibcon#end of sib2, iclass 33, count 2 2006.201.02:00:56.37#ibcon#*mode == 0, iclass 33, count 2 2006.201.02:00:56.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.02:00:56.37#ibcon#[27=AT06-04\r\n] 2006.201.02:00:56.37#ibcon#*before write, iclass 33, count 2 2006.201.02:00:56.37#ibcon#enter sib2, iclass 33, count 2 2006.201.02:00:56.37#ibcon#flushed, iclass 33, count 2 2006.201.02:00:56.37#ibcon#about to write, iclass 33, count 2 2006.201.02:00:56.37#ibcon#wrote, iclass 33, count 2 2006.201.02:00:56.37#ibcon#about to read 3, iclass 33, count 2 2006.201.02:00:56.40#ibcon#read 3, iclass 33, count 2 2006.201.02:00:56.40#ibcon#about to read 4, iclass 33, count 2 2006.201.02:00:56.40#ibcon#read 4, iclass 33, count 2 2006.201.02:00:56.40#ibcon#about to read 5, iclass 33, count 2 2006.201.02:00:56.40#ibcon#read 5, iclass 33, count 2 2006.201.02:00:56.40#ibcon#about to read 6, iclass 33, count 2 2006.201.02:00:56.40#ibcon#read 6, iclass 33, count 2 2006.201.02:00:56.40#ibcon#end of sib2, iclass 33, count 2 2006.201.02:00:56.40#ibcon#*after write, iclass 33, count 2 2006.201.02:00:56.40#ibcon#*before return 0, iclass 33, count 2 2006.201.02:00:56.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:56.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:00:56.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.02:00:56.40#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:56.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:56.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:56.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:56.52#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:00:56.52#ibcon#first serial, iclass 33, count 0 2006.201.02:00:56.52#ibcon#enter sib2, iclass 33, count 0 2006.201.02:00:56.52#ibcon#flushed, iclass 33, count 0 2006.201.02:00:56.52#ibcon#about to write, iclass 33, count 0 2006.201.02:00:56.52#ibcon#wrote, iclass 33, count 0 2006.201.02:00:56.52#ibcon#about to read 3, iclass 33, count 0 2006.201.02:00:56.54#ibcon#read 3, iclass 33, count 0 2006.201.02:00:56.54#ibcon#about to read 4, iclass 33, count 0 2006.201.02:00:56.54#ibcon#read 4, iclass 33, count 0 2006.201.02:00:56.54#ibcon#about to read 5, iclass 33, count 0 2006.201.02:00:56.54#ibcon#read 5, iclass 33, count 0 2006.201.02:00:56.54#ibcon#about to read 6, iclass 33, count 0 2006.201.02:00:56.54#ibcon#read 6, iclass 33, count 0 2006.201.02:00:56.54#ibcon#end of sib2, iclass 33, count 0 2006.201.02:00:56.54#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:00:56.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:00:56.54#ibcon#[27=USB\r\n] 2006.201.02:00:56.54#ibcon#*before write, iclass 33, count 0 2006.201.02:00:56.54#ibcon#enter sib2, iclass 33, count 0 2006.201.02:00:56.54#ibcon#flushed, iclass 33, count 0 2006.201.02:00:56.54#ibcon#about to write, iclass 33, count 0 2006.201.02:00:56.54#ibcon#wrote, iclass 33, count 0 2006.201.02:00:56.54#ibcon#about to read 3, iclass 33, count 0 2006.201.02:00:56.57#ibcon#read 3, iclass 33, count 0 2006.201.02:00:56.57#ibcon#about to read 4, iclass 33, count 0 2006.201.02:00:56.57#ibcon#read 4, iclass 33, count 0 2006.201.02:00:56.57#ibcon#about to read 5, iclass 33, count 0 2006.201.02:00:56.57#ibcon#read 5, iclass 33, count 0 2006.201.02:00:56.57#ibcon#about to read 6, iclass 33, count 0 2006.201.02:00:56.57#ibcon#read 6, iclass 33, count 0 2006.201.02:00:56.57#ibcon#end of sib2, iclass 33, count 0 2006.201.02:00:56.57#ibcon#*after write, iclass 33, count 0 2006.201.02:00:56.57#ibcon#*before return 0, iclass 33, count 0 2006.201.02:00:56.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:56.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:00:56.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:00:56.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:00:56.57$vck44/vblo=7,734.99 2006.201.02:00:56.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.02:00:56.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.02:00:56.57#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:56.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:56.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:56.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:56.57#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:00:56.57#ibcon#first serial, iclass 35, count 0 2006.201.02:00:56.57#ibcon#enter sib2, iclass 35, count 0 2006.201.02:00:56.57#ibcon#flushed, iclass 35, count 0 2006.201.02:00:56.57#ibcon#about to write, iclass 35, count 0 2006.201.02:00:56.57#ibcon#wrote, iclass 35, count 0 2006.201.02:00:56.57#ibcon#about to read 3, iclass 35, count 0 2006.201.02:00:56.59#ibcon#read 3, iclass 35, count 0 2006.201.02:00:56.59#ibcon#about to read 4, iclass 35, count 0 2006.201.02:00:56.59#ibcon#read 4, iclass 35, count 0 2006.201.02:00:56.59#ibcon#about to read 5, iclass 35, count 0 2006.201.02:00:56.59#ibcon#read 5, iclass 35, count 0 2006.201.02:00:56.59#ibcon#about to read 6, iclass 35, count 0 2006.201.02:00:56.59#ibcon#read 6, iclass 35, count 0 2006.201.02:00:56.59#ibcon#end of sib2, iclass 35, count 0 2006.201.02:00:56.59#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:00:56.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:00:56.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:00:56.59#ibcon#*before write, iclass 35, count 0 2006.201.02:00:56.59#ibcon#enter sib2, iclass 35, count 0 2006.201.02:00:56.59#ibcon#flushed, iclass 35, count 0 2006.201.02:00:56.59#ibcon#about to write, iclass 35, count 0 2006.201.02:00:56.59#ibcon#wrote, iclass 35, count 0 2006.201.02:00:56.59#ibcon#about to read 3, iclass 35, count 0 2006.201.02:00:56.63#ibcon#read 3, iclass 35, count 0 2006.201.02:00:56.63#ibcon#about to read 4, iclass 35, count 0 2006.201.02:00:56.63#ibcon#read 4, iclass 35, count 0 2006.201.02:00:56.63#ibcon#about to read 5, iclass 35, count 0 2006.201.02:00:56.63#ibcon#read 5, iclass 35, count 0 2006.201.02:00:56.63#ibcon#about to read 6, iclass 35, count 0 2006.201.02:00:56.63#ibcon#read 6, iclass 35, count 0 2006.201.02:00:56.63#ibcon#end of sib2, iclass 35, count 0 2006.201.02:00:56.63#ibcon#*after write, iclass 35, count 0 2006.201.02:00:56.63#ibcon#*before return 0, iclass 35, count 0 2006.201.02:00:56.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:56.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:00:56.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:00:56.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:00:56.63$vck44/vb=7,4 2006.201.02:00:56.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.02:00:56.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.02:00:56.63#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:56.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:56.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:56.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:56.69#ibcon#enter wrdev, iclass 37, count 2 2006.201.02:00:56.69#ibcon#first serial, iclass 37, count 2 2006.201.02:00:56.69#ibcon#enter sib2, iclass 37, count 2 2006.201.02:00:56.69#ibcon#flushed, iclass 37, count 2 2006.201.02:00:56.69#ibcon#about to write, iclass 37, count 2 2006.201.02:00:56.69#ibcon#wrote, iclass 37, count 2 2006.201.02:00:56.69#ibcon#about to read 3, iclass 37, count 2 2006.201.02:00:56.71#ibcon#read 3, iclass 37, count 2 2006.201.02:00:56.71#ibcon#about to read 4, iclass 37, count 2 2006.201.02:00:56.71#ibcon#read 4, iclass 37, count 2 2006.201.02:00:56.71#ibcon#about to read 5, iclass 37, count 2 2006.201.02:00:56.71#ibcon#read 5, iclass 37, count 2 2006.201.02:00:56.71#ibcon#about to read 6, iclass 37, count 2 2006.201.02:00:56.71#ibcon#read 6, iclass 37, count 2 2006.201.02:00:56.71#ibcon#end of sib2, iclass 37, count 2 2006.201.02:00:56.71#ibcon#*mode == 0, iclass 37, count 2 2006.201.02:00:56.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.02:00:56.71#ibcon#[27=AT07-04\r\n] 2006.201.02:00:56.71#ibcon#*before write, iclass 37, count 2 2006.201.02:00:56.71#ibcon#enter sib2, iclass 37, count 2 2006.201.02:00:56.71#ibcon#flushed, iclass 37, count 2 2006.201.02:00:56.71#ibcon#about to write, iclass 37, count 2 2006.201.02:00:56.71#ibcon#wrote, iclass 37, count 2 2006.201.02:00:56.71#ibcon#about to read 3, iclass 37, count 2 2006.201.02:00:56.74#ibcon#read 3, iclass 37, count 2 2006.201.02:00:56.74#ibcon#about to read 4, iclass 37, count 2 2006.201.02:00:56.74#ibcon#read 4, iclass 37, count 2 2006.201.02:00:56.74#ibcon#about to read 5, iclass 37, count 2 2006.201.02:00:56.74#ibcon#read 5, iclass 37, count 2 2006.201.02:00:56.74#ibcon#about to read 6, iclass 37, count 2 2006.201.02:00:56.74#ibcon#read 6, iclass 37, count 2 2006.201.02:00:56.74#ibcon#end of sib2, iclass 37, count 2 2006.201.02:00:56.74#ibcon#*after write, iclass 37, count 2 2006.201.02:00:56.74#ibcon#*before return 0, iclass 37, count 2 2006.201.02:00:56.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:56.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:00:56.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.02:00:56.74#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:56.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:56.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:56.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:56.86#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:00:56.86#ibcon#first serial, iclass 37, count 0 2006.201.02:00:56.86#ibcon#enter sib2, iclass 37, count 0 2006.201.02:00:56.86#ibcon#flushed, iclass 37, count 0 2006.201.02:00:56.86#ibcon#about to write, iclass 37, count 0 2006.201.02:00:56.86#ibcon#wrote, iclass 37, count 0 2006.201.02:00:56.86#ibcon#about to read 3, iclass 37, count 0 2006.201.02:00:56.88#ibcon#read 3, iclass 37, count 0 2006.201.02:00:56.88#ibcon#about to read 4, iclass 37, count 0 2006.201.02:00:56.88#ibcon#read 4, iclass 37, count 0 2006.201.02:00:56.88#ibcon#about to read 5, iclass 37, count 0 2006.201.02:00:56.88#ibcon#read 5, iclass 37, count 0 2006.201.02:00:56.88#ibcon#about to read 6, iclass 37, count 0 2006.201.02:00:56.88#ibcon#read 6, iclass 37, count 0 2006.201.02:00:56.88#ibcon#end of sib2, iclass 37, count 0 2006.201.02:00:56.88#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:00:56.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:00:56.88#ibcon#[27=USB\r\n] 2006.201.02:00:56.88#ibcon#*before write, iclass 37, count 0 2006.201.02:00:56.88#ibcon#enter sib2, iclass 37, count 0 2006.201.02:00:56.88#ibcon#flushed, iclass 37, count 0 2006.201.02:00:56.88#ibcon#about to write, iclass 37, count 0 2006.201.02:00:56.88#ibcon#wrote, iclass 37, count 0 2006.201.02:00:56.88#ibcon#about to read 3, iclass 37, count 0 2006.201.02:00:56.91#ibcon#read 3, iclass 37, count 0 2006.201.02:00:56.91#ibcon#about to read 4, iclass 37, count 0 2006.201.02:00:56.91#ibcon#read 4, iclass 37, count 0 2006.201.02:00:56.91#ibcon#about to read 5, iclass 37, count 0 2006.201.02:00:56.91#ibcon#read 5, iclass 37, count 0 2006.201.02:00:56.91#ibcon#about to read 6, iclass 37, count 0 2006.201.02:00:56.91#ibcon#read 6, iclass 37, count 0 2006.201.02:00:56.91#ibcon#end of sib2, iclass 37, count 0 2006.201.02:00:56.91#ibcon#*after write, iclass 37, count 0 2006.201.02:00:56.91#ibcon#*before return 0, iclass 37, count 0 2006.201.02:00:56.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:56.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:00:56.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:00:56.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:00:56.91$vck44/vblo=8,744.99 2006.201.02:00:56.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.02:00:56.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.02:00:56.91#ibcon#ireg 17 cls_cnt 0 2006.201.02:00:56.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:56.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:56.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:56.91#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:00:56.91#ibcon#first serial, iclass 39, count 0 2006.201.02:00:56.91#ibcon#enter sib2, iclass 39, count 0 2006.201.02:00:56.91#ibcon#flushed, iclass 39, count 0 2006.201.02:00:56.91#ibcon#about to write, iclass 39, count 0 2006.201.02:00:56.91#ibcon#wrote, iclass 39, count 0 2006.201.02:00:56.91#ibcon#about to read 3, iclass 39, count 0 2006.201.02:00:56.93#ibcon#read 3, iclass 39, count 0 2006.201.02:00:56.93#ibcon#about to read 4, iclass 39, count 0 2006.201.02:00:56.93#ibcon#read 4, iclass 39, count 0 2006.201.02:00:56.93#ibcon#about to read 5, iclass 39, count 0 2006.201.02:00:56.93#ibcon#read 5, iclass 39, count 0 2006.201.02:00:56.93#ibcon#about to read 6, iclass 39, count 0 2006.201.02:00:56.93#ibcon#read 6, iclass 39, count 0 2006.201.02:00:56.93#ibcon#end of sib2, iclass 39, count 0 2006.201.02:00:56.93#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:00:56.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:00:56.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:00:56.93#ibcon#*before write, iclass 39, count 0 2006.201.02:00:56.93#ibcon#enter sib2, iclass 39, count 0 2006.201.02:00:56.93#ibcon#flushed, iclass 39, count 0 2006.201.02:00:56.93#ibcon#about to write, iclass 39, count 0 2006.201.02:00:56.93#ibcon#wrote, iclass 39, count 0 2006.201.02:00:56.93#ibcon#about to read 3, iclass 39, count 0 2006.201.02:00:56.97#ibcon#read 3, iclass 39, count 0 2006.201.02:00:56.97#ibcon#about to read 4, iclass 39, count 0 2006.201.02:00:56.97#ibcon#read 4, iclass 39, count 0 2006.201.02:00:56.97#ibcon#about to read 5, iclass 39, count 0 2006.201.02:00:56.97#ibcon#read 5, iclass 39, count 0 2006.201.02:00:56.97#ibcon#about to read 6, iclass 39, count 0 2006.201.02:00:56.97#ibcon#read 6, iclass 39, count 0 2006.201.02:00:56.97#ibcon#end of sib2, iclass 39, count 0 2006.201.02:00:56.97#ibcon#*after write, iclass 39, count 0 2006.201.02:00:56.97#ibcon#*before return 0, iclass 39, count 0 2006.201.02:00:56.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:56.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:00:56.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:00:56.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:00:56.97$vck44/vb=8,4 2006.201.02:00:56.97#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.02:00:56.97#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.02:00:56.97#ibcon#ireg 11 cls_cnt 2 2006.201.02:00:56.97#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:57.03#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:57.03#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:57.03#ibcon#enter wrdev, iclass 2, count 2 2006.201.02:00:57.03#ibcon#first serial, iclass 2, count 2 2006.201.02:00:57.03#ibcon#enter sib2, iclass 2, count 2 2006.201.02:00:57.03#ibcon#flushed, iclass 2, count 2 2006.201.02:00:57.03#ibcon#about to write, iclass 2, count 2 2006.201.02:00:57.03#ibcon#wrote, iclass 2, count 2 2006.201.02:00:57.03#ibcon#about to read 3, iclass 2, count 2 2006.201.02:00:57.05#ibcon#read 3, iclass 2, count 2 2006.201.02:00:57.05#ibcon#about to read 4, iclass 2, count 2 2006.201.02:00:57.05#ibcon#read 4, iclass 2, count 2 2006.201.02:00:57.05#ibcon#about to read 5, iclass 2, count 2 2006.201.02:00:57.05#ibcon#read 5, iclass 2, count 2 2006.201.02:00:57.05#ibcon#about to read 6, iclass 2, count 2 2006.201.02:00:57.05#ibcon#read 6, iclass 2, count 2 2006.201.02:00:57.05#ibcon#end of sib2, iclass 2, count 2 2006.201.02:00:57.05#ibcon#*mode == 0, iclass 2, count 2 2006.201.02:00:57.05#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.02:00:57.05#ibcon#[27=AT08-04\r\n] 2006.201.02:00:57.05#ibcon#*before write, iclass 2, count 2 2006.201.02:00:57.05#ibcon#enter sib2, iclass 2, count 2 2006.201.02:00:57.05#ibcon#flushed, iclass 2, count 2 2006.201.02:00:57.05#ibcon#about to write, iclass 2, count 2 2006.201.02:00:57.05#ibcon#wrote, iclass 2, count 2 2006.201.02:00:57.05#ibcon#about to read 3, iclass 2, count 2 2006.201.02:00:57.08#ibcon#read 3, iclass 2, count 2 2006.201.02:00:57.08#ibcon#about to read 4, iclass 2, count 2 2006.201.02:00:57.08#ibcon#read 4, iclass 2, count 2 2006.201.02:00:57.08#ibcon#about to read 5, iclass 2, count 2 2006.201.02:00:57.08#ibcon#read 5, iclass 2, count 2 2006.201.02:00:57.08#ibcon#about to read 6, iclass 2, count 2 2006.201.02:00:57.08#ibcon#read 6, iclass 2, count 2 2006.201.02:00:57.08#ibcon#end of sib2, iclass 2, count 2 2006.201.02:00:57.08#ibcon#*after write, iclass 2, count 2 2006.201.02:00:57.08#ibcon#*before return 0, iclass 2, count 2 2006.201.02:00:57.08#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:57.08#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:00:57.08#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.02:00:57.08#ibcon#ireg 7 cls_cnt 0 2006.201.02:00:57.08#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:57.20#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:57.20#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:57.20#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:00:57.20#ibcon#first serial, iclass 2, count 0 2006.201.02:00:57.20#ibcon#enter sib2, iclass 2, count 0 2006.201.02:00:57.20#ibcon#flushed, iclass 2, count 0 2006.201.02:00:57.20#ibcon#about to write, iclass 2, count 0 2006.201.02:00:57.20#ibcon#wrote, iclass 2, count 0 2006.201.02:00:57.20#ibcon#about to read 3, iclass 2, count 0 2006.201.02:00:57.23#ibcon#read 3, iclass 2, count 0 2006.201.02:00:57.23#ibcon#about to read 4, iclass 2, count 0 2006.201.02:00:57.23#ibcon#read 4, iclass 2, count 0 2006.201.02:00:57.23#ibcon#about to read 5, iclass 2, count 0 2006.201.02:00:57.23#ibcon#read 5, iclass 2, count 0 2006.201.02:00:57.23#ibcon#about to read 6, iclass 2, count 0 2006.201.02:00:57.23#ibcon#read 6, iclass 2, count 0 2006.201.02:00:57.23#ibcon#end of sib2, iclass 2, count 0 2006.201.02:00:57.23#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:00:57.23#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:00:57.23#ibcon#[27=USB\r\n] 2006.201.02:00:57.23#ibcon#*before write, iclass 2, count 0 2006.201.02:00:57.23#ibcon#enter sib2, iclass 2, count 0 2006.201.02:00:57.23#ibcon#flushed, iclass 2, count 0 2006.201.02:00:57.23#ibcon#about to write, iclass 2, count 0 2006.201.02:00:57.23#ibcon#wrote, iclass 2, count 0 2006.201.02:00:57.23#ibcon#about to read 3, iclass 2, count 0 2006.201.02:00:57.26#ibcon#read 3, iclass 2, count 0 2006.201.02:00:57.26#ibcon#about to read 4, iclass 2, count 0 2006.201.02:00:57.26#ibcon#read 4, iclass 2, count 0 2006.201.02:00:57.26#ibcon#about to read 5, iclass 2, count 0 2006.201.02:00:57.26#ibcon#read 5, iclass 2, count 0 2006.201.02:00:57.26#ibcon#about to read 6, iclass 2, count 0 2006.201.02:00:57.26#ibcon#read 6, iclass 2, count 0 2006.201.02:00:57.26#ibcon#end of sib2, iclass 2, count 0 2006.201.02:00:57.26#ibcon#*after write, iclass 2, count 0 2006.201.02:00:57.26#ibcon#*before return 0, iclass 2, count 0 2006.201.02:00:57.26#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:57.26#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:00:57.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:00:57.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:00:57.26$vck44/vabw=wide 2006.201.02:00:57.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.02:00:57.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.02:00:57.26#ibcon#ireg 8 cls_cnt 0 2006.201.02:00:57.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:00:57.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:00:57.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:00:57.26#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:00:57.26#ibcon#first serial, iclass 5, count 0 2006.201.02:00:57.26#ibcon#enter sib2, iclass 5, count 0 2006.201.02:00:57.26#ibcon#flushed, iclass 5, count 0 2006.201.02:00:57.26#ibcon#about to write, iclass 5, count 0 2006.201.02:00:57.26#ibcon#wrote, iclass 5, count 0 2006.201.02:00:57.26#ibcon#about to read 3, iclass 5, count 0 2006.201.02:00:57.28#ibcon#read 3, iclass 5, count 0 2006.201.02:00:57.28#ibcon#about to read 4, iclass 5, count 0 2006.201.02:00:57.28#ibcon#read 4, iclass 5, count 0 2006.201.02:00:57.28#ibcon#about to read 5, iclass 5, count 0 2006.201.02:00:57.28#ibcon#read 5, iclass 5, count 0 2006.201.02:00:57.28#ibcon#about to read 6, iclass 5, count 0 2006.201.02:00:57.28#ibcon#read 6, iclass 5, count 0 2006.201.02:00:57.28#ibcon#end of sib2, iclass 5, count 0 2006.201.02:00:57.28#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:00:57.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:00:57.28#ibcon#[25=BW32\r\n] 2006.201.02:00:57.28#ibcon#*before write, iclass 5, count 0 2006.201.02:00:57.28#ibcon#enter sib2, iclass 5, count 0 2006.201.02:00:57.28#ibcon#flushed, iclass 5, count 0 2006.201.02:00:57.28#ibcon#about to write, iclass 5, count 0 2006.201.02:00:57.28#ibcon#wrote, iclass 5, count 0 2006.201.02:00:57.28#ibcon#about to read 3, iclass 5, count 0 2006.201.02:00:57.31#ibcon#read 3, iclass 5, count 0 2006.201.02:00:57.31#ibcon#about to read 4, iclass 5, count 0 2006.201.02:00:57.31#ibcon#read 4, iclass 5, count 0 2006.201.02:00:57.31#ibcon#about to read 5, iclass 5, count 0 2006.201.02:00:57.31#ibcon#read 5, iclass 5, count 0 2006.201.02:00:57.31#ibcon#about to read 6, iclass 5, count 0 2006.201.02:00:57.31#ibcon#read 6, iclass 5, count 0 2006.201.02:00:57.31#ibcon#end of sib2, iclass 5, count 0 2006.201.02:00:57.31#ibcon#*after write, iclass 5, count 0 2006.201.02:00:57.31#ibcon#*before return 0, iclass 5, count 0 2006.201.02:00:57.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:00:57.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:00:57.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:00:57.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:00:57.31$vck44/vbbw=wide 2006.201.02:00:57.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.02:00:57.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.02:00:57.31#ibcon#ireg 8 cls_cnt 0 2006.201.02:00:57.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:00:57.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:00:57.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:00:57.38#ibcon#enter wrdev, iclass 7, count 0 2006.201.02:00:57.38#ibcon#first serial, iclass 7, count 0 2006.201.02:00:57.38#ibcon#enter sib2, iclass 7, count 0 2006.201.02:00:57.38#ibcon#flushed, iclass 7, count 0 2006.201.02:00:57.38#ibcon#about to write, iclass 7, count 0 2006.201.02:00:57.38#ibcon#wrote, iclass 7, count 0 2006.201.02:00:57.38#ibcon#about to read 3, iclass 7, count 0 2006.201.02:00:57.40#ibcon#read 3, iclass 7, count 0 2006.201.02:00:57.40#ibcon#about to read 4, iclass 7, count 0 2006.201.02:00:57.40#ibcon#read 4, iclass 7, count 0 2006.201.02:00:57.40#ibcon#about to read 5, iclass 7, count 0 2006.201.02:00:57.40#ibcon#read 5, iclass 7, count 0 2006.201.02:00:57.40#ibcon#about to read 6, iclass 7, count 0 2006.201.02:00:57.40#ibcon#read 6, iclass 7, count 0 2006.201.02:00:57.40#ibcon#end of sib2, iclass 7, count 0 2006.201.02:00:57.40#ibcon#*mode == 0, iclass 7, count 0 2006.201.02:00:57.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.02:00:57.40#ibcon#[27=BW32\r\n] 2006.201.02:00:57.40#ibcon#*before write, iclass 7, count 0 2006.201.02:00:57.40#ibcon#enter sib2, iclass 7, count 0 2006.201.02:00:57.40#ibcon#flushed, iclass 7, count 0 2006.201.02:00:57.40#ibcon#about to write, iclass 7, count 0 2006.201.02:00:57.40#ibcon#wrote, iclass 7, count 0 2006.201.02:00:57.40#ibcon#about to read 3, iclass 7, count 0 2006.201.02:00:57.43#ibcon#read 3, iclass 7, count 0 2006.201.02:00:57.43#ibcon#about to read 4, iclass 7, count 0 2006.201.02:00:57.43#ibcon#read 4, iclass 7, count 0 2006.201.02:00:57.43#ibcon#about to read 5, iclass 7, count 0 2006.201.02:00:57.43#ibcon#read 5, iclass 7, count 0 2006.201.02:00:57.43#ibcon#about to read 6, iclass 7, count 0 2006.201.02:00:57.43#ibcon#read 6, iclass 7, count 0 2006.201.02:00:57.43#ibcon#end of sib2, iclass 7, count 0 2006.201.02:00:57.43#ibcon#*after write, iclass 7, count 0 2006.201.02:00:57.43#ibcon#*before return 0, iclass 7, count 0 2006.201.02:00:57.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:00:57.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:00:57.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.02:00:57.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.02:00:57.43$setupk4/ifdk4 2006.201.02:00:57.43$ifdk4/lo= 2006.201.02:00:57.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:00:57.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:00:57.43$ifdk4/patch= 2006.201.02:00:57.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:00:57.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:00:57.43$setupk4/!*+20s 2006.201.02:01:04.74#abcon#<5=/05 2.6 4.2 22.92 921005.1\r\n> 2006.201.02:01:04.76#abcon#{5=INTERFACE CLEAR} 2006.201.02:01:04.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:01:11.88$setupk4/"tpicd 2006.201.02:01:11.88$setupk4/echo=off 2006.201.02:01:11.88$setupk4/xlog=off 2006.201.02:01:11.88:!2006.201.02:03:05 2006.201.02:01:29.14#trakl#Source acquired 2006.201.02:01:31.14#flagr#flagr/antenna,acquired 2006.201.02:03:05.00:preob 2006.201.02:03:05.14/onsource/TRACKING 2006.201.02:03:05.14:!2006.201.02:03:15 2006.201.02:03:15.00:"tape 2006.201.02:03:15.00:"st=record 2006.201.02:03:15.00:data_valid=on 2006.201.02:03:15.00:midob 2006.201.02:03:16.14/onsource/TRACKING 2006.201.02:03:16.14/wx/22.92,1005.1,91 2006.201.02:03:16.27/cable/+6.4664E-03 2006.201.02:03:17.36/va/01,08,usb,yes,30,32 2006.201.02:03:17.36/va/02,07,usb,yes,32,33 2006.201.02:03:17.36/va/03,08,usb,yes,29,30 2006.201.02:03:17.36/va/04,07,usb,yes,33,35 2006.201.02:03:17.36/va/05,04,usb,yes,29,30 2006.201.02:03:17.36/va/06,05,usb,yes,29,29 2006.201.02:03:17.36/va/07,05,usb,yes,28,29 2006.201.02:03:17.36/va/08,04,usb,yes,28,34 2006.201.02:03:17.59/valo/01,524.99,yes,locked 2006.201.02:03:17.59/valo/02,534.99,yes,locked 2006.201.02:03:17.59/valo/03,564.99,yes,locked 2006.201.02:03:17.59/valo/04,624.99,yes,locked 2006.201.02:03:17.59/valo/05,734.99,yes,locked 2006.201.02:03:17.59/valo/06,814.99,yes,locked 2006.201.02:03:17.59/valo/07,864.99,yes,locked 2006.201.02:03:17.59/valo/08,884.99,yes,locked 2006.201.02:03:18.68/vb/01,04,usb,yes,29,27 2006.201.02:03:18.68/vb/02,05,usb,yes,28,28 2006.201.02:03:18.68/vb/03,04,usb,yes,29,32 2006.201.02:03:18.68/vb/04,05,usb,yes,29,28 2006.201.02:03:18.68/vb/05,04,usb,yes,25,28 2006.201.02:03:18.68/vb/06,04,usb,yes,30,26 2006.201.02:03:18.68/vb/07,04,usb,yes,30,30 2006.201.02:03:18.68/vb/08,04,usb,yes,27,31 2006.201.02:03:18.91/vblo/01,629.99,yes,locked 2006.201.02:03:18.91/vblo/02,634.99,yes,locked 2006.201.02:03:18.91/vblo/03,649.99,yes,locked 2006.201.02:03:18.91/vblo/04,679.99,yes,locked 2006.201.02:03:18.91/vblo/05,709.99,yes,locked 2006.201.02:03:18.91/vblo/06,719.99,yes,locked 2006.201.02:03:18.91/vblo/07,734.99,yes,locked 2006.201.02:03:18.91/vblo/08,744.99,yes,locked 2006.201.02:03:19.06/vabw/8 2006.201.02:03:19.21/vbbw/8 2006.201.02:03:19.34/xfe/off,on,16.0 2006.201.02:03:19.73/ifatt/23,28,28,28 2006.201.02:03:20.04/fmout-gps/S +4.43E-07 2006.201.02:03:20.09:!2006.201.02:07:05 2006.201.02:07:05.00:data_valid=off 2006.201.02:07:05.00:"et 2006.201.02:07:05.00:!+3s 2006.201.02:07:08.02:"tape 2006.201.02:07:08.02:postob 2006.201.02:07:08.15/cable/+6.4687E-03 2006.201.02:07:08.15/wx/22.91,1005.1,91 2006.201.02:07:08.21/fmout-gps/S +4.43E-07 2006.201.02:07:08.21:scan_name=201-0211,jd0607,90 2006.201.02:07:08.21:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.201.02:07:09.13#flagr#flagr/antenna,new-source 2006.201.02:07:09.13:checkk5 2006.201.02:07:09.58/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:07:10.03/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:07:10.44/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:07:10.86/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:07:11.28/chk_obsdata//k5ts1/T2010203??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.02:07:11.92/chk_obsdata//k5ts2/T2010203??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.02:07:12.37/chk_obsdata//k5ts3/T2010203??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.02:07:12.78/chk_obsdata//k5ts4/T2010203??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.02:07:13.72/k5log//k5ts1_log_newline 2006.201.02:07:14.56/k5log//k5ts2_log_newline 2006.201.02:07:15.33/k5log//k5ts3_log_newline 2006.201.02:07:16.08/k5log//k5ts4_log_newline 2006.201.02:07:16.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:07:16.10:setupk4=1 2006.201.02:07:16.10$setupk4/echo=on 2006.201.02:07:16.10$setupk4/pcalon 2006.201.02:07:16.10$pcalon/"no phase cal control is implemented here 2006.201.02:07:16.10$setupk4/"tpicd=stop 2006.201.02:07:16.10$setupk4/"rec=synch_on 2006.201.02:07:16.10$setupk4/"rec_mode=128 2006.201.02:07:16.10$setupk4/!* 2006.201.02:07:16.10$setupk4/recpk4 2006.201.02:07:16.10$recpk4/recpatch= 2006.201.02:07:16.11$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:07:16.11$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:07:16.11$setupk4/vck44 2006.201.02:07:16.11$vck44/valo=1,524.99 2006.201.02:07:16.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.02:07:16.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.02:07:16.11#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:16.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:16.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:16.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:16.11#ibcon#enter wrdev, iclass 18, count 0 2006.201.02:07:16.11#ibcon#first serial, iclass 18, count 0 2006.201.02:07:16.11#ibcon#enter sib2, iclass 18, count 0 2006.201.02:07:16.11#ibcon#flushed, iclass 18, count 0 2006.201.02:07:16.11#ibcon#about to write, iclass 18, count 0 2006.201.02:07:16.11#ibcon#wrote, iclass 18, count 0 2006.201.02:07:16.11#ibcon#about to read 3, iclass 18, count 0 2006.201.02:07:16.15#ibcon#read 3, iclass 18, count 0 2006.201.02:07:16.15#ibcon#about to read 4, iclass 18, count 0 2006.201.02:07:16.15#ibcon#read 4, iclass 18, count 0 2006.201.02:07:16.15#ibcon#about to read 5, iclass 18, count 0 2006.201.02:07:16.15#ibcon#read 5, iclass 18, count 0 2006.201.02:07:16.15#ibcon#about to read 6, iclass 18, count 0 2006.201.02:07:16.15#ibcon#read 6, iclass 18, count 0 2006.201.02:07:16.15#ibcon#end of sib2, iclass 18, count 0 2006.201.02:07:16.15#ibcon#*mode == 0, iclass 18, count 0 2006.201.02:07:16.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.02:07:16.15#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:07:16.15#ibcon#*before write, iclass 18, count 0 2006.201.02:07:16.15#ibcon#enter sib2, iclass 18, count 0 2006.201.02:07:16.15#ibcon#flushed, iclass 18, count 0 2006.201.02:07:16.15#ibcon#about to write, iclass 18, count 0 2006.201.02:07:16.15#ibcon#wrote, iclass 18, count 0 2006.201.02:07:16.15#ibcon#about to read 3, iclass 18, count 0 2006.201.02:07:16.20#ibcon#read 3, iclass 18, count 0 2006.201.02:07:16.20#ibcon#about to read 4, iclass 18, count 0 2006.201.02:07:16.20#ibcon#read 4, iclass 18, count 0 2006.201.02:07:16.20#ibcon#about to read 5, iclass 18, count 0 2006.201.02:07:16.20#ibcon#read 5, iclass 18, count 0 2006.201.02:07:16.20#ibcon#about to read 6, iclass 18, count 0 2006.201.02:07:16.20#ibcon#read 6, iclass 18, count 0 2006.201.02:07:16.20#ibcon#end of sib2, iclass 18, count 0 2006.201.02:07:16.20#ibcon#*after write, iclass 18, count 0 2006.201.02:07:16.20#ibcon#*before return 0, iclass 18, count 0 2006.201.02:07:16.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:16.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:16.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.02:07:16.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.02:07:16.20$vck44/va=1,8 2006.201.02:07:16.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.02:07:16.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.02:07:16.20#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:16.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:16.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:16.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:16.20#ibcon#enter wrdev, iclass 20, count 2 2006.201.02:07:16.20#ibcon#first serial, iclass 20, count 2 2006.201.02:07:16.20#ibcon#enter sib2, iclass 20, count 2 2006.201.02:07:16.20#ibcon#flushed, iclass 20, count 2 2006.201.02:07:16.20#ibcon#about to write, iclass 20, count 2 2006.201.02:07:16.20#ibcon#wrote, iclass 20, count 2 2006.201.02:07:16.20#ibcon#about to read 3, iclass 20, count 2 2006.201.02:07:16.22#ibcon#read 3, iclass 20, count 2 2006.201.02:07:16.22#ibcon#about to read 4, iclass 20, count 2 2006.201.02:07:16.22#ibcon#read 4, iclass 20, count 2 2006.201.02:07:16.22#ibcon#about to read 5, iclass 20, count 2 2006.201.02:07:16.22#ibcon#read 5, iclass 20, count 2 2006.201.02:07:16.22#ibcon#about to read 6, iclass 20, count 2 2006.201.02:07:16.22#ibcon#read 6, iclass 20, count 2 2006.201.02:07:16.22#ibcon#end of sib2, iclass 20, count 2 2006.201.02:07:16.22#ibcon#*mode == 0, iclass 20, count 2 2006.201.02:07:16.22#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.02:07:16.22#ibcon#[25=AT01-08\r\n] 2006.201.02:07:16.22#ibcon#*before write, iclass 20, count 2 2006.201.02:07:16.22#ibcon#enter sib2, iclass 20, count 2 2006.201.02:07:16.22#ibcon#flushed, iclass 20, count 2 2006.201.02:07:16.22#ibcon#about to write, iclass 20, count 2 2006.201.02:07:16.22#ibcon#wrote, iclass 20, count 2 2006.201.02:07:16.22#ibcon#about to read 3, iclass 20, count 2 2006.201.02:07:16.25#ibcon#read 3, iclass 20, count 2 2006.201.02:07:16.25#ibcon#about to read 4, iclass 20, count 2 2006.201.02:07:16.25#ibcon#read 4, iclass 20, count 2 2006.201.02:07:16.25#ibcon#about to read 5, iclass 20, count 2 2006.201.02:07:16.25#ibcon#read 5, iclass 20, count 2 2006.201.02:07:16.25#ibcon#about to read 6, iclass 20, count 2 2006.201.02:07:16.25#ibcon#read 6, iclass 20, count 2 2006.201.02:07:16.25#ibcon#end of sib2, iclass 20, count 2 2006.201.02:07:16.25#ibcon#*after write, iclass 20, count 2 2006.201.02:07:16.25#ibcon#*before return 0, iclass 20, count 2 2006.201.02:07:16.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:16.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:16.25#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.02:07:16.25#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:16.25#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:16.37#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:16.37#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:16.37#ibcon#enter wrdev, iclass 20, count 0 2006.201.02:07:16.37#ibcon#first serial, iclass 20, count 0 2006.201.02:07:16.37#ibcon#enter sib2, iclass 20, count 0 2006.201.02:07:16.37#ibcon#flushed, iclass 20, count 0 2006.201.02:07:16.37#ibcon#about to write, iclass 20, count 0 2006.201.02:07:16.37#ibcon#wrote, iclass 20, count 0 2006.201.02:07:16.37#ibcon#about to read 3, iclass 20, count 0 2006.201.02:07:16.39#ibcon#read 3, iclass 20, count 0 2006.201.02:07:16.39#ibcon#about to read 4, iclass 20, count 0 2006.201.02:07:16.39#ibcon#read 4, iclass 20, count 0 2006.201.02:07:16.39#ibcon#about to read 5, iclass 20, count 0 2006.201.02:07:16.39#ibcon#read 5, iclass 20, count 0 2006.201.02:07:16.39#ibcon#about to read 6, iclass 20, count 0 2006.201.02:07:16.39#ibcon#read 6, iclass 20, count 0 2006.201.02:07:16.39#ibcon#end of sib2, iclass 20, count 0 2006.201.02:07:16.39#ibcon#*mode == 0, iclass 20, count 0 2006.201.02:07:16.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.02:07:16.39#ibcon#[25=USB\r\n] 2006.201.02:07:16.39#ibcon#*before write, iclass 20, count 0 2006.201.02:07:16.39#ibcon#enter sib2, iclass 20, count 0 2006.201.02:07:16.39#ibcon#flushed, iclass 20, count 0 2006.201.02:07:16.39#ibcon#about to write, iclass 20, count 0 2006.201.02:07:16.39#ibcon#wrote, iclass 20, count 0 2006.201.02:07:16.39#ibcon#about to read 3, iclass 20, count 0 2006.201.02:07:16.42#ibcon#read 3, iclass 20, count 0 2006.201.02:07:16.42#ibcon#about to read 4, iclass 20, count 0 2006.201.02:07:16.42#ibcon#read 4, iclass 20, count 0 2006.201.02:07:16.42#ibcon#about to read 5, iclass 20, count 0 2006.201.02:07:16.42#ibcon#read 5, iclass 20, count 0 2006.201.02:07:16.42#ibcon#about to read 6, iclass 20, count 0 2006.201.02:07:16.42#ibcon#read 6, iclass 20, count 0 2006.201.02:07:16.42#ibcon#end of sib2, iclass 20, count 0 2006.201.02:07:16.42#ibcon#*after write, iclass 20, count 0 2006.201.02:07:16.42#ibcon#*before return 0, iclass 20, count 0 2006.201.02:07:16.42#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:16.42#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:16.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.02:07:16.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.02:07:16.42$vck44/valo=2,534.99 2006.201.02:07:16.42#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.02:07:16.42#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.02:07:16.42#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:16.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:16.42#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:16.42#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:16.42#ibcon#enter wrdev, iclass 22, count 0 2006.201.02:07:16.42#ibcon#first serial, iclass 22, count 0 2006.201.02:07:16.42#ibcon#enter sib2, iclass 22, count 0 2006.201.02:07:16.42#ibcon#flushed, iclass 22, count 0 2006.201.02:07:16.42#ibcon#about to write, iclass 22, count 0 2006.201.02:07:16.42#ibcon#wrote, iclass 22, count 0 2006.201.02:07:16.42#ibcon#about to read 3, iclass 22, count 0 2006.201.02:07:16.44#ibcon#read 3, iclass 22, count 0 2006.201.02:07:16.44#ibcon#about to read 4, iclass 22, count 0 2006.201.02:07:16.44#ibcon#read 4, iclass 22, count 0 2006.201.02:07:16.44#ibcon#about to read 5, iclass 22, count 0 2006.201.02:07:16.44#ibcon#read 5, iclass 22, count 0 2006.201.02:07:16.44#ibcon#about to read 6, iclass 22, count 0 2006.201.02:07:16.44#ibcon#read 6, iclass 22, count 0 2006.201.02:07:16.44#ibcon#end of sib2, iclass 22, count 0 2006.201.02:07:16.44#ibcon#*mode == 0, iclass 22, count 0 2006.201.02:07:16.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.02:07:16.44#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:07:16.44#ibcon#*before write, iclass 22, count 0 2006.201.02:07:16.44#ibcon#enter sib2, iclass 22, count 0 2006.201.02:07:16.44#ibcon#flushed, iclass 22, count 0 2006.201.02:07:16.44#ibcon#about to write, iclass 22, count 0 2006.201.02:07:16.44#ibcon#wrote, iclass 22, count 0 2006.201.02:07:16.44#ibcon#about to read 3, iclass 22, count 0 2006.201.02:07:16.49#ibcon#read 3, iclass 22, count 0 2006.201.02:07:16.49#ibcon#about to read 4, iclass 22, count 0 2006.201.02:07:16.49#ibcon#read 4, iclass 22, count 0 2006.201.02:07:16.49#ibcon#about to read 5, iclass 22, count 0 2006.201.02:07:16.49#ibcon#read 5, iclass 22, count 0 2006.201.02:07:16.49#ibcon#about to read 6, iclass 22, count 0 2006.201.02:07:16.49#ibcon#read 6, iclass 22, count 0 2006.201.02:07:16.49#ibcon#end of sib2, iclass 22, count 0 2006.201.02:07:16.49#ibcon#*after write, iclass 22, count 0 2006.201.02:07:16.49#ibcon#*before return 0, iclass 22, count 0 2006.201.02:07:16.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:16.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:16.49#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.02:07:16.49#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.02:07:16.49$vck44/va=2,7 2006.201.02:07:16.49#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.02:07:16.49#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.02:07:16.49#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:16.49#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:16.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:16.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:16.54#ibcon#enter wrdev, iclass 24, count 2 2006.201.02:07:16.54#ibcon#first serial, iclass 24, count 2 2006.201.02:07:16.54#ibcon#enter sib2, iclass 24, count 2 2006.201.02:07:16.54#ibcon#flushed, iclass 24, count 2 2006.201.02:07:16.54#ibcon#about to write, iclass 24, count 2 2006.201.02:07:16.54#ibcon#wrote, iclass 24, count 2 2006.201.02:07:16.54#ibcon#about to read 3, iclass 24, count 2 2006.201.02:07:16.56#ibcon#read 3, iclass 24, count 2 2006.201.02:07:16.56#ibcon#about to read 4, iclass 24, count 2 2006.201.02:07:16.56#ibcon#read 4, iclass 24, count 2 2006.201.02:07:16.56#ibcon#about to read 5, iclass 24, count 2 2006.201.02:07:16.56#ibcon#read 5, iclass 24, count 2 2006.201.02:07:16.56#ibcon#about to read 6, iclass 24, count 2 2006.201.02:07:16.56#ibcon#read 6, iclass 24, count 2 2006.201.02:07:16.56#ibcon#end of sib2, iclass 24, count 2 2006.201.02:07:16.56#ibcon#*mode == 0, iclass 24, count 2 2006.201.02:07:16.56#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.02:07:16.56#ibcon#[25=AT02-07\r\n] 2006.201.02:07:16.56#ibcon#*before write, iclass 24, count 2 2006.201.02:07:16.56#ibcon#enter sib2, iclass 24, count 2 2006.201.02:07:16.56#ibcon#flushed, iclass 24, count 2 2006.201.02:07:16.56#ibcon#about to write, iclass 24, count 2 2006.201.02:07:16.56#ibcon#wrote, iclass 24, count 2 2006.201.02:07:16.56#ibcon#about to read 3, iclass 24, count 2 2006.201.02:07:16.59#ibcon#read 3, iclass 24, count 2 2006.201.02:07:16.59#ibcon#about to read 4, iclass 24, count 2 2006.201.02:07:16.59#ibcon#read 4, iclass 24, count 2 2006.201.02:07:16.59#ibcon#about to read 5, iclass 24, count 2 2006.201.02:07:16.59#ibcon#read 5, iclass 24, count 2 2006.201.02:07:16.59#ibcon#about to read 6, iclass 24, count 2 2006.201.02:07:16.59#ibcon#read 6, iclass 24, count 2 2006.201.02:07:16.59#ibcon#end of sib2, iclass 24, count 2 2006.201.02:07:16.59#ibcon#*after write, iclass 24, count 2 2006.201.02:07:16.59#ibcon#*before return 0, iclass 24, count 2 2006.201.02:07:16.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:16.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:16.59#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.02:07:16.59#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:16.59#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:16.71#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:16.71#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:16.71#ibcon#enter wrdev, iclass 24, count 0 2006.201.02:07:16.71#ibcon#first serial, iclass 24, count 0 2006.201.02:07:16.71#ibcon#enter sib2, iclass 24, count 0 2006.201.02:07:16.71#ibcon#flushed, iclass 24, count 0 2006.201.02:07:16.71#ibcon#about to write, iclass 24, count 0 2006.201.02:07:16.71#ibcon#wrote, iclass 24, count 0 2006.201.02:07:16.71#ibcon#about to read 3, iclass 24, count 0 2006.201.02:07:16.73#ibcon#read 3, iclass 24, count 0 2006.201.02:07:16.73#ibcon#about to read 4, iclass 24, count 0 2006.201.02:07:16.73#ibcon#read 4, iclass 24, count 0 2006.201.02:07:16.73#ibcon#about to read 5, iclass 24, count 0 2006.201.02:07:16.73#ibcon#read 5, iclass 24, count 0 2006.201.02:07:16.73#ibcon#about to read 6, iclass 24, count 0 2006.201.02:07:16.73#ibcon#read 6, iclass 24, count 0 2006.201.02:07:16.73#ibcon#end of sib2, iclass 24, count 0 2006.201.02:07:16.73#ibcon#*mode == 0, iclass 24, count 0 2006.201.02:07:16.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.02:07:16.73#ibcon#[25=USB\r\n] 2006.201.02:07:16.73#ibcon#*before write, iclass 24, count 0 2006.201.02:07:16.73#ibcon#enter sib2, iclass 24, count 0 2006.201.02:07:16.73#ibcon#flushed, iclass 24, count 0 2006.201.02:07:16.73#ibcon#about to write, iclass 24, count 0 2006.201.02:07:16.73#ibcon#wrote, iclass 24, count 0 2006.201.02:07:16.73#ibcon#about to read 3, iclass 24, count 0 2006.201.02:07:16.76#ibcon#read 3, iclass 24, count 0 2006.201.02:07:16.76#ibcon#about to read 4, iclass 24, count 0 2006.201.02:07:16.76#ibcon#read 4, iclass 24, count 0 2006.201.02:07:16.76#ibcon#about to read 5, iclass 24, count 0 2006.201.02:07:16.76#ibcon#read 5, iclass 24, count 0 2006.201.02:07:16.76#ibcon#about to read 6, iclass 24, count 0 2006.201.02:07:16.76#ibcon#read 6, iclass 24, count 0 2006.201.02:07:16.76#ibcon#end of sib2, iclass 24, count 0 2006.201.02:07:16.76#ibcon#*after write, iclass 24, count 0 2006.201.02:07:16.76#ibcon#*before return 0, iclass 24, count 0 2006.201.02:07:16.76#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:16.76#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:16.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.02:07:16.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.02:07:16.76$vck44/valo=3,564.99 2006.201.02:07:16.76#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.02:07:16.76#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.02:07:16.76#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:16.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:16.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:16.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:16.76#ibcon#enter wrdev, iclass 26, count 0 2006.201.02:07:16.76#ibcon#first serial, iclass 26, count 0 2006.201.02:07:16.76#ibcon#enter sib2, iclass 26, count 0 2006.201.02:07:16.76#ibcon#flushed, iclass 26, count 0 2006.201.02:07:16.76#ibcon#about to write, iclass 26, count 0 2006.201.02:07:16.76#ibcon#wrote, iclass 26, count 0 2006.201.02:07:16.76#ibcon#about to read 3, iclass 26, count 0 2006.201.02:07:16.78#ibcon#read 3, iclass 26, count 0 2006.201.02:07:16.78#ibcon#about to read 4, iclass 26, count 0 2006.201.02:07:16.78#ibcon#read 4, iclass 26, count 0 2006.201.02:07:16.78#ibcon#about to read 5, iclass 26, count 0 2006.201.02:07:16.78#ibcon#read 5, iclass 26, count 0 2006.201.02:07:16.78#ibcon#about to read 6, iclass 26, count 0 2006.201.02:07:16.78#ibcon#read 6, iclass 26, count 0 2006.201.02:07:16.78#ibcon#end of sib2, iclass 26, count 0 2006.201.02:07:16.78#ibcon#*mode == 0, iclass 26, count 0 2006.201.02:07:16.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.02:07:16.78#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:07:16.78#ibcon#*before write, iclass 26, count 0 2006.201.02:07:16.78#ibcon#enter sib2, iclass 26, count 0 2006.201.02:07:16.78#ibcon#flushed, iclass 26, count 0 2006.201.02:07:16.78#ibcon#about to write, iclass 26, count 0 2006.201.02:07:16.78#ibcon#wrote, iclass 26, count 0 2006.201.02:07:16.78#ibcon#about to read 3, iclass 26, count 0 2006.201.02:07:16.83#ibcon#read 3, iclass 26, count 0 2006.201.02:07:16.83#ibcon#about to read 4, iclass 26, count 0 2006.201.02:07:16.83#ibcon#read 4, iclass 26, count 0 2006.201.02:07:16.83#ibcon#about to read 5, iclass 26, count 0 2006.201.02:07:16.83#ibcon#read 5, iclass 26, count 0 2006.201.02:07:16.83#ibcon#about to read 6, iclass 26, count 0 2006.201.02:07:16.83#ibcon#read 6, iclass 26, count 0 2006.201.02:07:16.83#ibcon#end of sib2, iclass 26, count 0 2006.201.02:07:16.83#ibcon#*after write, iclass 26, count 0 2006.201.02:07:16.83#ibcon#*before return 0, iclass 26, count 0 2006.201.02:07:16.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:16.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:16.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.02:07:16.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.02:07:16.83$vck44/va=3,8 2006.201.02:07:16.83#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.02:07:16.83#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.02:07:16.83#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:16.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:16.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:16.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:16.88#ibcon#enter wrdev, iclass 28, count 2 2006.201.02:07:16.88#ibcon#first serial, iclass 28, count 2 2006.201.02:07:16.88#ibcon#enter sib2, iclass 28, count 2 2006.201.02:07:16.88#ibcon#flushed, iclass 28, count 2 2006.201.02:07:16.88#ibcon#about to write, iclass 28, count 2 2006.201.02:07:16.88#ibcon#wrote, iclass 28, count 2 2006.201.02:07:16.88#ibcon#about to read 3, iclass 28, count 2 2006.201.02:07:16.90#ibcon#read 3, iclass 28, count 2 2006.201.02:07:16.90#ibcon#about to read 4, iclass 28, count 2 2006.201.02:07:16.90#ibcon#read 4, iclass 28, count 2 2006.201.02:07:16.90#ibcon#about to read 5, iclass 28, count 2 2006.201.02:07:16.90#ibcon#read 5, iclass 28, count 2 2006.201.02:07:16.90#ibcon#about to read 6, iclass 28, count 2 2006.201.02:07:16.90#ibcon#read 6, iclass 28, count 2 2006.201.02:07:16.90#ibcon#end of sib2, iclass 28, count 2 2006.201.02:07:16.90#ibcon#*mode == 0, iclass 28, count 2 2006.201.02:07:16.90#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.02:07:16.90#ibcon#[25=AT03-08\r\n] 2006.201.02:07:16.90#ibcon#*before write, iclass 28, count 2 2006.201.02:07:16.90#ibcon#enter sib2, iclass 28, count 2 2006.201.02:07:16.90#ibcon#flushed, iclass 28, count 2 2006.201.02:07:16.90#ibcon#about to write, iclass 28, count 2 2006.201.02:07:16.90#ibcon#wrote, iclass 28, count 2 2006.201.02:07:16.90#ibcon#about to read 3, iclass 28, count 2 2006.201.02:07:16.93#ibcon#read 3, iclass 28, count 2 2006.201.02:07:16.93#ibcon#about to read 4, iclass 28, count 2 2006.201.02:07:16.93#ibcon#read 4, iclass 28, count 2 2006.201.02:07:16.93#ibcon#about to read 5, iclass 28, count 2 2006.201.02:07:16.93#ibcon#read 5, iclass 28, count 2 2006.201.02:07:16.93#ibcon#about to read 6, iclass 28, count 2 2006.201.02:07:16.93#ibcon#read 6, iclass 28, count 2 2006.201.02:07:16.93#ibcon#end of sib2, iclass 28, count 2 2006.201.02:07:16.93#ibcon#*after write, iclass 28, count 2 2006.201.02:07:16.93#ibcon#*before return 0, iclass 28, count 2 2006.201.02:07:16.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:16.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:16.93#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.02:07:16.93#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:16.93#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:17.05#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:17.05#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:17.05#ibcon#enter wrdev, iclass 28, count 0 2006.201.02:07:17.05#ibcon#first serial, iclass 28, count 0 2006.201.02:07:17.05#ibcon#enter sib2, iclass 28, count 0 2006.201.02:07:17.05#ibcon#flushed, iclass 28, count 0 2006.201.02:07:17.05#ibcon#about to write, iclass 28, count 0 2006.201.02:07:17.05#ibcon#wrote, iclass 28, count 0 2006.201.02:07:17.05#ibcon#about to read 3, iclass 28, count 0 2006.201.02:07:17.08#ibcon#read 3, iclass 28, count 0 2006.201.02:07:17.08#ibcon#about to read 4, iclass 28, count 0 2006.201.02:07:17.08#ibcon#read 4, iclass 28, count 0 2006.201.02:07:17.08#ibcon#about to read 5, iclass 28, count 0 2006.201.02:07:17.08#ibcon#read 5, iclass 28, count 0 2006.201.02:07:17.08#ibcon#about to read 6, iclass 28, count 0 2006.201.02:07:17.08#ibcon#read 6, iclass 28, count 0 2006.201.02:07:17.08#ibcon#end of sib2, iclass 28, count 0 2006.201.02:07:17.08#ibcon#*mode == 0, iclass 28, count 0 2006.201.02:07:17.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.02:07:17.08#ibcon#[25=USB\r\n] 2006.201.02:07:17.08#ibcon#*before write, iclass 28, count 0 2006.201.02:07:17.08#ibcon#enter sib2, iclass 28, count 0 2006.201.02:07:17.08#ibcon#flushed, iclass 28, count 0 2006.201.02:07:17.08#ibcon#about to write, iclass 28, count 0 2006.201.02:07:17.08#ibcon#wrote, iclass 28, count 0 2006.201.02:07:17.08#ibcon#about to read 3, iclass 28, count 0 2006.201.02:07:17.11#ibcon#read 3, iclass 28, count 0 2006.201.02:07:17.11#ibcon#about to read 4, iclass 28, count 0 2006.201.02:07:17.11#ibcon#read 4, iclass 28, count 0 2006.201.02:07:17.11#ibcon#about to read 5, iclass 28, count 0 2006.201.02:07:17.11#ibcon#read 5, iclass 28, count 0 2006.201.02:07:17.11#ibcon#about to read 6, iclass 28, count 0 2006.201.02:07:17.11#ibcon#read 6, iclass 28, count 0 2006.201.02:07:17.11#ibcon#end of sib2, iclass 28, count 0 2006.201.02:07:17.11#ibcon#*after write, iclass 28, count 0 2006.201.02:07:17.11#ibcon#*before return 0, iclass 28, count 0 2006.201.02:07:17.11#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:17.11#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:17.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.02:07:17.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.02:07:17.11$vck44/valo=4,624.99 2006.201.02:07:17.11#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.02:07:17.11#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.02:07:17.11#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:17.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:17.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:17.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:17.11#ibcon#enter wrdev, iclass 30, count 0 2006.201.02:07:17.11#ibcon#first serial, iclass 30, count 0 2006.201.02:07:17.11#ibcon#enter sib2, iclass 30, count 0 2006.201.02:07:17.11#ibcon#flushed, iclass 30, count 0 2006.201.02:07:17.11#ibcon#about to write, iclass 30, count 0 2006.201.02:07:17.11#ibcon#wrote, iclass 30, count 0 2006.201.02:07:17.11#ibcon#about to read 3, iclass 30, count 0 2006.201.02:07:17.13#ibcon#read 3, iclass 30, count 0 2006.201.02:07:17.13#ibcon#about to read 4, iclass 30, count 0 2006.201.02:07:17.13#ibcon#read 4, iclass 30, count 0 2006.201.02:07:17.13#ibcon#about to read 5, iclass 30, count 0 2006.201.02:07:17.13#ibcon#read 5, iclass 30, count 0 2006.201.02:07:17.13#ibcon#about to read 6, iclass 30, count 0 2006.201.02:07:17.13#ibcon#read 6, iclass 30, count 0 2006.201.02:07:17.13#ibcon#end of sib2, iclass 30, count 0 2006.201.02:07:17.13#ibcon#*mode == 0, iclass 30, count 0 2006.201.02:07:17.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.02:07:17.13#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:07:17.13#ibcon#*before write, iclass 30, count 0 2006.201.02:07:17.13#ibcon#enter sib2, iclass 30, count 0 2006.201.02:07:17.13#ibcon#flushed, iclass 30, count 0 2006.201.02:07:17.13#ibcon#about to write, iclass 30, count 0 2006.201.02:07:17.13#ibcon#wrote, iclass 30, count 0 2006.201.02:07:17.13#ibcon#about to read 3, iclass 30, count 0 2006.201.02:07:17.17#ibcon#read 3, iclass 30, count 0 2006.201.02:07:17.17#ibcon#about to read 4, iclass 30, count 0 2006.201.02:07:17.17#ibcon#read 4, iclass 30, count 0 2006.201.02:07:17.17#ibcon#about to read 5, iclass 30, count 0 2006.201.02:07:17.17#ibcon#read 5, iclass 30, count 0 2006.201.02:07:17.17#ibcon#about to read 6, iclass 30, count 0 2006.201.02:07:17.17#ibcon#read 6, iclass 30, count 0 2006.201.02:07:17.17#ibcon#end of sib2, iclass 30, count 0 2006.201.02:07:17.17#ibcon#*after write, iclass 30, count 0 2006.201.02:07:17.17#ibcon#*before return 0, iclass 30, count 0 2006.201.02:07:17.17#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:17.17#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:17.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.02:07:17.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.02:07:17.17$vck44/va=4,7 2006.201.02:07:17.17#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.02:07:17.17#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.02:07:17.17#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:17.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:17.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:17.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:17.23#ibcon#enter wrdev, iclass 32, count 2 2006.201.02:07:17.23#ibcon#first serial, iclass 32, count 2 2006.201.02:07:17.23#ibcon#enter sib2, iclass 32, count 2 2006.201.02:07:17.23#ibcon#flushed, iclass 32, count 2 2006.201.02:07:17.23#ibcon#about to write, iclass 32, count 2 2006.201.02:07:17.23#ibcon#wrote, iclass 32, count 2 2006.201.02:07:17.23#ibcon#about to read 3, iclass 32, count 2 2006.201.02:07:17.25#ibcon#read 3, iclass 32, count 2 2006.201.02:07:17.25#ibcon#about to read 4, iclass 32, count 2 2006.201.02:07:17.25#ibcon#read 4, iclass 32, count 2 2006.201.02:07:17.25#ibcon#about to read 5, iclass 32, count 2 2006.201.02:07:17.25#ibcon#read 5, iclass 32, count 2 2006.201.02:07:17.25#ibcon#about to read 6, iclass 32, count 2 2006.201.02:07:17.25#ibcon#read 6, iclass 32, count 2 2006.201.02:07:17.25#ibcon#end of sib2, iclass 32, count 2 2006.201.02:07:17.25#ibcon#*mode == 0, iclass 32, count 2 2006.201.02:07:17.25#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.02:07:17.25#ibcon#[25=AT04-07\r\n] 2006.201.02:07:17.25#ibcon#*before write, iclass 32, count 2 2006.201.02:07:17.25#ibcon#enter sib2, iclass 32, count 2 2006.201.02:07:17.25#ibcon#flushed, iclass 32, count 2 2006.201.02:07:17.25#ibcon#about to write, iclass 32, count 2 2006.201.02:07:17.25#ibcon#wrote, iclass 32, count 2 2006.201.02:07:17.25#ibcon#about to read 3, iclass 32, count 2 2006.201.02:07:17.28#ibcon#read 3, iclass 32, count 2 2006.201.02:07:17.28#ibcon#about to read 4, iclass 32, count 2 2006.201.02:07:17.28#ibcon#read 4, iclass 32, count 2 2006.201.02:07:17.28#ibcon#about to read 5, iclass 32, count 2 2006.201.02:07:17.28#ibcon#read 5, iclass 32, count 2 2006.201.02:07:17.28#ibcon#about to read 6, iclass 32, count 2 2006.201.02:07:17.28#ibcon#read 6, iclass 32, count 2 2006.201.02:07:17.28#ibcon#end of sib2, iclass 32, count 2 2006.201.02:07:17.28#ibcon#*after write, iclass 32, count 2 2006.201.02:07:17.28#ibcon#*before return 0, iclass 32, count 2 2006.201.02:07:17.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:17.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:17.28#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.02:07:17.28#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:17.28#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:17.40#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:17.40#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:17.40#ibcon#enter wrdev, iclass 32, count 0 2006.201.02:07:17.40#ibcon#first serial, iclass 32, count 0 2006.201.02:07:17.40#ibcon#enter sib2, iclass 32, count 0 2006.201.02:07:17.40#ibcon#flushed, iclass 32, count 0 2006.201.02:07:17.40#ibcon#about to write, iclass 32, count 0 2006.201.02:07:17.40#ibcon#wrote, iclass 32, count 0 2006.201.02:07:17.40#ibcon#about to read 3, iclass 32, count 0 2006.201.02:07:17.42#ibcon#read 3, iclass 32, count 0 2006.201.02:07:17.42#ibcon#about to read 4, iclass 32, count 0 2006.201.02:07:17.42#ibcon#read 4, iclass 32, count 0 2006.201.02:07:17.42#ibcon#about to read 5, iclass 32, count 0 2006.201.02:07:17.42#ibcon#read 5, iclass 32, count 0 2006.201.02:07:17.42#ibcon#about to read 6, iclass 32, count 0 2006.201.02:07:17.42#ibcon#read 6, iclass 32, count 0 2006.201.02:07:17.42#ibcon#end of sib2, iclass 32, count 0 2006.201.02:07:17.42#ibcon#*mode == 0, iclass 32, count 0 2006.201.02:07:17.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.02:07:17.42#ibcon#[25=USB\r\n] 2006.201.02:07:17.42#ibcon#*before write, iclass 32, count 0 2006.201.02:07:17.42#ibcon#enter sib2, iclass 32, count 0 2006.201.02:07:17.42#ibcon#flushed, iclass 32, count 0 2006.201.02:07:17.42#ibcon#about to write, iclass 32, count 0 2006.201.02:07:17.42#ibcon#wrote, iclass 32, count 0 2006.201.02:07:17.42#ibcon#about to read 3, iclass 32, count 0 2006.201.02:07:17.45#ibcon#read 3, iclass 32, count 0 2006.201.02:07:17.45#ibcon#about to read 4, iclass 32, count 0 2006.201.02:07:17.45#ibcon#read 4, iclass 32, count 0 2006.201.02:07:17.45#ibcon#about to read 5, iclass 32, count 0 2006.201.02:07:17.45#ibcon#read 5, iclass 32, count 0 2006.201.02:07:17.45#ibcon#about to read 6, iclass 32, count 0 2006.201.02:07:17.45#ibcon#read 6, iclass 32, count 0 2006.201.02:07:17.45#ibcon#end of sib2, iclass 32, count 0 2006.201.02:07:17.45#ibcon#*after write, iclass 32, count 0 2006.201.02:07:17.45#ibcon#*before return 0, iclass 32, count 0 2006.201.02:07:17.45#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:17.45#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:17.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.02:07:17.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.02:07:17.45$vck44/valo=5,734.99 2006.201.02:07:17.45#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.02:07:17.45#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.02:07:17.45#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:17.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:17.45#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:17.45#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:17.45#ibcon#enter wrdev, iclass 34, count 0 2006.201.02:07:17.45#ibcon#first serial, iclass 34, count 0 2006.201.02:07:17.45#ibcon#enter sib2, iclass 34, count 0 2006.201.02:07:17.45#ibcon#flushed, iclass 34, count 0 2006.201.02:07:17.45#ibcon#about to write, iclass 34, count 0 2006.201.02:07:17.45#ibcon#wrote, iclass 34, count 0 2006.201.02:07:17.45#ibcon#about to read 3, iclass 34, count 0 2006.201.02:07:17.47#ibcon#read 3, iclass 34, count 0 2006.201.02:07:17.47#ibcon#about to read 4, iclass 34, count 0 2006.201.02:07:17.47#ibcon#read 4, iclass 34, count 0 2006.201.02:07:17.47#ibcon#about to read 5, iclass 34, count 0 2006.201.02:07:17.47#ibcon#read 5, iclass 34, count 0 2006.201.02:07:17.47#ibcon#about to read 6, iclass 34, count 0 2006.201.02:07:17.47#ibcon#read 6, iclass 34, count 0 2006.201.02:07:17.47#ibcon#end of sib2, iclass 34, count 0 2006.201.02:07:17.47#ibcon#*mode == 0, iclass 34, count 0 2006.201.02:07:17.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.02:07:17.47#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:07:17.47#ibcon#*before write, iclass 34, count 0 2006.201.02:07:17.47#ibcon#enter sib2, iclass 34, count 0 2006.201.02:07:17.47#ibcon#flushed, iclass 34, count 0 2006.201.02:07:17.47#ibcon#about to write, iclass 34, count 0 2006.201.02:07:17.47#ibcon#wrote, iclass 34, count 0 2006.201.02:07:17.47#ibcon#about to read 3, iclass 34, count 0 2006.201.02:07:17.51#ibcon#read 3, iclass 34, count 0 2006.201.02:07:17.51#ibcon#about to read 4, iclass 34, count 0 2006.201.02:07:17.51#ibcon#read 4, iclass 34, count 0 2006.201.02:07:17.51#ibcon#about to read 5, iclass 34, count 0 2006.201.02:07:17.51#ibcon#read 5, iclass 34, count 0 2006.201.02:07:17.51#ibcon#about to read 6, iclass 34, count 0 2006.201.02:07:17.51#ibcon#read 6, iclass 34, count 0 2006.201.02:07:17.51#ibcon#end of sib2, iclass 34, count 0 2006.201.02:07:17.51#ibcon#*after write, iclass 34, count 0 2006.201.02:07:17.51#ibcon#*before return 0, iclass 34, count 0 2006.201.02:07:17.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:17.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:17.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.02:07:17.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.02:07:17.51$vck44/va=5,4 2006.201.02:07:17.51#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.02:07:17.51#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.02:07:17.51#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:17.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:17.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:17.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:17.57#ibcon#enter wrdev, iclass 36, count 2 2006.201.02:07:17.57#ibcon#first serial, iclass 36, count 2 2006.201.02:07:17.57#ibcon#enter sib2, iclass 36, count 2 2006.201.02:07:17.57#ibcon#flushed, iclass 36, count 2 2006.201.02:07:17.57#ibcon#about to write, iclass 36, count 2 2006.201.02:07:17.57#ibcon#wrote, iclass 36, count 2 2006.201.02:07:17.57#ibcon#about to read 3, iclass 36, count 2 2006.201.02:07:17.59#ibcon#read 3, iclass 36, count 2 2006.201.02:07:17.59#ibcon#about to read 4, iclass 36, count 2 2006.201.02:07:17.59#ibcon#read 4, iclass 36, count 2 2006.201.02:07:17.59#ibcon#about to read 5, iclass 36, count 2 2006.201.02:07:17.59#ibcon#read 5, iclass 36, count 2 2006.201.02:07:17.59#ibcon#about to read 6, iclass 36, count 2 2006.201.02:07:17.59#ibcon#read 6, iclass 36, count 2 2006.201.02:07:17.59#ibcon#end of sib2, iclass 36, count 2 2006.201.02:07:17.59#ibcon#*mode == 0, iclass 36, count 2 2006.201.02:07:17.59#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.02:07:17.59#ibcon#[25=AT05-04\r\n] 2006.201.02:07:17.59#ibcon#*before write, iclass 36, count 2 2006.201.02:07:17.59#ibcon#enter sib2, iclass 36, count 2 2006.201.02:07:17.59#ibcon#flushed, iclass 36, count 2 2006.201.02:07:17.59#ibcon#about to write, iclass 36, count 2 2006.201.02:07:17.59#ibcon#wrote, iclass 36, count 2 2006.201.02:07:17.59#ibcon#about to read 3, iclass 36, count 2 2006.201.02:07:17.62#ibcon#read 3, iclass 36, count 2 2006.201.02:07:17.62#ibcon#about to read 4, iclass 36, count 2 2006.201.02:07:17.62#ibcon#read 4, iclass 36, count 2 2006.201.02:07:17.62#ibcon#about to read 5, iclass 36, count 2 2006.201.02:07:17.62#ibcon#read 5, iclass 36, count 2 2006.201.02:07:17.62#ibcon#about to read 6, iclass 36, count 2 2006.201.02:07:17.62#ibcon#read 6, iclass 36, count 2 2006.201.02:07:17.62#ibcon#end of sib2, iclass 36, count 2 2006.201.02:07:17.62#ibcon#*after write, iclass 36, count 2 2006.201.02:07:17.62#ibcon#*before return 0, iclass 36, count 2 2006.201.02:07:17.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:17.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:17.62#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.02:07:17.62#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:17.62#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:17.74#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:17.74#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:17.74#ibcon#enter wrdev, iclass 36, count 0 2006.201.02:07:17.74#ibcon#first serial, iclass 36, count 0 2006.201.02:07:17.74#ibcon#enter sib2, iclass 36, count 0 2006.201.02:07:17.74#ibcon#flushed, iclass 36, count 0 2006.201.02:07:17.74#ibcon#about to write, iclass 36, count 0 2006.201.02:07:17.74#ibcon#wrote, iclass 36, count 0 2006.201.02:07:17.74#ibcon#about to read 3, iclass 36, count 0 2006.201.02:07:17.76#ibcon#read 3, iclass 36, count 0 2006.201.02:07:17.76#ibcon#about to read 4, iclass 36, count 0 2006.201.02:07:17.76#ibcon#read 4, iclass 36, count 0 2006.201.02:07:17.76#ibcon#about to read 5, iclass 36, count 0 2006.201.02:07:17.76#ibcon#read 5, iclass 36, count 0 2006.201.02:07:17.76#ibcon#about to read 6, iclass 36, count 0 2006.201.02:07:17.76#ibcon#read 6, iclass 36, count 0 2006.201.02:07:17.76#ibcon#end of sib2, iclass 36, count 0 2006.201.02:07:17.76#ibcon#*mode == 0, iclass 36, count 0 2006.201.02:07:17.76#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.02:07:17.76#ibcon#[25=USB\r\n] 2006.201.02:07:17.76#ibcon#*before write, iclass 36, count 0 2006.201.02:07:17.76#ibcon#enter sib2, iclass 36, count 0 2006.201.02:07:17.76#ibcon#flushed, iclass 36, count 0 2006.201.02:07:17.76#ibcon#about to write, iclass 36, count 0 2006.201.02:07:17.76#ibcon#wrote, iclass 36, count 0 2006.201.02:07:17.76#ibcon#about to read 3, iclass 36, count 0 2006.201.02:07:17.79#ibcon#read 3, iclass 36, count 0 2006.201.02:07:17.79#ibcon#about to read 4, iclass 36, count 0 2006.201.02:07:17.79#ibcon#read 4, iclass 36, count 0 2006.201.02:07:17.79#ibcon#about to read 5, iclass 36, count 0 2006.201.02:07:17.79#ibcon#read 5, iclass 36, count 0 2006.201.02:07:17.79#ibcon#about to read 6, iclass 36, count 0 2006.201.02:07:17.79#ibcon#read 6, iclass 36, count 0 2006.201.02:07:17.79#ibcon#end of sib2, iclass 36, count 0 2006.201.02:07:17.79#ibcon#*after write, iclass 36, count 0 2006.201.02:07:17.79#ibcon#*before return 0, iclass 36, count 0 2006.201.02:07:17.79#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:17.79#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:17.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.02:07:17.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.02:07:17.79$vck44/valo=6,814.99 2006.201.02:07:17.79#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.02:07:17.79#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.02:07:17.79#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:17.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:17.79#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:17.79#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:17.79#ibcon#enter wrdev, iclass 38, count 0 2006.201.02:07:17.79#ibcon#first serial, iclass 38, count 0 2006.201.02:07:17.79#ibcon#enter sib2, iclass 38, count 0 2006.201.02:07:17.79#ibcon#flushed, iclass 38, count 0 2006.201.02:07:17.79#ibcon#about to write, iclass 38, count 0 2006.201.02:07:17.79#ibcon#wrote, iclass 38, count 0 2006.201.02:07:17.79#ibcon#about to read 3, iclass 38, count 0 2006.201.02:07:17.81#ibcon#read 3, iclass 38, count 0 2006.201.02:07:17.81#ibcon#about to read 4, iclass 38, count 0 2006.201.02:07:17.81#ibcon#read 4, iclass 38, count 0 2006.201.02:07:17.81#ibcon#about to read 5, iclass 38, count 0 2006.201.02:07:17.81#ibcon#read 5, iclass 38, count 0 2006.201.02:07:17.81#ibcon#about to read 6, iclass 38, count 0 2006.201.02:07:17.81#ibcon#read 6, iclass 38, count 0 2006.201.02:07:17.81#ibcon#end of sib2, iclass 38, count 0 2006.201.02:07:17.81#ibcon#*mode == 0, iclass 38, count 0 2006.201.02:07:17.81#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.02:07:17.81#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:07:17.81#ibcon#*before write, iclass 38, count 0 2006.201.02:07:17.81#ibcon#enter sib2, iclass 38, count 0 2006.201.02:07:17.81#ibcon#flushed, iclass 38, count 0 2006.201.02:07:17.81#ibcon#about to write, iclass 38, count 0 2006.201.02:07:17.81#ibcon#wrote, iclass 38, count 0 2006.201.02:07:17.81#ibcon#about to read 3, iclass 38, count 0 2006.201.02:07:17.85#ibcon#read 3, iclass 38, count 0 2006.201.02:07:17.85#ibcon#about to read 4, iclass 38, count 0 2006.201.02:07:17.85#ibcon#read 4, iclass 38, count 0 2006.201.02:07:17.85#ibcon#about to read 5, iclass 38, count 0 2006.201.02:07:17.85#ibcon#read 5, iclass 38, count 0 2006.201.02:07:17.85#ibcon#about to read 6, iclass 38, count 0 2006.201.02:07:17.85#ibcon#read 6, iclass 38, count 0 2006.201.02:07:17.85#ibcon#end of sib2, iclass 38, count 0 2006.201.02:07:17.85#ibcon#*after write, iclass 38, count 0 2006.201.02:07:17.85#ibcon#*before return 0, iclass 38, count 0 2006.201.02:07:17.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:17.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:17.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.02:07:17.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.02:07:17.85$vck44/va=6,5 2006.201.02:07:17.85#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.02:07:17.85#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.02:07:17.85#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:17.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:17.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:17.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:17.91#ibcon#enter wrdev, iclass 40, count 2 2006.201.02:07:17.91#ibcon#first serial, iclass 40, count 2 2006.201.02:07:17.91#ibcon#enter sib2, iclass 40, count 2 2006.201.02:07:17.91#ibcon#flushed, iclass 40, count 2 2006.201.02:07:17.91#ibcon#about to write, iclass 40, count 2 2006.201.02:07:17.91#ibcon#wrote, iclass 40, count 2 2006.201.02:07:17.91#ibcon#about to read 3, iclass 40, count 2 2006.201.02:07:17.93#ibcon#read 3, iclass 40, count 2 2006.201.02:07:17.93#ibcon#about to read 4, iclass 40, count 2 2006.201.02:07:17.93#ibcon#read 4, iclass 40, count 2 2006.201.02:07:17.93#ibcon#about to read 5, iclass 40, count 2 2006.201.02:07:17.93#ibcon#read 5, iclass 40, count 2 2006.201.02:07:17.93#ibcon#about to read 6, iclass 40, count 2 2006.201.02:07:17.93#ibcon#read 6, iclass 40, count 2 2006.201.02:07:17.93#ibcon#end of sib2, iclass 40, count 2 2006.201.02:07:17.93#ibcon#*mode == 0, iclass 40, count 2 2006.201.02:07:17.93#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.02:07:17.93#ibcon#[25=AT06-05\r\n] 2006.201.02:07:17.93#ibcon#*before write, iclass 40, count 2 2006.201.02:07:17.93#ibcon#enter sib2, iclass 40, count 2 2006.201.02:07:17.93#ibcon#flushed, iclass 40, count 2 2006.201.02:07:17.93#ibcon#about to write, iclass 40, count 2 2006.201.02:07:17.93#ibcon#wrote, iclass 40, count 2 2006.201.02:07:17.93#ibcon#about to read 3, iclass 40, count 2 2006.201.02:07:17.96#ibcon#read 3, iclass 40, count 2 2006.201.02:07:17.96#ibcon#about to read 4, iclass 40, count 2 2006.201.02:07:17.96#ibcon#read 4, iclass 40, count 2 2006.201.02:07:17.96#ibcon#about to read 5, iclass 40, count 2 2006.201.02:07:17.96#ibcon#read 5, iclass 40, count 2 2006.201.02:07:17.96#ibcon#about to read 6, iclass 40, count 2 2006.201.02:07:17.96#ibcon#read 6, iclass 40, count 2 2006.201.02:07:17.96#ibcon#end of sib2, iclass 40, count 2 2006.201.02:07:17.96#ibcon#*after write, iclass 40, count 2 2006.201.02:07:17.96#ibcon#*before return 0, iclass 40, count 2 2006.201.02:07:17.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:17.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:17.96#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.02:07:17.96#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:17.96#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:18.08#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:18.08#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:18.08#ibcon#enter wrdev, iclass 40, count 0 2006.201.02:07:18.08#ibcon#first serial, iclass 40, count 0 2006.201.02:07:18.08#ibcon#enter sib2, iclass 40, count 0 2006.201.02:07:18.08#ibcon#flushed, iclass 40, count 0 2006.201.02:07:18.08#ibcon#about to write, iclass 40, count 0 2006.201.02:07:18.08#ibcon#wrote, iclass 40, count 0 2006.201.02:07:18.08#ibcon#about to read 3, iclass 40, count 0 2006.201.02:07:18.10#ibcon#read 3, iclass 40, count 0 2006.201.02:07:18.10#ibcon#about to read 4, iclass 40, count 0 2006.201.02:07:18.10#ibcon#read 4, iclass 40, count 0 2006.201.02:07:18.10#ibcon#about to read 5, iclass 40, count 0 2006.201.02:07:18.10#ibcon#read 5, iclass 40, count 0 2006.201.02:07:18.10#ibcon#about to read 6, iclass 40, count 0 2006.201.02:07:18.10#ibcon#read 6, iclass 40, count 0 2006.201.02:07:18.10#ibcon#end of sib2, iclass 40, count 0 2006.201.02:07:18.10#ibcon#*mode == 0, iclass 40, count 0 2006.201.02:07:18.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.02:07:18.10#ibcon#[25=USB\r\n] 2006.201.02:07:18.10#ibcon#*before write, iclass 40, count 0 2006.201.02:07:18.10#ibcon#enter sib2, iclass 40, count 0 2006.201.02:07:18.10#ibcon#flushed, iclass 40, count 0 2006.201.02:07:18.10#ibcon#about to write, iclass 40, count 0 2006.201.02:07:18.10#ibcon#wrote, iclass 40, count 0 2006.201.02:07:18.10#ibcon#about to read 3, iclass 40, count 0 2006.201.02:07:18.13#ibcon#read 3, iclass 40, count 0 2006.201.02:07:18.13#ibcon#about to read 4, iclass 40, count 0 2006.201.02:07:18.13#ibcon#read 4, iclass 40, count 0 2006.201.02:07:18.13#ibcon#about to read 5, iclass 40, count 0 2006.201.02:07:18.13#ibcon#read 5, iclass 40, count 0 2006.201.02:07:18.13#ibcon#about to read 6, iclass 40, count 0 2006.201.02:07:18.13#ibcon#read 6, iclass 40, count 0 2006.201.02:07:18.13#ibcon#end of sib2, iclass 40, count 0 2006.201.02:07:18.13#ibcon#*after write, iclass 40, count 0 2006.201.02:07:18.13#ibcon#*before return 0, iclass 40, count 0 2006.201.02:07:18.13#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:18.13#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:18.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.02:07:18.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.02:07:18.13$vck44/valo=7,864.99 2006.201.02:07:18.13#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.02:07:18.13#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.02:07:18.13#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:18.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:07:18.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:07:18.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:07:18.13#ibcon#enter wrdev, iclass 4, count 0 2006.201.02:07:18.13#ibcon#first serial, iclass 4, count 0 2006.201.02:07:18.13#ibcon#enter sib2, iclass 4, count 0 2006.201.02:07:18.13#ibcon#flushed, iclass 4, count 0 2006.201.02:07:18.13#ibcon#about to write, iclass 4, count 0 2006.201.02:07:18.13#ibcon#wrote, iclass 4, count 0 2006.201.02:07:18.13#ibcon#about to read 3, iclass 4, count 0 2006.201.02:07:18.15#ibcon#read 3, iclass 4, count 0 2006.201.02:07:18.15#ibcon#about to read 4, iclass 4, count 0 2006.201.02:07:18.15#ibcon#read 4, iclass 4, count 0 2006.201.02:07:18.15#ibcon#about to read 5, iclass 4, count 0 2006.201.02:07:18.15#ibcon#read 5, iclass 4, count 0 2006.201.02:07:18.15#ibcon#about to read 6, iclass 4, count 0 2006.201.02:07:18.15#ibcon#read 6, iclass 4, count 0 2006.201.02:07:18.15#ibcon#end of sib2, iclass 4, count 0 2006.201.02:07:18.15#ibcon#*mode == 0, iclass 4, count 0 2006.201.02:07:18.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.02:07:18.15#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:07:18.15#ibcon#*before write, iclass 4, count 0 2006.201.02:07:18.15#ibcon#enter sib2, iclass 4, count 0 2006.201.02:07:18.15#ibcon#flushed, iclass 4, count 0 2006.201.02:07:18.15#ibcon#about to write, iclass 4, count 0 2006.201.02:07:18.15#ibcon#wrote, iclass 4, count 0 2006.201.02:07:18.15#ibcon#about to read 3, iclass 4, count 0 2006.201.02:07:18.19#ibcon#read 3, iclass 4, count 0 2006.201.02:07:18.19#ibcon#about to read 4, iclass 4, count 0 2006.201.02:07:18.19#ibcon#read 4, iclass 4, count 0 2006.201.02:07:18.19#ibcon#about to read 5, iclass 4, count 0 2006.201.02:07:18.19#ibcon#read 5, iclass 4, count 0 2006.201.02:07:18.19#ibcon#about to read 6, iclass 4, count 0 2006.201.02:07:18.19#ibcon#read 6, iclass 4, count 0 2006.201.02:07:18.19#ibcon#end of sib2, iclass 4, count 0 2006.201.02:07:18.19#ibcon#*after write, iclass 4, count 0 2006.201.02:07:18.19#ibcon#*before return 0, iclass 4, count 0 2006.201.02:07:18.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:07:18.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:07:18.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.02:07:18.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.02:07:18.19$vck44/va=7,5 2006.201.02:07:18.19#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.02:07:18.19#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.02:07:18.19#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:18.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:07:18.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:07:18.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:07:18.25#ibcon#enter wrdev, iclass 6, count 2 2006.201.02:07:18.25#ibcon#first serial, iclass 6, count 2 2006.201.02:07:18.25#ibcon#enter sib2, iclass 6, count 2 2006.201.02:07:18.25#ibcon#flushed, iclass 6, count 2 2006.201.02:07:18.25#ibcon#about to write, iclass 6, count 2 2006.201.02:07:18.25#ibcon#wrote, iclass 6, count 2 2006.201.02:07:18.25#ibcon#about to read 3, iclass 6, count 2 2006.201.02:07:18.27#ibcon#read 3, iclass 6, count 2 2006.201.02:07:18.27#ibcon#about to read 4, iclass 6, count 2 2006.201.02:07:18.27#ibcon#read 4, iclass 6, count 2 2006.201.02:07:18.27#ibcon#about to read 5, iclass 6, count 2 2006.201.02:07:18.27#ibcon#read 5, iclass 6, count 2 2006.201.02:07:18.27#ibcon#about to read 6, iclass 6, count 2 2006.201.02:07:18.27#ibcon#read 6, iclass 6, count 2 2006.201.02:07:18.27#ibcon#end of sib2, iclass 6, count 2 2006.201.02:07:18.27#ibcon#*mode == 0, iclass 6, count 2 2006.201.02:07:18.27#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.02:07:18.27#ibcon#[25=AT07-05\r\n] 2006.201.02:07:18.27#ibcon#*before write, iclass 6, count 2 2006.201.02:07:18.27#ibcon#enter sib2, iclass 6, count 2 2006.201.02:07:18.27#ibcon#flushed, iclass 6, count 2 2006.201.02:07:18.27#ibcon#about to write, iclass 6, count 2 2006.201.02:07:18.27#ibcon#wrote, iclass 6, count 2 2006.201.02:07:18.27#ibcon#about to read 3, iclass 6, count 2 2006.201.02:07:18.30#ibcon#read 3, iclass 6, count 2 2006.201.02:07:18.30#ibcon#about to read 4, iclass 6, count 2 2006.201.02:07:18.30#ibcon#read 4, iclass 6, count 2 2006.201.02:07:18.30#ibcon#about to read 5, iclass 6, count 2 2006.201.02:07:18.30#ibcon#read 5, iclass 6, count 2 2006.201.02:07:18.30#ibcon#about to read 6, iclass 6, count 2 2006.201.02:07:18.30#ibcon#read 6, iclass 6, count 2 2006.201.02:07:18.30#ibcon#end of sib2, iclass 6, count 2 2006.201.02:07:18.30#ibcon#*after write, iclass 6, count 2 2006.201.02:07:18.30#ibcon#*before return 0, iclass 6, count 2 2006.201.02:07:18.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:07:18.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:07:18.30#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.02:07:18.30#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:18.30#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:07:18.42#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:07:18.42#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:07:18.42#ibcon#enter wrdev, iclass 6, count 0 2006.201.02:07:18.42#ibcon#first serial, iclass 6, count 0 2006.201.02:07:18.42#ibcon#enter sib2, iclass 6, count 0 2006.201.02:07:18.42#ibcon#flushed, iclass 6, count 0 2006.201.02:07:18.42#ibcon#about to write, iclass 6, count 0 2006.201.02:07:18.42#ibcon#wrote, iclass 6, count 0 2006.201.02:07:18.42#ibcon#about to read 3, iclass 6, count 0 2006.201.02:07:18.44#ibcon#read 3, iclass 6, count 0 2006.201.02:07:18.44#ibcon#about to read 4, iclass 6, count 0 2006.201.02:07:18.44#ibcon#read 4, iclass 6, count 0 2006.201.02:07:18.44#ibcon#about to read 5, iclass 6, count 0 2006.201.02:07:18.44#ibcon#read 5, iclass 6, count 0 2006.201.02:07:18.44#ibcon#about to read 6, iclass 6, count 0 2006.201.02:07:18.44#ibcon#read 6, iclass 6, count 0 2006.201.02:07:18.44#ibcon#end of sib2, iclass 6, count 0 2006.201.02:07:18.44#ibcon#*mode == 0, iclass 6, count 0 2006.201.02:07:18.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.02:07:18.44#ibcon#[25=USB\r\n] 2006.201.02:07:18.44#ibcon#*before write, iclass 6, count 0 2006.201.02:07:18.44#ibcon#enter sib2, iclass 6, count 0 2006.201.02:07:18.44#ibcon#flushed, iclass 6, count 0 2006.201.02:07:18.44#ibcon#about to write, iclass 6, count 0 2006.201.02:07:18.44#ibcon#wrote, iclass 6, count 0 2006.201.02:07:18.44#ibcon#about to read 3, iclass 6, count 0 2006.201.02:07:18.47#ibcon#read 3, iclass 6, count 0 2006.201.02:07:18.47#ibcon#about to read 4, iclass 6, count 0 2006.201.02:07:18.47#ibcon#read 4, iclass 6, count 0 2006.201.02:07:18.47#ibcon#about to read 5, iclass 6, count 0 2006.201.02:07:18.47#ibcon#read 5, iclass 6, count 0 2006.201.02:07:18.47#ibcon#about to read 6, iclass 6, count 0 2006.201.02:07:18.47#ibcon#read 6, iclass 6, count 0 2006.201.02:07:18.47#ibcon#end of sib2, iclass 6, count 0 2006.201.02:07:18.47#ibcon#*after write, iclass 6, count 0 2006.201.02:07:18.47#ibcon#*before return 0, iclass 6, count 0 2006.201.02:07:18.47#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:07:18.47#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:07:18.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.02:07:18.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.02:07:18.47$vck44/valo=8,884.99 2006.201.02:07:18.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.02:07:18.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.02:07:18.47#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:18.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:07:18.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:07:18.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:07:18.47#ibcon#enter wrdev, iclass 10, count 0 2006.201.02:07:18.47#ibcon#first serial, iclass 10, count 0 2006.201.02:07:18.47#ibcon#enter sib2, iclass 10, count 0 2006.201.02:07:18.47#ibcon#flushed, iclass 10, count 0 2006.201.02:07:18.47#ibcon#about to write, iclass 10, count 0 2006.201.02:07:18.47#ibcon#wrote, iclass 10, count 0 2006.201.02:07:18.47#ibcon#about to read 3, iclass 10, count 0 2006.201.02:07:18.49#ibcon#read 3, iclass 10, count 0 2006.201.02:07:18.49#ibcon#about to read 4, iclass 10, count 0 2006.201.02:07:18.49#ibcon#read 4, iclass 10, count 0 2006.201.02:07:18.49#ibcon#about to read 5, iclass 10, count 0 2006.201.02:07:18.49#ibcon#read 5, iclass 10, count 0 2006.201.02:07:18.49#ibcon#about to read 6, iclass 10, count 0 2006.201.02:07:18.49#ibcon#read 6, iclass 10, count 0 2006.201.02:07:18.49#ibcon#end of sib2, iclass 10, count 0 2006.201.02:07:18.49#ibcon#*mode == 0, iclass 10, count 0 2006.201.02:07:18.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.02:07:18.49#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:07:18.49#ibcon#*before write, iclass 10, count 0 2006.201.02:07:18.49#ibcon#enter sib2, iclass 10, count 0 2006.201.02:07:18.49#ibcon#flushed, iclass 10, count 0 2006.201.02:07:18.49#ibcon#about to write, iclass 10, count 0 2006.201.02:07:18.49#ibcon#wrote, iclass 10, count 0 2006.201.02:07:18.49#ibcon#about to read 3, iclass 10, count 0 2006.201.02:07:18.53#ibcon#read 3, iclass 10, count 0 2006.201.02:07:18.53#ibcon#about to read 4, iclass 10, count 0 2006.201.02:07:18.53#ibcon#read 4, iclass 10, count 0 2006.201.02:07:18.53#ibcon#about to read 5, iclass 10, count 0 2006.201.02:07:18.53#ibcon#read 5, iclass 10, count 0 2006.201.02:07:18.53#ibcon#about to read 6, iclass 10, count 0 2006.201.02:07:18.53#ibcon#read 6, iclass 10, count 0 2006.201.02:07:18.53#ibcon#end of sib2, iclass 10, count 0 2006.201.02:07:18.53#ibcon#*after write, iclass 10, count 0 2006.201.02:07:18.53#ibcon#*before return 0, iclass 10, count 0 2006.201.02:07:18.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:07:18.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:07:18.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.02:07:18.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.02:07:18.53$vck44/va=8,4 2006.201.02:07:18.53#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.02:07:18.53#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.02:07:18.53#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:18.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:07:18.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:07:18.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:07:18.59#ibcon#enter wrdev, iclass 12, count 2 2006.201.02:07:18.59#ibcon#first serial, iclass 12, count 2 2006.201.02:07:18.59#ibcon#enter sib2, iclass 12, count 2 2006.201.02:07:18.59#ibcon#flushed, iclass 12, count 2 2006.201.02:07:18.59#ibcon#about to write, iclass 12, count 2 2006.201.02:07:18.59#ibcon#wrote, iclass 12, count 2 2006.201.02:07:18.59#ibcon#about to read 3, iclass 12, count 2 2006.201.02:07:18.61#ibcon#read 3, iclass 12, count 2 2006.201.02:07:18.61#ibcon#about to read 4, iclass 12, count 2 2006.201.02:07:18.61#ibcon#read 4, iclass 12, count 2 2006.201.02:07:18.61#ibcon#about to read 5, iclass 12, count 2 2006.201.02:07:18.61#ibcon#read 5, iclass 12, count 2 2006.201.02:07:18.61#ibcon#about to read 6, iclass 12, count 2 2006.201.02:07:18.61#ibcon#read 6, iclass 12, count 2 2006.201.02:07:18.61#ibcon#end of sib2, iclass 12, count 2 2006.201.02:07:18.61#ibcon#*mode == 0, iclass 12, count 2 2006.201.02:07:18.61#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.02:07:18.61#ibcon#[25=AT08-04\r\n] 2006.201.02:07:18.61#ibcon#*before write, iclass 12, count 2 2006.201.02:07:18.61#ibcon#enter sib2, iclass 12, count 2 2006.201.02:07:18.61#ibcon#flushed, iclass 12, count 2 2006.201.02:07:18.61#ibcon#about to write, iclass 12, count 2 2006.201.02:07:18.61#ibcon#wrote, iclass 12, count 2 2006.201.02:07:18.61#ibcon#about to read 3, iclass 12, count 2 2006.201.02:07:18.64#ibcon#read 3, iclass 12, count 2 2006.201.02:07:18.64#ibcon#about to read 4, iclass 12, count 2 2006.201.02:07:18.64#ibcon#read 4, iclass 12, count 2 2006.201.02:07:18.64#ibcon#about to read 5, iclass 12, count 2 2006.201.02:07:18.64#ibcon#read 5, iclass 12, count 2 2006.201.02:07:18.64#ibcon#about to read 6, iclass 12, count 2 2006.201.02:07:18.64#ibcon#read 6, iclass 12, count 2 2006.201.02:07:18.64#ibcon#end of sib2, iclass 12, count 2 2006.201.02:07:18.64#ibcon#*after write, iclass 12, count 2 2006.201.02:07:18.64#ibcon#*before return 0, iclass 12, count 2 2006.201.02:07:18.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:07:18.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:07:18.64#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.02:07:18.64#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:18.64#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:07:18.76#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:07:18.76#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:07:18.76#ibcon#enter wrdev, iclass 12, count 0 2006.201.02:07:18.76#ibcon#first serial, iclass 12, count 0 2006.201.02:07:18.76#ibcon#enter sib2, iclass 12, count 0 2006.201.02:07:18.76#ibcon#flushed, iclass 12, count 0 2006.201.02:07:18.76#ibcon#about to write, iclass 12, count 0 2006.201.02:07:18.76#ibcon#wrote, iclass 12, count 0 2006.201.02:07:18.76#ibcon#about to read 3, iclass 12, count 0 2006.201.02:07:18.78#ibcon#read 3, iclass 12, count 0 2006.201.02:07:18.78#ibcon#about to read 4, iclass 12, count 0 2006.201.02:07:18.78#ibcon#read 4, iclass 12, count 0 2006.201.02:07:18.78#ibcon#about to read 5, iclass 12, count 0 2006.201.02:07:18.78#ibcon#read 5, iclass 12, count 0 2006.201.02:07:18.78#ibcon#about to read 6, iclass 12, count 0 2006.201.02:07:18.78#ibcon#read 6, iclass 12, count 0 2006.201.02:07:18.78#ibcon#end of sib2, iclass 12, count 0 2006.201.02:07:18.78#ibcon#*mode == 0, iclass 12, count 0 2006.201.02:07:18.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.02:07:18.78#ibcon#[25=USB\r\n] 2006.201.02:07:18.78#ibcon#*before write, iclass 12, count 0 2006.201.02:07:18.78#ibcon#enter sib2, iclass 12, count 0 2006.201.02:07:18.78#ibcon#flushed, iclass 12, count 0 2006.201.02:07:18.78#ibcon#about to write, iclass 12, count 0 2006.201.02:07:18.78#ibcon#wrote, iclass 12, count 0 2006.201.02:07:18.78#ibcon#about to read 3, iclass 12, count 0 2006.201.02:07:18.81#ibcon#read 3, iclass 12, count 0 2006.201.02:07:18.81#ibcon#about to read 4, iclass 12, count 0 2006.201.02:07:18.81#ibcon#read 4, iclass 12, count 0 2006.201.02:07:18.81#ibcon#about to read 5, iclass 12, count 0 2006.201.02:07:18.81#ibcon#read 5, iclass 12, count 0 2006.201.02:07:18.81#ibcon#about to read 6, iclass 12, count 0 2006.201.02:07:18.81#ibcon#read 6, iclass 12, count 0 2006.201.02:07:18.81#ibcon#end of sib2, iclass 12, count 0 2006.201.02:07:18.81#ibcon#*after write, iclass 12, count 0 2006.201.02:07:18.81#ibcon#*before return 0, iclass 12, count 0 2006.201.02:07:18.81#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:07:18.81#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:07:18.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.02:07:18.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.02:07:18.81$vck44/vblo=1,629.99 2006.201.02:07:18.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.02:07:18.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.02:07:18.81#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:18.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:18.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:18.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:18.81#ibcon#enter wrdev, iclass 14, count 0 2006.201.02:07:18.81#ibcon#first serial, iclass 14, count 0 2006.201.02:07:18.81#ibcon#enter sib2, iclass 14, count 0 2006.201.02:07:18.81#ibcon#flushed, iclass 14, count 0 2006.201.02:07:18.81#ibcon#about to write, iclass 14, count 0 2006.201.02:07:18.81#ibcon#wrote, iclass 14, count 0 2006.201.02:07:18.81#ibcon#about to read 3, iclass 14, count 0 2006.201.02:07:18.83#ibcon#read 3, iclass 14, count 0 2006.201.02:07:18.83#ibcon#about to read 4, iclass 14, count 0 2006.201.02:07:18.83#ibcon#read 4, iclass 14, count 0 2006.201.02:07:18.83#ibcon#about to read 5, iclass 14, count 0 2006.201.02:07:18.83#ibcon#read 5, iclass 14, count 0 2006.201.02:07:18.83#ibcon#about to read 6, iclass 14, count 0 2006.201.02:07:18.83#ibcon#read 6, iclass 14, count 0 2006.201.02:07:18.83#ibcon#end of sib2, iclass 14, count 0 2006.201.02:07:18.83#ibcon#*mode == 0, iclass 14, count 0 2006.201.02:07:18.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.02:07:18.83#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:07:18.83#ibcon#*before write, iclass 14, count 0 2006.201.02:07:18.83#ibcon#enter sib2, iclass 14, count 0 2006.201.02:07:18.83#ibcon#flushed, iclass 14, count 0 2006.201.02:07:18.83#ibcon#about to write, iclass 14, count 0 2006.201.02:07:18.83#ibcon#wrote, iclass 14, count 0 2006.201.02:07:18.83#ibcon#about to read 3, iclass 14, count 0 2006.201.02:07:18.88#ibcon#read 3, iclass 14, count 0 2006.201.02:07:18.88#ibcon#about to read 4, iclass 14, count 0 2006.201.02:07:18.88#ibcon#read 4, iclass 14, count 0 2006.201.02:07:18.88#ibcon#about to read 5, iclass 14, count 0 2006.201.02:07:18.88#ibcon#read 5, iclass 14, count 0 2006.201.02:07:18.88#ibcon#about to read 6, iclass 14, count 0 2006.201.02:07:18.88#ibcon#read 6, iclass 14, count 0 2006.201.02:07:18.88#ibcon#end of sib2, iclass 14, count 0 2006.201.02:07:18.88#ibcon#*after write, iclass 14, count 0 2006.201.02:07:18.88#ibcon#*before return 0, iclass 14, count 0 2006.201.02:07:18.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:18.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:18.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.02:07:18.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.02:07:18.88$vck44/vb=1,4 2006.201.02:07:18.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.02:07:18.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.02:07:18.88#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:18.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:07:18.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:07:18.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:07:18.88#ibcon#enter wrdev, iclass 16, count 2 2006.201.02:07:18.88#ibcon#first serial, iclass 16, count 2 2006.201.02:07:18.88#ibcon#enter sib2, iclass 16, count 2 2006.201.02:07:18.88#ibcon#flushed, iclass 16, count 2 2006.201.02:07:18.88#ibcon#about to write, iclass 16, count 2 2006.201.02:07:18.88#ibcon#wrote, iclass 16, count 2 2006.201.02:07:18.88#ibcon#about to read 3, iclass 16, count 2 2006.201.02:07:18.90#ibcon#read 3, iclass 16, count 2 2006.201.02:07:18.90#ibcon#about to read 4, iclass 16, count 2 2006.201.02:07:18.90#ibcon#read 4, iclass 16, count 2 2006.201.02:07:18.90#ibcon#about to read 5, iclass 16, count 2 2006.201.02:07:18.90#ibcon#read 5, iclass 16, count 2 2006.201.02:07:18.90#ibcon#about to read 6, iclass 16, count 2 2006.201.02:07:18.90#ibcon#read 6, iclass 16, count 2 2006.201.02:07:18.90#ibcon#end of sib2, iclass 16, count 2 2006.201.02:07:18.90#ibcon#*mode == 0, iclass 16, count 2 2006.201.02:07:18.90#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.02:07:18.90#ibcon#[27=AT01-04\r\n] 2006.201.02:07:18.90#ibcon#*before write, iclass 16, count 2 2006.201.02:07:18.90#ibcon#enter sib2, iclass 16, count 2 2006.201.02:07:18.90#ibcon#flushed, iclass 16, count 2 2006.201.02:07:18.90#ibcon#about to write, iclass 16, count 2 2006.201.02:07:18.90#ibcon#wrote, iclass 16, count 2 2006.201.02:07:18.90#ibcon#about to read 3, iclass 16, count 2 2006.201.02:07:18.93#ibcon#read 3, iclass 16, count 2 2006.201.02:07:18.93#ibcon#about to read 4, iclass 16, count 2 2006.201.02:07:18.93#ibcon#read 4, iclass 16, count 2 2006.201.02:07:18.93#ibcon#about to read 5, iclass 16, count 2 2006.201.02:07:18.93#ibcon#read 5, iclass 16, count 2 2006.201.02:07:18.93#ibcon#about to read 6, iclass 16, count 2 2006.201.02:07:18.93#ibcon#read 6, iclass 16, count 2 2006.201.02:07:18.93#ibcon#end of sib2, iclass 16, count 2 2006.201.02:07:18.93#ibcon#*after write, iclass 16, count 2 2006.201.02:07:18.93#ibcon#*before return 0, iclass 16, count 2 2006.201.02:07:18.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:07:18.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:07:18.93#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.02:07:18.93#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:18.93#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:07:19.05#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:07:19.05#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:07:19.05#ibcon#enter wrdev, iclass 16, count 0 2006.201.02:07:19.05#ibcon#first serial, iclass 16, count 0 2006.201.02:07:19.05#ibcon#enter sib2, iclass 16, count 0 2006.201.02:07:19.05#ibcon#flushed, iclass 16, count 0 2006.201.02:07:19.05#ibcon#about to write, iclass 16, count 0 2006.201.02:07:19.05#ibcon#wrote, iclass 16, count 0 2006.201.02:07:19.05#ibcon#about to read 3, iclass 16, count 0 2006.201.02:07:19.07#ibcon#read 3, iclass 16, count 0 2006.201.02:07:19.07#ibcon#about to read 4, iclass 16, count 0 2006.201.02:07:19.07#ibcon#read 4, iclass 16, count 0 2006.201.02:07:19.07#ibcon#about to read 5, iclass 16, count 0 2006.201.02:07:19.07#ibcon#read 5, iclass 16, count 0 2006.201.02:07:19.07#ibcon#about to read 6, iclass 16, count 0 2006.201.02:07:19.07#ibcon#read 6, iclass 16, count 0 2006.201.02:07:19.07#ibcon#end of sib2, iclass 16, count 0 2006.201.02:07:19.07#ibcon#*mode == 0, iclass 16, count 0 2006.201.02:07:19.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.02:07:19.07#ibcon#[27=USB\r\n] 2006.201.02:07:19.07#ibcon#*before write, iclass 16, count 0 2006.201.02:07:19.07#ibcon#enter sib2, iclass 16, count 0 2006.201.02:07:19.07#ibcon#flushed, iclass 16, count 0 2006.201.02:07:19.07#ibcon#about to write, iclass 16, count 0 2006.201.02:07:19.07#ibcon#wrote, iclass 16, count 0 2006.201.02:07:19.07#ibcon#about to read 3, iclass 16, count 0 2006.201.02:07:19.10#ibcon#read 3, iclass 16, count 0 2006.201.02:07:19.10#ibcon#about to read 4, iclass 16, count 0 2006.201.02:07:19.10#ibcon#read 4, iclass 16, count 0 2006.201.02:07:19.10#ibcon#about to read 5, iclass 16, count 0 2006.201.02:07:19.10#ibcon#read 5, iclass 16, count 0 2006.201.02:07:19.10#ibcon#about to read 6, iclass 16, count 0 2006.201.02:07:19.10#ibcon#read 6, iclass 16, count 0 2006.201.02:07:19.10#ibcon#end of sib2, iclass 16, count 0 2006.201.02:07:19.10#ibcon#*after write, iclass 16, count 0 2006.201.02:07:19.10#ibcon#*before return 0, iclass 16, count 0 2006.201.02:07:19.10#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:07:19.10#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:07:19.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.02:07:19.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.02:07:19.10$vck44/vblo=2,634.99 2006.201.02:07:19.10#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.02:07:19.10#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.02:07:19.10#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:19.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:19.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:19.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:19.10#ibcon#enter wrdev, iclass 18, count 0 2006.201.02:07:19.10#ibcon#first serial, iclass 18, count 0 2006.201.02:07:19.10#ibcon#enter sib2, iclass 18, count 0 2006.201.02:07:19.10#ibcon#flushed, iclass 18, count 0 2006.201.02:07:19.10#ibcon#about to write, iclass 18, count 0 2006.201.02:07:19.10#ibcon#wrote, iclass 18, count 0 2006.201.02:07:19.10#ibcon#about to read 3, iclass 18, count 0 2006.201.02:07:19.12#ibcon#read 3, iclass 18, count 0 2006.201.02:07:19.12#ibcon#about to read 4, iclass 18, count 0 2006.201.02:07:19.12#ibcon#read 4, iclass 18, count 0 2006.201.02:07:19.12#ibcon#about to read 5, iclass 18, count 0 2006.201.02:07:19.12#ibcon#read 5, iclass 18, count 0 2006.201.02:07:19.12#ibcon#about to read 6, iclass 18, count 0 2006.201.02:07:19.12#ibcon#read 6, iclass 18, count 0 2006.201.02:07:19.12#ibcon#end of sib2, iclass 18, count 0 2006.201.02:07:19.12#ibcon#*mode == 0, iclass 18, count 0 2006.201.02:07:19.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.02:07:19.12#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:07:19.12#ibcon#*before write, iclass 18, count 0 2006.201.02:07:19.12#ibcon#enter sib2, iclass 18, count 0 2006.201.02:07:19.12#ibcon#flushed, iclass 18, count 0 2006.201.02:07:19.12#ibcon#about to write, iclass 18, count 0 2006.201.02:07:19.12#ibcon#wrote, iclass 18, count 0 2006.201.02:07:19.12#ibcon#about to read 3, iclass 18, count 0 2006.201.02:07:19.16#ibcon#read 3, iclass 18, count 0 2006.201.02:07:19.16#ibcon#about to read 4, iclass 18, count 0 2006.201.02:07:19.16#ibcon#read 4, iclass 18, count 0 2006.201.02:07:19.16#ibcon#about to read 5, iclass 18, count 0 2006.201.02:07:19.16#ibcon#read 5, iclass 18, count 0 2006.201.02:07:19.16#ibcon#about to read 6, iclass 18, count 0 2006.201.02:07:19.16#ibcon#read 6, iclass 18, count 0 2006.201.02:07:19.16#ibcon#end of sib2, iclass 18, count 0 2006.201.02:07:19.16#ibcon#*after write, iclass 18, count 0 2006.201.02:07:19.16#ibcon#*before return 0, iclass 18, count 0 2006.201.02:07:19.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:19.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:07:19.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.02:07:19.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.02:07:19.16$vck44/vb=2,5 2006.201.02:07:19.16#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.02:07:19.16#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.02:07:19.16#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:19.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:19.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:19.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:19.22#ibcon#enter wrdev, iclass 20, count 2 2006.201.02:07:19.22#ibcon#first serial, iclass 20, count 2 2006.201.02:07:19.22#ibcon#enter sib2, iclass 20, count 2 2006.201.02:07:19.22#ibcon#flushed, iclass 20, count 2 2006.201.02:07:19.22#ibcon#about to write, iclass 20, count 2 2006.201.02:07:19.22#ibcon#wrote, iclass 20, count 2 2006.201.02:07:19.22#ibcon#about to read 3, iclass 20, count 2 2006.201.02:07:19.24#ibcon#read 3, iclass 20, count 2 2006.201.02:07:19.24#ibcon#about to read 4, iclass 20, count 2 2006.201.02:07:19.24#ibcon#read 4, iclass 20, count 2 2006.201.02:07:19.24#ibcon#about to read 5, iclass 20, count 2 2006.201.02:07:19.24#ibcon#read 5, iclass 20, count 2 2006.201.02:07:19.24#ibcon#about to read 6, iclass 20, count 2 2006.201.02:07:19.24#ibcon#read 6, iclass 20, count 2 2006.201.02:07:19.24#ibcon#end of sib2, iclass 20, count 2 2006.201.02:07:19.24#ibcon#*mode == 0, iclass 20, count 2 2006.201.02:07:19.24#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.02:07:19.24#ibcon#[27=AT02-05\r\n] 2006.201.02:07:19.24#ibcon#*before write, iclass 20, count 2 2006.201.02:07:19.24#ibcon#enter sib2, iclass 20, count 2 2006.201.02:07:19.24#ibcon#flushed, iclass 20, count 2 2006.201.02:07:19.24#ibcon#about to write, iclass 20, count 2 2006.201.02:07:19.24#ibcon#wrote, iclass 20, count 2 2006.201.02:07:19.24#ibcon#about to read 3, iclass 20, count 2 2006.201.02:07:19.27#ibcon#read 3, iclass 20, count 2 2006.201.02:07:19.27#ibcon#about to read 4, iclass 20, count 2 2006.201.02:07:19.27#ibcon#read 4, iclass 20, count 2 2006.201.02:07:19.27#ibcon#about to read 5, iclass 20, count 2 2006.201.02:07:19.27#ibcon#read 5, iclass 20, count 2 2006.201.02:07:19.27#ibcon#about to read 6, iclass 20, count 2 2006.201.02:07:19.27#ibcon#read 6, iclass 20, count 2 2006.201.02:07:19.27#ibcon#end of sib2, iclass 20, count 2 2006.201.02:07:19.27#ibcon#*after write, iclass 20, count 2 2006.201.02:07:19.27#ibcon#*before return 0, iclass 20, count 2 2006.201.02:07:19.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:19.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:07:19.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.02:07:19.27#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:19.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:19.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:19.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:19.39#ibcon#enter wrdev, iclass 20, count 0 2006.201.02:07:19.39#ibcon#first serial, iclass 20, count 0 2006.201.02:07:19.39#ibcon#enter sib2, iclass 20, count 0 2006.201.02:07:19.39#ibcon#flushed, iclass 20, count 0 2006.201.02:07:19.39#ibcon#about to write, iclass 20, count 0 2006.201.02:07:19.39#ibcon#wrote, iclass 20, count 0 2006.201.02:07:19.39#ibcon#about to read 3, iclass 20, count 0 2006.201.02:07:19.41#ibcon#read 3, iclass 20, count 0 2006.201.02:07:19.41#ibcon#about to read 4, iclass 20, count 0 2006.201.02:07:19.41#ibcon#read 4, iclass 20, count 0 2006.201.02:07:19.41#ibcon#about to read 5, iclass 20, count 0 2006.201.02:07:19.41#ibcon#read 5, iclass 20, count 0 2006.201.02:07:19.41#ibcon#about to read 6, iclass 20, count 0 2006.201.02:07:19.41#ibcon#read 6, iclass 20, count 0 2006.201.02:07:19.41#ibcon#end of sib2, iclass 20, count 0 2006.201.02:07:19.41#ibcon#*mode == 0, iclass 20, count 0 2006.201.02:07:19.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.02:07:19.41#ibcon#[27=USB\r\n] 2006.201.02:07:19.41#ibcon#*before write, iclass 20, count 0 2006.201.02:07:19.41#ibcon#enter sib2, iclass 20, count 0 2006.201.02:07:19.41#ibcon#flushed, iclass 20, count 0 2006.201.02:07:19.41#ibcon#about to write, iclass 20, count 0 2006.201.02:07:19.41#ibcon#wrote, iclass 20, count 0 2006.201.02:07:19.41#ibcon#about to read 3, iclass 20, count 0 2006.201.02:07:19.44#ibcon#read 3, iclass 20, count 0 2006.201.02:07:19.44#ibcon#about to read 4, iclass 20, count 0 2006.201.02:07:19.44#ibcon#read 4, iclass 20, count 0 2006.201.02:07:19.44#ibcon#about to read 5, iclass 20, count 0 2006.201.02:07:19.44#ibcon#read 5, iclass 20, count 0 2006.201.02:07:19.44#ibcon#about to read 6, iclass 20, count 0 2006.201.02:07:19.44#ibcon#read 6, iclass 20, count 0 2006.201.02:07:19.44#ibcon#end of sib2, iclass 20, count 0 2006.201.02:07:19.44#ibcon#*after write, iclass 20, count 0 2006.201.02:07:19.44#ibcon#*before return 0, iclass 20, count 0 2006.201.02:07:19.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:19.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:07:19.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.02:07:19.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.02:07:19.44$vck44/vblo=3,649.99 2006.201.02:07:19.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.02:07:19.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.02:07:19.44#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:19.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:19.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:19.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:19.44#ibcon#enter wrdev, iclass 22, count 0 2006.201.02:07:19.44#ibcon#first serial, iclass 22, count 0 2006.201.02:07:19.44#ibcon#enter sib2, iclass 22, count 0 2006.201.02:07:19.44#ibcon#flushed, iclass 22, count 0 2006.201.02:07:19.44#ibcon#about to write, iclass 22, count 0 2006.201.02:07:19.44#ibcon#wrote, iclass 22, count 0 2006.201.02:07:19.44#ibcon#about to read 3, iclass 22, count 0 2006.201.02:07:19.46#ibcon#read 3, iclass 22, count 0 2006.201.02:07:19.46#ibcon#about to read 4, iclass 22, count 0 2006.201.02:07:19.46#ibcon#read 4, iclass 22, count 0 2006.201.02:07:19.46#ibcon#about to read 5, iclass 22, count 0 2006.201.02:07:19.46#ibcon#read 5, iclass 22, count 0 2006.201.02:07:19.46#ibcon#about to read 6, iclass 22, count 0 2006.201.02:07:19.46#ibcon#read 6, iclass 22, count 0 2006.201.02:07:19.46#ibcon#end of sib2, iclass 22, count 0 2006.201.02:07:19.46#ibcon#*mode == 0, iclass 22, count 0 2006.201.02:07:19.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.02:07:19.46#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:07:19.46#ibcon#*before write, iclass 22, count 0 2006.201.02:07:19.46#ibcon#enter sib2, iclass 22, count 0 2006.201.02:07:19.46#ibcon#flushed, iclass 22, count 0 2006.201.02:07:19.46#ibcon#about to write, iclass 22, count 0 2006.201.02:07:19.46#ibcon#wrote, iclass 22, count 0 2006.201.02:07:19.46#ibcon#about to read 3, iclass 22, count 0 2006.201.02:07:19.50#ibcon#read 3, iclass 22, count 0 2006.201.02:07:19.50#ibcon#about to read 4, iclass 22, count 0 2006.201.02:07:19.50#ibcon#read 4, iclass 22, count 0 2006.201.02:07:19.50#ibcon#about to read 5, iclass 22, count 0 2006.201.02:07:19.50#ibcon#read 5, iclass 22, count 0 2006.201.02:07:19.50#ibcon#about to read 6, iclass 22, count 0 2006.201.02:07:19.50#ibcon#read 6, iclass 22, count 0 2006.201.02:07:19.50#ibcon#end of sib2, iclass 22, count 0 2006.201.02:07:19.50#ibcon#*after write, iclass 22, count 0 2006.201.02:07:19.50#ibcon#*before return 0, iclass 22, count 0 2006.201.02:07:19.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:19.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:07:19.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.02:07:19.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.02:07:19.50$vck44/vb=3,4 2006.201.02:07:19.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.02:07:19.50#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.02:07:19.50#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:19.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:19.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:19.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:19.56#ibcon#enter wrdev, iclass 24, count 2 2006.201.02:07:19.56#ibcon#first serial, iclass 24, count 2 2006.201.02:07:19.56#ibcon#enter sib2, iclass 24, count 2 2006.201.02:07:19.56#ibcon#flushed, iclass 24, count 2 2006.201.02:07:19.56#ibcon#about to write, iclass 24, count 2 2006.201.02:07:19.56#ibcon#wrote, iclass 24, count 2 2006.201.02:07:19.56#ibcon#about to read 3, iclass 24, count 2 2006.201.02:07:19.58#ibcon#read 3, iclass 24, count 2 2006.201.02:07:19.58#ibcon#about to read 4, iclass 24, count 2 2006.201.02:07:19.58#ibcon#read 4, iclass 24, count 2 2006.201.02:07:19.58#ibcon#about to read 5, iclass 24, count 2 2006.201.02:07:19.58#ibcon#read 5, iclass 24, count 2 2006.201.02:07:19.58#ibcon#about to read 6, iclass 24, count 2 2006.201.02:07:19.58#ibcon#read 6, iclass 24, count 2 2006.201.02:07:19.58#ibcon#end of sib2, iclass 24, count 2 2006.201.02:07:19.58#ibcon#*mode == 0, iclass 24, count 2 2006.201.02:07:19.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.02:07:19.58#ibcon#[27=AT03-04\r\n] 2006.201.02:07:19.58#ibcon#*before write, iclass 24, count 2 2006.201.02:07:19.58#ibcon#enter sib2, iclass 24, count 2 2006.201.02:07:19.58#ibcon#flushed, iclass 24, count 2 2006.201.02:07:19.58#ibcon#about to write, iclass 24, count 2 2006.201.02:07:19.58#ibcon#wrote, iclass 24, count 2 2006.201.02:07:19.58#ibcon#about to read 3, iclass 24, count 2 2006.201.02:07:19.61#ibcon#read 3, iclass 24, count 2 2006.201.02:07:19.61#ibcon#about to read 4, iclass 24, count 2 2006.201.02:07:19.61#ibcon#read 4, iclass 24, count 2 2006.201.02:07:19.61#ibcon#about to read 5, iclass 24, count 2 2006.201.02:07:19.61#ibcon#read 5, iclass 24, count 2 2006.201.02:07:19.61#ibcon#about to read 6, iclass 24, count 2 2006.201.02:07:19.61#ibcon#read 6, iclass 24, count 2 2006.201.02:07:19.61#ibcon#end of sib2, iclass 24, count 2 2006.201.02:07:19.61#ibcon#*after write, iclass 24, count 2 2006.201.02:07:19.61#ibcon#*before return 0, iclass 24, count 2 2006.201.02:07:19.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:19.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:07:19.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.02:07:19.61#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:19.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:19.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:19.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:19.73#ibcon#enter wrdev, iclass 24, count 0 2006.201.02:07:19.73#ibcon#first serial, iclass 24, count 0 2006.201.02:07:19.73#ibcon#enter sib2, iclass 24, count 0 2006.201.02:07:19.73#ibcon#flushed, iclass 24, count 0 2006.201.02:07:19.73#ibcon#about to write, iclass 24, count 0 2006.201.02:07:19.73#ibcon#wrote, iclass 24, count 0 2006.201.02:07:19.73#ibcon#about to read 3, iclass 24, count 0 2006.201.02:07:19.75#ibcon#read 3, iclass 24, count 0 2006.201.02:07:19.75#ibcon#about to read 4, iclass 24, count 0 2006.201.02:07:19.75#ibcon#read 4, iclass 24, count 0 2006.201.02:07:19.75#ibcon#about to read 5, iclass 24, count 0 2006.201.02:07:19.75#ibcon#read 5, iclass 24, count 0 2006.201.02:07:19.75#ibcon#about to read 6, iclass 24, count 0 2006.201.02:07:19.75#ibcon#read 6, iclass 24, count 0 2006.201.02:07:19.75#ibcon#end of sib2, iclass 24, count 0 2006.201.02:07:19.75#ibcon#*mode == 0, iclass 24, count 0 2006.201.02:07:19.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.02:07:19.75#ibcon#[27=USB\r\n] 2006.201.02:07:19.75#ibcon#*before write, iclass 24, count 0 2006.201.02:07:19.75#ibcon#enter sib2, iclass 24, count 0 2006.201.02:07:19.75#ibcon#flushed, iclass 24, count 0 2006.201.02:07:19.75#ibcon#about to write, iclass 24, count 0 2006.201.02:07:19.75#ibcon#wrote, iclass 24, count 0 2006.201.02:07:19.75#ibcon#about to read 3, iclass 24, count 0 2006.201.02:07:19.78#ibcon#read 3, iclass 24, count 0 2006.201.02:07:19.78#ibcon#about to read 4, iclass 24, count 0 2006.201.02:07:19.78#ibcon#read 4, iclass 24, count 0 2006.201.02:07:19.78#ibcon#about to read 5, iclass 24, count 0 2006.201.02:07:19.78#ibcon#read 5, iclass 24, count 0 2006.201.02:07:19.78#ibcon#about to read 6, iclass 24, count 0 2006.201.02:07:19.78#ibcon#read 6, iclass 24, count 0 2006.201.02:07:19.78#ibcon#end of sib2, iclass 24, count 0 2006.201.02:07:19.78#ibcon#*after write, iclass 24, count 0 2006.201.02:07:19.78#ibcon#*before return 0, iclass 24, count 0 2006.201.02:07:19.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:19.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:07:19.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.02:07:19.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.02:07:19.78$vck44/vblo=4,679.99 2006.201.02:07:19.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.02:07:19.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.02:07:19.78#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:19.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:19.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:19.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:19.78#ibcon#enter wrdev, iclass 26, count 0 2006.201.02:07:19.78#ibcon#first serial, iclass 26, count 0 2006.201.02:07:19.78#ibcon#enter sib2, iclass 26, count 0 2006.201.02:07:19.78#ibcon#flushed, iclass 26, count 0 2006.201.02:07:19.78#ibcon#about to write, iclass 26, count 0 2006.201.02:07:19.78#ibcon#wrote, iclass 26, count 0 2006.201.02:07:19.78#ibcon#about to read 3, iclass 26, count 0 2006.201.02:07:19.80#ibcon#read 3, iclass 26, count 0 2006.201.02:07:19.80#ibcon#about to read 4, iclass 26, count 0 2006.201.02:07:19.80#ibcon#read 4, iclass 26, count 0 2006.201.02:07:19.80#ibcon#about to read 5, iclass 26, count 0 2006.201.02:07:19.80#ibcon#read 5, iclass 26, count 0 2006.201.02:07:19.80#ibcon#about to read 6, iclass 26, count 0 2006.201.02:07:19.80#ibcon#read 6, iclass 26, count 0 2006.201.02:07:19.80#ibcon#end of sib2, iclass 26, count 0 2006.201.02:07:19.80#ibcon#*mode == 0, iclass 26, count 0 2006.201.02:07:19.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.02:07:19.80#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:07:19.80#ibcon#*before write, iclass 26, count 0 2006.201.02:07:19.80#ibcon#enter sib2, iclass 26, count 0 2006.201.02:07:19.80#ibcon#flushed, iclass 26, count 0 2006.201.02:07:19.80#ibcon#about to write, iclass 26, count 0 2006.201.02:07:19.80#ibcon#wrote, iclass 26, count 0 2006.201.02:07:19.80#ibcon#about to read 3, iclass 26, count 0 2006.201.02:07:19.84#ibcon#read 3, iclass 26, count 0 2006.201.02:07:19.84#ibcon#about to read 4, iclass 26, count 0 2006.201.02:07:19.84#ibcon#read 4, iclass 26, count 0 2006.201.02:07:19.84#ibcon#about to read 5, iclass 26, count 0 2006.201.02:07:19.84#ibcon#read 5, iclass 26, count 0 2006.201.02:07:19.84#ibcon#about to read 6, iclass 26, count 0 2006.201.02:07:19.84#ibcon#read 6, iclass 26, count 0 2006.201.02:07:19.84#ibcon#end of sib2, iclass 26, count 0 2006.201.02:07:19.84#ibcon#*after write, iclass 26, count 0 2006.201.02:07:19.84#ibcon#*before return 0, iclass 26, count 0 2006.201.02:07:19.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:19.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:07:19.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.02:07:19.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.02:07:19.84$vck44/vb=4,5 2006.201.02:07:19.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.02:07:19.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.02:07:19.84#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:19.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:19.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:19.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:19.90#ibcon#enter wrdev, iclass 28, count 2 2006.201.02:07:19.90#ibcon#first serial, iclass 28, count 2 2006.201.02:07:19.90#ibcon#enter sib2, iclass 28, count 2 2006.201.02:07:19.90#ibcon#flushed, iclass 28, count 2 2006.201.02:07:19.90#ibcon#about to write, iclass 28, count 2 2006.201.02:07:19.90#ibcon#wrote, iclass 28, count 2 2006.201.02:07:19.90#ibcon#about to read 3, iclass 28, count 2 2006.201.02:07:19.92#ibcon#read 3, iclass 28, count 2 2006.201.02:07:19.92#ibcon#about to read 4, iclass 28, count 2 2006.201.02:07:19.92#ibcon#read 4, iclass 28, count 2 2006.201.02:07:19.92#ibcon#about to read 5, iclass 28, count 2 2006.201.02:07:19.92#ibcon#read 5, iclass 28, count 2 2006.201.02:07:19.92#ibcon#about to read 6, iclass 28, count 2 2006.201.02:07:19.92#ibcon#read 6, iclass 28, count 2 2006.201.02:07:19.92#ibcon#end of sib2, iclass 28, count 2 2006.201.02:07:19.92#ibcon#*mode == 0, iclass 28, count 2 2006.201.02:07:19.92#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.02:07:19.92#ibcon#[27=AT04-05\r\n] 2006.201.02:07:19.92#ibcon#*before write, iclass 28, count 2 2006.201.02:07:19.92#ibcon#enter sib2, iclass 28, count 2 2006.201.02:07:19.92#ibcon#flushed, iclass 28, count 2 2006.201.02:07:19.92#ibcon#about to write, iclass 28, count 2 2006.201.02:07:19.92#ibcon#wrote, iclass 28, count 2 2006.201.02:07:19.92#ibcon#about to read 3, iclass 28, count 2 2006.201.02:07:19.95#ibcon#read 3, iclass 28, count 2 2006.201.02:07:19.95#ibcon#about to read 4, iclass 28, count 2 2006.201.02:07:19.95#ibcon#read 4, iclass 28, count 2 2006.201.02:07:19.95#ibcon#about to read 5, iclass 28, count 2 2006.201.02:07:19.95#ibcon#read 5, iclass 28, count 2 2006.201.02:07:19.95#ibcon#about to read 6, iclass 28, count 2 2006.201.02:07:19.95#ibcon#read 6, iclass 28, count 2 2006.201.02:07:19.95#ibcon#end of sib2, iclass 28, count 2 2006.201.02:07:19.95#ibcon#*after write, iclass 28, count 2 2006.201.02:07:19.95#ibcon#*before return 0, iclass 28, count 2 2006.201.02:07:19.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:19.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:07:19.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.02:07:19.95#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:19.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:20.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:20.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:20.07#ibcon#enter wrdev, iclass 28, count 0 2006.201.02:07:20.07#ibcon#first serial, iclass 28, count 0 2006.201.02:07:20.07#ibcon#enter sib2, iclass 28, count 0 2006.201.02:07:20.07#ibcon#flushed, iclass 28, count 0 2006.201.02:07:20.07#ibcon#about to write, iclass 28, count 0 2006.201.02:07:20.07#ibcon#wrote, iclass 28, count 0 2006.201.02:07:20.07#ibcon#about to read 3, iclass 28, count 0 2006.201.02:07:20.09#ibcon#read 3, iclass 28, count 0 2006.201.02:07:20.09#ibcon#about to read 4, iclass 28, count 0 2006.201.02:07:20.09#ibcon#read 4, iclass 28, count 0 2006.201.02:07:20.09#ibcon#about to read 5, iclass 28, count 0 2006.201.02:07:20.09#ibcon#read 5, iclass 28, count 0 2006.201.02:07:20.09#ibcon#about to read 6, iclass 28, count 0 2006.201.02:07:20.09#ibcon#read 6, iclass 28, count 0 2006.201.02:07:20.09#ibcon#end of sib2, iclass 28, count 0 2006.201.02:07:20.09#ibcon#*mode == 0, iclass 28, count 0 2006.201.02:07:20.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.02:07:20.09#ibcon#[27=USB\r\n] 2006.201.02:07:20.09#ibcon#*before write, iclass 28, count 0 2006.201.02:07:20.09#ibcon#enter sib2, iclass 28, count 0 2006.201.02:07:20.09#ibcon#flushed, iclass 28, count 0 2006.201.02:07:20.09#ibcon#about to write, iclass 28, count 0 2006.201.02:07:20.09#ibcon#wrote, iclass 28, count 0 2006.201.02:07:20.09#ibcon#about to read 3, iclass 28, count 0 2006.201.02:07:20.12#ibcon#read 3, iclass 28, count 0 2006.201.02:07:20.12#ibcon#about to read 4, iclass 28, count 0 2006.201.02:07:20.12#ibcon#read 4, iclass 28, count 0 2006.201.02:07:20.12#ibcon#about to read 5, iclass 28, count 0 2006.201.02:07:20.12#ibcon#read 5, iclass 28, count 0 2006.201.02:07:20.12#ibcon#about to read 6, iclass 28, count 0 2006.201.02:07:20.12#ibcon#read 6, iclass 28, count 0 2006.201.02:07:20.12#ibcon#end of sib2, iclass 28, count 0 2006.201.02:07:20.12#ibcon#*after write, iclass 28, count 0 2006.201.02:07:20.12#ibcon#*before return 0, iclass 28, count 0 2006.201.02:07:20.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:20.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:07:20.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.02:07:20.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.02:07:20.12$vck44/vblo=5,709.99 2006.201.02:07:20.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.02:07:20.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.02:07:20.12#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:20.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:20.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:20.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:20.12#ibcon#enter wrdev, iclass 30, count 0 2006.201.02:07:20.12#ibcon#first serial, iclass 30, count 0 2006.201.02:07:20.12#ibcon#enter sib2, iclass 30, count 0 2006.201.02:07:20.12#ibcon#flushed, iclass 30, count 0 2006.201.02:07:20.12#ibcon#about to write, iclass 30, count 0 2006.201.02:07:20.12#ibcon#wrote, iclass 30, count 0 2006.201.02:07:20.12#ibcon#about to read 3, iclass 30, count 0 2006.201.02:07:20.14#ibcon#read 3, iclass 30, count 0 2006.201.02:07:20.14#ibcon#about to read 4, iclass 30, count 0 2006.201.02:07:20.14#ibcon#read 4, iclass 30, count 0 2006.201.02:07:20.14#ibcon#about to read 5, iclass 30, count 0 2006.201.02:07:20.14#ibcon#read 5, iclass 30, count 0 2006.201.02:07:20.14#ibcon#about to read 6, iclass 30, count 0 2006.201.02:07:20.14#ibcon#read 6, iclass 30, count 0 2006.201.02:07:20.14#ibcon#end of sib2, iclass 30, count 0 2006.201.02:07:20.14#ibcon#*mode == 0, iclass 30, count 0 2006.201.02:07:20.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.02:07:20.14#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:07:20.14#ibcon#*before write, iclass 30, count 0 2006.201.02:07:20.14#ibcon#enter sib2, iclass 30, count 0 2006.201.02:07:20.14#ibcon#flushed, iclass 30, count 0 2006.201.02:07:20.14#ibcon#about to write, iclass 30, count 0 2006.201.02:07:20.14#ibcon#wrote, iclass 30, count 0 2006.201.02:07:20.14#ibcon#about to read 3, iclass 30, count 0 2006.201.02:07:20.18#ibcon#read 3, iclass 30, count 0 2006.201.02:07:20.18#ibcon#about to read 4, iclass 30, count 0 2006.201.02:07:20.18#ibcon#read 4, iclass 30, count 0 2006.201.02:07:20.18#ibcon#about to read 5, iclass 30, count 0 2006.201.02:07:20.18#ibcon#read 5, iclass 30, count 0 2006.201.02:07:20.18#ibcon#about to read 6, iclass 30, count 0 2006.201.02:07:20.18#ibcon#read 6, iclass 30, count 0 2006.201.02:07:20.18#ibcon#end of sib2, iclass 30, count 0 2006.201.02:07:20.18#ibcon#*after write, iclass 30, count 0 2006.201.02:07:20.18#ibcon#*before return 0, iclass 30, count 0 2006.201.02:07:20.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:20.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:07:20.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.02:07:20.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.02:07:20.18$vck44/vb=5,4 2006.201.02:07:20.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.02:07:20.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.02:07:20.18#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:20.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:20.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:20.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:20.24#ibcon#enter wrdev, iclass 32, count 2 2006.201.02:07:20.24#ibcon#first serial, iclass 32, count 2 2006.201.02:07:20.24#ibcon#enter sib2, iclass 32, count 2 2006.201.02:07:20.24#ibcon#flushed, iclass 32, count 2 2006.201.02:07:20.24#ibcon#about to write, iclass 32, count 2 2006.201.02:07:20.24#ibcon#wrote, iclass 32, count 2 2006.201.02:07:20.24#ibcon#about to read 3, iclass 32, count 2 2006.201.02:07:20.26#ibcon#read 3, iclass 32, count 2 2006.201.02:07:20.26#ibcon#about to read 4, iclass 32, count 2 2006.201.02:07:20.26#ibcon#read 4, iclass 32, count 2 2006.201.02:07:20.26#ibcon#about to read 5, iclass 32, count 2 2006.201.02:07:20.26#ibcon#read 5, iclass 32, count 2 2006.201.02:07:20.26#ibcon#about to read 6, iclass 32, count 2 2006.201.02:07:20.26#ibcon#read 6, iclass 32, count 2 2006.201.02:07:20.26#ibcon#end of sib2, iclass 32, count 2 2006.201.02:07:20.26#ibcon#*mode == 0, iclass 32, count 2 2006.201.02:07:20.26#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.02:07:20.26#ibcon#[27=AT05-04\r\n] 2006.201.02:07:20.26#ibcon#*before write, iclass 32, count 2 2006.201.02:07:20.26#ibcon#enter sib2, iclass 32, count 2 2006.201.02:07:20.26#ibcon#flushed, iclass 32, count 2 2006.201.02:07:20.26#ibcon#about to write, iclass 32, count 2 2006.201.02:07:20.26#ibcon#wrote, iclass 32, count 2 2006.201.02:07:20.26#ibcon#about to read 3, iclass 32, count 2 2006.201.02:07:20.29#ibcon#read 3, iclass 32, count 2 2006.201.02:07:20.29#ibcon#about to read 4, iclass 32, count 2 2006.201.02:07:20.29#ibcon#read 4, iclass 32, count 2 2006.201.02:07:20.29#ibcon#about to read 5, iclass 32, count 2 2006.201.02:07:20.29#ibcon#read 5, iclass 32, count 2 2006.201.02:07:20.29#ibcon#about to read 6, iclass 32, count 2 2006.201.02:07:20.29#ibcon#read 6, iclass 32, count 2 2006.201.02:07:20.29#ibcon#end of sib2, iclass 32, count 2 2006.201.02:07:20.29#ibcon#*after write, iclass 32, count 2 2006.201.02:07:20.29#ibcon#*before return 0, iclass 32, count 2 2006.201.02:07:20.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:20.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:07:20.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.02:07:20.29#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:20.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:20.41#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:20.41#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:20.41#ibcon#enter wrdev, iclass 32, count 0 2006.201.02:07:20.41#ibcon#first serial, iclass 32, count 0 2006.201.02:07:20.41#ibcon#enter sib2, iclass 32, count 0 2006.201.02:07:20.41#ibcon#flushed, iclass 32, count 0 2006.201.02:07:20.41#ibcon#about to write, iclass 32, count 0 2006.201.02:07:20.41#ibcon#wrote, iclass 32, count 0 2006.201.02:07:20.41#ibcon#about to read 3, iclass 32, count 0 2006.201.02:07:20.43#ibcon#read 3, iclass 32, count 0 2006.201.02:07:20.43#ibcon#about to read 4, iclass 32, count 0 2006.201.02:07:20.43#ibcon#read 4, iclass 32, count 0 2006.201.02:07:20.43#ibcon#about to read 5, iclass 32, count 0 2006.201.02:07:20.43#ibcon#read 5, iclass 32, count 0 2006.201.02:07:20.43#ibcon#about to read 6, iclass 32, count 0 2006.201.02:07:20.43#ibcon#read 6, iclass 32, count 0 2006.201.02:07:20.43#ibcon#end of sib2, iclass 32, count 0 2006.201.02:07:20.43#ibcon#*mode == 0, iclass 32, count 0 2006.201.02:07:20.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.02:07:20.43#ibcon#[27=USB\r\n] 2006.201.02:07:20.43#ibcon#*before write, iclass 32, count 0 2006.201.02:07:20.43#ibcon#enter sib2, iclass 32, count 0 2006.201.02:07:20.43#ibcon#flushed, iclass 32, count 0 2006.201.02:07:20.43#ibcon#about to write, iclass 32, count 0 2006.201.02:07:20.43#ibcon#wrote, iclass 32, count 0 2006.201.02:07:20.43#ibcon#about to read 3, iclass 32, count 0 2006.201.02:07:20.46#ibcon#read 3, iclass 32, count 0 2006.201.02:07:20.46#ibcon#about to read 4, iclass 32, count 0 2006.201.02:07:20.46#ibcon#read 4, iclass 32, count 0 2006.201.02:07:20.46#ibcon#about to read 5, iclass 32, count 0 2006.201.02:07:20.46#ibcon#read 5, iclass 32, count 0 2006.201.02:07:20.46#ibcon#about to read 6, iclass 32, count 0 2006.201.02:07:20.46#ibcon#read 6, iclass 32, count 0 2006.201.02:07:20.46#ibcon#end of sib2, iclass 32, count 0 2006.201.02:07:20.46#ibcon#*after write, iclass 32, count 0 2006.201.02:07:20.46#ibcon#*before return 0, iclass 32, count 0 2006.201.02:07:20.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:20.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:07:20.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.02:07:20.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.02:07:20.46$vck44/vblo=6,719.99 2006.201.02:07:20.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.02:07:20.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.02:07:20.46#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:20.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:20.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:20.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:20.46#ibcon#enter wrdev, iclass 34, count 0 2006.201.02:07:20.46#ibcon#first serial, iclass 34, count 0 2006.201.02:07:20.46#ibcon#enter sib2, iclass 34, count 0 2006.201.02:07:20.46#ibcon#flushed, iclass 34, count 0 2006.201.02:07:20.46#ibcon#about to write, iclass 34, count 0 2006.201.02:07:20.46#ibcon#wrote, iclass 34, count 0 2006.201.02:07:20.46#ibcon#about to read 3, iclass 34, count 0 2006.201.02:07:20.48#ibcon#read 3, iclass 34, count 0 2006.201.02:07:20.48#ibcon#about to read 4, iclass 34, count 0 2006.201.02:07:20.48#ibcon#read 4, iclass 34, count 0 2006.201.02:07:20.48#ibcon#about to read 5, iclass 34, count 0 2006.201.02:07:20.48#ibcon#read 5, iclass 34, count 0 2006.201.02:07:20.48#ibcon#about to read 6, iclass 34, count 0 2006.201.02:07:20.48#ibcon#read 6, iclass 34, count 0 2006.201.02:07:20.48#ibcon#end of sib2, iclass 34, count 0 2006.201.02:07:20.48#ibcon#*mode == 0, iclass 34, count 0 2006.201.02:07:20.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.02:07:20.48#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:07:20.48#ibcon#*before write, iclass 34, count 0 2006.201.02:07:20.48#ibcon#enter sib2, iclass 34, count 0 2006.201.02:07:20.48#ibcon#flushed, iclass 34, count 0 2006.201.02:07:20.48#ibcon#about to write, iclass 34, count 0 2006.201.02:07:20.48#ibcon#wrote, iclass 34, count 0 2006.201.02:07:20.48#ibcon#about to read 3, iclass 34, count 0 2006.201.02:07:20.53#ibcon#read 3, iclass 34, count 0 2006.201.02:07:20.53#ibcon#about to read 4, iclass 34, count 0 2006.201.02:07:20.53#ibcon#read 4, iclass 34, count 0 2006.201.02:07:20.53#ibcon#about to read 5, iclass 34, count 0 2006.201.02:07:20.53#ibcon#read 5, iclass 34, count 0 2006.201.02:07:20.53#ibcon#about to read 6, iclass 34, count 0 2006.201.02:07:20.53#ibcon#read 6, iclass 34, count 0 2006.201.02:07:20.53#ibcon#end of sib2, iclass 34, count 0 2006.201.02:07:20.53#ibcon#*after write, iclass 34, count 0 2006.201.02:07:20.53#ibcon#*before return 0, iclass 34, count 0 2006.201.02:07:20.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:20.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:07:20.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.02:07:20.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.02:07:20.53$vck44/vb=6,4 2006.201.02:07:20.53#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.02:07:20.53#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.02:07:20.53#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:20.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:20.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:20.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:20.58#ibcon#enter wrdev, iclass 36, count 2 2006.201.02:07:20.58#ibcon#first serial, iclass 36, count 2 2006.201.02:07:20.58#ibcon#enter sib2, iclass 36, count 2 2006.201.02:07:20.58#ibcon#flushed, iclass 36, count 2 2006.201.02:07:20.58#ibcon#about to write, iclass 36, count 2 2006.201.02:07:20.58#ibcon#wrote, iclass 36, count 2 2006.201.02:07:20.58#ibcon#about to read 3, iclass 36, count 2 2006.201.02:07:20.60#ibcon#read 3, iclass 36, count 2 2006.201.02:07:20.60#ibcon#about to read 4, iclass 36, count 2 2006.201.02:07:20.60#ibcon#read 4, iclass 36, count 2 2006.201.02:07:20.60#ibcon#about to read 5, iclass 36, count 2 2006.201.02:07:20.60#ibcon#read 5, iclass 36, count 2 2006.201.02:07:20.60#ibcon#about to read 6, iclass 36, count 2 2006.201.02:07:20.60#ibcon#read 6, iclass 36, count 2 2006.201.02:07:20.60#ibcon#end of sib2, iclass 36, count 2 2006.201.02:07:20.60#ibcon#*mode == 0, iclass 36, count 2 2006.201.02:07:20.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.02:07:20.60#ibcon#[27=AT06-04\r\n] 2006.201.02:07:20.60#ibcon#*before write, iclass 36, count 2 2006.201.02:07:20.60#ibcon#enter sib2, iclass 36, count 2 2006.201.02:07:20.60#ibcon#flushed, iclass 36, count 2 2006.201.02:07:20.60#ibcon#about to write, iclass 36, count 2 2006.201.02:07:20.60#ibcon#wrote, iclass 36, count 2 2006.201.02:07:20.60#ibcon#about to read 3, iclass 36, count 2 2006.201.02:07:20.63#ibcon#read 3, iclass 36, count 2 2006.201.02:07:20.63#ibcon#about to read 4, iclass 36, count 2 2006.201.02:07:20.63#ibcon#read 4, iclass 36, count 2 2006.201.02:07:20.63#ibcon#about to read 5, iclass 36, count 2 2006.201.02:07:20.63#ibcon#read 5, iclass 36, count 2 2006.201.02:07:20.63#ibcon#about to read 6, iclass 36, count 2 2006.201.02:07:20.63#ibcon#read 6, iclass 36, count 2 2006.201.02:07:20.63#ibcon#end of sib2, iclass 36, count 2 2006.201.02:07:20.63#ibcon#*after write, iclass 36, count 2 2006.201.02:07:20.63#ibcon#*before return 0, iclass 36, count 2 2006.201.02:07:20.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:20.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:07:20.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.02:07:20.63#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:20.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:20.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:20.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:20.75#ibcon#enter wrdev, iclass 36, count 0 2006.201.02:07:20.75#ibcon#first serial, iclass 36, count 0 2006.201.02:07:20.75#ibcon#enter sib2, iclass 36, count 0 2006.201.02:07:20.75#ibcon#flushed, iclass 36, count 0 2006.201.02:07:20.75#ibcon#about to write, iclass 36, count 0 2006.201.02:07:20.75#ibcon#wrote, iclass 36, count 0 2006.201.02:07:20.75#ibcon#about to read 3, iclass 36, count 0 2006.201.02:07:20.77#ibcon#read 3, iclass 36, count 0 2006.201.02:07:20.77#ibcon#about to read 4, iclass 36, count 0 2006.201.02:07:20.77#ibcon#read 4, iclass 36, count 0 2006.201.02:07:20.77#ibcon#about to read 5, iclass 36, count 0 2006.201.02:07:20.77#ibcon#read 5, iclass 36, count 0 2006.201.02:07:20.77#ibcon#about to read 6, iclass 36, count 0 2006.201.02:07:20.77#ibcon#read 6, iclass 36, count 0 2006.201.02:07:20.77#ibcon#end of sib2, iclass 36, count 0 2006.201.02:07:20.77#ibcon#*mode == 0, iclass 36, count 0 2006.201.02:07:20.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.02:07:20.77#ibcon#[27=USB\r\n] 2006.201.02:07:20.77#ibcon#*before write, iclass 36, count 0 2006.201.02:07:20.77#ibcon#enter sib2, iclass 36, count 0 2006.201.02:07:20.77#ibcon#flushed, iclass 36, count 0 2006.201.02:07:20.77#ibcon#about to write, iclass 36, count 0 2006.201.02:07:20.77#ibcon#wrote, iclass 36, count 0 2006.201.02:07:20.77#ibcon#about to read 3, iclass 36, count 0 2006.201.02:07:20.80#ibcon#read 3, iclass 36, count 0 2006.201.02:07:20.80#ibcon#about to read 4, iclass 36, count 0 2006.201.02:07:20.80#ibcon#read 4, iclass 36, count 0 2006.201.02:07:20.80#ibcon#about to read 5, iclass 36, count 0 2006.201.02:07:20.80#ibcon#read 5, iclass 36, count 0 2006.201.02:07:20.80#ibcon#about to read 6, iclass 36, count 0 2006.201.02:07:20.80#ibcon#read 6, iclass 36, count 0 2006.201.02:07:20.80#ibcon#end of sib2, iclass 36, count 0 2006.201.02:07:20.80#ibcon#*after write, iclass 36, count 0 2006.201.02:07:20.80#ibcon#*before return 0, iclass 36, count 0 2006.201.02:07:20.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:20.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:07:20.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.02:07:20.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.02:07:20.80$vck44/vblo=7,734.99 2006.201.02:07:20.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.02:07:20.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.02:07:20.80#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:20.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:20.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:20.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:20.80#ibcon#enter wrdev, iclass 38, count 0 2006.201.02:07:20.80#ibcon#first serial, iclass 38, count 0 2006.201.02:07:20.80#ibcon#enter sib2, iclass 38, count 0 2006.201.02:07:20.80#ibcon#flushed, iclass 38, count 0 2006.201.02:07:20.80#ibcon#about to write, iclass 38, count 0 2006.201.02:07:20.80#ibcon#wrote, iclass 38, count 0 2006.201.02:07:20.80#ibcon#about to read 3, iclass 38, count 0 2006.201.02:07:20.82#ibcon#read 3, iclass 38, count 0 2006.201.02:07:20.82#ibcon#about to read 4, iclass 38, count 0 2006.201.02:07:20.82#ibcon#read 4, iclass 38, count 0 2006.201.02:07:20.82#ibcon#about to read 5, iclass 38, count 0 2006.201.02:07:20.82#ibcon#read 5, iclass 38, count 0 2006.201.02:07:20.82#ibcon#about to read 6, iclass 38, count 0 2006.201.02:07:20.82#ibcon#read 6, iclass 38, count 0 2006.201.02:07:20.82#ibcon#end of sib2, iclass 38, count 0 2006.201.02:07:20.82#ibcon#*mode == 0, iclass 38, count 0 2006.201.02:07:20.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.02:07:20.82#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:07:20.82#ibcon#*before write, iclass 38, count 0 2006.201.02:07:20.82#ibcon#enter sib2, iclass 38, count 0 2006.201.02:07:20.82#ibcon#flushed, iclass 38, count 0 2006.201.02:07:20.82#ibcon#about to write, iclass 38, count 0 2006.201.02:07:20.82#ibcon#wrote, iclass 38, count 0 2006.201.02:07:20.82#ibcon#about to read 3, iclass 38, count 0 2006.201.02:07:20.86#ibcon#read 3, iclass 38, count 0 2006.201.02:07:20.86#ibcon#about to read 4, iclass 38, count 0 2006.201.02:07:20.86#ibcon#read 4, iclass 38, count 0 2006.201.02:07:20.86#ibcon#about to read 5, iclass 38, count 0 2006.201.02:07:20.86#ibcon#read 5, iclass 38, count 0 2006.201.02:07:20.86#ibcon#about to read 6, iclass 38, count 0 2006.201.02:07:20.86#ibcon#read 6, iclass 38, count 0 2006.201.02:07:20.86#ibcon#end of sib2, iclass 38, count 0 2006.201.02:07:20.86#ibcon#*after write, iclass 38, count 0 2006.201.02:07:20.86#ibcon#*before return 0, iclass 38, count 0 2006.201.02:07:20.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:20.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:07:20.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.02:07:20.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.02:07:20.86$vck44/vb=7,4 2006.201.02:07:20.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.02:07:20.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.02:07:20.86#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:20.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:20.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:20.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:20.92#ibcon#enter wrdev, iclass 40, count 2 2006.201.02:07:20.92#ibcon#first serial, iclass 40, count 2 2006.201.02:07:20.92#ibcon#enter sib2, iclass 40, count 2 2006.201.02:07:20.92#ibcon#flushed, iclass 40, count 2 2006.201.02:07:20.92#ibcon#about to write, iclass 40, count 2 2006.201.02:07:20.92#ibcon#wrote, iclass 40, count 2 2006.201.02:07:20.92#ibcon#about to read 3, iclass 40, count 2 2006.201.02:07:20.94#ibcon#read 3, iclass 40, count 2 2006.201.02:07:20.94#ibcon#about to read 4, iclass 40, count 2 2006.201.02:07:20.94#ibcon#read 4, iclass 40, count 2 2006.201.02:07:20.94#ibcon#about to read 5, iclass 40, count 2 2006.201.02:07:20.94#ibcon#read 5, iclass 40, count 2 2006.201.02:07:20.94#ibcon#about to read 6, iclass 40, count 2 2006.201.02:07:20.94#ibcon#read 6, iclass 40, count 2 2006.201.02:07:20.94#ibcon#end of sib2, iclass 40, count 2 2006.201.02:07:20.94#ibcon#*mode == 0, iclass 40, count 2 2006.201.02:07:20.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.02:07:20.94#ibcon#[27=AT07-04\r\n] 2006.201.02:07:20.94#ibcon#*before write, iclass 40, count 2 2006.201.02:07:20.94#ibcon#enter sib2, iclass 40, count 2 2006.201.02:07:20.94#ibcon#flushed, iclass 40, count 2 2006.201.02:07:20.94#ibcon#about to write, iclass 40, count 2 2006.201.02:07:20.94#ibcon#wrote, iclass 40, count 2 2006.201.02:07:20.94#ibcon#about to read 3, iclass 40, count 2 2006.201.02:07:20.97#ibcon#read 3, iclass 40, count 2 2006.201.02:07:20.97#ibcon#about to read 4, iclass 40, count 2 2006.201.02:07:20.97#ibcon#read 4, iclass 40, count 2 2006.201.02:07:20.97#ibcon#about to read 5, iclass 40, count 2 2006.201.02:07:20.97#ibcon#read 5, iclass 40, count 2 2006.201.02:07:20.97#ibcon#about to read 6, iclass 40, count 2 2006.201.02:07:20.97#ibcon#read 6, iclass 40, count 2 2006.201.02:07:20.97#ibcon#end of sib2, iclass 40, count 2 2006.201.02:07:20.97#ibcon#*after write, iclass 40, count 2 2006.201.02:07:20.97#ibcon#*before return 0, iclass 40, count 2 2006.201.02:07:20.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:20.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:07:20.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.02:07:20.97#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:20.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:21.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:21.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:21.09#ibcon#enter wrdev, iclass 40, count 0 2006.201.02:07:21.09#ibcon#first serial, iclass 40, count 0 2006.201.02:07:21.09#ibcon#enter sib2, iclass 40, count 0 2006.201.02:07:21.09#ibcon#flushed, iclass 40, count 0 2006.201.02:07:21.09#ibcon#about to write, iclass 40, count 0 2006.201.02:07:21.09#ibcon#wrote, iclass 40, count 0 2006.201.02:07:21.09#ibcon#about to read 3, iclass 40, count 0 2006.201.02:07:21.11#ibcon#read 3, iclass 40, count 0 2006.201.02:07:21.11#ibcon#about to read 4, iclass 40, count 0 2006.201.02:07:21.11#ibcon#read 4, iclass 40, count 0 2006.201.02:07:21.11#ibcon#about to read 5, iclass 40, count 0 2006.201.02:07:21.11#ibcon#read 5, iclass 40, count 0 2006.201.02:07:21.11#ibcon#about to read 6, iclass 40, count 0 2006.201.02:07:21.11#ibcon#read 6, iclass 40, count 0 2006.201.02:07:21.11#ibcon#end of sib2, iclass 40, count 0 2006.201.02:07:21.11#ibcon#*mode == 0, iclass 40, count 0 2006.201.02:07:21.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.02:07:21.11#ibcon#[27=USB\r\n] 2006.201.02:07:21.11#ibcon#*before write, iclass 40, count 0 2006.201.02:07:21.11#ibcon#enter sib2, iclass 40, count 0 2006.201.02:07:21.11#ibcon#flushed, iclass 40, count 0 2006.201.02:07:21.11#ibcon#about to write, iclass 40, count 0 2006.201.02:07:21.11#ibcon#wrote, iclass 40, count 0 2006.201.02:07:21.11#ibcon#about to read 3, iclass 40, count 0 2006.201.02:07:21.14#ibcon#read 3, iclass 40, count 0 2006.201.02:07:21.14#ibcon#about to read 4, iclass 40, count 0 2006.201.02:07:21.14#ibcon#read 4, iclass 40, count 0 2006.201.02:07:21.14#ibcon#about to read 5, iclass 40, count 0 2006.201.02:07:21.14#ibcon#read 5, iclass 40, count 0 2006.201.02:07:21.14#ibcon#about to read 6, iclass 40, count 0 2006.201.02:07:21.14#ibcon#read 6, iclass 40, count 0 2006.201.02:07:21.14#ibcon#end of sib2, iclass 40, count 0 2006.201.02:07:21.14#ibcon#*after write, iclass 40, count 0 2006.201.02:07:21.14#ibcon#*before return 0, iclass 40, count 0 2006.201.02:07:21.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:21.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:07:21.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.02:07:21.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.02:07:21.14$vck44/vblo=8,744.99 2006.201.02:07:21.14#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.02:07:21.14#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.02:07:21.14#ibcon#ireg 17 cls_cnt 0 2006.201.02:07:21.14#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:07:21.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:07:21.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:07:21.14#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:07:21.14#ibcon#first serial, iclass 5, count 0 2006.201.02:07:21.14#ibcon#enter sib2, iclass 5, count 0 2006.201.02:07:21.14#ibcon#flushed, iclass 5, count 0 2006.201.02:07:21.14#ibcon#about to write, iclass 5, count 0 2006.201.02:07:21.14#ibcon#wrote, iclass 5, count 0 2006.201.02:07:21.14#ibcon#about to read 3, iclass 5, count 0 2006.201.02:07:21.16#ibcon#read 3, iclass 5, count 0 2006.201.02:07:21.16#ibcon#about to read 4, iclass 5, count 0 2006.201.02:07:21.16#ibcon#read 4, iclass 5, count 0 2006.201.02:07:21.16#ibcon#about to read 5, iclass 5, count 0 2006.201.02:07:21.16#ibcon#read 5, iclass 5, count 0 2006.201.02:07:21.16#ibcon#about to read 6, iclass 5, count 0 2006.201.02:07:21.16#ibcon#read 6, iclass 5, count 0 2006.201.02:07:21.16#ibcon#end of sib2, iclass 5, count 0 2006.201.02:07:21.16#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:07:21.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:07:21.16#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:07:21.16#ibcon#*before write, iclass 5, count 0 2006.201.02:07:21.16#ibcon#enter sib2, iclass 5, count 0 2006.201.02:07:21.16#ibcon#flushed, iclass 5, count 0 2006.201.02:07:21.16#ibcon#about to write, iclass 5, count 0 2006.201.02:07:21.16#ibcon#wrote, iclass 5, count 0 2006.201.02:07:21.16#ibcon#about to read 3, iclass 5, count 0 2006.201.02:07:21.17#abcon#<5=/05 2.9 5.8 22.91 911005.1\r\n> 2006.201.02:07:21.19#abcon#{5=INTERFACE CLEAR} 2006.201.02:07:21.20#ibcon#read 3, iclass 5, count 0 2006.201.02:07:21.20#ibcon#about to read 4, iclass 5, count 0 2006.201.02:07:21.20#ibcon#read 4, iclass 5, count 0 2006.201.02:07:21.20#ibcon#about to read 5, iclass 5, count 0 2006.201.02:07:21.20#ibcon#read 5, iclass 5, count 0 2006.201.02:07:21.20#ibcon#about to read 6, iclass 5, count 0 2006.201.02:07:21.20#ibcon#read 6, iclass 5, count 0 2006.201.02:07:21.20#ibcon#end of sib2, iclass 5, count 0 2006.201.02:07:21.20#ibcon#*after write, iclass 5, count 0 2006.201.02:07:21.20#ibcon#*before return 0, iclass 5, count 0 2006.201.02:07:21.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:07:21.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:07:21.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:07:21.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:07:21.20$vck44/vb=8,4 2006.201.02:07:21.20#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.02:07:21.20#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.02:07:21.20#ibcon#ireg 11 cls_cnt 2 2006.201.02:07:21.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:07:21.25#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:07:21.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:07:21.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:07:21.26#ibcon#enter wrdev, iclass 11, count 2 2006.201.02:07:21.26#ibcon#first serial, iclass 11, count 2 2006.201.02:07:21.26#ibcon#enter sib2, iclass 11, count 2 2006.201.02:07:21.26#ibcon#flushed, iclass 11, count 2 2006.201.02:07:21.26#ibcon#about to write, iclass 11, count 2 2006.201.02:07:21.26#ibcon#wrote, iclass 11, count 2 2006.201.02:07:21.26#ibcon#about to read 3, iclass 11, count 2 2006.201.02:07:21.28#ibcon#read 3, iclass 11, count 2 2006.201.02:07:21.28#ibcon#about to read 4, iclass 11, count 2 2006.201.02:07:21.28#ibcon#read 4, iclass 11, count 2 2006.201.02:07:21.28#ibcon#about to read 5, iclass 11, count 2 2006.201.02:07:21.28#ibcon#read 5, iclass 11, count 2 2006.201.02:07:21.28#ibcon#about to read 6, iclass 11, count 2 2006.201.02:07:21.28#ibcon#read 6, iclass 11, count 2 2006.201.02:07:21.28#ibcon#end of sib2, iclass 11, count 2 2006.201.02:07:21.28#ibcon#*mode == 0, iclass 11, count 2 2006.201.02:07:21.28#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.02:07:21.28#ibcon#[27=AT08-04\r\n] 2006.201.02:07:21.28#ibcon#*before write, iclass 11, count 2 2006.201.02:07:21.28#ibcon#enter sib2, iclass 11, count 2 2006.201.02:07:21.28#ibcon#flushed, iclass 11, count 2 2006.201.02:07:21.28#ibcon#about to write, iclass 11, count 2 2006.201.02:07:21.28#ibcon#wrote, iclass 11, count 2 2006.201.02:07:21.28#ibcon#about to read 3, iclass 11, count 2 2006.201.02:07:21.31#ibcon#read 3, iclass 11, count 2 2006.201.02:07:21.31#ibcon#about to read 4, iclass 11, count 2 2006.201.02:07:21.31#ibcon#read 4, iclass 11, count 2 2006.201.02:07:21.31#ibcon#about to read 5, iclass 11, count 2 2006.201.02:07:21.31#ibcon#read 5, iclass 11, count 2 2006.201.02:07:21.31#ibcon#about to read 6, iclass 11, count 2 2006.201.02:07:21.31#ibcon#read 6, iclass 11, count 2 2006.201.02:07:21.31#ibcon#end of sib2, iclass 11, count 2 2006.201.02:07:21.31#ibcon#*after write, iclass 11, count 2 2006.201.02:07:21.31#ibcon#*before return 0, iclass 11, count 2 2006.201.02:07:21.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:07:21.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:07:21.31#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.02:07:21.31#ibcon#ireg 7 cls_cnt 0 2006.201.02:07:21.31#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:07:21.43#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:07:21.43#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:07:21.43#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:07:21.43#ibcon#first serial, iclass 11, count 0 2006.201.02:07:21.43#ibcon#enter sib2, iclass 11, count 0 2006.201.02:07:21.43#ibcon#flushed, iclass 11, count 0 2006.201.02:07:21.43#ibcon#about to write, iclass 11, count 0 2006.201.02:07:21.43#ibcon#wrote, iclass 11, count 0 2006.201.02:07:21.43#ibcon#about to read 3, iclass 11, count 0 2006.201.02:07:21.45#ibcon#read 3, iclass 11, count 0 2006.201.02:07:21.45#ibcon#about to read 4, iclass 11, count 0 2006.201.02:07:21.45#ibcon#read 4, iclass 11, count 0 2006.201.02:07:21.45#ibcon#about to read 5, iclass 11, count 0 2006.201.02:07:21.45#ibcon#read 5, iclass 11, count 0 2006.201.02:07:21.45#ibcon#about to read 6, iclass 11, count 0 2006.201.02:07:21.45#ibcon#read 6, iclass 11, count 0 2006.201.02:07:21.45#ibcon#end of sib2, iclass 11, count 0 2006.201.02:07:21.45#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:07:21.45#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:07:21.45#ibcon#[27=USB\r\n] 2006.201.02:07:21.45#ibcon#*before write, iclass 11, count 0 2006.201.02:07:21.45#ibcon#enter sib2, iclass 11, count 0 2006.201.02:07:21.45#ibcon#flushed, iclass 11, count 0 2006.201.02:07:21.45#ibcon#about to write, iclass 11, count 0 2006.201.02:07:21.45#ibcon#wrote, iclass 11, count 0 2006.201.02:07:21.45#ibcon#about to read 3, iclass 11, count 0 2006.201.02:07:21.48#ibcon#read 3, iclass 11, count 0 2006.201.02:07:21.48#ibcon#about to read 4, iclass 11, count 0 2006.201.02:07:21.48#ibcon#read 4, iclass 11, count 0 2006.201.02:07:21.48#ibcon#about to read 5, iclass 11, count 0 2006.201.02:07:21.48#ibcon#read 5, iclass 11, count 0 2006.201.02:07:21.48#ibcon#about to read 6, iclass 11, count 0 2006.201.02:07:21.48#ibcon#read 6, iclass 11, count 0 2006.201.02:07:21.48#ibcon#end of sib2, iclass 11, count 0 2006.201.02:07:21.48#ibcon#*after write, iclass 11, count 0 2006.201.02:07:21.48#ibcon#*before return 0, iclass 11, count 0 2006.201.02:07:21.48#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:07:21.48#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:07:21.48#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:07:21.48#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:07:21.48$vck44/vabw=wide 2006.201.02:07:21.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.02:07:21.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.02:07:21.48#ibcon#ireg 8 cls_cnt 0 2006.201.02:07:21.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:21.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:21.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:21.48#ibcon#enter wrdev, iclass 14, count 0 2006.201.02:07:21.48#ibcon#first serial, iclass 14, count 0 2006.201.02:07:21.48#ibcon#enter sib2, iclass 14, count 0 2006.201.02:07:21.48#ibcon#flushed, iclass 14, count 0 2006.201.02:07:21.48#ibcon#about to write, iclass 14, count 0 2006.201.02:07:21.48#ibcon#wrote, iclass 14, count 0 2006.201.02:07:21.48#ibcon#about to read 3, iclass 14, count 0 2006.201.02:07:21.50#ibcon#read 3, iclass 14, count 0 2006.201.02:07:21.50#ibcon#about to read 4, iclass 14, count 0 2006.201.02:07:21.50#ibcon#read 4, iclass 14, count 0 2006.201.02:07:21.50#ibcon#about to read 5, iclass 14, count 0 2006.201.02:07:21.50#ibcon#read 5, iclass 14, count 0 2006.201.02:07:21.50#ibcon#about to read 6, iclass 14, count 0 2006.201.02:07:21.50#ibcon#read 6, iclass 14, count 0 2006.201.02:07:21.50#ibcon#end of sib2, iclass 14, count 0 2006.201.02:07:21.50#ibcon#*mode == 0, iclass 14, count 0 2006.201.02:07:21.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.02:07:21.50#ibcon#[25=BW32\r\n] 2006.201.02:07:21.50#ibcon#*before write, iclass 14, count 0 2006.201.02:07:21.50#ibcon#enter sib2, iclass 14, count 0 2006.201.02:07:21.50#ibcon#flushed, iclass 14, count 0 2006.201.02:07:21.50#ibcon#about to write, iclass 14, count 0 2006.201.02:07:21.50#ibcon#wrote, iclass 14, count 0 2006.201.02:07:21.50#ibcon#about to read 3, iclass 14, count 0 2006.201.02:07:21.53#ibcon#read 3, iclass 14, count 0 2006.201.02:07:21.53#ibcon#about to read 4, iclass 14, count 0 2006.201.02:07:21.53#ibcon#read 4, iclass 14, count 0 2006.201.02:07:21.53#ibcon#about to read 5, iclass 14, count 0 2006.201.02:07:21.53#ibcon#read 5, iclass 14, count 0 2006.201.02:07:21.53#ibcon#about to read 6, iclass 14, count 0 2006.201.02:07:21.53#ibcon#read 6, iclass 14, count 0 2006.201.02:07:21.53#ibcon#end of sib2, iclass 14, count 0 2006.201.02:07:21.53#ibcon#*after write, iclass 14, count 0 2006.201.02:07:21.53#ibcon#*before return 0, iclass 14, count 0 2006.201.02:07:21.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:21.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:07:21.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.02:07:21.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.02:07:21.53$vck44/vbbw=wide 2006.201.02:07:21.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.02:07:21.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.02:07:21.53#ibcon#ireg 8 cls_cnt 0 2006.201.02:07:21.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:07:21.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:07:21.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:07:21.60#ibcon#enter wrdev, iclass 16, count 0 2006.201.02:07:21.60#ibcon#first serial, iclass 16, count 0 2006.201.02:07:21.60#ibcon#enter sib2, iclass 16, count 0 2006.201.02:07:21.60#ibcon#flushed, iclass 16, count 0 2006.201.02:07:21.60#ibcon#about to write, iclass 16, count 0 2006.201.02:07:21.60#ibcon#wrote, iclass 16, count 0 2006.201.02:07:21.60#ibcon#about to read 3, iclass 16, count 0 2006.201.02:07:21.62#ibcon#read 3, iclass 16, count 0 2006.201.02:07:21.62#ibcon#about to read 4, iclass 16, count 0 2006.201.02:07:21.62#ibcon#read 4, iclass 16, count 0 2006.201.02:07:21.62#ibcon#about to read 5, iclass 16, count 0 2006.201.02:07:21.62#ibcon#read 5, iclass 16, count 0 2006.201.02:07:21.62#ibcon#about to read 6, iclass 16, count 0 2006.201.02:07:21.62#ibcon#read 6, iclass 16, count 0 2006.201.02:07:21.62#ibcon#end of sib2, iclass 16, count 0 2006.201.02:07:21.62#ibcon#*mode == 0, iclass 16, count 0 2006.201.02:07:21.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.02:07:21.62#ibcon#[27=BW32\r\n] 2006.201.02:07:21.62#ibcon#*before write, iclass 16, count 0 2006.201.02:07:21.62#ibcon#enter sib2, iclass 16, count 0 2006.201.02:07:21.62#ibcon#flushed, iclass 16, count 0 2006.201.02:07:21.62#ibcon#about to write, iclass 16, count 0 2006.201.02:07:21.62#ibcon#wrote, iclass 16, count 0 2006.201.02:07:21.62#ibcon#about to read 3, iclass 16, count 0 2006.201.02:07:21.65#ibcon#read 3, iclass 16, count 0 2006.201.02:07:21.65#ibcon#about to read 4, iclass 16, count 0 2006.201.02:07:21.65#ibcon#read 4, iclass 16, count 0 2006.201.02:07:21.65#ibcon#about to read 5, iclass 16, count 0 2006.201.02:07:21.65#ibcon#read 5, iclass 16, count 0 2006.201.02:07:21.65#ibcon#about to read 6, iclass 16, count 0 2006.201.02:07:21.65#ibcon#read 6, iclass 16, count 0 2006.201.02:07:21.65#ibcon#end of sib2, iclass 16, count 0 2006.201.02:07:21.65#ibcon#*after write, iclass 16, count 0 2006.201.02:07:21.65#ibcon#*before return 0, iclass 16, count 0 2006.201.02:07:21.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:07:21.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:07:21.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.02:07:21.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.02:07:21.65$setupk4/ifdk4 2006.201.02:07:21.65$ifdk4/lo= 2006.201.02:07:21.65$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:07:21.65$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:07:21.65$ifdk4/patch= 2006.201.02:07:21.65$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:07:21.65$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:07:21.65$setupk4/!*+20s 2006.201.02:07:31.34#abcon#<5=/05 2.9 5.8 22.91 911005.2\r\n> 2006.201.02:07:31.36#abcon#{5=INTERFACE CLEAR} 2006.201.02:07:31.42#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:07:36.11$setupk4/"tpicd 2006.201.02:07:36.11$setupk4/echo=off 2006.201.02:07:36.11$setupk4/xlog=off 2006.201.02:07:36.11:!2006.201.02:11:04 2006.201.02:07:46.13#trakl#Source acquired 2006.201.02:07:46.13#flagr#flagr/antenna,acquired 2006.201.02:11:04.00:preob 2006.201.02:11:05.14/onsource/TRACKING 2006.201.02:11:05.14:!2006.201.02:11:14 2006.201.02:11:14.00:"tape 2006.201.02:11:14.00:"st=record 2006.201.02:11:14.00:data_valid=on 2006.201.02:11:14.00:midob 2006.201.02:11:14.14/onsource/TRACKING 2006.201.02:11:14.14/wx/22.92,1005.3,92 2006.201.02:11:14.27/cable/+6.4678E-03 2006.201.02:11:15.36/va/01,08,usb,yes,28,30 2006.201.02:11:15.36/va/02,07,usb,yes,30,31 2006.201.02:11:15.36/va/03,08,usb,yes,27,28 2006.201.02:11:15.36/va/04,07,usb,yes,31,33 2006.201.02:11:15.36/va/05,04,usb,yes,27,28 2006.201.02:11:15.36/va/06,05,usb,yes,27,27 2006.201.02:11:15.36/va/07,05,usb,yes,26,28 2006.201.02:11:15.36/va/08,04,usb,yes,26,32 2006.201.02:11:15.59/valo/01,524.99,yes,locked 2006.201.02:11:15.59/valo/02,534.99,yes,locked 2006.201.02:11:15.59/valo/03,564.99,yes,locked 2006.201.02:11:15.59/valo/04,624.99,yes,locked 2006.201.02:11:15.59/valo/05,734.99,yes,locked 2006.201.02:11:15.59/valo/06,814.99,yes,locked 2006.201.02:11:15.59/valo/07,864.99,yes,locked 2006.201.02:11:15.59/valo/08,884.99,yes,locked 2006.201.02:11:16.68/vb/01,04,usb,yes,28,26 2006.201.02:11:16.68/vb/02,05,usb,yes,27,27 2006.201.02:11:16.68/vb/03,04,usb,yes,28,31 2006.201.02:11:16.68/vb/04,05,usb,yes,28,27 2006.201.02:11:16.68/vb/05,04,usb,yes,25,27 2006.201.02:11:16.68/vb/06,04,usb,yes,29,25 2006.201.02:11:16.68/vb/07,04,usb,yes,29,29 2006.201.02:11:16.68/vb/08,04,usb,yes,26,30 2006.201.02:11:16.92/vblo/01,629.99,yes,locked 2006.201.02:11:16.92/vblo/02,634.99,yes,locked 2006.201.02:11:16.92/vblo/03,649.99,yes,locked 2006.201.02:11:16.92/vblo/04,679.99,yes,locked 2006.201.02:11:16.92/vblo/05,709.99,yes,locked 2006.201.02:11:16.92/vblo/06,719.99,yes,locked 2006.201.02:11:16.92/vblo/07,734.99,yes,locked 2006.201.02:11:16.92/vblo/08,744.99,yes,locked 2006.201.02:11:17.07/vabw/8 2006.201.02:11:17.22/vbbw/8 2006.201.02:11:17.31/xfe/off,on,14.7 2006.201.02:11:17.70/ifatt/23,28,28,28 2006.201.02:11:18.04/fmout-gps/S +4.44E-07 2006.201.02:11:18.11:!2006.201.02:12:44 2006.201.02:12:44.00:data_valid=off 2006.201.02:12:44.00:"et 2006.201.02:12:44.00:!+3s 2006.201.02:12:47.02:"tape 2006.201.02:12:47.02:postob 2006.201.02:12:47.19/cable/+6.4670E-03 2006.201.02:12:47.19/wx/22.91,1005.4,91 2006.201.02:12:47.27/fmout-gps/S +4.43E-07 2006.201.02:12:47.27:scan_name=201-0215,jd0607,40 2006.201.02:12:47.28:source=0537-441,053850.36,-440508.9,2000.0,ccw 2006.201.02:12:48.14#flagr#flagr/antenna,new-source 2006.201.02:12:48.14:checkk5 2006.201.02:12:48.57/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:12:48.98/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:12:49.36/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:12:49.73/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:12:50.15/chk_obsdata//k5ts1/T2010211??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.02:12:50.57/chk_obsdata//k5ts2/T2010211??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.02:12:50.95/chk_obsdata//k5ts3/T2010211??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.02:12:51.35/chk_obsdata//k5ts4/T2010211??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.02:12:52.12/k5log//k5ts1_log_newline 2006.201.02:12:52.94/k5log//k5ts2_log_newline 2006.201.02:12:53.72/k5log//k5ts3_log_newline 2006.201.02:12:54.49/k5log//k5ts4_log_newline 2006.201.02:12:54.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:12:54.51:setupk4=1 2006.201.02:12:54.51$setupk4/echo=on 2006.201.02:12:54.51$setupk4/pcalon 2006.201.02:12:54.51$pcalon/"no phase cal control is implemented here 2006.201.02:12:54.51$setupk4/"tpicd=stop 2006.201.02:12:54.51$setupk4/"rec=synch_on 2006.201.02:12:54.51$setupk4/"rec_mode=128 2006.201.02:12:54.51$setupk4/!* 2006.201.02:12:54.51$setupk4/recpk4 2006.201.02:12:54.51$recpk4/recpatch= 2006.201.02:12:54.52$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:12:54.52$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:12:54.52$setupk4/vck44 2006.201.02:12:54.52$vck44/valo=1,524.99 2006.201.02:12:54.52#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.02:12:54.52#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.02:12:54.52#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:54.52#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:54.52#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:54.52#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:54.52#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:12:54.52#ibcon#first serial, iclass 2, count 0 2006.201.02:12:54.52#ibcon#enter sib2, iclass 2, count 0 2006.201.02:12:54.52#ibcon#flushed, iclass 2, count 0 2006.201.02:12:54.52#ibcon#about to write, iclass 2, count 0 2006.201.02:12:54.52#ibcon#wrote, iclass 2, count 0 2006.201.02:12:54.52#ibcon#about to read 3, iclass 2, count 0 2006.201.02:12:54.56#ibcon#read 3, iclass 2, count 0 2006.201.02:12:54.56#ibcon#about to read 4, iclass 2, count 0 2006.201.02:12:54.56#ibcon#read 4, iclass 2, count 0 2006.201.02:12:54.56#ibcon#about to read 5, iclass 2, count 0 2006.201.02:12:54.56#ibcon#read 5, iclass 2, count 0 2006.201.02:12:54.56#ibcon#about to read 6, iclass 2, count 0 2006.201.02:12:54.56#ibcon#read 6, iclass 2, count 0 2006.201.02:12:54.56#ibcon#end of sib2, iclass 2, count 0 2006.201.02:12:54.56#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:12:54.56#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:12:54.56#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:12:54.56#ibcon#*before write, iclass 2, count 0 2006.201.02:12:54.56#ibcon#enter sib2, iclass 2, count 0 2006.201.02:12:54.56#ibcon#flushed, iclass 2, count 0 2006.201.02:12:54.56#ibcon#about to write, iclass 2, count 0 2006.201.02:12:54.56#ibcon#wrote, iclass 2, count 0 2006.201.02:12:54.56#ibcon#about to read 3, iclass 2, count 0 2006.201.02:12:54.61#ibcon#read 3, iclass 2, count 0 2006.201.02:12:54.61#ibcon#about to read 4, iclass 2, count 0 2006.201.02:12:54.61#ibcon#read 4, iclass 2, count 0 2006.201.02:12:54.61#ibcon#about to read 5, iclass 2, count 0 2006.201.02:12:54.61#ibcon#read 5, iclass 2, count 0 2006.201.02:12:54.61#ibcon#about to read 6, iclass 2, count 0 2006.201.02:12:54.61#ibcon#read 6, iclass 2, count 0 2006.201.02:12:54.61#ibcon#end of sib2, iclass 2, count 0 2006.201.02:12:54.61#ibcon#*after write, iclass 2, count 0 2006.201.02:12:54.61#ibcon#*before return 0, iclass 2, count 0 2006.201.02:12:54.61#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:54.61#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:54.61#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:12:54.61#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:12:54.61$vck44/va=1,8 2006.201.02:12:54.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.02:12:54.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.02:12:54.61#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:54.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:54.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:54.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:54.61#ibcon#enter wrdev, iclass 5, count 2 2006.201.02:12:54.61#ibcon#first serial, iclass 5, count 2 2006.201.02:12:54.61#ibcon#enter sib2, iclass 5, count 2 2006.201.02:12:54.61#ibcon#flushed, iclass 5, count 2 2006.201.02:12:54.61#ibcon#about to write, iclass 5, count 2 2006.201.02:12:54.61#ibcon#wrote, iclass 5, count 2 2006.201.02:12:54.61#ibcon#about to read 3, iclass 5, count 2 2006.201.02:12:54.63#ibcon#read 3, iclass 5, count 2 2006.201.02:12:54.63#ibcon#about to read 4, iclass 5, count 2 2006.201.02:12:54.63#ibcon#read 4, iclass 5, count 2 2006.201.02:12:54.63#ibcon#about to read 5, iclass 5, count 2 2006.201.02:12:54.63#ibcon#read 5, iclass 5, count 2 2006.201.02:12:54.63#ibcon#about to read 6, iclass 5, count 2 2006.201.02:12:54.63#ibcon#read 6, iclass 5, count 2 2006.201.02:12:54.63#ibcon#end of sib2, iclass 5, count 2 2006.201.02:12:54.63#ibcon#*mode == 0, iclass 5, count 2 2006.201.02:12:54.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.02:12:54.63#ibcon#[25=AT01-08\r\n] 2006.201.02:12:54.63#ibcon#*before write, iclass 5, count 2 2006.201.02:12:54.63#ibcon#enter sib2, iclass 5, count 2 2006.201.02:12:54.63#ibcon#flushed, iclass 5, count 2 2006.201.02:12:54.63#ibcon#about to write, iclass 5, count 2 2006.201.02:12:54.63#ibcon#wrote, iclass 5, count 2 2006.201.02:12:54.63#ibcon#about to read 3, iclass 5, count 2 2006.201.02:12:54.66#ibcon#read 3, iclass 5, count 2 2006.201.02:12:54.66#ibcon#about to read 4, iclass 5, count 2 2006.201.02:12:54.66#ibcon#read 4, iclass 5, count 2 2006.201.02:12:54.66#ibcon#about to read 5, iclass 5, count 2 2006.201.02:12:54.66#ibcon#read 5, iclass 5, count 2 2006.201.02:12:54.66#ibcon#about to read 6, iclass 5, count 2 2006.201.02:12:54.66#ibcon#read 6, iclass 5, count 2 2006.201.02:12:54.66#ibcon#end of sib2, iclass 5, count 2 2006.201.02:12:54.66#ibcon#*after write, iclass 5, count 2 2006.201.02:12:54.66#ibcon#*before return 0, iclass 5, count 2 2006.201.02:12:54.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:54.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:54.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.02:12:54.66#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:54.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:54.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:54.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:54.78#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:12:54.78#ibcon#first serial, iclass 5, count 0 2006.201.02:12:54.78#ibcon#enter sib2, iclass 5, count 0 2006.201.02:12:54.78#ibcon#flushed, iclass 5, count 0 2006.201.02:12:54.78#ibcon#about to write, iclass 5, count 0 2006.201.02:12:54.78#ibcon#wrote, iclass 5, count 0 2006.201.02:12:54.78#ibcon#about to read 3, iclass 5, count 0 2006.201.02:12:54.80#ibcon#read 3, iclass 5, count 0 2006.201.02:12:54.80#ibcon#about to read 4, iclass 5, count 0 2006.201.02:12:54.80#ibcon#read 4, iclass 5, count 0 2006.201.02:12:54.80#ibcon#about to read 5, iclass 5, count 0 2006.201.02:12:54.80#ibcon#read 5, iclass 5, count 0 2006.201.02:12:54.80#ibcon#about to read 6, iclass 5, count 0 2006.201.02:12:54.80#ibcon#read 6, iclass 5, count 0 2006.201.02:12:54.80#ibcon#end of sib2, iclass 5, count 0 2006.201.02:12:54.80#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:12:54.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:12:54.80#ibcon#[25=USB\r\n] 2006.201.02:12:54.80#ibcon#*before write, iclass 5, count 0 2006.201.02:12:54.80#ibcon#enter sib2, iclass 5, count 0 2006.201.02:12:54.80#ibcon#flushed, iclass 5, count 0 2006.201.02:12:54.80#ibcon#about to write, iclass 5, count 0 2006.201.02:12:54.80#ibcon#wrote, iclass 5, count 0 2006.201.02:12:54.80#ibcon#about to read 3, iclass 5, count 0 2006.201.02:12:54.83#ibcon#read 3, iclass 5, count 0 2006.201.02:12:54.83#ibcon#about to read 4, iclass 5, count 0 2006.201.02:12:54.83#ibcon#read 4, iclass 5, count 0 2006.201.02:12:54.83#ibcon#about to read 5, iclass 5, count 0 2006.201.02:12:54.83#ibcon#read 5, iclass 5, count 0 2006.201.02:12:54.83#ibcon#about to read 6, iclass 5, count 0 2006.201.02:12:54.83#ibcon#read 6, iclass 5, count 0 2006.201.02:12:54.83#ibcon#end of sib2, iclass 5, count 0 2006.201.02:12:54.83#ibcon#*after write, iclass 5, count 0 2006.201.02:12:54.83#ibcon#*before return 0, iclass 5, count 0 2006.201.02:12:54.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:54.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:54.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:12:54.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:12:54.83$vck44/valo=2,534.99 2006.201.02:12:54.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.02:12:54.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.02:12:54.83#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:54.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:54.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:54.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:54.83#ibcon#enter wrdev, iclass 7, count 0 2006.201.02:12:54.83#ibcon#first serial, iclass 7, count 0 2006.201.02:12:54.83#ibcon#enter sib2, iclass 7, count 0 2006.201.02:12:54.83#ibcon#flushed, iclass 7, count 0 2006.201.02:12:54.83#ibcon#about to write, iclass 7, count 0 2006.201.02:12:54.83#ibcon#wrote, iclass 7, count 0 2006.201.02:12:54.83#ibcon#about to read 3, iclass 7, count 0 2006.201.02:12:54.85#ibcon#read 3, iclass 7, count 0 2006.201.02:12:54.85#ibcon#about to read 4, iclass 7, count 0 2006.201.02:12:54.85#ibcon#read 4, iclass 7, count 0 2006.201.02:12:54.85#ibcon#about to read 5, iclass 7, count 0 2006.201.02:12:54.85#ibcon#read 5, iclass 7, count 0 2006.201.02:12:54.85#ibcon#about to read 6, iclass 7, count 0 2006.201.02:12:54.85#ibcon#read 6, iclass 7, count 0 2006.201.02:12:54.85#ibcon#end of sib2, iclass 7, count 0 2006.201.02:12:54.85#ibcon#*mode == 0, iclass 7, count 0 2006.201.02:12:54.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.02:12:54.85#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:12:54.85#ibcon#*before write, iclass 7, count 0 2006.201.02:12:54.85#ibcon#enter sib2, iclass 7, count 0 2006.201.02:12:54.85#ibcon#flushed, iclass 7, count 0 2006.201.02:12:54.85#ibcon#about to write, iclass 7, count 0 2006.201.02:12:54.85#ibcon#wrote, iclass 7, count 0 2006.201.02:12:54.85#ibcon#about to read 3, iclass 7, count 0 2006.201.02:12:54.90#ibcon#read 3, iclass 7, count 0 2006.201.02:12:54.90#ibcon#about to read 4, iclass 7, count 0 2006.201.02:12:54.90#ibcon#read 4, iclass 7, count 0 2006.201.02:12:54.90#ibcon#about to read 5, iclass 7, count 0 2006.201.02:12:54.90#ibcon#read 5, iclass 7, count 0 2006.201.02:12:54.90#ibcon#about to read 6, iclass 7, count 0 2006.201.02:12:54.90#ibcon#read 6, iclass 7, count 0 2006.201.02:12:54.90#ibcon#end of sib2, iclass 7, count 0 2006.201.02:12:54.90#ibcon#*after write, iclass 7, count 0 2006.201.02:12:54.90#ibcon#*before return 0, iclass 7, count 0 2006.201.02:12:54.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:54.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:54.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.02:12:54.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.02:12:54.90$vck44/va=2,7 2006.201.02:12:54.90#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.02:12:54.90#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.02:12:54.90#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:54.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:54.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:54.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:54.95#ibcon#enter wrdev, iclass 11, count 2 2006.201.02:12:54.95#ibcon#first serial, iclass 11, count 2 2006.201.02:12:54.95#ibcon#enter sib2, iclass 11, count 2 2006.201.02:12:54.95#ibcon#flushed, iclass 11, count 2 2006.201.02:12:54.95#ibcon#about to write, iclass 11, count 2 2006.201.02:12:54.95#ibcon#wrote, iclass 11, count 2 2006.201.02:12:54.95#ibcon#about to read 3, iclass 11, count 2 2006.201.02:12:54.97#ibcon#read 3, iclass 11, count 2 2006.201.02:12:54.97#ibcon#about to read 4, iclass 11, count 2 2006.201.02:12:54.97#ibcon#read 4, iclass 11, count 2 2006.201.02:12:54.97#ibcon#about to read 5, iclass 11, count 2 2006.201.02:12:54.97#ibcon#read 5, iclass 11, count 2 2006.201.02:12:54.97#ibcon#about to read 6, iclass 11, count 2 2006.201.02:12:54.97#ibcon#read 6, iclass 11, count 2 2006.201.02:12:54.97#ibcon#end of sib2, iclass 11, count 2 2006.201.02:12:54.97#ibcon#*mode == 0, iclass 11, count 2 2006.201.02:12:54.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.02:12:54.97#ibcon#[25=AT02-07\r\n] 2006.201.02:12:54.97#ibcon#*before write, iclass 11, count 2 2006.201.02:12:54.97#ibcon#enter sib2, iclass 11, count 2 2006.201.02:12:54.97#ibcon#flushed, iclass 11, count 2 2006.201.02:12:54.97#ibcon#about to write, iclass 11, count 2 2006.201.02:12:54.97#ibcon#wrote, iclass 11, count 2 2006.201.02:12:54.97#ibcon#about to read 3, iclass 11, count 2 2006.201.02:12:55.00#ibcon#read 3, iclass 11, count 2 2006.201.02:12:55.00#ibcon#about to read 4, iclass 11, count 2 2006.201.02:12:55.00#ibcon#read 4, iclass 11, count 2 2006.201.02:12:55.00#ibcon#about to read 5, iclass 11, count 2 2006.201.02:12:55.00#ibcon#read 5, iclass 11, count 2 2006.201.02:12:55.00#ibcon#about to read 6, iclass 11, count 2 2006.201.02:12:55.00#ibcon#read 6, iclass 11, count 2 2006.201.02:12:55.00#ibcon#end of sib2, iclass 11, count 2 2006.201.02:12:55.00#ibcon#*after write, iclass 11, count 2 2006.201.02:12:55.00#ibcon#*before return 0, iclass 11, count 2 2006.201.02:12:55.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:55.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:55.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.02:12:55.00#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:55.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:55.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:55.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:55.12#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:12:55.12#ibcon#first serial, iclass 11, count 0 2006.201.02:12:55.12#ibcon#enter sib2, iclass 11, count 0 2006.201.02:12:55.12#ibcon#flushed, iclass 11, count 0 2006.201.02:12:55.12#ibcon#about to write, iclass 11, count 0 2006.201.02:12:55.12#ibcon#wrote, iclass 11, count 0 2006.201.02:12:55.12#ibcon#about to read 3, iclass 11, count 0 2006.201.02:12:55.14#ibcon#read 3, iclass 11, count 0 2006.201.02:12:55.14#ibcon#about to read 4, iclass 11, count 0 2006.201.02:12:55.14#ibcon#read 4, iclass 11, count 0 2006.201.02:12:55.14#ibcon#about to read 5, iclass 11, count 0 2006.201.02:12:55.14#ibcon#read 5, iclass 11, count 0 2006.201.02:12:55.14#ibcon#about to read 6, iclass 11, count 0 2006.201.02:12:55.14#ibcon#read 6, iclass 11, count 0 2006.201.02:12:55.14#ibcon#end of sib2, iclass 11, count 0 2006.201.02:12:55.14#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:12:55.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:12:55.14#ibcon#[25=USB\r\n] 2006.201.02:12:55.14#ibcon#*before write, iclass 11, count 0 2006.201.02:12:55.14#ibcon#enter sib2, iclass 11, count 0 2006.201.02:12:55.14#ibcon#flushed, iclass 11, count 0 2006.201.02:12:55.14#ibcon#about to write, iclass 11, count 0 2006.201.02:12:55.14#ibcon#wrote, iclass 11, count 0 2006.201.02:12:55.14#ibcon#about to read 3, iclass 11, count 0 2006.201.02:12:55.17#ibcon#read 3, iclass 11, count 0 2006.201.02:12:55.17#ibcon#about to read 4, iclass 11, count 0 2006.201.02:12:55.17#ibcon#read 4, iclass 11, count 0 2006.201.02:12:55.17#ibcon#about to read 5, iclass 11, count 0 2006.201.02:12:55.17#ibcon#read 5, iclass 11, count 0 2006.201.02:12:55.17#ibcon#about to read 6, iclass 11, count 0 2006.201.02:12:55.17#ibcon#read 6, iclass 11, count 0 2006.201.02:12:55.17#ibcon#end of sib2, iclass 11, count 0 2006.201.02:12:55.17#ibcon#*after write, iclass 11, count 0 2006.201.02:12:55.17#ibcon#*before return 0, iclass 11, count 0 2006.201.02:12:55.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:55.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:55.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:12:55.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:12:55.17$vck44/valo=3,564.99 2006.201.02:12:55.17#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.02:12:55.17#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.02:12:55.17#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:55.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:55.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:55.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:55.17#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:12:55.17#ibcon#first serial, iclass 13, count 0 2006.201.02:12:55.17#ibcon#enter sib2, iclass 13, count 0 2006.201.02:12:55.17#ibcon#flushed, iclass 13, count 0 2006.201.02:12:55.17#ibcon#about to write, iclass 13, count 0 2006.201.02:12:55.17#ibcon#wrote, iclass 13, count 0 2006.201.02:12:55.17#ibcon#about to read 3, iclass 13, count 0 2006.201.02:12:55.19#ibcon#read 3, iclass 13, count 0 2006.201.02:12:55.19#ibcon#about to read 4, iclass 13, count 0 2006.201.02:12:55.19#ibcon#read 4, iclass 13, count 0 2006.201.02:12:55.19#ibcon#about to read 5, iclass 13, count 0 2006.201.02:12:55.19#ibcon#read 5, iclass 13, count 0 2006.201.02:12:55.19#ibcon#about to read 6, iclass 13, count 0 2006.201.02:12:55.19#ibcon#read 6, iclass 13, count 0 2006.201.02:12:55.19#ibcon#end of sib2, iclass 13, count 0 2006.201.02:12:55.19#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:12:55.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:12:55.19#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:12:55.19#ibcon#*before write, iclass 13, count 0 2006.201.02:12:55.19#ibcon#enter sib2, iclass 13, count 0 2006.201.02:12:55.19#ibcon#flushed, iclass 13, count 0 2006.201.02:12:55.19#ibcon#about to write, iclass 13, count 0 2006.201.02:12:55.19#ibcon#wrote, iclass 13, count 0 2006.201.02:12:55.19#ibcon#about to read 3, iclass 13, count 0 2006.201.02:12:55.24#ibcon#read 3, iclass 13, count 0 2006.201.02:12:55.24#ibcon#about to read 4, iclass 13, count 0 2006.201.02:12:55.24#ibcon#read 4, iclass 13, count 0 2006.201.02:12:55.24#ibcon#about to read 5, iclass 13, count 0 2006.201.02:12:55.24#ibcon#read 5, iclass 13, count 0 2006.201.02:12:55.24#ibcon#about to read 6, iclass 13, count 0 2006.201.02:12:55.24#ibcon#read 6, iclass 13, count 0 2006.201.02:12:55.24#ibcon#end of sib2, iclass 13, count 0 2006.201.02:12:55.24#ibcon#*after write, iclass 13, count 0 2006.201.02:12:55.24#ibcon#*before return 0, iclass 13, count 0 2006.201.02:12:55.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:55.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:55.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:12:55.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:12:55.24$vck44/va=3,8 2006.201.02:12:55.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.02:12:55.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.02:12:55.24#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:55.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:55.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:55.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:55.29#ibcon#enter wrdev, iclass 15, count 2 2006.201.02:12:55.29#ibcon#first serial, iclass 15, count 2 2006.201.02:12:55.29#ibcon#enter sib2, iclass 15, count 2 2006.201.02:12:55.29#ibcon#flushed, iclass 15, count 2 2006.201.02:12:55.29#ibcon#about to write, iclass 15, count 2 2006.201.02:12:55.29#ibcon#wrote, iclass 15, count 2 2006.201.02:12:55.29#ibcon#about to read 3, iclass 15, count 2 2006.201.02:12:55.31#ibcon#read 3, iclass 15, count 2 2006.201.02:12:55.31#ibcon#about to read 4, iclass 15, count 2 2006.201.02:12:55.31#ibcon#read 4, iclass 15, count 2 2006.201.02:12:55.31#ibcon#about to read 5, iclass 15, count 2 2006.201.02:12:55.31#ibcon#read 5, iclass 15, count 2 2006.201.02:12:55.31#ibcon#about to read 6, iclass 15, count 2 2006.201.02:12:55.31#ibcon#read 6, iclass 15, count 2 2006.201.02:12:55.31#ibcon#end of sib2, iclass 15, count 2 2006.201.02:12:55.31#ibcon#*mode == 0, iclass 15, count 2 2006.201.02:12:55.31#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.02:12:55.31#ibcon#[25=AT03-08\r\n] 2006.201.02:12:55.31#ibcon#*before write, iclass 15, count 2 2006.201.02:12:55.31#ibcon#enter sib2, iclass 15, count 2 2006.201.02:12:55.31#ibcon#flushed, iclass 15, count 2 2006.201.02:12:55.31#ibcon#about to write, iclass 15, count 2 2006.201.02:12:55.31#ibcon#wrote, iclass 15, count 2 2006.201.02:12:55.31#ibcon#about to read 3, iclass 15, count 2 2006.201.02:12:55.34#ibcon#read 3, iclass 15, count 2 2006.201.02:12:55.34#ibcon#about to read 4, iclass 15, count 2 2006.201.02:12:55.34#ibcon#read 4, iclass 15, count 2 2006.201.02:12:55.34#ibcon#about to read 5, iclass 15, count 2 2006.201.02:12:55.34#ibcon#read 5, iclass 15, count 2 2006.201.02:12:55.34#ibcon#about to read 6, iclass 15, count 2 2006.201.02:12:55.34#ibcon#read 6, iclass 15, count 2 2006.201.02:12:55.34#ibcon#end of sib2, iclass 15, count 2 2006.201.02:12:55.34#ibcon#*after write, iclass 15, count 2 2006.201.02:12:55.34#ibcon#*before return 0, iclass 15, count 2 2006.201.02:12:55.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:55.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:55.34#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.02:12:55.34#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:55.34#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:55.46#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:55.46#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:55.46#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:12:55.46#ibcon#first serial, iclass 15, count 0 2006.201.02:12:55.46#ibcon#enter sib2, iclass 15, count 0 2006.201.02:12:55.46#ibcon#flushed, iclass 15, count 0 2006.201.02:12:55.46#ibcon#about to write, iclass 15, count 0 2006.201.02:12:55.46#ibcon#wrote, iclass 15, count 0 2006.201.02:12:55.46#ibcon#about to read 3, iclass 15, count 0 2006.201.02:12:55.48#ibcon#read 3, iclass 15, count 0 2006.201.02:12:55.48#ibcon#about to read 4, iclass 15, count 0 2006.201.02:12:55.48#ibcon#read 4, iclass 15, count 0 2006.201.02:12:55.48#ibcon#about to read 5, iclass 15, count 0 2006.201.02:12:55.48#ibcon#read 5, iclass 15, count 0 2006.201.02:12:55.48#ibcon#about to read 6, iclass 15, count 0 2006.201.02:12:55.48#ibcon#read 6, iclass 15, count 0 2006.201.02:12:55.48#ibcon#end of sib2, iclass 15, count 0 2006.201.02:12:55.48#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:12:55.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:12:55.48#ibcon#[25=USB\r\n] 2006.201.02:12:55.48#ibcon#*before write, iclass 15, count 0 2006.201.02:12:55.48#ibcon#enter sib2, iclass 15, count 0 2006.201.02:12:55.48#ibcon#flushed, iclass 15, count 0 2006.201.02:12:55.48#ibcon#about to write, iclass 15, count 0 2006.201.02:12:55.48#ibcon#wrote, iclass 15, count 0 2006.201.02:12:55.48#ibcon#about to read 3, iclass 15, count 0 2006.201.02:12:55.51#ibcon#read 3, iclass 15, count 0 2006.201.02:12:55.51#ibcon#about to read 4, iclass 15, count 0 2006.201.02:12:55.51#ibcon#read 4, iclass 15, count 0 2006.201.02:12:55.51#ibcon#about to read 5, iclass 15, count 0 2006.201.02:12:55.51#ibcon#read 5, iclass 15, count 0 2006.201.02:12:55.51#ibcon#about to read 6, iclass 15, count 0 2006.201.02:12:55.51#ibcon#read 6, iclass 15, count 0 2006.201.02:12:55.51#ibcon#end of sib2, iclass 15, count 0 2006.201.02:12:55.51#ibcon#*after write, iclass 15, count 0 2006.201.02:12:55.51#ibcon#*before return 0, iclass 15, count 0 2006.201.02:12:55.51#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:55.51#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:55.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:12:55.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:12:55.51$vck44/valo=4,624.99 2006.201.02:12:55.51#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.02:12:55.51#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.02:12:55.51#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:55.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:55.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:55.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:55.51#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:12:55.51#ibcon#first serial, iclass 17, count 0 2006.201.02:12:55.51#ibcon#enter sib2, iclass 17, count 0 2006.201.02:12:55.51#ibcon#flushed, iclass 17, count 0 2006.201.02:12:55.51#ibcon#about to write, iclass 17, count 0 2006.201.02:12:55.51#ibcon#wrote, iclass 17, count 0 2006.201.02:12:55.51#ibcon#about to read 3, iclass 17, count 0 2006.201.02:12:55.53#ibcon#read 3, iclass 17, count 0 2006.201.02:12:55.53#ibcon#about to read 4, iclass 17, count 0 2006.201.02:12:55.53#ibcon#read 4, iclass 17, count 0 2006.201.02:12:55.53#ibcon#about to read 5, iclass 17, count 0 2006.201.02:12:55.53#ibcon#read 5, iclass 17, count 0 2006.201.02:12:55.53#ibcon#about to read 6, iclass 17, count 0 2006.201.02:12:55.53#ibcon#read 6, iclass 17, count 0 2006.201.02:12:55.53#ibcon#end of sib2, iclass 17, count 0 2006.201.02:12:55.53#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:12:55.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:12:55.53#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:12:55.53#ibcon#*before write, iclass 17, count 0 2006.201.02:12:55.53#ibcon#enter sib2, iclass 17, count 0 2006.201.02:12:55.53#ibcon#flushed, iclass 17, count 0 2006.201.02:12:55.53#ibcon#about to write, iclass 17, count 0 2006.201.02:12:55.53#ibcon#wrote, iclass 17, count 0 2006.201.02:12:55.53#ibcon#about to read 3, iclass 17, count 0 2006.201.02:12:55.57#ibcon#read 3, iclass 17, count 0 2006.201.02:12:55.57#ibcon#about to read 4, iclass 17, count 0 2006.201.02:12:55.57#ibcon#read 4, iclass 17, count 0 2006.201.02:12:55.57#ibcon#about to read 5, iclass 17, count 0 2006.201.02:12:55.57#ibcon#read 5, iclass 17, count 0 2006.201.02:12:55.57#ibcon#about to read 6, iclass 17, count 0 2006.201.02:12:55.57#ibcon#read 6, iclass 17, count 0 2006.201.02:12:55.57#ibcon#end of sib2, iclass 17, count 0 2006.201.02:12:55.57#ibcon#*after write, iclass 17, count 0 2006.201.02:12:55.57#ibcon#*before return 0, iclass 17, count 0 2006.201.02:12:55.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:55.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:55.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:12:55.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:12:55.57$vck44/va=4,7 2006.201.02:12:55.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.02:12:55.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.02:12:55.57#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:55.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:55.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:55.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:55.63#ibcon#enter wrdev, iclass 19, count 2 2006.201.02:12:55.63#ibcon#first serial, iclass 19, count 2 2006.201.02:12:55.63#ibcon#enter sib2, iclass 19, count 2 2006.201.02:12:55.63#ibcon#flushed, iclass 19, count 2 2006.201.02:12:55.63#ibcon#about to write, iclass 19, count 2 2006.201.02:12:55.63#ibcon#wrote, iclass 19, count 2 2006.201.02:12:55.63#ibcon#about to read 3, iclass 19, count 2 2006.201.02:12:55.65#ibcon#read 3, iclass 19, count 2 2006.201.02:12:55.65#ibcon#about to read 4, iclass 19, count 2 2006.201.02:12:55.65#ibcon#read 4, iclass 19, count 2 2006.201.02:12:55.65#ibcon#about to read 5, iclass 19, count 2 2006.201.02:12:55.65#ibcon#read 5, iclass 19, count 2 2006.201.02:12:55.65#ibcon#about to read 6, iclass 19, count 2 2006.201.02:12:55.65#ibcon#read 6, iclass 19, count 2 2006.201.02:12:55.65#ibcon#end of sib2, iclass 19, count 2 2006.201.02:12:55.65#ibcon#*mode == 0, iclass 19, count 2 2006.201.02:12:55.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.02:12:55.65#ibcon#[25=AT04-07\r\n] 2006.201.02:12:55.65#ibcon#*before write, iclass 19, count 2 2006.201.02:12:55.65#ibcon#enter sib2, iclass 19, count 2 2006.201.02:12:55.65#ibcon#flushed, iclass 19, count 2 2006.201.02:12:55.65#ibcon#about to write, iclass 19, count 2 2006.201.02:12:55.65#ibcon#wrote, iclass 19, count 2 2006.201.02:12:55.65#ibcon#about to read 3, iclass 19, count 2 2006.201.02:12:55.68#ibcon#read 3, iclass 19, count 2 2006.201.02:12:55.68#ibcon#about to read 4, iclass 19, count 2 2006.201.02:12:55.68#ibcon#read 4, iclass 19, count 2 2006.201.02:12:55.68#ibcon#about to read 5, iclass 19, count 2 2006.201.02:12:55.68#ibcon#read 5, iclass 19, count 2 2006.201.02:12:55.68#ibcon#about to read 6, iclass 19, count 2 2006.201.02:12:55.68#ibcon#read 6, iclass 19, count 2 2006.201.02:12:55.68#ibcon#end of sib2, iclass 19, count 2 2006.201.02:12:55.68#ibcon#*after write, iclass 19, count 2 2006.201.02:12:55.68#ibcon#*before return 0, iclass 19, count 2 2006.201.02:12:55.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:55.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:55.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.02:12:55.68#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:55.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:55.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:55.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:55.80#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:12:55.80#ibcon#first serial, iclass 19, count 0 2006.201.02:12:55.80#ibcon#enter sib2, iclass 19, count 0 2006.201.02:12:55.80#ibcon#flushed, iclass 19, count 0 2006.201.02:12:55.80#ibcon#about to write, iclass 19, count 0 2006.201.02:12:55.80#ibcon#wrote, iclass 19, count 0 2006.201.02:12:55.80#ibcon#about to read 3, iclass 19, count 0 2006.201.02:12:55.82#ibcon#read 3, iclass 19, count 0 2006.201.02:12:55.82#ibcon#about to read 4, iclass 19, count 0 2006.201.02:12:55.82#ibcon#read 4, iclass 19, count 0 2006.201.02:12:55.82#ibcon#about to read 5, iclass 19, count 0 2006.201.02:12:55.82#ibcon#read 5, iclass 19, count 0 2006.201.02:12:55.82#ibcon#about to read 6, iclass 19, count 0 2006.201.02:12:55.82#ibcon#read 6, iclass 19, count 0 2006.201.02:12:55.82#ibcon#end of sib2, iclass 19, count 0 2006.201.02:12:55.82#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:12:55.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:12:55.82#ibcon#[25=USB\r\n] 2006.201.02:12:55.82#ibcon#*before write, iclass 19, count 0 2006.201.02:12:55.82#ibcon#enter sib2, iclass 19, count 0 2006.201.02:12:55.82#ibcon#flushed, iclass 19, count 0 2006.201.02:12:55.82#ibcon#about to write, iclass 19, count 0 2006.201.02:12:55.82#ibcon#wrote, iclass 19, count 0 2006.201.02:12:55.82#ibcon#about to read 3, iclass 19, count 0 2006.201.02:12:55.85#ibcon#read 3, iclass 19, count 0 2006.201.02:12:55.85#ibcon#about to read 4, iclass 19, count 0 2006.201.02:12:55.85#ibcon#read 4, iclass 19, count 0 2006.201.02:12:55.85#ibcon#about to read 5, iclass 19, count 0 2006.201.02:12:55.85#ibcon#read 5, iclass 19, count 0 2006.201.02:12:55.85#ibcon#about to read 6, iclass 19, count 0 2006.201.02:12:55.85#ibcon#read 6, iclass 19, count 0 2006.201.02:12:55.85#ibcon#end of sib2, iclass 19, count 0 2006.201.02:12:55.85#ibcon#*after write, iclass 19, count 0 2006.201.02:12:55.85#ibcon#*before return 0, iclass 19, count 0 2006.201.02:12:55.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:55.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:55.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:12:55.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:12:55.85$vck44/valo=5,734.99 2006.201.02:12:55.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.02:12:55.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.02:12:55.85#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:55.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:55.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:55.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:55.85#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:12:55.85#ibcon#first serial, iclass 21, count 0 2006.201.02:12:55.85#ibcon#enter sib2, iclass 21, count 0 2006.201.02:12:55.85#ibcon#flushed, iclass 21, count 0 2006.201.02:12:55.85#ibcon#about to write, iclass 21, count 0 2006.201.02:12:55.85#ibcon#wrote, iclass 21, count 0 2006.201.02:12:55.85#ibcon#about to read 3, iclass 21, count 0 2006.201.02:12:55.87#ibcon#read 3, iclass 21, count 0 2006.201.02:12:55.87#ibcon#about to read 4, iclass 21, count 0 2006.201.02:12:55.87#ibcon#read 4, iclass 21, count 0 2006.201.02:12:55.87#ibcon#about to read 5, iclass 21, count 0 2006.201.02:12:55.87#ibcon#read 5, iclass 21, count 0 2006.201.02:12:55.87#ibcon#about to read 6, iclass 21, count 0 2006.201.02:12:55.87#ibcon#read 6, iclass 21, count 0 2006.201.02:12:55.87#ibcon#end of sib2, iclass 21, count 0 2006.201.02:12:55.87#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:12:55.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:12:55.87#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:12:55.87#ibcon#*before write, iclass 21, count 0 2006.201.02:12:55.87#ibcon#enter sib2, iclass 21, count 0 2006.201.02:12:55.87#ibcon#flushed, iclass 21, count 0 2006.201.02:12:55.87#ibcon#about to write, iclass 21, count 0 2006.201.02:12:55.87#ibcon#wrote, iclass 21, count 0 2006.201.02:12:55.87#ibcon#about to read 3, iclass 21, count 0 2006.201.02:12:55.91#ibcon#read 3, iclass 21, count 0 2006.201.02:12:55.91#ibcon#about to read 4, iclass 21, count 0 2006.201.02:12:55.91#ibcon#read 4, iclass 21, count 0 2006.201.02:12:55.91#ibcon#about to read 5, iclass 21, count 0 2006.201.02:12:55.91#ibcon#read 5, iclass 21, count 0 2006.201.02:12:55.91#ibcon#about to read 6, iclass 21, count 0 2006.201.02:12:55.91#ibcon#read 6, iclass 21, count 0 2006.201.02:12:55.91#ibcon#end of sib2, iclass 21, count 0 2006.201.02:12:55.91#ibcon#*after write, iclass 21, count 0 2006.201.02:12:55.91#ibcon#*before return 0, iclass 21, count 0 2006.201.02:12:55.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:55.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:55.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:12:55.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:12:55.91$vck44/va=5,4 2006.201.02:12:55.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.02:12:55.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.02:12:55.91#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:55.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:55.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:55.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:55.97#ibcon#enter wrdev, iclass 23, count 2 2006.201.02:12:55.97#ibcon#first serial, iclass 23, count 2 2006.201.02:12:55.97#ibcon#enter sib2, iclass 23, count 2 2006.201.02:12:55.97#ibcon#flushed, iclass 23, count 2 2006.201.02:12:55.97#ibcon#about to write, iclass 23, count 2 2006.201.02:12:55.97#ibcon#wrote, iclass 23, count 2 2006.201.02:12:55.97#ibcon#about to read 3, iclass 23, count 2 2006.201.02:12:55.99#ibcon#read 3, iclass 23, count 2 2006.201.02:12:55.99#ibcon#about to read 4, iclass 23, count 2 2006.201.02:12:55.99#ibcon#read 4, iclass 23, count 2 2006.201.02:12:55.99#ibcon#about to read 5, iclass 23, count 2 2006.201.02:12:55.99#ibcon#read 5, iclass 23, count 2 2006.201.02:12:55.99#ibcon#about to read 6, iclass 23, count 2 2006.201.02:12:55.99#ibcon#read 6, iclass 23, count 2 2006.201.02:12:55.99#ibcon#end of sib2, iclass 23, count 2 2006.201.02:12:55.99#ibcon#*mode == 0, iclass 23, count 2 2006.201.02:12:55.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.02:12:55.99#ibcon#[25=AT05-04\r\n] 2006.201.02:12:55.99#ibcon#*before write, iclass 23, count 2 2006.201.02:12:55.99#ibcon#enter sib2, iclass 23, count 2 2006.201.02:12:55.99#ibcon#flushed, iclass 23, count 2 2006.201.02:12:55.99#ibcon#about to write, iclass 23, count 2 2006.201.02:12:55.99#ibcon#wrote, iclass 23, count 2 2006.201.02:12:55.99#ibcon#about to read 3, iclass 23, count 2 2006.201.02:12:56.02#ibcon#read 3, iclass 23, count 2 2006.201.02:12:56.02#ibcon#about to read 4, iclass 23, count 2 2006.201.02:12:56.02#ibcon#read 4, iclass 23, count 2 2006.201.02:12:56.02#ibcon#about to read 5, iclass 23, count 2 2006.201.02:12:56.02#ibcon#read 5, iclass 23, count 2 2006.201.02:12:56.02#ibcon#about to read 6, iclass 23, count 2 2006.201.02:12:56.02#ibcon#read 6, iclass 23, count 2 2006.201.02:12:56.02#ibcon#end of sib2, iclass 23, count 2 2006.201.02:12:56.02#ibcon#*after write, iclass 23, count 2 2006.201.02:12:56.02#ibcon#*before return 0, iclass 23, count 2 2006.201.02:12:56.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:56.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:56.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.02:12:56.02#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:56.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:56.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:56.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:56.14#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:12:56.14#ibcon#first serial, iclass 23, count 0 2006.201.02:12:56.14#ibcon#enter sib2, iclass 23, count 0 2006.201.02:12:56.14#ibcon#flushed, iclass 23, count 0 2006.201.02:12:56.14#ibcon#about to write, iclass 23, count 0 2006.201.02:12:56.14#ibcon#wrote, iclass 23, count 0 2006.201.02:12:56.14#ibcon#about to read 3, iclass 23, count 0 2006.201.02:12:56.16#ibcon#read 3, iclass 23, count 0 2006.201.02:12:56.16#ibcon#about to read 4, iclass 23, count 0 2006.201.02:12:56.16#ibcon#read 4, iclass 23, count 0 2006.201.02:12:56.16#ibcon#about to read 5, iclass 23, count 0 2006.201.02:12:56.16#ibcon#read 5, iclass 23, count 0 2006.201.02:12:56.16#ibcon#about to read 6, iclass 23, count 0 2006.201.02:12:56.16#ibcon#read 6, iclass 23, count 0 2006.201.02:12:56.16#ibcon#end of sib2, iclass 23, count 0 2006.201.02:12:56.16#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:12:56.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:12:56.16#ibcon#[25=USB\r\n] 2006.201.02:12:56.16#ibcon#*before write, iclass 23, count 0 2006.201.02:12:56.16#ibcon#enter sib2, iclass 23, count 0 2006.201.02:12:56.16#ibcon#flushed, iclass 23, count 0 2006.201.02:12:56.16#ibcon#about to write, iclass 23, count 0 2006.201.02:12:56.16#ibcon#wrote, iclass 23, count 0 2006.201.02:12:56.16#ibcon#about to read 3, iclass 23, count 0 2006.201.02:12:56.19#ibcon#read 3, iclass 23, count 0 2006.201.02:12:56.19#ibcon#about to read 4, iclass 23, count 0 2006.201.02:12:56.19#ibcon#read 4, iclass 23, count 0 2006.201.02:12:56.19#ibcon#about to read 5, iclass 23, count 0 2006.201.02:12:56.19#ibcon#read 5, iclass 23, count 0 2006.201.02:12:56.19#ibcon#about to read 6, iclass 23, count 0 2006.201.02:12:56.19#ibcon#read 6, iclass 23, count 0 2006.201.02:12:56.19#ibcon#end of sib2, iclass 23, count 0 2006.201.02:12:56.19#ibcon#*after write, iclass 23, count 0 2006.201.02:12:56.19#ibcon#*before return 0, iclass 23, count 0 2006.201.02:12:56.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:56.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:56.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:12:56.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:12:56.19$vck44/valo=6,814.99 2006.201.02:12:56.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.02:12:56.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.02:12:56.19#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:56.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:56.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:56.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:56.19#ibcon#enter wrdev, iclass 25, count 0 2006.201.02:12:56.19#ibcon#first serial, iclass 25, count 0 2006.201.02:12:56.19#ibcon#enter sib2, iclass 25, count 0 2006.201.02:12:56.19#ibcon#flushed, iclass 25, count 0 2006.201.02:12:56.19#ibcon#about to write, iclass 25, count 0 2006.201.02:12:56.19#ibcon#wrote, iclass 25, count 0 2006.201.02:12:56.19#ibcon#about to read 3, iclass 25, count 0 2006.201.02:12:56.21#ibcon#read 3, iclass 25, count 0 2006.201.02:12:56.21#ibcon#about to read 4, iclass 25, count 0 2006.201.02:12:56.21#ibcon#read 4, iclass 25, count 0 2006.201.02:12:56.21#ibcon#about to read 5, iclass 25, count 0 2006.201.02:12:56.21#ibcon#read 5, iclass 25, count 0 2006.201.02:12:56.21#ibcon#about to read 6, iclass 25, count 0 2006.201.02:12:56.21#ibcon#read 6, iclass 25, count 0 2006.201.02:12:56.21#ibcon#end of sib2, iclass 25, count 0 2006.201.02:12:56.21#ibcon#*mode == 0, iclass 25, count 0 2006.201.02:12:56.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.02:12:56.21#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:12:56.21#ibcon#*before write, iclass 25, count 0 2006.201.02:12:56.21#ibcon#enter sib2, iclass 25, count 0 2006.201.02:12:56.21#ibcon#flushed, iclass 25, count 0 2006.201.02:12:56.21#ibcon#about to write, iclass 25, count 0 2006.201.02:12:56.21#ibcon#wrote, iclass 25, count 0 2006.201.02:12:56.21#ibcon#about to read 3, iclass 25, count 0 2006.201.02:12:56.26#ibcon#read 3, iclass 25, count 0 2006.201.02:12:56.26#ibcon#about to read 4, iclass 25, count 0 2006.201.02:12:56.26#ibcon#read 4, iclass 25, count 0 2006.201.02:12:56.26#ibcon#about to read 5, iclass 25, count 0 2006.201.02:12:56.26#ibcon#read 5, iclass 25, count 0 2006.201.02:12:56.26#ibcon#about to read 6, iclass 25, count 0 2006.201.02:12:56.26#ibcon#read 6, iclass 25, count 0 2006.201.02:12:56.26#ibcon#end of sib2, iclass 25, count 0 2006.201.02:12:56.26#ibcon#*after write, iclass 25, count 0 2006.201.02:12:56.26#ibcon#*before return 0, iclass 25, count 0 2006.201.02:12:56.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:56.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:56.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.02:12:56.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.02:12:56.26$vck44/va=6,5 2006.201.02:12:56.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.02:12:56.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.02:12:56.26#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:56.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:56.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:56.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:56.31#ibcon#enter wrdev, iclass 27, count 2 2006.201.02:12:56.31#ibcon#first serial, iclass 27, count 2 2006.201.02:12:56.31#ibcon#enter sib2, iclass 27, count 2 2006.201.02:12:56.31#ibcon#flushed, iclass 27, count 2 2006.201.02:12:56.31#ibcon#about to write, iclass 27, count 2 2006.201.02:12:56.31#ibcon#wrote, iclass 27, count 2 2006.201.02:12:56.31#ibcon#about to read 3, iclass 27, count 2 2006.201.02:12:56.33#ibcon#read 3, iclass 27, count 2 2006.201.02:12:56.33#ibcon#about to read 4, iclass 27, count 2 2006.201.02:12:56.33#ibcon#read 4, iclass 27, count 2 2006.201.02:12:56.33#ibcon#about to read 5, iclass 27, count 2 2006.201.02:12:56.33#ibcon#read 5, iclass 27, count 2 2006.201.02:12:56.33#ibcon#about to read 6, iclass 27, count 2 2006.201.02:12:56.33#ibcon#read 6, iclass 27, count 2 2006.201.02:12:56.33#ibcon#end of sib2, iclass 27, count 2 2006.201.02:12:56.33#ibcon#*mode == 0, iclass 27, count 2 2006.201.02:12:56.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.02:12:56.33#ibcon#[25=AT06-05\r\n] 2006.201.02:12:56.33#ibcon#*before write, iclass 27, count 2 2006.201.02:12:56.33#ibcon#enter sib2, iclass 27, count 2 2006.201.02:12:56.33#ibcon#flushed, iclass 27, count 2 2006.201.02:12:56.33#ibcon#about to write, iclass 27, count 2 2006.201.02:12:56.33#ibcon#wrote, iclass 27, count 2 2006.201.02:12:56.33#ibcon#about to read 3, iclass 27, count 2 2006.201.02:12:56.36#ibcon#read 3, iclass 27, count 2 2006.201.02:12:56.36#ibcon#about to read 4, iclass 27, count 2 2006.201.02:12:56.36#ibcon#read 4, iclass 27, count 2 2006.201.02:12:56.36#ibcon#about to read 5, iclass 27, count 2 2006.201.02:12:56.36#ibcon#read 5, iclass 27, count 2 2006.201.02:12:56.36#ibcon#about to read 6, iclass 27, count 2 2006.201.02:12:56.36#ibcon#read 6, iclass 27, count 2 2006.201.02:12:56.36#ibcon#end of sib2, iclass 27, count 2 2006.201.02:12:56.36#ibcon#*after write, iclass 27, count 2 2006.201.02:12:56.36#ibcon#*before return 0, iclass 27, count 2 2006.201.02:12:56.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:56.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:56.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.02:12:56.36#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:56.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:56.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:56.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:56.48#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:12:56.48#ibcon#first serial, iclass 27, count 0 2006.201.02:12:56.48#ibcon#enter sib2, iclass 27, count 0 2006.201.02:12:56.48#ibcon#flushed, iclass 27, count 0 2006.201.02:12:56.48#ibcon#about to write, iclass 27, count 0 2006.201.02:12:56.48#ibcon#wrote, iclass 27, count 0 2006.201.02:12:56.48#ibcon#about to read 3, iclass 27, count 0 2006.201.02:12:56.50#ibcon#read 3, iclass 27, count 0 2006.201.02:12:56.50#ibcon#about to read 4, iclass 27, count 0 2006.201.02:12:56.50#ibcon#read 4, iclass 27, count 0 2006.201.02:12:56.50#ibcon#about to read 5, iclass 27, count 0 2006.201.02:12:56.50#ibcon#read 5, iclass 27, count 0 2006.201.02:12:56.50#ibcon#about to read 6, iclass 27, count 0 2006.201.02:12:56.50#ibcon#read 6, iclass 27, count 0 2006.201.02:12:56.50#ibcon#end of sib2, iclass 27, count 0 2006.201.02:12:56.50#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:12:56.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:12:56.50#ibcon#[25=USB\r\n] 2006.201.02:12:56.50#ibcon#*before write, iclass 27, count 0 2006.201.02:12:56.50#ibcon#enter sib2, iclass 27, count 0 2006.201.02:12:56.50#ibcon#flushed, iclass 27, count 0 2006.201.02:12:56.50#ibcon#about to write, iclass 27, count 0 2006.201.02:12:56.50#ibcon#wrote, iclass 27, count 0 2006.201.02:12:56.50#ibcon#about to read 3, iclass 27, count 0 2006.201.02:12:56.53#ibcon#read 3, iclass 27, count 0 2006.201.02:12:56.53#ibcon#about to read 4, iclass 27, count 0 2006.201.02:12:56.53#ibcon#read 4, iclass 27, count 0 2006.201.02:12:56.53#ibcon#about to read 5, iclass 27, count 0 2006.201.02:12:56.53#ibcon#read 5, iclass 27, count 0 2006.201.02:12:56.53#ibcon#about to read 6, iclass 27, count 0 2006.201.02:12:56.53#ibcon#read 6, iclass 27, count 0 2006.201.02:12:56.53#ibcon#end of sib2, iclass 27, count 0 2006.201.02:12:56.53#ibcon#*after write, iclass 27, count 0 2006.201.02:12:56.53#ibcon#*before return 0, iclass 27, count 0 2006.201.02:12:56.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:56.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:56.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:12:56.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:12:56.53$vck44/valo=7,864.99 2006.201.02:12:56.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.02:12:56.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.02:12:56.53#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:56.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:56.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:56.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:56.53#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:12:56.53#ibcon#first serial, iclass 29, count 0 2006.201.02:12:56.53#ibcon#enter sib2, iclass 29, count 0 2006.201.02:12:56.53#ibcon#flushed, iclass 29, count 0 2006.201.02:12:56.53#ibcon#about to write, iclass 29, count 0 2006.201.02:12:56.53#ibcon#wrote, iclass 29, count 0 2006.201.02:12:56.53#ibcon#about to read 3, iclass 29, count 0 2006.201.02:12:56.55#ibcon#read 3, iclass 29, count 0 2006.201.02:12:56.55#ibcon#about to read 4, iclass 29, count 0 2006.201.02:12:56.55#ibcon#read 4, iclass 29, count 0 2006.201.02:12:56.55#ibcon#about to read 5, iclass 29, count 0 2006.201.02:12:56.55#ibcon#read 5, iclass 29, count 0 2006.201.02:12:56.55#ibcon#about to read 6, iclass 29, count 0 2006.201.02:12:56.55#ibcon#read 6, iclass 29, count 0 2006.201.02:12:56.55#ibcon#end of sib2, iclass 29, count 0 2006.201.02:12:56.55#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:12:56.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:12:56.55#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:12:56.55#ibcon#*before write, iclass 29, count 0 2006.201.02:12:56.55#ibcon#enter sib2, iclass 29, count 0 2006.201.02:12:56.55#ibcon#flushed, iclass 29, count 0 2006.201.02:12:56.55#ibcon#about to write, iclass 29, count 0 2006.201.02:12:56.55#ibcon#wrote, iclass 29, count 0 2006.201.02:12:56.55#ibcon#about to read 3, iclass 29, count 0 2006.201.02:12:56.59#ibcon#read 3, iclass 29, count 0 2006.201.02:12:56.59#ibcon#about to read 4, iclass 29, count 0 2006.201.02:12:56.59#ibcon#read 4, iclass 29, count 0 2006.201.02:12:56.59#ibcon#about to read 5, iclass 29, count 0 2006.201.02:12:56.59#ibcon#read 5, iclass 29, count 0 2006.201.02:12:56.59#ibcon#about to read 6, iclass 29, count 0 2006.201.02:12:56.59#ibcon#read 6, iclass 29, count 0 2006.201.02:12:56.59#ibcon#end of sib2, iclass 29, count 0 2006.201.02:12:56.59#ibcon#*after write, iclass 29, count 0 2006.201.02:12:56.59#ibcon#*before return 0, iclass 29, count 0 2006.201.02:12:56.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:56.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:56.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:12:56.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:12:56.59$vck44/va=7,5 2006.201.02:12:56.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.02:12:56.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.02:12:56.59#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:56.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:56.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:56.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:56.65#ibcon#enter wrdev, iclass 31, count 2 2006.201.02:12:56.65#ibcon#first serial, iclass 31, count 2 2006.201.02:12:56.65#ibcon#enter sib2, iclass 31, count 2 2006.201.02:12:56.65#ibcon#flushed, iclass 31, count 2 2006.201.02:12:56.65#ibcon#about to write, iclass 31, count 2 2006.201.02:12:56.65#ibcon#wrote, iclass 31, count 2 2006.201.02:12:56.65#ibcon#about to read 3, iclass 31, count 2 2006.201.02:12:56.67#ibcon#read 3, iclass 31, count 2 2006.201.02:12:56.67#ibcon#about to read 4, iclass 31, count 2 2006.201.02:12:56.67#ibcon#read 4, iclass 31, count 2 2006.201.02:12:56.67#ibcon#about to read 5, iclass 31, count 2 2006.201.02:12:56.67#ibcon#read 5, iclass 31, count 2 2006.201.02:12:56.67#ibcon#about to read 6, iclass 31, count 2 2006.201.02:12:56.67#ibcon#read 6, iclass 31, count 2 2006.201.02:12:56.67#ibcon#end of sib2, iclass 31, count 2 2006.201.02:12:56.67#ibcon#*mode == 0, iclass 31, count 2 2006.201.02:12:56.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.02:12:56.67#ibcon#[25=AT07-05\r\n] 2006.201.02:12:56.67#ibcon#*before write, iclass 31, count 2 2006.201.02:12:56.67#ibcon#enter sib2, iclass 31, count 2 2006.201.02:12:56.67#ibcon#flushed, iclass 31, count 2 2006.201.02:12:56.67#ibcon#about to write, iclass 31, count 2 2006.201.02:12:56.67#ibcon#wrote, iclass 31, count 2 2006.201.02:12:56.67#ibcon#about to read 3, iclass 31, count 2 2006.201.02:12:56.70#ibcon#read 3, iclass 31, count 2 2006.201.02:12:56.70#ibcon#about to read 4, iclass 31, count 2 2006.201.02:12:56.70#ibcon#read 4, iclass 31, count 2 2006.201.02:12:56.70#ibcon#about to read 5, iclass 31, count 2 2006.201.02:12:56.70#ibcon#read 5, iclass 31, count 2 2006.201.02:12:56.70#ibcon#about to read 6, iclass 31, count 2 2006.201.02:12:56.70#ibcon#read 6, iclass 31, count 2 2006.201.02:12:56.70#ibcon#end of sib2, iclass 31, count 2 2006.201.02:12:56.70#ibcon#*after write, iclass 31, count 2 2006.201.02:12:56.70#ibcon#*before return 0, iclass 31, count 2 2006.201.02:12:56.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:56.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:56.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.02:12:56.70#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:56.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:56.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:56.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:56.82#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:12:56.82#ibcon#first serial, iclass 31, count 0 2006.201.02:12:56.82#ibcon#enter sib2, iclass 31, count 0 2006.201.02:12:56.82#ibcon#flushed, iclass 31, count 0 2006.201.02:12:56.82#ibcon#about to write, iclass 31, count 0 2006.201.02:12:56.82#ibcon#wrote, iclass 31, count 0 2006.201.02:12:56.82#ibcon#about to read 3, iclass 31, count 0 2006.201.02:12:56.84#ibcon#read 3, iclass 31, count 0 2006.201.02:12:56.84#ibcon#about to read 4, iclass 31, count 0 2006.201.02:12:56.84#ibcon#read 4, iclass 31, count 0 2006.201.02:12:56.84#ibcon#about to read 5, iclass 31, count 0 2006.201.02:12:56.84#ibcon#read 5, iclass 31, count 0 2006.201.02:12:56.84#ibcon#about to read 6, iclass 31, count 0 2006.201.02:12:56.84#ibcon#read 6, iclass 31, count 0 2006.201.02:12:56.84#ibcon#end of sib2, iclass 31, count 0 2006.201.02:12:56.84#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:12:56.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:12:56.84#ibcon#[25=USB\r\n] 2006.201.02:12:56.84#ibcon#*before write, iclass 31, count 0 2006.201.02:12:56.84#ibcon#enter sib2, iclass 31, count 0 2006.201.02:12:56.84#ibcon#flushed, iclass 31, count 0 2006.201.02:12:56.84#ibcon#about to write, iclass 31, count 0 2006.201.02:12:56.84#ibcon#wrote, iclass 31, count 0 2006.201.02:12:56.84#ibcon#about to read 3, iclass 31, count 0 2006.201.02:12:56.87#ibcon#read 3, iclass 31, count 0 2006.201.02:12:56.87#ibcon#about to read 4, iclass 31, count 0 2006.201.02:12:56.87#ibcon#read 4, iclass 31, count 0 2006.201.02:12:56.87#ibcon#about to read 5, iclass 31, count 0 2006.201.02:12:56.87#ibcon#read 5, iclass 31, count 0 2006.201.02:12:56.87#ibcon#about to read 6, iclass 31, count 0 2006.201.02:12:56.87#ibcon#read 6, iclass 31, count 0 2006.201.02:12:56.87#ibcon#end of sib2, iclass 31, count 0 2006.201.02:12:56.87#ibcon#*after write, iclass 31, count 0 2006.201.02:12:56.87#ibcon#*before return 0, iclass 31, count 0 2006.201.02:12:56.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:56.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:56.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:12:56.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:12:56.87$vck44/valo=8,884.99 2006.201.02:12:56.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.02:12:56.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.02:12:56.87#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:56.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:56.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:56.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:56.87#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:12:56.87#ibcon#first serial, iclass 33, count 0 2006.201.02:12:56.87#ibcon#enter sib2, iclass 33, count 0 2006.201.02:12:56.87#ibcon#flushed, iclass 33, count 0 2006.201.02:12:56.87#ibcon#about to write, iclass 33, count 0 2006.201.02:12:56.87#ibcon#wrote, iclass 33, count 0 2006.201.02:12:56.87#ibcon#about to read 3, iclass 33, count 0 2006.201.02:12:56.89#ibcon#read 3, iclass 33, count 0 2006.201.02:12:56.89#ibcon#about to read 4, iclass 33, count 0 2006.201.02:12:56.89#ibcon#read 4, iclass 33, count 0 2006.201.02:12:56.89#ibcon#about to read 5, iclass 33, count 0 2006.201.02:12:56.89#ibcon#read 5, iclass 33, count 0 2006.201.02:12:56.89#ibcon#about to read 6, iclass 33, count 0 2006.201.02:12:56.89#ibcon#read 6, iclass 33, count 0 2006.201.02:12:56.89#ibcon#end of sib2, iclass 33, count 0 2006.201.02:12:56.89#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:12:56.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:12:56.89#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:12:56.89#ibcon#*before write, iclass 33, count 0 2006.201.02:12:56.89#ibcon#enter sib2, iclass 33, count 0 2006.201.02:12:56.89#ibcon#flushed, iclass 33, count 0 2006.201.02:12:56.89#ibcon#about to write, iclass 33, count 0 2006.201.02:12:56.89#ibcon#wrote, iclass 33, count 0 2006.201.02:12:56.89#ibcon#about to read 3, iclass 33, count 0 2006.201.02:12:56.93#ibcon#read 3, iclass 33, count 0 2006.201.02:12:56.93#ibcon#about to read 4, iclass 33, count 0 2006.201.02:12:56.93#ibcon#read 4, iclass 33, count 0 2006.201.02:12:56.93#ibcon#about to read 5, iclass 33, count 0 2006.201.02:12:56.93#ibcon#read 5, iclass 33, count 0 2006.201.02:12:56.93#ibcon#about to read 6, iclass 33, count 0 2006.201.02:12:56.93#ibcon#read 6, iclass 33, count 0 2006.201.02:12:56.93#ibcon#end of sib2, iclass 33, count 0 2006.201.02:12:56.93#ibcon#*after write, iclass 33, count 0 2006.201.02:12:56.93#ibcon#*before return 0, iclass 33, count 0 2006.201.02:12:56.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:56.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:56.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:12:56.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:12:56.93$vck44/va=8,4 2006.201.02:12:56.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.02:12:56.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.02:12:56.93#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:56.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:56.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:56.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:56.99#ibcon#enter wrdev, iclass 35, count 2 2006.201.02:12:56.99#ibcon#first serial, iclass 35, count 2 2006.201.02:12:56.99#ibcon#enter sib2, iclass 35, count 2 2006.201.02:12:56.99#ibcon#flushed, iclass 35, count 2 2006.201.02:12:56.99#ibcon#about to write, iclass 35, count 2 2006.201.02:12:56.99#ibcon#wrote, iclass 35, count 2 2006.201.02:12:56.99#ibcon#about to read 3, iclass 35, count 2 2006.201.02:12:57.01#ibcon#read 3, iclass 35, count 2 2006.201.02:12:57.01#ibcon#about to read 4, iclass 35, count 2 2006.201.02:12:57.01#ibcon#read 4, iclass 35, count 2 2006.201.02:12:57.01#ibcon#about to read 5, iclass 35, count 2 2006.201.02:12:57.01#ibcon#read 5, iclass 35, count 2 2006.201.02:12:57.01#ibcon#about to read 6, iclass 35, count 2 2006.201.02:12:57.01#ibcon#read 6, iclass 35, count 2 2006.201.02:12:57.01#ibcon#end of sib2, iclass 35, count 2 2006.201.02:12:57.01#ibcon#*mode == 0, iclass 35, count 2 2006.201.02:12:57.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.02:12:57.01#ibcon#[25=AT08-04\r\n] 2006.201.02:12:57.01#ibcon#*before write, iclass 35, count 2 2006.201.02:12:57.01#ibcon#enter sib2, iclass 35, count 2 2006.201.02:12:57.01#ibcon#flushed, iclass 35, count 2 2006.201.02:12:57.01#ibcon#about to write, iclass 35, count 2 2006.201.02:12:57.01#ibcon#wrote, iclass 35, count 2 2006.201.02:12:57.01#ibcon#about to read 3, iclass 35, count 2 2006.201.02:12:57.02#abcon#<5=/04 3.1 5.8 22.91 911005.3\r\n> 2006.201.02:12:57.04#abcon#{5=INTERFACE CLEAR} 2006.201.02:12:57.04#ibcon#read 3, iclass 35, count 2 2006.201.02:12:57.04#ibcon#about to read 4, iclass 35, count 2 2006.201.02:12:57.04#ibcon#read 4, iclass 35, count 2 2006.201.02:12:57.04#ibcon#about to read 5, iclass 35, count 2 2006.201.02:12:57.04#ibcon#read 5, iclass 35, count 2 2006.201.02:12:57.04#ibcon#about to read 6, iclass 35, count 2 2006.201.02:12:57.04#ibcon#read 6, iclass 35, count 2 2006.201.02:12:57.04#ibcon#end of sib2, iclass 35, count 2 2006.201.02:12:57.04#ibcon#*after write, iclass 35, count 2 2006.201.02:12:57.04#ibcon#*before return 0, iclass 35, count 2 2006.201.02:12:57.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:57.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:57.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.02:12:57.04#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:57.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:57.10#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:12:57.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:57.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:57.16#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:12:57.16#ibcon#first serial, iclass 35, count 0 2006.201.02:12:57.16#ibcon#enter sib2, iclass 35, count 0 2006.201.02:12:57.16#ibcon#flushed, iclass 35, count 0 2006.201.02:12:57.16#ibcon#about to write, iclass 35, count 0 2006.201.02:12:57.16#ibcon#wrote, iclass 35, count 0 2006.201.02:12:57.16#ibcon#about to read 3, iclass 35, count 0 2006.201.02:12:57.19#ibcon#read 3, iclass 35, count 0 2006.201.02:12:57.19#ibcon#about to read 4, iclass 35, count 0 2006.201.02:12:57.19#ibcon#read 4, iclass 35, count 0 2006.201.02:12:57.19#ibcon#about to read 5, iclass 35, count 0 2006.201.02:12:57.19#ibcon#read 5, iclass 35, count 0 2006.201.02:12:57.19#ibcon#about to read 6, iclass 35, count 0 2006.201.02:12:57.19#ibcon#read 6, iclass 35, count 0 2006.201.02:12:57.19#ibcon#end of sib2, iclass 35, count 0 2006.201.02:12:57.19#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:12:57.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:12:57.19#ibcon#[25=USB\r\n] 2006.201.02:12:57.19#ibcon#*before write, iclass 35, count 0 2006.201.02:12:57.19#ibcon#enter sib2, iclass 35, count 0 2006.201.02:12:57.19#ibcon#flushed, iclass 35, count 0 2006.201.02:12:57.19#ibcon#about to write, iclass 35, count 0 2006.201.02:12:57.19#ibcon#wrote, iclass 35, count 0 2006.201.02:12:57.19#ibcon#about to read 3, iclass 35, count 0 2006.201.02:12:57.22#ibcon#read 3, iclass 35, count 0 2006.201.02:12:57.22#ibcon#about to read 4, iclass 35, count 0 2006.201.02:12:57.22#ibcon#read 4, iclass 35, count 0 2006.201.02:12:57.22#ibcon#about to read 5, iclass 35, count 0 2006.201.02:12:57.22#ibcon#read 5, iclass 35, count 0 2006.201.02:12:57.22#ibcon#about to read 6, iclass 35, count 0 2006.201.02:12:57.22#ibcon#read 6, iclass 35, count 0 2006.201.02:12:57.22#ibcon#end of sib2, iclass 35, count 0 2006.201.02:12:57.22#ibcon#*after write, iclass 35, count 0 2006.201.02:12:57.22#ibcon#*before return 0, iclass 35, count 0 2006.201.02:12:57.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:57.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:57.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:12:57.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:12:57.22$vck44/vblo=1,629.99 2006.201.02:12:57.22#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.02:12:57.22#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.02:12:57.22#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:57.22#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:57.22#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:57.22#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:57.22#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:12:57.22#ibcon#first serial, iclass 2, count 0 2006.201.02:12:57.22#ibcon#enter sib2, iclass 2, count 0 2006.201.02:12:57.22#ibcon#flushed, iclass 2, count 0 2006.201.02:12:57.22#ibcon#about to write, iclass 2, count 0 2006.201.02:12:57.22#ibcon#wrote, iclass 2, count 0 2006.201.02:12:57.22#ibcon#about to read 3, iclass 2, count 0 2006.201.02:12:57.24#ibcon#read 3, iclass 2, count 0 2006.201.02:12:57.24#ibcon#about to read 4, iclass 2, count 0 2006.201.02:12:57.24#ibcon#read 4, iclass 2, count 0 2006.201.02:12:57.24#ibcon#about to read 5, iclass 2, count 0 2006.201.02:12:57.24#ibcon#read 5, iclass 2, count 0 2006.201.02:12:57.24#ibcon#about to read 6, iclass 2, count 0 2006.201.02:12:57.24#ibcon#read 6, iclass 2, count 0 2006.201.02:12:57.24#ibcon#end of sib2, iclass 2, count 0 2006.201.02:12:57.24#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:12:57.24#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:12:57.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:12:57.24#ibcon#*before write, iclass 2, count 0 2006.201.02:12:57.24#ibcon#enter sib2, iclass 2, count 0 2006.201.02:12:57.24#ibcon#flushed, iclass 2, count 0 2006.201.02:12:57.24#ibcon#about to write, iclass 2, count 0 2006.201.02:12:57.24#ibcon#wrote, iclass 2, count 0 2006.201.02:12:57.24#ibcon#about to read 3, iclass 2, count 0 2006.201.02:12:57.28#ibcon#read 3, iclass 2, count 0 2006.201.02:12:57.28#ibcon#about to read 4, iclass 2, count 0 2006.201.02:12:57.28#ibcon#read 4, iclass 2, count 0 2006.201.02:12:57.28#ibcon#about to read 5, iclass 2, count 0 2006.201.02:12:57.28#ibcon#read 5, iclass 2, count 0 2006.201.02:12:57.28#ibcon#about to read 6, iclass 2, count 0 2006.201.02:12:57.28#ibcon#read 6, iclass 2, count 0 2006.201.02:12:57.28#ibcon#end of sib2, iclass 2, count 0 2006.201.02:12:57.28#ibcon#*after write, iclass 2, count 0 2006.201.02:12:57.28#ibcon#*before return 0, iclass 2, count 0 2006.201.02:12:57.28#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:57.28#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:12:57.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:12:57.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:12:57.28$vck44/vb=1,4 2006.201.02:12:57.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.02:12:57.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.02:12:57.28#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:57.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:57.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:57.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:57.28#ibcon#enter wrdev, iclass 5, count 2 2006.201.02:12:57.28#ibcon#first serial, iclass 5, count 2 2006.201.02:12:57.28#ibcon#enter sib2, iclass 5, count 2 2006.201.02:12:57.28#ibcon#flushed, iclass 5, count 2 2006.201.02:12:57.28#ibcon#about to write, iclass 5, count 2 2006.201.02:12:57.28#ibcon#wrote, iclass 5, count 2 2006.201.02:12:57.28#ibcon#about to read 3, iclass 5, count 2 2006.201.02:12:57.30#ibcon#read 3, iclass 5, count 2 2006.201.02:12:57.30#ibcon#about to read 4, iclass 5, count 2 2006.201.02:12:57.30#ibcon#read 4, iclass 5, count 2 2006.201.02:12:57.30#ibcon#about to read 5, iclass 5, count 2 2006.201.02:12:57.30#ibcon#read 5, iclass 5, count 2 2006.201.02:12:57.30#ibcon#about to read 6, iclass 5, count 2 2006.201.02:12:57.30#ibcon#read 6, iclass 5, count 2 2006.201.02:12:57.30#ibcon#end of sib2, iclass 5, count 2 2006.201.02:12:57.30#ibcon#*mode == 0, iclass 5, count 2 2006.201.02:12:57.30#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.02:12:57.30#ibcon#[27=AT01-04\r\n] 2006.201.02:12:57.30#ibcon#*before write, iclass 5, count 2 2006.201.02:12:57.30#ibcon#enter sib2, iclass 5, count 2 2006.201.02:12:57.30#ibcon#flushed, iclass 5, count 2 2006.201.02:12:57.30#ibcon#about to write, iclass 5, count 2 2006.201.02:12:57.30#ibcon#wrote, iclass 5, count 2 2006.201.02:12:57.30#ibcon#about to read 3, iclass 5, count 2 2006.201.02:12:57.33#ibcon#read 3, iclass 5, count 2 2006.201.02:12:57.33#ibcon#about to read 4, iclass 5, count 2 2006.201.02:12:57.33#ibcon#read 4, iclass 5, count 2 2006.201.02:12:57.33#ibcon#about to read 5, iclass 5, count 2 2006.201.02:12:57.33#ibcon#read 5, iclass 5, count 2 2006.201.02:12:57.33#ibcon#about to read 6, iclass 5, count 2 2006.201.02:12:57.33#ibcon#read 6, iclass 5, count 2 2006.201.02:12:57.33#ibcon#end of sib2, iclass 5, count 2 2006.201.02:12:57.33#ibcon#*after write, iclass 5, count 2 2006.201.02:12:57.33#ibcon#*before return 0, iclass 5, count 2 2006.201.02:12:57.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:57.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:12:57.33#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.02:12:57.33#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:57.33#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:57.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:57.45#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:57.45#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:12:57.45#ibcon#first serial, iclass 5, count 0 2006.201.02:12:57.45#ibcon#enter sib2, iclass 5, count 0 2006.201.02:12:57.45#ibcon#flushed, iclass 5, count 0 2006.201.02:12:57.45#ibcon#about to write, iclass 5, count 0 2006.201.02:12:57.45#ibcon#wrote, iclass 5, count 0 2006.201.02:12:57.45#ibcon#about to read 3, iclass 5, count 0 2006.201.02:12:57.47#ibcon#read 3, iclass 5, count 0 2006.201.02:12:57.47#ibcon#about to read 4, iclass 5, count 0 2006.201.02:12:57.47#ibcon#read 4, iclass 5, count 0 2006.201.02:12:57.47#ibcon#about to read 5, iclass 5, count 0 2006.201.02:12:57.47#ibcon#read 5, iclass 5, count 0 2006.201.02:12:57.47#ibcon#about to read 6, iclass 5, count 0 2006.201.02:12:57.47#ibcon#read 6, iclass 5, count 0 2006.201.02:12:57.47#ibcon#end of sib2, iclass 5, count 0 2006.201.02:12:57.47#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:12:57.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:12:57.47#ibcon#[27=USB\r\n] 2006.201.02:12:57.47#ibcon#*before write, iclass 5, count 0 2006.201.02:12:57.47#ibcon#enter sib2, iclass 5, count 0 2006.201.02:12:57.47#ibcon#flushed, iclass 5, count 0 2006.201.02:12:57.47#ibcon#about to write, iclass 5, count 0 2006.201.02:12:57.47#ibcon#wrote, iclass 5, count 0 2006.201.02:12:57.47#ibcon#about to read 3, iclass 5, count 0 2006.201.02:12:57.50#ibcon#read 3, iclass 5, count 0 2006.201.02:12:57.50#ibcon#about to read 4, iclass 5, count 0 2006.201.02:12:57.50#ibcon#read 4, iclass 5, count 0 2006.201.02:12:57.50#ibcon#about to read 5, iclass 5, count 0 2006.201.02:12:57.50#ibcon#read 5, iclass 5, count 0 2006.201.02:12:57.50#ibcon#about to read 6, iclass 5, count 0 2006.201.02:12:57.50#ibcon#read 6, iclass 5, count 0 2006.201.02:12:57.50#ibcon#end of sib2, iclass 5, count 0 2006.201.02:12:57.50#ibcon#*after write, iclass 5, count 0 2006.201.02:12:57.50#ibcon#*before return 0, iclass 5, count 0 2006.201.02:12:57.50#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:57.50#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:12:57.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:12:57.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:12:57.50$vck44/vblo=2,634.99 2006.201.02:12:57.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.02:12:57.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.02:12:57.50#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:57.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:57.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:57.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:57.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.02:12:57.50#ibcon#first serial, iclass 7, count 0 2006.201.02:12:57.50#ibcon#enter sib2, iclass 7, count 0 2006.201.02:12:57.50#ibcon#flushed, iclass 7, count 0 2006.201.02:12:57.50#ibcon#about to write, iclass 7, count 0 2006.201.02:12:57.50#ibcon#wrote, iclass 7, count 0 2006.201.02:12:57.50#ibcon#about to read 3, iclass 7, count 0 2006.201.02:12:57.52#ibcon#read 3, iclass 7, count 0 2006.201.02:12:57.52#ibcon#about to read 4, iclass 7, count 0 2006.201.02:12:57.52#ibcon#read 4, iclass 7, count 0 2006.201.02:12:57.52#ibcon#about to read 5, iclass 7, count 0 2006.201.02:12:57.52#ibcon#read 5, iclass 7, count 0 2006.201.02:12:57.52#ibcon#about to read 6, iclass 7, count 0 2006.201.02:12:57.52#ibcon#read 6, iclass 7, count 0 2006.201.02:12:57.52#ibcon#end of sib2, iclass 7, count 0 2006.201.02:12:57.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.02:12:57.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.02:12:57.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:12:57.52#ibcon#*before write, iclass 7, count 0 2006.201.02:12:57.52#ibcon#enter sib2, iclass 7, count 0 2006.201.02:12:57.52#ibcon#flushed, iclass 7, count 0 2006.201.02:12:57.52#ibcon#about to write, iclass 7, count 0 2006.201.02:12:57.52#ibcon#wrote, iclass 7, count 0 2006.201.02:12:57.52#ibcon#about to read 3, iclass 7, count 0 2006.201.02:12:57.56#ibcon#read 3, iclass 7, count 0 2006.201.02:12:57.56#ibcon#about to read 4, iclass 7, count 0 2006.201.02:12:57.56#ibcon#read 4, iclass 7, count 0 2006.201.02:12:57.56#ibcon#about to read 5, iclass 7, count 0 2006.201.02:12:57.56#ibcon#read 5, iclass 7, count 0 2006.201.02:12:57.56#ibcon#about to read 6, iclass 7, count 0 2006.201.02:12:57.56#ibcon#read 6, iclass 7, count 0 2006.201.02:12:57.56#ibcon#end of sib2, iclass 7, count 0 2006.201.02:12:57.56#ibcon#*after write, iclass 7, count 0 2006.201.02:12:57.56#ibcon#*before return 0, iclass 7, count 0 2006.201.02:12:57.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:57.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:12:57.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.02:12:57.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.02:12:57.56$vck44/vb=2,5 2006.201.02:12:57.56#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.02:12:57.56#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.02:12:57.56#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:57.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:57.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:57.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:57.62#ibcon#enter wrdev, iclass 11, count 2 2006.201.02:12:57.62#ibcon#first serial, iclass 11, count 2 2006.201.02:12:57.62#ibcon#enter sib2, iclass 11, count 2 2006.201.02:12:57.62#ibcon#flushed, iclass 11, count 2 2006.201.02:12:57.62#ibcon#about to write, iclass 11, count 2 2006.201.02:12:57.62#ibcon#wrote, iclass 11, count 2 2006.201.02:12:57.62#ibcon#about to read 3, iclass 11, count 2 2006.201.02:12:57.64#ibcon#read 3, iclass 11, count 2 2006.201.02:12:57.64#ibcon#about to read 4, iclass 11, count 2 2006.201.02:12:57.64#ibcon#read 4, iclass 11, count 2 2006.201.02:12:57.64#ibcon#about to read 5, iclass 11, count 2 2006.201.02:12:57.64#ibcon#read 5, iclass 11, count 2 2006.201.02:12:57.64#ibcon#about to read 6, iclass 11, count 2 2006.201.02:12:57.64#ibcon#read 6, iclass 11, count 2 2006.201.02:12:57.64#ibcon#end of sib2, iclass 11, count 2 2006.201.02:12:57.64#ibcon#*mode == 0, iclass 11, count 2 2006.201.02:12:57.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.02:12:57.64#ibcon#[27=AT02-05\r\n] 2006.201.02:12:57.64#ibcon#*before write, iclass 11, count 2 2006.201.02:12:57.64#ibcon#enter sib2, iclass 11, count 2 2006.201.02:12:57.64#ibcon#flushed, iclass 11, count 2 2006.201.02:12:57.64#ibcon#about to write, iclass 11, count 2 2006.201.02:12:57.64#ibcon#wrote, iclass 11, count 2 2006.201.02:12:57.64#ibcon#about to read 3, iclass 11, count 2 2006.201.02:12:57.67#ibcon#read 3, iclass 11, count 2 2006.201.02:12:57.67#ibcon#about to read 4, iclass 11, count 2 2006.201.02:12:57.67#ibcon#read 4, iclass 11, count 2 2006.201.02:12:57.67#ibcon#about to read 5, iclass 11, count 2 2006.201.02:12:57.67#ibcon#read 5, iclass 11, count 2 2006.201.02:12:57.67#ibcon#about to read 6, iclass 11, count 2 2006.201.02:12:57.67#ibcon#read 6, iclass 11, count 2 2006.201.02:12:57.67#ibcon#end of sib2, iclass 11, count 2 2006.201.02:12:57.67#ibcon#*after write, iclass 11, count 2 2006.201.02:12:57.67#ibcon#*before return 0, iclass 11, count 2 2006.201.02:12:57.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:57.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:12:57.67#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.02:12:57.67#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:57.67#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:57.79#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:57.79#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:57.79#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:12:57.79#ibcon#first serial, iclass 11, count 0 2006.201.02:12:57.79#ibcon#enter sib2, iclass 11, count 0 2006.201.02:12:57.79#ibcon#flushed, iclass 11, count 0 2006.201.02:12:57.79#ibcon#about to write, iclass 11, count 0 2006.201.02:12:57.79#ibcon#wrote, iclass 11, count 0 2006.201.02:12:57.79#ibcon#about to read 3, iclass 11, count 0 2006.201.02:12:57.81#ibcon#read 3, iclass 11, count 0 2006.201.02:12:57.81#ibcon#about to read 4, iclass 11, count 0 2006.201.02:12:57.81#ibcon#read 4, iclass 11, count 0 2006.201.02:12:57.81#ibcon#about to read 5, iclass 11, count 0 2006.201.02:12:57.81#ibcon#read 5, iclass 11, count 0 2006.201.02:12:57.81#ibcon#about to read 6, iclass 11, count 0 2006.201.02:12:57.81#ibcon#read 6, iclass 11, count 0 2006.201.02:12:57.81#ibcon#end of sib2, iclass 11, count 0 2006.201.02:12:57.81#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:12:57.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:12:57.81#ibcon#[27=USB\r\n] 2006.201.02:12:57.81#ibcon#*before write, iclass 11, count 0 2006.201.02:12:57.81#ibcon#enter sib2, iclass 11, count 0 2006.201.02:12:57.81#ibcon#flushed, iclass 11, count 0 2006.201.02:12:57.81#ibcon#about to write, iclass 11, count 0 2006.201.02:12:57.81#ibcon#wrote, iclass 11, count 0 2006.201.02:12:57.81#ibcon#about to read 3, iclass 11, count 0 2006.201.02:12:57.84#ibcon#read 3, iclass 11, count 0 2006.201.02:12:57.84#ibcon#about to read 4, iclass 11, count 0 2006.201.02:12:57.84#ibcon#read 4, iclass 11, count 0 2006.201.02:12:57.84#ibcon#about to read 5, iclass 11, count 0 2006.201.02:12:57.84#ibcon#read 5, iclass 11, count 0 2006.201.02:12:57.84#ibcon#about to read 6, iclass 11, count 0 2006.201.02:12:57.84#ibcon#read 6, iclass 11, count 0 2006.201.02:12:57.84#ibcon#end of sib2, iclass 11, count 0 2006.201.02:12:57.84#ibcon#*after write, iclass 11, count 0 2006.201.02:12:57.84#ibcon#*before return 0, iclass 11, count 0 2006.201.02:12:57.84#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:57.84#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:12:57.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:12:57.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:12:57.84$vck44/vblo=3,649.99 2006.201.02:12:57.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.02:12:57.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.02:12:57.84#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:57.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:57.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:57.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:57.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:12:57.84#ibcon#first serial, iclass 13, count 0 2006.201.02:12:57.84#ibcon#enter sib2, iclass 13, count 0 2006.201.02:12:57.84#ibcon#flushed, iclass 13, count 0 2006.201.02:12:57.84#ibcon#about to write, iclass 13, count 0 2006.201.02:12:57.84#ibcon#wrote, iclass 13, count 0 2006.201.02:12:57.84#ibcon#about to read 3, iclass 13, count 0 2006.201.02:12:57.86#ibcon#read 3, iclass 13, count 0 2006.201.02:12:57.86#ibcon#about to read 4, iclass 13, count 0 2006.201.02:12:57.86#ibcon#read 4, iclass 13, count 0 2006.201.02:12:57.86#ibcon#about to read 5, iclass 13, count 0 2006.201.02:12:57.86#ibcon#read 5, iclass 13, count 0 2006.201.02:12:57.86#ibcon#about to read 6, iclass 13, count 0 2006.201.02:12:57.86#ibcon#read 6, iclass 13, count 0 2006.201.02:12:57.86#ibcon#end of sib2, iclass 13, count 0 2006.201.02:12:57.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:12:57.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:12:57.86#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:12:57.86#ibcon#*before write, iclass 13, count 0 2006.201.02:12:57.86#ibcon#enter sib2, iclass 13, count 0 2006.201.02:12:57.86#ibcon#flushed, iclass 13, count 0 2006.201.02:12:57.86#ibcon#about to write, iclass 13, count 0 2006.201.02:12:57.86#ibcon#wrote, iclass 13, count 0 2006.201.02:12:57.86#ibcon#about to read 3, iclass 13, count 0 2006.201.02:12:57.90#ibcon#read 3, iclass 13, count 0 2006.201.02:12:57.90#ibcon#about to read 4, iclass 13, count 0 2006.201.02:12:57.90#ibcon#read 4, iclass 13, count 0 2006.201.02:12:57.90#ibcon#about to read 5, iclass 13, count 0 2006.201.02:12:57.90#ibcon#read 5, iclass 13, count 0 2006.201.02:12:57.90#ibcon#about to read 6, iclass 13, count 0 2006.201.02:12:57.90#ibcon#read 6, iclass 13, count 0 2006.201.02:12:57.90#ibcon#end of sib2, iclass 13, count 0 2006.201.02:12:57.90#ibcon#*after write, iclass 13, count 0 2006.201.02:12:57.90#ibcon#*before return 0, iclass 13, count 0 2006.201.02:12:57.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:57.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:12:57.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:12:57.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:12:57.90$vck44/vb=3,4 2006.201.02:12:57.90#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.02:12:57.90#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.02:12:57.90#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:57.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:57.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:57.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:57.96#ibcon#enter wrdev, iclass 15, count 2 2006.201.02:12:57.96#ibcon#first serial, iclass 15, count 2 2006.201.02:12:57.96#ibcon#enter sib2, iclass 15, count 2 2006.201.02:12:57.96#ibcon#flushed, iclass 15, count 2 2006.201.02:12:57.96#ibcon#about to write, iclass 15, count 2 2006.201.02:12:57.96#ibcon#wrote, iclass 15, count 2 2006.201.02:12:57.96#ibcon#about to read 3, iclass 15, count 2 2006.201.02:12:57.98#ibcon#read 3, iclass 15, count 2 2006.201.02:12:57.98#ibcon#about to read 4, iclass 15, count 2 2006.201.02:12:57.98#ibcon#read 4, iclass 15, count 2 2006.201.02:12:57.98#ibcon#about to read 5, iclass 15, count 2 2006.201.02:12:57.98#ibcon#read 5, iclass 15, count 2 2006.201.02:12:57.98#ibcon#about to read 6, iclass 15, count 2 2006.201.02:12:57.98#ibcon#read 6, iclass 15, count 2 2006.201.02:12:57.98#ibcon#end of sib2, iclass 15, count 2 2006.201.02:12:57.98#ibcon#*mode == 0, iclass 15, count 2 2006.201.02:12:57.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.02:12:57.98#ibcon#[27=AT03-04\r\n] 2006.201.02:12:57.98#ibcon#*before write, iclass 15, count 2 2006.201.02:12:57.98#ibcon#enter sib2, iclass 15, count 2 2006.201.02:12:57.98#ibcon#flushed, iclass 15, count 2 2006.201.02:12:57.98#ibcon#about to write, iclass 15, count 2 2006.201.02:12:57.98#ibcon#wrote, iclass 15, count 2 2006.201.02:12:57.98#ibcon#about to read 3, iclass 15, count 2 2006.201.02:12:58.01#ibcon#read 3, iclass 15, count 2 2006.201.02:12:58.01#ibcon#about to read 4, iclass 15, count 2 2006.201.02:12:58.01#ibcon#read 4, iclass 15, count 2 2006.201.02:12:58.01#ibcon#about to read 5, iclass 15, count 2 2006.201.02:12:58.01#ibcon#read 5, iclass 15, count 2 2006.201.02:12:58.01#ibcon#about to read 6, iclass 15, count 2 2006.201.02:12:58.01#ibcon#read 6, iclass 15, count 2 2006.201.02:12:58.01#ibcon#end of sib2, iclass 15, count 2 2006.201.02:12:58.01#ibcon#*after write, iclass 15, count 2 2006.201.02:12:58.01#ibcon#*before return 0, iclass 15, count 2 2006.201.02:12:58.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:58.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:12:58.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.02:12:58.01#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:58.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:58.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:58.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:58.13#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:12:58.13#ibcon#first serial, iclass 15, count 0 2006.201.02:12:58.13#ibcon#enter sib2, iclass 15, count 0 2006.201.02:12:58.13#ibcon#flushed, iclass 15, count 0 2006.201.02:12:58.13#ibcon#about to write, iclass 15, count 0 2006.201.02:12:58.13#ibcon#wrote, iclass 15, count 0 2006.201.02:12:58.13#ibcon#about to read 3, iclass 15, count 0 2006.201.02:12:58.15#ibcon#read 3, iclass 15, count 0 2006.201.02:12:58.15#ibcon#about to read 4, iclass 15, count 0 2006.201.02:12:58.15#ibcon#read 4, iclass 15, count 0 2006.201.02:12:58.15#ibcon#about to read 5, iclass 15, count 0 2006.201.02:12:58.15#ibcon#read 5, iclass 15, count 0 2006.201.02:12:58.15#ibcon#about to read 6, iclass 15, count 0 2006.201.02:12:58.15#ibcon#read 6, iclass 15, count 0 2006.201.02:12:58.15#ibcon#end of sib2, iclass 15, count 0 2006.201.02:12:58.15#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:12:58.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:12:58.15#ibcon#[27=USB\r\n] 2006.201.02:12:58.15#ibcon#*before write, iclass 15, count 0 2006.201.02:12:58.15#ibcon#enter sib2, iclass 15, count 0 2006.201.02:12:58.15#ibcon#flushed, iclass 15, count 0 2006.201.02:12:58.15#ibcon#about to write, iclass 15, count 0 2006.201.02:12:58.15#ibcon#wrote, iclass 15, count 0 2006.201.02:12:58.15#ibcon#about to read 3, iclass 15, count 0 2006.201.02:12:58.18#ibcon#read 3, iclass 15, count 0 2006.201.02:12:58.18#ibcon#about to read 4, iclass 15, count 0 2006.201.02:12:58.18#ibcon#read 4, iclass 15, count 0 2006.201.02:12:58.18#ibcon#about to read 5, iclass 15, count 0 2006.201.02:12:58.18#ibcon#read 5, iclass 15, count 0 2006.201.02:12:58.18#ibcon#about to read 6, iclass 15, count 0 2006.201.02:12:58.18#ibcon#read 6, iclass 15, count 0 2006.201.02:12:58.18#ibcon#end of sib2, iclass 15, count 0 2006.201.02:12:58.18#ibcon#*after write, iclass 15, count 0 2006.201.02:12:58.18#ibcon#*before return 0, iclass 15, count 0 2006.201.02:12:58.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:58.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:12:58.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:12:58.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:12:58.18$vck44/vblo=4,679.99 2006.201.02:12:58.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.02:12:58.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.02:12:58.18#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:58.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:58.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:58.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:58.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:12:58.18#ibcon#first serial, iclass 17, count 0 2006.201.02:12:58.18#ibcon#enter sib2, iclass 17, count 0 2006.201.02:12:58.18#ibcon#flushed, iclass 17, count 0 2006.201.02:12:58.18#ibcon#about to write, iclass 17, count 0 2006.201.02:12:58.18#ibcon#wrote, iclass 17, count 0 2006.201.02:12:58.18#ibcon#about to read 3, iclass 17, count 0 2006.201.02:12:58.20#ibcon#read 3, iclass 17, count 0 2006.201.02:12:58.20#ibcon#about to read 4, iclass 17, count 0 2006.201.02:12:58.20#ibcon#read 4, iclass 17, count 0 2006.201.02:12:58.20#ibcon#about to read 5, iclass 17, count 0 2006.201.02:12:58.20#ibcon#read 5, iclass 17, count 0 2006.201.02:12:58.20#ibcon#about to read 6, iclass 17, count 0 2006.201.02:12:58.20#ibcon#read 6, iclass 17, count 0 2006.201.02:12:58.20#ibcon#end of sib2, iclass 17, count 0 2006.201.02:12:58.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:12:58.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:12:58.20#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:12:58.20#ibcon#*before write, iclass 17, count 0 2006.201.02:12:58.20#ibcon#enter sib2, iclass 17, count 0 2006.201.02:12:58.20#ibcon#flushed, iclass 17, count 0 2006.201.02:12:58.20#ibcon#about to write, iclass 17, count 0 2006.201.02:12:58.20#ibcon#wrote, iclass 17, count 0 2006.201.02:12:58.20#ibcon#about to read 3, iclass 17, count 0 2006.201.02:12:58.24#ibcon#read 3, iclass 17, count 0 2006.201.02:12:58.24#ibcon#about to read 4, iclass 17, count 0 2006.201.02:12:58.24#ibcon#read 4, iclass 17, count 0 2006.201.02:12:58.24#ibcon#about to read 5, iclass 17, count 0 2006.201.02:12:58.24#ibcon#read 5, iclass 17, count 0 2006.201.02:12:58.24#ibcon#about to read 6, iclass 17, count 0 2006.201.02:12:58.24#ibcon#read 6, iclass 17, count 0 2006.201.02:12:58.24#ibcon#end of sib2, iclass 17, count 0 2006.201.02:12:58.24#ibcon#*after write, iclass 17, count 0 2006.201.02:12:58.24#ibcon#*before return 0, iclass 17, count 0 2006.201.02:12:58.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:58.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:12:58.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:12:58.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:12:58.24$vck44/vb=4,5 2006.201.02:12:58.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.02:12:58.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.02:12:58.24#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:58.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:58.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:58.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:58.30#ibcon#enter wrdev, iclass 19, count 2 2006.201.02:12:58.30#ibcon#first serial, iclass 19, count 2 2006.201.02:12:58.30#ibcon#enter sib2, iclass 19, count 2 2006.201.02:12:58.30#ibcon#flushed, iclass 19, count 2 2006.201.02:12:58.30#ibcon#about to write, iclass 19, count 2 2006.201.02:12:58.30#ibcon#wrote, iclass 19, count 2 2006.201.02:12:58.30#ibcon#about to read 3, iclass 19, count 2 2006.201.02:12:58.32#ibcon#read 3, iclass 19, count 2 2006.201.02:12:58.32#ibcon#about to read 4, iclass 19, count 2 2006.201.02:12:58.32#ibcon#read 4, iclass 19, count 2 2006.201.02:12:58.32#ibcon#about to read 5, iclass 19, count 2 2006.201.02:12:58.32#ibcon#read 5, iclass 19, count 2 2006.201.02:12:58.32#ibcon#about to read 6, iclass 19, count 2 2006.201.02:12:58.32#ibcon#read 6, iclass 19, count 2 2006.201.02:12:58.32#ibcon#end of sib2, iclass 19, count 2 2006.201.02:12:58.32#ibcon#*mode == 0, iclass 19, count 2 2006.201.02:12:58.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.02:12:58.32#ibcon#[27=AT04-05\r\n] 2006.201.02:12:58.32#ibcon#*before write, iclass 19, count 2 2006.201.02:12:58.32#ibcon#enter sib2, iclass 19, count 2 2006.201.02:12:58.32#ibcon#flushed, iclass 19, count 2 2006.201.02:12:58.32#ibcon#about to write, iclass 19, count 2 2006.201.02:12:58.32#ibcon#wrote, iclass 19, count 2 2006.201.02:12:58.32#ibcon#about to read 3, iclass 19, count 2 2006.201.02:12:58.35#ibcon#read 3, iclass 19, count 2 2006.201.02:12:58.35#ibcon#about to read 4, iclass 19, count 2 2006.201.02:12:58.35#ibcon#read 4, iclass 19, count 2 2006.201.02:12:58.35#ibcon#about to read 5, iclass 19, count 2 2006.201.02:12:58.35#ibcon#read 5, iclass 19, count 2 2006.201.02:12:58.35#ibcon#about to read 6, iclass 19, count 2 2006.201.02:12:58.35#ibcon#read 6, iclass 19, count 2 2006.201.02:12:58.35#ibcon#end of sib2, iclass 19, count 2 2006.201.02:12:58.35#ibcon#*after write, iclass 19, count 2 2006.201.02:12:58.35#ibcon#*before return 0, iclass 19, count 2 2006.201.02:12:58.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:58.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:12:58.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.02:12:58.35#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:58.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:58.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:58.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:58.47#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:12:58.47#ibcon#first serial, iclass 19, count 0 2006.201.02:12:58.47#ibcon#enter sib2, iclass 19, count 0 2006.201.02:12:58.47#ibcon#flushed, iclass 19, count 0 2006.201.02:12:58.47#ibcon#about to write, iclass 19, count 0 2006.201.02:12:58.47#ibcon#wrote, iclass 19, count 0 2006.201.02:12:58.47#ibcon#about to read 3, iclass 19, count 0 2006.201.02:12:58.49#ibcon#read 3, iclass 19, count 0 2006.201.02:12:58.49#ibcon#about to read 4, iclass 19, count 0 2006.201.02:12:58.49#ibcon#read 4, iclass 19, count 0 2006.201.02:12:58.49#ibcon#about to read 5, iclass 19, count 0 2006.201.02:12:58.49#ibcon#read 5, iclass 19, count 0 2006.201.02:12:58.49#ibcon#about to read 6, iclass 19, count 0 2006.201.02:12:58.49#ibcon#read 6, iclass 19, count 0 2006.201.02:12:58.49#ibcon#end of sib2, iclass 19, count 0 2006.201.02:12:58.49#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:12:58.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:12:58.49#ibcon#[27=USB\r\n] 2006.201.02:12:58.49#ibcon#*before write, iclass 19, count 0 2006.201.02:12:58.49#ibcon#enter sib2, iclass 19, count 0 2006.201.02:12:58.49#ibcon#flushed, iclass 19, count 0 2006.201.02:12:58.49#ibcon#about to write, iclass 19, count 0 2006.201.02:12:58.49#ibcon#wrote, iclass 19, count 0 2006.201.02:12:58.49#ibcon#about to read 3, iclass 19, count 0 2006.201.02:12:58.52#ibcon#read 3, iclass 19, count 0 2006.201.02:12:58.52#ibcon#about to read 4, iclass 19, count 0 2006.201.02:12:58.52#ibcon#read 4, iclass 19, count 0 2006.201.02:12:58.52#ibcon#about to read 5, iclass 19, count 0 2006.201.02:12:58.52#ibcon#read 5, iclass 19, count 0 2006.201.02:12:58.52#ibcon#about to read 6, iclass 19, count 0 2006.201.02:12:58.52#ibcon#read 6, iclass 19, count 0 2006.201.02:12:58.52#ibcon#end of sib2, iclass 19, count 0 2006.201.02:12:58.52#ibcon#*after write, iclass 19, count 0 2006.201.02:12:58.52#ibcon#*before return 0, iclass 19, count 0 2006.201.02:12:58.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:58.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:12:58.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:12:58.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:12:58.52$vck44/vblo=5,709.99 2006.201.02:12:58.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.02:12:58.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.02:12:58.52#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:58.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:58.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:58.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:58.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:12:58.52#ibcon#first serial, iclass 21, count 0 2006.201.02:12:58.52#ibcon#enter sib2, iclass 21, count 0 2006.201.02:12:58.52#ibcon#flushed, iclass 21, count 0 2006.201.02:12:58.52#ibcon#about to write, iclass 21, count 0 2006.201.02:12:58.52#ibcon#wrote, iclass 21, count 0 2006.201.02:12:58.52#ibcon#about to read 3, iclass 21, count 0 2006.201.02:12:58.54#ibcon#read 3, iclass 21, count 0 2006.201.02:12:58.54#ibcon#about to read 4, iclass 21, count 0 2006.201.02:12:58.54#ibcon#read 4, iclass 21, count 0 2006.201.02:12:58.54#ibcon#about to read 5, iclass 21, count 0 2006.201.02:12:58.54#ibcon#read 5, iclass 21, count 0 2006.201.02:12:58.54#ibcon#about to read 6, iclass 21, count 0 2006.201.02:12:58.54#ibcon#read 6, iclass 21, count 0 2006.201.02:12:58.54#ibcon#end of sib2, iclass 21, count 0 2006.201.02:12:58.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:12:58.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:12:58.54#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:12:58.54#ibcon#*before write, iclass 21, count 0 2006.201.02:12:58.54#ibcon#enter sib2, iclass 21, count 0 2006.201.02:12:58.54#ibcon#flushed, iclass 21, count 0 2006.201.02:12:58.54#ibcon#about to write, iclass 21, count 0 2006.201.02:12:58.54#ibcon#wrote, iclass 21, count 0 2006.201.02:12:58.54#ibcon#about to read 3, iclass 21, count 0 2006.201.02:12:58.58#ibcon#read 3, iclass 21, count 0 2006.201.02:12:58.58#ibcon#about to read 4, iclass 21, count 0 2006.201.02:12:58.58#ibcon#read 4, iclass 21, count 0 2006.201.02:12:58.58#ibcon#about to read 5, iclass 21, count 0 2006.201.02:12:58.58#ibcon#read 5, iclass 21, count 0 2006.201.02:12:58.58#ibcon#about to read 6, iclass 21, count 0 2006.201.02:12:58.58#ibcon#read 6, iclass 21, count 0 2006.201.02:12:58.58#ibcon#end of sib2, iclass 21, count 0 2006.201.02:12:58.58#ibcon#*after write, iclass 21, count 0 2006.201.02:12:58.58#ibcon#*before return 0, iclass 21, count 0 2006.201.02:12:58.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:58.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:12:58.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:12:58.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:12:58.58$vck44/vb=5,4 2006.201.02:12:58.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.02:12:58.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.02:12:58.58#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:58.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:58.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:58.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:58.64#ibcon#enter wrdev, iclass 23, count 2 2006.201.02:12:58.64#ibcon#first serial, iclass 23, count 2 2006.201.02:12:58.64#ibcon#enter sib2, iclass 23, count 2 2006.201.02:12:58.64#ibcon#flushed, iclass 23, count 2 2006.201.02:12:58.64#ibcon#about to write, iclass 23, count 2 2006.201.02:12:58.64#ibcon#wrote, iclass 23, count 2 2006.201.02:12:58.64#ibcon#about to read 3, iclass 23, count 2 2006.201.02:12:58.66#ibcon#read 3, iclass 23, count 2 2006.201.02:12:58.66#ibcon#about to read 4, iclass 23, count 2 2006.201.02:12:58.66#ibcon#read 4, iclass 23, count 2 2006.201.02:12:58.66#ibcon#about to read 5, iclass 23, count 2 2006.201.02:12:58.66#ibcon#read 5, iclass 23, count 2 2006.201.02:12:58.66#ibcon#about to read 6, iclass 23, count 2 2006.201.02:12:58.66#ibcon#read 6, iclass 23, count 2 2006.201.02:12:58.66#ibcon#end of sib2, iclass 23, count 2 2006.201.02:12:58.66#ibcon#*mode == 0, iclass 23, count 2 2006.201.02:12:58.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.02:12:58.66#ibcon#[27=AT05-04\r\n] 2006.201.02:12:58.66#ibcon#*before write, iclass 23, count 2 2006.201.02:12:58.66#ibcon#enter sib2, iclass 23, count 2 2006.201.02:12:58.66#ibcon#flushed, iclass 23, count 2 2006.201.02:12:58.66#ibcon#about to write, iclass 23, count 2 2006.201.02:12:58.66#ibcon#wrote, iclass 23, count 2 2006.201.02:12:58.66#ibcon#about to read 3, iclass 23, count 2 2006.201.02:12:58.69#ibcon#read 3, iclass 23, count 2 2006.201.02:12:58.69#ibcon#about to read 4, iclass 23, count 2 2006.201.02:12:58.69#ibcon#read 4, iclass 23, count 2 2006.201.02:12:58.69#ibcon#about to read 5, iclass 23, count 2 2006.201.02:12:58.69#ibcon#read 5, iclass 23, count 2 2006.201.02:12:58.69#ibcon#about to read 6, iclass 23, count 2 2006.201.02:12:58.69#ibcon#read 6, iclass 23, count 2 2006.201.02:12:58.69#ibcon#end of sib2, iclass 23, count 2 2006.201.02:12:58.69#ibcon#*after write, iclass 23, count 2 2006.201.02:12:58.69#ibcon#*before return 0, iclass 23, count 2 2006.201.02:12:58.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:58.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:12:58.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.02:12:58.69#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:58.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:58.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:58.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:58.81#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:12:58.81#ibcon#first serial, iclass 23, count 0 2006.201.02:12:58.81#ibcon#enter sib2, iclass 23, count 0 2006.201.02:12:58.81#ibcon#flushed, iclass 23, count 0 2006.201.02:12:58.81#ibcon#about to write, iclass 23, count 0 2006.201.02:12:58.81#ibcon#wrote, iclass 23, count 0 2006.201.02:12:58.81#ibcon#about to read 3, iclass 23, count 0 2006.201.02:12:58.83#ibcon#read 3, iclass 23, count 0 2006.201.02:12:58.83#ibcon#about to read 4, iclass 23, count 0 2006.201.02:12:58.83#ibcon#read 4, iclass 23, count 0 2006.201.02:12:58.83#ibcon#about to read 5, iclass 23, count 0 2006.201.02:12:58.83#ibcon#read 5, iclass 23, count 0 2006.201.02:12:58.83#ibcon#about to read 6, iclass 23, count 0 2006.201.02:12:58.83#ibcon#read 6, iclass 23, count 0 2006.201.02:12:58.83#ibcon#end of sib2, iclass 23, count 0 2006.201.02:12:58.83#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:12:58.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:12:58.83#ibcon#[27=USB\r\n] 2006.201.02:12:58.83#ibcon#*before write, iclass 23, count 0 2006.201.02:12:58.83#ibcon#enter sib2, iclass 23, count 0 2006.201.02:12:58.83#ibcon#flushed, iclass 23, count 0 2006.201.02:12:58.83#ibcon#about to write, iclass 23, count 0 2006.201.02:12:58.83#ibcon#wrote, iclass 23, count 0 2006.201.02:12:58.83#ibcon#about to read 3, iclass 23, count 0 2006.201.02:12:58.86#ibcon#read 3, iclass 23, count 0 2006.201.02:12:58.86#ibcon#about to read 4, iclass 23, count 0 2006.201.02:12:58.86#ibcon#read 4, iclass 23, count 0 2006.201.02:12:58.86#ibcon#about to read 5, iclass 23, count 0 2006.201.02:12:58.86#ibcon#read 5, iclass 23, count 0 2006.201.02:12:58.86#ibcon#about to read 6, iclass 23, count 0 2006.201.02:12:58.86#ibcon#read 6, iclass 23, count 0 2006.201.02:12:58.86#ibcon#end of sib2, iclass 23, count 0 2006.201.02:12:58.86#ibcon#*after write, iclass 23, count 0 2006.201.02:12:58.86#ibcon#*before return 0, iclass 23, count 0 2006.201.02:12:58.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:58.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:12:58.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:12:58.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:12:58.86$vck44/vblo=6,719.99 2006.201.02:12:58.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.02:12:58.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.02:12:58.86#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:58.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:58.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:58.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:58.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.02:12:58.86#ibcon#first serial, iclass 25, count 0 2006.201.02:12:58.86#ibcon#enter sib2, iclass 25, count 0 2006.201.02:12:58.86#ibcon#flushed, iclass 25, count 0 2006.201.02:12:58.86#ibcon#about to write, iclass 25, count 0 2006.201.02:12:58.86#ibcon#wrote, iclass 25, count 0 2006.201.02:12:58.86#ibcon#about to read 3, iclass 25, count 0 2006.201.02:12:58.88#ibcon#read 3, iclass 25, count 0 2006.201.02:12:58.88#ibcon#about to read 4, iclass 25, count 0 2006.201.02:12:58.88#ibcon#read 4, iclass 25, count 0 2006.201.02:12:58.88#ibcon#about to read 5, iclass 25, count 0 2006.201.02:12:58.88#ibcon#read 5, iclass 25, count 0 2006.201.02:12:58.88#ibcon#about to read 6, iclass 25, count 0 2006.201.02:12:58.88#ibcon#read 6, iclass 25, count 0 2006.201.02:12:58.88#ibcon#end of sib2, iclass 25, count 0 2006.201.02:12:58.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.02:12:58.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.02:12:58.88#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:12:58.88#ibcon#*before write, iclass 25, count 0 2006.201.02:12:58.88#ibcon#enter sib2, iclass 25, count 0 2006.201.02:12:58.88#ibcon#flushed, iclass 25, count 0 2006.201.02:12:58.88#ibcon#about to write, iclass 25, count 0 2006.201.02:12:58.88#ibcon#wrote, iclass 25, count 0 2006.201.02:12:58.88#ibcon#about to read 3, iclass 25, count 0 2006.201.02:12:58.92#ibcon#read 3, iclass 25, count 0 2006.201.02:12:58.92#ibcon#about to read 4, iclass 25, count 0 2006.201.02:12:58.92#ibcon#read 4, iclass 25, count 0 2006.201.02:12:58.92#ibcon#about to read 5, iclass 25, count 0 2006.201.02:12:58.92#ibcon#read 5, iclass 25, count 0 2006.201.02:12:58.92#ibcon#about to read 6, iclass 25, count 0 2006.201.02:12:58.92#ibcon#read 6, iclass 25, count 0 2006.201.02:12:58.92#ibcon#end of sib2, iclass 25, count 0 2006.201.02:12:58.92#ibcon#*after write, iclass 25, count 0 2006.201.02:12:58.92#ibcon#*before return 0, iclass 25, count 0 2006.201.02:12:58.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:58.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:12:58.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.02:12:58.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.02:12:58.92$vck44/vb=6,4 2006.201.02:12:58.92#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.02:12:58.92#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.02:12:58.92#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:58.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:58.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:58.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:58.98#ibcon#enter wrdev, iclass 27, count 2 2006.201.02:12:58.98#ibcon#first serial, iclass 27, count 2 2006.201.02:12:58.98#ibcon#enter sib2, iclass 27, count 2 2006.201.02:12:58.98#ibcon#flushed, iclass 27, count 2 2006.201.02:12:58.98#ibcon#about to write, iclass 27, count 2 2006.201.02:12:58.98#ibcon#wrote, iclass 27, count 2 2006.201.02:12:58.98#ibcon#about to read 3, iclass 27, count 2 2006.201.02:12:59.00#ibcon#read 3, iclass 27, count 2 2006.201.02:12:59.00#ibcon#about to read 4, iclass 27, count 2 2006.201.02:12:59.00#ibcon#read 4, iclass 27, count 2 2006.201.02:12:59.00#ibcon#about to read 5, iclass 27, count 2 2006.201.02:12:59.00#ibcon#read 5, iclass 27, count 2 2006.201.02:12:59.00#ibcon#about to read 6, iclass 27, count 2 2006.201.02:12:59.00#ibcon#read 6, iclass 27, count 2 2006.201.02:12:59.00#ibcon#end of sib2, iclass 27, count 2 2006.201.02:12:59.00#ibcon#*mode == 0, iclass 27, count 2 2006.201.02:12:59.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.02:12:59.00#ibcon#[27=AT06-04\r\n] 2006.201.02:12:59.00#ibcon#*before write, iclass 27, count 2 2006.201.02:12:59.00#ibcon#enter sib2, iclass 27, count 2 2006.201.02:12:59.00#ibcon#flushed, iclass 27, count 2 2006.201.02:12:59.00#ibcon#about to write, iclass 27, count 2 2006.201.02:12:59.00#ibcon#wrote, iclass 27, count 2 2006.201.02:12:59.00#ibcon#about to read 3, iclass 27, count 2 2006.201.02:12:59.03#ibcon#read 3, iclass 27, count 2 2006.201.02:12:59.03#ibcon#about to read 4, iclass 27, count 2 2006.201.02:12:59.03#ibcon#read 4, iclass 27, count 2 2006.201.02:12:59.03#ibcon#about to read 5, iclass 27, count 2 2006.201.02:12:59.03#ibcon#read 5, iclass 27, count 2 2006.201.02:12:59.03#ibcon#about to read 6, iclass 27, count 2 2006.201.02:12:59.03#ibcon#read 6, iclass 27, count 2 2006.201.02:12:59.03#ibcon#end of sib2, iclass 27, count 2 2006.201.02:12:59.03#ibcon#*after write, iclass 27, count 2 2006.201.02:12:59.03#ibcon#*before return 0, iclass 27, count 2 2006.201.02:12:59.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:59.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:12:59.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.02:12:59.03#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:59.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:59.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:59.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:59.15#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:12:59.15#ibcon#first serial, iclass 27, count 0 2006.201.02:12:59.15#ibcon#enter sib2, iclass 27, count 0 2006.201.02:12:59.15#ibcon#flushed, iclass 27, count 0 2006.201.02:12:59.15#ibcon#about to write, iclass 27, count 0 2006.201.02:12:59.15#ibcon#wrote, iclass 27, count 0 2006.201.02:12:59.15#ibcon#about to read 3, iclass 27, count 0 2006.201.02:12:59.17#ibcon#read 3, iclass 27, count 0 2006.201.02:12:59.17#ibcon#about to read 4, iclass 27, count 0 2006.201.02:12:59.17#ibcon#read 4, iclass 27, count 0 2006.201.02:12:59.17#ibcon#about to read 5, iclass 27, count 0 2006.201.02:12:59.17#ibcon#read 5, iclass 27, count 0 2006.201.02:12:59.17#ibcon#about to read 6, iclass 27, count 0 2006.201.02:12:59.17#ibcon#read 6, iclass 27, count 0 2006.201.02:12:59.17#ibcon#end of sib2, iclass 27, count 0 2006.201.02:12:59.17#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:12:59.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:12:59.17#ibcon#[27=USB\r\n] 2006.201.02:12:59.17#ibcon#*before write, iclass 27, count 0 2006.201.02:12:59.17#ibcon#enter sib2, iclass 27, count 0 2006.201.02:12:59.17#ibcon#flushed, iclass 27, count 0 2006.201.02:12:59.17#ibcon#about to write, iclass 27, count 0 2006.201.02:12:59.17#ibcon#wrote, iclass 27, count 0 2006.201.02:12:59.17#ibcon#about to read 3, iclass 27, count 0 2006.201.02:12:59.20#ibcon#read 3, iclass 27, count 0 2006.201.02:12:59.20#ibcon#about to read 4, iclass 27, count 0 2006.201.02:12:59.20#ibcon#read 4, iclass 27, count 0 2006.201.02:12:59.20#ibcon#about to read 5, iclass 27, count 0 2006.201.02:12:59.20#ibcon#read 5, iclass 27, count 0 2006.201.02:12:59.20#ibcon#about to read 6, iclass 27, count 0 2006.201.02:12:59.20#ibcon#read 6, iclass 27, count 0 2006.201.02:12:59.20#ibcon#end of sib2, iclass 27, count 0 2006.201.02:12:59.20#ibcon#*after write, iclass 27, count 0 2006.201.02:12:59.20#ibcon#*before return 0, iclass 27, count 0 2006.201.02:12:59.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:59.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:12:59.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:12:59.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:12:59.20$vck44/vblo=7,734.99 2006.201.02:12:59.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.02:12:59.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.02:12:59.20#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:59.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:59.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:59.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:59.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:12:59.20#ibcon#first serial, iclass 29, count 0 2006.201.02:12:59.20#ibcon#enter sib2, iclass 29, count 0 2006.201.02:12:59.20#ibcon#flushed, iclass 29, count 0 2006.201.02:12:59.20#ibcon#about to write, iclass 29, count 0 2006.201.02:12:59.20#ibcon#wrote, iclass 29, count 0 2006.201.02:12:59.20#ibcon#about to read 3, iclass 29, count 0 2006.201.02:12:59.22#ibcon#read 3, iclass 29, count 0 2006.201.02:12:59.22#ibcon#about to read 4, iclass 29, count 0 2006.201.02:12:59.22#ibcon#read 4, iclass 29, count 0 2006.201.02:12:59.22#ibcon#about to read 5, iclass 29, count 0 2006.201.02:12:59.22#ibcon#read 5, iclass 29, count 0 2006.201.02:12:59.22#ibcon#about to read 6, iclass 29, count 0 2006.201.02:12:59.22#ibcon#read 6, iclass 29, count 0 2006.201.02:12:59.22#ibcon#end of sib2, iclass 29, count 0 2006.201.02:12:59.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:12:59.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:12:59.22#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:12:59.22#ibcon#*before write, iclass 29, count 0 2006.201.02:12:59.22#ibcon#enter sib2, iclass 29, count 0 2006.201.02:12:59.22#ibcon#flushed, iclass 29, count 0 2006.201.02:12:59.22#ibcon#about to write, iclass 29, count 0 2006.201.02:12:59.22#ibcon#wrote, iclass 29, count 0 2006.201.02:12:59.22#ibcon#about to read 3, iclass 29, count 0 2006.201.02:12:59.26#ibcon#read 3, iclass 29, count 0 2006.201.02:12:59.26#ibcon#about to read 4, iclass 29, count 0 2006.201.02:12:59.26#ibcon#read 4, iclass 29, count 0 2006.201.02:12:59.26#ibcon#about to read 5, iclass 29, count 0 2006.201.02:12:59.26#ibcon#read 5, iclass 29, count 0 2006.201.02:12:59.26#ibcon#about to read 6, iclass 29, count 0 2006.201.02:12:59.26#ibcon#read 6, iclass 29, count 0 2006.201.02:12:59.26#ibcon#end of sib2, iclass 29, count 0 2006.201.02:12:59.26#ibcon#*after write, iclass 29, count 0 2006.201.02:12:59.26#ibcon#*before return 0, iclass 29, count 0 2006.201.02:12:59.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:59.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:12:59.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:12:59.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:12:59.26$vck44/vb=7,4 2006.201.02:12:59.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.02:12:59.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.02:12:59.26#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:59.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:59.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:59.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:59.32#ibcon#enter wrdev, iclass 31, count 2 2006.201.02:12:59.32#ibcon#first serial, iclass 31, count 2 2006.201.02:12:59.32#ibcon#enter sib2, iclass 31, count 2 2006.201.02:12:59.32#ibcon#flushed, iclass 31, count 2 2006.201.02:12:59.32#ibcon#about to write, iclass 31, count 2 2006.201.02:12:59.32#ibcon#wrote, iclass 31, count 2 2006.201.02:12:59.32#ibcon#about to read 3, iclass 31, count 2 2006.201.02:12:59.34#ibcon#read 3, iclass 31, count 2 2006.201.02:12:59.34#ibcon#about to read 4, iclass 31, count 2 2006.201.02:12:59.34#ibcon#read 4, iclass 31, count 2 2006.201.02:12:59.34#ibcon#about to read 5, iclass 31, count 2 2006.201.02:12:59.34#ibcon#read 5, iclass 31, count 2 2006.201.02:12:59.34#ibcon#about to read 6, iclass 31, count 2 2006.201.02:12:59.34#ibcon#read 6, iclass 31, count 2 2006.201.02:12:59.34#ibcon#end of sib2, iclass 31, count 2 2006.201.02:12:59.34#ibcon#*mode == 0, iclass 31, count 2 2006.201.02:12:59.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.02:12:59.34#ibcon#[27=AT07-04\r\n] 2006.201.02:12:59.34#ibcon#*before write, iclass 31, count 2 2006.201.02:12:59.34#ibcon#enter sib2, iclass 31, count 2 2006.201.02:12:59.34#ibcon#flushed, iclass 31, count 2 2006.201.02:12:59.34#ibcon#about to write, iclass 31, count 2 2006.201.02:12:59.34#ibcon#wrote, iclass 31, count 2 2006.201.02:12:59.34#ibcon#about to read 3, iclass 31, count 2 2006.201.02:12:59.37#ibcon#read 3, iclass 31, count 2 2006.201.02:12:59.37#ibcon#about to read 4, iclass 31, count 2 2006.201.02:12:59.37#ibcon#read 4, iclass 31, count 2 2006.201.02:12:59.37#ibcon#about to read 5, iclass 31, count 2 2006.201.02:12:59.37#ibcon#read 5, iclass 31, count 2 2006.201.02:12:59.37#ibcon#about to read 6, iclass 31, count 2 2006.201.02:12:59.37#ibcon#read 6, iclass 31, count 2 2006.201.02:12:59.37#ibcon#end of sib2, iclass 31, count 2 2006.201.02:12:59.37#ibcon#*after write, iclass 31, count 2 2006.201.02:12:59.37#ibcon#*before return 0, iclass 31, count 2 2006.201.02:12:59.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:59.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:12:59.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.02:12:59.37#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:59.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:59.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:59.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:59.49#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:12:59.49#ibcon#first serial, iclass 31, count 0 2006.201.02:12:59.49#ibcon#enter sib2, iclass 31, count 0 2006.201.02:12:59.49#ibcon#flushed, iclass 31, count 0 2006.201.02:12:59.49#ibcon#about to write, iclass 31, count 0 2006.201.02:12:59.49#ibcon#wrote, iclass 31, count 0 2006.201.02:12:59.49#ibcon#about to read 3, iclass 31, count 0 2006.201.02:12:59.51#ibcon#read 3, iclass 31, count 0 2006.201.02:12:59.51#ibcon#about to read 4, iclass 31, count 0 2006.201.02:12:59.51#ibcon#read 4, iclass 31, count 0 2006.201.02:12:59.51#ibcon#about to read 5, iclass 31, count 0 2006.201.02:12:59.51#ibcon#read 5, iclass 31, count 0 2006.201.02:12:59.51#ibcon#about to read 6, iclass 31, count 0 2006.201.02:12:59.51#ibcon#read 6, iclass 31, count 0 2006.201.02:12:59.51#ibcon#end of sib2, iclass 31, count 0 2006.201.02:12:59.51#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:12:59.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:12:59.51#ibcon#[27=USB\r\n] 2006.201.02:12:59.51#ibcon#*before write, iclass 31, count 0 2006.201.02:12:59.51#ibcon#enter sib2, iclass 31, count 0 2006.201.02:12:59.51#ibcon#flushed, iclass 31, count 0 2006.201.02:12:59.51#ibcon#about to write, iclass 31, count 0 2006.201.02:12:59.51#ibcon#wrote, iclass 31, count 0 2006.201.02:12:59.51#ibcon#about to read 3, iclass 31, count 0 2006.201.02:12:59.54#ibcon#read 3, iclass 31, count 0 2006.201.02:12:59.54#ibcon#about to read 4, iclass 31, count 0 2006.201.02:12:59.54#ibcon#read 4, iclass 31, count 0 2006.201.02:12:59.54#ibcon#about to read 5, iclass 31, count 0 2006.201.02:12:59.54#ibcon#read 5, iclass 31, count 0 2006.201.02:12:59.54#ibcon#about to read 6, iclass 31, count 0 2006.201.02:12:59.54#ibcon#read 6, iclass 31, count 0 2006.201.02:12:59.54#ibcon#end of sib2, iclass 31, count 0 2006.201.02:12:59.54#ibcon#*after write, iclass 31, count 0 2006.201.02:12:59.54#ibcon#*before return 0, iclass 31, count 0 2006.201.02:12:59.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:59.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:12:59.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:12:59.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:12:59.54$vck44/vblo=8,744.99 2006.201.02:12:59.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.02:12:59.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.02:12:59.54#ibcon#ireg 17 cls_cnt 0 2006.201.02:12:59.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:59.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:59.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:59.54#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:12:59.54#ibcon#first serial, iclass 33, count 0 2006.201.02:12:59.54#ibcon#enter sib2, iclass 33, count 0 2006.201.02:12:59.54#ibcon#flushed, iclass 33, count 0 2006.201.02:12:59.54#ibcon#about to write, iclass 33, count 0 2006.201.02:12:59.54#ibcon#wrote, iclass 33, count 0 2006.201.02:12:59.54#ibcon#about to read 3, iclass 33, count 0 2006.201.02:12:59.56#ibcon#read 3, iclass 33, count 0 2006.201.02:12:59.56#ibcon#about to read 4, iclass 33, count 0 2006.201.02:12:59.56#ibcon#read 4, iclass 33, count 0 2006.201.02:12:59.56#ibcon#about to read 5, iclass 33, count 0 2006.201.02:12:59.56#ibcon#read 5, iclass 33, count 0 2006.201.02:12:59.56#ibcon#about to read 6, iclass 33, count 0 2006.201.02:12:59.56#ibcon#read 6, iclass 33, count 0 2006.201.02:12:59.56#ibcon#end of sib2, iclass 33, count 0 2006.201.02:12:59.56#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:12:59.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:12:59.56#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:12:59.56#ibcon#*before write, iclass 33, count 0 2006.201.02:12:59.56#ibcon#enter sib2, iclass 33, count 0 2006.201.02:12:59.56#ibcon#flushed, iclass 33, count 0 2006.201.02:12:59.56#ibcon#about to write, iclass 33, count 0 2006.201.02:12:59.56#ibcon#wrote, iclass 33, count 0 2006.201.02:12:59.56#ibcon#about to read 3, iclass 33, count 0 2006.201.02:12:59.60#ibcon#read 3, iclass 33, count 0 2006.201.02:12:59.60#ibcon#about to read 4, iclass 33, count 0 2006.201.02:12:59.60#ibcon#read 4, iclass 33, count 0 2006.201.02:12:59.60#ibcon#about to read 5, iclass 33, count 0 2006.201.02:12:59.60#ibcon#read 5, iclass 33, count 0 2006.201.02:12:59.60#ibcon#about to read 6, iclass 33, count 0 2006.201.02:12:59.60#ibcon#read 6, iclass 33, count 0 2006.201.02:12:59.60#ibcon#end of sib2, iclass 33, count 0 2006.201.02:12:59.60#ibcon#*after write, iclass 33, count 0 2006.201.02:12:59.60#ibcon#*before return 0, iclass 33, count 0 2006.201.02:12:59.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:59.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:12:59.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:12:59.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:12:59.60$vck44/vb=8,4 2006.201.02:12:59.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.02:12:59.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.02:12:59.60#ibcon#ireg 11 cls_cnt 2 2006.201.02:12:59.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:59.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:59.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:59.66#ibcon#enter wrdev, iclass 35, count 2 2006.201.02:12:59.66#ibcon#first serial, iclass 35, count 2 2006.201.02:12:59.66#ibcon#enter sib2, iclass 35, count 2 2006.201.02:12:59.66#ibcon#flushed, iclass 35, count 2 2006.201.02:12:59.66#ibcon#about to write, iclass 35, count 2 2006.201.02:12:59.66#ibcon#wrote, iclass 35, count 2 2006.201.02:12:59.66#ibcon#about to read 3, iclass 35, count 2 2006.201.02:12:59.68#ibcon#read 3, iclass 35, count 2 2006.201.02:12:59.68#ibcon#about to read 4, iclass 35, count 2 2006.201.02:12:59.68#ibcon#read 4, iclass 35, count 2 2006.201.02:12:59.68#ibcon#about to read 5, iclass 35, count 2 2006.201.02:12:59.68#ibcon#read 5, iclass 35, count 2 2006.201.02:12:59.68#ibcon#about to read 6, iclass 35, count 2 2006.201.02:12:59.68#ibcon#read 6, iclass 35, count 2 2006.201.02:12:59.68#ibcon#end of sib2, iclass 35, count 2 2006.201.02:12:59.68#ibcon#*mode == 0, iclass 35, count 2 2006.201.02:12:59.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.02:12:59.68#ibcon#[27=AT08-04\r\n] 2006.201.02:12:59.68#ibcon#*before write, iclass 35, count 2 2006.201.02:12:59.68#ibcon#enter sib2, iclass 35, count 2 2006.201.02:12:59.68#ibcon#flushed, iclass 35, count 2 2006.201.02:12:59.68#ibcon#about to write, iclass 35, count 2 2006.201.02:12:59.68#ibcon#wrote, iclass 35, count 2 2006.201.02:12:59.68#ibcon#about to read 3, iclass 35, count 2 2006.201.02:12:59.72#ibcon#read 3, iclass 35, count 2 2006.201.02:12:59.72#ibcon#about to read 4, iclass 35, count 2 2006.201.02:12:59.72#ibcon#read 4, iclass 35, count 2 2006.201.02:12:59.72#ibcon#about to read 5, iclass 35, count 2 2006.201.02:12:59.72#ibcon#read 5, iclass 35, count 2 2006.201.02:12:59.72#ibcon#about to read 6, iclass 35, count 2 2006.201.02:12:59.72#ibcon#read 6, iclass 35, count 2 2006.201.02:12:59.72#ibcon#end of sib2, iclass 35, count 2 2006.201.02:12:59.72#ibcon#*after write, iclass 35, count 2 2006.201.02:12:59.72#ibcon#*before return 0, iclass 35, count 2 2006.201.02:12:59.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:59.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:12:59.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.02:12:59.72#ibcon#ireg 7 cls_cnt 0 2006.201.02:12:59.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:59.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:59.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:59.84#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:12:59.84#ibcon#first serial, iclass 35, count 0 2006.201.02:12:59.84#ibcon#enter sib2, iclass 35, count 0 2006.201.02:12:59.84#ibcon#flushed, iclass 35, count 0 2006.201.02:12:59.84#ibcon#about to write, iclass 35, count 0 2006.201.02:12:59.84#ibcon#wrote, iclass 35, count 0 2006.201.02:12:59.84#ibcon#about to read 3, iclass 35, count 0 2006.201.02:12:59.86#ibcon#read 3, iclass 35, count 0 2006.201.02:12:59.86#ibcon#about to read 4, iclass 35, count 0 2006.201.02:12:59.86#ibcon#read 4, iclass 35, count 0 2006.201.02:12:59.86#ibcon#about to read 5, iclass 35, count 0 2006.201.02:12:59.86#ibcon#read 5, iclass 35, count 0 2006.201.02:12:59.86#ibcon#about to read 6, iclass 35, count 0 2006.201.02:12:59.86#ibcon#read 6, iclass 35, count 0 2006.201.02:12:59.86#ibcon#end of sib2, iclass 35, count 0 2006.201.02:12:59.86#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:12:59.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:12:59.86#ibcon#[27=USB\r\n] 2006.201.02:12:59.86#ibcon#*before write, iclass 35, count 0 2006.201.02:12:59.86#ibcon#enter sib2, iclass 35, count 0 2006.201.02:12:59.86#ibcon#flushed, iclass 35, count 0 2006.201.02:12:59.86#ibcon#about to write, iclass 35, count 0 2006.201.02:12:59.86#ibcon#wrote, iclass 35, count 0 2006.201.02:12:59.86#ibcon#about to read 3, iclass 35, count 0 2006.201.02:12:59.89#ibcon#read 3, iclass 35, count 0 2006.201.02:12:59.89#ibcon#about to read 4, iclass 35, count 0 2006.201.02:12:59.89#ibcon#read 4, iclass 35, count 0 2006.201.02:12:59.89#ibcon#about to read 5, iclass 35, count 0 2006.201.02:12:59.89#ibcon#read 5, iclass 35, count 0 2006.201.02:12:59.89#ibcon#about to read 6, iclass 35, count 0 2006.201.02:12:59.89#ibcon#read 6, iclass 35, count 0 2006.201.02:12:59.89#ibcon#end of sib2, iclass 35, count 0 2006.201.02:12:59.89#ibcon#*after write, iclass 35, count 0 2006.201.02:12:59.89#ibcon#*before return 0, iclass 35, count 0 2006.201.02:12:59.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:59.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:12:59.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:12:59.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:12:59.89$vck44/vabw=wide 2006.201.02:12:59.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.02:12:59.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.02:12:59.89#ibcon#ireg 8 cls_cnt 0 2006.201.02:12:59.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:12:59.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:12:59.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:12:59.89#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:12:59.89#ibcon#first serial, iclass 37, count 0 2006.201.02:12:59.89#ibcon#enter sib2, iclass 37, count 0 2006.201.02:12:59.89#ibcon#flushed, iclass 37, count 0 2006.201.02:12:59.89#ibcon#about to write, iclass 37, count 0 2006.201.02:12:59.89#ibcon#wrote, iclass 37, count 0 2006.201.02:12:59.89#ibcon#about to read 3, iclass 37, count 0 2006.201.02:12:59.91#ibcon#read 3, iclass 37, count 0 2006.201.02:12:59.91#ibcon#about to read 4, iclass 37, count 0 2006.201.02:12:59.91#ibcon#read 4, iclass 37, count 0 2006.201.02:12:59.91#ibcon#about to read 5, iclass 37, count 0 2006.201.02:12:59.91#ibcon#read 5, iclass 37, count 0 2006.201.02:12:59.91#ibcon#about to read 6, iclass 37, count 0 2006.201.02:12:59.91#ibcon#read 6, iclass 37, count 0 2006.201.02:12:59.91#ibcon#end of sib2, iclass 37, count 0 2006.201.02:12:59.91#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:12:59.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:12:59.91#ibcon#[25=BW32\r\n] 2006.201.02:12:59.91#ibcon#*before write, iclass 37, count 0 2006.201.02:12:59.91#ibcon#enter sib2, iclass 37, count 0 2006.201.02:12:59.91#ibcon#flushed, iclass 37, count 0 2006.201.02:12:59.91#ibcon#about to write, iclass 37, count 0 2006.201.02:12:59.91#ibcon#wrote, iclass 37, count 0 2006.201.02:12:59.91#ibcon#about to read 3, iclass 37, count 0 2006.201.02:12:59.94#ibcon#read 3, iclass 37, count 0 2006.201.02:12:59.94#ibcon#about to read 4, iclass 37, count 0 2006.201.02:12:59.94#ibcon#read 4, iclass 37, count 0 2006.201.02:12:59.94#ibcon#about to read 5, iclass 37, count 0 2006.201.02:12:59.94#ibcon#read 5, iclass 37, count 0 2006.201.02:12:59.94#ibcon#about to read 6, iclass 37, count 0 2006.201.02:12:59.94#ibcon#read 6, iclass 37, count 0 2006.201.02:12:59.94#ibcon#end of sib2, iclass 37, count 0 2006.201.02:12:59.94#ibcon#*after write, iclass 37, count 0 2006.201.02:12:59.94#ibcon#*before return 0, iclass 37, count 0 2006.201.02:12:59.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:12:59.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:12:59.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:12:59.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:12:59.94$vck44/vbbw=wide 2006.201.02:12:59.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.02:12:59.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.02:12:59.94#ibcon#ireg 8 cls_cnt 0 2006.201.02:12:59.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:13:00.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:13:00.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:13:00.01#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:13:00.01#ibcon#first serial, iclass 39, count 0 2006.201.02:13:00.01#ibcon#enter sib2, iclass 39, count 0 2006.201.02:13:00.01#ibcon#flushed, iclass 39, count 0 2006.201.02:13:00.01#ibcon#about to write, iclass 39, count 0 2006.201.02:13:00.01#ibcon#wrote, iclass 39, count 0 2006.201.02:13:00.01#ibcon#about to read 3, iclass 39, count 0 2006.201.02:13:00.03#ibcon#read 3, iclass 39, count 0 2006.201.02:13:00.03#ibcon#about to read 4, iclass 39, count 0 2006.201.02:13:00.03#ibcon#read 4, iclass 39, count 0 2006.201.02:13:00.03#ibcon#about to read 5, iclass 39, count 0 2006.201.02:13:00.03#ibcon#read 5, iclass 39, count 0 2006.201.02:13:00.03#ibcon#about to read 6, iclass 39, count 0 2006.201.02:13:00.03#ibcon#read 6, iclass 39, count 0 2006.201.02:13:00.03#ibcon#end of sib2, iclass 39, count 0 2006.201.02:13:00.03#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:13:00.03#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:13:00.03#ibcon#[27=BW32\r\n] 2006.201.02:13:00.03#ibcon#*before write, iclass 39, count 0 2006.201.02:13:00.03#ibcon#enter sib2, iclass 39, count 0 2006.201.02:13:00.03#ibcon#flushed, iclass 39, count 0 2006.201.02:13:00.03#ibcon#about to write, iclass 39, count 0 2006.201.02:13:00.03#ibcon#wrote, iclass 39, count 0 2006.201.02:13:00.03#ibcon#about to read 3, iclass 39, count 0 2006.201.02:13:00.06#ibcon#read 3, iclass 39, count 0 2006.201.02:13:00.06#ibcon#about to read 4, iclass 39, count 0 2006.201.02:13:00.06#ibcon#read 4, iclass 39, count 0 2006.201.02:13:00.06#ibcon#about to read 5, iclass 39, count 0 2006.201.02:13:00.06#ibcon#read 5, iclass 39, count 0 2006.201.02:13:00.06#ibcon#about to read 6, iclass 39, count 0 2006.201.02:13:00.06#ibcon#read 6, iclass 39, count 0 2006.201.02:13:00.06#ibcon#end of sib2, iclass 39, count 0 2006.201.02:13:00.06#ibcon#*after write, iclass 39, count 0 2006.201.02:13:00.06#ibcon#*before return 0, iclass 39, count 0 2006.201.02:13:00.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:13:00.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:13:00.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:13:00.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:13:00.06$setupk4/ifdk4 2006.201.02:13:00.06$ifdk4/lo= 2006.201.02:13:00.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:13:00.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:13:00.06$ifdk4/patch= 2006.201.02:13:00.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:13:00.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:13:00.06$setupk4/!*+20s 2006.201.02:13:07.20#abcon#<5=/04 3.0 5.8 22.91 911005.3\r\n> 2006.201.02:13:07.22#abcon#{5=INTERFACE CLEAR} 2006.201.02:13:07.28#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:13:14.52$setupk4/"tpicd 2006.201.02:13:14.52$setupk4/echo=off 2006.201.02:13:14.52$setupk4/xlog=off 2006.201.02:13:14.52:!2006.201.02:15:11 2006.201.02:13:16.14#trakl#Source acquired 2006.201.02:13:17.14#flagr#flagr/antenna,acquired 2006.201.02:15:11.00:preob 2006.201.02:15:12.13/onsource/TRACKING 2006.201.02:15:12.13:!2006.201.02:15:21 2006.201.02:15:21.00:"tape 2006.201.02:15:21.00:"st=record 2006.201.02:15:21.00:data_valid=on 2006.201.02:15:21.00:midob 2006.201.02:15:21.13/onsource/TRACKING 2006.201.02:15:21.13/wx/22.90,1005.3,92 2006.201.02:15:21.20/cable/+6.4666E-03 2006.201.02:15:22.29/va/01,08,usb,yes,41,44 2006.201.02:15:22.29/va/02,07,usb,yes,44,45 2006.201.02:15:22.29/va/03,08,usb,yes,40,42 2006.201.02:15:22.29/va/04,07,usb,yes,46,48 2006.201.02:15:22.29/va/05,04,usb,yes,40,41 2006.201.02:15:22.29/va/06,05,usb,yes,41,41 2006.201.02:15:22.29/va/07,05,usb,yes,40,41 2006.201.02:15:22.29/va/08,04,usb,yes,40,47 2006.201.02:15:22.52/valo/01,524.99,yes,locked 2006.201.02:15:22.52/valo/02,534.99,yes,locked 2006.201.02:15:22.52/valo/03,564.99,yes,locked 2006.201.02:15:22.52/valo/04,624.99,yes,locked 2006.201.02:15:22.52/valo/05,734.99,yes,locked 2006.201.02:15:22.52/valo/06,814.99,yes,locked 2006.201.02:15:22.52/valo/07,864.99,yes,locked 2006.201.02:15:22.52/valo/08,884.99,yes,locked 2006.201.02:15:23.61/vb/01,04,usb,yes,35,32 2006.201.02:15:23.61/vb/02,05,usb,yes,33,32 2006.201.02:15:23.61/vb/03,04,usb,yes,34,37 2006.201.02:15:23.61/vb/04,05,usb,yes,34,33 2006.201.02:15:23.61/vb/05,04,usb,yes,31,33 2006.201.02:15:23.61/vb/06,04,usb,yes,36,31 2006.201.02:15:23.61/vb/07,04,usb,yes,35,35 2006.201.02:15:23.61/vb/08,04,usb,yes,33,36 2006.201.02:15:23.84/vblo/01,629.99,yes,locked 2006.201.02:15:23.84/vblo/02,634.99,yes,locked 2006.201.02:15:23.84/vblo/03,649.99,yes,locked 2006.201.02:15:23.84/vblo/04,679.99,yes,locked 2006.201.02:15:23.84/vblo/05,709.99,yes,locked 2006.201.02:15:23.84/vblo/06,719.99,yes,locked 2006.201.02:15:23.84/vblo/07,734.99,yes,locked 2006.201.02:15:23.84/vblo/08,744.99,yes,locked 2006.201.02:15:23.99/vabw/8 2006.201.02:15:24.14/vbbw/8 2006.201.02:15:24.23/xfe/off,on,15.5 2006.201.02:15:24.60/ifatt/23,28,28,28 2006.201.02:15:25.04/fmout-gps/S +4.44E-07 2006.201.02:15:25.09:!2006.201.02:16:01 2006.201.02:16:01.00:data_valid=off 2006.201.02:16:01.00:"et 2006.201.02:16:01.00:!+3s 2006.201.02:16:04.01:"tape 2006.201.02:16:04.01:postob 2006.201.02:16:04.16/cable/+6.4682E-03 2006.201.02:16:04.16/wx/22.90,1005.3,92 2006.201.02:16:04.22/fmout-gps/S +4.44E-07 2006.201.02:16:04.22:scan_name=201-0220,jd0607,110 2006.201.02:16:04.22:source=3c274,123049.42,122328.0,2000.0,ccw 2006.201.02:16:06.13#flagr#flagr/antenna,new-source 2006.201.02:16:06.13:checkk5 2006.201.02:16:06.55/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:16:07.01/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:16:07.43/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:16:07.84/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:16:08.45/chk_obsdata//k5ts1/T2010215??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.02:16:08.88/chk_obsdata//k5ts2/T2010215??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.02:16:09.32/chk_obsdata//k5ts3/T2010215??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.02:16:09.74/chk_obsdata//k5ts4/T2010215??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.02:16:10.57/k5log//k5ts1_log_newline 2006.201.02:16:11.36/k5log//k5ts2_log_newline 2006.201.02:16:12.39/k5log//k5ts3_log_newline 2006.201.02:16:13.16/k5log//k5ts4_log_newline 2006.201.02:16:13.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:16:13.22:setupk4=1 2006.201.02:16:13.22$setupk4/echo=on 2006.201.02:16:13.22$setupk4/pcalon 2006.201.02:16:13.22$pcalon/"no phase cal control is implemented here 2006.201.02:16:13.22$setupk4/"tpicd=stop 2006.201.02:16:13.22$setupk4/"rec=synch_on 2006.201.02:16:13.22$setupk4/"rec_mode=128 2006.201.02:16:13.22$setupk4/!* 2006.201.02:16:13.22$setupk4/recpk4 2006.201.02:16:13.22$recpk4/recpatch= 2006.201.02:16:13.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:16:13.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:16:13.22$setupk4/vck44 2006.201.02:16:13.22$vck44/valo=1,524.99 2006.201.02:16:13.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.02:16:13.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.02:16:13.23#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:13.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:13.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:13.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:13.23#ibcon#enter wrdev, iclass 12, count 0 2006.201.02:16:13.23#ibcon#first serial, iclass 12, count 0 2006.201.02:16:13.23#ibcon#enter sib2, iclass 12, count 0 2006.201.02:16:13.23#ibcon#flushed, iclass 12, count 0 2006.201.02:16:13.23#ibcon#about to write, iclass 12, count 0 2006.201.02:16:13.23#ibcon#wrote, iclass 12, count 0 2006.201.02:16:13.23#ibcon#about to read 3, iclass 12, count 0 2006.201.02:16:13.25#ibcon#read 3, iclass 12, count 0 2006.201.02:16:13.25#ibcon#about to read 4, iclass 12, count 0 2006.201.02:16:13.25#ibcon#read 4, iclass 12, count 0 2006.201.02:16:13.25#ibcon#about to read 5, iclass 12, count 0 2006.201.02:16:13.25#ibcon#read 5, iclass 12, count 0 2006.201.02:16:13.25#ibcon#about to read 6, iclass 12, count 0 2006.201.02:16:13.25#ibcon#read 6, iclass 12, count 0 2006.201.02:16:13.25#ibcon#end of sib2, iclass 12, count 0 2006.201.02:16:13.25#ibcon#*mode == 0, iclass 12, count 0 2006.201.02:16:13.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.02:16:13.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:16:13.25#ibcon#*before write, iclass 12, count 0 2006.201.02:16:13.25#ibcon#enter sib2, iclass 12, count 0 2006.201.02:16:13.25#ibcon#flushed, iclass 12, count 0 2006.201.02:16:13.25#ibcon#about to write, iclass 12, count 0 2006.201.02:16:13.25#ibcon#wrote, iclass 12, count 0 2006.201.02:16:13.25#ibcon#about to read 3, iclass 12, count 0 2006.201.02:16:13.30#ibcon#read 3, iclass 12, count 0 2006.201.02:16:13.30#ibcon#about to read 4, iclass 12, count 0 2006.201.02:16:13.30#ibcon#read 4, iclass 12, count 0 2006.201.02:16:13.30#ibcon#about to read 5, iclass 12, count 0 2006.201.02:16:13.30#ibcon#read 5, iclass 12, count 0 2006.201.02:16:13.30#ibcon#about to read 6, iclass 12, count 0 2006.201.02:16:13.30#ibcon#read 6, iclass 12, count 0 2006.201.02:16:13.30#ibcon#end of sib2, iclass 12, count 0 2006.201.02:16:13.30#ibcon#*after write, iclass 12, count 0 2006.201.02:16:13.30#ibcon#*before return 0, iclass 12, count 0 2006.201.02:16:13.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:13.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:13.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.02:16:13.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.02:16:13.30$vck44/va=1,8 2006.201.02:16:13.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.02:16:13.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.02:16:13.30#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:13.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:13.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:13.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:13.30#ibcon#enter wrdev, iclass 14, count 2 2006.201.02:16:13.30#ibcon#first serial, iclass 14, count 2 2006.201.02:16:13.30#ibcon#enter sib2, iclass 14, count 2 2006.201.02:16:13.30#ibcon#flushed, iclass 14, count 2 2006.201.02:16:13.30#ibcon#about to write, iclass 14, count 2 2006.201.02:16:13.30#ibcon#wrote, iclass 14, count 2 2006.201.02:16:13.30#ibcon#about to read 3, iclass 14, count 2 2006.201.02:16:13.32#ibcon#read 3, iclass 14, count 2 2006.201.02:16:13.32#ibcon#about to read 4, iclass 14, count 2 2006.201.02:16:13.32#ibcon#read 4, iclass 14, count 2 2006.201.02:16:13.32#ibcon#about to read 5, iclass 14, count 2 2006.201.02:16:13.32#ibcon#read 5, iclass 14, count 2 2006.201.02:16:13.32#ibcon#about to read 6, iclass 14, count 2 2006.201.02:16:13.32#ibcon#read 6, iclass 14, count 2 2006.201.02:16:13.32#ibcon#end of sib2, iclass 14, count 2 2006.201.02:16:13.32#ibcon#*mode == 0, iclass 14, count 2 2006.201.02:16:13.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.02:16:13.32#ibcon#[25=AT01-08\r\n] 2006.201.02:16:13.32#ibcon#*before write, iclass 14, count 2 2006.201.02:16:13.32#ibcon#enter sib2, iclass 14, count 2 2006.201.02:16:13.32#ibcon#flushed, iclass 14, count 2 2006.201.02:16:13.32#ibcon#about to write, iclass 14, count 2 2006.201.02:16:13.32#ibcon#wrote, iclass 14, count 2 2006.201.02:16:13.32#ibcon#about to read 3, iclass 14, count 2 2006.201.02:16:13.35#ibcon#read 3, iclass 14, count 2 2006.201.02:16:13.35#ibcon#about to read 4, iclass 14, count 2 2006.201.02:16:13.35#ibcon#read 4, iclass 14, count 2 2006.201.02:16:13.35#ibcon#about to read 5, iclass 14, count 2 2006.201.02:16:13.35#ibcon#read 5, iclass 14, count 2 2006.201.02:16:13.35#ibcon#about to read 6, iclass 14, count 2 2006.201.02:16:13.35#ibcon#read 6, iclass 14, count 2 2006.201.02:16:13.35#ibcon#end of sib2, iclass 14, count 2 2006.201.02:16:13.35#ibcon#*after write, iclass 14, count 2 2006.201.02:16:13.35#ibcon#*before return 0, iclass 14, count 2 2006.201.02:16:13.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:13.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:13.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.02:16:13.35#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:13.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:13.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:13.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:13.47#ibcon#enter wrdev, iclass 14, count 0 2006.201.02:16:13.47#ibcon#first serial, iclass 14, count 0 2006.201.02:16:13.47#ibcon#enter sib2, iclass 14, count 0 2006.201.02:16:13.47#ibcon#flushed, iclass 14, count 0 2006.201.02:16:13.47#ibcon#about to write, iclass 14, count 0 2006.201.02:16:13.47#ibcon#wrote, iclass 14, count 0 2006.201.02:16:13.47#ibcon#about to read 3, iclass 14, count 0 2006.201.02:16:13.49#ibcon#read 3, iclass 14, count 0 2006.201.02:16:13.49#ibcon#about to read 4, iclass 14, count 0 2006.201.02:16:13.49#ibcon#read 4, iclass 14, count 0 2006.201.02:16:13.49#ibcon#about to read 5, iclass 14, count 0 2006.201.02:16:13.49#ibcon#read 5, iclass 14, count 0 2006.201.02:16:13.49#ibcon#about to read 6, iclass 14, count 0 2006.201.02:16:13.49#ibcon#read 6, iclass 14, count 0 2006.201.02:16:13.49#ibcon#end of sib2, iclass 14, count 0 2006.201.02:16:13.49#ibcon#*mode == 0, iclass 14, count 0 2006.201.02:16:13.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.02:16:13.49#ibcon#[25=USB\r\n] 2006.201.02:16:13.49#ibcon#*before write, iclass 14, count 0 2006.201.02:16:13.49#ibcon#enter sib2, iclass 14, count 0 2006.201.02:16:13.49#ibcon#flushed, iclass 14, count 0 2006.201.02:16:13.49#ibcon#about to write, iclass 14, count 0 2006.201.02:16:13.49#ibcon#wrote, iclass 14, count 0 2006.201.02:16:13.49#ibcon#about to read 3, iclass 14, count 0 2006.201.02:16:13.52#ibcon#read 3, iclass 14, count 0 2006.201.02:16:13.52#ibcon#about to read 4, iclass 14, count 0 2006.201.02:16:13.52#ibcon#read 4, iclass 14, count 0 2006.201.02:16:13.52#ibcon#about to read 5, iclass 14, count 0 2006.201.02:16:13.52#ibcon#read 5, iclass 14, count 0 2006.201.02:16:13.52#ibcon#about to read 6, iclass 14, count 0 2006.201.02:16:13.52#ibcon#read 6, iclass 14, count 0 2006.201.02:16:13.52#ibcon#end of sib2, iclass 14, count 0 2006.201.02:16:13.52#ibcon#*after write, iclass 14, count 0 2006.201.02:16:13.52#ibcon#*before return 0, iclass 14, count 0 2006.201.02:16:13.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:13.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:13.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.02:16:13.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.02:16:13.52$vck44/valo=2,534.99 2006.201.02:16:13.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.02:16:13.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.02:16:13.52#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:13.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:13.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:13.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:13.52#ibcon#enter wrdev, iclass 16, count 0 2006.201.02:16:13.52#ibcon#first serial, iclass 16, count 0 2006.201.02:16:13.52#ibcon#enter sib2, iclass 16, count 0 2006.201.02:16:13.52#ibcon#flushed, iclass 16, count 0 2006.201.02:16:13.52#ibcon#about to write, iclass 16, count 0 2006.201.02:16:13.52#ibcon#wrote, iclass 16, count 0 2006.201.02:16:13.52#ibcon#about to read 3, iclass 16, count 0 2006.201.02:16:13.54#ibcon#read 3, iclass 16, count 0 2006.201.02:16:13.54#ibcon#about to read 4, iclass 16, count 0 2006.201.02:16:13.54#ibcon#read 4, iclass 16, count 0 2006.201.02:16:13.54#ibcon#about to read 5, iclass 16, count 0 2006.201.02:16:13.54#ibcon#read 5, iclass 16, count 0 2006.201.02:16:13.54#ibcon#about to read 6, iclass 16, count 0 2006.201.02:16:13.54#ibcon#read 6, iclass 16, count 0 2006.201.02:16:13.54#ibcon#end of sib2, iclass 16, count 0 2006.201.02:16:13.54#ibcon#*mode == 0, iclass 16, count 0 2006.201.02:16:13.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.02:16:13.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:16:13.54#ibcon#*before write, iclass 16, count 0 2006.201.02:16:13.54#ibcon#enter sib2, iclass 16, count 0 2006.201.02:16:13.54#ibcon#flushed, iclass 16, count 0 2006.201.02:16:13.54#ibcon#about to write, iclass 16, count 0 2006.201.02:16:13.54#ibcon#wrote, iclass 16, count 0 2006.201.02:16:13.54#ibcon#about to read 3, iclass 16, count 0 2006.201.02:16:13.59#ibcon#read 3, iclass 16, count 0 2006.201.02:16:13.59#ibcon#about to read 4, iclass 16, count 0 2006.201.02:16:13.59#ibcon#read 4, iclass 16, count 0 2006.201.02:16:13.59#ibcon#about to read 5, iclass 16, count 0 2006.201.02:16:13.59#ibcon#read 5, iclass 16, count 0 2006.201.02:16:13.59#ibcon#about to read 6, iclass 16, count 0 2006.201.02:16:13.59#ibcon#read 6, iclass 16, count 0 2006.201.02:16:13.59#ibcon#end of sib2, iclass 16, count 0 2006.201.02:16:13.59#ibcon#*after write, iclass 16, count 0 2006.201.02:16:13.59#ibcon#*before return 0, iclass 16, count 0 2006.201.02:16:13.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:13.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:13.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.02:16:13.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.02:16:13.59$vck44/va=2,7 2006.201.02:16:13.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.02:16:13.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.02:16:13.59#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:13.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:13.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:13.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:13.64#ibcon#enter wrdev, iclass 18, count 2 2006.201.02:16:13.64#ibcon#first serial, iclass 18, count 2 2006.201.02:16:13.64#ibcon#enter sib2, iclass 18, count 2 2006.201.02:16:13.64#ibcon#flushed, iclass 18, count 2 2006.201.02:16:13.64#ibcon#about to write, iclass 18, count 2 2006.201.02:16:13.64#ibcon#wrote, iclass 18, count 2 2006.201.02:16:13.64#ibcon#about to read 3, iclass 18, count 2 2006.201.02:16:13.66#ibcon#read 3, iclass 18, count 2 2006.201.02:16:13.66#ibcon#about to read 4, iclass 18, count 2 2006.201.02:16:13.66#ibcon#read 4, iclass 18, count 2 2006.201.02:16:13.66#ibcon#about to read 5, iclass 18, count 2 2006.201.02:16:13.66#ibcon#read 5, iclass 18, count 2 2006.201.02:16:13.66#ibcon#about to read 6, iclass 18, count 2 2006.201.02:16:13.66#ibcon#read 6, iclass 18, count 2 2006.201.02:16:13.66#ibcon#end of sib2, iclass 18, count 2 2006.201.02:16:13.66#ibcon#*mode == 0, iclass 18, count 2 2006.201.02:16:13.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.02:16:13.66#ibcon#[25=AT02-07\r\n] 2006.201.02:16:13.66#ibcon#*before write, iclass 18, count 2 2006.201.02:16:13.66#ibcon#enter sib2, iclass 18, count 2 2006.201.02:16:13.66#ibcon#flushed, iclass 18, count 2 2006.201.02:16:13.66#ibcon#about to write, iclass 18, count 2 2006.201.02:16:13.66#ibcon#wrote, iclass 18, count 2 2006.201.02:16:13.66#ibcon#about to read 3, iclass 18, count 2 2006.201.02:16:13.69#ibcon#read 3, iclass 18, count 2 2006.201.02:16:13.69#ibcon#about to read 4, iclass 18, count 2 2006.201.02:16:13.69#ibcon#read 4, iclass 18, count 2 2006.201.02:16:13.69#ibcon#about to read 5, iclass 18, count 2 2006.201.02:16:13.69#ibcon#read 5, iclass 18, count 2 2006.201.02:16:13.69#ibcon#about to read 6, iclass 18, count 2 2006.201.02:16:13.69#ibcon#read 6, iclass 18, count 2 2006.201.02:16:13.69#ibcon#end of sib2, iclass 18, count 2 2006.201.02:16:13.69#ibcon#*after write, iclass 18, count 2 2006.201.02:16:13.69#ibcon#*before return 0, iclass 18, count 2 2006.201.02:16:13.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:13.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:13.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.02:16:13.69#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:13.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:13.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:13.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:13.81#ibcon#enter wrdev, iclass 18, count 0 2006.201.02:16:13.81#ibcon#first serial, iclass 18, count 0 2006.201.02:16:13.81#ibcon#enter sib2, iclass 18, count 0 2006.201.02:16:13.81#ibcon#flushed, iclass 18, count 0 2006.201.02:16:13.81#ibcon#about to write, iclass 18, count 0 2006.201.02:16:13.81#ibcon#wrote, iclass 18, count 0 2006.201.02:16:13.81#ibcon#about to read 3, iclass 18, count 0 2006.201.02:16:13.83#ibcon#read 3, iclass 18, count 0 2006.201.02:16:13.83#ibcon#about to read 4, iclass 18, count 0 2006.201.02:16:13.83#ibcon#read 4, iclass 18, count 0 2006.201.02:16:13.83#ibcon#about to read 5, iclass 18, count 0 2006.201.02:16:13.83#ibcon#read 5, iclass 18, count 0 2006.201.02:16:13.83#ibcon#about to read 6, iclass 18, count 0 2006.201.02:16:13.83#ibcon#read 6, iclass 18, count 0 2006.201.02:16:13.83#ibcon#end of sib2, iclass 18, count 0 2006.201.02:16:13.83#ibcon#*mode == 0, iclass 18, count 0 2006.201.02:16:13.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.02:16:13.83#ibcon#[25=USB\r\n] 2006.201.02:16:13.83#ibcon#*before write, iclass 18, count 0 2006.201.02:16:13.83#ibcon#enter sib2, iclass 18, count 0 2006.201.02:16:13.83#ibcon#flushed, iclass 18, count 0 2006.201.02:16:13.83#ibcon#about to write, iclass 18, count 0 2006.201.02:16:13.83#ibcon#wrote, iclass 18, count 0 2006.201.02:16:13.83#ibcon#about to read 3, iclass 18, count 0 2006.201.02:16:13.86#ibcon#read 3, iclass 18, count 0 2006.201.02:16:13.86#ibcon#about to read 4, iclass 18, count 0 2006.201.02:16:13.86#ibcon#read 4, iclass 18, count 0 2006.201.02:16:13.86#ibcon#about to read 5, iclass 18, count 0 2006.201.02:16:13.86#ibcon#read 5, iclass 18, count 0 2006.201.02:16:13.86#ibcon#about to read 6, iclass 18, count 0 2006.201.02:16:13.86#ibcon#read 6, iclass 18, count 0 2006.201.02:16:13.86#ibcon#end of sib2, iclass 18, count 0 2006.201.02:16:13.86#ibcon#*after write, iclass 18, count 0 2006.201.02:16:13.86#ibcon#*before return 0, iclass 18, count 0 2006.201.02:16:13.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:13.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:13.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.02:16:13.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.02:16:13.86$vck44/valo=3,564.99 2006.201.02:16:13.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.02:16:13.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.02:16:13.86#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:13.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:13.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:13.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:13.86#ibcon#enter wrdev, iclass 20, count 0 2006.201.02:16:13.86#ibcon#first serial, iclass 20, count 0 2006.201.02:16:13.86#ibcon#enter sib2, iclass 20, count 0 2006.201.02:16:13.86#ibcon#flushed, iclass 20, count 0 2006.201.02:16:13.86#ibcon#about to write, iclass 20, count 0 2006.201.02:16:13.86#ibcon#wrote, iclass 20, count 0 2006.201.02:16:13.86#ibcon#about to read 3, iclass 20, count 0 2006.201.02:16:13.88#ibcon#read 3, iclass 20, count 0 2006.201.02:16:13.88#ibcon#about to read 4, iclass 20, count 0 2006.201.02:16:13.88#ibcon#read 4, iclass 20, count 0 2006.201.02:16:13.88#ibcon#about to read 5, iclass 20, count 0 2006.201.02:16:13.88#ibcon#read 5, iclass 20, count 0 2006.201.02:16:13.88#ibcon#about to read 6, iclass 20, count 0 2006.201.02:16:13.88#ibcon#read 6, iclass 20, count 0 2006.201.02:16:13.88#ibcon#end of sib2, iclass 20, count 0 2006.201.02:16:13.88#ibcon#*mode == 0, iclass 20, count 0 2006.201.02:16:13.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.02:16:13.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:16:13.88#ibcon#*before write, iclass 20, count 0 2006.201.02:16:13.88#ibcon#enter sib2, iclass 20, count 0 2006.201.02:16:13.88#ibcon#flushed, iclass 20, count 0 2006.201.02:16:13.88#ibcon#about to write, iclass 20, count 0 2006.201.02:16:13.88#ibcon#wrote, iclass 20, count 0 2006.201.02:16:13.88#ibcon#about to read 3, iclass 20, count 0 2006.201.02:16:13.93#ibcon#read 3, iclass 20, count 0 2006.201.02:16:13.93#ibcon#about to read 4, iclass 20, count 0 2006.201.02:16:13.93#ibcon#read 4, iclass 20, count 0 2006.201.02:16:13.93#ibcon#about to read 5, iclass 20, count 0 2006.201.02:16:13.93#ibcon#read 5, iclass 20, count 0 2006.201.02:16:13.93#ibcon#about to read 6, iclass 20, count 0 2006.201.02:16:13.93#ibcon#read 6, iclass 20, count 0 2006.201.02:16:13.93#ibcon#end of sib2, iclass 20, count 0 2006.201.02:16:13.93#ibcon#*after write, iclass 20, count 0 2006.201.02:16:13.93#ibcon#*before return 0, iclass 20, count 0 2006.201.02:16:13.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:13.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:13.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.02:16:13.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.02:16:13.93$vck44/va=3,8 2006.201.02:16:13.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.02:16:13.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.02:16:13.93#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:13.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:13.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:13.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:13.98#ibcon#enter wrdev, iclass 22, count 2 2006.201.02:16:13.98#ibcon#first serial, iclass 22, count 2 2006.201.02:16:13.98#ibcon#enter sib2, iclass 22, count 2 2006.201.02:16:13.98#ibcon#flushed, iclass 22, count 2 2006.201.02:16:13.98#ibcon#about to write, iclass 22, count 2 2006.201.02:16:13.98#ibcon#wrote, iclass 22, count 2 2006.201.02:16:13.98#ibcon#about to read 3, iclass 22, count 2 2006.201.02:16:14.00#ibcon#read 3, iclass 22, count 2 2006.201.02:16:14.00#ibcon#about to read 4, iclass 22, count 2 2006.201.02:16:14.00#ibcon#read 4, iclass 22, count 2 2006.201.02:16:14.00#ibcon#about to read 5, iclass 22, count 2 2006.201.02:16:14.00#ibcon#read 5, iclass 22, count 2 2006.201.02:16:14.00#ibcon#about to read 6, iclass 22, count 2 2006.201.02:16:14.00#ibcon#read 6, iclass 22, count 2 2006.201.02:16:14.00#ibcon#end of sib2, iclass 22, count 2 2006.201.02:16:14.00#ibcon#*mode == 0, iclass 22, count 2 2006.201.02:16:14.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.02:16:14.00#ibcon#[25=AT03-08\r\n] 2006.201.02:16:14.00#ibcon#*before write, iclass 22, count 2 2006.201.02:16:14.00#ibcon#enter sib2, iclass 22, count 2 2006.201.02:16:14.00#ibcon#flushed, iclass 22, count 2 2006.201.02:16:14.00#ibcon#about to write, iclass 22, count 2 2006.201.02:16:14.00#ibcon#wrote, iclass 22, count 2 2006.201.02:16:14.00#ibcon#about to read 3, iclass 22, count 2 2006.201.02:16:14.03#ibcon#read 3, iclass 22, count 2 2006.201.02:16:14.03#ibcon#about to read 4, iclass 22, count 2 2006.201.02:16:14.03#ibcon#read 4, iclass 22, count 2 2006.201.02:16:14.03#ibcon#about to read 5, iclass 22, count 2 2006.201.02:16:14.03#ibcon#read 5, iclass 22, count 2 2006.201.02:16:14.03#ibcon#about to read 6, iclass 22, count 2 2006.201.02:16:14.03#ibcon#read 6, iclass 22, count 2 2006.201.02:16:14.03#ibcon#end of sib2, iclass 22, count 2 2006.201.02:16:14.03#ibcon#*after write, iclass 22, count 2 2006.201.02:16:14.03#ibcon#*before return 0, iclass 22, count 2 2006.201.02:16:14.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:14.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:14.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.02:16:14.03#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:14.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:14.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:14.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:14.15#ibcon#enter wrdev, iclass 22, count 0 2006.201.02:16:14.15#ibcon#first serial, iclass 22, count 0 2006.201.02:16:14.15#ibcon#enter sib2, iclass 22, count 0 2006.201.02:16:14.15#ibcon#flushed, iclass 22, count 0 2006.201.02:16:14.15#ibcon#about to write, iclass 22, count 0 2006.201.02:16:14.15#ibcon#wrote, iclass 22, count 0 2006.201.02:16:14.15#ibcon#about to read 3, iclass 22, count 0 2006.201.02:16:14.17#ibcon#read 3, iclass 22, count 0 2006.201.02:16:14.17#ibcon#about to read 4, iclass 22, count 0 2006.201.02:16:14.17#ibcon#read 4, iclass 22, count 0 2006.201.02:16:14.17#ibcon#about to read 5, iclass 22, count 0 2006.201.02:16:14.17#ibcon#read 5, iclass 22, count 0 2006.201.02:16:14.17#ibcon#about to read 6, iclass 22, count 0 2006.201.02:16:14.17#ibcon#read 6, iclass 22, count 0 2006.201.02:16:14.17#ibcon#end of sib2, iclass 22, count 0 2006.201.02:16:14.17#ibcon#*mode == 0, iclass 22, count 0 2006.201.02:16:14.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.02:16:14.17#ibcon#[25=USB\r\n] 2006.201.02:16:14.17#ibcon#*before write, iclass 22, count 0 2006.201.02:16:14.17#ibcon#enter sib2, iclass 22, count 0 2006.201.02:16:14.17#ibcon#flushed, iclass 22, count 0 2006.201.02:16:14.17#ibcon#about to write, iclass 22, count 0 2006.201.02:16:14.17#ibcon#wrote, iclass 22, count 0 2006.201.02:16:14.17#ibcon#about to read 3, iclass 22, count 0 2006.201.02:16:14.20#ibcon#read 3, iclass 22, count 0 2006.201.02:16:14.20#ibcon#about to read 4, iclass 22, count 0 2006.201.02:16:14.20#ibcon#read 4, iclass 22, count 0 2006.201.02:16:14.20#ibcon#about to read 5, iclass 22, count 0 2006.201.02:16:14.20#ibcon#read 5, iclass 22, count 0 2006.201.02:16:14.20#ibcon#about to read 6, iclass 22, count 0 2006.201.02:16:14.20#ibcon#read 6, iclass 22, count 0 2006.201.02:16:14.20#ibcon#end of sib2, iclass 22, count 0 2006.201.02:16:14.20#ibcon#*after write, iclass 22, count 0 2006.201.02:16:14.20#ibcon#*before return 0, iclass 22, count 0 2006.201.02:16:14.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:14.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:14.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.02:16:14.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.02:16:14.20$vck44/valo=4,624.99 2006.201.02:16:14.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.02:16:14.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.02:16:14.20#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:14.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:14.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:14.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:14.20#ibcon#enter wrdev, iclass 24, count 0 2006.201.02:16:14.20#ibcon#first serial, iclass 24, count 0 2006.201.02:16:14.20#ibcon#enter sib2, iclass 24, count 0 2006.201.02:16:14.20#ibcon#flushed, iclass 24, count 0 2006.201.02:16:14.20#ibcon#about to write, iclass 24, count 0 2006.201.02:16:14.20#ibcon#wrote, iclass 24, count 0 2006.201.02:16:14.20#ibcon#about to read 3, iclass 24, count 0 2006.201.02:16:14.22#ibcon#read 3, iclass 24, count 0 2006.201.02:16:14.22#ibcon#about to read 4, iclass 24, count 0 2006.201.02:16:14.22#ibcon#read 4, iclass 24, count 0 2006.201.02:16:14.22#ibcon#about to read 5, iclass 24, count 0 2006.201.02:16:14.22#ibcon#read 5, iclass 24, count 0 2006.201.02:16:14.22#ibcon#about to read 6, iclass 24, count 0 2006.201.02:16:14.22#ibcon#read 6, iclass 24, count 0 2006.201.02:16:14.22#ibcon#end of sib2, iclass 24, count 0 2006.201.02:16:14.22#ibcon#*mode == 0, iclass 24, count 0 2006.201.02:16:14.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.02:16:14.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:16:14.22#ibcon#*before write, iclass 24, count 0 2006.201.02:16:14.22#ibcon#enter sib2, iclass 24, count 0 2006.201.02:16:14.22#ibcon#flushed, iclass 24, count 0 2006.201.02:16:14.22#ibcon#about to write, iclass 24, count 0 2006.201.02:16:14.22#ibcon#wrote, iclass 24, count 0 2006.201.02:16:14.22#ibcon#about to read 3, iclass 24, count 0 2006.201.02:16:14.26#ibcon#read 3, iclass 24, count 0 2006.201.02:16:14.26#ibcon#about to read 4, iclass 24, count 0 2006.201.02:16:14.26#ibcon#read 4, iclass 24, count 0 2006.201.02:16:14.26#ibcon#about to read 5, iclass 24, count 0 2006.201.02:16:14.26#ibcon#read 5, iclass 24, count 0 2006.201.02:16:14.26#ibcon#about to read 6, iclass 24, count 0 2006.201.02:16:14.26#ibcon#read 6, iclass 24, count 0 2006.201.02:16:14.26#ibcon#end of sib2, iclass 24, count 0 2006.201.02:16:14.26#ibcon#*after write, iclass 24, count 0 2006.201.02:16:14.26#ibcon#*before return 0, iclass 24, count 0 2006.201.02:16:14.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:14.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:14.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.02:16:14.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.02:16:14.26$vck44/va=4,7 2006.201.02:16:14.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.02:16:14.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.02:16:14.26#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:14.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:14.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:14.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:14.32#ibcon#enter wrdev, iclass 26, count 2 2006.201.02:16:14.32#ibcon#first serial, iclass 26, count 2 2006.201.02:16:14.32#ibcon#enter sib2, iclass 26, count 2 2006.201.02:16:14.32#ibcon#flushed, iclass 26, count 2 2006.201.02:16:14.32#ibcon#about to write, iclass 26, count 2 2006.201.02:16:14.32#ibcon#wrote, iclass 26, count 2 2006.201.02:16:14.32#ibcon#about to read 3, iclass 26, count 2 2006.201.02:16:14.34#ibcon#read 3, iclass 26, count 2 2006.201.02:16:14.34#ibcon#about to read 4, iclass 26, count 2 2006.201.02:16:14.34#ibcon#read 4, iclass 26, count 2 2006.201.02:16:14.34#ibcon#about to read 5, iclass 26, count 2 2006.201.02:16:14.34#ibcon#read 5, iclass 26, count 2 2006.201.02:16:14.34#ibcon#about to read 6, iclass 26, count 2 2006.201.02:16:14.34#ibcon#read 6, iclass 26, count 2 2006.201.02:16:14.34#ibcon#end of sib2, iclass 26, count 2 2006.201.02:16:14.34#ibcon#*mode == 0, iclass 26, count 2 2006.201.02:16:14.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.02:16:14.34#ibcon#[25=AT04-07\r\n] 2006.201.02:16:14.34#ibcon#*before write, iclass 26, count 2 2006.201.02:16:14.34#ibcon#enter sib2, iclass 26, count 2 2006.201.02:16:14.34#ibcon#flushed, iclass 26, count 2 2006.201.02:16:14.34#ibcon#about to write, iclass 26, count 2 2006.201.02:16:14.34#ibcon#wrote, iclass 26, count 2 2006.201.02:16:14.34#ibcon#about to read 3, iclass 26, count 2 2006.201.02:16:14.37#ibcon#read 3, iclass 26, count 2 2006.201.02:16:14.37#ibcon#about to read 4, iclass 26, count 2 2006.201.02:16:14.37#ibcon#read 4, iclass 26, count 2 2006.201.02:16:14.37#ibcon#about to read 5, iclass 26, count 2 2006.201.02:16:14.37#ibcon#read 5, iclass 26, count 2 2006.201.02:16:14.37#ibcon#about to read 6, iclass 26, count 2 2006.201.02:16:14.37#ibcon#read 6, iclass 26, count 2 2006.201.02:16:14.37#ibcon#end of sib2, iclass 26, count 2 2006.201.02:16:14.37#ibcon#*after write, iclass 26, count 2 2006.201.02:16:14.37#ibcon#*before return 0, iclass 26, count 2 2006.201.02:16:14.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:14.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:14.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.02:16:14.37#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:14.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:14.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:14.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:14.49#ibcon#enter wrdev, iclass 26, count 0 2006.201.02:16:14.49#ibcon#first serial, iclass 26, count 0 2006.201.02:16:14.49#ibcon#enter sib2, iclass 26, count 0 2006.201.02:16:14.49#ibcon#flushed, iclass 26, count 0 2006.201.02:16:14.49#ibcon#about to write, iclass 26, count 0 2006.201.02:16:14.49#ibcon#wrote, iclass 26, count 0 2006.201.02:16:14.49#ibcon#about to read 3, iclass 26, count 0 2006.201.02:16:14.51#ibcon#read 3, iclass 26, count 0 2006.201.02:16:14.51#ibcon#about to read 4, iclass 26, count 0 2006.201.02:16:14.51#ibcon#read 4, iclass 26, count 0 2006.201.02:16:14.51#ibcon#about to read 5, iclass 26, count 0 2006.201.02:16:14.51#ibcon#read 5, iclass 26, count 0 2006.201.02:16:14.51#ibcon#about to read 6, iclass 26, count 0 2006.201.02:16:14.51#ibcon#read 6, iclass 26, count 0 2006.201.02:16:14.51#ibcon#end of sib2, iclass 26, count 0 2006.201.02:16:14.51#ibcon#*mode == 0, iclass 26, count 0 2006.201.02:16:14.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.02:16:14.51#ibcon#[25=USB\r\n] 2006.201.02:16:14.51#ibcon#*before write, iclass 26, count 0 2006.201.02:16:14.51#ibcon#enter sib2, iclass 26, count 0 2006.201.02:16:14.51#ibcon#flushed, iclass 26, count 0 2006.201.02:16:14.51#ibcon#about to write, iclass 26, count 0 2006.201.02:16:14.51#ibcon#wrote, iclass 26, count 0 2006.201.02:16:14.51#ibcon#about to read 3, iclass 26, count 0 2006.201.02:16:14.54#ibcon#read 3, iclass 26, count 0 2006.201.02:16:14.54#ibcon#about to read 4, iclass 26, count 0 2006.201.02:16:14.54#ibcon#read 4, iclass 26, count 0 2006.201.02:16:14.54#ibcon#about to read 5, iclass 26, count 0 2006.201.02:16:14.54#ibcon#read 5, iclass 26, count 0 2006.201.02:16:14.54#ibcon#about to read 6, iclass 26, count 0 2006.201.02:16:14.54#ibcon#read 6, iclass 26, count 0 2006.201.02:16:14.54#ibcon#end of sib2, iclass 26, count 0 2006.201.02:16:14.54#ibcon#*after write, iclass 26, count 0 2006.201.02:16:14.54#ibcon#*before return 0, iclass 26, count 0 2006.201.02:16:14.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:14.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:14.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.02:16:14.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.02:16:14.54$vck44/valo=5,734.99 2006.201.02:16:14.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.02:16:14.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.02:16:14.54#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:14.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:14.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:14.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:14.54#ibcon#enter wrdev, iclass 28, count 0 2006.201.02:16:14.54#ibcon#first serial, iclass 28, count 0 2006.201.02:16:14.54#ibcon#enter sib2, iclass 28, count 0 2006.201.02:16:14.54#ibcon#flushed, iclass 28, count 0 2006.201.02:16:14.54#ibcon#about to write, iclass 28, count 0 2006.201.02:16:14.54#ibcon#wrote, iclass 28, count 0 2006.201.02:16:14.54#ibcon#about to read 3, iclass 28, count 0 2006.201.02:16:14.56#ibcon#read 3, iclass 28, count 0 2006.201.02:16:14.56#ibcon#about to read 4, iclass 28, count 0 2006.201.02:16:14.56#ibcon#read 4, iclass 28, count 0 2006.201.02:16:14.56#ibcon#about to read 5, iclass 28, count 0 2006.201.02:16:14.56#ibcon#read 5, iclass 28, count 0 2006.201.02:16:14.56#ibcon#about to read 6, iclass 28, count 0 2006.201.02:16:14.56#ibcon#read 6, iclass 28, count 0 2006.201.02:16:14.56#ibcon#end of sib2, iclass 28, count 0 2006.201.02:16:14.56#ibcon#*mode == 0, iclass 28, count 0 2006.201.02:16:14.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.02:16:14.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:16:14.56#ibcon#*before write, iclass 28, count 0 2006.201.02:16:14.56#ibcon#enter sib2, iclass 28, count 0 2006.201.02:16:14.56#ibcon#flushed, iclass 28, count 0 2006.201.02:16:14.56#ibcon#about to write, iclass 28, count 0 2006.201.02:16:14.56#ibcon#wrote, iclass 28, count 0 2006.201.02:16:14.56#ibcon#about to read 3, iclass 28, count 0 2006.201.02:16:14.60#ibcon#read 3, iclass 28, count 0 2006.201.02:16:14.60#ibcon#about to read 4, iclass 28, count 0 2006.201.02:16:14.60#ibcon#read 4, iclass 28, count 0 2006.201.02:16:14.60#ibcon#about to read 5, iclass 28, count 0 2006.201.02:16:14.60#ibcon#read 5, iclass 28, count 0 2006.201.02:16:14.60#ibcon#about to read 6, iclass 28, count 0 2006.201.02:16:14.60#ibcon#read 6, iclass 28, count 0 2006.201.02:16:14.60#ibcon#end of sib2, iclass 28, count 0 2006.201.02:16:14.60#ibcon#*after write, iclass 28, count 0 2006.201.02:16:14.60#ibcon#*before return 0, iclass 28, count 0 2006.201.02:16:14.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:14.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:14.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.02:16:14.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.02:16:14.60$vck44/va=5,4 2006.201.02:16:14.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.02:16:14.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.02:16:14.60#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:14.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:14.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:14.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:14.66#ibcon#enter wrdev, iclass 30, count 2 2006.201.02:16:14.66#ibcon#first serial, iclass 30, count 2 2006.201.02:16:14.66#ibcon#enter sib2, iclass 30, count 2 2006.201.02:16:14.66#ibcon#flushed, iclass 30, count 2 2006.201.02:16:14.66#ibcon#about to write, iclass 30, count 2 2006.201.02:16:14.66#ibcon#wrote, iclass 30, count 2 2006.201.02:16:14.66#ibcon#about to read 3, iclass 30, count 2 2006.201.02:16:14.68#ibcon#read 3, iclass 30, count 2 2006.201.02:16:14.68#ibcon#about to read 4, iclass 30, count 2 2006.201.02:16:14.68#ibcon#read 4, iclass 30, count 2 2006.201.02:16:14.68#ibcon#about to read 5, iclass 30, count 2 2006.201.02:16:14.68#ibcon#read 5, iclass 30, count 2 2006.201.02:16:14.68#ibcon#about to read 6, iclass 30, count 2 2006.201.02:16:14.68#ibcon#read 6, iclass 30, count 2 2006.201.02:16:14.68#ibcon#end of sib2, iclass 30, count 2 2006.201.02:16:14.68#ibcon#*mode == 0, iclass 30, count 2 2006.201.02:16:14.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.02:16:14.68#ibcon#[25=AT05-04\r\n] 2006.201.02:16:14.68#ibcon#*before write, iclass 30, count 2 2006.201.02:16:14.68#ibcon#enter sib2, iclass 30, count 2 2006.201.02:16:14.68#ibcon#flushed, iclass 30, count 2 2006.201.02:16:14.68#ibcon#about to write, iclass 30, count 2 2006.201.02:16:14.68#ibcon#wrote, iclass 30, count 2 2006.201.02:16:14.68#ibcon#about to read 3, iclass 30, count 2 2006.201.02:16:14.72#ibcon#read 3, iclass 30, count 2 2006.201.02:16:14.72#ibcon#about to read 4, iclass 30, count 2 2006.201.02:16:14.72#ibcon#read 4, iclass 30, count 2 2006.201.02:16:14.72#ibcon#about to read 5, iclass 30, count 2 2006.201.02:16:14.72#ibcon#read 5, iclass 30, count 2 2006.201.02:16:14.72#ibcon#about to read 6, iclass 30, count 2 2006.201.02:16:14.72#ibcon#read 6, iclass 30, count 2 2006.201.02:16:14.72#ibcon#end of sib2, iclass 30, count 2 2006.201.02:16:14.72#ibcon#*after write, iclass 30, count 2 2006.201.02:16:14.72#ibcon#*before return 0, iclass 30, count 2 2006.201.02:16:14.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:14.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:14.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.02:16:14.72#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:14.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:14.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:14.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:14.84#ibcon#enter wrdev, iclass 30, count 0 2006.201.02:16:14.84#ibcon#first serial, iclass 30, count 0 2006.201.02:16:14.84#ibcon#enter sib2, iclass 30, count 0 2006.201.02:16:14.84#ibcon#flushed, iclass 30, count 0 2006.201.02:16:14.84#ibcon#about to write, iclass 30, count 0 2006.201.02:16:14.84#ibcon#wrote, iclass 30, count 0 2006.201.02:16:14.84#ibcon#about to read 3, iclass 30, count 0 2006.201.02:16:14.86#ibcon#read 3, iclass 30, count 0 2006.201.02:16:14.86#ibcon#about to read 4, iclass 30, count 0 2006.201.02:16:14.86#ibcon#read 4, iclass 30, count 0 2006.201.02:16:14.86#ibcon#about to read 5, iclass 30, count 0 2006.201.02:16:14.86#ibcon#read 5, iclass 30, count 0 2006.201.02:16:14.86#ibcon#about to read 6, iclass 30, count 0 2006.201.02:16:14.86#ibcon#read 6, iclass 30, count 0 2006.201.02:16:14.86#ibcon#end of sib2, iclass 30, count 0 2006.201.02:16:14.86#ibcon#*mode == 0, iclass 30, count 0 2006.201.02:16:14.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.02:16:14.86#ibcon#[25=USB\r\n] 2006.201.02:16:14.86#ibcon#*before write, iclass 30, count 0 2006.201.02:16:14.86#ibcon#enter sib2, iclass 30, count 0 2006.201.02:16:14.86#ibcon#flushed, iclass 30, count 0 2006.201.02:16:14.86#ibcon#about to write, iclass 30, count 0 2006.201.02:16:14.86#ibcon#wrote, iclass 30, count 0 2006.201.02:16:14.86#ibcon#about to read 3, iclass 30, count 0 2006.201.02:16:14.89#ibcon#read 3, iclass 30, count 0 2006.201.02:16:14.89#ibcon#about to read 4, iclass 30, count 0 2006.201.02:16:14.89#ibcon#read 4, iclass 30, count 0 2006.201.02:16:14.89#ibcon#about to read 5, iclass 30, count 0 2006.201.02:16:14.89#ibcon#read 5, iclass 30, count 0 2006.201.02:16:14.89#ibcon#about to read 6, iclass 30, count 0 2006.201.02:16:14.89#ibcon#read 6, iclass 30, count 0 2006.201.02:16:14.89#ibcon#end of sib2, iclass 30, count 0 2006.201.02:16:14.89#ibcon#*after write, iclass 30, count 0 2006.201.02:16:14.89#ibcon#*before return 0, iclass 30, count 0 2006.201.02:16:14.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:14.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:14.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.02:16:14.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.02:16:14.89$vck44/valo=6,814.99 2006.201.02:16:14.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.02:16:14.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.02:16:14.89#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:14.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:14.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:14.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:14.89#ibcon#enter wrdev, iclass 32, count 0 2006.201.02:16:14.89#ibcon#first serial, iclass 32, count 0 2006.201.02:16:14.89#ibcon#enter sib2, iclass 32, count 0 2006.201.02:16:14.89#ibcon#flushed, iclass 32, count 0 2006.201.02:16:14.89#ibcon#about to write, iclass 32, count 0 2006.201.02:16:14.89#ibcon#wrote, iclass 32, count 0 2006.201.02:16:14.89#ibcon#about to read 3, iclass 32, count 0 2006.201.02:16:14.91#ibcon#read 3, iclass 32, count 0 2006.201.02:16:14.91#ibcon#about to read 4, iclass 32, count 0 2006.201.02:16:14.91#ibcon#read 4, iclass 32, count 0 2006.201.02:16:14.91#ibcon#about to read 5, iclass 32, count 0 2006.201.02:16:14.91#ibcon#read 5, iclass 32, count 0 2006.201.02:16:14.91#ibcon#about to read 6, iclass 32, count 0 2006.201.02:16:14.91#ibcon#read 6, iclass 32, count 0 2006.201.02:16:14.91#ibcon#end of sib2, iclass 32, count 0 2006.201.02:16:14.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.02:16:14.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.02:16:14.91#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:16:14.91#ibcon#*before write, iclass 32, count 0 2006.201.02:16:14.91#ibcon#enter sib2, iclass 32, count 0 2006.201.02:16:14.91#ibcon#flushed, iclass 32, count 0 2006.201.02:16:14.91#ibcon#about to write, iclass 32, count 0 2006.201.02:16:14.91#ibcon#wrote, iclass 32, count 0 2006.201.02:16:14.91#ibcon#about to read 3, iclass 32, count 0 2006.201.02:16:14.95#ibcon#read 3, iclass 32, count 0 2006.201.02:16:14.95#ibcon#about to read 4, iclass 32, count 0 2006.201.02:16:14.95#ibcon#read 4, iclass 32, count 0 2006.201.02:16:14.95#ibcon#about to read 5, iclass 32, count 0 2006.201.02:16:14.95#ibcon#read 5, iclass 32, count 0 2006.201.02:16:14.95#ibcon#about to read 6, iclass 32, count 0 2006.201.02:16:14.95#ibcon#read 6, iclass 32, count 0 2006.201.02:16:14.95#ibcon#end of sib2, iclass 32, count 0 2006.201.02:16:14.95#ibcon#*after write, iclass 32, count 0 2006.201.02:16:14.95#ibcon#*before return 0, iclass 32, count 0 2006.201.02:16:14.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:14.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:14.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.02:16:14.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.02:16:14.95$vck44/va=6,5 2006.201.02:16:14.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.02:16:14.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.02:16:14.95#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:14.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:15.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:15.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:15.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.02:16:15.01#ibcon#first serial, iclass 34, count 2 2006.201.02:16:15.01#ibcon#enter sib2, iclass 34, count 2 2006.201.02:16:15.01#ibcon#flushed, iclass 34, count 2 2006.201.02:16:15.01#ibcon#about to write, iclass 34, count 2 2006.201.02:16:15.01#ibcon#wrote, iclass 34, count 2 2006.201.02:16:15.01#ibcon#about to read 3, iclass 34, count 2 2006.201.02:16:15.03#ibcon#read 3, iclass 34, count 2 2006.201.02:16:15.03#ibcon#about to read 4, iclass 34, count 2 2006.201.02:16:15.03#ibcon#read 4, iclass 34, count 2 2006.201.02:16:15.03#ibcon#about to read 5, iclass 34, count 2 2006.201.02:16:15.03#ibcon#read 5, iclass 34, count 2 2006.201.02:16:15.03#ibcon#about to read 6, iclass 34, count 2 2006.201.02:16:15.03#ibcon#read 6, iclass 34, count 2 2006.201.02:16:15.03#ibcon#end of sib2, iclass 34, count 2 2006.201.02:16:15.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.02:16:15.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.02:16:15.03#ibcon#[25=AT06-05\r\n] 2006.201.02:16:15.03#ibcon#*before write, iclass 34, count 2 2006.201.02:16:15.03#ibcon#enter sib2, iclass 34, count 2 2006.201.02:16:15.03#ibcon#flushed, iclass 34, count 2 2006.201.02:16:15.03#ibcon#about to write, iclass 34, count 2 2006.201.02:16:15.03#ibcon#wrote, iclass 34, count 2 2006.201.02:16:15.03#ibcon#about to read 3, iclass 34, count 2 2006.201.02:16:15.06#ibcon#read 3, iclass 34, count 2 2006.201.02:16:15.06#ibcon#about to read 4, iclass 34, count 2 2006.201.02:16:15.06#ibcon#read 4, iclass 34, count 2 2006.201.02:16:15.06#ibcon#about to read 5, iclass 34, count 2 2006.201.02:16:15.06#ibcon#read 5, iclass 34, count 2 2006.201.02:16:15.06#ibcon#about to read 6, iclass 34, count 2 2006.201.02:16:15.06#ibcon#read 6, iclass 34, count 2 2006.201.02:16:15.06#ibcon#end of sib2, iclass 34, count 2 2006.201.02:16:15.06#ibcon#*after write, iclass 34, count 2 2006.201.02:16:15.06#ibcon#*before return 0, iclass 34, count 2 2006.201.02:16:15.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:15.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:15.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.02:16:15.06#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:15.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:15.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:15.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:15.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.02:16:15.18#ibcon#first serial, iclass 34, count 0 2006.201.02:16:15.18#ibcon#enter sib2, iclass 34, count 0 2006.201.02:16:15.18#ibcon#flushed, iclass 34, count 0 2006.201.02:16:15.18#ibcon#about to write, iclass 34, count 0 2006.201.02:16:15.18#ibcon#wrote, iclass 34, count 0 2006.201.02:16:15.18#ibcon#about to read 3, iclass 34, count 0 2006.201.02:16:15.20#ibcon#read 3, iclass 34, count 0 2006.201.02:16:15.20#ibcon#about to read 4, iclass 34, count 0 2006.201.02:16:15.20#ibcon#read 4, iclass 34, count 0 2006.201.02:16:15.20#ibcon#about to read 5, iclass 34, count 0 2006.201.02:16:15.20#ibcon#read 5, iclass 34, count 0 2006.201.02:16:15.20#ibcon#about to read 6, iclass 34, count 0 2006.201.02:16:15.20#ibcon#read 6, iclass 34, count 0 2006.201.02:16:15.20#ibcon#end of sib2, iclass 34, count 0 2006.201.02:16:15.20#ibcon#*mode == 0, iclass 34, count 0 2006.201.02:16:15.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.02:16:15.20#ibcon#[25=USB\r\n] 2006.201.02:16:15.20#ibcon#*before write, iclass 34, count 0 2006.201.02:16:15.20#ibcon#enter sib2, iclass 34, count 0 2006.201.02:16:15.20#ibcon#flushed, iclass 34, count 0 2006.201.02:16:15.20#ibcon#about to write, iclass 34, count 0 2006.201.02:16:15.20#ibcon#wrote, iclass 34, count 0 2006.201.02:16:15.20#ibcon#about to read 3, iclass 34, count 0 2006.201.02:16:15.23#ibcon#read 3, iclass 34, count 0 2006.201.02:16:15.23#ibcon#about to read 4, iclass 34, count 0 2006.201.02:16:15.23#ibcon#read 4, iclass 34, count 0 2006.201.02:16:15.23#ibcon#about to read 5, iclass 34, count 0 2006.201.02:16:15.23#ibcon#read 5, iclass 34, count 0 2006.201.02:16:15.23#ibcon#about to read 6, iclass 34, count 0 2006.201.02:16:15.23#ibcon#read 6, iclass 34, count 0 2006.201.02:16:15.23#ibcon#end of sib2, iclass 34, count 0 2006.201.02:16:15.23#ibcon#*after write, iclass 34, count 0 2006.201.02:16:15.23#ibcon#*before return 0, iclass 34, count 0 2006.201.02:16:15.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:15.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:15.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.02:16:15.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.02:16:15.23$vck44/valo=7,864.99 2006.201.02:16:15.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.02:16:15.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.02:16:15.23#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:15.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:15.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:15.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:15.23#ibcon#enter wrdev, iclass 36, count 0 2006.201.02:16:15.23#ibcon#first serial, iclass 36, count 0 2006.201.02:16:15.23#ibcon#enter sib2, iclass 36, count 0 2006.201.02:16:15.23#ibcon#flushed, iclass 36, count 0 2006.201.02:16:15.23#ibcon#about to write, iclass 36, count 0 2006.201.02:16:15.23#ibcon#wrote, iclass 36, count 0 2006.201.02:16:15.23#ibcon#about to read 3, iclass 36, count 0 2006.201.02:16:15.25#ibcon#read 3, iclass 36, count 0 2006.201.02:16:15.25#ibcon#about to read 4, iclass 36, count 0 2006.201.02:16:15.25#ibcon#read 4, iclass 36, count 0 2006.201.02:16:15.25#ibcon#about to read 5, iclass 36, count 0 2006.201.02:16:15.25#ibcon#read 5, iclass 36, count 0 2006.201.02:16:15.25#ibcon#about to read 6, iclass 36, count 0 2006.201.02:16:15.25#ibcon#read 6, iclass 36, count 0 2006.201.02:16:15.25#ibcon#end of sib2, iclass 36, count 0 2006.201.02:16:15.25#ibcon#*mode == 0, iclass 36, count 0 2006.201.02:16:15.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.02:16:15.25#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:16:15.25#ibcon#*before write, iclass 36, count 0 2006.201.02:16:15.25#ibcon#enter sib2, iclass 36, count 0 2006.201.02:16:15.25#ibcon#flushed, iclass 36, count 0 2006.201.02:16:15.25#ibcon#about to write, iclass 36, count 0 2006.201.02:16:15.25#ibcon#wrote, iclass 36, count 0 2006.201.02:16:15.25#ibcon#about to read 3, iclass 36, count 0 2006.201.02:16:15.29#ibcon#read 3, iclass 36, count 0 2006.201.02:16:15.29#ibcon#about to read 4, iclass 36, count 0 2006.201.02:16:15.29#ibcon#read 4, iclass 36, count 0 2006.201.02:16:15.29#ibcon#about to read 5, iclass 36, count 0 2006.201.02:16:15.29#ibcon#read 5, iclass 36, count 0 2006.201.02:16:15.29#ibcon#about to read 6, iclass 36, count 0 2006.201.02:16:15.29#ibcon#read 6, iclass 36, count 0 2006.201.02:16:15.29#ibcon#end of sib2, iclass 36, count 0 2006.201.02:16:15.29#ibcon#*after write, iclass 36, count 0 2006.201.02:16:15.29#ibcon#*before return 0, iclass 36, count 0 2006.201.02:16:15.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:15.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:15.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.02:16:15.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.02:16:15.29$vck44/va=7,5 2006.201.02:16:15.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.02:16:15.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.02:16:15.29#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:15.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:15.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:15.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:15.35#ibcon#enter wrdev, iclass 38, count 2 2006.201.02:16:15.35#ibcon#first serial, iclass 38, count 2 2006.201.02:16:15.35#ibcon#enter sib2, iclass 38, count 2 2006.201.02:16:15.35#ibcon#flushed, iclass 38, count 2 2006.201.02:16:15.35#ibcon#about to write, iclass 38, count 2 2006.201.02:16:15.35#ibcon#wrote, iclass 38, count 2 2006.201.02:16:15.35#ibcon#about to read 3, iclass 38, count 2 2006.201.02:16:15.37#ibcon#read 3, iclass 38, count 2 2006.201.02:16:15.37#ibcon#about to read 4, iclass 38, count 2 2006.201.02:16:15.37#ibcon#read 4, iclass 38, count 2 2006.201.02:16:15.37#ibcon#about to read 5, iclass 38, count 2 2006.201.02:16:15.37#ibcon#read 5, iclass 38, count 2 2006.201.02:16:15.37#ibcon#about to read 6, iclass 38, count 2 2006.201.02:16:15.37#ibcon#read 6, iclass 38, count 2 2006.201.02:16:15.37#ibcon#end of sib2, iclass 38, count 2 2006.201.02:16:15.37#ibcon#*mode == 0, iclass 38, count 2 2006.201.02:16:15.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.02:16:15.37#ibcon#[25=AT07-05\r\n] 2006.201.02:16:15.37#ibcon#*before write, iclass 38, count 2 2006.201.02:16:15.37#ibcon#enter sib2, iclass 38, count 2 2006.201.02:16:15.37#ibcon#flushed, iclass 38, count 2 2006.201.02:16:15.37#ibcon#about to write, iclass 38, count 2 2006.201.02:16:15.37#ibcon#wrote, iclass 38, count 2 2006.201.02:16:15.37#ibcon#about to read 3, iclass 38, count 2 2006.201.02:16:15.40#ibcon#read 3, iclass 38, count 2 2006.201.02:16:15.40#ibcon#about to read 4, iclass 38, count 2 2006.201.02:16:15.40#ibcon#read 4, iclass 38, count 2 2006.201.02:16:15.40#ibcon#about to read 5, iclass 38, count 2 2006.201.02:16:15.40#ibcon#read 5, iclass 38, count 2 2006.201.02:16:15.40#ibcon#about to read 6, iclass 38, count 2 2006.201.02:16:15.40#ibcon#read 6, iclass 38, count 2 2006.201.02:16:15.40#ibcon#end of sib2, iclass 38, count 2 2006.201.02:16:15.40#ibcon#*after write, iclass 38, count 2 2006.201.02:16:15.40#ibcon#*before return 0, iclass 38, count 2 2006.201.02:16:15.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:15.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:15.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.02:16:15.40#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:15.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:15.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:15.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:15.52#ibcon#enter wrdev, iclass 38, count 0 2006.201.02:16:15.52#ibcon#first serial, iclass 38, count 0 2006.201.02:16:15.52#ibcon#enter sib2, iclass 38, count 0 2006.201.02:16:15.52#ibcon#flushed, iclass 38, count 0 2006.201.02:16:15.52#ibcon#about to write, iclass 38, count 0 2006.201.02:16:15.52#ibcon#wrote, iclass 38, count 0 2006.201.02:16:15.52#ibcon#about to read 3, iclass 38, count 0 2006.201.02:16:15.54#ibcon#read 3, iclass 38, count 0 2006.201.02:16:15.54#ibcon#about to read 4, iclass 38, count 0 2006.201.02:16:15.54#ibcon#read 4, iclass 38, count 0 2006.201.02:16:15.54#ibcon#about to read 5, iclass 38, count 0 2006.201.02:16:15.54#ibcon#read 5, iclass 38, count 0 2006.201.02:16:15.54#ibcon#about to read 6, iclass 38, count 0 2006.201.02:16:15.54#ibcon#read 6, iclass 38, count 0 2006.201.02:16:15.54#ibcon#end of sib2, iclass 38, count 0 2006.201.02:16:15.54#ibcon#*mode == 0, iclass 38, count 0 2006.201.02:16:15.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.02:16:15.54#ibcon#[25=USB\r\n] 2006.201.02:16:15.54#ibcon#*before write, iclass 38, count 0 2006.201.02:16:15.54#ibcon#enter sib2, iclass 38, count 0 2006.201.02:16:15.54#ibcon#flushed, iclass 38, count 0 2006.201.02:16:15.54#ibcon#about to write, iclass 38, count 0 2006.201.02:16:15.54#ibcon#wrote, iclass 38, count 0 2006.201.02:16:15.54#ibcon#about to read 3, iclass 38, count 0 2006.201.02:16:15.57#ibcon#read 3, iclass 38, count 0 2006.201.02:16:15.57#ibcon#about to read 4, iclass 38, count 0 2006.201.02:16:15.57#ibcon#read 4, iclass 38, count 0 2006.201.02:16:15.57#ibcon#about to read 5, iclass 38, count 0 2006.201.02:16:15.57#ibcon#read 5, iclass 38, count 0 2006.201.02:16:15.57#ibcon#about to read 6, iclass 38, count 0 2006.201.02:16:15.57#ibcon#read 6, iclass 38, count 0 2006.201.02:16:15.57#ibcon#end of sib2, iclass 38, count 0 2006.201.02:16:15.57#ibcon#*after write, iclass 38, count 0 2006.201.02:16:15.57#ibcon#*before return 0, iclass 38, count 0 2006.201.02:16:15.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:15.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:15.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.02:16:15.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.02:16:15.57$vck44/valo=8,884.99 2006.201.02:16:15.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.02:16:15.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.02:16:15.57#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:15.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:15.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:15.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:15.57#ibcon#enter wrdev, iclass 40, count 0 2006.201.02:16:15.57#ibcon#first serial, iclass 40, count 0 2006.201.02:16:15.57#ibcon#enter sib2, iclass 40, count 0 2006.201.02:16:15.57#ibcon#flushed, iclass 40, count 0 2006.201.02:16:15.57#ibcon#about to write, iclass 40, count 0 2006.201.02:16:15.57#ibcon#wrote, iclass 40, count 0 2006.201.02:16:15.57#ibcon#about to read 3, iclass 40, count 0 2006.201.02:16:15.59#ibcon#read 3, iclass 40, count 0 2006.201.02:16:15.59#ibcon#about to read 4, iclass 40, count 0 2006.201.02:16:15.59#ibcon#read 4, iclass 40, count 0 2006.201.02:16:15.59#ibcon#about to read 5, iclass 40, count 0 2006.201.02:16:15.59#ibcon#read 5, iclass 40, count 0 2006.201.02:16:15.59#ibcon#about to read 6, iclass 40, count 0 2006.201.02:16:15.59#ibcon#read 6, iclass 40, count 0 2006.201.02:16:15.59#ibcon#end of sib2, iclass 40, count 0 2006.201.02:16:15.59#ibcon#*mode == 0, iclass 40, count 0 2006.201.02:16:15.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.02:16:15.59#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:16:15.59#ibcon#*before write, iclass 40, count 0 2006.201.02:16:15.59#ibcon#enter sib2, iclass 40, count 0 2006.201.02:16:15.59#ibcon#flushed, iclass 40, count 0 2006.201.02:16:15.59#ibcon#about to write, iclass 40, count 0 2006.201.02:16:15.59#ibcon#wrote, iclass 40, count 0 2006.201.02:16:15.59#ibcon#about to read 3, iclass 40, count 0 2006.201.02:16:15.64#ibcon#read 3, iclass 40, count 0 2006.201.02:16:15.64#ibcon#about to read 4, iclass 40, count 0 2006.201.02:16:15.64#ibcon#read 4, iclass 40, count 0 2006.201.02:16:15.64#ibcon#about to read 5, iclass 40, count 0 2006.201.02:16:15.64#ibcon#read 5, iclass 40, count 0 2006.201.02:16:15.64#ibcon#about to read 6, iclass 40, count 0 2006.201.02:16:15.64#ibcon#read 6, iclass 40, count 0 2006.201.02:16:15.64#ibcon#end of sib2, iclass 40, count 0 2006.201.02:16:15.64#ibcon#*after write, iclass 40, count 0 2006.201.02:16:15.64#ibcon#*before return 0, iclass 40, count 0 2006.201.02:16:15.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:15.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:15.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.02:16:15.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.02:16:15.64$vck44/va=8,4 2006.201.02:16:15.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.02:16:15.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.02:16:15.64#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:15.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:16:15.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:16:15.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:16:15.69#ibcon#enter wrdev, iclass 4, count 2 2006.201.02:16:15.69#ibcon#first serial, iclass 4, count 2 2006.201.02:16:15.69#ibcon#enter sib2, iclass 4, count 2 2006.201.02:16:15.69#ibcon#flushed, iclass 4, count 2 2006.201.02:16:15.69#ibcon#about to write, iclass 4, count 2 2006.201.02:16:15.69#ibcon#wrote, iclass 4, count 2 2006.201.02:16:15.69#ibcon#about to read 3, iclass 4, count 2 2006.201.02:16:15.71#ibcon#read 3, iclass 4, count 2 2006.201.02:16:15.71#ibcon#about to read 4, iclass 4, count 2 2006.201.02:16:15.71#ibcon#read 4, iclass 4, count 2 2006.201.02:16:15.71#ibcon#about to read 5, iclass 4, count 2 2006.201.02:16:15.71#ibcon#read 5, iclass 4, count 2 2006.201.02:16:15.71#ibcon#about to read 6, iclass 4, count 2 2006.201.02:16:15.71#ibcon#read 6, iclass 4, count 2 2006.201.02:16:15.71#ibcon#end of sib2, iclass 4, count 2 2006.201.02:16:15.71#ibcon#*mode == 0, iclass 4, count 2 2006.201.02:16:15.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.02:16:15.71#ibcon#[25=AT08-04\r\n] 2006.201.02:16:15.71#ibcon#*before write, iclass 4, count 2 2006.201.02:16:15.71#ibcon#enter sib2, iclass 4, count 2 2006.201.02:16:15.71#ibcon#flushed, iclass 4, count 2 2006.201.02:16:15.71#ibcon#about to write, iclass 4, count 2 2006.201.02:16:15.71#ibcon#wrote, iclass 4, count 2 2006.201.02:16:15.71#ibcon#about to read 3, iclass 4, count 2 2006.201.02:16:15.74#ibcon#read 3, iclass 4, count 2 2006.201.02:16:15.74#ibcon#about to read 4, iclass 4, count 2 2006.201.02:16:15.74#ibcon#read 4, iclass 4, count 2 2006.201.02:16:15.74#ibcon#about to read 5, iclass 4, count 2 2006.201.02:16:15.74#ibcon#read 5, iclass 4, count 2 2006.201.02:16:15.74#ibcon#about to read 6, iclass 4, count 2 2006.201.02:16:15.74#ibcon#read 6, iclass 4, count 2 2006.201.02:16:15.74#ibcon#end of sib2, iclass 4, count 2 2006.201.02:16:15.74#ibcon#*after write, iclass 4, count 2 2006.201.02:16:15.74#ibcon#*before return 0, iclass 4, count 2 2006.201.02:16:15.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:16:15.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:16:15.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.02:16:15.74#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:15.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:16:15.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:16:15.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:16:15.86#ibcon#enter wrdev, iclass 4, count 0 2006.201.02:16:15.86#ibcon#first serial, iclass 4, count 0 2006.201.02:16:15.86#ibcon#enter sib2, iclass 4, count 0 2006.201.02:16:15.86#ibcon#flushed, iclass 4, count 0 2006.201.02:16:15.86#ibcon#about to write, iclass 4, count 0 2006.201.02:16:15.86#ibcon#wrote, iclass 4, count 0 2006.201.02:16:15.86#ibcon#about to read 3, iclass 4, count 0 2006.201.02:16:15.88#ibcon#read 3, iclass 4, count 0 2006.201.02:16:15.88#ibcon#about to read 4, iclass 4, count 0 2006.201.02:16:15.88#ibcon#read 4, iclass 4, count 0 2006.201.02:16:15.88#ibcon#about to read 5, iclass 4, count 0 2006.201.02:16:15.88#ibcon#read 5, iclass 4, count 0 2006.201.02:16:15.88#ibcon#about to read 6, iclass 4, count 0 2006.201.02:16:15.88#ibcon#read 6, iclass 4, count 0 2006.201.02:16:15.88#ibcon#end of sib2, iclass 4, count 0 2006.201.02:16:15.88#ibcon#*mode == 0, iclass 4, count 0 2006.201.02:16:15.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.02:16:15.88#ibcon#[25=USB\r\n] 2006.201.02:16:15.88#ibcon#*before write, iclass 4, count 0 2006.201.02:16:15.88#ibcon#enter sib2, iclass 4, count 0 2006.201.02:16:15.88#ibcon#flushed, iclass 4, count 0 2006.201.02:16:15.88#ibcon#about to write, iclass 4, count 0 2006.201.02:16:15.88#ibcon#wrote, iclass 4, count 0 2006.201.02:16:15.88#ibcon#about to read 3, iclass 4, count 0 2006.201.02:16:15.91#ibcon#read 3, iclass 4, count 0 2006.201.02:16:15.91#ibcon#about to read 4, iclass 4, count 0 2006.201.02:16:15.91#ibcon#read 4, iclass 4, count 0 2006.201.02:16:15.91#ibcon#about to read 5, iclass 4, count 0 2006.201.02:16:15.91#ibcon#read 5, iclass 4, count 0 2006.201.02:16:15.91#ibcon#about to read 6, iclass 4, count 0 2006.201.02:16:15.91#ibcon#read 6, iclass 4, count 0 2006.201.02:16:15.91#ibcon#end of sib2, iclass 4, count 0 2006.201.02:16:15.91#ibcon#*after write, iclass 4, count 0 2006.201.02:16:15.91#ibcon#*before return 0, iclass 4, count 0 2006.201.02:16:15.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:16:15.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:16:15.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.02:16:15.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.02:16:15.91$vck44/vblo=1,629.99 2006.201.02:16:15.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.02:16:15.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.02:16:15.91#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:15.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:16:15.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:16:15.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:16:15.91#ibcon#enter wrdev, iclass 6, count 0 2006.201.02:16:15.91#ibcon#first serial, iclass 6, count 0 2006.201.02:16:15.91#ibcon#enter sib2, iclass 6, count 0 2006.201.02:16:15.91#ibcon#flushed, iclass 6, count 0 2006.201.02:16:15.91#ibcon#about to write, iclass 6, count 0 2006.201.02:16:15.91#ibcon#wrote, iclass 6, count 0 2006.201.02:16:15.91#ibcon#about to read 3, iclass 6, count 0 2006.201.02:16:15.93#ibcon#read 3, iclass 6, count 0 2006.201.02:16:15.93#ibcon#about to read 4, iclass 6, count 0 2006.201.02:16:15.93#ibcon#read 4, iclass 6, count 0 2006.201.02:16:15.93#ibcon#about to read 5, iclass 6, count 0 2006.201.02:16:15.93#ibcon#read 5, iclass 6, count 0 2006.201.02:16:15.93#ibcon#about to read 6, iclass 6, count 0 2006.201.02:16:15.93#ibcon#read 6, iclass 6, count 0 2006.201.02:16:15.93#ibcon#end of sib2, iclass 6, count 0 2006.201.02:16:15.93#ibcon#*mode == 0, iclass 6, count 0 2006.201.02:16:15.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.02:16:15.93#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:16:15.93#ibcon#*before write, iclass 6, count 0 2006.201.02:16:15.93#ibcon#enter sib2, iclass 6, count 0 2006.201.02:16:15.93#ibcon#flushed, iclass 6, count 0 2006.201.02:16:15.93#ibcon#about to write, iclass 6, count 0 2006.201.02:16:15.93#ibcon#wrote, iclass 6, count 0 2006.201.02:16:15.93#ibcon#about to read 3, iclass 6, count 0 2006.201.02:16:15.97#ibcon#read 3, iclass 6, count 0 2006.201.02:16:15.97#ibcon#about to read 4, iclass 6, count 0 2006.201.02:16:15.97#ibcon#read 4, iclass 6, count 0 2006.201.02:16:15.97#ibcon#about to read 5, iclass 6, count 0 2006.201.02:16:15.97#ibcon#read 5, iclass 6, count 0 2006.201.02:16:15.97#ibcon#about to read 6, iclass 6, count 0 2006.201.02:16:15.97#ibcon#read 6, iclass 6, count 0 2006.201.02:16:15.97#ibcon#end of sib2, iclass 6, count 0 2006.201.02:16:15.97#ibcon#*after write, iclass 6, count 0 2006.201.02:16:15.97#ibcon#*before return 0, iclass 6, count 0 2006.201.02:16:15.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:16:15.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:16:15.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.02:16:15.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.02:16:15.97$vck44/vb=1,4 2006.201.02:16:15.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.02:16:15.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.02:16:15.97#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:15.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:16:15.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:16:15.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:16:15.97#ibcon#enter wrdev, iclass 10, count 2 2006.201.02:16:15.97#ibcon#first serial, iclass 10, count 2 2006.201.02:16:15.97#ibcon#enter sib2, iclass 10, count 2 2006.201.02:16:15.97#ibcon#flushed, iclass 10, count 2 2006.201.02:16:15.97#ibcon#about to write, iclass 10, count 2 2006.201.02:16:15.97#ibcon#wrote, iclass 10, count 2 2006.201.02:16:15.97#ibcon#about to read 3, iclass 10, count 2 2006.201.02:16:15.99#ibcon#read 3, iclass 10, count 2 2006.201.02:16:15.99#ibcon#about to read 4, iclass 10, count 2 2006.201.02:16:15.99#ibcon#read 4, iclass 10, count 2 2006.201.02:16:15.99#ibcon#about to read 5, iclass 10, count 2 2006.201.02:16:15.99#ibcon#read 5, iclass 10, count 2 2006.201.02:16:15.99#ibcon#about to read 6, iclass 10, count 2 2006.201.02:16:15.99#ibcon#read 6, iclass 10, count 2 2006.201.02:16:15.99#ibcon#end of sib2, iclass 10, count 2 2006.201.02:16:15.99#ibcon#*mode == 0, iclass 10, count 2 2006.201.02:16:15.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.02:16:15.99#ibcon#[27=AT01-04\r\n] 2006.201.02:16:15.99#ibcon#*before write, iclass 10, count 2 2006.201.02:16:15.99#ibcon#enter sib2, iclass 10, count 2 2006.201.02:16:15.99#ibcon#flushed, iclass 10, count 2 2006.201.02:16:15.99#ibcon#about to write, iclass 10, count 2 2006.201.02:16:15.99#ibcon#wrote, iclass 10, count 2 2006.201.02:16:15.99#ibcon#about to read 3, iclass 10, count 2 2006.201.02:16:16.02#ibcon#read 3, iclass 10, count 2 2006.201.02:16:16.02#ibcon#about to read 4, iclass 10, count 2 2006.201.02:16:16.02#ibcon#read 4, iclass 10, count 2 2006.201.02:16:16.02#ibcon#about to read 5, iclass 10, count 2 2006.201.02:16:16.02#ibcon#read 5, iclass 10, count 2 2006.201.02:16:16.02#ibcon#about to read 6, iclass 10, count 2 2006.201.02:16:16.02#ibcon#read 6, iclass 10, count 2 2006.201.02:16:16.02#ibcon#end of sib2, iclass 10, count 2 2006.201.02:16:16.02#ibcon#*after write, iclass 10, count 2 2006.201.02:16:16.02#ibcon#*before return 0, iclass 10, count 2 2006.201.02:16:16.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:16:16.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:16:16.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.02:16:16.02#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:16.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:16:16.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:16:16.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:16:16.14#ibcon#enter wrdev, iclass 10, count 0 2006.201.02:16:16.14#ibcon#first serial, iclass 10, count 0 2006.201.02:16:16.14#ibcon#enter sib2, iclass 10, count 0 2006.201.02:16:16.14#ibcon#flushed, iclass 10, count 0 2006.201.02:16:16.14#ibcon#about to write, iclass 10, count 0 2006.201.02:16:16.14#ibcon#wrote, iclass 10, count 0 2006.201.02:16:16.14#ibcon#about to read 3, iclass 10, count 0 2006.201.02:16:16.16#ibcon#read 3, iclass 10, count 0 2006.201.02:16:16.16#ibcon#about to read 4, iclass 10, count 0 2006.201.02:16:16.16#ibcon#read 4, iclass 10, count 0 2006.201.02:16:16.16#ibcon#about to read 5, iclass 10, count 0 2006.201.02:16:16.16#ibcon#read 5, iclass 10, count 0 2006.201.02:16:16.16#ibcon#about to read 6, iclass 10, count 0 2006.201.02:16:16.16#ibcon#read 6, iclass 10, count 0 2006.201.02:16:16.16#ibcon#end of sib2, iclass 10, count 0 2006.201.02:16:16.16#ibcon#*mode == 0, iclass 10, count 0 2006.201.02:16:16.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.02:16:16.16#ibcon#[27=USB\r\n] 2006.201.02:16:16.16#ibcon#*before write, iclass 10, count 0 2006.201.02:16:16.16#ibcon#enter sib2, iclass 10, count 0 2006.201.02:16:16.16#ibcon#flushed, iclass 10, count 0 2006.201.02:16:16.16#ibcon#about to write, iclass 10, count 0 2006.201.02:16:16.16#ibcon#wrote, iclass 10, count 0 2006.201.02:16:16.16#ibcon#about to read 3, iclass 10, count 0 2006.201.02:16:16.19#ibcon#read 3, iclass 10, count 0 2006.201.02:16:16.19#ibcon#about to read 4, iclass 10, count 0 2006.201.02:16:16.19#ibcon#read 4, iclass 10, count 0 2006.201.02:16:16.19#ibcon#about to read 5, iclass 10, count 0 2006.201.02:16:16.19#ibcon#read 5, iclass 10, count 0 2006.201.02:16:16.19#ibcon#about to read 6, iclass 10, count 0 2006.201.02:16:16.19#ibcon#read 6, iclass 10, count 0 2006.201.02:16:16.19#ibcon#end of sib2, iclass 10, count 0 2006.201.02:16:16.19#ibcon#*after write, iclass 10, count 0 2006.201.02:16:16.19#ibcon#*before return 0, iclass 10, count 0 2006.201.02:16:16.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:16:16.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:16:16.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.02:16:16.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.02:16:16.19$vck44/vblo=2,634.99 2006.201.02:16:16.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.02:16:16.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.02:16:16.19#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:16.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:16.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:16.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:16.19#ibcon#enter wrdev, iclass 12, count 0 2006.201.02:16:16.19#ibcon#first serial, iclass 12, count 0 2006.201.02:16:16.19#ibcon#enter sib2, iclass 12, count 0 2006.201.02:16:16.19#ibcon#flushed, iclass 12, count 0 2006.201.02:16:16.19#ibcon#about to write, iclass 12, count 0 2006.201.02:16:16.19#ibcon#wrote, iclass 12, count 0 2006.201.02:16:16.19#ibcon#about to read 3, iclass 12, count 0 2006.201.02:16:16.21#ibcon#read 3, iclass 12, count 0 2006.201.02:16:16.21#ibcon#about to read 4, iclass 12, count 0 2006.201.02:16:16.21#ibcon#read 4, iclass 12, count 0 2006.201.02:16:16.21#ibcon#about to read 5, iclass 12, count 0 2006.201.02:16:16.21#ibcon#read 5, iclass 12, count 0 2006.201.02:16:16.21#ibcon#about to read 6, iclass 12, count 0 2006.201.02:16:16.21#ibcon#read 6, iclass 12, count 0 2006.201.02:16:16.21#ibcon#end of sib2, iclass 12, count 0 2006.201.02:16:16.21#ibcon#*mode == 0, iclass 12, count 0 2006.201.02:16:16.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.02:16:16.21#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:16:16.21#ibcon#*before write, iclass 12, count 0 2006.201.02:16:16.21#ibcon#enter sib2, iclass 12, count 0 2006.201.02:16:16.21#ibcon#flushed, iclass 12, count 0 2006.201.02:16:16.21#ibcon#about to write, iclass 12, count 0 2006.201.02:16:16.21#ibcon#wrote, iclass 12, count 0 2006.201.02:16:16.21#ibcon#about to read 3, iclass 12, count 0 2006.201.02:16:16.25#ibcon#read 3, iclass 12, count 0 2006.201.02:16:16.25#ibcon#about to read 4, iclass 12, count 0 2006.201.02:16:16.25#ibcon#read 4, iclass 12, count 0 2006.201.02:16:16.25#ibcon#about to read 5, iclass 12, count 0 2006.201.02:16:16.25#ibcon#read 5, iclass 12, count 0 2006.201.02:16:16.25#ibcon#about to read 6, iclass 12, count 0 2006.201.02:16:16.25#ibcon#read 6, iclass 12, count 0 2006.201.02:16:16.25#ibcon#end of sib2, iclass 12, count 0 2006.201.02:16:16.25#ibcon#*after write, iclass 12, count 0 2006.201.02:16:16.25#ibcon#*before return 0, iclass 12, count 0 2006.201.02:16:16.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:16.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:16:16.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.02:16:16.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.02:16:16.25$vck44/vb=2,5 2006.201.02:16:16.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.02:16:16.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.02:16:16.25#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:16.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:16.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:16.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:16.31#ibcon#enter wrdev, iclass 14, count 2 2006.201.02:16:16.31#ibcon#first serial, iclass 14, count 2 2006.201.02:16:16.31#ibcon#enter sib2, iclass 14, count 2 2006.201.02:16:16.31#ibcon#flushed, iclass 14, count 2 2006.201.02:16:16.31#ibcon#about to write, iclass 14, count 2 2006.201.02:16:16.31#ibcon#wrote, iclass 14, count 2 2006.201.02:16:16.31#ibcon#about to read 3, iclass 14, count 2 2006.201.02:16:16.33#ibcon#read 3, iclass 14, count 2 2006.201.02:16:16.33#ibcon#about to read 4, iclass 14, count 2 2006.201.02:16:16.33#ibcon#read 4, iclass 14, count 2 2006.201.02:16:16.33#ibcon#about to read 5, iclass 14, count 2 2006.201.02:16:16.33#ibcon#read 5, iclass 14, count 2 2006.201.02:16:16.33#ibcon#about to read 6, iclass 14, count 2 2006.201.02:16:16.33#ibcon#read 6, iclass 14, count 2 2006.201.02:16:16.33#ibcon#end of sib2, iclass 14, count 2 2006.201.02:16:16.33#ibcon#*mode == 0, iclass 14, count 2 2006.201.02:16:16.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.02:16:16.33#ibcon#[27=AT02-05\r\n] 2006.201.02:16:16.33#ibcon#*before write, iclass 14, count 2 2006.201.02:16:16.33#ibcon#enter sib2, iclass 14, count 2 2006.201.02:16:16.33#ibcon#flushed, iclass 14, count 2 2006.201.02:16:16.33#ibcon#about to write, iclass 14, count 2 2006.201.02:16:16.33#ibcon#wrote, iclass 14, count 2 2006.201.02:16:16.33#ibcon#about to read 3, iclass 14, count 2 2006.201.02:16:16.36#ibcon#read 3, iclass 14, count 2 2006.201.02:16:16.36#ibcon#about to read 4, iclass 14, count 2 2006.201.02:16:16.36#ibcon#read 4, iclass 14, count 2 2006.201.02:16:16.36#ibcon#about to read 5, iclass 14, count 2 2006.201.02:16:16.36#ibcon#read 5, iclass 14, count 2 2006.201.02:16:16.36#ibcon#about to read 6, iclass 14, count 2 2006.201.02:16:16.36#ibcon#read 6, iclass 14, count 2 2006.201.02:16:16.36#ibcon#end of sib2, iclass 14, count 2 2006.201.02:16:16.36#ibcon#*after write, iclass 14, count 2 2006.201.02:16:16.36#ibcon#*before return 0, iclass 14, count 2 2006.201.02:16:16.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:16.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:16:16.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.02:16:16.36#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:16.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:16.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:16.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:16.48#ibcon#enter wrdev, iclass 14, count 0 2006.201.02:16:16.48#ibcon#first serial, iclass 14, count 0 2006.201.02:16:16.48#ibcon#enter sib2, iclass 14, count 0 2006.201.02:16:16.48#ibcon#flushed, iclass 14, count 0 2006.201.02:16:16.48#ibcon#about to write, iclass 14, count 0 2006.201.02:16:16.48#ibcon#wrote, iclass 14, count 0 2006.201.02:16:16.48#ibcon#about to read 3, iclass 14, count 0 2006.201.02:16:16.50#ibcon#read 3, iclass 14, count 0 2006.201.02:16:16.50#ibcon#about to read 4, iclass 14, count 0 2006.201.02:16:16.50#ibcon#read 4, iclass 14, count 0 2006.201.02:16:16.50#ibcon#about to read 5, iclass 14, count 0 2006.201.02:16:16.50#ibcon#read 5, iclass 14, count 0 2006.201.02:16:16.50#ibcon#about to read 6, iclass 14, count 0 2006.201.02:16:16.50#ibcon#read 6, iclass 14, count 0 2006.201.02:16:16.50#ibcon#end of sib2, iclass 14, count 0 2006.201.02:16:16.50#ibcon#*mode == 0, iclass 14, count 0 2006.201.02:16:16.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.02:16:16.50#ibcon#[27=USB\r\n] 2006.201.02:16:16.50#ibcon#*before write, iclass 14, count 0 2006.201.02:16:16.50#ibcon#enter sib2, iclass 14, count 0 2006.201.02:16:16.50#ibcon#flushed, iclass 14, count 0 2006.201.02:16:16.50#ibcon#about to write, iclass 14, count 0 2006.201.02:16:16.50#ibcon#wrote, iclass 14, count 0 2006.201.02:16:16.50#ibcon#about to read 3, iclass 14, count 0 2006.201.02:16:16.53#ibcon#read 3, iclass 14, count 0 2006.201.02:16:16.53#ibcon#about to read 4, iclass 14, count 0 2006.201.02:16:16.53#ibcon#read 4, iclass 14, count 0 2006.201.02:16:16.53#ibcon#about to read 5, iclass 14, count 0 2006.201.02:16:16.53#ibcon#read 5, iclass 14, count 0 2006.201.02:16:16.53#ibcon#about to read 6, iclass 14, count 0 2006.201.02:16:16.53#ibcon#read 6, iclass 14, count 0 2006.201.02:16:16.53#ibcon#end of sib2, iclass 14, count 0 2006.201.02:16:16.53#ibcon#*after write, iclass 14, count 0 2006.201.02:16:16.53#ibcon#*before return 0, iclass 14, count 0 2006.201.02:16:16.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:16.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:16:16.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.02:16:16.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.02:16:16.53$vck44/vblo=3,649.99 2006.201.02:16:16.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.02:16:16.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.02:16:16.53#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:16.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:16.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:16.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:16.53#ibcon#enter wrdev, iclass 16, count 0 2006.201.02:16:16.53#ibcon#first serial, iclass 16, count 0 2006.201.02:16:16.53#ibcon#enter sib2, iclass 16, count 0 2006.201.02:16:16.53#ibcon#flushed, iclass 16, count 0 2006.201.02:16:16.53#ibcon#about to write, iclass 16, count 0 2006.201.02:16:16.53#ibcon#wrote, iclass 16, count 0 2006.201.02:16:16.53#ibcon#about to read 3, iclass 16, count 0 2006.201.02:16:16.55#ibcon#read 3, iclass 16, count 0 2006.201.02:16:16.55#ibcon#about to read 4, iclass 16, count 0 2006.201.02:16:16.55#ibcon#read 4, iclass 16, count 0 2006.201.02:16:16.55#ibcon#about to read 5, iclass 16, count 0 2006.201.02:16:16.55#ibcon#read 5, iclass 16, count 0 2006.201.02:16:16.55#ibcon#about to read 6, iclass 16, count 0 2006.201.02:16:16.55#ibcon#read 6, iclass 16, count 0 2006.201.02:16:16.55#ibcon#end of sib2, iclass 16, count 0 2006.201.02:16:16.55#ibcon#*mode == 0, iclass 16, count 0 2006.201.02:16:16.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.02:16:16.55#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:16:16.55#ibcon#*before write, iclass 16, count 0 2006.201.02:16:16.55#ibcon#enter sib2, iclass 16, count 0 2006.201.02:16:16.55#ibcon#flushed, iclass 16, count 0 2006.201.02:16:16.55#ibcon#about to write, iclass 16, count 0 2006.201.02:16:16.55#ibcon#wrote, iclass 16, count 0 2006.201.02:16:16.55#ibcon#about to read 3, iclass 16, count 0 2006.201.02:16:16.59#ibcon#read 3, iclass 16, count 0 2006.201.02:16:16.59#ibcon#about to read 4, iclass 16, count 0 2006.201.02:16:16.59#ibcon#read 4, iclass 16, count 0 2006.201.02:16:16.59#ibcon#about to read 5, iclass 16, count 0 2006.201.02:16:16.59#ibcon#read 5, iclass 16, count 0 2006.201.02:16:16.59#ibcon#about to read 6, iclass 16, count 0 2006.201.02:16:16.59#ibcon#read 6, iclass 16, count 0 2006.201.02:16:16.59#ibcon#end of sib2, iclass 16, count 0 2006.201.02:16:16.59#ibcon#*after write, iclass 16, count 0 2006.201.02:16:16.59#ibcon#*before return 0, iclass 16, count 0 2006.201.02:16:16.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:16.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:16:16.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.02:16:16.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.02:16:16.59$vck44/vb=3,4 2006.201.02:16:16.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.02:16:16.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.02:16:16.59#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:16.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:16.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:16.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:16.65#ibcon#enter wrdev, iclass 18, count 2 2006.201.02:16:16.65#ibcon#first serial, iclass 18, count 2 2006.201.02:16:16.65#ibcon#enter sib2, iclass 18, count 2 2006.201.02:16:16.65#ibcon#flushed, iclass 18, count 2 2006.201.02:16:16.65#ibcon#about to write, iclass 18, count 2 2006.201.02:16:16.65#ibcon#wrote, iclass 18, count 2 2006.201.02:16:16.65#ibcon#about to read 3, iclass 18, count 2 2006.201.02:16:16.67#ibcon#read 3, iclass 18, count 2 2006.201.02:16:16.67#ibcon#about to read 4, iclass 18, count 2 2006.201.02:16:16.67#ibcon#read 4, iclass 18, count 2 2006.201.02:16:16.67#ibcon#about to read 5, iclass 18, count 2 2006.201.02:16:16.67#ibcon#read 5, iclass 18, count 2 2006.201.02:16:16.67#ibcon#about to read 6, iclass 18, count 2 2006.201.02:16:16.67#ibcon#read 6, iclass 18, count 2 2006.201.02:16:16.67#ibcon#end of sib2, iclass 18, count 2 2006.201.02:16:16.67#ibcon#*mode == 0, iclass 18, count 2 2006.201.02:16:16.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.02:16:16.67#ibcon#[27=AT03-04\r\n] 2006.201.02:16:16.67#ibcon#*before write, iclass 18, count 2 2006.201.02:16:16.67#ibcon#enter sib2, iclass 18, count 2 2006.201.02:16:16.67#ibcon#flushed, iclass 18, count 2 2006.201.02:16:16.67#ibcon#about to write, iclass 18, count 2 2006.201.02:16:16.67#ibcon#wrote, iclass 18, count 2 2006.201.02:16:16.67#ibcon#about to read 3, iclass 18, count 2 2006.201.02:16:16.70#ibcon#read 3, iclass 18, count 2 2006.201.02:16:16.70#ibcon#about to read 4, iclass 18, count 2 2006.201.02:16:16.70#ibcon#read 4, iclass 18, count 2 2006.201.02:16:16.70#ibcon#about to read 5, iclass 18, count 2 2006.201.02:16:16.70#ibcon#read 5, iclass 18, count 2 2006.201.02:16:16.70#ibcon#about to read 6, iclass 18, count 2 2006.201.02:16:16.70#ibcon#read 6, iclass 18, count 2 2006.201.02:16:16.70#ibcon#end of sib2, iclass 18, count 2 2006.201.02:16:16.70#ibcon#*after write, iclass 18, count 2 2006.201.02:16:16.70#ibcon#*before return 0, iclass 18, count 2 2006.201.02:16:16.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:16.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:16:16.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.02:16:16.70#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:16.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:16.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:16.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:16.82#ibcon#enter wrdev, iclass 18, count 0 2006.201.02:16:16.82#ibcon#first serial, iclass 18, count 0 2006.201.02:16:16.82#ibcon#enter sib2, iclass 18, count 0 2006.201.02:16:16.82#ibcon#flushed, iclass 18, count 0 2006.201.02:16:16.82#ibcon#about to write, iclass 18, count 0 2006.201.02:16:16.82#ibcon#wrote, iclass 18, count 0 2006.201.02:16:16.82#ibcon#about to read 3, iclass 18, count 0 2006.201.02:16:16.84#ibcon#read 3, iclass 18, count 0 2006.201.02:16:16.84#ibcon#about to read 4, iclass 18, count 0 2006.201.02:16:16.84#ibcon#read 4, iclass 18, count 0 2006.201.02:16:16.84#ibcon#about to read 5, iclass 18, count 0 2006.201.02:16:16.84#ibcon#read 5, iclass 18, count 0 2006.201.02:16:16.84#ibcon#about to read 6, iclass 18, count 0 2006.201.02:16:16.84#ibcon#read 6, iclass 18, count 0 2006.201.02:16:16.84#ibcon#end of sib2, iclass 18, count 0 2006.201.02:16:16.84#ibcon#*mode == 0, iclass 18, count 0 2006.201.02:16:16.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.02:16:16.84#ibcon#[27=USB\r\n] 2006.201.02:16:16.84#ibcon#*before write, iclass 18, count 0 2006.201.02:16:16.84#ibcon#enter sib2, iclass 18, count 0 2006.201.02:16:16.84#ibcon#flushed, iclass 18, count 0 2006.201.02:16:16.84#ibcon#about to write, iclass 18, count 0 2006.201.02:16:16.84#ibcon#wrote, iclass 18, count 0 2006.201.02:16:16.84#ibcon#about to read 3, iclass 18, count 0 2006.201.02:16:16.87#ibcon#read 3, iclass 18, count 0 2006.201.02:16:16.87#ibcon#about to read 4, iclass 18, count 0 2006.201.02:16:16.87#ibcon#read 4, iclass 18, count 0 2006.201.02:16:16.87#ibcon#about to read 5, iclass 18, count 0 2006.201.02:16:16.87#ibcon#read 5, iclass 18, count 0 2006.201.02:16:16.87#ibcon#about to read 6, iclass 18, count 0 2006.201.02:16:16.87#ibcon#read 6, iclass 18, count 0 2006.201.02:16:16.87#ibcon#end of sib2, iclass 18, count 0 2006.201.02:16:16.87#ibcon#*after write, iclass 18, count 0 2006.201.02:16:16.87#ibcon#*before return 0, iclass 18, count 0 2006.201.02:16:16.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:16.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:16:16.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.02:16:16.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.02:16:16.87$vck44/vblo=4,679.99 2006.201.02:16:16.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.02:16:16.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.02:16:16.87#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:16.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:16.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:16.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:16.87#ibcon#enter wrdev, iclass 20, count 0 2006.201.02:16:16.87#ibcon#first serial, iclass 20, count 0 2006.201.02:16:16.87#ibcon#enter sib2, iclass 20, count 0 2006.201.02:16:16.87#ibcon#flushed, iclass 20, count 0 2006.201.02:16:16.87#ibcon#about to write, iclass 20, count 0 2006.201.02:16:16.87#ibcon#wrote, iclass 20, count 0 2006.201.02:16:16.87#ibcon#about to read 3, iclass 20, count 0 2006.201.02:16:16.89#ibcon#read 3, iclass 20, count 0 2006.201.02:16:16.89#ibcon#about to read 4, iclass 20, count 0 2006.201.02:16:16.89#ibcon#read 4, iclass 20, count 0 2006.201.02:16:16.89#ibcon#about to read 5, iclass 20, count 0 2006.201.02:16:16.89#ibcon#read 5, iclass 20, count 0 2006.201.02:16:16.89#ibcon#about to read 6, iclass 20, count 0 2006.201.02:16:16.89#ibcon#read 6, iclass 20, count 0 2006.201.02:16:16.89#ibcon#end of sib2, iclass 20, count 0 2006.201.02:16:16.89#ibcon#*mode == 0, iclass 20, count 0 2006.201.02:16:16.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.02:16:16.89#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:16:16.89#ibcon#*before write, iclass 20, count 0 2006.201.02:16:16.89#ibcon#enter sib2, iclass 20, count 0 2006.201.02:16:16.89#ibcon#flushed, iclass 20, count 0 2006.201.02:16:16.89#ibcon#about to write, iclass 20, count 0 2006.201.02:16:16.89#ibcon#wrote, iclass 20, count 0 2006.201.02:16:16.89#ibcon#about to read 3, iclass 20, count 0 2006.201.02:16:16.93#ibcon#read 3, iclass 20, count 0 2006.201.02:16:16.93#ibcon#about to read 4, iclass 20, count 0 2006.201.02:16:16.93#ibcon#read 4, iclass 20, count 0 2006.201.02:16:16.93#ibcon#about to read 5, iclass 20, count 0 2006.201.02:16:16.93#ibcon#read 5, iclass 20, count 0 2006.201.02:16:16.93#ibcon#about to read 6, iclass 20, count 0 2006.201.02:16:16.93#ibcon#read 6, iclass 20, count 0 2006.201.02:16:16.93#ibcon#end of sib2, iclass 20, count 0 2006.201.02:16:16.93#ibcon#*after write, iclass 20, count 0 2006.201.02:16:16.93#ibcon#*before return 0, iclass 20, count 0 2006.201.02:16:16.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:16.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:16:16.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.02:16:16.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.02:16:16.93$vck44/vb=4,5 2006.201.02:16:16.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.02:16:16.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.02:16:16.93#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:16.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:16.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:16.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:16.99#ibcon#enter wrdev, iclass 22, count 2 2006.201.02:16:16.99#ibcon#first serial, iclass 22, count 2 2006.201.02:16:16.99#ibcon#enter sib2, iclass 22, count 2 2006.201.02:16:16.99#ibcon#flushed, iclass 22, count 2 2006.201.02:16:16.99#ibcon#about to write, iclass 22, count 2 2006.201.02:16:16.99#ibcon#wrote, iclass 22, count 2 2006.201.02:16:16.99#ibcon#about to read 3, iclass 22, count 2 2006.201.02:16:17.01#ibcon#read 3, iclass 22, count 2 2006.201.02:16:17.01#ibcon#about to read 4, iclass 22, count 2 2006.201.02:16:17.01#ibcon#read 4, iclass 22, count 2 2006.201.02:16:17.01#ibcon#about to read 5, iclass 22, count 2 2006.201.02:16:17.01#ibcon#read 5, iclass 22, count 2 2006.201.02:16:17.01#ibcon#about to read 6, iclass 22, count 2 2006.201.02:16:17.01#ibcon#read 6, iclass 22, count 2 2006.201.02:16:17.01#ibcon#end of sib2, iclass 22, count 2 2006.201.02:16:17.01#ibcon#*mode == 0, iclass 22, count 2 2006.201.02:16:17.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.02:16:17.01#ibcon#[27=AT04-05\r\n] 2006.201.02:16:17.01#ibcon#*before write, iclass 22, count 2 2006.201.02:16:17.01#ibcon#enter sib2, iclass 22, count 2 2006.201.02:16:17.01#ibcon#flushed, iclass 22, count 2 2006.201.02:16:17.01#ibcon#about to write, iclass 22, count 2 2006.201.02:16:17.01#ibcon#wrote, iclass 22, count 2 2006.201.02:16:17.01#ibcon#about to read 3, iclass 22, count 2 2006.201.02:16:17.04#ibcon#read 3, iclass 22, count 2 2006.201.02:16:17.04#ibcon#about to read 4, iclass 22, count 2 2006.201.02:16:17.04#ibcon#read 4, iclass 22, count 2 2006.201.02:16:17.04#ibcon#about to read 5, iclass 22, count 2 2006.201.02:16:17.04#ibcon#read 5, iclass 22, count 2 2006.201.02:16:17.04#ibcon#about to read 6, iclass 22, count 2 2006.201.02:16:17.04#ibcon#read 6, iclass 22, count 2 2006.201.02:16:17.04#ibcon#end of sib2, iclass 22, count 2 2006.201.02:16:17.04#ibcon#*after write, iclass 22, count 2 2006.201.02:16:17.04#ibcon#*before return 0, iclass 22, count 2 2006.201.02:16:17.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:17.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:16:17.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.02:16:17.04#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:17.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:17.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:17.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:17.16#ibcon#enter wrdev, iclass 22, count 0 2006.201.02:16:17.16#ibcon#first serial, iclass 22, count 0 2006.201.02:16:17.16#ibcon#enter sib2, iclass 22, count 0 2006.201.02:16:17.16#ibcon#flushed, iclass 22, count 0 2006.201.02:16:17.16#ibcon#about to write, iclass 22, count 0 2006.201.02:16:17.16#ibcon#wrote, iclass 22, count 0 2006.201.02:16:17.16#ibcon#about to read 3, iclass 22, count 0 2006.201.02:16:17.18#ibcon#read 3, iclass 22, count 0 2006.201.02:16:17.18#ibcon#about to read 4, iclass 22, count 0 2006.201.02:16:17.18#ibcon#read 4, iclass 22, count 0 2006.201.02:16:17.18#ibcon#about to read 5, iclass 22, count 0 2006.201.02:16:17.18#ibcon#read 5, iclass 22, count 0 2006.201.02:16:17.18#ibcon#about to read 6, iclass 22, count 0 2006.201.02:16:17.18#ibcon#read 6, iclass 22, count 0 2006.201.02:16:17.18#ibcon#end of sib2, iclass 22, count 0 2006.201.02:16:17.18#ibcon#*mode == 0, iclass 22, count 0 2006.201.02:16:17.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.02:16:17.18#ibcon#[27=USB\r\n] 2006.201.02:16:17.18#ibcon#*before write, iclass 22, count 0 2006.201.02:16:17.18#ibcon#enter sib2, iclass 22, count 0 2006.201.02:16:17.18#ibcon#flushed, iclass 22, count 0 2006.201.02:16:17.18#ibcon#about to write, iclass 22, count 0 2006.201.02:16:17.18#ibcon#wrote, iclass 22, count 0 2006.201.02:16:17.18#ibcon#about to read 3, iclass 22, count 0 2006.201.02:16:17.21#ibcon#read 3, iclass 22, count 0 2006.201.02:16:17.21#ibcon#about to read 4, iclass 22, count 0 2006.201.02:16:17.21#ibcon#read 4, iclass 22, count 0 2006.201.02:16:17.21#ibcon#about to read 5, iclass 22, count 0 2006.201.02:16:17.21#ibcon#read 5, iclass 22, count 0 2006.201.02:16:17.21#ibcon#about to read 6, iclass 22, count 0 2006.201.02:16:17.21#ibcon#read 6, iclass 22, count 0 2006.201.02:16:17.21#ibcon#end of sib2, iclass 22, count 0 2006.201.02:16:17.21#ibcon#*after write, iclass 22, count 0 2006.201.02:16:17.21#ibcon#*before return 0, iclass 22, count 0 2006.201.02:16:17.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:17.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:16:17.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.02:16:17.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.02:16:17.21$vck44/vblo=5,709.99 2006.201.02:16:17.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.02:16:17.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.02:16:17.21#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:17.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:17.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:17.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:17.21#ibcon#enter wrdev, iclass 24, count 0 2006.201.02:16:17.21#ibcon#first serial, iclass 24, count 0 2006.201.02:16:17.21#ibcon#enter sib2, iclass 24, count 0 2006.201.02:16:17.21#ibcon#flushed, iclass 24, count 0 2006.201.02:16:17.21#ibcon#about to write, iclass 24, count 0 2006.201.02:16:17.21#ibcon#wrote, iclass 24, count 0 2006.201.02:16:17.21#ibcon#about to read 3, iclass 24, count 0 2006.201.02:16:17.23#ibcon#read 3, iclass 24, count 0 2006.201.02:16:17.23#ibcon#about to read 4, iclass 24, count 0 2006.201.02:16:17.23#ibcon#read 4, iclass 24, count 0 2006.201.02:16:17.23#ibcon#about to read 5, iclass 24, count 0 2006.201.02:16:17.23#ibcon#read 5, iclass 24, count 0 2006.201.02:16:17.23#ibcon#about to read 6, iclass 24, count 0 2006.201.02:16:17.23#ibcon#read 6, iclass 24, count 0 2006.201.02:16:17.23#ibcon#end of sib2, iclass 24, count 0 2006.201.02:16:17.23#ibcon#*mode == 0, iclass 24, count 0 2006.201.02:16:17.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.02:16:17.23#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:16:17.23#ibcon#*before write, iclass 24, count 0 2006.201.02:16:17.23#ibcon#enter sib2, iclass 24, count 0 2006.201.02:16:17.23#ibcon#flushed, iclass 24, count 0 2006.201.02:16:17.23#ibcon#about to write, iclass 24, count 0 2006.201.02:16:17.23#ibcon#wrote, iclass 24, count 0 2006.201.02:16:17.23#ibcon#about to read 3, iclass 24, count 0 2006.201.02:16:17.27#ibcon#read 3, iclass 24, count 0 2006.201.02:16:17.27#ibcon#about to read 4, iclass 24, count 0 2006.201.02:16:17.27#ibcon#read 4, iclass 24, count 0 2006.201.02:16:17.27#ibcon#about to read 5, iclass 24, count 0 2006.201.02:16:17.27#ibcon#read 5, iclass 24, count 0 2006.201.02:16:17.27#ibcon#about to read 6, iclass 24, count 0 2006.201.02:16:17.27#ibcon#read 6, iclass 24, count 0 2006.201.02:16:17.27#ibcon#end of sib2, iclass 24, count 0 2006.201.02:16:17.27#ibcon#*after write, iclass 24, count 0 2006.201.02:16:17.27#ibcon#*before return 0, iclass 24, count 0 2006.201.02:16:17.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:17.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:16:17.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.02:16:17.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.02:16:17.27$vck44/vb=5,4 2006.201.02:16:17.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.02:16:17.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.02:16:17.27#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:17.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:17.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:17.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:17.33#ibcon#enter wrdev, iclass 26, count 2 2006.201.02:16:17.33#ibcon#first serial, iclass 26, count 2 2006.201.02:16:17.33#ibcon#enter sib2, iclass 26, count 2 2006.201.02:16:17.33#ibcon#flushed, iclass 26, count 2 2006.201.02:16:17.33#ibcon#about to write, iclass 26, count 2 2006.201.02:16:17.33#ibcon#wrote, iclass 26, count 2 2006.201.02:16:17.33#ibcon#about to read 3, iclass 26, count 2 2006.201.02:16:17.35#ibcon#read 3, iclass 26, count 2 2006.201.02:16:17.35#ibcon#about to read 4, iclass 26, count 2 2006.201.02:16:17.35#ibcon#read 4, iclass 26, count 2 2006.201.02:16:17.35#ibcon#about to read 5, iclass 26, count 2 2006.201.02:16:17.35#ibcon#read 5, iclass 26, count 2 2006.201.02:16:17.35#ibcon#about to read 6, iclass 26, count 2 2006.201.02:16:17.35#ibcon#read 6, iclass 26, count 2 2006.201.02:16:17.35#ibcon#end of sib2, iclass 26, count 2 2006.201.02:16:17.35#ibcon#*mode == 0, iclass 26, count 2 2006.201.02:16:17.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.02:16:17.35#ibcon#[27=AT05-04\r\n] 2006.201.02:16:17.35#ibcon#*before write, iclass 26, count 2 2006.201.02:16:17.35#ibcon#enter sib2, iclass 26, count 2 2006.201.02:16:17.35#ibcon#flushed, iclass 26, count 2 2006.201.02:16:17.35#ibcon#about to write, iclass 26, count 2 2006.201.02:16:17.35#ibcon#wrote, iclass 26, count 2 2006.201.02:16:17.35#ibcon#about to read 3, iclass 26, count 2 2006.201.02:16:17.38#ibcon#read 3, iclass 26, count 2 2006.201.02:16:17.38#ibcon#about to read 4, iclass 26, count 2 2006.201.02:16:17.38#ibcon#read 4, iclass 26, count 2 2006.201.02:16:17.38#ibcon#about to read 5, iclass 26, count 2 2006.201.02:16:17.38#ibcon#read 5, iclass 26, count 2 2006.201.02:16:17.38#ibcon#about to read 6, iclass 26, count 2 2006.201.02:16:17.38#ibcon#read 6, iclass 26, count 2 2006.201.02:16:17.38#ibcon#end of sib2, iclass 26, count 2 2006.201.02:16:17.38#ibcon#*after write, iclass 26, count 2 2006.201.02:16:17.38#ibcon#*before return 0, iclass 26, count 2 2006.201.02:16:17.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:17.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:16:17.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.02:16:17.38#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:17.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:17.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:17.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:17.50#ibcon#enter wrdev, iclass 26, count 0 2006.201.02:16:17.50#ibcon#first serial, iclass 26, count 0 2006.201.02:16:17.50#ibcon#enter sib2, iclass 26, count 0 2006.201.02:16:17.50#ibcon#flushed, iclass 26, count 0 2006.201.02:16:17.50#ibcon#about to write, iclass 26, count 0 2006.201.02:16:17.50#ibcon#wrote, iclass 26, count 0 2006.201.02:16:17.50#ibcon#about to read 3, iclass 26, count 0 2006.201.02:16:17.52#ibcon#read 3, iclass 26, count 0 2006.201.02:16:17.52#ibcon#about to read 4, iclass 26, count 0 2006.201.02:16:17.52#ibcon#read 4, iclass 26, count 0 2006.201.02:16:17.52#ibcon#about to read 5, iclass 26, count 0 2006.201.02:16:17.52#ibcon#read 5, iclass 26, count 0 2006.201.02:16:17.52#ibcon#about to read 6, iclass 26, count 0 2006.201.02:16:17.52#ibcon#read 6, iclass 26, count 0 2006.201.02:16:17.52#ibcon#end of sib2, iclass 26, count 0 2006.201.02:16:17.52#ibcon#*mode == 0, iclass 26, count 0 2006.201.02:16:17.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.02:16:17.52#ibcon#[27=USB\r\n] 2006.201.02:16:17.52#ibcon#*before write, iclass 26, count 0 2006.201.02:16:17.52#ibcon#enter sib2, iclass 26, count 0 2006.201.02:16:17.52#ibcon#flushed, iclass 26, count 0 2006.201.02:16:17.52#ibcon#about to write, iclass 26, count 0 2006.201.02:16:17.52#ibcon#wrote, iclass 26, count 0 2006.201.02:16:17.52#ibcon#about to read 3, iclass 26, count 0 2006.201.02:16:17.55#ibcon#read 3, iclass 26, count 0 2006.201.02:16:17.55#ibcon#about to read 4, iclass 26, count 0 2006.201.02:16:17.55#ibcon#read 4, iclass 26, count 0 2006.201.02:16:17.55#ibcon#about to read 5, iclass 26, count 0 2006.201.02:16:17.55#ibcon#read 5, iclass 26, count 0 2006.201.02:16:17.55#ibcon#about to read 6, iclass 26, count 0 2006.201.02:16:17.55#ibcon#read 6, iclass 26, count 0 2006.201.02:16:17.55#ibcon#end of sib2, iclass 26, count 0 2006.201.02:16:17.55#ibcon#*after write, iclass 26, count 0 2006.201.02:16:17.55#ibcon#*before return 0, iclass 26, count 0 2006.201.02:16:17.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:17.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:16:17.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.02:16:17.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.02:16:17.55$vck44/vblo=6,719.99 2006.201.02:16:17.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.02:16:17.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.02:16:17.55#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:17.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:17.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:17.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:17.55#ibcon#enter wrdev, iclass 28, count 0 2006.201.02:16:17.55#ibcon#first serial, iclass 28, count 0 2006.201.02:16:17.55#ibcon#enter sib2, iclass 28, count 0 2006.201.02:16:17.55#ibcon#flushed, iclass 28, count 0 2006.201.02:16:17.55#ibcon#about to write, iclass 28, count 0 2006.201.02:16:17.55#ibcon#wrote, iclass 28, count 0 2006.201.02:16:17.55#ibcon#about to read 3, iclass 28, count 0 2006.201.02:16:17.57#ibcon#read 3, iclass 28, count 0 2006.201.02:16:17.57#ibcon#about to read 4, iclass 28, count 0 2006.201.02:16:17.57#ibcon#read 4, iclass 28, count 0 2006.201.02:16:17.57#ibcon#about to read 5, iclass 28, count 0 2006.201.02:16:17.57#ibcon#read 5, iclass 28, count 0 2006.201.02:16:17.57#ibcon#about to read 6, iclass 28, count 0 2006.201.02:16:17.57#ibcon#read 6, iclass 28, count 0 2006.201.02:16:17.57#ibcon#end of sib2, iclass 28, count 0 2006.201.02:16:17.57#ibcon#*mode == 0, iclass 28, count 0 2006.201.02:16:17.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.02:16:17.57#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:16:17.57#ibcon#*before write, iclass 28, count 0 2006.201.02:16:17.57#ibcon#enter sib2, iclass 28, count 0 2006.201.02:16:17.57#ibcon#flushed, iclass 28, count 0 2006.201.02:16:17.57#ibcon#about to write, iclass 28, count 0 2006.201.02:16:17.57#ibcon#wrote, iclass 28, count 0 2006.201.02:16:17.57#ibcon#about to read 3, iclass 28, count 0 2006.201.02:16:17.61#ibcon#read 3, iclass 28, count 0 2006.201.02:16:17.61#ibcon#about to read 4, iclass 28, count 0 2006.201.02:16:17.61#ibcon#read 4, iclass 28, count 0 2006.201.02:16:17.61#ibcon#about to read 5, iclass 28, count 0 2006.201.02:16:17.61#ibcon#read 5, iclass 28, count 0 2006.201.02:16:17.61#ibcon#about to read 6, iclass 28, count 0 2006.201.02:16:17.61#ibcon#read 6, iclass 28, count 0 2006.201.02:16:17.61#ibcon#end of sib2, iclass 28, count 0 2006.201.02:16:17.61#ibcon#*after write, iclass 28, count 0 2006.201.02:16:17.61#ibcon#*before return 0, iclass 28, count 0 2006.201.02:16:17.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:17.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:16:17.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.02:16:17.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.02:16:17.61$vck44/vb=6,4 2006.201.02:16:17.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.02:16:17.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.02:16:17.61#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:17.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:17.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:17.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:17.67#ibcon#enter wrdev, iclass 30, count 2 2006.201.02:16:17.67#ibcon#first serial, iclass 30, count 2 2006.201.02:16:17.67#ibcon#enter sib2, iclass 30, count 2 2006.201.02:16:17.67#ibcon#flushed, iclass 30, count 2 2006.201.02:16:17.67#ibcon#about to write, iclass 30, count 2 2006.201.02:16:17.67#ibcon#wrote, iclass 30, count 2 2006.201.02:16:17.67#ibcon#about to read 3, iclass 30, count 2 2006.201.02:16:17.69#ibcon#read 3, iclass 30, count 2 2006.201.02:16:17.69#ibcon#about to read 4, iclass 30, count 2 2006.201.02:16:17.69#ibcon#read 4, iclass 30, count 2 2006.201.02:16:17.69#ibcon#about to read 5, iclass 30, count 2 2006.201.02:16:17.69#ibcon#read 5, iclass 30, count 2 2006.201.02:16:17.69#ibcon#about to read 6, iclass 30, count 2 2006.201.02:16:17.69#ibcon#read 6, iclass 30, count 2 2006.201.02:16:17.69#ibcon#end of sib2, iclass 30, count 2 2006.201.02:16:17.69#ibcon#*mode == 0, iclass 30, count 2 2006.201.02:16:17.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.02:16:17.69#ibcon#[27=AT06-04\r\n] 2006.201.02:16:17.69#ibcon#*before write, iclass 30, count 2 2006.201.02:16:17.69#ibcon#enter sib2, iclass 30, count 2 2006.201.02:16:17.69#ibcon#flushed, iclass 30, count 2 2006.201.02:16:17.69#ibcon#about to write, iclass 30, count 2 2006.201.02:16:17.69#ibcon#wrote, iclass 30, count 2 2006.201.02:16:17.69#ibcon#about to read 3, iclass 30, count 2 2006.201.02:16:17.72#ibcon#read 3, iclass 30, count 2 2006.201.02:16:17.72#ibcon#about to read 4, iclass 30, count 2 2006.201.02:16:17.72#ibcon#read 4, iclass 30, count 2 2006.201.02:16:17.72#ibcon#about to read 5, iclass 30, count 2 2006.201.02:16:17.72#ibcon#read 5, iclass 30, count 2 2006.201.02:16:17.72#ibcon#about to read 6, iclass 30, count 2 2006.201.02:16:17.72#ibcon#read 6, iclass 30, count 2 2006.201.02:16:17.72#ibcon#end of sib2, iclass 30, count 2 2006.201.02:16:17.72#ibcon#*after write, iclass 30, count 2 2006.201.02:16:17.72#ibcon#*before return 0, iclass 30, count 2 2006.201.02:16:17.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:17.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:16:17.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.02:16:17.72#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:17.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:17.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:17.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:17.84#ibcon#enter wrdev, iclass 30, count 0 2006.201.02:16:17.84#ibcon#first serial, iclass 30, count 0 2006.201.02:16:17.84#ibcon#enter sib2, iclass 30, count 0 2006.201.02:16:17.84#ibcon#flushed, iclass 30, count 0 2006.201.02:16:17.84#ibcon#about to write, iclass 30, count 0 2006.201.02:16:17.84#ibcon#wrote, iclass 30, count 0 2006.201.02:16:17.84#ibcon#about to read 3, iclass 30, count 0 2006.201.02:16:17.86#ibcon#read 3, iclass 30, count 0 2006.201.02:16:17.86#ibcon#about to read 4, iclass 30, count 0 2006.201.02:16:17.86#ibcon#read 4, iclass 30, count 0 2006.201.02:16:17.86#ibcon#about to read 5, iclass 30, count 0 2006.201.02:16:17.86#ibcon#read 5, iclass 30, count 0 2006.201.02:16:17.86#ibcon#about to read 6, iclass 30, count 0 2006.201.02:16:17.86#ibcon#read 6, iclass 30, count 0 2006.201.02:16:17.86#ibcon#end of sib2, iclass 30, count 0 2006.201.02:16:17.86#ibcon#*mode == 0, iclass 30, count 0 2006.201.02:16:17.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.02:16:17.86#ibcon#[27=USB\r\n] 2006.201.02:16:17.86#ibcon#*before write, iclass 30, count 0 2006.201.02:16:17.86#ibcon#enter sib2, iclass 30, count 0 2006.201.02:16:17.86#ibcon#flushed, iclass 30, count 0 2006.201.02:16:17.86#ibcon#about to write, iclass 30, count 0 2006.201.02:16:17.86#ibcon#wrote, iclass 30, count 0 2006.201.02:16:17.86#ibcon#about to read 3, iclass 30, count 0 2006.201.02:16:17.89#ibcon#read 3, iclass 30, count 0 2006.201.02:16:17.89#ibcon#about to read 4, iclass 30, count 0 2006.201.02:16:17.89#ibcon#read 4, iclass 30, count 0 2006.201.02:16:17.89#ibcon#about to read 5, iclass 30, count 0 2006.201.02:16:17.89#ibcon#read 5, iclass 30, count 0 2006.201.02:16:17.89#ibcon#about to read 6, iclass 30, count 0 2006.201.02:16:17.89#ibcon#read 6, iclass 30, count 0 2006.201.02:16:17.89#ibcon#end of sib2, iclass 30, count 0 2006.201.02:16:17.89#ibcon#*after write, iclass 30, count 0 2006.201.02:16:17.89#ibcon#*before return 0, iclass 30, count 0 2006.201.02:16:17.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:17.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:16:17.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.02:16:17.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.02:16:17.89$vck44/vblo=7,734.99 2006.201.02:16:17.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.02:16:17.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.02:16:17.89#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:17.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:17.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:17.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:17.89#ibcon#enter wrdev, iclass 32, count 0 2006.201.02:16:17.89#ibcon#first serial, iclass 32, count 0 2006.201.02:16:17.89#ibcon#enter sib2, iclass 32, count 0 2006.201.02:16:17.89#ibcon#flushed, iclass 32, count 0 2006.201.02:16:17.89#ibcon#about to write, iclass 32, count 0 2006.201.02:16:17.89#ibcon#wrote, iclass 32, count 0 2006.201.02:16:17.89#ibcon#about to read 3, iclass 32, count 0 2006.201.02:16:17.91#ibcon#read 3, iclass 32, count 0 2006.201.02:16:17.91#ibcon#about to read 4, iclass 32, count 0 2006.201.02:16:17.91#ibcon#read 4, iclass 32, count 0 2006.201.02:16:17.91#ibcon#about to read 5, iclass 32, count 0 2006.201.02:16:17.91#ibcon#read 5, iclass 32, count 0 2006.201.02:16:17.91#ibcon#about to read 6, iclass 32, count 0 2006.201.02:16:17.91#ibcon#read 6, iclass 32, count 0 2006.201.02:16:17.91#ibcon#end of sib2, iclass 32, count 0 2006.201.02:16:17.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.02:16:17.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.02:16:17.91#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:16:17.91#ibcon#*before write, iclass 32, count 0 2006.201.02:16:17.91#ibcon#enter sib2, iclass 32, count 0 2006.201.02:16:17.91#ibcon#flushed, iclass 32, count 0 2006.201.02:16:17.91#ibcon#about to write, iclass 32, count 0 2006.201.02:16:17.91#ibcon#wrote, iclass 32, count 0 2006.201.02:16:17.91#ibcon#about to read 3, iclass 32, count 0 2006.201.02:16:17.95#ibcon#read 3, iclass 32, count 0 2006.201.02:16:17.95#ibcon#about to read 4, iclass 32, count 0 2006.201.02:16:17.95#ibcon#read 4, iclass 32, count 0 2006.201.02:16:17.95#ibcon#about to read 5, iclass 32, count 0 2006.201.02:16:17.95#ibcon#read 5, iclass 32, count 0 2006.201.02:16:17.95#ibcon#about to read 6, iclass 32, count 0 2006.201.02:16:17.95#ibcon#read 6, iclass 32, count 0 2006.201.02:16:17.95#ibcon#end of sib2, iclass 32, count 0 2006.201.02:16:17.95#ibcon#*after write, iclass 32, count 0 2006.201.02:16:17.95#ibcon#*before return 0, iclass 32, count 0 2006.201.02:16:17.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:17.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:16:17.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.02:16:17.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.02:16:17.95$vck44/vb=7,4 2006.201.02:16:17.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.02:16:17.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.02:16:17.95#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:17.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:18.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:18.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:18.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.02:16:18.01#ibcon#first serial, iclass 34, count 2 2006.201.02:16:18.01#ibcon#enter sib2, iclass 34, count 2 2006.201.02:16:18.01#ibcon#flushed, iclass 34, count 2 2006.201.02:16:18.01#ibcon#about to write, iclass 34, count 2 2006.201.02:16:18.01#ibcon#wrote, iclass 34, count 2 2006.201.02:16:18.01#ibcon#about to read 3, iclass 34, count 2 2006.201.02:16:18.03#ibcon#read 3, iclass 34, count 2 2006.201.02:16:18.03#ibcon#about to read 4, iclass 34, count 2 2006.201.02:16:18.03#ibcon#read 4, iclass 34, count 2 2006.201.02:16:18.03#ibcon#about to read 5, iclass 34, count 2 2006.201.02:16:18.03#ibcon#read 5, iclass 34, count 2 2006.201.02:16:18.03#ibcon#about to read 6, iclass 34, count 2 2006.201.02:16:18.03#ibcon#read 6, iclass 34, count 2 2006.201.02:16:18.03#ibcon#end of sib2, iclass 34, count 2 2006.201.02:16:18.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.02:16:18.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.02:16:18.03#ibcon#[27=AT07-04\r\n] 2006.201.02:16:18.03#ibcon#*before write, iclass 34, count 2 2006.201.02:16:18.03#ibcon#enter sib2, iclass 34, count 2 2006.201.02:16:18.03#ibcon#flushed, iclass 34, count 2 2006.201.02:16:18.03#ibcon#about to write, iclass 34, count 2 2006.201.02:16:18.03#ibcon#wrote, iclass 34, count 2 2006.201.02:16:18.03#ibcon#about to read 3, iclass 34, count 2 2006.201.02:16:18.06#ibcon#read 3, iclass 34, count 2 2006.201.02:16:18.06#ibcon#about to read 4, iclass 34, count 2 2006.201.02:16:18.06#ibcon#read 4, iclass 34, count 2 2006.201.02:16:18.06#ibcon#about to read 5, iclass 34, count 2 2006.201.02:16:18.06#ibcon#read 5, iclass 34, count 2 2006.201.02:16:18.06#ibcon#about to read 6, iclass 34, count 2 2006.201.02:16:18.06#ibcon#read 6, iclass 34, count 2 2006.201.02:16:18.06#ibcon#end of sib2, iclass 34, count 2 2006.201.02:16:18.06#ibcon#*after write, iclass 34, count 2 2006.201.02:16:18.06#ibcon#*before return 0, iclass 34, count 2 2006.201.02:16:18.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:18.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:16:18.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.02:16:18.06#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:18.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:18.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:18.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:18.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.02:16:18.18#ibcon#first serial, iclass 34, count 0 2006.201.02:16:18.18#ibcon#enter sib2, iclass 34, count 0 2006.201.02:16:18.18#ibcon#flushed, iclass 34, count 0 2006.201.02:16:18.18#ibcon#about to write, iclass 34, count 0 2006.201.02:16:18.18#ibcon#wrote, iclass 34, count 0 2006.201.02:16:18.18#ibcon#about to read 3, iclass 34, count 0 2006.201.02:16:18.20#ibcon#read 3, iclass 34, count 0 2006.201.02:16:18.20#ibcon#about to read 4, iclass 34, count 0 2006.201.02:16:18.20#ibcon#read 4, iclass 34, count 0 2006.201.02:16:18.20#ibcon#about to read 5, iclass 34, count 0 2006.201.02:16:18.20#ibcon#read 5, iclass 34, count 0 2006.201.02:16:18.20#ibcon#about to read 6, iclass 34, count 0 2006.201.02:16:18.20#ibcon#read 6, iclass 34, count 0 2006.201.02:16:18.20#ibcon#end of sib2, iclass 34, count 0 2006.201.02:16:18.20#ibcon#*mode == 0, iclass 34, count 0 2006.201.02:16:18.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.02:16:18.20#ibcon#[27=USB\r\n] 2006.201.02:16:18.20#ibcon#*before write, iclass 34, count 0 2006.201.02:16:18.20#ibcon#enter sib2, iclass 34, count 0 2006.201.02:16:18.20#ibcon#flushed, iclass 34, count 0 2006.201.02:16:18.20#ibcon#about to write, iclass 34, count 0 2006.201.02:16:18.20#ibcon#wrote, iclass 34, count 0 2006.201.02:16:18.20#ibcon#about to read 3, iclass 34, count 0 2006.201.02:16:18.23#ibcon#read 3, iclass 34, count 0 2006.201.02:16:18.23#ibcon#about to read 4, iclass 34, count 0 2006.201.02:16:18.23#ibcon#read 4, iclass 34, count 0 2006.201.02:16:18.23#ibcon#about to read 5, iclass 34, count 0 2006.201.02:16:18.23#ibcon#read 5, iclass 34, count 0 2006.201.02:16:18.23#ibcon#about to read 6, iclass 34, count 0 2006.201.02:16:18.23#ibcon#read 6, iclass 34, count 0 2006.201.02:16:18.23#ibcon#end of sib2, iclass 34, count 0 2006.201.02:16:18.23#ibcon#*after write, iclass 34, count 0 2006.201.02:16:18.23#ibcon#*before return 0, iclass 34, count 0 2006.201.02:16:18.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:18.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:16:18.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.02:16:18.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.02:16:18.23$vck44/vblo=8,744.99 2006.201.02:16:18.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.02:16:18.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.02:16:18.23#ibcon#ireg 17 cls_cnt 0 2006.201.02:16:18.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:18.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:18.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:18.23#ibcon#enter wrdev, iclass 36, count 0 2006.201.02:16:18.23#ibcon#first serial, iclass 36, count 0 2006.201.02:16:18.23#ibcon#enter sib2, iclass 36, count 0 2006.201.02:16:18.23#ibcon#flushed, iclass 36, count 0 2006.201.02:16:18.23#ibcon#about to write, iclass 36, count 0 2006.201.02:16:18.23#ibcon#wrote, iclass 36, count 0 2006.201.02:16:18.23#ibcon#about to read 3, iclass 36, count 0 2006.201.02:16:18.25#ibcon#read 3, iclass 36, count 0 2006.201.02:16:18.25#ibcon#about to read 4, iclass 36, count 0 2006.201.02:16:18.25#ibcon#read 4, iclass 36, count 0 2006.201.02:16:18.25#ibcon#about to read 5, iclass 36, count 0 2006.201.02:16:18.25#ibcon#read 5, iclass 36, count 0 2006.201.02:16:18.25#ibcon#about to read 6, iclass 36, count 0 2006.201.02:16:18.25#ibcon#read 6, iclass 36, count 0 2006.201.02:16:18.25#ibcon#end of sib2, iclass 36, count 0 2006.201.02:16:18.25#ibcon#*mode == 0, iclass 36, count 0 2006.201.02:16:18.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.02:16:18.25#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:16:18.25#ibcon#*before write, iclass 36, count 0 2006.201.02:16:18.25#ibcon#enter sib2, iclass 36, count 0 2006.201.02:16:18.25#ibcon#flushed, iclass 36, count 0 2006.201.02:16:18.25#ibcon#about to write, iclass 36, count 0 2006.201.02:16:18.25#ibcon#wrote, iclass 36, count 0 2006.201.02:16:18.25#ibcon#about to read 3, iclass 36, count 0 2006.201.02:16:18.29#ibcon#read 3, iclass 36, count 0 2006.201.02:16:18.29#ibcon#about to read 4, iclass 36, count 0 2006.201.02:16:18.29#ibcon#read 4, iclass 36, count 0 2006.201.02:16:18.29#ibcon#about to read 5, iclass 36, count 0 2006.201.02:16:18.29#ibcon#read 5, iclass 36, count 0 2006.201.02:16:18.29#ibcon#about to read 6, iclass 36, count 0 2006.201.02:16:18.29#ibcon#read 6, iclass 36, count 0 2006.201.02:16:18.29#ibcon#end of sib2, iclass 36, count 0 2006.201.02:16:18.29#ibcon#*after write, iclass 36, count 0 2006.201.02:16:18.29#ibcon#*before return 0, iclass 36, count 0 2006.201.02:16:18.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:18.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:16:18.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.02:16:18.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.02:16:18.29$vck44/vb=8,4 2006.201.02:16:18.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.02:16:18.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.02:16:18.29#ibcon#ireg 11 cls_cnt 2 2006.201.02:16:18.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:18.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:18.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:18.35#ibcon#enter wrdev, iclass 38, count 2 2006.201.02:16:18.35#ibcon#first serial, iclass 38, count 2 2006.201.02:16:18.35#ibcon#enter sib2, iclass 38, count 2 2006.201.02:16:18.35#ibcon#flushed, iclass 38, count 2 2006.201.02:16:18.35#ibcon#about to write, iclass 38, count 2 2006.201.02:16:18.35#ibcon#wrote, iclass 38, count 2 2006.201.02:16:18.35#ibcon#about to read 3, iclass 38, count 2 2006.201.02:16:18.37#ibcon#read 3, iclass 38, count 2 2006.201.02:16:18.37#ibcon#about to read 4, iclass 38, count 2 2006.201.02:16:18.37#ibcon#read 4, iclass 38, count 2 2006.201.02:16:18.37#ibcon#about to read 5, iclass 38, count 2 2006.201.02:16:18.37#ibcon#read 5, iclass 38, count 2 2006.201.02:16:18.37#ibcon#about to read 6, iclass 38, count 2 2006.201.02:16:18.37#ibcon#read 6, iclass 38, count 2 2006.201.02:16:18.37#ibcon#end of sib2, iclass 38, count 2 2006.201.02:16:18.37#ibcon#*mode == 0, iclass 38, count 2 2006.201.02:16:18.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.02:16:18.37#ibcon#[27=AT08-04\r\n] 2006.201.02:16:18.37#ibcon#*before write, iclass 38, count 2 2006.201.02:16:18.37#ibcon#enter sib2, iclass 38, count 2 2006.201.02:16:18.37#ibcon#flushed, iclass 38, count 2 2006.201.02:16:18.37#ibcon#about to write, iclass 38, count 2 2006.201.02:16:18.37#ibcon#wrote, iclass 38, count 2 2006.201.02:16:18.37#ibcon#about to read 3, iclass 38, count 2 2006.201.02:16:18.40#ibcon#read 3, iclass 38, count 2 2006.201.02:16:18.40#ibcon#about to read 4, iclass 38, count 2 2006.201.02:16:18.40#ibcon#read 4, iclass 38, count 2 2006.201.02:16:18.40#ibcon#about to read 5, iclass 38, count 2 2006.201.02:16:18.40#ibcon#read 5, iclass 38, count 2 2006.201.02:16:18.40#ibcon#about to read 6, iclass 38, count 2 2006.201.02:16:18.40#ibcon#read 6, iclass 38, count 2 2006.201.02:16:18.40#ibcon#end of sib2, iclass 38, count 2 2006.201.02:16:18.40#ibcon#*after write, iclass 38, count 2 2006.201.02:16:18.40#ibcon#*before return 0, iclass 38, count 2 2006.201.02:16:18.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:18.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:16:18.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.02:16:18.40#ibcon#ireg 7 cls_cnt 0 2006.201.02:16:18.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:18.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:18.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:18.52#ibcon#enter wrdev, iclass 38, count 0 2006.201.02:16:18.52#ibcon#first serial, iclass 38, count 0 2006.201.02:16:18.52#ibcon#enter sib2, iclass 38, count 0 2006.201.02:16:18.52#ibcon#flushed, iclass 38, count 0 2006.201.02:16:18.52#ibcon#about to write, iclass 38, count 0 2006.201.02:16:18.52#ibcon#wrote, iclass 38, count 0 2006.201.02:16:18.52#ibcon#about to read 3, iclass 38, count 0 2006.201.02:16:18.54#ibcon#read 3, iclass 38, count 0 2006.201.02:16:18.54#ibcon#about to read 4, iclass 38, count 0 2006.201.02:16:18.54#ibcon#read 4, iclass 38, count 0 2006.201.02:16:18.54#ibcon#about to read 5, iclass 38, count 0 2006.201.02:16:18.54#ibcon#read 5, iclass 38, count 0 2006.201.02:16:18.54#ibcon#about to read 6, iclass 38, count 0 2006.201.02:16:18.54#ibcon#read 6, iclass 38, count 0 2006.201.02:16:18.54#ibcon#end of sib2, iclass 38, count 0 2006.201.02:16:18.54#ibcon#*mode == 0, iclass 38, count 0 2006.201.02:16:18.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.02:16:18.54#ibcon#[27=USB\r\n] 2006.201.02:16:18.54#ibcon#*before write, iclass 38, count 0 2006.201.02:16:18.54#ibcon#enter sib2, iclass 38, count 0 2006.201.02:16:18.54#ibcon#flushed, iclass 38, count 0 2006.201.02:16:18.54#ibcon#about to write, iclass 38, count 0 2006.201.02:16:18.54#ibcon#wrote, iclass 38, count 0 2006.201.02:16:18.54#ibcon#about to read 3, iclass 38, count 0 2006.201.02:16:18.57#ibcon#read 3, iclass 38, count 0 2006.201.02:16:18.57#ibcon#about to read 4, iclass 38, count 0 2006.201.02:16:18.57#ibcon#read 4, iclass 38, count 0 2006.201.02:16:18.57#ibcon#about to read 5, iclass 38, count 0 2006.201.02:16:18.57#ibcon#read 5, iclass 38, count 0 2006.201.02:16:18.57#ibcon#about to read 6, iclass 38, count 0 2006.201.02:16:18.57#ibcon#read 6, iclass 38, count 0 2006.201.02:16:18.57#ibcon#end of sib2, iclass 38, count 0 2006.201.02:16:18.57#ibcon#*after write, iclass 38, count 0 2006.201.02:16:18.57#ibcon#*before return 0, iclass 38, count 0 2006.201.02:16:18.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:18.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:16:18.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.02:16:18.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.02:16:18.57$vck44/vabw=wide 2006.201.02:16:18.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.02:16:18.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.02:16:18.57#ibcon#ireg 8 cls_cnt 0 2006.201.02:16:18.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:18.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:18.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:18.57#ibcon#enter wrdev, iclass 40, count 0 2006.201.02:16:18.57#ibcon#first serial, iclass 40, count 0 2006.201.02:16:18.57#ibcon#enter sib2, iclass 40, count 0 2006.201.02:16:18.57#ibcon#flushed, iclass 40, count 0 2006.201.02:16:18.57#ibcon#about to write, iclass 40, count 0 2006.201.02:16:18.57#ibcon#wrote, iclass 40, count 0 2006.201.02:16:18.57#ibcon#about to read 3, iclass 40, count 0 2006.201.02:16:18.59#ibcon#read 3, iclass 40, count 0 2006.201.02:16:18.59#ibcon#about to read 4, iclass 40, count 0 2006.201.02:16:18.59#ibcon#read 4, iclass 40, count 0 2006.201.02:16:18.59#ibcon#about to read 5, iclass 40, count 0 2006.201.02:16:18.59#ibcon#read 5, iclass 40, count 0 2006.201.02:16:18.59#ibcon#about to read 6, iclass 40, count 0 2006.201.02:16:18.59#ibcon#read 6, iclass 40, count 0 2006.201.02:16:18.59#ibcon#end of sib2, iclass 40, count 0 2006.201.02:16:18.59#ibcon#*mode == 0, iclass 40, count 0 2006.201.02:16:18.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.02:16:18.59#ibcon#[25=BW32\r\n] 2006.201.02:16:18.59#ibcon#*before write, iclass 40, count 0 2006.201.02:16:18.59#ibcon#enter sib2, iclass 40, count 0 2006.201.02:16:18.59#ibcon#flushed, iclass 40, count 0 2006.201.02:16:18.59#ibcon#about to write, iclass 40, count 0 2006.201.02:16:18.59#ibcon#wrote, iclass 40, count 0 2006.201.02:16:18.59#ibcon#about to read 3, iclass 40, count 0 2006.201.02:16:18.62#ibcon#read 3, iclass 40, count 0 2006.201.02:16:18.62#ibcon#about to read 4, iclass 40, count 0 2006.201.02:16:18.62#ibcon#read 4, iclass 40, count 0 2006.201.02:16:18.62#ibcon#about to read 5, iclass 40, count 0 2006.201.02:16:18.62#ibcon#read 5, iclass 40, count 0 2006.201.02:16:18.62#ibcon#about to read 6, iclass 40, count 0 2006.201.02:16:18.62#ibcon#read 6, iclass 40, count 0 2006.201.02:16:18.62#ibcon#end of sib2, iclass 40, count 0 2006.201.02:16:18.62#ibcon#*after write, iclass 40, count 0 2006.201.02:16:18.62#ibcon#*before return 0, iclass 40, count 0 2006.201.02:16:18.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:18.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:16:18.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.02:16:18.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.02:16:18.62$vck44/vbbw=wide 2006.201.02:16:18.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.02:16:18.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.02:16:18.62#ibcon#ireg 8 cls_cnt 0 2006.201.02:16:18.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:16:18.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:16:18.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:16:18.69#ibcon#enter wrdev, iclass 4, count 0 2006.201.02:16:18.69#ibcon#first serial, iclass 4, count 0 2006.201.02:16:18.69#ibcon#enter sib2, iclass 4, count 0 2006.201.02:16:18.69#ibcon#flushed, iclass 4, count 0 2006.201.02:16:18.69#ibcon#about to write, iclass 4, count 0 2006.201.02:16:18.69#ibcon#wrote, iclass 4, count 0 2006.201.02:16:18.69#ibcon#about to read 3, iclass 4, count 0 2006.201.02:16:18.71#ibcon#read 3, iclass 4, count 0 2006.201.02:16:18.71#ibcon#about to read 4, iclass 4, count 0 2006.201.02:16:18.71#ibcon#read 4, iclass 4, count 0 2006.201.02:16:18.71#ibcon#about to read 5, iclass 4, count 0 2006.201.02:16:18.71#ibcon#read 5, iclass 4, count 0 2006.201.02:16:18.71#ibcon#about to read 6, iclass 4, count 0 2006.201.02:16:18.71#ibcon#read 6, iclass 4, count 0 2006.201.02:16:18.71#ibcon#end of sib2, iclass 4, count 0 2006.201.02:16:18.71#ibcon#*mode == 0, iclass 4, count 0 2006.201.02:16:18.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.02:16:18.71#ibcon#[27=BW32\r\n] 2006.201.02:16:18.71#ibcon#*before write, iclass 4, count 0 2006.201.02:16:18.71#ibcon#enter sib2, iclass 4, count 0 2006.201.02:16:18.71#ibcon#flushed, iclass 4, count 0 2006.201.02:16:18.71#ibcon#about to write, iclass 4, count 0 2006.201.02:16:18.71#ibcon#wrote, iclass 4, count 0 2006.201.02:16:18.71#ibcon#about to read 3, iclass 4, count 0 2006.201.02:16:18.74#ibcon#read 3, iclass 4, count 0 2006.201.02:16:18.74#ibcon#about to read 4, iclass 4, count 0 2006.201.02:16:18.74#ibcon#read 4, iclass 4, count 0 2006.201.02:16:18.74#ibcon#about to read 5, iclass 4, count 0 2006.201.02:16:18.74#ibcon#read 5, iclass 4, count 0 2006.201.02:16:18.74#ibcon#about to read 6, iclass 4, count 0 2006.201.02:16:18.74#ibcon#read 6, iclass 4, count 0 2006.201.02:16:18.74#ibcon#end of sib2, iclass 4, count 0 2006.201.02:16:18.74#ibcon#*after write, iclass 4, count 0 2006.201.02:16:18.74#ibcon#*before return 0, iclass 4, count 0 2006.201.02:16:18.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:16:18.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:16:18.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.02:16:18.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.02:16:18.74$setupk4/ifdk4 2006.201.02:16:18.74$ifdk4/lo= 2006.201.02:16:18.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:16:18.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:16:18.74$ifdk4/patch= 2006.201.02:16:18.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:16:18.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:16:18.74$setupk4/!*+20s 2006.201.02:16:20.43#abcon#<5=/04 2.9 5.4 22.90 911005.3\r\n> 2006.201.02:16:20.45#abcon#{5=INTERFACE CLEAR} 2006.201.02:16:20.51#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:16:30.60#abcon#<5=/04 2.9 5.4 22.90 911005.3\r\n> 2006.201.02:16:30.62#abcon#{5=INTERFACE CLEAR} 2006.201.02:16:30.68#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:16:33.23$setupk4/"tpicd 2006.201.02:16:33.23$setupk4/echo=off 2006.201.02:16:33.23$setupk4/xlog=off 2006.201.02:16:33.23:!2006.201.02:20:06 2006.201.02:16:52.14#trakl#Source acquired 2006.201.02:16:52.14#flagr#flagr/antenna,acquired 2006.201.02:20:06.00:preob 2006.201.02:20:06.14/onsource/TRACKING 2006.201.02:20:06.14:!2006.201.02:20:16 2006.201.02:20:16.00:"tape 2006.201.02:20:16.00:"st=record 2006.201.02:20:16.00:data_valid=on 2006.201.02:20:16.00:midob 2006.201.02:20:16.14/onsource/TRACKING 2006.201.02:20:16.14/wx/22.91,1005.2,91 2006.201.02:20:16.27/cable/+6.4675E-03 2006.201.02:20:17.36/va/01,08,usb,yes,33,36 2006.201.02:20:17.36/va/02,07,usb,yes,36,37 2006.201.02:20:17.36/va/03,08,usb,yes,33,34 2006.201.02:20:17.36/va/04,07,usb,yes,37,39 2006.201.02:20:17.36/va/05,04,usb,yes,33,33 2006.201.02:20:17.36/va/06,05,usb,yes,33,33 2006.201.02:20:17.36/va/07,05,usb,yes,32,33 2006.201.02:20:17.36/va/08,04,usb,yes,31,38 2006.201.02:20:17.59/valo/01,524.99,yes,locked 2006.201.02:20:17.59/valo/02,534.99,yes,locked 2006.201.02:20:17.59/valo/03,564.99,yes,locked 2006.201.02:20:17.59/valo/04,624.99,yes,locked 2006.201.02:20:17.59/valo/05,734.99,yes,locked 2006.201.02:20:17.59/valo/06,814.99,yes,locked 2006.201.02:20:17.59/valo/07,864.99,yes,locked 2006.201.02:20:17.59/valo/08,884.99,yes,locked 2006.201.02:20:18.68/vb/01,04,usb,yes,37,34 2006.201.02:20:18.68/vb/02,05,usb,yes,35,35 2006.201.02:20:18.68/vb/03,04,usb,yes,36,40 2006.201.02:20:18.68/vb/04,05,usb,yes,36,35 2006.201.02:20:18.68/vb/05,04,usb,yes,32,35 2006.201.02:20:18.68/vb/06,04,usb,yes,37,33 2006.201.02:20:18.68/vb/07,04,usb,yes,37,37 2006.201.02:20:18.68/vb/08,04,usb,yes,34,38 2006.201.02:20:18.91/vblo/01,629.99,yes,locked 2006.201.02:20:18.91/vblo/02,634.99,yes,locked 2006.201.02:20:18.91/vblo/03,649.99,yes,locked 2006.201.02:20:18.91/vblo/04,679.99,yes,locked 2006.201.02:20:18.91/vblo/05,709.99,yes,locked 2006.201.02:20:18.91/vblo/06,719.99,yes,locked 2006.201.02:20:18.91/vblo/07,734.99,yes,locked 2006.201.02:20:18.91/vblo/08,744.99,yes,locked 2006.201.02:20:19.06/vabw/8 2006.201.02:20:19.21/vbbw/8 2006.201.02:20:19.30/xfe/off,on,15.0 2006.201.02:20:19.69/ifatt/23,28,28,28 2006.201.02:20:20.04/fmout-gps/S +4.42E-07 2006.201.02:20:20.12:!2006.201.02:22:06 2006.201.02:22:06.00:data_valid=off 2006.201.02:22:06.00:"et 2006.201.02:22:06.00:!+3s 2006.201.02:22:09.02:"tape 2006.201.02:22:09.02:postob 2006.201.02:22:09.16/cable/+6.4682E-03 2006.201.02:22:09.16/wx/22.93,1005.1,91 2006.201.02:22:09.22/fmout-gps/S +4.42E-07 2006.201.02:22:09.22:scan_name=201-0229,jd0607,60 2006.201.02:22:09.23:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.201.02:22:10.14#flagr#flagr/antenna,new-source 2006.201.02:22:10.14:checkk5 2006.201.02:22:10.55/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:22:10.98/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:22:11.39/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:22:11.83/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:22:12.28/chk_obsdata//k5ts1/T2010220??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.02:22:12.71/chk_obsdata//k5ts2/T2010220??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.02:22:13.14/chk_obsdata//k5ts3/T2010220??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.02:22:13.51/chk_obsdata//k5ts4/T2010220??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.02:22:14.36/k5log//k5ts1_log_newline 2006.201.02:22:15.11/k5log//k5ts2_log_newline 2006.201.02:22:15.89/k5log//k5ts3_log_newline 2006.201.02:22:16.66/k5log//k5ts4_log_newline 2006.201.02:22:16.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:22:16.68:setupk4=1 2006.201.02:22:16.68$setupk4/echo=on 2006.201.02:22:16.68$setupk4/pcalon 2006.201.02:22:16.68$pcalon/"no phase cal control is implemented here 2006.201.02:22:16.68$setupk4/"tpicd=stop 2006.201.02:22:16.68$setupk4/"rec=synch_on 2006.201.02:22:16.68$setupk4/"rec_mode=128 2006.201.02:22:16.69$setupk4/!* 2006.201.02:22:16.69$setupk4/recpk4 2006.201.02:22:16.69$recpk4/recpatch= 2006.201.02:22:16.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:22:16.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:22:16.69$setupk4/vck44 2006.201.02:22:16.69$vck44/valo=1,524.99 2006.201.02:22:16.69#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.02:22:16.69#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.02:22:16.69#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:16.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:16.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:16.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:16.69#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:22:16.69#ibcon#first serial, iclass 11, count 0 2006.201.02:22:16.69#ibcon#enter sib2, iclass 11, count 0 2006.201.02:22:16.69#ibcon#flushed, iclass 11, count 0 2006.201.02:22:16.69#ibcon#about to write, iclass 11, count 0 2006.201.02:22:16.69#ibcon#wrote, iclass 11, count 0 2006.201.02:22:16.69#ibcon#about to read 3, iclass 11, count 0 2006.201.02:22:16.73#ibcon#read 3, iclass 11, count 0 2006.201.02:22:16.73#ibcon#about to read 4, iclass 11, count 0 2006.201.02:22:16.73#ibcon#read 4, iclass 11, count 0 2006.201.02:22:16.73#ibcon#about to read 5, iclass 11, count 0 2006.201.02:22:16.73#ibcon#read 5, iclass 11, count 0 2006.201.02:22:16.73#ibcon#about to read 6, iclass 11, count 0 2006.201.02:22:16.73#ibcon#read 6, iclass 11, count 0 2006.201.02:22:16.73#ibcon#end of sib2, iclass 11, count 0 2006.201.02:22:16.73#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:22:16.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:22:16.73#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:22:16.73#ibcon#*before write, iclass 11, count 0 2006.201.02:22:16.73#ibcon#enter sib2, iclass 11, count 0 2006.201.02:22:16.73#ibcon#flushed, iclass 11, count 0 2006.201.02:22:16.73#ibcon#about to write, iclass 11, count 0 2006.201.02:22:16.73#ibcon#wrote, iclass 11, count 0 2006.201.02:22:16.73#ibcon#about to read 3, iclass 11, count 0 2006.201.02:22:16.78#ibcon#read 3, iclass 11, count 0 2006.201.02:22:16.78#ibcon#about to read 4, iclass 11, count 0 2006.201.02:22:16.78#ibcon#read 4, iclass 11, count 0 2006.201.02:22:16.78#ibcon#about to read 5, iclass 11, count 0 2006.201.02:22:16.78#ibcon#read 5, iclass 11, count 0 2006.201.02:22:16.78#ibcon#about to read 6, iclass 11, count 0 2006.201.02:22:16.78#ibcon#read 6, iclass 11, count 0 2006.201.02:22:16.78#ibcon#end of sib2, iclass 11, count 0 2006.201.02:22:16.78#ibcon#*after write, iclass 11, count 0 2006.201.02:22:16.78#ibcon#*before return 0, iclass 11, count 0 2006.201.02:22:16.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:16.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:16.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:22:16.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:22:16.78$vck44/va=1,8 2006.201.02:22:16.78#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.02:22:16.78#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.02:22:16.78#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:16.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:16.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:16.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:16.78#ibcon#enter wrdev, iclass 13, count 2 2006.201.02:22:16.78#ibcon#first serial, iclass 13, count 2 2006.201.02:22:16.78#ibcon#enter sib2, iclass 13, count 2 2006.201.02:22:16.78#ibcon#flushed, iclass 13, count 2 2006.201.02:22:16.78#ibcon#about to write, iclass 13, count 2 2006.201.02:22:16.78#ibcon#wrote, iclass 13, count 2 2006.201.02:22:16.78#ibcon#about to read 3, iclass 13, count 2 2006.201.02:22:16.80#ibcon#read 3, iclass 13, count 2 2006.201.02:22:16.80#ibcon#about to read 4, iclass 13, count 2 2006.201.02:22:16.80#ibcon#read 4, iclass 13, count 2 2006.201.02:22:16.80#ibcon#about to read 5, iclass 13, count 2 2006.201.02:22:16.80#ibcon#read 5, iclass 13, count 2 2006.201.02:22:16.80#ibcon#about to read 6, iclass 13, count 2 2006.201.02:22:16.80#ibcon#read 6, iclass 13, count 2 2006.201.02:22:16.80#ibcon#end of sib2, iclass 13, count 2 2006.201.02:22:16.80#ibcon#*mode == 0, iclass 13, count 2 2006.201.02:22:16.80#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.02:22:16.80#ibcon#[25=AT01-08\r\n] 2006.201.02:22:16.80#ibcon#*before write, iclass 13, count 2 2006.201.02:22:16.80#ibcon#enter sib2, iclass 13, count 2 2006.201.02:22:16.80#ibcon#flushed, iclass 13, count 2 2006.201.02:22:16.80#ibcon#about to write, iclass 13, count 2 2006.201.02:22:16.80#ibcon#wrote, iclass 13, count 2 2006.201.02:22:16.80#ibcon#about to read 3, iclass 13, count 2 2006.201.02:22:16.83#ibcon#read 3, iclass 13, count 2 2006.201.02:22:16.83#ibcon#about to read 4, iclass 13, count 2 2006.201.02:22:16.83#ibcon#read 4, iclass 13, count 2 2006.201.02:22:16.83#ibcon#about to read 5, iclass 13, count 2 2006.201.02:22:16.83#ibcon#read 5, iclass 13, count 2 2006.201.02:22:16.83#ibcon#about to read 6, iclass 13, count 2 2006.201.02:22:16.83#ibcon#read 6, iclass 13, count 2 2006.201.02:22:16.83#ibcon#end of sib2, iclass 13, count 2 2006.201.02:22:16.83#ibcon#*after write, iclass 13, count 2 2006.201.02:22:16.83#ibcon#*before return 0, iclass 13, count 2 2006.201.02:22:16.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:16.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:16.83#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.02:22:16.83#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:16.83#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:16.95#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:16.95#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:16.95#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:22:16.95#ibcon#first serial, iclass 13, count 0 2006.201.02:22:16.95#ibcon#enter sib2, iclass 13, count 0 2006.201.02:22:16.95#ibcon#flushed, iclass 13, count 0 2006.201.02:22:16.95#ibcon#about to write, iclass 13, count 0 2006.201.02:22:16.95#ibcon#wrote, iclass 13, count 0 2006.201.02:22:16.95#ibcon#about to read 3, iclass 13, count 0 2006.201.02:22:16.97#ibcon#read 3, iclass 13, count 0 2006.201.02:22:16.97#ibcon#about to read 4, iclass 13, count 0 2006.201.02:22:16.97#ibcon#read 4, iclass 13, count 0 2006.201.02:22:16.97#ibcon#about to read 5, iclass 13, count 0 2006.201.02:22:16.97#ibcon#read 5, iclass 13, count 0 2006.201.02:22:16.97#ibcon#about to read 6, iclass 13, count 0 2006.201.02:22:16.97#ibcon#read 6, iclass 13, count 0 2006.201.02:22:16.97#ibcon#end of sib2, iclass 13, count 0 2006.201.02:22:16.97#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:22:16.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:22:16.97#ibcon#[25=USB\r\n] 2006.201.02:22:16.97#ibcon#*before write, iclass 13, count 0 2006.201.02:22:16.97#ibcon#enter sib2, iclass 13, count 0 2006.201.02:22:16.97#ibcon#flushed, iclass 13, count 0 2006.201.02:22:16.97#ibcon#about to write, iclass 13, count 0 2006.201.02:22:16.97#ibcon#wrote, iclass 13, count 0 2006.201.02:22:16.97#ibcon#about to read 3, iclass 13, count 0 2006.201.02:22:17.00#ibcon#read 3, iclass 13, count 0 2006.201.02:22:17.00#ibcon#about to read 4, iclass 13, count 0 2006.201.02:22:17.00#ibcon#read 4, iclass 13, count 0 2006.201.02:22:17.00#ibcon#about to read 5, iclass 13, count 0 2006.201.02:22:17.00#ibcon#read 5, iclass 13, count 0 2006.201.02:22:17.00#ibcon#about to read 6, iclass 13, count 0 2006.201.02:22:17.00#ibcon#read 6, iclass 13, count 0 2006.201.02:22:17.00#ibcon#end of sib2, iclass 13, count 0 2006.201.02:22:17.00#ibcon#*after write, iclass 13, count 0 2006.201.02:22:17.00#ibcon#*before return 0, iclass 13, count 0 2006.201.02:22:17.00#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:17.00#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:17.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:22:17.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:22:17.00$vck44/valo=2,534.99 2006.201.02:22:17.00#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.02:22:17.00#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.02:22:17.00#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:17.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:17.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:17.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:17.00#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:22:17.00#ibcon#first serial, iclass 15, count 0 2006.201.02:22:17.00#ibcon#enter sib2, iclass 15, count 0 2006.201.02:22:17.00#ibcon#flushed, iclass 15, count 0 2006.201.02:22:17.00#ibcon#about to write, iclass 15, count 0 2006.201.02:22:17.00#ibcon#wrote, iclass 15, count 0 2006.201.02:22:17.00#ibcon#about to read 3, iclass 15, count 0 2006.201.02:22:17.02#ibcon#read 3, iclass 15, count 0 2006.201.02:22:17.02#ibcon#about to read 4, iclass 15, count 0 2006.201.02:22:17.02#ibcon#read 4, iclass 15, count 0 2006.201.02:22:17.02#ibcon#about to read 5, iclass 15, count 0 2006.201.02:22:17.02#ibcon#read 5, iclass 15, count 0 2006.201.02:22:17.02#ibcon#about to read 6, iclass 15, count 0 2006.201.02:22:17.02#ibcon#read 6, iclass 15, count 0 2006.201.02:22:17.02#ibcon#end of sib2, iclass 15, count 0 2006.201.02:22:17.02#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:22:17.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:22:17.02#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:22:17.02#ibcon#*before write, iclass 15, count 0 2006.201.02:22:17.02#ibcon#enter sib2, iclass 15, count 0 2006.201.02:22:17.02#ibcon#flushed, iclass 15, count 0 2006.201.02:22:17.02#ibcon#about to write, iclass 15, count 0 2006.201.02:22:17.02#ibcon#wrote, iclass 15, count 0 2006.201.02:22:17.02#ibcon#about to read 3, iclass 15, count 0 2006.201.02:22:17.07#ibcon#read 3, iclass 15, count 0 2006.201.02:22:17.07#ibcon#about to read 4, iclass 15, count 0 2006.201.02:22:17.07#ibcon#read 4, iclass 15, count 0 2006.201.02:22:17.07#ibcon#about to read 5, iclass 15, count 0 2006.201.02:22:17.07#ibcon#read 5, iclass 15, count 0 2006.201.02:22:17.07#ibcon#about to read 6, iclass 15, count 0 2006.201.02:22:17.07#ibcon#read 6, iclass 15, count 0 2006.201.02:22:17.07#ibcon#end of sib2, iclass 15, count 0 2006.201.02:22:17.07#ibcon#*after write, iclass 15, count 0 2006.201.02:22:17.07#ibcon#*before return 0, iclass 15, count 0 2006.201.02:22:17.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:17.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:17.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:22:17.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:22:17.07$vck44/va=2,7 2006.201.02:22:17.07#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.02:22:17.07#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.02:22:17.07#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:17.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:17.12#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:17.12#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:17.12#ibcon#enter wrdev, iclass 17, count 2 2006.201.02:22:17.12#ibcon#first serial, iclass 17, count 2 2006.201.02:22:17.12#ibcon#enter sib2, iclass 17, count 2 2006.201.02:22:17.12#ibcon#flushed, iclass 17, count 2 2006.201.02:22:17.12#ibcon#about to write, iclass 17, count 2 2006.201.02:22:17.12#ibcon#wrote, iclass 17, count 2 2006.201.02:22:17.12#ibcon#about to read 3, iclass 17, count 2 2006.201.02:22:17.14#ibcon#read 3, iclass 17, count 2 2006.201.02:22:17.14#ibcon#about to read 4, iclass 17, count 2 2006.201.02:22:17.14#ibcon#read 4, iclass 17, count 2 2006.201.02:22:17.14#ibcon#about to read 5, iclass 17, count 2 2006.201.02:22:17.14#ibcon#read 5, iclass 17, count 2 2006.201.02:22:17.14#ibcon#about to read 6, iclass 17, count 2 2006.201.02:22:17.14#ibcon#read 6, iclass 17, count 2 2006.201.02:22:17.14#ibcon#end of sib2, iclass 17, count 2 2006.201.02:22:17.14#ibcon#*mode == 0, iclass 17, count 2 2006.201.02:22:17.14#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.02:22:17.14#ibcon#[25=AT02-07\r\n] 2006.201.02:22:17.14#ibcon#*before write, iclass 17, count 2 2006.201.02:22:17.14#ibcon#enter sib2, iclass 17, count 2 2006.201.02:22:17.14#ibcon#flushed, iclass 17, count 2 2006.201.02:22:17.14#ibcon#about to write, iclass 17, count 2 2006.201.02:22:17.14#ibcon#wrote, iclass 17, count 2 2006.201.02:22:17.14#ibcon#about to read 3, iclass 17, count 2 2006.201.02:22:17.17#ibcon#read 3, iclass 17, count 2 2006.201.02:22:17.17#ibcon#about to read 4, iclass 17, count 2 2006.201.02:22:17.17#ibcon#read 4, iclass 17, count 2 2006.201.02:22:17.17#ibcon#about to read 5, iclass 17, count 2 2006.201.02:22:17.17#ibcon#read 5, iclass 17, count 2 2006.201.02:22:17.17#ibcon#about to read 6, iclass 17, count 2 2006.201.02:22:17.17#ibcon#read 6, iclass 17, count 2 2006.201.02:22:17.17#ibcon#end of sib2, iclass 17, count 2 2006.201.02:22:17.17#ibcon#*after write, iclass 17, count 2 2006.201.02:22:17.17#ibcon#*before return 0, iclass 17, count 2 2006.201.02:22:17.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:17.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:17.17#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.02:22:17.17#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:17.17#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:17.29#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:17.29#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:17.29#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:22:17.29#ibcon#first serial, iclass 17, count 0 2006.201.02:22:17.29#ibcon#enter sib2, iclass 17, count 0 2006.201.02:22:17.29#ibcon#flushed, iclass 17, count 0 2006.201.02:22:17.29#ibcon#about to write, iclass 17, count 0 2006.201.02:22:17.29#ibcon#wrote, iclass 17, count 0 2006.201.02:22:17.29#ibcon#about to read 3, iclass 17, count 0 2006.201.02:22:17.31#ibcon#read 3, iclass 17, count 0 2006.201.02:22:17.31#ibcon#about to read 4, iclass 17, count 0 2006.201.02:22:17.31#ibcon#read 4, iclass 17, count 0 2006.201.02:22:17.31#ibcon#about to read 5, iclass 17, count 0 2006.201.02:22:17.31#ibcon#read 5, iclass 17, count 0 2006.201.02:22:17.31#ibcon#about to read 6, iclass 17, count 0 2006.201.02:22:17.31#ibcon#read 6, iclass 17, count 0 2006.201.02:22:17.31#ibcon#end of sib2, iclass 17, count 0 2006.201.02:22:17.31#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:22:17.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:22:17.31#ibcon#[25=USB\r\n] 2006.201.02:22:17.31#ibcon#*before write, iclass 17, count 0 2006.201.02:22:17.31#ibcon#enter sib2, iclass 17, count 0 2006.201.02:22:17.31#ibcon#flushed, iclass 17, count 0 2006.201.02:22:17.31#ibcon#about to write, iclass 17, count 0 2006.201.02:22:17.31#ibcon#wrote, iclass 17, count 0 2006.201.02:22:17.31#ibcon#about to read 3, iclass 17, count 0 2006.201.02:22:17.34#ibcon#read 3, iclass 17, count 0 2006.201.02:22:17.34#ibcon#about to read 4, iclass 17, count 0 2006.201.02:22:17.34#ibcon#read 4, iclass 17, count 0 2006.201.02:22:17.34#ibcon#about to read 5, iclass 17, count 0 2006.201.02:22:17.34#ibcon#read 5, iclass 17, count 0 2006.201.02:22:17.34#ibcon#about to read 6, iclass 17, count 0 2006.201.02:22:17.34#ibcon#read 6, iclass 17, count 0 2006.201.02:22:17.34#ibcon#end of sib2, iclass 17, count 0 2006.201.02:22:17.34#ibcon#*after write, iclass 17, count 0 2006.201.02:22:17.34#ibcon#*before return 0, iclass 17, count 0 2006.201.02:22:17.34#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:17.34#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:17.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:22:17.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:22:17.34$vck44/valo=3,564.99 2006.201.02:22:17.34#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.02:22:17.34#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.02:22:17.34#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:17.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:17.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:17.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:17.34#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:22:17.34#ibcon#first serial, iclass 19, count 0 2006.201.02:22:17.34#ibcon#enter sib2, iclass 19, count 0 2006.201.02:22:17.34#ibcon#flushed, iclass 19, count 0 2006.201.02:22:17.34#ibcon#about to write, iclass 19, count 0 2006.201.02:22:17.34#ibcon#wrote, iclass 19, count 0 2006.201.02:22:17.34#ibcon#about to read 3, iclass 19, count 0 2006.201.02:22:17.36#ibcon#read 3, iclass 19, count 0 2006.201.02:22:17.36#ibcon#about to read 4, iclass 19, count 0 2006.201.02:22:17.36#ibcon#read 4, iclass 19, count 0 2006.201.02:22:17.36#ibcon#about to read 5, iclass 19, count 0 2006.201.02:22:17.36#ibcon#read 5, iclass 19, count 0 2006.201.02:22:17.36#ibcon#about to read 6, iclass 19, count 0 2006.201.02:22:17.36#ibcon#read 6, iclass 19, count 0 2006.201.02:22:17.36#ibcon#end of sib2, iclass 19, count 0 2006.201.02:22:17.36#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:22:17.36#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:22:17.36#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:22:17.36#ibcon#*before write, iclass 19, count 0 2006.201.02:22:17.36#ibcon#enter sib2, iclass 19, count 0 2006.201.02:22:17.36#ibcon#flushed, iclass 19, count 0 2006.201.02:22:17.36#ibcon#about to write, iclass 19, count 0 2006.201.02:22:17.36#ibcon#wrote, iclass 19, count 0 2006.201.02:22:17.36#ibcon#about to read 3, iclass 19, count 0 2006.201.02:22:17.41#ibcon#read 3, iclass 19, count 0 2006.201.02:22:17.41#ibcon#about to read 4, iclass 19, count 0 2006.201.02:22:17.41#ibcon#read 4, iclass 19, count 0 2006.201.02:22:17.41#ibcon#about to read 5, iclass 19, count 0 2006.201.02:22:17.41#ibcon#read 5, iclass 19, count 0 2006.201.02:22:17.41#ibcon#about to read 6, iclass 19, count 0 2006.201.02:22:17.41#ibcon#read 6, iclass 19, count 0 2006.201.02:22:17.41#ibcon#end of sib2, iclass 19, count 0 2006.201.02:22:17.41#ibcon#*after write, iclass 19, count 0 2006.201.02:22:17.41#ibcon#*before return 0, iclass 19, count 0 2006.201.02:22:17.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:17.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:17.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:22:17.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:22:17.41$vck44/va=3,8 2006.201.02:22:17.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.02:22:17.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.02:22:17.41#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:17.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:17.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:17.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:17.46#ibcon#enter wrdev, iclass 21, count 2 2006.201.02:22:17.46#ibcon#first serial, iclass 21, count 2 2006.201.02:22:17.46#ibcon#enter sib2, iclass 21, count 2 2006.201.02:22:17.46#ibcon#flushed, iclass 21, count 2 2006.201.02:22:17.46#ibcon#about to write, iclass 21, count 2 2006.201.02:22:17.46#ibcon#wrote, iclass 21, count 2 2006.201.02:22:17.46#ibcon#about to read 3, iclass 21, count 2 2006.201.02:22:17.48#ibcon#read 3, iclass 21, count 2 2006.201.02:22:17.48#ibcon#about to read 4, iclass 21, count 2 2006.201.02:22:17.48#ibcon#read 4, iclass 21, count 2 2006.201.02:22:17.48#ibcon#about to read 5, iclass 21, count 2 2006.201.02:22:17.48#ibcon#read 5, iclass 21, count 2 2006.201.02:22:17.48#ibcon#about to read 6, iclass 21, count 2 2006.201.02:22:17.48#ibcon#read 6, iclass 21, count 2 2006.201.02:22:17.48#ibcon#end of sib2, iclass 21, count 2 2006.201.02:22:17.48#ibcon#*mode == 0, iclass 21, count 2 2006.201.02:22:17.48#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.02:22:17.48#ibcon#[25=AT03-08\r\n] 2006.201.02:22:17.48#ibcon#*before write, iclass 21, count 2 2006.201.02:22:17.48#ibcon#enter sib2, iclass 21, count 2 2006.201.02:22:17.48#ibcon#flushed, iclass 21, count 2 2006.201.02:22:17.48#ibcon#about to write, iclass 21, count 2 2006.201.02:22:17.48#ibcon#wrote, iclass 21, count 2 2006.201.02:22:17.48#ibcon#about to read 3, iclass 21, count 2 2006.201.02:22:17.51#ibcon#read 3, iclass 21, count 2 2006.201.02:22:17.51#ibcon#about to read 4, iclass 21, count 2 2006.201.02:22:17.51#ibcon#read 4, iclass 21, count 2 2006.201.02:22:17.51#ibcon#about to read 5, iclass 21, count 2 2006.201.02:22:17.51#ibcon#read 5, iclass 21, count 2 2006.201.02:22:17.51#ibcon#about to read 6, iclass 21, count 2 2006.201.02:22:17.51#ibcon#read 6, iclass 21, count 2 2006.201.02:22:17.51#ibcon#end of sib2, iclass 21, count 2 2006.201.02:22:17.51#ibcon#*after write, iclass 21, count 2 2006.201.02:22:17.51#ibcon#*before return 0, iclass 21, count 2 2006.201.02:22:17.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:17.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:17.51#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.02:22:17.51#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:17.51#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:17.63#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:17.63#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:17.63#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:22:17.63#ibcon#first serial, iclass 21, count 0 2006.201.02:22:17.63#ibcon#enter sib2, iclass 21, count 0 2006.201.02:22:17.63#ibcon#flushed, iclass 21, count 0 2006.201.02:22:17.63#ibcon#about to write, iclass 21, count 0 2006.201.02:22:17.63#ibcon#wrote, iclass 21, count 0 2006.201.02:22:17.63#ibcon#about to read 3, iclass 21, count 0 2006.201.02:22:17.65#ibcon#read 3, iclass 21, count 0 2006.201.02:22:17.65#ibcon#about to read 4, iclass 21, count 0 2006.201.02:22:17.65#ibcon#read 4, iclass 21, count 0 2006.201.02:22:17.65#ibcon#about to read 5, iclass 21, count 0 2006.201.02:22:17.65#ibcon#read 5, iclass 21, count 0 2006.201.02:22:17.65#ibcon#about to read 6, iclass 21, count 0 2006.201.02:22:17.65#ibcon#read 6, iclass 21, count 0 2006.201.02:22:17.65#ibcon#end of sib2, iclass 21, count 0 2006.201.02:22:17.65#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:22:17.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:22:17.65#ibcon#[25=USB\r\n] 2006.201.02:22:17.65#ibcon#*before write, iclass 21, count 0 2006.201.02:22:17.65#ibcon#enter sib2, iclass 21, count 0 2006.201.02:22:17.65#ibcon#flushed, iclass 21, count 0 2006.201.02:22:17.65#ibcon#about to write, iclass 21, count 0 2006.201.02:22:17.65#ibcon#wrote, iclass 21, count 0 2006.201.02:22:17.65#ibcon#about to read 3, iclass 21, count 0 2006.201.02:22:17.68#ibcon#read 3, iclass 21, count 0 2006.201.02:22:17.68#ibcon#about to read 4, iclass 21, count 0 2006.201.02:22:17.68#ibcon#read 4, iclass 21, count 0 2006.201.02:22:17.68#ibcon#about to read 5, iclass 21, count 0 2006.201.02:22:17.68#ibcon#read 5, iclass 21, count 0 2006.201.02:22:17.68#ibcon#about to read 6, iclass 21, count 0 2006.201.02:22:17.68#ibcon#read 6, iclass 21, count 0 2006.201.02:22:17.68#ibcon#end of sib2, iclass 21, count 0 2006.201.02:22:17.68#ibcon#*after write, iclass 21, count 0 2006.201.02:22:17.68#ibcon#*before return 0, iclass 21, count 0 2006.201.02:22:17.68#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:17.68#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:17.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:22:17.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:22:17.68$vck44/valo=4,624.99 2006.201.02:22:17.68#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.02:22:17.68#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.02:22:17.68#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:17.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:17.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:17.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:17.68#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:22:17.68#ibcon#first serial, iclass 23, count 0 2006.201.02:22:17.68#ibcon#enter sib2, iclass 23, count 0 2006.201.02:22:17.68#ibcon#flushed, iclass 23, count 0 2006.201.02:22:17.68#ibcon#about to write, iclass 23, count 0 2006.201.02:22:17.68#ibcon#wrote, iclass 23, count 0 2006.201.02:22:17.68#ibcon#about to read 3, iclass 23, count 0 2006.201.02:22:17.70#ibcon#read 3, iclass 23, count 0 2006.201.02:22:17.70#ibcon#about to read 4, iclass 23, count 0 2006.201.02:22:17.70#ibcon#read 4, iclass 23, count 0 2006.201.02:22:17.70#ibcon#about to read 5, iclass 23, count 0 2006.201.02:22:17.70#ibcon#read 5, iclass 23, count 0 2006.201.02:22:17.70#ibcon#about to read 6, iclass 23, count 0 2006.201.02:22:17.70#ibcon#read 6, iclass 23, count 0 2006.201.02:22:17.70#ibcon#end of sib2, iclass 23, count 0 2006.201.02:22:17.70#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:22:17.70#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:22:17.70#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:22:17.70#ibcon#*before write, iclass 23, count 0 2006.201.02:22:17.70#ibcon#enter sib2, iclass 23, count 0 2006.201.02:22:17.70#ibcon#flushed, iclass 23, count 0 2006.201.02:22:17.70#ibcon#about to write, iclass 23, count 0 2006.201.02:22:17.70#ibcon#wrote, iclass 23, count 0 2006.201.02:22:17.70#ibcon#about to read 3, iclass 23, count 0 2006.201.02:22:17.75#ibcon#read 3, iclass 23, count 0 2006.201.02:22:17.75#ibcon#about to read 4, iclass 23, count 0 2006.201.02:22:17.75#ibcon#read 4, iclass 23, count 0 2006.201.02:22:17.75#ibcon#about to read 5, iclass 23, count 0 2006.201.02:22:17.75#ibcon#read 5, iclass 23, count 0 2006.201.02:22:17.75#ibcon#about to read 6, iclass 23, count 0 2006.201.02:22:17.75#ibcon#read 6, iclass 23, count 0 2006.201.02:22:17.75#ibcon#end of sib2, iclass 23, count 0 2006.201.02:22:17.75#ibcon#*after write, iclass 23, count 0 2006.201.02:22:17.75#ibcon#*before return 0, iclass 23, count 0 2006.201.02:22:17.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:17.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:17.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:22:17.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:22:17.75$vck44/va=4,7 2006.201.02:22:17.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.02:22:17.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.02:22:17.75#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:17.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:17.80#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:17.80#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:17.80#ibcon#enter wrdev, iclass 25, count 2 2006.201.02:22:17.80#ibcon#first serial, iclass 25, count 2 2006.201.02:22:17.80#ibcon#enter sib2, iclass 25, count 2 2006.201.02:22:17.80#ibcon#flushed, iclass 25, count 2 2006.201.02:22:17.80#ibcon#about to write, iclass 25, count 2 2006.201.02:22:17.80#ibcon#wrote, iclass 25, count 2 2006.201.02:22:17.80#ibcon#about to read 3, iclass 25, count 2 2006.201.02:22:17.82#ibcon#read 3, iclass 25, count 2 2006.201.02:22:17.82#ibcon#about to read 4, iclass 25, count 2 2006.201.02:22:17.82#ibcon#read 4, iclass 25, count 2 2006.201.02:22:17.82#ibcon#about to read 5, iclass 25, count 2 2006.201.02:22:17.82#ibcon#read 5, iclass 25, count 2 2006.201.02:22:17.82#ibcon#about to read 6, iclass 25, count 2 2006.201.02:22:17.82#ibcon#read 6, iclass 25, count 2 2006.201.02:22:17.82#ibcon#end of sib2, iclass 25, count 2 2006.201.02:22:17.82#ibcon#*mode == 0, iclass 25, count 2 2006.201.02:22:17.82#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.02:22:17.82#ibcon#[25=AT04-07\r\n] 2006.201.02:22:17.82#ibcon#*before write, iclass 25, count 2 2006.201.02:22:17.82#ibcon#enter sib2, iclass 25, count 2 2006.201.02:22:17.82#ibcon#flushed, iclass 25, count 2 2006.201.02:22:17.82#ibcon#about to write, iclass 25, count 2 2006.201.02:22:17.82#ibcon#wrote, iclass 25, count 2 2006.201.02:22:17.82#ibcon#about to read 3, iclass 25, count 2 2006.201.02:22:17.85#ibcon#read 3, iclass 25, count 2 2006.201.02:22:17.85#ibcon#about to read 4, iclass 25, count 2 2006.201.02:22:17.85#ibcon#read 4, iclass 25, count 2 2006.201.02:22:17.85#ibcon#about to read 5, iclass 25, count 2 2006.201.02:22:17.85#ibcon#read 5, iclass 25, count 2 2006.201.02:22:17.85#ibcon#about to read 6, iclass 25, count 2 2006.201.02:22:17.85#ibcon#read 6, iclass 25, count 2 2006.201.02:22:17.85#ibcon#end of sib2, iclass 25, count 2 2006.201.02:22:17.85#ibcon#*after write, iclass 25, count 2 2006.201.02:22:17.85#ibcon#*before return 0, iclass 25, count 2 2006.201.02:22:17.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:17.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:17.85#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.02:22:17.85#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:17.85#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:17.97#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:17.97#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:17.97#ibcon#enter wrdev, iclass 25, count 0 2006.201.02:22:17.97#ibcon#first serial, iclass 25, count 0 2006.201.02:22:17.97#ibcon#enter sib2, iclass 25, count 0 2006.201.02:22:17.97#ibcon#flushed, iclass 25, count 0 2006.201.02:22:17.97#ibcon#about to write, iclass 25, count 0 2006.201.02:22:17.97#ibcon#wrote, iclass 25, count 0 2006.201.02:22:17.97#ibcon#about to read 3, iclass 25, count 0 2006.201.02:22:17.99#ibcon#read 3, iclass 25, count 0 2006.201.02:22:17.99#ibcon#about to read 4, iclass 25, count 0 2006.201.02:22:17.99#ibcon#read 4, iclass 25, count 0 2006.201.02:22:17.99#ibcon#about to read 5, iclass 25, count 0 2006.201.02:22:17.99#ibcon#read 5, iclass 25, count 0 2006.201.02:22:17.99#ibcon#about to read 6, iclass 25, count 0 2006.201.02:22:17.99#ibcon#read 6, iclass 25, count 0 2006.201.02:22:17.99#ibcon#end of sib2, iclass 25, count 0 2006.201.02:22:17.99#ibcon#*mode == 0, iclass 25, count 0 2006.201.02:22:17.99#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.02:22:17.99#ibcon#[25=USB\r\n] 2006.201.02:22:17.99#ibcon#*before write, iclass 25, count 0 2006.201.02:22:17.99#ibcon#enter sib2, iclass 25, count 0 2006.201.02:22:17.99#ibcon#flushed, iclass 25, count 0 2006.201.02:22:17.99#ibcon#about to write, iclass 25, count 0 2006.201.02:22:17.99#ibcon#wrote, iclass 25, count 0 2006.201.02:22:17.99#ibcon#about to read 3, iclass 25, count 0 2006.201.02:22:18.02#ibcon#read 3, iclass 25, count 0 2006.201.02:22:18.02#ibcon#about to read 4, iclass 25, count 0 2006.201.02:22:18.02#ibcon#read 4, iclass 25, count 0 2006.201.02:22:18.02#ibcon#about to read 5, iclass 25, count 0 2006.201.02:22:18.02#ibcon#read 5, iclass 25, count 0 2006.201.02:22:18.02#ibcon#about to read 6, iclass 25, count 0 2006.201.02:22:18.02#ibcon#read 6, iclass 25, count 0 2006.201.02:22:18.02#ibcon#end of sib2, iclass 25, count 0 2006.201.02:22:18.02#ibcon#*after write, iclass 25, count 0 2006.201.02:22:18.02#ibcon#*before return 0, iclass 25, count 0 2006.201.02:22:18.02#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:18.02#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:18.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.02:22:18.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.02:22:18.02$vck44/valo=5,734.99 2006.201.02:22:18.02#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.02:22:18.02#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.02:22:18.02#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:18.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:18.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:18.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:18.02#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:22:18.02#ibcon#first serial, iclass 27, count 0 2006.201.02:22:18.02#ibcon#enter sib2, iclass 27, count 0 2006.201.02:22:18.02#ibcon#flushed, iclass 27, count 0 2006.201.02:22:18.02#ibcon#about to write, iclass 27, count 0 2006.201.02:22:18.02#ibcon#wrote, iclass 27, count 0 2006.201.02:22:18.02#ibcon#about to read 3, iclass 27, count 0 2006.201.02:22:18.04#ibcon#read 3, iclass 27, count 0 2006.201.02:22:18.04#ibcon#about to read 4, iclass 27, count 0 2006.201.02:22:18.04#ibcon#read 4, iclass 27, count 0 2006.201.02:22:18.04#ibcon#about to read 5, iclass 27, count 0 2006.201.02:22:18.04#ibcon#read 5, iclass 27, count 0 2006.201.02:22:18.04#ibcon#about to read 6, iclass 27, count 0 2006.201.02:22:18.04#ibcon#read 6, iclass 27, count 0 2006.201.02:22:18.04#ibcon#end of sib2, iclass 27, count 0 2006.201.02:22:18.04#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:22:18.04#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:22:18.04#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:22:18.04#ibcon#*before write, iclass 27, count 0 2006.201.02:22:18.04#ibcon#enter sib2, iclass 27, count 0 2006.201.02:22:18.04#ibcon#flushed, iclass 27, count 0 2006.201.02:22:18.04#ibcon#about to write, iclass 27, count 0 2006.201.02:22:18.04#ibcon#wrote, iclass 27, count 0 2006.201.02:22:18.04#ibcon#about to read 3, iclass 27, count 0 2006.201.02:22:18.08#ibcon#read 3, iclass 27, count 0 2006.201.02:22:18.08#ibcon#about to read 4, iclass 27, count 0 2006.201.02:22:18.08#ibcon#read 4, iclass 27, count 0 2006.201.02:22:18.08#ibcon#about to read 5, iclass 27, count 0 2006.201.02:22:18.08#ibcon#read 5, iclass 27, count 0 2006.201.02:22:18.08#ibcon#about to read 6, iclass 27, count 0 2006.201.02:22:18.08#ibcon#read 6, iclass 27, count 0 2006.201.02:22:18.08#ibcon#end of sib2, iclass 27, count 0 2006.201.02:22:18.08#ibcon#*after write, iclass 27, count 0 2006.201.02:22:18.08#ibcon#*before return 0, iclass 27, count 0 2006.201.02:22:18.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:18.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:18.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:22:18.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:22:18.08$vck44/va=5,4 2006.201.02:22:18.08#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.02:22:18.08#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.02:22:18.08#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:18.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:18.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:18.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:18.14#ibcon#enter wrdev, iclass 29, count 2 2006.201.02:22:18.14#ibcon#first serial, iclass 29, count 2 2006.201.02:22:18.14#ibcon#enter sib2, iclass 29, count 2 2006.201.02:22:18.14#ibcon#flushed, iclass 29, count 2 2006.201.02:22:18.14#ibcon#about to write, iclass 29, count 2 2006.201.02:22:18.14#ibcon#wrote, iclass 29, count 2 2006.201.02:22:18.14#ibcon#about to read 3, iclass 29, count 2 2006.201.02:22:18.16#ibcon#read 3, iclass 29, count 2 2006.201.02:22:18.16#ibcon#about to read 4, iclass 29, count 2 2006.201.02:22:18.16#ibcon#read 4, iclass 29, count 2 2006.201.02:22:18.16#ibcon#about to read 5, iclass 29, count 2 2006.201.02:22:18.16#ibcon#read 5, iclass 29, count 2 2006.201.02:22:18.16#ibcon#about to read 6, iclass 29, count 2 2006.201.02:22:18.16#ibcon#read 6, iclass 29, count 2 2006.201.02:22:18.16#ibcon#end of sib2, iclass 29, count 2 2006.201.02:22:18.16#ibcon#*mode == 0, iclass 29, count 2 2006.201.02:22:18.16#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.02:22:18.16#ibcon#[25=AT05-04\r\n] 2006.201.02:22:18.16#ibcon#*before write, iclass 29, count 2 2006.201.02:22:18.16#ibcon#enter sib2, iclass 29, count 2 2006.201.02:22:18.16#ibcon#flushed, iclass 29, count 2 2006.201.02:22:18.16#ibcon#about to write, iclass 29, count 2 2006.201.02:22:18.16#ibcon#wrote, iclass 29, count 2 2006.201.02:22:18.16#ibcon#about to read 3, iclass 29, count 2 2006.201.02:22:18.19#ibcon#read 3, iclass 29, count 2 2006.201.02:22:18.19#ibcon#about to read 4, iclass 29, count 2 2006.201.02:22:18.19#ibcon#read 4, iclass 29, count 2 2006.201.02:22:18.19#ibcon#about to read 5, iclass 29, count 2 2006.201.02:22:18.19#ibcon#read 5, iclass 29, count 2 2006.201.02:22:18.19#ibcon#about to read 6, iclass 29, count 2 2006.201.02:22:18.19#ibcon#read 6, iclass 29, count 2 2006.201.02:22:18.19#ibcon#end of sib2, iclass 29, count 2 2006.201.02:22:18.19#ibcon#*after write, iclass 29, count 2 2006.201.02:22:18.19#ibcon#*before return 0, iclass 29, count 2 2006.201.02:22:18.19#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:18.19#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:18.19#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.02:22:18.19#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:18.19#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:18.31#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:18.31#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:18.31#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:22:18.31#ibcon#first serial, iclass 29, count 0 2006.201.02:22:18.31#ibcon#enter sib2, iclass 29, count 0 2006.201.02:22:18.31#ibcon#flushed, iclass 29, count 0 2006.201.02:22:18.31#ibcon#about to write, iclass 29, count 0 2006.201.02:22:18.31#ibcon#wrote, iclass 29, count 0 2006.201.02:22:18.31#ibcon#about to read 3, iclass 29, count 0 2006.201.02:22:18.33#ibcon#read 3, iclass 29, count 0 2006.201.02:22:18.33#ibcon#about to read 4, iclass 29, count 0 2006.201.02:22:18.33#ibcon#read 4, iclass 29, count 0 2006.201.02:22:18.33#ibcon#about to read 5, iclass 29, count 0 2006.201.02:22:18.33#ibcon#read 5, iclass 29, count 0 2006.201.02:22:18.33#ibcon#about to read 6, iclass 29, count 0 2006.201.02:22:18.33#ibcon#read 6, iclass 29, count 0 2006.201.02:22:18.33#ibcon#end of sib2, iclass 29, count 0 2006.201.02:22:18.33#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:22:18.33#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:22:18.33#ibcon#[25=USB\r\n] 2006.201.02:22:18.33#ibcon#*before write, iclass 29, count 0 2006.201.02:22:18.33#ibcon#enter sib2, iclass 29, count 0 2006.201.02:22:18.33#ibcon#flushed, iclass 29, count 0 2006.201.02:22:18.33#ibcon#about to write, iclass 29, count 0 2006.201.02:22:18.33#ibcon#wrote, iclass 29, count 0 2006.201.02:22:18.33#ibcon#about to read 3, iclass 29, count 0 2006.201.02:22:18.36#ibcon#read 3, iclass 29, count 0 2006.201.02:22:18.36#ibcon#about to read 4, iclass 29, count 0 2006.201.02:22:18.36#ibcon#read 4, iclass 29, count 0 2006.201.02:22:18.36#ibcon#about to read 5, iclass 29, count 0 2006.201.02:22:18.36#ibcon#read 5, iclass 29, count 0 2006.201.02:22:18.36#ibcon#about to read 6, iclass 29, count 0 2006.201.02:22:18.36#ibcon#read 6, iclass 29, count 0 2006.201.02:22:18.36#ibcon#end of sib2, iclass 29, count 0 2006.201.02:22:18.36#ibcon#*after write, iclass 29, count 0 2006.201.02:22:18.36#ibcon#*before return 0, iclass 29, count 0 2006.201.02:22:18.36#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:18.36#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:18.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:22:18.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:22:18.36$vck44/valo=6,814.99 2006.201.02:22:18.36#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.02:22:18.36#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.02:22:18.36#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:18.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:18.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:18.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:18.36#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:22:18.36#ibcon#first serial, iclass 31, count 0 2006.201.02:22:18.36#ibcon#enter sib2, iclass 31, count 0 2006.201.02:22:18.36#ibcon#flushed, iclass 31, count 0 2006.201.02:22:18.36#ibcon#about to write, iclass 31, count 0 2006.201.02:22:18.36#ibcon#wrote, iclass 31, count 0 2006.201.02:22:18.36#ibcon#about to read 3, iclass 31, count 0 2006.201.02:22:18.38#ibcon#read 3, iclass 31, count 0 2006.201.02:22:18.38#ibcon#about to read 4, iclass 31, count 0 2006.201.02:22:18.38#ibcon#read 4, iclass 31, count 0 2006.201.02:22:18.38#ibcon#about to read 5, iclass 31, count 0 2006.201.02:22:18.38#ibcon#read 5, iclass 31, count 0 2006.201.02:22:18.38#ibcon#about to read 6, iclass 31, count 0 2006.201.02:22:18.38#ibcon#read 6, iclass 31, count 0 2006.201.02:22:18.38#ibcon#end of sib2, iclass 31, count 0 2006.201.02:22:18.38#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:22:18.38#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:22:18.38#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:22:18.38#ibcon#*before write, iclass 31, count 0 2006.201.02:22:18.38#ibcon#enter sib2, iclass 31, count 0 2006.201.02:22:18.38#ibcon#flushed, iclass 31, count 0 2006.201.02:22:18.38#ibcon#about to write, iclass 31, count 0 2006.201.02:22:18.38#ibcon#wrote, iclass 31, count 0 2006.201.02:22:18.38#ibcon#about to read 3, iclass 31, count 0 2006.201.02:22:18.43#ibcon#read 3, iclass 31, count 0 2006.201.02:22:18.43#ibcon#about to read 4, iclass 31, count 0 2006.201.02:22:18.43#ibcon#read 4, iclass 31, count 0 2006.201.02:22:18.43#ibcon#about to read 5, iclass 31, count 0 2006.201.02:22:18.43#ibcon#read 5, iclass 31, count 0 2006.201.02:22:18.43#ibcon#about to read 6, iclass 31, count 0 2006.201.02:22:18.43#ibcon#read 6, iclass 31, count 0 2006.201.02:22:18.43#ibcon#end of sib2, iclass 31, count 0 2006.201.02:22:18.43#ibcon#*after write, iclass 31, count 0 2006.201.02:22:18.43#ibcon#*before return 0, iclass 31, count 0 2006.201.02:22:18.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:18.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:18.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:22:18.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:22:18.43$vck44/va=6,5 2006.201.02:22:18.43#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.02:22:18.43#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.02:22:18.43#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:18.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:18.48#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:18.48#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:18.48#ibcon#enter wrdev, iclass 33, count 2 2006.201.02:22:18.48#ibcon#first serial, iclass 33, count 2 2006.201.02:22:18.48#ibcon#enter sib2, iclass 33, count 2 2006.201.02:22:18.48#ibcon#flushed, iclass 33, count 2 2006.201.02:22:18.48#ibcon#about to write, iclass 33, count 2 2006.201.02:22:18.48#ibcon#wrote, iclass 33, count 2 2006.201.02:22:18.48#ibcon#about to read 3, iclass 33, count 2 2006.201.02:22:18.50#ibcon#read 3, iclass 33, count 2 2006.201.02:22:18.50#ibcon#about to read 4, iclass 33, count 2 2006.201.02:22:18.50#ibcon#read 4, iclass 33, count 2 2006.201.02:22:18.50#ibcon#about to read 5, iclass 33, count 2 2006.201.02:22:18.50#ibcon#read 5, iclass 33, count 2 2006.201.02:22:18.50#ibcon#about to read 6, iclass 33, count 2 2006.201.02:22:18.50#ibcon#read 6, iclass 33, count 2 2006.201.02:22:18.50#ibcon#end of sib2, iclass 33, count 2 2006.201.02:22:18.50#ibcon#*mode == 0, iclass 33, count 2 2006.201.02:22:18.50#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.02:22:18.50#ibcon#[25=AT06-05\r\n] 2006.201.02:22:18.50#ibcon#*before write, iclass 33, count 2 2006.201.02:22:18.50#ibcon#enter sib2, iclass 33, count 2 2006.201.02:22:18.50#ibcon#flushed, iclass 33, count 2 2006.201.02:22:18.50#ibcon#about to write, iclass 33, count 2 2006.201.02:22:18.50#ibcon#wrote, iclass 33, count 2 2006.201.02:22:18.50#ibcon#about to read 3, iclass 33, count 2 2006.201.02:22:18.53#ibcon#read 3, iclass 33, count 2 2006.201.02:22:18.53#ibcon#about to read 4, iclass 33, count 2 2006.201.02:22:18.53#ibcon#read 4, iclass 33, count 2 2006.201.02:22:18.53#ibcon#about to read 5, iclass 33, count 2 2006.201.02:22:18.53#ibcon#read 5, iclass 33, count 2 2006.201.02:22:18.53#ibcon#about to read 6, iclass 33, count 2 2006.201.02:22:18.53#ibcon#read 6, iclass 33, count 2 2006.201.02:22:18.53#ibcon#end of sib2, iclass 33, count 2 2006.201.02:22:18.53#ibcon#*after write, iclass 33, count 2 2006.201.02:22:18.53#ibcon#*before return 0, iclass 33, count 2 2006.201.02:22:18.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:18.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:18.53#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.02:22:18.53#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:18.53#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:18.65#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:18.65#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:18.65#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:22:18.65#ibcon#first serial, iclass 33, count 0 2006.201.02:22:18.65#ibcon#enter sib2, iclass 33, count 0 2006.201.02:22:18.65#ibcon#flushed, iclass 33, count 0 2006.201.02:22:18.65#ibcon#about to write, iclass 33, count 0 2006.201.02:22:18.65#ibcon#wrote, iclass 33, count 0 2006.201.02:22:18.65#ibcon#about to read 3, iclass 33, count 0 2006.201.02:22:18.67#ibcon#read 3, iclass 33, count 0 2006.201.02:22:18.67#ibcon#about to read 4, iclass 33, count 0 2006.201.02:22:18.67#ibcon#read 4, iclass 33, count 0 2006.201.02:22:18.67#ibcon#about to read 5, iclass 33, count 0 2006.201.02:22:18.67#ibcon#read 5, iclass 33, count 0 2006.201.02:22:18.67#ibcon#about to read 6, iclass 33, count 0 2006.201.02:22:18.67#ibcon#read 6, iclass 33, count 0 2006.201.02:22:18.67#ibcon#end of sib2, iclass 33, count 0 2006.201.02:22:18.67#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:22:18.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:22:18.67#ibcon#[25=USB\r\n] 2006.201.02:22:18.67#ibcon#*before write, iclass 33, count 0 2006.201.02:22:18.67#ibcon#enter sib2, iclass 33, count 0 2006.201.02:22:18.67#ibcon#flushed, iclass 33, count 0 2006.201.02:22:18.67#ibcon#about to write, iclass 33, count 0 2006.201.02:22:18.67#ibcon#wrote, iclass 33, count 0 2006.201.02:22:18.67#ibcon#about to read 3, iclass 33, count 0 2006.201.02:22:18.70#ibcon#read 3, iclass 33, count 0 2006.201.02:22:18.70#ibcon#about to read 4, iclass 33, count 0 2006.201.02:22:18.70#ibcon#read 4, iclass 33, count 0 2006.201.02:22:18.70#ibcon#about to read 5, iclass 33, count 0 2006.201.02:22:18.70#ibcon#read 5, iclass 33, count 0 2006.201.02:22:18.70#ibcon#about to read 6, iclass 33, count 0 2006.201.02:22:18.70#ibcon#read 6, iclass 33, count 0 2006.201.02:22:18.70#ibcon#end of sib2, iclass 33, count 0 2006.201.02:22:18.70#ibcon#*after write, iclass 33, count 0 2006.201.02:22:18.70#ibcon#*before return 0, iclass 33, count 0 2006.201.02:22:18.70#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:18.70#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:18.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:22:18.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:22:18.70$vck44/valo=7,864.99 2006.201.02:22:18.70#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.02:22:18.70#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.02:22:18.70#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:18.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:18.70#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:18.70#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:18.70#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:22:18.70#ibcon#first serial, iclass 35, count 0 2006.201.02:22:18.70#ibcon#enter sib2, iclass 35, count 0 2006.201.02:22:18.70#ibcon#flushed, iclass 35, count 0 2006.201.02:22:18.70#ibcon#about to write, iclass 35, count 0 2006.201.02:22:18.70#ibcon#wrote, iclass 35, count 0 2006.201.02:22:18.70#ibcon#about to read 3, iclass 35, count 0 2006.201.02:22:18.72#ibcon#read 3, iclass 35, count 0 2006.201.02:22:18.72#ibcon#about to read 4, iclass 35, count 0 2006.201.02:22:18.72#ibcon#read 4, iclass 35, count 0 2006.201.02:22:18.72#ibcon#about to read 5, iclass 35, count 0 2006.201.02:22:18.72#ibcon#read 5, iclass 35, count 0 2006.201.02:22:18.72#ibcon#about to read 6, iclass 35, count 0 2006.201.02:22:18.72#ibcon#read 6, iclass 35, count 0 2006.201.02:22:18.72#ibcon#end of sib2, iclass 35, count 0 2006.201.02:22:18.72#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:22:18.72#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:22:18.72#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:22:18.72#ibcon#*before write, iclass 35, count 0 2006.201.02:22:18.72#ibcon#enter sib2, iclass 35, count 0 2006.201.02:22:18.72#ibcon#flushed, iclass 35, count 0 2006.201.02:22:18.72#ibcon#about to write, iclass 35, count 0 2006.201.02:22:18.72#ibcon#wrote, iclass 35, count 0 2006.201.02:22:18.72#ibcon#about to read 3, iclass 35, count 0 2006.201.02:22:18.76#ibcon#read 3, iclass 35, count 0 2006.201.02:22:18.76#ibcon#about to read 4, iclass 35, count 0 2006.201.02:22:18.76#ibcon#read 4, iclass 35, count 0 2006.201.02:22:18.76#ibcon#about to read 5, iclass 35, count 0 2006.201.02:22:18.76#ibcon#read 5, iclass 35, count 0 2006.201.02:22:18.76#ibcon#about to read 6, iclass 35, count 0 2006.201.02:22:18.76#ibcon#read 6, iclass 35, count 0 2006.201.02:22:18.76#ibcon#end of sib2, iclass 35, count 0 2006.201.02:22:18.76#ibcon#*after write, iclass 35, count 0 2006.201.02:22:18.76#ibcon#*before return 0, iclass 35, count 0 2006.201.02:22:18.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:18.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:18.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:22:18.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:22:18.76$vck44/va=7,5 2006.201.02:22:18.76#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.02:22:18.76#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.02:22:18.76#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:18.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:18.82#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:18.82#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:18.82#ibcon#enter wrdev, iclass 37, count 2 2006.201.02:22:18.82#ibcon#first serial, iclass 37, count 2 2006.201.02:22:18.82#ibcon#enter sib2, iclass 37, count 2 2006.201.02:22:18.82#ibcon#flushed, iclass 37, count 2 2006.201.02:22:18.82#ibcon#about to write, iclass 37, count 2 2006.201.02:22:18.82#ibcon#wrote, iclass 37, count 2 2006.201.02:22:18.82#ibcon#about to read 3, iclass 37, count 2 2006.201.02:22:18.84#ibcon#read 3, iclass 37, count 2 2006.201.02:22:18.84#ibcon#about to read 4, iclass 37, count 2 2006.201.02:22:18.84#ibcon#read 4, iclass 37, count 2 2006.201.02:22:18.84#ibcon#about to read 5, iclass 37, count 2 2006.201.02:22:18.84#ibcon#read 5, iclass 37, count 2 2006.201.02:22:18.84#ibcon#about to read 6, iclass 37, count 2 2006.201.02:22:18.84#ibcon#read 6, iclass 37, count 2 2006.201.02:22:18.84#ibcon#end of sib2, iclass 37, count 2 2006.201.02:22:18.84#ibcon#*mode == 0, iclass 37, count 2 2006.201.02:22:18.84#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.02:22:18.84#ibcon#[25=AT07-05\r\n] 2006.201.02:22:18.84#ibcon#*before write, iclass 37, count 2 2006.201.02:22:18.84#ibcon#enter sib2, iclass 37, count 2 2006.201.02:22:18.84#ibcon#flushed, iclass 37, count 2 2006.201.02:22:18.84#ibcon#about to write, iclass 37, count 2 2006.201.02:22:18.84#ibcon#wrote, iclass 37, count 2 2006.201.02:22:18.84#ibcon#about to read 3, iclass 37, count 2 2006.201.02:22:18.87#ibcon#read 3, iclass 37, count 2 2006.201.02:22:18.87#ibcon#about to read 4, iclass 37, count 2 2006.201.02:22:18.87#ibcon#read 4, iclass 37, count 2 2006.201.02:22:18.87#ibcon#about to read 5, iclass 37, count 2 2006.201.02:22:18.87#ibcon#read 5, iclass 37, count 2 2006.201.02:22:18.87#ibcon#about to read 6, iclass 37, count 2 2006.201.02:22:18.87#ibcon#read 6, iclass 37, count 2 2006.201.02:22:18.87#ibcon#end of sib2, iclass 37, count 2 2006.201.02:22:18.87#ibcon#*after write, iclass 37, count 2 2006.201.02:22:18.87#ibcon#*before return 0, iclass 37, count 2 2006.201.02:22:18.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:18.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:18.87#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.02:22:18.87#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:18.87#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:18.99#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:18.99#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:18.99#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:22:18.99#ibcon#first serial, iclass 37, count 0 2006.201.02:22:18.99#ibcon#enter sib2, iclass 37, count 0 2006.201.02:22:18.99#ibcon#flushed, iclass 37, count 0 2006.201.02:22:18.99#ibcon#about to write, iclass 37, count 0 2006.201.02:22:18.99#ibcon#wrote, iclass 37, count 0 2006.201.02:22:18.99#ibcon#about to read 3, iclass 37, count 0 2006.201.02:22:19.01#ibcon#read 3, iclass 37, count 0 2006.201.02:22:19.01#ibcon#about to read 4, iclass 37, count 0 2006.201.02:22:19.01#ibcon#read 4, iclass 37, count 0 2006.201.02:22:19.01#ibcon#about to read 5, iclass 37, count 0 2006.201.02:22:19.01#ibcon#read 5, iclass 37, count 0 2006.201.02:22:19.01#ibcon#about to read 6, iclass 37, count 0 2006.201.02:22:19.01#ibcon#read 6, iclass 37, count 0 2006.201.02:22:19.01#ibcon#end of sib2, iclass 37, count 0 2006.201.02:22:19.01#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:22:19.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:22:19.01#ibcon#[25=USB\r\n] 2006.201.02:22:19.01#ibcon#*before write, iclass 37, count 0 2006.201.02:22:19.01#ibcon#enter sib2, iclass 37, count 0 2006.201.02:22:19.01#ibcon#flushed, iclass 37, count 0 2006.201.02:22:19.01#ibcon#about to write, iclass 37, count 0 2006.201.02:22:19.01#ibcon#wrote, iclass 37, count 0 2006.201.02:22:19.01#ibcon#about to read 3, iclass 37, count 0 2006.201.02:22:19.04#ibcon#read 3, iclass 37, count 0 2006.201.02:22:19.04#ibcon#about to read 4, iclass 37, count 0 2006.201.02:22:19.04#ibcon#read 4, iclass 37, count 0 2006.201.02:22:19.04#ibcon#about to read 5, iclass 37, count 0 2006.201.02:22:19.04#ibcon#read 5, iclass 37, count 0 2006.201.02:22:19.04#ibcon#about to read 6, iclass 37, count 0 2006.201.02:22:19.04#ibcon#read 6, iclass 37, count 0 2006.201.02:22:19.04#ibcon#end of sib2, iclass 37, count 0 2006.201.02:22:19.04#ibcon#*after write, iclass 37, count 0 2006.201.02:22:19.04#ibcon#*before return 0, iclass 37, count 0 2006.201.02:22:19.04#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:19.04#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:19.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:22:19.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:22:19.04$vck44/valo=8,884.99 2006.201.02:22:19.04#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.02:22:19.04#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.02:22:19.04#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:19.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:19.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:19.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:19.04#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:22:19.04#ibcon#first serial, iclass 39, count 0 2006.201.02:22:19.04#ibcon#enter sib2, iclass 39, count 0 2006.201.02:22:19.04#ibcon#flushed, iclass 39, count 0 2006.201.02:22:19.04#ibcon#about to write, iclass 39, count 0 2006.201.02:22:19.04#ibcon#wrote, iclass 39, count 0 2006.201.02:22:19.04#ibcon#about to read 3, iclass 39, count 0 2006.201.02:22:19.06#ibcon#read 3, iclass 39, count 0 2006.201.02:22:19.06#ibcon#about to read 4, iclass 39, count 0 2006.201.02:22:19.06#ibcon#read 4, iclass 39, count 0 2006.201.02:22:19.06#ibcon#about to read 5, iclass 39, count 0 2006.201.02:22:19.06#ibcon#read 5, iclass 39, count 0 2006.201.02:22:19.06#ibcon#about to read 6, iclass 39, count 0 2006.201.02:22:19.06#ibcon#read 6, iclass 39, count 0 2006.201.02:22:19.06#ibcon#end of sib2, iclass 39, count 0 2006.201.02:22:19.06#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:22:19.06#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:22:19.06#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:22:19.06#ibcon#*before write, iclass 39, count 0 2006.201.02:22:19.06#ibcon#enter sib2, iclass 39, count 0 2006.201.02:22:19.06#ibcon#flushed, iclass 39, count 0 2006.201.02:22:19.06#ibcon#about to write, iclass 39, count 0 2006.201.02:22:19.06#ibcon#wrote, iclass 39, count 0 2006.201.02:22:19.06#ibcon#about to read 3, iclass 39, count 0 2006.201.02:22:19.10#ibcon#read 3, iclass 39, count 0 2006.201.02:22:19.10#ibcon#about to read 4, iclass 39, count 0 2006.201.02:22:19.10#ibcon#read 4, iclass 39, count 0 2006.201.02:22:19.10#ibcon#about to read 5, iclass 39, count 0 2006.201.02:22:19.10#ibcon#read 5, iclass 39, count 0 2006.201.02:22:19.10#ibcon#about to read 6, iclass 39, count 0 2006.201.02:22:19.10#ibcon#read 6, iclass 39, count 0 2006.201.02:22:19.10#ibcon#end of sib2, iclass 39, count 0 2006.201.02:22:19.10#ibcon#*after write, iclass 39, count 0 2006.201.02:22:19.10#ibcon#*before return 0, iclass 39, count 0 2006.201.02:22:19.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:19.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:19.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:22:19.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:22:19.10$vck44/va=8,4 2006.201.02:22:19.10#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.02:22:19.10#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.02:22:19.10#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:19.10#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:22:19.16#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:22:19.16#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:22:19.16#ibcon#enter wrdev, iclass 2, count 2 2006.201.02:22:19.16#ibcon#first serial, iclass 2, count 2 2006.201.02:22:19.16#ibcon#enter sib2, iclass 2, count 2 2006.201.02:22:19.16#ibcon#flushed, iclass 2, count 2 2006.201.02:22:19.16#ibcon#about to write, iclass 2, count 2 2006.201.02:22:19.16#ibcon#wrote, iclass 2, count 2 2006.201.02:22:19.16#ibcon#about to read 3, iclass 2, count 2 2006.201.02:22:19.18#ibcon#read 3, iclass 2, count 2 2006.201.02:22:19.18#ibcon#about to read 4, iclass 2, count 2 2006.201.02:22:19.18#ibcon#read 4, iclass 2, count 2 2006.201.02:22:19.18#ibcon#about to read 5, iclass 2, count 2 2006.201.02:22:19.18#ibcon#read 5, iclass 2, count 2 2006.201.02:22:19.18#ibcon#about to read 6, iclass 2, count 2 2006.201.02:22:19.18#ibcon#read 6, iclass 2, count 2 2006.201.02:22:19.18#ibcon#end of sib2, iclass 2, count 2 2006.201.02:22:19.18#ibcon#*mode == 0, iclass 2, count 2 2006.201.02:22:19.18#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.02:22:19.18#ibcon#[25=AT08-04\r\n] 2006.201.02:22:19.18#ibcon#*before write, iclass 2, count 2 2006.201.02:22:19.18#ibcon#enter sib2, iclass 2, count 2 2006.201.02:22:19.18#ibcon#flushed, iclass 2, count 2 2006.201.02:22:19.18#ibcon#about to write, iclass 2, count 2 2006.201.02:22:19.18#ibcon#wrote, iclass 2, count 2 2006.201.02:22:19.18#ibcon#about to read 3, iclass 2, count 2 2006.201.02:22:19.21#ibcon#read 3, iclass 2, count 2 2006.201.02:22:19.21#ibcon#about to read 4, iclass 2, count 2 2006.201.02:22:19.21#ibcon#read 4, iclass 2, count 2 2006.201.02:22:19.21#ibcon#about to read 5, iclass 2, count 2 2006.201.02:22:19.21#ibcon#read 5, iclass 2, count 2 2006.201.02:22:19.21#ibcon#about to read 6, iclass 2, count 2 2006.201.02:22:19.21#ibcon#read 6, iclass 2, count 2 2006.201.02:22:19.21#ibcon#end of sib2, iclass 2, count 2 2006.201.02:22:19.21#ibcon#*after write, iclass 2, count 2 2006.201.02:22:19.21#ibcon#*before return 0, iclass 2, count 2 2006.201.02:22:19.21#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:22:19.21#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:22:19.21#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.02:22:19.21#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:19.21#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:22:19.33#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:22:19.33#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:22:19.33#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:22:19.33#ibcon#first serial, iclass 2, count 0 2006.201.02:22:19.33#ibcon#enter sib2, iclass 2, count 0 2006.201.02:22:19.33#ibcon#flushed, iclass 2, count 0 2006.201.02:22:19.33#ibcon#about to write, iclass 2, count 0 2006.201.02:22:19.33#ibcon#wrote, iclass 2, count 0 2006.201.02:22:19.33#ibcon#about to read 3, iclass 2, count 0 2006.201.02:22:19.35#ibcon#read 3, iclass 2, count 0 2006.201.02:22:19.35#ibcon#about to read 4, iclass 2, count 0 2006.201.02:22:19.35#ibcon#read 4, iclass 2, count 0 2006.201.02:22:19.35#ibcon#about to read 5, iclass 2, count 0 2006.201.02:22:19.35#ibcon#read 5, iclass 2, count 0 2006.201.02:22:19.35#ibcon#about to read 6, iclass 2, count 0 2006.201.02:22:19.35#ibcon#read 6, iclass 2, count 0 2006.201.02:22:19.35#ibcon#end of sib2, iclass 2, count 0 2006.201.02:22:19.35#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:22:19.35#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:22:19.35#ibcon#[25=USB\r\n] 2006.201.02:22:19.35#ibcon#*before write, iclass 2, count 0 2006.201.02:22:19.35#ibcon#enter sib2, iclass 2, count 0 2006.201.02:22:19.35#ibcon#flushed, iclass 2, count 0 2006.201.02:22:19.35#ibcon#about to write, iclass 2, count 0 2006.201.02:22:19.35#ibcon#wrote, iclass 2, count 0 2006.201.02:22:19.35#ibcon#about to read 3, iclass 2, count 0 2006.201.02:22:19.38#ibcon#read 3, iclass 2, count 0 2006.201.02:22:19.38#ibcon#about to read 4, iclass 2, count 0 2006.201.02:22:19.38#ibcon#read 4, iclass 2, count 0 2006.201.02:22:19.38#ibcon#about to read 5, iclass 2, count 0 2006.201.02:22:19.38#ibcon#read 5, iclass 2, count 0 2006.201.02:22:19.38#ibcon#about to read 6, iclass 2, count 0 2006.201.02:22:19.38#ibcon#read 6, iclass 2, count 0 2006.201.02:22:19.38#ibcon#end of sib2, iclass 2, count 0 2006.201.02:22:19.38#ibcon#*after write, iclass 2, count 0 2006.201.02:22:19.38#ibcon#*before return 0, iclass 2, count 0 2006.201.02:22:19.38#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:22:19.38#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:22:19.38#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:22:19.38#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:22:19.38$vck44/vblo=1,629.99 2006.201.02:22:19.38#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.02:22:19.38#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.02:22:19.38#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:19.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:22:19.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:22:19.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:22:19.38#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:22:19.38#ibcon#first serial, iclass 5, count 0 2006.201.02:22:19.38#ibcon#enter sib2, iclass 5, count 0 2006.201.02:22:19.38#ibcon#flushed, iclass 5, count 0 2006.201.02:22:19.38#ibcon#about to write, iclass 5, count 0 2006.201.02:22:19.38#ibcon#wrote, iclass 5, count 0 2006.201.02:22:19.38#ibcon#about to read 3, iclass 5, count 0 2006.201.02:22:19.40#ibcon#read 3, iclass 5, count 0 2006.201.02:22:19.40#ibcon#about to read 4, iclass 5, count 0 2006.201.02:22:19.40#ibcon#read 4, iclass 5, count 0 2006.201.02:22:19.40#ibcon#about to read 5, iclass 5, count 0 2006.201.02:22:19.40#ibcon#read 5, iclass 5, count 0 2006.201.02:22:19.40#ibcon#about to read 6, iclass 5, count 0 2006.201.02:22:19.40#ibcon#read 6, iclass 5, count 0 2006.201.02:22:19.40#ibcon#end of sib2, iclass 5, count 0 2006.201.02:22:19.40#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:22:19.40#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:22:19.40#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:22:19.40#ibcon#*before write, iclass 5, count 0 2006.201.02:22:19.40#ibcon#enter sib2, iclass 5, count 0 2006.201.02:22:19.40#ibcon#flushed, iclass 5, count 0 2006.201.02:22:19.40#ibcon#about to write, iclass 5, count 0 2006.201.02:22:19.40#ibcon#wrote, iclass 5, count 0 2006.201.02:22:19.40#ibcon#about to read 3, iclass 5, count 0 2006.201.02:22:19.45#ibcon#read 3, iclass 5, count 0 2006.201.02:22:19.45#ibcon#about to read 4, iclass 5, count 0 2006.201.02:22:19.45#ibcon#read 4, iclass 5, count 0 2006.201.02:22:19.45#ibcon#about to read 5, iclass 5, count 0 2006.201.02:22:19.45#ibcon#read 5, iclass 5, count 0 2006.201.02:22:19.45#ibcon#about to read 6, iclass 5, count 0 2006.201.02:22:19.45#ibcon#read 6, iclass 5, count 0 2006.201.02:22:19.45#ibcon#end of sib2, iclass 5, count 0 2006.201.02:22:19.45#ibcon#*after write, iclass 5, count 0 2006.201.02:22:19.45#ibcon#*before return 0, iclass 5, count 0 2006.201.02:22:19.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:22:19.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:22:19.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:22:19.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:22:19.45$vck44/vb=1,4 2006.201.02:22:19.45#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.02:22:19.45#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.02:22:19.45#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:19.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:22:19.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:22:19.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:22:19.45#ibcon#enter wrdev, iclass 7, count 2 2006.201.02:22:19.45#ibcon#first serial, iclass 7, count 2 2006.201.02:22:19.45#ibcon#enter sib2, iclass 7, count 2 2006.201.02:22:19.45#ibcon#flushed, iclass 7, count 2 2006.201.02:22:19.45#ibcon#about to write, iclass 7, count 2 2006.201.02:22:19.45#ibcon#wrote, iclass 7, count 2 2006.201.02:22:19.45#ibcon#about to read 3, iclass 7, count 2 2006.201.02:22:19.47#ibcon#read 3, iclass 7, count 2 2006.201.02:22:19.47#ibcon#about to read 4, iclass 7, count 2 2006.201.02:22:19.47#ibcon#read 4, iclass 7, count 2 2006.201.02:22:19.47#ibcon#about to read 5, iclass 7, count 2 2006.201.02:22:19.47#ibcon#read 5, iclass 7, count 2 2006.201.02:22:19.47#ibcon#about to read 6, iclass 7, count 2 2006.201.02:22:19.47#ibcon#read 6, iclass 7, count 2 2006.201.02:22:19.47#ibcon#end of sib2, iclass 7, count 2 2006.201.02:22:19.47#ibcon#*mode == 0, iclass 7, count 2 2006.201.02:22:19.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.02:22:19.47#ibcon#[27=AT01-04\r\n] 2006.201.02:22:19.47#ibcon#*before write, iclass 7, count 2 2006.201.02:22:19.47#ibcon#enter sib2, iclass 7, count 2 2006.201.02:22:19.47#ibcon#flushed, iclass 7, count 2 2006.201.02:22:19.47#ibcon#about to write, iclass 7, count 2 2006.201.02:22:19.47#ibcon#wrote, iclass 7, count 2 2006.201.02:22:19.47#ibcon#about to read 3, iclass 7, count 2 2006.201.02:22:19.50#ibcon#read 3, iclass 7, count 2 2006.201.02:22:19.50#ibcon#about to read 4, iclass 7, count 2 2006.201.02:22:19.50#ibcon#read 4, iclass 7, count 2 2006.201.02:22:19.50#ibcon#about to read 5, iclass 7, count 2 2006.201.02:22:19.50#ibcon#read 5, iclass 7, count 2 2006.201.02:22:19.50#ibcon#about to read 6, iclass 7, count 2 2006.201.02:22:19.50#ibcon#read 6, iclass 7, count 2 2006.201.02:22:19.50#ibcon#end of sib2, iclass 7, count 2 2006.201.02:22:19.50#ibcon#*after write, iclass 7, count 2 2006.201.02:22:19.50#ibcon#*before return 0, iclass 7, count 2 2006.201.02:22:19.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:22:19.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:22:19.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.02:22:19.50#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:19.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:22:19.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:22:19.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:22:19.62#ibcon#enter wrdev, iclass 7, count 0 2006.201.02:22:19.62#ibcon#first serial, iclass 7, count 0 2006.201.02:22:19.62#ibcon#enter sib2, iclass 7, count 0 2006.201.02:22:19.62#ibcon#flushed, iclass 7, count 0 2006.201.02:22:19.62#ibcon#about to write, iclass 7, count 0 2006.201.02:22:19.62#ibcon#wrote, iclass 7, count 0 2006.201.02:22:19.62#ibcon#about to read 3, iclass 7, count 0 2006.201.02:22:19.64#ibcon#read 3, iclass 7, count 0 2006.201.02:22:19.64#ibcon#about to read 4, iclass 7, count 0 2006.201.02:22:19.64#ibcon#read 4, iclass 7, count 0 2006.201.02:22:19.64#ibcon#about to read 5, iclass 7, count 0 2006.201.02:22:19.64#ibcon#read 5, iclass 7, count 0 2006.201.02:22:19.64#ibcon#about to read 6, iclass 7, count 0 2006.201.02:22:19.64#ibcon#read 6, iclass 7, count 0 2006.201.02:22:19.64#ibcon#end of sib2, iclass 7, count 0 2006.201.02:22:19.64#ibcon#*mode == 0, iclass 7, count 0 2006.201.02:22:19.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.02:22:19.64#ibcon#[27=USB\r\n] 2006.201.02:22:19.64#ibcon#*before write, iclass 7, count 0 2006.201.02:22:19.64#ibcon#enter sib2, iclass 7, count 0 2006.201.02:22:19.64#ibcon#flushed, iclass 7, count 0 2006.201.02:22:19.64#ibcon#about to write, iclass 7, count 0 2006.201.02:22:19.64#ibcon#wrote, iclass 7, count 0 2006.201.02:22:19.64#ibcon#about to read 3, iclass 7, count 0 2006.201.02:22:19.67#ibcon#read 3, iclass 7, count 0 2006.201.02:22:19.67#ibcon#about to read 4, iclass 7, count 0 2006.201.02:22:19.67#ibcon#read 4, iclass 7, count 0 2006.201.02:22:19.67#ibcon#about to read 5, iclass 7, count 0 2006.201.02:22:19.67#ibcon#read 5, iclass 7, count 0 2006.201.02:22:19.67#ibcon#about to read 6, iclass 7, count 0 2006.201.02:22:19.67#ibcon#read 6, iclass 7, count 0 2006.201.02:22:19.67#ibcon#end of sib2, iclass 7, count 0 2006.201.02:22:19.67#ibcon#*after write, iclass 7, count 0 2006.201.02:22:19.67#ibcon#*before return 0, iclass 7, count 0 2006.201.02:22:19.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:22:19.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:22:19.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.02:22:19.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.02:22:19.67$vck44/vblo=2,634.99 2006.201.02:22:19.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.02:22:19.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.02:22:19.67#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:19.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:19.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:19.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:19.67#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:22:19.67#ibcon#first serial, iclass 11, count 0 2006.201.02:22:19.67#ibcon#enter sib2, iclass 11, count 0 2006.201.02:22:19.67#ibcon#flushed, iclass 11, count 0 2006.201.02:22:19.67#ibcon#about to write, iclass 11, count 0 2006.201.02:22:19.67#ibcon#wrote, iclass 11, count 0 2006.201.02:22:19.67#ibcon#about to read 3, iclass 11, count 0 2006.201.02:22:19.69#ibcon#read 3, iclass 11, count 0 2006.201.02:22:19.69#ibcon#about to read 4, iclass 11, count 0 2006.201.02:22:19.69#ibcon#read 4, iclass 11, count 0 2006.201.02:22:19.69#ibcon#about to read 5, iclass 11, count 0 2006.201.02:22:19.69#ibcon#read 5, iclass 11, count 0 2006.201.02:22:19.69#ibcon#about to read 6, iclass 11, count 0 2006.201.02:22:19.69#ibcon#read 6, iclass 11, count 0 2006.201.02:22:19.69#ibcon#end of sib2, iclass 11, count 0 2006.201.02:22:19.69#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:22:19.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:22:19.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:22:19.69#ibcon#*before write, iclass 11, count 0 2006.201.02:22:19.69#ibcon#enter sib2, iclass 11, count 0 2006.201.02:22:19.69#ibcon#flushed, iclass 11, count 0 2006.201.02:22:19.69#ibcon#about to write, iclass 11, count 0 2006.201.02:22:19.69#ibcon#wrote, iclass 11, count 0 2006.201.02:22:19.69#ibcon#about to read 3, iclass 11, count 0 2006.201.02:22:19.73#ibcon#read 3, iclass 11, count 0 2006.201.02:22:19.73#ibcon#about to read 4, iclass 11, count 0 2006.201.02:22:19.73#ibcon#read 4, iclass 11, count 0 2006.201.02:22:19.73#ibcon#about to read 5, iclass 11, count 0 2006.201.02:22:19.73#ibcon#read 5, iclass 11, count 0 2006.201.02:22:19.73#ibcon#about to read 6, iclass 11, count 0 2006.201.02:22:19.73#ibcon#read 6, iclass 11, count 0 2006.201.02:22:19.73#ibcon#end of sib2, iclass 11, count 0 2006.201.02:22:19.73#ibcon#*after write, iclass 11, count 0 2006.201.02:22:19.73#ibcon#*before return 0, iclass 11, count 0 2006.201.02:22:19.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:19.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:22:19.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:22:19.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:22:19.73$vck44/vb=2,5 2006.201.02:22:19.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.02:22:19.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.02:22:19.73#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:19.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:19.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:19.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:19.79#ibcon#enter wrdev, iclass 13, count 2 2006.201.02:22:19.79#ibcon#first serial, iclass 13, count 2 2006.201.02:22:19.79#ibcon#enter sib2, iclass 13, count 2 2006.201.02:22:19.79#ibcon#flushed, iclass 13, count 2 2006.201.02:22:19.79#ibcon#about to write, iclass 13, count 2 2006.201.02:22:19.79#ibcon#wrote, iclass 13, count 2 2006.201.02:22:19.79#ibcon#about to read 3, iclass 13, count 2 2006.201.02:22:19.81#ibcon#read 3, iclass 13, count 2 2006.201.02:22:19.81#ibcon#about to read 4, iclass 13, count 2 2006.201.02:22:19.81#ibcon#read 4, iclass 13, count 2 2006.201.02:22:19.81#ibcon#about to read 5, iclass 13, count 2 2006.201.02:22:19.81#ibcon#read 5, iclass 13, count 2 2006.201.02:22:19.81#ibcon#about to read 6, iclass 13, count 2 2006.201.02:22:19.81#ibcon#read 6, iclass 13, count 2 2006.201.02:22:19.81#ibcon#end of sib2, iclass 13, count 2 2006.201.02:22:19.81#ibcon#*mode == 0, iclass 13, count 2 2006.201.02:22:19.81#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.02:22:19.81#ibcon#[27=AT02-05\r\n] 2006.201.02:22:19.81#ibcon#*before write, iclass 13, count 2 2006.201.02:22:19.81#ibcon#enter sib2, iclass 13, count 2 2006.201.02:22:19.81#ibcon#flushed, iclass 13, count 2 2006.201.02:22:19.81#ibcon#about to write, iclass 13, count 2 2006.201.02:22:19.81#ibcon#wrote, iclass 13, count 2 2006.201.02:22:19.81#ibcon#about to read 3, iclass 13, count 2 2006.201.02:22:19.84#ibcon#read 3, iclass 13, count 2 2006.201.02:22:19.84#ibcon#about to read 4, iclass 13, count 2 2006.201.02:22:19.84#ibcon#read 4, iclass 13, count 2 2006.201.02:22:19.84#ibcon#about to read 5, iclass 13, count 2 2006.201.02:22:19.84#ibcon#read 5, iclass 13, count 2 2006.201.02:22:19.84#ibcon#about to read 6, iclass 13, count 2 2006.201.02:22:19.84#ibcon#read 6, iclass 13, count 2 2006.201.02:22:19.84#ibcon#end of sib2, iclass 13, count 2 2006.201.02:22:19.84#ibcon#*after write, iclass 13, count 2 2006.201.02:22:19.84#ibcon#*before return 0, iclass 13, count 2 2006.201.02:22:19.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:19.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:22:19.84#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.02:22:19.84#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:19.84#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:19.96#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:19.96#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:19.96#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:22:19.96#ibcon#first serial, iclass 13, count 0 2006.201.02:22:19.96#ibcon#enter sib2, iclass 13, count 0 2006.201.02:22:19.96#ibcon#flushed, iclass 13, count 0 2006.201.02:22:19.96#ibcon#about to write, iclass 13, count 0 2006.201.02:22:19.96#ibcon#wrote, iclass 13, count 0 2006.201.02:22:19.96#ibcon#about to read 3, iclass 13, count 0 2006.201.02:22:19.98#ibcon#read 3, iclass 13, count 0 2006.201.02:22:19.98#ibcon#about to read 4, iclass 13, count 0 2006.201.02:22:19.98#ibcon#read 4, iclass 13, count 0 2006.201.02:22:19.98#ibcon#about to read 5, iclass 13, count 0 2006.201.02:22:19.98#ibcon#read 5, iclass 13, count 0 2006.201.02:22:19.98#ibcon#about to read 6, iclass 13, count 0 2006.201.02:22:19.98#ibcon#read 6, iclass 13, count 0 2006.201.02:22:19.98#ibcon#end of sib2, iclass 13, count 0 2006.201.02:22:19.98#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:22:19.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:22:19.98#ibcon#[27=USB\r\n] 2006.201.02:22:19.98#ibcon#*before write, iclass 13, count 0 2006.201.02:22:19.98#ibcon#enter sib2, iclass 13, count 0 2006.201.02:22:19.98#ibcon#flushed, iclass 13, count 0 2006.201.02:22:19.98#ibcon#about to write, iclass 13, count 0 2006.201.02:22:19.98#ibcon#wrote, iclass 13, count 0 2006.201.02:22:19.98#ibcon#about to read 3, iclass 13, count 0 2006.201.02:22:20.01#ibcon#read 3, iclass 13, count 0 2006.201.02:22:20.01#ibcon#about to read 4, iclass 13, count 0 2006.201.02:22:20.01#ibcon#read 4, iclass 13, count 0 2006.201.02:22:20.01#ibcon#about to read 5, iclass 13, count 0 2006.201.02:22:20.01#ibcon#read 5, iclass 13, count 0 2006.201.02:22:20.01#ibcon#about to read 6, iclass 13, count 0 2006.201.02:22:20.01#ibcon#read 6, iclass 13, count 0 2006.201.02:22:20.01#ibcon#end of sib2, iclass 13, count 0 2006.201.02:22:20.01#ibcon#*after write, iclass 13, count 0 2006.201.02:22:20.01#ibcon#*before return 0, iclass 13, count 0 2006.201.02:22:20.01#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:20.01#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:22:20.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:22:20.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:22:20.01$vck44/vblo=3,649.99 2006.201.02:22:20.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.02:22:20.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.02:22:20.01#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:20.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:20.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:20.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:20.01#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:22:20.01#ibcon#first serial, iclass 15, count 0 2006.201.02:22:20.01#ibcon#enter sib2, iclass 15, count 0 2006.201.02:22:20.01#ibcon#flushed, iclass 15, count 0 2006.201.02:22:20.01#ibcon#about to write, iclass 15, count 0 2006.201.02:22:20.01#ibcon#wrote, iclass 15, count 0 2006.201.02:22:20.01#ibcon#about to read 3, iclass 15, count 0 2006.201.02:22:20.03#ibcon#read 3, iclass 15, count 0 2006.201.02:22:20.03#ibcon#about to read 4, iclass 15, count 0 2006.201.02:22:20.03#ibcon#read 4, iclass 15, count 0 2006.201.02:22:20.03#ibcon#about to read 5, iclass 15, count 0 2006.201.02:22:20.03#ibcon#read 5, iclass 15, count 0 2006.201.02:22:20.03#ibcon#about to read 6, iclass 15, count 0 2006.201.02:22:20.03#ibcon#read 6, iclass 15, count 0 2006.201.02:22:20.03#ibcon#end of sib2, iclass 15, count 0 2006.201.02:22:20.03#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:22:20.03#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:22:20.03#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:22:20.03#ibcon#*before write, iclass 15, count 0 2006.201.02:22:20.03#ibcon#enter sib2, iclass 15, count 0 2006.201.02:22:20.03#ibcon#flushed, iclass 15, count 0 2006.201.02:22:20.03#ibcon#about to write, iclass 15, count 0 2006.201.02:22:20.03#ibcon#wrote, iclass 15, count 0 2006.201.02:22:20.03#ibcon#about to read 3, iclass 15, count 0 2006.201.02:22:20.08#ibcon#read 3, iclass 15, count 0 2006.201.02:22:20.08#ibcon#about to read 4, iclass 15, count 0 2006.201.02:22:20.08#ibcon#read 4, iclass 15, count 0 2006.201.02:22:20.08#ibcon#about to read 5, iclass 15, count 0 2006.201.02:22:20.08#ibcon#read 5, iclass 15, count 0 2006.201.02:22:20.08#ibcon#about to read 6, iclass 15, count 0 2006.201.02:22:20.08#ibcon#read 6, iclass 15, count 0 2006.201.02:22:20.08#ibcon#end of sib2, iclass 15, count 0 2006.201.02:22:20.08#ibcon#*after write, iclass 15, count 0 2006.201.02:22:20.08#ibcon#*before return 0, iclass 15, count 0 2006.201.02:22:20.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:20.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:22:20.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:22:20.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:22:20.08$vck44/vb=3,4 2006.201.02:22:20.08#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.02:22:20.08#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.02:22:20.08#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:20.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:20.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:20.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:20.13#ibcon#enter wrdev, iclass 17, count 2 2006.201.02:22:20.13#ibcon#first serial, iclass 17, count 2 2006.201.02:22:20.13#ibcon#enter sib2, iclass 17, count 2 2006.201.02:22:20.13#ibcon#flushed, iclass 17, count 2 2006.201.02:22:20.13#ibcon#about to write, iclass 17, count 2 2006.201.02:22:20.13#ibcon#wrote, iclass 17, count 2 2006.201.02:22:20.13#ibcon#about to read 3, iclass 17, count 2 2006.201.02:22:20.15#ibcon#read 3, iclass 17, count 2 2006.201.02:22:20.15#ibcon#about to read 4, iclass 17, count 2 2006.201.02:22:20.15#ibcon#read 4, iclass 17, count 2 2006.201.02:22:20.15#ibcon#about to read 5, iclass 17, count 2 2006.201.02:22:20.15#ibcon#read 5, iclass 17, count 2 2006.201.02:22:20.15#ibcon#about to read 6, iclass 17, count 2 2006.201.02:22:20.15#ibcon#read 6, iclass 17, count 2 2006.201.02:22:20.15#ibcon#end of sib2, iclass 17, count 2 2006.201.02:22:20.15#ibcon#*mode == 0, iclass 17, count 2 2006.201.02:22:20.15#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.02:22:20.15#ibcon#[27=AT03-04\r\n] 2006.201.02:22:20.15#ibcon#*before write, iclass 17, count 2 2006.201.02:22:20.15#ibcon#enter sib2, iclass 17, count 2 2006.201.02:22:20.15#ibcon#flushed, iclass 17, count 2 2006.201.02:22:20.15#ibcon#about to write, iclass 17, count 2 2006.201.02:22:20.15#ibcon#wrote, iclass 17, count 2 2006.201.02:22:20.15#ibcon#about to read 3, iclass 17, count 2 2006.201.02:22:20.18#ibcon#read 3, iclass 17, count 2 2006.201.02:22:20.18#ibcon#about to read 4, iclass 17, count 2 2006.201.02:22:20.18#ibcon#read 4, iclass 17, count 2 2006.201.02:22:20.18#ibcon#about to read 5, iclass 17, count 2 2006.201.02:22:20.18#ibcon#read 5, iclass 17, count 2 2006.201.02:22:20.18#ibcon#about to read 6, iclass 17, count 2 2006.201.02:22:20.18#ibcon#read 6, iclass 17, count 2 2006.201.02:22:20.18#ibcon#end of sib2, iclass 17, count 2 2006.201.02:22:20.18#ibcon#*after write, iclass 17, count 2 2006.201.02:22:20.18#ibcon#*before return 0, iclass 17, count 2 2006.201.02:22:20.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:20.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:22:20.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.02:22:20.18#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:20.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:20.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:20.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:20.30#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:22:20.30#ibcon#first serial, iclass 17, count 0 2006.201.02:22:20.30#ibcon#enter sib2, iclass 17, count 0 2006.201.02:22:20.30#ibcon#flushed, iclass 17, count 0 2006.201.02:22:20.30#ibcon#about to write, iclass 17, count 0 2006.201.02:22:20.30#ibcon#wrote, iclass 17, count 0 2006.201.02:22:20.30#ibcon#about to read 3, iclass 17, count 0 2006.201.02:22:20.32#ibcon#read 3, iclass 17, count 0 2006.201.02:22:20.32#ibcon#about to read 4, iclass 17, count 0 2006.201.02:22:20.32#ibcon#read 4, iclass 17, count 0 2006.201.02:22:20.32#ibcon#about to read 5, iclass 17, count 0 2006.201.02:22:20.32#ibcon#read 5, iclass 17, count 0 2006.201.02:22:20.32#ibcon#about to read 6, iclass 17, count 0 2006.201.02:22:20.32#ibcon#read 6, iclass 17, count 0 2006.201.02:22:20.32#ibcon#end of sib2, iclass 17, count 0 2006.201.02:22:20.32#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:22:20.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:22:20.32#ibcon#[27=USB\r\n] 2006.201.02:22:20.32#ibcon#*before write, iclass 17, count 0 2006.201.02:22:20.32#ibcon#enter sib2, iclass 17, count 0 2006.201.02:22:20.32#ibcon#flushed, iclass 17, count 0 2006.201.02:22:20.32#ibcon#about to write, iclass 17, count 0 2006.201.02:22:20.32#ibcon#wrote, iclass 17, count 0 2006.201.02:22:20.32#ibcon#about to read 3, iclass 17, count 0 2006.201.02:22:20.35#ibcon#read 3, iclass 17, count 0 2006.201.02:22:20.35#ibcon#about to read 4, iclass 17, count 0 2006.201.02:22:20.35#ibcon#read 4, iclass 17, count 0 2006.201.02:22:20.35#ibcon#about to read 5, iclass 17, count 0 2006.201.02:22:20.35#ibcon#read 5, iclass 17, count 0 2006.201.02:22:20.35#ibcon#about to read 6, iclass 17, count 0 2006.201.02:22:20.35#ibcon#read 6, iclass 17, count 0 2006.201.02:22:20.35#ibcon#end of sib2, iclass 17, count 0 2006.201.02:22:20.35#ibcon#*after write, iclass 17, count 0 2006.201.02:22:20.35#ibcon#*before return 0, iclass 17, count 0 2006.201.02:22:20.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:20.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:22:20.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:22:20.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:22:20.35$vck44/vblo=4,679.99 2006.201.02:22:20.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.02:22:20.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.02:22:20.35#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:20.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:20.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:20.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:20.35#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:22:20.35#ibcon#first serial, iclass 19, count 0 2006.201.02:22:20.35#ibcon#enter sib2, iclass 19, count 0 2006.201.02:22:20.35#ibcon#flushed, iclass 19, count 0 2006.201.02:22:20.35#ibcon#about to write, iclass 19, count 0 2006.201.02:22:20.35#ibcon#wrote, iclass 19, count 0 2006.201.02:22:20.35#ibcon#about to read 3, iclass 19, count 0 2006.201.02:22:20.37#ibcon#read 3, iclass 19, count 0 2006.201.02:22:20.37#ibcon#about to read 4, iclass 19, count 0 2006.201.02:22:20.37#ibcon#read 4, iclass 19, count 0 2006.201.02:22:20.37#ibcon#about to read 5, iclass 19, count 0 2006.201.02:22:20.37#ibcon#read 5, iclass 19, count 0 2006.201.02:22:20.37#ibcon#about to read 6, iclass 19, count 0 2006.201.02:22:20.37#ibcon#read 6, iclass 19, count 0 2006.201.02:22:20.37#ibcon#end of sib2, iclass 19, count 0 2006.201.02:22:20.37#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:22:20.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:22:20.37#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:22:20.37#ibcon#*before write, iclass 19, count 0 2006.201.02:22:20.37#ibcon#enter sib2, iclass 19, count 0 2006.201.02:22:20.37#ibcon#flushed, iclass 19, count 0 2006.201.02:22:20.37#ibcon#about to write, iclass 19, count 0 2006.201.02:22:20.37#ibcon#wrote, iclass 19, count 0 2006.201.02:22:20.37#ibcon#about to read 3, iclass 19, count 0 2006.201.02:22:20.41#ibcon#read 3, iclass 19, count 0 2006.201.02:22:20.41#ibcon#about to read 4, iclass 19, count 0 2006.201.02:22:20.41#ibcon#read 4, iclass 19, count 0 2006.201.02:22:20.41#ibcon#about to read 5, iclass 19, count 0 2006.201.02:22:20.41#ibcon#read 5, iclass 19, count 0 2006.201.02:22:20.41#ibcon#about to read 6, iclass 19, count 0 2006.201.02:22:20.41#ibcon#read 6, iclass 19, count 0 2006.201.02:22:20.41#ibcon#end of sib2, iclass 19, count 0 2006.201.02:22:20.41#ibcon#*after write, iclass 19, count 0 2006.201.02:22:20.41#ibcon#*before return 0, iclass 19, count 0 2006.201.02:22:20.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:20.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:22:20.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:22:20.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:22:20.41$vck44/vb=4,5 2006.201.02:22:20.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.02:22:20.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.02:22:20.41#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:20.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:20.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:20.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:20.47#ibcon#enter wrdev, iclass 21, count 2 2006.201.02:22:20.47#ibcon#first serial, iclass 21, count 2 2006.201.02:22:20.47#ibcon#enter sib2, iclass 21, count 2 2006.201.02:22:20.47#ibcon#flushed, iclass 21, count 2 2006.201.02:22:20.47#ibcon#about to write, iclass 21, count 2 2006.201.02:22:20.47#ibcon#wrote, iclass 21, count 2 2006.201.02:22:20.47#ibcon#about to read 3, iclass 21, count 2 2006.201.02:22:20.49#ibcon#read 3, iclass 21, count 2 2006.201.02:22:20.49#ibcon#about to read 4, iclass 21, count 2 2006.201.02:22:20.49#ibcon#read 4, iclass 21, count 2 2006.201.02:22:20.49#ibcon#about to read 5, iclass 21, count 2 2006.201.02:22:20.49#ibcon#read 5, iclass 21, count 2 2006.201.02:22:20.49#ibcon#about to read 6, iclass 21, count 2 2006.201.02:22:20.49#ibcon#read 6, iclass 21, count 2 2006.201.02:22:20.49#ibcon#end of sib2, iclass 21, count 2 2006.201.02:22:20.49#ibcon#*mode == 0, iclass 21, count 2 2006.201.02:22:20.49#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.02:22:20.49#ibcon#[27=AT04-05\r\n] 2006.201.02:22:20.49#ibcon#*before write, iclass 21, count 2 2006.201.02:22:20.49#ibcon#enter sib2, iclass 21, count 2 2006.201.02:22:20.49#ibcon#flushed, iclass 21, count 2 2006.201.02:22:20.49#ibcon#about to write, iclass 21, count 2 2006.201.02:22:20.49#ibcon#wrote, iclass 21, count 2 2006.201.02:22:20.49#ibcon#about to read 3, iclass 21, count 2 2006.201.02:22:20.52#ibcon#read 3, iclass 21, count 2 2006.201.02:22:20.52#ibcon#about to read 4, iclass 21, count 2 2006.201.02:22:20.52#ibcon#read 4, iclass 21, count 2 2006.201.02:22:20.52#ibcon#about to read 5, iclass 21, count 2 2006.201.02:22:20.52#ibcon#read 5, iclass 21, count 2 2006.201.02:22:20.52#ibcon#about to read 6, iclass 21, count 2 2006.201.02:22:20.52#ibcon#read 6, iclass 21, count 2 2006.201.02:22:20.52#ibcon#end of sib2, iclass 21, count 2 2006.201.02:22:20.52#ibcon#*after write, iclass 21, count 2 2006.201.02:22:20.52#ibcon#*before return 0, iclass 21, count 2 2006.201.02:22:20.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:20.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:22:20.52#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.02:22:20.52#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:20.52#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:20.64#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:20.64#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:20.64#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:22:20.64#ibcon#first serial, iclass 21, count 0 2006.201.02:22:20.64#ibcon#enter sib2, iclass 21, count 0 2006.201.02:22:20.64#ibcon#flushed, iclass 21, count 0 2006.201.02:22:20.64#ibcon#about to write, iclass 21, count 0 2006.201.02:22:20.64#ibcon#wrote, iclass 21, count 0 2006.201.02:22:20.64#ibcon#about to read 3, iclass 21, count 0 2006.201.02:22:20.66#ibcon#read 3, iclass 21, count 0 2006.201.02:22:20.66#ibcon#about to read 4, iclass 21, count 0 2006.201.02:22:20.66#ibcon#read 4, iclass 21, count 0 2006.201.02:22:20.66#ibcon#about to read 5, iclass 21, count 0 2006.201.02:22:20.66#ibcon#read 5, iclass 21, count 0 2006.201.02:22:20.66#ibcon#about to read 6, iclass 21, count 0 2006.201.02:22:20.66#ibcon#read 6, iclass 21, count 0 2006.201.02:22:20.66#ibcon#end of sib2, iclass 21, count 0 2006.201.02:22:20.66#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:22:20.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:22:20.66#ibcon#[27=USB\r\n] 2006.201.02:22:20.66#ibcon#*before write, iclass 21, count 0 2006.201.02:22:20.66#ibcon#enter sib2, iclass 21, count 0 2006.201.02:22:20.66#ibcon#flushed, iclass 21, count 0 2006.201.02:22:20.66#ibcon#about to write, iclass 21, count 0 2006.201.02:22:20.66#ibcon#wrote, iclass 21, count 0 2006.201.02:22:20.66#ibcon#about to read 3, iclass 21, count 0 2006.201.02:22:20.69#ibcon#read 3, iclass 21, count 0 2006.201.02:22:20.69#ibcon#about to read 4, iclass 21, count 0 2006.201.02:22:20.69#ibcon#read 4, iclass 21, count 0 2006.201.02:22:20.69#ibcon#about to read 5, iclass 21, count 0 2006.201.02:22:20.69#ibcon#read 5, iclass 21, count 0 2006.201.02:22:20.69#ibcon#about to read 6, iclass 21, count 0 2006.201.02:22:20.69#ibcon#read 6, iclass 21, count 0 2006.201.02:22:20.69#ibcon#end of sib2, iclass 21, count 0 2006.201.02:22:20.69#ibcon#*after write, iclass 21, count 0 2006.201.02:22:20.69#ibcon#*before return 0, iclass 21, count 0 2006.201.02:22:20.69#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:20.69#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:22:20.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:22:20.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:22:20.69$vck44/vblo=5,709.99 2006.201.02:22:20.69#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.02:22:20.69#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.02:22:20.69#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:20.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:20.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:20.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:20.69#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:22:20.69#ibcon#first serial, iclass 23, count 0 2006.201.02:22:20.69#ibcon#enter sib2, iclass 23, count 0 2006.201.02:22:20.69#ibcon#flushed, iclass 23, count 0 2006.201.02:22:20.69#ibcon#about to write, iclass 23, count 0 2006.201.02:22:20.69#ibcon#wrote, iclass 23, count 0 2006.201.02:22:20.69#ibcon#about to read 3, iclass 23, count 0 2006.201.02:22:20.71#ibcon#read 3, iclass 23, count 0 2006.201.02:22:20.71#ibcon#about to read 4, iclass 23, count 0 2006.201.02:22:20.71#ibcon#read 4, iclass 23, count 0 2006.201.02:22:20.71#ibcon#about to read 5, iclass 23, count 0 2006.201.02:22:20.71#ibcon#read 5, iclass 23, count 0 2006.201.02:22:20.71#ibcon#about to read 6, iclass 23, count 0 2006.201.02:22:20.71#ibcon#read 6, iclass 23, count 0 2006.201.02:22:20.71#ibcon#end of sib2, iclass 23, count 0 2006.201.02:22:20.71#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:22:20.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:22:20.71#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:22:20.71#ibcon#*before write, iclass 23, count 0 2006.201.02:22:20.71#ibcon#enter sib2, iclass 23, count 0 2006.201.02:22:20.71#ibcon#flushed, iclass 23, count 0 2006.201.02:22:20.71#ibcon#about to write, iclass 23, count 0 2006.201.02:22:20.71#ibcon#wrote, iclass 23, count 0 2006.201.02:22:20.71#ibcon#about to read 3, iclass 23, count 0 2006.201.02:22:20.75#ibcon#read 3, iclass 23, count 0 2006.201.02:22:20.75#ibcon#about to read 4, iclass 23, count 0 2006.201.02:22:20.75#ibcon#read 4, iclass 23, count 0 2006.201.02:22:20.75#ibcon#about to read 5, iclass 23, count 0 2006.201.02:22:20.75#ibcon#read 5, iclass 23, count 0 2006.201.02:22:20.75#ibcon#about to read 6, iclass 23, count 0 2006.201.02:22:20.75#ibcon#read 6, iclass 23, count 0 2006.201.02:22:20.75#ibcon#end of sib2, iclass 23, count 0 2006.201.02:22:20.75#ibcon#*after write, iclass 23, count 0 2006.201.02:22:20.75#ibcon#*before return 0, iclass 23, count 0 2006.201.02:22:20.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:20.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:22:20.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:22:20.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:22:20.75$vck44/vb=5,4 2006.201.02:22:20.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.02:22:20.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.02:22:20.75#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:20.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:20.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:20.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:20.81#ibcon#enter wrdev, iclass 25, count 2 2006.201.02:22:20.81#ibcon#first serial, iclass 25, count 2 2006.201.02:22:20.81#ibcon#enter sib2, iclass 25, count 2 2006.201.02:22:20.81#ibcon#flushed, iclass 25, count 2 2006.201.02:22:20.81#ibcon#about to write, iclass 25, count 2 2006.201.02:22:20.81#ibcon#wrote, iclass 25, count 2 2006.201.02:22:20.81#ibcon#about to read 3, iclass 25, count 2 2006.201.02:22:20.83#ibcon#read 3, iclass 25, count 2 2006.201.02:22:20.83#ibcon#about to read 4, iclass 25, count 2 2006.201.02:22:20.83#ibcon#read 4, iclass 25, count 2 2006.201.02:22:20.83#ibcon#about to read 5, iclass 25, count 2 2006.201.02:22:20.83#ibcon#read 5, iclass 25, count 2 2006.201.02:22:20.83#ibcon#about to read 6, iclass 25, count 2 2006.201.02:22:20.83#ibcon#read 6, iclass 25, count 2 2006.201.02:22:20.83#ibcon#end of sib2, iclass 25, count 2 2006.201.02:22:20.83#ibcon#*mode == 0, iclass 25, count 2 2006.201.02:22:20.83#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.02:22:20.83#ibcon#[27=AT05-04\r\n] 2006.201.02:22:20.83#ibcon#*before write, iclass 25, count 2 2006.201.02:22:20.83#ibcon#enter sib2, iclass 25, count 2 2006.201.02:22:20.83#ibcon#flushed, iclass 25, count 2 2006.201.02:22:20.83#ibcon#about to write, iclass 25, count 2 2006.201.02:22:20.83#ibcon#wrote, iclass 25, count 2 2006.201.02:22:20.83#ibcon#about to read 3, iclass 25, count 2 2006.201.02:22:20.86#ibcon#read 3, iclass 25, count 2 2006.201.02:22:20.86#ibcon#about to read 4, iclass 25, count 2 2006.201.02:22:20.86#ibcon#read 4, iclass 25, count 2 2006.201.02:22:20.86#ibcon#about to read 5, iclass 25, count 2 2006.201.02:22:20.86#ibcon#read 5, iclass 25, count 2 2006.201.02:22:20.86#ibcon#about to read 6, iclass 25, count 2 2006.201.02:22:20.86#ibcon#read 6, iclass 25, count 2 2006.201.02:22:20.86#ibcon#end of sib2, iclass 25, count 2 2006.201.02:22:20.86#ibcon#*after write, iclass 25, count 2 2006.201.02:22:20.86#ibcon#*before return 0, iclass 25, count 2 2006.201.02:22:20.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:20.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:22:20.86#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.02:22:20.86#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:20.86#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:20.98#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:20.98#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:20.98#ibcon#enter wrdev, iclass 25, count 0 2006.201.02:22:20.98#ibcon#first serial, iclass 25, count 0 2006.201.02:22:20.98#ibcon#enter sib2, iclass 25, count 0 2006.201.02:22:20.98#ibcon#flushed, iclass 25, count 0 2006.201.02:22:20.98#ibcon#about to write, iclass 25, count 0 2006.201.02:22:20.98#ibcon#wrote, iclass 25, count 0 2006.201.02:22:20.98#ibcon#about to read 3, iclass 25, count 0 2006.201.02:22:21.00#ibcon#read 3, iclass 25, count 0 2006.201.02:22:21.00#ibcon#about to read 4, iclass 25, count 0 2006.201.02:22:21.00#ibcon#read 4, iclass 25, count 0 2006.201.02:22:21.00#ibcon#about to read 5, iclass 25, count 0 2006.201.02:22:21.00#ibcon#read 5, iclass 25, count 0 2006.201.02:22:21.00#ibcon#about to read 6, iclass 25, count 0 2006.201.02:22:21.00#ibcon#read 6, iclass 25, count 0 2006.201.02:22:21.00#ibcon#end of sib2, iclass 25, count 0 2006.201.02:22:21.00#ibcon#*mode == 0, iclass 25, count 0 2006.201.02:22:21.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.02:22:21.00#ibcon#[27=USB\r\n] 2006.201.02:22:21.00#ibcon#*before write, iclass 25, count 0 2006.201.02:22:21.00#ibcon#enter sib2, iclass 25, count 0 2006.201.02:22:21.00#ibcon#flushed, iclass 25, count 0 2006.201.02:22:21.00#ibcon#about to write, iclass 25, count 0 2006.201.02:22:21.00#ibcon#wrote, iclass 25, count 0 2006.201.02:22:21.00#ibcon#about to read 3, iclass 25, count 0 2006.201.02:22:21.03#ibcon#read 3, iclass 25, count 0 2006.201.02:22:21.03#ibcon#about to read 4, iclass 25, count 0 2006.201.02:22:21.03#ibcon#read 4, iclass 25, count 0 2006.201.02:22:21.03#ibcon#about to read 5, iclass 25, count 0 2006.201.02:22:21.03#ibcon#read 5, iclass 25, count 0 2006.201.02:22:21.03#ibcon#about to read 6, iclass 25, count 0 2006.201.02:22:21.03#ibcon#read 6, iclass 25, count 0 2006.201.02:22:21.03#ibcon#end of sib2, iclass 25, count 0 2006.201.02:22:21.03#ibcon#*after write, iclass 25, count 0 2006.201.02:22:21.03#ibcon#*before return 0, iclass 25, count 0 2006.201.02:22:21.03#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:21.03#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:22:21.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.02:22:21.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.02:22:21.03$vck44/vblo=6,719.99 2006.201.02:22:21.03#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.02:22:21.03#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.02:22:21.03#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:21.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:21.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:21.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:21.03#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:22:21.03#ibcon#first serial, iclass 27, count 0 2006.201.02:22:21.03#ibcon#enter sib2, iclass 27, count 0 2006.201.02:22:21.03#ibcon#flushed, iclass 27, count 0 2006.201.02:22:21.03#ibcon#about to write, iclass 27, count 0 2006.201.02:22:21.03#ibcon#wrote, iclass 27, count 0 2006.201.02:22:21.03#ibcon#about to read 3, iclass 27, count 0 2006.201.02:22:21.05#ibcon#read 3, iclass 27, count 0 2006.201.02:22:21.05#ibcon#about to read 4, iclass 27, count 0 2006.201.02:22:21.05#ibcon#read 4, iclass 27, count 0 2006.201.02:22:21.05#ibcon#about to read 5, iclass 27, count 0 2006.201.02:22:21.05#ibcon#read 5, iclass 27, count 0 2006.201.02:22:21.05#ibcon#about to read 6, iclass 27, count 0 2006.201.02:22:21.05#ibcon#read 6, iclass 27, count 0 2006.201.02:22:21.05#ibcon#end of sib2, iclass 27, count 0 2006.201.02:22:21.05#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:22:21.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:22:21.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:22:21.05#ibcon#*before write, iclass 27, count 0 2006.201.02:22:21.05#ibcon#enter sib2, iclass 27, count 0 2006.201.02:22:21.05#ibcon#flushed, iclass 27, count 0 2006.201.02:22:21.05#ibcon#about to write, iclass 27, count 0 2006.201.02:22:21.05#ibcon#wrote, iclass 27, count 0 2006.201.02:22:21.05#ibcon#about to read 3, iclass 27, count 0 2006.201.02:22:21.09#ibcon#read 3, iclass 27, count 0 2006.201.02:22:21.09#ibcon#about to read 4, iclass 27, count 0 2006.201.02:22:21.09#ibcon#read 4, iclass 27, count 0 2006.201.02:22:21.09#ibcon#about to read 5, iclass 27, count 0 2006.201.02:22:21.09#ibcon#read 5, iclass 27, count 0 2006.201.02:22:21.09#ibcon#about to read 6, iclass 27, count 0 2006.201.02:22:21.09#ibcon#read 6, iclass 27, count 0 2006.201.02:22:21.09#ibcon#end of sib2, iclass 27, count 0 2006.201.02:22:21.09#ibcon#*after write, iclass 27, count 0 2006.201.02:22:21.09#ibcon#*before return 0, iclass 27, count 0 2006.201.02:22:21.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:21.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:22:21.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:22:21.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:22:21.09$vck44/vb=6,4 2006.201.02:22:21.09#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.02:22:21.09#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.02:22:21.09#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:21.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:21.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:21.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:21.15#ibcon#enter wrdev, iclass 29, count 2 2006.201.02:22:21.15#ibcon#first serial, iclass 29, count 2 2006.201.02:22:21.15#ibcon#enter sib2, iclass 29, count 2 2006.201.02:22:21.15#ibcon#flushed, iclass 29, count 2 2006.201.02:22:21.15#ibcon#about to write, iclass 29, count 2 2006.201.02:22:21.15#ibcon#wrote, iclass 29, count 2 2006.201.02:22:21.15#ibcon#about to read 3, iclass 29, count 2 2006.201.02:22:21.17#ibcon#read 3, iclass 29, count 2 2006.201.02:22:21.17#ibcon#about to read 4, iclass 29, count 2 2006.201.02:22:21.17#ibcon#read 4, iclass 29, count 2 2006.201.02:22:21.17#ibcon#about to read 5, iclass 29, count 2 2006.201.02:22:21.17#ibcon#read 5, iclass 29, count 2 2006.201.02:22:21.17#ibcon#about to read 6, iclass 29, count 2 2006.201.02:22:21.17#ibcon#read 6, iclass 29, count 2 2006.201.02:22:21.17#ibcon#end of sib2, iclass 29, count 2 2006.201.02:22:21.17#ibcon#*mode == 0, iclass 29, count 2 2006.201.02:22:21.17#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.02:22:21.17#ibcon#[27=AT06-04\r\n] 2006.201.02:22:21.17#ibcon#*before write, iclass 29, count 2 2006.201.02:22:21.17#ibcon#enter sib2, iclass 29, count 2 2006.201.02:22:21.17#ibcon#flushed, iclass 29, count 2 2006.201.02:22:21.17#ibcon#about to write, iclass 29, count 2 2006.201.02:22:21.17#ibcon#wrote, iclass 29, count 2 2006.201.02:22:21.17#ibcon#about to read 3, iclass 29, count 2 2006.201.02:22:21.20#ibcon#read 3, iclass 29, count 2 2006.201.02:22:21.20#ibcon#about to read 4, iclass 29, count 2 2006.201.02:22:21.20#ibcon#read 4, iclass 29, count 2 2006.201.02:22:21.20#ibcon#about to read 5, iclass 29, count 2 2006.201.02:22:21.20#ibcon#read 5, iclass 29, count 2 2006.201.02:22:21.20#ibcon#about to read 6, iclass 29, count 2 2006.201.02:22:21.20#ibcon#read 6, iclass 29, count 2 2006.201.02:22:21.20#ibcon#end of sib2, iclass 29, count 2 2006.201.02:22:21.20#ibcon#*after write, iclass 29, count 2 2006.201.02:22:21.20#ibcon#*before return 0, iclass 29, count 2 2006.201.02:22:21.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:21.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:22:21.20#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.02:22:21.20#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:21.20#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:21.32#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:21.32#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:21.32#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:22:21.32#ibcon#first serial, iclass 29, count 0 2006.201.02:22:21.32#ibcon#enter sib2, iclass 29, count 0 2006.201.02:22:21.32#ibcon#flushed, iclass 29, count 0 2006.201.02:22:21.32#ibcon#about to write, iclass 29, count 0 2006.201.02:22:21.32#ibcon#wrote, iclass 29, count 0 2006.201.02:22:21.32#ibcon#about to read 3, iclass 29, count 0 2006.201.02:22:21.34#ibcon#read 3, iclass 29, count 0 2006.201.02:22:21.34#ibcon#about to read 4, iclass 29, count 0 2006.201.02:22:21.34#ibcon#read 4, iclass 29, count 0 2006.201.02:22:21.34#ibcon#about to read 5, iclass 29, count 0 2006.201.02:22:21.34#ibcon#read 5, iclass 29, count 0 2006.201.02:22:21.34#ibcon#about to read 6, iclass 29, count 0 2006.201.02:22:21.34#ibcon#read 6, iclass 29, count 0 2006.201.02:22:21.34#ibcon#end of sib2, iclass 29, count 0 2006.201.02:22:21.34#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:22:21.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:22:21.34#ibcon#[27=USB\r\n] 2006.201.02:22:21.34#ibcon#*before write, iclass 29, count 0 2006.201.02:22:21.34#ibcon#enter sib2, iclass 29, count 0 2006.201.02:22:21.34#ibcon#flushed, iclass 29, count 0 2006.201.02:22:21.34#ibcon#about to write, iclass 29, count 0 2006.201.02:22:21.34#ibcon#wrote, iclass 29, count 0 2006.201.02:22:21.34#ibcon#about to read 3, iclass 29, count 0 2006.201.02:22:21.37#ibcon#read 3, iclass 29, count 0 2006.201.02:22:21.37#ibcon#about to read 4, iclass 29, count 0 2006.201.02:22:21.37#ibcon#read 4, iclass 29, count 0 2006.201.02:22:21.37#ibcon#about to read 5, iclass 29, count 0 2006.201.02:22:21.37#ibcon#read 5, iclass 29, count 0 2006.201.02:22:21.37#ibcon#about to read 6, iclass 29, count 0 2006.201.02:22:21.37#ibcon#read 6, iclass 29, count 0 2006.201.02:22:21.37#ibcon#end of sib2, iclass 29, count 0 2006.201.02:22:21.37#ibcon#*after write, iclass 29, count 0 2006.201.02:22:21.37#ibcon#*before return 0, iclass 29, count 0 2006.201.02:22:21.37#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:21.37#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:22:21.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:22:21.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:22:21.37$vck44/vblo=7,734.99 2006.201.02:22:21.37#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.02:22:21.37#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.02:22:21.37#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:21.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:21.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:21.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:21.37#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:22:21.37#ibcon#first serial, iclass 31, count 0 2006.201.02:22:21.37#ibcon#enter sib2, iclass 31, count 0 2006.201.02:22:21.37#ibcon#flushed, iclass 31, count 0 2006.201.02:22:21.37#ibcon#about to write, iclass 31, count 0 2006.201.02:22:21.37#ibcon#wrote, iclass 31, count 0 2006.201.02:22:21.37#ibcon#about to read 3, iclass 31, count 0 2006.201.02:22:21.39#ibcon#read 3, iclass 31, count 0 2006.201.02:22:21.39#ibcon#about to read 4, iclass 31, count 0 2006.201.02:22:21.39#ibcon#read 4, iclass 31, count 0 2006.201.02:22:21.39#ibcon#about to read 5, iclass 31, count 0 2006.201.02:22:21.39#ibcon#read 5, iclass 31, count 0 2006.201.02:22:21.39#ibcon#about to read 6, iclass 31, count 0 2006.201.02:22:21.39#ibcon#read 6, iclass 31, count 0 2006.201.02:22:21.39#ibcon#end of sib2, iclass 31, count 0 2006.201.02:22:21.39#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:22:21.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:22:21.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:22:21.39#ibcon#*before write, iclass 31, count 0 2006.201.02:22:21.39#ibcon#enter sib2, iclass 31, count 0 2006.201.02:22:21.39#ibcon#flushed, iclass 31, count 0 2006.201.02:22:21.39#ibcon#about to write, iclass 31, count 0 2006.201.02:22:21.39#ibcon#wrote, iclass 31, count 0 2006.201.02:22:21.39#ibcon#about to read 3, iclass 31, count 0 2006.201.02:22:21.43#ibcon#read 3, iclass 31, count 0 2006.201.02:22:21.43#ibcon#about to read 4, iclass 31, count 0 2006.201.02:22:21.43#ibcon#read 4, iclass 31, count 0 2006.201.02:22:21.43#ibcon#about to read 5, iclass 31, count 0 2006.201.02:22:21.43#ibcon#read 5, iclass 31, count 0 2006.201.02:22:21.43#ibcon#about to read 6, iclass 31, count 0 2006.201.02:22:21.43#ibcon#read 6, iclass 31, count 0 2006.201.02:22:21.43#ibcon#end of sib2, iclass 31, count 0 2006.201.02:22:21.43#ibcon#*after write, iclass 31, count 0 2006.201.02:22:21.43#ibcon#*before return 0, iclass 31, count 0 2006.201.02:22:21.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:21.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:22:21.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:22:21.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:22:21.43$vck44/vb=7,4 2006.201.02:22:21.43#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.02:22:21.43#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.02:22:21.43#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:21.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:21.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:21.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:21.49#ibcon#enter wrdev, iclass 33, count 2 2006.201.02:22:21.49#ibcon#first serial, iclass 33, count 2 2006.201.02:22:21.49#ibcon#enter sib2, iclass 33, count 2 2006.201.02:22:21.49#ibcon#flushed, iclass 33, count 2 2006.201.02:22:21.49#ibcon#about to write, iclass 33, count 2 2006.201.02:22:21.49#ibcon#wrote, iclass 33, count 2 2006.201.02:22:21.49#ibcon#about to read 3, iclass 33, count 2 2006.201.02:22:21.51#ibcon#read 3, iclass 33, count 2 2006.201.02:22:21.51#ibcon#about to read 4, iclass 33, count 2 2006.201.02:22:21.51#ibcon#read 4, iclass 33, count 2 2006.201.02:22:21.51#ibcon#about to read 5, iclass 33, count 2 2006.201.02:22:21.51#ibcon#read 5, iclass 33, count 2 2006.201.02:22:21.51#ibcon#about to read 6, iclass 33, count 2 2006.201.02:22:21.51#ibcon#read 6, iclass 33, count 2 2006.201.02:22:21.51#ibcon#end of sib2, iclass 33, count 2 2006.201.02:22:21.51#ibcon#*mode == 0, iclass 33, count 2 2006.201.02:22:21.51#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.02:22:21.51#ibcon#[27=AT07-04\r\n] 2006.201.02:22:21.51#ibcon#*before write, iclass 33, count 2 2006.201.02:22:21.51#ibcon#enter sib2, iclass 33, count 2 2006.201.02:22:21.51#ibcon#flushed, iclass 33, count 2 2006.201.02:22:21.51#ibcon#about to write, iclass 33, count 2 2006.201.02:22:21.51#ibcon#wrote, iclass 33, count 2 2006.201.02:22:21.51#ibcon#about to read 3, iclass 33, count 2 2006.201.02:22:21.54#ibcon#read 3, iclass 33, count 2 2006.201.02:22:21.54#ibcon#about to read 4, iclass 33, count 2 2006.201.02:22:21.54#ibcon#read 4, iclass 33, count 2 2006.201.02:22:21.54#ibcon#about to read 5, iclass 33, count 2 2006.201.02:22:21.54#ibcon#read 5, iclass 33, count 2 2006.201.02:22:21.54#ibcon#about to read 6, iclass 33, count 2 2006.201.02:22:21.54#ibcon#read 6, iclass 33, count 2 2006.201.02:22:21.54#ibcon#end of sib2, iclass 33, count 2 2006.201.02:22:21.54#ibcon#*after write, iclass 33, count 2 2006.201.02:22:21.54#ibcon#*before return 0, iclass 33, count 2 2006.201.02:22:21.54#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:21.54#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:22:21.54#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.02:22:21.54#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:21.54#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:21.66#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:21.66#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:21.66#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:22:21.66#ibcon#first serial, iclass 33, count 0 2006.201.02:22:21.66#ibcon#enter sib2, iclass 33, count 0 2006.201.02:22:21.66#ibcon#flushed, iclass 33, count 0 2006.201.02:22:21.66#ibcon#about to write, iclass 33, count 0 2006.201.02:22:21.66#ibcon#wrote, iclass 33, count 0 2006.201.02:22:21.66#ibcon#about to read 3, iclass 33, count 0 2006.201.02:22:21.68#ibcon#read 3, iclass 33, count 0 2006.201.02:22:21.68#ibcon#about to read 4, iclass 33, count 0 2006.201.02:22:21.68#ibcon#read 4, iclass 33, count 0 2006.201.02:22:21.68#ibcon#about to read 5, iclass 33, count 0 2006.201.02:22:21.68#ibcon#read 5, iclass 33, count 0 2006.201.02:22:21.68#ibcon#about to read 6, iclass 33, count 0 2006.201.02:22:21.68#ibcon#read 6, iclass 33, count 0 2006.201.02:22:21.68#ibcon#end of sib2, iclass 33, count 0 2006.201.02:22:21.68#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:22:21.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:22:21.68#ibcon#[27=USB\r\n] 2006.201.02:22:21.68#ibcon#*before write, iclass 33, count 0 2006.201.02:22:21.68#ibcon#enter sib2, iclass 33, count 0 2006.201.02:22:21.68#ibcon#flushed, iclass 33, count 0 2006.201.02:22:21.68#ibcon#about to write, iclass 33, count 0 2006.201.02:22:21.68#ibcon#wrote, iclass 33, count 0 2006.201.02:22:21.68#ibcon#about to read 3, iclass 33, count 0 2006.201.02:22:21.71#ibcon#read 3, iclass 33, count 0 2006.201.02:22:21.71#ibcon#about to read 4, iclass 33, count 0 2006.201.02:22:21.71#ibcon#read 4, iclass 33, count 0 2006.201.02:22:21.71#ibcon#about to read 5, iclass 33, count 0 2006.201.02:22:21.71#ibcon#read 5, iclass 33, count 0 2006.201.02:22:21.71#ibcon#about to read 6, iclass 33, count 0 2006.201.02:22:21.71#ibcon#read 6, iclass 33, count 0 2006.201.02:22:21.71#ibcon#end of sib2, iclass 33, count 0 2006.201.02:22:21.71#ibcon#*after write, iclass 33, count 0 2006.201.02:22:21.71#ibcon#*before return 0, iclass 33, count 0 2006.201.02:22:21.71#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:21.71#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:22:21.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:22:21.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:22:21.71$vck44/vblo=8,744.99 2006.201.02:22:21.71#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.02:22:21.71#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.02:22:21.71#ibcon#ireg 17 cls_cnt 0 2006.201.02:22:21.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:21.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:21.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:21.71#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:22:21.71#ibcon#first serial, iclass 35, count 0 2006.201.02:22:21.71#ibcon#enter sib2, iclass 35, count 0 2006.201.02:22:21.71#ibcon#flushed, iclass 35, count 0 2006.201.02:22:21.71#ibcon#about to write, iclass 35, count 0 2006.201.02:22:21.71#ibcon#wrote, iclass 35, count 0 2006.201.02:22:21.71#ibcon#about to read 3, iclass 35, count 0 2006.201.02:22:21.73#ibcon#read 3, iclass 35, count 0 2006.201.02:22:21.73#ibcon#about to read 4, iclass 35, count 0 2006.201.02:22:21.73#ibcon#read 4, iclass 35, count 0 2006.201.02:22:21.73#ibcon#about to read 5, iclass 35, count 0 2006.201.02:22:21.73#ibcon#read 5, iclass 35, count 0 2006.201.02:22:21.73#ibcon#about to read 6, iclass 35, count 0 2006.201.02:22:21.73#ibcon#read 6, iclass 35, count 0 2006.201.02:22:21.73#ibcon#end of sib2, iclass 35, count 0 2006.201.02:22:21.73#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:22:21.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:22:21.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:22:21.73#ibcon#*before write, iclass 35, count 0 2006.201.02:22:21.73#ibcon#enter sib2, iclass 35, count 0 2006.201.02:22:21.73#ibcon#flushed, iclass 35, count 0 2006.201.02:22:21.73#ibcon#about to write, iclass 35, count 0 2006.201.02:22:21.73#ibcon#wrote, iclass 35, count 0 2006.201.02:22:21.73#ibcon#about to read 3, iclass 35, count 0 2006.201.02:22:21.78#ibcon#read 3, iclass 35, count 0 2006.201.02:22:21.78#ibcon#about to read 4, iclass 35, count 0 2006.201.02:22:21.78#ibcon#read 4, iclass 35, count 0 2006.201.02:22:21.78#ibcon#about to read 5, iclass 35, count 0 2006.201.02:22:21.78#ibcon#read 5, iclass 35, count 0 2006.201.02:22:21.78#ibcon#about to read 6, iclass 35, count 0 2006.201.02:22:21.78#ibcon#read 6, iclass 35, count 0 2006.201.02:22:21.78#ibcon#end of sib2, iclass 35, count 0 2006.201.02:22:21.78#ibcon#*after write, iclass 35, count 0 2006.201.02:22:21.78#ibcon#*before return 0, iclass 35, count 0 2006.201.02:22:21.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:21.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:22:21.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:22:21.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:22:21.78$vck44/vb=8,4 2006.201.02:22:21.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.02:22:21.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.02:22:21.78#ibcon#ireg 11 cls_cnt 2 2006.201.02:22:21.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:21.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:21.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:21.83#ibcon#enter wrdev, iclass 37, count 2 2006.201.02:22:21.83#ibcon#first serial, iclass 37, count 2 2006.201.02:22:21.83#ibcon#enter sib2, iclass 37, count 2 2006.201.02:22:21.83#ibcon#flushed, iclass 37, count 2 2006.201.02:22:21.83#ibcon#about to write, iclass 37, count 2 2006.201.02:22:21.83#ibcon#wrote, iclass 37, count 2 2006.201.02:22:21.83#ibcon#about to read 3, iclass 37, count 2 2006.201.02:22:21.85#ibcon#read 3, iclass 37, count 2 2006.201.02:22:21.85#ibcon#about to read 4, iclass 37, count 2 2006.201.02:22:21.85#ibcon#read 4, iclass 37, count 2 2006.201.02:22:21.85#ibcon#about to read 5, iclass 37, count 2 2006.201.02:22:21.85#ibcon#read 5, iclass 37, count 2 2006.201.02:22:21.85#ibcon#about to read 6, iclass 37, count 2 2006.201.02:22:21.85#ibcon#read 6, iclass 37, count 2 2006.201.02:22:21.85#ibcon#end of sib2, iclass 37, count 2 2006.201.02:22:21.85#ibcon#*mode == 0, iclass 37, count 2 2006.201.02:22:21.85#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.02:22:21.85#ibcon#[27=AT08-04\r\n] 2006.201.02:22:21.85#ibcon#*before write, iclass 37, count 2 2006.201.02:22:21.85#ibcon#enter sib2, iclass 37, count 2 2006.201.02:22:21.85#ibcon#flushed, iclass 37, count 2 2006.201.02:22:21.85#ibcon#about to write, iclass 37, count 2 2006.201.02:22:21.85#ibcon#wrote, iclass 37, count 2 2006.201.02:22:21.85#ibcon#about to read 3, iclass 37, count 2 2006.201.02:22:21.88#ibcon#read 3, iclass 37, count 2 2006.201.02:22:21.88#ibcon#about to read 4, iclass 37, count 2 2006.201.02:22:21.88#ibcon#read 4, iclass 37, count 2 2006.201.02:22:21.88#ibcon#about to read 5, iclass 37, count 2 2006.201.02:22:21.88#ibcon#read 5, iclass 37, count 2 2006.201.02:22:21.88#ibcon#about to read 6, iclass 37, count 2 2006.201.02:22:21.88#ibcon#read 6, iclass 37, count 2 2006.201.02:22:21.88#ibcon#end of sib2, iclass 37, count 2 2006.201.02:22:21.88#ibcon#*after write, iclass 37, count 2 2006.201.02:22:21.88#ibcon#*before return 0, iclass 37, count 2 2006.201.02:22:21.88#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:21.88#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:22:21.88#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.02:22:21.88#ibcon#ireg 7 cls_cnt 0 2006.201.02:22:21.88#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:22.00#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:22.00#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:22.00#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:22:22.00#ibcon#first serial, iclass 37, count 0 2006.201.02:22:22.00#ibcon#enter sib2, iclass 37, count 0 2006.201.02:22:22.00#ibcon#flushed, iclass 37, count 0 2006.201.02:22:22.00#ibcon#about to write, iclass 37, count 0 2006.201.02:22:22.00#ibcon#wrote, iclass 37, count 0 2006.201.02:22:22.00#ibcon#about to read 3, iclass 37, count 0 2006.201.02:22:22.02#ibcon#read 3, iclass 37, count 0 2006.201.02:22:22.02#ibcon#about to read 4, iclass 37, count 0 2006.201.02:22:22.02#ibcon#read 4, iclass 37, count 0 2006.201.02:22:22.02#ibcon#about to read 5, iclass 37, count 0 2006.201.02:22:22.02#ibcon#read 5, iclass 37, count 0 2006.201.02:22:22.02#ibcon#about to read 6, iclass 37, count 0 2006.201.02:22:22.02#ibcon#read 6, iclass 37, count 0 2006.201.02:22:22.02#ibcon#end of sib2, iclass 37, count 0 2006.201.02:22:22.02#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:22:22.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:22:22.02#ibcon#[27=USB\r\n] 2006.201.02:22:22.02#ibcon#*before write, iclass 37, count 0 2006.201.02:22:22.02#ibcon#enter sib2, iclass 37, count 0 2006.201.02:22:22.02#ibcon#flushed, iclass 37, count 0 2006.201.02:22:22.02#ibcon#about to write, iclass 37, count 0 2006.201.02:22:22.02#ibcon#wrote, iclass 37, count 0 2006.201.02:22:22.02#ibcon#about to read 3, iclass 37, count 0 2006.201.02:22:22.05#ibcon#read 3, iclass 37, count 0 2006.201.02:22:22.05#ibcon#about to read 4, iclass 37, count 0 2006.201.02:22:22.05#ibcon#read 4, iclass 37, count 0 2006.201.02:22:22.05#ibcon#about to read 5, iclass 37, count 0 2006.201.02:22:22.05#ibcon#read 5, iclass 37, count 0 2006.201.02:22:22.05#ibcon#about to read 6, iclass 37, count 0 2006.201.02:22:22.05#ibcon#read 6, iclass 37, count 0 2006.201.02:22:22.05#ibcon#end of sib2, iclass 37, count 0 2006.201.02:22:22.05#ibcon#*after write, iclass 37, count 0 2006.201.02:22:22.05#ibcon#*before return 0, iclass 37, count 0 2006.201.02:22:22.05#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:22.05#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:22:22.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:22:22.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:22:22.05$vck44/vabw=wide 2006.201.02:22:22.05#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.02:22:22.05#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.02:22:22.05#ibcon#ireg 8 cls_cnt 0 2006.201.02:22:22.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:22.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:22.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:22.05#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:22:22.05#ibcon#first serial, iclass 39, count 0 2006.201.02:22:22.05#ibcon#enter sib2, iclass 39, count 0 2006.201.02:22:22.05#ibcon#flushed, iclass 39, count 0 2006.201.02:22:22.05#ibcon#about to write, iclass 39, count 0 2006.201.02:22:22.05#ibcon#wrote, iclass 39, count 0 2006.201.02:22:22.05#ibcon#about to read 3, iclass 39, count 0 2006.201.02:22:22.07#ibcon#read 3, iclass 39, count 0 2006.201.02:22:22.07#ibcon#about to read 4, iclass 39, count 0 2006.201.02:22:22.07#ibcon#read 4, iclass 39, count 0 2006.201.02:22:22.07#ibcon#about to read 5, iclass 39, count 0 2006.201.02:22:22.07#ibcon#read 5, iclass 39, count 0 2006.201.02:22:22.07#ibcon#about to read 6, iclass 39, count 0 2006.201.02:22:22.07#ibcon#read 6, iclass 39, count 0 2006.201.02:22:22.07#ibcon#end of sib2, iclass 39, count 0 2006.201.02:22:22.07#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:22:22.07#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:22:22.07#ibcon#[25=BW32\r\n] 2006.201.02:22:22.07#ibcon#*before write, iclass 39, count 0 2006.201.02:22:22.07#ibcon#enter sib2, iclass 39, count 0 2006.201.02:22:22.07#ibcon#flushed, iclass 39, count 0 2006.201.02:22:22.07#ibcon#about to write, iclass 39, count 0 2006.201.02:22:22.07#ibcon#wrote, iclass 39, count 0 2006.201.02:22:22.07#ibcon#about to read 3, iclass 39, count 0 2006.201.02:22:22.10#ibcon#read 3, iclass 39, count 0 2006.201.02:22:22.10#ibcon#about to read 4, iclass 39, count 0 2006.201.02:22:22.10#ibcon#read 4, iclass 39, count 0 2006.201.02:22:22.10#ibcon#about to read 5, iclass 39, count 0 2006.201.02:22:22.10#ibcon#read 5, iclass 39, count 0 2006.201.02:22:22.10#ibcon#about to read 6, iclass 39, count 0 2006.201.02:22:22.10#ibcon#read 6, iclass 39, count 0 2006.201.02:22:22.10#ibcon#end of sib2, iclass 39, count 0 2006.201.02:22:22.10#ibcon#*after write, iclass 39, count 0 2006.201.02:22:22.10#ibcon#*before return 0, iclass 39, count 0 2006.201.02:22:22.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:22.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:22:22.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:22:22.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:22:22.10$vck44/vbbw=wide 2006.201.02:22:22.10#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.02:22:22.10#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.02:22:22.10#ibcon#ireg 8 cls_cnt 0 2006.201.02:22:22.10#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:22:22.17#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:22:22.17#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:22:22.17#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:22:22.17#ibcon#first serial, iclass 2, count 0 2006.201.02:22:22.17#ibcon#enter sib2, iclass 2, count 0 2006.201.02:22:22.17#ibcon#flushed, iclass 2, count 0 2006.201.02:22:22.17#ibcon#about to write, iclass 2, count 0 2006.201.02:22:22.17#ibcon#wrote, iclass 2, count 0 2006.201.02:22:22.17#ibcon#about to read 3, iclass 2, count 0 2006.201.02:22:22.19#ibcon#read 3, iclass 2, count 0 2006.201.02:22:22.19#ibcon#about to read 4, iclass 2, count 0 2006.201.02:22:22.19#ibcon#read 4, iclass 2, count 0 2006.201.02:22:22.19#ibcon#about to read 5, iclass 2, count 0 2006.201.02:22:22.19#ibcon#read 5, iclass 2, count 0 2006.201.02:22:22.19#ibcon#about to read 6, iclass 2, count 0 2006.201.02:22:22.19#ibcon#read 6, iclass 2, count 0 2006.201.02:22:22.19#ibcon#end of sib2, iclass 2, count 0 2006.201.02:22:22.19#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:22:22.19#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:22:22.19#ibcon#[27=BW32\r\n] 2006.201.02:22:22.19#ibcon#*before write, iclass 2, count 0 2006.201.02:22:22.19#ibcon#enter sib2, iclass 2, count 0 2006.201.02:22:22.19#ibcon#flushed, iclass 2, count 0 2006.201.02:22:22.19#ibcon#about to write, iclass 2, count 0 2006.201.02:22:22.19#ibcon#wrote, iclass 2, count 0 2006.201.02:22:22.19#ibcon#about to read 3, iclass 2, count 0 2006.201.02:22:22.22#ibcon#read 3, iclass 2, count 0 2006.201.02:22:22.22#ibcon#about to read 4, iclass 2, count 0 2006.201.02:22:22.22#ibcon#read 4, iclass 2, count 0 2006.201.02:22:22.22#ibcon#about to read 5, iclass 2, count 0 2006.201.02:22:22.22#ibcon#read 5, iclass 2, count 0 2006.201.02:22:22.22#ibcon#about to read 6, iclass 2, count 0 2006.201.02:22:22.22#ibcon#read 6, iclass 2, count 0 2006.201.02:22:22.22#ibcon#end of sib2, iclass 2, count 0 2006.201.02:22:22.22#ibcon#*after write, iclass 2, count 0 2006.201.02:22:22.22#ibcon#*before return 0, iclass 2, count 0 2006.201.02:22:22.22#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:22:22.22#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:22:22.22#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:22:22.22#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:22:22.22$setupk4/ifdk4 2006.201.02:22:22.22$ifdk4/lo= 2006.201.02:22:22.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:22:22.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:22:22.22$ifdk4/patch= 2006.201.02:22:22.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:22:22.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:22:22.22$setupk4/!*+20s 2006.201.02:22:26.76#abcon#<5=/04 2.5 4.8 22.93 911005.0\r\n> 2006.201.02:22:26.78#abcon#{5=INTERFACE CLEAR} 2006.201.02:22:26.84#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:22:36.70$setupk4/"tpicd 2006.201.02:22:36.70$setupk4/echo=off 2006.201.02:22:36.70$setupk4/xlog=off 2006.201.02:22:36.70:!2006.201.02:29:36 2006.201.02:22:48.13#trakl#Source acquired 2006.201.02:22:50.13#flagr#flagr/antenna,acquired 2006.201.02:29:36.00:preob 2006.201.02:29:36.14/onsource/TRACKING 2006.201.02:29:36.14:!2006.201.02:29:46 2006.201.02:29:46.00:"tape 2006.201.02:29:46.00:"st=record 2006.201.02:29:46.00:data_valid=on 2006.201.02:29:46.00:midob 2006.201.02:29:47.14/onsource/TRACKING 2006.201.02:29:47.14/wx/22.98,1004.8,92 2006.201.02:29:47.27/cable/+6.4672E-03 2006.201.02:29:48.36/va/01,08,usb,yes,28,30 2006.201.02:29:48.36/va/02,07,usb,yes,31,31 2006.201.02:29:48.36/va/03,08,usb,yes,27,29 2006.201.02:29:48.36/va/04,07,usb,yes,31,33 2006.201.02:29:48.36/va/05,04,usb,yes,28,28 2006.201.02:29:48.36/va/06,05,usb,yes,28,28 2006.201.02:29:48.36/va/07,05,usb,yes,27,28 2006.201.02:29:48.36/va/08,04,usb,yes,27,32 2006.201.02:29:48.59/valo/01,524.99,yes,locked 2006.201.02:29:48.59/valo/02,534.99,yes,locked 2006.201.02:29:48.59/valo/03,564.99,yes,locked 2006.201.02:29:48.59/valo/04,624.99,yes,locked 2006.201.02:29:48.59/valo/05,734.99,yes,locked 2006.201.02:29:48.59/valo/06,814.99,yes,locked 2006.201.02:29:48.59/valo/07,864.99,yes,locked 2006.201.02:29:48.59/valo/08,884.99,yes,locked 2006.201.02:29:49.68/vb/01,04,usb,yes,29,26 2006.201.02:29:49.68/vb/02,05,usb,yes,27,27 2006.201.02:29:49.68/vb/03,04,usb,yes,28,31 2006.201.02:29:49.68/vb/04,05,usb,yes,28,27 2006.201.02:29:49.68/vb/05,04,usb,yes,25,27 2006.201.02:29:49.68/vb/06,04,usb,yes,29,25 2006.201.02:29:49.68/vb/07,04,usb,yes,29,29 2006.201.02:29:49.68/vb/08,04,usb,yes,26,30 2006.201.02:29:49.91/vblo/01,629.99,yes,locked 2006.201.02:29:49.91/vblo/02,634.99,yes,locked 2006.201.02:29:49.91/vblo/03,649.99,yes,locked 2006.201.02:29:49.91/vblo/04,679.99,yes,locked 2006.201.02:29:49.91/vblo/05,709.99,yes,locked 2006.201.02:29:49.91/vblo/06,719.99,yes,locked 2006.201.02:29:49.91/vblo/07,734.99,yes,locked 2006.201.02:29:49.91/vblo/08,744.99,yes,locked 2006.201.02:29:50.06/vabw/8 2006.201.02:29:50.21/vbbw/8 2006.201.02:29:50.30/xfe/off,on,16.2 2006.201.02:29:50.70/ifatt/23,28,28,28 2006.201.02:29:51.04/fmout-gps/S +4.43E-07 2006.201.02:29:51.11:!2006.201.02:30:46 2006.201.02:30:46.00:data_valid=off 2006.201.02:30:46.00:"et 2006.201.02:30:46.00:!+3s 2006.201.02:30:49.02:"tape 2006.201.02:30:49.02:postob 2006.201.02:30:49.19/cable/+6.4665E-03 2006.201.02:30:49.19/wx/22.98,1004.8,91 2006.201.02:30:49.27/fmout-gps/S +4.43E-07 2006.201.02:30:49.27:scan_name=201-0233,jd0607,190 2006.201.02:30:49.28:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.201.02:30:50.14#flagr#flagr/antenna,new-source 2006.201.02:30:50.14:checkk5 2006.201.02:30:50.55/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:30:51.00/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:30:51.38/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:30:51.98/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:30:52.42/chk_obsdata//k5ts1/T2010229??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.02:30:52.85/chk_obsdata//k5ts2/T2010229??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.02:30:53.28/chk_obsdata//k5ts3/T2010229??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.02:30:53.68/chk_obsdata//k5ts4/T2010229??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.02:30:54.39/k5log//k5ts1_log_newline 2006.201.02:30:55.14/k5log//k5ts2_log_newline 2006.201.02:30:56.15/k5log//k5ts3_log_newline 2006.201.02:30:57.13/k5log//k5ts4_log_newline 2006.201.02:30:57.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:30:57.16:setupk4=1 2006.201.02:30:57.16$setupk4/echo=on 2006.201.02:30:57.16$setupk4/pcalon 2006.201.02:30:57.16$pcalon/"no phase cal control is implemented here 2006.201.02:30:57.16$setupk4/"tpicd=stop 2006.201.02:30:57.16$setupk4/"rec=synch_on 2006.201.02:30:57.16$setupk4/"rec_mode=128 2006.201.02:30:57.16$setupk4/!* 2006.201.02:30:57.16$setupk4/recpk4 2006.201.02:30:57.16$recpk4/recpatch= 2006.201.02:30:57.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:30:57.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:30:57.16$setupk4/vck44 2006.201.02:30:57.16$vck44/valo=1,524.99 2006.201.02:30:57.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.02:30:57.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.02:30:57.16#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:57.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:30:57.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:30:57.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:30:57.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.02:30:57.17#ibcon#first serial, iclass 34, count 0 2006.201.02:30:57.17#ibcon#enter sib2, iclass 34, count 0 2006.201.02:30:57.17#ibcon#flushed, iclass 34, count 0 2006.201.02:30:57.17#ibcon#about to write, iclass 34, count 0 2006.201.02:30:57.17#ibcon#wrote, iclass 34, count 0 2006.201.02:30:57.17#ibcon#about to read 3, iclass 34, count 0 2006.201.02:30:57.23#ibcon#read 3, iclass 34, count 0 2006.201.02:30:57.23#ibcon#about to read 4, iclass 34, count 0 2006.201.02:30:57.23#ibcon#read 4, iclass 34, count 0 2006.201.02:30:57.23#ibcon#about to read 5, iclass 34, count 0 2006.201.02:30:57.23#ibcon#read 5, iclass 34, count 0 2006.201.02:30:57.23#ibcon#about to read 6, iclass 34, count 0 2006.201.02:30:57.23#ibcon#read 6, iclass 34, count 0 2006.201.02:30:57.23#ibcon#end of sib2, iclass 34, count 0 2006.201.02:30:57.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.02:30:57.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.02:30:57.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:30:57.23#ibcon#*before write, iclass 34, count 0 2006.201.02:30:57.23#ibcon#enter sib2, iclass 34, count 0 2006.201.02:30:57.23#ibcon#flushed, iclass 34, count 0 2006.201.02:30:57.23#ibcon#about to write, iclass 34, count 0 2006.201.02:30:57.23#ibcon#wrote, iclass 34, count 0 2006.201.02:30:57.23#ibcon#about to read 3, iclass 34, count 0 2006.201.02:30:57.28#ibcon#read 3, iclass 34, count 0 2006.201.02:30:57.28#ibcon#about to read 4, iclass 34, count 0 2006.201.02:30:57.28#ibcon#read 4, iclass 34, count 0 2006.201.02:30:57.28#ibcon#about to read 5, iclass 34, count 0 2006.201.02:30:57.28#ibcon#read 5, iclass 34, count 0 2006.201.02:30:57.28#ibcon#about to read 6, iclass 34, count 0 2006.201.02:30:57.28#ibcon#read 6, iclass 34, count 0 2006.201.02:30:57.28#ibcon#end of sib2, iclass 34, count 0 2006.201.02:30:57.28#ibcon#*after write, iclass 34, count 0 2006.201.02:30:57.28#ibcon#*before return 0, iclass 34, count 0 2006.201.02:30:57.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:30:57.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:30:57.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.02:30:57.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.02:30:57.28$vck44/va=1,8 2006.201.02:30:57.28#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.02:30:57.28#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.02:30:57.28#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:57.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:30:57.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:30:57.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:30:57.28#ibcon#enter wrdev, iclass 36, count 2 2006.201.02:30:57.28#ibcon#first serial, iclass 36, count 2 2006.201.02:30:57.28#ibcon#enter sib2, iclass 36, count 2 2006.201.02:30:57.28#ibcon#flushed, iclass 36, count 2 2006.201.02:30:57.28#ibcon#about to write, iclass 36, count 2 2006.201.02:30:57.28#ibcon#wrote, iclass 36, count 2 2006.201.02:30:57.28#ibcon#about to read 3, iclass 36, count 2 2006.201.02:30:57.30#ibcon#read 3, iclass 36, count 2 2006.201.02:30:57.30#ibcon#about to read 4, iclass 36, count 2 2006.201.02:30:57.30#ibcon#read 4, iclass 36, count 2 2006.201.02:30:57.30#ibcon#about to read 5, iclass 36, count 2 2006.201.02:30:57.30#ibcon#read 5, iclass 36, count 2 2006.201.02:30:57.30#ibcon#about to read 6, iclass 36, count 2 2006.201.02:30:57.30#ibcon#read 6, iclass 36, count 2 2006.201.02:30:57.30#ibcon#end of sib2, iclass 36, count 2 2006.201.02:30:57.30#ibcon#*mode == 0, iclass 36, count 2 2006.201.02:30:57.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.02:30:57.30#ibcon#[25=AT01-08\r\n] 2006.201.02:30:57.30#ibcon#*before write, iclass 36, count 2 2006.201.02:30:57.30#ibcon#enter sib2, iclass 36, count 2 2006.201.02:30:57.30#ibcon#flushed, iclass 36, count 2 2006.201.02:30:57.30#ibcon#about to write, iclass 36, count 2 2006.201.02:30:57.30#ibcon#wrote, iclass 36, count 2 2006.201.02:30:57.30#ibcon#about to read 3, iclass 36, count 2 2006.201.02:30:57.33#ibcon#read 3, iclass 36, count 2 2006.201.02:30:57.33#ibcon#about to read 4, iclass 36, count 2 2006.201.02:30:57.33#ibcon#read 4, iclass 36, count 2 2006.201.02:30:57.33#ibcon#about to read 5, iclass 36, count 2 2006.201.02:30:57.33#ibcon#read 5, iclass 36, count 2 2006.201.02:30:57.33#ibcon#about to read 6, iclass 36, count 2 2006.201.02:30:57.33#ibcon#read 6, iclass 36, count 2 2006.201.02:30:57.33#ibcon#end of sib2, iclass 36, count 2 2006.201.02:30:57.33#ibcon#*after write, iclass 36, count 2 2006.201.02:30:57.33#ibcon#*before return 0, iclass 36, count 2 2006.201.02:30:57.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:30:57.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:30:57.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.02:30:57.33#ibcon#ireg 7 cls_cnt 0 2006.201.02:30:57.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:30:57.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:30:57.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:30:57.45#ibcon#enter wrdev, iclass 36, count 0 2006.201.02:30:57.45#ibcon#first serial, iclass 36, count 0 2006.201.02:30:57.45#ibcon#enter sib2, iclass 36, count 0 2006.201.02:30:57.45#ibcon#flushed, iclass 36, count 0 2006.201.02:30:57.45#ibcon#about to write, iclass 36, count 0 2006.201.02:30:57.45#ibcon#wrote, iclass 36, count 0 2006.201.02:30:57.45#ibcon#about to read 3, iclass 36, count 0 2006.201.02:30:57.47#ibcon#read 3, iclass 36, count 0 2006.201.02:30:57.47#ibcon#about to read 4, iclass 36, count 0 2006.201.02:30:57.47#ibcon#read 4, iclass 36, count 0 2006.201.02:30:57.47#ibcon#about to read 5, iclass 36, count 0 2006.201.02:30:57.47#ibcon#read 5, iclass 36, count 0 2006.201.02:30:57.47#ibcon#about to read 6, iclass 36, count 0 2006.201.02:30:57.47#ibcon#read 6, iclass 36, count 0 2006.201.02:30:57.47#ibcon#end of sib2, iclass 36, count 0 2006.201.02:30:57.47#ibcon#*mode == 0, iclass 36, count 0 2006.201.02:30:57.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.02:30:57.47#ibcon#[25=USB\r\n] 2006.201.02:30:57.47#ibcon#*before write, iclass 36, count 0 2006.201.02:30:57.47#ibcon#enter sib2, iclass 36, count 0 2006.201.02:30:57.47#ibcon#flushed, iclass 36, count 0 2006.201.02:30:57.47#ibcon#about to write, iclass 36, count 0 2006.201.02:30:57.47#ibcon#wrote, iclass 36, count 0 2006.201.02:30:57.47#ibcon#about to read 3, iclass 36, count 0 2006.201.02:30:57.50#ibcon#read 3, iclass 36, count 0 2006.201.02:30:57.50#ibcon#about to read 4, iclass 36, count 0 2006.201.02:30:57.50#ibcon#read 4, iclass 36, count 0 2006.201.02:30:57.50#ibcon#about to read 5, iclass 36, count 0 2006.201.02:30:57.50#ibcon#read 5, iclass 36, count 0 2006.201.02:30:57.50#ibcon#about to read 6, iclass 36, count 0 2006.201.02:30:57.50#ibcon#read 6, iclass 36, count 0 2006.201.02:30:57.50#ibcon#end of sib2, iclass 36, count 0 2006.201.02:30:57.50#ibcon#*after write, iclass 36, count 0 2006.201.02:30:57.50#ibcon#*before return 0, iclass 36, count 0 2006.201.02:30:57.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:30:57.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:30:57.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.02:30:57.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.02:30:57.50$vck44/valo=2,534.99 2006.201.02:30:57.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.02:30:57.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.02:30:57.50#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:57.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:30:57.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:30:57.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:30:57.50#ibcon#enter wrdev, iclass 38, count 0 2006.201.02:30:57.50#ibcon#first serial, iclass 38, count 0 2006.201.02:30:57.50#ibcon#enter sib2, iclass 38, count 0 2006.201.02:30:57.50#ibcon#flushed, iclass 38, count 0 2006.201.02:30:57.50#ibcon#about to write, iclass 38, count 0 2006.201.02:30:57.50#ibcon#wrote, iclass 38, count 0 2006.201.02:30:57.50#ibcon#about to read 3, iclass 38, count 0 2006.201.02:30:57.52#ibcon#read 3, iclass 38, count 0 2006.201.02:30:57.52#ibcon#about to read 4, iclass 38, count 0 2006.201.02:30:57.52#ibcon#read 4, iclass 38, count 0 2006.201.02:30:57.52#ibcon#about to read 5, iclass 38, count 0 2006.201.02:30:57.52#ibcon#read 5, iclass 38, count 0 2006.201.02:30:57.52#ibcon#about to read 6, iclass 38, count 0 2006.201.02:30:57.52#ibcon#read 6, iclass 38, count 0 2006.201.02:30:57.52#ibcon#end of sib2, iclass 38, count 0 2006.201.02:30:57.52#ibcon#*mode == 0, iclass 38, count 0 2006.201.02:30:57.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.02:30:57.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:30:57.52#ibcon#*before write, iclass 38, count 0 2006.201.02:30:57.52#ibcon#enter sib2, iclass 38, count 0 2006.201.02:30:57.52#ibcon#flushed, iclass 38, count 0 2006.201.02:30:57.52#ibcon#about to write, iclass 38, count 0 2006.201.02:30:57.52#ibcon#wrote, iclass 38, count 0 2006.201.02:30:57.52#ibcon#about to read 3, iclass 38, count 0 2006.201.02:30:57.57#ibcon#read 3, iclass 38, count 0 2006.201.02:30:57.57#ibcon#about to read 4, iclass 38, count 0 2006.201.02:30:57.57#ibcon#read 4, iclass 38, count 0 2006.201.02:30:57.57#ibcon#about to read 5, iclass 38, count 0 2006.201.02:30:57.57#ibcon#read 5, iclass 38, count 0 2006.201.02:30:57.57#ibcon#about to read 6, iclass 38, count 0 2006.201.02:30:57.57#ibcon#read 6, iclass 38, count 0 2006.201.02:30:57.57#ibcon#end of sib2, iclass 38, count 0 2006.201.02:30:57.57#ibcon#*after write, iclass 38, count 0 2006.201.02:30:57.57#ibcon#*before return 0, iclass 38, count 0 2006.201.02:30:57.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:30:57.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:30:57.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.02:30:57.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.02:30:57.57$vck44/va=2,7 2006.201.02:30:57.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.02:30:57.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.02:30:57.57#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:57.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:30:57.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:30:57.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:30:57.62#ibcon#enter wrdev, iclass 40, count 2 2006.201.02:30:57.62#ibcon#first serial, iclass 40, count 2 2006.201.02:30:57.62#ibcon#enter sib2, iclass 40, count 2 2006.201.02:30:57.62#ibcon#flushed, iclass 40, count 2 2006.201.02:30:57.62#ibcon#about to write, iclass 40, count 2 2006.201.02:30:57.62#ibcon#wrote, iclass 40, count 2 2006.201.02:30:57.62#ibcon#about to read 3, iclass 40, count 2 2006.201.02:30:57.64#ibcon#read 3, iclass 40, count 2 2006.201.02:30:57.64#ibcon#about to read 4, iclass 40, count 2 2006.201.02:30:57.64#ibcon#read 4, iclass 40, count 2 2006.201.02:30:57.64#ibcon#about to read 5, iclass 40, count 2 2006.201.02:30:57.64#ibcon#read 5, iclass 40, count 2 2006.201.02:30:57.64#ibcon#about to read 6, iclass 40, count 2 2006.201.02:30:57.64#ibcon#read 6, iclass 40, count 2 2006.201.02:30:57.64#ibcon#end of sib2, iclass 40, count 2 2006.201.02:30:57.64#ibcon#*mode == 0, iclass 40, count 2 2006.201.02:30:57.64#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.02:30:57.64#ibcon#[25=AT02-07\r\n] 2006.201.02:30:57.64#ibcon#*before write, iclass 40, count 2 2006.201.02:30:57.64#ibcon#enter sib2, iclass 40, count 2 2006.201.02:30:57.64#ibcon#flushed, iclass 40, count 2 2006.201.02:30:57.64#ibcon#about to write, iclass 40, count 2 2006.201.02:30:57.64#ibcon#wrote, iclass 40, count 2 2006.201.02:30:57.64#ibcon#about to read 3, iclass 40, count 2 2006.201.02:30:57.67#ibcon#read 3, iclass 40, count 2 2006.201.02:30:57.67#ibcon#about to read 4, iclass 40, count 2 2006.201.02:30:57.67#ibcon#read 4, iclass 40, count 2 2006.201.02:30:57.67#ibcon#about to read 5, iclass 40, count 2 2006.201.02:30:57.67#ibcon#read 5, iclass 40, count 2 2006.201.02:30:57.67#ibcon#about to read 6, iclass 40, count 2 2006.201.02:30:57.67#ibcon#read 6, iclass 40, count 2 2006.201.02:30:57.67#ibcon#end of sib2, iclass 40, count 2 2006.201.02:30:57.67#ibcon#*after write, iclass 40, count 2 2006.201.02:30:57.67#ibcon#*before return 0, iclass 40, count 2 2006.201.02:30:57.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:30:57.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:30:57.67#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.02:30:57.67#ibcon#ireg 7 cls_cnt 0 2006.201.02:30:57.67#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:30:57.79#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:30:57.79#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:30:57.79#ibcon#enter wrdev, iclass 40, count 0 2006.201.02:30:57.79#ibcon#first serial, iclass 40, count 0 2006.201.02:30:57.79#ibcon#enter sib2, iclass 40, count 0 2006.201.02:30:57.79#ibcon#flushed, iclass 40, count 0 2006.201.02:30:57.79#ibcon#about to write, iclass 40, count 0 2006.201.02:30:57.79#ibcon#wrote, iclass 40, count 0 2006.201.02:30:57.79#ibcon#about to read 3, iclass 40, count 0 2006.201.02:30:57.81#ibcon#read 3, iclass 40, count 0 2006.201.02:30:57.81#ibcon#about to read 4, iclass 40, count 0 2006.201.02:30:57.81#ibcon#read 4, iclass 40, count 0 2006.201.02:30:57.81#ibcon#about to read 5, iclass 40, count 0 2006.201.02:30:57.81#ibcon#read 5, iclass 40, count 0 2006.201.02:30:57.81#ibcon#about to read 6, iclass 40, count 0 2006.201.02:30:57.81#ibcon#read 6, iclass 40, count 0 2006.201.02:30:57.81#ibcon#end of sib2, iclass 40, count 0 2006.201.02:30:57.81#ibcon#*mode == 0, iclass 40, count 0 2006.201.02:30:57.81#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.02:30:57.81#ibcon#[25=USB\r\n] 2006.201.02:30:57.81#ibcon#*before write, iclass 40, count 0 2006.201.02:30:57.81#ibcon#enter sib2, iclass 40, count 0 2006.201.02:30:57.81#ibcon#flushed, iclass 40, count 0 2006.201.02:30:57.81#ibcon#about to write, iclass 40, count 0 2006.201.02:30:57.81#ibcon#wrote, iclass 40, count 0 2006.201.02:30:57.81#ibcon#about to read 3, iclass 40, count 0 2006.201.02:30:57.84#ibcon#read 3, iclass 40, count 0 2006.201.02:30:57.84#ibcon#about to read 4, iclass 40, count 0 2006.201.02:30:57.84#ibcon#read 4, iclass 40, count 0 2006.201.02:30:57.84#ibcon#about to read 5, iclass 40, count 0 2006.201.02:30:57.84#ibcon#read 5, iclass 40, count 0 2006.201.02:30:57.84#ibcon#about to read 6, iclass 40, count 0 2006.201.02:30:57.84#ibcon#read 6, iclass 40, count 0 2006.201.02:30:57.84#ibcon#end of sib2, iclass 40, count 0 2006.201.02:30:57.84#ibcon#*after write, iclass 40, count 0 2006.201.02:30:57.84#ibcon#*before return 0, iclass 40, count 0 2006.201.02:30:57.84#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:30:57.84#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:30:57.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.02:30:57.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.02:30:57.84$vck44/valo=3,564.99 2006.201.02:30:57.84#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.02:30:57.84#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.02:30:57.84#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:57.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:30:57.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:30:57.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:30:57.84#ibcon#enter wrdev, iclass 4, count 0 2006.201.02:30:57.84#ibcon#first serial, iclass 4, count 0 2006.201.02:30:57.84#ibcon#enter sib2, iclass 4, count 0 2006.201.02:30:57.84#ibcon#flushed, iclass 4, count 0 2006.201.02:30:57.84#ibcon#about to write, iclass 4, count 0 2006.201.02:30:57.84#ibcon#wrote, iclass 4, count 0 2006.201.02:30:57.84#ibcon#about to read 3, iclass 4, count 0 2006.201.02:30:57.86#ibcon#read 3, iclass 4, count 0 2006.201.02:30:57.86#ibcon#about to read 4, iclass 4, count 0 2006.201.02:30:57.86#ibcon#read 4, iclass 4, count 0 2006.201.02:30:57.86#ibcon#about to read 5, iclass 4, count 0 2006.201.02:30:57.86#ibcon#read 5, iclass 4, count 0 2006.201.02:30:57.86#ibcon#about to read 6, iclass 4, count 0 2006.201.02:30:57.86#ibcon#read 6, iclass 4, count 0 2006.201.02:30:57.86#ibcon#end of sib2, iclass 4, count 0 2006.201.02:30:57.86#ibcon#*mode == 0, iclass 4, count 0 2006.201.02:30:57.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.02:30:57.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:30:57.86#ibcon#*before write, iclass 4, count 0 2006.201.02:30:57.86#ibcon#enter sib2, iclass 4, count 0 2006.201.02:30:57.86#ibcon#flushed, iclass 4, count 0 2006.201.02:30:57.86#ibcon#about to write, iclass 4, count 0 2006.201.02:30:57.86#ibcon#wrote, iclass 4, count 0 2006.201.02:30:57.86#ibcon#about to read 3, iclass 4, count 0 2006.201.02:30:57.91#ibcon#read 3, iclass 4, count 0 2006.201.02:30:57.91#ibcon#about to read 4, iclass 4, count 0 2006.201.02:30:57.91#ibcon#read 4, iclass 4, count 0 2006.201.02:30:57.91#ibcon#about to read 5, iclass 4, count 0 2006.201.02:30:57.91#ibcon#read 5, iclass 4, count 0 2006.201.02:30:57.91#ibcon#about to read 6, iclass 4, count 0 2006.201.02:30:57.91#ibcon#read 6, iclass 4, count 0 2006.201.02:30:57.91#ibcon#end of sib2, iclass 4, count 0 2006.201.02:30:57.91#ibcon#*after write, iclass 4, count 0 2006.201.02:30:57.91#ibcon#*before return 0, iclass 4, count 0 2006.201.02:30:57.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:30:57.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:30:57.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.02:30:57.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.02:30:57.91$vck44/va=3,8 2006.201.02:30:57.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.02:30:57.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.02:30:57.91#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:57.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:30:57.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:30:57.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:30:57.96#ibcon#enter wrdev, iclass 6, count 2 2006.201.02:30:57.96#ibcon#first serial, iclass 6, count 2 2006.201.02:30:57.96#ibcon#enter sib2, iclass 6, count 2 2006.201.02:30:57.96#ibcon#flushed, iclass 6, count 2 2006.201.02:30:57.96#ibcon#about to write, iclass 6, count 2 2006.201.02:30:57.96#ibcon#wrote, iclass 6, count 2 2006.201.02:30:57.96#ibcon#about to read 3, iclass 6, count 2 2006.201.02:30:57.98#ibcon#read 3, iclass 6, count 2 2006.201.02:30:57.98#ibcon#about to read 4, iclass 6, count 2 2006.201.02:30:57.98#ibcon#read 4, iclass 6, count 2 2006.201.02:30:57.98#ibcon#about to read 5, iclass 6, count 2 2006.201.02:30:57.98#ibcon#read 5, iclass 6, count 2 2006.201.02:30:57.98#ibcon#about to read 6, iclass 6, count 2 2006.201.02:30:57.98#ibcon#read 6, iclass 6, count 2 2006.201.02:30:57.98#ibcon#end of sib2, iclass 6, count 2 2006.201.02:30:57.98#ibcon#*mode == 0, iclass 6, count 2 2006.201.02:30:57.98#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.02:30:57.98#ibcon#[25=AT03-08\r\n] 2006.201.02:30:57.98#ibcon#*before write, iclass 6, count 2 2006.201.02:30:57.98#ibcon#enter sib2, iclass 6, count 2 2006.201.02:30:57.98#ibcon#flushed, iclass 6, count 2 2006.201.02:30:57.98#ibcon#about to write, iclass 6, count 2 2006.201.02:30:57.98#ibcon#wrote, iclass 6, count 2 2006.201.02:30:57.98#ibcon#about to read 3, iclass 6, count 2 2006.201.02:30:58.01#ibcon#read 3, iclass 6, count 2 2006.201.02:30:58.01#ibcon#about to read 4, iclass 6, count 2 2006.201.02:30:58.01#ibcon#read 4, iclass 6, count 2 2006.201.02:30:58.01#ibcon#about to read 5, iclass 6, count 2 2006.201.02:30:58.01#ibcon#read 5, iclass 6, count 2 2006.201.02:30:58.01#ibcon#about to read 6, iclass 6, count 2 2006.201.02:30:58.01#ibcon#read 6, iclass 6, count 2 2006.201.02:30:58.01#ibcon#end of sib2, iclass 6, count 2 2006.201.02:30:58.01#ibcon#*after write, iclass 6, count 2 2006.201.02:30:58.01#ibcon#*before return 0, iclass 6, count 2 2006.201.02:30:58.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:30:58.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:30:58.01#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.02:30:58.01#ibcon#ireg 7 cls_cnt 0 2006.201.02:30:58.01#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:30:58.13#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:30:58.13#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:30:58.13#ibcon#enter wrdev, iclass 6, count 0 2006.201.02:30:58.13#ibcon#first serial, iclass 6, count 0 2006.201.02:30:58.13#ibcon#enter sib2, iclass 6, count 0 2006.201.02:30:58.13#ibcon#flushed, iclass 6, count 0 2006.201.02:30:58.13#ibcon#about to write, iclass 6, count 0 2006.201.02:30:58.13#ibcon#wrote, iclass 6, count 0 2006.201.02:30:58.13#ibcon#about to read 3, iclass 6, count 0 2006.201.02:30:58.15#ibcon#read 3, iclass 6, count 0 2006.201.02:30:58.15#ibcon#about to read 4, iclass 6, count 0 2006.201.02:30:58.15#ibcon#read 4, iclass 6, count 0 2006.201.02:30:58.15#ibcon#about to read 5, iclass 6, count 0 2006.201.02:30:58.15#ibcon#read 5, iclass 6, count 0 2006.201.02:30:58.15#ibcon#about to read 6, iclass 6, count 0 2006.201.02:30:58.15#ibcon#read 6, iclass 6, count 0 2006.201.02:30:58.15#ibcon#end of sib2, iclass 6, count 0 2006.201.02:30:58.15#ibcon#*mode == 0, iclass 6, count 0 2006.201.02:30:58.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.02:30:58.15#ibcon#[25=USB\r\n] 2006.201.02:30:58.15#ibcon#*before write, iclass 6, count 0 2006.201.02:30:58.15#ibcon#enter sib2, iclass 6, count 0 2006.201.02:30:58.15#ibcon#flushed, iclass 6, count 0 2006.201.02:30:58.15#ibcon#about to write, iclass 6, count 0 2006.201.02:30:58.15#ibcon#wrote, iclass 6, count 0 2006.201.02:30:58.15#ibcon#about to read 3, iclass 6, count 0 2006.201.02:30:58.18#ibcon#read 3, iclass 6, count 0 2006.201.02:30:58.18#ibcon#about to read 4, iclass 6, count 0 2006.201.02:30:58.18#ibcon#read 4, iclass 6, count 0 2006.201.02:30:58.18#ibcon#about to read 5, iclass 6, count 0 2006.201.02:30:58.18#ibcon#read 5, iclass 6, count 0 2006.201.02:30:58.18#ibcon#about to read 6, iclass 6, count 0 2006.201.02:30:58.18#ibcon#read 6, iclass 6, count 0 2006.201.02:30:58.18#ibcon#end of sib2, iclass 6, count 0 2006.201.02:30:58.18#ibcon#*after write, iclass 6, count 0 2006.201.02:30:58.18#ibcon#*before return 0, iclass 6, count 0 2006.201.02:30:58.18#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:30:58.18#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:30:58.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.02:30:58.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.02:30:58.18$vck44/valo=4,624.99 2006.201.02:30:58.18#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.02:30:58.18#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.02:30:58.18#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:58.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:30:58.18#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:30:58.18#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:30:58.18#ibcon#enter wrdev, iclass 10, count 0 2006.201.02:30:58.18#ibcon#first serial, iclass 10, count 0 2006.201.02:30:58.18#ibcon#enter sib2, iclass 10, count 0 2006.201.02:30:58.18#ibcon#flushed, iclass 10, count 0 2006.201.02:30:58.18#ibcon#about to write, iclass 10, count 0 2006.201.02:30:58.18#ibcon#wrote, iclass 10, count 0 2006.201.02:30:58.18#ibcon#about to read 3, iclass 10, count 0 2006.201.02:30:58.20#ibcon#read 3, iclass 10, count 0 2006.201.02:30:58.20#ibcon#about to read 4, iclass 10, count 0 2006.201.02:30:58.20#ibcon#read 4, iclass 10, count 0 2006.201.02:30:58.20#ibcon#about to read 5, iclass 10, count 0 2006.201.02:30:58.20#ibcon#read 5, iclass 10, count 0 2006.201.02:30:58.20#ibcon#about to read 6, iclass 10, count 0 2006.201.02:30:58.20#ibcon#read 6, iclass 10, count 0 2006.201.02:30:58.20#ibcon#end of sib2, iclass 10, count 0 2006.201.02:30:58.20#ibcon#*mode == 0, iclass 10, count 0 2006.201.02:30:58.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.02:30:58.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:30:58.20#ibcon#*before write, iclass 10, count 0 2006.201.02:30:58.20#ibcon#enter sib2, iclass 10, count 0 2006.201.02:30:58.20#ibcon#flushed, iclass 10, count 0 2006.201.02:30:58.20#ibcon#about to write, iclass 10, count 0 2006.201.02:30:58.20#ibcon#wrote, iclass 10, count 0 2006.201.02:30:58.20#ibcon#about to read 3, iclass 10, count 0 2006.201.02:30:58.25#ibcon#read 3, iclass 10, count 0 2006.201.02:30:58.25#ibcon#about to read 4, iclass 10, count 0 2006.201.02:30:58.25#ibcon#read 4, iclass 10, count 0 2006.201.02:30:58.25#ibcon#about to read 5, iclass 10, count 0 2006.201.02:30:58.25#ibcon#read 5, iclass 10, count 0 2006.201.02:30:58.25#ibcon#about to read 6, iclass 10, count 0 2006.201.02:30:58.25#ibcon#read 6, iclass 10, count 0 2006.201.02:30:58.25#ibcon#end of sib2, iclass 10, count 0 2006.201.02:30:58.25#ibcon#*after write, iclass 10, count 0 2006.201.02:30:58.25#ibcon#*before return 0, iclass 10, count 0 2006.201.02:30:58.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:30:58.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:30:58.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.02:30:58.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.02:30:58.25$vck44/va=4,7 2006.201.02:30:58.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.02:30:58.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.02:30:58.25#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:58.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:30:58.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:30:58.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:30:58.30#ibcon#enter wrdev, iclass 12, count 2 2006.201.02:30:58.30#ibcon#first serial, iclass 12, count 2 2006.201.02:30:58.30#ibcon#enter sib2, iclass 12, count 2 2006.201.02:30:58.30#ibcon#flushed, iclass 12, count 2 2006.201.02:30:58.30#ibcon#about to write, iclass 12, count 2 2006.201.02:30:58.30#ibcon#wrote, iclass 12, count 2 2006.201.02:30:58.30#ibcon#about to read 3, iclass 12, count 2 2006.201.02:30:58.32#ibcon#read 3, iclass 12, count 2 2006.201.02:30:58.32#ibcon#about to read 4, iclass 12, count 2 2006.201.02:30:58.32#ibcon#read 4, iclass 12, count 2 2006.201.02:30:58.32#ibcon#about to read 5, iclass 12, count 2 2006.201.02:30:58.32#ibcon#read 5, iclass 12, count 2 2006.201.02:30:58.32#ibcon#about to read 6, iclass 12, count 2 2006.201.02:30:58.32#ibcon#read 6, iclass 12, count 2 2006.201.02:30:58.32#ibcon#end of sib2, iclass 12, count 2 2006.201.02:30:58.32#ibcon#*mode == 0, iclass 12, count 2 2006.201.02:30:58.32#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.02:30:58.32#ibcon#[25=AT04-07\r\n] 2006.201.02:30:58.32#ibcon#*before write, iclass 12, count 2 2006.201.02:30:58.32#ibcon#enter sib2, iclass 12, count 2 2006.201.02:30:58.32#ibcon#flushed, iclass 12, count 2 2006.201.02:30:58.32#ibcon#about to write, iclass 12, count 2 2006.201.02:30:58.32#ibcon#wrote, iclass 12, count 2 2006.201.02:30:58.32#ibcon#about to read 3, iclass 12, count 2 2006.201.02:30:58.35#ibcon#read 3, iclass 12, count 2 2006.201.02:30:58.35#ibcon#about to read 4, iclass 12, count 2 2006.201.02:30:58.35#ibcon#read 4, iclass 12, count 2 2006.201.02:30:58.35#ibcon#about to read 5, iclass 12, count 2 2006.201.02:30:58.35#ibcon#read 5, iclass 12, count 2 2006.201.02:30:58.35#ibcon#about to read 6, iclass 12, count 2 2006.201.02:30:58.35#ibcon#read 6, iclass 12, count 2 2006.201.02:30:58.35#ibcon#end of sib2, iclass 12, count 2 2006.201.02:30:58.35#ibcon#*after write, iclass 12, count 2 2006.201.02:30:58.35#ibcon#*before return 0, iclass 12, count 2 2006.201.02:30:58.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:30:58.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:30:58.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.02:30:58.35#ibcon#ireg 7 cls_cnt 0 2006.201.02:30:58.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:30:58.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:30:58.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:30:58.47#ibcon#enter wrdev, iclass 12, count 0 2006.201.02:30:58.47#ibcon#first serial, iclass 12, count 0 2006.201.02:30:58.47#ibcon#enter sib2, iclass 12, count 0 2006.201.02:30:58.47#ibcon#flushed, iclass 12, count 0 2006.201.02:30:58.47#ibcon#about to write, iclass 12, count 0 2006.201.02:30:58.47#ibcon#wrote, iclass 12, count 0 2006.201.02:30:58.47#ibcon#about to read 3, iclass 12, count 0 2006.201.02:30:58.49#ibcon#read 3, iclass 12, count 0 2006.201.02:30:58.49#ibcon#about to read 4, iclass 12, count 0 2006.201.02:30:58.49#ibcon#read 4, iclass 12, count 0 2006.201.02:30:58.49#ibcon#about to read 5, iclass 12, count 0 2006.201.02:30:58.49#ibcon#read 5, iclass 12, count 0 2006.201.02:30:58.49#ibcon#about to read 6, iclass 12, count 0 2006.201.02:30:58.49#ibcon#read 6, iclass 12, count 0 2006.201.02:30:58.49#ibcon#end of sib2, iclass 12, count 0 2006.201.02:30:58.49#ibcon#*mode == 0, iclass 12, count 0 2006.201.02:30:58.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.02:30:58.49#ibcon#[25=USB\r\n] 2006.201.02:30:58.49#ibcon#*before write, iclass 12, count 0 2006.201.02:30:58.49#ibcon#enter sib2, iclass 12, count 0 2006.201.02:30:58.49#ibcon#flushed, iclass 12, count 0 2006.201.02:30:58.49#ibcon#about to write, iclass 12, count 0 2006.201.02:30:58.49#ibcon#wrote, iclass 12, count 0 2006.201.02:30:58.49#ibcon#about to read 3, iclass 12, count 0 2006.201.02:30:58.52#ibcon#read 3, iclass 12, count 0 2006.201.02:30:58.52#ibcon#about to read 4, iclass 12, count 0 2006.201.02:30:58.52#ibcon#read 4, iclass 12, count 0 2006.201.02:30:58.52#ibcon#about to read 5, iclass 12, count 0 2006.201.02:30:58.52#ibcon#read 5, iclass 12, count 0 2006.201.02:30:58.52#ibcon#about to read 6, iclass 12, count 0 2006.201.02:30:58.52#ibcon#read 6, iclass 12, count 0 2006.201.02:30:58.52#ibcon#end of sib2, iclass 12, count 0 2006.201.02:30:58.52#ibcon#*after write, iclass 12, count 0 2006.201.02:30:58.52#ibcon#*before return 0, iclass 12, count 0 2006.201.02:30:58.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:30:58.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:30:58.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.02:30:58.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.02:30:58.52$vck44/valo=5,734.99 2006.201.02:30:58.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.02:30:58.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.02:30:58.52#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:58.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:30:58.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:30:58.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:30:58.52#ibcon#enter wrdev, iclass 14, count 0 2006.201.02:30:58.52#ibcon#first serial, iclass 14, count 0 2006.201.02:30:58.52#ibcon#enter sib2, iclass 14, count 0 2006.201.02:30:58.52#ibcon#flushed, iclass 14, count 0 2006.201.02:30:58.52#ibcon#about to write, iclass 14, count 0 2006.201.02:30:58.52#ibcon#wrote, iclass 14, count 0 2006.201.02:30:58.52#ibcon#about to read 3, iclass 14, count 0 2006.201.02:30:58.54#ibcon#read 3, iclass 14, count 0 2006.201.02:30:58.54#ibcon#about to read 4, iclass 14, count 0 2006.201.02:30:58.54#ibcon#read 4, iclass 14, count 0 2006.201.02:30:58.54#ibcon#about to read 5, iclass 14, count 0 2006.201.02:30:58.54#ibcon#read 5, iclass 14, count 0 2006.201.02:30:58.54#ibcon#about to read 6, iclass 14, count 0 2006.201.02:30:58.54#ibcon#read 6, iclass 14, count 0 2006.201.02:30:58.54#ibcon#end of sib2, iclass 14, count 0 2006.201.02:30:58.54#ibcon#*mode == 0, iclass 14, count 0 2006.201.02:30:58.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.02:30:58.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:30:58.54#ibcon#*before write, iclass 14, count 0 2006.201.02:30:58.54#ibcon#enter sib2, iclass 14, count 0 2006.201.02:30:58.54#ibcon#flushed, iclass 14, count 0 2006.201.02:30:58.54#ibcon#about to write, iclass 14, count 0 2006.201.02:30:58.54#ibcon#wrote, iclass 14, count 0 2006.201.02:30:58.54#ibcon#about to read 3, iclass 14, count 0 2006.201.02:30:58.58#ibcon#read 3, iclass 14, count 0 2006.201.02:30:58.58#ibcon#about to read 4, iclass 14, count 0 2006.201.02:30:58.58#ibcon#read 4, iclass 14, count 0 2006.201.02:30:58.58#ibcon#about to read 5, iclass 14, count 0 2006.201.02:30:58.58#ibcon#read 5, iclass 14, count 0 2006.201.02:30:58.58#ibcon#about to read 6, iclass 14, count 0 2006.201.02:30:58.58#ibcon#read 6, iclass 14, count 0 2006.201.02:30:58.58#ibcon#end of sib2, iclass 14, count 0 2006.201.02:30:58.58#ibcon#*after write, iclass 14, count 0 2006.201.02:30:58.58#ibcon#*before return 0, iclass 14, count 0 2006.201.02:30:58.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:30:58.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:30:58.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.02:30:58.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.02:30:58.58$vck44/va=5,4 2006.201.02:30:58.58#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.02:30:58.58#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.02:30:58.58#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:58.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:30:58.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:30:58.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:30:58.64#ibcon#enter wrdev, iclass 16, count 2 2006.201.02:30:58.64#ibcon#first serial, iclass 16, count 2 2006.201.02:30:58.64#ibcon#enter sib2, iclass 16, count 2 2006.201.02:30:58.64#ibcon#flushed, iclass 16, count 2 2006.201.02:30:58.64#ibcon#about to write, iclass 16, count 2 2006.201.02:30:58.64#ibcon#wrote, iclass 16, count 2 2006.201.02:30:58.64#ibcon#about to read 3, iclass 16, count 2 2006.201.02:30:58.66#ibcon#read 3, iclass 16, count 2 2006.201.02:30:58.66#ibcon#about to read 4, iclass 16, count 2 2006.201.02:30:58.66#ibcon#read 4, iclass 16, count 2 2006.201.02:30:58.66#ibcon#about to read 5, iclass 16, count 2 2006.201.02:30:58.66#ibcon#read 5, iclass 16, count 2 2006.201.02:30:58.66#ibcon#about to read 6, iclass 16, count 2 2006.201.02:30:58.66#ibcon#read 6, iclass 16, count 2 2006.201.02:30:58.66#ibcon#end of sib2, iclass 16, count 2 2006.201.02:30:58.66#ibcon#*mode == 0, iclass 16, count 2 2006.201.02:30:58.66#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.02:30:58.66#ibcon#[25=AT05-04\r\n] 2006.201.02:30:58.66#ibcon#*before write, iclass 16, count 2 2006.201.02:30:58.66#ibcon#enter sib2, iclass 16, count 2 2006.201.02:30:58.66#ibcon#flushed, iclass 16, count 2 2006.201.02:30:58.66#ibcon#about to write, iclass 16, count 2 2006.201.02:30:58.66#ibcon#wrote, iclass 16, count 2 2006.201.02:30:58.66#ibcon#about to read 3, iclass 16, count 2 2006.201.02:30:58.69#ibcon#read 3, iclass 16, count 2 2006.201.02:30:58.69#ibcon#about to read 4, iclass 16, count 2 2006.201.02:30:58.69#ibcon#read 4, iclass 16, count 2 2006.201.02:30:58.69#ibcon#about to read 5, iclass 16, count 2 2006.201.02:30:58.69#ibcon#read 5, iclass 16, count 2 2006.201.02:30:58.69#ibcon#about to read 6, iclass 16, count 2 2006.201.02:30:58.69#ibcon#read 6, iclass 16, count 2 2006.201.02:30:58.69#ibcon#end of sib2, iclass 16, count 2 2006.201.02:30:58.69#ibcon#*after write, iclass 16, count 2 2006.201.02:30:58.69#ibcon#*before return 0, iclass 16, count 2 2006.201.02:30:58.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:30:58.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:30:58.69#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.02:30:58.69#ibcon#ireg 7 cls_cnt 0 2006.201.02:30:58.69#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:30:58.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:30:58.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:30:58.81#ibcon#enter wrdev, iclass 16, count 0 2006.201.02:30:58.81#ibcon#first serial, iclass 16, count 0 2006.201.02:30:58.81#ibcon#enter sib2, iclass 16, count 0 2006.201.02:30:58.81#ibcon#flushed, iclass 16, count 0 2006.201.02:30:58.81#ibcon#about to write, iclass 16, count 0 2006.201.02:30:58.81#ibcon#wrote, iclass 16, count 0 2006.201.02:30:58.81#ibcon#about to read 3, iclass 16, count 0 2006.201.02:30:58.83#ibcon#read 3, iclass 16, count 0 2006.201.02:30:58.83#ibcon#about to read 4, iclass 16, count 0 2006.201.02:30:58.83#ibcon#read 4, iclass 16, count 0 2006.201.02:30:58.83#ibcon#about to read 5, iclass 16, count 0 2006.201.02:30:58.83#ibcon#read 5, iclass 16, count 0 2006.201.02:30:58.83#ibcon#about to read 6, iclass 16, count 0 2006.201.02:30:58.83#ibcon#read 6, iclass 16, count 0 2006.201.02:30:58.83#ibcon#end of sib2, iclass 16, count 0 2006.201.02:30:58.83#ibcon#*mode == 0, iclass 16, count 0 2006.201.02:30:58.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.02:30:58.83#ibcon#[25=USB\r\n] 2006.201.02:30:58.83#ibcon#*before write, iclass 16, count 0 2006.201.02:30:58.83#ibcon#enter sib2, iclass 16, count 0 2006.201.02:30:58.83#ibcon#flushed, iclass 16, count 0 2006.201.02:30:58.83#ibcon#about to write, iclass 16, count 0 2006.201.02:30:58.83#ibcon#wrote, iclass 16, count 0 2006.201.02:30:58.83#ibcon#about to read 3, iclass 16, count 0 2006.201.02:30:58.86#ibcon#read 3, iclass 16, count 0 2006.201.02:30:58.86#ibcon#about to read 4, iclass 16, count 0 2006.201.02:30:58.86#ibcon#read 4, iclass 16, count 0 2006.201.02:30:58.86#ibcon#about to read 5, iclass 16, count 0 2006.201.02:30:58.86#ibcon#read 5, iclass 16, count 0 2006.201.02:30:58.86#ibcon#about to read 6, iclass 16, count 0 2006.201.02:30:58.86#ibcon#read 6, iclass 16, count 0 2006.201.02:30:58.86#ibcon#end of sib2, iclass 16, count 0 2006.201.02:30:58.86#ibcon#*after write, iclass 16, count 0 2006.201.02:30:58.86#ibcon#*before return 0, iclass 16, count 0 2006.201.02:30:58.86#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:30:58.86#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:30:58.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.02:30:58.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.02:30:58.86$vck44/valo=6,814.99 2006.201.02:30:58.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.02:30:58.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.02:30:58.86#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:58.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:30:58.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:30:58.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:30:58.86#ibcon#enter wrdev, iclass 18, count 0 2006.201.02:30:58.86#ibcon#first serial, iclass 18, count 0 2006.201.02:30:58.86#ibcon#enter sib2, iclass 18, count 0 2006.201.02:30:58.86#ibcon#flushed, iclass 18, count 0 2006.201.02:30:58.86#ibcon#about to write, iclass 18, count 0 2006.201.02:30:58.86#ibcon#wrote, iclass 18, count 0 2006.201.02:30:58.86#ibcon#about to read 3, iclass 18, count 0 2006.201.02:30:58.88#ibcon#read 3, iclass 18, count 0 2006.201.02:30:58.88#ibcon#about to read 4, iclass 18, count 0 2006.201.02:30:58.88#ibcon#read 4, iclass 18, count 0 2006.201.02:30:58.88#ibcon#about to read 5, iclass 18, count 0 2006.201.02:30:58.88#ibcon#read 5, iclass 18, count 0 2006.201.02:30:58.88#ibcon#about to read 6, iclass 18, count 0 2006.201.02:30:58.88#ibcon#read 6, iclass 18, count 0 2006.201.02:30:58.88#ibcon#end of sib2, iclass 18, count 0 2006.201.02:30:58.88#ibcon#*mode == 0, iclass 18, count 0 2006.201.02:30:58.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.02:30:58.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:30:58.88#ibcon#*before write, iclass 18, count 0 2006.201.02:30:58.88#ibcon#enter sib2, iclass 18, count 0 2006.201.02:30:58.88#ibcon#flushed, iclass 18, count 0 2006.201.02:30:58.88#ibcon#about to write, iclass 18, count 0 2006.201.02:30:58.88#ibcon#wrote, iclass 18, count 0 2006.201.02:30:58.88#ibcon#about to read 3, iclass 18, count 0 2006.201.02:30:58.93#ibcon#read 3, iclass 18, count 0 2006.201.02:30:58.93#ibcon#about to read 4, iclass 18, count 0 2006.201.02:30:58.93#ibcon#read 4, iclass 18, count 0 2006.201.02:30:58.93#ibcon#about to read 5, iclass 18, count 0 2006.201.02:30:58.93#ibcon#read 5, iclass 18, count 0 2006.201.02:30:58.93#ibcon#about to read 6, iclass 18, count 0 2006.201.02:30:58.93#ibcon#read 6, iclass 18, count 0 2006.201.02:30:58.93#ibcon#end of sib2, iclass 18, count 0 2006.201.02:30:58.93#ibcon#*after write, iclass 18, count 0 2006.201.02:30:58.93#ibcon#*before return 0, iclass 18, count 0 2006.201.02:30:58.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:30:58.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:30:58.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.02:30:58.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.02:30:58.93$vck44/va=6,5 2006.201.02:30:58.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.02:30:58.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.02:30:58.93#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:58.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:30:58.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:30:58.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:30:58.98#ibcon#enter wrdev, iclass 20, count 2 2006.201.02:30:58.98#ibcon#first serial, iclass 20, count 2 2006.201.02:30:58.98#ibcon#enter sib2, iclass 20, count 2 2006.201.02:30:58.98#ibcon#flushed, iclass 20, count 2 2006.201.02:30:58.98#ibcon#about to write, iclass 20, count 2 2006.201.02:30:58.98#ibcon#wrote, iclass 20, count 2 2006.201.02:30:58.98#ibcon#about to read 3, iclass 20, count 2 2006.201.02:30:59.00#ibcon#read 3, iclass 20, count 2 2006.201.02:30:59.00#ibcon#about to read 4, iclass 20, count 2 2006.201.02:30:59.00#ibcon#read 4, iclass 20, count 2 2006.201.02:30:59.00#ibcon#about to read 5, iclass 20, count 2 2006.201.02:30:59.00#ibcon#read 5, iclass 20, count 2 2006.201.02:30:59.00#ibcon#about to read 6, iclass 20, count 2 2006.201.02:30:59.00#ibcon#read 6, iclass 20, count 2 2006.201.02:30:59.00#ibcon#end of sib2, iclass 20, count 2 2006.201.02:30:59.00#ibcon#*mode == 0, iclass 20, count 2 2006.201.02:30:59.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.02:30:59.00#ibcon#[25=AT06-05\r\n] 2006.201.02:30:59.00#ibcon#*before write, iclass 20, count 2 2006.201.02:30:59.00#ibcon#enter sib2, iclass 20, count 2 2006.201.02:30:59.00#ibcon#flushed, iclass 20, count 2 2006.201.02:30:59.00#ibcon#about to write, iclass 20, count 2 2006.201.02:30:59.00#ibcon#wrote, iclass 20, count 2 2006.201.02:30:59.00#ibcon#about to read 3, iclass 20, count 2 2006.201.02:30:59.03#ibcon#read 3, iclass 20, count 2 2006.201.02:30:59.03#ibcon#about to read 4, iclass 20, count 2 2006.201.02:30:59.03#ibcon#read 4, iclass 20, count 2 2006.201.02:30:59.03#ibcon#about to read 5, iclass 20, count 2 2006.201.02:30:59.03#ibcon#read 5, iclass 20, count 2 2006.201.02:30:59.03#ibcon#about to read 6, iclass 20, count 2 2006.201.02:30:59.03#ibcon#read 6, iclass 20, count 2 2006.201.02:30:59.03#ibcon#end of sib2, iclass 20, count 2 2006.201.02:30:59.03#ibcon#*after write, iclass 20, count 2 2006.201.02:30:59.03#ibcon#*before return 0, iclass 20, count 2 2006.201.02:30:59.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:30:59.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:30:59.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.02:30:59.03#ibcon#ireg 7 cls_cnt 0 2006.201.02:30:59.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:30:59.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:30:59.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:30:59.15#ibcon#enter wrdev, iclass 20, count 0 2006.201.02:30:59.15#ibcon#first serial, iclass 20, count 0 2006.201.02:30:59.15#ibcon#enter sib2, iclass 20, count 0 2006.201.02:30:59.15#ibcon#flushed, iclass 20, count 0 2006.201.02:30:59.15#ibcon#about to write, iclass 20, count 0 2006.201.02:30:59.15#ibcon#wrote, iclass 20, count 0 2006.201.02:30:59.15#ibcon#about to read 3, iclass 20, count 0 2006.201.02:30:59.17#ibcon#read 3, iclass 20, count 0 2006.201.02:30:59.17#ibcon#about to read 4, iclass 20, count 0 2006.201.02:30:59.17#ibcon#read 4, iclass 20, count 0 2006.201.02:30:59.17#ibcon#about to read 5, iclass 20, count 0 2006.201.02:30:59.17#ibcon#read 5, iclass 20, count 0 2006.201.02:30:59.17#ibcon#about to read 6, iclass 20, count 0 2006.201.02:30:59.17#ibcon#read 6, iclass 20, count 0 2006.201.02:30:59.17#ibcon#end of sib2, iclass 20, count 0 2006.201.02:30:59.17#ibcon#*mode == 0, iclass 20, count 0 2006.201.02:30:59.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.02:30:59.17#ibcon#[25=USB\r\n] 2006.201.02:30:59.17#ibcon#*before write, iclass 20, count 0 2006.201.02:30:59.17#ibcon#enter sib2, iclass 20, count 0 2006.201.02:30:59.17#ibcon#flushed, iclass 20, count 0 2006.201.02:30:59.17#ibcon#about to write, iclass 20, count 0 2006.201.02:30:59.17#ibcon#wrote, iclass 20, count 0 2006.201.02:30:59.17#ibcon#about to read 3, iclass 20, count 0 2006.201.02:30:59.20#ibcon#read 3, iclass 20, count 0 2006.201.02:30:59.20#ibcon#about to read 4, iclass 20, count 0 2006.201.02:30:59.20#ibcon#read 4, iclass 20, count 0 2006.201.02:30:59.20#ibcon#about to read 5, iclass 20, count 0 2006.201.02:30:59.20#ibcon#read 5, iclass 20, count 0 2006.201.02:30:59.20#ibcon#about to read 6, iclass 20, count 0 2006.201.02:30:59.20#ibcon#read 6, iclass 20, count 0 2006.201.02:30:59.20#ibcon#end of sib2, iclass 20, count 0 2006.201.02:30:59.20#ibcon#*after write, iclass 20, count 0 2006.201.02:30:59.20#ibcon#*before return 0, iclass 20, count 0 2006.201.02:30:59.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:30:59.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:30:59.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.02:30:59.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.02:30:59.20$vck44/valo=7,864.99 2006.201.02:30:59.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.02:30:59.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.02:30:59.20#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:59.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:30:59.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:30:59.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:30:59.20#ibcon#enter wrdev, iclass 22, count 0 2006.201.02:30:59.20#ibcon#first serial, iclass 22, count 0 2006.201.02:30:59.20#ibcon#enter sib2, iclass 22, count 0 2006.201.02:30:59.20#ibcon#flushed, iclass 22, count 0 2006.201.02:30:59.20#ibcon#about to write, iclass 22, count 0 2006.201.02:30:59.20#ibcon#wrote, iclass 22, count 0 2006.201.02:30:59.20#ibcon#about to read 3, iclass 22, count 0 2006.201.02:30:59.22#ibcon#read 3, iclass 22, count 0 2006.201.02:30:59.22#ibcon#about to read 4, iclass 22, count 0 2006.201.02:30:59.22#ibcon#read 4, iclass 22, count 0 2006.201.02:30:59.22#ibcon#about to read 5, iclass 22, count 0 2006.201.02:30:59.22#ibcon#read 5, iclass 22, count 0 2006.201.02:30:59.22#ibcon#about to read 6, iclass 22, count 0 2006.201.02:30:59.22#ibcon#read 6, iclass 22, count 0 2006.201.02:30:59.22#ibcon#end of sib2, iclass 22, count 0 2006.201.02:30:59.22#ibcon#*mode == 0, iclass 22, count 0 2006.201.02:30:59.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.02:30:59.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:30:59.22#ibcon#*before write, iclass 22, count 0 2006.201.02:30:59.22#ibcon#enter sib2, iclass 22, count 0 2006.201.02:30:59.22#ibcon#flushed, iclass 22, count 0 2006.201.02:30:59.22#ibcon#about to write, iclass 22, count 0 2006.201.02:30:59.22#ibcon#wrote, iclass 22, count 0 2006.201.02:30:59.22#ibcon#about to read 3, iclass 22, count 0 2006.201.02:30:59.26#ibcon#read 3, iclass 22, count 0 2006.201.02:30:59.26#ibcon#about to read 4, iclass 22, count 0 2006.201.02:30:59.26#ibcon#read 4, iclass 22, count 0 2006.201.02:30:59.26#ibcon#about to read 5, iclass 22, count 0 2006.201.02:30:59.26#ibcon#read 5, iclass 22, count 0 2006.201.02:30:59.26#ibcon#about to read 6, iclass 22, count 0 2006.201.02:30:59.26#ibcon#read 6, iclass 22, count 0 2006.201.02:30:59.26#ibcon#end of sib2, iclass 22, count 0 2006.201.02:30:59.26#ibcon#*after write, iclass 22, count 0 2006.201.02:30:59.26#ibcon#*before return 0, iclass 22, count 0 2006.201.02:30:59.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:30:59.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:30:59.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.02:30:59.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.02:30:59.26$vck44/va=7,5 2006.201.02:30:59.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.02:30:59.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.02:30:59.26#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:59.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:30:59.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:30:59.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:30:59.32#ibcon#enter wrdev, iclass 24, count 2 2006.201.02:30:59.32#ibcon#first serial, iclass 24, count 2 2006.201.02:30:59.32#ibcon#enter sib2, iclass 24, count 2 2006.201.02:30:59.32#ibcon#flushed, iclass 24, count 2 2006.201.02:30:59.32#ibcon#about to write, iclass 24, count 2 2006.201.02:30:59.32#ibcon#wrote, iclass 24, count 2 2006.201.02:30:59.32#ibcon#about to read 3, iclass 24, count 2 2006.201.02:30:59.34#ibcon#read 3, iclass 24, count 2 2006.201.02:30:59.34#ibcon#about to read 4, iclass 24, count 2 2006.201.02:30:59.34#ibcon#read 4, iclass 24, count 2 2006.201.02:30:59.34#ibcon#about to read 5, iclass 24, count 2 2006.201.02:30:59.34#ibcon#read 5, iclass 24, count 2 2006.201.02:30:59.34#ibcon#about to read 6, iclass 24, count 2 2006.201.02:30:59.34#ibcon#read 6, iclass 24, count 2 2006.201.02:30:59.34#ibcon#end of sib2, iclass 24, count 2 2006.201.02:30:59.34#ibcon#*mode == 0, iclass 24, count 2 2006.201.02:30:59.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.02:30:59.34#ibcon#[25=AT07-05\r\n] 2006.201.02:30:59.34#ibcon#*before write, iclass 24, count 2 2006.201.02:30:59.34#ibcon#enter sib2, iclass 24, count 2 2006.201.02:30:59.34#ibcon#flushed, iclass 24, count 2 2006.201.02:30:59.34#ibcon#about to write, iclass 24, count 2 2006.201.02:30:59.34#ibcon#wrote, iclass 24, count 2 2006.201.02:30:59.34#ibcon#about to read 3, iclass 24, count 2 2006.201.02:30:59.37#ibcon#read 3, iclass 24, count 2 2006.201.02:30:59.37#ibcon#about to read 4, iclass 24, count 2 2006.201.02:30:59.37#ibcon#read 4, iclass 24, count 2 2006.201.02:30:59.37#ibcon#about to read 5, iclass 24, count 2 2006.201.02:30:59.37#ibcon#read 5, iclass 24, count 2 2006.201.02:30:59.37#ibcon#about to read 6, iclass 24, count 2 2006.201.02:30:59.37#ibcon#read 6, iclass 24, count 2 2006.201.02:30:59.37#ibcon#end of sib2, iclass 24, count 2 2006.201.02:30:59.37#ibcon#*after write, iclass 24, count 2 2006.201.02:30:59.37#ibcon#*before return 0, iclass 24, count 2 2006.201.02:30:59.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:30:59.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:30:59.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.02:30:59.37#ibcon#ireg 7 cls_cnt 0 2006.201.02:30:59.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:30:59.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:30:59.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:30:59.49#ibcon#enter wrdev, iclass 24, count 0 2006.201.02:30:59.49#ibcon#first serial, iclass 24, count 0 2006.201.02:30:59.49#ibcon#enter sib2, iclass 24, count 0 2006.201.02:30:59.49#ibcon#flushed, iclass 24, count 0 2006.201.02:30:59.49#ibcon#about to write, iclass 24, count 0 2006.201.02:30:59.49#ibcon#wrote, iclass 24, count 0 2006.201.02:30:59.49#ibcon#about to read 3, iclass 24, count 0 2006.201.02:30:59.51#ibcon#read 3, iclass 24, count 0 2006.201.02:30:59.51#ibcon#about to read 4, iclass 24, count 0 2006.201.02:30:59.51#ibcon#read 4, iclass 24, count 0 2006.201.02:30:59.51#ibcon#about to read 5, iclass 24, count 0 2006.201.02:30:59.51#ibcon#read 5, iclass 24, count 0 2006.201.02:30:59.51#ibcon#about to read 6, iclass 24, count 0 2006.201.02:30:59.51#ibcon#read 6, iclass 24, count 0 2006.201.02:30:59.51#ibcon#end of sib2, iclass 24, count 0 2006.201.02:30:59.51#ibcon#*mode == 0, iclass 24, count 0 2006.201.02:30:59.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.02:30:59.51#ibcon#[25=USB\r\n] 2006.201.02:30:59.51#ibcon#*before write, iclass 24, count 0 2006.201.02:30:59.51#ibcon#enter sib2, iclass 24, count 0 2006.201.02:30:59.51#ibcon#flushed, iclass 24, count 0 2006.201.02:30:59.51#ibcon#about to write, iclass 24, count 0 2006.201.02:30:59.51#ibcon#wrote, iclass 24, count 0 2006.201.02:30:59.51#ibcon#about to read 3, iclass 24, count 0 2006.201.02:30:59.54#ibcon#read 3, iclass 24, count 0 2006.201.02:30:59.54#ibcon#about to read 4, iclass 24, count 0 2006.201.02:30:59.54#ibcon#read 4, iclass 24, count 0 2006.201.02:30:59.54#ibcon#about to read 5, iclass 24, count 0 2006.201.02:30:59.54#ibcon#read 5, iclass 24, count 0 2006.201.02:30:59.54#ibcon#about to read 6, iclass 24, count 0 2006.201.02:30:59.54#ibcon#read 6, iclass 24, count 0 2006.201.02:30:59.54#ibcon#end of sib2, iclass 24, count 0 2006.201.02:30:59.54#ibcon#*after write, iclass 24, count 0 2006.201.02:30:59.54#ibcon#*before return 0, iclass 24, count 0 2006.201.02:30:59.54#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:30:59.54#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:30:59.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.02:30:59.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.02:30:59.54$vck44/valo=8,884.99 2006.201.02:30:59.54#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.02:30:59.54#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.02:30:59.54#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:59.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:30:59.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:30:59.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:30:59.54#ibcon#enter wrdev, iclass 26, count 0 2006.201.02:30:59.54#ibcon#first serial, iclass 26, count 0 2006.201.02:30:59.54#ibcon#enter sib2, iclass 26, count 0 2006.201.02:30:59.54#ibcon#flushed, iclass 26, count 0 2006.201.02:30:59.54#ibcon#about to write, iclass 26, count 0 2006.201.02:30:59.54#ibcon#wrote, iclass 26, count 0 2006.201.02:30:59.54#ibcon#about to read 3, iclass 26, count 0 2006.201.02:30:59.56#ibcon#read 3, iclass 26, count 0 2006.201.02:30:59.56#ibcon#about to read 4, iclass 26, count 0 2006.201.02:30:59.56#ibcon#read 4, iclass 26, count 0 2006.201.02:30:59.56#ibcon#about to read 5, iclass 26, count 0 2006.201.02:30:59.56#ibcon#read 5, iclass 26, count 0 2006.201.02:30:59.56#ibcon#about to read 6, iclass 26, count 0 2006.201.02:30:59.56#ibcon#read 6, iclass 26, count 0 2006.201.02:30:59.56#ibcon#end of sib2, iclass 26, count 0 2006.201.02:30:59.56#ibcon#*mode == 0, iclass 26, count 0 2006.201.02:30:59.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.02:30:59.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:30:59.56#ibcon#*before write, iclass 26, count 0 2006.201.02:30:59.56#ibcon#enter sib2, iclass 26, count 0 2006.201.02:30:59.56#ibcon#flushed, iclass 26, count 0 2006.201.02:30:59.56#ibcon#about to write, iclass 26, count 0 2006.201.02:30:59.56#ibcon#wrote, iclass 26, count 0 2006.201.02:30:59.56#ibcon#about to read 3, iclass 26, count 0 2006.201.02:30:59.60#ibcon#read 3, iclass 26, count 0 2006.201.02:30:59.60#ibcon#about to read 4, iclass 26, count 0 2006.201.02:30:59.60#ibcon#read 4, iclass 26, count 0 2006.201.02:30:59.60#ibcon#about to read 5, iclass 26, count 0 2006.201.02:30:59.60#ibcon#read 5, iclass 26, count 0 2006.201.02:30:59.60#ibcon#about to read 6, iclass 26, count 0 2006.201.02:30:59.60#ibcon#read 6, iclass 26, count 0 2006.201.02:30:59.60#ibcon#end of sib2, iclass 26, count 0 2006.201.02:30:59.60#ibcon#*after write, iclass 26, count 0 2006.201.02:30:59.60#ibcon#*before return 0, iclass 26, count 0 2006.201.02:30:59.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:30:59.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:30:59.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.02:30:59.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.02:30:59.60$vck44/va=8,4 2006.201.02:30:59.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.02:30:59.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.02:30:59.60#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:59.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:30:59.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:30:59.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:30:59.66#ibcon#enter wrdev, iclass 28, count 2 2006.201.02:30:59.66#ibcon#first serial, iclass 28, count 2 2006.201.02:30:59.66#ibcon#enter sib2, iclass 28, count 2 2006.201.02:30:59.66#ibcon#flushed, iclass 28, count 2 2006.201.02:30:59.66#ibcon#about to write, iclass 28, count 2 2006.201.02:30:59.66#ibcon#wrote, iclass 28, count 2 2006.201.02:30:59.66#ibcon#about to read 3, iclass 28, count 2 2006.201.02:30:59.68#ibcon#read 3, iclass 28, count 2 2006.201.02:30:59.68#ibcon#about to read 4, iclass 28, count 2 2006.201.02:30:59.68#ibcon#read 4, iclass 28, count 2 2006.201.02:30:59.68#ibcon#about to read 5, iclass 28, count 2 2006.201.02:30:59.68#ibcon#read 5, iclass 28, count 2 2006.201.02:30:59.68#ibcon#about to read 6, iclass 28, count 2 2006.201.02:30:59.68#ibcon#read 6, iclass 28, count 2 2006.201.02:30:59.68#ibcon#end of sib2, iclass 28, count 2 2006.201.02:30:59.68#ibcon#*mode == 0, iclass 28, count 2 2006.201.02:30:59.68#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.02:30:59.68#ibcon#[25=AT08-04\r\n] 2006.201.02:30:59.68#ibcon#*before write, iclass 28, count 2 2006.201.02:30:59.68#ibcon#enter sib2, iclass 28, count 2 2006.201.02:30:59.68#ibcon#flushed, iclass 28, count 2 2006.201.02:30:59.68#ibcon#about to write, iclass 28, count 2 2006.201.02:30:59.68#ibcon#wrote, iclass 28, count 2 2006.201.02:30:59.68#ibcon#about to read 3, iclass 28, count 2 2006.201.02:30:59.72#ibcon#read 3, iclass 28, count 2 2006.201.02:30:59.72#ibcon#about to read 4, iclass 28, count 2 2006.201.02:30:59.72#ibcon#read 4, iclass 28, count 2 2006.201.02:30:59.72#ibcon#about to read 5, iclass 28, count 2 2006.201.02:30:59.72#ibcon#read 5, iclass 28, count 2 2006.201.02:30:59.72#ibcon#about to read 6, iclass 28, count 2 2006.201.02:30:59.72#ibcon#read 6, iclass 28, count 2 2006.201.02:30:59.72#ibcon#end of sib2, iclass 28, count 2 2006.201.02:30:59.72#ibcon#*after write, iclass 28, count 2 2006.201.02:30:59.72#ibcon#*before return 0, iclass 28, count 2 2006.201.02:30:59.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:30:59.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.02:30:59.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.02:30:59.72#ibcon#ireg 7 cls_cnt 0 2006.201.02:30:59.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:30:59.84#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:30:59.84#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:30:59.84#ibcon#enter wrdev, iclass 28, count 0 2006.201.02:30:59.84#ibcon#first serial, iclass 28, count 0 2006.201.02:30:59.84#ibcon#enter sib2, iclass 28, count 0 2006.201.02:30:59.84#ibcon#flushed, iclass 28, count 0 2006.201.02:30:59.84#ibcon#about to write, iclass 28, count 0 2006.201.02:30:59.84#ibcon#wrote, iclass 28, count 0 2006.201.02:30:59.84#ibcon#about to read 3, iclass 28, count 0 2006.201.02:30:59.86#ibcon#read 3, iclass 28, count 0 2006.201.02:30:59.86#ibcon#about to read 4, iclass 28, count 0 2006.201.02:30:59.86#ibcon#read 4, iclass 28, count 0 2006.201.02:30:59.86#ibcon#about to read 5, iclass 28, count 0 2006.201.02:30:59.86#ibcon#read 5, iclass 28, count 0 2006.201.02:30:59.86#ibcon#about to read 6, iclass 28, count 0 2006.201.02:30:59.86#ibcon#read 6, iclass 28, count 0 2006.201.02:30:59.86#ibcon#end of sib2, iclass 28, count 0 2006.201.02:30:59.86#ibcon#*mode == 0, iclass 28, count 0 2006.201.02:30:59.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.02:30:59.86#ibcon#[25=USB\r\n] 2006.201.02:30:59.86#ibcon#*before write, iclass 28, count 0 2006.201.02:30:59.86#ibcon#enter sib2, iclass 28, count 0 2006.201.02:30:59.86#ibcon#flushed, iclass 28, count 0 2006.201.02:30:59.86#ibcon#about to write, iclass 28, count 0 2006.201.02:30:59.86#ibcon#wrote, iclass 28, count 0 2006.201.02:30:59.86#ibcon#about to read 3, iclass 28, count 0 2006.201.02:30:59.89#ibcon#read 3, iclass 28, count 0 2006.201.02:30:59.89#ibcon#about to read 4, iclass 28, count 0 2006.201.02:30:59.89#ibcon#read 4, iclass 28, count 0 2006.201.02:30:59.89#ibcon#about to read 5, iclass 28, count 0 2006.201.02:30:59.89#ibcon#read 5, iclass 28, count 0 2006.201.02:30:59.89#ibcon#about to read 6, iclass 28, count 0 2006.201.02:30:59.89#ibcon#read 6, iclass 28, count 0 2006.201.02:30:59.89#ibcon#end of sib2, iclass 28, count 0 2006.201.02:30:59.89#ibcon#*after write, iclass 28, count 0 2006.201.02:30:59.89#ibcon#*before return 0, iclass 28, count 0 2006.201.02:30:59.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:30:59.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.02:30:59.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.02:30:59.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.02:30:59.89$vck44/vblo=1,629.99 2006.201.02:30:59.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.02:30:59.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.02:30:59.89#ibcon#ireg 17 cls_cnt 0 2006.201.02:30:59.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:30:59.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:30:59.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:30:59.89#ibcon#enter wrdev, iclass 30, count 0 2006.201.02:30:59.89#ibcon#first serial, iclass 30, count 0 2006.201.02:30:59.89#ibcon#enter sib2, iclass 30, count 0 2006.201.02:30:59.89#ibcon#flushed, iclass 30, count 0 2006.201.02:30:59.89#ibcon#about to write, iclass 30, count 0 2006.201.02:30:59.89#ibcon#wrote, iclass 30, count 0 2006.201.02:30:59.89#ibcon#about to read 3, iclass 30, count 0 2006.201.02:30:59.91#ibcon#read 3, iclass 30, count 0 2006.201.02:30:59.91#ibcon#about to read 4, iclass 30, count 0 2006.201.02:30:59.91#ibcon#read 4, iclass 30, count 0 2006.201.02:30:59.91#ibcon#about to read 5, iclass 30, count 0 2006.201.02:30:59.91#ibcon#read 5, iclass 30, count 0 2006.201.02:30:59.91#ibcon#about to read 6, iclass 30, count 0 2006.201.02:30:59.91#ibcon#read 6, iclass 30, count 0 2006.201.02:30:59.91#ibcon#end of sib2, iclass 30, count 0 2006.201.02:30:59.91#ibcon#*mode == 0, iclass 30, count 0 2006.201.02:30:59.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.02:30:59.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:30:59.91#ibcon#*before write, iclass 30, count 0 2006.201.02:30:59.91#ibcon#enter sib2, iclass 30, count 0 2006.201.02:30:59.91#ibcon#flushed, iclass 30, count 0 2006.201.02:30:59.91#ibcon#about to write, iclass 30, count 0 2006.201.02:30:59.91#ibcon#wrote, iclass 30, count 0 2006.201.02:30:59.91#ibcon#about to read 3, iclass 30, count 0 2006.201.02:30:59.95#ibcon#read 3, iclass 30, count 0 2006.201.02:30:59.95#ibcon#about to read 4, iclass 30, count 0 2006.201.02:30:59.95#ibcon#read 4, iclass 30, count 0 2006.201.02:30:59.95#ibcon#about to read 5, iclass 30, count 0 2006.201.02:30:59.95#ibcon#read 5, iclass 30, count 0 2006.201.02:30:59.95#ibcon#about to read 6, iclass 30, count 0 2006.201.02:30:59.95#ibcon#read 6, iclass 30, count 0 2006.201.02:30:59.95#ibcon#end of sib2, iclass 30, count 0 2006.201.02:30:59.95#ibcon#*after write, iclass 30, count 0 2006.201.02:30:59.95#ibcon#*before return 0, iclass 30, count 0 2006.201.02:30:59.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:30:59.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.02:30:59.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.02:30:59.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.02:30:59.95$vck44/vb=1,4 2006.201.02:30:59.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.02:30:59.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.02:30:59.95#ibcon#ireg 11 cls_cnt 2 2006.201.02:30:59.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:30:59.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:30:59.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:30:59.95#ibcon#enter wrdev, iclass 32, count 2 2006.201.02:30:59.95#ibcon#first serial, iclass 32, count 2 2006.201.02:30:59.95#ibcon#enter sib2, iclass 32, count 2 2006.201.02:30:59.95#ibcon#flushed, iclass 32, count 2 2006.201.02:30:59.95#ibcon#about to write, iclass 32, count 2 2006.201.02:30:59.95#ibcon#wrote, iclass 32, count 2 2006.201.02:30:59.95#ibcon#about to read 3, iclass 32, count 2 2006.201.02:30:59.97#ibcon#read 3, iclass 32, count 2 2006.201.02:30:59.97#ibcon#about to read 4, iclass 32, count 2 2006.201.02:30:59.97#ibcon#read 4, iclass 32, count 2 2006.201.02:30:59.97#ibcon#about to read 5, iclass 32, count 2 2006.201.02:30:59.97#ibcon#read 5, iclass 32, count 2 2006.201.02:30:59.97#ibcon#about to read 6, iclass 32, count 2 2006.201.02:30:59.97#ibcon#read 6, iclass 32, count 2 2006.201.02:30:59.97#ibcon#end of sib2, iclass 32, count 2 2006.201.02:30:59.97#ibcon#*mode == 0, iclass 32, count 2 2006.201.02:30:59.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.02:30:59.97#ibcon#[27=AT01-04\r\n] 2006.201.02:30:59.97#ibcon#*before write, iclass 32, count 2 2006.201.02:30:59.97#ibcon#enter sib2, iclass 32, count 2 2006.201.02:30:59.97#ibcon#flushed, iclass 32, count 2 2006.201.02:30:59.97#ibcon#about to write, iclass 32, count 2 2006.201.02:30:59.97#ibcon#wrote, iclass 32, count 2 2006.201.02:30:59.97#ibcon#about to read 3, iclass 32, count 2 2006.201.02:31:00.00#ibcon#read 3, iclass 32, count 2 2006.201.02:31:00.00#ibcon#about to read 4, iclass 32, count 2 2006.201.02:31:00.00#ibcon#read 4, iclass 32, count 2 2006.201.02:31:00.00#ibcon#about to read 5, iclass 32, count 2 2006.201.02:31:00.00#ibcon#read 5, iclass 32, count 2 2006.201.02:31:00.00#ibcon#about to read 6, iclass 32, count 2 2006.201.02:31:00.00#ibcon#read 6, iclass 32, count 2 2006.201.02:31:00.00#ibcon#end of sib2, iclass 32, count 2 2006.201.02:31:00.00#ibcon#*after write, iclass 32, count 2 2006.201.02:31:00.00#ibcon#*before return 0, iclass 32, count 2 2006.201.02:31:00.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:31:00.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.02:31:00.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.02:31:00.00#ibcon#ireg 7 cls_cnt 0 2006.201.02:31:00.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:31:00.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:31:00.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:31:00.12#ibcon#enter wrdev, iclass 32, count 0 2006.201.02:31:00.12#ibcon#first serial, iclass 32, count 0 2006.201.02:31:00.12#ibcon#enter sib2, iclass 32, count 0 2006.201.02:31:00.12#ibcon#flushed, iclass 32, count 0 2006.201.02:31:00.12#ibcon#about to write, iclass 32, count 0 2006.201.02:31:00.12#ibcon#wrote, iclass 32, count 0 2006.201.02:31:00.12#ibcon#about to read 3, iclass 32, count 0 2006.201.02:31:00.14#ibcon#read 3, iclass 32, count 0 2006.201.02:31:00.14#ibcon#about to read 4, iclass 32, count 0 2006.201.02:31:00.14#ibcon#read 4, iclass 32, count 0 2006.201.02:31:00.14#ibcon#about to read 5, iclass 32, count 0 2006.201.02:31:00.14#ibcon#read 5, iclass 32, count 0 2006.201.02:31:00.14#ibcon#about to read 6, iclass 32, count 0 2006.201.02:31:00.14#ibcon#read 6, iclass 32, count 0 2006.201.02:31:00.14#ibcon#end of sib2, iclass 32, count 0 2006.201.02:31:00.14#ibcon#*mode == 0, iclass 32, count 0 2006.201.02:31:00.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.02:31:00.14#ibcon#[27=USB\r\n] 2006.201.02:31:00.14#ibcon#*before write, iclass 32, count 0 2006.201.02:31:00.14#ibcon#enter sib2, iclass 32, count 0 2006.201.02:31:00.14#ibcon#flushed, iclass 32, count 0 2006.201.02:31:00.14#ibcon#about to write, iclass 32, count 0 2006.201.02:31:00.14#ibcon#wrote, iclass 32, count 0 2006.201.02:31:00.14#ibcon#about to read 3, iclass 32, count 0 2006.201.02:31:00.17#ibcon#read 3, iclass 32, count 0 2006.201.02:31:00.17#ibcon#about to read 4, iclass 32, count 0 2006.201.02:31:00.17#ibcon#read 4, iclass 32, count 0 2006.201.02:31:00.17#ibcon#about to read 5, iclass 32, count 0 2006.201.02:31:00.17#ibcon#read 5, iclass 32, count 0 2006.201.02:31:00.17#ibcon#about to read 6, iclass 32, count 0 2006.201.02:31:00.17#ibcon#read 6, iclass 32, count 0 2006.201.02:31:00.17#ibcon#end of sib2, iclass 32, count 0 2006.201.02:31:00.17#ibcon#*after write, iclass 32, count 0 2006.201.02:31:00.17#ibcon#*before return 0, iclass 32, count 0 2006.201.02:31:00.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:31:00.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.02:31:00.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.02:31:00.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.02:31:00.17$vck44/vblo=2,634.99 2006.201.02:31:00.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.02:31:00.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.02:31:00.17#ibcon#ireg 17 cls_cnt 0 2006.201.02:31:00.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:31:00.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:31:00.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:31:00.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.02:31:00.17#ibcon#first serial, iclass 34, count 0 2006.201.02:31:00.17#ibcon#enter sib2, iclass 34, count 0 2006.201.02:31:00.17#ibcon#flushed, iclass 34, count 0 2006.201.02:31:00.17#ibcon#about to write, iclass 34, count 0 2006.201.02:31:00.17#ibcon#wrote, iclass 34, count 0 2006.201.02:31:00.17#ibcon#about to read 3, iclass 34, count 0 2006.201.02:31:00.19#ibcon#read 3, iclass 34, count 0 2006.201.02:31:00.19#ibcon#about to read 4, iclass 34, count 0 2006.201.02:31:00.19#ibcon#read 4, iclass 34, count 0 2006.201.02:31:00.19#ibcon#about to read 5, iclass 34, count 0 2006.201.02:31:00.19#ibcon#read 5, iclass 34, count 0 2006.201.02:31:00.19#ibcon#about to read 6, iclass 34, count 0 2006.201.02:31:00.19#ibcon#read 6, iclass 34, count 0 2006.201.02:31:00.19#ibcon#end of sib2, iclass 34, count 0 2006.201.02:31:00.19#ibcon#*mode == 0, iclass 34, count 0 2006.201.02:31:00.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.02:31:00.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:31:00.19#ibcon#*before write, iclass 34, count 0 2006.201.02:31:00.19#ibcon#enter sib2, iclass 34, count 0 2006.201.02:31:00.19#ibcon#flushed, iclass 34, count 0 2006.201.02:31:00.19#ibcon#about to write, iclass 34, count 0 2006.201.02:31:00.19#ibcon#wrote, iclass 34, count 0 2006.201.02:31:00.19#ibcon#about to read 3, iclass 34, count 0 2006.201.02:31:00.23#ibcon#read 3, iclass 34, count 0 2006.201.02:31:00.23#ibcon#about to read 4, iclass 34, count 0 2006.201.02:31:00.23#ibcon#read 4, iclass 34, count 0 2006.201.02:31:00.23#ibcon#about to read 5, iclass 34, count 0 2006.201.02:31:00.23#ibcon#read 5, iclass 34, count 0 2006.201.02:31:00.23#ibcon#about to read 6, iclass 34, count 0 2006.201.02:31:00.23#ibcon#read 6, iclass 34, count 0 2006.201.02:31:00.23#ibcon#end of sib2, iclass 34, count 0 2006.201.02:31:00.23#ibcon#*after write, iclass 34, count 0 2006.201.02:31:00.23#ibcon#*before return 0, iclass 34, count 0 2006.201.02:31:00.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:31:00.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.02:31:00.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.02:31:00.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.02:31:00.23$vck44/vb=2,5 2006.201.02:31:00.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.02:31:00.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.02:31:00.23#ibcon#ireg 11 cls_cnt 2 2006.201.02:31:00.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:31:00.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:31:00.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:31:00.29#ibcon#enter wrdev, iclass 36, count 2 2006.201.02:31:00.29#ibcon#first serial, iclass 36, count 2 2006.201.02:31:00.29#ibcon#enter sib2, iclass 36, count 2 2006.201.02:31:00.29#ibcon#flushed, iclass 36, count 2 2006.201.02:31:00.29#ibcon#about to write, iclass 36, count 2 2006.201.02:31:00.29#ibcon#wrote, iclass 36, count 2 2006.201.02:31:00.29#ibcon#about to read 3, iclass 36, count 2 2006.201.02:31:00.31#ibcon#read 3, iclass 36, count 2 2006.201.02:31:00.31#ibcon#about to read 4, iclass 36, count 2 2006.201.02:31:00.31#ibcon#read 4, iclass 36, count 2 2006.201.02:31:00.31#ibcon#about to read 5, iclass 36, count 2 2006.201.02:31:00.31#ibcon#read 5, iclass 36, count 2 2006.201.02:31:00.31#ibcon#about to read 6, iclass 36, count 2 2006.201.02:31:00.31#ibcon#read 6, iclass 36, count 2 2006.201.02:31:00.31#ibcon#end of sib2, iclass 36, count 2 2006.201.02:31:00.31#ibcon#*mode == 0, iclass 36, count 2 2006.201.02:31:00.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.02:31:00.31#ibcon#[27=AT02-05\r\n] 2006.201.02:31:00.31#ibcon#*before write, iclass 36, count 2 2006.201.02:31:00.31#ibcon#enter sib2, iclass 36, count 2 2006.201.02:31:00.31#ibcon#flushed, iclass 36, count 2 2006.201.02:31:00.31#ibcon#about to write, iclass 36, count 2 2006.201.02:31:00.31#ibcon#wrote, iclass 36, count 2 2006.201.02:31:00.31#ibcon#about to read 3, iclass 36, count 2 2006.201.02:31:00.34#ibcon#read 3, iclass 36, count 2 2006.201.02:31:00.34#ibcon#about to read 4, iclass 36, count 2 2006.201.02:31:00.34#ibcon#read 4, iclass 36, count 2 2006.201.02:31:00.34#ibcon#about to read 5, iclass 36, count 2 2006.201.02:31:00.34#ibcon#read 5, iclass 36, count 2 2006.201.02:31:00.34#ibcon#about to read 6, iclass 36, count 2 2006.201.02:31:00.34#ibcon#read 6, iclass 36, count 2 2006.201.02:31:00.34#ibcon#end of sib2, iclass 36, count 2 2006.201.02:31:00.34#ibcon#*after write, iclass 36, count 2 2006.201.02:31:00.34#ibcon#*before return 0, iclass 36, count 2 2006.201.02:31:00.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:31:00.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.02:31:00.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.02:31:00.34#ibcon#ireg 7 cls_cnt 0 2006.201.02:31:00.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:31:00.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:31:00.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:31:00.46#ibcon#enter wrdev, iclass 36, count 0 2006.201.02:31:00.46#ibcon#first serial, iclass 36, count 0 2006.201.02:31:00.46#ibcon#enter sib2, iclass 36, count 0 2006.201.02:31:00.46#ibcon#flushed, iclass 36, count 0 2006.201.02:31:00.46#ibcon#about to write, iclass 36, count 0 2006.201.02:31:00.46#ibcon#wrote, iclass 36, count 0 2006.201.02:31:00.46#ibcon#about to read 3, iclass 36, count 0 2006.201.02:31:00.48#ibcon#read 3, iclass 36, count 0 2006.201.02:31:00.48#ibcon#about to read 4, iclass 36, count 0 2006.201.02:31:00.48#ibcon#read 4, iclass 36, count 0 2006.201.02:31:00.48#ibcon#about to read 5, iclass 36, count 0 2006.201.02:31:00.48#ibcon#read 5, iclass 36, count 0 2006.201.02:31:00.48#ibcon#about to read 6, iclass 36, count 0 2006.201.02:31:00.48#ibcon#read 6, iclass 36, count 0 2006.201.02:31:00.48#ibcon#end of sib2, iclass 36, count 0 2006.201.02:31:00.48#ibcon#*mode == 0, iclass 36, count 0 2006.201.02:31:00.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.02:31:00.48#ibcon#[27=USB\r\n] 2006.201.02:31:00.48#ibcon#*before write, iclass 36, count 0 2006.201.02:31:00.48#ibcon#enter sib2, iclass 36, count 0 2006.201.02:31:00.48#ibcon#flushed, iclass 36, count 0 2006.201.02:31:00.48#ibcon#about to write, iclass 36, count 0 2006.201.02:31:00.48#ibcon#wrote, iclass 36, count 0 2006.201.02:31:00.48#ibcon#about to read 3, iclass 36, count 0 2006.201.02:31:00.51#ibcon#read 3, iclass 36, count 0 2006.201.02:31:00.51#ibcon#about to read 4, iclass 36, count 0 2006.201.02:31:00.51#ibcon#read 4, iclass 36, count 0 2006.201.02:31:00.51#ibcon#about to read 5, iclass 36, count 0 2006.201.02:31:00.51#ibcon#read 5, iclass 36, count 0 2006.201.02:31:00.51#ibcon#about to read 6, iclass 36, count 0 2006.201.02:31:00.51#ibcon#read 6, iclass 36, count 0 2006.201.02:31:00.51#ibcon#end of sib2, iclass 36, count 0 2006.201.02:31:00.51#ibcon#*after write, iclass 36, count 0 2006.201.02:31:00.51#ibcon#*before return 0, iclass 36, count 0 2006.201.02:31:00.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:31:00.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.02:31:00.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.02:31:00.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.02:31:00.51$vck44/vblo=3,649.99 2006.201.02:31:00.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.02:31:00.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.02:31:00.51#ibcon#ireg 17 cls_cnt 0 2006.201.02:31:00.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:31:00.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:31:00.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:31:00.51#ibcon#enter wrdev, iclass 38, count 0 2006.201.02:31:00.51#ibcon#first serial, iclass 38, count 0 2006.201.02:31:00.51#ibcon#enter sib2, iclass 38, count 0 2006.201.02:31:00.51#ibcon#flushed, iclass 38, count 0 2006.201.02:31:00.51#ibcon#about to write, iclass 38, count 0 2006.201.02:31:00.51#ibcon#wrote, iclass 38, count 0 2006.201.02:31:00.51#ibcon#about to read 3, iclass 38, count 0 2006.201.02:31:00.53#ibcon#read 3, iclass 38, count 0 2006.201.02:31:00.53#ibcon#about to read 4, iclass 38, count 0 2006.201.02:31:00.53#ibcon#read 4, iclass 38, count 0 2006.201.02:31:00.53#ibcon#about to read 5, iclass 38, count 0 2006.201.02:31:00.53#ibcon#read 5, iclass 38, count 0 2006.201.02:31:00.53#ibcon#about to read 6, iclass 38, count 0 2006.201.02:31:00.53#ibcon#read 6, iclass 38, count 0 2006.201.02:31:00.53#ibcon#end of sib2, iclass 38, count 0 2006.201.02:31:00.53#ibcon#*mode == 0, iclass 38, count 0 2006.201.02:31:00.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.02:31:00.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:31:00.53#ibcon#*before write, iclass 38, count 0 2006.201.02:31:00.53#ibcon#enter sib2, iclass 38, count 0 2006.201.02:31:00.53#ibcon#flushed, iclass 38, count 0 2006.201.02:31:00.53#ibcon#about to write, iclass 38, count 0 2006.201.02:31:00.53#ibcon#wrote, iclass 38, count 0 2006.201.02:31:00.53#ibcon#about to read 3, iclass 38, count 0 2006.201.02:31:00.58#ibcon#read 3, iclass 38, count 0 2006.201.02:31:00.58#ibcon#about to read 4, iclass 38, count 0 2006.201.02:31:00.58#ibcon#read 4, iclass 38, count 0 2006.201.02:31:00.58#ibcon#about to read 5, iclass 38, count 0 2006.201.02:31:00.58#ibcon#read 5, iclass 38, count 0 2006.201.02:31:00.58#ibcon#about to read 6, iclass 38, count 0 2006.201.02:31:00.58#ibcon#read 6, iclass 38, count 0 2006.201.02:31:00.58#ibcon#end of sib2, iclass 38, count 0 2006.201.02:31:00.58#ibcon#*after write, iclass 38, count 0 2006.201.02:31:00.58#ibcon#*before return 0, iclass 38, count 0 2006.201.02:31:00.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:31:00.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:31:00.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.02:31:00.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.02:31:00.58$vck44/vb=3,4 2006.201.02:31:00.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.02:31:00.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.02:31:00.58#ibcon#ireg 11 cls_cnt 2 2006.201.02:31:00.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:31:00.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:31:00.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:31:00.63#ibcon#enter wrdev, iclass 40, count 2 2006.201.02:31:00.63#ibcon#first serial, iclass 40, count 2 2006.201.02:31:00.63#ibcon#enter sib2, iclass 40, count 2 2006.201.02:31:00.63#ibcon#flushed, iclass 40, count 2 2006.201.02:31:00.63#ibcon#about to write, iclass 40, count 2 2006.201.02:31:00.63#ibcon#wrote, iclass 40, count 2 2006.201.02:31:00.63#ibcon#about to read 3, iclass 40, count 2 2006.201.02:31:00.65#ibcon#read 3, iclass 40, count 2 2006.201.02:31:00.65#ibcon#about to read 4, iclass 40, count 2 2006.201.02:31:00.65#ibcon#read 4, iclass 40, count 2 2006.201.02:31:00.65#ibcon#about to read 5, iclass 40, count 2 2006.201.02:31:00.65#ibcon#read 5, iclass 40, count 2 2006.201.02:31:00.65#ibcon#about to read 6, iclass 40, count 2 2006.201.02:31:00.65#ibcon#read 6, iclass 40, count 2 2006.201.02:31:00.65#ibcon#end of sib2, iclass 40, count 2 2006.201.02:31:00.65#ibcon#*mode == 0, iclass 40, count 2 2006.201.02:31:00.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.02:31:00.65#ibcon#[27=AT03-04\r\n] 2006.201.02:31:00.65#ibcon#*before write, iclass 40, count 2 2006.201.02:31:00.65#ibcon#enter sib2, iclass 40, count 2 2006.201.02:31:00.65#ibcon#flushed, iclass 40, count 2 2006.201.02:31:00.65#ibcon#about to write, iclass 40, count 2 2006.201.02:31:00.65#ibcon#wrote, iclass 40, count 2 2006.201.02:31:00.65#ibcon#about to read 3, iclass 40, count 2 2006.201.02:31:00.68#ibcon#read 3, iclass 40, count 2 2006.201.02:31:00.68#ibcon#about to read 4, iclass 40, count 2 2006.201.02:31:00.68#ibcon#read 4, iclass 40, count 2 2006.201.02:31:00.68#ibcon#about to read 5, iclass 40, count 2 2006.201.02:31:00.68#ibcon#read 5, iclass 40, count 2 2006.201.02:31:00.68#ibcon#about to read 6, iclass 40, count 2 2006.201.02:31:00.68#ibcon#read 6, iclass 40, count 2 2006.201.02:31:00.68#ibcon#end of sib2, iclass 40, count 2 2006.201.02:31:00.68#ibcon#*after write, iclass 40, count 2 2006.201.02:31:00.68#ibcon#*before return 0, iclass 40, count 2 2006.201.02:31:00.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:31:00.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.02:31:00.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.02:31:00.68#ibcon#ireg 7 cls_cnt 0 2006.201.02:31:00.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:31:00.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:31:00.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:31:00.80#ibcon#enter wrdev, iclass 40, count 0 2006.201.02:31:00.80#ibcon#first serial, iclass 40, count 0 2006.201.02:31:00.80#ibcon#enter sib2, iclass 40, count 0 2006.201.02:31:00.80#ibcon#flushed, iclass 40, count 0 2006.201.02:31:00.80#ibcon#about to write, iclass 40, count 0 2006.201.02:31:00.80#ibcon#wrote, iclass 40, count 0 2006.201.02:31:00.80#ibcon#about to read 3, iclass 40, count 0 2006.201.02:31:00.82#ibcon#read 3, iclass 40, count 0 2006.201.02:31:00.82#ibcon#about to read 4, iclass 40, count 0 2006.201.02:31:00.82#ibcon#read 4, iclass 40, count 0 2006.201.02:31:00.82#ibcon#about to read 5, iclass 40, count 0 2006.201.02:31:00.82#ibcon#read 5, iclass 40, count 0 2006.201.02:31:00.82#ibcon#about to read 6, iclass 40, count 0 2006.201.02:31:00.82#ibcon#read 6, iclass 40, count 0 2006.201.02:31:00.82#ibcon#end of sib2, iclass 40, count 0 2006.201.02:31:00.82#ibcon#*mode == 0, iclass 40, count 0 2006.201.02:31:00.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.02:31:00.82#ibcon#[27=USB\r\n] 2006.201.02:31:00.82#ibcon#*before write, iclass 40, count 0 2006.201.02:31:00.82#ibcon#enter sib2, iclass 40, count 0 2006.201.02:31:00.82#ibcon#flushed, iclass 40, count 0 2006.201.02:31:00.82#ibcon#about to write, iclass 40, count 0 2006.201.02:31:00.82#ibcon#wrote, iclass 40, count 0 2006.201.02:31:00.82#ibcon#about to read 3, iclass 40, count 0 2006.201.02:31:00.85#ibcon#read 3, iclass 40, count 0 2006.201.02:31:00.85#ibcon#about to read 4, iclass 40, count 0 2006.201.02:31:00.85#ibcon#read 4, iclass 40, count 0 2006.201.02:31:00.85#ibcon#about to read 5, iclass 40, count 0 2006.201.02:31:00.85#ibcon#read 5, iclass 40, count 0 2006.201.02:31:00.85#ibcon#about to read 6, iclass 40, count 0 2006.201.02:31:00.85#ibcon#read 6, iclass 40, count 0 2006.201.02:31:00.85#ibcon#end of sib2, iclass 40, count 0 2006.201.02:31:00.85#ibcon#*after write, iclass 40, count 0 2006.201.02:31:00.85#ibcon#*before return 0, iclass 40, count 0 2006.201.02:31:00.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:31:00.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.02:31:00.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.02:31:00.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.02:31:00.85$vck44/vblo=4,679.99 2006.201.02:31:00.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.02:31:00.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.02:31:00.85#ibcon#ireg 17 cls_cnt 0 2006.201.02:31:00.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:31:00.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:31:00.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:31:00.85#ibcon#enter wrdev, iclass 4, count 0 2006.201.02:31:00.85#ibcon#first serial, iclass 4, count 0 2006.201.02:31:00.85#ibcon#enter sib2, iclass 4, count 0 2006.201.02:31:00.85#ibcon#flushed, iclass 4, count 0 2006.201.02:31:00.85#ibcon#about to write, iclass 4, count 0 2006.201.02:31:00.85#ibcon#wrote, iclass 4, count 0 2006.201.02:31:00.85#ibcon#about to read 3, iclass 4, count 0 2006.201.02:31:00.87#ibcon#read 3, iclass 4, count 0 2006.201.02:31:00.87#ibcon#about to read 4, iclass 4, count 0 2006.201.02:31:00.87#ibcon#read 4, iclass 4, count 0 2006.201.02:31:00.87#ibcon#about to read 5, iclass 4, count 0 2006.201.02:31:00.87#ibcon#read 5, iclass 4, count 0 2006.201.02:31:00.87#ibcon#about to read 6, iclass 4, count 0 2006.201.02:31:00.87#ibcon#read 6, iclass 4, count 0 2006.201.02:31:00.87#ibcon#end of sib2, iclass 4, count 0 2006.201.02:31:00.87#ibcon#*mode == 0, iclass 4, count 0 2006.201.02:31:00.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.02:31:00.87#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:31:00.87#ibcon#*before write, iclass 4, count 0 2006.201.02:31:00.87#ibcon#enter sib2, iclass 4, count 0 2006.201.02:31:00.87#ibcon#flushed, iclass 4, count 0 2006.201.02:31:00.87#ibcon#about to write, iclass 4, count 0 2006.201.02:31:00.87#ibcon#wrote, iclass 4, count 0 2006.201.02:31:00.87#ibcon#about to read 3, iclass 4, count 0 2006.201.02:31:00.91#ibcon#read 3, iclass 4, count 0 2006.201.02:31:00.91#ibcon#about to read 4, iclass 4, count 0 2006.201.02:31:00.91#ibcon#read 4, iclass 4, count 0 2006.201.02:31:00.91#ibcon#about to read 5, iclass 4, count 0 2006.201.02:31:00.91#ibcon#read 5, iclass 4, count 0 2006.201.02:31:00.91#ibcon#about to read 6, iclass 4, count 0 2006.201.02:31:00.91#ibcon#read 6, iclass 4, count 0 2006.201.02:31:00.91#ibcon#end of sib2, iclass 4, count 0 2006.201.02:31:00.91#ibcon#*after write, iclass 4, count 0 2006.201.02:31:00.91#ibcon#*before return 0, iclass 4, count 0 2006.201.02:31:00.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:31:00.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.02:31:00.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.02:31:00.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.02:31:00.91$vck44/vb=4,5 2006.201.02:31:00.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.02:31:00.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.02:31:00.91#ibcon#ireg 11 cls_cnt 2 2006.201.02:31:00.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:31:00.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:31:00.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:31:00.97#ibcon#enter wrdev, iclass 6, count 2 2006.201.02:31:00.97#ibcon#first serial, iclass 6, count 2 2006.201.02:31:00.97#ibcon#enter sib2, iclass 6, count 2 2006.201.02:31:00.97#ibcon#flushed, iclass 6, count 2 2006.201.02:31:00.97#ibcon#about to write, iclass 6, count 2 2006.201.02:31:00.97#ibcon#wrote, iclass 6, count 2 2006.201.02:31:00.97#ibcon#about to read 3, iclass 6, count 2 2006.201.02:31:00.99#ibcon#read 3, iclass 6, count 2 2006.201.02:31:00.99#ibcon#about to read 4, iclass 6, count 2 2006.201.02:31:00.99#ibcon#read 4, iclass 6, count 2 2006.201.02:31:00.99#ibcon#about to read 5, iclass 6, count 2 2006.201.02:31:00.99#ibcon#read 5, iclass 6, count 2 2006.201.02:31:00.99#ibcon#about to read 6, iclass 6, count 2 2006.201.02:31:00.99#ibcon#read 6, iclass 6, count 2 2006.201.02:31:00.99#ibcon#end of sib2, iclass 6, count 2 2006.201.02:31:00.99#ibcon#*mode == 0, iclass 6, count 2 2006.201.02:31:00.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.02:31:00.99#ibcon#[27=AT04-05\r\n] 2006.201.02:31:00.99#ibcon#*before write, iclass 6, count 2 2006.201.02:31:00.99#ibcon#enter sib2, iclass 6, count 2 2006.201.02:31:00.99#ibcon#flushed, iclass 6, count 2 2006.201.02:31:00.99#ibcon#about to write, iclass 6, count 2 2006.201.02:31:00.99#ibcon#wrote, iclass 6, count 2 2006.201.02:31:00.99#ibcon#about to read 3, iclass 6, count 2 2006.201.02:31:01.02#ibcon#read 3, iclass 6, count 2 2006.201.02:31:01.02#ibcon#about to read 4, iclass 6, count 2 2006.201.02:31:01.02#ibcon#read 4, iclass 6, count 2 2006.201.02:31:01.02#ibcon#about to read 5, iclass 6, count 2 2006.201.02:31:01.02#ibcon#read 5, iclass 6, count 2 2006.201.02:31:01.02#ibcon#about to read 6, iclass 6, count 2 2006.201.02:31:01.02#ibcon#read 6, iclass 6, count 2 2006.201.02:31:01.02#ibcon#end of sib2, iclass 6, count 2 2006.201.02:31:01.02#ibcon#*after write, iclass 6, count 2 2006.201.02:31:01.02#ibcon#*before return 0, iclass 6, count 2 2006.201.02:31:01.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:31:01.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.02:31:01.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.02:31:01.02#ibcon#ireg 7 cls_cnt 0 2006.201.02:31:01.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:31:01.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:31:01.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:31:01.14#ibcon#enter wrdev, iclass 6, count 0 2006.201.02:31:01.14#ibcon#first serial, iclass 6, count 0 2006.201.02:31:01.14#ibcon#enter sib2, iclass 6, count 0 2006.201.02:31:01.14#ibcon#flushed, iclass 6, count 0 2006.201.02:31:01.14#ibcon#about to write, iclass 6, count 0 2006.201.02:31:01.14#ibcon#wrote, iclass 6, count 0 2006.201.02:31:01.14#ibcon#about to read 3, iclass 6, count 0 2006.201.02:31:01.16#ibcon#read 3, iclass 6, count 0 2006.201.02:31:01.16#ibcon#about to read 4, iclass 6, count 0 2006.201.02:31:01.16#ibcon#read 4, iclass 6, count 0 2006.201.02:31:01.16#ibcon#about to read 5, iclass 6, count 0 2006.201.02:31:01.16#ibcon#read 5, iclass 6, count 0 2006.201.02:31:01.16#ibcon#about to read 6, iclass 6, count 0 2006.201.02:31:01.16#ibcon#read 6, iclass 6, count 0 2006.201.02:31:01.16#ibcon#end of sib2, iclass 6, count 0 2006.201.02:31:01.16#ibcon#*mode == 0, iclass 6, count 0 2006.201.02:31:01.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.02:31:01.16#ibcon#[27=USB\r\n] 2006.201.02:31:01.16#ibcon#*before write, iclass 6, count 0 2006.201.02:31:01.16#ibcon#enter sib2, iclass 6, count 0 2006.201.02:31:01.16#ibcon#flushed, iclass 6, count 0 2006.201.02:31:01.16#ibcon#about to write, iclass 6, count 0 2006.201.02:31:01.16#ibcon#wrote, iclass 6, count 0 2006.201.02:31:01.16#ibcon#about to read 3, iclass 6, count 0 2006.201.02:31:01.19#ibcon#read 3, iclass 6, count 0 2006.201.02:31:01.19#ibcon#about to read 4, iclass 6, count 0 2006.201.02:31:01.19#ibcon#read 4, iclass 6, count 0 2006.201.02:31:01.19#ibcon#about to read 5, iclass 6, count 0 2006.201.02:31:01.19#ibcon#read 5, iclass 6, count 0 2006.201.02:31:01.19#ibcon#about to read 6, iclass 6, count 0 2006.201.02:31:01.19#ibcon#read 6, iclass 6, count 0 2006.201.02:31:01.19#ibcon#end of sib2, iclass 6, count 0 2006.201.02:31:01.19#ibcon#*after write, iclass 6, count 0 2006.201.02:31:01.19#ibcon#*before return 0, iclass 6, count 0 2006.201.02:31:01.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:31:01.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.02:31:01.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.02:31:01.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.02:31:01.19$vck44/vblo=5,709.99 2006.201.02:31:01.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.02:31:01.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.02:31:01.19#ibcon#ireg 17 cls_cnt 0 2006.201.02:31:01.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:31:01.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:31:01.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:31:01.19#ibcon#enter wrdev, iclass 10, count 0 2006.201.02:31:01.19#ibcon#first serial, iclass 10, count 0 2006.201.02:31:01.19#ibcon#enter sib2, iclass 10, count 0 2006.201.02:31:01.19#ibcon#flushed, iclass 10, count 0 2006.201.02:31:01.19#ibcon#about to write, iclass 10, count 0 2006.201.02:31:01.19#ibcon#wrote, iclass 10, count 0 2006.201.02:31:01.19#ibcon#about to read 3, iclass 10, count 0 2006.201.02:31:01.21#ibcon#read 3, iclass 10, count 0 2006.201.02:31:01.21#ibcon#about to read 4, iclass 10, count 0 2006.201.02:31:01.21#ibcon#read 4, iclass 10, count 0 2006.201.02:31:01.21#ibcon#about to read 5, iclass 10, count 0 2006.201.02:31:01.21#ibcon#read 5, iclass 10, count 0 2006.201.02:31:01.21#ibcon#about to read 6, iclass 10, count 0 2006.201.02:31:01.21#ibcon#read 6, iclass 10, count 0 2006.201.02:31:01.21#ibcon#end of sib2, iclass 10, count 0 2006.201.02:31:01.21#ibcon#*mode == 0, iclass 10, count 0 2006.201.02:31:01.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.02:31:01.21#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:31:01.21#ibcon#*before write, iclass 10, count 0 2006.201.02:31:01.21#ibcon#enter sib2, iclass 10, count 0 2006.201.02:31:01.21#ibcon#flushed, iclass 10, count 0 2006.201.02:31:01.21#ibcon#about to write, iclass 10, count 0 2006.201.02:31:01.21#ibcon#wrote, iclass 10, count 0 2006.201.02:31:01.21#ibcon#about to read 3, iclass 10, count 0 2006.201.02:31:01.25#ibcon#read 3, iclass 10, count 0 2006.201.02:31:01.25#ibcon#about to read 4, iclass 10, count 0 2006.201.02:31:01.25#ibcon#read 4, iclass 10, count 0 2006.201.02:31:01.25#ibcon#about to read 5, iclass 10, count 0 2006.201.02:31:01.25#ibcon#read 5, iclass 10, count 0 2006.201.02:31:01.25#ibcon#about to read 6, iclass 10, count 0 2006.201.02:31:01.25#ibcon#read 6, iclass 10, count 0 2006.201.02:31:01.25#ibcon#end of sib2, iclass 10, count 0 2006.201.02:31:01.25#ibcon#*after write, iclass 10, count 0 2006.201.02:31:01.25#ibcon#*before return 0, iclass 10, count 0 2006.201.02:31:01.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:31:01.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.02:31:01.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.02:31:01.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.02:31:01.25$vck44/vb=5,4 2006.201.02:31:01.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.02:31:01.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.02:31:01.25#ibcon#ireg 11 cls_cnt 2 2006.201.02:31:01.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:31:01.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:31:01.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:31:01.31#ibcon#enter wrdev, iclass 12, count 2 2006.201.02:31:01.31#ibcon#first serial, iclass 12, count 2 2006.201.02:31:01.31#ibcon#enter sib2, iclass 12, count 2 2006.201.02:31:01.31#ibcon#flushed, iclass 12, count 2 2006.201.02:31:01.31#ibcon#about to write, iclass 12, count 2 2006.201.02:31:01.31#ibcon#wrote, iclass 12, count 2 2006.201.02:31:01.31#ibcon#about to read 3, iclass 12, count 2 2006.201.02:31:01.33#ibcon#read 3, iclass 12, count 2 2006.201.02:31:01.33#ibcon#about to read 4, iclass 12, count 2 2006.201.02:31:01.33#ibcon#read 4, iclass 12, count 2 2006.201.02:31:01.33#ibcon#about to read 5, iclass 12, count 2 2006.201.02:31:01.33#ibcon#read 5, iclass 12, count 2 2006.201.02:31:01.33#ibcon#about to read 6, iclass 12, count 2 2006.201.02:31:01.33#ibcon#read 6, iclass 12, count 2 2006.201.02:31:01.33#ibcon#end of sib2, iclass 12, count 2 2006.201.02:31:01.33#ibcon#*mode == 0, iclass 12, count 2 2006.201.02:31:01.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.02:31:01.33#ibcon#[27=AT05-04\r\n] 2006.201.02:31:01.33#ibcon#*before write, iclass 12, count 2 2006.201.02:31:01.33#ibcon#enter sib2, iclass 12, count 2 2006.201.02:31:01.33#ibcon#flushed, iclass 12, count 2 2006.201.02:31:01.33#ibcon#about to write, iclass 12, count 2 2006.201.02:31:01.33#ibcon#wrote, iclass 12, count 2 2006.201.02:31:01.33#ibcon#about to read 3, iclass 12, count 2 2006.201.02:31:01.36#ibcon#read 3, iclass 12, count 2 2006.201.02:31:01.36#ibcon#about to read 4, iclass 12, count 2 2006.201.02:31:01.36#ibcon#read 4, iclass 12, count 2 2006.201.02:31:01.36#ibcon#about to read 5, iclass 12, count 2 2006.201.02:31:01.36#ibcon#read 5, iclass 12, count 2 2006.201.02:31:01.36#ibcon#about to read 6, iclass 12, count 2 2006.201.02:31:01.36#ibcon#read 6, iclass 12, count 2 2006.201.02:31:01.36#ibcon#end of sib2, iclass 12, count 2 2006.201.02:31:01.36#ibcon#*after write, iclass 12, count 2 2006.201.02:31:01.36#ibcon#*before return 0, iclass 12, count 2 2006.201.02:31:01.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:31:01.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.02:31:01.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.02:31:01.36#ibcon#ireg 7 cls_cnt 0 2006.201.02:31:01.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:31:01.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:31:01.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:31:01.48#ibcon#enter wrdev, iclass 12, count 0 2006.201.02:31:01.48#ibcon#first serial, iclass 12, count 0 2006.201.02:31:01.48#ibcon#enter sib2, iclass 12, count 0 2006.201.02:31:01.48#ibcon#flushed, iclass 12, count 0 2006.201.02:31:01.48#ibcon#about to write, iclass 12, count 0 2006.201.02:31:01.48#ibcon#wrote, iclass 12, count 0 2006.201.02:31:01.48#ibcon#about to read 3, iclass 12, count 0 2006.201.02:31:01.50#ibcon#read 3, iclass 12, count 0 2006.201.02:31:01.50#ibcon#about to read 4, iclass 12, count 0 2006.201.02:31:01.50#ibcon#read 4, iclass 12, count 0 2006.201.02:31:01.50#ibcon#about to read 5, iclass 12, count 0 2006.201.02:31:01.50#ibcon#read 5, iclass 12, count 0 2006.201.02:31:01.50#ibcon#about to read 6, iclass 12, count 0 2006.201.02:31:01.50#ibcon#read 6, iclass 12, count 0 2006.201.02:31:01.50#ibcon#end of sib2, iclass 12, count 0 2006.201.02:31:01.50#ibcon#*mode == 0, iclass 12, count 0 2006.201.02:31:01.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.02:31:01.50#ibcon#[27=USB\r\n] 2006.201.02:31:01.50#ibcon#*before write, iclass 12, count 0 2006.201.02:31:01.50#ibcon#enter sib2, iclass 12, count 0 2006.201.02:31:01.50#ibcon#flushed, iclass 12, count 0 2006.201.02:31:01.50#ibcon#about to write, iclass 12, count 0 2006.201.02:31:01.50#ibcon#wrote, iclass 12, count 0 2006.201.02:31:01.50#ibcon#about to read 3, iclass 12, count 0 2006.201.02:31:01.53#ibcon#read 3, iclass 12, count 0 2006.201.02:31:01.53#ibcon#about to read 4, iclass 12, count 0 2006.201.02:31:01.53#ibcon#read 4, iclass 12, count 0 2006.201.02:31:01.53#ibcon#about to read 5, iclass 12, count 0 2006.201.02:31:01.53#ibcon#read 5, iclass 12, count 0 2006.201.02:31:01.53#ibcon#about to read 6, iclass 12, count 0 2006.201.02:31:01.53#ibcon#read 6, iclass 12, count 0 2006.201.02:31:01.53#ibcon#end of sib2, iclass 12, count 0 2006.201.02:31:01.53#ibcon#*after write, iclass 12, count 0 2006.201.02:31:01.53#ibcon#*before return 0, iclass 12, count 0 2006.201.02:31:01.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:31:01.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.02:31:01.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.02:31:01.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.02:31:01.53$vck44/vblo=6,719.99 2006.201.02:31:01.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.02:31:01.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.02:31:01.53#ibcon#ireg 17 cls_cnt 0 2006.201.02:31:01.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:31:01.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:31:01.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:31:01.53#ibcon#enter wrdev, iclass 14, count 0 2006.201.02:31:01.53#ibcon#first serial, iclass 14, count 0 2006.201.02:31:01.53#ibcon#enter sib2, iclass 14, count 0 2006.201.02:31:01.53#ibcon#flushed, iclass 14, count 0 2006.201.02:31:01.53#ibcon#about to write, iclass 14, count 0 2006.201.02:31:01.53#ibcon#wrote, iclass 14, count 0 2006.201.02:31:01.53#ibcon#about to read 3, iclass 14, count 0 2006.201.02:31:01.55#ibcon#read 3, iclass 14, count 0 2006.201.02:31:01.55#ibcon#about to read 4, iclass 14, count 0 2006.201.02:31:01.55#ibcon#read 4, iclass 14, count 0 2006.201.02:31:01.55#ibcon#about to read 5, iclass 14, count 0 2006.201.02:31:01.55#ibcon#read 5, iclass 14, count 0 2006.201.02:31:01.55#ibcon#about to read 6, iclass 14, count 0 2006.201.02:31:01.55#ibcon#read 6, iclass 14, count 0 2006.201.02:31:01.55#ibcon#end of sib2, iclass 14, count 0 2006.201.02:31:01.55#ibcon#*mode == 0, iclass 14, count 0 2006.201.02:31:01.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.02:31:01.55#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:31:01.55#ibcon#*before write, iclass 14, count 0 2006.201.02:31:01.55#ibcon#enter sib2, iclass 14, count 0 2006.201.02:31:01.55#ibcon#flushed, iclass 14, count 0 2006.201.02:31:01.55#ibcon#about to write, iclass 14, count 0 2006.201.02:31:01.55#ibcon#wrote, iclass 14, count 0 2006.201.02:31:01.55#ibcon#about to read 3, iclass 14, count 0 2006.201.02:31:01.59#ibcon#read 3, iclass 14, count 0 2006.201.02:31:01.59#ibcon#about to read 4, iclass 14, count 0 2006.201.02:31:01.59#ibcon#read 4, iclass 14, count 0 2006.201.02:31:01.59#ibcon#about to read 5, iclass 14, count 0 2006.201.02:31:01.59#ibcon#read 5, iclass 14, count 0 2006.201.02:31:01.59#ibcon#about to read 6, iclass 14, count 0 2006.201.02:31:01.59#ibcon#read 6, iclass 14, count 0 2006.201.02:31:01.59#ibcon#end of sib2, iclass 14, count 0 2006.201.02:31:01.59#ibcon#*after write, iclass 14, count 0 2006.201.02:31:01.59#ibcon#*before return 0, iclass 14, count 0 2006.201.02:31:01.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:31:01.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.02:31:01.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.02:31:01.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.02:31:01.59$vck44/vb=6,4 2006.201.02:31:01.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.02:31:01.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.02:31:01.59#ibcon#ireg 11 cls_cnt 2 2006.201.02:31:01.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:31:01.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:31:01.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:31:01.65#ibcon#enter wrdev, iclass 16, count 2 2006.201.02:31:01.65#ibcon#first serial, iclass 16, count 2 2006.201.02:31:01.65#ibcon#enter sib2, iclass 16, count 2 2006.201.02:31:01.65#ibcon#flushed, iclass 16, count 2 2006.201.02:31:01.65#ibcon#about to write, iclass 16, count 2 2006.201.02:31:01.65#ibcon#wrote, iclass 16, count 2 2006.201.02:31:01.65#ibcon#about to read 3, iclass 16, count 2 2006.201.02:31:01.67#ibcon#read 3, iclass 16, count 2 2006.201.02:31:01.67#ibcon#about to read 4, iclass 16, count 2 2006.201.02:31:01.67#ibcon#read 4, iclass 16, count 2 2006.201.02:31:01.67#ibcon#about to read 5, iclass 16, count 2 2006.201.02:31:01.67#ibcon#read 5, iclass 16, count 2 2006.201.02:31:01.67#ibcon#about to read 6, iclass 16, count 2 2006.201.02:31:01.67#ibcon#read 6, iclass 16, count 2 2006.201.02:31:01.67#ibcon#end of sib2, iclass 16, count 2 2006.201.02:31:01.67#ibcon#*mode == 0, iclass 16, count 2 2006.201.02:31:01.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.02:31:01.67#ibcon#[27=AT06-04\r\n] 2006.201.02:31:01.67#ibcon#*before write, iclass 16, count 2 2006.201.02:31:01.67#ibcon#enter sib2, iclass 16, count 2 2006.201.02:31:01.67#ibcon#flushed, iclass 16, count 2 2006.201.02:31:01.67#ibcon#about to write, iclass 16, count 2 2006.201.02:31:01.67#ibcon#wrote, iclass 16, count 2 2006.201.02:31:01.67#ibcon#about to read 3, iclass 16, count 2 2006.201.02:31:01.70#ibcon#read 3, iclass 16, count 2 2006.201.02:31:01.70#ibcon#about to read 4, iclass 16, count 2 2006.201.02:31:01.70#ibcon#read 4, iclass 16, count 2 2006.201.02:31:01.70#ibcon#about to read 5, iclass 16, count 2 2006.201.02:31:01.70#ibcon#read 5, iclass 16, count 2 2006.201.02:31:01.70#ibcon#about to read 6, iclass 16, count 2 2006.201.02:31:01.70#ibcon#read 6, iclass 16, count 2 2006.201.02:31:01.70#ibcon#end of sib2, iclass 16, count 2 2006.201.02:31:01.70#ibcon#*after write, iclass 16, count 2 2006.201.02:31:01.70#ibcon#*before return 0, iclass 16, count 2 2006.201.02:31:01.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:31:01.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.02:31:01.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.02:31:01.70#ibcon#ireg 7 cls_cnt 0 2006.201.02:31:01.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:31:01.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:31:01.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:31:01.82#ibcon#enter wrdev, iclass 16, count 0 2006.201.02:31:01.82#ibcon#first serial, iclass 16, count 0 2006.201.02:31:01.82#ibcon#enter sib2, iclass 16, count 0 2006.201.02:31:01.82#ibcon#flushed, iclass 16, count 0 2006.201.02:31:01.82#ibcon#about to write, iclass 16, count 0 2006.201.02:31:01.82#ibcon#wrote, iclass 16, count 0 2006.201.02:31:01.82#ibcon#about to read 3, iclass 16, count 0 2006.201.02:31:01.84#ibcon#read 3, iclass 16, count 0 2006.201.02:31:01.84#ibcon#about to read 4, iclass 16, count 0 2006.201.02:31:01.84#ibcon#read 4, iclass 16, count 0 2006.201.02:31:01.84#ibcon#about to read 5, iclass 16, count 0 2006.201.02:31:01.84#ibcon#read 5, iclass 16, count 0 2006.201.02:31:01.84#ibcon#about to read 6, iclass 16, count 0 2006.201.02:31:01.84#ibcon#read 6, iclass 16, count 0 2006.201.02:31:01.84#ibcon#end of sib2, iclass 16, count 0 2006.201.02:31:01.84#ibcon#*mode == 0, iclass 16, count 0 2006.201.02:31:01.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.02:31:01.84#ibcon#[27=USB\r\n] 2006.201.02:31:01.84#ibcon#*before write, iclass 16, count 0 2006.201.02:31:01.84#ibcon#enter sib2, iclass 16, count 0 2006.201.02:31:01.84#ibcon#flushed, iclass 16, count 0 2006.201.02:31:01.84#ibcon#about to write, iclass 16, count 0 2006.201.02:31:01.84#ibcon#wrote, iclass 16, count 0 2006.201.02:31:01.84#ibcon#about to read 3, iclass 16, count 0 2006.201.02:31:01.87#ibcon#read 3, iclass 16, count 0 2006.201.02:31:01.87#ibcon#about to read 4, iclass 16, count 0 2006.201.02:31:01.87#ibcon#read 4, iclass 16, count 0 2006.201.02:31:01.87#ibcon#about to read 5, iclass 16, count 0 2006.201.02:31:01.87#ibcon#read 5, iclass 16, count 0 2006.201.02:31:01.87#ibcon#about to read 6, iclass 16, count 0 2006.201.02:31:01.87#ibcon#read 6, iclass 16, count 0 2006.201.02:31:01.87#ibcon#end of sib2, iclass 16, count 0 2006.201.02:31:01.87#ibcon#*after write, iclass 16, count 0 2006.201.02:31:01.87#ibcon#*before return 0, iclass 16, count 0 2006.201.02:31:01.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:31:01.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.02:31:01.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.02:31:01.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.02:31:01.87$vck44/vblo=7,734.99 2006.201.02:31:01.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.02:31:01.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.02:31:01.87#ibcon#ireg 17 cls_cnt 0 2006.201.02:31:01.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:31:01.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:31:01.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:31:01.87#ibcon#enter wrdev, iclass 18, count 0 2006.201.02:31:01.87#ibcon#first serial, iclass 18, count 0 2006.201.02:31:01.87#ibcon#enter sib2, iclass 18, count 0 2006.201.02:31:01.87#ibcon#flushed, iclass 18, count 0 2006.201.02:31:01.87#ibcon#about to write, iclass 18, count 0 2006.201.02:31:01.87#ibcon#wrote, iclass 18, count 0 2006.201.02:31:01.87#ibcon#about to read 3, iclass 18, count 0 2006.201.02:31:01.89#ibcon#read 3, iclass 18, count 0 2006.201.02:31:01.89#ibcon#about to read 4, iclass 18, count 0 2006.201.02:31:01.89#ibcon#read 4, iclass 18, count 0 2006.201.02:31:01.89#ibcon#about to read 5, iclass 18, count 0 2006.201.02:31:01.89#ibcon#read 5, iclass 18, count 0 2006.201.02:31:01.89#ibcon#about to read 6, iclass 18, count 0 2006.201.02:31:01.89#ibcon#read 6, iclass 18, count 0 2006.201.02:31:01.89#ibcon#end of sib2, iclass 18, count 0 2006.201.02:31:01.89#ibcon#*mode == 0, iclass 18, count 0 2006.201.02:31:01.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.02:31:01.89#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:31:01.89#ibcon#*before write, iclass 18, count 0 2006.201.02:31:01.89#ibcon#enter sib2, iclass 18, count 0 2006.201.02:31:01.89#ibcon#flushed, iclass 18, count 0 2006.201.02:31:01.89#ibcon#about to write, iclass 18, count 0 2006.201.02:31:01.89#ibcon#wrote, iclass 18, count 0 2006.201.02:31:01.89#ibcon#about to read 3, iclass 18, count 0 2006.201.02:31:01.93#ibcon#read 3, iclass 18, count 0 2006.201.02:31:01.93#ibcon#about to read 4, iclass 18, count 0 2006.201.02:31:01.93#ibcon#read 4, iclass 18, count 0 2006.201.02:31:01.93#ibcon#about to read 5, iclass 18, count 0 2006.201.02:31:01.93#ibcon#read 5, iclass 18, count 0 2006.201.02:31:01.93#ibcon#about to read 6, iclass 18, count 0 2006.201.02:31:01.93#ibcon#read 6, iclass 18, count 0 2006.201.02:31:01.93#ibcon#end of sib2, iclass 18, count 0 2006.201.02:31:01.93#ibcon#*after write, iclass 18, count 0 2006.201.02:31:01.93#ibcon#*before return 0, iclass 18, count 0 2006.201.02:31:01.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:31:01.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.02:31:01.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.02:31:01.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.02:31:01.93$vck44/vb=7,4 2006.201.02:31:01.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.02:31:01.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.02:31:01.93#ibcon#ireg 11 cls_cnt 2 2006.201.02:31:01.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:31:01.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:31:01.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:31:01.99#ibcon#enter wrdev, iclass 20, count 2 2006.201.02:31:01.99#ibcon#first serial, iclass 20, count 2 2006.201.02:31:01.99#ibcon#enter sib2, iclass 20, count 2 2006.201.02:31:01.99#ibcon#flushed, iclass 20, count 2 2006.201.02:31:01.99#ibcon#about to write, iclass 20, count 2 2006.201.02:31:01.99#ibcon#wrote, iclass 20, count 2 2006.201.02:31:01.99#ibcon#about to read 3, iclass 20, count 2 2006.201.02:31:02.01#ibcon#read 3, iclass 20, count 2 2006.201.02:31:02.01#ibcon#about to read 4, iclass 20, count 2 2006.201.02:31:02.01#ibcon#read 4, iclass 20, count 2 2006.201.02:31:02.01#ibcon#about to read 5, iclass 20, count 2 2006.201.02:31:02.01#ibcon#read 5, iclass 20, count 2 2006.201.02:31:02.01#ibcon#about to read 6, iclass 20, count 2 2006.201.02:31:02.01#ibcon#read 6, iclass 20, count 2 2006.201.02:31:02.01#ibcon#end of sib2, iclass 20, count 2 2006.201.02:31:02.01#ibcon#*mode == 0, iclass 20, count 2 2006.201.02:31:02.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.02:31:02.01#ibcon#[27=AT07-04\r\n] 2006.201.02:31:02.01#ibcon#*before write, iclass 20, count 2 2006.201.02:31:02.01#ibcon#enter sib2, iclass 20, count 2 2006.201.02:31:02.01#ibcon#flushed, iclass 20, count 2 2006.201.02:31:02.01#ibcon#about to write, iclass 20, count 2 2006.201.02:31:02.01#ibcon#wrote, iclass 20, count 2 2006.201.02:31:02.01#ibcon#about to read 3, iclass 20, count 2 2006.201.02:31:02.04#ibcon#read 3, iclass 20, count 2 2006.201.02:31:02.04#ibcon#about to read 4, iclass 20, count 2 2006.201.02:31:02.04#ibcon#read 4, iclass 20, count 2 2006.201.02:31:02.04#ibcon#about to read 5, iclass 20, count 2 2006.201.02:31:02.04#ibcon#read 5, iclass 20, count 2 2006.201.02:31:02.04#ibcon#about to read 6, iclass 20, count 2 2006.201.02:31:02.04#ibcon#read 6, iclass 20, count 2 2006.201.02:31:02.04#ibcon#end of sib2, iclass 20, count 2 2006.201.02:31:02.04#ibcon#*after write, iclass 20, count 2 2006.201.02:31:02.04#ibcon#*before return 0, iclass 20, count 2 2006.201.02:31:02.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:31:02.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.02:31:02.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.02:31:02.04#ibcon#ireg 7 cls_cnt 0 2006.201.02:31:02.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:31:02.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:31:02.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:31:02.16#ibcon#enter wrdev, iclass 20, count 0 2006.201.02:31:02.16#ibcon#first serial, iclass 20, count 0 2006.201.02:31:02.16#ibcon#enter sib2, iclass 20, count 0 2006.201.02:31:02.16#ibcon#flushed, iclass 20, count 0 2006.201.02:31:02.16#ibcon#about to write, iclass 20, count 0 2006.201.02:31:02.16#ibcon#wrote, iclass 20, count 0 2006.201.02:31:02.16#ibcon#about to read 3, iclass 20, count 0 2006.201.02:31:02.19#ibcon#read 3, iclass 20, count 0 2006.201.02:31:02.19#ibcon#about to read 4, iclass 20, count 0 2006.201.02:31:02.19#ibcon#read 4, iclass 20, count 0 2006.201.02:31:02.19#ibcon#about to read 5, iclass 20, count 0 2006.201.02:31:02.19#ibcon#read 5, iclass 20, count 0 2006.201.02:31:02.19#ibcon#about to read 6, iclass 20, count 0 2006.201.02:31:02.19#ibcon#read 6, iclass 20, count 0 2006.201.02:31:02.19#ibcon#end of sib2, iclass 20, count 0 2006.201.02:31:02.19#ibcon#*mode == 0, iclass 20, count 0 2006.201.02:31:02.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.02:31:02.19#ibcon#[27=USB\r\n] 2006.201.02:31:02.19#ibcon#*before write, iclass 20, count 0 2006.201.02:31:02.19#ibcon#enter sib2, iclass 20, count 0 2006.201.02:31:02.19#ibcon#flushed, iclass 20, count 0 2006.201.02:31:02.19#ibcon#about to write, iclass 20, count 0 2006.201.02:31:02.19#ibcon#wrote, iclass 20, count 0 2006.201.02:31:02.19#ibcon#about to read 3, iclass 20, count 0 2006.201.02:31:02.22#ibcon#read 3, iclass 20, count 0 2006.201.02:31:02.22#ibcon#about to read 4, iclass 20, count 0 2006.201.02:31:02.22#ibcon#read 4, iclass 20, count 0 2006.201.02:31:02.22#ibcon#about to read 5, iclass 20, count 0 2006.201.02:31:02.22#ibcon#read 5, iclass 20, count 0 2006.201.02:31:02.22#ibcon#about to read 6, iclass 20, count 0 2006.201.02:31:02.22#ibcon#read 6, iclass 20, count 0 2006.201.02:31:02.22#ibcon#end of sib2, iclass 20, count 0 2006.201.02:31:02.22#ibcon#*after write, iclass 20, count 0 2006.201.02:31:02.22#ibcon#*before return 0, iclass 20, count 0 2006.201.02:31:02.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:31:02.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.02:31:02.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.02:31:02.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.02:31:02.22$vck44/vblo=8,744.99 2006.201.02:31:02.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.02:31:02.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.02:31:02.22#ibcon#ireg 17 cls_cnt 0 2006.201.02:31:02.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:31:02.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:31:02.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:31:02.22#ibcon#enter wrdev, iclass 22, count 0 2006.201.02:31:02.22#ibcon#first serial, iclass 22, count 0 2006.201.02:31:02.22#ibcon#enter sib2, iclass 22, count 0 2006.201.02:31:02.22#ibcon#flushed, iclass 22, count 0 2006.201.02:31:02.22#ibcon#about to write, iclass 22, count 0 2006.201.02:31:02.22#ibcon#wrote, iclass 22, count 0 2006.201.02:31:02.22#ibcon#about to read 3, iclass 22, count 0 2006.201.02:31:02.24#ibcon#read 3, iclass 22, count 0 2006.201.02:31:02.24#ibcon#about to read 4, iclass 22, count 0 2006.201.02:31:02.24#ibcon#read 4, iclass 22, count 0 2006.201.02:31:02.24#ibcon#about to read 5, iclass 22, count 0 2006.201.02:31:02.24#ibcon#read 5, iclass 22, count 0 2006.201.02:31:02.24#ibcon#about to read 6, iclass 22, count 0 2006.201.02:31:02.24#ibcon#read 6, iclass 22, count 0 2006.201.02:31:02.24#ibcon#end of sib2, iclass 22, count 0 2006.201.02:31:02.24#ibcon#*mode == 0, iclass 22, count 0 2006.201.02:31:02.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.02:31:02.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:31:02.24#ibcon#*before write, iclass 22, count 0 2006.201.02:31:02.24#ibcon#enter sib2, iclass 22, count 0 2006.201.02:31:02.24#ibcon#flushed, iclass 22, count 0 2006.201.02:31:02.24#ibcon#about to write, iclass 22, count 0 2006.201.02:31:02.24#ibcon#wrote, iclass 22, count 0 2006.201.02:31:02.24#ibcon#about to read 3, iclass 22, count 0 2006.201.02:31:02.28#ibcon#read 3, iclass 22, count 0 2006.201.02:31:02.28#ibcon#about to read 4, iclass 22, count 0 2006.201.02:31:02.28#ibcon#read 4, iclass 22, count 0 2006.201.02:31:02.28#ibcon#about to read 5, iclass 22, count 0 2006.201.02:31:02.28#ibcon#read 5, iclass 22, count 0 2006.201.02:31:02.28#ibcon#about to read 6, iclass 22, count 0 2006.201.02:31:02.28#ibcon#read 6, iclass 22, count 0 2006.201.02:31:02.28#ibcon#end of sib2, iclass 22, count 0 2006.201.02:31:02.28#ibcon#*after write, iclass 22, count 0 2006.201.02:31:02.28#ibcon#*before return 0, iclass 22, count 0 2006.201.02:31:02.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:31:02.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.02:31:02.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.02:31:02.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.02:31:02.28$vck44/vb=8,4 2006.201.02:31:02.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.02:31:02.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.02:31:02.28#ibcon#ireg 11 cls_cnt 2 2006.201.02:31:02.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:31:02.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:31:02.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:31:02.34#ibcon#enter wrdev, iclass 24, count 2 2006.201.02:31:02.34#ibcon#first serial, iclass 24, count 2 2006.201.02:31:02.34#ibcon#enter sib2, iclass 24, count 2 2006.201.02:31:02.34#ibcon#flushed, iclass 24, count 2 2006.201.02:31:02.34#ibcon#about to write, iclass 24, count 2 2006.201.02:31:02.34#ibcon#wrote, iclass 24, count 2 2006.201.02:31:02.34#ibcon#about to read 3, iclass 24, count 2 2006.201.02:31:02.36#ibcon#read 3, iclass 24, count 2 2006.201.02:31:02.36#ibcon#about to read 4, iclass 24, count 2 2006.201.02:31:02.36#ibcon#read 4, iclass 24, count 2 2006.201.02:31:02.36#ibcon#about to read 5, iclass 24, count 2 2006.201.02:31:02.36#ibcon#read 5, iclass 24, count 2 2006.201.02:31:02.36#ibcon#about to read 6, iclass 24, count 2 2006.201.02:31:02.36#ibcon#read 6, iclass 24, count 2 2006.201.02:31:02.36#ibcon#end of sib2, iclass 24, count 2 2006.201.02:31:02.36#ibcon#*mode == 0, iclass 24, count 2 2006.201.02:31:02.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.02:31:02.36#ibcon#[27=AT08-04\r\n] 2006.201.02:31:02.36#ibcon#*before write, iclass 24, count 2 2006.201.02:31:02.36#ibcon#enter sib2, iclass 24, count 2 2006.201.02:31:02.36#ibcon#flushed, iclass 24, count 2 2006.201.02:31:02.36#ibcon#about to write, iclass 24, count 2 2006.201.02:31:02.36#ibcon#wrote, iclass 24, count 2 2006.201.02:31:02.36#ibcon#about to read 3, iclass 24, count 2 2006.201.02:31:02.39#ibcon#read 3, iclass 24, count 2 2006.201.02:31:02.39#ibcon#about to read 4, iclass 24, count 2 2006.201.02:31:02.39#ibcon#read 4, iclass 24, count 2 2006.201.02:31:02.39#ibcon#about to read 5, iclass 24, count 2 2006.201.02:31:02.39#ibcon#read 5, iclass 24, count 2 2006.201.02:31:02.39#ibcon#about to read 6, iclass 24, count 2 2006.201.02:31:02.39#ibcon#read 6, iclass 24, count 2 2006.201.02:31:02.39#ibcon#end of sib2, iclass 24, count 2 2006.201.02:31:02.39#ibcon#*after write, iclass 24, count 2 2006.201.02:31:02.39#ibcon#*before return 0, iclass 24, count 2 2006.201.02:31:02.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:31:02.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.02:31:02.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.02:31:02.39#ibcon#ireg 7 cls_cnt 0 2006.201.02:31:02.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:31:02.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:31:02.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:31:02.51#ibcon#enter wrdev, iclass 24, count 0 2006.201.02:31:02.51#ibcon#first serial, iclass 24, count 0 2006.201.02:31:02.51#ibcon#enter sib2, iclass 24, count 0 2006.201.02:31:02.51#ibcon#flushed, iclass 24, count 0 2006.201.02:31:02.51#ibcon#about to write, iclass 24, count 0 2006.201.02:31:02.51#ibcon#wrote, iclass 24, count 0 2006.201.02:31:02.51#ibcon#about to read 3, iclass 24, count 0 2006.201.02:31:02.53#ibcon#read 3, iclass 24, count 0 2006.201.02:31:02.53#ibcon#about to read 4, iclass 24, count 0 2006.201.02:31:02.53#ibcon#read 4, iclass 24, count 0 2006.201.02:31:02.53#ibcon#about to read 5, iclass 24, count 0 2006.201.02:31:02.53#ibcon#read 5, iclass 24, count 0 2006.201.02:31:02.53#ibcon#about to read 6, iclass 24, count 0 2006.201.02:31:02.53#ibcon#read 6, iclass 24, count 0 2006.201.02:31:02.53#ibcon#end of sib2, iclass 24, count 0 2006.201.02:31:02.53#ibcon#*mode == 0, iclass 24, count 0 2006.201.02:31:02.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.02:31:02.53#ibcon#[27=USB\r\n] 2006.201.02:31:02.53#ibcon#*before write, iclass 24, count 0 2006.201.02:31:02.53#ibcon#enter sib2, iclass 24, count 0 2006.201.02:31:02.53#ibcon#flushed, iclass 24, count 0 2006.201.02:31:02.53#ibcon#about to write, iclass 24, count 0 2006.201.02:31:02.53#ibcon#wrote, iclass 24, count 0 2006.201.02:31:02.53#ibcon#about to read 3, iclass 24, count 0 2006.201.02:31:02.56#ibcon#read 3, iclass 24, count 0 2006.201.02:31:02.56#ibcon#about to read 4, iclass 24, count 0 2006.201.02:31:02.56#ibcon#read 4, iclass 24, count 0 2006.201.02:31:02.56#ibcon#about to read 5, iclass 24, count 0 2006.201.02:31:02.56#ibcon#read 5, iclass 24, count 0 2006.201.02:31:02.56#ibcon#about to read 6, iclass 24, count 0 2006.201.02:31:02.56#ibcon#read 6, iclass 24, count 0 2006.201.02:31:02.56#ibcon#end of sib2, iclass 24, count 0 2006.201.02:31:02.56#ibcon#*after write, iclass 24, count 0 2006.201.02:31:02.56#ibcon#*before return 0, iclass 24, count 0 2006.201.02:31:02.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:31:02.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.02:31:02.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.02:31:02.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.02:31:02.56$vck44/vabw=wide 2006.201.02:31:02.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.02:31:02.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.02:31:02.56#ibcon#ireg 8 cls_cnt 0 2006.201.02:31:02.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:31:02.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:31:02.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:31:02.56#ibcon#enter wrdev, iclass 26, count 0 2006.201.02:31:02.56#ibcon#first serial, iclass 26, count 0 2006.201.02:31:02.56#ibcon#enter sib2, iclass 26, count 0 2006.201.02:31:02.56#ibcon#flushed, iclass 26, count 0 2006.201.02:31:02.56#ibcon#about to write, iclass 26, count 0 2006.201.02:31:02.56#ibcon#wrote, iclass 26, count 0 2006.201.02:31:02.56#ibcon#about to read 3, iclass 26, count 0 2006.201.02:31:02.58#ibcon#read 3, iclass 26, count 0 2006.201.02:31:02.58#ibcon#about to read 4, iclass 26, count 0 2006.201.02:31:02.58#ibcon#read 4, iclass 26, count 0 2006.201.02:31:02.58#ibcon#about to read 5, iclass 26, count 0 2006.201.02:31:02.58#ibcon#read 5, iclass 26, count 0 2006.201.02:31:02.58#ibcon#about to read 6, iclass 26, count 0 2006.201.02:31:02.58#ibcon#read 6, iclass 26, count 0 2006.201.02:31:02.58#ibcon#end of sib2, iclass 26, count 0 2006.201.02:31:02.58#ibcon#*mode == 0, iclass 26, count 0 2006.201.02:31:02.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.02:31:02.58#ibcon#[25=BW32\r\n] 2006.201.02:31:02.58#ibcon#*before write, iclass 26, count 0 2006.201.02:31:02.58#ibcon#enter sib2, iclass 26, count 0 2006.201.02:31:02.58#ibcon#flushed, iclass 26, count 0 2006.201.02:31:02.58#ibcon#about to write, iclass 26, count 0 2006.201.02:31:02.58#ibcon#wrote, iclass 26, count 0 2006.201.02:31:02.58#ibcon#about to read 3, iclass 26, count 0 2006.201.02:31:02.61#ibcon#read 3, iclass 26, count 0 2006.201.02:31:02.61#ibcon#about to read 4, iclass 26, count 0 2006.201.02:31:02.61#ibcon#read 4, iclass 26, count 0 2006.201.02:31:02.61#ibcon#about to read 5, iclass 26, count 0 2006.201.02:31:02.61#ibcon#read 5, iclass 26, count 0 2006.201.02:31:02.61#ibcon#about to read 6, iclass 26, count 0 2006.201.02:31:02.61#ibcon#read 6, iclass 26, count 0 2006.201.02:31:02.61#ibcon#end of sib2, iclass 26, count 0 2006.201.02:31:02.61#ibcon#*after write, iclass 26, count 0 2006.201.02:31:02.61#ibcon#*before return 0, iclass 26, count 0 2006.201.02:31:02.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:31:02.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.02:31:02.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.02:31:02.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.02:31:02.61$vck44/vbbw=wide 2006.201.02:31:02.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.02:31:02.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.02:31:02.61#ibcon#ireg 8 cls_cnt 0 2006.201.02:31:02.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:31:02.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:31:02.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:31:02.68#ibcon#enter wrdev, iclass 28, count 0 2006.201.02:31:02.68#ibcon#first serial, iclass 28, count 0 2006.201.02:31:02.68#ibcon#enter sib2, iclass 28, count 0 2006.201.02:31:02.68#ibcon#flushed, iclass 28, count 0 2006.201.02:31:02.68#ibcon#about to write, iclass 28, count 0 2006.201.02:31:02.68#ibcon#wrote, iclass 28, count 0 2006.201.02:31:02.68#ibcon#about to read 3, iclass 28, count 0 2006.201.02:31:02.70#ibcon#read 3, iclass 28, count 0 2006.201.02:31:02.70#ibcon#about to read 4, iclass 28, count 0 2006.201.02:31:02.70#ibcon#read 4, iclass 28, count 0 2006.201.02:31:02.70#ibcon#about to read 5, iclass 28, count 0 2006.201.02:31:02.70#ibcon#read 5, iclass 28, count 0 2006.201.02:31:02.70#ibcon#about to read 6, iclass 28, count 0 2006.201.02:31:02.70#ibcon#read 6, iclass 28, count 0 2006.201.02:31:02.70#ibcon#end of sib2, iclass 28, count 0 2006.201.02:31:02.70#ibcon#*mode == 0, iclass 28, count 0 2006.201.02:31:02.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.02:31:02.70#ibcon#[27=BW32\r\n] 2006.201.02:31:02.70#ibcon#*before write, iclass 28, count 0 2006.201.02:31:02.70#ibcon#enter sib2, iclass 28, count 0 2006.201.02:31:02.70#ibcon#flushed, iclass 28, count 0 2006.201.02:31:02.70#ibcon#about to write, iclass 28, count 0 2006.201.02:31:02.70#ibcon#wrote, iclass 28, count 0 2006.201.02:31:02.70#ibcon#about to read 3, iclass 28, count 0 2006.201.02:31:02.73#ibcon#read 3, iclass 28, count 0 2006.201.02:31:02.73#ibcon#about to read 4, iclass 28, count 0 2006.201.02:31:02.73#ibcon#read 4, iclass 28, count 0 2006.201.02:31:02.73#ibcon#about to read 5, iclass 28, count 0 2006.201.02:31:02.73#ibcon#read 5, iclass 28, count 0 2006.201.02:31:02.73#ibcon#about to read 6, iclass 28, count 0 2006.201.02:31:02.73#ibcon#read 6, iclass 28, count 0 2006.201.02:31:02.73#ibcon#end of sib2, iclass 28, count 0 2006.201.02:31:02.73#ibcon#*after write, iclass 28, count 0 2006.201.02:31:02.73#ibcon#*before return 0, iclass 28, count 0 2006.201.02:31:02.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:31:02.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:31:02.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.02:31:02.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.02:31:02.73$setupk4/ifdk4 2006.201.02:31:02.73$ifdk4/lo= 2006.201.02:31:02.73$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:31:02.73$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:31:02.73$ifdk4/patch= 2006.201.02:31:02.73$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:31:02.73$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:31:02.73$setupk4/!*+20s 2006.201.02:31:05.57#abcon#<5=/04 2.8 5.6 22.98 921004.8\r\n> 2006.201.02:31:05.59#abcon#{5=INTERFACE CLEAR} 2006.201.02:31:05.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:31:15.74#abcon#<5=/04 2.8 5.6 22.98 921004.8\r\n> 2006.201.02:31:15.76#abcon#{5=INTERFACE CLEAR} 2006.201.02:31:15.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:31:17.17$setupk4/"tpicd 2006.201.02:31:17.17$setupk4/echo=off 2006.201.02:31:17.17$setupk4/xlog=off 2006.201.02:31:17.17:!2006.201.02:33:21 2006.201.02:31:39.13#trakl#Source acquired 2006.201.02:31:40.13#flagr#flagr/antenna,acquired 2006.201.02:33:21.00:preob 2006.201.02:33:21.14/onsource/TRACKING 2006.201.02:33:21.14:!2006.201.02:33:31 2006.201.02:33:31.00:"tape 2006.201.02:33:31.00:"st=record 2006.201.02:33:31.00:data_valid=on 2006.201.02:33:31.00:midob 2006.201.02:33:31.14/onsource/TRACKING 2006.201.02:33:31.14/wx/22.97,1004.8,91 2006.201.02:33:31.23/cable/+6.4668E-03 2006.201.02:33:32.32/va/01,08,usb,yes,28,30 2006.201.02:33:32.32/va/02,07,usb,yes,30,30 2006.201.02:33:32.32/va/03,08,usb,yes,27,28 2006.201.02:33:32.32/va/04,07,usb,yes,31,32 2006.201.02:33:32.32/va/05,04,usb,yes,27,28 2006.201.02:33:32.32/va/06,05,usb,yes,27,27 2006.201.02:33:32.32/va/07,05,usb,yes,26,27 2006.201.02:33:32.32/va/08,04,usb,yes,26,32 2006.201.02:33:32.55/valo/01,524.99,yes,locked 2006.201.02:33:32.55/valo/02,534.99,yes,locked 2006.201.02:33:32.55/valo/03,564.99,yes,locked 2006.201.02:33:32.55/valo/04,624.99,yes,locked 2006.201.02:33:32.55/valo/05,734.99,yes,locked 2006.201.02:33:32.55/valo/06,814.99,yes,locked 2006.201.02:33:32.55/valo/07,864.99,yes,locked 2006.201.02:33:32.55/valo/08,884.99,yes,locked 2006.201.02:33:33.64/vb/01,04,usb,yes,28,26 2006.201.02:33:33.64/vb/02,05,usb,yes,27,27 2006.201.02:33:33.64/vb/03,04,usb,yes,28,31 2006.201.02:33:33.64/vb/04,05,usb,yes,28,27 2006.201.02:33:33.64/vb/05,04,usb,yes,25,27 2006.201.02:33:33.64/vb/06,04,usb,yes,29,25 2006.201.02:33:33.64/vb/07,04,usb,yes,29,29 2006.201.02:33:33.64/vb/08,04,usb,yes,26,30 2006.201.02:33:33.87/vblo/01,629.99,yes,locked 2006.201.02:33:33.87/vblo/02,634.99,yes,locked 2006.201.02:33:33.87/vblo/03,649.99,yes,locked 2006.201.02:33:33.87/vblo/04,679.99,yes,locked 2006.201.02:33:33.87/vblo/05,709.99,yes,locked 2006.201.02:33:33.87/vblo/06,719.99,yes,locked 2006.201.02:33:33.87/vblo/07,734.99,yes,locked 2006.201.02:33:33.87/vblo/08,744.99,yes,locked 2006.201.02:33:34.02/vabw/8 2006.201.02:33:34.17/vbbw/8 2006.201.02:33:34.28/xfe/off,on,15.2 2006.201.02:33:34.65/ifatt/23,28,28,28 2006.201.02:33:35.04/fmout-gps/S +4.44E-07 2006.201.02:33:35.11:!2006.201.02:36:41 2006.201.02:36:41.00:data_valid=off 2006.201.02:36:41.00:"et 2006.201.02:36:41.00:!+3s 2006.201.02:36:44.02:"tape 2006.201.02:36:44.02:postob 2006.201.02:36:44.19/cable/+6.4676E-03 2006.201.02:36:44.19/wx/22.95,1004.7,91 2006.201.02:36:44.26/fmout-gps/S +4.44E-07 2006.201.02:36:44.26:scan_name=201-0239,jd0607,220 2006.201.02:36:44.26:source=1044+719,104827.62,714335.9,2000.0,cw 2006.201.02:36:46.14#flagr#flagr/antenna,new-source 2006.201.02:36:46.14:checkk5 2006.201.02:36:46.57/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:36:47.00/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:36:47.41/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:36:47.78/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:36:48.18/chk_obsdata//k5ts1/T2010233??a.dat file size is correct (nominal:760MB, actual:760MB). 2006.201.02:36:48.67/chk_obsdata//k5ts2/T2010233??b.dat file size is correct (nominal:760MB, actual:760MB). 2006.201.02:36:49.11/chk_obsdata//k5ts3/T2010233??c.dat file size is correct (nominal:760MB, actual:760MB). 2006.201.02:36:49.50/chk_obsdata//k5ts4/T2010233??d.dat file size is correct (nominal:760MB, actual:760MB). 2006.201.02:36:50.31/k5log//k5ts1_log_newline 2006.201.02:36:54.08/k5log//k5ts2_log_newline 2006.201.02:36:54.90/k5log//k5ts3_log_newline 2006.201.02:36:55.77/k5log//k5ts4_log_newline 2006.201.02:36:55.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:36:55.80:setupk4=1 2006.201.02:36:55.80$setupk4/echo=on 2006.201.02:36:55.80$setupk4/pcalon 2006.201.02:36:55.80$pcalon/"no phase cal control is implemented here 2006.201.02:36:55.80$setupk4/"tpicd=stop 2006.201.02:36:55.80$setupk4/"rec=synch_on 2006.201.02:36:55.80$setupk4/"rec_mode=128 2006.201.02:36:55.80$setupk4/!* 2006.201.02:36:55.80$setupk4/recpk4 2006.201.02:36:55.80$recpk4/recpatch= 2006.201.02:36:55.80$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:36:55.80$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:36:55.80$setupk4/vck44 2006.201.02:36:55.80$vck44/valo=1,524.99 2006.201.02:36:55.80#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.02:36:55.80#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.02:36:55.80#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:55.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:55.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:55.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:55.80#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:36:55.80#ibcon#first serial, iclass 29, count 0 2006.201.02:36:55.80#ibcon#enter sib2, iclass 29, count 0 2006.201.02:36:55.80#ibcon#flushed, iclass 29, count 0 2006.201.02:36:55.80#ibcon#about to write, iclass 29, count 0 2006.201.02:36:55.80#ibcon#wrote, iclass 29, count 0 2006.201.02:36:55.80#ibcon#about to read 3, iclass 29, count 0 2006.201.02:36:55.84#ibcon#read 3, iclass 29, count 0 2006.201.02:36:55.84#ibcon#about to read 4, iclass 29, count 0 2006.201.02:36:55.84#ibcon#read 4, iclass 29, count 0 2006.201.02:36:55.84#ibcon#about to read 5, iclass 29, count 0 2006.201.02:36:55.84#ibcon#read 5, iclass 29, count 0 2006.201.02:36:55.84#ibcon#about to read 6, iclass 29, count 0 2006.201.02:36:55.84#ibcon#read 6, iclass 29, count 0 2006.201.02:36:55.84#ibcon#end of sib2, iclass 29, count 0 2006.201.02:36:55.84#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:36:55.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:36:55.84#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:36:55.84#ibcon#*before write, iclass 29, count 0 2006.201.02:36:55.84#ibcon#enter sib2, iclass 29, count 0 2006.201.02:36:55.84#ibcon#flushed, iclass 29, count 0 2006.201.02:36:55.84#ibcon#about to write, iclass 29, count 0 2006.201.02:36:55.84#ibcon#wrote, iclass 29, count 0 2006.201.02:36:55.84#ibcon#about to read 3, iclass 29, count 0 2006.201.02:36:55.89#ibcon#read 3, iclass 29, count 0 2006.201.02:36:55.89#ibcon#about to read 4, iclass 29, count 0 2006.201.02:36:55.89#ibcon#read 4, iclass 29, count 0 2006.201.02:36:55.89#ibcon#about to read 5, iclass 29, count 0 2006.201.02:36:55.89#ibcon#read 5, iclass 29, count 0 2006.201.02:36:55.89#ibcon#about to read 6, iclass 29, count 0 2006.201.02:36:55.89#ibcon#read 6, iclass 29, count 0 2006.201.02:36:55.89#ibcon#end of sib2, iclass 29, count 0 2006.201.02:36:55.89#ibcon#*after write, iclass 29, count 0 2006.201.02:36:55.89#ibcon#*before return 0, iclass 29, count 0 2006.201.02:36:55.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:55.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:55.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:36:55.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:36:55.89$vck44/va=1,8 2006.201.02:36:55.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.02:36:55.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.02:36:55.89#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:55.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:55.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:55.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:55.89#ibcon#enter wrdev, iclass 31, count 2 2006.201.02:36:55.89#ibcon#first serial, iclass 31, count 2 2006.201.02:36:55.89#ibcon#enter sib2, iclass 31, count 2 2006.201.02:36:55.89#ibcon#flushed, iclass 31, count 2 2006.201.02:36:55.89#ibcon#about to write, iclass 31, count 2 2006.201.02:36:55.89#ibcon#wrote, iclass 31, count 2 2006.201.02:36:55.89#ibcon#about to read 3, iclass 31, count 2 2006.201.02:36:55.91#ibcon#read 3, iclass 31, count 2 2006.201.02:36:55.91#ibcon#about to read 4, iclass 31, count 2 2006.201.02:36:55.91#ibcon#read 4, iclass 31, count 2 2006.201.02:36:55.91#ibcon#about to read 5, iclass 31, count 2 2006.201.02:36:55.91#ibcon#read 5, iclass 31, count 2 2006.201.02:36:55.91#ibcon#about to read 6, iclass 31, count 2 2006.201.02:36:55.91#ibcon#read 6, iclass 31, count 2 2006.201.02:36:55.91#ibcon#end of sib2, iclass 31, count 2 2006.201.02:36:55.91#ibcon#*mode == 0, iclass 31, count 2 2006.201.02:36:55.91#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.02:36:55.91#ibcon#[25=AT01-08\r\n] 2006.201.02:36:55.91#ibcon#*before write, iclass 31, count 2 2006.201.02:36:55.91#ibcon#enter sib2, iclass 31, count 2 2006.201.02:36:55.91#ibcon#flushed, iclass 31, count 2 2006.201.02:36:55.91#ibcon#about to write, iclass 31, count 2 2006.201.02:36:55.91#ibcon#wrote, iclass 31, count 2 2006.201.02:36:55.91#ibcon#about to read 3, iclass 31, count 2 2006.201.02:36:55.94#ibcon#read 3, iclass 31, count 2 2006.201.02:36:55.94#ibcon#about to read 4, iclass 31, count 2 2006.201.02:36:55.94#ibcon#read 4, iclass 31, count 2 2006.201.02:36:55.94#ibcon#about to read 5, iclass 31, count 2 2006.201.02:36:55.94#ibcon#read 5, iclass 31, count 2 2006.201.02:36:55.94#ibcon#about to read 6, iclass 31, count 2 2006.201.02:36:55.94#ibcon#read 6, iclass 31, count 2 2006.201.02:36:55.94#ibcon#end of sib2, iclass 31, count 2 2006.201.02:36:55.94#ibcon#*after write, iclass 31, count 2 2006.201.02:36:55.94#ibcon#*before return 0, iclass 31, count 2 2006.201.02:36:55.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:55.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:55.94#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.02:36:55.94#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:55.94#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:56.06#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:56.06#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:56.06#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:36:56.06#ibcon#first serial, iclass 31, count 0 2006.201.02:36:56.06#ibcon#enter sib2, iclass 31, count 0 2006.201.02:36:56.06#ibcon#flushed, iclass 31, count 0 2006.201.02:36:56.06#ibcon#about to write, iclass 31, count 0 2006.201.02:36:56.06#ibcon#wrote, iclass 31, count 0 2006.201.02:36:56.06#ibcon#about to read 3, iclass 31, count 0 2006.201.02:36:56.08#ibcon#read 3, iclass 31, count 0 2006.201.02:36:56.08#ibcon#about to read 4, iclass 31, count 0 2006.201.02:36:56.08#ibcon#read 4, iclass 31, count 0 2006.201.02:36:56.08#ibcon#about to read 5, iclass 31, count 0 2006.201.02:36:56.08#ibcon#read 5, iclass 31, count 0 2006.201.02:36:56.08#ibcon#about to read 6, iclass 31, count 0 2006.201.02:36:56.08#ibcon#read 6, iclass 31, count 0 2006.201.02:36:56.08#ibcon#end of sib2, iclass 31, count 0 2006.201.02:36:56.08#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:36:56.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:36:56.08#ibcon#[25=USB\r\n] 2006.201.02:36:56.08#ibcon#*before write, iclass 31, count 0 2006.201.02:36:56.08#ibcon#enter sib2, iclass 31, count 0 2006.201.02:36:56.08#ibcon#flushed, iclass 31, count 0 2006.201.02:36:56.08#ibcon#about to write, iclass 31, count 0 2006.201.02:36:56.08#ibcon#wrote, iclass 31, count 0 2006.201.02:36:56.08#ibcon#about to read 3, iclass 31, count 0 2006.201.02:36:56.11#ibcon#read 3, iclass 31, count 0 2006.201.02:36:56.11#ibcon#about to read 4, iclass 31, count 0 2006.201.02:36:56.11#ibcon#read 4, iclass 31, count 0 2006.201.02:36:56.11#ibcon#about to read 5, iclass 31, count 0 2006.201.02:36:56.11#ibcon#read 5, iclass 31, count 0 2006.201.02:36:56.11#ibcon#about to read 6, iclass 31, count 0 2006.201.02:36:56.11#ibcon#read 6, iclass 31, count 0 2006.201.02:36:56.11#ibcon#end of sib2, iclass 31, count 0 2006.201.02:36:56.11#ibcon#*after write, iclass 31, count 0 2006.201.02:36:56.11#ibcon#*before return 0, iclass 31, count 0 2006.201.02:36:56.11#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:56.11#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:56.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:36:56.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:36:56.11$vck44/valo=2,534.99 2006.201.02:36:56.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.02:36:56.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.02:36:56.11#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:56.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:56.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:56.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:56.11#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:36:56.11#ibcon#first serial, iclass 33, count 0 2006.201.02:36:56.11#ibcon#enter sib2, iclass 33, count 0 2006.201.02:36:56.11#ibcon#flushed, iclass 33, count 0 2006.201.02:36:56.11#ibcon#about to write, iclass 33, count 0 2006.201.02:36:56.11#ibcon#wrote, iclass 33, count 0 2006.201.02:36:56.11#ibcon#about to read 3, iclass 33, count 0 2006.201.02:36:56.13#ibcon#read 3, iclass 33, count 0 2006.201.02:36:56.13#ibcon#about to read 4, iclass 33, count 0 2006.201.02:36:56.13#ibcon#read 4, iclass 33, count 0 2006.201.02:36:56.13#ibcon#about to read 5, iclass 33, count 0 2006.201.02:36:56.13#ibcon#read 5, iclass 33, count 0 2006.201.02:36:56.13#ibcon#about to read 6, iclass 33, count 0 2006.201.02:36:56.13#ibcon#read 6, iclass 33, count 0 2006.201.02:36:56.13#ibcon#end of sib2, iclass 33, count 0 2006.201.02:36:56.13#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:36:56.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:36:56.13#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:36:56.13#ibcon#*before write, iclass 33, count 0 2006.201.02:36:56.13#ibcon#enter sib2, iclass 33, count 0 2006.201.02:36:56.13#ibcon#flushed, iclass 33, count 0 2006.201.02:36:56.13#ibcon#about to write, iclass 33, count 0 2006.201.02:36:56.13#ibcon#wrote, iclass 33, count 0 2006.201.02:36:56.13#ibcon#about to read 3, iclass 33, count 0 2006.201.02:36:56.17#ibcon#read 3, iclass 33, count 0 2006.201.02:36:56.17#ibcon#about to read 4, iclass 33, count 0 2006.201.02:36:56.17#ibcon#read 4, iclass 33, count 0 2006.201.02:36:56.17#ibcon#about to read 5, iclass 33, count 0 2006.201.02:36:56.17#ibcon#read 5, iclass 33, count 0 2006.201.02:36:56.17#ibcon#about to read 6, iclass 33, count 0 2006.201.02:36:56.17#ibcon#read 6, iclass 33, count 0 2006.201.02:36:56.17#ibcon#end of sib2, iclass 33, count 0 2006.201.02:36:56.17#ibcon#*after write, iclass 33, count 0 2006.201.02:36:56.17#ibcon#*before return 0, iclass 33, count 0 2006.201.02:36:56.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:56.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:56.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:36:56.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:36:56.17$vck44/va=2,7 2006.201.02:36:56.17#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.02:36:56.17#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.02:36:56.17#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:56.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:56.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:56.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:56.23#ibcon#enter wrdev, iclass 35, count 2 2006.201.02:36:56.23#ibcon#first serial, iclass 35, count 2 2006.201.02:36:56.23#ibcon#enter sib2, iclass 35, count 2 2006.201.02:36:56.23#ibcon#flushed, iclass 35, count 2 2006.201.02:36:56.23#ibcon#about to write, iclass 35, count 2 2006.201.02:36:56.23#ibcon#wrote, iclass 35, count 2 2006.201.02:36:56.23#ibcon#about to read 3, iclass 35, count 2 2006.201.02:36:56.25#ibcon#read 3, iclass 35, count 2 2006.201.02:36:56.25#ibcon#about to read 4, iclass 35, count 2 2006.201.02:36:56.25#ibcon#read 4, iclass 35, count 2 2006.201.02:36:56.25#ibcon#about to read 5, iclass 35, count 2 2006.201.02:36:56.25#ibcon#read 5, iclass 35, count 2 2006.201.02:36:56.25#ibcon#about to read 6, iclass 35, count 2 2006.201.02:36:56.25#ibcon#read 6, iclass 35, count 2 2006.201.02:36:56.25#ibcon#end of sib2, iclass 35, count 2 2006.201.02:36:56.25#ibcon#*mode == 0, iclass 35, count 2 2006.201.02:36:56.25#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.02:36:56.25#ibcon#[25=AT02-07\r\n] 2006.201.02:36:56.25#ibcon#*before write, iclass 35, count 2 2006.201.02:36:56.25#ibcon#enter sib2, iclass 35, count 2 2006.201.02:36:56.25#ibcon#flushed, iclass 35, count 2 2006.201.02:36:56.25#ibcon#about to write, iclass 35, count 2 2006.201.02:36:56.25#ibcon#wrote, iclass 35, count 2 2006.201.02:36:56.25#ibcon#about to read 3, iclass 35, count 2 2006.201.02:36:56.28#ibcon#read 3, iclass 35, count 2 2006.201.02:36:56.28#ibcon#about to read 4, iclass 35, count 2 2006.201.02:36:56.28#ibcon#read 4, iclass 35, count 2 2006.201.02:36:56.28#ibcon#about to read 5, iclass 35, count 2 2006.201.02:36:56.28#ibcon#read 5, iclass 35, count 2 2006.201.02:36:56.28#ibcon#about to read 6, iclass 35, count 2 2006.201.02:36:56.28#ibcon#read 6, iclass 35, count 2 2006.201.02:36:56.28#ibcon#end of sib2, iclass 35, count 2 2006.201.02:36:56.28#ibcon#*after write, iclass 35, count 2 2006.201.02:36:56.28#ibcon#*before return 0, iclass 35, count 2 2006.201.02:36:56.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:56.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:56.28#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.02:36:56.28#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:56.28#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:56.40#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:56.40#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:56.40#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:36:56.40#ibcon#first serial, iclass 35, count 0 2006.201.02:36:56.40#ibcon#enter sib2, iclass 35, count 0 2006.201.02:36:56.40#ibcon#flushed, iclass 35, count 0 2006.201.02:36:56.40#ibcon#about to write, iclass 35, count 0 2006.201.02:36:56.40#ibcon#wrote, iclass 35, count 0 2006.201.02:36:56.40#ibcon#about to read 3, iclass 35, count 0 2006.201.02:36:56.42#ibcon#read 3, iclass 35, count 0 2006.201.02:36:56.42#ibcon#about to read 4, iclass 35, count 0 2006.201.02:36:56.42#ibcon#read 4, iclass 35, count 0 2006.201.02:36:56.42#ibcon#about to read 5, iclass 35, count 0 2006.201.02:36:56.42#ibcon#read 5, iclass 35, count 0 2006.201.02:36:56.42#ibcon#about to read 6, iclass 35, count 0 2006.201.02:36:56.42#ibcon#read 6, iclass 35, count 0 2006.201.02:36:56.42#ibcon#end of sib2, iclass 35, count 0 2006.201.02:36:56.42#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:36:56.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:36:56.42#ibcon#[25=USB\r\n] 2006.201.02:36:56.42#ibcon#*before write, iclass 35, count 0 2006.201.02:36:56.42#ibcon#enter sib2, iclass 35, count 0 2006.201.02:36:56.42#ibcon#flushed, iclass 35, count 0 2006.201.02:36:56.42#ibcon#about to write, iclass 35, count 0 2006.201.02:36:56.42#ibcon#wrote, iclass 35, count 0 2006.201.02:36:56.42#ibcon#about to read 3, iclass 35, count 0 2006.201.02:36:56.45#ibcon#read 3, iclass 35, count 0 2006.201.02:36:56.45#ibcon#about to read 4, iclass 35, count 0 2006.201.02:36:56.45#ibcon#read 4, iclass 35, count 0 2006.201.02:36:56.45#ibcon#about to read 5, iclass 35, count 0 2006.201.02:36:56.45#ibcon#read 5, iclass 35, count 0 2006.201.02:36:56.45#ibcon#about to read 6, iclass 35, count 0 2006.201.02:36:56.45#ibcon#read 6, iclass 35, count 0 2006.201.02:36:56.45#ibcon#end of sib2, iclass 35, count 0 2006.201.02:36:56.45#ibcon#*after write, iclass 35, count 0 2006.201.02:36:56.45#ibcon#*before return 0, iclass 35, count 0 2006.201.02:36:56.45#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:56.45#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:56.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:36:56.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:36:56.45$vck44/valo=3,564.99 2006.201.02:36:56.45#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.02:36:56.45#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.02:36:56.45#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:56.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:56.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:56.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:56.45#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:36:56.45#ibcon#first serial, iclass 37, count 0 2006.201.02:36:56.45#ibcon#enter sib2, iclass 37, count 0 2006.201.02:36:56.45#ibcon#flushed, iclass 37, count 0 2006.201.02:36:56.45#ibcon#about to write, iclass 37, count 0 2006.201.02:36:56.45#ibcon#wrote, iclass 37, count 0 2006.201.02:36:56.45#ibcon#about to read 3, iclass 37, count 0 2006.201.02:36:56.47#ibcon#read 3, iclass 37, count 0 2006.201.02:36:56.47#ibcon#about to read 4, iclass 37, count 0 2006.201.02:36:56.47#ibcon#read 4, iclass 37, count 0 2006.201.02:36:56.47#ibcon#about to read 5, iclass 37, count 0 2006.201.02:36:56.47#ibcon#read 5, iclass 37, count 0 2006.201.02:36:56.47#ibcon#about to read 6, iclass 37, count 0 2006.201.02:36:56.47#ibcon#read 6, iclass 37, count 0 2006.201.02:36:56.47#ibcon#end of sib2, iclass 37, count 0 2006.201.02:36:56.47#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:36:56.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:36:56.47#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:36:56.47#ibcon#*before write, iclass 37, count 0 2006.201.02:36:56.47#ibcon#enter sib2, iclass 37, count 0 2006.201.02:36:56.47#ibcon#flushed, iclass 37, count 0 2006.201.02:36:56.47#ibcon#about to write, iclass 37, count 0 2006.201.02:36:56.47#ibcon#wrote, iclass 37, count 0 2006.201.02:36:56.47#ibcon#about to read 3, iclass 37, count 0 2006.201.02:36:56.52#ibcon#read 3, iclass 37, count 0 2006.201.02:36:56.52#ibcon#about to read 4, iclass 37, count 0 2006.201.02:36:56.52#ibcon#read 4, iclass 37, count 0 2006.201.02:36:56.52#ibcon#about to read 5, iclass 37, count 0 2006.201.02:36:56.52#ibcon#read 5, iclass 37, count 0 2006.201.02:36:56.52#ibcon#about to read 6, iclass 37, count 0 2006.201.02:36:56.52#ibcon#read 6, iclass 37, count 0 2006.201.02:36:56.52#ibcon#end of sib2, iclass 37, count 0 2006.201.02:36:56.52#ibcon#*after write, iclass 37, count 0 2006.201.02:36:56.52#ibcon#*before return 0, iclass 37, count 0 2006.201.02:36:56.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:56.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:56.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:36:56.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:36:56.52$vck44/va=3,8 2006.201.02:36:56.52#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.02:36:56.52#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.02:36:56.52#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:56.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:56.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:56.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:56.57#ibcon#enter wrdev, iclass 39, count 2 2006.201.02:36:56.57#ibcon#first serial, iclass 39, count 2 2006.201.02:36:56.57#ibcon#enter sib2, iclass 39, count 2 2006.201.02:36:56.57#ibcon#flushed, iclass 39, count 2 2006.201.02:36:56.57#ibcon#about to write, iclass 39, count 2 2006.201.02:36:56.57#ibcon#wrote, iclass 39, count 2 2006.201.02:36:56.57#ibcon#about to read 3, iclass 39, count 2 2006.201.02:36:56.59#ibcon#read 3, iclass 39, count 2 2006.201.02:36:56.59#ibcon#about to read 4, iclass 39, count 2 2006.201.02:36:56.59#ibcon#read 4, iclass 39, count 2 2006.201.02:36:56.59#ibcon#about to read 5, iclass 39, count 2 2006.201.02:36:56.59#ibcon#read 5, iclass 39, count 2 2006.201.02:36:56.59#ibcon#about to read 6, iclass 39, count 2 2006.201.02:36:56.59#ibcon#read 6, iclass 39, count 2 2006.201.02:36:56.59#ibcon#end of sib2, iclass 39, count 2 2006.201.02:36:56.59#ibcon#*mode == 0, iclass 39, count 2 2006.201.02:36:56.59#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.02:36:56.59#ibcon#[25=AT03-08\r\n] 2006.201.02:36:56.59#ibcon#*before write, iclass 39, count 2 2006.201.02:36:56.59#ibcon#enter sib2, iclass 39, count 2 2006.201.02:36:56.59#ibcon#flushed, iclass 39, count 2 2006.201.02:36:56.59#ibcon#about to write, iclass 39, count 2 2006.201.02:36:56.59#ibcon#wrote, iclass 39, count 2 2006.201.02:36:56.59#ibcon#about to read 3, iclass 39, count 2 2006.201.02:36:56.62#ibcon#read 3, iclass 39, count 2 2006.201.02:36:56.62#ibcon#about to read 4, iclass 39, count 2 2006.201.02:36:56.62#ibcon#read 4, iclass 39, count 2 2006.201.02:36:56.62#ibcon#about to read 5, iclass 39, count 2 2006.201.02:36:56.62#ibcon#read 5, iclass 39, count 2 2006.201.02:36:56.62#ibcon#about to read 6, iclass 39, count 2 2006.201.02:36:56.62#ibcon#read 6, iclass 39, count 2 2006.201.02:36:56.62#ibcon#end of sib2, iclass 39, count 2 2006.201.02:36:56.62#ibcon#*after write, iclass 39, count 2 2006.201.02:36:56.62#ibcon#*before return 0, iclass 39, count 2 2006.201.02:36:56.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:56.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:56.62#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.02:36:56.62#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:56.62#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:56.74#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:56.74#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:56.74#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:36:56.74#ibcon#first serial, iclass 39, count 0 2006.201.02:36:56.74#ibcon#enter sib2, iclass 39, count 0 2006.201.02:36:56.74#ibcon#flushed, iclass 39, count 0 2006.201.02:36:56.74#ibcon#about to write, iclass 39, count 0 2006.201.02:36:56.74#ibcon#wrote, iclass 39, count 0 2006.201.02:36:56.74#ibcon#about to read 3, iclass 39, count 0 2006.201.02:36:56.76#ibcon#read 3, iclass 39, count 0 2006.201.02:36:56.76#ibcon#about to read 4, iclass 39, count 0 2006.201.02:36:56.76#ibcon#read 4, iclass 39, count 0 2006.201.02:36:56.76#ibcon#about to read 5, iclass 39, count 0 2006.201.02:36:56.76#ibcon#read 5, iclass 39, count 0 2006.201.02:36:56.76#ibcon#about to read 6, iclass 39, count 0 2006.201.02:36:56.76#ibcon#read 6, iclass 39, count 0 2006.201.02:36:56.76#ibcon#end of sib2, iclass 39, count 0 2006.201.02:36:56.76#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:36:56.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:36:56.76#ibcon#[25=USB\r\n] 2006.201.02:36:56.76#ibcon#*before write, iclass 39, count 0 2006.201.02:36:56.76#ibcon#enter sib2, iclass 39, count 0 2006.201.02:36:56.76#ibcon#flushed, iclass 39, count 0 2006.201.02:36:56.76#ibcon#about to write, iclass 39, count 0 2006.201.02:36:56.76#ibcon#wrote, iclass 39, count 0 2006.201.02:36:56.76#ibcon#about to read 3, iclass 39, count 0 2006.201.02:36:56.79#ibcon#read 3, iclass 39, count 0 2006.201.02:36:56.79#ibcon#about to read 4, iclass 39, count 0 2006.201.02:36:56.79#ibcon#read 4, iclass 39, count 0 2006.201.02:36:56.79#ibcon#about to read 5, iclass 39, count 0 2006.201.02:36:56.79#ibcon#read 5, iclass 39, count 0 2006.201.02:36:56.79#ibcon#about to read 6, iclass 39, count 0 2006.201.02:36:56.79#ibcon#read 6, iclass 39, count 0 2006.201.02:36:56.79#ibcon#end of sib2, iclass 39, count 0 2006.201.02:36:56.79#ibcon#*after write, iclass 39, count 0 2006.201.02:36:56.79#ibcon#*before return 0, iclass 39, count 0 2006.201.02:36:56.79#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:56.79#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:56.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:36:56.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:36:56.79$vck44/valo=4,624.99 2006.201.02:36:56.79#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.02:36:56.79#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.02:36:56.79#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:56.79#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:56.79#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:56.79#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:56.79#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:36:56.79#ibcon#first serial, iclass 2, count 0 2006.201.02:36:56.79#ibcon#enter sib2, iclass 2, count 0 2006.201.02:36:56.79#ibcon#flushed, iclass 2, count 0 2006.201.02:36:56.79#ibcon#about to write, iclass 2, count 0 2006.201.02:36:56.79#ibcon#wrote, iclass 2, count 0 2006.201.02:36:56.79#ibcon#about to read 3, iclass 2, count 0 2006.201.02:36:56.81#ibcon#read 3, iclass 2, count 0 2006.201.02:36:56.81#ibcon#about to read 4, iclass 2, count 0 2006.201.02:36:56.81#ibcon#read 4, iclass 2, count 0 2006.201.02:36:56.81#ibcon#about to read 5, iclass 2, count 0 2006.201.02:36:56.81#ibcon#read 5, iclass 2, count 0 2006.201.02:36:56.81#ibcon#about to read 6, iclass 2, count 0 2006.201.02:36:56.81#ibcon#read 6, iclass 2, count 0 2006.201.02:36:56.81#ibcon#end of sib2, iclass 2, count 0 2006.201.02:36:56.81#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:36:56.81#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:36:56.81#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:36:56.81#ibcon#*before write, iclass 2, count 0 2006.201.02:36:56.81#ibcon#enter sib2, iclass 2, count 0 2006.201.02:36:56.81#ibcon#flushed, iclass 2, count 0 2006.201.02:36:56.81#ibcon#about to write, iclass 2, count 0 2006.201.02:36:56.81#ibcon#wrote, iclass 2, count 0 2006.201.02:36:56.81#ibcon#about to read 3, iclass 2, count 0 2006.201.02:36:56.86#ibcon#read 3, iclass 2, count 0 2006.201.02:36:56.86#ibcon#about to read 4, iclass 2, count 0 2006.201.02:36:56.86#ibcon#read 4, iclass 2, count 0 2006.201.02:36:56.86#ibcon#about to read 5, iclass 2, count 0 2006.201.02:36:56.86#ibcon#read 5, iclass 2, count 0 2006.201.02:36:56.86#ibcon#about to read 6, iclass 2, count 0 2006.201.02:36:56.86#ibcon#read 6, iclass 2, count 0 2006.201.02:36:56.86#ibcon#end of sib2, iclass 2, count 0 2006.201.02:36:56.86#ibcon#*after write, iclass 2, count 0 2006.201.02:36:56.86#ibcon#*before return 0, iclass 2, count 0 2006.201.02:36:56.86#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:56.86#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:56.86#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:36:56.86#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:36:56.86$vck44/va=4,7 2006.201.02:36:56.86#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.02:36:56.86#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.02:36:56.86#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:56.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:56.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:56.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:56.91#ibcon#enter wrdev, iclass 5, count 2 2006.201.02:36:56.91#ibcon#first serial, iclass 5, count 2 2006.201.02:36:56.91#ibcon#enter sib2, iclass 5, count 2 2006.201.02:36:56.91#ibcon#flushed, iclass 5, count 2 2006.201.02:36:56.91#ibcon#about to write, iclass 5, count 2 2006.201.02:36:56.91#ibcon#wrote, iclass 5, count 2 2006.201.02:36:56.91#ibcon#about to read 3, iclass 5, count 2 2006.201.02:36:56.93#ibcon#read 3, iclass 5, count 2 2006.201.02:36:56.93#ibcon#about to read 4, iclass 5, count 2 2006.201.02:36:56.93#ibcon#read 4, iclass 5, count 2 2006.201.02:36:56.93#ibcon#about to read 5, iclass 5, count 2 2006.201.02:36:56.93#ibcon#read 5, iclass 5, count 2 2006.201.02:36:56.93#ibcon#about to read 6, iclass 5, count 2 2006.201.02:36:56.93#ibcon#read 6, iclass 5, count 2 2006.201.02:36:56.93#ibcon#end of sib2, iclass 5, count 2 2006.201.02:36:56.93#ibcon#*mode == 0, iclass 5, count 2 2006.201.02:36:56.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.02:36:56.93#ibcon#[25=AT04-07\r\n] 2006.201.02:36:56.93#ibcon#*before write, iclass 5, count 2 2006.201.02:36:56.93#ibcon#enter sib2, iclass 5, count 2 2006.201.02:36:56.93#ibcon#flushed, iclass 5, count 2 2006.201.02:36:56.93#ibcon#about to write, iclass 5, count 2 2006.201.02:36:56.93#ibcon#wrote, iclass 5, count 2 2006.201.02:36:56.93#ibcon#about to read 3, iclass 5, count 2 2006.201.02:36:56.96#ibcon#read 3, iclass 5, count 2 2006.201.02:36:56.96#ibcon#about to read 4, iclass 5, count 2 2006.201.02:36:56.96#ibcon#read 4, iclass 5, count 2 2006.201.02:36:56.96#ibcon#about to read 5, iclass 5, count 2 2006.201.02:36:56.96#ibcon#read 5, iclass 5, count 2 2006.201.02:36:56.96#ibcon#about to read 6, iclass 5, count 2 2006.201.02:36:56.96#ibcon#read 6, iclass 5, count 2 2006.201.02:36:56.96#ibcon#end of sib2, iclass 5, count 2 2006.201.02:36:56.96#ibcon#*after write, iclass 5, count 2 2006.201.02:36:56.96#ibcon#*before return 0, iclass 5, count 2 2006.201.02:36:56.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:56.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:56.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.02:36:56.96#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:56.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:36:57.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:36:57.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:36:57.08#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:36:57.08#ibcon#first serial, iclass 5, count 0 2006.201.02:36:57.08#ibcon#enter sib2, iclass 5, count 0 2006.201.02:36:57.08#ibcon#flushed, iclass 5, count 0 2006.201.02:36:57.08#ibcon#about to write, iclass 5, count 0 2006.201.02:36:57.08#ibcon#wrote, iclass 5, count 0 2006.201.02:36:57.08#ibcon#about to read 3, iclass 5, count 0 2006.201.02:36:57.10#ibcon#read 3, iclass 5, count 0 2006.201.02:36:57.10#ibcon#about to read 4, iclass 5, count 0 2006.201.02:36:57.10#ibcon#read 4, iclass 5, count 0 2006.201.02:36:57.10#ibcon#about to read 5, iclass 5, count 0 2006.201.02:36:57.10#ibcon#read 5, iclass 5, count 0 2006.201.02:36:57.10#ibcon#about to read 6, iclass 5, count 0 2006.201.02:36:57.10#ibcon#read 6, iclass 5, count 0 2006.201.02:36:57.10#ibcon#end of sib2, iclass 5, count 0 2006.201.02:36:57.10#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:36:57.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:36:57.10#ibcon#[25=USB\r\n] 2006.201.02:36:57.10#ibcon#*before write, iclass 5, count 0 2006.201.02:36:57.10#ibcon#enter sib2, iclass 5, count 0 2006.201.02:36:57.10#ibcon#flushed, iclass 5, count 0 2006.201.02:36:57.10#ibcon#about to write, iclass 5, count 0 2006.201.02:36:57.10#ibcon#wrote, iclass 5, count 0 2006.201.02:36:57.10#ibcon#about to read 3, iclass 5, count 0 2006.201.02:36:57.13#ibcon#read 3, iclass 5, count 0 2006.201.02:36:57.13#ibcon#about to read 4, iclass 5, count 0 2006.201.02:36:57.13#ibcon#read 4, iclass 5, count 0 2006.201.02:36:57.13#ibcon#about to read 5, iclass 5, count 0 2006.201.02:36:57.13#ibcon#read 5, iclass 5, count 0 2006.201.02:36:57.13#ibcon#about to read 6, iclass 5, count 0 2006.201.02:36:57.13#ibcon#read 6, iclass 5, count 0 2006.201.02:36:57.13#ibcon#end of sib2, iclass 5, count 0 2006.201.02:36:57.13#ibcon#*after write, iclass 5, count 0 2006.201.02:36:57.13#ibcon#*before return 0, iclass 5, count 0 2006.201.02:36:57.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:36:57.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:36:57.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:36:57.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:36:57.13$vck44/valo=5,734.99 2006.201.02:36:57.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.02:36:57.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.02:36:57.13#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:57.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:36:57.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:36:57.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:36:57.13#ibcon#enter wrdev, iclass 7, count 0 2006.201.02:36:57.13#ibcon#first serial, iclass 7, count 0 2006.201.02:36:57.13#ibcon#enter sib2, iclass 7, count 0 2006.201.02:36:57.13#ibcon#flushed, iclass 7, count 0 2006.201.02:36:57.13#ibcon#about to write, iclass 7, count 0 2006.201.02:36:57.13#ibcon#wrote, iclass 7, count 0 2006.201.02:36:57.13#ibcon#about to read 3, iclass 7, count 0 2006.201.02:36:57.15#ibcon#read 3, iclass 7, count 0 2006.201.02:36:57.15#ibcon#about to read 4, iclass 7, count 0 2006.201.02:36:57.15#ibcon#read 4, iclass 7, count 0 2006.201.02:36:57.15#ibcon#about to read 5, iclass 7, count 0 2006.201.02:36:57.15#ibcon#read 5, iclass 7, count 0 2006.201.02:36:57.15#ibcon#about to read 6, iclass 7, count 0 2006.201.02:36:57.15#ibcon#read 6, iclass 7, count 0 2006.201.02:36:57.15#ibcon#end of sib2, iclass 7, count 0 2006.201.02:36:57.15#ibcon#*mode == 0, iclass 7, count 0 2006.201.02:36:57.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.02:36:57.15#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:36:57.15#ibcon#*before write, iclass 7, count 0 2006.201.02:36:57.15#ibcon#enter sib2, iclass 7, count 0 2006.201.02:36:57.15#ibcon#flushed, iclass 7, count 0 2006.201.02:36:57.15#ibcon#about to write, iclass 7, count 0 2006.201.02:36:57.15#ibcon#wrote, iclass 7, count 0 2006.201.02:36:57.15#ibcon#about to read 3, iclass 7, count 0 2006.201.02:36:57.19#ibcon#read 3, iclass 7, count 0 2006.201.02:36:57.19#ibcon#about to read 4, iclass 7, count 0 2006.201.02:36:57.19#ibcon#read 4, iclass 7, count 0 2006.201.02:36:57.19#ibcon#about to read 5, iclass 7, count 0 2006.201.02:36:57.19#ibcon#read 5, iclass 7, count 0 2006.201.02:36:57.19#ibcon#about to read 6, iclass 7, count 0 2006.201.02:36:57.19#ibcon#read 6, iclass 7, count 0 2006.201.02:36:57.19#ibcon#end of sib2, iclass 7, count 0 2006.201.02:36:57.19#ibcon#*after write, iclass 7, count 0 2006.201.02:36:57.19#ibcon#*before return 0, iclass 7, count 0 2006.201.02:36:57.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:36:57.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:36:57.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.02:36:57.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.02:36:57.19$vck44/va=5,4 2006.201.02:36:57.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.02:36:57.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.02:36:57.19#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:57.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:36:57.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:36:57.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:36:57.25#ibcon#enter wrdev, iclass 11, count 2 2006.201.02:36:57.25#ibcon#first serial, iclass 11, count 2 2006.201.02:36:57.25#ibcon#enter sib2, iclass 11, count 2 2006.201.02:36:57.25#ibcon#flushed, iclass 11, count 2 2006.201.02:36:57.25#ibcon#about to write, iclass 11, count 2 2006.201.02:36:57.25#ibcon#wrote, iclass 11, count 2 2006.201.02:36:57.25#ibcon#about to read 3, iclass 11, count 2 2006.201.02:36:57.27#ibcon#read 3, iclass 11, count 2 2006.201.02:36:57.27#ibcon#about to read 4, iclass 11, count 2 2006.201.02:36:57.27#ibcon#read 4, iclass 11, count 2 2006.201.02:36:57.27#ibcon#about to read 5, iclass 11, count 2 2006.201.02:36:57.27#ibcon#read 5, iclass 11, count 2 2006.201.02:36:57.27#ibcon#about to read 6, iclass 11, count 2 2006.201.02:36:57.27#ibcon#read 6, iclass 11, count 2 2006.201.02:36:57.27#ibcon#end of sib2, iclass 11, count 2 2006.201.02:36:57.27#ibcon#*mode == 0, iclass 11, count 2 2006.201.02:36:57.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.02:36:57.27#ibcon#[25=AT05-04\r\n] 2006.201.02:36:57.27#ibcon#*before write, iclass 11, count 2 2006.201.02:36:57.27#ibcon#enter sib2, iclass 11, count 2 2006.201.02:36:57.27#ibcon#flushed, iclass 11, count 2 2006.201.02:36:57.27#ibcon#about to write, iclass 11, count 2 2006.201.02:36:57.27#ibcon#wrote, iclass 11, count 2 2006.201.02:36:57.27#ibcon#about to read 3, iclass 11, count 2 2006.201.02:36:57.30#ibcon#read 3, iclass 11, count 2 2006.201.02:36:57.30#ibcon#about to read 4, iclass 11, count 2 2006.201.02:36:57.30#ibcon#read 4, iclass 11, count 2 2006.201.02:36:57.30#ibcon#about to read 5, iclass 11, count 2 2006.201.02:36:57.30#ibcon#read 5, iclass 11, count 2 2006.201.02:36:57.30#ibcon#about to read 6, iclass 11, count 2 2006.201.02:36:57.30#ibcon#read 6, iclass 11, count 2 2006.201.02:36:57.30#ibcon#end of sib2, iclass 11, count 2 2006.201.02:36:57.30#ibcon#*after write, iclass 11, count 2 2006.201.02:36:57.30#ibcon#*before return 0, iclass 11, count 2 2006.201.02:36:57.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:36:57.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:36:57.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.02:36:57.30#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:57.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:36:57.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:36:57.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:36:57.42#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:36:57.42#ibcon#first serial, iclass 11, count 0 2006.201.02:36:57.42#ibcon#enter sib2, iclass 11, count 0 2006.201.02:36:57.42#ibcon#flushed, iclass 11, count 0 2006.201.02:36:57.42#ibcon#about to write, iclass 11, count 0 2006.201.02:36:57.42#ibcon#wrote, iclass 11, count 0 2006.201.02:36:57.42#ibcon#about to read 3, iclass 11, count 0 2006.201.02:36:57.44#ibcon#read 3, iclass 11, count 0 2006.201.02:36:57.44#ibcon#about to read 4, iclass 11, count 0 2006.201.02:36:57.44#ibcon#read 4, iclass 11, count 0 2006.201.02:36:57.44#ibcon#about to read 5, iclass 11, count 0 2006.201.02:36:57.44#ibcon#read 5, iclass 11, count 0 2006.201.02:36:57.44#ibcon#about to read 6, iclass 11, count 0 2006.201.02:36:57.44#ibcon#read 6, iclass 11, count 0 2006.201.02:36:57.44#ibcon#end of sib2, iclass 11, count 0 2006.201.02:36:57.44#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:36:57.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:36:57.44#ibcon#[25=USB\r\n] 2006.201.02:36:57.44#ibcon#*before write, iclass 11, count 0 2006.201.02:36:57.44#ibcon#enter sib2, iclass 11, count 0 2006.201.02:36:57.44#ibcon#flushed, iclass 11, count 0 2006.201.02:36:57.44#ibcon#about to write, iclass 11, count 0 2006.201.02:36:57.44#ibcon#wrote, iclass 11, count 0 2006.201.02:36:57.44#ibcon#about to read 3, iclass 11, count 0 2006.201.02:36:57.47#ibcon#read 3, iclass 11, count 0 2006.201.02:36:57.47#ibcon#about to read 4, iclass 11, count 0 2006.201.02:36:57.47#ibcon#read 4, iclass 11, count 0 2006.201.02:36:57.47#ibcon#about to read 5, iclass 11, count 0 2006.201.02:36:57.47#ibcon#read 5, iclass 11, count 0 2006.201.02:36:57.47#ibcon#about to read 6, iclass 11, count 0 2006.201.02:36:57.47#ibcon#read 6, iclass 11, count 0 2006.201.02:36:57.47#ibcon#end of sib2, iclass 11, count 0 2006.201.02:36:57.47#ibcon#*after write, iclass 11, count 0 2006.201.02:36:57.47#ibcon#*before return 0, iclass 11, count 0 2006.201.02:36:57.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:36:57.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:36:57.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:36:57.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:36:57.47$vck44/valo=6,814.99 2006.201.02:36:57.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.02:36:57.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.02:36:57.47#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:57.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:36:57.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:36:57.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:36:57.47#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:36:57.47#ibcon#first serial, iclass 13, count 0 2006.201.02:36:57.47#ibcon#enter sib2, iclass 13, count 0 2006.201.02:36:57.47#ibcon#flushed, iclass 13, count 0 2006.201.02:36:57.47#ibcon#about to write, iclass 13, count 0 2006.201.02:36:57.47#ibcon#wrote, iclass 13, count 0 2006.201.02:36:57.47#ibcon#about to read 3, iclass 13, count 0 2006.201.02:36:57.49#ibcon#read 3, iclass 13, count 0 2006.201.02:36:57.49#ibcon#about to read 4, iclass 13, count 0 2006.201.02:36:57.49#ibcon#read 4, iclass 13, count 0 2006.201.02:36:57.49#ibcon#about to read 5, iclass 13, count 0 2006.201.02:36:57.49#ibcon#read 5, iclass 13, count 0 2006.201.02:36:57.49#ibcon#about to read 6, iclass 13, count 0 2006.201.02:36:57.49#ibcon#read 6, iclass 13, count 0 2006.201.02:36:57.49#ibcon#end of sib2, iclass 13, count 0 2006.201.02:36:57.49#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:36:57.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:36:57.49#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:36:57.49#ibcon#*before write, iclass 13, count 0 2006.201.02:36:57.49#ibcon#enter sib2, iclass 13, count 0 2006.201.02:36:57.49#ibcon#flushed, iclass 13, count 0 2006.201.02:36:57.49#ibcon#about to write, iclass 13, count 0 2006.201.02:36:57.49#ibcon#wrote, iclass 13, count 0 2006.201.02:36:57.49#ibcon#about to read 3, iclass 13, count 0 2006.201.02:36:57.53#ibcon#read 3, iclass 13, count 0 2006.201.02:36:57.53#ibcon#about to read 4, iclass 13, count 0 2006.201.02:36:57.53#ibcon#read 4, iclass 13, count 0 2006.201.02:36:57.53#ibcon#about to read 5, iclass 13, count 0 2006.201.02:36:57.53#ibcon#read 5, iclass 13, count 0 2006.201.02:36:57.53#ibcon#about to read 6, iclass 13, count 0 2006.201.02:36:57.53#ibcon#read 6, iclass 13, count 0 2006.201.02:36:57.53#ibcon#end of sib2, iclass 13, count 0 2006.201.02:36:57.53#ibcon#*after write, iclass 13, count 0 2006.201.02:36:57.53#ibcon#*before return 0, iclass 13, count 0 2006.201.02:36:57.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:36:57.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:36:57.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:36:57.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:36:57.53$vck44/va=6,5 2006.201.02:36:57.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.02:36:57.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.02:36:57.53#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:57.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:36:57.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:36:57.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:36:57.59#ibcon#enter wrdev, iclass 15, count 2 2006.201.02:36:57.59#ibcon#first serial, iclass 15, count 2 2006.201.02:36:57.59#ibcon#enter sib2, iclass 15, count 2 2006.201.02:36:57.59#ibcon#flushed, iclass 15, count 2 2006.201.02:36:57.59#ibcon#about to write, iclass 15, count 2 2006.201.02:36:57.59#ibcon#wrote, iclass 15, count 2 2006.201.02:36:57.59#ibcon#about to read 3, iclass 15, count 2 2006.201.02:36:57.61#ibcon#read 3, iclass 15, count 2 2006.201.02:36:57.61#ibcon#about to read 4, iclass 15, count 2 2006.201.02:36:57.61#ibcon#read 4, iclass 15, count 2 2006.201.02:36:57.61#ibcon#about to read 5, iclass 15, count 2 2006.201.02:36:57.61#ibcon#read 5, iclass 15, count 2 2006.201.02:36:57.61#ibcon#about to read 6, iclass 15, count 2 2006.201.02:36:57.61#ibcon#read 6, iclass 15, count 2 2006.201.02:36:57.61#ibcon#end of sib2, iclass 15, count 2 2006.201.02:36:57.61#ibcon#*mode == 0, iclass 15, count 2 2006.201.02:36:57.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.02:36:57.61#ibcon#[25=AT06-05\r\n] 2006.201.02:36:57.61#ibcon#*before write, iclass 15, count 2 2006.201.02:36:57.61#ibcon#enter sib2, iclass 15, count 2 2006.201.02:36:57.61#ibcon#flushed, iclass 15, count 2 2006.201.02:36:57.61#ibcon#about to write, iclass 15, count 2 2006.201.02:36:57.61#ibcon#wrote, iclass 15, count 2 2006.201.02:36:57.61#ibcon#about to read 3, iclass 15, count 2 2006.201.02:36:57.64#ibcon#read 3, iclass 15, count 2 2006.201.02:36:57.64#ibcon#about to read 4, iclass 15, count 2 2006.201.02:36:57.64#ibcon#read 4, iclass 15, count 2 2006.201.02:36:57.64#ibcon#about to read 5, iclass 15, count 2 2006.201.02:36:57.64#ibcon#read 5, iclass 15, count 2 2006.201.02:36:57.64#ibcon#about to read 6, iclass 15, count 2 2006.201.02:36:57.64#ibcon#read 6, iclass 15, count 2 2006.201.02:36:57.64#ibcon#end of sib2, iclass 15, count 2 2006.201.02:36:57.64#ibcon#*after write, iclass 15, count 2 2006.201.02:36:57.64#ibcon#*before return 0, iclass 15, count 2 2006.201.02:36:57.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:36:57.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:36:57.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.02:36:57.64#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:57.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:36:57.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:36:57.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:36:57.76#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:36:57.76#ibcon#first serial, iclass 15, count 0 2006.201.02:36:57.76#ibcon#enter sib2, iclass 15, count 0 2006.201.02:36:57.76#ibcon#flushed, iclass 15, count 0 2006.201.02:36:57.76#ibcon#about to write, iclass 15, count 0 2006.201.02:36:57.76#ibcon#wrote, iclass 15, count 0 2006.201.02:36:57.76#ibcon#about to read 3, iclass 15, count 0 2006.201.02:36:57.78#ibcon#read 3, iclass 15, count 0 2006.201.02:36:57.78#ibcon#about to read 4, iclass 15, count 0 2006.201.02:36:57.78#ibcon#read 4, iclass 15, count 0 2006.201.02:36:57.78#ibcon#about to read 5, iclass 15, count 0 2006.201.02:36:57.78#ibcon#read 5, iclass 15, count 0 2006.201.02:36:57.78#ibcon#about to read 6, iclass 15, count 0 2006.201.02:36:57.78#ibcon#read 6, iclass 15, count 0 2006.201.02:36:57.78#ibcon#end of sib2, iclass 15, count 0 2006.201.02:36:57.78#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:36:57.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:36:57.78#ibcon#[25=USB\r\n] 2006.201.02:36:57.78#ibcon#*before write, iclass 15, count 0 2006.201.02:36:57.78#ibcon#enter sib2, iclass 15, count 0 2006.201.02:36:57.78#ibcon#flushed, iclass 15, count 0 2006.201.02:36:57.78#ibcon#about to write, iclass 15, count 0 2006.201.02:36:57.78#ibcon#wrote, iclass 15, count 0 2006.201.02:36:57.78#ibcon#about to read 3, iclass 15, count 0 2006.201.02:36:57.81#ibcon#read 3, iclass 15, count 0 2006.201.02:36:57.81#ibcon#about to read 4, iclass 15, count 0 2006.201.02:36:57.81#ibcon#read 4, iclass 15, count 0 2006.201.02:36:57.81#ibcon#about to read 5, iclass 15, count 0 2006.201.02:36:57.81#ibcon#read 5, iclass 15, count 0 2006.201.02:36:57.81#ibcon#about to read 6, iclass 15, count 0 2006.201.02:36:57.81#ibcon#read 6, iclass 15, count 0 2006.201.02:36:57.81#ibcon#end of sib2, iclass 15, count 0 2006.201.02:36:57.81#ibcon#*after write, iclass 15, count 0 2006.201.02:36:57.81#ibcon#*before return 0, iclass 15, count 0 2006.201.02:36:57.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:36:57.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:36:57.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:36:57.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:36:57.81$vck44/valo=7,864.99 2006.201.02:36:57.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.02:36:57.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.02:36:57.81#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:57.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:36:57.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:36:57.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:36:57.81#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:36:57.81#ibcon#first serial, iclass 17, count 0 2006.201.02:36:57.81#ibcon#enter sib2, iclass 17, count 0 2006.201.02:36:57.81#ibcon#flushed, iclass 17, count 0 2006.201.02:36:57.81#ibcon#about to write, iclass 17, count 0 2006.201.02:36:57.81#ibcon#wrote, iclass 17, count 0 2006.201.02:36:57.81#ibcon#about to read 3, iclass 17, count 0 2006.201.02:36:57.83#ibcon#read 3, iclass 17, count 0 2006.201.02:36:57.83#ibcon#about to read 4, iclass 17, count 0 2006.201.02:36:57.83#ibcon#read 4, iclass 17, count 0 2006.201.02:36:57.83#ibcon#about to read 5, iclass 17, count 0 2006.201.02:36:57.83#ibcon#read 5, iclass 17, count 0 2006.201.02:36:57.83#ibcon#about to read 6, iclass 17, count 0 2006.201.02:36:57.83#ibcon#read 6, iclass 17, count 0 2006.201.02:36:57.83#ibcon#end of sib2, iclass 17, count 0 2006.201.02:36:57.83#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:36:57.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:36:57.83#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:36:57.83#ibcon#*before write, iclass 17, count 0 2006.201.02:36:57.83#ibcon#enter sib2, iclass 17, count 0 2006.201.02:36:57.83#ibcon#flushed, iclass 17, count 0 2006.201.02:36:57.83#ibcon#about to write, iclass 17, count 0 2006.201.02:36:57.83#ibcon#wrote, iclass 17, count 0 2006.201.02:36:57.83#ibcon#about to read 3, iclass 17, count 0 2006.201.02:36:57.87#ibcon#read 3, iclass 17, count 0 2006.201.02:36:57.87#ibcon#about to read 4, iclass 17, count 0 2006.201.02:36:57.87#ibcon#read 4, iclass 17, count 0 2006.201.02:36:57.87#ibcon#about to read 5, iclass 17, count 0 2006.201.02:36:57.87#ibcon#read 5, iclass 17, count 0 2006.201.02:36:57.87#ibcon#about to read 6, iclass 17, count 0 2006.201.02:36:57.87#ibcon#read 6, iclass 17, count 0 2006.201.02:36:57.87#ibcon#end of sib2, iclass 17, count 0 2006.201.02:36:57.87#ibcon#*after write, iclass 17, count 0 2006.201.02:36:57.87#ibcon#*before return 0, iclass 17, count 0 2006.201.02:36:57.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:36:57.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:36:57.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:36:57.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:36:57.87$vck44/va=7,5 2006.201.02:36:57.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.02:36:57.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.02:36:57.87#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:57.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:36:57.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:36:57.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:36:57.93#ibcon#enter wrdev, iclass 19, count 2 2006.201.02:36:57.93#ibcon#first serial, iclass 19, count 2 2006.201.02:36:57.93#ibcon#enter sib2, iclass 19, count 2 2006.201.02:36:57.93#ibcon#flushed, iclass 19, count 2 2006.201.02:36:57.93#ibcon#about to write, iclass 19, count 2 2006.201.02:36:57.93#ibcon#wrote, iclass 19, count 2 2006.201.02:36:57.93#ibcon#about to read 3, iclass 19, count 2 2006.201.02:36:57.95#ibcon#read 3, iclass 19, count 2 2006.201.02:36:57.95#ibcon#about to read 4, iclass 19, count 2 2006.201.02:36:57.95#ibcon#read 4, iclass 19, count 2 2006.201.02:36:57.95#ibcon#about to read 5, iclass 19, count 2 2006.201.02:36:57.95#ibcon#read 5, iclass 19, count 2 2006.201.02:36:57.95#ibcon#about to read 6, iclass 19, count 2 2006.201.02:36:57.95#ibcon#read 6, iclass 19, count 2 2006.201.02:36:57.95#ibcon#end of sib2, iclass 19, count 2 2006.201.02:36:57.95#ibcon#*mode == 0, iclass 19, count 2 2006.201.02:36:57.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.02:36:57.95#ibcon#[25=AT07-05\r\n] 2006.201.02:36:57.95#ibcon#*before write, iclass 19, count 2 2006.201.02:36:57.95#ibcon#enter sib2, iclass 19, count 2 2006.201.02:36:57.95#ibcon#flushed, iclass 19, count 2 2006.201.02:36:57.95#ibcon#about to write, iclass 19, count 2 2006.201.02:36:57.95#ibcon#wrote, iclass 19, count 2 2006.201.02:36:57.95#ibcon#about to read 3, iclass 19, count 2 2006.201.02:36:57.98#ibcon#read 3, iclass 19, count 2 2006.201.02:36:57.98#ibcon#about to read 4, iclass 19, count 2 2006.201.02:36:57.98#ibcon#read 4, iclass 19, count 2 2006.201.02:36:57.98#ibcon#about to read 5, iclass 19, count 2 2006.201.02:36:57.98#ibcon#read 5, iclass 19, count 2 2006.201.02:36:57.98#ibcon#about to read 6, iclass 19, count 2 2006.201.02:36:57.98#ibcon#read 6, iclass 19, count 2 2006.201.02:36:57.98#ibcon#end of sib2, iclass 19, count 2 2006.201.02:36:57.98#ibcon#*after write, iclass 19, count 2 2006.201.02:36:57.98#ibcon#*before return 0, iclass 19, count 2 2006.201.02:36:57.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:36:57.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:36:57.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.02:36:57.98#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:57.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:36:58.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:36:58.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:36:58.10#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:36:58.10#ibcon#first serial, iclass 19, count 0 2006.201.02:36:58.10#ibcon#enter sib2, iclass 19, count 0 2006.201.02:36:58.10#ibcon#flushed, iclass 19, count 0 2006.201.02:36:58.10#ibcon#about to write, iclass 19, count 0 2006.201.02:36:58.10#ibcon#wrote, iclass 19, count 0 2006.201.02:36:58.10#ibcon#about to read 3, iclass 19, count 0 2006.201.02:36:58.12#ibcon#read 3, iclass 19, count 0 2006.201.02:36:58.12#ibcon#about to read 4, iclass 19, count 0 2006.201.02:36:58.12#ibcon#read 4, iclass 19, count 0 2006.201.02:36:58.12#ibcon#about to read 5, iclass 19, count 0 2006.201.02:36:58.12#ibcon#read 5, iclass 19, count 0 2006.201.02:36:58.12#ibcon#about to read 6, iclass 19, count 0 2006.201.02:36:58.12#ibcon#read 6, iclass 19, count 0 2006.201.02:36:58.12#ibcon#end of sib2, iclass 19, count 0 2006.201.02:36:58.12#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:36:58.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:36:58.12#ibcon#[25=USB\r\n] 2006.201.02:36:58.12#ibcon#*before write, iclass 19, count 0 2006.201.02:36:58.12#ibcon#enter sib2, iclass 19, count 0 2006.201.02:36:58.12#ibcon#flushed, iclass 19, count 0 2006.201.02:36:58.12#ibcon#about to write, iclass 19, count 0 2006.201.02:36:58.12#ibcon#wrote, iclass 19, count 0 2006.201.02:36:58.12#ibcon#about to read 3, iclass 19, count 0 2006.201.02:36:58.15#ibcon#read 3, iclass 19, count 0 2006.201.02:36:58.15#ibcon#about to read 4, iclass 19, count 0 2006.201.02:36:58.15#ibcon#read 4, iclass 19, count 0 2006.201.02:36:58.15#ibcon#about to read 5, iclass 19, count 0 2006.201.02:36:58.15#ibcon#read 5, iclass 19, count 0 2006.201.02:36:58.15#ibcon#about to read 6, iclass 19, count 0 2006.201.02:36:58.15#ibcon#read 6, iclass 19, count 0 2006.201.02:36:58.15#ibcon#end of sib2, iclass 19, count 0 2006.201.02:36:58.15#ibcon#*after write, iclass 19, count 0 2006.201.02:36:58.15#ibcon#*before return 0, iclass 19, count 0 2006.201.02:36:58.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:36:58.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:36:58.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:36:58.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:36:58.15$vck44/valo=8,884.99 2006.201.02:36:58.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.02:36:58.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.02:36:58.15#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:58.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:36:58.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:36:58.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:36:58.15#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:36:58.15#ibcon#first serial, iclass 21, count 0 2006.201.02:36:58.15#ibcon#enter sib2, iclass 21, count 0 2006.201.02:36:58.15#ibcon#flushed, iclass 21, count 0 2006.201.02:36:58.15#ibcon#about to write, iclass 21, count 0 2006.201.02:36:58.15#ibcon#wrote, iclass 21, count 0 2006.201.02:36:58.15#ibcon#about to read 3, iclass 21, count 0 2006.201.02:36:58.17#ibcon#read 3, iclass 21, count 0 2006.201.02:36:58.17#ibcon#about to read 4, iclass 21, count 0 2006.201.02:36:58.17#ibcon#read 4, iclass 21, count 0 2006.201.02:36:58.17#ibcon#about to read 5, iclass 21, count 0 2006.201.02:36:58.17#ibcon#read 5, iclass 21, count 0 2006.201.02:36:58.17#ibcon#about to read 6, iclass 21, count 0 2006.201.02:36:58.17#ibcon#read 6, iclass 21, count 0 2006.201.02:36:58.17#ibcon#end of sib2, iclass 21, count 0 2006.201.02:36:58.17#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:36:58.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:36:58.17#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:36:58.17#ibcon#*before write, iclass 21, count 0 2006.201.02:36:58.17#ibcon#enter sib2, iclass 21, count 0 2006.201.02:36:58.17#ibcon#flushed, iclass 21, count 0 2006.201.02:36:58.17#ibcon#about to write, iclass 21, count 0 2006.201.02:36:58.17#ibcon#wrote, iclass 21, count 0 2006.201.02:36:58.17#ibcon#about to read 3, iclass 21, count 0 2006.201.02:36:58.21#ibcon#read 3, iclass 21, count 0 2006.201.02:36:58.21#ibcon#about to read 4, iclass 21, count 0 2006.201.02:36:58.21#ibcon#read 4, iclass 21, count 0 2006.201.02:36:58.21#ibcon#about to read 5, iclass 21, count 0 2006.201.02:36:58.21#ibcon#read 5, iclass 21, count 0 2006.201.02:36:58.21#ibcon#about to read 6, iclass 21, count 0 2006.201.02:36:58.21#ibcon#read 6, iclass 21, count 0 2006.201.02:36:58.21#ibcon#end of sib2, iclass 21, count 0 2006.201.02:36:58.21#ibcon#*after write, iclass 21, count 0 2006.201.02:36:58.21#ibcon#*before return 0, iclass 21, count 0 2006.201.02:36:58.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:36:58.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:36:58.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:36:58.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:36:58.21$vck44/va=8,4 2006.201.02:36:58.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.02:36:58.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.02:36:58.21#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:58.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:36:58.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:36:58.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:36:58.27#ibcon#enter wrdev, iclass 23, count 2 2006.201.02:36:58.27#ibcon#first serial, iclass 23, count 2 2006.201.02:36:58.27#ibcon#enter sib2, iclass 23, count 2 2006.201.02:36:58.27#ibcon#flushed, iclass 23, count 2 2006.201.02:36:58.27#ibcon#about to write, iclass 23, count 2 2006.201.02:36:58.27#ibcon#wrote, iclass 23, count 2 2006.201.02:36:58.27#ibcon#about to read 3, iclass 23, count 2 2006.201.02:36:58.29#ibcon#read 3, iclass 23, count 2 2006.201.02:36:58.29#ibcon#about to read 4, iclass 23, count 2 2006.201.02:36:58.29#ibcon#read 4, iclass 23, count 2 2006.201.02:36:58.29#ibcon#about to read 5, iclass 23, count 2 2006.201.02:36:58.29#ibcon#read 5, iclass 23, count 2 2006.201.02:36:58.29#ibcon#about to read 6, iclass 23, count 2 2006.201.02:36:58.29#ibcon#read 6, iclass 23, count 2 2006.201.02:36:58.29#ibcon#end of sib2, iclass 23, count 2 2006.201.02:36:58.29#ibcon#*mode == 0, iclass 23, count 2 2006.201.02:36:58.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.02:36:58.29#ibcon#[25=AT08-04\r\n] 2006.201.02:36:58.29#ibcon#*before write, iclass 23, count 2 2006.201.02:36:58.29#ibcon#enter sib2, iclass 23, count 2 2006.201.02:36:58.29#ibcon#flushed, iclass 23, count 2 2006.201.02:36:58.29#ibcon#about to write, iclass 23, count 2 2006.201.02:36:58.29#ibcon#wrote, iclass 23, count 2 2006.201.02:36:58.29#ibcon#about to read 3, iclass 23, count 2 2006.201.02:36:58.32#ibcon#read 3, iclass 23, count 2 2006.201.02:36:58.32#ibcon#about to read 4, iclass 23, count 2 2006.201.02:36:58.32#ibcon#read 4, iclass 23, count 2 2006.201.02:36:58.32#ibcon#about to read 5, iclass 23, count 2 2006.201.02:36:58.32#ibcon#read 5, iclass 23, count 2 2006.201.02:36:58.32#ibcon#about to read 6, iclass 23, count 2 2006.201.02:36:58.32#ibcon#read 6, iclass 23, count 2 2006.201.02:36:58.32#ibcon#end of sib2, iclass 23, count 2 2006.201.02:36:58.32#ibcon#*after write, iclass 23, count 2 2006.201.02:36:58.32#ibcon#*before return 0, iclass 23, count 2 2006.201.02:36:58.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:36:58.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.02:36:58.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.02:36:58.32#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:58.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:36:58.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:36:58.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:36:58.44#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:36:58.44#ibcon#first serial, iclass 23, count 0 2006.201.02:36:58.44#ibcon#enter sib2, iclass 23, count 0 2006.201.02:36:58.44#ibcon#flushed, iclass 23, count 0 2006.201.02:36:58.44#ibcon#about to write, iclass 23, count 0 2006.201.02:36:58.44#ibcon#wrote, iclass 23, count 0 2006.201.02:36:58.44#ibcon#about to read 3, iclass 23, count 0 2006.201.02:36:58.46#ibcon#read 3, iclass 23, count 0 2006.201.02:36:58.46#ibcon#about to read 4, iclass 23, count 0 2006.201.02:36:58.46#ibcon#read 4, iclass 23, count 0 2006.201.02:36:58.46#ibcon#about to read 5, iclass 23, count 0 2006.201.02:36:58.46#ibcon#read 5, iclass 23, count 0 2006.201.02:36:58.46#ibcon#about to read 6, iclass 23, count 0 2006.201.02:36:58.46#ibcon#read 6, iclass 23, count 0 2006.201.02:36:58.46#ibcon#end of sib2, iclass 23, count 0 2006.201.02:36:58.46#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:36:58.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:36:58.46#ibcon#[25=USB\r\n] 2006.201.02:36:58.46#ibcon#*before write, iclass 23, count 0 2006.201.02:36:58.46#ibcon#enter sib2, iclass 23, count 0 2006.201.02:36:58.46#ibcon#flushed, iclass 23, count 0 2006.201.02:36:58.46#ibcon#about to write, iclass 23, count 0 2006.201.02:36:58.46#ibcon#wrote, iclass 23, count 0 2006.201.02:36:58.46#ibcon#about to read 3, iclass 23, count 0 2006.201.02:36:58.49#ibcon#read 3, iclass 23, count 0 2006.201.02:36:58.49#ibcon#about to read 4, iclass 23, count 0 2006.201.02:36:58.49#ibcon#read 4, iclass 23, count 0 2006.201.02:36:58.49#ibcon#about to read 5, iclass 23, count 0 2006.201.02:36:58.49#ibcon#read 5, iclass 23, count 0 2006.201.02:36:58.49#ibcon#about to read 6, iclass 23, count 0 2006.201.02:36:58.49#ibcon#read 6, iclass 23, count 0 2006.201.02:36:58.49#ibcon#end of sib2, iclass 23, count 0 2006.201.02:36:58.49#ibcon#*after write, iclass 23, count 0 2006.201.02:36:58.49#ibcon#*before return 0, iclass 23, count 0 2006.201.02:36:58.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:36:58.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.02:36:58.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:36:58.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:36:58.49$vck44/vblo=1,629.99 2006.201.02:36:58.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.02:36:58.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.02:36:58.49#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:58.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:36:58.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:36:58.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:36:58.49#ibcon#enter wrdev, iclass 25, count 0 2006.201.02:36:58.49#ibcon#first serial, iclass 25, count 0 2006.201.02:36:58.49#ibcon#enter sib2, iclass 25, count 0 2006.201.02:36:58.49#ibcon#flushed, iclass 25, count 0 2006.201.02:36:58.49#ibcon#about to write, iclass 25, count 0 2006.201.02:36:58.49#ibcon#wrote, iclass 25, count 0 2006.201.02:36:58.49#ibcon#about to read 3, iclass 25, count 0 2006.201.02:36:58.51#ibcon#read 3, iclass 25, count 0 2006.201.02:36:58.51#ibcon#about to read 4, iclass 25, count 0 2006.201.02:36:58.51#ibcon#read 4, iclass 25, count 0 2006.201.02:36:58.51#ibcon#about to read 5, iclass 25, count 0 2006.201.02:36:58.51#ibcon#read 5, iclass 25, count 0 2006.201.02:36:58.51#ibcon#about to read 6, iclass 25, count 0 2006.201.02:36:58.51#ibcon#read 6, iclass 25, count 0 2006.201.02:36:58.51#ibcon#end of sib2, iclass 25, count 0 2006.201.02:36:58.51#ibcon#*mode == 0, iclass 25, count 0 2006.201.02:36:58.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.02:36:58.51#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:36:58.51#ibcon#*before write, iclass 25, count 0 2006.201.02:36:58.51#ibcon#enter sib2, iclass 25, count 0 2006.201.02:36:58.51#ibcon#flushed, iclass 25, count 0 2006.201.02:36:58.51#ibcon#about to write, iclass 25, count 0 2006.201.02:36:58.51#ibcon#wrote, iclass 25, count 0 2006.201.02:36:58.51#ibcon#about to read 3, iclass 25, count 0 2006.201.02:36:58.56#ibcon#read 3, iclass 25, count 0 2006.201.02:36:58.56#ibcon#about to read 4, iclass 25, count 0 2006.201.02:36:58.56#ibcon#read 4, iclass 25, count 0 2006.201.02:36:58.56#ibcon#about to read 5, iclass 25, count 0 2006.201.02:36:58.56#ibcon#read 5, iclass 25, count 0 2006.201.02:36:58.56#ibcon#about to read 6, iclass 25, count 0 2006.201.02:36:58.56#ibcon#read 6, iclass 25, count 0 2006.201.02:36:58.56#ibcon#end of sib2, iclass 25, count 0 2006.201.02:36:58.56#ibcon#*after write, iclass 25, count 0 2006.201.02:36:58.56#ibcon#*before return 0, iclass 25, count 0 2006.201.02:36:58.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:36:58.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.02:36:58.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.02:36:58.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.02:36:58.56$vck44/vb=1,4 2006.201.02:36:58.56#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.02:36:58.56#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.02:36:58.56#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:58.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:36:58.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:36:58.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:36:58.56#ibcon#enter wrdev, iclass 27, count 2 2006.201.02:36:58.56#ibcon#first serial, iclass 27, count 2 2006.201.02:36:58.56#ibcon#enter sib2, iclass 27, count 2 2006.201.02:36:58.56#ibcon#flushed, iclass 27, count 2 2006.201.02:36:58.56#ibcon#about to write, iclass 27, count 2 2006.201.02:36:58.56#ibcon#wrote, iclass 27, count 2 2006.201.02:36:58.56#ibcon#about to read 3, iclass 27, count 2 2006.201.02:36:58.58#ibcon#read 3, iclass 27, count 2 2006.201.02:36:58.58#ibcon#about to read 4, iclass 27, count 2 2006.201.02:36:58.58#ibcon#read 4, iclass 27, count 2 2006.201.02:36:58.58#ibcon#about to read 5, iclass 27, count 2 2006.201.02:36:58.58#ibcon#read 5, iclass 27, count 2 2006.201.02:36:58.58#ibcon#about to read 6, iclass 27, count 2 2006.201.02:36:58.58#ibcon#read 6, iclass 27, count 2 2006.201.02:36:58.58#ibcon#end of sib2, iclass 27, count 2 2006.201.02:36:58.58#ibcon#*mode == 0, iclass 27, count 2 2006.201.02:36:58.58#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.02:36:58.58#ibcon#[27=AT01-04\r\n] 2006.201.02:36:58.58#ibcon#*before write, iclass 27, count 2 2006.201.02:36:58.58#ibcon#enter sib2, iclass 27, count 2 2006.201.02:36:58.58#ibcon#flushed, iclass 27, count 2 2006.201.02:36:58.58#ibcon#about to write, iclass 27, count 2 2006.201.02:36:58.58#ibcon#wrote, iclass 27, count 2 2006.201.02:36:58.58#ibcon#about to read 3, iclass 27, count 2 2006.201.02:36:58.61#ibcon#read 3, iclass 27, count 2 2006.201.02:36:58.61#ibcon#about to read 4, iclass 27, count 2 2006.201.02:36:58.61#ibcon#read 4, iclass 27, count 2 2006.201.02:36:58.61#ibcon#about to read 5, iclass 27, count 2 2006.201.02:36:58.61#ibcon#read 5, iclass 27, count 2 2006.201.02:36:58.61#ibcon#about to read 6, iclass 27, count 2 2006.201.02:36:58.61#ibcon#read 6, iclass 27, count 2 2006.201.02:36:58.61#ibcon#end of sib2, iclass 27, count 2 2006.201.02:36:58.61#ibcon#*after write, iclass 27, count 2 2006.201.02:36:58.61#ibcon#*before return 0, iclass 27, count 2 2006.201.02:36:58.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:36:58.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.02:36:58.61#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.02:36:58.61#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:58.61#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:36:58.73#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:36:58.73#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:36:58.73#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:36:58.73#ibcon#first serial, iclass 27, count 0 2006.201.02:36:58.73#ibcon#enter sib2, iclass 27, count 0 2006.201.02:36:58.73#ibcon#flushed, iclass 27, count 0 2006.201.02:36:58.73#ibcon#about to write, iclass 27, count 0 2006.201.02:36:58.73#ibcon#wrote, iclass 27, count 0 2006.201.02:36:58.73#ibcon#about to read 3, iclass 27, count 0 2006.201.02:36:58.75#ibcon#read 3, iclass 27, count 0 2006.201.02:36:58.75#ibcon#about to read 4, iclass 27, count 0 2006.201.02:36:58.75#ibcon#read 4, iclass 27, count 0 2006.201.02:36:58.75#ibcon#about to read 5, iclass 27, count 0 2006.201.02:36:58.75#ibcon#read 5, iclass 27, count 0 2006.201.02:36:58.75#ibcon#about to read 6, iclass 27, count 0 2006.201.02:36:58.75#ibcon#read 6, iclass 27, count 0 2006.201.02:36:58.75#ibcon#end of sib2, iclass 27, count 0 2006.201.02:36:58.75#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:36:58.75#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:36:58.75#ibcon#[27=USB\r\n] 2006.201.02:36:58.75#ibcon#*before write, iclass 27, count 0 2006.201.02:36:58.75#ibcon#enter sib2, iclass 27, count 0 2006.201.02:36:58.75#ibcon#flushed, iclass 27, count 0 2006.201.02:36:58.75#ibcon#about to write, iclass 27, count 0 2006.201.02:36:58.75#ibcon#wrote, iclass 27, count 0 2006.201.02:36:58.75#ibcon#about to read 3, iclass 27, count 0 2006.201.02:36:58.78#ibcon#read 3, iclass 27, count 0 2006.201.02:36:58.78#ibcon#about to read 4, iclass 27, count 0 2006.201.02:36:58.78#ibcon#read 4, iclass 27, count 0 2006.201.02:36:58.78#ibcon#about to read 5, iclass 27, count 0 2006.201.02:36:58.78#ibcon#read 5, iclass 27, count 0 2006.201.02:36:58.78#ibcon#about to read 6, iclass 27, count 0 2006.201.02:36:58.78#ibcon#read 6, iclass 27, count 0 2006.201.02:36:58.78#ibcon#end of sib2, iclass 27, count 0 2006.201.02:36:58.78#ibcon#*after write, iclass 27, count 0 2006.201.02:36:58.78#ibcon#*before return 0, iclass 27, count 0 2006.201.02:36:58.78#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:36:58.78#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.02:36:58.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:36:58.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:36:58.78$vck44/vblo=2,634.99 2006.201.02:36:58.78#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.02:36:58.78#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.02:36:58.78#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:58.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:58.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:58.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:58.78#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:36:58.78#ibcon#first serial, iclass 29, count 0 2006.201.02:36:58.78#ibcon#enter sib2, iclass 29, count 0 2006.201.02:36:58.78#ibcon#flushed, iclass 29, count 0 2006.201.02:36:58.78#ibcon#about to write, iclass 29, count 0 2006.201.02:36:58.78#ibcon#wrote, iclass 29, count 0 2006.201.02:36:58.78#ibcon#about to read 3, iclass 29, count 0 2006.201.02:36:58.80#ibcon#read 3, iclass 29, count 0 2006.201.02:36:58.80#ibcon#about to read 4, iclass 29, count 0 2006.201.02:36:58.80#ibcon#read 4, iclass 29, count 0 2006.201.02:36:58.80#ibcon#about to read 5, iclass 29, count 0 2006.201.02:36:58.80#ibcon#read 5, iclass 29, count 0 2006.201.02:36:58.80#ibcon#about to read 6, iclass 29, count 0 2006.201.02:36:58.80#ibcon#read 6, iclass 29, count 0 2006.201.02:36:58.80#ibcon#end of sib2, iclass 29, count 0 2006.201.02:36:58.80#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:36:58.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:36:58.80#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:36:58.80#ibcon#*before write, iclass 29, count 0 2006.201.02:36:58.80#ibcon#enter sib2, iclass 29, count 0 2006.201.02:36:58.80#ibcon#flushed, iclass 29, count 0 2006.201.02:36:58.80#ibcon#about to write, iclass 29, count 0 2006.201.02:36:58.80#ibcon#wrote, iclass 29, count 0 2006.201.02:36:58.80#ibcon#about to read 3, iclass 29, count 0 2006.201.02:36:58.84#ibcon#read 3, iclass 29, count 0 2006.201.02:36:58.84#ibcon#about to read 4, iclass 29, count 0 2006.201.02:36:58.84#ibcon#read 4, iclass 29, count 0 2006.201.02:36:58.84#ibcon#about to read 5, iclass 29, count 0 2006.201.02:36:58.84#ibcon#read 5, iclass 29, count 0 2006.201.02:36:58.84#ibcon#about to read 6, iclass 29, count 0 2006.201.02:36:58.84#ibcon#read 6, iclass 29, count 0 2006.201.02:36:58.84#ibcon#end of sib2, iclass 29, count 0 2006.201.02:36:58.84#ibcon#*after write, iclass 29, count 0 2006.201.02:36:58.84#ibcon#*before return 0, iclass 29, count 0 2006.201.02:36:58.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:58.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.02:36:58.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:36:58.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:36:58.84$vck44/vb=2,5 2006.201.02:36:58.84#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.02:36:58.84#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.02:36:58.84#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:58.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:58.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:58.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:58.90#ibcon#enter wrdev, iclass 31, count 2 2006.201.02:36:58.90#ibcon#first serial, iclass 31, count 2 2006.201.02:36:58.90#ibcon#enter sib2, iclass 31, count 2 2006.201.02:36:58.90#ibcon#flushed, iclass 31, count 2 2006.201.02:36:58.90#ibcon#about to write, iclass 31, count 2 2006.201.02:36:58.90#ibcon#wrote, iclass 31, count 2 2006.201.02:36:58.90#ibcon#about to read 3, iclass 31, count 2 2006.201.02:36:58.92#ibcon#read 3, iclass 31, count 2 2006.201.02:36:58.92#ibcon#about to read 4, iclass 31, count 2 2006.201.02:36:58.92#ibcon#read 4, iclass 31, count 2 2006.201.02:36:58.92#ibcon#about to read 5, iclass 31, count 2 2006.201.02:36:58.92#ibcon#read 5, iclass 31, count 2 2006.201.02:36:58.92#ibcon#about to read 6, iclass 31, count 2 2006.201.02:36:58.92#ibcon#read 6, iclass 31, count 2 2006.201.02:36:58.92#ibcon#end of sib2, iclass 31, count 2 2006.201.02:36:58.92#ibcon#*mode == 0, iclass 31, count 2 2006.201.02:36:58.92#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.02:36:58.92#ibcon#[27=AT02-05\r\n] 2006.201.02:36:58.92#ibcon#*before write, iclass 31, count 2 2006.201.02:36:58.92#ibcon#enter sib2, iclass 31, count 2 2006.201.02:36:58.92#ibcon#flushed, iclass 31, count 2 2006.201.02:36:58.92#ibcon#about to write, iclass 31, count 2 2006.201.02:36:58.92#ibcon#wrote, iclass 31, count 2 2006.201.02:36:58.92#ibcon#about to read 3, iclass 31, count 2 2006.201.02:36:58.95#ibcon#read 3, iclass 31, count 2 2006.201.02:36:58.95#ibcon#about to read 4, iclass 31, count 2 2006.201.02:36:58.95#ibcon#read 4, iclass 31, count 2 2006.201.02:36:58.95#ibcon#about to read 5, iclass 31, count 2 2006.201.02:36:58.95#ibcon#read 5, iclass 31, count 2 2006.201.02:36:58.95#ibcon#about to read 6, iclass 31, count 2 2006.201.02:36:58.95#ibcon#read 6, iclass 31, count 2 2006.201.02:36:58.95#ibcon#end of sib2, iclass 31, count 2 2006.201.02:36:58.95#ibcon#*after write, iclass 31, count 2 2006.201.02:36:58.95#ibcon#*before return 0, iclass 31, count 2 2006.201.02:36:58.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:58.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.02:36:58.95#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.02:36:58.95#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:58.95#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:59.07#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:59.07#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:59.07#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:36:59.07#ibcon#first serial, iclass 31, count 0 2006.201.02:36:59.07#ibcon#enter sib2, iclass 31, count 0 2006.201.02:36:59.07#ibcon#flushed, iclass 31, count 0 2006.201.02:36:59.07#ibcon#about to write, iclass 31, count 0 2006.201.02:36:59.07#ibcon#wrote, iclass 31, count 0 2006.201.02:36:59.07#ibcon#about to read 3, iclass 31, count 0 2006.201.02:36:59.09#ibcon#read 3, iclass 31, count 0 2006.201.02:36:59.09#ibcon#about to read 4, iclass 31, count 0 2006.201.02:36:59.09#ibcon#read 4, iclass 31, count 0 2006.201.02:36:59.09#ibcon#about to read 5, iclass 31, count 0 2006.201.02:36:59.09#ibcon#read 5, iclass 31, count 0 2006.201.02:36:59.09#ibcon#about to read 6, iclass 31, count 0 2006.201.02:36:59.09#ibcon#read 6, iclass 31, count 0 2006.201.02:36:59.09#ibcon#end of sib2, iclass 31, count 0 2006.201.02:36:59.09#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:36:59.09#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:36:59.09#ibcon#[27=USB\r\n] 2006.201.02:36:59.09#ibcon#*before write, iclass 31, count 0 2006.201.02:36:59.09#ibcon#enter sib2, iclass 31, count 0 2006.201.02:36:59.09#ibcon#flushed, iclass 31, count 0 2006.201.02:36:59.09#ibcon#about to write, iclass 31, count 0 2006.201.02:36:59.09#ibcon#wrote, iclass 31, count 0 2006.201.02:36:59.09#ibcon#about to read 3, iclass 31, count 0 2006.201.02:36:59.12#ibcon#read 3, iclass 31, count 0 2006.201.02:36:59.12#ibcon#about to read 4, iclass 31, count 0 2006.201.02:36:59.12#ibcon#read 4, iclass 31, count 0 2006.201.02:36:59.12#ibcon#about to read 5, iclass 31, count 0 2006.201.02:36:59.12#ibcon#read 5, iclass 31, count 0 2006.201.02:36:59.12#ibcon#about to read 6, iclass 31, count 0 2006.201.02:36:59.12#ibcon#read 6, iclass 31, count 0 2006.201.02:36:59.12#ibcon#end of sib2, iclass 31, count 0 2006.201.02:36:59.12#ibcon#*after write, iclass 31, count 0 2006.201.02:36:59.12#ibcon#*before return 0, iclass 31, count 0 2006.201.02:36:59.12#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:59.12#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.02:36:59.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:36:59.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:36:59.12$vck44/vblo=3,649.99 2006.201.02:36:59.12#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.02:36:59.12#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.02:36:59.12#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:59.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:59.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:59.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:59.12#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:36:59.12#ibcon#first serial, iclass 33, count 0 2006.201.02:36:59.12#ibcon#enter sib2, iclass 33, count 0 2006.201.02:36:59.12#ibcon#flushed, iclass 33, count 0 2006.201.02:36:59.12#ibcon#about to write, iclass 33, count 0 2006.201.02:36:59.12#ibcon#wrote, iclass 33, count 0 2006.201.02:36:59.12#ibcon#about to read 3, iclass 33, count 0 2006.201.02:36:59.14#ibcon#read 3, iclass 33, count 0 2006.201.02:36:59.14#ibcon#about to read 4, iclass 33, count 0 2006.201.02:36:59.14#ibcon#read 4, iclass 33, count 0 2006.201.02:36:59.14#ibcon#about to read 5, iclass 33, count 0 2006.201.02:36:59.14#ibcon#read 5, iclass 33, count 0 2006.201.02:36:59.14#ibcon#about to read 6, iclass 33, count 0 2006.201.02:36:59.14#ibcon#read 6, iclass 33, count 0 2006.201.02:36:59.14#ibcon#end of sib2, iclass 33, count 0 2006.201.02:36:59.14#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:36:59.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:36:59.14#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:36:59.14#ibcon#*before write, iclass 33, count 0 2006.201.02:36:59.14#ibcon#enter sib2, iclass 33, count 0 2006.201.02:36:59.14#ibcon#flushed, iclass 33, count 0 2006.201.02:36:59.14#ibcon#about to write, iclass 33, count 0 2006.201.02:36:59.14#ibcon#wrote, iclass 33, count 0 2006.201.02:36:59.14#ibcon#about to read 3, iclass 33, count 0 2006.201.02:36:59.18#ibcon#read 3, iclass 33, count 0 2006.201.02:36:59.18#ibcon#about to read 4, iclass 33, count 0 2006.201.02:36:59.18#ibcon#read 4, iclass 33, count 0 2006.201.02:36:59.18#ibcon#about to read 5, iclass 33, count 0 2006.201.02:36:59.18#ibcon#read 5, iclass 33, count 0 2006.201.02:36:59.18#ibcon#about to read 6, iclass 33, count 0 2006.201.02:36:59.18#ibcon#read 6, iclass 33, count 0 2006.201.02:36:59.18#ibcon#end of sib2, iclass 33, count 0 2006.201.02:36:59.18#ibcon#*after write, iclass 33, count 0 2006.201.02:36:59.18#ibcon#*before return 0, iclass 33, count 0 2006.201.02:36:59.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:59.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.02:36:59.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:36:59.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:36:59.18$vck44/vb=3,4 2006.201.02:36:59.18#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.02:36:59.18#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.02:36:59.18#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:59.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:59.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:59.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:59.24#ibcon#enter wrdev, iclass 35, count 2 2006.201.02:36:59.24#ibcon#first serial, iclass 35, count 2 2006.201.02:36:59.24#ibcon#enter sib2, iclass 35, count 2 2006.201.02:36:59.24#ibcon#flushed, iclass 35, count 2 2006.201.02:36:59.24#ibcon#about to write, iclass 35, count 2 2006.201.02:36:59.24#ibcon#wrote, iclass 35, count 2 2006.201.02:36:59.24#ibcon#about to read 3, iclass 35, count 2 2006.201.02:36:59.26#ibcon#read 3, iclass 35, count 2 2006.201.02:36:59.26#ibcon#about to read 4, iclass 35, count 2 2006.201.02:36:59.26#ibcon#read 4, iclass 35, count 2 2006.201.02:36:59.26#ibcon#about to read 5, iclass 35, count 2 2006.201.02:36:59.26#ibcon#read 5, iclass 35, count 2 2006.201.02:36:59.26#ibcon#about to read 6, iclass 35, count 2 2006.201.02:36:59.26#ibcon#read 6, iclass 35, count 2 2006.201.02:36:59.26#ibcon#end of sib2, iclass 35, count 2 2006.201.02:36:59.26#ibcon#*mode == 0, iclass 35, count 2 2006.201.02:36:59.26#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.02:36:59.26#ibcon#[27=AT03-04\r\n] 2006.201.02:36:59.26#ibcon#*before write, iclass 35, count 2 2006.201.02:36:59.26#ibcon#enter sib2, iclass 35, count 2 2006.201.02:36:59.26#ibcon#flushed, iclass 35, count 2 2006.201.02:36:59.26#ibcon#about to write, iclass 35, count 2 2006.201.02:36:59.26#ibcon#wrote, iclass 35, count 2 2006.201.02:36:59.26#ibcon#about to read 3, iclass 35, count 2 2006.201.02:36:59.29#ibcon#read 3, iclass 35, count 2 2006.201.02:36:59.29#ibcon#about to read 4, iclass 35, count 2 2006.201.02:36:59.29#ibcon#read 4, iclass 35, count 2 2006.201.02:36:59.29#ibcon#about to read 5, iclass 35, count 2 2006.201.02:36:59.29#ibcon#read 5, iclass 35, count 2 2006.201.02:36:59.29#ibcon#about to read 6, iclass 35, count 2 2006.201.02:36:59.29#ibcon#read 6, iclass 35, count 2 2006.201.02:36:59.29#ibcon#end of sib2, iclass 35, count 2 2006.201.02:36:59.29#ibcon#*after write, iclass 35, count 2 2006.201.02:36:59.29#ibcon#*before return 0, iclass 35, count 2 2006.201.02:36:59.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:59.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.02:36:59.29#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.02:36:59.29#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:59.29#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:59.41#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:59.41#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:59.41#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:36:59.41#ibcon#first serial, iclass 35, count 0 2006.201.02:36:59.41#ibcon#enter sib2, iclass 35, count 0 2006.201.02:36:59.41#ibcon#flushed, iclass 35, count 0 2006.201.02:36:59.41#ibcon#about to write, iclass 35, count 0 2006.201.02:36:59.41#ibcon#wrote, iclass 35, count 0 2006.201.02:36:59.41#ibcon#about to read 3, iclass 35, count 0 2006.201.02:36:59.43#ibcon#read 3, iclass 35, count 0 2006.201.02:36:59.43#ibcon#about to read 4, iclass 35, count 0 2006.201.02:36:59.43#ibcon#read 4, iclass 35, count 0 2006.201.02:36:59.43#ibcon#about to read 5, iclass 35, count 0 2006.201.02:36:59.43#ibcon#read 5, iclass 35, count 0 2006.201.02:36:59.43#ibcon#about to read 6, iclass 35, count 0 2006.201.02:36:59.43#ibcon#read 6, iclass 35, count 0 2006.201.02:36:59.43#ibcon#end of sib2, iclass 35, count 0 2006.201.02:36:59.43#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:36:59.43#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:36:59.43#ibcon#[27=USB\r\n] 2006.201.02:36:59.43#ibcon#*before write, iclass 35, count 0 2006.201.02:36:59.43#ibcon#enter sib2, iclass 35, count 0 2006.201.02:36:59.43#ibcon#flushed, iclass 35, count 0 2006.201.02:36:59.43#ibcon#about to write, iclass 35, count 0 2006.201.02:36:59.43#ibcon#wrote, iclass 35, count 0 2006.201.02:36:59.43#ibcon#about to read 3, iclass 35, count 0 2006.201.02:36:59.46#ibcon#read 3, iclass 35, count 0 2006.201.02:36:59.46#ibcon#about to read 4, iclass 35, count 0 2006.201.02:36:59.46#ibcon#read 4, iclass 35, count 0 2006.201.02:36:59.46#ibcon#about to read 5, iclass 35, count 0 2006.201.02:36:59.46#ibcon#read 5, iclass 35, count 0 2006.201.02:36:59.46#ibcon#about to read 6, iclass 35, count 0 2006.201.02:36:59.46#ibcon#read 6, iclass 35, count 0 2006.201.02:36:59.46#ibcon#end of sib2, iclass 35, count 0 2006.201.02:36:59.46#ibcon#*after write, iclass 35, count 0 2006.201.02:36:59.46#ibcon#*before return 0, iclass 35, count 0 2006.201.02:36:59.46#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:59.46#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.02:36:59.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:36:59.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:36:59.46$vck44/vblo=4,679.99 2006.201.02:36:59.46#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.02:36:59.46#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.02:36:59.46#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:59.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:59.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:59.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:59.46#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:36:59.46#ibcon#first serial, iclass 37, count 0 2006.201.02:36:59.46#ibcon#enter sib2, iclass 37, count 0 2006.201.02:36:59.46#ibcon#flushed, iclass 37, count 0 2006.201.02:36:59.46#ibcon#about to write, iclass 37, count 0 2006.201.02:36:59.46#ibcon#wrote, iclass 37, count 0 2006.201.02:36:59.46#ibcon#about to read 3, iclass 37, count 0 2006.201.02:36:59.48#ibcon#read 3, iclass 37, count 0 2006.201.02:36:59.48#ibcon#about to read 4, iclass 37, count 0 2006.201.02:36:59.48#ibcon#read 4, iclass 37, count 0 2006.201.02:36:59.48#ibcon#about to read 5, iclass 37, count 0 2006.201.02:36:59.48#ibcon#read 5, iclass 37, count 0 2006.201.02:36:59.48#ibcon#about to read 6, iclass 37, count 0 2006.201.02:36:59.48#ibcon#read 6, iclass 37, count 0 2006.201.02:36:59.48#ibcon#end of sib2, iclass 37, count 0 2006.201.02:36:59.48#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:36:59.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:36:59.48#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:36:59.48#ibcon#*before write, iclass 37, count 0 2006.201.02:36:59.48#ibcon#enter sib2, iclass 37, count 0 2006.201.02:36:59.48#ibcon#flushed, iclass 37, count 0 2006.201.02:36:59.48#ibcon#about to write, iclass 37, count 0 2006.201.02:36:59.48#ibcon#wrote, iclass 37, count 0 2006.201.02:36:59.48#ibcon#about to read 3, iclass 37, count 0 2006.201.02:36:59.53#ibcon#read 3, iclass 37, count 0 2006.201.02:36:59.53#ibcon#about to read 4, iclass 37, count 0 2006.201.02:36:59.53#ibcon#read 4, iclass 37, count 0 2006.201.02:36:59.53#ibcon#about to read 5, iclass 37, count 0 2006.201.02:36:59.53#ibcon#read 5, iclass 37, count 0 2006.201.02:36:59.53#ibcon#about to read 6, iclass 37, count 0 2006.201.02:36:59.53#ibcon#read 6, iclass 37, count 0 2006.201.02:36:59.53#ibcon#end of sib2, iclass 37, count 0 2006.201.02:36:59.53#ibcon#*after write, iclass 37, count 0 2006.201.02:36:59.53#ibcon#*before return 0, iclass 37, count 0 2006.201.02:36:59.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:59.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:36:59.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:36:59.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:36:59.53$vck44/vb=4,5 2006.201.02:36:59.53#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.02:36:59.53#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.02:36:59.53#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:59.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:59.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:59.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:59.58#ibcon#enter wrdev, iclass 39, count 2 2006.201.02:36:59.58#ibcon#first serial, iclass 39, count 2 2006.201.02:36:59.58#ibcon#enter sib2, iclass 39, count 2 2006.201.02:36:59.58#ibcon#flushed, iclass 39, count 2 2006.201.02:36:59.58#ibcon#about to write, iclass 39, count 2 2006.201.02:36:59.58#ibcon#wrote, iclass 39, count 2 2006.201.02:36:59.58#ibcon#about to read 3, iclass 39, count 2 2006.201.02:36:59.60#ibcon#read 3, iclass 39, count 2 2006.201.02:36:59.60#ibcon#about to read 4, iclass 39, count 2 2006.201.02:36:59.60#ibcon#read 4, iclass 39, count 2 2006.201.02:36:59.60#ibcon#about to read 5, iclass 39, count 2 2006.201.02:36:59.60#ibcon#read 5, iclass 39, count 2 2006.201.02:36:59.60#ibcon#about to read 6, iclass 39, count 2 2006.201.02:36:59.60#ibcon#read 6, iclass 39, count 2 2006.201.02:36:59.60#ibcon#end of sib2, iclass 39, count 2 2006.201.02:36:59.60#ibcon#*mode == 0, iclass 39, count 2 2006.201.02:36:59.60#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.02:36:59.60#ibcon#[27=AT04-05\r\n] 2006.201.02:36:59.60#ibcon#*before write, iclass 39, count 2 2006.201.02:36:59.60#ibcon#enter sib2, iclass 39, count 2 2006.201.02:36:59.60#ibcon#flushed, iclass 39, count 2 2006.201.02:36:59.60#ibcon#about to write, iclass 39, count 2 2006.201.02:36:59.60#ibcon#wrote, iclass 39, count 2 2006.201.02:36:59.60#ibcon#about to read 3, iclass 39, count 2 2006.201.02:36:59.63#ibcon#read 3, iclass 39, count 2 2006.201.02:36:59.63#ibcon#about to read 4, iclass 39, count 2 2006.201.02:36:59.63#ibcon#read 4, iclass 39, count 2 2006.201.02:36:59.63#ibcon#about to read 5, iclass 39, count 2 2006.201.02:36:59.63#ibcon#read 5, iclass 39, count 2 2006.201.02:36:59.63#ibcon#about to read 6, iclass 39, count 2 2006.201.02:36:59.63#ibcon#read 6, iclass 39, count 2 2006.201.02:36:59.63#ibcon#end of sib2, iclass 39, count 2 2006.201.02:36:59.63#ibcon#*after write, iclass 39, count 2 2006.201.02:36:59.63#ibcon#*before return 0, iclass 39, count 2 2006.201.02:36:59.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:59.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.02:36:59.63#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.02:36:59.63#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:59.63#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:59.75#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:59.75#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:59.75#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:36:59.75#ibcon#first serial, iclass 39, count 0 2006.201.02:36:59.75#ibcon#enter sib2, iclass 39, count 0 2006.201.02:36:59.75#ibcon#flushed, iclass 39, count 0 2006.201.02:36:59.75#ibcon#about to write, iclass 39, count 0 2006.201.02:36:59.75#ibcon#wrote, iclass 39, count 0 2006.201.02:36:59.75#ibcon#about to read 3, iclass 39, count 0 2006.201.02:36:59.77#ibcon#read 3, iclass 39, count 0 2006.201.02:36:59.77#ibcon#about to read 4, iclass 39, count 0 2006.201.02:36:59.77#ibcon#read 4, iclass 39, count 0 2006.201.02:36:59.77#ibcon#about to read 5, iclass 39, count 0 2006.201.02:36:59.77#ibcon#read 5, iclass 39, count 0 2006.201.02:36:59.77#ibcon#about to read 6, iclass 39, count 0 2006.201.02:36:59.77#ibcon#read 6, iclass 39, count 0 2006.201.02:36:59.77#ibcon#end of sib2, iclass 39, count 0 2006.201.02:36:59.77#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:36:59.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:36:59.77#ibcon#[27=USB\r\n] 2006.201.02:36:59.77#ibcon#*before write, iclass 39, count 0 2006.201.02:36:59.77#ibcon#enter sib2, iclass 39, count 0 2006.201.02:36:59.77#ibcon#flushed, iclass 39, count 0 2006.201.02:36:59.77#ibcon#about to write, iclass 39, count 0 2006.201.02:36:59.77#ibcon#wrote, iclass 39, count 0 2006.201.02:36:59.77#ibcon#about to read 3, iclass 39, count 0 2006.201.02:36:59.80#ibcon#read 3, iclass 39, count 0 2006.201.02:36:59.80#ibcon#about to read 4, iclass 39, count 0 2006.201.02:36:59.80#ibcon#read 4, iclass 39, count 0 2006.201.02:36:59.80#ibcon#about to read 5, iclass 39, count 0 2006.201.02:36:59.80#ibcon#read 5, iclass 39, count 0 2006.201.02:36:59.80#ibcon#about to read 6, iclass 39, count 0 2006.201.02:36:59.80#ibcon#read 6, iclass 39, count 0 2006.201.02:36:59.80#ibcon#end of sib2, iclass 39, count 0 2006.201.02:36:59.80#ibcon#*after write, iclass 39, count 0 2006.201.02:36:59.80#ibcon#*before return 0, iclass 39, count 0 2006.201.02:36:59.80#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:59.80#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.02:36:59.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:36:59.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:36:59.80$vck44/vblo=5,709.99 2006.201.02:36:59.80#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.02:36:59.80#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.02:36:59.80#ibcon#ireg 17 cls_cnt 0 2006.201.02:36:59.80#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:59.80#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:59.80#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:59.80#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:36:59.80#ibcon#first serial, iclass 2, count 0 2006.201.02:36:59.80#ibcon#enter sib2, iclass 2, count 0 2006.201.02:36:59.80#ibcon#flushed, iclass 2, count 0 2006.201.02:36:59.80#ibcon#about to write, iclass 2, count 0 2006.201.02:36:59.80#ibcon#wrote, iclass 2, count 0 2006.201.02:36:59.80#ibcon#about to read 3, iclass 2, count 0 2006.201.02:36:59.82#ibcon#read 3, iclass 2, count 0 2006.201.02:36:59.82#ibcon#about to read 4, iclass 2, count 0 2006.201.02:36:59.82#ibcon#read 4, iclass 2, count 0 2006.201.02:36:59.82#ibcon#about to read 5, iclass 2, count 0 2006.201.02:36:59.82#ibcon#read 5, iclass 2, count 0 2006.201.02:36:59.82#ibcon#about to read 6, iclass 2, count 0 2006.201.02:36:59.82#ibcon#read 6, iclass 2, count 0 2006.201.02:36:59.82#ibcon#end of sib2, iclass 2, count 0 2006.201.02:36:59.82#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:36:59.82#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:36:59.82#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:36:59.82#ibcon#*before write, iclass 2, count 0 2006.201.02:36:59.82#ibcon#enter sib2, iclass 2, count 0 2006.201.02:36:59.82#ibcon#flushed, iclass 2, count 0 2006.201.02:36:59.82#ibcon#about to write, iclass 2, count 0 2006.201.02:36:59.82#ibcon#wrote, iclass 2, count 0 2006.201.02:36:59.82#ibcon#about to read 3, iclass 2, count 0 2006.201.02:36:59.86#ibcon#read 3, iclass 2, count 0 2006.201.02:36:59.86#ibcon#about to read 4, iclass 2, count 0 2006.201.02:36:59.86#ibcon#read 4, iclass 2, count 0 2006.201.02:36:59.86#ibcon#about to read 5, iclass 2, count 0 2006.201.02:36:59.86#ibcon#read 5, iclass 2, count 0 2006.201.02:36:59.86#ibcon#about to read 6, iclass 2, count 0 2006.201.02:36:59.86#ibcon#read 6, iclass 2, count 0 2006.201.02:36:59.86#ibcon#end of sib2, iclass 2, count 0 2006.201.02:36:59.86#ibcon#*after write, iclass 2, count 0 2006.201.02:36:59.86#ibcon#*before return 0, iclass 2, count 0 2006.201.02:36:59.86#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:59.86#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.02:36:59.86#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:36:59.86#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:36:59.86$vck44/vb=5,4 2006.201.02:36:59.86#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.02:36:59.86#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.02:36:59.86#ibcon#ireg 11 cls_cnt 2 2006.201.02:36:59.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:59.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:59.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:59.92#ibcon#enter wrdev, iclass 5, count 2 2006.201.02:36:59.92#ibcon#first serial, iclass 5, count 2 2006.201.02:36:59.92#ibcon#enter sib2, iclass 5, count 2 2006.201.02:36:59.92#ibcon#flushed, iclass 5, count 2 2006.201.02:36:59.92#ibcon#about to write, iclass 5, count 2 2006.201.02:36:59.92#ibcon#wrote, iclass 5, count 2 2006.201.02:36:59.92#ibcon#about to read 3, iclass 5, count 2 2006.201.02:36:59.94#ibcon#read 3, iclass 5, count 2 2006.201.02:36:59.94#ibcon#about to read 4, iclass 5, count 2 2006.201.02:36:59.94#ibcon#read 4, iclass 5, count 2 2006.201.02:36:59.94#ibcon#about to read 5, iclass 5, count 2 2006.201.02:36:59.94#ibcon#read 5, iclass 5, count 2 2006.201.02:36:59.94#ibcon#about to read 6, iclass 5, count 2 2006.201.02:36:59.94#ibcon#read 6, iclass 5, count 2 2006.201.02:36:59.94#ibcon#end of sib2, iclass 5, count 2 2006.201.02:36:59.94#ibcon#*mode == 0, iclass 5, count 2 2006.201.02:36:59.94#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.02:36:59.94#ibcon#[27=AT05-04\r\n] 2006.201.02:36:59.94#ibcon#*before write, iclass 5, count 2 2006.201.02:36:59.94#ibcon#enter sib2, iclass 5, count 2 2006.201.02:36:59.94#ibcon#flushed, iclass 5, count 2 2006.201.02:36:59.94#ibcon#about to write, iclass 5, count 2 2006.201.02:36:59.94#ibcon#wrote, iclass 5, count 2 2006.201.02:36:59.94#ibcon#about to read 3, iclass 5, count 2 2006.201.02:36:59.97#ibcon#read 3, iclass 5, count 2 2006.201.02:36:59.97#ibcon#about to read 4, iclass 5, count 2 2006.201.02:36:59.97#ibcon#read 4, iclass 5, count 2 2006.201.02:36:59.97#ibcon#about to read 5, iclass 5, count 2 2006.201.02:36:59.97#ibcon#read 5, iclass 5, count 2 2006.201.02:36:59.97#ibcon#about to read 6, iclass 5, count 2 2006.201.02:36:59.97#ibcon#read 6, iclass 5, count 2 2006.201.02:36:59.97#ibcon#end of sib2, iclass 5, count 2 2006.201.02:36:59.97#ibcon#*after write, iclass 5, count 2 2006.201.02:36:59.97#ibcon#*before return 0, iclass 5, count 2 2006.201.02:36:59.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:59.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.02:36:59.97#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.02:36:59.97#ibcon#ireg 7 cls_cnt 0 2006.201.02:36:59.97#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:37:00.09#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:37:00.09#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:37:00.09#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:37:00.09#ibcon#first serial, iclass 5, count 0 2006.201.02:37:00.09#ibcon#enter sib2, iclass 5, count 0 2006.201.02:37:00.09#ibcon#flushed, iclass 5, count 0 2006.201.02:37:00.09#ibcon#about to write, iclass 5, count 0 2006.201.02:37:00.09#ibcon#wrote, iclass 5, count 0 2006.201.02:37:00.09#ibcon#about to read 3, iclass 5, count 0 2006.201.02:37:00.11#ibcon#read 3, iclass 5, count 0 2006.201.02:37:00.11#ibcon#about to read 4, iclass 5, count 0 2006.201.02:37:00.11#ibcon#read 4, iclass 5, count 0 2006.201.02:37:00.11#ibcon#about to read 5, iclass 5, count 0 2006.201.02:37:00.11#ibcon#read 5, iclass 5, count 0 2006.201.02:37:00.11#ibcon#about to read 6, iclass 5, count 0 2006.201.02:37:00.11#ibcon#read 6, iclass 5, count 0 2006.201.02:37:00.11#ibcon#end of sib2, iclass 5, count 0 2006.201.02:37:00.11#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:37:00.11#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:37:00.11#ibcon#[27=USB\r\n] 2006.201.02:37:00.11#ibcon#*before write, iclass 5, count 0 2006.201.02:37:00.11#ibcon#enter sib2, iclass 5, count 0 2006.201.02:37:00.11#ibcon#flushed, iclass 5, count 0 2006.201.02:37:00.11#ibcon#about to write, iclass 5, count 0 2006.201.02:37:00.11#ibcon#wrote, iclass 5, count 0 2006.201.02:37:00.11#ibcon#about to read 3, iclass 5, count 0 2006.201.02:37:00.14#ibcon#read 3, iclass 5, count 0 2006.201.02:37:00.14#ibcon#about to read 4, iclass 5, count 0 2006.201.02:37:00.14#ibcon#read 4, iclass 5, count 0 2006.201.02:37:00.14#ibcon#about to read 5, iclass 5, count 0 2006.201.02:37:00.14#ibcon#read 5, iclass 5, count 0 2006.201.02:37:00.14#ibcon#about to read 6, iclass 5, count 0 2006.201.02:37:00.14#ibcon#read 6, iclass 5, count 0 2006.201.02:37:00.14#ibcon#end of sib2, iclass 5, count 0 2006.201.02:37:00.14#ibcon#*after write, iclass 5, count 0 2006.201.02:37:00.14#ibcon#*before return 0, iclass 5, count 0 2006.201.02:37:00.14#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:37:00.14#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.02:37:00.14#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:37:00.14#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:37:00.14$vck44/vblo=6,719.99 2006.201.02:37:00.14#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.02:37:00.14#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.02:37:00.14#ibcon#ireg 17 cls_cnt 0 2006.201.02:37:00.14#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:37:00.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:37:00.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:37:00.14#ibcon#enter wrdev, iclass 7, count 0 2006.201.02:37:00.14#ibcon#first serial, iclass 7, count 0 2006.201.02:37:00.14#ibcon#enter sib2, iclass 7, count 0 2006.201.02:37:00.14#ibcon#flushed, iclass 7, count 0 2006.201.02:37:00.14#ibcon#about to write, iclass 7, count 0 2006.201.02:37:00.14#ibcon#wrote, iclass 7, count 0 2006.201.02:37:00.14#ibcon#about to read 3, iclass 7, count 0 2006.201.02:37:00.16#ibcon#read 3, iclass 7, count 0 2006.201.02:37:00.16#ibcon#about to read 4, iclass 7, count 0 2006.201.02:37:00.16#ibcon#read 4, iclass 7, count 0 2006.201.02:37:00.16#ibcon#about to read 5, iclass 7, count 0 2006.201.02:37:00.16#ibcon#read 5, iclass 7, count 0 2006.201.02:37:00.16#ibcon#about to read 6, iclass 7, count 0 2006.201.02:37:00.16#ibcon#read 6, iclass 7, count 0 2006.201.02:37:00.16#ibcon#end of sib2, iclass 7, count 0 2006.201.02:37:00.16#ibcon#*mode == 0, iclass 7, count 0 2006.201.02:37:00.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.02:37:00.16#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:37:00.16#ibcon#*before write, iclass 7, count 0 2006.201.02:37:00.16#ibcon#enter sib2, iclass 7, count 0 2006.201.02:37:00.16#ibcon#flushed, iclass 7, count 0 2006.201.02:37:00.16#ibcon#about to write, iclass 7, count 0 2006.201.02:37:00.16#ibcon#wrote, iclass 7, count 0 2006.201.02:37:00.16#ibcon#about to read 3, iclass 7, count 0 2006.201.02:37:00.20#ibcon#read 3, iclass 7, count 0 2006.201.02:37:00.20#ibcon#about to read 4, iclass 7, count 0 2006.201.02:37:00.20#ibcon#read 4, iclass 7, count 0 2006.201.02:37:00.20#ibcon#about to read 5, iclass 7, count 0 2006.201.02:37:00.20#ibcon#read 5, iclass 7, count 0 2006.201.02:37:00.20#ibcon#about to read 6, iclass 7, count 0 2006.201.02:37:00.20#ibcon#read 6, iclass 7, count 0 2006.201.02:37:00.20#ibcon#end of sib2, iclass 7, count 0 2006.201.02:37:00.20#ibcon#*after write, iclass 7, count 0 2006.201.02:37:00.20#ibcon#*before return 0, iclass 7, count 0 2006.201.02:37:00.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:37:00.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.02:37:00.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.02:37:00.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.02:37:00.20$vck44/vb=6,4 2006.201.02:37:00.20#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.02:37:00.20#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.02:37:00.20#ibcon#ireg 11 cls_cnt 2 2006.201.02:37:00.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:37:00.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:37:00.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:37:00.26#ibcon#enter wrdev, iclass 11, count 2 2006.201.02:37:00.26#ibcon#first serial, iclass 11, count 2 2006.201.02:37:00.26#ibcon#enter sib2, iclass 11, count 2 2006.201.02:37:00.26#ibcon#flushed, iclass 11, count 2 2006.201.02:37:00.26#ibcon#about to write, iclass 11, count 2 2006.201.02:37:00.26#ibcon#wrote, iclass 11, count 2 2006.201.02:37:00.26#ibcon#about to read 3, iclass 11, count 2 2006.201.02:37:00.28#ibcon#read 3, iclass 11, count 2 2006.201.02:37:00.28#ibcon#about to read 4, iclass 11, count 2 2006.201.02:37:00.28#ibcon#read 4, iclass 11, count 2 2006.201.02:37:00.28#ibcon#about to read 5, iclass 11, count 2 2006.201.02:37:00.28#ibcon#read 5, iclass 11, count 2 2006.201.02:37:00.28#ibcon#about to read 6, iclass 11, count 2 2006.201.02:37:00.28#ibcon#read 6, iclass 11, count 2 2006.201.02:37:00.28#ibcon#end of sib2, iclass 11, count 2 2006.201.02:37:00.28#ibcon#*mode == 0, iclass 11, count 2 2006.201.02:37:00.28#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.02:37:00.28#ibcon#[27=AT06-04\r\n] 2006.201.02:37:00.28#ibcon#*before write, iclass 11, count 2 2006.201.02:37:00.28#ibcon#enter sib2, iclass 11, count 2 2006.201.02:37:00.28#ibcon#flushed, iclass 11, count 2 2006.201.02:37:00.28#ibcon#about to write, iclass 11, count 2 2006.201.02:37:00.28#ibcon#wrote, iclass 11, count 2 2006.201.02:37:00.28#ibcon#about to read 3, iclass 11, count 2 2006.201.02:37:00.31#ibcon#read 3, iclass 11, count 2 2006.201.02:37:00.31#ibcon#about to read 4, iclass 11, count 2 2006.201.02:37:00.31#ibcon#read 4, iclass 11, count 2 2006.201.02:37:00.31#ibcon#about to read 5, iclass 11, count 2 2006.201.02:37:00.31#ibcon#read 5, iclass 11, count 2 2006.201.02:37:00.31#ibcon#about to read 6, iclass 11, count 2 2006.201.02:37:00.31#ibcon#read 6, iclass 11, count 2 2006.201.02:37:00.31#ibcon#end of sib2, iclass 11, count 2 2006.201.02:37:00.31#ibcon#*after write, iclass 11, count 2 2006.201.02:37:00.31#ibcon#*before return 0, iclass 11, count 2 2006.201.02:37:00.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:37:00.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.02:37:00.31#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.02:37:00.31#ibcon#ireg 7 cls_cnt 0 2006.201.02:37:00.31#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:37:00.43#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:37:00.43#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:37:00.43#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:37:00.43#ibcon#first serial, iclass 11, count 0 2006.201.02:37:00.43#ibcon#enter sib2, iclass 11, count 0 2006.201.02:37:00.43#ibcon#flushed, iclass 11, count 0 2006.201.02:37:00.43#ibcon#about to write, iclass 11, count 0 2006.201.02:37:00.43#ibcon#wrote, iclass 11, count 0 2006.201.02:37:00.43#ibcon#about to read 3, iclass 11, count 0 2006.201.02:37:00.45#ibcon#read 3, iclass 11, count 0 2006.201.02:37:00.45#ibcon#about to read 4, iclass 11, count 0 2006.201.02:37:00.45#ibcon#read 4, iclass 11, count 0 2006.201.02:37:00.45#ibcon#about to read 5, iclass 11, count 0 2006.201.02:37:00.45#ibcon#read 5, iclass 11, count 0 2006.201.02:37:00.45#ibcon#about to read 6, iclass 11, count 0 2006.201.02:37:00.45#ibcon#read 6, iclass 11, count 0 2006.201.02:37:00.45#ibcon#end of sib2, iclass 11, count 0 2006.201.02:37:00.45#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:37:00.45#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:37:00.45#ibcon#[27=USB\r\n] 2006.201.02:37:00.45#ibcon#*before write, iclass 11, count 0 2006.201.02:37:00.45#ibcon#enter sib2, iclass 11, count 0 2006.201.02:37:00.45#ibcon#flushed, iclass 11, count 0 2006.201.02:37:00.45#ibcon#about to write, iclass 11, count 0 2006.201.02:37:00.45#ibcon#wrote, iclass 11, count 0 2006.201.02:37:00.45#ibcon#about to read 3, iclass 11, count 0 2006.201.02:37:00.48#ibcon#read 3, iclass 11, count 0 2006.201.02:37:00.48#ibcon#about to read 4, iclass 11, count 0 2006.201.02:37:00.48#ibcon#read 4, iclass 11, count 0 2006.201.02:37:00.48#ibcon#about to read 5, iclass 11, count 0 2006.201.02:37:00.48#ibcon#read 5, iclass 11, count 0 2006.201.02:37:00.48#ibcon#about to read 6, iclass 11, count 0 2006.201.02:37:00.48#ibcon#read 6, iclass 11, count 0 2006.201.02:37:00.48#ibcon#end of sib2, iclass 11, count 0 2006.201.02:37:00.48#ibcon#*after write, iclass 11, count 0 2006.201.02:37:00.48#ibcon#*before return 0, iclass 11, count 0 2006.201.02:37:00.48#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:37:00.48#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.02:37:00.48#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:37:00.48#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:37:00.48$vck44/vblo=7,734.99 2006.201.02:37:00.48#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.02:37:00.48#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.02:37:00.48#ibcon#ireg 17 cls_cnt 0 2006.201.02:37:00.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:37:00.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:37:00.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:37:00.48#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:37:00.48#ibcon#first serial, iclass 13, count 0 2006.201.02:37:00.48#ibcon#enter sib2, iclass 13, count 0 2006.201.02:37:00.48#ibcon#flushed, iclass 13, count 0 2006.201.02:37:00.48#ibcon#about to write, iclass 13, count 0 2006.201.02:37:00.48#ibcon#wrote, iclass 13, count 0 2006.201.02:37:00.48#ibcon#about to read 3, iclass 13, count 0 2006.201.02:37:00.50#ibcon#read 3, iclass 13, count 0 2006.201.02:37:00.50#ibcon#about to read 4, iclass 13, count 0 2006.201.02:37:00.50#ibcon#read 4, iclass 13, count 0 2006.201.02:37:00.50#ibcon#about to read 5, iclass 13, count 0 2006.201.02:37:00.50#ibcon#read 5, iclass 13, count 0 2006.201.02:37:00.50#ibcon#about to read 6, iclass 13, count 0 2006.201.02:37:00.50#ibcon#read 6, iclass 13, count 0 2006.201.02:37:00.50#ibcon#end of sib2, iclass 13, count 0 2006.201.02:37:00.50#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:37:00.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:37:00.50#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:37:00.50#ibcon#*before write, iclass 13, count 0 2006.201.02:37:00.50#ibcon#enter sib2, iclass 13, count 0 2006.201.02:37:00.50#ibcon#flushed, iclass 13, count 0 2006.201.02:37:00.50#ibcon#about to write, iclass 13, count 0 2006.201.02:37:00.50#ibcon#wrote, iclass 13, count 0 2006.201.02:37:00.50#ibcon#about to read 3, iclass 13, count 0 2006.201.02:37:00.54#ibcon#read 3, iclass 13, count 0 2006.201.02:37:00.54#ibcon#about to read 4, iclass 13, count 0 2006.201.02:37:00.54#ibcon#read 4, iclass 13, count 0 2006.201.02:37:00.54#ibcon#about to read 5, iclass 13, count 0 2006.201.02:37:00.54#ibcon#read 5, iclass 13, count 0 2006.201.02:37:00.54#ibcon#about to read 6, iclass 13, count 0 2006.201.02:37:00.54#ibcon#read 6, iclass 13, count 0 2006.201.02:37:00.54#ibcon#end of sib2, iclass 13, count 0 2006.201.02:37:00.54#ibcon#*after write, iclass 13, count 0 2006.201.02:37:00.54#ibcon#*before return 0, iclass 13, count 0 2006.201.02:37:00.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:37:00.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.02:37:00.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:37:00.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:37:00.54$vck44/vb=7,4 2006.201.02:37:00.54#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.02:37:00.54#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.02:37:00.54#ibcon#ireg 11 cls_cnt 2 2006.201.02:37:00.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:37:00.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:37:00.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:37:00.60#ibcon#enter wrdev, iclass 15, count 2 2006.201.02:37:00.60#ibcon#first serial, iclass 15, count 2 2006.201.02:37:00.60#ibcon#enter sib2, iclass 15, count 2 2006.201.02:37:00.60#ibcon#flushed, iclass 15, count 2 2006.201.02:37:00.60#ibcon#about to write, iclass 15, count 2 2006.201.02:37:00.60#ibcon#wrote, iclass 15, count 2 2006.201.02:37:00.60#ibcon#about to read 3, iclass 15, count 2 2006.201.02:37:00.62#ibcon#read 3, iclass 15, count 2 2006.201.02:37:00.62#ibcon#about to read 4, iclass 15, count 2 2006.201.02:37:00.62#ibcon#read 4, iclass 15, count 2 2006.201.02:37:00.62#ibcon#about to read 5, iclass 15, count 2 2006.201.02:37:00.62#ibcon#read 5, iclass 15, count 2 2006.201.02:37:00.62#ibcon#about to read 6, iclass 15, count 2 2006.201.02:37:00.62#ibcon#read 6, iclass 15, count 2 2006.201.02:37:00.62#ibcon#end of sib2, iclass 15, count 2 2006.201.02:37:00.62#ibcon#*mode == 0, iclass 15, count 2 2006.201.02:37:00.62#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.02:37:00.62#ibcon#[27=AT07-04\r\n] 2006.201.02:37:00.62#ibcon#*before write, iclass 15, count 2 2006.201.02:37:00.62#ibcon#enter sib2, iclass 15, count 2 2006.201.02:37:00.62#ibcon#flushed, iclass 15, count 2 2006.201.02:37:00.62#ibcon#about to write, iclass 15, count 2 2006.201.02:37:00.62#ibcon#wrote, iclass 15, count 2 2006.201.02:37:00.62#ibcon#about to read 3, iclass 15, count 2 2006.201.02:37:00.65#ibcon#read 3, iclass 15, count 2 2006.201.02:37:00.65#ibcon#about to read 4, iclass 15, count 2 2006.201.02:37:00.65#ibcon#read 4, iclass 15, count 2 2006.201.02:37:00.65#ibcon#about to read 5, iclass 15, count 2 2006.201.02:37:00.65#ibcon#read 5, iclass 15, count 2 2006.201.02:37:00.65#ibcon#about to read 6, iclass 15, count 2 2006.201.02:37:00.65#ibcon#read 6, iclass 15, count 2 2006.201.02:37:00.65#ibcon#end of sib2, iclass 15, count 2 2006.201.02:37:00.65#ibcon#*after write, iclass 15, count 2 2006.201.02:37:00.65#ibcon#*before return 0, iclass 15, count 2 2006.201.02:37:00.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:37:00.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.02:37:00.65#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.02:37:00.65#ibcon#ireg 7 cls_cnt 0 2006.201.02:37:00.65#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:37:00.77#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:37:00.77#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:37:00.77#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:37:00.77#ibcon#first serial, iclass 15, count 0 2006.201.02:37:00.77#ibcon#enter sib2, iclass 15, count 0 2006.201.02:37:00.77#ibcon#flushed, iclass 15, count 0 2006.201.02:37:00.77#ibcon#about to write, iclass 15, count 0 2006.201.02:37:00.77#ibcon#wrote, iclass 15, count 0 2006.201.02:37:00.77#ibcon#about to read 3, iclass 15, count 0 2006.201.02:37:00.79#ibcon#read 3, iclass 15, count 0 2006.201.02:37:00.79#ibcon#about to read 4, iclass 15, count 0 2006.201.02:37:00.79#ibcon#read 4, iclass 15, count 0 2006.201.02:37:00.79#ibcon#about to read 5, iclass 15, count 0 2006.201.02:37:00.79#ibcon#read 5, iclass 15, count 0 2006.201.02:37:00.79#ibcon#about to read 6, iclass 15, count 0 2006.201.02:37:00.79#ibcon#read 6, iclass 15, count 0 2006.201.02:37:00.79#ibcon#end of sib2, iclass 15, count 0 2006.201.02:37:00.79#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:37:00.79#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:37:00.79#ibcon#[27=USB\r\n] 2006.201.02:37:00.79#ibcon#*before write, iclass 15, count 0 2006.201.02:37:00.79#ibcon#enter sib2, iclass 15, count 0 2006.201.02:37:00.79#ibcon#flushed, iclass 15, count 0 2006.201.02:37:00.79#ibcon#about to write, iclass 15, count 0 2006.201.02:37:00.79#ibcon#wrote, iclass 15, count 0 2006.201.02:37:00.79#ibcon#about to read 3, iclass 15, count 0 2006.201.02:37:00.82#ibcon#read 3, iclass 15, count 0 2006.201.02:37:00.82#ibcon#about to read 4, iclass 15, count 0 2006.201.02:37:00.82#ibcon#read 4, iclass 15, count 0 2006.201.02:37:00.82#ibcon#about to read 5, iclass 15, count 0 2006.201.02:37:00.82#ibcon#read 5, iclass 15, count 0 2006.201.02:37:00.82#ibcon#about to read 6, iclass 15, count 0 2006.201.02:37:00.82#ibcon#read 6, iclass 15, count 0 2006.201.02:37:00.82#ibcon#end of sib2, iclass 15, count 0 2006.201.02:37:00.82#ibcon#*after write, iclass 15, count 0 2006.201.02:37:00.82#ibcon#*before return 0, iclass 15, count 0 2006.201.02:37:00.82#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:37:00.82#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.02:37:00.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:37:00.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:37:00.82$vck44/vblo=8,744.99 2006.201.02:37:00.82#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.02:37:00.82#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.02:37:00.82#ibcon#ireg 17 cls_cnt 0 2006.201.02:37:00.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:37:00.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:37:00.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:37:00.82#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:37:00.82#ibcon#first serial, iclass 17, count 0 2006.201.02:37:00.82#ibcon#enter sib2, iclass 17, count 0 2006.201.02:37:00.82#ibcon#flushed, iclass 17, count 0 2006.201.02:37:00.82#ibcon#about to write, iclass 17, count 0 2006.201.02:37:00.82#ibcon#wrote, iclass 17, count 0 2006.201.02:37:00.82#ibcon#about to read 3, iclass 17, count 0 2006.201.02:37:00.84#ibcon#read 3, iclass 17, count 0 2006.201.02:37:00.84#ibcon#about to read 4, iclass 17, count 0 2006.201.02:37:00.84#ibcon#read 4, iclass 17, count 0 2006.201.02:37:00.84#ibcon#about to read 5, iclass 17, count 0 2006.201.02:37:00.84#ibcon#read 5, iclass 17, count 0 2006.201.02:37:00.84#ibcon#about to read 6, iclass 17, count 0 2006.201.02:37:00.84#ibcon#read 6, iclass 17, count 0 2006.201.02:37:00.84#ibcon#end of sib2, iclass 17, count 0 2006.201.02:37:00.84#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:37:00.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:37:00.84#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:37:00.84#ibcon#*before write, iclass 17, count 0 2006.201.02:37:00.84#ibcon#enter sib2, iclass 17, count 0 2006.201.02:37:00.84#ibcon#flushed, iclass 17, count 0 2006.201.02:37:00.84#ibcon#about to write, iclass 17, count 0 2006.201.02:37:00.84#ibcon#wrote, iclass 17, count 0 2006.201.02:37:00.84#ibcon#about to read 3, iclass 17, count 0 2006.201.02:37:00.88#ibcon#read 3, iclass 17, count 0 2006.201.02:37:00.88#ibcon#about to read 4, iclass 17, count 0 2006.201.02:37:00.88#ibcon#read 4, iclass 17, count 0 2006.201.02:37:00.88#ibcon#about to read 5, iclass 17, count 0 2006.201.02:37:00.88#ibcon#read 5, iclass 17, count 0 2006.201.02:37:00.88#ibcon#about to read 6, iclass 17, count 0 2006.201.02:37:00.88#ibcon#read 6, iclass 17, count 0 2006.201.02:37:00.88#ibcon#end of sib2, iclass 17, count 0 2006.201.02:37:00.88#ibcon#*after write, iclass 17, count 0 2006.201.02:37:00.88#ibcon#*before return 0, iclass 17, count 0 2006.201.02:37:00.88#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:37:00.88#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.02:37:00.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:37:00.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:37:00.88$vck44/vb=8,4 2006.201.02:37:00.88#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.02:37:00.88#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.02:37:00.88#ibcon#ireg 11 cls_cnt 2 2006.201.02:37:00.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:37:00.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:37:00.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:37:00.94#ibcon#enter wrdev, iclass 19, count 2 2006.201.02:37:00.94#ibcon#first serial, iclass 19, count 2 2006.201.02:37:00.94#ibcon#enter sib2, iclass 19, count 2 2006.201.02:37:00.94#ibcon#flushed, iclass 19, count 2 2006.201.02:37:00.94#ibcon#about to write, iclass 19, count 2 2006.201.02:37:00.94#ibcon#wrote, iclass 19, count 2 2006.201.02:37:00.94#ibcon#about to read 3, iclass 19, count 2 2006.201.02:37:00.96#ibcon#read 3, iclass 19, count 2 2006.201.02:37:00.96#ibcon#about to read 4, iclass 19, count 2 2006.201.02:37:00.96#ibcon#read 4, iclass 19, count 2 2006.201.02:37:00.96#ibcon#about to read 5, iclass 19, count 2 2006.201.02:37:00.96#ibcon#read 5, iclass 19, count 2 2006.201.02:37:00.96#ibcon#about to read 6, iclass 19, count 2 2006.201.02:37:00.96#ibcon#read 6, iclass 19, count 2 2006.201.02:37:00.96#ibcon#end of sib2, iclass 19, count 2 2006.201.02:37:00.96#ibcon#*mode == 0, iclass 19, count 2 2006.201.02:37:00.96#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.02:37:00.96#ibcon#[27=AT08-04\r\n] 2006.201.02:37:00.96#ibcon#*before write, iclass 19, count 2 2006.201.02:37:00.96#ibcon#enter sib2, iclass 19, count 2 2006.201.02:37:00.96#ibcon#flushed, iclass 19, count 2 2006.201.02:37:00.96#ibcon#about to write, iclass 19, count 2 2006.201.02:37:00.96#ibcon#wrote, iclass 19, count 2 2006.201.02:37:00.96#ibcon#about to read 3, iclass 19, count 2 2006.201.02:37:00.99#ibcon#read 3, iclass 19, count 2 2006.201.02:37:00.99#ibcon#about to read 4, iclass 19, count 2 2006.201.02:37:00.99#ibcon#read 4, iclass 19, count 2 2006.201.02:37:00.99#ibcon#about to read 5, iclass 19, count 2 2006.201.02:37:00.99#ibcon#read 5, iclass 19, count 2 2006.201.02:37:00.99#ibcon#about to read 6, iclass 19, count 2 2006.201.02:37:00.99#ibcon#read 6, iclass 19, count 2 2006.201.02:37:00.99#ibcon#end of sib2, iclass 19, count 2 2006.201.02:37:00.99#ibcon#*after write, iclass 19, count 2 2006.201.02:37:00.99#ibcon#*before return 0, iclass 19, count 2 2006.201.02:37:00.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:37:00.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.02:37:00.99#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.02:37:00.99#ibcon#ireg 7 cls_cnt 0 2006.201.02:37:00.99#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:37:01.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:37:01.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:37:01.11#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:37:01.11#ibcon#first serial, iclass 19, count 0 2006.201.02:37:01.11#ibcon#enter sib2, iclass 19, count 0 2006.201.02:37:01.11#ibcon#flushed, iclass 19, count 0 2006.201.02:37:01.11#ibcon#about to write, iclass 19, count 0 2006.201.02:37:01.11#ibcon#wrote, iclass 19, count 0 2006.201.02:37:01.11#ibcon#about to read 3, iclass 19, count 0 2006.201.02:37:01.13#ibcon#read 3, iclass 19, count 0 2006.201.02:37:01.13#ibcon#about to read 4, iclass 19, count 0 2006.201.02:37:01.13#ibcon#read 4, iclass 19, count 0 2006.201.02:37:01.13#ibcon#about to read 5, iclass 19, count 0 2006.201.02:37:01.13#ibcon#read 5, iclass 19, count 0 2006.201.02:37:01.13#ibcon#about to read 6, iclass 19, count 0 2006.201.02:37:01.13#ibcon#read 6, iclass 19, count 0 2006.201.02:37:01.13#ibcon#end of sib2, iclass 19, count 0 2006.201.02:37:01.13#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:37:01.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:37:01.13#ibcon#[27=USB\r\n] 2006.201.02:37:01.13#ibcon#*before write, iclass 19, count 0 2006.201.02:37:01.13#ibcon#enter sib2, iclass 19, count 0 2006.201.02:37:01.13#ibcon#flushed, iclass 19, count 0 2006.201.02:37:01.13#ibcon#about to write, iclass 19, count 0 2006.201.02:37:01.13#ibcon#wrote, iclass 19, count 0 2006.201.02:37:01.13#ibcon#about to read 3, iclass 19, count 0 2006.201.02:37:01.16#ibcon#read 3, iclass 19, count 0 2006.201.02:37:01.16#ibcon#about to read 4, iclass 19, count 0 2006.201.02:37:01.16#ibcon#read 4, iclass 19, count 0 2006.201.02:37:01.16#ibcon#about to read 5, iclass 19, count 0 2006.201.02:37:01.16#ibcon#read 5, iclass 19, count 0 2006.201.02:37:01.16#ibcon#about to read 6, iclass 19, count 0 2006.201.02:37:01.16#ibcon#read 6, iclass 19, count 0 2006.201.02:37:01.16#ibcon#end of sib2, iclass 19, count 0 2006.201.02:37:01.16#ibcon#*after write, iclass 19, count 0 2006.201.02:37:01.16#ibcon#*before return 0, iclass 19, count 0 2006.201.02:37:01.16#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:37:01.16#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.02:37:01.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:37:01.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:37:01.16$vck44/vabw=wide 2006.201.02:37:01.16#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.02:37:01.16#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.02:37:01.16#ibcon#ireg 8 cls_cnt 0 2006.201.02:37:01.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:37:01.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:37:01.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:37:01.16#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:37:01.16#ibcon#first serial, iclass 21, count 0 2006.201.02:37:01.16#ibcon#enter sib2, iclass 21, count 0 2006.201.02:37:01.16#ibcon#flushed, iclass 21, count 0 2006.201.02:37:01.16#ibcon#about to write, iclass 21, count 0 2006.201.02:37:01.16#ibcon#wrote, iclass 21, count 0 2006.201.02:37:01.16#ibcon#about to read 3, iclass 21, count 0 2006.201.02:37:01.18#ibcon#read 3, iclass 21, count 0 2006.201.02:37:01.18#ibcon#about to read 4, iclass 21, count 0 2006.201.02:37:01.18#ibcon#read 4, iclass 21, count 0 2006.201.02:37:01.18#ibcon#about to read 5, iclass 21, count 0 2006.201.02:37:01.18#ibcon#read 5, iclass 21, count 0 2006.201.02:37:01.18#ibcon#about to read 6, iclass 21, count 0 2006.201.02:37:01.18#ibcon#read 6, iclass 21, count 0 2006.201.02:37:01.18#ibcon#end of sib2, iclass 21, count 0 2006.201.02:37:01.18#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:37:01.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:37:01.18#ibcon#[25=BW32\r\n] 2006.201.02:37:01.18#ibcon#*before write, iclass 21, count 0 2006.201.02:37:01.18#ibcon#enter sib2, iclass 21, count 0 2006.201.02:37:01.18#ibcon#flushed, iclass 21, count 0 2006.201.02:37:01.18#ibcon#about to write, iclass 21, count 0 2006.201.02:37:01.18#ibcon#wrote, iclass 21, count 0 2006.201.02:37:01.18#ibcon#about to read 3, iclass 21, count 0 2006.201.02:37:01.22#ibcon#read 3, iclass 21, count 0 2006.201.02:37:01.22#ibcon#about to read 4, iclass 21, count 0 2006.201.02:37:01.22#ibcon#read 4, iclass 21, count 0 2006.201.02:37:01.22#ibcon#about to read 5, iclass 21, count 0 2006.201.02:37:01.22#ibcon#read 5, iclass 21, count 0 2006.201.02:37:01.22#ibcon#about to read 6, iclass 21, count 0 2006.201.02:37:01.22#ibcon#read 6, iclass 21, count 0 2006.201.02:37:01.22#ibcon#end of sib2, iclass 21, count 0 2006.201.02:37:01.22#ibcon#*after write, iclass 21, count 0 2006.201.02:37:01.22#ibcon#*before return 0, iclass 21, count 0 2006.201.02:37:01.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:37:01.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.02:37:01.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:37:01.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:37:01.22$vck44/vbbw=wide 2006.201.02:37:01.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.02:37:01.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.02:37:01.22#ibcon#ireg 8 cls_cnt 0 2006.201.02:37:01.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:37:01.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:37:01.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:37:01.28#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:37:01.28#ibcon#first serial, iclass 23, count 0 2006.201.02:37:01.28#ibcon#enter sib2, iclass 23, count 0 2006.201.02:37:01.28#ibcon#flushed, iclass 23, count 0 2006.201.02:37:01.28#ibcon#about to write, iclass 23, count 0 2006.201.02:37:01.28#ibcon#wrote, iclass 23, count 0 2006.201.02:37:01.28#ibcon#about to read 3, iclass 23, count 0 2006.201.02:37:01.30#ibcon#read 3, iclass 23, count 0 2006.201.02:37:01.30#ibcon#about to read 4, iclass 23, count 0 2006.201.02:37:01.30#ibcon#read 4, iclass 23, count 0 2006.201.02:37:01.30#ibcon#about to read 5, iclass 23, count 0 2006.201.02:37:01.30#ibcon#read 5, iclass 23, count 0 2006.201.02:37:01.30#ibcon#about to read 6, iclass 23, count 0 2006.201.02:37:01.30#ibcon#read 6, iclass 23, count 0 2006.201.02:37:01.30#ibcon#end of sib2, iclass 23, count 0 2006.201.02:37:01.30#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:37:01.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:37:01.30#ibcon#[27=BW32\r\n] 2006.201.02:37:01.30#ibcon#*before write, iclass 23, count 0 2006.201.02:37:01.30#ibcon#enter sib2, iclass 23, count 0 2006.201.02:37:01.30#ibcon#flushed, iclass 23, count 0 2006.201.02:37:01.30#ibcon#about to write, iclass 23, count 0 2006.201.02:37:01.30#ibcon#wrote, iclass 23, count 0 2006.201.02:37:01.30#ibcon#about to read 3, iclass 23, count 0 2006.201.02:37:01.33#ibcon#read 3, iclass 23, count 0 2006.201.02:37:01.33#ibcon#about to read 4, iclass 23, count 0 2006.201.02:37:01.33#ibcon#read 4, iclass 23, count 0 2006.201.02:37:01.33#ibcon#about to read 5, iclass 23, count 0 2006.201.02:37:01.33#ibcon#read 5, iclass 23, count 0 2006.201.02:37:01.33#ibcon#about to read 6, iclass 23, count 0 2006.201.02:37:01.33#ibcon#read 6, iclass 23, count 0 2006.201.02:37:01.33#ibcon#end of sib2, iclass 23, count 0 2006.201.02:37:01.33#ibcon#*after write, iclass 23, count 0 2006.201.02:37:01.33#ibcon#*before return 0, iclass 23, count 0 2006.201.02:37:01.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:37:01.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:37:01.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:37:01.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:37:01.33$setupk4/ifdk4 2006.201.02:37:01.33$ifdk4/lo= 2006.201.02:37:01.33$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:37:01.33$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:37:01.33$ifdk4/patch= 2006.201.02:37:01.33$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:37:01.33$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:37:01.33$setupk4/!*+20s 2006.201.02:37:01.51#abcon#<5=/04 2.7 5.0 22.95 911004.7\r\n> 2006.201.02:37:01.53#abcon#{5=INTERFACE CLEAR} 2006.201.02:37:01.59#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:37:11.68#abcon#<5=/04 2.6 4.9 22.95 911004.6\r\n> 2006.201.02:37:11.70#abcon#{5=INTERFACE CLEAR} 2006.201.02:37:11.76#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:37:15.81$setupk4/"tpicd 2006.201.02:37:15.81$setupk4/echo=off 2006.201.02:37:15.81$setupk4/xlog=off 2006.201.02:37:15.81:!2006.201.02:39:38 2006.201.02:37:17.14#trakl#Source acquired 2006.201.02:37:17.14#flagr#flagr/antenna,acquired 2006.201.02:39:38.00:preob 2006.201.02:39:39.13/onsource/TRACKING 2006.201.02:39:39.13:!2006.201.02:39:48 2006.201.02:39:48.00:"tape 2006.201.02:39:48.00:"st=record 2006.201.02:39:48.00:data_valid=on 2006.201.02:39:48.00:midob 2006.201.02:39:48.13/onsource/TRACKING 2006.201.02:39:48.13/wx/22.94,1004.6,90 2006.201.02:39:48.30/cable/+6.4677E-03 2006.201.02:39:49.39/va/01,08,usb,yes,28,30 2006.201.02:39:49.39/va/02,07,usb,yes,30,31 2006.201.02:39:49.39/va/03,08,usb,yes,27,28 2006.201.02:39:49.39/va/04,07,usb,yes,31,33 2006.201.02:39:49.39/va/05,04,usb,yes,28,28 2006.201.02:39:49.39/va/06,05,usb,yes,28,27 2006.201.02:39:49.39/va/07,05,usb,yes,27,28 2006.201.02:39:49.39/va/08,04,usb,yes,26,32 2006.201.02:39:49.62/valo/01,524.99,yes,locked 2006.201.02:39:49.62/valo/02,534.99,yes,locked 2006.201.02:39:49.62/valo/03,564.99,yes,locked 2006.201.02:39:49.62/valo/04,624.99,yes,locked 2006.201.02:39:49.62/valo/05,734.99,yes,locked 2006.201.02:39:49.62/valo/06,814.99,yes,locked 2006.201.02:39:49.62/valo/07,864.99,yes,locked 2006.201.02:39:49.62/valo/08,884.99,yes,locked 2006.201.02:39:50.71/vb/01,04,usb,yes,28,26 2006.201.02:39:50.71/vb/02,05,usb,yes,27,27 2006.201.02:39:50.71/vb/03,04,usb,yes,28,31 2006.201.02:39:50.71/vb/04,05,usb,yes,28,27 2006.201.02:39:50.71/vb/05,04,usb,yes,25,27 2006.201.02:39:50.71/vb/06,04,usb,yes,29,25 2006.201.02:39:50.71/vb/07,04,usb,yes,29,29 2006.201.02:39:50.71/vb/08,04,usb,yes,26,30 2006.201.02:39:50.95/vblo/01,629.99,yes,locked 2006.201.02:39:50.95/vblo/02,634.99,yes,locked 2006.201.02:39:50.95/vblo/03,649.99,yes,locked 2006.201.02:39:50.95/vblo/04,679.99,yes,locked 2006.201.02:39:50.95/vblo/05,709.99,yes,locked 2006.201.02:39:50.95/vblo/06,719.99,yes,locked 2006.201.02:39:50.95/vblo/07,734.99,yes,locked 2006.201.02:39:50.95/vblo/08,744.99,yes,locked 2006.201.02:39:51.10/vabw/8 2006.201.02:39:51.25/vbbw/8 2006.201.02:39:51.34/xfe/off,on,15.5 2006.201.02:39:51.72/ifatt/23,28,28,28 2006.201.02:39:52.04/fmout-gps/S +4.46E-07 2006.201.02:39:52.11:!2006.201.02:43:28 2006.201.02:43:28.00:data_valid=off 2006.201.02:43:28.00:"et 2006.201.02:43:28.00:!+3s 2006.201.02:43:31.02:"tape 2006.201.02:43:31.02:postob 2006.201.02:43:31.09/cable/+6.4657E-03 2006.201.02:43:31.09/wx/22.91,1004.6,92 2006.201.02:43:31.17/fmout-gps/S +4.48E-07 2006.201.02:43:31.18:scan_name=201-0246,jd0607,520 2006.201.02:43:31.18:source=1418+546,141946.60,542314.8,2000.0,cw 2006.201.02:43:33.14#flagr#flagr/antenna,new-source 2006.201.02:43:33.14:checkk5 2006.201.02:43:33.84/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:43:34.23/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:43:34.62/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:43:35.08/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:43:35.57/chk_obsdata//k5ts1/T2010239??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.02:43:36.00/chk_obsdata//k5ts2/T2010239??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.02:43:36.41/chk_obsdata//k5ts3/T2010239??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.02:43:36.83/chk_obsdata//k5ts4/T2010239??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.02:43:37.59/k5log//k5ts1_log_newline 2006.201.02:43:38.36/k5log//k5ts2_log_newline 2006.201.02:43:40.07/k5log//k5ts3_log_newline 2006.201.02:43:40.88/k5log//k5ts4_log_newline 2006.201.02:43:40.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:43:40.90:setupk4=1 2006.201.02:43:40.90$setupk4/echo=on 2006.201.02:43:40.90$setupk4/pcalon 2006.201.02:43:40.91$pcalon/"no phase cal control is implemented here 2006.201.02:43:40.91$setupk4/"tpicd=stop 2006.201.02:43:40.91$setupk4/"rec=synch_on 2006.201.02:43:40.91$setupk4/"rec_mode=128 2006.201.02:43:40.91$setupk4/!* 2006.201.02:43:40.91$setupk4/recpk4 2006.201.02:43:40.91$recpk4/recpatch= 2006.201.02:43:40.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:43:40.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:43:40.91$setupk4/vck44 2006.201.02:43:40.91$vck44/valo=1,524.99 2006.201.02:43:40.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.02:43:40.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.02:43:40.91#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:40.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:40.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:40.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:40.91#ibcon#enter wrdev, iclass 6, count 0 2006.201.02:43:40.91#ibcon#first serial, iclass 6, count 0 2006.201.02:43:40.91#ibcon#enter sib2, iclass 6, count 0 2006.201.02:43:40.91#ibcon#flushed, iclass 6, count 0 2006.201.02:43:40.91#ibcon#about to write, iclass 6, count 0 2006.201.02:43:40.91#ibcon#wrote, iclass 6, count 0 2006.201.02:43:40.91#ibcon#about to read 3, iclass 6, count 0 2006.201.02:43:40.95#ibcon#read 3, iclass 6, count 0 2006.201.02:43:40.95#ibcon#about to read 4, iclass 6, count 0 2006.201.02:43:40.95#ibcon#read 4, iclass 6, count 0 2006.201.02:43:40.95#ibcon#about to read 5, iclass 6, count 0 2006.201.02:43:40.95#ibcon#read 5, iclass 6, count 0 2006.201.02:43:40.95#ibcon#about to read 6, iclass 6, count 0 2006.201.02:43:40.95#ibcon#read 6, iclass 6, count 0 2006.201.02:43:40.95#ibcon#end of sib2, iclass 6, count 0 2006.201.02:43:40.95#ibcon#*mode == 0, iclass 6, count 0 2006.201.02:43:40.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.02:43:40.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:43:40.95#ibcon#*before write, iclass 6, count 0 2006.201.02:43:40.95#ibcon#enter sib2, iclass 6, count 0 2006.201.02:43:40.95#ibcon#flushed, iclass 6, count 0 2006.201.02:43:40.95#ibcon#about to write, iclass 6, count 0 2006.201.02:43:40.95#ibcon#wrote, iclass 6, count 0 2006.201.02:43:40.95#ibcon#about to read 3, iclass 6, count 0 2006.201.02:43:41.00#ibcon#read 3, iclass 6, count 0 2006.201.02:43:41.00#ibcon#about to read 4, iclass 6, count 0 2006.201.02:43:41.00#ibcon#read 4, iclass 6, count 0 2006.201.02:43:41.00#ibcon#about to read 5, iclass 6, count 0 2006.201.02:43:41.00#ibcon#read 5, iclass 6, count 0 2006.201.02:43:41.00#ibcon#about to read 6, iclass 6, count 0 2006.201.02:43:41.00#ibcon#read 6, iclass 6, count 0 2006.201.02:43:41.00#ibcon#end of sib2, iclass 6, count 0 2006.201.02:43:41.00#ibcon#*after write, iclass 6, count 0 2006.201.02:43:41.00#ibcon#*before return 0, iclass 6, count 0 2006.201.02:43:41.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:41.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:41.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.02:43:41.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.02:43:41.00$vck44/va=1,8 2006.201.02:43:41.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.02:43:41.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.02:43:41.00#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:41.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:41.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:41.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:41.00#ibcon#enter wrdev, iclass 10, count 2 2006.201.02:43:41.00#ibcon#first serial, iclass 10, count 2 2006.201.02:43:41.00#ibcon#enter sib2, iclass 10, count 2 2006.201.02:43:41.00#ibcon#flushed, iclass 10, count 2 2006.201.02:43:41.00#ibcon#about to write, iclass 10, count 2 2006.201.02:43:41.00#ibcon#wrote, iclass 10, count 2 2006.201.02:43:41.00#ibcon#about to read 3, iclass 10, count 2 2006.201.02:43:41.02#ibcon#read 3, iclass 10, count 2 2006.201.02:43:41.02#ibcon#about to read 4, iclass 10, count 2 2006.201.02:43:41.02#ibcon#read 4, iclass 10, count 2 2006.201.02:43:41.02#ibcon#about to read 5, iclass 10, count 2 2006.201.02:43:41.02#ibcon#read 5, iclass 10, count 2 2006.201.02:43:41.02#ibcon#about to read 6, iclass 10, count 2 2006.201.02:43:41.02#ibcon#read 6, iclass 10, count 2 2006.201.02:43:41.02#ibcon#end of sib2, iclass 10, count 2 2006.201.02:43:41.02#ibcon#*mode == 0, iclass 10, count 2 2006.201.02:43:41.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.02:43:41.02#ibcon#[25=AT01-08\r\n] 2006.201.02:43:41.02#ibcon#*before write, iclass 10, count 2 2006.201.02:43:41.02#ibcon#enter sib2, iclass 10, count 2 2006.201.02:43:41.02#ibcon#flushed, iclass 10, count 2 2006.201.02:43:41.02#ibcon#about to write, iclass 10, count 2 2006.201.02:43:41.02#ibcon#wrote, iclass 10, count 2 2006.201.02:43:41.02#ibcon#about to read 3, iclass 10, count 2 2006.201.02:43:41.05#ibcon#read 3, iclass 10, count 2 2006.201.02:43:41.05#ibcon#about to read 4, iclass 10, count 2 2006.201.02:43:41.05#ibcon#read 4, iclass 10, count 2 2006.201.02:43:41.05#ibcon#about to read 5, iclass 10, count 2 2006.201.02:43:41.05#ibcon#read 5, iclass 10, count 2 2006.201.02:43:41.05#ibcon#about to read 6, iclass 10, count 2 2006.201.02:43:41.05#ibcon#read 6, iclass 10, count 2 2006.201.02:43:41.05#ibcon#end of sib2, iclass 10, count 2 2006.201.02:43:41.05#ibcon#*after write, iclass 10, count 2 2006.201.02:43:41.05#ibcon#*before return 0, iclass 10, count 2 2006.201.02:43:41.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:41.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:41.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.02:43:41.05#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:41.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:41.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:41.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:41.17#ibcon#enter wrdev, iclass 10, count 0 2006.201.02:43:41.17#ibcon#first serial, iclass 10, count 0 2006.201.02:43:41.17#ibcon#enter sib2, iclass 10, count 0 2006.201.02:43:41.17#ibcon#flushed, iclass 10, count 0 2006.201.02:43:41.17#ibcon#about to write, iclass 10, count 0 2006.201.02:43:41.17#ibcon#wrote, iclass 10, count 0 2006.201.02:43:41.17#ibcon#about to read 3, iclass 10, count 0 2006.201.02:43:41.19#ibcon#read 3, iclass 10, count 0 2006.201.02:43:41.19#ibcon#about to read 4, iclass 10, count 0 2006.201.02:43:41.19#ibcon#read 4, iclass 10, count 0 2006.201.02:43:41.19#ibcon#about to read 5, iclass 10, count 0 2006.201.02:43:41.19#ibcon#read 5, iclass 10, count 0 2006.201.02:43:41.19#ibcon#about to read 6, iclass 10, count 0 2006.201.02:43:41.19#ibcon#read 6, iclass 10, count 0 2006.201.02:43:41.19#ibcon#end of sib2, iclass 10, count 0 2006.201.02:43:41.19#ibcon#*mode == 0, iclass 10, count 0 2006.201.02:43:41.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.02:43:41.19#ibcon#[25=USB\r\n] 2006.201.02:43:41.19#ibcon#*before write, iclass 10, count 0 2006.201.02:43:41.19#ibcon#enter sib2, iclass 10, count 0 2006.201.02:43:41.19#ibcon#flushed, iclass 10, count 0 2006.201.02:43:41.19#ibcon#about to write, iclass 10, count 0 2006.201.02:43:41.19#ibcon#wrote, iclass 10, count 0 2006.201.02:43:41.19#ibcon#about to read 3, iclass 10, count 0 2006.201.02:43:41.22#ibcon#read 3, iclass 10, count 0 2006.201.02:43:41.22#ibcon#about to read 4, iclass 10, count 0 2006.201.02:43:41.22#ibcon#read 4, iclass 10, count 0 2006.201.02:43:41.22#ibcon#about to read 5, iclass 10, count 0 2006.201.02:43:41.22#ibcon#read 5, iclass 10, count 0 2006.201.02:43:41.22#ibcon#about to read 6, iclass 10, count 0 2006.201.02:43:41.22#ibcon#read 6, iclass 10, count 0 2006.201.02:43:41.22#ibcon#end of sib2, iclass 10, count 0 2006.201.02:43:41.22#ibcon#*after write, iclass 10, count 0 2006.201.02:43:41.22#ibcon#*before return 0, iclass 10, count 0 2006.201.02:43:41.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:41.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:41.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.02:43:41.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.02:43:41.22$vck44/valo=2,534.99 2006.201.02:43:41.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.02:43:41.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.02:43:41.22#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:41.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:41.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:41.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:41.22#ibcon#enter wrdev, iclass 12, count 0 2006.201.02:43:41.22#ibcon#first serial, iclass 12, count 0 2006.201.02:43:41.22#ibcon#enter sib2, iclass 12, count 0 2006.201.02:43:41.22#ibcon#flushed, iclass 12, count 0 2006.201.02:43:41.22#ibcon#about to write, iclass 12, count 0 2006.201.02:43:41.22#ibcon#wrote, iclass 12, count 0 2006.201.02:43:41.22#ibcon#about to read 3, iclass 12, count 0 2006.201.02:43:41.24#ibcon#read 3, iclass 12, count 0 2006.201.02:43:41.24#ibcon#about to read 4, iclass 12, count 0 2006.201.02:43:41.24#ibcon#read 4, iclass 12, count 0 2006.201.02:43:41.24#ibcon#about to read 5, iclass 12, count 0 2006.201.02:43:41.24#ibcon#read 5, iclass 12, count 0 2006.201.02:43:41.24#ibcon#about to read 6, iclass 12, count 0 2006.201.02:43:41.24#ibcon#read 6, iclass 12, count 0 2006.201.02:43:41.24#ibcon#end of sib2, iclass 12, count 0 2006.201.02:43:41.24#ibcon#*mode == 0, iclass 12, count 0 2006.201.02:43:41.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.02:43:41.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:43:41.24#ibcon#*before write, iclass 12, count 0 2006.201.02:43:41.24#ibcon#enter sib2, iclass 12, count 0 2006.201.02:43:41.24#ibcon#flushed, iclass 12, count 0 2006.201.02:43:41.24#ibcon#about to write, iclass 12, count 0 2006.201.02:43:41.24#ibcon#wrote, iclass 12, count 0 2006.201.02:43:41.24#ibcon#about to read 3, iclass 12, count 0 2006.201.02:43:41.28#ibcon#read 3, iclass 12, count 0 2006.201.02:43:41.28#ibcon#about to read 4, iclass 12, count 0 2006.201.02:43:41.28#ibcon#read 4, iclass 12, count 0 2006.201.02:43:41.28#ibcon#about to read 5, iclass 12, count 0 2006.201.02:43:41.28#ibcon#read 5, iclass 12, count 0 2006.201.02:43:41.28#ibcon#about to read 6, iclass 12, count 0 2006.201.02:43:41.28#ibcon#read 6, iclass 12, count 0 2006.201.02:43:41.28#ibcon#end of sib2, iclass 12, count 0 2006.201.02:43:41.28#ibcon#*after write, iclass 12, count 0 2006.201.02:43:41.28#ibcon#*before return 0, iclass 12, count 0 2006.201.02:43:41.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:41.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:41.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.02:43:41.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.02:43:41.28$vck44/va=2,7 2006.201.02:43:41.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.02:43:41.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.02:43:41.28#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:41.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:41.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:41.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:41.34#ibcon#enter wrdev, iclass 14, count 2 2006.201.02:43:41.34#ibcon#first serial, iclass 14, count 2 2006.201.02:43:41.34#ibcon#enter sib2, iclass 14, count 2 2006.201.02:43:41.34#ibcon#flushed, iclass 14, count 2 2006.201.02:43:41.34#ibcon#about to write, iclass 14, count 2 2006.201.02:43:41.34#ibcon#wrote, iclass 14, count 2 2006.201.02:43:41.34#ibcon#about to read 3, iclass 14, count 2 2006.201.02:43:41.36#ibcon#read 3, iclass 14, count 2 2006.201.02:43:41.36#ibcon#about to read 4, iclass 14, count 2 2006.201.02:43:41.36#ibcon#read 4, iclass 14, count 2 2006.201.02:43:41.36#ibcon#about to read 5, iclass 14, count 2 2006.201.02:43:41.36#ibcon#read 5, iclass 14, count 2 2006.201.02:43:41.36#ibcon#about to read 6, iclass 14, count 2 2006.201.02:43:41.36#ibcon#read 6, iclass 14, count 2 2006.201.02:43:41.36#ibcon#end of sib2, iclass 14, count 2 2006.201.02:43:41.36#ibcon#*mode == 0, iclass 14, count 2 2006.201.02:43:41.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.02:43:41.36#ibcon#[25=AT02-07\r\n] 2006.201.02:43:41.36#ibcon#*before write, iclass 14, count 2 2006.201.02:43:41.36#ibcon#enter sib2, iclass 14, count 2 2006.201.02:43:41.36#ibcon#flushed, iclass 14, count 2 2006.201.02:43:41.36#ibcon#about to write, iclass 14, count 2 2006.201.02:43:41.36#ibcon#wrote, iclass 14, count 2 2006.201.02:43:41.36#ibcon#about to read 3, iclass 14, count 2 2006.201.02:43:41.39#ibcon#read 3, iclass 14, count 2 2006.201.02:43:41.39#ibcon#about to read 4, iclass 14, count 2 2006.201.02:43:41.39#ibcon#read 4, iclass 14, count 2 2006.201.02:43:41.39#ibcon#about to read 5, iclass 14, count 2 2006.201.02:43:41.39#ibcon#read 5, iclass 14, count 2 2006.201.02:43:41.39#ibcon#about to read 6, iclass 14, count 2 2006.201.02:43:41.39#ibcon#read 6, iclass 14, count 2 2006.201.02:43:41.39#ibcon#end of sib2, iclass 14, count 2 2006.201.02:43:41.39#ibcon#*after write, iclass 14, count 2 2006.201.02:43:41.39#ibcon#*before return 0, iclass 14, count 2 2006.201.02:43:41.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:41.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:41.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.02:43:41.39#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:41.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:41.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:41.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:41.51#ibcon#enter wrdev, iclass 14, count 0 2006.201.02:43:41.51#ibcon#first serial, iclass 14, count 0 2006.201.02:43:41.51#ibcon#enter sib2, iclass 14, count 0 2006.201.02:43:41.51#ibcon#flushed, iclass 14, count 0 2006.201.02:43:41.51#ibcon#about to write, iclass 14, count 0 2006.201.02:43:41.51#ibcon#wrote, iclass 14, count 0 2006.201.02:43:41.51#ibcon#about to read 3, iclass 14, count 0 2006.201.02:43:41.53#ibcon#read 3, iclass 14, count 0 2006.201.02:43:41.53#ibcon#about to read 4, iclass 14, count 0 2006.201.02:43:41.53#ibcon#read 4, iclass 14, count 0 2006.201.02:43:41.53#ibcon#about to read 5, iclass 14, count 0 2006.201.02:43:41.53#ibcon#read 5, iclass 14, count 0 2006.201.02:43:41.53#ibcon#about to read 6, iclass 14, count 0 2006.201.02:43:41.53#ibcon#read 6, iclass 14, count 0 2006.201.02:43:41.53#ibcon#end of sib2, iclass 14, count 0 2006.201.02:43:41.53#ibcon#*mode == 0, iclass 14, count 0 2006.201.02:43:41.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.02:43:41.53#ibcon#[25=USB\r\n] 2006.201.02:43:41.53#ibcon#*before write, iclass 14, count 0 2006.201.02:43:41.53#ibcon#enter sib2, iclass 14, count 0 2006.201.02:43:41.53#ibcon#flushed, iclass 14, count 0 2006.201.02:43:41.53#ibcon#about to write, iclass 14, count 0 2006.201.02:43:41.53#ibcon#wrote, iclass 14, count 0 2006.201.02:43:41.53#ibcon#about to read 3, iclass 14, count 0 2006.201.02:43:41.56#ibcon#read 3, iclass 14, count 0 2006.201.02:43:41.56#ibcon#about to read 4, iclass 14, count 0 2006.201.02:43:41.56#ibcon#read 4, iclass 14, count 0 2006.201.02:43:41.56#ibcon#about to read 5, iclass 14, count 0 2006.201.02:43:41.56#ibcon#read 5, iclass 14, count 0 2006.201.02:43:41.56#ibcon#about to read 6, iclass 14, count 0 2006.201.02:43:41.56#ibcon#read 6, iclass 14, count 0 2006.201.02:43:41.56#ibcon#end of sib2, iclass 14, count 0 2006.201.02:43:41.56#ibcon#*after write, iclass 14, count 0 2006.201.02:43:41.56#ibcon#*before return 0, iclass 14, count 0 2006.201.02:43:41.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:41.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:41.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.02:43:41.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.02:43:41.56$vck44/valo=3,564.99 2006.201.02:43:41.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.02:43:41.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.02:43:41.56#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:41.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:41.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:41.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:41.56#ibcon#enter wrdev, iclass 16, count 0 2006.201.02:43:41.56#ibcon#first serial, iclass 16, count 0 2006.201.02:43:41.56#ibcon#enter sib2, iclass 16, count 0 2006.201.02:43:41.56#ibcon#flushed, iclass 16, count 0 2006.201.02:43:41.56#ibcon#about to write, iclass 16, count 0 2006.201.02:43:41.56#ibcon#wrote, iclass 16, count 0 2006.201.02:43:41.56#ibcon#about to read 3, iclass 16, count 0 2006.201.02:43:41.58#ibcon#read 3, iclass 16, count 0 2006.201.02:43:41.58#ibcon#about to read 4, iclass 16, count 0 2006.201.02:43:41.58#ibcon#read 4, iclass 16, count 0 2006.201.02:43:41.58#ibcon#about to read 5, iclass 16, count 0 2006.201.02:43:41.58#ibcon#read 5, iclass 16, count 0 2006.201.02:43:41.58#ibcon#about to read 6, iclass 16, count 0 2006.201.02:43:41.58#ibcon#read 6, iclass 16, count 0 2006.201.02:43:41.58#ibcon#end of sib2, iclass 16, count 0 2006.201.02:43:41.58#ibcon#*mode == 0, iclass 16, count 0 2006.201.02:43:41.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.02:43:41.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:43:41.58#ibcon#*before write, iclass 16, count 0 2006.201.02:43:41.58#ibcon#enter sib2, iclass 16, count 0 2006.201.02:43:41.58#ibcon#flushed, iclass 16, count 0 2006.201.02:43:41.58#ibcon#about to write, iclass 16, count 0 2006.201.02:43:41.58#ibcon#wrote, iclass 16, count 0 2006.201.02:43:41.58#ibcon#about to read 3, iclass 16, count 0 2006.201.02:43:41.63#ibcon#read 3, iclass 16, count 0 2006.201.02:43:41.63#ibcon#about to read 4, iclass 16, count 0 2006.201.02:43:41.63#ibcon#read 4, iclass 16, count 0 2006.201.02:43:41.63#ibcon#about to read 5, iclass 16, count 0 2006.201.02:43:41.63#ibcon#read 5, iclass 16, count 0 2006.201.02:43:41.63#ibcon#about to read 6, iclass 16, count 0 2006.201.02:43:41.63#ibcon#read 6, iclass 16, count 0 2006.201.02:43:41.63#ibcon#end of sib2, iclass 16, count 0 2006.201.02:43:41.63#ibcon#*after write, iclass 16, count 0 2006.201.02:43:41.63#ibcon#*before return 0, iclass 16, count 0 2006.201.02:43:41.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:41.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:41.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.02:43:41.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.02:43:41.63$vck44/va=3,8 2006.201.02:43:41.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.02:43:41.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.02:43:41.63#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:41.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:41.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:41.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:41.68#ibcon#enter wrdev, iclass 18, count 2 2006.201.02:43:41.68#ibcon#first serial, iclass 18, count 2 2006.201.02:43:41.68#ibcon#enter sib2, iclass 18, count 2 2006.201.02:43:41.68#ibcon#flushed, iclass 18, count 2 2006.201.02:43:41.68#ibcon#about to write, iclass 18, count 2 2006.201.02:43:41.68#ibcon#wrote, iclass 18, count 2 2006.201.02:43:41.68#ibcon#about to read 3, iclass 18, count 2 2006.201.02:43:41.70#ibcon#read 3, iclass 18, count 2 2006.201.02:43:41.70#ibcon#about to read 4, iclass 18, count 2 2006.201.02:43:41.70#ibcon#read 4, iclass 18, count 2 2006.201.02:43:41.70#ibcon#about to read 5, iclass 18, count 2 2006.201.02:43:41.70#ibcon#read 5, iclass 18, count 2 2006.201.02:43:41.70#ibcon#about to read 6, iclass 18, count 2 2006.201.02:43:41.70#ibcon#read 6, iclass 18, count 2 2006.201.02:43:41.70#ibcon#end of sib2, iclass 18, count 2 2006.201.02:43:41.70#ibcon#*mode == 0, iclass 18, count 2 2006.201.02:43:41.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.02:43:41.70#ibcon#[25=AT03-08\r\n] 2006.201.02:43:41.70#ibcon#*before write, iclass 18, count 2 2006.201.02:43:41.70#ibcon#enter sib2, iclass 18, count 2 2006.201.02:43:41.70#ibcon#flushed, iclass 18, count 2 2006.201.02:43:41.70#ibcon#about to write, iclass 18, count 2 2006.201.02:43:41.70#ibcon#wrote, iclass 18, count 2 2006.201.02:43:41.70#ibcon#about to read 3, iclass 18, count 2 2006.201.02:43:41.73#ibcon#read 3, iclass 18, count 2 2006.201.02:43:41.73#ibcon#about to read 4, iclass 18, count 2 2006.201.02:43:41.73#ibcon#read 4, iclass 18, count 2 2006.201.02:43:41.73#ibcon#about to read 5, iclass 18, count 2 2006.201.02:43:41.73#ibcon#read 5, iclass 18, count 2 2006.201.02:43:41.73#ibcon#about to read 6, iclass 18, count 2 2006.201.02:43:41.73#ibcon#read 6, iclass 18, count 2 2006.201.02:43:41.73#ibcon#end of sib2, iclass 18, count 2 2006.201.02:43:41.73#ibcon#*after write, iclass 18, count 2 2006.201.02:43:41.73#ibcon#*before return 0, iclass 18, count 2 2006.201.02:43:41.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:41.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:41.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.02:43:41.73#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:41.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:41.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:41.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:41.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.02:43:41.85#ibcon#first serial, iclass 18, count 0 2006.201.02:43:41.85#ibcon#enter sib2, iclass 18, count 0 2006.201.02:43:41.85#ibcon#flushed, iclass 18, count 0 2006.201.02:43:41.85#ibcon#about to write, iclass 18, count 0 2006.201.02:43:41.85#ibcon#wrote, iclass 18, count 0 2006.201.02:43:41.85#ibcon#about to read 3, iclass 18, count 0 2006.201.02:43:41.87#ibcon#read 3, iclass 18, count 0 2006.201.02:43:41.87#ibcon#about to read 4, iclass 18, count 0 2006.201.02:43:41.87#ibcon#read 4, iclass 18, count 0 2006.201.02:43:41.87#ibcon#about to read 5, iclass 18, count 0 2006.201.02:43:41.87#ibcon#read 5, iclass 18, count 0 2006.201.02:43:41.87#ibcon#about to read 6, iclass 18, count 0 2006.201.02:43:41.87#ibcon#read 6, iclass 18, count 0 2006.201.02:43:41.87#ibcon#end of sib2, iclass 18, count 0 2006.201.02:43:41.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.02:43:41.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.02:43:41.87#ibcon#[25=USB\r\n] 2006.201.02:43:41.87#ibcon#*before write, iclass 18, count 0 2006.201.02:43:41.87#ibcon#enter sib2, iclass 18, count 0 2006.201.02:43:41.87#ibcon#flushed, iclass 18, count 0 2006.201.02:43:41.87#ibcon#about to write, iclass 18, count 0 2006.201.02:43:41.87#ibcon#wrote, iclass 18, count 0 2006.201.02:43:41.87#ibcon#about to read 3, iclass 18, count 0 2006.201.02:43:41.90#ibcon#read 3, iclass 18, count 0 2006.201.02:43:41.90#ibcon#about to read 4, iclass 18, count 0 2006.201.02:43:41.90#ibcon#read 4, iclass 18, count 0 2006.201.02:43:41.90#ibcon#about to read 5, iclass 18, count 0 2006.201.02:43:41.90#ibcon#read 5, iclass 18, count 0 2006.201.02:43:41.90#ibcon#about to read 6, iclass 18, count 0 2006.201.02:43:41.90#ibcon#read 6, iclass 18, count 0 2006.201.02:43:41.90#ibcon#end of sib2, iclass 18, count 0 2006.201.02:43:41.90#ibcon#*after write, iclass 18, count 0 2006.201.02:43:41.90#ibcon#*before return 0, iclass 18, count 0 2006.201.02:43:41.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:41.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:41.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.02:43:41.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.02:43:41.90$vck44/valo=4,624.99 2006.201.02:43:41.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.02:43:41.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.02:43:41.90#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:41.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:41.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:41.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:41.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.02:43:41.90#ibcon#first serial, iclass 20, count 0 2006.201.02:43:41.90#ibcon#enter sib2, iclass 20, count 0 2006.201.02:43:41.90#ibcon#flushed, iclass 20, count 0 2006.201.02:43:41.90#ibcon#about to write, iclass 20, count 0 2006.201.02:43:41.90#ibcon#wrote, iclass 20, count 0 2006.201.02:43:41.90#ibcon#about to read 3, iclass 20, count 0 2006.201.02:43:41.92#ibcon#read 3, iclass 20, count 0 2006.201.02:43:41.92#ibcon#about to read 4, iclass 20, count 0 2006.201.02:43:41.92#ibcon#read 4, iclass 20, count 0 2006.201.02:43:41.92#ibcon#about to read 5, iclass 20, count 0 2006.201.02:43:41.92#ibcon#read 5, iclass 20, count 0 2006.201.02:43:41.92#ibcon#about to read 6, iclass 20, count 0 2006.201.02:43:41.92#ibcon#read 6, iclass 20, count 0 2006.201.02:43:41.92#ibcon#end of sib2, iclass 20, count 0 2006.201.02:43:41.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.02:43:41.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.02:43:41.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:43:41.92#ibcon#*before write, iclass 20, count 0 2006.201.02:43:41.92#ibcon#enter sib2, iclass 20, count 0 2006.201.02:43:41.92#ibcon#flushed, iclass 20, count 0 2006.201.02:43:41.92#ibcon#about to write, iclass 20, count 0 2006.201.02:43:41.92#ibcon#wrote, iclass 20, count 0 2006.201.02:43:41.92#ibcon#about to read 3, iclass 20, count 0 2006.201.02:43:41.97#ibcon#read 3, iclass 20, count 0 2006.201.02:43:41.97#ibcon#about to read 4, iclass 20, count 0 2006.201.02:43:41.97#ibcon#read 4, iclass 20, count 0 2006.201.02:43:41.97#ibcon#about to read 5, iclass 20, count 0 2006.201.02:43:41.97#ibcon#read 5, iclass 20, count 0 2006.201.02:43:41.97#ibcon#about to read 6, iclass 20, count 0 2006.201.02:43:41.97#ibcon#read 6, iclass 20, count 0 2006.201.02:43:41.97#ibcon#end of sib2, iclass 20, count 0 2006.201.02:43:41.97#ibcon#*after write, iclass 20, count 0 2006.201.02:43:41.97#ibcon#*before return 0, iclass 20, count 0 2006.201.02:43:41.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:41.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:41.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.02:43:41.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.02:43:41.97$vck44/va=4,7 2006.201.02:43:41.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.02:43:41.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.02:43:41.97#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:41.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:42.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:42.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:42.02#ibcon#enter wrdev, iclass 22, count 2 2006.201.02:43:42.02#ibcon#first serial, iclass 22, count 2 2006.201.02:43:42.02#ibcon#enter sib2, iclass 22, count 2 2006.201.02:43:42.02#ibcon#flushed, iclass 22, count 2 2006.201.02:43:42.02#ibcon#about to write, iclass 22, count 2 2006.201.02:43:42.02#ibcon#wrote, iclass 22, count 2 2006.201.02:43:42.02#ibcon#about to read 3, iclass 22, count 2 2006.201.02:43:42.04#ibcon#read 3, iclass 22, count 2 2006.201.02:43:42.04#ibcon#about to read 4, iclass 22, count 2 2006.201.02:43:42.04#ibcon#read 4, iclass 22, count 2 2006.201.02:43:42.04#ibcon#about to read 5, iclass 22, count 2 2006.201.02:43:42.04#ibcon#read 5, iclass 22, count 2 2006.201.02:43:42.04#ibcon#about to read 6, iclass 22, count 2 2006.201.02:43:42.04#ibcon#read 6, iclass 22, count 2 2006.201.02:43:42.04#ibcon#end of sib2, iclass 22, count 2 2006.201.02:43:42.04#ibcon#*mode == 0, iclass 22, count 2 2006.201.02:43:42.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.02:43:42.04#ibcon#[25=AT04-07\r\n] 2006.201.02:43:42.04#ibcon#*before write, iclass 22, count 2 2006.201.02:43:42.04#ibcon#enter sib2, iclass 22, count 2 2006.201.02:43:42.04#ibcon#flushed, iclass 22, count 2 2006.201.02:43:42.04#ibcon#about to write, iclass 22, count 2 2006.201.02:43:42.04#ibcon#wrote, iclass 22, count 2 2006.201.02:43:42.04#ibcon#about to read 3, iclass 22, count 2 2006.201.02:43:42.07#ibcon#read 3, iclass 22, count 2 2006.201.02:43:42.07#ibcon#about to read 4, iclass 22, count 2 2006.201.02:43:42.07#ibcon#read 4, iclass 22, count 2 2006.201.02:43:42.07#ibcon#about to read 5, iclass 22, count 2 2006.201.02:43:42.07#ibcon#read 5, iclass 22, count 2 2006.201.02:43:42.07#ibcon#about to read 6, iclass 22, count 2 2006.201.02:43:42.07#ibcon#read 6, iclass 22, count 2 2006.201.02:43:42.07#ibcon#end of sib2, iclass 22, count 2 2006.201.02:43:42.07#ibcon#*after write, iclass 22, count 2 2006.201.02:43:42.07#ibcon#*before return 0, iclass 22, count 2 2006.201.02:43:42.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:42.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:42.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.02:43:42.07#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:42.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:42.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:42.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:42.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.02:43:42.19#ibcon#first serial, iclass 22, count 0 2006.201.02:43:42.19#ibcon#enter sib2, iclass 22, count 0 2006.201.02:43:42.19#ibcon#flushed, iclass 22, count 0 2006.201.02:43:42.19#ibcon#about to write, iclass 22, count 0 2006.201.02:43:42.19#ibcon#wrote, iclass 22, count 0 2006.201.02:43:42.19#ibcon#about to read 3, iclass 22, count 0 2006.201.02:43:42.21#ibcon#read 3, iclass 22, count 0 2006.201.02:43:42.21#ibcon#about to read 4, iclass 22, count 0 2006.201.02:43:42.21#ibcon#read 4, iclass 22, count 0 2006.201.02:43:42.21#ibcon#about to read 5, iclass 22, count 0 2006.201.02:43:42.21#ibcon#read 5, iclass 22, count 0 2006.201.02:43:42.21#ibcon#about to read 6, iclass 22, count 0 2006.201.02:43:42.21#ibcon#read 6, iclass 22, count 0 2006.201.02:43:42.21#ibcon#end of sib2, iclass 22, count 0 2006.201.02:43:42.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.02:43:42.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.02:43:42.21#ibcon#[25=USB\r\n] 2006.201.02:43:42.21#ibcon#*before write, iclass 22, count 0 2006.201.02:43:42.21#ibcon#enter sib2, iclass 22, count 0 2006.201.02:43:42.21#ibcon#flushed, iclass 22, count 0 2006.201.02:43:42.21#ibcon#about to write, iclass 22, count 0 2006.201.02:43:42.21#ibcon#wrote, iclass 22, count 0 2006.201.02:43:42.21#ibcon#about to read 3, iclass 22, count 0 2006.201.02:43:42.24#ibcon#read 3, iclass 22, count 0 2006.201.02:43:42.24#ibcon#about to read 4, iclass 22, count 0 2006.201.02:43:42.24#ibcon#read 4, iclass 22, count 0 2006.201.02:43:42.24#ibcon#about to read 5, iclass 22, count 0 2006.201.02:43:42.24#ibcon#read 5, iclass 22, count 0 2006.201.02:43:42.24#ibcon#about to read 6, iclass 22, count 0 2006.201.02:43:42.24#ibcon#read 6, iclass 22, count 0 2006.201.02:43:42.24#ibcon#end of sib2, iclass 22, count 0 2006.201.02:43:42.24#ibcon#*after write, iclass 22, count 0 2006.201.02:43:42.24#ibcon#*before return 0, iclass 22, count 0 2006.201.02:43:42.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:42.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:42.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.02:43:42.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.02:43:42.24$vck44/valo=5,734.99 2006.201.02:43:42.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.02:43:42.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.02:43:42.24#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:42.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:42.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:42.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:42.24#ibcon#enter wrdev, iclass 24, count 0 2006.201.02:43:42.24#ibcon#first serial, iclass 24, count 0 2006.201.02:43:42.24#ibcon#enter sib2, iclass 24, count 0 2006.201.02:43:42.24#ibcon#flushed, iclass 24, count 0 2006.201.02:43:42.24#ibcon#about to write, iclass 24, count 0 2006.201.02:43:42.24#ibcon#wrote, iclass 24, count 0 2006.201.02:43:42.24#ibcon#about to read 3, iclass 24, count 0 2006.201.02:43:42.26#ibcon#read 3, iclass 24, count 0 2006.201.02:43:42.26#ibcon#about to read 4, iclass 24, count 0 2006.201.02:43:42.26#ibcon#read 4, iclass 24, count 0 2006.201.02:43:42.26#ibcon#about to read 5, iclass 24, count 0 2006.201.02:43:42.26#ibcon#read 5, iclass 24, count 0 2006.201.02:43:42.26#ibcon#about to read 6, iclass 24, count 0 2006.201.02:43:42.26#ibcon#read 6, iclass 24, count 0 2006.201.02:43:42.26#ibcon#end of sib2, iclass 24, count 0 2006.201.02:43:42.26#ibcon#*mode == 0, iclass 24, count 0 2006.201.02:43:42.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.02:43:42.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:43:42.26#ibcon#*before write, iclass 24, count 0 2006.201.02:43:42.26#ibcon#enter sib2, iclass 24, count 0 2006.201.02:43:42.26#ibcon#flushed, iclass 24, count 0 2006.201.02:43:42.26#ibcon#about to write, iclass 24, count 0 2006.201.02:43:42.26#ibcon#wrote, iclass 24, count 0 2006.201.02:43:42.26#ibcon#about to read 3, iclass 24, count 0 2006.201.02:43:42.30#ibcon#read 3, iclass 24, count 0 2006.201.02:43:42.30#ibcon#about to read 4, iclass 24, count 0 2006.201.02:43:42.30#ibcon#read 4, iclass 24, count 0 2006.201.02:43:42.30#ibcon#about to read 5, iclass 24, count 0 2006.201.02:43:42.30#ibcon#read 5, iclass 24, count 0 2006.201.02:43:42.30#ibcon#about to read 6, iclass 24, count 0 2006.201.02:43:42.30#ibcon#read 6, iclass 24, count 0 2006.201.02:43:42.30#ibcon#end of sib2, iclass 24, count 0 2006.201.02:43:42.30#ibcon#*after write, iclass 24, count 0 2006.201.02:43:42.30#ibcon#*before return 0, iclass 24, count 0 2006.201.02:43:42.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:42.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:42.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.02:43:42.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.02:43:42.30$vck44/va=5,4 2006.201.02:43:42.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.02:43:42.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.02:43:42.30#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:42.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:42.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:42.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:42.36#ibcon#enter wrdev, iclass 26, count 2 2006.201.02:43:42.36#ibcon#first serial, iclass 26, count 2 2006.201.02:43:42.36#ibcon#enter sib2, iclass 26, count 2 2006.201.02:43:42.36#ibcon#flushed, iclass 26, count 2 2006.201.02:43:42.36#ibcon#about to write, iclass 26, count 2 2006.201.02:43:42.36#ibcon#wrote, iclass 26, count 2 2006.201.02:43:42.36#ibcon#about to read 3, iclass 26, count 2 2006.201.02:43:42.38#ibcon#read 3, iclass 26, count 2 2006.201.02:43:42.38#ibcon#about to read 4, iclass 26, count 2 2006.201.02:43:42.38#ibcon#read 4, iclass 26, count 2 2006.201.02:43:42.38#ibcon#about to read 5, iclass 26, count 2 2006.201.02:43:42.38#ibcon#read 5, iclass 26, count 2 2006.201.02:43:42.38#ibcon#about to read 6, iclass 26, count 2 2006.201.02:43:42.38#ibcon#read 6, iclass 26, count 2 2006.201.02:43:42.38#ibcon#end of sib2, iclass 26, count 2 2006.201.02:43:42.38#ibcon#*mode == 0, iclass 26, count 2 2006.201.02:43:42.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.02:43:42.38#ibcon#[25=AT05-04\r\n] 2006.201.02:43:42.38#ibcon#*before write, iclass 26, count 2 2006.201.02:43:42.38#ibcon#enter sib2, iclass 26, count 2 2006.201.02:43:42.38#ibcon#flushed, iclass 26, count 2 2006.201.02:43:42.38#ibcon#about to write, iclass 26, count 2 2006.201.02:43:42.38#ibcon#wrote, iclass 26, count 2 2006.201.02:43:42.38#ibcon#about to read 3, iclass 26, count 2 2006.201.02:43:42.41#ibcon#read 3, iclass 26, count 2 2006.201.02:43:42.41#ibcon#about to read 4, iclass 26, count 2 2006.201.02:43:42.41#ibcon#read 4, iclass 26, count 2 2006.201.02:43:42.41#ibcon#about to read 5, iclass 26, count 2 2006.201.02:43:42.41#ibcon#read 5, iclass 26, count 2 2006.201.02:43:42.41#ibcon#about to read 6, iclass 26, count 2 2006.201.02:43:42.41#ibcon#read 6, iclass 26, count 2 2006.201.02:43:42.41#ibcon#end of sib2, iclass 26, count 2 2006.201.02:43:42.41#ibcon#*after write, iclass 26, count 2 2006.201.02:43:42.41#ibcon#*before return 0, iclass 26, count 2 2006.201.02:43:42.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:42.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:42.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.02:43:42.41#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:42.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:42.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:42.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:42.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.02:43:42.53#ibcon#first serial, iclass 26, count 0 2006.201.02:43:42.53#ibcon#enter sib2, iclass 26, count 0 2006.201.02:43:42.53#ibcon#flushed, iclass 26, count 0 2006.201.02:43:42.53#ibcon#about to write, iclass 26, count 0 2006.201.02:43:42.53#ibcon#wrote, iclass 26, count 0 2006.201.02:43:42.53#ibcon#about to read 3, iclass 26, count 0 2006.201.02:43:42.55#ibcon#read 3, iclass 26, count 0 2006.201.02:43:42.55#ibcon#about to read 4, iclass 26, count 0 2006.201.02:43:42.55#ibcon#read 4, iclass 26, count 0 2006.201.02:43:42.55#ibcon#about to read 5, iclass 26, count 0 2006.201.02:43:42.55#ibcon#read 5, iclass 26, count 0 2006.201.02:43:42.55#ibcon#about to read 6, iclass 26, count 0 2006.201.02:43:42.55#ibcon#read 6, iclass 26, count 0 2006.201.02:43:42.55#ibcon#end of sib2, iclass 26, count 0 2006.201.02:43:42.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.02:43:42.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.02:43:42.55#ibcon#[25=USB\r\n] 2006.201.02:43:42.55#ibcon#*before write, iclass 26, count 0 2006.201.02:43:42.55#ibcon#enter sib2, iclass 26, count 0 2006.201.02:43:42.55#ibcon#flushed, iclass 26, count 0 2006.201.02:43:42.55#ibcon#about to write, iclass 26, count 0 2006.201.02:43:42.55#ibcon#wrote, iclass 26, count 0 2006.201.02:43:42.55#ibcon#about to read 3, iclass 26, count 0 2006.201.02:43:42.58#ibcon#read 3, iclass 26, count 0 2006.201.02:43:42.58#ibcon#about to read 4, iclass 26, count 0 2006.201.02:43:42.58#ibcon#read 4, iclass 26, count 0 2006.201.02:43:42.58#ibcon#about to read 5, iclass 26, count 0 2006.201.02:43:42.58#ibcon#read 5, iclass 26, count 0 2006.201.02:43:42.58#ibcon#about to read 6, iclass 26, count 0 2006.201.02:43:42.58#ibcon#read 6, iclass 26, count 0 2006.201.02:43:42.58#ibcon#end of sib2, iclass 26, count 0 2006.201.02:43:42.58#ibcon#*after write, iclass 26, count 0 2006.201.02:43:42.58#ibcon#*before return 0, iclass 26, count 0 2006.201.02:43:42.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:42.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:42.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.02:43:42.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.02:43:42.58$vck44/valo=6,814.99 2006.201.02:43:42.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.02:43:42.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.02:43:42.58#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:42.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:42.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:42.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:42.58#ibcon#enter wrdev, iclass 28, count 0 2006.201.02:43:42.58#ibcon#first serial, iclass 28, count 0 2006.201.02:43:42.58#ibcon#enter sib2, iclass 28, count 0 2006.201.02:43:42.58#ibcon#flushed, iclass 28, count 0 2006.201.02:43:42.58#ibcon#about to write, iclass 28, count 0 2006.201.02:43:42.58#ibcon#wrote, iclass 28, count 0 2006.201.02:43:42.58#ibcon#about to read 3, iclass 28, count 0 2006.201.02:43:42.60#ibcon#read 3, iclass 28, count 0 2006.201.02:43:42.60#ibcon#about to read 4, iclass 28, count 0 2006.201.02:43:42.60#ibcon#read 4, iclass 28, count 0 2006.201.02:43:42.60#ibcon#about to read 5, iclass 28, count 0 2006.201.02:43:42.60#ibcon#read 5, iclass 28, count 0 2006.201.02:43:42.60#ibcon#about to read 6, iclass 28, count 0 2006.201.02:43:42.60#ibcon#read 6, iclass 28, count 0 2006.201.02:43:42.60#ibcon#end of sib2, iclass 28, count 0 2006.201.02:43:42.60#ibcon#*mode == 0, iclass 28, count 0 2006.201.02:43:42.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.02:43:42.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:43:42.60#ibcon#*before write, iclass 28, count 0 2006.201.02:43:42.60#ibcon#enter sib2, iclass 28, count 0 2006.201.02:43:42.60#ibcon#flushed, iclass 28, count 0 2006.201.02:43:42.60#ibcon#about to write, iclass 28, count 0 2006.201.02:43:42.60#ibcon#wrote, iclass 28, count 0 2006.201.02:43:42.60#ibcon#about to read 3, iclass 28, count 0 2006.201.02:43:42.64#ibcon#read 3, iclass 28, count 0 2006.201.02:43:42.64#ibcon#about to read 4, iclass 28, count 0 2006.201.02:43:42.64#ibcon#read 4, iclass 28, count 0 2006.201.02:43:42.64#ibcon#about to read 5, iclass 28, count 0 2006.201.02:43:42.64#ibcon#read 5, iclass 28, count 0 2006.201.02:43:42.64#ibcon#about to read 6, iclass 28, count 0 2006.201.02:43:42.64#ibcon#read 6, iclass 28, count 0 2006.201.02:43:42.64#ibcon#end of sib2, iclass 28, count 0 2006.201.02:43:42.64#ibcon#*after write, iclass 28, count 0 2006.201.02:43:42.64#ibcon#*before return 0, iclass 28, count 0 2006.201.02:43:42.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:42.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:42.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.02:43:42.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.02:43:42.64$vck44/va=6,5 2006.201.02:43:42.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.02:43:42.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.02:43:42.64#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:42.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:42.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:42.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:42.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.02:43:42.70#ibcon#first serial, iclass 30, count 2 2006.201.02:43:42.70#ibcon#enter sib2, iclass 30, count 2 2006.201.02:43:42.70#ibcon#flushed, iclass 30, count 2 2006.201.02:43:42.70#ibcon#about to write, iclass 30, count 2 2006.201.02:43:42.70#ibcon#wrote, iclass 30, count 2 2006.201.02:43:42.70#ibcon#about to read 3, iclass 30, count 2 2006.201.02:43:42.72#ibcon#read 3, iclass 30, count 2 2006.201.02:43:42.72#ibcon#about to read 4, iclass 30, count 2 2006.201.02:43:42.72#ibcon#read 4, iclass 30, count 2 2006.201.02:43:42.72#ibcon#about to read 5, iclass 30, count 2 2006.201.02:43:42.72#ibcon#read 5, iclass 30, count 2 2006.201.02:43:42.72#ibcon#about to read 6, iclass 30, count 2 2006.201.02:43:42.72#ibcon#read 6, iclass 30, count 2 2006.201.02:43:42.72#ibcon#end of sib2, iclass 30, count 2 2006.201.02:43:42.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.02:43:42.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.02:43:42.72#ibcon#[25=AT06-05\r\n] 2006.201.02:43:42.72#ibcon#*before write, iclass 30, count 2 2006.201.02:43:42.72#ibcon#enter sib2, iclass 30, count 2 2006.201.02:43:42.72#ibcon#flushed, iclass 30, count 2 2006.201.02:43:42.72#ibcon#about to write, iclass 30, count 2 2006.201.02:43:42.72#ibcon#wrote, iclass 30, count 2 2006.201.02:43:42.72#ibcon#about to read 3, iclass 30, count 2 2006.201.02:43:42.75#ibcon#read 3, iclass 30, count 2 2006.201.02:43:42.75#ibcon#about to read 4, iclass 30, count 2 2006.201.02:43:42.75#ibcon#read 4, iclass 30, count 2 2006.201.02:43:42.75#ibcon#about to read 5, iclass 30, count 2 2006.201.02:43:42.75#ibcon#read 5, iclass 30, count 2 2006.201.02:43:42.75#ibcon#about to read 6, iclass 30, count 2 2006.201.02:43:42.75#ibcon#read 6, iclass 30, count 2 2006.201.02:43:42.75#ibcon#end of sib2, iclass 30, count 2 2006.201.02:43:42.75#ibcon#*after write, iclass 30, count 2 2006.201.02:43:42.75#ibcon#*before return 0, iclass 30, count 2 2006.201.02:43:42.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:42.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:42.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.02:43:42.75#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:42.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:42.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:42.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:42.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.02:43:42.87#ibcon#first serial, iclass 30, count 0 2006.201.02:43:42.87#ibcon#enter sib2, iclass 30, count 0 2006.201.02:43:42.87#ibcon#flushed, iclass 30, count 0 2006.201.02:43:42.87#ibcon#about to write, iclass 30, count 0 2006.201.02:43:42.87#ibcon#wrote, iclass 30, count 0 2006.201.02:43:42.87#ibcon#about to read 3, iclass 30, count 0 2006.201.02:43:42.89#ibcon#read 3, iclass 30, count 0 2006.201.02:43:42.89#ibcon#about to read 4, iclass 30, count 0 2006.201.02:43:42.89#ibcon#read 4, iclass 30, count 0 2006.201.02:43:42.89#ibcon#about to read 5, iclass 30, count 0 2006.201.02:43:42.89#ibcon#read 5, iclass 30, count 0 2006.201.02:43:42.89#ibcon#about to read 6, iclass 30, count 0 2006.201.02:43:42.89#ibcon#read 6, iclass 30, count 0 2006.201.02:43:42.89#ibcon#end of sib2, iclass 30, count 0 2006.201.02:43:42.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.02:43:42.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.02:43:42.89#ibcon#[25=USB\r\n] 2006.201.02:43:42.89#ibcon#*before write, iclass 30, count 0 2006.201.02:43:42.89#ibcon#enter sib2, iclass 30, count 0 2006.201.02:43:42.89#ibcon#flushed, iclass 30, count 0 2006.201.02:43:42.89#ibcon#about to write, iclass 30, count 0 2006.201.02:43:42.89#ibcon#wrote, iclass 30, count 0 2006.201.02:43:42.89#ibcon#about to read 3, iclass 30, count 0 2006.201.02:43:42.92#ibcon#read 3, iclass 30, count 0 2006.201.02:43:42.92#ibcon#about to read 4, iclass 30, count 0 2006.201.02:43:42.92#ibcon#read 4, iclass 30, count 0 2006.201.02:43:42.92#ibcon#about to read 5, iclass 30, count 0 2006.201.02:43:42.92#ibcon#read 5, iclass 30, count 0 2006.201.02:43:42.92#ibcon#about to read 6, iclass 30, count 0 2006.201.02:43:42.92#ibcon#read 6, iclass 30, count 0 2006.201.02:43:42.92#ibcon#end of sib2, iclass 30, count 0 2006.201.02:43:42.92#ibcon#*after write, iclass 30, count 0 2006.201.02:43:42.92#ibcon#*before return 0, iclass 30, count 0 2006.201.02:43:42.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:42.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:42.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.02:43:42.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.02:43:42.92$vck44/valo=7,864.99 2006.201.02:43:42.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.02:43:42.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.02:43:42.92#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:42.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:42.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:42.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:42.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.02:43:42.92#ibcon#first serial, iclass 32, count 0 2006.201.02:43:42.92#ibcon#enter sib2, iclass 32, count 0 2006.201.02:43:42.92#ibcon#flushed, iclass 32, count 0 2006.201.02:43:42.92#ibcon#about to write, iclass 32, count 0 2006.201.02:43:42.92#ibcon#wrote, iclass 32, count 0 2006.201.02:43:42.92#ibcon#about to read 3, iclass 32, count 0 2006.201.02:43:42.94#ibcon#read 3, iclass 32, count 0 2006.201.02:43:42.94#ibcon#about to read 4, iclass 32, count 0 2006.201.02:43:42.94#ibcon#read 4, iclass 32, count 0 2006.201.02:43:42.94#ibcon#about to read 5, iclass 32, count 0 2006.201.02:43:42.94#ibcon#read 5, iclass 32, count 0 2006.201.02:43:42.94#ibcon#about to read 6, iclass 32, count 0 2006.201.02:43:42.94#ibcon#read 6, iclass 32, count 0 2006.201.02:43:42.94#ibcon#end of sib2, iclass 32, count 0 2006.201.02:43:42.94#ibcon#*mode == 0, iclass 32, count 0 2006.201.02:43:42.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.02:43:42.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:43:42.94#ibcon#*before write, iclass 32, count 0 2006.201.02:43:42.94#ibcon#enter sib2, iclass 32, count 0 2006.201.02:43:42.94#ibcon#flushed, iclass 32, count 0 2006.201.02:43:42.94#ibcon#about to write, iclass 32, count 0 2006.201.02:43:42.94#ibcon#wrote, iclass 32, count 0 2006.201.02:43:42.94#ibcon#about to read 3, iclass 32, count 0 2006.201.02:43:42.98#ibcon#read 3, iclass 32, count 0 2006.201.02:43:42.98#ibcon#about to read 4, iclass 32, count 0 2006.201.02:43:42.98#ibcon#read 4, iclass 32, count 0 2006.201.02:43:42.98#ibcon#about to read 5, iclass 32, count 0 2006.201.02:43:42.98#ibcon#read 5, iclass 32, count 0 2006.201.02:43:42.98#ibcon#about to read 6, iclass 32, count 0 2006.201.02:43:42.98#ibcon#read 6, iclass 32, count 0 2006.201.02:43:42.98#ibcon#end of sib2, iclass 32, count 0 2006.201.02:43:42.98#ibcon#*after write, iclass 32, count 0 2006.201.02:43:42.98#ibcon#*before return 0, iclass 32, count 0 2006.201.02:43:42.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:42.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:42.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.02:43:42.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.02:43:42.98$vck44/va=7,5 2006.201.02:43:42.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.02:43:42.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.02:43:42.98#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:42.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:43.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:43.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:43.04#ibcon#enter wrdev, iclass 34, count 2 2006.201.02:43:43.04#ibcon#first serial, iclass 34, count 2 2006.201.02:43:43.04#ibcon#enter sib2, iclass 34, count 2 2006.201.02:43:43.04#ibcon#flushed, iclass 34, count 2 2006.201.02:43:43.04#ibcon#about to write, iclass 34, count 2 2006.201.02:43:43.04#ibcon#wrote, iclass 34, count 2 2006.201.02:43:43.04#ibcon#about to read 3, iclass 34, count 2 2006.201.02:43:43.06#ibcon#read 3, iclass 34, count 2 2006.201.02:43:43.06#ibcon#about to read 4, iclass 34, count 2 2006.201.02:43:43.06#ibcon#read 4, iclass 34, count 2 2006.201.02:43:43.06#ibcon#about to read 5, iclass 34, count 2 2006.201.02:43:43.06#ibcon#read 5, iclass 34, count 2 2006.201.02:43:43.06#ibcon#about to read 6, iclass 34, count 2 2006.201.02:43:43.06#ibcon#read 6, iclass 34, count 2 2006.201.02:43:43.06#ibcon#end of sib2, iclass 34, count 2 2006.201.02:43:43.06#ibcon#*mode == 0, iclass 34, count 2 2006.201.02:43:43.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.02:43:43.06#ibcon#[25=AT07-05\r\n] 2006.201.02:43:43.06#ibcon#*before write, iclass 34, count 2 2006.201.02:43:43.06#ibcon#enter sib2, iclass 34, count 2 2006.201.02:43:43.06#ibcon#flushed, iclass 34, count 2 2006.201.02:43:43.06#ibcon#about to write, iclass 34, count 2 2006.201.02:43:43.06#ibcon#wrote, iclass 34, count 2 2006.201.02:43:43.06#ibcon#about to read 3, iclass 34, count 2 2006.201.02:43:43.09#ibcon#read 3, iclass 34, count 2 2006.201.02:43:43.09#ibcon#about to read 4, iclass 34, count 2 2006.201.02:43:43.09#ibcon#read 4, iclass 34, count 2 2006.201.02:43:43.09#ibcon#about to read 5, iclass 34, count 2 2006.201.02:43:43.09#ibcon#read 5, iclass 34, count 2 2006.201.02:43:43.09#ibcon#about to read 6, iclass 34, count 2 2006.201.02:43:43.09#ibcon#read 6, iclass 34, count 2 2006.201.02:43:43.09#ibcon#end of sib2, iclass 34, count 2 2006.201.02:43:43.09#ibcon#*after write, iclass 34, count 2 2006.201.02:43:43.09#ibcon#*before return 0, iclass 34, count 2 2006.201.02:43:43.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:43.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:43.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.02:43:43.09#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:43.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:43.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:43.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:43.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.02:43:43.21#ibcon#first serial, iclass 34, count 0 2006.201.02:43:43.21#ibcon#enter sib2, iclass 34, count 0 2006.201.02:43:43.21#ibcon#flushed, iclass 34, count 0 2006.201.02:43:43.21#ibcon#about to write, iclass 34, count 0 2006.201.02:43:43.21#ibcon#wrote, iclass 34, count 0 2006.201.02:43:43.21#ibcon#about to read 3, iclass 34, count 0 2006.201.02:43:43.23#ibcon#read 3, iclass 34, count 0 2006.201.02:43:43.23#ibcon#about to read 4, iclass 34, count 0 2006.201.02:43:43.23#ibcon#read 4, iclass 34, count 0 2006.201.02:43:43.23#ibcon#about to read 5, iclass 34, count 0 2006.201.02:43:43.23#ibcon#read 5, iclass 34, count 0 2006.201.02:43:43.23#ibcon#about to read 6, iclass 34, count 0 2006.201.02:43:43.23#ibcon#read 6, iclass 34, count 0 2006.201.02:43:43.23#ibcon#end of sib2, iclass 34, count 0 2006.201.02:43:43.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.02:43:43.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.02:43:43.23#ibcon#[25=USB\r\n] 2006.201.02:43:43.23#ibcon#*before write, iclass 34, count 0 2006.201.02:43:43.23#ibcon#enter sib2, iclass 34, count 0 2006.201.02:43:43.23#ibcon#flushed, iclass 34, count 0 2006.201.02:43:43.23#ibcon#about to write, iclass 34, count 0 2006.201.02:43:43.23#ibcon#wrote, iclass 34, count 0 2006.201.02:43:43.23#ibcon#about to read 3, iclass 34, count 0 2006.201.02:43:43.26#ibcon#read 3, iclass 34, count 0 2006.201.02:43:43.26#ibcon#about to read 4, iclass 34, count 0 2006.201.02:43:43.26#ibcon#read 4, iclass 34, count 0 2006.201.02:43:43.26#ibcon#about to read 5, iclass 34, count 0 2006.201.02:43:43.26#ibcon#read 5, iclass 34, count 0 2006.201.02:43:43.26#ibcon#about to read 6, iclass 34, count 0 2006.201.02:43:43.26#ibcon#read 6, iclass 34, count 0 2006.201.02:43:43.26#ibcon#end of sib2, iclass 34, count 0 2006.201.02:43:43.26#ibcon#*after write, iclass 34, count 0 2006.201.02:43:43.26#ibcon#*before return 0, iclass 34, count 0 2006.201.02:43:43.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:43.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:43.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.02:43:43.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.02:43:43.26$vck44/valo=8,884.99 2006.201.02:43:43.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.02:43:43.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.02:43:43.26#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:43.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:43.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:43.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:43.26#ibcon#enter wrdev, iclass 36, count 0 2006.201.02:43:43.26#ibcon#first serial, iclass 36, count 0 2006.201.02:43:43.26#ibcon#enter sib2, iclass 36, count 0 2006.201.02:43:43.26#ibcon#flushed, iclass 36, count 0 2006.201.02:43:43.26#ibcon#about to write, iclass 36, count 0 2006.201.02:43:43.26#ibcon#wrote, iclass 36, count 0 2006.201.02:43:43.26#ibcon#about to read 3, iclass 36, count 0 2006.201.02:43:43.28#ibcon#read 3, iclass 36, count 0 2006.201.02:43:43.28#ibcon#about to read 4, iclass 36, count 0 2006.201.02:43:43.28#ibcon#read 4, iclass 36, count 0 2006.201.02:43:43.28#ibcon#about to read 5, iclass 36, count 0 2006.201.02:43:43.28#ibcon#read 5, iclass 36, count 0 2006.201.02:43:43.28#ibcon#about to read 6, iclass 36, count 0 2006.201.02:43:43.28#ibcon#read 6, iclass 36, count 0 2006.201.02:43:43.28#ibcon#end of sib2, iclass 36, count 0 2006.201.02:43:43.28#ibcon#*mode == 0, iclass 36, count 0 2006.201.02:43:43.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.02:43:43.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:43:43.28#ibcon#*before write, iclass 36, count 0 2006.201.02:43:43.28#ibcon#enter sib2, iclass 36, count 0 2006.201.02:43:43.28#ibcon#flushed, iclass 36, count 0 2006.201.02:43:43.28#ibcon#about to write, iclass 36, count 0 2006.201.02:43:43.28#ibcon#wrote, iclass 36, count 0 2006.201.02:43:43.28#ibcon#about to read 3, iclass 36, count 0 2006.201.02:43:43.32#ibcon#read 3, iclass 36, count 0 2006.201.02:43:43.32#ibcon#about to read 4, iclass 36, count 0 2006.201.02:43:43.32#ibcon#read 4, iclass 36, count 0 2006.201.02:43:43.32#ibcon#about to read 5, iclass 36, count 0 2006.201.02:43:43.32#ibcon#read 5, iclass 36, count 0 2006.201.02:43:43.32#ibcon#about to read 6, iclass 36, count 0 2006.201.02:43:43.32#ibcon#read 6, iclass 36, count 0 2006.201.02:43:43.32#ibcon#end of sib2, iclass 36, count 0 2006.201.02:43:43.32#ibcon#*after write, iclass 36, count 0 2006.201.02:43:43.32#ibcon#*before return 0, iclass 36, count 0 2006.201.02:43:43.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:43.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:43.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.02:43:43.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.02:43:43.32$vck44/va=8,4 2006.201.02:43:43.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.02:43:43.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.02:43:43.32#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:43.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:43:43.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:43:43.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:43:43.38#ibcon#enter wrdev, iclass 38, count 2 2006.201.02:43:43.38#ibcon#first serial, iclass 38, count 2 2006.201.02:43:43.38#ibcon#enter sib2, iclass 38, count 2 2006.201.02:43:43.38#ibcon#flushed, iclass 38, count 2 2006.201.02:43:43.38#ibcon#about to write, iclass 38, count 2 2006.201.02:43:43.38#ibcon#wrote, iclass 38, count 2 2006.201.02:43:43.38#ibcon#about to read 3, iclass 38, count 2 2006.201.02:43:43.40#ibcon#read 3, iclass 38, count 2 2006.201.02:43:43.40#ibcon#about to read 4, iclass 38, count 2 2006.201.02:43:43.40#ibcon#read 4, iclass 38, count 2 2006.201.02:43:43.40#ibcon#about to read 5, iclass 38, count 2 2006.201.02:43:43.40#ibcon#read 5, iclass 38, count 2 2006.201.02:43:43.40#ibcon#about to read 6, iclass 38, count 2 2006.201.02:43:43.40#ibcon#read 6, iclass 38, count 2 2006.201.02:43:43.40#ibcon#end of sib2, iclass 38, count 2 2006.201.02:43:43.40#ibcon#*mode == 0, iclass 38, count 2 2006.201.02:43:43.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.02:43:43.40#ibcon#[25=AT08-04\r\n] 2006.201.02:43:43.40#ibcon#*before write, iclass 38, count 2 2006.201.02:43:43.40#ibcon#enter sib2, iclass 38, count 2 2006.201.02:43:43.40#ibcon#flushed, iclass 38, count 2 2006.201.02:43:43.40#ibcon#about to write, iclass 38, count 2 2006.201.02:43:43.40#ibcon#wrote, iclass 38, count 2 2006.201.02:43:43.40#ibcon#about to read 3, iclass 38, count 2 2006.201.02:43:43.43#ibcon#read 3, iclass 38, count 2 2006.201.02:43:43.43#ibcon#about to read 4, iclass 38, count 2 2006.201.02:43:43.43#ibcon#read 4, iclass 38, count 2 2006.201.02:43:43.43#ibcon#about to read 5, iclass 38, count 2 2006.201.02:43:43.43#ibcon#read 5, iclass 38, count 2 2006.201.02:43:43.43#ibcon#about to read 6, iclass 38, count 2 2006.201.02:43:43.43#ibcon#read 6, iclass 38, count 2 2006.201.02:43:43.43#ibcon#end of sib2, iclass 38, count 2 2006.201.02:43:43.43#ibcon#*after write, iclass 38, count 2 2006.201.02:43:43.43#ibcon#*before return 0, iclass 38, count 2 2006.201.02:43:43.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:43:43.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.02:43:43.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.02:43:43.43#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:43.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:43:43.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:43:43.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:43:43.55#ibcon#enter wrdev, iclass 38, count 0 2006.201.02:43:43.55#ibcon#first serial, iclass 38, count 0 2006.201.02:43:43.55#ibcon#enter sib2, iclass 38, count 0 2006.201.02:43:43.55#ibcon#flushed, iclass 38, count 0 2006.201.02:43:43.55#ibcon#about to write, iclass 38, count 0 2006.201.02:43:43.55#ibcon#wrote, iclass 38, count 0 2006.201.02:43:43.55#ibcon#about to read 3, iclass 38, count 0 2006.201.02:43:43.57#ibcon#read 3, iclass 38, count 0 2006.201.02:43:43.57#ibcon#about to read 4, iclass 38, count 0 2006.201.02:43:43.57#ibcon#read 4, iclass 38, count 0 2006.201.02:43:43.57#ibcon#about to read 5, iclass 38, count 0 2006.201.02:43:43.57#ibcon#read 5, iclass 38, count 0 2006.201.02:43:43.57#ibcon#about to read 6, iclass 38, count 0 2006.201.02:43:43.57#ibcon#read 6, iclass 38, count 0 2006.201.02:43:43.57#ibcon#end of sib2, iclass 38, count 0 2006.201.02:43:43.57#ibcon#*mode == 0, iclass 38, count 0 2006.201.02:43:43.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.02:43:43.57#ibcon#[25=USB\r\n] 2006.201.02:43:43.57#ibcon#*before write, iclass 38, count 0 2006.201.02:43:43.57#ibcon#enter sib2, iclass 38, count 0 2006.201.02:43:43.57#ibcon#flushed, iclass 38, count 0 2006.201.02:43:43.57#ibcon#about to write, iclass 38, count 0 2006.201.02:43:43.57#ibcon#wrote, iclass 38, count 0 2006.201.02:43:43.57#ibcon#about to read 3, iclass 38, count 0 2006.201.02:43:43.60#ibcon#read 3, iclass 38, count 0 2006.201.02:43:43.60#ibcon#about to read 4, iclass 38, count 0 2006.201.02:43:43.60#ibcon#read 4, iclass 38, count 0 2006.201.02:43:43.60#ibcon#about to read 5, iclass 38, count 0 2006.201.02:43:43.60#ibcon#read 5, iclass 38, count 0 2006.201.02:43:43.60#ibcon#about to read 6, iclass 38, count 0 2006.201.02:43:43.60#ibcon#read 6, iclass 38, count 0 2006.201.02:43:43.60#ibcon#end of sib2, iclass 38, count 0 2006.201.02:43:43.60#ibcon#*after write, iclass 38, count 0 2006.201.02:43:43.60#ibcon#*before return 0, iclass 38, count 0 2006.201.02:43:43.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:43:43.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.02:43:43.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.02:43:43.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.02:43:43.60$vck44/vblo=1,629.99 2006.201.02:43:43.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.02:43:43.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.02:43:43.60#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:43.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:43:43.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:43:43.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:43:43.60#ibcon#enter wrdev, iclass 40, count 0 2006.201.02:43:43.60#ibcon#first serial, iclass 40, count 0 2006.201.02:43:43.60#ibcon#enter sib2, iclass 40, count 0 2006.201.02:43:43.60#ibcon#flushed, iclass 40, count 0 2006.201.02:43:43.60#ibcon#about to write, iclass 40, count 0 2006.201.02:43:43.60#ibcon#wrote, iclass 40, count 0 2006.201.02:43:43.60#ibcon#about to read 3, iclass 40, count 0 2006.201.02:43:43.62#ibcon#read 3, iclass 40, count 0 2006.201.02:43:43.62#ibcon#about to read 4, iclass 40, count 0 2006.201.02:43:43.62#ibcon#read 4, iclass 40, count 0 2006.201.02:43:43.62#ibcon#about to read 5, iclass 40, count 0 2006.201.02:43:43.62#ibcon#read 5, iclass 40, count 0 2006.201.02:43:43.62#ibcon#about to read 6, iclass 40, count 0 2006.201.02:43:43.62#ibcon#read 6, iclass 40, count 0 2006.201.02:43:43.62#ibcon#end of sib2, iclass 40, count 0 2006.201.02:43:43.62#ibcon#*mode == 0, iclass 40, count 0 2006.201.02:43:43.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.02:43:43.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:43:43.62#ibcon#*before write, iclass 40, count 0 2006.201.02:43:43.62#ibcon#enter sib2, iclass 40, count 0 2006.201.02:43:43.62#ibcon#flushed, iclass 40, count 0 2006.201.02:43:43.62#ibcon#about to write, iclass 40, count 0 2006.201.02:43:43.62#ibcon#wrote, iclass 40, count 0 2006.201.02:43:43.62#ibcon#about to read 3, iclass 40, count 0 2006.201.02:43:43.66#ibcon#read 3, iclass 40, count 0 2006.201.02:43:43.66#ibcon#about to read 4, iclass 40, count 0 2006.201.02:43:43.66#ibcon#read 4, iclass 40, count 0 2006.201.02:43:43.66#ibcon#about to read 5, iclass 40, count 0 2006.201.02:43:43.66#ibcon#read 5, iclass 40, count 0 2006.201.02:43:43.66#ibcon#about to read 6, iclass 40, count 0 2006.201.02:43:43.66#ibcon#read 6, iclass 40, count 0 2006.201.02:43:43.66#ibcon#end of sib2, iclass 40, count 0 2006.201.02:43:43.66#ibcon#*after write, iclass 40, count 0 2006.201.02:43:43.66#ibcon#*before return 0, iclass 40, count 0 2006.201.02:43:43.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:43:43.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.02:43:43.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.02:43:43.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.02:43:43.66$vck44/vb=1,4 2006.201.02:43:43.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.02:43:43.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.02:43:43.66#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:43.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:43:43.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:43:43.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:43:43.66#ibcon#enter wrdev, iclass 4, count 2 2006.201.02:43:43.66#ibcon#first serial, iclass 4, count 2 2006.201.02:43:43.66#ibcon#enter sib2, iclass 4, count 2 2006.201.02:43:43.66#ibcon#flushed, iclass 4, count 2 2006.201.02:43:43.66#ibcon#about to write, iclass 4, count 2 2006.201.02:43:43.66#ibcon#wrote, iclass 4, count 2 2006.201.02:43:43.66#ibcon#about to read 3, iclass 4, count 2 2006.201.02:43:43.68#ibcon#read 3, iclass 4, count 2 2006.201.02:43:43.68#ibcon#about to read 4, iclass 4, count 2 2006.201.02:43:43.68#ibcon#read 4, iclass 4, count 2 2006.201.02:43:43.68#ibcon#about to read 5, iclass 4, count 2 2006.201.02:43:43.68#ibcon#read 5, iclass 4, count 2 2006.201.02:43:43.68#ibcon#about to read 6, iclass 4, count 2 2006.201.02:43:43.68#ibcon#read 6, iclass 4, count 2 2006.201.02:43:43.68#ibcon#end of sib2, iclass 4, count 2 2006.201.02:43:43.68#ibcon#*mode == 0, iclass 4, count 2 2006.201.02:43:43.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.02:43:43.68#ibcon#[27=AT01-04\r\n] 2006.201.02:43:43.68#ibcon#*before write, iclass 4, count 2 2006.201.02:43:43.68#ibcon#enter sib2, iclass 4, count 2 2006.201.02:43:43.68#ibcon#flushed, iclass 4, count 2 2006.201.02:43:43.68#ibcon#about to write, iclass 4, count 2 2006.201.02:43:43.68#ibcon#wrote, iclass 4, count 2 2006.201.02:43:43.68#ibcon#about to read 3, iclass 4, count 2 2006.201.02:43:43.71#ibcon#read 3, iclass 4, count 2 2006.201.02:43:43.71#ibcon#about to read 4, iclass 4, count 2 2006.201.02:43:43.71#ibcon#read 4, iclass 4, count 2 2006.201.02:43:43.71#ibcon#about to read 5, iclass 4, count 2 2006.201.02:43:43.71#ibcon#read 5, iclass 4, count 2 2006.201.02:43:43.71#ibcon#about to read 6, iclass 4, count 2 2006.201.02:43:43.71#ibcon#read 6, iclass 4, count 2 2006.201.02:43:43.71#ibcon#end of sib2, iclass 4, count 2 2006.201.02:43:43.71#ibcon#*after write, iclass 4, count 2 2006.201.02:43:43.71#ibcon#*before return 0, iclass 4, count 2 2006.201.02:43:43.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:43:43.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.02:43:43.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.02:43:43.71#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:43.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:43:43.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:43:43.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:43:43.83#ibcon#enter wrdev, iclass 4, count 0 2006.201.02:43:43.83#ibcon#first serial, iclass 4, count 0 2006.201.02:43:43.83#ibcon#enter sib2, iclass 4, count 0 2006.201.02:43:43.83#ibcon#flushed, iclass 4, count 0 2006.201.02:43:43.83#ibcon#about to write, iclass 4, count 0 2006.201.02:43:43.83#ibcon#wrote, iclass 4, count 0 2006.201.02:43:43.83#ibcon#about to read 3, iclass 4, count 0 2006.201.02:43:43.85#ibcon#read 3, iclass 4, count 0 2006.201.02:43:43.85#ibcon#about to read 4, iclass 4, count 0 2006.201.02:43:43.85#ibcon#read 4, iclass 4, count 0 2006.201.02:43:43.85#ibcon#about to read 5, iclass 4, count 0 2006.201.02:43:43.85#ibcon#read 5, iclass 4, count 0 2006.201.02:43:43.85#ibcon#about to read 6, iclass 4, count 0 2006.201.02:43:43.85#ibcon#read 6, iclass 4, count 0 2006.201.02:43:43.85#ibcon#end of sib2, iclass 4, count 0 2006.201.02:43:43.85#ibcon#*mode == 0, iclass 4, count 0 2006.201.02:43:43.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.02:43:43.85#ibcon#[27=USB\r\n] 2006.201.02:43:43.85#ibcon#*before write, iclass 4, count 0 2006.201.02:43:43.85#ibcon#enter sib2, iclass 4, count 0 2006.201.02:43:43.85#ibcon#flushed, iclass 4, count 0 2006.201.02:43:43.85#ibcon#about to write, iclass 4, count 0 2006.201.02:43:43.85#ibcon#wrote, iclass 4, count 0 2006.201.02:43:43.85#ibcon#about to read 3, iclass 4, count 0 2006.201.02:43:43.88#ibcon#read 3, iclass 4, count 0 2006.201.02:43:43.88#ibcon#about to read 4, iclass 4, count 0 2006.201.02:43:43.88#ibcon#read 4, iclass 4, count 0 2006.201.02:43:43.88#ibcon#about to read 5, iclass 4, count 0 2006.201.02:43:43.88#ibcon#read 5, iclass 4, count 0 2006.201.02:43:43.88#ibcon#about to read 6, iclass 4, count 0 2006.201.02:43:43.88#ibcon#read 6, iclass 4, count 0 2006.201.02:43:43.88#ibcon#end of sib2, iclass 4, count 0 2006.201.02:43:43.88#ibcon#*after write, iclass 4, count 0 2006.201.02:43:43.88#ibcon#*before return 0, iclass 4, count 0 2006.201.02:43:43.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:43:43.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.02:43:43.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.02:43:43.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.02:43:43.88$vck44/vblo=2,634.99 2006.201.02:43:43.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.02:43:43.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.02:43:43.88#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:43.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:43.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:43.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:43.88#ibcon#enter wrdev, iclass 6, count 0 2006.201.02:43:43.88#ibcon#first serial, iclass 6, count 0 2006.201.02:43:43.88#ibcon#enter sib2, iclass 6, count 0 2006.201.02:43:43.88#ibcon#flushed, iclass 6, count 0 2006.201.02:43:43.88#ibcon#about to write, iclass 6, count 0 2006.201.02:43:43.88#ibcon#wrote, iclass 6, count 0 2006.201.02:43:43.88#ibcon#about to read 3, iclass 6, count 0 2006.201.02:43:43.90#ibcon#read 3, iclass 6, count 0 2006.201.02:43:43.90#ibcon#about to read 4, iclass 6, count 0 2006.201.02:43:43.90#ibcon#read 4, iclass 6, count 0 2006.201.02:43:43.90#ibcon#about to read 5, iclass 6, count 0 2006.201.02:43:43.90#ibcon#read 5, iclass 6, count 0 2006.201.02:43:43.90#ibcon#about to read 6, iclass 6, count 0 2006.201.02:43:43.90#ibcon#read 6, iclass 6, count 0 2006.201.02:43:43.90#ibcon#end of sib2, iclass 6, count 0 2006.201.02:43:43.90#ibcon#*mode == 0, iclass 6, count 0 2006.201.02:43:43.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.02:43:43.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:43:43.90#ibcon#*before write, iclass 6, count 0 2006.201.02:43:43.90#ibcon#enter sib2, iclass 6, count 0 2006.201.02:43:43.90#ibcon#flushed, iclass 6, count 0 2006.201.02:43:43.90#ibcon#about to write, iclass 6, count 0 2006.201.02:43:43.90#ibcon#wrote, iclass 6, count 0 2006.201.02:43:43.90#ibcon#about to read 3, iclass 6, count 0 2006.201.02:43:43.94#ibcon#read 3, iclass 6, count 0 2006.201.02:43:43.94#ibcon#about to read 4, iclass 6, count 0 2006.201.02:43:43.94#ibcon#read 4, iclass 6, count 0 2006.201.02:43:43.94#ibcon#about to read 5, iclass 6, count 0 2006.201.02:43:43.94#ibcon#read 5, iclass 6, count 0 2006.201.02:43:43.94#ibcon#about to read 6, iclass 6, count 0 2006.201.02:43:43.94#ibcon#read 6, iclass 6, count 0 2006.201.02:43:43.94#ibcon#end of sib2, iclass 6, count 0 2006.201.02:43:43.94#ibcon#*after write, iclass 6, count 0 2006.201.02:43:43.94#ibcon#*before return 0, iclass 6, count 0 2006.201.02:43:43.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:43.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.02:43:43.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.02:43:43.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.02:43:43.94$vck44/vb=2,5 2006.201.02:43:43.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.02:43:43.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.02:43:43.94#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:43.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:44.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:44.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:44.00#ibcon#enter wrdev, iclass 10, count 2 2006.201.02:43:44.00#ibcon#first serial, iclass 10, count 2 2006.201.02:43:44.00#ibcon#enter sib2, iclass 10, count 2 2006.201.02:43:44.00#ibcon#flushed, iclass 10, count 2 2006.201.02:43:44.00#ibcon#about to write, iclass 10, count 2 2006.201.02:43:44.00#ibcon#wrote, iclass 10, count 2 2006.201.02:43:44.00#ibcon#about to read 3, iclass 10, count 2 2006.201.02:43:44.02#ibcon#read 3, iclass 10, count 2 2006.201.02:43:44.02#ibcon#about to read 4, iclass 10, count 2 2006.201.02:43:44.02#ibcon#read 4, iclass 10, count 2 2006.201.02:43:44.02#ibcon#about to read 5, iclass 10, count 2 2006.201.02:43:44.02#ibcon#read 5, iclass 10, count 2 2006.201.02:43:44.02#ibcon#about to read 6, iclass 10, count 2 2006.201.02:43:44.02#ibcon#read 6, iclass 10, count 2 2006.201.02:43:44.02#ibcon#end of sib2, iclass 10, count 2 2006.201.02:43:44.02#ibcon#*mode == 0, iclass 10, count 2 2006.201.02:43:44.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.02:43:44.02#ibcon#[27=AT02-05\r\n] 2006.201.02:43:44.02#ibcon#*before write, iclass 10, count 2 2006.201.02:43:44.02#ibcon#enter sib2, iclass 10, count 2 2006.201.02:43:44.02#ibcon#flushed, iclass 10, count 2 2006.201.02:43:44.02#ibcon#about to write, iclass 10, count 2 2006.201.02:43:44.02#ibcon#wrote, iclass 10, count 2 2006.201.02:43:44.02#ibcon#about to read 3, iclass 10, count 2 2006.201.02:43:44.05#ibcon#read 3, iclass 10, count 2 2006.201.02:43:44.05#ibcon#about to read 4, iclass 10, count 2 2006.201.02:43:44.05#ibcon#read 4, iclass 10, count 2 2006.201.02:43:44.05#ibcon#about to read 5, iclass 10, count 2 2006.201.02:43:44.05#ibcon#read 5, iclass 10, count 2 2006.201.02:43:44.05#ibcon#about to read 6, iclass 10, count 2 2006.201.02:43:44.05#ibcon#read 6, iclass 10, count 2 2006.201.02:43:44.05#ibcon#end of sib2, iclass 10, count 2 2006.201.02:43:44.05#ibcon#*after write, iclass 10, count 2 2006.201.02:43:44.05#ibcon#*before return 0, iclass 10, count 2 2006.201.02:43:44.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:44.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.02:43:44.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.02:43:44.05#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:44.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:44.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:44.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:44.17#ibcon#enter wrdev, iclass 10, count 0 2006.201.02:43:44.17#ibcon#first serial, iclass 10, count 0 2006.201.02:43:44.17#ibcon#enter sib2, iclass 10, count 0 2006.201.02:43:44.17#ibcon#flushed, iclass 10, count 0 2006.201.02:43:44.17#ibcon#about to write, iclass 10, count 0 2006.201.02:43:44.17#ibcon#wrote, iclass 10, count 0 2006.201.02:43:44.17#ibcon#about to read 3, iclass 10, count 0 2006.201.02:43:44.19#ibcon#read 3, iclass 10, count 0 2006.201.02:43:44.19#ibcon#about to read 4, iclass 10, count 0 2006.201.02:43:44.19#ibcon#read 4, iclass 10, count 0 2006.201.02:43:44.19#ibcon#about to read 5, iclass 10, count 0 2006.201.02:43:44.19#ibcon#read 5, iclass 10, count 0 2006.201.02:43:44.19#ibcon#about to read 6, iclass 10, count 0 2006.201.02:43:44.19#ibcon#read 6, iclass 10, count 0 2006.201.02:43:44.19#ibcon#end of sib2, iclass 10, count 0 2006.201.02:43:44.19#ibcon#*mode == 0, iclass 10, count 0 2006.201.02:43:44.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.02:43:44.19#ibcon#[27=USB\r\n] 2006.201.02:43:44.19#ibcon#*before write, iclass 10, count 0 2006.201.02:43:44.19#ibcon#enter sib2, iclass 10, count 0 2006.201.02:43:44.19#ibcon#flushed, iclass 10, count 0 2006.201.02:43:44.19#ibcon#about to write, iclass 10, count 0 2006.201.02:43:44.19#ibcon#wrote, iclass 10, count 0 2006.201.02:43:44.19#ibcon#about to read 3, iclass 10, count 0 2006.201.02:43:44.22#ibcon#read 3, iclass 10, count 0 2006.201.02:43:44.22#ibcon#about to read 4, iclass 10, count 0 2006.201.02:43:44.22#ibcon#read 4, iclass 10, count 0 2006.201.02:43:44.22#ibcon#about to read 5, iclass 10, count 0 2006.201.02:43:44.22#ibcon#read 5, iclass 10, count 0 2006.201.02:43:44.22#ibcon#about to read 6, iclass 10, count 0 2006.201.02:43:44.22#ibcon#read 6, iclass 10, count 0 2006.201.02:43:44.22#ibcon#end of sib2, iclass 10, count 0 2006.201.02:43:44.22#ibcon#*after write, iclass 10, count 0 2006.201.02:43:44.22#ibcon#*before return 0, iclass 10, count 0 2006.201.02:43:44.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:44.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.02:43:44.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.02:43:44.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.02:43:44.22$vck44/vblo=3,649.99 2006.201.02:43:44.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.02:43:44.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.02:43:44.22#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:44.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:44.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:44.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:44.22#ibcon#enter wrdev, iclass 12, count 0 2006.201.02:43:44.22#ibcon#first serial, iclass 12, count 0 2006.201.02:43:44.22#ibcon#enter sib2, iclass 12, count 0 2006.201.02:43:44.22#ibcon#flushed, iclass 12, count 0 2006.201.02:43:44.22#ibcon#about to write, iclass 12, count 0 2006.201.02:43:44.22#ibcon#wrote, iclass 12, count 0 2006.201.02:43:44.22#ibcon#about to read 3, iclass 12, count 0 2006.201.02:43:44.24#ibcon#read 3, iclass 12, count 0 2006.201.02:43:44.24#ibcon#about to read 4, iclass 12, count 0 2006.201.02:43:44.24#ibcon#read 4, iclass 12, count 0 2006.201.02:43:44.24#ibcon#about to read 5, iclass 12, count 0 2006.201.02:43:44.24#ibcon#read 5, iclass 12, count 0 2006.201.02:43:44.24#ibcon#about to read 6, iclass 12, count 0 2006.201.02:43:44.24#ibcon#read 6, iclass 12, count 0 2006.201.02:43:44.24#ibcon#end of sib2, iclass 12, count 0 2006.201.02:43:44.24#ibcon#*mode == 0, iclass 12, count 0 2006.201.02:43:44.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.02:43:44.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:43:44.24#ibcon#*before write, iclass 12, count 0 2006.201.02:43:44.24#ibcon#enter sib2, iclass 12, count 0 2006.201.02:43:44.24#ibcon#flushed, iclass 12, count 0 2006.201.02:43:44.24#ibcon#about to write, iclass 12, count 0 2006.201.02:43:44.24#ibcon#wrote, iclass 12, count 0 2006.201.02:43:44.24#ibcon#about to read 3, iclass 12, count 0 2006.201.02:43:44.28#ibcon#read 3, iclass 12, count 0 2006.201.02:43:44.28#ibcon#about to read 4, iclass 12, count 0 2006.201.02:43:44.28#ibcon#read 4, iclass 12, count 0 2006.201.02:43:44.28#ibcon#about to read 5, iclass 12, count 0 2006.201.02:43:44.28#ibcon#read 5, iclass 12, count 0 2006.201.02:43:44.28#ibcon#about to read 6, iclass 12, count 0 2006.201.02:43:44.28#ibcon#read 6, iclass 12, count 0 2006.201.02:43:44.28#ibcon#end of sib2, iclass 12, count 0 2006.201.02:43:44.28#ibcon#*after write, iclass 12, count 0 2006.201.02:43:44.28#ibcon#*before return 0, iclass 12, count 0 2006.201.02:43:44.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:44.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.02:43:44.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.02:43:44.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.02:43:44.28$vck44/vb=3,4 2006.201.02:43:44.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.02:43:44.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.02:43:44.28#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:44.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:44.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:44.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:44.34#ibcon#enter wrdev, iclass 14, count 2 2006.201.02:43:44.34#ibcon#first serial, iclass 14, count 2 2006.201.02:43:44.34#ibcon#enter sib2, iclass 14, count 2 2006.201.02:43:44.34#ibcon#flushed, iclass 14, count 2 2006.201.02:43:44.34#ibcon#about to write, iclass 14, count 2 2006.201.02:43:44.34#ibcon#wrote, iclass 14, count 2 2006.201.02:43:44.34#ibcon#about to read 3, iclass 14, count 2 2006.201.02:43:44.36#ibcon#read 3, iclass 14, count 2 2006.201.02:43:44.36#ibcon#about to read 4, iclass 14, count 2 2006.201.02:43:44.36#ibcon#read 4, iclass 14, count 2 2006.201.02:43:44.36#ibcon#about to read 5, iclass 14, count 2 2006.201.02:43:44.36#ibcon#read 5, iclass 14, count 2 2006.201.02:43:44.36#ibcon#about to read 6, iclass 14, count 2 2006.201.02:43:44.36#ibcon#read 6, iclass 14, count 2 2006.201.02:43:44.36#ibcon#end of sib2, iclass 14, count 2 2006.201.02:43:44.36#ibcon#*mode == 0, iclass 14, count 2 2006.201.02:43:44.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.02:43:44.36#ibcon#[27=AT03-04\r\n] 2006.201.02:43:44.36#ibcon#*before write, iclass 14, count 2 2006.201.02:43:44.36#ibcon#enter sib2, iclass 14, count 2 2006.201.02:43:44.36#ibcon#flushed, iclass 14, count 2 2006.201.02:43:44.36#ibcon#about to write, iclass 14, count 2 2006.201.02:43:44.36#ibcon#wrote, iclass 14, count 2 2006.201.02:43:44.36#ibcon#about to read 3, iclass 14, count 2 2006.201.02:43:44.39#ibcon#read 3, iclass 14, count 2 2006.201.02:43:44.39#ibcon#about to read 4, iclass 14, count 2 2006.201.02:43:44.39#ibcon#read 4, iclass 14, count 2 2006.201.02:43:44.39#ibcon#about to read 5, iclass 14, count 2 2006.201.02:43:44.39#ibcon#read 5, iclass 14, count 2 2006.201.02:43:44.39#ibcon#about to read 6, iclass 14, count 2 2006.201.02:43:44.39#ibcon#read 6, iclass 14, count 2 2006.201.02:43:44.39#ibcon#end of sib2, iclass 14, count 2 2006.201.02:43:44.39#ibcon#*after write, iclass 14, count 2 2006.201.02:43:44.39#ibcon#*before return 0, iclass 14, count 2 2006.201.02:43:44.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:44.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.02:43:44.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.02:43:44.39#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:44.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:44.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:44.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:44.51#ibcon#enter wrdev, iclass 14, count 0 2006.201.02:43:44.51#ibcon#first serial, iclass 14, count 0 2006.201.02:43:44.51#ibcon#enter sib2, iclass 14, count 0 2006.201.02:43:44.51#ibcon#flushed, iclass 14, count 0 2006.201.02:43:44.51#ibcon#about to write, iclass 14, count 0 2006.201.02:43:44.51#ibcon#wrote, iclass 14, count 0 2006.201.02:43:44.51#ibcon#about to read 3, iclass 14, count 0 2006.201.02:43:44.53#ibcon#read 3, iclass 14, count 0 2006.201.02:43:44.53#ibcon#about to read 4, iclass 14, count 0 2006.201.02:43:44.53#ibcon#read 4, iclass 14, count 0 2006.201.02:43:44.53#ibcon#about to read 5, iclass 14, count 0 2006.201.02:43:44.53#ibcon#read 5, iclass 14, count 0 2006.201.02:43:44.53#ibcon#about to read 6, iclass 14, count 0 2006.201.02:43:44.53#ibcon#read 6, iclass 14, count 0 2006.201.02:43:44.53#ibcon#end of sib2, iclass 14, count 0 2006.201.02:43:44.53#ibcon#*mode == 0, iclass 14, count 0 2006.201.02:43:44.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.02:43:44.53#ibcon#[27=USB\r\n] 2006.201.02:43:44.53#ibcon#*before write, iclass 14, count 0 2006.201.02:43:44.53#ibcon#enter sib2, iclass 14, count 0 2006.201.02:43:44.53#ibcon#flushed, iclass 14, count 0 2006.201.02:43:44.53#ibcon#about to write, iclass 14, count 0 2006.201.02:43:44.53#ibcon#wrote, iclass 14, count 0 2006.201.02:43:44.53#ibcon#about to read 3, iclass 14, count 0 2006.201.02:43:44.56#ibcon#read 3, iclass 14, count 0 2006.201.02:43:44.56#ibcon#about to read 4, iclass 14, count 0 2006.201.02:43:44.56#ibcon#read 4, iclass 14, count 0 2006.201.02:43:44.56#ibcon#about to read 5, iclass 14, count 0 2006.201.02:43:44.56#ibcon#read 5, iclass 14, count 0 2006.201.02:43:44.56#ibcon#about to read 6, iclass 14, count 0 2006.201.02:43:44.56#ibcon#read 6, iclass 14, count 0 2006.201.02:43:44.56#ibcon#end of sib2, iclass 14, count 0 2006.201.02:43:44.56#ibcon#*after write, iclass 14, count 0 2006.201.02:43:44.56#ibcon#*before return 0, iclass 14, count 0 2006.201.02:43:44.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:44.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.02:43:44.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.02:43:44.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.02:43:44.56$vck44/vblo=4,679.99 2006.201.02:43:44.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.02:43:44.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.02:43:44.56#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:44.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:44.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:44.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:44.56#ibcon#enter wrdev, iclass 16, count 0 2006.201.02:43:44.56#ibcon#first serial, iclass 16, count 0 2006.201.02:43:44.56#ibcon#enter sib2, iclass 16, count 0 2006.201.02:43:44.56#ibcon#flushed, iclass 16, count 0 2006.201.02:43:44.56#ibcon#about to write, iclass 16, count 0 2006.201.02:43:44.56#ibcon#wrote, iclass 16, count 0 2006.201.02:43:44.56#ibcon#about to read 3, iclass 16, count 0 2006.201.02:43:44.58#ibcon#read 3, iclass 16, count 0 2006.201.02:43:44.58#ibcon#about to read 4, iclass 16, count 0 2006.201.02:43:44.58#ibcon#read 4, iclass 16, count 0 2006.201.02:43:44.58#ibcon#about to read 5, iclass 16, count 0 2006.201.02:43:44.58#ibcon#read 5, iclass 16, count 0 2006.201.02:43:44.58#ibcon#about to read 6, iclass 16, count 0 2006.201.02:43:44.58#ibcon#read 6, iclass 16, count 0 2006.201.02:43:44.58#ibcon#end of sib2, iclass 16, count 0 2006.201.02:43:44.58#ibcon#*mode == 0, iclass 16, count 0 2006.201.02:43:44.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.02:43:44.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:43:44.58#ibcon#*before write, iclass 16, count 0 2006.201.02:43:44.58#ibcon#enter sib2, iclass 16, count 0 2006.201.02:43:44.58#ibcon#flushed, iclass 16, count 0 2006.201.02:43:44.58#ibcon#about to write, iclass 16, count 0 2006.201.02:43:44.58#ibcon#wrote, iclass 16, count 0 2006.201.02:43:44.58#ibcon#about to read 3, iclass 16, count 0 2006.201.02:43:44.62#ibcon#read 3, iclass 16, count 0 2006.201.02:43:44.62#ibcon#about to read 4, iclass 16, count 0 2006.201.02:43:44.62#ibcon#read 4, iclass 16, count 0 2006.201.02:43:44.62#ibcon#about to read 5, iclass 16, count 0 2006.201.02:43:44.62#ibcon#read 5, iclass 16, count 0 2006.201.02:43:44.62#ibcon#about to read 6, iclass 16, count 0 2006.201.02:43:44.62#ibcon#read 6, iclass 16, count 0 2006.201.02:43:44.62#ibcon#end of sib2, iclass 16, count 0 2006.201.02:43:44.62#ibcon#*after write, iclass 16, count 0 2006.201.02:43:44.62#ibcon#*before return 0, iclass 16, count 0 2006.201.02:43:44.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:44.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.02:43:44.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.02:43:44.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.02:43:44.62$vck44/vb=4,5 2006.201.02:43:44.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.02:43:44.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.02:43:44.62#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:44.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:44.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:44.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:44.68#ibcon#enter wrdev, iclass 18, count 2 2006.201.02:43:44.68#ibcon#first serial, iclass 18, count 2 2006.201.02:43:44.68#ibcon#enter sib2, iclass 18, count 2 2006.201.02:43:44.68#ibcon#flushed, iclass 18, count 2 2006.201.02:43:44.68#ibcon#about to write, iclass 18, count 2 2006.201.02:43:44.68#ibcon#wrote, iclass 18, count 2 2006.201.02:43:44.68#ibcon#about to read 3, iclass 18, count 2 2006.201.02:43:44.70#ibcon#read 3, iclass 18, count 2 2006.201.02:43:44.70#ibcon#about to read 4, iclass 18, count 2 2006.201.02:43:44.70#ibcon#read 4, iclass 18, count 2 2006.201.02:43:44.70#ibcon#about to read 5, iclass 18, count 2 2006.201.02:43:44.70#ibcon#read 5, iclass 18, count 2 2006.201.02:43:44.70#ibcon#about to read 6, iclass 18, count 2 2006.201.02:43:44.70#ibcon#read 6, iclass 18, count 2 2006.201.02:43:44.70#ibcon#end of sib2, iclass 18, count 2 2006.201.02:43:44.70#ibcon#*mode == 0, iclass 18, count 2 2006.201.02:43:44.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.02:43:44.70#ibcon#[27=AT04-05\r\n] 2006.201.02:43:44.70#ibcon#*before write, iclass 18, count 2 2006.201.02:43:44.70#ibcon#enter sib2, iclass 18, count 2 2006.201.02:43:44.70#ibcon#flushed, iclass 18, count 2 2006.201.02:43:44.70#ibcon#about to write, iclass 18, count 2 2006.201.02:43:44.70#ibcon#wrote, iclass 18, count 2 2006.201.02:43:44.70#ibcon#about to read 3, iclass 18, count 2 2006.201.02:43:44.73#ibcon#read 3, iclass 18, count 2 2006.201.02:43:44.73#ibcon#about to read 4, iclass 18, count 2 2006.201.02:43:44.73#ibcon#read 4, iclass 18, count 2 2006.201.02:43:44.73#ibcon#about to read 5, iclass 18, count 2 2006.201.02:43:44.73#ibcon#read 5, iclass 18, count 2 2006.201.02:43:44.73#ibcon#about to read 6, iclass 18, count 2 2006.201.02:43:44.73#ibcon#read 6, iclass 18, count 2 2006.201.02:43:44.73#ibcon#end of sib2, iclass 18, count 2 2006.201.02:43:44.73#ibcon#*after write, iclass 18, count 2 2006.201.02:43:44.73#ibcon#*before return 0, iclass 18, count 2 2006.201.02:43:44.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:44.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.02:43:44.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.02:43:44.73#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:44.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:44.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:44.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:44.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.02:43:44.85#ibcon#first serial, iclass 18, count 0 2006.201.02:43:44.85#ibcon#enter sib2, iclass 18, count 0 2006.201.02:43:44.85#ibcon#flushed, iclass 18, count 0 2006.201.02:43:44.85#ibcon#about to write, iclass 18, count 0 2006.201.02:43:44.85#ibcon#wrote, iclass 18, count 0 2006.201.02:43:44.85#ibcon#about to read 3, iclass 18, count 0 2006.201.02:43:44.87#ibcon#read 3, iclass 18, count 0 2006.201.02:43:44.87#ibcon#about to read 4, iclass 18, count 0 2006.201.02:43:44.87#ibcon#read 4, iclass 18, count 0 2006.201.02:43:44.87#ibcon#about to read 5, iclass 18, count 0 2006.201.02:43:44.87#ibcon#read 5, iclass 18, count 0 2006.201.02:43:44.87#ibcon#about to read 6, iclass 18, count 0 2006.201.02:43:44.87#ibcon#read 6, iclass 18, count 0 2006.201.02:43:44.87#ibcon#end of sib2, iclass 18, count 0 2006.201.02:43:44.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.02:43:44.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.02:43:44.87#ibcon#[27=USB\r\n] 2006.201.02:43:44.87#ibcon#*before write, iclass 18, count 0 2006.201.02:43:44.87#ibcon#enter sib2, iclass 18, count 0 2006.201.02:43:44.87#ibcon#flushed, iclass 18, count 0 2006.201.02:43:44.87#ibcon#about to write, iclass 18, count 0 2006.201.02:43:44.87#ibcon#wrote, iclass 18, count 0 2006.201.02:43:44.87#ibcon#about to read 3, iclass 18, count 0 2006.201.02:43:44.90#ibcon#read 3, iclass 18, count 0 2006.201.02:43:44.90#ibcon#about to read 4, iclass 18, count 0 2006.201.02:43:44.90#ibcon#read 4, iclass 18, count 0 2006.201.02:43:44.90#ibcon#about to read 5, iclass 18, count 0 2006.201.02:43:44.90#ibcon#read 5, iclass 18, count 0 2006.201.02:43:44.90#ibcon#about to read 6, iclass 18, count 0 2006.201.02:43:44.90#ibcon#read 6, iclass 18, count 0 2006.201.02:43:44.90#ibcon#end of sib2, iclass 18, count 0 2006.201.02:43:44.90#ibcon#*after write, iclass 18, count 0 2006.201.02:43:44.90#ibcon#*before return 0, iclass 18, count 0 2006.201.02:43:44.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:44.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.02:43:44.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.02:43:44.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.02:43:44.90$vck44/vblo=5,709.99 2006.201.02:43:44.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.02:43:44.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.02:43:44.90#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:44.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:44.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:44.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:44.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.02:43:44.90#ibcon#first serial, iclass 20, count 0 2006.201.02:43:44.90#ibcon#enter sib2, iclass 20, count 0 2006.201.02:43:44.90#ibcon#flushed, iclass 20, count 0 2006.201.02:43:44.90#ibcon#about to write, iclass 20, count 0 2006.201.02:43:44.90#ibcon#wrote, iclass 20, count 0 2006.201.02:43:44.90#ibcon#about to read 3, iclass 20, count 0 2006.201.02:43:44.92#ibcon#read 3, iclass 20, count 0 2006.201.02:43:44.92#ibcon#about to read 4, iclass 20, count 0 2006.201.02:43:44.92#ibcon#read 4, iclass 20, count 0 2006.201.02:43:44.92#ibcon#about to read 5, iclass 20, count 0 2006.201.02:43:44.92#ibcon#read 5, iclass 20, count 0 2006.201.02:43:44.92#ibcon#about to read 6, iclass 20, count 0 2006.201.02:43:44.92#ibcon#read 6, iclass 20, count 0 2006.201.02:43:44.92#ibcon#end of sib2, iclass 20, count 0 2006.201.02:43:44.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.02:43:44.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.02:43:44.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:43:44.92#ibcon#*before write, iclass 20, count 0 2006.201.02:43:44.92#ibcon#enter sib2, iclass 20, count 0 2006.201.02:43:44.92#ibcon#flushed, iclass 20, count 0 2006.201.02:43:44.92#ibcon#about to write, iclass 20, count 0 2006.201.02:43:44.92#ibcon#wrote, iclass 20, count 0 2006.201.02:43:44.92#ibcon#about to read 3, iclass 20, count 0 2006.201.02:43:44.96#ibcon#read 3, iclass 20, count 0 2006.201.02:43:44.96#ibcon#about to read 4, iclass 20, count 0 2006.201.02:43:44.96#ibcon#read 4, iclass 20, count 0 2006.201.02:43:44.96#ibcon#about to read 5, iclass 20, count 0 2006.201.02:43:44.96#ibcon#read 5, iclass 20, count 0 2006.201.02:43:44.96#ibcon#about to read 6, iclass 20, count 0 2006.201.02:43:44.96#ibcon#read 6, iclass 20, count 0 2006.201.02:43:44.96#ibcon#end of sib2, iclass 20, count 0 2006.201.02:43:44.96#ibcon#*after write, iclass 20, count 0 2006.201.02:43:44.96#ibcon#*before return 0, iclass 20, count 0 2006.201.02:43:44.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:44.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.02:43:44.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.02:43:44.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.02:43:44.96$vck44/vb=5,4 2006.201.02:43:44.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.02:43:44.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.02:43:44.96#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:44.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:45.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:45.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:45.02#ibcon#enter wrdev, iclass 22, count 2 2006.201.02:43:45.02#ibcon#first serial, iclass 22, count 2 2006.201.02:43:45.02#ibcon#enter sib2, iclass 22, count 2 2006.201.02:43:45.02#ibcon#flushed, iclass 22, count 2 2006.201.02:43:45.02#ibcon#about to write, iclass 22, count 2 2006.201.02:43:45.02#ibcon#wrote, iclass 22, count 2 2006.201.02:43:45.02#ibcon#about to read 3, iclass 22, count 2 2006.201.02:43:45.04#ibcon#read 3, iclass 22, count 2 2006.201.02:43:45.04#ibcon#about to read 4, iclass 22, count 2 2006.201.02:43:45.04#ibcon#read 4, iclass 22, count 2 2006.201.02:43:45.04#ibcon#about to read 5, iclass 22, count 2 2006.201.02:43:45.04#ibcon#read 5, iclass 22, count 2 2006.201.02:43:45.04#ibcon#about to read 6, iclass 22, count 2 2006.201.02:43:45.04#ibcon#read 6, iclass 22, count 2 2006.201.02:43:45.04#ibcon#end of sib2, iclass 22, count 2 2006.201.02:43:45.04#ibcon#*mode == 0, iclass 22, count 2 2006.201.02:43:45.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.02:43:45.04#ibcon#[27=AT05-04\r\n] 2006.201.02:43:45.04#ibcon#*before write, iclass 22, count 2 2006.201.02:43:45.04#ibcon#enter sib2, iclass 22, count 2 2006.201.02:43:45.04#ibcon#flushed, iclass 22, count 2 2006.201.02:43:45.04#ibcon#about to write, iclass 22, count 2 2006.201.02:43:45.04#ibcon#wrote, iclass 22, count 2 2006.201.02:43:45.04#ibcon#about to read 3, iclass 22, count 2 2006.201.02:43:45.07#ibcon#read 3, iclass 22, count 2 2006.201.02:43:45.07#ibcon#about to read 4, iclass 22, count 2 2006.201.02:43:45.07#ibcon#read 4, iclass 22, count 2 2006.201.02:43:45.07#ibcon#about to read 5, iclass 22, count 2 2006.201.02:43:45.07#ibcon#read 5, iclass 22, count 2 2006.201.02:43:45.07#ibcon#about to read 6, iclass 22, count 2 2006.201.02:43:45.07#ibcon#read 6, iclass 22, count 2 2006.201.02:43:45.07#ibcon#end of sib2, iclass 22, count 2 2006.201.02:43:45.07#ibcon#*after write, iclass 22, count 2 2006.201.02:43:45.07#ibcon#*before return 0, iclass 22, count 2 2006.201.02:43:45.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:45.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.02:43:45.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.02:43:45.07#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:45.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:45.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:45.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:45.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.02:43:45.19#ibcon#first serial, iclass 22, count 0 2006.201.02:43:45.19#ibcon#enter sib2, iclass 22, count 0 2006.201.02:43:45.19#ibcon#flushed, iclass 22, count 0 2006.201.02:43:45.19#ibcon#about to write, iclass 22, count 0 2006.201.02:43:45.19#ibcon#wrote, iclass 22, count 0 2006.201.02:43:45.19#ibcon#about to read 3, iclass 22, count 0 2006.201.02:43:45.21#ibcon#read 3, iclass 22, count 0 2006.201.02:43:45.21#ibcon#about to read 4, iclass 22, count 0 2006.201.02:43:45.21#ibcon#read 4, iclass 22, count 0 2006.201.02:43:45.21#ibcon#about to read 5, iclass 22, count 0 2006.201.02:43:45.21#ibcon#read 5, iclass 22, count 0 2006.201.02:43:45.21#ibcon#about to read 6, iclass 22, count 0 2006.201.02:43:45.21#ibcon#read 6, iclass 22, count 0 2006.201.02:43:45.21#ibcon#end of sib2, iclass 22, count 0 2006.201.02:43:45.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.02:43:45.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.02:43:45.21#ibcon#[27=USB\r\n] 2006.201.02:43:45.21#ibcon#*before write, iclass 22, count 0 2006.201.02:43:45.21#ibcon#enter sib2, iclass 22, count 0 2006.201.02:43:45.21#ibcon#flushed, iclass 22, count 0 2006.201.02:43:45.21#ibcon#about to write, iclass 22, count 0 2006.201.02:43:45.21#ibcon#wrote, iclass 22, count 0 2006.201.02:43:45.21#ibcon#about to read 3, iclass 22, count 0 2006.201.02:43:45.24#ibcon#read 3, iclass 22, count 0 2006.201.02:43:45.24#ibcon#about to read 4, iclass 22, count 0 2006.201.02:43:45.24#ibcon#read 4, iclass 22, count 0 2006.201.02:43:45.24#ibcon#about to read 5, iclass 22, count 0 2006.201.02:43:45.24#ibcon#read 5, iclass 22, count 0 2006.201.02:43:45.24#ibcon#about to read 6, iclass 22, count 0 2006.201.02:43:45.24#ibcon#read 6, iclass 22, count 0 2006.201.02:43:45.24#ibcon#end of sib2, iclass 22, count 0 2006.201.02:43:45.24#ibcon#*after write, iclass 22, count 0 2006.201.02:43:45.24#ibcon#*before return 0, iclass 22, count 0 2006.201.02:43:45.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:45.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.02:43:45.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.02:43:45.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.02:43:45.24$vck44/vblo=6,719.99 2006.201.02:43:45.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.02:43:45.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.02:43:45.24#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:45.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:45.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:45.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:45.24#ibcon#enter wrdev, iclass 24, count 0 2006.201.02:43:45.24#ibcon#first serial, iclass 24, count 0 2006.201.02:43:45.24#ibcon#enter sib2, iclass 24, count 0 2006.201.02:43:45.24#ibcon#flushed, iclass 24, count 0 2006.201.02:43:45.24#ibcon#about to write, iclass 24, count 0 2006.201.02:43:45.24#ibcon#wrote, iclass 24, count 0 2006.201.02:43:45.24#ibcon#about to read 3, iclass 24, count 0 2006.201.02:43:45.26#ibcon#read 3, iclass 24, count 0 2006.201.02:43:45.26#ibcon#about to read 4, iclass 24, count 0 2006.201.02:43:45.26#ibcon#read 4, iclass 24, count 0 2006.201.02:43:45.26#ibcon#about to read 5, iclass 24, count 0 2006.201.02:43:45.26#ibcon#read 5, iclass 24, count 0 2006.201.02:43:45.26#ibcon#about to read 6, iclass 24, count 0 2006.201.02:43:45.26#ibcon#read 6, iclass 24, count 0 2006.201.02:43:45.26#ibcon#end of sib2, iclass 24, count 0 2006.201.02:43:45.26#ibcon#*mode == 0, iclass 24, count 0 2006.201.02:43:45.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.02:43:45.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:43:45.26#ibcon#*before write, iclass 24, count 0 2006.201.02:43:45.26#ibcon#enter sib2, iclass 24, count 0 2006.201.02:43:45.26#ibcon#flushed, iclass 24, count 0 2006.201.02:43:45.26#ibcon#about to write, iclass 24, count 0 2006.201.02:43:45.26#ibcon#wrote, iclass 24, count 0 2006.201.02:43:45.26#ibcon#about to read 3, iclass 24, count 0 2006.201.02:43:45.30#ibcon#read 3, iclass 24, count 0 2006.201.02:43:45.30#ibcon#about to read 4, iclass 24, count 0 2006.201.02:43:45.30#ibcon#read 4, iclass 24, count 0 2006.201.02:43:45.30#ibcon#about to read 5, iclass 24, count 0 2006.201.02:43:45.30#ibcon#read 5, iclass 24, count 0 2006.201.02:43:45.30#ibcon#about to read 6, iclass 24, count 0 2006.201.02:43:45.30#ibcon#read 6, iclass 24, count 0 2006.201.02:43:45.30#ibcon#end of sib2, iclass 24, count 0 2006.201.02:43:45.30#ibcon#*after write, iclass 24, count 0 2006.201.02:43:45.30#ibcon#*before return 0, iclass 24, count 0 2006.201.02:43:45.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:45.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.02:43:45.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.02:43:45.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.02:43:45.30$vck44/vb=6,4 2006.201.02:43:45.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.02:43:45.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.02:43:45.30#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:45.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:45.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:45.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:45.36#ibcon#enter wrdev, iclass 26, count 2 2006.201.02:43:45.36#ibcon#first serial, iclass 26, count 2 2006.201.02:43:45.36#ibcon#enter sib2, iclass 26, count 2 2006.201.02:43:45.36#ibcon#flushed, iclass 26, count 2 2006.201.02:43:45.36#ibcon#about to write, iclass 26, count 2 2006.201.02:43:45.36#ibcon#wrote, iclass 26, count 2 2006.201.02:43:45.36#ibcon#about to read 3, iclass 26, count 2 2006.201.02:43:45.38#ibcon#read 3, iclass 26, count 2 2006.201.02:43:45.38#ibcon#about to read 4, iclass 26, count 2 2006.201.02:43:45.38#ibcon#read 4, iclass 26, count 2 2006.201.02:43:45.38#ibcon#about to read 5, iclass 26, count 2 2006.201.02:43:45.38#ibcon#read 5, iclass 26, count 2 2006.201.02:43:45.38#ibcon#about to read 6, iclass 26, count 2 2006.201.02:43:45.38#ibcon#read 6, iclass 26, count 2 2006.201.02:43:45.38#ibcon#end of sib2, iclass 26, count 2 2006.201.02:43:45.38#ibcon#*mode == 0, iclass 26, count 2 2006.201.02:43:45.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.02:43:45.38#ibcon#[27=AT06-04\r\n] 2006.201.02:43:45.38#ibcon#*before write, iclass 26, count 2 2006.201.02:43:45.38#ibcon#enter sib2, iclass 26, count 2 2006.201.02:43:45.38#ibcon#flushed, iclass 26, count 2 2006.201.02:43:45.38#ibcon#about to write, iclass 26, count 2 2006.201.02:43:45.38#ibcon#wrote, iclass 26, count 2 2006.201.02:43:45.38#ibcon#about to read 3, iclass 26, count 2 2006.201.02:43:45.41#ibcon#read 3, iclass 26, count 2 2006.201.02:43:45.41#ibcon#about to read 4, iclass 26, count 2 2006.201.02:43:45.41#ibcon#read 4, iclass 26, count 2 2006.201.02:43:45.41#ibcon#about to read 5, iclass 26, count 2 2006.201.02:43:45.41#ibcon#read 5, iclass 26, count 2 2006.201.02:43:45.41#ibcon#about to read 6, iclass 26, count 2 2006.201.02:43:45.41#ibcon#read 6, iclass 26, count 2 2006.201.02:43:45.41#ibcon#end of sib2, iclass 26, count 2 2006.201.02:43:45.41#ibcon#*after write, iclass 26, count 2 2006.201.02:43:45.41#ibcon#*before return 0, iclass 26, count 2 2006.201.02:43:45.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:45.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.02:43:45.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.02:43:45.41#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:45.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:45.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:45.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:45.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.02:43:45.53#ibcon#first serial, iclass 26, count 0 2006.201.02:43:45.53#ibcon#enter sib2, iclass 26, count 0 2006.201.02:43:45.53#ibcon#flushed, iclass 26, count 0 2006.201.02:43:45.53#ibcon#about to write, iclass 26, count 0 2006.201.02:43:45.53#ibcon#wrote, iclass 26, count 0 2006.201.02:43:45.53#ibcon#about to read 3, iclass 26, count 0 2006.201.02:43:45.55#ibcon#read 3, iclass 26, count 0 2006.201.02:43:45.55#ibcon#about to read 4, iclass 26, count 0 2006.201.02:43:45.55#ibcon#read 4, iclass 26, count 0 2006.201.02:43:45.55#ibcon#about to read 5, iclass 26, count 0 2006.201.02:43:45.55#ibcon#read 5, iclass 26, count 0 2006.201.02:43:45.55#ibcon#about to read 6, iclass 26, count 0 2006.201.02:43:45.55#ibcon#read 6, iclass 26, count 0 2006.201.02:43:45.55#ibcon#end of sib2, iclass 26, count 0 2006.201.02:43:45.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.02:43:45.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.02:43:45.55#ibcon#[27=USB\r\n] 2006.201.02:43:45.55#ibcon#*before write, iclass 26, count 0 2006.201.02:43:45.55#ibcon#enter sib2, iclass 26, count 0 2006.201.02:43:45.55#ibcon#flushed, iclass 26, count 0 2006.201.02:43:45.55#ibcon#about to write, iclass 26, count 0 2006.201.02:43:45.55#ibcon#wrote, iclass 26, count 0 2006.201.02:43:45.55#ibcon#about to read 3, iclass 26, count 0 2006.201.02:43:45.58#ibcon#read 3, iclass 26, count 0 2006.201.02:43:45.58#ibcon#about to read 4, iclass 26, count 0 2006.201.02:43:45.58#ibcon#read 4, iclass 26, count 0 2006.201.02:43:45.58#ibcon#about to read 5, iclass 26, count 0 2006.201.02:43:45.58#ibcon#read 5, iclass 26, count 0 2006.201.02:43:45.58#ibcon#about to read 6, iclass 26, count 0 2006.201.02:43:45.58#ibcon#read 6, iclass 26, count 0 2006.201.02:43:45.58#ibcon#end of sib2, iclass 26, count 0 2006.201.02:43:45.58#ibcon#*after write, iclass 26, count 0 2006.201.02:43:45.58#ibcon#*before return 0, iclass 26, count 0 2006.201.02:43:45.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:45.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.02:43:45.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.02:43:45.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.02:43:45.58$vck44/vblo=7,734.99 2006.201.02:43:45.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.02:43:45.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.02:43:45.58#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:45.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:45.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:45.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:45.58#ibcon#enter wrdev, iclass 28, count 0 2006.201.02:43:45.58#ibcon#first serial, iclass 28, count 0 2006.201.02:43:45.58#ibcon#enter sib2, iclass 28, count 0 2006.201.02:43:45.58#ibcon#flushed, iclass 28, count 0 2006.201.02:43:45.58#ibcon#about to write, iclass 28, count 0 2006.201.02:43:45.58#ibcon#wrote, iclass 28, count 0 2006.201.02:43:45.58#ibcon#about to read 3, iclass 28, count 0 2006.201.02:43:45.60#ibcon#read 3, iclass 28, count 0 2006.201.02:43:45.60#ibcon#about to read 4, iclass 28, count 0 2006.201.02:43:45.60#ibcon#read 4, iclass 28, count 0 2006.201.02:43:45.60#ibcon#about to read 5, iclass 28, count 0 2006.201.02:43:45.60#ibcon#read 5, iclass 28, count 0 2006.201.02:43:45.60#ibcon#about to read 6, iclass 28, count 0 2006.201.02:43:45.60#ibcon#read 6, iclass 28, count 0 2006.201.02:43:45.60#ibcon#end of sib2, iclass 28, count 0 2006.201.02:43:45.60#ibcon#*mode == 0, iclass 28, count 0 2006.201.02:43:45.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.02:43:45.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:43:45.60#ibcon#*before write, iclass 28, count 0 2006.201.02:43:45.60#ibcon#enter sib2, iclass 28, count 0 2006.201.02:43:45.60#ibcon#flushed, iclass 28, count 0 2006.201.02:43:45.60#ibcon#about to write, iclass 28, count 0 2006.201.02:43:45.60#ibcon#wrote, iclass 28, count 0 2006.201.02:43:45.60#ibcon#about to read 3, iclass 28, count 0 2006.201.02:43:45.64#ibcon#read 3, iclass 28, count 0 2006.201.02:43:45.64#ibcon#about to read 4, iclass 28, count 0 2006.201.02:43:45.64#ibcon#read 4, iclass 28, count 0 2006.201.02:43:45.64#ibcon#about to read 5, iclass 28, count 0 2006.201.02:43:45.64#ibcon#read 5, iclass 28, count 0 2006.201.02:43:45.64#ibcon#about to read 6, iclass 28, count 0 2006.201.02:43:45.64#ibcon#read 6, iclass 28, count 0 2006.201.02:43:45.64#ibcon#end of sib2, iclass 28, count 0 2006.201.02:43:45.64#ibcon#*after write, iclass 28, count 0 2006.201.02:43:45.64#ibcon#*before return 0, iclass 28, count 0 2006.201.02:43:45.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:45.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.02:43:45.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.02:43:45.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.02:43:45.64$vck44/vb=7,4 2006.201.02:43:45.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.02:43:45.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.02:43:45.64#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:45.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:45.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:45.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:45.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.02:43:45.70#ibcon#first serial, iclass 30, count 2 2006.201.02:43:45.70#ibcon#enter sib2, iclass 30, count 2 2006.201.02:43:45.70#ibcon#flushed, iclass 30, count 2 2006.201.02:43:45.70#ibcon#about to write, iclass 30, count 2 2006.201.02:43:45.70#ibcon#wrote, iclass 30, count 2 2006.201.02:43:45.70#ibcon#about to read 3, iclass 30, count 2 2006.201.02:43:45.72#ibcon#read 3, iclass 30, count 2 2006.201.02:43:45.72#ibcon#about to read 4, iclass 30, count 2 2006.201.02:43:45.72#ibcon#read 4, iclass 30, count 2 2006.201.02:43:45.72#ibcon#about to read 5, iclass 30, count 2 2006.201.02:43:45.72#ibcon#read 5, iclass 30, count 2 2006.201.02:43:45.72#ibcon#about to read 6, iclass 30, count 2 2006.201.02:43:45.72#ibcon#read 6, iclass 30, count 2 2006.201.02:43:45.72#ibcon#end of sib2, iclass 30, count 2 2006.201.02:43:45.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.02:43:45.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.02:43:45.72#ibcon#[27=AT07-04\r\n] 2006.201.02:43:45.72#ibcon#*before write, iclass 30, count 2 2006.201.02:43:45.72#ibcon#enter sib2, iclass 30, count 2 2006.201.02:43:45.72#ibcon#flushed, iclass 30, count 2 2006.201.02:43:45.72#ibcon#about to write, iclass 30, count 2 2006.201.02:43:45.72#ibcon#wrote, iclass 30, count 2 2006.201.02:43:45.72#ibcon#about to read 3, iclass 30, count 2 2006.201.02:43:45.75#ibcon#read 3, iclass 30, count 2 2006.201.02:43:45.75#ibcon#about to read 4, iclass 30, count 2 2006.201.02:43:45.75#ibcon#read 4, iclass 30, count 2 2006.201.02:43:45.75#ibcon#about to read 5, iclass 30, count 2 2006.201.02:43:45.75#ibcon#read 5, iclass 30, count 2 2006.201.02:43:45.75#ibcon#about to read 6, iclass 30, count 2 2006.201.02:43:45.75#ibcon#read 6, iclass 30, count 2 2006.201.02:43:45.75#ibcon#end of sib2, iclass 30, count 2 2006.201.02:43:45.75#ibcon#*after write, iclass 30, count 2 2006.201.02:43:45.75#ibcon#*before return 0, iclass 30, count 2 2006.201.02:43:45.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:45.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.02:43:45.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.02:43:45.75#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:45.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:45.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:45.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:45.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.02:43:45.87#ibcon#first serial, iclass 30, count 0 2006.201.02:43:45.87#ibcon#enter sib2, iclass 30, count 0 2006.201.02:43:45.87#ibcon#flushed, iclass 30, count 0 2006.201.02:43:45.87#ibcon#about to write, iclass 30, count 0 2006.201.02:43:45.87#ibcon#wrote, iclass 30, count 0 2006.201.02:43:45.87#ibcon#about to read 3, iclass 30, count 0 2006.201.02:43:45.89#ibcon#read 3, iclass 30, count 0 2006.201.02:43:45.89#ibcon#about to read 4, iclass 30, count 0 2006.201.02:43:45.89#ibcon#read 4, iclass 30, count 0 2006.201.02:43:45.89#ibcon#about to read 5, iclass 30, count 0 2006.201.02:43:45.89#ibcon#read 5, iclass 30, count 0 2006.201.02:43:45.89#ibcon#about to read 6, iclass 30, count 0 2006.201.02:43:45.89#ibcon#read 6, iclass 30, count 0 2006.201.02:43:45.89#ibcon#end of sib2, iclass 30, count 0 2006.201.02:43:45.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.02:43:45.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.02:43:45.89#ibcon#[27=USB\r\n] 2006.201.02:43:45.89#ibcon#*before write, iclass 30, count 0 2006.201.02:43:45.89#ibcon#enter sib2, iclass 30, count 0 2006.201.02:43:45.89#ibcon#flushed, iclass 30, count 0 2006.201.02:43:45.89#ibcon#about to write, iclass 30, count 0 2006.201.02:43:45.89#ibcon#wrote, iclass 30, count 0 2006.201.02:43:45.89#ibcon#about to read 3, iclass 30, count 0 2006.201.02:43:45.92#ibcon#read 3, iclass 30, count 0 2006.201.02:43:45.92#ibcon#about to read 4, iclass 30, count 0 2006.201.02:43:45.92#ibcon#read 4, iclass 30, count 0 2006.201.02:43:45.92#ibcon#about to read 5, iclass 30, count 0 2006.201.02:43:45.92#ibcon#read 5, iclass 30, count 0 2006.201.02:43:45.92#ibcon#about to read 6, iclass 30, count 0 2006.201.02:43:45.92#ibcon#read 6, iclass 30, count 0 2006.201.02:43:45.92#ibcon#end of sib2, iclass 30, count 0 2006.201.02:43:45.92#ibcon#*after write, iclass 30, count 0 2006.201.02:43:45.92#ibcon#*before return 0, iclass 30, count 0 2006.201.02:43:45.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:45.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.02:43:45.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.02:43:45.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.02:43:45.92$vck44/vblo=8,744.99 2006.201.02:43:45.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.02:43:45.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.02:43:45.92#ibcon#ireg 17 cls_cnt 0 2006.201.02:43:45.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:45.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:45.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:45.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.02:43:45.92#ibcon#first serial, iclass 32, count 0 2006.201.02:43:45.92#ibcon#enter sib2, iclass 32, count 0 2006.201.02:43:45.92#ibcon#flushed, iclass 32, count 0 2006.201.02:43:45.92#ibcon#about to write, iclass 32, count 0 2006.201.02:43:45.92#ibcon#wrote, iclass 32, count 0 2006.201.02:43:45.92#ibcon#about to read 3, iclass 32, count 0 2006.201.02:43:45.94#ibcon#read 3, iclass 32, count 0 2006.201.02:43:45.94#ibcon#about to read 4, iclass 32, count 0 2006.201.02:43:45.94#ibcon#read 4, iclass 32, count 0 2006.201.02:43:45.94#ibcon#about to read 5, iclass 32, count 0 2006.201.02:43:45.94#ibcon#read 5, iclass 32, count 0 2006.201.02:43:45.94#ibcon#about to read 6, iclass 32, count 0 2006.201.02:43:45.94#ibcon#read 6, iclass 32, count 0 2006.201.02:43:45.94#ibcon#end of sib2, iclass 32, count 0 2006.201.02:43:45.94#ibcon#*mode == 0, iclass 32, count 0 2006.201.02:43:45.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.02:43:45.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:43:45.94#ibcon#*before write, iclass 32, count 0 2006.201.02:43:45.94#ibcon#enter sib2, iclass 32, count 0 2006.201.02:43:45.94#ibcon#flushed, iclass 32, count 0 2006.201.02:43:45.94#ibcon#about to write, iclass 32, count 0 2006.201.02:43:45.94#ibcon#wrote, iclass 32, count 0 2006.201.02:43:45.94#ibcon#about to read 3, iclass 32, count 0 2006.201.02:43:45.99#ibcon#read 3, iclass 32, count 0 2006.201.02:43:45.99#ibcon#about to read 4, iclass 32, count 0 2006.201.02:43:45.99#ibcon#read 4, iclass 32, count 0 2006.201.02:43:45.99#ibcon#about to read 5, iclass 32, count 0 2006.201.02:43:45.99#ibcon#read 5, iclass 32, count 0 2006.201.02:43:45.99#ibcon#about to read 6, iclass 32, count 0 2006.201.02:43:45.99#ibcon#read 6, iclass 32, count 0 2006.201.02:43:45.99#ibcon#end of sib2, iclass 32, count 0 2006.201.02:43:45.99#ibcon#*after write, iclass 32, count 0 2006.201.02:43:45.99#ibcon#*before return 0, iclass 32, count 0 2006.201.02:43:45.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:45.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.02:43:45.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.02:43:45.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.02:43:45.99$vck44/vb=8,4 2006.201.02:43:45.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.02:43:45.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.02:43:45.99#ibcon#ireg 11 cls_cnt 2 2006.201.02:43:45.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:46.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:46.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:46.04#ibcon#enter wrdev, iclass 34, count 2 2006.201.02:43:46.04#ibcon#first serial, iclass 34, count 2 2006.201.02:43:46.04#ibcon#enter sib2, iclass 34, count 2 2006.201.02:43:46.04#ibcon#flushed, iclass 34, count 2 2006.201.02:43:46.04#ibcon#about to write, iclass 34, count 2 2006.201.02:43:46.04#ibcon#wrote, iclass 34, count 2 2006.201.02:43:46.04#ibcon#about to read 3, iclass 34, count 2 2006.201.02:43:46.06#ibcon#read 3, iclass 34, count 2 2006.201.02:43:46.06#ibcon#about to read 4, iclass 34, count 2 2006.201.02:43:46.06#ibcon#read 4, iclass 34, count 2 2006.201.02:43:46.06#ibcon#about to read 5, iclass 34, count 2 2006.201.02:43:46.06#ibcon#read 5, iclass 34, count 2 2006.201.02:43:46.06#ibcon#about to read 6, iclass 34, count 2 2006.201.02:43:46.06#ibcon#read 6, iclass 34, count 2 2006.201.02:43:46.06#ibcon#end of sib2, iclass 34, count 2 2006.201.02:43:46.06#ibcon#*mode == 0, iclass 34, count 2 2006.201.02:43:46.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.02:43:46.06#ibcon#[27=AT08-04\r\n] 2006.201.02:43:46.06#ibcon#*before write, iclass 34, count 2 2006.201.02:43:46.06#ibcon#enter sib2, iclass 34, count 2 2006.201.02:43:46.06#ibcon#flushed, iclass 34, count 2 2006.201.02:43:46.06#ibcon#about to write, iclass 34, count 2 2006.201.02:43:46.06#ibcon#wrote, iclass 34, count 2 2006.201.02:43:46.06#ibcon#about to read 3, iclass 34, count 2 2006.201.02:43:46.09#ibcon#read 3, iclass 34, count 2 2006.201.02:43:46.09#ibcon#about to read 4, iclass 34, count 2 2006.201.02:43:46.09#ibcon#read 4, iclass 34, count 2 2006.201.02:43:46.09#ibcon#about to read 5, iclass 34, count 2 2006.201.02:43:46.09#ibcon#read 5, iclass 34, count 2 2006.201.02:43:46.09#ibcon#about to read 6, iclass 34, count 2 2006.201.02:43:46.09#ibcon#read 6, iclass 34, count 2 2006.201.02:43:46.09#ibcon#end of sib2, iclass 34, count 2 2006.201.02:43:46.09#ibcon#*after write, iclass 34, count 2 2006.201.02:43:46.09#ibcon#*before return 0, iclass 34, count 2 2006.201.02:43:46.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:46.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.02:43:46.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.02:43:46.09#ibcon#ireg 7 cls_cnt 0 2006.201.02:43:46.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:46.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:46.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:46.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.02:43:46.21#ibcon#first serial, iclass 34, count 0 2006.201.02:43:46.21#ibcon#enter sib2, iclass 34, count 0 2006.201.02:43:46.21#ibcon#flushed, iclass 34, count 0 2006.201.02:43:46.21#ibcon#about to write, iclass 34, count 0 2006.201.02:43:46.21#ibcon#wrote, iclass 34, count 0 2006.201.02:43:46.21#ibcon#about to read 3, iclass 34, count 0 2006.201.02:43:46.23#ibcon#read 3, iclass 34, count 0 2006.201.02:43:46.23#ibcon#about to read 4, iclass 34, count 0 2006.201.02:43:46.23#ibcon#read 4, iclass 34, count 0 2006.201.02:43:46.23#ibcon#about to read 5, iclass 34, count 0 2006.201.02:43:46.23#ibcon#read 5, iclass 34, count 0 2006.201.02:43:46.23#ibcon#about to read 6, iclass 34, count 0 2006.201.02:43:46.23#ibcon#read 6, iclass 34, count 0 2006.201.02:43:46.23#ibcon#end of sib2, iclass 34, count 0 2006.201.02:43:46.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.02:43:46.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.02:43:46.23#ibcon#[27=USB\r\n] 2006.201.02:43:46.23#ibcon#*before write, iclass 34, count 0 2006.201.02:43:46.23#ibcon#enter sib2, iclass 34, count 0 2006.201.02:43:46.23#ibcon#flushed, iclass 34, count 0 2006.201.02:43:46.23#ibcon#about to write, iclass 34, count 0 2006.201.02:43:46.23#ibcon#wrote, iclass 34, count 0 2006.201.02:43:46.23#ibcon#about to read 3, iclass 34, count 0 2006.201.02:43:46.26#ibcon#read 3, iclass 34, count 0 2006.201.02:43:46.26#ibcon#about to read 4, iclass 34, count 0 2006.201.02:43:46.26#ibcon#read 4, iclass 34, count 0 2006.201.02:43:46.26#ibcon#about to read 5, iclass 34, count 0 2006.201.02:43:46.26#ibcon#read 5, iclass 34, count 0 2006.201.02:43:46.26#ibcon#about to read 6, iclass 34, count 0 2006.201.02:43:46.26#ibcon#read 6, iclass 34, count 0 2006.201.02:43:46.26#ibcon#end of sib2, iclass 34, count 0 2006.201.02:43:46.26#ibcon#*after write, iclass 34, count 0 2006.201.02:43:46.26#ibcon#*before return 0, iclass 34, count 0 2006.201.02:43:46.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:46.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.02:43:46.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.02:43:46.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.02:43:46.26$vck44/vabw=wide 2006.201.02:43:46.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.02:43:46.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.02:43:46.26#ibcon#ireg 8 cls_cnt 0 2006.201.02:43:46.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:46.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:46.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:46.26#ibcon#enter wrdev, iclass 36, count 0 2006.201.02:43:46.26#ibcon#first serial, iclass 36, count 0 2006.201.02:43:46.26#ibcon#enter sib2, iclass 36, count 0 2006.201.02:43:46.26#ibcon#flushed, iclass 36, count 0 2006.201.02:43:46.26#ibcon#about to write, iclass 36, count 0 2006.201.02:43:46.26#ibcon#wrote, iclass 36, count 0 2006.201.02:43:46.26#ibcon#about to read 3, iclass 36, count 0 2006.201.02:43:46.28#ibcon#read 3, iclass 36, count 0 2006.201.02:43:46.28#ibcon#about to read 4, iclass 36, count 0 2006.201.02:43:46.28#ibcon#read 4, iclass 36, count 0 2006.201.02:43:46.28#ibcon#about to read 5, iclass 36, count 0 2006.201.02:43:46.28#ibcon#read 5, iclass 36, count 0 2006.201.02:43:46.28#ibcon#about to read 6, iclass 36, count 0 2006.201.02:43:46.28#ibcon#read 6, iclass 36, count 0 2006.201.02:43:46.28#ibcon#end of sib2, iclass 36, count 0 2006.201.02:43:46.28#ibcon#*mode == 0, iclass 36, count 0 2006.201.02:43:46.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.02:43:46.28#ibcon#[25=BW32\r\n] 2006.201.02:43:46.28#ibcon#*before write, iclass 36, count 0 2006.201.02:43:46.28#ibcon#enter sib2, iclass 36, count 0 2006.201.02:43:46.28#ibcon#flushed, iclass 36, count 0 2006.201.02:43:46.28#ibcon#about to write, iclass 36, count 0 2006.201.02:43:46.28#ibcon#wrote, iclass 36, count 0 2006.201.02:43:46.28#ibcon#about to read 3, iclass 36, count 0 2006.201.02:43:46.31#ibcon#read 3, iclass 36, count 0 2006.201.02:43:46.31#ibcon#about to read 4, iclass 36, count 0 2006.201.02:43:46.31#ibcon#read 4, iclass 36, count 0 2006.201.02:43:46.31#ibcon#about to read 5, iclass 36, count 0 2006.201.02:43:46.31#ibcon#read 5, iclass 36, count 0 2006.201.02:43:46.31#ibcon#about to read 6, iclass 36, count 0 2006.201.02:43:46.31#ibcon#read 6, iclass 36, count 0 2006.201.02:43:46.31#ibcon#end of sib2, iclass 36, count 0 2006.201.02:43:46.31#ibcon#*after write, iclass 36, count 0 2006.201.02:43:46.31#ibcon#*before return 0, iclass 36, count 0 2006.201.02:43:46.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:46.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.02:43:46.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.02:43:46.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.02:43:46.31$vck44/vbbw=wide 2006.201.02:43:46.31#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.02:43:46.31#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.02:43:46.31#ibcon#ireg 8 cls_cnt 0 2006.201.02:43:46.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:43:46.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:43:46.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:43:46.38#ibcon#enter wrdev, iclass 38, count 0 2006.201.02:43:46.38#ibcon#first serial, iclass 38, count 0 2006.201.02:43:46.38#ibcon#enter sib2, iclass 38, count 0 2006.201.02:43:46.38#ibcon#flushed, iclass 38, count 0 2006.201.02:43:46.38#ibcon#about to write, iclass 38, count 0 2006.201.02:43:46.38#ibcon#wrote, iclass 38, count 0 2006.201.02:43:46.38#ibcon#about to read 3, iclass 38, count 0 2006.201.02:43:46.40#ibcon#read 3, iclass 38, count 0 2006.201.02:43:46.40#ibcon#about to read 4, iclass 38, count 0 2006.201.02:43:46.40#ibcon#read 4, iclass 38, count 0 2006.201.02:43:46.40#ibcon#about to read 5, iclass 38, count 0 2006.201.02:43:46.40#ibcon#read 5, iclass 38, count 0 2006.201.02:43:46.40#ibcon#about to read 6, iclass 38, count 0 2006.201.02:43:46.40#ibcon#read 6, iclass 38, count 0 2006.201.02:43:46.40#ibcon#end of sib2, iclass 38, count 0 2006.201.02:43:46.40#ibcon#*mode == 0, iclass 38, count 0 2006.201.02:43:46.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.02:43:46.40#ibcon#[27=BW32\r\n] 2006.201.02:43:46.40#ibcon#*before write, iclass 38, count 0 2006.201.02:43:46.40#ibcon#enter sib2, iclass 38, count 0 2006.201.02:43:46.40#ibcon#flushed, iclass 38, count 0 2006.201.02:43:46.40#ibcon#about to write, iclass 38, count 0 2006.201.02:43:46.40#ibcon#wrote, iclass 38, count 0 2006.201.02:43:46.40#ibcon#about to read 3, iclass 38, count 0 2006.201.02:43:46.43#ibcon#read 3, iclass 38, count 0 2006.201.02:43:46.43#ibcon#about to read 4, iclass 38, count 0 2006.201.02:43:46.43#ibcon#read 4, iclass 38, count 0 2006.201.02:43:46.43#ibcon#about to read 5, iclass 38, count 0 2006.201.02:43:46.43#ibcon#read 5, iclass 38, count 0 2006.201.02:43:46.43#ibcon#about to read 6, iclass 38, count 0 2006.201.02:43:46.43#ibcon#read 6, iclass 38, count 0 2006.201.02:43:46.43#ibcon#end of sib2, iclass 38, count 0 2006.201.02:43:46.43#ibcon#*after write, iclass 38, count 0 2006.201.02:43:46.43#ibcon#*before return 0, iclass 38, count 0 2006.201.02:43:46.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:43:46.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.02:43:46.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.02:43:46.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.02:43:46.43$setupk4/ifdk4 2006.201.02:43:46.43$ifdk4/lo= 2006.201.02:43:46.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:43:46.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:43:46.43$ifdk4/patch= 2006.201.02:43:46.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:43:46.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:43:46.43$setupk4/!*+20s 2006.201.02:43:48.45#abcon#<5=/04 2.5 4.9 22.91 911004.6\r\n> 2006.201.02:43:48.47#abcon#{5=INTERFACE CLEAR} 2006.201.02:43:48.53#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:43:53.14#trakl#Source acquired 2006.201.02:43:55.14#flagr#flagr/antenna,acquired 2006.201.02:43:58.62#abcon#<5=/04 2.5 5.0 22.91 911004.6\r\n> 2006.201.02:43:58.64#abcon#{5=INTERFACE CLEAR} 2006.201.02:43:58.72#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:44:00.92$setupk4/"tpicd 2006.201.02:44:00.92$setupk4/echo=off 2006.201.02:44:00.92$setupk4/xlog=off 2006.201.02:44:00.92:!2006.201.02:46:45 2006.201.02:46:45.00:preob 2006.201.02:46:45.14/onsource/TRACKING 2006.201.02:46:45.14:!2006.201.02:46:55 2006.201.02:46:55.00:"tape 2006.201.02:46:55.00:"st=record 2006.201.02:46:55.00:data_valid=on 2006.201.02:46:55.00:midob 2006.201.02:46:55.14/onsource/TRACKING 2006.201.02:46:55.14/wx/22.90,1004.5,92 2006.201.02:46:55.22/cable/+6.4683E-03 2006.201.02:46:56.31/va/01,08,usb,yes,29,31 2006.201.02:46:56.31/va/02,07,usb,yes,32,32 2006.201.02:46:56.31/va/03,08,usb,yes,28,30 2006.201.02:46:56.31/va/04,07,usb,yes,32,34 2006.201.02:46:56.31/va/05,04,usb,yes,29,29 2006.201.02:46:56.31/va/06,05,usb,yes,29,29 2006.201.02:46:56.31/va/07,05,usb,yes,28,29 2006.201.02:46:56.31/va/08,04,usb,yes,28,33 2006.201.02:46:56.54/valo/01,524.99,yes,locked 2006.201.02:46:56.54/valo/02,534.99,yes,locked 2006.201.02:46:56.54/valo/03,564.99,yes,locked 2006.201.02:46:56.54/valo/04,624.99,yes,locked 2006.201.02:46:56.54/valo/05,734.99,yes,locked 2006.201.02:46:56.54/valo/06,814.99,yes,locked 2006.201.02:46:56.54/valo/07,864.99,yes,locked 2006.201.02:46:56.54/valo/08,884.99,yes,locked 2006.201.02:46:57.63/vb/01,04,usb,yes,29,27 2006.201.02:46:57.63/vb/02,05,usb,yes,28,28 2006.201.02:46:57.63/vb/03,04,usb,yes,29,32 2006.201.02:46:57.63/vb/04,05,usb,yes,29,28 2006.201.02:46:57.63/vb/05,04,usb,yes,25,28 2006.201.02:46:57.63/vb/06,04,usb,yes,30,26 2006.201.02:46:57.63/vb/07,04,usb,yes,30,30 2006.201.02:46:57.63/vb/08,04,usb,yes,27,31 2006.201.02:46:57.86/vblo/01,629.99,yes,locked 2006.201.02:46:57.86/vblo/02,634.99,yes,locked 2006.201.02:46:57.86/vblo/03,649.99,yes,locked 2006.201.02:46:57.86/vblo/04,679.99,yes,locked 2006.201.02:46:57.86/vblo/05,709.99,yes,locked 2006.201.02:46:57.86/vblo/06,719.99,yes,locked 2006.201.02:46:57.86/vblo/07,734.99,yes,locked 2006.201.02:46:57.86/vblo/08,744.99,yes,locked 2006.201.02:46:58.01/vabw/8 2006.201.02:46:58.16/vbbw/8 2006.201.02:46:58.25/xfe/off,on,15.0 2006.201.02:46:58.64/ifatt/23,28,28,28 2006.201.02:46:59.04/fmout-gps/S +4.47E-07 2006.201.02:46:59.11:!2006.201.02:55:35 2006.201.02:55:35.00:data_valid=off 2006.201.02:55:35.00:"et 2006.201.02:55:35.00:!+3s 2006.201.02:55:38.02:"tape 2006.201.02:55:38.02:postob 2006.201.02:55:38.15/cable/+6.4648E-03 2006.201.02:55:38.15/wx/22.86,1004.5,95 2006.201.02:55:38.22/fmout-gps/S +4.50E-07 2006.201.02:55:38.22:scan_name=201-0300,jd0607,230 2006.201.02:55:38.23:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.201.02:55:40.14#flagr#flagr/antenna,new-source 2006.201.02:55:40.14:checkk5 2006.201.02:55:40.57/chk_autoobs//k5ts1/ autoobs is running! 2006.201.02:55:41.00/chk_autoobs//k5ts2/ autoobs is running! 2006.201.02:55:41.45/chk_autoobs//k5ts3/ autoobs is running! 2006.201.02:55:41.85/chk_autoobs//k5ts4/ autoobs is running! 2006.201.02:55:42.57/chk_obsdata//k5ts1/T2010246??a.dat file size is correct (nominal:2080MB, actual:2080MB). 2006.201.02:55:43.34/chk_obsdata//k5ts2/T2010246??b.dat file size is correct (nominal:2080MB, actual:2080MB). 2006.201.02:55:44.79/chk_obsdata//k5ts3/T2010246??c.dat file size is correct (nominal:2080MB, actual:2080MB). 2006.201.02:55:45.76/chk_obsdata//k5ts4/T2010246??d.dat file size is correct (nominal:2080MB, actual:2080MB). 2006.201.02:55:46.66/k5log//k5ts1_log_newline 2006.201.02:55:47.66/k5log//k5ts2_log_newline 2006.201.02:55:48.41/k5log//k5ts3_log_newline 2006.201.02:55:49.21/k5log//k5ts4_log_newline 2006.201.02:55:49.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.02:55:49.23:setupk4=1 2006.201.02:55:49.23$setupk4/echo=on 2006.201.02:55:49.24$setupk4/pcalon 2006.201.02:55:49.24$pcalon/"no phase cal control is implemented here 2006.201.02:55:49.24$setupk4/"tpicd=stop 2006.201.02:55:49.24$setupk4/"rec=synch_on 2006.201.02:55:49.24$setupk4/"rec_mode=128 2006.201.02:55:49.24$setupk4/!* 2006.201.02:55:49.24$setupk4/recpk4 2006.201.02:55:49.24$recpk4/recpatch= 2006.201.02:55:49.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.02:55:49.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.02:55:49.24$setupk4/vck44 2006.201.02:55:49.24$vck44/valo=1,524.99 2006.201.02:55:49.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.02:55:49.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.02:55:49.24#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:49.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:49.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:49.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:49.24#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:55:49.24#ibcon#first serial, iclass 39, count 0 2006.201.02:55:49.24#ibcon#enter sib2, iclass 39, count 0 2006.201.02:55:49.24#ibcon#flushed, iclass 39, count 0 2006.201.02:55:49.24#ibcon#about to write, iclass 39, count 0 2006.201.02:55:49.24#ibcon#wrote, iclass 39, count 0 2006.201.02:55:49.24#ibcon#about to read 3, iclass 39, count 0 2006.201.02:55:49.28#ibcon#read 3, iclass 39, count 0 2006.201.02:55:49.28#ibcon#about to read 4, iclass 39, count 0 2006.201.02:55:49.28#ibcon#read 4, iclass 39, count 0 2006.201.02:55:49.28#ibcon#about to read 5, iclass 39, count 0 2006.201.02:55:49.28#ibcon#read 5, iclass 39, count 0 2006.201.02:55:49.28#ibcon#about to read 6, iclass 39, count 0 2006.201.02:55:49.28#ibcon#read 6, iclass 39, count 0 2006.201.02:55:49.28#ibcon#end of sib2, iclass 39, count 0 2006.201.02:55:49.28#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:55:49.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:55:49.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.02:55:49.28#ibcon#*before write, iclass 39, count 0 2006.201.02:55:49.28#ibcon#enter sib2, iclass 39, count 0 2006.201.02:55:49.28#ibcon#flushed, iclass 39, count 0 2006.201.02:55:49.28#ibcon#about to write, iclass 39, count 0 2006.201.02:55:49.28#ibcon#wrote, iclass 39, count 0 2006.201.02:55:49.28#ibcon#about to read 3, iclass 39, count 0 2006.201.02:55:49.33#ibcon#read 3, iclass 39, count 0 2006.201.02:55:49.33#ibcon#about to read 4, iclass 39, count 0 2006.201.02:55:49.33#ibcon#read 4, iclass 39, count 0 2006.201.02:55:49.33#ibcon#about to read 5, iclass 39, count 0 2006.201.02:55:49.33#ibcon#read 5, iclass 39, count 0 2006.201.02:55:49.33#ibcon#about to read 6, iclass 39, count 0 2006.201.02:55:49.33#ibcon#read 6, iclass 39, count 0 2006.201.02:55:49.33#ibcon#end of sib2, iclass 39, count 0 2006.201.02:55:49.33#ibcon#*after write, iclass 39, count 0 2006.201.02:55:49.33#ibcon#*before return 0, iclass 39, count 0 2006.201.02:55:49.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:49.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:49.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:55:49.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:55:49.33$vck44/va=1,8 2006.201.02:55:49.33#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.02:55:49.33#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.02:55:49.33#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:49.33#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:49.33#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:49.33#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:49.33#ibcon#enter wrdev, iclass 2, count 2 2006.201.02:55:49.33#ibcon#first serial, iclass 2, count 2 2006.201.02:55:49.33#ibcon#enter sib2, iclass 2, count 2 2006.201.02:55:49.33#ibcon#flushed, iclass 2, count 2 2006.201.02:55:49.33#ibcon#about to write, iclass 2, count 2 2006.201.02:55:49.33#ibcon#wrote, iclass 2, count 2 2006.201.02:55:49.33#ibcon#about to read 3, iclass 2, count 2 2006.201.02:55:49.35#ibcon#read 3, iclass 2, count 2 2006.201.02:55:49.35#ibcon#about to read 4, iclass 2, count 2 2006.201.02:55:49.35#ibcon#read 4, iclass 2, count 2 2006.201.02:55:49.35#ibcon#about to read 5, iclass 2, count 2 2006.201.02:55:49.35#ibcon#read 5, iclass 2, count 2 2006.201.02:55:49.35#ibcon#about to read 6, iclass 2, count 2 2006.201.02:55:49.35#ibcon#read 6, iclass 2, count 2 2006.201.02:55:49.35#ibcon#end of sib2, iclass 2, count 2 2006.201.02:55:49.35#ibcon#*mode == 0, iclass 2, count 2 2006.201.02:55:49.35#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.02:55:49.35#ibcon#[25=AT01-08\r\n] 2006.201.02:55:49.35#ibcon#*before write, iclass 2, count 2 2006.201.02:55:49.35#ibcon#enter sib2, iclass 2, count 2 2006.201.02:55:49.35#ibcon#flushed, iclass 2, count 2 2006.201.02:55:49.35#ibcon#about to write, iclass 2, count 2 2006.201.02:55:49.35#ibcon#wrote, iclass 2, count 2 2006.201.02:55:49.35#ibcon#about to read 3, iclass 2, count 2 2006.201.02:55:49.39#ibcon#read 3, iclass 2, count 2 2006.201.02:55:49.39#ibcon#about to read 4, iclass 2, count 2 2006.201.02:55:49.39#ibcon#read 4, iclass 2, count 2 2006.201.02:55:49.39#ibcon#about to read 5, iclass 2, count 2 2006.201.02:55:49.39#ibcon#read 5, iclass 2, count 2 2006.201.02:55:49.39#ibcon#about to read 6, iclass 2, count 2 2006.201.02:55:49.39#ibcon#read 6, iclass 2, count 2 2006.201.02:55:49.39#ibcon#end of sib2, iclass 2, count 2 2006.201.02:55:49.39#ibcon#*after write, iclass 2, count 2 2006.201.02:55:49.39#ibcon#*before return 0, iclass 2, count 2 2006.201.02:55:49.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:49.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:49.39#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.02:55:49.39#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:49.39#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:49.51#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:49.51#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:49.51#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:55:49.51#ibcon#first serial, iclass 2, count 0 2006.201.02:55:49.51#ibcon#enter sib2, iclass 2, count 0 2006.201.02:55:49.51#ibcon#flushed, iclass 2, count 0 2006.201.02:55:49.51#ibcon#about to write, iclass 2, count 0 2006.201.02:55:49.51#ibcon#wrote, iclass 2, count 0 2006.201.02:55:49.51#ibcon#about to read 3, iclass 2, count 0 2006.201.02:55:49.53#ibcon#read 3, iclass 2, count 0 2006.201.02:55:49.53#ibcon#about to read 4, iclass 2, count 0 2006.201.02:55:49.53#ibcon#read 4, iclass 2, count 0 2006.201.02:55:49.53#ibcon#about to read 5, iclass 2, count 0 2006.201.02:55:49.53#ibcon#read 5, iclass 2, count 0 2006.201.02:55:49.53#ibcon#about to read 6, iclass 2, count 0 2006.201.02:55:49.53#ibcon#read 6, iclass 2, count 0 2006.201.02:55:49.53#ibcon#end of sib2, iclass 2, count 0 2006.201.02:55:49.53#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:55:49.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:55:49.53#ibcon#[25=USB\r\n] 2006.201.02:55:49.53#ibcon#*before write, iclass 2, count 0 2006.201.02:55:49.53#ibcon#enter sib2, iclass 2, count 0 2006.201.02:55:49.53#ibcon#flushed, iclass 2, count 0 2006.201.02:55:49.53#ibcon#about to write, iclass 2, count 0 2006.201.02:55:49.53#ibcon#wrote, iclass 2, count 0 2006.201.02:55:49.53#ibcon#about to read 3, iclass 2, count 0 2006.201.02:55:49.56#ibcon#read 3, iclass 2, count 0 2006.201.02:55:49.56#ibcon#about to read 4, iclass 2, count 0 2006.201.02:55:49.56#ibcon#read 4, iclass 2, count 0 2006.201.02:55:49.56#ibcon#about to read 5, iclass 2, count 0 2006.201.02:55:49.56#ibcon#read 5, iclass 2, count 0 2006.201.02:55:49.56#ibcon#about to read 6, iclass 2, count 0 2006.201.02:55:49.56#ibcon#read 6, iclass 2, count 0 2006.201.02:55:49.56#ibcon#end of sib2, iclass 2, count 0 2006.201.02:55:49.56#ibcon#*after write, iclass 2, count 0 2006.201.02:55:49.56#ibcon#*before return 0, iclass 2, count 0 2006.201.02:55:49.56#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:49.56#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:49.56#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:55:49.56#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:55:49.56$vck44/valo=2,534.99 2006.201.02:55:49.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.02:55:49.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.02:55:49.56#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:49.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:49.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:49.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:49.56#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:55:49.56#ibcon#first serial, iclass 5, count 0 2006.201.02:55:49.56#ibcon#enter sib2, iclass 5, count 0 2006.201.02:55:49.56#ibcon#flushed, iclass 5, count 0 2006.201.02:55:49.56#ibcon#about to write, iclass 5, count 0 2006.201.02:55:49.56#ibcon#wrote, iclass 5, count 0 2006.201.02:55:49.56#ibcon#about to read 3, iclass 5, count 0 2006.201.02:55:49.58#ibcon#read 3, iclass 5, count 0 2006.201.02:55:49.58#ibcon#about to read 4, iclass 5, count 0 2006.201.02:55:49.58#ibcon#read 4, iclass 5, count 0 2006.201.02:55:49.58#ibcon#about to read 5, iclass 5, count 0 2006.201.02:55:49.58#ibcon#read 5, iclass 5, count 0 2006.201.02:55:49.58#ibcon#about to read 6, iclass 5, count 0 2006.201.02:55:49.58#ibcon#read 6, iclass 5, count 0 2006.201.02:55:49.58#ibcon#end of sib2, iclass 5, count 0 2006.201.02:55:49.58#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:55:49.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:55:49.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.02:55:49.58#ibcon#*before write, iclass 5, count 0 2006.201.02:55:49.58#ibcon#enter sib2, iclass 5, count 0 2006.201.02:55:49.58#ibcon#flushed, iclass 5, count 0 2006.201.02:55:49.58#ibcon#about to write, iclass 5, count 0 2006.201.02:55:49.58#ibcon#wrote, iclass 5, count 0 2006.201.02:55:49.58#ibcon#about to read 3, iclass 5, count 0 2006.201.02:55:49.63#ibcon#read 3, iclass 5, count 0 2006.201.02:55:49.63#ibcon#about to read 4, iclass 5, count 0 2006.201.02:55:49.63#ibcon#read 4, iclass 5, count 0 2006.201.02:55:49.63#ibcon#about to read 5, iclass 5, count 0 2006.201.02:55:49.63#ibcon#read 5, iclass 5, count 0 2006.201.02:55:49.63#ibcon#about to read 6, iclass 5, count 0 2006.201.02:55:49.63#ibcon#read 6, iclass 5, count 0 2006.201.02:55:49.63#ibcon#end of sib2, iclass 5, count 0 2006.201.02:55:49.63#ibcon#*after write, iclass 5, count 0 2006.201.02:55:49.63#ibcon#*before return 0, iclass 5, count 0 2006.201.02:55:49.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:49.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:49.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:55:49.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:55:49.63$vck44/va=2,7 2006.201.02:55:49.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.02:55:49.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.02:55:49.63#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:49.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:49.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:49.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:49.68#ibcon#enter wrdev, iclass 7, count 2 2006.201.02:55:49.68#ibcon#first serial, iclass 7, count 2 2006.201.02:55:49.68#ibcon#enter sib2, iclass 7, count 2 2006.201.02:55:49.68#ibcon#flushed, iclass 7, count 2 2006.201.02:55:49.68#ibcon#about to write, iclass 7, count 2 2006.201.02:55:49.68#ibcon#wrote, iclass 7, count 2 2006.201.02:55:49.68#ibcon#about to read 3, iclass 7, count 2 2006.201.02:55:49.70#ibcon#read 3, iclass 7, count 2 2006.201.02:55:49.70#ibcon#about to read 4, iclass 7, count 2 2006.201.02:55:49.70#ibcon#read 4, iclass 7, count 2 2006.201.02:55:49.70#ibcon#about to read 5, iclass 7, count 2 2006.201.02:55:49.70#ibcon#read 5, iclass 7, count 2 2006.201.02:55:49.70#ibcon#about to read 6, iclass 7, count 2 2006.201.02:55:49.70#ibcon#read 6, iclass 7, count 2 2006.201.02:55:49.70#ibcon#end of sib2, iclass 7, count 2 2006.201.02:55:49.70#ibcon#*mode == 0, iclass 7, count 2 2006.201.02:55:49.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.02:55:49.70#ibcon#[25=AT02-07\r\n] 2006.201.02:55:49.70#ibcon#*before write, iclass 7, count 2 2006.201.02:55:49.70#ibcon#enter sib2, iclass 7, count 2 2006.201.02:55:49.70#ibcon#flushed, iclass 7, count 2 2006.201.02:55:49.70#ibcon#about to write, iclass 7, count 2 2006.201.02:55:49.70#ibcon#wrote, iclass 7, count 2 2006.201.02:55:49.70#ibcon#about to read 3, iclass 7, count 2 2006.201.02:55:49.73#ibcon#read 3, iclass 7, count 2 2006.201.02:55:49.73#ibcon#about to read 4, iclass 7, count 2 2006.201.02:55:49.73#ibcon#read 4, iclass 7, count 2 2006.201.02:55:49.73#ibcon#about to read 5, iclass 7, count 2 2006.201.02:55:49.73#ibcon#read 5, iclass 7, count 2 2006.201.02:55:49.73#ibcon#about to read 6, iclass 7, count 2 2006.201.02:55:49.73#ibcon#read 6, iclass 7, count 2 2006.201.02:55:49.73#ibcon#end of sib2, iclass 7, count 2 2006.201.02:55:49.73#ibcon#*after write, iclass 7, count 2 2006.201.02:55:49.73#ibcon#*before return 0, iclass 7, count 2 2006.201.02:55:49.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:49.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:49.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.02:55:49.73#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:49.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:49.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:49.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:49.85#ibcon#enter wrdev, iclass 7, count 0 2006.201.02:55:49.85#ibcon#first serial, iclass 7, count 0 2006.201.02:55:49.85#ibcon#enter sib2, iclass 7, count 0 2006.201.02:55:49.85#ibcon#flushed, iclass 7, count 0 2006.201.02:55:49.85#ibcon#about to write, iclass 7, count 0 2006.201.02:55:49.85#ibcon#wrote, iclass 7, count 0 2006.201.02:55:49.85#ibcon#about to read 3, iclass 7, count 0 2006.201.02:55:49.87#ibcon#read 3, iclass 7, count 0 2006.201.02:55:49.87#ibcon#about to read 4, iclass 7, count 0 2006.201.02:55:49.87#ibcon#read 4, iclass 7, count 0 2006.201.02:55:49.87#ibcon#about to read 5, iclass 7, count 0 2006.201.02:55:49.87#ibcon#read 5, iclass 7, count 0 2006.201.02:55:49.87#ibcon#about to read 6, iclass 7, count 0 2006.201.02:55:49.87#ibcon#read 6, iclass 7, count 0 2006.201.02:55:49.87#ibcon#end of sib2, iclass 7, count 0 2006.201.02:55:49.87#ibcon#*mode == 0, iclass 7, count 0 2006.201.02:55:49.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.02:55:49.87#ibcon#[25=USB\r\n] 2006.201.02:55:49.87#ibcon#*before write, iclass 7, count 0 2006.201.02:55:49.87#ibcon#enter sib2, iclass 7, count 0 2006.201.02:55:49.87#ibcon#flushed, iclass 7, count 0 2006.201.02:55:49.87#ibcon#about to write, iclass 7, count 0 2006.201.02:55:49.87#ibcon#wrote, iclass 7, count 0 2006.201.02:55:49.87#ibcon#about to read 3, iclass 7, count 0 2006.201.02:55:49.90#ibcon#read 3, iclass 7, count 0 2006.201.02:55:49.90#ibcon#about to read 4, iclass 7, count 0 2006.201.02:55:49.90#ibcon#read 4, iclass 7, count 0 2006.201.02:55:49.90#ibcon#about to read 5, iclass 7, count 0 2006.201.02:55:49.90#ibcon#read 5, iclass 7, count 0 2006.201.02:55:49.90#ibcon#about to read 6, iclass 7, count 0 2006.201.02:55:49.90#ibcon#read 6, iclass 7, count 0 2006.201.02:55:49.90#ibcon#end of sib2, iclass 7, count 0 2006.201.02:55:49.90#ibcon#*after write, iclass 7, count 0 2006.201.02:55:49.90#ibcon#*before return 0, iclass 7, count 0 2006.201.02:55:49.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:49.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:49.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.02:55:49.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.02:55:49.90$vck44/valo=3,564.99 2006.201.02:55:49.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.02:55:49.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.02:55:49.90#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:49.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:49.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:49.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:49.90#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:55:49.90#ibcon#first serial, iclass 11, count 0 2006.201.02:55:49.90#ibcon#enter sib2, iclass 11, count 0 2006.201.02:55:49.90#ibcon#flushed, iclass 11, count 0 2006.201.02:55:49.90#ibcon#about to write, iclass 11, count 0 2006.201.02:55:49.90#ibcon#wrote, iclass 11, count 0 2006.201.02:55:49.90#ibcon#about to read 3, iclass 11, count 0 2006.201.02:55:49.92#ibcon#read 3, iclass 11, count 0 2006.201.02:55:49.92#ibcon#about to read 4, iclass 11, count 0 2006.201.02:55:49.92#ibcon#read 4, iclass 11, count 0 2006.201.02:55:49.92#ibcon#about to read 5, iclass 11, count 0 2006.201.02:55:49.92#ibcon#read 5, iclass 11, count 0 2006.201.02:55:49.92#ibcon#about to read 6, iclass 11, count 0 2006.201.02:55:49.92#ibcon#read 6, iclass 11, count 0 2006.201.02:55:49.92#ibcon#end of sib2, iclass 11, count 0 2006.201.02:55:49.92#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:55:49.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:55:49.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.02:55:49.92#ibcon#*before write, iclass 11, count 0 2006.201.02:55:49.92#ibcon#enter sib2, iclass 11, count 0 2006.201.02:55:49.92#ibcon#flushed, iclass 11, count 0 2006.201.02:55:49.92#ibcon#about to write, iclass 11, count 0 2006.201.02:55:49.92#ibcon#wrote, iclass 11, count 0 2006.201.02:55:49.92#ibcon#about to read 3, iclass 11, count 0 2006.201.02:55:49.96#ibcon#read 3, iclass 11, count 0 2006.201.02:55:49.96#ibcon#about to read 4, iclass 11, count 0 2006.201.02:55:49.96#ibcon#read 4, iclass 11, count 0 2006.201.02:55:49.96#ibcon#about to read 5, iclass 11, count 0 2006.201.02:55:49.96#ibcon#read 5, iclass 11, count 0 2006.201.02:55:49.96#ibcon#about to read 6, iclass 11, count 0 2006.201.02:55:49.96#ibcon#read 6, iclass 11, count 0 2006.201.02:55:49.96#ibcon#end of sib2, iclass 11, count 0 2006.201.02:55:49.96#ibcon#*after write, iclass 11, count 0 2006.201.02:55:49.96#ibcon#*before return 0, iclass 11, count 0 2006.201.02:55:49.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:49.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:49.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:55:49.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:55:49.96$vck44/va=3,8 2006.201.02:55:49.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.02:55:49.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.02:55:49.96#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:49.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:50.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:50.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:50.02#ibcon#enter wrdev, iclass 13, count 2 2006.201.02:55:50.02#ibcon#first serial, iclass 13, count 2 2006.201.02:55:50.02#ibcon#enter sib2, iclass 13, count 2 2006.201.02:55:50.02#ibcon#flushed, iclass 13, count 2 2006.201.02:55:50.02#ibcon#about to write, iclass 13, count 2 2006.201.02:55:50.02#ibcon#wrote, iclass 13, count 2 2006.201.02:55:50.02#ibcon#about to read 3, iclass 13, count 2 2006.201.02:55:50.04#ibcon#read 3, iclass 13, count 2 2006.201.02:55:50.04#ibcon#about to read 4, iclass 13, count 2 2006.201.02:55:50.04#ibcon#read 4, iclass 13, count 2 2006.201.02:55:50.04#ibcon#about to read 5, iclass 13, count 2 2006.201.02:55:50.04#ibcon#read 5, iclass 13, count 2 2006.201.02:55:50.04#ibcon#about to read 6, iclass 13, count 2 2006.201.02:55:50.04#ibcon#read 6, iclass 13, count 2 2006.201.02:55:50.04#ibcon#end of sib2, iclass 13, count 2 2006.201.02:55:50.04#ibcon#*mode == 0, iclass 13, count 2 2006.201.02:55:50.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.02:55:50.04#ibcon#[25=AT03-08\r\n] 2006.201.02:55:50.04#ibcon#*before write, iclass 13, count 2 2006.201.02:55:50.04#ibcon#enter sib2, iclass 13, count 2 2006.201.02:55:50.04#ibcon#flushed, iclass 13, count 2 2006.201.02:55:50.04#ibcon#about to write, iclass 13, count 2 2006.201.02:55:50.04#ibcon#wrote, iclass 13, count 2 2006.201.02:55:50.04#ibcon#about to read 3, iclass 13, count 2 2006.201.02:55:50.07#ibcon#read 3, iclass 13, count 2 2006.201.02:55:50.07#ibcon#about to read 4, iclass 13, count 2 2006.201.02:55:50.07#ibcon#read 4, iclass 13, count 2 2006.201.02:55:50.07#ibcon#about to read 5, iclass 13, count 2 2006.201.02:55:50.07#ibcon#read 5, iclass 13, count 2 2006.201.02:55:50.07#ibcon#about to read 6, iclass 13, count 2 2006.201.02:55:50.07#ibcon#read 6, iclass 13, count 2 2006.201.02:55:50.07#ibcon#end of sib2, iclass 13, count 2 2006.201.02:55:50.07#ibcon#*after write, iclass 13, count 2 2006.201.02:55:50.07#ibcon#*before return 0, iclass 13, count 2 2006.201.02:55:50.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:50.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:50.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.02:55:50.07#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:50.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:50.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:50.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:50.19#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:55:50.19#ibcon#first serial, iclass 13, count 0 2006.201.02:55:50.19#ibcon#enter sib2, iclass 13, count 0 2006.201.02:55:50.19#ibcon#flushed, iclass 13, count 0 2006.201.02:55:50.19#ibcon#about to write, iclass 13, count 0 2006.201.02:55:50.19#ibcon#wrote, iclass 13, count 0 2006.201.02:55:50.19#ibcon#about to read 3, iclass 13, count 0 2006.201.02:55:50.22#ibcon#read 3, iclass 13, count 0 2006.201.02:55:50.22#ibcon#about to read 4, iclass 13, count 0 2006.201.02:55:50.22#ibcon#read 4, iclass 13, count 0 2006.201.02:55:50.22#ibcon#about to read 5, iclass 13, count 0 2006.201.02:55:50.22#ibcon#read 5, iclass 13, count 0 2006.201.02:55:50.22#ibcon#about to read 6, iclass 13, count 0 2006.201.02:55:50.22#ibcon#read 6, iclass 13, count 0 2006.201.02:55:50.22#ibcon#end of sib2, iclass 13, count 0 2006.201.02:55:50.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:55:50.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:55:50.22#ibcon#[25=USB\r\n] 2006.201.02:55:50.22#ibcon#*before write, iclass 13, count 0 2006.201.02:55:50.22#ibcon#enter sib2, iclass 13, count 0 2006.201.02:55:50.22#ibcon#flushed, iclass 13, count 0 2006.201.02:55:50.22#ibcon#about to write, iclass 13, count 0 2006.201.02:55:50.22#ibcon#wrote, iclass 13, count 0 2006.201.02:55:50.22#ibcon#about to read 3, iclass 13, count 0 2006.201.02:55:50.25#ibcon#read 3, iclass 13, count 0 2006.201.02:55:50.25#ibcon#about to read 4, iclass 13, count 0 2006.201.02:55:50.25#ibcon#read 4, iclass 13, count 0 2006.201.02:55:50.25#ibcon#about to read 5, iclass 13, count 0 2006.201.02:55:50.25#ibcon#read 5, iclass 13, count 0 2006.201.02:55:50.25#ibcon#about to read 6, iclass 13, count 0 2006.201.02:55:50.25#ibcon#read 6, iclass 13, count 0 2006.201.02:55:50.25#ibcon#end of sib2, iclass 13, count 0 2006.201.02:55:50.25#ibcon#*after write, iclass 13, count 0 2006.201.02:55:50.25#ibcon#*before return 0, iclass 13, count 0 2006.201.02:55:50.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:50.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:50.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:55:50.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:55:50.25$vck44/valo=4,624.99 2006.201.02:55:50.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.02:55:50.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.02:55:50.25#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:50.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:50.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:50.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:50.25#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:55:50.25#ibcon#first serial, iclass 15, count 0 2006.201.02:55:50.25#ibcon#enter sib2, iclass 15, count 0 2006.201.02:55:50.25#ibcon#flushed, iclass 15, count 0 2006.201.02:55:50.25#ibcon#about to write, iclass 15, count 0 2006.201.02:55:50.25#ibcon#wrote, iclass 15, count 0 2006.201.02:55:50.25#ibcon#about to read 3, iclass 15, count 0 2006.201.02:55:50.27#ibcon#read 3, iclass 15, count 0 2006.201.02:55:50.27#ibcon#about to read 4, iclass 15, count 0 2006.201.02:55:50.27#ibcon#read 4, iclass 15, count 0 2006.201.02:55:50.27#ibcon#about to read 5, iclass 15, count 0 2006.201.02:55:50.27#ibcon#read 5, iclass 15, count 0 2006.201.02:55:50.27#ibcon#about to read 6, iclass 15, count 0 2006.201.02:55:50.27#ibcon#read 6, iclass 15, count 0 2006.201.02:55:50.27#ibcon#end of sib2, iclass 15, count 0 2006.201.02:55:50.27#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:55:50.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:55:50.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.02:55:50.27#ibcon#*before write, iclass 15, count 0 2006.201.02:55:50.27#ibcon#enter sib2, iclass 15, count 0 2006.201.02:55:50.27#ibcon#flushed, iclass 15, count 0 2006.201.02:55:50.27#ibcon#about to write, iclass 15, count 0 2006.201.02:55:50.27#ibcon#wrote, iclass 15, count 0 2006.201.02:55:50.27#ibcon#about to read 3, iclass 15, count 0 2006.201.02:55:50.31#ibcon#read 3, iclass 15, count 0 2006.201.02:55:50.31#ibcon#about to read 4, iclass 15, count 0 2006.201.02:55:50.31#ibcon#read 4, iclass 15, count 0 2006.201.02:55:50.31#ibcon#about to read 5, iclass 15, count 0 2006.201.02:55:50.31#ibcon#read 5, iclass 15, count 0 2006.201.02:55:50.31#ibcon#about to read 6, iclass 15, count 0 2006.201.02:55:50.31#ibcon#read 6, iclass 15, count 0 2006.201.02:55:50.31#ibcon#end of sib2, iclass 15, count 0 2006.201.02:55:50.31#ibcon#*after write, iclass 15, count 0 2006.201.02:55:50.31#ibcon#*before return 0, iclass 15, count 0 2006.201.02:55:50.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:50.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:50.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:55:50.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:55:50.31$vck44/va=4,7 2006.201.02:55:50.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.02:55:50.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.02:55:50.31#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:50.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:50.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:50.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:50.37#ibcon#enter wrdev, iclass 17, count 2 2006.201.02:55:50.37#ibcon#first serial, iclass 17, count 2 2006.201.02:55:50.37#ibcon#enter sib2, iclass 17, count 2 2006.201.02:55:50.37#ibcon#flushed, iclass 17, count 2 2006.201.02:55:50.37#ibcon#about to write, iclass 17, count 2 2006.201.02:55:50.37#ibcon#wrote, iclass 17, count 2 2006.201.02:55:50.37#ibcon#about to read 3, iclass 17, count 2 2006.201.02:55:50.39#ibcon#read 3, iclass 17, count 2 2006.201.02:55:50.39#ibcon#about to read 4, iclass 17, count 2 2006.201.02:55:50.39#ibcon#read 4, iclass 17, count 2 2006.201.02:55:50.39#ibcon#about to read 5, iclass 17, count 2 2006.201.02:55:50.39#ibcon#read 5, iclass 17, count 2 2006.201.02:55:50.39#ibcon#about to read 6, iclass 17, count 2 2006.201.02:55:50.39#ibcon#read 6, iclass 17, count 2 2006.201.02:55:50.39#ibcon#end of sib2, iclass 17, count 2 2006.201.02:55:50.39#ibcon#*mode == 0, iclass 17, count 2 2006.201.02:55:50.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.02:55:50.39#ibcon#[25=AT04-07\r\n] 2006.201.02:55:50.39#ibcon#*before write, iclass 17, count 2 2006.201.02:55:50.39#ibcon#enter sib2, iclass 17, count 2 2006.201.02:55:50.39#ibcon#flushed, iclass 17, count 2 2006.201.02:55:50.39#ibcon#about to write, iclass 17, count 2 2006.201.02:55:50.39#ibcon#wrote, iclass 17, count 2 2006.201.02:55:50.39#ibcon#about to read 3, iclass 17, count 2 2006.201.02:55:50.42#ibcon#read 3, iclass 17, count 2 2006.201.02:55:50.42#ibcon#about to read 4, iclass 17, count 2 2006.201.02:55:50.42#ibcon#read 4, iclass 17, count 2 2006.201.02:55:50.42#ibcon#about to read 5, iclass 17, count 2 2006.201.02:55:50.42#ibcon#read 5, iclass 17, count 2 2006.201.02:55:50.42#ibcon#about to read 6, iclass 17, count 2 2006.201.02:55:50.42#ibcon#read 6, iclass 17, count 2 2006.201.02:55:50.42#ibcon#end of sib2, iclass 17, count 2 2006.201.02:55:50.42#ibcon#*after write, iclass 17, count 2 2006.201.02:55:50.42#ibcon#*before return 0, iclass 17, count 2 2006.201.02:55:50.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:50.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:50.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.02:55:50.42#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:50.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:50.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:50.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:50.54#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:55:50.54#ibcon#first serial, iclass 17, count 0 2006.201.02:55:50.54#ibcon#enter sib2, iclass 17, count 0 2006.201.02:55:50.54#ibcon#flushed, iclass 17, count 0 2006.201.02:55:50.54#ibcon#about to write, iclass 17, count 0 2006.201.02:55:50.54#ibcon#wrote, iclass 17, count 0 2006.201.02:55:50.54#ibcon#about to read 3, iclass 17, count 0 2006.201.02:55:50.56#ibcon#read 3, iclass 17, count 0 2006.201.02:55:50.56#ibcon#about to read 4, iclass 17, count 0 2006.201.02:55:50.56#ibcon#read 4, iclass 17, count 0 2006.201.02:55:50.56#ibcon#about to read 5, iclass 17, count 0 2006.201.02:55:50.56#ibcon#read 5, iclass 17, count 0 2006.201.02:55:50.56#ibcon#about to read 6, iclass 17, count 0 2006.201.02:55:50.56#ibcon#read 6, iclass 17, count 0 2006.201.02:55:50.56#ibcon#end of sib2, iclass 17, count 0 2006.201.02:55:50.56#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:55:50.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:55:50.56#ibcon#[25=USB\r\n] 2006.201.02:55:50.56#ibcon#*before write, iclass 17, count 0 2006.201.02:55:50.56#ibcon#enter sib2, iclass 17, count 0 2006.201.02:55:50.56#ibcon#flushed, iclass 17, count 0 2006.201.02:55:50.56#ibcon#about to write, iclass 17, count 0 2006.201.02:55:50.56#ibcon#wrote, iclass 17, count 0 2006.201.02:55:50.56#ibcon#about to read 3, iclass 17, count 0 2006.201.02:55:50.59#ibcon#read 3, iclass 17, count 0 2006.201.02:55:50.59#ibcon#about to read 4, iclass 17, count 0 2006.201.02:55:50.59#ibcon#read 4, iclass 17, count 0 2006.201.02:55:50.59#ibcon#about to read 5, iclass 17, count 0 2006.201.02:55:50.59#ibcon#read 5, iclass 17, count 0 2006.201.02:55:50.59#ibcon#about to read 6, iclass 17, count 0 2006.201.02:55:50.59#ibcon#read 6, iclass 17, count 0 2006.201.02:55:50.59#ibcon#end of sib2, iclass 17, count 0 2006.201.02:55:50.59#ibcon#*after write, iclass 17, count 0 2006.201.02:55:50.59#ibcon#*before return 0, iclass 17, count 0 2006.201.02:55:50.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:50.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:50.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:55:50.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:55:50.59$vck44/valo=5,734.99 2006.201.02:55:50.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.02:55:50.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.02:55:50.59#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:50.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:50.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:50.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:50.59#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:55:50.59#ibcon#first serial, iclass 19, count 0 2006.201.02:55:50.59#ibcon#enter sib2, iclass 19, count 0 2006.201.02:55:50.59#ibcon#flushed, iclass 19, count 0 2006.201.02:55:50.59#ibcon#about to write, iclass 19, count 0 2006.201.02:55:50.59#ibcon#wrote, iclass 19, count 0 2006.201.02:55:50.59#ibcon#about to read 3, iclass 19, count 0 2006.201.02:55:50.61#ibcon#read 3, iclass 19, count 0 2006.201.02:55:50.61#ibcon#about to read 4, iclass 19, count 0 2006.201.02:55:50.61#ibcon#read 4, iclass 19, count 0 2006.201.02:55:50.61#ibcon#about to read 5, iclass 19, count 0 2006.201.02:55:50.61#ibcon#read 5, iclass 19, count 0 2006.201.02:55:50.61#ibcon#about to read 6, iclass 19, count 0 2006.201.02:55:50.61#ibcon#read 6, iclass 19, count 0 2006.201.02:55:50.61#ibcon#end of sib2, iclass 19, count 0 2006.201.02:55:50.61#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:55:50.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:55:50.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.02:55:50.61#ibcon#*before write, iclass 19, count 0 2006.201.02:55:50.61#ibcon#enter sib2, iclass 19, count 0 2006.201.02:55:50.61#ibcon#flushed, iclass 19, count 0 2006.201.02:55:50.61#ibcon#about to write, iclass 19, count 0 2006.201.02:55:50.61#ibcon#wrote, iclass 19, count 0 2006.201.02:55:50.61#ibcon#about to read 3, iclass 19, count 0 2006.201.02:55:50.65#ibcon#read 3, iclass 19, count 0 2006.201.02:55:50.65#ibcon#about to read 4, iclass 19, count 0 2006.201.02:55:50.65#ibcon#read 4, iclass 19, count 0 2006.201.02:55:50.65#ibcon#about to read 5, iclass 19, count 0 2006.201.02:55:50.65#ibcon#read 5, iclass 19, count 0 2006.201.02:55:50.65#ibcon#about to read 6, iclass 19, count 0 2006.201.02:55:50.65#ibcon#read 6, iclass 19, count 0 2006.201.02:55:50.65#ibcon#end of sib2, iclass 19, count 0 2006.201.02:55:50.65#ibcon#*after write, iclass 19, count 0 2006.201.02:55:50.65#ibcon#*before return 0, iclass 19, count 0 2006.201.02:55:50.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:50.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:50.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:55:50.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:55:50.65$vck44/va=5,4 2006.201.02:55:50.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.02:55:50.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.02:55:50.65#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:50.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:50.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:50.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:50.71#ibcon#enter wrdev, iclass 21, count 2 2006.201.02:55:50.71#ibcon#first serial, iclass 21, count 2 2006.201.02:55:50.71#ibcon#enter sib2, iclass 21, count 2 2006.201.02:55:50.71#ibcon#flushed, iclass 21, count 2 2006.201.02:55:50.71#ibcon#about to write, iclass 21, count 2 2006.201.02:55:50.71#ibcon#wrote, iclass 21, count 2 2006.201.02:55:50.71#ibcon#about to read 3, iclass 21, count 2 2006.201.02:55:50.73#ibcon#read 3, iclass 21, count 2 2006.201.02:55:50.73#ibcon#about to read 4, iclass 21, count 2 2006.201.02:55:50.73#ibcon#read 4, iclass 21, count 2 2006.201.02:55:50.73#ibcon#about to read 5, iclass 21, count 2 2006.201.02:55:50.73#ibcon#read 5, iclass 21, count 2 2006.201.02:55:50.73#ibcon#about to read 6, iclass 21, count 2 2006.201.02:55:50.73#ibcon#read 6, iclass 21, count 2 2006.201.02:55:50.73#ibcon#end of sib2, iclass 21, count 2 2006.201.02:55:50.73#ibcon#*mode == 0, iclass 21, count 2 2006.201.02:55:50.73#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.02:55:50.73#ibcon#[25=AT05-04\r\n] 2006.201.02:55:50.73#ibcon#*before write, iclass 21, count 2 2006.201.02:55:50.73#ibcon#enter sib2, iclass 21, count 2 2006.201.02:55:50.73#ibcon#flushed, iclass 21, count 2 2006.201.02:55:50.73#ibcon#about to write, iclass 21, count 2 2006.201.02:55:50.73#ibcon#wrote, iclass 21, count 2 2006.201.02:55:50.73#ibcon#about to read 3, iclass 21, count 2 2006.201.02:55:50.76#abcon#<5=/03 1.8 3.8 22.86 951004.5\r\n> 2006.201.02:55:50.76#ibcon#read 3, iclass 21, count 2 2006.201.02:55:50.76#ibcon#about to read 4, iclass 21, count 2 2006.201.02:55:50.76#ibcon#read 4, iclass 21, count 2 2006.201.02:55:50.76#ibcon#about to read 5, iclass 21, count 2 2006.201.02:55:50.76#ibcon#read 5, iclass 21, count 2 2006.201.02:55:50.76#ibcon#about to read 6, iclass 21, count 2 2006.201.02:55:50.76#ibcon#read 6, iclass 21, count 2 2006.201.02:55:50.76#ibcon#end of sib2, iclass 21, count 2 2006.201.02:55:50.76#ibcon#*after write, iclass 21, count 2 2006.201.02:55:50.76#ibcon#*before return 0, iclass 21, count 2 2006.201.02:55:50.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:50.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:50.76#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.02:55:50.76#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:50.76#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:50.78#abcon#{5=INTERFACE CLEAR} 2006.201.02:55:50.84#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:55:50.88#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:50.88#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:50.88#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:55:50.88#ibcon#first serial, iclass 21, count 0 2006.201.02:55:50.88#ibcon#enter sib2, iclass 21, count 0 2006.201.02:55:50.88#ibcon#flushed, iclass 21, count 0 2006.201.02:55:50.88#ibcon#about to write, iclass 21, count 0 2006.201.02:55:50.88#ibcon#wrote, iclass 21, count 0 2006.201.02:55:50.88#ibcon#about to read 3, iclass 21, count 0 2006.201.02:55:50.91#ibcon#read 3, iclass 21, count 0 2006.201.02:55:50.91#ibcon#about to read 4, iclass 21, count 0 2006.201.02:55:50.91#ibcon#read 4, iclass 21, count 0 2006.201.02:55:50.91#ibcon#about to read 5, iclass 21, count 0 2006.201.02:55:50.91#ibcon#read 5, iclass 21, count 0 2006.201.02:55:50.91#ibcon#about to read 6, iclass 21, count 0 2006.201.02:55:50.91#ibcon#read 6, iclass 21, count 0 2006.201.02:55:50.91#ibcon#end of sib2, iclass 21, count 0 2006.201.02:55:50.91#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:55:50.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:55:50.91#ibcon#[25=USB\r\n] 2006.201.02:55:50.91#ibcon#*before write, iclass 21, count 0 2006.201.02:55:50.91#ibcon#enter sib2, iclass 21, count 0 2006.201.02:55:50.91#ibcon#flushed, iclass 21, count 0 2006.201.02:55:50.91#ibcon#about to write, iclass 21, count 0 2006.201.02:55:50.91#ibcon#wrote, iclass 21, count 0 2006.201.02:55:50.91#ibcon#about to read 3, iclass 21, count 0 2006.201.02:55:50.94#ibcon#read 3, iclass 21, count 0 2006.201.02:55:50.94#ibcon#about to read 4, iclass 21, count 0 2006.201.02:55:50.94#ibcon#read 4, iclass 21, count 0 2006.201.02:55:50.94#ibcon#about to read 5, iclass 21, count 0 2006.201.02:55:50.94#ibcon#read 5, iclass 21, count 0 2006.201.02:55:50.94#ibcon#about to read 6, iclass 21, count 0 2006.201.02:55:50.94#ibcon#read 6, iclass 21, count 0 2006.201.02:55:50.94#ibcon#end of sib2, iclass 21, count 0 2006.201.02:55:50.94#ibcon#*after write, iclass 21, count 0 2006.201.02:55:50.94#ibcon#*before return 0, iclass 21, count 0 2006.201.02:55:50.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:50.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:50.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:55:50.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:55:50.94$vck44/valo=6,814.99 2006.201.02:55:50.94#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.02:55:50.94#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.02:55:50.94#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:50.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:50.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:50.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:50.94#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:55:50.94#ibcon#first serial, iclass 27, count 0 2006.201.02:55:50.94#ibcon#enter sib2, iclass 27, count 0 2006.201.02:55:50.94#ibcon#flushed, iclass 27, count 0 2006.201.02:55:50.94#ibcon#about to write, iclass 27, count 0 2006.201.02:55:50.94#ibcon#wrote, iclass 27, count 0 2006.201.02:55:50.94#ibcon#about to read 3, iclass 27, count 0 2006.201.02:55:50.96#ibcon#read 3, iclass 27, count 0 2006.201.02:55:50.96#ibcon#about to read 4, iclass 27, count 0 2006.201.02:55:50.96#ibcon#read 4, iclass 27, count 0 2006.201.02:55:50.96#ibcon#about to read 5, iclass 27, count 0 2006.201.02:55:50.96#ibcon#read 5, iclass 27, count 0 2006.201.02:55:50.96#ibcon#about to read 6, iclass 27, count 0 2006.201.02:55:50.96#ibcon#read 6, iclass 27, count 0 2006.201.02:55:50.96#ibcon#end of sib2, iclass 27, count 0 2006.201.02:55:50.96#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:55:50.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:55:50.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.02:55:50.96#ibcon#*before write, iclass 27, count 0 2006.201.02:55:50.96#ibcon#enter sib2, iclass 27, count 0 2006.201.02:55:50.96#ibcon#flushed, iclass 27, count 0 2006.201.02:55:50.96#ibcon#about to write, iclass 27, count 0 2006.201.02:55:50.96#ibcon#wrote, iclass 27, count 0 2006.201.02:55:50.96#ibcon#about to read 3, iclass 27, count 0 2006.201.02:55:51.00#ibcon#read 3, iclass 27, count 0 2006.201.02:55:51.00#ibcon#about to read 4, iclass 27, count 0 2006.201.02:55:51.00#ibcon#read 4, iclass 27, count 0 2006.201.02:55:51.00#ibcon#about to read 5, iclass 27, count 0 2006.201.02:55:51.00#ibcon#read 5, iclass 27, count 0 2006.201.02:55:51.00#ibcon#about to read 6, iclass 27, count 0 2006.201.02:55:51.00#ibcon#read 6, iclass 27, count 0 2006.201.02:55:51.00#ibcon#end of sib2, iclass 27, count 0 2006.201.02:55:51.00#ibcon#*after write, iclass 27, count 0 2006.201.02:55:51.00#ibcon#*before return 0, iclass 27, count 0 2006.201.02:55:51.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:51.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:51.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:55:51.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:55:51.00$vck44/va=6,5 2006.201.02:55:51.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.02:55:51.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.02:55:51.00#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:51.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:51.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:51.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:51.06#ibcon#enter wrdev, iclass 29, count 2 2006.201.02:55:51.06#ibcon#first serial, iclass 29, count 2 2006.201.02:55:51.06#ibcon#enter sib2, iclass 29, count 2 2006.201.02:55:51.06#ibcon#flushed, iclass 29, count 2 2006.201.02:55:51.06#ibcon#about to write, iclass 29, count 2 2006.201.02:55:51.06#ibcon#wrote, iclass 29, count 2 2006.201.02:55:51.06#ibcon#about to read 3, iclass 29, count 2 2006.201.02:55:51.08#ibcon#read 3, iclass 29, count 2 2006.201.02:55:51.08#ibcon#about to read 4, iclass 29, count 2 2006.201.02:55:51.08#ibcon#read 4, iclass 29, count 2 2006.201.02:55:51.08#ibcon#about to read 5, iclass 29, count 2 2006.201.02:55:51.08#ibcon#read 5, iclass 29, count 2 2006.201.02:55:51.08#ibcon#about to read 6, iclass 29, count 2 2006.201.02:55:51.08#ibcon#read 6, iclass 29, count 2 2006.201.02:55:51.08#ibcon#end of sib2, iclass 29, count 2 2006.201.02:55:51.08#ibcon#*mode == 0, iclass 29, count 2 2006.201.02:55:51.08#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.02:55:51.08#ibcon#[25=AT06-05\r\n] 2006.201.02:55:51.08#ibcon#*before write, iclass 29, count 2 2006.201.02:55:51.08#ibcon#enter sib2, iclass 29, count 2 2006.201.02:55:51.08#ibcon#flushed, iclass 29, count 2 2006.201.02:55:51.08#ibcon#about to write, iclass 29, count 2 2006.201.02:55:51.08#ibcon#wrote, iclass 29, count 2 2006.201.02:55:51.08#ibcon#about to read 3, iclass 29, count 2 2006.201.02:55:51.11#ibcon#read 3, iclass 29, count 2 2006.201.02:55:51.11#ibcon#about to read 4, iclass 29, count 2 2006.201.02:55:51.11#ibcon#read 4, iclass 29, count 2 2006.201.02:55:51.11#ibcon#about to read 5, iclass 29, count 2 2006.201.02:55:51.11#ibcon#read 5, iclass 29, count 2 2006.201.02:55:51.11#ibcon#about to read 6, iclass 29, count 2 2006.201.02:55:51.11#ibcon#read 6, iclass 29, count 2 2006.201.02:55:51.11#ibcon#end of sib2, iclass 29, count 2 2006.201.02:55:51.11#ibcon#*after write, iclass 29, count 2 2006.201.02:55:51.11#ibcon#*before return 0, iclass 29, count 2 2006.201.02:55:51.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:51.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:51.11#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.02:55:51.11#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:51.11#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:51.23#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:51.23#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:51.23#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:55:51.23#ibcon#first serial, iclass 29, count 0 2006.201.02:55:51.23#ibcon#enter sib2, iclass 29, count 0 2006.201.02:55:51.23#ibcon#flushed, iclass 29, count 0 2006.201.02:55:51.23#ibcon#about to write, iclass 29, count 0 2006.201.02:55:51.23#ibcon#wrote, iclass 29, count 0 2006.201.02:55:51.23#ibcon#about to read 3, iclass 29, count 0 2006.201.02:55:51.25#ibcon#read 3, iclass 29, count 0 2006.201.02:55:51.25#ibcon#about to read 4, iclass 29, count 0 2006.201.02:55:51.25#ibcon#read 4, iclass 29, count 0 2006.201.02:55:51.25#ibcon#about to read 5, iclass 29, count 0 2006.201.02:55:51.25#ibcon#read 5, iclass 29, count 0 2006.201.02:55:51.25#ibcon#about to read 6, iclass 29, count 0 2006.201.02:55:51.25#ibcon#read 6, iclass 29, count 0 2006.201.02:55:51.25#ibcon#end of sib2, iclass 29, count 0 2006.201.02:55:51.25#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:55:51.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:55:51.25#ibcon#[25=USB\r\n] 2006.201.02:55:51.25#ibcon#*before write, iclass 29, count 0 2006.201.02:55:51.25#ibcon#enter sib2, iclass 29, count 0 2006.201.02:55:51.25#ibcon#flushed, iclass 29, count 0 2006.201.02:55:51.25#ibcon#about to write, iclass 29, count 0 2006.201.02:55:51.25#ibcon#wrote, iclass 29, count 0 2006.201.02:55:51.25#ibcon#about to read 3, iclass 29, count 0 2006.201.02:55:51.28#ibcon#read 3, iclass 29, count 0 2006.201.02:55:51.28#ibcon#about to read 4, iclass 29, count 0 2006.201.02:55:51.28#ibcon#read 4, iclass 29, count 0 2006.201.02:55:51.28#ibcon#about to read 5, iclass 29, count 0 2006.201.02:55:51.28#ibcon#read 5, iclass 29, count 0 2006.201.02:55:51.28#ibcon#about to read 6, iclass 29, count 0 2006.201.02:55:51.28#ibcon#read 6, iclass 29, count 0 2006.201.02:55:51.28#ibcon#end of sib2, iclass 29, count 0 2006.201.02:55:51.28#ibcon#*after write, iclass 29, count 0 2006.201.02:55:51.28#ibcon#*before return 0, iclass 29, count 0 2006.201.02:55:51.28#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:51.28#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:51.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:55:51.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:55:51.28$vck44/valo=7,864.99 2006.201.02:55:51.28#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.02:55:51.28#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.02:55:51.28#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:51.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:51.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:51.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:51.28#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:55:51.28#ibcon#first serial, iclass 31, count 0 2006.201.02:55:51.28#ibcon#enter sib2, iclass 31, count 0 2006.201.02:55:51.28#ibcon#flushed, iclass 31, count 0 2006.201.02:55:51.28#ibcon#about to write, iclass 31, count 0 2006.201.02:55:51.28#ibcon#wrote, iclass 31, count 0 2006.201.02:55:51.28#ibcon#about to read 3, iclass 31, count 0 2006.201.02:55:51.30#ibcon#read 3, iclass 31, count 0 2006.201.02:55:51.30#ibcon#about to read 4, iclass 31, count 0 2006.201.02:55:51.30#ibcon#read 4, iclass 31, count 0 2006.201.02:55:51.30#ibcon#about to read 5, iclass 31, count 0 2006.201.02:55:51.30#ibcon#read 5, iclass 31, count 0 2006.201.02:55:51.30#ibcon#about to read 6, iclass 31, count 0 2006.201.02:55:51.30#ibcon#read 6, iclass 31, count 0 2006.201.02:55:51.30#ibcon#end of sib2, iclass 31, count 0 2006.201.02:55:51.30#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:55:51.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:55:51.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.02:55:51.30#ibcon#*before write, iclass 31, count 0 2006.201.02:55:51.30#ibcon#enter sib2, iclass 31, count 0 2006.201.02:55:51.30#ibcon#flushed, iclass 31, count 0 2006.201.02:55:51.30#ibcon#about to write, iclass 31, count 0 2006.201.02:55:51.30#ibcon#wrote, iclass 31, count 0 2006.201.02:55:51.30#ibcon#about to read 3, iclass 31, count 0 2006.201.02:55:51.34#ibcon#read 3, iclass 31, count 0 2006.201.02:55:51.34#ibcon#about to read 4, iclass 31, count 0 2006.201.02:55:51.34#ibcon#read 4, iclass 31, count 0 2006.201.02:55:51.34#ibcon#about to read 5, iclass 31, count 0 2006.201.02:55:51.34#ibcon#read 5, iclass 31, count 0 2006.201.02:55:51.34#ibcon#about to read 6, iclass 31, count 0 2006.201.02:55:51.34#ibcon#read 6, iclass 31, count 0 2006.201.02:55:51.34#ibcon#end of sib2, iclass 31, count 0 2006.201.02:55:51.34#ibcon#*after write, iclass 31, count 0 2006.201.02:55:51.34#ibcon#*before return 0, iclass 31, count 0 2006.201.02:55:51.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:51.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:51.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:55:51.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:55:51.34$vck44/va=7,5 2006.201.02:55:51.34#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.02:55:51.34#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.02:55:51.34#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:51.34#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:51.40#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:51.40#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:51.40#ibcon#enter wrdev, iclass 33, count 2 2006.201.02:55:51.40#ibcon#first serial, iclass 33, count 2 2006.201.02:55:51.40#ibcon#enter sib2, iclass 33, count 2 2006.201.02:55:51.40#ibcon#flushed, iclass 33, count 2 2006.201.02:55:51.40#ibcon#about to write, iclass 33, count 2 2006.201.02:55:51.40#ibcon#wrote, iclass 33, count 2 2006.201.02:55:51.40#ibcon#about to read 3, iclass 33, count 2 2006.201.02:55:51.42#ibcon#read 3, iclass 33, count 2 2006.201.02:55:51.42#ibcon#about to read 4, iclass 33, count 2 2006.201.02:55:51.42#ibcon#read 4, iclass 33, count 2 2006.201.02:55:51.42#ibcon#about to read 5, iclass 33, count 2 2006.201.02:55:51.42#ibcon#read 5, iclass 33, count 2 2006.201.02:55:51.42#ibcon#about to read 6, iclass 33, count 2 2006.201.02:55:51.42#ibcon#read 6, iclass 33, count 2 2006.201.02:55:51.42#ibcon#end of sib2, iclass 33, count 2 2006.201.02:55:51.42#ibcon#*mode == 0, iclass 33, count 2 2006.201.02:55:51.42#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.02:55:51.42#ibcon#[25=AT07-05\r\n] 2006.201.02:55:51.42#ibcon#*before write, iclass 33, count 2 2006.201.02:55:51.42#ibcon#enter sib2, iclass 33, count 2 2006.201.02:55:51.42#ibcon#flushed, iclass 33, count 2 2006.201.02:55:51.42#ibcon#about to write, iclass 33, count 2 2006.201.02:55:51.42#ibcon#wrote, iclass 33, count 2 2006.201.02:55:51.42#ibcon#about to read 3, iclass 33, count 2 2006.201.02:55:51.45#ibcon#read 3, iclass 33, count 2 2006.201.02:55:51.45#ibcon#about to read 4, iclass 33, count 2 2006.201.02:55:51.45#ibcon#read 4, iclass 33, count 2 2006.201.02:55:51.45#ibcon#about to read 5, iclass 33, count 2 2006.201.02:55:51.45#ibcon#read 5, iclass 33, count 2 2006.201.02:55:51.45#ibcon#about to read 6, iclass 33, count 2 2006.201.02:55:51.45#ibcon#read 6, iclass 33, count 2 2006.201.02:55:51.45#ibcon#end of sib2, iclass 33, count 2 2006.201.02:55:51.45#ibcon#*after write, iclass 33, count 2 2006.201.02:55:51.45#ibcon#*before return 0, iclass 33, count 2 2006.201.02:55:51.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:51.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:51.45#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.02:55:51.45#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:51.45#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:51.57#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:51.57#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:51.57#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:55:51.57#ibcon#first serial, iclass 33, count 0 2006.201.02:55:51.57#ibcon#enter sib2, iclass 33, count 0 2006.201.02:55:51.57#ibcon#flushed, iclass 33, count 0 2006.201.02:55:51.57#ibcon#about to write, iclass 33, count 0 2006.201.02:55:51.57#ibcon#wrote, iclass 33, count 0 2006.201.02:55:51.57#ibcon#about to read 3, iclass 33, count 0 2006.201.02:55:51.59#ibcon#read 3, iclass 33, count 0 2006.201.02:55:51.59#ibcon#about to read 4, iclass 33, count 0 2006.201.02:55:51.59#ibcon#read 4, iclass 33, count 0 2006.201.02:55:51.59#ibcon#about to read 5, iclass 33, count 0 2006.201.02:55:51.59#ibcon#read 5, iclass 33, count 0 2006.201.02:55:51.59#ibcon#about to read 6, iclass 33, count 0 2006.201.02:55:51.59#ibcon#read 6, iclass 33, count 0 2006.201.02:55:51.59#ibcon#end of sib2, iclass 33, count 0 2006.201.02:55:51.59#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:55:51.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:55:51.59#ibcon#[25=USB\r\n] 2006.201.02:55:51.59#ibcon#*before write, iclass 33, count 0 2006.201.02:55:51.59#ibcon#enter sib2, iclass 33, count 0 2006.201.02:55:51.59#ibcon#flushed, iclass 33, count 0 2006.201.02:55:51.59#ibcon#about to write, iclass 33, count 0 2006.201.02:55:51.59#ibcon#wrote, iclass 33, count 0 2006.201.02:55:51.59#ibcon#about to read 3, iclass 33, count 0 2006.201.02:55:51.62#ibcon#read 3, iclass 33, count 0 2006.201.02:55:51.62#ibcon#about to read 4, iclass 33, count 0 2006.201.02:55:51.62#ibcon#read 4, iclass 33, count 0 2006.201.02:55:51.62#ibcon#about to read 5, iclass 33, count 0 2006.201.02:55:51.62#ibcon#read 5, iclass 33, count 0 2006.201.02:55:51.62#ibcon#about to read 6, iclass 33, count 0 2006.201.02:55:51.62#ibcon#read 6, iclass 33, count 0 2006.201.02:55:51.62#ibcon#end of sib2, iclass 33, count 0 2006.201.02:55:51.62#ibcon#*after write, iclass 33, count 0 2006.201.02:55:51.62#ibcon#*before return 0, iclass 33, count 0 2006.201.02:55:51.62#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:51.62#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:51.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:55:51.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:55:51.62$vck44/valo=8,884.99 2006.201.02:55:51.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.02:55:51.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.02:55:51.62#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:51.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:51.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:51.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:51.62#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:55:51.62#ibcon#first serial, iclass 35, count 0 2006.201.02:55:51.62#ibcon#enter sib2, iclass 35, count 0 2006.201.02:55:51.62#ibcon#flushed, iclass 35, count 0 2006.201.02:55:51.62#ibcon#about to write, iclass 35, count 0 2006.201.02:55:51.62#ibcon#wrote, iclass 35, count 0 2006.201.02:55:51.62#ibcon#about to read 3, iclass 35, count 0 2006.201.02:55:51.64#ibcon#read 3, iclass 35, count 0 2006.201.02:55:51.64#ibcon#about to read 4, iclass 35, count 0 2006.201.02:55:51.64#ibcon#read 4, iclass 35, count 0 2006.201.02:55:51.64#ibcon#about to read 5, iclass 35, count 0 2006.201.02:55:51.64#ibcon#read 5, iclass 35, count 0 2006.201.02:55:51.64#ibcon#about to read 6, iclass 35, count 0 2006.201.02:55:51.64#ibcon#read 6, iclass 35, count 0 2006.201.02:55:51.64#ibcon#end of sib2, iclass 35, count 0 2006.201.02:55:51.64#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:55:51.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:55:51.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.02:55:51.64#ibcon#*before write, iclass 35, count 0 2006.201.02:55:51.64#ibcon#enter sib2, iclass 35, count 0 2006.201.02:55:51.64#ibcon#flushed, iclass 35, count 0 2006.201.02:55:51.64#ibcon#about to write, iclass 35, count 0 2006.201.02:55:51.64#ibcon#wrote, iclass 35, count 0 2006.201.02:55:51.64#ibcon#about to read 3, iclass 35, count 0 2006.201.02:55:51.68#ibcon#read 3, iclass 35, count 0 2006.201.02:55:51.68#ibcon#about to read 4, iclass 35, count 0 2006.201.02:55:51.68#ibcon#read 4, iclass 35, count 0 2006.201.02:55:51.68#ibcon#about to read 5, iclass 35, count 0 2006.201.02:55:51.68#ibcon#read 5, iclass 35, count 0 2006.201.02:55:51.68#ibcon#about to read 6, iclass 35, count 0 2006.201.02:55:51.68#ibcon#read 6, iclass 35, count 0 2006.201.02:55:51.68#ibcon#end of sib2, iclass 35, count 0 2006.201.02:55:51.68#ibcon#*after write, iclass 35, count 0 2006.201.02:55:51.68#ibcon#*before return 0, iclass 35, count 0 2006.201.02:55:51.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:51.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:51.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:55:51.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:55:51.68$vck44/va=8,4 2006.201.02:55:51.68#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.02:55:51.68#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.02:55:51.68#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:51.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:55:51.74#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:55:51.74#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:55:51.74#ibcon#enter wrdev, iclass 37, count 2 2006.201.02:55:51.74#ibcon#first serial, iclass 37, count 2 2006.201.02:55:51.74#ibcon#enter sib2, iclass 37, count 2 2006.201.02:55:51.74#ibcon#flushed, iclass 37, count 2 2006.201.02:55:51.74#ibcon#about to write, iclass 37, count 2 2006.201.02:55:51.74#ibcon#wrote, iclass 37, count 2 2006.201.02:55:51.74#ibcon#about to read 3, iclass 37, count 2 2006.201.02:55:51.76#ibcon#read 3, iclass 37, count 2 2006.201.02:55:51.76#ibcon#about to read 4, iclass 37, count 2 2006.201.02:55:51.76#ibcon#read 4, iclass 37, count 2 2006.201.02:55:51.76#ibcon#about to read 5, iclass 37, count 2 2006.201.02:55:51.76#ibcon#read 5, iclass 37, count 2 2006.201.02:55:51.76#ibcon#about to read 6, iclass 37, count 2 2006.201.02:55:51.76#ibcon#read 6, iclass 37, count 2 2006.201.02:55:51.76#ibcon#end of sib2, iclass 37, count 2 2006.201.02:55:51.76#ibcon#*mode == 0, iclass 37, count 2 2006.201.02:55:51.76#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.02:55:51.76#ibcon#[25=AT08-04\r\n] 2006.201.02:55:51.76#ibcon#*before write, iclass 37, count 2 2006.201.02:55:51.76#ibcon#enter sib2, iclass 37, count 2 2006.201.02:55:51.76#ibcon#flushed, iclass 37, count 2 2006.201.02:55:51.76#ibcon#about to write, iclass 37, count 2 2006.201.02:55:51.76#ibcon#wrote, iclass 37, count 2 2006.201.02:55:51.76#ibcon#about to read 3, iclass 37, count 2 2006.201.02:55:51.79#ibcon#read 3, iclass 37, count 2 2006.201.02:55:51.79#ibcon#about to read 4, iclass 37, count 2 2006.201.02:55:51.79#ibcon#read 4, iclass 37, count 2 2006.201.02:55:51.79#ibcon#about to read 5, iclass 37, count 2 2006.201.02:55:51.79#ibcon#read 5, iclass 37, count 2 2006.201.02:55:51.79#ibcon#about to read 6, iclass 37, count 2 2006.201.02:55:51.79#ibcon#read 6, iclass 37, count 2 2006.201.02:55:51.79#ibcon#end of sib2, iclass 37, count 2 2006.201.02:55:51.79#ibcon#*after write, iclass 37, count 2 2006.201.02:55:51.79#ibcon#*before return 0, iclass 37, count 2 2006.201.02:55:51.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:55:51.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.02:55:51.79#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.02:55:51.79#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:51.79#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:55:51.91#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:55:51.91#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:55:51.91#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:55:51.91#ibcon#first serial, iclass 37, count 0 2006.201.02:55:51.91#ibcon#enter sib2, iclass 37, count 0 2006.201.02:55:51.91#ibcon#flushed, iclass 37, count 0 2006.201.02:55:51.91#ibcon#about to write, iclass 37, count 0 2006.201.02:55:51.91#ibcon#wrote, iclass 37, count 0 2006.201.02:55:51.91#ibcon#about to read 3, iclass 37, count 0 2006.201.02:55:51.93#ibcon#read 3, iclass 37, count 0 2006.201.02:55:51.93#ibcon#about to read 4, iclass 37, count 0 2006.201.02:55:51.93#ibcon#read 4, iclass 37, count 0 2006.201.02:55:51.93#ibcon#about to read 5, iclass 37, count 0 2006.201.02:55:51.93#ibcon#read 5, iclass 37, count 0 2006.201.02:55:51.93#ibcon#about to read 6, iclass 37, count 0 2006.201.02:55:51.93#ibcon#read 6, iclass 37, count 0 2006.201.02:55:51.93#ibcon#end of sib2, iclass 37, count 0 2006.201.02:55:51.93#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:55:51.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:55:51.93#ibcon#[25=USB\r\n] 2006.201.02:55:51.93#ibcon#*before write, iclass 37, count 0 2006.201.02:55:51.93#ibcon#enter sib2, iclass 37, count 0 2006.201.02:55:51.93#ibcon#flushed, iclass 37, count 0 2006.201.02:55:51.93#ibcon#about to write, iclass 37, count 0 2006.201.02:55:51.93#ibcon#wrote, iclass 37, count 0 2006.201.02:55:51.93#ibcon#about to read 3, iclass 37, count 0 2006.201.02:55:51.96#ibcon#read 3, iclass 37, count 0 2006.201.02:55:51.96#ibcon#about to read 4, iclass 37, count 0 2006.201.02:55:51.96#ibcon#read 4, iclass 37, count 0 2006.201.02:55:51.96#ibcon#about to read 5, iclass 37, count 0 2006.201.02:55:51.96#ibcon#read 5, iclass 37, count 0 2006.201.02:55:51.96#ibcon#about to read 6, iclass 37, count 0 2006.201.02:55:51.96#ibcon#read 6, iclass 37, count 0 2006.201.02:55:51.96#ibcon#end of sib2, iclass 37, count 0 2006.201.02:55:51.96#ibcon#*after write, iclass 37, count 0 2006.201.02:55:51.96#ibcon#*before return 0, iclass 37, count 0 2006.201.02:55:51.96#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:55:51.96#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.02:55:51.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:55:51.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:55:51.96$vck44/vblo=1,629.99 2006.201.02:55:51.96#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.02:55:51.96#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.02:55:51.96#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:51.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:51.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:51.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:51.96#ibcon#enter wrdev, iclass 39, count 0 2006.201.02:55:51.96#ibcon#first serial, iclass 39, count 0 2006.201.02:55:51.96#ibcon#enter sib2, iclass 39, count 0 2006.201.02:55:51.96#ibcon#flushed, iclass 39, count 0 2006.201.02:55:51.96#ibcon#about to write, iclass 39, count 0 2006.201.02:55:51.96#ibcon#wrote, iclass 39, count 0 2006.201.02:55:51.96#ibcon#about to read 3, iclass 39, count 0 2006.201.02:55:51.98#ibcon#read 3, iclass 39, count 0 2006.201.02:55:51.98#ibcon#about to read 4, iclass 39, count 0 2006.201.02:55:51.98#ibcon#read 4, iclass 39, count 0 2006.201.02:55:51.98#ibcon#about to read 5, iclass 39, count 0 2006.201.02:55:51.98#ibcon#read 5, iclass 39, count 0 2006.201.02:55:51.98#ibcon#about to read 6, iclass 39, count 0 2006.201.02:55:51.98#ibcon#read 6, iclass 39, count 0 2006.201.02:55:51.98#ibcon#end of sib2, iclass 39, count 0 2006.201.02:55:51.98#ibcon#*mode == 0, iclass 39, count 0 2006.201.02:55:51.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.02:55:51.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.02:55:51.98#ibcon#*before write, iclass 39, count 0 2006.201.02:55:51.98#ibcon#enter sib2, iclass 39, count 0 2006.201.02:55:51.98#ibcon#flushed, iclass 39, count 0 2006.201.02:55:51.98#ibcon#about to write, iclass 39, count 0 2006.201.02:55:51.98#ibcon#wrote, iclass 39, count 0 2006.201.02:55:51.98#ibcon#about to read 3, iclass 39, count 0 2006.201.02:55:52.02#ibcon#read 3, iclass 39, count 0 2006.201.02:55:52.02#ibcon#about to read 4, iclass 39, count 0 2006.201.02:55:52.02#ibcon#read 4, iclass 39, count 0 2006.201.02:55:52.02#ibcon#about to read 5, iclass 39, count 0 2006.201.02:55:52.02#ibcon#read 5, iclass 39, count 0 2006.201.02:55:52.02#ibcon#about to read 6, iclass 39, count 0 2006.201.02:55:52.02#ibcon#read 6, iclass 39, count 0 2006.201.02:55:52.02#ibcon#end of sib2, iclass 39, count 0 2006.201.02:55:52.02#ibcon#*after write, iclass 39, count 0 2006.201.02:55:52.02#ibcon#*before return 0, iclass 39, count 0 2006.201.02:55:52.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:52.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.02:55:52.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.02:55:52.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.02:55:52.02$vck44/vb=1,4 2006.201.02:55:52.02#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.02:55:52.02#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.02:55:52.02#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:52.02#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:52.02#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:52.02#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:52.02#ibcon#enter wrdev, iclass 2, count 2 2006.201.02:55:52.02#ibcon#first serial, iclass 2, count 2 2006.201.02:55:52.02#ibcon#enter sib2, iclass 2, count 2 2006.201.02:55:52.02#ibcon#flushed, iclass 2, count 2 2006.201.02:55:52.02#ibcon#about to write, iclass 2, count 2 2006.201.02:55:52.02#ibcon#wrote, iclass 2, count 2 2006.201.02:55:52.02#ibcon#about to read 3, iclass 2, count 2 2006.201.02:55:52.04#ibcon#read 3, iclass 2, count 2 2006.201.02:55:52.04#ibcon#about to read 4, iclass 2, count 2 2006.201.02:55:52.04#ibcon#read 4, iclass 2, count 2 2006.201.02:55:52.04#ibcon#about to read 5, iclass 2, count 2 2006.201.02:55:52.04#ibcon#read 5, iclass 2, count 2 2006.201.02:55:52.04#ibcon#about to read 6, iclass 2, count 2 2006.201.02:55:52.04#ibcon#read 6, iclass 2, count 2 2006.201.02:55:52.04#ibcon#end of sib2, iclass 2, count 2 2006.201.02:55:52.04#ibcon#*mode == 0, iclass 2, count 2 2006.201.02:55:52.04#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.02:55:52.04#ibcon#[27=AT01-04\r\n] 2006.201.02:55:52.04#ibcon#*before write, iclass 2, count 2 2006.201.02:55:52.04#ibcon#enter sib2, iclass 2, count 2 2006.201.02:55:52.04#ibcon#flushed, iclass 2, count 2 2006.201.02:55:52.04#ibcon#about to write, iclass 2, count 2 2006.201.02:55:52.04#ibcon#wrote, iclass 2, count 2 2006.201.02:55:52.04#ibcon#about to read 3, iclass 2, count 2 2006.201.02:55:52.07#ibcon#read 3, iclass 2, count 2 2006.201.02:55:52.07#ibcon#about to read 4, iclass 2, count 2 2006.201.02:55:52.07#ibcon#read 4, iclass 2, count 2 2006.201.02:55:52.07#ibcon#about to read 5, iclass 2, count 2 2006.201.02:55:52.07#ibcon#read 5, iclass 2, count 2 2006.201.02:55:52.07#ibcon#about to read 6, iclass 2, count 2 2006.201.02:55:52.07#ibcon#read 6, iclass 2, count 2 2006.201.02:55:52.07#ibcon#end of sib2, iclass 2, count 2 2006.201.02:55:52.07#ibcon#*after write, iclass 2, count 2 2006.201.02:55:52.07#ibcon#*before return 0, iclass 2, count 2 2006.201.02:55:52.07#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:52.07#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.02:55:52.07#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.02:55:52.07#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:52.07#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:52.19#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:52.19#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:52.19#ibcon#enter wrdev, iclass 2, count 0 2006.201.02:55:52.19#ibcon#first serial, iclass 2, count 0 2006.201.02:55:52.19#ibcon#enter sib2, iclass 2, count 0 2006.201.02:55:52.19#ibcon#flushed, iclass 2, count 0 2006.201.02:55:52.19#ibcon#about to write, iclass 2, count 0 2006.201.02:55:52.19#ibcon#wrote, iclass 2, count 0 2006.201.02:55:52.19#ibcon#about to read 3, iclass 2, count 0 2006.201.02:55:52.21#ibcon#read 3, iclass 2, count 0 2006.201.02:55:52.21#ibcon#about to read 4, iclass 2, count 0 2006.201.02:55:52.21#ibcon#read 4, iclass 2, count 0 2006.201.02:55:52.21#ibcon#about to read 5, iclass 2, count 0 2006.201.02:55:52.21#ibcon#read 5, iclass 2, count 0 2006.201.02:55:52.21#ibcon#about to read 6, iclass 2, count 0 2006.201.02:55:52.21#ibcon#read 6, iclass 2, count 0 2006.201.02:55:52.21#ibcon#end of sib2, iclass 2, count 0 2006.201.02:55:52.21#ibcon#*mode == 0, iclass 2, count 0 2006.201.02:55:52.21#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.02:55:52.21#ibcon#[27=USB\r\n] 2006.201.02:55:52.21#ibcon#*before write, iclass 2, count 0 2006.201.02:55:52.21#ibcon#enter sib2, iclass 2, count 0 2006.201.02:55:52.21#ibcon#flushed, iclass 2, count 0 2006.201.02:55:52.21#ibcon#about to write, iclass 2, count 0 2006.201.02:55:52.21#ibcon#wrote, iclass 2, count 0 2006.201.02:55:52.21#ibcon#about to read 3, iclass 2, count 0 2006.201.02:55:52.24#ibcon#read 3, iclass 2, count 0 2006.201.02:55:52.24#ibcon#about to read 4, iclass 2, count 0 2006.201.02:55:52.24#ibcon#read 4, iclass 2, count 0 2006.201.02:55:52.24#ibcon#about to read 5, iclass 2, count 0 2006.201.02:55:52.24#ibcon#read 5, iclass 2, count 0 2006.201.02:55:52.24#ibcon#about to read 6, iclass 2, count 0 2006.201.02:55:52.24#ibcon#read 6, iclass 2, count 0 2006.201.02:55:52.24#ibcon#end of sib2, iclass 2, count 0 2006.201.02:55:52.24#ibcon#*after write, iclass 2, count 0 2006.201.02:55:52.24#ibcon#*before return 0, iclass 2, count 0 2006.201.02:55:52.24#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:52.24#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.02:55:52.24#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.02:55:52.24#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.02:55:52.24$vck44/vblo=2,634.99 2006.201.02:55:52.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.02:55:52.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.02:55:52.24#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:52.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:52.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:52.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:52.24#ibcon#enter wrdev, iclass 5, count 0 2006.201.02:55:52.24#ibcon#first serial, iclass 5, count 0 2006.201.02:55:52.24#ibcon#enter sib2, iclass 5, count 0 2006.201.02:55:52.24#ibcon#flushed, iclass 5, count 0 2006.201.02:55:52.24#ibcon#about to write, iclass 5, count 0 2006.201.02:55:52.24#ibcon#wrote, iclass 5, count 0 2006.201.02:55:52.24#ibcon#about to read 3, iclass 5, count 0 2006.201.02:55:52.26#ibcon#read 3, iclass 5, count 0 2006.201.02:55:52.26#ibcon#about to read 4, iclass 5, count 0 2006.201.02:55:52.26#ibcon#read 4, iclass 5, count 0 2006.201.02:55:52.26#ibcon#about to read 5, iclass 5, count 0 2006.201.02:55:52.26#ibcon#read 5, iclass 5, count 0 2006.201.02:55:52.26#ibcon#about to read 6, iclass 5, count 0 2006.201.02:55:52.26#ibcon#read 6, iclass 5, count 0 2006.201.02:55:52.26#ibcon#end of sib2, iclass 5, count 0 2006.201.02:55:52.26#ibcon#*mode == 0, iclass 5, count 0 2006.201.02:55:52.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.02:55:52.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.02:55:52.26#ibcon#*before write, iclass 5, count 0 2006.201.02:55:52.26#ibcon#enter sib2, iclass 5, count 0 2006.201.02:55:52.26#ibcon#flushed, iclass 5, count 0 2006.201.02:55:52.26#ibcon#about to write, iclass 5, count 0 2006.201.02:55:52.26#ibcon#wrote, iclass 5, count 0 2006.201.02:55:52.26#ibcon#about to read 3, iclass 5, count 0 2006.201.02:55:52.30#ibcon#read 3, iclass 5, count 0 2006.201.02:55:52.30#ibcon#about to read 4, iclass 5, count 0 2006.201.02:55:52.30#ibcon#read 4, iclass 5, count 0 2006.201.02:55:52.30#ibcon#about to read 5, iclass 5, count 0 2006.201.02:55:52.30#ibcon#read 5, iclass 5, count 0 2006.201.02:55:52.30#ibcon#about to read 6, iclass 5, count 0 2006.201.02:55:52.30#ibcon#read 6, iclass 5, count 0 2006.201.02:55:52.30#ibcon#end of sib2, iclass 5, count 0 2006.201.02:55:52.30#ibcon#*after write, iclass 5, count 0 2006.201.02:55:52.30#ibcon#*before return 0, iclass 5, count 0 2006.201.02:55:52.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:52.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.02:55:52.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.02:55:52.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.02:55:52.30$vck44/vb=2,5 2006.201.02:55:52.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.02:55:52.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.02:55:52.30#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:52.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:52.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:52.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:52.36#ibcon#enter wrdev, iclass 7, count 2 2006.201.02:55:52.36#ibcon#first serial, iclass 7, count 2 2006.201.02:55:52.36#ibcon#enter sib2, iclass 7, count 2 2006.201.02:55:52.36#ibcon#flushed, iclass 7, count 2 2006.201.02:55:52.36#ibcon#about to write, iclass 7, count 2 2006.201.02:55:52.36#ibcon#wrote, iclass 7, count 2 2006.201.02:55:52.36#ibcon#about to read 3, iclass 7, count 2 2006.201.02:55:52.38#ibcon#read 3, iclass 7, count 2 2006.201.02:55:52.38#ibcon#about to read 4, iclass 7, count 2 2006.201.02:55:52.38#ibcon#read 4, iclass 7, count 2 2006.201.02:55:52.38#ibcon#about to read 5, iclass 7, count 2 2006.201.02:55:52.38#ibcon#read 5, iclass 7, count 2 2006.201.02:55:52.38#ibcon#about to read 6, iclass 7, count 2 2006.201.02:55:52.38#ibcon#read 6, iclass 7, count 2 2006.201.02:55:52.38#ibcon#end of sib2, iclass 7, count 2 2006.201.02:55:52.38#ibcon#*mode == 0, iclass 7, count 2 2006.201.02:55:52.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.02:55:52.38#ibcon#[27=AT02-05\r\n] 2006.201.02:55:52.38#ibcon#*before write, iclass 7, count 2 2006.201.02:55:52.38#ibcon#enter sib2, iclass 7, count 2 2006.201.02:55:52.38#ibcon#flushed, iclass 7, count 2 2006.201.02:55:52.38#ibcon#about to write, iclass 7, count 2 2006.201.02:55:52.38#ibcon#wrote, iclass 7, count 2 2006.201.02:55:52.38#ibcon#about to read 3, iclass 7, count 2 2006.201.02:55:52.41#ibcon#read 3, iclass 7, count 2 2006.201.02:55:52.41#ibcon#about to read 4, iclass 7, count 2 2006.201.02:55:52.41#ibcon#read 4, iclass 7, count 2 2006.201.02:55:52.41#ibcon#about to read 5, iclass 7, count 2 2006.201.02:55:52.41#ibcon#read 5, iclass 7, count 2 2006.201.02:55:52.41#ibcon#about to read 6, iclass 7, count 2 2006.201.02:55:52.41#ibcon#read 6, iclass 7, count 2 2006.201.02:55:52.41#ibcon#end of sib2, iclass 7, count 2 2006.201.02:55:52.41#ibcon#*after write, iclass 7, count 2 2006.201.02:55:52.41#ibcon#*before return 0, iclass 7, count 2 2006.201.02:55:52.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:52.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.02:55:52.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.02:55:52.41#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:52.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:52.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:52.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:52.53#ibcon#enter wrdev, iclass 7, count 0 2006.201.02:55:52.53#ibcon#first serial, iclass 7, count 0 2006.201.02:55:52.53#ibcon#enter sib2, iclass 7, count 0 2006.201.02:55:52.53#ibcon#flushed, iclass 7, count 0 2006.201.02:55:52.53#ibcon#about to write, iclass 7, count 0 2006.201.02:55:52.53#ibcon#wrote, iclass 7, count 0 2006.201.02:55:52.53#ibcon#about to read 3, iclass 7, count 0 2006.201.02:55:52.55#ibcon#read 3, iclass 7, count 0 2006.201.02:55:52.55#ibcon#about to read 4, iclass 7, count 0 2006.201.02:55:52.55#ibcon#read 4, iclass 7, count 0 2006.201.02:55:52.55#ibcon#about to read 5, iclass 7, count 0 2006.201.02:55:52.55#ibcon#read 5, iclass 7, count 0 2006.201.02:55:52.55#ibcon#about to read 6, iclass 7, count 0 2006.201.02:55:52.55#ibcon#read 6, iclass 7, count 0 2006.201.02:55:52.55#ibcon#end of sib2, iclass 7, count 0 2006.201.02:55:52.55#ibcon#*mode == 0, iclass 7, count 0 2006.201.02:55:52.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.02:55:52.55#ibcon#[27=USB\r\n] 2006.201.02:55:52.55#ibcon#*before write, iclass 7, count 0 2006.201.02:55:52.55#ibcon#enter sib2, iclass 7, count 0 2006.201.02:55:52.55#ibcon#flushed, iclass 7, count 0 2006.201.02:55:52.55#ibcon#about to write, iclass 7, count 0 2006.201.02:55:52.55#ibcon#wrote, iclass 7, count 0 2006.201.02:55:52.55#ibcon#about to read 3, iclass 7, count 0 2006.201.02:55:52.58#ibcon#read 3, iclass 7, count 0 2006.201.02:55:52.58#ibcon#about to read 4, iclass 7, count 0 2006.201.02:55:52.58#ibcon#read 4, iclass 7, count 0 2006.201.02:55:52.58#ibcon#about to read 5, iclass 7, count 0 2006.201.02:55:52.58#ibcon#read 5, iclass 7, count 0 2006.201.02:55:52.58#ibcon#about to read 6, iclass 7, count 0 2006.201.02:55:52.58#ibcon#read 6, iclass 7, count 0 2006.201.02:55:52.58#ibcon#end of sib2, iclass 7, count 0 2006.201.02:55:52.58#ibcon#*after write, iclass 7, count 0 2006.201.02:55:52.58#ibcon#*before return 0, iclass 7, count 0 2006.201.02:55:52.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:52.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.02:55:52.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.02:55:52.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.02:55:52.58$vck44/vblo=3,649.99 2006.201.02:55:52.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.02:55:52.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.02:55:52.58#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:52.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:52.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:52.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:52.58#ibcon#enter wrdev, iclass 11, count 0 2006.201.02:55:52.58#ibcon#first serial, iclass 11, count 0 2006.201.02:55:52.58#ibcon#enter sib2, iclass 11, count 0 2006.201.02:55:52.58#ibcon#flushed, iclass 11, count 0 2006.201.02:55:52.58#ibcon#about to write, iclass 11, count 0 2006.201.02:55:52.58#ibcon#wrote, iclass 11, count 0 2006.201.02:55:52.58#ibcon#about to read 3, iclass 11, count 0 2006.201.02:55:52.60#ibcon#read 3, iclass 11, count 0 2006.201.02:55:52.60#ibcon#about to read 4, iclass 11, count 0 2006.201.02:55:52.60#ibcon#read 4, iclass 11, count 0 2006.201.02:55:52.60#ibcon#about to read 5, iclass 11, count 0 2006.201.02:55:52.60#ibcon#read 5, iclass 11, count 0 2006.201.02:55:52.60#ibcon#about to read 6, iclass 11, count 0 2006.201.02:55:52.60#ibcon#read 6, iclass 11, count 0 2006.201.02:55:52.60#ibcon#end of sib2, iclass 11, count 0 2006.201.02:55:52.60#ibcon#*mode == 0, iclass 11, count 0 2006.201.02:55:52.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.02:55:52.60#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.02:55:52.60#ibcon#*before write, iclass 11, count 0 2006.201.02:55:52.60#ibcon#enter sib2, iclass 11, count 0 2006.201.02:55:52.60#ibcon#flushed, iclass 11, count 0 2006.201.02:55:52.60#ibcon#about to write, iclass 11, count 0 2006.201.02:55:52.60#ibcon#wrote, iclass 11, count 0 2006.201.02:55:52.60#ibcon#about to read 3, iclass 11, count 0 2006.201.02:55:52.64#ibcon#read 3, iclass 11, count 0 2006.201.02:55:52.64#ibcon#about to read 4, iclass 11, count 0 2006.201.02:55:52.64#ibcon#read 4, iclass 11, count 0 2006.201.02:55:52.64#ibcon#about to read 5, iclass 11, count 0 2006.201.02:55:52.64#ibcon#read 5, iclass 11, count 0 2006.201.02:55:52.64#ibcon#about to read 6, iclass 11, count 0 2006.201.02:55:52.64#ibcon#read 6, iclass 11, count 0 2006.201.02:55:52.64#ibcon#end of sib2, iclass 11, count 0 2006.201.02:55:52.64#ibcon#*after write, iclass 11, count 0 2006.201.02:55:52.64#ibcon#*before return 0, iclass 11, count 0 2006.201.02:55:52.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:52.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.02:55:52.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.02:55:52.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.02:55:52.64$vck44/vb=3,4 2006.201.02:55:52.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.02:55:52.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.02:55:52.64#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:52.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:52.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:52.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:52.70#ibcon#enter wrdev, iclass 13, count 2 2006.201.02:55:52.70#ibcon#first serial, iclass 13, count 2 2006.201.02:55:52.70#ibcon#enter sib2, iclass 13, count 2 2006.201.02:55:52.70#ibcon#flushed, iclass 13, count 2 2006.201.02:55:52.70#ibcon#about to write, iclass 13, count 2 2006.201.02:55:52.70#ibcon#wrote, iclass 13, count 2 2006.201.02:55:52.70#ibcon#about to read 3, iclass 13, count 2 2006.201.02:55:52.72#ibcon#read 3, iclass 13, count 2 2006.201.02:55:52.72#ibcon#about to read 4, iclass 13, count 2 2006.201.02:55:52.72#ibcon#read 4, iclass 13, count 2 2006.201.02:55:52.72#ibcon#about to read 5, iclass 13, count 2 2006.201.02:55:52.72#ibcon#read 5, iclass 13, count 2 2006.201.02:55:52.72#ibcon#about to read 6, iclass 13, count 2 2006.201.02:55:52.72#ibcon#read 6, iclass 13, count 2 2006.201.02:55:52.72#ibcon#end of sib2, iclass 13, count 2 2006.201.02:55:52.72#ibcon#*mode == 0, iclass 13, count 2 2006.201.02:55:52.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.02:55:52.72#ibcon#[27=AT03-04\r\n] 2006.201.02:55:52.72#ibcon#*before write, iclass 13, count 2 2006.201.02:55:52.72#ibcon#enter sib2, iclass 13, count 2 2006.201.02:55:52.72#ibcon#flushed, iclass 13, count 2 2006.201.02:55:52.72#ibcon#about to write, iclass 13, count 2 2006.201.02:55:52.72#ibcon#wrote, iclass 13, count 2 2006.201.02:55:52.72#ibcon#about to read 3, iclass 13, count 2 2006.201.02:55:52.75#ibcon#read 3, iclass 13, count 2 2006.201.02:55:52.75#ibcon#about to read 4, iclass 13, count 2 2006.201.02:55:52.75#ibcon#read 4, iclass 13, count 2 2006.201.02:55:52.75#ibcon#about to read 5, iclass 13, count 2 2006.201.02:55:52.75#ibcon#read 5, iclass 13, count 2 2006.201.02:55:52.75#ibcon#about to read 6, iclass 13, count 2 2006.201.02:55:52.75#ibcon#read 6, iclass 13, count 2 2006.201.02:55:52.75#ibcon#end of sib2, iclass 13, count 2 2006.201.02:55:52.75#ibcon#*after write, iclass 13, count 2 2006.201.02:55:52.75#ibcon#*before return 0, iclass 13, count 2 2006.201.02:55:52.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:52.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.02:55:52.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.02:55:52.75#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:52.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:52.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:52.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:52.87#ibcon#enter wrdev, iclass 13, count 0 2006.201.02:55:52.87#ibcon#first serial, iclass 13, count 0 2006.201.02:55:52.87#ibcon#enter sib2, iclass 13, count 0 2006.201.02:55:52.87#ibcon#flushed, iclass 13, count 0 2006.201.02:55:52.87#ibcon#about to write, iclass 13, count 0 2006.201.02:55:52.87#ibcon#wrote, iclass 13, count 0 2006.201.02:55:52.87#ibcon#about to read 3, iclass 13, count 0 2006.201.02:55:52.89#ibcon#read 3, iclass 13, count 0 2006.201.02:55:52.89#ibcon#about to read 4, iclass 13, count 0 2006.201.02:55:52.89#ibcon#read 4, iclass 13, count 0 2006.201.02:55:52.89#ibcon#about to read 5, iclass 13, count 0 2006.201.02:55:52.89#ibcon#read 5, iclass 13, count 0 2006.201.02:55:52.89#ibcon#about to read 6, iclass 13, count 0 2006.201.02:55:52.89#ibcon#read 6, iclass 13, count 0 2006.201.02:55:52.89#ibcon#end of sib2, iclass 13, count 0 2006.201.02:55:52.89#ibcon#*mode == 0, iclass 13, count 0 2006.201.02:55:52.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.02:55:52.89#ibcon#[27=USB\r\n] 2006.201.02:55:52.89#ibcon#*before write, iclass 13, count 0 2006.201.02:55:52.89#ibcon#enter sib2, iclass 13, count 0 2006.201.02:55:52.89#ibcon#flushed, iclass 13, count 0 2006.201.02:55:52.89#ibcon#about to write, iclass 13, count 0 2006.201.02:55:52.89#ibcon#wrote, iclass 13, count 0 2006.201.02:55:52.89#ibcon#about to read 3, iclass 13, count 0 2006.201.02:55:52.92#ibcon#read 3, iclass 13, count 0 2006.201.02:55:52.92#ibcon#about to read 4, iclass 13, count 0 2006.201.02:55:52.92#ibcon#read 4, iclass 13, count 0 2006.201.02:55:52.92#ibcon#about to read 5, iclass 13, count 0 2006.201.02:55:52.92#ibcon#read 5, iclass 13, count 0 2006.201.02:55:52.92#ibcon#about to read 6, iclass 13, count 0 2006.201.02:55:52.92#ibcon#read 6, iclass 13, count 0 2006.201.02:55:52.92#ibcon#end of sib2, iclass 13, count 0 2006.201.02:55:52.92#ibcon#*after write, iclass 13, count 0 2006.201.02:55:52.92#ibcon#*before return 0, iclass 13, count 0 2006.201.02:55:52.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:52.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.02:55:52.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.02:55:52.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.02:55:52.92$vck44/vblo=4,679.99 2006.201.02:55:52.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.02:55:52.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.02:55:52.92#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:52.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:52.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:52.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:52.92#ibcon#enter wrdev, iclass 15, count 0 2006.201.02:55:52.92#ibcon#first serial, iclass 15, count 0 2006.201.02:55:52.92#ibcon#enter sib2, iclass 15, count 0 2006.201.02:55:52.92#ibcon#flushed, iclass 15, count 0 2006.201.02:55:52.92#ibcon#about to write, iclass 15, count 0 2006.201.02:55:52.92#ibcon#wrote, iclass 15, count 0 2006.201.02:55:52.92#ibcon#about to read 3, iclass 15, count 0 2006.201.02:55:52.94#ibcon#read 3, iclass 15, count 0 2006.201.02:55:52.94#ibcon#about to read 4, iclass 15, count 0 2006.201.02:55:52.94#ibcon#read 4, iclass 15, count 0 2006.201.02:55:52.94#ibcon#about to read 5, iclass 15, count 0 2006.201.02:55:52.94#ibcon#read 5, iclass 15, count 0 2006.201.02:55:52.94#ibcon#about to read 6, iclass 15, count 0 2006.201.02:55:52.94#ibcon#read 6, iclass 15, count 0 2006.201.02:55:52.94#ibcon#end of sib2, iclass 15, count 0 2006.201.02:55:52.94#ibcon#*mode == 0, iclass 15, count 0 2006.201.02:55:52.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.02:55:52.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.02:55:52.94#ibcon#*before write, iclass 15, count 0 2006.201.02:55:52.94#ibcon#enter sib2, iclass 15, count 0 2006.201.02:55:52.94#ibcon#flushed, iclass 15, count 0 2006.201.02:55:52.94#ibcon#about to write, iclass 15, count 0 2006.201.02:55:52.94#ibcon#wrote, iclass 15, count 0 2006.201.02:55:52.94#ibcon#about to read 3, iclass 15, count 0 2006.201.02:55:52.98#ibcon#read 3, iclass 15, count 0 2006.201.02:55:52.98#ibcon#about to read 4, iclass 15, count 0 2006.201.02:55:52.98#ibcon#read 4, iclass 15, count 0 2006.201.02:55:52.98#ibcon#about to read 5, iclass 15, count 0 2006.201.02:55:52.98#ibcon#read 5, iclass 15, count 0 2006.201.02:55:52.98#ibcon#about to read 6, iclass 15, count 0 2006.201.02:55:52.98#ibcon#read 6, iclass 15, count 0 2006.201.02:55:52.98#ibcon#end of sib2, iclass 15, count 0 2006.201.02:55:52.98#ibcon#*after write, iclass 15, count 0 2006.201.02:55:52.98#ibcon#*before return 0, iclass 15, count 0 2006.201.02:55:52.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:52.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.02:55:52.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.02:55:52.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.02:55:52.98$vck44/vb=4,5 2006.201.02:55:52.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.02:55:52.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.02:55:52.98#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:52.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:53.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:53.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:53.04#ibcon#enter wrdev, iclass 17, count 2 2006.201.02:55:53.04#ibcon#first serial, iclass 17, count 2 2006.201.02:55:53.04#ibcon#enter sib2, iclass 17, count 2 2006.201.02:55:53.04#ibcon#flushed, iclass 17, count 2 2006.201.02:55:53.04#ibcon#about to write, iclass 17, count 2 2006.201.02:55:53.04#ibcon#wrote, iclass 17, count 2 2006.201.02:55:53.04#ibcon#about to read 3, iclass 17, count 2 2006.201.02:55:53.06#ibcon#read 3, iclass 17, count 2 2006.201.02:55:53.06#ibcon#about to read 4, iclass 17, count 2 2006.201.02:55:53.06#ibcon#read 4, iclass 17, count 2 2006.201.02:55:53.06#ibcon#about to read 5, iclass 17, count 2 2006.201.02:55:53.06#ibcon#read 5, iclass 17, count 2 2006.201.02:55:53.06#ibcon#about to read 6, iclass 17, count 2 2006.201.02:55:53.06#ibcon#read 6, iclass 17, count 2 2006.201.02:55:53.06#ibcon#end of sib2, iclass 17, count 2 2006.201.02:55:53.06#ibcon#*mode == 0, iclass 17, count 2 2006.201.02:55:53.06#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.02:55:53.06#ibcon#[27=AT04-05\r\n] 2006.201.02:55:53.06#ibcon#*before write, iclass 17, count 2 2006.201.02:55:53.06#ibcon#enter sib2, iclass 17, count 2 2006.201.02:55:53.06#ibcon#flushed, iclass 17, count 2 2006.201.02:55:53.06#ibcon#about to write, iclass 17, count 2 2006.201.02:55:53.06#ibcon#wrote, iclass 17, count 2 2006.201.02:55:53.06#ibcon#about to read 3, iclass 17, count 2 2006.201.02:55:53.09#ibcon#read 3, iclass 17, count 2 2006.201.02:55:53.09#ibcon#about to read 4, iclass 17, count 2 2006.201.02:55:53.09#ibcon#read 4, iclass 17, count 2 2006.201.02:55:53.09#ibcon#about to read 5, iclass 17, count 2 2006.201.02:55:53.09#ibcon#read 5, iclass 17, count 2 2006.201.02:55:53.09#ibcon#about to read 6, iclass 17, count 2 2006.201.02:55:53.09#ibcon#read 6, iclass 17, count 2 2006.201.02:55:53.09#ibcon#end of sib2, iclass 17, count 2 2006.201.02:55:53.09#ibcon#*after write, iclass 17, count 2 2006.201.02:55:53.09#ibcon#*before return 0, iclass 17, count 2 2006.201.02:55:53.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:53.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.02:55:53.09#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.02:55:53.09#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:53.09#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:53.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:53.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:53.21#ibcon#enter wrdev, iclass 17, count 0 2006.201.02:55:53.21#ibcon#first serial, iclass 17, count 0 2006.201.02:55:53.21#ibcon#enter sib2, iclass 17, count 0 2006.201.02:55:53.21#ibcon#flushed, iclass 17, count 0 2006.201.02:55:53.21#ibcon#about to write, iclass 17, count 0 2006.201.02:55:53.21#ibcon#wrote, iclass 17, count 0 2006.201.02:55:53.21#ibcon#about to read 3, iclass 17, count 0 2006.201.02:55:53.24#ibcon#read 3, iclass 17, count 0 2006.201.02:55:53.24#ibcon#about to read 4, iclass 17, count 0 2006.201.02:55:53.24#ibcon#read 4, iclass 17, count 0 2006.201.02:55:53.24#ibcon#about to read 5, iclass 17, count 0 2006.201.02:55:53.24#ibcon#read 5, iclass 17, count 0 2006.201.02:55:53.24#ibcon#about to read 6, iclass 17, count 0 2006.201.02:55:53.24#ibcon#read 6, iclass 17, count 0 2006.201.02:55:53.24#ibcon#end of sib2, iclass 17, count 0 2006.201.02:55:53.24#ibcon#*mode == 0, iclass 17, count 0 2006.201.02:55:53.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.02:55:53.24#ibcon#[27=USB\r\n] 2006.201.02:55:53.24#ibcon#*before write, iclass 17, count 0 2006.201.02:55:53.24#ibcon#enter sib2, iclass 17, count 0 2006.201.02:55:53.24#ibcon#flushed, iclass 17, count 0 2006.201.02:55:53.24#ibcon#about to write, iclass 17, count 0 2006.201.02:55:53.24#ibcon#wrote, iclass 17, count 0 2006.201.02:55:53.24#ibcon#about to read 3, iclass 17, count 0 2006.201.02:55:53.27#ibcon#read 3, iclass 17, count 0 2006.201.02:55:53.27#ibcon#about to read 4, iclass 17, count 0 2006.201.02:55:53.27#ibcon#read 4, iclass 17, count 0 2006.201.02:55:53.27#ibcon#about to read 5, iclass 17, count 0 2006.201.02:55:53.27#ibcon#read 5, iclass 17, count 0 2006.201.02:55:53.27#ibcon#about to read 6, iclass 17, count 0 2006.201.02:55:53.27#ibcon#read 6, iclass 17, count 0 2006.201.02:55:53.27#ibcon#end of sib2, iclass 17, count 0 2006.201.02:55:53.27#ibcon#*after write, iclass 17, count 0 2006.201.02:55:53.27#ibcon#*before return 0, iclass 17, count 0 2006.201.02:55:53.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:53.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.02:55:53.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.02:55:53.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.02:55:53.27$vck44/vblo=5,709.99 2006.201.02:55:53.27#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.02:55:53.27#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.02:55:53.27#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:53.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:53.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:53.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:53.27#ibcon#enter wrdev, iclass 19, count 0 2006.201.02:55:53.27#ibcon#first serial, iclass 19, count 0 2006.201.02:55:53.27#ibcon#enter sib2, iclass 19, count 0 2006.201.02:55:53.27#ibcon#flushed, iclass 19, count 0 2006.201.02:55:53.27#ibcon#about to write, iclass 19, count 0 2006.201.02:55:53.27#ibcon#wrote, iclass 19, count 0 2006.201.02:55:53.27#ibcon#about to read 3, iclass 19, count 0 2006.201.02:55:53.29#ibcon#read 3, iclass 19, count 0 2006.201.02:55:53.29#ibcon#about to read 4, iclass 19, count 0 2006.201.02:55:53.29#ibcon#read 4, iclass 19, count 0 2006.201.02:55:53.29#ibcon#about to read 5, iclass 19, count 0 2006.201.02:55:53.29#ibcon#read 5, iclass 19, count 0 2006.201.02:55:53.29#ibcon#about to read 6, iclass 19, count 0 2006.201.02:55:53.29#ibcon#read 6, iclass 19, count 0 2006.201.02:55:53.29#ibcon#end of sib2, iclass 19, count 0 2006.201.02:55:53.29#ibcon#*mode == 0, iclass 19, count 0 2006.201.02:55:53.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.02:55:53.29#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.02:55:53.29#ibcon#*before write, iclass 19, count 0 2006.201.02:55:53.29#ibcon#enter sib2, iclass 19, count 0 2006.201.02:55:53.29#ibcon#flushed, iclass 19, count 0 2006.201.02:55:53.29#ibcon#about to write, iclass 19, count 0 2006.201.02:55:53.29#ibcon#wrote, iclass 19, count 0 2006.201.02:55:53.29#ibcon#about to read 3, iclass 19, count 0 2006.201.02:55:53.33#ibcon#read 3, iclass 19, count 0 2006.201.02:55:53.33#ibcon#about to read 4, iclass 19, count 0 2006.201.02:55:53.33#ibcon#read 4, iclass 19, count 0 2006.201.02:55:53.33#ibcon#about to read 5, iclass 19, count 0 2006.201.02:55:53.33#ibcon#read 5, iclass 19, count 0 2006.201.02:55:53.33#ibcon#about to read 6, iclass 19, count 0 2006.201.02:55:53.33#ibcon#read 6, iclass 19, count 0 2006.201.02:55:53.33#ibcon#end of sib2, iclass 19, count 0 2006.201.02:55:53.33#ibcon#*after write, iclass 19, count 0 2006.201.02:55:53.33#ibcon#*before return 0, iclass 19, count 0 2006.201.02:55:53.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:53.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.02:55:53.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.02:55:53.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.02:55:53.33$vck44/vb=5,4 2006.201.02:55:53.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.02:55:53.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.02:55:53.33#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:53.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:53.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:53.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:53.39#ibcon#enter wrdev, iclass 21, count 2 2006.201.02:55:53.39#ibcon#first serial, iclass 21, count 2 2006.201.02:55:53.39#ibcon#enter sib2, iclass 21, count 2 2006.201.02:55:53.39#ibcon#flushed, iclass 21, count 2 2006.201.02:55:53.39#ibcon#about to write, iclass 21, count 2 2006.201.02:55:53.39#ibcon#wrote, iclass 21, count 2 2006.201.02:55:53.39#ibcon#about to read 3, iclass 21, count 2 2006.201.02:55:53.41#ibcon#read 3, iclass 21, count 2 2006.201.02:55:53.41#ibcon#about to read 4, iclass 21, count 2 2006.201.02:55:53.41#ibcon#read 4, iclass 21, count 2 2006.201.02:55:53.41#ibcon#about to read 5, iclass 21, count 2 2006.201.02:55:53.41#ibcon#read 5, iclass 21, count 2 2006.201.02:55:53.41#ibcon#about to read 6, iclass 21, count 2 2006.201.02:55:53.41#ibcon#read 6, iclass 21, count 2 2006.201.02:55:53.41#ibcon#end of sib2, iclass 21, count 2 2006.201.02:55:53.41#ibcon#*mode == 0, iclass 21, count 2 2006.201.02:55:53.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.02:55:53.41#ibcon#[27=AT05-04\r\n] 2006.201.02:55:53.41#ibcon#*before write, iclass 21, count 2 2006.201.02:55:53.41#ibcon#enter sib2, iclass 21, count 2 2006.201.02:55:53.41#ibcon#flushed, iclass 21, count 2 2006.201.02:55:53.41#ibcon#about to write, iclass 21, count 2 2006.201.02:55:53.41#ibcon#wrote, iclass 21, count 2 2006.201.02:55:53.41#ibcon#about to read 3, iclass 21, count 2 2006.201.02:55:53.45#ibcon#read 3, iclass 21, count 2 2006.201.02:55:53.45#ibcon#about to read 4, iclass 21, count 2 2006.201.02:55:53.45#ibcon#read 4, iclass 21, count 2 2006.201.02:55:53.45#ibcon#about to read 5, iclass 21, count 2 2006.201.02:55:53.45#ibcon#read 5, iclass 21, count 2 2006.201.02:55:53.45#ibcon#about to read 6, iclass 21, count 2 2006.201.02:55:53.45#ibcon#read 6, iclass 21, count 2 2006.201.02:55:53.45#ibcon#end of sib2, iclass 21, count 2 2006.201.02:55:53.45#ibcon#*after write, iclass 21, count 2 2006.201.02:55:53.45#ibcon#*before return 0, iclass 21, count 2 2006.201.02:55:53.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:53.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.02:55:53.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.02:55:53.45#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:53.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:53.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:53.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:53.57#ibcon#enter wrdev, iclass 21, count 0 2006.201.02:55:53.57#ibcon#first serial, iclass 21, count 0 2006.201.02:55:53.57#ibcon#enter sib2, iclass 21, count 0 2006.201.02:55:53.57#ibcon#flushed, iclass 21, count 0 2006.201.02:55:53.57#ibcon#about to write, iclass 21, count 0 2006.201.02:55:53.57#ibcon#wrote, iclass 21, count 0 2006.201.02:55:53.57#ibcon#about to read 3, iclass 21, count 0 2006.201.02:55:53.59#ibcon#read 3, iclass 21, count 0 2006.201.02:55:53.59#ibcon#about to read 4, iclass 21, count 0 2006.201.02:55:53.59#ibcon#read 4, iclass 21, count 0 2006.201.02:55:53.59#ibcon#about to read 5, iclass 21, count 0 2006.201.02:55:53.59#ibcon#read 5, iclass 21, count 0 2006.201.02:55:53.59#ibcon#about to read 6, iclass 21, count 0 2006.201.02:55:53.59#ibcon#read 6, iclass 21, count 0 2006.201.02:55:53.59#ibcon#end of sib2, iclass 21, count 0 2006.201.02:55:53.59#ibcon#*mode == 0, iclass 21, count 0 2006.201.02:55:53.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.02:55:53.59#ibcon#[27=USB\r\n] 2006.201.02:55:53.59#ibcon#*before write, iclass 21, count 0 2006.201.02:55:53.59#ibcon#enter sib2, iclass 21, count 0 2006.201.02:55:53.59#ibcon#flushed, iclass 21, count 0 2006.201.02:55:53.59#ibcon#about to write, iclass 21, count 0 2006.201.02:55:53.59#ibcon#wrote, iclass 21, count 0 2006.201.02:55:53.59#ibcon#about to read 3, iclass 21, count 0 2006.201.02:55:53.62#ibcon#read 3, iclass 21, count 0 2006.201.02:55:53.62#ibcon#about to read 4, iclass 21, count 0 2006.201.02:55:53.62#ibcon#read 4, iclass 21, count 0 2006.201.02:55:53.62#ibcon#about to read 5, iclass 21, count 0 2006.201.02:55:53.62#ibcon#read 5, iclass 21, count 0 2006.201.02:55:53.62#ibcon#about to read 6, iclass 21, count 0 2006.201.02:55:53.62#ibcon#read 6, iclass 21, count 0 2006.201.02:55:53.62#ibcon#end of sib2, iclass 21, count 0 2006.201.02:55:53.62#ibcon#*after write, iclass 21, count 0 2006.201.02:55:53.62#ibcon#*before return 0, iclass 21, count 0 2006.201.02:55:53.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:53.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.02:55:53.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.02:55:53.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.02:55:53.62$vck44/vblo=6,719.99 2006.201.02:55:53.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.02:55:53.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.02:55:53.62#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:53.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:55:53.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:55:53.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:55:53.62#ibcon#enter wrdev, iclass 23, count 0 2006.201.02:55:53.62#ibcon#first serial, iclass 23, count 0 2006.201.02:55:53.62#ibcon#enter sib2, iclass 23, count 0 2006.201.02:55:53.62#ibcon#flushed, iclass 23, count 0 2006.201.02:55:53.62#ibcon#about to write, iclass 23, count 0 2006.201.02:55:53.62#ibcon#wrote, iclass 23, count 0 2006.201.02:55:53.62#ibcon#about to read 3, iclass 23, count 0 2006.201.02:55:53.64#ibcon#read 3, iclass 23, count 0 2006.201.02:55:53.64#ibcon#about to read 4, iclass 23, count 0 2006.201.02:55:53.64#ibcon#read 4, iclass 23, count 0 2006.201.02:55:53.64#ibcon#about to read 5, iclass 23, count 0 2006.201.02:55:53.64#ibcon#read 5, iclass 23, count 0 2006.201.02:55:53.64#ibcon#about to read 6, iclass 23, count 0 2006.201.02:55:53.64#ibcon#read 6, iclass 23, count 0 2006.201.02:55:53.64#ibcon#end of sib2, iclass 23, count 0 2006.201.02:55:53.64#ibcon#*mode == 0, iclass 23, count 0 2006.201.02:55:53.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.02:55:53.64#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.02:55:53.64#ibcon#*before write, iclass 23, count 0 2006.201.02:55:53.64#ibcon#enter sib2, iclass 23, count 0 2006.201.02:55:53.64#ibcon#flushed, iclass 23, count 0 2006.201.02:55:53.64#ibcon#about to write, iclass 23, count 0 2006.201.02:55:53.64#ibcon#wrote, iclass 23, count 0 2006.201.02:55:53.64#ibcon#about to read 3, iclass 23, count 0 2006.201.02:55:53.68#ibcon#read 3, iclass 23, count 0 2006.201.02:55:53.68#ibcon#about to read 4, iclass 23, count 0 2006.201.02:55:53.68#ibcon#read 4, iclass 23, count 0 2006.201.02:55:53.68#ibcon#about to read 5, iclass 23, count 0 2006.201.02:55:53.68#ibcon#read 5, iclass 23, count 0 2006.201.02:55:53.68#ibcon#about to read 6, iclass 23, count 0 2006.201.02:55:53.68#ibcon#read 6, iclass 23, count 0 2006.201.02:55:53.68#ibcon#end of sib2, iclass 23, count 0 2006.201.02:55:53.68#ibcon#*after write, iclass 23, count 0 2006.201.02:55:53.68#ibcon#*before return 0, iclass 23, count 0 2006.201.02:55:53.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:55:53.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.02:55:53.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.02:55:53.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.02:55:53.68$vck44/vb=6,4 2006.201.02:55:53.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.02:55:53.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.02:55:53.68#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:53.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:55:53.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:55:53.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:55:53.74#ibcon#enter wrdev, iclass 25, count 2 2006.201.02:55:53.74#ibcon#first serial, iclass 25, count 2 2006.201.02:55:53.74#ibcon#enter sib2, iclass 25, count 2 2006.201.02:55:53.74#ibcon#flushed, iclass 25, count 2 2006.201.02:55:53.74#ibcon#about to write, iclass 25, count 2 2006.201.02:55:53.74#ibcon#wrote, iclass 25, count 2 2006.201.02:55:53.74#ibcon#about to read 3, iclass 25, count 2 2006.201.02:55:53.76#ibcon#read 3, iclass 25, count 2 2006.201.02:55:53.76#ibcon#about to read 4, iclass 25, count 2 2006.201.02:55:53.76#ibcon#read 4, iclass 25, count 2 2006.201.02:55:53.76#ibcon#about to read 5, iclass 25, count 2 2006.201.02:55:53.76#ibcon#read 5, iclass 25, count 2 2006.201.02:55:53.76#ibcon#about to read 6, iclass 25, count 2 2006.201.02:55:53.76#ibcon#read 6, iclass 25, count 2 2006.201.02:55:53.76#ibcon#end of sib2, iclass 25, count 2 2006.201.02:55:53.76#ibcon#*mode == 0, iclass 25, count 2 2006.201.02:55:53.76#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.02:55:53.76#ibcon#[27=AT06-04\r\n] 2006.201.02:55:53.76#ibcon#*before write, iclass 25, count 2 2006.201.02:55:53.76#ibcon#enter sib2, iclass 25, count 2 2006.201.02:55:53.76#ibcon#flushed, iclass 25, count 2 2006.201.02:55:53.76#ibcon#about to write, iclass 25, count 2 2006.201.02:55:53.76#ibcon#wrote, iclass 25, count 2 2006.201.02:55:53.76#ibcon#about to read 3, iclass 25, count 2 2006.201.02:55:53.79#ibcon#read 3, iclass 25, count 2 2006.201.02:55:53.79#ibcon#about to read 4, iclass 25, count 2 2006.201.02:55:53.79#ibcon#read 4, iclass 25, count 2 2006.201.02:55:53.79#ibcon#about to read 5, iclass 25, count 2 2006.201.02:55:53.79#ibcon#read 5, iclass 25, count 2 2006.201.02:55:53.79#ibcon#about to read 6, iclass 25, count 2 2006.201.02:55:53.79#ibcon#read 6, iclass 25, count 2 2006.201.02:55:53.79#ibcon#end of sib2, iclass 25, count 2 2006.201.02:55:53.79#ibcon#*after write, iclass 25, count 2 2006.201.02:55:53.79#ibcon#*before return 0, iclass 25, count 2 2006.201.02:55:53.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:55:53.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.02:55:53.79#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.02:55:53.79#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:53.79#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:55:53.91#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:55:53.91#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:55:53.91#ibcon#enter wrdev, iclass 25, count 0 2006.201.02:55:53.91#ibcon#first serial, iclass 25, count 0 2006.201.02:55:53.91#ibcon#enter sib2, iclass 25, count 0 2006.201.02:55:53.91#ibcon#flushed, iclass 25, count 0 2006.201.02:55:53.91#ibcon#about to write, iclass 25, count 0 2006.201.02:55:53.91#ibcon#wrote, iclass 25, count 0 2006.201.02:55:53.91#ibcon#about to read 3, iclass 25, count 0 2006.201.02:55:53.93#ibcon#read 3, iclass 25, count 0 2006.201.02:55:53.93#ibcon#about to read 4, iclass 25, count 0 2006.201.02:55:53.93#ibcon#read 4, iclass 25, count 0 2006.201.02:55:53.93#ibcon#about to read 5, iclass 25, count 0 2006.201.02:55:53.93#ibcon#read 5, iclass 25, count 0 2006.201.02:55:53.93#ibcon#about to read 6, iclass 25, count 0 2006.201.02:55:53.93#ibcon#read 6, iclass 25, count 0 2006.201.02:55:53.93#ibcon#end of sib2, iclass 25, count 0 2006.201.02:55:53.93#ibcon#*mode == 0, iclass 25, count 0 2006.201.02:55:53.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.02:55:53.93#ibcon#[27=USB\r\n] 2006.201.02:55:53.93#ibcon#*before write, iclass 25, count 0 2006.201.02:55:53.93#ibcon#enter sib2, iclass 25, count 0 2006.201.02:55:53.93#ibcon#flushed, iclass 25, count 0 2006.201.02:55:53.93#ibcon#about to write, iclass 25, count 0 2006.201.02:55:53.93#ibcon#wrote, iclass 25, count 0 2006.201.02:55:53.93#ibcon#about to read 3, iclass 25, count 0 2006.201.02:55:53.96#ibcon#read 3, iclass 25, count 0 2006.201.02:55:53.96#ibcon#about to read 4, iclass 25, count 0 2006.201.02:55:53.96#ibcon#read 4, iclass 25, count 0 2006.201.02:55:53.96#ibcon#about to read 5, iclass 25, count 0 2006.201.02:55:53.96#ibcon#read 5, iclass 25, count 0 2006.201.02:55:53.96#ibcon#about to read 6, iclass 25, count 0 2006.201.02:55:53.96#ibcon#read 6, iclass 25, count 0 2006.201.02:55:53.96#ibcon#end of sib2, iclass 25, count 0 2006.201.02:55:53.96#ibcon#*after write, iclass 25, count 0 2006.201.02:55:53.96#ibcon#*before return 0, iclass 25, count 0 2006.201.02:55:53.96#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:55:53.96#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.02:55:53.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.02:55:53.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.02:55:53.96$vck44/vblo=7,734.99 2006.201.02:55:53.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.02:55:53.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.02:55:53.96#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:53.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:53.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:53.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:53.96#ibcon#enter wrdev, iclass 27, count 0 2006.201.02:55:53.96#ibcon#first serial, iclass 27, count 0 2006.201.02:55:53.96#ibcon#enter sib2, iclass 27, count 0 2006.201.02:55:53.96#ibcon#flushed, iclass 27, count 0 2006.201.02:55:53.96#ibcon#about to write, iclass 27, count 0 2006.201.02:55:53.96#ibcon#wrote, iclass 27, count 0 2006.201.02:55:53.96#ibcon#about to read 3, iclass 27, count 0 2006.201.02:55:53.98#ibcon#read 3, iclass 27, count 0 2006.201.02:55:53.98#ibcon#about to read 4, iclass 27, count 0 2006.201.02:55:53.98#ibcon#read 4, iclass 27, count 0 2006.201.02:55:53.98#ibcon#about to read 5, iclass 27, count 0 2006.201.02:55:53.98#ibcon#read 5, iclass 27, count 0 2006.201.02:55:53.98#ibcon#about to read 6, iclass 27, count 0 2006.201.02:55:53.98#ibcon#read 6, iclass 27, count 0 2006.201.02:55:53.98#ibcon#end of sib2, iclass 27, count 0 2006.201.02:55:53.98#ibcon#*mode == 0, iclass 27, count 0 2006.201.02:55:53.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.02:55:53.98#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.02:55:53.98#ibcon#*before write, iclass 27, count 0 2006.201.02:55:53.98#ibcon#enter sib2, iclass 27, count 0 2006.201.02:55:53.98#ibcon#flushed, iclass 27, count 0 2006.201.02:55:53.98#ibcon#about to write, iclass 27, count 0 2006.201.02:55:53.98#ibcon#wrote, iclass 27, count 0 2006.201.02:55:53.98#ibcon#about to read 3, iclass 27, count 0 2006.201.02:55:54.02#ibcon#read 3, iclass 27, count 0 2006.201.02:55:54.02#ibcon#about to read 4, iclass 27, count 0 2006.201.02:55:54.02#ibcon#read 4, iclass 27, count 0 2006.201.02:55:54.02#ibcon#about to read 5, iclass 27, count 0 2006.201.02:55:54.02#ibcon#read 5, iclass 27, count 0 2006.201.02:55:54.02#ibcon#about to read 6, iclass 27, count 0 2006.201.02:55:54.02#ibcon#read 6, iclass 27, count 0 2006.201.02:55:54.02#ibcon#end of sib2, iclass 27, count 0 2006.201.02:55:54.02#ibcon#*after write, iclass 27, count 0 2006.201.02:55:54.02#ibcon#*before return 0, iclass 27, count 0 2006.201.02:55:54.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:54.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.02:55:54.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.02:55:54.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.02:55:54.02$vck44/vb=7,4 2006.201.02:55:54.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.02:55:54.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.02:55:54.02#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:54.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:54.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:54.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:54.08#ibcon#enter wrdev, iclass 29, count 2 2006.201.02:55:54.08#ibcon#first serial, iclass 29, count 2 2006.201.02:55:54.08#ibcon#enter sib2, iclass 29, count 2 2006.201.02:55:54.08#ibcon#flushed, iclass 29, count 2 2006.201.02:55:54.08#ibcon#about to write, iclass 29, count 2 2006.201.02:55:54.08#ibcon#wrote, iclass 29, count 2 2006.201.02:55:54.08#ibcon#about to read 3, iclass 29, count 2 2006.201.02:55:54.10#ibcon#read 3, iclass 29, count 2 2006.201.02:55:54.10#ibcon#about to read 4, iclass 29, count 2 2006.201.02:55:54.10#ibcon#read 4, iclass 29, count 2 2006.201.02:55:54.10#ibcon#about to read 5, iclass 29, count 2 2006.201.02:55:54.10#ibcon#read 5, iclass 29, count 2 2006.201.02:55:54.10#ibcon#about to read 6, iclass 29, count 2 2006.201.02:55:54.10#ibcon#read 6, iclass 29, count 2 2006.201.02:55:54.10#ibcon#end of sib2, iclass 29, count 2 2006.201.02:55:54.10#ibcon#*mode == 0, iclass 29, count 2 2006.201.02:55:54.10#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.02:55:54.10#ibcon#[27=AT07-04\r\n] 2006.201.02:55:54.10#ibcon#*before write, iclass 29, count 2 2006.201.02:55:54.10#ibcon#enter sib2, iclass 29, count 2 2006.201.02:55:54.10#ibcon#flushed, iclass 29, count 2 2006.201.02:55:54.10#ibcon#about to write, iclass 29, count 2 2006.201.02:55:54.10#ibcon#wrote, iclass 29, count 2 2006.201.02:55:54.10#ibcon#about to read 3, iclass 29, count 2 2006.201.02:55:54.13#ibcon#read 3, iclass 29, count 2 2006.201.02:55:54.13#ibcon#about to read 4, iclass 29, count 2 2006.201.02:55:54.13#ibcon#read 4, iclass 29, count 2 2006.201.02:55:54.13#ibcon#about to read 5, iclass 29, count 2 2006.201.02:55:54.13#ibcon#read 5, iclass 29, count 2 2006.201.02:55:54.13#ibcon#about to read 6, iclass 29, count 2 2006.201.02:55:54.13#ibcon#read 6, iclass 29, count 2 2006.201.02:55:54.13#ibcon#end of sib2, iclass 29, count 2 2006.201.02:55:54.13#ibcon#*after write, iclass 29, count 2 2006.201.02:55:54.13#ibcon#*before return 0, iclass 29, count 2 2006.201.02:55:54.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:54.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.02:55:54.13#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.02:55:54.13#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:54.13#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:54.25#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:54.25#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:54.25#ibcon#enter wrdev, iclass 29, count 0 2006.201.02:55:54.25#ibcon#first serial, iclass 29, count 0 2006.201.02:55:54.25#ibcon#enter sib2, iclass 29, count 0 2006.201.02:55:54.25#ibcon#flushed, iclass 29, count 0 2006.201.02:55:54.25#ibcon#about to write, iclass 29, count 0 2006.201.02:55:54.25#ibcon#wrote, iclass 29, count 0 2006.201.02:55:54.25#ibcon#about to read 3, iclass 29, count 0 2006.201.02:55:54.27#ibcon#read 3, iclass 29, count 0 2006.201.02:55:54.27#ibcon#about to read 4, iclass 29, count 0 2006.201.02:55:54.27#ibcon#read 4, iclass 29, count 0 2006.201.02:55:54.27#ibcon#about to read 5, iclass 29, count 0 2006.201.02:55:54.27#ibcon#read 5, iclass 29, count 0 2006.201.02:55:54.27#ibcon#about to read 6, iclass 29, count 0 2006.201.02:55:54.27#ibcon#read 6, iclass 29, count 0 2006.201.02:55:54.27#ibcon#end of sib2, iclass 29, count 0 2006.201.02:55:54.27#ibcon#*mode == 0, iclass 29, count 0 2006.201.02:55:54.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.02:55:54.27#ibcon#[27=USB\r\n] 2006.201.02:55:54.27#ibcon#*before write, iclass 29, count 0 2006.201.02:55:54.27#ibcon#enter sib2, iclass 29, count 0 2006.201.02:55:54.27#ibcon#flushed, iclass 29, count 0 2006.201.02:55:54.27#ibcon#about to write, iclass 29, count 0 2006.201.02:55:54.27#ibcon#wrote, iclass 29, count 0 2006.201.02:55:54.27#ibcon#about to read 3, iclass 29, count 0 2006.201.02:55:54.30#ibcon#read 3, iclass 29, count 0 2006.201.02:55:54.30#ibcon#about to read 4, iclass 29, count 0 2006.201.02:55:54.30#ibcon#read 4, iclass 29, count 0 2006.201.02:55:54.30#ibcon#about to read 5, iclass 29, count 0 2006.201.02:55:54.30#ibcon#read 5, iclass 29, count 0 2006.201.02:55:54.30#ibcon#about to read 6, iclass 29, count 0 2006.201.02:55:54.30#ibcon#read 6, iclass 29, count 0 2006.201.02:55:54.30#ibcon#end of sib2, iclass 29, count 0 2006.201.02:55:54.30#ibcon#*after write, iclass 29, count 0 2006.201.02:55:54.30#ibcon#*before return 0, iclass 29, count 0 2006.201.02:55:54.30#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:54.30#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.02:55:54.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.02:55:54.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.02:55:54.30$vck44/vblo=8,744.99 2006.201.02:55:54.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.02:55:54.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.02:55:54.30#ibcon#ireg 17 cls_cnt 0 2006.201.02:55:54.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:54.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:54.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:54.30#ibcon#enter wrdev, iclass 31, count 0 2006.201.02:55:54.30#ibcon#first serial, iclass 31, count 0 2006.201.02:55:54.30#ibcon#enter sib2, iclass 31, count 0 2006.201.02:55:54.30#ibcon#flushed, iclass 31, count 0 2006.201.02:55:54.30#ibcon#about to write, iclass 31, count 0 2006.201.02:55:54.30#ibcon#wrote, iclass 31, count 0 2006.201.02:55:54.30#ibcon#about to read 3, iclass 31, count 0 2006.201.02:55:54.32#ibcon#read 3, iclass 31, count 0 2006.201.02:55:54.32#ibcon#about to read 4, iclass 31, count 0 2006.201.02:55:54.32#ibcon#read 4, iclass 31, count 0 2006.201.02:55:54.32#ibcon#about to read 5, iclass 31, count 0 2006.201.02:55:54.32#ibcon#read 5, iclass 31, count 0 2006.201.02:55:54.32#ibcon#about to read 6, iclass 31, count 0 2006.201.02:55:54.32#ibcon#read 6, iclass 31, count 0 2006.201.02:55:54.32#ibcon#end of sib2, iclass 31, count 0 2006.201.02:55:54.32#ibcon#*mode == 0, iclass 31, count 0 2006.201.02:55:54.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.02:55:54.32#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.02:55:54.32#ibcon#*before write, iclass 31, count 0 2006.201.02:55:54.32#ibcon#enter sib2, iclass 31, count 0 2006.201.02:55:54.32#ibcon#flushed, iclass 31, count 0 2006.201.02:55:54.32#ibcon#about to write, iclass 31, count 0 2006.201.02:55:54.32#ibcon#wrote, iclass 31, count 0 2006.201.02:55:54.32#ibcon#about to read 3, iclass 31, count 0 2006.201.02:55:54.36#ibcon#read 3, iclass 31, count 0 2006.201.02:55:54.36#ibcon#about to read 4, iclass 31, count 0 2006.201.02:55:54.36#ibcon#read 4, iclass 31, count 0 2006.201.02:55:54.36#ibcon#about to read 5, iclass 31, count 0 2006.201.02:55:54.36#ibcon#read 5, iclass 31, count 0 2006.201.02:55:54.36#ibcon#about to read 6, iclass 31, count 0 2006.201.02:55:54.36#ibcon#read 6, iclass 31, count 0 2006.201.02:55:54.36#ibcon#end of sib2, iclass 31, count 0 2006.201.02:55:54.36#ibcon#*after write, iclass 31, count 0 2006.201.02:55:54.36#ibcon#*before return 0, iclass 31, count 0 2006.201.02:55:54.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:54.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.02:55:54.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.02:55:54.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.02:55:54.36$vck44/vb=8,4 2006.201.02:55:54.36#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.02:55:54.36#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.02:55:54.36#ibcon#ireg 11 cls_cnt 2 2006.201.02:55:54.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:54.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:54.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:54.42#ibcon#enter wrdev, iclass 33, count 2 2006.201.02:55:54.42#ibcon#first serial, iclass 33, count 2 2006.201.02:55:54.42#ibcon#enter sib2, iclass 33, count 2 2006.201.02:55:54.42#ibcon#flushed, iclass 33, count 2 2006.201.02:55:54.42#ibcon#about to write, iclass 33, count 2 2006.201.02:55:54.42#ibcon#wrote, iclass 33, count 2 2006.201.02:55:54.42#ibcon#about to read 3, iclass 33, count 2 2006.201.02:55:54.44#ibcon#read 3, iclass 33, count 2 2006.201.02:55:54.44#ibcon#about to read 4, iclass 33, count 2 2006.201.02:55:54.44#ibcon#read 4, iclass 33, count 2 2006.201.02:55:54.44#ibcon#about to read 5, iclass 33, count 2 2006.201.02:55:54.44#ibcon#read 5, iclass 33, count 2 2006.201.02:55:54.44#ibcon#about to read 6, iclass 33, count 2 2006.201.02:55:54.44#ibcon#read 6, iclass 33, count 2 2006.201.02:55:54.44#ibcon#end of sib2, iclass 33, count 2 2006.201.02:55:54.44#ibcon#*mode == 0, iclass 33, count 2 2006.201.02:55:54.44#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.02:55:54.44#ibcon#[27=AT08-04\r\n] 2006.201.02:55:54.44#ibcon#*before write, iclass 33, count 2 2006.201.02:55:54.44#ibcon#enter sib2, iclass 33, count 2 2006.201.02:55:54.44#ibcon#flushed, iclass 33, count 2 2006.201.02:55:54.44#ibcon#about to write, iclass 33, count 2 2006.201.02:55:54.44#ibcon#wrote, iclass 33, count 2 2006.201.02:55:54.44#ibcon#about to read 3, iclass 33, count 2 2006.201.02:55:54.47#ibcon#read 3, iclass 33, count 2 2006.201.02:55:54.47#ibcon#about to read 4, iclass 33, count 2 2006.201.02:55:54.47#ibcon#read 4, iclass 33, count 2 2006.201.02:55:54.47#ibcon#about to read 5, iclass 33, count 2 2006.201.02:55:54.47#ibcon#read 5, iclass 33, count 2 2006.201.02:55:54.47#ibcon#about to read 6, iclass 33, count 2 2006.201.02:55:54.47#ibcon#read 6, iclass 33, count 2 2006.201.02:55:54.47#ibcon#end of sib2, iclass 33, count 2 2006.201.02:55:54.47#ibcon#*after write, iclass 33, count 2 2006.201.02:55:54.47#ibcon#*before return 0, iclass 33, count 2 2006.201.02:55:54.47#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:54.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.02:55:54.47#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.02:55:54.47#ibcon#ireg 7 cls_cnt 0 2006.201.02:55:54.47#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:54.59#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:54.59#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:54.59#ibcon#enter wrdev, iclass 33, count 0 2006.201.02:55:54.59#ibcon#first serial, iclass 33, count 0 2006.201.02:55:54.59#ibcon#enter sib2, iclass 33, count 0 2006.201.02:55:54.59#ibcon#flushed, iclass 33, count 0 2006.201.02:55:54.59#ibcon#about to write, iclass 33, count 0 2006.201.02:55:54.59#ibcon#wrote, iclass 33, count 0 2006.201.02:55:54.59#ibcon#about to read 3, iclass 33, count 0 2006.201.02:55:54.61#ibcon#read 3, iclass 33, count 0 2006.201.02:55:54.61#ibcon#about to read 4, iclass 33, count 0 2006.201.02:55:54.61#ibcon#read 4, iclass 33, count 0 2006.201.02:55:54.61#ibcon#about to read 5, iclass 33, count 0 2006.201.02:55:54.61#ibcon#read 5, iclass 33, count 0 2006.201.02:55:54.61#ibcon#about to read 6, iclass 33, count 0 2006.201.02:55:54.61#ibcon#read 6, iclass 33, count 0 2006.201.02:55:54.61#ibcon#end of sib2, iclass 33, count 0 2006.201.02:55:54.61#ibcon#*mode == 0, iclass 33, count 0 2006.201.02:55:54.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.02:55:54.61#ibcon#[27=USB\r\n] 2006.201.02:55:54.61#ibcon#*before write, iclass 33, count 0 2006.201.02:55:54.61#ibcon#enter sib2, iclass 33, count 0 2006.201.02:55:54.61#ibcon#flushed, iclass 33, count 0 2006.201.02:55:54.61#ibcon#about to write, iclass 33, count 0 2006.201.02:55:54.61#ibcon#wrote, iclass 33, count 0 2006.201.02:55:54.61#ibcon#about to read 3, iclass 33, count 0 2006.201.02:55:54.64#ibcon#read 3, iclass 33, count 0 2006.201.02:55:54.64#ibcon#about to read 4, iclass 33, count 0 2006.201.02:55:54.64#ibcon#read 4, iclass 33, count 0 2006.201.02:55:54.64#ibcon#about to read 5, iclass 33, count 0 2006.201.02:55:54.64#ibcon#read 5, iclass 33, count 0 2006.201.02:55:54.64#ibcon#about to read 6, iclass 33, count 0 2006.201.02:55:54.64#ibcon#read 6, iclass 33, count 0 2006.201.02:55:54.64#ibcon#end of sib2, iclass 33, count 0 2006.201.02:55:54.64#ibcon#*after write, iclass 33, count 0 2006.201.02:55:54.64#ibcon#*before return 0, iclass 33, count 0 2006.201.02:55:54.64#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:54.64#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.02:55:54.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.02:55:54.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.02:55:54.64$vck44/vabw=wide 2006.201.02:55:54.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.02:55:54.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.02:55:54.64#ibcon#ireg 8 cls_cnt 0 2006.201.02:55:54.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:54.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:54.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:54.64#ibcon#enter wrdev, iclass 35, count 0 2006.201.02:55:54.64#ibcon#first serial, iclass 35, count 0 2006.201.02:55:54.64#ibcon#enter sib2, iclass 35, count 0 2006.201.02:55:54.64#ibcon#flushed, iclass 35, count 0 2006.201.02:55:54.64#ibcon#about to write, iclass 35, count 0 2006.201.02:55:54.64#ibcon#wrote, iclass 35, count 0 2006.201.02:55:54.64#ibcon#about to read 3, iclass 35, count 0 2006.201.02:55:54.66#ibcon#read 3, iclass 35, count 0 2006.201.02:55:54.66#ibcon#about to read 4, iclass 35, count 0 2006.201.02:55:54.66#ibcon#read 4, iclass 35, count 0 2006.201.02:55:54.66#ibcon#about to read 5, iclass 35, count 0 2006.201.02:55:54.66#ibcon#read 5, iclass 35, count 0 2006.201.02:55:54.66#ibcon#about to read 6, iclass 35, count 0 2006.201.02:55:54.66#ibcon#read 6, iclass 35, count 0 2006.201.02:55:54.66#ibcon#end of sib2, iclass 35, count 0 2006.201.02:55:54.66#ibcon#*mode == 0, iclass 35, count 0 2006.201.02:55:54.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.02:55:54.66#ibcon#[25=BW32\r\n] 2006.201.02:55:54.66#ibcon#*before write, iclass 35, count 0 2006.201.02:55:54.66#ibcon#enter sib2, iclass 35, count 0 2006.201.02:55:54.66#ibcon#flushed, iclass 35, count 0 2006.201.02:55:54.66#ibcon#about to write, iclass 35, count 0 2006.201.02:55:54.66#ibcon#wrote, iclass 35, count 0 2006.201.02:55:54.66#ibcon#about to read 3, iclass 35, count 0 2006.201.02:55:54.69#ibcon#read 3, iclass 35, count 0 2006.201.02:55:54.69#ibcon#about to read 4, iclass 35, count 0 2006.201.02:55:54.69#ibcon#read 4, iclass 35, count 0 2006.201.02:55:54.69#ibcon#about to read 5, iclass 35, count 0 2006.201.02:55:54.69#ibcon#read 5, iclass 35, count 0 2006.201.02:55:54.69#ibcon#about to read 6, iclass 35, count 0 2006.201.02:55:54.69#ibcon#read 6, iclass 35, count 0 2006.201.02:55:54.69#ibcon#end of sib2, iclass 35, count 0 2006.201.02:55:54.69#ibcon#*after write, iclass 35, count 0 2006.201.02:55:54.69#ibcon#*before return 0, iclass 35, count 0 2006.201.02:55:54.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:54.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.02:55:54.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.02:55:54.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.02:55:54.69$vck44/vbbw=wide 2006.201.02:55:54.69#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.02:55:54.69#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.02:55:54.69#ibcon#ireg 8 cls_cnt 0 2006.201.02:55:54.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:55:54.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:55:54.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:55:54.76#ibcon#enter wrdev, iclass 37, count 0 2006.201.02:55:54.76#ibcon#first serial, iclass 37, count 0 2006.201.02:55:54.76#ibcon#enter sib2, iclass 37, count 0 2006.201.02:55:54.76#ibcon#flushed, iclass 37, count 0 2006.201.02:55:54.76#ibcon#about to write, iclass 37, count 0 2006.201.02:55:54.76#ibcon#wrote, iclass 37, count 0 2006.201.02:55:54.76#ibcon#about to read 3, iclass 37, count 0 2006.201.02:55:54.78#ibcon#read 3, iclass 37, count 0 2006.201.02:55:54.78#ibcon#about to read 4, iclass 37, count 0 2006.201.02:55:54.78#ibcon#read 4, iclass 37, count 0 2006.201.02:55:54.78#ibcon#about to read 5, iclass 37, count 0 2006.201.02:55:54.78#ibcon#read 5, iclass 37, count 0 2006.201.02:55:54.78#ibcon#about to read 6, iclass 37, count 0 2006.201.02:55:54.78#ibcon#read 6, iclass 37, count 0 2006.201.02:55:54.78#ibcon#end of sib2, iclass 37, count 0 2006.201.02:55:54.78#ibcon#*mode == 0, iclass 37, count 0 2006.201.02:55:54.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.02:55:54.78#ibcon#[27=BW32\r\n] 2006.201.02:55:54.78#ibcon#*before write, iclass 37, count 0 2006.201.02:55:54.78#ibcon#enter sib2, iclass 37, count 0 2006.201.02:55:54.78#ibcon#flushed, iclass 37, count 0 2006.201.02:55:54.78#ibcon#about to write, iclass 37, count 0 2006.201.02:55:54.78#ibcon#wrote, iclass 37, count 0 2006.201.02:55:54.78#ibcon#about to read 3, iclass 37, count 0 2006.201.02:55:54.81#ibcon#read 3, iclass 37, count 0 2006.201.02:55:54.81#ibcon#about to read 4, iclass 37, count 0 2006.201.02:55:54.81#ibcon#read 4, iclass 37, count 0 2006.201.02:55:54.81#ibcon#about to read 5, iclass 37, count 0 2006.201.02:55:54.81#ibcon#read 5, iclass 37, count 0 2006.201.02:55:54.81#ibcon#about to read 6, iclass 37, count 0 2006.201.02:55:54.81#ibcon#read 6, iclass 37, count 0 2006.201.02:55:54.81#ibcon#end of sib2, iclass 37, count 0 2006.201.02:55:54.81#ibcon#*after write, iclass 37, count 0 2006.201.02:55:54.81#ibcon#*before return 0, iclass 37, count 0 2006.201.02:55:54.81#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:55:54.81#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.02:55:54.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.02:55:54.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.02:55:54.81$setupk4/ifdk4 2006.201.02:55:54.81$ifdk4/lo= 2006.201.02:55:54.81$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.02:55:54.81$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.02:55:54.81$ifdk4/patch= 2006.201.02:55:54.81$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.02:55:54.81$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.02:55:54.81$setupk4/!*+20s 2006.201.02:56:00.93#abcon#<5=/02 1.8 3.8 22.86 951004.5\r\n> 2006.201.02:56:00.95#abcon#{5=INTERFACE CLEAR} 2006.201.02:56:01.02#abcon#[5=S1D000X0/0*\r\n] 2006.201.02:56:05.14#trakl#Source acquired 2006.201.02:56:05.14#flagr#flagr/antenna,acquired 2006.201.02:56:09.25$setupk4/"tpicd 2006.201.02:56:09.25$setupk4/echo=off 2006.201.02:56:09.25$setupk4/xlog=off 2006.201.02:56:09.25:!2006.201.03:00:36 2006.201.03:00:36.00:preob 2006.201.03:00:36.14/onsource/TRACKING 2006.201.03:00:36.14:!2006.201.03:00:46 2006.201.03:00:46.00:"tape 2006.201.03:00:46.00:"st=record 2006.201.03:00:46.00:data_valid=on 2006.201.03:00:46.00:midob 2006.201.03:00:47.14/onsource/TRACKING 2006.201.03:00:47.14/wx/22.87,1004.5,95 2006.201.03:00:47.32/cable/+6.4664E-03 2006.201.03:00:48.41/va/01,08,usb,yes,29,31 2006.201.03:00:48.41/va/02,07,usb,yes,31,32 2006.201.03:00:48.41/va/03,08,usb,yes,28,30 2006.201.03:00:48.41/va/04,07,usb,yes,32,34 2006.201.03:00:48.41/va/05,04,usb,yes,28,29 2006.201.03:00:48.41/va/06,05,usb,yes,28,28 2006.201.03:00:48.41/va/07,05,usb,yes,28,29 2006.201.03:00:48.41/va/08,04,usb,yes,27,33 2006.201.03:00:48.64/valo/01,524.99,yes,locked 2006.201.03:00:48.64/valo/02,534.99,yes,locked 2006.201.03:00:48.64/valo/03,564.99,yes,locked 2006.201.03:00:48.64/valo/04,624.99,yes,locked 2006.201.03:00:48.64/valo/05,734.99,yes,locked 2006.201.03:00:48.64/valo/06,814.99,yes,locked 2006.201.03:00:48.64/valo/07,864.99,yes,locked 2006.201.03:00:48.64/valo/08,884.99,yes,locked 2006.201.03:00:49.73/vb/01,04,usb,yes,29,27 2006.201.03:00:49.73/vb/02,05,usb,yes,27,27 2006.201.03:00:49.73/vb/03,04,usb,yes,28,31 2006.201.03:00:49.73/vb/04,05,usb,yes,29,28 2006.201.03:00:49.73/vb/05,04,usb,yes,25,28 2006.201.03:00:49.73/vb/06,04,usb,yes,30,26 2006.201.03:00:49.73/vb/07,04,usb,yes,29,29 2006.201.03:00:49.73/vb/08,04,usb,yes,27,30 2006.201.03:00:49.96/vblo/01,629.99,yes,locked 2006.201.03:00:49.96/vblo/02,634.99,yes,locked 2006.201.03:00:49.96/vblo/03,649.99,yes,locked 2006.201.03:00:49.96/vblo/04,679.99,yes,locked 2006.201.03:00:49.96/vblo/05,709.99,yes,locked 2006.201.03:00:49.96/vblo/06,719.99,yes,locked 2006.201.03:00:49.96/vblo/07,734.99,yes,locked 2006.201.03:00:49.96/vblo/08,744.99,yes,locked 2006.201.03:00:50.11/vabw/8 2006.201.03:00:50.26/vbbw/8 2006.201.03:00:50.35/xfe/off,on,15.0 2006.201.03:00:50.72/ifatt/23,28,28,28 2006.201.03:00:51.04/fmout-gps/S +4.48E-07 2006.201.03:00:51.11:!2006.201.03:04:36 2006.201.03:04:36.00:data_valid=off 2006.201.03:04:36.00:"et 2006.201.03:04:36.00:!+3s 2006.201.03:04:39.02:"tape 2006.201.03:04:39.02:postob 2006.201.03:04:39.12/cable/+6.4685E-03 2006.201.03:04:39.12/wx/22.86,1004.5,94 2006.201.03:04:39.18/fmout-gps/S +4.47E-07 2006.201.03:04:39.18:scan_name=201-0314,jd0607,390 2006.201.03:04:39.18:source=1308+326,131028.66,322043.8,2000.0,cw 2006.201.03:04:40.14#flagr#flagr/antenna,new-source 2006.201.03:04:40.14:checkk5 2006.201.03:04:40.59/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:04:41.00/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:04:41.42/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:04:41.81/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:04:42.18/chk_obsdata//k5ts1/T2010300??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.03:04:42.59/chk_obsdata//k5ts2/T2010300??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.03:04:43.19/chk_obsdata//k5ts3/T2010300??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.03:04:43.92/chk_obsdata//k5ts4/T2010300??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.03:04:44.67/k5log//k5ts1_log_newline 2006.201.03:04:45.67/k5log//k5ts2_log_newline 2006.201.03:04:46.75/k5log//k5ts3_log_newline 2006.201.03:04:47.70/k5log//k5ts4_log_newline 2006.201.03:04:47.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:04:47.72:setupk4=1 2006.201.03:04:47.72$setupk4/echo=on 2006.201.03:04:47.72$setupk4/pcalon 2006.201.03:04:47.72$pcalon/"no phase cal control is implemented here 2006.201.03:04:47.72$setupk4/"tpicd=stop 2006.201.03:04:47.72$setupk4/"rec=synch_on 2006.201.03:04:47.72$setupk4/"rec_mode=128 2006.201.03:04:47.72$setupk4/!* 2006.201.03:04:47.72$setupk4/recpk4 2006.201.03:04:47.72$recpk4/recpatch= 2006.201.03:04:47.73$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:04:47.73$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:04:47.73$setupk4/vck44 2006.201.03:04:47.73$vck44/valo=1,524.99 2006.201.03:04:47.73#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.03:04:47.73#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.03:04:47.73#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:47.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:47.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:47.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:47.73#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:04:47.73#ibcon#first serial, iclass 34, count 0 2006.201.03:04:47.73#ibcon#enter sib2, iclass 34, count 0 2006.201.03:04:47.73#ibcon#flushed, iclass 34, count 0 2006.201.03:04:47.73#ibcon#about to write, iclass 34, count 0 2006.201.03:04:47.73#ibcon#wrote, iclass 34, count 0 2006.201.03:04:47.73#ibcon#about to read 3, iclass 34, count 0 2006.201.03:04:47.77#ibcon#read 3, iclass 34, count 0 2006.201.03:04:47.77#ibcon#about to read 4, iclass 34, count 0 2006.201.03:04:47.77#ibcon#read 4, iclass 34, count 0 2006.201.03:04:47.77#ibcon#about to read 5, iclass 34, count 0 2006.201.03:04:47.77#ibcon#read 5, iclass 34, count 0 2006.201.03:04:47.77#ibcon#about to read 6, iclass 34, count 0 2006.201.03:04:47.77#ibcon#read 6, iclass 34, count 0 2006.201.03:04:47.77#ibcon#end of sib2, iclass 34, count 0 2006.201.03:04:47.77#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:04:47.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:04:47.77#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:04:47.77#ibcon#*before write, iclass 34, count 0 2006.201.03:04:47.77#ibcon#enter sib2, iclass 34, count 0 2006.201.03:04:47.77#ibcon#flushed, iclass 34, count 0 2006.201.03:04:47.77#ibcon#about to write, iclass 34, count 0 2006.201.03:04:47.77#ibcon#wrote, iclass 34, count 0 2006.201.03:04:47.77#ibcon#about to read 3, iclass 34, count 0 2006.201.03:04:47.82#ibcon#read 3, iclass 34, count 0 2006.201.03:04:47.82#ibcon#about to read 4, iclass 34, count 0 2006.201.03:04:47.82#ibcon#read 4, iclass 34, count 0 2006.201.03:04:47.82#ibcon#about to read 5, iclass 34, count 0 2006.201.03:04:47.82#ibcon#read 5, iclass 34, count 0 2006.201.03:04:47.82#ibcon#about to read 6, iclass 34, count 0 2006.201.03:04:47.82#ibcon#read 6, iclass 34, count 0 2006.201.03:04:47.82#ibcon#end of sib2, iclass 34, count 0 2006.201.03:04:47.82#ibcon#*after write, iclass 34, count 0 2006.201.03:04:47.82#ibcon#*before return 0, iclass 34, count 0 2006.201.03:04:47.82#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:47.82#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:47.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:04:47.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:04:47.82$vck44/va=1,8 2006.201.03:04:47.82#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.03:04:47.82#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.03:04:47.82#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:47.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:47.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:47.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:47.82#ibcon#enter wrdev, iclass 36, count 2 2006.201.03:04:47.82#ibcon#first serial, iclass 36, count 2 2006.201.03:04:47.82#ibcon#enter sib2, iclass 36, count 2 2006.201.03:04:47.82#ibcon#flushed, iclass 36, count 2 2006.201.03:04:47.82#ibcon#about to write, iclass 36, count 2 2006.201.03:04:47.82#ibcon#wrote, iclass 36, count 2 2006.201.03:04:47.82#ibcon#about to read 3, iclass 36, count 2 2006.201.03:04:47.84#ibcon#read 3, iclass 36, count 2 2006.201.03:04:47.84#ibcon#about to read 4, iclass 36, count 2 2006.201.03:04:47.84#ibcon#read 4, iclass 36, count 2 2006.201.03:04:47.84#ibcon#about to read 5, iclass 36, count 2 2006.201.03:04:47.84#ibcon#read 5, iclass 36, count 2 2006.201.03:04:47.84#ibcon#about to read 6, iclass 36, count 2 2006.201.03:04:47.84#ibcon#read 6, iclass 36, count 2 2006.201.03:04:47.84#ibcon#end of sib2, iclass 36, count 2 2006.201.03:04:47.84#ibcon#*mode == 0, iclass 36, count 2 2006.201.03:04:47.84#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.03:04:47.84#ibcon#[25=AT01-08\r\n] 2006.201.03:04:47.84#ibcon#*before write, iclass 36, count 2 2006.201.03:04:47.84#ibcon#enter sib2, iclass 36, count 2 2006.201.03:04:47.84#ibcon#flushed, iclass 36, count 2 2006.201.03:04:47.84#ibcon#about to write, iclass 36, count 2 2006.201.03:04:47.84#ibcon#wrote, iclass 36, count 2 2006.201.03:04:47.84#ibcon#about to read 3, iclass 36, count 2 2006.201.03:04:47.87#ibcon#read 3, iclass 36, count 2 2006.201.03:04:47.87#ibcon#about to read 4, iclass 36, count 2 2006.201.03:04:47.87#ibcon#read 4, iclass 36, count 2 2006.201.03:04:47.87#ibcon#about to read 5, iclass 36, count 2 2006.201.03:04:47.87#ibcon#read 5, iclass 36, count 2 2006.201.03:04:47.87#ibcon#about to read 6, iclass 36, count 2 2006.201.03:04:47.87#ibcon#read 6, iclass 36, count 2 2006.201.03:04:47.87#ibcon#end of sib2, iclass 36, count 2 2006.201.03:04:47.87#ibcon#*after write, iclass 36, count 2 2006.201.03:04:47.87#ibcon#*before return 0, iclass 36, count 2 2006.201.03:04:47.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:47.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:47.87#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.03:04:47.87#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:47.87#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:47.99#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:47.99#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:47.99#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:04:47.99#ibcon#first serial, iclass 36, count 0 2006.201.03:04:47.99#ibcon#enter sib2, iclass 36, count 0 2006.201.03:04:47.99#ibcon#flushed, iclass 36, count 0 2006.201.03:04:47.99#ibcon#about to write, iclass 36, count 0 2006.201.03:04:47.99#ibcon#wrote, iclass 36, count 0 2006.201.03:04:47.99#ibcon#about to read 3, iclass 36, count 0 2006.201.03:04:48.01#ibcon#read 3, iclass 36, count 0 2006.201.03:04:48.01#ibcon#about to read 4, iclass 36, count 0 2006.201.03:04:48.01#ibcon#read 4, iclass 36, count 0 2006.201.03:04:48.01#ibcon#about to read 5, iclass 36, count 0 2006.201.03:04:48.01#ibcon#read 5, iclass 36, count 0 2006.201.03:04:48.01#ibcon#about to read 6, iclass 36, count 0 2006.201.03:04:48.01#ibcon#read 6, iclass 36, count 0 2006.201.03:04:48.01#ibcon#end of sib2, iclass 36, count 0 2006.201.03:04:48.01#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:04:48.01#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:04:48.01#ibcon#[25=USB\r\n] 2006.201.03:04:48.01#ibcon#*before write, iclass 36, count 0 2006.201.03:04:48.01#ibcon#enter sib2, iclass 36, count 0 2006.201.03:04:48.01#ibcon#flushed, iclass 36, count 0 2006.201.03:04:48.01#ibcon#about to write, iclass 36, count 0 2006.201.03:04:48.01#ibcon#wrote, iclass 36, count 0 2006.201.03:04:48.01#ibcon#about to read 3, iclass 36, count 0 2006.201.03:04:48.04#ibcon#read 3, iclass 36, count 0 2006.201.03:04:48.04#ibcon#about to read 4, iclass 36, count 0 2006.201.03:04:48.04#ibcon#read 4, iclass 36, count 0 2006.201.03:04:48.04#ibcon#about to read 5, iclass 36, count 0 2006.201.03:04:48.04#ibcon#read 5, iclass 36, count 0 2006.201.03:04:48.04#ibcon#about to read 6, iclass 36, count 0 2006.201.03:04:48.04#ibcon#read 6, iclass 36, count 0 2006.201.03:04:48.04#ibcon#end of sib2, iclass 36, count 0 2006.201.03:04:48.04#ibcon#*after write, iclass 36, count 0 2006.201.03:04:48.04#ibcon#*before return 0, iclass 36, count 0 2006.201.03:04:48.04#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:48.04#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:48.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:04:48.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:04:48.04$vck44/valo=2,534.99 2006.201.03:04:48.04#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.03:04:48.04#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.03:04:48.04#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:48.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:48.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:48.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:48.04#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:04:48.04#ibcon#first serial, iclass 38, count 0 2006.201.03:04:48.04#ibcon#enter sib2, iclass 38, count 0 2006.201.03:04:48.04#ibcon#flushed, iclass 38, count 0 2006.201.03:04:48.04#ibcon#about to write, iclass 38, count 0 2006.201.03:04:48.04#ibcon#wrote, iclass 38, count 0 2006.201.03:04:48.04#ibcon#about to read 3, iclass 38, count 0 2006.201.03:04:48.06#ibcon#read 3, iclass 38, count 0 2006.201.03:04:48.06#ibcon#about to read 4, iclass 38, count 0 2006.201.03:04:48.06#ibcon#read 4, iclass 38, count 0 2006.201.03:04:48.06#ibcon#about to read 5, iclass 38, count 0 2006.201.03:04:48.06#ibcon#read 5, iclass 38, count 0 2006.201.03:04:48.06#ibcon#about to read 6, iclass 38, count 0 2006.201.03:04:48.06#ibcon#read 6, iclass 38, count 0 2006.201.03:04:48.06#ibcon#end of sib2, iclass 38, count 0 2006.201.03:04:48.06#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:04:48.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:04:48.06#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:04:48.06#ibcon#*before write, iclass 38, count 0 2006.201.03:04:48.06#ibcon#enter sib2, iclass 38, count 0 2006.201.03:04:48.06#ibcon#flushed, iclass 38, count 0 2006.201.03:04:48.06#ibcon#about to write, iclass 38, count 0 2006.201.03:04:48.06#ibcon#wrote, iclass 38, count 0 2006.201.03:04:48.06#ibcon#about to read 3, iclass 38, count 0 2006.201.03:04:48.11#ibcon#read 3, iclass 38, count 0 2006.201.03:04:48.11#ibcon#about to read 4, iclass 38, count 0 2006.201.03:04:48.11#ibcon#read 4, iclass 38, count 0 2006.201.03:04:48.11#ibcon#about to read 5, iclass 38, count 0 2006.201.03:04:48.11#ibcon#read 5, iclass 38, count 0 2006.201.03:04:48.11#ibcon#about to read 6, iclass 38, count 0 2006.201.03:04:48.11#ibcon#read 6, iclass 38, count 0 2006.201.03:04:48.11#ibcon#end of sib2, iclass 38, count 0 2006.201.03:04:48.11#ibcon#*after write, iclass 38, count 0 2006.201.03:04:48.11#ibcon#*before return 0, iclass 38, count 0 2006.201.03:04:48.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:48.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:48.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:04:48.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:04:48.11$vck44/va=2,7 2006.201.03:04:48.11#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.03:04:48.11#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.03:04:48.11#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:48.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:48.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:48.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:48.16#ibcon#enter wrdev, iclass 40, count 2 2006.201.03:04:48.16#ibcon#first serial, iclass 40, count 2 2006.201.03:04:48.16#ibcon#enter sib2, iclass 40, count 2 2006.201.03:04:48.16#ibcon#flushed, iclass 40, count 2 2006.201.03:04:48.16#ibcon#about to write, iclass 40, count 2 2006.201.03:04:48.16#ibcon#wrote, iclass 40, count 2 2006.201.03:04:48.16#ibcon#about to read 3, iclass 40, count 2 2006.201.03:04:48.18#ibcon#read 3, iclass 40, count 2 2006.201.03:04:48.18#ibcon#about to read 4, iclass 40, count 2 2006.201.03:04:48.18#ibcon#read 4, iclass 40, count 2 2006.201.03:04:48.18#ibcon#about to read 5, iclass 40, count 2 2006.201.03:04:48.18#ibcon#read 5, iclass 40, count 2 2006.201.03:04:48.18#ibcon#about to read 6, iclass 40, count 2 2006.201.03:04:48.18#ibcon#read 6, iclass 40, count 2 2006.201.03:04:48.18#ibcon#end of sib2, iclass 40, count 2 2006.201.03:04:48.18#ibcon#*mode == 0, iclass 40, count 2 2006.201.03:04:48.18#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.03:04:48.18#ibcon#[25=AT02-07\r\n] 2006.201.03:04:48.18#ibcon#*before write, iclass 40, count 2 2006.201.03:04:48.18#ibcon#enter sib2, iclass 40, count 2 2006.201.03:04:48.18#ibcon#flushed, iclass 40, count 2 2006.201.03:04:48.18#ibcon#about to write, iclass 40, count 2 2006.201.03:04:48.18#ibcon#wrote, iclass 40, count 2 2006.201.03:04:48.18#ibcon#about to read 3, iclass 40, count 2 2006.201.03:04:48.21#ibcon#read 3, iclass 40, count 2 2006.201.03:04:48.21#ibcon#about to read 4, iclass 40, count 2 2006.201.03:04:48.21#ibcon#read 4, iclass 40, count 2 2006.201.03:04:48.21#ibcon#about to read 5, iclass 40, count 2 2006.201.03:04:48.21#ibcon#read 5, iclass 40, count 2 2006.201.03:04:48.21#ibcon#about to read 6, iclass 40, count 2 2006.201.03:04:48.21#ibcon#read 6, iclass 40, count 2 2006.201.03:04:48.21#ibcon#end of sib2, iclass 40, count 2 2006.201.03:04:48.21#ibcon#*after write, iclass 40, count 2 2006.201.03:04:48.21#ibcon#*before return 0, iclass 40, count 2 2006.201.03:04:48.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:48.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:48.21#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.03:04:48.21#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:48.21#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:48.33#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:48.33#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:48.33#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:04:48.33#ibcon#first serial, iclass 40, count 0 2006.201.03:04:48.33#ibcon#enter sib2, iclass 40, count 0 2006.201.03:04:48.33#ibcon#flushed, iclass 40, count 0 2006.201.03:04:48.33#ibcon#about to write, iclass 40, count 0 2006.201.03:04:48.33#ibcon#wrote, iclass 40, count 0 2006.201.03:04:48.33#ibcon#about to read 3, iclass 40, count 0 2006.201.03:04:48.35#ibcon#read 3, iclass 40, count 0 2006.201.03:04:48.35#ibcon#about to read 4, iclass 40, count 0 2006.201.03:04:48.35#ibcon#read 4, iclass 40, count 0 2006.201.03:04:48.35#ibcon#about to read 5, iclass 40, count 0 2006.201.03:04:48.35#ibcon#read 5, iclass 40, count 0 2006.201.03:04:48.35#ibcon#about to read 6, iclass 40, count 0 2006.201.03:04:48.35#ibcon#read 6, iclass 40, count 0 2006.201.03:04:48.35#ibcon#end of sib2, iclass 40, count 0 2006.201.03:04:48.35#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:04:48.35#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:04:48.35#ibcon#[25=USB\r\n] 2006.201.03:04:48.35#ibcon#*before write, iclass 40, count 0 2006.201.03:04:48.35#ibcon#enter sib2, iclass 40, count 0 2006.201.03:04:48.35#ibcon#flushed, iclass 40, count 0 2006.201.03:04:48.35#ibcon#about to write, iclass 40, count 0 2006.201.03:04:48.35#ibcon#wrote, iclass 40, count 0 2006.201.03:04:48.35#ibcon#about to read 3, iclass 40, count 0 2006.201.03:04:48.38#ibcon#read 3, iclass 40, count 0 2006.201.03:04:48.38#ibcon#about to read 4, iclass 40, count 0 2006.201.03:04:48.38#ibcon#read 4, iclass 40, count 0 2006.201.03:04:48.38#ibcon#about to read 5, iclass 40, count 0 2006.201.03:04:48.38#ibcon#read 5, iclass 40, count 0 2006.201.03:04:48.38#ibcon#about to read 6, iclass 40, count 0 2006.201.03:04:48.38#ibcon#read 6, iclass 40, count 0 2006.201.03:04:48.38#ibcon#end of sib2, iclass 40, count 0 2006.201.03:04:48.38#ibcon#*after write, iclass 40, count 0 2006.201.03:04:48.38#ibcon#*before return 0, iclass 40, count 0 2006.201.03:04:48.38#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:48.38#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:48.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:04:48.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:04:48.38$vck44/valo=3,564.99 2006.201.03:04:48.38#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.03:04:48.38#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.03:04:48.38#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:48.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:48.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:48.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:48.38#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:04:48.38#ibcon#first serial, iclass 4, count 0 2006.201.03:04:48.38#ibcon#enter sib2, iclass 4, count 0 2006.201.03:04:48.38#ibcon#flushed, iclass 4, count 0 2006.201.03:04:48.38#ibcon#about to write, iclass 4, count 0 2006.201.03:04:48.38#ibcon#wrote, iclass 4, count 0 2006.201.03:04:48.38#ibcon#about to read 3, iclass 4, count 0 2006.201.03:04:48.40#ibcon#read 3, iclass 4, count 0 2006.201.03:04:48.40#ibcon#about to read 4, iclass 4, count 0 2006.201.03:04:48.40#ibcon#read 4, iclass 4, count 0 2006.201.03:04:48.40#ibcon#about to read 5, iclass 4, count 0 2006.201.03:04:48.40#ibcon#read 5, iclass 4, count 0 2006.201.03:04:48.40#ibcon#about to read 6, iclass 4, count 0 2006.201.03:04:48.40#ibcon#read 6, iclass 4, count 0 2006.201.03:04:48.40#ibcon#end of sib2, iclass 4, count 0 2006.201.03:04:48.40#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:04:48.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:04:48.40#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:04:48.40#ibcon#*before write, iclass 4, count 0 2006.201.03:04:48.40#ibcon#enter sib2, iclass 4, count 0 2006.201.03:04:48.40#ibcon#flushed, iclass 4, count 0 2006.201.03:04:48.40#ibcon#about to write, iclass 4, count 0 2006.201.03:04:48.40#ibcon#wrote, iclass 4, count 0 2006.201.03:04:48.40#ibcon#about to read 3, iclass 4, count 0 2006.201.03:04:48.45#ibcon#read 3, iclass 4, count 0 2006.201.03:04:48.45#ibcon#about to read 4, iclass 4, count 0 2006.201.03:04:48.45#ibcon#read 4, iclass 4, count 0 2006.201.03:04:48.45#ibcon#about to read 5, iclass 4, count 0 2006.201.03:04:48.45#ibcon#read 5, iclass 4, count 0 2006.201.03:04:48.45#ibcon#about to read 6, iclass 4, count 0 2006.201.03:04:48.45#ibcon#read 6, iclass 4, count 0 2006.201.03:04:48.45#ibcon#end of sib2, iclass 4, count 0 2006.201.03:04:48.45#ibcon#*after write, iclass 4, count 0 2006.201.03:04:48.45#ibcon#*before return 0, iclass 4, count 0 2006.201.03:04:48.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:48.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:48.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:04:48.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:04:48.45$vck44/va=3,8 2006.201.03:04:48.45#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.03:04:48.45#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.03:04:48.45#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:48.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:48.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:48.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:48.50#ibcon#enter wrdev, iclass 6, count 2 2006.201.03:04:48.50#ibcon#first serial, iclass 6, count 2 2006.201.03:04:48.50#ibcon#enter sib2, iclass 6, count 2 2006.201.03:04:48.50#ibcon#flushed, iclass 6, count 2 2006.201.03:04:48.50#ibcon#about to write, iclass 6, count 2 2006.201.03:04:48.50#ibcon#wrote, iclass 6, count 2 2006.201.03:04:48.50#ibcon#about to read 3, iclass 6, count 2 2006.201.03:04:48.52#ibcon#read 3, iclass 6, count 2 2006.201.03:04:48.52#ibcon#about to read 4, iclass 6, count 2 2006.201.03:04:48.52#ibcon#read 4, iclass 6, count 2 2006.201.03:04:48.52#ibcon#about to read 5, iclass 6, count 2 2006.201.03:04:48.52#ibcon#read 5, iclass 6, count 2 2006.201.03:04:48.52#ibcon#about to read 6, iclass 6, count 2 2006.201.03:04:48.52#ibcon#read 6, iclass 6, count 2 2006.201.03:04:48.52#ibcon#end of sib2, iclass 6, count 2 2006.201.03:04:48.52#ibcon#*mode == 0, iclass 6, count 2 2006.201.03:04:48.52#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.03:04:48.52#ibcon#[25=AT03-08\r\n] 2006.201.03:04:48.52#ibcon#*before write, iclass 6, count 2 2006.201.03:04:48.52#ibcon#enter sib2, iclass 6, count 2 2006.201.03:04:48.52#ibcon#flushed, iclass 6, count 2 2006.201.03:04:48.52#ibcon#about to write, iclass 6, count 2 2006.201.03:04:48.52#ibcon#wrote, iclass 6, count 2 2006.201.03:04:48.52#ibcon#about to read 3, iclass 6, count 2 2006.201.03:04:48.55#ibcon#read 3, iclass 6, count 2 2006.201.03:04:48.55#ibcon#about to read 4, iclass 6, count 2 2006.201.03:04:48.55#ibcon#read 4, iclass 6, count 2 2006.201.03:04:48.55#ibcon#about to read 5, iclass 6, count 2 2006.201.03:04:48.55#ibcon#read 5, iclass 6, count 2 2006.201.03:04:48.55#ibcon#about to read 6, iclass 6, count 2 2006.201.03:04:48.55#ibcon#read 6, iclass 6, count 2 2006.201.03:04:48.55#ibcon#end of sib2, iclass 6, count 2 2006.201.03:04:48.55#ibcon#*after write, iclass 6, count 2 2006.201.03:04:48.55#ibcon#*before return 0, iclass 6, count 2 2006.201.03:04:48.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:48.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:48.55#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.03:04:48.55#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:48.55#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:48.67#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:48.67#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:48.67#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:04:48.67#ibcon#first serial, iclass 6, count 0 2006.201.03:04:48.67#ibcon#enter sib2, iclass 6, count 0 2006.201.03:04:48.67#ibcon#flushed, iclass 6, count 0 2006.201.03:04:48.67#ibcon#about to write, iclass 6, count 0 2006.201.03:04:48.67#ibcon#wrote, iclass 6, count 0 2006.201.03:04:48.67#ibcon#about to read 3, iclass 6, count 0 2006.201.03:04:48.69#ibcon#read 3, iclass 6, count 0 2006.201.03:04:48.69#ibcon#about to read 4, iclass 6, count 0 2006.201.03:04:48.69#ibcon#read 4, iclass 6, count 0 2006.201.03:04:48.69#ibcon#about to read 5, iclass 6, count 0 2006.201.03:04:48.69#ibcon#read 5, iclass 6, count 0 2006.201.03:04:48.69#ibcon#about to read 6, iclass 6, count 0 2006.201.03:04:48.69#ibcon#read 6, iclass 6, count 0 2006.201.03:04:48.69#ibcon#end of sib2, iclass 6, count 0 2006.201.03:04:48.69#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:04:48.69#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:04:48.69#ibcon#[25=USB\r\n] 2006.201.03:04:48.69#ibcon#*before write, iclass 6, count 0 2006.201.03:04:48.69#ibcon#enter sib2, iclass 6, count 0 2006.201.03:04:48.69#ibcon#flushed, iclass 6, count 0 2006.201.03:04:48.69#ibcon#about to write, iclass 6, count 0 2006.201.03:04:48.69#ibcon#wrote, iclass 6, count 0 2006.201.03:04:48.69#ibcon#about to read 3, iclass 6, count 0 2006.201.03:04:48.72#ibcon#read 3, iclass 6, count 0 2006.201.03:04:48.72#ibcon#about to read 4, iclass 6, count 0 2006.201.03:04:48.72#ibcon#read 4, iclass 6, count 0 2006.201.03:04:48.72#ibcon#about to read 5, iclass 6, count 0 2006.201.03:04:48.72#ibcon#read 5, iclass 6, count 0 2006.201.03:04:48.72#ibcon#about to read 6, iclass 6, count 0 2006.201.03:04:48.72#ibcon#read 6, iclass 6, count 0 2006.201.03:04:48.72#ibcon#end of sib2, iclass 6, count 0 2006.201.03:04:48.72#ibcon#*after write, iclass 6, count 0 2006.201.03:04:48.72#ibcon#*before return 0, iclass 6, count 0 2006.201.03:04:48.72#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:48.72#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:48.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:04:48.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:04:48.72$vck44/valo=4,624.99 2006.201.03:04:48.72#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.03:04:48.72#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.03:04:48.72#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:48.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:48.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:48.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:48.72#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:04:48.72#ibcon#first serial, iclass 10, count 0 2006.201.03:04:48.72#ibcon#enter sib2, iclass 10, count 0 2006.201.03:04:48.72#ibcon#flushed, iclass 10, count 0 2006.201.03:04:48.72#ibcon#about to write, iclass 10, count 0 2006.201.03:04:48.72#ibcon#wrote, iclass 10, count 0 2006.201.03:04:48.72#ibcon#about to read 3, iclass 10, count 0 2006.201.03:04:48.74#ibcon#read 3, iclass 10, count 0 2006.201.03:04:48.74#ibcon#about to read 4, iclass 10, count 0 2006.201.03:04:48.74#ibcon#read 4, iclass 10, count 0 2006.201.03:04:48.74#ibcon#about to read 5, iclass 10, count 0 2006.201.03:04:48.74#ibcon#read 5, iclass 10, count 0 2006.201.03:04:48.74#ibcon#about to read 6, iclass 10, count 0 2006.201.03:04:48.74#ibcon#read 6, iclass 10, count 0 2006.201.03:04:48.74#ibcon#end of sib2, iclass 10, count 0 2006.201.03:04:48.74#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:04:48.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:04:48.74#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:04:48.74#ibcon#*before write, iclass 10, count 0 2006.201.03:04:48.74#ibcon#enter sib2, iclass 10, count 0 2006.201.03:04:48.74#ibcon#flushed, iclass 10, count 0 2006.201.03:04:48.74#ibcon#about to write, iclass 10, count 0 2006.201.03:04:48.74#ibcon#wrote, iclass 10, count 0 2006.201.03:04:48.74#ibcon#about to read 3, iclass 10, count 0 2006.201.03:04:48.78#ibcon#read 3, iclass 10, count 0 2006.201.03:04:48.78#ibcon#about to read 4, iclass 10, count 0 2006.201.03:04:48.78#ibcon#read 4, iclass 10, count 0 2006.201.03:04:48.78#ibcon#about to read 5, iclass 10, count 0 2006.201.03:04:48.78#ibcon#read 5, iclass 10, count 0 2006.201.03:04:48.78#ibcon#about to read 6, iclass 10, count 0 2006.201.03:04:48.78#ibcon#read 6, iclass 10, count 0 2006.201.03:04:48.78#ibcon#end of sib2, iclass 10, count 0 2006.201.03:04:48.78#ibcon#*after write, iclass 10, count 0 2006.201.03:04:48.78#ibcon#*before return 0, iclass 10, count 0 2006.201.03:04:48.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:48.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:48.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:04:48.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:04:48.78$vck44/va=4,7 2006.201.03:04:48.78#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.03:04:48.78#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.03:04:48.78#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:48.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:48.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:48.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:48.84#ibcon#enter wrdev, iclass 12, count 2 2006.201.03:04:48.84#ibcon#first serial, iclass 12, count 2 2006.201.03:04:48.84#ibcon#enter sib2, iclass 12, count 2 2006.201.03:04:48.84#ibcon#flushed, iclass 12, count 2 2006.201.03:04:48.84#ibcon#about to write, iclass 12, count 2 2006.201.03:04:48.84#ibcon#wrote, iclass 12, count 2 2006.201.03:04:48.84#ibcon#about to read 3, iclass 12, count 2 2006.201.03:04:48.86#ibcon#read 3, iclass 12, count 2 2006.201.03:04:48.86#ibcon#about to read 4, iclass 12, count 2 2006.201.03:04:48.86#ibcon#read 4, iclass 12, count 2 2006.201.03:04:48.86#ibcon#about to read 5, iclass 12, count 2 2006.201.03:04:48.86#ibcon#read 5, iclass 12, count 2 2006.201.03:04:48.86#ibcon#about to read 6, iclass 12, count 2 2006.201.03:04:48.86#ibcon#read 6, iclass 12, count 2 2006.201.03:04:48.86#ibcon#end of sib2, iclass 12, count 2 2006.201.03:04:48.86#ibcon#*mode == 0, iclass 12, count 2 2006.201.03:04:48.86#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.03:04:48.86#ibcon#[25=AT04-07\r\n] 2006.201.03:04:48.86#ibcon#*before write, iclass 12, count 2 2006.201.03:04:48.86#ibcon#enter sib2, iclass 12, count 2 2006.201.03:04:48.86#ibcon#flushed, iclass 12, count 2 2006.201.03:04:48.86#ibcon#about to write, iclass 12, count 2 2006.201.03:04:48.86#ibcon#wrote, iclass 12, count 2 2006.201.03:04:48.86#ibcon#about to read 3, iclass 12, count 2 2006.201.03:04:48.89#ibcon#read 3, iclass 12, count 2 2006.201.03:04:48.89#ibcon#about to read 4, iclass 12, count 2 2006.201.03:04:48.89#ibcon#read 4, iclass 12, count 2 2006.201.03:04:48.89#ibcon#about to read 5, iclass 12, count 2 2006.201.03:04:48.89#ibcon#read 5, iclass 12, count 2 2006.201.03:04:48.89#ibcon#about to read 6, iclass 12, count 2 2006.201.03:04:48.89#ibcon#read 6, iclass 12, count 2 2006.201.03:04:48.89#ibcon#end of sib2, iclass 12, count 2 2006.201.03:04:48.89#ibcon#*after write, iclass 12, count 2 2006.201.03:04:48.89#ibcon#*before return 0, iclass 12, count 2 2006.201.03:04:48.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:48.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:48.89#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.03:04:48.89#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:48.89#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:49.01#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:49.01#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:49.01#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:04:49.01#ibcon#first serial, iclass 12, count 0 2006.201.03:04:49.01#ibcon#enter sib2, iclass 12, count 0 2006.201.03:04:49.01#ibcon#flushed, iclass 12, count 0 2006.201.03:04:49.01#ibcon#about to write, iclass 12, count 0 2006.201.03:04:49.01#ibcon#wrote, iclass 12, count 0 2006.201.03:04:49.01#ibcon#about to read 3, iclass 12, count 0 2006.201.03:04:49.03#ibcon#read 3, iclass 12, count 0 2006.201.03:04:49.03#ibcon#about to read 4, iclass 12, count 0 2006.201.03:04:49.03#ibcon#read 4, iclass 12, count 0 2006.201.03:04:49.03#ibcon#about to read 5, iclass 12, count 0 2006.201.03:04:49.03#ibcon#read 5, iclass 12, count 0 2006.201.03:04:49.03#ibcon#about to read 6, iclass 12, count 0 2006.201.03:04:49.03#ibcon#read 6, iclass 12, count 0 2006.201.03:04:49.03#ibcon#end of sib2, iclass 12, count 0 2006.201.03:04:49.03#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:04:49.03#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:04:49.03#ibcon#[25=USB\r\n] 2006.201.03:04:49.03#ibcon#*before write, iclass 12, count 0 2006.201.03:04:49.03#ibcon#enter sib2, iclass 12, count 0 2006.201.03:04:49.03#ibcon#flushed, iclass 12, count 0 2006.201.03:04:49.03#ibcon#about to write, iclass 12, count 0 2006.201.03:04:49.03#ibcon#wrote, iclass 12, count 0 2006.201.03:04:49.03#ibcon#about to read 3, iclass 12, count 0 2006.201.03:04:49.06#ibcon#read 3, iclass 12, count 0 2006.201.03:04:49.06#ibcon#about to read 4, iclass 12, count 0 2006.201.03:04:49.06#ibcon#read 4, iclass 12, count 0 2006.201.03:04:49.06#ibcon#about to read 5, iclass 12, count 0 2006.201.03:04:49.06#ibcon#read 5, iclass 12, count 0 2006.201.03:04:49.06#ibcon#about to read 6, iclass 12, count 0 2006.201.03:04:49.06#ibcon#read 6, iclass 12, count 0 2006.201.03:04:49.06#ibcon#end of sib2, iclass 12, count 0 2006.201.03:04:49.06#ibcon#*after write, iclass 12, count 0 2006.201.03:04:49.06#ibcon#*before return 0, iclass 12, count 0 2006.201.03:04:49.06#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:49.06#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:49.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:04:49.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:04:49.06$vck44/valo=5,734.99 2006.201.03:04:49.06#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.03:04:49.06#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.03:04:49.06#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:49.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:49.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:49.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:49.06#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:04:49.06#ibcon#first serial, iclass 14, count 0 2006.201.03:04:49.06#ibcon#enter sib2, iclass 14, count 0 2006.201.03:04:49.06#ibcon#flushed, iclass 14, count 0 2006.201.03:04:49.06#ibcon#about to write, iclass 14, count 0 2006.201.03:04:49.06#ibcon#wrote, iclass 14, count 0 2006.201.03:04:49.06#ibcon#about to read 3, iclass 14, count 0 2006.201.03:04:49.08#ibcon#read 3, iclass 14, count 0 2006.201.03:04:49.08#ibcon#about to read 4, iclass 14, count 0 2006.201.03:04:49.08#ibcon#read 4, iclass 14, count 0 2006.201.03:04:49.08#ibcon#about to read 5, iclass 14, count 0 2006.201.03:04:49.08#ibcon#read 5, iclass 14, count 0 2006.201.03:04:49.08#ibcon#about to read 6, iclass 14, count 0 2006.201.03:04:49.08#ibcon#read 6, iclass 14, count 0 2006.201.03:04:49.08#ibcon#end of sib2, iclass 14, count 0 2006.201.03:04:49.08#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:04:49.08#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:04:49.08#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:04:49.08#ibcon#*before write, iclass 14, count 0 2006.201.03:04:49.08#ibcon#enter sib2, iclass 14, count 0 2006.201.03:04:49.08#ibcon#flushed, iclass 14, count 0 2006.201.03:04:49.08#ibcon#about to write, iclass 14, count 0 2006.201.03:04:49.08#ibcon#wrote, iclass 14, count 0 2006.201.03:04:49.08#ibcon#about to read 3, iclass 14, count 0 2006.201.03:04:49.12#ibcon#read 3, iclass 14, count 0 2006.201.03:04:49.12#ibcon#about to read 4, iclass 14, count 0 2006.201.03:04:49.12#ibcon#read 4, iclass 14, count 0 2006.201.03:04:49.12#ibcon#about to read 5, iclass 14, count 0 2006.201.03:04:49.12#ibcon#read 5, iclass 14, count 0 2006.201.03:04:49.12#ibcon#about to read 6, iclass 14, count 0 2006.201.03:04:49.12#ibcon#read 6, iclass 14, count 0 2006.201.03:04:49.12#ibcon#end of sib2, iclass 14, count 0 2006.201.03:04:49.12#ibcon#*after write, iclass 14, count 0 2006.201.03:04:49.12#ibcon#*before return 0, iclass 14, count 0 2006.201.03:04:49.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:49.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:49.12#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:04:49.12#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:04:49.12$vck44/va=5,4 2006.201.03:04:49.12#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.03:04:49.12#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.03:04:49.12#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:49.12#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:49.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:49.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:49.18#ibcon#enter wrdev, iclass 16, count 2 2006.201.03:04:49.18#ibcon#first serial, iclass 16, count 2 2006.201.03:04:49.18#ibcon#enter sib2, iclass 16, count 2 2006.201.03:04:49.18#ibcon#flushed, iclass 16, count 2 2006.201.03:04:49.18#ibcon#about to write, iclass 16, count 2 2006.201.03:04:49.18#ibcon#wrote, iclass 16, count 2 2006.201.03:04:49.18#ibcon#about to read 3, iclass 16, count 2 2006.201.03:04:49.20#ibcon#read 3, iclass 16, count 2 2006.201.03:04:49.20#ibcon#about to read 4, iclass 16, count 2 2006.201.03:04:49.20#ibcon#read 4, iclass 16, count 2 2006.201.03:04:49.20#ibcon#about to read 5, iclass 16, count 2 2006.201.03:04:49.20#ibcon#read 5, iclass 16, count 2 2006.201.03:04:49.20#ibcon#about to read 6, iclass 16, count 2 2006.201.03:04:49.20#ibcon#read 6, iclass 16, count 2 2006.201.03:04:49.20#ibcon#end of sib2, iclass 16, count 2 2006.201.03:04:49.20#ibcon#*mode == 0, iclass 16, count 2 2006.201.03:04:49.20#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.03:04:49.20#ibcon#[25=AT05-04\r\n] 2006.201.03:04:49.20#ibcon#*before write, iclass 16, count 2 2006.201.03:04:49.20#ibcon#enter sib2, iclass 16, count 2 2006.201.03:04:49.20#ibcon#flushed, iclass 16, count 2 2006.201.03:04:49.20#ibcon#about to write, iclass 16, count 2 2006.201.03:04:49.20#ibcon#wrote, iclass 16, count 2 2006.201.03:04:49.20#ibcon#about to read 3, iclass 16, count 2 2006.201.03:04:49.23#ibcon#read 3, iclass 16, count 2 2006.201.03:04:49.23#ibcon#about to read 4, iclass 16, count 2 2006.201.03:04:49.23#ibcon#read 4, iclass 16, count 2 2006.201.03:04:49.23#ibcon#about to read 5, iclass 16, count 2 2006.201.03:04:49.23#ibcon#read 5, iclass 16, count 2 2006.201.03:04:49.23#ibcon#about to read 6, iclass 16, count 2 2006.201.03:04:49.23#ibcon#read 6, iclass 16, count 2 2006.201.03:04:49.23#ibcon#end of sib2, iclass 16, count 2 2006.201.03:04:49.23#ibcon#*after write, iclass 16, count 2 2006.201.03:04:49.23#ibcon#*before return 0, iclass 16, count 2 2006.201.03:04:49.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:49.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:49.23#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.03:04:49.23#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:49.23#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:49.35#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:49.35#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:49.35#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:04:49.35#ibcon#first serial, iclass 16, count 0 2006.201.03:04:49.35#ibcon#enter sib2, iclass 16, count 0 2006.201.03:04:49.35#ibcon#flushed, iclass 16, count 0 2006.201.03:04:49.35#ibcon#about to write, iclass 16, count 0 2006.201.03:04:49.35#ibcon#wrote, iclass 16, count 0 2006.201.03:04:49.35#ibcon#about to read 3, iclass 16, count 0 2006.201.03:04:49.37#ibcon#read 3, iclass 16, count 0 2006.201.03:04:49.37#ibcon#about to read 4, iclass 16, count 0 2006.201.03:04:49.37#ibcon#read 4, iclass 16, count 0 2006.201.03:04:49.37#ibcon#about to read 5, iclass 16, count 0 2006.201.03:04:49.37#ibcon#read 5, iclass 16, count 0 2006.201.03:04:49.37#ibcon#about to read 6, iclass 16, count 0 2006.201.03:04:49.37#ibcon#read 6, iclass 16, count 0 2006.201.03:04:49.37#ibcon#end of sib2, iclass 16, count 0 2006.201.03:04:49.37#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:04:49.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:04:49.37#ibcon#[25=USB\r\n] 2006.201.03:04:49.37#ibcon#*before write, iclass 16, count 0 2006.201.03:04:49.37#ibcon#enter sib2, iclass 16, count 0 2006.201.03:04:49.37#ibcon#flushed, iclass 16, count 0 2006.201.03:04:49.37#ibcon#about to write, iclass 16, count 0 2006.201.03:04:49.37#ibcon#wrote, iclass 16, count 0 2006.201.03:04:49.37#ibcon#about to read 3, iclass 16, count 0 2006.201.03:04:49.40#ibcon#read 3, iclass 16, count 0 2006.201.03:04:49.40#ibcon#about to read 4, iclass 16, count 0 2006.201.03:04:49.40#ibcon#read 4, iclass 16, count 0 2006.201.03:04:49.40#ibcon#about to read 5, iclass 16, count 0 2006.201.03:04:49.40#ibcon#read 5, iclass 16, count 0 2006.201.03:04:49.40#ibcon#about to read 6, iclass 16, count 0 2006.201.03:04:49.40#ibcon#read 6, iclass 16, count 0 2006.201.03:04:49.40#ibcon#end of sib2, iclass 16, count 0 2006.201.03:04:49.40#ibcon#*after write, iclass 16, count 0 2006.201.03:04:49.40#ibcon#*before return 0, iclass 16, count 0 2006.201.03:04:49.40#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:49.40#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:49.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:04:49.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:04:49.40$vck44/valo=6,814.99 2006.201.03:04:49.40#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.03:04:49.40#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.03:04:49.40#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:49.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:49.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:49.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:49.40#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:04:49.40#ibcon#first serial, iclass 18, count 0 2006.201.03:04:49.40#ibcon#enter sib2, iclass 18, count 0 2006.201.03:04:49.40#ibcon#flushed, iclass 18, count 0 2006.201.03:04:49.40#ibcon#about to write, iclass 18, count 0 2006.201.03:04:49.40#ibcon#wrote, iclass 18, count 0 2006.201.03:04:49.40#ibcon#about to read 3, iclass 18, count 0 2006.201.03:04:49.42#ibcon#read 3, iclass 18, count 0 2006.201.03:04:49.42#ibcon#about to read 4, iclass 18, count 0 2006.201.03:04:49.42#ibcon#read 4, iclass 18, count 0 2006.201.03:04:49.42#ibcon#about to read 5, iclass 18, count 0 2006.201.03:04:49.42#ibcon#read 5, iclass 18, count 0 2006.201.03:04:49.42#ibcon#about to read 6, iclass 18, count 0 2006.201.03:04:49.42#ibcon#read 6, iclass 18, count 0 2006.201.03:04:49.42#ibcon#end of sib2, iclass 18, count 0 2006.201.03:04:49.42#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:04:49.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:04:49.42#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:04:49.42#ibcon#*before write, iclass 18, count 0 2006.201.03:04:49.42#ibcon#enter sib2, iclass 18, count 0 2006.201.03:04:49.42#ibcon#flushed, iclass 18, count 0 2006.201.03:04:49.42#ibcon#about to write, iclass 18, count 0 2006.201.03:04:49.42#ibcon#wrote, iclass 18, count 0 2006.201.03:04:49.42#ibcon#about to read 3, iclass 18, count 0 2006.201.03:04:49.47#ibcon#read 3, iclass 18, count 0 2006.201.03:04:49.47#ibcon#about to read 4, iclass 18, count 0 2006.201.03:04:49.47#ibcon#read 4, iclass 18, count 0 2006.201.03:04:49.47#ibcon#about to read 5, iclass 18, count 0 2006.201.03:04:49.47#ibcon#read 5, iclass 18, count 0 2006.201.03:04:49.47#ibcon#about to read 6, iclass 18, count 0 2006.201.03:04:49.47#ibcon#read 6, iclass 18, count 0 2006.201.03:04:49.47#ibcon#end of sib2, iclass 18, count 0 2006.201.03:04:49.47#ibcon#*after write, iclass 18, count 0 2006.201.03:04:49.47#ibcon#*before return 0, iclass 18, count 0 2006.201.03:04:49.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:49.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:49.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:04:49.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:04:49.47$vck44/va=6,5 2006.201.03:04:49.47#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.03:04:49.47#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.03:04:49.47#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:49.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:49.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:49.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:49.52#ibcon#enter wrdev, iclass 20, count 2 2006.201.03:04:49.52#ibcon#first serial, iclass 20, count 2 2006.201.03:04:49.52#ibcon#enter sib2, iclass 20, count 2 2006.201.03:04:49.52#ibcon#flushed, iclass 20, count 2 2006.201.03:04:49.52#ibcon#about to write, iclass 20, count 2 2006.201.03:04:49.52#ibcon#wrote, iclass 20, count 2 2006.201.03:04:49.52#ibcon#about to read 3, iclass 20, count 2 2006.201.03:04:49.54#ibcon#read 3, iclass 20, count 2 2006.201.03:04:49.54#ibcon#about to read 4, iclass 20, count 2 2006.201.03:04:49.54#ibcon#read 4, iclass 20, count 2 2006.201.03:04:49.54#ibcon#about to read 5, iclass 20, count 2 2006.201.03:04:49.54#ibcon#read 5, iclass 20, count 2 2006.201.03:04:49.54#ibcon#about to read 6, iclass 20, count 2 2006.201.03:04:49.54#ibcon#read 6, iclass 20, count 2 2006.201.03:04:49.54#ibcon#end of sib2, iclass 20, count 2 2006.201.03:04:49.54#ibcon#*mode == 0, iclass 20, count 2 2006.201.03:04:49.54#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.03:04:49.54#ibcon#[25=AT06-05\r\n] 2006.201.03:04:49.54#ibcon#*before write, iclass 20, count 2 2006.201.03:04:49.54#ibcon#enter sib2, iclass 20, count 2 2006.201.03:04:49.54#ibcon#flushed, iclass 20, count 2 2006.201.03:04:49.54#ibcon#about to write, iclass 20, count 2 2006.201.03:04:49.54#ibcon#wrote, iclass 20, count 2 2006.201.03:04:49.54#ibcon#about to read 3, iclass 20, count 2 2006.201.03:04:49.57#ibcon#read 3, iclass 20, count 2 2006.201.03:04:49.57#ibcon#about to read 4, iclass 20, count 2 2006.201.03:04:49.57#ibcon#read 4, iclass 20, count 2 2006.201.03:04:49.57#ibcon#about to read 5, iclass 20, count 2 2006.201.03:04:49.57#ibcon#read 5, iclass 20, count 2 2006.201.03:04:49.57#ibcon#about to read 6, iclass 20, count 2 2006.201.03:04:49.57#ibcon#read 6, iclass 20, count 2 2006.201.03:04:49.57#ibcon#end of sib2, iclass 20, count 2 2006.201.03:04:49.57#ibcon#*after write, iclass 20, count 2 2006.201.03:04:49.57#ibcon#*before return 0, iclass 20, count 2 2006.201.03:04:49.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:49.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:49.57#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.03:04:49.57#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:49.57#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:49.69#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:49.69#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:49.69#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:04:49.69#ibcon#first serial, iclass 20, count 0 2006.201.03:04:49.69#ibcon#enter sib2, iclass 20, count 0 2006.201.03:04:49.69#ibcon#flushed, iclass 20, count 0 2006.201.03:04:49.69#ibcon#about to write, iclass 20, count 0 2006.201.03:04:49.69#ibcon#wrote, iclass 20, count 0 2006.201.03:04:49.69#ibcon#about to read 3, iclass 20, count 0 2006.201.03:04:49.71#ibcon#read 3, iclass 20, count 0 2006.201.03:04:49.71#ibcon#about to read 4, iclass 20, count 0 2006.201.03:04:49.71#ibcon#read 4, iclass 20, count 0 2006.201.03:04:49.71#ibcon#about to read 5, iclass 20, count 0 2006.201.03:04:49.71#ibcon#read 5, iclass 20, count 0 2006.201.03:04:49.71#ibcon#about to read 6, iclass 20, count 0 2006.201.03:04:49.71#ibcon#read 6, iclass 20, count 0 2006.201.03:04:49.71#ibcon#end of sib2, iclass 20, count 0 2006.201.03:04:49.71#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:04:49.71#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:04:49.71#ibcon#[25=USB\r\n] 2006.201.03:04:49.71#ibcon#*before write, iclass 20, count 0 2006.201.03:04:49.71#ibcon#enter sib2, iclass 20, count 0 2006.201.03:04:49.71#ibcon#flushed, iclass 20, count 0 2006.201.03:04:49.71#ibcon#about to write, iclass 20, count 0 2006.201.03:04:49.71#ibcon#wrote, iclass 20, count 0 2006.201.03:04:49.71#ibcon#about to read 3, iclass 20, count 0 2006.201.03:04:49.74#ibcon#read 3, iclass 20, count 0 2006.201.03:04:49.74#ibcon#about to read 4, iclass 20, count 0 2006.201.03:04:49.74#ibcon#read 4, iclass 20, count 0 2006.201.03:04:49.74#ibcon#about to read 5, iclass 20, count 0 2006.201.03:04:49.74#ibcon#read 5, iclass 20, count 0 2006.201.03:04:49.74#ibcon#about to read 6, iclass 20, count 0 2006.201.03:04:49.74#ibcon#read 6, iclass 20, count 0 2006.201.03:04:49.74#ibcon#end of sib2, iclass 20, count 0 2006.201.03:04:49.74#ibcon#*after write, iclass 20, count 0 2006.201.03:04:49.74#ibcon#*before return 0, iclass 20, count 0 2006.201.03:04:49.74#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:49.74#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:49.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:04:49.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:04:49.74$vck44/valo=7,864.99 2006.201.03:04:49.74#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.03:04:49.74#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.03:04:49.74#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:49.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:49.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:49.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:49.74#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:04:49.74#ibcon#first serial, iclass 22, count 0 2006.201.03:04:49.74#ibcon#enter sib2, iclass 22, count 0 2006.201.03:04:49.74#ibcon#flushed, iclass 22, count 0 2006.201.03:04:49.74#ibcon#about to write, iclass 22, count 0 2006.201.03:04:49.74#ibcon#wrote, iclass 22, count 0 2006.201.03:04:49.74#ibcon#about to read 3, iclass 22, count 0 2006.201.03:04:49.76#ibcon#read 3, iclass 22, count 0 2006.201.03:04:49.76#ibcon#about to read 4, iclass 22, count 0 2006.201.03:04:49.76#ibcon#read 4, iclass 22, count 0 2006.201.03:04:49.76#ibcon#about to read 5, iclass 22, count 0 2006.201.03:04:49.76#ibcon#read 5, iclass 22, count 0 2006.201.03:04:49.76#ibcon#about to read 6, iclass 22, count 0 2006.201.03:04:49.76#ibcon#read 6, iclass 22, count 0 2006.201.03:04:49.76#ibcon#end of sib2, iclass 22, count 0 2006.201.03:04:49.76#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:04:49.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:04:49.76#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:04:49.76#ibcon#*before write, iclass 22, count 0 2006.201.03:04:49.76#ibcon#enter sib2, iclass 22, count 0 2006.201.03:04:49.76#ibcon#flushed, iclass 22, count 0 2006.201.03:04:49.76#ibcon#about to write, iclass 22, count 0 2006.201.03:04:49.76#ibcon#wrote, iclass 22, count 0 2006.201.03:04:49.76#ibcon#about to read 3, iclass 22, count 0 2006.201.03:04:49.80#ibcon#read 3, iclass 22, count 0 2006.201.03:04:49.80#ibcon#about to read 4, iclass 22, count 0 2006.201.03:04:49.80#ibcon#read 4, iclass 22, count 0 2006.201.03:04:49.80#ibcon#about to read 5, iclass 22, count 0 2006.201.03:04:49.80#ibcon#read 5, iclass 22, count 0 2006.201.03:04:49.80#ibcon#about to read 6, iclass 22, count 0 2006.201.03:04:49.80#ibcon#read 6, iclass 22, count 0 2006.201.03:04:49.80#ibcon#end of sib2, iclass 22, count 0 2006.201.03:04:49.80#ibcon#*after write, iclass 22, count 0 2006.201.03:04:49.80#ibcon#*before return 0, iclass 22, count 0 2006.201.03:04:49.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:49.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:49.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:04:49.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:04:49.80$vck44/va=7,5 2006.201.03:04:49.80#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.03:04:49.80#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.03:04:49.80#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:49.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:49.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:49.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:49.86#ibcon#enter wrdev, iclass 24, count 2 2006.201.03:04:49.86#ibcon#first serial, iclass 24, count 2 2006.201.03:04:49.86#ibcon#enter sib2, iclass 24, count 2 2006.201.03:04:49.86#ibcon#flushed, iclass 24, count 2 2006.201.03:04:49.86#ibcon#about to write, iclass 24, count 2 2006.201.03:04:49.86#ibcon#wrote, iclass 24, count 2 2006.201.03:04:49.86#ibcon#about to read 3, iclass 24, count 2 2006.201.03:04:49.88#ibcon#read 3, iclass 24, count 2 2006.201.03:04:49.88#ibcon#about to read 4, iclass 24, count 2 2006.201.03:04:49.88#ibcon#read 4, iclass 24, count 2 2006.201.03:04:49.88#ibcon#about to read 5, iclass 24, count 2 2006.201.03:04:49.88#ibcon#read 5, iclass 24, count 2 2006.201.03:04:49.88#ibcon#about to read 6, iclass 24, count 2 2006.201.03:04:49.88#ibcon#read 6, iclass 24, count 2 2006.201.03:04:49.88#ibcon#end of sib2, iclass 24, count 2 2006.201.03:04:49.88#ibcon#*mode == 0, iclass 24, count 2 2006.201.03:04:49.88#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.03:04:49.88#ibcon#[25=AT07-05\r\n] 2006.201.03:04:49.88#ibcon#*before write, iclass 24, count 2 2006.201.03:04:49.88#ibcon#enter sib2, iclass 24, count 2 2006.201.03:04:49.88#ibcon#flushed, iclass 24, count 2 2006.201.03:04:49.88#ibcon#about to write, iclass 24, count 2 2006.201.03:04:49.88#ibcon#wrote, iclass 24, count 2 2006.201.03:04:49.88#ibcon#about to read 3, iclass 24, count 2 2006.201.03:04:49.91#ibcon#read 3, iclass 24, count 2 2006.201.03:04:49.91#ibcon#about to read 4, iclass 24, count 2 2006.201.03:04:49.91#ibcon#read 4, iclass 24, count 2 2006.201.03:04:49.91#ibcon#about to read 5, iclass 24, count 2 2006.201.03:04:49.91#ibcon#read 5, iclass 24, count 2 2006.201.03:04:49.91#ibcon#about to read 6, iclass 24, count 2 2006.201.03:04:49.91#ibcon#read 6, iclass 24, count 2 2006.201.03:04:49.91#ibcon#end of sib2, iclass 24, count 2 2006.201.03:04:49.91#ibcon#*after write, iclass 24, count 2 2006.201.03:04:49.91#ibcon#*before return 0, iclass 24, count 2 2006.201.03:04:49.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:49.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:49.91#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.03:04:49.91#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:49.91#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:49.98#abcon#<5=/03 2.3 4.1 22.85 941004.5\r\n> 2006.201.03:04:50.00#abcon#{5=INTERFACE CLEAR} 2006.201.03:04:50.03#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:50.03#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:50.03#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:04:50.03#ibcon#first serial, iclass 24, count 0 2006.201.03:04:50.03#ibcon#enter sib2, iclass 24, count 0 2006.201.03:04:50.03#ibcon#flushed, iclass 24, count 0 2006.201.03:04:50.03#ibcon#about to write, iclass 24, count 0 2006.201.03:04:50.03#ibcon#wrote, iclass 24, count 0 2006.201.03:04:50.03#ibcon#about to read 3, iclass 24, count 0 2006.201.03:04:50.05#ibcon#read 3, iclass 24, count 0 2006.201.03:04:50.05#ibcon#about to read 4, iclass 24, count 0 2006.201.03:04:50.05#ibcon#read 4, iclass 24, count 0 2006.201.03:04:50.05#ibcon#about to read 5, iclass 24, count 0 2006.201.03:04:50.05#ibcon#read 5, iclass 24, count 0 2006.201.03:04:50.05#ibcon#about to read 6, iclass 24, count 0 2006.201.03:04:50.05#ibcon#read 6, iclass 24, count 0 2006.201.03:04:50.05#ibcon#end of sib2, iclass 24, count 0 2006.201.03:04:50.05#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:04:50.05#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:04:50.05#ibcon#[25=USB\r\n] 2006.201.03:04:50.05#ibcon#*before write, iclass 24, count 0 2006.201.03:04:50.05#ibcon#enter sib2, iclass 24, count 0 2006.201.03:04:50.05#ibcon#flushed, iclass 24, count 0 2006.201.03:04:50.05#ibcon#about to write, iclass 24, count 0 2006.201.03:04:50.05#ibcon#wrote, iclass 24, count 0 2006.201.03:04:50.05#ibcon#about to read 3, iclass 24, count 0 2006.201.03:04:50.06#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:04:50.08#ibcon#read 3, iclass 24, count 0 2006.201.03:04:50.08#ibcon#about to read 4, iclass 24, count 0 2006.201.03:04:50.08#ibcon#read 4, iclass 24, count 0 2006.201.03:04:50.08#ibcon#about to read 5, iclass 24, count 0 2006.201.03:04:50.08#ibcon#read 5, iclass 24, count 0 2006.201.03:04:50.08#ibcon#about to read 6, iclass 24, count 0 2006.201.03:04:50.08#ibcon#read 6, iclass 24, count 0 2006.201.03:04:50.08#ibcon#end of sib2, iclass 24, count 0 2006.201.03:04:50.08#ibcon#*after write, iclass 24, count 0 2006.201.03:04:50.08#ibcon#*before return 0, iclass 24, count 0 2006.201.03:04:50.08#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:50.08#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:50.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:04:50.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:04:50.08$vck44/valo=8,884.99 2006.201.03:04:50.08#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.03:04:50.08#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.03:04:50.08#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:50.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:50.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:50.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:50.08#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:04:50.08#ibcon#first serial, iclass 30, count 0 2006.201.03:04:50.08#ibcon#enter sib2, iclass 30, count 0 2006.201.03:04:50.08#ibcon#flushed, iclass 30, count 0 2006.201.03:04:50.08#ibcon#about to write, iclass 30, count 0 2006.201.03:04:50.08#ibcon#wrote, iclass 30, count 0 2006.201.03:04:50.08#ibcon#about to read 3, iclass 30, count 0 2006.201.03:04:50.10#ibcon#read 3, iclass 30, count 0 2006.201.03:04:50.10#ibcon#about to read 4, iclass 30, count 0 2006.201.03:04:50.10#ibcon#read 4, iclass 30, count 0 2006.201.03:04:50.10#ibcon#about to read 5, iclass 30, count 0 2006.201.03:04:50.10#ibcon#read 5, iclass 30, count 0 2006.201.03:04:50.10#ibcon#about to read 6, iclass 30, count 0 2006.201.03:04:50.10#ibcon#read 6, iclass 30, count 0 2006.201.03:04:50.10#ibcon#end of sib2, iclass 30, count 0 2006.201.03:04:50.10#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:04:50.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:04:50.10#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:04:50.10#ibcon#*before write, iclass 30, count 0 2006.201.03:04:50.10#ibcon#enter sib2, iclass 30, count 0 2006.201.03:04:50.10#ibcon#flushed, iclass 30, count 0 2006.201.03:04:50.10#ibcon#about to write, iclass 30, count 0 2006.201.03:04:50.10#ibcon#wrote, iclass 30, count 0 2006.201.03:04:50.10#ibcon#about to read 3, iclass 30, count 0 2006.201.03:04:50.14#ibcon#read 3, iclass 30, count 0 2006.201.03:04:50.14#ibcon#about to read 4, iclass 30, count 0 2006.201.03:04:50.14#ibcon#read 4, iclass 30, count 0 2006.201.03:04:50.14#ibcon#about to read 5, iclass 30, count 0 2006.201.03:04:50.14#ibcon#read 5, iclass 30, count 0 2006.201.03:04:50.14#ibcon#about to read 6, iclass 30, count 0 2006.201.03:04:50.14#ibcon#read 6, iclass 30, count 0 2006.201.03:04:50.14#ibcon#end of sib2, iclass 30, count 0 2006.201.03:04:50.14#ibcon#*after write, iclass 30, count 0 2006.201.03:04:50.14#ibcon#*before return 0, iclass 30, count 0 2006.201.03:04:50.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:50.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:50.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:04:50.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:04:50.14$vck44/va=8,4 2006.201.03:04:50.14#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.03:04:50.14#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.03:04:50.14#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:50.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:04:50.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:04:50.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:04:50.20#ibcon#enter wrdev, iclass 32, count 2 2006.201.03:04:50.20#ibcon#first serial, iclass 32, count 2 2006.201.03:04:50.20#ibcon#enter sib2, iclass 32, count 2 2006.201.03:04:50.20#ibcon#flushed, iclass 32, count 2 2006.201.03:04:50.20#ibcon#about to write, iclass 32, count 2 2006.201.03:04:50.20#ibcon#wrote, iclass 32, count 2 2006.201.03:04:50.20#ibcon#about to read 3, iclass 32, count 2 2006.201.03:04:50.22#ibcon#read 3, iclass 32, count 2 2006.201.03:04:50.22#ibcon#about to read 4, iclass 32, count 2 2006.201.03:04:50.22#ibcon#read 4, iclass 32, count 2 2006.201.03:04:50.22#ibcon#about to read 5, iclass 32, count 2 2006.201.03:04:50.22#ibcon#read 5, iclass 32, count 2 2006.201.03:04:50.22#ibcon#about to read 6, iclass 32, count 2 2006.201.03:04:50.22#ibcon#read 6, iclass 32, count 2 2006.201.03:04:50.22#ibcon#end of sib2, iclass 32, count 2 2006.201.03:04:50.22#ibcon#*mode == 0, iclass 32, count 2 2006.201.03:04:50.22#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.03:04:50.22#ibcon#[25=AT08-04\r\n] 2006.201.03:04:50.22#ibcon#*before write, iclass 32, count 2 2006.201.03:04:50.22#ibcon#enter sib2, iclass 32, count 2 2006.201.03:04:50.22#ibcon#flushed, iclass 32, count 2 2006.201.03:04:50.22#ibcon#about to write, iclass 32, count 2 2006.201.03:04:50.22#ibcon#wrote, iclass 32, count 2 2006.201.03:04:50.22#ibcon#about to read 3, iclass 32, count 2 2006.201.03:04:50.25#ibcon#read 3, iclass 32, count 2 2006.201.03:04:50.25#ibcon#about to read 4, iclass 32, count 2 2006.201.03:04:50.25#ibcon#read 4, iclass 32, count 2 2006.201.03:04:50.25#ibcon#about to read 5, iclass 32, count 2 2006.201.03:04:50.25#ibcon#read 5, iclass 32, count 2 2006.201.03:04:50.25#ibcon#about to read 6, iclass 32, count 2 2006.201.03:04:50.25#ibcon#read 6, iclass 32, count 2 2006.201.03:04:50.25#ibcon#end of sib2, iclass 32, count 2 2006.201.03:04:50.25#ibcon#*after write, iclass 32, count 2 2006.201.03:04:50.25#ibcon#*before return 0, iclass 32, count 2 2006.201.03:04:50.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:04:50.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:04:50.25#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.03:04:50.25#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:50.25#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:04:50.37#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:04:50.37#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:04:50.37#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:04:50.37#ibcon#first serial, iclass 32, count 0 2006.201.03:04:50.37#ibcon#enter sib2, iclass 32, count 0 2006.201.03:04:50.37#ibcon#flushed, iclass 32, count 0 2006.201.03:04:50.37#ibcon#about to write, iclass 32, count 0 2006.201.03:04:50.37#ibcon#wrote, iclass 32, count 0 2006.201.03:04:50.37#ibcon#about to read 3, iclass 32, count 0 2006.201.03:04:50.39#ibcon#read 3, iclass 32, count 0 2006.201.03:04:50.39#ibcon#about to read 4, iclass 32, count 0 2006.201.03:04:50.39#ibcon#read 4, iclass 32, count 0 2006.201.03:04:50.39#ibcon#about to read 5, iclass 32, count 0 2006.201.03:04:50.39#ibcon#read 5, iclass 32, count 0 2006.201.03:04:50.39#ibcon#about to read 6, iclass 32, count 0 2006.201.03:04:50.39#ibcon#read 6, iclass 32, count 0 2006.201.03:04:50.39#ibcon#end of sib2, iclass 32, count 0 2006.201.03:04:50.39#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:04:50.39#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:04:50.39#ibcon#[25=USB\r\n] 2006.201.03:04:50.39#ibcon#*before write, iclass 32, count 0 2006.201.03:04:50.39#ibcon#enter sib2, iclass 32, count 0 2006.201.03:04:50.39#ibcon#flushed, iclass 32, count 0 2006.201.03:04:50.39#ibcon#about to write, iclass 32, count 0 2006.201.03:04:50.39#ibcon#wrote, iclass 32, count 0 2006.201.03:04:50.39#ibcon#about to read 3, iclass 32, count 0 2006.201.03:04:50.42#ibcon#read 3, iclass 32, count 0 2006.201.03:04:50.42#ibcon#about to read 4, iclass 32, count 0 2006.201.03:04:50.42#ibcon#read 4, iclass 32, count 0 2006.201.03:04:50.42#ibcon#about to read 5, iclass 32, count 0 2006.201.03:04:50.42#ibcon#read 5, iclass 32, count 0 2006.201.03:04:50.42#ibcon#about to read 6, iclass 32, count 0 2006.201.03:04:50.42#ibcon#read 6, iclass 32, count 0 2006.201.03:04:50.42#ibcon#end of sib2, iclass 32, count 0 2006.201.03:04:50.42#ibcon#*after write, iclass 32, count 0 2006.201.03:04:50.42#ibcon#*before return 0, iclass 32, count 0 2006.201.03:04:50.42#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:04:50.42#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:04:50.42#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:04:50.42#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:04:50.42$vck44/vblo=1,629.99 2006.201.03:04:50.42#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.03:04:50.42#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.03:04:50.42#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:50.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:50.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:50.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:50.42#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:04:50.42#ibcon#first serial, iclass 34, count 0 2006.201.03:04:50.42#ibcon#enter sib2, iclass 34, count 0 2006.201.03:04:50.42#ibcon#flushed, iclass 34, count 0 2006.201.03:04:50.42#ibcon#about to write, iclass 34, count 0 2006.201.03:04:50.42#ibcon#wrote, iclass 34, count 0 2006.201.03:04:50.42#ibcon#about to read 3, iclass 34, count 0 2006.201.03:04:50.44#ibcon#read 3, iclass 34, count 0 2006.201.03:04:50.44#ibcon#about to read 4, iclass 34, count 0 2006.201.03:04:50.44#ibcon#read 4, iclass 34, count 0 2006.201.03:04:50.44#ibcon#about to read 5, iclass 34, count 0 2006.201.03:04:50.44#ibcon#read 5, iclass 34, count 0 2006.201.03:04:50.44#ibcon#about to read 6, iclass 34, count 0 2006.201.03:04:50.44#ibcon#read 6, iclass 34, count 0 2006.201.03:04:50.44#ibcon#end of sib2, iclass 34, count 0 2006.201.03:04:50.44#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:04:50.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:04:50.44#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:04:50.44#ibcon#*before write, iclass 34, count 0 2006.201.03:04:50.44#ibcon#enter sib2, iclass 34, count 0 2006.201.03:04:50.44#ibcon#flushed, iclass 34, count 0 2006.201.03:04:50.44#ibcon#about to write, iclass 34, count 0 2006.201.03:04:50.44#ibcon#wrote, iclass 34, count 0 2006.201.03:04:50.44#ibcon#about to read 3, iclass 34, count 0 2006.201.03:04:50.48#ibcon#read 3, iclass 34, count 0 2006.201.03:04:50.48#ibcon#about to read 4, iclass 34, count 0 2006.201.03:04:50.48#ibcon#read 4, iclass 34, count 0 2006.201.03:04:50.48#ibcon#about to read 5, iclass 34, count 0 2006.201.03:04:50.48#ibcon#read 5, iclass 34, count 0 2006.201.03:04:50.48#ibcon#about to read 6, iclass 34, count 0 2006.201.03:04:50.48#ibcon#read 6, iclass 34, count 0 2006.201.03:04:50.48#ibcon#end of sib2, iclass 34, count 0 2006.201.03:04:50.48#ibcon#*after write, iclass 34, count 0 2006.201.03:04:50.48#ibcon#*before return 0, iclass 34, count 0 2006.201.03:04:50.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:50.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:04:50.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:04:50.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:04:50.48$vck44/vb=1,4 2006.201.03:04:50.48#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.03:04:50.48#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.03:04:50.48#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:50.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:50.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:50.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:50.48#ibcon#enter wrdev, iclass 36, count 2 2006.201.03:04:50.48#ibcon#first serial, iclass 36, count 2 2006.201.03:04:50.48#ibcon#enter sib2, iclass 36, count 2 2006.201.03:04:50.48#ibcon#flushed, iclass 36, count 2 2006.201.03:04:50.48#ibcon#about to write, iclass 36, count 2 2006.201.03:04:50.48#ibcon#wrote, iclass 36, count 2 2006.201.03:04:50.48#ibcon#about to read 3, iclass 36, count 2 2006.201.03:04:50.50#ibcon#read 3, iclass 36, count 2 2006.201.03:04:50.50#ibcon#about to read 4, iclass 36, count 2 2006.201.03:04:50.50#ibcon#read 4, iclass 36, count 2 2006.201.03:04:50.50#ibcon#about to read 5, iclass 36, count 2 2006.201.03:04:50.50#ibcon#read 5, iclass 36, count 2 2006.201.03:04:50.50#ibcon#about to read 6, iclass 36, count 2 2006.201.03:04:50.50#ibcon#read 6, iclass 36, count 2 2006.201.03:04:50.50#ibcon#end of sib2, iclass 36, count 2 2006.201.03:04:50.50#ibcon#*mode == 0, iclass 36, count 2 2006.201.03:04:50.50#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.03:04:50.50#ibcon#[27=AT01-04\r\n] 2006.201.03:04:50.50#ibcon#*before write, iclass 36, count 2 2006.201.03:04:50.50#ibcon#enter sib2, iclass 36, count 2 2006.201.03:04:50.50#ibcon#flushed, iclass 36, count 2 2006.201.03:04:50.50#ibcon#about to write, iclass 36, count 2 2006.201.03:04:50.50#ibcon#wrote, iclass 36, count 2 2006.201.03:04:50.50#ibcon#about to read 3, iclass 36, count 2 2006.201.03:04:50.53#ibcon#read 3, iclass 36, count 2 2006.201.03:04:50.53#ibcon#about to read 4, iclass 36, count 2 2006.201.03:04:50.53#ibcon#read 4, iclass 36, count 2 2006.201.03:04:50.53#ibcon#about to read 5, iclass 36, count 2 2006.201.03:04:50.53#ibcon#read 5, iclass 36, count 2 2006.201.03:04:50.53#ibcon#about to read 6, iclass 36, count 2 2006.201.03:04:50.53#ibcon#read 6, iclass 36, count 2 2006.201.03:04:50.53#ibcon#end of sib2, iclass 36, count 2 2006.201.03:04:50.53#ibcon#*after write, iclass 36, count 2 2006.201.03:04:50.53#ibcon#*before return 0, iclass 36, count 2 2006.201.03:04:50.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:50.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:04:50.53#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.03:04:50.53#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:50.53#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:50.65#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:50.65#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:50.65#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:04:50.65#ibcon#first serial, iclass 36, count 0 2006.201.03:04:50.65#ibcon#enter sib2, iclass 36, count 0 2006.201.03:04:50.65#ibcon#flushed, iclass 36, count 0 2006.201.03:04:50.65#ibcon#about to write, iclass 36, count 0 2006.201.03:04:50.65#ibcon#wrote, iclass 36, count 0 2006.201.03:04:50.65#ibcon#about to read 3, iclass 36, count 0 2006.201.03:04:50.67#ibcon#read 3, iclass 36, count 0 2006.201.03:04:50.67#ibcon#about to read 4, iclass 36, count 0 2006.201.03:04:50.67#ibcon#read 4, iclass 36, count 0 2006.201.03:04:50.67#ibcon#about to read 5, iclass 36, count 0 2006.201.03:04:50.67#ibcon#read 5, iclass 36, count 0 2006.201.03:04:50.67#ibcon#about to read 6, iclass 36, count 0 2006.201.03:04:50.67#ibcon#read 6, iclass 36, count 0 2006.201.03:04:50.67#ibcon#end of sib2, iclass 36, count 0 2006.201.03:04:50.67#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:04:50.67#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:04:50.67#ibcon#[27=USB\r\n] 2006.201.03:04:50.67#ibcon#*before write, iclass 36, count 0 2006.201.03:04:50.67#ibcon#enter sib2, iclass 36, count 0 2006.201.03:04:50.67#ibcon#flushed, iclass 36, count 0 2006.201.03:04:50.67#ibcon#about to write, iclass 36, count 0 2006.201.03:04:50.67#ibcon#wrote, iclass 36, count 0 2006.201.03:04:50.67#ibcon#about to read 3, iclass 36, count 0 2006.201.03:04:50.70#ibcon#read 3, iclass 36, count 0 2006.201.03:04:50.70#ibcon#about to read 4, iclass 36, count 0 2006.201.03:04:50.70#ibcon#read 4, iclass 36, count 0 2006.201.03:04:50.70#ibcon#about to read 5, iclass 36, count 0 2006.201.03:04:50.70#ibcon#read 5, iclass 36, count 0 2006.201.03:04:50.70#ibcon#about to read 6, iclass 36, count 0 2006.201.03:04:50.70#ibcon#read 6, iclass 36, count 0 2006.201.03:04:50.70#ibcon#end of sib2, iclass 36, count 0 2006.201.03:04:50.70#ibcon#*after write, iclass 36, count 0 2006.201.03:04:50.70#ibcon#*before return 0, iclass 36, count 0 2006.201.03:04:50.70#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:50.70#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:04:50.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:04:50.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:04:50.70$vck44/vblo=2,634.99 2006.201.03:04:50.70#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.03:04:50.70#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.03:04:50.70#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:50.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:50.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:50.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:50.70#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:04:50.70#ibcon#first serial, iclass 38, count 0 2006.201.03:04:50.70#ibcon#enter sib2, iclass 38, count 0 2006.201.03:04:50.70#ibcon#flushed, iclass 38, count 0 2006.201.03:04:50.70#ibcon#about to write, iclass 38, count 0 2006.201.03:04:50.70#ibcon#wrote, iclass 38, count 0 2006.201.03:04:50.70#ibcon#about to read 3, iclass 38, count 0 2006.201.03:04:50.72#ibcon#read 3, iclass 38, count 0 2006.201.03:04:50.72#ibcon#about to read 4, iclass 38, count 0 2006.201.03:04:50.72#ibcon#read 4, iclass 38, count 0 2006.201.03:04:50.72#ibcon#about to read 5, iclass 38, count 0 2006.201.03:04:50.72#ibcon#read 5, iclass 38, count 0 2006.201.03:04:50.72#ibcon#about to read 6, iclass 38, count 0 2006.201.03:04:50.72#ibcon#read 6, iclass 38, count 0 2006.201.03:04:50.72#ibcon#end of sib2, iclass 38, count 0 2006.201.03:04:50.72#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:04:50.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:04:50.72#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:04:50.72#ibcon#*before write, iclass 38, count 0 2006.201.03:04:50.72#ibcon#enter sib2, iclass 38, count 0 2006.201.03:04:50.72#ibcon#flushed, iclass 38, count 0 2006.201.03:04:50.72#ibcon#about to write, iclass 38, count 0 2006.201.03:04:50.72#ibcon#wrote, iclass 38, count 0 2006.201.03:04:50.72#ibcon#about to read 3, iclass 38, count 0 2006.201.03:04:50.76#ibcon#read 3, iclass 38, count 0 2006.201.03:04:50.76#ibcon#about to read 4, iclass 38, count 0 2006.201.03:04:50.76#ibcon#read 4, iclass 38, count 0 2006.201.03:04:50.76#ibcon#about to read 5, iclass 38, count 0 2006.201.03:04:50.76#ibcon#read 5, iclass 38, count 0 2006.201.03:04:50.76#ibcon#about to read 6, iclass 38, count 0 2006.201.03:04:50.76#ibcon#read 6, iclass 38, count 0 2006.201.03:04:50.76#ibcon#end of sib2, iclass 38, count 0 2006.201.03:04:50.76#ibcon#*after write, iclass 38, count 0 2006.201.03:04:50.76#ibcon#*before return 0, iclass 38, count 0 2006.201.03:04:50.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:50.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:04:50.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:04:50.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:04:50.76$vck44/vb=2,5 2006.201.03:04:50.76#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.03:04:50.76#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.03:04:50.76#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:50.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:50.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:50.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:50.82#ibcon#enter wrdev, iclass 40, count 2 2006.201.03:04:50.82#ibcon#first serial, iclass 40, count 2 2006.201.03:04:50.82#ibcon#enter sib2, iclass 40, count 2 2006.201.03:04:50.82#ibcon#flushed, iclass 40, count 2 2006.201.03:04:50.82#ibcon#about to write, iclass 40, count 2 2006.201.03:04:50.82#ibcon#wrote, iclass 40, count 2 2006.201.03:04:50.82#ibcon#about to read 3, iclass 40, count 2 2006.201.03:04:50.84#ibcon#read 3, iclass 40, count 2 2006.201.03:04:50.84#ibcon#about to read 4, iclass 40, count 2 2006.201.03:04:50.84#ibcon#read 4, iclass 40, count 2 2006.201.03:04:50.84#ibcon#about to read 5, iclass 40, count 2 2006.201.03:04:50.84#ibcon#read 5, iclass 40, count 2 2006.201.03:04:50.84#ibcon#about to read 6, iclass 40, count 2 2006.201.03:04:50.84#ibcon#read 6, iclass 40, count 2 2006.201.03:04:50.84#ibcon#end of sib2, iclass 40, count 2 2006.201.03:04:50.84#ibcon#*mode == 0, iclass 40, count 2 2006.201.03:04:50.84#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.03:04:50.84#ibcon#[27=AT02-05\r\n] 2006.201.03:04:50.84#ibcon#*before write, iclass 40, count 2 2006.201.03:04:50.84#ibcon#enter sib2, iclass 40, count 2 2006.201.03:04:50.84#ibcon#flushed, iclass 40, count 2 2006.201.03:04:50.84#ibcon#about to write, iclass 40, count 2 2006.201.03:04:50.84#ibcon#wrote, iclass 40, count 2 2006.201.03:04:50.84#ibcon#about to read 3, iclass 40, count 2 2006.201.03:04:50.87#ibcon#read 3, iclass 40, count 2 2006.201.03:04:50.87#ibcon#about to read 4, iclass 40, count 2 2006.201.03:04:50.87#ibcon#read 4, iclass 40, count 2 2006.201.03:04:50.87#ibcon#about to read 5, iclass 40, count 2 2006.201.03:04:50.87#ibcon#read 5, iclass 40, count 2 2006.201.03:04:50.87#ibcon#about to read 6, iclass 40, count 2 2006.201.03:04:50.87#ibcon#read 6, iclass 40, count 2 2006.201.03:04:50.87#ibcon#end of sib2, iclass 40, count 2 2006.201.03:04:50.87#ibcon#*after write, iclass 40, count 2 2006.201.03:04:50.87#ibcon#*before return 0, iclass 40, count 2 2006.201.03:04:50.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:50.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:04:50.87#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.03:04:50.87#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:50.87#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:50.99#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:50.99#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:50.99#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:04:50.99#ibcon#first serial, iclass 40, count 0 2006.201.03:04:50.99#ibcon#enter sib2, iclass 40, count 0 2006.201.03:04:50.99#ibcon#flushed, iclass 40, count 0 2006.201.03:04:50.99#ibcon#about to write, iclass 40, count 0 2006.201.03:04:50.99#ibcon#wrote, iclass 40, count 0 2006.201.03:04:50.99#ibcon#about to read 3, iclass 40, count 0 2006.201.03:04:51.01#ibcon#read 3, iclass 40, count 0 2006.201.03:04:51.01#ibcon#about to read 4, iclass 40, count 0 2006.201.03:04:51.01#ibcon#read 4, iclass 40, count 0 2006.201.03:04:51.01#ibcon#about to read 5, iclass 40, count 0 2006.201.03:04:51.01#ibcon#read 5, iclass 40, count 0 2006.201.03:04:51.01#ibcon#about to read 6, iclass 40, count 0 2006.201.03:04:51.01#ibcon#read 6, iclass 40, count 0 2006.201.03:04:51.01#ibcon#end of sib2, iclass 40, count 0 2006.201.03:04:51.01#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:04:51.01#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:04:51.01#ibcon#[27=USB\r\n] 2006.201.03:04:51.01#ibcon#*before write, iclass 40, count 0 2006.201.03:04:51.01#ibcon#enter sib2, iclass 40, count 0 2006.201.03:04:51.01#ibcon#flushed, iclass 40, count 0 2006.201.03:04:51.01#ibcon#about to write, iclass 40, count 0 2006.201.03:04:51.01#ibcon#wrote, iclass 40, count 0 2006.201.03:04:51.01#ibcon#about to read 3, iclass 40, count 0 2006.201.03:04:51.04#ibcon#read 3, iclass 40, count 0 2006.201.03:04:51.04#ibcon#about to read 4, iclass 40, count 0 2006.201.03:04:51.04#ibcon#read 4, iclass 40, count 0 2006.201.03:04:51.04#ibcon#about to read 5, iclass 40, count 0 2006.201.03:04:51.04#ibcon#read 5, iclass 40, count 0 2006.201.03:04:51.04#ibcon#about to read 6, iclass 40, count 0 2006.201.03:04:51.04#ibcon#read 6, iclass 40, count 0 2006.201.03:04:51.04#ibcon#end of sib2, iclass 40, count 0 2006.201.03:04:51.04#ibcon#*after write, iclass 40, count 0 2006.201.03:04:51.04#ibcon#*before return 0, iclass 40, count 0 2006.201.03:04:51.04#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:51.04#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:04:51.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:04:51.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:04:51.04$vck44/vblo=3,649.99 2006.201.03:04:51.04#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.03:04:51.04#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.03:04:51.04#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:51.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:51.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:51.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:51.04#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:04:51.04#ibcon#first serial, iclass 4, count 0 2006.201.03:04:51.04#ibcon#enter sib2, iclass 4, count 0 2006.201.03:04:51.04#ibcon#flushed, iclass 4, count 0 2006.201.03:04:51.04#ibcon#about to write, iclass 4, count 0 2006.201.03:04:51.04#ibcon#wrote, iclass 4, count 0 2006.201.03:04:51.04#ibcon#about to read 3, iclass 4, count 0 2006.201.03:04:51.06#ibcon#read 3, iclass 4, count 0 2006.201.03:04:51.06#ibcon#about to read 4, iclass 4, count 0 2006.201.03:04:51.06#ibcon#read 4, iclass 4, count 0 2006.201.03:04:51.06#ibcon#about to read 5, iclass 4, count 0 2006.201.03:04:51.06#ibcon#read 5, iclass 4, count 0 2006.201.03:04:51.06#ibcon#about to read 6, iclass 4, count 0 2006.201.03:04:51.06#ibcon#read 6, iclass 4, count 0 2006.201.03:04:51.06#ibcon#end of sib2, iclass 4, count 0 2006.201.03:04:51.06#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:04:51.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:04:51.06#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:04:51.06#ibcon#*before write, iclass 4, count 0 2006.201.03:04:51.06#ibcon#enter sib2, iclass 4, count 0 2006.201.03:04:51.06#ibcon#flushed, iclass 4, count 0 2006.201.03:04:51.06#ibcon#about to write, iclass 4, count 0 2006.201.03:04:51.06#ibcon#wrote, iclass 4, count 0 2006.201.03:04:51.06#ibcon#about to read 3, iclass 4, count 0 2006.201.03:04:51.11#ibcon#read 3, iclass 4, count 0 2006.201.03:04:51.11#ibcon#about to read 4, iclass 4, count 0 2006.201.03:04:51.11#ibcon#read 4, iclass 4, count 0 2006.201.03:04:51.11#ibcon#about to read 5, iclass 4, count 0 2006.201.03:04:51.11#ibcon#read 5, iclass 4, count 0 2006.201.03:04:51.11#ibcon#about to read 6, iclass 4, count 0 2006.201.03:04:51.11#ibcon#read 6, iclass 4, count 0 2006.201.03:04:51.11#ibcon#end of sib2, iclass 4, count 0 2006.201.03:04:51.11#ibcon#*after write, iclass 4, count 0 2006.201.03:04:51.11#ibcon#*before return 0, iclass 4, count 0 2006.201.03:04:51.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:51.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:04:51.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:04:51.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:04:51.11$vck44/vb=3,4 2006.201.03:04:51.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.03:04:51.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.03:04:51.11#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:51.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:51.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:51.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:51.16#ibcon#enter wrdev, iclass 6, count 2 2006.201.03:04:51.16#ibcon#first serial, iclass 6, count 2 2006.201.03:04:51.16#ibcon#enter sib2, iclass 6, count 2 2006.201.03:04:51.16#ibcon#flushed, iclass 6, count 2 2006.201.03:04:51.16#ibcon#about to write, iclass 6, count 2 2006.201.03:04:51.16#ibcon#wrote, iclass 6, count 2 2006.201.03:04:51.16#ibcon#about to read 3, iclass 6, count 2 2006.201.03:04:51.18#ibcon#read 3, iclass 6, count 2 2006.201.03:04:51.18#ibcon#about to read 4, iclass 6, count 2 2006.201.03:04:51.18#ibcon#read 4, iclass 6, count 2 2006.201.03:04:51.18#ibcon#about to read 5, iclass 6, count 2 2006.201.03:04:51.18#ibcon#read 5, iclass 6, count 2 2006.201.03:04:51.18#ibcon#about to read 6, iclass 6, count 2 2006.201.03:04:51.18#ibcon#read 6, iclass 6, count 2 2006.201.03:04:51.18#ibcon#end of sib2, iclass 6, count 2 2006.201.03:04:51.18#ibcon#*mode == 0, iclass 6, count 2 2006.201.03:04:51.18#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.03:04:51.18#ibcon#[27=AT03-04\r\n] 2006.201.03:04:51.18#ibcon#*before write, iclass 6, count 2 2006.201.03:04:51.18#ibcon#enter sib2, iclass 6, count 2 2006.201.03:04:51.18#ibcon#flushed, iclass 6, count 2 2006.201.03:04:51.18#ibcon#about to write, iclass 6, count 2 2006.201.03:04:51.18#ibcon#wrote, iclass 6, count 2 2006.201.03:04:51.18#ibcon#about to read 3, iclass 6, count 2 2006.201.03:04:51.21#ibcon#read 3, iclass 6, count 2 2006.201.03:04:51.21#ibcon#about to read 4, iclass 6, count 2 2006.201.03:04:51.21#ibcon#read 4, iclass 6, count 2 2006.201.03:04:51.21#ibcon#about to read 5, iclass 6, count 2 2006.201.03:04:51.21#ibcon#read 5, iclass 6, count 2 2006.201.03:04:51.21#ibcon#about to read 6, iclass 6, count 2 2006.201.03:04:51.21#ibcon#read 6, iclass 6, count 2 2006.201.03:04:51.21#ibcon#end of sib2, iclass 6, count 2 2006.201.03:04:51.21#ibcon#*after write, iclass 6, count 2 2006.201.03:04:51.21#ibcon#*before return 0, iclass 6, count 2 2006.201.03:04:51.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:51.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:04:51.21#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.03:04:51.21#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:51.21#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:51.33#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:51.33#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:51.33#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:04:51.33#ibcon#first serial, iclass 6, count 0 2006.201.03:04:51.33#ibcon#enter sib2, iclass 6, count 0 2006.201.03:04:51.33#ibcon#flushed, iclass 6, count 0 2006.201.03:04:51.33#ibcon#about to write, iclass 6, count 0 2006.201.03:04:51.33#ibcon#wrote, iclass 6, count 0 2006.201.03:04:51.33#ibcon#about to read 3, iclass 6, count 0 2006.201.03:04:51.35#ibcon#read 3, iclass 6, count 0 2006.201.03:04:51.35#ibcon#about to read 4, iclass 6, count 0 2006.201.03:04:51.35#ibcon#read 4, iclass 6, count 0 2006.201.03:04:51.35#ibcon#about to read 5, iclass 6, count 0 2006.201.03:04:51.35#ibcon#read 5, iclass 6, count 0 2006.201.03:04:51.35#ibcon#about to read 6, iclass 6, count 0 2006.201.03:04:51.35#ibcon#read 6, iclass 6, count 0 2006.201.03:04:51.35#ibcon#end of sib2, iclass 6, count 0 2006.201.03:04:51.35#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:04:51.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:04:51.35#ibcon#[27=USB\r\n] 2006.201.03:04:51.35#ibcon#*before write, iclass 6, count 0 2006.201.03:04:51.35#ibcon#enter sib2, iclass 6, count 0 2006.201.03:04:51.35#ibcon#flushed, iclass 6, count 0 2006.201.03:04:51.35#ibcon#about to write, iclass 6, count 0 2006.201.03:04:51.35#ibcon#wrote, iclass 6, count 0 2006.201.03:04:51.35#ibcon#about to read 3, iclass 6, count 0 2006.201.03:04:51.38#ibcon#read 3, iclass 6, count 0 2006.201.03:04:51.38#ibcon#about to read 4, iclass 6, count 0 2006.201.03:04:51.38#ibcon#read 4, iclass 6, count 0 2006.201.03:04:51.38#ibcon#about to read 5, iclass 6, count 0 2006.201.03:04:51.38#ibcon#read 5, iclass 6, count 0 2006.201.03:04:51.38#ibcon#about to read 6, iclass 6, count 0 2006.201.03:04:51.38#ibcon#read 6, iclass 6, count 0 2006.201.03:04:51.38#ibcon#end of sib2, iclass 6, count 0 2006.201.03:04:51.38#ibcon#*after write, iclass 6, count 0 2006.201.03:04:51.38#ibcon#*before return 0, iclass 6, count 0 2006.201.03:04:51.38#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:51.38#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:04:51.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:04:51.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:04:51.38$vck44/vblo=4,679.99 2006.201.03:04:51.38#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.03:04:51.38#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.03:04:51.38#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:51.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:51.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:51.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:51.38#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:04:51.38#ibcon#first serial, iclass 10, count 0 2006.201.03:04:51.38#ibcon#enter sib2, iclass 10, count 0 2006.201.03:04:51.38#ibcon#flushed, iclass 10, count 0 2006.201.03:04:51.38#ibcon#about to write, iclass 10, count 0 2006.201.03:04:51.38#ibcon#wrote, iclass 10, count 0 2006.201.03:04:51.38#ibcon#about to read 3, iclass 10, count 0 2006.201.03:04:51.40#ibcon#read 3, iclass 10, count 0 2006.201.03:04:51.40#ibcon#about to read 4, iclass 10, count 0 2006.201.03:04:51.40#ibcon#read 4, iclass 10, count 0 2006.201.03:04:51.40#ibcon#about to read 5, iclass 10, count 0 2006.201.03:04:51.40#ibcon#read 5, iclass 10, count 0 2006.201.03:04:51.40#ibcon#about to read 6, iclass 10, count 0 2006.201.03:04:51.40#ibcon#read 6, iclass 10, count 0 2006.201.03:04:51.40#ibcon#end of sib2, iclass 10, count 0 2006.201.03:04:51.40#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:04:51.40#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:04:51.40#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:04:51.40#ibcon#*before write, iclass 10, count 0 2006.201.03:04:51.40#ibcon#enter sib2, iclass 10, count 0 2006.201.03:04:51.40#ibcon#flushed, iclass 10, count 0 2006.201.03:04:51.40#ibcon#about to write, iclass 10, count 0 2006.201.03:04:51.40#ibcon#wrote, iclass 10, count 0 2006.201.03:04:51.40#ibcon#about to read 3, iclass 10, count 0 2006.201.03:04:51.44#ibcon#read 3, iclass 10, count 0 2006.201.03:04:51.44#ibcon#about to read 4, iclass 10, count 0 2006.201.03:04:51.44#ibcon#read 4, iclass 10, count 0 2006.201.03:04:51.44#ibcon#about to read 5, iclass 10, count 0 2006.201.03:04:51.44#ibcon#read 5, iclass 10, count 0 2006.201.03:04:51.44#ibcon#about to read 6, iclass 10, count 0 2006.201.03:04:51.44#ibcon#read 6, iclass 10, count 0 2006.201.03:04:51.44#ibcon#end of sib2, iclass 10, count 0 2006.201.03:04:51.44#ibcon#*after write, iclass 10, count 0 2006.201.03:04:51.44#ibcon#*before return 0, iclass 10, count 0 2006.201.03:04:51.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:51.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:04:51.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:04:51.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:04:51.44$vck44/vb=4,5 2006.201.03:04:51.44#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.03:04:51.44#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.03:04:51.44#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:51.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:51.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:51.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:51.50#ibcon#enter wrdev, iclass 12, count 2 2006.201.03:04:51.50#ibcon#first serial, iclass 12, count 2 2006.201.03:04:51.50#ibcon#enter sib2, iclass 12, count 2 2006.201.03:04:51.50#ibcon#flushed, iclass 12, count 2 2006.201.03:04:51.50#ibcon#about to write, iclass 12, count 2 2006.201.03:04:51.50#ibcon#wrote, iclass 12, count 2 2006.201.03:04:51.50#ibcon#about to read 3, iclass 12, count 2 2006.201.03:04:51.52#ibcon#read 3, iclass 12, count 2 2006.201.03:04:51.52#ibcon#about to read 4, iclass 12, count 2 2006.201.03:04:51.52#ibcon#read 4, iclass 12, count 2 2006.201.03:04:51.52#ibcon#about to read 5, iclass 12, count 2 2006.201.03:04:51.52#ibcon#read 5, iclass 12, count 2 2006.201.03:04:51.52#ibcon#about to read 6, iclass 12, count 2 2006.201.03:04:51.52#ibcon#read 6, iclass 12, count 2 2006.201.03:04:51.52#ibcon#end of sib2, iclass 12, count 2 2006.201.03:04:51.52#ibcon#*mode == 0, iclass 12, count 2 2006.201.03:04:51.52#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.03:04:51.52#ibcon#[27=AT04-05\r\n] 2006.201.03:04:51.52#ibcon#*before write, iclass 12, count 2 2006.201.03:04:51.52#ibcon#enter sib2, iclass 12, count 2 2006.201.03:04:51.52#ibcon#flushed, iclass 12, count 2 2006.201.03:04:51.52#ibcon#about to write, iclass 12, count 2 2006.201.03:04:51.52#ibcon#wrote, iclass 12, count 2 2006.201.03:04:51.52#ibcon#about to read 3, iclass 12, count 2 2006.201.03:04:51.55#ibcon#read 3, iclass 12, count 2 2006.201.03:04:51.55#ibcon#about to read 4, iclass 12, count 2 2006.201.03:04:51.55#ibcon#read 4, iclass 12, count 2 2006.201.03:04:51.55#ibcon#about to read 5, iclass 12, count 2 2006.201.03:04:51.55#ibcon#read 5, iclass 12, count 2 2006.201.03:04:51.55#ibcon#about to read 6, iclass 12, count 2 2006.201.03:04:51.55#ibcon#read 6, iclass 12, count 2 2006.201.03:04:51.55#ibcon#end of sib2, iclass 12, count 2 2006.201.03:04:51.55#ibcon#*after write, iclass 12, count 2 2006.201.03:04:51.55#ibcon#*before return 0, iclass 12, count 2 2006.201.03:04:51.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:51.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:04:51.55#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.03:04:51.55#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:51.55#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:51.67#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:51.67#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:51.67#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:04:51.67#ibcon#first serial, iclass 12, count 0 2006.201.03:04:51.67#ibcon#enter sib2, iclass 12, count 0 2006.201.03:04:51.67#ibcon#flushed, iclass 12, count 0 2006.201.03:04:51.67#ibcon#about to write, iclass 12, count 0 2006.201.03:04:51.67#ibcon#wrote, iclass 12, count 0 2006.201.03:04:51.67#ibcon#about to read 3, iclass 12, count 0 2006.201.03:04:51.69#ibcon#read 3, iclass 12, count 0 2006.201.03:04:51.69#ibcon#about to read 4, iclass 12, count 0 2006.201.03:04:51.69#ibcon#read 4, iclass 12, count 0 2006.201.03:04:51.69#ibcon#about to read 5, iclass 12, count 0 2006.201.03:04:51.69#ibcon#read 5, iclass 12, count 0 2006.201.03:04:51.69#ibcon#about to read 6, iclass 12, count 0 2006.201.03:04:51.69#ibcon#read 6, iclass 12, count 0 2006.201.03:04:51.69#ibcon#end of sib2, iclass 12, count 0 2006.201.03:04:51.69#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:04:51.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:04:51.69#ibcon#[27=USB\r\n] 2006.201.03:04:51.69#ibcon#*before write, iclass 12, count 0 2006.201.03:04:51.69#ibcon#enter sib2, iclass 12, count 0 2006.201.03:04:51.69#ibcon#flushed, iclass 12, count 0 2006.201.03:04:51.69#ibcon#about to write, iclass 12, count 0 2006.201.03:04:51.69#ibcon#wrote, iclass 12, count 0 2006.201.03:04:51.69#ibcon#about to read 3, iclass 12, count 0 2006.201.03:04:51.72#ibcon#read 3, iclass 12, count 0 2006.201.03:04:51.72#ibcon#about to read 4, iclass 12, count 0 2006.201.03:04:51.72#ibcon#read 4, iclass 12, count 0 2006.201.03:04:51.72#ibcon#about to read 5, iclass 12, count 0 2006.201.03:04:51.72#ibcon#read 5, iclass 12, count 0 2006.201.03:04:51.72#ibcon#about to read 6, iclass 12, count 0 2006.201.03:04:51.72#ibcon#read 6, iclass 12, count 0 2006.201.03:04:51.72#ibcon#end of sib2, iclass 12, count 0 2006.201.03:04:51.72#ibcon#*after write, iclass 12, count 0 2006.201.03:04:51.72#ibcon#*before return 0, iclass 12, count 0 2006.201.03:04:51.72#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:51.72#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:04:51.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:04:51.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:04:51.72$vck44/vblo=5,709.99 2006.201.03:04:51.72#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.03:04:51.72#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.03:04:51.72#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:51.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:51.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:51.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:51.72#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:04:51.72#ibcon#first serial, iclass 14, count 0 2006.201.03:04:51.72#ibcon#enter sib2, iclass 14, count 0 2006.201.03:04:51.72#ibcon#flushed, iclass 14, count 0 2006.201.03:04:51.72#ibcon#about to write, iclass 14, count 0 2006.201.03:04:51.72#ibcon#wrote, iclass 14, count 0 2006.201.03:04:51.72#ibcon#about to read 3, iclass 14, count 0 2006.201.03:04:51.74#ibcon#read 3, iclass 14, count 0 2006.201.03:04:51.74#ibcon#about to read 4, iclass 14, count 0 2006.201.03:04:51.74#ibcon#read 4, iclass 14, count 0 2006.201.03:04:51.74#ibcon#about to read 5, iclass 14, count 0 2006.201.03:04:51.74#ibcon#read 5, iclass 14, count 0 2006.201.03:04:51.74#ibcon#about to read 6, iclass 14, count 0 2006.201.03:04:51.74#ibcon#read 6, iclass 14, count 0 2006.201.03:04:51.74#ibcon#end of sib2, iclass 14, count 0 2006.201.03:04:51.74#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:04:51.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:04:51.74#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:04:51.74#ibcon#*before write, iclass 14, count 0 2006.201.03:04:51.74#ibcon#enter sib2, iclass 14, count 0 2006.201.03:04:51.74#ibcon#flushed, iclass 14, count 0 2006.201.03:04:51.74#ibcon#about to write, iclass 14, count 0 2006.201.03:04:51.74#ibcon#wrote, iclass 14, count 0 2006.201.03:04:51.74#ibcon#about to read 3, iclass 14, count 0 2006.201.03:04:51.78#ibcon#read 3, iclass 14, count 0 2006.201.03:04:51.78#ibcon#about to read 4, iclass 14, count 0 2006.201.03:04:51.78#ibcon#read 4, iclass 14, count 0 2006.201.03:04:51.78#ibcon#about to read 5, iclass 14, count 0 2006.201.03:04:51.78#ibcon#read 5, iclass 14, count 0 2006.201.03:04:51.78#ibcon#about to read 6, iclass 14, count 0 2006.201.03:04:51.78#ibcon#read 6, iclass 14, count 0 2006.201.03:04:51.78#ibcon#end of sib2, iclass 14, count 0 2006.201.03:04:51.78#ibcon#*after write, iclass 14, count 0 2006.201.03:04:51.78#ibcon#*before return 0, iclass 14, count 0 2006.201.03:04:51.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:51.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:04:51.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:04:51.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:04:51.78$vck44/vb=5,4 2006.201.03:04:51.78#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.03:04:51.78#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.03:04:51.78#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:51.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:51.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:51.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:51.84#ibcon#enter wrdev, iclass 16, count 2 2006.201.03:04:51.84#ibcon#first serial, iclass 16, count 2 2006.201.03:04:51.84#ibcon#enter sib2, iclass 16, count 2 2006.201.03:04:51.84#ibcon#flushed, iclass 16, count 2 2006.201.03:04:51.84#ibcon#about to write, iclass 16, count 2 2006.201.03:04:51.84#ibcon#wrote, iclass 16, count 2 2006.201.03:04:51.84#ibcon#about to read 3, iclass 16, count 2 2006.201.03:04:51.86#ibcon#read 3, iclass 16, count 2 2006.201.03:04:51.86#ibcon#about to read 4, iclass 16, count 2 2006.201.03:04:51.86#ibcon#read 4, iclass 16, count 2 2006.201.03:04:51.86#ibcon#about to read 5, iclass 16, count 2 2006.201.03:04:51.86#ibcon#read 5, iclass 16, count 2 2006.201.03:04:51.86#ibcon#about to read 6, iclass 16, count 2 2006.201.03:04:51.86#ibcon#read 6, iclass 16, count 2 2006.201.03:04:51.86#ibcon#end of sib2, iclass 16, count 2 2006.201.03:04:51.86#ibcon#*mode == 0, iclass 16, count 2 2006.201.03:04:51.86#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.03:04:51.86#ibcon#[27=AT05-04\r\n] 2006.201.03:04:51.86#ibcon#*before write, iclass 16, count 2 2006.201.03:04:51.86#ibcon#enter sib2, iclass 16, count 2 2006.201.03:04:51.86#ibcon#flushed, iclass 16, count 2 2006.201.03:04:51.86#ibcon#about to write, iclass 16, count 2 2006.201.03:04:51.86#ibcon#wrote, iclass 16, count 2 2006.201.03:04:51.86#ibcon#about to read 3, iclass 16, count 2 2006.201.03:04:51.89#ibcon#read 3, iclass 16, count 2 2006.201.03:04:51.89#ibcon#about to read 4, iclass 16, count 2 2006.201.03:04:51.89#ibcon#read 4, iclass 16, count 2 2006.201.03:04:51.89#ibcon#about to read 5, iclass 16, count 2 2006.201.03:04:51.89#ibcon#read 5, iclass 16, count 2 2006.201.03:04:51.89#ibcon#about to read 6, iclass 16, count 2 2006.201.03:04:51.89#ibcon#read 6, iclass 16, count 2 2006.201.03:04:51.89#ibcon#end of sib2, iclass 16, count 2 2006.201.03:04:51.89#ibcon#*after write, iclass 16, count 2 2006.201.03:04:51.89#ibcon#*before return 0, iclass 16, count 2 2006.201.03:04:51.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:51.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:04:51.89#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.03:04:51.89#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:51.89#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:52.01#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:52.01#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:52.01#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:04:52.01#ibcon#first serial, iclass 16, count 0 2006.201.03:04:52.01#ibcon#enter sib2, iclass 16, count 0 2006.201.03:04:52.01#ibcon#flushed, iclass 16, count 0 2006.201.03:04:52.01#ibcon#about to write, iclass 16, count 0 2006.201.03:04:52.01#ibcon#wrote, iclass 16, count 0 2006.201.03:04:52.01#ibcon#about to read 3, iclass 16, count 0 2006.201.03:04:52.03#ibcon#read 3, iclass 16, count 0 2006.201.03:04:52.03#ibcon#about to read 4, iclass 16, count 0 2006.201.03:04:52.03#ibcon#read 4, iclass 16, count 0 2006.201.03:04:52.03#ibcon#about to read 5, iclass 16, count 0 2006.201.03:04:52.03#ibcon#read 5, iclass 16, count 0 2006.201.03:04:52.03#ibcon#about to read 6, iclass 16, count 0 2006.201.03:04:52.03#ibcon#read 6, iclass 16, count 0 2006.201.03:04:52.03#ibcon#end of sib2, iclass 16, count 0 2006.201.03:04:52.03#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:04:52.03#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:04:52.03#ibcon#[27=USB\r\n] 2006.201.03:04:52.03#ibcon#*before write, iclass 16, count 0 2006.201.03:04:52.03#ibcon#enter sib2, iclass 16, count 0 2006.201.03:04:52.03#ibcon#flushed, iclass 16, count 0 2006.201.03:04:52.03#ibcon#about to write, iclass 16, count 0 2006.201.03:04:52.03#ibcon#wrote, iclass 16, count 0 2006.201.03:04:52.03#ibcon#about to read 3, iclass 16, count 0 2006.201.03:04:52.06#ibcon#read 3, iclass 16, count 0 2006.201.03:04:52.06#ibcon#about to read 4, iclass 16, count 0 2006.201.03:04:52.06#ibcon#read 4, iclass 16, count 0 2006.201.03:04:52.06#ibcon#about to read 5, iclass 16, count 0 2006.201.03:04:52.06#ibcon#read 5, iclass 16, count 0 2006.201.03:04:52.06#ibcon#about to read 6, iclass 16, count 0 2006.201.03:04:52.06#ibcon#read 6, iclass 16, count 0 2006.201.03:04:52.06#ibcon#end of sib2, iclass 16, count 0 2006.201.03:04:52.06#ibcon#*after write, iclass 16, count 0 2006.201.03:04:52.06#ibcon#*before return 0, iclass 16, count 0 2006.201.03:04:52.06#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:52.06#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:04:52.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:04:52.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:04:52.06$vck44/vblo=6,719.99 2006.201.03:04:52.06#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.03:04:52.06#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.03:04:52.06#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:52.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:52.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:52.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:52.06#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:04:52.06#ibcon#first serial, iclass 18, count 0 2006.201.03:04:52.06#ibcon#enter sib2, iclass 18, count 0 2006.201.03:04:52.06#ibcon#flushed, iclass 18, count 0 2006.201.03:04:52.06#ibcon#about to write, iclass 18, count 0 2006.201.03:04:52.06#ibcon#wrote, iclass 18, count 0 2006.201.03:04:52.06#ibcon#about to read 3, iclass 18, count 0 2006.201.03:04:52.08#ibcon#read 3, iclass 18, count 0 2006.201.03:04:52.08#ibcon#about to read 4, iclass 18, count 0 2006.201.03:04:52.08#ibcon#read 4, iclass 18, count 0 2006.201.03:04:52.08#ibcon#about to read 5, iclass 18, count 0 2006.201.03:04:52.08#ibcon#read 5, iclass 18, count 0 2006.201.03:04:52.08#ibcon#about to read 6, iclass 18, count 0 2006.201.03:04:52.08#ibcon#read 6, iclass 18, count 0 2006.201.03:04:52.08#ibcon#end of sib2, iclass 18, count 0 2006.201.03:04:52.08#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:04:52.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:04:52.08#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:04:52.08#ibcon#*before write, iclass 18, count 0 2006.201.03:04:52.08#ibcon#enter sib2, iclass 18, count 0 2006.201.03:04:52.08#ibcon#flushed, iclass 18, count 0 2006.201.03:04:52.08#ibcon#about to write, iclass 18, count 0 2006.201.03:04:52.08#ibcon#wrote, iclass 18, count 0 2006.201.03:04:52.08#ibcon#about to read 3, iclass 18, count 0 2006.201.03:04:52.12#ibcon#read 3, iclass 18, count 0 2006.201.03:04:52.12#ibcon#about to read 4, iclass 18, count 0 2006.201.03:04:52.12#ibcon#read 4, iclass 18, count 0 2006.201.03:04:52.12#ibcon#about to read 5, iclass 18, count 0 2006.201.03:04:52.12#ibcon#read 5, iclass 18, count 0 2006.201.03:04:52.12#ibcon#about to read 6, iclass 18, count 0 2006.201.03:04:52.12#ibcon#read 6, iclass 18, count 0 2006.201.03:04:52.12#ibcon#end of sib2, iclass 18, count 0 2006.201.03:04:52.12#ibcon#*after write, iclass 18, count 0 2006.201.03:04:52.12#ibcon#*before return 0, iclass 18, count 0 2006.201.03:04:52.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:52.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:04:52.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:04:52.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:04:52.12$vck44/vb=6,4 2006.201.03:04:52.12#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.03:04:52.12#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.03:04:52.12#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:52.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:52.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:52.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:52.18#ibcon#enter wrdev, iclass 20, count 2 2006.201.03:04:52.18#ibcon#first serial, iclass 20, count 2 2006.201.03:04:52.18#ibcon#enter sib2, iclass 20, count 2 2006.201.03:04:52.18#ibcon#flushed, iclass 20, count 2 2006.201.03:04:52.18#ibcon#about to write, iclass 20, count 2 2006.201.03:04:52.18#ibcon#wrote, iclass 20, count 2 2006.201.03:04:52.18#ibcon#about to read 3, iclass 20, count 2 2006.201.03:04:52.20#ibcon#read 3, iclass 20, count 2 2006.201.03:04:52.20#ibcon#about to read 4, iclass 20, count 2 2006.201.03:04:52.20#ibcon#read 4, iclass 20, count 2 2006.201.03:04:52.20#ibcon#about to read 5, iclass 20, count 2 2006.201.03:04:52.20#ibcon#read 5, iclass 20, count 2 2006.201.03:04:52.20#ibcon#about to read 6, iclass 20, count 2 2006.201.03:04:52.20#ibcon#read 6, iclass 20, count 2 2006.201.03:04:52.20#ibcon#end of sib2, iclass 20, count 2 2006.201.03:04:52.20#ibcon#*mode == 0, iclass 20, count 2 2006.201.03:04:52.20#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.03:04:52.20#ibcon#[27=AT06-04\r\n] 2006.201.03:04:52.20#ibcon#*before write, iclass 20, count 2 2006.201.03:04:52.20#ibcon#enter sib2, iclass 20, count 2 2006.201.03:04:52.20#ibcon#flushed, iclass 20, count 2 2006.201.03:04:52.20#ibcon#about to write, iclass 20, count 2 2006.201.03:04:52.20#ibcon#wrote, iclass 20, count 2 2006.201.03:04:52.20#ibcon#about to read 3, iclass 20, count 2 2006.201.03:04:52.23#ibcon#read 3, iclass 20, count 2 2006.201.03:04:52.23#ibcon#about to read 4, iclass 20, count 2 2006.201.03:04:52.23#ibcon#read 4, iclass 20, count 2 2006.201.03:04:52.23#ibcon#about to read 5, iclass 20, count 2 2006.201.03:04:52.23#ibcon#read 5, iclass 20, count 2 2006.201.03:04:52.23#ibcon#about to read 6, iclass 20, count 2 2006.201.03:04:52.23#ibcon#read 6, iclass 20, count 2 2006.201.03:04:52.23#ibcon#end of sib2, iclass 20, count 2 2006.201.03:04:52.23#ibcon#*after write, iclass 20, count 2 2006.201.03:04:52.23#ibcon#*before return 0, iclass 20, count 2 2006.201.03:04:52.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:52.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:04:52.23#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.03:04:52.23#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:52.23#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:52.35#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:52.35#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:52.35#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:04:52.35#ibcon#first serial, iclass 20, count 0 2006.201.03:04:52.35#ibcon#enter sib2, iclass 20, count 0 2006.201.03:04:52.35#ibcon#flushed, iclass 20, count 0 2006.201.03:04:52.35#ibcon#about to write, iclass 20, count 0 2006.201.03:04:52.35#ibcon#wrote, iclass 20, count 0 2006.201.03:04:52.35#ibcon#about to read 3, iclass 20, count 0 2006.201.03:04:52.37#ibcon#read 3, iclass 20, count 0 2006.201.03:04:52.37#ibcon#about to read 4, iclass 20, count 0 2006.201.03:04:52.37#ibcon#read 4, iclass 20, count 0 2006.201.03:04:52.37#ibcon#about to read 5, iclass 20, count 0 2006.201.03:04:52.37#ibcon#read 5, iclass 20, count 0 2006.201.03:04:52.37#ibcon#about to read 6, iclass 20, count 0 2006.201.03:04:52.37#ibcon#read 6, iclass 20, count 0 2006.201.03:04:52.37#ibcon#end of sib2, iclass 20, count 0 2006.201.03:04:52.37#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:04:52.37#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:04:52.37#ibcon#[27=USB\r\n] 2006.201.03:04:52.37#ibcon#*before write, iclass 20, count 0 2006.201.03:04:52.37#ibcon#enter sib2, iclass 20, count 0 2006.201.03:04:52.37#ibcon#flushed, iclass 20, count 0 2006.201.03:04:52.37#ibcon#about to write, iclass 20, count 0 2006.201.03:04:52.37#ibcon#wrote, iclass 20, count 0 2006.201.03:04:52.37#ibcon#about to read 3, iclass 20, count 0 2006.201.03:04:52.40#ibcon#read 3, iclass 20, count 0 2006.201.03:04:52.40#ibcon#about to read 4, iclass 20, count 0 2006.201.03:04:52.40#ibcon#read 4, iclass 20, count 0 2006.201.03:04:52.40#ibcon#about to read 5, iclass 20, count 0 2006.201.03:04:52.40#ibcon#read 5, iclass 20, count 0 2006.201.03:04:52.40#ibcon#about to read 6, iclass 20, count 0 2006.201.03:04:52.40#ibcon#read 6, iclass 20, count 0 2006.201.03:04:52.40#ibcon#end of sib2, iclass 20, count 0 2006.201.03:04:52.40#ibcon#*after write, iclass 20, count 0 2006.201.03:04:52.40#ibcon#*before return 0, iclass 20, count 0 2006.201.03:04:52.40#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:52.40#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:04:52.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:04:52.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:04:52.40$vck44/vblo=7,734.99 2006.201.03:04:52.40#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.03:04:52.40#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.03:04:52.40#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:52.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:52.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:52.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:52.40#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:04:52.40#ibcon#first serial, iclass 22, count 0 2006.201.03:04:52.40#ibcon#enter sib2, iclass 22, count 0 2006.201.03:04:52.40#ibcon#flushed, iclass 22, count 0 2006.201.03:04:52.40#ibcon#about to write, iclass 22, count 0 2006.201.03:04:52.40#ibcon#wrote, iclass 22, count 0 2006.201.03:04:52.40#ibcon#about to read 3, iclass 22, count 0 2006.201.03:04:52.42#ibcon#read 3, iclass 22, count 0 2006.201.03:04:52.42#ibcon#about to read 4, iclass 22, count 0 2006.201.03:04:52.42#ibcon#read 4, iclass 22, count 0 2006.201.03:04:52.42#ibcon#about to read 5, iclass 22, count 0 2006.201.03:04:52.42#ibcon#read 5, iclass 22, count 0 2006.201.03:04:52.42#ibcon#about to read 6, iclass 22, count 0 2006.201.03:04:52.42#ibcon#read 6, iclass 22, count 0 2006.201.03:04:52.42#ibcon#end of sib2, iclass 22, count 0 2006.201.03:04:52.42#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:04:52.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:04:52.42#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:04:52.42#ibcon#*before write, iclass 22, count 0 2006.201.03:04:52.42#ibcon#enter sib2, iclass 22, count 0 2006.201.03:04:52.42#ibcon#flushed, iclass 22, count 0 2006.201.03:04:52.42#ibcon#about to write, iclass 22, count 0 2006.201.03:04:52.42#ibcon#wrote, iclass 22, count 0 2006.201.03:04:52.42#ibcon#about to read 3, iclass 22, count 0 2006.201.03:04:52.46#ibcon#read 3, iclass 22, count 0 2006.201.03:04:52.46#ibcon#about to read 4, iclass 22, count 0 2006.201.03:04:52.46#ibcon#read 4, iclass 22, count 0 2006.201.03:04:52.46#ibcon#about to read 5, iclass 22, count 0 2006.201.03:04:52.46#ibcon#read 5, iclass 22, count 0 2006.201.03:04:52.46#ibcon#about to read 6, iclass 22, count 0 2006.201.03:04:52.46#ibcon#read 6, iclass 22, count 0 2006.201.03:04:52.46#ibcon#end of sib2, iclass 22, count 0 2006.201.03:04:52.46#ibcon#*after write, iclass 22, count 0 2006.201.03:04:52.46#ibcon#*before return 0, iclass 22, count 0 2006.201.03:04:52.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:52.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:04:52.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:04:52.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:04:52.46$vck44/vb=7,4 2006.201.03:04:52.46#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.03:04:52.46#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.03:04:52.46#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:52.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:52.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:52.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:52.52#ibcon#enter wrdev, iclass 24, count 2 2006.201.03:04:52.52#ibcon#first serial, iclass 24, count 2 2006.201.03:04:52.52#ibcon#enter sib2, iclass 24, count 2 2006.201.03:04:52.52#ibcon#flushed, iclass 24, count 2 2006.201.03:04:52.52#ibcon#about to write, iclass 24, count 2 2006.201.03:04:52.52#ibcon#wrote, iclass 24, count 2 2006.201.03:04:52.52#ibcon#about to read 3, iclass 24, count 2 2006.201.03:04:52.54#ibcon#read 3, iclass 24, count 2 2006.201.03:04:52.54#ibcon#about to read 4, iclass 24, count 2 2006.201.03:04:52.54#ibcon#read 4, iclass 24, count 2 2006.201.03:04:52.54#ibcon#about to read 5, iclass 24, count 2 2006.201.03:04:52.54#ibcon#read 5, iclass 24, count 2 2006.201.03:04:52.54#ibcon#about to read 6, iclass 24, count 2 2006.201.03:04:52.54#ibcon#read 6, iclass 24, count 2 2006.201.03:04:52.54#ibcon#end of sib2, iclass 24, count 2 2006.201.03:04:52.54#ibcon#*mode == 0, iclass 24, count 2 2006.201.03:04:52.54#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.03:04:52.54#ibcon#[27=AT07-04\r\n] 2006.201.03:04:52.54#ibcon#*before write, iclass 24, count 2 2006.201.03:04:52.54#ibcon#enter sib2, iclass 24, count 2 2006.201.03:04:52.54#ibcon#flushed, iclass 24, count 2 2006.201.03:04:52.54#ibcon#about to write, iclass 24, count 2 2006.201.03:04:52.54#ibcon#wrote, iclass 24, count 2 2006.201.03:04:52.54#ibcon#about to read 3, iclass 24, count 2 2006.201.03:04:52.57#ibcon#read 3, iclass 24, count 2 2006.201.03:04:52.57#ibcon#about to read 4, iclass 24, count 2 2006.201.03:04:52.57#ibcon#read 4, iclass 24, count 2 2006.201.03:04:52.57#ibcon#about to read 5, iclass 24, count 2 2006.201.03:04:52.57#ibcon#read 5, iclass 24, count 2 2006.201.03:04:52.57#ibcon#about to read 6, iclass 24, count 2 2006.201.03:04:52.57#ibcon#read 6, iclass 24, count 2 2006.201.03:04:52.57#ibcon#end of sib2, iclass 24, count 2 2006.201.03:04:52.57#ibcon#*after write, iclass 24, count 2 2006.201.03:04:52.57#ibcon#*before return 0, iclass 24, count 2 2006.201.03:04:52.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:52.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:04:52.57#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.03:04:52.57#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:52.57#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:52.69#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:52.69#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:52.69#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:04:52.69#ibcon#first serial, iclass 24, count 0 2006.201.03:04:52.69#ibcon#enter sib2, iclass 24, count 0 2006.201.03:04:52.69#ibcon#flushed, iclass 24, count 0 2006.201.03:04:52.69#ibcon#about to write, iclass 24, count 0 2006.201.03:04:52.69#ibcon#wrote, iclass 24, count 0 2006.201.03:04:52.69#ibcon#about to read 3, iclass 24, count 0 2006.201.03:04:52.71#ibcon#read 3, iclass 24, count 0 2006.201.03:04:52.71#ibcon#about to read 4, iclass 24, count 0 2006.201.03:04:52.71#ibcon#read 4, iclass 24, count 0 2006.201.03:04:52.71#ibcon#about to read 5, iclass 24, count 0 2006.201.03:04:52.71#ibcon#read 5, iclass 24, count 0 2006.201.03:04:52.71#ibcon#about to read 6, iclass 24, count 0 2006.201.03:04:52.71#ibcon#read 6, iclass 24, count 0 2006.201.03:04:52.71#ibcon#end of sib2, iclass 24, count 0 2006.201.03:04:52.71#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:04:52.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:04:52.71#ibcon#[27=USB\r\n] 2006.201.03:04:52.71#ibcon#*before write, iclass 24, count 0 2006.201.03:04:52.71#ibcon#enter sib2, iclass 24, count 0 2006.201.03:04:52.71#ibcon#flushed, iclass 24, count 0 2006.201.03:04:52.71#ibcon#about to write, iclass 24, count 0 2006.201.03:04:52.71#ibcon#wrote, iclass 24, count 0 2006.201.03:04:52.71#ibcon#about to read 3, iclass 24, count 0 2006.201.03:04:52.74#ibcon#read 3, iclass 24, count 0 2006.201.03:04:52.74#ibcon#about to read 4, iclass 24, count 0 2006.201.03:04:52.74#ibcon#read 4, iclass 24, count 0 2006.201.03:04:52.74#ibcon#about to read 5, iclass 24, count 0 2006.201.03:04:52.74#ibcon#read 5, iclass 24, count 0 2006.201.03:04:52.74#ibcon#about to read 6, iclass 24, count 0 2006.201.03:04:52.74#ibcon#read 6, iclass 24, count 0 2006.201.03:04:52.74#ibcon#end of sib2, iclass 24, count 0 2006.201.03:04:52.74#ibcon#*after write, iclass 24, count 0 2006.201.03:04:52.74#ibcon#*before return 0, iclass 24, count 0 2006.201.03:04:52.74#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:52.74#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:04:52.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:04:52.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:04:52.74$vck44/vblo=8,744.99 2006.201.03:04:52.74#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.03:04:52.74#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.03:04:52.74#ibcon#ireg 17 cls_cnt 0 2006.201.03:04:52.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:04:52.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:04:52.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:04:52.74#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:04:52.74#ibcon#first serial, iclass 26, count 0 2006.201.03:04:52.74#ibcon#enter sib2, iclass 26, count 0 2006.201.03:04:52.74#ibcon#flushed, iclass 26, count 0 2006.201.03:04:52.74#ibcon#about to write, iclass 26, count 0 2006.201.03:04:52.74#ibcon#wrote, iclass 26, count 0 2006.201.03:04:52.74#ibcon#about to read 3, iclass 26, count 0 2006.201.03:04:52.76#ibcon#read 3, iclass 26, count 0 2006.201.03:04:52.76#ibcon#about to read 4, iclass 26, count 0 2006.201.03:04:52.76#ibcon#read 4, iclass 26, count 0 2006.201.03:04:52.76#ibcon#about to read 5, iclass 26, count 0 2006.201.03:04:52.76#ibcon#read 5, iclass 26, count 0 2006.201.03:04:52.76#ibcon#about to read 6, iclass 26, count 0 2006.201.03:04:52.76#ibcon#read 6, iclass 26, count 0 2006.201.03:04:52.76#ibcon#end of sib2, iclass 26, count 0 2006.201.03:04:52.76#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:04:52.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:04:52.76#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:04:52.76#ibcon#*before write, iclass 26, count 0 2006.201.03:04:52.76#ibcon#enter sib2, iclass 26, count 0 2006.201.03:04:52.76#ibcon#flushed, iclass 26, count 0 2006.201.03:04:52.76#ibcon#about to write, iclass 26, count 0 2006.201.03:04:52.76#ibcon#wrote, iclass 26, count 0 2006.201.03:04:52.76#ibcon#about to read 3, iclass 26, count 0 2006.201.03:04:52.81#ibcon#read 3, iclass 26, count 0 2006.201.03:04:52.81#ibcon#about to read 4, iclass 26, count 0 2006.201.03:04:52.81#ibcon#read 4, iclass 26, count 0 2006.201.03:04:52.81#ibcon#about to read 5, iclass 26, count 0 2006.201.03:04:52.81#ibcon#read 5, iclass 26, count 0 2006.201.03:04:52.81#ibcon#about to read 6, iclass 26, count 0 2006.201.03:04:52.81#ibcon#read 6, iclass 26, count 0 2006.201.03:04:52.81#ibcon#end of sib2, iclass 26, count 0 2006.201.03:04:52.81#ibcon#*after write, iclass 26, count 0 2006.201.03:04:52.81#ibcon#*before return 0, iclass 26, count 0 2006.201.03:04:52.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:04:52.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:04:52.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:04:52.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:04:52.81$vck44/vb=8,4 2006.201.03:04:52.81#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.03:04:52.81#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.03:04:52.81#ibcon#ireg 11 cls_cnt 2 2006.201.03:04:52.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:04:52.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:04:52.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:04:52.86#ibcon#enter wrdev, iclass 28, count 2 2006.201.03:04:52.86#ibcon#first serial, iclass 28, count 2 2006.201.03:04:52.86#ibcon#enter sib2, iclass 28, count 2 2006.201.03:04:52.86#ibcon#flushed, iclass 28, count 2 2006.201.03:04:52.86#ibcon#about to write, iclass 28, count 2 2006.201.03:04:52.86#ibcon#wrote, iclass 28, count 2 2006.201.03:04:52.86#ibcon#about to read 3, iclass 28, count 2 2006.201.03:04:52.88#ibcon#read 3, iclass 28, count 2 2006.201.03:04:52.88#ibcon#about to read 4, iclass 28, count 2 2006.201.03:04:52.88#ibcon#read 4, iclass 28, count 2 2006.201.03:04:52.88#ibcon#about to read 5, iclass 28, count 2 2006.201.03:04:52.88#ibcon#read 5, iclass 28, count 2 2006.201.03:04:52.88#ibcon#about to read 6, iclass 28, count 2 2006.201.03:04:52.88#ibcon#read 6, iclass 28, count 2 2006.201.03:04:52.88#ibcon#end of sib2, iclass 28, count 2 2006.201.03:04:52.88#ibcon#*mode == 0, iclass 28, count 2 2006.201.03:04:52.88#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.03:04:52.88#ibcon#[27=AT08-04\r\n] 2006.201.03:04:52.88#ibcon#*before write, iclass 28, count 2 2006.201.03:04:52.88#ibcon#enter sib2, iclass 28, count 2 2006.201.03:04:52.88#ibcon#flushed, iclass 28, count 2 2006.201.03:04:52.88#ibcon#about to write, iclass 28, count 2 2006.201.03:04:52.88#ibcon#wrote, iclass 28, count 2 2006.201.03:04:52.88#ibcon#about to read 3, iclass 28, count 2 2006.201.03:04:52.91#ibcon#read 3, iclass 28, count 2 2006.201.03:04:52.91#ibcon#about to read 4, iclass 28, count 2 2006.201.03:04:52.91#ibcon#read 4, iclass 28, count 2 2006.201.03:04:52.91#ibcon#about to read 5, iclass 28, count 2 2006.201.03:04:52.91#ibcon#read 5, iclass 28, count 2 2006.201.03:04:52.91#ibcon#about to read 6, iclass 28, count 2 2006.201.03:04:52.91#ibcon#read 6, iclass 28, count 2 2006.201.03:04:52.91#ibcon#end of sib2, iclass 28, count 2 2006.201.03:04:52.91#ibcon#*after write, iclass 28, count 2 2006.201.03:04:52.91#ibcon#*before return 0, iclass 28, count 2 2006.201.03:04:52.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:04:52.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:04:52.91#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.03:04:52.91#ibcon#ireg 7 cls_cnt 0 2006.201.03:04:52.91#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:04:53.03#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:04:53.03#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:04:53.03#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:04:53.03#ibcon#first serial, iclass 28, count 0 2006.201.03:04:53.03#ibcon#enter sib2, iclass 28, count 0 2006.201.03:04:53.03#ibcon#flushed, iclass 28, count 0 2006.201.03:04:53.03#ibcon#about to write, iclass 28, count 0 2006.201.03:04:53.03#ibcon#wrote, iclass 28, count 0 2006.201.03:04:53.03#ibcon#about to read 3, iclass 28, count 0 2006.201.03:04:53.05#ibcon#read 3, iclass 28, count 0 2006.201.03:04:53.05#ibcon#about to read 4, iclass 28, count 0 2006.201.03:04:53.05#ibcon#read 4, iclass 28, count 0 2006.201.03:04:53.05#ibcon#about to read 5, iclass 28, count 0 2006.201.03:04:53.05#ibcon#read 5, iclass 28, count 0 2006.201.03:04:53.05#ibcon#about to read 6, iclass 28, count 0 2006.201.03:04:53.05#ibcon#read 6, iclass 28, count 0 2006.201.03:04:53.05#ibcon#end of sib2, iclass 28, count 0 2006.201.03:04:53.05#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:04:53.05#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:04:53.05#ibcon#[27=USB\r\n] 2006.201.03:04:53.05#ibcon#*before write, iclass 28, count 0 2006.201.03:04:53.05#ibcon#enter sib2, iclass 28, count 0 2006.201.03:04:53.05#ibcon#flushed, iclass 28, count 0 2006.201.03:04:53.05#ibcon#about to write, iclass 28, count 0 2006.201.03:04:53.05#ibcon#wrote, iclass 28, count 0 2006.201.03:04:53.05#ibcon#about to read 3, iclass 28, count 0 2006.201.03:04:53.08#ibcon#read 3, iclass 28, count 0 2006.201.03:04:53.08#ibcon#about to read 4, iclass 28, count 0 2006.201.03:04:53.08#ibcon#read 4, iclass 28, count 0 2006.201.03:04:53.08#ibcon#about to read 5, iclass 28, count 0 2006.201.03:04:53.08#ibcon#read 5, iclass 28, count 0 2006.201.03:04:53.08#ibcon#about to read 6, iclass 28, count 0 2006.201.03:04:53.08#ibcon#read 6, iclass 28, count 0 2006.201.03:04:53.08#ibcon#end of sib2, iclass 28, count 0 2006.201.03:04:53.08#ibcon#*after write, iclass 28, count 0 2006.201.03:04:53.08#ibcon#*before return 0, iclass 28, count 0 2006.201.03:04:53.08#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:04:53.08#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:04:53.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:04:53.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:04:53.08$vck44/vabw=wide 2006.201.03:04:53.08#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.03:04:53.08#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.03:04:53.08#ibcon#ireg 8 cls_cnt 0 2006.201.03:04:53.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:53.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:53.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:53.08#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:04:53.08#ibcon#first serial, iclass 30, count 0 2006.201.03:04:53.08#ibcon#enter sib2, iclass 30, count 0 2006.201.03:04:53.08#ibcon#flushed, iclass 30, count 0 2006.201.03:04:53.08#ibcon#about to write, iclass 30, count 0 2006.201.03:04:53.08#ibcon#wrote, iclass 30, count 0 2006.201.03:04:53.08#ibcon#about to read 3, iclass 30, count 0 2006.201.03:04:53.10#ibcon#read 3, iclass 30, count 0 2006.201.03:04:53.10#ibcon#about to read 4, iclass 30, count 0 2006.201.03:04:53.10#ibcon#read 4, iclass 30, count 0 2006.201.03:04:53.10#ibcon#about to read 5, iclass 30, count 0 2006.201.03:04:53.10#ibcon#read 5, iclass 30, count 0 2006.201.03:04:53.10#ibcon#about to read 6, iclass 30, count 0 2006.201.03:04:53.10#ibcon#read 6, iclass 30, count 0 2006.201.03:04:53.10#ibcon#end of sib2, iclass 30, count 0 2006.201.03:04:53.10#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:04:53.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:04:53.10#ibcon#[25=BW32\r\n] 2006.201.03:04:53.10#ibcon#*before write, iclass 30, count 0 2006.201.03:04:53.10#ibcon#enter sib2, iclass 30, count 0 2006.201.03:04:53.10#ibcon#flushed, iclass 30, count 0 2006.201.03:04:53.10#ibcon#about to write, iclass 30, count 0 2006.201.03:04:53.10#ibcon#wrote, iclass 30, count 0 2006.201.03:04:53.10#ibcon#about to read 3, iclass 30, count 0 2006.201.03:04:53.13#ibcon#read 3, iclass 30, count 0 2006.201.03:04:53.13#ibcon#about to read 4, iclass 30, count 0 2006.201.03:04:53.13#ibcon#read 4, iclass 30, count 0 2006.201.03:04:53.13#ibcon#about to read 5, iclass 30, count 0 2006.201.03:04:53.13#ibcon#read 5, iclass 30, count 0 2006.201.03:04:53.13#ibcon#about to read 6, iclass 30, count 0 2006.201.03:04:53.13#ibcon#read 6, iclass 30, count 0 2006.201.03:04:53.13#ibcon#end of sib2, iclass 30, count 0 2006.201.03:04:53.13#ibcon#*after write, iclass 30, count 0 2006.201.03:04:53.13#ibcon#*before return 0, iclass 30, count 0 2006.201.03:04:53.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:53.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:04:53.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:04:53.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:04:53.13$vck44/vbbw=wide 2006.201.03:04:53.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.03:04:53.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.03:04:53.13#ibcon#ireg 8 cls_cnt 0 2006.201.03:04:53.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:04:53.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:04:53.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:04:53.20#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:04:53.20#ibcon#first serial, iclass 32, count 0 2006.201.03:04:53.20#ibcon#enter sib2, iclass 32, count 0 2006.201.03:04:53.20#ibcon#flushed, iclass 32, count 0 2006.201.03:04:53.20#ibcon#about to write, iclass 32, count 0 2006.201.03:04:53.20#ibcon#wrote, iclass 32, count 0 2006.201.03:04:53.20#ibcon#about to read 3, iclass 32, count 0 2006.201.03:04:53.22#ibcon#read 3, iclass 32, count 0 2006.201.03:04:53.22#ibcon#about to read 4, iclass 32, count 0 2006.201.03:04:53.22#ibcon#read 4, iclass 32, count 0 2006.201.03:04:53.22#ibcon#about to read 5, iclass 32, count 0 2006.201.03:04:53.22#ibcon#read 5, iclass 32, count 0 2006.201.03:04:53.22#ibcon#about to read 6, iclass 32, count 0 2006.201.03:04:53.22#ibcon#read 6, iclass 32, count 0 2006.201.03:04:53.22#ibcon#end of sib2, iclass 32, count 0 2006.201.03:04:53.22#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:04:53.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:04:53.22#ibcon#[27=BW32\r\n] 2006.201.03:04:53.22#ibcon#*before write, iclass 32, count 0 2006.201.03:04:53.22#ibcon#enter sib2, iclass 32, count 0 2006.201.03:04:53.22#ibcon#flushed, iclass 32, count 0 2006.201.03:04:53.22#ibcon#about to write, iclass 32, count 0 2006.201.03:04:53.22#ibcon#wrote, iclass 32, count 0 2006.201.03:04:53.22#ibcon#about to read 3, iclass 32, count 0 2006.201.03:04:53.25#ibcon#read 3, iclass 32, count 0 2006.201.03:04:53.25#ibcon#about to read 4, iclass 32, count 0 2006.201.03:04:53.25#ibcon#read 4, iclass 32, count 0 2006.201.03:04:53.25#ibcon#about to read 5, iclass 32, count 0 2006.201.03:04:53.25#ibcon#read 5, iclass 32, count 0 2006.201.03:04:53.25#ibcon#about to read 6, iclass 32, count 0 2006.201.03:04:53.25#ibcon#read 6, iclass 32, count 0 2006.201.03:04:53.25#ibcon#end of sib2, iclass 32, count 0 2006.201.03:04:53.25#ibcon#*after write, iclass 32, count 0 2006.201.03:04:53.25#ibcon#*before return 0, iclass 32, count 0 2006.201.03:04:53.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:04:53.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:04:53.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:04:53.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:04:53.25$setupk4/ifdk4 2006.201.03:04:53.25$ifdk4/lo= 2006.201.03:04:53.25$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:04:53.25$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:04:53.25$ifdk4/patch= 2006.201.03:04:53.25$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:04:53.25$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:04:53.25$setupk4/!*+20s 2006.201.03:05:00.15#abcon#<5=/03 2.4 4.1 22.85 941004.5\r\n> 2006.201.03:05:00.17#abcon#{5=INTERFACE CLEAR} 2006.201.03:05:00.23#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:05:07.73$setupk4/"tpicd 2006.201.03:05:07.73$setupk4/echo=off 2006.201.03:05:07.73$setupk4/xlog=off 2006.201.03:05:07.73:!2006.201.03:14:31 2006.201.03:05:15.13#trakl#Source acquired 2006.201.03:05:17.13#flagr#flagr/antenna,acquired 2006.201.03:14:31.00:preob 2006.201.03:14:31.13/onsource/TRACKING 2006.201.03:14:31.13:!2006.201.03:14:41 2006.201.03:14:41.00:"tape 2006.201.03:14:41.00:"st=record 2006.201.03:14:41.00:data_valid=on 2006.201.03:14:41.00:midob 2006.201.03:14:41.13/onsource/TRACKING 2006.201.03:14:41.13/wx/22.82,1004.4,92 2006.201.03:14:41.21/cable/+6.4663E-03 2006.201.03:14:42.30/va/01,08,usb,yes,29,31 2006.201.03:14:42.30/va/02,07,usb,yes,31,32 2006.201.03:14:42.30/va/03,08,usb,yes,28,29 2006.201.03:14:42.30/va/04,07,usb,yes,32,34 2006.201.03:14:42.30/va/05,04,usb,yes,28,29 2006.201.03:14:42.30/va/06,05,usb,yes,28,28 2006.201.03:14:42.30/va/07,05,usb,yes,27,29 2006.201.03:14:42.30/va/08,04,usb,yes,27,33 2006.201.03:14:42.53/valo/01,524.99,yes,locked 2006.201.03:14:42.53/valo/02,534.99,yes,locked 2006.201.03:14:42.53/valo/03,564.99,yes,locked 2006.201.03:14:42.53/valo/04,624.99,yes,locked 2006.201.03:14:42.53/valo/05,734.99,yes,locked 2006.201.03:14:42.53/valo/06,814.99,yes,locked 2006.201.03:14:42.53/valo/07,864.99,yes,locked 2006.201.03:14:42.53/valo/08,884.99,yes,locked 2006.201.03:14:43.62/vb/01,04,usb,yes,29,27 2006.201.03:14:43.62/vb/02,05,usb,yes,27,27 2006.201.03:14:43.62/vb/03,04,usb,yes,28,31 2006.201.03:14:43.62/vb/04,05,usb,yes,29,28 2006.201.03:14:43.62/vb/05,04,usb,yes,25,28 2006.201.03:14:43.62/vb/06,04,usb,yes,30,26 2006.201.03:14:43.62/vb/07,04,usb,yes,29,29 2006.201.03:14:43.62/vb/08,04,usb,yes,27,30 2006.201.03:14:43.86/vblo/01,629.99,yes,locked 2006.201.03:14:43.86/vblo/02,634.99,yes,locked 2006.201.03:14:43.86/vblo/03,649.99,yes,locked 2006.201.03:14:43.86/vblo/04,679.99,yes,locked 2006.201.03:14:43.86/vblo/05,709.99,yes,locked 2006.201.03:14:43.86/vblo/06,719.99,yes,locked 2006.201.03:14:43.86/vblo/07,734.99,yes,locked 2006.201.03:14:43.86/vblo/08,744.99,yes,locked 2006.201.03:14:44.01/vabw/8 2006.201.03:14:44.16/vbbw/8 2006.201.03:14:44.32/xfe/off,on,15.2 2006.201.03:14:44.69/ifatt/23,28,28,28 2006.201.03:14:45.03/fmout-gps/S +4.46E-07 2006.201.03:14:45.10:!2006.201.03:21:11 2006.201.03:21:11.00:data_valid=off 2006.201.03:21:11.00:"et 2006.201.03:21:11.00:!+3s 2006.201.03:21:14.02:"tape 2006.201.03:21:14.02:postob 2006.201.03:21:14.15/cable/+6.4676E-03 2006.201.03:21:14.15/wx/22.89,1004.3,92 2006.201.03:21:14.21/fmout-gps/S +4.46E-07 2006.201.03:21:14.21:scan_name=201-0328,jd0607,40 2006.201.03:21:14.22:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.201.03:21:15.14#flagr#flagr/antenna,new-source 2006.201.03:21:15.14:checkk5 2006.201.03:21:15.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:21:15.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:21:16.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:21:16.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:21:17.05/chk_obsdata//k5ts1/T2010314??a.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.201.03:21:17.42/chk_obsdata//k5ts2/T2010314??b.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.201.03:21:17.79/chk_obsdata//k5ts3/T2010314??c.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.201.03:21:18.16/chk_obsdata//k5ts4/T2010314??d.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.201.03:21:18.86/k5log//k5ts1_log_newline 2006.201.03:21:19.56/k5log//k5ts2_log_newline 2006.201.03:21:20.25/k5log//k5ts3_log_newline 2006.201.03:21:20.94/k5log//k5ts4_log_newline 2006.201.03:21:20.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:21:20.97:setupk4=1 2006.201.03:21:20.97$setupk4/echo=on 2006.201.03:21:20.97$setupk4/pcalon 2006.201.03:21:20.97$pcalon/"no phase cal control is implemented here 2006.201.03:21:20.97$setupk4/"tpicd=stop 2006.201.03:21:20.97$setupk4/"rec=synch_on 2006.201.03:21:20.97$setupk4/"rec_mode=128 2006.201.03:21:20.97$setupk4/!* 2006.201.03:21:20.97$setupk4/recpk4 2006.201.03:21:20.97$recpk4/recpatch= 2006.201.03:21:20.97$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:21:20.97$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:21:20.97$setupk4/vck44 2006.201.03:21:20.97$vck44/valo=1,524.99 2006.201.03:21:20.97#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.03:21:20.97#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.03:21:20.97#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:20.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:20.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:20.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:20.97#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:21:20.97#ibcon#first serial, iclass 24, count 0 2006.201.03:21:20.97#ibcon#enter sib2, iclass 24, count 0 2006.201.03:21:20.97#ibcon#flushed, iclass 24, count 0 2006.201.03:21:20.97#ibcon#about to write, iclass 24, count 0 2006.201.03:21:20.97#ibcon#wrote, iclass 24, count 0 2006.201.03:21:20.97#ibcon#about to read 3, iclass 24, count 0 2006.201.03:21:21.01#ibcon#read 3, iclass 24, count 0 2006.201.03:21:21.01#ibcon#about to read 4, iclass 24, count 0 2006.201.03:21:21.01#ibcon#read 4, iclass 24, count 0 2006.201.03:21:21.01#ibcon#about to read 5, iclass 24, count 0 2006.201.03:21:21.01#ibcon#read 5, iclass 24, count 0 2006.201.03:21:21.01#ibcon#about to read 6, iclass 24, count 0 2006.201.03:21:21.01#ibcon#read 6, iclass 24, count 0 2006.201.03:21:21.01#ibcon#end of sib2, iclass 24, count 0 2006.201.03:21:21.01#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:21:21.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:21:21.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:21:21.01#ibcon#*before write, iclass 24, count 0 2006.201.03:21:21.01#ibcon#enter sib2, iclass 24, count 0 2006.201.03:21:21.01#ibcon#flushed, iclass 24, count 0 2006.201.03:21:21.01#ibcon#about to write, iclass 24, count 0 2006.201.03:21:21.01#ibcon#wrote, iclass 24, count 0 2006.201.03:21:21.01#ibcon#about to read 3, iclass 24, count 0 2006.201.03:21:21.06#ibcon#read 3, iclass 24, count 0 2006.201.03:21:21.06#ibcon#about to read 4, iclass 24, count 0 2006.201.03:21:21.06#ibcon#read 4, iclass 24, count 0 2006.201.03:21:21.06#ibcon#about to read 5, iclass 24, count 0 2006.201.03:21:21.06#ibcon#read 5, iclass 24, count 0 2006.201.03:21:21.06#ibcon#about to read 6, iclass 24, count 0 2006.201.03:21:21.06#ibcon#read 6, iclass 24, count 0 2006.201.03:21:21.06#ibcon#end of sib2, iclass 24, count 0 2006.201.03:21:21.06#ibcon#*after write, iclass 24, count 0 2006.201.03:21:21.06#ibcon#*before return 0, iclass 24, count 0 2006.201.03:21:21.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:21.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:21.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:21:21.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:21:21.06$vck44/va=1,8 2006.201.03:21:21.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.03:21:21.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.03:21:21.06#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:21.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:21.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:21.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:21.06#ibcon#enter wrdev, iclass 26, count 2 2006.201.03:21:21.06#ibcon#first serial, iclass 26, count 2 2006.201.03:21:21.06#ibcon#enter sib2, iclass 26, count 2 2006.201.03:21:21.06#ibcon#flushed, iclass 26, count 2 2006.201.03:21:21.06#ibcon#about to write, iclass 26, count 2 2006.201.03:21:21.06#ibcon#wrote, iclass 26, count 2 2006.201.03:21:21.06#ibcon#about to read 3, iclass 26, count 2 2006.201.03:21:21.08#ibcon#read 3, iclass 26, count 2 2006.201.03:21:21.08#ibcon#about to read 4, iclass 26, count 2 2006.201.03:21:21.08#ibcon#read 4, iclass 26, count 2 2006.201.03:21:21.08#ibcon#about to read 5, iclass 26, count 2 2006.201.03:21:21.08#ibcon#read 5, iclass 26, count 2 2006.201.03:21:21.08#ibcon#about to read 6, iclass 26, count 2 2006.201.03:21:21.08#ibcon#read 6, iclass 26, count 2 2006.201.03:21:21.08#ibcon#end of sib2, iclass 26, count 2 2006.201.03:21:21.08#ibcon#*mode == 0, iclass 26, count 2 2006.201.03:21:21.08#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.03:21:21.08#ibcon#[25=AT01-08\r\n] 2006.201.03:21:21.08#ibcon#*before write, iclass 26, count 2 2006.201.03:21:21.08#ibcon#enter sib2, iclass 26, count 2 2006.201.03:21:21.08#ibcon#flushed, iclass 26, count 2 2006.201.03:21:21.08#ibcon#about to write, iclass 26, count 2 2006.201.03:21:21.08#ibcon#wrote, iclass 26, count 2 2006.201.03:21:21.08#ibcon#about to read 3, iclass 26, count 2 2006.201.03:21:21.11#ibcon#read 3, iclass 26, count 2 2006.201.03:21:21.11#ibcon#about to read 4, iclass 26, count 2 2006.201.03:21:21.11#ibcon#read 4, iclass 26, count 2 2006.201.03:21:21.11#ibcon#about to read 5, iclass 26, count 2 2006.201.03:21:21.11#ibcon#read 5, iclass 26, count 2 2006.201.03:21:21.11#ibcon#about to read 6, iclass 26, count 2 2006.201.03:21:21.11#ibcon#read 6, iclass 26, count 2 2006.201.03:21:21.11#ibcon#end of sib2, iclass 26, count 2 2006.201.03:21:21.11#ibcon#*after write, iclass 26, count 2 2006.201.03:21:21.11#ibcon#*before return 0, iclass 26, count 2 2006.201.03:21:21.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:21.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:21.11#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.03:21:21.11#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:21.11#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:21.23#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:21.23#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:21.23#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:21:21.23#ibcon#first serial, iclass 26, count 0 2006.201.03:21:21.23#ibcon#enter sib2, iclass 26, count 0 2006.201.03:21:21.23#ibcon#flushed, iclass 26, count 0 2006.201.03:21:21.23#ibcon#about to write, iclass 26, count 0 2006.201.03:21:21.23#ibcon#wrote, iclass 26, count 0 2006.201.03:21:21.23#ibcon#about to read 3, iclass 26, count 0 2006.201.03:21:21.25#ibcon#read 3, iclass 26, count 0 2006.201.03:21:21.25#ibcon#about to read 4, iclass 26, count 0 2006.201.03:21:21.25#ibcon#read 4, iclass 26, count 0 2006.201.03:21:21.25#ibcon#about to read 5, iclass 26, count 0 2006.201.03:21:21.25#ibcon#read 5, iclass 26, count 0 2006.201.03:21:21.25#ibcon#about to read 6, iclass 26, count 0 2006.201.03:21:21.25#ibcon#read 6, iclass 26, count 0 2006.201.03:21:21.25#ibcon#end of sib2, iclass 26, count 0 2006.201.03:21:21.25#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:21:21.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:21:21.25#ibcon#[25=USB\r\n] 2006.201.03:21:21.25#ibcon#*before write, iclass 26, count 0 2006.201.03:21:21.25#ibcon#enter sib2, iclass 26, count 0 2006.201.03:21:21.25#ibcon#flushed, iclass 26, count 0 2006.201.03:21:21.25#ibcon#about to write, iclass 26, count 0 2006.201.03:21:21.25#ibcon#wrote, iclass 26, count 0 2006.201.03:21:21.25#ibcon#about to read 3, iclass 26, count 0 2006.201.03:21:21.28#ibcon#read 3, iclass 26, count 0 2006.201.03:21:21.28#ibcon#about to read 4, iclass 26, count 0 2006.201.03:21:21.28#ibcon#read 4, iclass 26, count 0 2006.201.03:21:21.28#ibcon#about to read 5, iclass 26, count 0 2006.201.03:21:21.28#ibcon#read 5, iclass 26, count 0 2006.201.03:21:21.28#ibcon#about to read 6, iclass 26, count 0 2006.201.03:21:21.28#ibcon#read 6, iclass 26, count 0 2006.201.03:21:21.28#ibcon#end of sib2, iclass 26, count 0 2006.201.03:21:21.28#ibcon#*after write, iclass 26, count 0 2006.201.03:21:21.28#ibcon#*before return 0, iclass 26, count 0 2006.201.03:21:21.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:21.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:21.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:21:21.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:21:21.28$vck44/valo=2,534.99 2006.201.03:21:21.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.03:21:21.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.03:21:21.28#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:21.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:21.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:21.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:21.28#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:21:21.28#ibcon#first serial, iclass 28, count 0 2006.201.03:21:21.28#ibcon#enter sib2, iclass 28, count 0 2006.201.03:21:21.28#ibcon#flushed, iclass 28, count 0 2006.201.03:21:21.28#ibcon#about to write, iclass 28, count 0 2006.201.03:21:21.28#ibcon#wrote, iclass 28, count 0 2006.201.03:21:21.28#ibcon#about to read 3, iclass 28, count 0 2006.201.03:21:21.30#ibcon#read 3, iclass 28, count 0 2006.201.03:21:21.30#ibcon#about to read 4, iclass 28, count 0 2006.201.03:21:21.30#ibcon#read 4, iclass 28, count 0 2006.201.03:21:21.30#ibcon#about to read 5, iclass 28, count 0 2006.201.03:21:21.30#ibcon#read 5, iclass 28, count 0 2006.201.03:21:21.30#ibcon#about to read 6, iclass 28, count 0 2006.201.03:21:21.30#ibcon#read 6, iclass 28, count 0 2006.201.03:21:21.30#ibcon#end of sib2, iclass 28, count 0 2006.201.03:21:21.30#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:21:21.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:21:21.30#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:21:21.30#ibcon#*before write, iclass 28, count 0 2006.201.03:21:21.30#ibcon#enter sib2, iclass 28, count 0 2006.201.03:21:21.30#ibcon#flushed, iclass 28, count 0 2006.201.03:21:21.30#ibcon#about to write, iclass 28, count 0 2006.201.03:21:21.30#ibcon#wrote, iclass 28, count 0 2006.201.03:21:21.30#ibcon#about to read 3, iclass 28, count 0 2006.201.03:21:21.34#ibcon#read 3, iclass 28, count 0 2006.201.03:21:21.34#ibcon#about to read 4, iclass 28, count 0 2006.201.03:21:21.34#ibcon#read 4, iclass 28, count 0 2006.201.03:21:21.34#ibcon#about to read 5, iclass 28, count 0 2006.201.03:21:21.34#ibcon#read 5, iclass 28, count 0 2006.201.03:21:21.34#ibcon#about to read 6, iclass 28, count 0 2006.201.03:21:21.34#ibcon#read 6, iclass 28, count 0 2006.201.03:21:21.34#ibcon#end of sib2, iclass 28, count 0 2006.201.03:21:21.34#ibcon#*after write, iclass 28, count 0 2006.201.03:21:21.34#ibcon#*before return 0, iclass 28, count 0 2006.201.03:21:21.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:21.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:21.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:21:21.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:21:21.34$vck44/va=2,7 2006.201.03:21:21.34#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.03:21:21.34#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.03:21:21.34#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:21.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:21.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:21.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:21.40#ibcon#enter wrdev, iclass 30, count 2 2006.201.03:21:21.40#ibcon#first serial, iclass 30, count 2 2006.201.03:21:21.40#ibcon#enter sib2, iclass 30, count 2 2006.201.03:21:21.40#ibcon#flushed, iclass 30, count 2 2006.201.03:21:21.40#ibcon#about to write, iclass 30, count 2 2006.201.03:21:21.40#ibcon#wrote, iclass 30, count 2 2006.201.03:21:21.40#ibcon#about to read 3, iclass 30, count 2 2006.201.03:21:21.42#ibcon#read 3, iclass 30, count 2 2006.201.03:21:21.42#ibcon#about to read 4, iclass 30, count 2 2006.201.03:21:21.42#ibcon#read 4, iclass 30, count 2 2006.201.03:21:21.42#ibcon#about to read 5, iclass 30, count 2 2006.201.03:21:21.42#ibcon#read 5, iclass 30, count 2 2006.201.03:21:21.42#ibcon#about to read 6, iclass 30, count 2 2006.201.03:21:21.42#ibcon#read 6, iclass 30, count 2 2006.201.03:21:21.42#ibcon#end of sib2, iclass 30, count 2 2006.201.03:21:21.42#ibcon#*mode == 0, iclass 30, count 2 2006.201.03:21:21.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.03:21:21.42#ibcon#[25=AT02-07\r\n] 2006.201.03:21:21.42#ibcon#*before write, iclass 30, count 2 2006.201.03:21:21.42#ibcon#enter sib2, iclass 30, count 2 2006.201.03:21:21.42#ibcon#flushed, iclass 30, count 2 2006.201.03:21:21.42#ibcon#about to write, iclass 30, count 2 2006.201.03:21:21.42#ibcon#wrote, iclass 30, count 2 2006.201.03:21:21.42#ibcon#about to read 3, iclass 30, count 2 2006.201.03:21:21.45#ibcon#read 3, iclass 30, count 2 2006.201.03:21:21.45#ibcon#about to read 4, iclass 30, count 2 2006.201.03:21:21.45#ibcon#read 4, iclass 30, count 2 2006.201.03:21:21.45#ibcon#about to read 5, iclass 30, count 2 2006.201.03:21:21.45#ibcon#read 5, iclass 30, count 2 2006.201.03:21:21.45#ibcon#about to read 6, iclass 30, count 2 2006.201.03:21:21.45#ibcon#read 6, iclass 30, count 2 2006.201.03:21:21.45#ibcon#end of sib2, iclass 30, count 2 2006.201.03:21:21.45#ibcon#*after write, iclass 30, count 2 2006.201.03:21:21.45#ibcon#*before return 0, iclass 30, count 2 2006.201.03:21:21.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:21.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:21.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.03:21:21.45#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:21.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:21.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:21.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:21.57#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:21:21.57#ibcon#first serial, iclass 30, count 0 2006.201.03:21:21.57#ibcon#enter sib2, iclass 30, count 0 2006.201.03:21:21.57#ibcon#flushed, iclass 30, count 0 2006.201.03:21:21.57#ibcon#about to write, iclass 30, count 0 2006.201.03:21:21.57#ibcon#wrote, iclass 30, count 0 2006.201.03:21:21.57#ibcon#about to read 3, iclass 30, count 0 2006.201.03:21:21.59#ibcon#read 3, iclass 30, count 0 2006.201.03:21:21.59#ibcon#about to read 4, iclass 30, count 0 2006.201.03:21:21.59#ibcon#read 4, iclass 30, count 0 2006.201.03:21:21.59#ibcon#about to read 5, iclass 30, count 0 2006.201.03:21:21.59#ibcon#read 5, iclass 30, count 0 2006.201.03:21:21.59#ibcon#about to read 6, iclass 30, count 0 2006.201.03:21:21.59#ibcon#read 6, iclass 30, count 0 2006.201.03:21:21.59#ibcon#end of sib2, iclass 30, count 0 2006.201.03:21:21.59#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:21:21.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:21:21.59#ibcon#[25=USB\r\n] 2006.201.03:21:21.59#ibcon#*before write, iclass 30, count 0 2006.201.03:21:21.59#ibcon#enter sib2, iclass 30, count 0 2006.201.03:21:21.59#ibcon#flushed, iclass 30, count 0 2006.201.03:21:21.59#ibcon#about to write, iclass 30, count 0 2006.201.03:21:21.59#ibcon#wrote, iclass 30, count 0 2006.201.03:21:21.59#ibcon#about to read 3, iclass 30, count 0 2006.201.03:21:21.62#ibcon#read 3, iclass 30, count 0 2006.201.03:21:21.62#ibcon#about to read 4, iclass 30, count 0 2006.201.03:21:21.62#ibcon#read 4, iclass 30, count 0 2006.201.03:21:21.62#ibcon#about to read 5, iclass 30, count 0 2006.201.03:21:21.62#ibcon#read 5, iclass 30, count 0 2006.201.03:21:21.62#ibcon#about to read 6, iclass 30, count 0 2006.201.03:21:21.62#ibcon#read 6, iclass 30, count 0 2006.201.03:21:21.62#ibcon#end of sib2, iclass 30, count 0 2006.201.03:21:21.62#ibcon#*after write, iclass 30, count 0 2006.201.03:21:21.62#ibcon#*before return 0, iclass 30, count 0 2006.201.03:21:21.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:21.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:21.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:21:21.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:21:21.62$vck44/valo=3,564.99 2006.201.03:21:21.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.03:21:21.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.03:21:21.62#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:21.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:21.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:21.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:21.62#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:21:21.62#ibcon#first serial, iclass 32, count 0 2006.201.03:21:21.62#ibcon#enter sib2, iclass 32, count 0 2006.201.03:21:21.62#ibcon#flushed, iclass 32, count 0 2006.201.03:21:21.62#ibcon#about to write, iclass 32, count 0 2006.201.03:21:21.62#ibcon#wrote, iclass 32, count 0 2006.201.03:21:21.62#ibcon#about to read 3, iclass 32, count 0 2006.201.03:21:21.64#ibcon#read 3, iclass 32, count 0 2006.201.03:21:21.64#ibcon#about to read 4, iclass 32, count 0 2006.201.03:21:21.64#ibcon#read 4, iclass 32, count 0 2006.201.03:21:21.64#ibcon#about to read 5, iclass 32, count 0 2006.201.03:21:21.64#ibcon#read 5, iclass 32, count 0 2006.201.03:21:21.64#ibcon#about to read 6, iclass 32, count 0 2006.201.03:21:21.64#ibcon#read 6, iclass 32, count 0 2006.201.03:21:21.64#ibcon#end of sib2, iclass 32, count 0 2006.201.03:21:21.64#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:21:21.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:21:21.64#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:21:21.64#ibcon#*before write, iclass 32, count 0 2006.201.03:21:21.64#ibcon#enter sib2, iclass 32, count 0 2006.201.03:21:21.64#ibcon#flushed, iclass 32, count 0 2006.201.03:21:21.64#ibcon#about to write, iclass 32, count 0 2006.201.03:21:21.64#ibcon#wrote, iclass 32, count 0 2006.201.03:21:21.64#ibcon#about to read 3, iclass 32, count 0 2006.201.03:21:21.68#ibcon#read 3, iclass 32, count 0 2006.201.03:21:21.68#ibcon#about to read 4, iclass 32, count 0 2006.201.03:21:21.68#ibcon#read 4, iclass 32, count 0 2006.201.03:21:21.68#ibcon#about to read 5, iclass 32, count 0 2006.201.03:21:21.68#ibcon#read 5, iclass 32, count 0 2006.201.03:21:21.68#ibcon#about to read 6, iclass 32, count 0 2006.201.03:21:21.68#ibcon#read 6, iclass 32, count 0 2006.201.03:21:21.68#ibcon#end of sib2, iclass 32, count 0 2006.201.03:21:21.68#ibcon#*after write, iclass 32, count 0 2006.201.03:21:21.68#ibcon#*before return 0, iclass 32, count 0 2006.201.03:21:21.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:21.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:21.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:21:21.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:21:21.68$vck44/va=3,8 2006.201.03:21:21.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.03:21:21.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.03:21:21.68#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:21.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:21.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:21.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:21.74#ibcon#enter wrdev, iclass 34, count 2 2006.201.03:21:21.74#ibcon#first serial, iclass 34, count 2 2006.201.03:21:21.74#ibcon#enter sib2, iclass 34, count 2 2006.201.03:21:21.74#ibcon#flushed, iclass 34, count 2 2006.201.03:21:21.74#ibcon#about to write, iclass 34, count 2 2006.201.03:21:21.74#ibcon#wrote, iclass 34, count 2 2006.201.03:21:21.74#ibcon#about to read 3, iclass 34, count 2 2006.201.03:21:21.76#ibcon#read 3, iclass 34, count 2 2006.201.03:21:21.76#ibcon#about to read 4, iclass 34, count 2 2006.201.03:21:21.76#ibcon#read 4, iclass 34, count 2 2006.201.03:21:21.76#ibcon#about to read 5, iclass 34, count 2 2006.201.03:21:21.76#ibcon#read 5, iclass 34, count 2 2006.201.03:21:21.76#ibcon#about to read 6, iclass 34, count 2 2006.201.03:21:21.76#ibcon#read 6, iclass 34, count 2 2006.201.03:21:21.76#ibcon#end of sib2, iclass 34, count 2 2006.201.03:21:21.76#ibcon#*mode == 0, iclass 34, count 2 2006.201.03:21:21.76#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.03:21:21.76#ibcon#[25=AT03-08\r\n] 2006.201.03:21:21.76#ibcon#*before write, iclass 34, count 2 2006.201.03:21:21.76#ibcon#enter sib2, iclass 34, count 2 2006.201.03:21:21.76#ibcon#flushed, iclass 34, count 2 2006.201.03:21:21.76#ibcon#about to write, iclass 34, count 2 2006.201.03:21:21.76#ibcon#wrote, iclass 34, count 2 2006.201.03:21:21.76#ibcon#about to read 3, iclass 34, count 2 2006.201.03:21:21.79#ibcon#read 3, iclass 34, count 2 2006.201.03:21:21.79#ibcon#about to read 4, iclass 34, count 2 2006.201.03:21:21.79#ibcon#read 4, iclass 34, count 2 2006.201.03:21:21.79#ibcon#about to read 5, iclass 34, count 2 2006.201.03:21:21.79#ibcon#read 5, iclass 34, count 2 2006.201.03:21:21.79#ibcon#about to read 6, iclass 34, count 2 2006.201.03:21:21.79#ibcon#read 6, iclass 34, count 2 2006.201.03:21:21.79#ibcon#end of sib2, iclass 34, count 2 2006.201.03:21:21.79#ibcon#*after write, iclass 34, count 2 2006.201.03:21:21.79#ibcon#*before return 0, iclass 34, count 2 2006.201.03:21:21.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:21.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:21.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.03:21:21.79#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:21.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:21.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:21.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:21.91#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:21:21.91#ibcon#first serial, iclass 34, count 0 2006.201.03:21:21.91#ibcon#enter sib2, iclass 34, count 0 2006.201.03:21:21.91#ibcon#flushed, iclass 34, count 0 2006.201.03:21:21.91#ibcon#about to write, iclass 34, count 0 2006.201.03:21:21.91#ibcon#wrote, iclass 34, count 0 2006.201.03:21:21.91#ibcon#about to read 3, iclass 34, count 0 2006.201.03:21:21.93#ibcon#read 3, iclass 34, count 0 2006.201.03:21:21.93#ibcon#about to read 4, iclass 34, count 0 2006.201.03:21:21.93#ibcon#read 4, iclass 34, count 0 2006.201.03:21:21.93#ibcon#about to read 5, iclass 34, count 0 2006.201.03:21:21.93#ibcon#read 5, iclass 34, count 0 2006.201.03:21:21.93#ibcon#about to read 6, iclass 34, count 0 2006.201.03:21:21.93#ibcon#read 6, iclass 34, count 0 2006.201.03:21:21.93#ibcon#end of sib2, iclass 34, count 0 2006.201.03:21:21.93#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:21:21.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:21:21.93#ibcon#[25=USB\r\n] 2006.201.03:21:21.93#ibcon#*before write, iclass 34, count 0 2006.201.03:21:21.93#ibcon#enter sib2, iclass 34, count 0 2006.201.03:21:21.93#ibcon#flushed, iclass 34, count 0 2006.201.03:21:21.93#ibcon#about to write, iclass 34, count 0 2006.201.03:21:21.93#ibcon#wrote, iclass 34, count 0 2006.201.03:21:21.93#ibcon#about to read 3, iclass 34, count 0 2006.201.03:21:21.96#ibcon#read 3, iclass 34, count 0 2006.201.03:21:21.96#ibcon#about to read 4, iclass 34, count 0 2006.201.03:21:21.96#ibcon#read 4, iclass 34, count 0 2006.201.03:21:21.96#ibcon#about to read 5, iclass 34, count 0 2006.201.03:21:21.96#ibcon#read 5, iclass 34, count 0 2006.201.03:21:21.96#ibcon#about to read 6, iclass 34, count 0 2006.201.03:21:21.96#ibcon#read 6, iclass 34, count 0 2006.201.03:21:21.96#ibcon#end of sib2, iclass 34, count 0 2006.201.03:21:21.96#ibcon#*after write, iclass 34, count 0 2006.201.03:21:21.96#ibcon#*before return 0, iclass 34, count 0 2006.201.03:21:21.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:21.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:21.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:21:21.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:21:21.96$vck44/valo=4,624.99 2006.201.03:21:21.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.03:21:21.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.03:21:21.96#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:21.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:21.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:21.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:21.96#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:21:21.96#ibcon#first serial, iclass 36, count 0 2006.201.03:21:21.96#ibcon#enter sib2, iclass 36, count 0 2006.201.03:21:21.96#ibcon#flushed, iclass 36, count 0 2006.201.03:21:21.96#ibcon#about to write, iclass 36, count 0 2006.201.03:21:21.96#ibcon#wrote, iclass 36, count 0 2006.201.03:21:21.96#ibcon#about to read 3, iclass 36, count 0 2006.201.03:21:21.98#ibcon#read 3, iclass 36, count 0 2006.201.03:21:21.98#ibcon#about to read 4, iclass 36, count 0 2006.201.03:21:21.98#ibcon#read 4, iclass 36, count 0 2006.201.03:21:21.98#ibcon#about to read 5, iclass 36, count 0 2006.201.03:21:21.98#ibcon#read 5, iclass 36, count 0 2006.201.03:21:21.98#ibcon#about to read 6, iclass 36, count 0 2006.201.03:21:21.98#ibcon#read 6, iclass 36, count 0 2006.201.03:21:21.98#ibcon#end of sib2, iclass 36, count 0 2006.201.03:21:21.98#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:21:21.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:21:21.98#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:21:21.98#ibcon#*before write, iclass 36, count 0 2006.201.03:21:21.98#ibcon#enter sib2, iclass 36, count 0 2006.201.03:21:21.98#ibcon#flushed, iclass 36, count 0 2006.201.03:21:21.98#ibcon#about to write, iclass 36, count 0 2006.201.03:21:21.98#ibcon#wrote, iclass 36, count 0 2006.201.03:21:21.98#ibcon#about to read 3, iclass 36, count 0 2006.201.03:21:22.02#ibcon#read 3, iclass 36, count 0 2006.201.03:21:22.02#ibcon#about to read 4, iclass 36, count 0 2006.201.03:21:22.02#ibcon#read 4, iclass 36, count 0 2006.201.03:21:22.02#ibcon#about to read 5, iclass 36, count 0 2006.201.03:21:22.02#ibcon#read 5, iclass 36, count 0 2006.201.03:21:22.02#ibcon#about to read 6, iclass 36, count 0 2006.201.03:21:22.02#ibcon#read 6, iclass 36, count 0 2006.201.03:21:22.02#ibcon#end of sib2, iclass 36, count 0 2006.201.03:21:22.02#ibcon#*after write, iclass 36, count 0 2006.201.03:21:22.02#ibcon#*before return 0, iclass 36, count 0 2006.201.03:21:22.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:22.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:22.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:21:22.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:21:22.02$vck44/va=4,7 2006.201.03:21:22.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.03:21:22.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.03:21:22.02#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:22.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:22.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:22.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:22.08#ibcon#enter wrdev, iclass 38, count 2 2006.201.03:21:22.08#ibcon#first serial, iclass 38, count 2 2006.201.03:21:22.08#ibcon#enter sib2, iclass 38, count 2 2006.201.03:21:22.08#ibcon#flushed, iclass 38, count 2 2006.201.03:21:22.08#ibcon#about to write, iclass 38, count 2 2006.201.03:21:22.08#ibcon#wrote, iclass 38, count 2 2006.201.03:21:22.08#ibcon#about to read 3, iclass 38, count 2 2006.201.03:21:22.10#ibcon#read 3, iclass 38, count 2 2006.201.03:21:22.10#ibcon#about to read 4, iclass 38, count 2 2006.201.03:21:22.10#ibcon#read 4, iclass 38, count 2 2006.201.03:21:22.10#ibcon#about to read 5, iclass 38, count 2 2006.201.03:21:22.10#ibcon#read 5, iclass 38, count 2 2006.201.03:21:22.10#ibcon#about to read 6, iclass 38, count 2 2006.201.03:21:22.10#ibcon#read 6, iclass 38, count 2 2006.201.03:21:22.10#ibcon#end of sib2, iclass 38, count 2 2006.201.03:21:22.10#ibcon#*mode == 0, iclass 38, count 2 2006.201.03:21:22.10#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.03:21:22.10#ibcon#[25=AT04-07\r\n] 2006.201.03:21:22.10#ibcon#*before write, iclass 38, count 2 2006.201.03:21:22.10#ibcon#enter sib2, iclass 38, count 2 2006.201.03:21:22.10#ibcon#flushed, iclass 38, count 2 2006.201.03:21:22.10#ibcon#about to write, iclass 38, count 2 2006.201.03:21:22.10#ibcon#wrote, iclass 38, count 2 2006.201.03:21:22.10#ibcon#about to read 3, iclass 38, count 2 2006.201.03:21:22.13#ibcon#read 3, iclass 38, count 2 2006.201.03:21:22.13#ibcon#about to read 4, iclass 38, count 2 2006.201.03:21:22.13#ibcon#read 4, iclass 38, count 2 2006.201.03:21:22.13#ibcon#about to read 5, iclass 38, count 2 2006.201.03:21:22.13#ibcon#read 5, iclass 38, count 2 2006.201.03:21:22.13#ibcon#about to read 6, iclass 38, count 2 2006.201.03:21:22.13#ibcon#read 6, iclass 38, count 2 2006.201.03:21:22.13#ibcon#end of sib2, iclass 38, count 2 2006.201.03:21:22.13#ibcon#*after write, iclass 38, count 2 2006.201.03:21:22.13#ibcon#*before return 0, iclass 38, count 2 2006.201.03:21:22.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:22.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:22.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.03:21:22.13#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:22.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:22.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:22.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:22.25#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:21:22.25#ibcon#first serial, iclass 38, count 0 2006.201.03:21:22.25#ibcon#enter sib2, iclass 38, count 0 2006.201.03:21:22.25#ibcon#flushed, iclass 38, count 0 2006.201.03:21:22.25#ibcon#about to write, iclass 38, count 0 2006.201.03:21:22.25#ibcon#wrote, iclass 38, count 0 2006.201.03:21:22.25#ibcon#about to read 3, iclass 38, count 0 2006.201.03:21:22.27#ibcon#read 3, iclass 38, count 0 2006.201.03:21:22.27#ibcon#about to read 4, iclass 38, count 0 2006.201.03:21:22.27#ibcon#read 4, iclass 38, count 0 2006.201.03:21:22.27#ibcon#about to read 5, iclass 38, count 0 2006.201.03:21:22.27#ibcon#read 5, iclass 38, count 0 2006.201.03:21:22.27#ibcon#about to read 6, iclass 38, count 0 2006.201.03:21:22.27#ibcon#read 6, iclass 38, count 0 2006.201.03:21:22.27#ibcon#end of sib2, iclass 38, count 0 2006.201.03:21:22.27#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:21:22.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:21:22.27#ibcon#[25=USB\r\n] 2006.201.03:21:22.27#ibcon#*before write, iclass 38, count 0 2006.201.03:21:22.27#ibcon#enter sib2, iclass 38, count 0 2006.201.03:21:22.27#ibcon#flushed, iclass 38, count 0 2006.201.03:21:22.27#ibcon#about to write, iclass 38, count 0 2006.201.03:21:22.27#ibcon#wrote, iclass 38, count 0 2006.201.03:21:22.27#ibcon#about to read 3, iclass 38, count 0 2006.201.03:21:22.30#ibcon#read 3, iclass 38, count 0 2006.201.03:21:22.30#ibcon#about to read 4, iclass 38, count 0 2006.201.03:21:22.30#ibcon#read 4, iclass 38, count 0 2006.201.03:21:22.30#ibcon#about to read 5, iclass 38, count 0 2006.201.03:21:22.30#ibcon#read 5, iclass 38, count 0 2006.201.03:21:22.30#ibcon#about to read 6, iclass 38, count 0 2006.201.03:21:22.30#ibcon#read 6, iclass 38, count 0 2006.201.03:21:22.30#ibcon#end of sib2, iclass 38, count 0 2006.201.03:21:22.30#ibcon#*after write, iclass 38, count 0 2006.201.03:21:22.30#ibcon#*before return 0, iclass 38, count 0 2006.201.03:21:22.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:22.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:22.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:21:22.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:21:22.30$vck44/valo=5,734.99 2006.201.03:21:22.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.03:21:22.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.03:21:22.30#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:22.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:22.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:22.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:22.30#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:21:22.30#ibcon#first serial, iclass 40, count 0 2006.201.03:21:22.30#ibcon#enter sib2, iclass 40, count 0 2006.201.03:21:22.30#ibcon#flushed, iclass 40, count 0 2006.201.03:21:22.30#ibcon#about to write, iclass 40, count 0 2006.201.03:21:22.30#ibcon#wrote, iclass 40, count 0 2006.201.03:21:22.30#ibcon#about to read 3, iclass 40, count 0 2006.201.03:21:22.32#ibcon#read 3, iclass 40, count 0 2006.201.03:21:22.32#ibcon#about to read 4, iclass 40, count 0 2006.201.03:21:22.32#ibcon#read 4, iclass 40, count 0 2006.201.03:21:22.32#ibcon#about to read 5, iclass 40, count 0 2006.201.03:21:22.32#ibcon#read 5, iclass 40, count 0 2006.201.03:21:22.32#ibcon#about to read 6, iclass 40, count 0 2006.201.03:21:22.32#ibcon#read 6, iclass 40, count 0 2006.201.03:21:22.32#ibcon#end of sib2, iclass 40, count 0 2006.201.03:21:22.32#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:21:22.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:21:22.32#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:21:22.32#ibcon#*before write, iclass 40, count 0 2006.201.03:21:22.32#ibcon#enter sib2, iclass 40, count 0 2006.201.03:21:22.32#ibcon#flushed, iclass 40, count 0 2006.201.03:21:22.32#ibcon#about to write, iclass 40, count 0 2006.201.03:21:22.32#ibcon#wrote, iclass 40, count 0 2006.201.03:21:22.32#ibcon#about to read 3, iclass 40, count 0 2006.201.03:21:22.36#ibcon#read 3, iclass 40, count 0 2006.201.03:21:22.36#ibcon#about to read 4, iclass 40, count 0 2006.201.03:21:22.36#ibcon#read 4, iclass 40, count 0 2006.201.03:21:22.36#ibcon#about to read 5, iclass 40, count 0 2006.201.03:21:22.36#ibcon#read 5, iclass 40, count 0 2006.201.03:21:22.36#ibcon#about to read 6, iclass 40, count 0 2006.201.03:21:22.36#ibcon#read 6, iclass 40, count 0 2006.201.03:21:22.36#ibcon#end of sib2, iclass 40, count 0 2006.201.03:21:22.36#ibcon#*after write, iclass 40, count 0 2006.201.03:21:22.36#ibcon#*before return 0, iclass 40, count 0 2006.201.03:21:22.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:22.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:22.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:21:22.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:21:22.36$vck44/va=5,4 2006.201.03:21:22.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.03:21:22.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.03:21:22.36#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:22.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:22.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:22.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:22.42#ibcon#enter wrdev, iclass 4, count 2 2006.201.03:21:22.42#ibcon#first serial, iclass 4, count 2 2006.201.03:21:22.42#ibcon#enter sib2, iclass 4, count 2 2006.201.03:21:22.42#ibcon#flushed, iclass 4, count 2 2006.201.03:21:22.42#ibcon#about to write, iclass 4, count 2 2006.201.03:21:22.42#ibcon#wrote, iclass 4, count 2 2006.201.03:21:22.42#ibcon#about to read 3, iclass 4, count 2 2006.201.03:21:22.44#ibcon#read 3, iclass 4, count 2 2006.201.03:21:22.44#ibcon#about to read 4, iclass 4, count 2 2006.201.03:21:22.44#ibcon#read 4, iclass 4, count 2 2006.201.03:21:22.44#ibcon#about to read 5, iclass 4, count 2 2006.201.03:21:22.44#ibcon#read 5, iclass 4, count 2 2006.201.03:21:22.44#ibcon#about to read 6, iclass 4, count 2 2006.201.03:21:22.44#ibcon#read 6, iclass 4, count 2 2006.201.03:21:22.44#ibcon#end of sib2, iclass 4, count 2 2006.201.03:21:22.44#ibcon#*mode == 0, iclass 4, count 2 2006.201.03:21:22.44#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.03:21:22.44#ibcon#[25=AT05-04\r\n] 2006.201.03:21:22.44#ibcon#*before write, iclass 4, count 2 2006.201.03:21:22.44#ibcon#enter sib2, iclass 4, count 2 2006.201.03:21:22.44#ibcon#flushed, iclass 4, count 2 2006.201.03:21:22.44#ibcon#about to write, iclass 4, count 2 2006.201.03:21:22.44#ibcon#wrote, iclass 4, count 2 2006.201.03:21:22.44#ibcon#about to read 3, iclass 4, count 2 2006.201.03:21:22.47#ibcon#read 3, iclass 4, count 2 2006.201.03:21:22.47#ibcon#about to read 4, iclass 4, count 2 2006.201.03:21:22.47#ibcon#read 4, iclass 4, count 2 2006.201.03:21:22.47#ibcon#about to read 5, iclass 4, count 2 2006.201.03:21:22.47#ibcon#read 5, iclass 4, count 2 2006.201.03:21:22.47#ibcon#about to read 6, iclass 4, count 2 2006.201.03:21:22.47#ibcon#read 6, iclass 4, count 2 2006.201.03:21:22.47#ibcon#end of sib2, iclass 4, count 2 2006.201.03:21:22.47#ibcon#*after write, iclass 4, count 2 2006.201.03:21:22.47#ibcon#*before return 0, iclass 4, count 2 2006.201.03:21:22.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:22.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:22.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.03:21:22.47#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:22.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:22.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:22.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:22.59#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:21:22.59#ibcon#first serial, iclass 4, count 0 2006.201.03:21:22.59#ibcon#enter sib2, iclass 4, count 0 2006.201.03:21:22.59#ibcon#flushed, iclass 4, count 0 2006.201.03:21:22.59#ibcon#about to write, iclass 4, count 0 2006.201.03:21:22.59#ibcon#wrote, iclass 4, count 0 2006.201.03:21:22.59#ibcon#about to read 3, iclass 4, count 0 2006.201.03:21:22.61#ibcon#read 3, iclass 4, count 0 2006.201.03:21:22.61#ibcon#about to read 4, iclass 4, count 0 2006.201.03:21:22.61#ibcon#read 4, iclass 4, count 0 2006.201.03:21:22.61#ibcon#about to read 5, iclass 4, count 0 2006.201.03:21:22.61#ibcon#read 5, iclass 4, count 0 2006.201.03:21:22.61#ibcon#about to read 6, iclass 4, count 0 2006.201.03:21:22.61#ibcon#read 6, iclass 4, count 0 2006.201.03:21:22.61#ibcon#end of sib2, iclass 4, count 0 2006.201.03:21:22.61#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:21:22.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:21:22.61#ibcon#[25=USB\r\n] 2006.201.03:21:22.61#ibcon#*before write, iclass 4, count 0 2006.201.03:21:22.61#ibcon#enter sib2, iclass 4, count 0 2006.201.03:21:22.61#ibcon#flushed, iclass 4, count 0 2006.201.03:21:22.61#ibcon#about to write, iclass 4, count 0 2006.201.03:21:22.61#ibcon#wrote, iclass 4, count 0 2006.201.03:21:22.61#ibcon#about to read 3, iclass 4, count 0 2006.201.03:21:22.64#ibcon#read 3, iclass 4, count 0 2006.201.03:21:22.64#ibcon#about to read 4, iclass 4, count 0 2006.201.03:21:22.64#ibcon#read 4, iclass 4, count 0 2006.201.03:21:22.64#ibcon#about to read 5, iclass 4, count 0 2006.201.03:21:22.64#ibcon#read 5, iclass 4, count 0 2006.201.03:21:22.64#ibcon#about to read 6, iclass 4, count 0 2006.201.03:21:22.64#ibcon#read 6, iclass 4, count 0 2006.201.03:21:22.64#ibcon#end of sib2, iclass 4, count 0 2006.201.03:21:22.64#ibcon#*after write, iclass 4, count 0 2006.201.03:21:22.64#ibcon#*before return 0, iclass 4, count 0 2006.201.03:21:22.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:22.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:22.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:21:22.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:21:22.64$vck44/valo=6,814.99 2006.201.03:21:22.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.03:21:22.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.03:21:22.64#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:22.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:22.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:22.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:22.64#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:21:22.64#ibcon#first serial, iclass 6, count 0 2006.201.03:21:22.64#ibcon#enter sib2, iclass 6, count 0 2006.201.03:21:22.64#ibcon#flushed, iclass 6, count 0 2006.201.03:21:22.64#ibcon#about to write, iclass 6, count 0 2006.201.03:21:22.64#ibcon#wrote, iclass 6, count 0 2006.201.03:21:22.64#ibcon#about to read 3, iclass 6, count 0 2006.201.03:21:22.66#ibcon#read 3, iclass 6, count 0 2006.201.03:21:22.66#ibcon#about to read 4, iclass 6, count 0 2006.201.03:21:22.66#ibcon#read 4, iclass 6, count 0 2006.201.03:21:22.66#ibcon#about to read 5, iclass 6, count 0 2006.201.03:21:22.66#ibcon#read 5, iclass 6, count 0 2006.201.03:21:22.66#ibcon#about to read 6, iclass 6, count 0 2006.201.03:21:22.66#ibcon#read 6, iclass 6, count 0 2006.201.03:21:22.66#ibcon#end of sib2, iclass 6, count 0 2006.201.03:21:22.66#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:21:22.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:21:22.66#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:21:22.66#ibcon#*before write, iclass 6, count 0 2006.201.03:21:22.66#ibcon#enter sib2, iclass 6, count 0 2006.201.03:21:22.66#ibcon#flushed, iclass 6, count 0 2006.201.03:21:22.66#ibcon#about to write, iclass 6, count 0 2006.201.03:21:22.66#ibcon#wrote, iclass 6, count 0 2006.201.03:21:22.66#ibcon#about to read 3, iclass 6, count 0 2006.201.03:21:22.70#ibcon#read 3, iclass 6, count 0 2006.201.03:21:22.70#ibcon#about to read 4, iclass 6, count 0 2006.201.03:21:22.70#ibcon#read 4, iclass 6, count 0 2006.201.03:21:22.70#ibcon#about to read 5, iclass 6, count 0 2006.201.03:21:22.70#ibcon#read 5, iclass 6, count 0 2006.201.03:21:22.70#ibcon#about to read 6, iclass 6, count 0 2006.201.03:21:22.70#ibcon#read 6, iclass 6, count 0 2006.201.03:21:22.70#ibcon#end of sib2, iclass 6, count 0 2006.201.03:21:22.70#ibcon#*after write, iclass 6, count 0 2006.201.03:21:22.70#ibcon#*before return 0, iclass 6, count 0 2006.201.03:21:22.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:22.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:22.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:21:22.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:21:22.70$vck44/va=6,5 2006.201.03:21:22.70#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.03:21:22.70#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.03:21:22.70#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:22.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:22.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:22.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:22.76#ibcon#enter wrdev, iclass 10, count 2 2006.201.03:21:22.76#ibcon#first serial, iclass 10, count 2 2006.201.03:21:22.76#ibcon#enter sib2, iclass 10, count 2 2006.201.03:21:22.76#ibcon#flushed, iclass 10, count 2 2006.201.03:21:22.76#ibcon#about to write, iclass 10, count 2 2006.201.03:21:22.76#ibcon#wrote, iclass 10, count 2 2006.201.03:21:22.76#ibcon#about to read 3, iclass 10, count 2 2006.201.03:21:22.78#ibcon#read 3, iclass 10, count 2 2006.201.03:21:22.78#ibcon#about to read 4, iclass 10, count 2 2006.201.03:21:22.78#ibcon#read 4, iclass 10, count 2 2006.201.03:21:22.78#ibcon#about to read 5, iclass 10, count 2 2006.201.03:21:22.78#ibcon#read 5, iclass 10, count 2 2006.201.03:21:22.78#ibcon#about to read 6, iclass 10, count 2 2006.201.03:21:22.78#ibcon#read 6, iclass 10, count 2 2006.201.03:21:22.78#ibcon#end of sib2, iclass 10, count 2 2006.201.03:21:22.78#ibcon#*mode == 0, iclass 10, count 2 2006.201.03:21:22.78#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.03:21:22.78#ibcon#[25=AT06-05\r\n] 2006.201.03:21:22.78#ibcon#*before write, iclass 10, count 2 2006.201.03:21:22.78#ibcon#enter sib2, iclass 10, count 2 2006.201.03:21:22.78#ibcon#flushed, iclass 10, count 2 2006.201.03:21:22.78#ibcon#about to write, iclass 10, count 2 2006.201.03:21:22.78#ibcon#wrote, iclass 10, count 2 2006.201.03:21:22.78#ibcon#about to read 3, iclass 10, count 2 2006.201.03:21:22.81#ibcon#read 3, iclass 10, count 2 2006.201.03:21:22.81#ibcon#about to read 4, iclass 10, count 2 2006.201.03:21:22.81#ibcon#read 4, iclass 10, count 2 2006.201.03:21:22.81#ibcon#about to read 5, iclass 10, count 2 2006.201.03:21:22.81#ibcon#read 5, iclass 10, count 2 2006.201.03:21:22.81#ibcon#about to read 6, iclass 10, count 2 2006.201.03:21:22.81#ibcon#read 6, iclass 10, count 2 2006.201.03:21:22.81#ibcon#end of sib2, iclass 10, count 2 2006.201.03:21:22.81#ibcon#*after write, iclass 10, count 2 2006.201.03:21:22.81#ibcon#*before return 0, iclass 10, count 2 2006.201.03:21:22.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:22.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:22.81#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.03:21:22.81#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:22.81#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:22.93#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:22.93#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:22.93#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:21:22.93#ibcon#first serial, iclass 10, count 0 2006.201.03:21:22.93#ibcon#enter sib2, iclass 10, count 0 2006.201.03:21:22.93#ibcon#flushed, iclass 10, count 0 2006.201.03:21:22.93#ibcon#about to write, iclass 10, count 0 2006.201.03:21:22.93#ibcon#wrote, iclass 10, count 0 2006.201.03:21:22.93#ibcon#about to read 3, iclass 10, count 0 2006.201.03:21:22.95#ibcon#read 3, iclass 10, count 0 2006.201.03:21:22.95#ibcon#about to read 4, iclass 10, count 0 2006.201.03:21:22.95#ibcon#read 4, iclass 10, count 0 2006.201.03:21:22.95#ibcon#about to read 5, iclass 10, count 0 2006.201.03:21:22.95#ibcon#read 5, iclass 10, count 0 2006.201.03:21:22.95#ibcon#about to read 6, iclass 10, count 0 2006.201.03:21:22.95#ibcon#read 6, iclass 10, count 0 2006.201.03:21:22.95#ibcon#end of sib2, iclass 10, count 0 2006.201.03:21:22.95#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:21:22.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:21:22.95#ibcon#[25=USB\r\n] 2006.201.03:21:22.95#ibcon#*before write, iclass 10, count 0 2006.201.03:21:22.95#ibcon#enter sib2, iclass 10, count 0 2006.201.03:21:22.95#ibcon#flushed, iclass 10, count 0 2006.201.03:21:22.95#ibcon#about to write, iclass 10, count 0 2006.201.03:21:22.95#ibcon#wrote, iclass 10, count 0 2006.201.03:21:22.95#ibcon#about to read 3, iclass 10, count 0 2006.201.03:21:22.98#ibcon#read 3, iclass 10, count 0 2006.201.03:21:22.98#ibcon#about to read 4, iclass 10, count 0 2006.201.03:21:22.98#ibcon#read 4, iclass 10, count 0 2006.201.03:21:22.98#ibcon#about to read 5, iclass 10, count 0 2006.201.03:21:22.98#ibcon#read 5, iclass 10, count 0 2006.201.03:21:22.98#ibcon#about to read 6, iclass 10, count 0 2006.201.03:21:22.98#ibcon#read 6, iclass 10, count 0 2006.201.03:21:22.98#ibcon#end of sib2, iclass 10, count 0 2006.201.03:21:22.98#ibcon#*after write, iclass 10, count 0 2006.201.03:21:22.98#ibcon#*before return 0, iclass 10, count 0 2006.201.03:21:22.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:22.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:22.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:21:22.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:21:22.98$vck44/valo=7,864.99 2006.201.03:21:22.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.03:21:22.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.03:21:22.98#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:22.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:22.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:22.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:22.98#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:21:22.98#ibcon#first serial, iclass 12, count 0 2006.201.03:21:22.98#ibcon#enter sib2, iclass 12, count 0 2006.201.03:21:22.98#ibcon#flushed, iclass 12, count 0 2006.201.03:21:22.98#ibcon#about to write, iclass 12, count 0 2006.201.03:21:22.98#ibcon#wrote, iclass 12, count 0 2006.201.03:21:22.98#ibcon#about to read 3, iclass 12, count 0 2006.201.03:21:23.00#ibcon#read 3, iclass 12, count 0 2006.201.03:21:23.00#ibcon#about to read 4, iclass 12, count 0 2006.201.03:21:23.00#ibcon#read 4, iclass 12, count 0 2006.201.03:21:23.00#ibcon#about to read 5, iclass 12, count 0 2006.201.03:21:23.00#ibcon#read 5, iclass 12, count 0 2006.201.03:21:23.00#ibcon#about to read 6, iclass 12, count 0 2006.201.03:21:23.00#ibcon#read 6, iclass 12, count 0 2006.201.03:21:23.00#ibcon#end of sib2, iclass 12, count 0 2006.201.03:21:23.00#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:21:23.00#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:21:23.00#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:21:23.00#ibcon#*before write, iclass 12, count 0 2006.201.03:21:23.00#ibcon#enter sib2, iclass 12, count 0 2006.201.03:21:23.00#ibcon#flushed, iclass 12, count 0 2006.201.03:21:23.00#ibcon#about to write, iclass 12, count 0 2006.201.03:21:23.00#ibcon#wrote, iclass 12, count 0 2006.201.03:21:23.00#ibcon#about to read 3, iclass 12, count 0 2006.201.03:21:23.04#ibcon#read 3, iclass 12, count 0 2006.201.03:21:23.04#ibcon#about to read 4, iclass 12, count 0 2006.201.03:21:23.04#ibcon#read 4, iclass 12, count 0 2006.201.03:21:23.04#ibcon#about to read 5, iclass 12, count 0 2006.201.03:21:23.04#ibcon#read 5, iclass 12, count 0 2006.201.03:21:23.04#ibcon#about to read 6, iclass 12, count 0 2006.201.03:21:23.04#ibcon#read 6, iclass 12, count 0 2006.201.03:21:23.04#ibcon#end of sib2, iclass 12, count 0 2006.201.03:21:23.04#ibcon#*after write, iclass 12, count 0 2006.201.03:21:23.04#ibcon#*before return 0, iclass 12, count 0 2006.201.03:21:23.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:23.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:23.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:21:23.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:21:23.04$vck44/va=7,5 2006.201.03:21:23.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.03:21:23.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.03:21:23.04#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:23.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:23.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:23.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:23.10#ibcon#enter wrdev, iclass 14, count 2 2006.201.03:21:23.10#ibcon#first serial, iclass 14, count 2 2006.201.03:21:23.10#ibcon#enter sib2, iclass 14, count 2 2006.201.03:21:23.10#ibcon#flushed, iclass 14, count 2 2006.201.03:21:23.10#ibcon#about to write, iclass 14, count 2 2006.201.03:21:23.10#ibcon#wrote, iclass 14, count 2 2006.201.03:21:23.10#ibcon#about to read 3, iclass 14, count 2 2006.201.03:21:23.12#ibcon#read 3, iclass 14, count 2 2006.201.03:21:23.12#ibcon#about to read 4, iclass 14, count 2 2006.201.03:21:23.12#ibcon#read 4, iclass 14, count 2 2006.201.03:21:23.12#ibcon#about to read 5, iclass 14, count 2 2006.201.03:21:23.12#ibcon#read 5, iclass 14, count 2 2006.201.03:21:23.12#ibcon#about to read 6, iclass 14, count 2 2006.201.03:21:23.12#ibcon#read 6, iclass 14, count 2 2006.201.03:21:23.12#ibcon#end of sib2, iclass 14, count 2 2006.201.03:21:23.12#ibcon#*mode == 0, iclass 14, count 2 2006.201.03:21:23.12#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.03:21:23.12#ibcon#[25=AT07-05\r\n] 2006.201.03:21:23.12#ibcon#*before write, iclass 14, count 2 2006.201.03:21:23.12#ibcon#enter sib2, iclass 14, count 2 2006.201.03:21:23.12#ibcon#flushed, iclass 14, count 2 2006.201.03:21:23.12#ibcon#about to write, iclass 14, count 2 2006.201.03:21:23.12#ibcon#wrote, iclass 14, count 2 2006.201.03:21:23.12#ibcon#about to read 3, iclass 14, count 2 2006.201.03:21:23.15#ibcon#read 3, iclass 14, count 2 2006.201.03:21:23.15#ibcon#about to read 4, iclass 14, count 2 2006.201.03:21:23.15#ibcon#read 4, iclass 14, count 2 2006.201.03:21:23.15#ibcon#about to read 5, iclass 14, count 2 2006.201.03:21:23.15#ibcon#read 5, iclass 14, count 2 2006.201.03:21:23.15#ibcon#about to read 6, iclass 14, count 2 2006.201.03:21:23.15#ibcon#read 6, iclass 14, count 2 2006.201.03:21:23.15#ibcon#end of sib2, iclass 14, count 2 2006.201.03:21:23.15#ibcon#*after write, iclass 14, count 2 2006.201.03:21:23.15#ibcon#*before return 0, iclass 14, count 2 2006.201.03:21:23.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:23.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:23.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.03:21:23.15#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:23.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:23.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:23.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:23.27#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:21:23.27#ibcon#first serial, iclass 14, count 0 2006.201.03:21:23.27#ibcon#enter sib2, iclass 14, count 0 2006.201.03:21:23.27#ibcon#flushed, iclass 14, count 0 2006.201.03:21:23.27#ibcon#about to write, iclass 14, count 0 2006.201.03:21:23.27#ibcon#wrote, iclass 14, count 0 2006.201.03:21:23.27#ibcon#about to read 3, iclass 14, count 0 2006.201.03:21:23.29#ibcon#read 3, iclass 14, count 0 2006.201.03:21:23.29#ibcon#about to read 4, iclass 14, count 0 2006.201.03:21:23.29#ibcon#read 4, iclass 14, count 0 2006.201.03:21:23.29#ibcon#about to read 5, iclass 14, count 0 2006.201.03:21:23.29#ibcon#read 5, iclass 14, count 0 2006.201.03:21:23.29#ibcon#about to read 6, iclass 14, count 0 2006.201.03:21:23.29#ibcon#read 6, iclass 14, count 0 2006.201.03:21:23.29#ibcon#end of sib2, iclass 14, count 0 2006.201.03:21:23.29#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:21:23.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:21:23.29#ibcon#[25=USB\r\n] 2006.201.03:21:23.29#ibcon#*before write, iclass 14, count 0 2006.201.03:21:23.29#ibcon#enter sib2, iclass 14, count 0 2006.201.03:21:23.29#ibcon#flushed, iclass 14, count 0 2006.201.03:21:23.29#ibcon#about to write, iclass 14, count 0 2006.201.03:21:23.29#ibcon#wrote, iclass 14, count 0 2006.201.03:21:23.29#ibcon#about to read 3, iclass 14, count 0 2006.201.03:21:23.32#ibcon#read 3, iclass 14, count 0 2006.201.03:21:23.32#ibcon#about to read 4, iclass 14, count 0 2006.201.03:21:23.32#ibcon#read 4, iclass 14, count 0 2006.201.03:21:23.32#ibcon#about to read 5, iclass 14, count 0 2006.201.03:21:23.32#ibcon#read 5, iclass 14, count 0 2006.201.03:21:23.32#ibcon#about to read 6, iclass 14, count 0 2006.201.03:21:23.32#ibcon#read 6, iclass 14, count 0 2006.201.03:21:23.32#ibcon#end of sib2, iclass 14, count 0 2006.201.03:21:23.32#ibcon#*after write, iclass 14, count 0 2006.201.03:21:23.32#ibcon#*before return 0, iclass 14, count 0 2006.201.03:21:23.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:23.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:23.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:21:23.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:21:23.32$vck44/valo=8,884.99 2006.201.03:21:23.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.03:21:23.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.03:21:23.32#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:23.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:23.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:23.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:23.32#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:21:23.32#ibcon#first serial, iclass 16, count 0 2006.201.03:21:23.32#ibcon#enter sib2, iclass 16, count 0 2006.201.03:21:23.32#ibcon#flushed, iclass 16, count 0 2006.201.03:21:23.32#ibcon#about to write, iclass 16, count 0 2006.201.03:21:23.32#ibcon#wrote, iclass 16, count 0 2006.201.03:21:23.32#ibcon#about to read 3, iclass 16, count 0 2006.201.03:21:23.34#ibcon#read 3, iclass 16, count 0 2006.201.03:21:23.34#ibcon#about to read 4, iclass 16, count 0 2006.201.03:21:23.34#ibcon#read 4, iclass 16, count 0 2006.201.03:21:23.34#ibcon#about to read 5, iclass 16, count 0 2006.201.03:21:23.34#ibcon#read 5, iclass 16, count 0 2006.201.03:21:23.34#ibcon#about to read 6, iclass 16, count 0 2006.201.03:21:23.34#ibcon#read 6, iclass 16, count 0 2006.201.03:21:23.34#ibcon#end of sib2, iclass 16, count 0 2006.201.03:21:23.34#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:21:23.34#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:21:23.34#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:21:23.34#ibcon#*before write, iclass 16, count 0 2006.201.03:21:23.34#ibcon#enter sib2, iclass 16, count 0 2006.201.03:21:23.34#ibcon#flushed, iclass 16, count 0 2006.201.03:21:23.34#ibcon#about to write, iclass 16, count 0 2006.201.03:21:23.34#ibcon#wrote, iclass 16, count 0 2006.201.03:21:23.34#ibcon#about to read 3, iclass 16, count 0 2006.201.03:21:23.38#ibcon#read 3, iclass 16, count 0 2006.201.03:21:23.38#ibcon#about to read 4, iclass 16, count 0 2006.201.03:21:23.38#ibcon#read 4, iclass 16, count 0 2006.201.03:21:23.38#ibcon#about to read 5, iclass 16, count 0 2006.201.03:21:23.38#ibcon#read 5, iclass 16, count 0 2006.201.03:21:23.38#ibcon#about to read 6, iclass 16, count 0 2006.201.03:21:23.38#ibcon#read 6, iclass 16, count 0 2006.201.03:21:23.38#ibcon#end of sib2, iclass 16, count 0 2006.201.03:21:23.38#ibcon#*after write, iclass 16, count 0 2006.201.03:21:23.38#ibcon#*before return 0, iclass 16, count 0 2006.201.03:21:23.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:23.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:23.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:21:23.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:21:23.38$vck44/va=8,4 2006.201.03:21:23.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.03:21:23.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.03:21:23.38#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:23.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:21:23.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:21:23.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:21:23.44#ibcon#enter wrdev, iclass 18, count 2 2006.201.03:21:23.44#ibcon#first serial, iclass 18, count 2 2006.201.03:21:23.44#ibcon#enter sib2, iclass 18, count 2 2006.201.03:21:23.44#ibcon#flushed, iclass 18, count 2 2006.201.03:21:23.44#ibcon#about to write, iclass 18, count 2 2006.201.03:21:23.44#ibcon#wrote, iclass 18, count 2 2006.201.03:21:23.44#ibcon#about to read 3, iclass 18, count 2 2006.201.03:21:23.46#ibcon#read 3, iclass 18, count 2 2006.201.03:21:23.46#ibcon#about to read 4, iclass 18, count 2 2006.201.03:21:23.46#ibcon#read 4, iclass 18, count 2 2006.201.03:21:23.46#ibcon#about to read 5, iclass 18, count 2 2006.201.03:21:23.46#ibcon#read 5, iclass 18, count 2 2006.201.03:21:23.46#ibcon#about to read 6, iclass 18, count 2 2006.201.03:21:23.46#ibcon#read 6, iclass 18, count 2 2006.201.03:21:23.46#ibcon#end of sib2, iclass 18, count 2 2006.201.03:21:23.46#ibcon#*mode == 0, iclass 18, count 2 2006.201.03:21:23.46#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.03:21:23.46#ibcon#[25=AT08-04\r\n] 2006.201.03:21:23.46#ibcon#*before write, iclass 18, count 2 2006.201.03:21:23.46#ibcon#enter sib2, iclass 18, count 2 2006.201.03:21:23.46#ibcon#flushed, iclass 18, count 2 2006.201.03:21:23.46#ibcon#about to write, iclass 18, count 2 2006.201.03:21:23.46#ibcon#wrote, iclass 18, count 2 2006.201.03:21:23.46#ibcon#about to read 3, iclass 18, count 2 2006.201.03:21:23.49#ibcon#read 3, iclass 18, count 2 2006.201.03:21:23.49#ibcon#about to read 4, iclass 18, count 2 2006.201.03:21:23.49#ibcon#read 4, iclass 18, count 2 2006.201.03:21:23.49#ibcon#about to read 5, iclass 18, count 2 2006.201.03:21:23.49#ibcon#read 5, iclass 18, count 2 2006.201.03:21:23.49#ibcon#about to read 6, iclass 18, count 2 2006.201.03:21:23.49#ibcon#read 6, iclass 18, count 2 2006.201.03:21:23.49#ibcon#end of sib2, iclass 18, count 2 2006.201.03:21:23.49#ibcon#*after write, iclass 18, count 2 2006.201.03:21:23.49#ibcon#*before return 0, iclass 18, count 2 2006.201.03:21:23.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:21:23.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:21:23.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.03:21:23.49#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:23.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:21:23.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:21:23.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:21:23.61#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:21:23.61#ibcon#first serial, iclass 18, count 0 2006.201.03:21:23.61#ibcon#enter sib2, iclass 18, count 0 2006.201.03:21:23.61#ibcon#flushed, iclass 18, count 0 2006.201.03:21:23.61#ibcon#about to write, iclass 18, count 0 2006.201.03:21:23.61#ibcon#wrote, iclass 18, count 0 2006.201.03:21:23.61#ibcon#about to read 3, iclass 18, count 0 2006.201.03:21:23.63#ibcon#read 3, iclass 18, count 0 2006.201.03:21:23.63#ibcon#about to read 4, iclass 18, count 0 2006.201.03:21:23.63#ibcon#read 4, iclass 18, count 0 2006.201.03:21:23.63#ibcon#about to read 5, iclass 18, count 0 2006.201.03:21:23.63#ibcon#read 5, iclass 18, count 0 2006.201.03:21:23.63#ibcon#about to read 6, iclass 18, count 0 2006.201.03:21:23.63#ibcon#read 6, iclass 18, count 0 2006.201.03:21:23.63#ibcon#end of sib2, iclass 18, count 0 2006.201.03:21:23.63#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:21:23.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:21:23.63#ibcon#[25=USB\r\n] 2006.201.03:21:23.63#ibcon#*before write, iclass 18, count 0 2006.201.03:21:23.63#ibcon#enter sib2, iclass 18, count 0 2006.201.03:21:23.63#ibcon#flushed, iclass 18, count 0 2006.201.03:21:23.63#ibcon#about to write, iclass 18, count 0 2006.201.03:21:23.63#ibcon#wrote, iclass 18, count 0 2006.201.03:21:23.63#ibcon#about to read 3, iclass 18, count 0 2006.201.03:21:23.66#ibcon#read 3, iclass 18, count 0 2006.201.03:21:23.66#ibcon#about to read 4, iclass 18, count 0 2006.201.03:21:23.66#ibcon#read 4, iclass 18, count 0 2006.201.03:21:23.66#ibcon#about to read 5, iclass 18, count 0 2006.201.03:21:23.66#ibcon#read 5, iclass 18, count 0 2006.201.03:21:23.66#ibcon#about to read 6, iclass 18, count 0 2006.201.03:21:23.66#ibcon#read 6, iclass 18, count 0 2006.201.03:21:23.66#ibcon#end of sib2, iclass 18, count 0 2006.201.03:21:23.66#ibcon#*after write, iclass 18, count 0 2006.201.03:21:23.66#ibcon#*before return 0, iclass 18, count 0 2006.201.03:21:23.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:21:23.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:21:23.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:21:23.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:21:23.66$vck44/vblo=1,629.99 2006.201.03:21:23.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.03:21:23.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.03:21:23.66#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:23.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:21:23.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:21:23.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:21:23.66#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:21:23.66#ibcon#first serial, iclass 20, count 0 2006.201.03:21:23.66#ibcon#enter sib2, iclass 20, count 0 2006.201.03:21:23.66#ibcon#flushed, iclass 20, count 0 2006.201.03:21:23.66#ibcon#about to write, iclass 20, count 0 2006.201.03:21:23.66#ibcon#wrote, iclass 20, count 0 2006.201.03:21:23.66#ibcon#about to read 3, iclass 20, count 0 2006.201.03:21:23.68#ibcon#read 3, iclass 20, count 0 2006.201.03:21:23.68#ibcon#about to read 4, iclass 20, count 0 2006.201.03:21:23.68#ibcon#read 4, iclass 20, count 0 2006.201.03:21:23.68#ibcon#about to read 5, iclass 20, count 0 2006.201.03:21:23.68#ibcon#read 5, iclass 20, count 0 2006.201.03:21:23.68#ibcon#about to read 6, iclass 20, count 0 2006.201.03:21:23.68#ibcon#read 6, iclass 20, count 0 2006.201.03:21:23.68#ibcon#end of sib2, iclass 20, count 0 2006.201.03:21:23.68#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:21:23.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:21:23.68#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:21:23.68#ibcon#*before write, iclass 20, count 0 2006.201.03:21:23.68#ibcon#enter sib2, iclass 20, count 0 2006.201.03:21:23.68#ibcon#flushed, iclass 20, count 0 2006.201.03:21:23.68#ibcon#about to write, iclass 20, count 0 2006.201.03:21:23.68#ibcon#wrote, iclass 20, count 0 2006.201.03:21:23.68#ibcon#about to read 3, iclass 20, count 0 2006.201.03:21:23.72#ibcon#read 3, iclass 20, count 0 2006.201.03:21:23.72#ibcon#about to read 4, iclass 20, count 0 2006.201.03:21:23.72#ibcon#read 4, iclass 20, count 0 2006.201.03:21:23.72#ibcon#about to read 5, iclass 20, count 0 2006.201.03:21:23.72#ibcon#read 5, iclass 20, count 0 2006.201.03:21:23.72#ibcon#about to read 6, iclass 20, count 0 2006.201.03:21:23.72#ibcon#read 6, iclass 20, count 0 2006.201.03:21:23.72#ibcon#end of sib2, iclass 20, count 0 2006.201.03:21:23.72#ibcon#*after write, iclass 20, count 0 2006.201.03:21:23.72#ibcon#*before return 0, iclass 20, count 0 2006.201.03:21:23.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:21:23.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:21:23.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:21:23.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:21:23.72$vck44/vb=1,4 2006.201.03:21:23.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.03:21:23.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.03:21:23.72#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:23.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:21:23.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:21:23.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:21:23.72#ibcon#enter wrdev, iclass 22, count 2 2006.201.03:21:23.72#ibcon#first serial, iclass 22, count 2 2006.201.03:21:23.72#ibcon#enter sib2, iclass 22, count 2 2006.201.03:21:23.72#ibcon#flushed, iclass 22, count 2 2006.201.03:21:23.72#ibcon#about to write, iclass 22, count 2 2006.201.03:21:23.72#ibcon#wrote, iclass 22, count 2 2006.201.03:21:23.72#ibcon#about to read 3, iclass 22, count 2 2006.201.03:21:23.74#ibcon#read 3, iclass 22, count 2 2006.201.03:21:23.74#ibcon#about to read 4, iclass 22, count 2 2006.201.03:21:23.74#ibcon#read 4, iclass 22, count 2 2006.201.03:21:23.74#ibcon#about to read 5, iclass 22, count 2 2006.201.03:21:23.74#ibcon#read 5, iclass 22, count 2 2006.201.03:21:23.74#ibcon#about to read 6, iclass 22, count 2 2006.201.03:21:23.74#ibcon#read 6, iclass 22, count 2 2006.201.03:21:23.74#ibcon#end of sib2, iclass 22, count 2 2006.201.03:21:23.74#ibcon#*mode == 0, iclass 22, count 2 2006.201.03:21:23.74#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.03:21:23.74#ibcon#[27=AT01-04\r\n] 2006.201.03:21:23.74#ibcon#*before write, iclass 22, count 2 2006.201.03:21:23.74#ibcon#enter sib2, iclass 22, count 2 2006.201.03:21:23.74#ibcon#flushed, iclass 22, count 2 2006.201.03:21:23.74#ibcon#about to write, iclass 22, count 2 2006.201.03:21:23.74#ibcon#wrote, iclass 22, count 2 2006.201.03:21:23.74#ibcon#about to read 3, iclass 22, count 2 2006.201.03:21:23.77#ibcon#read 3, iclass 22, count 2 2006.201.03:21:23.77#ibcon#about to read 4, iclass 22, count 2 2006.201.03:21:23.77#ibcon#read 4, iclass 22, count 2 2006.201.03:21:23.77#ibcon#about to read 5, iclass 22, count 2 2006.201.03:21:23.77#ibcon#read 5, iclass 22, count 2 2006.201.03:21:23.77#ibcon#about to read 6, iclass 22, count 2 2006.201.03:21:23.77#ibcon#read 6, iclass 22, count 2 2006.201.03:21:23.77#ibcon#end of sib2, iclass 22, count 2 2006.201.03:21:23.77#ibcon#*after write, iclass 22, count 2 2006.201.03:21:23.77#ibcon#*before return 0, iclass 22, count 2 2006.201.03:21:23.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:21:23.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:21:23.77#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.03:21:23.77#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:23.77#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:21:23.89#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:21:23.89#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:21:23.89#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:21:23.89#ibcon#first serial, iclass 22, count 0 2006.201.03:21:23.89#ibcon#enter sib2, iclass 22, count 0 2006.201.03:21:23.89#ibcon#flushed, iclass 22, count 0 2006.201.03:21:23.89#ibcon#about to write, iclass 22, count 0 2006.201.03:21:23.89#ibcon#wrote, iclass 22, count 0 2006.201.03:21:23.89#ibcon#about to read 3, iclass 22, count 0 2006.201.03:21:23.91#ibcon#read 3, iclass 22, count 0 2006.201.03:21:23.91#ibcon#about to read 4, iclass 22, count 0 2006.201.03:21:23.91#ibcon#read 4, iclass 22, count 0 2006.201.03:21:23.91#ibcon#about to read 5, iclass 22, count 0 2006.201.03:21:23.91#ibcon#read 5, iclass 22, count 0 2006.201.03:21:23.91#ibcon#about to read 6, iclass 22, count 0 2006.201.03:21:23.91#ibcon#read 6, iclass 22, count 0 2006.201.03:21:23.91#ibcon#end of sib2, iclass 22, count 0 2006.201.03:21:23.91#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:21:23.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:21:23.91#ibcon#[27=USB\r\n] 2006.201.03:21:23.91#ibcon#*before write, iclass 22, count 0 2006.201.03:21:23.91#ibcon#enter sib2, iclass 22, count 0 2006.201.03:21:23.91#ibcon#flushed, iclass 22, count 0 2006.201.03:21:23.91#ibcon#about to write, iclass 22, count 0 2006.201.03:21:23.91#ibcon#wrote, iclass 22, count 0 2006.201.03:21:23.91#ibcon#about to read 3, iclass 22, count 0 2006.201.03:21:23.94#ibcon#read 3, iclass 22, count 0 2006.201.03:21:23.94#ibcon#about to read 4, iclass 22, count 0 2006.201.03:21:23.94#ibcon#read 4, iclass 22, count 0 2006.201.03:21:23.94#ibcon#about to read 5, iclass 22, count 0 2006.201.03:21:23.94#ibcon#read 5, iclass 22, count 0 2006.201.03:21:23.94#ibcon#about to read 6, iclass 22, count 0 2006.201.03:21:23.94#ibcon#read 6, iclass 22, count 0 2006.201.03:21:23.94#ibcon#end of sib2, iclass 22, count 0 2006.201.03:21:23.94#ibcon#*after write, iclass 22, count 0 2006.201.03:21:23.94#ibcon#*before return 0, iclass 22, count 0 2006.201.03:21:23.94#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:21:23.94#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:21:23.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:21:23.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:21:23.94$vck44/vblo=2,634.99 2006.201.03:21:23.94#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.03:21:23.94#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.03:21:23.94#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:23.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:23.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:23.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:23.94#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:21:23.94#ibcon#first serial, iclass 24, count 0 2006.201.03:21:23.94#ibcon#enter sib2, iclass 24, count 0 2006.201.03:21:23.94#ibcon#flushed, iclass 24, count 0 2006.201.03:21:23.94#ibcon#about to write, iclass 24, count 0 2006.201.03:21:23.94#ibcon#wrote, iclass 24, count 0 2006.201.03:21:23.94#ibcon#about to read 3, iclass 24, count 0 2006.201.03:21:23.96#ibcon#read 3, iclass 24, count 0 2006.201.03:21:23.96#ibcon#about to read 4, iclass 24, count 0 2006.201.03:21:23.96#ibcon#read 4, iclass 24, count 0 2006.201.03:21:23.96#ibcon#about to read 5, iclass 24, count 0 2006.201.03:21:23.96#ibcon#read 5, iclass 24, count 0 2006.201.03:21:23.96#ibcon#about to read 6, iclass 24, count 0 2006.201.03:21:23.96#ibcon#read 6, iclass 24, count 0 2006.201.03:21:23.96#ibcon#end of sib2, iclass 24, count 0 2006.201.03:21:23.96#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:21:23.96#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:21:23.96#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:21:23.96#ibcon#*before write, iclass 24, count 0 2006.201.03:21:23.96#ibcon#enter sib2, iclass 24, count 0 2006.201.03:21:23.96#ibcon#flushed, iclass 24, count 0 2006.201.03:21:23.96#ibcon#about to write, iclass 24, count 0 2006.201.03:21:23.96#ibcon#wrote, iclass 24, count 0 2006.201.03:21:23.96#ibcon#about to read 3, iclass 24, count 0 2006.201.03:21:24.00#ibcon#read 3, iclass 24, count 0 2006.201.03:21:24.00#ibcon#about to read 4, iclass 24, count 0 2006.201.03:21:24.00#ibcon#read 4, iclass 24, count 0 2006.201.03:21:24.00#ibcon#about to read 5, iclass 24, count 0 2006.201.03:21:24.00#ibcon#read 5, iclass 24, count 0 2006.201.03:21:24.00#ibcon#about to read 6, iclass 24, count 0 2006.201.03:21:24.00#ibcon#read 6, iclass 24, count 0 2006.201.03:21:24.00#ibcon#end of sib2, iclass 24, count 0 2006.201.03:21:24.00#ibcon#*after write, iclass 24, count 0 2006.201.03:21:24.00#ibcon#*before return 0, iclass 24, count 0 2006.201.03:21:24.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:24.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:21:24.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:21:24.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:21:24.00$vck44/vb=2,5 2006.201.03:21:24.00#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.03:21:24.00#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.03:21:24.00#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:24.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:24.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:24.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:24.06#ibcon#enter wrdev, iclass 26, count 2 2006.201.03:21:24.06#ibcon#first serial, iclass 26, count 2 2006.201.03:21:24.06#ibcon#enter sib2, iclass 26, count 2 2006.201.03:21:24.06#ibcon#flushed, iclass 26, count 2 2006.201.03:21:24.06#ibcon#about to write, iclass 26, count 2 2006.201.03:21:24.06#ibcon#wrote, iclass 26, count 2 2006.201.03:21:24.06#ibcon#about to read 3, iclass 26, count 2 2006.201.03:21:24.08#ibcon#read 3, iclass 26, count 2 2006.201.03:21:24.08#ibcon#about to read 4, iclass 26, count 2 2006.201.03:21:24.08#ibcon#read 4, iclass 26, count 2 2006.201.03:21:24.08#ibcon#about to read 5, iclass 26, count 2 2006.201.03:21:24.08#ibcon#read 5, iclass 26, count 2 2006.201.03:21:24.08#ibcon#about to read 6, iclass 26, count 2 2006.201.03:21:24.08#ibcon#read 6, iclass 26, count 2 2006.201.03:21:24.08#ibcon#end of sib2, iclass 26, count 2 2006.201.03:21:24.08#ibcon#*mode == 0, iclass 26, count 2 2006.201.03:21:24.08#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.03:21:24.08#ibcon#[27=AT02-05\r\n] 2006.201.03:21:24.08#ibcon#*before write, iclass 26, count 2 2006.201.03:21:24.08#ibcon#enter sib2, iclass 26, count 2 2006.201.03:21:24.08#ibcon#flushed, iclass 26, count 2 2006.201.03:21:24.08#ibcon#about to write, iclass 26, count 2 2006.201.03:21:24.08#ibcon#wrote, iclass 26, count 2 2006.201.03:21:24.08#ibcon#about to read 3, iclass 26, count 2 2006.201.03:21:24.11#ibcon#read 3, iclass 26, count 2 2006.201.03:21:24.11#ibcon#about to read 4, iclass 26, count 2 2006.201.03:21:24.11#ibcon#read 4, iclass 26, count 2 2006.201.03:21:24.11#ibcon#about to read 5, iclass 26, count 2 2006.201.03:21:24.11#ibcon#read 5, iclass 26, count 2 2006.201.03:21:24.11#ibcon#about to read 6, iclass 26, count 2 2006.201.03:21:24.11#ibcon#read 6, iclass 26, count 2 2006.201.03:21:24.11#ibcon#end of sib2, iclass 26, count 2 2006.201.03:21:24.11#ibcon#*after write, iclass 26, count 2 2006.201.03:21:24.11#ibcon#*before return 0, iclass 26, count 2 2006.201.03:21:24.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:24.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:21:24.11#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.03:21:24.11#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:24.11#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:24.23#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:24.23#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:24.23#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:21:24.23#ibcon#first serial, iclass 26, count 0 2006.201.03:21:24.23#ibcon#enter sib2, iclass 26, count 0 2006.201.03:21:24.23#ibcon#flushed, iclass 26, count 0 2006.201.03:21:24.23#ibcon#about to write, iclass 26, count 0 2006.201.03:21:24.23#ibcon#wrote, iclass 26, count 0 2006.201.03:21:24.23#ibcon#about to read 3, iclass 26, count 0 2006.201.03:21:24.25#ibcon#read 3, iclass 26, count 0 2006.201.03:21:24.25#ibcon#about to read 4, iclass 26, count 0 2006.201.03:21:24.25#ibcon#read 4, iclass 26, count 0 2006.201.03:21:24.25#ibcon#about to read 5, iclass 26, count 0 2006.201.03:21:24.25#ibcon#read 5, iclass 26, count 0 2006.201.03:21:24.25#ibcon#about to read 6, iclass 26, count 0 2006.201.03:21:24.25#ibcon#read 6, iclass 26, count 0 2006.201.03:21:24.25#ibcon#end of sib2, iclass 26, count 0 2006.201.03:21:24.25#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:21:24.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:21:24.25#ibcon#[27=USB\r\n] 2006.201.03:21:24.25#ibcon#*before write, iclass 26, count 0 2006.201.03:21:24.25#ibcon#enter sib2, iclass 26, count 0 2006.201.03:21:24.25#ibcon#flushed, iclass 26, count 0 2006.201.03:21:24.25#ibcon#about to write, iclass 26, count 0 2006.201.03:21:24.25#ibcon#wrote, iclass 26, count 0 2006.201.03:21:24.25#ibcon#about to read 3, iclass 26, count 0 2006.201.03:21:24.28#ibcon#read 3, iclass 26, count 0 2006.201.03:21:24.28#ibcon#about to read 4, iclass 26, count 0 2006.201.03:21:24.28#ibcon#read 4, iclass 26, count 0 2006.201.03:21:24.28#ibcon#about to read 5, iclass 26, count 0 2006.201.03:21:24.28#ibcon#read 5, iclass 26, count 0 2006.201.03:21:24.28#ibcon#about to read 6, iclass 26, count 0 2006.201.03:21:24.28#ibcon#read 6, iclass 26, count 0 2006.201.03:21:24.28#ibcon#end of sib2, iclass 26, count 0 2006.201.03:21:24.28#ibcon#*after write, iclass 26, count 0 2006.201.03:21:24.28#ibcon#*before return 0, iclass 26, count 0 2006.201.03:21:24.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:24.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:21:24.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:21:24.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:21:24.28$vck44/vblo=3,649.99 2006.201.03:21:24.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.03:21:24.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.03:21:24.28#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:24.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:24.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:24.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:24.28#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:21:24.28#ibcon#first serial, iclass 28, count 0 2006.201.03:21:24.28#ibcon#enter sib2, iclass 28, count 0 2006.201.03:21:24.28#ibcon#flushed, iclass 28, count 0 2006.201.03:21:24.28#ibcon#about to write, iclass 28, count 0 2006.201.03:21:24.28#ibcon#wrote, iclass 28, count 0 2006.201.03:21:24.28#ibcon#about to read 3, iclass 28, count 0 2006.201.03:21:24.30#ibcon#read 3, iclass 28, count 0 2006.201.03:21:24.30#ibcon#about to read 4, iclass 28, count 0 2006.201.03:21:24.30#ibcon#read 4, iclass 28, count 0 2006.201.03:21:24.30#ibcon#about to read 5, iclass 28, count 0 2006.201.03:21:24.30#ibcon#read 5, iclass 28, count 0 2006.201.03:21:24.30#ibcon#about to read 6, iclass 28, count 0 2006.201.03:21:24.30#ibcon#read 6, iclass 28, count 0 2006.201.03:21:24.30#ibcon#end of sib2, iclass 28, count 0 2006.201.03:21:24.30#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:21:24.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:21:24.30#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:21:24.30#ibcon#*before write, iclass 28, count 0 2006.201.03:21:24.30#ibcon#enter sib2, iclass 28, count 0 2006.201.03:21:24.30#ibcon#flushed, iclass 28, count 0 2006.201.03:21:24.30#ibcon#about to write, iclass 28, count 0 2006.201.03:21:24.30#ibcon#wrote, iclass 28, count 0 2006.201.03:21:24.30#ibcon#about to read 3, iclass 28, count 0 2006.201.03:21:24.34#ibcon#read 3, iclass 28, count 0 2006.201.03:21:24.34#ibcon#about to read 4, iclass 28, count 0 2006.201.03:21:24.34#ibcon#read 4, iclass 28, count 0 2006.201.03:21:24.34#ibcon#about to read 5, iclass 28, count 0 2006.201.03:21:24.34#ibcon#read 5, iclass 28, count 0 2006.201.03:21:24.34#ibcon#about to read 6, iclass 28, count 0 2006.201.03:21:24.34#ibcon#read 6, iclass 28, count 0 2006.201.03:21:24.34#ibcon#end of sib2, iclass 28, count 0 2006.201.03:21:24.34#ibcon#*after write, iclass 28, count 0 2006.201.03:21:24.34#ibcon#*before return 0, iclass 28, count 0 2006.201.03:21:24.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:24.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:21:24.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:21:24.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:21:24.34$vck44/vb=3,4 2006.201.03:21:24.34#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.03:21:24.34#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.03:21:24.34#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:24.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:24.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:24.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:24.40#ibcon#enter wrdev, iclass 30, count 2 2006.201.03:21:24.40#ibcon#first serial, iclass 30, count 2 2006.201.03:21:24.40#ibcon#enter sib2, iclass 30, count 2 2006.201.03:21:24.40#ibcon#flushed, iclass 30, count 2 2006.201.03:21:24.40#ibcon#about to write, iclass 30, count 2 2006.201.03:21:24.40#ibcon#wrote, iclass 30, count 2 2006.201.03:21:24.40#ibcon#about to read 3, iclass 30, count 2 2006.201.03:21:24.42#ibcon#read 3, iclass 30, count 2 2006.201.03:21:24.42#ibcon#about to read 4, iclass 30, count 2 2006.201.03:21:24.42#ibcon#read 4, iclass 30, count 2 2006.201.03:21:24.42#ibcon#about to read 5, iclass 30, count 2 2006.201.03:21:24.42#ibcon#read 5, iclass 30, count 2 2006.201.03:21:24.42#ibcon#about to read 6, iclass 30, count 2 2006.201.03:21:24.42#ibcon#read 6, iclass 30, count 2 2006.201.03:21:24.42#ibcon#end of sib2, iclass 30, count 2 2006.201.03:21:24.42#ibcon#*mode == 0, iclass 30, count 2 2006.201.03:21:24.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.03:21:24.42#ibcon#[27=AT03-04\r\n] 2006.201.03:21:24.42#ibcon#*before write, iclass 30, count 2 2006.201.03:21:24.42#ibcon#enter sib2, iclass 30, count 2 2006.201.03:21:24.42#ibcon#flushed, iclass 30, count 2 2006.201.03:21:24.42#ibcon#about to write, iclass 30, count 2 2006.201.03:21:24.42#ibcon#wrote, iclass 30, count 2 2006.201.03:21:24.42#ibcon#about to read 3, iclass 30, count 2 2006.201.03:21:24.45#ibcon#read 3, iclass 30, count 2 2006.201.03:21:24.45#ibcon#about to read 4, iclass 30, count 2 2006.201.03:21:24.45#ibcon#read 4, iclass 30, count 2 2006.201.03:21:24.45#ibcon#about to read 5, iclass 30, count 2 2006.201.03:21:24.45#ibcon#read 5, iclass 30, count 2 2006.201.03:21:24.45#ibcon#about to read 6, iclass 30, count 2 2006.201.03:21:24.45#ibcon#read 6, iclass 30, count 2 2006.201.03:21:24.45#ibcon#end of sib2, iclass 30, count 2 2006.201.03:21:24.45#ibcon#*after write, iclass 30, count 2 2006.201.03:21:24.45#ibcon#*before return 0, iclass 30, count 2 2006.201.03:21:24.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:24.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:21:24.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.03:21:24.45#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:24.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:24.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:24.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:24.57#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:21:24.57#ibcon#first serial, iclass 30, count 0 2006.201.03:21:24.57#ibcon#enter sib2, iclass 30, count 0 2006.201.03:21:24.57#ibcon#flushed, iclass 30, count 0 2006.201.03:21:24.57#ibcon#about to write, iclass 30, count 0 2006.201.03:21:24.57#ibcon#wrote, iclass 30, count 0 2006.201.03:21:24.57#ibcon#about to read 3, iclass 30, count 0 2006.201.03:21:24.59#ibcon#read 3, iclass 30, count 0 2006.201.03:21:24.59#ibcon#about to read 4, iclass 30, count 0 2006.201.03:21:24.59#ibcon#read 4, iclass 30, count 0 2006.201.03:21:24.59#ibcon#about to read 5, iclass 30, count 0 2006.201.03:21:24.59#ibcon#read 5, iclass 30, count 0 2006.201.03:21:24.59#ibcon#about to read 6, iclass 30, count 0 2006.201.03:21:24.59#ibcon#read 6, iclass 30, count 0 2006.201.03:21:24.59#ibcon#end of sib2, iclass 30, count 0 2006.201.03:21:24.59#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:21:24.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:21:24.59#ibcon#[27=USB\r\n] 2006.201.03:21:24.59#ibcon#*before write, iclass 30, count 0 2006.201.03:21:24.59#ibcon#enter sib2, iclass 30, count 0 2006.201.03:21:24.59#ibcon#flushed, iclass 30, count 0 2006.201.03:21:24.59#ibcon#about to write, iclass 30, count 0 2006.201.03:21:24.59#ibcon#wrote, iclass 30, count 0 2006.201.03:21:24.59#ibcon#about to read 3, iclass 30, count 0 2006.201.03:21:24.62#ibcon#read 3, iclass 30, count 0 2006.201.03:21:24.62#ibcon#about to read 4, iclass 30, count 0 2006.201.03:21:24.62#ibcon#read 4, iclass 30, count 0 2006.201.03:21:24.62#ibcon#about to read 5, iclass 30, count 0 2006.201.03:21:24.62#ibcon#read 5, iclass 30, count 0 2006.201.03:21:24.62#ibcon#about to read 6, iclass 30, count 0 2006.201.03:21:24.62#ibcon#read 6, iclass 30, count 0 2006.201.03:21:24.62#ibcon#end of sib2, iclass 30, count 0 2006.201.03:21:24.62#ibcon#*after write, iclass 30, count 0 2006.201.03:21:24.62#ibcon#*before return 0, iclass 30, count 0 2006.201.03:21:24.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:24.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:21:24.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:21:24.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:21:24.62$vck44/vblo=4,679.99 2006.201.03:21:24.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.03:21:24.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.03:21:24.62#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:24.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:24.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:24.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:24.62#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:21:24.62#ibcon#first serial, iclass 32, count 0 2006.201.03:21:24.62#ibcon#enter sib2, iclass 32, count 0 2006.201.03:21:24.62#ibcon#flushed, iclass 32, count 0 2006.201.03:21:24.62#ibcon#about to write, iclass 32, count 0 2006.201.03:21:24.62#ibcon#wrote, iclass 32, count 0 2006.201.03:21:24.62#ibcon#about to read 3, iclass 32, count 0 2006.201.03:21:24.64#ibcon#read 3, iclass 32, count 0 2006.201.03:21:24.64#ibcon#about to read 4, iclass 32, count 0 2006.201.03:21:24.64#ibcon#read 4, iclass 32, count 0 2006.201.03:21:24.64#ibcon#about to read 5, iclass 32, count 0 2006.201.03:21:24.64#ibcon#read 5, iclass 32, count 0 2006.201.03:21:24.64#ibcon#about to read 6, iclass 32, count 0 2006.201.03:21:24.64#ibcon#read 6, iclass 32, count 0 2006.201.03:21:24.64#ibcon#end of sib2, iclass 32, count 0 2006.201.03:21:24.64#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:21:24.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:21:24.64#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:21:24.64#ibcon#*before write, iclass 32, count 0 2006.201.03:21:24.64#ibcon#enter sib2, iclass 32, count 0 2006.201.03:21:24.64#ibcon#flushed, iclass 32, count 0 2006.201.03:21:24.64#ibcon#about to write, iclass 32, count 0 2006.201.03:21:24.64#ibcon#wrote, iclass 32, count 0 2006.201.03:21:24.64#ibcon#about to read 3, iclass 32, count 0 2006.201.03:21:24.68#ibcon#read 3, iclass 32, count 0 2006.201.03:21:24.68#ibcon#about to read 4, iclass 32, count 0 2006.201.03:21:24.68#ibcon#read 4, iclass 32, count 0 2006.201.03:21:24.68#ibcon#about to read 5, iclass 32, count 0 2006.201.03:21:24.68#ibcon#read 5, iclass 32, count 0 2006.201.03:21:24.68#ibcon#about to read 6, iclass 32, count 0 2006.201.03:21:24.68#ibcon#read 6, iclass 32, count 0 2006.201.03:21:24.68#ibcon#end of sib2, iclass 32, count 0 2006.201.03:21:24.68#ibcon#*after write, iclass 32, count 0 2006.201.03:21:24.68#ibcon#*before return 0, iclass 32, count 0 2006.201.03:21:24.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:24.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:21:24.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:21:24.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:21:24.68$vck44/vb=4,5 2006.201.03:21:24.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.03:21:24.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.03:21:24.68#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:24.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:24.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:24.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:24.74#ibcon#enter wrdev, iclass 34, count 2 2006.201.03:21:24.74#ibcon#first serial, iclass 34, count 2 2006.201.03:21:24.74#ibcon#enter sib2, iclass 34, count 2 2006.201.03:21:24.74#ibcon#flushed, iclass 34, count 2 2006.201.03:21:24.74#ibcon#about to write, iclass 34, count 2 2006.201.03:21:24.74#ibcon#wrote, iclass 34, count 2 2006.201.03:21:24.74#ibcon#about to read 3, iclass 34, count 2 2006.201.03:21:24.76#ibcon#read 3, iclass 34, count 2 2006.201.03:21:24.76#ibcon#about to read 4, iclass 34, count 2 2006.201.03:21:24.76#ibcon#read 4, iclass 34, count 2 2006.201.03:21:24.76#ibcon#about to read 5, iclass 34, count 2 2006.201.03:21:24.76#ibcon#read 5, iclass 34, count 2 2006.201.03:21:24.76#ibcon#about to read 6, iclass 34, count 2 2006.201.03:21:24.76#ibcon#read 6, iclass 34, count 2 2006.201.03:21:24.76#ibcon#end of sib2, iclass 34, count 2 2006.201.03:21:24.76#ibcon#*mode == 0, iclass 34, count 2 2006.201.03:21:24.76#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.03:21:24.76#ibcon#[27=AT04-05\r\n] 2006.201.03:21:24.76#ibcon#*before write, iclass 34, count 2 2006.201.03:21:24.76#ibcon#enter sib2, iclass 34, count 2 2006.201.03:21:24.76#ibcon#flushed, iclass 34, count 2 2006.201.03:21:24.76#ibcon#about to write, iclass 34, count 2 2006.201.03:21:24.76#ibcon#wrote, iclass 34, count 2 2006.201.03:21:24.76#ibcon#about to read 3, iclass 34, count 2 2006.201.03:21:24.79#ibcon#read 3, iclass 34, count 2 2006.201.03:21:24.79#ibcon#about to read 4, iclass 34, count 2 2006.201.03:21:24.79#ibcon#read 4, iclass 34, count 2 2006.201.03:21:24.79#ibcon#about to read 5, iclass 34, count 2 2006.201.03:21:24.79#ibcon#read 5, iclass 34, count 2 2006.201.03:21:24.79#ibcon#about to read 6, iclass 34, count 2 2006.201.03:21:24.79#ibcon#read 6, iclass 34, count 2 2006.201.03:21:24.79#ibcon#end of sib2, iclass 34, count 2 2006.201.03:21:24.79#ibcon#*after write, iclass 34, count 2 2006.201.03:21:24.79#ibcon#*before return 0, iclass 34, count 2 2006.201.03:21:24.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:24.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:21:24.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.03:21:24.79#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:24.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:24.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:24.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:24.91#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:21:24.91#ibcon#first serial, iclass 34, count 0 2006.201.03:21:24.91#ibcon#enter sib2, iclass 34, count 0 2006.201.03:21:24.91#ibcon#flushed, iclass 34, count 0 2006.201.03:21:24.91#ibcon#about to write, iclass 34, count 0 2006.201.03:21:24.91#ibcon#wrote, iclass 34, count 0 2006.201.03:21:24.91#ibcon#about to read 3, iclass 34, count 0 2006.201.03:21:24.93#ibcon#read 3, iclass 34, count 0 2006.201.03:21:24.93#ibcon#about to read 4, iclass 34, count 0 2006.201.03:21:24.93#ibcon#read 4, iclass 34, count 0 2006.201.03:21:24.93#ibcon#about to read 5, iclass 34, count 0 2006.201.03:21:24.93#ibcon#read 5, iclass 34, count 0 2006.201.03:21:24.93#ibcon#about to read 6, iclass 34, count 0 2006.201.03:21:24.93#ibcon#read 6, iclass 34, count 0 2006.201.03:21:24.93#ibcon#end of sib2, iclass 34, count 0 2006.201.03:21:24.93#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:21:24.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:21:24.93#ibcon#[27=USB\r\n] 2006.201.03:21:24.93#ibcon#*before write, iclass 34, count 0 2006.201.03:21:24.93#ibcon#enter sib2, iclass 34, count 0 2006.201.03:21:24.93#ibcon#flushed, iclass 34, count 0 2006.201.03:21:24.93#ibcon#about to write, iclass 34, count 0 2006.201.03:21:24.93#ibcon#wrote, iclass 34, count 0 2006.201.03:21:24.93#ibcon#about to read 3, iclass 34, count 0 2006.201.03:21:24.96#ibcon#read 3, iclass 34, count 0 2006.201.03:21:24.96#ibcon#about to read 4, iclass 34, count 0 2006.201.03:21:24.96#ibcon#read 4, iclass 34, count 0 2006.201.03:21:24.96#ibcon#about to read 5, iclass 34, count 0 2006.201.03:21:24.96#ibcon#read 5, iclass 34, count 0 2006.201.03:21:24.96#ibcon#about to read 6, iclass 34, count 0 2006.201.03:21:24.96#ibcon#read 6, iclass 34, count 0 2006.201.03:21:24.96#ibcon#end of sib2, iclass 34, count 0 2006.201.03:21:24.96#ibcon#*after write, iclass 34, count 0 2006.201.03:21:24.96#ibcon#*before return 0, iclass 34, count 0 2006.201.03:21:24.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:24.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:21:24.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:21:24.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:21:24.96$vck44/vblo=5,709.99 2006.201.03:21:24.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.03:21:24.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.03:21:24.96#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:24.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:24.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:24.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:24.96#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:21:24.96#ibcon#first serial, iclass 36, count 0 2006.201.03:21:24.96#ibcon#enter sib2, iclass 36, count 0 2006.201.03:21:24.96#ibcon#flushed, iclass 36, count 0 2006.201.03:21:24.96#ibcon#about to write, iclass 36, count 0 2006.201.03:21:24.96#ibcon#wrote, iclass 36, count 0 2006.201.03:21:24.96#ibcon#about to read 3, iclass 36, count 0 2006.201.03:21:24.98#ibcon#read 3, iclass 36, count 0 2006.201.03:21:24.98#ibcon#about to read 4, iclass 36, count 0 2006.201.03:21:24.98#ibcon#read 4, iclass 36, count 0 2006.201.03:21:24.98#ibcon#about to read 5, iclass 36, count 0 2006.201.03:21:24.98#ibcon#read 5, iclass 36, count 0 2006.201.03:21:24.98#ibcon#about to read 6, iclass 36, count 0 2006.201.03:21:24.98#ibcon#read 6, iclass 36, count 0 2006.201.03:21:24.98#ibcon#end of sib2, iclass 36, count 0 2006.201.03:21:24.98#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:21:24.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:21:24.98#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:21:24.98#ibcon#*before write, iclass 36, count 0 2006.201.03:21:24.98#ibcon#enter sib2, iclass 36, count 0 2006.201.03:21:24.98#ibcon#flushed, iclass 36, count 0 2006.201.03:21:24.98#ibcon#about to write, iclass 36, count 0 2006.201.03:21:24.98#ibcon#wrote, iclass 36, count 0 2006.201.03:21:24.98#ibcon#about to read 3, iclass 36, count 0 2006.201.03:21:25.02#ibcon#read 3, iclass 36, count 0 2006.201.03:21:25.02#ibcon#about to read 4, iclass 36, count 0 2006.201.03:21:25.02#ibcon#read 4, iclass 36, count 0 2006.201.03:21:25.02#ibcon#about to read 5, iclass 36, count 0 2006.201.03:21:25.02#ibcon#read 5, iclass 36, count 0 2006.201.03:21:25.02#ibcon#about to read 6, iclass 36, count 0 2006.201.03:21:25.02#ibcon#read 6, iclass 36, count 0 2006.201.03:21:25.02#ibcon#end of sib2, iclass 36, count 0 2006.201.03:21:25.02#ibcon#*after write, iclass 36, count 0 2006.201.03:21:25.02#ibcon#*before return 0, iclass 36, count 0 2006.201.03:21:25.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:25.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:21:25.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:21:25.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:21:25.02$vck44/vb=5,4 2006.201.03:21:25.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.03:21:25.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.03:21:25.02#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:25.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:25.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:25.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:25.08#ibcon#enter wrdev, iclass 38, count 2 2006.201.03:21:25.08#ibcon#first serial, iclass 38, count 2 2006.201.03:21:25.08#ibcon#enter sib2, iclass 38, count 2 2006.201.03:21:25.08#ibcon#flushed, iclass 38, count 2 2006.201.03:21:25.08#ibcon#about to write, iclass 38, count 2 2006.201.03:21:25.08#ibcon#wrote, iclass 38, count 2 2006.201.03:21:25.08#ibcon#about to read 3, iclass 38, count 2 2006.201.03:21:25.10#ibcon#read 3, iclass 38, count 2 2006.201.03:21:25.10#ibcon#about to read 4, iclass 38, count 2 2006.201.03:21:25.10#ibcon#read 4, iclass 38, count 2 2006.201.03:21:25.10#ibcon#about to read 5, iclass 38, count 2 2006.201.03:21:25.10#ibcon#read 5, iclass 38, count 2 2006.201.03:21:25.10#ibcon#about to read 6, iclass 38, count 2 2006.201.03:21:25.10#ibcon#read 6, iclass 38, count 2 2006.201.03:21:25.10#ibcon#end of sib2, iclass 38, count 2 2006.201.03:21:25.10#ibcon#*mode == 0, iclass 38, count 2 2006.201.03:21:25.10#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.03:21:25.10#ibcon#[27=AT05-04\r\n] 2006.201.03:21:25.10#ibcon#*before write, iclass 38, count 2 2006.201.03:21:25.10#ibcon#enter sib2, iclass 38, count 2 2006.201.03:21:25.10#ibcon#flushed, iclass 38, count 2 2006.201.03:21:25.10#ibcon#about to write, iclass 38, count 2 2006.201.03:21:25.10#ibcon#wrote, iclass 38, count 2 2006.201.03:21:25.10#ibcon#about to read 3, iclass 38, count 2 2006.201.03:21:25.13#ibcon#read 3, iclass 38, count 2 2006.201.03:21:25.13#ibcon#about to read 4, iclass 38, count 2 2006.201.03:21:25.13#ibcon#read 4, iclass 38, count 2 2006.201.03:21:25.13#ibcon#about to read 5, iclass 38, count 2 2006.201.03:21:25.13#ibcon#read 5, iclass 38, count 2 2006.201.03:21:25.13#ibcon#about to read 6, iclass 38, count 2 2006.201.03:21:25.13#ibcon#read 6, iclass 38, count 2 2006.201.03:21:25.13#ibcon#end of sib2, iclass 38, count 2 2006.201.03:21:25.13#ibcon#*after write, iclass 38, count 2 2006.201.03:21:25.13#ibcon#*before return 0, iclass 38, count 2 2006.201.03:21:25.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:25.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:21:25.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.03:21:25.13#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:25.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:25.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:25.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:25.25#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:21:25.25#ibcon#first serial, iclass 38, count 0 2006.201.03:21:25.25#ibcon#enter sib2, iclass 38, count 0 2006.201.03:21:25.25#ibcon#flushed, iclass 38, count 0 2006.201.03:21:25.25#ibcon#about to write, iclass 38, count 0 2006.201.03:21:25.25#ibcon#wrote, iclass 38, count 0 2006.201.03:21:25.25#ibcon#about to read 3, iclass 38, count 0 2006.201.03:21:25.27#ibcon#read 3, iclass 38, count 0 2006.201.03:21:25.27#ibcon#about to read 4, iclass 38, count 0 2006.201.03:21:25.27#ibcon#read 4, iclass 38, count 0 2006.201.03:21:25.27#ibcon#about to read 5, iclass 38, count 0 2006.201.03:21:25.27#ibcon#read 5, iclass 38, count 0 2006.201.03:21:25.27#ibcon#about to read 6, iclass 38, count 0 2006.201.03:21:25.27#ibcon#read 6, iclass 38, count 0 2006.201.03:21:25.27#ibcon#end of sib2, iclass 38, count 0 2006.201.03:21:25.27#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:21:25.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:21:25.27#ibcon#[27=USB\r\n] 2006.201.03:21:25.27#ibcon#*before write, iclass 38, count 0 2006.201.03:21:25.27#ibcon#enter sib2, iclass 38, count 0 2006.201.03:21:25.27#ibcon#flushed, iclass 38, count 0 2006.201.03:21:25.27#ibcon#about to write, iclass 38, count 0 2006.201.03:21:25.27#ibcon#wrote, iclass 38, count 0 2006.201.03:21:25.27#ibcon#about to read 3, iclass 38, count 0 2006.201.03:21:25.30#ibcon#read 3, iclass 38, count 0 2006.201.03:21:25.30#ibcon#about to read 4, iclass 38, count 0 2006.201.03:21:25.30#ibcon#read 4, iclass 38, count 0 2006.201.03:21:25.30#ibcon#about to read 5, iclass 38, count 0 2006.201.03:21:25.30#ibcon#read 5, iclass 38, count 0 2006.201.03:21:25.30#ibcon#about to read 6, iclass 38, count 0 2006.201.03:21:25.30#ibcon#read 6, iclass 38, count 0 2006.201.03:21:25.30#ibcon#end of sib2, iclass 38, count 0 2006.201.03:21:25.30#ibcon#*after write, iclass 38, count 0 2006.201.03:21:25.30#ibcon#*before return 0, iclass 38, count 0 2006.201.03:21:25.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:25.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:21:25.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:21:25.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:21:25.30$vck44/vblo=6,719.99 2006.201.03:21:25.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.03:21:25.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.03:21:25.30#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:25.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:25.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:25.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:25.30#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:21:25.30#ibcon#first serial, iclass 40, count 0 2006.201.03:21:25.30#ibcon#enter sib2, iclass 40, count 0 2006.201.03:21:25.30#ibcon#flushed, iclass 40, count 0 2006.201.03:21:25.30#ibcon#about to write, iclass 40, count 0 2006.201.03:21:25.30#ibcon#wrote, iclass 40, count 0 2006.201.03:21:25.30#ibcon#about to read 3, iclass 40, count 0 2006.201.03:21:25.32#ibcon#read 3, iclass 40, count 0 2006.201.03:21:25.32#ibcon#about to read 4, iclass 40, count 0 2006.201.03:21:25.32#ibcon#read 4, iclass 40, count 0 2006.201.03:21:25.32#ibcon#about to read 5, iclass 40, count 0 2006.201.03:21:25.32#ibcon#read 5, iclass 40, count 0 2006.201.03:21:25.32#ibcon#about to read 6, iclass 40, count 0 2006.201.03:21:25.32#ibcon#read 6, iclass 40, count 0 2006.201.03:21:25.32#ibcon#end of sib2, iclass 40, count 0 2006.201.03:21:25.32#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:21:25.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:21:25.32#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:21:25.32#ibcon#*before write, iclass 40, count 0 2006.201.03:21:25.32#ibcon#enter sib2, iclass 40, count 0 2006.201.03:21:25.32#ibcon#flushed, iclass 40, count 0 2006.201.03:21:25.32#ibcon#about to write, iclass 40, count 0 2006.201.03:21:25.32#ibcon#wrote, iclass 40, count 0 2006.201.03:21:25.32#ibcon#about to read 3, iclass 40, count 0 2006.201.03:21:25.36#ibcon#read 3, iclass 40, count 0 2006.201.03:21:25.36#ibcon#about to read 4, iclass 40, count 0 2006.201.03:21:25.36#ibcon#read 4, iclass 40, count 0 2006.201.03:21:25.36#ibcon#about to read 5, iclass 40, count 0 2006.201.03:21:25.36#ibcon#read 5, iclass 40, count 0 2006.201.03:21:25.36#ibcon#about to read 6, iclass 40, count 0 2006.201.03:21:25.36#ibcon#read 6, iclass 40, count 0 2006.201.03:21:25.36#ibcon#end of sib2, iclass 40, count 0 2006.201.03:21:25.36#ibcon#*after write, iclass 40, count 0 2006.201.03:21:25.36#ibcon#*before return 0, iclass 40, count 0 2006.201.03:21:25.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:25.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:21:25.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:21:25.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:21:25.36$vck44/vb=6,4 2006.201.03:21:25.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.03:21:25.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.03:21:25.36#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:25.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:25.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:25.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:25.42#ibcon#enter wrdev, iclass 4, count 2 2006.201.03:21:25.42#ibcon#first serial, iclass 4, count 2 2006.201.03:21:25.42#ibcon#enter sib2, iclass 4, count 2 2006.201.03:21:25.42#ibcon#flushed, iclass 4, count 2 2006.201.03:21:25.42#ibcon#about to write, iclass 4, count 2 2006.201.03:21:25.42#ibcon#wrote, iclass 4, count 2 2006.201.03:21:25.42#ibcon#about to read 3, iclass 4, count 2 2006.201.03:21:25.44#ibcon#read 3, iclass 4, count 2 2006.201.03:21:25.44#ibcon#about to read 4, iclass 4, count 2 2006.201.03:21:25.44#ibcon#read 4, iclass 4, count 2 2006.201.03:21:25.44#ibcon#about to read 5, iclass 4, count 2 2006.201.03:21:25.44#ibcon#read 5, iclass 4, count 2 2006.201.03:21:25.44#ibcon#about to read 6, iclass 4, count 2 2006.201.03:21:25.44#ibcon#read 6, iclass 4, count 2 2006.201.03:21:25.44#ibcon#end of sib2, iclass 4, count 2 2006.201.03:21:25.44#ibcon#*mode == 0, iclass 4, count 2 2006.201.03:21:25.44#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.03:21:25.44#ibcon#[27=AT06-04\r\n] 2006.201.03:21:25.44#ibcon#*before write, iclass 4, count 2 2006.201.03:21:25.44#ibcon#enter sib2, iclass 4, count 2 2006.201.03:21:25.44#ibcon#flushed, iclass 4, count 2 2006.201.03:21:25.44#ibcon#about to write, iclass 4, count 2 2006.201.03:21:25.44#ibcon#wrote, iclass 4, count 2 2006.201.03:21:25.44#ibcon#about to read 3, iclass 4, count 2 2006.201.03:21:25.47#ibcon#read 3, iclass 4, count 2 2006.201.03:21:25.47#ibcon#about to read 4, iclass 4, count 2 2006.201.03:21:25.47#ibcon#read 4, iclass 4, count 2 2006.201.03:21:25.47#ibcon#about to read 5, iclass 4, count 2 2006.201.03:21:25.47#ibcon#read 5, iclass 4, count 2 2006.201.03:21:25.47#ibcon#about to read 6, iclass 4, count 2 2006.201.03:21:25.47#ibcon#read 6, iclass 4, count 2 2006.201.03:21:25.47#ibcon#end of sib2, iclass 4, count 2 2006.201.03:21:25.47#ibcon#*after write, iclass 4, count 2 2006.201.03:21:25.47#ibcon#*before return 0, iclass 4, count 2 2006.201.03:21:25.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:25.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:21:25.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.03:21:25.47#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:25.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:25.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:25.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:25.59#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:21:25.59#ibcon#first serial, iclass 4, count 0 2006.201.03:21:25.59#ibcon#enter sib2, iclass 4, count 0 2006.201.03:21:25.59#ibcon#flushed, iclass 4, count 0 2006.201.03:21:25.59#ibcon#about to write, iclass 4, count 0 2006.201.03:21:25.59#ibcon#wrote, iclass 4, count 0 2006.201.03:21:25.59#ibcon#about to read 3, iclass 4, count 0 2006.201.03:21:25.61#ibcon#read 3, iclass 4, count 0 2006.201.03:21:25.61#ibcon#about to read 4, iclass 4, count 0 2006.201.03:21:25.61#ibcon#read 4, iclass 4, count 0 2006.201.03:21:25.61#ibcon#about to read 5, iclass 4, count 0 2006.201.03:21:25.61#ibcon#read 5, iclass 4, count 0 2006.201.03:21:25.61#ibcon#about to read 6, iclass 4, count 0 2006.201.03:21:25.61#ibcon#read 6, iclass 4, count 0 2006.201.03:21:25.61#ibcon#end of sib2, iclass 4, count 0 2006.201.03:21:25.61#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:21:25.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:21:25.61#ibcon#[27=USB\r\n] 2006.201.03:21:25.61#ibcon#*before write, iclass 4, count 0 2006.201.03:21:25.61#ibcon#enter sib2, iclass 4, count 0 2006.201.03:21:25.61#ibcon#flushed, iclass 4, count 0 2006.201.03:21:25.61#ibcon#about to write, iclass 4, count 0 2006.201.03:21:25.61#ibcon#wrote, iclass 4, count 0 2006.201.03:21:25.61#ibcon#about to read 3, iclass 4, count 0 2006.201.03:21:25.64#ibcon#read 3, iclass 4, count 0 2006.201.03:21:25.64#ibcon#about to read 4, iclass 4, count 0 2006.201.03:21:25.64#ibcon#read 4, iclass 4, count 0 2006.201.03:21:25.64#ibcon#about to read 5, iclass 4, count 0 2006.201.03:21:25.64#ibcon#read 5, iclass 4, count 0 2006.201.03:21:25.64#ibcon#about to read 6, iclass 4, count 0 2006.201.03:21:25.64#ibcon#read 6, iclass 4, count 0 2006.201.03:21:25.64#ibcon#end of sib2, iclass 4, count 0 2006.201.03:21:25.64#ibcon#*after write, iclass 4, count 0 2006.201.03:21:25.64#ibcon#*before return 0, iclass 4, count 0 2006.201.03:21:25.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:25.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:21:25.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:21:25.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:21:25.64$vck44/vblo=7,734.99 2006.201.03:21:25.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.03:21:25.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.03:21:25.64#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:25.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:25.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:25.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:25.64#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:21:25.64#ibcon#first serial, iclass 6, count 0 2006.201.03:21:25.64#ibcon#enter sib2, iclass 6, count 0 2006.201.03:21:25.64#ibcon#flushed, iclass 6, count 0 2006.201.03:21:25.64#ibcon#about to write, iclass 6, count 0 2006.201.03:21:25.64#ibcon#wrote, iclass 6, count 0 2006.201.03:21:25.64#ibcon#about to read 3, iclass 6, count 0 2006.201.03:21:25.66#ibcon#read 3, iclass 6, count 0 2006.201.03:21:25.66#ibcon#about to read 4, iclass 6, count 0 2006.201.03:21:25.66#ibcon#read 4, iclass 6, count 0 2006.201.03:21:25.66#ibcon#about to read 5, iclass 6, count 0 2006.201.03:21:25.66#ibcon#read 5, iclass 6, count 0 2006.201.03:21:25.66#ibcon#about to read 6, iclass 6, count 0 2006.201.03:21:25.66#ibcon#read 6, iclass 6, count 0 2006.201.03:21:25.66#ibcon#end of sib2, iclass 6, count 0 2006.201.03:21:25.66#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:21:25.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:21:25.66#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:21:25.66#ibcon#*before write, iclass 6, count 0 2006.201.03:21:25.66#ibcon#enter sib2, iclass 6, count 0 2006.201.03:21:25.66#ibcon#flushed, iclass 6, count 0 2006.201.03:21:25.66#ibcon#about to write, iclass 6, count 0 2006.201.03:21:25.66#ibcon#wrote, iclass 6, count 0 2006.201.03:21:25.66#ibcon#about to read 3, iclass 6, count 0 2006.201.03:21:25.70#ibcon#read 3, iclass 6, count 0 2006.201.03:21:25.70#ibcon#about to read 4, iclass 6, count 0 2006.201.03:21:25.70#ibcon#read 4, iclass 6, count 0 2006.201.03:21:25.70#ibcon#about to read 5, iclass 6, count 0 2006.201.03:21:25.70#ibcon#read 5, iclass 6, count 0 2006.201.03:21:25.70#ibcon#about to read 6, iclass 6, count 0 2006.201.03:21:25.70#ibcon#read 6, iclass 6, count 0 2006.201.03:21:25.70#ibcon#end of sib2, iclass 6, count 0 2006.201.03:21:25.70#ibcon#*after write, iclass 6, count 0 2006.201.03:21:25.70#ibcon#*before return 0, iclass 6, count 0 2006.201.03:21:25.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:25.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:21:25.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:21:25.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:21:25.70$vck44/vb=7,4 2006.201.03:21:25.70#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.03:21:25.70#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.03:21:25.70#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:25.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:25.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:25.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:25.76#ibcon#enter wrdev, iclass 10, count 2 2006.201.03:21:25.76#ibcon#first serial, iclass 10, count 2 2006.201.03:21:25.76#ibcon#enter sib2, iclass 10, count 2 2006.201.03:21:25.76#ibcon#flushed, iclass 10, count 2 2006.201.03:21:25.76#ibcon#about to write, iclass 10, count 2 2006.201.03:21:25.76#ibcon#wrote, iclass 10, count 2 2006.201.03:21:25.76#ibcon#about to read 3, iclass 10, count 2 2006.201.03:21:25.78#ibcon#read 3, iclass 10, count 2 2006.201.03:21:25.78#ibcon#about to read 4, iclass 10, count 2 2006.201.03:21:25.78#ibcon#read 4, iclass 10, count 2 2006.201.03:21:25.78#ibcon#about to read 5, iclass 10, count 2 2006.201.03:21:25.78#ibcon#read 5, iclass 10, count 2 2006.201.03:21:25.78#ibcon#about to read 6, iclass 10, count 2 2006.201.03:21:25.78#ibcon#read 6, iclass 10, count 2 2006.201.03:21:25.78#ibcon#end of sib2, iclass 10, count 2 2006.201.03:21:25.78#ibcon#*mode == 0, iclass 10, count 2 2006.201.03:21:25.78#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.03:21:25.78#ibcon#[27=AT07-04\r\n] 2006.201.03:21:25.78#ibcon#*before write, iclass 10, count 2 2006.201.03:21:25.78#ibcon#enter sib2, iclass 10, count 2 2006.201.03:21:25.78#ibcon#flushed, iclass 10, count 2 2006.201.03:21:25.78#ibcon#about to write, iclass 10, count 2 2006.201.03:21:25.78#ibcon#wrote, iclass 10, count 2 2006.201.03:21:25.78#ibcon#about to read 3, iclass 10, count 2 2006.201.03:21:25.81#ibcon#read 3, iclass 10, count 2 2006.201.03:21:25.81#ibcon#about to read 4, iclass 10, count 2 2006.201.03:21:25.81#ibcon#read 4, iclass 10, count 2 2006.201.03:21:25.81#ibcon#about to read 5, iclass 10, count 2 2006.201.03:21:25.81#ibcon#read 5, iclass 10, count 2 2006.201.03:21:25.81#ibcon#about to read 6, iclass 10, count 2 2006.201.03:21:25.81#ibcon#read 6, iclass 10, count 2 2006.201.03:21:25.81#ibcon#end of sib2, iclass 10, count 2 2006.201.03:21:25.81#ibcon#*after write, iclass 10, count 2 2006.201.03:21:25.81#ibcon#*before return 0, iclass 10, count 2 2006.201.03:21:25.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:25.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:21:25.81#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.03:21:25.81#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:25.81#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:25.93#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:25.93#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:25.93#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:21:25.93#ibcon#first serial, iclass 10, count 0 2006.201.03:21:25.93#ibcon#enter sib2, iclass 10, count 0 2006.201.03:21:25.93#ibcon#flushed, iclass 10, count 0 2006.201.03:21:25.93#ibcon#about to write, iclass 10, count 0 2006.201.03:21:25.93#ibcon#wrote, iclass 10, count 0 2006.201.03:21:25.93#ibcon#about to read 3, iclass 10, count 0 2006.201.03:21:25.95#ibcon#read 3, iclass 10, count 0 2006.201.03:21:25.95#ibcon#about to read 4, iclass 10, count 0 2006.201.03:21:25.95#ibcon#read 4, iclass 10, count 0 2006.201.03:21:25.95#ibcon#about to read 5, iclass 10, count 0 2006.201.03:21:25.95#ibcon#read 5, iclass 10, count 0 2006.201.03:21:25.95#ibcon#about to read 6, iclass 10, count 0 2006.201.03:21:25.95#ibcon#read 6, iclass 10, count 0 2006.201.03:21:25.95#ibcon#end of sib2, iclass 10, count 0 2006.201.03:21:25.95#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:21:25.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:21:25.95#ibcon#[27=USB\r\n] 2006.201.03:21:25.95#ibcon#*before write, iclass 10, count 0 2006.201.03:21:25.95#ibcon#enter sib2, iclass 10, count 0 2006.201.03:21:25.95#ibcon#flushed, iclass 10, count 0 2006.201.03:21:25.95#ibcon#about to write, iclass 10, count 0 2006.201.03:21:25.95#ibcon#wrote, iclass 10, count 0 2006.201.03:21:25.95#ibcon#about to read 3, iclass 10, count 0 2006.201.03:21:25.98#ibcon#read 3, iclass 10, count 0 2006.201.03:21:25.98#ibcon#about to read 4, iclass 10, count 0 2006.201.03:21:25.98#ibcon#read 4, iclass 10, count 0 2006.201.03:21:25.98#ibcon#about to read 5, iclass 10, count 0 2006.201.03:21:25.98#ibcon#read 5, iclass 10, count 0 2006.201.03:21:25.98#ibcon#about to read 6, iclass 10, count 0 2006.201.03:21:25.98#ibcon#read 6, iclass 10, count 0 2006.201.03:21:25.98#ibcon#end of sib2, iclass 10, count 0 2006.201.03:21:25.98#ibcon#*after write, iclass 10, count 0 2006.201.03:21:25.98#ibcon#*before return 0, iclass 10, count 0 2006.201.03:21:25.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:25.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:21:25.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:21:25.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:21:25.98$vck44/vblo=8,744.99 2006.201.03:21:25.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.03:21:25.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.03:21:25.98#ibcon#ireg 17 cls_cnt 0 2006.201.03:21:25.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:25.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:25.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:25.98#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:21:25.98#ibcon#first serial, iclass 12, count 0 2006.201.03:21:25.98#ibcon#enter sib2, iclass 12, count 0 2006.201.03:21:25.98#ibcon#flushed, iclass 12, count 0 2006.201.03:21:25.98#ibcon#about to write, iclass 12, count 0 2006.201.03:21:25.98#ibcon#wrote, iclass 12, count 0 2006.201.03:21:25.98#ibcon#about to read 3, iclass 12, count 0 2006.201.03:21:26.00#ibcon#read 3, iclass 12, count 0 2006.201.03:21:26.00#ibcon#about to read 4, iclass 12, count 0 2006.201.03:21:26.00#ibcon#read 4, iclass 12, count 0 2006.201.03:21:26.00#ibcon#about to read 5, iclass 12, count 0 2006.201.03:21:26.00#ibcon#read 5, iclass 12, count 0 2006.201.03:21:26.00#ibcon#about to read 6, iclass 12, count 0 2006.201.03:21:26.00#ibcon#read 6, iclass 12, count 0 2006.201.03:21:26.00#ibcon#end of sib2, iclass 12, count 0 2006.201.03:21:26.00#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:21:26.00#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:21:26.00#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:21:26.00#ibcon#*before write, iclass 12, count 0 2006.201.03:21:26.00#ibcon#enter sib2, iclass 12, count 0 2006.201.03:21:26.00#ibcon#flushed, iclass 12, count 0 2006.201.03:21:26.00#ibcon#about to write, iclass 12, count 0 2006.201.03:21:26.00#ibcon#wrote, iclass 12, count 0 2006.201.03:21:26.00#ibcon#about to read 3, iclass 12, count 0 2006.201.03:21:26.04#ibcon#read 3, iclass 12, count 0 2006.201.03:21:26.04#ibcon#about to read 4, iclass 12, count 0 2006.201.03:21:26.04#ibcon#read 4, iclass 12, count 0 2006.201.03:21:26.04#ibcon#about to read 5, iclass 12, count 0 2006.201.03:21:26.04#ibcon#read 5, iclass 12, count 0 2006.201.03:21:26.04#ibcon#about to read 6, iclass 12, count 0 2006.201.03:21:26.04#ibcon#read 6, iclass 12, count 0 2006.201.03:21:26.04#ibcon#end of sib2, iclass 12, count 0 2006.201.03:21:26.04#ibcon#*after write, iclass 12, count 0 2006.201.03:21:26.04#ibcon#*before return 0, iclass 12, count 0 2006.201.03:21:26.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:26.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:21:26.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:21:26.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:21:26.04$vck44/vb=8,4 2006.201.03:21:26.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.03:21:26.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.03:21:26.04#ibcon#ireg 11 cls_cnt 2 2006.201.03:21:26.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:26.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:26.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:26.10#ibcon#enter wrdev, iclass 14, count 2 2006.201.03:21:26.10#ibcon#first serial, iclass 14, count 2 2006.201.03:21:26.10#ibcon#enter sib2, iclass 14, count 2 2006.201.03:21:26.10#ibcon#flushed, iclass 14, count 2 2006.201.03:21:26.10#ibcon#about to write, iclass 14, count 2 2006.201.03:21:26.10#ibcon#wrote, iclass 14, count 2 2006.201.03:21:26.10#ibcon#about to read 3, iclass 14, count 2 2006.201.03:21:26.12#ibcon#read 3, iclass 14, count 2 2006.201.03:21:26.12#ibcon#about to read 4, iclass 14, count 2 2006.201.03:21:26.12#ibcon#read 4, iclass 14, count 2 2006.201.03:21:26.12#ibcon#about to read 5, iclass 14, count 2 2006.201.03:21:26.12#ibcon#read 5, iclass 14, count 2 2006.201.03:21:26.12#ibcon#about to read 6, iclass 14, count 2 2006.201.03:21:26.12#ibcon#read 6, iclass 14, count 2 2006.201.03:21:26.12#ibcon#end of sib2, iclass 14, count 2 2006.201.03:21:26.12#ibcon#*mode == 0, iclass 14, count 2 2006.201.03:21:26.12#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.03:21:26.12#ibcon#[27=AT08-04\r\n] 2006.201.03:21:26.12#ibcon#*before write, iclass 14, count 2 2006.201.03:21:26.12#ibcon#enter sib2, iclass 14, count 2 2006.201.03:21:26.12#ibcon#flushed, iclass 14, count 2 2006.201.03:21:26.12#ibcon#about to write, iclass 14, count 2 2006.201.03:21:26.12#ibcon#wrote, iclass 14, count 2 2006.201.03:21:26.12#ibcon#about to read 3, iclass 14, count 2 2006.201.03:21:26.15#ibcon#read 3, iclass 14, count 2 2006.201.03:21:26.15#ibcon#about to read 4, iclass 14, count 2 2006.201.03:21:26.15#ibcon#read 4, iclass 14, count 2 2006.201.03:21:26.15#ibcon#about to read 5, iclass 14, count 2 2006.201.03:21:26.15#ibcon#read 5, iclass 14, count 2 2006.201.03:21:26.15#ibcon#about to read 6, iclass 14, count 2 2006.201.03:21:26.15#ibcon#read 6, iclass 14, count 2 2006.201.03:21:26.15#ibcon#end of sib2, iclass 14, count 2 2006.201.03:21:26.15#ibcon#*after write, iclass 14, count 2 2006.201.03:21:26.15#ibcon#*before return 0, iclass 14, count 2 2006.201.03:21:26.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:26.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:21:26.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.03:21:26.15#ibcon#ireg 7 cls_cnt 0 2006.201.03:21:26.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:26.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:26.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:26.27#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:21:26.27#ibcon#first serial, iclass 14, count 0 2006.201.03:21:26.27#ibcon#enter sib2, iclass 14, count 0 2006.201.03:21:26.27#ibcon#flushed, iclass 14, count 0 2006.201.03:21:26.27#ibcon#about to write, iclass 14, count 0 2006.201.03:21:26.27#ibcon#wrote, iclass 14, count 0 2006.201.03:21:26.27#ibcon#about to read 3, iclass 14, count 0 2006.201.03:21:26.29#ibcon#read 3, iclass 14, count 0 2006.201.03:21:26.29#ibcon#about to read 4, iclass 14, count 0 2006.201.03:21:26.29#ibcon#read 4, iclass 14, count 0 2006.201.03:21:26.29#ibcon#about to read 5, iclass 14, count 0 2006.201.03:21:26.29#ibcon#read 5, iclass 14, count 0 2006.201.03:21:26.29#ibcon#about to read 6, iclass 14, count 0 2006.201.03:21:26.29#ibcon#read 6, iclass 14, count 0 2006.201.03:21:26.29#ibcon#end of sib2, iclass 14, count 0 2006.201.03:21:26.29#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:21:26.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:21:26.29#ibcon#[27=USB\r\n] 2006.201.03:21:26.29#ibcon#*before write, iclass 14, count 0 2006.201.03:21:26.29#ibcon#enter sib2, iclass 14, count 0 2006.201.03:21:26.29#ibcon#flushed, iclass 14, count 0 2006.201.03:21:26.29#ibcon#about to write, iclass 14, count 0 2006.201.03:21:26.29#ibcon#wrote, iclass 14, count 0 2006.201.03:21:26.29#ibcon#about to read 3, iclass 14, count 0 2006.201.03:21:26.32#ibcon#read 3, iclass 14, count 0 2006.201.03:21:26.32#ibcon#about to read 4, iclass 14, count 0 2006.201.03:21:26.32#ibcon#read 4, iclass 14, count 0 2006.201.03:21:26.32#ibcon#about to read 5, iclass 14, count 0 2006.201.03:21:26.32#ibcon#read 5, iclass 14, count 0 2006.201.03:21:26.32#ibcon#about to read 6, iclass 14, count 0 2006.201.03:21:26.32#ibcon#read 6, iclass 14, count 0 2006.201.03:21:26.32#ibcon#end of sib2, iclass 14, count 0 2006.201.03:21:26.32#ibcon#*after write, iclass 14, count 0 2006.201.03:21:26.32#ibcon#*before return 0, iclass 14, count 0 2006.201.03:21:26.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:26.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:21:26.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:21:26.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:21:26.32$vck44/vabw=wide 2006.201.03:21:26.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.03:21:26.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.03:21:26.32#ibcon#ireg 8 cls_cnt 0 2006.201.03:21:26.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:26.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:26.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:26.32#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:21:26.32#ibcon#first serial, iclass 16, count 0 2006.201.03:21:26.32#ibcon#enter sib2, iclass 16, count 0 2006.201.03:21:26.32#ibcon#flushed, iclass 16, count 0 2006.201.03:21:26.32#ibcon#about to write, iclass 16, count 0 2006.201.03:21:26.32#ibcon#wrote, iclass 16, count 0 2006.201.03:21:26.32#ibcon#about to read 3, iclass 16, count 0 2006.201.03:21:26.34#ibcon#read 3, iclass 16, count 0 2006.201.03:21:26.34#ibcon#about to read 4, iclass 16, count 0 2006.201.03:21:26.34#ibcon#read 4, iclass 16, count 0 2006.201.03:21:26.34#ibcon#about to read 5, iclass 16, count 0 2006.201.03:21:26.34#ibcon#read 5, iclass 16, count 0 2006.201.03:21:26.34#ibcon#about to read 6, iclass 16, count 0 2006.201.03:21:26.34#ibcon#read 6, iclass 16, count 0 2006.201.03:21:26.34#ibcon#end of sib2, iclass 16, count 0 2006.201.03:21:26.34#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:21:26.34#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:21:26.34#ibcon#[25=BW32\r\n] 2006.201.03:21:26.34#ibcon#*before write, iclass 16, count 0 2006.201.03:21:26.34#ibcon#enter sib2, iclass 16, count 0 2006.201.03:21:26.34#ibcon#flushed, iclass 16, count 0 2006.201.03:21:26.34#ibcon#about to write, iclass 16, count 0 2006.201.03:21:26.34#ibcon#wrote, iclass 16, count 0 2006.201.03:21:26.34#ibcon#about to read 3, iclass 16, count 0 2006.201.03:21:26.37#ibcon#read 3, iclass 16, count 0 2006.201.03:21:26.37#ibcon#about to read 4, iclass 16, count 0 2006.201.03:21:26.37#ibcon#read 4, iclass 16, count 0 2006.201.03:21:26.37#ibcon#about to read 5, iclass 16, count 0 2006.201.03:21:26.37#ibcon#read 5, iclass 16, count 0 2006.201.03:21:26.37#ibcon#about to read 6, iclass 16, count 0 2006.201.03:21:26.37#ibcon#read 6, iclass 16, count 0 2006.201.03:21:26.37#ibcon#end of sib2, iclass 16, count 0 2006.201.03:21:26.37#ibcon#*after write, iclass 16, count 0 2006.201.03:21:26.37#ibcon#*before return 0, iclass 16, count 0 2006.201.03:21:26.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:26.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:21:26.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:21:26.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:21:26.37$vck44/vbbw=wide 2006.201.03:21:26.37#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.03:21:26.37#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.03:21:26.37#ibcon#ireg 8 cls_cnt 0 2006.201.03:21:26.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:21:26.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:21:26.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:21:26.44#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:21:26.44#ibcon#first serial, iclass 18, count 0 2006.201.03:21:26.44#ibcon#enter sib2, iclass 18, count 0 2006.201.03:21:26.44#ibcon#flushed, iclass 18, count 0 2006.201.03:21:26.44#ibcon#about to write, iclass 18, count 0 2006.201.03:21:26.44#ibcon#wrote, iclass 18, count 0 2006.201.03:21:26.44#ibcon#about to read 3, iclass 18, count 0 2006.201.03:21:26.46#ibcon#read 3, iclass 18, count 0 2006.201.03:21:26.46#ibcon#about to read 4, iclass 18, count 0 2006.201.03:21:26.46#ibcon#read 4, iclass 18, count 0 2006.201.03:21:26.46#ibcon#about to read 5, iclass 18, count 0 2006.201.03:21:26.46#ibcon#read 5, iclass 18, count 0 2006.201.03:21:26.46#ibcon#about to read 6, iclass 18, count 0 2006.201.03:21:26.46#ibcon#read 6, iclass 18, count 0 2006.201.03:21:26.46#ibcon#end of sib2, iclass 18, count 0 2006.201.03:21:26.46#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:21:26.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:21:26.46#ibcon#[27=BW32\r\n] 2006.201.03:21:26.46#ibcon#*before write, iclass 18, count 0 2006.201.03:21:26.46#ibcon#enter sib2, iclass 18, count 0 2006.201.03:21:26.46#ibcon#flushed, iclass 18, count 0 2006.201.03:21:26.46#ibcon#about to write, iclass 18, count 0 2006.201.03:21:26.46#ibcon#wrote, iclass 18, count 0 2006.201.03:21:26.46#ibcon#about to read 3, iclass 18, count 0 2006.201.03:21:26.49#ibcon#read 3, iclass 18, count 0 2006.201.03:21:26.49#ibcon#about to read 4, iclass 18, count 0 2006.201.03:21:26.49#ibcon#read 4, iclass 18, count 0 2006.201.03:21:26.49#ibcon#about to read 5, iclass 18, count 0 2006.201.03:21:26.49#ibcon#read 5, iclass 18, count 0 2006.201.03:21:26.49#ibcon#about to read 6, iclass 18, count 0 2006.201.03:21:26.49#ibcon#read 6, iclass 18, count 0 2006.201.03:21:26.49#ibcon#end of sib2, iclass 18, count 0 2006.201.03:21:26.49#ibcon#*after write, iclass 18, count 0 2006.201.03:21:26.49#ibcon#*before return 0, iclass 18, count 0 2006.201.03:21:26.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:21:26.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:21:26.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:21:26.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:21:26.49$setupk4/ifdk4 2006.201.03:21:26.49$ifdk4/lo= 2006.201.03:21:26.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:21:26.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:21:26.49$ifdk4/patch= 2006.201.03:21:26.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:21:26.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:21:26.49$setupk4/!*+20s 2006.201.03:21:29.73#abcon#<5=/03 2.4 5.1 22.90 921004.3\r\n> 2006.201.03:21:29.75#abcon#{5=INTERFACE CLEAR} 2006.201.03:21:29.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:21:39.91#abcon#<5=/03 2.3 5.1 22.91 921004.4\r\n> 2006.201.03:21:39.93#abcon#{5=INTERFACE CLEAR} 2006.201.03:21:40.01#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:21:40.98$setupk4/"tpicd 2006.201.03:21:40.98$setupk4/echo=off 2006.201.03:21:40.98$setupk4/xlog=off 2006.201.03:21:40.98:!2006.201.03:28:22 2006.201.03:21:41.14#trakl#Source acquired 2006.201.03:21:41.14#flagr#flagr/antenna,acquired 2006.201.03:28:22.00:preob 2006.201.03:28:22.14/onsource/TRACKING 2006.201.03:28:22.14:!2006.201.03:28:32 2006.201.03:28:32.00:"tape 2006.201.03:28:32.00:"st=record 2006.201.03:28:32.00:data_valid=on 2006.201.03:28:32.00:midob 2006.201.03:28:32.14/onsource/TRACKING 2006.201.03:28:32.14/wx/23.02,1004.4,91 2006.201.03:28:32.28/cable/+6.4654E-03 2006.201.03:28:33.37/va/01,08,usb,yes,28,30 2006.201.03:28:33.37/va/02,07,usb,yes,30,31 2006.201.03:28:33.37/va/03,08,usb,yes,27,28 2006.201.03:28:33.37/va/04,07,usb,yes,31,33 2006.201.03:28:33.37/va/05,04,usb,yes,28,28 2006.201.03:28:33.37/va/06,05,usb,yes,28,27 2006.201.03:28:33.37/va/07,05,usb,yes,27,28 2006.201.03:28:33.37/va/08,04,usb,yes,26,32 2006.201.03:28:33.60/valo/01,524.99,yes,locked 2006.201.03:28:33.60/valo/02,534.99,yes,locked 2006.201.03:28:33.60/valo/03,564.99,yes,locked 2006.201.03:28:33.60/valo/04,624.99,yes,locked 2006.201.03:28:33.60/valo/05,734.99,yes,locked 2006.201.03:28:33.60/valo/06,814.99,yes,locked 2006.201.03:28:33.60/valo/07,864.99,yes,locked 2006.201.03:28:33.60/valo/08,884.99,yes,locked 2006.201.03:28:34.69/vb/01,04,usb,yes,29,27 2006.201.03:28:34.69/vb/02,05,usb,yes,27,27 2006.201.03:28:34.69/vb/03,04,usb,yes,28,31 2006.201.03:28:34.69/vb/04,05,usb,yes,28,27 2006.201.03:28:34.69/vb/05,04,usb,yes,25,27 2006.201.03:28:34.69/vb/06,04,usb,yes,29,26 2006.201.03:28:34.69/vb/07,04,usb,yes,29,29 2006.201.03:28:34.69/vb/08,04,usb,yes,27,30 2006.201.03:28:34.93/vblo/01,629.99,yes,locked 2006.201.03:28:34.93/vblo/02,634.99,yes,locked 2006.201.03:28:34.93/vblo/03,649.99,yes,locked 2006.201.03:28:34.93/vblo/04,679.99,yes,locked 2006.201.03:28:34.93/vblo/05,709.99,yes,locked 2006.201.03:28:34.93/vblo/06,719.99,yes,locked 2006.201.03:28:34.93/vblo/07,734.99,yes,locked 2006.201.03:28:34.93/vblo/08,744.99,yes,locked 2006.201.03:28:35.08/vabw/8 2006.201.03:28:35.23/vbbw/8 2006.201.03:28:35.32/xfe/off,on,15.2 2006.201.03:28:35.70/ifatt/23,28,28,28 2006.201.03:28:36.04/fmout-gps/S +4.49E-07 2006.201.03:28:36.11:!2006.201.03:29:12 2006.201.03:29:12.00:data_valid=off 2006.201.03:29:12.00:"et 2006.201.03:29:12.00:!+3s 2006.201.03:29:15.02:"tape 2006.201.03:29:15.02:postob 2006.201.03:29:15.24/cable/+6.4648E-03 2006.201.03:29:15.24/wx/23.02,1004.4,91 2006.201.03:29:15.32/fmout-gps/S +4.47E-07 2006.201.03:29:15.32:scan_name=201-0330,jd0607,100 2006.201.03:29:15.32:source=3c274,123049.42,122328.0,2000.0,cw 2006.201.03:29:17.14#flagr#flagr/antenna,new-source 2006.201.03:29:17.14:checkk5 2006.201.03:29:17.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:29:17.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:29:18.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:29:18.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:29:19.03/chk_obsdata//k5ts1/T2010328??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.03:29:19.40/chk_obsdata//k5ts2/T2010328??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.03:29:19.77/chk_obsdata//k5ts3/T2010328??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.03:29:20.14/chk_obsdata//k5ts4/T2010328??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.03:29:20.82/k5log//k5ts1_log_newline 2006.201.03:29:21.53/k5log//k5ts2_log_newline 2006.201.03:29:22.22/k5log//k5ts3_log_newline 2006.201.03:29:22.90/k5log//k5ts4_log_newline 2006.201.03:29:22.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:29:22.93:setupk4=1 2006.201.03:29:22.93$setupk4/echo=on 2006.201.03:29:22.93$setupk4/pcalon 2006.201.03:29:22.93$pcalon/"no phase cal control is implemented here 2006.201.03:29:22.93$setupk4/"tpicd=stop 2006.201.03:29:22.93$setupk4/"rec=synch_on 2006.201.03:29:22.93$setupk4/"rec_mode=128 2006.201.03:29:22.93$setupk4/!* 2006.201.03:29:22.93$setupk4/recpk4 2006.201.03:29:22.93$recpk4/recpatch= 2006.201.03:29:22.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:29:22.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:29:22.93$setupk4/vck44 2006.201.03:29:22.93$vck44/valo=1,524.99 2006.201.03:29:22.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.03:29:22.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.03:29:22.93#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:22.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:22.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:22.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:22.93#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:29:22.93#ibcon#first serial, iclass 26, count 0 2006.201.03:29:22.93#ibcon#enter sib2, iclass 26, count 0 2006.201.03:29:22.93#ibcon#flushed, iclass 26, count 0 2006.201.03:29:22.93#ibcon#about to write, iclass 26, count 0 2006.201.03:29:22.93#ibcon#wrote, iclass 26, count 0 2006.201.03:29:22.93#ibcon#about to read 3, iclass 26, count 0 2006.201.03:29:22.98#ibcon#read 3, iclass 26, count 0 2006.201.03:29:22.98#ibcon#about to read 4, iclass 26, count 0 2006.201.03:29:22.98#ibcon#read 4, iclass 26, count 0 2006.201.03:29:22.98#ibcon#about to read 5, iclass 26, count 0 2006.201.03:29:22.98#ibcon#read 5, iclass 26, count 0 2006.201.03:29:22.98#ibcon#about to read 6, iclass 26, count 0 2006.201.03:29:22.98#ibcon#read 6, iclass 26, count 0 2006.201.03:29:22.98#ibcon#end of sib2, iclass 26, count 0 2006.201.03:29:22.98#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:29:22.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:29:22.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:29:22.98#ibcon#*before write, iclass 26, count 0 2006.201.03:29:22.98#ibcon#enter sib2, iclass 26, count 0 2006.201.03:29:22.98#ibcon#flushed, iclass 26, count 0 2006.201.03:29:22.98#ibcon#about to write, iclass 26, count 0 2006.201.03:29:22.98#ibcon#wrote, iclass 26, count 0 2006.201.03:29:22.98#ibcon#about to read 3, iclass 26, count 0 2006.201.03:29:23.03#ibcon#read 3, iclass 26, count 0 2006.201.03:29:23.03#ibcon#about to read 4, iclass 26, count 0 2006.201.03:29:23.03#ibcon#read 4, iclass 26, count 0 2006.201.03:29:23.03#ibcon#about to read 5, iclass 26, count 0 2006.201.03:29:23.03#ibcon#read 5, iclass 26, count 0 2006.201.03:29:23.03#ibcon#about to read 6, iclass 26, count 0 2006.201.03:29:23.03#ibcon#read 6, iclass 26, count 0 2006.201.03:29:23.03#ibcon#end of sib2, iclass 26, count 0 2006.201.03:29:23.03#ibcon#*after write, iclass 26, count 0 2006.201.03:29:23.03#ibcon#*before return 0, iclass 26, count 0 2006.201.03:29:23.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:23.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:23.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:29:23.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:29:23.03$vck44/va=1,8 2006.201.03:29:23.03#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.03:29:23.03#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.03:29:23.03#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:23.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:23.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:23.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:23.03#ibcon#enter wrdev, iclass 28, count 2 2006.201.03:29:23.03#ibcon#first serial, iclass 28, count 2 2006.201.03:29:23.03#ibcon#enter sib2, iclass 28, count 2 2006.201.03:29:23.03#ibcon#flushed, iclass 28, count 2 2006.201.03:29:23.03#ibcon#about to write, iclass 28, count 2 2006.201.03:29:23.03#ibcon#wrote, iclass 28, count 2 2006.201.03:29:23.03#ibcon#about to read 3, iclass 28, count 2 2006.201.03:29:23.05#ibcon#read 3, iclass 28, count 2 2006.201.03:29:23.05#ibcon#about to read 4, iclass 28, count 2 2006.201.03:29:23.05#ibcon#read 4, iclass 28, count 2 2006.201.03:29:23.05#ibcon#about to read 5, iclass 28, count 2 2006.201.03:29:23.05#ibcon#read 5, iclass 28, count 2 2006.201.03:29:23.05#ibcon#about to read 6, iclass 28, count 2 2006.201.03:29:23.05#ibcon#read 6, iclass 28, count 2 2006.201.03:29:23.05#ibcon#end of sib2, iclass 28, count 2 2006.201.03:29:23.05#ibcon#*mode == 0, iclass 28, count 2 2006.201.03:29:23.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.03:29:23.05#ibcon#[25=AT01-08\r\n] 2006.201.03:29:23.05#ibcon#*before write, iclass 28, count 2 2006.201.03:29:23.05#ibcon#enter sib2, iclass 28, count 2 2006.201.03:29:23.05#ibcon#flushed, iclass 28, count 2 2006.201.03:29:23.05#ibcon#about to write, iclass 28, count 2 2006.201.03:29:23.05#ibcon#wrote, iclass 28, count 2 2006.201.03:29:23.05#ibcon#about to read 3, iclass 28, count 2 2006.201.03:29:23.09#ibcon#read 3, iclass 28, count 2 2006.201.03:29:23.09#ibcon#about to read 4, iclass 28, count 2 2006.201.03:29:23.09#ibcon#read 4, iclass 28, count 2 2006.201.03:29:23.09#ibcon#about to read 5, iclass 28, count 2 2006.201.03:29:23.09#ibcon#read 5, iclass 28, count 2 2006.201.03:29:23.09#ibcon#about to read 6, iclass 28, count 2 2006.201.03:29:23.09#ibcon#read 6, iclass 28, count 2 2006.201.03:29:23.09#ibcon#end of sib2, iclass 28, count 2 2006.201.03:29:23.09#ibcon#*after write, iclass 28, count 2 2006.201.03:29:23.09#ibcon#*before return 0, iclass 28, count 2 2006.201.03:29:23.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:23.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:23.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.03:29:23.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:23.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:23.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:23.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:23.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:29:23.21#ibcon#first serial, iclass 28, count 0 2006.201.03:29:23.21#ibcon#enter sib2, iclass 28, count 0 2006.201.03:29:23.21#ibcon#flushed, iclass 28, count 0 2006.201.03:29:23.21#ibcon#about to write, iclass 28, count 0 2006.201.03:29:23.21#ibcon#wrote, iclass 28, count 0 2006.201.03:29:23.21#ibcon#about to read 3, iclass 28, count 0 2006.201.03:29:23.23#ibcon#read 3, iclass 28, count 0 2006.201.03:29:23.23#ibcon#about to read 4, iclass 28, count 0 2006.201.03:29:23.23#ibcon#read 4, iclass 28, count 0 2006.201.03:29:23.23#ibcon#about to read 5, iclass 28, count 0 2006.201.03:29:23.23#ibcon#read 5, iclass 28, count 0 2006.201.03:29:23.23#ibcon#about to read 6, iclass 28, count 0 2006.201.03:29:23.23#ibcon#read 6, iclass 28, count 0 2006.201.03:29:23.23#ibcon#end of sib2, iclass 28, count 0 2006.201.03:29:23.23#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:29:23.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:29:23.23#ibcon#[25=USB\r\n] 2006.201.03:29:23.23#ibcon#*before write, iclass 28, count 0 2006.201.03:29:23.23#ibcon#enter sib2, iclass 28, count 0 2006.201.03:29:23.23#ibcon#flushed, iclass 28, count 0 2006.201.03:29:23.23#ibcon#about to write, iclass 28, count 0 2006.201.03:29:23.23#ibcon#wrote, iclass 28, count 0 2006.201.03:29:23.23#ibcon#about to read 3, iclass 28, count 0 2006.201.03:29:23.26#ibcon#read 3, iclass 28, count 0 2006.201.03:29:23.26#ibcon#about to read 4, iclass 28, count 0 2006.201.03:29:23.26#ibcon#read 4, iclass 28, count 0 2006.201.03:29:23.26#ibcon#about to read 5, iclass 28, count 0 2006.201.03:29:23.26#ibcon#read 5, iclass 28, count 0 2006.201.03:29:23.26#ibcon#about to read 6, iclass 28, count 0 2006.201.03:29:23.26#ibcon#read 6, iclass 28, count 0 2006.201.03:29:23.26#ibcon#end of sib2, iclass 28, count 0 2006.201.03:29:23.26#ibcon#*after write, iclass 28, count 0 2006.201.03:29:23.26#ibcon#*before return 0, iclass 28, count 0 2006.201.03:29:23.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:23.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:23.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:29:23.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:29:23.26$vck44/valo=2,534.99 2006.201.03:29:23.26#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.03:29:23.26#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.03:29:23.26#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:23.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:23.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:23.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:23.26#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:29:23.26#ibcon#first serial, iclass 30, count 0 2006.201.03:29:23.26#ibcon#enter sib2, iclass 30, count 0 2006.201.03:29:23.26#ibcon#flushed, iclass 30, count 0 2006.201.03:29:23.26#ibcon#about to write, iclass 30, count 0 2006.201.03:29:23.26#ibcon#wrote, iclass 30, count 0 2006.201.03:29:23.26#ibcon#about to read 3, iclass 30, count 0 2006.201.03:29:23.28#ibcon#read 3, iclass 30, count 0 2006.201.03:29:23.28#ibcon#about to read 4, iclass 30, count 0 2006.201.03:29:23.28#ibcon#read 4, iclass 30, count 0 2006.201.03:29:23.28#ibcon#about to read 5, iclass 30, count 0 2006.201.03:29:23.28#ibcon#read 5, iclass 30, count 0 2006.201.03:29:23.28#ibcon#about to read 6, iclass 30, count 0 2006.201.03:29:23.28#ibcon#read 6, iclass 30, count 0 2006.201.03:29:23.28#ibcon#end of sib2, iclass 30, count 0 2006.201.03:29:23.28#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:29:23.28#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:29:23.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:29:23.28#ibcon#*before write, iclass 30, count 0 2006.201.03:29:23.28#ibcon#enter sib2, iclass 30, count 0 2006.201.03:29:23.28#ibcon#flushed, iclass 30, count 0 2006.201.03:29:23.28#ibcon#about to write, iclass 30, count 0 2006.201.03:29:23.28#ibcon#wrote, iclass 30, count 0 2006.201.03:29:23.28#ibcon#about to read 3, iclass 30, count 0 2006.201.03:29:23.32#ibcon#read 3, iclass 30, count 0 2006.201.03:29:23.32#ibcon#about to read 4, iclass 30, count 0 2006.201.03:29:23.32#ibcon#read 4, iclass 30, count 0 2006.201.03:29:23.32#ibcon#about to read 5, iclass 30, count 0 2006.201.03:29:23.32#ibcon#read 5, iclass 30, count 0 2006.201.03:29:23.32#ibcon#about to read 6, iclass 30, count 0 2006.201.03:29:23.32#ibcon#read 6, iclass 30, count 0 2006.201.03:29:23.32#ibcon#end of sib2, iclass 30, count 0 2006.201.03:29:23.32#ibcon#*after write, iclass 30, count 0 2006.201.03:29:23.32#ibcon#*before return 0, iclass 30, count 0 2006.201.03:29:23.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:23.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:23.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:29:23.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:29:23.32$vck44/va=2,7 2006.201.03:29:23.32#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.03:29:23.32#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.03:29:23.32#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:23.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:23.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:23.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:23.38#ibcon#enter wrdev, iclass 32, count 2 2006.201.03:29:23.38#ibcon#first serial, iclass 32, count 2 2006.201.03:29:23.38#ibcon#enter sib2, iclass 32, count 2 2006.201.03:29:23.38#ibcon#flushed, iclass 32, count 2 2006.201.03:29:23.38#ibcon#about to write, iclass 32, count 2 2006.201.03:29:23.38#ibcon#wrote, iclass 32, count 2 2006.201.03:29:23.38#ibcon#about to read 3, iclass 32, count 2 2006.201.03:29:23.40#ibcon#read 3, iclass 32, count 2 2006.201.03:29:23.40#ibcon#about to read 4, iclass 32, count 2 2006.201.03:29:23.40#ibcon#read 4, iclass 32, count 2 2006.201.03:29:23.40#ibcon#about to read 5, iclass 32, count 2 2006.201.03:29:23.40#ibcon#read 5, iclass 32, count 2 2006.201.03:29:23.40#ibcon#about to read 6, iclass 32, count 2 2006.201.03:29:23.40#ibcon#read 6, iclass 32, count 2 2006.201.03:29:23.40#ibcon#end of sib2, iclass 32, count 2 2006.201.03:29:23.40#ibcon#*mode == 0, iclass 32, count 2 2006.201.03:29:23.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.03:29:23.40#ibcon#[25=AT02-07\r\n] 2006.201.03:29:23.40#ibcon#*before write, iclass 32, count 2 2006.201.03:29:23.40#ibcon#enter sib2, iclass 32, count 2 2006.201.03:29:23.40#ibcon#flushed, iclass 32, count 2 2006.201.03:29:23.40#ibcon#about to write, iclass 32, count 2 2006.201.03:29:23.40#ibcon#wrote, iclass 32, count 2 2006.201.03:29:23.40#ibcon#about to read 3, iclass 32, count 2 2006.201.03:29:23.43#ibcon#read 3, iclass 32, count 2 2006.201.03:29:23.43#ibcon#about to read 4, iclass 32, count 2 2006.201.03:29:23.43#ibcon#read 4, iclass 32, count 2 2006.201.03:29:23.43#ibcon#about to read 5, iclass 32, count 2 2006.201.03:29:23.43#ibcon#read 5, iclass 32, count 2 2006.201.03:29:23.43#ibcon#about to read 6, iclass 32, count 2 2006.201.03:29:23.43#ibcon#read 6, iclass 32, count 2 2006.201.03:29:23.43#ibcon#end of sib2, iclass 32, count 2 2006.201.03:29:23.43#ibcon#*after write, iclass 32, count 2 2006.201.03:29:23.43#ibcon#*before return 0, iclass 32, count 2 2006.201.03:29:23.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:23.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:23.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.03:29:23.43#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:23.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:23.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:23.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:23.55#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:29:23.55#ibcon#first serial, iclass 32, count 0 2006.201.03:29:23.55#ibcon#enter sib2, iclass 32, count 0 2006.201.03:29:23.55#ibcon#flushed, iclass 32, count 0 2006.201.03:29:23.55#ibcon#about to write, iclass 32, count 0 2006.201.03:29:23.55#ibcon#wrote, iclass 32, count 0 2006.201.03:29:23.55#ibcon#about to read 3, iclass 32, count 0 2006.201.03:29:23.57#ibcon#read 3, iclass 32, count 0 2006.201.03:29:23.57#ibcon#about to read 4, iclass 32, count 0 2006.201.03:29:23.57#ibcon#read 4, iclass 32, count 0 2006.201.03:29:23.57#ibcon#about to read 5, iclass 32, count 0 2006.201.03:29:23.57#ibcon#read 5, iclass 32, count 0 2006.201.03:29:23.57#ibcon#about to read 6, iclass 32, count 0 2006.201.03:29:23.57#ibcon#read 6, iclass 32, count 0 2006.201.03:29:23.57#ibcon#end of sib2, iclass 32, count 0 2006.201.03:29:23.57#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:29:23.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:29:23.57#ibcon#[25=USB\r\n] 2006.201.03:29:23.57#ibcon#*before write, iclass 32, count 0 2006.201.03:29:23.57#ibcon#enter sib2, iclass 32, count 0 2006.201.03:29:23.57#ibcon#flushed, iclass 32, count 0 2006.201.03:29:23.57#ibcon#about to write, iclass 32, count 0 2006.201.03:29:23.57#ibcon#wrote, iclass 32, count 0 2006.201.03:29:23.57#ibcon#about to read 3, iclass 32, count 0 2006.201.03:29:23.60#ibcon#read 3, iclass 32, count 0 2006.201.03:29:23.60#ibcon#about to read 4, iclass 32, count 0 2006.201.03:29:23.60#ibcon#read 4, iclass 32, count 0 2006.201.03:29:23.60#ibcon#about to read 5, iclass 32, count 0 2006.201.03:29:23.60#ibcon#read 5, iclass 32, count 0 2006.201.03:29:23.60#ibcon#about to read 6, iclass 32, count 0 2006.201.03:29:23.60#ibcon#read 6, iclass 32, count 0 2006.201.03:29:23.60#ibcon#end of sib2, iclass 32, count 0 2006.201.03:29:23.60#ibcon#*after write, iclass 32, count 0 2006.201.03:29:23.60#ibcon#*before return 0, iclass 32, count 0 2006.201.03:29:23.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:23.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:23.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:29:23.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:29:23.60$vck44/valo=3,564.99 2006.201.03:29:23.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.03:29:23.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.03:29:23.60#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:23.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:23.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:23.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:23.60#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:29:23.60#ibcon#first serial, iclass 34, count 0 2006.201.03:29:23.60#ibcon#enter sib2, iclass 34, count 0 2006.201.03:29:23.60#ibcon#flushed, iclass 34, count 0 2006.201.03:29:23.60#ibcon#about to write, iclass 34, count 0 2006.201.03:29:23.60#ibcon#wrote, iclass 34, count 0 2006.201.03:29:23.60#ibcon#about to read 3, iclass 34, count 0 2006.201.03:29:23.62#ibcon#read 3, iclass 34, count 0 2006.201.03:29:23.62#ibcon#about to read 4, iclass 34, count 0 2006.201.03:29:23.62#ibcon#read 4, iclass 34, count 0 2006.201.03:29:23.62#ibcon#about to read 5, iclass 34, count 0 2006.201.03:29:23.62#ibcon#read 5, iclass 34, count 0 2006.201.03:29:23.62#ibcon#about to read 6, iclass 34, count 0 2006.201.03:29:23.62#ibcon#read 6, iclass 34, count 0 2006.201.03:29:23.62#ibcon#end of sib2, iclass 34, count 0 2006.201.03:29:23.62#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:29:23.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:29:23.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:29:23.62#ibcon#*before write, iclass 34, count 0 2006.201.03:29:23.62#ibcon#enter sib2, iclass 34, count 0 2006.201.03:29:23.62#ibcon#flushed, iclass 34, count 0 2006.201.03:29:23.62#ibcon#about to write, iclass 34, count 0 2006.201.03:29:23.62#ibcon#wrote, iclass 34, count 0 2006.201.03:29:23.62#ibcon#about to read 3, iclass 34, count 0 2006.201.03:29:23.67#ibcon#read 3, iclass 34, count 0 2006.201.03:29:23.67#ibcon#about to read 4, iclass 34, count 0 2006.201.03:29:23.67#ibcon#read 4, iclass 34, count 0 2006.201.03:29:23.67#ibcon#about to read 5, iclass 34, count 0 2006.201.03:29:23.67#ibcon#read 5, iclass 34, count 0 2006.201.03:29:23.67#ibcon#about to read 6, iclass 34, count 0 2006.201.03:29:23.67#ibcon#read 6, iclass 34, count 0 2006.201.03:29:23.67#ibcon#end of sib2, iclass 34, count 0 2006.201.03:29:23.67#ibcon#*after write, iclass 34, count 0 2006.201.03:29:23.67#ibcon#*before return 0, iclass 34, count 0 2006.201.03:29:23.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:23.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:23.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:29:23.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:29:23.67$vck44/va=3,8 2006.201.03:29:23.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.03:29:23.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.03:29:23.67#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:23.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:23.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:23.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:23.72#ibcon#enter wrdev, iclass 36, count 2 2006.201.03:29:23.72#ibcon#first serial, iclass 36, count 2 2006.201.03:29:23.72#ibcon#enter sib2, iclass 36, count 2 2006.201.03:29:23.72#ibcon#flushed, iclass 36, count 2 2006.201.03:29:23.72#ibcon#about to write, iclass 36, count 2 2006.201.03:29:23.72#ibcon#wrote, iclass 36, count 2 2006.201.03:29:23.72#ibcon#about to read 3, iclass 36, count 2 2006.201.03:29:23.74#ibcon#read 3, iclass 36, count 2 2006.201.03:29:23.74#ibcon#about to read 4, iclass 36, count 2 2006.201.03:29:23.74#ibcon#read 4, iclass 36, count 2 2006.201.03:29:23.74#ibcon#about to read 5, iclass 36, count 2 2006.201.03:29:23.74#ibcon#read 5, iclass 36, count 2 2006.201.03:29:23.74#ibcon#about to read 6, iclass 36, count 2 2006.201.03:29:23.74#ibcon#read 6, iclass 36, count 2 2006.201.03:29:23.74#ibcon#end of sib2, iclass 36, count 2 2006.201.03:29:23.74#ibcon#*mode == 0, iclass 36, count 2 2006.201.03:29:23.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.03:29:23.74#ibcon#[25=AT03-08\r\n] 2006.201.03:29:23.74#ibcon#*before write, iclass 36, count 2 2006.201.03:29:23.74#ibcon#enter sib2, iclass 36, count 2 2006.201.03:29:23.74#ibcon#flushed, iclass 36, count 2 2006.201.03:29:23.74#ibcon#about to write, iclass 36, count 2 2006.201.03:29:23.74#ibcon#wrote, iclass 36, count 2 2006.201.03:29:23.74#ibcon#about to read 3, iclass 36, count 2 2006.201.03:29:23.77#ibcon#read 3, iclass 36, count 2 2006.201.03:29:23.77#ibcon#about to read 4, iclass 36, count 2 2006.201.03:29:23.77#ibcon#read 4, iclass 36, count 2 2006.201.03:29:23.77#ibcon#about to read 5, iclass 36, count 2 2006.201.03:29:23.77#ibcon#read 5, iclass 36, count 2 2006.201.03:29:23.77#ibcon#about to read 6, iclass 36, count 2 2006.201.03:29:23.77#ibcon#read 6, iclass 36, count 2 2006.201.03:29:23.77#ibcon#end of sib2, iclass 36, count 2 2006.201.03:29:23.77#ibcon#*after write, iclass 36, count 2 2006.201.03:29:23.77#ibcon#*before return 0, iclass 36, count 2 2006.201.03:29:23.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:23.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:23.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.03:29:23.77#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:23.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:23.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:23.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:23.89#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:29:23.89#ibcon#first serial, iclass 36, count 0 2006.201.03:29:23.89#ibcon#enter sib2, iclass 36, count 0 2006.201.03:29:23.89#ibcon#flushed, iclass 36, count 0 2006.201.03:29:23.89#ibcon#about to write, iclass 36, count 0 2006.201.03:29:23.89#ibcon#wrote, iclass 36, count 0 2006.201.03:29:23.89#ibcon#about to read 3, iclass 36, count 0 2006.201.03:29:23.91#ibcon#read 3, iclass 36, count 0 2006.201.03:29:23.91#ibcon#about to read 4, iclass 36, count 0 2006.201.03:29:23.91#ibcon#read 4, iclass 36, count 0 2006.201.03:29:23.91#ibcon#about to read 5, iclass 36, count 0 2006.201.03:29:23.91#ibcon#read 5, iclass 36, count 0 2006.201.03:29:23.91#ibcon#about to read 6, iclass 36, count 0 2006.201.03:29:23.91#ibcon#read 6, iclass 36, count 0 2006.201.03:29:23.91#ibcon#end of sib2, iclass 36, count 0 2006.201.03:29:23.91#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:29:23.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:29:23.91#ibcon#[25=USB\r\n] 2006.201.03:29:23.91#ibcon#*before write, iclass 36, count 0 2006.201.03:29:23.91#ibcon#enter sib2, iclass 36, count 0 2006.201.03:29:23.91#ibcon#flushed, iclass 36, count 0 2006.201.03:29:23.91#ibcon#about to write, iclass 36, count 0 2006.201.03:29:23.91#ibcon#wrote, iclass 36, count 0 2006.201.03:29:23.91#ibcon#about to read 3, iclass 36, count 0 2006.201.03:29:23.94#ibcon#read 3, iclass 36, count 0 2006.201.03:29:23.94#ibcon#about to read 4, iclass 36, count 0 2006.201.03:29:23.94#ibcon#read 4, iclass 36, count 0 2006.201.03:29:23.94#ibcon#about to read 5, iclass 36, count 0 2006.201.03:29:23.94#ibcon#read 5, iclass 36, count 0 2006.201.03:29:23.94#ibcon#about to read 6, iclass 36, count 0 2006.201.03:29:23.94#ibcon#read 6, iclass 36, count 0 2006.201.03:29:23.94#ibcon#end of sib2, iclass 36, count 0 2006.201.03:29:23.94#ibcon#*after write, iclass 36, count 0 2006.201.03:29:23.94#ibcon#*before return 0, iclass 36, count 0 2006.201.03:29:23.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:23.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:23.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:29:23.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:29:23.94$vck44/valo=4,624.99 2006.201.03:29:23.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.03:29:23.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.03:29:23.94#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:23.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:23.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:23.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:23.94#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:29:23.94#ibcon#first serial, iclass 38, count 0 2006.201.03:29:23.94#ibcon#enter sib2, iclass 38, count 0 2006.201.03:29:23.94#ibcon#flushed, iclass 38, count 0 2006.201.03:29:23.94#ibcon#about to write, iclass 38, count 0 2006.201.03:29:23.94#ibcon#wrote, iclass 38, count 0 2006.201.03:29:23.94#ibcon#about to read 3, iclass 38, count 0 2006.201.03:29:23.96#ibcon#read 3, iclass 38, count 0 2006.201.03:29:23.96#ibcon#about to read 4, iclass 38, count 0 2006.201.03:29:23.96#ibcon#read 4, iclass 38, count 0 2006.201.03:29:23.96#ibcon#about to read 5, iclass 38, count 0 2006.201.03:29:23.96#ibcon#read 5, iclass 38, count 0 2006.201.03:29:23.96#ibcon#about to read 6, iclass 38, count 0 2006.201.03:29:23.96#ibcon#read 6, iclass 38, count 0 2006.201.03:29:23.96#ibcon#end of sib2, iclass 38, count 0 2006.201.03:29:23.96#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:29:23.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:29:23.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:29:23.96#ibcon#*before write, iclass 38, count 0 2006.201.03:29:23.96#ibcon#enter sib2, iclass 38, count 0 2006.201.03:29:23.96#ibcon#flushed, iclass 38, count 0 2006.201.03:29:23.96#ibcon#about to write, iclass 38, count 0 2006.201.03:29:23.96#ibcon#wrote, iclass 38, count 0 2006.201.03:29:23.96#ibcon#about to read 3, iclass 38, count 0 2006.201.03:29:24.00#ibcon#read 3, iclass 38, count 0 2006.201.03:29:24.00#ibcon#about to read 4, iclass 38, count 0 2006.201.03:29:24.00#ibcon#read 4, iclass 38, count 0 2006.201.03:29:24.00#ibcon#about to read 5, iclass 38, count 0 2006.201.03:29:24.00#ibcon#read 5, iclass 38, count 0 2006.201.03:29:24.00#ibcon#about to read 6, iclass 38, count 0 2006.201.03:29:24.00#ibcon#read 6, iclass 38, count 0 2006.201.03:29:24.00#ibcon#end of sib2, iclass 38, count 0 2006.201.03:29:24.00#ibcon#*after write, iclass 38, count 0 2006.201.03:29:24.00#ibcon#*before return 0, iclass 38, count 0 2006.201.03:29:24.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:24.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:24.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:29:24.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:29:24.00$vck44/va=4,7 2006.201.03:29:24.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.03:29:24.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.03:29:24.00#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:24.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:24.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:24.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:24.06#ibcon#enter wrdev, iclass 40, count 2 2006.201.03:29:24.06#ibcon#first serial, iclass 40, count 2 2006.201.03:29:24.06#ibcon#enter sib2, iclass 40, count 2 2006.201.03:29:24.06#ibcon#flushed, iclass 40, count 2 2006.201.03:29:24.06#ibcon#about to write, iclass 40, count 2 2006.201.03:29:24.06#ibcon#wrote, iclass 40, count 2 2006.201.03:29:24.06#ibcon#about to read 3, iclass 40, count 2 2006.201.03:29:24.08#ibcon#read 3, iclass 40, count 2 2006.201.03:29:24.08#ibcon#about to read 4, iclass 40, count 2 2006.201.03:29:24.08#ibcon#read 4, iclass 40, count 2 2006.201.03:29:24.08#ibcon#about to read 5, iclass 40, count 2 2006.201.03:29:24.08#ibcon#read 5, iclass 40, count 2 2006.201.03:29:24.08#ibcon#about to read 6, iclass 40, count 2 2006.201.03:29:24.08#ibcon#read 6, iclass 40, count 2 2006.201.03:29:24.08#ibcon#end of sib2, iclass 40, count 2 2006.201.03:29:24.08#ibcon#*mode == 0, iclass 40, count 2 2006.201.03:29:24.08#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.03:29:24.08#ibcon#[25=AT04-07\r\n] 2006.201.03:29:24.08#ibcon#*before write, iclass 40, count 2 2006.201.03:29:24.08#ibcon#enter sib2, iclass 40, count 2 2006.201.03:29:24.08#ibcon#flushed, iclass 40, count 2 2006.201.03:29:24.08#ibcon#about to write, iclass 40, count 2 2006.201.03:29:24.08#ibcon#wrote, iclass 40, count 2 2006.201.03:29:24.08#ibcon#about to read 3, iclass 40, count 2 2006.201.03:29:24.11#ibcon#read 3, iclass 40, count 2 2006.201.03:29:24.11#ibcon#about to read 4, iclass 40, count 2 2006.201.03:29:24.11#ibcon#read 4, iclass 40, count 2 2006.201.03:29:24.11#ibcon#about to read 5, iclass 40, count 2 2006.201.03:29:24.11#ibcon#read 5, iclass 40, count 2 2006.201.03:29:24.11#ibcon#about to read 6, iclass 40, count 2 2006.201.03:29:24.11#ibcon#read 6, iclass 40, count 2 2006.201.03:29:24.11#ibcon#end of sib2, iclass 40, count 2 2006.201.03:29:24.11#ibcon#*after write, iclass 40, count 2 2006.201.03:29:24.11#ibcon#*before return 0, iclass 40, count 2 2006.201.03:29:24.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:24.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:24.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.03:29:24.11#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:24.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:24.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:24.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:24.23#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:29:24.23#ibcon#first serial, iclass 40, count 0 2006.201.03:29:24.23#ibcon#enter sib2, iclass 40, count 0 2006.201.03:29:24.23#ibcon#flushed, iclass 40, count 0 2006.201.03:29:24.23#ibcon#about to write, iclass 40, count 0 2006.201.03:29:24.23#ibcon#wrote, iclass 40, count 0 2006.201.03:29:24.23#ibcon#about to read 3, iclass 40, count 0 2006.201.03:29:24.25#ibcon#read 3, iclass 40, count 0 2006.201.03:29:24.25#ibcon#about to read 4, iclass 40, count 0 2006.201.03:29:24.25#ibcon#read 4, iclass 40, count 0 2006.201.03:29:24.25#ibcon#about to read 5, iclass 40, count 0 2006.201.03:29:24.25#ibcon#read 5, iclass 40, count 0 2006.201.03:29:24.25#ibcon#about to read 6, iclass 40, count 0 2006.201.03:29:24.25#ibcon#read 6, iclass 40, count 0 2006.201.03:29:24.25#ibcon#end of sib2, iclass 40, count 0 2006.201.03:29:24.25#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:29:24.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:29:24.25#ibcon#[25=USB\r\n] 2006.201.03:29:24.25#ibcon#*before write, iclass 40, count 0 2006.201.03:29:24.25#ibcon#enter sib2, iclass 40, count 0 2006.201.03:29:24.25#ibcon#flushed, iclass 40, count 0 2006.201.03:29:24.25#ibcon#about to write, iclass 40, count 0 2006.201.03:29:24.25#ibcon#wrote, iclass 40, count 0 2006.201.03:29:24.25#ibcon#about to read 3, iclass 40, count 0 2006.201.03:29:24.28#ibcon#read 3, iclass 40, count 0 2006.201.03:29:24.28#ibcon#about to read 4, iclass 40, count 0 2006.201.03:29:24.28#ibcon#read 4, iclass 40, count 0 2006.201.03:29:24.28#ibcon#about to read 5, iclass 40, count 0 2006.201.03:29:24.28#ibcon#read 5, iclass 40, count 0 2006.201.03:29:24.28#ibcon#about to read 6, iclass 40, count 0 2006.201.03:29:24.28#ibcon#read 6, iclass 40, count 0 2006.201.03:29:24.28#ibcon#end of sib2, iclass 40, count 0 2006.201.03:29:24.28#ibcon#*after write, iclass 40, count 0 2006.201.03:29:24.28#ibcon#*before return 0, iclass 40, count 0 2006.201.03:29:24.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:24.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:24.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:29:24.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:29:24.28$vck44/valo=5,734.99 2006.201.03:29:24.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.03:29:24.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.03:29:24.28#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:24.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:24.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:24.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:24.28#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:29:24.28#ibcon#first serial, iclass 4, count 0 2006.201.03:29:24.28#ibcon#enter sib2, iclass 4, count 0 2006.201.03:29:24.28#ibcon#flushed, iclass 4, count 0 2006.201.03:29:24.28#ibcon#about to write, iclass 4, count 0 2006.201.03:29:24.28#ibcon#wrote, iclass 4, count 0 2006.201.03:29:24.28#ibcon#about to read 3, iclass 4, count 0 2006.201.03:29:24.30#ibcon#read 3, iclass 4, count 0 2006.201.03:29:24.30#ibcon#about to read 4, iclass 4, count 0 2006.201.03:29:24.30#ibcon#read 4, iclass 4, count 0 2006.201.03:29:24.30#ibcon#about to read 5, iclass 4, count 0 2006.201.03:29:24.30#ibcon#read 5, iclass 4, count 0 2006.201.03:29:24.30#ibcon#about to read 6, iclass 4, count 0 2006.201.03:29:24.30#ibcon#read 6, iclass 4, count 0 2006.201.03:29:24.30#ibcon#end of sib2, iclass 4, count 0 2006.201.03:29:24.30#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:29:24.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:29:24.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:29:24.30#ibcon#*before write, iclass 4, count 0 2006.201.03:29:24.30#ibcon#enter sib2, iclass 4, count 0 2006.201.03:29:24.30#ibcon#flushed, iclass 4, count 0 2006.201.03:29:24.30#ibcon#about to write, iclass 4, count 0 2006.201.03:29:24.30#ibcon#wrote, iclass 4, count 0 2006.201.03:29:24.30#ibcon#about to read 3, iclass 4, count 0 2006.201.03:29:24.34#ibcon#read 3, iclass 4, count 0 2006.201.03:29:24.34#ibcon#about to read 4, iclass 4, count 0 2006.201.03:29:24.34#ibcon#read 4, iclass 4, count 0 2006.201.03:29:24.34#ibcon#about to read 5, iclass 4, count 0 2006.201.03:29:24.34#ibcon#read 5, iclass 4, count 0 2006.201.03:29:24.34#ibcon#about to read 6, iclass 4, count 0 2006.201.03:29:24.34#ibcon#read 6, iclass 4, count 0 2006.201.03:29:24.34#ibcon#end of sib2, iclass 4, count 0 2006.201.03:29:24.34#ibcon#*after write, iclass 4, count 0 2006.201.03:29:24.34#ibcon#*before return 0, iclass 4, count 0 2006.201.03:29:24.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:24.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:24.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:29:24.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:29:24.34$vck44/va=5,4 2006.201.03:29:24.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.03:29:24.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.03:29:24.34#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:24.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:24.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:24.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:24.40#ibcon#enter wrdev, iclass 6, count 2 2006.201.03:29:24.40#ibcon#first serial, iclass 6, count 2 2006.201.03:29:24.40#ibcon#enter sib2, iclass 6, count 2 2006.201.03:29:24.40#ibcon#flushed, iclass 6, count 2 2006.201.03:29:24.40#ibcon#about to write, iclass 6, count 2 2006.201.03:29:24.40#ibcon#wrote, iclass 6, count 2 2006.201.03:29:24.40#ibcon#about to read 3, iclass 6, count 2 2006.201.03:29:24.42#ibcon#read 3, iclass 6, count 2 2006.201.03:29:24.42#ibcon#about to read 4, iclass 6, count 2 2006.201.03:29:24.42#ibcon#read 4, iclass 6, count 2 2006.201.03:29:24.42#ibcon#about to read 5, iclass 6, count 2 2006.201.03:29:24.42#ibcon#read 5, iclass 6, count 2 2006.201.03:29:24.42#ibcon#about to read 6, iclass 6, count 2 2006.201.03:29:24.42#ibcon#read 6, iclass 6, count 2 2006.201.03:29:24.42#ibcon#end of sib2, iclass 6, count 2 2006.201.03:29:24.42#ibcon#*mode == 0, iclass 6, count 2 2006.201.03:29:24.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.03:29:24.42#ibcon#[25=AT05-04\r\n] 2006.201.03:29:24.42#ibcon#*before write, iclass 6, count 2 2006.201.03:29:24.42#ibcon#enter sib2, iclass 6, count 2 2006.201.03:29:24.42#ibcon#flushed, iclass 6, count 2 2006.201.03:29:24.42#ibcon#about to write, iclass 6, count 2 2006.201.03:29:24.42#ibcon#wrote, iclass 6, count 2 2006.201.03:29:24.42#ibcon#about to read 3, iclass 6, count 2 2006.201.03:29:24.45#ibcon#read 3, iclass 6, count 2 2006.201.03:29:24.45#ibcon#about to read 4, iclass 6, count 2 2006.201.03:29:24.45#ibcon#read 4, iclass 6, count 2 2006.201.03:29:24.45#ibcon#about to read 5, iclass 6, count 2 2006.201.03:29:24.45#ibcon#read 5, iclass 6, count 2 2006.201.03:29:24.45#ibcon#about to read 6, iclass 6, count 2 2006.201.03:29:24.45#ibcon#read 6, iclass 6, count 2 2006.201.03:29:24.45#ibcon#end of sib2, iclass 6, count 2 2006.201.03:29:24.45#ibcon#*after write, iclass 6, count 2 2006.201.03:29:24.45#ibcon#*before return 0, iclass 6, count 2 2006.201.03:29:24.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:24.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:24.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.03:29:24.45#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:24.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:24.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:24.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:24.57#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:29:24.57#ibcon#first serial, iclass 6, count 0 2006.201.03:29:24.57#ibcon#enter sib2, iclass 6, count 0 2006.201.03:29:24.57#ibcon#flushed, iclass 6, count 0 2006.201.03:29:24.57#ibcon#about to write, iclass 6, count 0 2006.201.03:29:24.57#ibcon#wrote, iclass 6, count 0 2006.201.03:29:24.57#ibcon#about to read 3, iclass 6, count 0 2006.201.03:29:24.59#ibcon#read 3, iclass 6, count 0 2006.201.03:29:24.59#ibcon#about to read 4, iclass 6, count 0 2006.201.03:29:24.59#ibcon#read 4, iclass 6, count 0 2006.201.03:29:24.59#ibcon#about to read 5, iclass 6, count 0 2006.201.03:29:24.59#ibcon#read 5, iclass 6, count 0 2006.201.03:29:24.59#ibcon#about to read 6, iclass 6, count 0 2006.201.03:29:24.59#ibcon#read 6, iclass 6, count 0 2006.201.03:29:24.59#ibcon#end of sib2, iclass 6, count 0 2006.201.03:29:24.59#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:29:24.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:29:24.59#ibcon#[25=USB\r\n] 2006.201.03:29:24.59#ibcon#*before write, iclass 6, count 0 2006.201.03:29:24.59#ibcon#enter sib2, iclass 6, count 0 2006.201.03:29:24.59#ibcon#flushed, iclass 6, count 0 2006.201.03:29:24.59#ibcon#about to write, iclass 6, count 0 2006.201.03:29:24.59#ibcon#wrote, iclass 6, count 0 2006.201.03:29:24.59#ibcon#about to read 3, iclass 6, count 0 2006.201.03:29:24.62#ibcon#read 3, iclass 6, count 0 2006.201.03:29:24.62#ibcon#about to read 4, iclass 6, count 0 2006.201.03:29:24.62#ibcon#read 4, iclass 6, count 0 2006.201.03:29:24.62#ibcon#about to read 5, iclass 6, count 0 2006.201.03:29:24.62#ibcon#read 5, iclass 6, count 0 2006.201.03:29:24.62#ibcon#about to read 6, iclass 6, count 0 2006.201.03:29:24.62#ibcon#read 6, iclass 6, count 0 2006.201.03:29:24.62#ibcon#end of sib2, iclass 6, count 0 2006.201.03:29:24.62#ibcon#*after write, iclass 6, count 0 2006.201.03:29:24.62#ibcon#*before return 0, iclass 6, count 0 2006.201.03:29:24.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:24.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:24.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:29:24.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:29:24.62$vck44/valo=6,814.99 2006.201.03:29:24.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.03:29:24.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.03:29:24.62#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:24.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:24.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:24.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:24.62#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:29:24.62#ibcon#first serial, iclass 10, count 0 2006.201.03:29:24.62#ibcon#enter sib2, iclass 10, count 0 2006.201.03:29:24.62#ibcon#flushed, iclass 10, count 0 2006.201.03:29:24.62#ibcon#about to write, iclass 10, count 0 2006.201.03:29:24.62#ibcon#wrote, iclass 10, count 0 2006.201.03:29:24.62#ibcon#about to read 3, iclass 10, count 0 2006.201.03:29:24.64#ibcon#read 3, iclass 10, count 0 2006.201.03:29:24.64#ibcon#about to read 4, iclass 10, count 0 2006.201.03:29:24.64#ibcon#read 4, iclass 10, count 0 2006.201.03:29:24.64#ibcon#about to read 5, iclass 10, count 0 2006.201.03:29:24.64#ibcon#read 5, iclass 10, count 0 2006.201.03:29:24.64#ibcon#about to read 6, iclass 10, count 0 2006.201.03:29:24.64#ibcon#read 6, iclass 10, count 0 2006.201.03:29:24.64#ibcon#end of sib2, iclass 10, count 0 2006.201.03:29:24.64#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:29:24.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:29:24.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:29:24.64#ibcon#*before write, iclass 10, count 0 2006.201.03:29:24.64#ibcon#enter sib2, iclass 10, count 0 2006.201.03:29:24.64#ibcon#flushed, iclass 10, count 0 2006.201.03:29:24.64#ibcon#about to write, iclass 10, count 0 2006.201.03:29:24.64#ibcon#wrote, iclass 10, count 0 2006.201.03:29:24.64#ibcon#about to read 3, iclass 10, count 0 2006.201.03:29:24.69#ibcon#read 3, iclass 10, count 0 2006.201.03:29:24.69#ibcon#about to read 4, iclass 10, count 0 2006.201.03:29:24.69#ibcon#read 4, iclass 10, count 0 2006.201.03:29:24.69#ibcon#about to read 5, iclass 10, count 0 2006.201.03:29:24.69#ibcon#read 5, iclass 10, count 0 2006.201.03:29:24.69#ibcon#about to read 6, iclass 10, count 0 2006.201.03:29:24.69#ibcon#read 6, iclass 10, count 0 2006.201.03:29:24.69#ibcon#end of sib2, iclass 10, count 0 2006.201.03:29:24.69#ibcon#*after write, iclass 10, count 0 2006.201.03:29:24.69#ibcon#*before return 0, iclass 10, count 0 2006.201.03:29:24.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:24.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:24.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:29:24.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:29:24.69$vck44/va=6,5 2006.201.03:29:24.69#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.03:29:24.69#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.03:29:24.69#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:24.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:24.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:24.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:24.74#ibcon#enter wrdev, iclass 12, count 2 2006.201.03:29:24.74#ibcon#first serial, iclass 12, count 2 2006.201.03:29:24.74#ibcon#enter sib2, iclass 12, count 2 2006.201.03:29:24.74#ibcon#flushed, iclass 12, count 2 2006.201.03:29:24.74#ibcon#about to write, iclass 12, count 2 2006.201.03:29:24.74#ibcon#wrote, iclass 12, count 2 2006.201.03:29:24.74#ibcon#about to read 3, iclass 12, count 2 2006.201.03:29:24.76#ibcon#read 3, iclass 12, count 2 2006.201.03:29:24.76#ibcon#about to read 4, iclass 12, count 2 2006.201.03:29:24.76#ibcon#read 4, iclass 12, count 2 2006.201.03:29:24.76#ibcon#about to read 5, iclass 12, count 2 2006.201.03:29:24.76#ibcon#read 5, iclass 12, count 2 2006.201.03:29:24.76#ibcon#about to read 6, iclass 12, count 2 2006.201.03:29:24.76#ibcon#read 6, iclass 12, count 2 2006.201.03:29:24.76#ibcon#end of sib2, iclass 12, count 2 2006.201.03:29:24.76#ibcon#*mode == 0, iclass 12, count 2 2006.201.03:29:24.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.03:29:24.76#ibcon#[25=AT06-05\r\n] 2006.201.03:29:24.76#ibcon#*before write, iclass 12, count 2 2006.201.03:29:24.76#ibcon#enter sib2, iclass 12, count 2 2006.201.03:29:24.76#ibcon#flushed, iclass 12, count 2 2006.201.03:29:24.76#ibcon#about to write, iclass 12, count 2 2006.201.03:29:24.76#ibcon#wrote, iclass 12, count 2 2006.201.03:29:24.76#ibcon#about to read 3, iclass 12, count 2 2006.201.03:29:24.79#ibcon#read 3, iclass 12, count 2 2006.201.03:29:24.79#ibcon#about to read 4, iclass 12, count 2 2006.201.03:29:24.79#ibcon#read 4, iclass 12, count 2 2006.201.03:29:24.79#ibcon#about to read 5, iclass 12, count 2 2006.201.03:29:24.79#ibcon#read 5, iclass 12, count 2 2006.201.03:29:24.79#ibcon#about to read 6, iclass 12, count 2 2006.201.03:29:24.79#ibcon#read 6, iclass 12, count 2 2006.201.03:29:24.79#ibcon#end of sib2, iclass 12, count 2 2006.201.03:29:24.79#ibcon#*after write, iclass 12, count 2 2006.201.03:29:24.79#ibcon#*before return 0, iclass 12, count 2 2006.201.03:29:24.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:24.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:24.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.03:29:24.79#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:24.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:24.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:24.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:24.91#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:29:24.91#ibcon#first serial, iclass 12, count 0 2006.201.03:29:24.91#ibcon#enter sib2, iclass 12, count 0 2006.201.03:29:24.91#ibcon#flushed, iclass 12, count 0 2006.201.03:29:24.91#ibcon#about to write, iclass 12, count 0 2006.201.03:29:24.91#ibcon#wrote, iclass 12, count 0 2006.201.03:29:24.91#ibcon#about to read 3, iclass 12, count 0 2006.201.03:29:24.93#ibcon#read 3, iclass 12, count 0 2006.201.03:29:24.93#ibcon#about to read 4, iclass 12, count 0 2006.201.03:29:24.93#ibcon#read 4, iclass 12, count 0 2006.201.03:29:24.93#ibcon#about to read 5, iclass 12, count 0 2006.201.03:29:24.93#ibcon#read 5, iclass 12, count 0 2006.201.03:29:24.93#ibcon#about to read 6, iclass 12, count 0 2006.201.03:29:24.93#ibcon#read 6, iclass 12, count 0 2006.201.03:29:24.93#ibcon#end of sib2, iclass 12, count 0 2006.201.03:29:24.93#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:29:24.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:29:24.93#ibcon#[25=USB\r\n] 2006.201.03:29:24.93#ibcon#*before write, iclass 12, count 0 2006.201.03:29:24.93#ibcon#enter sib2, iclass 12, count 0 2006.201.03:29:24.93#ibcon#flushed, iclass 12, count 0 2006.201.03:29:24.93#ibcon#about to write, iclass 12, count 0 2006.201.03:29:24.93#ibcon#wrote, iclass 12, count 0 2006.201.03:29:24.93#ibcon#about to read 3, iclass 12, count 0 2006.201.03:29:24.96#ibcon#read 3, iclass 12, count 0 2006.201.03:29:24.96#ibcon#about to read 4, iclass 12, count 0 2006.201.03:29:24.96#ibcon#read 4, iclass 12, count 0 2006.201.03:29:24.96#ibcon#about to read 5, iclass 12, count 0 2006.201.03:29:24.96#ibcon#read 5, iclass 12, count 0 2006.201.03:29:24.96#ibcon#about to read 6, iclass 12, count 0 2006.201.03:29:24.96#ibcon#read 6, iclass 12, count 0 2006.201.03:29:24.96#ibcon#end of sib2, iclass 12, count 0 2006.201.03:29:24.96#ibcon#*after write, iclass 12, count 0 2006.201.03:29:24.96#ibcon#*before return 0, iclass 12, count 0 2006.201.03:29:24.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:24.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:24.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:29:24.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:29:24.96$vck44/valo=7,864.99 2006.201.03:29:24.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.03:29:24.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.03:29:24.96#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:24.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:24.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:24.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:24.96#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:29:24.96#ibcon#first serial, iclass 14, count 0 2006.201.03:29:24.96#ibcon#enter sib2, iclass 14, count 0 2006.201.03:29:24.96#ibcon#flushed, iclass 14, count 0 2006.201.03:29:24.96#ibcon#about to write, iclass 14, count 0 2006.201.03:29:24.96#ibcon#wrote, iclass 14, count 0 2006.201.03:29:24.96#ibcon#about to read 3, iclass 14, count 0 2006.201.03:29:24.98#ibcon#read 3, iclass 14, count 0 2006.201.03:29:24.98#ibcon#about to read 4, iclass 14, count 0 2006.201.03:29:24.98#ibcon#read 4, iclass 14, count 0 2006.201.03:29:24.98#ibcon#about to read 5, iclass 14, count 0 2006.201.03:29:24.98#ibcon#read 5, iclass 14, count 0 2006.201.03:29:24.98#ibcon#about to read 6, iclass 14, count 0 2006.201.03:29:24.98#ibcon#read 6, iclass 14, count 0 2006.201.03:29:24.98#ibcon#end of sib2, iclass 14, count 0 2006.201.03:29:24.98#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:29:24.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:29:24.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:29:24.98#ibcon#*before write, iclass 14, count 0 2006.201.03:29:24.98#ibcon#enter sib2, iclass 14, count 0 2006.201.03:29:24.98#ibcon#flushed, iclass 14, count 0 2006.201.03:29:24.98#ibcon#about to write, iclass 14, count 0 2006.201.03:29:24.98#ibcon#wrote, iclass 14, count 0 2006.201.03:29:24.98#ibcon#about to read 3, iclass 14, count 0 2006.201.03:29:25.02#ibcon#read 3, iclass 14, count 0 2006.201.03:29:25.02#ibcon#about to read 4, iclass 14, count 0 2006.201.03:29:25.02#ibcon#read 4, iclass 14, count 0 2006.201.03:29:25.02#ibcon#about to read 5, iclass 14, count 0 2006.201.03:29:25.02#ibcon#read 5, iclass 14, count 0 2006.201.03:29:25.02#ibcon#about to read 6, iclass 14, count 0 2006.201.03:29:25.02#ibcon#read 6, iclass 14, count 0 2006.201.03:29:25.02#ibcon#end of sib2, iclass 14, count 0 2006.201.03:29:25.02#ibcon#*after write, iclass 14, count 0 2006.201.03:29:25.02#ibcon#*before return 0, iclass 14, count 0 2006.201.03:29:25.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:25.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:25.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:29:25.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:29:25.02$vck44/va=7,5 2006.201.03:29:25.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.03:29:25.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.03:29:25.02#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:25.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:25.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:25.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:25.08#ibcon#enter wrdev, iclass 16, count 2 2006.201.03:29:25.08#ibcon#first serial, iclass 16, count 2 2006.201.03:29:25.08#ibcon#enter sib2, iclass 16, count 2 2006.201.03:29:25.08#ibcon#flushed, iclass 16, count 2 2006.201.03:29:25.08#ibcon#about to write, iclass 16, count 2 2006.201.03:29:25.08#ibcon#wrote, iclass 16, count 2 2006.201.03:29:25.08#ibcon#about to read 3, iclass 16, count 2 2006.201.03:29:25.10#ibcon#read 3, iclass 16, count 2 2006.201.03:29:25.10#ibcon#about to read 4, iclass 16, count 2 2006.201.03:29:25.10#ibcon#read 4, iclass 16, count 2 2006.201.03:29:25.10#ibcon#about to read 5, iclass 16, count 2 2006.201.03:29:25.10#ibcon#read 5, iclass 16, count 2 2006.201.03:29:25.10#ibcon#about to read 6, iclass 16, count 2 2006.201.03:29:25.10#ibcon#read 6, iclass 16, count 2 2006.201.03:29:25.10#ibcon#end of sib2, iclass 16, count 2 2006.201.03:29:25.10#ibcon#*mode == 0, iclass 16, count 2 2006.201.03:29:25.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.03:29:25.10#ibcon#[25=AT07-05\r\n] 2006.201.03:29:25.10#ibcon#*before write, iclass 16, count 2 2006.201.03:29:25.10#ibcon#enter sib2, iclass 16, count 2 2006.201.03:29:25.10#ibcon#flushed, iclass 16, count 2 2006.201.03:29:25.10#ibcon#about to write, iclass 16, count 2 2006.201.03:29:25.10#ibcon#wrote, iclass 16, count 2 2006.201.03:29:25.10#ibcon#about to read 3, iclass 16, count 2 2006.201.03:29:25.13#ibcon#read 3, iclass 16, count 2 2006.201.03:29:25.13#ibcon#about to read 4, iclass 16, count 2 2006.201.03:29:25.13#ibcon#read 4, iclass 16, count 2 2006.201.03:29:25.13#ibcon#about to read 5, iclass 16, count 2 2006.201.03:29:25.13#ibcon#read 5, iclass 16, count 2 2006.201.03:29:25.13#ibcon#about to read 6, iclass 16, count 2 2006.201.03:29:25.13#ibcon#read 6, iclass 16, count 2 2006.201.03:29:25.13#ibcon#end of sib2, iclass 16, count 2 2006.201.03:29:25.13#ibcon#*after write, iclass 16, count 2 2006.201.03:29:25.13#ibcon#*before return 0, iclass 16, count 2 2006.201.03:29:25.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:25.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:25.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.03:29:25.13#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:25.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:25.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:25.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:25.25#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:29:25.25#ibcon#first serial, iclass 16, count 0 2006.201.03:29:25.25#ibcon#enter sib2, iclass 16, count 0 2006.201.03:29:25.25#ibcon#flushed, iclass 16, count 0 2006.201.03:29:25.25#ibcon#about to write, iclass 16, count 0 2006.201.03:29:25.25#ibcon#wrote, iclass 16, count 0 2006.201.03:29:25.25#ibcon#about to read 3, iclass 16, count 0 2006.201.03:29:25.27#ibcon#read 3, iclass 16, count 0 2006.201.03:29:25.27#ibcon#about to read 4, iclass 16, count 0 2006.201.03:29:25.27#ibcon#read 4, iclass 16, count 0 2006.201.03:29:25.27#ibcon#about to read 5, iclass 16, count 0 2006.201.03:29:25.27#ibcon#read 5, iclass 16, count 0 2006.201.03:29:25.27#ibcon#about to read 6, iclass 16, count 0 2006.201.03:29:25.27#ibcon#read 6, iclass 16, count 0 2006.201.03:29:25.27#ibcon#end of sib2, iclass 16, count 0 2006.201.03:29:25.27#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:29:25.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:29:25.27#ibcon#[25=USB\r\n] 2006.201.03:29:25.27#ibcon#*before write, iclass 16, count 0 2006.201.03:29:25.27#ibcon#enter sib2, iclass 16, count 0 2006.201.03:29:25.27#ibcon#flushed, iclass 16, count 0 2006.201.03:29:25.27#ibcon#about to write, iclass 16, count 0 2006.201.03:29:25.27#ibcon#wrote, iclass 16, count 0 2006.201.03:29:25.27#ibcon#about to read 3, iclass 16, count 0 2006.201.03:29:25.30#ibcon#read 3, iclass 16, count 0 2006.201.03:29:25.30#ibcon#about to read 4, iclass 16, count 0 2006.201.03:29:25.30#ibcon#read 4, iclass 16, count 0 2006.201.03:29:25.30#ibcon#about to read 5, iclass 16, count 0 2006.201.03:29:25.30#ibcon#read 5, iclass 16, count 0 2006.201.03:29:25.30#ibcon#about to read 6, iclass 16, count 0 2006.201.03:29:25.30#ibcon#read 6, iclass 16, count 0 2006.201.03:29:25.30#ibcon#end of sib2, iclass 16, count 0 2006.201.03:29:25.30#ibcon#*after write, iclass 16, count 0 2006.201.03:29:25.30#ibcon#*before return 0, iclass 16, count 0 2006.201.03:29:25.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:25.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:25.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:29:25.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:29:25.30$vck44/valo=8,884.99 2006.201.03:29:25.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.03:29:25.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.03:29:25.30#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:25.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:25.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:25.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:25.30#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:29:25.30#ibcon#first serial, iclass 18, count 0 2006.201.03:29:25.30#ibcon#enter sib2, iclass 18, count 0 2006.201.03:29:25.30#ibcon#flushed, iclass 18, count 0 2006.201.03:29:25.30#ibcon#about to write, iclass 18, count 0 2006.201.03:29:25.30#ibcon#wrote, iclass 18, count 0 2006.201.03:29:25.30#ibcon#about to read 3, iclass 18, count 0 2006.201.03:29:25.32#ibcon#read 3, iclass 18, count 0 2006.201.03:29:25.32#ibcon#about to read 4, iclass 18, count 0 2006.201.03:29:25.32#ibcon#read 4, iclass 18, count 0 2006.201.03:29:25.32#ibcon#about to read 5, iclass 18, count 0 2006.201.03:29:25.32#ibcon#read 5, iclass 18, count 0 2006.201.03:29:25.32#ibcon#about to read 6, iclass 18, count 0 2006.201.03:29:25.32#ibcon#read 6, iclass 18, count 0 2006.201.03:29:25.32#ibcon#end of sib2, iclass 18, count 0 2006.201.03:29:25.32#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:29:25.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:29:25.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:29:25.32#ibcon#*before write, iclass 18, count 0 2006.201.03:29:25.32#ibcon#enter sib2, iclass 18, count 0 2006.201.03:29:25.32#ibcon#flushed, iclass 18, count 0 2006.201.03:29:25.32#ibcon#about to write, iclass 18, count 0 2006.201.03:29:25.32#ibcon#wrote, iclass 18, count 0 2006.201.03:29:25.32#ibcon#about to read 3, iclass 18, count 0 2006.201.03:29:25.37#ibcon#read 3, iclass 18, count 0 2006.201.03:29:25.37#ibcon#about to read 4, iclass 18, count 0 2006.201.03:29:25.37#ibcon#read 4, iclass 18, count 0 2006.201.03:29:25.37#ibcon#about to read 5, iclass 18, count 0 2006.201.03:29:25.37#ibcon#read 5, iclass 18, count 0 2006.201.03:29:25.37#ibcon#about to read 6, iclass 18, count 0 2006.201.03:29:25.37#ibcon#read 6, iclass 18, count 0 2006.201.03:29:25.37#ibcon#end of sib2, iclass 18, count 0 2006.201.03:29:25.37#ibcon#*after write, iclass 18, count 0 2006.201.03:29:25.37#ibcon#*before return 0, iclass 18, count 0 2006.201.03:29:25.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:25.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:25.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:29:25.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:29:25.37$vck44/va=8,4 2006.201.03:29:25.37#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.03:29:25.37#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.03:29:25.37#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:25.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:29:25.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:29:25.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:29:25.42#ibcon#enter wrdev, iclass 20, count 2 2006.201.03:29:25.42#ibcon#first serial, iclass 20, count 2 2006.201.03:29:25.42#ibcon#enter sib2, iclass 20, count 2 2006.201.03:29:25.42#ibcon#flushed, iclass 20, count 2 2006.201.03:29:25.42#ibcon#about to write, iclass 20, count 2 2006.201.03:29:25.42#ibcon#wrote, iclass 20, count 2 2006.201.03:29:25.42#ibcon#about to read 3, iclass 20, count 2 2006.201.03:29:25.44#ibcon#read 3, iclass 20, count 2 2006.201.03:29:25.44#ibcon#about to read 4, iclass 20, count 2 2006.201.03:29:25.44#ibcon#read 4, iclass 20, count 2 2006.201.03:29:25.44#ibcon#about to read 5, iclass 20, count 2 2006.201.03:29:25.44#ibcon#read 5, iclass 20, count 2 2006.201.03:29:25.44#ibcon#about to read 6, iclass 20, count 2 2006.201.03:29:25.44#ibcon#read 6, iclass 20, count 2 2006.201.03:29:25.44#ibcon#end of sib2, iclass 20, count 2 2006.201.03:29:25.44#ibcon#*mode == 0, iclass 20, count 2 2006.201.03:29:25.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.03:29:25.44#ibcon#[25=AT08-04\r\n] 2006.201.03:29:25.44#ibcon#*before write, iclass 20, count 2 2006.201.03:29:25.44#ibcon#enter sib2, iclass 20, count 2 2006.201.03:29:25.44#ibcon#flushed, iclass 20, count 2 2006.201.03:29:25.44#ibcon#about to write, iclass 20, count 2 2006.201.03:29:25.44#ibcon#wrote, iclass 20, count 2 2006.201.03:29:25.44#ibcon#about to read 3, iclass 20, count 2 2006.201.03:29:25.47#ibcon#read 3, iclass 20, count 2 2006.201.03:29:25.47#ibcon#about to read 4, iclass 20, count 2 2006.201.03:29:25.47#ibcon#read 4, iclass 20, count 2 2006.201.03:29:25.47#ibcon#about to read 5, iclass 20, count 2 2006.201.03:29:25.47#ibcon#read 5, iclass 20, count 2 2006.201.03:29:25.47#ibcon#about to read 6, iclass 20, count 2 2006.201.03:29:25.47#ibcon#read 6, iclass 20, count 2 2006.201.03:29:25.47#ibcon#end of sib2, iclass 20, count 2 2006.201.03:29:25.47#ibcon#*after write, iclass 20, count 2 2006.201.03:29:25.47#ibcon#*before return 0, iclass 20, count 2 2006.201.03:29:25.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:29:25.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:29:25.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.03:29:25.47#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:25.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:29:25.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:29:25.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:29:25.59#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:29:25.59#ibcon#first serial, iclass 20, count 0 2006.201.03:29:25.59#ibcon#enter sib2, iclass 20, count 0 2006.201.03:29:25.59#ibcon#flushed, iclass 20, count 0 2006.201.03:29:25.59#ibcon#about to write, iclass 20, count 0 2006.201.03:29:25.59#ibcon#wrote, iclass 20, count 0 2006.201.03:29:25.59#ibcon#about to read 3, iclass 20, count 0 2006.201.03:29:25.61#ibcon#read 3, iclass 20, count 0 2006.201.03:29:25.61#ibcon#about to read 4, iclass 20, count 0 2006.201.03:29:25.61#ibcon#read 4, iclass 20, count 0 2006.201.03:29:25.61#ibcon#about to read 5, iclass 20, count 0 2006.201.03:29:25.61#ibcon#read 5, iclass 20, count 0 2006.201.03:29:25.61#ibcon#about to read 6, iclass 20, count 0 2006.201.03:29:25.61#ibcon#read 6, iclass 20, count 0 2006.201.03:29:25.61#ibcon#end of sib2, iclass 20, count 0 2006.201.03:29:25.61#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:29:25.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:29:25.61#ibcon#[25=USB\r\n] 2006.201.03:29:25.61#ibcon#*before write, iclass 20, count 0 2006.201.03:29:25.61#ibcon#enter sib2, iclass 20, count 0 2006.201.03:29:25.61#ibcon#flushed, iclass 20, count 0 2006.201.03:29:25.61#ibcon#about to write, iclass 20, count 0 2006.201.03:29:25.61#ibcon#wrote, iclass 20, count 0 2006.201.03:29:25.61#ibcon#about to read 3, iclass 20, count 0 2006.201.03:29:25.64#ibcon#read 3, iclass 20, count 0 2006.201.03:29:25.64#ibcon#about to read 4, iclass 20, count 0 2006.201.03:29:25.64#ibcon#read 4, iclass 20, count 0 2006.201.03:29:25.64#ibcon#about to read 5, iclass 20, count 0 2006.201.03:29:25.64#ibcon#read 5, iclass 20, count 0 2006.201.03:29:25.64#ibcon#about to read 6, iclass 20, count 0 2006.201.03:29:25.64#ibcon#read 6, iclass 20, count 0 2006.201.03:29:25.64#ibcon#end of sib2, iclass 20, count 0 2006.201.03:29:25.64#ibcon#*after write, iclass 20, count 0 2006.201.03:29:25.64#ibcon#*before return 0, iclass 20, count 0 2006.201.03:29:25.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:29:25.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:29:25.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:29:25.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:29:25.64$vck44/vblo=1,629.99 2006.201.03:29:25.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.03:29:25.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.03:29:25.64#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:25.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:29:25.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:29:25.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:29:25.64#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:29:25.64#ibcon#first serial, iclass 22, count 0 2006.201.03:29:25.64#ibcon#enter sib2, iclass 22, count 0 2006.201.03:29:25.64#ibcon#flushed, iclass 22, count 0 2006.201.03:29:25.64#ibcon#about to write, iclass 22, count 0 2006.201.03:29:25.64#ibcon#wrote, iclass 22, count 0 2006.201.03:29:25.64#ibcon#about to read 3, iclass 22, count 0 2006.201.03:29:25.66#ibcon#read 3, iclass 22, count 0 2006.201.03:29:25.66#ibcon#about to read 4, iclass 22, count 0 2006.201.03:29:25.66#ibcon#read 4, iclass 22, count 0 2006.201.03:29:25.66#ibcon#about to read 5, iclass 22, count 0 2006.201.03:29:25.66#ibcon#read 5, iclass 22, count 0 2006.201.03:29:25.66#ibcon#about to read 6, iclass 22, count 0 2006.201.03:29:25.66#ibcon#read 6, iclass 22, count 0 2006.201.03:29:25.66#ibcon#end of sib2, iclass 22, count 0 2006.201.03:29:25.66#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:29:25.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:29:25.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:29:25.66#ibcon#*before write, iclass 22, count 0 2006.201.03:29:25.66#ibcon#enter sib2, iclass 22, count 0 2006.201.03:29:25.66#ibcon#flushed, iclass 22, count 0 2006.201.03:29:25.66#ibcon#about to write, iclass 22, count 0 2006.201.03:29:25.66#ibcon#wrote, iclass 22, count 0 2006.201.03:29:25.66#ibcon#about to read 3, iclass 22, count 0 2006.201.03:29:25.70#ibcon#read 3, iclass 22, count 0 2006.201.03:29:25.70#ibcon#about to read 4, iclass 22, count 0 2006.201.03:29:25.70#ibcon#read 4, iclass 22, count 0 2006.201.03:29:25.70#ibcon#about to read 5, iclass 22, count 0 2006.201.03:29:25.70#ibcon#read 5, iclass 22, count 0 2006.201.03:29:25.70#ibcon#about to read 6, iclass 22, count 0 2006.201.03:29:25.70#ibcon#read 6, iclass 22, count 0 2006.201.03:29:25.70#ibcon#end of sib2, iclass 22, count 0 2006.201.03:29:25.70#ibcon#*after write, iclass 22, count 0 2006.201.03:29:25.70#ibcon#*before return 0, iclass 22, count 0 2006.201.03:29:25.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:29:25.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:29:25.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:29:25.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:29:25.70$vck44/vb=1,4 2006.201.03:29:25.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.03:29:25.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.03:29:25.70#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:25.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:29:25.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:29:25.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:29:25.70#ibcon#enter wrdev, iclass 24, count 2 2006.201.03:29:25.70#ibcon#first serial, iclass 24, count 2 2006.201.03:29:25.70#ibcon#enter sib2, iclass 24, count 2 2006.201.03:29:25.70#ibcon#flushed, iclass 24, count 2 2006.201.03:29:25.70#ibcon#about to write, iclass 24, count 2 2006.201.03:29:25.70#ibcon#wrote, iclass 24, count 2 2006.201.03:29:25.70#ibcon#about to read 3, iclass 24, count 2 2006.201.03:29:25.72#ibcon#read 3, iclass 24, count 2 2006.201.03:29:25.72#ibcon#about to read 4, iclass 24, count 2 2006.201.03:29:25.72#ibcon#read 4, iclass 24, count 2 2006.201.03:29:25.72#ibcon#about to read 5, iclass 24, count 2 2006.201.03:29:25.72#ibcon#read 5, iclass 24, count 2 2006.201.03:29:25.72#ibcon#about to read 6, iclass 24, count 2 2006.201.03:29:25.72#ibcon#read 6, iclass 24, count 2 2006.201.03:29:25.72#ibcon#end of sib2, iclass 24, count 2 2006.201.03:29:25.72#ibcon#*mode == 0, iclass 24, count 2 2006.201.03:29:25.72#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.03:29:25.72#ibcon#[27=AT01-04\r\n] 2006.201.03:29:25.72#ibcon#*before write, iclass 24, count 2 2006.201.03:29:25.72#ibcon#enter sib2, iclass 24, count 2 2006.201.03:29:25.72#ibcon#flushed, iclass 24, count 2 2006.201.03:29:25.72#ibcon#about to write, iclass 24, count 2 2006.201.03:29:25.72#ibcon#wrote, iclass 24, count 2 2006.201.03:29:25.72#ibcon#about to read 3, iclass 24, count 2 2006.201.03:29:25.75#ibcon#read 3, iclass 24, count 2 2006.201.03:29:25.75#ibcon#about to read 4, iclass 24, count 2 2006.201.03:29:25.75#ibcon#read 4, iclass 24, count 2 2006.201.03:29:25.75#ibcon#about to read 5, iclass 24, count 2 2006.201.03:29:25.75#ibcon#read 5, iclass 24, count 2 2006.201.03:29:25.75#ibcon#about to read 6, iclass 24, count 2 2006.201.03:29:25.75#ibcon#read 6, iclass 24, count 2 2006.201.03:29:25.75#ibcon#end of sib2, iclass 24, count 2 2006.201.03:29:25.75#ibcon#*after write, iclass 24, count 2 2006.201.03:29:25.75#ibcon#*before return 0, iclass 24, count 2 2006.201.03:29:25.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:29:25.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:29:25.75#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.03:29:25.75#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:25.75#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:29:25.87#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:29:25.87#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:29:25.87#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:29:25.87#ibcon#first serial, iclass 24, count 0 2006.201.03:29:25.87#ibcon#enter sib2, iclass 24, count 0 2006.201.03:29:25.87#ibcon#flushed, iclass 24, count 0 2006.201.03:29:25.87#ibcon#about to write, iclass 24, count 0 2006.201.03:29:25.87#ibcon#wrote, iclass 24, count 0 2006.201.03:29:25.87#ibcon#about to read 3, iclass 24, count 0 2006.201.03:29:25.89#ibcon#read 3, iclass 24, count 0 2006.201.03:29:25.89#ibcon#about to read 4, iclass 24, count 0 2006.201.03:29:25.89#ibcon#read 4, iclass 24, count 0 2006.201.03:29:25.89#ibcon#about to read 5, iclass 24, count 0 2006.201.03:29:25.89#ibcon#read 5, iclass 24, count 0 2006.201.03:29:25.89#ibcon#about to read 6, iclass 24, count 0 2006.201.03:29:25.89#ibcon#read 6, iclass 24, count 0 2006.201.03:29:25.89#ibcon#end of sib2, iclass 24, count 0 2006.201.03:29:25.89#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:29:25.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:29:25.89#ibcon#[27=USB\r\n] 2006.201.03:29:25.89#ibcon#*before write, iclass 24, count 0 2006.201.03:29:25.89#ibcon#enter sib2, iclass 24, count 0 2006.201.03:29:25.89#ibcon#flushed, iclass 24, count 0 2006.201.03:29:25.89#ibcon#about to write, iclass 24, count 0 2006.201.03:29:25.89#ibcon#wrote, iclass 24, count 0 2006.201.03:29:25.89#ibcon#about to read 3, iclass 24, count 0 2006.201.03:29:25.92#ibcon#read 3, iclass 24, count 0 2006.201.03:29:25.92#ibcon#about to read 4, iclass 24, count 0 2006.201.03:29:25.92#ibcon#read 4, iclass 24, count 0 2006.201.03:29:25.92#ibcon#about to read 5, iclass 24, count 0 2006.201.03:29:25.92#ibcon#read 5, iclass 24, count 0 2006.201.03:29:25.92#ibcon#about to read 6, iclass 24, count 0 2006.201.03:29:25.92#ibcon#read 6, iclass 24, count 0 2006.201.03:29:25.92#ibcon#end of sib2, iclass 24, count 0 2006.201.03:29:25.92#ibcon#*after write, iclass 24, count 0 2006.201.03:29:25.92#ibcon#*before return 0, iclass 24, count 0 2006.201.03:29:25.92#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:29:25.92#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:29:25.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:29:25.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:29:25.92$vck44/vblo=2,634.99 2006.201.03:29:25.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.03:29:25.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.03:29:25.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:25.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:25.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:25.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:25.92#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:29:25.92#ibcon#first serial, iclass 26, count 0 2006.201.03:29:25.92#ibcon#enter sib2, iclass 26, count 0 2006.201.03:29:25.92#ibcon#flushed, iclass 26, count 0 2006.201.03:29:25.92#ibcon#about to write, iclass 26, count 0 2006.201.03:29:25.92#ibcon#wrote, iclass 26, count 0 2006.201.03:29:25.92#ibcon#about to read 3, iclass 26, count 0 2006.201.03:29:25.94#ibcon#read 3, iclass 26, count 0 2006.201.03:29:25.94#ibcon#about to read 4, iclass 26, count 0 2006.201.03:29:25.94#ibcon#read 4, iclass 26, count 0 2006.201.03:29:25.94#ibcon#about to read 5, iclass 26, count 0 2006.201.03:29:25.94#ibcon#read 5, iclass 26, count 0 2006.201.03:29:25.94#ibcon#about to read 6, iclass 26, count 0 2006.201.03:29:25.94#ibcon#read 6, iclass 26, count 0 2006.201.03:29:25.94#ibcon#end of sib2, iclass 26, count 0 2006.201.03:29:25.94#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:29:25.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:29:25.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:29:25.94#ibcon#*before write, iclass 26, count 0 2006.201.03:29:25.94#ibcon#enter sib2, iclass 26, count 0 2006.201.03:29:25.94#ibcon#flushed, iclass 26, count 0 2006.201.03:29:25.94#ibcon#about to write, iclass 26, count 0 2006.201.03:29:25.94#ibcon#wrote, iclass 26, count 0 2006.201.03:29:25.94#ibcon#about to read 3, iclass 26, count 0 2006.201.03:29:25.98#ibcon#read 3, iclass 26, count 0 2006.201.03:29:25.98#ibcon#about to read 4, iclass 26, count 0 2006.201.03:29:25.98#ibcon#read 4, iclass 26, count 0 2006.201.03:29:25.98#ibcon#about to read 5, iclass 26, count 0 2006.201.03:29:25.98#ibcon#read 5, iclass 26, count 0 2006.201.03:29:25.98#ibcon#about to read 6, iclass 26, count 0 2006.201.03:29:25.98#ibcon#read 6, iclass 26, count 0 2006.201.03:29:25.98#ibcon#end of sib2, iclass 26, count 0 2006.201.03:29:25.98#ibcon#*after write, iclass 26, count 0 2006.201.03:29:25.98#ibcon#*before return 0, iclass 26, count 0 2006.201.03:29:25.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:25.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:29:25.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:29:25.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:29:25.98$vck44/vb=2,5 2006.201.03:29:25.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.03:29:25.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.03:29:25.98#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:25.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:26.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:26.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:26.04#ibcon#enter wrdev, iclass 28, count 2 2006.201.03:29:26.04#ibcon#first serial, iclass 28, count 2 2006.201.03:29:26.04#ibcon#enter sib2, iclass 28, count 2 2006.201.03:29:26.04#ibcon#flushed, iclass 28, count 2 2006.201.03:29:26.04#ibcon#about to write, iclass 28, count 2 2006.201.03:29:26.04#ibcon#wrote, iclass 28, count 2 2006.201.03:29:26.04#ibcon#about to read 3, iclass 28, count 2 2006.201.03:29:26.06#ibcon#read 3, iclass 28, count 2 2006.201.03:29:26.06#ibcon#about to read 4, iclass 28, count 2 2006.201.03:29:26.06#ibcon#read 4, iclass 28, count 2 2006.201.03:29:26.06#ibcon#about to read 5, iclass 28, count 2 2006.201.03:29:26.06#ibcon#read 5, iclass 28, count 2 2006.201.03:29:26.06#ibcon#about to read 6, iclass 28, count 2 2006.201.03:29:26.06#ibcon#read 6, iclass 28, count 2 2006.201.03:29:26.06#ibcon#end of sib2, iclass 28, count 2 2006.201.03:29:26.06#ibcon#*mode == 0, iclass 28, count 2 2006.201.03:29:26.06#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.03:29:26.06#ibcon#[27=AT02-05\r\n] 2006.201.03:29:26.06#ibcon#*before write, iclass 28, count 2 2006.201.03:29:26.06#ibcon#enter sib2, iclass 28, count 2 2006.201.03:29:26.06#ibcon#flushed, iclass 28, count 2 2006.201.03:29:26.06#ibcon#about to write, iclass 28, count 2 2006.201.03:29:26.06#ibcon#wrote, iclass 28, count 2 2006.201.03:29:26.06#ibcon#about to read 3, iclass 28, count 2 2006.201.03:29:26.09#ibcon#read 3, iclass 28, count 2 2006.201.03:29:26.09#ibcon#about to read 4, iclass 28, count 2 2006.201.03:29:26.09#ibcon#read 4, iclass 28, count 2 2006.201.03:29:26.09#ibcon#about to read 5, iclass 28, count 2 2006.201.03:29:26.09#ibcon#read 5, iclass 28, count 2 2006.201.03:29:26.09#ibcon#about to read 6, iclass 28, count 2 2006.201.03:29:26.09#ibcon#read 6, iclass 28, count 2 2006.201.03:29:26.09#ibcon#end of sib2, iclass 28, count 2 2006.201.03:29:26.09#ibcon#*after write, iclass 28, count 2 2006.201.03:29:26.09#ibcon#*before return 0, iclass 28, count 2 2006.201.03:29:26.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:26.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:29:26.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.03:29:26.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:26.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:26.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:26.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:26.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:29:26.21#ibcon#first serial, iclass 28, count 0 2006.201.03:29:26.21#ibcon#enter sib2, iclass 28, count 0 2006.201.03:29:26.21#ibcon#flushed, iclass 28, count 0 2006.201.03:29:26.21#ibcon#about to write, iclass 28, count 0 2006.201.03:29:26.21#ibcon#wrote, iclass 28, count 0 2006.201.03:29:26.21#ibcon#about to read 3, iclass 28, count 0 2006.201.03:29:26.24#ibcon#read 3, iclass 28, count 0 2006.201.03:29:26.24#ibcon#about to read 4, iclass 28, count 0 2006.201.03:29:26.24#ibcon#read 4, iclass 28, count 0 2006.201.03:29:26.24#ibcon#about to read 5, iclass 28, count 0 2006.201.03:29:26.24#ibcon#read 5, iclass 28, count 0 2006.201.03:29:26.24#ibcon#about to read 6, iclass 28, count 0 2006.201.03:29:26.24#ibcon#read 6, iclass 28, count 0 2006.201.03:29:26.24#ibcon#end of sib2, iclass 28, count 0 2006.201.03:29:26.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:29:26.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:29:26.24#ibcon#[27=USB\r\n] 2006.201.03:29:26.24#ibcon#*before write, iclass 28, count 0 2006.201.03:29:26.24#ibcon#enter sib2, iclass 28, count 0 2006.201.03:29:26.24#ibcon#flushed, iclass 28, count 0 2006.201.03:29:26.24#ibcon#about to write, iclass 28, count 0 2006.201.03:29:26.24#ibcon#wrote, iclass 28, count 0 2006.201.03:29:26.24#ibcon#about to read 3, iclass 28, count 0 2006.201.03:29:26.27#ibcon#read 3, iclass 28, count 0 2006.201.03:29:26.27#ibcon#about to read 4, iclass 28, count 0 2006.201.03:29:26.27#ibcon#read 4, iclass 28, count 0 2006.201.03:29:26.27#ibcon#about to read 5, iclass 28, count 0 2006.201.03:29:26.27#ibcon#read 5, iclass 28, count 0 2006.201.03:29:26.27#ibcon#about to read 6, iclass 28, count 0 2006.201.03:29:26.27#ibcon#read 6, iclass 28, count 0 2006.201.03:29:26.27#ibcon#end of sib2, iclass 28, count 0 2006.201.03:29:26.27#ibcon#*after write, iclass 28, count 0 2006.201.03:29:26.27#ibcon#*before return 0, iclass 28, count 0 2006.201.03:29:26.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:26.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:29:26.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:29:26.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:29:26.27$vck44/vblo=3,649.99 2006.201.03:29:26.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.03:29:26.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.03:29:26.27#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:26.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:26.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:26.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:26.27#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:29:26.27#ibcon#first serial, iclass 30, count 0 2006.201.03:29:26.27#ibcon#enter sib2, iclass 30, count 0 2006.201.03:29:26.27#ibcon#flushed, iclass 30, count 0 2006.201.03:29:26.27#ibcon#about to write, iclass 30, count 0 2006.201.03:29:26.27#ibcon#wrote, iclass 30, count 0 2006.201.03:29:26.27#ibcon#about to read 3, iclass 30, count 0 2006.201.03:29:26.29#ibcon#read 3, iclass 30, count 0 2006.201.03:29:26.29#ibcon#about to read 4, iclass 30, count 0 2006.201.03:29:26.29#ibcon#read 4, iclass 30, count 0 2006.201.03:29:26.29#ibcon#about to read 5, iclass 30, count 0 2006.201.03:29:26.29#ibcon#read 5, iclass 30, count 0 2006.201.03:29:26.29#ibcon#about to read 6, iclass 30, count 0 2006.201.03:29:26.29#ibcon#read 6, iclass 30, count 0 2006.201.03:29:26.29#ibcon#end of sib2, iclass 30, count 0 2006.201.03:29:26.29#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:29:26.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:29:26.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:29:26.29#ibcon#*before write, iclass 30, count 0 2006.201.03:29:26.29#ibcon#enter sib2, iclass 30, count 0 2006.201.03:29:26.29#ibcon#flushed, iclass 30, count 0 2006.201.03:29:26.29#ibcon#about to write, iclass 30, count 0 2006.201.03:29:26.29#ibcon#wrote, iclass 30, count 0 2006.201.03:29:26.29#ibcon#about to read 3, iclass 30, count 0 2006.201.03:29:26.33#ibcon#read 3, iclass 30, count 0 2006.201.03:29:26.33#ibcon#about to read 4, iclass 30, count 0 2006.201.03:29:26.33#ibcon#read 4, iclass 30, count 0 2006.201.03:29:26.33#ibcon#about to read 5, iclass 30, count 0 2006.201.03:29:26.33#ibcon#read 5, iclass 30, count 0 2006.201.03:29:26.33#ibcon#about to read 6, iclass 30, count 0 2006.201.03:29:26.33#ibcon#read 6, iclass 30, count 0 2006.201.03:29:26.33#ibcon#end of sib2, iclass 30, count 0 2006.201.03:29:26.33#ibcon#*after write, iclass 30, count 0 2006.201.03:29:26.33#ibcon#*before return 0, iclass 30, count 0 2006.201.03:29:26.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:26.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:29:26.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:29:26.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:29:26.33$vck44/vb=3,4 2006.201.03:29:26.33#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.03:29:26.33#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.03:29:26.33#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:26.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:26.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:26.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:26.39#ibcon#enter wrdev, iclass 32, count 2 2006.201.03:29:26.39#ibcon#first serial, iclass 32, count 2 2006.201.03:29:26.39#ibcon#enter sib2, iclass 32, count 2 2006.201.03:29:26.39#ibcon#flushed, iclass 32, count 2 2006.201.03:29:26.39#ibcon#about to write, iclass 32, count 2 2006.201.03:29:26.39#ibcon#wrote, iclass 32, count 2 2006.201.03:29:26.39#ibcon#about to read 3, iclass 32, count 2 2006.201.03:29:26.41#ibcon#read 3, iclass 32, count 2 2006.201.03:29:26.41#ibcon#about to read 4, iclass 32, count 2 2006.201.03:29:26.41#ibcon#read 4, iclass 32, count 2 2006.201.03:29:26.41#ibcon#about to read 5, iclass 32, count 2 2006.201.03:29:26.41#ibcon#read 5, iclass 32, count 2 2006.201.03:29:26.41#ibcon#about to read 6, iclass 32, count 2 2006.201.03:29:26.41#ibcon#read 6, iclass 32, count 2 2006.201.03:29:26.41#ibcon#end of sib2, iclass 32, count 2 2006.201.03:29:26.41#ibcon#*mode == 0, iclass 32, count 2 2006.201.03:29:26.41#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.03:29:26.41#ibcon#[27=AT03-04\r\n] 2006.201.03:29:26.41#ibcon#*before write, iclass 32, count 2 2006.201.03:29:26.41#ibcon#enter sib2, iclass 32, count 2 2006.201.03:29:26.41#ibcon#flushed, iclass 32, count 2 2006.201.03:29:26.41#ibcon#about to write, iclass 32, count 2 2006.201.03:29:26.41#ibcon#wrote, iclass 32, count 2 2006.201.03:29:26.41#ibcon#about to read 3, iclass 32, count 2 2006.201.03:29:26.44#ibcon#read 3, iclass 32, count 2 2006.201.03:29:26.44#ibcon#about to read 4, iclass 32, count 2 2006.201.03:29:26.44#ibcon#read 4, iclass 32, count 2 2006.201.03:29:26.44#ibcon#about to read 5, iclass 32, count 2 2006.201.03:29:26.44#ibcon#read 5, iclass 32, count 2 2006.201.03:29:26.44#ibcon#about to read 6, iclass 32, count 2 2006.201.03:29:26.44#ibcon#read 6, iclass 32, count 2 2006.201.03:29:26.44#ibcon#end of sib2, iclass 32, count 2 2006.201.03:29:26.44#ibcon#*after write, iclass 32, count 2 2006.201.03:29:26.44#ibcon#*before return 0, iclass 32, count 2 2006.201.03:29:26.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:26.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:29:26.44#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.03:29:26.44#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:26.44#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:26.56#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:26.56#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:26.56#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:29:26.56#ibcon#first serial, iclass 32, count 0 2006.201.03:29:26.56#ibcon#enter sib2, iclass 32, count 0 2006.201.03:29:26.56#ibcon#flushed, iclass 32, count 0 2006.201.03:29:26.56#ibcon#about to write, iclass 32, count 0 2006.201.03:29:26.56#ibcon#wrote, iclass 32, count 0 2006.201.03:29:26.56#ibcon#about to read 3, iclass 32, count 0 2006.201.03:29:26.58#ibcon#read 3, iclass 32, count 0 2006.201.03:29:26.58#ibcon#about to read 4, iclass 32, count 0 2006.201.03:29:26.58#ibcon#read 4, iclass 32, count 0 2006.201.03:29:26.58#ibcon#about to read 5, iclass 32, count 0 2006.201.03:29:26.58#ibcon#read 5, iclass 32, count 0 2006.201.03:29:26.58#ibcon#about to read 6, iclass 32, count 0 2006.201.03:29:26.58#ibcon#read 6, iclass 32, count 0 2006.201.03:29:26.58#ibcon#end of sib2, iclass 32, count 0 2006.201.03:29:26.58#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:29:26.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:29:26.58#ibcon#[27=USB\r\n] 2006.201.03:29:26.58#ibcon#*before write, iclass 32, count 0 2006.201.03:29:26.58#ibcon#enter sib2, iclass 32, count 0 2006.201.03:29:26.58#ibcon#flushed, iclass 32, count 0 2006.201.03:29:26.58#ibcon#about to write, iclass 32, count 0 2006.201.03:29:26.58#ibcon#wrote, iclass 32, count 0 2006.201.03:29:26.58#ibcon#about to read 3, iclass 32, count 0 2006.201.03:29:26.61#ibcon#read 3, iclass 32, count 0 2006.201.03:29:26.61#ibcon#about to read 4, iclass 32, count 0 2006.201.03:29:26.61#ibcon#read 4, iclass 32, count 0 2006.201.03:29:26.61#ibcon#about to read 5, iclass 32, count 0 2006.201.03:29:26.61#ibcon#read 5, iclass 32, count 0 2006.201.03:29:26.61#ibcon#about to read 6, iclass 32, count 0 2006.201.03:29:26.61#ibcon#read 6, iclass 32, count 0 2006.201.03:29:26.61#ibcon#end of sib2, iclass 32, count 0 2006.201.03:29:26.61#ibcon#*after write, iclass 32, count 0 2006.201.03:29:26.61#ibcon#*before return 0, iclass 32, count 0 2006.201.03:29:26.61#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:26.61#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:29:26.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:29:26.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:29:26.61$vck44/vblo=4,679.99 2006.201.03:29:26.61#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.03:29:26.61#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.03:29:26.61#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:26.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:26.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:26.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:26.61#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:29:26.61#ibcon#first serial, iclass 34, count 0 2006.201.03:29:26.61#ibcon#enter sib2, iclass 34, count 0 2006.201.03:29:26.61#ibcon#flushed, iclass 34, count 0 2006.201.03:29:26.61#ibcon#about to write, iclass 34, count 0 2006.201.03:29:26.61#ibcon#wrote, iclass 34, count 0 2006.201.03:29:26.61#ibcon#about to read 3, iclass 34, count 0 2006.201.03:29:26.63#ibcon#read 3, iclass 34, count 0 2006.201.03:29:26.63#ibcon#about to read 4, iclass 34, count 0 2006.201.03:29:26.63#ibcon#read 4, iclass 34, count 0 2006.201.03:29:26.63#ibcon#about to read 5, iclass 34, count 0 2006.201.03:29:26.63#ibcon#read 5, iclass 34, count 0 2006.201.03:29:26.63#ibcon#about to read 6, iclass 34, count 0 2006.201.03:29:26.63#ibcon#read 6, iclass 34, count 0 2006.201.03:29:26.63#ibcon#end of sib2, iclass 34, count 0 2006.201.03:29:26.63#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:29:26.63#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:29:26.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:29:26.63#ibcon#*before write, iclass 34, count 0 2006.201.03:29:26.63#ibcon#enter sib2, iclass 34, count 0 2006.201.03:29:26.63#ibcon#flushed, iclass 34, count 0 2006.201.03:29:26.63#ibcon#about to write, iclass 34, count 0 2006.201.03:29:26.63#ibcon#wrote, iclass 34, count 0 2006.201.03:29:26.63#ibcon#about to read 3, iclass 34, count 0 2006.201.03:29:26.67#ibcon#read 3, iclass 34, count 0 2006.201.03:29:26.67#ibcon#about to read 4, iclass 34, count 0 2006.201.03:29:26.67#ibcon#read 4, iclass 34, count 0 2006.201.03:29:26.67#ibcon#about to read 5, iclass 34, count 0 2006.201.03:29:26.67#ibcon#read 5, iclass 34, count 0 2006.201.03:29:26.67#ibcon#about to read 6, iclass 34, count 0 2006.201.03:29:26.67#ibcon#read 6, iclass 34, count 0 2006.201.03:29:26.67#ibcon#end of sib2, iclass 34, count 0 2006.201.03:29:26.67#ibcon#*after write, iclass 34, count 0 2006.201.03:29:26.67#ibcon#*before return 0, iclass 34, count 0 2006.201.03:29:26.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:26.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:29:26.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:29:26.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:29:26.67$vck44/vb=4,5 2006.201.03:29:26.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.03:29:26.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.03:29:26.67#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:26.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:26.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:26.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:26.73#ibcon#enter wrdev, iclass 36, count 2 2006.201.03:29:26.73#ibcon#first serial, iclass 36, count 2 2006.201.03:29:26.73#ibcon#enter sib2, iclass 36, count 2 2006.201.03:29:26.73#ibcon#flushed, iclass 36, count 2 2006.201.03:29:26.73#ibcon#about to write, iclass 36, count 2 2006.201.03:29:26.73#ibcon#wrote, iclass 36, count 2 2006.201.03:29:26.73#ibcon#about to read 3, iclass 36, count 2 2006.201.03:29:26.75#ibcon#read 3, iclass 36, count 2 2006.201.03:29:26.75#ibcon#about to read 4, iclass 36, count 2 2006.201.03:29:26.75#ibcon#read 4, iclass 36, count 2 2006.201.03:29:26.75#ibcon#about to read 5, iclass 36, count 2 2006.201.03:29:26.75#ibcon#read 5, iclass 36, count 2 2006.201.03:29:26.75#ibcon#about to read 6, iclass 36, count 2 2006.201.03:29:26.75#ibcon#read 6, iclass 36, count 2 2006.201.03:29:26.75#ibcon#end of sib2, iclass 36, count 2 2006.201.03:29:26.75#ibcon#*mode == 0, iclass 36, count 2 2006.201.03:29:26.75#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.03:29:26.75#ibcon#[27=AT04-05\r\n] 2006.201.03:29:26.75#ibcon#*before write, iclass 36, count 2 2006.201.03:29:26.75#ibcon#enter sib2, iclass 36, count 2 2006.201.03:29:26.75#ibcon#flushed, iclass 36, count 2 2006.201.03:29:26.75#ibcon#about to write, iclass 36, count 2 2006.201.03:29:26.75#ibcon#wrote, iclass 36, count 2 2006.201.03:29:26.75#ibcon#about to read 3, iclass 36, count 2 2006.201.03:29:26.78#ibcon#read 3, iclass 36, count 2 2006.201.03:29:26.78#ibcon#about to read 4, iclass 36, count 2 2006.201.03:29:26.78#ibcon#read 4, iclass 36, count 2 2006.201.03:29:26.78#ibcon#about to read 5, iclass 36, count 2 2006.201.03:29:26.78#ibcon#read 5, iclass 36, count 2 2006.201.03:29:26.78#ibcon#about to read 6, iclass 36, count 2 2006.201.03:29:26.78#ibcon#read 6, iclass 36, count 2 2006.201.03:29:26.78#ibcon#end of sib2, iclass 36, count 2 2006.201.03:29:26.78#ibcon#*after write, iclass 36, count 2 2006.201.03:29:26.78#ibcon#*before return 0, iclass 36, count 2 2006.201.03:29:26.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:26.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:29:26.78#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.03:29:26.78#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:26.78#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:26.90#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:26.90#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:26.90#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:29:26.90#ibcon#first serial, iclass 36, count 0 2006.201.03:29:26.90#ibcon#enter sib2, iclass 36, count 0 2006.201.03:29:26.90#ibcon#flushed, iclass 36, count 0 2006.201.03:29:26.90#ibcon#about to write, iclass 36, count 0 2006.201.03:29:26.90#ibcon#wrote, iclass 36, count 0 2006.201.03:29:26.90#ibcon#about to read 3, iclass 36, count 0 2006.201.03:29:26.92#ibcon#read 3, iclass 36, count 0 2006.201.03:29:26.92#ibcon#about to read 4, iclass 36, count 0 2006.201.03:29:26.92#ibcon#read 4, iclass 36, count 0 2006.201.03:29:26.92#ibcon#about to read 5, iclass 36, count 0 2006.201.03:29:26.92#ibcon#read 5, iclass 36, count 0 2006.201.03:29:26.92#ibcon#about to read 6, iclass 36, count 0 2006.201.03:29:26.92#ibcon#read 6, iclass 36, count 0 2006.201.03:29:26.92#ibcon#end of sib2, iclass 36, count 0 2006.201.03:29:26.92#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:29:26.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:29:26.92#ibcon#[27=USB\r\n] 2006.201.03:29:26.92#ibcon#*before write, iclass 36, count 0 2006.201.03:29:26.92#ibcon#enter sib2, iclass 36, count 0 2006.201.03:29:26.92#ibcon#flushed, iclass 36, count 0 2006.201.03:29:26.92#ibcon#about to write, iclass 36, count 0 2006.201.03:29:26.92#ibcon#wrote, iclass 36, count 0 2006.201.03:29:26.92#ibcon#about to read 3, iclass 36, count 0 2006.201.03:29:26.95#ibcon#read 3, iclass 36, count 0 2006.201.03:29:26.95#ibcon#about to read 4, iclass 36, count 0 2006.201.03:29:26.95#ibcon#read 4, iclass 36, count 0 2006.201.03:29:26.95#ibcon#about to read 5, iclass 36, count 0 2006.201.03:29:26.95#ibcon#read 5, iclass 36, count 0 2006.201.03:29:26.95#ibcon#about to read 6, iclass 36, count 0 2006.201.03:29:26.95#ibcon#read 6, iclass 36, count 0 2006.201.03:29:26.95#ibcon#end of sib2, iclass 36, count 0 2006.201.03:29:26.95#ibcon#*after write, iclass 36, count 0 2006.201.03:29:26.95#ibcon#*before return 0, iclass 36, count 0 2006.201.03:29:26.95#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:26.95#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:29:26.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:29:26.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:29:26.95$vck44/vblo=5,709.99 2006.201.03:29:26.95#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.03:29:26.95#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.03:29:26.95#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:26.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:26.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:26.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:26.95#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:29:26.95#ibcon#first serial, iclass 38, count 0 2006.201.03:29:26.95#ibcon#enter sib2, iclass 38, count 0 2006.201.03:29:26.95#ibcon#flushed, iclass 38, count 0 2006.201.03:29:26.95#ibcon#about to write, iclass 38, count 0 2006.201.03:29:26.95#ibcon#wrote, iclass 38, count 0 2006.201.03:29:26.95#ibcon#about to read 3, iclass 38, count 0 2006.201.03:29:26.97#ibcon#read 3, iclass 38, count 0 2006.201.03:29:26.97#ibcon#about to read 4, iclass 38, count 0 2006.201.03:29:26.97#ibcon#read 4, iclass 38, count 0 2006.201.03:29:26.97#ibcon#about to read 5, iclass 38, count 0 2006.201.03:29:26.97#ibcon#read 5, iclass 38, count 0 2006.201.03:29:26.97#ibcon#about to read 6, iclass 38, count 0 2006.201.03:29:26.97#ibcon#read 6, iclass 38, count 0 2006.201.03:29:26.97#ibcon#end of sib2, iclass 38, count 0 2006.201.03:29:26.97#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:29:26.97#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:29:26.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:29:26.97#ibcon#*before write, iclass 38, count 0 2006.201.03:29:26.97#ibcon#enter sib2, iclass 38, count 0 2006.201.03:29:26.97#ibcon#flushed, iclass 38, count 0 2006.201.03:29:26.97#ibcon#about to write, iclass 38, count 0 2006.201.03:29:26.97#ibcon#wrote, iclass 38, count 0 2006.201.03:29:26.97#ibcon#about to read 3, iclass 38, count 0 2006.201.03:29:27.02#ibcon#read 3, iclass 38, count 0 2006.201.03:29:27.02#ibcon#about to read 4, iclass 38, count 0 2006.201.03:29:27.02#ibcon#read 4, iclass 38, count 0 2006.201.03:29:27.02#ibcon#about to read 5, iclass 38, count 0 2006.201.03:29:27.02#ibcon#read 5, iclass 38, count 0 2006.201.03:29:27.02#ibcon#about to read 6, iclass 38, count 0 2006.201.03:29:27.02#ibcon#read 6, iclass 38, count 0 2006.201.03:29:27.02#ibcon#end of sib2, iclass 38, count 0 2006.201.03:29:27.02#ibcon#*after write, iclass 38, count 0 2006.201.03:29:27.02#ibcon#*before return 0, iclass 38, count 0 2006.201.03:29:27.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:27.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:29:27.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:29:27.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:29:27.02$vck44/vb=5,4 2006.201.03:29:27.02#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.03:29:27.02#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.03:29:27.02#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:27.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:27.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:27.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:27.07#ibcon#enter wrdev, iclass 40, count 2 2006.201.03:29:27.07#ibcon#first serial, iclass 40, count 2 2006.201.03:29:27.07#ibcon#enter sib2, iclass 40, count 2 2006.201.03:29:27.07#ibcon#flushed, iclass 40, count 2 2006.201.03:29:27.07#ibcon#about to write, iclass 40, count 2 2006.201.03:29:27.07#ibcon#wrote, iclass 40, count 2 2006.201.03:29:27.07#ibcon#about to read 3, iclass 40, count 2 2006.201.03:29:27.09#ibcon#read 3, iclass 40, count 2 2006.201.03:29:27.09#ibcon#about to read 4, iclass 40, count 2 2006.201.03:29:27.09#ibcon#read 4, iclass 40, count 2 2006.201.03:29:27.09#ibcon#about to read 5, iclass 40, count 2 2006.201.03:29:27.09#ibcon#read 5, iclass 40, count 2 2006.201.03:29:27.09#ibcon#about to read 6, iclass 40, count 2 2006.201.03:29:27.09#ibcon#read 6, iclass 40, count 2 2006.201.03:29:27.09#ibcon#end of sib2, iclass 40, count 2 2006.201.03:29:27.09#ibcon#*mode == 0, iclass 40, count 2 2006.201.03:29:27.09#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.03:29:27.09#ibcon#[27=AT05-04\r\n] 2006.201.03:29:27.09#ibcon#*before write, iclass 40, count 2 2006.201.03:29:27.09#ibcon#enter sib2, iclass 40, count 2 2006.201.03:29:27.09#ibcon#flushed, iclass 40, count 2 2006.201.03:29:27.09#ibcon#about to write, iclass 40, count 2 2006.201.03:29:27.09#ibcon#wrote, iclass 40, count 2 2006.201.03:29:27.09#ibcon#about to read 3, iclass 40, count 2 2006.201.03:29:27.12#ibcon#read 3, iclass 40, count 2 2006.201.03:29:27.12#ibcon#about to read 4, iclass 40, count 2 2006.201.03:29:27.12#ibcon#read 4, iclass 40, count 2 2006.201.03:29:27.12#ibcon#about to read 5, iclass 40, count 2 2006.201.03:29:27.12#ibcon#read 5, iclass 40, count 2 2006.201.03:29:27.12#ibcon#about to read 6, iclass 40, count 2 2006.201.03:29:27.12#ibcon#read 6, iclass 40, count 2 2006.201.03:29:27.12#ibcon#end of sib2, iclass 40, count 2 2006.201.03:29:27.12#ibcon#*after write, iclass 40, count 2 2006.201.03:29:27.12#ibcon#*before return 0, iclass 40, count 2 2006.201.03:29:27.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:27.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:29:27.12#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.03:29:27.12#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:27.12#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:27.24#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:27.24#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:27.24#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:29:27.24#ibcon#first serial, iclass 40, count 0 2006.201.03:29:27.24#ibcon#enter sib2, iclass 40, count 0 2006.201.03:29:27.24#ibcon#flushed, iclass 40, count 0 2006.201.03:29:27.24#ibcon#about to write, iclass 40, count 0 2006.201.03:29:27.24#ibcon#wrote, iclass 40, count 0 2006.201.03:29:27.24#ibcon#about to read 3, iclass 40, count 0 2006.201.03:29:27.26#ibcon#read 3, iclass 40, count 0 2006.201.03:29:27.26#ibcon#about to read 4, iclass 40, count 0 2006.201.03:29:27.26#ibcon#read 4, iclass 40, count 0 2006.201.03:29:27.26#ibcon#about to read 5, iclass 40, count 0 2006.201.03:29:27.26#ibcon#read 5, iclass 40, count 0 2006.201.03:29:27.26#ibcon#about to read 6, iclass 40, count 0 2006.201.03:29:27.26#ibcon#read 6, iclass 40, count 0 2006.201.03:29:27.26#ibcon#end of sib2, iclass 40, count 0 2006.201.03:29:27.26#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:29:27.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:29:27.26#ibcon#[27=USB\r\n] 2006.201.03:29:27.26#ibcon#*before write, iclass 40, count 0 2006.201.03:29:27.26#ibcon#enter sib2, iclass 40, count 0 2006.201.03:29:27.26#ibcon#flushed, iclass 40, count 0 2006.201.03:29:27.26#ibcon#about to write, iclass 40, count 0 2006.201.03:29:27.26#ibcon#wrote, iclass 40, count 0 2006.201.03:29:27.26#ibcon#about to read 3, iclass 40, count 0 2006.201.03:29:27.29#ibcon#read 3, iclass 40, count 0 2006.201.03:29:27.29#ibcon#about to read 4, iclass 40, count 0 2006.201.03:29:27.29#ibcon#read 4, iclass 40, count 0 2006.201.03:29:27.29#ibcon#about to read 5, iclass 40, count 0 2006.201.03:29:27.29#ibcon#read 5, iclass 40, count 0 2006.201.03:29:27.29#ibcon#about to read 6, iclass 40, count 0 2006.201.03:29:27.29#ibcon#read 6, iclass 40, count 0 2006.201.03:29:27.29#ibcon#end of sib2, iclass 40, count 0 2006.201.03:29:27.29#ibcon#*after write, iclass 40, count 0 2006.201.03:29:27.29#ibcon#*before return 0, iclass 40, count 0 2006.201.03:29:27.29#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:27.29#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:29:27.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:29:27.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:29:27.29$vck44/vblo=6,719.99 2006.201.03:29:27.29#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.03:29:27.29#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.03:29:27.29#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:27.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:27.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:27.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:27.29#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:29:27.29#ibcon#first serial, iclass 4, count 0 2006.201.03:29:27.29#ibcon#enter sib2, iclass 4, count 0 2006.201.03:29:27.29#ibcon#flushed, iclass 4, count 0 2006.201.03:29:27.29#ibcon#about to write, iclass 4, count 0 2006.201.03:29:27.29#ibcon#wrote, iclass 4, count 0 2006.201.03:29:27.29#ibcon#about to read 3, iclass 4, count 0 2006.201.03:29:27.31#ibcon#read 3, iclass 4, count 0 2006.201.03:29:27.31#ibcon#about to read 4, iclass 4, count 0 2006.201.03:29:27.31#ibcon#read 4, iclass 4, count 0 2006.201.03:29:27.31#ibcon#about to read 5, iclass 4, count 0 2006.201.03:29:27.31#ibcon#read 5, iclass 4, count 0 2006.201.03:29:27.31#ibcon#about to read 6, iclass 4, count 0 2006.201.03:29:27.31#ibcon#read 6, iclass 4, count 0 2006.201.03:29:27.31#ibcon#end of sib2, iclass 4, count 0 2006.201.03:29:27.31#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:29:27.31#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:29:27.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:29:27.31#ibcon#*before write, iclass 4, count 0 2006.201.03:29:27.31#ibcon#enter sib2, iclass 4, count 0 2006.201.03:29:27.31#ibcon#flushed, iclass 4, count 0 2006.201.03:29:27.31#ibcon#about to write, iclass 4, count 0 2006.201.03:29:27.31#ibcon#wrote, iclass 4, count 0 2006.201.03:29:27.31#ibcon#about to read 3, iclass 4, count 0 2006.201.03:29:27.35#ibcon#read 3, iclass 4, count 0 2006.201.03:29:27.35#ibcon#about to read 4, iclass 4, count 0 2006.201.03:29:27.35#ibcon#read 4, iclass 4, count 0 2006.201.03:29:27.35#ibcon#about to read 5, iclass 4, count 0 2006.201.03:29:27.35#ibcon#read 5, iclass 4, count 0 2006.201.03:29:27.35#ibcon#about to read 6, iclass 4, count 0 2006.201.03:29:27.35#ibcon#read 6, iclass 4, count 0 2006.201.03:29:27.35#ibcon#end of sib2, iclass 4, count 0 2006.201.03:29:27.35#ibcon#*after write, iclass 4, count 0 2006.201.03:29:27.35#ibcon#*before return 0, iclass 4, count 0 2006.201.03:29:27.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:27.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:29:27.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:29:27.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:29:27.35$vck44/vb=6,4 2006.201.03:29:27.35#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.03:29:27.35#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.03:29:27.35#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:27.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:27.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:27.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:27.41#ibcon#enter wrdev, iclass 6, count 2 2006.201.03:29:27.41#ibcon#first serial, iclass 6, count 2 2006.201.03:29:27.41#ibcon#enter sib2, iclass 6, count 2 2006.201.03:29:27.41#ibcon#flushed, iclass 6, count 2 2006.201.03:29:27.41#ibcon#about to write, iclass 6, count 2 2006.201.03:29:27.41#ibcon#wrote, iclass 6, count 2 2006.201.03:29:27.41#ibcon#about to read 3, iclass 6, count 2 2006.201.03:29:27.43#ibcon#read 3, iclass 6, count 2 2006.201.03:29:27.43#ibcon#about to read 4, iclass 6, count 2 2006.201.03:29:27.43#ibcon#read 4, iclass 6, count 2 2006.201.03:29:27.43#ibcon#about to read 5, iclass 6, count 2 2006.201.03:29:27.43#ibcon#read 5, iclass 6, count 2 2006.201.03:29:27.43#ibcon#about to read 6, iclass 6, count 2 2006.201.03:29:27.43#ibcon#read 6, iclass 6, count 2 2006.201.03:29:27.43#ibcon#end of sib2, iclass 6, count 2 2006.201.03:29:27.43#ibcon#*mode == 0, iclass 6, count 2 2006.201.03:29:27.43#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.03:29:27.43#ibcon#[27=AT06-04\r\n] 2006.201.03:29:27.43#ibcon#*before write, iclass 6, count 2 2006.201.03:29:27.43#ibcon#enter sib2, iclass 6, count 2 2006.201.03:29:27.43#ibcon#flushed, iclass 6, count 2 2006.201.03:29:27.43#ibcon#about to write, iclass 6, count 2 2006.201.03:29:27.43#ibcon#wrote, iclass 6, count 2 2006.201.03:29:27.43#ibcon#about to read 3, iclass 6, count 2 2006.201.03:29:27.46#ibcon#read 3, iclass 6, count 2 2006.201.03:29:27.46#ibcon#about to read 4, iclass 6, count 2 2006.201.03:29:27.46#ibcon#read 4, iclass 6, count 2 2006.201.03:29:27.46#ibcon#about to read 5, iclass 6, count 2 2006.201.03:29:27.46#ibcon#read 5, iclass 6, count 2 2006.201.03:29:27.46#ibcon#about to read 6, iclass 6, count 2 2006.201.03:29:27.46#ibcon#read 6, iclass 6, count 2 2006.201.03:29:27.46#ibcon#end of sib2, iclass 6, count 2 2006.201.03:29:27.46#ibcon#*after write, iclass 6, count 2 2006.201.03:29:27.46#ibcon#*before return 0, iclass 6, count 2 2006.201.03:29:27.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:27.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:29:27.46#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.03:29:27.46#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:27.46#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:27.58#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:27.58#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:27.58#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:29:27.58#ibcon#first serial, iclass 6, count 0 2006.201.03:29:27.58#ibcon#enter sib2, iclass 6, count 0 2006.201.03:29:27.58#ibcon#flushed, iclass 6, count 0 2006.201.03:29:27.58#ibcon#about to write, iclass 6, count 0 2006.201.03:29:27.58#ibcon#wrote, iclass 6, count 0 2006.201.03:29:27.58#ibcon#about to read 3, iclass 6, count 0 2006.201.03:29:27.60#ibcon#read 3, iclass 6, count 0 2006.201.03:29:27.60#ibcon#about to read 4, iclass 6, count 0 2006.201.03:29:27.60#ibcon#read 4, iclass 6, count 0 2006.201.03:29:27.60#ibcon#about to read 5, iclass 6, count 0 2006.201.03:29:27.60#ibcon#read 5, iclass 6, count 0 2006.201.03:29:27.60#ibcon#about to read 6, iclass 6, count 0 2006.201.03:29:27.60#ibcon#read 6, iclass 6, count 0 2006.201.03:29:27.60#ibcon#end of sib2, iclass 6, count 0 2006.201.03:29:27.60#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:29:27.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:29:27.60#ibcon#[27=USB\r\n] 2006.201.03:29:27.60#ibcon#*before write, iclass 6, count 0 2006.201.03:29:27.60#ibcon#enter sib2, iclass 6, count 0 2006.201.03:29:27.60#ibcon#flushed, iclass 6, count 0 2006.201.03:29:27.60#ibcon#about to write, iclass 6, count 0 2006.201.03:29:27.60#ibcon#wrote, iclass 6, count 0 2006.201.03:29:27.60#ibcon#about to read 3, iclass 6, count 0 2006.201.03:29:27.63#ibcon#read 3, iclass 6, count 0 2006.201.03:29:27.63#ibcon#about to read 4, iclass 6, count 0 2006.201.03:29:27.63#ibcon#read 4, iclass 6, count 0 2006.201.03:29:27.63#ibcon#about to read 5, iclass 6, count 0 2006.201.03:29:27.63#ibcon#read 5, iclass 6, count 0 2006.201.03:29:27.63#ibcon#about to read 6, iclass 6, count 0 2006.201.03:29:27.63#ibcon#read 6, iclass 6, count 0 2006.201.03:29:27.63#ibcon#end of sib2, iclass 6, count 0 2006.201.03:29:27.63#ibcon#*after write, iclass 6, count 0 2006.201.03:29:27.63#ibcon#*before return 0, iclass 6, count 0 2006.201.03:29:27.63#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:27.63#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:29:27.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:29:27.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:29:27.63$vck44/vblo=7,734.99 2006.201.03:29:27.63#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.03:29:27.63#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.03:29:27.63#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:27.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:27.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:27.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:27.63#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:29:27.63#ibcon#first serial, iclass 10, count 0 2006.201.03:29:27.63#ibcon#enter sib2, iclass 10, count 0 2006.201.03:29:27.63#ibcon#flushed, iclass 10, count 0 2006.201.03:29:27.63#ibcon#about to write, iclass 10, count 0 2006.201.03:29:27.63#ibcon#wrote, iclass 10, count 0 2006.201.03:29:27.63#ibcon#about to read 3, iclass 10, count 0 2006.201.03:29:27.65#ibcon#read 3, iclass 10, count 0 2006.201.03:29:27.65#ibcon#about to read 4, iclass 10, count 0 2006.201.03:29:27.65#ibcon#read 4, iclass 10, count 0 2006.201.03:29:27.65#ibcon#about to read 5, iclass 10, count 0 2006.201.03:29:27.65#ibcon#read 5, iclass 10, count 0 2006.201.03:29:27.65#ibcon#about to read 6, iclass 10, count 0 2006.201.03:29:27.65#ibcon#read 6, iclass 10, count 0 2006.201.03:29:27.65#ibcon#end of sib2, iclass 10, count 0 2006.201.03:29:27.65#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:29:27.65#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:29:27.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:29:27.65#ibcon#*before write, iclass 10, count 0 2006.201.03:29:27.65#ibcon#enter sib2, iclass 10, count 0 2006.201.03:29:27.65#ibcon#flushed, iclass 10, count 0 2006.201.03:29:27.65#ibcon#about to write, iclass 10, count 0 2006.201.03:29:27.65#ibcon#wrote, iclass 10, count 0 2006.201.03:29:27.65#ibcon#about to read 3, iclass 10, count 0 2006.201.03:29:27.69#ibcon#read 3, iclass 10, count 0 2006.201.03:29:27.69#ibcon#about to read 4, iclass 10, count 0 2006.201.03:29:27.69#ibcon#read 4, iclass 10, count 0 2006.201.03:29:27.69#ibcon#about to read 5, iclass 10, count 0 2006.201.03:29:27.69#ibcon#read 5, iclass 10, count 0 2006.201.03:29:27.69#ibcon#about to read 6, iclass 10, count 0 2006.201.03:29:27.69#ibcon#read 6, iclass 10, count 0 2006.201.03:29:27.69#ibcon#end of sib2, iclass 10, count 0 2006.201.03:29:27.69#ibcon#*after write, iclass 10, count 0 2006.201.03:29:27.69#ibcon#*before return 0, iclass 10, count 0 2006.201.03:29:27.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:27.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:29:27.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:29:27.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:29:27.69$vck44/vb=7,4 2006.201.03:29:27.69#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.03:29:27.69#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.03:29:27.69#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:27.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:27.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:27.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:27.75#ibcon#enter wrdev, iclass 12, count 2 2006.201.03:29:27.75#ibcon#first serial, iclass 12, count 2 2006.201.03:29:27.75#ibcon#enter sib2, iclass 12, count 2 2006.201.03:29:27.75#ibcon#flushed, iclass 12, count 2 2006.201.03:29:27.75#ibcon#about to write, iclass 12, count 2 2006.201.03:29:27.75#ibcon#wrote, iclass 12, count 2 2006.201.03:29:27.75#ibcon#about to read 3, iclass 12, count 2 2006.201.03:29:27.77#ibcon#read 3, iclass 12, count 2 2006.201.03:29:27.77#ibcon#about to read 4, iclass 12, count 2 2006.201.03:29:27.77#ibcon#read 4, iclass 12, count 2 2006.201.03:29:27.77#ibcon#about to read 5, iclass 12, count 2 2006.201.03:29:27.77#ibcon#read 5, iclass 12, count 2 2006.201.03:29:27.77#ibcon#about to read 6, iclass 12, count 2 2006.201.03:29:27.77#ibcon#read 6, iclass 12, count 2 2006.201.03:29:27.77#ibcon#end of sib2, iclass 12, count 2 2006.201.03:29:27.77#ibcon#*mode == 0, iclass 12, count 2 2006.201.03:29:27.77#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.03:29:27.77#ibcon#[27=AT07-04\r\n] 2006.201.03:29:27.77#ibcon#*before write, iclass 12, count 2 2006.201.03:29:27.77#ibcon#enter sib2, iclass 12, count 2 2006.201.03:29:27.77#ibcon#flushed, iclass 12, count 2 2006.201.03:29:27.77#ibcon#about to write, iclass 12, count 2 2006.201.03:29:27.77#ibcon#wrote, iclass 12, count 2 2006.201.03:29:27.77#ibcon#about to read 3, iclass 12, count 2 2006.201.03:29:27.80#ibcon#read 3, iclass 12, count 2 2006.201.03:29:27.80#ibcon#about to read 4, iclass 12, count 2 2006.201.03:29:27.80#ibcon#read 4, iclass 12, count 2 2006.201.03:29:27.80#ibcon#about to read 5, iclass 12, count 2 2006.201.03:29:27.80#ibcon#read 5, iclass 12, count 2 2006.201.03:29:27.80#ibcon#about to read 6, iclass 12, count 2 2006.201.03:29:27.80#ibcon#read 6, iclass 12, count 2 2006.201.03:29:27.80#ibcon#end of sib2, iclass 12, count 2 2006.201.03:29:27.80#ibcon#*after write, iclass 12, count 2 2006.201.03:29:27.80#ibcon#*before return 0, iclass 12, count 2 2006.201.03:29:27.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:27.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:29:27.80#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.03:29:27.80#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:27.80#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:27.92#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:27.92#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:27.92#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:29:27.92#ibcon#first serial, iclass 12, count 0 2006.201.03:29:27.92#ibcon#enter sib2, iclass 12, count 0 2006.201.03:29:27.92#ibcon#flushed, iclass 12, count 0 2006.201.03:29:27.92#ibcon#about to write, iclass 12, count 0 2006.201.03:29:27.92#ibcon#wrote, iclass 12, count 0 2006.201.03:29:27.92#ibcon#about to read 3, iclass 12, count 0 2006.201.03:29:27.94#ibcon#read 3, iclass 12, count 0 2006.201.03:29:27.94#ibcon#about to read 4, iclass 12, count 0 2006.201.03:29:27.94#ibcon#read 4, iclass 12, count 0 2006.201.03:29:27.94#ibcon#about to read 5, iclass 12, count 0 2006.201.03:29:27.94#ibcon#read 5, iclass 12, count 0 2006.201.03:29:27.94#ibcon#about to read 6, iclass 12, count 0 2006.201.03:29:27.94#ibcon#read 6, iclass 12, count 0 2006.201.03:29:27.94#ibcon#end of sib2, iclass 12, count 0 2006.201.03:29:27.94#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:29:27.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:29:27.94#ibcon#[27=USB\r\n] 2006.201.03:29:27.94#ibcon#*before write, iclass 12, count 0 2006.201.03:29:27.94#ibcon#enter sib2, iclass 12, count 0 2006.201.03:29:27.94#ibcon#flushed, iclass 12, count 0 2006.201.03:29:27.94#ibcon#about to write, iclass 12, count 0 2006.201.03:29:27.94#ibcon#wrote, iclass 12, count 0 2006.201.03:29:27.94#ibcon#about to read 3, iclass 12, count 0 2006.201.03:29:27.97#ibcon#read 3, iclass 12, count 0 2006.201.03:29:27.97#ibcon#about to read 4, iclass 12, count 0 2006.201.03:29:27.97#ibcon#read 4, iclass 12, count 0 2006.201.03:29:27.97#ibcon#about to read 5, iclass 12, count 0 2006.201.03:29:27.97#ibcon#read 5, iclass 12, count 0 2006.201.03:29:27.97#ibcon#about to read 6, iclass 12, count 0 2006.201.03:29:27.97#ibcon#read 6, iclass 12, count 0 2006.201.03:29:27.97#ibcon#end of sib2, iclass 12, count 0 2006.201.03:29:27.97#ibcon#*after write, iclass 12, count 0 2006.201.03:29:27.97#ibcon#*before return 0, iclass 12, count 0 2006.201.03:29:27.97#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:27.97#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:29:27.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:29:27.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:29:27.97$vck44/vblo=8,744.99 2006.201.03:29:27.97#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.03:29:27.97#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.03:29:27.97#ibcon#ireg 17 cls_cnt 0 2006.201.03:29:27.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:27.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:27.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:27.97#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:29:27.97#ibcon#first serial, iclass 14, count 0 2006.201.03:29:27.97#ibcon#enter sib2, iclass 14, count 0 2006.201.03:29:27.97#ibcon#flushed, iclass 14, count 0 2006.201.03:29:27.97#ibcon#about to write, iclass 14, count 0 2006.201.03:29:27.97#ibcon#wrote, iclass 14, count 0 2006.201.03:29:27.97#ibcon#about to read 3, iclass 14, count 0 2006.201.03:29:27.99#ibcon#read 3, iclass 14, count 0 2006.201.03:29:27.99#ibcon#about to read 4, iclass 14, count 0 2006.201.03:29:27.99#ibcon#read 4, iclass 14, count 0 2006.201.03:29:27.99#ibcon#about to read 5, iclass 14, count 0 2006.201.03:29:27.99#ibcon#read 5, iclass 14, count 0 2006.201.03:29:27.99#ibcon#about to read 6, iclass 14, count 0 2006.201.03:29:27.99#ibcon#read 6, iclass 14, count 0 2006.201.03:29:27.99#ibcon#end of sib2, iclass 14, count 0 2006.201.03:29:27.99#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:29:27.99#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:29:27.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:29:27.99#ibcon#*before write, iclass 14, count 0 2006.201.03:29:27.99#ibcon#enter sib2, iclass 14, count 0 2006.201.03:29:27.99#ibcon#flushed, iclass 14, count 0 2006.201.03:29:27.99#ibcon#about to write, iclass 14, count 0 2006.201.03:29:27.99#ibcon#wrote, iclass 14, count 0 2006.201.03:29:27.99#ibcon#about to read 3, iclass 14, count 0 2006.201.03:29:28.03#ibcon#read 3, iclass 14, count 0 2006.201.03:29:28.03#ibcon#about to read 4, iclass 14, count 0 2006.201.03:29:28.03#ibcon#read 4, iclass 14, count 0 2006.201.03:29:28.03#ibcon#about to read 5, iclass 14, count 0 2006.201.03:29:28.03#ibcon#read 5, iclass 14, count 0 2006.201.03:29:28.03#ibcon#about to read 6, iclass 14, count 0 2006.201.03:29:28.03#ibcon#read 6, iclass 14, count 0 2006.201.03:29:28.03#ibcon#end of sib2, iclass 14, count 0 2006.201.03:29:28.03#ibcon#*after write, iclass 14, count 0 2006.201.03:29:28.03#ibcon#*before return 0, iclass 14, count 0 2006.201.03:29:28.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:28.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:29:28.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:29:28.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:29:28.03$vck44/vb=8,4 2006.201.03:29:28.03#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.03:29:28.03#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.03:29:28.03#ibcon#ireg 11 cls_cnt 2 2006.201.03:29:28.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:28.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:28.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:28.09#ibcon#enter wrdev, iclass 16, count 2 2006.201.03:29:28.09#ibcon#first serial, iclass 16, count 2 2006.201.03:29:28.09#ibcon#enter sib2, iclass 16, count 2 2006.201.03:29:28.09#ibcon#flushed, iclass 16, count 2 2006.201.03:29:28.09#ibcon#about to write, iclass 16, count 2 2006.201.03:29:28.09#ibcon#wrote, iclass 16, count 2 2006.201.03:29:28.09#ibcon#about to read 3, iclass 16, count 2 2006.201.03:29:28.11#ibcon#read 3, iclass 16, count 2 2006.201.03:29:28.11#ibcon#about to read 4, iclass 16, count 2 2006.201.03:29:28.11#ibcon#read 4, iclass 16, count 2 2006.201.03:29:28.11#ibcon#about to read 5, iclass 16, count 2 2006.201.03:29:28.11#ibcon#read 5, iclass 16, count 2 2006.201.03:29:28.11#ibcon#about to read 6, iclass 16, count 2 2006.201.03:29:28.11#ibcon#read 6, iclass 16, count 2 2006.201.03:29:28.11#ibcon#end of sib2, iclass 16, count 2 2006.201.03:29:28.11#ibcon#*mode == 0, iclass 16, count 2 2006.201.03:29:28.11#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.03:29:28.11#ibcon#[27=AT08-04\r\n] 2006.201.03:29:28.11#ibcon#*before write, iclass 16, count 2 2006.201.03:29:28.11#ibcon#enter sib2, iclass 16, count 2 2006.201.03:29:28.11#ibcon#flushed, iclass 16, count 2 2006.201.03:29:28.11#ibcon#about to write, iclass 16, count 2 2006.201.03:29:28.11#ibcon#wrote, iclass 16, count 2 2006.201.03:29:28.11#ibcon#about to read 3, iclass 16, count 2 2006.201.03:29:28.14#ibcon#read 3, iclass 16, count 2 2006.201.03:29:28.14#ibcon#about to read 4, iclass 16, count 2 2006.201.03:29:28.14#ibcon#read 4, iclass 16, count 2 2006.201.03:29:28.14#ibcon#about to read 5, iclass 16, count 2 2006.201.03:29:28.14#ibcon#read 5, iclass 16, count 2 2006.201.03:29:28.14#ibcon#about to read 6, iclass 16, count 2 2006.201.03:29:28.14#ibcon#read 6, iclass 16, count 2 2006.201.03:29:28.14#ibcon#end of sib2, iclass 16, count 2 2006.201.03:29:28.14#ibcon#*after write, iclass 16, count 2 2006.201.03:29:28.14#ibcon#*before return 0, iclass 16, count 2 2006.201.03:29:28.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:28.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:29:28.14#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.03:29:28.14#ibcon#ireg 7 cls_cnt 0 2006.201.03:29:28.14#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:28.26#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:28.26#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:28.26#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:29:28.26#ibcon#first serial, iclass 16, count 0 2006.201.03:29:28.26#ibcon#enter sib2, iclass 16, count 0 2006.201.03:29:28.26#ibcon#flushed, iclass 16, count 0 2006.201.03:29:28.26#ibcon#about to write, iclass 16, count 0 2006.201.03:29:28.26#ibcon#wrote, iclass 16, count 0 2006.201.03:29:28.26#ibcon#about to read 3, iclass 16, count 0 2006.201.03:29:28.28#ibcon#read 3, iclass 16, count 0 2006.201.03:29:28.28#ibcon#about to read 4, iclass 16, count 0 2006.201.03:29:28.28#ibcon#read 4, iclass 16, count 0 2006.201.03:29:28.28#ibcon#about to read 5, iclass 16, count 0 2006.201.03:29:28.28#ibcon#read 5, iclass 16, count 0 2006.201.03:29:28.28#ibcon#about to read 6, iclass 16, count 0 2006.201.03:29:28.28#ibcon#read 6, iclass 16, count 0 2006.201.03:29:28.28#ibcon#end of sib2, iclass 16, count 0 2006.201.03:29:28.28#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:29:28.28#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:29:28.28#ibcon#[27=USB\r\n] 2006.201.03:29:28.28#ibcon#*before write, iclass 16, count 0 2006.201.03:29:28.28#ibcon#enter sib2, iclass 16, count 0 2006.201.03:29:28.28#ibcon#flushed, iclass 16, count 0 2006.201.03:29:28.28#ibcon#about to write, iclass 16, count 0 2006.201.03:29:28.28#ibcon#wrote, iclass 16, count 0 2006.201.03:29:28.28#ibcon#about to read 3, iclass 16, count 0 2006.201.03:29:28.31#ibcon#read 3, iclass 16, count 0 2006.201.03:29:28.31#ibcon#about to read 4, iclass 16, count 0 2006.201.03:29:28.31#ibcon#read 4, iclass 16, count 0 2006.201.03:29:28.31#ibcon#about to read 5, iclass 16, count 0 2006.201.03:29:28.31#ibcon#read 5, iclass 16, count 0 2006.201.03:29:28.31#ibcon#about to read 6, iclass 16, count 0 2006.201.03:29:28.31#ibcon#read 6, iclass 16, count 0 2006.201.03:29:28.31#ibcon#end of sib2, iclass 16, count 0 2006.201.03:29:28.31#ibcon#*after write, iclass 16, count 0 2006.201.03:29:28.31#ibcon#*before return 0, iclass 16, count 0 2006.201.03:29:28.31#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:28.31#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:29:28.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:29:28.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:29:28.31$vck44/vabw=wide 2006.201.03:29:28.31#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.03:29:28.31#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.03:29:28.31#ibcon#ireg 8 cls_cnt 0 2006.201.03:29:28.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:28.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:28.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:28.31#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:29:28.31#ibcon#first serial, iclass 18, count 0 2006.201.03:29:28.31#ibcon#enter sib2, iclass 18, count 0 2006.201.03:29:28.31#ibcon#flushed, iclass 18, count 0 2006.201.03:29:28.31#ibcon#about to write, iclass 18, count 0 2006.201.03:29:28.31#ibcon#wrote, iclass 18, count 0 2006.201.03:29:28.31#ibcon#about to read 3, iclass 18, count 0 2006.201.03:29:28.33#ibcon#read 3, iclass 18, count 0 2006.201.03:29:28.33#ibcon#about to read 4, iclass 18, count 0 2006.201.03:29:28.33#ibcon#read 4, iclass 18, count 0 2006.201.03:29:28.33#ibcon#about to read 5, iclass 18, count 0 2006.201.03:29:28.33#ibcon#read 5, iclass 18, count 0 2006.201.03:29:28.33#ibcon#about to read 6, iclass 18, count 0 2006.201.03:29:28.33#ibcon#read 6, iclass 18, count 0 2006.201.03:29:28.33#ibcon#end of sib2, iclass 18, count 0 2006.201.03:29:28.33#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:29:28.33#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:29:28.33#ibcon#[25=BW32\r\n] 2006.201.03:29:28.33#ibcon#*before write, iclass 18, count 0 2006.201.03:29:28.33#ibcon#enter sib2, iclass 18, count 0 2006.201.03:29:28.33#ibcon#flushed, iclass 18, count 0 2006.201.03:29:28.33#ibcon#about to write, iclass 18, count 0 2006.201.03:29:28.33#ibcon#wrote, iclass 18, count 0 2006.201.03:29:28.33#ibcon#about to read 3, iclass 18, count 0 2006.201.03:29:28.36#ibcon#read 3, iclass 18, count 0 2006.201.03:29:28.36#ibcon#about to read 4, iclass 18, count 0 2006.201.03:29:28.36#ibcon#read 4, iclass 18, count 0 2006.201.03:29:28.36#ibcon#about to read 5, iclass 18, count 0 2006.201.03:29:28.36#ibcon#read 5, iclass 18, count 0 2006.201.03:29:28.36#ibcon#about to read 6, iclass 18, count 0 2006.201.03:29:28.36#ibcon#read 6, iclass 18, count 0 2006.201.03:29:28.36#ibcon#end of sib2, iclass 18, count 0 2006.201.03:29:28.36#ibcon#*after write, iclass 18, count 0 2006.201.03:29:28.36#ibcon#*before return 0, iclass 18, count 0 2006.201.03:29:28.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:28.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:29:28.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:29:28.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:29:28.36$vck44/vbbw=wide 2006.201.03:29:28.36#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.03:29:28.36#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.03:29:28.36#ibcon#ireg 8 cls_cnt 0 2006.201.03:29:28.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:29:28.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:29:28.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:29:28.43#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:29:28.43#ibcon#first serial, iclass 20, count 0 2006.201.03:29:28.43#ibcon#enter sib2, iclass 20, count 0 2006.201.03:29:28.43#ibcon#flushed, iclass 20, count 0 2006.201.03:29:28.43#ibcon#about to write, iclass 20, count 0 2006.201.03:29:28.43#ibcon#wrote, iclass 20, count 0 2006.201.03:29:28.43#ibcon#about to read 3, iclass 20, count 0 2006.201.03:29:28.45#ibcon#read 3, iclass 20, count 0 2006.201.03:29:28.45#ibcon#about to read 4, iclass 20, count 0 2006.201.03:29:28.45#ibcon#read 4, iclass 20, count 0 2006.201.03:29:28.45#ibcon#about to read 5, iclass 20, count 0 2006.201.03:29:28.45#ibcon#read 5, iclass 20, count 0 2006.201.03:29:28.45#ibcon#about to read 6, iclass 20, count 0 2006.201.03:29:28.45#ibcon#read 6, iclass 20, count 0 2006.201.03:29:28.45#ibcon#end of sib2, iclass 20, count 0 2006.201.03:29:28.45#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:29:28.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:29:28.45#ibcon#[27=BW32\r\n] 2006.201.03:29:28.45#ibcon#*before write, iclass 20, count 0 2006.201.03:29:28.45#ibcon#enter sib2, iclass 20, count 0 2006.201.03:29:28.45#ibcon#flushed, iclass 20, count 0 2006.201.03:29:28.45#ibcon#about to write, iclass 20, count 0 2006.201.03:29:28.45#ibcon#wrote, iclass 20, count 0 2006.201.03:29:28.45#ibcon#about to read 3, iclass 20, count 0 2006.201.03:29:28.48#ibcon#read 3, iclass 20, count 0 2006.201.03:29:28.48#ibcon#about to read 4, iclass 20, count 0 2006.201.03:29:28.48#ibcon#read 4, iclass 20, count 0 2006.201.03:29:28.48#ibcon#about to read 5, iclass 20, count 0 2006.201.03:29:28.48#ibcon#read 5, iclass 20, count 0 2006.201.03:29:28.48#ibcon#about to read 6, iclass 20, count 0 2006.201.03:29:28.48#ibcon#read 6, iclass 20, count 0 2006.201.03:29:28.48#ibcon#end of sib2, iclass 20, count 0 2006.201.03:29:28.48#ibcon#*after write, iclass 20, count 0 2006.201.03:29:28.48#ibcon#*before return 0, iclass 20, count 0 2006.201.03:29:28.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:29:28.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:29:28.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:29:28.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:29:28.48$setupk4/ifdk4 2006.201.03:29:28.48$ifdk4/lo= 2006.201.03:29:28.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:29:28.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:29:28.48$ifdk4/patch= 2006.201.03:29:28.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:29:28.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:29:28.48$setupk4/!*+20s 2006.201.03:29:30.76#abcon#<5=/03 2.6 4.7 23.02 921004.4\r\n> 2006.201.03:29:30.78#abcon#{5=INTERFACE CLEAR} 2006.201.03:29:30.86#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:29:40.95#abcon#<5=/03 2.6 4.7 23.02 921004.5\r\n> 2006.201.03:29:40.97#abcon#{5=INTERFACE CLEAR} 2006.201.03:29:41.03#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:29:42.94$setupk4/"tpicd 2006.201.03:29:42.94$setupk4/echo=off 2006.201.03:29:42.94$setupk4/xlog=off 2006.201.03:29:42.94:!2006.201.03:30:17 2006.201.03:29:44.14#trakl#Source acquired 2006.201.03:29:45.14#flagr#flagr/antenna,acquired 2006.201.03:30:17.00:preob 2006.201.03:30:17.13/onsource/TRACKING 2006.201.03:30:17.13:!2006.201.03:30:27 2006.201.03:30:27.00:"tape 2006.201.03:30:27.00:"st=record 2006.201.03:30:27.00:data_valid=on 2006.201.03:30:27.00:midob 2006.201.03:30:27.13/onsource/TRACKING 2006.201.03:30:27.13/wx/23.03,1004.5,91 2006.201.03:30:27.22/cable/+6.4667E-03 2006.201.03:30:28.31/va/01,08,usb,yes,31,34 2006.201.03:30:28.31/va/02,07,usb,yes,34,35 2006.201.03:30:28.31/va/03,08,usb,yes,31,32 2006.201.03:30:28.31/va/04,07,usb,yes,35,37 2006.201.03:30:28.31/va/05,04,usb,yes,31,31 2006.201.03:30:28.31/va/06,05,usb,yes,31,31 2006.201.03:30:28.31/va/07,05,usb,yes,30,31 2006.201.03:30:28.31/va/08,04,usb,yes,29,36 2006.201.03:30:28.54/valo/01,524.99,yes,locked 2006.201.03:30:28.54/valo/02,534.99,yes,locked 2006.201.03:30:28.54/valo/03,564.99,yes,locked 2006.201.03:30:28.54/valo/04,624.99,yes,locked 2006.201.03:30:28.54/valo/05,734.99,yes,locked 2006.201.03:30:28.54/valo/06,814.99,yes,locked 2006.201.03:30:28.54/valo/07,864.99,yes,locked 2006.201.03:30:28.54/valo/08,884.99,yes,locked 2006.201.03:30:29.63/vb/01,04,usb,yes,36,33 2006.201.03:30:29.63/vb/02,05,usb,yes,34,34 2006.201.03:30:29.63/vb/03,04,usb,yes,35,39 2006.201.03:30:29.63/vb/04,05,usb,yes,35,34 2006.201.03:30:29.63/vb/05,04,usb,yes,31,34 2006.201.03:30:29.63/vb/06,04,usb,yes,36,32 2006.201.03:30:29.63/vb/07,04,usb,yes,36,36 2006.201.03:30:29.63/vb/08,04,usb,yes,33,37 2006.201.03:30:29.86/vblo/01,629.99,yes,locked 2006.201.03:30:29.86/vblo/02,634.99,yes,locked 2006.201.03:30:29.86/vblo/03,649.99,yes,locked 2006.201.03:30:29.86/vblo/04,679.99,yes,locked 2006.201.03:30:29.86/vblo/05,709.99,yes,locked 2006.201.03:30:29.86/vblo/06,719.99,yes,locked 2006.201.03:30:29.86/vblo/07,734.99,yes,locked 2006.201.03:30:29.86/vblo/08,744.99,yes,locked 2006.201.03:30:30.01/vabw/8 2006.201.03:30:30.16/vbbw/8 2006.201.03:30:30.25/xfe/off,on,16.0 2006.201.03:30:30.62/ifatt/23,28,28,28 2006.201.03:30:31.03/fmout-gps/S +4.49E-07 2006.201.03:30:31.10:!2006.201.03:32:07 2006.201.03:32:07.00:data_valid=off 2006.201.03:32:07.00:"et 2006.201.03:32:07.00:!+3s 2006.201.03:32:10.02:"tape 2006.201.03:32:10.02:postob 2006.201.03:32:10.24/cable/+6.4666E-03 2006.201.03:32:10.24/wx/23.04,1004.5,91 2006.201.03:32:10.31/fmout-gps/S +4.50E-07 2006.201.03:32:10.31:scan_name=201-0336,jd0607,40 2006.201.03:32:10.32:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.201.03:32:12.13#flagr#flagr/antenna,new-source 2006.201.03:32:12.13:checkk5 2006.201.03:32:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:32:12.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:32:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:32:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:32:14.00/chk_obsdata//k5ts1/T2010330??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.201.03:32:14.38/chk_obsdata//k5ts2/T2010330??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.201.03:32:14.75/chk_obsdata//k5ts3/T2010330??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.201.03:32:15.12/chk_obsdata//k5ts4/T2010330??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.201.03:32:15.81/k5log//k5ts1_log_newline 2006.201.03:32:16.51/k5log//k5ts2_log_newline 2006.201.03:32:17.20/k5log//k5ts3_log_newline 2006.201.03:32:17.89/k5log//k5ts4_log_newline 2006.201.03:32:17.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:32:17.91:setupk4=1 2006.201.03:32:17.91$setupk4/echo=on 2006.201.03:32:17.91$setupk4/pcalon 2006.201.03:32:17.91$pcalon/"no phase cal control is implemented here 2006.201.03:32:17.91$setupk4/"tpicd=stop 2006.201.03:32:17.91$setupk4/"rec=synch_on 2006.201.03:32:17.91$setupk4/"rec_mode=128 2006.201.03:32:17.91$setupk4/!* 2006.201.03:32:17.91$setupk4/recpk4 2006.201.03:32:17.91$recpk4/recpatch= 2006.201.03:32:17.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:32:17.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:32:17.92$setupk4/vck44 2006.201.03:32:17.92$vck44/valo=1,524.99 2006.201.03:32:17.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.03:32:17.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.03:32:17.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:17.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:17.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:17.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:17.92#ibcon#enter wrdev, iclass 21, count 0 2006.201.03:32:17.92#ibcon#first serial, iclass 21, count 0 2006.201.03:32:17.92#ibcon#enter sib2, iclass 21, count 0 2006.201.03:32:17.92#ibcon#flushed, iclass 21, count 0 2006.201.03:32:17.92#ibcon#about to write, iclass 21, count 0 2006.201.03:32:17.92#ibcon#wrote, iclass 21, count 0 2006.201.03:32:17.92#ibcon#about to read 3, iclass 21, count 0 2006.201.03:32:17.96#ibcon#read 3, iclass 21, count 0 2006.201.03:32:17.96#ibcon#about to read 4, iclass 21, count 0 2006.201.03:32:17.96#ibcon#read 4, iclass 21, count 0 2006.201.03:32:17.96#ibcon#about to read 5, iclass 21, count 0 2006.201.03:32:17.96#ibcon#read 5, iclass 21, count 0 2006.201.03:32:17.96#ibcon#about to read 6, iclass 21, count 0 2006.201.03:32:17.96#ibcon#read 6, iclass 21, count 0 2006.201.03:32:17.96#ibcon#end of sib2, iclass 21, count 0 2006.201.03:32:17.96#ibcon#*mode == 0, iclass 21, count 0 2006.201.03:32:17.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.03:32:17.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:32:17.96#ibcon#*before write, iclass 21, count 0 2006.201.03:32:17.96#ibcon#enter sib2, iclass 21, count 0 2006.201.03:32:17.96#ibcon#flushed, iclass 21, count 0 2006.201.03:32:17.96#ibcon#about to write, iclass 21, count 0 2006.201.03:32:17.96#ibcon#wrote, iclass 21, count 0 2006.201.03:32:17.96#ibcon#about to read 3, iclass 21, count 0 2006.201.03:32:18.01#ibcon#read 3, iclass 21, count 0 2006.201.03:32:18.01#ibcon#about to read 4, iclass 21, count 0 2006.201.03:32:18.01#ibcon#read 4, iclass 21, count 0 2006.201.03:32:18.01#ibcon#about to read 5, iclass 21, count 0 2006.201.03:32:18.01#ibcon#read 5, iclass 21, count 0 2006.201.03:32:18.01#ibcon#about to read 6, iclass 21, count 0 2006.201.03:32:18.01#ibcon#read 6, iclass 21, count 0 2006.201.03:32:18.01#ibcon#end of sib2, iclass 21, count 0 2006.201.03:32:18.01#ibcon#*after write, iclass 21, count 0 2006.201.03:32:18.01#ibcon#*before return 0, iclass 21, count 0 2006.201.03:32:18.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:18.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:18.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.03:32:18.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.03:32:18.01$vck44/va=1,8 2006.201.03:32:18.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.03:32:18.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.03:32:18.01#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:18.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:18.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:18.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:18.01#ibcon#enter wrdev, iclass 23, count 2 2006.201.03:32:18.01#ibcon#first serial, iclass 23, count 2 2006.201.03:32:18.01#ibcon#enter sib2, iclass 23, count 2 2006.201.03:32:18.01#ibcon#flushed, iclass 23, count 2 2006.201.03:32:18.01#ibcon#about to write, iclass 23, count 2 2006.201.03:32:18.01#ibcon#wrote, iclass 23, count 2 2006.201.03:32:18.01#ibcon#about to read 3, iclass 23, count 2 2006.201.03:32:18.03#ibcon#read 3, iclass 23, count 2 2006.201.03:32:18.03#ibcon#about to read 4, iclass 23, count 2 2006.201.03:32:18.03#ibcon#read 4, iclass 23, count 2 2006.201.03:32:18.03#ibcon#about to read 5, iclass 23, count 2 2006.201.03:32:18.03#ibcon#read 5, iclass 23, count 2 2006.201.03:32:18.03#ibcon#about to read 6, iclass 23, count 2 2006.201.03:32:18.03#ibcon#read 6, iclass 23, count 2 2006.201.03:32:18.03#ibcon#end of sib2, iclass 23, count 2 2006.201.03:32:18.03#ibcon#*mode == 0, iclass 23, count 2 2006.201.03:32:18.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.03:32:18.03#ibcon#[25=AT01-08\r\n] 2006.201.03:32:18.03#ibcon#*before write, iclass 23, count 2 2006.201.03:32:18.03#ibcon#enter sib2, iclass 23, count 2 2006.201.03:32:18.03#ibcon#flushed, iclass 23, count 2 2006.201.03:32:18.03#ibcon#about to write, iclass 23, count 2 2006.201.03:32:18.03#ibcon#wrote, iclass 23, count 2 2006.201.03:32:18.03#ibcon#about to read 3, iclass 23, count 2 2006.201.03:32:18.06#ibcon#read 3, iclass 23, count 2 2006.201.03:32:18.06#ibcon#about to read 4, iclass 23, count 2 2006.201.03:32:18.06#ibcon#read 4, iclass 23, count 2 2006.201.03:32:18.06#ibcon#about to read 5, iclass 23, count 2 2006.201.03:32:18.06#ibcon#read 5, iclass 23, count 2 2006.201.03:32:18.06#ibcon#about to read 6, iclass 23, count 2 2006.201.03:32:18.06#ibcon#read 6, iclass 23, count 2 2006.201.03:32:18.06#ibcon#end of sib2, iclass 23, count 2 2006.201.03:32:18.06#ibcon#*after write, iclass 23, count 2 2006.201.03:32:18.06#ibcon#*before return 0, iclass 23, count 2 2006.201.03:32:18.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:18.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:18.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.03:32:18.06#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:18.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:18.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:18.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:18.18#ibcon#enter wrdev, iclass 23, count 0 2006.201.03:32:18.18#ibcon#first serial, iclass 23, count 0 2006.201.03:32:18.18#ibcon#enter sib2, iclass 23, count 0 2006.201.03:32:18.18#ibcon#flushed, iclass 23, count 0 2006.201.03:32:18.18#ibcon#about to write, iclass 23, count 0 2006.201.03:32:18.18#ibcon#wrote, iclass 23, count 0 2006.201.03:32:18.18#ibcon#about to read 3, iclass 23, count 0 2006.201.03:32:18.20#ibcon#read 3, iclass 23, count 0 2006.201.03:32:18.20#ibcon#about to read 4, iclass 23, count 0 2006.201.03:32:18.20#ibcon#read 4, iclass 23, count 0 2006.201.03:32:18.20#ibcon#about to read 5, iclass 23, count 0 2006.201.03:32:18.20#ibcon#read 5, iclass 23, count 0 2006.201.03:32:18.20#ibcon#about to read 6, iclass 23, count 0 2006.201.03:32:18.20#ibcon#read 6, iclass 23, count 0 2006.201.03:32:18.20#ibcon#end of sib2, iclass 23, count 0 2006.201.03:32:18.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.03:32:18.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.03:32:18.20#ibcon#[25=USB\r\n] 2006.201.03:32:18.20#ibcon#*before write, iclass 23, count 0 2006.201.03:32:18.20#ibcon#enter sib2, iclass 23, count 0 2006.201.03:32:18.20#ibcon#flushed, iclass 23, count 0 2006.201.03:32:18.20#ibcon#about to write, iclass 23, count 0 2006.201.03:32:18.20#ibcon#wrote, iclass 23, count 0 2006.201.03:32:18.20#ibcon#about to read 3, iclass 23, count 0 2006.201.03:32:18.23#ibcon#read 3, iclass 23, count 0 2006.201.03:32:18.23#ibcon#about to read 4, iclass 23, count 0 2006.201.03:32:18.23#ibcon#read 4, iclass 23, count 0 2006.201.03:32:18.23#ibcon#about to read 5, iclass 23, count 0 2006.201.03:32:18.23#ibcon#read 5, iclass 23, count 0 2006.201.03:32:18.23#ibcon#about to read 6, iclass 23, count 0 2006.201.03:32:18.23#ibcon#read 6, iclass 23, count 0 2006.201.03:32:18.23#ibcon#end of sib2, iclass 23, count 0 2006.201.03:32:18.23#ibcon#*after write, iclass 23, count 0 2006.201.03:32:18.23#ibcon#*before return 0, iclass 23, count 0 2006.201.03:32:18.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:18.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:18.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.03:32:18.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.03:32:18.23$vck44/valo=2,534.99 2006.201.03:32:18.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.03:32:18.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.03:32:18.23#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:18.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:18.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:18.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:18.23#ibcon#enter wrdev, iclass 25, count 0 2006.201.03:32:18.23#ibcon#first serial, iclass 25, count 0 2006.201.03:32:18.23#ibcon#enter sib2, iclass 25, count 0 2006.201.03:32:18.23#ibcon#flushed, iclass 25, count 0 2006.201.03:32:18.23#ibcon#about to write, iclass 25, count 0 2006.201.03:32:18.23#ibcon#wrote, iclass 25, count 0 2006.201.03:32:18.23#ibcon#about to read 3, iclass 25, count 0 2006.201.03:32:18.25#ibcon#read 3, iclass 25, count 0 2006.201.03:32:18.25#ibcon#about to read 4, iclass 25, count 0 2006.201.03:32:18.25#ibcon#read 4, iclass 25, count 0 2006.201.03:32:18.25#ibcon#about to read 5, iclass 25, count 0 2006.201.03:32:18.25#ibcon#read 5, iclass 25, count 0 2006.201.03:32:18.25#ibcon#about to read 6, iclass 25, count 0 2006.201.03:32:18.25#ibcon#read 6, iclass 25, count 0 2006.201.03:32:18.25#ibcon#end of sib2, iclass 25, count 0 2006.201.03:32:18.25#ibcon#*mode == 0, iclass 25, count 0 2006.201.03:32:18.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.03:32:18.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:32:18.25#ibcon#*before write, iclass 25, count 0 2006.201.03:32:18.25#ibcon#enter sib2, iclass 25, count 0 2006.201.03:32:18.25#ibcon#flushed, iclass 25, count 0 2006.201.03:32:18.25#ibcon#about to write, iclass 25, count 0 2006.201.03:32:18.25#ibcon#wrote, iclass 25, count 0 2006.201.03:32:18.25#ibcon#about to read 3, iclass 25, count 0 2006.201.03:32:18.29#ibcon#read 3, iclass 25, count 0 2006.201.03:32:18.29#ibcon#about to read 4, iclass 25, count 0 2006.201.03:32:18.29#ibcon#read 4, iclass 25, count 0 2006.201.03:32:18.29#ibcon#about to read 5, iclass 25, count 0 2006.201.03:32:18.29#ibcon#read 5, iclass 25, count 0 2006.201.03:32:18.29#ibcon#about to read 6, iclass 25, count 0 2006.201.03:32:18.29#ibcon#read 6, iclass 25, count 0 2006.201.03:32:18.29#ibcon#end of sib2, iclass 25, count 0 2006.201.03:32:18.29#ibcon#*after write, iclass 25, count 0 2006.201.03:32:18.29#ibcon#*before return 0, iclass 25, count 0 2006.201.03:32:18.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:18.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:18.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.03:32:18.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.03:32:18.29$vck44/va=2,7 2006.201.03:32:18.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.03:32:18.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.03:32:18.29#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:18.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:18.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:18.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:18.35#ibcon#enter wrdev, iclass 27, count 2 2006.201.03:32:18.35#ibcon#first serial, iclass 27, count 2 2006.201.03:32:18.35#ibcon#enter sib2, iclass 27, count 2 2006.201.03:32:18.35#ibcon#flushed, iclass 27, count 2 2006.201.03:32:18.35#ibcon#about to write, iclass 27, count 2 2006.201.03:32:18.35#ibcon#wrote, iclass 27, count 2 2006.201.03:32:18.35#ibcon#about to read 3, iclass 27, count 2 2006.201.03:32:18.37#ibcon#read 3, iclass 27, count 2 2006.201.03:32:18.37#ibcon#about to read 4, iclass 27, count 2 2006.201.03:32:18.37#ibcon#read 4, iclass 27, count 2 2006.201.03:32:18.37#ibcon#about to read 5, iclass 27, count 2 2006.201.03:32:18.37#ibcon#read 5, iclass 27, count 2 2006.201.03:32:18.37#ibcon#about to read 6, iclass 27, count 2 2006.201.03:32:18.37#ibcon#read 6, iclass 27, count 2 2006.201.03:32:18.37#ibcon#end of sib2, iclass 27, count 2 2006.201.03:32:18.37#ibcon#*mode == 0, iclass 27, count 2 2006.201.03:32:18.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.03:32:18.37#ibcon#[25=AT02-07\r\n] 2006.201.03:32:18.37#ibcon#*before write, iclass 27, count 2 2006.201.03:32:18.37#ibcon#enter sib2, iclass 27, count 2 2006.201.03:32:18.37#ibcon#flushed, iclass 27, count 2 2006.201.03:32:18.37#ibcon#about to write, iclass 27, count 2 2006.201.03:32:18.37#ibcon#wrote, iclass 27, count 2 2006.201.03:32:18.37#ibcon#about to read 3, iclass 27, count 2 2006.201.03:32:18.40#ibcon#read 3, iclass 27, count 2 2006.201.03:32:18.40#ibcon#about to read 4, iclass 27, count 2 2006.201.03:32:18.40#ibcon#read 4, iclass 27, count 2 2006.201.03:32:18.40#ibcon#about to read 5, iclass 27, count 2 2006.201.03:32:18.40#ibcon#read 5, iclass 27, count 2 2006.201.03:32:18.40#ibcon#about to read 6, iclass 27, count 2 2006.201.03:32:18.40#ibcon#read 6, iclass 27, count 2 2006.201.03:32:18.40#ibcon#end of sib2, iclass 27, count 2 2006.201.03:32:18.40#ibcon#*after write, iclass 27, count 2 2006.201.03:32:18.40#ibcon#*before return 0, iclass 27, count 2 2006.201.03:32:18.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:18.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:18.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.03:32:18.40#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:18.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:18.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:18.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:18.52#ibcon#enter wrdev, iclass 27, count 0 2006.201.03:32:18.52#ibcon#first serial, iclass 27, count 0 2006.201.03:32:18.52#ibcon#enter sib2, iclass 27, count 0 2006.201.03:32:18.52#ibcon#flushed, iclass 27, count 0 2006.201.03:32:18.52#ibcon#about to write, iclass 27, count 0 2006.201.03:32:18.52#ibcon#wrote, iclass 27, count 0 2006.201.03:32:18.52#ibcon#about to read 3, iclass 27, count 0 2006.201.03:32:18.54#ibcon#read 3, iclass 27, count 0 2006.201.03:32:18.54#ibcon#about to read 4, iclass 27, count 0 2006.201.03:32:18.54#ibcon#read 4, iclass 27, count 0 2006.201.03:32:18.54#ibcon#about to read 5, iclass 27, count 0 2006.201.03:32:18.54#ibcon#read 5, iclass 27, count 0 2006.201.03:32:18.54#ibcon#about to read 6, iclass 27, count 0 2006.201.03:32:18.54#ibcon#read 6, iclass 27, count 0 2006.201.03:32:18.54#ibcon#end of sib2, iclass 27, count 0 2006.201.03:32:18.54#ibcon#*mode == 0, iclass 27, count 0 2006.201.03:32:18.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.03:32:18.54#ibcon#[25=USB\r\n] 2006.201.03:32:18.54#ibcon#*before write, iclass 27, count 0 2006.201.03:32:18.54#ibcon#enter sib2, iclass 27, count 0 2006.201.03:32:18.54#ibcon#flushed, iclass 27, count 0 2006.201.03:32:18.54#ibcon#about to write, iclass 27, count 0 2006.201.03:32:18.54#ibcon#wrote, iclass 27, count 0 2006.201.03:32:18.54#ibcon#about to read 3, iclass 27, count 0 2006.201.03:32:18.57#ibcon#read 3, iclass 27, count 0 2006.201.03:32:18.57#ibcon#about to read 4, iclass 27, count 0 2006.201.03:32:18.57#ibcon#read 4, iclass 27, count 0 2006.201.03:32:18.57#ibcon#about to read 5, iclass 27, count 0 2006.201.03:32:18.57#ibcon#read 5, iclass 27, count 0 2006.201.03:32:18.57#ibcon#about to read 6, iclass 27, count 0 2006.201.03:32:18.57#ibcon#read 6, iclass 27, count 0 2006.201.03:32:18.57#ibcon#end of sib2, iclass 27, count 0 2006.201.03:32:18.57#ibcon#*after write, iclass 27, count 0 2006.201.03:32:18.57#ibcon#*before return 0, iclass 27, count 0 2006.201.03:32:18.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:18.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:18.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.03:32:18.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.03:32:18.57$vck44/valo=3,564.99 2006.201.03:32:18.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.03:32:18.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.03:32:18.57#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:18.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:18.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:18.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:18.57#ibcon#enter wrdev, iclass 29, count 0 2006.201.03:32:18.57#ibcon#first serial, iclass 29, count 0 2006.201.03:32:18.57#ibcon#enter sib2, iclass 29, count 0 2006.201.03:32:18.57#ibcon#flushed, iclass 29, count 0 2006.201.03:32:18.57#ibcon#about to write, iclass 29, count 0 2006.201.03:32:18.57#ibcon#wrote, iclass 29, count 0 2006.201.03:32:18.57#ibcon#about to read 3, iclass 29, count 0 2006.201.03:32:18.59#ibcon#read 3, iclass 29, count 0 2006.201.03:32:18.59#ibcon#about to read 4, iclass 29, count 0 2006.201.03:32:18.59#ibcon#read 4, iclass 29, count 0 2006.201.03:32:18.59#ibcon#about to read 5, iclass 29, count 0 2006.201.03:32:18.59#ibcon#read 5, iclass 29, count 0 2006.201.03:32:18.59#ibcon#about to read 6, iclass 29, count 0 2006.201.03:32:18.59#ibcon#read 6, iclass 29, count 0 2006.201.03:32:18.59#ibcon#end of sib2, iclass 29, count 0 2006.201.03:32:18.59#ibcon#*mode == 0, iclass 29, count 0 2006.201.03:32:18.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.03:32:18.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:32:18.59#ibcon#*before write, iclass 29, count 0 2006.201.03:32:18.59#ibcon#enter sib2, iclass 29, count 0 2006.201.03:32:18.59#ibcon#flushed, iclass 29, count 0 2006.201.03:32:18.59#ibcon#about to write, iclass 29, count 0 2006.201.03:32:18.59#ibcon#wrote, iclass 29, count 0 2006.201.03:32:18.59#ibcon#about to read 3, iclass 29, count 0 2006.201.03:32:18.63#ibcon#read 3, iclass 29, count 0 2006.201.03:32:18.63#ibcon#about to read 4, iclass 29, count 0 2006.201.03:32:18.63#ibcon#read 4, iclass 29, count 0 2006.201.03:32:18.63#ibcon#about to read 5, iclass 29, count 0 2006.201.03:32:18.63#ibcon#read 5, iclass 29, count 0 2006.201.03:32:18.63#ibcon#about to read 6, iclass 29, count 0 2006.201.03:32:18.63#ibcon#read 6, iclass 29, count 0 2006.201.03:32:18.63#ibcon#end of sib2, iclass 29, count 0 2006.201.03:32:18.63#ibcon#*after write, iclass 29, count 0 2006.201.03:32:18.63#ibcon#*before return 0, iclass 29, count 0 2006.201.03:32:18.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:18.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:18.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.03:32:18.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.03:32:18.63$vck44/va=3,8 2006.201.03:32:18.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.03:32:18.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.03:32:18.63#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:18.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:18.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:18.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:18.69#ibcon#enter wrdev, iclass 31, count 2 2006.201.03:32:18.69#ibcon#first serial, iclass 31, count 2 2006.201.03:32:18.69#ibcon#enter sib2, iclass 31, count 2 2006.201.03:32:18.69#ibcon#flushed, iclass 31, count 2 2006.201.03:32:18.69#ibcon#about to write, iclass 31, count 2 2006.201.03:32:18.69#ibcon#wrote, iclass 31, count 2 2006.201.03:32:18.69#ibcon#about to read 3, iclass 31, count 2 2006.201.03:32:18.71#ibcon#read 3, iclass 31, count 2 2006.201.03:32:18.71#ibcon#about to read 4, iclass 31, count 2 2006.201.03:32:18.71#ibcon#read 4, iclass 31, count 2 2006.201.03:32:18.71#ibcon#about to read 5, iclass 31, count 2 2006.201.03:32:18.71#ibcon#read 5, iclass 31, count 2 2006.201.03:32:18.71#ibcon#about to read 6, iclass 31, count 2 2006.201.03:32:18.71#ibcon#read 6, iclass 31, count 2 2006.201.03:32:18.71#ibcon#end of sib2, iclass 31, count 2 2006.201.03:32:18.71#ibcon#*mode == 0, iclass 31, count 2 2006.201.03:32:18.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.03:32:18.71#ibcon#[25=AT03-08\r\n] 2006.201.03:32:18.71#ibcon#*before write, iclass 31, count 2 2006.201.03:32:18.71#ibcon#enter sib2, iclass 31, count 2 2006.201.03:32:18.71#ibcon#flushed, iclass 31, count 2 2006.201.03:32:18.71#ibcon#about to write, iclass 31, count 2 2006.201.03:32:18.71#ibcon#wrote, iclass 31, count 2 2006.201.03:32:18.71#ibcon#about to read 3, iclass 31, count 2 2006.201.03:32:18.75#ibcon#read 3, iclass 31, count 2 2006.201.03:32:18.75#ibcon#about to read 4, iclass 31, count 2 2006.201.03:32:18.75#ibcon#read 4, iclass 31, count 2 2006.201.03:32:18.75#ibcon#about to read 5, iclass 31, count 2 2006.201.03:32:18.75#ibcon#read 5, iclass 31, count 2 2006.201.03:32:18.75#ibcon#about to read 6, iclass 31, count 2 2006.201.03:32:18.75#ibcon#read 6, iclass 31, count 2 2006.201.03:32:18.75#ibcon#end of sib2, iclass 31, count 2 2006.201.03:32:18.75#ibcon#*after write, iclass 31, count 2 2006.201.03:32:18.75#ibcon#*before return 0, iclass 31, count 2 2006.201.03:32:18.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:18.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:18.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.03:32:18.75#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:18.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:18.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:18.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:18.87#ibcon#enter wrdev, iclass 31, count 0 2006.201.03:32:18.87#ibcon#first serial, iclass 31, count 0 2006.201.03:32:18.87#ibcon#enter sib2, iclass 31, count 0 2006.201.03:32:18.87#ibcon#flushed, iclass 31, count 0 2006.201.03:32:18.87#ibcon#about to write, iclass 31, count 0 2006.201.03:32:18.87#ibcon#wrote, iclass 31, count 0 2006.201.03:32:18.87#ibcon#about to read 3, iclass 31, count 0 2006.201.03:32:18.89#ibcon#read 3, iclass 31, count 0 2006.201.03:32:18.89#ibcon#about to read 4, iclass 31, count 0 2006.201.03:32:18.89#ibcon#read 4, iclass 31, count 0 2006.201.03:32:18.89#ibcon#about to read 5, iclass 31, count 0 2006.201.03:32:18.89#ibcon#read 5, iclass 31, count 0 2006.201.03:32:18.89#ibcon#about to read 6, iclass 31, count 0 2006.201.03:32:18.89#ibcon#read 6, iclass 31, count 0 2006.201.03:32:18.89#ibcon#end of sib2, iclass 31, count 0 2006.201.03:32:18.89#ibcon#*mode == 0, iclass 31, count 0 2006.201.03:32:18.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.03:32:18.89#ibcon#[25=USB\r\n] 2006.201.03:32:18.89#ibcon#*before write, iclass 31, count 0 2006.201.03:32:18.89#ibcon#enter sib2, iclass 31, count 0 2006.201.03:32:18.89#ibcon#flushed, iclass 31, count 0 2006.201.03:32:18.89#ibcon#about to write, iclass 31, count 0 2006.201.03:32:18.89#ibcon#wrote, iclass 31, count 0 2006.201.03:32:18.89#ibcon#about to read 3, iclass 31, count 0 2006.201.03:32:18.92#ibcon#read 3, iclass 31, count 0 2006.201.03:32:18.92#ibcon#about to read 4, iclass 31, count 0 2006.201.03:32:18.92#ibcon#read 4, iclass 31, count 0 2006.201.03:32:18.92#ibcon#about to read 5, iclass 31, count 0 2006.201.03:32:18.92#ibcon#read 5, iclass 31, count 0 2006.201.03:32:18.92#ibcon#about to read 6, iclass 31, count 0 2006.201.03:32:18.92#ibcon#read 6, iclass 31, count 0 2006.201.03:32:18.92#ibcon#end of sib2, iclass 31, count 0 2006.201.03:32:18.92#ibcon#*after write, iclass 31, count 0 2006.201.03:32:18.92#ibcon#*before return 0, iclass 31, count 0 2006.201.03:32:18.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:18.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:18.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.03:32:18.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.03:32:18.92$vck44/valo=4,624.99 2006.201.03:32:18.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.03:32:18.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.03:32:18.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:18.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:18.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:18.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:18.92#ibcon#enter wrdev, iclass 33, count 0 2006.201.03:32:18.92#ibcon#first serial, iclass 33, count 0 2006.201.03:32:18.92#ibcon#enter sib2, iclass 33, count 0 2006.201.03:32:18.92#ibcon#flushed, iclass 33, count 0 2006.201.03:32:18.92#ibcon#about to write, iclass 33, count 0 2006.201.03:32:18.92#ibcon#wrote, iclass 33, count 0 2006.201.03:32:18.92#ibcon#about to read 3, iclass 33, count 0 2006.201.03:32:18.94#ibcon#read 3, iclass 33, count 0 2006.201.03:32:18.94#ibcon#about to read 4, iclass 33, count 0 2006.201.03:32:18.94#ibcon#read 4, iclass 33, count 0 2006.201.03:32:18.94#ibcon#about to read 5, iclass 33, count 0 2006.201.03:32:18.94#ibcon#read 5, iclass 33, count 0 2006.201.03:32:18.94#ibcon#about to read 6, iclass 33, count 0 2006.201.03:32:18.94#ibcon#read 6, iclass 33, count 0 2006.201.03:32:18.94#ibcon#end of sib2, iclass 33, count 0 2006.201.03:32:18.94#ibcon#*mode == 0, iclass 33, count 0 2006.201.03:32:18.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.03:32:18.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:32:18.94#ibcon#*before write, iclass 33, count 0 2006.201.03:32:18.94#ibcon#enter sib2, iclass 33, count 0 2006.201.03:32:18.94#ibcon#flushed, iclass 33, count 0 2006.201.03:32:18.94#ibcon#about to write, iclass 33, count 0 2006.201.03:32:18.94#ibcon#wrote, iclass 33, count 0 2006.201.03:32:18.94#ibcon#about to read 3, iclass 33, count 0 2006.201.03:32:18.98#ibcon#read 3, iclass 33, count 0 2006.201.03:32:18.98#ibcon#about to read 4, iclass 33, count 0 2006.201.03:32:18.98#ibcon#read 4, iclass 33, count 0 2006.201.03:32:18.98#ibcon#about to read 5, iclass 33, count 0 2006.201.03:32:18.98#ibcon#read 5, iclass 33, count 0 2006.201.03:32:18.98#ibcon#about to read 6, iclass 33, count 0 2006.201.03:32:18.98#ibcon#read 6, iclass 33, count 0 2006.201.03:32:18.98#ibcon#end of sib2, iclass 33, count 0 2006.201.03:32:18.98#ibcon#*after write, iclass 33, count 0 2006.201.03:32:18.98#ibcon#*before return 0, iclass 33, count 0 2006.201.03:32:18.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:18.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:18.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.03:32:18.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.03:32:18.98$vck44/va=4,7 2006.201.03:32:18.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.03:32:18.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.03:32:18.98#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:18.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:19.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:19.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:19.04#ibcon#enter wrdev, iclass 35, count 2 2006.201.03:32:19.04#ibcon#first serial, iclass 35, count 2 2006.201.03:32:19.04#ibcon#enter sib2, iclass 35, count 2 2006.201.03:32:19.04#ibcon#flushed, iclass 35, count 2 2006.201.03:32:19.04#ibcon#about to write, iclass 35, count 2 2006.201.03:32:19.04#ibcon#wrote, iclass 35, count 2 2006.201.03:32:19.04#ibcon#about to read 3, iclass 35, count 2 2006.201.03:32:19.06#ibcon#read 3, iclass 35, count 2 2006.201.03:32:19.06#ibcon#about to read 4, iclass 35, count 2 2006.201.03:32:19.06#ibcon#read 4, iclass 35, count 2 2006.201.03:32:19.06#ibcon#about to read 5, iclass 35, count 2 2006.201.03:32:19.06#ibcon#read 5, iclass 35, count 2 2006.201.03:32:19.06#ibcon#about to read 6, iclass 35, count 2 2006.201.03:32:19.06#ibcon#read 6, iclass 35, count 2 2006.201.03:32:19.06#ibcon#end of sib2, iclass 35, count 2 2006.201.03:32:19.06#ibcon#*mode == 0, iclass 35, count 2 2006.201.03:32:19.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.03:32:19.06#ibcon#[25=AT04-07\r\n] 2006.201.03:32:19.06#ibcon#*before write, iclass 35, count 2 2006.201.03:32:19.06#ibcon#enter sib2, iclass 35, count 2 2006.201.03:32:19.06#ibcon#flushed, iclass 35, count 2 2006.201.03:32:19.06#ibcon#about to write, iclass 35, count 2 2006.201.03:32:19.06#ibcon#wrote, iclass 35, count 2 2006.201.03:32:19.06#ibcon#about to read 3, iclass 35, count 2 2006.201.03:32:19.09#ibcon#read 3, iclass 35, count 2 2006.201.03:32:19.09#ibcon#about to read 4, iclass 35, count 2 2006.201.03:32:19.09#ibcon#read 4, iclass 35, count 2 2006.201.03:32:19.09#ibcon#about to read 5, iclass 35, count 2 2006.201.03:32:19.09#ibcon#read 5, iclass 35, count 2 2006.201.03:32:19.09#ibcon#about to read 6, iclass 35, count 2 2006.201.03:32:19.09#ibcon#read 6, iclass 35, count 2 2006.201.03:32:19.09#ibcon#end of sib2, iclass 35, count 2 2006.201.03:32:19.09#ibcon#*after write, iclass 35, count 2 2006.201.03:32:19.09#ibcon#*before return 0, iclass 35, count 2 2006.201.03:32:19.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:19.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:19.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.03:32:19.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:19.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:19.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:19.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:19.21#ibcon#enter wrdev, iclass 35, count 0 2006.201.03:32:19.21#ibcon#first serial, iclass 35, count 0 2006.201.03:32:19.21#ibcon#enter sib2, iclass 35, count 0 2006.201.03:32:19.21#ibcon#flushed, iclass 35, count 0 2006.201.03:32:19.21#ibcon#about to write, iclass 35, count 0 2006.201.03:32:19.21#ibcon#wrote, iclass 35, count 0 2006.201.03:32:19.21#ibcon#about to read 3, iclass 35, count 0 2006.201.03:32:19.23#ibcon#read 3, iclass 35, count 0 2006.201.03:32:19.23#ibcon#about to read 4, iclass 35, count 0 2006.201.03:32:19.23#ibcon#read 4, iclass 35, count 0 2006.201.03:32:19.23#ibcon#about to read 5, iclass 35, count 0 2006.201.03:32:19.23#ibcon#read 5, iclass 35, count 0 2006.201.03:32:19.23#ibcon#about to read 6, iclass 35, count 0 2006.201.03:32:19.23#ibcon#read 6, iclass 35, count 0 2006.201.03:32:19.23#ibcon#end of sib2, iclass 35, count 0 2006.201.03:32:19.23#ibcon#*mode == 0, iclass 35, count 0 2006.201.03:32:19.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.03:32:19.23#ibcon#[25=USB\r\n] 2006.201.03:32:19.23#ibcon#*before write, iclass 35, count 0 2006.201.03:32:19.23#ibcon#enter sib2, iclass 35, count 0 2006.201.03:32:19.23#ibcon#flushed, iclass 35, count 0 2006.201.03:32:19.23#ibcon#about to write, iclass 35, count 0 2006.201.03:32:19.23#ibcon#wrote, iclass 35, count 0 2006.201.03:32:19.23#ibcon#about to read 3, iclass 35, count 0 2006.201.03:32:19.26#ibcon#read 3, iclass 35, count 0 2006.201.03:32:19.26#ibcon#about to read 4, iclass 35, count 0 2006.201.03:32:19.26#ibcon#read 4, iclass 35, count 0 2006.201.03:32:19.26#ibcon#about to read 5, iclass 35, count 0 2006.201.03:32:19.26#ibcon#read 5, iclass 35, count 0 2006.201.03:32:19.26#ibcon#about to read 6, iclass 35, count 0 2006.201.03:32:19.26#ibcon#read 6, iclass 35, count 0 2006.201.03:32:19.26#ibcon#end of sib2, iclass 35, count 0 2006.201.03:32:19.26#ibcon#*after write, iclass 35, count 0 2006.201.03:32:19.26#ibcon#*before return 0, iclass 35, count 0 2006.201.03:32:19.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:19.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:19.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.03:32:19.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.03:32:19.26$vck44/valo=5,734.99 2006.201.03:32:19.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.03:32:19.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.03:32:19.26#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:19.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:19.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:19.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:19.26#ibcon#enter wrdev, iclass 37, count 0 2006.201.03:32:19.26#ibcon#first serial, iclass 37, count 0 2006.201.03:32:19.26#ibcon#enter sib2, iclass 37, count 0 2006.201.03:32:19.26#ibcon#flushed, iclass 37, count 0 2006.201.03:32:19.26#ibcon#about to write, iclass 37, count 0 2006.201.03:32:19.26#ibcon#wrote, iclass 37, count 0 2006.201.03:32:19.26#ibcon#about to read 3, iclass 37, count 0 2006.201.03:32:19.28#ibcon#read 3, iclass 37, count 0 2006.201.03:32:19.28#ibcon#about to read 4, iclass 37, count 0 2006.201.03:32:19.28#ibcon#read 4, iclass 37, count 0 2006.201.03:32:19.28#ibcon#about to read 5, iclass 37, count 0 2006.201.03:32:19.28#ibcon#read 5, iclass 37, count 0 2006.201.03:32:19.28#ibcon#about to read 6, iclass 37, count 0 2006.201.03:32:19.28#ibcon#read 6, iclass 37, count 0 2006.201.03:32:19.28#ibcon#end of sib2, iclass 37, count 0 2006.201.03:32:19.28#ibcon#*mode == 0, iclass 37, count 0 2006.201.03:32:19.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.03:32:19.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:32:19.28#ibcon#*before write, iclass 37, count 0 2006.201.03:32:19.28#ibcon#enter sib2, iclass 37, count 0 2006.201.03:32:19.28#ibcon#flushed, iclass 37, count 0 2006.201.03:32:19.28#ibcon#about to write, iclass 37, count 0 2006.201.03:32:19.28#ibcon#wrote, iclass 37, count 0 2006.201.03:32:19.28#ibcon#about to read 3, iclass 37, count 0 2006.201.03:32:19.32#ibcon#read 3, iclass 37, count 0 2006.201.03:32:19.32#ibcon#about to read 4, iclass 37, count 0 2006.201.03:32:19.32#ibcon#read 4, iclass 37, count 0 2006.201.03:32:19.32#ibcon#about to read 5, iclass 37, count 0 2006.201.03:32:19.32#ibcon#read 5, iclass 37, count 0 2006.201.03:32:19.32#ibcon#about to read 6, iclass 37, count 0 2006.201.03:32:19.32#ibcon#read 6, iclass 37, count 0 2006.201.03:32:19.32#ibcon#end of sib2, iclass 37, count 0 2006.201.03:32:19.32#ibcon#*after write, iclass 37, count 0 2006.201.03:32:19.32#ibcon#*before return 0, iclass 37, count 0 2006.201.03:32:19.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:19.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:19.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.03:32:19.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.03:32:19.32$vck44/va=5,4 2006.201.03:32:19.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.03:32:19.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.03:32:19.32#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:19.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:19.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:19.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:19.38#ibcon#enter wrdev, iclass 39, count 2 2006.201.03:32:19.38#ibcon#first serial, iclass 39, count 2 2006.201.03:32:19.38#ibcon#enter sib2, iclass 39, count 2 2006.201.03:32:19.38#ibcon#flushed, iclass 39, count 2 2006.201.03:32:19.38#ibcon#about to write, iclass 39, count 2 2006.201.03:32:19.38#ibcon#wrote, iclass 39, count 2 2006.201.03:32:19.38#ibcon#about to read 3, iclass 39, count 2 2006.201.03:32:19.40#ibcon#read 3, iclass 39, count 2 2006.201.03:32:19.40#ibcon#about to read 4, iclass 39, count 2 2006.201.03:32:19.40#ibcon#read 4, iclass 39, count 2 2006.201.03:32:19.40#ibcon#about to read 5, iclass 39, count 2 2006.201.03:32:19.40#ibcon#read 5, iclass 39, count 2 2006.201.03:32:19.40#ibcon#about to read 6, iclass 39, count 2 2006.201.03:32:19.40#ibcon#read 6, iclass 39, count 2 2006.201.03:32:19.40#ibcon#end of sib2, iclass 39, count 2 2006.201.03:32:19.40#ibcon#*mode == 0, iclass 39, count 2 2006.201.03:32:19.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.03:32:19.40#ibcon#[25=AT05-04\r\n] 2006.201.03:32:19.40#ibcon#*before write, iclass 39, count 2 2006.201.03:32:19.40#ibcon#enter sib2, iclass 39, count 2 2006.201.03:32:19.40#ibcon#flushed, iclass 39, count 2 2006.201.03:32:19.40#ibcon#about to write, iclass 39, count 2 2006.201.03:32:19.40#ibcon#wrote, iclass 39, count 2 2006.201.03:32:19.40#ibcon#about to read 3, iclass 39, count 2 2006.201.03:32:19.43#ibcon#read 3, iclass 39, count 2 2006.201.03:32:19.43#ibcon#about to read 4, iclass 39, count 2 2006.201.03:32:19.43#ibcon#read 4, iclass 39, count 2 2006.201.03:32:19.43#ibcon#about to read 5, iclass 39, count 2 2006.201.03:32:19.43#ibcon#read 5, iclass 39, count 2 2006.201.03:32:19.43#ibcon#about to read 6, iclass 39, count 2 2006.201.03:32:19.43#ibcon#read 6, iclass 39, count 2 2006.201.03:32:19.43#ibcon#end of sib2, iclass 39, count 2 2006.201.03:32:19.43#ibcon#*after write, iclass 39, count 2 2006.201.03:32:19.43#ibcon#*before return 0, iclass 39, count 2 2006.201.03:32:19.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:19.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:19.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.03:32:19.43#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:19.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:19.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:19.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:19.55#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:32:19.55#ibcon#first serial, iclass 39, count 0 2006.201.03:32:19.55#ibcon#enter sib2, iclass 39, count 0 2006.201.03:32:19.55#ibcon#flushed, iclass 39, count 0 2006.201.03:32:19.55#ibcon#about to write, iclass 39, count 0 2006.201.03:32:19.55#ibcon#wrote, iclass 39, count 0 2006.201.03:32:19.55#ibcon#about to read 3, iclass 39, count 0 2006.201.03:32:19.57#ibcon#read 3, iclass 39, count 0 2006.201.03:32:19.57#ibcon#about to read 4, iclass 39, count 0 2006.201.03:32:19.57#ibcon#read 4, iclass 39, count 0 2006.201.03:32:19.57#ibcon#about to read 5, iclass 39, count 0 2006.201.03:32:19.57#ibcon#read 5, iclass 39, count 0 2006.201.03:32:19.57#ibcon#about to read 6, iclass 39, count 0 2006.201.03:32:19.57#ibcon#read 6, iclass 39, count 0 2006.201.03:32:19.57#ibcon#end of sib2, iclass 39, count 0 2006.201.03:32:19.57#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:32:19.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:32:19.57#ibcon#[25=USB\r\n] 2006.201.03:32:19.57#ibcon#*before write, iclass 39, count 0 2006.201.03:32:19.57#ibcon#enter sib2, iclass 39, count 0 2006.201.03:32:19.57#ibcon#flushed, iclass 39, count 0 2006.201.03:32:19.57#ibcon#about to write, iclass 39, count 0 2006.201.03:32:19.57#ibcon#wrote, iclass 39, count 0 2006.201.03:32:19.57#ibcon#about to read 3, iclass 39, count 0 2006.201.03:32:19.60#ibcon#read 3, iclass 39, count 0 2006.201.03:32:19.60#ibcon#about to read 4, iclass 39, count 0 2006.201.03:32:19.60#ibcon#read 4, iclass 39, count 0 2006.201.03:32:19.60#ibcon#about to read 5, iclass 39, count 0 2006.201.03:32:19.60#ibcon#read 5, iclass 39, count 0 2006.201.03:32:19.60#ibcon#about to read 6, iclass 39, count 0 2006.201.03:32:19.60#ibcon#read 6, iclass 39, count 0 2006.201.03:32:19.60#ibcon#end of sib2, iclass 39, count 0 2006.201.03:32:19.60#ibcon#*after write, iclass 39, count 0 2006.201.03:32:19.60#ibcon#*before return 0, iclass 39, count 0 2006.201.03:32:19.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:19.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:19.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:32:19.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:32:19.60$vck44/valo=6,814.99 2006.201.03:32:19.60#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.03:32:19.60#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.03:32:19.60#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:19.60#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:19.60#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:19.60#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:19.60#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:32:19.60#ibcon#first serial, iclass 2, count 0 2006.201.03:32:19.60#ibcon#enter sib2, iclass 2, count 0 2006.201.03:32:19.60#ibcon#flushed, iclass 2, count 0 2006.201.03:32:19.60#ibcon#about to write, iclass 2, count 0 2006.201.03:32:19.60#ibcon#wrote, iclass 2, count 0 2006.201.03:32:19.60#ibcon#about to read 3, iclass 2, count 0 2006.201.03:32:19.62#ibcon#read 3, iclass 2, count 0 2006.201.03:32:19.62#ibcon#about to read 4, iclass 2, count 0 2006.201.03:32:19.62#ibcon#read 4, iclass 2, count 0 2006.201.03:32:19.62#ibcon#about to read 5, iclass 2, count 0 2006.201.03:32:19.62#ibcon#read 5, iclass 2, count 0 2006.201.03:32:19.62#ibcon#about to read 6, iclass 2, count 0 2006.201.03:32:19.62#ibcon#read 6, iclass 2, count 0 2006.201.03:32:19.62#ibcon#end of sib2, iclass 2, count 0 2006.201.03:32:19.62#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:32:19.62#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:32:19.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:32:19.62#ibcon#*before write, iclass 2, count 0 2006.201.03:32:19.62#ibcon#enter sib2, iclass 2, count 0 2006.201.03:32:19.62#ibcon#flushed, iclass 2, count 0 2006.201.03:32:19.62#ibcon#about to write, iclass 2, count 0 2006.201.03:32:19.62#ibcon#wrote, iclass 2, count 0 2006.201.03:32:19.62#ibcon#about to read 3, iclass 2, count 0 2006.201.03:32:19.66#ibcon#read 3, iclass 2, count 0 2006.201.03:32:19.66#ibcon#about to read 4, iclass 2, count 0 2006.201.03:32:19.66#ibcon#read 4, iclass 2, count 0 2006.201.03:32:19.66#ibcon#about to read 5, iclass 2, count 0 2006.201.03:32:19.66#ibcon#read 5, iclass 2, count 0 2006.201.03:32:19.66#ibcon#about to read 6, iclass 2, count 0 2006.201.03:32:19.66#ibcon#read 6, iclass 2, count 0 2006.201.03:32:19.66#ibcon#end of sib2, iclass 2, count 0 2006.201.03:32:19.66#ibcon#*after write, iclass 2, count 0 2006.201.03:32:19.66#ibcon#*before return 0, iclass 2, count 0 2006.201.03:32:19.66#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:19.66#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:19.66#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:32:19.66#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:32:19.66$vck44/va=6,5 2006.201.03:32:19.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.03:32:19.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.03:32:19.66#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:19.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:19.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:19.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:19.72#ibcon#enter wrdev, iclass 5, count 2 2006.201.03:32:19.72#ibcon#first serial, iclass 5, count 2 2006.201.03:32:19.72#ibcon#enter sib2, iclass 5, count 2 2006.201.03:32:19.72#ibcon#flushed, iclass 5, count 2 2006.201.03:32:19.72#ibcon#about to write, iclass 5, count 2 2006.201.03:32:19.72#ibcon#wrote, iclass 5, count 2 2006.201.03:32:19.72#ibcon#about to read 3, iclass 5, count 2 2006.201.03:32:19.74#ibcon#read 3, iclass 5, count 2 2006.201.03:32:19.74#ibcon#about to read 4, iclass 5, count 2 2006.201.03:32:19.74#ibcon#read 4, iclass 5, count 2 2006.201.03:32:19.74#ibcon#about to read 5, iclass 5, count 2 2006.201.03:32:19.74#ibcon#read 5, iclass 5, count 2 2006.201.03:32:19.74#ibcon#about to read 6, iclass 5, count 2 2006.201.03:32:19.74#ibcon#read 6, iclass 5, count 2 2006.201.03:32:19.74#ibcon#end of sib2, iclass 5, count 2 2006.201.03:32:19.74#ibcon#*mode == 0, iclass 5, count 2 2006.201.03:32:19.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.03:32:19.74#ibcon#[25=AT06-05\r\n] 2006.201.03:32:19.74#ibcon#*before write, iclass 5, count 2 2006.201.03:32:19.74#ibcon#enter sib2, iclass 5, count 2 2006.201.03:32:19.74#ibcon#flushed, iclass 5, count 2 2006.201.03:32:19.74#ibcon#about to write, iclass 5, count 2 2006.201.03:32:19.74#ibcon#wrote, iclass 5, count 2 2006.201.03:32:19.74#ibcon#about to read 3, iclass 5, count 2 2006.201.03:32:19.77#ibcon#read 3, iclass 5, count 2 2006.201.03:32:19.77#ibcon#about to read 4, iclass 5, count 2 2006.201.03:32:19.77#ibcon#read 4, iclass 5, count 2 2006.201.03:32:19.77#ibcon#about to read 5, iclass 5, count 2 2006.201.03:32:19.77#ibcon#read 5, iclass 5, count 2 2006.201.03:32:19.77#ibcon#about to read 6, iclass 5, count 2 2006.201.03:32:19.77#ibcon#read 6, iclass 5, count 2 2006.201.03:32:19.77#ibcon#end of sib2, iclass 5, count 2 2006.201.03:32:19.77#ibcon#*after write, iclass 5, count 2 2006.201.03:32:19.77#ibcon#*before return 0, iclass 5, count 2 2006.201.03:32:19.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:19.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:19.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.03:32:19.77#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:19.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:19.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:19.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:19.89#ibcon#enter wrdev, iclass 5, count 0 2006.201.03:32:19.89#ibcon#first serial, iclass 5, count 0 2006.201.03:32:19.89#ibcon#enter sib2, iclass 5, count 0 2006.201.03:32:19.89#ibcon#flushed, iclass 5, count 0 2006.201.03:32:19.89#ibcon#about to write, iclass 5, count 0 2006.201.03:32:19.89#ibcon#wrote, iclass 5, count 0 2006.201.03:32:19.89#ibcon#about to read 3, iclass 5, count 0 2006.201.03:32:19.91#ibcon#read 3, iclass 5, count 0 2006.201.03:32:19.91#ibcon#about to read 4, iclass 5, count 0 2006.201.03:32:19.91#ibcon#read 4, iclass 5, count 0 2006.201.03:32:19.91#ibcon#about to read 5, iclass 5, count 0 2006.201.03:32:19.91#ibcon#read 5, iclass 5, count 0 2006.201.03:32:19.91#ibcon#about to read 6, iclass 5, count 0 2006.201.03:32:19.91#ibcon#read 6, iclass 5, count 0 2006.201.03:32:19.91#ibcon#end of sib2, iclass 5, count 0 2006.201.03:32:19.91#ibcon#*mode == 0, iclass 5, count 0 2006.201.03:32:19.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.03:32:19.91#ibcon#[25=USB\r\n] 2006.201.03:32:19.91#ibcon#*before write, iclass 5, count 0 2006.201.03:32:19.91#ibcon#enter sib2, iclass 5, count 0 2006.201.03:32:19.91#ibcon#flushed, iclass 5, count 0 2006.201.03:32:19.91#ibcon#about to write, iclass 5, count 0 2006.201.03:32:19.91#ibcon#wrote, iclass 5, count 0 2006.201.03:32:19.91#ibcon#about to read 3, iclass 5, count 0 2006.201.03:32:19.94#ibcon#read 3, iclass 5, count 0 2006.201.03:32:19.94#ibcon#about to read 4, iclass 5, count 0 2006.201.03:32:19.94#ibcon#read 4, iclass 5, count 0 2006.201.03:32:19.94#ibcon#about to read 5, iclass 5, count 0 2006.201.03:32:19.94#ibcon#read 5, iclass 5, count 0 2006.201.03:32:19.94#ibcon#about to read 6, iclass 5, count 0 2006.201.03:32:19.94#ibcon#read 6, iclass 5, count 0 2006.201.03:32:19.94#ibcon#end of sib2, iclass 5, count 0 2006.201.03:32:19.94#ibcon#*after write, iclass 5, count 0 2006.201.03:32:19.94#ibcon#*before return 0, iclass 5, count 0 2006.201.03:32:19.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:19.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:19.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.03:32:19.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.03:32:19.94$vck44/valo=7,864.99 2006.201.03:32:19.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.03:32:19.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.03:32:19.94#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:19.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:19.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:19.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:19.94#ibcon#enter wrdev, iclass 7, count 0 2006.201.03:32:19.94#ibcon#first serial, iclass 7, count 0 2006.201.03:32:19.94#ibcon#enter sib2, iclass 7, count 0 2006.201.03:32:19.94#ibcon#flushed, iclass 7, count 0 2006.201.03:32:19.94#ibcon#about to write, iclass 7, count 0 2006.201.03:32:19.94#ibcon#wrote, iclass 7, count 0 2006.201.03:32:19.94#ibcon#about to read 3, iclass 7, count 0 2006.201.03:32:19.96#ibcon#read 3, iclass 7, count 0 2006.201.03:32:19.96#ibcon#about to read 4, iclass 7, count 0 2006.201.03:32:19.96#ibcon#read 4, iclass 7, count 0 2006.201.03:32:19.96#ibcon#about to read 5, iclass 7, count 0 2006.201.03:32:19.96#ibcon#read 5, iclass 7, count 0 2006.201.03:32:19.96#ibcon#about to read 6, iclass 7, count 0 2006.201.03:32:19.96#ibcon#read 6, iclass 7, count 0 2006.201.03:32:19.96#ibcon#end of sib2, iclass 7, count 0 2006.201.03:32:19.96#ibcon#*mode == 0, iclass 7, count 0 2006.201.03:32:19.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.03:32:19.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:32:19.96#ibcon#*before write, iclass 7, count 0 2006.201.03:32:19.96#ibcon#enter sib2, iclass 7, count 0 2006.201.03:32:19.96#ibcon#flushed, iclass 7, count 0 2006.201.03:32:19.96#ibcon#about to write, iclass 7, count 0 2006.201.03:32:19.96#ibcon#wrote, iclass 7, count 0 2006.201.03:32:19.96#ibcon#about to read 3, iclass 7, count 0 2006.201.03:32:20.00#ibcon#read 3, iclass 7, count 0 2006.201.03:32:20.00#ibcon#about to read 4, iclass 7, count 0 2006.201.03:32:20.00#ibcon#read 4, iclass 7, count 0 2006.201.03:32:20.00#ibcon#about to read 5, iclass 7, count 0 2006.201.03:32:20.00#ibcon#read 5, iclass 7, count 0 2006.201.03:32:20.00#ibcon#about to read 6, iclass 7, count 0 2006.201.03:32:20.00#ibcon#read 6, iclass 7, count 0 2006.201.03:32:20.00#ibcon#end of sib2, iclass 7, count 0 2006.201.03:32:20.00#ibcon#*after write, iclass 7, count 0 2006.201.03:32:20.00#ibcon#*before return 0, iclass 7, count 0 2006.201.03:32:20.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:20.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:20.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.03:32:20.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.03:32:20.00$vck44/va=7,5 2006.201.03:32:20.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.03:32:20.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.03:32:20.00#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:20.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:20.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:20.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:20.06#ibcon#enter wrdev, iclass 11, count 2 2006.201.03:32:20.06#ibcon#first serial, iclass 11, count 2 2006.201.03:32:20.06#ibcon#enter sib2, iclass 11, count 2 2006.201.03:32:20.06#ibcon#flushed, iclass 11, count 2 2006.201.03:32:20.06#ibcon#about to write, iclass 11, count 2 2006.201.03:32:20.06#ibcon#wrote, iclass 11, count 2 2006.201.03:32:20.06#ibcon#about to read 3, iclass 11, count 2 2006.201.03:32:20.08#ibcon#read 3, iclass 11, count 2 2006.201.03:32:20.08#ibcon#about to read 4, iclass 11, count 2 2006.201.03:32:20.08#ibcon#read 4, iclass 11, count 2 2006.201.03:32:20.08#ibcon#about to read 5, iclass 11, count 2 2006.201.03:32:20.08#ibcon#read 5, iclass 11, count 2 2006.201.03:32:20.08#ibcon#about to read 6, iclass 11, count 2 2006.201.03:32:20.08#ibcon#read 6, iclass 11, count 2 2006.201.03:32:20.08#ibcon#end of sib2, iclass 11, count 2 2006.201.03:32:20.08#ibcon#*mode == 0, iclass 11, count 2 2006.201.03:32:20.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.03:32:20.08#ibcon#[25=AT07-05\r\n] 2006.201.03:32:20.08#ibcon#*before write, iclass 11, count 2 2006.201.03:32:20.08#ibcon#enter sib2, iclass 11, count 2 2006.201.03:32:20.08#ibcon#flushed, iclass 11, count 2 2006.201.03:32:20.08#ibcon#about to write, iclass 11, count 2 2006.201.03:32:20.08#ibcon#wrote, iclass 11, count 2 2006.201.03:32:20.08#ibcon#about to read 3, iclass 11, count 2 2006.201.03:32:20.11#ibcon#read 3, iclass 11, count 2 2006.201.03:32:20.11#ibcon#about to read 4, iclass 11, count 2 2006.201.03:32:20.11#ibcon#read 4, iclass 11, count 2 2006.201.03:32:20.11#ibcon#about to read 5, iclass 11, count 2 2006.201.03:32:20.11#ibcon#read 5, iclass 11, count 2 2006.201.03:32:20.11#ibcon#about to read 6, iclass 11, count 2 2006.201.03:32:20.11#ibcon#read 6, iclass 11, count 2 2006.201.03:32:20.11#ibcon#end of sib2, iclass 11, count 2 2006.201.03:32:20.11#ibcon#*after write, iclass 11, count 2 2006.201.03:32:20.11#ibcon#*before return 0, iclass 11, count 2 2006.201.03:32:20.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:20.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:20.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.03:32:20.11#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:20.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:20.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:20.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:20.23#ibcon#enter wrdev, iclass 11, count 0 2006.201.03:32:20.23#ibcon#first serial, iclass 11, count 0 2006.201.03:32:20.23#ibcon#enter sib2, iclass 11, count 0 2006.201.03:32:20.23#ibcon#flushed, iclass 11, count 0 2006.201.03:32:20.23#ibcon#about to write, iclass 11, count 0 2006.201.03:32:20.23#ibcon#wrote, iclass 11, count 0 2006.201.03:32:20.23#ibcon#about to read 3, iclass 11, count 0 2006.201.03:32:20.25#ibcon#read 3, iclass 11, count 0 2006.201.03:32:20.25#ibcon#about to read 4, iclass 11, count 0 2006.201.03:32:20.25#ibcon#read 4, iclass 11, count 0 2006.201.03:32:20.25#ibcon#about to read 5, iclass 11, count 0 2006.201.03:32:20.25#ibcon#read 5, iclass 11, count 0 2006.201.03:32:20.25#ibcon#about to read 6, iclass 11, count 0 2006.201.03:32:20.25#ibcon#read 6, iclass 11, count 0 2006.201.03:32:20.25#ibcon#end of sib2, iclass 11, count 0 2006.201.03:32:20.25#ibcon#*mode == 0, iclass 11, count 0 2006.201.03:32:20.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.03:32:20.25#ibcon#[25=USB\r\n] 2006.201.03:32:20.25#ibcon#*before write, iclass 11, count 0 2006.201.03:32:20.25#ibcon#enter sib2, iclass 11, count 0 2006.201.03:32:20.25#ibcon#flushed, iclass 11, count 0 2006.201.03:32:20.25#ibcon#about to write, iclass 11, count 0 2006.201.03:32:20.25#ibcon#wrote, iclass 11, count 0 2006.201.03:32:20.25#ibcon#about to read 3, iclass 11, count 0 2006.201.03:32:20.28#ibcon#read 3, iclass 11, count 0 2006.201.03:32:20.28#ibcon#about to read 4, iclass 11, count 0 2006.201.03:32:20.28#ibcon#read 4, iclass 11, count 0 2006.201.03:32:20.28#ibcon#about to read 5, iclass 11, count 0 2006.201.03:32:20.28#ibcon#read 5, iclass 11, count 0 2006.201.03:32:20.28#ibcon#about to read 6, iclass 11, count 0 2006.201.03:32:20.28#ibcon#read 6, iclass 11, count 0 2006.201.03:32:20.28#ibcon#end of sib2, iclass 11, count 0 2006.201.03:32:20.28#ibcon#*after write, iclass 11, count 0 2006.201.03:32:20.28#ibcon#*before return 0, iclass 11, count 0 2006.201.03:32:20.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:20.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:20.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.03:32:20.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.03:32:20.28$vck44/valo=8,884.99 2006.201.03:32:20.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.03:32:20.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.03:32:20.28#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:20.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:20.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:20.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:20.28#ibcon#enter wrdev, iclass 13, count 0 2006.201.03:32:20.28#ibcon#first serial, iclass 13, count 0 2006.201.03:32:20.28#ibcon#enter sib2, iclass 13, count 0 2006.201.03:32:20.28#ibcon#flushed, iclass 13, count 0 2006.201.03:32:20.28#ibcon#about to write, iclass 13, count 0 2006.201.03:32:20.28#ibcon#wrote, iclass 13, count 0 2006.201.03:32:20.28#ibcon#about to read 3, iclass 13, count 0 2006.201.03:32:20.30#ibcon#read 3, iclass 13, count 0 2006.201.03:32:20.30#ibcon#about to read 4, iclass 13, count 0 2006.201.03:32:20.30#ibcon#read 4, iclass 13, count 0 2006.201.03:32:20.30#ibcon#about to read 5, iclass 13, count 0 2006.201.03:32:20.30#ibcon#read 5, iclass 13, count 0 2006.201.03:32:20.30#ibcon#about to read 6, iclass 13, count 0 2006.201.03:32:20.30#ibcon#read 6, iclass 13, count 0 2006.201.03:32:20.30#ibcon#end of sib2, iclass 13, count 0 2006.201.03:32:20.30#ibcon#*mode == 0, iclass 13, count 0 2006.201.03:32:20.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.03:32:20.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:32:20.30#ibcon#*before write, iclass 13, count 0 2006.201.03:32:20.30#ibcon#enter sib2, iclass 13, count 0 2006.201.03:32:20.30#ibcon#flushed, iclass 13, count 0 2006.201.03:32:20.30#ibcon#about to write, iclass 13, count 0 2006.201.03:32:20.30#ibcon#wrote, iclass 13, count 0 2006.201.03:32:20.30#ibcon#about to read 3, iclass 13, count 0 2006.201.03:32:20.34#ibcon#read 3, iclass 13, count 0 2006.201.03:32:20.34#ibcon#about to read 4, iclass 13, count 0 2006.201.03:32:20.34#ibcon#read 4, iclass 13, count 0 2006.201.03:32:20.34#ibcon#about to read 5, iclass 13, count 0 2006.201.03:32:20.34#ibcon#read 5, iclass 13, count 0 2006.201.03:32:20.34#ibcon#about to read 6, iclass 13, count 0 2006.201.03:32:20.34#ibcon#read 6, iclass 13, count 0 2006.201.03:32:20.34#ibcon#end of sib2, iclass 13, count 0 2006.201.03:32:20.34#ibcon#*after write, iclass 13, count 0 2006.201.03:32:20.34#ibcon#*before return 0, iclass 13, count 0 2006.201.03:32:20.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:20.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:20.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.03:32:20.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.03:32:20.34$vck44/va=8,4 2006.201.03:32:20.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.03:32:20.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.03:32:20.34#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:20.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:32:20.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:32:20.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:32:20.40#ibcon#enter wrdev, iclass 15, count 2 2006.201.03:32:20.40#ibcon#first serial, iclass 15, count 2 2006.201.03:32:20.40#ibcon#enter sib2, iclass 15, count 2 2006.201.03:32:20.40#ibcon#flushed, iclass 15, count 2 2006.201.03:32:20.40#ibcon#about to write, iclass 15, count 2 2006.201.03:32:20.40#ibcon#wrote, iclass 15, count 2 2006.201.03:32:20.40#ibcon#about to read 3, iclass 15, count 2 2006.201.03:32:20.42#ibcon#read 3, iclass 15, count 2 2006.201.03:32:20.42#ibcon#about to read 4, iclass 15, count 2 2006.201.03:32:20.42#ibcon#read 4, iclass 15, count 2 2006.201.03:32:20.42#ibcon#about to read 5, iclass 15, count 2 2006.201.03:32:20.42#ibcon#read 5, iclass 15, count 2 2006.201.03:32:20.42#ibcon#about to read 6, iclass 15, count 2 2006.201.03:32:20.42#ibcon#read 6, iclass 15, count 2 2006.201.03:32:20.42#ibcon#end of sib2, iclass 15, count 2 2006.201.03:32:20.42#ibcon#*mode == 0, iclass 15, count 2 2006.201.03:32:20.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.03:32:20.42#ibcon#[25=AT08-04\r\n] 2006.201.03:32:20.42#ibcon#*before write, iclass 15, count 2 2006.201.03:32:20.42#ibcon#enter sib2, iclass 15, count 2 2006.201.03:32:20.42#ibcon#flushed, iclass 15, count 2 2006.201.03:32:20.42#ibcon#about to write, iclass 15, count 2 2006.201.03:32:20.42#ibcon#wrote, iclass 15, count 2 2006.201.03:32:20.42#ibcon#about to read 3, iclass 15, count 2 2006.201.03:32:20.45#ibcon#read 3, iclass 15, count 2 2006.201.03:32:20.45#ibcon#about to read 4, iclass 15, count 2 2006.201.03:32:20.45#ibcon#read 4, iclass 15, count 2 2006.201.03:32:20.45#ibcon#about to read 5, iclass 15, count 2 2006.201.03:32:20.45#ibcon#read 5, iclass 15, count 2 2006.201.03:32:20.45#ibcon#about to read 6, iclass 15, count 2 2006.201.03:32:20.45#ibcon#read 6, iclass 15, count 2 2006.201.03:32:20.45#ibcon#end of sib2, iclass 15, count 2 2006.201.03:32:20.45#ibcon#*after write, iclass 15, count 2 2006.201.03:32:20.45#ibcon#*before return 0, iclass 15, count 2 2006.201.03:32:20.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:32:20.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:32:20.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.03:32:20.45#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:20.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:32:20.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:32:20.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:32:20.57#ibcon#enter wrdev, iclass 15, count 0 2006.201.03:32:20.57#ibcon#first serial, iclass 15, count 0 2006.201.03:32:20.57#ibcon#enter sib2, iclass 15, count 0 2006.201.03:32:20.57#ibcon#flushed, iclass 15, count 0 2006.201.03:32:20.57#ibcon#about to write, iclass 15, count 0 2006.201.03:32:20.57#ibcon#wrote, iclass 15, count 0 2006.201.03:32:20.57#ibcon#about to read 3, iclass 15, count 0 2006.201.03:32:20.59#ibcon#read 3, iclass 15, count 0 2006.201.03:32:20.59#ibcon#about to read 4, iclass 15, count 0 2006.201.03:32:20.59#ibcon#read 4, iclass 15, count 0 2006.201.03:32:20.59#ibcon#about to read 5, iclass 15, count 0 2006.201.03:32:20.59#ibcon#read 5, iclass 15, count 0 2006.201.03:32:20.59#ibcon#about to read 6, iclass 15, count 0 2006.201.03:32:20.59#ibcon#read 6, iclass 15, count 0 2006.201.03:32:20.59#ibcon#end of sib2, iclass 15, count 0 2006.201.03:32:20.59#ibcon#*mode == 0, iclass 15, count 0 2006.201.03:32:20.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.03:32:20.59#ibcon#[25=USB\r\n] 2006.201.03:32:20.59#ibcon#*before write, iclass 15, count 0 2006.201.03:32:20.59#ibcon#enter sib2, iclass 15, count 0 2006.201.03:32:20.59#ibcon#flushed, iclass 15, count 0 2006.201.03:32:20.59#ibcon#about to write, iclass 15, count 0 2006.201.03:32:20.59#ibcon#wrote, iclass 15, count 0 2006.201.03:32:20.59#ibcon#about to read 3, iclass 15, count 0 2006.201.03:32:20.62#ibcon#read 3, iclass 15, count 0 2006.201.03:32:20.62#ibcon#about to read 4, iclass 15, count 0 2006.201.03:32:20.62#ibcon#read 4, iclass 15, count 0 2006.201.03:32:20.62#ibcon#about to read 5, iclass 15, count 0 2006.201.03:32:20.62#ibcon#read 5, iclass 15, count 0 2006.201.03:32:20.62#ibcon#about to read 6, iclass 15, count 0 2006.201.03:32:20.62#ibcon#read 6, iclass 15, count 0 2006.201.03:32:20.62#ibcon#end of sib2, iclass 15, count 0 2006.201.03:32:20.62#ibcon#*after write, iclass 15, count 0 2006.201.03:32:20.62#ibcon#*before return 0, iclass 15, count 0 2006.201.03:32:20.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:32:20.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:32:20.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.03:32:20.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.03:32:20.62$vck44/vblo=1,629.99 2006.201.03:32:20.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.03:32:20.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.03:32:20.62#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:20.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:32:20.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:32:20.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:32:20.62#ibcon#enter wrdev, iclass 17, count 0 2006.201.03:32:20.62#ibcon#first serial, iclass 17, count 0 2006.201.03:32:20.62#ibcon#enter sib2, iclass 17, count 0 2006.201.03:32:20.62#ibcon#flushed, iclass 17, count 0 2006.201.03:32:20.62#ibcon#about to write, iclass 17, count 0 2006.201.03:32:20.62#ibcon#wrote, iclass 17, count 0 2006.201.03:32:20.62#ibcon#about to read 3, iclass 17, count 0 2006.201.03:32:20.64#ibcon#read 3, iclass 17, count 0 2006.201.03:32:20.64#ibcon#about to read 4, iclass 17, count 0 2006.201.03:32:20.64#ibcon#read 4, iclass 17, count 0 2006.201.03:32:20.64#ibcon#about to read 5, iclass 17, count 0 2006.201.03:32:20.64#ibcon#read 5, iclass 17, count 0 2006.201.03:32:20.64#ibcon#about to read 6, iclass 17, count 0 2006.201.03:32:20.64#ibcon#read 6, iclass 17, count 0 2006.201.03:32:20.64#ibcon#end of sib2, iclass 17, count 0 2006.201.03:32:20.64#ibcon#*mode == 0, iclass 17, count 0 2006.201.03:32:20.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.03:32:20.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:32:20.64#ibcon#*before write, iclass 17, count 0 2006.201.03:32:20.64#ibcon#enter sib2, iclass 17, count 0 2006.201.03:32:20.64#ibcon#flushed, iclass 17, count 0 2006.201.03:32:20.64#ibcon#about to write, iclass 17, count 0 2006.201.03:32:20.64#ibcon#wrote, iclass 17, count 0 2006.201.03:32:20.64#ibcon#about to read 3, iclass 17, count 0 2006.201.03:32:20.68#ibcon#read 3, iclass 17, count 0 2006.201.03:32:20.68#ibcon#about to read 4, iclass 17, count 0 2006.201.03:32:20.68#ibcon#read 4, iclass 17, count 0 2006.201.03:32:20.68#ibcon#about to read 5, iclass 17, count 0 2006.201.03:32:20.68#ibcon#read 5, iclass 17, count 0 2006.201.03:32:20.68#ibcon#about to read 6, iclass 17, count 0 2006.201.03:32:20.68#ibcon#read 6, iclass 17, count 0 2006.201.03:32:20.68#ibcon#end of sib2, iclass 17, count 0 2006.201.03:32:20.68#ibcon#*after write, iclass 17, count 0 2006.201.03:32:20.68#ibcon#*before return 0, iclass 17, count 0 2006.201.03:32:20.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:32:20.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:32:20.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.03:32:20.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.03:32:20.68$vck44/vb=1,4 2006.201.03:32:20.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.03:32:20.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.03:32:20.68#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:20.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:32:20.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:32:20.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:32:20.68#ibcon#enter wrdev, iclass 19, count 2 2006.201.03:32:20.68#ibcon#first serial, iclass 19, count 2 2006.201.03:32:20.68#ibcon#enter sib2, iclass 19, count 2 2006.201.03:32:20.68#ibcon#flushed, iclass 19, count 2 2006.201.03:32:20.68#ibcon#about to write, iclass 19, count 2 2006.201.03:32:20.68#ibcon#wrote, iclass 19, count 2 2006.201.03:32:20.68#ibcon#about to read 3, iclass 19, count 2 2006.201.03:32:20.70#ibcon#read 3, iclass 19, count 2 2006.201.03:32:20.70#ibcon#about to read 4, iclass 19, count 2 2006.201.03:32:20.70#ibcon#read 4, iclass 19, count 2 2006.201.03:32:20.70#ibcon#about to read 5, iclass 19, count 2 2006.201.03:32:20.70#ibcon#read 5, iclass 19, count 2 2006.201.03:32:20.70#ibcon#about to read 6, iclass 19, count 2 2006.201.03:32:20.70#ibcon#read 6, iclass 19, count 2 2006.201.03:32:20.70#ibcon#end of sib2, iclass 19, count 2 2006.201.03:32:20.70#ibcon#*mode == 0, iclass 19, count 2 2006.201.03:32:20.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.03:32:20.70#ibcon#[27=AT01-04\r\n] 2006.201.03:32:20.70#ibcon#*before write, iclass 19, count 2 2006.201.03:32:20.70#ibcon#enter sib2, iclass 19, count 2 2006.201.03:32:20.70#ibcon#flushed, iclass 19, count 2 2006.201.03:32:20.70#ibcon#about to write, iclass 19, count 2 2006.201.03:32:20.70#ibcon#wrote, iclass 19, count 2 2006.201.03:32:20.70#ibcon#about to read 3, iclass 19, count 2 2006.201.03:32:20.73#ibcon#read 3, iclass 19, count 2 2006.201.03:32:20.73#ibcon#about to read 4, iclass 19, count 2 2006.201.03:32:20.73#ibcon#read 4, iclass 19, count 2 2006.201.03:32:20.73#ibcon#about to read 5, iclass 19, count 2 2006.201.03:32:20.73#ibcon#read 5, iclass 19, count 2 2006.201.03:32:20.73#ibcon#about to read 6, iclass 19, count 2 2006.201.03:32:20.73#ibcon#read 6, iclass 19, count 2 2006.201.03:32:20.73#ibcon#end of sib2, iclass 19, count 2 2006.201.03:32:20.73#ibcon#*after write, iclass 19, count 2 2006.201.03:32:20.73#ibcon#*before return 0, iclass 19, count 2 2006.201.03:32:20.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:32:20.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:32:20.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.03:32:20.73#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:20.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:32:20.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:32:20.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:32:20.85#ibcon#enter wrdev, iclass 19, count 0 2006.201.03:32:20.85#ibcon#first serial, iclass 19, count 0 2006.201.03:32:20.85#ibcon#enter sib2, iclass 19, count 0 2006.201.03:32:20.85#ibcon#flushed, iclass 19, count 0 2006.201.03:32:20.85#ibcon#about to write, iclass 19, count 0 2006.201.03:32:20.85#ibcon#wrote, iclass 19, count 0 2006.201.03:32:20.85#ibcon#about to read 3, iclass 19, count 0 2006.201.03:32:20.87#ibcon#read 3, iclass 19, count 0 2006.201.03:32:20.87#ibcon#about to read 4, iclass 19, count 0 2006.201.03:32:20.87#ibcon#read 4, iclass 19, count 0 2006.201.03:32:20.87#ibcon#about to read 5, iclass 19, count 0 2006.201.03:32:20.87#ibcon#read 5, iclass 19, count 0 2006.201.03:32:20.87#ibcon#about to read 6, iclass 19, count 0 2006.201.03:32:20.87#ibcon#read 6, iclass 19, count 0 2006.201.03:32:20.87#ibcon#end of sib2, iclass 19, count 0 2006.201.03:32:20.87#ibcon#*mode == 0, iclass 19, count 0 2006.201.03:32:20.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.03:32:20.87#ibcon#[27=USB\r\n] 2006.201.03:32:20.87#ibcon#*before write, iclass 19, count 0 2006.201.03:32:20.87#ibcon#enter sib2, iclass 19, count 0 2006.201.03:32:20.87#ibcon#flushed, iclass 19, count 0 2006.201.03:32:20.87#ibcon#about to write, iclass 19, count 0 2006.201.03:32:20.87#ibcon#wrote, iclass 19, count 0 2006.201.03:32:20.87#ibcon#about to read 3, iclass 19, count 0 2006.201.03:32:20.90#ibcon#read 3, iclass 19, count 0 2006.201.03:32:20.90#ibcon#about to read 4, iclass 19, count 0 2006.201.03:32:20.90#ibcon#read 4, iclass 19, count 0 2006.201.03:32:20.90#ibcon#about to read 5, iclass 19, count 0 2006.201.03:32:20.90#ibcon#read 5, iclass 19, count 0 2006.201.03:32:20.90#ibcon#about to read 6, iclass 19, count 0 2006.201.03:32:20.90#ibcon#read 6, iclass 19, count 0 2006.201.03:32:20.90#ibcon#end of sib2, iclass 19, count 0 2006.201.03:32:20.90#ibcon#*after write, iclass 19, count 0 2006.201.03:32:20.90#ibcon#*before return 0, iclass 19, count 0 2006.201.03:32:20.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:32:20.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:32:20.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.03:32:20.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.03:32:20.90$vck44/vblo=2,634.99 2006.201.03:32:20.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.03:32:20.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.03:32:20.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:20.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:20.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:20.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:20.90#ibcon#enter wrdev, iclass 21, count 0 2006.201.03:32:20.90#ibcon#first serial, iclass 21, count 0 2006.201.03:32:20.90#ibcon#enter sib2, iclass 21, count 0 2006.201.03:32:20.90#ibcon#flushed, iclass 21, count 0 2006.201.03:32:20.90#ibcon#about to write, iclass 21, count 0 2006.201.03:32:20.90#ibcon#wrote, iclass 21, count 0 2006.201.03:32:20.90#ibcon#about to read 3, iclass 21, count 0 2006.201.03:32:20.92#ibcon#read 3, iclass 21, count 0 2006.201.03:32:20.92#ibcon#about to read 4, iclass 21, count 0 2006.201.03:32:20.92#ibcon#read 4, iclass 21, count 0 2006.201.03:32:20.92#ibcon#about to read 5, iclass 21, count 0 2006.201.03:32:20.92#ibcon#read 5, iclass 21, count 0 2006.201.03:32:20.92#ibcon#about to read 6, iclass 21, count 0 2006.201.03:32:20.92#ibcon#read 6, iclass 21, count 0 2006.201.03:32:20.92#ibcon#end of sib2, iclass 21, count 0 2006.201.03:32:20.92#ibcon#*mode == 0, iclass 21, count 0 2006.201.03:32:20.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.03:32:20.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:32:20.92#ibcon#*before write, iclass 21, count 0 2006.201.03:32:20.92#ibcon#enter sib2, iclass 21, count 0 2006.201.03:32:20.92#ibcon#flushed, iclass 21, count 0 2006.201.03:32:20.92#ibcon#about to write, iclass 21, count 0 2006.201.03:32:20.92#ibcon#wrote, iclass 21, count 0 2006.201.03:32:20.92#ibcon#about to read 3, iclass 21, count 0 2006.201.03:32:20.96#ibcon#read 3, iclass 21, count 0 2006.201.03:32:20.96#ibcon#about to read 4, iclass 21, count 0 2006.201.03:32:20.96#ibcon#read 4, iclass 21, count 0 2006.201.03:32:20.96#ibcon#about to read 5, iclass 21, count 0 2006.201.03:32:20.96#ibcon#read 5, iclass 21, count 0 2006.201.03:32:20.96#ibcon#about to read 6, iclass 21, count 0 2006.201.03:32:20.96#ibcon#read 6, iclass 21, count 0 2006.201.03:32:20.96#ibcon#end of sib2, iclass 21, count 0 2006.201.03:32:20.96#ibcon#*after write, iclass 21, count 0 2006.201.03:32:20.96#ibcon#*before return 0, iclass 21, count 0 2006.201.03:32:20.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:20.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:32:20.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.03:32:20.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.03:32:20.96$vck44/vb=2,5 2006.201.03:32:20.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.03:32:20.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.03:32:20.96#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:20.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:21.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:21.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:21.02#ibcon#enter wrdev, iclass 23, count 2 2006.201.03:32:21.02#ibcon#first serial, iclass 23, count 2 2006.201.03:32:21.02#ibcon#enter sib2, iclass 23, count 2 2006.201.03:32:21.02#ibcon#flushed, iclass 23, count 2 2006.201.03:32:21.02#ibcon#about to write, iclass 23, count 2 2006.201.03:32:21.02#ibcon#wrote, iclass 23, count 2 2006.201.03:32:21.02#ibcon#about to read 3, iclass 23, count 2 2006.201.03:32:21.04#ibcon#read 3, iclass 23, count 2 2006.201.03:32:21.04#ibcon#about to read 4, iclass 23, count 2 2006.201.03:32:21.04#ibcon#read 4, iclass 23, count 2 2006.201.03:32:21.04#ibcon#about to read 5, iclass 23, count 2 2006.201.03:32:21.04#ibcon#read 5, iclass 23, count 2 2006.201.03:32:21.04#ibcon#about to read 6, iclass 23, count 2 2006.201.03:32:21.04#ibcon#read 6, iclass 23, count 2 2006.201.03:32:21.04#ibcon#end of sib2, iclass 23, count 2 2006.201.03:32:21.04#ibcon#*mode == 0, iclass 23, count 2 2006.201.03:32:21.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.03:32:21.04#ibcon#[27=AT02-05\r\n] 2006.201.03:32:21.04#ibcon#*before write, iclass 23, count 2 2006.201.03:32:21.04#ibcon#enter sib2, iclass 23, count 2 2006.201.03:32:21.04#ibcon#flushed, iclass 23, count 2 2006.201.03:32:21.04#ibcon#about to write, iclass 23, count 2 2006.201.03:32:21.04#ibcon#wrote, iclass 23, count 2 2006.201.03:32:21.04#ibcon#about to read 3, iclass 23, count 2 2006.201.03:32:21.07#ibcon#read 3, iclass 23, count 2 2006.201.03:32:21.07#ibcon#about to read 4, iclass 23, count 2 2006.201.03:32:21.07#ibcon#read 4, iclass 23, count 2 2006.201.03:32:21.07#ibcon#about to read 5, iclass 23, count 2 2006.201.03:32:21.07#ibcon#read 5, iclass 23, count 2 2006.201.03:32:21.07#ibcon#about to read 6, iclass 23, count 2 2006.201.03:32:21.07#ibcon#read 6, iclass 23, count 2 2006.201.03:32:21.07#ibcon#end of sib2, iclass 23, count 2 2006.201.03:32:21.07#ibcon#*after write, iclass 23, count 2 2006.201.03:32:21.07#ibcon#*before return 0, iclass 23, count 2 2006.201.03:32:21.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:21.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:32:21.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.03:32:21.07#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:21.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:21.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:21.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:21.19#ibcon#enter wrdev, iclass 23, count 0 2006.201.03:32:21.19#ibcon#first serial, iclass 23, count 0 2006.201.03:32:21.19#ibcon#enter sib2, iclass 23, count 0 2006.201.03:32:21.19#ibcon#flushed, iclass 23, count 0 2006.201.03:32:21.19#ibcon#about to write, iclass 23, count 0 2006.201.03:32:21.19#ibcon#wrote, iclass 23, count 0 2006.201.03:32:21.19#ibcon#about to read 3, iclass 23, count 0 2006.201.03:32:21.21#ibcon#read 3, iclass 23, count 0 2006.201.03:32:21.21#ibcon#about to read 4, iclass 23, count 0 2006.201.03:32:21.21#ibcon#read 4, iclass 23, count 0 2006.201.03:32:21.21#ibcon#about to read 5, iclass 23, count 0 2006.201.03:32:21.21#ibcon#read 5, iclass 23, count 0 2006.201.03:32:21.21#ibcon#about to read 6, iclass 23, count 0 2006.201.03:32:21.21#ibcon#read 6, iclass 23, count 0 2006.201.03:32:21.21#ibcon#end of sib2, iclass 23, count 0 2006.201.03:32:21.21#ibcon#*mode == 0, iclass 23, count 0 2006.201.03:32:21.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.03:32:21.21#ibcon#[27=USB\r\n] 2006.201.03:32:21.21#ibcon#*before write, iclass 23, count 0 2006.201.03:32:21.21#ibcon#enter sib2, iclass 23, count 0 2006.201.03:32:21.21#ibcon#flushed, iclass 23, count 0 2006.201.03:32:21.21#ibcon#about to write, iclass 23, count 0 2006.201.03:32:21.21#ibcon#wrote, iclass 23, count 0 2006.201.03:32:21.21#ibcon#about to read 3, iclass 23, count 0 2006.201.03:32:21.24#ibcon#read 3, iclass 23, count 0 2006.201.03:32:21.24#ibcon#about to read 4, iclass 23, count 0 2006.201.03:32:21.24#ibcon#read 4, iclass 23, count 0 2006.201.03:32:21.24#ibcon#about to read 5, iclass 23, count 0 2006.201.03:32:21.24#ibcon#read 5, iclass 23, count 0 2006.201.03:32:21.24#ibcon#about to read 6, iclass 23, count 0 2006.201.03:32:21.24#ibcon#read 6, iclass 23, count 0 2006.201.03:32:21.24#ibcon#end of sib2, iclass 23, count 0 2006.201.03:32:21.24#ibcon#*after write, iclass 23, count 0 2006.201.03:32:21.24#ibcon#*before return 0, iclass 23, count 0 2006.201.03:32:21.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:21.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:32:21.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.03:32:21.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.03:32:21.24$vck44/vblo=3,649.99 2006.201.03:32:21.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.03:32:21.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.03:32:21.24#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:21.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:21.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:21.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:21.24#ibcon#enter wrdev, iclass 25, count 0 2006.201.03:32:21.24#ibcon#first serial, iclass 25, count 0 2006.201.03:32:21.24#ibcon#enter sib2, iclass 25, count 0 2006.201.03:32:21.24#ibcon#flushed, iclass 25, count 0 2006.201.03:32:21.24#ibcon#about to write, iclass 25, count 0 2006.201.03:32:21.24#ibcon#wrote, iclass 25, count 0 2006.201.03:32:21.24#ibcon#about to read 3, iclass 25, count 0 2006.201.03:32:21.26#ibcon#read 3, iclass 25, count 0 2006.201.03:32:21.26#ibcon#about to read 4, iclass 25, count 0 2006.201.03:32:21.26#ibcon#read 4, iclass 25, count 0 2006.201.03:32:21.26#ibcon#about to read 5, iclass 25, count 0 2006.201.03:32:21.26#ibcon#read 5, iclass 25, count 0 2006.201.03:32:21.26#ibcon#about to read 6, iclass 25, count 0 2006.201.03:32:21.26#ibcon#read 6, iclass 25, count 0 2006.201.03:32:21.26#ibcon#end of sib2, iclass 25, count 0 2006.201.03:32:21.26#ibcon#*mode == 0, iclass 25, count 0 2006.201.03:32:21.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.03:32:21.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:32:21.26#ibcon#*before write, iclass 25, count 0 2006.201.03:32:21.26#ibcon#enter sib2, iclass 25, count 0 2006.201.03:32:21.26#ibcon#flushed, iclass 25, count 0 2006.201.03:32:21.26#ibcon#about to write, iclass 25, count 0 2006.201.03:32:21.26#ibcon#wrote, iclass 25, count 0 2006.201.03:32:21.26#ibcon#about to read 3, iclass 25, count 0 2006.201.03:32:21.30#ibcon#read 3, iclass 25, count 0 2006.201.03:32:21.30#ibcon#about to read 4, iclass 25, count 0 2006.201.03:32:21.30#ibcon#read 4, iclass 25, count 0 2006.201.03:32:21.30#ibcon#about to read 5, iclass 25, count 0 2006.201.03:32:21.30#ibcon#read 5, iclass 25, count 0 2006.201.03:32:21.30#ibcon#about to read 6, iclass 25, count 0 2006.201.03:32:21.30#ibcon#read 6, iclass 25, count 0 2006.201.03:32:21.30#ibcon#end of sib2, iclass 25, count 0 2006.201.03:32:21.30#ibcon#*after write, iclass 25, count 0 2006.201.03:32:21.30#ibcon#*before return 0, iclass 25, count 0 2006.201.03:32:21.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:21.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:32:21.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.03:32:21.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.03:32:21.30$vck44/vb=3,4 2006.201.03:32:21.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.03:32:21.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.03:32:21.30#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:21.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:21.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:21.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:21.36#ibcon#enter wrdev, iclass 27, count 2 2006.201.03:32:21.36#ibcon#first serial, iclass 27, count 2 2006.201.03:32:21.36#ibcon#enter sib2, iclass 27, count 2 2006.201.03:32:21.36#ibcon#flushed, iclass 27, count 2 2006.201.03:32:21.36#ibcon#about to write, iclass 27, count 2 2006.201.03:32:21.36#ibcon#wrote, iclass 27, count 2 2006.201.03:32:21.36#ibcon#about to read 3, iclass 27, count 2 2006.201.03:32:21.38#ibcon#read 3, iclass 27, count 2 2006.201.03:32:21.38#ibcon#about to read 4, iclass 27, count 2 2006.201.03:32:21.38#ibcon#read 4, iclass 27, count 2 2006.201.03:32:21.38#ibcon#about to read 5, iclass 27, count 2 2006.201.03:32:21.38#ibcon#read 5, iclass 27, count 2 2006.201.03:32:21.38#ibcon#about to read 6, iclass 27, count 2 2006.201.03:32:21.38#ibcon#read 6, iclass 27, count 2 2006.201.03:32:21.38#ibcon#end of sib2, iclass 27, count 2 2006.201.03:32:21.38#ibcon#*mode == 0, iclass 27, count 2 2006.201.03:32:21.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.03:32:21.38#ibcon#[27=AT03-04\r\n] 2006.201.03:32:21.38#ibcon#*before write, iclass 27, count 2 2006.201.03:32:21.38#ibcon#enter sib2, iclass 27, count 2 2006.201.03:32:21.38#ibcon#flushed, iclass 27, count 2 2006.201.03:32:21.38#ibcon#about to write, iclass 27, count 2 2006.201.03:32:21.38#ibcon#wrote, iclass 27, count 2 2006.201.03:32:21.38#ibcon#about to read 3, iclass 27, count 2 2006.201.03:32:21.41#ibcon#read 3, iclass 27, count 2 2006.201.03:32:21.41#ibcon#about to read 4, iclass 27, count 2 2006.201.03:32:21.41#ibcon#read 4, iclass 27, count 2 2006.201.03:32:21.41#ibcon#about to read 5, iclass 27, count 2 2006.201.03:32:21.41#ibcon#read 5, iclass 27, count 2 2006.201.03:32:21.41#ibcon#about to read 6, iclass 27, count 2 2006.201.03:32:21.41#ibcon#read 6, iclass 27, count 2 2006.201.03:32:21.41#ibcon#end of sib2, iclass 27, count 2 2006.201.03:32:21.41#ibcon#*after write, iclass 27, count 2 2006.201.03:32:21.41#ibcon#*before return 0, iclass 27, count 2 2006.201.03:32:21.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:21.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:32:21.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.03:32:21.41#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:21.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:21.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:21.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:21.53#ibcon#enter wrdev, iclass 27, count 0 2006.201.03:32:21.53#ibcon#first serial, iclass 27, count 0 2006.201.03:32:21.53#ibcon#enter sib2, iclass 27, count 0 2006.201.03:32:21.53#ibcon#flushed, iclass 27, count 0 2006.201.03:32:21.53#ibcon#about to write, iclass 27, count 0 2006.201.03:32:21.53#ibcon#wrote, iclass 27, count 0 2006.201.03:32:21.53#ibcon#about to read 3, iclass 27, count 0 2006.201.03:32:21.55#ibcon#read 3, iclass 27, count 0 2006.201.03:32:21.55#ibcon#about to read 4, iclass 27, count 0 2006.201.03:32:21.55#ibcon#read 4, iclass 27, count 0 2006.201.03:32:21.55#ibcon#about to read 5, iclass 27, count 0 2006.201.03:32:21.55#ibcon#read 5, iclass 27, count 0 2006.201.03:32:21.55#ibcon#about to read 6, iclass 27, count 0 2006.201.03:32:21.55#ibcon#read 6, iclass 27, count 0 2006.201.03:32:21.55#ibcon#end of sib2, iclass 27, count 0 2006.201.03:32:21.55#ibcon#*mode == 0, iclass 27, count 0 2006.201.03:32:21.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.03:32:21.55#ibcon#[27=USB\r\n] 2006.201.03:32:21.55#ibcon#*before write, iclass 27, count 0 2006.201.03:32:21.55#ibcon#enter sib2, iclass 27, count 0 2006.201.03:32:21.55#ibcon#flushed, iclass 27, count 0 2006.201.03:32:21.55#ibcon#about to write, iclass 27, count 0 2006.201.03:32:21.55#ibcon#wrote, iclass 27, count 0 2006.201.03:32:21.55#ibcon#about to read 3, iclass 27, count 0 2006.201.03:32:21.58#ibcon#read 3, iclass 27, count 0 2006.201.03:32:21.58#ibcon#about to read 4, iclass 27, count 0 2006.201.03:32:21.58#ibcon#read 4, iclass 27, count 0 2006.201.03:32:21.58#ibcon#about to read 5, iclass 27, count 0 2006.201.03:32:21.58#ibcon#read 5, iclass 27, count 0 2006.201.03:32:21.58#ibcon#about to read 6, iclass 27, count 0 2006.201.03:32:21.58#ibcon#read 6, iclass 27, count 0 2006.201.03:32:21.58#ibcon#end of sib2, iclass 27, count 0 2006.201.03:32:21.58#ibcon#*after write, iclass 27, count 0 2006.201.03:32:21.58#ibcon#*before return 0, iclass 27, count 0 2006.201.03:32:21.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:21.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:32:21.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.03:32:21.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.03:32:21.58$vck44/vblo=4,679.99 2006.201.03:32:21.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.03:32:21.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.03:32:21.58#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:21.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:21.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:21.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:21.58#ibcon#enter wrdev, iclass 29, count 0 2006.201.03:32:21.58#ibcon#first serial, iclass 29, count 0 2006.201.03:32:21.58#ibcon#enter sib2, iclass 29, count 0 2006.201.03:32:21.58#ibcon#flushed, iclass 29, count 0 2006.201.03:32:21.58#ibcon#about to write, iclass 29, count 0 2006.201.03:32:21.58#ibcon#wrote, iclass 29, count 0 2006.201.03:32:21.58#ibcon#about to read 3, iclass 29, count 0 2006.201.03:32:21.60#ibcon#read 3, iclass 29, count 0 2006.201.03:32:21.60#ibcon#about to read 4, iclass 29, count 0 2006.201.03:32:21.60#ibcon#read 4, iclass 29, count 0 2006.201.03:32:21.60#ibcon#about to read 5, iclass 29, count 0 2006.201.03:32:21.60#ibcon#read 5, iclass 29, count 0 2006.201.03:32:21.60#ibcon#about to read 6, iclass 29, count 0 2006.201.03:32:21.60#ibcon#read 6, iclass 29, count 0 2006.201.03:32:21.60#ibcon#end of sib2, iclass 29, count 0 2006.201.03:32:21.60#ibcon#*mode == 0, iclass 29, count 0 2006.201.03:32:21.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.03:32:21.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:32:21.60#ibcon#*before write, iclass 29, count 0 2006.201.03:32:21.60#ibcon#enter sib2, iclass 29, count 0 2006.201.03:32:21.60#ibcon#flushed, iclass 29, count 0 2006.201.03:32:21.60#ibcon#about to write, iclass 29, count 0 2006.201.03:32:21.60#ibcon#wrote, iclass 29, count 0 2006.201.03:32:21.60#ibcon#about to read 3, iclass 29, count 0 2006.201.03:32:21.64#ibcon#read 3, iclass 29, count 0 2006.201.03:32:21.64#ibcon#about to read 4, iclass 29, count 0 2006.201.03:32:21.64#ibcon#read 4, iclass 29, count 0 2006.201.03:32:21.64#ibcon#about to read 5, iclass 29, count 0 2006.201.03:32:21.64#ibcon#read 5, iclass 29, count 0 2006.201.03:32:21.64#ibcon#about to read 6, iclass 29, count 0 2006.201.03:32:21.64#ibcon#read 6, iclass 29, count 0 2006.201.03:32:21.64#ibcon#end of sib2, iclass 29, count 0 2006.201.03:32:21.64#ibcon#*after write, iclass 29, count 0 2006.201.03:32:21.64#ibcon#*before return 0, iclass 29, count 0 2006.201.03:32:21.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:21.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:32:21.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.03:32:21.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.03:32:21.64$vck44/vb=4,5 2006.201.03:32:21.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.03:32:21.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.03:32:21.64#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:21.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:21.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:21.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:21.70#ibcon#enter wrdev, iclass 31, count 2 2006.201.03:32:21.70#ibcon#first serial, iclass 31, count 2 2006.201.03:32:21.70#ibcon#enter sib2, iclass 31, count 2 2006.201.03:32:21.70#ibcon#flushed, iclass 31, count 2 2006.201.03:32:21.70#ibcon#about to write, iclass 31, count 2 2006.201.03:32:21.70#ibcon#wrote, iclass 31, count 2 2006.201.03:32:21.70#ibcon#about to read 3, iclass 31, count 2 2006.201.03:32:21.72#ibcon#read 3, iclass 31, count 2 2006.201.03:32:21.72#ibcon#about to read 4, iclass 31, count 2 2006.201.03:32:21.72#ibcon#read 4, iclass 31, count 2 2006.201.03:32:21.72#ibcon#about to read 5, iclass 31, count 2 2006.201.03:32:21.72#ibcon#read 5, iclass 31, count 2 2006.201.03:32:21.72#ibcon#about to read 6, iclass 31, count 2 2006.201.03:32:21.72#ibcon#read 6, iclass 31, count 2 2006.201.03:32:21.72#ibcon#end of sib2, iclass 31, count 2 2006.201.03:32:21.72#ibcon#*mode == 0, iclass 31, count 2 2006.201.03:32:21.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.03:32:21.72#ibcon#[27=AT04-05\r\n] 2006.201.03:32:21.72#ibcon#*before write, iclass 31, count 2 2006.201.03:32:21.72#ibcon#enter sib2, iclass 31, count 2 2006.201.03:32:21.72#ibcon#flushed, iclass 31, count 2 2006.201.03:32:21.72#ibcon#about to write, iclass 31, count 2 2006.201.03:32:21.72#ibcon#wrote, iclass 31, count 2 2006.201.03:32:21.72#ibcon#about to read 3, iclass 31, count 2 2006.201.03:32:21.75#ibcon#read 3, iclass 31, count 2 2006.201.03:32:21.75#ibcon#about to read 4, iclass 31, count 2 2006.201.03:32:21.75#ibcon#read 4, iclass 31, count 2 2006.201.03:32:21.75#ibcon#about to read 5, iclass 31, count 2 2006.201.03:32:21.75#ibcon#read 5, iclass 31, count 2 2006.201.03:32:21.75#ibcon#about to read 6, iclass 31, count 2 2006.201.03:32:21.75#ibcon#read 6, iclass 31, count 2 2006.201.03:32:21.75#ibcon#end of sib2, iclass 31, count 2 2006.201.03:32:21.75#ibcon#*after write, iclass 31, count 2 2006.201.03:32:21.75#ibcon#*before return 0, iclass 31, count 2 2006.201.03:32:21.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:21.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:32:21.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.03:32:21.75#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:21.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:21.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:21.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:21.87#ibcon#enter wrdev, iclass 31, count 0 2006.201.03:32:21.87#ibcon#first serial, iclass 31, count 0 2006.201.03:32:21.87#ibcon#enter sib2, iclass 31, count 0 2006.201.03:32:21.87#ibcon#flushed, iclass 31, count 0 2006.201.03:32:21.87#ibcon#about to write, iclass 31, count 0 2006.201.03:32:21.87#ibcon#wrote, iclass 31, count 0 2006.201.03:32:21.87#ibcon#about to read 3, iclass 31, count 0 2006.201.03:32:21.89#ibcon#read 3, iclass 31, count 0 2006.201.03:32:21.89#ibcon#about to read 4, iclass 31, count 0 2006.201.03:32:21.89#ibcon#read 4, iclass 31, count 0 2006.201.03:32:21.89#ibcon#about to read 5, iclass 31, count 0 2006.201.03:32:21.89#ibcon#read 5, iclass 31, count 0 2006.201.03:32:21.89#ibcon#about to read 6, iclass 31, count 0 2006.201.03:32:21.89#ibcon#read 6, iclass 31, count 0 2006.201.03:32:21.89#ibcon#end of sib2, iclass 31, count 0 2006.201.03:32:21.89#ibcon#*mode == 0, iclass 31, count 0 2006.201.03:32:21.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.03:32:21.89#ibcon#[27=USB\r\n] 2006.201.03:32:21.89#ibcon#*before write, iclass 31, count 0 2006.201.03:32:21.89#ibcon#enter sib2, iclass 31, count 0 2006.201.03:32:21.89#ibcon#flushed, iclass 31, count 0 2006.201.03:32:21.89#ibcon#about to write, iclass 31, count 0 2006.201.03:32:21.89#ibcon#wrote, iclass 31, count 0 2006.201.03:32:21.89#ibcon#about to read 3, iclass 31, count 0 2006.201.03:32:21.92#ibcon#read 3, iclass 31, count 0 2006.201.03:32:21.92#ibcon#about to read 4, iclass 31, count 0 2006.201.03:32:21.92#ibcon#read 4, iclass 31, count 0 2006.201.03:32:21.92#ibcon#about to read 5, iclass 31, count 0 2006.201.03:32:21.92#ibcon#read 5, iclass 31, count 0 2006.201.03:32:21.92#ibcon#about to read 6, iclass 31, count 0 2006.201.03:32:21.92#ibcon#read 6, iclass 31, count 0 2006.201.03:32:21.92#ibcon#end of sib2, iclass 31, count 0 2006.201.03:32:21.92#ibcon#*after write, iclass 31, count 0 2006.201.03:32:21.92#ibcon#*before return 0, iclass 31, count 0 2006.201.03:32:21.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:21.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:32:21.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.03:32:21.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.03:32:21.92$vck44/vblo=5,709.99 2006.201.03:32:21.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.03:32:21.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.03:32:21.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:21.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:21.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:21.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:21.92#ibcon#enter wrdev, iclass 33, count 0 2006.201.03:32:21.92#ibcon#first serial, iclass 33, count 0 2006.201.03:32:21.92#ibcon#enter sib2, iclass 33, count 0 2006.201.03:32:21.92#ibcon#flushed, iclass 33, count 0 2006.201.03:32:21.92#ibcon#about to write, iclass 33, count 0 2006.201.03:32:21.92#ibcon#wrote, iclass 33, count 0 2006.201.03:32:21.92#ibcon#about to read 3, iclass 33, count 0 2006.201.03:32:21.94#ibcon#read 3, iclass 33, count 0 2006.201.03:32:21.94#ibcon#about to read 4, iclass 33, count 0 2006.201.03:32:21.94#ibcon#read 4, iclass 33, count 0 2006.201.03:32:21.94#ibcon#about to read 5, iclass 33, count 0 2006.201.03:32:21.94#ibcon#read 5, iclass 33, count 0 2006.201.03:32:21.94#ibcon#about to read 6, iclass 33, count 0 2006.201.03:32:21.94#ibcon#read 6, iclass 33, count 0 2006.201.03:32:21.94#ibcon#end of sib2, iclass 33, count 0 2006.201.03:32:21.94#ibcon#*mode == 0, iclass 33, count 0 2006.201.03:32:21.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.03:32:21.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:32:21.94#ibcon#*before write, iclass 33, count 0 2006.201.03:32:21.94#ibcon#enter sib2, iclass 33, count 0 2006.201.03:32:21.94#ibcon#flushed, iclass 33, count 0 2006.201.03:32:21.94#ibcon#about to write, iclass 33, count 0 2006.201.03:32:21.94#ibcon#wrote, iclass 33, count 0 2006.201.03:32:21.94#ibcon#about to read 3, iclass 33, count 0 2006.201.03:32:21.98#ibcon#read 3, iclass 33, count 0 2006.201.03:32:21.98#ibcon#about to read 4, iclass 33, count 0 2006.201.03:32:21.98#ibcon#read 4, iclass 33, count 0 2006.201.03:32:21.98#ibcon#about to read 5, iclass 33, count 0 2006.201.03:32:21.98#ibcon#read 5, iclass 33, count 0 2006.201.03:32:21.98#ibcon#about to read 6, iclass 33, count 0 2006.201.03:32:21.98#ibcon#read 6, iclass 33, count 0 2006.201.03:32:21.98#ibcon#end of sib2, iclass 33, count 0 2006.201.03:32:21.98#ibcon#*after write, iclass 33, count 0 2006.201.03:32:21.98#ibcon#*before return 0, iclass 33, count 0 2006.201.03:32:21.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:21.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:32:21.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.03:32:21.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.03:32:21.98$vck44/vb=5,4 2006.201.03:32:21.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.03:32:21.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.03:32:21.98#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:21.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:22.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:22.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:22.04#ibcon#enter wrdev, iclass 35, count 2 2006.201.03:32:22.04#ibcon#first serial, iclass 35, count 2 2006.201.03:32:22.04#ibcon#enter sib2, iclass 35, count 2 2006.201.03:32:22.04#ibcon#flushed, iclass 35, count 2 2006.201.03:32:22.04#ibcon#about to write, iclass 35, count 2 2006.201.03:32:22.04#ibcon#wrote, iclass 35, count 2 2006.201.03:32:22.04#ibcon#about to read 3, iclass 35, count 2 2006.201.03:32:22.06#ibcon#read 3, iclass 35, count 2 2006.201.03:32:22.06#ibcon#about to read 4, iclass 35, count 2 2006.201.03:32:22.06#ibcon#read 4, iclass 35, count 2 2006.201.03:32:22.06#ibcon#about to read 5, iclass 35, count 2 2006.201.03:32:22.06#ibcon#read 5, iclass 35, count 2 2006.201.03:32:22.06#ibcon#about to read 6, iclass 35, count 2 2006.201.03:32:22.06#ibcon#read 6, iclass 35, count 2 2006.201.03:32:22.06#ibcon#end of sib2, iclass 35, count 2 2006.201.03:32:22.06#ibcon#*mode == 0, iclass 35, count 2 2006.201.03:32:22.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.03:32:22.06#ibcon#[27=AT05-04\r\n] 2006.201.03:32:22.06#ibcon#*before write, iclass 35, count 2 2006.201.03:32:22.06#ibcon#enter sib2, iclass 35, count 2 2006.201.03:32:22.06#ibcon#flushed, iclass 35, count 2 2006.201.03:32:22.06#ibcon#about to write, iclass 35, count 2 2006.201.03:32:22.06#ibcon#wrote, iclass 35, count 2 2006.201.03:32:22.06#ibcon#about to read 3, iclass 35, count 2 2006.201.03:32:22.09#ibcon#read 3, iclass 35, count 2 2006.201.03:32:22.09#ibcon#about to read 4, iclass 35, count 2 2006.201.03:32:22.09#ibcon#read 4, iclass 35, count 2 2006.201.03:32:22.09#ibcon#about to read 5, iclass 35, count 2 2006.201.03:32:22.09#ibcon#read 5, iclass 35, count 2 2006.201.03:32:22.09#ibcon#about to read 6, iclass 35, count 2 2006.201.03:32:22.09#ibcon#read 6, iclass 35, count 2 2006.201.03:32:22.09#ibcon#end of sib2, iclass 35, count 2 2006.201.03:32:22.09#ibcon#*after write, iclass 35, count 2 2006.201.03:32:22.09#ibcon#*before return 0, iclass 35, count 2 2006.201.03:32:22.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:22.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:32:22.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.03:32:22.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:22.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:22.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:22.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:22.21#ibcon#enter wrdev, iclass 35, count 0 2006.201.03:32:22.21#ibcon#first serial, iclass 35, count 0 2006.201.03:32:22.21#ibcon#enter sib2, iclass 35, count 0 2006.201.03:32:22.21#ibcon#flushed, iclass 35, count 0 2006.201.03:32:22.21#ibcon#about to write, iclass 35, count 0 2006.201.03:32:22.21#ibcon#wrote, iclass 35, count 0 2006.201.03:32:22.21#ibcon#about to read 3, iclass 35, count 0 2006.201.03:32:22.24#ibcon#read 3, iclass 35, count 0 2006.201.03:32:22.24#ibcon#about to read 4, iclass 35, count 0 2006.201.03:32:22.24#ibcon#read 4, iclass 35, count 0 2006.201.03:32:22.24#ibcon#about to read 5, iclass 35, count 0 2006.201.03:32:22.24#ibcon#read 5, iclass 35, count 0 2006.201.03:32:22.24#ibcon#about to read 6, iclass 35, count 0 2006.201.03:32:22.24#ibcon#read 6, iclass 35, count 0 2006.201.03:32:22.24#ibcon#end of sib2, iclass 35, count 0 2006.201.03:32:22.24#ibcon#*mode == 0, iclass 35, count 0 2006.201.03:32:22.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.03:32:22.24#ibcon#[27=USB\r\n] 2006.201.03:32:22.24#ibcon#*before write, iclass 35, count 0 2006.201.03:32:22.24#ibcon#enter sib2, iclass 35, count 0 2006.201.03:32:22.24#ibcon#flushed, iclass 35, count 0 2006.201.03:32:22.24#ibcon#about to write, iclass 35, count 0 2006.201.03:32:22.24#ibcon#wrote, iclass 35, count 0 2006.201.03:32:22.24#ibcon#about to read 3, iclass 35, count 0 2006.201.03:32:22.27#ibcon#read 3, iclass 35, count 0 2006.201.03:32:22.27#ibcon#about to read 4, iclass 35, count 0 2006.201.03:32:22.27#ibcon#read 4, iclass 35, count 0 2006.201.03:32:22.27#ibcon#about to read 5, iclass 35, count 0 2006.201.03:32:22.27#ibcon#read 5, iclass 35, count 0 2006.201.03:32:22.27#ibcon#about to read 6, iclass 35, count 0 2006.201.03:32:22.27#ibcon#read 6, iclass 35, count 0 2006.201.03:32:22.27#ibcon#end of sib2, iclass 35, count 0 2006.201.03:32:22.27#ibcon#*after write, iclass 35, count 0 2006.201.03:32:22.27#ibcon#*before return 0, iclass 35, count 0 2006.201.03:32:22.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:22.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:32:22.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.03:32:22.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.03:32:22.27$vck44/vblo=6,719.99 2006.201.03:32:22.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.03:32:22.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.03:32:22.27#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:22.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:22.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:22.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:22.27#ibcon#enter wrdev, iclass 37, count 0 2006.201.03:32:22.27#ibcon#first serial, iclass 37, count 0 2006.201.03:32:22.27#ibcon#enter sib2, iclass 37, count 0 2006.201.03:32:22.27#ibcon#flushed, iclass 37, count 0 2006.201.03:32:22.27#ibcon#about to write, iclass 37, count 0 2006.201.03:32:22.27#ibcon#wrote, iclass 37, count 0 2006.201.03:32:22.27#ibcon#about to read 3, iclass 37, count 0 2006.201.03:32:22.29#ibcon#read 3, iclass 37, count 0 2006.201.03:32:22.29#ibcon#about to read 4, iclass 37, count 0 2006.201.03:32:22.29#ibcon#read 4, iclass 37, count 0 2006.201.03:32:22.29#ibcon#about to read 5, iclass 37, count 0 2006.201.03:32:22.29#ibcon#read 5, iclass 37, count 0 2006.201.03:32:22.29#ibcon#about to read 6, iclass 37, count 0 2006.201.03:32:22.29#ibcon#read 6, iclass 37, count 0 2006.201.03:32:22.29#ibcon#end of sib2, iclass 37, count 0 2006.201.03:32:22.29#ibcon#*mode == 0, iclass 37, count 0 2006.201.03:32:22.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.03:32:22.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:32:22.29#ibcon#*before write, iclass 37, count 0 2006.201.03:32:22.29#ibcon#enter sib2, iclass 37, count 0 2006.201.03:32:22.29#ibcon#flushed, iclass 37, count 0 2006.201.03:32:22.29#ibcon#about to write, iclass 37, count 0 2006.201.03:32:22.29#ibcon#wrote, iclass 37, count 0 2006.201.03:32:22.29#ibcon#about to read 3, iclass 37, count 0 2006.201.03:32:22.33#ibcon#read 3, iclass 37, count 0 2006.201.03:32:22.33#ibcon#about to read 4, iclass 37, count 0 2006.201.03:32:22.33#ibcon#read 4, iclass 37, count 0 2006.201.03:32:22.33#ibcon#about to read 5, iclass 37, count 0 2006.201.03:32:22.33#ibcon#read 5, iclass 37, count 0 2006.201.03:32:22.33#ibcon#about to read 6, iclass 37, count 0 2006.201.03:32:22.33#ibcon#read 6, iclass 37, count 0 2006.201.03:32:22.33#ibcon#end of sib2, iclass 37, count 0 2006.201.03:32:22.33#ibcon#*after write, iclass 37, count 0 2006.201.03:32:22.33#ibcon#*before return 0, iclass 37, count 0 2006.201.03:32:22.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:22.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:32:22.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.03:32:22.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.03:32:22.33$vck44/vb=6,4 2006.201.03:32:22.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.03:32:22.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.03:32:22.33#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:22.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:22.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:22.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:22.39#ibcon#enter wrdev, iclass 39, count 2 2006.201.03:32:22.39#ibcon#first serial, iclass 39, count 2 2006.201.03:32:22.39#ibcon#enter sib2, iclass 39, count 2 2006.201.03:32:22.39#ibcon#flushed, iclass 39, count 2 2006.201.03:32:22.39#ibcon#about to write, iclass 39, count 2 2006.201.03:32:22.39#ibcon#wrote, iclass 39, count 2 2006.201.03:32:22.39#ibcon#about to read 3, iclass 39, count 2 2006.201.03:32:22.41#ibcon#read 3, iclass 39, count 2 2006.201.03:32:22.41#ibcon#about to read 4, iclass 39, count 2 2006.201.03:32:22.41#ibcon#read 4, iclass 39, count 2 2006.201.03:32:22.41#ibcon#about to read 5, iclass 39, count 2 2006.201.03:32:22.41#ibcon#read 5, iclass 39, count 2 2006.201.03:32:22.41#ibcon#about to read 6, iclass 39, count 2 2006.201.03:32:22.41#ibcon#read 6, iclass 39, count 2 2006.201.03:32:22.41#ibcon#end of sib2, iclass 39, count 2 2006.201.03:32:22.41#ibcon#*mode == 0, iclass 39, count 2 2006.201.03:32:22.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.03:32:22.41#ibcon#[27=AT06-04\r\n] 2006.201.03:32:22.41#ibcon#*before write, iclass 39, count 2 2006.201.03:32:22.41#ibcon#enter sib2, iclass 39, count 2 2006.201.03:32:22.41#ibcon#flushed, iclass 39, count 2 2006.201.03:32:22.41#ibcon#about to write, iclass 39, count 2 2006.201.03:32:22.41#ibcon#wrote, iclass 39, count 2 2006.201.03:32:22.41#ibcon#about to read 3, iclass 39, count 2 2006.201.03:32:22.44#ibcon#read 3, iclass 39, count 2 2006.201.03:32:22.44#ibcon#about to read 4, iclass 39, count 2 2006.201.03:32:22.44#ibcon#read 4, iclass 39, count 2 2006.201.03:32:22.44#ibcon#about to read 5, iclass 39, count 2 2006.201.03:32:22.44#ibcon#read 5, iclass 39, count 2 2006.201.03:32:22.44#ibcon#about to read 6, iclass 39, count 2 2006.201.03:32:22.44#ibcon#read 6, iclass 39, count 2 2006.201.03:32:22.44#ibcon#end of sib2, iclass 39, count 2 2006.201.03:32:22.44#ibcon#*after write, iclass 39, count 2 2006.201.03:32:22.44#ibcon#*before return 0, iclass 39, count 2 2006.201.03:32:22.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:22.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:32:22.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.03:32:22.44#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:22.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:22.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:22.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:22.56#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:32:22.56#ibcon#first serial, iclass 39, count 0 2006.201.03:32:22.56#ibcon#enter sib2, iclass 39, count 0 2006.201.03:32:22.56#ibcon#flushed, iclass 39, count 0 2006.201.03:32:22.56#ibcon#about to write, iclass 39, count 0 2006.201.03:32:22.56#ibcon#wrote, iclass 39, count 0 2006.201.03:32:22.56#ibcon#about to read 3, iclass 39, count 0 2006.201.03:32:22.58#ibcon#read 3, iclass 39, count 0 2006.201.03:32:22.58#ibcon#about to read 4, iclass 39, count 0 2006.201.03:32:22.58#ibcon#read 4, iclass 39, count 0 2006.201.03:32:22.58#ibcon#about to read 5, iclass 39, count 0 2006.201.03:32:22.58#ibcon#read 5, iclass 39, count 0 2006.201.03:32:22.58#ibcon#about to read 6, iclass 39, count 0 2006.201.03:32:22.58#ibcon#read 6, iclass 39, count 0 2006.201.03:32:22.58#ibcon#end of sib2, iclass 39, count 0 2006.201.03:32:22.58#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:32:22.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:32:22.58#ibcon#[27=USB\r\n] 2006.201.03:32:22.58#ibcon#*before write, iclass 39, count 0 2006.201.03:32:22.58#ibcon#enter sib2, iclass 39, count 0 2006.201.03:32:22.58#ibcon#flushed, iclass 39, count 0 2006.201.03:32:22.58#ibcon#about to write, iclass 39, count 0 2006.201.03:32:22.58#ibcon#wrote, iclass 39, count 0 2006.201.03:32:22.58#ibcon#about to read 3, iclass 39, count 0 2006.201.03:32:22.61#ibcon#read 3, iclass 39, count 0 2006.201.03:32:22.61#ibcon#about to read 4, iclass 39, count 0 2006.201.03:32:22.61#ibcon#read 4, iclass 39, count 0 2006.201.03:32:22.61#ibcon#about to read 5, iclass 39, count 0 2006.201.03:32:22.61#ibcon#read 5, iclass 39, count 0 2006.201.03:32:22.61#ibcon#about to read 6, iclass 39, count 0 2006.201.03:32:22.61#ibcon#read 6, iclass 39, count 0 2006.201.03:32:22.61#ibcon#end of sib2, iclass 39, count 0 2006.201.03:32:22.61#ibcon#*after write, iclass 39, count 0 2006.201.03:32:22.61#ibcon#*before return 0, iclass 39, count 0 2006.201.03:32:22.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:22.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:32:22.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:32:22.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:32:22.61$vck44/vblo=7,734.99 2006.201.03:32:22.61#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.03:32:22.61#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.03:32:22.61#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:22.61#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:22.61#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:22.61#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:22.61#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:32:22.61#ibcon#first serial, iclass 2, count 0 2006.201.03:32:22.61#ibcon#enter sib2, iclass 2, count 0 2006.201.03:32:22.61#ibcon#flushed, iclass 2, count 0 2006.201.03:32:22.61#ibcon#about to write, iclass 2, count 0 2006.201.03:32:22.61#ibcon#wrote, iclass 2, count 0 2006.201.03:32:22.61#ibcon#about to read 3, iclass 2, count 0 2006.201.03:32:22.63#ibcon#read 3, iclass 2, count 0 2006.201.03:32:22.63#ibcon#about to read 4, iclass 2, count 0 2006.201.03:32:22.63#ibcon#read 4, iclass 2, count 0 2006.201.03:32:22.63#ibcon#about to read 5, iclass 2, count 0 2006.201.03:32:22.63#ibcon#read 5, iclass 2, count 0 2006.201.03:32:22.63#ibcon#about to read 6, iclass 2, count 0 2006.201.03:32:22.63#ibcon#read 6, iclass 2, count 0 2006.201.03:32:22.63#ibcon#end of sib2, iclass 2, count 0 2006.201.03:32:22.63#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:32:22.63#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:32:22.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:32:22.63#ibcon#*before write, iclass 2, count 0 2006.201.03:32:22.63#ibcon#enter sib2, iclass 2, count 0 2006.201.03:32:22.63#ibcon#flushed, iclass 2, count 0 2006.201.03:32:22.63#ibcon#about to write, iclass 2, count 0 2006.201.03:32:22.63#ibcon#wrote, iclass 2, count 0 2006.201.03:32:22.63#ibcon#about to read 3, iclass 2, count 0 2006.201.03:32:22.67#ibcon#read 3, iclass 2, count 0 2006.201.03:32:22.67#ibcon#about to read 4, iclass 2, count 0 2006.201.03:32:22.67#ibcon#read 4, iclass 2, count 0 2006.201.03:32:22.67#ibcon#about to read 5, iclass 2, count 0 2006.201.03:32:22.67#ibcon#read 5, iclass 2, count 0 2006.201.03:32:22.67#ibcon#about to read 6, iclass 2, count 0 2006.201.03:32:22.67#ibcon#read 6, iclass 2, count 0 2006.201.03:32:22.67#ibcon#end of sib2, iclass 2, count 0 2006.201.03:32:22.67#ibcon#*after write, iclass 2, count 0 2006.201.03:32:22.67#ibcon#*before return 0, iclass 2, count 0 2006.201.03:32:22.67#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:22.67#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:32:22.67#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:32:22.67#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:32:22.67$vck44/vb=7,4 2006.201.03:32:22.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.03:32:22.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.03:32:22.67#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:22.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:22.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:22.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:22.73#ibcon#enter wrdev, iclass 5, count 2 2006.201.03:32:22.73#ibcon#first serial, iclass 5, count 2 2006.201.03:32:22.73#ibcon#enter sib2, iclass 5, count 2 2006.201.03:32:22.73#ibcon#flushed, iclass 5, count 2 2006.201.03:32:22.73#ibcon#about to write, iclass 5, count 2 2006.201.03:32:22.73#ibcon#wrote, iclass 5, count 2 2006.201.03:32:22.73#ibcon#about to read 3, iclass 5, count 2 2006.201.03:32:22.75#ibcon#read 3, iclass 5, count 2 2006.201.03:32:22.75#ibcon#about to read 4, iclass 5, count 2 2006.201.03:32:22.75#ibcon#read 4, iclass 5, count 2 2006.201.03:32:22.75#ibcon#about to read 5, iclass 5, count 2 2006.201.03:32:22.75#ibcon#read 5, iclass 5, count 2 2006.201.03:32:22.75#ibcon#about to read 6, iclass 5, count 2 2006.201.03:32:22.75#ibcon#read 6, iclass 5, count 2 2006.201.03:32:22.75#ibcon#end of sib2, iclass 5, count 2 2006.201.03:32:22.75#ibcon#*mode == 0, iclass 5, count 2 2006.201.03:32:22.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.03:32:22.75#ibcon#[27=AT07-04\r\n] 2006.201.03:32:22.75#ibcon#*before write, iclass 5, count 2 2006.201.03:32:22.75#ibcon#enter sib2, iclass 5, count 2 2006.201.03:32:22.75#ibcon#flushed, iclass 5, count 2 2006.201.03:32:22.75#ibcon#about to write, iclass 5, count 2 2006.201.03:32:22.75#ibcon#wrote, iclass 5, count 2 2006.201.03:32:22.75#ibcon#about to read 3, iclass 5, count 2 2006.201.03:32:22.78#ibcon#read 3, iclass 5, count 2 2006.201.03:32:22.78#ibcon#about to read 4, iclass 5, count 2 2006.201.03:32:22.78#ibcon#read 4, iclass 5, count 2 2006.201.03:32:22.78#ibcon#about to read 5, iclass 5, count 2 2006.201.03:32:22.78#ibcon#read 5, iclass 5, count 2 2006.201.03:32:22.78#ibcon#about to read 6, iclass 5, count 2 2006.201.03:32:22.78#ibcon#read 6, iclass 5, count 2 2006.201.03:32:22.78#ibcon#end of sib2, iclass 5, count 2 2006.201.03:32:22.78#ibcon#*after write, iclass 5, count 2 2006.201.03:32:22.78#ibcon#*before return 0, iclass 5, count 2 2006.201.03:32:22.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:22.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:32:22.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.03:32:22.78#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:22.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:22.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:22.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:22.90#ibcon#enter wrdev, iclass 5, count 0 2006.201.03:32:22.90#ibcon#first serial, iclass 5, count 0 2006.201.03:32:22.90#ibcon#enter sib2, iclass 5, count 0 2006.201.03:32:22.90#ibcon#flushed, iclass 5, count 0 2006.201.03:32:22.90#ibcon#about to write, iclass 5, count 0 2006.201.03:32:22.90#ibcon#wrote, iclass 5, count 0 2006.201.03:32:22.90#ibcon#about to read 3, iclass 5, count 0 2006.201.03:32:22.92#ibcon#read 3, iclass 5, count 0 2006.201.03:32:22.92#ibcon#about to read 4, iclass 5, count 0 2006.201.03:32:22.92#ibcon#read 4, iclass 5, count 0 2006.201.03:32:22.92#ibcon#about to read 5, iclass 5, count 0 2006.201.03:32:22.92#ibcon#read 5, iclass 5, count 0 2006.201.03:32:22.92#ibcon#about to read 6, iclass 5, count 0 2006.201.03:32:22.92#ibcon#read 6, iclass 5, count 0 2006.201.03:32:22.92#ibcon#end of sib2, iclass 5, count 0 2006.201.03:32:22.92#ibcon#*mode == 0, iclass 5, count 0 2006.201.03:32:22.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.03:32:22.92#ibcon#[27=USB\r\n] 2006.201.03:32:22.92#ibcon#*before write, iclass 5, count 0 2006.201.03:32:22.92#ibcon#enter sib2, iclass 5, count 0 2006.201.03:32:22.92#ibcon#flushed, iclass 5, count 0 2006.201.03:32:22.92#ibcon#about to write, iclass 5, count 0 2006.201.03:32:22.92#ibcon#wrote, iclass 5, count 0 2006.201.03:32:22.92#ibcon#about to read 3, iclass 5, count 0 2006.201.03:32:22.95#ibcon#read 3, iclass 5, count 0 2006.201.03:32:22.95#ibcon#about to read 4, iclass 5, count 0 2006.201.03:32:22.95#ibcon#read 4, iclass 5, count 0 2006.201.03:32:22.95#ibcon#about to read 5, iclass 5, count 0 2006.201.03:32:22.95#ibcon#read 5, iclass 5, count 0 2006.201.03:32:22.95#ibcon#about to read 6, iclass 5, count 0 2006.201.03:32:22.95#ibcon#read 6, iclass 5, count 0 2006.201.03:32:22.95#ibcon#end of sib2, iclass 5, count 0 2006.201.03:32:22.95#ibcon#*after write, iclass 5, count 0 2006.201.03:32:22.95#ibcon#*before return 0, iclass 5, count 0 2006.201.03:32:22.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:22.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:32:22.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.03:32:22.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.03:32:22.95$vck44/vblo=8,744.99 2006.201.03:32:22.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.03:32:22.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.03:32:22.95#ibcon#ireg 17 cls_cnt 0 2006.201.03:32:22.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:22.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:22.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:22.95#ibcon#enter wrdev, iclass 7, count 0 2006.201.03:32:22.95#ibcon#first serial, iclass 7, count 0 2006.201.03:32:22.95#ibcon#enter sib2, iclass 7, count 0 2006.201.03:32:22.95#ibcon#flushed, iclass 7, count 0 2006.201.03:32:22.95#ibcon#about to write, iclass 7, count 0 2006.201.03:32:22.95#ibcon#wrote, iclass 7, count 0 2006.201.03:32:22.95#ibcon#about to read 3, iclass 7, count 0 2006.201.03:32:22.97#ibcon#read 3, iclass 7, count 0 2006.201.03:32:22.97#ibcon#about to read 4, iclass 7, count 0 2006.201.03:32:22.97#ibcon#read 4, iclass 7, count 0 2006.201.03:32:22.97#ibcon#about to read 5, iclass 7, count 0 2006.201.03:32:22.97#ibcon#read 5, iclass 7, count 0 2006.201.03:32:22.97#ibcon#about to read 6, iclass 7, count 0 2006.201.03:32:22.97#ibcon#read 6, iclass 7, count 0 2006.201.03:32:22.97#ibcon#end of sib2, iclass 7, count 0 2006.201.03:32:22.97#ibcon#*mode == 0, iclass 7, count 0 2006.201.03:32:22.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.03:32:22.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:32:22.97#ibcon#*before write, iclass 7, count 0 2006.201.03:32:22.97#ibcon#enter sib2, iclass 7, count 0 2006.201.03:32:22.97#ibcon#flushed, iclass 7, count 0 2006.201.03:32:22.97#ibcon#about to write, iclass 7, count 0 2006.201.03:32:22.97#ibcon#wrote, iclass 7, count 0 2006.201.03:32:22.97#ibcon#about to read 3, iclass 7, count 0 2006.201.03:32:23.01#ibcon#read 3, iclass 7, count 0 2006.201.03:32:23.01#ibcon#about to read 4, iclass 7, count 0 2006.201.03:32:23.01#ibcon#read 4, iclass 7, count 0 2006.201.03:32:23.01#ibcon#about to read 5, iclass 7, count 0 2006.201.03:32:23.01#ibcon#read 5, iclass 7, count 0 2006.201.03:32:23.01#ibcon#about to read 6, iclass 7, count 0 2006.201.03:32:23.01#ibcon#read 6, iclass 7, count 0 2006.201.03:32:23.01#ibcon#end of sib2, iclass 7, count 0 2006.201.03:32:23.01#ibcon#*after write, iclass 7, count 0 2006.201.03:32:23.01#ibcon#*before return 0, iclass 7, count 0 2006.201.03:32:23.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:23.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:32:23.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.03:32:23.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.03:32:23.01$vck44/vb=8,4 2006.201.03:32:23.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.03:32:23.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.03:32:23.01#ibcon#ireg 11 cls_cnt 2 2006.201.03:32:23.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:23.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:23.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:23.07#ibcon#enter wrdev, iclass 11, count 2 2006.201.03:32:23.07#ibcon#first serial, iclass 11, count 2 2006.201.03:32:23.07#ibcon#enter sib2, iclass 11, count 2 2006.201.03:32:23.07#ibcon#flushed, iclass 11, count 2 2006.201.03:32:23.07#ibcon#about to write, iclass 11, count 2 2006.201.03:32:23.07#ibcon#wrote, iclass 11, count 2 2006.201.03:32:23.07#ibcon#about to read 3, iclass 11, count 2 2006.201.03:32:23.09#ibcon#read 3, iclass 11, count 2 2006.201.03:32:23.09#ibcon#about to read 4, iclass 11, count 2 2006.201.03:32:23.09#ibcon#read 4, iclass 11, count 2 2006.201.03:32:23.09#ibcon#about to read 5, iclass 11, count 2 2006.201.03:32:23.09#ibcon#read 5, iclass 11, count 2 2006.201.03:32:23.09#ibcon#about to read 6, iclass 11, count 2 2006.201.03:32:23.09#ibcon#read 6, iclass 11, count 2 2006.201.03:32:23.09#ibcon#end of sib2, iclass 11, count 2 2006.201.03:32:23.09#ibcon#*mode == 0, iclass 11, count 2 2006.201.03:32:23.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.03:32:23.09#ibcon#[27=AT08-04\r\n] 2006.201.03:32:23.09#ibcon#*before write, iclass 11, count 2 2006.201.03:32:23.09#ibcon#enter sib2, iclass 11, count 2 2006.201.03:32:23.09#ibcon#flushed, iclass 11, count 2 2006.201.03:32:23.09#ibcon#about to write, iclass 11, count 2 2006.201.03:32:23.09#ibcon#wrote, iclass 11, count 2 2006.201.03:32:23.09#ibcon#about to read 3, iclass 11, count 2 2006.201.03:32:23.12#ibcon#read 3, iclass 11, count 2 2006.201.03:32:23.12#ibcon#about to read 4, iclass 11, count 2 2006.201.03:32:23.12#ibcon#read 4, iclass 11, count 2 2006.201.03:32:23.12#ibcon#about to read 5, iclass 11, count 2 2006.201.03:32:23.12#ibcon#read 5, iclass 11, count 2 2006.201.03:32:23.12#ibcon#about to read 6, iclass 11, count 2 2006.201.03:32:23.12#ibcon#read 6, iclass 11, count 2 2006.201.03:32:23.12#ibcon#end of sib2, iclass 11, count 2 2006.201.03:32:23.12#ibcon#*after write, iclass 11, count 2 2006.201.03:32:23.12#ibcon#*before return 0, iclass 11, count 2 2006.201.03:32:23.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:23.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:32:23.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.03:32:23.12#ibcon#ireg 7 cls_cnt 0 2006.201.03:32:23.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:23.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:23.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:23.24#ibcon#enter wrdev, iclass 11, count 0 2006.201.03:32:23.24#ibcon#first serial, iclass 11, count 0 2006.201.03:32:23.24#ibcon#enter sib2, iclass 11, count 0 2006.201.03:32:23.24#ibcon#flushed, iclass 11, count 0 2006.201.03:32:23.24#ibcon#about to write, iclass 11, count 0 2006.201.03:32:23.24#ibcon#wrote, iclass 11, count 0 2006.201.03:32:23.24#ibcon#about to read 3, iclass 11, count 0 2006.201.03:32:23.26#ibcon#read 3, iclass 11, count 0 2006.201.03:32:23.26#ibcon#about to read 4, iclass 11, count 0 2006.201.03:32:23.26#ibcon#read 4, iclass 11, count 0 2006.201.03:32:23.26#ibcon#about to read 5, iclass 11, count 0 2006.201.03:32:23.26#ibcon#read 5, iclass 11, count 0 2006.201.03:32:23.26#ibcon#about to read 6, iclass 11, count 0 2006.201.03:32:23.26#ibcon#read 6, iclass 11, count 0 2006.201.03:32:23.26#ibcon#end of sib2, iclass 11, count 0 2006.201.03:32:23.26#ibcon#*mode == 0, iclass 11, count 0 2006.201.03:32:23.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.03:32:23.26#ibcon#[27=USB\r\n] 2006.201.03:32:23.26#ibcon#*before write, iclass 11, count 0 2006.201.03:32:23.26#ibcon#enter sib2, iclass 11, count 0 2006.201.03:32:23.26#ibcon#flushed, iclass 11, count 0 2006.201.03:32:23.26#ibcon#about to write, iclass 11, count 0 2006.201.03:32:23.26#ibcon#wrote, iclass 11, count 0 2006.201.03:32:23.26#ibcon#about to read 3, iclass 11, count 0 2006.201.03:32:23.29#ibcon#read 3, iclass 11, count 0 2006.201.03:32:23.29#ibcon#about to read 4, iclass 11, count 0 2006.201.03:32:23.29#ibcon#read 4, iclass 11, count 0 2006.201.03:32:23.29#ibcon#about to read 5, iclass 11, count 0 2006.201.03:32:23.29#ibcon#read 5, iclass 11, count 0 2006.201.03:32:23.29#ibcon#about to read 6, iclass 11, count 0 2006.201.03:32:23.29#ibcon#read 6, iclass 11, count 0 2006.201.03:32:23.29#ibcon#end of sib2, iclass 11, count 0 2006.201.03:32:23.29#ibcon#*after write, iclass 11, count 0 2006.201.03:32:23.29#ibcon#*before return 0, iclass 11, count 0 2006.201.03:32:23.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:23.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:32:23.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.03:32:23.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.03:32:23.29$vck44/vabw=wide 2006.201.03:32:23.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.03:32:23.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.03:32:23.29#ibcon#ireg 8 cls_cnt 0 2006.201.03:32:23.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:23.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:23.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:23.29#ibcon#enter wrdev, iclass 13, count 0 2006.201.03:32:23.29#ibcon#first serial, iclass 13, count 0 2006.201.03:32:23.29#ibcon#enter sib2, iclass 13, count 0 2006.201.03:32:23.29#ibcon#flushed, iclass 13, count 0 2006.201.03:32:23.29#ibcon#about to write, iclass 13, count 0 2006.201.03:32:23.29#ibcon#wrote, iclass 13, count 0 2006.201.03:32:23.29#ibcon#about to read 3, iclass 13, count 0 2006.201.03:32:23.31#ibcon#read 3, iclass 13, count 0 2006.201.03:32:23.31#ibcon#about to read 4, iclass 13, count 0 2006.201.03:32:23.31#ibcon#read 4, iclass 13, count 0 2006.201.03:32:23.31#ibcon#about to read 5, iclass 13, count 0 2006.201.03:32:23.31#ibcon#read 5, iclass 13, count 0 2006.201.03:32:23.31#ibcon#about to read 6, iclass 13, count 0 2006.201.03:32:23.31#ibcon#read 6, iclass 13, count 0 2006.201.03:32:23.31#ibcon#end of sib2, iclass 13, count 0 2006.201.03:32:23.31#ibcon#*mode == 0, iclass 13, count 0 2006.201.03:32:23.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.03:32:23.31#ibcon#[25=BW32\r\n] 2006.201.03:32:23.31#ibcon#*before write, iclass 13, count 0 2006.201.03:32:23.31#ibcon#enter sib2, iclass 13, count 0 2006.201.03:32:23.31#ibcon#flushed, iclass 13, count 0 2006.201.03:32:23.31#ibcon#about to write, iclass 13, count 0 2006.201.03:32:23.31#ibcon#wrote, iclass 13, count 0 2006.201.03:32:23.31#ibcon#about to read 3, iclass 13, count 0 2006.201.03:32:23.34#ibcon#read 3, iclass 13, count 0 2006.201.03:32:23.34#ibcon#about to read 4, iclass 13, count 0 2006.201.03:32:23.34#ibcon#read 4, iclass 13, count 0 2006.201.03:32:23.34#ibcon#about to read 5, iclass 13, count 0 2006.201.03:32:23.34#ibcon#read 5, iclass 13, count 0 2006.201.03:32:23.34#ibcon#about to read 6, iclass 13, count 0 2006.201.03:32:23.34#ibcon#read 6, iclass 13, count 0 2006.201.03:32:23.34#ibcon#end of sib2, iclass 13, count 0 2006.201.03:32:23.34#ibcon#*after write, iclass 13, count 0 2006.201.03:32:23.34#ibcon#*before return 0, iclass 13, count 0 2006.201.03:32:23.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:23.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:32:23.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.03:32:23.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.03:32:23.34$vck44/vbbw=wide 2006.201.03:32:23.34#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.03:32:23.34#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.03:32:23.34#ibcon#ireg 8 cls_cnt 0 2006.201.03:32:23.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:32:23.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:32:23.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:32:23.41#ibcon#enter wrdev, iclass 15, count 0 2006.201.03:32:23.41#ibcon#first serial, iclass 15, count 0 2006.201.03:32:23.41#ibcon#enter sib2, iclass 15, count 0 2006.201.03:32:23.41#ibcon#flushed, iclass 15, count 0 2006.201.03:32:23.41#ibcon#about to write, iclass 15, count 0 2006.201.03:32:23.41#ibcon#wrote, iclass 15, count 0 2006.201.03:32:23.41#ibcon#about to read 3, iclass 15, count 0 2006.201.03:32:23.43#ibcon#read 3, iclass 15, count 0 2006.201.03:32:23.43#ibcon#about to read 4, iclass 15, count 0 2006.201.03:32:23.43#ibcon#read 4, iclass 15, count 0 2006.201.03:32:23.43#ibcon#about to read 5, iclass 15, count 0 2006.201.03:32:23.43#ibcon#read 5, iclass 15, count 0 2006.201.03:32:23.43#ibcon#about to read 6, iclass 15, count 0 2006.201.03:32:23.43#ibcon#read 6, iclass 15, count 0 2006.201.03:32:23.43#ibcon#end of sib2, iclass 15, count 0 2006.201.03:32:23.43#ibcon#*mode == 0, iclass 15, count 0 2006.201.03:32:23.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.03:32:23.43#ibcon#[27=BW32\r\n] 2006.201.03:32:23.43#ibcon#*before write, iclass 15, count 0 2006.201.03:32:23.43#ibcon#enter sib2, iclass 15, count 0 2006.201.03:32:23.43#ibcon#flushed, iclass 15, count 0 2006.201.03:32:23.43#ibcon#about to write, iclass 15, count 0 2006.201.03:32:23.43#ibcon#wrote, iclass 15, count 0 2006.201.03:32:23.43#ibcon#about to read 3, iclass 15, count 0 2006.201.03:32:23.46#ibcon#read 3, iclass 15, count 0 2006.201.03:32:23.46#ibcon#about to read 4, iclass 15, count 0 2006.201.03:32:23.46#ibcon#read 4, iclass 15, count 0 2006.201.03:32:23.46#ibcon#about to read 5, iclass 15, count 0 2006.201.03:32:23.46#ibcon#read 5, iclass 15, count 0 2006.201.03:32:23.46#ibcon#about to read 6, iclass 15, count 0 2006.201.03:32:23.46#ibcon#read 6, iclass 15, count 0 2006.201.03:32:23.46#ibcon#end of sib2, iclass 15, count 0 2006.201.03:32:23.46#ibcon#*after write, iclass 15, count 0 2006.201.03:32:23.46#ibcon#*before return 0, iclass 15, count 0 2006.201.03:32:23.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:32:23.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:32:23.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.03:32:23.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.03:32:23.46$setupk4/ifdk4 2006.201.03:32:23.46$ifdk4/lo= 2006.201.03:32:23.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:32:23.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:32:23.46$ifdk4/patch= 2006.201.03:32:23.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:32:23.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:32:23.46$setupk4/!*+20s 2006.201.03:32:23.67#abcon#<5=/03 2.7 4.7 23.04 911004.5\r\n> 2006.201.03:32:23.69#abcon#{5=INTERFACE CLEAR} 2006.201.03:32:23.75#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:32:33.84#abcon#<5=/03 2.7 4.7 23.04 911004.5\r\n> 2006.201.03:32:33.86#abcon#{5=INTERFACE CLEAR} 2006.201.03:32:33.92#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:32:34.14#trakl#Source acquired 2006.201.03:32:34.14#flagr#flagr/antenna,acquired 2006.201.03:32:37.92$setupk4/"tpicd 2006.201.03:32:37.92$setupk4/echo=off 2006.201.03:32:37.92$setupk4/xlog=off 2006.201.03:32:37.92:!2006.201.03:36:44 2006.201.03:36:44.00:preob 2006.201.03:36:44.14/onsource/TRACKING 2006.201.03:36:44.14:!2006.201.03:36:54 2006.201.03:36:54.00:"tape 2006.201.03:36:54.00:"st=record 2006.201.03:36:54.00:data_valid=on 2006.201.03:36:54.00:midob 2006.201.03:36:55.14/onsource/TRACKING 2006.201.03:36:55.14/wx/23.04,1004.5,92 2006.201.03:36:55.20/cable/+6.4661E-03 2006.201.03:36:56.29/va/01,08,usb,yes,38,40 2006.201.03:36:56.29/va/02,07,usb,yes,41,42 2006.201.03:36:56.29/va/03,08,usb,yes,37,39 2006.201.03:36:56.29/va/04,07,usb,yes,42,44 2006.201.03:36:56.29/va/05,04,usb,yes,37,38 2006.201.03:36:56.29/va/06,05,usb,yes,37,37 2006.201.03:36:56.29/va/07,05,usb,yes,36,38 2006.201.03:36:56.29/va/08,04,usb,yes,36,43 2006.201.03:36:56.52/valo/01,524.99,yes,locked 2006.201.03:36:56.52/valo/02,534.99,yes,locked 2006.201.03:36:56.52/valo/03,564.99,yes,locked 2006.201.03:36:56.52/valo/04,624.99,yes,locked 2006.201.03:36:56.52/valo/05,734.99,yes,locked 2006.201.03:36:56.52/valo/06,814.99,yes,locked 2006.201.03:36:56.52/valo/07,864.99,yes,locked 2006.201.03:36:56.52/valo/08,884.99,yes,locked 2006.201.03:36:57.61/vb/01,04,usb,yes,33,30 2006.201.03:36:57.61/vb/02,05,usb,yes,31,31 2006.201.03:36:57.61/vb/03,04,usb,yes,32,36 2006.201.03:36:57.61/vb/04,05,usb,yes,32,31 2006.201.03:36:57.61/vb/05,04,usb,yes,29,32 2006.201.03:36:57.61/vb/06,04,usb,yes,34,30 2006.201.03:36:57.61/vb/07,04,usb,yes,34,34 2006.201.03:36:57.61/vb/08,04,usb,yes,31,35 2006.201.03:36:57.84/vblo/01,629.99,yes,locked 2006.201.03:36:57.84/vblo/02,634.99,yes,locked 2006.201.03:36:57.84/vblo/03,649.99,yes,locked 2006.201.03:36:57.84/vblo/04,679.99,yes,locked 2006.201.03:36:57.84/vblo/05,709.99,yes,locked 2006.201.03:36:57.84/vblo/06,719.99,yes,locked 2006.201.03:36:57.84/vblo/07,734.99,yes,locked 2006.201.03:36:57.84/vblo/08,744.99,yes,locked 2006.201.03:36:57.99/vabw/8 2006.201.03:36:58.14/vbbw/8 2006.201.03:36:58.23/xfe/off,on,15.0 2006.201.03:36:58.60/ifatt/23,28,28,28 2006.201.03:36:59.05/fmout-gps/S +4.53E-07 2006.201.03:36:59.10:!2006.201.03:37:34 2006.201.03:37:34.00:data_valid=off 2006.201.03:37:34.00:"et 2006.201.03:37:34.00:!+3s 2006.201.03:37:37.01:"tape 2006.201.03:37:37.01:postob 2006.201.03:37:37.11/cable/+6.4647E-03 2006.201.03:37:37.11/wx/23.04,1004.6,92 2006.201.03:37:37.17/fmout-gps/S +4.53E-07 2006.201.03:37:37.17:scan_name=201-0338,jd0607,170 2006.201.03:37:37.17:source=1611+343,161341.06,341247.9,2000.0,cw 2006.201.03:37:39.14#flagr#flagr/antenna,new-source 2006.201.03:37:39.14:checkk5 2006.201.03:37:39.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:37:39.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:37:40.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:37:40.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:37:41.01/chk_obsdata//k5ts1/T2010336??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.03:37:41.38/chk_obsdata//k5ts2/T2010336??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.03:37:41.75/chk_obsdata//k5ts3/T2010336??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.03:37:42.12/chk_obsdata//k5ts4/T2010336??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.03:37:42.81/k5log//k5ts1_log_newline 2006.201.03:37:43.50/k5log//k5ts2_log_newline 2006.201.03:37:44.18/k5log//k5ts3_log_newline 2006.201.03:37:44.87/k5log//k5ts4_log_newline 2006.201.03:37:44.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:37:44.89:setupk4=1 2006.201.03:37:44.89$setupk4/echo=on 2006.201.03:37:44.89$setupk4/pcalon 2006.201.03:37:44.89$pcalon/"no phase cal control is implemented here 2006.201.03:37:44.89$setupk4/"tpicd=stop 2006.201.03:37:44.89$setupk4/"rec=synch_on 2006.201.03:37:44.89$setupk4/"rec_mode=128 2006.201.03:37:44.89$setupk4/!* 2006.201.03:37:44.89$setupk4/recpk4 2006.201.03:37:44.89$recpk4/recpatch= 2006.201.03:37:44.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:37:44.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:37:44.90$setupk4/vck44 2006.201.03:37:44.90$vck44/valo=1,524.99 2006.201.03:37:44.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.03:37:44.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.03:37:44.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:44.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:44.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:44.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:44.90#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:37:44.90#ibcon#first serial, iclass 40, count 0 2006.201.03:37:44.90#ibcon#enter sib2, iclass 40, count 0 2006.201.03:37:44.90#ibcon#flushed, iclass 40, count 0 2006.201.03:37:44.90#ibcon#about to write, iclass 40, count 0 2006.201.03:37:44.90#ibcon#wrote, iclass 40, count 0 2006.201.03:37:44.90#ibcon#about to read 3, iclass 40, count 0 2006.201.03:37:44.94#ibcon#read 3, iclass 40, count 0 2006.201.03:37:44.94#ibcon#about to read 4, iclass 40, count 0 2006.201.03:37:44.94#ibcon#read 4, iclass 40, count 0 2006.201.03:37:44.94#ibcon#about to read 5, iclass 40, count 0 2006.201.03:37:44.94#ibcon#read 5, iclass 40, count 0 2006.201.03:37:44.94#ibcon#about to read 6, iclass 40, count 0 2006.201.03:37:44.94#ibcon#read 6, iclass 40, count 0 2006.201.03:37:44.94#ibcon#end of sib2, iclass 40, count 0 2006.201.03:37:44.94#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:37:44.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:37:44.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:37:44.94#ibcon#*before write, iclass 40, count 0 2006.201.03:37:44.94#ibcon#enter sib2, iclass 40, count 0 2006.201.03:37:44.94#ibcon#flushed, iclass 40, count 0 2006.201.03:37:44.94#ibcon#about to write, iclass 40, count 0 2006.201.03:37:44.94#ibcon#wrote, iclass 40, count 0 2006.201.03:37:44.94#ibcon#about to read 3, iclass 40, count 0 2006.201.03:37:44.99#ibcon#read 3, iclass 40, count 0 2006.201.03:37:44.99#ibcon#about to read 4, iclass 40, count 0 2006.201.03:37:44.99#ibcon#read 4, iclass 40, count 0 2006.201.03:37:44.99#ibcon#about to read 5, iclass 40, count 0 2006.201.03:37:44.99#ibcon#read 5, iclass 40, count 0 2006.201.03:37:44.99#ibcon#about to read 6, iclass 40, count 0 2006.201.03:37:44.99#ibcon#read 6, iclass 40, count 0 2006.201.03:37:44.99#ibcon#end of sib2, iclass 40, count 0 2006.201.03:37:44.99#ibcon#*after write, iclass 40, count 0 2006.201.03:37:44.99#ibcon#*before return 0, iclass 40, count 0 2006.201.03:37:44.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:44.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:44.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:37:44.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:37:44.99$vck44/va=1,8 2006.201.03:37:44.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.03:37:44.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.03:37:44.99#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:44.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:44.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:44.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:44.99#ibcon#enter wrdev, iclass 4, count 2 2006.201.03:37:44.99#ibcon#first serial, iclass 4, count 2 2006.201.03:37:44.99#ibcon#enter sib2, iclass 4, count 2 2006.201.03:37:44.99#ibcon#flushed, iclass 4, count 2 2006.201.03:37:44.99#ibcon#about to write, iclass 4, count 2 2006.201.03:37:44.99#ibcon#wrote, iclass 4, count 2 2006.201.03:37:44.99#ibcon#about to read 3, iclass 4, count 2 2006.201.03:37:45.01#ibcon#read 3, iclass 4, count 2 2006.201.03:37:45.01#ibcon#about to read 4, iclass 4, count 2 2006.201.03:37:45.01#ibcon#read 4, iclass 4, count 2 2006.201.03:37:45.01#ibcon#about to read 5, iclass 4, count 2 2006.201.03:37:45.01#ibcon#read 5, iclass 4, count 2 2006.201.03:37:45.01#ibcon#about to read 6, iclass 4, count 2 2006.201.03:37:45.01#ibcon#read 6, iclass 4, count 2 2006.201.03:37:45.01#ibcon#end of sib2, iclass 4, count 2 2006.201.03:37:45.01#ibcon#*mode == 0, iclass 4, count 2 2006.201.03:37:45.01#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.03:37:45.01#ibcon#[25=AT01-08\r\n] 2006.201.03:37:45.01#ibcon#*before write, iclass 4, count 2 2006.201.03:37:45.01#ibcon#enter sib2, iclass 4, count 2 2006.201.03:37:45.01#ibcon#flushed, iclass 4, count 2 2006.201.03:37:45.01#ibcon#about to write, iclass 4, count 2 2006.201.03:37:45.01#ibcon#wrote, iclass 4, count 2 2006.201.03:37:45.01#ibcon#about to read 3, iclass 4, count 2 2006.201.03:37:45.04#ibcon#read 3, iclass 4, count 2 2006.201.03:37:45.04#ibcon#about to read 4, iclass 4, count 2 2006.201.03:37:45.04#ibcon#read 4, iclass 4, count 2 2006.201.03:37:45.04#ibcon#about to read 5, iclass 4, count 2 2006.201.03:37:45.04#ibcon#read 5, iclass 4, count 2 2006.201.03:37:45.04#ibcon#about to read 6, iclass 4, count 2 2006.201.03:37:45.04#ibcon#read 6, iclass 4, count 2 2006.201.03:37:45.04#ibcon#end of sib2, iclass 4, count 2 2006.201.03:37:45.04#ibcon#*after write, iclass 4, count 2 2006.201.03:37:45.04#ibcon#*before return 0, iclass 4, count 2 2006.201.03:37:45.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:45.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:45.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.03:37:45.04#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:45.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:45.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:45.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:45.16#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:37:45.16#ibcon#first serial, iclass 4, count 0 2006.201.03:37:45.16#ibcon#enter sib2, iclass 4, count 0 2006.201.03:37:45.16#ibcon#flushed, iclass 4, count 0 2006.201.03:37:45.16#ibcon#about to write, iclass 4, count 0 2006.201.03:37:45.16#ibcon#wrote, iclass 4, count 0 2006.201.03:37:45.16#ibcon#about to read 3, iclass 4, count 0 2006.201.03:37:45.18#ibcon#read 3, iclass 4, count 0 2006.201.03:37:45.18#ibcon#about to read 4, iclass 4, count 0 2006.201.03:37:45.18#ibcon#read 4, iclass 4, count 0 2006.201.03:37:45.18#ibcon#about to read 5, iclass 4, count 0 2006.201.03:37:45.18#ibcon#read 5, iclass 4, count 0 2006.201.03:37:45.18#ibcon#about to read 6, iclass 4, count 0 2006.201.03:37:45.18#ibcon#read 6, iclass 4, count 0 2006.201.03:37:45.18#ibcon#end of sib2, iclass 4, count 0 2006.201.03:37:45.18#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:37:45.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:37:45.18#ibcon#[25=USB\r\n] 2006.201.03:37:45.18#ibcon#*before write, iclass 4, count 0 2006.201.03:37:45.18#ibcon#enter sib2, iclass 4, count 0 2006.201.03:37:45.18#ibcon#flushed, iclass 4, count 0 2006.201.03:37:45.18#ibcon#about to write, iclass 4, count 0 2006.201.03:37:45.18#ibcon#wrote, iclass 4, count 0 2006.201.03:37:45.18#ibcon#about to read 3, iclass 4, count 0 2006.201.03:37:45.21#ibcon#read 3, iclass 4, count 0 2006.201.03:37:45.21#ibcon#about to read 4, iclass 4, count 0 2006.201.03:37:45.21#ibcon#read 4, iclass 4, count 0 2006.201.03:37:45.21#ibcon#about to read 5, iclass 4, count 0 2006.201.03:37:45.21#ibcon#read 5, iclass 4, count 0 2006.201.03:37:45.21#ibcon#about to read 6, iclass 4, count 0 2006.201.03:37:45.21#ibcon#read 6, iclass 4, count 0 2006.201.03:37:45.21#ibcon#end of sib2, iclass 4, count 0 2006.201.03:37:45.21#ibcon#*after write, iclass 4, count 0 2006.201.03:37:45.21#ibcon#*before return 0, iclass 4, count 0 2006.201.03:37:45.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:45.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:45.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:37:45.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:37:45.21$vck44/valo=2,534.99 2006.201.03:37:45.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.03:37:45.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.03:37:45.21#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:45.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:45.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:45.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:45.21#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:37:45.21#ibcon#first serial, iclass 6, count 0 2006.201.03:37:45.21#ibcon#enter sib2, iclass 6, count 0 2006.201.03:37:45.21#ibcon#flushed, iclass 6, count 0 2006.201.03:37:45.21#ibcon#about to write, iclass 6, count 0 2006.201.03:37:45.21#ibcon#wrote, iclass 6, count 0 2006.201.03:37:45.21#ibcon#about to read 3, iclass 6, count 0 2006.201.03:37:45.23#ibcon#read 3, iclass 6, count 0 2006.201.03:37:45.23#ibcon#about to read 4, iclass 6, count 0 2006.201.03:37:45.23#ibcon#read 4, iclass 6, count 0 2006.201.03:37:45.23#ibcon#about to read 5, iclass 6, count 0 2006.201.03:37:45.23#ibcon#read 5, iclass 6, count 0 2006.201.03:37:45.23#ibcon#about to read 6, iclass 6, count 0 2006.201.03:37:45.23#ibcon#read 6, iclass 6, count 0 2006.201.03:37:45.23#ibcon#end of sib2, iclass 6, count 0 2006.201.03:37:45.23#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:37:45.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:37:45.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:37:45.23#ibcon#*before write, iclass 6, count 0 2006.201.03:37:45.23#ibcon#enter sib2, iclass 6, count 0 2006.201.03:37:45.23#ibcon#flushed, iclass 6, count 0 2006.201.03:37:45.23#ibcon#about to write, iclass 6, count 0 2006.201.03:37:45.23#ibcon#wrote, iclass 6, count 0 2006.201.03:37:45.23#ibcon#about to read 3, iclass 6, count 0 2006.201.03:37:45.27#ibcon#read 3, iclass 6, count 0 2006.201.03:37:45.27#ibcon#about to read 4, iclass 6, count 0 2006.201.03:37:45.27#ibcon#read 4, iclass 6, count 0 2006.201.03:37:45.27#ibcon#about to read 5, iclass 6, count 0 2006.201.03:37:45.27#ibcon#read 5, iclass 6, count 0 2006.201.03:37:45.27#ibcon#about to read 6, iclass 6, count 0 2006.201.03:37:45.27#ibcon#read 6, iclass 6, count 0 2006.201.03:37:45.27#ibcon#end of sib2, iclass 6, count 0 2006.201.03:37:45.27#ibcon#*after write, iclass 6, count 0 2006.201.03:37:45.27#ibcon#*before return 0, iclass 6, count 0 2006.201.03:37:45.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:45.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:45.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:37:45.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:37:45.27$vck44/va=2,7 2006.201.03:37:45.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.03:37:45.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.03:37:45.27#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:45.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:45.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:45.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:45.33#ibcon#enter wrdev, iclass 10, count 2 2006.201.03:37:45.33#ibcon#first serial, iclass 10, count 2 2006.201.03:37:45.33#ibcon#enter sib2, iclass 10, count 2 2006.201.03:37:45.33#ibcon#flushed, iclass 10, count 2 2006.201.03:37:45.33#ibcon#about to write, iclass 10, count 2 2006.201.03:37:45.33#ibcon#wrote, iclass 10, count 2 2006.201.03:37:45.33#ibcon#about to read 3, iclass 10, count 2 2006.201.03:37:45.35#ibcon#read 3, iclass 10, count 2 2006.201.03:37:45.35#ibcon#about to read 4, iclass 10, count 2 2006.201.03:37:45.35#ibcon#read 4, iclass 10, count 2 2006.201.03:37:45.35#ibcon#about to read 5, iclass 10, count 2 2006.201.03:37:45.35#ibcon#read 5, iclass 10, count 2 2006.201.03:37:45.35#ibcon#about to read 6, iclass 10, count 2 2006.201.03:37:45.35#ibcon#read 6, iclass 10, count 2 2006.201.03:37:45.35#ibcon#end of sib2, iclass 10, count 2 2006.201.03:37:45.35#ibcon#*mode == 0, iclass 10, count 2 2006.201.03:37:45.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.03:37:45.35#ibcon#[25=AT02-07\r\n] 2006.201.03:37:45.35#ibcon#*before write, iclass 10, count 2 2006.201.03:37:45.35#ibcon#enter sib2, iclass 10, count 2 2006.201.03:37:45.35#ibcon#flushed, iclass 10, count 2 2006.201.03:37:45.35#ibcon#about to write, iclass 10, count 2 2006.201.03:37:45.35#ibcon#wrote, iclass 10, count 2 2006.201.03:37:45.35#ibcon#about to read 3, iclass 10, count 2 2006.201.03:37:45.38#ibcon#read 3, iclass 10, count 2 2006.201.03:37:45.38#ibcon#about to read 4, iclass 10, count 2 2006.201.03:37:45.38#ibcon#read 4, iclass 10, count 2 2006.201.03:37:45.38#ibcon#about to read 5, iclass 10, count 2 2006.201.03:37:45.38#ibcon#read 5, iclass 10, count 2 2006.201.03:37:45.38#ibcon#about to read 6, iclass 10, count 2 2006.201.03:37:45.38#ibcon#read 6, iclass 10, count 2 2006.201.03:37:45.38#ibcon#end of sib2, iclass 10, count 2 2006.201.03:37:45.38#ibcon#*after write, iclass 10, count 2 2006.201.03:37:45.38#ibcon#*before return 0, iclass 10, count 2 2006.201.03:37:45.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:45.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:45.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.03:37:45.38#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:45.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:45.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:45.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:45.50#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:37:45.50#ibcon#first serial, iclass 10, count 0 2006.201.03:37:45.50#ibcon#enter sib2, iclass 10, count 0 2006.201.03:37:45.50#ibcon#flushed, iclass 10, count 0 2006.201.03:37:45.50#ibcon#about to write, iclass 10, count 0 2006.201.03:37:45.50#ibcon#wrote, iclass 10, count 0 2006.201.03:37:45.50#ibcon#about to read 3, iclass 10, count 0 2006.201.03:37:45.52#ibcon#read 3, iclass 10, count 0 2006.201.03:37:45.52#ibcon#about to read 4, iclass 10, count 0 2006.201.03:37:45.52#ibcon#read 4, iclass 10, count 0 2006.201.03:37:45.52#ibcon#about to read 5, iclass 10, count 0 2006.201.03:37:45.52#ibcon#read 5, iclass 10, count 0 2006.201.03:37:45.52#ibcon#about to read 6, iclass 10, count 0 2006.201.03:37:45.52#ibcon#read 6, iclass 10, count 0 2006.201.03:37:45.52#ibcon#end of sib2, iclass 10, count 0 2006.201.03:37:45.52#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:37:45.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:37:45.52#ibcon#[25=USB\r\n] 2006.201.03:37:45.52#ibcon#*before write, iclass 10, count 0 2006.201.03:37:45.52#ibcon#enter sib2, iclass 10, count 0 2006.201.03:37:45.52#ibcon#flushed, iclass 10, count 0 2006.201.03:37:45.52#ibcon#about to write, iclass 10, count 0 2006.201.03:37:45.52#ibcon#wrote, iclass 10, count 0 2006.201.03:37:45.52#ibcon#about to read 3, iclass 10, count 0 2006.201.03:37:45.55#ibcon#read 3, iclass 10, count 0 2006.201.03:37:45.55#ibcon#about to read 4, iclass 10, count 0 2006.201.03:37:45.55#ibcon#read 4, iclass 10, count 0 2006.201.03:37:45.55#ibcon#about to read 5, iclass 10, count 0 2006.201.03:37:45.55#ibcon#read 5, iclass 10, count 0 2006.201.03:37:45.55#ibcon#about to read 6, iclass 10, count 0 2006.201.03:37:45.55#ibcon#read 6, iclass 10, count 0 2006.201.03:37:45.55#ibcon#end of sib2, iclass 10, count 0 2006.201.03:37:45.55#ibcon#*after write, iclass 10, count 0 2006.201.03:37:45.55#ibcon#*before return 0, iclass 10, count 0 2006.201.03:37:45.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:45.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:45.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:37:45.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:37:45.55$vck44/valo=3,564.99 2006.201.03:37:45.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.03:37:45.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.03:37:45.55#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:45.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:45.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:45.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:45.55#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:37:45.55#ibcon#first serial, iclass 12, count 0 2006.201.03:37:45.55#ibcon#enter sib2, iclass 12, count 0 2006.201.03:37:45.55#ibcon#flushed, iclass 12, count 0 2006.201.03:37:45.55#ibcon#about to write, iclass 12, count 0 2006.201.03:37:45.55#ibcon#wrote, iclass 12, count 0 2006.201.03:37:45.55#ibcon#about to read 3, iclass 12, count 0 2006.201.03:37:45.57#ibcon#read 3, iclass 12, count 0 2006.201.03:37:45.57#ibcon#about to read 4, iclass 12, count 0 2006.201.03:37:45.57#ibcon#read 4, iclass 12, count 0 2006.201.03:37:45.57#ibcon#about to read 5, iclass 12, count 0 2006.201.03:37:45.57#ibcon#read 5, iclass 12, count 0 2006.201.03:37:45.57#ibcon#about to read 6, iclass 12, count 0 2006.201.03:37:45.57#ibcon#read 6, iclass 12, count 0 2006.201.03:37:45.57#ibcon#end of sib2, iclass 12, count 0 2006.201.03:37:45.57#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:37:45.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:37:45.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:37:45.57#ibcon#*before write, iclass 12, count 0 2006.201.03:37:45.57#ibcon#enter sib2, iclass 12, count 0 2006.201.03:37:45.57#ibcon#flushed, iclass 12, count 0 2006.201.03:37:45.57#ibcon#about to write, iclass 12, count 0 2006.201.03:37:45.57#ibcon#wrote, iclass 12, count 0 2006.201.03:37:45.57#ibcon#about to read 3, iclass 12, count 0 2006.201.03:37:45.62#ibcon#read 3, iclass 12, count 0 2006.201.03:37:45.62#ibcon#about to read 4, iclass 12, count 0 2006.201.03:37:45.62#ibcon#read 4, iclass 12, count 0 2006.201.03:37:45.62#ibcon#about to read 5, iclass 12, count 0 2006.201.03:37:45.62#ibcon#read 5, iclass 12, count 0 2006.201.03:37:45.62#ibcon#about to read 6, iclass 12, count 0 2006.201.03:37:45.62#ibcon#read 6, iclass 12, count 0 2006.201.03:37:45.62#ibcon#end of sib2, iclass 12, count 0 2006.201.03:37:45.62#ibcon#*after write, iclass 12, count 0 2006.201.03:37:45.62#ibcon#*before return 0, iclass 12, count 0 2006.201.03:37:45.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:45.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:45.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:37:45.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:37:45.62$vck44/va=3,8 2006.201.03:37:45.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.03:37:45.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.03:37:45.62#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:45.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:45.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:45.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:45.67#ibcon#enter wrdev, iclass 14, count 2 2006.201.03:37:45.67#ibcon#first serial, iclass 14, count 2 2006.201.03:37:45.67#ibcon#enter sib2, iclass 14, count 2 2006.201.03:37:45.67#ibcon#flushed, iclass 14, count 2 2006.201.03:37:45.67#ibcon#about to write, iclass 14, count 2 2006.201.03:37:45.67#ibcon#wrote, iclass 14, count 2 2006.201.03:37:45.67#ibcon#about to read 3, iclass 14, count 2 2006.201.03:37:45.69#ibcon#read 3, iclass 14, count 2 2006.201.03:37:45.69#ibcon#about to read 4, iclass 14, count 2 2006.201.03:37:45.69#ibcon#read 4, iclass 14, count 2 2006.201.03:37:45.69#ibcon#about to read 5, iclass 14, count 2 2006.201.03:37:45.69#ibcon#read 5, iclass 14, count 2 2006.201.03:37:45.69#ibcon#about to read 6, iclass 14, count 2 2006.201.03:37:45.69#ibcon#read 6, iclass 14, count 2 2006.201.03:37:45.69#ibcon#end of sib2, iclass 14, count 2 2006.201.03:37:45.69#ibcon#*mode == 0, iclass 14, count 2 2006.201.03:37:45.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.03:37:45.69#ibcon#[25=AT03-08\r\n] 2006.201.03:37:45.69#ibcon#*before write, iclass 14, count 2 2006.201.03:37:45.69#ibcon#enter sib2, iclass 14, count 2 2006.201.03:37:45.69#ibcon#flushed, iclass 14, count 2 2006.201.03:37:45.69#ibcon#about to write, iclass 14, count 2 2006.201.03:37:45.69#ibcon#wrote, iclass 14, count 2 2006.201.03:37:45.69#ibcon#about to read 3, iclass 14, count 2 2006.201.03:37:45.72#ibcon#read 3, iclass 14, count 2 2006.201.03:37:45.72#ibcon#about to read 4, iclass 14, count 2 2006.201.03:37:45.72#ibcon#read 4, iclass 14, count 2 2006.201.03:37:45.72#ibcon#about to read 5, iclass 14, count 2 2006.201.03:37:45.72#ibcon#read 5, iclass 14, count 2 2006.201.03:37:45.72#ibcon#about to read 6, iclass 14, count 2 2006.201.03:37:45.72#ibcon#read 6, iclass 14, count 2 2006.201.03:37:45.72#ibcon#end of sib2, iclass 14, count 2 2006.201.03:37:45.72#ibcon#*after write, iclass 14, count 2 2006.201.03:37:45.72#ibcon#*before return 0, iclass 14, count 2 2006.201.03:37:45.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:45.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:45.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.03:37:45.72#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:45.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:45.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:45.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:45.84#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:37:45.84#ibcon#first serial, iclass 14, count 0 2006.201.03:37:45.84#ibcon#enter sib2, iclass 14, count 0 2006.201.03:37:45.84#ibcon#flushed, iclass 14, count 0 2006.201.03:37:45.84#ibcon#about to write, iclass 14, count 0 2006.201.03:37:45.84#ibcon#wrote, iclass 14, count 0 2006.201.03:37:45.84#ibcon#about to read 3, iclass 14, count 0 2006.201.03:37:45.86#ibcon#read 3, iclass 14, count 0 2006.201.03:37:45.86#ibcon#about to read 4, iclass 14, count 0 2006.201.03:37:45.86#ibcon#read 4, iclass 14, count 0 2006.201.03:37:45.86#ibcon#about to read 5, iclass 14, count 0 2006.201.03:37:45.86#ibcon#read 5, iclass 14, count 0 2006.201.03:37:45.86#ibcon#about to read 6, iclass 14, count 0 2006.201.03:37:45.86#ibcon#read 6, iclass 14, count 0 2006.201.03:37:45.86#ibcon#end of sib2, iclass 14, count 0 2006.201.03:37:45.86#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:37:45.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:37:45.86#ibcon#[25=USB\r\n] 2006.201.03:37:45.86#ibcon#*before write, iclass 14, count 0 2006.201.03:37:45.86#ibcon#enter sib2, iclass 14, count 0 2006.201.03:37:45.86#ibcon#flushed, iclass 14, count 0 2006.201.03:37:45.86#ibcon#about to write, iclass 14, count 0 2006.201.03:37:45.86#ibcon#wrote, iclass 14, count 0 2006.201.03:37:45.86#ibcon#about to read 3, iclass 14, count 0 2006.201.03:37:45.89#ibcon#read 3, iclass 14, count 0 2006.201.03:37:45.89#ibcon#about to read 4, iclass 14, count 0 2006.201.03:37:45.89#ibcon#read 4, iclass 14, count 0 2006.201.03:37:45.89#ibcon#about to read 5, iclass 14, count 0 2006.201.03:37:45.89#ibcon#read 5, iclass 14, count 0 2006.201.03:37:45.89#ibcon#about to read 6, iclass 14, count 0 2006.201.03:37:45.89#ibcon#read 6, iclass 14, count 0 2006.201.03:37:45.89#ibcon#end of sib2, iclass 14, count 0 2006.201.03:37:45.89#ibcon#*after write, iclass 14, count 0 2006.201.03:37:45.89#ibcon#*before return 0, iclass 14, count 0 2006.201.03:37:45.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:45.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:45.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:37:45.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:37:45.89$vck44/valo=4,624.99 2006.201.03:37:45.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.03:37:45.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.03:37:45.89#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:45.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:45.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:45.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:45.89#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:37:45.89#ibcon#first serial, iclass 16, count 0 2006.201.03:37:45.89#ibcon#enter sib2, iclass 16, count 0 2006.201.03:37:45.89#ibcon#flushed, iclass 16, count 0 2006.201.03:37:45.89#ibcon#about to write, iclass 16, count 0 2006.201.03:37:45.89#ibcon#wrote, iclass 16, count 0 2006.201.03:37:45.89#ibcon#about to read 3, iclass 16, count 0 2006.201.03:37:45.91#ibcon#read 3, iclass 16, count 0 2006.201.03:37:45.91#ibcon#about to read 4, iclass 16, count 0 2006.201.03:37:45.91#ibcon#read 4, iclass 16, count 0 2006.201.03:37:45.91#ibcon#about to read 5, iclass 16, count 0 2006.201.03:37:45.91#ibcon#read 5, iclass 16, count 0 2006.201.03:37:45.91#ibcon#about to read 6, iclass 16, count 0 2006.201.03:37:45.91#ibcon#read 6, iclass 16, count 0 2006.201.03:37:45.91#ibcon#end of sib2, iclass 16, count 0 2006.201.03:37:45.91#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:37:45.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:37:45.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:37:45.91#ibcon#*before write, iclass 16, count 0 2006.201.03:37:45.91#ibcon#enter sib2, iclass 16, count 0 2006.201.03:37:45.91#ibcon#flushed, iclass 16, count 0 2006.201.03:37:45.91#ibcon#about to write, iclass 16, count 0 2006.201.03:37:45.91#ibcon#wrote, iclass 16, count 0 2006.201.03:37:45.91#ibcon#about to read 3, iclass 16, count 0 2006.201.03:37:45.96#ibcon#read 3, iclass 16, count 0 2006.201.03:37:45.96#ibcon#about to read 4, iclass 16, count 0 2006.201.03:37:45.96#ibcon#read 4, iclass 16, count 0 2006.201.03:37:45.96#ibcon#about to read 5, iclass 16, count 0 2006.201.03:37:45.96#ibcon#read 5, iclass 16, count 0 2006.201.03:37:45.96#ibcon#about to read 6, iclass 16, count 0 2006.201.03:37:45.96#ibcon#read 6, iclass 16, count 0 2006.201.03:37:45.96#ibcon#end of sib2, iclass 16, count 0 2006.201.03:37:45.96#ibcon#*after write, iclass 16, count 0 2006.201.03:37:45.96#ibcon#*before return 0, iclass 16, count 0 2006.201.03:37:45.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:45.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:45.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:37:45.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:37:45.96$vck44/va=4,7 2006.201.03:37:45.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.03:37:45.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.03:37:45.96#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:45.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:46.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:46.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:46.01#ibcon#enter wrdev, iclass 18, count 2 2006.201.03:37:46.01#ibcon#first serial, iclass 18, count 2 2006.201.03:37:46.01#ibcon#enter sib2, iclass 18, count 2 2006.201.03:37:46.01#ibcon#flushed, iclass 18, count 2 2006.201.03:37:46.01#ibcon#about to write, iclass 18, count 2 2006.201.03:37:46.01#ibcon#wrote, iclass 18, count 2 2006.201.03:37:46.01#ibcon#about to read 3, iclass 18, count 2 2006.201.03:37:46.03#ibcon#read 3, iclass 18, count 2 2006.201.03:37:46.03#ibcon#about to read 4, iclass 18, count 2 2006.201.03:37:46.03#ibcon#read 4, iclass 18, count 2 2006.201.03:37:46.03#ibcon#about to read 5, iclass 18, count 2 2006.201.03:37:46.03#ibcon#read 5, iclass 18, count 2 2006.201.03:37:46.03#ibcon#about to read 6, iclass 18, count 2 2006.201.03:37:46.03#ibcon#read 6, iclass 18, count 2 2006.201.03:37:46.03#ibcon#end of sib2, iclass 18, count 2 2006.201.03:37:46.03#ibcon#*mode == 0, iclass 18, count 2 2006.201.03:37:46.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.03:37:46.03#ibcon#[25=AT04-07\r\n] 2006.201.03:37:46.03#ibcon#*before write, iclass 18, count 2 2006.201.03:37:46.03#ibcon#enter sib2, iclass 18, count 2 2006.201.03:37:46.03#ibcon#flushed, iclass 18, count 2 2006.201.03:37:46.03#ibcon#about to write, iclass 18, count 2 2006.201.03:37:46.03#ibcon#wrote, iclass 18, count 2 2006.201.03:37:46.03#ibcon#about to read 3, iclass 18, count 2 2006.201.03:37:46.06#ibcon#read 3, iclass 18, count 2 2006.201.03:37:46.06#ibcon#about to read 4, iclass 18, count 2 2006.201.03:37:46.06#ibcon#read 4, iclass 18, count 2 2006.201.03:37:46.06#ibcon#about to read 5, iclass 18, count 2 2006.201.03:37:46.06#ibcon#read 5, iclass 18, count 2 2006.201.03:37:46.06#ibcon#about to read 6, iclass 18, count 2 2006.201.03:37:46.06#ibcon#read 6, iclass 18, count 2 2006.201.03:37:46.06#ibcon#end of sib2, iclass 18, count 2 2006.201.03:37:46.06#ibcon#*after write, iclass 18, count 2 2006.201.03:37:46.06#ibcon#*before return 0, iclass 18, count 2 2006.201.03:37:46.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:46.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:46.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.03:37:46.06#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:46.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:46.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:46.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:46.18#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:37:46.18#ibcon#first serial, iclass 18, count 0 2006.201.03:37:46.18#ibcon#enter sib2, iclass 18, count 0 2006.201.03:37:46.18#ibcon#flushed, iclass 18, count 0 2006.201.03:37:46.18#ibcon#about to write, iclass 18, count 0 2006.201.03:37:46.18#ibcon#wrote, iclass 18, count 0 2006.201.03:37:46.18#ibcon#about to read 3, iclass 18, count 0 2006.201.03:37:46.20#ibcon#read 3, iclass 18, count 0 2006.201.03:37:46.20#ibcon#about to read 4, iclass 18, count 0 2006.201.03:37:46.20#ibcon#read 4, iclass 18, count 0 2006.201.03:37:46.20#ibcon#about to read 5, iclass 18, count 0 2006.201.03:37:46.20#ibcon#read 5, iclass 18, count 0 2006.201.03:37:46.20#ibcon#about to read 6, iclass 18, count 0 2006.201.03:37:46.20#ibcon#read 6, iclass 18, count 0 2006.201.03:37:46.20#ibcon#end of sib2, iclass 18, count 0 2006.201.03:37:46.20#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:37:46.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:37:46.20#ibcon#[25=USB\r\n] 2006.201.03:37:46.20#ibcon#*before write, iclass 18, count 0 2006.201.03:37:46.20#ibcon#enter sib2, iclass 18, count 0 2006.201.03:37:46.20#ibcon#flushed, iclass 18, count 0 2006.201.03:37:46.20#ibcon#about to write, iclass 18, count 0 2006.201.03:37:46.20#ibcon#wrote, iclass 18, count 0 2006.201.03:37:46.20#ibcon#about to read 3, iclass 18, count 0 2006.201.03:37:46.23#ibcon#read 3, iclass 18, count 0 2006.201.03:37:46.23#ibcon#about to read 4, iclass 18, count 0 2006.201.03:37:46.23#ibcon#read 4, iclass 18, count 0 2006.201.03:37:46.23#ibcon#about to read 5, iclass 18, count 0 2006.201.03:37:46.23#ibcon#read 5, iclass 18, count 0 2006.201.03:37:46.23#ibcon#about to read 6, iclass 18, count 0 2006.201.03:37:46.23#ibcon#read 6, iclass 18, count 0 2006.201.03:37:46.23#ibcon#end of sib2, iclass 18, count 0 2006.201.03:37:46.23#ibcon#*after write, iclass 18, count 0 2006.201.03:37:46.23#ibcon#*before return 0, iclass 18, count 0 2006.201.03:37:46.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:46.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:46.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:37:46.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:37:46.23$vck44/valo=5,734.99 2006.201.03:37:46.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.03:37:46.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.03:37:46.23#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:46.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:46.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:46.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:46.23#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:37:46.23#ibcon#first serial, iclass 20, count 0 2006.201.03:37:46.23#ibcon#enter sib2, iclass 20, count 0 2006.201.03:37:46.23#ibcon#flushed, iclass 20, count 0 2006.201.03:37:46.23#ibcon#about to write, iclass 20, count 0 2006.201.03:37:46.23#ibcon#wrote, iclass 20, count 0 2006.201.03:37:46.23#ibcon#about to read 3, iclass 20, count 0 2006.201.03:37:46.25#ibcon#read 3, iclass 20, count 0 2006.201.03:37:46.25#ibcon#about to read 4, iclass 20, count 0 2006.201.03:37:46.25#ibcon#read 4, iclass 20, count 0 2006.201.03:37:46.25#ibcon#about to read 5, iclass 20, count 0 2006.201.03:37:46.25#ibcon#read 5, iclass 20, count 0 2006.201.03:37:46.25#ibcon#about to read 6, iclass 20, count 0 2006.201.03:37:46.25#ibcon#read 6, iclass 20, count 0 2006.201.03:37:46.25#ibcon#end of sib2, iclass 20, count 0 2006.201.03:37:46.25#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:37:46.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:37:46.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:37:46.25#ibcon#*before write, iclass 20, count 0 2006.201.03:37:46.25#ibcon#enter sib2, iclass 20, count 0 2006.201.03:37:46.25#ibcon#flushed, iclass 20, count 0 2006.201.03:37:46.25#ibcon#about to write, iclass 20, count 0 2006.201.03:37:46.25#ibcon#wrote, iclass 20, count 0 2006.201.03:37:46.25#ibcon#about to read 3, iclass 20, count 0 2006.201.03:37:46.29#ibcon#read 3, iclass 20, count 0 2006.201.03:37:46.29#ibcon#about to read 4, iclass 20, count 0 2006.201.03:37:46.29#ibcon#read 4, iclass 20, count 0 2006.201.03:37:46.29#ibcon#about to read 5, iclass 20, count 0 2006.201.03:37:46.29#ibcon#read 5, iclass 20, count 0 2006.201.03:37:46.29#ibcon#about to read 6, iclass 20, count 0 2006.201.03:37:46.29#ibcon#read 6, iclass 20, count 0 2006.201.03:37:46.29#ibcon#end of sib2, iclass 20, count 0 2006.201.03:37:46.29#ibcon#*after write, iclass 20, count 0 2006.201.03:37:46.29#ibcon#*before return 0, iclass 20, count 0 2006.201.03:37:46.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:46.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:46.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:37:46.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:37:46.29$vck44/va=5,4 2006.201.03:37:46.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.03:37:46.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.03:37:46.29#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:46.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:46.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:46.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:46.35#ibcon#enter wrdev, iclass 22, count 2 2006.201.03:37:46.35#ibcon#first serial, iclass 22, count 2 2006.201.03:37:46.35#ibcon#enter sib2, iclass 22, count 2 2006.201.03:37:46.35#ibcon#flushed, iclass 22, count 2 2006.201.03:37:46.35#ibcon#about to write, iclass 22, count 2 2006.201.03:37:46.35#ibcon#wrote, iclass 22, count 2 2006.201.03:37:46.35#ibcon#about to read 3, iclass 22, count 2 2006.201.03:37:46.37#ibcon#read 3, iclass 22, count 2 2006.201.03:37:46.37#ibcon#about to read 4, iclass 22, count 2 2006.201.03:37:46.37#ibcon#read 4, iclass 22, count 2 2006.201.03:37:46.37#ibcon#about to read 5, iclass 22, count 2 2006.201.03:37:46.37#ibcon#read 5, iclass 22, count 2 2006.201.03:37:46.37#ibcon#about to read 6, iclass 22, count 2 2006.201.03:37:46.37#ibcon#read 6, iclass 22, count 2 2006.201.03:37:46.37#ibcon#end of sib2, iclass 22, count 2 2006.201.03:37:46.37#ibcon#*mode == 0, iclass 22, count 2 2006.201.03:37:46.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.03:37:46.37#ibcon#[25=AT05-04\r\n] 2006.201.03:37:46.37#ibcon#*before write, iclass 22, count 2 2006.201.03:37:46.37#ibcon#enter sib2, iclass 22, count 2 2006.201.03:37:46.37#ibcon#flushed, iclass 22, count 2 2006.201.03:37:46.37#ibcon#about to write, iclass 22, count 2 2006.201.03:37:46.37#ibcon#wrote, iclass 22, count 2 2006.201.03:37:46.37#ibcon#about to read 3, iclass 22, count 2 2006.201.03:37:46.40#ibcon#read 3, iclass 22, count 2 2006.201.03:37:46.40#ibcon#about to read 4, iclass 22, count 2 2006.201.03:37:46.40#ibcon#read 4, iclass 22, count 2 2006.201.03:37:46.40#ibcon#about to read 5, iclass 22, count 2 2006.201.03:37:46.40#ibcon#read 5, iclass 22, count 2 2006.201.03:37:46.40#ibcon#about to read 6, iclass 22, count 2 2006.201.03:37:46.40#ibcon#read 6, iclass 22, count 2 2006.201.03:37:46.40#ibcon#end of sib2, iclass 22, count 2 2006.201.03:37:46.40#ibcon#*after write, iclass 22, count 2 2006.201.03:37:46.40#ibcon#*before return 0, iclass 22, count 2 2006.201.03:37:46.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:46.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:46.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.03:37:46.40#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:46.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:46.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:46.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:46.52#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:37:46.52#ibcon#first serial, iclass 22, count 0 2006.201.03:37:46.52#ibcon#enter sib2, iclass 22, count 0 2006.201.03:37:46.52#ibcon#flushed, iclass 22, count 0 2006.201.03:37:46.52#ibcon#about to write, iclass 22, count 0 2006.201.03:37:46.52#ibcon#wrote, iclass 22, count 0 2006.201.03:37:46.52#ibcon#about to read 3, iclass 22, count 0 2006.201.03:37:46.54#ibcon#read 3, iclass 22, count 0 2006.201.03:37:46.54#ibcon#about to read 4, iclass 22, count 0 2006.201.03:37:46.54#ibcon#read 4, iclass 22, count 0 2006.201.03:37:46.54#ibcon#about to read 5, iclass 22, count 0 2006.201.03:37:46.54#ibcon#read 5, iclass 22, count 0 2006.201.03:37:46.54#ibcon#about to read 6, iclass 22, count 0 2006.201.03:37:46.54#ibcon#read 6, iclass 22, count 0 2006.201.03:37:46.54#ibcon#end of sib2, iclass 22, count 0 2006.201.03:37:46.54#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:37:46.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:37:46.54#ibcon#[25=USB\r\n] 2006.201.03:37:46.54#ibcon#*before write, iclass 22, count 0 2006.201.03:37:46.54#ibcon#enter sib2, iclass 22, count 0 2006.201.03:37:46.54#ibcon#flushed, iclass 22, count 0 2006.201.03:37:46.54#ibcon#about to write, iclass 22, count 0 2006.201.03:37:46.54#ibcon#wrote, iclass 22, count 0 2006.201.03:37:46.54#ibcon#about to read 3, iclass 22, count 0 2006.201.03:37:46.57#ibcon#read 3, iclass 22, count 0 2006.201.03:37:46.57#ibcon#about to read 4, iclass 22, count 0 2006.201.03:37:46.57#ibcon#read 4, iclass 22, count 0 2006.201.03:37:46.57#ibcon#about to read 5, iclass 22, count 0 2006.201.03:37:46.57#ibcon#read 5, iclass 22, count 0 2006.201.03:37:46.57#ibcon#about to read 6, iclass 22, count 0 2006.201.03:37:46.57#ibcon#read 6, iclass 22, count 0 2006.201.03:37:46.57#ibcon#end of sib2, iclass 22, count 0 2006.201.03:37:46.57#ibcon#*after write, iclass 22, count 0 2006.201.03:37:46.57#ibcon#*before return 0, iclass 22, count 0 2006.201.03:37:46.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:46.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:46.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:37:46.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:37:46.57$vck44/valo=6,814.99 2006.201.03:37:46.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.03:37:46.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.03:37:46.57#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:46.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:37:46.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:37:46.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:37:46.57#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:37:46.57#ibcon#first serial, iclass 24, count 0 2006.201.03:37:46.57#ibcon#enter sib2, iclass 24, count 0 2006.201.03:37:46.57#ibcon#flushed, iclass 24, count 0 2006.201.03:37:46.57#ibcon#about to write, iclass 24, count 0 2006.201.03:37:46.57#ibcon#wrote, iclass 24, count 0 2006.201.03:37:46.57#ibcon#about to read 3, iclass 24, count 0 2006.201.03:37:46.59#ibcon#read 3, iclass 24, count 0 2006.201.03:37:46.59#ibcon#about to read 4, iclass 24, count 0 2006.201.03:37:46.59#ibcon#read 4, iclass 24, count 0 2006.201.03:37:46.59#ibcon#about to read 5, iclass 24, count 0 2006.201.03:37:46.59#ibcon#read 5, iclass 24, count 0 2006.201.03:37:46.59#ibcon#about to read 6, iclass 24, count 0 2006.201.03:37:46.59#ibcon#read 6, iclass 24, count 0 2006.201.03:37:46.59#ibcon#end of sib2, iclass 24, count 0 2006.201.03:37:46.59#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:37:46.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:37:46.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:37:46.59#ibcon#*before write, iclass 24, count 0 2006.201.03:37:46.59#ibcon#enter sib2, iclass 24, count 0 2006.201.03:37:46.59#ibcon#flushed, iclass 24, count 0 2006.201.03:37:46.59#ibcon#about to write, iclass 24, count 0 2006.201.03:37:46.59#ibcon#wrote, iclass 24, count 0 2006.201.03:37:46.59#ibcon#about to read 3, iclass 24, count 0 2006.201.03:37:46.63#ibcon#read 3, iclass 24, count 0 2006.201.03:37:46.63#ibcon#about to read 4, iclass 24, count 0 2006.201.03:37:46.63#ibcon#read 4, iclass 24, count 0 2006.201.03:37:46.63#ibcon#about to read 5, iclass 24, count 0 2006.201.03:37:46.63#ibcon#read 5, iclass 24, count 0 2006.201.03:37:46.63#ibcon#about to read 6, iclass 24, count 0 2006.201.03:37:46.63#ibcon#read 6, iclass 24, count 0 2006.201.03:37:46.63#ibcon#end of sib2, iclass 24, count 0 2006.201.03:37:46.63#ibcon#*after write, iclass 24, count 0 2006.201.03:37:46.63#ibcon#*before return 0, iclass 24, count 0 2006.201.03:37:46.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:37:46.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:37:46.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:37:46.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:37:46.63$vck44/va=6,5 2006.201.03:37:46.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.03:37:46.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.03:37:46.63#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:46.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:37:46.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:37:46.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:37:46.69#ibcon#enter wrdev, iclass 26, count 2 2006.201.03:37:46.69#ibcon#first serial, iclass 26, count 2 2006.201.03:37:46.69#ibcon#enter sib2, iclass 26, count 2 2006.201.03:37:46.69#ibcon#flushed, iclass 26, count 2 2006.201.03:37:46.69#ibcon#about to write, iclass 26, count 2 2006.201.03:37:46.69#ibcon#wrote, iclass 26, count 2 2006.201.03:37:46.69#ibcon#about to read 3, iclass 26, count 2 2006.201.03:37:46.71#ibcon#read 3, iclass 26, count 2 2006.201.03:37:46.71#ibcon#about to read 4, iclass 26, count 2 2006.201.03:37:46.71#ibcon#read 4, iclass 26, count 2 2006.201.03:37:46.71#ibcon#about to read 5, iclass 26, count 2 2006.201.03:37:46.71#ibcon#read 5, iclass 26, count 2 2006.201.03:37:46.71#ibcon#about to read 6, iclass 26, count 2 2006.201.03:37:46.71#ibcon#read 6, iclass 26, count 2 2006.201.03:37:46.71#ibcon#end of sib2, iclass 26, count 2 2006.201.03:37:46.71#ibcon#*mode == 0, iclass 26, count 2 2006.201.03:37:46.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.03:37:46.71#ibcon#[25=AT06-05\r\n] 2006.201.03:37:46.71#ibcon#*before write, iclass 26, count 2 2006.201.03:37:46.71#ibcon#enter sib2, iclass 26, count 2 2006.201.03:37:46.71#ibcon#flushed, iclass 26, count 2 2006.201.03:37:46.71#ibcon#about to write, iclass 26, count 2 2006.201.03:37:46.71#ibcon#wrote, iclass 26, count 2 2006.201.03:37:46.71#ibcon#about to read 3, iclass 26, count 2 2006.201.03:37:46.74#ibcon#read 3, iclass 26, count 2 2006.201.03:37:46.74#ibcon#about to read 4, iclass 26, count 2 2006.201.03:37:46.74#ibcon#read 4, iclass 26, count 2 2006.201.03:37:46.74#ibcon#about to read 5, iclass 26, count 2 2006.201.03:37:46.74#ibcon#read 5, iclass 26, count 2 2006.201.03:37:46.74#ibcon#about to read 6, iclass 26, count 2 2006.201.03:37:46.74#ibcon#read 6, iclass 26, count 2 2006.201.03:37:46.74#ibcon#end of sib2, iclass 26, count 2 2006.201.03:37:46.74#ibcon#*after write, iclass 26, count 2 2006.201.03:37:46.74#ibcon#*before return 0, iclass 26, count 2 2006.201.03:37:46.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:37:46.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:37:46.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.03:37:46.74#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:46.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:37:46.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:37:46.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:37:46.86#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:37:46.86#ibcon#first serial, iclass 26, count 0 2006.201.03:37:46.86#ibcon#enter sib2, iclass 26, count 0 2006.201.03:37:46.86#ibcon#flushed, iclass 26, count 0 2006.201.03:37:46.86#ibcon#about to write, iclass 26, count 0 2006.201.03:37:46.86#ibcon#wrote, iclass 26, count 0 2006.201.03:37:46.86#ibcon#about to read 3, iclass 26, count 0 2006.201.03:37:46.88#ibcon#read 3, iclass 26, count 0 2006.201.03:37:46.88#ibcon#about to read 4, iclass 26, count 0 2006.201.03:37:46.88#ibcon#read 4, iclass 26, count 0 2006.201.03:37:46.88#ibcon#about to read 5, iclass 26, count 0 2006.201.03:37:46.88#ibcon#read 5, iclass 26, count 0 2006.201.03:37:46.88#ibcon#about to read 6, iclass 26, count 0 2006.201.03:37:46.88#ibcon#read 6, iclass 26, count 0 2006.201.03:37:46.88#ibcon#end of sib2, iclass 26, count 0 2006.201.03:37:46.88#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:37:46.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:37:46.88#ibcon#[25=USB\r\n] 2006.201.03:37:46.88#ibcon#*before write, iclass 26, count 0 2006.201.03:37:46.88#ibcon#enter sib2, iclass 26, count 0 2006.201.03:37:46.88#ibcon#flushed, iclass 26, count 0 2006.201.03:37:46.88#ibcon#about to write, iclass 26, count 0 2006.201.03:37:46.88#ibcon#wrote, iclass 26, count 0 2006.201.03:37:46.88#ibcon#about to read 3, iclass 26, count 0 2006.201.03:37:46.91#ibcon#read 3, iclass 26, count 0 2006.201.03:37:46.91#ibcon#about to read 4, iclass 26, count 0 2006.201.03:37:46.91#ibcon#read 4, iclass 26, count 0 2006.201.03:37:46.91#ibcon#about to read 5, iclass 26, count 0 2006.201.03:37:46.91#ibcon#read 5, iclass 26, count 0 2006.201.03:37:46.91#ibcon#about to read 6, iclass 26, count 0 2006.201.03:37:46.91#ibcon#read 6, iclass 26, count 0 2006.201.03:37:46.91#ibcon#end of sib2, iclass 26, count 0 2006.201.03:37:46.91#ibcon#*after write, iclass 26, count 0 2006.201.03:37:46.91#ibcon#*before return 0, iclass 26, count 0 2006.201.03:37:46.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:37:46.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:37:46.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:37:46.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:37:46.91$vck44/valo=7,864.99 2006.201.03:37:46.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.03:37:46.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.03:37:46.91#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:46.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:46.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:46.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:46.91#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:37:46.91#ibcon#first serial, iclass 28, count 0 2006.201.03:37:46.91#ibcon#enter sib2, iclass 28, count 0 2006.201.03:37:46.91#ibcon#flushed, iclass 28, count 0 2006.201.03:37:46.91#ibcon#about to write, iclass 28, count 0 2006.201.03:37:46.91#ibcon#wrote, iclass 28, count 0 2006.201.03:37:46.91#ibcon#about to read 3, iclass 28, count 0 2006.201.03:37:46.93#ibcon#read 3, iclass 28, count 0 2006.201.03:37:46.93#ibcon#about to read 4, iclass 28, count 0 2006.201.03:37:46.93#ibcon#read 4, iclass 28, count 0 2006.201.03:37:46.93#ibcon#about to read 5, iclass 28, count 0 2006.201.03:37:46.93#ibcon#read 5, iclass 28, count 0 2006.201.03:37:46.93#ibcon#about to read 6, iclass 28, count 0 2006.201.03:37:46.93#ibcon#read 6, iclass 28, count 0 2006.201.03:37:46.93#ibcon#end of sib2, iclass 28, count 0 2006.201.03:37:46.93#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:37:46.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:37:46.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:37:46.93#ibcon#*before write, iclass 28, count 0 2006.201.03:37:46.93#ibcon#enter sib2, iclass 28, count 0 2006.201.03:37:46.93#ibcon#flushed, iclass 28, count 0 2006.201.03:37:46.93#ibcon#about to write, iclass 28, count 0 2006.201.03:37:46.93#ibcon#wrote, iclass 28, count 0 2006.201.03:37:46.93#ibcon#about to read 3, iclass 28, count 0 2006.201.03:37:46.97#ibcon#read 3, iclass 28, count 0 2006.201.03:37:46.97#ibcon#about to read 4, iclass 28, count 0 2006.201.03:37:46.97#ibcon#read 4, iclass 28, count 0 2006.201.03:37:46.97#ibcon#about to read 5, iclass 28, count 0 2006.201.03:37:46.97#ibcon#read 5, iclass 28, count 0 2006.201.03:37:46.97#ibcon#about to read 6, iclass 28, count 0 2006.201.03:37:46.97#ibcon#read 6, iclass 28, count 0 2006.201.03:37:46.97#ibcon#end of sib2, iclass 28, count 0 2006.201.03:37:46.97#ibcon#*after write, iclass 28, count 0 2006.201.03:37:46.97#ibcon#*before return 0, iclass 28, count 0 2006.201.03:37:46.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:46.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:46.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:37:46.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:37:46.97$vck44/va=7,5 2006.201.03:37:46.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.03:37:46.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.03:37:46.97#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:46.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:47.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:47.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:47.03#ibcon#enter wrdev, iclass 30, count 2 2006.201.03:37:47.03#ibcon#first serial, iclass 30, count 2 2006.201.03:37:47.03#ibcon#enter sib2, iclass 30, count 2 2006.201.03:37:47.03#ibcon#flushed, iclass 30, count 2 2006.201.03:37:47.03#ibcon#about to write, iclass 30, count 2 2006.201.03:37:47.03#ibcon#wrote, iclass 30, count 2 2006.201.03:37:47.03#ibcon#about to read 3, iclass 30, count 2 2006.201.03:37:47.05#ibcon#read 3, iclass 30, count 2 2006.201.03:37:47.05#ibcon#about to read 4, iclass 30, count 2 2006.201.03:37:47.05#ibcon#read 4, iclass 30, count 2 2006.201.03:37:47.05#ibcon#about to read 5, iclass 30, count 2 2006.201.03:37:47.05#ibcon#read 5, iclass 30, count 2 2006.201.03:37:47.05#ibcon#about to read 6, iclass 30, count 2 2006.201.03:37:47.05#ibcon#read 6, iclass 30, count 2 2006.201.03:37:47.05#ibcon#end of sib2, iclass 30, count 2 2006.201.03:37:47.05#ibcon#*mode == 0, iclass 30, count 2 2006.201.03:37:47.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.03:37:47.05#ibcon#[25=AT07-05\r\n] 2006.201.03:37:47.05#ibcon#*before write, iclass 30, count 2 2006.201.03:37:47.05#ibcon#enter sib2, iclass 30, count 2 2006.201.03:37:47.05#ibcon#flushed, iclass 30, count 2 2006.201.03:37:47.05#ibcon#about to write, iclass 30, count 2 2006.201.03:37:47.05#ibcon#wrote, iclass 30, count 2 2006.201.03:37:47.05#ibcon#about to read 3, iclass 30, count 2 2006.201.03:37:47.08#ibcon#read 3, iclass 30, count 2 2006.201.03:37:47.08#ibcon#about to read 4, iclass 30, count 2 2006.201.03:37:47.08#ibcon#read 4, iclass 30, count 2 2006.201.03:37:47.08#ibcon#about to read 5, iclass 30, count 2 2006.201.03:37:47.08#ibcon#read 5, iclass 30, count 2 2006.201.03:37:47.08#ibcon#about to read 6, iclass 30, count 2 2006.201.03:37:47.08#ibcon#read 6, iclass 30, count 2 2006.201.03:37:47.08#ibcon#end of sib2, iclass 30, count 2 2006.201.03:37:47.08#ibcon#*after write, iclass 30, count 2 2006.201.03:37:47.08#ibcon#*before return 0, iclass 30, count 2 2006.201.03:37:47.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:47.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:47.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.03:37:47.08#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:47.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:47.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:47.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:47.20#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:37:47.20#ibcon#first serial, iclass 30, count 0 2006.201.03:37:47.20#ibcon#enter sib2, iclass 30, count 0 2006.201.03:37:47.20#ibcon#flushed, iclass 30, count 0 2006.201.03:37:47.20#ibcon#about to write, iclass 30, count 0 2006.201.03:37:47.20#ibcon#wrote, iclass 30, count 0 2006.201.03:37:47.20#ibcon#about to read 3, iclass 30, count 0 2006.201.03:37:47.23#ibcon#read 3, iclass 30, count 0 2006.201.03:37:47.23#ibcon#about to read 4, iclass 30, count 0 2006.201.03:37:47.23#ibcon#read 4, iclass 30, count 0 2006.201.03:37:47.23#ibcon#about to read 5, iclass 30, count 0 2006.201.03:37:47.23#ibcon#read 5, iclass 30, count 0 2006.201.03:37:47.23#ibcon#about to read 6, iclass 30, count 0 2006.201.03:37:47.23#ibcon#read 6, iclass 30, count 0 2006.201.03:37:47.23#ibcon#end of sib2, iclass 30, count 0 2006.201.03:37:47.23#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:37:47.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:37:47.23#ibcon#[25=USB\r\n] 2006.201.03:37:47.23#ibcon#*before write, iclass 30, count 0 2006.201.03:37:47.23#ibcon#enter sib2, iclass 30, count 0 2006.201.03:37:47.23#ibcon#flushed, iclass 30, count 0 2006.201.03:37:47.23#ibcon#about to write, iclass 30, count 0 2006.201.03:37:47.23#ibcon#wrote, iclass 30, count 0 2006.201.03:37:47.23#ibcon#about to read 3, iclass 30, count 0 2006.201.03:37:47.26#ibcon#read 3, iclass 30, count 0 2006.201.03:37:47.26#ibcon#about to read 4, iclass 30, count 0 2006.201.03:37:47.26#ibcon#read 4, iclass 30, count 0 2006.201.03:37:47.26#ibcon#about to read 5, iclass 30, count 0 2006.201.03:37:47.26#ibcon#read 5, iclass 30, count 0 2006.201.03:37:47.26#ibcon#about to read 6, iclass 30, count 0 2006.201.03:37:47.26#ibcon#read 6, iclass 30, count 0 2006.201.03:37:47.26#ibcon#end of sib2, iclass 30, count 0 2006.201.03:37:47.26#ibcon#*after write, iclass 30, count 0 2006.201.03:37:47.26#ibcon#*before return 0, iclass 30, count 0 2006.201.03:37:47.26#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:47.26#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:47.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:37:47.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:37:47.26$vck44/valo=8,884.99 2006.201.03:37:47.26#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.03:37:47.26#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.03:37:47.26#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:47.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:47.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:47.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:47.26#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:37:47.26#ibcon#first serial, iclass 32, count 0 2006.201.03:37:47.26#ibcon#enter sib2, iclass 32, count 0 2006.201.03:37:47.26#ibcon#flushed, iclass 32, count 0 2006.201.03:37:47.26#ibcon#about to write, iclass 32, count 0 2006.201.03:37:47.26#ibcon#wrote, iclass 32, count 0 2006.201.03:37:47.26#ibcon#about to read 3, iclass 32, count 0 2006.201.03:37:47.28#ibcon#read 3, iclass 32, count 0 2006.201.03:37:47.28#ibcon#about to read 4, iclass 32, count 0 2006.201.03:37:47.28#ibcon#read 4, iclass 32, count 0 2006.201.03:37:47.28#ibcon#about to read 5, iclass 32, count 0 2006.201.03:37:47.28#ibcon#read 5, iclass 32, count 0 2006.201.03:37:47.28#ibcon#about to read 6, iclass 32, count 0 2006.201.03:37:47.28#ibcon#read 6, iclass 32, count 0 2006.201.03:37:47.28#ibcon#end of sib2, iclass 32, count 0 2006.201.03:37:47.28#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:37:47.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:37:47.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:37:47.28#ibcon#*before write, iclass 32, count 0 2006.201.03:37:47.28#ibcon#enter sib2, iclass 32, count 0 2006.201.03:37:47.28#ibcon#flushed, iclass 32, count 0 2006.201.03:37:47.28#ibcon#about to write, iclass 32, count 0 2006.201.03:37:47.28#ibcon#wrote, iclass 32, count 0 2006.201.03:37:47.28#ibcon#about to read 3, iclass 32, count 0 2006.201.03:37:47.32#ibcon#read 3, iclass 32, count 0 2006.201.03:37:47.32#ibcon#about to read 4, iclass 32, count 0 2006.201.03:37:47.32#ibcon#read 4, iclass 32, count 0 2006.201.03:37:47.32#ibcon#about to read 5, iclass 32, count 0 2006.201.03:37:47.32#ibcon#read 5, iclass 32, count 0 2006.201.03:37:47.32#ibcon#about to read 6, iclass 32, count 0 2006.201.03:37:47.32#ibcon#read 6, iclass 32, count 0 2006.201.03:37:47.32#ibcon#end of sib2, iclass 32, count 0 2006.201.03:37:47.32#ibcon#*after write, iclass 32, count 0 2006.201.03:37:47.32#ibcon#*before return 0, iclass 32, count 0 2006.201.03:37:47.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:47.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:47.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:37:47.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:37:47.32$vck44/va=8,4 2006.201.03:37:47.32#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.03:37:47.32#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.03:37:47.32#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:47.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:47.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:47.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:47.38#ibcon#enter wrdev, iclass 34, count 2 2006.201.03:37:47.38#ibcon#first serial, iclass 34, count 2 2006.201.03:37:47.38#ibcon#enter sib2, iclass 34, count 2 2006.201.03:37:47.38#ibcon#flushed, iclass 34, count 2 2006.201.03:37:47.38#ibcon#about to write, iclass 34, count 2 2006.201.03:37:47.38#ibcon#wrote, iclass 34, count 2 2006.201.03:37:47.38#ibcon#about to read 3, iclass 34, count 2 2006.201.03:37:47.40#ibcon#read 3, iclass 34, count 2 2006.201.03:37:47.40#ibcon#about to read 4, iclass 34, count 2 2006.201.03:37:47.40#ibcon#read 4, iclass 34, count 2 2006.201.03:37:47.40#ibcon#about to read 5, iclass 34, count 2 2006.201.03:37:47.40#ibcon#read 5, iclass 34, count 2 2006.201.03:37:47.40#ibcon#about to read 6, iclass 34, count 2 2006.201.03:37:47.40#ibcon#read 6, iclass 34, count 2 2006.201.03:37:47.40#ibcon#end of sib2, iclass 34, count 2 2006.201.03:37:47.40#ibcon#*mode == 0, iclass 34, count 2 2006.201.03:37:47.40#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.03:37:47.40#ibcon#[25=AT08-04\r\n] 2006.201.03:37:47.40#ibcon#*before write, iclass 34, count 2 2006.201.03:37:47.40#ibcon#enter sib2, iclass 34, count 2 2006.201.03:37:47.40#ibcon#flushed, iclass 34, count 2 2006.201.03:37:47.40#ibcon#about to write, iclass 34, count 2 2006.201.03:37:47.40#ibcon#wrote, iclass 34, count 2 2006.201.03:37:47.40#ibcon#about to read 3, iclass 34, count 2 2006.201.03:37:47.43#ibcon#read 3, iclass 34, count 2 2006.201.03:37:47.43#ibcon#about to read 4, iclass 34, count 2 2006.201.03:37:47.43#ibcon#read 4, iclass 34, count 2 2006.201.03:37:47.43#ibcon#about to read 5, iclass 34, count 2 2006.201.03:37:47.43#ibcon#read 5, iclass 34, count 2 2006.201.03:37:47.43#ibcon#about to read 6, iclass 34, count 2 2006.201.03:37:47.43#ibcon#read 6, iclass 34, count 2 2006.201.03:37:47.43#ibcon#end of sib2, iclass 34, count 2 2006.201.03:37:47.43#ibcon#*after write, iclass 34, count 2 2006.201.03:37:47.43#ibcon#*before return 0, iclass 34, count 2 2006.201.03:37:47.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:47.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:47.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.03:37:47.43#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:47.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:47.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:47.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:47.55#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:37:47.55#ibcon#first serial, iclass 34, count 0 2006.201.03:37:47.55#ibcon#enter sib2, iclass 34, count 0 2006.201.03:37:47.55#ibcon#flushed, iclass 34, count 0 2006.201.03:37:47.55#ibcon#about to write, iclass 34, count 0 2006.201.03:37:47.55#ibcon#wrote, iclass 34, count 0 2006.201.03:37:47.55#ibcon#about to read 3, iclass 34, count 0 2006.201.03:37:47.57#ibcon#read 3, iclass 34, count 0 2006.201.03:37:47.57#ibcon#about to read 4, iclass 34, count 0 2006.201.03:37:47.57#ibcon#read 4, iclass 34, count 0 2006.201.03:37:47.57#ibcon#about to read 5, iclass 34, count 0 2006.201.03:37:47.57#ibcon#read 5, iclass 34, count 0 2006.201.03:37:47.57#ibcon#about to read 6, iclass 34, count 0 2006.201.03:37:47.57#ibcon#read 6, iclass 34, count 0 2006.201.03:37:47.57#ibcon#end of sib2, iclass 34, count 0 2006.201.03:37:47.57#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:37:47.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:37:47.57#ibcon#[25=USB\r\n] 2006.201.03:37:47.57#ibcon#*before write, iclass 34, count 0 2006.201.03:37:47.57#ibcon#enter sib2, iclass 34, count 0 2006.201.03:37:47.57#ibcon#flushed, iclass 34, count 0 2006.201.03:37:47.57#ibcon#about to write, iclass 34, count 0 2006.201.03:37:47.57#ibcon#wrote, iclass 34, count 0 2006.201.03:37:47.57#ibcon#about to read 3, iclass 34, count 0 2006.201.03:37:47.60#ibcon#read 3, iclass 34, count 0 2006.201.03:37:47.60#ibcon#about to read 4, iclass 34, count 0 2006.201.03:37:47.60#ibcon#read 4, iclass 34, count 0 2006.201.03:37:47.60#ibcon#about to read 5, iclass 34, count 0 2006.201.03:37:47.60#ibcon#read 5, iclass 34, count 0 2006.201.03:37:47.60#ibcon#about to read 6, iclass 34, count 0 2006.201.03:37:47.60#ibcon#read 6, iclass 34, count 0 2006.201.03:37:47.60#ibcon#end of sib2, iclass 34, count 0 2006.201.03:37:47.60#ibcon#*after write, iclass 34, count 0 2006.201.03:37:47.60#ibcon#*before return 0, iclass 34, count 0 2006.201.03:37:47.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:47.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:47.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:37:47.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:37:47.60$vck44/vblo=1,629.99 2006.201.03:37:47.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.03:37:47.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.03:37:47.60#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:47.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:47.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:47.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:47.60#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:37:47.60#ibcon#first serial, iclass 36, count 0 2006.201.03:37:47.60#ibcon#enter sib2, iclass 36, count 0 2006.201.03:37:47.60#ibcon#flushed, iclass 36, count 0 2006.201.03:37:47.60#ibcon#about to write, iclass 36, count 0 2006.201.03:37:47.60#ibcon#wrote, iclass 36, count 0 2006.201.03:37:47.60#ibcon#about to read 3, iclass 36, count 0 2006.201.03:37:47.62#ibcon#read 3, iclass 36, count 0 2006.201.03:37:47.62#ibcon#about to read 4, iclass 36, count 0 2006.201.03:37:47.62#ibcon#read 4, iclass 36, count 0 2006.201.03:37:47.62#ibcon#about to read 5, iclass 36, count 0 2006.201.03:37:47.62#ibcon#read 5, iclass 36, count 0 2006.201.03:37:47.62#ibcon#about to read 6, iclass 36, count 0 2006.201.03:37:47.62#ibcon#read 6, iclass 36, count 0 2006.201.03:37:47.62#ibcon#end of sib2, iclass 36, count 0 2006.201.03:37:47.62#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:37:47.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:37:47.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:37:47.62#ibcon#*before write, iclass 36, count 0 2006.201.03:37:47.62#ibcon#enter sib2, iclass 36, count 0 2006.201.03:37:47.62#ibcon#flushed, iclass 36, count 0 2006.201.03:37:47.62#ibcon#about to write, iclass 36, count 0 2006.201.03:37:47.62#ibcon#wrote, iclass 36, count 0 2006.201.03:37:47.62#ibcon#about to read 3, iclass 36, count 0 2006.201.03:37:47.66#ibcon#read 3, iclass 36, count 0 2006.201.03:37:47.66#ibcon#about to read 4, iclass 36, count 0 2006.201.03:37:47.66#ibcon#read 4, iclass 36, count 0 2006.201.03:37:47.66#ibcon#about to read 5, iclass 36, count 0 2006.201.03:37:47.66#ibcon#read 5, iclass 36, count 0 2006.201.03:37:47.66#ibcon#about to read 6, iclass 36, count 0 2006.201.03:37:47.66#ibcon#read 6, iclass 36, count 0 2006.201.03:37:47.66#ibcon#end of sib2, iclass 36, count 0 2006.201.03:37:47.66#ibcon#*after write, iclass 36, count 0 2006.201.03:37:47.66#ibcon#*before return 0, iclass 36, count 0 2006.201.03:37:47.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:47.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:47.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:37:47.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:37:47.66$vck44/vb=1,4 2006.201.03:37:47.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.03:37:47.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.03:37:47.66#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:47.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:37:47.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:37:47.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:37:47.66#ibcon#enter wrdev, iclass 38, count 2 2006.201.03:37:47.66#ibcon#first serial, iclass 38, count 2 2006.201.03:37:47.66#ibcon#enter sib2, iclass 38, count 2 2006.201.03:37:47.66#ibcon#flushed, iclass 38, count 2 2006.201.03:37:47.66#ibcon#about to write, iclass 38, count 2 2006.201.03:37:47.66#ibcon#wrote, iclass 38, count 2 2006.201.03:37:47.66#ibcon#about to read 3, iclass 38, count 2 2006.201.03:37:47.68#ibcon#read 3, iclass 38, count 2 2006.201.03:37:47.68#ibcon#about to read 4, iclass 38, count 2 2006.201.03:37:47.68#ibcon#read 4, iclass 38, count 2 2006.201.03:37:47.68#ibcon#about to read 5, iclass 38, count 2 2006.201.03:37:47.68#ibcon#read 5, iclass 38, count 2 2006.201.03:37:47.68#ibcon#about to read 6, iclass 38, count 2 2006.201.03:37:47.68#ibcon#read 6, iclass 38, count 2 2006.201.03:37:47.68#ibcon#end of sib2, iclass 38, count 2 2006.201.03:37:47.68#ibcon#*mode == 0, iclass 38, count 2 2006.201.03:37:47.68#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.03:37:47.68#ibcon#[27=AT01-04\r\n] 2006.201.03:37:47.68#ibcon#*before write, iclass 38, count 2 2006.201.03:37:47.68#ibcon#enter sib2, iclass 38, count 2 2006.201.03:37:47.68#ibcon#flushed, iclass 38, count 2 2006.201.03:37:47.68#ibcon#about to write, iclass 38, count 2 2006.201.03:37:47.68#ibcon#wrote, iclass 38, count 2 2006.201.03:37:47.68#ibcon#about to read 3, iclass 38, count 2 2006.201.03:37:47.71#ibcon#read 3, iclass 38, count 2 2006.201.03:37:47.71#ibcon#about to read 4, iclass 38, count 2 2006.201.03:37:47.71#ibcon#read 4, iclass 38, count 2 2006.201.03:37:47.71#ibcon#about to read 5, iclass 38, count 2 2006.201.03:37:47.71#ibcon#read 5, iclass 38, count 2 2006.201.03:37:47.71#ibcon#about to read 6, iclass 38, count 2 2006.201.03:37:47.71#ibcon#read 6, iclass 38, count 2 2006.201.03:37:47.71#ibcon#end of sib2, iclass 38, count 2 2006.201.03:37:47.71#ibcon#*after write, iclass 38, count 2 2006.201.03:37:47.71#ibcon#*before return 0, iclass 38, count 2 2006.201.03:37:47.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:37:47.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.03:37:47.71#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.03:37:47.71#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:47.71#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:37:47.83#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:37:47.83#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:37:47.83#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:37:47.83#ibcon#first serial, iclass 38, count 0 2006.201.03:37:47.83#ibcon#enter sib2, iclass 38, count 0 2006.201.03:37:47.83#ibcon#flushed, iclass 38, count 0 2006.201.03:37:47.83#ibcon#about to write, iclass 38, count 0 2006.201.03:37:47.83#ibcon#wrote, iclass 38, count 0 2006.201.03:37:47.83#ibcon#about to read 3, iclass 38, count 0 2006.201.03:37:47.85#ibcon#read 3, iclass 38, count 0 2006.201.03:37:47.85#ibcon#about to read 4, iclass 38, count 0 2006.201.03:37:47.85#ibcon#read 4, iclass 38, count 0 2006.201.03:37:47.85#ibcon#about to read 5, iclass 38, count 0 2006.201.03:37:47.85#ibcon#read 5, iclass 38, count 0 2006.201.03:37:47.85#ibcon#about to read 6, iclass 38, count 0 2006.201.03:37:47.85#ibcon#read 6, iclass 38, count 0 2006.201.03:37:47.85#ibcon#end of sib2, iclass 38, count 0 2006.201.03:37:47.85#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:37:47.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:37:47.85#ibcon#[27=USB\r\n] 2006.201.03:37:47.85#ibcon#*before write, iclass 38, count 0 2006.201.03:37:47.85#ibcon#enter sib2, iclass 38, count 0 2006.201.03:37:47.85#ibcon#flushed, iclass 38, count 0 2006.201.03:37:47.85#ibcon#about to write, iclass 38, count 0 2006.201.03:37:47.85#ibcon#wrote, iclass 38, count 0 2006.201.03:37:47.85#ibcon#about to read 3, iclass 38, count 0 2006.201.03:37:47.88#ibcon#read 3, iclass 38, count 0 2006.201.03:37:47.88#ibcon#about to read 4, iclass 38, count 0 2006.201.03:37:47.88#ibcon#read 4, iclass 38, count 0 2006.201.03:37:47.88#ibcon#about to read 5, iclass 38, count 0 2006.201.03:37:47.88#ibcon#read 5, iclass 38, count 0 2006.201.03:37:47.88#ibcon#about to read 6, iclass 38, count 0 2006.201.03:37:47.88#ibcon#read 6, iclass 38, count 0 2006.201.03:37:47.88#ibcon#end of sib2, iclass 38, count 0 2006.201.03:37:47.88#ibcon#*after write, iclass 38, count 0 2006.201.03:37:47.88#ibcon#*before return 0, iclass 38, count 0 2006.201.03:37:47.88#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:37:47.88#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.03:37:47.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:37:47.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:37:47.88$vck44/vblo=2,634.99 2006.201.03:37:47.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.03:37:47.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.03:37:47.88#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:47.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:47.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:47.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:47.88#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:37:47.88#ibcon#first serial, iclass 40, count 0 2006.201.03:37:47.88#ibcon#enter sib2, iclass 40, count 0 2006.201.03:37:47.88#ibcon#flushed, iclass 40, count 0 2006.201.03:37:47.88#ibcon#about to write, iclass 40, count 0 2006.201.03:37:47.88#ibcon#wrote, iclass 40, count 0 2006.201.03:37:47.88#ibcon#about to read 3, iclass 40, count 0 2006.201.03:37:47.90#ibcon#read 3, iclass 40, count 0 2006.201.03:37:47.90#ibcon#about to read 4, iclass 40, count 0 2006.201.03:37:47.90#ibcon#read 4, iclass 40, count 0 2006.201.03:37:47.90#ibcon#about to read 5, iclass 40, count 0 2006.201.03:37:47.90#ibcon#read 5, iclass 40, count 0 2006.201.03:37:47.90#ibcon#about to read 6, iclass 40, count 0 2006.201.03:37:47.90#ibcon#read 6, iclass 40, count 0 2006.201.03:37:47.90#ibcon#end of sib2, iclass 40, count 0 2006.201.03:37:47.90#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:37:47.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:37:47.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:37:47.90#ibcon#*before write, iclass 40, count 0 2006.201.03:37:47.90#ibcon#enter sib2, iclass 40, count 0 2006.201.03:37:47.90#ibcon#flushed, iclass 40, count 0 2006.201.03:37:47.90#ibcon#about to write, iclass 40, count 0 2006.201.03:37:47.90#ibcon#wrote, iclass 40, count 0 2006.201.03:37:47.90#ibcon#about to read 3, iclass 40, count 0 2006.201.03:37:47.94#ibcon#read 3, iclass 40, count 0 2006.201.03:37:47.94#ibcon#about to read 4, iclass 40, count 0 2006.201.03:37:47.94#ibcon#read 4, iclass 40, count 0 2006.201.03:37:47.94#ibcon#about to read 5, iclass 40, count 0 2006.201.03:37:47.94#ibcon#read 5, iclass 40, count 0 2006.201.03:37:47.94#ibcon#about to read 6, iclass 40, count 0 2006.201.03:37:47.94#ibcon#read 6, iclass 40, count 0 2006.201.03:37:47.94#ibcon#end of sib2, iclass 40, count 0 2006.201.03:37:47.94#ibcon#*after write, iclass 40, count 0 2006.201.03:37:47.94#ibcon#*before return 0, iclass 40, count 0 2006.201.03:37:47.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:47.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:37:47.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:37:47.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:37:47.94$vck44/vb=2,5 2006.201.03:37:47.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.03:37:47.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.03:37:47.94#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:47.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:48.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:48.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:48.00#ibcon#enter wrdev, iclass 4, count 2 2006.201.03:37:48.00#ibcon#first serial, iclass 4, count 2 2006.201.03:37:48.00#ibcon#enter sib2, iclass 4, count 2 2006.201.03:37:48.00#ibcon#flushed, iclass 4, count 2 2006.201.03:37:48.00#ibcon#about to write, iclass 4, count 2 2006.201.03:37:48.00#ibcon#wrote, iclass 4, count 2 2006.201.03:37:48.00#ibcon#about to read 3, iclass 4, count 2 2006.201.03:37:48.02#ibcon#read 3, iclass 4, count 2 2006.201.03:37:48.02#ibcon#about to read 4, iclass 4, count 2 2006.201.03:37:48.02#ibcon#read 4, iclass 4, count 2 2006.201.03:37:48.02#ibcon#about to read 5, iclass 4, count 2 2006.201.03:37:48.02#ibcon#read 5, iclass 4, count 2 2006.201.03:37:48.02#ibcon#about to read 6, iclass 4, count 2 2006.201.03:37:48.02#ibcon#read 6, iclass 4, count 2 2006.201.03:37:48.02#ibcon#end of sib2, iclass 4, count 2 2006.201.03:37:48.02#ibcon#*mode == 0, iclass 4, count 2 2006.201.03:37:48.02#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.03:37:48.02#ibcon#[27=AT02-05\r\n] 2006.201.03:37:48.02#ibcon#*before write, iclass 4, count 2 2006.201.03:37:48.02#ibcon#enter sib2, iclass 4, count 2 2006.201.03:37:48.02#ibcon#flushed, iclass 4, count 2 2006.201.03:37:48.02#ibcon#about to write, iclass 4, count 2 2006.201.03:37:48.02#ibcon#wrote, iclass 4, count 2 2006.201.03:37:48.02#ibcon#about to read 3, iclass 4, count 2 2006.201.03:37:48.05#ibcon#read 3, iclass 4, count 2 2006.201.03:37:48.05#ibcon#about to read 4, iclass 4, count 2 2006.201.03:37:48.05#ibcon#read 4, iclass 4, count 2 2006.201.03:37:48.05#ibcon#about to read 5, iclass 4, count 2 2006.201.03:37:48.05#ibcon#read 5, iclass 4, count 2 2006.201.03:37:48.05#ibcon#about to read 6, iclass 4, count 2 2006.201.03:37:48.05#ibcon#read 6, iclass 4, count 2 2006.201.03:37:48.05#ibcon#end of sib2, iclass 4, count 2 2006.201.03:37:48.05#ibcon#*after write, iclass 4, count 2 2006.201.03:37:48.05#ibcon#*before return 0, iclass 4, count 2 2006.201.03:37:48.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:48.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:37:48.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.03:37:48.05#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:48.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:48.17#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:48.17#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:48.17#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:37:48.17#ibcon#first serial, iclass 4, count 0 2006.201.03:37:48.17#ibcon#enter sib2, iclass 4, count 0 2006.201.03:37:48.17#ibcon#flushed, iclass 4, count 0 2006.201.03:37:48.17#ibcon#about to write, iclass 4, count 0 2006.201.03:37:48.17#ibcon#wrote, iclass 4, count 0 2006.201.03:37:48.17#ibcon#about to read 3, iclass 4, count 0 2006.201.03:37:48.19#ibcon#read 3, iclass 4, count 0 2006.201.03:37:48.19#ibcon#about to read 4, iclass 4, count 0 2006.201.03:37:48.19#ibcon#read 4, iclass 4, count 0 2006.201.03:37:48.19#ibcon#about to read 5, iclass 4, count 0 2006.201.03:37:48.19#ibcon#read 5, iclass 4, count 0 2006.201.03:37:48.19#ibcon#about to read 6, iclass 4, count 0 2006.201.03:37:48.19#ibcon#read 6, iclass 4, count 0 2006.201.03:37:48.19#ibcon#end of sib2, iclass 4, count 0 2006.201.03:37:48.19#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:37:48.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:37:48.19#ibcon#[27=USB\r\n] 2006.201.03:37:48.19#ibcon#*before write, iclass 4, count 0 2006.201.03:37:48.19#ibcon#enter sib2, iclass 4, count 0 2006.201.03:37:48.19#ibcon#flushed, iclass 4, count 0 2006.201.03:37:48.19#ibcon#about to write, iclass 4, count 0 2006.201.03:37:48.19#ibcon#wrote, iclass 4, count 0 2006.201.03:37:48.19#ibcon#about to read 3, iclass 4, count 0 2006.201.03:37:48.22#ibcon#read 3, iclass 4, count 0 2006.201.03:37:48.22#ibcon#about to read 4, iclass 4, count 0 2006.201.03:37:48.22#ibcon#read 4, iclass 4, count 0 2006.201.03:37:48.22#ibcon#about to read 5, iclass 4, count 0 2006.201.03:37:48.22#ibcon#read 5, iclass 4, count 0 2006.201.03:37:48.22#ibcon#about to read 6, iclass 4, count 0 2006.201.03:37:48.22#ibcon#read 6, iclass 4, count 0 2006.201.03:37:48.22#ibcon#end of sib2, iclass 4, count 0 2006.201.03:37:48.22#ibcon#*after write, iclass 4, count 0 2006.201.03:37:48.22#ibcon#*before return 0, iclass 4, count 0 2006.201.03:37:48.22#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:48.22#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:37:48.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:37:48.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:37:48.22$vck44/vblo=3,649.99 2006.201.03:37:48.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.03:37:48.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.03:37:48.22#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:48.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:48.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:48.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:48.22#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:37:48.22#ibcon#first serial, iclass 6, count 0 2006.201.03:37:48.22#ibcon#enter sib2, iclass 6, count 0 2006.201.03:37:48.22#ibcon#flushed, iclass 6, count 0 2006.201.03:37:48.22#ibcon#about to write, iclass 6, count 0 2006.201.03:37:48.22#ibcon#wrote, iclass 6, count 0 2006.201.03:37:48.22#ibcon#about to read 3, iclass 6, count 0 2006.201.03:37:48.24#ibcon#read 3, iclass 6, count 0 2006.201.03:37:48.24#ibcon#about to read 4, iclass 6, count 0 2006.201.03:37:48.24#ibcon#read 4, iclass 6, count 0 2006.201.03:37:48.24#ibcon#about to read 5, iclass 6, count 0 2006.201.03:37:48.24#ibcon#read 5, iclass 6, count 0 2006.201.03:37:48.24#ibcon#about to read 6, iclass 6, count 0 2006.201.03:37:48.24#ibcon#read 6, iclass 6, count 0 2006.201.03:37:48.24#ibcon#end of sib2, iclass 6, count 0 2006.201.03:37:48.24#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:37:48.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:37:48.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:37:48.24#ibcon#*before write, iclass 6, count 0 2006.201.03:37:48.24#ibcon#enter sib2, iclass 6, count 0 2006.201.03:37:48.24#ibcon#flushed, iclass 6, count 0 2006.201.03:37:48.24#ibcon#about to write, iclass 6, count 0 2006.201.03:37:48.24#ibcon#wrote, iclass 6, count 0 2006.201.03:37:48.24#ibcon#about to read 3, iclass 6, count 0 2006.201.03:37:48.28#ibcon#read 3, iclass 6, count 0 2006.201.03:37:48.28#ibcon#about to read 4, iclass 6, count 0 2006.201.03:37:48.28#ibcon#read 4, iclass 6, count 0 2006.201.03:37:48.28#ibcon#about to read 5, iclass 6, count 0 2006.201.03:37:48.28#ibcon#read 5, iclass 6, count 0 2006.201.03:37:48.28#ibcon#about to read 6, iclass 6, count 0 2006.201.03:37:48.28#ibcon#read 6, iclass 6, count 0 2006.201.03:37:48.28#ibcon#end of sib2, iclass 6, count 0 2006.201.03:37:48.28#ibcon#*after write, iclass 6, count 0 2006.201.03:37:48.28#ibcon#*before return 0, iclass 6, count 0 2006.201.03:37:48.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:48.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:37:48.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:37:48.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:37:48.28$vck44/vb=3,4 2006.201.03:37:48.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.03:37:48.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.03:37:48.28#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:48.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:48.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:48.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:48.34#ibcon#enter wrdev, iclass 10, count 2 2006.201.03:37:48.34#ibcon#first serial, iclass 10, count 2 2006.201.03:37:48.34#ibcon#enter sib2, iclass 10, count 2 2006.201.03:37:48.34#ibcon#flushed, iclass 10, count 2 2006.201.03:37:48.34#ibcon#about to write, iclass 10, count 2 2006.201.03:37:48.34#ibcon#wrote, iclass 10, count 2 2006.201.03:37:48.34#ibcon#about to read 3, iclass 10, count 2 2006.201.03:37:48.36#ibcon#read 3, iclass 10, count 2 2006.201.03:37:48.36#ibcon#about to read 4, iclass 10, count 2 2006.201.03:37:48.36#ibcon#read 4, iclass 10, count 2 2006.201.03:37:48.36#ibcon#about to read 5, iclass 10, count 2 2006.201.03:37:48.36#ibcon#read 5, iclass 10, count 2 2006.201.03:37:48.36#ibcon#about to read 6, iclass 10, count 2 2006.201.03:37:48.36#ibcon#read 6, iclass 10, count 2 2006.201.03:37:48.36#ibcon#end of sib2, iclass 10, count 2 2006.201.03:37:48.36#ibcon#*mode == 0, iclass 10, count 2 2006.201.03:37:48.36#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.03:37:48.36#ibcon#[27=AT03-04\r\n] 2006.201.03:37:48.36#ibcon#*before write, iclass 10, count 2 2006.201.03:37:48.36#ibcon#enter sib2, iclass 10, count 2 2006.201.03:37:48.36#ibcon#flushed, iclass 10, count 2 2006.201.03:37:48.36#ibcon#about to write, iclass 10, count 2 2006.201.03:37:48.36#ibcon#wrote, iclass 10, count 2 2006.201.03:37:48.36#ibcon#about to read 3, iclass 10, count 2 2006.201.03:37:48.39#ibcon#read 3, iclass 10, count 2 2006.201.03:37:48.39#ibcon#about to read 4, iclass 10, count 2 2006.201.03:37:48.39#ibcon#read 4, iclass 10, count 2 2006.201.03:37:48.39#ibcon#about to read 5, iclass 10, count 2 2006.201.03:37:48.39#ibcon#read 5, iclass 10, count 2 2006.201.03:37:48.39#ibcon#about to read 6, iclass 10, count 2 2006.201.03:37:48.39#ibcon#read 6, iclass 10, count 2 2006.201.03:37:48.39#ibcon#end of sib2, iclass 10, count 2 2006.201.03:37:48.39#ibcon#*after write, iclass 10, count 2 2006.201.03:37:48.39#ibcon#*before return 0, iclass 10, count 2 2006.201.03:37:48.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:48.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:37:48.39#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.03:37:48.39#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:48.39#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:48.51#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:48.51#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:48.51#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:37:48.51#ibcon#first serial, iclass 10, count 0 2006.201.03:37:48.51#ibcon#enter sib2, iclass 10, count 0 2006.201.03:37:48.51#ibcon#flushed, iclass 10, count 0 2006.201.03:37:48.51#ibcon#about to write, iclass 10, count 0 2006.201.03:37:48.51#ibcon#wrote, iclass 10, count 0 2006.201.03:37:48.51#ibcon#about to read 3, iclass 10, count 0 2006.201.03:37:48.53#ibcon#read 3, iclass 10, count 0 2006.201.03:37:48.53#ibcon#about to read 4, iclass 10, count 0 2006.201.03:37:48.53#ibcon#read 4, iclass 10, count 0 2006.201.03:37:48.53#ibcon#about to read 5, iclass 10, count 0 2006.201.03:37:48.53#ibcon#read 5, iclass 10, count 0 2006.201.03:37:48.53#ibcon#about to read 6, iclass 10, count 0 2006.201.03:37:48.53#ibcon#read 6, iclass 10, count 0 2006.201.03:37:48.53#ibcon#end of sib2, iclass 10, count 0 2006.201.03:37:48.53#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:37:48.53#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:37:48.53#ibcon#[27=USB\r\n] 2006.201.03:37:48.53#ibcon#*before write, iclass 10, count 0 2006.201.03:37:48.53#ibcon#enter sib2, iclass 10, count 0 2006.201.03:37:48.53#ibcon#flushed, iclass 10, count 0 2006.201.03:37:48.53#ibcon#about to write, iclass 10, count 0 2006.201.03:37:48.53#ibcon#wrote, iclass 10, count 0 2006.201.03:37:48.53#ibcon#about to read 3, iclass 10, count 0 2006.201.03:37:48.56#ibcon#read 3, iclass 10, count 0 2006.201.03:37:48.56#ibcon#about to read 4, iclass 10, count 0 2006.201.03:37:48.56#ibcon#read 4, iclass 10, count 0 2006.201.03:37:48.56#ibcon#about to read 5, iclass 10, count 0 2006.201.03:37:48.56#ibcon#read 5, iclass 10, count 0 2006.201.03:37:48.56#ibcon#about to read 6, iclass 10, count 0 2006.201.03:37:48.56#ibcon#read 6, iclass 10, count 0 2006.201.03:37:48.56#ibcon#end of sib2, iclass 10, count 0 2006.201.03:37:48.56#ibcon#*after write, iclass 10, count 0 2006.201.03:37:48.56#ibcon#*before return 0, iclass 10, count 0 2006.201.03:37:48.56#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:48.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:37:48.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:37:48.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:37:48.56$vck44/vblo=4,679.99 2006.201.03:37:48.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.03:37:48.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.03:37:48.56#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:48.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:48.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:48.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:48.56#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:37:48.56#ibcon#first serial, iclass 12, count 0 2006.201.03:37:48.56#ibcon#enter sib2, iclass 12, count 0 2006.201.03:37:48.56#ibcon#flushed, iclass 12, count 0 2006.201.03:37:48.56#ibcon#about to write, iclass 12, count 0 2006.201.03:37:48.56#ibcon#wrote, iclass 12, count 0 2006.201.03:37:48.56#ibcon#about to read 3, iclass 12, count 0 2006.201.03:37:48.58#ibcon#read 3, iclass 12, count 0 2006.201.03:37:48.58#ibcon#about to read 4, iclass 12, count 0 2006.201.03:37:48.58#ibcon#read 4, iclass 12, count 0 2006.201.03:37:48.58#ibcon#about to read 5, iclass 12, count 0 2006.201.03:37:48.58#ibcon#read 5, iclass 12, count 0 2006.201.03:37:48.58#ibcon#about to read 6, iclass 12, count 0 2006.201.03:37:48.58#ibcon#read 6, iclass 12, count 0 2006.201.03:37:48.58#ibcon#end of sib2, iclass 12, count 0 2006.201.03:37:48.58#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:37:48.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:37:48.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:37:48.58#ibcon#*before write, iclass 12, count 0 2006.201.03:37:48.58#ibcon#enter sib2, iclass 12, count 0 2006.201.03:37:48.58#ibcon#flushed, iclass 12, count 0 2006.201.03:37:48.58#ibcon#about to write, iclass 12, count 0 2006.201.03:37:48.58#ibcon#wrote, iclass 12, count 0 2006.201.03:37:48.58#ibcon#about to read 3, iclass 12, count 0 2006.201.03:37:48.62#ibcon#read 3, iclass 12, count 0 2006.201.03:37:48.62#ibcon#about to read 4, iclass 12, count 0 2006.201.03:37:48.62#ibcon#read 4, iclass 12, count 0 2006.201.03:37:48.62#ibcon#about to read 5, iclass 12, count 0 2006.201.03:37:48.62#ibcon#read 5, iclass 12, count 0 2006.201.03:37:48.62#ibcon#about to read 6, iclass 12, count 0 2006.201.03:37:48.62#ibcon#read 6, iclass 12, count 0 2006.201.03:37:48.62#ibcon#end of sib2, iclass 12, count 0 2006.201.03:37:48.62#ibcon#*after write, iclass 12, count 0 2006.201.03:37:48.62#ibcon#*before return 0, iclass 12, count 0 2006.201.03:37:48.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:48.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:37:48.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:37:48.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:37:48.62$vck44/vb=4,5 2006.201.03:37:48.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.03:37:48.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.03:37:48.62#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:48.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:48.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:48.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:48.68#ibcon#enter wrdev, iclass 14, count 2 2006.201.03:37:48.68#ibcon#first serial, iclass 14, count 2 2006.201.03:37:48.68#ibcon#enter sib2, iclass 14, count 2 2006.201.03:37:48.68#ibcon#flushed, iclass 14, count 2 2006.201.03:37:48.68#ibcon#about to write, iclass 14, count 2 2006.201.03:37:48.68#ibcon#wrote, iclass 14, count 2 2006.201.03:37:48.68#ibcon#about to read 3, iclass 14, count 2 2006.201.03:37:48.70#ibcon#read 3, iclass 14, count 2 2006.201.03:37:48.70#ibcon#about to read 4, iclass 14, count 2 2006.201.03:37:48.70#ibcon#read 4, iclass 14, count 2 2006.201.03:37:48.70#ibcon#about to read 5, iclass 14, count 2 2006.201.03:37:48.70#ibcon#read 5, iclass 14, count 2 2006.201.03:37:48.70#ibcon#about to read 6, iclass 14, count 2 2006.201.03:37:48.70#ibcon#read 6, iclass 14, count 2 2006.201.03:37:48.70#ibcon#end of sib2, iclass 14, count 2 2006.201.03:37:48.70#ibcon#*mode == 0, iclass 14, count 2 2006.201.03:37:48.70#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.03:37:48.70#ibcon#[27=AT04-05\r\n] 2006.201.03:37:48.70#ibcon#*before write, iclass 14, count 2 2006.201.03:37:48.70#ibcon#enter sib2, iclass 14, count 2 2006.201.03:37:48.70#ibcon#flushed, iclass 14, count 2 2006.201.03:37:48.70#ibcon#about to write, iclass 14, count 2 2006.201.03:37:48.70#ibcon#wrote, iclass 14, count 2 2006.201.03:37:48.70#ibcon#about to read 3, iclass 14, count 2 2006.201.03:37:48.73#ibcon#read 3, iclass 14, count 2 2006.201.03:37:48.73#ibcon#about to read 4, iclass 14, count 2 2006.201.03:37:48.73#ibcon#read 4, iclass 14, count 2 2006.201.03:37:48.73#ibcon#about to read 5, iclass 14, count 2 2006.201.03:37:48.73#ibcon#read 5, iclass 14, count 2 2006.201.03:37:48.73#ibcon#about to read 6, iclass 14, count 2 2006.201.03:37:48.73#ibcon#read 6, iclass 14, count 2 2006.201.03:37:48.73#ibcon#end of sib2, iclass 14, count 2 2006.201.03:37:48.73#ibcon#*after write, iclass 14, count 2 2006.201.03:37:48.73#ibcon#*before return 0, iclass 14, count 2 2006.201.03:37:48.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:48.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:37:48.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.03:37:48.73#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:48.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:48.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:48.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:48.85#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:37:48.85#ibcon#first serial, iclass 14, count 0 2006.201.03:37:48.85#ibcon#enter sib2, iclass 14, count 0 2006.201.03:37:48.85#ibcon#flushed, iclass 14, count 0 2006.201.03:37:48.85#ibcon#about to write, iclass 14, count 0 2006.201.03:37:48.85#ibcon#wrote, iclass 14, count 0 2006.201.03:37:48.85#ibcon#about to read 3, iclass 14, count 0 2006.201.03:37:48.87#ibcon#read 3, iclass 14, count 0 2006.201.03:37:48.87#ibcon#about to read 4, iclass 14, count 0 2006.201.03:37:48.87#ibcon#read 4, iclass 14, count 0 2006.201.03:37:48.87#ibcon#about to read 5, iclass 14, count 0 2006.201.03:37:48.87#ibcon#read 5, iclass 14, count 0 2006.201.03:37:48.87#ibcon#about to read 6, iclass 14, count 0 2006.201.03:37:48.87#ibcon#read 6, iclass 14, count 0 2006.201.03:37:48.87#ibcon#end of sib2, iclass 14, count 0 2006.201.03:37:48.87#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:37:48.87#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:37:48.87#ibcon#[27=USB\r\n] 2006.201.03:37:48.87#ibcon#*before write, iclass 14, count 0 2006.201.03:37:48.87#ibcon#enter sib2, iclass 14, count 0 2006.201.03:37:48.87#ibcon#flushed, iclass 14, count 0 2006.201.03:37:48.87#ibcon#about to write, iclass 14, count 0 2006.201.03:37:48.87#ibcon#wrote, iclass 14, count 0 2006.201.03:37:48.87#ibcon#about to read 3, iclass 14, count 0 2006.201.03:37:48.90#ibcon#read 3, iclass 14, count 0 2006.201.03:37:48.90#ibcon#about to read 4, iclass 14, count 0 2006.201.03:37:48.90#ibcon#read 4, iclass 14, count 0 2006.201.03:37:48.90#ibcon#about to read 5, iclass 14, count 0 2006.201.03:37:48.90#ibcon#read 5, iclass 14, count 0 2006.201.03:37:48.90#ibcon#about to read 6, iclass 14, count 0 2006.201.03:37:48.90#ibcon#read 6, iclass 14, count 0 2006.201.03:37:48.90#ibcon#end of sib2, iclass 14, count 0 2006.201.03:37:48.90#ibcon#*after write, iclass 14, count 0 2006.201.03:37:48.90#ibcon#*before return 0, iclass 14, count 0 2006.201.03:37:48.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:48.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:37:48.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:37:48.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:37:48.90$vck44/vblo=5,709.99 2006.201.03:37:48.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.03:37:48.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.03:37:48.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:48.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:48.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:48.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:48.90#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:37:48.90#ibcon#first serial, iclass 16, count 0 2006.201.03:37:48.90#ibcon#enter sib2, iclass 16, count 0 2006.201.03:37:48.90#ibcon#flushed, iclass 16, count 0 2006.201.03:37:48.90#ibcon#about to write, iclass 16, count 0 2006.201.03:37:48.90#ibcon#wrote, iclass 16, count 0 2006.201.03:37:48.90#ibcon#about to read 3, iclass 16, count 0 2006.201.03:37:48.92#ibcon#read 3, iclass 16, count 0 2006.201.03:37:48.92#ibcon#about to read 4, iclass 16, count 0 2006.201.03:37:48.92#ibcon#read 4, iclass 16, count 0 2006.201.03:37:48.92#ibcon#about to read 5, iclass 16, count 0 2006.201.03:37:48.92#ibcon#read 5, iclass 16, count 0 2006.201.03:37:48.92#ibcon#about to read 6, iclass 16, count 0 2006.201.03:37:48.92#ibcon#read 6, iclass 16, count 0 2006.201.03:37:48.92#ibcon#end of sib2, iclass 16, count 0 2006.201.03:37:48.92#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:37:48.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:37:48.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:37:48.92#ibcon#*before write, iclass 16, count 0 2006.201.03:37:48.92#ibcon#enter sib2, iclass 16, count 0 2006.201.03:37:48.92#ibcon#flushed, iclass 16, count 0 2006.201.03:37:48.92#ibcon#about to write, iclass 16, count 0 2006.201.03:37:48.92#ibcon#wrote, iclass 16, count 0 2006.201.03:37:48.92#ibcon#about to read 3, iclass 16, count 0 2006.201.03:37:48.96#ibcon#read 3, iclass 16, count 0 2006.201.03:37:48.96#ibcon#about to read 4, iclass 16, count 0 2006.201.03:37:48.96#ibcon#read 4, iclass 16, count 0 2006.201.03:37:48.96#ibcon#about to read 5, iclass 16, count 0 2006.201.03:37:48.96#ibcon#read 5, iclass 16, count 0 2006.201.03:37:48.96#ibcon#about to read 6, iclass 16, count 0 2006.201.03:37:48.96#ibcon#read 6, iclass 16, count 0 2006.201.03:37:48.96#ibcon#end of sib2, iclass 16, count 0 2006.201.03:37:48.96#ibcon#*after write, iclass 16, count 0 2006.201.03:37:48.96#ibcon#*before return 0, iclass 16, count 0 2006.201.03:37:48.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:48.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:37:48.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:37:48.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:37:48.96$vck44/vb=5,4 2006.201.03:37:48.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.03:37:48.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.03:37:48.96#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:48.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:49.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:49.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:49.02#ibcon#enter wrdev, iclass 18, count 2 2006.201.03:37:49.02#ibcon#first serial, iclass 18, count 2 2006.201.03:37:49.02#ibcon#enter sib2, iclass 18, count 2 2006.201.03:37:49.02#ibcon#flushed, iclass 18, count 2 2006.201.03:37:49.02#ibcon#about to write, iclass 18, count 2 2006.201.03:37:49.02#ibcon#wrote, iclass 18, count 2 2006.201.03:37:49.02#ibcon#about to read 3, iclass 18, count 2 2006.201.03:37:49.04#ibcon#read 3, iclass 18, count 2 2006.201.03:37:49.04#ibcon#about to read 4, iclass 18, count 2 2006.201.03:37:49.04#ibcon#read 4, iclass 18, count 2 2006.201.03:37:49.04#ibcon#about to read 5, iclass 18, count 2 2006.201.03:37:49.04#ibcon#read 5, iclass 18, count 2 2006.201.03:37:49.04#ibcon#about to read 6, iclass 18, count 2 2006.201.03:37:49.04#ibcon#read 6, iclass 18, count 2 2006.201.03:37:49.04#ibcon#end of sib2, iclass 18, count 2 2006.201.03:37:49.04#ibcon#*mode == 0, iclass 18, count 2 2006.201.03:37:49.04#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.03:37:49.04#ibcon#[27=AT05-04\r\n] 2006.201.03:37:49.04#ibcon#*before write, iclass 18, count 2 2006.201.03:37:49.04#ibcon#enter sib2, iclass 18, count 2 2006.201.03:37:49.04#ibcon#flushed, iclass 18, count 2 2006.201.03:37:49.04#ibcon#about to write, iclass 18, count 2 2006.201.03:37:49.04#ibcon#wrote, iclass 18, count 2 2006.201.03:37:49.04#ibcon#about to read 3, iclass 18, count 2 2006.201.03:37:49.07#ibcon#read 3, iclass 18, count 2 2006.201.03:37:49.07#ibcon#about to read 4, iclass 18, count 2 2006.201.03:37:49.07#ibcon#read 4, iclass 18, count 2 2006.201.03:37:49.07#ibcon#about to read 5, iclass 18, count 2 2006.201.03:37:49.07#ibcon#read 5, iclass 18, count 2 2006.201.03:37:49.07#ibcon#about to read 6, iclass 18, count 2 2006.201.03:37:49.07#ibcon#read 6, iclass 18, count 2 2006.201.03:37:49.07#ibcon#end of sib2, iclass 18, count 2 2006.201.03:37:49.07#ibcon#*after write, iclass 18, count 2 2006.201.03:37:49.07#ibcon#*before return 0, iclass 18, count 2 2006.201.03:37:49.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:49.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:37:49.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.03:37:49.07#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:49.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:49.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:49.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:49.19#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:37:49.19#ibcon#first serial, iclass 18, count 0 2006.201.03:37:49.19#ibcon#enter sib2, iclass 18, count 0 2006.201.03:37:49.19#ibcon#flushed, iclass 18, count 0 2006.201.03:37:49.19#ibcon#about to write, iclass 18, count 0 2006.201.03:37:49.19#ibcon#wrote, iclass 18, count 0 2006.201.03:37:49.19#ibcon#about to read 3, iclass 18, count 0 2006.201.03:37:49.21#ibcon#read 3, iclass 18, count 0 2006.201.03:37:49.21#ibcon#about to read 4, iclass 18, count 0 2006.201.03:37:49.21#ibcon#read 4, iclass 18, count 0 2006.201.03:37:49.21#ibcon#about to read 5, iclass 18, count 0 2006.201.03:37:49.21#ibcon#read 5, iclass 18, count 0 2006.201.03:37:49.21#ibcon#about to read 6, iclass 18, count 0 2006.201.03:37:49.21#ibcon#read 6, iclass 18, count 0 2006.201.03:37:49.21#ibcon#end of sib2, iclass 18, count 0 2006.201.03:37:49.21#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:37:49.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:37:49.21#ibcon#[27=USB\r\n] 2006.201.03:37:49.21#ibcon#*before write, iclass 18, count 0 2006.201.03:37:49.21#ibcon#enter sib2, iclass 18, count 0 2006.201.03:37:49.21#ibcon#flushed, iclass 18, count 0 2006.201.03:37:49.21#ibcon#about to write, iclass 18, count 0 2006.201.03:37:49.21#ibcon#wrote, iclass 18, count 0 2006.201.03:37:49.21#ibcon#about to read 3, iclass 18, count 0 2006.201.03:37:49.24#ibcon#read 3, iclass 18, count 0 2006.201.03:37:49.24#ibcon#about to read 4, iclass 18, count 0 2006.201.03:37:49.24#ibcon#read 4, iclass 18, count 0 2006.201.03:37:49.24#ibcon#about to read 5, iclass 18, count 0 2006.201.03:37:49.24#ibcon#read 5, iclass 18, count 0 2006.201.03:37:49.24#ibcon#about to read 6, iclass 18, count 0 2006.201.03:37:49.24#ibcon#read 6, iclass 18, count 0 2006.201.03:37:49.24#ibcon#end of sib2, iclass 18, count 0 2006.201.03:37:49.24#ibcon#*after write, iclass 18, count 0 2006.201.03:37:49.24#ibcon#*before return 0, iclass 18, count 0 2006.201.03:37:49.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:49.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:37:49.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:37:49.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:37:49.24$vck44/vblo=6,719.99 2006.201.03:37:49.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.03:37:49.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.03:37:49.24#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:49.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:49.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:49.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:49.24#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:37:49.24#ibcon#first serial, iclass 20, count 0 2006.201.03:37:49.24#ibcon#enter sib2, iclass 20, count 0 2006.201.03:37:49.24#ibcon#flushed, iclass 20, count 0 2006.201.03:37:49.24#ibcon#about to write, iclass 20, count 0 2006.201.03:37:49.24#ibcon#wrote, iclass 20, count 0 2006.201.03:37:49.24#ibcon#about to read 3, iclass 20, count 0 2006.201.03:37:49.26#ibcon#read 3, iclass 20, count 0 2006.201.03:37:49.26#ibcon#about to read 4, iclass 20, count 0 2006.201.03:37:49.26#ibcon#read 4, iclass 20, count 0 2006.201.03:37:49.26#ibcon#about to read 5, iclass 20, count 0 2006.201.03:37:49.26#ibcon#read 5, iclass 20, count 0 2006.201.03:37:49.26#ibcon#about to read 6, iclass 20, count 0 2006.201.03:37:49.26#ibcon#read 6, iclass 20, count 0 2006.201.03:37:49.26#ibcon#end of sib2, iclass 20, count 0 2006.201.03:37:49.26#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:37:49.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:37:49.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:37:49.26#ibcon#*before write, iclass 20, count 0 2006.201.03:37:49.26#ibcon#enter sib2, iclass 20, count 0 2006.201.03:37:49.26#ibcon#flushed, iclass 20, count 0 2006.201.03:37:49.26#ibcon#about to write, iclass 20, count 0 2006.201.03:37:49.26#ibcon#wrote, iclass 20, count 0 2006.201.03:37:49.26#ibcon#about to read 3, iclass 20, count 0 2006.201.03:37:49.30#ibcon#read 3, iclass 20, count 0 2006.201.03:37:49.30#ibcon#about to read 4, iclass 20, count 0 2006.201.03:37:49.30#ibcon#read 4, iclass 20, count 0 2006.201.03:37:49.30#ibcon#about to read 5, iclass 20, count 0 2006.201.03:37:49.30#ibcon#read 5, iclass 20, count 0 2006.201.03:37:49.30#ibcon#about to read 6, iclass 20, count 0 2006.201.03:37:49.30#ibcon#read 6, iclass 20, count 0 2006.201.03:37:49.30#ibcon#end of sib2, iclass 20, count 0 2006.201.03:37:49.30#ibcon#*after write, iclass 20, count 0 2006.201.03:37:49.30#ibcon#*before return 0, iclass 20, count 0 2006.201.03:37:49.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:49.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:37:49.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:37:49.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:37:49.30$vck44/vb=6,4 2006.201.03:37:49.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.03:37:49.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.03:37:49.30#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:49.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:49.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:49.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:49.36#ibcon#enter wrdev, iclass 22, count 2 2006.201.03:37:49.36#ibcon#first serial, iclass 22, count 2 2006.201.03:37:49.36#ibcon#enter sib2, iclass 22, count 2 2006.201.03:37:49.36#ibcon#flushed, iclass 22, count 2 2006.201.03:37:49.36#ibcon#about to write, iclass 22, count 2 2006.201.03:37:49.36#ibcon#wrote, iclass 22, count 2 2006.201.03:37:49.36#ibcon#about to read 3, iclass 22, count 2 2006.201.03:37:49.38#ibcon#read 3, iclass 22, count 2 2006.201.03:37:49.38#ibcon#about to read 4, iclass 22, count 2 2006.201.03:37:49.38#ibcon#read 4, iclass 22, count 2 2006.201.03:37:49.38#ibcon#about to read 5, iclass 22, count 2 2006.201.03:37:49.38#ibcon#read 5, iclass 22, count 2 2006.201.03:37:49.38#ibcon#about to read 6, iclass 22, count 2 2006.201.03:37:49.38#ibcon#read 6, iclass 22, count 2 2006.201.03:37:49.38#ibcon#end of sib2, iclass 22, count 2 2006.201.03:37:49.38#ibcon#*mode == 0, iclass 22, count 2 2006.201.03:37:49.38#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.03:37:49.38#ibcon#[27=AT06-04\r\n] 2006.201.03:37:49.38#ibcon#*before write, iclass 22, count 2 2006.201.03:37:49.38#ibcon#enter sib2, iclass 22, count 2 2006.201.03:37:49.38#ibcon#flushed, iclass 22, count 2 2006.201.03:37:49.38#ibcon#about to write, iclass 22, count 2 2006.201.03:37:49.38#ibcon#wrote, iclass 22, count 2 2006.201.03:37:49.38#ibcon#about to read 3, iclass 22, count 2 2006.201.03:37:49.41#ibcon#read 3, iclass 22, count 2 2006.201.03:37:49.41#ibcon#about to read 4, iclass 22, count 2 2006.201.03:37:49.41#ibcon#read 4, iclass 22, count 2 2006.201.03:37:49.41#ibcon#about to read 5, iclass 22, count 2 2006.201.03:37:49.41#ibcon#read 5, iclass 22, count 2 2006.201.03:37:49.41#ibcon#about to read 6, iclass 22, count 2 2006.201.03:37:49.41#ibcon#read 6, iclass 22, count 2 2006.201.03:37:49.41#ibcon#end of sib2, iclass 22, count 2 2006.201.03:37:49.41#ibcon#*after write, iclass 22, count 2 2006.201.03:37:49.41#ibcon#*before return 0, iclass 22, count 2 2006.201.03:37:49.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:49.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:37:49.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.03:37:49.41#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:49.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:49.50#abcon#<5=/04 2.1 4.3 23.05 921004.6\r\n> 2006.201.03:37:49.52#abcon#{5=INTERFACE CLEAR} 2006.201.03:37:49.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:49.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:49.53#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:37:49.53#ibcon#first serial, iclass 22, count 0 2006.201.03:37:49.53#ibcon#enter sib2, iclass 22, count 0 2006.201.03:37:49.53#ibcon#flushed, iclass 22, count 0 2006.201.03:37:49.53#ibcon#about to write, iclass 22, count 0 2006.201.03:37:49.53#ibcon#wrote, iclass 22, count 0 2006.201.03:37:49.53#ibcon#about to read 3, iclass 22, count 0 2006.201.03:37:49.55#ibcon#read 3, iclass 22, count 0 2006.201.03:37:49.55#ibcon#about to read 4, iclass 22, count 0 2006.201.03:37:49.55#ibcon#read 4, iclass 22, count 0 2006.201.03:37:49.55#ibcon#about to read 5, iclass 22, count 0 2006.201.03:37:49.55#ibcon#read 5, iclass 22, count 0 2006.201.03:37:49.55#ibcon#about to read 6, iclass 22, count 0 2006.201.03:37:49.55#ibcon#read 6, iclass 22, count 0 2006.201.03:37:49.55#ibcon#end of sib2, iclass 22, count 0 2006.201.03:37:49.55#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:37:49.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:37:49.55#ibcon#[27=USB\r\n] 2006.201.03:37:49.55#ibcon#*before write, iclass 22, count 0 2006.201.03:37:49.55#ibcon#enter sib2, iclass 22, count 0 2006.201.03:37:49.55#ibcon#flushed, iclass 22, count 0 2006.201.03:37:49.55#ibcon#about to write, iclass 22, count 0 2006.201.03:37:49.55#ibcon#wrote, iclass 22, count 0 2006.201.03:37:49.55#ibcon#about to read 3, iclass 22, count 0 2006.201.03:37:49.58#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:37:49.58#ibcon#read 3, iclass 22, count 0 2006.201.03:37:49.58#ibcon#about to read 4, iclass 22, count 0 2006.201.03:37:49.58#ibcon#read 4, iclass 22, count 0 2006.201.03:37:49.58#ibcon#about to read 5, iclass 22, count 0 2006.201.03:37:49.58#ibcon#read 5, iclass 22, count 0 2006.201.03:37:49.58#ibcon#about to read 6, iclass 22, count 0 2006.201.03:37:49.58#ibcon#read 6, iclass 22, count 0 2006.201.03:37:49.58#ibcon#end of sib2, iclass 22, count 0 2006.201.03:37:49.58#ibcon#*after write, iclass 22, count 0 2006.201.03:37:49.58#ibcon#*before return 0, iclass 22, count 0 2006.201.03:37:49.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:49.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:37:49.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:37:49.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:37:49.58$vck44/vblo=7,734.99 2006.201.03:37:49.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.03:37:49.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.03:37:49.58#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:49.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:49.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:49.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:49.58#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:37:49.58#ibcon#first serial, iclass 28, count 0 2006.201.03:37:49.58#ibcon#enter sib2, iclass 28, count 0 2006.201.03:37:49.58#ibcon#flushed, iclass 28, count 0 2006.201.03:37:49.58#ibcon#about to write, iclass 28, count 0 2006.201.03:37:49.58#ibcon#wrote, iclass 28, count 0 2006.201.03:37:49.58#ibcon#about to read 3, iclass 28, count 0 2006.201.03:37:49.60#ibcon#read 3, iclass 28, count 0 2006.201.03:37:49.60#ibcon#about to read 4, iclass 28, count 0 2006.201.03:37:49.60#ibcon#read 4, iclass 28, count 0 2006.201.03:37:49.60#ibcon#about to read 5, iclass 28, count 0 2006.201.03:37:49.60#ibcon#read 5, iclass 28, count 0 2006.201.03:37:49.60#ibcon#about to read 6, iclass 28, count 0 2006.201.03:37:49.60#ibcon#read 6, iclass 28, count 0 2006.201.03:37:49.60#ibcon#end of sib2, iclass 28, count 0 2006.201.03:37:49.60#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:37:49.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:37:49.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:37:49.60#ibcon#*before write, iclass 28, count 0 2006.201.03:37:49.60#ibcon#enter sib2, iclass 28, count 0 2006.201.03:37:49.60#ibcon#flushed, iclass 28, count 0 2006.201.03:37:49.60#ibcon#about to write, iclass 28, count 0 2006.201.03:37:49.60#ibcon#wrote, iclass 28, count 0 2006.201.03:37:49.60#ibcon#about to read 3, iclass 28, count 0 2006.201.03:37:49.64#ibcon#read 3, iclass 28, count 0 2006.201.03:37:49.64#ibcon#about to read 4, iclass 28, count 0 2006.201.03:37:49.64#ibcon#read 4, iclass 28, count 0 2006.201.03:37:49.64#ibcon#about to read 5, iclass 28, count 0 2006.201.03:37:49.64#ibcon#read 5, iclass 28, count 0 2006.201.03:37:49.64#ibcon#about to read 6, iclass 28, count 0 2006.201.03:37:49.64#ibcon#read 6, iclass 28, count 0 2006.201.03:37:49.64#ibcon#end of sib2, iclass 28, count 0 2006.201.03:37:49.64#ibcon#*after write, iclass 28, count 0 2006.201.03:37:49.64#ibcon#*before return 0, iclass 28, count 0 2006.201.03:37:49.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:49.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:37:49.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:37:49.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:37:49.64$vck44/vb=7,4 2006.201.03:37:49.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.03:37:49.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.03:37:49.64#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:49.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:49.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:49.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:49.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.03:37:49.70#ibcon#first serial, iclass 30, count 2 2006.201.03:37:49.70#ibcon#enter sib2, iclass 30, count 2 2006.201.03:37:49.70#ibcon#flushed, iclass 30, count 2 2006.201.03:37:49.70#ibcon#about to write, iclass 30, count 2 2006.201.03:37:49.70#ibcon#wrote, iclass 30, count 2 2006.201.03:37:49.70#ibcon#about to read 3, iclass 30, count 2 2006.201.03:37:49.72#ibcon#read 3, iclass 30, count 2 2006.201.03:37:49.72#ibcon#about to read 4, iclass 30, count 2 2006.201.03:37:49.72#ibcon#read 4, iclass 30, count 2 2006.201.03:37:49.72#ibcon#about to read 5, iclass 30, count 2 2006.201.03:37:49.72#ibcon#read 5, iclass 30, count 2 2006.201.03:37:49.72#ibcon#about to read 6, iclass 30, count 2 2006.201.03:37:49.72#ibcon#read 6, iclass 30, count 2 2006.201.03:37:49.72#ibcon#end of sib2, iclass 30, count 2 2006.201.03:37:49.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.03:37:49.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.03:37:49.72#ibcon#[27=AT07-04\r\n] 2006.201.03:37:49.72#ibcon#*before write, iclass 30, count 2 2006.201.03:37:49.72#ibcon#enter sib2, iclass 30, count 2 2006.201.03:37:49.72#ibcon#flushed, iclass 30, count 2 2006.201.03:37:49.72#ibcon#about to write, iclass 30, count 2 2006.201.03:37:49.72#ibcon#wrote, iclass 30, count 2 2006.201.03:37:49.72#ibcon#about to read 3, iclass 30, count 2 2006.201.03:37:49.75#ibcon#read 3, iclass 30, count 2 2006.201.03:37:49.75#ibcon#about to read 4, iclass 30, count 2 2006.201.03:37:49.75#ibcon#read 4, iclass 30, count 2 2006.201.03:37:49.75#ibcon#about to read 5, iclass 30, count 2 2006.201.03:37:49.75#ibcon#read 5, iclass 30, count 2 2006.201.03:37:49.75#ibcon#about to read 6, iclass 30, count 2 2006.201.03:37:49.75#ibcon#read 6, iclass 30, count 2 2006.201.03:37:49.75#ibcon#end of sib2, iclass 30, count 2 2006.201.03:37:49.75#ibcon#*after write, iclass 30, count 2 2006.201.03:37:49.75#ibcon#*before return 0, iclass 30, count 2 2006.201.03:37:49.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:49.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:37:49.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.03:37:49.75#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:49.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:49.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:49.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:49.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:37:49.87#ibcon#first serial, iclass 30, count 0 2006.201.03:37:49.87#ibcon#enter sib2, iclass 30, count 0 2006.201.03:37:49.87#ibcon#flushed, iclass 30, count 0 2006.201.03:37:49.87#ibcon#about to write, iclass 30, count 0 2006.201.03:37:49.87#ibcon#wrote, iclass 30, count 0 2006.201.03:37:49.87#ibcon#about to read 3, iclass 30, count 0 2006.201.03:37:49.89#ibcon#read 3, iclass 30, count 0 2006.201.03:37:49.89#ibcon#about to read 4, iclass 30, count 0 2006.201.03:37:49.89#ibcon#read 4, iclass 30, count 0 2006.201.03:37:49.89#ibcon#about to read 5, iclass 30, count 0 2006.201.03:37:49.89#ibcon#read 5, iclass 30, count 0 2006.201.03:37:49.89#ibcon#about to read 6, iclass 30, count 0 2006.201.03:37:49.89#ibcon#read 6, iclass 30, count 0 2006.201.03:37:49.89#ibcon#end of sib2, iclass 30, count 0 2006.201.03:37:49.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:37:49.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:37:49.89#ibcon#[27=USB\r\n] 2006.201.03:37:49.89#ibcon#*before write, iclass 30, count 0 2006.201.03:37:49.89#ibcon#enter sib2, iclass 30, count 0 2006.201.03:37:49.89#ibcon#flushed, iclass 30, count 0 2006.201.03:37:49.89#ibcon#about to write, iclass 30, count 0 2006.201.03:37:49.89#ibcon#wrote, iclass 30, count 0 2006.201.03:37:49.89#ibcon#about to read 3, iclass 30, count 0 2006.201.03:37:49.92#ibcon#read 3, iclass 30, count 0 2006.201.03:37:49.92#ibcon#about to read 4, iclass 30, count 0 2006.201.03:37:49.92#ibcon#read 4, iclass 30, count 0 2006.201.03:37:49.92#ibcon#about to read 5, iclass 30, count 0 2006.201.03:37:49.92#ibcon#read 5, iclass 30, count 0 2006.201.03:37:49.92#ibcon#about to read 6, iclass 30, count 0 2006.201.03:37:49.92#ibcon#read 6, iclass 30, count 0 2006.201.03:37:49.92#ibcon#end of sib2, iclass 30, count 0 2006.201.03:37:49.92#ibcon#*after write, iclass 30, count 0 2006.201.03:37:49.92#ibcon#*before return 0, iclass 30, count 0 2006.201.03:37:49.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:49.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:37:49.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:37:49.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:37:49.92$vck44/vblo=8,744.99 2006.201.03:37:49.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.03:37:49.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.03:37:49.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:37:49.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:49.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:49.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:49.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:37:49.92#ibcon#first serial, iclass 32, count 0 2006.201.03:37:49.92#ibcon#enter sib2, iclass 32, count 0 2006.201.03:37:49.92#ibcon#flushed, iclass 32, count 0 2006.201.03:37:49.92#ibcon#about to write, iclass 32, count 0 2006.201.03:37:49.92#ibcon#wrote, iclass 32, count 0 2006.201.03:37:49.92#ibcon#about to read 3, iclass 32, count 0 2006.201.03:37:49.94#ibcon#read 3, iclass 32, count 0 2006.201.03:37:49.94#ibcon#about to read 4, iclass 32, count 0 2006.201.03:37:49.94#ibcon#read 4, iclass 32, count 0 2006.201.03:37:49.94#ibcon#about to read 5, iclass 32, count 0 2006.201.03:37:49.94#ibcon#read 5, iclass 32, count 0 2006.201.03:37:49.94#ibcon#about to read 6, iclass 32, count 0 2006.201.03:37:49.94#ibcon#read 6, iclass 32, count 0 2006.201.03:37:49.94#ibcon#end of sib2, iclass 32, count 0 2006.201.03:37:49.94#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:37:49.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:37:49.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:37:49.94#ibcon#*before write, iclass 32, count 0 2006.201.03:37:49.94#ibcon#enter sib2, iclass 32, count 0 2006.201.03:37:49.94#ibcon#flushed, iclass 32, count 0 2006.201.03:37:49.94#ibcon#about to write, iclass 32, count 0 2006.201.03:37:49.94#ibcon#wrote, iclass 32, count 0 2006.201.03:37:49.94#ibcon#about to read 3, iclass 32, count 0 2006.201.03:37:49.98#ibcon#read 3, iclass 32, count 0 2006.201.03:37:49.98#ibcon#about to read 4, iclass 32, count 0 2006.201.03:37:49.98#ibcon#read 4, iclass 32, count 0 2006.201.03:37:49.98#ibcon#about to read 5, iclass 32, count 0 2006.201.03:37:49.98#ibcon#read 5, iclass 32, count 0 2006.201.03:37:49.98#ibcon#about to read 6, iclass 32, count 0 2006.201.03:37:49.98#ibcon#read 6, iclass 32, count 0 2006.201.03:37:49.98#ibcon#end of sib2, iclass 32, count 0 2006.201.03:37:49.98#ibcon#*after write, iclass 32, count 0 2006.201.03:37:49.98#ibcon#*before return 0, iclass 32, count 0 2006.201.03:37:49.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:49.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:37:49.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:37:49.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:37:49.98$vck44/vb=8,4 2006.201.03:37:49.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.03:37:49.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.03:37:49.98#ibcon#ireg 11 cls_cnt 2 2006.201.03:37:49.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:50.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:50.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:50.04#ibcon#enter wrdev, iclass 34, count 2 2006.201.03:37:50.04#ibcon#first serial, iclass 34, count 2 2006.201.03:37:50.04#ibcon#enter sib2, iclass 34, count 2 2006.201.03:37:50.04#ibcon#flushed, iclass 34, count 2 2006.201.03:37:50.04#ibcon#about to write, iclass 34, count 2 2006.201.03:37:50.04#ibcon#wrote, iclass 34, count 2 2006.201.03:37:50.04#ibcon#about to read 3, iclass 34, count 2 2006.201.03:37:50.06#ibcon#read 3, iclass 34, count 2 2006.201.03:37:50.06#ibcon#about to read 4, iclass 34, count 2 2006.201.03:37:50.06#ibcon#read 4, iclass 34, count 2 2006.201.03:37:50.06#ibcon#about to read 5, iclass 34, count 2 2006.201.03:37:50.06#ibcon#read 5, iclass 34, count 2 2006.201.03:37:50.06#ibcon#about to read 6, iclass 34, count 2 2006.201.03:37:50.06#ibcon#read 6, iclass 34, count 2 2006.201.03:37:50.06#ibcon#end of sib2, iclass 34, count 2 2006.201.03:37:50.06#ibcon#*mode == 0, iclass 34, count 2 2006.201.03:37:50.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.03:37:50.06#ibcon#[27=AT08-04\r\n] 2006.201.03:37:50.06#ibcon#*before write, iclass 34, count 2 2006.201.03:37:50.06#ibcon#enter sib2, iclass 34, count 2 2006.201.03:37:50.06#ibcon#flushed, iclass 34, count 2 2006.201.03:37:50.06#ibcon#about to write, iclass 34, count 2 2006.201.03:37:50.06#ibcon#wrote, iclass 34, count 2 2006.201.03:37:50.06#ibcon#about to read 3, iclass 34, count 2 2006.201.03:37:50.09#ibcon#read 3, iclass 34, count 2 2006.201.03:37:50.09#ibcon#about to read 4, iclass 34, count 2 2006.201.03:37:50.09#ibcon#read 4, iclass 34, count 2 2006.201.03:37:50.09#ibcon#about to read 5, iclass 34, count 2 2006.201.03:37:50.09#ibcon#read 5, iclass 34, count 2 2006.201.03:37:50.09#ibcon#about to read 6, iclass 34, count 2 2006.201.03:37:50.09#ibcon#read 6, iclass 34, count 2 2006.201.03:37:50.09#ibcon#end of sib2, iclass 34, count 2 2006.201.03:37:50.09#ibcon#*after write, iclass 34, count 2 2006.201.03:37:50.09#ibcon#*before return 0, iclass 34, count 2 2006.201.03:37:50.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:50.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:37:50.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.03:37:50.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:37:50.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:50.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:50.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:50.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:37:50.21#ibcon#first serial, iclass 34, count 0 2006.201.03:37:50.21#ibcon#enter sib2, iclass 34, count 0 2006.201.03:37:50.21#ibcon#flushed, iclass 34, count 0 2006.201.03:37:50.21#ibcon#about to write, iclass 34, count 0 2006.201.03:37:50.21#ibcon#wrote, iclass 34, count 0 2006.201.03:37:50.21#ibcon#about to read 3, iclass 34, count 0 2006.201.03:37:50.23#ibcon#read 3, iclass 34, count 0 2006.201.03:37:50.23#ibcon#about to read 4, iclass 34, count 0 2006.201.03:37:50.23#ibcon#read 4, iclass 34, count 0 2006.201.03:37:50.23#ibcon#about to read 5, iclass 34, count 0 2006.201.03:37:50.23#ibcon#read 5, iclass 34, count 0 2006.201.03:37:50.23#ibcon#about to read 6, iclass 34, count 0 2006.201.03:37:50.23#ibcon#read 6, iclass 34, count 0 2006.201.03:37:50.23#ibcon#end of sib2, iclass 34, count 0 2006.201.03:37:50.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:37:50.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:37:50.23#ibcon#[27=USB\r\n] 2006.201.03:37:50.23#ibcon#*before write, iclass 34, count 0 2006.201.03:37:50.23#ibcon#enter sib2, iclass 34, count 0 2006.201.03:37:50.23#ibcon#flushed, iclass 34, count 0 2006.201.03:37:50.23#ibcon#about to write, iclass 34, count 0 2006.201.03:37:50.23#ibcon#wrote, iclass 34, count 0 2006.201.03:37:50.23#ibcon#about to read 3, iclass 34, count 0 2006.201.03:37:50.26#ibcon#read 3, iclass 34, count 0 2006.201.03:37:50.26#ibcon#about to read 4, iclass 34, count 0 2006.201.03:37:50.26#ibcon#read 4, iclass 34, count 0 2006.201.03:37:50.26#ibcon#about to read 5, iclass 34, count 0 2006.201.03:37:50.26#ibcon#read 5, iclass 34, count 0 2006.201.03:37:50.26#ibcon#about to read 6, iclass 34, count 0 2006.201.03:37:50.26#ibcon#read 6, iclass 34, count 0 2006.201.03:37:50.26#ibcon#end of sib2, iclass 34, count 0 2006.201.03:37:50.26#ibcon#*after write, iclass 34, count 0 2006.201.03:37:50.26#ibcon#*before return 0, iclass 34, count 0 2006.201.03:37:50.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:50.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:37:50.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:37:50.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:37:50.26$vck44/vabw=wide 2006.201.03:37:50.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.03:37:50.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.03:37:50.26#ibcon#ireg 8 cls_cnt 0 2006.201.03:37:50.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:50.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:50.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:50.26#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:37:50.26#ibcon#first serial, iclass 36, count 0 2006.201.03:37:50.26#ibcon#enter sib2, iclass 36, count 0 2006.201.03:37:50.26#ibcon#flushed, iclass 36, count 0 2006.201.03:37:50.26#ibcon#about to write, iclass 36, count 0 2006.201.03:37:50.26#ibcon#wrote, iclass 36, count 0 2006.201.03:37:50.26#ibcon#about to read 3, iclass 36, count 0 2006.201.03:37:50.28#ibcon#read 3, iclass 36, count 0 2006.201.03:37:50.28#ibcon#about to read 4, iclass 36, count 0 2006.201.03:37:50.28#ibcon#read 4, iclass 36, count 0 2006.201.03:37:50.28#ibcon#about to read 5, iclass 36, count 0 2006.201.03:37:50.28#ibcon#read 5, iclass 36, count 0 2006.201.03:37:50.28#ibcon#about to read 6, iclass 36, count 0 2006.201.03:37:50.28#ibcon#read 6, iclass 36, count 0 2006.201.03:37:50.28#ibcon#end of sib2, iclass 36, count 0 2006.201.03:37:50.28#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:37:50.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:37:50.28#ibcon#[25=BW32\r\n] 2006.201.03:37:50.28#ibcon#*before write, iclass 36, count 0 2006.201.03:37:50.28#ibcon#enter sib2, iclass 36, count 0 2006.201.03:37:50.28#ibcon#flushed, iclass 36, count 0 2006.201.03:37:50.28#ibcon#about to write, iclass 36, count 0 2006.201.03:37:50.28#ibcon#wrote, iclass 36, count 0 2006.201.03:37:50.28#ibcon#about to read 3, iclass 36, count 0 2006.201.03:37:50.31#ibcon#read 3, iclass 36, count 0 2006.201.03:37:50.31#ibcon#about to read 4, iclass 36, count 0 2006.201.03:37:50.31#ibcon#read 4, iclass 36, count 0 2006.201.03:37:50.31#ibcon#about to read 5, iclass 36, count 0 2006.201.03:37:50.31#ibcon#read 5, iclass 36, count 0 2006.201.03:37:50.31#ibcon#about to read 6, iclass 36, count 0 2006.201.03:37:50.31#ibcon#read 6, iclass 36, count 0 2006.201.03:37:50.31#ibcon#end of sib2, iclass 36, count 0 2006.201.03:37:50.31#ibcon#*after write, iclass 36, count 0 2006.201.03:37:50.31#ibcon#*before return 0, iclass 36, count 0 2006.201.03:37:50.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:50.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:37:50.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:37:50.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:37:50.31$vck44/vbbw=wide 2006.201.03:37:50.31#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.03:37:50.31#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.03:37:50.31#ibcon#ireg 8 cls_cnt 0 2006.201.03:37:50.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:37:50.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:37:50.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:37:50.38#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:37:50.38#ibcon#first serial, iclass 38, count 0 2006.201.03:37:50.38#ibcon#enter sib2, iclass 38, count 0 2006.201.03:37:50.38#ibcon#flushed, iclass 38, count 0 2006.201.03:37:50.38#ibcon#about to write, iclass 38, count 0 2006.201.03:37:50.38#ibcon#wrote, iclass 38, count 0 2006.201.03:37:50.38#ibcon#about to read 3, iclass 38, count 0 2006.201.03:37:50.40#ibcon#read 3, iclass 38, count 0 2006.201.03:37:50.40#ibcon#about to read 4, iclass 38, count 0 2006.201.03:37:50.40#ibcon#read 4, iclass 38, count 0 2006.201.03:37:50.40#ibcon#about to read 5, iclass 38, count 0 2006.201.03:37:50.40#ibcon#read 5, iclass 38, count 0 2006.201.03:37:50.40#ibcon#about to read 6, iclass 38, count 0 2006.201.03:37:50.40#ibcon#read 6, iclass 38, count 0 2006.201.03:37:50.40#ibcon#end of sib2, iclass 38, count 0 2006.201.03:37:50.40#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:37:50.40#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:37:50.40#ibcon#[27=BW32\r\n] 2006.201.03:37:50.40#ibcon#*before write, iclass 38, count 0 2006.201.03:37:50.40#ibcon#enter sib2, iclass 38, count 0 2006.201.03:37:50.40#ibcon#flushed, iclass 38, count 0 2006.201.03:37:50.40#ibcon#about to write, iclass 38, count 0 2006.201.03:37:50.40#ibcon#wrote, iclass 38, count 0 2006.201.03:37:50.40#ibcon#about to read 3, iclass 38, count 0 2006.201.03:37:50.43#ibcon#read 3, iclass 38, count 0 2006.201.03:37:50.43#ibcon#about to read 4, iclass 38, count 0 2006.201.03:37:50.43#ibcon#read 4, iclass 38, count 0 2006.201.03:37:50.43#ibcon#about to read 5, iclass 38, count 0 2006.201.03:37:50.43#ibcon#read 5, iclass 38, count 0 2006.201.03:37:50.43#ibcon#about to read 6, iclass 38, count 0 2006.201.03:37:50.43#ibcon#read 6, iclass 38, count 0 2006.201.03:37:50.43#ibcon#end of sib2, iclass 38, count 0 2006.201.03:37:50.43#ibcon#*after write, iclass 38, count 0 2006.201.03:37:50.43#ibcon#*before return 0, iclass 38, count 0 2006.201.03:37:50.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:37:50.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:37:50.43#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:37:50.43#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:37:50.43$setupk4/ifdk4 2006.201.03:37:50.43$ifdk4/lo= 2006.201.03:37:50.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:37:50.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:37:50.43$ifdk4/patch= 2006.201.03:37:50.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:37:50.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:37:50.43$setupk4/!*+20s 2006.201.03:37:59.67#abcon#<5=/04 2.1 4.3 23.05 911004.5\r\n> 2006.201.03:37:59.69#abcon#{5=INTERFACE CLEAR} 2006.201.03:37:59.76#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:38:04.90$setupk4/"tpicd 2006.201.03:38:04.90$setupk4/echo=off 2006.201.03:38:04.90$setupk4/xlog=off 2006.201.03:38:04.90:!2006.201.03:38:25 2006.201.03:38:07.14#trakl#Source acquired 2006.201.03:38:07.14#flagr#flagr/antenna,acquired 2006.201.03:38:25.00:preob 2006.201.03:38:26.14/onsource/TRACKING 2006.201.03:38:26.14:!2006.201.03:38:35 2006.201.03:38:35.00:"tape 2006.201.03:38:35.00:"st=record 2006.201.03:38:35.00:data_valid=on 2006.201.03:38:35.00:midob 2006.201.03:38:35.13/onsource/TRACKING 2006.201.03:38:35.13/wx/23.05,1004.5,91 2006.201.03:38:35.32/cable/+6.4673E-03 2006.201.03:38:36.41/va/01,08,usb,yes,39,42 2006.201.03:38:36.41/va/02,07,usb,yes,42,43 2006.201.03:38:36.41/va/03,08,usb,yes,39,40 2006.201.03:38:36.41/va/04,07,usb,yes,44,46 2006.201.03:38:36.41/va/05,04,usb,yes,39,40 2006.201.03:38:36.41/va/06,05,usb,yes,39,39 2006.201.03:38:36.41/va/07,05,usb,yes,38,40 2006.201.03:38:36.41/va/08,04,usb,yes,38,45 2006.201.03:38:36.64/valo/01,524.99,yes,locked 2006.201.03:38:36.64/valo/02,534.99,yes,locked 2006.201.03:38:36.64/valo/03,564.99,yes,locked 2006.201.03:38:36.64/valo/04,624.99,yes,locked 2006.201.03:38:36.64/valo/05,734.99,yes,locked 2006.201.03:38:36.64/valo/06,814.99,yes,locked 2006.201.03:38:36.64/valo/07,864.99,yes,locked 2006.201.03:38:36.64/valo/08,884.99,yes,locked 2006.201.03:38:37.73/vb/01,04,usb,yes,34,32 2006.201.03:38:37.73/vb/02,05,usb,yes,33,32 2006.201.03:38:37.73/vb/03,04,usb,yes,34,37 2006.201.03:38:37.73/vb/04,05,usb,yes,34,33 2006.201.03:38:37.73/vb/05,04,usb,yes,30,33 2006.201.03:38:37.73/vb/06,04,usb,yes,36,31 2006.201.03:38:37.73/vb/07,04,usb,yes,35,35 2006.201.03:38:37.73/vb/08,04,usb,yes,32,36 2006.201.03:38:37.96/vblo/01,629.99,yes,locked 2006.201.03:38:37.96/vblo/02,634.99,yes,locked 2006.201.03:38:37.96/vblo/03,649.99,yes,locked 2006.201.03:38:37.96/vblo/04,679.99,yes,locked 2006.201.03:38:37.96/vblo/05,709.99,yes,locked 2006.201.03:38:37.96/vblo/06,719.99,yes,locked 2006.201.03:38:37.96/vblo/07,734.99,yes,locked 2006.201.03:38:37.96/vblo/08,744.99,yes,locked 2006.201.03:38:38.11/vabw/8 2006.201.03:38:38.26/vbbw/8 2006.201.03:38:38.35/xfe/off,on,15.0 2006.201.03:38:38.74/ifatt/23,28,28,28 2006.201.03:38:39.05/fmout-gps/S +4.52E-07 2006.201.03:38:39.12:!2006.201.03:41:25 2006.201.03:41:25.00:data_valid=off 2006.201.03:41:25.00:"et 2006.201.03:41:25.00:!+3s 2006.201.03:41:28.02:"tape 2006.201.03:41:28.02:postob 2006.201.03:41:28.15/cable/+6.4657E-03 2006.201.03:41:28.15/wx/23.03,1004.5,92 2006.201.03:41:28.22/fmout-gps/S +4.53E-07 2006.201.03:41:28.22:scan_name=201-0344,jd0607,50 2006.201.03:41:28.23:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.201.03:41:29.14#flagr#flagr/antenna,new-source 2006.201.03:41:29.14:checkk5 2006.201.03:41:29.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:41:29.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:41:30.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:41:30.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:41:31.01/chk_obsdata//k5ts1/T2010338??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.03:41:31.38/chk_obsdata//k5ts2/T2010338??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.03:41:31.75/chk_obsdata//k5ts3/T2010338??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.03:41:32.11/chk_obsdata//k5ts4/T2010338??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.03:41:32.81/k5log//k5ts1_log_newline 2006.201.03:41:33.50/k5log//k5ts2_log_newline 2006.201.03:41:34.19/k5log//k5ts3_log_newline 2006.201.03:41:34.87/k5log//k5ts4_log_newline 2006.201.03:41:34.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:41:34.89:setupk4=1 2006.201.03:41:34.89$setupk4/echo=on 2006.201.03:41:34.90$setupk4/pcalon 2006.201.03:41:34.90$pcalon/"no phase cal control is implemented here 2006.201.03:41:34.90$setupk4/"tpicd=stop 2006.201.03:41:34.90$setupk4/"rec=synch_on 2006.201.03:41:34.90$setupk4/"rec_mode=128 2006.201.03:41:34.90$setupk4/!* 2006.201.03:41:34.90$setupk4/recpk4 2006.201.03:41:34.90$recpk4/recpatch= 2006.201.03:41:34.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:41:34.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:41:34.90$setupk4/vck44 2006.201.03:41:34.90$vck44/valo=1,524.99 2006.201.03:41:34.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.03:41:34.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.03:41:34.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:34.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:34.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:34.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:34.90#ibcon#enter wrdev, iclass 23, count 0 2006.201.03:41:34.90#ibcon#first serial, iclass 23, count 0 2006.201.03:41:34.90#ibcon#enter sib2, iclass 23, count 0 2006.201.03:41:34.90#ibcon#flushed, iclass 23, count 0 2006.201.03:41:34.90#ibcon#about to write, iclass 23, count 0 2006.201.03:41:34.90#ibcon#wrote, iclass 23, count 0 2006.201.03:41:34.90#ibcon#about to read 3, iclass 23, count 0 2006.201.03:41:34.94#ibcon#read 3, iclass 23, count 0 2006.201.03:41:34.94#ibcon#about to read 4, iclass 23, count 0 2006.201.03:41:34.94#ibcon#read 4, iclass 23, count 0 2006.201.03:41:34.94#ibcon#about to read 5, iclass 23, count 0 2006.201.03:41:34.94#ibcon#read 5, iclass 23, count 0 2006.201.03:41:34.94#ibcon#about to read 6, iclass 23, count 0 2006.201.03:41:34.94#ibcon#read 6, iclass 23, count 0 2006.201.03:41:34.94#ibcon#end of sib2, iclass 23, count 0 2006.201.03:41:34.94#ibcon#*mode == 0, iclass 23, count 0 2006.201.03:41:34.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.03:41:34.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:41:34.94#ibcon#*before write, iclass 23, count 0 2006.201.03:41:34.94#ibcon#enter sib2, iclass 23, count 0 2006.201.03:41:34.94#ibcon#flushed, iclass 23, count 0 2006.201.03:41:34.94#ibcon#about to write, iclass 23, count 0 2006.201.03:41:34.94#ibcon#wrote, iclass 23, count 0 2006.201.03:41:34.94#ibcon#about to read 3, iclass 23, count 0 2006.201.03:41:34.99#ibcon#read 3, iclass 23, count 0 2006.201.03:41:34.99#ibcon#about to read 4, iclass 23, count 0 2006.201.03:41:34.99#ibcon#read 4, iclass 23, count 0 2006.201.03:41:34.99#ibcon#about to read 5, iclass 23, count 0 2006.201.03:41:34.99#ibcon#read 5, iclass 23, count 0 2006.201.03:41:34.99#ibcon#about to read 6, iclass 23, count 0 2006.201.03:41:34.99#ibcon#read 6, iclass 23, count 0 2006.201.03:41:34.99#ibcon#end of sib2, iclass 23, count 0 2006.201.03:41:34.99#ibcon#*after write, iclass 23, count 0 2006.201.03:41:34.99#ibcon#*before return 0, iclass 23, count 0 2006.201.03:41:34.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:34.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:34.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.03:41:34.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.03:41:34.99$vck44/va=1,8 2006.201.03:41:34.99#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.03:41:34.99#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.03:41:34.99#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:34.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:34.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:34.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:34.99#ibcon#enter wrdev, iclass 25, count 2 2006.201.03:41:34.99#ibcon#first serial, iclass 25, count 2 2006.201.03:41:34.99#ibcon#enter sib2, iclass 25, count 2 2006.201.03:41:34.99#ibcon#flushed, iclass 25, count 2 2006.201.03:41:34.99#ibcon#about to write, iclass 25, count 2 2006.201.03:41:34.99#ibcon#wrote, iclass 25, count 2 2006.201.03:41:34.99#ibcon#about to read 3, iclass 25, count 2 2006.201.03:41:35.01#ibcon#read 3, iclass 25, count 2 2006.201.03:41:35.01#ibcon#about to read 4, iclass 25, count 2 2006.201.03:41:35.01#ibcon#read 4, iclass 25, count 2 2006.201.03:41:35.01#ibcon#about to read 5, iclass 25, count 2 2006.201.03:41:35.01#ibcon#read 5, iclass 25, count 2 2006.201.03:41:35.01#ibcon#about to read 6, iclass 25, count 2 2006.201.03:41:35.01#ibcon#read 6, iclass 25, count 2 2006.201.03:41:35.01#ibcon#end of sib2, iclass 25, count 2 2006.201.03:41:35.01#ibcon#*mode == 0, iclass 25, count 2 2006.201.03:41:35.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.03:41:35.01#ibcon#[25=AT01-08\r\n] 2006.201.03:41:35.01#ibcon#*before write, iclass 25, count 2 2006.201.03:41:35.01#ibcon#enter sib2, iclass 25, count 2 2006.201.03:41:35.01#ibcon#flushed, iclass 25, count 2 2006.201.03:41:35.01#ibcon#about to write, iclass 25, count 2 2006.201.03:41:35.01#ibcon#wrote, iclass 25, count 2 2006.201.03:41:35.01#ibcon#about to read 3, iclass 25, count 2 2006.201.03:41:35.04#ibcon#read 3, iclass 25, count 2 2006.201.03:41:35.04#ibcon#about to read 4, iclass 25, count 2 2006.201.03:41:35.04#ibcon#read 4, iclass 25, count 2 2006.201.03:41:35.04#ibcon#about to read 5, iclass 25, count 2 2006.201.03:41:35.04#ibcon#read 5, iclass 25, count 2 2006.201.03:41:35.04#ibcon#about to read 6, iclass 25, count 2 2006.201.03:41:35.04#ibcon#read 6, iclass 25, count 2 2006.201.03:41:35.04#ibcon#end of sib2, iclass 25, count 2 2006.201.03:41:35.04#ibcon#*after write, iclass 25, count 2 2006.201.03:41:35.04#ibcon#*before return 0, iclass 25, count 2 2006.201.03:41:35.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:35.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:35.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.03:41:35.04#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:35.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:35.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:35.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:35.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.03:41:35.16#ibcon#first serial, iclass 25, count 0 2006.201.03:41:35.16#ibcon#enter sib2, iclass 25, count 0 2006.201.03:41:35.16#ibcon#flushed, iclass 25, count 0 2006.201.03:41:35.16#ibcon#about to write, iclass 25, count 0 2006.201.03:41:35.16#ibcon#wrote, iclass 25, count 0 2006.201.03:41:35.16#ibcon#about to read 3, iclass 25, count 0 2006.201.03:41:35.18#ibcon#read 3, iclass 25, count 0 2006.201.03:41:35.18#ibcon#about to read 4, iclass 25, count 0 2006.201.03:41:35.18#ibcon#read 4, iclass 25, count 0 2006.201.03:41:35.18#ibcon#about to read 5, iclass 25, count 0 2006.201.03:41:35.18#ibcon#read 5, iclass 25, count 0 2006.201.03:41:35.18#ibcon#about to read 6, iclass 25, count 0 2006.201.03:41:35.18#ibcon#read 6, iclass 25, count 0 2006.201.03:41:35.18#ibcon#end of sib2, iclass 25, count 0 2006.201.03:41:35.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.03:41:35.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.03:41:35.18#ibcon#[25=USB\r\n] 2006.201.03:41:35.18#ibcon#*before write, iclass 25, count 0 2006.201.03:41:35.18#ibcon#enter sib2, iclass 25, count 0 2006.201.03:41:35.18#ibcon#flushed, iclass 25, count 0 2006.201.03:41:35.18#ibcon#about to write, iclass 25, count 0 2006.201.03:41:35.18#ibcon#wrote, iclass 25, count 0 2006.201.03:41:35.18#ibcon#about to read 3, iclass 25, count 0 2006.201.03:41:35.21#ibcon#read 3, iclass 25, count 0 2006.201.03:41:35.21#ibcon#about to read 4, iclass 25, count 0 2006.201.03:41:35.21#ibcon#read 4, iclass 25, count 0 2006.201.03:41:35.21#ibcon#about to read 5, iclass 25, count 0 2006.201.03:41:35.21#ibcon#read 5, iclass 25, count 0 2006.201.03:41:35.21#ibcon#about to read 6, iclass 25, count 0 2006.201.03:41:35.21#ibcon#read 6, iclass 25, count 0 2006.201.03:41:35.21#ibcon#end of sib2, iclass 25, count 0 2006.201.03:41:35.21#ibcon#*after write, iclass 25, count 0 2006.201.03:41:35.21#ibcon#*before return 0, iclass 25, count 0 2006.201.03:41:35.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:35.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:35.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.03:41:35.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.03:41:35.21$vck44/valo=2,534.99 2006.201.03:41:35.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.03:41:35.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.03:41:35.21#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:35.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:35.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:35.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:35.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.03:41:35.21#ibcon#first serial, iclass 27, count 0 2006.201.03:41:35.21#ibcon#enter sib2, iclass 27, count 0 2006.201.03:41:35.21#ibcon#flushed, iclass 27, count 0 2006.201.03:41:35.21#ibcon#about to write, iclass 27, count 0 2006.201.03:41:35.21#ibcon#wrote, iclass 27, count 0 2006.201.03:41:35.21#ibcon#about to read 3, iclass 27, count 0 2006.201.03:41:35.23#ibcon#read 3, iclass 27, count 0 2006.201.03:41:35.23#ibcon#about to read 4, iclass 27, count 0 2006.201.03:41:35.23#ibcon#read 4, iclass 27, count 0 2006.201.03:41:35.23#ibcon#about to read 5, iclass 27, count 0 2006.201.03:41:35.23#ibcon#read 5, iclass 27, count 0 2006.201.03:41:35.23#ibcon#about to read 6, iclass 27, count 0 2006.201.03:41:35.23#ibcon#read 6, iclass 27, count 0 2006.201.03:41:35.23#ibcon#end of sib2, iclass 27, count 0 2006.201.03:41:35.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.03:41:35.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.03:41:35.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:41:35.23#ibcon#*before write, iclass 27, count 0 2006.201.03:41:35.23#ibcon#enter sib2, iclass 27, count 0 2006.201.03:41:35.23#ibcon#flushed, iclass 27, count 0 2006.201.03:41:35.23#ibcon#about to write, iclass 27, count 0 2006.201.03:41:35.23#ibcon#wrote, iclass 27, count 0 2006.201.03:41:35.23#ibcon#about to read 3, iclass 27, count 0 2006.201.03:41:35.27#ibcon#read 3, iclass 27, count 0 2006.201.03:41:35.27#ibcon#about to read 4, iclass 27, count 0 2006.201.03:41:35.27#ibcon#read 4, iclass 27, count 0 2006.201.03:41:35.27#ibcon#about to read 5, iclass 27, count 0 2006.201.03:41:35.27#ibcon#read 5, iclass 27, count 0 2006.201.03:41:35.27#ibcon#about to read 6, iclass 27, count 0 2006.201.03:41:35.27#ibcon#read 6, iclass 27, count 0 2006.201.03:41:35.27#ibcon#end of sib2, iclass 27, count 0 2006.201.03:41:35.27#ibcon#*after write, iclass 27, count 0 2006.201.03:41:35.27#ibcon#*before return 0, iclass 27, count 0 2006.201.03:41:35.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:35.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:35.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.03:41:35.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.03:41:35.27$vck44/va=2,7 2006.201.03:41:35.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.03:41:35.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.03:41:35.27#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:35.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:35.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:35.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:35.33#ibcon#enter wrdev, iclass 29, count 2 2006.201.03:41:35.33#ibcon#first serial, iclass 29, count 2 2006.201.03:41:35.33#ibcon#enter sib2, iclass 29, count 2 2006.201.03:41:35.33#ibcon#flushed, iclass 29, count 2 2006.201.03:41:35.33#ibcon#about to write, iclass 29, count 2 2006.201.03:41:35.33#ibcon#wrote, iclass 29, count 2 2006.201.03:41:35.33#ibcon#about to read 3, iclass 29, count 2 2006.201.03:41:35.35#ibcon#read 3, iclass 29, count 2 2006.201.03:41:35.35#ibcon#about to read 4, iclass 29, count 2 2006.201.03:41:35.35#ibcon#read 4, iclass 29, count 2 2006.201.03:41:35.35#ibcon#about to read 5, iclass 29, count 2 2006.201.03:41:35.35#ibcon#read 5, iclass 29, count 2 2006.201.03:41:35.35#ibcon#about to read 6, iclass 29, count 2 2006.201.03:41:35.35#ibcon#read 6, iclass 29, count 2 2006.201.03:41:35.35#ibcon#end of sib2, iclass 29, count 2 2006.201.03:41:35.35#ibcon#*mode == 0, iclass 29, count 2 2006.201.03:41:35.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.03:41:35.35#ibcon#[25=AT02-07\r\n] 2006.201.03:41:35.35#ibcon#*before write, iclass 29, count 2 2006.201.03:41:35.35#ibcon#enter sib2, iclass 29, count 2 2006.201.03:41:35.35#ibcon#flushed, iclass 29, count 2 2006.201.03:41:35.35#ibcon#about to write, iclass 29, count 2 2006.201.03:41:35.35#ibcon#wrote, iclass 29, count 2 2006.201.03:41:35.35#ibcon#about to read 3, iclass 29, count 2 2006.201.03:41:35.38#ibcon#read 3, iclass 29, count 2 2006.201.03:41:35.38#ibcon#about to read 4, iclass 29, count 2 2006.201.03:41:35.38#ibcon#read 4, iclass 29, count 2 2006.201.03:41:35.38#ibcon#about to read 5, iclass 29, count 2 2006.201.03:41:35.38#ibcon#read 5, iclass 29, count 2 2006.201.03:41:35.38#ibcon#about to read 6, iclass 29, count 2 2006.201.03:41:35.38#ibcon#read 6, iclass 29, count 2 2006.201.03:41:35.38#ibcon#end of sib2, iclass 29, count 2 2006.201.03:41:35.38#ibcon#*after write, iclass 29, count 2 2006.201.03:41:35.38#ibcon#*before return 0, iclass 29, count 2 2006.201.03:41:35.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:35.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:35.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.03:41:35.38#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:35.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:35.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:35.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:35.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.03:41:35.50#ibcon#first serial, iclass 29, count 0 2006.201.03:41:35.50#ibcon#enter sib2, iclass 29, count 0 2006.201.03:41:35.50#ibcon#flushed, iclass 29, count 0 2006.201.03:41:35.50#ibcon#about to write, iclass 29, count 0 2006.201.03:41:35.50#ibcon#wrote, iclass 29, count 0 2006.201.03:41:35.50#ibcon#about to read 3, iclass 29, count 0 2006.201.03:41:35.52#ibcon#read 3, iclass 29, count 0 2006.201.03:41:35.52#ibcon#about to read 4, iclass 29, count 0 2006.201.03:41:35.52#ibcon#read 4, iclass 29, count 0 2006.201.03:41:35.52#ibcon#about to read 5, iclass 29, count 0 2006.201.03:41:35.52#ibcon#read 5, iclass 29, count 0 2006.201.03:41:35.52#ibcon#about to read 6, iclass 29, count 0 2006.201.03:41:35.52#ibcon#read 6, iclass 29, count 0 2006.201.03:41:35.52#ibcon#end of sib2, iclass 29, count 0 2006.201.03:41:35.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.03:41:35.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.03:41:35.52#ibcon#[25=USB\r\n] 2006.201.03:41:35.52#ibcon#*before write, iclass 29, count 0 2006.201.03:41:35.52#ibcon#enter sib2, iclass 29, count 0 2006.201.03:41:35.52#ibcon#flushed, iclass 29, count 0 2006.201.03:41:35.52#ibcon#about to write, iclass 29, count 0 2006.201.03:41:35.52#ibcon#wrote, iclass 29, count 0 2006.201.03:41:35.52#ibcon#about to read 3, iclass 29, count 0 2006.201.03:41:35.55#ibcon#read 3, iclass 29, count 0 2006.201.03:41:35.55#ibcon#about to read 4, iclass 29, count 0 2006.201.03:41:35.55#ibcon#read 4, iclass 29, count 0 2006.201.03:41:35.55#ibcon#about to read 5, iclass 29, count 0 2006.201.03:41:35.55#ibcon#read 5, iclass 29, count 0 2006.201.03:41:35.55#ibcon#about to read 6, iclass 29, count 0 2006.201.03:41:35.55#ibcon#read 6, iclass 29, count 0 2006.201.03:41:35.55#ibcon#end of sib2, iclass 29, count 0 2006.201.03:41:35.55#ibcon#*after write, iclass 29, count 0 2006.201.03:41:35.55#ibcon#*before return 0, iclass 29, count 0 2006.201.03:41:35.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:35.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:35.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.03:41:35.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.03:41:35.55$vck44/valo=3,564.99 2006.201.03:41:35.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.03:41:35.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.03:41:35.55#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:35.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:35.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:35.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:35.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.03:41:35.55#ibcon#first serial, iclass 31, count 0 2006.201.03:41:35.55#ibcon#enter sib2, iclass 31, count 0 2006.201.03:41:35.55#ibcon#flushed, iclass 31, count 0 2006.201.03:41:35.55#ibcon#about to write, iclass 31, count 0 2006.201.03:41:35.55#ibcon#wrote, iclass 31, count 0 2006.201.03:41:35.55#ibcon#about to read 3, iclass 31, count 0 2006.201.03:41:35.57#ibcon#read 3, iclass 31, count 0 2006.201.03:41:35.57#ibcon#about to read 4, iclass 31, count 0 2006.201.03:41:35.57#ibcon#read 4, iclass 31, count 0 2006.201.03:41:35.57#ibcon#about to read 5, iclass 31, count 0 2006.201.03:41:35.57#ibcon#read 5, iclass 31, count 0 2006.201.03:41:35.57#ibcon#about to read 6, iclass 31, count 0 2006.201.03:41:35.57#ibcon#read 6, iclass 31, count 0 2006.201.03:41:35.57#ibcon#end of sib2, iclass 31, count 0 2006.201.03:41:35.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.03:41:35.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.03:41:35.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:41:35.57#ibcon#*before write, iclass 31, count 0 2006.201.03:41:35.57#ibcon#enter sib2, iclass 31, count 0 2006.201.03:41:35.57#ibcon#flushed, iclass 31, count 0 2006.201.03:41:35.57#ibcon#about to write, iclass 31, count 0 2006.201.03:41:35.57#ibcon#wrote, iclass 31, count 0 2006.201.03:41:35.57#ibcon#about to read 3, iclass 31, count 0 2006.201.03:41:35.62#ibcon#read 3, iclass 31, count 0 2006.201.03:41:35.62#ibcon#about to read 4, iclass 31, count 0 2006.201.03:41:35.62#ibcon#read 4, iclass 31, count 0 2006.201.03:41:35.62#ibcon#about to read 5, iclass 31, count 0 2006.201.03:41:35.62#ibcon#read 5, iclass 31, count 0 2006.201.03:41:35.62#ibcon#about to read 6, iclass 31, count 0 2006.201.03:41:35.62#ibcon#read 6, iclass 31, count 0 2006.201.03:41:35.62#ibcon#end of sib2, iclass 31, count 0 2006.201.03:41:35.62#ibcon#*after write, iclass 31, count 0 2006.201.03:41:35.62#ibcon#*before return 0, iclass 31, count 0 2006.201.03:41:35.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:35.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:35.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.03:41:35.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.03:41:35.62$vck44/va=3,8 2006.201.03:41:35.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.03:41:35.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.03:41:35.62#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:35.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:35.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:35.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:35.67#ibcon#enter wrdev, iclass 33, count 2 2006.201.03:41:35.67#ibcon#first serial, iclass 33, count 2 2006.201.03:41:35.67#ibcon#enter sib2, iclass 33, count 2 2006.201.03:41:35.67#ibcon#flushed, iclass 33, count 2 2006.201.03:41:35.67#ibcon#about to write, iclass 33, count 2 2006.201.03:41:35.67#ibcon#wrote, iclass 33, count 2 2006.201.03:41:35.67#ibcon#about to read 3, iclass 33, count 2 2006.201.03:41:35.69#ibcon#read 3, iclass 33, count 2 2006.201.03:41:35.69#ibcon#about to read 4, iclass 33, count 2 2006.201.03:41:35.69#ibcon#read 4, iclass 33, count 2 2006.201.03:41:35.69#ibcon#about to read 5, iclass 33, count 2 2006.201.03:41:35.69#ibcon#read 5, iclass 33, count 2 2006.201.03:41:35.69#ibcon#about to read 6, iclass 33, count 2 2006.201.03:41:35.69#ibcon#read 6, iclass 33, count 2 2006.201.03:41:35.69#ibcon#end of sib2, iclass 33, count 2 2006.201.03:41:35.69#ibcon#*mode == 0, iclass 33, count 2 2006.201.03:41:35.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.03:41:35.69#ibcon#[25=AT03-08\r\n] 2006.201.03:41:35.69#ibcon#*before write, iclass 33, count 2 2006.201.03:41:35.69#ibcon#enter sib2, iclass 33, count 2 2006.201.03:41:35.69#ibcon#flushed, iclass 33, count 2 2006.201.03:41:35.69#ibcon#about to write, iclass 33, count 2 2006.201.03:41:35.69#ibcon#wrote, iclass 33, count 2 2006.201.03:41:35.69#ibcon#about to read 3, iclass 33, count 2 2006.201.03:41:35.72#ibcon#read 3, iclass 33, count 2 2006.201.03:41:35.72#ibcon#about to read 4, iclass 33, count 2 2006.201.03:41:35.72#ibcon#read 4, iclass 33, count 2 2006.201.03:41:35.72#ibcon#about to read 5, iclass 33, count 2 2006.201.03:41:35.72#ibcon#read 5, iclass 33, count 2 2006.201.03:41:35.72#ibcon#about to read 6, iclass 33, count 2 2006.201.03:41:35.72#ibcon#read 6, iclass 33, count 2 2006.201.03:41:35.72#ibcon#end of sib2, iclass 33, count 2 2006.201.03:41:35.72#ibcon#*after write, iclass 33, count 2 2006.201.03:41:35.72#ibcon#*before return 0, iclass 33, count 2 2006.201.03:41:35.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:35.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:35.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.03:41:35.72#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:35.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:35.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:35.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:35.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.03:41:35.84#ibcon#first serial, iclass 33, count 0 2006.201.03:41:35.84#ibcon#enter sib2, iclass 33, count 0 2006.201.03:41:35.84#ibcon#flushed, iclass 33, count 0 2006.201.03:41:35.84#ibcon#about to write, iclass 33, count 0 2006.201.03:41:35.84#ibcon#wrote, iclass 33, count 0 2006.201.03:41:35.84#ibcon#about to read 3, iclass 33, count 0 2006.201.03:41:35.86#ibcon#read 3, iclass 33, count 0 2006.201.03:41:35.86#ibcon#about to read 4, iclass 33, count 0 2006.201.03:41:35.86#ibcon#read 4, iclass 33, count 0 2006.201.03:41:35.86#ibcon#about to read 5, iclass 33, count 0 2006.201.03:41:35.86#ibcon#read 5, iclass 33, count 0 2006.201.03:41:35.86#ibcon#about to read 6, iclass 33, count 0 2006.201.03:41:35.86#ibcon#read 6, iclass 33, count 0 2006.201.03:41:35.86#ibcon#end of sib2, iclass 33, count 0 2006.201.03:41:35.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.03:41:35.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.03:41:35.86#ibcon#[25=USB\r\n] 2006.201.03:41:35.86#ibcon#*before write, iclass 33, count 0 2006.201.03:41:35.86#ibcon#enter sib2, iclass 33, count 0 2006.201.03:41:35.86#ibcon#flushed, iclass 33, count 0 2006.201.03:41:35.86#ibcon#about to write, iclass 33, count 0 2006.201.03:41:35.86#ibcon#wrote, iclass 33, count 0 2006.201.03:41:35.86#ibcon#about to read 3, iclass 33, count 0 2006.201.03:41:35.89#ibcon#read 3, iclass 33, count 0 2006.201.03:41:35.89#ibcon#about to read 4, iclass 33, count 0 2006.201.03:41:35.89#ibcon#read 4, iclass 33, count 0 2006.201.03:41:35.89#ibcon#about to read 5, iclass 33, count 0 2006.201.03:41:35.89#ibcon#read 5, iclass 33, count 0 2006.201.03:41:35.89#ibcon#about to read 6, iclass 33, count 0 2006.201.03:41:35.89#ibcon#read 6, iclass 33, count 0 2006.201.03:41:35.89#ibcon#end of sib2, iclass 33, count 0 2006.201.03:41:35.89#ibcon#*after write, iclass 33, count 0 2006.201.03:41:35.89#ibcon#*before return 0, iclass 33, count 0 2006.201.03:41:35.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:35.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:35.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.03:41:35.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.03:41:35.89$vck44/valo=4,624.99 2006.201.03:41:35.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.03:41:35.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.03:41:35.89#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:35.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:35.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:35.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:35.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.03:41:35.89#ibcon#first serial, iclass 35, count 0 2006.201.03:41:35.89#ibcon#enter sib2, iclass 35, count 0 2006.201.03:41:35.89#ibcon#flushed, iclass 35, count 0 2006.201.03:41:35.89#ibcon#about to write, iclass 35, count 0 2006.201.03:41:35.89#ibcon#wrote, iclass 35, count 0 2006.201.03:41:35.89#ibcon#about to read 3, iclass 35, count 0 2006.201.03:41:35.91#ibcon#read 3, iclass 35, count 0 2006.201.03:41:35.91#ibcon#about to read 4, iclass 35, count 0 2006.201.03:41:35.91#ibcon#read 4, iclass 35, count 0 2006.201.03:41:35.91#ibcon#about to read 5, iclass 35, count 0 2006.201.03:41:35.91#ibcon#read 5, iclass 35, count 0 2006.201.03:41:35.91#ibcon#about to read 6, iclass 35, count 0 2006.201.03:41:35.91#ibcon#read 6, iclass 35, count 0 2006.201.03:41:35.91#ibcon#end of sib2, iclass 35, count 0 2006.201.03:41:35.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.03:41:35.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.03:41:35.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:41:35.91#ibcon#*before write, iclass 35, count 0 2006.201.03:41:35.91#ibcon#enter sib2, iclass 35, count 0 2006.201.03:41:35.91#ibcon#flushed, iclass 35, count 0 2006.201.03:41:35.91#ibcon#about to write, iclass 35, count 0 2006.201.03:41:35.91#ibcon#wrote, iclass 35, count 0 2006.201.03:41:35.91#ibcon#about to read 3, iclass 35, count 0 2006.201.03:41:35.95#ibcon#read 3, iclass 35, count 0 2006.201.03:41:35.95#ibcon#about to read 4, iclass 35, count 0 2006.201.03:41:35.95#ibcon#read 4, iclass 35, count 0 2006.201.03:41:35.95#ibcon#about to read 5, iclass 35, count 0 2006.201.03:41:35.95#ibcon#read 5, iclass 35, count 0 2006.201.03:41:35.95#ibcon#about to read 6, iclass 35, count 0 2006.201.03:41:35.95#ibcon#read 6, iclass 35, count 0 2006.201.03:41:35.95#ibcon#end of sib2, iclass 35, count 0 2006.201.03:41:35.95#ibcon#*after write, iclass 35, count 0 2006.201.03:41:35.95#ibcon#*before return 0, iclass 35, count 0 2006.201.03:41:35.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:35.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:35.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.03:41:35.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.03:41:35.95$vck44/va=4,7 2006.201.03:41:35.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.03:41:35.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.03:41:35.95#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:35.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:36.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:36.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:36.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.03:41:36.01#ibcon#first serial, iclass 37, count 2 2006.201.03:41:36.01#ibcon#enter sib2, iclass 37, count 2 2006.201.03:41:36.01#ibcon#flushed, iclass 37, count 2 2006.201.03:41:36.01#ibcon#about to write, iclass 37, count 2 2006.201.03:41:36.01#ibcon#wrote, iclass 37, count 2 2006.201.03:41:36.01#ibcon#about to read 3, iclass 37, count 2 2006.201.03:41:36.03#ibcon#read 3, iclass 37, count 2 2006.201.03:41:36.03#ibcon#about to read 4, iclass 37, count 2 2006.201.03:41:36.03#ibcon#read 4, iclass 37, count 2 2006.201.03:41:36.03#ibcon#about to read 5, iclass 37, count 2 2006.201.03:41:36.03#ibcon#read 5, iclass 37, count 2 2006.201.03:41:36.03#ibcon#about to read 6, iclass 37, count 2 2006.201.03:41:36.03#ibcon#read 6, iclass 37, count 2 2006.201.03:41:36.03#ibcon#end of sib2, iclass 37, count 2 2006.201.03:41:36.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.03:41:36.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.03:41:36.03#ibcon#[25=AT04-07\r\n] 2006.201.03:41:36.03#ibcon#*before write, iclass 37, count 2 2006.201.03:41:36.03#ibcon#enter sib2, iclass 37, count 2 2006.201.03:41:36.03#ibcon#flushed, iclass 37, count 2 2006.201.03:41:36.03#ibcon#about to write, iclass 37, count 2 2006.201.03:41:36.03#ibcon#wrote, iclass 37, count 2 2006.201.03:41:36.03#ibcon#about to read 3, iclass 37, count 2 2006.201.03:41:36.06#ibcon#read 3, iclass 37, count 2 2006.201.03:41:36.06#ibcon#about to read 4, iclass 37, count 2 2006.201.03:41:36.06#ibcon#read 4, iclass 37, count 2 2006.201.03:41:36.06#ibcon#about to read 5, iclass 37, count 2 2006.201.03:41:36.06#ibcon#read 5, iclass 37, count 2 2006.201.03:41:36.06#ibcon#about to read 6, iclass 37, count 2 2006.201.03:41:36.06#ibcon#read 6, iclass 37, count 2 2006.201.03:41:36.06#ibcon#end of sib2, iclass 37, count 2 2006.201.03:41:36.06#ibcon#*after write, iclass 37, count 2 2006.201.03:41:36.06#ibcon#*before return 0, iclass 37, count 2 2006.201.03:41:36.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:36.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:36.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.03:41:36.06#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:36.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:36.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:36.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:36.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.03:41:36.18#ibcon#first serial, iclass 37, count 0 2006.201.03:41:36.18#ibcon#enter sib2, iclass 37, count 0 2006.201.03:41:36.18#ibcon#flushed, iclass 37, count 0 2006.201.03:41:36.18#ibcon#about to write, iclass 37, count 0 2006.201.03:41:36.18#ibcon#wrote, iclass 37, count 0 2006.201.03:41:36.18#ibcon#about to read 3, iclass 37, count 0 2006.201.03:41:36.20#ibcon#read 3, iclass 37, count 0 2006.201.03:41:36.20#ibcon#about to read 4, iclass 37, count 0 2006.201.03:41:36.20#ibcon#read 4, iclass 37, count 0 2006.201.03:41:36.20#ibcon#about to read 5, iclass 37, count 0 2006.201.03:41:36.20#ibcon#read 5, iclass 37, count 0 2006.201.03:41:36.20#ibcon#about to read 6, iclass 37, count 0 2006.201.03:41:36.20#ibcon#read 6, iclass 37, count 0 2006.201.03:41:36.20#ibcon#end of sib2, iclass 37, count 0 2006.201.03:41:36.20#ibcon#*mode == 0, iclass 37, count 0 2006.201.03:41:36.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.03:41:36.20#ibcon#[25=USB\r\n] 2006.201.03:41:36.20#ibcon#*before write, iclass 37, count 0 2006.201.03:41:36.20#ibcon#enter sib2, iclass 37, count 0 2006.201.03:41:36.20#ibcon#flushed, iclass 37, count 0 2006.201.03:41:36.20#ibcon#about to write, iclass 37, count 0 2006.201.03:41:36.20#ibcon#wrote, iclass 37, count 0 2006.201.03:41:36.20#ibcon#about to read 3, iclass 37, count 0 2006.201.03:41:36.23#ibcon#read 3, iclass 37, count 0 2006.201.03:41:36.23#ibcon#about to read 4, iclass 37, count 0 2006.201.03:41:36.23#ibcon#read 4, iclass 37, count 0 2006.201.03:41:36.23#ibcon#about to read 5, iclass 37, count 0 2006.201.03:41:36.23#ibcon#read 5, iclass 37, count 0 2006.201.03:41:36.23#ibcon#about to read 6, iclass 37, count 0 2006.201.03:41:36.23#ibcon#read 6, iclass 37, count 0 2006.201.03:41:36.23#ibcon#end of sib2, iclass 37, count 0 2006.201.03:41:36.23#ibcon#*after write, iclass 37, count 0 2006.201.03:41:36.23#ibcon#*before return 0, iclass 37, count 0 2006.201.03:41:36.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:36.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:36.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.03:41:36.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.03:41:36.23$vck44/valo=5,734.99 2006.201.03:41:36.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.03:41:36.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.03:41:36.23#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:36.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:36.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:36.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:36.23#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:41:36.23#ibcon#first serial, iclass 39, count 0 2006.201.03:41:36.23#ibcon#enter sib2, iclass 39, count 0 2006.201.03:41:36.23#ibcon#flushed, iclass 39, count 0 2006.201.03:41:36.23#ibcon#about to write, iclass 39, count 0 2006.201.03:41:36.23#ibcon#wrote, iclass 39, count 0 2006.201.03:41:36.23#ibcon#about to read 3, iclass 39, count 0 2006.201.03:41:36.25#ibcon#read 3, iclass 39, count 0 2006.201.03:41:36.25#ibcon#about to read 4, iclass 39, count 0 2006.201.03:41:36.25#ibcon#read 4, iclass 39, count 0 2006.201.03:41:36.25#ibcon#about to read 5, iclass 39, count 0 2006.201.03:41:36.25#ibcon#read 5, iclass 39, count 0 2006.201.03:41:36.25#ibcon#about to read 6, iclass 39, count 0 2006.201.03:41:36.25#ibcon#read 6, iclass 39, count 0 2006.201.03:41:36.25#ibcon#end of sib2, iclass 39, count 0 2006.201.03:41:36.25#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:41:36.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:41:36.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:41:36.25#ibcon#*before write, iclass 39, count 0 2006.201.03:41:36.25#ibcon#enter sib2, iclass 39, count 0 2006.201.03:41:36.25#ibcon#flushed, iclass 39, count 0 2006.201.03:41:36.25#ibcon#about to write, iclass 39, count 0 2006.201.03:41:36.25#ibcon#wrote, iclass 39, count 0 2006.201.03:41:36.25#ibcon#about to read 3, iclass 39, count 0 2006.201.03:41:36.29#ibcon#read 3, iclass 39, count 0 2006.201.03:41:36.29#ibcon#about to read 4, iclass 39, count 0 2006.201.03:41:36.29#ibcon#read 4, iclass 39, count 0 2006.201.03:41:36.29#ibcon#about to read 5, iclass 39, count 0 2006.201.03:41:36.29#ibcon#read 5, iclass 39, count 0 2006.201.03:41:36.29#ibcon#about to read 6, iclass 39, count 0 2006.201.03:41:36.29#ibcon#read 6, iclass 39, count 0 2006.201.03:41:36.29#ibcon#end of sib2, iclass 39, count 0 2006.201.03:41:36.29#ibcon#*after write, iclass 39, count 0 2006.201.03:41:36.29#ibcon#*before return 0, iclass 39, count 0 2006.201.03:41:36.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:36.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:36.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:41:36.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:41:36.29$vck44/va=5,4 2006.201.03:41:36.29#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.03:41:36.29#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.03:41:36.29#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:36.29#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:36.35#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:36.35#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:36.35#ibcon#enter wrdev, iclass 2, count 2 2006.201.03:41:36.35#ibcon#first serial, iclass 2, count 2 2006.201.03:41:36.35#ibcon#enter sib2, iclass 2, count 2 2006.201.03:41:36.35#ibcon#flushed, iclass 2, count 2 2006.201.03:41:36.35#ibcon#about to write, iclass 2, count 2 2006.201.03:41:36.35#ibcon#wrote, iclass 2, count 2 2006.201.03:41:36.35#ibcon#about to read 3, iclass 2, count 2 2006.201.03:41:36.37#ibcon#read 3, iclass 2, count 2 2006.201.03:41:36.37#ibcon#about to read 4, iclass 2, count 2 2006.201.03:41:36.37#ibcon#read 4, iclass 2, count 2 2006.201.03:41:36.37#ibcon#about to read 5, iclass 2, count 2 2006.201.03:41:36.37#ibcon#read 5, iclass 2, count 2 2006.201.03:41:36.37#ibcon#about to read 6, iclass 2, count 2 2006.201.03:41:36.37#ibcon#read 6, iclass 2, count 2 2006.201.03:41:36.37#ibcon#end of sib2, iclass 2, count 2 2006.201.03:41:36.37#ibcon#*mode == 0, iclass 2, count 2 2006.201.03:41:36.37#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.03:41:36.37#ibcon#[25=AT05-04\r\n] 2006.201.03:41:36.37#ibcon#*before write, iclass 2, count 2 2006.201.03:41:36.37#ibcon#enter sib2, iclass 2, count 2 2006.201.03:41:36.37#ibcon#flushed, iclass 2, count 2 2006.201.03:41:36.37#ibcon#about to write, iclass 2, count 2 2006.201.03:41:36.37#ibcon#wrote, iclass 2, count 2 2006.201.03:41:36.37#ibcon#about to read 3, iclass 2, count 2 2006.201.03:41:36.40#ibcon#read 3, iclass 2, count 2 2006.201.03:41:36.40#ibcon#about to read 4, iclass 2, count 2 2006.201.03:41:36.40#ibcon#read 4, iclass 2, count 2 2006.201.03:41:36.40#ibcon#about to read 5, iclass 2, count 2 2006.201.03:41:36.40#ibcon#read 5, iclass 2, count 2 2006.201.03:41:36.40#ibcon#about to read 6, iclass 2, count 2 2006.201.03:41:36.40#ibcon#read 6, iclass 2, count 2 2006.201.03:41:36.40#ibcon#end of sib2, iclass 2, count 2 2006.201.03:41:36.40#ibcon#*after write, iclass 2, count 2 2006.201.03:41:36.40#ibcon#*before return 0, iclass 2, count 2 2006.201.03:41:36.40#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:36.40#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:36.40#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.03:41:36.40#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:36.40#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:36.52#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:36.52#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:36.52#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:41:36.52#ibcon#first serial, iclass 2, count 0 2006.201.03:41:36.52#ibcon#enter sib2, iclass 2, count 0 2006.201.03:41:36.52#ibcon#flushed, iclass 2, count 0 2006.201.03:41:36.52#ibcon#about to write, iclass 2, count 0 2006.201.03:41:36.52#ibcon#wrote, iclass 2, count 0 2006.201.03:41:36.52#ibcon#about to read 3, iclass 2, count 0 2006.201.03:41:36.54#ibcon#read 3, iclass 2, count 0 2006.201.03:41:36.54#ibcon#about to read 4, iclass 2, count 0 2006.201.03:41:36.54#ibcon#read 4, iclass 2, count 0 2006.201.03:41:36.54#ibcon#about to read 5, iclass 2, count 0 2006.201.03:41:36.54#ibcon#read 5, iclass 2, count 0 2006.201.03:41:36.54#ibcon#about to read 6, iclass 2, count 0 2006.201.03:41:36.54#ibcon#read 6, iclass 2, count 0 2006.201.03:41:36.54#ibcon#end of sib2, iclass 2, count 0 2006.201.03:41:36.54#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:41:36.54#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:41:36.54#ibcon#[25=USB\r\n] 2006.201.03:41:36.54#ibcon#*before write, iclass 2, count 0 2006.201.03:41:36.54#ibcon#enter sib2, iclass 2, count 0 2006.201.03:41:36.54#ibcon#flushed, iclass 2, count 0 2006.201.03:41:36.54#ibcon#about to write, iclass 2, count 0 2006.201.03:41:36.54#ibcon#wrote, iclass 2, count 0 2006.201.03:41:36.54#ibcon#about to read 3, iclass 2, count 0 2006.201.03:41:36.57#ibcon#read 3, iclass 2, count 0 2006.201.03:41:36.57#ibcon#about to read 4, iclass 2, count 0 2006.201.03:41:36.57#ibcon#read 4, iclass 2, count 0 2006.201.03:41:36.57#ibcon#about to read 5, iclass 2, count 0 2006.201.03:41:36.57#ibcon#read 5, iclass 2, count 0 2006.201.03:41:36.57#ibcon#about to read 6, iclass 2, count 0 2006.201.03:41:36.57#ibcon#read 6, iclass 2, count 0 2006.201.03:41:36.57#ibcon#end of sib2, iclass 2, count 0 2006.201.03:41:36.57#ibcon#*after write, iclass 2, count 0 2006.201.03:41:36.57#ibcon#*before return 0, iclass 2, count 0 2006.201.03:41:36.57#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:36.57#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:36.57#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:41:36.57#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:41:36.57$vck44/valo=6,814.99 2006.201.03:41:36.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.03:41:36.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.03:41:36.57#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:36.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:36.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:36.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:36.57#ibcon#enter wrdev, iclass 5, count 0 2006.201.03:41:36.57#ibcon#first serial, iclass 5, count 0 2006.201.03:41:36.57#ibcon#enter sib2, iclass 5, count 0 2006.201.03:41:36.57#ibcon#flushed, iclass 5, count 0 2006.201.03:41:36.57#ibcon#about to write, iclass 5, count 0 2006.201.03:41:36.57#ibcon#wrote, iclass 5, count 0 2006.201.03:41:36.57#ibcon#about to read 3, iclass 5, count 0 2006.201.03:41:36.59#ibcon#read 3, iclass 5, count 0 2006.201.03:41:36.59#ibcon#about to read 4, iclass 5, count 0 2006.201.03:41:36.59#ibcon#read 4, iclass 5, count 0 2006.201.03:41:36.59#ibcon#about to read 5, iclass 5, count 0 2006.201.03:41:36.59#ibcon#read 5, iclass 5, count 0 2006.201.03:41:36.59#ibcon#about to read 6, iclass 5, count 0 2006.201.03:41:36.59#ibcon#read 6, iclass 5, count 0 2006.201.03:41:36.59#ibcon#end of sib2, iclass 5, count 0 2006.201.03:41:36.59#ibcon#*mode == 0, iclass 5, count 0 2006.201.03:41:36.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.03:41:36.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:41:36.59#ibcon#*before write, iclass 5, count 0 2006.201.03:41:36.59#ibcon#enter sib2, iclass 5, count 0 2006.201.03:41:36.59#ibcon#flushed, iclass 5, count 0 2006.201.03:41:36.59#ibcon#about to write, iclass 5, count 0 2006.201.03:41:36.59#ibcon#wrote, iclass 5, count 0 2006.201.03:41:36.59#ibcon#about to read 3, iclass 5, count 0 2006.201.03:41:36.64#ibcon#read 3, iclass 5, count 0 2006.201.03:41:36.64#ibcon#about to read 4, iclass 5, count 0 2006.201.03:41:36.64#ibcon#read 4, iclass 5, count 0 2006.201.03:41:36.64#ibcon#about to read 5, iclass 5, count 0 2006.201.03:41:36.64#ibcon#read 5, iclass 5, count 0 2006.201.03:41:36.64#ibcon#about to read 6, iclass 5, count 0 2006.201.03:41:36.64#ibcon#read 6, iclass 5, count 0 2006.201.03:41:36.64#ibcon#end of sib2, iclass 5, count 0 2006.201.03:41:36.64#ibcon#*after write, iclass 5, count 0 2006.201.03:41:36.64#ibcon#*before return 0, iclass 5, count 0 2006.201.03:41:36.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:36.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:36.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.03:41:36.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.03:41:36.64$vck44/va=6,5 2006.201.03:41:36.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.03:41:36.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.03:41:36.64#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:36.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:36.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:36.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:36.69#ibcon#enter wrdev, iclass 7, count 2 2006.201.03:41:36.69#ibcon#first serial, iclass 7, count 2 2006.201.03:41:36.69#ibcon#enter sib2, iclass 7, count 2 2006.201.03:41:36.69#ibcon#flushed, iclass 7, count 2 2006.201.03:41:36.69#ibcon#about to write, iclass 7, count 2 2006.201.03:41:36.69#ibcon#wrote, iclass 7, count 2 2006.201.03:41:36.69#ibcon#about to read 3, iclass 7, count 2 2006.201.03:41:36.71#ibcon#read 3, iclass 7, count 2 2006.201.03:41:36.71#ibcon#about to read 4, iclass 7, count 2 2006.201.03:41:36.71#ibcon#read 4, iclass 7, count 2 2006.201.03:41:36.71#ibcon#about to read 5, iclass 7, count 2 2006.201.03:41:36.71#ibcon#read 5, iclass 7, count 2 2006.201.03:41:36.71#ibcon#about to read 6, iclass 7, count 2 2006.201.03:41:36.71#ibcon#read 6, iclass 7, count 2 2006.201.03:41:36.71#ibcon#end of sib2, iclass 7, count 2 2006.201.03:41:36.71#ibcon#*mode == 0, iclass 7, count 2 2006.201.03:41:36.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.03:41:36.71#ibcon#[25=AT06-05\r\n] 2006.201.03:41:36.71#ibcon#*before write, iclass 7, count 2 2006.201.03:41:36.71#ibcon#enter sib2, iclass 7, count 2 2006.201.03:41:36.71#ibcon#flushed, iclass 7, count 2 2006.201.03:41:36.71#ibcon#about to write, iclass 7, count 2 2006.201.03:41:36.71#ibcon#wrote, iclass 7, count 2 2006.201.03:41:36.71#ibcon#about to read 3, iclass 7, count 2 2006.201.03:41:36.74#ibcon#read 3, iclass 7, count 2 2006.201.03:41:36.74#ibcon#about to read 4, iclass 7, count 2 2006.201.03:41:36.74#ibcon#read 4, iclass 7, count 2 2006.201.03:41:36.74#ibcon#about to read 5, iclass 7, count 2 2006.201.03:41:36.74#ibcon#read 5, iclass 7, count 2 2006.201.03:41:36.74#ibcon#about to read 6, iclass 7, count 2 2006.201.03:41:36.74#ibcon#read 6, iclass 7, count 2 2006.201.03:41:36.74#ibcon#end of sib2, iclass 7, count 2 2006.201.03:41:36.74#ibcon#*after write, iclass 7, count 2 2006.201.03:41:36.74#ibcon#*before return 0, iclass 7, count 2 2006.201.03:41:36.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:36.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:36.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.03:41:36.74#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:36.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:36.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:36.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:36.86#ibcon#enter wrdev, iclass 7, count 0 2006.201.03:41:36.86#ibcon#first serial, iclass 7, count 0 2006.201.03:41:36.86#ibcon#enter sib2, iclass 7, count 0 2006.201.03:41:36.86#ibcon#flushed, iclass 7, count 0 2006.201.03:41:36.86#ibcon#about to write, iclass 7, count 0 2006.201.03:41:36.86#ibcon#wrote, iclass 7, count 0 2006.201.03:41:36.86#ibcon#about to read 3, iclass 7, count 0 2006.201.03:41:36.88#ibcon#read 3, iclass 7, count 0 2006.201.03:41:36.88#ibcon#about to read 4, iclass 7, count 0 2006.201.03:41:36.88#ibcon#read 4, iclass 7, count 0 2006.201.03:41:36.88#ibcon#about to read 5, iclass 7, count 0 2006.201.03:41:36.88#ibcon#read 5, iclass 7, count 0 2006.201.03:41:36.88#ibcon#about to read 6, iclass 7, count 0 2006.201.03:41:36.88#ibcon#read 6, iclass 7, count 0 2006.201.03:41:36.88#ibcon#end of sib2, iclass 7, count 0 2006.201.03:41:36.88#ibcon#*mode == 0, iclass 7, count 0 2006.201.03:41:36.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.03:41:36.88#ibcon#[25=USB\r\n] 2006.201.03:41:36.88#ibcon#*before write, iclass 7, count 0 2006.201.03:41:36.88#ibcon#enter sib2, iclass 7, count 0 2006.201.03:41:36.88#ibcon#flushed, iclass 7, count 0 2006.201.03:41:36.88#ibcon#about to write, iclass 7, count 0 2006.201.03:41:36.88#ibcon#wrote, iclass 7, count 0 2006.201.03:41:36.88#ibcon#about to read 3, iclass 7, count 0 2006.201.03:41:36.91#ibcon#read 3, iclass 7, count 0 2006.201.03:41:36.91#ibcon#about to read 4, iclass 7, count 0 2006.201.03:41:36.91#ibcon#read 4, iclass 7, count 0 2006.201.03:41:36.91#ibcon#about to read 5, iclass 7, count 0 2006.201.03:41:36.91#ibcon#read 5, iclass 7, count 0 2006.201.03:41:36.91#ibcon#about to read 6, iclass 7, count 0 2006.201.03:41:36.91#ibcon#read 6, iclass 7, count 0 2006.201.03:41:36.91#ibcon#end of sib2, iclass 7, count 0 2006.201.03:41:36.91#ibcon#*after write, iclass 7, count 0 2006.201.03:41:36.91#ibcon#*before return 0, iclass 7, count 0 2006.201.03:41:36.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:36.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:36.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.03:41:36.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.03:41:36.91$vck44/valo=7,864.99 2006.201.03:41:36.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.03:41:36.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.03:41:36.91#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:36.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:36.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:36.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:36.91#ibcon#enter wrdev, iclass 11, count 0 2006.201.03:41:36.91#ibcon#first serial, iclass 11, count 0 2006.201.03:41:36.91#ibcon#enter sib2, iclass 11, count 0 2006.201.03:41:36.91#ibcon#flushed, iclass 11, count 0 2006.201.03:41:36.91#ibcon#about to write, iclass 11, count 0 2006.201.03:41:36.91#ibcon#wrote, iclass 11, count 0 2006.201.03:41:36.91#ibcon#about to read 3, iclass 11, count 0 2006.201.03:41:36.93#ibcon#read 3, iclass 11, count 0 2006.201.03:41:36.93#ibcon#about to read 4, iclass 11, count 0 2006.201.03:41:36.93#ibcon#read 4, iclass 11, count 0 2006.201.03:41:36.93#ibcon#about to read 5, iclass 11, count 0 2006.201.03:41:36.93#ibcon#read 5, iclass 11, count 0 2006.201.03:41:36.93#ibcon#about to read 6, iclass 11, count 0 2006.201.03:41:36.93#ibcon#read 6, iclass 11, count 0 2006.201.03:41:36.93#ibcon#end of sib2, iclass 11, count 0 2006.201.03:41:36.93#ibcon#*mode == 0, iclass 11, count 0 2006.201.03:41:36.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.03:41:36.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:41:36.93#ibcon#*before write, iclass 11, count 0 2006.201.03:41:36.93#ibcon#enter sib2, iclass 11, count 0 2006.201.03:41:36.93#ibcon#flushed, iclass 11, count 0 2006.201.03:41:36.93#ibcon#about to write, iclass 11, count 0 2006.201.03:41:36.93#ibcon#wrote, iclass 11, count 0 2006.201.03:41:36.93#ibcon#about to read 3, iclass 11, count 0 2006.201.03:41:36.97#ibcon#read 3, iclass 11, count 0 2006.201.03:41:36.97#ibcon#about to read 4, iclass 11, count 0 2006.201.03:41:36.97#ibcon#read 4, iclass 11, count 0 2006.201.03:41:36.97#ibcon#about to read 5, iclass 11, count 0 2006.201.03:41:36.97#ibcon#read 5, iclass 11, count 0 2006.201.03:41:36.97#ibcon#about to read 6, iclass 11, count 0 2006.201.03:41:36.97#ibcon#read 6, iclass 11, count 0 2006.201.03:41:36.97#ibcon#end of sib2, iclass 11, count 0 2006.201.03:41:36.97#ibcon#*after write, iclass 11, count 0 2006.201.03:41:36.97#ibcon#*before return 0, iclass 11, count 0 2006.201.03:41:36.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:36.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:36.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.03:41:36.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.03:41:36.97$vck44/va=7,5 2006.201.03:41:36.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.03:41:36.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.03:41:36.97#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:36.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:37.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:37.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:37.03#ibcon#enter wrdev, iclass 13, count 2 2006.201.03:41:37.03#ibcon#first serial, iclass 13, count 2 2006.201.03:41:37.03#ibcon#enter sib2, iclass 13, count 2 2006.201.03:41:37.03#ibcon#flushed, iclass 13, count 2 2006.201.03:41:37.03#ibcon#about to write, iclass 13, count 2 2006.201.03:41:37.03#ibcon#wrote, iclass 13, count 2 2006.201.03:41:37.03#ibcon#about to read 3, iclass 13, count 2 2006.201.03:41:37.05#ibcon#read 3, iclass 13, count 2 2006.201.03:41:37.05#ibcon#about to read 4, iclass 13, count 2 2006.201.03:41:37.05#ibcon#read 4, iclass 13, count 2 2006.201.03:41:37.05#ibcon#about to read 5, iclass 13, count 2 2006.201.03:41:37.05#ibcon#read 5, iclass 13, count 2 2006.201.03:41:37.05#ibcon#about to read 6, iclass 13, count 2 2006.201.03:41:37.05#ibcon#read 6, iclass 13, count 2 2006.201.03:41:37.05#ibcon#end of sib2, iclass 13, count 2 2006.201.03:41:37.05#ibcon#*mode == 0, iclass 13, count 2 2006.201.03:41:37.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.03:41:37.05#ibcon#[25=AT07-05\r\n] 2006.201.03:41:37.05#ibcon#*before write, iclass 13, count 2 2006.201.03:41:37.05#ibcon#enter sib2, iclass 13, count 2 2006.201.03:41:37.05#ibcon#flushed, iclass 13, count 2 2006.201.03:41:37.05#ibcon#about to write, iclass 13, count 2 2006.201.03:41:37.05#ibcon#wrote, iclass 13, count 2 2006.201.03:41:37.05#ibcon#about to read 3, iclass 13, count 2 2006.201.03:41:37.08#ibcon#read 3, iclass 13, count 2 2006.201.03:41:37.08#ibcon#about to read 4, iclass 13, count 2 2006.201.03:41:37.08#ibcon#read 4, iclass 13, count 2 2006.201.03:41:37.08#ibcon#about to read 5, iclass 13, count 2 2006.201.03:41:37.08#ibcon#read 5, iclass 13, count 2 2006.201.03:41:37.08#ibcon#about to read 6, iclass 13, count 2 2006.201.03:41:37.08#ibcon#read 6, iclass 13, count 2 2006.201.03:41:37.08#ibcon#end of sib2, iclass 13, count 2 2006.201.03:41:37.08#ibcon#*after write, iclass 13, count 2 2006.201.03:41:37.08#ibcon#*before return 0, iclass 13, count 2 2006.201.03:41:37.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:37.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:37.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.03:41:37.08#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:37.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:37.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:37.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:37.20#ibcon#enter wrdev, iclass 13, count 0 2006.201.03:41:37.20#ibcon#first serial, iclass 13, count 0 2006.201.03:41:37.20#ibcon#enter sib2, iclass 13, count 0 2006.201.03:41:37.20#ibcon#flushed, iclass 13, count 0 2006.201.03:41:37.20#ibcon#about to write, iclass 13, count 0 2006.201.03:41:37.20#ibcon#wrote, iclass 13, count 0 2006.201.03:41:37.20#ibcon#about to read 3, iclass 13, count 0 2006.201.03:41:37.22#ibcon#read 3, iclass 13, count 0 2006.201.03:41:37.22#ibcon#about to read 4, iclass 13, count 0 2006.201.03:41:37.22#ibcon#read 4, iclass 13, count 0 2006.201.03:41:37.22#ibcon#about to read 5, iclass 13, count 0 2006.201.03:41:37.22#ibcon#read 5, iclass 13, count 0 2006.201.03:41:37.22#ibcon#about to read 6, iclass 13, count 0 2006.201.03:41:37.22#ibcon#read 6, iclass 13, count 0 2006.201.03:41:37.22#ibcon#end of sib2, iclass 13, count 0 2006.201.03:41:37.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.03:41:37.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.03:41:37.22#ibcon#[25=USB\r\n] 2006.201.03:41:37.22#ibcon#*before write, iclass 13, count 0 2006.201.03:41:37.22#ibcon#enter sib2, iclass 13, count 0 2006.201.03:41:37.22#ibcon#flushed, iclass 13, count 0 2006.201.03:41:37.22#ibcon#about to write, iclass 13, count 0 2006.201.03:41:37.22#ibcon#wrote, iclass 13, count 0 2006.201.03:41:37.22#ibcon#about to read 3, iclass 13, count 0 2006.201.03:41:37.25#ibcon#read 3, iclass 13, count 0 2006.201.03:41:37.25#ibcon#about to read 4, iclass 13, count 0 2006.201.03:41:37.25#ibcon#read 4, iclass 13, count 0 2006.201.03:41:37.25#ibcon#about to read 5, iclass 13, count 0 2006.201.03:41:37.25#ibcon#read 5, iclass 13, count 0 2006.201.03:41:37.25#ibcon#about to read 6, iclass 13, count 0 2006.201.03:41:37.25#ibcon#read 6, iclass 13, count 0 2006.201.03:41:37.25#ibcon#end of sib2, iclass 13, count 0 2006.201.03:41:37.25#ibcon#*after write, iclass 13, count 0 2006.201.03:41:37.25#ibcon#*before return 0, iclass 13, count 0 2006.201.03:41:37.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:37.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:37.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.03:41:37.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.03:41:37.25$vck44/valo=8,884.99 2006.201.03:41:37.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.03:41:37.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.03:41:37.25#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:37.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:37.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:37.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:37.25#ibcon#enter wrdev, iclass 15, count 0 2006.201.03:41:37.25#ibcon#first serial, iclass 15, count 0 2006.201.03:41:37.25#ibcon#enter sib2, iclass 15, count 0 2006.201.03:41:37.25#ibcon#flushed, iclass 15, count 0 2006.201.03:41:37.25#ibcon#about to write, iclass 15, count 0 2006.201.03:41:37.25#ibcon#wrote, iclass 15, count 0 2006.201.03:41:37.25#ibcon#about to read 3, iclass 15, count 0 2006.201.03:41:37.27#ibcon#read 3, iclass 15, count 0 2006.201.03:41:37.27#ibcon#about to read 4, iclass 15, count 0 2006.201.03:41:37.27#ibcon#read 4, iclass 15, count 0 2006.201.03:41:37.27#ibcon#about to read 5, iclass 15, count 0 2006.201.03:41:37.27#ibcon#read 5, iclass 15, count 0 2006.201.03:41:37.27#ibcon#about to read 6, iclass 15, count 0 2006.201.03:41:37.27#ibcon#read 6, iclass 15, count 0 2006.201.03:41:37.27#ibcon#end of sib2, iclass 15, count 0 2006.201.03:41:37.27#ibcon#*mode == 0, iclass 15, count 0 2006.201.03:41:37.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.03:41:37.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:41:37.27#ibcon#*before write, iclass 15, count 0 2006.201.03:41:37.27#ibcon#enter sib2, iclass 15, count 0 2006.201.03:41:37.27#ibcon#flushed, iclass 15, count 0 2006.201.03:41:37.27#ibcon#about to write, iclass 15, count 0 2006.201.03:41:37.27#ibcon#wrote, iclass 15, count 0 2006.201.03:41:37.27#ibcon#about to read 3, iclass 15, count 0 2006.201.03:41:37.31#ibcon#read 3, iclass 15, count 0 2006.201.03:41:37.31#ibcon#about to read 4, iclass 15, count 0 2006.201.03:41:37.31#ibcon#read 4, iclass 15, count 0 2006.201.03:41:37.31#ibcon#about to read 5, iclass 15, count 0 2006.201.03:41:37.31#ibcon#read 5, iclass 15, count 0 2006.201.03:41:37.31#ibcon#about to read 6, iclass 15, count 0 2006.201.03:41:37.31#ibcon#read 6, iclass 15, count 0 2006.201.03:41:37.31#ibcon#end of sib2, iclass 15, count 0 2006.201.03:41:37.31#ibcon#*after write, iclass 15, count 0 2006.201.03:41:37.31#ibcon#*before return 0, iclass 15, count 0 2006.201.03:41:37.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:37.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:37.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.03:41:37.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.03:41:37.31$vck44/va=8,4 2006.201.03:41:37.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.03:41:37.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.03:41:37.31#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:37.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:41:37.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:41:37.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:41:37.37#ibcon#enter wrdev, iclass 17, count 2 2006.201.03:41:37.37#ibcon#first serial, iclass 17, count 2 2006.201.03:41:37.37#ibcon#enter sib2, iclass 17, count 2 2006.201.03:41:37.37#ibcon#flushed, iclass 17, count 2 2006.201.03:41:37.37#ibcon#about to write, iclass 17, count 2 2006.201.03:41:37.37#ibcon#wrote, iclass 17, count 2 2006.201.03:41:37.37#ibcon#about to read 3, iclass 17, count 2 2006.201.03:41:37.39#ibcon#read 3, iclass 17, count 2 2006.201.03:41:37.39#ibcon#about to read 4, iclass 17, count 2 2006.201.03:41:37.39#ibcon#read 4, iclass 17, count 2 2006.201.03:41:37.39#ibcon#about to read 5, iclass 17, count 2 2006.201.03:41:37.39#ibcon#read 5, iclass 17, count 2 2006.201.03:41:37.39#ibcon#about to read 6, iclass 17, count 2 2006.201.03:41:37.39#ibcon#read 6, iclass 17, count 2 2006.201.03:41:37.39#ibcon#end of sib2, iclass 17, count 2 2006.201.03:41:37.39#ibcon#*mode == 0, iclass 17, count 2 2006.201.03:41:37.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.03:41:37.39#ibcon#[25=AT08-04\r\n] 2006.201.03:41:37.39#ibcon#*before write, iclass 17, count 2 2006.201.03:41:37.39#ibcon#enter sib2, iclass 17, count 2 2006.201.03:41:37.39#ibcon#flushed, iclass 17, count 2 2006.201.03:41:37.39#ibcon#about to write, iclass 17, count 2 2006.201.03:41:37.39#ibcon#wrote, iclass 17, count 2 2006.201.03:41:37.39#ibcon#about to read 3, iclass 17, count 2 2006.201.03:41:37.42#ibcon#read 3, iclass 17, count 2 2006.201.03:41:37.42#ibcon#about to read 4, iclass 17, count 2 2006.201.03:41:37.42#ibcon#read 4, iclass 17, count 2 2006.201.03:41:37.42#ibcon#about to read 5, iclass 17, count 2 2006.201.03:41:37.42#ibcon#read 5, iclass 17, count 2 2006.201.03:41:37.42#ibcon#about to read 6, iclass 17, count 2 2006.201.03:41:37.42#ibcon#read 6, iclass 17, count 2 2006.201.03:41:37.42#ibcon#end of sib2, iclass 17, count 2 2006.201.03:41:37.42#ibcon#*after write, iclass 17, count 2 2006.201.03:41:37.42#ibcon#*before return 0, iclass 17, count 2 2006.201.03:41:37.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:41:37.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:41:37.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.03:41:37.42#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:37.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:41:37.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:41:37.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:41:37.54#ibcon#enter wrdev, iclass 17, count 0 2006.201.03:41:37.54#ibcon#first serial, iclass 17, count 0 2006.201.03:41:37.54#ibcon#enter sib2, iclass 17, count 0 2006.201.03:41:37.54#ibcon#flushed, iclass 17, count 0 2006.201.03:41:37.54#ibcon#about to write, iclass 17, count 0 2006.201.03:41:37.54#ibcon#wrote, iclass 17, count 0 2006.201.03:41:37.54#ibcon#about to read 3, iclass 17, count 0 2006.201.03:41:37.56#ibcon#read 3, iclass 17, count 0 2006.201.03:41:37.56#ibcon#about to read 4, iclass 17, count 0 2006.201.03:41:37.56#ibcon#read 4, iclass 17, count 0 2006.201.03:41:37.56#ibcon#about to read 5, iclass 17, count 0 2006.201.03:41:37.56#ibcon#read 5, iclass 17, count 0 2006.201.03:41:37.56#ibcon#about to read 6, iclass 17, count 0 2006.201.03:41:37.56#ibcon#read 6, iclass 17, count 0 2006.201.03:41:37.56#ibcon#end of sib2, iclass 17, count 0 2006.201.03:41:37.56#ibcon#*mode == 0, iclass 17, count 0 2006.201.03:41:37.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.03:41:37.56#ibcon#[25=USB\r\n] 2006.201.03:41:37.56#ibcon#*before write, iclass 17, count 0 2006.201.03:41:37.56#ibcon#enter sib2, iclass 17, count 0 2006.201.03:41:37.56#ibcon#flushed, iclass 17, count 0 2006.201.03:41:37.56#ibcon#about to write, iclass 17, count 0 2006.201.03:41:37.56#ibcon#wrote, iclass 17, count 0 2006.201.03:41:37.56#ibcon#about to read 3, iclass 17, count 0 2006.201.03:41:37.59#ibcon#read 3, iclass 17, count 0 2006.201.03:41:37.59#ibcon#about to read 4, iclass 17, count 0 2006.201.03:41:37.59#ibcon#read 4, iclass 17, count 0 2006.201.03:41:37.59#ibcon#about to read 5, iclass 17, count 0 2006.201.03:41:37.59#ibcon#read 5, iclass 17, count 0 2006.201.03:41:37.59#ibcon#about to read 6, iclass 17, count 0 2006.201.03:41:37.59#ibcon#read 6, iclass 17, count 0 2006.201.03:41:37.59#ibcon#end of sib2, iclass 17, count 0 2006.201.03:41:37.59#ibcon#*after write, iclass 17, count 0 2006.201.03:41:37.59#ibcon#*before return 0, iclass 17, count 0 2006.201.03:41:37.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:41:37.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:41:37.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.03:41:37.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.03:41:37.59$vck44/vblo=1,629.99 2006.201.03:41:37.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.03:41:37.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.03:41:37.59#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:37.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:41:37.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:41:37.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:41:37.59#ibcon#enter wrdev, iclass 19, count 0 2006.201.03:41:37.59#ibcon#first serial, iclass 19, count 0 2006.201.03:41:37.59#ibcon#enter sib2, iclass 19, count 0 2006.201.03:41:37.59#ibcon#flushed, iclass 19, count 0 2006.201.03:41:37.59#ibcon#about to write, iclass 19, count 0 2006.201.03:41:37.59#ibcon#wrote, iclass 19, count 0 2006.201.03:41:37.59#ibcon#about to read 3, iclass 19, count 0 2006.201.03:41:37.61#ibcon#read 3, iclass 19, count 0 2006.201.03:41:37.61#ibcon#about to read 4, iclass 19, count 0 2006.201.03:41:37.61#ibcon#read 4, iclass 19, count 0 2006.201.03:41:37.61#ibcon#about to read 5, iclass 19, count 0 2006.201.03:41:37.61#ibcon#read 5, iclass 19, count 0 2006.201.03:41:37.61#ibcon#about to read 6, iclass 19, count 0 2006.201.03:41:37.61#ibcon#read 6, iclass 19, count 0 2006.201.03:41:37.61#ibcon#end of sib2, iclass 19, count 0 2006.201.03:41:37.61#ibcon#*mode == 0, iclass 19, count 0 2006.201.03:41:37.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.03:41:37.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:41:37.61#ibcon#*before write, iclass 19, count 0 2006.201.03:41:37.61#ibcon#enter sib2, iclass 19, count 0 2006.201.03:41:37.61#ibcon#flushed, iclass 19, count 0 2006.201.03:41:37.61#ibcon#about to write, iclass 19, count 0 2006.201.03:41:37.61#ibcon#wrote, iclass 19, count 0 2006.201.03:41:37.61#ibcon#about to read 3, iclass 19, count 0 2006.201.03:41:37.65#ibcon#read 3, iclass 19, count 0 2006.201.03:41:37.65#ibcon#about to read 4, iclass 19, count 0 2006.201.03:41:37.65#ibcon#read 4, iclass 19, count 0 2006.201.03:41:37.65#ibcon#about to read 5, iclass 19, count 0 2006.201.03:41:37.65#ibcon#read 5, iclass 19, count 0 2006.201.03:41:37.65#ibcon#about to read 6, iclass 19, count 0 2006.201.03:41:37.65#ibcon#read 6, iclass 19, count 0 2006.201.03:41:37.65#ibcon#end of sib2, iclass 19, count 0 2006.201.03:41:37.65#ibcon#*after write, iclass 19, count 0 2006.201.03:41:37.65#ibcon#*before return 0, iclass 19, count 0 2006.201.03:41:37.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:41:37.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:41:37.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.03:41:37.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.03:41:37.65$vck44/vb=1,4 2006.201.03:41:37.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.03:41:37.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.03:41:37.65#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:37.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:41:37.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:41:37.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:41:37.65#ibcon#enter wrdev, iclass 21, count 2 2006.201.03:41:37.65#ibcon#first serial, iclass 21, count 2 2006.201.03:41:37.65#ibcon#enter sib2, iclass 21, count 2 2006.201.03:41:37.65#ibcon#flushed, iclass 21, count 2 2006.201.03:41:37.65#ibcon#about to write, iclass 21, count 2 2006.201.03:41:37.65#ibcon#wrote, iclass 21, count 2 2006.201.03:41:37.65#ibcon#about to read 3, iclass 21, count 2 2006.201.03:41:37.67#ibcon#read 3, iclass 21, count 2 2006.201.03:41:37.67#ibcon#about to read 4, iclass 21, count 2 2006.201.03:41:37.67#ibcon#read 4, iclass 21, count 2 2006.201.03:41:37.67#ibcon#about to read 5, iclass 21, count 2 2006.201.03:41:37.67#ibcon#read 5, iclass 21, count 2 2006.201.03:41:37.67#ibcon#about to read 6, iclass 21, count 2 2006.201.03:41:37.67#ibcon#read 6, iclass 21, count 2 2006.201.03:41:37.67#ibcon#end of sib2, iclass 21, count 2 2006.201.03:41:37.67#ibcon#*mode == 0, iclass 21, count 2 2006.201.03:41:37.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.03:41:37.67#ibcon#[27=AT01-04\r\n] 2006.201.03:41:37.67#ibcon#*before write, iclass 21, count 2 2006.201.03:41:37.67#ibcon#enter sib2, iclass 21, count 2 2006.201.03:41:37.67#ibcon#flushed, iclass 21, count 2 2006.201.03:41:37.67#ibcon#about to write, iclass 21, count 2 2006.201.03:41:37.67#ibcon#wrote, iclass 21, count 2 2006.201.03:41:37.67#ibcon#about to read 3, iclass 21, count 2 2006.201.03:41:37.70#ibcon#read 3, iclass 21, count 2 2006.201.03:41:37.70#ibcon#about to read 4, iclass 21, count 2 2006.201.03:41:37.70#ibcon#read 4, iclass 21, count 2 2006.201.03:41:37.70#ibcon#about to read 5, iclass 21, count 2 2006.201.03:41:37.70#ibcon#read 5, iclass 21, count 2 2006.201.03:41:37.70#ibcon#about to read 6, iclass 21, count 2 2006.201.03:41:37.70#ibcon#read 6, iclass 21, count 2 2006.201.03:41:37.70#ibcon#end of sib2, iclass 21, count 2 2006.201.03:41:37.70#ibcon#*after write, iclass 21, count 2 2006.201.03:41:37.70#ibcon#*before return 0, iclass 21, count 2 2006.201.03:41:37.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:41:37.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:41:37.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.03:41:37.70#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:37.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:41:37.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:41:37.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:41:37.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.03:41:37.82#ibcon#first serial, iclass 21, count 0 2006.201.03:41:37.82#ibcon#enter sib2, iclass 21, count 0 2006.201.03:41:37.82#ibcon#flushed, iclass 21, count 0 2006.201.03:41:37.82#ibcon#about to write, iclass 21, count 0 2006.201.03:41:37.82#ibcon#wrote, iclass 21, count 0 2006.201.03:41:37.82#ibcon#about to read 3, iclass 21, count 0 2006.201.03:41:37.84#ibcon#read 3, iclass 21, count 0 2006.201.03:41:37.84#ibcon#about to read 4, iclass 21, count 0 2006.201.03:41:37.84#ibcon#read 4, iclass 21, count 0 2006.201.03:41:37.84#ibcon#about to read 5, iclass 21, count 0 2006.201.03:41:37.84#ibcon#read 5, iclass 21, count 0 2006.201.03:41:37.84#ibcon#about to read 6, iclass 21, count 0 2006.201.03:41:37.84#ibcon#read 6, iclass 21, count 0 2006.201.03:41:37.84#ibcon#end of sib2, iclass 21, count 0 2006.201.03:41:37.84#ibcon#*mode == 0, iclass 21, count 0 2006.201.03:41:37.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.03:41:37.84#ibcon#[27=USB\r\n] 2006.201.03:41:37.84#ibcon#*before write, iclass 21, count 0 2006.201.03:41:37.84#ibcon#enter sib2, iclass 21, count 0 2006.201.03:41:37.84#ibcon#flushed, iclass 21, count 0 2006.201.03:41:37.84#ibcon#about to write, iclass 21, count 0 2006.201.03:41:37.84#ibcon#wrote, iclass 21, count 0 2006.201.03:41:37.84#ibcon#about to read 3, iclass 21, count 0 2006.201.03:41:37.87#ibcon#read 3, iclass 21, count 0 2006.201.03:41:37.87#ibcon#about to read 4, iclass 21, count 0 2006.201.03:41:37.87#ibcon#read 4, iclass 21, count 0 2006.201.03:41:37.87#ibcon#about to read 5, iclass 21, count 0 2006.201.03:41:37.87#ibcon#read 5, iclass 21, count 0 2006.201.03:41:37.87#ibcon#about to read 6, iclass 21, count 0 2006.201.03:41:37.87#ibcon#read 6, iclass 21, count 0 2006.201.03:41:37.87#ibcon#end of sib2, iclass 21, count 0 2006.201.03:41:37.87#ibcon#*after write, iclass 21, count 0 2006.201.03:41:37.87#ibcon#*before return 0, iclass 21, count 0 2006.201.03:41:37.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:41:37.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:41:37.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.03:41:37.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.03:41:37.87$vck44/vblo=2,634.99 2006.201.03:41:37.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.03:41:37.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.03:41:37.87#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:37.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:37.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:37.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:37.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.03:41:37.87#ibcon#first serial, iclass 23, count 0 2006.201.03:41:37.87#ibcon#enter sib2, iclass 23, count 0 2006.201.03:41:37.87#ibcon#flushed, iclass 23, count 0 2006.201.03:41:37.87#ibcon#about to write, iclass 23, count 0 2006.201.03:41:37.87#ibcon#wrote, iclass 23, count 0 2006.201.03:41:37.87#ibcon#about to read 3, iclass 23, count 0 2006.201.03:41:37.89#ibcon#read 3, iclass 23, count 0 2006.201.03:41:37.89#ibcon#about to read 4, iclass 23, count 0 2006.201.03:41:37.89#ibcon#read 4, iclass 23, count 0 2006.201.03:41:37.89#ibcon#about to read 5, iclass 23, count 0 2006.201.03:41:37.89#ibcon#read 5, iclass 23, count 0 2006.201.03:41:37.89#ibcon#about to read 6, iclass 23, count 0 2006.201.03:41:37.89#ibcon#read 6, iclass 23, count 0 2006.201.03:41:37.89#ibcon#end of sib2, iclass 23, count 0 2006.201.03:41:37.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.03:41:37.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.03:41:37.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:41:37.89#ibcon#*before write, iclass 23, count 0 2006.201.03:41:37.89#ibcon#enter sib2, iclass 23, count 0 2006.201.03:41:37.89#ibcon#flushed, iclass 23, count 0 2006.201.03:41:37.89#ibcon#about to write, iclass 23, count 0 2006.201.03:41:37.89#ibcon#wrote, iclass 23, count 0 2006.201.03:41:37.89#ibcon#about to read 3, iclass 23, count 0 2006.201.03:41:37.93#ibcon#read 3, iclass 23, count 0 2006.201.03:41:37.93#ibcon#about to read 4, iclass 23, count 0 2006.201.03:41:37.93#ibcon#read 4, iclass 23, count 0 2006.201.03:41:37.93#ibcon#about to read 5, iclass 23, count 0 2006.201.03:41:37.93#ibcon#read 5, iclass 23, count 0 2006.201.03:41:37.93#ibcon#about to read 6, iclass 23, count 0 2006.201.03:41:37.93#ibcon#read 6, iclass 23, count 0 2006.201.03:41:37.93#ibcon#end of sib2, iclass 23, count 0 2006.201.03:41:37.93#ibcon#*after write, iclass 23, count 0 2006.201.03:41:37.93#ibcon#*before return 0, iclass 23, count 0 2006.201.03:41:37.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:37.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:41:37.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.03:41:37.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.03:41:37.93$vck44/vb=2,5 2006.201.03:41:37.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.03:41:37.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.03:41:37.93#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:37.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:37.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:37.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:37.99#ibcon#enter wrdev, iclass 25, count 2 2006.201.03:41:37.99#ibcon#first serial, iclass 25, count 2 2006.201.03:41:37.99#ibcon#enter sib2, iclass 25, count 2 2006.201.03:41:37.99#ibcon#flushed, iclass 25, count 2 2006.201.03:41:37.99#ibcon#about to write, iclass 25, count 2 2006.201.03:41:37.99#ibcon#wrote, iclass 25, count 2 2006.201.03:41:37.99#ibcon#about to read 3, iclass 25, count 2 2006.201.03:41:38.01#ibcon#read 3, iclass 25, count 2 2006.201.03:41:38.01#ibcon#about to read 4, iclass 25, count 2 2006.201.03:41:38.01#ibcon#read 4, iclass 25, count 2 2006.201.03:41:38.01#ibcon#about to read 5, iclass 25, count 2 2006.201.03:41:38.01#ibcon#read 5, iclass 25, count 2 2006.201.03:41:38.01#ibcon#about to read 6, iclass 25, count 2 2006.201.03:41:38.01#ibcon#read 6, iclass 25, count 2 2006.201.03:41:38.01#ibcon#end of sib2, iclass 25, count 2 2006.201.03:41:38.01#ibcon#*mode == 0, iclass 25, count 2 2006.201.03:41:38.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.03:41:38.01#ibcon#[27=AT02-05\r\n] 2006.201.03:41:38.01#ibcon#*before write, iclass 25, count 2 2006.201.03:41:38.01#ibcon#enter sib2, iclass 25, count 2 2006.201.03:41:38.01#ibcon#flushed, iclass 25, count 2 2006.201.03:41:38.01#ibcon#about to write, iclass 25, count 2 2006.201.03:41:38.01#ibcon#wrote, iclass 25, count 2 2006.201.03:41:38.01#ibcon#about to read 3, iclass 25, count 2 2006.201.03:41:38.04#ibcon#read 3, iclass 25, count 2 2006.201.03:41:38.04#ibcon#about to read 4, iclass 25, count 2 2006.201.03:41:38.04#ibcon#read 4, iclass 25, count 2 2006.201.03:41:38.04#ibcon#about to read 5, iclass 25, count 2 2006.201.03:41:38.04#ibcon#read 5, iclass 25, count 2 2006.201.03:41:38.04#ibcon#about to read 6, iclass 25, count 2 2006.201.03:41:38.04#ibcon#read 6, iclass 25, count 2 2006.201.03:41:38.04#ibcon#end of sib2, iclass 25, count 2 2006.201.03:41:38.04#ibcon#*after write, iclass 25, count 2 2006.201.03:41:38.04#ibcon#*before return 0, iclass 25, count 2 2006.201.03:41:38.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:38.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:41:38.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.03:41:38.04#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:38.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:38.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:38.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:38.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.03:41:38.16#ibcon#first serial, iclass 25, count 0 2006.201.03:41:38.16#ibcon#enter sib2, iclass 25, count 0 2006.201.03:41:38.16#ibcon#flushed, iclass 25, count 0 2006.201.03:41:38.16#ibcon#about to write, iclass 25, count 0 2006.201.03:41:38.16#ibcon#wrote, iclass 25, count 0 2006.201.03:41:38.16#ibcon#about to read 3, iclass 25, count 0 2006.201.03:41:38.18#ibcon#read 3, iclass 25, count 0 2006.201.03:41:38.18#ibcon#about to read 4, iclass 25, count 0 2006.201.03:41:38.18#ibcon#read 4, iclass 25, count 0 2006.201.03:41:38.18#ibcon#about to read 5, iclass 25, count 0 2006.201.03:41:38.18#ibcon#read 5, iclass 25, count 0 2006.201.03:41:38.18#ibcon#about to read 6, iclass 25, count 0 2006.201.03:41:38.18#ibcon#read 6, iclass 25, count 0 2006.201.03:41:38.18#ibcon#end of sib2, iclass 25, count 0 2006.201.03:41:38.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.03:41:38.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.03:41:38.18#ibcon#[27=USB\r\n] 2006.201.03:41:38.18#ibcon#*before write, iclass 25, count 0 2006.201.03:41:38.18#ibcon#enter sib2, iclass 25, count 0 2006.201.03:41:38.18#ibcon#flushed, iclass 25, count 0 2006.201.03:41:38.18#ibcon#about to write, iclass 25, count 0 2006.201.03:41:38.18#ibcon#wrote, iclass 25, count 0 2006.201.03:41:38.18#ibcon#about to read 3, iclass 25, count 0 2006.201.03:41:38.21#ibcon#read 3, iclass 25, count 0 2006.201.03:41:38.21#ibcon#about to read 4, iclass 25, count 0 2006.201.03:41:38.21#ibcon#read 4, iclass 25, count 0 2006.201.03:41:38.21#ibcon#about to read 5, iclass 25, count 0 2006.201.03:41:38.21#ibcon#read 5, iclass 25, count 0 2006.201.03:41:38.21#ibcon#about to read 6, iclass 25, count 0 2006.201.03:41:38.21#ibcon#read 6, iclass 25, count 0 2006.201.03:41:38.21#ibcon#end of sib2, iclass 25, count 0 2006.201.03:41:38.21#ibcon#*after write, iclass 25, count 0 2006.201.03:41:38.21#ibcon#*before return 0, iclass 25, count 0 2006.201.03:41:38.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:38.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:41:38.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.03:41:38.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.03:41:38.21$vck44/vblo=3,649.99 2006.201.03:41:38.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.03:41:38.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.03:41:38.21#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:38.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:38.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:38.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:38.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.03:41:38.21#ibcon#first serial, iclass 27, count 0 2006.201.03:41:38.21#ibcon#enter sib2, iclass 27, count 0 2006.201.03:41:38.21#ibcon#flushed, iclass 27, count 0 2006.201.03:41:38.21#ibcon#about to write, iclass 27, count 0 2006.201.03:41:38.21#ibcon#wrote, iclass 27, count 0 2006.201.03:41:38.21#ibcon#about to read 3, iclass 27, count 0 2006.201.03:41:38.23#ibcon#read 3, iclass 27, count 0 2006.201.03:41:38.23#ibcon#about to read 4, iclass 27, count 0 2006.201.03:41:38.23#ibcon#read 4, iclass 27, count 0 2006.201.03:41:38.23#ibcon#about to read 5, iclass 27, count 0 2006.201.03:41:38.23#ibcon#read 5, iclass 27, count 0 2006.201.03:41:38.23#ibcon#about to read 6, iclass 27, count 0 2006.201.03:41:38.23#ibcon#read 6, iclass 27, count 0 2006.201.03:41:38.23#ibcon#end of sib2, iclass 27, count 0 2006.201.03:41:38.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.03:41:38.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.03:41:38.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:41:38.23#ibcon#*before write, iclass 27, count 0 2006.201.03:41:38.23#ibcon#enter sib2, iclass 27, count 0 2006.201.03:41:38.23#ibcon#flushed, iclass 27, count 0 2006.201.03:41:38.23#ibcon#about to write, iclass 27, count 0 2006.201.03:41:38.23#ibcon#wrote, iclass 27, count 0 2006.201.03:41:38.23#ibcon#about to read 3, iclass 27, count 0 2006.201.03:41:38.27#ibcon#read 3, iclass 27, count 0 2006.201.03:41:38.27#ibcon#about to read 4, iclass 27, count 0 2006.201.03:41:38.27#ibcon#read 4, iclass 27, count 0 2006.201.03:41:38.27#ibcon#about to read 5, iclass 27, count 0 2006.201.03:41:38.27#ibcon#read 5, iclass 27, count 0 2006.201.03:41:38.27#ibcon#about to read 6, iclass 27, count 0 2006.201.03:41:38.27#ibcon#read 6, iclass 27, count 0 2006.201.03:41:38.27#ibcon#end of sib2, iclass 27, count 0 2006.201.03:41:38.27#ibcon#*after write, iclass 27, count 0 2006.201.03:41:38.27#ibcon#*before return 0, iclass 27, count 0 2006.201.03:41:38.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:38.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:41:38.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.03:41:38.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.03:41:38.27$vck44/vb=3,4 2006.201.03:41:38.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.03:41:38.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.03:41:38.27#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:38.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:38.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:38.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:38.33#ibcon#enter wrdev, iclass 29, count 2 2006.201.03:41:38.33#ibcon#first serial, iclass 29, count 2 2006.201.03:41:38.33#ibcon#enter sib2, iclass 29, count 2 2006.201.03:41:38.33#ibcon#flushed, iclass 29, count 2 2006.201.03:41:38.33#ibcon#about to write, iclass 29, count 2 2006.201.03:41:38.33#ibcon#wrote, iclass 29, count 2 2006.201.03:41:38.33#ibcon#about to read 3, iclass 29, count 2 2006.201.03:41:38.35#ibcon#read 3, iclass 29, count 2 2006.201.03:41:38.35#ibcon#about to read 4, iclass 29, count 2 2006.201.03:41:38.35#ibcon#read 4, iclass 29, count 2 2006.201.03:41:38.35#ibcon#about to read 5, iclass 29, count 2 2006.201.03:41:38.35#ibcon#read 5, iclass 29, count 2 2006.201.03:41:38.35#ibcon#about to read 6, iclass 29, count 2 2006.201.03:41:38.35#ibcon#read 6, iclass 29, count 2 2006.201.03:41:38.35#ibcon#end of sib2, iclass 29, count 2 2006.201.03:41:38.35#ibcon#*mode == 0, iclass 29, count 2 2006.201.03:41:38.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.03:41:38.35#ibcon#[27=AT03-04\r\n] 2006.201.03:41:38.35#ibcon#*before write, iclass 29, count 2 2006.201.03:41:38.35#ibcon#enter sib2, iclass 29, count 2 2006.201.03:41:38.35#ibcon#flushed, iclass 29, count 2 2006.201.03:41:38.35#ibcon#about to write, iclass 29, count 2 2006.201.03:41:38.35#ibcon#wrote, iclass 29, count 2 2006.201.03:41:38.35#ibcon#about to read 3, iclass 29, count 2 2006.201.03:41:38.38#ibcon#read 3, iclass 29, count 2 2006.201.03:41:38.38#ibcon#about to read 4, iclass 29, count 2 2006.201.03:41:38.38#ibcon#read 4, iclass 29, count 2 2006.201.03:41:38.38#ibcon#about to read 5, iclass 29, count 2 2006.201.03:41:38.38#ibcon#read 5, iclass 29, count 2 2006.201.03:41:38.38#ibcon#about to read 6, iclass 29, count 2 2006.201.03:41:38.38#ibcon#read 6, iclass 29, count 2 2006.201.03:41:38.38#ibcon#end of sib2, iclass 29, count 2 2006.201.03:41:38.38#ibcon#*after write, iclass 29, count 2 2006.201.03:41:38.38#ibcon#*before return 0, iclass 29, count 2 2006.201.03:41:38.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:38.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:41:38.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.03:41:38.38#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:38.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:38.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:38.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:38.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.03:41:38.50#ibcon#first serial, iclass 29, count 0 2006.201.03:41:38.50#ibcon#enter sib2, iclass 29, count 0 2006.201.03:41:38.50#ibcon#flushed, iclass 29, count 0 2006.201.03:41:38.50#ibcon#about to write, iclass 29, count 0 2006.201.03:41:38.50#ibcon#wrote, iclass 29, count 0 2006.201.03:41:38.50#ibcon#about to read 3, iclass 29, count 0 2006.201.03:41:38.52#ibcon#read 3, iclass 29, count 0 2006.201.03:41:38.52#ibcon#about to read 4, iclass 29, count 0 2006.201.03:41:38.52#ibcon#read 4, iclass 29, count 0 2006.201.03:41:38.52#ibcon#about to read 5, iclass 29, count 0 2006.201.03:41:38.52#ibcon#read 5, iclass 29, count 0 2006.201.03:41:38.52#ibcon#about to read 6, iclass 29, count 0 2006.201.03:41:38.52#ibcon#read 6, iclass 29, count 0 2006.201.03:41:38.52#ibcon#end of sib2, iclass 29, count 0 2006.201.03:41:38.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.03:41:38.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.03:41:38.52#ibcon#[27=USB\r\n] 2006.201.03:41:38.52#ibcon#*before write, iclass 29, count 0 2006.201.03:41:38.52#ibcon#enter sib2, iclass 29, count 0 2006.201.03:41:38.52#ibcon#flushed, iclass 29, count 0 2006.201.03:41:38.52#ibcon#about to write, iclass 29, count 0 2006.201.03:41:38.52#ibcon#wrote, iclass 29, count 0 2006.201.03:41:38.52#ibcon#about to read 3, iclass 29, count 0 2006.201.03:41:38.55#ibcon#read 3, iclass 29, count 0 2006.201.03:41:38.55#ibcon#about to read 4, iclass 29, count 0 2006.201.03:41:38.55#ibcon#read 4, iclass 29, count 0 2006.201.03:41:38.55#ibcon#about to read 5, iclass 29, count 0 2006.201.03:41:38.55#ibcon#read 5, iclass 29, count 0 2006.201.03:41:38.55#ibcon#about to read 6, iclass 29, count 0 2006.201.03:41:38.55#ibcon#read 6, iclass 29, count 0 2006.201.03:41:38.55#ibcon#end of sib2, iclass 29, count 0 2006.201.03:41:38.55#ibcon#*after write, iclass 29, count 0 2006.201.03:41:38.55#ibcon#*before return 0, iclass 29, count 0 2006.201.03:41:38.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:38.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:41:38.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.03:41:38.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.03:41:38.55$vck44/vblo=4,679.99 2006.201.03:41:38.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.03:41:38.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.03:41:38.55#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:38.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:38.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:38.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:38.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.03:41:38.55#ibcon#first serial, iclass 31, count 0 2006.201.03:41:38.55#ibcon#enter sib2, iclass 31, count 0 2006.201.03:41:38.55#ibcon#flushed, iclass 31, count 0 2006.201.03:41:38.55#ibcon#about to write, iclass 31, count 0 2006.201.03:41:38.55#ibcon#wrote, iclass 31, count 0 2006.201.03:41:38.55#ibcon#about to read 3, iclass 31, count 0 2006.201.03:41:38.57#ibcon#read 3, iclass 31, count 0 2006.201.03:41:38.57#ibcon#about to read 4, iclass 31, count 0 2006.201.03:41:38.57#ibcon#read 4, iclass 31, count 0 2006.201.03:41:38.57#ibcon#about to read 5, iclass 31, count 0 2006.201.03:41:38.57#ibcon#read 5, iclass 31, count 0 2006.201.03:41:38.57#ibcon#about to read 6, iclass 31, count 0 2006.201.03:41:38.57#ibcon#read 6, iclass 31, count 0 2006.201.03:41:38.57#ibcon#end of sib2, iclass 31, count 0 2006.201.03:41:38.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.03:41:38.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.03:41:38.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:41:38.57#ibcon#*before write, iclass 31, count 0 2006.201.03:41:38.57#ibcon#enter sib2, iclass 31, count 0 2006.201.03:41:38.57#ibcon#flushed, iclass 31, count 0 2006.201.03:41:38.57#ibcon#about to write, iclass 31, count 0 2006.201.03:41:38.57#ibcon#wrote, iclass 31, count 0 2006.201.03:41:38.57#ibcon#about to read 3, iclass 31, count 0 2006.201.03:41:38.61#ibcon#read 3, iclass 31, count 0 2006.201.03:41:38.61#ibcon#about to read 4, iclass 31, count 0 2006.201.03:41:38.61#ibcon#read 4, iclass 31, count 0 2006.201.03:41:38.61#ibcon#about to read 5, iclass 31, count 0 2006.201.03:41:38.61#ibcon#read 5, iclass 31, count 0 2006.201.03:41:38.61#ibcon#about to read 6, iclass 31, count 0 2006.201.03:41:38.61#ibcon#read 6, iclass 31, count 0 2006.201.03:41:38.61#ibcon#end of sib2, iclass 31, count 0 2006.201.03:41:38.61#ibcon#*after write, iclass 31, count 0 2006.201.03:41:38.61#ibcon#*before return 0, iclass 31, count 0 2006.201.03:41:38.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:38.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:41:38.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.03:41:38.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.03:41:38.61$vck44/vb=4,5 2006.201.03:41:38.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.03:41:38.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.03:41:38.61#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:38.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:38.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:38.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:38.67#ibcon#enter wrdev, iclass 33, count 2 2006.201.03:41:38.67#ibcon#first serial, iclass 33, count 2 2006.201.03:41:38.67#ibcon#enter sib2, iclass 33, count 2 2006.201.03:41:38.67#ibcon#flushed, iclass 33, count 2 2006.201.03:41:38.67#ibcon#about to write, iclass 33, count 2 2006.201.03:41:38.67#ibcon#wrote, iclass 33, count 2 2006.201.03:41:38.67#ibcon#about to read 3, iclass 33, count 2 2006.201.03:41:38.69#ibcon#read 3, iclass 33, count 2 2006.201.03:41:38.69#ibcon#about to read 4, iclass 33, count 2 2006.201.03:41:38.69#ibcon#read 4, iclass 33, count 2 2006.201.03:41:38.69#ibcon#about to read 5, iclass 33, count 2 2006.201.03:41:38.69#ibcon#read 5, iclass 33, count 2 2006.201.03:41:38.69#ibcon#about to read 6, iclass 33, count 2 2006.201.03:41:38.69#ibcon#read 6, iclass 33, count 2 2006.201.03:41:38.69#ibcon#end of sib2, iclass 33, count 2 2006.201.03:41:38.69#ibcon#*mode == 0, iclass 33, count 2 2006.201.03:41:38.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.03:41:38.69#ibcon#[27=AT04-05\r\n] 2006.201.03:41:38.69#ibcon#*before write, iclass 33, count 2 2006.201.03:41:38.69#ibcon#enter sib2, iclass 33, count 2 2006.201.03:41:38.69#ibcon#flushed, iclass 33, count 2 2006.201.03:41:38.69#ibcon#about to write, iclass 33, count 2 2006.201.03:41:38.69#ibcon#wrote, iclass 33, count 2 2006.201.03:41:38.69#ibcon#about to read 3, iclass 33, count 2 2006.201.03:41:38.72#ibcon#read 3, iclass 33, count 2 2006.201.03:41:38.72#ibcon#about to read 4, iclass 33, count 2 2006.201.03:41:38.72#ibcon#read 4, iclass 33, count 2 2006.201.03:41:38.72#ibcon#about to read 5, iclass 33, count 2 2006.201.03:41:38.72#ibcon#read 5, iclass 33, count 2 2006.201.03:41:38.72#ibcon#about to read 6, iclass 33, count 2 2006.201.03:41:38.72#ibcon#read 6, iclass 33, count 2 2006.201.03:41:38.72#ibcon#end of sib2, iclass 33, count 2 2006.201.03:41:38.72#ibcon#*after write, iclass 33, count 2 2006.201.03:41:38.72#ibcon#*before return 0, iclass 33, count 2 2006.201.03:41:38.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:38.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:41:38.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.03:41:38.72#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:38.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:38.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:38.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:38.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.03:41:38.84#ibcon#first serial, iclass 33, count 0 2006.201.03:41:38.84#ibcon#enter sib2, iclass 33, count 0 2006.201.03:41:38.84#ibcon#flushed, iclass 33, count 0 2006.201.03:41:38.84#ibcon#about to write, iclass 33, count 0 2006.201.03:41:38.84#ibcon#wrote, iclass 33, count 0 2006.201.03:41:38.84#ibcon#about to read 3, iclass 33, count 0 2006.201.03:41:38.86#ibcon#read 3, iclass 33, count 0 2006.201.03:41:38.86#ibcon#about to read 4, iclass 33, count 0 2006.201.03:41:38.86#ibcon#read 4, iclass 33, count 0 2006.201.03:41:38.86#ibcon#about to read 5, iclass 33, count 0 2006.201.03:41:38.86#ibcon#read 5, iclass 33, count 0 2006.201.03:41:38.86#ibcon#about to read 6, iclass 33, count 0 2006.201.03:41:38.86#ibcon#read 6, iclass 33, count 0 2006.201.03:41:38.86#ibcon#end of sib2, iclass 33, count 0 2006.201.03:41:38.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.03:41:38.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.03:41:38.86#ibcon#[27=USB\r\n] 2006.201.03:41:38.86#ibcon#*before write, iclass 33, count 0 2006.201.03:41:38.86#ibcon#enter sib2, iclass 33, count 0 2006.201.03:41:38.86#ibcon#flushed, iclass 33, count 0 2006.201.03:41:38.86#ibcon#about to write, iclass 33, count 0 2006.201.03:41:38.86#ibcon#wrote, iclass 33, count 0 2006.201.03:41:38.86#ibcon#about to read 3, iclass 33, count 0 2006.201.03:41:38.89#ibcon#read 3, iclass 33, count 0 2006.201.03:41:38.89#ibcon#about to read 4, iclass 33, count 0 2006.201.03:41:38.89#ibcon#read 4, iclass 33, count 0 2006.201.03:41:38.89#ibcon#about to read 5, iclass 33, count 0 2006.201.03:41:38.89#ibcon#read 5, iclass 33, count 0 2006.201.03:41:38.89#ibcon#about to read 6, iclass 33, count 0 2006.201.03:41:38.89#ibcon#read 6, iclass 33, count 0 2006.201.03:41:38.89#ibcon#end of sib2, iclass 33, count 0 2006.201.03:41:38.89#ibcon#*after write, iclass 33, count 0 2006.201.03:41:38.89#ibcon#*before return 0, iclass 33, count 0 2006.201.03:41:38.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:38.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:41:38.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.03:41:38.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.03:41:38.89$vck44/vblo=5,709.99 2006.201.03:41:38.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.03:41:38.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.03:41:38.89#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:38.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:38.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:38.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:38.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.03:41:38.89#ibcon#first serial, iclass 35, count 0 2006.201.03:41:38.89#ibcon#enter sib2, iclass 35, count 0 2006.201.03:41:38.89#ibcon#flushed, iclass 35, count 0 2006.201.03:41:38.89#ibcon#about to write, iclass 35, count 0 2006.201.03:41:38.89#ibcon#wrote, iclass 35, count 0 2006.201.03:41:38.89#ibcon#about to read 3, iclass 35, count 0 2006.201.03:41:38.91#ibcon#read 3, iclass 35, count 0 2006.201.03:41:38.91#ibcon#about to read 4, iclass 35, count 0 2006.201.03:41:38.91#ibcon#read 4, iclass 35, count 0 2006.201.03:41:38.91#ibcon#about to read 5, iclass 35, count 0 2006.201.03:41:38.91#ibcon#read 5, iclass 35, count 0 2006.201.03:41:38.91#ibcon#about to read 6, iclass 35, count 0 2006.201.03:41:38.91#ibcon#read 6, iclass 35, count 0 2006.201.03:41:38.91#ibcon#end of sib2, iclass 35, count 0 2006.201.03:41:38.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.03:41:38.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.03:41:38.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:41:38.91#ibcon#*before write, iclass 35, count 0 2006.201.03:41:38.91#ibcon#enter sib2, iclass 35, count 0 2006.201.03:41:38.91#ibcon#flushed, iclass 35, count 0 2006.201.03:41:38.91#ibcon#about to write, iclass 35, count 0 2006.201.03:41:38.91#ibcon#wrote, iclass 35, count 0 2006.201.03:41:38.91#ibcon#about to read 3, iclass 35, count 0 2006.201.03:41:38.95#ibcon#read 3, iclass 35, count 0 2006.201.03:41:38.95#ibcon#about to read 4, iclass 35, count 0 2006.201.03:41:38.95#ibcon#read 4, iclass 35, count 0 2006.201.03:41:38.95#ibcon#about to read 5, iclass 35, count 0 2006.201.03:41:38.95#ibcon#read 5, iclass 35, count 0 2006.201.03:41:38.95#ibcon#about to read 6, iclass 35, count 0 2006.201.03:41:38.95#ibcon#read 6, iclass 35, count 0 2006.201.03:41:38.95#ibcon#end of sib2, iclass 35, count 0 2006.201.03:41:38.95#ibcon#*after write, iclass 35, count 0 2006.201.03:41:38.95#ibcon#*before return 0, iclass 35, count 0 2006.201.03:41:38.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:38.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:41:38.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.03:41:38.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.03:41:38.95$vck44/vb=5,4 2006.201.03:41:38.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.03:41:38.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.03:41:38.95#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:38.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:39.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:39.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:39.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.03:41:39.01#ibcon#first serial, iclass 37, count 2 2006.201.03:41:39.01#ibcon#enter sib2, iclass 37, count 2 2006.201.03:41:39.01#ibcon#flushed, iclass 37, count 2 2006.201.03:41:39.01#ibcon#about to write, iclass 37, count 2 2006.201.03:41:39.01#ibcon#wrote, iclass 37, count 2 2006.201.03:41:39.01#ibcon#about to read 3, iclass 37, count 2 2006.201.03:41:39.03#ibcon#read 3, iclass 37, count 2 2006.201.03:41:39.03#ibcon#about to read 4, iclass 37, count 2 2006.201.03:41:39.03#ibcon#read 4, iclass 37, count 2 2006.201.03:41:39.03#ibcon#about to read 5, iclass 37, count 2 2006.201.03:41:39.03#ibcon#read 5, iclass 37, count 2 2006.201.03:41:39.03#ibcon#about to read 6, iclass 37, count 2 2006.201.03:41:39.03#ibcon#read 6, iclass 37, count 2 2006.201.03:41:39.03#ibcon#end of sib2, iclass 37, count 2 2006.201.03:41:39.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.03:41:39.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.03:41:39.03#ibcon#[27=AT05-04\r\n] 2006.201.03:41:39.03#ibcon#*before write, iclass 37, count 2 2006.201.03:41:39.03#ibcon#enter sib2, iclass 37, count 2 2006.201.03:41:39.03#ibcon#flushed, iclass 37, count 2 2006.201.03:41:39.03#ibcon#about to write, iclass 37, count 2 2006.201.03:41:39.03#ibcon#wrote, iclass 37, count 2 2006.201.03:41:39.03#ibcon#about to read 3, iclass 37, count 2 2006.201.03:41:39.06#ibcon#read 3, iclass 37, count 2 2006.201.03:41:39.06#ibcon#about to read 4, iclass 37, count 2 2006.201.03:41:39.06#ibcon#read 4, iclass 37, count 2 2006.201.03:41:39.06#ibcon#about to read 5, iclass 37, count 2 2006.201.03:41:39.06#ibcon#read 5, iclass 37, count 2 2006.201.03:41:39.06#ibcon#about to read 6, iclass 37, count 2 2006.201.03:41:39.06#ibcon#read 6, iclass 37, count 2 2006.201.03:41:39.06#ibcon#end of sib2, iclass 37, count 2 2006.201.03:41:39.06#ibcon#*after write, iclass 37, count 2 2006.201.03:41:39.06#ibcon#*before return 0, iclass 37, count 2 2006.201.03:41:39.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:39.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:41:39.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.03:41:39.06#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:39.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:39.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:39.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:39.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.03:41:39.18#ibcon#first serial, iclass 37, count 0 2006.201.03:41:39.18#ibcon#enter sib2, iclass 37, count 0 2006.201.03:41:39.18#ibcon#flushed, iclass 37, count 0 2006.201.03:41:39.18#ibcon#about to write, iclass 37, count 0 2006.201.03:41:39.18#ibcon#wrote, iclass 37, count 0 2006.201.03:41:39.18#ibcon#about to read 3, iclass 37, count 0 2006.201.03:41:39.21#ibcon#read 3, iclass 37, count 0 2006.201.03:41:39.21#ibcon#about to read 4, iclass 37, count 0 2006.201.03:41:39.21#ibcon#read 4, iclass 37, count 0 2006.201.03:41:39.21#ibcon#about to read 5, iclass 37, count 0 2006.201.03:41:39.21#ibcon#read 5, iclass 37, count 0 2006.201.03:41:39.21#ibcon#about to read 6, iclass 37, count 0 2006.201.03:41:39.21#ibcon#read 6, iclass 37, count 0 2006.201.03:41:39.21#ibcon#end of sib2, iclass 37, count 0 2006.201.03:41:39.21#ibcon#*mode == 0, iclass 37, count 0 2006.201.03:41:39.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.03:41:39.21#ibcon#[27=USB\r\n] 2006.201.03:41:39.21#ibcon#*before write, iclass 37, count 0 2006.201.03:41:39.21#ibcon#enter sib2, iclass 37, count 0 2006.201.03:41:39.21#ibcon#flushed, iclass 37, count 0 2006.201.03:41:39.21#ibcon#about to write, iclass 37, count 0 2006.201.03:41:39.21#ibcon#wrote, iclass 37, count 0 2006.201.03:41:39.21#ibcon#about to read 3, iclass 37, count 0 2006.201.03:41:39.24#ibcon#read 3, iclass 37, count 0 2006.201.03:41:39.24#ibcon#about to read 4, iclass 37, count 0 2006.201.03:41:39.24#ibcon#read 4, iclass 37, count 0 2006.201.03:41:39.24#ibcon#about to read 5, iclass 37, count 0 2006.201.03:41:39.24#ibcon#read 5, iclass 37, count 0 2006.201.03:41:39.24#ibcon#about to read 6, iclass 37, count 0 2006.201.03:41:39.24#ibcon#read 6, iclass 37, count 0 2006.201.03:41:39.24#ibcon#end of sib2, iclass 37, count 0 2006.201.03:41:39.24#ibcon#*after write, iclass 37, count 0 2006.201.03:41:39.24#ibcon#*before return 0, iclass 37, count 0 2006.201.03:41:39.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:39.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:41:39.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.03:41:39.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.03:41:39.24$vck44/vblo=6,719.99 2006.201.03:41:39.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.03:41:39.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.03:41:39.24#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:39.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:39.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:39.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:39.24#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:41:39.24#ibcon#first serial, iclass 39, count 0 2006.201.03:41:39.24#ibcon#enter sib2, iclass 39, count 0 2006.201.03:41:39.24#ibcon#flushed, iclass 39, count 0 2006.201.03:41:39.24#ibcon#about to write, iclass 39, count 0 2006.201.03:41:39.24#ibcon#wrote, iclass 39, count 0 2006.201.03:41:39.24#ibcon#about to read 3, iclass 39, count 0 2006.201.03:41:39.26#ibcon#read 3, iclass 39, count 0 2006.201.03:41:39.26#ibcon#about to read 4, iclass 39, count 0 2006.201.03:41:39.26#ibcon#read 4, iclass 39, count 0 2006.201.03:41:39.26#ibcon#about to read 5, iclass 39, count 0 2006.201.03:41:39.26#ibcon#read 5, iclass 39, count 0 2006.201.03:41:39.26#ibcon#about to read 6, iclass 39, count 0 2006.201.03:41:39.26#ibcon#read 6, iclass 39, count 0 2006.201.03:41:39.26#ibcon#end of sib2, iclass 39, count 0 2006.201.03:41:39.26#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:41:39.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:41:39.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:41:39.26#ibcon#*before write, iclass 39, count 0 2006.201.03:41:39.26#ibcon#enter sib2, iclass 39, count 0 2006.201.03:41:39.26#ibcon#flushed, iclass 39, count 0 2006.201.03:41:39.26#ibcon#about to write, iclass 39, count 0 2006.201.03:41:39.26#ibcon#wrote, iclass 39, count 0 2006.201.03:41:39.26#ibcon#about to read 3, iclass 39, count 0 2006.201.03:41:39.30#ibcon#read 3, iclass 39, count 0 2006.201.03:41:39.30#ibcon#about to read 4, iclass 39, count 0 2006.201.03:41:39.30#ibcon#read 4, iclass 39, count 0 2006.201.03:41:39.30#ibcon#about to read 5, iclass 39, count 0 2006.201.03:41:39.30#ibcon#read 5, iclass 39, count 0 2006.201.03:41:39.30#ibcon#about to read 6, iclass 39, count 0 2006.201.03:41:39.30#ibcon#read 6, iclass 39, count 0 2006.201.03:41:39.30#ibcon#end of sib2, iclass 39, count 0 2006.201.03:41:39.30#ibcon#*after write, iclass 39, count 0 2006.201.03:41:39.30#ibcon#*before return 0, iclass 39, count 0 2006.201.03:41:39.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:39.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:41:39.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:41:39.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:41:39.30$vck44/vb=6,4 2006.201.03:41:39.30#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.03:41:39.30#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.03:41:39.30#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:39.30#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:39.36#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:39.36#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:39.36#ibcon#enter wrdev, iclass 2, count 2 2006.201.03:41:39.36#ibcon#first serial, iclass 2, count 2 2006.201.03:41:39.36#ibcon#enter sib2, iclass 2, count 2 2006.201.03:41:39.36#ibcon#flushed, iclass 2, count 2 2006.201.03:41:39.36#ibcon#about to write, iclass 2, count 2 2006.201.03:41:39.36#ibcon#wrote, iclass 2, count 2 2006.201.03:41:39.36#ibcon#about to read 3, iclass 2, count 2 2006.201.03:41:39.38#ibcon#read 3, iclass 2, count 2 2006.201.03:41:39.38#ibcon#about to read 4, iclass 2, count 2 2006.201.03:41:39.38#ibcon#read 4, iclass 2, count 2 2006.201.03:41:39.38#ibcon#about to read 5, iclass 2, count 2 2006.201.03:41:39.38#ibcon#read 5, iclass 2, count 2 2006.201.03:41:39.38#ibcon#about to read 6, iclass 2, count 2 2006.201.03:41:39.38#ibcon#read 6, iclass 2, count 2 2006.201.03:41:39.38#ibcon#end of sib2, iclass 2, count 2 2006.201.03:41:39.38#ibcon#*mode == 0, iclass 2, count 2 2006.201.03:41:39.38#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.03:41:39.38#ibcon#[27=AT06-04\r\n] 2006.201.03:41:39.38#ibcon#*before write, iclass 2, count 2 2006.201.03:41:39.38#ibcon#enter sib2, iclass 2, count 2 2006.201.03:41:39.38#ibcon#flushed, iclass 2, count 2 2006.201.03:41:39.38#ibcon#about to write, iclass 2, count 2 2006.201.03:41:39.38#ibcon#wrote, iclass 2, count 2 2006.201.03:41:39.38#ibcon#about to read 3, iclass 2, count 2 2006.201.03:41:39.41#ibcon#read 3, iclass 2, count 2 2006.201.03:41:39.41#ibcon#about to read 4, iclass 2, count 2 2006.201.03:41:39.41#ibcon#read 4, iclass 2, count 2 2006.201.03:41:39.41#ibcon#about to read 5, iclass 2, count 2 2006.201.03:41:39.41#ibcon#read 5, iclass 2, count 2 2006.201.03:41:39.41#ibcon#about to read 6, iclass 2, count 2 2006.201.03:41:39.41#ibcon#read 6, iclass 2, count 2 2006.201.03:41:39.41#ibcon#end of sib2, iclass 2, count 2 2006.201.03:41:39.41#ibcon#*after write, iclass 2, count 2 2006.201.03:41:39.41#ibcon#*before return 0, iclass 2, count 2 2006.201.03:41:39.41#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:39.41#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:41:39.41#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.03:41:39.41#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:39.41#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:39.53#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:39.53#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:39.53#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:41:39.53#ibcon#first serial, iclass 2, count 0 2006.201.03:41:39.53#ibcon#enter sib2, iclass 2, count 0 2006.201.03:41:39.53#ibcon#flushed, iclass 2, count 0 2006.201.03:41:39.53#ibcon#about to write, iclass 2, count 0 2006.201.03:41:39.53#ibcon#wrote, iclass 2, count 0 2006.201.03:41:39.53#ibcon#about to read 3, iclass 2, count 0 2006.201.03:41:39.55#ibcon#read 3, iclass 2, count 0 2006.201.03:41:39.55#ibcon#about to read 4, iclass 2, count 0 2006.201.03:41:39.55#ibcon#read 4, iclass 2, count 0 2006.201.03:41:39.55#ibcon#about to read 5, iclass 2, count 0 2006.201.03:41:39.55#ibcon#read 5, iclass 2, count 0 2006.201.03:41:39.55#ibcon#about to read 6, iclass 2, count 0 2006.201.03:41:39.55#ibcon#read 6, iclass 2, count 0 2006.201.03:41:39.55#ibcon#end of sib2, iclass 2, count 0 2006.201.03:41:39.55#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:41:39.55#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:41:39.55#ibcon#[27=USB\r\n] 2006.201.03:41:39.55#ibcon#*before write, iclass 2, count 0 2006.201.03:41:39.55#ibcon#enter sib2, iclass 2, count 0 2006.201.03:41:39.55#ibcon#flushed, iclass 2, count 0 2006.201.03:41:39.55#ibcon#about to write, iclass 2, count 0 2006.201.03:41:39.55#ibcon#wrote, iclass 2, count 0 2006.201.03:41:39.55#ibcon#about to read 3, iclass 2, count 0 2006.201.03:41:39.58#ibcon#read 3, iclass 2, count 0 2006.201.03:41:39.58#ibcon#about to read 4, iclass 2, count 0 2006.201.03:41:39.58#ibcon#read 4, iclass 2, count 0 2006.201.03:41:39.58#ibcon#about to read 5, iclass 2, count 0 2006.201.03:41:39.58#ibcon#read 5, iclass 2, count 0 2006.201.03:41:39.58#ibcon#about to read 6, iclass 2, count 0 2006.201.03:41:39.58#ibcon#read 6, iclass 2, count 0 2006.201.03:41:39.58#ibcon#end of sib2, iclass 2, count 0 2006.201.03:41:39.58#ibcon#*after write, iclass 2, count 0 2006.201.03:41:39.58#ibcon#*before return 0, iclass 2, count 0 2006.201.03:41:39.58#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:39.58#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:41:39.58#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:41:39.58#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:41:39.58$vck44/vblo=7,734.99 2006.201.03:41:39.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.03:41:39.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.03:41:39.58#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:39.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:39.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:39.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:39.58#ibcon#enter wrdev, iclass 5, count 0 2006.201.03:41:39.58#ibcon#first serial, iclass 5, count 0 2006.201.03:41:39.58#ibcon#enter sib2, iclass 5, count 0 2006.201.03:41:39.58#ibcon#flushed, iclass 5, count 0 2006.201.03:41:39.58#ibcon#about to write, iclass 5, count 0 2006.201.03:41:39.58#ibcon#wrote, iclass 5, count 0 2006.201.03:41:39.58#ibcon#about to read 3, iclass 5, count 0 2006.201.03:41:39.60#ibcon#read 3, iclass 5, count 0 2006.201.03:41:39.60#ibcon#about to read 4, iclass 5, count 0 2006.201.03:41:39.60#ibcon#read 4, iclass 5, count 0 2006.201.03:41:39.60#ibcon#about to read 5, iclass 5, count 0 2006.201.03:41:39.60#ibcon#read 5, iclass 5, count 0 2006.201.03:41:39.60#ibcon#about to read 6, iclass 5, count 0 2006.201.03:41:39.60#ibcon#read 6, iclass 5, count 0 2006.201.03:41:39.60#ibcon#end of sib2, iclass 5, count 0 2006.201.03:41:39.60#ibcon#*mode == 0, iclass 5, count 0 2006.201.03:41:39.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.03:41:39.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:41:39.60#ibcon#*before write, iclass 5, count 0 2006.201.03:41:39.60#ibcon#enter sib2, iclass 5, count 0 2006.201.03:41:39.60#ibcon#flushed, iclass 5, count 0 2006.201.03:41:39.60#ibcon#about to write, iclass 5, count 0 2006.201.03:41:39.60#ibcon#wrote, iclass 5, count 0 2006.201.03:41:39.60#ibcon#about to read 3, iclass 5, count 0 2006.201.03:41:39.64#ibcon#read 3, iclass 5, count 0 2006.201.03:41:39.64#ibcon#about to read 4, iclass 5, count 0 2006.201.03:41:39.64#ibcon#read 4, iclass 5, count 0 2006.201.03:41:39.64#ibcon#about to read 5, iclass 5, count 0 2006.201.03:41:39.64#ibcon#read 5, iclass 5, count 0 2006.201.03:41:39.64#ibcon#about to read 6, iclass 5, count 0 2006.201.03:41:39.64#ibcon#read 6, iclass 5, count 0 2006.201.03:41:39.64#ibcon#end of sib2, iclass 5, count 0 2006.201.03:41:39.64#ibcon#*after write, iclass 5, count 0 2006.201.03:41:39.64#ibcon#*before return 0, iclass 5, count 0 2006.201.03:41:39.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:39.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:41:39.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.03:41:39.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.03:41:39.64$vck44/vb=7,4 2006.201.03:41:39.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.03:41:39.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.03:41:39.64#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:39.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:39.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:39.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:39.70#ibcon#enter wrdev, iclass 7, count 2 2006.201.03:41:39.70#ibcon#first serial, iclass 7, count 2 2006.201.03:41:39.70#ibcon#enter sib2, iclass 7, count 2 2006.201.03:41:39.70#ibcon#flushed, iclass 7, count 2 2006.201.03:41:39.70#ibcon#about to write, iclass 7, count 2 2006.201.03:41:39.70#ibcon#wrote, iclass 7, count 2 2006.201.03:41:39.70#ibcon#about to read 3, iclass 7, count 2 2006.201.03:41:39.72#ibcon#read 3, iclass 7, count 2 2006.201.03:41:39.72#ibcon#about to read 4, iclass 7, count 2 2006.201.03:41:39.72#ibcon#read 4, iclass 7, count 2 2006.201.03:41:39.72#ibcon#about to read 5, iclass 7, count 2 2006.201.03:41:39.72#ibcon#read 5, iclass 7, count 2 2006.201.03:41:39.72#ibcon#about to read 6, iclass 7, count 2 2006.201.03:41:39.72#ibcon#read 6, iclass 7, count 2 2006.201.03:41:39.72#ibcon#end of sib2, iclass 7, count 2 2006.201.03:41:39.72#ibcon#*mode == 0, iclass 7, count 2 2006.201.03:41:39.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.03:41:39.72#ibcon#[27=AT07-04\r\n] 2006.201.03:41:39.72#ibcon#*before write, iclass 7, count 2 2006.201.03:41:39.72#ibcon#enter sib2, iclass 7, count 2 2006.201.03:41:39.72#ibcon#flushed, iclass 7, count 2 2006.201.03:41:39.72#ibcon#about to write, iclass 7, count 2 2006.201.03:41:39.72#ibcon#wrote, iclass 7, count 2 2006.201.03:41:39.72#ibcon#about to read 3, iclass 7, count 2 2006.201.03:41:39.75#ibcon#read 3, iclass 7, count 2 2006.201.03:41:39.75#ibcon#about to read 4, iclass 7, count 2 2006.201.03:41:39.75#ibcon#read 4, iclass 7, count 2 2006.201.03:41:39.75#ibcon#about to read 5, iclass 7, count 2 2006.201.03:41:39.75#ibcon#read 5, iclass 7, count 2 2006.201.03:41:39.75#ibcon#about to read 6, iclass 7, count 2 2006.201.03:41:39.75#ibcon#read 6, iclass 7, count 2 2006.201.03:41:39.75#ibcon#end of sib2, iclass 7, count 2 2006.201.03:41:39.75#ibcon#*after write, iclass 7, count 2 2006.201.03:41:39.75#ibcon#*before return 0, iclass 7, count 2 2006.201.03:41:39.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:39.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:41:39.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.03:41:39.75#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:39.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:39.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:39.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:39.87#ibcon#enter wrdev, iclass 7, count 0 2006.201.03:41:39.87#ibcon#first serial, iclass 7, count 0 2006.201.03:41:39.87#ibcon#enter sib2, iclass 7, count 0 2006.201.03:41:39.87#ibcon#flushed, iclass 7, count 0 2006.201.03:41:39.87#ibcon#about to write, iclass 7, count 0 2006.201.03:41:39.87#ibcon#wrote, iclass 7, count 0 2006.201.03:41:39.87#ibcon#about to read 3, iclass 7, count 0 2006.201.03:41:39.89#ibcon#read 3, iclass 7, count 0 2006.201.03:41:39.89#ibcon#about to read 4, iclass 7, count 0 2006.201.03:41:39.89#ibcon#read 4, iclass 7, count 0 2006.201.03:41:39.89#ibcon#about to read 5, iclass 7, count 0 2006.201.03:41:39.89#ibcon#read 5, iclass 7, count 0 2006.201.03:41:39.89#ibcon#about to read 6, iclass 7, count 0 2006.201.03:41:39.89#ibcon#read 6, iclass 7, count 0 2006.201.03:41:39.89#ibcon#end of sib2, iclass 7, count 0 2006.201.03:41:39.89#ibcon#*mode == 0, iclass 7, count 0 2006.201.03:41:39.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.03:41:39.89#ibcon#[27=USB\r\n] 2006.201.03:41:39.89#ibcon#*before write, iclass 7, count 0 2006.201.03:41:39.89#ibcon#enter sib2, iclass 7, count 0 2006.201.03:41:39.89#ibcon#flushed, iclass 7, count 0 2006.201.03:41:39.89#ibcon#about to write, iclass 7, count 0 2006.201.03:41:39.89#ibcon#wrote, iclass 7, count 0 2006.201.03:41:39.89#ibcon#about to read 3, iclass 7, count 0 2006.201.03:41:39.92#ibcon#read 3, iclass 7, count 0 2006.201.03:41:39.92#ibcon#about to read 4, iclass 7, count 0 2006.201.03:41:39.92#ibcon#read 4, iclass 7, count 0 2006.201.03:41:39.92#ibcon#about to read 5, iclass 7, count 0 2006.201.03:41:39.92#ibcon#read 5, iclass 7, count 0 2006.201.03:41:39.92#ibcon#about to read 6, iclass 7, count 0 2006.201.03:41:39.92#ibcon#read 6, iclass 7, count 0 2006.201.03:41:39.92#ibcon#end of sib2, iclass 7, count 0 2006.201.03:41:39.92#ibcon#*after write, iclass 7, count 0 2006.201.03:41:39.92#ibcon#*before return 0, iclass 7, count 0 2006.201.03:41:39.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:39.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:41:39.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.03:41:39.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.03:41:39.92$vck44/vblo=8,744.99 2006.201.03:41:39.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.03:41:39.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.03:41:39.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:41:39.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:39.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:39.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:39.92#ibcon#enter wrdev, iclass 11, count 0 2006.201.03:41:39.92#ibcon#first serial, iclass 11, count 0 2006.201.03:41:39.92#ibcon#enter sib2, iclass 11, count 0 2006.201.03:41:39.92#ibcon#flushed, iclass 11, count 0 2006.201.03:41:39.92#ibcon#about to write, iclass 11, count 0 2006.201.03:41:39.92#ibcon#wrote, iclass 11, count 0 2006.201.03:41:39.92#ibcon#about to read 3, iclass 11, count 0 2006.201.03:41:39.94#ibcon#read 3, iclass 11, count 0 2006.201.03:41:39.94#ibcon#about to read 4, iclass 11, count 0 2006.201.03:41:39.94#ibcon#read 4, iclass 11, count 0 2006.201.03:41:39.94#ibcon#about to read 5, iclass 11, count 0 2006.201.03:41:39.94#ibcon#read 5, iclass 11, count 0 2006.201.03:41:39.94#ibcon#about to read 6, iclass 11, count 0 2006.201.03:41:39.94#ibcon#read 6, iclass 11, count 0 2006.201.03:41:39.94#ibcon#end of sib2, iclass 11, count 0 2006.201.03:41:39.94#ibcon#*mode == 0, iclass 11, count 0 2006.201.03:41:39.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.03:41:39.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:41:39.94#ibcon#*before write, iclass 11, count 0 2006.201.03:41:39.94#ibcon#enter sib2, iclass 11, count 0 2006.201.03:41:39.94#ibcon#flushed, iclass 11, count 0 2006.201.03:41:39.94#ibcon#about to write, iclass 11, count 0 2006.201.03:41:39.94#ibcon#wrote, iclass 11, count 0 2006.201.03:41:39.94#ibcon#about to read 3, iclass 11, count 0 2006.201.03:41:39.99#ibcon#read 3, iclass 11, count 0 2006.201.03:41:39.99#ibcon#about to read 4, iclass 11, count 0 2006.201.03:41:39.99#ibcon#read 4, iclass 11, count 0 2006.201.03:41:39.99#ibcon#about to read 5, iclass 11, count 0 2006.201.03:41:39.99#ibcon#read 5, iclass 11, count 0 2006.201.03:41:39.99#ibcon#about to read 6, iclass 11, count 0 2006.201.03:41:39.99#ibcon#read 6, iclass 11, count 0 2006.201.03:41:39.99#ibcon#end of sib2, iclass 11, count 0 2006.201.03:41:39.99#ibcon#*after write, iclass 11, count 0 2006.201.03:41:39.99#ibcon#*before return 0, iclass 11, count 0 2006.201.03:41:39.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:39.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:41:39.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.03:41:39.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.03:41:39.99$vck44/vb=8,4 2006.201.03:41:39.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.03:41:39.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.03:41:39.99#ibcon#ireg 11 cls_cnt 2 2006.201.03:41:39.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:40.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:40.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:40.04#ibcon#enter wrdev, iclass 13, count 2 2006.201.03:41:40.04#ibcon#first serial, iclass 13, count 2 2006.201.03:41:40.04#ibcon#enter sib2, iclass 13, count 2 2006.201.03:41:40.04#ibcon#flushed, iclass 13, count 2 2006.201.03:41:40.04#ibcon#about to write, iclass 13, count 2 2006.201.03:41:40.04#ibcon#wrote, iclass 13, count 2 2006.201.03:41:40.04#ibcon#about to read 3, iclass 13, count 2 2006.201.03:41:40.06#ibcon#read 3, iclass 13, count 2 2006.201.03:41:40.06#ibcon#about to read 4, iclass 13, count 2 2006.201.03:41:40.06#ibcon#read 4, iclass 13, count 2 2006.201.03:41:40.06#ibcon#about to read 5, iclass 13, count 2 2006.201.03:41:40.06#ibcon#read 5, iclass 13, count 2 2006.201.03:41:40.06#ibcon#about to read 6, iclass 13, count 2 2006.201.03:41:40.06#ibcon#read 6, iclass 13, count 2 2006.201.03:41:40.06#ibcon#end of sib2, iclass 13, count 2 2006.201.03:41:40.06#ibcon#*mode == 0, iclass 13, count 2 2006.201.03:41:40.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.03:41:40.06#ibcon#[27=AT08-04\r\n] 2006.201.03:41:40.06#ibcon#*before write, iclass 13, count 2 2006.201.03:41:40.06#ibcon#enter sib2, iclass 13, count 2 2006.201.03:41:40.06#ibcon#flushed, iclass 13, count 2 2006.201.03:41:40.06#ibcon#about to write, iclass 13, count 2 2006.201.03:41:40.06#ibcon#wrote, iclass 13, count 2 2006.201.03:41:40.06#ibcon#about to read 3, iclass 13, count 2 2006.201.03:41:40.09#ibcon#read 3, iclass 13, count 2 2006.201.03:41:40.09#ibcon#about to read 4, iclass 13, count 2 2006.201.03:41:40.09#ibcon#read 4, iclass 13, count 2 2006.201.03:41:40.09#ibcon#about to read 5, iclass 13, count 2 2006.201.03:41:40.09#ibcon#read 5, iclass 13, count 2 2006.201.03:41:40.09#ibcon#about to read 6, iclass 13, count 2 2006.201.03:41:40.09#ibcon#read 6, iclass 13, count 2 2006.201.03:41:40.09#ibcon#end of sib2, iclass 13, count 2 2006.201.03:41:40.09#ibcon#*after write, iclass 13, count 2 2006.201.03:41:40.09#ibcon#*before return 0, iclass 13, count 2 2006.201.03:41:40.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:40.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:41:40.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.03:41:40.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:41:40.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:40.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:40.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:40.21#ibcon#enter wrdev, iclass 13, count 0 2006.201.03:41:40.21#ibcon#first serial, iclass 13, count 0 2006.201.03:41:40.21#ibcon#enter sib2, iclass 13, count 0 2006.201.03:41:40.21#ibcon#flushed, iclass 13, count 0 2006.201.03:41:40.21#ibcon#about to write, iclass 13, count 0 2006.201.03:41:40.21#ibcon#wrote, iclass 13, count 0 2006.201.03:41:40.21#ibcon#about to read 3, iclass 13, count 0 2006.201.03:41:40.23#ibcon#read 3, iclass 13, count 0 2006.201.03:41:40.23#ibcon#about to read 4, iclass 13, count 0 2006.201.03:41:40.23#ibcon#read 4, iclass 13, count 0 2006.201.03:41:40.23#ibcon#about to read 5, iclass 13, count 0 2006.201.03:41:40.23#ibcon#read 5, iclass 13, count 0 2006.201.03:41:40.23#ibcon#about to read 6, iclass 13, count 0 2006.201.03:41:40.23#ibcon#read 6, iclass 13, count 0 2006.201.03:41:40.23#ibcon#end of sib2, iclass 13, count 0 2006.201.03:41:40.23#ibcon#*mode == 0, iclass 13, count 0 2006.201.03:41:40.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.03:41:40.23#ibcon#[27=USB\r\n] 2006.201.03:41:40.23#ibcon#*before write, iclass 13, count 0 2006.201.03:41:40.23#ibcon#enter sib2, iclass 13, count 0 2006.201.03:41:40.23#ibcon#flushed, iclass 13, count 0 2006.201.03:41:40.23#ibcon#about to write, iclass 13, count 0 2006.201.03:41:40.23#ibcon#wrote, iclass 13, count 0 2006.201.03:41:40.23#ibcon#about to read 3, iclass 13, count 0 2006.201.03:41:40.26#ibcon#read 3, iclass 13, count 0 2006.201.03:41:40.26#ibcon#about to read 4, iclass 13, count 0 2006.201.03:41:40.26#ibcon#read 4, iclass 13, count 0 2006.201.03:41:40.26#ibcon#about to read 5, iclass 13, count 0 2006.201.03:41:40.26#ibcon#read 5, iclass 13, count 0 2006.201.03:41:40.26#ibcon#about to read 6, iclass 13, count 0 2006.201.03:41:40.26#ibcon#read 6, iclass 13, count 0 2006.201.03:41:40.26#ibcon#end of sib2, iclass 13, count 0 2006.201.03:41:40.26#ibcon#*after write, iclass 13, count 0 2006.201.03:41:40.26#ibcon#*before return 0, iclass 13, count 0 2006.201.03:41:40.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:40.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:41:40.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.03:41:40.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.03:41:40.26$vck44/vabw=wide 2006.201.03:41:40.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.03:41:40.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.03:41:40.26#ibcon#ireg 8 cls_cnt 0 2006.201.03:41:40.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:40.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:40.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:40.26#ibcon#enter wrdev, iclass 15, count 0 2006.201.03:41:40.26#ibcon#first serial, iclass 15, count 0 2006.201.03:41:40.26#ibcon#enter sib2, iclass 15, count 0 2006.201.03:41:40.26#ibcon#flushed, iclass 15, count 0 2006.201.03:41:40.26#ibcon#about to write, iclass 15, count 0 2006.201.03:41:40.26#ibcon#wrote, iclass 15, count 0 2006.201.03:41:40.26#ibcon#about to read 3, iclass 15, count 0 2006.201.03:41:40.28#ibcon#read 3, iclass 15, count 0 2006.201.03:41:40.28#ibcon#about to read 4, iclass 15, count 0 2006.201.03:41:40.28#ibcon#read 4, iclass 15, count 0 2006.201.03:41:40.28#ibcon#about to read 5, iclass 15, count 0 2006.201.03:41:40.28#ibcon#read 5, iclass 15, count 0 2006.201.03:41:40.28#ibcon#about to read 6, iclass 15, count 0 2006.201.03:41:40.28#ibcon#read 6, iclass 15, count 0 2006.201.03:41:40.28#ibcon#end of sib2, iclass 15, count 0 2006.201.03:41:40.28#ibcon#*mode == 0, iclass 15, count 0 2006.201.03:41:40.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.03:41:40.28#ibcon#[25=BW32\r\n] 2006.201.03:41:40.28#ibcon#*before write, iclass 15, count 0 2006.201.03:41:40.28#ibcon#enter sib2, iclass 15, count 0 2006.201.03:41:40.28#ibcon#flushed, iclass 15, count 0 2006.201.03:41:40.28#ibcon#about to write, iclass 15, count 0 2006.201.03:41:40.28#ibcon#wrote, iclass 15, count 0 2006.201.03:41:40.28#ibcon#about to read 3, iclass 15, count 0 2006.201.03:41:40.31#ibcon#read 3, iclass 15, count 0 2006.201.03:41:40.31#ibcon#about to read 4, iclass 15, count 0 2006.201.03:41:40.31#ibcon#read 4, iclass 15, count 0 2006.201.03:41:40.31#ibcon#about to read 5, iclass 15, count 0 2006.201.03:41:40.31#ibcon#read 5, iclass 15, count 0 2006.201.03:41:40.31#ibcon#about to read 6, iclass 15, count 0 2006.201.03:41:40.31#ibcon#read 6, iclass 15, count 0 2006.201.03:41:40.31#ibcon#end of sib2, iclass 15, count 0 2006.201.03:41:40.31#ibcon#*after write, iclass 15, count 0 2006.201.03:41:40.31#ibcon#*before return 0, iclass 15, count 0 2006.201.03:41:40.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:40.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:41:40.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.03:41:40.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.03:41:40.31$vck44/vbbw=wide 2006.201.03:41:40.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.03:41:40.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.03:41:40.31#ibcon#ireg 8 cls_cnt 0 2006.201.03:41:40.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:41:40.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:41:40.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:41:40.38#ibcon#enter wrdev, iclass 17, count 0 2006.201.03:41:40.38#ibcon#first serial, iclass 17, count 0 2006.201.03:41:40.38#ibcon#enter sib2, iclass 17, count 0 2006.201.03:41:40.38#ibcon#flushed, iclass 17, count 0 2006.201.03:41:40.38#ibcon#about to write, iclass 17, count 0 2006.201.03:41:40.38#ibcon#wrote, iclass 17, count 0 2006.201.03:41:40.38#ibcon#about to read 3, iclass 17, count 0 2006.201.03:41:40.40#ibcon#read 3, iclass 17, count 0 2006.201.03:41:40.40#ibcon#about to read 4, iclass 17, count 0 2006.201.03:41:40.40#ibcon#read 4, iclass 17, count 0 2006.201.03:41:40.40#ibcon#about to read 5, iclass 17, count 0 2006.201.03:41:40.40#ibcon#read 5, iclass 17, count 0 2006.201.03:41:40.40#ibcon#about to read 6, iclass 17, count 0 2006.201.03:41:40.40#ibcon#read 6, iclass 17, count 0 2006.201.03:41:40.40#ibcon#end of sib2, iclass 17, count 0 2006.201.03:41:40.40#ibcon#*mode == 0, iclass 17, count 0 2006.201.03:41:40.40#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.03:41:40.40#ibcon#[27=BW32\r\n] 2006.201.03:41:40.40#ibcon#*before write, iclass 17, count 0 2006.201.03:41:40.40#ibcon#enter sib2, iclass 17, count 0 2006.201.03:41:40.40#ibcon#flushed, iclass 17, count 0 2006.201.03:41:40.40#ibcon#about to write, iclass 17, count 0 2006.201.03:41:40.40#ibcon#wrote, iclass 17, count 0 2006.201.03:41:40.40#ibcon#about to read 3, iclass 17, count 0 2006.201.03:41:40.43#ibcon#read 3, iclass 17, count 0 2006.201.03:41:40.43#ibcon#about to read 4, iclass 17, count 0 2006.201.03:41:40.43#ibcon#read 4, iclass 17, count 0 2006.201.03:41:40.43#ibcon#about to read 5, iclass 17, count 0 2006.201.03:41:40.43#ibcon#read 5, iclass 17, count 0 2006.201.03:41:40.43#ibcon#about to read 6, iclass 17, count 0 2006.201.03:41:40.43#ibcon#read 6, iclass 17, count 0 2006.201.03:41:40.43#ibcon#end of sib2, iclass 17, count 0 2006.201.03:41:40.43#ibcon#*after write, iclass 17, count 0 2006.201.03:41:40.43#ibcon#*before return 0, iclass 17, count 0 2006.201.03:41:40.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:41:40.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:41:40.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.03:41:40.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.03:41:40.43$setupk4/ifdk4 2006.201.03:41:40.43$ifdk4/lo= 2006.201.03:41:40.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:41:40.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:41:40.43$ifdk4/patch= 2006.201.03:41:40.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:41:40.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:41:40.43$setupk4/!*+20s 2006.201.03:41:43.51#abcon#<5=/03 1.8 4.1 23.03 921004.5\r\n> 2006.201.03:41:43.53#abcon#{5=INTERFACE CLEAR} 2006.201.03:41:43.59#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:41:53.68#abcon#<5=/03 1.8 4.1 23.03 921004.5\r\n> 2006.201.03:41:53.70#abcon#{5=INTERFACE CLEAR} 2006.201.03:41:53.76#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:41:54.91$setupk4/"tpicd 2006.201.03:41:54.91$setupk4/echo=off 2006.201.03:41:54.91$setupk4/xlog=off 2006.201.03:41:54.91:!2006.201.03:43:54 2006.201.03:42:16.14#trakl#Source acquired 2006.201.03:42:16.14#flagr#flagr/antenna,acquired 2006.201.03:43:54.00:preob 2006.201.03:43:54.14/onsource/TRACKING 2006.201.03:43:54.14:!2006.201.03:44:04 2006.201.03:44:04.00:"tape 2006.201.03:44:04.00:"st=record 2006.201.03:44:04.00:data_valid=on 2006.201.03:44:04.00:midob 2006.201.03:44:04.14/onsource/TRACKING 2006.201.03:44:04.14/wx/23.02,1004.5,92 2006.201.03:44:04.20/cable/+6.4689E-03 2006.201.03:44:05.29/va/01,08,usb,yes,28,30 2006.201.03:44:05.29/va/02,07,usb,yes,30,31 2006.201.03:44:05.29/va/03,08,usb,yes,27,28 2006.201.03:44:05.29/va/04,07,usb,yes,31,33 2006.201.03:44:05.29/va/05,04,usb,yes,27,28 2006.201.03:44:05.29/va/06,05,usb,yes,28,27 2006.201.03:44:05.29/va/07,05,usb,yes,27,28 2006.201.03:44:05.29/va/08,04,usb,yes,26,32 2006.201.03:44:05.52/valo/01,524.99,yes,locked 2006.201.03:44:05.52/valo/02,534.99,yes,locked 2006.201.03:44:05.52/valo/03,564.99,yes,locked 2006.201.03:44:05.52/valo/04,624.99,yes,locked 2006.201.03:44:05.52/valo/05,734.99,yes,locked 2006.201.03:44:05.52/valo/06,814.99,yes,locked 2006.201.03:44:05.52/valo/07,864.99,yes,locked 2006.201.03:44:05.52/valo/08,884.99,yes,locked 2006.201.03:44:06.61/vb/01,04,usb,yes,28,26 2006.201.03:44:06.61/vb/02,05,usb,yes,27,27 2006.201.03:44:06.61/vb/03,04,usb,yes,28,31 2006.201.03:44:06.61/vb/04,05,usb,yes,28,27 2006.201.03:44:06.61/vb/05,04,usb,yes,25,27 2006.201.03:44:06.61/vb/06,04,usb,yes,29,25 2006.201.03:44:06.61/vb/07,04,usb,yes,29,29 2006.201.03:44:06.61/vb/08,04,usb,yes,26,30 2006.201.03:44:06.84/vblo/01,629.99,yes,locked 2006.201.03:44:06.84/vblo/02,634.99,yes,locked 2006.201.03:44:06.84/vblo/03,649.99,yes,locked 2006.201.03:44:06.84/vblo/04,679.99,yes,locked 2006.201.03:44:06.84/vblo/05,709.99,yes,locked 2006.201.03:44:06.84/vblo/06,719.99,yes,locked 2006.201.03:44:06.84/vblo/07,734.99,yes,locked 2006.201.03:44:06.84/vblo/08,744.99,yes,locked 2006.201.03:44:06.99/vabw/8 2006.201.03:44:07.14/vbbw/8 2006.201.03:44:07.25/xfe/off,on,16.0 2006.201.03:44:07.63/ifatt/23,28,28,28 2006.201.03:44:08.04/fmout-gps/S +4.54E-07 2006.201.03:44:08.11:!2006.201.03:44:54 2006.201.03:44:54.00:data_valid=off 2006.201.03:44:54.00:"et 2006.201.03:44:54.00:!+3s 2006.201.03:44:57.02:"tape 2006.201.03:44:57.02:postob 2006.201.03:44:57.09/cable/+6.4661E-03 2006.201.03:44:57.09/wx/23.01,1004.5,92 2006.201.03:44:57.16/fmout-gps/S +4.53E-07 2006.201.03:44:57.16:scan_name=201-0347,jd0607,90 2006.201.03:44:57.16:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.201.03:44:58.14#flagr#flagr/antenna,new-source 2006.201.03:44:58.14:checkk5 2006.201.03:44:58.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:44:58.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:44:59.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:44:59.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:45:00.01/chk_obsdata//k5ts1/T2010344??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.03:45:00.38/chk_obsdata//k5ts2/T2010344??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.03:45:00.75/chk_obsdata//k5ts3/T2010344??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.03:45:01.14/chk_obsdata//k5ts4/T2010344??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.03:45:01.83/k5log//k5ts1_log_newline 2006.201.03:45:02.52/k5log//k5ts2_log_newline 2006.201.03:45:03.22/k5log//k5ts3_log_newline 2006.201.03:45:03.91/k5log//k5ts4_log_newline 2006.201.03:45:03.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:45:03.94:setupk4=1 2006.201.03:45:03.94$setupk4/echo=on 2006.201.03:45:03.94$setupk4/pcalon 2006.201.03:45:03.94$pcalon/"no phase cal control is implemented here 2006.201.03:45:03.94$setupk4/"tpicd=stop 2006.201.03:45:03.94$setupk4/"rec=synch_on 2006.201.03:45:03.94$setupk4/"rec_mode=128 2006.201.03:45:03.94$setupk4/!* 2006.201.03:45:03.94$setupk4/recpk4 2006.201.03:45:03.94$recpk4/recpatch= 2006.201.03:45:03.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:45:03.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:45:03.94$setupk4/vck44 2006.201.03:45:03.94$vck44/valo=1,524.99 2006.201.03:45:03.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.03:45:03.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.03:45:03.94#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:03.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:03.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:03.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:03.94#ibcon#enter wrdev, iclass 25, count 0 2006.201.03:45:03.94#ibcon#first serial, iclass 25, count 0 2006.201.03:45:03.94#ibcon#enter sib2, iclass 25, count 0 2006.201.03:45:03.94#ibcon#flushed, iclass 25, count 0 2006.201.03:45:03.94#ibcon#about to write, iclass 25, count 0 2006.201.03:45:03.94#ibcon#wrote, iclass 25, count 0 2006.201.03:45:03.94#ibcon#about to read 3, iclass 25, count 0 2006.201.03:45:03.98#ibcon#read 3, iclass 25, count 0 2006.201.03:45:03.98#ibcon#about to read 4, iclass 25, count 0 2006.201.03:45:03.98#ibcon#read 4, iclass 25, count 0 2006.201.03:45:03.98#ibcon#about to read 5, iclass 25, count 0 2006.201.03:45:03.98#ibcon#read 5, iclass 25, count 0 2006.201.03:45:03.98#ibcon#about to read 6, iclass 25, count 0 2006.201.03:45:03.98#ibcon#read 6, iclass 25, count 0 2006.201.03:45:03.98#ibcon#end of sib2, iclass 25, count 0 2006.201.03:45:03.98#ibcon#*mode == 0, iclass 25, count 0 2006.201.03:45:03.98#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.03:45:03.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:45:03.98#ibcon#*before write, iclass 25, count 0 2006.201.03:45:03.98#ibcon#enter sib2, iclass 25, count 0 2006.201.03:45:03.98#ibcon#flushed, iclass 25, count 0 2006.201.03:45:03.98#ibcon#about to write, iclass 25, count 0 2006.201.03:45:03.98#ibcon#wrote, iclass 25, count 0 2006.201.03:45:03.98#ibcon#about to read 3, iclass 25, count 0 2006.201.03:45:04.03#ibcon#read 3, iclass 25, count 0 2006.201.03:45:04.03#ibcon#about to read 4, iclass 25, count 0 2006.201.03:45:04.03#ibcon#read 4, iclass 25, count 0 2006.201.03:45:04.03#ibcon#about to read 5, iclass 25, count 0 2006.201.03:45:04.03#ibcon#read 5, iclass 25, count 0 2006.201.03:45:04.03#ibcon#about to read 6, iclass 25, count 0 2006.201.03:45:04.03#ibcon#read 6, iclass 25, count 0 2006.201.03:45:04.03#ibcon#end of sib2, iclass 25, count 0 2006.201.03:45:04.03#ibcon#*after write, iclass 25, count 0 2006.201.03:45:04.03#ibcon#*before return 0, iclass 25, count 0 2006.201.03:45:04.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:04.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:04.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.03:45:04.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.03:45:04.03$vck44/va=1,8 2006.201.03:45:04.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.03:45:04.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.03:45:04.03#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:04.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:04.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:04.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:04.03#ibcon#enter wrdev, iclass 27, count 2 2006.201.03:45:04.03#ibcon#first serial, iclass 27, count 2 2006.201.03:45:04.03#ibcon#enter sib2, iclass 27, count 2 2006.201.03:45:04.03#ibcon#flushed, iclass 27, count 2 2006.201.03:45:04.03#ibcon#about to write, iclass 27, count 2 2006.201.03:45:04.03#ibcon#wrote, iclass 27, count 2 2006.201.03:45:04.03#ibcon#about to read 3, iclass 27, count 2 2006.201.03:45:04.05#ibcon#read 3, iclass 27, count 2 2006.201.03:45:04.05#ibcon#about to read 4, iclass 27, count 2 2006.201.03:45:04.05#ibcon#read 4, iclass 27, count 2 2006.201.03:45:04.05#ibcon#about to read 5, iclass 27, count 2 2006.201.03:45:04.05#ibcon#read 5, iclass 27, count 2 2006.201.03:45:04.05#ibcon#about to read 6, iclass 27, count 2 2006.201.03:45:04.05#ibcon#read 6, iclass 27, count 2 2006.201.03:45:04.05#ibcon#end of sib2, iclass 27, count 2 2006.201.03:45:04.05#ibcon#*mode == 0, iclass 27, count 2 2006.201.03:45:04.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.03:45:04.05#ibcon#[25=AT01-08\r\n] 2006.201.03:45:04.05#ibcon#*before write, iclass 27, count 2 2006.201.03:45:04.05#ibcon#enter sib2, iclass 27, count 2 2006.201.03:45:04.05#ibcon#flushed, iclass 27, count 2 2006.201.03:45:04.05#ibcon#about to write, iclass 27, count 2 2006.201.03:45:04.05#ibcon#wrote, iclass 27, count 2 2006.201.03:45:04.05#ibcon#about to read 3, iclass 27, count 2 2006.201.03:45:04.08#ibcon#read 3, iclass 27, count 2 2006.201.03:45:04.08#ibcon#about to read 4, iclass 27, count 2 2006.201.03:45:04.08#ibcon#read 4, iclass 27, count 2 2006.201.03:45:04.08#ibcon#about to read 5, iclass 27, count 2 2006.201.03:45:04.08#ibcon#read 5, iclass 27, count 2 2006.201.03:45:04.08#ibcon#about to read 6, iclass 27, count 2 2006.201.03:45:04.08#ibcon#read 6, iclass 27, count 2 2006.201.03:45:04.08#ibcon#end of sib2, iclass 27, count 2 2006.201.03:45:04.08#ibcon#*after write, iclass 27, count 2 2006.201.03:45:04.08#ibcon#*before return 0, iclass 27, count 2 2006.201.03:45:04.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:04.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:04.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.03:45:04.08#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:04.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:04.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:04.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:04.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.03:45:04.20#ibcon#first serial, iclass 27, count 0 2006.201.03:45:04.20#ibcon#enter sib2, iclass 27, count 0 2006.201.03:45:04.20#ibcon#flushed, iclass 27, count 0 2006.201.03:45:04.20#ibcon#about to write, iclass 27, count 0 2006.201.03:45:04.20#ibcon#wrote, iclass 27, count 0 2006.201.03:45:04.20#ibcon#about to read 3, iclass 27, count 0 2006.201.03:45:04.22#ibcon#read 3, iclass 27, count 0 2006.201.03:45:04.22#ibcon#about to read 4, iclass 27, count 0 2006.201.03:45:04.22#ibcon#read 4, iclass 27, count 0 2006.201.03:45:04.22#ibcon#about to read 5, iclass 27, count 0 2006.201.03:45:04.22#ibcon#read 5, iclass 27, count 0 2006.201.03:45:04.22#ibcon#about to read 6, iclass 27, count 0 2006.201.03:45:04.22#ibcon#read 6, iclass 27, count 0 2006.201.03:45:04.22#ibcon#end of sib2, iclass 27, count 0 2006.201.03:45:04.22#ibcon#*mode == 0, iclass 27, count 0 2006.201.03:45:04.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.03:45:04.22#ibcon#[25=USB\r\n] 2006.201.03:45:04.22#ibcon#*before write, iclass 27, count 0 2006.201.03:45:04.22#ibcon#enter sib2, iclass 27, count 0 2006.201.03:45:04.22#ibcon#flushed, iclass 27, count 0 2006.201.03:45:04.22#ibcon#about to write, iclass 27, count 0 2006.201.03:45:04.22#ibcon#wrote, iclass 27, count 0 2006.201.03:45:04.22#ibcon#about to read 3, iclass 27, count 0 2006.201.03:45:04.25#ibcon#read 3, iclass 27, count 0 2006.201.03:45:04.25#ibcon#about to read 4, iclass 27, count 0 2006.201.03:45:04.25#ibcon#read 4, iclass 27, count 0 2006.201.03:45:04.25#ibcon#about to read 5, iclass 27, count 0 2006.201.03:45:04.25#ibcon#read 5, iclass 27, count 0 2006.201.03:45:04.25#ibcon#about to read 6, iclass 27, count 0 2006.201.03:45:04.25#ibcon#read 6, iclass 27, count 0 2006.201.03:45:04.25#ibcon#end of sib2, iclass 27, count 0 2006.201.03:45:04.25#ibcon#*after write, iclass 27, count 0 2006.201.03:45:04.25#ibcon#*before return 0, iclass 27, count 0 2006.201.03:45:04.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:04.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:04.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.03:45:04.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.03:45:04.25$vck44/valo=2,534.99 2006.201.03:45:04.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.03:45:04.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.03:45:04.25#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:04.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:04.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:04.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:04.25#ibcon#enter wrdev, iclass 29, count 0 2006.201.03:45:04.25#ibcon#first serial, iclass 29, count 0 2006.201.03:45:04.25#ibcon#enter sib2, iclass 29, count 0 2006.201.03:45:04.25#ibcon#flushed, iclass 29, count 0 2006.201.03:45:04.25#ibcon#about to write, iclass 29, count 0 2006.201.03:45:04.25#ibcon#wrote, iclass 29, count 0 2006.201.03:45:04.25#ibcon#about to read 3, iclass 29, count 0 2006.201.03:45:04.27#ibcon#read 3, iclass 29, count 0 2006.201.03:45:04.27#ibcon#about to read 4, iclass 29, count 0 2006.201.03:45:04.27#ibcon#read 4, iclass 29, count 0 2006.201.03:45:04.27#ibcon#about to read 5, iclass 29, count 0 2006.201.03:45:04.27#ibcon#read 5, iclass 29, count 0 2006.201.03:45:04.27#ibcon#about to read 6, iclass 29, count 0 2006.201.03:45:04.27#ibcon#read 6, iclass 29, count 0 2006.201.03:45:04.27#ibcon#end of sib2, iclass 29, count 0 2006.201.03:45:04.27#ibcon#*mode == 0, iclass 29, count 0 2006.201.03:45:04.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.03:45:04.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:45:04.27#ibcon#*before write, iclass 29, count 0 2006.201.03:45:04.27#ibcon#enter sib2, iclass 29, count 0 2006.201.03:45:04.27#ibcon#flushed, iclass 29, count 0 2006.201.03:45:04.27#ibcon#about to write, iclass 29, count 0 2006.201.03:45:04.27#ibcon#wrote, iclass 29, count 0 2006.201.03:45:04.27#ibcon#about to read 3, iclass 29, count 0 2006.201.03:45:04.32#ibcon#read 3, iclass 29, count 0 2006.201.03:45:04.32#ibcon#about to read 4, iclass 29, count 0 2006.201.03:45:04.32#ibcon#read 4, iclass 29, count 0 2006.201.03:45:04.32#ibcon#about to read 5, iclass 29, count 0 2006.201.03:45:04.32#ibcon#read 5, iclass 29, count 0 2006.201.03:45:04.32#ibcon#about to read 6, iclass 29, count 0 2006.201.03:45:04.32#ibcon#read 6, iclass 29, count 0 2006.201.03:45:04.32#ibcon#end of sib2, iclass 29, count 0 2006.201.03:45:04.32#ibcon#*after write, iclass 29, count 0 2006.201.03:45:04.32#ibcon#*before return 0, iclass 29, count 0 2006.201.03:45:04.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:04.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:04.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.03:45:04.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.03:45:04.32$vck44/va=2,7 2006.201.03:45:04.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.03:45:04.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.03:45:04.32#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:04.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:04.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:04.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:04.37#ibcon#enter wrdev, iclass 31, count 2 2006.201.03:45:04.37#ibcon#first serial, iclass 31, count 2 2006.201.03:45:04.37#ibcon#enter sib2, iclass 31, count 2 2006.201.03:45:04.37#ibcon#flushed, iclass 31, count 2 2006.201.03:45:04.37#ibcon#about to write, iclass 31, count 2 2006.201.03:45:04.37#ibcon#wrote, iclass 31, count 2 2006.201.03:45:04.37#ibcon#about to read 3, iclass 31, count 2 2006.201.03:45:04.39#ibcon#read 3, iclass 31, count 2 2006.201.03:45:04.39#ibcon#about to read 4, iclass 31, count 2 2006.201.03:45:04.39#ibcon#read 4, iclass 31, count 2 2006.201.03:45:04.39#ibcon#about to read 5, iclass 31, count 2 2006.201.03:45:04.39#ibcon#read 5, iclass 31, count 2 2006.201.03:45:04.39#ibcon#about to read 6, iclass 31, count 2 2006.201.03:45:04.39#ibcon#read 6, iclass 31, count 2 2006.201.03:45:04.39#ibcon#end of sib2, iclass 31, count 2 2006.201.03:45:04.39#ibcon#*mode == 0, iclass 31, count 2 2006.201.03:45:04.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.03:45:04.39#ibcon#[25=AT02-07\r\n] 2006.201.03:45:04.39#ibcon#*before write, iclass 31, count 2 2006.201.03:45:04.39#ibcon#enter sib2, iclass 31, count 2 2006.201.03:45:04.39#ibcon#flushed, iclass 31, count 2 2006.201.03:45:04.39#ibcon#about to write, iclass 31, count 2 2006.201.03:45:04.39#ibcon#wrote, iclass 31, count 2 2006.201.03:45:04.39#ibcon#about to read 3, iclass 31, count 2 2006.201.03:45:04.42#ibcon#read 3, iclass 31, count 2 2006.201.03:45:04.42#ibcon#about to read 4, iclass 31, count 2 2006.201.03:45:04.42#ibcon#read 4, iclass 31, count 2 2006.201.03:45:04.42#ibcon#about to read 5, iclass 31, count 2 2006.201.03:45:04.42#ibcon#read 5, iclass 31, count 2 2006.201.03:45:04.42#ibcon#about to read 6, iclass 31, count 2 2006.201.03:45:04.42#ibcon#read 6, iclass 31, count 2 2006.201.03:45:04.42#ibcon#end of sib2, iclass 31, count 2 2006.201.03:45:04.42#ibcon#*after write, iclass 31, count 2 2006.201.03:45:04.42#ibcon#*before return 0, iclass 31, count 2 2006.201.03:45:04.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:04.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:04.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.03:45:04.42#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:04.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:04.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:04.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:04.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.03:45:04.54#ibcon#first serial, iclass 31, count 0 2006.201.03:45:04.54#ibcon#enter sib2, iclass 31, count 0 2006.201.03:45:04.54#ibcon#flushed, iclass 31, count 0 2006.201.03:45:04.54#ibcon#about to write, iclass 31, count 0 2006.201.03:45:04.54#ibcon#wrote, iclass 31, count 0 2006.201.03:45:04.54#ibcon#about to read 3, iclass 31, count 0 2006.201.03:45:04.56#ibcon#read 3, iclass 31, count 0 2006.201.03:45:04.56#ibcon#about to read 4, iclass 31, count 0 2006.201.03:45:04.56#ibcon#read 4, iclass 31, count 0 2006.201.03:45:04.56#ibcon#about to read 5, iclass 31, count 0 2006.201.03:45:04.56#ibcon#read 5, iclass 31, count 0 2006.201.03:45:04.56#ibcon#about to read 6, iclass 31, count 0 2006.201.03:45:04.56#ibcon#read 6, iclass 31, count 0 2006.201.03:45:04.56#ibcon#end of sib2, iclass 31, count 0 2006.201.03:45:04.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.03:45:04.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.03:45:04.56#ibcon#[25=USB\r\n] 2006.201.03:45:04.56#ibcon#*before write, iclass 31, count 0 2006.201.03:45:04.56#ibcon#enter sib2, iclass 31, count 0 2006.201.03:45:04.56#ibcon#flushed, iclass 31, count 0 2006.201.03:45:04.56#ibcon#about to write, iclass 31, count 0 2006.201.03:45:04.56#ibcon#wrote, iclass 31, count 0 2006.201.03:45:04.56#ibcon#about to read 3, iclass 31, count 0 2006.201.03:45:04.59#ibcon#read 3, iclass 31, count 0 2006.201.03:45:04.59#ibcon#about to read 4, iclass 31, count 0 2006.201.03:45:04.59#ibcon#read 4, iclass 31, count 0 2006.201.03:45:04.59#ibcon#about to read 5, iclass 31, count 0 2006.201.03:45:04.59#ibcon#read 5, iclass 31, count 0 2006.201.03:45:04.59#ibcon#about to read 6, iclass 31, count 0 2006.201.03:45:04.59#ibcon#read 6, iclass 31, count 0 2006.201.03:45:04.59#ibcon#end of sib2, iclass 31, count 0 2006.201.03:45:04.59#ibcon#*after write, iclass 31, count 0 2006.201.03:45:04.59#ibcon#*before return 0, iclass 31, count 0 2006.201.03:45:04.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:04.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:04.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.03:45:04.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.03:45:04.59$vck44/valo=3,564.99 2006.201.03:45:04.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.03:45:04.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.03:45:04.59#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:04.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:04.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:04.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:04.59#ibcon#enter wrdev, iclass 33, count 0 2006.201.03:45:04.59#ibcon#first serial, iclass 33, count 0 2006.201.03:45:04.59#ibcon#enter sib2, iclass 33, count 0 2006.201.03:45:04.59#ibcon#flushed, iclass 33, count 0 2006.201.03:45:04.59#ibcon#about to write, iclass 33, count 0 2006.201.03:45:04.59#ibcon#wrote, iclass 33, count 0 2006.201.03:45:04.59#ibcon#about to read 3, iclass 33, count 0 2006.201.03:45:04.61#ibcon#read 3, iclass 33, count 0 2006.201.03:45:04.61#ibcon#about to read 4, iclass 33, count 0 2006.201.03:45:04.61#ibcon#read 4, iclass 33, count 0 2006.201.03:45:04.61#ibcon#about to read 5, iclass 33, count 0 2006.201.03:45:04.61#ibcon#read 5, iclass 33, count 0 2006.201.03:45:04.61#ibcon#about to read 6, iclass 33, count 0 2006.201.03:45:04.61#ibcon#read 6, iclass 33, count 0 2006.201.03:45:04.61#ibcon#end of sib2, iclass 33, count 0 2006.201.03:45:04.61#ibcon#*mode == 0, iclass 33, count 0 2006.201.03:45:04.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.03:45:04.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:45:04.61#ibcon#*before write, iclass 33, count 0 2006.201.03:45:04.61#ibcon#enter sib2, iclass 33, count 0 2006.201.03:45:04.61#ibcon#flushed, iclass 33, count 0 2006.201.03:45:04.61#ibcon#about to write, iclass 33, count 0 2006.201.03:45:04.61#ibcon#wrote, iclass 33, count 0 2006.201.03:45:04.61#ibcon#about to read 3, iclass 33, count 0 2006.201.03:45:04.66#ibcon#read 3, iclass 33, count 0 2006.201.03:45:04.66#ibcon#about to read 4, iclass 33, count 0 2006.201.03:45:04.66#ibcon#read 4, iclass 33, count 0 2006.201.03:45:04.66#ibcon#about to read 5, iclass 33, count 0 2006.201.03:45:04.66#ibcon#read 5, iclass 33, count 0 2006.201.03:45:04.66#ibcon#about to read 6, iclass 33, count 0 2006.201.03:45:04.66#ibcon#read 6, iclass 33, count 0 2006.201.03:45:04.66#ibcon#end of sib2, iclass 33, count 0 2006.201.03:45:04.66#ibcon#*after write, iclass 33, count 0 2006.201.03:45:04.66#ibcon#*before return 0, iclass 33, count 0 2006.201.03:45:04.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:04.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:04.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.03:45:04.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.03:45:04.66$vck44/va=3,8 2006.201.03:45:04.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.03:45:04.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.03:45:04.66#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:04.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:04.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:04.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:04.71#ibcon#enter wrdev, iclass 35, count 2 2006.201.03:45:04.71#ibcon#first serial, iclass 35, count 2 2006.201.03:45:04.71#ibcon#enter sib2, iclass 35, count 2 2006.201.03:45:04.71#ibcon#flushed, iclass 35, count 2 2006.201.03:45:04.71#ibcon#about to write, iclass 35, count 2 2006.201.03:45:04.71#ibcon#wrote, iclass 35, count 2 2006.201.03:45:04.71#ibcon#about to read 3, iclass 35, count 2 2006.201.03:45:04.73#ibcon#read 3, iclass 35, count 2 2006.201.03:45:04.73#ibcon#about to read 4, iclass 35, count 2 2006.201.03:45:04.73#ibcon#read 4, iclass 35, count 2 2006.201.03:45:04.73#ibcon#about to read 5, iclass 35, count 2 2006.201.03:45:04.73#ibcon#read 5, iclass 35, count 2 2006.201.03:45:04.73#ibcon#about to read 6, iclass 35, count 2 2006.201.03:45:04.73#ibcon#read 6, iclass 35, count 2 2006.201.03:45:04.73#ibcon#end of sib2, iclass 35, count 2 2006.201.03:45:04.73#ibcon#*mode == 0, iclass 35, count 2 2006.201.03:45:04.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.03:45:04.73#ibcon#[25=AT03-08\r\n] 2006.201.03:45:04.73#ibcon#*before write, iclass 35, count 2 2006.201.03:45:04.73#ibcon#enter sib2, iclass 35, count 2 2006.201.03:45:04.73#ibcon#flushed, iclass 35, count 2 2006.201.03:45:04.73#ibcon#about to write, iclass 35, count 2 2006.201.03:45:04.73#ibcon#wrote, iclass 35, count 2 2006.201.03:45:04.73#ibcon#about to read 3, iclass 35, count 2 2006.201.03:45:04.76#ibcon#read 3, iclass 35, count 2 2006.201.03:45:04.76#ibcon#about to read 4, iclass 35, count 2 2006.201.03:45:04.76#ibcon#read 4, iclass 35, count 2 2006.201.03:45:04.76#ibcon#about to read 5, iclass 35, count 2 2006.201.03:45:04.76#ibcon#read 5, iclass 35, count 2 2006.201.03:45:04.76#ibcon#about to read 6, iclass 35, count 2 2006.201.03:45:04.76#ibcon#read 6, iclass 35, count 2 2006.201.03:45:04.76#ibcon#end of sib2, iclass 35, count 2 2006.201.03:45:04.76#ibcon#*after write, iclass 35, count 2 2006.201.03:45:04.76#ibcon#*before return 0, iclass 35, count 2 2006.201.03:45:04.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:04.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:04.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.03:45:04.76#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:04.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:04.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:04.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:04.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.03:45:04.88#ibcon#first serial, iclass 35, count 0 2006.201.03:45:04.88#ibcon#enter sib2, iclass 35, count 0 2006.201.03:45:04.88#ibcon#flushed, iclass 35, count 0 2006.201.03:45:04.88#ibcon#about to write, iclass 35, count 0 2006.201.03:45:04.88#ibcon#wrote, iclass 35, count 0 2006.201.03:45:04.88#ibcon#about to read 3, iclass 35, count 0 2006.201.03:45:04.90#ibcon#read 3, iclass 35, count 0 2006.201.03:45:04.90#ibcon#about to read 4, iclass 35, count 0 2006.201.03:45:04.90#ibcon#read 4, iclass 35, count 0 2006.201.03:45:04.90#ibcon#about to read 5, iclass 35, count 0 2006.201.03:45:04.90#ibcon#read 5, iclass 35, count 0 2006.201.03:45:04.90#ibcon#about to read 6, iclass 35, count 0 2006.201.03:45:04.90#ibcon#read 6, iclass 35, count 0 2006.201.03:45:04.90#ibcon#end of sib2, iclass 35, count 0 2006.201.03:45:04.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.03:45:04.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.03:45:04.90#ibcon#[25=USB\r\n] 2006.201.03:45:04.90#ibcon#*before write, iclass 35, count 0 2006.201.03:45:04.90#ibcon#enter sib2, iclass 35, count 0 2006.201.03:45:04.90#ibcon#flushed, iclass 35, count 0 2006.201.03:45:04.90#ibcon#about to write, iclass 35, count 0 2006.201.03:45:04.90#ibcon#wrote, iclass 35, count 0 2006.201.03:45:04.90#ibcon#about to read 3, iclass 35, count 0 2006.201.03:45:04.93#ibcon#read 3, iclass 35, count 0 2006.201.03:45:04.93#ibcon#about to read 4, iclass 35, count 0 2006.201.03:45:04.93#ibcon#read 4, iclass 35, count 0 2006.201.03:45:04.93#ibcon#about to read 5, iclass 35, count 0 2006.201.03:45:04.93#ibcon#read 5, iclass 35, count 0 2006.201.03:45:04.93#ibcon#about to read 6, iclass 35, count 0 2006.201.03:45:04.93#ibcon#read 6, iclass 35, count 0 2006.201.03:45:04.93#ibcon#end of sib2, iclass 35, count 0 2006.201.03:45:04.93#ibcon#*after write, iclass 35, count 0 2006.201.03:45:04.93#ibcon#*before return 0, iclass 35, count 0 2006.201.03:45:04.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:04.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:04.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.03:45:04.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.03:45:04.93$vck44/valo=4,624.99 2006.201.03:45:04.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.03:45:04.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.03:45:04.93#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:04.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:04.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:04.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:04.93#ibcon#enter wrdev, iclass 37, count 0 2006.201.03:45:04.93#ibcon#first serial, iclass 37, count 0 2006.201.03:45:04.93#ibcon#enter sib2, iclass 37, count 0 2006.201.03:45:04.93#ibcon#flushed, iclass 37, count 0 2006.201.03:45:04.93#ibcon#about to write, iclass 37, count 0 2006.201.03:45:04.93#ibcon#wrote, iclass 37, count 0 2006.201.03:45:04.93#ibcon#about to read 3, iclass 37, count 0 2006.201.03:45:04.95#ibcon#read 3, iclass 37, count 0 2006.201.03:45:04.95#ibcon#about to read 4, iclass 37, count 0 2006.201.03:45:04.95#ibcon#read 4, iclass 37, count 0 2006.201.03:45:04.95#ibcon#about to read 5, iclass 37, count 0 2006.201.03:45:04.95#ibcon#read 5, iclass 37, count 0 2006.201.03:45:04.95#ibcon#about to read 6, iclass 37, count 0 2006.201.03:45:04.95#ibcon#read 6, iclass 37, count 0 2006.201.03:45:04.95#ibcon#end of sib2, iclass 37, count 0 2006.201.03:45:04.95#ibcon#*mode == 0, iclass 37, count 0 2006.201.03:45:04.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.03:45:04.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:45:04.95#ibcon#*before write, iclass 37, count 0 2006.201.03:45:04.95#ibcon#enter sib2, iclass 37, count 0 2006.201.03:45:04.95#ibcon#flushed, iclass 37, count 0 2006.201.03:45:04.95#ibcon#about to write, iclass 37, count 0 2006.201.03:45:04.95#ibcon#wrote, iclass 37, count 0 2006.201.03:45:04.95#ibcon#about to read 3, iclass 37, count 0 2006.201.03:45:04.99#ibcon#read 3, iclass 37, count 0 2006.201.03:45:04.99#ibcon#about to read 4, iclass 37, count 0 2006.201.03:45:04.99#ibcon#read 4, iclass 37, count 0 2006.201.03:45:04.99#ibcon#about to read 5, iclass 37, count 0 2006.201.03:45:04.99#ibcon#read 5, iclass 37, count 0 2006.201.03:45:04.99#ibcon#about to read 6, iclass 37, count 0 2006.201.03:45:04.99#ibcon#read 6, iclass 37, count 0 2006.201.03:45:04.99#ibcon#end of sib2, iclass 37, count 0 2006.201.03:45:04.99#ibcon#*after write, iclass 37, count 0 2006.201.03:45:04.99#ibcon#*before return 0, iclass 37, count 0 2006.201.03:45:04.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:04.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:04.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.03:45:04.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.03:45:04.99$vck44/va=4,7 2006.201.03:45:04.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.03:45:04.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.03:45:04.99#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:04.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:05.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:05.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:05.05#ibcon#enter wrdev, iclass 39, count 2 2006.201.03:45:05.05#ibcon#first serial, iclass 39, count 2 2006.201.03:45:05.05#ibcon#enter sib2, iclass 39, count 2 2006.201.03:45:05.05#ibcon#flushed, iclass 39, count 2 2006.201.03:45:05.05#ibcon#about to write, iclass 39, count 2 2006.201.03:45:05.05#ibcon#wrote, iclass 39, count 2 2006.201.03:45:05.05#ibcon#about to read 3, iclass 39, count 2 2006.201.03:45:05.07#ibcon#read 3, iclass 39, count 2 2006.201.03:45:05.07#ibcon#about to read 4, iclass 39, count 2 2006.201.03:45:05.07#ibcon#read 4, iclass 39, count 2 2006.201.03:45:05.07#ibcon#about to read 5, iclass 39, count 2 2006.201.03:45:05.07#ibcon#read 5, iclass 39, count 2 2006.201.03:45:05.07#ibcon#about to read 6, iclass 39, count 2 2006.201.03:45:05.07#ibcon#read 6, iclass 39, count 2 2006.201.03:45:05.07#ibcon#end of sib2, iclass 39, count 2 2006.201.03:45:05.07#ibcon#*mode == 0, iclass 39, count 2 2006.201.03:45:05.07#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.03:45:05.07#ibcon#[25=AT04-07\r\n] 2006.201.03:45:05.07#ibcon#*before write, iclass 39, count 2 2006.201.03:45:05.07#ibcon#enter sib2, iclass 39, count 2 2006.201.03:45:05.07#ibcon#flushed, iclass 39, count 2 2006.201.03:45:05.07#ibcon#about to write, iclass 39, count 2 2006.201.03:45:05.07#ibcon#wrote, iclass 39, count 2 2006.201.03:45:05.07#ibcon#about to read 3, iclass 39, count 2 2006.201.03:45:05.10#ibcon#read 3, iclass 39, count 2 2006.201.03:45:05.10#ibcon#about to read 4, iclass 39, count 2 2006.201.03:45:05.10#ibcon#read 4, iclass 39, count 2 2006.201.03:45:05.10#ibcon#about to read 5, iclass 39, count 2 2006.201.03:45:05.10#ibcon#read 5, iclass 39, count 2 2006.201.03:45:05.10#ibcon#about to read 6, iclass 39, count 2 2006.201.03:45:05.10#ibcon#read 6, iclass 39, count 2 2006.201.03:45:05.10#ibcon#end of sib2, iclass 39, count 2 2006.201.03:45:05.10#ibcon#*after write, iclass 39, count 2 2006.201.03:45:05.10#ibcon#*before return 0, iclass 39, count 2 2006.201.03:45:05.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:05.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:05.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.03:45:05.10#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:05.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:05.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:05.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:05.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:45:05.22#ibcon#first serial, iclass 39, count 0 2006.201.03:45:05.22#ibcon#enter sib2, iclass 39, count 0 2006.201.03:45:05.22#ibcon#flushed, iclass 39, count 0 2006.201.03:45:05.22#ibcon#about to write, iclass 39, count 0 2006.201.03:45:05.22#ibcon#wrote, iclass 39, count 0 2006.201.03:45:05.22#ibcon#about to read 3, iclass 39, count 0 2006.201.03:45:05.24#ibcon#read 3, iclass 39, count 0 2006.201.03:45:05.24#ibcon#about to read 4, iclass 39, count 0 2006.201.03:45:05.24#ibcon#read 4, iclass 39, count 0 2006.201.03:45:05.24#ibcon#about to read 5, iclass 39, count 0 2006.201.03:45:05.24#ibcon#read 5, iclass 39, count 0 2006.201.03:45:05.24#ibcon#about to read 6, iclass 39, count 0 2006.201.03:45:05.24#ibcon#read 6, iclass 39, count 0 2006.201.03:45:05.24#ibcon#end of sib2, iclass 39, count 0 2006.201.03:45:05.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:45:05.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:45:05.24#ibcon#[25=USB\r\n] 2006.201.03:45:05.24#ibcon#*before write, iclass 39, count 0 2006.201.03:45:05.24#ibcon#enter sib2, iclass 39, count 0 2006.201.03:45:05.24#ibcon#flushed, iclass 39, count 0 2006.201.03:45:05.24#ibcon#about to write, iclass 39, count 0 2006.201.03:45:05.24#ibcon#wrote, iclass 39, count 0 2006.201.03:45:05.24#ibcon#about to read 3, iclass 39, count 0 2006.201.03:45:05.27#ibcon#read 3, iclass 39, count 0 2006.201.03:45:05.27#ibcon#about to read 4, iclass 39, count 0 2006.201.03:45:05.27#ibcon#read 4, iclass 39, count 0 2006.201.03:45:05.27#ibcon#about to read 5, iclass 39, count 0 2006.201.03:45:05.27#ibcon#read 5, iclass 39, count 0 2006.201.03:45:05.27#ibcon#about to read 6, iclass 39, count 0 2006.201.03:45:05.27#ibcon#read 6, iclass 39, count 0 2006.201.03:45:05.27#ibcon#end of sib2, iclass 39, count 0 2006.201.03:45:05.27#ibcon#*after write, iclass 39, count 0 2006.201.03:45:05.27#ibcon#*before return 0, iclass 39, count 0 2006.201.03:45:05.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:05.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:05.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:45:05.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:45:05.27$vck44/valo=5,734.99 2006.201.03:45:05.27#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.03:45:05.27#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.03:45:05.27#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:05.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:05.27#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:05.27#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:05.27#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:45:05.27#ibcon#first serial, iclass 2, count 0 2006.201.03:45:05.27#ibcon#enter sib2, iclass 2, count 0 2006.201.03:45:05.27#ibcon#flushed, iclass 2, count 0 2006.201.03:45:05.27#ibcon#about to write, iclass 2, count 0 2006.201.03:45:05.27#ibcon#wrote, iclass 2, count 0 2006.201.03:45:05.27#ibcon#about to read 3, iclass 2, count 0 2006.201.03:45:05.29#ibcon#read 3, iclass 2, count 0 2006.201.03:45:05.29#ibcon#about to read 4, iclass 2, count 0 2006.201.03:45:05.29#ibcon#read 4, iclass 2, count 0 2006.201.03:45:05.29#ibcon#about to read 5, iclass 2, count 0 2006.201.03:45:05.29#ibcon#read 5, iclass 2, count 0 2006.201.03:45:05.29#ibcon#about to read 6, iclass 2, count 0 2006.201.03:45:05.29#ibcon#read 6, iclass 2, count 0 2006.201.03:45:05.29#ibcon#end of sib2, iclass 2, count 0 2006.201.03:45:05.29#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:45:05.29#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:45:05.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:45:05.29#ibcon#*before write, iclass 2, count 0 2006.201.03:45:05.29#ibcon#enter sib2, iclass 2, count 0 2006.201.03:45:05.29#ibcon#flushed, iclass 2, count 0 2006.201.03:45:05.29#ibcon#about to write, iclass 2, count 0 2006.201.03:45:05.29#ibcon#wrote, iclass 2, count 0 2006.201.03:45:05.29#ibcon#about to read 3, iclass 2, count 0 2006.201.03:45:05.33#ibcon#read 3, iclass 2, count 0 2006.201.03:45:05.33#ibcon#about to read 4, iclass 2, count 0 2006.201.03:45:05.33#ibcon#read 4, iclass 2, count 0 2006.201.03:45:05.33#ibcon#about to read 5, iclass 2, count 0 2006.201.03:45:05.33#ibcon#read 5, iclass 2, count 0 2006.201.03:45:05.33#ibcon#about to read 6, iclass 2, count 0 2006.201.03:45:05.33#ibcon#read 6, iclass 2, count 0 2006.201.03:45:05.33#ibcon#end of sib2, iclass 2, count 0 2006.201.03:45:05.33#ibcon#*after write, iclass 2, count 0 2006.201.03:45:05.33#ibcon#*before return 0, iclass 2, count 0 2006.201.03:45:05.33#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:05.33#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:05.33#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:45:05.33#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:45:05.33$vck44/va=5,4 2006.201.03:45:05.33#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.03:45:05.33#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.03:45:05.33#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:05.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:05.39#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:05.39#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:05.39#ibcon#enter wrdev, iclass 5, count 2 2006.201.03:45:05.39#ibcon#first serial, iclass 5, count 2 2006.201.03:45:05.39#ibcon#enter sib2, iclass 5, count 2 2006.201.03:45:05.39#ibcon#flushed, iclass 5, count 2 2006.201.03:45:05.39#ibcon#about to write, iclass 5, count 2 2006.201.03:45:05.39#ibcon#wrote, iclass 5, count 2 2006.201.03:45:05.39#ibcon#about to read 3, iclass 5, count 2 2006.201.03:45:05.41#ibcon#read 3, iclass 5, count 2 2006.201.03:45:05.41#ibcon#about to read 4, iclass 5, count 2 2006.201.03:45:05.41#ibcon#read 4, iclass 5, count 2 2006.201.03:45:05.41#ibcon#about to read 5, iclass 5, count 2 2006.201.03:45:05.41#ibcon#read 5, iclass 5, count 2 2006.201.03:45:05.41#ibcon#about to read 6, iclass 5, count 2 2006.201.03:45:05.41#ibcon#read 6, iclass 5, count 2 2006.201.03:45:05.41#ibcon#end of sib2, iclass 5, count 2 2006.201.03:45:05.41#ibcon#*mode == 0, iclass 5, count 2 2006.201.03:45:05.41#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.03:45:05.41#ibcon#[25=AT05-04\r\n] 2006.201.03:45:05.41#ibcon#*before write, iclass 5, count 2 2006.201.03:45:05.41#ibcon#enter sib2, iclass 5, count 2 2006.201.03:45:05.41#ibcon#flushed, iclass 5, count 2 2006.201.03:45:05.41#ibcon#about to write, iclass 5, count 2 2006.201.03:45:05.41#ibcon#wrote, iclass 5, count 2 2006.201.03:45:05.41#ibcon#about to read 3, iclass 5, count 2 2006.201.03:45:05.44#ibcon#read 3, iclass 5, count 2 2006.201.03:45:05.44#ibcon#about to read 4, iclass 5, count 2 2006.201.03:45:05.44#ibcon#read 4, iclass 5, count 2 2006.201.03:45:05.44#ibcon#about to read 5, iclass 5, count 2 2006.201.03:45:05.44#ibcon#read 5, iclass 5, count 2 2006.201.03:45:05.44#ibcon#about to read 6, iclass 5, count 2 2006.201.03:45:05.44#ibcon#read 6, iclass 5, count 2 2006.201.03:45:05.44#ibcon#end of sib2, iclass 5, count 2 2006.201.03:45:05.44#ibcon#*after write, iclass 5, count 2 2006.201.03:45:05.44#ibcon#*before return 0, iclass 5, count 2 2006.201.03:45:05.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:05.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:05.44#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.03:45:05.44#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:05.44#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:05.56#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:05.56#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:05.56#ibcon#enter wrdev, iclass 5, count 0 2006.201.03:45:05.56#ibcon#first serial, iclass 5, count 0 2006.201.03:45:05.56#ibcon#enter sib2, iclass 5, count 0 2006.201.03:45:05.56#ibcon#flushed, iclass 5, count 0 2006.201.03:45:05.56#ibcon#about to write, iclass 5, count 0 2006.201.03:45:05.56#ibcon#wrote, iclass 5, count 0 2006.201.03:45:05.56#ibcon#about to read 3, iclass 5, count 0 2006.201.03:45:05.58#ibcon#read 3, iclass 5, count 0 2006.201.03:45:05.58#ibcon#about to read 4, iclass 5, count 0 2006.201.03:45:05.58#ibcon#read 4, iclass 5, count 0 2006.201.03:45:05.58#ibcon#about to read 5, iclass 5, count 0 2006.201.03:45:05.58#ibcon#read 5, iclass 5, count 0 2006.201.03:45:05.58#ibcon#about to read 6, iclass 5, count 0 2006.201.03:45:05.58#ibcon#read 6, iclass 5, count 0 2006.201.03:45:05.58#ibcon#end of sib2, iclass 5, count 0 2006.201.03:45:05.58#ibcon#*mode == 0, iclass 5, count 0 2006.201.03:45:05.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.03:45:05.58#ibcon#[25=USB\r\n] 2006.201.03:45:05.58#ibcon#*before write, iclass 5, count 0 2006.201.03:45:05.58#ibcon#enter sib2, iclass 5, count 0 2006.201.03:45:05.58#ibcon#flushed, iclass 5, count 0 2006.201.03:45:05.58#ibcon#about to write, iclass 5, count 0 2006.201.03:45:05.58#ibcon#wrote, iclass 5, count 0 2006.201.03:45:05.58#ibcon#about to read 3, iclass 5, count 0 2006.201.03:45:05.61#ibcon#read 3, iclass 5, count 0 2006.201.03:45:05.61#ibcon#about to read 4, iclass 5, count 0 2006.201.03:45:05.61#ibcon#read 4, iclass 5, count 0 2006.201.03:45:05.61#ibcon#about to read 5, iclass 5, count 0 2006.201.03:45:05.61#ibcon#read 5, iclass 5, count 0 2006.201.03:45:05.61#ibcon#about to read 6, iclass 5, count 0 2006.201.03:45:05.61#ibcon#read 6, iclass 5, count 0 2006.201.03:45:05.61#ibcon#end of sib2, iclass 5, count 0 2006.201.03:45:05.61#ibcon#*after write, iclass 5, count 0 2006.201.03:45:05.61#ibcon#*before return 0, iclass 5, count 0 2006.201.03:45:05.61#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:05.61#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:05.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.03:45:05.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.03:45:05.61$vck44/valo=6,814.99 2006.201.03:45:05.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.03:45:05.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.03:45:05.61#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:05.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:05.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:05.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:05.61#ibcon#enter wrdev, iclass 7, count 0 2006.201.03:45:05.61#ibcon#first serial, iclass 7, count 0 2006.201.03:45:05.61#ibcon#enter sib2, iclass 7, count 0 2006.201.03:45:05.61#ibcon#flushed, iclass 7, count 0 2006.201.03:45:05.61#ibcon#about to write, iclass 7, count 0 2006.201.03:45:05.61#ibcon#wrote, iclass 7, count 0 2006.201.03:45:05.61#ibcon#about to read 3, iclass 7, count 0 2006.201.03:45:05.63#ibcon#read 3, iclass 7, count 0 2006.201.03:45:05.63#ibcon#about to read 4, iclass 7, count 0 2006.201.03:45:05.63#ibcon#read 4, iclass 7, count 0 2006.201.03:45:05.63#ibcon#about to read 5, iclass 7, count 0 2006.201.03:45:05.63#ibcon#read 5, iclass 7, count 0 2006.201.03:45:05.63#ibcon#about to read 6, iclass 7, count 0 2006.201.03:45:05.63#ibcon#read 6, iclass 7, count 0 2006.201.03:45:05.63#ibcon#end of sib2, iclass 7, count 0 2006.201.03:45:05.63#ibcon#*mode == 0, iclass 7, count 0 2006.201.03:45:05.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.03:45:05.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:45:05.63#ibcon#*before write, iclass 7, count 0 2006.201.03:45:05.63#ibcon#enter sib2, iclass 7, count 0 2006.201.03:45:05.63#ibcon#flushed, iclass 7, count 0 2006.201.03:45:05.63#ibcon#about to write, iclass 7, count 0 2006.201.03:45:05.63#ibcon#wrote, iclass 7, count 0 2006.201.03:45:05.63#ibcon#about to read 3, iclass 7, count 0 2006.201.03:45:05.68#ibcon#read 3, iclass 7, count 0 2006.201.03:45:05.68#ibcon#about to read 4, iclass 7, count 0 2006.201.03:45:05.68#ibcon#read 4, iclass 7, count 0 2006.201.03:45:05.68#ibcon#about to read 5, iclass 7, count 0 2006.201.03:45:05.68#ibcon#read 5, iclass 7, count 0 2006.201.03:45:05.68#ibcon#about to read 6, iclass 7, count 0 2006.201.03:45:05.68#ibcon#read 6, iclass 7, count 0 2006.201.03:45:05.68#ibcon#end of sib2, iclass 7, count 0 2006.201.03:45:05.68#ibcon#*after write, iclass 7, count 0 2006.201.03:45:05.68#ibcon#*before return 0, iclass 7, count 0 2006.201.03:45:05.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:05.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:05.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.03:45:05.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.03:45:05.68$vck44/va=6,5 2006.201.03:45:05.68#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.03:45:05.68#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.03:45:05.68#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:05.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:05.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:05.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:05.73#ibcon#enter wrdev, iclass 11, count 2 2006.201.03:45:05.73#ibcon#first serial, iclass 11, count 2 2006.201.03:45:05.73#ibcon#enter sib2, iclass 11, count 2 2006.201.03:45:05.73#ibcon#flushed, iclass 11, count 2 2006.201.03:45:05.73#ibcon#about to write, iclass 11, count 2 2006.201.03:45:05.73#ibcon#wrote, iclass 11, count 2 2006.201.03:45:05.73#ibcon#about to read 3, iclass 11, count 2 2006.201.03:45:05.75#ibcon#read 3, iclass 11, count 2 2006.201.03:45:05.75#ibcon#about to read 4, iclass 11, count 2 2006.201.03:45:05.75#ibcon#read 4, iclass 11, count 2 2006.201.03:45:05.75#ibcon#about to read 5, iclass 11, count 2 2006.201.03:45:05.75#ibcon#read 5, iclass 11, count 2 2006.201.03:45:05.75#ibcon#about to read 6, iclass 11, count 2 2006.201.03:45:05.75#ibcon#read 6, iclass 11, count 2 2006.201.03:45:05.75#ibcon#end of sib2, iclass 11, count 2 2006.201.03:45:05.75#ibcon#*mode == 0, iclass 11, count 2 2006.201.03:45:05.75#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.03:45:05.75#ibcon#[25=AT06-05\r\n] 2006.201.03:45:05.75#ibcon#*before write, iclass 11, count 2 2006.201.03:45:05.75#ibcon#enter sib2, iclass 11, count 2 2006.201.03:45:05.75#ibcon#flushed, iclass 11, count 2 2006.201.03:45:05.75#ibcon#about to write, iclass 11, count 2 2006.201.03:45:05.75#ibcon#wrote, iclass 11, count 2 2006.201.03:45:05.75#ibcon#about to read 3, iclass 11, count 2 2006.201.03:45:05.78#ibcon#read 3, iclass 11, count 2 2006.201.03:45:05.78#ibcon#about to read 4, iclass 11, count 2 2006.201.03:45:05.78#ibcon#read 4, iclass 11, count 2 2006.201.03:45:05.78#ibcon#about to read 5, iclass 11, count 2 2006.201.03:45:05.78#ibcon#read 5, iclass 11, count 2 2006.201.03:45:05.78#ibcon#about to read 6, iclass 11, count 2 2006.201.03:45:05.78#ibcon#read 6, iclass 11, count 2 2006.201.03:45:05.78#ibcon#end of sib2, iclass 11, count 2 2006.201.03:45:05.78#ibcon#*after write, iclass 11, count 2 2006.201.03:45:05.78#ibcon#*before return 0, iclass 11, count 2 2006.201.03:45:05.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:05.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:05.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.03:45:05.78#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:05.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:05.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:05.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:05.90#ibcon#enter wrdev, iclass 11, count 0 2006.201.03:45:05.90#ibcon#first serial, iclass 11, count 0 2006.201.03:45:05.90#ibcon#enter sib2, iclass 11, count 0 2006.201.03:45:05.90#ibcon#flushed, iclass 11, count 0 2006.201.03:45:05.90#ibcon#about to write, iclass 11, count 0 2006.201.03:45:05.90#ibcon#wrote, iclass 11, count 0 2006.201.03:45:05.90#ibcon#about to read 3, iclass 11, count 0 2006.201.03:45:05.92#ibcon#read 3, iclass 11, count 0 2006.201.03:45:05.92#ibcon#about to read 4, iclass 11, count 0 2006.201.03:45:05.92#ibcon#read 4, iclass 11, count 0 2006.201.03:45:05.92#ibcon#about to read 5, iclass 11, count 0 2006.201.03:45:05.92#ibcon#read 5, iclass 11, count 0 2006.201.03:45:05.92#ibcon#about to read 6, iclass 11, count 0 2006.201.03:45:05.92#ibcon#read 6, iclass 11, count 0 2006.201.03:45:05.92#ibcon#end of sib2, iclass 11, count 0 2006.201.03:45:05.92#ibcon#*mode == 0, iclass 11, count 0 2006.201.03:45:05.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.03:45:05.92#ibcon#[25=USB\r\n] 2006.201.03:45:05.92#ibcon#*before write, iclass 11, count 0 2006.201.03:45:05.92#ibcon#enter sib2, iclass 11, count 0 2006.201.03:45:05.92#ibcon#flushed, iclass 11, count 0 2006.201.03:45:05.92#ibcon#about to write, iclass 11, count 0 2006.201.03:45:05.92#ibcon#wrote, iclass 11, count 0 2006.201.03:45:05.92#ibcon#about to read 3, iclass 11, count 0 2006.201.03:45:05.95#ibcon#read 3, iclass 11, count 0 2006.201.03:45:05.95#ibcon#about to read 4, iclass 11, count 0 2006.201.03:45:05.95#ibcon#read 4, iclass 11, count 0 2006.201.03:45:05.95#ibcon#about to read 5, iclass 11, count 0 2006.201.03:45:05.95#ibcon#read 5, iclass 11, count 0 2006.201.03:45:05.95#ibcon#about to read 6, iclass 11, count 0 2006.201.03:45:05.95#ibcon#read 6, iclass 11, count 0 2006.201.03:45:05.95#ibcon#end of sib2, iclass 11, count 0 2006.201.03:45:05.95#ibcon#*after write, iclass 11, count 0 2006.201.03:45:05.95#ibcon#*before return 0, iclass 11, count 0 2006.201.03:45:05.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:05.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:05.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.03:45:05.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.03:45:05.95$vck44/valo=7,864.99 2006.201.03:45:05.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.03:45:05.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.03:45:05.95#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:05.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:05.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:05.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:05.95#ibcon#enter wrdev, iclass 13, count 0 2006.201.03:45:05.95#ibcon#first serial, iclass 13, count 0 2006.201.03:45:05.95#ibcon#enter sib2, iclass 13, count 0 2006.201.03:45:05.95#ibcon#flushed, iclass 13, count 0 2006.201.03:45:05.95#ibcon#about to write, iclass 13, count 0 2006.201.03:45:05.95#ibcon#wrote, iclass 13, count 0 2006.201.03:45:05.95#ibcon#about to read 3, iclass 13, count 0 2006.201.03:45:05.97#ibcon#read 3, iclass 13, count 0 2006.201.03:45:05.97#ibcon#about to read 4, iclass 13, count 0 2006.201.03:45:05.97#ibcon#read 4, iclass 13, count 0 2006.201.03:45:05.97#ibcon#about to read 5, iclass 13, count 0 2006.201.03:45:05.97#ibcon#read 5, iclass 13, count 0 2006.201.03:45:05.97#ibcon#about to read 6, iclass 13, count 0 2006.201.03:45:05.97#ibcon#read 6, iclass 13, count 0 2006.201.03:45:05.97#ibcon#end of sib2, iclass 13, count 0 2006.201.03:45:05.97#ibcon#*mode == 0, iclass 13, count 0 2006.201.03:45:05.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.03:45:05.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:45:05.97#ibcon#*before write, iclass 13, count 0 2006.201.03:45:05.97#ibcon#enter sib2, iclass 13, count 0 2006.201.03:45:05.97#ibcon#flushed, iclass 13, count 0 2006.201.03:45:05.97#ibcon#about to write, iclass 13, count 0 2006.201.03:45:05.97#ibcon#wrote, iclass 13, count 0 2006.201.03:45:05.97#ibcon#about to read 3, iclass 13, count 0 2006.201.03:45:06.01#ibcon#read 3, iclass 13, count 0 2006.201.03:45:06.01#ibcon#about to read 4, iclass 13, count 0 2006.201.03:45:06.01#ibcon#read 4, iclass 13, count 0 2006.201.03:45:06.01#ibcon#about to read 5, iclass 13, count 0 2006.201.03:45:06.01#ibcon#read 5, iclass 13, count 0 2006.201.03:45:06.01#ibcon#about to read 6, iclass 13, count 0 2006.201.03:45:06.01#ibcon#read 6, iclass 13, count 0 2006.201.03:45:06.01#ibcon#end of sib2, iclass 13, count 0 2006.201.03:45:06.01#ibcon#*after write, iclass 13, count 0 2006.201.03:45:06.01#ibcon#*before return 0, iclass 13, count 0 2006.201.03:45:06.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:06.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:06.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.03:45:06.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.03:45:06.01$vck44/va=7,5 2006.201.03:45:06.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.03:45:06.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.03:45:06.01#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:06.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:06.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:06.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:06.07#ibcon#enter wrdev, iclass 15, count 2 2006.201.03:45:06.07#ibcon#first serial, iclass 15, count 2 2006.201.03:45:06.07#ibcon#enter sib2, iclass 15, count 2 2006.201.03:45:06.07#ibcon#flushed, iclass 15, count 2 2006.201.03:45:06.07#ibcon#about to write, iclass 15, count 2 2006.201.03:45:06.07#ibcon#wrote, iclass 15, count 2 2006.201.03:45:06.07#ibcon#about to read 3, iclass 15, count 2 2006.201.03:45:06.09#ibcon#read 3, iclass 15, count 2 2006.201.03:45:06.09#ibcon#about to read 4, iclass 15, count 2 2006.201.03:45:06.09#ibcon#read 4, iclass 15, count 2 2006.201.03:45:06.09#ibcon#about to read 5, iclass 15, count 2 2006.201.03:45:06.09#ibcon#read 5, iclass 15, count 2 2006.201.03:45:06.09#ibcon#about to read 6, iclass 15, count 2 2006.201.03:45:06.09#ibcon#read 6, iclass 15, count 2 2006.201.03:45:06.09#ibcon#end of sib2, iclass 15, count 2 2006.201.03:45:06.09#ibcon#*mode == 0, iclass 15, count 2 2006.201.03:45:06.09#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.03:45:06.09#ibcon#[25=AT07-05\r\n] 2006.201.03:45:06.09#ibcon#*before write, iclass 15, count 2 2006.201.03:45:06.09#ibcon#enter sib2, iclass 15, count 2 2006.201.03:45:06.09#ibcon#flushed, iclass 15, count 2 2006.201.03:45:06.09#ibcon#about to write, iclass 15, count 2 2006.201.03:45:06.09#ibcon#wrote, iclass 15, count 2 2006.201.03:45:06.09#ibcon#about to read 3, iclass 15, count 2 2006.201.03:45:06.12#ibcon#read 3, iclass 15, count 2 2006.201.03:45:06.12#ibcon#about to read 4, iclass 15, count 2 2006.201.03:45:06.12#ibcon#read 4, iclass 15, count 2 2006.201.03:45:06.12#ibcon#about to read 5, iclass 15, count 2 2006.201.03:45:06.12#ibcon#read 5, iclass 15, count 2 2006.201.03:45:06.12#ibcon#about to read 6, iclass 15, count 2 2006.201.03:45:06.12#ibcon#read 6, iclass 15, count 2 2006.201.03:45:06.12#ibcon#end of sib2, iclass 15, count 2 2006.201.03:45:06.12#ibcon#*after write, iclass 15, count 2 2006.201.03:45:06.12#ibcon#*before return 0, iclass 15, count 2 2006.201.03:45:06.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:06.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:06.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.03:45:06.12#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:06.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:06.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:06.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:06.24#ibcon#enter wrdev, iclass 15, count 0 2006.201.03:45:06.24#ibcon#first serial, iclass 15, count 0 2006.201.03:45:06.24#ibcon#enter sib2, iclass 15, count 0 2006.201.03:45:06.24#ibcon#flushed, iclass 15, count 0 2006.201.03:45:06.24#ibcon#about to write, iclass 15, count 0 2006.201.03:45:06.24#ibcon#wrote, iclass 15, count 0 2006.201.03:45:06.24#ibcon#about to read 3, iclass 15, count 0 2006.201.03:45:06.26#ibcon#read 3, iclass 15, count 0 2006.201.03:45:06.26#ibcon#about to read 4, iclass 15, count 0 2006.201.03:45:06.26#ibcon#read 4, iclass 15, count 0 2006.201.03:45:06.26#ibcon#about to read 5, iclass 15, count 0 2006.201.03:45:06.26#ibcon#read 5, iclass 15, count 0 2006.201.03:45:06.26#ibcon#about to read 6, iclass 15, count 0 2006.201.03:45:06.26#ibcon#read 6, iclass 15, count 0 2006.201.03:45:06.26#ibcon#end of sib2, iclass 15, count 0 2006.201.03:45:06.26#ibcon#*mode == 0, iclass 15, count 0 2006.201.03:45:06.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.03:45:06.26#ibcon#[25=USB\r\n] 2006.201.03:45:06.26#ibcon#*before write, iclass 15, count 0 2006.201.03:45:06.26#ibcon#enter sib2, iclass 15, count 0 2006.201.03:45:06.26#ibcon#flushed, iclass 15, count 0 2006.201.03:45:06.26#ibcon#about to write, iclass 15, count 0 2006.201.03:45:06.26#ibcon#wrote, iclass 15, count 0 2006.201.03:45:06.26#ibcon#about to read 3, iclass 15, count 0 2006.201.03:45:06.29#ibcon#read 3, iclass 15, count 0 2006.201.03:45:06.29#ibcon#about to read 4, iclass 15, count 0 2006.201.03:45:06.29#ibcon#read 4, iclass 15, count 0 2006.201.03:45:06.29#ibcon#about to read 5, iclass 15, count 0 2006.201.03:45:06.29#ibcon#read 5, iclass 15, count 0 2006.201.03:45:06.29#ibcon#about to read 6, iclass 15, count 0 2006.201.03:45:06.29#ibcon#read 6, iclass 15, count 0 2006.201.03:45:06.29#ibcon#end of sib2, iclass 15, count 0 2006.201.03:45:06.29#ibcon#*after write, iclass 15, count 0 2006.201.03:45:06.29#ibcon#*before return 0, iclass 15, count 0 2006.201.03:45:06.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:06.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:06.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.03:45:06.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.03:45:06.29$vck44/valo=8,884.99 2006.201.03:45:06.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.03:45:06.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.03:45:06.29#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:06.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:06.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:06.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:06.29#ibcon#enter wrdev, iclass 17, count 0 2006.201.03:45:06.29#ibcon#first serial, iclass 17, count 0 2006.201.03:45:06.29#ibcon#enter sib2, iclass 17, count 0 2006.201.03:45:06.29#ibcon#flushed, iclass 17, count 0 2006.201.03:45:06.29#ibcon#about to write, iclass 17, count 0 2006.201.03:45:06.29#ibcon#wrote, iclass 17, count 0 2006.201.03:45:06.29#ibcon#about to read 3, iclass 17, count 0 2006.201.03:45:06.31#ibcon#read 3, iclass 17, count 0 2006.201.03:45:06.31#ibcon#about to read 4, iclass 17, count 0 2006.201.03:45:06.31#ibcon#read 4, iclass 17, count 0 2006.201.03:45:06.31#ibcon#about to read 5, iclass 17, count 0 2006.201.03:45:06.31#ibcon#read 5, iclass 17, count 0 2006.201.03:45:06.31#ibcon#about to read 6, iclass 17, count 0 2006.201.03:45:06.31#ibcon#read 6, iclass 17, count 0 2006.201.03:45:06.31#ibcon#end of sib2, iclass 17, count 0 2006.201.03:45:06.31#ibcon#*mode == 0, iclass 17, count 0 2006.201.03:45:06.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.03:45:06.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:45:06.31#ibcon#*before write, iclass 17, count 0 2006.201.03:45:06.31#ibcon#enter sib2, iclass 17, count 0 2006.201.03:45:06.31#ibcon#flushed, iclass 17, count 0 2006.201.03:45:06.31#ibcon#about to write, iclass 17, count 0 2006.201.03:45:06.31#ibcon#wrote, iclass 17, count 0 2006.201.03:45:06.31#ibcon#about to read 3, iclass 17, count 0 2006.201.03:45:06.35#ibcon#read 3, iclass 17, count 0 2006.201.03:45:06.35#ibcon#about to read 4, iclass 17, count 0 2006.201.03:45:06.35#ibcon#read 4, iclass 17, count 0 2006.201.03:45:06.35#ibcon#about to read 5, iclass 17, count 0 2006.201.03:45:06.35#ibcon#read 5, iclass 17, count 0 2006.201.03:45:06.35#ibcon#about to read 6, iclass 17, count 0 2006.201.03:45:06.35#ibcon#read 6, iclass 17, count 0 2006.201.03:45:06.35#ibcon#end of sib2, iclass 17, count 0 2006.201.03:45:06.35#ibcon#*after write, iclass 17, count 0 2006.201.03:45:06.35#ibcon#*before return 0, iclass 17, count 0 2006.201.03:45:06.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:06.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:06.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.03:45:06.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.03:45:06.35$vck44/va=8,4 2006.201.03:45:06.35#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.03:45:06.35#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.03:45:06.35#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:06.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:45:06.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:45:06.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:45:06.41#ibcon#enter wrdev, iclass 19, count 2 2006.201.03:45:06.41#ibcon#first serial, iclass 19, count 2 2006.201.03:45:06.41#ibcon#enter sib2, iclass 19, count 2 2006.201.03:45:06.41#ibcon#flushed, iclass 19, count 2 2006.201.03:45:06.41#ibcon#about to write, iclass 19, count 2 2006.201.03:45:06.41#ibcon#wrote, iclass 19, count 2 2006.201.03:45:06.41#ibcon#about to read 3, iclass 19, count 2 2006.201.03:45:06.43#ibcon#read 3, iclass 19, count 2 2006.201.03:45:06.43#ibcon#about to read 4, iclass 19, count 2 2006.201.03:45:06.43#ibcon#read 4, iclass 19, count 2 2006.201.03:45:06.43#ibcon#about to read 5, iclass 19, count 2 2006.201.03:45:06.43#ibcon#read 5, iclass 19, count 2 2006.201.03:45:06.43#ibcon#about to read 6, iclass 19, count 2 2006.201.03:45:06.43#ibcon#read 6, iclass 19, count 2 2006.201.03:45:06.43#ibcon#end of sib2, iclass 19, count 2 2006.201.03:45:06.43#ibcon#*mode == 0, iclass 19, count 2 2006.201.03:45:06.43#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.03:45:06.43#ibcon#[25=AT08-04\r\n] 2006.201.03:45:06.43#ibcon#*before write, iclass 19, count 2 2006.201.03:45:06.43#ibcon#enter sib2, iclass 19, count 2 2006.201.03:45:06.43#ibcon#flushed, iclass 19, count 2 2006.201.03:45:06.43#ibcon#about to write, iclass 19, count 2 2006.201.03:45:06.43#ibcon#wrote, iclass 19, count 2 2006.201.03:45:06.43#ibcon#about to read 3, iclass 19, count 2 2006.201.03:45:06.46#ibcon#read 3, iclass 19, count 2 2006.201.03:45:06.46#ibcon#about to read 4, iclass 19, count 2 2006.201.03:45:06.46#ibcon#read 4, iclass 19, count 2 2006.201.03:45:06.46#ibcon#about to read 5, iclass 19, count 2 2006.201.03:45:06.46#ibcon#read 5, iclass 19, count 2 2006.201.03:45:06.46#ibcon#about to read 6, iclass 19, count 2 2006.201.03:45:06.46#ibcon#read 6, iclass 19, count 2 2006.201.03:45:06.46#ibcon#end of sib2, iclass 19, count 2 2006.201.03:45:06.46#ibcon#*after write, iclass 19, count 2 2006.201.03:45:06.46#ibcon#*before return 0, iclass 19, count 2 2006.201.03:45:06.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:45:06.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.03:45:06.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.03:45:06.46#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:06.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:45:06.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:45:06.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:45:06.58#ibcon#enter wrdev, iclass 19, count 0 2006.201.03:45:06.58#ibcon#first serial, iclass 19, count 0 2006.201.03:45:06.58#ibcon#enter sib2, iclass 19, count 0 2006.201.03:45:06.58#ibcon#flushed, iclass 19, count 0 2006.201.03:45:06.58#ibcon#about to write, iclass 19, count 0 2006.201.03:45:06.58#ibcon#wrote, iclass 19, count 0 2006.201.03:45:06.58#ibcon#about to read 3, iclass 19, count 0 2006.201.03:45:06.60#ibcon#read 3, iclass 19, count 0 2006.201.03:45:06.60#ibcon#about to read 4, iclass 19, count 0 2006.201.03:45:06.60#ibcon#read 4, iclass 19, count 0 2006.201.03:45:06.60#ibcon#about to read 5, iclass 19, count 0 2006.201.03:45:06.60#ibcon#read 5, iclass 19, count 0 2006.201.03:45:06.60#ibcon#about to read 6, iclass 19, count 0 2006.201.03:45:06.60#ibcon#read 6, iclass 19, count 0 2006.201.03:45:06.60#ibcon#end of sib2, iclass 19, count 0 2006.201.03:45:06.60#ibcon#*mode == 0, iclass 19, count 0 2006.201.03:45:06.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.03:45:06.60#ibcon#[25=USB\r\n] 2006.201.03:45:06.60#ibcon#*before write, iclass 19, count 0 2006.201.03:45:06.60#ibcon#enter sib2, iclass 19, count 0 2006.201.03:45:06.60#ibcon#flushed, iclass 19, count 0 2006.201.03:45:06.60#ibcon#about to write, iclass 19, count 0 2006.201.03:45:06.60#ibcon#wrote, iclass 19, count 0 2006.201.03:45:06.60#ibcon#about to read 3, iclass 19, count 0 2006.201.03:45:06.63#ibcon#read 3, iclass 19, count 0 2006.201.03:45:06.63#ibcon#about to read 4, iclass 19, count 0 2006.201.03:45:06.63#ibcon#read 4, iclass 19, count 0 2006.201.03:45:06.63#ibcon#about to read 5, iclass 19, count 0 2006.201.03:45:06.63#ibcon#read 5, iclass 19, count 0 2006.201.03:45:06.63#ibcon#about to read 6, iclass 19, count 0 2006.201.03:45:06.63#ibcon#read 6, iclass 19, count 0 2006.201.03:45:06.63#ibcon#end of sib2, iclass 19, count 0 2006.201.03:45:06.63#ibcon#*after write, iclass 19, count 0 2006.201.03:45:06.63#ibcon#*before return 0, iclass 19, count 0 2006.201.03:45:06.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:45:06.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.03:45:06.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.03:45:06.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.03:45:06.63$vck44/vblo=1,629.99 2006.201.03:45:06.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.03:45:06.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.03:45:06.63#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:06.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:45:06.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:45:06.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:45:06.63#ibcon#enter wrdev, iclass 21, count 0 2006.201.03:45:06.63#ibcon#first serial, iclass 21, count 0 2006.201.03:45:06.63#ibcon#enter sib2, iclass 21, count 0 2006.201.03:45:06.63#ibcon#flushed, iclass 21, count 0 2006.201.03:45:06.63#ibcon#about to write, iclass 21, count 0 2006.201.03:45:06.63#ibcon#wrote, iclass 21, count 0 2006.201.03:45:06.63#ibcon#about to read 3, iclass 21, count 0 2006.201.03:45:06.65#ibcon#read 3, iclass 21, count 0 2006.201.03:45:06.65#ibcon#about to read 4, iclass 21, count 0 2006.201.03:45:06.65#ibcon#read 4, iclass 21, count 0 2006.201.03:45:06.65#ibcon#about to read 5, iclass 21, count 0 2006.201.03:45:06.65#ibcon#read 5, iclass 21, count 0 2006.201.03:45:06.65#ibcon#about to read 6, iclass 21, count 0 2006.201.03:45:06.65#ibcon#read 6, iclass 21, count 0 2006.201.03:45:06.65#ibcon#end of sib2, iclass 21, count 0 2006.201.03:45:06.65#ibcon#*mode == 0, iclass 21, count 0 2006.201.03:45:06.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.03:45:06.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:45:06.65#ibcon#*before write, iclass 21, count 0 2006.201.03:45:06.65#ibcon#enter sib2, iclass 21, count 0 2006.201.03:45:06.65#ibcon#flushed, iclass 21, count 0 2006.201.03:45:06.65#ibcon#about to write, iclass 21, count 0 2006.201.03:45:06.65#ibcon#wrote, iclass 21, count 0 2006.201.03:45:06.65#ibcon#about to read 3, iclass 21, count 0 2006.201.03:45:06.69#ibcon#read 3, iclass 21, count 0 2006.201.03:45:06.69#ibcon#about to read 4, iclass 21, count 0 2006.201.03:45:06.69#ibcon#read 4, iclass 21, count 0 2006.201.03:45:06.69#ibcon#about to read 5, iclass 21, count 0 2006.201.03:45:06.69#ibcon#read 5, iclass 21, count 0 2006.201.03:45:06.69#ibcon#about to read 6, iclass 21, count 0 2006.201.03:45:06.69#ibcon#read 6, iclass 21, count 0 2006.201.03:45:06.69#ibcon#end of sib2, iclass 21, count 0 2006.201.03:45:06.69#ibcon#*after write, iclass 21, count 0 2006.201.03:45:06.69#ibcon#*before return 0, iclass 21, count 0 2006.201.03:45:06.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:45:06.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:45:06.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.03:45:06.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.03:45:06.69$vck44/vb=1,4 2006.201.03:45:06.69#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.03:45:06.69#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.03:45:06.69#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:06.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:45:06.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:45:06.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:45:06.69#ibcon#enter wrdev, iclass 23, count 2 2006.201.03:45:06.69#ibcon#first serial, iclass 23, count 2 2006.201.03:45:06.69#ibcon#enter sib2, iclass 23, count 2 2006.201.03:45:06.69#ibcon#flushed, iclass 23, count 2 2006.201.03:45:06.69#ibcon#about to write, iclass 23, count 2 2006.201.03:45:06.69#ibcon#wrote, iclass 23, count 2 2006.201.03:45:06.69#ibcon#about to read 3, iclass 23, count 2 2006.201.03:45:06.71#ibcon#read 3, iclass 23, count 2 2006.201.03:45:06.71#ibcon#about to read 4, iclass 23, count 2 2006.201.03:45:06.71#ibcon#read 4, iclass 23, count 2 2006.201.03:45:06.71#ibcon#about to read 5, iclass 23, count 2 2006.201.03:45:06.71#ibcon#read 5, iclass 23, count 2 2006.201.03:45:06.71#ibcon#about to read 6, iclass 23, count 2 2006.201.03:45:06.71#ibcon#read 6, iclass 23, count 2 2006.201.03:45:06.71#ibcon#end of sib2, iclass 23, count 2 2006.201.03:45:06.71#ibcon#*mode == 0, iclass 23, count 2 2006.201.03:45:06.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.03:45:06.71#ibcon#[27=AT01-04\r\n] 2006.201.03:45:06.71#ibcon#*before write, iclass 23, count 2 2006.201.03:45:06.71#ibcon#enter sib2, iclass 23, count 2 2006.201.03:45:06.71#ibcon#flushed, iclass 23, count 2 2006.201.03:45:06.71#ibcon#about to write, iclass 23, count 2 2006.201.03:45:06.71#ibcon#wrote, iclass 23, count 2 2006.201.03:45:06.71#ibcon#about to read 3, iclass 23, count 2 2006.201.03:45:06.74#ibcon#read 3, iclass 23, count 2 2006.201.03:45:06.74#ibcon#about to read 4, iclass 23, count 2 2006.201.03:45:06.74#ibcon#read 4, iclass 23, count 2 2006.201.03:45:06.74#ibcon#about to read 5, iclass 23, count 2 2006.201.03:45:06.74#ibcon#read 5, iclass 23, count 2 2006.201.03:45:06.74#ibcon#about to read 6, iclass 23, count 2 2006.201.03:45:06.74#ibcon#read 6, iclass 23, count 2 2006.201.03:45:06.74#ibcon#end of sib2, iclass 23, count 2 2006.201.03:45:06.74#ibcon#*after write, iclass 23, count 2 2006.201.03:45:06.74#ibcon#*before return 0, iclass 23, count 2 2006.201.03:45:06.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:45:06.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.03:45:06.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.03:45:06.74#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:06.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:45:06.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:45:06.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:45:06.86#ibcon#enter wrdev, iclass 23, count 0 2006.201.03:45:06.86#ibcon#first serial, iclass 23, count 0 2006.201.03:45:06.86#ibcon#enter sib2, iclass 23, count 0 2006.201.03:45:06.86#ibcon#flushed, iclass 23, count 0 2006.201.03:45:06.86#ibcon#about to write, iclass 23, count 0 2006.201.03:45:06.86#ibcon#wrote, iclass 23, count 0 2006.201.03:45:06.86#ibcon#about to read 3, iclass 23, count 0 2006.201.03:45:06.88#ibcon#read 3, iclass 23, count 0 2006.201.03:45:06.88#ibcon#about to read 4, iclass 23, count 0 2006.201.03:45:06.88#ibcon#read 4, iclass 23, count 0 2006.201.03:45:06.88#ibcon#about to read 5, iclass 23, count 0 2006.201.03:45:06.88#ibcon#read 5, iclass 23, count 0 2006.201.03:45:06.88#ibcon#about to read 6, iclass 23, count 0 2006.201.03:45:06.88#ibcon#read 6, iclass 23, count 0 2006.201.03:45:06.88#ibcon#end of sib2, iclass 23, count 0 2006.201.03:45:06.88#ibcon#*mode == 0, iclass 23, count 0 2006.201.03:45:06.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.03:45:06.88#ibcon#[27=USB\r\n] 2006.201.03:45:06.88#ibcon#*before write, iclass 23, count 0 2006.201.03:45:06.88#ibcon#enter sib2, iclass 23, count 0 2006.201.03:45:06.88#ibcon#flushed, iclass 23, count 0 2006.201.03:45:06.88#ibcon#about to write, iclass 23, count 0 2006.201.03:45:06.88#ibcon#wrote, iclass 23, count 0 2006.201.03:45:06.88#ibcon#about to read 3, iclass 23, count 0 2006.201.03:45:06.91#ibcon#read 3, iclass 23, count 0 2006.201.03:45:06.91#ibcon#about to read 4, iclass 23, count 0 2006.201.03:45:06.91#ibcon#read 4, iclass 23, count 0 2006.201.03:45:06.91#ibcon#about to read 5, iclass 23, count 0 2006.201.03:45:06.91#ibcon#read 5, iclass 23, count 0 2006.201.03:45:06.91#ibcon#about to read 6, iclass 23, count 0 2006.201.03:45:06.91#ibcon#read 6, iclass 23, count 0 2006.201.03:45:06.91#ibcon#end of sib2, iclass 23, count 0 2006.201.03:45:06.91#ibcon#*after write, iclass 23, count 0 2006.201.03:45:06.91#ibcon#*before return 0, iclass 23, count 0 2006.201.03:45:06.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:45:06.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.03:45:06.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.03:45:06.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.03:45:06.91$vck44/vblo=2,634.99 2006.201.03:45:06.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.03:45:06.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.03:45:06.91#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:06.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:06.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:06.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:06.91#ibcon#enter wrdev, iclass 25, count 0 2006.201.03:45:06.91#ibcon#first serial, iclass 25, count 0 2006.201.03:45:06.91#ibcon#enter sib2, iclass 25, count 0 2006.201.03:45:06.91#ibcon#flushed, iclass 25, count 0 2006.201.03:45:06.91#ibcon#about to write, iclass 25, count 0 2006.201.03:45:06.91#ibcon#wrote, iclass 25, count 0 2006.201.03:45:06.91#ibcon#about to read 3, iclass 25, count 0 2006.201.03:45:06.93#ibcon#read 3, iclass 25, count 0 2006.201.03:45:06.93#ibcon#about to read 4, iclass 25, count 0 2006.201.03:45:06.93#ibcon#read 4, iclass 25, count 0 2006.201.03:45:06.93#ibcon#about to read 5, iclass 25, count 0 2006.201.03:45:06.93#ibcon#read 5, iclass 25, count 0 2006.201.03:45:06.93#ibcon#about to read 6, iclass 25, count 0 2006.201.03:45:06.93#ibcon#read 6, iclass 25, count 0 2006.201.03:45:06.93#ibcon#end of sib2, iclass 25, count 0 2006.201.03:45:06.93#ibcon#*mode == 0, iclass 25, count 0 2006.201.03:45:06.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.03:45:06.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:45:06.93#ibcon#*before write, iclass 25, count 0 2006.201.03:45:06.93#ibcon#enter sib2, iclass 25, count 0 2006.201.03:45:06.93#ibcon#flushed, iclass 25, count 0 2006.201.03:45:06.93#ibcon#about to write, iclass 25, count 0 2006.201.03:45:06.93#ibcon#wrote, iclass 25, count 0 2006.201.03:45:06.93#ibcon#about to read 3, iclass 25, count 0 2006.201.03:45:06.97#ibcon#read 3, iclass 25, count 0 2006.201.03:45:06.97#ibcon#about to read 4, iclass 25, count 0 2006.201.03:45:06.97#ibcon#read 4, iclass 25, count 0 2006.201.03:45:06.97#ibcon#about to read 5, iclass 25, count 0 2006.201.03:45:06.97#ibcon#read 5, iclass 25, count 0 2006.201.03:45:06.97#ibcon#about to read 6, iclass 25, count 0 2006.201.03:45:06.97#ibcon#read 6, iclass 25, count 0 2006.201.03:45:06.97#ibcon#end of sib2, iclass 25, count 0 2006.201.03:45:06.97#ibcon#*after write, iclass 25, count 0 2006.201.03:45:06.97#ibcon#*before return 0, iclass 25, count 0 2006.201.03:45:06.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:06.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.03:45:06.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.03:45:06.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.03:45:06.97$vck44/vb=2,5 2006.201.03:45:06.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.03:45:06.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.03:45:06.97#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:06.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:07.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:07.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:07.03#ibcon#enter wrdev, iclass 27, count 2 2006.201.03:45:07.03#ibcon#first serial, iclass 27, count 2 2006.201.03:45:07.03#ibcon#enter sib2, iclass 27, count 2 2006.201.03:45:07.03#ibcon#flushed, iclass 27, count 2 2006.201.03:45:07.03#ibcon#about to write, iclass 27, count 2 2006.201.03:45:07.03#ibcon#wrote, iclass 27, count 2 2006.201.03:45:07.03#ibcon#about to read 3, iclass 27, count 2 2006.201.03:45:07.05#ibcon#read 3, iclass 27, count 2 2006.201.03:45:07.05#ibcon#about to read 4, iclass 27, count 2 2006.201.03:45:07.05#ibcon#read 4, iclass 27, count 2 2006.201.03:45:07.05#ibcon#about to read 5, iclass 27, count 2 2006.201.03:45:07.05#ibcon#read 5, iclass 27, count 2 2006.201.03:45:07.05#ibcon#about to read 6, iclass 27, count 2 2006.201.03:45:07.05#ibcon#read 6, iclass 27, count 2 2006.201.03:45:07.05#ibcon#end of sib2, iclass 27, count 2 2006.201.03:45:07.05#ibcon#*mode == 0, iclass 27, count 2 2006.201.03:45:07.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.03:45:07.05#ibcon#[27=AT02-05\r\n] 2006.201.03:45:07.05#ibcon#*before write, iclass 27, count 2 2006.201.03:45:07.05#ibcon#enter sib2, iclass 27, count 2 2006.201.03:45:07.05#ibcon#flushed, iclass 27, count 2 2006.201.03:45:07.05#ibcon#about to write, iclass 27, count 2 2006.201.03:45:07.05#ibcon#wrote, iclass 27, count 2 2006.201.03:45:07.05#ibcon#about to read 3, iclass 27, count 2 2006.201.03:45:07.08#ibcon#read 3, iclass 27, count 2 2006.201.03:45:07.08#ibcon#about to read 4, iclass 27, count 2 2006.201.03:45:07.08#ibcon#read 4, iclass 27, count 2 2006.201.03:45:07.08#ibcon#about to read 5, iclass 27, count 2 2006.201.03:45:07.08#ibcon#read 5, iclass 27, count 2 2006.201.03:45:07.08#ibcon#about to read 6, iclass 27, count 2 2006.201.03:45:07.08#ibcon#read 6, iclass 27, count 2 2006.201.03:45:07.08#ibcon#end of sib2, iclass 27, count 2 2006.201.03:45:07.08#ibcon#*after write, iclass 27, count 2 2006.201.03:45:07.08#ibcon#*before return 0, iclass 27, count 2 2006.201.03:45:07.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:07.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.03:45:07.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.03:45:07.08#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:07.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:07.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:07.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:07.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.03:45:07.20#ibcon#first serial, iclass 27, count 0 2006.201.03:45:07.20#ibcon#enter sib2, iclass 27, count 0 2006.201.03:45:07.20#ibcon#flushed, iclass 27, count 0 2006.201.03:45:07.20#ibcon#about to write, iclass 27, count 0 2006.201.03:45:07.20#ibcon#wrote, iclass 27, count 0 2006.201.03:45:07.20#ibcon#about to read 3, iclass 27, count 0 2006.201.03:45:07.23#ibcon#read 3, iclass 27, count 0 2006.201.03:45:07.23#ibcon#about to read 4, iclass 27, count 0 2006.201.03:45:07.23#ibcon#read 4, iclass 27, count 0 2006.201.03:45:07.23#ibcon#about to read 5, iclass 27, count 0 2006.201.03:45:07.23#ibcon#read 5, iclass 27, count 0 2006.201.03:45:07.23#ibcon#about to read 6, iclass 27, count 0 2006.201.03:45:07.23#ibcon#read 6, iclass 27, count 0 2006.201.03:45:07.23#ibcon#end of sib2, iclass 27, count 0 2006.201.03:45:07.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.03:45:07.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.03:45:07.23#ibcon#[27=USB\r\n] 2006.201.03:45:07.23#ibcon#*before write, iclass 27, count 0 2006.201.03:45:07.23#ibcon#enter sib2, iclass 27, count 0 2006.201.03:45:07.23#ibcon#flushed, iclass 27, count 0 2006.201.03:45:07.23#ibcon#about to write, iclass 27, count 0 2006.201.03:45:07.23#ibcon#wrote, iclass 27, count 0 2006.201.03:45:07.23#ibcon#about to read 3, iclass 27, count 0 2006.201.03:45:07.26#ibcon#read 3, iclass 27, count 0 2006.201.03:45:07.26#ibcon#about to read 4, iclass 27, count 0 2006.201.03:45:07.26#ibcon#read 4, iclass 27, count 0 2006.201.03:45:07.26#ibcon#about to read 5, iclass 27, count 0 2006.201.03:45:07.26#ibcon#read 5, iclass 27, count 0 2006.201.03:45:07.26#ibcon#about to read 6, iclass 27, count 0 2006.201.03:45:07.26#ibcon#read 6, iclass 27, count 0 2006.201.03:45:07.26#ibcon#end of sib2, iclass 27, count 0 2006.201.03:45:07.26#ibcon#*after write, iclass 27, count 0 2006.201.03:45:07.26#ibcon#*before return 0, iclass 27, count 0 2006.201.03:45:07.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:07.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.03:45:07.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.03:45:07.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.03:45:07.26$vck44/vblo=3,649.99 2006.201.03:45:07.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.03:45:07.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.03:45:07.26#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:07.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:07.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:07.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:07.26#ibcon#enter wrdev, iclass 29, count 0 2006.201.03:45:07.26#ibcon#first serial, iclass 29, count 0 2006.201.03:45:07.26#ibcon#enter sib2, iclass 29, count 0 2006.201.03:45:07.26#ibcon#flushed, iclass 29, count 0 2006.201.03:45:07.26#ibcon#about to write, iclass 29, count 0 2006.201.03:45:07.26#ibcon#wrote, iclass 29, count 0 2006.201.03:45:07.26#ibcon#about to read 3, iclass 29, count 0 2006.201.03:45:07.28#ibcon#read 3, iclass 29, count 0 2006.201.03:45:07.28#ibcon#about to read 4, iclass 29, count 0 2006.201.03:45:07.28#ibcon#read 4, iclass 29, count 0 2006.201.03:45:07.28#ibcon#about to read 5, iclass 29, count 0 2006.201.03:45:07.28#ibcon#read 5, iclass 29, count 0 2006.201.03:45:07.28#ibcon#about to read 6, iclass 29, count 0 2006.201.03:45:07.28#ibcon#read 6, iclass 29, count 0 2006.201.03:45:07.28#ibcon#end of sib2, iclass 29, count 0 2006.201.03:45:07.28#ibcon#*mode == 0, iclass 29, count 0 2006.201.03:45:07.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.03:45:07.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:45:07.28#ibcon#*before write, iclass 29, count 0 2006.201.03:45:07.28#ibcon#enter sib2, iclass 29, count 0 2006.201.03:45:07.28#ibcon#flushed, iclass 29, count 0 2006.201.03:45:07.28#ibcon#about to write, iclass 29, count 0 2006.201.03:45:07.28#ibcon#wrote, iclass 29, count 0 2006.201.03:45:07.28#ibcon#about to read 3, iclass 29, count 0 2006.201.03:45:07.32#ibcon#read 3, iclass 29, count 0 2006.201.03:45:07.32#ibcon#about to read 4, iclass 29, count 0 2006.201.03:45:07.32#ibcon#read 4, iclass 29, count 0 2006.201.03:45:07.32#ibcon#about to read 5, iclass 29, count 0 2006.201.03:45:07.32#ibcon#read 5, iclass 29, count 0 2006.201.03:45:07.32#ibcon#about to read 6, iclass 29, count 0 2006.201.03:45:07.32#ibcon#read 6, iclass 29, count 0 2006.201.03:45:07.32#ibcon#end of sib2, iclass 29, count 0 2006.201.03:45:07.32#ibcon#*after write, iclass 29, count 0 2006.201.03:45:07.32#ibcon#*before return 0, iclass 29, count 0 2006.201.03:45:07.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:07.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.03:45:07.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.03:45:07.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.03:45:07.32$vck44/vb=3,4 2006.201.03:45:07.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.03:45:07.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.03:45:07.32#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:07.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:07.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:07.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:07.38#ibcon#enter wrdev, iclass 31, count 2 2006.201.03:45:07.38#ibcon#first serial, iclass 31, count 2 2006.201.03:45:07.38#ibcon#enter sib2, iclass 31, count 2 2006.201.03:45:07.38#ibcon#flushed, iclass 31, count 2 2006.201.03:45:07.38#ibcon#about to write, iclass 31, count 2 2006.201.03:45:07.38#ibcon#wrote, iclass 31, count 2 2006.201.03:45:07.38#ibcon#about to read 3, iclass 31, count 2 2006.201.03:45:07.40#ibcon#read 3, iclass 31, count 2 2006.201.03:45:07.40#ibcon#about to read 4, iclass 31, count 2 2006.201.03:45:07.40#ibcon#read 4, iclass 31, count 2 2006.201.03:45:07.40#ibcon#about to read 5, iclass 31, count 2 2006.201.03:45:07.40#ibcon#read 5, iclass 31, count 2 2006.201.03:45:07.40#ibcon#about to read 6, iclass 31, count 2 2006.201.03:45:07.40#ibcon#read 6, iclass 31, count 2 2006.201.03:45:07.40#ibcon#end of sib2, iclass 31, count 2 2006.201.03:45:07.40#ibcon#*mode == 0, iclass 31, count 2 2006.201.03:45:07.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.03:45:07.40#ibcon#[27=AT03-04\r\n] 2006.201.03:45:07.40#ibcon#*before write, iclass 31, count 2 2006.201.03:45:07.40#ibcon#enter sib2, iclass 31, count 2 2006.201.03:45:07.40#ibcon#flushed, iclass 31, count 2 2006.201.03:45:07.40#ibcon#about to write, iclass 31, count 2 2006.201.03:45:07.40#ibcon#wrote, iclass 31, count 2 2006.201.03:45:07.40#ibcon#about to read 3, iclass 31, count 2 2006.201.03:45:07.43#ibcon#read 3, iclass 31, count 2 2006.201.03:45:07.43#ibcon#about to read 4, iclass 31, count 2 2006.201.03:45:07.43#ibcon#read 4, iclass 31, count 2 2006.201.03:45:07.43#ibcon#about to read 5, iclass 31, count 2 2006.201.03:45:07.43#ibcon#read 5, iclass 31, count 2 2006.201.03:45:07.43#ibcon#about to read 6, iclass 31, count 2 2006.201.03:45:07.43#ibcon#read 6, iclass 31, count 2 2006.201.03:45:07.43#ibcon#end of sib2, iclass 31, count 2 2006.201.03:45:07.43#ibcon#*after write, iclass 31, count 2 2006.201.03:45:07.43#ibcon#*before return 0, iclass 31, count 2 2006.201.03:45:07.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:07.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.03:45:07.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.03:45:07.43#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:07.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:07.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:07.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:07.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.03:45:07.55#ibcon#first serial, iclass 31, count 0 2006.201.03:45:07.55#ibcon#enter sib2, iclass 31, count 0 2006.201.03:45:07.55#ibcon#flushed, iclass 31, count 0 2006.201.03:45:07.55#ibcon#about to write, iclass 31, count 0 2006.201.03:45:07.55#ibcon#wrote, iclass 31, count 0 2006.201.03:45:07.55#ibcon#about to read 3, iclass 31, count 0 2006.201.03:45:07.57#ibcon#read 3, iclass 31, count 0 2006.201.03:45:07.57#ibcon#about to read 4, iclass 31, count 0 2006.201.03:45:07.57#ibcon#read 4, iclass 31, count 0 2006.201.03:45:07.57#ibcon#about to read 5, iclass 31, count 0 2006.201.03:45:07.57#ibcon#read 5, iclass 31, count 0 2006.201.03:45:07.57#ibcon#about to read 6, iclass 31, count 0 2006.201.03:45:07.57#ibcon#read 6, iclass 31, count 0 2006.201.03:45:07.57#ibcon#end of sib2, iclass 31, count 0 2006.201.03:45:07.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.03:45:07.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.03:45:07.57#ibcon#[27=USB\r\n] 2006.201.03:45:07.57#ibcon#*before write, iclass 31, count 0 2006.201.03:45:07.57#ibcon#enter sib2, iclass 31, count 0 2006.201.03:45:07.57#ibcon#flushed, iclass 31, count 0 2006.201.03:45:07.57#ibcon#about to write, iclass 31, count 0 2006.201.03:45:07.57#ibcon#wrote, iclass 31, count 0 2006.201.03:45:07.57#ibcon#about to read 3, iclass 31, count 0 2006.201.03:45:07.60#ibcon#read 3, iclass 31, count 0 2006.201.03:45:07.60#ibcon#about to read 4, iclass 31, count 0 2006.201.03:45:07.60#ibcon#read 4, iclass 31, count 0 2006.201.03:45:07.60#ibcon#about to read 5, iclass 31, count 0 2006.201.03:45:07.60#ibcon#read 5, iclass 31, count 0 2006.201.03:45:07.60#ibcon#about to read 6, iclass 31, count 0 2006.201.03:45:07.60#ibcon#read 6, iclass 31, count 0 2006.201.03:45:07.60#ibcon#end of sib2, iclass 31, count 0 2006.201.03:45:07.60#ibcon#*after write, iclass 31, count 0 2006.201.03:45:07.60#ibcon#*before return 0, iclass 31, count 0 2006.201.03:45:07.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:07.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.03:45:07.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.03:45:07.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.03:45:07.60$vck44/vblo=4,679.99 2006.201.03:45:07.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.03:45:07.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.03:45:07.60#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:07.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:07.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:07.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:07.60#ibcon#enter wrdev, iclass 33, count 0 2006.201.03:45:07.60#ibcon#first serial, iclass 33, count 0 2006.201.03:45:07.60#ibcon#enter sib2, iclass 33, count 0 2006.201.03:45:07.60#ibcon#flushed, iclass 33, count 0 2006.201.03:45:07.60#ibcon#about to write, iclass 33, count 0 2006.201.03:45:07.60#ibcon#wrote, iclass 33, count 0 2006.201.03:45:07.60#ibcon#about to read 3, iclass 33, count 0 2006.201.03:45:07.62#ibcon#read 3, iclass 33, count 0 2006.201.03:45:07.62#ibcon#about to read 4, iclass 33, count 0 2006.201.03:45:07.62#ibcon#read 4, iclass 33, count 0 2006.201.03:45:07.62#ibcon#about to read 5, iclass 33, count 0 2006.201.03:45:07.62#ibcon#read 5, iclass 33, count 0 2006.201.03:45:07.62#ibcon#about to read 6, iclass 33, count 0 2006.201.03:45:07.62#ibcon#read 6, iclass 33, count 0 2006.201.03:45:07.62#ibcon#end of sib2, iclass 33, count 0 2006.201.03:45:07.62#ibcon#*mode == 0, iclass 33, count 0 2006.201.03:45:07.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.03:45:07.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:45:07.62#ibcon#*before write, iclass 33, count 0 2006.201.03:45:07.62#ibcon#enter sib2, iclass 33, count 0 2006.201.03:45:07.62#ibcon#flushed, iclass 33, count 0 2006.201.03:45:07.62#ibcon#about to write, iclass 33, count 0 2006.201.03:45:07.62#ibcon#wrote, iclass 33, count 0 2006.201.03:45:07.62#ibcon#about to read 3, iclass 33, count 0 2006.201.03:45:07.66#ibcon#read 3, iclass 33, count 0 2006.201.03:45:07.66#ibcon#about to read 4, iclass 33, count 0 2006.201.03:45:07.66#ibcon#read 4, iclass 33, count 0 2006.201.03:45:07.66#ibcon#about to read 5, iclass 33, count 0 2006.201.03:45:07.66#ibcon#read 5, iclass 33, count 0 2006.201.03:45:07.66#ibcon#about to read 6, iclass 33, count 0 2006.201.03:45:07.66#ibcon#read 6, iclass 33, count 0 2006.201.03:45:07.66#ibcon#end of sib2, iclass 33, count 0 2006.201.03:45:07.66#ibcon#*after write, iclass 33, count 0 2006.201.03:45:07.66#ibcon#*before return 0, iclass 33, count 0 2006.201.03:45:07.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:07.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.03:45:07.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.03:45:07.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.03:45:07.66$vck44/vb=4,5 2006.201.03:45:07.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.03:45:07.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.03:45:07.66#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:07.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:07.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:07.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:07.72#ibcon#enter wrdev, iclass 35, count 2 2006.201.03:45:07.72#ibcon#first serial, iclass 35, count 2 2006.201.03:45:07.72#ibcon#enter sib2, iclass 35, count 2 2006.201.03:45:07.72#ibcon#flushed, iclass 35, count 2 2006.201.03:45:07.72#ibcon#about to write, iclass 35, count 2 2006.201.03:45:07.72#ibcon#wrote, iclass 35, count 2 2006.201.03:45:07.72#ibcon#about to read 3, iclass 35, count 2 2006.201.03:45:07.74#ibcon#read 3, iclass 35, count 2 2006.201.03:45:07.74#ibcon#about to read 4, iclass 35, count 2 2006.201.03:45:07.74#ibcon#read 4, iclass 35, count 2 2006.201.03:45:07.74#ibcon#about to read 5, iclass 35, count 2 2006.201.03:45:07.74#ibcon#read 5, iclass 35, count 2 2006.201.03:45:07.74#ibcon#about to read 6, iclass 35, count 2 2006.201.03:45:07.74#ibcon#read 6, iclass 35, count 2 2006.201.03:45:07.74#ibcon#end of sib2, iclass 35, count 2 2006.201.03:45:07.74#ibcon#*mode == 0, iclass 35, count 2 2006.201.03:45:07.74#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.03:45:07.74#ibcon#[27=AT04-05\r\n] 2006.201.03:45:07.74#ibcon#*before write, iclass 35, count 2 2006.201.03:45:07.74#ibcon#enter sib2, iclass 35, count 2 2006.201.03:45:07.74#ibcon#flushed, iclass 35, count 2 2006.201.03:45:07.74#ibcon#about to write, iclass 35, count 2 2006.201.03:45:07.74#ibcon#wrote, iclass 35, count 2 2006.201.03:45:07.74#ibcon#about to read 3, iclass 35, count 2 2006.201.03:45:07.77#ibcon#read 3, iclass 35, count 2 2006.201.03:45:07.77#ibcon#about to read 4, iclass 35, count 2 2006.201.03:45:07.77#ibcon#read 4, iclass 35, count 2 2006.201.03:45:07.77#ibcon#about to read 5, iclass 35, count 2 2006.201.03:45:07.77#ibcon#read 5, iclass 35, count 2 2006.201.03:45:07.77#ibcon#about to read 6, iclass 35, count 2 2006.201.03:45:07.77#ibcon#read 6, iclass 35, count 2 2006.201.03:45:07.77#ibcon#end of sib2, iclass 35, count 2 2006.201.03:45:07.77#ibcon#*after write, iclass 35, count 2 2006.201.03:45:07.77#ibcon#*before return 0, iclass 35, count 2 2006.201.03:45:07.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:07.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.03:45:07.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.03:45:07.77#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:07.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:07.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:07.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:07.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.03:45:07.89#ibcon#first serial, iclass 35, count 0 2006.201.03:45:07.89#ibcon#enter sib2, iclass 35, count 0 2006.201.03:45:07.89#ibcon#flushed, iclass 35, count 0 2006.201.03:45:07.89#ibcon#about to write, iclass 35, count 0 2006.201.03:45:07.89#ibcon#wrote, iclass 35, count 0 2006.201.03:45:07.89#ibcon#about to read 3, iclass 35, count 0 2006.201.03:45:07.91#ibcon#read 3, iclass 35, count 0 2006.201.03:45:07.91#ibcon#about to read 4, iclass 35, count 0 2006.201.03:45:07.91#ibcon#read 4, iclass 35, count 0 2006.201.03:45:07.91#ibcon#about to read 5, iclass 35, count 0 2006.201.03:45:07.91#ibcon#read 5, iclass 35, count 0 2006.201.03:45:07.91#ibcon#about to read 6, iclass 35, count 0 2006.201.03:45:07.91#ibcon#read 6, iclass 35, count 0 2006.201.03:45:07.91#ibcon#end of sib2, iclass 35, count 0 2006.201.03:45:07.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.03:45:07.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.03:45:07.91#ibcon#[27=USB\r\n] 2006.201.03:45:07.91#ibcon#*before write, iclass 35, count 0 2006.201.03:45:07.91#ibcon#enter sib2, iclass 35, count 0 2006.201.03:45:07.91#ibcon#flushed, iclass 35, count 0 2006.201.03:45:07.91#ibcon#about to write, iclass 35, count 0 2006.201.03:45:07.91#ibcon#wrote, iclass 35, count 0 2006.201.03:45:07.91#ibcon#about to read 3, iclass 35, count 0 2006.201.03:45:07.94#ibcon#read 3, iclass 35, count 0 2006.201.03:45:07.94#ibcon#about to read 4, iclass 35, count 0 2006.201.03:45:07.94#ibcon#read 4, iclass 35, count 0 2006.201.03:45:07.94#ibcon#about to read 5, iclass 35, count 0 2006.201.03:45:07.94#ibcon#read 5, iclass 35, count 0 2006.201.03:45:07.94#ibcon#about to read 6, iclass 35, count 0 2006.201.03:45:07.94#ibcon#read 6, iclass 35, count 0 2006.201.03:45:07.94#ibcon#end of sib2, iclass 35, count 0 2006.201.03:45:07.94#ibcon#*after write, iclass 35, count 0 2006.201.03:45:07.94#ibcon#*before return 0, iclass 35, count 0 2006.201.03:45:07.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:07.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.03:45:07.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.03:45:07.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.03:45:07.94$vck44/vblo=5,709.99 2006.201.03:45:07.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.03:45:07.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.03:45:07.94#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:07.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:07.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:07.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:07.94#ibcon#enter wrdev, iclass 37, count 0 2006.201.03:45:07.94#ibcon#first serial, iclass 37, count 0 2006.201.03:45:07.94#ibcon#enter sib2, iclass 37, count 0 2006.201.03:45:07.94#ibcon#flushed, iclass 37, count 0 2006.201.03:45:07.94#ibcon#about to write, iclass 37, count 0 2006.201.03:45:07.94#ibcon#wrote, iclass 37, count 0 2006.201.03:45:07.94#ibcon#about to read 3, iclass 37, count 0 2006.201.03:45:07.96#ibcon#read 3, iclass 37, count 0 2006.201.03:45:07.96#ibcon#about to read 4, iclass 37, count 0 2006.201.03:45:07.96#ibcon#read 4, iclass 37, count 0 2006.201.03:45:07.96#ibcon#about to read 5, iclass 37, count 0 2006.201.03:45:07.96#ibcon#read 5, iclass 37, count 0 2006.201.03:45:07.96#ibcon#about to read 6, iclass 37, count 0 2006.201.03:45:07.96#ibcon#read 6, iclass 37, count 0 2006.201.03:45:07.96#ibcon#end of sib2, iclass 37, count 0 2006.201.03:45:07.96#ibcon#*mode == 0, iclass 37, count 0 2006.201.03:45:07.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.03:45:07.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:45:07.96#ibcon#*before write, iclass 37, count 0 2006.201.03:45:07.96#ibcon#enter sib2, iclass 37, count 0 2006.201.03:45:07.96#ibcon#flushed, iclass 37, count 0 2006.201.03:45:07.96#ibcon#about to write, iclass 37, count 0 2006.201.03:45:07.96#ibcon#wrote, iclass 37, count 0 2006.201.03:45:07.96#ibcon#about to read 3, iclass 37, count 0 2006.201.03:45:08.01#ibcon#read 3, iclass 37, count 0 2006.201.03:45:08.01#ibcon#about to read 4, iclass 37, count 0 2006.201.03:45:08.01#ibcon#read 4, iclass 37, count 0 2006.201.03:45:08.01#ibcon#about to read 5, iclass 37, count 0 2006.201.03:45:08.01#ibcon#read 5, iclass 37, count 0 2006.201.03:45:08.01#ibcon#about to read 6, iclass 37, count 0 2006.201.03:45:08.01#ibcon#read 6, iclass 37, count 0 2006.201.03:45:08.01#ibcon#end of sib2, iclass 37, count 0 2006.201.03:45:08.01#ibcon#*after write, iclass 37, count 0 2006.201.03:45:08.01#ibcon#*before return 0, iclass 37, count 0 2006.201.03:45:08.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:08.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.03:45:08.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.03:45:08.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.03:45:08.01$vck44/vb=5,4 2006.201.03:45:08.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.03:45:08.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.03:45:08.01#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:08.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:08.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:08.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:08.06#ibcon#enter wrdev, iclass 39, count 2 2006.201.03:45:08.06#ibcon#first serial, iclass 39, count 2 2006.201.03:45:08.06#ibcon#enter sib2, iclass 39, count 2 2006.201.03:45:08.06#ibcon#flushed, iclass 39, count 2 2006.201.03:45:08.06#ibcon#about to write, iclass 39, count 2 2006.201.03:45:08.06#ibcon#wrote, iclass 39, count 2 2006.201.03:45:08.06#ibcon#about to read 3, iclass 39, count 2 2006.201.03:45:08.08#ibcon#read 3, iclass 39, count 2 2006.201.03:45:08.08#ibcon#about to read 4, iclass 39, count 2 2006.201.03:45:08.08#ibcon#read 4, iclass 39, count 2 2006.201.03:45:08.08#ibcon#about to read 5, iclass 39, count 2 2006.201.03:45:08.08#ibcon#read 5, iclass 39, count 2 2006.201.03:45:08.08#ibcon#about to read 6, iclass 39, count 2 2006.201.03:45:08.08#ibcon#read 6, iclass 39, count 2 2006.201.03:45:08.08#ibcon#end of sib2, iclass 39, count 2 2006.201.03:45:08.08#ibcon#*mode == 0, iclass 39, count 2 2006.201.03:45:08.08#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.03:45:08.08#ibcon#[27=AT05-04\r\n] 2006.201.03:45:08.08#ibcon#*before write, iclass 39, count 2 2006.201.03:45:08.08#ibcon#enter sib2, iclass 39, count 2 2006.201.03:45:08.08#ibcon#flushed, iclass 39, count 2 2006.201.03:45:08.08#ibcon#about to write, iclass 39, count 2 2006.201.03:45:08.08#ibcon#wrote, iclass 39, count 2 2006.201.03:45:08.08#ibcon#about to read 3, iclass 39, count 2 2006.201.03:45:08.11#ibcon#read 3, iclass 39, count 2 2006.201.03:45:08.11#ibcon#about to read 4, iclass 39, count 2 2006.201.03:45:08.11#ibcon#read 4, iclass 39, count 2 2006.201.03:45:08.11#ibcon#about to read 5, iclass 39, count 2 2006.201.03:45:08.11#ibcon#read 5, iclass 39, count 2 2006.201.03:45:08.11#ibcon#about to read 6, iclass 39, count 2 2006.201.03:45:08.11#ibcon#read 6, iclass 39, count 2 2006.201.03:45:08.11#ibcon#end of sib2, iclass 39, count 2 2006.201.03:45:08.11#ibcon#*after write, iclass 39, count 2 2006.201.03:45:08.11#ibcon#*before return 0, iclass 39, count 2 2006.201.03:45:08.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:08.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.03:45:08.11#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.03:45:08.11#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:08.11#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:08.23#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:08.23#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:08.23#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:45:08.23#ibcon#first serial, iclass 39, count 0 2006.201.03:45:08.23#ibcon#enter sib2, iclass 39, count 0 2006.201.03:45:08.23#ibcon#flushed, iclass 39, count 0 2006.201.03:45:08.23#ibcon#about to write, iclass 39, count 0 2006.201.03:45:08.23#ibcon#wrote, iclass 39, count 0 2006.201.03:45:08.23#ibcon#about to read 3, iclass 39, count 0 2006.201.03:45:08.25#ibcon#read 3, iclass 39, count 0 2006.201.03:45:08.25#ibcon#about to read 4, iclass 39, count 0 2006.201.03:45:08.25#ibcon#read 4, iclass 39, count 0 2006.201.03:45:08.25#ibcon#about to read 5, iclass 39, count 0 2006.201.03:45:08.25#ibcon#read 5, iclass 39, count 0 2006.201.03:45:08.25#ibcon#about to read 6, iclass 39, count 0 2006.201.03:45:08.25#ibcon#read 6, iclass 39, count 0 2006.201.03:45:08.25#ibcon#end of sib2, iclass 39, count 0 2006.201.03:45:08.25#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:45:08.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:45:08.25#ibcon#[27=USB\r\n] 2006.201.03:45:08.25#ibcon#*before write, iclass 39, count 0 2006.201.03:45:08.25#ibcon#enter sib2, iclass 39, count 0 2006.201.03:45:08.25#ibcon#flushed, iclass 39, count 0 2006.201.03:45:08.25#ibcon#about to write, iclass 39, count 0 2006.201.03:45:08.25#ibcon#wrote, iclass 39, count 0 2006.201.03:45:08.25#ibcon#about to read 3, iclass 39, count 0 2006.201.03:45:08.28#ibcon#read 3, iclass 39, count 0 2006.201.03:45:08.28#ibcon#about to read 4, iclass 39, count 0 2006.201.03:45:08.28#ibcon#read 4, iclass 39, count 0 2006.201.03:45:08.28#ibcon#about to read 5, iclass 39, count 0 2006.201.03:45:08.28#ibcon#read 5, iclass 39, count 0 2006.201.03:45:08.28#ibcon#about to read 6, iclass 39, count 0 2006.201.03:45:08.28#ibcon#read 6, iclass 39, count 0 2006.201.03:45:08.28#ibcon#end of sib2, iclass 39, count 0 2006.201.03:45:08.28#ibcon#*after write, iclass 39, count 0 2006.201.03:45:08.28#ibcon#*before return 0, iclass 39, count 0 2006.201.03:45:08.28#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:08.28#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.03:45:08.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:45:08.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:45:08.28$vck44/vblo=6,719.99 2006.201.03:45:08.28#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.03:45:08.28#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.03:45:08.28#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:08.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:08.28#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:08.28#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:08.28#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:45:08.28#ibcon#first serial, iclass 2, count 0 2006.201.03:45:08.28#ibcon#enter sib2, iclass 2, count 0 2006.201.03:45:08.28#ibcon#flushed, iclass 2, count 0 2006.201.03:45:08.28#ibcon#about to write, iclass 2, count 0 2006.201.03:45:08.28#ibcon#wrote, iclass 2, count 0 2006.201.03:45:08.28#ibcon#about to read 3, iclass 2, count 0 2006.201.03:45:08.30#ibcon#read 3, iclass 2, count 0 2006.201.03:45:08.30#ibcon#about to read 4, iclass 2, count 0 2006.201.03:45:08.30#ibcon#read 4, iclass 2, count 0 2006.201.03:45:08.30#ibcon#about to read 5, iclass 2, count 0 2006.201.03:45:08.30#ibcon#read 5, iclass 2, count 0 2006.201.03:45:08.30#ibcon#about to read 6, iclass 2, count 0 2006.201.03:45:08.30#ibcon#read 6, iclass 2, count 0 2006.201.03:45:08.30#ibcon#end of sib2, iclass 2, count 0 2006.201.03:45:08.30#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:45:08.30#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:45:08.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:45:08.30#ibcon#*before write, iclass 2, count 0 2006.201.03:45:08.30#ibcon#enter sib2, iclass 2, count 0 2006.201.03:45:08.30#ibcon#flushed, iclass 2, count 0 2006.201.03:45:08.30#ibcon#about to write, iclass 2, count 0 2006.201.03:45:08.30#ibcon#wrote, iclass 2, count 0 2006.201.03:45:08.30#ibcon#about to read 3, iclass 2, count 0 2006.201.03:45:08.34#ibcon#read 3, iclass 2, count 0 2006.201.03:45:08.34#ibcon#about to read 4, iclass 2, count 0 2006.201.03:45:08.34#ibcon#read 4, iclass 2, count 0 2006.201.03:45:08.34#ibcon#about to read 5, iclass 2, count 0 2006.201.03:45:08.34#ibcon#read 5, iclass 2, count 0 2006.201.03:45:08.34#ibcon#about to read 6, iclass 2, count 0 2006.201.03:45:08.34#ibcon#read 6, iclass 2, count 0 2006.201.03:45:08.34#ibcon#end of sib2, iclass 2, count 0 2006.201.03:45:08.34#ibcon#*after write, iclass 2, count 0 2006.201.03:45:08.34#ibcon#*before return 0, iclass 2, count 0 2006.201.03:45:08.34#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:08.34#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.03:45:08.34#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:45:08.34#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:45:08.34$vck44/vb=6,4 2006.201.03:45:08.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.03:45:08.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.03:45:08.34#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:08.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:08.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:08.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:08.40#ibcon#enter wrdev, iclass 5, count 2 2006.201.03:45:08.40#ibcon#first serial, iclass 5, count 2 2006.201.03:45:08.40#ibcon#enter sib2, iclass 5, count 2 2006.201.03:45:08.40#ibcon#flushed, iclass 5, count 2 2006.201.03:45:08.40#ibcon#about to write, iclass 5, count 2 2006.201.03:45:08.40#ibcon#wrote, iclass 5, count 2 2006.201.03:45:08.40#ibcon#about to read 3, iclass 5, count 2 2006.201.03:45:08.42#ibcon#read 3, iclass 5, count 2 2006.201.03:45:08.42#ibcon#about to read 4, iclass 5, count 2 2006.201.03:45:08.42#ibcon#read 4, iclass 5, count 2 2006.201.03:45:08.42#ibcon#about to read 5, iclass 5, count 2 2006.201.03:45:08.42#ibcon#read 5, iclass 5, count 2 2006.201.03:45:08.42#ibcon#about to read 6, iclass 5, count 2 2006.201.03:45:08.42#ibcon#read 6, iclass 5, count 2 2006.201.03:45:08.42#ibcon#end of sib2, iclass 5, count 2 2006.201.03:45:08.42#ibcon#*mode == 0, iclass 5, count 2 2006.201.03:45:08.42#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.03:45:08.42#ibcon#[27=AT06-04\r\n] 2006.201.03:45:08.42#ibcon#*before write, iclass 5, count 2 2006.201.03:45:08.42#ibcon#enter sib2, iclass 5, count 2 2006.201.03:45:08.42#ibcon#flushed, iclass 5, count 2 2006.201.03:45:08.42#ibcon#about to write, iclass 5, count 2 2006.201.03:45:08.42#ibcon#wrote, iclass 5, count 2 2006.201.03:45:08.42#ibcon#about to read 3, iclass 5, count 2 2006.201.03:45:08.45#ibcon#read 3, iclass 5, count 2 2006.201.03:45:08.45#ibcon#about to read 4, iclass 5, count 2 2006.201.03:45:08.45#ibcon#read 4, iclass 5, count 2 2006.201.03:45:08.45#ibcon#about to read 5, iclass 5, count 2 2006.201.03:45:08.45#ibcon#read 5, iclass 5, count 2 2006.201.03:45:08.45#ibcon#about to read 6, iclass 5, count 2 2006.201.03:45:08.45#ibcon#read 6, iclass 5, count 2 2006.201.03:45:08.45#ibcon#end of sib2, iclass 5, count 2 2006.201.03:45:08.45#ibcon#*after write, iclass 5, count 2 2006.201.03:45:08.45#ibcon#*before return 0, iclass 5, count 2 2006.201.03:45:08.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:08.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.03:45:08.45#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.03:45:08.45#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:08.45#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:08.57#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:08.57#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:08.57#ibcon#enter wrdev, iclass 5, count 0 2006.201.03:45:08.57#ibcon#first serial, iclass 5, count 0 2006.201.03:45:08.57#ibcon#enter sib2, iclass 5, count 0 2006.201.03:45:08.57#ibcon#flushed, iclass 5, count 0 2006.201.03:45:08.57#ibcon#about to write, iclass 5, count 0 2006.201.03:45:08.57#ibcon#wrote, iclass 5, count 0 2006.201.03:45:08.57#ibcon#about to read 3, iclass 5, count 0 2006.201.03:45:08.59#ibcon#read 3, iclass 5, count 0 2006.201.03:45:08.59#ibcon#about to read 4, iclass 5, count 0 2006.201.03:45:08.59#ibcon#read 4, iclass 5, count 0 2006.201.03:45:08.59#ibcon#about to read 5, iclass 5, count 0 2006.201.03:45:08.59#ibcon#read 5, iclass 5, count 0 2006.201.03:45:08.59#ibcon#about to read 6, iclass 5, count 0 2006.201.03:45:08.59#ibcon#read 6, iclass 5, count 0 2006.201.03:45:08.59#ibcon#end of sib2, iclass 5, count 0 2006.201.03:45:08.59#ibcon#*mode == 0, iclass 5, count 0 2006.201.03:45:08.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.03:45:08.59#ibcon#[27=USB\r\n] 2006.201.03:45:08.59#ibcon#*before write, iclass 5, count 0 2006.201.03:45:08.59#ibcon#enter sib2, iclass 5, count 0 2006.201.03:45:08.59#ibcon#flushed, iclass 5, count 0 2006.201.03:45:08.59#ibcon#about to write, iclass 5, count 0 2006.201.03:45:08.59#ibcon#wrote, iclass 5, count 0 2006.201.03:45:08.59#ibcon#about to read 3, iclass 5, count 0 2006.201.03:45:08.62#ibcon#read 3, iclass 5, count 0 2006.201.03:45:08.62#ibcon#about to read 4, iclass 5, count 0 2006.201.03:45:08.62#ibcon#read 4, iclass 5, count 0 2006.201.03:45:08.62#ibcon#about to read 5, iclass 5, count 0 2006.201.03:45:08.62#ibcon#read 5, iclass 5, count 0 2006.201.03:45:08.62#ibcon#about to read 6, iclass 5, count 0 2006.201.03:45:08.62#ibcon#read 6, iclass 5, count 0 2006.201.03:45:08.62#ibcon#end of sib2, iclass 5, count 0 2006.201.03:45:08.62#ibcon#*after write, iclass 5, count 0 2006.201.03:45:08.62#ibcon#*before return 0, iclass 5, count 0 2006.201.03:45:08.62#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:08.62#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.03:45:08.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.03:45:08.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.03:45:08.62$vck44/vblo=7,734.99 2006.201.03:45:08.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.03:45:08.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.03:45:08.62#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:08.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:08.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:08.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:08.62#ibcon#enter wrdev, iclass 7, count 0 2006.201.03:45:08.62#ibcon#first serial, iclass 7, count 0 2006.201.03:45:08.62#ibcon#enter sib2, iclass 7, count 0 2006.201.03:45:08.62#ibcon#flushed, iclass 7, count 0 2006.201.03:45:08.62#ibcon#about to write, iclass 7, count 0 2006.201.03:45:08.62#ibcon#wrote, iclass 7, count 0 2006.201.03:45:08.62#ibcon#about to read 3, iclass 7, count 0 2006.201.03:45:08.64#ibcon#read 3, iclass 7, count 0 2006.201.03:45:08.64#ibcon#about to read 4, iclass 7, count 0 2006.201.03:45:08.64#ibcon#read 4, iclass 7, count 0 2006.201.03:45:08.64#ibcon#about to read 5, iclass 7, count 0 2006.201.03:45:08.64#ibcon#read 5, iclass 7, count 0 2006.201.03:45:08.64#ibcon#about to read 6, iclass 7, count 0 2006.201.03:45:08.64#ibcon#read 6, iclass 7, count 0 2006.201.03:45:08.64#ibcon#end of sib2, iclass 7, count 0 2006.201.03:45:08.64#ibcon#*mode == 0, iclass 7, count 0 2006.201.03:45:08.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.03:45:08.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:45:08.64#ibcon#*before write, iclass 7, count 0 2006.201.03:45:08.64#ibcon#enter sib2, iclass 7, count 0 2006.201.03:45:08.64#ibcon#flushed, iclass 7, count 0 2006.201.03:45:08.64#ibcon#about to write, iclass 7, count 0 2006.201.03:45:08.64#ibcon#wrote, iclass 7, count 0 2006.201.03:45:08.64#ibcon#about to read 3, iclass 7, count 0 2006.201.03:45:08.68#ibcon#read 3, iclass 7, count 0 2006.201.03:45:08.68#ibcon#about to read 4, iclass 7, count 0 2006.201.03:45:08.68#ibcon#read 4, iclass 7, count 0 2006.201.03:45:08.68#ibcon#about to read 5, iclass 7, count 0 2006.201.03:45:08.68#ibcon#read 5, iclass 7, count 0 2006.201.03:45:08.68#ibcon#about to read 6, iclass 7, count 0 2006.201.03:45:08.68#ibcon#read 6, iclass 7, count 0 2006.201.03:45:08.68#ibcon#end of sib2, iclass 7, count 0 2006.201.03:45:08.68#ibcon#*after write, iclass 7, count 0 2006.201.03:45:08.68#ibcon#*before return 0, iclass 7, count 0 2006.201.03:45:08.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:08.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.03:45:08.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.03:45:08.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.03:45:08.68$vck44/vb=7,4 2006.201.03:45:08.68#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.03:45:08.68#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.03:45:08.68#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:08.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:08.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:08.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:08.74#ibcon#enter wrdev, iclass 11, count 2 2006.201.03:45:08.74#ibcon#first serial, iclass 11, count 2 2006.201.03:45:08.74#ibcon#enter sib2, iclass 11, count 2 2006.201.03:45:08.74#ibcon#flushed, iclass 11, count 2 2006.201.03:45:08.74#ibcon#about to write, iclass 11, count 2 2006.201.03:45:08.74#ibcon#wrote, iclass 11, count 2 2006.201.03:45:08.74#ibcon#about to read 3, iclass 11, count 2 2006.201.03:45:08.76#ibcon#read 3, iclass 11, count 2 2006.201.03:45:08.76#ibcon#about to read 4, iclass 11, count 2 2006.201.03:45:08.76#ibcon#read 4, iclass 11, count 2 2006.201.03:45:08.76#ibcon#about to read 5, iclass 11, count 2 2006.201.03:45:08.76#ibcon#read 5, iclass 11, count 2 2006.201.03:45:08.76#ibcon#about to read 6, iclass 11, count 2 2006.201.03:45:08.76#ibcon#read 6, iclass 11, count 2 2006.201.03:45:08.76#ibcon#end of sib2, iclass 11, count 2 2006.201.03:45:08.76#ibcon#*mode == 0, iclass 11, count 2 2006.201.03:45:08.76#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.03:45:08.76#ibcon#[27=AT07-04\r\n] 2006.201.03:45:08.76#ibcon#*before write, iclass 11, count 2 2006.201.03:45:08.76#ibcon#enter sib2, iclass 11, count 2 2006.201.03:45:08.76#ibcon#flushed, iclass 11, count 2 2006.201.03:45:08.76#ibcon#about to write, iclass 11, count 2 2006.201.03:45:08.76#ibcon#wrote, iclass 11, count 2 2006.201.03:45:08.76#ibcon#about to read 3, iclass 11, count 2 2006.201.03:45:08.79#ibcon#read 3, iclass 11, count 2 2006.201.03:45:08.79#ibcon#about to read 4, iclass 11, count 2 2006.201.03:45:08.79#ibcon#read 4, iclass 11, count 2 2006.201.03:45:08.79#ibcon#about to read 5, iclass 11, count 2 2006.201.03:45:08.79#ibcon#read 5, iclass 11, count 2 2006.201.03:45:08.79#ibcon#about to read 6, iclass 11, count 2 2006.201.03:45:08.79#ibcon#read 6, iclass 11, count 2 2006.201.03:45:08.79#ibcon#end of sib2, iclass 11, count 2 2006.201.03:45:08.79#ibcon#*after write, iclass 11, count 2 2006.201.03:45:08.79#ibcon#*before return 0, iclass 11, count 2 2006.201.03:45:08.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:08.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.03:45:08.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.03:45:08.79#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:08.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:08.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:08.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:08.91#ibcon#enter wrdev, iclass 11, count 0 2006.201.03:45:08.91#ibcon#first serial, iclass 11, count 0 2006.201.03:45:08.91#ibcon#enter sib2, iclass 11, count 0 2006.201.03:45:08.91#ibcon#flushed, iclass 11, count 0 2006.201.03:45:08.91#ibcon#about to write, iclass 11, count 0 2006.201.03:45:08.91#ibcon#wrote, iclass 11, count 0 2006.201.03:45:08.91#ibcon#about to read 3, iclass 11, count 0 2006.201.03:45:08.93#ibcon#read 3, iclass 11, count 0 2006.201.03:45:08.93#ibcon#about to read 4, iclass 11, count 0 2006.201.03:45:08.93#ibcon#read 4, iclass 11, count 0 2006.201.03:45:08.93#ibcon#about to read 5, iclass 11, count 0 2006.201.03:45:08.93#ibcon#read 5, iclass 11, count 0 2006.201.03:45:08.93#ibcon#about to read 6, iclass 11, count 0 2006.201.03:45:08.93#ibcon#read 6, iclass 11, count 0 2006.201.03:45:08.93#ibcon#end of sib2, iclass 11, count 0 2006.201.03:45:08.93#ibcon#*mode == 0, iclass 11, count 0 2006.201.03:45:08.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.03:45:08.93#ibcon#[27=USB\r\n] 2006.201.03:45:08.93#ibcon#*before write, iclass 11, count 0 2006.201.03:45:08.93#ibcon#enter sib2, iclass 11, count 0 2006.201.03:45:08.93#ibcon#flushed, iclass 11, count 0 2006.201.03:45:08.93#ibcon#about to write, iclass 11, count 0 2006.201.03:45:08.93#ibcon#wrote, iclass 11, count 0 2006.201.03:45:08.93#ibcon#about to read 3, iclass 11, count 0 2006.201.03:45:08.96#ibcon#read 3, iclass 11, count 0 2006.201.03:45:08.96#ibcon#about to read 4, iclass 11, count 0 2006.201.03:45:08.96#ibcon#read 4, iclass 11, count 0 2006.201.03:45:08.96#ibcon#about to read 5, iclass 11, count 0 2006.201.03:45:08.96#ibcon#read 5, iclass 11, count 0 2006.201.03:45:08.96#ibcon#about to read 6, iclass 11, count 0 2006.201.03:45:08.96#ibcon#read 6, iclass 11, count 0 2006.201.03:45:08.96#ibcon#end of sib2, iclass 11, count 0 2006.201.03:45:08.96#ibcon#*after write, iclass 11, count 0 2006.201.03:45:08.96#ibcon#*before return 0, iclass 11, count 0 2006.201.03:45:08.96#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:08.96#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.03:45:08.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.03:45:08.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.03:45:08.96$vck44/vblo=8,744.99 2006.201.03:45:08.96#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.03:45:08.96#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.03:45:08.96#ibcon#ireg 17 cls_cnt 0 2006.201.03:45:08.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:08.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:08.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:08.96#ibcon#enter wrdev, iclass 13, count 0 2006.201.03:45:08.96#ibcon#first serial, iclass 13, count 0 2006.201.03:45:08.96#ibcon#enter sib2, iclass 13, count 0 2006.201.03:45:08.96#ibcon#flushed, iclass 13, count 0 2006.201.03:45:08.96#ibcon#about to write, iclass 13, count 0 2006.201.03:45:08.96#ibcon#wrote, iclass 13, count 0 2006.201.03:45:08.96#ibcon#about to read 3, iclass 13, count 0 2006.201.03:45:08.98#ibcon#read 3, iclass 13, count 0 2006.201.03:45:08.98#ibcon#about to read 4, iclass 13, count 0 2006.201.03:45:08.98#ibcon#read 4, iclass 13, count 0 2006.201.03:45:08.98#ibcon#about to read 5, iclass 13, count 0 2006.201.03:45:08.98#ibcon#read 5, iclass 13, count 0 2006.201.03:45:08.98#ibcon#about to read 6, iclass 13, count 0 2006.201.03:45:08.98#ibcon#read 6, iclass 13, count 0 2006.201.03:45:08.98#ibcon#end of sib2, iclass 13, count 0 2006.201.03:45:08.98#ibcon#*mode == 0, iclass 13, count 0 2006.201.03:45:08.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.03:45:08.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:45:08.98#ibcon#*before write, iclass 13, count 0 2006.201.03:45:08.98#ibcon#enter sib2, iclass 13, count 0 2006.201.03:45:08.98#ibcon#flushed, iclass 13, count 0 2006.201.03:45:08.98#ibcon#about to write, iclass 13, count 0 2006.201.03:45:08.98#ibcon#wrote, iclass 13, count 0 2006.201.03:45:08.98#ibcon#about to read 3, iclass 13, count 0 2006.201.03:45:09.03#ibcon#read 3, iclass 13, count 0 2006.201.03:45:09.03#ibcon#about to read 4, iclass 13, count 0 2006.201.03:45:09.03#ibcon#read 4, iclass 13, count 0 2006.201.03:45:09.03#ibcon#about to read 5, iclass 13, count 0 2006.201.03:45:09.03#ibcon#read 5, iclass 13, count 0 2006.201.03:45:09.03#ibcon#about to read 6, iclass 13, count 0 2006.201.03:45:09.03#ibcon#read 6, iclass 13, count 0 2006.201.03:45:09.03#ibcon#end of sib2, iclass 13, count 0 2006.201.03:45:09.03#ibcon#*after write, iclass 13, count 0 2006.201.03:45:09.03#ibcon#*before return 0, iclass 13, count 0 2006.201.03:45:09.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:09.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.03:45:09.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.03:45:09.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.03:45:09.03$vck44/vb=8,4 2006.201.03:45:09.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.03:45:09.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.03:45:09.03#ibcon#ireg 11 cls_cnt 2 2006.201.03:45:09.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:09.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:09.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:09.08#ibcon#enter wrdev, iclass 15, count 2 2006.201.03:45:09.08#ibcon#first serial, iclass 15, count 2 2006.201.03:45:09.08#ibcon#enter sib2, iclass 15, count 2 2006.201.03:45:09.08#ibcon#flushed, iclass 15, count 2 2006.201.03:45:09.08#ibcon#about to write, iclass 15, count 2 2006.201.03:45:09.08#ibcon#wrote, iclass 15, count 2 2006.201.03:45:09.08#ibcon#about to read 3, iclass 15, count 2 2006.201.03:45:09.10#ibcon#read 3, iclass 15, count 2 2006.201.03:45:09.10#ibcon#about to read 4, iclass 15, count 2 2006.201.03:45:09.10#ibcon#read 4, iclass 15, count 2 2006.201.03:45:09.10#ibcon#about to read 5, iclass 15, count 2 2006.201.03:45:09.10#ibcon#read 5, iclass 15, count 2 2006.201.03:45:09.10#ibcon#about to read 6, iclass 15, count 2 2006.201.03:45:09.10#ibcon#read 6, iclass 15, count 2 2006.201.03:45:09.10#ibcon#end of sib2, iclass 15, count 2 2006.201.03:45:09.10#ibcon#*mode == 0, iclass 15, count 2 2006.201.03:45:09.10#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.03:45:09.10#ibcon#[27=AT08-04\r\n] 2006.201.03:45:09.10#ibcon#*before write, iclass 15, count 2 2006.201.03:45:09.10#ibcon#enter sib2, iclass 15, count 2 2006.201.03:45:09.10#ibcon#flushed, iclass 15, count 2 2006.201.03:45:09.10#ibcon#about to write, iclass 15, count 2 2006.201.03:45:09.10#ibcon#wrote, iclass 15, count 2 2006.201.03:45:09.10#ibcon#about to read 3, iclass 15, count 2 2006.201.03:45:09.13#ibcon#read 3, iclass 15, count 2 2006.201.03:45:09.13#ibcon#about to read 4, iclass 15, count 2 2006.201.03:45:09.13#ibcon#read 4, iclass 15, count 2 2006.201.03:45:09.13#ibcon#about to read 5, iclass 15, count 2 2006.201.03:45:09.13#ibcon#read 5, iclass 15, count 2 2006.201.03:45:09.13#ibcon#about to read 6, iclass 15, count 2 2006.201.03:45:09.13#ibcon#read 6, iclass 15, count 2 2006.201.03:45:09.13#ibcon#end of sib2, iclass 15, count 2 2006.201.03:45:09.13#ibcon#*after write, iclass 15, count 2 2006.201.03:45:09.13#ibcon#*before return 0, iclass 15, count 2 2006.201.03:45:09.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:09.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.03:45:09.13#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.03:45:09.13#ibcon#ireg 7 cls_cnt 0 2006.201.03:45:09.13#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:09.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:09.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:09.25#ibcon#enter wrdev, iclass 15, count 0 2006.201.03:45:09.25#ibcon#first serial, iclass 15, count 0 2006.201.03:45:09.25#ibcon#enter sib2, iclass 15, count 0 2006.201.03:45:09.25#ibcon#flushed, iclass 15, count 0 2006.201.03:45:09.25#ibcon#about to write, iclass 15, count 0 2006.201.03:45:09.25#ibcon#wrote, iclass 15, count 0 2006.201.03:45:09.25#ibcon#about to read 3, iclass 15, count 0 2006.201.03:45:09.27#ibcon#read 3, iclass 15, count 0 2006.201.03:45:09.27#ibcon#about to read 4, iclass 15, count 0 2006.201.03:45:09.27#ibcon#read 4, iclass 15, count 0 2006.201.03:45:09.27#ibcon#about to read 5, iclass 15, count 0 2006.201.03:45:09.27#ibcon#read 5, iclass 15, count 0 2006.201.03:45:09.27#ibcon#about to read 6, iclass 15, count 0 2006.201.03:45:09.27#ibcon#read 6, iclass 15, count 0 2006.201.03:45:09.27#ibcon#end of sib2, iclass 15, count 0 2006.201.03:45:09.27#ibcon#*mode == 0, iclass 15, count 0 2006.201.03:45:09.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.03:45:09.27#ibcon#[27=USB\r\n] 2006.201.03:45:09.27#ibcon#*before write, iclass 15, count 0 2006.201.03:45:09.27#ibcon#enter sib2, iclass 15, count 0 2006.201.03:45:09.27#ibcon#flushed, iclass 15, count 0 2006.201.03:45:09.27#ibcon#about to write, iclass 15, count 0 2006.201.03:45:09.27#ibcon#wrote, iclass 15, count 0 2006.201.03:45:09.27#ibcon#about to read 3, iclass 15, count 0 2006.201.03:45:09.30#ibcon#read 3, iclass 15, count 0 2006.201.03:45:09.30#ibcon#about to read 4, iclass 15, count 0 2006.201.03:45:09.30#ibcon#read 4, iclass 15, count 0 2006.201.03:45:09.30#ibcon#about to read 5, iclass 15, count 0 2006.201.03:45:09.30#ibcon#read 5, iclass 15, count 0 2006.201.03:45:09.30#ibcon#about to read 6, iclass 15, count 0 2006.201.03:45:09.30#ibcon#read 6, iclass 15, count 0 2006.201.03:45:09.30#ibcon#end of sib2, iclass 15, count 0 2006.201.03:45:09.30#ibcon#*after write, iclass 15, count 0 2006.201.03:45:09.30#ibcon#*before return 0, iclass 15, count 0 2006.201.03:45:09.30#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:09.30#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.03:45:09.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.03:45:09.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.03:45:09.30$vck44/vabw=wide 2006.201.03:45:09.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.03:45:09.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.03:45:09.30#ibcon#ireg 8 cls_cnt 0 2006.201.03:45:09.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:09.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:09.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:09.30#ibcon#enter wrdev, iclass 17, count 0 2006.201.03:45:09.30#ibcon#first serial, iclass 17, count 0 2006.201.03:45:09.30#ibcon#enter sib2, iclass 17, count 0 2006.201.03:45:09.30#ibcon#flushed, iclass 17, count 0 2006.201.03:45:09.30#ibcon#about to write, iclass 17, count 0 2006.201.03:45:09.30#ibcon#wrote, iclass 17, count 0 2006.201.03:45:09.30#ibcon#about to read 3, iclass 17, count 0 2006.201.03:45:09.32#ibcon#read 3, iclass 17, count 0 2006.201.03:45:09.32#ibcon#about to read 4, iclass 17, count 0 2006.201.03:45:09.32#ibcon#read 4, iclass 17, count 0 2006.201.03:45:09.32#ibcon#about to read 5, iclass 17, count 0 2006.201.03:45:09.32#ibcon#read 5, iclass 17, count 0 2006.201.03:45:09.32#ibcon#about to read 6, iclass 17, count 0 2006.201.03:45:09.32#ibcon#read 6, iclass 17, count 0 2006.201.03:45:09.32#ibcon#end of sib2, iclass 17, count 0 2006.201.03:45:09.32#ibcon#*mode == 0, iclass 17, count 0 2006.201.03:45:09.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.03:45:09.32#ibcon#[25=BW32\r\n] 2006.201.03:45:09.32#ibcon#*before write, iclass 17, count 0 2006.201.03:45:09.32#ibcon#enter sib2, iclass 17, count 0 2006.201.03:45:09.32#ibcon#flushed, iclass 17, count 0 2006.201.03:45:09.32#ibcon#about to write, iclass 17, count 0 2006.201.03:45:09.32#ibcon#wrote, iclass 17, count 0 2006.201.03:45:09.32#ibcon#about to read 3, iclass 17, count 0 2006.201.03:45:09.35#ibcon#read 3, iclass 17, count 0 2006.201.03:45:09.35#ibcon#about to read 4, iclass 17, count 0 2006.201.03:45:09.35#ibcon#read 4, iclass 17, count 0 2006.201.03:45:09.35#ibcon#about to read 5, iclass 17, count 0 2006.201.03:45:09.35#ibcon#read 5, iclass 17, count 0 2006.201.03:45:09.35#ibcon#about to read 6, iclass 17, count 0 2006.201.03:45:09.35#ibcon#read 6, iclass 17, count 0 2006.201.03:45:09.35#ibcon#end of sib2, iclass 17, count 0 2006.201.03:45:09.35#ibcon#*after write, iclass 17, count 0 2006.201.03:45:09.35#ibcon#*before return 0, iclass 17, count 0 2006.201.03:45:09.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:09.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.03:45:09.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.03:45:09.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.03:45:09.35$vck44/vbbw=wide 2006.201.03:45:09.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.03:45:09.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.03:45:09.35#ibcon#ireg 8 cls_cnt 0 2006.201.03:45:09.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:45:09.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:45:09.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:45:09.42#ibcon#enter wrdev, iclass 19, count 0 2006.201.03:45:09.42#ibcon#first serial, iclass 19, count 0 2006.201.03:45:09.42#ibcon#enter sib2, iclass 19, count 0 2006.201.03:45:09.42#ibcon#flushed, iclass 19, count 0 2006.201.03:45:09.42#ibcon#about to write, iclass 19, count 0 2006.201.03:45:09.42#ibcon#wrote, iclass 19, count 0 2006.201.03:45:09.42#ibcon#about to read 3, iclass 19, count 0 2006.201.03:45:09.44#ibcon#read 3, iclass 19, count 0 2006.201.03:45:09.44#ibcon#about to read 4, iclass 19, count 0 2006.201.03:45:09.44#ibcon#read 4, iclass 19, count 0 2006.201.03:45:09.44#ibcon#about to read 5, iclass 19, count 0 2006.201.03:45:09.44#ibcon#read 5, iclass 19, count 0 2006.201.03:45:09.44#ibcon#about to read 6, iclass 19, count 0 2006.201.03:45:09.44#ibcon#read 6, iclass 19, count 0 2006.201.03:45:09.44#ibcon#end of sib2, iclass 19, count 0 2006.201.03:45:09.44#ibcon#*mode == 0, iclass 19, count 0 2006.201.03:45:09.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.03:45:09.44#ibcon#[27=BW32\r\n] 2006.201.03:45:09.44#ibcon#*before write, iclass 19, count 0 2006.201.03:45:09.44#ibcon#enter sib2, iclass 19, count 0 2006.201.03:45:09.44#ibcon#flushed, iclass 19, count 0 2006.201.03:45:09.44#ibcon#about to write, iclass 19, count 0 2006.201.03:45:09.44#ibcon#wrote, iclass 19, count 0 2006.201.03:45:09.44#ibcon#about to read 3, iclass 19, count 0 2006.201.03:45:09.47#ibcon#read 3, iclass 19, count 0 2006.201.03:45:09.47#ibcon#about to read 4, iclass 19, count 0 2006.201.03:45:09.47#ibcon#read 4, iclass 19, count 0 2006.201.03:45:09.47#ibcon#about to read 5, iclass 19, count 0 2006.201.03:45:09.47#ibcon#read 5, iclass 19, count 0 2006.201.03:45:09.47#ibcon#about to read 6, iclass 19, count 0 2006.201.03:45:09.47#ibcon#read 6, iclass 19, count 0 2006.201.03:45:09.47#ibcon#end of sib2, iclass 19, count 0 2006.201.03:45:09.47#ibcon#*after write, iclass 19, count 0 2006.201.03:45:09.47#ibcon#*before return 0, iclass 19, count 0 2006.201.03:45:09.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:45:09.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:45:09.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.03:45:09.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.03:45:09.47$setupk4/ifdk4 2006.201.03:45:09.47$ifdk4/lo= 2006.201.03:45:09.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:45:09.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:45:09.47$ifdk4/patch= 2006.201.03:45:09.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:45:09.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:45:09.47$setupk4/!*+20s 2006.201.03:45:09.84#abcon#<5=/03 1.8 3.6 23.01 911004.5\r\n> 2006.201.03:45:09.86#abcon#{5=INTERFACE CLEAR} 2006.201.03:45:09.92#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:45:18.14#trakl#Source acquired 2006.201.03:45:20.01#abcon#<5=/03 1.8 3.6 23.01 921004.5\r\n> 2006.201.03:45:20.03#abcon#{5=INTERFACE CLEAR} 2006.201.03:45:20.09#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:45:20.14#flagr#flagr/antenna,acquired 2006.201.03:45:23.95$setupk4/"tpicd 2006.201.03:45:23.95$setupk4/echo=off 2006.201.03:45:23.95$setupk4/xlog=off 2006.201.03:45:23.95:!2006.201.03:47:01 2006.201.03:47:01.00:preob 2006.201.03:47:01.14/onsource/TRACKING 2006.201.03:47:01.14:!2006.201.03:47:11 2006.201.03:47:11.00:"tape 2006.201.03:47:11.00:"st=record 2006.201.03:47:11.00:data_valid=on 2006.201.03:47:11.00:midob 2006.201.03:47:11.13/onsource/TRACKING 2006.201.03:47:11.13/wx/23.00,1004.5,92 2006.201.03:47:11.23/cable/+6.4681E-03 2006.201.03:47:12.32/va/01,08,usb,yes,29,31 2006.201.03:47:12.32/va/02,07,usb,yes,31,32 2006.201.03:47:12.32/va/03,08,usb,yes,28,29 2006.201.03:47:12.32/va/04,07,usb,yes,32,34 2006.201.03:47:12.32/va/05,04,usb,yes,28,29 2006.201.03:47:12.32/va/06,05,usb,yes,28,28 2006.201.03:47:12.32/va/07,05,usb,yes,27,29 2006.201.03:47:12.32/va/08,04,usb,yes,27,33 2006.201.03:47:12.55/valo/01,524.99,yes,locked 2006.201.03:47:12.55/valo/02,534.99,yes,locked 2006.201.03:47:12.55/valo/03,564.99,yes,locked 2006.201.03:47:12.55/valo/04,624.99,yes,locked 2006.201.03:47:12.55/valo/05,734.99,yes,locked 2006.201.03:47:12.55/valo/06,814.99,yes,locked 2006.201.03:47:12.55/valo/07,864.99,yes,locked 2006.201.03:47:12.55/valo/08,884.99,yes,locked 2006.201.03:47:13.64/vb/01,04,usb,yes,29,27 2006.201.03:47:13.64/vb/02,05,usb,yes,27,27 2006.201.03:47:13.64/vb/03,04,usb,yes,28,31 2006.201.03:47:13.64/vb/04,05,usb,yes,28,27 2006.201.03:47:13.64/vb/05,04,usb,yes,25,27 2006.201.03:47:13.64/vb/06,04,usb,yes,29,26 2006.201.03:47:13.64/vb/07,04,usb,yes,29,29 2006.201.03:47:13.64/vb/08,04,usb,yes,27,30 2006.201.03:47:13.88/vblo/01,629.99,yes,locked 2006.201.03:47:13.88/vblo/02,634.99,yes,locked 2006.201.03:47:13.88/vblo/03,649.99,yes,locked 2006.201.03:47:13.88/vblo/04,679.99,yes,locked 2006.201.03:47:13.88/vblo/05,709.99,yes,locked 2006.201.03:47:13.88/vblo/06,719.99,yes,locked 2006.201.03:47:13.88/vblo/07,734.99,yes,locked 2006.201.03:47:13.88/vblo/08,744.99,yes,locked 2006.201.03:47:14.03/vabw/8 2006.201.03:47:14.18/vbbw/8 2006.201.03:47:14.27/xfe/off,on,16.2 2006.201.03:47:14.65/ifatt/23,28,28,28 2006.201.03:47:15.05/fmout-gps/S +4.53E-07 2006.201.03:47:15.12:!2006.201.03:48:41 2006.201.03:48:41.00:data_valid=off 2006.201.03:48:41.00:"et 2006.201.03:48:41.00:!+3s 2006.201.03:48:44.02:"tape 2006.201.03:48:44.02:postob 2006.201.03:48:44.23/cable/+6.4679E-03 2006.201.03:48:44.23/wx/22.99,1004.4,91 2006.201.03:48:44.29/fmout-gps/S +4.55E-07 2006.201.03:48:44.29:scan_name=201-0351,jd0607,60 2006.201.03:48:44.29:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.201.03:48:45.13#flagr#flagr/antenna,new-source 2006.201.03:48:45.13:checkk5 2006.201.03:48:45.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:48:45.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:48:46.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:48:46.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:48:47.01/chk_obsdata//k5ts1/T2010347??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.03:48:47.38/chk_obsdata//k5ts2/T2010347??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.03:48:47.74/chk_obsdata//k5ts3/T2010347??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.03:48:48.11/chk_obsdata//k5ts4/T2010347??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.03:48:48.80/k5log//k5ts1_log_newline 2006.201.03:48:49.50/k5log//k5ts2_log_newline 2006.201.03:48:50.18/k5log//k5ts3_log_newline 2006.201.03:48:50.87/k5log//k5ts4_log_newline 2006.201.03:48:50.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:48:50.90:setupk4=1 2006.201.03:48:50.90$setupk4/echo=on 2006.201.03:48:50.90$setupk4/pcalon 2006.201.03:48:50.90$pcalon/"no phase cal control is implemented here 2006.201.03:48:50.90$setupk4/"tpicd=stop 2006.201.03:48:50.90$setupk4/"rec=synch_on 2006.201.03:48:50.90$setupk4/"rec_mode=128 2006.201.03:48:50.90$setupk4/!* 2006.201.03:48:50.90$setupk4/recpk4 2006.201.03:48:50.90$recpk4/recpatch= 2006.201.03:48:50.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:48:50.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:48:50.90$setupk4/vck44 2006.201.03:48:50.90$vck44/valo=1,524.99 2006.201.03:48:50.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.03:48:50.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.03:48:50.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:50.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:48:50.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:48:50.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:48:50.90#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:48:50.90#ibcon#first serial, iclass 40, count 0 2006.201.03:48:50.90#ibcon#enter sib2, iclass 40, count 0 2006.201.03:48:50.90#ibcon#flushed, iclass 40, count 0 2006.201.03:48:50.90#ibcon#about to write, iclass 40, count 0 2006.201.03:48:50.90#ibcon#wrote, iclass 40, count 0 2006.201.03:48:50.90#ibcon#about to read 3, iclass 40, count 0 2006.201.03:48:50.92#ibcon#read 3, iclass 40, count 0 2006.201.03:48:50.92#ibcon#about to read 4, iclass 40, count 0 2006.201.03:48:50.92#ibcon#read 4, iclass 40, count 0 2006.201.03:48:50.92#ibcon#about to read 5, iclass 40, count 0 2006.201.03:48:50.92#ibcon#read 5, iclass 40, count 0 2006.201.03:48:50.92#ibcon#about to read 6, iclass 40, count 0 2006.201.03:48:50.92#ibcon#read 6, iclass 40, count 0 2006.201.03:48:50.92#ibcon#end of sib2, iclass 40, count 0 2006.201.03:48:50.92#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:48:50.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:48:50.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:48:50.92#ibcon#*before write, iclass 40, count 0 2006.201.03:48:50.92#ibcon#enter sib2, iclass 40, count 0 2006.201.03:48:50.92#ibcon#flushed, iclass 40, count 0 2006.201.03:48:50.92#ibcon#about to write, iclass 40, count 0 2006.201.03:48:50.92#ibcon#wrote, iclass 40, count 0 2006.201.03:48:50.92#ibcon#about to read 3, iclass 40, count 0 2006.201.03:48:50.97#ibcon#read 3, iclass 40, count 0 2006.201.03:48:50.97#ibcon#about to read 4, iclass 40, count 0 2006.201.03:48:50.97#ibcon#read 4, iclass 40, count 0 2006.201.03:48:50.97#ibcon#about to read 5, iclass 40, count 0 2006.201.03:48:50.97#ibcon#read 5, iclass 40, count 0 2006.201.03:48:50.97#ibcon#about to read 6, iclass 40, count 0 2006.201.03:48:50.97#ibcon#read 6, iclass 40, count 0 2006.201.03:48:50.97#ibcon#end of sib2, iclass 40, count 0 2006.201.03:48:50.97#ibcon#*after write, iclass 40, count 0 2006.201.03:48:50.97#ibcon#*before return 0, iclass 40, count 0 2006.201.03:48:50.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:48:50.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.03:48:50.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:48:50.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:48:50.97$vck44/va=1,8 2006.201.03:48:50.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.03:48:50.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.03:48:50.97#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:50.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:48:50.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:48:50.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:48:50.97#ibcon#enter wrdev, iclass 4, count 2 2006.201.03:48:50.97#ibcon#first serial, iclass 4, count 2 2006.201.03:48:50.97#ibcon#enter sib2, iclass 4, count 2 2006.201.03:48:50.97#ibcon#flushed, iclass 4, count 2 2006.201.03:48:50.97#ibcon#about to write, iclass 4, count 2 2006.201.03:48:50.97#ibcon#wrote, iclass 4, count 2 2006.201.03:48:50.97#ibcon#about to read 3, iclass 4, count 2 2006.201.03:48:50.99#ibcon#read 3, iclass 4, count 2 2006.201.03:48:50.99#ibcon#about to read 4, iclass 4, count 2 2006.201.03:48:50.99#ibcon#read 4, iclass 4, count 2 2006.201.03:48:50.99#ibcon#about to read 5, iclass 4, count 2 2006.201.03:48:50.99#ibcon#read 5, iclass 4, count 2 2006.201.03:48:50.99#ibcon#about to read 6, iclass 4, count 2 2006.201.03:48:50.99#ibcon#read 6, iclass 4, count 2 2006.201.03:48:50.99#ibcon#end of sib2, iclass 4, count 2 2006.201.03:48:50.99#ibcon#*mode == 0, iclass 4, count 2 2006.201.03:48:50.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.03:48:50.99#ibcon#[25=AT01-08\r\n] 2006.201.03:48:50.99#ibcon#*before write, iclass 4, count 2 2006.201.03:48:50.99#ibcon#enter sib2, iclass 4, count 2 2006.201.03:48:50.99#ibcon#flushed, iclass 4, count 2 2006.201.03:48:50.99#ibcon#about to write, iclass 4, count 2 2006.201.03:48:50.99#ibcon#wrote, iclass 4, count 2 2006.201.03:48:50.99#ibcon#about to read 3, iclass 4, count 2 2006.201.03:48:51.02#ibcon#read 3, iclass 4, count 2 2006.201.03:48:51.02#ibcon#about to read 4, iclass 4, count 2 2006.201.03:48:51.02#ibcon#read 4, iclass 4, count 2 2006.201.03:48:51.02#ibcon#about to read 5, iclass 4, count 2 2006.201.03:48:51.02#ibcon#read 5, iclass 4, count 2 2006.201.03:48:51.02#ibcon#about to read 6, iclass 4, count 2 2006.201.03:48:51.02#ibcon#read 6, iclass 4, count 2 2006.201.03:48:51.02#ibcon#end of sib2, iclass 4, count 2 2006.201.03:48:51.02#ibcon#*after write, iclass 4, count 2 2006.201.03:48:51.02#ibcon#*before return 0, iclass 4, count 2 2006.201.03:48:51.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:48:51.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.03:48:51.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.03:48:51.02#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:51.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:48:51.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:48:51.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:48:51.14#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:48:51.14#ibcon#first serial, iclass 4, count 0 2006.201.03:48:51.14#ibcon#enter sib2, iclass 4, count 0 2006.201.03:48:51.14#ibcon#flushed, iclass 4, count 0 2006.201.03:48:51.14#ibcon#about to write, iclass 4, count 0 2006.201.03:48:51.14#ibcon#wrote, iclass 4, count 0 2006.201.03:48:51.14#ibcon#about to read 3, iclass 4, count 0 2006.201.03:48:51.16#ibcon#read 3, iclass 4, count 0 2006.201.03:48:51.16#ibcon#about to read 4, iclass 4, count 0 2006.201.03:48:51.16#ibcon#read 4, iclass 4, count 0 2006.201.03:48:51.16#ibcon#about to read 5, iclass 4, count 0 2006.201.03:48:51.16#ibcon#read 5, iclass 4, count 0 2006.201.03:48:51.16#ibcon#about to read 6, iclass 4, count 0 2006.201.03:48:51.16#ibcon#read 6, iclass 4, count 0 2006.201.03:48:51.16#ibcon#end of sib2, iclass 4, count 0 2006.201.03:48:51.16#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:48:51.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:48:51.16#ibcon#[25=USB\r\n] 2006.201.03:48:51.16#ibcon#*before write, iclass 4, count 0 2006.201.03:48:51.16#ibcon#enter sib2, iclass 4, count 0 2006.201.03:48:51.16#ibcon#flushed, iclass 4, count 0 2006.201.03:48:51.16#ibcon#about to write, iclass 4, count 0 2006.201.03:48:51.16#ibcon#wrote, iclass 4, count 0 2006.201.03:48:51.16#ibcon#about to read 3, iclass 4, count 0 2006.201.03:48:51.19#ibcon#read 3, iclass 4, count 0 2006.201.03:48:51.19#ibcon#about to read 4, iclass 4, count 0 2006.201.03:48:51.19#ibcon#read 4, iclass 4, count 0 2006.201.03:48:51.19#ibcon#about to read 5, iclass 4, count 0 2006.201.03:48:51.19#ibcon#read 5, iclass 4, count 0 2006.201.03:48:51.19#ibcon#about to read 6, iclass 4, count 0 2006.201.03:48:51.19#ibcon#read 6, iclass 4, count 0 2006.201.03:48:51.19#ibcon#end of sib2, iclass 4, count 0 2006.201.03:48:51.19#ibcon#*after write, iclass 4, count 0 2006.201.03:48:51.19#ibcon#*before return 0, iclass 4, count 0 2006.201.03:48:51.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:48:51.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.03:48:51.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:48:51.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:48:51.19$vck44/valo=2,534.99 2006.201.03:48:51.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.03:48:51.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.03:48:51.19#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:51.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:51.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:51.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:51.19#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:48:51.19#ibcon#first serial, iclass 6, count 0 2006.201.03:48:51.19#ibcon#enter sib2, iclass 6, count 0 2006.201.03:48:51.19#ibcon#flushed, iclass 6, count 0 2006.201.03:48:51.19#ibcon#about to write, iclass 6, count 0 2006.201.03:48:51.19#ibcon#wrote, iclass 6, count 0 2006.201.03:48:51.19#ibcon#about to read 3, iclass 6, count 0 2006.201.03:48:51.21#ibcon#read 3, iclass 6, count 0 2006.201.03:48:51.21#ibcon#about to read 4, iclass 6, count 0 2006.201.03:48:51.21#ibcon#read 4, iclass 6, count 0 2006.201.03:48:51.21#ibcon#about to read 5, iclass 6, count 0 2006.201.03:48:51.21#ibcon#read 5, iclass 6, count 0 2006.201.03:48:51.21#ibcon#about to read 6, iclass 6, count 0 2006.201.03:48:51.21#ibcon#read 6, iclass 6, count 0 2006.201.03:48:51.21#ibcon#end of sib2, iclass 6, count 0 2006.201.03:48:51.21#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:48:51.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:48:51.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:48:51.21#ibcon#*before write, iclass 6, count 0 2006.201.03:48:51.21#ibcon#enter sib2, iclass 6, count 0 2006.201.03:48:51.21#ibcon#flushed, iclass 6, count 0 2006.201.03:48:51.21#ibcon#about to write, iclass 6, count 0 2006.201.03:48:51.21#ibcon#wrote, iclass 6, count 0 2006.201.03:48:51.21#ibcon#about to read 3, iclass 6, count 0 2006.201.03:48:51.26#ibcon#read 3, iclass 6, count 0 2006.201.03:48:51.26#ibcon#about to read 4, iclass 6, count 0 2006.201.03:48:51.26#ibcon#read 4, iclass 6, count 0 2006.201.03:48:51.26#ibcon#about to read 5, iclass 6, count 0 2006.201.03:48:51.26#ibcon#read 5, iclass 6, count 0 2006.201.03:48:51.26#ibcon#about to read 6, iclass 6, count 0 2006.201.03:48:51.26#ibcon#read 6, iclass 6, count 0 2006.201.03:48:51.26#ibcon#end of sib2, iclass 6, count 0 2006.201.03:48:51.26#ibcon#*after write, iclass 6, count 0 2006.201.03:48:51.26#ibcon#*before return 0, iclass 6, count 0 2006.201.03:48:51.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:51.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:51.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:48:51.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:48:51.26$vck44/va=2,7 2006.201.03:48:51.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.03:48:51.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.03:48:51.26#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:51.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:51.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:51.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:51.31#ibcon#enter wrdev, iclass 10, count 2 2006.201.03:48:51.31#ibcon#first serial, iclass 10, count 2 2006.201.03:48:51.31#ibcon#enter sib2, iclass 10, count 2 2006.201.03:48:51.31#ibcon#flushed, iclass 10, count 2 2006.201.03:48:51.31#ibcon#about to write, iclass 10, count 2 2006.201.03:48:51.31#ibcon#wrote, iclass 10, count 2 2006.201.03:48:51.31#ibcon#about to read 3, iclass 10, count 2 2006.201.03:48:51.33#ibcon#read 3, iclass 10, count 2 2006.201.03:48:51.33#ibcon#about to read 4, iclass 10, count 2 2006.201.03:48:51.33#ibcon#read 4, iclass 10, count 2 2006.201.03:48:51.33#ibcon#about to read 5, iclass 10, count 2 2006.201.03:48:51.33#ibcon#read 5, iclass 10, count 2 2006.201.03:48:51.33#ibcon#about to read 6, iclass 10, count 2 2006.201.03:48:51.33#ibcon#read 6, iclass 10, count 2 2006.201.03:48:51.33#ibcon#end of sib2, iclass 10, count 2 2006.201.03:48:51.33#ibcon#*mode == 0, iclass 10, count 2 2006.201.03:48:51.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.03:48:51.33#ibcon#[25=AT02-07\r\n] 2006.201.03:48:51.33#ibcon#*before write, iclass 10, count 2 2006.201.03:48:51.33#ibcon#enter sib2, iclass 10, count 2 2006.201.03:48:51.33#ibcon#flushed, iclass 10, count 2 2006.201.03:48:51.33#ibcon#about to write, iclass 10, count 2 2006.201.03:48:51.33#ibcon#wrote, iclass 10, count 2 2006.201.03:48:51.33#ibcon#about to read 3, iclass 10, count 2 2006.201.03:48:51.36#ibcon#read 3, iclass 10, count 2 2006.201.03:48:51.36#ibcon#about to read 4, iclass 10, count 2 2006.201.03:48:51.36#ibcon#read 4, iclass 10, count 2 2006.201.03:48:51.36#ibcon#about to read 5, iclass 10, count 2 2006.201.03:48:51.36#ibcon#read 5, iclass 10, count 2 2006.201.03:48:51.36#ibcon#about to read 6, iclass 10, count 2 2006.201.03:48:51.36#ibcon#read 6, iclass 10, count 2 2006.201.03:48:51.36#ibcon#end of sib2, iclass 10, count 2 2006.201.03:48:51.36#ibcon#*after write, iclass 10, count 2 2006.201.03:48:51.36#ibcon#*before return 0, iclass 10, count 2 2006.201.03:48:51.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:51.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:51.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.03:48:51.36#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:51.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:51.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:51.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:51.48#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:48:51.48#ibcon#first serial, iclass 10, count 0 2006.201.03:48:51.48#ibcon#enter sib2, iclass 10, count 0 2006.201.03:48:51.48#ibcon#flushed, iclass 10, count 0 2006.201.03:48:51.48#ibcon#about to write, iclass 10, count 0 2006.201.03:48:51.48#ibcon#wrote, iclass 10, count 0 2006.201.03:48:51.48#ibcon#about to read 3, iclass 10, count 0 2006.201.03:48:51.50#ibcon#read 3, iclass 10, count 0 2006.201.03:48:51.50#ibcon#about to read 4, iclass 10, count 0 2006.201.03:48:51.50#ibcon#read 4, iclass 10, count 0 2006.201.03:48:51.50#ibcon#about to read 5, iclass 10, count 0 2006.201.03:48:51.50#ibcon#read 5, iclass 10, count 0 2006.201.03:48:51.50#ibcon#about to read 6, iclass 10, count 0 2006.201.03:48:51.50#ibcon#read 6, iclass 10, count 0 2006.201.03:48:51.50#ibcon#end of sib2, iclass 10, count 0 2006.201.03:48:51.50#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:48:51.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:48:51.50#ibcon#[25=USB\r\n] 2006.201.03:48:51.50#ibcon#*before write, iclass 10, count 0 2006.201.03:48:51.50#ibcon#enter sib2, iclass 10, count 0 2006.201.03:48:51.50#ibcon#flushed, iclass 10, count 0 2006.201.03:48:51.50#ibcon#about to write, iclass 10, count 0 2006.201.03:48:51.50#ibcon#wrote, iclass 10, count 0 2006.201.03:48:51.50#ibcon#about to read 3, iclass 10, count 0 2006.201.03:48:51.53#ibcon#read 3, iclass 10, count 0 2006.201.03:48:51.53#ibcon#about to read 4, iclass 10, count 0 2006.201.03:48:51.53#ibcon#read 4, iclass 10, count 0 2006.201.03:48:51.53#ibcon#about to read 5, iclass 10, count 0 2006.201.03:48:51.53#ibcon#read 5, iclass 10, count 0 2006.201.03:48:51.53#ibcon#about to read 6, iclass 10, count 0 2006.201.03:48:51.53#ibcon#read 6, iclass 10, count 0 2006.201.03:48:51.53#ibcon#end of sib2, iclass 10, count 0 2006.201.03:48:51.53#ibcon#*after write, iclass 10, count 0 2006.201.03:48:51.53#ibcon#*before return 0, iclass 10, count 0 2006.201.03:48:51.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:51.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:51.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:48:51.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:48:51.53$vck44/valo=3,564.99 2006.201.03:48:51.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.03:48:51.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.03:48:51.53#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:51.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:51.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:51.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:51.53#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:48:51.53#ibcon#first serial, iclass 12, count 0 2006.201.03:48:51.53#ibcon#enter sib2, iclass 12, count 0 2006.201.03:48:51.53#ibcon#flushed, iclass 12, count 0 2006.201.03:48:51.53#ibcon#about to write, iclass 12, count 0 2006.201.03:48:51.53#ibcon#wrote, iclass 12, count 0 2006.201.03:48:51.53#ibcon#about to read 3, iclass 12, count 0 2006.201.03:48:51.55#ibcon#read 3, iclass 12, count 0 2006.201.03:48:51.55#ibcon#about to read 4, iclass 12, count 0 2006.201.03:48:51.55#ibcon#read 4, iclass 12, count 0 2006.201.03:48:51.55#ibcon#about to read 5, iclass 12, count 0 2006.201.03:48:51.55#ibcon#read 5, iclass 12, count 0 2006.201.03:48:51.55#ibcon#about to read 6, iclass 12, count 0 2006.201.03:48:51.55#ibcon#read 6, iclass 12, count 0 2006.201.03:48:51.55#ibcon#end of sib2, iclass 12, count 0 2006.201.03:48:51.55#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:48:51.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:48:51.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:48:51.55#ibcon#*before write, iclass 12, count 0 2006.201.03:48:51.55#ibcon#enter sib2, iclass 12, count 0 2006.201.03:48:51.55#ibcon#flushed, iclass 12, count 0 2006.201.03:48:51.55#ibcon#about to write, iclass 12, count 0 2006.201.03:48:51.55#ibcon#wrote, iclass 12, count 0 2006.201.03:48:51.55#ibcon#about to read 3, iclass 12, count 0 2006.201.03:48:51.60#ibcon#read 3, iclass 12, count 0 2006.201.03:48:51.60#ibcon#about to read 4, iclass 12, count 0 2006.201.03:48:51.60#ibcon#read 4, iclass 12, count 0 2006.201.03:48:51.60#ibcon#about to read 5, iclass 12, count 0 2006.201.03:48:51.60#ibcon#read 5, iclass 12, count 0 2006.201.03:48:51.60#ibcon#about to read 6, iclass 12, count 0 2006.201.03:48:51.60#ibcon#read 6, iclass 12, count 0 2006.201.03:48:51.60#ibcon#end of sib2, iclass 12, count 0 2006.201.03:48:51.60#ibcon#*after write, iclass 12, count 0 2006.201.03:48:51.60#ibcon#*before return 0, iclass 12, count 0 2006.201.03:48:51.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:51.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:51.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:48:51.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:48:51.60$vck44/va=3,8 2006.201.03:48:51.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.03:48:51.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.03:48:51.60#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:51.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:51.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:51.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:51.65#ibcon#enter wrdev, iclass 14, count 2 2006.201.03:48:51.65#ibcon#first serial, iclass 14, count 2 2006.201.03:48:51.65#ibcon#enter sib2, iclass 14, count 2 2006.201.03:48:51.65#ibcon#flushed, iclass 14, count 2 2006.201.03:48:51.65#ibcon#about to write, iclass 14, count 2 2006.201.03:48:51.65#ibcon#wrote, iclass 14, count 2 2006.201.03:48:51.65#ibcon#about to read 3, iclass 14, count 2 2006.201.03:48:51.67#ibcon#read 3, iclass 14, count 2 2006.201.03:48:51.67#ibcon#about to read 4, iclass 14, count 2 2006.201.03:48:51.67#ibcon#read 4, iclass 14, count 2 2006.201.03:48:51.67#ibcon#about to read 5, iclass 14, count 2 2006.201.03:48:51.67#ibcon#read 5, iclass 14, count 2 2006.201.03:48:51.67#ibcon#about to read 6, iclass 14, count 2 2006.201.03:48:51.67#ibcon#read 6, iclass 14, count 2 2006.201.03:48:51.67#ibcon#end of sib2, iclass 14, count 2 2006.201.03:48:51.67#ibcon#*mode == 0, iclass 14, count 2 2006.201.03:48:51.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.03:48:51.67#ibcon#[25=AT03-08\r\n] 2006.201.03:48:51.67#ibcon#*before write, iclass 14, count 2 2006.201.03:48:51.67#ibcon#enter sib2, iclass 14, count 2 2006.201.03:48:51.67#ibcon#flushed, iclass 14, count 2 2006.201.03:48:51.67#ibcon#about to write, iclass 14, count 2 2006.201.03:48:51.67#ibcon#wrote, iclass 14, count 2 2006.201.03:48:51.67#ibcon#about to read 3, iclass 14, count 2 2006.201.03:48:51.70#ibcon#read 3, iclass 14, count 2 2006.201.03:48:51.70#ibcon#about to read 4, iclass 14, count 2 2006.201.03:48:51.70#ibcon#read 4, iclass 14, count 2 2006.201.03:48:51.70#ibcon#about to read 5, iclass 14, count 2 2006.201.03:48:51.70#ibcon#read 5, iclass 14, count 2 2006.201.03:48:51.70#ibcon#about to read 6, iclass 14, count 2 2006.201.03:48:51.70#ibcon#read 6, iclass 14, count 2 2006.201.03:48:51.70#ibcon#end of sib2, iclass 14, count 2 2006.201.03:48:51.70#ibcon#*after write, iclass 14, count 2 2006.201.03:48:51.70#ibcon#*before return 0, iclass 14, count 2 2006.201.03:48:51.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:51.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:51.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.03:48:51.70#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:51.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:51.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:51.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:51.82#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:48:51.82#ibcon#first serial, iclass 14, count 0 2006.201.03:48:51.82#ibcon#enter sib2, iclass 14, count 0 2006.201.03:48:51.82#ibcon#flushed, iclass 14, count 0 2006.201.03:48:51.82#ibcon#about to write, iclass 14, count 0 2006.201.03:48:51.82#ibcon#wrote, iclass 14, count 0 2006.201.03:48:51.82#ibcon#about to read 3, iclass 14, count 0 2006.201.03:48:51.84#ibcon#read 3, iclass 14, count 0 2006.201.03:48:51.84#ibcon#about to read 4, iclass 14, count 0 2006.201.03:48:51.84#ibcon#read 4, iclass 14, count 0 2006.201.03:48:51.84#ibcon#about to read 5, iclass 14, count 0 2006.201.03:48:51.84#ibcon#read 5, iclass 14, count 0 2006.201.03:48:51.84#ibcon#about to read 6, iclass 14, count 0 2006.201.03:48:51.84#ibcon#read 6, iclass 14, count 0 2006.201.03:48:51.84#ibcon#end of sib2, iclass 14, count 0 2006.201.03:48:51.84#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:48:51.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:48:51.84#ibcon#[25=USB\r\n] 2006.201.03:48:51.84#ibcon#*before write, iclass 14, count 0 2006.201.03:48:51.84#ibcon#enter sib2, iclass 14, count 0 2006.201.03:48:51.84#ibcon#flushed, iclass 14, count 0 2006.201.03:48:51.84#ibcon#about to write, iclass 14, count 0 2006.201.03:48:51.84#ibcon#wrote, iclass 14, count 0 2006.201.03:48:51.84#ibcon#about to read 3, iclass 14, count 0 2006.201.03:48:51.87#ibcon#read 3, iclass 14, count 0 2006.201.03:48:51.87#ibcon#about to read 4, iclass 14, count 0 2006.201.03:48:51.87#ibcon#read 4, iclass 14, count 0 2006.201.03:48:51.87#ibcon#about to read 5, iclass 14, count 0 2006.201.03:48:51.87#ibcon#read 5, iclass 14, count 0 2006.201.03:48:51.87#ibcon#about to read 6, iclass 14, count 0 2006.201.03:48:51.87#ibcon#read 6, iclass 14, count 0 2006.201.03:48:51.87#ibcon#end of sib2, iclass 14, count 0 2006.201.03:48:51.87#ibcon#*after write, iclass 14, count 0 2006.201.03:48:51.87#ibcon#*before return 0, iclass 14, count 0 2006.201.03:48:51.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:51.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:51.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:48:51.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:48:51.87$vck44/valo=4,624.99 2006.201.03:48:51.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.03:48:51.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.03:48:51.87#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:51.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:51.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:51.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:51.87#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:48:51.87#ibcon#first serial, iclass 16, count 0 2006.201.03:48:51.87#ibcon#enter sib2, iclass 16, count 0 2006.201.03:48:51.87#ibcon#flushed, iclass 16, count 0 2006.201.03:48:51.87#ibcon#about to write, iclass 16, count 0 2006.201.03:48:51.87#ibcon#wrote, iclass 16, count 0 2006.201.03:48:51.87#ibcon#about to read 3, iclass 16, count 0 2006.201.03:48:51.89#ibcon#read 3, iclass 16, count 0 2006.201.03:48:51.89#ibcon#about to read 4, iclass 16, count 0 2006.201.03:48:51.89#ibcon#read 4, iclass 16, count 0 2006.201.03:48:51.89#ibcon#about to read 5, iclass 16, count 0 2006.201.03:48:51.89#ibcon#read 5, iclass 16, count 0 2006.201.03:48:51.89#ibcon#about to read 6, iclass 16, count 0 2006.201.03:48:51.89#ibcon#read 6, iclass 16, count 0 2006.201.03:48:51.89#ibcon#end of sib2, iclass 16, count 0 2006.201.03:48:51.89#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:48:51.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:48:51.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:48:51.89#ibcon#*before write, iclass 16, count 0 2006.201.03:48:51.89#ibcon#enter sib2, iclass 16, count 0 2006.201.03:48:51.89#ibcon#flushed, iclass 16, count 0 2006.201.03:48:51.89#ibcon#about to write, iclass 16, count 0 2006.201.03:48:51.89#ibcon#wrote, iclass 16, count 0 2006.201.03:48:51.89#ibcon#about to read 3, iclass 16, count 0 2006.201.03:48:51.93#ibcon#read 3, iclass 16, count 0 2006.201.03:48:51.93#ibcon#about to read 4, iclass 16, count 0 2006.201.03:48:51.93#ibcon#read 4, iclass 16, count 0 2006.201.03:48:51.93#ibcon#about to read 5, iclass 16, count 0 2006.201.03:48:51.93#ibcon#read 5, iclass 16, count 0 2006.201.03:48:51.93#ibcon#about to read 6, iclass 16, count 0 2006.201.03:48:51.93#ibcon#read 6, iclass 16, count 0 2006.201.03:48:51.93#ibcon#end of sib2, iclass 16, count 0 2006.201.03:48:51.93#ibcon#*after write, iclass 16, count 0 2006.201.03:48:51.93#ibcon#*before return 0, iclass 16, count 0 2006.201.03:48:51.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:51.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:51.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:48:51.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:48:51.93$vck44/va=4,7 2006.201.03:48:51.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.03:48:51.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.03:48:51.93#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:51.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:51.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:51.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:51.99#ibcon#enter wrdev, iclass 18, count 2 2006.201.03:48:51.99#ibcon#first serial, iclass 18, count 2 2006.201.03:48:51.99#ibcon#enter sib2, iclass 18, count 2 2006.201.03:48:51.99#ibcon#flushed, iclass 18, count 2 2006.201.03:48:51.99#ibcon#about to write, iclass 18, count 2 2006.201.03:48:51.99#ibcon#wrote, iclass 18, count 2 2006.201.03:48:51.99#ibcon#about to read 3, iclass 18, count 2 2006.201.03:48:52.01#ibcon#read 3, iclass 18, count 2 2006.201.03:48:52.01#ibcon#about to read 4, iclass 18, count 2 2006.201.03:48:52.01#ibcon#read 4, iclass 18, count 2 2006.201.03:48:52.01#ibcon#about to read 5, iclass 18, count 2 2006.201.03:48:52.01#ibcon#read 5, iclass 18, count 2 2006.201.03:48:52.01#ibcon#about to read 6, iclass 18, count 2 2006.201.03:48:52.01#ibcon#read 6, iclass 18, count 2 2006.201.03:48:52.01#ibcon#end of sib2, iclass 18, count 2 2006.201.03:48:52.01#ibcon#*mode == 0, iclass 18, count 2 2006.201.03:48:52.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.03:48:52.01#ibcon#[25=AT04-07\r\n] 2006.201.03:48:52.01#ibcon#*before write, iclass 18, count 2 2006.201.03:48:52.01#ibcon#enter sib2, iclass 18, count 2 2006.201.03:48:52.01#ibcon#flushed, iclass 18, count 2 2006.201.03:48:52.01#ibcon#about to write, iclass 18, count 2 2006.201.03:48:52.01#ibcon#wrote, iclass 18, count 2 2006.201.03:48:52.01#ibcon#about to read 3, iclass 18, count 2 2006.201.03:48:52.04#ibcon#read 3, iclass 18, count 2 2006.201.03:48:52.04#ibcon#about to read 4, iclass 18, count 2 2006.201.03:48:52.04#ibcon#read 4, iclass 18, count 2 2006.201.03:48:52.04#ibcon#about to read 5, iclass 18, count 2 2006.201.03:48:52.04#ibcon#read 5, iclass 18, count 2 2006.201.03:48:52.04#ibcon#about to read 6, iclass 18, count 2 2006.201.03:48:52.04#ibcon#read 6, iclass 18, count 2 2006.201.03:48:52.04#ibcon#end of sib2, iclass 18, count 2 2006.201.03:48:52.04#ibcon#*after write, iclass 18, count 2 2006.201.03:48:52.04#ibcon#*before return 0, iclass 18, count 2 2006.201.03:48:52.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:52.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:52.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.03:48:52.04#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:52.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:52.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:52.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:52.16#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:48:52.16#ibcon#first serial, iclass 18, count 0 2006.201.03:48:52.16#ibcon#enter sib2, iclass 18, count 0 2006.201.03:48:52.16#ibcon#flushed, iclass 18, count 0 2006.201.03:48:52.16#ibcon#about to write, iclass 18, count 0 2006.201.03:48:52.16#ibcon#wrote, iclass 18, count 0 2006.201.03:48:52.16#ibcon#about to read 3, iclass 18, count 0 2006.201.03:48:52.18#ibcon#read 3, iclass 18, count 0 2006.201.03:48:52.18#ibcon#about to read 4, iclass 18, count 0 2006.201.03:48:52.18#ibcon#read 4, iclass 18, count 0 2006.201.03:48:52.18#ibcon#about to read 5, iclass 18, count 0 2006.201.03:48:52.18#ibcon#read 5, iclass 18, count 0 2006.201.03:48:52.18#ibcon#about to read 6, iclass 18, count 0 2006.201.03:48:52.18#ibcon#read 6, iclass 18, count 0 2006.201.03:48:52.18#ibcon#end of sib2, iclass 18, count 0 2006.201.03:48:52.18#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:48:52.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:48:52.18#ibcon#[25=USB\r\n] 2006.201.03:48:52.18#ibcon#*before write, iclass 18, count 0 2006.201.03:48:52.18#ibcon#enter sib2, iclass 18, count 0 2006.201.03:48:52.18#ibcon#flushed, iclass 18, count 0 2006.201.03:48:52.18#ibcon#about to write, iclass 18, count 0 2006.201.03:48:52.18#ibcon#wrote, iclass 18, count 0 2006.201.03:48:52.18#ibcon#about to read 3, iclass 18, count 0 2006.201.03:48:52.21#ibcon#read 3, iclass 18, count 0 2006.201.03:48:52.21#ibcon#about to read 4, iclass 18, count 0 2006.201.03:48:52.21#ibcon#read 4, iclass 18, count 0 2006.201.03:48:52.21#ibcon#about to read 5, iclass 18, count 0 2006.201.03:48:52.21#ibcon#read 5, iclass 18, count 0 2006.201.03:48:52.21#ibcon#about to read 6, iclass 18, count 0 2006.201.03:48:52.21#ibcon#read 6, iclass 18, count 0 2006.201.03:48:52.21#ibcon#end of sib2, iclass 18, count 0 2006.201.03:48:52.21#ibcon#*after write, iclass 18, count 0 2006.201.03:48:52.21#ibcon#*before return 0, iclass 18, count 0 2006.201.03:48:52.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:52.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:52.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:48:52.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:48:52.21$vck44/valo=5,734.99 2006.201.03:48:52.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.03:48:52.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.03:48:52.21#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:52.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:52.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:52.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:52.21#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:48:52.21#ibcon#first serial, iclass 20, count 0 2006.201.03:48:52.21#ibcon#enter sib2, iclass 20, count 0 2006.201.03:48:52.21#ibcon#flushed, iclass 20, count 0 2006.201.03:48:52.21#ibcon#about to write, iclass 20, count 0 2006.201.03:48:52.21#ibcon#wrote, iclass 20, count 0 2006.201.03:48:52.21#ibcon#about to read 3, iclass 20, count 0 2006.201.03:48:52.23#ibcon#read 3, iclass 20, count 0 2006.201.03:48:52.23#ibcon#about to read 4, iclass 20, count 0 2006.201.03:48:52.23#ibcon#read 4, iclass 20, count 0 2006.201.03:48:52.23#ibcon#about to read 5, iclass 20, count 0 2006.201.03:48:52.23#ibcon#read 5, iclass 20, count 0 2006.201.03:48:52.23#ibcon#about to read 6, iclass 20, count 0 2006.201.03:48:52.23#ibcon#read 6, iclass 20, count 0 2006.201.03:48:52.23#ibcon#end of sib2, iclass 20, count 0 2006.201.03:48:52.23#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:48:52.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:48:52.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:48:52.23#ibcon#*before write, iclass 20, count 0 2006.201.03:48:52.23#ibcon#enter sib2, iclass 20, count 0 2006.201.03:48:52.23#ibcon#flushed, iclass 20, count 0 2006.201.03:48:52.23#ibcon#about to write, iclass 20, count 0 2006.201.03:48:52.23#ibcon#wrote, iclass 20, count 0 2006.201.03:48:52.23#ibcon#about to read 3, iclass 20, count 0 2006.201.03:48:52.27#ibcon#read 3, iclass 20, count 0 2006.201.03:48:52.27#ibcon#about to read 4, iclass 20, count 0 2006.201.03:48:52.27#ibcon#read 4, iclass 20, count 0 2006.201.03:48:52.27#ibcon#about to read 5, iclass 20, count 0 2006.201.03:48:52.27#ibcon#read 5, iclass 20, count 0 2006.201.03:48:52.27#ibcon#about to read 6, iclass 20, count 0 2006.201.03:48:52.27#ibcon#read 6, iclass 20, count 0 2006.201.03:48:52.27#ibcon#end of sib2, iclass 20, count 0 2006.201.03:48:52.27#ibcon#*after write, iclass 20, count 0 2006.201.03:48:52.27#ibcon#*before return 0, iclass 20, count 0 2006.201.03:48:52.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:52.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:52.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:48:52.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:48:52.27$vck44/va=5,4 2006.201.03:48:52.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.03:48:52.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.03:48:52.27#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:52.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:52.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:52.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:52.33#ibcon#enter wrdev, iclass 22, count 2 2006.201.03:48:52.33#ibcon#first serial, iclass 22, count 2 2006.201.03:48:52.33#ibcon#enter sib2, iclass 22, count 2 2006.201.03:48:52.33#ibcon#flushed, iclass 22, count 2 2006.201.03:48:52.33#ibcon#about to write, iclass 22, count 2 2006.201.03:48:52.33#ibcon#wrote, iclass 22, count 2 2006.201.03:48:52.33#ibcon#about to read 3, iclass 22, count 2 2006.201.03:48:52.35#ibcon#read 3, iclass 22, count 2 2006.201.03:48:52.35#ibcon#about to read 4, iclass 22, count 2 2006.201.03:48:52.35#ibcon#read 4, iclass 22, count 2 2006.201.03:48:52.35#ibcon#about to read 5, iclass 22, count 2 2006.201.03:48:52.35#ibcon#read 5, iclass 22, count 2 2006.201.03:48:52.35#ibcon#about to read 6, iclass 22, count 2 2006.201.03:48:52.35#ibcon#read 6, iclass 22, count 2 2006.201.03:48:52.35#ibcon#end of sib2, iclass 22, count 2 2006.201.03:48:52.35#ibcon#*mode == 0, iclass 22, count 2 2006.201.03:48:52.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.03:48:52.35#ibcon#[25=AT05-04\r\n] 2006.201.03:48:52.35#ibcon#*before write, iclass 22, count 2 2006.201.03:48:52.35#ibcon#enter sib2, iclass 22, count 2 2006.201.03:48:52.35#ibcon#flushed, iclass 22, count 2 2006.201.03:48:52.35#ibcon#about to write, iclass 22, count 2 2006.201.03:48:52.35#ibcon#wrote, iclass 22, count 2 2006.201.03:48:52.35#ibcon#about to read 3, iclass 22, count 2 2006.201.03:48:52.38#ibcon#read 3, iclass 22, count 2 2006.201.03:48:52.38#ibcon#about to read 4, iclass 22, count 2 2006.201.03:48:52.38#ibcon#read 4, iclass 22, count 2 2006.201.03:48:52.38#ibcon#about to read 5, iclass 22, count 2 2006.201.03:48:52.38#ibcon#read 5, iclass 22, count 2 2006.201.03:48:52.38#ibcon#about to read 6, iclass 22, count 2 2006.201.03:48:52.38#ibcon#read 6, iclass 22, count 2 2006.201.03:48:52.38#ibcon#end of sib2, iclass 22, count 2 2006.201.03:48:52.38#ibcon#*after write, iclass 22, count 2 2006.201.03:48:52.38#ibcon#*before return 0, iclass 22, count 2 2006.201.03:48:52.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:52.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:52.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.03:48:52.38#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:52.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:52.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:52.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:52.50#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:48:52.50#ibcon#first serial, iclass 22, count 0 2006.201.03:48:52.50#ibcon#enter sib2, iclass 22, count 0 2006.201.03:48:52.50#ibcon#flushed, iclass 22, count 0 2006.201.03:48:52.50#ibcon#about to write, iclass 22, count 0 2006.201.03:48:52.50#ibcon#wrote, iclass 22, count 0 2006.201.03:48:52.50#ibcon#about to read 3, iclass 22, count 0 2006.201.03:48:52.52#ibcon#read 3, iclass 22, count 0 2006.201.03:48:52.52#ibcon#about to read 4, iclass 22, count 0 2006.201.03:48:52.52#ibcon#read 4, iclass 22, count 0 2006.201.03:48:52.52#ibcon#about to read 5, iclass 22, count 0 2006.201.03:48:52.52#ibcon#read 5, iclass 22, count 0 2006.201.03:48:52.52#ibcon#about to read 6, iclass 22, count 0 2006.201.03:48:52.52#ibcon#read 6, iclass 22, count 0 2006.201.03:48:52.52#ibcon#end of sib2, iclass 22, count 0 2006.201.03:48:52.52#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:48:52.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:48:52.52#ibcon#[25=USB\r\n] 2006.201.03:48:52.52#ibcon#*before write, iclass 22, count 0 2006.201.03:48:52.52#ibcon#enter sib2, iclass 22, count 0 2006.201.03:48:52.52#ibcon#flushed, iclass 22, count 0 2006.201.03:48:52.52#ibcon#about to write, iclass 22, count 0 2006.201.03:48:52.52#ibcon#wrote, iclass 22, count 0 2006.201.03:48:52.52#ibcon#about to read 3, iclass 22, count 0 2006.201.03:48:52.55#ibcon#read 3, iclass 22, count 0 2006.201.03:48:52.55#ibcon#about to read 4, iclass 22, count 0 2006.201.03:48:52.55#ibcon#read 4, iclass 22, count 0 2006.201.03:48:52.55#ibcon#about to read 5, iclass 22, count 0 2006.201.03:48:52.55#ibcon#read 5, iclass 22, count 0 2006.201.03:48:52.55#ibcon#about to read 6, iclass 22, count 0 2006.201.03:48:52.55#ibcon#read 6, iclass 22, count 0 2006.201.03:48:52.55#ibcon#end of sib2, iclass 22, count 0 2006.201.03:48:52.55#ibcon#*after write, iclass 22, count 0 2006.201.03:48:52.55#ibcon#*before return 0, iclass 22, count 0 2006.201.03:48:52.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:52.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:52.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:48:52.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:48:52.55$vck44/valo=6,814.99 2006.201.03:48:52.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.03:48:52.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.03:48:52.55#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:52.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:52.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:52.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:52.55#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:48:52.55#ibcon#first serial, iclass 24, count 0 2006.201.03:48:52.55#ibcon#enter sib2, iclass 24, count 0 2006.201.03:48:52.55#ibcon#flushed, iclass 24, count 0 2006.201.03:48:52.55#ibcon#about to write, iclass 24, count 0 2006.201.03:48:52.55#ibcon#wrote, iclass 24, count 0 2006.201.03:48:52.55#ibcon#about to read 3, iclass 24, count 0 2006.201.03:48:52.57#ibcon#read 3, iclass 24, count 0 2006.201.03:48:52.57#ibcon#about to read 4, iclass 24, count 0 2006.201.03:48:52.57#ibcon#read 4, iclass 24, count 0 2006.201.03:48:52.57#ibcon#about to read 5, iclass 24, count 0 2006.201.03:48:52.57#ibcon#read 5, iclass 24, count 0 2006.201.03:48:52.57#ibcon#about to read 6, iclass 24, count 0 2006.201.03:48:52.57#ibcon#read 6, iclass 24, count 0 2006.201.03:48:52.57#ibcon#end of sib2, iclass 24, count 0 2006.201.03:48:52.57#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:48:52.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:48:52.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:48:52.57#ibcon#*before write, iclass 24, count 0 2006.201.03:48:52.57#ibcon#enter sib2, iclass 24, count 0 2006.201.03:48:52.57#ibcon#flushed, iclass 24, count 0 2006.201.03:48:52.57#ibcon#about to write, iclass 24, count 0 2006.201.03:48:52.57#ibcon#wrote, iclass 24, count 0 2006.201.03:48:52.57#ibcon#about to read 3, iclass 24, count 0 2006.201.03:48:52.61#ibcon#read 3, iclass 24, count 0 2006.201.03:48:52.61#ibcon#about to read 4, iclass 24, count 0 2006.201.03:48:52.61#ibcon#read 4, iclass 24, count 0 2006.201.03:48:52.61#ibcon#about to read 5, iclass 24, count 0 2006.201.03:48:52.61#ibcon#read 5, iclass 24, count 0 2006.201.03:48:52.61#ibcon#about to read 6, iclass 24, count 0 2006.201.03:48:52.61#ibcon#read 6, iclass 24, count 0 2006.201.03:48:52.61#ibcon#end of sib2, iclass 24, count 0 2006.201.03:48:52.61#ibcon#*after write, iclass 24, count 0 2006.201.03:48:52.61#ibcon#*before return 0, iclass 24, count 0 2006.201.03:48:52.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:52.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:52.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:48:52.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:48:52.61$vck44/va=6,5 2006.201.03:48:52.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.03:48:52.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.03:48:52.61#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:52.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:52.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:52.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:52.67#ibcon#enter wrdev, iclass 26, count 2 2006.201.03:48:52.67#ibcon#first serial, iclass 26, count 2 2006.201.03:48:52.67#ibcon#enter sib2, iclass 26, count 2 2006.201.03:48:52.67#ibcon#flushed, iclass 26, count 2 2006.201.03:48:52.67#ibcon#about to write, iclass 26, count 2 2006.201.03:48:52.67#ibcon#wrote, iclass 26, count 2 2006.201.03:48:52.67#ibcon#about to read 3, iclass 26, count 2 2006.201.03:48:52.69#ibcon#read 3, iclass 26, count 2 2006.201.03:48:52.69#ibcon#about to read 4, iclass 26, count 2 2006.201.03:48:52.69#ibcon#read 4, iclass 26, count 2 2006.201.03:48:52.69#ibcon#about to read 5, iclass 26, count 2 2006.201.03:48:52.69#ibcon#read 5, iclass 26, count 2 2006.201.03:48:52.69#ibcon#about to read 6, iclass 26, count 2 2006.201.03:48:52.69#ibcon#read 6, iclass 26, count 2 2006.201.03:48:52.69#ibcon#end of sib2, iclass 26, count 2 2006.201.03:48:52.69#ibcon#*mode == 0, iclass 26, count 2 2006.201.03:48:52.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.03:48:52.69#ibcon#[25=AT06-05\r\n] 2006.201.03:48:52.69#ibcon#*before write, iclass 26, count 2 2006.201.03:48:52.69#ibcon#enter sib2, iclass 26, count 2 2006.201.03:48:52.69#ibcon#flushed, iclass 26, count 2 2006.201.03:48:52.69#ibcon#about to write, iclass 26, count 2 2006.201.03:48:52.69#ibcon#wrote, iclass 26, count 2 2006.201.03:48:52.69#ibcon#about to read 3, iclass 26, count 2 2006.201.03:48:52.72#ibcon#read 3, iclass 26, count 2 2006.201.03:48:52.72#ibcon#about to read 4, iclass 26, count 2 2006.201.03:48:52.72#ibcon#read 4, iclass 26, count 2 2006.201.03:48:52.72#ibcon#about to read 5, iclass 26, count 2 2006.201.03:48:52.72#ibcon#read 5, iclass 26, count 2 2006.201.03:48:52.72#ibcon#about to read 6, iclass 26, count 2 2006.201.03:48:52.72#ibcon#read 6, iclass 26, count 2 2006.201.03:48:52.72#ibcon#end of sib2, iclass 26, count 2 2006.201.03:48:52.72#ibcon#*after write, iclass 26, count 2 2006.201.03:48:52.72#ibcon#*before return 0, iclass 26, count 2 2006.201.03:48:52.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:52.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:52.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.03:48:52.72#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:52.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:52.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:52.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:52.84#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:48:52.84#ibcon#first serial, iclass 26, count 0 2006.201.03:48:52.84#ibcon#enter sib2, iclass 26, count 0 2006.201.03:48:52.84#ibcon#flushed, iclass 26, count 0 2006.201.03:48:52.84#ibcon#about to write, iclass 26, count 0 2006.201.03:48:52.84#ibcon#wrote, iclass 26, count 0 2006.201.03:48:52.84#ibcon#about to read 3, iclass 26, count 0 2006.201.03:48:52.86#ibcon#read 3, iclass 26, count 0 2006.201.03:48:52.86#ibcon#about to read 4, iclass 26, count 0 2006.201.03:48:52.86#ibcon#read 4, iclass 26, count 0 2006.201.03:48:52.86#ibcon#about to read 5, iclass 26, count 0 2006.201.03:48:52.86#ibcon#read 5, iclass 26, count 0 2006.201.03:48:52.86#ibcon#about to read 6, iclass 26, count 0 2006.201.03:48:52.86#ibcon#read 6, iclass 26, count 0 2006.201.03:48:52.86#ibcon#end of sib2, iclass 26, count 0 2006.201.03:48:52.86#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:48:52.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:48:52.86#ibcon#[25=USB\r\n] 2006.201.03:48:52.86#ibcon#*before write, iclass 26, count 0 2006.201.03:48:52.86#ibcon#enter sib2, iclass 26, count 0 2006.201.03:48:52.86#ibcon#flushed, iclass 26, count 0 2006.201.03:48:52.86#ibcon#about to write, iclass 26, count 0 2006.201.03:48:52.86#ibcon#wrote, iclass 26, count 0 2006.201.03:48:52.86#ibcon#about to read 3, iclass 26, count 0 2006.201.03:48:52.89#ibcon#read 3, iclass 26, count 0 2006.201.03:48:52.89#ibcon#about to read 4, iclass 26, count 0 2006.201.03:48:52.89#ibcon#read 4, iclass 26, count 0 2006.201.03:48:52.89#ibcon#about to read 5, iclass 26, count 0 2006.201.03:48:52.89#ibcon#read 5, iclass 26, count 0 2006.201.03:48:52.89#ibcon#about to read 6, iclass 26, count 0 2006.201.03:48:52.89#ibcon#read 6, iclass 26, count 0 2006.201.03:48:52.89#ibcon#end of sib2, iclass 26, count 0 2006.201.03:48:52.89#ibcon#*after write, iclass 26, count 0 2006.201.03:48:52.89#ibcon#*before return 0, iclass 26, count 0 2006.201.03:48:52.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:52.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:52.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:48:52.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:48:52.89$vck44/valo=7,864.99 2006.201.03:48:52.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.03:48:52.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.03:48:52.89#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:52.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:52.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:52.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:52.89#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:48:52.89#ibcon#first serial, iclass 28, count 0 2006.201.03:48:52.89#ibcon#enter sib2, iclass 28, count 0 2006.201.03:48:52.89#ibcon#flushed, iclass 28, count 0 2006.201.03:48:52.89#ibcon#about to write, iclass 28, count 0 2006.201.03:48:52.89#ibcon#wrote, iclass 28, count 0 2006.201.03:48:52.89#ibcon#about to read 3, iclass 28, count 0 2006.201.03:48:52.91#ibcon#read 3, iclass 28, count 0 2006.201.03:48:52.91#ibcon#about to read 4, iclass 28, count 0 2006.201.03:48:52.91#ibcon#read 4, iclass 28, count 0 2006.201.03:48:52.91#ibcon#about to read 5, iclass 28, count 0 2006.201.03:48:52.91#ibcon#read 5, iclass 28, count 0 2006.201.03:48:52.91#ibcon#about to read 6, iclass 28, count 0 2006.201.03:48:52.91#ibcon#read 6, iclass 28, count 0 2006.201.03:48:52.91#ibcon#end of sib2, iclass 28, count 0 2006.201.03:48:52.91#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:48:52.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:48:52.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:48:52.91#ibcon#*before write, iclass 28, count 0 2006.201.03:48:52.91#ibcon#enter sib2, iclass 28, count 0 2006.201.03:48:52.91#ibcon#flushed, iclass 28, count 0 2006.201.03:48:52.91#ibcon#about to write, iclass 28, count 0 2006.201.03:48:52.91#ibcon#wrote, iclass 28, count 0 2006.201.03:48:52.91#ibcon#about to read 3, iclass 28, count 0 2006.201.03:48:52.95#ibcon#read 3, iclass 28, count 0 2006.201.03:48:52.95#ibcon#about to read 4, iclass 28, count 0 2006.201.03:48:52.95#ibcon#read 4, iclass 28, count 0 2006.201.03:48:52.95#ibcon#about to read 5, iclass 28, count 0 2006.201.03:48:52.95#ibcon#read 5, iclass 28, count 0 2006.201.03:48:52.95#ibcon#about to read 6, iclass 28, count 0 2006.201.03:48:52.95#ibcon#read 6, iclass 28, count 0 2006.201.03:48:52.95#ibcon#end of sib2, iclass 28, count 0 2006.201.03:48:52.95#ibcon#*after write, iclass 28, count 0 2006.201.03:48:52.95#ibcon#*before return 0, iclass 28, count 0 2006.201.03:48:52.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:52.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:52.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:48:52.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:48:52.95$vck44/va=7,5 2006.201.03:48:52.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.03:48:52.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.03:48:52.95#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:52.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:53.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:53.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:53.01#ibcon#enter wrdev, iclass 30, count 2 2006.201.03:48:53.01#ibcon#first serial, iclass 30, count 2 2006.201.03:48:53.01#ibcon#enter sib2, iclass 30, count 2 2006.201.03:48:53.01#ibcon#flushed, iclass 30, count 2 2006.201.03:48:53.01#ibcon#about to write, iclass 30, count 2 2006.201.03:48:53.01#ibcon#wrote, iclass 30, count 2 2006.201.03:48:53.01#ibcon#about to read 3, iclass 30, count 2 2006.201.03:48:53.03#ibcon#read 3, iclass 30, count 2 2006.201.03:48:53.03#ibcon#about to read 4, iclass 30, count 2 2006.201.03:48:53.03#ibcon#read 4, iclass 30, count 2 2006.201.03:48:53.03#ibcon#about to read 5, iclass 30, count 2 2006.201.03:48:53.03#ibcon#read 5, iclass 30, count 2 2006.201.03:48:53.03#ibcon#about to read 6, iclass 30, count 2 2006.201.03:48:53.03#ibcon#read 6, iclass 30, count 2 2006.201.03:48:53.03#ibcon#end of sib2, iclass 30, count 2 2006.201.03:48:53.03#ibcon#*mode == 0, iclass 30, count 2 2006.201.03:48:53.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.03:48:53.03#ibcon#[25=AT07-05\r\n] 2006.201.03:48:53.03#ibcon#*before write, iclass 30, count 2 2006.201.03:48:53.03#ibcon#enter sib2, iclass 30, count 2 2006.201.03:48:53.03#ibcon#flushed, iclass 30, count 2 2006.201.03:48:53.03#ibcon#about to write, iclass 30, count 2 2006.201.03:48:53.03#ibcon#wrote, iclass 30, count 2 2006.201.03:48:53.03#ibcon#about to read 3, iclass 30, count 2 2006.201.03:48:53.06#ibcon#read 3, iclass 30, count 2 2006.201.03:48:53.06#ibcon#about to read 4, iclass 30, count 2 2006.201.03:48:53.06#ibcon#read 4, iclass 30, count 2 2006.201.03:48:53.06#ibcon#about to read 5, iclass 30, count 2 2006.201.03:48:53.06#ibcon#read 5, iclass 30, count 2 2006.201.03:48:53.06#ibcon#about to read 6, iclass 30, count 2 2006.201.03:48:53.06#ibcon#read 6, iclass 30, count 2 2006.201.03:48:53.06#ibcon#end of sib2, iclass 30, count 2 2006.201.03:48:53.06#ibcon#*after write, iclass 30, count 2 2006.201.03:48:53.06#ibcon#*before return 0, iclass 30, count 2 2006.201.03:48:53.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:53.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:53.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.03:48:53.06#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:53.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:53.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:53.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:53.18#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:48:53.18#ibcon#first serial, iclass 30, count 0 2006.201.03:48:53.18#ibcon#enter sib2, iclass 30, count 0 2006.201.03:48:53.18#ibcon#flushed, iclass 30, count 0 2006.201.03:48:53.18#ibcon#about to write, iclass 30, count 0 2006.201.03:48:53.18#ibcon#wrote, iclass 30, count 0 2006.201.03:48:53.18#ibcon#about to read 3, iclass 30, count 0 2006.201.03:48:53.21#ibcon#read 3, iclass 30, count 0 2006.201.03:48:53.21#ibcon#about to read 4, iclass 30, count 0 2006.201.03:48:53.21#ibcon#read 4, iclass 30, count 0 2006.201.03:48:53.21#ibcon#about to read 5, iclass 30, count 0 2006.201.03:48:53.21#ibcon#read 5, iclass 30, count 0 2006.201.03:48:53.21#ibcon#about to read 6, iclass 30, count 0 2006.201.03:48:53.21#ibcon#read 6, iclass 30, count 0 2006.201.03:48:53.21#ibcon#end of sib2, iclass 30, count 0 2006.201.03:48:53.21#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:48:53.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:48:53.21#ibcon#[25=USB\r\n] 2006.201.03:48:53.21#ibcon#*before write, iclass 30, count 0 2006.201.03:48:53.21#ibcon#enter sib2, iclass 30, count 0 2006.201.03:48:53.21#ibcon#flushed, iclass 30, count 0 2006.201.03:48:53.21#ibcon#about to write, iclass 30, count 0 2006.201.03:48:53.21#ibcon#wrote, iclass 30, count 0 2006.201.03:48:53.21#ibcon#about to read 3, iclass 30, count 0 2006.201.03:48:53.24#ibcon#read 3, iclass 30, count 0 2006.201.03:48:53.24#ibcon#about to read 4, iclass 30, count 0 2006.201.03:48:53.24#ibcon#read 4, iclass 30, count 0 2006.201.03:48:53.24#ibcon#about to read 5, iclass 30, count 0 2006.201.03:48:53.24#ibcon#read 5, iclass 30, count 0 2006.201.03:48:53.24#ibcon#about to read 6, iclass 30, count 0 2006.201.03:48:53.24#ibcon#read 6, iclass 30, count 0 2006.201.03:48:53.24#ibcon#end of sib2, iclass 30, count 0 2006.201.03:48:53.24#ibcon#*after write, iclass 30, count 0 2006.201.03:48:53.24#ibcon#*before return 0, iclass 30, count 0 2006.201.03:48:53.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:53.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:53.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:48:53.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:48:53.24$vck44/valo=8,884.99 2006.201.03:48:53.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.03:48:53.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.03:48:53.24#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:53.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:53.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:53.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:53.24#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:48:53.24#ibcon#first serial, iclass 32, count 0 2006.201.03:48:53.24#ibcon#enter sib2, iclass 32, count 0 2006.201.03:48:53.24#ibcon#flushed, iclass 32, count 0 2006.201.03:48:53.24#ibcon#about to write, iclass 32, count 0 2006.201.03:48:53.24#ibcon#wrote, iclass 32, count 0 2006.201.03:48:53.24#ibcon#about to read 3, iclass 32, count 0 2006.201.03:48:53.26#ibcon#read 3, iclass 32, count 0 2006.201.03:48:53.26#ibcon#about to read 4, iclass 32, count 0 2006.201.03:48:53.26#ibcon#read 4, iclass 32, count 0 2006.201.03:48:53.26#ibcon#about to read 5, iclass 32, count 0 2006.201.03:48:53.26#ibcon#read 5, iclass 32, count 0 2006.201.03:48:53.26#ibcon#about to read 6, iclass 32, count 0 2006.201.03:48:53.26#ibcon#read 6, iclass 32, count 0 2006.201.03:48:53.26#ibcon#end of sib2, iclass 32, count 0 2006.201.03:48:53.26#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:48:53.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:48:53.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:48:53.26#ibcon#*before write, iclass 32, count 0 2006.201.03:48:53.26#ibcon#enter sib2, iclass 32, count 0 2006.201.03:48:53.26#ibcon#flushed, iclass 32, count 0 2006.201.03:48:53.26#ibcon#about to write, iclass 32, count 0 2006.201.03:48:53.26#ibcon#wrote, iclass 32, count 0 2006.201.03:48:53.26#ibcon#about to read 3, iclass 32, count 0 2006.201.03:48:53.30#ibcon#read 3, iclass 32, count 0 2006.201.03:48:53.30#ibcon#about to read 4, iclass 32, count 0 2006.201.03:48:53.30#ibcon#read 4, iclass 32, count 0 2006.201.03:48:53.30#ibcon#about to read 5, iclass 32, count 0 2006.201.03:48:53.30#ibcon#read 5, iclass 32, count 0 2006.201.03:48:53.30#ibcon#about to read 6, iclass 32, count 0 2006.201.03:48:53.30#ibcon#read 6, iclass 32, count 0 2006.201.03:48:53.30#ibcon#end of sib2, iclass 32, count 0 2006.201.03:48:53.30#ibcon#*after write, iclass 32, count 0 2006.201.03:48:53.30#ibcon#*before return 0, iclass 32, count 0 2006.201.03:48:53.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:53.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:53.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:48:53.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:48:53.30$vck44/va=8,4 2006.201.03:48:53.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.03:48:53.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.03:48:53.30#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:53.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:53.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:53.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:53.36#ibcon#enter wrdev, iclass 34, count 2 2006.201.03:48:53.36#ibcon#first serial, iclass 34, count 2 2006.201.03:48:53.36#ibcon#enter sib2, iclass 34, count 2 2006.201.03:48:53.36#ibcon#flushed, iclass 34, count 2 2006.201.03:48:53.36#ibcon#about to write, iclass 34, count 2 2006.201.03:48:53.36#ibcon#wrote, iclass 34, count 2 2006.201.03:48:53.36#ibcon#about to read 3, iclass 34, count 2 2006.201.03:48:53.38#ibcon#read 3, iclass 34, count 2 2006.201.03:48:53.38#ibcon#about to read 4, iclass 34, count 2 2006.201.03:48:53.38#ibcon#read 4, iclass 34, count 2 2006.201.03:48:53.38#ibcon#about to read 5, iclass 34, count 2 2006.201.03:48:53.38#ibcon#read 5, iclass 34, count 2 2006.201.03:48:53.38#ibcon#about to read 6, iclass 34, count 2 2006.201.03:48:53.38#ibcon#read 6, iclass 34, count 2 2006.201.03:48:53.38#ibcon#end of sib2, iclass 34, count 2 2006.201.03:48:53.38#ibcon#*mode == 0, iclass 34, count 2 2006.201.03:48:53.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.03:48:53.38#ibcon#[25=AT08-04\r\n] 2006.201.03:48:53.38#ibcon#*before write, iclass 34, count 2 2006.201.03:48:53.38#ibcon#enter sib2, iclass 34, count 2 2006.201.03:48:53.38#ibcon#flushed, iclass 34, count 2 2006.201.03:48:53.38#ibcon#about to write, iclass 34, count 2 2006.201.03:48:53.38#ibcon#wrote, iclass 34, count 2 2006.201.03:48:53.38#ibcon#about to read 3, iclass 34, count 2 2006.201.03:48:53.41#ibcon#read 3, iclass 34, count 2 2006.201.03:48:53.41#ibcon#about to read 4, iclass 34, count 2 2006.201.03:48:53.41#ibcon#read 4, iclass 34, count 2 2006.201.03:48:53.41#ibcon#about to read 5, iclass 34, count 2 2006.201.03:48:53.41#ibcon#read 5, iclass 34, count 2 2006.201.03:48:53.41#ibcon#about to read 6, iclass 34, count 2 2006.201.03:48:53.41#ibcon#read 6, iclass 34, count 2 2006.201.03:48:53.41#ibcon#end of sib2, iclass 34, count 2 2006.201.03:48:53.41#ibcon#*after write, iclass 34, count 2 2006.201.03:48:53.41#ibcon#*before return 0, iclass 34, count 2 2006.201.03:48:53.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:53.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:53.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.03:48:53.41#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:53.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:53.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:53.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:53.53#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:48:53.53#ibcon#first serial, iclass 34, count 0 2006.201.03:48:53.53#ibcon#enter sib2, iclass 34, count 0 2006.201.03:48:53.53#ibcon#flushed, iclass 34, count 0 2006.201.03:48:53.53#ibcon#about to write, iclass 34, count 0 2006.201.03:48:53.53#ibcon#wrote, iclass 34, count 0 2006.201.03:48:53.53#ibcon#about to read 3, iclass 34, count 0 2006.201.03:48:53.55#ibcon#read 3, iclass 34, count 0 2006.201.03:48:53.55#ibcon#about to read 4, iclass 34, count 0 2006.201.03:48:53.55#ibcon#read 4, iclass 34, count 0 2006.201.03:48:53.55#ibcon#about to read 5, iclass 34, count 0 2006.201.03:48:53.55#ibcon#read 5, iclass 34, count 0 2006.201.03:48:53.55#ibcon#about to read 6, iclass 34, count 0 2006.201.03:48:53.55#ibcon#read 6, iclass 34, count 0 2006.201.03:48:53.55#ibcon#end of sib2, iclass 34, count 0 2006.201.03:48:53.55#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:48:53.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:48:53.55#ibcon#[25=USB\r\n] 2006.201.03:48:53.55#ibcon#*before write, iclass 34, count 0 2006.201.03:48:53.55#ibcon#enter sib2, iclass 34, count 0 2006.201.03:48:53.55#ibcon#flushed, iclass 34, count 0 2006.201.03:48:53.55#ibcon#about to write, iclass 34, count 0 2006.201.03:48:53.55#ibcon#wrote, iclass 34, count 0 2006.201.03:48:53.55#ibcon#about to read 3, iclass 34, count 0 2006.201.03:48:53.58#abcon#<5=/03 1.8 3.6 22.99 911004.4\r\n> 2006.201.03:48:53.58#ibcon#read 3, iclass 34, count 0 2006.201.03:48:53.58#ibcon#about to read 4, iclass 34, count 0 2006.201.03:48:53.58#ibcon#read 4, iclass 34, count 0 2006.201.03:48:53.58#ibcon#about to read 5, iclass 34, count 0 2006.201.03:48:53.58#ibcon#read 5, iclass 34, count 0 2006.201.03:48:53.58#ibcon#about to read 6, iclass 34, count 0 2006.201.03:48:53.58#ibcon#read 6, iclass 34, count 0 2006.201.03:48:53.58#ibcon#end of sib2, iclass 34, count 0 2006.201.03:48:53.58#ibcon#*after write, iclass 34, count 0 2006.201.03:48:53.58#ibcon#*before return 0, iclass 34, count 0 2006.201.03:48:53.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:53.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:53.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:48:53.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:48:53.58$vck44/vblo=1,629.99 2006.201.03:48:53.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.03:48:53.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.03:48:53.58#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:53.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:48:53.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:48:53.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:48:53.58#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:48:53.58#ibcon#first serial, iclass 39, count 0 2006.201.03:48:53.58#ibcon#enter sib2, iclass 39, count 0 2006.201.03:48:53.58#ibcon#flushed, iclass 39, count 0 2006.201.03:48:53.58#ibcon#about to write, iclass 39, count 0 2006.201.03:48:53.58#ibcon#wrote, iclass 39, count 0 2006.201.03:48:53.58#ibcon#about to read 3, iclass 39, count 0 2006.201.03:48:53.60#abcon#{5=INTERFACE CLEAR} 2006.201.03:48:53.60#ibcon#read 3, iclass 39, count 0 2006.201.03:48:53.60#ibcon#about to read 4, iclass 39, count 0 2006.201.03:48:53.60#ibcon#read 4, iclass 39, count 0 2006.201.03:48:53.60#ibcon#about to read 5, iclass 39, count 0 2006.201.03:48:53.60#ibcon#read 5, iclass 39, count 0 2006.201.03:48:53.60#ibcon#about to read 6, iclass 39, count 0 2006.201.03:48:53.60#ibcon#read 6, iclass 39, count 0 2006.201.03:48:53.60#ibcon#end of sib2, iclass 39, count 0 2006.201.03:48:53.60#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:48:53.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:48:53.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:48:53.60#ibcon#*before write, iclass 39, count 0 2006.201.03:48:53.60#ibcon#enter sib2, iclass 39, count 0 2006.201.03:48:53.60#ibcon#flushed, iclass 39, count 0 2006.201.03:48:53.60#ibcon#about to write, iclass 39, count 0 2006.201.03:48:53.60#ibcon#wrote, iclass 39, count 0 2006.201.03:48:53.60#ibcon#about to read 3, iclass 39, count 0 2006.201.03:48:53.64#ibcon#read 3, iclass 39, count 0 2006.201.03:48:53.64#ibcon#about to read 4, iclass 39, count 0 2006.201.03:48:53.64#ibcon#read 4, iclass 39, count 0 2006.201.03:48:53.64#ibcon#about to read 5, iclass 39, count 0 2006.201.03:48:53.64#ibcon#read 5, iclass 39, count 0 2006.201.03:48:53.64#ibcon#about to read 6, iclass 39, count 0 2006.201.03:48:53.64#ibcon#read 6, iclass 39, count 0 2006.201.03:48:53.64#ibcon#end of sib2, iclass 39, count 0 2006.201.03:48:53.64#ibcon#*after write, iclass 39, count 0 2006.201.03:48:53.64#ibcon#*before return 0, iclass 39, count 0 2006.201.03:48:53.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:48:53.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:48:53.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:48:53.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:48:53.64$vck44/vb=1,4 2006.201.03:48:53.64#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.03:48:53.64#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.03:48:53.64#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:53.64#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:48:53.64#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:48:53.64#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:48:53.64#ibcon#enter wrdev, iclass 2, count 2 2006.201.03:48:53.64#ibcon#first serial, iclass 2, count 2 2006.201.03:48:53.64#ibcon#enter sib2, iclass 2, count 2 2006.201.03:48:53.64#ibcon#flushed, iclass 2, count 2 2006.201.03:48:53.64#ibcon#about to write, iclass 2, count 2 2006.201.03:48:53.64#ibcon#wrote, iclass 2, count 2 2006.201.03:48:53.64#ibcon#about to read 3, iclass 2, count 2 2006.201.03:48:53.66#ibcon#read 3, iclass 2, count 2 2006.201.03:48:53.66#ibcon#about to read 4, iclass 2, count 2 2006.201.03:48:53.66#ibcon#read 4, iclass 2, count 2 2006.201.03:48:53.66#ibcon#about to read 5, iclass 2, count 2 2006.201.03:48:53.66#ibcon#read 5, iclass 2, count 2 2006.201.03:48:53.66#ibcon#about to read 6, iclass 2, count 2 2006.201.03:48:53.66#ibcon#read 6, iclass 2, count 2 2006.201.03:48:53.66#ibcon#end of sib2, iclass 2, count 2 2006.201.03:48:53.66#ibcon#*mode == 0, iclass 2, count 2 2006.201.03:48:53.66#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.03:48:53.66#ibcon#[27=AT01-04\r\n] 2006.201.03:48:53.66#ibcon#*before write, iclass 2, count 2 2006.201.03:48:53.66#ibcon#enter sib2, iclass 2, count 2 2006.201.03:48:53.66#ibcon#flushed, iclass 2, count 2 2006.201.03:48:53.66#ibcon#about to write, iclass 2, count 2 2006.201.03:48:53.66#ibcon#wrote, iclass 2, count 2 2006.201.03:48:53.66#ibcon#about to read 3, iclass 2, count 2 2006.201.03:48:53.66#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:48:53.69#ibcon#read 3, iclass 2, count 2 2006.201.03:48:53.69#ibcon#about to read 4, iclass 2, count 2 2006.201.03:48:53.69#ibcon#read 4, iclass 2, count 2 2006.201.03:48:53.69#ibcon#about to read 5, iclass 2, count 2 2006.201.03:48:53.69#ibcon#read 5, iclass 2, count 2 2006.201.03:48:53.69#ibcon#about to read 6, iclass 2, count 2 2006.201.03:48:53.69#ibcon#read 6, iclass 2, count 2 2006.201.03:48:53.69#ibcon#end of sib2, iclass 2, count 2 2006.201.03:48:53.69#ibcon#*after write, iclass 2, count 2 2006.201.03:48:53.69#ibcon#*before return 0, iclass 2, count 2 2006.201.03:48:53.69#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:48:53.69#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:48:53.69#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.03:48:53.69#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:53.69#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:48:53.81#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:48:53.81#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:48:53.81#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:48:53.81#ibcon#first serial, iclass 2, count 0 2006.201.03:48:53.81#ibcon#enter sib2, iclass 2, count 0 2006.201.03:48:53.81#ibcon#flushed, iclass 2, count 0 2006.201.03:48:53.81#ibcon#about to write, iclass 2, count 0 2006.201.03:48:53.81#ibcon#wrote, iclass 2, count 0 2006.201.03:48:53.81#ibcon#about to read 3, iclass 2, count 0 2006.201.03:48:53.83#ibcon#read 3, iclass 2, count 0 2006.201.03:48:53.83#ibcon#about to read 4, iclass 2, count 0 2006.201.03:48:53.83#ibcon#read 4, iclass 2, count 0 2006.201.03:48:53.83#ibcon#about to read 5, iclass 2, count 0 2006.201.03:48:53.83#ibcon#read 5, iclass 2, count 0 2006.201.03:48:53.83#ibcon#about to read 6, iclass 2, count 0 2006.201.03:48:53.83#ibcon#read 6, iclass 2, count 0 2006.201.03:48:53.83#ibcon#end of sib2, iclass 2, count 0 2006.201.03:48:53.83#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:48:53.83#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:48:53.83#ibcon#[27=USB\r\n] 2006.201.03:48:53.83#ibcon#*before write, iclass 2, count 0 2006.201.03:48:53.83#ibcon#enter sib2, iclass 2, count 0 2006.201.03:48:53.83#ibcon#flushed, iclass 2, count 0 2006.201.03:48:53.83#ibcon#about to write, iclass 2, count 0 2006.201.03:48:53.83#ibcon#wrote, iclass 2, count 0 2006.201.03:48:53.83#ibcon#about to read 3, iclass 2, count 0 2006.201.03:48:53.86#ibcon#read 3, iclass 2, count 0 2006.201.03:48:53.86#ibcon#about to read 4, iclass 2, count 0 2006.201.03:48:53.86#ibcon#read 4, iclass 2, count 0 2006.201.03:48:53.86#ibcon#about to read 5, iclass 2, count 0 2006.201.03:48:53.86#ibcon#read 5, iclass 2, count 0 2006.201.03:48:53.86#ibcon#about to read 6, iclass 2, count 0 2006.201.03:48:53.86#ibcon#read 6, iclass 2, count 0 2006.201.03:48:53.86#ibcon#end of sib2, iclass 2, count 0 2006.201.03:48:53.86#ibcon#*after write, iclass 2, count 0 2006.201.03:48:53.86#ibcon#*before return 0, iclass 2, count 0 2006.201.03:48:53.86#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:48:53.86#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:48:53.86#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:48:53.86#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:48:53.86$vck44/vblo=2,634.99 2006.201.03:48:53.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.03:48:53.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.03:48:53.86#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:53.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:53.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:53.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:53.86#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:48:53.86#ibcon#first serial, iclass 6, count 0 2006.201.03:48:53.86#ibcon#enter sib2, iclass 6, count 0 2006.201.03:48:53.86#ibcon#flushed, iclass 6, count 0 2006.201.03:48:53.86#ibcon#about to write, iclass 6, count 0 2006.201.03:48:53.86#ibcon#wrote, iclass 6, count 0 2006.201.03:48:53.86#ibcon#about to read 3, iclass 6, count 0 2006.201.03:48:53.88#ibcon#read 3, iclass 6, count 0 2006.201.03:48:53.88#ibcon#about to read 4, iclass 6, count 0 2006.201.03:48:53.88#ibcon#read 4, iclass 6, count 0 2006.201.03:48:53.88#ibcon#about to read 5, iclass 6, count 0 2006.201.03:48:53.88#ibcon#read 5, iclass 6, count 0 2006.201.03:48:53.88#ibcon#about to read 6, iclass 6, count 0 2006.201.03:48:53.88#ibcon#read 6, iclass 6, count 0 2006.201.03:48:53.88#ibcon#end of sib2, iclass 6, count 0 2006.201.03:48:53.88#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:48:53.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:48:53.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:48:53.88#ibcon#*before write, iclass 6, count 0 2006.201.03:48:53.88#ibcon#enter sib2, iclass 6, count 0 2006.201.03:48:53.88#ibcon#flushed, iclass 6, count 0 2006.201.03:48:53.88#ibcon#about to write, iclass 6, count 0 2006.201.03:48:53.88#ibcon#wrote, iclass 6, count 0 2006.201.03:48:53.88#ibcon#about to read 3, iclass 6, count 0 2006.201.03:48:53.92#ibcon#read 3, iclass 6, count 0 2006.201.03:48:53.92#ibcon#about to read 4, iclass 6, count 0 2006.201.03:48:53.92#ibcon#read 4, iclass 6, count 0 2006.201.03:48:53.92#ibcon#about to read 5, iclass 6, count 0 2006.201.03:48:53.92#ibcon#read 5, iclass 6, count 0 2006.201.03:48:53.92#ibcon#about to read 6, iclass 6, count 0 2006.201.03:48:53.92#ibcon#read 6, iclass 6, count 0 2006.201.03:48:53.92#ibcon#end of sib2, iclass 6, count 0 2006.201.03:48:53.92#ibcon#*after write, iclass 6, count 0 2006.201.03:48:53.92#ibcon#*before return 0, iclass 6, count 0 2006.201.03:48:53.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:53.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.03:48:53.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:48:53.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:48:53.92$vck44/vb=2,5 2006.201.03:48:53.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.03:48:53.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.03:48:53.92#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:53.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:53.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:53.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:53.98#ibcon#enter wrdev, iclass 10, count 2 2006.201.03:48:53.98#ibcon#first serial, iclass 10, count 2 2006.201.03:48:53.98#ibcon#enter sib2, iclass 10, count 2 2006.201.03:48:53.98#ibcon#flushed, iclass 10, count 2 2006.201.03:48:53.98#ibcon#about to write, iclass 10, count 2 2006.201.03:48:53.98#ibcon#wrote, iclass 10, count 2 2006.201.03:48:53.98#ibcon#about to read 3, iclass 10, count 2 2006.201.03:48:54.00#ibcon#read 3, iclass 10, count 2 2006.201.03:48:54.00#ibcon#about to read 4, iclass 10, count 2 2006.201.03:48:54.00#ibcon#read 4, iclass 10, count 2 2006.201.03:48:54.00#ibcon#about to read 5, iclass 10, count 2 2006.201.03:48:54.00#ibcon#read 5, iclass 10, count 2 2006.201.03:48:54.00#ibcon#about to read 6, iclass 10, count 2 2006.201.03:48:54.00#ibcon#read 6, iclass 10, count 2 2006.201.03:48:54.00#ibcon#end of sib2, iclass 10, count 2 2006.201.03:48:54.00#ibcon#*mode == 0, iclass 10, count 2 2006.201.03:48:54.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.03:48:54.00#ibcon#[27=AT02-05\r\n] 2006.201.03:48:54.00#ibcon#*before write, iclass 10, count 2 2006.201.03:48:54.00#ibcon#enter sib2, iclass 10, count 2 2006.201.03:48:54.00#ibcon#flushed, iclass 10, count 2 2006.201.03:48:54.00#ibcon#about to write, iclass 10, count 2 2006.201.03:48:54.00#ibcon#wrote, iclass 10, count 2 2006.201.03:48:54.00#ibcon#about to read 3, iclass 10, count 2 2006.201.03:48:54.03#ibcon#read 3, iclass 10, count 2 2006.201.03:48:54.03#ibcon#about to read 4, iclass 10, count 2 2006.201.03:48:54.03#ibcon#read 4, iclass 10, count 2 2006.201.03:48:54.03#ibcon#about to read 5, iclass 10, count 2 2006.201.03:48:54.03#ibcon#read 5, iclass 10, count 2 2006.201.03:48:54.03#ibcon#about to read 6, iclass 10, count 2 2006.201.03:48:54.03#ibcon#read 6, iclass 10, count 2 2006.201.03:48:54.03#ibcon#end of sib2, iclass 10, count 2 2006.201.03:48:54.03#ibcon#*after write, iclass 10, count 2 2006.201.03:48:54.03#ibcon#*before return 0, iclass 10, count 2 2006.201.03:48:54.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:54.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.03:48:54.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.03:48:54.03#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:54.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:54.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:54.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:54.15#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:48:54.15#ibcon#first serial, iclass 10, count 0 2006.201.03:48:54.15#ibcon#enter sib2, iclass 10, count 0 2006.201.03:48:54.15#ibcon#flushed, iclass 10, count 0 2006.201.03:48:54.15#ibcon#about to write, iclass 10, count 0 2006.201.03:48:54.15#ibcon#wrote, iclass 10, count 0 2006.201.03:48:54.15#ibcon#about to read 3, iclass 10, count 0 2006.201.03:48:54.17#ibcon#read 3, iclass 10, count 0 2006.201.03:48:54.17#ibcon#about to read 4, iclass 10, count 0 2006.201.03:48:54.17#ibcon#read 4, iclass 10, count 0 2006.201.03:48:54.17#ibcon#about to read 5, iclass 10, count 0 2006.201.03:48:54.17#ibcon#read 5, iclass 10, count 0 2006.201.03:48:54.17#ibcon#about to read 6, iclass 10, count 0 2006.201.03:48:54.17#ibcon#read 6, iclass 10, count 0 2006.201.03:48:54.17#ibcon#end of sib2, iclass 10, count 0 2006.201.03:48:54.17#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:48:54.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:48:54.17#ibcon#[27=USB\r\n] 2006.201.03:48:54.17#ibcon#*before write, iclass 10, count 0 2006.201.03:48:54.17#ibcon#enter sib2, iclass 10, count 0 2006.201.03:48:54.17#ibcon#flushed, iclass 10, count 0 2006.201.03:48:54.17#ibcon#about to write, iclass 10, count 0 2006.201.03:48:54.17#ibcon#wrote, iclass 10, count 0 2006.201.03:48:54.17#ibcon#about to read 3, iclass 10, count 0 2006.201.03:48:54.20#ibcon#read 3, iclass 10, count 0 2006.201.03:48:54.20#ibcon#about to read 4, iclass 10, count 0 2006.201.03:48:54.20#ibcon#read 4, iclass 10, count 0 2006.201.03:48:54.20#ibcon#about to read 5, iclass 10, count 0 2006.201.03:48:54.20#ibcon#read 5, iclass 10, count 0 2006.201.03:48:54.20#ibcon#about to read 6, iclass 10, count 0 2006.201.03:48:54.20#ibcon#read 6, iclass 10, count 0 2006.201.03:48:54.20#ibcon#end of sib2, iclass 10, count 0 2006.201.03:48:54.20#ibcon#*after write, iclass 10, count 0 2006.201.03:48:54.20#ibcon#*before return 0, iclass 10, count 0 2006.201.03:48:54.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:54.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.03:48:54.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:48:54.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:48:54.20$vck44/vblo=3,649.99 2006.201.03:48:54.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.03:48:54.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.03:48:54.20#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:54.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:54.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:54.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:54.20#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:48:54.20#ibcon#first serial, iclass 12, count 0 2006.201.03:48:54.20#ibcon#enter sib2, iclass 12, count 0 2006.201.03:48:54.20#ibcon#flushed, iclass 12, count 0 2006.201.03:48:54.20#ibcon#about to write, iclass 12, count 0 2006.201.03:48:54.20#ibcon#wrote, iclass 12, count 0 2006.201.03:48:54.20#ibcon#about to read 3, iclass 12, count 0 2006.201.03:48:54.22#ibcon#read 3, iclass 12, count 0 2006.201.03:48:54.22#ibcon#about to read 4, iclass 12, count 0 2006.201.03:48:54.22#ibcon#read 4, iclass 12, count 0 2006.201.03:48:54.22#ibcon#about to read 5, iclass 12, count 0 2006.201.03:48:54.22#ibcon#read 5, iclass 12, count 0 2006.201.03:48:54.22#ibcon#about to read 6, iclass 12, count 0 2006.201.03:48:54.22#ibcon#read 6, iclass 12, count 0 2006.201.03:48:54.22#ibcon#end of sib2, iclass 12, count 0 2006.201.03:48:54.22#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:48:54.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:48:54.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:48:54.22#ibcon#*before write, iclass 12, count 0 2006.201.03:48:54.22#ibcon#enter sib2, iclass 12, count 0 2006.201.03:48:54.22#ibcon#flushed, iclass 12, count 0 2006.201.03:48:54.22#ibcon#about to write, iclass 12, count 0 2006.201.03:48:54.22#ibcon#wrote, iclass 12, count 0 2006.201.03:48:54.22#ibcon#about to read 3, iclass 12, count 0 2006.201.03:48:54.26#ibcon#read 3, iclass 12, count 0 2006.201.03:48:54.26#ibcon#about to read 4, iclass 12, count 0 2006.201.03:48:54.26#ibcon#read 4, iclass 12, count 0 2006.201.03:48:54.26#ibcon#about to read 5, iclass 12, count 0 2006.201.03:48:54.26#ibcon#read 5, iclass 12, count 0 2006.201.03:48:54.26#ibcon#about to read 6, iclass 12, count 0 2006.201.03:48:54.26#ibcon#read 6, iclass 12, count 0 2006.201.03:48:54.26#ibcon#end of sib2, iclass 12, count 0 2006.201.03:48:54.26#ibcon#*after write, iclass 12, count 0 2006.201.03:48:54.26#ibcon#*before return 0, iclass 12, count 0 2006.201.03:48:54.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:54.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:48:54.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:48:54.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:48:54.26$vck44/vb=3,4 2006.201.03:48:54.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.03:48:54.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.03:48:54.26#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:54.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:54.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:54.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:54.32#ibcon#enter wrdev, iclass 14, count 2 2006.201.03:48:54.32#ibcon#first serial, iclass 14, count 2 2006.201.03:48:54.32#ibcon#enter sib2, iclass 14, count 2 2006.201.03:48:54.32#ibcon#flushed, iclass 14, count 2 2006.201.03:48:54.32#ibcon#about to write, iclass 14, count 2 2006.201.03:48:54.32#ibcon#wrote, iclass 14, count 2 2006.201.03:48:54.32#ibcon#about to read 3, iclass 14, count 2 2006.201.03:48:54.34#ibcon#read 3, iclass 14, count 2 2006.201.03:48:54.34#ibcon#about to read 4, iclass 14, count 2 2006.201.03:48:54.34#ibcon#read 4, iclass 14, count 2 2006.201.03:48:54.34#ibcon#about to read 5, iclass 14, count 2 2006.201.03:48:54.34#ibcon#read 5, iclass 14, count 2 2006.201.03:48:54.34#ibcon#about to read 6, iclass 14, count 2 2006.201.03:48:54.34#ibcon#read 6, iclass 14, count 2 2006.201.03:48:54.34#ibcon#end of sib2, iclass 14, count 2 2006.201.03:48:54.34#ibcon#*mode == 0, iclass 14, count 2 2006.201.03:48:54.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.03:48:54.34#ibcon#[27=AT03-04\r\n] 2006.201.03:48:54.34#ibcon#*before write, iclass 14, count 2 2006.201.03:48:54.34#ibcon#enter sib2, iclass 14, count 2 2006.201.03:48:54.34#ibcon#flushed, iclass 14, count 2 2006.201.03:48:54.34#ibcon#about to write, iclass 14, count 2 2006.201.03:48:54.34#ibcon#wrote, iclass 14, count 2 2006.201.03:48:54.34#ibcon#about to read 3, iclass 14, count 2 2006.201.03:48:54.37#ibcon#read 3, iclass 14, count 2 2006.201.03:48:54.37#ibcon#about to read 4, iclass 14, count 2 2006.201.03:48:54.37#ibcon#read 4, iclass 14, count 2 2006.201.03:48:54.37#ibcon#about to read 5, iclass 14, count 2 2006.201.03:48:54.37#ibcon#read 5, iclass 14, count 2 2006.201.03:48:54.37#ibcon#about to read 6, iclass 14, count 2 2006.201.03:48:54.37#ibcon#read 6, iclass 14, count 2 2006.201.03:48:54.37#ibcon#end of sib2, iclass 14, count 2 2006.201.03:48:54.37#ibcon#*after write, iclass 14, count 2 2006.201.03:48:54.37#ibcon#*before return 0, iclass 14, count 2 2006.201.03:48:54.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:54.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.03:48:54.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.03:48:54.37#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:54.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:54.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:54.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:54.49#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:48:54.49#ibcon#first serial, iclass 14, count 0 2006.201.03:48:54.49#ibcon#enter sib2, iclass 14, count 0 2006.201.03:48:54.49#ibcon#flushed, iclass 14, count 0 2006.201.03:48:54.49#ibcon#about to write, iclass 14, count 0 2006.201.03:48:54.49#ibcon#wrote, iclass 14, count 0 2006.201.03:48:54.49#ibcon#about to read 3, iclass 14, count 0 2006.201.03:48:54.51#ibcon#read 3, iclass 14, count 0 2006.201.03:48:54.51#ibcon#about to read 4, iclass 14, count 0 2006.201.03:48:54.51#ibcon#read 4, iclass 14, count 0 2006.201.03:48:54.51#ibcon#about to read 5, iclass 14, count 0 2006.201.03:48:54.51#ibcon#read 5, iclass 14, count 0 2006.201.03:48:54.51#ibcon#about to read 6, iclass 14, count 0 2006.201.03:48:54.51#ibcon#read 6, iclass 14, count 0 2006.201.03:48:54.51#ibcon#end of sib2, iclass 14, count 0 2006.201.03:48:54.51#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:48:54.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:48:54.51#ibcon#[27=USB\r\n] 2006.201.03:48:54.51#ibcon#*before write, iclass 14, count 0 2006.201.03:48:54.51#ibcon#enter sib2, iclass 14, count 0 2006.201.03:48:54.51#ibcon#flushed, iclass 14, count 0 2006.201.03:48:54.51#ibcon#about to write, iclass 14, count 0 2006.201.03:48:54.51#ibcon#wrote, iclass 14, count 0 2006.201.03:48:54.51#ibcon#about to read 3, iclass 14, count 0 2006.201.03:48:54.54#ibcon#read 3, iclass 14, count 0 2006.201.03:48:54.54#ibcon#about to read 4, iclass 14, count 0 2006.201.03:48:54.54#ibcon#read 4, iclass 14, count 0 2006.201.03:48:54.54#ibcon#about to read 5, iclass 14, count 0 2006.201.03:48:54.54#ibcon#read 5, iclass 14, count 0 2006.201.03:48:54.54#ibcon#about to read 6, iclass 14, count 0 2006.201.03:48:54.54#ibcon#read 6, iclass 14, count 0 2006.201.03:48:54.54#ibcon#end of sib2, iclass 14, count 0 2006.201.03:48:54.54#ibcon#*after write, iclass 14, count 0 2006.201.03:48:54.54#ibcon#*before return 0, iclass 14, count 0 2006.201.03:48:54.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:54.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.03:48:54.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:48:54.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:48:54.54$vck44/vblo=4,679.99 2006.201.03:48:54.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.03:48:54.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.03:48:54.54#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:54.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:54.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:54.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:54.54#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:48:54.54#ibcon#first serial, iclass 16, count 0 2006.201.03:48:54.54#ibcon#enter sib2, iclass 16, count 0 2006.201.03:48:54.54#ibcon#flushed, iclass 16, count 0 2006.201.03:48:54.54#ibcon#about to write, iclass 16, count 0 2006.201.03:48:54.54#ibcon#wrote, iclass 16, count 0 2006.201.03:48:54.54#ibcon#about to read 3, iclass 16, count 0 2006.201.03:48:54.56#ibcon#read 3, iclass 16, count 0 2006.201.03:48:54.56#ibcon#about to read 4, iclass 16, count 0 2006.201.03:48:54.56#ibcon#read 4, iclass 16, count 0 2006.201.03:48:54.56#ibcon#about to read 5, iclass 16, count 0 2006.201.03:48:54.56#ibcon#read 5, iclass 16, count 0 2006.201.03:48:54.56#ibcon#about to read 6, iclass 16, count 0 2006.201.03:48:54.56#ibcon#read 6, iclass 16, count 0 2006.201.03:48:54.56#ibcon#end of sib2, iclass 16, count 0 2006.201.03:48:54.56#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:48:54.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:48:54.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:48:54.56#ibcon#*before write, iclass 16, count 0 2006.201.03:48:54.56#ibcon#enter sib2, iclass 16, count 0 2006.201.03:48:54.56#ibcon#flushed, iclass 16, count 0 2006.201.03:48:54.56#ibcon#about to write, iclass 16, count 0 2006.201.03:48:54.56#ibcon#wrote, iclass 16, count 0 2006.201.03:48:54.56#ibcon#about to read 3, iclass 16, count 0 2006.201.03:48:54.60#ibcon#read 3, iclass 16, count 0 2006.201.03:48:54.60#ibcon#about to read 4, iclass 16, count 0 2006.201.03:48:54.60#ibcon#read 4, iclass 16, count 0 2006.201.03:48:54.60#ibcon#about to read 5, iclass 16, count 0 2006.201.03:48:54.60#ibcon#read 5, iclass 16, count 0 2006.201.03:48:54.60#ibcon#about to read 6, iclass 16, count 0 2006.201.03:48:54.60#ibcon#read 6, iclass 16, count 0 2006.201.03:48:54.60#ibcon#end of sib2, iclass 16, count 0 2006.201.03:48:54.60#ibcon#*after write, iclass 16, count 0 2006.201.03:48:54.60#ibcon#*before return 0, iclass 16, count 0 2006.201.03:48:54.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:54.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.03:48:54.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:48:54.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:48:54.60$vck44/vb=4,5 2006.201.03:48:54.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.03:48:54.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.03:48:54.60#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:54.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:54.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:54.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:54.66#ibcon#enter wrdev, iclass 18, count 2 2006.201.03:48:54.66#ibcon#first serial, iclass 18, count 2 2006.201.03:48:54.66#ibcon#enter sib2, iclass 18, count 2 2006.201.03:48:54.66#ibcon#flushed, iclass 18, count 2 2006.201.03:48:54.66#ibcon#about to write, iclass 18, count 2 2006.201.03:48:54.66#ibcon#wrote, iclass 18, count 2 2006.201.03:48:54.66#ibcon#about to read 3, iclass 18, count 2 2006.201.03:48:54.68#ibcon#read 3, iclass 18, count 2 2006.201.03:48:54.68#ibcon#about to read 4, iclass 18, count 2 2006.201.03:48:54.68#ibcon#read 4, iclass 18, count 2 2006.201.03:48:54.68#ibcon#about to read 5, iclass 18, count 2 2006.201.03:48:54.68#ibcon#read 5, iclass 18, count 2 2006.201.03:48:54.68#ibcon#about to read 6, iclass 18, count 2 2006.201.03:48:54.68#ibcon#read 6, iclass 18, count 2 2006.201.03:48:54.68#ibcon#end of sib2, iclass 18, count 2 2006.201.03:48:54.68#ibcon#*mode == 0, iclass 18, count 2 2006.201.03:48:54.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.03:48:54.68#ibcon#[27=AT04-05\r\n] 2006.201.03:48:54.68#ibcon#*before write, iclass 18, count 2 2006.201.03:48:54.68#ibcon#enter sib2, iclass 18, count 2 2006.201.03:48:54.68#ibcon#flushed, iclass 18, count 2 2006.201.03:48:54.68#ibcon#about to write, iclass 18, count 2 2006.201.03:48:54.68#ibcon#wrote, iclass 18, count 2 2006.201.03:48:54.68#ibcon#about to read 3, iclass 18, count 2 2006.201.03:48:54.71#ibcon#read 3, iclass 18, count 2 2006.201.03:48:54.71#ibcon#about to read 4, iclass 18, count 2 2006.201.03:48:54.71#ibcon#read 4, iclass 18, count 2 2006.201.03:48:54.71#ibcon#about to read 5, iclass 18, count 2 2006.201.03:48:54.71#ibcon#read 5, iclass 18, count 2 2006.201.03:48:54.71#ibcon#about to read 6, iclass 18, count 2 2006.201.03:48:54.71#ibcon#read 6, iclass 18, count 2 2006.201.03:48:54.71#ibcon#end of sib2, iclass 18, count 2 2006.201.03:48:54.71#ibcon#*after write, iclass 18, count 2 2006.201.03:48:54.71#ibcon#*before return 0, iclass 18, count 2 2006.201.03:48:54.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:54.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.03:48:54.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.03:48:54.71#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:54.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:54.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:54.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:54.83#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:48:54.83#ibcon#first serial, iclass 18, count 0 2006.201.03:48:54.83#ibcon#enter sib2, iclass 18, count 0 2006.201.03:48:54.83#ibcon#flushed, iclass 18, count 0 2006.201.03:48:54.83#ibcon#about to write, iclass 18, count 0 2006.201.03:48:54.83#ibcon#wrote, iclass 18, count 0 2006.201.03:48:54.83#ibcon#about to read 3, iclass 18, count 0 2006.201.03:48:54.85#ibcon#read 3, iclass 18, count 0 2006.201.03:48:54.85#ibcon#about to read 4, iclass 18, count 0 2006.201.03:48:54.85#ibcon#read 4, iclass 18, count 0 2006.201.03:48:54.85#ibcon#about to read 5, iclass 18, count 0 2006.201.03:48:54.85#ibcon#read 5, iclass 18, count 0 2006.201.03:48:54.85#ibcon#about to read 6, iclass 18, count 0 2006.201.03:48:54.85#ibcon#read 6, iclass 18, count 0 2006.201.03:48:54.85#ibcon#end of sib2, iclass 18, count 0 2006.201.03:48:54.85#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:48:54.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:48:54.85#ibcon#[27=USB\r\n] 2006.201.03:48:54.85#ibcon#*before write, iclass 18, count 0 2006.201.03:48:54.85#ibcon#enter sib2, iclass 18, count 0 2006.201.03:48:54.85#ibcon#flushed, iclass 18, count 0 2006.201.03:48:54.85#ibcon#about to write, iclass 18, count 0 2006.201.03:48:54.85#ibcon#wrote, iclass 18, count 0 2006.201.03:48:54.85#ibcon#about to read 3, iclass 18, count 0 2006.201.03:48:54.88#ibcon#read 3, iclass 18, count 0 2006.201.03:48:54.88#ibcon#about to read 4, iclass 18, count 0 2006.201.03:48:54.88#ibcon#read 4, iclass 18, count 0 2006.201.03:48:54.88#ibcon#about to read 5, iclass 18, count 0 2006.201.03:48:54.88#ibcon#read 5, iclass 18, count 0 2006.201.03:48:54.88#ibcon#about to read 6, iclass 18, count 0 2006.201.03:48:54.88#ibcon#read 6, iclass 18, count 0 2006.201.03:48:54.88#ibcon#end of sib2, iclass 18, count 0 2006.201.03:48:54.88#ibcon#*after write, iclass 18, count 0 2006.201.03:48:54.88#ibcon#*before return 0, iclass 18, count 0 2006.201.03:48:54.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:54.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.03:48:54.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:48:54.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:48:54.88$vck44/vblo=5,709.99 2006.201.03:48:54.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.03:48:54.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.03:48:54.88#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:54.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:54.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:54.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:54.88#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:48:54.88#ibcon#first serial, iclass 20, count 0 2006.201.03:48:54.88#ibcon#enter sib2, iclass 20, count 0 2006.201.03:48:54.88#ibcon#flushed, iclass 20, count 0 2006.201.03:48:54.88#ibcon#about to write, iclass 20, count 0 2006.201.03:48:54.88#ibcon#wrote, iclass 20, count 0 2006.201.03:48:54.88#ibcon#about to read 3, iclass 20, count 0 2006.201.03:48:54.90#ibcon#read 3, iclass 20, count 0 2006.201.03:48:54.90#ibcon#about to read 4, iclass 20, count 0 2006.201.03:48:54.90#ibcon#read 4, iclass 20, count 0 2006.201.03:48:54.90#ibcon#about to read 5, iclass 20, count 0 2006.201.03:48:54.90#ibcon#read 5, iclass 20, count 0 2006.201.03:48:54.90#ibcon#about to read 6, iclass 20, count 0 2006.201.03:48:54.90#ibcon#read 6, iclass 20, count 0 2006.201.03:48:54.90#ibcon#end of sib2, iclass 20, count 0 2006.201.03:48:54.90#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:48:54.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:48:54.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:48:54.90#ibcon#*before write, iclass 20, count 0 2006.201.03:48:54.90#ibcon#enter sib2, iclass 20, count 0 2006.201.03:48:54.90#ibcon#flushed, iclass 20, count 0 2006.201.03:48:54.90#ibcon#about to write, iclass 20, count 0 2006.201.03:48:54.90#ibcon#wrote, iclass 20, count 0 2006.201.03:48:54.90#ibcon#about to read 3, iclass 20, count 0 2006.201.03:48:54.95#ibcon#read 3, iclass 20, count 0 2006.201.03:48:54.95#ibcon#about to read 4, iclass 20, count 0 2006.201.03:48:54.95#ibcon#read 4, iclass 20, count 0 2006.201.03:48:54.95#ibcon#about to read 5, iclass 20, count 0 2006.201.03:48:54.95#ibcon#read 5, iclass 20, count 0 2006.201.03:48:54.95#ibcon#about to read 6, iclass 20, count 0 2006.201.03:48:54.95#ibcon#read 6, iclass 20, count 0 2006.201.03:48:54.95#ibcon#end of sib2, iclass 20, count 0 2006.201.03:48:54.95#ibcon#*after write, iclass 20, count 0 2006.201.03:48:54.95#ibcon#*before return 0, iclass 20, count 0 2006.201.03:48:54.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:54.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.03:48:54.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:48:54.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:48:54.95$vck44/vb=5,4 2006.201.03:48:54.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.03:48:54.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.03:48:54.95#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:54.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:55.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:55.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:55.00#ibcon#enter wrdev, iclass 22, count 2 2006.201.03:48:55.00#ibcon#first serial, iclass 22, count 2 2006.201.03:48:55.00#ibcon#enter sib2, iclass 22, count 2 2006.201.03:48:55.00#ibcon#flushed, iclass 22, count 2 2006.201.03:48:55.00#ibcon#about to write, iclass 22, count 2 2006.201.03:48:55.00#ibcon#wrote, iclass 22, count 2 2006.201.03:48:55.00#ibcon#about to read 3, iclass 22, count 2 2006.201.03:48:55.02#ibcon#read 3, iclass 22, count 2 2006.201.03:48:55.02#ibcon#about to read 4, iclass 22, count 2 2006.201.03:48:55.02#ibcon#read 4, iclass 22, count 2 2006.201.03:48:55.02#ibcon#about to read 5, iclass 22, count 2 2006.201.03:48:55.02#ibcon#read 5, iclass 22, count 2 2006.201.03:48:55.02#ibcon#about to read 6, iclass 22, count 2 2006.201.03:48:55.02#ibcon#read 6, iclass 22, count 2 2006.201.03:48:55.02#ibcon#end of sib2, iclass 22, count 2 2006.201.03:48:55.02#ibcon#*mode == 0, iclass 22, count 2 2006.201.03:48:55.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.03:48:55.02#ibcon#[27=AT05-04\r\n] 2006.201.03:48:55.02#ibcon#*before write, iclass 22, count 2 2006.201.03:48:55.02#ibcon#enter sib2, iclass 22, count 2 2006.201.03:48:55.02#ibcon#flushed, iclass 22, count 2 2006.201.03:48:55.02#ibcon#about to write, iclass 22, count 2 2006.201.03:48:55.02#ibcon#wrote, iclass 22, count 2 2006.201.03:48:55.02#ibcon#about to read 3, iclass 22, count 2 2006.201.03:48:55.05#ibcon#read 3, iclass 22, count 2 2006.201.03:48:55.05#ibcon#about to read 4, iclass 22, count 2 2006.201.03:48:55.05#ibcon#read 4, iclass 22, count 2 2006.201.03:48:55.05#ibcon#about to read 5, iclass 22, count 2 2006.201.03:48:55.05#ibcon#read 5, iclass 22, count 2 2006.201.03:48:55.05#ibcon#about to read 6, iclass 22, count 2 2006.201.03:48:55.05#ibcon#read 6, iclass 22, count 2 2006.201.03:48:55.05#ibcon#end of sib2, iclass 22, count 2 2006.201.03:48:55.05#ibcon#*after write, iclass 22, count 2 2006.201.03:48:55.05#ibcon#*before return 0, iclass 22, count 2 2006.201.03:48:55.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:55.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.03:48:55.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.03:48:55.05#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:55.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:55.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:55.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:55.17#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:48:55.17#ibcon#first serial, iclass 22, count 0 2006.201.03:48:55.17#ibcon#enter sib2, iclass 22, count 0 2006.201.03:48:55.17#ibcon#flushed, iclass 22, count 0 2006.201.03:48:55.17#ibcon#about to write, iclass 22, count 0 2006.201.03:48:55.17#ibcon#wrote, iclass 22, count 0 2006.201.03:48:55.17#ibcon#about to read 3, iclass 22, count 0 2006.201.03:48:55.19#ibcon#read 3, iclass 22, count 0 2006.201.03:48:55.19#ibcon#about to read 4, iclass 22, count 0 2006.201.03:48:55.19#ibcon#read 4, iclass 22, count 0 2006.201.03:48:55.19#ibcon#about to read 5, iclass 22, count 0 2006.201.03:48:55.19#ibcon#read 5, iclass 22, count 0 2006.201.03:48:55.19#ibcon#about to read 6, iclass 22, count 0 2006.201.03:48:55.19#ibcon#read 6, iclass 22, count 0 2006.201.03:48:55.19#ibcon#end of sib2, iclass 22, count 0 2006.201.03:48:55.19#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:48:55.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:48:55.19#ibcon#[27=USB\r\n] 2006.201.03:48:55.19#ibcon#*before write, iclass 22, count 0 2006.201.03:48:55.19#ibcon#enter sib2, iclass 22, count 0 2006.201.03:48:55.19#ibcon#flushed, iclass 22, count 0 2006.201.03:48:55.19#ibcon#about to write, iclass 22, count 0 2006.201.03:48:55.19#ibcon#wrote, iclass 22, count 0 2006.201.03:48:55.19#ibcon#about to read 3, iclass 22, count 0 2006.201.03:48:55.22#ibcon#read 3, iclass 22, count 0 2006.201.03:48:55.22#ibcon#about to read 4, iclass 22, count 0 2006.201.03:48:55.22#ibcon#read 4, iclass 22, count 0 2006.201.03:48:55.22#ibcon#about to read 5, iclass 22, count 0 2006.201.03:48:55.22#ibcon#read 5, iclass 22, count 0 2006.201.03:48:55.22#ibcon#about to read 6, iclass 22, count 0 2006.201.03:48:55.22#ibcon#read 6, iclass 22, count 0 2006.201.03:48:55.22#ibcon#end of sib2, iclass 22, count 0 2006.201.03:48:55.22#ibcon#*after write, iclass 22, count 0 2006.201.03:48:55.22#ibcon#*before return 0, iclass 22, count 0 2006.201.03:48:55.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:55.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.03:48:55.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:48:55.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:48:55.22$vck44/vblo=6,719.99 2006.201.03:48:55.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.03:48:55.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.03:48:55.22#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:55.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:55.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:55.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:55.22#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:48:55.22#ibcon#first serial, iclass 24, count 0 2006.201.03:48:55.22#ibcon#enter sib2, iclass 24, count 0 2006.201.03:48:55.22#ibcon#flushed, iclass 24, count 0 2006.201.03:48:55.22#ibcon#about to write, iclass 24, count 0 2006.201.03:48:55.22#ibcon#wrote, iclass 24, count 0 2006.201.03:48:55.22#ibcon#about to read 3, iclass 24, count 0 2006.201.03:48:55.24#ibcon#read 3, iclass 24, count 0 2006.201.03:48:55.24#ibcon#about to read 4, iclass 24, count 0 2006.201.03:48:55.24#ibcon#read 4, iclass 24, count 0 2006.201.03:48:55.24#ibcon#about to read 5, iclass 24, count 0 2006.201.03:48:55.24#ibcon#read 5, iclass 24, count 0 2006.201.03:48:55.24#ibcon#about to read 6, iclass 24, count 0 2006.201.03:48:55.24#ibcon#read 6, iclass 24, count 0 2006.201.03:48:55.24#ibcon#end of sib2, iclass 24, count 0 2006.201.03:48:55.24#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:48:55.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:48:55.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:48:55.24#ibcon#*before write, iclass 24, count 0 2006.201.03:48:55.24#ibcon#enter sib2, iclass 24, count 0 2006.201.03:48:55.24#ibcon#flushed, iclass 24, count 0 2006.201.03:48:55.24#ibcon#about to write, iclass 24, count 0 2006.201.03:48:55.24#ibcon#wrote, iclass 24, count 0 2006.201.03:48:55.24#ibcon#about to read 3, iclass 24, count 0 2006.201.03:48:55.28#ibcon#read 3, iclass 24, count 0 2006.201.03:48:55.28#ibcon#about to read 4, iclass 24, count 0 2006.201.03:48:55.28#ibcon#read 4, iclass 24, count 0 2006.201.03:48:55.28#ibcon#about to read 5, iclass 24, count 0 2006.201.03:48:55.28#ibcon#read 5, iclass 24, count 0 2006.201.03:48:55.28#ibcon#about to read 6, iclass 24, count 0 2006.201.03:48:55.28#ibcon#read 6, iclass 24, count 0 2006.201.03:48:55.28#ibcon#end of sib2, iclass 24, count 0 2006.201.03:48:55.28#ibcon#*after write, iclass 24, count 0 2006.201.03:48:55.28#ibcon#*before return 0, iclass 24, count 0 2006.201.03:48:55.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:55.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.03:48:55.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:48:55.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:48:55.28$vck44/vb=6,4 2006.201.03:48:55.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.03:48:55.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.03:48:55.28#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:55.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:55.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:55.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:55.34#ibcon#enter wrdev, iclass 26, count 2 2006.201.03:48:55.34#ibcon#first serial, iclass 26, count 2 2006.201.03:48:55.34#ibcon#enter sib2, iclass 26, count 2 2006.201.03:48:55.34#ibcon#flushed, iclass 26, count 2 2006.201.03:48:55.34#ibcon#about to write, iclass 26, count 2 2006.201.03:48:55.34#ibcon#wrote, iclass 26, count 2 2006.201.03:48:55.34#ibcon#about to read 3, iclass 26, count 2 2006.201.03:48:55.36#ibcon#read 3, iclass 26, count 2 2006.201.03:48:55.36#ibcon#about to read 4, iclass 26, count 2 2006.201.03:48:55.36#ibcon#read 4, iclass 26, count 2 2006.201.03:48:55.36#ibcon#about to read 5, iclass 26, count 2 2006.201.03:48:55.36#ibcon#read 5, iclass 26, count 2 2006.201.03:48:55.36#ibcon#about to read 6, iclass 26, count 2 2006.201.03:48:55.36#ibcon#read 6, iclass 26, count 2 2006.201.03:48:55.36#ibcon#end of sib2, iclass 26, count 2 2006.201.03:48:55.36#ibcon#*mode == 0, iclass 26, count 2 2006.201.03:48:55.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.03:48:55.36#ibcon#[27=AT06-04\r\n] 2006.201.03:48:55.36#ibcon#*before write, iclass 26, count 2 2006.201.03:48:55.36#ibcon#enter sib2, iclass 26, count 2 2006.201.03:48:55.36#ibcon#flushed, iclass 26, count 2 2006.201.03:48:55.36#ibcon#about to write, iclass 26, count 2 2006.201.03:48:55.36#ibcon#wrote, iclass 26, count 2 2006.201.03:48:55.36#ibcon#about to read 3, iclass 26, count 2 2006.201.03:48:55.39#ibcon#read 3, iclass 26, count 2 2006.201.03:48:55.39#ibcon#about to read 4, iclass 26, count 2 2006.201.03:48:55.39#ibcon#read 4, iclass 26, count 2 2006.201.03:48:55.39#ibcon#about to read 5, iclass 26, count 2 2006.201.03:48:55.39#ibcon#read 5, iclass 26, count 2 2006.201.03:48:55.39#ibcon#about to read 6, iclass 26, count 2 2006.201.03:48:55.39#ibcon#read 6, iclass 26, count 2 2006.201.03:48:55.39#ibcon#end of sib2, iclass 26, count 2 2006.201.03:48:55.39#ibcon#*after write, iclass 26, count 2 2006.201.03:48:55.39#ibcon#*before return 0, iclass 26, count 2 2006.201.03:48:55.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:55.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.03:48:55.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.03:48:55.39#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:55.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:55.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:55.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:55.51#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:48:55.51#ibcon#first serial, iclass 26, count 0 2006.201.03:48:55.51#ibcon#enter sib2, iclass 26, count 0 2006.201.03:48:55.51#ibcon#flushed, iclass 26, count 0 2006.201.03:48:55.51#ibcon#about to write, iclass 26, count 0 2006.201.03:48:55.51#ibcon#wrote, iclass 26, count 0 2006.201.03:48:55.51#ibcon#about to read 3, iclass 26, count 0 2006.201.03:48:55.53#ibcon#read 3, iclass 26, count 0 2006.201.03:48:55.53#ibcon#about to read 4, iclass 26, count 0 2006.201.03:48:55.53#ibcon#read 4, iclass 26, count 0 2006.201.03:48:55.53#ibcon#about to read 5, iclass 26, count 0 2006.201.03:48:55.53#ibcon#read 5, iclass 26, count 0 2006.201.03:48:55.53#ibcon#about to read 6, iclass 26, count 0 2006.201.03:48:55.53#ibcon#read 6, iclass 26, count 0 2006.201.03:48:55.53#ibcon#end of sib2, iclass 26, count 0 2006.201.03:48:55.53#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:48:55.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:48:55.53#ibcon#[27=USB\r\n] 2006.201.03:48:55.53#ibcon#*before write, iclass 26, count 0 2006.201.03:48:55.53#ibcon#enter sib2, iclass 26, count 0 2006.201.03:48:55.53#ibcon#flushed, iclass 26, count 0 2006.201.03:48:55.53#ibcon#about to write, iclass 26, count 0 2006.201.03:48:55.53#ibcon#wrote, iclass 26, count 0 2006.201.03:48:55.53#ibcon#about to read 3, iclass 26, count 0 2006.201.03:48:55.56#ibcon#read 3, iclass 26, count 0 2006.201.03:48:55.56#ibcon#about to read 4, iclass 26, count 0 2006.201.03:48:55.56#ibcon#read 4, iclass 26, count 0 2006.201.03:48:55.56#ibcon#about to read 5, iclass 26, count 0 2006.201.03:48:55.56#ibcon#read 5, iclass 26, count 0 2006.201.03:48:55.56#ibcon#about to read 6, iclass 26, count 0 2006.201.03:48:55.56#ibcon#read 6, iclass 26, count 0 2006.201.03:48:55.56#ibcon#end of sib2, iclass 26, count 0 2006.201.03:48:55.56#ibcon#*after write, iclass 26, count 0 2006.201.03:48:55.56#ibcon#*before return 0, iclass 26, count 0 2006.201.03:48:55.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:55.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.03:48:55.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:48:55.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:48:55.56$vck44/vblo=7,734.99 2006.201.03:48:55.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.03:48:55.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.03:48:55.56#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:55.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:55.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:55.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:55.56#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:48:55.56#ibcon#first serial, iclass 28, count 0 2006.201.03:48:55.56#ibcon#enter sib2, iclass 28, count 0 2006.201.03:48:55.56#ibcon#flushed, iclass 28, count 0 2006.201.03:48:55.56#ibcon#about to write, iclass 28, count 0 2006.201.03:48:55.56#ibcon#wrote, iclass 28, count 0 2006.201.03:48:55.56#ibcon#about to read 3, iclass 28, count 0 2006.201.03:48:55.58#ibcon#read 3, iclass 28, count 0 2006.201.03:48:55.58#ibcon#about to read 4, iclass 28, count 0 2006.201.03:48:55.58#ibcon#read 4, iclass 28, count 0 2006.201.03:48:55.58#ibcon#about to read 5, iclass 28, count 0 2006.201.03:48:55.58#ibcon#read 5, iclass 28, count 0 2006.201.03:48:55.58#ibcon#about to read 6, iclass 28, count 0 2006.201.03:48:55.58#ibcon#read 6, iclass 28, count 0 2006.201.03:48:55.58#ibcon#end of sib2, iclass 28, count 0 2006.201.03:48:55.58#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:48:55.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:48:55.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:48:55.58#ibcon#*before write, iclass 28, count 0 2006.201.03:48:55.58#ibcon#enter sib2, iclass 28, count 0 2006.201.03:48:55.58#ibcon#flushed, iclass 28, count 0 2006.201.03:48:55.58#ibcon#about to write, iclass 28, count 0 2006.201.03:48:55.58#ibcon#wrote, iclass 28, count 0 2006.201.03:48:55.58#ibcon#about to read 3, iclass 28, count 0 2006.201.03:48:55.62#ibcon#read 3, iclass 28, count 0 2006.201.03:48:55.62#ibcon#about to read 4, iclass 28, count 0 2006.201.03:48:55.62#ibcon#read 4, iclass 28, count 0 2006.201.03:48:55.62#ibcon#about to read 5, iclass 28, count 0 2006.201.03:48:55.62#ibcon#read 5, iclass 28, count 0 2006.201.03:48:55.62#ibcon#about to read 6, iclass 28, count 0 2006.201.03:48:55.62#ibcon#read 6, iclass 28, count 0 2006.201.03:48:55.62#ibcon#end of sib2, iclass 28, count 0 2006.201.03:48:55.62#ibcon#*after write, iclass 28, count 0 2006.201.03:48:55.62#ibcon#*before return 0, iclass 28, count 0 2006.201.03:48:55.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:55.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.03:48:55.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:48:55.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:48:55.62$vck44/vb=7,4 2006.201.03:48:55.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.03:48:55.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.03:48:55.62#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:55.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:55.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:55.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:55.68#ibcon#enter wrdev, iclass 30, count 2 2006.201.03:48:55.68#ibcon#first serial, iclass 30, count 2 2006.201.03:48:55.68#ibcon#enter sib2, iclass 30, count 2 2006.201.03:48:55.68#ibcon#flushed, iclass 30, count 2 2006.201.03:48:55.68#ibcon#about to write, iclass 30, count 2 2006.201.03:48:55.68#ibcon#wrote, iclass 30, count 2 2006.201.03:48:55.68#ibcon#about to read 3, iclass 30, count 2 2006.201.03:48:55.70#ibcon#read 3, iclass 30, count 2 2006.201.03:48:55.70#ibcon#about to read 4, iclass 30, count 2 2006.201.03:48:55.70#ibcon#read 4, iclass 30, count 2 2006.201.03:48:55.70#ibcon#about to read 5, iclass 30, count 2 2006.201.03:48:55.70#ibcon#read 5, iclass 30, count 2 2006.201.03:48:55.70#ibcon#about to read 6, iclass 30, count 2 2006.201.03:48:55.70#ibcon#read 6, iclass 30, count 2 2006.201.03:48:55.70#ibcon#end of sib2, iclass 30, count 2 2006.201.03:48:55.70#ibcon#*mode == 0, iclass 30, count 2 2006.201.03:48:55.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.03:48:55.70#ibcon#[27=AT07-04\r\n] 2006.201.03:48:55.70#ibcon#*before write, iclass 30, count 2 2006.201.03:48:55.70#ibcon#enter sib2, iclass 30, count 2 2006.201.03:48:55.70#ibcon#flushed, iclass 30, count 2 2006.201.03:48:55.70#ibcon#about to write, iclass 30, count 2 2006.201.03:48:55.70#ibcon#wrote, iclass 30, count 2 2006.201.03:48:55.70#ibcon#about to read 3, iclass 30, count 2 2006.201.03:48:55.73#ibcon#read 3, iclass 30, count 2 2006.201.03:48:55.73#ibcon#about to read 4, iclass 30, count 2 2006.201.03:48:55.73#ibcon#read 4, iclass 30, count 2 2006.201.03:48:55.73#ibcon#about to read 5, iclass 30, count 2 2006.201.03:48:55.73#ibcon#read 5, iclass 30, count 2 2006.201.03:48:55.73#ibcon#about to read 6, iclass 30, count 2 2006.201.03:48:55.73#ibcon#read 6, iclass 30, count 2 2006.201.03:48:55.73#ibcon#end of sib2, iclass 30, count 2 2006.201.03:48:55.73#ibcon#*after write, iclass 30, count 2 2006.201.03:48:55.73#ibcon#*before return 0, iclass 30, count 2 2006.201.03:48:55.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:55.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.03:48:55.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.03:48:55.73#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:55.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:55.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:55.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:55.85#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:48:55.85#ibcon#first serial, iclass 30, count 0 2006.201.03:48:55.85#ibcon#enter sib2, iclass 30, count 0 2006.201.03:48:55.85#ibcon#flushed, iclass 30, count 0 2006.201.03:48:55.85#ibcon#about to write, iclass 30, count 0 2006.201.03:48:55.85#ibcon#wrote, iclass 30, count 0 2006.201.03:48:55.85#ibcon#about to read 3, iclass 30, count 0 2006.201.03:48:55.87#ibcon#read 3, iclass 30, count 0 2006.201.03:48:55.87#ibcon#about to read 4, iclass 30, count 0 2006.201.03:48:55.87#ibcon#read 4, iclass 30, count 0 2006.201.03:48:55.87#ibcon#about to read 5, iclass 30, count 0 2006.201.03:48:55.87#ibcon#read 5, iclass 30, count 0 2006.201.03:48:55.87#ibcon#about to read 6, iclass 30, count 0 2006.201.03:48:55.87#ibcon#read 6, iclass 30, count 0 2006.201.03:48:55.87#ibcon#end of sib2, iclass 30, count 0 2006.201.03:48:55.87#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:48:55.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:48:55.87#ibcon#[27=USB\r\n] 2006.201.03:48:55.87#ibcon#*before write, iclass 30, count 0 2006.201.03:48:55.87#ibcon#enter sib2, iclass 30, count 0 2006.201.03:48:55.87#ibcon#flushed, iclass 30, count 0 2006.201.03:48:55.87#ibcon#about to write, iclass 30, count 0 2006.201.03:48:55.87#ibcon#wrote, iclass 30, count 0 2006.201.03:48:55.87#ibcon#about to read 3, iclass 30, count 0 2006.201.03:48:55.90#ibcon#read 3, iclass 30, count 0 2006.201.03:48:55.90#ibcon#about to read 4, iclass 30, count 0 2006.201.03:48:55.90#ibcon#read 4, iclass 30, count 0 2006.201.03:48:55.90#ibcon#about to read 5, iclass 30, count 0 2006.201.03:48:55.90#ibcon#read 5, iclass 30, count 0 2006.201.03:48:55.90#ibcon#about to read 6, iclass 30, count 0 2006.201.03:48:55.90#ibcon#read 6, iclass 30, count 0 2006.201.03:48:55.90#ibcon#end of sib2, iclass 30, count 0 2006.201.03:48:55.90#ibcon#*after write, iclass 30, count 0 2006.201.03:48:55.90#ibcon#*before return 0, iclass 30, count 0 2006.201.03:48:55.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:55.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.03:48:55.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:48:55.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:48:55.90$vck44/vblo=8,744.99 2006.201.03:48:55.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.03:48:55.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.03:48:55.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:48:55.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:55.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:55.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:55.90#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:48:55.90#ibcon#first serial, iclass 32, count 0 2006.201.03:48:55.90#ibcon#enter sib2, iclass 32, count 0 2006.201.03:48:55.90#ibcon#flushed, iclass 32, count 0 2006.201.03:48:55.90#ibcon#about to write, iclass 32, count 0 2006.201.03:48:55.90#ibcon#wrote, iclass 32, count 0 2006.201.03:48:55.90#ibcon#about to read 3, iclass 32, count 0 2006.201.03:48:55.92#ibcon#read 3, iclass 32, count 0 2006.201.03:48:55.92#ibcon#about to read 4, iclass 32, count 0 2006.201.03:48:55.92#ibcon#read 4, iclass 32, count 0 2006.201.03:48:55.92#ibcon#about to read 5, iclass 32, count 0 2006.201.03:48:55.92#ibcon#read 5, iclass 32, count 0 2006.201.03:48:55.92#ibcon#about to read 6, iclass 32, count 0 2006.201.03:48:55.92#ibcon#read 6, iclass 32, count 0 2006.201.03:48:55.92#ibcon#end of sib2, iclass 32, count 0 2006.201.03:48:55.92#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:48:55.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:48:55.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:48:55.92#ibcon#*before write, iclass 32, count 0 2006.201.03:48:55.92#ibcon#enter sib2, iclass 32, count 0 2006.201.03:48:55.92#ibcon#flushed, iclass 32, count 0 2006.201.03:48:55.92#ibcon#about to write, iclass 32, count 0 2006.201.03:48:55.92#ibcon#wrote, iclass 32, count 0 2006.201.03:48:55.92#ibcon#about to read 3, iclass 32, count 0 2006.201.03:48:55.96#ibcon#read 3, iclass 32, count 0 2006.201.03:48:55.96#ibcon#about to read 4, iclass 32, count 0 2006.201.03:48:55.96#ibcon#read 4, iclass 32, count 0 2006.201.03:48:55.96#ibcon#about to read 5, iclass 32, count 0 2006.201.03:48:55.96#ibcon#read 5, iclass 32, count 0 2006.201.03:48:55.96#ibcon#about to read 6, iclass 32, count 0 2006.201.03:48:55.96#ibcon#read 6, iclass 32, count 0 2006.201.03:48:55.96#ibcon#end of sib2, iclass 32, count 0 2006.201.03:48:55.96#ibcon#*after write, iclass 32, count 0 2006.201.03:48:55.96#ibcon#*before return 0, iclass 32, count 0 2006.201.03:48:55.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:55.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.03:48:55.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:48:55.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:48:55.96$vck44/vb=8,4 2006.201.03:48:55.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.03:48:55.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.03:48:55.96#ibcon#ireg 11 cls_cnt 2 2006.201.03:48:55.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:56.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:56.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:56.02#ibcon#enter wrdev, iclass 34, count 2 2006.201.03:48:56.02#ibcon#first serial, iclass 34, count 2 2006.201.03:48:56.02#ibcon#enter sib2, iclass 34, count 2 2006.201.03:48:56.02#ibcon#flushed, iclass 34, count 2 2006.201.03:48:56.02#ibcon#about to write, iclass 34, count 2 2006.201.03:48:56.02#ibcon#wrote, iclass 34, count 2 2006.201.03:48:56.02#ibcon#about to read 3, iclass 34, count 2 2006.201.03:48:56.04#ibcon#read 3, iclass 34, count 2 2006.201.03:48:56.04#ibcon#about to read 4, iclass 34, count 2 2006.201.03:48:56.04#ibcon#read 4, iclass 34, count 2 2006.201.03:48:56.04#ibcon#about to read 5, iclass 34, count 2 2006.201.03:48:56.04#ibcon#read 5, iclass 34, count 2 2006.201.03:48:56.04#ibcon#about to read 6, iclass 34, count 2 2006.201.03:48:56.04#ibcon#read 6, iclass 34, count 2 2006.201.03:48:56.04#ibcon#end of sib2, iclass 34, count 2 2006.201.03:48:56.04#ibcon#*mode == 0, iclass 34, count 2 2006.201.03:48:56.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.03:48:56.04#ibcon#[27=AT08-04\r\n] 2006.201.03:48:56.04#ibcon#*before write, iclass 34, count 2 2006.201.03:48:56.04#ibcon#enter sib2, iclass 34, count 2 2006.201.03:48:56.04#ibcon#flushed, iclass 34, count 2 2006.201.03:48:56.04#ibcon#about to write, iclass 34, count 2 2006.201.03:48:56.04#ibcon#wrote, iclass 34, count 2 2006.201.03:48:56.04#ibcon#about to read 3, iclass 34, count 2 2006.201.03:48:56.07#ibcon#read 3, iclass 34, count 2 2006.201.03:48:56.07#ibcon#about to read 4, iclass 34, count 2 2006.201.03:48:56.07#ibcon#read 4, iclass 34, count 2 2006.201.03:48:56.07#ibcon#about to read 5, iclass 34, count 2 2006.201.03:48:56.07#ibcon#read 5, iclass 34, count 2 2006.201.03:48:56.07#ibcon#about to read 6, iclass 34, count 2 2006.201.03:48:56.07#ibcon#read 6, iclass 34, count 2 2006.201.03:48:56.07#ibcon#end of sib2, iclass 34, count 2 2006.201.03:48:56.07#ibcon#*after write, iclass 34, count 2 2006.201.03:48:56.07#ibcon#*before return 0, iclass 34, count 2 2006.201.03:48:56.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:56.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.03:48:56.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.03:48:56.07#ibcon#ireg 7 cls_cnt 0 2006.201.03:48:56.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:56.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:56.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:56.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:48:56.19#ibcon#first serial, iclass 34, count 0 2006.201.03:48:56.19#ibcon#enter sib2, iclass 34, count 0 2006.201.03:48:56.19#ibcon#flushed, iclass 34, count 0 2006.201.03:48:56.19#ibcon#about to write, iclass 34, count 0 2006.201.03:48:56.19#ibcon#wrote, iclass 34, count 0 2006.201.03:48:56.19#ibcon#about to read 3, iclass 34, count 0 2006.201.03:48:56.21#ibcon#read 3, iclass 34, count 0 2006.201.03:48:56.21#ibcon#about to read 4, iclass 34, count 0 2006.201.03:48:56.21#ibcon#read 4, iclass 34, count 0 2006.201.03:48:56.21#ibcon#about to read 5, iclass 34, count 0 2006.201.03:48:56.21#ibcon#read 5, iclass 34, count 0 2006.201.03:48:56.21#ibcon#about to read 6, iclass 34, count 0 2006.201.03:48:56.21#ibcon#read 6, iclass 34, count 0 2006.201.03:48:56.21#ibcon#end of sib2, iclass 34, count 0 2006.201.03:48:56.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:48:56.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:48:56.21#ibcon#[27=USB\r\n] 2006.201.03:48:56.21#ibcon#*before write, iclass 34, count 0 2006.201.03:48:56.21#ibcon#enter sib2, iclass 34, count 0 2006.201.03:48:56.21#ibcon#flushed, iclass 34, count 0 2006.201.03:48:56.21#ibcon#about to write, iclass 34, count 0 2006.201.03:48:56.21#ibcon#wrote, iclass 34, count 0 2006.201.03:48:56.21#ibcon#about to read 3, iclass 34, count 0 2006.201.03:48:56.24#ibcon#read 3, iclass 34, count 0 2006.201.03:48:56.24#ibcon#about to read 4, iclass 34, count 0 2006.201.03:48:56.24#ibcon#read 4, iclass 34, count 0 2006.201.03:48:56.24#ibcon#about to read 5, iclass 34, count 0 2006.201.03:48:56.24#ibcon#read 5, iclass 34, count 0 2006.201.03:48:56.24#ibcon#about to read 6, iclass 34, count 0 2006.201.03:48:56.24#ibcon#read 6, iclass 34, count 0 2006.201.03:48:56.24#ibcon#end of sib2, iclass 34, count 0 2006.201.03:48:56.24#ibcon#*after write, iclass 34, count 0 2006.201.03:48:56.24#ibcon#*before return 0, iclass 34, count 0 2006.201.03:48:56.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:56.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.03:48:56.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:48:56.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:48:56.24$vck44/vabw=wide 2006.201.03:48:56.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.03:48:56.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.03:48:56.24#ibcon#ireg 8 cls_cnt 0 2006.201.03:48:56.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:48:56.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:48:56.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:48:56.24#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:48:56.24#ibcon#first serial, iclass 36, count 0 2006.201.03:48:56.24#ibcon#enter sib2, iclass 36, count 0 2006.201.03:48:56.24#ibcon#flushed, iclass 36, count 0 2006.201.03:48:56.24#ibcon#about to write, iclass 36, count 0 2006.201.03:48:56.24#ibcon#wrote, iclass 36, count 0 2006.201.03:48:56.24#ibcon#about to read 3, iclass 36, count 0 2006.201.03:48:56.26#ibcon#read 3, iclass 36, count 0 2006.201.03:48:56.26#ibcon#about to read 4, iclass 36, count 0 2006.201.03:48:56.26#ibcon#read 4, iclass 36, count 0 2006.201.03:48:56.26#ibcon#about to read 5, iclass 36, count 0 2006.201.03:48:56.26#ibcon#read 5, iclass 36, count 0 2006.201.03:48:56.26#ibcon#about to read 6, iclass 36, count 0 2006.201.03:48:56.26#ibcon#read 6, iclass 36, count 0 2006.201.03:48:56.26#ibcon#end of sib2, iclass 36, count 0 2006.201.03:48:56.26#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:48:56.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:48:56.26#ibcon#[25=BW32\r\n] 2006.201.03:48:56.26#ibcon#*before write, iclass 36, count 0 2006.201.03:48:56.26#ibcon#enter sib2, iclass 36, count 0 2006.201.03:48:56.26#ibcon#flushed, iclass 36, count 0 2006.201.03:48:56.26#ibcon#about to write, iclass 36, count 0 2006.201.03:48:56.26#ibcon#wrote, iclass 36, count 0 2006.201.03:48:56.26#ibcon#about to read 3, iclass 36, count 0 2006.201.03:48:56.29#ibcon#read 3, iclass 36, count 0 2006.201.03:48:56.29#ibcon#about to read 4, iclass 36, count 0 2006.201.03:48:56.29#ibcon#read 4, iclass 36, count 0 2006.201.03:48:56.29#ibcon#about to read 5, iclass 36, count 0 2006.201.03:48:56.29#ibcon#read 5, iclass 36, count 0 2006.201.03:48:56.29#ibcon#about to read 6, iclass 36, count 0 2006.201.03:48:56.29#ibcon#read 6, iclass 36, count 0 2006.201.03:48:56.29#ibcon#end of sib2, iclass 36, count 0 2006.201.03:48:56.29#ibcon#*after write, iclass 36, count 0 2006.201.03:48:56.29#ibcon#*before return 0, iclass 36, count 0 2006.201.03:48:56.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:48:56.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.03:48:56.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:48:56.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:48:56.29$vck44/vbbw=wide 2006.201.03:48:56.29#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.03:48:56.29#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.03:48:56.29#ibcon#ireg 8 cls_cnt 0 2006.201.03:48:56.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:48:56.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:48:56.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:48:56.36#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:48:56.36#ibcon#first serial, iclass 38, count 0 2006.201.03:48:56.36#ibcon#enter sib2, iclass 38, count 0 2006.201.03:48:56.36#ibcon#flushed, iclass 38, count 0 2006.201.03:48:56.36#ibcon#about to write, iclass 38, count 0 2006.201.03:48:56.36#ibcon#wrote, iclass 38, count 0 2006.201.03:48:56.36#ibcon#about to read 3, iclass 38, count 0 2006.201.03:48:56.38#ibcon#read 3, iclass 38, count 0 2006.201.03:48:56.38#ibcon#about to read 4, iclass 38, count 0 2006.201.03:48:56.38#ibcon#read 4, iclass 38, count 0 2006.201.03:48:56.38#ibcon#about to read 5, iclass 38, count 0 2006.201.03:48:56.38#ibcon#read 5, iclass 38, count 0 2006.201.03:48:56.38#ibcon#about to read 6, iclass 38, count 0 2006.201.03:48:56.38#ibcon#read 6, iclass 38, count 0 2006.201.03:48:56.38#ibcon#end of sib2, iclass 38, count 0 2006.201.03:48:56.38#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:48:56.38#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:48:56.38#ibcon#[27=BW32\r\n] 2006.201.03:48:56.38#ibcon#*before write, iclass 38, count 0 2006.201.03:48:56.38#ibcon#enter sib2, iclass 38, count 0 2006.201.03:48:56.38#ibcon#flushed, iclass 38, count 0 2006.201.03:48:56.38#ibcon#about to write, iclass 38, count 0 2006.201.03:48:56.38#ibcon#wrote, iclass 38, count 0 2006.201.03:48:56.38#ibcon#about to read 3, iclass 38, count 0 2006.201.03:48:56.41#ibcon#read 3, iclass 38, count 0 2006.201.03:48:56.41#ibcon#about to read 4, iclass 38, count 0 2006.201.03:48:56.41#ibcon#read 4, iclass 38, count 0 2006.201.03:48:56.41#ibcon#about to read 5, iclass 38, count 0 2006.201.03:48:56.41#ibcon#read 5, iclass 38, count 0 2006.201.03:48:56.41#ibcon#about to read 6, iclass 38, count 0 2006.201.03:48:56.41#ibcon#read 6, iclass 38, count 0 2006.201.03:48:56.41#ibcon#end of sib2, iclass 38, count 0 2006.201.03:48:56.41#ibcon#*after write, iclass 38, count 0 2006.201.03:48:56.41#ibcon#*before return 0, iclass 38, count 0 2006.201.03:48:56.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:48:56.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:48:56.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:48:56.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:48:56.41$setupk4/ifdk4 2006.201.03:48:56.41$ifdk4/lo= 2006.201.03:48:56.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:48:56.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:48:56.41$ifdk4/patch= 2006.201.03:48:56.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:48:56.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:48:56.41$setupk4/!*+20s 2006.201.03:49:03.75#abcon#<5=/03 1.8 3.6 22.99 911004.4\r\n> 2006.201.03:49:03.77#abcon#{5=INTERFACE CLEAR} 2006.201.03:49:03.85#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:49:10.14#trakl#Source acquired 2006.201.03:49:10.91$setupk4/"tpicd 2006.201.03:49:10.91$setupk4/echo=off 2006.201.03:49:10.91$setupk4/xlog=off 2006.201.03:49:10.91:!2006.201.03:51:28 2006.201.03:49:11.14#flagr#flagr/antenna,acquired 2006.201.03:51:28.00:preob 2006.201.03:51:28.14/onsource/TRACKING 2006.201.03:51:28.14:!2006.201.03:51:38 2006.201.03:51:38.00:"tape 2006.201.03:51:38.00:"st=record 2006.201.03:51:38.00:data_valid=on 2006.201.03:51:38.00:midob 2006.201.03:51:38.14/onsource/TRACKING 2006.201.03:51:38.14/wx/22.96,1004.3,92 2006.201.03:51:38.32/cable/+6.4657E-03 2006.201.03:51:39.41/va/01,08,usb,yes,29,31 2006.201.03:51:39.41/va/02,07,usb,yes,31,32 2006.201.03:51:39.41/va/03,08,usb,yes,28,29 2006.201.03:51:39.41/va/04,07,usb,yes,32,34 2006.201.03:51:39.41/va/05,04,usb,yes,28,29 2006.201.03:51:39.41/va/06,05,usb,yes,28,28 2006.201.03:51:39.41/va/07,05,usb,yes,27,29 2006.201.03:51:39.41/va/08,04,usb,yes,27,33 2006.201.03:51:39.64/valo/01,524.99,yes,locked 2006.201.03:51:39.64/valo/02,534.99,yes,locked 2006.201.03:51:39.64/valo/03,564.99,yes,locked 2006.201.03:51:39.64/valo/04,624.99,yes,locked 2006.201.03:51:39.64/valo/05,734.99,yes,locked 2006.201.03:51:39.64/valo/06,814.99,yes,locked 2006.201.03:51:39.64/valo/07,864.99,yes,locked 2006.201.03:51:39.64/valo/08,884.99,yes,locked 2006.201.03:51:40.73/vb/01,04,usb,yes,29,27 2006.201.03:51:40.73/vb/02,05,usb,yes,27,27 2006.201.03:51:40.73/vb/03,04,usb,yes,28,31 2006.201.03:51:40.73/vb/04,05,usb,yes,29,28 2006.201.03:51:40.73/vb/05,04,usb,yes,25,28 2006.201.03:51:40.73/vb/06,04,usb,yes,29,26 2006.201.03:51:40.73/vb/07,04,usb,yes,29,29 2006.201.03:51:40.73/vb/08,04,usb,yes,27,30 2006.201.03:51:40.97/vblo/01,629.99,yes,locked 2006.201.03:51:40.97/vblo/02,634.99,yes,locked 2006.201.03:51:40.97/vblo/03,649.99,yes,locked 2006.201.03:51:40.97/vblo/04,679.99,yes,locked 2006.201.03:51:40.97/vblo/05,709.99,yes,locked 2006.201.03:51:40.97/vblo/06,719.99,yes,locked 2006.201.03:51:40.97/vblo/07,734.99,yes,locked 2006.201.03:51:40.97/vblo/08,744.99,yes,locked 2006.201.03:51:41.12/vabw/8 2006.201.03:51:41.27/vbbw/8 2006.201.03:51:41.36/xfe/off,on,15.0 2006.201.03:51:41.74/ifatt/23,28,28,28 2006.201.03:51:42.04/fmout-gps/S +4.56E-07 2006.201.03:51:42.11:!2006.201.03:52:38 2006.201.03:52:38.00:data_valid=off 2006.201.03:52:38.00:"et 2006.201.03:52:38.00:!+3s 2006.201.03:52:41.02:"tape 2006.201.03:52:41.02:postob 2006.201.03:52:41.15/cable/+6.4661E-03 2006.201.03:52:41.15/wx/22.95,1004.3,91 2006.201.03:52:41.22/fmout-gps/S +4.56E-07 2006.201.03:52:41.22:scan_name=201-0354,jd0607,130 2006.201.03:52:41.23:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.201.03:52:42.14#flagr#flagr/antenna,new-source 2006.201.03:52:42.14:checkk5 2006.201.03:52:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:52:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:52:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:52:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:52:44.02/chk_obsdata//k5ts1/T2010351??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.03:52:44.39/chk_obsdata//k5ts2/T2010351??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.03:52:44.77/chk_obsdata//k5ts3/T2010351??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.03:52:45.14/chk_obsdata//k5ts4/T2010351??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.03:52:45.83/k5log//k5ts1_log_newline 2006.201.03:52:46.52/k5log//k5ts2_log_newline 2006.201.03:52:47.21/k5log//k5ts3_log_newline 2006.201.03:52:47.90/k5log//k5ts4_log_newline 2006.201.03:52:47.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:52:47.92:setupk4=1 2006.201.03:52:47.92$setupk4/echo=on 2006.201.03:52:47.92$setupk4/pcalon 2006.201.03:52:47.92$pcalon/"no phase cal control is implemented here 2006.201.03:52:47.92$setupk4/"tpicd=stop 2006.201.03:52:47.92$setupk4/"rec=synch_on 2006.201.03:52:47.92$setupk4/"rec_mode=128 2006.201.03:52:47.92$setupk4/!* 2006.201.03:52:47.92$setupk4/recpk4 2006.201.03:52:47.92$recpk4/recpatch= 2006.201.03:52:47.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:52:47.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:52:47.93$setupk4/vck44 2006.201.03:52:47.93$vck44/valo=1,524.99 2006.201.03:52:47.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.03:52:47.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.03:52:47.93#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:47.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:47.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:47.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:47.93#ibcon#enter wrdev, iclass 27, count 0 2006.201.03:52:47.93#ibcon#first serial, iclass 27, count 0 2006.201.03:52:47.93#ibcon#enter sib2, iclass 27, count 0 2006.201.03:52:47.93#ibcon#flushed, iclass 27, count 0 2006.201.03:52:47.93#ibcon#about to write, iclass 27, count 0 2006.201.03:52:47.93#ibcon#wrote, iclass 27, count 0 2006.201.03:52:47.93#ibcon#about to read 3, iclass 27, count 0 2006.201.03:52:47.97#ibcon#read 3, iclass 27, count 0 2006.201.03:52:47.97#ibcon#about to read 4, iclass 27, count 0 2006.201.03:52:47.97#ibcon#read 4, iclass 27, count 0 2006.201.03:52:47.97#ibcon#about to read 5, iclass 27, count 0 2006.201.03:52:47.97#ibcon#read 5, iclass 27, count 0 2006.201.03:52:47.97#ibcon#about to read 6, iclass 27, count 0 2006.201.03:52:47.97#ibcon#read 6, iclass 27, count 0 2006.201.03:52:47.97#ibcon#end of sib2, iclass 27, count 0 2006.201.03:52:47.97#ibcon#*mode == 0, iclass 27, count 0 2006.201.03:52:47.97#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.03:52:47.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:52:47.97#ibcon#*before write, iclass 27, count 0 2006.201.03:52:47.97#ibcon#enter sib2, iclass 27, count 0 2006.201.03:52:47.97#ibcon#flushed, iclass 27, count 0 2006.201.03:52:47.97#ibcon#about to write, iclass 27, count 0 2006.201.03:52:47.97#ibcon#wrote, iclass 27, count 0 2006.201.03:52:47.97#ibcon#about to read 3, iclass 27, count 0 2006.201.03:52:48.02#ibcon#read 3, iclass 27, count 0 2006.201.03:52:48.02#ibcon#about to read 4, iclass 27, count 0 2006.201.03:52:48.02#ibcon#read 4, iclass 27, count 0 2006.201.03:52:48.02#ibcon#about to read 5, iclass 27, count 0 2006.201.03:52:48.02#ibcon#read 5, iclass 27, count 0 2006.201.03:52:48.02#ibcon#about to read 6, iclass 27, count 0 2006.201.03:52:48.02#ibcon#read 6, iclass 27, count 0 2006.201.03:52:48.02#ibcon#end of sib2, iclass 27, count 0 2006.201.03:52:48.02#ibcon#*after write, iclass 27, count 0 2006.201.03:52:48.02#ibcon#*before return 0, iclass 27, count 0 2006.201.03:52:48.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:48.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:48.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.03:52:48.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.03:52:48.02$vck44/va=1,8 2006.201.03:52:48.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.03:52:48.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.03:52:48.02#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:48.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:48.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:48.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:48.02#ibcon#enter wrdev, iclass 29, count 2 2006.201.03:52:48.02#ibcon#first serial, iclass 29, count 2 2006.201.03:52:48.02#ibcon#enter sib2, iclass 29, count 2 2006.201.03:52:48.02#ibcon#flushed, iclass 29, count 2 2006.201.03:52:48.02#ibcon#about to write, iclass 29, count 2 2006.201.03:52:48.02#ibcon#wrote, iclass 29, count 2 2006.201.03:52:48.02#ibcon#about to read 3, iclass 29, count 2 2006.201.03:52:48.04#ibcon#read 3, iclass 29, count 2 2006.201.03:52:48.04#ibcon#about to read 4, iclass 29, count 2 2006.201.03:52:48.04#ibcon#read 4, iclass 29, count 2 2006.201.03:52:48.04#ibcon#about to read 5, iclass 29, count 2 2006.201.03:52:48.04#ibcon#read 5, iclass 29, count 2 2006.201.03:52:48.04#ibcon#about to read 6, iclass 29, count 2 2006.201.03:52:48.04#ibcon#read 6, iclass 29, count 2 2006.201.03:52:48.04#ibcon#end of sib2, iclass 29, count 2 2006.201.03:52:48.04#ibcon#*mode == 0, iclass 29, count 2 2006.201.03:52:48.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.03:52:48.04#ibcon#[25=AT01-08\r\n] 2006.201.03:52:48.04#ibcon#*before write, iclass 29, count 2 2006.201.03:52:48.04#ibcon#enter sib2, iclass 29, count 2 2006.201.03:52:48.04#ibcon#flushed, iclass 29, count 2 2006.201.03:52:48.04#ibcon#about to write, iclass 29, count 2 2006.201.03:52:48.04#ibcon#wrote, iclass 29, count 2 2006.201.03:52:48.04#ibcon#about to read 3, iclass 29, count 2 2006.201.03:52:48.07#ibcon#read 3, iclass 29, count 2 2006.201.03:52:48.07#ibcon#about to read 4, iclass 29, count 2 2006.201.03:52:48.07#ibcon#read 4, iclass 29, count 2 2006.201.03:52:48.07#ibcon#about to read 5, iclass 29, count 2 2006.201.03:52:48.07#ibcon#read 5, iclass 29, count 2 2006.201.03:52:48.07#ibcon#about to read 6, iclass 29, count 2 2006.201.03:52:48.07#ibcon#read 6, iclass 29, count 2 2006.201.03:52:48.07#ibcon#end of sib2, iclass 29, count 2 2006.201.03:52:48.07#ibcon#*after write, iclass 29, count 2 2006.201.03:52:48.07#ibcon#*before return 0, iclass 29, count 2 2006.201.03:52:48.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:48.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:48.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.03:52:48.07#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:48.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:48.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:48.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:48.19#ibcon#enter wrdev, iclass 29, count 0 2006.201.03:52:48.19#ibcon#first serial, iclass 29, count 0 2006.201.03:52:48.19#ibcon#enter sib2, iclass 29, count 0 2006.201.03:52:48.19#ibcon#flushed, iclass 29, count 0 2006.201.03:52:48.19#ibcon#about to write, iclass 29, count 0 2006.201.03:52:48.19#ibcon#wrote, iclass 29, count 0 2006.201.03:52:48.19#ibcon#about to read 3, iclass 29, count 0 2006.201.03:52:48.21#ibcon#read 3, iclass 29, count 0 2006.201.03:52:48.21#ibcon#about to read 4, iclass 29, count 0 2006.201.03:52:48.21#ibcon#read 4, iclass 29, count 0 2006.201.03:52:48.21#ibcon#about to read 5, iclass 29, count 0 2006.201.03:52:48.21#ibcon#read 5, iclass 29, count 0 2006.201.03:52:48.21#ibcon#about to read 6, iclass 29, count 0 2006.201.03:52:48.21#ibcon#read 6, iclass 29, count 0 2006.201.03:52:48.21#ibcon#end of sib2, iclass 29, count 0 2006.201.03:52:48.21#ibcon#*mode == 0, iclass 29, count 0 2006.201.03:52:48.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.03:52:48.21#ibcon#[25=USB\r\n] 2006.201.03:52:48.21#ibcon#*before write, iclass 29, count 0 2006.201.03:52:48.21#ibcon#enter sib2, iclass 29, count 0 2006.201.03:52:48.21#ibcon#flushed, iclass 29, count 0 2006.201.03:52:48.21#ibcon#about to write, iclass 29, count 0 2006.201.03:52:48.21#ibcon#wrote, iclass 29, count 0 2006.201.03:52:48.21#ibcon#about to read 3, iclass 29, count 0 2006.201.03:52:48.24#ibcon#read 3, iclass 29, count 0 2006.201.03:52:48.24#ibcon#about to read 4, iclass 29, count 0 2006.201.03:52:48.24#ibcon#read 4, iclass 29, count 0 2006.201.03:52:48.24#ibcon#about to read 5, iclass 29, count 0 2006.201.03:52:48.24#ibcon#read 5, iclass 29, count 0 2006.201.03:52:48.24#ibcon#about to read 6, iclass 29, count 0 2006.201.03:52:48.24#ibcon#read 6, iclass 29, count 0 2006.201.03:52:48.24#ibcon#end of sib2, iclass 29, count 0 2006.201.03:52:48.24#ibcon#*after write, iclass 29, count 0 2006.201.03:52:48.24#ibcon#*before return 0, iclass 29, count 0 2006.201.03:52:48.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:48.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:48.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.03:52:48.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.03:52:48.24$vck44/valo=2,534.99 2006.201.03:52:48.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.03:52:48.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.03:52:48.24#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:48.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:48.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:48.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:48.24#ibcon#enter wrdev, iclass 31, count 0 2006.201.03:52:48.24#ibcon#first serial, iclass 31, count 0 2006.201.03:52:48.24#ibcon#enter sib2, iclass 31, count 0 2006.201.03:52:48.24#ibcon#flushed, iclass 31, count 0 2006.201.03:52:48.24#ibcon#about to write, iclass 31, count 0 2006.201.03:52:48.24#ibcon#wrote, iclass 31, count 0 2006.201.03:52:48.24#ibcon#about to read 3, iclass 31, count 0 2006.201.03:52:48.26#ibcon#read 3, iclass 31, count 0 2006.201.03:52:48.26#ibcon#about to read 4, iclass 31, count 0 2006.201.03:52:48.26#ibcon#read 4, iclass 31, count 0 2006.201.03:52:48.26#ibcon#about to read 5, iclass 31, count 0 2006.201.03:52:48.26#ibcon#read 5, iclass 31, count 0 2006.201.03:52:48.26#ibcon#about to read 6, iclass 31, count 0 2006.201.03:52:48.26#ibcon#read 6, iclass 31, count 0 2006.201.03:52:48.26#ibcon#end of sib2, iclass 31, count 0 2006.201.03:52:48.26#ibcon#*mode == 0, iclass 31, count 0 2006.201.03:52:48.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.03:52:48.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:52:48.26#ibcon#*before write, iclass 31, count 0 2006.201.03:52:48.26#ibcon#enter sib2, iclass 31, count 0 2006.201.03:52:48.26#ibcon#flushed, iclass 31, count 0 2006.201.03:52:48.26#ibcon#about to write, iclass 31, count 0 2006.201.03:52:48.26#ibcon#wrote, iclass 31, count 0 2006.201.03:52:48.26#ibcon#about to read 3, iclass 31, count 0 2006.201.03:52:48.30#ibcon#read 3, iclass 31, count 0 2006.201.03:52:48.30#ibcon#about to read 4, iclass 31, count 0 2006.201.03:52:48.30#ibcon#read 4, iclass 31, count 0 2006.201.03:52:48.30#ibcon#about to read 5, iclass 31, count 0 2006.201.03:52:48.30#ibcon#read 5, iclass 31, count 0 2006.201.03:52:48.30#ibcon#about to read 6, iclass 31, count 0 2006.201.03:52:48.30#ibcon#read 6, iclass 31, count 0 2006.201.03:52:48.30#ibcon#end of sib2, iclass 31, count 0 2006.201.03:52:48.30#ibcon#*after write, iclass 31, count 0 2006.201.03:52:48.30#ibcon#*before return 0, iclass 31, count 0 2006.201.03:52:48.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:48.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:48.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.03:52:48.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.03:52:48.30$vck44/va=2,7 2006.201.03:52:48.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.03:52:48.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.03:52:48.30#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:48.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:48.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:48.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:48.36#ibcon#enter wrdev, iclass 33, count 2 2006.201.03:52:48.36#ibcon#first serial, iclass 33, count 2 2006.201.03:52:48.36#ibcon#enter sib2, iclass 33, count 2 2006.201.03:52:48.36#ibcon#flushed, iclass 33, count 2 2006.201.03:52:48.36#ibcon#about to write, iclass 33, count 2 2006.201.03:52:48.36#ibcon#wrote, iclass 33, count 2 2006.201.03:52:48.36#ibcon#about to read 3, iclass 33, count 2 2006.201.03:52:48.38#ibcon#read 3, iclass 33, count 2 2006.201.03:52:48.38#ibcon#about to read 4, iclass 33, count 2 2006.201.03:52:48.38#ibcon#read 4, iclass 33, count 2 2006.201.03:52:48.38#ibcon#about to read 5, iclass 33, count 2 2006.201.03:52:48.38#ibcon#read 5, iclass 33, count 2 2006.201.03:52:48.38#ibcon#about to read 6, iclass 33, count 2 2006.201.03:52:48.38#ibcon#read 6, iclass 33, count 2 2006.201.03:52:48.38#ibcon#end of sib2, iclass 33, count 2 2006.201.03:52:48.38#ibcon#*mode == 0, iclass 33, count 2 2006.201.03:52:48.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.03:52:48.38#ibcon#[25=AT02-07\r\n] 2006.201.03:52:48.38#ibcon#*before write, iclass 33, count 2 2006.201.03:52:48.38#ibcon#enter sib2, iclass 33, count 2 2006.201.03:52:48.38#ibcon#flushed, iclass 33, count 2 2006.201.03:52:48.38#ibcon#about to write, iclass 33, count 2 2006.201.03:52:48.38#ibcon#wrote, iclass 33, count 2 2006.201.03:52:48.38#ibcon#about to read 3, iclass 33, count 2 2006.201.03:52:48.41#ibcon#read 3, iclass 33, count 2 2006.201.03:52:48.41#ibcon#about to read 4, iclass 33, count 2 2006.201.03:52:48.41#ibcon#read 4, iclass 33, count 2 2006.201.03:52:48.41#ibcon#about to read 5, iclass 33, count 2 2006.201.03:52:48.41#ibcon#read 5, iclass 33, count 2 2006.201.03:52:48.41#ibcon#about to read 6, iclass 33, count 2 2006.201.03:52:48.41#ibcon#read 6, iclass 33, count 2 2006.201.03:52:48.41#ibcon#end of sib2, iclass 33, count 2 2006.201.03:52:48.41#ibcon#*after write, iclass 33, count 2 2006.201.03:52:48.41#ibcon#*before return 0, iclass 33, count 2 2006.201.03:52:48.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:48.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:48.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.03:52:48.41#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:48.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:48.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:48.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:48.53#ibcon#enter wrdev, iclass 33, count 0 2006.201.03:52:48.53#ibcon#first serial, iclass 33, count 0 2006.201.03:52:48.53#ibcon#enter sib2, iclass 33, count 0 2006.201.03:52:48.53#ibcon#flushed, iclass 33, count 0 2006.201.03:52:48.53#ibcon#about to write, iclass 33, count 0 2006.201.03:52:48.53#ibcon#wrote, iclass 33, count 0 2006.201.03:52:48.53#ibcon#about to read 3, iclass 33, count 0 2006.201.03:52:48.55#ibcon#read 3, iclass 33, count 0 2006.201.03:52:48.55#ibcon#about to read 4, iclass 33, count 0 2006.201.03:52:48.55#ibcon#read 4, iclass 33, count 0 2006.201.03:52:48.55#ibcon#about to read 5, iclass 33, count 0 2006.201.03:52:48.55#ibcon#read 5, iclass 33, count 0 2006.201.03:52:48.55#ibcon#about to read 6, iclass 33, count 0 2006.201.03:52:48.55#ibcon#read 6, iclass 33, count 0 2006.201.03:52:48.55#ibcon#end of sib2, iclass 33, count 0 2006.201.03:52:48.55#ibcon#*mode == 0, iclass 33, count 0 2006.201.03:52:48.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.03:52:48.55#ibcon#[25=USB\r\n] 2006.201.03:52:48.55#ibcon#*before write, iclass 33, count 0 2006.201.03:52:48.55#ibcon#enter sib2, iclass 33, count 0 2006.201.03:52:48.55#ibcon#flushed, iclass 33, count 0 2006.201.03:52:48.55#ibcon#about to write, iclass 33, count 0 2006.201.03:52:48.55#ibcon#wrote, iclass 33, count 0 2006.201.03:52:48.55#ibcon#about to read 3, iclass 33, count 0 2006.201.03:52:48.58#ibcon#read 3, iclass 33, count 0 2006.201.03:52:48.58#ibcon#about to read 4, iclass 33, count 0 2006.201.03:52:48.58#ibcon#read 4, iclass 33, count 0 2006.201.03:52:48.58#ibcon#about to read 5, iclass 33, count 0 2006.201.03:52:48.58#ibcon#read 5, iclass 33, count 0 2006.201.03:52:48.58#ibcon#about to read 6, iclass 33, count 0 2006.201.03:52:48.58#ibcon#read 6, iclass 33, count 0 2006.201.03:52:48.58#ibcon#end of sib2, iclass 33, count 0 2006.201.03:52:48.58#ibcon#*after write, iclass 33, count 0 2006.201.03:52:48.58#ibcon#*before return 0, iclass 33, count 0 2006.201.03:52:48.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:48.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:48.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.03:52:48.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.03:52:48.58$vck44/valo=3,564.99 2006.201.03:52:48.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.03:52:48.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.03:52:48.58#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:48.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:48.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:48.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:48.58#ibcon#enter wrdev, iclass 35, count 0 2006.201.03:52:48.58#ibcon#first serial, iclass 35, count 0 2006.201.03:52:48.58#ibcon#enter sib2, iclass 35, count 0 2006.201.03:52:48.58#ibcon#flushed, iclass 35, count 0 2006.201.03:52:48.58#ibcon#about to write, iclass 35, count 0 2006.201.03:52:48.58#ibcon#wrote, iclass 35, count 0 2006.201.03:52:48.58#ibcon#about to read 3, iclass 35, count 0 2006.201.03:52:48.60#ibcon#read 3, iclass 35, count 0 2006.201.03:52:48.60#ibcon#about to read 4, iclass 35, count 0 2006.201.03:52:48.60#ibcon#read 4, iclass 35, count 0 2006.201.03:52:48.60#ibcon#about to read 5, iclass 35, count 0 2006.201.03:52:48.60#ibcon#read 5, iclass 35, count 0 2006.201.03:52:48.60#ibcon#about to read 6, iclass 35, count 0 2006.201.03:52:48.60#ibcon#read 6, iclass 35, count 0 2006.201.03:52:48.60#ibcon#end of sib2, iclass 35, count 0 2006.201.03:52:48.60#ibcon#*mode == 0, iclass 35, count 0 2006.201.03:52:48.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.03:52:48.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:52:48.60#ibcon#*before write, iclass 35, count 0 2006.201.03:52:48.60#ibcon#enter sib2, iclass 35, count 0 2006.201.03:52:48.60#ibcon#flushed, iclass 35, count 0 2006.201.03:52:48.60#ibcon#about to write, iclass 35, count 0 2006.201.03:52:48.60#ibcon#wrote, iclass 35, count 0 2006.201.03:52:48.60#ibcon#about to read 3, iclass 35, count 0 2006.201.03:52:48.65#ibcon#read 3, iclass 35, count 0 2006.201.03:52:48.65#ibcon#about to read 4, iclass 35, count 0 2006.201.03:52:48.65#ibcon#read 4, iclass 35, count 0 2006.201.03:52:48.65#ibcon#about to read 5, iclass 35, count 0 2006.201.03:52:48.65#ibcon#read 5, iclass 35, count 0 2006.201.03:52:48.65#ibcon#about to read 6, iclass 35, count 0 2006.201.03:52:48.65#ibcon#read 6, iclass 35, count 0 2006.201.03:52:48.65#ibcon#end of sib2, iclass 35, count 0 2006.201.03:52:48.65#ibcon#*after write, iclass 35, count 0 2006.201.03:52:48.65#ibcon#*before return 0, iclass 35, count 0 2006.201.03:52:48.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:48.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:48.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.03:52:48.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.03:52:48.65$vck44/va=3,8 2006.201.03:52:48.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.03:52:48.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.03:52:48.65#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:48.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:48.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:48.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:48.70#ibcon#enter wrdev, iclass 37, count 2 2006.201.03:52:48.70#ibcon#first serial, iclass 37, count 2 2006.201.03:52:48.70#ibcon#enter sib2, iclass 37, count 2 2006.201.03:52:48.70#ibcon#flushed, iclass 37, count 2 2006.201.03:52:48.70#ibcon#about to write, iclass 37, count 2 2006.201.03:52:48.70#ibcon#wrote, iclass 37, count 2 2006.201.03:52:48.70#ibcon#about to read 3, iclass 37, count 2 2006.201.03:52:48.72#ibcon#read 3, iclass 37, count 2 2006.201.03:52:48.72#ibcon#about to read 4, iclass 37, count 2 2006.201.03:52:48.72#ibcon#read 4, iclass 37, count 2 2006.201.03:52:48.72#ibcon#about to read 5, iclass 37, count 2 2006.201.03:52:48.72#ibcon#read 5, iclass 37, count 2 2006.201.03:52:48.72#ibcon#about to read 6, iclass 37, count 2 2006.201.03:52:48.72#ibcon#read 6, iclass 37, count 2 2006.201.03:52:48.72#ibcon#end of sib2, iclass 37, count 2 2006.201.03:52:48.72#ibcon#*mode == 0, iclass 37, count 2 2006.201.03:52:48.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.03:52:48.72#ibcon#[25=AT03-08\r\n] 2006.201.03:52:48.72#ibcon#*before write, iclass 37, count 2 2006.201.03:52:48.72#ibcon#enter sib2, iclass 37, count 2 2006.201.03:52:48.72#ibcon#flushed, iclass 37, count 2 2006.201.03:52:48.72#ibcon#about to write, iclass 37, count 2 2006.201.03:52:48.72#ibcon#wrote, iclass 37, count 2 2006.201.03:52:48.72#ibcon#about to read 3, iclass 37, count 2 2006.201.03:52:48.75#ibcon#read 3, iclass 37, count 2 2006.201.03:52:48.75#ibcon#about to read 4, iclass 37, count 2 2006.201.03:52:48.75#ibcon#read 4, iclass 37, count 2 2006.201.03:52:48.75#ibcon#about to read 5, iclass 37, count 2 2006.201.03:52:48.75#ibcon#read 5, iclass 37, count 2 2006.201.03:52:48.75#ibcon#about to read 6, iclass 37, count 2 2006.201.03:52:48.75#ibcon#read 6, iclass 37, count 2 2006.201.03:52:48.75#ibcon#end of sib2, iclass 37, count 2 2006.201.03:52:48.75#ibcon#*after write, iclass 37, count 2 2006.201.03:52:48.75#ibcon#*before return 0, iclass 37, count 2 2006.201.03:52:48.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:48.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:48.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.03:52:48.75#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:48.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:48.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:48.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:48.87#ibcon#enter wrdev, iclass 37, count 0 2006.201.03:52:48.87#ibcon#first serial, iclass 37, count 0 2006.201.03:52:48.87#ibcon#enter sib2, iclass 37, count 0 2006.201.03:52:48.87#ibcon#flushed, iclass 37, count 0 2006.201.03:52:48.87#ibcon#about to write, iclass 37, count 0 2006.201.03:52:48.87#ibcon#wrote, iclass 37, count 0 2006.201.03:52:48.87#ibcon#about to read 3, iclass 37, count 0 2006.201.03:52:48.89#ibcon#read 3, iclass 37, count 0 2006.201.03:52:48.89#ibcon#about to read 4, iclass 37, count 0 2006.201.03:52:48.89#ibcon#read 4, iclass 37, count 0 2006.201.03:52:48.89#ibcon#about to read 5, iclass 37, count 0 2006.201.03:52:48.89#ibcon#read 5, iclass 37, count 0 2006.201.03:52:48.89#ibcon#about to read 6, iclass 37, count 0 2006.201.03:52:48.89#ibcon#read 6, iclass 37, count 0 2006.201.03:52:48.89#ibcon#end of sib2, iclass 37, count 0 2006.201.03:52:48.89#ibcon#*mode == 0, iclass 37, count 0 2006.201.03:52:48.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.03:52:48.89#ibcon#[25=USB\r\n] 2006.201.03:52:48.89#ibcon#*before write, iclass 37, count 0 2006.201.03:52:48.89#ibcon#enter sib2, iclass 37, count 0 2006.201.03:52:48.89#ibcon#flushed, iclass 37, count 0 2006.201.03:52:48.89#ibcon#about to write, iclass 37, count 0 2006.201.03:52:48.89#ibcon#wrote, iclass 37, count 0 2006.201.03:52:48.89#ibcon#about to read 3, iclass 37, count 0 2006.201.03:52:48.92#ibcon#read 3, iclass 37, count 0 2006.201.03:52:48.92#ibcon#about to read 4, iclass 37, count 0 2006.201.03:52:48.92#ibcon#read 4, iclass 37, count 0 2006.201.03:52:48.92#ibcon#about to read 5, iclass 37, count 0 2006.201.03:52:48.92#ibcon#read 5, iclass 37, count 0 2006.201.03:52:48.92#ibcon#about to read 6, iclass 37, count 0 2006.201.03:52:48.92#ibcon#read 6, iclass 37, count 0 2006.201.03:52:48.92#ibcon#end of sib2, iclass 37, count 0 2006.201.03:52:48.92#ibcon#*after write, iclass 37, count 0 2006.201.03:52:48.92#ibcon#*before return 0, iclass 37, count 0 2006.201.03:52:48.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:48.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:48.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.03:52:48.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.03:52:48.92$vck44/valo=4,624.99 2006.201.03:52:48.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.03:52:48.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.03:52:48.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:48.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:48.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:48.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:48.92#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:52:48.92#ibcon#first serial, iclass 39, count 0 2006.201.03:52:48.92#ibcon#enter sib2, iclass 39, count 0 2006.201.03:52:48.92#ibcon#flushed, iclass 39, count 0 2006.201.03:52:48.92#ibcon#about to write, iclass 39, count 0 2006.201.03:52:48.92#ibcon#wrote, iclass 39, count 0 2006.201.03:52:48.92#ibcon#about to read 3, iclass 39, count 0 2006.201.03:52:48.94#ibcon#read 3, iclass 39, count 0 2006.201.03:52:48.94#ibcon#about to read 4, iclass 39, count 0 2006.201.03:52:48.94#ibcon#read 4, iclass 39, count 0 2006.201.03:52:48.94#ibcon#about to read 5, iclass 39, count 0 2006.201.03:52:48.94#ibcon#read 5, iclass 39, count 0 2006.201.03:52:48.94#ibcon#about to read 6, iclass 39, count 0 2006.201.03:52:48.94#ibcon#read 6, iclass 39, count 0 2006.201.03:52:48.94#ibcon#end of sib2, iclass 39, count 0 2006.201.03:52:48.94#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:52:48.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:52:48.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:52:48.94#ibcon#*before write, iclass 39, count 0 2006.201.03:52:48.94#ibcon#enter sib2, iclass 39, count 0 2006.201.03:52:48.94#ibcon#flushed, iclass 39, count 0 2006.201.03:52:48.94#ibcon#about to write, iclass 39, count 0 2006.201.03:52:48.94#ibcon#wrote, iclass 39, count 0 2006.201.03:52:48.94#ibcon#about to read 3, iclass 39, count 0 2006.201.03:52:48.99#ibcon#read 3, iclass 39, count 0 2006.201.03:52:48.99#ibcon#about to read 4, iclass 39, count 0 2006.201.03:52:48.99#ibcon#read 4, iclass 39, count 0 2006.201.03:52:48.99#ibcon#about to read 5, iclass 39, count 0 2006.201.03:52:48.99#ibcon#read 5, iclass 39, count 0 2006.201.03:52:48.99#ibcon#about to read 6, iclass 39, count 0 2006.201.03:52:48.99#ibcon#read 6, iclass 39, count 0 2006.201.03:52:48.99#ibcon#end of sib2, iclass 39, count 0 2006.201.03:52:48.99#ibcon#*after write, iclass 39, count 0 2006.201.03:52:48.99#ibcon#*before return 0, iclass 39, count 0 2006.201.03:52:48.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:48.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:48.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:52:48.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:52:48.99$vck44/va=4,7 2006.201.03:52:48.99#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.03:52:48.99#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.03:52:48.99#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:48.99#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:49.04#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:49.04#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:49.04#ibcon#enter wrdev, iclass 2, count 2 2006.201.03:52:49.04#ibcon#first serial, iclass 2, count 2 2006.201.03:52:49.04#ibcon#enter sib2, iclass 2, count 2 2006.201.03:52:49.04#ibcon#flushed, iclass 2, count 2 2006.201.03:52:49.04#ibcon#about to write, iclass 2, count 2 2006.201.03:52:49.04#ibcon#wrote, iclass 2, count 2 2006.201.03:52:49.04#ibcon#about to read 3, iclass 2, count 2 2006.201.03:52:49.06#ibcon#read 3, iclass 2, count 2 2006.201.03:52:49.06#ibcon#about to read 4, iclass 2, count 2 2006.201.03:52:49.06#ibcon#read 4, iclass 2, count 2 2006.201.03:52:49.06#ibcon#about to read 5, iclass 2, count 2 2006.201.03:52:49.06#ibcon#read 5, iclass 2, count 2 2006.201.03:52:49.06#ibcon#about to read 6, iclass 2, count 2 2006.201.03:52:49.06#ibcon#read 6, iclass 2, count 2 2006.201.03:52:49.06#ibcon#end of sib2, iclass 2, count 2 2006.201.03:52:49.06#ibcon#*mode == 0, iclass 2, count 2 2006.201.03:52:49.06#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.03:52:49.06#ibcon#[25=AT04-07\r\n] 2006.201.03:52:49.06#ibcon#*before write, iclass 2, count 2 2006.201.03:52:49.06#ibcon#enter sib2, iclass 2, count 2 2006.201.03:52:49.06#ibcon#flushed, iclass 2, count 2 2006.201.03:52:49.06#ibcon#about to write, iclass 2, count 2 2006.201.03:52:49.06#ibcon#wrote, iclass 2, count 2 2006.201.03:52:49.06#ibcon#about to read 3, iclass 2, count 2 2006.201.03:52:49.09#ibcon#read 3, iclass 2, count 2 2006.201.03:52:49.09#ibcon#about to read 4, iclass 2, count 2 2006.201.03:52:49.09#ibcon#read 4, iclass 2, count 2 2006.201.03:52:49.09#ibcon#about to read 5, iclass 2, count 2 2006.201.03:52:49.09#ibcon#read 5, iclass 2, count 2 2006.201.03:52:49.09#ibcon#about to read 6, iclass 2, count 2 2006.201.03:52:49.09#ibcon#read 6, iclass 2, count 2 2006.201.03:52:49.09#ibcon#end of sib2, iclass 2, count 2 2006.201.03:52:49.09#ibcon#*after write, iclass 2, count 2 2006.201.03:52:49.09#ibcon#*before return 0, iclass 2, count 2 2006.201.03:52:49.09#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:49.09#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:49.09#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.03:52:49.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:49.09#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:49.21#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:49.21#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:49.21#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:52:49.21#ibcon#first serial, iclass 2, count 0 2006.201.03:52:49.21#ibcon#enter sib2, iclass 2, count 0 2006.201.03:52:49.21#ibcon#flushed, iclass 2, count 0 2006.201.03:52:49.21#ibcon#about to write, iclass 2, count 0 2006.201.03:52:49.21#ibcon#wrote, iclass 2, count 0 2006.201.03:52:49.21#ibcon#about to read 3, iclass 2, count 0 2006.201.03:52:49.23#ibcon#read 3, iclass 2, count 0 2006.201.03:52:49.23#ibcon#about to read 4, iclass 2, count 0 2006.201.03:52:49.23#ibcon#read 4, iclass 2, count 0 2006.201.03:52:49.23#ibcon#about to read 5, iclass 2, count 0 2006.201.03:52:49.23#ibcon#read 5, iclass 2, count 0 2006.201.03:52:49.23#ibcon#about to read 6, iclass 2, count 0 2006.201.03:52:49.23#ibcon#read 6, iclass 2, count 0 2006.201.03:52:49.23#ibcon#end of sib2, iclass 2, count 0 2006.201.03:52:49.23#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:52:49.23#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:52:49.23#ibcon#[25=USB\r\n] 2006.201.03:52:49.23#ibcon#*before write, iclass 2, count 0 2006.201.03:52:49.23#ibcon#enter sib2, iclass 2, count 0 2006.201.03:52:49.23#ibcon#flushed, iclass 2, count 0 2006.201.03:52:49.23#ibcon#about to write, iclass 2, count 0 2006.201.03:52:49.23#ibcon#wrote, iclass 2, count 0 2006.201.03:52:49.23#ibcon#about to read 3, iclass 2, count 0 2006.201.03:52:49.26#ibcon#read 3, iclass 2, count 0 2006.201.03:52:49.26#ibcon#about to read 4, iclass 2, count 0 2006.201.03:52:49.26#ibcon#read 4, iclass 2, count 0 2006.201.03:52:49.26#ibcon#about to read 5, iclass 2, count 0 2006.201.03:52:49.26#ibcon#read 5, iclass 2, count 0 2006.201.03:52:49.26#ibcon#about to read 6, iclass 2, count 0 2006.201.03:52:49.26#ibcon#read 6, iclass 2, count 0 2006.201.03:52:49.26#ibcon#end of sib2, iclass 2, count 0 2006.201.03:52:49.26#ibcon#*after write, iclass 2, count 0 2006.201.03:52:49.26#ibcon#*before return 0, iclass 2, count 0 2006.201.03:52:49.26#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:49.26#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:49.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:52:49.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:52:49.26$vck44/valo=5,734.99 2006.201.03:52:49.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.03:52:49.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.03:52:49.26#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:49.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:49.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:49.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:49.26#ibcon#enter wrdev, iclass 5, count 0 2006.201.03:52:49.26#ibcon#first serial, iclass 5, count 0 2006.201.03:52:49.26#ibcon#enter sib2, iclass 5, count 0 2006.201.03:52:49.26#ibcon#flushed, iclass 5, count 0 2006.201.03:52:49.26#ibcon#about to write, iclass 5, count 0 2006.201.03:52:49.26#ibcon#wrote, iclass 5, count 0 2006.201.03:52:49.26#ibcon#about to read 3, iclass 5, count 0 2006.201.03:52:49.28#ibcon#read 3, iclass 5, count 0 2006.201.03:52:49.28#ibcon#about to read 4, iclass 5, count 0 2006.201.03:52:49.28#ibcon#read 4, iclass 5, count 0 2006.201.03:52:49.28#ibcon#about to read 5, iclass 5, count 0 2006.201.03:52:49.28#ibcon#read 5, iclass 5, count 0 2006.201.03:52:49.28#ibcon#about to read 6, iclass 5, count 0 2006.201.03:52:49.28#ibcon#read 6, iclass 5, count 0 2006.201.03:52:49.28#ibcon#end of sib2, iclass 5, count 0 2006.201.03:52:49.28#ibcon#*mode == 0, iclass 5, count 0 2006.201.03:52:49.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.03:52:49.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:52:49.28#ibcon#*before write, iclass 5, count 0 2006.201.03:52:49.28#ibcon#enter sib2, iclass 5, count 0 2006.201.03:52:49.28#ibcon#flushed, iclass 5, count 0 2006.201.03:52:49.28#ibcon#about to write, iclass 5, count 0 2006.201.03:52:49.28#ibcon#wrote, iclass 5, count 0 2006.201.03:52:49.28#ibcon#about to read 3, iclass 5, count 0 2006.201.03:52:49.32#ibcon#read 3, iclass 5, count 0 2006.201.03:52:49.32#ibcon#about to read 4, iclass 5, count 0 2006.201.03:52:49.32#ibcon#read 4, iclass 5, count 0 2006.201.03:52:49.32#ibcon#about to read 5, iclass 5, count 0 2006.201.03:52:49.32#ibcon#read 5, iclass 5, count 0 2006.201.03:52:49.32#ibcon#about to read 6, iclass 5, count 0 2006.201.03:52:49.32#ibcon#read 6, iclass 5, count 0 2006.201.03:52:49.32#ibcon#end of sib2, iclass 5, count 0 2006.201.03:52:49.32#ibcon#*after write, iclass 5, count 0 2006.201.03:52:49.32#ibcon#*before return 0, iclass 5, count 0 2006.201.03:52:49.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:49.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:49.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.03:52:49.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.03:52:49.32$vck44/va=5,4 2006.201.03:52:49.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.03:52:49.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.03:52:49.32#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:49.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:49.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:49.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:49.38#ibcon#enter wrdev, iclass 7, count 2 2006.201.03:52:49.38#ibcon#first serial, iclass 7, count 2 2006.201.03:52:49.38#ibcon#enter sib2, iclass 7, count 2 2006.201.03:52:49.38#ibcon#flushed, iclass 7, count 2 2006.201.03:52:49.38#ibcon#about to write, iclass 7, count 2 2006.201.03:52:49.38#ibcon#wrote, iclass 7, count 2 2006.201.03:52:49.38#ibcon#about to read 3, iclass 7, count 2 2006.201.03:52:49.40#ibcon#read 3, iclass 7, count 2 2006.201.03:52:49.40#ibcon#about to read 4, iclass 7, count 2 2006.201.03:52:49.40#ibcon#read 4, iclass 7, count 2 2006.201.03:52:49.40#ibcon#about to read 5, iclass 7, count 2 2006.201.03:52:49.40#ibcon#read 5, iclass 7, count 2 2006.201.03:52:49.40#ibcon#about to read 6, iclass 7, count 2 2006.201.03:52:49.40#ibcon#read 6, iclass 7, count 2 2006.201.03:52:49.40#ibcon#end of sib2, iclass 7, count 2 2006.201.03:52:49.40#ibcon#*mode == 0, iclass 7, count 2 2006.201.03:52:49.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.03:52:49.40#ibcon#[25=AT05-04\r\n] 2006.201.03:52:49.40#ibcon#*before write, iclass 7, count 2 2006.201.03:52:49.40#ibcon#enter sib2, iclass 7, count 2 2006.201.03:52:49.40#ibcon#flushed, iclass 7, count 2 2006.201.03:52:49.40#ibcon#about to write, iclass 7, count 2 2006.201.03:52:49.40#ibcon#wrote, iclass 7, count 2 2006.201.03:52:49.40#ibcon#about to read 3, iclass 7, count 2 2006.201.03:52:49.43#ibcon#read 3, iclass 7, count 2 2006.201.03:52:49.43#ibcon#about to read 4, iclass 7, count 2 2006.201.03:52:49.43#ibcon#read 4, iclass 7, count 2 2006.201.03:52:49.43#ibcon#about to read 5, iclass 7, count 2 2006.201.03:52:49.43#ibcon#read 5, iclass 7, count 2 2006.201.03:52:49.43#ibcon#about to read 6, iclass 7, count 2 2006.201.03:52:49.43#ibcon#read 6, iclass 7, count 2 2006.201.03:52:49.43#ibcon#end of sib2, iclass 7, count 2 2006.201.03:52:49.43#ibcon#*after write, iclass 7, count 2 2006.201.03:52:49.43#ibcon#*before return 0, iclass 7, count 2 2006.201.03:52:49.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:49.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:49.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.03:52:49.43#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:49.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:49.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:49.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:49.55#ibcon#enter wrdev, iclass 7, count 0 2006.201.03:52:49.55#ibcon#first serial, iclass 7, count 0 2006.201.03:52:49.55#ibcon#enter sib2, iclass 7, count 0 2006.201.03:52:49.55#ibcon#flushed, iclass 7, count 0 2006.201.03:52:49.55#ibcon#about to write, iclass 7, count 0 2006.201.03:52:49.55#ibcon#wrote, iclass 7, count 0 2006.201.03:52:49.55#ibcon#about to read 3, iclass 7, count 0 2006.201.03:52:49.57#ibcon#read 3, iclass 7, count 0 2006.201.03:52:49.57#ibcon#about to read 4, iclass 7, count 0 2006.201.03:52:49.57#ibcon#read 4, iclass 7, count 0 2006.201.03:52:49.57#ibcon#about to read 5, iclass 7, count 0 2006.201.03:52:49.57#ibcon#read 5, iclass 7, count 0 2006.201.03:52:49.57#ibcon#about to read 6, iclass 7, count 0 2006.201.03:52:49.57#ibcon#read 6, iclass 7, count 0 2006.201.03:52:49.57#ibcon#end of sib2, iclass 7, count 0 2006.201.03:52:49.57#ibcon#*mode == 0, iclass 7, count 0 2006.201.03:52:49.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.03:52:49.57#ibcon#[25=USB\r\n] 2006.201.03:52:49.57#ibcon#*before write, iclass 7, count 0 2006.201.03:52:49.57#ibcon#enter sib2, iclass 7, count 0 2006.201.03:52:49.57#ibcon#flushed, iclass 7, count 0 2006.201.03:52:49.57#ibcon#about to write, iclass 7, count 0 2006.201.03:52:49.57#ibcon#wrote, iclass 7, count 0 2006.201.03:52:49.57#ibcon#about to read 3, iclass 7, count 0 2006.201.03:52:49.60#ibcon#read 3, iclass 7, count 0 2006.201.03:52:49.60#ibcon#about to read 4, iclass 7, count 0 2006.201.03:52:49.60#ibcon#read 4, iclass 7, count 0 2006.201.03:52:49.60#ibcon#about to read 5, iclass 7, count 0 2006.201.03:52:49.60#ibcon#read 5, iclass 7, count 0 2006.201.03:52:49.60#ibcon#about to read 6, iclass 7, count 0 2006.201.03:52:49.60#ibcon#read 6, iclass 7, count 0 2006.201.03:52:49.60#ibcon#end of sib2, iclass 7, count 0 2006.201.03:52:49.60#ibcon#*after write, iclass 7, count 0 2006.201.03:52:49.60#ibcon#*before return 0, iclass 7, count 0 2006.201.03:52:49.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:49.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:49.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.03:52:49.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.03:52:49.60$vck44/valo=6,814.99 2006.201.03:52:49.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.03:52:49.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.03:52:49.60#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:49.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:49.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:49.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:49.60#ibcon#enter wrdev, iclass 11, count 0 2006.201.03:52:49.60#ibcon#first serial, iclass 11, count 0 2006.201.03:52:49.60#ibcon#enter sib2, iclass 11, count 0 2006.201.03:52:49.60#ibcon#flushed, iclass 11, count 0 2006.201.03:52:49.60#ibcon#about to write, iclass 11, count 0 2006.201.03:52:49.60#ibcon#wrote, iclass 11, count 0 2006.201.03:52:49.60#ibcon#about to read 3, iclass 11, count 0 2006.201.03:52:49.62#ibcon#read 3, iclass 11, count 0 2006.201.03:52:49.62#ibcon#about to read 4, iclass 11, count 0 2006.201.03:52:49.62#ibcon#read 4, iclass 11, count 0 2006.201.03:52:49.62#ibcon#about to read 5, iclass 11, count 0 2006.201.03:52:49.62#ibcon#read 5, iclass 11, count 0 2006.201.03:52:49.62#ibcon#about to read 6, iclass 11, count 0 2006.201.03:52:49.62#ibcon#read 6, iclass 11, count 0 2006.201.03:52:49.62#ibcon#end of sib2, iclass 11, count 0 2006.201.03:52:49.62#ibcon#*mode == 0, iclass 11, count 0 2006.201.03:52:49.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.03:52:49.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:52:49.62#ibcon#*before write, iclass 11, count 0 2006.201.03:52:49.62#ibcon#enter sib2, iclass 11, count 0 2006.201.03:52:49.62#ibcon#flushed, iclass 11, count 0 2006.201.03:52:49.62#ibcon#about to write, iclass 11, count 0 2006.201.03:52:49.62#ibcon#wrote, iclass 11, count 0 2006.201.03:52:49.62#ibcon#about to read 3, iclass 11, count 0 2006.201.03:52:49.66#ibcon#read 3, iclass 11, count 0 2006.201.03:52:49.66#ibcon#about to read 4, iclass 11, count 0 2006.201.03:52:49.66#ibcon#read 4, iclass 11, count 0 2006.201.03:52:49.66#ibcon#about to read 5, iclass 11, count 0 2006.201.03:52:49.66#ibcon#read 5, iclass 11, count 0 2006.201.03:52:49.66#ibcon#about to read 6, iclass 11, count 0 2006.201.03:52:49.66#ibcon#read 6, iclass 11, count 0 2006.201.03:52:49.66#ibcon#end of sib2, iclass 11, count 0 2006.201.03:52:49.66#ibcon#*after write, iclass 11, count 0 2006.201.03:52:49.66#ibcon#*before return 0, iclass 11, count 0 2006.201.03:52:49.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:49.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:49.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.03:52:49.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.03:52:49.66$vck44/va=6,5 2006.201.03:52:49.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.03:52:49.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.03:52:49.66#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:49.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:49.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:49.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:49.72#ibcon#enter wrdev, iclass 13, count 2 2006.201.03:52:49.72#ibcon#first serial, iclass 13, count 2 2006.201.03:52:49.72#ibcon#enter sib2, iclass 13, count 2 2006.201.03:52:49.72#ibcon#flushed, iclass 13, count 2 2006.201.03:52:49.72#ibcon#about to write, iclass 13, count 2 2006.201.03:52:49.72#ibcon#wrote, iclass 13, count 2 2006.201.03:52:49.72#ibcon#about to read 3, iclass 13, count 2 2006.201.03:52:49.74#ibcon#read 3, iclass 13, count 2 2006.201.03:52:49.74#ibcon#about to read 4, iclass 13, count 2 2006.201.03:52:49.74#ibcon#read 4, iclass 13, count 2 2006.201.03:52:49.74#ibcon#about to read 5, iclass 13, count 2 2006.201.03:52:49.74#ibcon#read 5, iclass 13, count 2 2006.201.03:52:49.74#ibcon#about to read 6, iclass 13, count 2 2006.201.03:52:49.74#ibcon#read 6, iclass 13, count 2 2006.201.03:52:49.74#ibcon#end of sib2, iclass 13, count 2 2006.201.03:52:49.74#ibcon#*mode == 0, iclass 13, count 2 2006.201.03:52:49.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.03:52:49.74#ibcon#[25=AT06-05\r\n] 2006.201.03:52:49.74#ibcon#*before write, iclass 13, count 2 2006.201.03:52:49.74#ibcon#enter sib2, iclass 13, count 2 2006.201.03:52:49.74#ibcon#flushed, iclass 13, count 2 2006.201.03:52:49.74#ibcon#about to write, iclass 13, count 2 2006.201.03:52:49.74#ibcon#wrote, iclass 13, count 2 2006.201.03:52:49.74#ibcon#about to read 3, iclass 13, count 2 2006.201.03:52:49.77#ibcon#read 3, iclass 13, count 2 2006.201.03:52:49.77#ibcon#about to read 4, iclass 13, count 2 2006.201.03:52:49.77#ibcon#read 4, iclass 13, count 2 2006.201.03:52:49.77#ibcon#about to read 5, iclass 13, count 2 2006.201.03:52:49.77#ibcon#read 5, iclass 13, count 2 2006.201.03:52:49.77#ibcon#about to read 6, iclass 13, count 2 2006.201.03:52:49.77#ibcon#read 6, iclass 13, count 2 2006.201.03:52:49.77#ibcon#end of sib2, iclass 13, count 2 2006.201.03:52:49.77#ibcon#*after write, iclass 13, count 2 2006.201.03:52:49.77#ibcon#*before return 0, iclass 13, count 2 2006.201.03:52:49.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:49.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:49.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.03:52:49.77#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:49.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:49.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:49.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:49.89#ibcon#enter wrdev, iclass 13, count 0 2006.201.03:52:49.89#ibcon#first serial, iclass 13, count 0 2006.201.03:52:49.89#ibcon#enter sib2, iclass 13, count 0 2006.201.03:52:49.89#ibcon#flushed, iclass 13, count 0 2006.201.03:52:49.89#ibcon#about to write, iclass 13, count 0 2006.201.03:52:49.89#ibcon#wrote, iclass 13, count 0 2006.201.03:52:49.89#ibcon#about to read 3, iclass 13, count 0 2006.201.03:52:49.91#ibcon#read 3, iclass 13, count 0 2006.201.03:52:49.91#ibcon#about to read 4, iclass 13, count 0 2006.201.03:52:49.91#ibcon#read 4, iclass 13, count 0 2006.201.03:52:49.91#ibcon#about to read 5, iclass 13, count 0 2006.201.03:52:49.91#ibcon#read 5, iclass 13, count 0 2006.201.03:52:49.91#ibcon#about to read 6, iclass 13, count 0 2006.201.03:52:49.91#ibcon#read 6, iclass 13, count 0 2006.201.03:52:49.91#ibcon#end of sib2, iclass 13, count 0 2006.201.03:52:49.91#ibcon#*mode == 0, iclass 13, count 0 2006.201.03:52:49.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.03:52:49.91#ibcon#[25=USB\r\n] 2006.201.03:52:49.91#ibcon#*before write, iclass 13, count 0 2006.201.03:52:49.91#ibcon#enter sib2, iclass 13, count 0 2006.201.03:52:49.91#ibcon#flushed, iclass 13, count 0 2006.201.03:52:49.91#ibcon#about to write, iclass 13, count 0 2006.201.03:52:49.91#ibcon#wrote, iclass 13, count 0 2006.201.03:52:49.91#ibcon#about to read 3, iclass 13, count 0 2006.201.03:52:49.94#ibcon#read 3, iclass 13, count 0 2006.201.03:52:49.94#ibcon#about to read 4, iclass 13, count 0 2006.201.03:52:49.94#ibcon#read 4, iclass 13, count 0 2006.201.03:52:49.94#ibcon#about to read 5, iclass 13, count 0 2006.201.03:52:49.94#ibcon#read 5, iclass 13, count 0 2006.201.03:52:49.94#ibcon#about to read 6, iclass 13, count 0 2006.201.03:52:49.94#ibcon#read 6, iclass 13, count 0 2006.201.03:52:49.94#ibcon#end of sib2, iclass 13, count 0 2006.201.03:52:49.94#ibcon#*after write, iclass 13, count 0 2006.201.03:52:49.94#ibcon#*before return 0, iclass 13, count 0 2006.201.03:52:49.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:49.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:49.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.03:52:49.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.03:52:49.94$vck44/valo=7,864.99 2006.201.03:52:49.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.03:52:49.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.03:52:49.94#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:49.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:49.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:49.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:49.94#ibcon#enter wrdev, iclass 15, count 0 2006.201.03:52:49.94#ibcon#first serial, iclass 15, count 0 2006.201.03:52:49.94#ibcon#enter sib2, iclass 15, count 0 2006.201.03:52:49.94#ibcon#flushed, iclass 15, count 0 2006.201.03:52:49.94#ibcon#about to write, iclass 15, count 0 2006.201.03:52:49.94#ibcon#wrote, iclass 15, count 0 2006.201.03:52:49.94#ibcon#about to read 3, iclass 15, count 0 2006.201.03:52:49.96#ibcon#read 3, iclass 15, count 0 2006.201.03:52:49.96#ibcon#about to read 4, iclass 15, count 0 2006.201.03:52:49.96#ibcon#read 4, iclass 15, count 0 2006.201.03:52:49.96#ibcon#about to read 5, iclass 15, count 0 2006.201.03:52:49.96#ibcon#read 5, iclass 15, count 0 2006.201.03:52:49.96#ibcon#about to read 6, iclass 15, count 0 2006.201.03:52:49.96#ibcon#read 6, iclass 15, count 0 2006.201.03:52:49.96#ibcon#end of sib2, iclass 15, count 0 2006.201.03:52:49.96#ibcon#*mode == 0, iclass 15, count 0 2006.201.03:52:49.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.03:52:49.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:52:49.96#ibcon#*before write, iclass 15, count 0 2006.201.03:52:49.96#ibcon#enter sib2, iclass 15, count 0 2006.201.03:52:49.96#ibcon#flushed, iclass 15, count 0 2006.201.03:52:49.96#ibcon#about to write, iclass 15, count 0 2006.201.03:52:49.96#ibcon#wrote, iclass 15, count 0 2006.201.03:52:49.96#ibcon#about to read 3, iclass 15, count 0 2006.201.03:52:50.00#ibcon#read 3, iclass 15, count 0 2006.201.03:52:50.00#ibcon#about to read 4, iclass 15, count 0 2006.201.03:52:50.00#ibcon#read 4, iclass 15, count 0 2006.201.03:52:50.00#ibcon#about to read 5, iclass 15, count 0 2006.201.03:52:50.00#ibcon#read 5, iclass 15, count 0 2006.201.03:52:50.00#ibcon#about to read 6, iclass 15, count 0 2006.201.03:52:50.00#ibcon#read 6, iclass 15, count 0 2006.201.03:52:50.00#ibcon#end of sib2, iclass 15, count 0 2006.201.03:52:50.00#ibcon#*after write, iclass 15, count 0 2006.201.03:52:50.00#ibcon#*before return 0, iclass 15, count 0 2006.201.03:52:50.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:50.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:50.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.03:52:50.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.03:52:50.00$vck44/va=7,5 2006.201.03:52:50.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.03:52:50.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.03:52:50.00#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:50.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:50.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:50.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:50.06#ibcon#enter wrdev, iclass 17, count 2 2006.201.03:52:50.06#ibcon#first serial, iclass 17, count 2 2006.201.03:52:50.06#ibcon#enter sib2, iclass 17, count 2 2006.201.03:52:50.06#ibcon#flushed, iclass 17, count 2 2006.201.03:52:50.06#ibcon#about to write, iclass 17, count 2 2006.201.03:52:50.06#ibcon#wrote, iclass 17, count 2 2006.201.03:52:50.06#ibcon#about to read 3, iclass 17, count 2 2006.201.03:52:50.08#ibcon#read 3, iclass 17, count 2 2006.201.03:52:50.08#ibcon#about to read 4, iclass 17, count 2 2006.201.03:52:50.08#ibcon#read 4, iclass 17, count 2 2006.201.03:52:50.08#ibcon#about to read 5, iclass 17, count 2 2006.201.03:52:50.08#ibcon#read 5, iclass 17, count 2 2006.201.03:52:50.08#ibcon#about to read 6, iclass 17, count 2 2006.201.03:52:50.08#ibcon#read 6, iclass 17, count 2 2006.201.03:52:50.08#ibcon#end of sib2, iclass 17, count 2 2006.201.03:52:50.08#ibcon#*mode == 0, iclass 17, count 2 2006.201.03:52:50.08#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.03:52:50.08#ibcon#[25=AT07-05\r\n] 2006.201.03:52:50.08#ibcon#*before write, iclass 17, count 2 2006.201.03:52:50.08#ibcon#enter sib2, iclass 17, count 2 2006.201.03:52:50.08#ibcon#flushed, iclass 17, count 2 2006.201.03:52:50.08#ibcon#about to write, iclass 17, count 2 2006.201.03:52:50.08#ibcon#wrote, iclass 17, count 2 2006.201.03:52:50.08#ibcon#about to read 3, iclass 17, count 2 2006.201.03:52:50.11#ibcon#read 3, iclass 17, count 2 2006.201.03:52:50.11#ibcon#about to read 4, iclass 17, count 2 2006.201.03:52:50.11#ibcon#read 4, iclass 17, count 2 2006.201.03:52:50.11#ibcon#about to read 5, iclass 17, count 2 2006.201.03:52:50.11#ibcon#read 5, iclass 17, count 2 2006.201.03:52:50.11#ibcon#about to read 6, iclass 17, count 2 2006.201.03:52:50.11#ibcon#read 6, iclass 17, count 2 2006.201.03:52:50.11#ibcon#end of sib2, iclass 17, count 2 2006.201.03:52:50.11#ibcon#*after write, iclass 17, count 2 2006.201.03:52:50.11#ibcon#*before return 0, iclass 17, count 2 2006.201.03:52:50.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:50.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:50.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.03:52:50.11#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:50.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:50.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:50.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:50.23#ibcon#enter wrdev, iclass 17, count 0 2006.201.03:52:50.23#ibcon#first serial, iclass 17, count 0 2006.201.03:52:50.23#ibcon#enter sib2, iclass 17, count 0 2006.201.03:52:50.23#ibcon#flushed, iclass 17, count 0 2006.201.03:52:50.23#ibcon#about to write, iclass 17, count 0 2006.201.03:52:50.23#ibcon#wrote, iclass 17, count 0 2006.201.03:52:50.23#ibcon#about to read 3, iclass 17, count 0 2006.201.03:52:50.25#ibcon#read 3, iclass 17, count 0 2006.201.03:52:50.25#ibcon#about to read 4, iclass 17, count 0 2006.201.03:52:50.25#ibcon#read 4, iclass 17, count 0 2006.201.03:52:50.25#ibcon#about to read 5, iclass 17, count 0 2006.201.03:52:50.25#ibcon#read 5, iclass 17, count 0 2006.201.03:52:50.25#ibcon#about to read 6, iclass 17, count 0 2006.201.03:52:50.25#ibcon#read 6, iclass 17, count 0 2006.201.03:52:50.25#ibcon#end of sib2, iclass 17, count 0 2006.201.03:52:50.25#ibcon#*mode == 0, iclass 17, count 0 2006.201.03:52:50.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.03:52:50.25#ibcon#[25=USB\r\n] 2006.201.03:52:50.25#ibcon#*before write, iclass 17, count 0 2006.201.03:52:50.25#ibcon#enter sib2, iclass 17, count 0 2006.201.03:52:50.25#ibcon#flushed, iclass 17, count 0 2006.201.03:52:50.25#ibcon#about to write, iclass 17, count 0 2006.201.03:52:50.25#ibcon#wrote, iclass 17, count 0 2006.201.03:52:50.25#ibcon#about to read 3, iclass 17, count 0 2006.201.03:52:50.28#ibcon#read 3, iclass 17, count 0 2006.201.03:52:50.28#ibcon#about to read 4, iclass 17, count 0 2006.201.03:52:50.28#ibcon#read 4, iclass 17, count 0 2006.201.03:52:50.28#ibcon#about to read 5, iclass 17, count 0 2006.201.03:52:50.28#ibcon#read 5, iclass 17, count 0 2006.201.03:52:50.28#ibcon#about to read 6, iclass 17, count 0 2006.201.03:52:50.28#ibcon#read 6, iclass 17, count 0 2006.201.03:52:50.28#ibcon#end of sib2, iclass 17, count 0 2006.201.03:52:50.28#ibcon#*after write, iclass 17, count 0 2006.201.03:52:50.28#ibcon#*before return 0, iclass 17, count 0 2006.201.03:52:50.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:50.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:50.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.03:52:50.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.03:52:50.28$vck44/valo=8,884.99 2006.201.03:52:50.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.03:52:50.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.03:52:50.28#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:50.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:50.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:50.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:50.28#ibcon#enter wrdev, iclass 19, count 0 2006.201.03:52:50.28#ibcon#first serial, iclass 19, count 0 2006.201.03:52:50.28#ibcon#enter sib2, iclass 19, count 0 2006.201.03:52:50.28#ibcon#flushed, iclass 19, count 0 2006.201.03:52:50.28#ibcon#about to write, iclass 19, count 0 2006.201.03:52:50.28#ibcon#wrote, iclass 19, count 0 2006.201.03:52:50.28#ibcon#about to read 3, iclass 19, count 0 2006.201.03:52:50.30#ibcon#read 3, iclass 19, count 0 2006.201.03:52:50.30#ibcon#about to read 4, iclass 19, count 0 2006.201.03:52:50.30#ibcon#read 4, iclass 19, count 0 2006.201.03:52:50.30#ibcon#about to read 5, iclass 19, count 0 2006.201.03:52:50.30#ibcon#read 5, iclass 19, count 0 2006.201.03:52:50.30#ibcon#about to read 6, iclass 19, count 0 2006.201.03:52:50.30#ibcon#read 6, iclass 19, count 0 2006.201.03:52:50.30#ibcon#end of sib2, iclass 19, count 0 2006.201.03:52:50.30#ibcon#*mode == 0, iclass 19, count 0 2006.201.03:52:50.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.03:52:50.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:52:50.30#ibcon#*before write, iclass 19, count 0 2006.201.03:52:50.30#ibcon#enter sib2, iclass 19, count 0 2006.201.03:52:50.30#ibcon#flushed, iclass 19, count 0 2006.201.03:52:50.30#ibcon#about to write, iclass 19, count 0 2006.201.03:52:50.30#ibcon#wrote, iclass 19, count 0 2006.201.03:52:50.30#ibcon#about to read 3, iclass 19, count 0 2006.201.03:52:50.35#ibcon#read 3, iclass 19, count 0 2006.201.03:52:50.35#ibcon#about to read 4, iclass 19, count 0 2006.201.03:52:50.35#ibcon#read 4, iclass 19, count 0 2006.201.03:52:50.35#ibcon#about to read 5, iclass 19, count 0 2006.201.03:52:50.35#ibcon#read 5, iclass 19, count 0 2006.201.03:52:50.35#ibcon#about to read 6, iclass 19, count 0 2006.201.03:52:50.35#ibcon#read 6, iclass 19, count 0 2006.201.03:52:50.35#ibcon#end of sib2, iclass 19, count 0 2006.201.03:52:50.35#ibcon#*after write, iclass 19, count 0 2006.201.03:52:50.35#ibcon#*before return 0, iclass 19, count 0 2006.201.03:52:50.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:50.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:50.35#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.03:52:50.35#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.03:52:50.35$vck44/va=8,4 2006.201.03:52:50.35#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.03:52:50.35#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.03:52:50.35#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:50.35#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:52:50.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:52:50.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:52:50.40#ibcon#enter wrdev, iclass 21, count 2 2006.201.03:52:50.40#ibcon#first serial, iclass 21, count 2 2006.201.03:52:50.40#ibcon#enter sib2, iclass 21, count 2 2006.201.03:52:50.40#ibcon#flushed, iclass 21, count 2 2006.201.03:52:50.40#ibcon#about to write, iclass 21, count 2 2006.201.03:52:50.40#ibcon#wrote, iclass 21, count 2 2006.201.03:52:50.40#ibcon#about to read 3, iclass 21, count 2 2006.201.03:52:50.42#ibcon#read 3, iclass 21, count 2 2006.201.03:52:50.42#ibcon#about to read 4, iclass 21, count 2 2006.201.03:52:50.42#ibcon#read 4, iclass 21, count 2 2006.201.03:52:50.42#ibcon#about to read 5, iclass 21, count 2 2006.201.03:52:50.42#ibcon#read 5, iclass 21, count 2 2006.201.03:52:50.42#ibcon#about to read 6, iclass 21, count 2 2006.201.03:52:50.42#ibcon#read 6, iclass 21, count 2 2006.201.03:52:50.42#ibcon#end of sib2, iclass 21, count 2 2006.201.03:52:50.42#ibcon#*mode == 0, iclass 21, count 2 2006.201.03:52:50.42#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.03:52:50.42#ibcon#[25=AT08-04\r\n] 2006.201.03:52:50.42#ibcon#*before write, iclass 21, count 2 2006.201.03:52:50.42#ibcon#enter sib2, iclass 21, count 2 2006.201.03:52:50.42#ibcon#flushed, iclass 21, count 2 2006.201.03:52:50.42#ibcon#about to write, iclass 21, count 2 2006.201.03:52:50.42#ibcon#wrote, iclass 21, count 2 2006.201.03:52:50.42#ibcon#about to read 3, iclass 21, count 2 2006.201.03:52:50.45#ibcon#read 3, iclass 21, count 2 2006.201.03:52:50.45#ibcon#about to read 4, iclass 21, count 2 2006.201.03:52:50.45#ibcon#read 4, iclass 21, count 2 2006.201.03:52:50.45#ibcon#about to read 5, iclass 21, count 2 2006.201.03:52:50.45#ibcon#read 5, iclass 21, count 2 2006.201.03:52:50.45#ibcon#about to read 6, iclass 21, count 2 2006.201.03:52:50.45#ibcon#read 6, iclass 21, count 2 2006.201.03:52:50.45#ibcon#end of sib2, iclass 21, count 2 2006.201.03:52:50.45#ibcon#*after write, iclass 21, count 2 2006.201.03:52:50.45#ibcon#*before return 0, iclass 21, count 2 2006.201.03:52:50.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:52:50.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.03:52:50.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.03:52:50.45#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:50.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:52:50.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:52:50.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:52:50.57#ibcon#enter wrdev, iclass 21, count 0 2006.201.03:52:50.57#ibcon#first serial, iclass 21, count 0 2006.201.03:52:50.57#ibcon#enter sib2, iclass 21, count 0 2006.201.03:52:50.57#ibcon#flushed, iclass 21, count 0 2006.201.03:52:50.57#ibcon#about to write, iclass 21, count 0 2006.201.03:52:50.57#ibcon#wrote, iclass 21, count 0 2006.201.03:52:50.57#ibcon#about to read 3, iclass 21, count 0 2006.201.03:52:50.59#ibcon#read 3, iclass 21, count 0 2006.201.03:52:50.59#ibcon#about to read 4, iclass 21, count 0 2006.201.03:52:50.59#ibcon#read 4, iclass 21, count 0 2006.201.03:52:50.59#ibcon#about to read 5, iclass 21, count 0 2006.201.03:52:50.59#ibcon#read 5, iclass 21, count 0 2006.201.03:52:50.59#ibcon#about to read 6, iclass 21, count 0 2006.201.03:52:50.59#ibcon#read 6, iclass 21, count 0 2006.201.03:52:50.59#ibcon#end of sib2, iclass 21, count 0 2006.201.03:52:50.59#ibcon#*mode == 0, iclass 21, count 0 2006.201.03:52:50.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.03:52:50.59#ibcon#[25=USB\r\n] 2006.201.03:52:50.59#ibcon#*before write, iclass 21, count 0 2006.201.03:52:50.59#ibcon#enter sib2, iclass 21, count 0 2006.201.03:52:50.59#ibcon#flushed, iclass 21, count 0 2006.201.03:52:50.59#ibcon#about to write, iclass 21, count 0 2006.201.03:52:50.59#ibcon#wrote, iclass 21, count 0 2006.201.03:52:50.59#ibcon#about to read 3, iclass 21, count 0 2006.201.03:52:50.62#ibcon#read 3, iclass 21, count 0 2006.201.03:52:50.62#ibcon#about to read 4, iclass 21, count 0 2006.201.03:52:50.62#ibcon#read 4, iclass 21, count 0 2006.201.03:52:50.62#ibcon#about to read 5, iclass 21, count 0 2006.201.03:52:50.62#ibcon#read 5, iclass 21, count 0 2006.201.03:52:50.62#ibcon#about to read 6, iclass 21, count 0 2006.201.03:52:50.62#ibcon#read 6, iclass 21, count 0 2006.201.03:52:50.62#ibcon#end of sib2, iclass 21, count 0 2006.201.03:52:50.62#ibcon#*after write, iclass 21, count 0 2006.201.03:52:50.62#ibcon#*before return 0, iclass 21, count 0 2006.201.03:52:50.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:52:50.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.03:52:50.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.03:52:50.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.03:52:50.62$vck44/vblo=1,629.99 2006.201.03:52:50.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.03:52:50.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.03:52:50.62#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:50.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:52:50.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:52:50.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:52:50.62#ibcon#enter wrdev, iclass 23, count 0 2006.201.03:52:50.62#ibcon#first serial, iclass 23, count 0 2006.201.03:52:50.62#ibcon#enter sib2, iclass 23, count 0 2006.201.03:52:50.62#ibcon#flushed, iclass 23, count 0 2006.201.03:52:50.62#ibcon#about to write, iclass 23, count 0 2006.201.03:52:50.62#ibcon#wrote, iclass 23, count 0 2006.201.03:52:50.62#ibcon#about to read 3, iclass 23, count 0 2006.201.03:52:50.64#ibcon#read 3, iclass 23, count 0 2006.201.03:52:50.64#ibcon#about to read 4, iclass 23, count 0 2006.201.03:52:50.64#ibcon#read 4, iclass 23, count 0 2006.201.03:52:50.64#ibcon#about to read 5, iclass 23, count 0 2006.201.03:52:50.64#ibcon#read 5, iclass 23, count 0 2006.201.03:52:50.64#ibcon#about to read 6, iclass 23, count 0 2006.201.03:52:50.64#ibcon#read 6, iclass 23, count 0 2006.201.03:52:50.64#ibcon#end of sib2, iclass 23, count 0 2006.201.03:52:50.64#ibcon#*mode == 0, iclass 23, count 0 2006.201.03:52:50.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.03:52:50.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:52:50.64#ibcon#*before write, iclass 23, count 0 2006.201.03:52:50.64#ibcon#enter sib2, iclass 23, count 0 2006.201.03:52:50.64#ibcon#flushed, iclass 23, count 0 2006.201.03:52:50.64#ibcon#about to write, iclass 23, count 0 2006.201.03:52:50.64#ibcon#wrote, iclass 23, count 0 2006.201.03:52:50.64#ibcon#about to read 3, iclass 23, count 0 2006.201.03:52:50.68#ibcon#read 3, iclass 23, count 0 2006.201.03:52:50.68#ibcon#about to read 4, iclass 23, count 0 2006.201.03:52:50.68#ibcon#read 4, iclass 23, count 0 2006.201.03:52:50.68#ibcon#about to read 5, iclass 23, count 0 2006.201.03:52:50.68#ibcon#read 5, iclass 23, count 0 2006.201.03:52:50.68#ibcon#about to read 6, iclass 23, count 0 2006.201.03:52:50.68#ibcon#read 6, iclass 23, count 0 2006.201.03:52:50.68#ibcon#end of sib2, iclass 23, count 0 2006.201.03:52:50.68#ibcon#*after write, iclass 23, count 0 2006.201.03:52:50.68#ibcon#*before return 0, iclass 23, count 0 2006.201.03:52:50.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:52:50.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.03:52:50.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.03:52:50.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.03:52:50.68$vck44/vb=1,4 2006.201.03:52:50.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.03:52:50.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.03:52:50.68#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:50.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:52:50.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:52:50.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:52:50.68#ibcon#enter wrdev, iclass 25, count 2 2006.201.03:52:50.68#ibcon#first serial, iclass 25, count 2 2006.201.03:52:50.68#ibcon#enter sib2, iclass 25, count 2 2006.201.03:52:50.68#ibcon#flushed, iclass 25, count 2 2006.201.03:52:50.68#ibcon#about to write, iclass 25, count 2 2006.201.03:52:50.68#ibcon#wrote, iclass 25, count 2 2006.201.03:52:50.68#ibcon#about to read 3, iclass 25, count 2 2006.201.03:52:50.70#ibcon#read 3, iclass 25, count 2 2006.201.03:52:50.70#ibcon#about to read 4, iclass 25, count 2 2006.201.03:52:50.70#ibcon#read 4, iclass 25, count 2 2006.201.03:52:50.70#ibcon#about to read 5, iclass 25, count 2 2006.201.03:52:50.70#ibcon#read 5, iclass 25, count 2 2006.201.03:52:50.70#ibcon#about to read 6, iclass 25, count 2 2006.201.03:52:50.70#ibcon#read 6, iclass 25, count 2 2006.201.03:52:50.70#ibcon#end of sib2, iclass 25, count 2 2006.201.03:52:50.70#ibcon#*mode == 0, iclass 25, count 2 2006.201.03:52:50.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.03:52:50.70#ibcon#[27=AT01-04\r\n] 2006.201.03:52:50.70#ibcon#*before write, iclass 25, count 2 2006.201.03:52:50.70#ibcon#enter sib2, iclass 25, count 2 2006.201.03:52:50.70#ibcon#flushed, iclass 25, count 2 2006.201.03:52:50.70#ibcon#about to write, iclass 25, count 2 2006.201.03:52:50.70#ibcon#wrote, iclass 25, count 2 2006.201.03:52:50.70#ibcon#about to read 3, iclass 25, count 2 2006.201.03:52:50.73#ibcon#read 3, iclass 25, count 2 2006.201.03:52:50.73#ibcon#about to read 4, iclass 25, count 2 2006.201.03:52:50.73#ibcon#read 4, iclass 25, count 2 2006.201.03:52:50.73#ibcon#about to read 5, iclass 25, count 2 2006.201.03:52:50.73#ibcon#read 5, iclass 25, count 2 2006.201.03:52:50.73#ibcon#about to read 6, iclass 25, count 2 2006.201.03:52:50.73#ibcon#read 6, iclass 25, count 2 2006.201.03:52:50.73#ibcon#end of sib2, iclass 25, count 2 2006.201.03:52:50.73#ibcon#*after write, iclass 25, count 2 2006.201.03:52:50.73#ibcon#*before return 0, iclass 25, count 2 2006.201.03:52:50.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:52:50.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.03:52:50.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.03:52:50.73#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:50.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:52:50.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:52:50.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:52:50.85#ibcon#enter wrdev, iclass 25, count 0 2006.201.03:52:50.85#ibcon#first serial, iclass 25, count 0 2006.201.03:52:50.85#ibcon#enter sib2, iclass 25, count 0 2006.201.03:52:50.85#ibcon#flushed, iclass 25, count 0 2006.201.03:52:50.85#ibcon#about to write, iclass 25, count 0 2006.201.03:52:50.85#ibcon#wrote, iclass 25, count 0 2006.201.03:52:50.85#ibcon#about to read 3, iclass 25, count 0 2006.201.03:52:50.87#ibcon#read 3, iclass 25, count 0 2006.201.03:52:50.87#ibcon#about to read 4, iclass 25, count 0 2006.201.03:52:50.87#ibcon#read 4, iclass 25, count 0 2006.201.03:52:50.87#ibcon#about to read 5, iclass 25, count 0 2006.201.03:52:50.87#ibcon#read 5, iclass 25, count 0 2006.201.03:52:50.87#ibcon#about to read 6, iclass 25, count 0 2006.201.03:52:50.87#ibcon#read 6, iclass 25, count 0 2006.201.03:52:50.87#ibcon#end of sib2, iclass 25, count 0 2006.201.03:52:50.87#ibcon#*mode == 0, iclass 25, count 0 2006.201.03:52:50.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.03:52:50.87#ibcon#[27=USB\r\n] 2006.201.03:52:50.87#ibcon#*before write, iclass 25, count 0 2006.201.03:52:50.87#ibcon#enter sib2, iclass 25, count 0 2006.201.03:52:50.87#ibcon#flushed, iclass 25, count 0 2006.201.03:52:50.87#ibcon#about to write, iclass 25, count 0 2006.201.03:52:50.87#ibcon#wrote, iclass 25, count 0 2006.201.03:52:50.87#ibcon#about to read 3, iclass 25, count 0 2006.201.03:52:50.90#ibcon#read 3, iclass 25, count 0 2006.201.03:52:50.90#ibcon#about to read 4, iclass 25, count 0 2006.201.03:52:50.90#ibcon#read 4, iclass 25, count 0 2006.201.03:52:50.90#ibcon#about to read 5, iclass 25, count 0 2006.201.03:52:50.90#ibcon#read 5, iclass 25, count 0 2006.201.03:52:50.90#ibcon#about to read 6, iclass 25, count 0 2006.201.03:52:50.90#ibcon#read 6, iclass 25, count 0 2006.201.03:52:50.90#ibcon#end of sib2, iclass 25, count 0 2006.201.03:52:50.90#ibcon#*after write, iclass 25, count 0 2006.201.03:52:50.90#ibcon#*before return 0, iclass 25, count 0 2006.201.03:52:50.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:52:50.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.03:52:50.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.03:52:50.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.03:52:50.90$vck44/vblo=2,634.99 2006.201.03:52:50.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.03:52:50.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.03:52:50.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:50.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:50.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:50.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:50.90#ibcon#enter wrdev, iclass 27, count 0 2006.201.03:52:50.90#ibcon#first serial, iclass 27, count 0 2006.201.03:52:50.90#ibcon#enter sib2, iclass 27, count 0 2006.201.03:52:50.90#ibcon#flushed, iclass 27, count 0 2006.201.03:52:50.90#ibcon#about to write, iclass 27, count 0 2006.201.03:52:50.90#ibcon#wrote, iclass 27, count 0 2006.201.03:52:50.90#ibcon#about to read 3, iclass 27, count 0 2006.201.03:52:50.92#ibcon#read 3, iclass 27, count 0 2006.201.03:52:50.92#ibcon#about to read 4, iclass 27, count 0 2006.201.03:52:50.92#ibcon#read 4, iclass 27, count 0 2006.201.03:52:50.92#ibcon#about to read 5, iclass 27, count 0 2006.201.03:52:50.92#ibcon#read 5, iclass 27, count 0 2006.201.03:52:50.92#ibcon#about to read 6, iclass 27, count 0 2006.201.03:52:50.92#ibcon#read 6, iclass 27, count 0 2006.201.03:52:50.92#ibcon#end of sib2, iclass 27, count 0 2006.201.03:52:50.92#ibcon#*mode == 0, iclass 27, count 0 2006.201.03:52:50.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.03:52:50.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:52:50.92#ibcon#*before write, iclass 27, count 0 2006.201.03:52:50.92#ibcon#enter sib2, iclass 27, count 0 2006.201.03:52:50.92#ibcon#flushed, iclass 27, count 0 2006.201.03:52:50.92#ibcon#about to write, iclass 27, count 0 2006.201.03:52:50.92#ibcon#wrote, iclass 27, count 0 2006.201.03:52:50.92#ibcon#about to read 3, iclass 27, count 0 2006.201.03:52:50.97#ibcon#read 3, iclass 27, count 0 2006.201.03:52:50.97#ibcon#about to read 4, iclass 27, count 0 2006.201.03:52:50.97#ibcon#read 4, iclass 27, count 0 2006.201.03:52:50.97#ibcon#about to read 5, iclass 27, count 0 2006.201.03:52:50.97#ibcon#read 5, iclass 27, count 0 2006.201.03:52:50.97#ibcon#about to read 6, iclass 27, count 0 2006.201.03:52:50.97#ibcon#read 6, iclass 27, count 0 2006.201.03:52:50.97#ibcon#end of sib2, iclass 27, count 0 2006.201.03:52:50.97#ibcon#*after write, iclass 27, count 0 2006.201.03:52:50.97#ibcon#*before return 0, iclass 27, count 0 2006.201.03:52:50.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:50.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.03:52:50.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.03:52:50.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.03:52:50.97$vck44/vb=2,5 2006.201.03:52:50.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.03:52:50.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.03:52:50.97#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:50.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:51.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:51.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:51.02#ibcon#enter wrdev, iclass 29, count 2 2006.201.03:52:51.02#ibcon#first serial, iclass 29, count 2 2006.201.03:52:51.02#ibcon#enter sib2, iclass 29, count 2 2006.201.03:52:51.02#ibcon#flushed, iclass 29, count 2 2006.201.03:52:51.02#ibcon#about to write, iclass 29, count 2 2006.201.03:52:51.02#ibcon#wrote, iclass 29, count 2 2006.201.03:52:51.02#ibcon#about to read 3, iclass 29, count 2 2006.201.03:52:51.04#ibcon#read 3, iclass 29, count 2 2006.201.03:52:51.04#ibcon#about to read 4, iclass 29, count 2 2006.201.03:52:51.04#ibcon#read 4, iclass 29, count 2 2006.201.03:52:51.04#ibcon#about to read 5, iclass 29, count 2 2006.201.03:52:51.04#ibcon#read 5, iclass 29, count 2 2006.201.03:52:51.04#ibcon#about to read 6, iclass 29, count 2 2006.201.03:52:51.04#ibcon#read 6, iclass 29, count 2 2006.201.03:52:51.04#ibcon#end of sib2, iclass 29, count 2 2006.201.03:52:51.04#ibcon#*mode == 0, iclass 29, count 2 2006.201.03:52:51.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.03:52:51.04#ibcon#[27=AT02-05\r\n] 2006.201.03:52:51.04#ibcon#*before write, iclass 29, count 2 2006.201.03:52:51.04#ibcon#enter sib2, iclass 29, count 2 2006.201.03:52:51.04#ibcon#flushed, iclass 29, count 2 2006.201.03:52:51.04#ibcon#about to write, iclass 29, count 2 2006.201.03:52:51.04#ibcon#wrote, iclass 29, count 2 2006.201.03:52:51.04#ibcon#about to read 3, iclass 29, count 2 2006.201.03:52:51.07#ibcon#read 3, iclass 29, count 2 2006.201.03:52:51.07#ibcon#about to read 4, iclass 29, count 2 2006.201.03:52:51.07#ibcon#read 4, iclass 29, count 2 2006.201.03:52:51.07#ibcon#about to read 5, iclass 29, count 2 2006.201.03:52:51.07#ibcon#read 5, iclass 29, count 2 2006.201.03:52:51.07#ibcon#about to read 6, iclass 29, count 2 2006.201.03:52:51.07#ibcon#read 6, iclass 29, count 2 2006.201.03:52:51.07#ibcon#end of sib2, iclass 29, count 2 2006.201.03:52:51.07#ibcon#*after write, iclass 29, count 2 2006.201.03:52:51.07#ibcon#*before return 0, iclass 29, count 2 2006.201.03:52:51.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:51.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.03:52:51.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.03:52:51.07#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:51.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:51.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:51.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:51.19#ibcon#enter wrdev, iclass 29, count 0 2006.201.03:52:51.19#ibcon#first serial, iclass 29, count 0 2006.201.03:52:51.19#ibcon#enter sib2, iclass 29, count 0 2006.201.03:52:51.19#ibcon#flushed, iclass 29, count 0 2006.201.03:52:51.19#ibcon#about to write, iclass 29, count 0 2006.201.03:52:51.19#ibcon#wrote, iclass 29, count 0 2006.201.03:52:51.19#ibcon#about to read 3, iclass 29, count 0 2006.201.03:52:51.21#ibcon#read 3, iclass 29, count 0 2006.201.03:52:51.21#ibcon#about to read 4, iclass 29, count 0 2006.201.03:52:51.21#ibcon#read 4, iclass 29, count 0 2006.201.03:52:51.21#ibcon#about to read 5, iclass 29, count 0 2006.201.03:52:51.21#ibcon#read 5, iclass 29, count 0 2006.201.03:52:51.21#ibcon#about to read 6, iclass 29, count 0 2006.201.03:52:51.21#ibcon#read 6, iclass 29, count 0 2006.201.03:52:51.21#ibcon#end of sib2, iclass 29, count 0 2006.201.03:52:51.21#ibcon#*mode == 0, iclass 29, count 0 2006.201.03:52:51.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.03:52:51.21#ibcon#[27=USB\r\n] 2006.201.03:52:51.21#ibcon#*before write, iclass 29, count 0 2006.201.03:52:51.21#ibcon#enter sib2, iclass 29, count 0 2006.201.03:52:51.21#ibcon#flushed, iclass 29, count 0 2006.201.03:52:51.21#ibcon#about to write, iclass 29, count 0 2006.201.03:52:51.21#ibcon#wrote, iclass 29, count 0 2006.201.03:52:51.21#ibcon#about to read 3, iclass 29, count 0 2006.201.03:52:51.24#ibcon#read 3, iclass 29, count 0 2006.201.03:52:51.24#ibcon#about to read 4, iclass 29, count 0 2006.201.03:52:51.24#ibcon#read 4, iclass 29, count 0 2006.201.03:52:51.24#ibcon#about to read 5, iclass 29, count 0 2006.201.03:52:51.24#ibcon#read 5, iclass 29, count 0 2006.201.03:52:51.24#ibcon#about to read 6, iclass 29, count 0 2006.201.03:52:51.24#ibcon#read 6, iclass 29, count 0 2006.201.03:52:51.24#ibcon#end of sib2, iclass 29, count 0 2006.201.03:52:51.24#ibcon#*after write, iclass 29, count 0 2006.201.03:52:51.24#ibcon#*before return 0, iclass 29, count 0 2006.201.03:52:51.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:51.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.03:52:51.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.03:52:51.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.03:52:51.24$vck44/vblo=3,649.99 2006.201.03:52:51.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.03:52:51.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.03:52:51.24#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:51.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:51.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:51.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:51.24#ibcon#enter wrdev, iclass 31, count 0 2006.201.03:52:51.24#ibcon#first serial, iclass 31, count 0 2006.201.03:52:51.24#ibcon#enter sib2, iclass 31, count 0 2006.201.03:52:51.24#ibcon#flushed, iclass 31, count 0 2006.201.03:52:51.24#ibcon#about to write, iclass 31, count 0 2006.201.03:52:51.24#ibcon#wrote, iclass 31, count 0 2006.201.03:52:51.24#ibcon#about to read 3, iclass 31, count 0 2006.201.03:52:51.26#ibcon#read 3, iclass 31, count 0 2006.201.03:52:51.26#ibcon#about to read 4, iclass 31, count 0 2006.201.03:52:51.26#ibcon#read 4, iclass 31, count 0 2006.201.03:52:51.26#ibcon#about to read 5, iclass 31, count 0 2006.201.03:52:51.26#ibcon#read 5, iclass 31, count 0 2006.201.03:52:51.26#ibcon#about to read 6, iclass 31, count 0 2006.201.03:52:51.26#ibcon#read 6, iclass 31, count 0 2006.201.03:52:51.26#ibcon#end of sib2, iclass 31, count 0 2006.201.03:52:51.26#ibcon#*mode == 0, iclass 31, count 0 2006.201.03:52:51.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.03:52:51.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:52:51.26#ibcon#*before write, iclass 31, count 0 2006.201.03:52:51.26#ibcon#enter sib2, iclass 31, count 0 2006.201.03:52:51.26#ibcon#flushed, iclass 31, count 0 2006.201.03:52:51.26#ibcon#about to write, iclass 31, count 0 2006.201.03:52:51.26#ibcon#wrote, iclass 31, count 0 2006.201.03:52:51.26#ibcon#about to read 3, iclass 31, count 0 2006.201.03:52:51.30#ibcon#read 3, iclass 31, count 0 2006.201.03:52:51.30#ibcon#about to read 4, iclass 31, count 0 2006.201.03:52:51.30#ibcon#read 4, iclass 31, count 0 2006.201.03:52:51.30#ibcon#about to read 5, iclass 31, count 0 2006.201.03:52:51.30#ibcon#read 5, iclass 31, count 0 2006.201.03:52:51.30#ibcon#about to read 6, iclass 31, count 0 2006.201.03:52:51.30#ibcon#read 6, iclass 31, count 0 2006.201.03:52:51.30#ibcon#end of sib2, iclass 31, count 0 2006.201.03:52:51.30#ibcon#*after write, iclass 31, count 0 2006.201.03:52:51.30#ibcon#*before return 0, iclass 31, count 0 2006.201.03:52:51.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:51.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.03:52:51.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.03:52:51.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.03:52:51.30$vck44/vb=3,4 2006.201.03:52:51.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.03:52:51.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.03:52:51.30#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:51.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:51.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:51.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:51.36#ibcon#enter wrdev, iclass 33, count 2 2006.201.03:52:51.36#ibcon#first serial, iclass 33, count 2 2006.201.03:52:51.36#ibcon#enter sib2, iclass 33, count 2 2006.201.03:52:51.36#ibcon#flushed, iclass 33, count 2 2006.201.03:52:51.36#ibcon#about to write, iclass 33, count 2 2006.201.03:52:51.36#ibcon#wrote, iclass 33, count 2 2006.201.03:52:51.36#ibcon#about to read 3, iclass 33, count 2 2006.201.03:52:51.38#ibcon#read 3, iclass 33, count 2 2006.201.03:52:51.38#ibcon#about to read 4, iclass 33, count 2 2006.201.03:52:51.38#ibcon#read 4, iclass 33, count 2 2006.201.03:52:51.38#ibcon#about to read 5, iclass 33, count 2 2006.201.03:52:51.38#ibcon#read 5, iclass 33, count 2 2006.201.03:52:51.38#ibcon#about to read 6, iclass 33, count 2 2006.201.03:52:51.38#ibcon#read 6, iclass 33, count 2 2006.201.03:52:51.38#ibcon#end of sib2, iclass 33, count 2 2006.201.03:52:51.38#ibcon#*mode == 0, iclass 33, count 2 2006.201.03:52:51.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.03:52:51.38#ibcon#[27=AT03-04\r\n] 2006.201.03:52:51.38#ibcon#*before write, iclass 33, count 2 2006.201.03:52:51.38#ibcon#enter sib2, iclass 33, count 2 2006.201.03:52:51.38#ibcon#flushed, iclass 33, count 2 2006.201.03:52:51.38#ibcon#about to write, iclass 33, count 2 2006.201.03:52:51.38#ibcon#wrote, iclass 33, count 2 2006.201.03:52:51.38#ibcon#about to read 3, iclass 33, count 2 2006.201.03:52:51.41#ibcon#read 3, iclass 33, count 2 2006.201.03:52:51.41#ibcon#about to read 4, iclass 33, count 2 2006.201.03:52:51.41#ibcon#read 4, iclass 33, count 2 2006.201.03:52:51.41#ibcon#about to read 5, iclass 33, count 2 2006.201.03:52:51.41#ibcon#read 5, iclass 33, count 2 2006.201.03:52:51.41#ibcon#about to read 6, iclass 33, count 2 2006.201.03:52:51.41#ibcon#read 6, iclass 33, count 2 2006.201.03:52:51.41#ibcon#end of sib2, iclass 33, count 2 2006.201.03:52:51.41#ibcon#*after write, iclass 33, count 2 2006.201.03:52:51.41#ibcon#*before return 0, iclass 33, count 2 2006.201.03:52:51.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:51.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.03:52:51.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.03:52:51.41#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:51.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:51.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:51.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:51.53#ibcon#enter wrdev, iclass 33, count 0 2006.201.03:52:51.53#ibcon#first serial, iclass 33, count 0 2006.201.03:52:51.53#ibcon#enter sib2, iclass 33, count 0 2006.201.03:52:51.53#ibcon#flushed, iclass 33, count 0 2006.201.03:52:51.53#ibcon#about to write, iclass 33, count 0 2006.201.03:52:51.53#ibcon#wrote, iclass 33, count 0 2006.201.03:52:51.53#ibcon#about to read 3, iclass 33, count 0 2006.201.03:52:51.55#ibcon#read 3, iclass 33, count 0 2006.201.03:52:51.55#ibcon#about to read 4, iclass 33, count 0 2006.201.03:52:51.55#ibcon#read 4, iclass 33, count 0 2006.201.03:52:51.55#ibcon#about to read 5, iclass 33, count 0 2006.201.03:52:51.55#ibcon#read 5, iclass 33, count 0 2006.201.03:52:51.55#ibcon#about to read 6, iclass 33, count 0 2006.201.03:52:51.55#ibcon#read 6, iclass 33, count 0 2006.201.03:52:51.55#ibcon#end of sib2, iclass 33, count 0 2006.201.03:52:51.55#ibcon#*mode == 0, iclass 33, count 0 2006.201.03:52:51.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.03:52:51.55#ibcon#[27=USB\r\n] 2006.201.03:52:51.55#ibcon#*before write, iclass 33, count 0 2006.201.03:52:51.55#ibcon#enter sib2, iclass 33, count 0 2006.201.03:52:51.55#ibcon#flushed, iclass 33, count 0 2006.201.03:52:51.55#ibcon#about to write, iclass 33, count 0 2006.201.03:52:51.55#ibcon#wrote, iclass 33, count 0 2006.201.03:52:51.55#ibcon#about to read 3, iclass 33, count 0 2006.201.03:52:51.58#ibcon#read 3, iclass 33, count 0 2006.201.03:52:51.58#ibcon#about to read 4, iclass 33, count 0 2006.201.03:52:51.58#ibcon#read 4, iclass 33, count 0 2006.201.03:52:51.58#ibcon#about to read 5, iclass 33, count 0 2006.201.03:52:51.58#ibcon#read 5, iclass 33, count 0 2006.201.03:52:51.58#ibcon#about to read 6, iclass 33, count 0 2006.201.03:52:51.58#ibcon#read 6, iclass 33, count 0 2006.201.03:52:51.58#ibcon#end of sib2, iclass 33, count 0 2006.201.03:52:51.58#ibcon#*after write, iclass 33, count 0 2006.201.03:52:51.58#ibcon#*before return 0, iclass 33, count 0 2006.201.03:52:51.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:51.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.03:52:51.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.03:52:51.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.03:52:51.58$vck44/vblo=4,679.99 2006.201.03:52:51.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.03:52:51.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.03:52:51.58#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:51.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:51.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:51.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:51.58#ibcon#enter wrdev, iclass 35, count 0 2006.201.03:52:51.58#ibcon#first serial, iclass 35, count 0 2006.201.03:52:51.58#ibcon#enter sib2, iclass 35, count 0 2006.201.03:52:51.58#ibcon#flushed, iclass 35, count 0 2006.201.03:52:51.58#ibcon#about to write, iclass 35, count 0 2006.201.03:52:51.58#ibcon#wrote, iclass 35, count 0 2006.201.03:52:51.58#ibcon#about to read 3, iclass 35, count 0 2006.201.03:52:51.60#ibcon#read 3, iclass 35, count 0 2006.201.03:52:51.60#ibcon#about to read 4, iclass 35, count 0 2006.201.03:52:51.60#ibcon#read 4, iclass 35, count 0 2006.201.03:52:51.60#ibcon#about to read 5, iclass 35, count 0 2006.201.03:52:51.60#ibcon#read 5, iclass 35, count 0 2006.201.03:52:51.60#ibcon#about to read 6, iclass 35, count 0 2006.201.03:52:51.60#ibcon#read 6, iclass 35, count 0 2006.201.03:52:51.60#ibcon#end of sib2, iclass 35, count 0 2006.201.03:52:51.60#ibcon#*mode == 0, iclass 35, count 0 2006.201.03:52:51.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.03:52:51.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:52:51.60#ibcon#*before write, iclass 35, count 0 2006.201.03:52:51.60#ibcon#enter sib2, iclass 35, count 0 2006.201.03:52:51.60#ibcon#flushed, iclass 35, count 0 2006.201.03:52:51.60#ibcon#about to write, iclass 35, count 0 2006.201.03:52:51.60#ibcon#wrote, iclass 35, count 0 2006.201.03:52:51.60#ibcon#about to read 3, iclass 35, count 0 2006.201.03:52:51.64#ibcon#read 3, iclass 35, count 0 2006.201.03:52:51.64#ibcon#about to read 4, iclass 35, count 0 2006.201.03:52:51.64#ibcon#read 4, iclass 35, count 0 2006.201.03:52:51.64#ibcon#about to read 5, iclass 35, count 0 2006.201.03:52:51.64#ibcon#read 5, iclass 35, count 0 2006.201.03:52:51.64#ibcon#about to read 6, iclass 35, count 0 2006.201.03:52:51.64#ibcon#read 6, iclass 35, count 0 2006.201.03:52:51.64#ibcon#end of sib2, iclass 35, count 0 2006.201.03:52:51.64#ibcon#*after write, iclass 35, count 0 2006.201.03:52:51.64#ibcon#*before return 0, iclass 35, count 0 2006.201.03:52:51.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:51.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.03:52:51.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.03:52:51.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.03:52:51.64$vck44/vb=4,5 2006.201.03:52:51.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.03:52:51.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.03:52:51.64#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:51.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:51.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:51.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:51.70#ibcon#enter wrdev, iclass 37, count 2 2006.201.03:52:51.70#ibcon#first serial, iclass 37, count 2 2006.201.03:52:51.70#ibcon#enter sib2, iclass 37, count 2 2006.201.03:52:51.70#ibcon#flushed, iclass 37, count 2 2006.201.03:52:51.70#ibcon#about to write, iclass 37, count 2 2006.201.03:52:51.70#ibcon#wrote, iclass 37, count 2 2006.201.03:52:51.70#ibcon#about to read 3, iclass 37, count 2 2006.201.03:52:51.72#ibcon#read 3, iclass 37, count 2 2006.201.03:52:51.72#ibcon#about to read 4, iclass 37, count 2 2006.201.03:52:51.72#ibcon#read 4, iclass 37, count 2 2006.201.03:52:51.72#ibcon#about to read 5, iclass 37, count 2 2006.201.03:52:51.72#ibcon#read 5, iclass 37, count 2 2006.201.03:52:51.72#ibcon#about to read 6, iclass 37, count 2 2006.201.03:52:51.72#ibcon#read 6, iclass 37, count 2 2006.201.03:52:51.72#ibcon#end of sib2, iclass 37, count 2 2006.201.03:52:51.72#ibcon#*mode == 0, iclass 37, count 2 2006.201.03:52:51.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.03:52:51.72#ibcon#[27=AT04-05\r\n] 2006.201.03:52:51.72#ibcon#*before write, iclass 37, count 2 2006.201.03:52:51.72#ibcon#enter sib2, iclass 37, count 2 2006.201.03:52:51.72#ibcon#flushed, iclass 37, count 2 2006.201.03:52:51.72#ibcon#about to write, iclass 37, count 2 2006.201.03:52:51.72#ibcon#wrote, iclass 37, count 2 2006.201.03:52:51.72#ibcon#about to read 3, iclass 37, count 2 2006.201.03:52:51.75#ibcon#read 3, iclass 37, count 2 2006.201.03:52:51.75#ibcon#about to read 4, iclass 37, count 2 2006.201.03:52:51.75#ibcon#read 4, iclass 37, count 2 2006.201.03:52:51.75#ibcon#about to read 5, iclass 37, count 2 2006.201.03:52:51.75#ibcon#read 5, iclass 37, count 2 2006.201.03:52:51.75#ibcon#about to read 6, iclass 37, count 2 2006.201.03:52:51.75#ibcon#read 6, iclass 37, count 2 2006.201.03:52:51.75#ibcon#end of sib2, iclass 37, count 2 2006.201.03:52:51.75#ibcon#*after write, iclass 37, count 2 2006.201.03:52:51.75#ibcon#*before return 0, iclass 37, count 2 2006.201.03:52:51.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:51.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.03:52:51.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.03:52:51.75#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:51.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:51.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:51.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:51.87#ibcon#enter wrdev, iclass 37, count 0 2006.201.03:52:51.87#ibcon#first serial, iclass 37, count 0 2006.201.03:52:51.87#ibcon#enter sib2, iclass 37, count 0 2006.201.03:52:51.87#ibcon#flushed, iclass 37, count 0 2006.201.03:52:51.87#ibcon#about to write, iclass 37, count 0 2006.201.03:52:51.87#ibcon#wrote, iclass 37, count 0 2006.201.03:52:51.87#ibcon#about to read 3, iclass 37, count 0 2006.201.03:52:51.89#ibcon#read 3, iclass 37, count 0 2006.201.03:52:51.89#ibcon#about to read 4, iclass 37, count 0 2006.201.03:52:51.89#ibcon#read 4, iclass 37, count 0 2006.201.03:52:51.89#ibcon#about to read 5, iclass 37, count 0 2006.201.03:52:51.89#ibcon#read 5, iclass 37, count 0 2006.201.03:52:51.89#ibcon#about to read 6, iclass 37, count 0 2006.201.03:52:51.89#ibcon#read 6, iclass 37, count 0 2006.201.03:52:51.89#ibcon#end of sib2, iclass 37, count 0 2006.201.03:52:51.89#ibcon#*mode == 0, iclass 37, count 0 2006.201.03:52:51.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.03:52:51.89#ibcon#[27=USB\r\n] 2006.201.03:52:51.89#ibcon#*before write, iclass 37, count 0 2006.201.03:52:51.89#ibcon#enter sib2, iclass 37, count 0 2006.201.03:52:51.89#ibcon#flushed, iclass 37, count 0 2006.201.03:52:51.89#ibcon#about to write, iclass 37, count 0 2006.201.03:52:51.89#ibcon#wrote, iclass 37, count 0 2006.201.03:52:51.89#ibcon#about to read 3, iclass 37, count 0 2006.201.03:52:51.92#ibcon#read 3, iclass 37, count 0 2006.201.03:52:51.92#ibcon#about to read 4, iclass 37, count 0 2006.201.03:52:51.92#ibcon#read 4, iclass 37, count 0 2006.201.03:52:51.92#ibcon#about to read 5, iclass 37, count 0 2006.201.03:52:51.92#ibcon#read 5, iclass 37, count 0 2006.201.03:52:51.92#ibcon#about to read 6, iclass 37, count 0 2006.201.03:52:51.92#ibcon#read 6, iclass 37, count 0 2006.201.03:52:51.92#ibcon#end of sib2, iclass 37, count 0 2006.201.03:52:51.92#ibcon#*after write, iclass 37, count 0 2006.201.03:52:51.92#ibcon#*before return 0, iclass 37, count 0 2006.201.03:52:51.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:51.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.03:52:51.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.03:52:51.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.03:52:51.92$vck44/vblo=5,709.99 2006.201.03:52:51.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.03:52:51.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.03:52:51.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:51.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:51.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:51.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:51.92#ibcon#enter wrdev, iclass 39, count 0 2006.201.03:52:51.92#ibcon#first serial, iclass 39, count 0 2006.201.03:52:51.92#ibcon#enter sib2, iclass 39, count 0 2006.201.03:52:51.92#ibcon#flushed, iclass 39, count 0 2006.201.03:52:51.92#ibcon#about to write, iclass 39, count 0 2006.201.03:52:51.92#ibcon#wrote, iclass 39, count 0 2006.201.03:52:51.92#ibcon#about to read 3, iclass 39, count 0 2006.201.03:52:51.94#ibcon#read 3, iclass 39, count 0 2006.201.03:52:51.94#ibcon#about to read 4, iclass 39, count 0 2006.201.03:52:51.94#ibcon#read 4, iclass 39, count 0 2006.201.03:52:51.94#ibcon#about to read 5, iclass 39, count 0 2006.201.03:52:51.94#ibcon#read 5, iclass 39, count 0 2006.201.03:52:51.94#ibcon#about to read 6, iclass 39, count 0 2006.201.03:52:51.94#ibcon#read 6, iclass 39, count 0 2006.201.03:52:51.94#ibcon#end of sib2, iclass 39, count 0 2006.201.03:52:51.94#ibcon#*mode == 0, iclass 39, count 0 2006.201.03:52:51.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.03:52:51.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:52:51.94#ibcon#*before write, iclass 39, count 0 2006.201.03:52:51.94#ibcon#enter sib2, iclass 39, count 0 2006.201.03:52:51.94#ibcon#flushed, iclass 39, count 0 2006.201.03:52:51.94#ibcon#about to write, iclass 39, count 0 2006.201.03:52:51.94#ibcon#wrote, iclass 39, count 0 2006.201.03:52:51.94#ibcon#about to read 3, iclass 39, count 0 2006.201.03:52:51.99#ibcon#read 3, iclass 39, count 0 2006.201.03:52:51.99#ibcon#about to read 4, iclass 39, count 0 2006.201.03:52:51.99#ibcon#read 4, iclass 39, count 0 2006.201.03:52:51.99#ibcon#about to read 5, iclass 39, count 0 2006.201.03:52:51.99#ibcon#read 5, iclass 39, count 0 2006.201.03:52:51.99#ibcon#about to read 6, iclass 39, count 0 2006.201.03:52:51.99#ibcon#read 6, iclass 39, count 0 2006.201.03:52:51.99#ibcon#end of sib2, iclass 39, count 0 2006.201.03:52:51.99#ibcon#*after write, iclass 39, count 0 2006.201.03:52:51.99#ibcon#*before return 0, iclass 39, count 0 2006.201.03:52:51.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:51.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.03:52:51.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.03:52:51.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.03:52:51.99$vck44/vb=5,4 2006.201.03:52:51.99#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.03:52:51.99#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.03:52:51.99#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:51.99#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:52.04#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:52.04#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:52.04#ibcon#enter wrdev, iclass 2, count 2 2006.201.03:52:52.04#ibcon#first serial, iclass 2, count 2 2006.201.03:52:52.04#ibcon#enter sib2, iclass 2, count 2 2006.201.03:52:52.04#ibcon#flushed, iclass 2, count 2 2006.201.03:52:52.04#ibcon#about to write, iclass 2, count 2 2006.201.03:52:52.04#ibcon#wrote, iclass 2, count 2 2006.201.03:52:52.04#ibcon#about to read 3, iclass 2, count 2 2006.201.03:52:52.06#ibcon#read 3, iclass 2, count 2 2006.201.03:52:52.06#ibcon#about to read 4, iclass 2, count 2 2006.201.03:52:52.06#ibcon#read 4, iclass 2, count 2 2006.201.03:52:52.06#ibcon#about to read 5, iclass 2, count 2 2006.201.03:52:52.06#ibcon#read 5, iclass 2, count 2 2006.201.03:52:52.06#ibcon#about to read 6, iclass 2, count 2 2006.201.03:52:52.06#ibcon#read 6, iclass 2, count 2 2006.201.03:52:52.06#ibcon#end of sib2, iclass 2, count 2 2006.201.03:52:52.06#ibcon#*mode == 0, iclass 2, count 2 2006.201.03:52:52.06#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.03:52:52.06#ibcon#[27=AT05-04\r\n] 2006.201.03:52:52.06#ibcon#*before write, iclass 2, count 2 2006.201.03:52:52.06#ibcon#enter sib2, iclass 2, count 2 2006.201.03:52:52.06#ibcon#flushed, iclass 2, count 2 2006.201.03:52:52.06#ibcon#about to write, iclass 2, count 2 2006.201.03:52:52.06#ibcon#wrote, iclass 2, count 2 2006.201.03:52:52.06#ibcon#about to read 3, iclass 2, count 2 2006.201.03:52:52.09#ibcon#read 3, iclass 2, count 2 2006.201.03:52:52.09#ibcon#about to read 4, iclass 2, count 2 2006.201.03:52:52.09#ibcon#read 4, iclass 2, count 2 2006.201.03:52:52.09#ibcon#about to read 5, iclass 2, count 2 2006.201.03:52:52.09#ibcon#read 5, iclass 2, count 2 2006.201.03:52:52.09#ibcon#about to read 6, iclass 2, count 2 2006.201.03:52:52.09#ibcon#read 6, iclass 2, count 2 2006.201.03:52:52.09#ibcon#end of sib2, iclass 2, count 2 2006.201.03:52:52.09#ibcon#*after write, iclass 2, count 2 2006.201.03:52:52.09#ibcon#*before return 0, iclass 2, count 2 2006.201.03:52:52.09#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:52.09#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.03:52:52.09#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.03:52:52.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:52.09#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:52.21#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:52.21#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:52.21#ibcon#enter wrdev, iclass 2, count 0 2006.201.03:52:52.21#ibcon#first serial, iclass 2, count 0 2006.201.03:52:52.21#ibcon#enter sib2, iclass 2, count 0 2006.201.03:52:52.21#ibcon#flushed, iclass 2, count 0 2006.201.03:52:52.21#ibcon#about to write, iclass 2, count 0 2006.201.03:52:52.21#ibcon#wrote, iclass 2, count 0 2006.201.03:52:52.21#ibcon#about to read 3, iclass 2, count 0 2006.201.03:52:52.23#ibcon#read 3, iclass 2, count 0 2006.201.03:52:52.23#ibcon#about to read 4, iclass 2, count 0 2006.201.03:52:52.23#ibcon#read 4, iclass 2, count 0 2006.201.03:52:52.23#ibcon#about to read 5, iclass 2, count 0 2006.201.03:52:52.23#ibcon#read 5, iclass 2, count 0 2006.201.03:52:52.23#ibcon#about to read 6, iclass 2, count 0 2006.201.03:52:52.23#ibcon#read 6, iclass 2, count 0 2006.201.03:52:52.23#ibcon#end of sib2, iclass 2, count 0 2006.201.03:52:52.23#ibcon#*mode == 0, iclass 2, count 0 2006.201.03:52:52.23#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.03:52:52.23#ibcon#[27=USB\r\n] 2006.201.03:52:52.23#ibcon#*before write, iclass 2, count 0 2006.201.03:52:52.23#ibcon#enter sib2, iclass 2, count 0 2006.201.03:52:52.23#ibcon#flushed, iclass 2, count 0 2006.201.03:52:52.23#ibcon#about to write, iclass 2, count 0 2006.201.03:52:52.23#ibcon#wrote, iclass 2, count 0 2006.201.03:52:52.23#ibcon#about to read 3, iclass 2, count 0 2006.201.03:52:52.26#ibcon#read 3, iclass 2, count 0 2006.201.03:52:52.26#ibcon#about to read 4, iclass 2, count 0 2006.201.03:52:52.26#ibcon#read 4, iclass 2, count 0 2006.201.03:52:52.26#ibcon#about to read 5, iclass 2, count 0 2006.201.03:52:52.26#ibcon#read 5, iclass 2, count 0 2006.201.03:52:52.26#ibcon#about to read 6, iclass 2, count 0 2006.201.03:52:52.26#ibcon#read 6, iclass 2, count 0 2006.201.03:52:52.26#ibcon#end of sib2, iclass 2, count 0 2006.201.03:52:52.26#ibcon#*after write, iclass 2, count 0 2006.201.03:52:52.26#ibcon#*before return 0, iclass 2, count 0 2006.201.03:52:52.26#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:52.26#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.03:52:52.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.03:52:52.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.03:52:52.26$vck44/vblo=6,719.99 2006.201.03:52:52.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.03:52:52.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.03:52:52.26#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:52.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:52.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:52.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:52.26#ibcon#enter wrdev, iclass 5, count 0 2006.201.03:52:52.26#ibcon#first serial, iclass 5, count 0 2006.201.03:52:52.26#ibcon#enter sib2, iclass 5, count 0 2006.201.03:52:52.26#ibcon#flushed, iclass 5, count 0 2006.201.03:52:52.26#ibcon#about to write, iclass 5, count 0 2006.201.03:52:52.26#ibcon#wrote, iclass 5, count 0 2006.201.03:52:52.26#ibcon#about to read 3, iclass 5, count 0 2006.201.03:52:52.28#ibcon#read 3, iclass 5, count 0 2006.201.03:52:52.28#ibcon#about to read 4, iclass 5, count 0 2006.201.03:52:52.28#ibcon#read 4, iclass 5, count 0 2006.201.03:52:52.28#ibcon#about to read 5, iclass 5, count 0 2006.201.03:52:52.28#ibcon#read 5, iclass 5, count 0 2006.201.03:52:52.28#ibcon#about to read 6, iclass 5, count 0 2006.201.03:52:52.28#ibcon#read 6, iclass 5, count 0 2006.201.03:52:52.28#ibcon#end of sib2, iclass 5, count 0 2006.201.03:52:52.28#ibcon#*mode == 0, iclass 5, count 0 2006.201.03:52:52.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.03:52:52.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:52:52.28#ibcon#*before write, iclass 5, count 0 2006.201.03:52:52.28#ibcon#enter sib2, iclass 5, count 0 2006.201.03:52:52.28#ibcon#flushed, iclass 5, count 0 2006.201.03:52:52.28#ibcon#about to write, iclass 5, count 0 2006.201.03:52:52.28#ibcon#wrote, iclass 5, count 0 2006.201.03:52:52.28#ibcon#about to read 3, iclass 5, count 0 2006.201.03:52:52.32#ibcon#read 3, iclass 5, count 0 2006.201.03:52:52.32#ibcon#about to read 4, iclass 5, count 0 2006.201.03:52:52.32#ibcon#read 4, iclass 5, count 0 2006.201.03:52:52.32#ibcon#about to read 5, iclass 5, count 0 2006.201.03:52:52.32#ibcon#read 5, iclass 5, count 0 2006.201.03:52:52.32#ibcon#about to read 6, iclass 5, count 0 2006.201.03:52:52.32#ibcon#read 6, iclass 5, count 0 2006.201.03:52:52.32#ibcon#end of sib2, iclass 5, count 0 2006.201.03:52:52.32#ibcon#*after write, iclass 5, count 0 2006.201.03:52:52.32#ibcon#*before return 0, iclass 5, count 0 2006.201.03:52:52.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:52.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.03:52:52.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.03:52:52.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.03:52:52.32$vck44/vb=6,4 2006.201.03:52:52.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.03:52:52.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.03:52:52.32#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:52.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:52.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:52.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:52.38#ibcon#enter wrdev, iclass 7, count 2 2006.201.03:52:52.38#ibcon#first serial, iclass 7, count 2 2006.201.03:52:52.38#ibcon#enter sib2, iclass 7, count 2 2006.201.03:52:52.38#ibcon#flushed, iclass 7, count 2 2006.201.03:52:52.38#ibcon#about to write, iclass 7, count 2 2006.201.03:52:52.38#ibcon#wrote, iclass 7, count 2 2006.201.03:52:52.38#ibcon#about to read 3, iclass 7, count 2 2006.201.03:52:52.40#ibcon#read 3, iclass 7, count 2 2006.201.03:52:52.40#ibcon#about to read 4, iclass 7, count 2 2006.201.03:52:52.40#ibcon#read 4, iclass 7, count 2 2006.201.03:52:52.40#ibcon#about to read 5, iclass 7, count 2 2006.201.03:52:52.40#ibcon#read 5, iclass 7, count 2 2006.201.03:52:52.40#ibcon#about to read 6, iclass 7, count 2 2006.201.03:52:52.40#ibcon#read 6, iclass 7, count 2 2006.201.03:52:52.40#ibcon#end of sib2, iclass 7, count 2 2006.201.03:52:52.40#ibcon#*mode == 0, iclass 7, count 2 2006.201.03:52:52.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.03:52:52.40#ibcon#[27=AT06-04\r\n] 2006.201.03:52:52.40#ibcon#*before write, iclass 7, count 2 2006.201.03:52:52.40#ibcon#enter sib2, iclass 7, count 2 2006.201.03:52:52.40#ibcon#flushed, iclass 7, count 2 2006.201.03:52:52.40#ibcon#about to write, iclass 7, count 2 2006.201.03:52:52.40#ibcon#wrote, iclass 7, count 2 2006.201.03:52:52.40#ibcon#about to read 3, iclass 7, count 2 2006.201.03:52:52.43#ibcon#read 3, iclass 7, count 2 2006.201.03:52:52.43#ibcon#about to read 4, iclass 7, count 2 2006.201.03:52:52.43#ibcon#read 4, iclass 7, count 2 2006.201.03:52:52.43#ibcon#about to read 5, iclass 7, count 2 2006.201.03:52:52.43#ibcon#read 5, iclass 7, count 2 2006.201.03:52:52.43#ibcon#about to read 6, iclass 7, count 2 2006.201.03:52:52.43#ibcon#read 6, iclass 7, count 2 2006.201.03:52:52.43#ibcon#end of sib2, iclass 7, count 2 2006.201.03:52:52.43#ibcon#*after write, iclass 7, count 2 2006.201.03:52:52.43#ibcon#*before return 0, iclass 7, count 2 2006.201.03:52:52.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:52.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.03:52:52.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.03:52:52.43#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:52.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:52.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:52.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:52.55#ibcon#enter wrdev, iclass 7, count 0 2006.201.03:52:52.55#ibcon#first serial, iclass 7, count 0 2006.201.03:52:52.55#ibcon#enter sib2, iclass 7, count 0 2006.201.03:52:52.55#ibcon#flushed, iclass 7, count 0 2006.201.03:52:52.55#ibcon#about to write, iclass 7, count 0 2006.201.03:52:52.55#ibcon#wrote, iclass 7, count 0 2006.201.03:52:52.55#ibcon#about to read 3, iclass 7, count 0 2006.201.03:52:52.57#ibcon#read 3, iclass 7, count 0 2006.201.03:52:52.57#ibcon#about to read 4, iclass 7, count 0 2006.201.03:52:52.57#ibcon#read 4, iclass 7, count 0 2006.201.03:52:52.57#ibcon#about to read 5, iclass 7, count 0 2006.201.03:52:52.57#ibcon#read 5, iclass 7, count 0 2006.201.03:52:52.57#ibcon#about to read 6, iclass 7, count 0 2006.201.03:52:52.57#ibcon#read 6, iclass 7, count 0 2006.201.03:52:52.57#ibcon#end of sib2, iclass 7, count 0 2006.201.03:52:52.57#ibcon#*mode == 0, iclass 7, count 0 2006.201.03:52:52.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.03:52:52.57#ibcon#[27=USB\r\n] 2006.201.03:52:52.57#ibcon#*before write, iclass 7, count 0 2006.201.03:52:52.57#ibcon#enter sib2, iclass 7, count 0 2006.201.03:52:52.57#ibcon#flushed, iclass 7, count 0 2006.201.03:52:52.57#ibcon#about to write, iclass 7, count 0 2006.201.03:52:52.57#ibcon#wrote, iclass 7, count 0 2006.201.03:52:52.57#ibcon#about to read 3, iclass 7, count 0 2006.201.03:52:52.60#ibcon#read 3, iclass 7, count 0 2006.201.03:52:52.60#ibcon#about to read 4, iclass 7, count 0 2006.201.03:52:52.60#ibcon#read 4, iclass 7, count 0 2006.201.03:52:52.60#ibcon#about to read 5, iclass 7, count 0 2006.201.03:52:52.60#ibcon#read 5, iclass 7, count 0 2006.201.03:52:52.60#ibcon#about to read 6, iclass 7, count 0 2006.201.03:52:52.60#ibcon#read 6, iclass 7, count 0 2006.201.03:52:52.60#ibcon#end of sib2, iclass 7, count 0 2006.201.03:52:52.60#ibcon#*after write, iclass 7, count 0 2006.201.03:52:52.60#ibcon#*before return 0, iclass 7, count 0 2006.201.03:52:52.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:52.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.03:52:52.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.03:52:52.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.03:52:52.60$vck44/vblo=7,734.99 2006.201.03:52:52.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.03:52:52.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.03:52:52.60#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:52.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:52.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:52.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:52.60#ibcon#enter wrdev, iclass 11, count 0 2006.201.03:52:52.60#ibcon#first serial, iclass 11, count 0 2006.201.03:52:52.60#ibcon#enter sib2, iclass 11, count 0 2006.201.03:52:52.60#ibcon#flushed, iclass 11, count 0 2006.201.03:52:52.60#ibcon#about to write, iclass 11, count 0 2006.201.03:52:52.60#ibcon#wrote, iclass 11, count 0 2006.201.03:52:52.60#ibcon#about to read 3, iclass 11, count 0 2006.201.03:52:52.62#ibcon#read 3, iclass 11, count 0 2006.201.03:52:52.62#ibcon#about to read 4, iclass 11, count 0 2006.201.03:52:52.62#ibcon#read 4, iclass 11, count 0 2006.201.03:52:52.62#ibcon#about to read 5, iclass 11, count 0 2006.201.03:52:52.62#ibcon#read 5, iclass 11, count 0 2006.201.03:52:52.62#ibcon#about to read 6, iclass 11, count 0 2006.201.03:52:52.62#ibcon#read 6, iclass 11, count 0 2006.201.03:52:52.62#ibcon#end of sib2, iclass 11, count 0 2006.201.03:52:52.62#ibcon#*mode == 0, iclass 11, count 0 2006.201.03:52:52.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.03:52:52.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:52:52.62#ibcon#*before write, iclass 11, count 0 2006.201.03:52:52.62#ibcon#enter sib2, iclass 11, count 0 2006.201.03:52:52.62#ibcon#flushed, iclass 11, count 0 2006.201.03:52:52.62#ibcon#about to write, iclass 11, count 0 2006.201.03:52:52.62#ibcon#wrote, iclass 11, count 0 2006.201.03:52:52.62#ibcon#about to read 3, iclass 11, count 0 2006.201.03:52:52.66#ibcon#read 3, iclass 11, count 0 2006.201.03:52:52.66#ibcon#about to read 4, iclass 11, count 0 2006.201.03:52:52.66#ibcon#read 4, iclass 11, count 0 2006.201.03:52:52.66#ibcon#about to read 5, iclass 11, count 0 2006.201.03:52:52.66#ibcon#read 5, iclass 11, count 0 2006.201.03:52:52.66#ibcon#about to read 6, iclass 11, count 0 2006.201.03:52:52.66#ibcon#read 6, iclass 11, count 0 2006.201.03:52:52.66#ibcon#end of sib2, iclass 11, count 0 2006.201.03:52:52.66#ibcon#*after write, iclass 11, count 0 2006.201.03:52:52.66#ibcon#*before return 0, iclass 11, count 0 2006.201.03:52:52.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:52.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.03:52:52.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.03:52:52.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.03:52:52.66$vck44/vb=7,4 2006.201.03:52:52.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.03:52:52.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.03:52:52.66#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:52.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:52.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:52.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:52.72#ibcon#enter wrdev, iclass 13, count 2 2006.201.03:52:52.72#ibcon#first serial, iclass 13, count 2 2006.201.03:52:52.72#ibcon#enter sib2, iclass 13, count 2 2006.201.03:52:52.72#ibcon#flushed, iclass 13, count 2 2006.201.03:52:52.72#ibcon#about to write, iclass 13, count 2 2006.201.03:52:52.72#ibcon#wrote, iclass 13, count 2 2006.201.03:52:52.72#ibcon#about to read 3, iclass 13, count 2 2006.201.03:52:52.74#ibcon#read 3, iclass 13, count 2 2006.201.03:52:52.74#ibcon#about to read 4, iclass 13, count 2 2006.201.03:52:52.74#ibcon#read 4, iclass 13, count 2 2006.201.03:52:52.74#ibcon#about to read 5, iclass 13, count 2 2006.201.03:52:52.74#ibcon#read 5, iclass 13, count 2 2006.201.03:52:52.74#ibcon#about to read 6, iclass 13, count 2 2006.201.03:52:52.74#ibcon#read 6, iclass 13, count 2 2006.201.03:52:52.74#ibcon#end of sib2, iclass 13, count 2 2006.201.03:52:52.74#ibcon#*mode == 0, iclass 13, count 2 2006.201.03:52:52.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.03:52:52.74#ibcon#[27=AT07-04\r\n] 2006.201.03:52:52.74#ibcon#*before write, iclass 13, count 2 2006.201.03:52:52.74#ibcon#enter sib2, iclass 13, count 2 2006.201.03:52:52.74#ibcon#flushed, iclass 13, count 2 2006.201.03:52:52.74#ibcon#about to write, iclass 13, count 2 2006.201.03:52:52.74#ibcon#wrote, iclass 13, count 2 2006.201.03:52:52.74#ibcon#about to read 3, iclass 13, count 2 2006.201.03:52:52.77#ibcon#read 3, iclass 13, count 2 2006.201.03:52:52.77#ibcon#about to read 4, iclass 13, count 2 2006.201.03:52:52.77#ibcon#read 4, iclass 13, count 2 2006.201.03:52:52.77#ibcon#about to read 5, iclass 13, count 2 2006.201.03:52:52.77#ibcon#read 5, iclass 13, count 2 2006.201.03:52:52.77#ibcon#about to read 6, iclass 13, count 2 2006.201.03:52:52.77#ibcon#read 6, iclass 13, count 2 2006.201.03:52:52.77#ibcon#end of sib2, iclass 13, count 2 2006.201.03:52:52.77#ibcon#*after write, iclass 13, count 2 2006.201.03:52:52.77#ibcon#*before return 0, iclass 13, count 2 2006.201.03:52:52.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:52.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.03:52:52.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.03:52:52.77#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:52.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:52.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:52.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:52.89#ibcon#enter wrdev, iclass 13, count 0 2006.201.03:52:52.89#ibcon#first serial, iclass 13, count 0 2006.201.03:52:52.89#ibcon#enter sib2, iclass 13, count 0 2006.201.03:52:52.89#ibcon#flushed, iclass 13, count 0 2006.201.03:52:52.89#ibcon#about to write, iclass 13, count 0 2006.201.03:52:52.89#ibcon#wrote, iclass 13, count 0 2006.201.03:52:52.89#ibcon#about to read 3, iclass 13, count 0 2006.201.03:52:52.91#ibcon#read 3, iclass 13, count 0 2006.201.03:52:52.91#ibcon#about to read 4, iclass 13, count 0 2006.201.03:52:52.91#ibcon#read 4, iclass 13, count 0 2006.201.03:52:52.91#ibcon#about to read 5, iclass 13, count 0 2006.201.03:52:52.91#ibcon#read 5, iclass 13, count 0 2006.201.03:52:52.91#ibcon#about to read 6, iclass 13, count 0 2006.201.03:52:52.91#ibcon#read 6, iclass 13, count 0 2006.201.03:52:52.91#ibcon#end of sib2, iclass 13, count 0 2006.201.03:52:52.91#ibcon#*mode == 0, iclass 13, count 0 2006.201.03:52:52.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.03:52:52.91#ibcon#[27=USB\r\n] 2006.201.03:52:52.91#ibcon#*before write, iclass 13, count 0 2006.201.03:52:52.91#ibcon#enter sib2, iclass 13, count 0 2006.201.03:52:52.91#ibcon#flushed, iclass 13, count 0 2006.201.03:52:52.91#ibcon#about to write, iclass 13, count 0 2006.201.03:52:52.91#ibcon#wrote, iclass 13, count 0 2006.201.03:52:52.91#ibcon#about to read 3, iclass 13, count 0 2006.201.03:52:52.94#ibcon#read 3, iclass 13, count 0 2006.201.03:52:52.94#ibcon#about to read 4, iclass 13, count 0 2006.201.03:52:52.94#ibcon#read 4, iclass 13, count 0 2006.201.03:52:52.94#ibcon#about to read 5, iclass 13, count 0 2006.201.03:52:52.94#ibcon#read 5, iclass 13, count 0 2006.201.03:52:52.94#ibcon#about to read 6, iclass 13, count 0 2006.201.03:52:52.94#ibcon#read 6, iclass 13, count 0 2006.201.03:52:52.94#ibcon#end of sib2, iclass 13, count 0 2006.201.03:52:52.94#ibcon#*after write, iclass 13, count 0 2006.201.03:52:52.94#ibcon#*before return 0, iclass 13, count 0 2006.201.03:52:52.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:52.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.03:52:52.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.03:52:52.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.03:52:52.94$vck44/vblo=8,744.99 2006.201.03:52:52.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.03:52:52.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.03:52:52.94#ibcon#ireg 17 cls_cnt 0 2006.201.03:52:52.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:52.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:52.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:52.94#ibcon#enter wrdev, iclass 15, count 0 2006.201.03:52:52.94#ibcon#first serial, iclass 15, count 0 2006.201.03:52:52.94#ibcon#enter sib2, iclass 15, count 0 2006.201.03:52:52.94#ibcon#flushed, iclass 15, count 0 2006.201.03:52:52.94#ibcon#about to write, iclass 15, count 0 2006.201.03:52:52.94#ibcon#wrote, iclass 15, count 0 2006.201.03:52:52.94#ibcon#about to read 3, iclass 15, count 0 2006.201.03:52:52.96#ibcon#read 3, iclass 15, count 0 2006.201.03:52:52.96#ibcon#about to read 4, iclass 15, count 0 2006.201.03:52:52.96#ibcon#read 4, iclass 15, count 0 2006.201.03:52:52.96#ibcon#about to read 5, iclass 15, count 0 2006.201.03:52:52.96#ibcon#read 5, iclass 15, count 0 2006.201.03:52:52.96#ibcon#about to read 6, iclass 15, count 0 2006.201.03:52:52.96#ibcon#read 6, iclass 15, count 0 2006.201.03:52:52.96#ibcon#end of sib2, iclass 15, count 0 2006.201.03:52:52.96#ibcon#*mode == 0, iclass 15, count 0 2006.201.03:52:52.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.03:52:52.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:52:52.96#ibcon#*before write, iclass 15, count 0 2006.201.03:52:52.96#ibcon#enter sib2, iclass 15, count 0 2006.201.03:52:52.96#ibcon#flushed, iclass 15, count 0 2006.201.03:52:52.96#ibcon#about to write, iclass 15, count 0 2006.201.03:52:52.96#ibcon#wrote, iclass 15, count 0 2006.201.03:52:52.96#ibcon#about to read 3, iclass 15, count 0 2006.201.03:52:53.00#ibcon#read 3, iclass 15, count 0 2006.201.03:52:53.00#ibcon#about to read 4, iclass 15, count 0 2006.201.03:52:53.00#ibcon#read 4, iclass 15, count 0 2006.201.03:52:53.00#ibcon#about to read 5, iclass 15, count 0 2006.201.03:52:53.00#ibcon#read 5, iclass 15, count 0 2006.201.03:52:53.00#ibcon#about to read 6, iclass 15, count 0 2006.201.03:52:53.00#ibcon#read 6, iclass 15, count 0 2006.201.03:52:53.00#ibcon#end of sib2, iclass 15, count 0 2006.201.03:52:53.00#ibcon#*after write, iclass 15, count 0 2006.201.03:52:53.00#ibcon#*before return 0, iclass 15, count 0 2006.201.03:52:53.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:53.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.03:52:53.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.03:52:53.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.03:52:53.00$vck44/vb=8,4 2006.201.03:52:53.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.03:52:53.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.03:52:53.00#ibcon#ireg 11 cls_cnt 2 2006.201.03:52:53.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:53.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:53.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:53.06#ibcon#enter wrdev, iclass 17, count 2 2006.201.03:52:53.06#ibcon#first serial, iclass 17, count 2 2006.201.03:52:53.06#ibcon#enter sib2, iclass 17, count 2 2006.201.03:52:53.06#ibcon#flushed, iclass 17, count 2 2006.201.03:52:53.06#ibcon#about to write, iclass 17, count 2 2006.201.03:52:53.06#ibcon#wrote, iclass 17, count 2 2006.201.03:52:53.06#ibcon#about to read 3, iclass 17, count 2 2006.201.03:52:53.08#ibcon#read 3, iclass 17, count 2 2006.201.03:52:53.08#ibcon#about to read 4, iclass 17, count 2 2006.201.03:52:53.08#ibcon#read 4, iclass 17, count 2 2006.201.03:52:53.08#ibcon#about to read 5, iclass 17, count 2 2006.201.03:52:53.08#ibcon#read 5, iclass 17, count 2 2006.201.03:52:53.08#ibcon#about to read 6, iclass 17, count 2 2006.201.03:52:53.08#ibcon#read 6, iclass 17, count 2 2006.201.03:52:53.08#ibcon#end of sib2, iclass 17, count 2 2006.201.03:52:53.08#ibcon#*mode == 0, iclass 17, count 2 2006.201.03:52:53.08#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.03:52:53.08#ibcon#[27=AT08-04\r\n] 2006.201.03:52:53.08#ibcon#*before write, iclass 17, count 2 2006.201.03:52:53.08#ibcon#enter sib2, iclass 17, count 2 2006.201.03:52:53.08#ibcon#flushed, iclass 17, count 2 2006.201.03:52:53.08#ibcon#about to write, iclass 17, count 2 2006.201.03:52:53.08#ibcon#wrote, iclass 17, count 2 2006.201.03:52:53.08#ibcon#about to read 3, iclass 17, count 2 2006.201.03:52:53.11#ibcon#read 3, iclass 17, count 2 2006.201.03:52:53.11#ibcon#about to read 4, iclass 17, count 2 2006.201.03:52:53.11#ibcon#read 4, iclass 17, count 2 2006.201.03:52:53.11#ibcon#about to read 5, iclass 17, count 2 2006.201.03:52:53.11#ibcon#read 5, iclass 17, count 2 2006.201.03:52:53.11#ibcon#about to read 6, iclass 17, count 2 2006.201.03:52:53.11#ibcon#read 6, iclass 17, count 2 2006.201.03:52:53.11#ibcon#end of sib2, iclass 17, count 2 2006.201.03:52:53.11#ibcon#*after write, iclass 17, count 2 2006.201.03:52:53.11#ibcon#*before return 0, iclass 17, count 2 2006.201.03:52:53.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:53.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.03:52:53.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.03:52:53.11#ibcon#ireg 7 cls_cnt 0 2006.201.03:52:53.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:53.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:53.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:53.23#ibcon#enter wrdev, iclass 17, count 0 2006.201.03:52:53.23#ibcon#first serial, iclass 17, count 0 2006.201.03:52:53.23#ibcon#enter sib2, iclass 17, count 0 2006.201.03:52:53.23#ibcon#flushed, iclass 17, count 0 2006.201.03:52:53.23#ibcon#about to write, iclass 17, count 0 2006.201.03:52:53.23#ibcon#wrote, iclass 17, count 0 2006.201.03:52:53.23#ibcon#about to read 3, iclass 17, count 0 2006.201.03:52:53.25#ibcon#read 3, iclass 17, count 0 2006.201.03:52:53.25#ibcon#about to read 4, iclass 17, count 0 2006.201.03:52:53.25#ibcon#read 4, iclass 17, count 0 2006.201.03:52:53.25#ibcon#about to read 5, iclass 17, count 0 2006.201.03:52:53.25#ibcon#read 5, iclass 17, count 0 2006.201.03:52:53.25#ibcon#about to read 6, iclass 17, count 0 2006.201.03:52:53.25#ibcon#read 6, iclass 17, count 0 2006.201.03:52:53.25#ibcon#end of sib2, iclass 17, count 0 2006.201.03:52:53.25#ibcon#*mode == 0, iclass 17, count 0 2006.201.03:52:53.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.03:52:53.25#ibcon#[27=USB\r\n] 2006.201.03:52:53.25#ibcon#*before write, iclass 17, count 0 2006.201.03:52:53.25#ibcon#enter sib2, iclass 17, count 0 2006.201.03:52:53.25#ibcon#flushed, iclass 17, count 0 2006.201.03:52:53.25#ibcon#about to write, iclass 17, count 0 2006.201.03:52:53.25#ibcon#wrote, iclass 17, count 0 2006.201.03:52:53.25#ibcon#about to read 3, iclass 17, count 0 2006.201.03:52:53.28#ibcon#read 3, iclass 17, count 0 2006.201.03:52:53.28#ibcon#about to read 4, iclass 17, count 0 2006.201.03:52:53.28#ibcon#read 4, iclass 17, count 0 2006.201.03:52:53.28#ibcon#about to read 5, iclass 17, count 0 2006.201.03:52:53.28#ibcon#read 5, iclass 17, count 0 2006.201.03:52:53.28#ibcon#about to read 6, iclass 17, count 0 2006.201.03:52:53.28#ibcon#read 6, iclass 17, count 0 2006.201.03:52:53.28#ibcon#end of sib2, iclass 17, count 0 2006.201.03:52:53.28#ibcon#*after write, iclass 17, count 0 2006.201.03:52:53.28#ibcon#*before return 0, iclass 17, count 0 2006.201.03:52:53.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:53.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.03:52:53.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.03:52:53.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.03:52:53.28$vck44/vabw=wide 2006.201.03:52:53.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.03:52:53.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.03:52:53.28#ibcon#ireg 8 cls_cnt 0 2006.201.03:52:53.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:53.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:53.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:53.28#ibcon#enter wrdev, iclass 19, count 0 2006.201.03:52:53.28#ibcon#first serial, iclass 19, count 0 2006.201.03:52:53.28#ibcon#enter sib2, iclass 19, count 0 2006.201.03:52:53.28#ibcon#flushed, iclass 19, count 0 2006.201.03:52:53.28#ibcon#about to write, iclass 19, count 0 2006.201.03:52:53.28#ibcon#wrote, iclass 19, count 0 2006.201.03:52:53.28#ibcon#about to read 3, iclass 19, count 0 2006.201.03:52:53.30#ibcon#read 3, iclass 19, count 0 2006.201.03:52:53.30#ibcon#about to read 4, iclass 19, count 0 2006.201.03:52:53.30#ibcon#read 4, iclass 19, count 0 2006.201.03:52:53.30#ibcon#about to read 5, iclass 19, count 0 2006.201.03:52:53.30#ibcon#read 5, iclass 19, count 0 2006.201.03:52:53.30#ibcon#about to read 6, iclass 19, count 0 2006.201.03:52:53.30#ibcon#read 6, iclass 19, count 0 2006.201.03:52:53.30#ibcon#end of sib2, iclass 19, count 0 2006.201.03:52:53.30#ibcon#*mode == 0, iclass 19, count 0 2006.201.03:52:53.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.03:52:53.30#ibcon#[25=BW32\r\n] 2006.201.03:52:53.30#ibcon#*before write, iclass 19, count 0 2006.201.03:52:53.30#ibcon#enter sib2, iclass 19, count 0 2006.201.03:52:53.30#ibcon#flushed, iclass 19, count 0 2006.201.03:52:53.30#ibcon#about to write, iclass 19, count 0 2006.201.03:52:53.30#ibcon#wrote, iclass 19, count 0 2006.201.03:52:53.30#ibcon#about to read 3, iclass 19, count 0 2006.201.03:52:53.33#ibcon#read 3, iclass 19, count 0 2006.201.03:52:53.33#ibcon#about to read 4, iclass 19, count 0 2006.201.03:52:53.33#ibcon#read 4, iclass 19, count 0 2006.201.03:52:53.33#ibcon#about to read 5, iclass 19, count 0 2006.201.03:52:53.33#ibcon#read 5, iclass 19, count 0 2006.201.03:52:53.33#ibcon#about to read 6, iclass 19, count 0 2006.201.03:52:53.33#ibcon#read 6, iclass 19, count 0 2006.201.03:52:53.33#ibcon#end of sib2, iclass 19, count 0 2006.201.03:52:53.33#ibcon#*after write, iclass 19, count 0 2006.201.03:52:53.33#ibcon#*before return 0, iclass 19, count 0 2006.201.03:52:53.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:53.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.03:52:53.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.03:52:53.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.03:52:53.33$vck44/vbbw=wide 2006.201.03:52:53.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.03:52:53.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.03:52:53.33#ibcon#ireg 8 cls_cnt 0 2006.201.03:52:53.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:52:53.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:52:53.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:52:53.40#ibcon#enter wrdev, iclass 21, count 0 2006.201.03:52:53.40#ibcon#first serial, iclass 21, count 0 2006.201.03:52:53.40#ibcon#enter sib2, iclass 21, count 0 2006.201.03:52:53.40#ibcon#flushed, iclass 21, count 0 2006.201.03:52:53.40#ibcon#about to write, iclass 21, count 0 2006.201.03:52:53.40#ibcon#wrote, iclass 21, count 0 2006.201.03:52:53.40#ibcon#about to read 3, iclass 21, count 0 2006.201.03:52:53.42#ibcon#read 3, iclass 21, count 0 2006.201.03:52:53.42#ibcon#about to read 4, iclass 21, count 0 2006.201.03:52:53.42#ibcon#read 4, iclass 21, count 0 2006.201.03:52:53.42#ibcon#about to read 5, iclass 21, count 0 2006.201.03:52:53.42#ibcon#read 5, iclass 21, count 0 2006.201.03:52:53.42#ibcon#about to read 6, iclass 21, count 0 2006.201.03:52:53.42#ibcon#read 6, iclass 21, count 0 2006.201.03:52:53.42#ibcon#end of sib2, iclass 21, count 0 2006.201.03:52:53.42#ibcon#*mode == 0, iclass 21, count 0 2006.201.03:52:53.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.03:52:53.42#ibcon#[27=BW32\r\n] 2006.201.03:52:53.42#ibcon#*before write, iclass 21, count 0 2006.201.03:52:53.42#ibcon#enter sib2, iclass 21, count 0 2006.201.03:52:53.42#ibcon#flushed, iclass 21, count 0 2006.201.03:52:53.42#ibcon#about to write, iclass 21, count 0 2006.201.03:52:53.42#ibcon#wrote, iclass 21, count 0 2006.201.03:52:53.42#ibcon#about to read 3, iclass 21, count 0 2006.201.03:52:53.45#ibcon#read 3, iclass 21, count 0 2006.201.03:52:53.45#ibcon#about to read 4, iclass 21, count 0 2006.201.03:52:53.45#ibcon#read 4, iclass 21, count 0 2006.201.03:52:53.45#ibcon#about to read 5, iclass 21, count 0 2006.201.03:52:53.45#ibcon#read 5, iclass 21, count 0 2006.201.03:52:53.45#ibcon#about to read 6, iclass 21, count 0 2006.201.03:52:53.45#ibcon#read 6, iclass 21, count 0 2006.201.03:52:53.45#ibcon#end of sib2, iclass 21, count 0 2006.201.03:52:53.45#ibcon#*after write, iclass 21, count 0 2006.201.03:52:53.45#ibcon#*before return 0, iclass 21, count 0 2006.201.03:52:53.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:52:53.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.03:52:53.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.03:52:53.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.03:52:53.45$setupk4/ifdk4 2006.201.03:52:53.45$ifdk4/lo= 2006.201.03:52:53.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:52:53.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:52:53.45$ifdk4/patch= 2006.201.03:52:53.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:52:53.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:52:53.45$setupk4/!*+20s 2006.201.03:52:57.77#abcon#<5=/03 2.0 4.6 22.94 911004.3\r\n> 2006.201.03:52:57.79#abcon#{5=INTERFACE CLEAR} 2006.201.03:52:57.87#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:53:07.93$setupk4/"tpicd 2006.201.03:53:07.93$setupk4/echo=off 2006.201.03:53:07.93$setupk4/xlog=off 2006.201.03:53:07.93:!2006.201.03:54:35 2006.201.03:53:07.96#abcon#<5=/03 2.1 4.6 22.94 911004.3\r\n> 2006.201.03:53:08.14#trakl#Source acquired 2006.201.03:53:08.14#flagr#flagr/antenna,acquired 2006.201.03:54:35.00:preob 2006.201.03:54:36.14/onsource/TRACKING 2006.201.03:54:36.14:!2006.201.03:54:45 2006.201.03:54:45.00:"tape 2006.201.03:54:45.00:"st=record 2006.201.03:54:45.00:data_valid=on 2006.201.03:54:45.00:midob 2006.201.03:54:45.14/onsource/TRACKING 2006.201.03:54:45.14/wx/22.92,1004.2,91 2006.201.03:54:45.31/cable/+6.4664E-03 2006.201.03:54:46.40/va/01,08,usb,yes,38,41 2006.201.03:54:46.40/va/02,07,usb,yes,41,42 2006.201.03:54:46.40/va/03,08,usb,yes,37,39 2006.201.03:54:46.40/va/04,07,usb,yes,42,44 2006.201.03:54:46.40/va/05,04,usb,yes,37,38 2006.201.03:54:46.40/va/06,05,usb,yes,37,38 2006.201.03:54:46.40/va/07,05,usb,yes,37,38 2006.201.03:54:46.40/va/08,04,usb,yes,36,43 2006.201.03:54:46.63/valo/01,524.99,yes,locked 2006.201.03:54:46.63/valo/02,534.99,yes,locked 2006.201.03:54:46.63/valo/03,564.99,yes,locked 2006.201.03:54:46.63/valo/04,624.99,yes,locked 2006.201.03:54:46.63/valo/05,734.99,yes,locked 2006.201.03:54:46.63/valo/06,814.99,yes,locked 2006.201.03:54:46.63/valo/07,864.99,yes,locked 2006.201.03:54:46.63/valo/08,884.99,yes,locked 2006.201.03:54:47.72/vb/01,04,usb,yes,30,56 2006.201.03:54:47.72/vb/02,05,usb,yes,28,61 2006.201.03:54:47.72/vb/03,04,usb,yes,29,40 2006.201.03:54:47.72/vb/04,05,usb,yes,29,28 2006.201.03:54:47.72/vb/05,04,usb,yes,26,29 2006.201.03:54:47.72/vb/06,04,usb,yes,31,27 2006.201.03:54:47.72/vb/07,04,usb,yes,31,31 2006.201.03:54:47.72/vb/08,04,usb,yes,28,32 2006.201.03:54:47.95/vblo/01,629.99,yes,locked 2006.201.03:54:47.95/vblo/02,634.99,yes,locked 2006.201.03:54:47.95/vblo/03,649.99,yes,locked 2006.201.03:54:47.95/vblo/04,679.99,yes,locked 2006.201.03:54:47.95/vblo/05,709.99,yes,locked 2006.201.03:54:47.95/vblo/06,719.99,yes,locked 2006.201.03:54:47.95/vblo/07,734.99,yes,locked 2006.201.03:54:47.95/vblo/08,744.99,yes,locked 2006.201.03:54:48.10/vabw/8 2006.201.03:54:48.25/vbbw/8 2006.201.03:54:48.34/xfe/off,on,14.7 2006.201.03:54:48.72/ifatt/23,28,28,28 2006.201.03:54:49.03/fmout-gps/S +4.56E-07 2006.201.03:54:49.07:!2006.201.03:56:55 2006.201.03:56:55.00:data_valid=off 2006.201.03:56:55.00:"et 2006.201.03:56:55.00:!+3s 2006.201.03:56:58.02:"tape 2006.201.03:56:58.02:postob 2006.201.03:56:58.12/cable/+6.4689E-03 2006.201.03:56:58.12/wx/22.90,1004.2,91 2006.201.03:56:58.18/fmout-gps/S +4.55E-07 2006.201.03:56:58.18:scan_name=201-0357,jd0607,270 2006.201.03:56:58.18:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.201.03:57:00.13#flagr#flagr/antenna,new-source 2006.201.03:57:00.13:checkk5 2006.201.03:57:00.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.03:57:00.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.03:57:01.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.03:57:01.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.03:57:02.01/chk_obsdata//k5ts1/T2010354??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.201.03:57:02.39/chk_obsdata//k5ts2/T2010354??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.201.03:57:02.75/chk_obsdata//k5ts3/T2010354??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.201.03:57:03.12/chk_obsdata//k5ts4/T2010354??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.201.03:57:03.81/k5log//k5ts1_log_newline 2006.201.03:57:04.49/k5log//k5ts2_log_newline 2006.201.03:57:05.18/k5log//k5ts3_log_newline 2006.201.03:57:05.87/k5log//k5ts4_log_newline 2006.201.03:57:05.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.03:57:05.89:setupk4=1 2006.201.03:57:05.89$setupk4/echo=on 2006.201.03:57:05.89$setupk4/pcalon 2006.201.03:57:05.89$pcalon/"no phase cal control is implemented here 2006.201.03:57:05.89$setupk4/"tpicd=stop 2006.201.03:57:05.89$setupk4/"rec=synch_on 2006.201.03:57:05.89$setupk4/"rec_mode=128 2006.201.03:57:05.89$setupk4/!* 2006.201.03:57:05.89$setupk4/recpk4 2006.201.03:57:05.89$recpk4/recpatch= 2006.201.03:57:05.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.03:57:05.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.03:57:05.90$setupk4/vck44 2006.201.03:57:05.90$vck44/valo=1,524.99 2006.201.03:57:05.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.03:57:05.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.03:57:05.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:05.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:05.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:05.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:05.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:57:05.90#ibcon#first serial, iclass 18, count 0 2006.201.03:57:05.90#ibcon#enter sib2, iclass 18, count 0 2006.201.03:57:05.90#ibcon#flushed, iclass 18, count 0 2006.201.03:57:05.90#ibcon#about to write, iclass 18, count 0 2006.201.03:57:05.90#ibcon#wrote, iclass 18, count 0 2006.201.03:57:05.90#ibcon#about to read 3, iclass 18, count 0 2006.201.03:57:05.94#ibcon#read 3, iclass 18, count 0 2006.201.03:57:05.94#ibcon#about to read 4, iclass 18, count 0 2006.201.03:57:05.94#ibcon#read 4, iclass 18, count 0 2006.201.03:57:05.94#ibcon#about to read 5, iclass 18, count 0 2006.201.03:57:05.94#ibcon#read 5, iclass 18, count 0 2006.201.03:57:05.94#ibcon#about to read 6, iclass 18, count 0 2006.201.03:57:05.94#ibcon#read 6, iclass 18, count 0 2006.201.03:57:05.94#ibcon#end of sib2, iclass 18, count 0 2006.201.03:57:05.94#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:57:05.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:57:05.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.03:57:05.94#ibcon#*before write, iclass 18, count 0 2006.201.03:57:05.94#ibcon#enter sib2, iclass 18, count 0 2006.201.03:57:05.94#ibcon#flushed, iclass 18, count 0 2006.201.03:57:05.94#ibcon#about to write, iclass 18, count 0 2006.201.03:57:05.94#ibcon#wrote, iclass 18, count 0 2006.201.03:57:05.94#ibcon#about to read 3, iclass 18, count 0 2006.201.03:57:05.99#ibcon#read 3, iclass 18, count 0 2006.201.03:57:05.99#ibcon#about to read 4, iclass 18, count 0 2006.201.03:57:05.99#ibcon#read 4, iclass 18, count 0 2006.201.03:57:05.99#ibcon#about to read 5, iclass 18, count 0 2006.201.03:57:05.99#ibcon#read 5, iclass 18, count 0 2006.201.03:57:05.99#ibcon#about to read 6, iclass 18, count 0 2006.201.03:57:05.99#ibcon#read 6, iclass 18, count 0 2006.201.03:57:05.99#ibcon#end of sib2, iclass 18, count 0 2006.201.03:57:05.99#ibcon#*after write, iclass 18, count 0 2006.201.03:57:05.99#ibcon#*before return 0, iclass 18, count 0 2006.201.03:57:05.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:05.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:05.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:57:05.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:57:05.99$vck44/va=1,8 2006.201.03:57:05.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.03:57:05.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.03:57:05.99#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:05.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:05.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:05.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:05.99#ibcon#enter wrdev, iclass 20, count 2 2006.201.03:57:05.99#ibcon#first serial, iclass 20, count 2 2006.201.03:57:05.99#ibcon#enter sib2, iclass 20, count 2 2006.201.03:57:05.99#ibcon#flushed, iclass 20, count 2 2006.201.03:57:05.99#ibcon#about to write, iclass 20, count 2 2006.201.03:57:05.99#ibcon#wrote, iclass 20, count 2 2006.201.03:57:05.99#ibcon#about to read 3, iclass 20, count 2 2006.201.03:57:06.01#ibcon#read 3, iclass 20, count 2 2006.201.03:57:06.01#ibcon#about to read 4, iclass 20, count 2 2006.201.03:57:06.01#ibcon#read 4, iclass 20, count 2 2006.201.03:57:06.01#ibcon#about to read 5, iclass 20, count 2 2006.201.03:57:06.01#ibcon#read 5, iclass 20, count 2 2006.201.03:57:06.01#ibcon#about to read 6, iclass 20, count 2 2006.201.03:57:06.01#ibcon#read 6, iclass 20, count 2 2006.201.03:57:06.01#ibcon#end of sib2, iclass 20, count 2 2006.201.03:57:06.01#ibcon#*mode == 0, iclass 20, count 2 2006.201.03:57:06.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.03:57:06.01#ibcon#[25=AT01-08\r\n] 2006.201.03:57:06.01#ibcon#*before write, iclass 20, count 2 2006.201.03:57:06.01#ibcon#enter sib2, iclass 20, count 2 2006.201.03:57:06.01#ibcon#flushed, iclass 20, count 2 2006.201.03:57:06.01#ibcon#about to write, iclass 20, count 2 2006.201.03:57:06.01#ibcon#wrote, iclass 20, count 2 2006.201.03:57:06.01#ibcon#about to read 3, iclass 20, count 2 2006.201.03:57:06.04#ibcon#read 3, iclass 20, count 2 2006.201.03:57:06.04#ibcon#about to read 4, iclass 20, count 2 2006.201.03:57:06.04#ibcon#read 4, iclass 20, count 2 2006.201.03:57:06.04#ibcon#about to read 5, iclass 20, count 2 2006.201.03:57:06.04#ibcon#read 5, iclass 20, count 2 2006.201.03:57:06.04#ibcon#about to read 6, iclass 20, count 2 2006.201.03:57:06.04#ibcon#read 6, iclass 20, count 2 2006.201.03:57:06.04#ibcon#end of sib2, iclass 20, count 2 2006.201.03:57:06.04#ibcon#*after write, iclass 20, count 2 2006.201.03:57:06.04#ibcon#*before return 0, iclass 20, count 2 2006.201.03:57:06.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:06.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:06.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.03:57:06.04#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:06.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:06.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:06.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:06.16#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:57:06.16#ibcon#first serial, iclass 20, count 0 2006.201.03:57:06.16#ibcon#enter sib2, iclass 20, count 0 2006.201.03:57:06.16#ibcon#flushed, iclass 20, count 0 2006.201.03:57:06.16#ibcon#about to write, iclass 20, count 0 2006.201.03:57:06.16#ibcon#wrote, iclass 20, count 0 2006.201.03:57:06.16#ibcon#about to read 3, iclass 20, count 0 2006.201.03:57:06.18#ibcon#read 3, iclass 20, count 0 2006.201.03:57:06.18#ibcon#about to read 4, iclass 20, count 0 2006.201.03:57:06.18#ibcon#read 4, iclass 20, count 0 2006.201.03:57:06.18#ibcon#about to read 5, iclass 20, count 0 2006.201.03:57:06.18#ibcon#read 5, iclass 20, count 0 2006.201.03:57:06.18#ibcon#about to read 6, iclass 20, count 0 2006.201.03:57:06.18#ibcon#read 6, iclass 20, count 0 2006.201.03:57:06.18#ibcon#end of sib2, iclass 20, count 0 2006.201.03:57:06.18#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:57:06.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:57:06.18#ibcon#[25=USB\r\n] 2006.201.03:57:06.18#ibcon#*before write, iclass 20, count 0 2006.201.03:57:06.18#ibcon#enter sib2, iclass 20, count 0 2006.201.03:57:06.18#ibcon#flushed, iclass 20, count 0 2006.201.03:57:06.18#ibcon#about to write, iclass 20, count 0 2006.201.03:57:06.18#ibcon#wrote, iclass 20, count 0 2006.201.03:57:06.18#ibcon#about to read 3, iclass 20, count 0 2006.201.03:57:06.21#ibcon#read 3, iclass 20, count 0 2006.201.03:57:06.21#ibcon#about to read 4, iclass 20, count 0 2006.201.03:57:06.21#ibcon#read 4, iclass 20, count 0 2006.201.03:57:06.21#ibcon#about to read 5, iclass 20, count 0 2006.201.03:57:06.21#ibcon#read 5, iclass 20, count 0 2006.201.03:57:06.21#ibcon#about to read 6, iclass 20, count 0 2006.201.03:57:06.21#ibcon#read 6, iclass 20, count 0 2006.201.03:57:06.21#ibcon#end of sib2, iclass 20, count 0 2006.201.03:57:06.21#ibcon#*after write, iclass 20, count 0 2006.201.03:57:06.21#ibcon#*before return 0, iclass 20, count 0 2006.201.03:57:06.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:06.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:06.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:57:06.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:57:06.21$vck44/valo=2,534.99 2006.201.03:57:06.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.03:57:06.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.03:57:06.21#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:06.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:06.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:06.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:06.21#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:57:06.21#ibcon#first serial, iclass 22, count 0 2006.201.03:57:06.21#ibcon#enter sib2, iclass 22, count 0 2006.201.03:57:06.21#ibcon#flushed, iclass 22, count 0 2006.201.03:57:06.21#ibcon#about to write, iclass 22, count 0 2006.201.03:57:06.21#ibcon#wrote, iclass 22, count 0 2006.201.03:57:06.21#ibcon#about to read 3, iclass 22, count 0 2006.201.03:57:06.23#ibcon#read 3, iclass 22, count 0 2006.201.03:57:06.23#ibcon#about to read 4, iclass 22, count 0 2006.201.03:57:06.23#ibcon#read 4, iclass 22, count 0 2006.201.03:57:06.23#ibcon#about to read 5, iclass 22, count 0 2006.201.03:57:06.23#ibcon#read 5, iclass 22, count 0 2006.201.03:57:06.23#ibcon#about to read 6, iclass 22, count 0 2006.201.03:57:06.23#ibcon#read 6, iclass 22, count 0 2006.201.03:57:06.23#ibcon#end of sib2, iclass 22, count 0 2006.201.03:57:06.23#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:57:06.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:57:06.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.03:57:06.23#ibcon#*before write, iclass 22, count 0 2006.201.03:57:06.23#ibcon#enter sib2, iclass 22, count 0 2006.201.03:57:06.23#ibcon#flushed, iclass 22, count 0 2006.201.03:57:06.23#ibcon#about to write, iclass 22, count 0 2006.201.03:57:06.23#ibcon#wrote, iclass 22, count 0 2006.201.03:57:06.23#ibcon#about to read 3, iclass 22, count 0 2006.201.03:57:06.27#ibcon#read 3, iclass 22, count 0 2006.201.03:57:06.27#ibcon#about to read 4, iclass 22, count 0 2006.201.03:57:06.27#ibcon#read 4, iclass 22, count 0 2006.201.03:57:06.27#ibcon#about to read 5, iclass 22, count 0 2006.201.03:57:06.27#ibcon#read 5, iclass 22, count 0 2006.201.03:57:06.27#ibcon#about to read 6, iclass 22, count 0 2006.201.03:57:06.27#ibcon#read 6, iclass 22, count 0 2006.201.03:57:06.27#ibcon#end of sib2, iclass 22, count 0 2006.201.03:57:06.27#ibcon#*after write, iclass 22, count 0 2006.201.03:57:06.27#ibcon#*before return 0, iclass 22, count 0 2006.201.03:57:06.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:06.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:06.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:57:06.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:57:06.27$vck44/va=2,7 2006.201.03:57:06.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.03:57:06.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.03:57:06.27#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:06.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:06.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:06.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:06.33#ibcon#enter wrdev, iclass 24, count 2 2006.201.03:57:06.33#ibcon#first serial, iclass 24, count 2 2006.201.03:57:06.33#ibcon#enter sib2, iclass 24, count 2 2006.201.03:57:06.33#ibcon#flushed, iclass 24, count 2 2006.201.03:57:06.33#ibcon#about to write, iclass 24, count 2 2006.201.03:57:06.33#ibcon#wrote, iclass 24, count 2 2006.201.03:57:06.33#ibcon#about to read 3, iclass 24, count 2 2006.201.03:57:06.35#ibcon#read 3, iclass 24, count 2 2006.201.03:57:06.35#ibcon#about to read 4, iclass 24, count 2 2006.201.03:57:06.35#ibcon#read 4, iclass 24, count 2 2006.201.03:57:06.35#ibcon#about to read 5, iclass 24, count 2 2006.201.03:57:06.35#ibcon#read 5, iclass 24, count 2 2006.201.03:57:06.35#ibcon#about to read 6, iclass 24, count 2 2006.201.03:57:06.35#ibcon#read 6, iclass 24, count 2 2006.201.03:57:06.35#ibcon#end of sib2, iclass 24, count 2 2006.201.03:57:06.35#ibcon#*mode == 0, iclass 24, count 2 2006.201.03:57:06.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.03:57:06.35#ibcon#[25=AT02-07\r\n] 2006.201.03:57:06.35#ibcon#*before write, iclass 24, count 2 2006.201.03:57:06.35#ibcon#enter sib2, iclass 24, count 2 2006.201.03:57:06.35#ibcon#flushed, iclass 24, count 2 2006.201.03:57:06.35#ibcon#about to write, iclass 24, count 2 2006.201.03:57:06.35#ibcon#wrote, iclass 24, count 2 2006.201.03:57:06.35#ibcon#about to read 3, iclass 24, count 2 2006.201.03:57:06.38#ibcon#read 3, iclass 24, count 2 2006.201.03:57:06.38#ibcon#about to read 4, iclass 24, count 2 2006.201.03:57:06.38#ibcon#read 4, iclass 24, count 2 2006.201.03:57:06.38#ibcon#about to read 5, iclass 24, count 2 2006.201.03:57:06.38#ibcon#read 5, iclass 24, count 2 2006.201.03:57:06.38#ibcon#about to read 6, iclass 24, count 2 2006.201.03:57:06.38#ibcon#read 6, iclass 24, count 2 2006.201.03:57:06.38#ibcon#end of sib2, iclass 24, count 2 2006.201.03:57:06.38#ibcon#*after write, iclass 24, count 2 2006.201.03:57:06.38#ibcon#*before return 0, iclass 24, count 2 2006.201.03:57:06.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:06.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:06.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.03:57:06.38#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:06.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:06.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:06.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:06.50#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:57:06.50#ibcon#first serial, iclass 24, count 0 2006.201.03:57:06.50#ibcon#enter sib2, iclass 24, count 0 2006.201.03:57:06.50#ibcon#flushed, iclass 24, count 0 2006.201.03:57:06.50#ibcon#about to write, iclass 24, count 0 2006.201.03:57:06.50#ibcon#wrote, iclass 24, count 0 2006.201.03:57:06.50#ibcon#about to read 3, iclass 24, count 0 2006.201.03:57:06.52#ibcon#read 3, iclass 24, count 0 2006.201.03:57:06.52#ibcon#about to read 4, iclass 24, count 0 2006.201.03:57:06.52#ibcon#read 4, iclass 24, count 0 2006.201.03:57:06.52#ibcon#about to read 5, iclass 24, count 0 2006.201.03:57:06.52#ibcon#read 5, iclass 24, count 0 2006.201.03:57:06.52#ibcon#about to read 6, iclass 24, count 0 2006.201.03:57:06.52#ibcon#read 6, iclass 24, count 0 2006.201.03:57:06.52#ibcon#end of sib2, iclass 24, count 0 2006.201.03:57:06.52#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:57:06.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:57:06.52#ibcon#[25=USB\r\n] 2006.201.03:57:06.52#ibcon#*before write, iclass 24, count 0 2006.201.03:57:06.52#ibcon#enter sib2, iclass 24, count 0 2006.201.03:57:06.52#ibcon#flushed, iclass 24, count 0 2006.201.03:57:06.52#ibcon#about to write, iclass 24, count 0 2006.201.03:57:06.52#ibcon#wrote, iclass 24, count 0 2006.201.03:57:06.52#ibcon#about to read 3, iclass 24, count 0 2006.201.03:57:06.55#ibcon#read 3, iclass 24, count 0 2006.201.03:57:06.55#ibcon#about to read 4, iclass 24, count 0 2006.201.03:57:06.55#ibcon#read 4, iclass 24, count 0 2006.201.03:57:06.55#ibcon#about to read 5, iclass 24, count 0 2006.201.03:57:06.55#ibcon#read 5, iclass 24, count 0 2006.201.03:57:06.55#ibcon#about to read 6, iclass 24, count 0 2006.201.03:57:06.55#ibcon#read 6, iclass 24, count 0 2006.201.03:57:06.55#ibcon#end of sib2, iclass 24, count 0 2006.201.03:57:06.55#ibcon#*after write, iclass 24, count 0 2006.201.03:57:06.55#ibcon#*before return 0, iclass 24, count 0 2006.201.03:57:06.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:06.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:06.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:57:06.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:57:06.55$vck44/valo=3,564.99 2006.201.03:57:06.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.03:57:06.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.03:57:06.55#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:06.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:06.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:06.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:06.55#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:57:06.55#ibcon#first serial, iclass 26, count 0 2006.201.03:57:06.55#ibcon#enter sib2, iclass 26, count 0 2006.201.03:57:06.55#ibcon#flushed, iclass 26, count 0 2006.201.03:57:06.55#ibcon#about to write, iclass 26, count 0 2006.201.03:57:06.55#ibcon#wrote, iclass 26, count 0 2006.201.03:57:06.55#ibcon#about to read 3, iclass 26, count 0 2006.201.03:57:06.57#ibcon#read 3, iclass 26, count 0 2006.201.03:57:06.57#ibcon#about to read 4, iclass 26, count 0 2006.201.03:57:06.57#ibcon#read 4, iclass 26, count 0 2006.201.03:57:06.57#ibcon#about to read 5, iclass 26, count 0 2006.201.03:57:06.57#ibcon#read 5, iclass 26, count 0 2006.201.03:57:06.57#ibcon#about to read 6, iclass 26, count 0 2006.201.03:57:06.57#ibcon#read 6, iclass 26, count 0 2006.201.03:57:06.57#ibcon#end of sib2, iclass 26, count 0 2006.201.03:57:06.57#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:57:06.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:57:06.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.03:57:06.57#ibcon#*before write, iclass 26, count 0 2006.201.03:57:06.57#ibcon#enter sib2, iclass 26, count 0 2006.201.03:57:06.57#ibcon#flushed, iclass 26, count 0 2006.201.03:57:06.57#ibcon#about to write, iclass 26, count 0 2006.201.03:57:06.57#ibcon#wrote, iclass 26, count 0 2006.201.03:57:06.57#ibcon#about to read 3, iclass 26, count 0 2006.201.03:57:06.61#ibcon#read 3, iclass 26, count 0 2006.201.03:57:06.61#ibcon#about to read 4, iclass 26, count 0 2006.201.03:57:06.61#ibcon#read 4, iclass 26, count 0 2006.201.03:57:06.61#ibcon#about to read 5, iclass 26, count 0 2006.201.03:57:06.61#ibcon#read 5, iclass 26, count 0 2006.201.03:57:06.61#ibcon#about to read 6, iclass 26, count 0 2006.201.03:57:06.61#ibcon#read 6, iclass 26, count 0 2006.201.03:57:06.61#ibcon#end of sib2, iclass 26, count 0 2006.201.03:57:06.61#ibcon#*after write, iclass 26, count 0 2006.201.03:57:06.61#ibcon#*before return 0, iclass 26, count 0 2006.201.03:57:06.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:06.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:06.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:57:06.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:57:06.61$vck44/va=3,8 2006.201.03:57:06.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.03:57:06.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.03:57:06.61#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:06.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:06.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:06.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:06.67#ibcon#enter wrdev, iclass 28, count 2 2006.201.03:57:06.67#ibcon#first serial, iclass 28, count 2 2006.201.03:57:06.67#ibcon#enter sib2, iclass 28, count 2 2006.201.03:57:06.67#ibcon#flushed, iclass 28, count 2 2006.201.03:57:06.67#ibcon#about to write, iclass 28, count 2 2006.201.03:57:06.67#ibcon#wrote, iclass 28, count 2 2006.201.03:57:06.67#ibcon#about to read 3, iclass 28, count 2 2006.201.03:57:06.69#ibcon#read 3, iclass 28, count 2 2006.201.03:57:06.69#ibcon#about to read 4, iclass 28, count 2 2006.201.03:57:06.69#ibcon#read 4, iclass 28, count 2 2006.201.03:57:06.69#ibcon#about to read 5, iclass 28, count 2 2006.201.03:57:06.69#ibcon#read 5, iclass 28, count 2 2006.201.03:57:06.69#ibcon#about to read 6, iclass 28, count 2 2006.201.03:57:06.69#ibcon#read 6, iclass 28, count 2 2006.201.03:57:06.69#ibcon#end of sib2, iclass 28, count 2 2006.201.03:57:06.69#ibcon#*mode == 0, iclass 28, count 2 2006.201.03:57:06.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.03:57:06.69#ibcon#[25=AT03-08\r\n] 2006.201.03:57:06.69#ibcon#*before write, iclass 28, count 2 2006.201.03:57:06.69#ibcon#enter sib2, iclass 28, count 2 2006.201.03:57:06.69#ibcon#flushed, iclass 28, count 2 2006.201.03:57:06.69#ibcon#about to write, iclass 28, count 2 2006.201.03:57:06.69#ibcon#wrote, iclass 28, count 2 2006.201.03:57:06.69#ibcon#about to read 3, iclass 28, count 2 2006.201.03:57:06.73#ibcon#read 3, iclass 28, count 2 2006.201.03:57:06.73#ibcon#about to read 4, iclass 28, count 2 2006.201.03:57:06.73#ibcon#read 4, iclass 28, count 2 2006.201.03:57:06.73#ibcon#about to read 5, iclass 28, count 2 2006.201.03:57:06.73#ibcon#read 5, iclass 28, count 2 2006.201.03:57:06.73#ibcon#about to read 6, iclass 28, count 2 2006.201.03:57:06.73#ibcon#read 6, iclass 28, count 2 2006.201.03:57:06.73#ibcon#end of sib2, iclass 28, count 2 2006.201.03:57:06.73#ibcon#*after write, iclass 28, count 2 2006.201.03:57:06.73#ibcon#*before return 0, iclass 28, count 2 2006.201.03:57:06.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:06.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:06.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.03:57:06.73#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:06.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:06.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:06.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:06.85#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:57:06.85#ibcon#first serial, iclass 28, count 0 2006.201.03:57:06.85#ibcon#enter sib2, iclass 28, count 0 2006.201.03:57:06.85#ibcon#flushed, iclass 28, count 0 2006.201.03:57:06.85#ibcon#about to write, iclass 28, count 0 2006.201.03:57:06.85#ibcon#wrote, iclass 28, count 0 2006.201.03:57:06.85#ibcon#about to read 3, iclass 28, count 0 2006.201.03:57:06.87#ibcon#read 3, iclass 28, count 0 2006.201.03:57:06.87#ibcon#about to read 4, iclass 28, count 0 2006.201.03:57:06.87#ibcon#read 4, iclass 28, count 0 2006.201.03:57:06.87#ibcon#about to read 5, iclass 28, count 0 2006.201.03:57:06.87#ibcon#read 5, iclass 28, count 0 2006.201.03:57:06.87#ibcon#about to read 6, iclass 28, count 0 2006.201.03:57:06.87#ibcon#read 6, iclass 28, count 0 2006.201.03:57:06.87#ibcon#end of sib2, iclass 28, count 0 2006.201.03:57:06.87#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:57:06.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:57:06.87#ibcon#[25=USB\r\n] 2006.201.03:57:06.87#ibcon#*before write, iclass 28, count 0 2006.201.03:57:06.87#ibcon#enter sib2, iclass 28, count 0 2006.201.03:57:06.87#ibcon#flushed, iclass 28, count 0 2006.201.03:57:06.87#ibcon#about to write, iclass 28, count 0 2006.201.03:57:06.87#ibcon#wrote, iclass 28, count 0 2006.201.03:57:06.87#ibcon#about to read 3, iclass 28, count 0 2006.201.03:57:06.90#ibcon#read 3, iclass 28, count 0 2006.201.03:57:06.90#ibcon#about to read 4, iclass 28, count 0 2006.201.03:57:06.90#ibcon#read 4, iclass 28, count 0 2006.201.03:57:06.90#ibcon#about to read 5, iclass 28, count 0 2006.201.03:57:06.90#ibcon#read 5, iclass 28, count 0 2006.201.03:57:06.90#ibcon#about to read 6, iclass 28, count 0 2006.201.03:57:06.90#ibcon#read 6, iclass 28, count 0 2006.201.03:57:06.90#ibcon#end of sib2, iclass 28, count 0 2006.201.03:57:06.90#ibcon#*after write, iclass 28, count 0 2006.201.03:57:06.90#ibcon#*before return 0, iclass 28, count 0 2006.201.03:57:06.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:06.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:06.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:57:06.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:57:06.90$vck44/valo=4,624.99 2006.201.03:57:06.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.03:57:06.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.03:57:06.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:06.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:06.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:06.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:06.90#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:57:06.90#ibcon#first serial, iclass 30, count 0 2006.201.03:57:06.90#ibcon#enter sib2, iclass 30, count 0 2006.201.03:57:06.90#ibcon#flushed, iclass 30, count 0 2006.201.03:57:06.90#ibcon#about to write, iclass 30, count 0 2006.201.03:57:06.90#ibcon#wrote, iclass 30, count 0 2006.201.03:57:06.90#ibcon#about to read 3, iclass 30, count 0 2006.201.03:57:06.92#ibcon#read 3, iclass 30, count 0 2006.201.03:57:06.92#ibcon#about to read 4, iclass 30, count 0 2006.201.03:57:06.92#ibcon#read 4, iclass 30, count 0 2006.201.03:57:06.92#ibcon#about to read 5, iclass 30, count 0 2006.201.03:57:06.92#ibcon#read 5, iclass 30, count 0 2006.201.03:57:06.92#ibcon#about to read 6, iclass 30, count 0 2006.201.03:57:06.92#ibcon#read 6, iclass 30, count 0 2006.201.03:57:06.92#ibcon#end of sib2, iclass 30, count 0 2006.201.03:57:06.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:57:06.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:57:06.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.03:57:06.92#ibcon#*before write, iclass 30, count 0 2006.201.03:57:06.92#ibcon#enter sib2, iclass 30, count 0 2006.201.03:57:06.92#ibcon#flushed, iclass 30, count 0 2006.201.03:57:06.92#ibcon#about to write, iclass 30, count 0 2006.201.03:57:06.92#ibcon#wrote, iclass 30, count 0 2006.201.03:57:06.92#ibcon#about to read 3, iclass 30, count 0 2006.201.03:57:06.96#ibcon#read 3, iclass 30, count 0 2006.201.03:57:06.96#ibcon#about to read 4, iclass 30, count 0 2006.201.03:57:06.96#ibcon#read 4, iclass 30, count 0 2006.201.03:57:06.96#ibcon#about to read 5, iclass 30, count 0 2006.201.03:57:06.96#ibcon#read 5, iclass 30, count 0 2006.201.03:57:06.96#ibcon#about to read 6, iclass 30, count 0 2006.201.03:57:06.96#ibcon#read 6, iclass 30, count 0 2006.201.03:57:06.96#ibcon#end of sib2, iclass 30, count 0 2006.201.03:57:06.96#ibcon#*after write, iclass 30, count 0 2006.201.03:57:06.96#ibcon#*before return 0, iclass 30, count 0 2006.201.03:57:06.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:06.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:06.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:57:06.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:57:06.96$vck44/va=4,7 2006.201.03:57:06.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.03:57:06.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.03:57:06.96#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:06.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:07.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:07.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:07.02#ibcon#enter wrdev, iclass 32, count 2 2006.201.03:57:07.02#ibcon#first serial, iclass 32, count 2 2006.201.03:57:07.02#ibcon#enter sib2, iclass 32, count 2 2006.201.03:57:07.02#ibcon#flushed, iclass 32, count 2 2006.201.03:57:07.02#ibcon#about to write, iclass 32, count 2 2006.201.03:57:07.02#ibcon#wrote, iclass 32, count 2 2006.201.03:57:07.02#ibcon#about to read 3, iclass 32, count 2 2006.201.03:57:07.04#ibcon#read 3, iclass 32, count 2 2006.201.03:57:07.04#ibcon#about to read 4, iclass 32, count 2 2006.201.03:57:07.04#ibcon#read 4, iclass 32, count 2 2006.201.03:57:07.04#ibcon#about to read 5, iclass 32, count 2 2006.201.03:57:07.04#ibcon#read 5, iclass 32, count 2 2006.201.03:57:07.04#ibcon#about to read 6, iclass 32, count 2 2006.201.03:57:07.04#ibcon#read 6, iclass 32, count 2 2006.201.03:57:07.04#ibcon#end of sib2, iclass 32, count 2 2006.201.03:57:07.04#ibcon#*mode == 0, iclass 32, count 2 2006.201.03:57:07.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.03:57:07.04#ibcon#[25=AT04-07\r\n] 2006.201.03:57:07.04#ibcon#*before write, iclass 32, count 2 2006.201.03:57:07.04#ibcon#enter sib2, iclass 32, count 2 2006.201.03:57:07.04#ibcon#flushed, iclass 32, count 2 2006.201.03:57:07.04#ibcon#about to write, iclass 32, count 2 2006.201.03:57:07.04#ibcon#wrote, iclass 32, count 2 2006.201.03:57:07.04#ibcon#about to read 3, iclass 32, count 2 2006.201.03:57:07.07#ibcon#read 3, iclass 32, count 2 2006.201.03:57:07.07#ibcon#about to read 4, iclass 32, count 2 2006.201.03:57:07.07#ibcon#read 4, iclass 32, count 2 2006.201.03:57:07.07#ibcon#about to read 5, iclass 32, count 2 2006.201.03:57:07.07#ibcon#read 5, iclass 32, count 2 2006.201.03:57:07.07#ibcon#about to read 6, iclass 32, count 2 2006.201.03:57:07.07#ibcon#read 6, iclass 32, count 2 2006.201.03:57:07.07#ibcon#end of sib2, iclass 32, count 2 2006.201.03:57:07.07#ibcon#*after write, iclass 32, count 2 2006.201.03:57:07.07#ibcon#*before return 0, iclass 32, count 2 2006.201.03:57:07.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:07.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:07.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.03:57:07.07#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:07.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:07.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:07.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:07.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:57:07.19#ibcon#first serial, iclass 32, count 0 2006.201.03:57:07.19#ibcon#enter sib2, iclass 32, count 0 2006.201.03:57:07.19#ibcon#flushed, iclass 32, count 0 2006.201.03:57:07.19#ibcon#about to write, iclass 32, count 0 2006.201.03:57:07.19#ibcon#wrote, iclass 32, count 0 2006.201.03:57:07.19#ibcon#about to read 3, iclass 32, count 0 2006.201.03:57:07.21#ibcon#read 3, iclass 32, count 0 2006.201.03:57:07.21#ibcon#about to read 4, iclass 32, count 0 2006.201.03:57:07.21#ibcon#read 4, iclass 32, count 0 2006.201.03:57:07.21#ibcon#about to read 5, iclass 32, count 0 2006.201.03:57:07.21#ibcon#read 5, iclass 32, count 0 2006.201.03:57:07.21#ibcon#about to read 6, iclass 32, count 0 2006.201.03:57:07.21#ibcon#read 6, iclass 32, count 0 2006.201.03:57:07.21#ibcon#end of sib2, iclass 32, count 0 2006.201.03:57:07.21#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:57:07.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:57:07.21#ibcon#[25=USB\r\n] 2006.201.03:57:07.21#ibcon#*before write, iclass 32, count 0 2006.201.03:57:07.21#ibcon#enter sib2, iclass 32, count 0 2006.201.03:57:07.21#ibcon#flushed, iclass 32, count 0 2006.201.03:57:07.21#ibcon#about to write, iclass 32, count 0 2006.201.03:57:07.21#ibcon#wrote, iclass 32, count 0 2006.201.03:57:07.21#ibcon#about to read 3, iclass 32, count 0 2006.201.03:57:07.24#ibcon#read 3, iclass 32, count 0 2006.201.03:57:07.24#ibcon#about to read 4, iclass 32, count 0 2006.201.03:57:07.24#ibcon#read 4, iclass 32, count 0 2006.201.03:57:07.24#ibcon#about to read 5, iclass 32, count 0 2006.201.03:57:07.24#ibcon#read 5, iclass 32, count 0 2006.201.03:57:07.24#ibcon#about to read 6, iclass 32, count 0 2006.201.03:57:07.24#ibcon#read 6, iclass 32, count 0 2006.201.03:57:07.24#ibcon#end of sib2, iclass 32, count 0 2006.201.03:57:07.24#ibcon#*after write, iclass 32, count 0 2006.201.03:57:07.24#ibcon#*before return 0, iclass 32, count 0 2006.201.03:57:07.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:07.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:07.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:57:07.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:57:07.24$vck44/valo=5,734.99 2006.201.03:57:07.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.03:57:07.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.03:57:07.24#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:07.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:07.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:07.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:07.24#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:57:07.24#ibcon#first serial, iclass 34, count 0 2006.201.03:57:07.24#ibcon#enter sib2, iclass 34, count 0 2006.201.03:57:07.24#ibcon#flushed, iclass 34, count 0 2006.201.03:57:07.24#ibcon#about to write, iclass 34, count 0 2006.201.03:57:07.24#ibcon#wrote, iclass 34, count 0 2006.201.03:57:07.24#ibcon#about to read 3, iclass 34, count 0 2006.201.03:57:07.26#ibcon#read 3, iclass 34, count 0 2006.201.03:57:07.26#ibcon#about to read 4, iclass 34, count 0 2006.201.03:57:07.26#ibcon#read 4, iclass 34, count 0 2006.201.03:57:07.26#ibcon#about to read 5, iclass 34, count 0 2006.201.03:57:07.26#ibcon#read 5, iclass 34, count 0 2006.201.03:57:07.26#ibcon#about to read 6, iclass 34, count 0 2006.201.03:57:07.26#ibcon#read 6, iclass 34, count 0 2006.201.03:57:07.26#ibcon#end of sib2, iclass 34, count 0 2006.201.03:57:07.26#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:57:07.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:57:07.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.03:57:07.26#ibcon#*before write, iclass 34, count 0 2006.201.03:57:07.26#ibcon#enter sib2, iclass 34, count 0 2006.201.03:57:07.26#ibcon#flushed, iclass 34, count 0 2006.201.03:57:07.26#ibcon#about to write, iclass 34, count 0 2006.201.03:57:07.26#ibcon#wrote, iclass 34, count 0 2006.201.03:57:07.26#ibcon#about to read 3, iclass 34, count 0 2006.201.03:57:07.30#ibcon#read 3, iclass 34, count 0 2006.201.03:57:07.30#ibcon#about to read 4, iclass 34, count 0 2006.201.03:57:07.30#ibcon#read 4, iclass 34, count 0 2006.201.03:57:07.30#ibcon#about to read 5, iclass 34, count 0 2006.201.03:57:07.30#ibcon#read 5, iclass 34, count 0 2006.201.03:57:07.30#ibcon#about to read 6, iclass 34, count 0 2006.201.03:57:07.30#ibcon#read 6, iclass 34, count 0 2006.201.03:57:07.30#ibcon#end of sib2, iclass 34, count 0 2006.201.03:57:07.30#ibcon#*after write, iclass 34, count 0 2006.201.03:57:07.30#ibcon#*before return 0, iclass 34, count 0 2006.201.03:57:07.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:07.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:07.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:57:07.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:57:07.30$vck44/va=5,4 2006.201.03:57:07.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.03:57:07.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.03:57:07.30#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:07.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:07.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:07.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:07.36#ibcon#enter wrdev, iclass 36, count 2 2006.201.03:57:07.36#ibcon#first serial, iclass 36, count 2 2006.201.03:57:07.36#ibcon#enter sib2, iclass 36, count 2 2006.201.03:57:07.36#ibcon#flushed, iclass 36, count 2 2006.201.03:57:07.36#ibcon#about to write, iclass 36, count 2 2006.201.03:57:07.36#ibcon#wrote, iclass 36, count 2 2006.201.03:57:07.36#ibcon#about to read 3, iclass 36, count 2 2006.201.03:57:07.38#ibcon#read 3, iclass 36, count 2 2006.201.03:57:07.38#ibcon#about to read 4, iclass 36, count 2 2006.201.03:57:07.38#ibcon#read 4, iclass 36, count 2 2006.201.03:57:07.38#ibcon#about to read 5, iclass 36, count 2 2006.201.03:57:07.38#ibcon#read 5, iclass 36, count 2 2006.201.03:57:07.38#ibcon#about to read 6, iclass 36, count 2 2006.201.03:57:07.38#ibcon#read 6, iclass 36, count 2 2006.201.03:57:07.38#ibcon#end of sib2, iclass 36, count 2 2006.201.03:57:07.38#ibcon#*mode == 0, iclass 36, count 2 2006.201.03:57:07.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.03:57:07.38#ibcon#[25=AT05-04\r\n] 2006.201.03:57:07.38#ibcon#*before write, iclass 36, count 2 2006.201.03:57:07.38#ibcon#enter sib2, iclass 36, count 2 2006.201.03:57:07.38#ibcon#flushed, iclass 36, count 2 2006.201.03:57:07.38#ibcon#about to write, iclass 36, count 2 2006.201.03:57:07.38#ibcon#wrote, iclass 36, count 2 2006.201.03:57:07.38#ibcon#about to read 3, iclass 36, count 2 2006.201.03:57:07.41#ibcon#read 3, iclass 36, count 2 2006.201.03:57:07.41#ibcon#about to read 4, iclass 36, count 2 2006.201.03:57:07.41#ibcon#read 4, iclass 36, count 2 2006.201.03:57:07.41#ibcon#about to read 5, iclass 36, count 2 2006.201.03:57:07.41#ibcon#read 5, iclass 36, count 2 2006.201.03:57:07.41#ibcon#about to read 6, iclass 36, count 2 2006.201.03:57:07.41#ibcon#read 6, iclass 36, count 2 2006.201.03:57:07.41#ibcon#end of sib2, iclass 36, count 2 2006.201.03:57:07.41#ibcon#*after write, iclass 36, count 2 2006.201.03:57:07.41#ibcon#*before return 0, iclass 36, count 2 2006.201.03:57:07.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:07.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:07.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.03:57:07.41#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:07.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:07.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:07.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:07.53#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:57:07.53#ibcon#first serial, iclass 36, count 0 2006.201.03:57:07.53#ibcon#enter sib2, iclass 36, count 0 2006.201.03:57:07.53#ibcon#flushed, iclass 36, count 0 2006.201.03:57:07.53#ibcon#about to write, iclass 36, count 0 2006.201.03:57:07.53#ibcon#wrote, iclass 36, count 0 2006.201.03:57:07.53#ibcon#about to read 3, iclass 36, count 0 2006.201.03:57:07.55#ibcon#read 3, iclass 36, count 0 2006.201.03:57:07.55#ibcon#about to read 4, iclass 36, count 0 2006.201.03:57:07.55#ibcon#read 4, iclass 36, count 0 2006.201.03:57:07.55#ibcon#about to read 5, iclass 36, count 0 2006.201.03:57:07.55#ibcon#read 5, iclass 36, count 0 2006.201.03:57:07.55#ibcon#about to read 6, iclass 36, count 0 2006.201.03:57:07.55#ibcon#read 6, iclass 36, count 0 2006.201.03:57:07.55#ibcon#end of sib2, iclass 36, count 0 2006.201.03:57:07.55#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:57:07.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:57:07.55#ibcon#[25=USB\r\n] 2006.201.03:57:07.55#ibcon#*before write, iclass 36, count 0 2006.201.03:57:07.55#ibcon#enter sib2, iclass 36, count 0 2006.201.03:57:07.55#ibcon#flushed, iclass 36, count 0 2006.201.03:57:07.55#ibcon#about to write, iclass 36, count 0 2006.201.03:57:07.55#ibcon#wrote, iclass 36, count 0 2006.201.03:57:07.55#ibcon#about to read 3, iclass 36, count 0 2006.201.03:57:07.58#ibcon#read 3, iclass 36, count 0 2006.201.03:57:07.58#ibcon#about to read 4, iclass 36, count 0 2006.201.03:57:07.58#ibcon#read 4, iclass 36, count 0 2006.201.03:57:07.58#ibcon#about to read 5, iclass 36, count 0 2006.201.03:57:07.58#ibcon#read 5, iclass 36, count 0 2006.201.03:57:07.58#ibcon#about to read 6, iclass 36, count 0 2006.201.03:57:07.58#ibcon#read 6, iclass 36, count 0 2006.201.03:57:07.58#ibcon#end of sib2, iclass 36, count 0 2006.201.03:57:07.58#ibcon#*after write, iclass 36, count 0 2006.201.03:57:07.58#ibcon#*before return 0, iclass 36, count 0 2006.201.03:57:07.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:07.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:07.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:57:07.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:57:07.58$vck44/valo=6,814.99 2006.201.03:57:07.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.03:57:07.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.03:57:07.58#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:07.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:07.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:07.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:07.58#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:57:07.58#ibcon#first serial, iclass 38, count 0 2006.201.03:57:07.58#ibcon#enter sib2, iclass 38, count 0 2006.201.03:57:07.58#ibcon#flushed, iclass 38, count 0 2006.201.03:57:07.58#ibcon#about to write, iclass 38, count 0 2006.201.03:57:07.58#ibcon#wrote, iclass 38, count 0 2006.201.03:57:07.58#ibcon#about to read 3, iclass 38, count 0 2006.201.03:57:07.60#ibcon#read 3, iclass 38, count 0 2006.201.03:57:07.60#ibcon#about to read 4, iclass 38, count 0 2006.201.03:57:07.60#ibcon#read 4, iclass 38, count 0 2006.201.03:57:07.60#ibcon#about to read 5, iclass 38, count 0 2006.201.03:57:07.60#ibcon#read 5, iclass 38, count 0 2006.201.03:57:07.60#ibcon#about to read 6, iclass 38, count 0 2006.201.03:57:07.60#ibcon#read 6, iclass 38, count 0 2006.201.03:57:07.60#ibcon#end of sib2, iclass 38, count 0 2006.201.03:57:07.60#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:57:07.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:57:07.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.03:57:07.60#ibcon#*before write, iclass 38, count 0 2006.201.03:57:07.60#ibcon#enter sib2, iclass 38, count 0 2006.201.03:57:07.60#ibcon#flushed, iclass 38, count 0 2006.201.03:57:07.60#ibcon#about to write, iclass 38, count 0 2006.201.03:57:07.60#ibcon#wrote, iclass 38, count 0 2006.201.03:57:07.60#ibcon#about to read 3, iclass 38, count 0 2006.201.03:57:07.64#ibcon#read 3, iclass 38, count 0 2006.201.03:57:07.64#ibcon#about to read 4, iclass 38, count 0 2006.201.03:57:07.64#ibcon#read 4, iclass 38, count 0 2006.201.03:57:07.64#ibcon#about to read 5, iclass 38, count 0 2006.201.03:57:07.64#ibcon#read 5, iclass 38, count 0 2006.201.03:57:07.64#ibcon#about to read 6, iclass 38, count 0 2006.201.03:57:07.64#ibcon#read 6, iclass 38, count 0 2006.201.03:57:07.64#ibcon#end of sib2, iclass 38, count 0 2006.201.03:57:07.64#ibcon#*after write, iclass 38, count 0 2006.201.03:57:07.64#ibcon#*before return 0, iclass 38, count 0 2006.201.03:57:07.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:07.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:07.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:57:07.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:57:07.64$vck44/va=6,5 2006.201.03:57:07.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.03:57:07.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.03:57:07.64#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:07.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:07.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:07.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:07.70#ibcon#enter wrdev, iclass 40, count 2 2006.201.03:57:07.70#ibcon#first serial, iclass 40, count 2 2006.201.03:57:07.70#ibcon#enter sib2, iclass 40, count 2 2006.201.03:57:07.70#ibcon#flushed, iclass 40, count 2 2006.201.03:57:07.70#ibcon#about to write, iclass 40, count 2 2006.201.03:57:07.70#ibcon#wrote, iclass 40, count 2 2006.201.03:57:07.70#ibcon#about to read 3, iclass 40, count 2 2006.201.03:57:07.72#ibcon#read 3, iclass 40, count 2 2006.201.03:57:07.72#ibcon#about to read 4, iclass 40, count 2 2006.201.03:57:07.72#ibcon#read 4, iclass 40, count 2 2006.201.03:57:07.72#ibcon#about to read 5, iclass 40, count 2 2006.201.03:57:07.72#ibcon#read 5, iclass 40, count 2 2006.201.03:57:07.72#ibcon#about to read 6, iclass 40, count 2 2006.201.03:57:07.72#ibcon#read 6, iclass 40, count 2 2006.201.03:57:07.72#ibcon#end of sib2, iclass 40, count 2 2006.201.03:57:07.72#ibcon#*mode == 0, iclass 40, count 2 2006.201.03:57:07.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.03:57:07.72#ibcon#[25=AT06-05\r\n] 2006.201.03:57:07.72#ibcon#*before write, iclass 40, count 2 2006.201.03:57:07.72#ibcon#enter sib2, iclass 40, count 2 2006.201.03:57:07.72#ibcon#flushed, iclass 40, count 2 2006.201.03:57:07.72#ibcon#about to write, iclass 40, count 2 2006.201.03:57:07.72#ibcon#wrote, iclass 40, count 2 2006.201.03:57:07.72#ibcon#about to read 3, iclass 40, count 2 2006.201.03:57:07.75#ibcon#read 3, iclass 40, count 2 2006.201.03:57:07.75#ibcon#about to read 4, iclass 40, count 2 2006.201.03:57:07.75#ibcon#read 4, iclass 40, count 2 2006.201.03:57:07.75#ibcon#about to read 5, iclass 40, count 2 2006.201.03:57:07.75#ibcon#read 5, iclass 40, count 2 2006.201.03:57:07.75#ibcon#about to read 6, iclass 40, count 2 2006.201.03:57:07.75#ibcon#read 6, iclass 40, count 2 2006.201.03:57:07.75#ibcon#end of sib2, iclass 40, count 2 2006.201.03:57:07.75#ibcon#*after write, iclass 40, count 2 2006.201.03:57:07.75#ibcon#*before return 0, iclass 40, count 2 2006.201.03:57:07.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:07.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:07.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.03:57:07.75#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:07.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:07.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:07.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:07.87#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:57:07.87#ibcon#first serial, iclass 40, count 0 2006.201.03:57:07.87#ibcon#enter sib2, iclass 40, count 0 2006.201.03:57:07.87#ibcon#flushed, iclass 40, count 0 2006.201.03:57:07.87#ibcon#about to write, iclass 40, count 0 2006.201.03:57:07.87#ibcon#wrote, iclass 40, count 0 2006.201.03:57:07.87#ibcon#about to read 3, iclass 40, count 0 2006.201.03:57:07.89#ibcon#read 3, iclass 40, count 0 2006.201.03:57:07.89#ibcon#about to read 4, iclass 40, count 0 2006.201.03:57:07.89#ibcon#read 4, iclass 40, count 0 2006.201.03:57:07.89#ibcon#about to read 5, iclass 40, count 0 2006.201.03:57:07.89#ibcon#read 5, iclass 40, count 0 2006.201.03:57:07.89#ibcon#about to read 6, iclass 40, count 0 2006.201.03:57:07.89#ibcon#read 6, iclass 40, count 0 2006.201.03:57:07.89#ibcon#end of sib2, iclass 40, count 0 2006.201.03:57:07.89#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:57:07.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:57:07.89#ibcon#[25=USB\r\n] 2006.201.03:57:07.89#ibcon#*before write, iclass 40, count 0 2006.201.03:57:07.89#ibcon#enter sib2, iclass 40, count 0 2006.201.03:57:07.89#ibcon#flushed, iclass 40, count 0 2006.201.03:57:07.89#ibcon#about to write, iclass 40, count 0 2006.201.03:57:07.89#ibcon#wrote, iclass 40, count 0 2006.201.03:57:07.89#ibcon#about to read 3, iclass 40, count 0 2006.201.03:57:07.92#ibcon#read 3, iclass 40, count 0 2006.201.03:57:07.92#ibcon#about to read 4, iclass 40, count 0 2006.201.03:57:07.92#ibcon#read 4, iclass 40, count 0 2006.201.03:57:07.92#ibcon#about to read 5, iclass 40, count 0 2006.201.03:57:07.92#ibcon#read 5, iclass 40, count 0 2006.201.03:57:07.92#ibcon#about to read 6, iclass 40, count 0 2006.201.03:57:07.92#ibcon#read 6, iclass 40, count 0 2006.201.03:57:07.92#ibcon#end of sib2, iclass 40, count 0 2006.201.03:57:07.92#ibcon#*after write, iclass 40, count 0 2006.201.03:57:07.92#ibcon#*before return 0, iclass 40, count 0 2006.201.03:57:07.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:07.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:07.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:57:07.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:57:07.92$vck44/valo=7,864.99 2006.201.03:57:07.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.03:57:07.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.03:57:07.92#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:07.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:07.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:07.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:07.92#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:57:07.92#ibcon#first serial, iclass 4, count 0 2006.201.03:57:07.92#ibcon#enter sib2, iclass 4, count 0 2006.201.03:57:07.92#ibcon#flushed, iclass 4, count 0 2006.201.03:57:07.92#ibcon#about to write, iclass 4, count 0 2006.201.03:57:07.92#ibcon#wrote, iclass 4, count 0 2006.201.03:57:07.92#ibcon#about to read 3, iclass 4, count 0 2006.201.03:57:07.94#ibcon#read 3, iclass 4, count 0 2006.201.03:57:07.94#ibcon#about to read 4, iclass 4, count 0 2006.201.03:57:07.94#ibcon#read 4, iclass 4, count 0 2006.201.03:57:07.94#ibcon#about to read 5, iclass 4, count 0 2006.201.03:57:07.94#ibcon#read 5, iclass 4, count 0 2006.201.03:57:07.94#ibcon#about to read 6, iclass 4, count 0 2006.201.03:57:07.94#ibcon#read 6, iclass 4, count 0 2006.201.03:57:07.94#ibcon#end of sib2, iclass 4, count 0 2006.201.03:57:07.94#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:57:07.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:57:07.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.03:57:07.94#ibcon#*before write, iclass 4, count 0 2006.201.03:57:07.94#ibcon#enter sib2, iclass 4, count 0 2006.201.03:57:07.94#ibcon#flushed, iclass 4, count 0 2006.201.03:57:07.94#ibcon#about to write, iclass 4, count 0 2006.201.03:57:07.94#ibcon#wrote, iclass 4, count 0 2006.201.03:57:07.94#ibcon#about to read 3, iclass 4, count 0 2006.201.03:57:07.98#ibcon#read 3, iclass 4, count 0 2006.201.03:57:07.98#ibcon#about to read 4, iclass 4, count 0 2006.201.03:57:07.98#ibcon#read 4, iclass 4, count 0 2006.201.03:57:07.98#ibcon#about to read 5, iclass 4, count 0 2006.201.03:57:07.98#ibcon#read 5, iclass 4, count 0 2006.201.03:57:07.98#ibcon#about to read 6, iclass 4, count 0 2006.201.03:57:07.98#ibcon#read 6, iclass 4, count 0 2006.201.03:57:07.98#ibcon#end of sib2, iclass 4, count 0 2006.201.03:57:07.98#ibcon#*after write, iclass 4, count 0 2006.201.03:57:07.98#ibcon#*before return 0, iclass 4, count 0 2006.201.03:57:07.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:07.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:07.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:57:07.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:57:07.98$vck44/va=7,5 2006.201.03:57:07.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.03:57:07.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.03:57:07.98#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:07.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:08.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:08.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:08.04#ibcon#enter wrdev, iclass 6, count 2 2006.201.03:57:08.04#ibcon#first serial, iclass 6, count 2 2006.201.03:57:08.04#ibcon#enter sib2, iclass 6, count 2 2006.201.03:57:08.04#ibcon#flushed, iclass 6, count 2 2006.201.03:57:08.04#ibcon#about to write, iclass 6, count 2 2006.201.03:57:08.04#ibcon#wrote, iclass 6, count 2 2006.201.03:57:08.04#ibcon#about to read 3, iclass 6, count 2 2006.201.03:57:08.06#ibcon#read 3, iclass 6, count 2 2006.201.03:57:08.06#ibcon#about to read 4, iclass 6, count 2 2006.201.03:57:08.06#ibcon#read 4, iclass 6, count 2 2006.201.03:57:08.06#ibcon#about to read 5, iclass 6, count 2 2006.201.03:57:08.06#ibcon#read 5, iclass 6, count 2 2006.201.03:57:08.06#ibcon#about to read 6, iclass 6, count 2 2006.201.03:57:08.06#ibcon#read 6, iclass 6, count 2 2006.201.03:57:08.06#ibcon#end of sib2, iclass 6, count 2 2006.201.03:57:08.06#ibcon#*mode == 0, iclass 6, count 2 2006.201.03:57:08.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.03:57:08.06#ibcon#[25=AT07-05\r\n] 2006.201.03:57:08.06#ibcon#*before write, iclass 6, count 2 2006.201.03:57:08.06#ibcon#enter sib2, iclass 6, count 2 2006.201.03:57:08.06#ibcon#flushed, iclass 6, count 2 2006.201.03:57:08.06#ibcon#about to write, iclass 6, count 2 2006.201.03:57:08.06#ibcon#wrote, iclass 6, count 2 2006.201.03:57:08.06#ibcon#about to read 3, iclass 6, count 2 2006.201.03:57:08.09#ibcon#read 3, iclass 6, count 2 2006.201.03:57:08.09#ibcon#about to read 4, iclass 6, count 2 2006.201.03:57:08.09#ibcon#read 4, iclass 6, count 2 2006.201.03:57:08.09#ibcon#about to read 5, iclass 6, count 2 2006.201.03:57:08.09#ibcon#read 5, iclass 6, count 2 2006.201.03:57:08.09#ibcon#about to read 6, iclass 6, count 2 2006.201.03:57:08.09#ibcon#read 6, iclass 6, count 2 2006.201.03:57:08.09#ibcon#end of sib2, iclass 6, count 2 2006.201.03:57:08.09#ibcon#*after write, iclass 6, count 2 2006.201.03:57:08.09#ibcon#*before return 0, iclass 6, count 2 2006.201.03:57:08.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:08.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:08.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.03:57:08.09#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:08.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:08.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:08.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:08.21#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:57:08.21#ibcon#first serial, iclass 6, count 0 2006.201.03:57:08.21#ibcon#enter sib2, iclass 6, count 0 2006.201.03:57:08.21#ibcon#flushed, iclass 6, count 0 2006.201.03:57:08.21#ibcon#about to write, iclass 6, count 0 2006.201.03:57:08.21#ibcon#wrote, iclass 6, count 0 2006.201.03:57:08.21#ibcon#about to read 3, iclass 6, count 0 2006.201.03:57:08.23#ibcon#read 3, iclass 6, count 0 2006.201.03:57:08.23#ibcon#about to read 4, iclass 6, count 0 2006.201.03:57:08.23#ibcon#read 4, iclass 6, count 0 2006.201.03:57:08.23#ibcon#about to read 5, iclass 6, count 0 2006.201.03:57:08.23#ibcon#read 5, iclass 6, count 0 2006.201.03:57:08.23#ibcon#about to read 6, iclass 6, count 0 2006.201.03:57:08.23#ibcon#read 6, iclass 6, count 0 2006.201.03:57:08.23#ibcon#end of sib2, iclass 6, count 0 2006.201.03:57:08.23#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:57:08.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:57:08.23#ibcon#[25=USB\r\n] 2006.201.03:57:08.23#ibcon#*before write, iclass 6, count 0 2006.201.03:57:08.23#ibcon#enter sib2, iclass 6, count 0 2006.201.03:57:08.23#ibcon#flushed, iclass 6, count 0 2006.201.03:57:08.23#ibcon#about to write, iclass 6, count 0 2006.201.03:57:08.23#ibcon#wrote, iclass 6, count 0 2006.201.03:57:08.23#ibcon#about to read 3, iclass 6, count 0 2006.201.03:57:08.26#ibcon#read 3, iclass 6, count 0 2006.201.03:57:08.26#ibcon#about to read 4, iclass 6, count 0 2006.201.03:57:08.26#ibcon#read 4, iclass 6, count 0 2006.201.03:57:08.26#ibcon#about to read 5, iclass 6, count 0 2006.201.03:57:08.26#ibcon#read 5, iclass 6, count 0 2006.201.03:57:08.26#ibcon#about to read 6, iclass 6, count 0 2006.201.03:57:08.26#ibcon#read 6, iclass 6, count 0 2006.201.03:57:08.26#ibcon#end of sib2, iclass 6, count 0 2006.201.03:57:08.26#ibcon#*after write, iclass 6, count 0 2006.201.03:57:08.26#ibcon#*before return 0, iclass 6, count 0 2006.201.03:57:08.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:08.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:08.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:57:08.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:57:08.26$vck44/valo=8,884.99 2006.201.03:57:08.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.03:57:08.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.03:57:08.26#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:08.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:08.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:08.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:08.26#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:57:08.26#ibcon#first serial, iclass 10, count 0 2006.201.03:57:08.26#ibcon#enter sib2, iclass 10, count 0 2006.201.03:57:08.26#ibcon#flushed, iclass 10, count 0 2006.201.03:57:08.26#ibcon#about to write, iclass 10, count 0 2006.201.03:57:08.26#ibcon#wrote, iclass 10, count 0 2006.201.03:57:08.26#ibcon#about to read 3, iclass 10, count 0 2006.201.03:57:08.28#ibcon#read 3, iclass 10, count 0 2006.201.03:57:08.28#ibcon#about to read 4, iclass 10, count 0 2006.201.03:57:08.28#ibcon#read 4, iclass 10, count 0 2006.201.03:57:08.28#ibcon#about to read 5, iclass 10, count 0 2006.201.03:57:08.28#ibcon#read 5, iclass 10, count 0 2006.201.03:57:08.28#ibcon#about to read 6, iclass 10, count 0 2006.201.03:57:08.28#ibcon#read 6, iclass 10, count 0 2006.201.03:57:08.28#ibcon#end of sib2, iclass 10, count 0 2006.201.03:57:08.28#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:57:08.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:57:08.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.03:57:08.28#ibcon#*before write, iclass 10, count 0 2006.201.03:57:08.28#ibcon#enter sib2, iclass 10, count 0 2006.201.03:57:08.28#ibcon#flushed, iclass 10, count 0 2006.201.03:57:08.28#ibcon#about to write, iclass 10, count 0 2006.201.03:57:08.28#ibcon#wrote, iclass 10, count 0 2006.201.03:57:08.28#ibcon#about to read 3, iclass 10, count 0 2006.201.03:57:08.32#ibcon#read 3, iclass 10, count 0 2006.201.03:57:08.32#ibcon#about to read 4, iclass 10, count 0 2006.201.03:57:08.32#ibcon#read 4, iclass 10, count 0 2006.201.03:57:08.32#ibcon#about to read 5, iclass 10, count 0 2006.201.03:57:08.32#ibcon#read 5, iclass 10, count 0 2006.201.03:57:08.32#ibcon#about to read 6, iclass 10, count 0 2006.201.03:57:08.32#ibcon#read 6, iclass 10, count 0 2006.201.03:57:08.32#ibcon#end of sib2, iclass 10, count 0 2006.201.03:57:08.32#ibcon#*after write, iclass 10, count 0 2006.201.03:57:08.32#ibcon#*before return 0, iclass 10, count 0 2006.201.03:57:08.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:08.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:08.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:57:08.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:57:08.32$vck44/va=8,4 2006.201.03:57:08.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.03:57:08.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.03:57:08.32#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:08.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:57:08.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:57:08.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:57:08.38#ibcon#enter wrdev, iclass 12, count 2 2006.201.03:57:08.38#ibcon#first serial, iclass 12, count 2 2006.201.03:57:08.38#ibcon#enter sib2, iclass 12, count 2 2006.201.03:57:08.38#ibcon#flushed, iclass 12, count 2 2006.201.03:57:08.38#ibcon#about to write, iclass 12, count 2 2006.201.03:57:08.38#ibcon#wrote, iclass 12, count 2 2006.201.03:57:08.38#ibcon#about to read 3, iclass 12, count 2 2006.201.03:57:08.40#ibcon#read 3, iclass 12, count 2 2006.201.03:57:08.40#ibcon#about to read 4, iclass 12, count 2 2006.201.03:57:08.40#ibcon#read 4, iclass 12, count 2 2006.201.03:57:08.40#ibcon#about to read 5, iclass 12, count 2 2006.201.03:57:08.40#ibcon#read 5, iclass 12, count 2 2006.201.03:57:08.40#ibcon#about to read 6, iclass 12, count 2 2006.201.03:57:08.40#ibcon#read 6, iclass 12, count 2 2006.201.03:57:08.40#ibcon#end of sib2, iclass 12, count 2 2006.201.03:57:08.40#ibcon#*mode == 0, iclass 12, count 2 2006.201.03:57:08.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.03:57:08.40#ibcon#[25=AT08-04\r\n] 2006.201.03:57:08.40#ibcon#*before write, iclass 12, count 2 2006.201.03:57:08.40#ibcon#enter sib2, iclass 12, count 2 2006.201.03:57:08.40#ibcon#flushed, iclass 12, count 2 2006.201.03:57:08.40#ibcon#about to write, iclass 12, count 2 2006.201.03:57:08.40#ibcon#wrote, iclass 12, count 2 2006.201.03:57:08.40#ibcon#about to read 3, iclass 12, count 2 2006.201.03:57:08.43#ibcon#read 3, iclass 12, count 2 2006.201.03:57:08.43#ibcon#about to read 4, iclass 12, count 2 2006.201.03:57:08.43#ibcon#read 4, iclass 12, count 2 2006.201.03:57:08.43#ibcon#about to read 5, iclass 12, count 2 2006.201.03:57:08.43#ibcon#read 5, iclass 12, count 2 2006.201.03:57:08.43#ibcon#about to read 6, iclass 12, count 2 2006.201.03:57:08.43#ibcon#read 6, iclass 12, count 2 2006.201.03:57:08.43#ibcon#end of sib2, iclass 12, count 2 2006.201.03:57:08.43#ibcon#*after write, iclass 12, count 2 2006.201.03:57:08.43#ibcon#*before return 0, iclass 12, count 2 2006.201.03:57:08.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:57:08.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.03:57:08.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.03:57:08.43#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:08.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:57:08.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:57:08.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:57:08.55#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:57:08.55#ibcon#first serial, iclass 12, count 0 2006.201.03:57:08.55#ibcon#enter sib2, iclass 12, count 0 2006.201.03:57:08.55#ibcon#flushed, iclass 12, count 0 2006.201.03:57:08.55#ibcon#about to write, iclass 12, count 0 2006.201.03:57:08.55#ibcon#wrote, iclass 12, count 0 2006.201.03:57:08.55#ibcon#about to read 3, iclass 12, count 0 2006.201.03:57:08.57#ibcon#read 3, iclass 12, count 0 2006.201.03:57:08.57#ibcon#about to read 4, iclass 12, count 0 2006.201.03:57:08.57#ibcon#read 4, iclass 12, count 0 2006.201.03:57:08.57#ibcon#about to read 5, iclass 12, count 0 2006.201.03:57:08.57#ibcon#read 5, iclass 12, count 0 2006.201.03:57:08.57#ibcon#about to read 6, iclass 12, count 0 2006.201.03:57:08.57#ibcon#read 6, iclass 12, count 0 2006.201.03:57:08.57#ibcon#end of sib2, iclass 12, count 0 2006.201.03:57:08.57#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:57:08.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:57:08.57#ibcon#[25=USB\r\n] 2006.201.03:57:08.57#ibcon#*before write, iclass 12, count 0 2006.201.03:57:08.57#ibcon#enter sib2, iclass 12, count 0 2006.201.03:57:08.57#ibcon#flushed, iclass 12, count 0 2006.201.03:57:08.57#ibcon#about to write, iclass 12, count 0 2006.201.03:57:08.57#ibcon#wrote, iclass 12, count 0 2006.201.03:57:08.57#ibcon#about to read 3, iclass 12, count 0 2006.201.03:57:08.60#ibcon#read 3, iclass 12, count 0 2006.201.03:57:08.60#ibcon#about to read 4, iclass 12, count 0 2006.201.03:57:08.60#ibcon#read 4, iclass 12, count 0 2006.201.03:57:08.60#ibcon#about to read 5, iclass 12, count 0 2006.201.03:57:08.60#ibcon#read 5, iclass 12, count 0 2006.201.03:57:08.60#ibcon#about to read 6, iclass 12, count 0 2006.201.03:57:08.60#ibcon#read 6, iclass 12, count 0 2006.201.03:57:08.60#ibcon#end of sib2, iclass 12, count 0 2006.201.03:57:08.60#ibcon#*after write, iclass 12, count 0 2006.201.03:57:08.60#ibcon#*before return 0, iclass 12, count 0 2006.201.03:57:08.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:57:08.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.03:57:08.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:57:08.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:57:08.60$vck44/vblo=1,629.99 2006.201.03:57:08.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.03:57:08.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.03:57:08.60#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:08.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:57:08.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:57:08.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:57:08.60#ibcon#enter wrdev, iclass 14, count 0 2006.201.03:57:08.60#ibcon#first serial, iclass 14, count 0 2006.201.03:57:08.60#ibcon#enter sib2, iclass 14, count 0 2006.201.03:57:08.60#ibcon#flushed, iclass 14, count 0 2006.201.03:57:08.60#ibcon#about to write, iclass 14, count 0 2006.201.03:57:08.60#ibcon#wrote, iclass 14, count 0 2006.201.03:57:08.60#ibcon#about to read 3, iclass 14, count 0 2006.201.03:57:08.62#ibcon#read 3, iclass 14, count 0 2006.201.03:57:08.62#ibcon#about to read 4, iclass 14, count 0 2006.201.03:57:08.62#ibcon#read 4, iclass 14, count 0 2006.201.03:57:08.62#ibcon#about to read 5, iclass 14, count 0 2006.201.03:57:08.62#ibcon#read 5, iclass 14, count 0 2006.201.03:57:08.62#ibcon#about to read 6, iclass 14, count 0 2006.201.03:57:08.62#ibcon#read 6, iclass 14, count 0 2006.201.03:57:08.62#ibcon#end of sib2, iclass 14, count 0 2006.201.03:57:08.62#ibcon#*mode == 0, iclass 14, count 0 2006.201.03:57:08.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.03:57:08.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.03:57:08.62#ibcon#*before write, iclass 14, count 0 2006.201.03:57:08.62#ibcon#enter sib2, iclass 14, count 0 2006.201.03:57:08.62#ibcon#flushed, iclass 14, count 0 2006.201.03:57:08.62#ibcon#about to write, iclass 14, count 0 2006.201.03:57:08.62#ibcon#wrote, iclass 14, count 0 2006.201.03:57:08.62#ibcon#about to read 3, iclass 14, count 0 2006.201.03:57:08.66#ibcon#read 3, iclass 14, count 0 2006.201.03:57:08.66#ibcon#about to read 4, iclass 14, count 0 2006.201.03:57:08.66#ibcon#read 4, iclass 14, count 0 2006.201.03:57:08.66#ibcon#about to read 5, iclass 14, count 0 2006.201.03:57:08.66#ibcon#read 5, iclass 14, count 0 2006.201.03:57:08.66#ibcon#about to read 6, iclass 14, count 0 2006.201.03:57:08.66#ibcon#read 6, iclass 14, count 0 2006.201.03:57:08.66#ibcon#end of sib2, iclass 14, count 0 2006.201.03:57:08.66#ibcon#*after write, iclass 14, count 0 2006.201.03:57:08.66#ibcon#*before return 0, iclass 14, count 0 2006.201.03:57:08.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:57:08.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.03:57:08.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.03:57:08.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.03:57:08.66$vck44/vb=1,4 2006.201.03:57:08.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.03:57:08.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.03:57:08.66#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:08.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:57:08.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:57:08.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:57:08.66#ibcon#enter wrdev, iclass 16, count 2 2006.201.03:57:08.66#ibcon#first serial, iclass 16, count 2 2006.201.03:57:08.66#ibcon#enter sib2, iclass 16, count 2 2006.201.03:57:08.66#ibcon#flushed, iclass 16, count 2 2006.201.03:57:08.66#ibcon#about to write, iclass 16, count 2 2006.201.03:57:08.66#ibcon#wrote, iclass 16, count 2 2006.201.03:57:08.66#ibcon#about to read 3, iclass 16, count 2 2006.201.03:57:08.68#ibcon#read 3, iclass 16, count 2 2006.201.03:57:08.68#ibcon#about to read 4, iclass 16, count 2 2006.201.03:57:08.68#ibcon#read 4, iclass 16, count 2 2006.201.03:57:08.68#ibcon#about to read 5, iclass 16, count 2 2006.201.03:57:08.68#ibcon#read 5, iclass 16, count 2 2006.201.03:57:08.68#ibcon#about to read 6, iclass 16, count 2 2006.201.03:57:08.68#ibcon#read 6, iclass 16, count 2 2006.201.03:57:08.68#ibcon#end of sib2, iclass 16, count 2 2006.201.03:57:08.68#ibcon#*mode == 0, iclass 16, count 2 2006.201.03:57:08.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.03:57:08.68#ibcon#[27=AT01-04\r\n] 2006.201.03:57:08.68#ibcon#*before write, iclass 16, count 2 2006.201.03:57:08.68#ibcon#enter sib2, iclass 16, count 2 2006.201.03:57:08.68#ibcon#flushed, iclass 16, count 2 2006.201.03:57:08.68#ibcon#about to write, iclass 16, count 2 2006.201.03:57:08.68#ibcon#wrote, iclass 16, count 2 2006.201.03:57:08.68#ibcon#about to read 3, iclass 16, count 2 2006.201.03:57:08.71#ibcon#read 3, iclass 16, count 2 2006.201.03:57:08.71#ibcon#about to read 4, iclass 16, count 2 2006.201.03:57:08.71#ibcon#read 4, iclass 16, count 2 2006.201.03:57:08.71#ibcon#about to read 5, iclass 16, count 2 2006.201.03:57:08.71#ibcon#read 5, iclass 16, count 2 2006.201.03:57:08.71#ibcon#about to read 6, iclass 16, count 2 2006.201.03:57:08.71#ibcon#read 6, iclass 16, count 2 2006.201.03:57:08.71#ibcon#end of sib2, iclass 16, count 2 2006.201.03:57:08.71#ibcon#*after write, iclass 16, count 2 2006.201.03:57:08.71#ibcon#*before return 0, iclass 16, count 2 2006.201.03:57:08.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:57:08.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.03:57:08.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.03:57:08.71#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:08.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:57:08.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:57:08.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:57:08.83#ibcon#enter wrdev, iclass 16, count 0 2006.201.03:57:08.83#ibcon#first serial, iclass 16, count 0 2006.201.03:57:08.83#ibcon#enter sib2, iclass 16, count 0 2006.201.03:57:08.83#ibcon#flushed, iclass 16, count 0 2006.201.03:57:08.83#ibcon#about to write, iclass 16, count 0 2006.201.03:57:08.83#ibcon#wrote, iclass 16, count 0 2006.201.03:57:08.83#ibcon#about to read 3, iclass 16, count 0 2006.201.03:57:08.85#ibcon#read 3, iclass 16, count 0 2006.201.03:57:08.85#ibcon#about to read 4, iclass 16, count 0 2006.201.03:57:08.85#ibcon#read 4, iclass 16, count 0 2006.201.03:57:08.85#ibcon#about to read 5, iclass 16, count 0 2006.201.03:57:08.85#ibcon#read 5, iclass 16, count 0 2006.201.03:57:08.85#ibcon#about to read 6, iclass 16, count 0 2006.201.03:57:08.85#ibcon#read 6, iclass 16, count 0 2006.201.03:57:08.85#ibcon#end of sib2, iclass 16, count 0 2006.201.03:57:08.85#ibcon#*mode == 0, iclass 16, count 0 2006.201.03:57:08.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.03:57:08.85#ibcon#[27=USB\r\n] 2006.201.03:57:08.85#ibcon#*before write, iclass 16, count 0 2006.201.03:57:08.85#ibcon#enter sib2, iclass 16, count 0 2006.201.03:57:08.85#ibcon#flushed, iclass 16, count 0 2006.201.03:57:08.85#ibcon#about to write, iclass 16, count 0 2006.201.03:57:08.85#ibcon#wrote, iclass 16, count 0 2006.201.03:57:08.85#ibcon#about to read 3, iclass 16, count 0 2006.201.03:57:08.88#ibcon#read 3, iclass 16, count 0 2006.201.03:57:08.88#ibcon#about to read 4, iclass 16, count 0 2006.201.03:57:08.88#ibcon#read 4, iclass 16, count 0 2006.201.03:57:08.88#ibcon#about to read 5, iclass 16, count 0 2006.201.03:57:08.88#ibcon#read 5, iclass 16, count 0 2006.201.03:57:08.88#ibcon#about to read 6, iclass 16, count 0 2006.201.03:57:08.88#ibcon#read 6, iclass 16, count 0 2006.201.03:57:08.88#ibcon#end of sib2, iclass 16, count 0 2006.201.03:57:08.88#ibcon#*after write, iclass 16, count 0 2006.201.03:57:08.88#ibcon#*before return 0, iclass 16, count 0 2006.201.03:57:08.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:57:08.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.03:57:08.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.03:57:08.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.03:57:08.88$vck44/vblo=2,634.99 2006.201.03:57:08.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.03:57:08.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.03:57:08.88#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:08.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:08.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:08.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:08.88#ibcon#enter wrdev, iclass 18, count 0 2006.201.03:57:08.88#ibcon#first serial, iclass 18, count 0 2006.201.03:57:08.88#ibcon#enter sib2, iclass 18, count 0 2006.201.03:57:08.88#ibcon#flushed, iclass 18, count 0 2006.201.03:57:08.88#ibcon#about to write, iclass 18, count 0 2006.201.03:57:08.88#ibcon#wrote, iclass 18, count 0 2006.201.03:57:08.88#ibcon#about to read 3, iclass 18, count 0 2006.201.03:57:08.90#ibcon#read 3, iclass 18, count 0 2006.201.03:57:08.90#ibcon#about to read 4, iclass 18, count 0 2006.201.03:57:08.90#ibcon#read 4, iclass 18, count 0 2006.201.03:57:08.90#ibcon#about to read 5, iclass 18, count 0 2006.201.03:57:08.90#ibcon#read 5, iclass 18, count 0 2006.201.03:57:08.90#ibcon#about to read 6, iclass 18, count 0 2006.201.03:57:08.90#ibcon#read 6, iclass 18, count 0 2006.201.03:57:08.90#ibcon#end of sib2, iclass 18, count 0 2006.201.03:57:08.90#ibcon#*mode == 0, iclass 18, count 0 2006.201.03:57:08.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.03:57:08.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.03:57:08.90#ibcon#*before write, iclass 18, count 0 2006.201.03:57:08.90#ibcon#enter sib2, iclass 18, count 0 2006.201.03:57:08.90#ibcon#flushed, iclass 18, count 0 2006.201.03:57:08.90#ibcon#about to write, iclass 18, count 0 2006.201.03:57:08.90#ibcon#wrote, iclass 18, count 0 2006.201.03:57:08.90#ibcon#about to read 3, iclass 18, count 0 2006.201.03:57:08.94#ibcon#read 3, iclass 18, count 0 2006.201.03:57:08.94#ibcon#about to read 4, iclass 18, count 0 2006.201.03:57:08.94#ibcon#read 4, iclass 18, count 0 2006.201.03:57:08.94#ibcon#about to read 5, iclass 18, count 0 2006.201.03:57:08.94#ibcon#read 5, iclass 18, count 0 2006.201.03:57:08.94#ibcon#about to read 6, iclass 18, count 0 2006.201.03:57:08.94#ibcon#read 6, iclass 18, count 0 2006.201.03:57:08.94#ibcon#end of sib2, iclass 18, count 0 2006.201.03:57:08.94#ibcon#*after write, iclass 18, count 0 2006.201.03:57:08.94#ibcon#*before return 0, iclass 18, count 0 2006.201.03:57:08.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:08.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.03:57:08.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.03:57:08.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.03:57:08.94$vck44/vb=2,5 2006.201.03:57:08.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.03:57:08.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.03:57:08.94#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:08.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:09.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:09.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:09.00#ibcon#enter wrdev, iclass 20, count 2 2006.201.03:57:09.00#ibcon#first serial, iclass 20, count 2 2006.201.03:57:09.00#ibcon#enter sib2, iclass 20, count 2 2006.201.03:57:09.00#ibcon#flushed, iclass 20, count 2 2006.201.03:57:09.00#ibcon#about to write, iclass 20, count 2 2006.201.03:57:09.00#ibcon#wrote, iclass 20, count 2 2006.201.03:57:09.00#ibcon#about to read 3, iclass 20, count 2 2006.201.03:57:09.02#ibcon#read 3, iclass 20, count 2 2006.201.03:57:09.02#ibcon#about to read 4, iclass 20, count 2 2006.201.03:57:09.02#ibcon#read 4, iclass 20, count 2 2006.201.03:57:09.02#ibcon#about to read 5, iclass 20, count 2 2006.201.03:57:09.02#ibcon#read 5, iclass 20, count 2 2006.201.03:57:09.02#ibcon#about to read 6, iclass 20, count 2 2006.201.03:57:09.02#ibcon#read 6, iclass 20, count 2 2006.201.03:57:09.02#ibcon#end of sib2, iclass 20, count 2 2006.201.03:57:09.02#ibcon#*mode == 0, iclass 20, count 2 2006.201.03:57:09.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.03:57:09.02#ibcon#[27=AT02-05\r\n] 2006.201.03:57:09.02#ibcon#*before write, iclass 20, count 2 2006.201.03:57:09.02#ibcon#enter sib2, iclass 20, count 2 2006.201.03:57:09.02#ibcon#flushed, iclass 20, count 2 2006.201.03:57:09.02#ibcon#about to write, iclass 20, count 2 2006.201.03:57:09.02#ibcon#wrote, iclass 20, count 2 2006.201.03:57:09.02#ibcon#about to read 3, iclass 20, count 2 2006.201.03:57:09.05#ibcon#read 3, iclass 20, count 2 2006.201.03:57:09.05#ibcon#about to read 4, iclass 20, count 2 2006.201.03:57:09.05#ibcon#read 4, iclass 20, count 2 2006.201.03:57:09.05#ibcon#about to read 5, iclass 20, count 2 2006.201.03:57:09.05#ibcon#read 5, iclass 20, count 2 2006.201.03:57:09.05#ibcon#about to read 6, iclass 20, count 2 2006.201.03:57:09.05#ibcon#read 6, iclass 20, count 2 2006.201.03:57:09.05#ibcon#end of sib2, iclass 20, count 2 2006.201.03:57:09.05#ibcon#*after write, iclass 20, count 2 2006.201.03:57:09.05#ibcon#*before return 0, iclass 20, count 2 2006.201.03:57:09.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:09.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.03:57:09.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.03:57:09.05#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:09.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:09.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:09.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:09.17#ibcon#enter wrdev, iclass 20, count 0 2006.201.03:57:09.17#ibcon#first serial, iclass 20, count 0 2006.201.03:57:09.17#ibcon#enter sib2, iclass 20, count 0 2006.201.03:57:09.17#ibcon#flushed, iclass 20, count 0 2006.201.03:57:09.17#ibcon#about to write, iclass 20, count 0 2006.201.03:57:09.17#ibcon#wrote, iclass 20, count 0 2006.201.03:57:09.17#ibcon#about to read 3, iclass 20, count 0 2006.201.03:57:09.19#ibcon#read 3, iclass 20, count 0 2006.201.03:57:09.19#ibcon#about to read 4, iclass 20, count 0 2006.201.03:57:09.19#ibcon#read 4, iclass 20, count 0 2006.201.03:57:09.19#ibcon#about to read 5, iclass 20, count 0 2006.201.03:57:09.19#ibcon#read 5, iclass 20, count 0 2006.201.03:57:09.19#ibcon#about to read 6, iclass 20, count 0 2006.201.03:57:09.19#ibcon#read 6, iclass 20, count 0 2006.201.03:57:09.19#ibcon#end of sib2, iclass 20, count 0 2006.201.03:57:09.19#ibcon#*mode == 0, iclass 20, count 0 2006.201.03:57:09.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.03:57:09.19#ibcon#[27=USB\r\n] 2006.201.03:57:09.19#ibcon#*before write, iclass 20, count 0 2006.201.03:57:09.19#ibcon#enter sib2, iclass 20, count 0 2006.201.03:57:09.19#ibcon#flushed, iclass 20, count 0 2006.201.03:57:09.19#ibcon#about to write, iclass 20, count 0 2006.201.03:57:09.19#ibcon#wrote, iclass 20, count 0 2006.201.03:57:09.19#ibcon#about to read 3, iclass 20, count 0 2006.201.03:57:09.22#ibcon#read 3, iclass 20, count 0 2006.201.03:57:09.22#ibcon#about to read 4, iclass 20, count 0 2006.201.03:57:09.22#ibcon#read 4, iclass 20, count 0 2006.201.03:57:09.22#ibcon#about to read 5, iclass 20, count 0 2006.201.03:57:09.22#ibcon#read 5, iclass 20, count 0 2006.201.03:57:09.22#ibcon#about to read 6, iclass 20, count 0 2006.201.03:57:09.22#ibcon#read 6, iclass 20, count 0 2006.201.03:57:09.22#ibcon#end of sib2, iclass 20, count 0 2006.201.03:57:09.22#ibcon#*after write, iclass 20, count 0 2006.201.03:57:09.22#ibcon#*before return 0, iclass 20, count 0 2006.201.03:57:09.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:09.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.03:57:09.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.03:57:09.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.03:57:09.22$vck44/vblo=3,649.99 2006.201.03:57:09.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.03:57:09.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.03:57:09.22#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:09.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:09.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:09.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:09.22#ibcon#enter wrdev, iclass 22, count 0 2006.201.03:57:09.22#ibcon#first serial, iclass 22, count 0 2006.201.03:57:09.22#ibcon#enter sib2, iclass 22, count 0 2006.201.03:57:09.22#ibcon#flushed, iclass 22, count 0 2006.201.03:57:09.22#ibcon#about to write, iclass 22, count 0 2006.201.03:57:09.22#ibcon#wrote, iclass 22, count 0 2006.201.03:57:09.22#ibcon#about to read 3, iclass 22, count 0 2006.201.03:57:09.24#ibcon#read 3, iclass 22, count 0 2006.201.03:57:09.24#ibcon#about to read 4, iclass 22, count 0 2006.201.03:57:09.24#ibcon#read 4, iclass 22, count 0 2006.201.03:57:09.24#ibcon#about to read 5, iclass 22, count 0 2006.201.03:57:09.24#ibcon#read 5, iclass 22, count 0 2006.201.03:57:09.24#ibcon#about to read 6, iclass 22, count 0 2006.201.03:57:09.24#ibcon#read 6, iclass 22, count 0 2006.201.03:57:09.24#ibcon#end of sib2, iclass 22, count 0 2006.201.03:57:09.24#ibcon#*mode == 0, iclass 22, count 0 2006.201.03:57:09.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.03:57:09.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.03:57:09.24#ibcon#*before write, iclass 22, count 0 2006.201.03:57:09.24#ibcon#enter sib2, iclass 22, count 0 2006.201.03:57:09.24#ibcon#flushed, iclass 22, count 0 2006.201.03:57:09.24#ibcon#about to write, iclass 22, count 0 2006.201.03:57:09.24#ibcon#wrote, iclass 22, count 0 2006.201.03:57:09.24#ibcon#about to read 3, iclass 22, count 0 2006.201.03:57:09.28#ibcon#read 3, iclass 22, count 0 2006.201.03:57:09.28#ibcon#about to read 4, iclass 22, count 0 2006.201.03:57:09.28#ibcon#read 4, iclass 22, count 0 2006.201.03:57:09.28#ibcon#about to read 5, iclass 22, count 0 2006.201.03:57:09.28#ibcon#read 5, iclass 22, count 0 2006.201.03:57:09.28#ibcon#about to read 6, iclass 22, count 0 2006.201.03:57:09.28#ibcon#read 6, iclass 22, count 0 2006.201.03:57:09.28#ibcon#end of sib2, iclass 22, count 0 2006.201.03:57:09.28#ibcon#*after write, iclass 22, count 0 2006.201.03:57:09.28#ibcon#*before return 0, iclass 22, count 0 2006.201.03:57:09.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:09.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.03:57:09.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.03:57:09.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.03:57:09.28$vck44/vb=3,4 2006.201.03:57:09.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.03:57:09.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.03:57:09.28#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:09.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:09.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:09.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:09.34#ibcon#enter wrdev, iclass 24, count 2 2006.201.03:57:09.34#ibcon#first serial, iclass 24, count 2 2006.201.03:57:09.34#ibcon#enter sib2, iclass 24, count 2 2006.201.03:57:09.34#ibcon#flushed, iclass 24, count 2 2006.201.03:57:09.34#ibcon#about to write, iclass 24, count 2 2006.201.03:57:09.34#ibcon#wrote, iclass 24, count 2 2006.201.03:57:09.34#ibcon#about to read 3, iclass 24, count 2 2006.201.03:57:09.36#ibcon#read 3, iclass 24, count 2 2006.201.03:57:09.36#ibcon#about to read 4, iclass 24, count 2 2006.201.03:57:09.36#ibcon#read 4, iclass 24, count 2 2006.201.03:57:09.36#ibcon#about to read 5, iclass 24, count 2 2006.201.03:57:09.36#ibcon#read 5, iclass 24, count 2 2006.201.03:57:09.36#ibcon#about to read 6, iclass 24, count 2 2006.201.03:57:09.36#ibcon#read 6, iclass 24, count 2 2006.201.03:57:09.36#ibcon#end of sib2, iclass 24, count 2 2006.201.03:57:09.36#ibcon#*mode == 0, iclass 24, count 2 2006.201.03:57:09.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.03:57:09.36#ibcon#[27=AT03-04\r\n] 2006.201.03:57:09.36#ibcon#*before write, iclass 24, count 2 2006.201.03:57:09.36#ibcon#enter sib2, iclass 24, count 2 2006.201.03:57:09.36#ibcon#flushed, iclass 24, count 2 2006.201.03:57:09.36#ibcon#about to write, iclass 24, count 2 2006.201.03:57:09.36#ibcon#wrote, iclass 24, count 2 2006.201.03:57:09.36#ibcon#about to read 3, iclass 24, count 2 2006.201.03:57:09.39#ibcon#read 3, iclass 24, count 2 2006.201.03:57:09.39#ibcon#about to read 4, iclass 24, count 2 2006.201.03:57:09.39#ibcon#read 4, iclass 24, count 2 2006.201.03:57:09.39#ibcon#about to read 5, iclass 24, count 2 2006.201.03:57:09.39#ibcon#read 5, iclass 24, count 2 2006.201.03:57:09.39#ibcon#about to read 6, iclass 24, count 2 2006.201.03:57:09.39#ibcon#read 6, iclass 24, count 2 2006.201.03:57:09.39#ibcon#end of sib2, iclass 24, count 2 2006.201.03:57:09.39#ibcon#*after write, iclass 24, count 2 2006.201.03:57:09.39#ibcon#*before return 0, iclass 24, count 2 2006.201.03:57:09.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:09.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.03:57:09.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.03:57:09.39#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:09.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:09.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:09.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:09.51#ibcon#enter wrdev, iclass 24, count 0 2006.201.03:57:09.51#ibcon#first serial, iclass 24, count 0 2006.201.03:57:09.51#ibcon#enter sib2, iclass 24, count 0 2006.201.03:57:09.51#ibcon#flushed, iclass 24, count 0 2006.201.03:57:09.51#ibcon#about to write, iclass 24, count 0 2006.201.03:57:09.51#ibcon#wrote, iclass 24, count 0 2006.201.03:57:09.51#ibcon#about to read 3, iclass 24, count 0 2006.201.03:57:09.53#ibcon#read 3, iclass 24, count 0 2006.201.03:57:09.53#ibcon#about to read 4, iclass 24, count 0 2006.201.03:57:09.53#ibcon#read 4, iclass 24, count 0 2006.201.03:57:09.53#ibcon#about to read 5, iclass 24, count 0 2006.201.03:57:09.53#ibcon#read 5, iclass 24, count 0 2006.201.03:57:09.53#ibcon#about to read 6, iclass 24, count 0 2006.201.03:57:09.53#ibcon#read 6, iclass 24, count 0 2006.201.03:57:09.53#ibcon#end of sib2, iclass 24, count 0 2006.201.03:57:09.53#ibcon#*mode == 0, iclass 24, count 0 2006.201.03:57:09.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.03:57:09.53#ibcon#[27=USB\r\n] 2006.201.03:57:09.53#ibcon#*before write, iclass 24, count 0 2006.201.03:57:09.53#ibcon#enter sib2, iclass 24, count 0 2006.201.03:57:09.53#ibcon#flushed, iclass 24, count 0 2006.201.03:57:09.53#ibcon#about to write, iclass 24, count 0 2006.201.03:57:09.53#ibcon#wrote, iclass 24, count 0 2006.201.03:57:09.53#ibcon#about to read 3, iclass 24, count 0 2006.201.03:57:09.56#ibcon#read 3, iclass 24, count 0 2006.201.03:57:09.56#ibcon#about to read 4, iclass 24, count 0 2006.201.03:57:09.56#ibcon#read 4, iclass 24, count 0 2006.201.03:57:09.56#ibcon#about to read 5, iclass 24, count 0 2006.201.03:57:09.56#ibcon#read 5, iclass 24, count 0 2006.201.03:57:09.56#ibcon#about to read 6, iclass 24, count 0 2006.201.03:57:09.56#ibcon#read 6, iclass 24, count 0 2006.201.03:57:09.56#ibcon#end of sib2, iclass 24, count 0 2006.201.03:57:09.56#ibcon#*after write, iclass 24, count 0 2006.201.03:57:09.56#ibcon#*before return 0, iclass 24, count 0 2006.201.03:57:09.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:09.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.03:57:09.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.03:57:09.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.03:57:09.56$vck44/vblo=4,679.99 2006.201.03:57:09.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.03:57:09.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.03:57:09.56#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:09.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:09.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:09.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:09.56#ibcon#enter wrdev, iclass 26, count 0 2006.201.03:57:09.56#ibcon#first serial, iclass 26, count 0 2006.201.03:57:09.56#ibcon#enter sib2, iclass 26, count 0 2006.201.03:57:09.56#ibcon#flushed, iclass 26, count 0 2006.201.03:57:09.56#ibcon#about to write, iclass 26, count 0 2006.201.03:57:09.56#ibcon#wrote, iclass 26, count 0 2006.201.03:57:09.56#ibcon#about to read 3, iclass 26, count 0 2006.201.03:57:09.58#ibcon#read 3, iclass 26, count 0 2006.201.03:57:09.58#ibcon#about to read 4, iclass 26, count 0 2006.201.03:57:09.58#ibcon#read 4, iclass 26, count 0 2006.201.03:57:09.58#ibcon#about to read 5, iclass 26, count 0 2006.201.03:57:09.58#ibcon#read 5, iclass 26, count 0 2006.201.03:57:09.58#ibcon#about to read 6, iclass 26, count 0 2006.201.03:57:09.58#ibcon#read 6, iclass 26, count 0 2006.201.03:57:09.58#ibcon#end of sib2, iclass 26, count 0 2006.201.03:57:09.58#ibcon#*mode == 0, iclass 26, count 0 2006.201.03:57:09.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.03:57:09.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.03:57:09.58#ibcon#*before write, iclass 26, count 0 2006.201.03:57:09.58#ibcon#enter sib2, iclass 26, count 0 2006.201.03:57:09.58#ibcon#flushed, iclass 26, count 0 2006.201.03:57:09.58#ibcon#about to write, iclass 26, count 0 2006.201.03:57:09.58#ibcon#wrote, iclass 26, count 0 2006.201.03:57:09.58#ibcon#about to read 3, iclass 26, count 0 2006.201.03:57:09.62#ibcon#read 3, iclass 26, count 0 2006.201.03:57:09.62#ibcon#about to read 4, iclass 26, count 0 2006.201.03:57:09.62#ibcon#read 4, iclass 26, count 0 2006.201.03:57:09.62#ibcon#about to read 5, iclass 26, count 0 2006.201.03:57:09.62#ibcon#read 5, iclass 26, count 0 2006.201.03:57:09.62#ibcon#about to read 6, iclass 26, count 0 2006.201.03:57:09.62#ibcon#read 6, iclass 26, count 0 2006.201.03:57:09.62#ibcon#end of sib2, iclass 26, count 0 2006.201.03:57:09.62#ibcon#*after write, iclass 26, count 0 2006.201.03:57:09.62#ibcon#*before return 0, iclass 26, count 0 2006.201.03:57:09.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:09.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.03:57:09.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.03:57:09.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.03:57:09.62$vck44/vb=4,5 2006.201.03:57:09.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.03:57:09.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.03:57:09.62#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:09.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:09.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:09.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:09.68#ibcon#enter wrdev, iclass 28, count 2 2006.201.03:57:09.68#ibcon#first serial, iclass 28, count 2 2006.201.03:57:09.68#ibcon#enter sib2, iclass 28, count 2 2006.201.03:57:09.68#ibcon#flushed, iclass 28, count 2 2006.201.03:57:09.68#ibcon#about to write, iclass 28, count 2 2006.201.03:57:09.68#ibcon#wrote, iclass 28, count 2 2006.201.03:57:09.68#ibcon#about to read 3, iclass 28, count 2 2006.201.03:57:09.70#ibcon#read 3, iclass 28, count 2 2006.201.03:57:09.70#ibcon#about to read 4, iclass 28, count 2 2006.201.03:57:09.70#ibcon#read 4, iclass 28, count 2 2006.201.03:57:09.70#ibcon#about to read 5, iclass 28, count 2 2006.201.03:57:09.70#ibcon#read 5, iclass 28, count 2 2006.201.03:57:09.70#ibcon#about to read 6, iclass 28, count 2 2006.201.03:57:09.70#ibcon#read 6, iclass 28, count 2 2006.201.03:57:09.70#ibcon#end of sib2, iclass 28, count 2 2006.201.03:57:09.70#ibcon#*mode == 0, iclass 28, count 2 2006.201.03:57:09.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.03:57:09.70#ibcon#[27=AT04-05\r\n] 2006.201.03:57:09.70#ibcon#*before write, iclass 28, count 2 2006.201.03:57:09.70#ibcon#enter sib2, iclass 28, count 2 2006.201.03:57:09.70#ibcon#flushed, iclass 28, count 2 2006.201.03:57:09.70#ibcon#about to write, iclass 28, count 2 2006.201.03:57:09.70#ibcon#wrote, iclass 28, count 2 2006.201.03:57:09.70#ibcon#about to read 3, iclass 28, count 2 2006.201.03:57:09.73#ibcon#read 3, iclass 28, count 2 2006.201.03:57:09.73#ibcon#about to read 4, iclass 28, count 2 2006.201.03:57:09.73#ibcon#read 4, iclass 28, count 2 2006.201.03:57:09.73#ibcon#about to read 5, iclass 28, count 2 2006.201.03:57:09.73#ibcon#read 5, iclass 28, count 2 2006.201.03:57:09.73#ibcon#about to read 6, iclass 28, count 2 2006.201.03:57:09.73#ibcon#read 6, iclass 28, count 2 2006.201.03:57:09.73#ibcon#end of sib2, iclass 28, count 2 2006.201.03:57:09.73#ibcon#*after write, iclass 28, count 2 2006.201.03:57:09.73#ibcon#*before return 0, iclass 28, count 2 2006.201.03:57:09.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:09.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.03:57:09.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.03:57:09.73#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:09.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:09.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:09.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:09.85#ibcon#enter wrdev, iclass 28, count 0 2006.201.03:57:09.85#ibcon#first serial, iclass 28, count 0 2006.201.03:57:09.85#ibcon#enter sib2, iclass 28, count 0 2006.201.03:57:09.85#ibcon#flushed, iclass 28, count 0 2006.201.03:57:09.85#ibcon#about to write, iclass 28, count 0 2006.201.03:57:09.85#ibcon#wrote, iclass 28, count 0 2006.201.03:57:09.85#ibcon#about to read 3, iclass 28, count 0 2006.201.03:57:09.87#ibcon#read 3, iclass 28, count 0 2006.201.03:57:09.87#ibcon#about to read 4, iclass 28, count 0 2006.201.03:57:09.87#ibcon#read 4, iclass 28, count 0 2006.201.03:57:09.87#ibcon#about to read 5, iclass 28, count 0 2006.201.03:57:09.87#ibcon#read 5, iclass 28, count 0 2006.201.03:57:09.87#ibcon#about to read 6, iclass 28, count 0 2006.201.03:57:09.87#ibcon#read 6, iclass 28, count 0 2006.201.03:57:09.87#ibcon#end of sib2, iclass 28, count 0 2006.201.03:57:09.87#ibcon#*mode == 0, iclass 28, count 0 2006.201.03:57:09.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.03:57:09.87#ibcon#[27=USB\r\n] 2006.201.03:57:09.87#ibcon#*before write, iclass 28, count 0 2006.201.03:57:09.87#ibcon#enter sib2, iclass 28, count 0 2006.201.03:57:09.87#ibcon#flushed, iclass 28, count 0 2006.201.03:57:09.87#ibcon#about to write, iclass 28, count 0 2006.201.03:57:09.87#ibcon#wrote, iclass 28, count 0 2006.201.03:57:09.87#ibcon#about to read 3, iclass 28, count 0 2006.201.03:57:09.90#ibcon#read 3, iclass 28, count 0 2006.201.03:57:09.90#ibcon#about to read 4, iclass 28, count 0 2006.201.03:57:09.90#ibcon#read 4, iclass 28, count 0 2006.201.03:57:09.90#ibcon#about to read 5, iclass 28, count 0 2006.201.03:57:09.90#ibcon#read 5, iclass 28, count 0 2006.201.03:57:09.90#ibcon#about to read 6, iclass 28, count 0 2006.201.03:57:09.90#ibcon#read 6, iclass 28, count 0 2006.201.03:57:09.90#ibcon#end of sib2, iclass 28, count 0 2006.201.03:57:09.90#ibcon#*after write, iclass 28, count 0 2006.201.03:57:09.90#ibcon#*before return 0, iclass 28, count 0 2006.201.03:57:09.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:09.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.03:57:09.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.03:57:09.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.03:57:09.90$vck44/vblo=5,709.99 2006.201.03:57:09.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.03:57:09.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.03:57:09.90#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:09.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:09.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:09.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:09.90#ibcon#enter wrdev, iclass 30, count 0 2006.201.03:57:09.90#ibcon#first serial, iclass 30, count 0 2006.201.03:57:09.90#ibcon#enter sib2, iclass 30, count 0 2006.201.03:57:09.90#ibcon#flushed, iclass 30, count 0 2006.201.03:57:09.90#ibcon#about to write, iclass 30, count 0 2006.201.03:57:09.90#ibcon#wrote, iclass 30, count 0 2006.201.03:57:09.90#ibcon#about to read 3, iclass 30, count 0 2006.201.03:57:09.92#ibcon#read 3, iclass 30, count 0 2006.201.03:57:09.92#ibcon#about to read 4, iclass 30, count 0 2006.201.03:57:09.92#ibcon#read 4, iclass 30, count 0 2006.201.03:57:09.92#ibcon#about to read 5, iclass 30, count 0 2006.201.03:57:09.92#ibcon#read 5, iclass 30, count 0 2006.201.03:57:09.92#ibcon#about to read 6, iclass 30, count 0 2006.201.03:57:09.92#ibcon#read 6, iclass 30, count 0 2006.201.03:57:09.92#ibcon#end of sib2, iclass 30, count 0 2006.201.03:57:09.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.03:57:09.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.03:57:09.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.03:57:09.92#ibcon#*before write, iclass 30, count 0 2006.201.03:57:09.92#ibcon#enter sib2, iclass 30, count 0 2006.201.03:57:09.92#ibcon#flushed, iclass 30, count 0 2006.201.03:57:09.92#ibcon#about to write, iclass 30, count 0 2006.201.03:57:09.92#ibcon#wrote, iclass 30, count 0 2006.201.03:57:09.92#ibcon#about to read 3, iclass 30, count 0 2006.201.03:57:09.96#ibcon#read 3, iclass 30, count 0 2006.201.03:57:09.96#ibcon#about to read 4, iclass 30, count 0 2006.201.03:57:09.96#ibcon#read 4, iclass 30, count 0 2006.201.03:57:09.96#ibcon#about to read 5, iclass 30, count 0 2006.201.03:57:09.96#ibcon#read 5, iclass 30, count 0 2006.201.03:57:09.96#ibcon#about to read 6, iclass 30, count 0 2006.201.03:57:09.96#ibcon#read 6, iclass 30, count 0 2006.201.03:57:09.96#ibcon#end of sib2, iclass 30, count 0 2006.201.03:57:09.96#ibcon#*after write, iclass 30, count 0 2006.201.03:57:09.96#ibcon#*before return 0, iclass 30, count 0 2006.201.03:57:09.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:09.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.03:57:09.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.03:57:09.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.03:57:09.96$vck44/vb=5,4 2006.201.03:57:09.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.03:57:09.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.03:57:09.96#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:09.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:10.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:10.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:10.02#ibcon#enter wrdev, iclass 32, count 2 2006.201.03:57:10.02#ibcon#first serial, iclass 32, count 2 2006.201.03:57:10.02#ibcon#enter sib2, iclass 32, count 2 2006.201.03:57:10.02#ibcon#flushed, iclass 32, count 2 2006.201.03:57:10.02#ibcon#about to write, iclass 32, count 2 2006.201.03:57:10.02#ibcon#wrote, iclass 32, count 2 2006.201.03:57:10.02#ibcon#about to read 3, iclass 32, count 2 2006.201.03:57:10.04#ibcon#read 3, iclass 32, count 2 2006.201.03:57:10.04#ibcon#about to read 4, iclass 32, count 2 2006.201.03:57:10.04#ibcon#read 4, iclass 32, count 2 2006.201.03:57:10.04#ibcon#about to read 5, iclass 32, count 2 2006.201.03:57:10.04#ibcon#read 5, iclass 32, count 2 2006.201.03:57:10.04#ibcon#about to read 6, iclass 32, count 2 2006.201.03:57:10.04#ibcon#read 6, iclass 32, count 2 2006.201.03:57:10.04#ibcon#end of sib2, iclass 32, count 2 2006.201.03:57:10.04#ibcon#*mode == 0, iclass 32, count 2 2006.201.03:57:10.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.03:57:10.04#ibcon#[27=AT05-04\r\n] 2006.201.03:57:10.04#ibcon#*before write, iclass 32, count 2 2006.201.03:57:10.04#ibcon#enter sib2, iclass 32, count 2 2006.201.03:57:10.04#ibcon#flushed, iclass 32, count 2 2006.201.03:57:10.04#ibcon#about to write, iclass 32, count 2 2006.201.03:57:10.04#ibcon#wrote, iclass 32, count 2 2006.201.03:57:10.04#ibcon#about to read 3, iclass 32, count 2 2006.201.03:57:10.07#ibcon#read 3, iclass 32, count 2 2006.201.03:57:10.07#ibcon#about to read 4, iclass 32, count 2 2006.201.03:57:10.07#ibcon#read 4, iclass 32, count 2 2006.201.03:57:10.07#ibcon#about to read 5, iclass 32, count 2 2006.201.03:57:10.07#ibcon#read 5, iclass 32, count 2 2006.201.03:57:10.07#ibcon#about to read 6, iclass 32, count 2 2006.201.03:57:10.07#ibcon#read 6, iclass 32, count 2 2006.201.03:57:10.07#ibcon#end of sib2, iclass 32, count 2 2006.201.03:57:10.07#ibcon#*after write, iclass 32, count 2 2006.201.03:57:10.07#ibcon#*before return 0, iclass 32, count 2 2006.201.03:57:10.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:10.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.03:57:10.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.03:57:10.07#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:10.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:10.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:10.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:10.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.03:57:10.19#ibcon#first serial, iclass 32, count 0 2006.201.03:57:10.19#ibcon#enter sib2, iclass 32, count 0 2006.201.03:57:10.19#ibcon#flushed, iclass 32, count 0 2006.201.03:57:10.19#ibcon#about to write, iclass 32, count 0 2006.201.03:57:10.19#ibcon#wrote, iclass 32, count 0 2006.201.03:57:10.19#ibcon#about to read 3, iclass 32, count 0 2006.201.03:57:10.22#ibcon#read 3, iclass 32, count 0 2006.201.03:57:10.22#ibcon#about to read 4, iclass 32, count 0 2006.201.03:57:10.22#ibcon#read 4, iclass 32, count 0 2006.201.03:57:10.22#ibcon#about to read 5, iclass 32, count 0 2006.201.03:57:10.22#ibcon#read 5, iclass 32, count 0 2006.201.03:57:10.22#ibcon#about to read 6, iclass 32, count 0 2006.201.03:57:10.22#ibcon#read 6, iclass 32, count 0 2006.201.03:57:10.22#ibcon#end of sib2, iclass 32, count 0 2006.201.03:57:10.22#ibcon#*mode == 0, iclass 32, count 0 2006.201.03:57:10.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.03:57:10.22#ibcon#[27=USB\r\n] 2006.201.03:57:10.22#ibcon#*before write, iclass 32, count 0 2006.201.03:57:10.22#ibcon#enter sib2, iclass 32, count 0 2006.201.03:57:10.22#ibcon#flushed, iclass 32, count 0 2006.201.03:57:10.22#ibcon#about to write, iclass 32, count 0 2006.201.03:57:10.22#ibcon#wrote, iclass 32, count 0 2006.201.03:57:10.22#ibcon#about to read 3, iclass 32, count 0 2006.201.03:57:10.25#ibcon#read 3, iclass 32, count 0 2006.201.03:57:10.25#ibcon#about to read 4, iclass 32, count 0 2006.201.03:57:10.25#ibcon#read 4, iclass 32, count 0 2006.201.03:57:10.25#ibcon#about to read 5, iclass 32, count 0 2006.201.03:57:10.25#ibcon#read 5, iclass 32, count 0 2006.201.03:57:10.25#ibcon#about to read 6, iclass 32, count 0 2006.201.03:57:10.25#ibcon#read 6, iclass 32, count 0 2006.201.03:57:10.25#ibcon#end of sib2, iclass 32, count 0 2006.201.03:57:10.25#ibcon#*after write, iclass 32, count 0 2006.201.03:57:10.25#ibcon#*before return 0, iclass 32, count 0 2006.201.03:57:10.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:10.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.03:57:10.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.03:57:10.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.03:57:10.25$vck44/vblo=6,719.99 2006.201.03:57:10.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.03:57:10.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.03:57:10.25#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:10.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:10.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:10.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:10.25#ibcon#enter wrdev, iclass 34, count 0 2006.201.03:57:10.25#ibcon#first serial, iclass 34, count 0 2006.201.03:57:10.25#ibcon#enter sib2, iclass 34, count 0 2006.201.03:57:10.25#ibcon#flushed, iclass 34, count 0 2006.201.03:57:10.25#ibcon#about to write, iclass 34, count 0 2006.201.03:57:10.25#ibcon#wrote, iclass 34, count 0 2006.201.03:57:10.25#ibcon#about to read 3, iclass 34, count 0 2006.201.03:57:10.27#ibcon#read 3, iclass 34, count 0 2006.201.03:57:10.27#ibcon#about to read 4, iclass 34, count 0 2006.201.03:57:10.27#ibcon#read 4, iclass 34, count 0 2006.201.03:57:10.27#ibcon#about to read 5, iclass 34, count 0 2006.201.03:57:10.27#ibcon#read 5, iclass 34, count 0 2006.201.03:57:10.27#ibcon#about to read 6, iclass 34, count 0 2006.201.03:57:10.27#ibcon#read 6, iclass 34, count 0 2006.201.03:57:10.27#ibcon#end of sib2, iclass 34, count 0 2006.201.03:57:10.27#ibcon#*mode == 0, iclass 34, count 0 2006.201.03:57:10.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.03:57:10.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.03:57:10.27#ibcon#*before write, iclass 34, count 0 2006.201.03:57:10.27#ibcon#enter sib2, iclass 34, count 0 2006.201.03:57:10.27#ibcon#flushed, iclass 34, count 0 2006.201.03:57:10.27#ibcon#about to write, iclass 34, count 0 2006.201.03:57:10.27#ibcon#wrote, iclass 34, count 0 2006.201.03:57:10.27#ibcon#about to read 3, iclass 34, count 0 2006.201.03:57:10.31#ibcon#read 3, iclass 34, count 0 2006.201.03:57:10.31#ibcon#about to read 4, iclass 34, count 0 2006.201.03:57:10.31#ibcon#read 4, iclass 34, count 0 2006.201.03:57:10.31#ibcon#about to read 5, iclass 34, count 0 2006.201.03:57:10.31#ibcon#read 5, iclass 34, count 0 2006.201.03:57:10.31#ibcon#about to read 6, iclass 34, count 0 2006.201.03:57:10.31#ibcon#read 6, iclass 34, count 0 2006.201.03:57:10.31#ibcon#end of sib2, iclass 34, count 0 2006.201.03:57:10.31#ibcon#*after write, iclass 34, count 0 2006.201.03:57:10.31#ibcon#*before return 0, iclass 34, count 0 2006.201.03:57:10.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:10.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.03:57:10.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.03:57:10.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.03:57:10.31$vck44/vb=6,4 2006.201.03:57:10.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.03:57:10.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.03:57:10.31#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:10.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:10.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:10.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:10.37#ibcon#enter wrdev, iclass 36, count 2 2006.201.03:57:10.37#ibcon#first serial, iclass 36, count 2 2006.201.03:57:10.37#ibcon#enter sib2, iclass 36, count 2 2006.201.03:57:10.37#ibcon#flushed, iclass 36, count 2 2006.201.03:57:10.37#ibcon#about to write, iclass 36, count 2 2006.201.03:57:10.37#ibcon#wrote, iclass 36, count 2 2006.201.03:57:10.37#ibcon#about to read 3, iclass 36, count 2 2006.201.03:57:10.39#ibcon#read 3, iclass 36, count 2 2006.201.03:57:10.39#ibcon#about to read 4, iclass 36, count 2 2006.201.03:57:10.39#ibcon#read 4, iclass 36, count 2 2006.201.03:57:10.39#ibcon#about to read 5, iclass 36, count 2 2006.201.03:57:10.39#ibcon#read 5, iclass 36, count 2 2006.201.03:57:10.39#ibcon#about to read 6, iclass 36, count 2 2006.201.03:57:10.39#ibcon#read 6, iclass 36, count 2 2006.201.03:57:10.39#ibcon#end of sib2, iclass 36, count 2 2006.201.03:57:10.39#ibcon#*mode == 0, iclass 36, count 2 2006.201.03:57:10.39#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.03:57:10.39#ibcon#[27=AT06-04\r\n] 2006.201.03:57:10.39#ibcon#*before write, iclass 36, count 2 2006.201.03:57:10.39#ibcon#enter sib2, iclass 36, count 2 2006.201.03:57:10.39#ibcon#flushed, iclass 36, count 2 2006.201.03:57:10.39#ibcon#about to write, iclass 36, count 2 2006.201.03:57:10.39#ibcon#wrote, iclass 36, count 2 2006.201.03:57:10.39#ibcon#about to read 3, iclass 36, count 2 2006.201.03:57:10.42#ibcon#read 3, iclass 36, count 2 2006.201.03:57:10.42#ibcon#about to read 4, iclass 36, count 2 2006.201.03:57:10.42#ibcon#read 4, iclass 36, count 2 2006.201.03:57:10.42#ibcon#about to read 5, iclass 36, count 2 2006.201.03:57:10.42#ibcon#read 5, iclass 36, count 2 2006.201.03:57:10.42#ibcon#about to read 6, iclass 36, count 2 2006.201.03:57:10.42#ibcon#read 6, iclass 36, count 2 2006.201.03:57:10.42#ibcon#end of sib2, iclass 36, count 2 2006.201.03:57:10.42#ibcon#*after write, iclass 36, count 2 2006.201.03:57:10.42#ibcon#*before return 0, iclass 36, count 2 2006.201.03:57:10.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:10.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.03:57:10.42#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.03:57:10.42#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:10.42#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:10.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:10.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:10.54#ibcon#enter wrdev, iclass 36, count 0 2006.201.03:57:10.54#ibcon#first serial, iclass 36, count 0 2006.201.03:57:10.54#ibcon#enter sib2, iclass 36, count 0 2006.201.03:57:10.54#ibcon#flushed, iclass 36, count 0 2006.201.03:57:10.54#ibcon#about to write, iclass 36, count 0 2006.201.03:57:10.54#ibcon#wrote, iclass 36, count 0 2006.201.03:57:10.54#ibcon#about to read 3, iclass 36, count 0 2006.201.03:57:10.56#ibcon#read 3, iclass 36, count 0 2006.201.03:57:10.56#ibcon#about to read 4, iclass 36, count 0 2006.201.03:57:10.56#ibcon#read 4, iclass 36, count 0 2006.201.03:57:10.56#ibcon#about to read 5, iclass 36, count 0 2006.201.03:57:10.56#ibcon#read 5, iclass 36, count 0 2006.201.03:57:10.56#ibcon#about to read 6, iclass 36, count 0 2006.201.03:57:10.56#ibcon#read 6, iclass 36, count 0 2006.201.03:57:10.56#ibcon#end of sib2, iclass 36, count 0 2006.201.03:57:10.56#ibcon#*mode == 0, iclass 36, count 0 2006.201.03:57:10.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.03:57:10.56#ibcon#[27=USB\r\n] 2006.201.03:57:10.56#ibcon#*before write, iclass 36, count 0 2006.201.03:57:10.56#ibcon#enter sib2, iclass 36, count 0 2006.201.03:57:10.56#ibcon#flushed, iclass 36, count 0 2006.201.03:57:10.56#ibcon#about to write, iclass 36, count 0 2006.201.03:57:10.56#ibcon#wrote, iclass 36, count 0 2006.201.03:57:10.56#ibcon#about to read 3, iclass 36, count 0 2006.201.03:57:10.59#ibcon#read 3, iclass 36, count 0 2006.201.03:57:10.59#ibcon#about to read 4, iclass 36, count 0 2006.201.03:57:10.59#ibcon#read 4, iclass 36, count 0 2006.201.03:57:10.59#ibcon#about to read 5, iclass 36, count 0 2006.201.03:57:10.59#ibcon#read 5, iclass 36, count 0 2006.201.03:57:10.59#ibcon#about to read 6, iclass 36, count 0 2006.201.03:57:10.59#ibcon#read 6, iclass 36, count 0 2006.201.03:57:10.59#ibcon#end of sib2, iclass 36, count 0 2006.201.03:57:10.59#ibcon#*after write, iclass 36, count 0 2006.201.03:57:10.59#ibcon#*before return 0, iclass 36, count 0 2006.201.03:57:10.59#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:10.59#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.03:57:10.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.03:57:10.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.03:57:10.59$vck44/vblo=7,734.99 2006.201.03:57:10.59#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.03:57:10.59#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.03:57:10.59#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:10.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:10.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:10.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:10.59#ibcon#enter wrdev, iclass 38, count 0 2006.201.03:57:10.59#ibcon#first serial, iclass 38, count 0 2006.201.03:57:10.59#ibcon#enter sib2, iclass 38, count 0 2006.201.03:57:10.59#ibcon#flushed, iclass 38, count 0 2006.201.03:57:10.59#ibcon#about to write, iclass 38, count 0 2006.201.03:57:10.59#ibcon#wrote, iclass 38, count 0 2006.201.03:57:10.59#ibcon#about to read 3, iclass 38, count 0 2006.201.03:57:10.61#ibcon#read 3, iclass 38, count 0 2006.201.03:57:10.61#ibcon#about to read 4, iclass 38, count 0 2006.201.03:57:10.61#ibcon#read 4, iclass 38, count 0 2006.201.03:57:10.61#ibcon#about to read 5, iclass 38, count 0 2006.201.03:57:10.61#ibcon#read 5, iclass 38, count 0 2006.201.03:57:10.61#ibcon#about to read 6, iclass 38, count 0 2006.201.03:57:10.61#ibcon#read 6, iclass 38, count 0 2006.201.03:57:10.61#ibcon#end of sib2, iclass 38, count 0 2006.201.03:57:10.61#ibcon#*mode == 0, iclass 38, count 0 2006.201.03:57:10.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.03:57:10.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.03:57:10.61#ibcon#*before write, iclass 38, count 0 2006.201.03:57:10.61#ibcon#enter sib2, iclass 38, count 0 2006.201.03:57:10.61#ibcon#flushed, iclass 38, count 0 2006.201.03:57:10.61#ibcon#about to write, iclass 38, count 0 2006.201.03:57:10.61#ibcon#wrote, iclass 38, count 0 2006.201.03:57:10.61#ibcon#about to read 3, iclass 38, count 0 2006.201.03:57:10.65#ibcon#read 3, iclass 38, count 0 2006.201.03:57:10.65#ibcon#about to read 4, iclass 38, count 0 2006.201.03:57:10.65#ibcon#read 4, iclass 38, count 0 2006.201.03:57:10.65#ibcon#about to read 5, iclass 38, count 0 2006.201.03:57:10.65#ibcon#read 5, iclass 38, count 0 2006.201.03:57:10.65#ibcon#about to read 6, iclass 38, count 0 2006.201.03:57:10.65#ibcon#read 6, iclass 38, count 0 2006.201.03:57:10.65#ibcon#end of sib2, iclass 38, count 0 2006.201.03:57:10.65#ibcon#*after write, iclass 38, count 0 2006.201.03:57:10.65#ibcon#*before return 0, iclass 38, count 0 2006.201.03:57:10.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:10.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.03:57:10.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.03:57:10.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.03:57:10.65$vck44/vb=7,4 2006.201.03:57:10.65#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.03:57:10.65#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.03:57:10.65#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:10.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:10.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:10.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:10.71#ibcon#enter wrdev, iclass 40, count 2 2006.201.03:57:10.71#ibcon#first serial, iclass 40, count 2 2006.201.03:57:10.71#ibcon#enter sib2, iclass 40, count 2 2006.201.03:57:10.71#ibcon#flushed, iclass 40, count 2 2006.201.03:57:10.71#ibcon#about to write, iclass 40, count 2 2006.201.03:57:10.71#ibcon#wrote, iclass 40, count 2 2006.201.03:57:10.71#ibcon#about to read 3, iclass 40, count 2 2006.201.03:57:10.73#ibcon#read 3, iclass 40, count 2 2006.201.03:57:10.73#ibcon#about to read 4, iclass 40, count 2 2006.201.03:57:10.73#ibcon#read 4, iclass 40, count 2 2006.201.03:57:10.73#ibcon#about to read 5, iclass 40, count 2 2006.201.03:57:10.73#ibcon#read 5, iclass 40, count 2 2006.201.03:57:10.73#ibcon#about to read 6, iclass 40, count 2 2006.201.03:57:10.73#ibcon#read 6, iclass 40, count 2 2006.201.03:57:10.73#ibcon#end of sib2, iclass 40, count 2 2006.201.03:57:10.73#ibcon#*mode == 0, iclass 40, count 2 2006.201.03:57:10.73#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.03:57:10.73#ibcon#[27=AT07-04\r\n] 2006.201.03:57:10.73#ibcon#*before write, iclass 40, count 2 2006.201.03:57:10.73#ibcon#enter sib2, iclass 40, count 2 2006.201.03:57:10.73#ibcon#flushed, iclass 40, count 2 2006.201.03:57:10.73#ibcon#about to write, iclass 40, count 2 2006.201.03:57:10.73#ibcon#wrote, iclass 40, count 2 2006.201.03:57:10.73#ibcon#about to read 3, iclass 40, count 2 2006.201.03:57:10.76#ibcon#read 3, iclass 40, count 2 2006.201.03:57:10.76#ibcon#about to read 4, iclass 40, count 2 2006.201.03:57:10.76#ibcon#read 4, iclass 40, count 2 2006.201.03:57:10.76#ibcon#about to read 5, iclass 40, count 2 2006.201.03:57:10.76#ibcon#read 5, iclass 40, count 2 2006.201.03:57:10.76#ibcon#about to read 6, iclass 40, count 2 2006.201.03:57:10.76#ibcon#read 6, iclass 40, count 2 2006.201.03:57:10.76#ibcon#end of sib2, iclass 40, count 2 2006.201.03:57:10.76#ibcon#*after write, iclass 40, count 2 2006.201.03:57:10.76#ibcon#*before return 0, iclass 40, count 2 2006.201.03:57:10.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:10.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.03:57:10.76#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.03:57:10.76#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:10.76#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:10.88#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:10.88#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:10.88#ibcon#enter wrdev, iclass 40, count 0 2006.201.03:57:10.88#ibcon#first serial, iclass 40, count 0 2006.201.03:57:10.88#ibcon#enter sib2, iclass 40, count 0 2006.201.03:57:10.88#ibcon#flushed, iclass 40, count 0 2006.201.03:57:10.88#ibcon#about to write, iclass 40, count 0 2006.201.03:57:10.88#ibcon#wrote, iclass 40, count 0 2006.201.03:57:10.88#ibcon#about to read 3, iclass 40, count 0 2006.201.03:57:10.90#ibcon#read 3, iclass 40, count 0 2006.201.03:57:10.90#ibcon#about to read 4, iclass 40, count 0 2006.201.03:57:10.90#ibcon#read 4, iclass 40, count 0 2006.201.03:57:10.90#ibcon#about to read 5, iclass 40, count 0 2006.201.03:57:10.90#ibcon#read 5, iclass 40, count 0 2006.201.03:57:10.90#ibcon#about to read 6, iclass 40, count 0 2006.201.03:57:10.90#ibcon#read 6, iclass 40, count 0 2006.201.03:57:10.90#ibcon#end of sib2, iclass 40, count 0 2006.201.03:57:10.90#ibcon#*mode == 0, iclass 40, count 0 2006.201.03:57:10.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.03:57:10.90#ibcon#[27=USB\r\n] 2006.201.03:57:10.90#ibcon#*before write, iclass 40, count 0 2006.201.03:57:10.90#ibcon#enter sib2, iclass 40, count 0 2006.201.03:57:10.90#ibcon#flushed, iclass 40, count 0 2006.201.03:57:10.90#ibcon#about to write, iclass 40, count 0 2006.201.03:57:10.90#ibcon#wrote, iclass 40, count 0 2006.201.03:57:10.90#ibcon#about to read 3, iclass 40, count 0 2006.201.03:57:10.93#ibcon#read 3, iclass 40, count 0 2006.201.03:57:10.93#ibcon#about to read 4, iclass 40, count 0 2006.201.03:57:10.93#ibcon#read 4, iclass 40, count 0 2006.201.03:57:10.93#ibcon#about to read 5, iclass 40, count 0 2006.201.03:57:10.93#ibcon#read 5, iclass 40, count 0 2006.201.03:57:10.93#ibcon#about to read 6, iclass 40, count 0 2006.201.03:57:10.93#ibcon#read 6, iclass 40, count 0 2006.201.03:57:10.93#ibcon#end of sib2, iclass 40, count 0 2006.201.03:57:10.93#ibcon#*after write, iclass 40, count 0 2006.201.03:57:10.93#ibcon#*before return 0, iclass 40, count 0 2006.201.03:57:10.93#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:10.93#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.03:57:10.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.03:57:10.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.03:57:10.93$vck44/vblo=8,744.99 2006.201.03:57:10.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.03:57:10.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.03:57:10.93#ibcon#ireg 17 cls_cnt 0 2006.201.03:57:10.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:10.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:10.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:10.93#ibcon#enter wrdev, iclass 4, count 0 2006.201.03:57:10.93#ibcon#first serial, iclass 4, count 0 2006.201.03:57:10.93#ibcon#enter sib2, iclass 4, count 0 2006.201.03:57:10.93#ibcon#flushed, iclass 4, count 0 2006.201.03:57:10.93#ibcon#about to write, iclass 4, count 0 2006.201.03:57:10.93#ibcon#wrote, iclass 4, count 0 2006.201.03:57:10.93#ibcon#about to read 3, iclass 4, count 0 2006.201.03:57:10.95#ibcon#read 3, iclass 4, count 0 2006.201.03:57:10.95#ibcon#about to read 4, iclass 4, count 0 2006.201.03:57:10.95#ibcon#read 4, iclass 4, count 0 2006.201.03:57:10.95#ibcon#about to read 5, iclass 4, count 0 2006.201.03:57:10.95#ibcon#read 5, iclass 4, count 0 2006.201.03:57:10.95#ibcon#about to read 6, iclass 4, count 0 2006.201.03:57:10.95#ibcon#read 6, iclass 4, count 0 2006.201.03:57:10.95#ibcon#end of sib2, iclass 4, count 0 2006.201.03:57:10.95#ibcon#*mode == 0, iclass 4, count 0 2006.201.03:57:10.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.03:57:10.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.03:57:10.95#ibcon#*before write, iclass 4, count 0 2006.201.03:57:10.95#ibcon#enter sib2, iclass 4, count 0 2006.201.03:57:10.95#ibcon#flushed, iclass 4, count 0 2006.201.03:57:10.95#ibcon#about to write, iclass 4, count 0 2006.201.03:57:10.95#ibcon#wrote, iclass 4, count 0 2006.201.03:57:10.95#ibcon#about to read 3, iclass 4, count 0 2006.201.03:57:10.99#ibcon#read 3, iclass 4, count 0 2006.201.03:57:10.99#ibcon#about to read 4, iclass 4, count 0 2006.201.03:57:10.99#ibcon#read 4, iclass 4, count 0 2006.201.03:57:10.99#ibcon#about to read 5, iclass 4, count 0 2006.201.03:57:10.99#ibcon#read 5, iclass 4, count 0 2006.201.03:57:10.99#ibcon#about to read 6, iclass 4, count 0 2006.201.03:57:10.99#ibcon#read 6, iclass 4, count 0 2006.201.03:57:10.99#ibcon#end of sib2, iclass 4, count 0 2006.201.03:57:10.99#ibcon#*after write, iclass 4, count 0 2006.201.03:57:10.99#ibcon#*before return 0, iclass 4, count 0 2006.201.03:57:10.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:10.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.03:57:10.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.03:57:10.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.03:57:10.99$vck44/vb=8,4 2006.201.03:57:10.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.03:57:10.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.03:57:10.99#ibcon#ireg 11 cls_cnt 2 2006.201.03:57:10.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:11.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:11.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:11.05#ibcon#enter wrdev, iclass 6, count 2 2006.201.03:57:11.05#ibcon#first serial, iclass 6, count 2 2006.201.03:57:11.05#ibcon#enter sib2, iclass 6, count 2 2006.201.03:57:11.05#ibcon#flushed, iclass 6, count 2 2006.201.03:57:11.05#ibcon#about to write, iclass 6, count 2 2006.201.03:57:11.05#ibcon#wrote, iclass 6, count 2 2006.201.03:57:11.05#ibcon#about to read 3, iclass 6, count 2 2006.201.03:57:11.07#ibcon#read 3, iclass 6, count 2 2006.201.03:57:11.07#ibcon#about to read 4, iclass 6, count 2 2006.201.03:57:11.07#ibcon#read 4, iclass 6, count 2 2006.201.03:57:11.07#ibcon#about to read 5, iclass 6, count 2 2006.201.03:57:11.07#ibcon#read 5, iclass 6, count 2 2006.201.03:57:11.07#ibcon#about to read 6, iclass 6, count 2 2006.201.03:57:11.07#ibcon#read 6, iclass 6, count 2 2006.201.03:57:11.07#ibcon#end of sib2, iclass 6, count 2 2006.201.03:57:11.07#ibcon#*mode == 0, iclass 6, count 2 2006.201.03:57:11.07#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.03:57:11.07#ibcon#[27=AT08-04\r\n] 2006.201.03:57:11.07#ibcon#*before write, iclass 6, count 2 2006.201.03:57:11.07#ibcon#enter sib2, iclass 6, count 2 2006.201.03:57:11.07#ibcon#flushed, iclass 6, count 2 2006.201.03:57:11.07#ibcon#about to write, iclass 6, count 2 2006.201.03:57:11.07#ibcon#wrote, iclass 6, count 2 2006.201.03:57:11.07#ibcon#about to read 3, iclass 6, count 2 2006.201.03:57:11.10#ibcon#read 3, iclass 6, count 2 2006.201.03:57:11.10#ibcon#about to read 4, iclass 6, count 2 2006.201.03:57:11.10#ibcon#read 4, iclass 6, count 2 2006.201.03:57:11.10#ibcon#about to read 5, iclass 6, count 2 2006.201.03:57:11.10#ibcon#read 5, iclass 6, count 2 2006.201.03:57:11.10#ibcon#about to read 6, iclass 6, count 2 2006.201.03:57:11.10#ibcon#read 6, iclass 6, count 2 2006.201.03:57:11.10#ibcon#end of sib2, iclass 6, count 2 2006.201.03:57:11.10#ibcon#*after write, iclass 6, count 2 2006.201.03:57:11.10#ibcon#*before return 0, iclass 6, count 2 2006.201.03:57:11.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:11.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.03:57:11.10#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.03:57:11.10#ibcon#ireg 7 cls_cnt 0 2006.201.03:57:11.10#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:11.22#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:11.22#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:11.22#ibcon#enter wrdev, iclass 6, count 0 2006.201.03:57:11.22#ibcon#first serial, iclass 6, count 0 2006.201.03:57:11.22#ibcon#enter sib2, iclass 6, count 0 2006.201.03:57:11.22#ibcon#flushed, iclass 6, count 0 2006.201.03:57:11.22#ibcon#about to write, iclass 6, count 0 2006.201.03:57:11.22#ibcon#wrote, iclass 6, count 0 2006.201.03:57:11.22#ibcon#about to read 3, iclass 6, count 0 2006.201.03:57:11.24#ibcon#read 3, iclass 6, count 0 2006.201.03:57:11.24#ibcon#about to read 4, iclass 6, count 0 2006.201.03:57:11.24#ibcon#read 4, iclass 6, count 0 2006.201.03:57:11.24#ibcon#about to read 5, iclass 6, count 0 2006.201.03:57:11.24#ibcon#read 5, iclass 6, count 0 2006.201.03:57:11.24#ibcon#about to read 6, iclass 6, count 0 2006.201.03:57:11.24#ibcon#read 6, iclass 6, count 0 2006.201.03:57:11.24#ibcon#end of sib2, iclass 6, count 0 2006.201.03:57:11.24#ibcon#*mode == 0, iclass 6, count 0 2006.201.03:57:11.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.03:57:11.24#ibcon#[27=USB\r\n] 2006.201.03:57:11.24#ibcon#*before write, iclass 6, count 0 2006.201.03:57:11.24#ibcon#enter sib2, iclass 6, count 0 2006.201.03:57:11.24#ibcon#flushed, iclass 6, count 0 2006.201.03:57:11.24#ibcon#about to write, iclass 6, count 0 2006.201.03:57:11.24#ibcon#wrote, iclass 6, count 0 2006.201.03:57:11.24#ibcon#about to read 3, iclass 6, count 0 2006.201.03:57:11.27#ibcon#read 3, iclass 6, count 0 2006.201.03:57:11.27#ibcon#about to read 4, iclass 6, count 0 2006.201.03:57:11.27#ibcon#read 4, iclass 6, count 0 2006.201.03:57:11.27#ibcon#about to read 5, iclass 6, count 0 2006.201.03:57:11.27#ibcon#read 5, iclass 6, count 0 2006.201.03:57:11.27#ibcon#about to read 6, iclass 6, count 0 2006.201.03:57:11.27#ibcon#read 6, iclass 6, count 0 2006.201.03:57:11.27#ibcon#end of sib2, iclass 6, count 0 2006.201.03:57:11.27#ibcon#*after write, iclass 6, count 0 2006.201.03:57:11.27#ibcon#*before return 0, iclass 6, count 0 2006.201.03:57:11.27#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:11.27#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.03:57:11.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.03:57:11.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.03:57:11.27$vck44/vabw=wide 2006.201.03:57:11.27#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.03:57:11.27#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.03:57:11.27#ibcon#ireg 8 cls_cnt 0 2006.201.03:57:11.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:11.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:11.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:11.27#ibcon#enter wrdev, iclass 10, count 0 2006.201.03:57:11.27#ibcon#first serial, iclass 10, count 0 2006.201.03:57:11.27#ibcon#enter sib2, iclass 10, count 0 2006.201.03:57:11.27#ibcon#flushed, iclass 10, count 0 2006.201.03:57:11.27#ibcon#about to write, iclass 10, count 0 2006.201.03:57:11.27#ibcon#wrote, iclass 10, count 0 2006.201.03:57:11.27#ibcon#about to read 3, iclass 10, count 0 2006.201.03:57:11.29#ibcon#read 3, iclass 10, count 0 2006.201.03:57:11.29#ibcon#about to read 4, iclass 10, count 0 2006.201.03:57:11.29#ibcon#read 4, iclass 10, count 0 2006.201.03:57:11.29#ibcon#about to read 5, iclass 10, count 0 2006.201.03:57:11.29#ibcon#read 5, iclass 10, count 0 2006.201.03:57:11.29#ibcon#about to read 6, iclass 10, count 0 2006.201.03:57:11.29#ibcon#read 6, iclass 10, count 0 2006.201.03:57:11.29#ibcon#end of sib2, iclass 10, count 0 2006.201.03:57:11.29#ibcon#*mode == 0, iclass 10, count 0 2006.201.03:57:11.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.03:57:11.29#ibcon#[25=BW32\r\n] 2006.201.03:57:11.29#ibcon#*before write, iclass 10, count 0 2006.201.03:57:11.29#ibcon#enter sib2, iclass 10, count 0 2006.201.03:57:11.29#ibcon#flushed, iclass 10, count 0 2006.201.03:57:11.29#ibcon#about to write, iclass 10, count 0 2006.201.03:57:11.29#ibcon#wrote, iclass 10, count 0 2006.201.03:57:11.29#ibcon#about to read 3, iclass 10, count 0 2006.201.03:57:11.32#ibcon#read 3, iclass 10, count 0 2006.201.03:57:11.32#ibcon#about to read 4, iclass 10, count 0 2006.201.03:57:11.32#ibcon#read 4, iclass 10, count 0 2006.201.03:57:11.32#ibcon#about to read 5, iclass 10, count 0 2006.201.03:57:11.32#ibcon#read 5, iclass 10, count 0 2006.201.03:57:11.32#ibcon#about to read 6, iclass 10, count 0 2006.201.03:57:11.32#ibcon#read 6, iclass 10, count 0 2006.201.03:57:11.32#ibcon#end of sib2, iclass 10, count 0 2006.201.03:57:11.32#ibcon#*after write, iclass 10, count 0 2006.201.03:57:11.32#ibcon#*before return 0, iclass 10, count 0 2006.201.03:57:11.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:11.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.03:57:11.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.03:57:11.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.03:57:11.32$vck44/vbbw=wide 2006.201.03:57:11.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.03:57:11.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.03:57:11.32#ibcon#ireg 8 cls_cnt 0 2006.201.03:57:11.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:57:11.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:57:11.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:57:11.39#ibcon#enter wrdev, iclass 12, count 0 2006.201.03:57:11.39#ibcon#first serial, iclass 12, count 0 2006.201.03:57:11.39#ibcon#enter sib2, iclass 12, count 0 2006.201.03:57:11.39#ibcon#flushed, iclass 12, count 0 2006.201.03:57:11.39#ibcon#about to write, iclass 12, count 0 2006.201.03:57:11.39#ibcon#wrote, iclass 12, count 0 2006.201.03:57:11.39#ibcon#about to read 3, iclass 12, count 0 2006.201.03:57:11.41#ibcon#read 3, iclass 12, count 0 2006.201.03:57:11.41#ibcon#about to read 4, iclass 12, count 0 2006.201.03:57:11.41#ibcon#read 4, iclass 12, count 0 2006.201.03:57:11.41#ibcon#about to read 5, iclass 12, count 0 2006.201.03:57:11.41#ibcon#read 5, iclass 12, count 0 2006.201.03:57:11.41#ibcon#about to read 6, iclass 12, count 0 2006.201.03:57:11.41#ibcon#read 6, iclass 12, count 0 2006.201.03:57:11.41#ibcon#end of sib2, iclass 12, count 0 2006.201.03:57:11.41#ibcon#*mode == 0, iclass 12, count 0 2006.201.03:57:11.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.03:57:11.41#ibcon#[27=BW32\r\n] 2006.201.03:57:11.41#ibcon#*before write, iclass 12, count 0 2006.201.03:57:11.41#ibcon#enter sib2, iclass 12, count 0 2006.201.03:57:11.41#ibcon#flushed, iclass 12, count 0 2006.201.03:57:11.41#ibcon#about to write, iclass 12, count 0 2006.201.03:57:11.41#ibcon#wrote, iclass 12, count 0 2006.201.03:57:11.41#ibcon#about to read 3, iclass 12, count 0 2006.201.03:57:11.44#ibcon#read 3, iclass 12, count 0 2006.201.03:57:11.44#ibcon#about to read 4, iclass 12, count 0 2006.201.03:57:11.44#ibcon#read 4, iclass 12, count 0 2006.201.03:57:11.44#ibcon#about to read 5, iclass 12, count 0 2006.201.03:57:11.44#ibcon#read 5, iclass 12, count 0 2006.201.03:57:11.44#ibcon#about to read 6, iclass 12, count 0 2006.201.03:57:11.44#ibcon#read 6, iclass 12, count 0 2006.201.03:57:11.44#ibcon#end of sib2, iclass 12, count 0 2006.201.03:57:11.44#ibcon#*after write, iclass 12, count 0 2006.201.03:57:11.44#ibcon#*before return 0, iclass 12, count 0 2006.201.03:57:11.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:57:11.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.03:57:11.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.03:57:11.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.03:57:11.44$setupk4/ifdk4 2006.201.03:57:11.44$ifdk4/lo= 2006.201.03:57:11.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.03:57:11.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.03:57:11.44$ifdk4/patch= 2006.201.03:57:11.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.03:57:11.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.03:57:11.44$setupk4/!*+20s 2006.201.03:57:12.05#abcon#<5=/04 2.2 4.6 22.90 911004.2\r\n> 2006.201.03:57:12.07#abcon#{5=INTERFACE CLEAR} 2006.201.03:57:12.13#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:57:22.22#abcon#<5=/04 2.2 4.6 22.90 921004.2\r\n> 2006.201.03:57:22.24#abcon#{5=INTERFACE CLEAR} 2006.201.03:57:22.30#abcon#[5=S1D000X0/0*\r\n] 2006.201.03:57:25.90$setupk4/"tpicd 2006.201.03:57:25.90$setupk4/echo=off 2006.201.03:57:25.90$setupk4/xlog=off 2006.201.03:57:25.90:!2006.201.03:57:48 2006.201.03:57:31.13#trakl#Source acquired 2006.201.03:57:31.13#flagr#flagr/antenna,acquired 2006.201.03:57:48.00:preob 2006.201.03:57:48.14/onsource/TRACKING 2006.201.03:57:48.14:!2006.201.03:57:58 2006.201.03:57:58.00:"tape 2006.201.03:57:58.00:"st=record 2006.201.03:57:58.00:data_valid=on 2006.201.03:57:58.00:midob 2006.201.03:57:58.14/onsource/TRACKING 2006.201.03:57:58.14/wx/22.90,1004.2,91 2006.201.03:57:58.22/cable/+6.4661E-03 2006.201.03:57:59.31/va/01,08,usb,yes,31,33 2006.201.03:57:59.31/va/02,07,usb,yes,33,34 2006.201.03:57:59.31/va/03,08,usb,yes,30,31 2006.201.03:57:59.31/va/04,07,usb,yes,34,36 2006.201.03:57:59.31/va/05,04,usb,yes,30,31 2006.201.03:57:59.31/va/06,05,usb,yes,30,30 2006.201.03:57:59.31/va/07,05,usb,yes,29,31 2006.201.03:57:59.31/va/08,04,usb,yes,29,35 2006.201.03:57:59.54/valo/01,524.99,yes,locked 2006.201.03:57:59.54/valo/02,534.99,yes,locked 2006.201.03:57:59.54/valo/03,564.99,yes,locked 2006.201.03:57:59.54/valo/04,624.99,yes,locked 2006.201.03:57:59.54/valo/05,734.99,yes,locked 2006.201.03:57:59.54/valo/06,814.99,yes,locked 2006.201.03:57:59.54/valo/07,864.99,yes,locked 2006.201.03:57:59.54/valo/08,884.99,yes,locked 2006.201.03:58:00.63/vb/01,04,usb,yes,30,28 2006.201.03:58:00.63/vb/02,05,usb,yes,28,28 2006.201.03:58:00.63/vb/03,04,usb,yes,29,32 2006.201.03:58:00.63/vb/04,05,usb,yes,30,29 2006.201.03:58:00.63/vb/05,04,usb,yes,26,29 2006.201.03:58:00.63/vb/06,04,usb,yes,31,27 2006.201.03:58:00.63/vb/07,04,usb,yes,31,31 2006.201.03:58:00.63/vb/08,04,usb,yes,28,32 2006.201.03:58:00.86/vblo/01,629.99,yes,locked 2006.201.03:58:00.86/vblo/02,634.99,yes,locked 2006.201.03:58:00.86/vblo/03,649.99,yes,locked 2006.201.03:58:00.86/vblo/04,679.99,yes,locked 2006.201.03:58:00.86/vblo/05,709.99,yes,locked 2006.201.03:58:00.86/vblo/06,719.99,yes,locked 2006.201.03:58:00.86/vblo/07,734.99,yes,locked 2006.201.03:58:00.86/vblo/08,744.99,yes,locked 2006.201.03:58:01.01/vabw/8 2006.201.03:58:01.16/vbbw/8 2006.201.03:58:01.25/xfe/off,on,15.0 2006.201.03:58:01.64/ifatt/23,28,28,28 2006.201.03:58:02.03/fmout-gps/S +4.54E-07 2006.201.03:58:02.10:!2006.201.04:02:28 2006.201.04:02:28.00:data_valid=off 2006.201.04:02:28.00:"et 2006.201.04:02:28.00:!+3s 2006.201.04:02:31.02:"tape 2006.201.04:02:31.02:postob 2006.201.04:02:31.22/cable/+6.4660E-03 2006.201.04:02:31.22/wx/22.93,1004.1,91 2006.201.04:02:31.30/fmout-gps/S +4.54E-07 2006.201.04:02:31.30:scan_name=201-0408,jd0607,290 2006.201.04:02:31.31:source=1803+784,180045.68,782804.0,2000.0,cw 2006.201.04:02:32.14#flagr#flagr/antenna,new-source 2006.201.04:02:32.14:checkk5 2006.201.04:02:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:02:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:02:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:02:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:02:34.01/chk_obsdata//k5ts1/T2010357??a.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.201.04:02:34.38/chk_obsdata//k5ts2/T2010357??b.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.201.04:02:34.75/chk_obsdata//k5ts3/T2010357??c.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.201.04:02:35.12/chk_obsdata//k5ts4/T2010357??d.dat file size is correct (nominal:1080MB, actual:1076MB). 2006.201.04:02:35.82/k5log//k5ts1_log_newline 2006.201.04:02:36.51/k5log//k5ts2_log_newline 2006.201.04:02:37.20/k5log//k5ts3_log_newline 2006.201.04:02:37.89/k5log//k5ts4_log_newline 2006.201.04:02:37.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:02:37.91:setupk4=1 2006.201.04:02:37.91$setupk4/echo=on 2006.201.04:02:37.91$setupk4/pcalon 2006.201.04:02:37.91$pcalon/"no phase cal control is implemented here 2006.201.04:02:37.91$setupk4/"tpicd=stop 2006.201.04:02:37.91$setupk4/"rec=synch_on 2006.201.04:02:37.91$setupk4/"rec_mode=128 2006.201.04:02:37.91$setupk4/!* 2006.201.04:02:37.91$setupk4/recpk4 2006.201.04:02:37.91$recpk4/recpatch= 2006.201.04:02:37.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:02:37.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:02:37.92$setupk4/vck44 2006.201.04:02:37.92$vck44/valo=1,524.99 2006.201.04:02:37.92#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.04:02:37.92#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.04:02:37.92#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:37.92#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:37.92#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:37.92#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:37.92#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:02:37.92#ibcon#first serial, iclass 2, count 0 2006.201.04:02:37.92#ibcon#enter sib2, iclass 2, count 0 2006.201.04:02:37.92#ibcon#flushed, iclass 2, count 0 2006.201.04:02:37.92#ibcon#about to write, iclass 2, count 0 2006.201.04:02:37.92#ibcon#wrote, iclass 2, count 0 2006.201.04:02:37.92#ibcon#about to read 3, iclass 2, count 0 2006.201.04:02:37.96#ibcon#read 3, iclass 2, count 0 2006.201.04:02:37.96#ibcon#about to read 4, iclass 2, count 0 2006.201.04:02:37.96#ibcon#read 4, iclass 2, count 0 2006.201.04:02:37.96#ibcon#about to read 5, iclass 2, count 0 2006.201.04:02:37.96#ibcon#read 5, iclass 2, count 0 2006.201.04:02:37.96#ibcon#about to read 6, iclass 2, count 0 2006.201.04:02:37.96#ibcon#read 6, iclass 2, count 0 2006.201.04:02:37.96#ibcon#end of sib2, iclass 2, count 0 2006.201.04:02:37.96#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:02:37.96#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:02:37.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:02:37.96#ibcon#*before write, iclass 2, count 0 2006.201.04:02:37.96#ibcon#enter sib2, iclass 2, count 0 2006.201.04:02:37.96#ibcon#flushed, iclass 2, count 0 2006.201.04:02:37.96#ibcon#about to write, iclass 2, count 0 2006.201.04:02:37.96#ibcon#wrote, iclass 2, count 0 2006.201.04:02:37.96#ibcon#about to read 3, iclass 2, count 0 2006.201.04:02:38.01#ibcon#read 3, iclass 2, count 0 2006.201.04:02:38.01#ibcon#about to read 4, iclass 2, count 0 2006.201.04:02:38.01#ibcon#read 4, iclass 2, count 0 2006.201.04:02:38.01#ibcon#about to read 5, iclass 2, count 0 2006.201.04:02:38.01#ibcon#read 5, iclass 2, count 0 2006.201.04:02:38.01#ibcon#about to read 6, iclass 2, count 0 2006.201.04:02:38.01#ibcon#read 6, iclass 2, count 0 2006.201.04:02:38.01#ibcon#end of sib2, iclass 2, count 0 2006.201.04:02:38.01#ibcon#*after write, iclass 2, count 0 2006.201.04:02:38.01#ibcon#*before return 0, iclass 2, count 0 2006.201.04:02:38.01#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:38.01#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:38.01#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:02:38.01#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:02:38.01$vck44/va=1,8 2006.201.04:02:38.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.04:02:38.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.04:02:38.01#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:38.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:38.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:38.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:38.01#ibcon#enter wrdev, iclass 5, count 2 2006.201.04:02:38.01#ibcon#first serial, iclass 5, count 2 2006.201.04:02:38.01#ibcon#enter sib2, iclass 5, count 2 2006.201.04:02:38.01#ibcon#flushed, iclass 5, count 2 2006.201.04:02:38.01#ibcon#about to write, iclass 5, count 2 2006.201.04:02:38.01#ibcon#wrote, iclass 5, count 2 2006.201.04:02:38.01#ibcon#about to read 3, iclass 5, count 2 2006.201.04:02:38.03#ibcon#read 3, iclass 5, count 2 2006.201.04:02:38.03#ibcon#about to read 4, iclass 5, count 2 2006.201.04:02:38.03#ibcon#read 4, iclass 5, count 2 2006.201.04:02:38.03#ibcon#about to read 5, iclass 5, count 2 2006.201.04:02:38.03#ibcon#read 5, iclass 5, count 2 2006.201.04:02:38.03#ibcon#about to read 6, iclass 5, count 2 2006.201.04:02:38.03#ibcon#read 6, iclass 5, count 2 2006.201.04:02:38.03#ibcon#end of sib2, iclass 5, count 2 2006.201.04:02:38.03#ibcon#*mode == 0, iclass 5, count 2 2006.201.04:02:38.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.04:02:38.03#ibcon#[25=AT01-08\r\n] 2006.201.04:02:38.03#ibcon#*before write, iclass 5, count 2 2006.201.04:02:38.03#ibcon#enter sib2, iclass 5, count 2 2006.201.04:02:38.03#ibcon#flushed, iclass 5, count 2 2006.201.04:02:38.03#ibcon#about to write, iclass 5, count 2 2006.201.04:02:38.03#ibcon#wrote, iclass 5, count 2 2006.201.04:02:38.03#ibcon#about to read 3, iclass 5, count 2 2006.201.04:02:38.06#ibcon#read 3, iclass 5, count 2 2006.201.04:02:38.06#ibcon#about to read 4, iclass 5, count 2 2006.201.04:02:38.06#ibcon#read 4, iclass 5, count 2 2006.201.04:02:38.06#ibcon#about to read 5, iclass 5, count 2 2006.201.04:02:38.06#ibcon#read 5, iclass 5, count 2 2006.201.04:02:38.06#ibcon#about to read 6, iclass 5, count 2 2006.201.04:02:38.06#ibcon#read 6, iclass 5, count 2 2006.201.04:02:38.06#ibcon#end of sib2, iclass 5, count 2 2006.201.04:02:38.06#ibcon#*after write, iclass 5, count 2 2006.201.04:02:38.06#ibcon#*before return 0, iclass 5, count 2 2006.201.04:02:38.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:38.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:38.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.04:02:38.06#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:38.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:38.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:38.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:38.18#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:02:38.18#ibcon#first serial, iclass 5, count 0 2006.201.04:02:38.18#ibcon#enter sib2, iclass 5, count 0 2006.201.04:02:38.18#ibcon#flushed, iclass 5, count 0 2006.201.04:02:38.18#ibcon#about to write, iclass 5, count 0 2006.201.04:02:38.18#ibcon#wrote, iclass 5, count 0 2006.201.04:02:38.18#ibcon#about to read 3, iclass 5, count 0 2006.201.04:02:38.20#ibcon#read 3, iclass 5, count 0 2006.201.04:02:38.20#ibcon#about to read 4, iclass 5, count 0 2006.201.04:02:38.20#ibcon#read 4, iclass 5, count 0 2006.201.04:02:38.20#ibcon#about to read 5, iclass 5, count 0 2006.201.04:02:38.20#ibcon#read 5, iclass 5, count 0 2006.201.04:02:38.20#ibcon#about to read 6, iclass 5, count 0 2006.201.04:02:38.20#ibcon#read 6, iclass 5, count 0 2006.201.04:02:38.20#ibcon#end of sib2, iclass 5, count 0 2006.201.04:02:38.20#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:02:38.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:02:38.20#ibcon#[25=USB\r\n] 2006.201.04:02:38.20#ibcon#*before write, iclass 5, count 0 2006.201.04:02:38.20#ibcon#enter sib2, iclass 5, count 0 2006.201.04:02:38.20#ibcon#flushed, iclass 5, count 0 2006.201.04:02:38.20#ibcon#about to write, iclass 5, count 0 2006.201.04:02:38.20#ibcon#wrote, iclass 5, count 0 2006.201.04:02:38.20#ibcon#about to read 3, iclass 5, count 0 2006.201.04:02:38.23#ibcon#read 3, iclass 5, count 0 2006.201.04:02:38.23#ibcon#about to read 4, iclass 5, count 0 2006.201.04:02:38.23#ibcon#read 4, iclass 5, count 0 2006.201.04:02:38.23#ibcon#about to read 5, iclass 5, count 0 2006.201.04:02:38.23#ibcon#read 5, iclass 5, count 0 2006.201.04:02:38.23#ibcon#about to read 6, iclass 5, count 0 2006.201.04:02:38.23#ibcon#read 6, iclass 5, count 0 2006.201.04:02:38.23#ibcon#end of sib2, iclass 5, count 0 2006.201.04:02:38.23#ibcon#*after write, iclass 5, count 0 2006.201.04:02:38.23#ibcon#*before return 0, iclass 5, count 0 2006.201.04:02:38.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:38.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:38.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:02:38.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:02:38.23$vck44/valo=2,534.99 2006.201.04:02:38.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.04:02:38.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.04:02:38.23#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:38.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:38.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:38.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:38.23#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:02:38.23#ibcon#first serial, iclass 7, count 0 2006.201.04:02:38.23#ibcon#enter sib2, iclass 7, count 0 2006.201.04:02:38.23#ibcon#flushed, iclass 7, count 0 2006.201.04:02:38.23#ibcon#about to write, iclass 7, count 0 2006.201.04:02:38.23#ibcon#wrote, iclass 7, count 0 2006.201.04:02:38.23#ibcon#about to read 3, iclass 7, count 0 2006.201.04:02:38.25#ibcon#read 3, iclass 7, count 0 2006.201.04:02:38.25#ibcon#about to read 4, iclass 7, count 0 2006.201.04:02:38.25#ibcon#read 4, iclass 7, count 0 2006.201.04:02:38.25#ibcon#about to read 5, iclass 7, count 0 2006.201.04:02:38.25#ibcon#read 5, iclass 7, count 0 2006.201.04:02:38.25#ibcon#about to read 6, iclass 7, count 0 2006.201.04:02:38.25#ibcon#read 6, iclass 7, count 0 2006.201.04:02:38.25#ibcon#end of sib2, iclass 7, count 0 2006.201.04:02:38.25#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:02:38.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:02:38.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:02:38.25#ibcon#*before write, iclass 7, count 0 2006.201.04:02:38.25#ibcon#enter sib2, iclass 7, count 0 2006.201.04:02:38.25#ibcon#flushed, iclass 7, count 0 2006.201.04:02:38.25#ibcon#about to write, iclass 7, count 0 2006.201.04:02:38.25#ibcon#wrote, iclass 7, count 0 2006.201.04:02:38.25#ibcon#about to read 3, iclass 7, count 0 2006.201.04:02:38.30#ibcon#read 3, iclass 7, count 0 2006.201.04:02:38.30#ibcon#about to read 4, iclass 7, count 0 2006.201.04:02:38.30#ibcon#read 4, iclass 7, count 0 2006.201.04:02:38.30#ibcon#about to read 5, iclass 7, count 0 2006.201.04:02:38.30#ibcon#read 5, iclass 7, count 0 2006.201.04:02:38.30#ibcon#about to read 6, iclass 7, count 0 2006.201.04:02:38.30#ibcon#read 6, iclass 7, count 0 2006.201.04:02:38.30#ibcon#end of sib2, iclass 7, count 0 2006.201.04:02:38.30#ibcon#*after write, iclass 7, count 0 2006.201.04:02:38.30#ibcon#*before return 0, iclass 7, count 0 2006.201.04:02:38.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:38.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:38.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:02:38.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:02:38.30$vck44/va=2,7 2006.201.04:02:38.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.04:02:38.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.04:02:38.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:38.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:38.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:38.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:38.35#ibcon#enter wrdev, iclass 11, count 2 2006.201.04:02:38.35#ibcon#first serial, iclass 11, count 2 2006.201.04:02:38.35#ibcon#enter sib2, iclass 11, count 2 2006.201.04:02:38.35#ibcon#flushed, iclass 11, count 2 2006.201.04:02:38.35#ibcon#about to write, iclass 11, count 2 2006.201.04:02:38.35#ibcon#wrote, iclass 11, count 2 2006.201.04:02:38.35#ibcon#about to read 3, iclass 11, count 2 2006.201.04:02:38.37#ibcon#read 3, iclass 11, count 2 2006.201.04:02:38.37#ibcon#about to read 4, iclass 11, count 2 2006.201.04:02:38.37#ibcon#read 4, iclass 11, count 2 2006.201.04:02:38.37#ibcon#about to read 5, iclass 11, count 2 2006.201.04:02:38.37#ibcon#read 5, iclass 11, count 2 2006.201.04:02:38.37#ibcon#about to read 6, iclass 11, count 2 2006.201.04:02:38.37#ibcon#read 6, iclass 11, count 2 2006.201.04:02:38.37#ibcon#end of sib2, iclass 11, count 2 2006.201.04:02:38.37#ibcon#*mode == 0, iclass 11, count 2 2006.201.04:02:38.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.04:02:38.37#ibcon#[25=AT02-07\r\n] 2006.201.04:02:38.37#ibcon#*before write, iclass 11, count 2 2006.201.04:02:38.37#ibcon#enter sib2, iclass 11, count 2 2006.201.04:02:38.37#ibcon#flushed, iclass 11, count 2 2006.201.04:02:38.37#ibcon#about to write, iclass 11, count 2 2006.201.04:02:38.37#ibcon#wrote, iclass 11, count 2 2006.201.04:02:38.37#ibcon#about to read 3, iclass 11, count 2 2006.201.04:02:38.40#ibcon#read 3, iclass 11, count 2 2006.201.04:02:38.40#ibcon#about to read 4, iclass 11, count 2 2006.201.04:02:38.40#ibcon#read 4, iclass 11, count 2 2006.201.04:02:38.40#ibcon#about to read 5, iclass 11, count 2 2006.201.04:02:38.40#ibcon#read 5, iclass 11, count 2 2006.201.04:02:38.40#ibcon#about to read 6, iclass 11, count 2 2006.201.04:02:38.40#ibcon#read 6, iclass 11, count 2 2006.201.04:02:38.40#ibcon#end of sib2, iclass 11, count 2 2006.201.04:02:38.40#ibcon#*after write, iclass 11, count 2 2006.201.04:02:38.40#ibcon#*before return 0, iclass 11, count 2 2006.201.04:02:38.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:38.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:38.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.04:02:38.40#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:38.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:38.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:38.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:38.52#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:02:38.52#ibcon#first serial, iclass 11, count 0 2006.201.04:02:38.52#ibcon#enter sib2, iclass 11, count 0 2006.201.04:02:38.52#ibcon#flushed, iclass 11, count 0 2006.201.04:02:38.52#ibcon#about to write, iclass 11, count 0 2006.201.04:02:38.52#ibcon#wrote, iclass 11, count 0 2006.201.04:02:38.52#ibcon#about to read 3, iclass 11, count 0 2006.201.04:02:38.54#ibcon#read 3, iclass 11, count 0 2006.201.04:02:38.54#ibcon#about to read 4, iclass 11, count 0 2006.201.04:02:38.54#ibcon#read 4, iclass 11, count 0 2006.201.04:02:38.54#ibcon#about to read 5, iclass 11, count 0 2006.201.04:02:38.54#ibcon#read 5, iclass 11, count 0 2006.201.04:02:38.54#ibcon#about to read 6, iclass 11, count 0 2006.201.04:02:38.54#ibcon#read 6, iclass 11, count 0 2006.201.04:02:38.54#ibcon#end of sib2, iclass 11, count 0 2006.201.04:02:38.54#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:02:38.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:02:38.54#ibcon#[25=USB\r\n] 2006.201.04:02:38.54#ibcon#*before write, iclass 11, count 0 2006.201.04:02:38.54#ibcon#enter sib2, iclass 11, count 0 2006.201.04:02:38.54#ibcon#flushed, iclass 11, count 0 2006.201.04:02:38.54#ibcon#about to write, iclass 11, count 0 2006.201.04:02:38.54#ibcon#wrote, iclass 11, count 0 2006.201.04:02:38.54#ibcon#about to read 3, iclass 11, count 0 2006.201.04:02:38.57#ibcon#read 3, iclass 11, count 0 2006.201.04:02:38.57#ibcon#about to read 4, iclass 11, count 0 2006.201.04:02:38.57#ibcon#read 4, iclass 11, count 0 2006.201.04:02:38.57#ibcon#about to read 5, iclass 11, count 0 2006.201.04:02:38.57#ibcon#read 5, iclass 11, count 0 2006.201.04:02:38.57#ibcon#about to read 6, iclass 11, count 0 2006.201.04:02:38.57#ibcon#read 6, iclass 11, count 0 2006.201.04:02:38.57#ibcon#end of sib2, iclass 11, count 0 2006.201.04:02:38.57#ibcon#*after write, iclass 11, count 0 2006.201.04:02:38.57#ibcon#*before return 0, iclass 11, count 0 2006.201.04:02:38.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:38.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:38.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:02:38.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:02:38.57$vck44/valo=3,564.99 2006.201.04:02:38.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.04:02:38.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.04:02:38.57#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:38.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:38.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:38.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:38.57#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:02:38.57#ibcon#first serial, iclass 13, count 0 2006.201.04:02:38.57#ibcon#enter sib2, iclass 13, count 0 2006.201.04:02:38.57#ibcon#flushed, iclass 13, count 0 2006.201.04:02:38.57#ibcon#about to write, iclass 13, count 0 2006.201.04:02:38.57#ibcon#wrote, iclass 13, count 0 2006.201.04:02:38.57#ibcon#about to read 3, iclass 13, count 0 2006.201.04:02:38.59#ibcon#read 3, iclass 13, count 0 2006.201.04:02:38.59#ibcon#about to read 4, iclass 13, count 0 2006.201.04:02:38.59#ibcon#read 4, iclass 13, count 0 2006.201.04:02:38.59#ibcon#about to read 5, iclass 13, count 0 2006.201.04:02:38.59#ibcon#read 5, iclass 13, count 0 2006.201.04:02:38.59#ibcon#about to read 6, iclass 13, count 0 2006.201.04:02:38.59#ibcon#read 6, iclass 13, count 0 2006.201.04:02:38.59#ibcon#end of sib2, iclass 13, count 0 2006.201.04:02:38.59#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:02:38.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:02:38.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:02:38.59#ibcon#*before write, iclass 13, count 0 2006.201.04:02:38.59#ibcon#enter sib2, iclass 13, count 0 2006.201.04:02:38.59#ibcon#flushed, iclass 13, count 0 2006.201.04:02:38.59#ibcon#about to write, iclass 13, count 0 2006.201.04:02:38.59#ibcon#wrote, iclass 13, count 0 2006.201.04:02:38.59#ibcon#about to read 3, iclass 13, count 0 2006.201.04:02:38.64#ibcon#read 3, iclass 13, count 0 2006.201.04:02:38.64#ibcon#about to read 4, iclass 13, count 0 2006.201.04:02:38.64#ibcon#read 4, iclass 13, count 0 2006.201.04:02:38.64#ibcon#about to read 5, iclass 13, count 0 2006.201.04:02:38.64#ibcon#read 5, iclass 13, count 0 2006.201.04:02:38.64#ibcon#about to read 6, iclass 13, count 0 2006.201.04:02:38.64#ibcon#read 6, iclass 13, count 0 2006.201.04:02:38.64#ibcon#end of sib2, iclass 13, count 0 2006.201.04:02:38.64#ibcon#*after write, iclass 13, count 0 2006.201.04:02:38.64#ibcon#*before return 0, iclass 13, count 0 2006.201.04:02:38.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:38.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:38.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:02:38.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:02:38.64$vck44/va=3,8 2006.201.04:02:38.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.04:02:38.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.04:02:38.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:38.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:38.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:38.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:38.69#ibcon#enter wrdev, iclass 15, count 2 2006.201.04:02:38.69#ibcon#first serial, iclass 15, count 2 2006.201.04:02:38.69#ibcon#enter sib2, iclass 15, count 2 2006.201.04:02:38.69#ibcon#flushed, iclass 15, count 2 2006.201.04:02:38.69#ibcon#about to write, iclass 15, count 2 2006.201.04:02:38.69#ibcon#wrote, iclass 15, count 2 2006.201.04:02:38.69#ibcon#about to read 3, iclass 15, count 2 2006.201.04:02:38.71#ibcon#read 3, iclass 15, count 2 2006.201.04:02:38.71#ibcon#about to read 4, iclass 15, count 2 2006.201.04:02:38.71#ibcon#read 4, iclass 15, count 2 2006.201.04:02:38.71#ibcon#about to read 5, iclass 15, count 2 2006.201.04:02:38.71#ibcon#read 5, iclass 15, count 2 2006.201.04:02:38.71#ibcon#about to read 6, iclass 15, count 2 2006.201.04:02:38.71#ibcon#read 6, iclass 15, count 2 2006.201.04:02:38.71#ibcon#end of sib2, iclass 15, count 2 2006.201.04:02:38.71#ibcon#*mode == 0, iclass 15, count 2 2006.201.04:02:38.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.04:02:38.71#ibcon#[25=AT03-08\r\n] 2006.201.04:02:38.71#ibcon#*before write, iclass 15, count 2 2006.201.04:02:38.71#ibcon#enter sib2, iclass 15, count 2 2006.201.04:02:38.71#ibcon#flushed, iclass 15, count 2 2006.201.04:02:38.71#ibcon#about to write, iclass 15, count 2 2006.201.04:02:38.71#ibcon#wrote, iclass 15, count 2 2006.201.04:02:38.71#ibcon#about to read 3, iclass 15, count 2 2006.201.04:02:38.74#ibcon#read 3, iclass 15, count 2 2006.201.04:02:38.74#ibcon#about to read 4, iclass 15, count 2 2006.201.04:02:38.74#ibcon#read 4, iclass 15, count 2 2006.201.04:02:38.74#ibcon#about to read 5, iclass 15, count 2 2006.201.04:02:38.74#ibcon#read 5, iclass 15, count 2 2006.201.04:02:38.74#ibcon#about to read 6, iclass 15, count 2 2006.201.04:02:38.74#ibcon#read 6, iclass 15, count 2 2006.201.04:02:38.74#ibcon#end of sib2, iclass 15, count 2 2006.201.04:02:38.74#ibcon#*after write, iclass 15, count 2 2006.201.04:02:38.74#ibcon#*before return 0, iclass 15, count 2 2006.201.04:02:38.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:38.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:38.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.04:02:38.74#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:38.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:38.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:38.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:38.86#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:02:38.86#ibcon#first serial, iclass 15, count 0 2006.201.04:02:38.86#ibcon#enter sib2, iclass 15, count 0 2006.201.04:02:38.86#ibcon#flushed, iclass 15, count 0 2006.201.04:02:38.86#ibcon#about to write, iclass 15, count 0 2006.201.04:02:38.86#ibcon#wrote, iclass 15, count 0 2006.201.04:02:38.86#ibcon#about to read 3, iclass 15, count 0 2006.201.04:02:38.88#ibcon#read 3, iclass 15, count 0 2006.201.04:02:38.88#ibcon#about to read 4, iclass 15, count 0 2006.201.04:02:38.88#ibcon#read 4, iclass 15, count 0 2006.201.04:02:38.88#ibcon#about to read 5, iclass 15, count 0 2006.201.04:02:38.88#ibcon#read 5, iclass 15, count 0 2006.201.04:02:38.88#ibcon#about to read 6, iclass 15, count 0 2006.201.04:02:38.88#ibcon#read 6, iclass 15, count 0 2006.201.04:02:38.88#ibcon#end of sib2, iclass 15, count 0 2006.201.04:02:38.88#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:02:38.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:02:38.88#ibcon#[25=USB\r\n] 2006.201.04:02:38.88#ibcon#*before write, iclass 15, count 0 2006.201.04:02:38.88#ibcon#enter sib2, iclass 15, count 0 2006.201.04:02:38.88#ibcon#flushed, iclass 15, count 0 2006.201.04:02:38.88#ibcon#about to write, iclass 15, count 0 2006.201.04:02:38.88#ibcon#wrote, iclass 15, count 0 2006.201.04:02:38.88#ibcon#about to read 3, iclass 15, count 0 2006.201.04:02:38.91#ibcon#read 3, iclass 15, count 0 2006.201.04:02:38.91#ibcon#about to read 4, iclass 15, count 0 2006.201.04:02:38.91#ibcon#read 4, iclass 15, count 0 2006.201.04:02:38.91#ibcon#about to read 5, iclass 15, count 0 2006.201.04:02:38.91#ibcon#read 5, iclass 15, count 0 2006.201.04:02:38.91#ibcon#about to read 6, iclass 15, count 0 2006.201.04:02:38.91#ibcon#read 6, iclass 15, count 0 2006.201.04:02:38.91#ibcon#end of sib2, iclass 15, count 0 2006.201.04:02:38.91#ibcon#*after write, iclass 15, count 0 2006.201.04:02:38.91#ibcon#*before return 0, iclass 15, count 0 2006.201.04:02:38.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:38.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:38.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:02:38.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:02:38.91$vck44/valo=4,624.99 2006.201.04:02:38.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.04:02:38.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.04:02:38.91#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:38.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:38.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:38.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:38.91#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:02:38.91#ibcon#first serial, iclass 17, count 0 2006.201.04:02:38.91#ibcon#enter sib2, iclass 17, count 0 2006.201.04:02:38.91#ibcon#flushed, iclass 17, count 0 2006.201.04:02:38.91#ibcon#about to write, iclass 17, count 0 2006.201.04:02:38.91#ibcon#wrote, iclass 17, count 0 2006.201.04:02:38.91#ibcon#about to read 3, iclass 17, count 0 2006.201.04:02:38.93#ibcon#read 3, iclass 17, count 0 2006.201.04:02:38.93#ibcon#about to read 4, iclass 17, count 0 2006.201.04:02:38.93#ibcon#read 4, iclass 17, count 0 2006.201.04:02:38.93#ibcon#about to read 5, iclass 17, count 0 2006.201.04:02:38.93#ibcon#read 5, iclass 17, count 0 2006.201.04:02:38.93#ibcon#about to read 6, iclass 17, count 0 2006.201.04:02:38.93#ibcon#read 6, iclass 17, count 0 2006.201.04:02:38.93#ibcon#end of sib2, iclass 17, count 0 2006.201.04:02:38.93#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:02:38.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:02:38.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:02:38.93#ibcon#*before write, iclass 17, count 0 2006.201.04:02:38.93#ibcon#enter sib2, iclass 17, count 0 2006.201.04:02:38.93#ibcon#flushed, iclass 17, count 0 2006.201.04:02:38.93#ibcon#about to write, iclass 17, count 0 2006.201.04:02:38.93#ibcon#wrote, iclass 17, count 0 2006.201.04:02:38.93#ibcon#about to read 3, iclass 17, count 0 2006.201.04:02:38.98#ibcon#read 3, iclass 17, count 0 2006.201.04:02:38.98#ibcon#about to read 4, iclass 17, count 0 2006.201.04:02:38.98#ibcon#read 4, iclass 17, count 0 2006.201.04:02:38.98#ibcon#about to read 5, iclass 17, count 0 2006.201.04:02:38.98#ibcon#read 5, iclass 17, count 0 2006.201.04:02:38.98#ibcon#about to read 6, iclass 17, count 0 2006.201.04:02:38.98#ibcon#read 6, iclass 17, count 0 2006.201.04:02:38.98#ibcon#end of sib2, iclass 17, count 0 2006.201.04:02:38.98#ibcon#*after write, iclass 17, count 0 2006.201.04:02:38.98#ibcon#*before return 0, iclass 17, count 0 2006.201.04:02:38.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:38.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:38.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:02:38.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:02:38.98$vck44/va=4,7 2006.201.04:02:38.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.04:02:38.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.04:02:38.98#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:38.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:39.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:39.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:39.03#ibcon#enter wrdev, iclass 19, count 2 2006.201.04:02:39.03#ibcon#first serial, iclass 19, count 2 2006.201.04:02:39.03#ibcon#enter sib2, iclass 19, count 2 2006.201.04:02:39.03#ibcon#flushed, iclass 19, count 2 2006.201.04:02:39.03#ibcon#about to write, iclass 19, count 2 2006.201.04:02:39.03#ibcon#wrote, iclass 19, count 2 2006.201.04:02:39.03#ibcon#about to read 3, iclass 19, count 2 2006.201.04:02:39.05#ibcon#read 3, iclass 19, count 2 2006.201.04:02:39.05#ibcon#about to read 4, iclass 19, count 2 2006.201.04:02:39.05#ibcon#read 4, iclass 19, count 2 2006.201.04:02:39.05#ibcon#about to read 5, iclass 19, count 2 2006.201.04:02:39.05#ibcon#read 5, iclass 19, count 2 2006.201.04:02:39.05#ibcon#about to read 6, iclass 19, count 2 2006.201.04:02:39.05#ibcon#read 6, iclass 19, count 2 2006.201.04:02:39.05#ibcon#end of sib2, iclass 19, count 2 2006.201.04:02:39.05#ibcon#*mode == 0, iclass 19, count 2 2006.201.04:02:39.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.04:02:39.05#ibcon#[25=AT04-07\r\n] 2006.201.04:02:39.05#ibcon#*before write, iclass 19, count 2 2006.201.04:02:39.05#ibcon#enter sib2, iclass 19, count 2 2006.201.04:02:39.05#ibcon#flushed, iclass 19, count 2 2006.201.04:02:39.05#ibcon#about to write, iclass 19, count 2 2006.201.04:02:39.05#ibcon#wrote, iclass 19, count 2 2006.201.04:02:39.05#ibcon#about to read 3, iclass 19, count 2 2006.201.04:02:39.08#ibcon#read 3, iclass 19, count 2 2006.201.04:02:39.08#ibcon#about to read 4, iclass 19, count 2 2006.201.04:02:39.08#ibcon#read 4, iclass 19, count 2 2006.201.04:02:39.08#ibcon#about to read 5, iclass 19, count 2 2006.201.04:02:39.08#ibcon#read 5, iclass 19, count 2 2006.201.04:02:39.08#ibcon#about to read 6, iclass 19, count 2 2006.201.04:02:39.08#ibcon#read 6, iclass 19, count 2 2006.201.04:02:39.08#ibcon#end of sib2, iclass 19, count 2 2006.201.04:02:39.08#ibcon#*after write, iclass 19, count 2 2006.201.04:02:39.08#ibcon#*before return 0, iclass 19, count 2 2006.201.04:02:39.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:39.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:39.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.04:02:39.08#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:39.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:39.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:39.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:39.20#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:02:39.20#ibcon#first serial, iclass 19, count 0 2006.201.04:02:39.20#ibcon#enter sib2, iclass 19, count 0 2006.201.04:02:39.20#ibcon#flushed, iclass 19, count 0 2006.201.04:02:39.20#ibcon#about to write, iclass 19, count 0 2006.201.04:02:39.20#ibcon#wrote, iclass 19, count 0 2006.201.04:02:39.20#ibcon#about to read 3, iclass 19, count 0 2006.201.04:02:39.22#ibcon#read 3, iclass 19, count 0 2006.201.04:02:39.22#ibcon#about to read 4, iclass 19, count 0 2006.201.04:02:39.22#ibcon#read 4, iclass 19, count 0 2006.201.04:02:39.22#ibcon#about to read 5, iclass 19, count 0 2006.201.04:02:39.22#ibcon#read 5, iclass 19, count 0 2006.201.04:02:39.22#ibcon#about to read 6, iclass 19, count 0 2006.201.04:02:39.22#ibcon#read 6, iclass 19, count 0 2006.201.04:02:39.22#ibcon#end of sib2, iclass 19, count 0 2006.201.04:02:39.22#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:02:39.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:02:39.22#ibcon#[25=USB\r\n] 2006.201.04:02:39.22#ibcon#*before write, iclass 19, count 0 2006.201.04:02:39.22#ibcon#enter sib2, iclass 19, count 0 2006.201.04:02:39.22#ibcon#flushed, iclass 19, count 0 2006.201.04:02:39.22#ibcon#about to write, iclass 19, count 0 2006.201.04:02:39.22#ibcon#wrote, iclass 19, count 0 2006.201.04:02:39.22#ibcon#about to read 3, iclass 19, count 0 2006.201.04:02:39.25#ibcon#read 3, iclass 19, count 0 2006.201.04:02:39.25#ibcon#about to read 4, iclass 19, count 0 2006.201.04:02:39.25#ibcon#read 4, iclass 19, count 0 2006.201.04:02:39.25#ibcon#about to read 5, iclass 19, count 0 2006.201.04:02:39.25#ibcon#read 5, iclass 19, count 0 2006.201.04:02:39.25#ibcon#about to read 6, iclass 19, count 0 2006.201.04:02:39.25#ibcon#read 6, iclass 19, count 0 2006.201.04:02:39.25#ibcon#end of sib2, iclass 19, count 0 2006.201.04:02:39.25#ibcon#*after write, iclass 19, count 0 2006.201.04:02:39.25#ibcon#*before return 0, iclass 19, count 0 2006.201.04:02:39.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:39.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:39.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:02:39.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:02:39.25$vck44/valo=5,734.99 2006.201.04:02:39.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.04:02:39.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.04:02:39.25#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:39.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:39.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:39.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:39.25#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:02:39.25#ibcon#first serial, iclass 21, count 0 2006.201.04:02:39.25#ibcon#enter sib2, iclass 21, count 0 2006.201.04:02:39.25#ibcon#flushed, iclass 21, count 0 2006.201.04:02:39.25#ibcon#about to write, iclass 21, count 0 2006.201.04:02:39.25#ibcon#wrote, iclass 21, count 0 2006.201.04:02:39.25#ibcon#about to read 3, iclass 21, count 0 2006.201.04:02:39.27#ibcon#read 3, iclass 21, count 0 2006.201.04:02:39.27#ibcon#about to read 4, iclass 21, count 0 2006.201.04:02:39.27#ibcon#read 4, iclass 21, count 0 2006.201.04:02:39.27#ibcon#about to read 5, iclass 21, count 0 2006.201.04:02:39.27#ibcon#read 5, iclass 21, count 0 2006.201.04:02:39.27#ibcon#about to read 6, iclass 21, count 0 2006.201.04:02:39.27#ibcon#read 6, iclass 21, count 0 2006.201.04:02:39.27#ibcon#end of sib2, iclass 21, count 0 2006.201.04:02:39.27#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:02:39.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:02:39.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:02:39.27#ibcon#*before write, iclass 21, count 0 2006.201.04:02:39.27#ibcon#enter sib2, iclass 21, count 0 2006.201.04:02:39.27#ibcon#flushed, iclass 21, count 0 2006.201.04:02:39.27#ibcon#about to write, iclass 21, count 0 2006.201.04:02:39.27#ibcon#wrote, iclass 21, count 0 2006.201.04:02:39.27#ibcon#about to read 3, iclass 21, count 0 2006.201.04:02:39.31#ibcon#read 3, iclass 21, count 0 2006.201.04:02:39.31#ibcon#about to read 4, iclass 21, count 0 2006.201.04:02:39.31#ibcon#read 4, iclass 21, count 0 2006.201.04:02:39.31#ibcon#about to read 5, iclass 21, count 0 2006.201.04:02:39.31#ibcon#read 5, iclass 21, count 0 2006.201.04:02:39.31#ibcon#about to read 6, iclass 21, count 0 2006.201.04:02:39.31#ibcon#read 6, iclass 21, count 0 2006.201.04:02:39.31#ibcon#end of sib2, iclass 21, count 0 2006.201.04:02:39.31#ibcon#*after write, iclass 21, count 0 2006.201.04:02:39.31#ibcon#*before return 0, iclass 21, count 0 2006.201.04:02:39.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:39.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:39.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:02:39.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:02:39.31$vck44/va=5,4 2006.201.04:02:39.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.04:02:39.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.04:02:39.31#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:39.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:39.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:39.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:39.37#ibcon#enter wrdev, iclass 23, count 2 2006.201.04:02:39.37#ibcon#first serial, iclass 23, count 2 2006.201.04:02:39.37#ibcon#enter sib2, iclass 23, count 2 2006.201.04:02:39.37#ibcon#flushed, iclass 23, count 2 2006.201.04:02:39.37#ibcon#about to write, iclass 23, count 2 2006.201.04:02:39.37#ibcon#wrote, iclass 23, count 2 2006.201.04:02:39.37#ibcon#about to read 3, iclass 23, count 2 2006.201.04:02:39.39#ibcon#read 3, iclass 23, count 2 2006.201.04:02:39.39#ibcon#about to read 4, iclass 23, count 2 2006.201.04:02:39.39#ibcon#read 4, iclass 23, count 2 2006.201.04:02:39.39#ibcon#about to read 5, iclass 23, count 2 2006.201.04:02:39.39#ibcon#read 5, iclass 23, count 2 2006.201.04:02:39.39#ibcon#about to read 6, iclass 23, count 2 2006.201.04:02:39.39#ibcon#read 6, iclass 23, count 2 2006.201.04:02:39.39#ibcon#end of sib2, iclass 23, count 2 2006.201.04:02:39.39#ibcon#*mode == 0, iclass 23, count 2 2006.201.04:02:39.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.04:02:39.39#ibcon#[25=AT05-04\r\n] 2006.201.04:02:39.39#ibcon#*before write, iclass 23, count 2 2006.201.04:02:39.39#ibcon#enter sib2, iclass 23, count 2 2006.201.04:02:39.39#ibcon#flushed, iclass 23, count 2 2006.201.04:02:39.39#ibcon#about to write, iclass 23, count 2 2006.201.04:02:39.39#ibcon#wrote, iclass 23, count 2 2006.201.04:02:39.39#ibcon#about to read 3, iclass 23, count 2 2006.201.04:02:39.42#ibcon#read 3, iclass 23, count 2 2006.201.04:02:39.42#ibcon#about to read 4, iclass 23, count 2 2006.201.04:02:39.42#ibcon#read 4, iclass 23, count 2 2006.201.04:02:39.42#ibcon#about to read 5, iclass 23, count 2 2006.201.04:02:39.42#ibcon#read 5, iclass 23, count 2 2006.201.04:02:39.42#ibcon#about to read 6, iclass 23, count 2 2006.201.04:02:39.42#ibcon#read 6, iclass 23, count 2 2006.201.04:02:39.42#ibcon#end of sib2, iclass 23, count 2 2006.201.04:02:39.42#ibcon#*after write, iclass 23, count 2 2006.201.04:02:39.42#ibcon#*before return 0, iclass 23, count 2 2006.201.04:02:39.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:39.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:39.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.04:02:39.42#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:39.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:39.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:39.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:39.54#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:02:39.54#ibcon#first serial, iclass 23, count 0 2006.201.04:02:39.54#ibcon#enter sib2, iclass 23, count 0 2006.201.04:02:39.54#ibcon#flushed, iclass 23, count 0 2006.201.04:02:39.54#ibcon#about to write, iclass 23, count 0 2006.201.04:02:39.54#ibcon#wrote, iclass 23, count 0 2006.201.04:02:39.54#ibcon#about to read 3, iclass 23, count 0 2006.201.04:02:39.56#ibcon#read 3, iclass 23, count 0 2006.201.04:02:39.56#ibcon#about to read 4, iclass 23, count 0 2006.201.04:02:39.56#ibcon#read 4, iclass 23, count 0 2006.201.04:02:39.56#ibcon#about to read 5, iclass 23, count 0 2006.201.04:02:39.56#ibcon#read 5, iclass 23, count 0 2006.201.04:02:39.56#ibcon#about to read 6, iclass 23, count 0 2006.201.04:02:39.56#ibcon#read 6, iclass 23, count 0 2006.201.04:02:39.56#ibcon#end of sib2, iclass 23, count 0 2006.201.04:02:39.56#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:02:39.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:02:39.56#ibcon#[25=USB\r\n] 2006.201.04:02:39.56#ibcon#*before write, iclass 23, count 0 2006.201.04:02:39.56#ibcon#enter sib2, iclass 23, count 0 2006.201.04:02:39.56#ibcon#flushed, iclass 23, count 0 2006.201.04:02:39.56#ibcon#about to write, iclass 23, count 0 2006.201.04:02:39.56#ibcon#wrote, iclass 23, count 0 2006.201.04:02:39.56#ibcon#about to read 3, iclass 23, count 0 2006.201.04:02:39.59#ibcon#read 3, iclass 23, count 0 2006.201.04:02:39.59#ibcon#about to read 4, iclass 23, count 0 2006.201.04:02:39.59#ibcon#read 4, iclass 23, count 0 2006.201.04:02:39.59#ibcon#about to read 5, iclass 23, count 0 2006.201.04:02:39.59#ibcon#read 5, iclass 23, count 0 2006.201.04:02:39.59#ibcon#about to read 6, iclass 23, count 0 2006.201.04:02:39.59#ibcon#read 6, iclass 23, count 0 2006.201.04:02:39.59#ibcon#end of sib2, iclass 23, count 0 2006.201.04:02:39.59#ibcon#*after write, iclass 23, count 0 2006.201.04:02:39.59#ibcon#*before return 0, iclass 23, count 0 2006.201.04:02:39.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:39.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:39.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:02:39.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:02:39.59$vck44/valo=6,814.99 2006.201.04:02:39.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.04:02:39.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.04:02:39.59#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:39.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:39.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:39.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:39.59#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:02:39.59#ibcon#first serial, iclass 25, count 0 2006.201.04:02:39.59#ibcon#enter sib2, iclass 25, count 0 2006.201.04:02:39.59#ibcon#flushed, iclass 25, count 0 2006.201.04:02:39.59#ibcon#about to write, iclass 25, count 0 2006.201.04:02:39.59#ibcon#wrote, iclass 25, count 0 2006.201.04:02:39.59#ibcon#about to read 3, iclass 25, count 0 2006.201.04:02:39.61#ibcon#read 3, iclass 25, count 0 2006.201.04:02:39.61#ibcon#about to read 4, iclass 25, count 0 2006.201.04:02:39.61#ibcon#read 4, iclass 25, count 0 2006.201.04:02:39.61#ibcon#about to read 5, iclass 25, count 0 2006.201.04:02:39.61#ibcon#read 5, iclass 25, count 0 2006.201.04:02:39.61#ibcon#about to read 6, iclass 25, count 0 2006.201.04:02:39.61#ibcon#read 6, iclass 25, count 0 2006.201.04:02:39.61#ibcon#end of sib2, iclass 25, count 0 2006.201.04:02:39.61#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:02:39.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:02:39.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:02:39.61#ibcon#*before write, iclass 25, count 0 2006.201.04:02:39.61#ibcon#enter sib2, iclass 25, count 0 2006.201.04:02:39.61#ibcon#flushed, iclass 25, count 0 2006.201.04:02:39.61#ibcon#about to write, iclass 25, count 0 2006.201.04:02:39.61#ibcon#wrote, iclass 25, count 0 2006.201.04:02:39.61#ibcon#about to read 3, iclass 25, count 0 2006.201.04:02:39.65#ibcon#read 3, iclass 25, count 0 2006.201.04:02:39.65#ibcon#about to read 4, iclass 25, count 0 2006.201.04:02:39.65#ibcon#read 4, iclass 25, count 0 2006.201.04:02:39.65#ibcon#about to read 5, iclass 25, count 0 2006.201.04:02:39.65#ibcon#read 5, iclass 25, count 0 2006.201.04:02:39.65#ibcon#about to read 6, iclass 25, count 0 2006.201.04:02:39.65#ibcon#read 6, iclass 25, count 0 2006.201.04:02:39.65#ibcon#end of sib2, iclass 25, count 0 2006.201.04:02:39.65#ibcon#*after write, iclass 25, count 0 2006.201.04:02:39.65#ibcon#*before return 0, iclass 25, count 0 2006.201.04:02:39.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:39.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:39.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:02:39.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:02:39.65$vck44/va=6,5 2006.201.04:02:39.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.04:02:39.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.04:02:39.65#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:39.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:39.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:39.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:39.71#ibcon#enter wrdev, iclass 27, count 2 2006.201.04:02:39.71#ibcon#first serial, iclass 27, count 2 2006.201.04:02:39.71#ibcon#enter sib2, iclass 27, count 2 2006.201.04:02:39.71#ibcon#flushed, iclass 27, count 2 2006.201.04:02:39.71#ibcon#about to write, iclass 27, count 2 2006.201.04:02:39.71#ibcon#wrote, iclass 27, count 2 2006.201.04:02:39.71#ibcon#about to read 3, iclass 27, count 2 2006.201.04:02:39.73#ibcon#read 3, iclass 27, count 2 2006.201.04:02:39.73#ibcon#about to read 4, iclass 27, count 2 2006.201.04:02:39.73#ibcon#read 4, iclass 27, count 2 2006.201.04:02:39.73#ibcon#about to read 5, iclass 27, count 2 2006.201.04:02:39.73#ibcon#read 5, iclass 27, count 2 2006.201.04:02:39.73#ibcon#about to read 6, iclass 27, count 2 2006.201.04:02:39.73#ibcon#read 6, iclass 27, count 2 2006.201.04:02:39.73#ibcon#end of sib2, iclass 27, count 2 2006.201.04:02:39.73#ibcon#*mode == 0, iclass 27, count 2 2006.201.04:02:39.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.04:02:39.73#ibcon#[25=AT06-05\r\n] 2006.201.04:02:39.73#ibcon#*before write, iclass 27, count 2 2006.201.04:02:39.73#ibcon#enter sib2, iclass 27, count 2 2006.201.04:02:39.73#ibcon#flushed, iclass 27, count 2 2006.201.04:02:39.73#ibcon#about to write, iclass 27, count 2 2006.201.04:02:39.73#ibcon#wrote, iclass 27, count 2 2006.201.04:02:39.73#ibcon#about to read 3, iclass 27, count 2 2006.201.04:02:39.76#ibcon#read 3, iclass 27, count 2 2006.201.04:02:39.76#ibcon#about to read 4, iclass 27, count 2 2006.201.04:02:39.76#ibcon#read 4, iclass 27, count 2 2006.201.04:02:39.76#ibcon#about to read 5, iclass 27, count 2 2006.201.04:02:39.76#ibcon#read 5, iclass 27, count 2 2006.201.04:02:39.76#ibcon#about to read 6, iclass 27, count 2 2006.201.04:02:39.76#ibcon#read 6, iclass 27, count 2 2006.201.04:02:39.76#ibcon#end of sib2, iclass 27, count 2 2006.201.04:02:39.76#ibcon#*after write, iclass 27, count 2 2006.201.04:02:39.76#ibcon#*before return 0, iclass 27, count 2 2006.201.04:02:39.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:39.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:39.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.04:02:39.76#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:39.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:39.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:39.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:39.88#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:02:39.88#ibcon#first serial, iclass 27, count 0 2006.201.04:02:39.88#ibcon#enter sib2, iclass 27, count 0 2006.201.04:02:39.88#ibcon#flushed, iclass 27, count 0 2006.201.04:02:39.88#ibcon#about to write, iclass 27, count 0 2006.201.04:02:39.88#ibcon#wrote, iclass 27, count 0 2006.201.04:02:39.88#ibcon#about to read 3, iclass 27, count 0 2006.201.04:02:39.90#ibcon#read 3, iclass 27, count 0 2006.201.04:02:39.90#ibcon#about to read 4, iclass 27, count 0 2006.201.04:02:39.90#ibcon#read 4, iclass 27, count 0 2006.201.04:02:39.90#ibcon#about to read 5, iclass 27, count 0 2006.201.04:02:39.90#ibcon#read 5, iclass 27, count 0 2006.201.04:02:39.90#ibcon#about to read 6, iclass 27, count 0 2006.201.04:02:39.90#ibcon#read 6, iclass 27, count 0 2006.201.04:02:39.90#ibcon#end of sib2, iclass 27, count 0 2006.201.04:02:39.90#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:02:39.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:02:39.90#ibcon#[25=USB\r\n] 2006.201.04:02:39.90#ibcon#*before write, iclass 27, count 0 2006.201.04:02:39.90#ibcon#enter sib2, iclass 27, count 0 2006.201.04:02:39.90#ibcon#flushed, iclass 27, count 0 2006.201.04:02:39.90#ibcon#about to write, iclass 27, count 0 2006.201.04:02:39.90#ibcon#wrote, iclass 27, count 0 2006.201.04:02:39.90#ibcon#about to read 3, iclass 27, count 0 2006.201.04:02:39.93#ibcon#read 3, iclass 27, count 0 2006.201.04:02:39.93#ibcon#about to read 4, iclass 27, count 0 2006.201.04:02:39.93#ibcon#read 4, iclass 27, count 0 2006.201.04:02:39.93#ibcon#about to read 5, iclass 27, count 0 2006.201.04:02:39.93#ibcon#read 5, iclass 27, count 0 2006.201.04:02:39.93#ibcon#about to read 6, iclass 27, count 0 2006.201.04:02:39.93#ibcon#read 6, iclass 27, count 0 2006.201.04:02:39.93#ibcon#end of sib2, iclass 27, count 0 2006.201.04:02:39.93#ibcon#*after write, iclass 27, count 0 2006.201.04:02:39.93#ibcon#*before return 0, iclass 27, count 0 2006.201.04:02:39.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:39.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:39.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:02:39.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:02:39.93$vck44/valo=7,864.99 2006.201.04:02:39.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.04:02:39.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.04:02:39.93#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:39.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:39.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:39.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:39.93#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:02:39.93#ibcon#first serial, iclass 29, count 0 2006.201.04:02:39.93#ibcon#enter sib2, iclass 29, count 0 2006.201.04:02:39.93#ibcon#flushed, iclass 29, count 0 2006.201.04:02:39.93#ibcon#about to write, iclass 29, count 0 2006.201.04:02:39.93#ibcon#wrote, iclass 29, count 0 2006.201.04:02:39.93#ibcon#about to read 3, iclass 29, count 0 2006.201.04:02:39.95#ibcon#read 3, iclass 29, count 0 2006.201.04:02:39.95#ibcon#about to read 4, iclass 29, count 0 2006.201.04:02:39.95#ibcon#read 4, iclass 29, count 0 2006.201.04:02:39.95#ibcon#about to read 5, iclass 29, count 0 2006.201.04:02:39.95#ibcon#read 5, iclass 29, count 0 2006.201.04:02:39.95#ibcon#about to read 6, iclass 29, count 0 2006.201.04:02:39.95#ibcon#read 6, iclass 29, count 0 2006.201.04:02:39.95#ibcon#end of sib2, iclass 29, count 0 2006.201.04:02:39.95#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:02:39.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:02:39.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:02:39.95#ibcon#*before write, iclass 29, count 0 2006.201.04:02:39.95#ibcon#enter sib2, iclass 29, count 0 2006.201.04:02:39.95#ibcon#flushed, iclass 29, count 0 2006.201.04:02:39.95#ibcon#about to write, iclass 29, count 0 2006.201.04:02:39.95#ibcon#wrote, iclass 29, count 0 2006.201.04:02:39.95#ibcon#about to read 3, iclass 29, count 0 2006.201.04:02:39.99#ibcon#read 3, iclass 29, count 0 2006.201.04:02:39.99#ibcon#about to read 4, iclass 29, count 0 2006.201.04:02:39.99#ibcon#read 4, iclass 29, count 0 2006.201.04:02:39.99#ibcon#about to read 5, iclass 29, count 0 2006.201.04:02:39.99#ibcon#read 5, iclass 29, count 0 2006.201.04:02:39.99#ibcon#about to read 6, iclass 29, count 0 2006.201.04:02:39.99#ibcon#read 6, iclass 29, count 0 2006.201.04:02:39.99#ibcon#end of sib2, iclass 29, count 0 2006.201.04:02:39.99#ibcon#*after write, iclass 29, count 0 2006.201.04:02:39.99#ibcon#*before return 0, iclass 29, count 0 2006.201.04:02:39.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:39.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:39.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:02:39.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:02:39.99$vck44/va=7,5 2006.201.04:02:39.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.04:02:39.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.04:02:39.99#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:39.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:40.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:40.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:40.05#ibcon#enter wrdev, iclass 31, count 2 2006.201.04:02:40.05#ibcon#first serial, iclass 31, count 2 2006.201.04:02:40.05#ibcon#enter sib2, iclass 31, count 2 2006.201.04:02:40.05#ibcon#flushed, iclass 31, count 2 2006.201.04:02:40.05#ibcon#about to write, iclass 31, count 2 2006.201.04:02:40.05#ibcon#wrote, iclass 31, count 2 2006.201.04:02:40.05#ibcon#about to read 3, iclass 31, count 2 2006.201.04:02:40.07#ibcon#read 3, iclass 31, count 2 2006.201.04:02:40.07#ibcon#about to read 4, iclass 31, count 2 2006.201.04:02:40.07#ibcon#read 4, iclass 31, count 2 2006.201.04:02:40.07#ibcon#about to read 5, iclass 31, count 2 2006.201.04:02:40.07#ibcon#read 5, iclass 31, count 2 2006.201.04:02:40.07#ibcon#about to read 6, iclass 31, count 2 2006.201.04:02:40.07#ibcon#read 6, iclass 31, count 2 2006.201.04:02:40.07#ibcon#end of sib2, iclass 31, count 2 2006.201.04:02:40.07#ibcon#*mode == 0, iclass 31, count 2 2006.201.04:02:40.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.04:02:40.07#ibcon#[25=AT07-05\r\n] 2006.201.04:02:40.07#ibcon#*before write, iclass 31, count 2 2006.201.04:02:40.07#ibcon#enter sib2, iclass 31, count 2 2006.201.04:02:40.07#ibcon#flushed, iclass 31, count 2 2006.201.04:02:40.07#ibcon#about to write, iclass 31, count 2 2006.201.04:02:40.07#ibcon#wrote, iclass 31, count 2 2006.201.04:02:40.07#ibcon#about to read 3, iclass 31, count 2 2006.201.04:02:40.10#ibcon#read 3, iclass 31, count 2 2006.201.04:02:40.10#ibcon#about to read 4, iclass 31, count 2 2006.201.04:02:40.10#ibcon#read 4, iclass 31, count 2 2006.201.04:02:40.10#ibcon#about to read 5, iclass 31, count 2 2006.201.04:02:40.10#ibcon#read 5, iclass 31, count 2 2006.201.04:02:40.10#ibcon#about to read 6, iclass 31, count 2 2006.201.04:02:40.10#ibcon#read 6, iclass 31, count 2 2006.201.04:02:40.10#ibcon#end of sib2, iclass 31, count 2 2006.201.04:02:40.10#ibcon#*after write, iclass 31, count 2 2006.201.04:02:40.10#ibcon#*before return 0, iclass 31, count 2 2006.201.04:02:40.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:40.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:40.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.04:02:40.10#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:40.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:40.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:40.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:40.22#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:02:40.22#ibcon#first serial, iclass 31, count 0 2006.201.04:02:40.22#ibcon#enter sib2, iclass 31, count 0 2006.201.04:02:40.22#ibcon#flushed, iclass 31, count 0 2006.201.04:02:40.22#ibcon#about to write, iclass 31, count 0 2006.201.04:02:40.22#ibcon#wrote, iclass 31, count 0 2006.201.04:02:40.22#ibcon#about to read 3, iclass 31, count 0 2006.201.04:02:40.24#ibcon#read 3, iclass 31, count 0 2006.201.04:02:40.24#ibcon#about to read 4, iclass 31, count 0 2006.201.04:02:40.24#ibcon#read 4, iclass 31, count 0 2006.201.04:02:40.24#ibcon#about to read 5, iclass 31, count 0 2006.201.04:02:40.24#ibcon#read 5, iclass 31, count 0 2006.201.04:02:40.24#ibcon#about to read 6, iclass 31, count 0 2006.201.04:02:40.24#ibcon#read 6, iclass 31, count 0 2006.201.04:02:40.24#ibcon#end of sib2, iclass 31, count 0 2006.201.04:02:40.24#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:02:40.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:02:40.24#ibcon#[25=USB\r\n] 2006.201.04:02:40.24#ibcon#*before write, iclass 31, count 0 2006.201.04:02:40.24#ibcon#enter sib2, iclass 31, count 0 2006.201.04:02:40.24#ibcon#flushed, iclass 31, count 0 2006.201.04:02:40.24#ibcon#about to write, iclass 31, count 0 2006.201.04:02:40.24#ibcon#wrote, iclass 31, count 0 2006.201.04:02:40.24#ibcon#about to read 3, iclass 31, count 0 2006.201.04:02:40.27#ibcon#read 3, iclass 31, count 0 2006.201.04:02:40.27#ibcon#about to read 4, iclass 31, count 0 2006.201.04:02:40.27#ibcon#read 4, iclass 31, count 0 2006.201.04:02:40.27#ibcon#about to read 5, iclass 31, count 0 2006.201.04:02:40.27#ibcon#read 5, iclass 31, count 0 2006.201.04:02:40.27#ibcon#about to read 6, iclass 31, count 0 2006.201.04:02:40.27#ibcon#read 6, iclass 31, count 0 2006.201.04:02:40.27#ibcon#end of sib2, iclass 31, count 0 2006.201.04:02:40.27#ibcon#*after write, iclass 31, count 0 2006.201.04:02:40.27#ibcon#*before return 0, iclass 31, count 0 2006.201.04:02:40.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:40.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:40.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:02:40.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:02:40.27$vck44/valo=8,884.99 2006.201.04:02:40.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.04:02:40.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.04:02:40.27#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:40.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:40.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:40.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:40.27#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:02:40.27#ibcon#first serial, iclass 33, count 0 2006.201.04:02:40.27#ibcon#enter sib2, iclass 33, count 0 2006.201.04:02:40.27#ibcon#flushed, iclass 33, count 0 2006.201.04:02:40.27#ibcon#about to write, iclass 33, count 0 2006.201.04:02:40.27#ibcon#wrote, iclass 33, count 0 2006.201.04:02:40.27#ibcon#about to read 3, iclass 33, count 0 2006.201.04:02:40.29#ibcon#read 3, iclass 33, count 0 2006.201.04:02:40.29#ibcon#about to read 4, iclass 33, count 0 2006.201.04:02:40.29#ibcon#read 4, iclass 33, count 0 2006.201.04:02:40.29#ibcon#about to read 5, iclass 33, count 0 2006.201.04:02:40.29#ibcon#read 5, iclass 33, count 0 2006.201.04:02:40.29#ibcon#about to read 6, iclass 33, count 0 2006.201.04:02:40.29#ibcon#read 6, iclass 33, count 0 2006.201.04:02:40.29#ibcon#end of sib2, iclass 33, count 0 2006.201.04:02:40.29#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:02:40.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:02:40.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:02:40.29#ibcon#*before write, iclass 33, count 0 2006.201.04:02:40.29#ibcon#enter sib2, iclass 33, count 0 2006.201.04:02:40.29#ibcon#flushed, iclass 33, count 0 2006.201.04:02:40.29#ibcon#about to write, iclass 33, count 0 2006.201.04:02:40.29#ibcon#wrote, iclass 33, count 0 2006.201.04:02:40.29#ibcon#about to read 3, iclass 33, count 0 2006.201.04:02:40.33#ibcon#read 3, iclass 33, count 0 2006.201.04:02:40.33#ibcon#about to read 4, iclass 33, count 0 2006.201.04:02:40.33#ibcon#read 4, iclass 33, count 0 2006.201.04:02:40.33#ibcon#about to read 5, iclass 33, count 0 2006.201.04:02:40.33#ibcon#read 5, iclass 33, count 0 2006.201.04:02:40.33#ibcon#about to read 6, iclass 33, count 0 2006.201.04:02:40.33#ibcon#read 6, iclass 33, count 0 2006.201.04:02:40.33#ibcon#end of sib2, iclass 33, count 0 2006.201.04:02:40.33#ibcon#*after write, iclass 33, count 0 2006.201.04:02:40.33#ibcon#*before return 0, iclass 33, count 0 2006.201.04:02:40.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:40.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:40.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:02:40.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:02:40.33$vck44/va=8,4 2006.201.04:02:40.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.04:02:40.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.04:02:40.33#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:40.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:02:40.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:02:40.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:02:40.39#ibcon#enter wrdev, iclass 35, count 2 2006.201.04:02:40.39#ibcon#first serial, iclass 35, count 2 2006.201.04:02:40.39#ibcon#enter sib2, iclass 35, count 2 2006.201.04:02:40.39#ibcon#flushed, iclass 35, count 2 2006.201.04:02:40.39#ibcon#about to write, iclass 35, count 2 2006.201.04:02:40.39#ibcon#wrote, iclass 35, count 2 2006.201.04:02:40.39#ibcon#about to read 3, iclass 35, count 2 2006.201.04:02:40.41#ibcon#read 3, iclass 35, count 2 2006.201.04:02:40.41#ibcon#about to read 4, iclass 35, count 2 2006.201.04:02:40.41#ibcon#read 4, iclass 35, count 2 2006.201.04:02:40.41#ibcon#about to read 5, iclass 35, count 2 2006.201.04:02:40.41#ibcon#read 5, iclass 35, count 2 2006.201.04:02:40.41#ibcon#about to read 6, iclass 35, count 2 2006.201.04:02:40.41#ibcon#read 6, iclass 35, count 2 2006.201.04:02:40.41#ibcon#end of sib2, iclass 35, count 2 2006.201.04:02:40.41#ibcon#*mode == 0, iclass 35, count 2 2006.201.04:02:40.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.04:02:40.41#ibcon#[25=AT08-04\r\n] 2006.201.04:02:40.41#ibcon#*before write, iclass 35, count 2 2006.201.04:02:40.41#ibcon#enter sib2, iclass 35, count 2 2006.201.04:02:40.41#ibcon#flushed, iclass 35, count 2 2006.201.04:02:40.41#ibcon#about to write, iclass 35, count 2 2006.201.04:02:40.41#ibcon#wrote, iclass 35, count 2 2006.201.04:02:40.41#ibcon#about to read 3, iclass 35, count 2 2006.201.04:02:40.44#ibcon#read 3, iclass 35, count 2 2006.201.04:02:40.44#ibcon#about to read 4, iclass 35, count 2 2006.201.04:02:40.44#ibcon#read 4, iclass 35, count 2 2006.201.04:02:40.44#ibcon#about to read 5, iclass 35, count 2 2006.201.04:02:40.44#ibcon#read 5, iclass 35, count 2 2006.201.04:02:40.44#ibcon#about to read 6, iclass 35, count 2 2006.201.04:02:40.44#ibcon#read 6, iclass 35, count 2 2006.201.04:02:40.44#ibcon#end of sib2, iclass 35, count 2 2006.201.04:02:40.44#ibcon#*after write, iclass 35, count 2 2006.201.04:02:40.44#ibcon#*before return 0, iclass 35, count 2 2006.201.04:02:40.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:02:40.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:02:40.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.04:02:40.44#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:40.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:02:40.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:02:40.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:02:40.56#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:02:40.56#ibcon#first serial, iclass 35, count 0 2006.201.04:02:40.56#ibcon#enter sib2, iclass 35, count 0 2006.201.04:02:40.56#ibcon#flushed, iclass 35, count 0 2006.201.04:02:40.56#ibcon#about to write, iclass 35, count 0 2006.201.04:02:40.56#ibcon#wrote, iclass 35, count 0 2006.201.04:02:40.56#ibcon#about to read 3, iclass 35, count 0 2006.201.04:02:40.58#ibcon#read 3, iclass 35, count 0 2006.201.04:02:40.58#ibcon#about to read 4, iclass 35, count 0 2006.201.04:02:40.58#ibcon#read 4, iclass 35, count 0 2006.201.04:02:40.58#ibcon#about to read 5, iclass 35, count 0 2006.201.04:02:40.58#ibcon#read 5, iclass 35, count 0 2006.201.04:02:40.58#ibcon#about to read 6, iclass 35, count 0 2006.201.04:02:40.58#ibcon#read 6, iclass 35, count 0 2006.201.04:02:40.58#ibcon#end of sib2, iclass 35, count 0 2006.201.04:02:40.58#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:02:40.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:02:40.58#ibcon#[25=USB\r\n] 2006.201.04:02:40.58#ibcon#*before write, iclass 35, count 0 2006.201.04:02:40.58#ibcon#enter sib2, iclass 35, count 0 2006.201.04:02:40.58#ibcon#flushed, iclass 35, count 0 2006.201.04:02:40.58#ibcon#about to write, iclass 35, count 0 2006.201.04:02:40.58#ibcon#wrote, iclass 35, count 0 2006.201.04:02:40.58#ibcon#about to read 3, iclass 35, count 0 2006.201.04:02:40.61#ibcon#read 3, iclass 35, count 0 2006.201.04:02:40.61#ibcon#about to read 4, iclass 35, count 0 2006.201.04:02:40.61#ibcon#read 4, iclass 35, count 0 2006.201.04:02:40.61#ibcon#about to read 5, iclass 35, count 0 2006.201.04:02:40.61#ibcon#read 5, iclass 35, count 0 2006.201.04:02:40.61#ibcon#about to read 6, iclass 35, count 0 2006.201.04:02:40.61#ibcon#read 6, iclass 35, count 0 2006.201.04:02:40.61#ibcon#end of sib2, iclass 35, count 0 2006.201.04:02:40.61#ibcon#*after write, iclass 35, count 0 2006.201.04:02:40.61#ibcon#*before return 0, iclass 35, count 0 2006.201.04:02:40.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:02:40.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:02:40.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:02:40.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:02:40.61$vck44/vblo=1,629.99 2006.201.04:02:40.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.04:02:40.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.04:02:40.61#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:40.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:02:40.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:02:40.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:02:40.61#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:02:40.61#ibcon#first serial, iclass 37, count 0 2006.201.04:02:40.61#ibcon#enter sib2, iclass 37, count 0 2006.201.04:02:40.61#ibcon#flushed, iclass 37, count 0 2006.201.04:02:40.61#ibcon#about to write, iclass 37, count 0 2006.201.04:02:40.61#ibcon#wrote, iclass 37, count 0 2006.201.04:02:40.61#ibcon#about to read 3, iclass 37, count 0 2006.201.04:02:40.63#ibcon#read 3, iclass 37, count 0 2006.201.04:02:40.63#ibcon#about to read 4, iclass 37, count 0 2006.201.04:02:40.63#ibcon#read 4, iclass 37, count 0 2006.201.04:02:40.63#ibcon#about to read 5, iclass 37, count 0 2006.201.04:02:40.63#ibcon#read 5, iclass 37, count 0 2006.201.04:02:40.63#ibcon#about to read 6, iclass 37, count 0 2006.201.04:02:40.63#ibcon#read 6, iclass 37, count 0 2006.201.04:02:40.63#ibcon#end of sib2, iclass 37, count 0 2006.201.04:02:40.63#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:02:40.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:02:40.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:02:40.63#ibcon#*before write, iclass 37, count 0 2006.201.04:02:40.63#ibcon#enter sib2, iclass 37, count 0 2006.201.04:02:40.63#ibcon#flushed, iclass 37, count 0 2006.201.04:02:40.63#ibcon#about to write, iclass 37, count 0 2006.201.04:02:40.63#ibcon#wrote, iclass 37, count 0 2006.201.04:02:40.63#ibcon#about to read 3, iclass 37, count 0 2006.201.04:02:40.67#ibcon#read 3, iclass 37, count 0 2006.201.04:02:40.67#ibcon#about to read 4, iclass 37, count 0 2006.201.04:02:40.67#ibcon#read 4, iclass 37, count 0 2006.201.04:02:40.67#ibcon#about to read 5, iclass 37, count 0 2006.201.04:02:40.67#ibcon#read 5, iclass 37, count 0 2006.201.04:02:40.67#ibcon#about to read 6, iclass 37, count 0 2006.201.04:02:40.67#ibcon#read 6, iclass 37, count 0 2006.201.04:02:40.67#ibcon#end of sib2, iclass 37, count 0 2006.201.04:02:40.67#ibcon#*after write, iclass 37, count 0 2006.201.04:02:40.67#ibcon#*before return 0, iclass 37, count 0 2006.201.04:02:40.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:02:40.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:02:40.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:02:40.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:02:40.67$vck44/vb=1,4 2006.201.04:02:40.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.04:02:40.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.04:02:40.67#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:40.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:02:40.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:02:40.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:02:40.67#ibcon#enter wrdev, iclass 39, count 2 2006.201.04:02:40.67#ibcon#first serial, iclass 39, count 2 2006.201.04:02:40.67#ibcon#enter sib2, iclass 39, count 2 2006.201.04:02:40.67#ibcon#flushed, iclass 39, count 2 2006.201.04:02:40.67#ibcon#about to write, iclass 39, count 2 2006.201.04:02:40.67#ibcon#wrote, iclass 39, count 2 2006.201.04:02:40.67#ibcon#about to read 3, iclass 39, count 2 2006.201.04:02:40.69#ibcon#read 3, iclass 39, count 2 2006.201.04:02:40.69#ibcon#about to read 4, iclass 39, count 2 2006.201.04:02:40.69#ibcon#read 4, iclass 39, count 2 2006.201.04:02:40.69#ibcon#about to read 5, iclass 39, count 2 2006.201.04:02:40.69#ibcon#read 5, iclass 39, count 2 2006.201.04:02:40.69#ibcon#about to read 6, iclass 39, count 2 2006.201.04:02:40.69#ibcon#read 6, iclass 39, count 2 2006.201.04:02:40.69#ibcon#end of sib2, iclass 39, count 2 2006.201.04:02:40.69#ibcon#*mode == 0, iclass 39, count 2 2006.201.04:02:40.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.04:02:40.69#ibcon#[27=AT01-04\r\n] 2006.201.04:02:40.69#ibcon#*before write, iclass 39, count 2 2006.201.04:02:40.69#ibcon#enter sib2, iclass 39, count 2 2006.201.04:02:40.69#ibcon#flushed, iclass 39, count 2 2006.201.04:02:40.69#ibcon#about to write, iclass 39, count 2 2006.201.04:02:40.69#ibcon#wrote, iclass 39, count 2 2006.201.04:02:40.69#ibcon#about to read 3, iclass 39, count 2 2006.201.04:02:40.72#ibcon#read 3, iclass 39, count 2 2006.201.04:02:40.72#ibcon#about to read 4, iclass 39, count 2 2006.201.04:02:40.72#ibcon#read 4, iclass 39, count 2 2006.201.04:02:40.72#ibcon#about to read 5, iclass 39, count 2 2006.201.04:02:40.72#ibcon#read 5, iclass 39, count 2 2006.201.04:02:40.72#ibcon#about to read 6, iclass 39, count 2 2006.201.04:02:40.72#ibcon#read 6, iclass 39, count 2 2006.201.04:02:40.72#ibcon#end of sib2, iclass 39, count 2 2006.201.04:02:40.72#ibcon#*after write, iclass 39, count 2 2006.201.04:02:40.72#ibcon#*before return 0, iclass 39, count 2 2006.201.04:02:40.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:02:40.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:02:40.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.04:02:40.72#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:40.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:02:40.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:02:40.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:02:40.84#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:02:40.84#ibcon#first serial, iclass 39, count 0 2006.201.04:02:40.84#ibcon#enter sib2, iclass 39, count 0 2006.201.04:02:40.84#ibcon#flushed, iclass 39, count 0 2006.201.04:02:40.84#ibcon#about to write, iclass 39, count 0 2006.201.04:02:40.84#ibcon#wrote, iclass 39, count 0 2006.201.04:02:40.84#ibcon#about to read 3, iclass 39, count 0 2006.201.04:02:40.86#ibcon#read 3, iclass 39, count 0 2006.201.04:02:40.86#ibcon#about to read 4, iclass 39, count 0 2006.201.04:02:40.86#ibcon#read 4, iclass 39, count 0 2006.201.04:02:40.86#ibcon#about to read 5, iclass 39, count 0 2006.201.04:02:40.86#ibcon#read 5, iclass 39, count 0 2006.201.04:02:40.86#ibcon#about to read 6, iclass 39, count 0 2006.201.04:02:40.86#ibcon#read 6, iclass 39, count 0 2006.201.04:02:40.86#ibcon#end of sib2, iclass 39, count 0 2006.201.04:02:40.86#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:02:40.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:02:40.86#ibcon#[27=USB\r\n] 2006.201.04:02:40.86#ibcon#*before write, iclass 39, count 0 2006.201.04:02:40.86#ibcon#enter sib2, iclass 39, count 0 2006.201.04:02:40.86#ibcon#flushed, iclass 39, count 0 2006.201.04:02:40.86#ibcon#about to write, iclass 39, count 0 2006.201.04:02:40.86#ibcon#wrote, iclass 39, count 0 2006.201.04:02:40.86#ibcon#about to read 3, iclass 39, count 0 2006.201.04:02:40.89#ibcon#read 3, iclass 39, count 0 2006.201.04:02:40.89#ibcon#about to read 4, iclass 39, count 0 2006.201.04:02:40.89#ibcon#read 4, iclass 39, count 0 2006.201.04:02:40.89#ibcon#about to read 5, iclass 39, count 0 2006.201.04:02:40.89#ibcon#read 5, iclass 39, count 0 2006.201.04:02:40.89#ibcon#about to read 6, iclass 39, count 0 2006.201.04:02:40.89#ibcon#read 6, iclass 39, count 0 2006.201.04:02:40.89#ibcon#end of sib2, iclass 39, count 0 2006.201.04:02:40.89#ibcon#*after write, iclass 39, count 0 2006.201.04:02:40.89#ibcon#*before return 0, iclass 39, count 0 2006.201.04:02:40.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:02:40.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:02:40.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:02:40.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:02:40.89$vck44/vblo=2,634.99 2006.201.04:02:40.89#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.04:02:40.89#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.04:02:40.89#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:40.89#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:40.89#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:40.89#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:40.89#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:02:40.89#ibcon#first serial, iclass 2, count 0 2006.201.04:02:40.89#ibcon#enter sib2, iclass 2, count 0 2006.201.04:02:40.89#ibcon#flushed, iclass 2, count 0 2006.201.04:02:40.89#ibcon#about to write, iclass 2, count 0 2006.201.04:02:40.89#ibcon#wrote, iclass 2, count 0 2006.201.04:02:40.89#ibcon#about to read 3, iclass 2, count 0 2006.201.04:02:40.91#ibcon#read 3, iclass 2, count 0 2006.201.04:02:40.91#ibcon#about to read 4, iclass 2, count 0 2006.201.04:02:40.91#ibcon#read 4, iclass 2, count 0 2006.201.04:02:40.91#ibcon#about to read 5, iclass 2, count 0 2006.201.04:02:40.91#ibcon#read 5, iclass 2, count 0 2006.201.04:02:40.91#ibcon#about to read 6, iclass 2, count 0 2006.201.04:02:40.91#ibcon#read 6, iclass 2, count 0 2006.201.04:02:40.91#ibcon#end of sib2, iclass 2, count 0 2006.201.04:02:40.91#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:02:40.91#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:02:40.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:02:40.91#ibcon#*before write, iclass 2, count 0 2006.201.04:02:40.91#ibcon#enter sib2, iclass 2, count 0 2006.201.04:02:40.91#ibcon#flushed, iclass 2, count 0 2006.201.04:02:40.91#ibcon#about to write, iclass 2, count 0 2006.201.04:02:40.91#ibcon#wrote, iclass 2, count 0 2006.201.04:02:40.91#ibcon#about to read 3, iclass 2, count 0 2006.201.04:02:40.95#ibcon#read 3, iclass 2, count 0 2006.201.04:02:40.95#ibcon#about to read 4, iclass 2, count 0 2006.201.04:02:40.95#ibcon#read 4, iclass 2, count 0 2006.201.04:02:40.95#ibcon#about to read 5, iclass 2, count 0 2006.201.04:02:40.95#ibcon#read 5, iclass 2, count 0 2006.201.04:02:40.95#ibcon#about to read 6, iclass 2, count 0 2006.201.04:02:40.95#ibcon#read 6, iclass 2, count 0 2006.201.04:02:40.95#ibcon#end of sib2, iclass 2, count 0 2006.201.04:02:40.95#ibcon#*after write, iclass 2, count 0 2006.201.04:02:40.95#ibcon#*before return 0, iclass 2, count 0 2006.201.04:02:40.95#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:40.95#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:02:40.95#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:02:40.95#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:02:40.95$vck44/vb=2,5 2006.201.04:02:40.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.04:02:40.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.04:02:40.95#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:40.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:41.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:41.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:41.01#ibcon#enter wrdev, iclass 5, count 2 2006.201.04:02:41.01#ibcon#first serial, iclass 5, count 2 2006.201.04:02:41.01#ibcon#enter sib2, iclass 5, count 2 2006.201.04:02:41.01#ibcon#flushed, iclass 5, count 2 2006.201.04:02:41.01#ibcon#about to write, iclass 5, count 2 2006.201.04:02:41.01#ibcon#wrote, iclass 5, count 2 2006.201.04:02:41.01#ibcon#about to read 3, iclass 5, count 2 2006.201.04:02:41.03#ibcon#read 3, iclass 5, count 2 2006.201.04:02:41.03#ibcon#about to read 4, iclass 5, count 2 2006.201.04:02:41.03#ibcon#read 4, iclass 5, count 2 2006.201.04:02:41.03#ibcon#about to read 5, iclass 5, count 2 2006.201.04:02:41.03#ibcon#read 5, iclass 5, count 2 2006.201.04:02:41.03#ibcon#about to read 6, iclass 5, count 2 2006.201.04:02:41.03#ibcon#read 6, iclass 5, count 2 2006.201.04:02:41.03#ibcon#end of sib2, iclass 5, count 2 2006.201.04:02:41.03#ibcon#*mode == 0, iclass 5, count 2 2006.201.04:02:41.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.04:02:41.03#ibcon#[27=AT02-05\r\n] 2006.201.04:02:41.03#ibcon#*before write, iclass 5, count 2 2006.201.04:02:41.03#ibcon#enter sib2, iclass 5, count 2 2006.201.04:02:41.03#ibcon#flushed, iclass 5, count 2 2006.201.04:02:41.03#ibcon#about to write, iclass 5, count 2 2006.201.04:02:41.03#ibcon#wrote, iclass 5, count 2 2006.201.04:02:41.03#ibcon#about to read 3, iclass 5, count 2 2006.201.04:02:41.06#ibcon#read 3, iclass 5, count 2 2006.201.04:02:41.06#ibcon#about to read 4, iclass 5, count 2 2006.201.04:02:41.06#ibcon#read 4, iclass 5, count 2 2006.201.04:02:41.06#ibcon#about to read 5, iclass 5, count 2 2006.201.04:02:41.06#ibcon#read 5, iclass 5, count 2 2006.201.04:02:41.06#ibcon#about to read 6, iclass 5, count 2 2006.201.04:02:41.06#ibcon#read 6, iclass 5, count 2 2006.201.04:02:41.06#ibcon#end of sib2, iclass 5, count 2 2006.201.04:02:41.06#ibcon#*after write, iclass 5, count 2 2006.201.04:02:41.06#ibcon#*before return 0, iclass 5, count 2 2006.201.04:02:41.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:41.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:02:41.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.04:02:41.06#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:41.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:41.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:41.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:41.18#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:02:41.18#ibcon#first serial, iclass 5, count 0 2006.201.04:02:41.18#ibcon#enter sib2, iclass 5, count 0 2006.201.04:02:41.18#ibcon#flushed, iclass 5, count 0 2006.201.04:02:41.18#ibcon#about to write, iclass 5, count 0 2006.201.04:02:41.18#ibcon#wrote, iclass 5, count 0 2006.201.04:02:41.18#ibcon#about to read 3, iclass 5, count 0 2006.201.04:02:41.21#ibcon#read 3, iclass 5, count 0 2006.201.04:02:41.21#ibcon#about to read 4, iclass 5, count 0 2006.201.04:02:41.21#ibcon#read 4, iclass 5, count 0 2006.201.04:02:41.21#ibcon#about to read 5, iclass 5, count 0 2006.201.04:02:41.21#ibcon#read 5, iclass 5, count 0 2006.201.04:02:41.21#ibcon#about to read 6, iclass 5, count 0 2006.201.04:02:41.21#ibcon#read 6, iclass 5, count 0 2006.201.04:02:41.21#ibcon#end of sib2, iclass 5, count 0 2006.201.04:02:41.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:02:41.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:02:41.21#ibcon#[27=USB\r\n] 2006.201.04:02:41.21#ibcon#*before write, iclass 5, count 0 2006.201.04:02:41.21#ibcon#enter sib2, iclass 5, count 0 2006.201.04:02:41.21#ibcon#flushed, iclass 5, count 0 2006.201.04:02:41.21#ibcon#about to write, iclass 5, count 0 2006.201.04:02:41.21#ibcon#wrote, iclass 5, count 0 2006.201.04:02:41.21#ibcon#about to read 3, iclass 5, count 0 2006.201.04:02:41.24#ibcon#read 3, iclass 5, count 0 2006.201.04:02:41.24#ibcon#about to read 4, iclass 5, count 0 2006.201.04:02:41.24#ibcon#read 4, iclass 5, count 0 2006.201.04:02:41.24#ibcon#about to read 5, iclass 5, count 0 2006.201.04:02:41.24#ibcon#read 5, iclass 5, count 0 2006.201.04:02:41.24#ibcon#about to read 6, iclass 5, count 0 2006.201.04:02:41.24#ibcon#read 6, iclass 5, count 0 2006.201.04:02:41.24#ibcon#end of sib2, iclass 5, count 0 2006.201.04:02:41.24#ibcon#*after write, iclass 5, count 0 2006.201.04:02:41.24#ibcon#*before return 0, iclass 5, count 0 2006.201.04:02:41.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:41.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:02:41.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:02:41.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:02:41.24$vck44/vblo=3,649.99 2006.201.04:02:41.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.04:02:41.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.04:02:41.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:41.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:41.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:41.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:41.24#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:02:41.24#ibcon#first serial, iclass 7, count 0 2006.201.04:02:41.24#ibcon#enter sib2, iclass 7, count 0 2006.201.04:02:41.24#ibcon#flushed, iclass 7, count 0 2006.201.04:02:41.24#ibcon#about to write, iclass 7, count 0 2006.201.04:02:41.24#ibcon#wrote, iclass 7, count 0 2006.201.04:02:41.24#ibcon#about to read 3, iclass 7, count 0 2006.201.04:02:41.26#ibcon#read 3, iclass 7, count 0 2006.201.04:02:41.26#ibcon#about to read 4, iclass 7, count 0 2006.201.04:02:41.26#ibcon#read 4, iclass 7, count 0 2006.201.04:02:41.26#ibcon#about to read 5, iclass 7, count 0 2006.201.04:02:41.26#ibcon#read 5, iclass 7, count 0 2006.201.04:02:41.26#ibcon#about to read 6, iclass 7, count 0 2006.201.04:02:41.26#ibcon#read 6, iclass 7, count 0 2006.201.04:02:41.26#ibcon#end of sib2, iclass 7, count 0 2006.201.04:02:41.26#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:02:41.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:02:41.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:02:41.26#ibcon#*before write, iclass 7, count 0 2006.201.04:02:41.26#ibcon#enter sib2, iclass 7, count 0 2006.201.04:02:41.26#ibcon#flushed, iclass 7, count 0 2006.201.04:02:41.26#ibcon#about to write, iclass 7, count 0 2006.201.04:02:41.26#ibcon#wrote, iclass 7, count 0 2006.201.04:02:41.26#ibcon#about to read 3, iclass 7, count 0 2006.201.04:02:41.30#ibcon#read 3, iclass 7, count 0 2006.201.04:02:41.30#ibcon#about to read 4, iclass 7, count 0 2006.201.04:02:41.30#ibcon#read 4, iclass 7, count 0 2006.201.04:02:41.30#ibcon#about to read 5, iclass 7, count 0 2006.201.04:02:41.30#ibcon#read 5, iclass 7, count 0 2006.201.04:02:41.30#ibcon#about to read 6, iclass 7, count 0 2006.201.04:02:41.30#ibcon#read 6, iclass 7, count 0 2006.201.04:02:41.30#ibcon#end of sib2, iclass 7, count 0 2006.201.04:02:41.30#ibcon#*after write, iclass 7, count 0 2006.201.04:02:41.30#ibcon#*before return 0, iclass 7, count 0 2006.201.04:02:41.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:41.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:02:41.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:02:41.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:02:41.30$vck44/vb=3,4 2006.201.04:02:41.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.04:02:41.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.04:02:41.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:41.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:41.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:41.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:41.36#ibcon#enter wrdev, iclass 11, count 2 2006.201.04:02:41.36#ibcon#first serial, iclass 11, count 2 2006.201.04:02:41.36#ibcon#enter sib2, iclass 11, count 2 2006.201.04:02:41.36#ibcon#flushed, iclass 11, count 2 2006.201.04:02:41.36#ibcon#about to write, iclass 11, count 2 2006.201.04:02:41.36#ibcon#wrote, iclass 11, count 2 2006.201.04:02:41.36#ibcon#about to read 3, iclass 11, count 2 2006.201.04:02:41.38#ibcon#read 3, iclass 11, count 2 2006.201.04:02:41.38#ibcon#about to read 4, iclass 11, count 2 2006.201.04:02:41.38#ibcon#read 4, iclass 11, count 2 2006.201.04:02:41.38#ibcon#about to read 5, iclass 11, count 2 2006.201.04:02:41.38#ibcon#read 5, iclass 11, count 2 2006.201.04:02:41.38#ibcon#about to read 6, iclass 11, count 2 2006.201.04:02:41.38#ibcon#read 6, iclass 11, count 2 2006.201.04:02:41.38#ibcon#end of sib2, iclass 11, count 2 2006.201.04:02:41.38#ibcon#*mode == 0, iclass 11, count 2 2006.201.04:02:41.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.04:02:41.38#ibcon#[27=AT03-04\r\n] 2006.201.04:02:41.38#ibcon#*before write, iclass 11, count 2 2006.201.04:02:41.38#ibcon#enter sib2, iclass 11, count 2 2006.201.04:02:41.38#ibcon#flushed, iclass 11, count 2 2006.201.04:02:41.38#ibcon#about to write, iclass 11, count 2 2006.201.04:02:41.38#ibcon#wrote, iclass 11, count 2 2006.201.04:02:41.38#ibcon#about to read 3, iclass 11, count 2 2006.201.04:02:41.41#ibcon#read 3, iclass 11, count 2 2006.201.04:02:41.41#ibcon#about to read 4, iclass 11, count 2 2006.201.04:02:41.41#ibcon#read 4, iclass 11, count 2 2006.201.04:02:41.41#ibcon#about to read 5, iclass 11, count 2 2006.201.04:02:41.41#ibcon#read 5, iclass 11, count 2 2006.201.04:02:41.41#ibcon#about to read 6, iclass 11, count 2 2006.201.04:02:41.41#ibcon#read 6, iclass 11, count 2 2006.201.04:02:41.41#ibcon#end of sib2, iclass 11, count 2 2006.201.04:02:41.41#ibcon#*after write, iclass 11, count 2 2006.201.04:02:41.41#ibcon#*before return 0, iclass 11, count 2 2006.201.04:02:41.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:41.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:02:41.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.04:02:41.41#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:41.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:41.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:41.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:41.53#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:02:41.53#ibcon#first serial, iclass 11, count 0 2006.201.04:02:41.53#ibcon#enter sib2, iclass 11, count 0 2006.201.04:02:41.53#ibcon#flushed, iclass 11, count 0 2006.201.04:02:41.53#ibcon#about to write, iclass 11, count 0 2006.201.04:02:41.53#ibcon#wrote, iclass 11, count 0 2006.201.04:02:41.53#ibcon#about to read 3, iclass 11, count 0 2006.201.04:02:41.55#ibcon#read 3, iclass 11, count 0 2006.201.04:02:41.55#ibcon#about to read 4, iclass 11, count 0 2006.201.04:02:41.55#ibcon#read 4, iclass 11, count 0 2006.201.04:02:41.55#ibcon#about to read 5, iclass 11, count 0 2006.201.04:02:41.55#ibcon#read 5, iclass 11, count 0 2006.201.04:02:41.55#ibcon#about to read 6, iclass 11, count 0 2006.201.04:02:41.55#ibcon#read 6, iclass 11, count 0 2006.201.04:02:41.55#ibcon#end of sib2, iclass 11, count 0 2006.201.04:02:41.55#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:02:41.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:02:41.55#ibcon#[27=USB\r\n] 2006.201.04:02:41.55#ibcon#*before write, iclass 11, count 0 2006.201.04:02:41.55#ibcon#enter sib2, iclass 11, count 0 2006.201.04:02:41.55#ibcon#flushed, iclass 11, count 0 2006.201.04:02:41.55#ibcon#about to write, iclass 11, count 0 2006.201.04:02:41.55#ibcon#wrote, iclass 11, count 0 2006.201.04:02:41.55#ibcon#about to read 3, iclass 11, count 0 2006.201.04:02:41.58#ibcon#read 3, iclass 11, count 0 2006.201.04:02:41.58#ibcon#about to read 4, iclass 11, count 0 2006.201.04:02:41.58#ibcon#read 4, iclass 11, count 0 2006.201.04:02:41.58#ibcon#about to read 5, iclass 11, count 0 2006.201.04:02:41.58#ibcon#read 5, iclass 11, count 0 2006.201.04:02:41.58#ibcon#about to read 6, iclass 11, count 0 2006.201.04:02:41.58#ibcon#read 6, iclass 11, count 0 2006.201.04:02:41.58#ibcon#end of sib2, iclass 11, count 0 2006.201.04:02:41.58#ibcon#*after write, iclass 11, count 0 2006.201.04:02:41.58#ibcon#*before return 0, iclass 11, count 0 2006.201.04:02:41.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:41.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:02:41.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:02:41.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:02:41.58$vck44/vblo=4,679.99 2006.201.04:02:41.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.04:02:41.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.04:02:41.58#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:41.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:41.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:41.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:41.58#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:02:41.58#ibcon#first serial, iclass 13, count 0 2006.201.04:02:41.58#ibcon#enter sib2, iclass 13, count 0 2006.201.04:02:41.58#ibcon#flushed, iclass 13, count 0 2006.201.04:02:41.58#ibcon#about to write, iclass 13, count 0 2006.201.04:02:41.58#ibcon#wrote, iclass 13, count 0 2006.201.04:02:41.58#ibcon#about to read 3, iclass 13, count 0 2006.201.04:02:41.60#ibcon#read 3, iclass 13, count 0 2006.201.04:02:41.60#ibcon#about to read 4, iclass 13, count 0 2006.201.04:02:41.60#ibcon#read 4, iclass 13, count 0 2006.201.04:02:41.60#ibcon#about to read 5, iclass 13, count 0 2006.201.04:02:41.60#ibcon#read 5, iclass 13, count 0 2006.201.04:02:41.60#ibcon#about to read 6, iclass 13, count 0 2006.201.04:02:41.60#ibcon#read 6, iclass 13, count 0 2006.201.04:02:41.60#ibcon#end of sib2, iclass 13, count 0 2006.201.04:02:41.60#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:02:41.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:02:41.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:02:41.60#ibcon#*before write, iclass 13, count 0 2006.201.04:02:41.60#ibcon#enter sib2, iclass 13, count 0 2006.201.04:02:41.60#ibcon#flushed, iclass 13, count 0 2006.201.04:02:41.60#ibcon#about to write, iclass 13, count 0 2006.201.04:02:41.60#ibcon#wrote, iclass 13, count 0 2006.201.04:02:41.60#ibcon#about to read 3, iclass 13, count 0 2006.201.04:02:41.64#ibcon#read 3, iclass 13, count 0 2006.201.04:02:41.64#ibcon#about to read 4, iclass 13, count 0 2006.201.04:02:41.64#ibcon#read 4, iclass 13, count 0 2006.201.04:02:41.64#ibcon#about to read 5, iclass 13, count 0 2006.201.04:02:41.64#ibcon#read 5, iclass 13, count 0 2006.201.04:02:41.64#ibcon#about to read 6, iclass 13, count 0 2006.201.04:02:41.64#ibcon#read 6, iclass 13, count 0 2006.201.04:02:41.64#ibcon#end of sib2, iclass 13, count 0 2006.201.04:02:41.64#ibcon#*after write, iclass 13, count 0 2006.201.04:02:41.64#ibcon#*before return 0, iclass 13, count 0 2006.201.04:02:41.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:41.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:02:41.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:02:41.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:02:41.64$vck44/vb=4,5 2006.201.04:02:41.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.04:02:41.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.04:02:41.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:41.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:41.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:41.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:41.70#ibcon#enter wrdev, iclass 15, count 2 2006.201.04:02:41.70#ibcon#first serial, iclass 15, count 2 2006.201.04:02:41.70#ibcon#enter sib2, iclass 15, count 2 2006.201.04:02:41.70#ibcon#flushed, iclass 15, count 2 2006.201.04:02:41.70#ibcon#about to write, iclass 15, count 2 2006.201.04:02:41.70#ibcon#wrote, iclass 15, count 2 2006.201.04:02:41.70#ibcon#about to read 3, iclass 15, count 2 2006.201.04:02:41.72#ibcon#read 3, iclass 15, count 2 2006.201.04:02:41.72#ibcon#about to read 4, iclass 15, count 2 2006.201.04:02:41.72#ibcon#read 4, iclass 15, count 2 2006.201.04:02:41.72#ibcon#about to read 5, iclass 15, count 2 2006.201.04:02:41.72#ibcon#read 5, iclass 15, count 2 2006.201.04:02:41.72#ibcon#about to read 6, iclass 15, count 2 2006.201.04:02:41.72#ibcon#read 6, iclass 15, count 2 2006.201.04:02:41.72#ibcon#end of sib2, iclass 15, count 2 2006.201.04:02:41.72#ibcon#*mode == 0, iclass 15, count 2 2006.201.04:02:41.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.04:02:41.72#ibcon#[27=AT04-05\r\n] 2006.201.04:02:41.72#ibcon#*before write, iclass 15, count 2 2006.201.04:02:41.72#ibcon#enter sib2, iclass 15, count 2 2006.201.04:02:41.72#ibcon#flushed, iclass 15, count 2 2006.201.04:02:41.72#ibcon#about to write, iclass 15, count 2 2006.201.04:02:41.72#ibcon#wrote, iclass 15, count 2 2006.201.04:02:41.72#ibcon#about to read 3, iclass 15, count 2 2006.201.04:02:41.75#ibcon#read 3, iclass 15, count 2 2006.201.04:02:41.75#ibcon#about to read 4, iclass 15, count 2 2006.201.04:02:41.75#ibcon#read 4, iclass 15, count 2 2006.201.04:02:41.75#ibcon#about to read 5, iclass 15, count 2 2006.201.04:02:41.75#ibcon#read 5, iclass 15, count 2 2006.201.04:02:41.75#ibcon#about to read 6, iclass 15, count 2 2006.201.04:02:41.75#ibcon#read 6, iclass 15, count 2 2006.201.04:02:41.75#ibcon#end of sib2, iclass 15, count 2 2006.201.04:02:41.75#ibcon#*after write, iclass 15, count 2 2006.201.04:02:41.75#ibcon#*before return 0, iclass 15, count 2 2006.201.04:02:41.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:41.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:02:41.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.04:02:41.75#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:41.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:41.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:41.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:41.87#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:02:41.87#ibcon#first serial, iclass 15, count 0 2006.201.04:02:41.87#ibcon#enter sib2, iclass 15, count 0 2006.201.04:02:41.87#ibcon#flushed, iclass 15, count 0 2006.201.04:02:41.87#ibcon#about to write, iclass 15, count 0 2006.201.04:02:41.87#ibcon#wrote, iclass 15, count 0 2006.201.04:02:41.87#ibcon#about to read 3, iclass 15, count 0 2006.201.04:02:41.89#ibcon#read 3, iclass 15, count 0 2006.201.04:02:41.89#ibcon#about to read 4, iclass 15, count 0 2006.201.04:02:41.89#ibcon#read 4, iclass 15, count 0 2006.201.04:02:41.89#ibcon#about to read 5, iclass 15, count 0 2006.201.04:02:41.89#ibcon#read 5, iclass 15, count 0 2006.201.04:02:41.89#ibcon#about to read 6, iclass 15, count 0 2006.201.04:02:41.89#ibcon#read 6, iclass 15, count 0 2006.201.04:02:41.89#ibcon#end of sib2, iclass 15, count 0 2006.201.04:02:41.89#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:02:41.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:02:41.89#ibcon#[27=USB\r\n] 2006.201.04:02:41.89#ibcon#*before write, iclass 15, count 0 2006.201.04:02:41.89#ibcon#enter sib2, iclass 15, count 0 2006.201.04:02:41.89#ibcon#flushed, iclass 15, count 0 2006.201.04:02:41.89#ibcon#about to write, iclass 15, count 0 2006.201.04:02:41.89#ibcon#wrote, iclass 15, count 0 2006.201.04:02:41.89#ibcon#about to read 3, iclass 15, count 0 2006.201.04:02:41.92#ibcon#read 3, iclass 15, count 0 2006.201.04:02:41.92#ibcon#about to read 4, iclass 15, count 0 2006.201.04:02:41.92#ibcon#read 4, iclass 15, count 0 2006.201.04:02:41.92#ibcon#about to read 5, iclass 15, count 0 2006.201.04:02:41.92#ibcon#read 5, iclass 15, count 0 2006.201.04:02:41.92#ibcon#about to read 6, iclass 15, count 0 2006.201.04:02:41.92#ibcon#read 6, iclass 15, count 0 2006.201.04:02:41.92#ibcon#end of sib2, iclass 15, count 0 2006.201.04:02:41.92#ibcon#*after write, iclass 15, count 0 2006.201.04:02:41.92#ibcon#*before return 0, iclass 15, count 0 2006.201.04:02:41.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:41.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:02:41.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:02:41.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:02:41.92$vck44/vblo=5,709.99 2006.201.04:02:41.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.04:02:41.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.04:02:41.92#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:41.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:41.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:41.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:41.92#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:02:41.92#ibcon#first serial, iclass 17, count 0 2006.201.04:02:41.92#ibcon#enter sib2, iclass 17, count 0 2006.201.04:02:41.92#ibcon#flushed, iclass 17, count 0 2006.201.04:02:41.92#ibcon#about to write, iclass 17, count 0 2006.201.04:02:41.92#ibcon#wrote, iclass 17, count 0 2006.201.04:02:41.92#ibcon#about to read 3, iclass 17, count 0 2006.201.04:02:41.94#ibcon#read 3, iclass 17, count 0 2006.201.04:02:41.94#ibcon#about to read 4, iclass 17, count 0 2006.201.04:02:41.94#ibcon#read 4, iclass 17, count 0 2006.201.04:02:41.94#ibcon#about to read 5, iclass 17, count 0 2006.201.04:02:41.94#ibcon#read 5, iclass 17, count 0 2006.201.04:02:41.94#ibcon#about to read 6, iclass 17, count 0 2006.201.04:02:41.94#ibcon#read 6, iclass 17, count 0 2006.201.04:02:41.94#ibcon#end of sib2, iclass 17, count 0 2006.201.04:02:41.94#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:02:41.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:02:41.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:02:41.94#ibcon#*before write, iclass 17, count 0 2006.201.04:02:41.94#ibcon#enter sib2, iclass 17, count 0 2006.201.04:02:41.94#ibcon#flushed, iclass 17, count 0 2006.201.04:02:41.94#ibcon#about to write, iclass 17, count 0 2006.201.04:02:41.94#ibcon#wrote, iclass 17, count 0 2006.201.04:02:41.94#ibcon#about to read 3, iclass 17, count 0 2006.201.04:02:41.99#ibcon#read 3, iclass 17, count 0 2006.201.04:02:41.99#ibcon#about to read 4, iclass 17, count 0 2006.201.04:02:41.99#ibcon#read 4, iclass 17, count 0 2006.201.04:02:41.99#ibcon#about to read 5, iclass 17, count 0 2006.201.04:02:41.99#ibcon#read 5, iclass 17, count 0 2006.201.04:02:41.99#ibcon#about to read 6, iclass 17, count 0 2006.201.04:02:41.99#ibcon#read 6, iclass 17, count 0 2006.201.04:02:41.99#ibcon#end of sib2, iclass 17, count 0 2006.201.04:02:41.99#ibcon#*after write, iclass 17, count 0 2006.201.04:02:41.99#ibcon#*before return 0, iclass 17, count 0 2006.201.04:02:41.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:41.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:02:41.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:02:41.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:02:41.99$vck44/vb=5,4 2006.201.04:02:41.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.04:02:41.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.04:02:41.99#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:41.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:42.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:42.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:42.04#ibcon#enter wrdev, iclass 19, count 2 2006.201.04:02:42.04#ibcon#first serial, iclass 19, count 2 2006.201.04:02:42.04#ibcon#enter sib2, iclass 19, count 2 2006.201.04:02:42.04#ibcon#flushed, iclass 19, count 2 2006.201.04:02:42.04#ibcon#about to write, iclass 19, count 2 2006.201.04:02:42.04#ibcon#wrote, iclass 19, count 2 2006.201.04:02:42.04#ibcon#about to read 3, iclass 19, count 2 2006.201.04:02:42.06#ibcon#read 3, iclass 19, count 2 2006.201.04:02:42.06#ibcon#about to read 4, iclass 19, count 2 2006.201.04:02:42.06#ibcon#read 4, iclass 19, count 2 2006.201.04:02:42.06#ibcon#about to read 5, iclass 19, count 2 2006.201.04:02:42.06#ibcon#read 5, iclass 19, count 2 2006.201.04:02:42.06#ibcon#about to read 6, iclass 19, count 2 2006.201.04:02:42.06#ibcon#read 6, iclass 19, count 2 2006.201.04:02:42.06#ibcon#end of sib2, iclass 19, count 2 2006.201.04:02:42.06#ibcon#*mode == 0, iclass 19, count 2 2006.201.04:02:42.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.04:02:42.06#ibcon#[27=AT05-04\r\n] 2006.201.04:02:42.06#ibcon#*before write, iclass 19, count 2 2006.201.04:02:42.06#ibcon#enter sib2, iclass 19, count 2 2006.201.04:02:42.06#ibcon#flushed, iclass 19, count 2 2006.201.04:02:42.06#ibcon#about to write, iclass 19, count 2 2006.201.04:02:42.06#ibcon#wrote, iclass 19, count 2 2006.201.04:02:42.06#ibcon#about to read 3, iclass 19, count 2 2006.201.04:02:42.09#ibcon#read 3, iclass 19, count 2 2006.201.04:02:42.09#ibcon#about to read 4, iclass 19, count 2 2006.201.04:02:42.09#ibcon#read 4, iclass 19, count 2 2006.201.04:02:42.09#ibcon#about to read 5, iclass 19, count 2 2006.201.04:02:42.09#ibcon#read 5, iclass 19, count 2 2006.201.04:02:42.09#ibcon#about to read 6, iclass 19, count 2 2006.201.04:02:42.09#ibcon#read 6, iclass 19, count 2 2006.201.04:02:42.09#ibcon#end of sib2, iclass 19, count 2 2006.201.04:02:42.09#ibcon#*after write, iclass 19, count 2 2006.201.04:02:42.09#ibcon#*before return 0, iclass 19, count 2 2006.201.04:02:42.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:42.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:02:42.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.04:02:42.09#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:42.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:42.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:42.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:42.21#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:02:42.21#ibcon#first serial, iclass 19, count 0 2006.201.04:02:42.21#ibcon#enter sib2, iclass 19, count 0 2006.201.04:02:42.21#ibcon#flushed, iclass 19, count 0 2006.201.04:02:42.21#ibcon#about to write, iclass 19, count 0 2006.201.04:02:42.21#ibcon#wrote, iclass 19, count 0 2006.201.04:02:42.21#ibcon#about to read 3, iclass 19, count 0 2006.201.04:02:42.23#ibcon#read 3, iclass 19, count 0 2006.201.04:02:42.23#ibcon#about to read 4, iclass 19, count 0 2006.201.04:02:42.23#ibcon#read 4, iclass 19, count 0 2006.201.04:02:42.23#ibcon#about to read 5, iclass 19, count 0 2006.201.04:02:42.23#ibcon#read 5, iclass 19, count 0 2006.201.04:02:42.23#ibcon#about to read 6, iclass 19, count 0 2006.201.04:02:42.23#ibcon#read 6, iclass 19, count 0 2006.201.04:02:42.23#ibcon#end of sib2, iclass 19, count 0 2006.201.04:02:42.23#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:02:42.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:02:42.23#ibcon#[27=USB\r\n] 2006.201.04:02:42.23#ibcon#*before write, iclass 19, count 0 2006.201.04:02:42.23#ibcon#enter sib2, iclass 19, count 0 2006.201.04:02:42.23#ibcon#flushed, iclass 19, count 0 2006.201.04:02:42.23#ibcon#about to write, iclass 19, count 0 2006.201.04:02:42.23#ibcon#wrote, iclass 19, count 0 2006.201.04:02:42.23#ibcon#about to read 3, iclass 19, count 0 2006.201.04:02:42.26#ibcon#read 3, iclass 19, count 0 2006.201.04:02:42.26#ibcon#about to read 4, iclass 19, count 0 2006.201.04:02:42.26#ibcon#read 4, iclass 19, count 0 2006.201.04:02:42.26#ibcon#about to read 5, iclass 19, count 0 2006.201.04:02:42.26#ibcon#read 5, iclass 19, count 0 2006.201.04:02:42.26#ibcon#about to read 6, iclass 19, count 0 2006.201.04:02:42.26#ibcon#read 6, iclass 19, count 0 2006.201.04:02:42.26#ibcon#end of sib2, iclass 19, count 0 2006.201.04:02:42.26#ibcon#*after write, iclass 19, count 0 2006.201.04:02:42.26#ibcon#*before return 0, iclass 19, count 0 2006.201.04:02:42.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:42.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:02:42.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:02:42.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:02:42.26$vck44/vblo=6,719.99 2006.201.04:02:42.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.04:02:42.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.04:02:42.26#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:42.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:42.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:42.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:42.26#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:02:42.26#ibcon#first serial, iclass 21, count 0 2006.201.04:02:42.26#ibcon#enter sib2, iclass 21, count 0 2006.201.04:02:42.26#ibcon#flushed, iclass 21, count 0 2006.201.04:02:42.26#ibcon#about to write, iclass 21, count 0 2006.201.04:02:42.26#ibcon#wrote, iclass 21, count 0 2006.201.04:02:42.26#ibcon#about to read 3, iclass 21, count 0 2006.201.04:02:42.28#ibcon#read 3, iclass 21, count 0 2006.201.04:02:42.28#ibcon#about to read 4, iclass 21, count 0 2006.201.04:02:42.28#ibcon#read 4, iclass 21, count 0 2006.201.04:02:42.28#ibcon#about to read 5, iclass 21, count 0 2006.201.04:02:42.28#ibcon#read 5, iclass 21, count 0 2006.201.04:02:42.28#ibcon#about to read 6, iclass 21, count 0 2006.201.04:02:42.28#ibcon#read 6, iclass 21, count 0 2006.201.04:02:42.28#ibcon#end of sib2, iclass 21, count 0 2006.201.04:02:42.28#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:02:42.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:02:42.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:02:42.28#ibcon#*before write, iclass 21, count 0 2006.201.04:02:42.28#ibcon#enter sib2, iclass 21, count 0 2006.201.04:02:42.28#ibcon#flushed, iclass 21, count 0 2006.201.04:02:42.28#ibcon#about to write, iclass 21, count 0 2006.201.04:02:42.28#ibcon#wrote, iclass 21, count 0 2006.201.04:02:42.28#ibcon#about to read 3, iclass 21, count 0 2006.201.04:02:42.32#ibcon#read 3, iclass 21, count 0 2006.201.04:02:42.32#ibcon#about to read 4, iclass 21, count 0 2006.201.04:02:42.32#ibcon#read 4, iclass 21, count 0 2006.201.04:02:42.32#ibcon#about to read 5, iclass 21, count 0 2006.201.04:02:42.32#ibcon#read 5, iclass 21, count 0 2006.201.04:02:42.32#ibcon#about to read 6, iclass 21, count 0 2006.201.04:02:42.32#ibcon#read 6, iclass 21, count 0 2006.201.04:02:42.32#ibcon#end of sib2, iclass 21, count 0 2006.201.04:02:42.32#ibcon#*after write, iclass 21, count 0 2006.201.04:02:42.32#ibcon#*before return 0, iclass 21, count 0 2006.201.04:02:42.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:42.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:02:42.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:02:42.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:02:42.32$vck44/vb=6,4 2006.201.04:02:42.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.04:02:42.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.04:02:42.32#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:42.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:42.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:42.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:42.38#ibcon#enter wrdev, iclass 23, count 2 2006.201.04:02:42.38#ibcon#first serial, iclass 23, count 2 2006.201.04:02:42.38#ibcon#enter sib2, iclass 23, count 2 2006.201.04:02:42.38#ibcon#flushed, iclass 23, count 2 2006.201.04:02:42.38#ibcon#about to write, iclass 23, count 2 2006.201.04:02:42.38#ibcon#wrote, iclass 23, count 2 2006.201.04:02:42.38#ibcon#about to read 3, iclass 23, count 2 2006.201.04:02:42.40#ibcon#read 3, iclass 23, count 2 2006.201.04:02:42.40#ibcon#about to read 4, iclass 23, count 2 2006.201.04:02:42.40#ibcon#read 4, iclass 23, count 2 2006.201.04:02:42.40#ibcon#about to read 5, iclass 23, count 2 2006.201.04:02:42.40#ibcon#read 5, iclass 23, count 2 2006.201.04:02:42.40#ibcon#about to read 6, iclass 23, count 2 2006.201.04:02:42.40#ibcon#read 6, iclass 23, count 2 2006.201.04:02:42.40#ibcon#end of sib2, iclass 23, count 2 2006.201.04:02:42.40#ibcon#*mode == 0, iclass 23, count 2 2006.201.04:02:42.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.04:02:42.40#ibcon#[27=AT06-04\r\n] 2006.201.04:02:42.40#ibcon#*before write, iclass 23, count 2 2006.201.04:02:42.40#ibcon#enter sib2, iclass 23, count 2 2006.201.04:02:42.40#ibcon#flushed, iclass 23, count 2 2006.201.04:02:42.40#ibcon#about to write, iclass 23, count 2 2006.201.04:02:42.40#ibcon#wrote, iclass 23, count 2 2006.201.04:02:42.40#ibcon#about to read 3, iclass 23, count 2 2006.201.04:02:42.43#ibcon#read 3, iclass 23, count 2 2006.201.04:02:42.43#ibcon#about to read 4, iclass 23, count 2 2006.201.04:02:42.43#ibcon#read 4, iclass 23, count 2 2006.201.04:02:42.43#ibcon#about to read 5, iclass 23, count 2 2006.201.04:02:42.43#ibcon#read 5, iclass 23, count 2 2006.201.04:02:42.43#ibcon#about to read 6, iclass 23, count 2 2006.201.04:02:42.43#ibcon#read 6, iclass 23, count 2 2006.201.04:02:42.43#ibcon#end of sib2, iclass 23, count 2 2006.201.04:02:42.43#ibcon#*after write, iclass 23, count 2 2006.201.04:02:42.43#ibcon#*before return 0, iclass 23, count 2 2006.201.04:02:42.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:42.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:02:42.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.04:02:42.43#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:42.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:42.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:42.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:42.55#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:02:42.55#ibcon#first serial, iclass 23, count 0 2006.201.04:02:42.55#ibcon#enter sib2, iclass 23, count 0 2006.201.04:02:42.55#ibcon#flushed, iclass 23, count 0 2006.201.04:02:42.55#ibcon#about to write, iclass 23, count 0 2006.201.04:02:42.55#ibcon#wrote, iclass 23, count 0 2006.201.04:02:42.55#ibcon#about to read 3, iclass 23, count 0 2006.201.04:02:42.57#ibcon#read 3, iclass 23, count 0 2006.201.04:02:42.57#ibcon#about to read 4, iclass 23, count 0 2006.201.04:02:42.57#ibcon#read 4, iclass 23, count 0 2006.201.04:02:42.57#ibcon#about to read 5, iclass 23, count 0 2006.201.04:02:42.57#ibcon#read 5, iclass 23, count 0 2006.201.04:02:42.57#ibcon#about to read 6, iclass 23, count 0 2006.201.04:02:42.57#ibcon#read 6, iclass 23, count 0 2006.201.04:02:42.57#ibcon#end of sib2, iclass 23, count 0 2006.201.04:02:42.57#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:02:42.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:02:42.57#ibcon#[27=USB\r\n] 2006.201.04:02:42.57#ibcon#*before write, iclass 23, count 0 2006.201.04:02:42.57#ibcon#enter sib2, iclass 23, count 0 2006.201.04:02:42.57#ibcon#flushed, iclass 23, count 0 2006.201.04:02:42.57#ibcon#about to write, iclass 23, count 0 2006.201.04:02:42.57#ibcon#wrote, iclass 23, count 0 2006.201.04:02:42.57#ibcon#about to read 3, iclass 23, count 0 2006.201.04:02:42.60#ibcon#read 3, iclass 23, count 0 2006.201.04:02:42.60#ibcon#about to read 4, iclass 23, count 0 2006.201.04:02:42.60#ibcon#read 4, iclass 23, count 0 2006.201.04:02:42.60#ibcon#about to read 5, iclass 23, count 0 2006.201.04:02:42.60#ibcon#read 5, iclass 23, count 0 2006.201.04:02:42.60#ibcon#about to read 6, iclass 23, count 0 2006.201.04:02:42.60#ibcon#read 6, iclass 23, count 0 2006.201.04:02:42.60#ibcon#end of sib2, iclass 23, count 0 2006.201.04:02:42.60#ibcon#*after write, iclass 23, count 0 2006.201.04:02:42.60#ibcon#*before return 0, iclass 23, count 0 2006.201.04:02:42.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:42.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:02:42.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:02:42.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:02:42.60$vck44/vblo=7,734.99 2006.201.04:02:42.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.04:02:42.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.04:02:42.60#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:42.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:42.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:42.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:42.60#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:02:42.60#ibcon#first serial, iclass 25, count 0 2006.201.04:02:42.60#ibcon#enter sib2, iclass 25, count 0 2006.201.04:02:42.60#ibcon#flushed, iclass 25, count 0 2006.201.04:02:42.60#ibcon#about to write, iclass 25, count 0 2006.201.04:02:42.60#ibcon#wrote, iclass 25, count 0 2006.201.04:02:42.60#ibcon#about to read 3, iclass 25, count 0 2006.201.04:02:42.62#ibcon#read 3, iclass 25, count 0 2006.201.04:02:42.62#ibcon#about to read 4, iclass 25, count 0 2006.201.04:02:42.62#ibcon#read 4, iclass 25, count 0 2006.201.04:02:42.62#ibcon#about to read 5, iclass 25, count 0 2006.201.04:02:42.62#ibcon#read 5, iclass 25, count 0 2006.201.04:02:42.62#ibcon#about to read 6, iclass 25, count 0 2006.201.04:02:42.62#ibcon#read 6, iclass 25, count 0 2006.201.04:02:42.62#ibcon#end of sib2, iclass 25, count 0 2006.201.04:02:42.62#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:02:42.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:02:42.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:02:42.62#ibcon#*before write, iclass 25, count 0 2006.201.04:02:42.62#ibcon#enter sib2, iclass 25, count 0 2006.201.04:02:42.62#ibcon#flushed, iclass 25, count 0 2006.201.04:02:42.62#ibcon#about to write, iclass 25, count 0 2006.201.04:02:42.62#ibcon#wrote, iclass 25, count 0 2006.201.04:02:42.62#ibcon#about to read 3, iclass 25, count 0 2006.201.04:02:42.66#ibcon#read 3, iclass 25, count 0 2006.201.04:02:42.66#ibcon#about to read 4, iclass 25, count 0 2006.201.04:02:42.66#ibcon#read 4, iclass 25, count 0 2006.201.04:02:42.66#ibcon#about to read 5, iclass 25, count 0 2006.201.04:02:42.66#ibcon#read 5, iclass 25, count 0 2006.201.04:02:42.66#ibcon#about to read 6, iclass 25, count 0 2006.201.04:02:42.66#ibcon#read 6, iclass 25, count 0 2006.201.04:02:42.66#ibcon#end of sib2, iclass 25, count 0 2006.201.04:02:42.66#ibcon#*after write, iclass 25, count 0 2006.201.04:02:42.66#ibcon#*before return 0, iclass 25, count 0 2006.201.04:02:42.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:42.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:02:42.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:02:42.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:02:42.66$vck44/vb=7,4 2006.201.04:02:42.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.04:02:42.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.04:02:42.66#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:42.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:42.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:42.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:42.72#ibcon#enter wrdev, iclass 27, count 2 2006.201.04:02:42.72#ibcon#first serial, iclass 27, count 2 2006.201.04:02:42.72#ibcon#enter sib2, iclass 27, count 2 2006.201.04:02:42.72#ibcon#flushed, iclass 27, count 2 2006.201.04:02:42.72#ibcon#about to write, iclass 27, count 2 2006.201.04:02:42.72#ibcon#wrote, iclass 27, count 2 2006.201.04:02:42.72#ibcon#about to read 3, iclass 27, count 2 2006.201.04:02:42.74#ibcon#read 3, iclass 27, count 2 2006.201.04:02:42.74#ibcon#about to read 4, iclass 27, count 2 2006.201.04:02:42.74#ibcon#read 4, iclass 27, count 2 2006.201.04:02:42.74#ibcon#about to read 5, iclass 27, count 2 2006.201.04:02:42.74#ibcon#read 5, iclass 27, count 2 2006.201.04:02:42.74#ibcon#about to read 6, iclass 27, count 2 2006.201.04:02:42.74#ibcon#read 6, iclass 27, count 2 2006.201.04:02:42.74#ibcon#end of sib2, iclass 27, count 2 2006.201.04:02:42.74#ibcon#*mode == 0, iclass 27, count 2 2006.201.04:02:42.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.04:02:42.74#ibcon#[27=AT07-04\r\n] 2006.201.04:02:42.74#ibcon#*before write, iclass 27, count 2 2006.201.04:02:42.74#ibcon#enter sib2, iclass 27, count 2 2006.201.04:02:42.74#ibcon#flushed, iclass 27, count 2 2006.201.04:02:42.74#ibcon#about to write, iclass 27, count 2 2006.201.04:02:42.74#ibcon#wrote, iclass 27, count 2 2006.201.04:02:42.74#ibcon#about to read 3, iclass 27, count 2 2006.201.04:02:42.77#ibcon#read 3, iclass 27, count 2 2006.201.04:02:42.77#ibcon#about to read 4, iclass 27, count 2 2006.201.04:02:42.77#ibcon#read 4, iclass 27, count 2 2006.201.04:02:42.77#ibcon#about to read 5, iclass 27, count 2 2006.201.04:02:42.77#ibcon#read 5, iclass 27, count 2 2006.201.04:02:42.77#ibcon#about to read 6, iclass 27, count 2 2006.201.04:02:42.77#ibcon#read 6, iclass 27, count 2 2006.201.04:02:42.77#ibcon#end of sib2, iclass 27, count 2 2006.201.04:02:42.77#ibcon#*after write, iclass 27, count 2 2006.201.04:02:42.77#ibcon#*before return 0, iclass 27, count 2 2006.201.04:02:42.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:42.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:02:42.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.04:02:42.77#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:42.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:42.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:42.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:42.89#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:02:42.89#ibcon#first serial, iclass 27, count 0 2006.201.04:02:42.89#ibcon#enter sib2, iclass 27, count 0 2006.201.04:02:42.89#ibcon#flushed, iclass 27, count 0 2006.201.04:02:42.89#ibcon#about to write, iclass 27, count 0 2006.201.04:02:42.89#ibcon#wrote, iclass 27, count 0 2006.201.04:02:42.89#ibcon#about to read 3, iclass 27, count 0 2006.201.04:02:42.91#ibcon#read 3, iclass 27, count 0 2006.201.04:02:42.91#ibcon#about to read 4, iclass 27, count 0 2006.201.04:02:42.91#ibcon#read 4, iclass 27, count 0 2006.201.04:02:42.91#ibcon#about to read 5, iclass 27, count 0 2006.201.04:02:42.91#ibcon#read 5, iclass 27, count 0 2006.201.04:02:42.91#ibcon#about to read 6, iclass 27, count 0 2006.201.04:02:42.91#ibcon#read 6, iclass 27, count 0 2006.201.04:02:42.91#ibcon#end of sib2, iclass 27, count 0 2006.201.04:02:42.91#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:02:42.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:02:42.91#ibcon#[27=USB\r\n] 2006.201.04:02:42.91#ibcon#*before write, iclass 27, count 0 2006.201.04:02:42.91#ibcon#enter sib2, iclass 27, count 0 2006.201.04:02:42.91#ibcon#flushed, iclass 27, count 0 2006.201.04:02:42.91#ibcon#about to write, iclass 27, count 0 2006.201.04:02:42.91#ibcon#wrote, iclass 27, count 0 2006.201.04:02:42.91#ibcon#about to read 3, iclass 27, count 0 2006.201.04:02:42.94#ibcon#read 3, iclass 27, count 0 2006.201.04:02:42.94#ibcon#about to read 4, iclass 27, count 0 2006.201.04:02:42.94#ibcon#read 4, iclass 27, count 0 2006.201.04:02:42.94#ibcon#about to read 5, iclass 27, count 0 2006.201.04:02:42.94#ibcon#read 5, iclass 27, count 0 2006.201.04:02:42.94#ibcon#about to read 6, iclass 27, count 0 2006.201.04:02:42.94#ibcon#read 6, iclass 27, count 0 2006.201.04:02:42.94#ibcon#end of sib2, iclass 27, count 0 2006.201.04:02:42.94#ibcon#*after write, iclass 27, count 0 2006.201.04:02:42.94#ibcon#*before return 0, iclass 27, count 0 2006.201.04:02:42.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:42.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:02:42.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:02:42.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:02:42.94$vck44/vblo=8,744.99 2006.201.04:02:42.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.04:02:42.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.04:02:42.94#ibcon#ireg 17 cls_cnt 0 2006.201.04:02:42.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:42.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:42.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:42.94#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:02:42.94#ibcon#first serial, iclass 29, count 0 2006.201.04:02:42.94#ibcon#enter sib2, iclass 29, count 0 2006.201.04:02:42.94#ibcon#flushed, iclass 29, count 0 2006.201.04:02:42.94#ibcon#about to write, iclass 29, count 0 2006.201.04:02:42.94#ibcon#wrote, iclass 29, count 0 2006.201.04:02:42.94#ibcon#about to read 3, iclass 29, count 0 2006.201.04:02:42.96#ibcon#read 3, iclass 29, count 0 2006.201.04:02:42.96#ibcon#about to read 4, iclass 29, count 0 2006.201.04:02:42.96#ibcon#read 4, iclass 29, count 0 2006.201.04:02:42.96#ibcon#about to read 5, iclass 29, count 0 2006.201.04:02:42.96#ibcon#read 5, iclass 29, count 0 2006.201.04:02:42.96#ibcon#about to read 6, iclass 29, count 0 2006.201.04:02:42.96#ibcon#read 6, iclass 29, count 0 2006.201.04:02:42.96#ibcon#end of sib2, iclass 29, count 0 2006.201.04:02:42.96#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:02:42.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:02:42.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:02:42.96#ibcon#*before write, iclass 29, count 0 2006.201.04:02:42.96#ibcon#enter sib2, iclass 29, count 0 2006.201.04:02:42.96#ibcon#flushed, iclass 29, count 0 2006.201.04:02:42.96#ibcon#about to write, iclass 29, count 0 2006.201.04:02:42.96#ibcon#wrote, iclass 29, count 0 2006.201.04:02:42.96#ibcon#about to read 3, iclass 29, count 0 2006.201.04:02:43.00#ibcon#read 3, iclass 29, count 0 2006.201.04:02:43.00#ibcon#about to read 4, iclass 29, count 0 2006.201.04:02:43.00#ibcon#read 4, iclass 29, count 0 2006.201.04:02:43.00#ibcon#about to read 5, iclass 29, count 0 2006.201.04:02:43.00#ibcon#read 5, iclass 29, count 0 2006.201.04:02:43.00#ibcon#about to read 6, iclass 29, count 0 2006.201.04:02:43.00#ibcon#read 6, iclass 29, count 0 2006.201.04:02:43.00#ibcon#end of sib2, iclass 29, count 0 2006.201.04:02:43.00#ibcon#*after write, iclass 29, count 0 2006.201.04:02:43.00#ibcon#*before return 0, iclass 29, count 0 2006.201.04:02:43.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:43.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:02:43.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:02:43.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:02:43.00$vck44/vb=8,4 2006.201.04:02:43.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.04:02:43.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.04:02:43.00#ibcon#ireg 11 cls_cnt 2 2006.201.04:02:43.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:43.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:43.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:43.06#ibcon#enter wrdev, iclass 31, count 2 2006.201.04:02:43.06#ibcon#first serial, iclass 31, count 2 2006.201.04:02:43.06#ibcon#enter sib2, iclass 31, count 2 2006.201.04:02:43.06#ibcon#flushed, iclass 31, count 2 2006.201.04:02:43.06#ibcon#about to write, iclass 31, count 2 2006.201.04:02:43.06#ibcon#wrote, iclass 31, count 2 2006.201.04:02:43.06#ibcon#about to read 3, iclass 31, count 2 2006.201.04:02:43.08#ibcon#read 3, iclass 31, count 2 2006.201.04:02:43.08#ibcon#about to read 4, iclass 31, count 2 2006.201.04:02:43.08#ibcon#read 4, iclass 31, count 2 2006.201.04:02:43.08#ibcon#about to read 5, iclass 31, count 2 2006.201.04:02:43.08#ibcon#read 5, iclass 31, count 2 2006.201.04:02:43.08#ibcon#about to read 6, iclass 31, count 2 2006.201.04:02:43.08#ibcon#read 6, iclass 31, count 2 2006.201.04:02:43.08#ibcon#end of sib2, iclass 31, count 2 2006.201.04:02:43.08#ibcon#*mode == 0, iclass 31, count 2 2006.201.04:02:43.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.04:02:43.08#ibcon#[27=AT08-04\r\n] 2006.201.04:02:43.08#ibcon#*before write, iclass 31, count 2 2006.201.04:02:43.08#ibcon#enter sib2, iclass 31, count 2 2006.201.04:02:43.08#ibcon#flushed, iclass 31, count 2 2006.201.04:02:43.08#ibcon#about to write, iclass 31, count 2 2006.201.04:02:43.08#ibcon#wrote, iclass 31, count 2 2006.201.04:02:43.08#ibcon#about to read 3, iclass 31, count 2 2006.201.04:02:43.11#ibcon#read 3, iclass 31, count 2 2006.201.04:02:43.11#ibcon#about to read 4, iclass 31, count 2 2006.201.04:02:43.11#ibcon#read 4, iclass 31, count 2 2006.201.04:02:43.11#ibcon#about to read 5, iclass 31, count 2 2006.201.04:02:43.11#ibcon#read 5, iclass 31, count 2 2006.201.04:02:43.11#ibcon#about to read 6, iclass 31, count 2 2006.201.04:02:43.11#ibcon#read 6, iclass 31, count 2 2006.201.04:02:43.11#ibcon#end of sib2, iclass 31, count 2 2006.201.04:02:43.11#ibcon#*after write, iclass 31, count 2 2006.201.04:02:43.11#ibcon#*before return 0, iclass 31, count 2 2006.201.04:02:43.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:43.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:02:43.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.04:02:43.11#ibcon#ireg 7 cls_cnt 0 2006.201.04:02:43.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:43.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:43.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:43.23#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:02:43.23#ibcon#first serial, iclass 31, count 0 2006.201.04:02:43.23#ibcon#enter sib2, iclass 31, count 0 2006.201.04:02:43.23#ibcon#flushed, iclass 31, count 0 2006.201.04:02:43.23#ibcon#about to write, iclass 31, count 0 2006.201.04:02:43.23#ibcon#wrote, iclass 31, count 0 2006.201.04:02:43.23#ibcon#about to read 3, iclass 31, count 0 2006.201.04:02:43.25#ibcon#read 3, iclass 31, count 0 2006.201.04:02:43.25#ibcon#about to read 4, iclass 31, count 0 2006.201.04:02:43.25#ibcon#read 4, iclass 31, count 0 2006.201.04:02:43.25#ibcon#about to read 5, iclass 31, count 0 2006.201.04:02:43.25#ibcon#read 5, iclass 31, count 0 2006.201.04:02:43.25#ibcon#about to read 6, iclass 31, count 0 2006.201.04:02:43.25#ibcon#read 6, iclass 31, count 0 2006.201.04:02:43.25#ibcon#end of sib2, iclass 31, count 0 2006.201.04:02:43.25#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:02:43.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:02:43.25#ibcon#[27=USB\r\n] 2006.201.04:02:43.25#ibcon#*before write, iclass 31, count 0 2006.201.04:02:43.25#ibcon#enter sib2, iclass 31, count 0 2006.201.04:02:43.25#ibcon#flushed, iclass 31, count 0 2006.201.04:02:43.25#ibcon#about to write, iclass 31, count 0 2006.201.04:02:43.25#ibcon#wrote, iclass 31, count 0 2006.201.04:02:43.25#ibcon#about to read 3, iclass 31, count 0 2006.201.04:02:43.28#ibcon#read 3, iclass 31, count 0 2006.201.04:02:43.28#ibcon#about to read 4, iclass 31, count 0 2006.201.04:02:43.28#ibcon#read 4, iclass 31, count 0 2006.201.04:02:43.28#ibcon#about to read 5, iclass 31, count 0 2006.201.04:02:43.28#ibcon#read 5, iclass 31, count 0 2006.201.04:02:43.28#ibcon#about to read 6, iclass 31, count 0 2006.201.04:02:43.28#ibcon#read 6, iclass 31, count 0 2006.201.04:02:43.28#ibcon#end of sib2, iclass 31, count 0 2006.201.04:02:43.28#ibcon#*after write, iclass 31, count 0 2006.201.04:02:43.28#ibcon#*before return 0, iclass 31, count 0 2006.201.04:02:43.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:43.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:02:43.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:02:43.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:02:43.28$vck44/vabw=wide 2006.201.04:02:43.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.04:02:43.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.04:02:43.28#ibcon#ireg 8 cls_cnt 0 2006.201.04:02:43.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:43.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:43.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:43.28#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:02:43.28#ibcon#first serial, iclass 33, count 0 2006.201.04:02:43.28#ibcon#enter sib2, iclass 33, count 0 2006.201.04:02:43.28#ibcon#flushed, iclass 33, count 0 2006.201.04:02:43.28#ibcon#about to write, iclass 33, count 0 2006.201.04:02:43.28#ibcon#wrote, iclass 33, count 0 2006.201.04:02:43.28#ibcon#about to read 3, iclass 33, count 0 2006.201.04:02:43.30#ibcon#read 3, iclass 33, count 0 2006.201.04:02:43.30#ibcon#about to read 4, iclass 33, count 0 2006.201.04:02:43.30#ibcon#read 4, iclass 33, count 0 2006.201.04:02:43.30#ibcon#about to read 5, iclass 33, count 0 2006.201.04:02:43.30#ibcon#read 5, iclass 33, count 0 2006.201.04:02:43.30#ibcon#about to read 6, iclass 33, count 0 2006.201.04:02:43.30#ibcon#read 6, iclass 33, count 0 2006.201.04:02:43.30#ibcon#end of sib2, iclass 33, count 0 2006.201.04:02:43.30#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:02:43.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:02:43.30#ibcon#[25=BW32\r\n] 2006.201.04:02:43.30#ibcon#*before write, iclass 33, count 0 2006.201.04:02:43.30#ibcon#enter sib2, iclass 33, count 0 2006.201.04:02:43.30#ibcon#flushed, iclass 33, count 0 2006.201.04:02:43.30#ibcon#about to write, iclass 33, count 0 2006.201.04:02:43.30#ibcon#wrote, iclass 33, count 0 2006.201.04:02:43.30#ibcon#about to read 3, iclass 33, count 0 2006.201.04:02:43.33#ibcon#read 3, iclass 33, count 0 2006.201.04:02:43.33#ibcon#about to read 4, iclass 33, count 0 2006.201.04:02:43.33#ibcon#read 4, iclass 33, count 0 2006.201.04:02:43.33#ibcon#about to read 5, iclass 33, count 0 2006.201.04:02:43.33#ibcon#read 5, iclass 33, count 0 2006.201.04:02:43.33#ibcon#about to read 6, iclass 33, count 0 2006.201.04:02:43.33#ibcon#read 6, iclass 33, count 0 2006.201.04:02:43.33#ibcon#end of sib2, iclass 33, count 0 2006.201.04:02:43.33#ibcon#*after write, iclass 33, count 0 2006.201.04:02:43.33#ibcon#*before return 0, iclass 33, count 0 2006.201.04:02:43.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:43.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:02:43.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:02:43.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:02:43.33$vck44/vbbw=wide 2006.201.04:02:43.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.04:02:43.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.04:02:43.33#ibcon#ireg 8 cls_cnt 0 2006.201.04:02:43.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:02:43.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:02:43.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:02:43.40#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:02:43.40#ibcon#first serial, iclass 35, count 0 2006.201.04:02:43.40#ibcon#enter sib2, iclass 35, count 0 2006.201.04:02:43.40#ibcon#flushed, iclass 35, count 0 2006.201.04:02:43.40#ibcon#about to write, iclass 35, count 0 2006.201.04:02:43.40#ibcon#wrote, iclass 35, count 0 2006.201.04:02:43.40#ibcon#about to read 3, iclass 35, count 0 2006.201.04:02:43.42#ibcon#read 3, iclass 35, count 0 2006.201.04:02:43.42#ibcon#about to read 4, iclass 35, count 0 2006.201.04:02:43.42#ibcon#read 4, iclass 35, count 0 2006.201.04:02:43.42#ibcon#about to read 5, iclass 35, count 0 2006.201.04:02:43.42#ibcon#read 5, iclass 35, count 0 2006.201.04:02:43.42#ibcon#about to read 6, iclass 35, count 0 2006.201.04:02:43.42#ibcon#read 6, iclass 35, count 0 2006.201.04:02:43.42#ibcon#end of sib2, iclass 35, count 0 2006.201.04:02:43.42#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:02:43.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:02:43.42#ibcon#[27=BW32\r\n] 2006.201.04:02:43.42#ibcon#*before write, iclass 35, count 0 2006.201.04:02:43.42#ibcon#enter sib2, iclass 35, count 0 2006.201.04:02:43.42#ibcon#flushed, iclass 35, count 0 2006.201.04:02:43.42#ibcon#about to write, iclass 35, count 0 2006.201.04:02:43.42#ibcon#wrote, iclass 35, count 0 2006.201.04:02:43.42#ibcon#about to read 3, iclass 35, count 0 2006.201.04:02:43.45#ibcon#read 3, iclass 35, count 0 2006.201.04:02:43.45#ibcon#about to read 4, iclass 35, count 0 2006.201.04:02:43.45#ibcon#read 4, iclass 35, count 0 2006.201.04:02:43.45#ibcon#about to read 5, iclass 35, count 0 2006.201.04:02:43.45#ibcon#read 5, iclass 35, count 0 2006.201.04:02:43.45#ibcon#about to read 6, iclass 35, count 0 2006.201.04:02:43.45#ibcon#read 6, iclass 35, count 0 2006.201.04:02:43.45#ibcon#end of sib2, iclass 35, count 0 2006.201.04:02:43.45#ibcon#*after write, iclass 35, count 0 2006.201.04:02:43.45#ibcon#*before return 0, iclass 35, count 0 2006.201.04:02:43.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:02:43.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:02:43.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:02:43.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:02:43.45$setupk4/ifdk4 2006.201.04:02:43.45$ifdk4/lo= 2006.201.04:02:43.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:02:43.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:02:43.45$ifdk4/patch= 2006.201.04:02:43.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:02:43.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:02:43.45$setupk4/!*+20s 2006.201.04:02:47.77#abcon#<5=/04 2.5 5.3 22.93 911004.1\r\n> 2006.201.04:02:47.79#abcon#{5=INTERFACE CLEAR} 2006.201.04:02:47.85#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:02:53.14#trakl#Source acquired 2006.201.04:02:55.14#flagr#flagr/antenna,acquired 2006.201.04:02:57.92$setupk4/"tpicd 2006.201.04:02:57.92$setupk4/echo=off 2006.201.04:02:57.92$setupk4/xlog=off 2006.201.04:02:57.92:!2006.201.04:08:15 2006.201.04:02:57.94#abcon#<5=/04 2.5 5.3 22.93 901004.1\r\n> 2006.201.04:08:15.00:preob 2006.201.04:08:15.14/onsource/TRACKING 2006.201.04:08:15.14:!2006.201.04:08:25 2006.201.04:08:25.00:"tape 2006.201.04:08:25.00:"st=record 2006.201.04:08:25.00:data_valid=on 2006.201.04:08:25.00:midob 2006.201.04:08:25.14/onsource/TRACKING 2006.201.04:08:25.14/wx/22.95,1004.1,91 2006.201.04:08:25.32/cable/+6.4658E-03 2006.201.04:08:26.41/va/01,08,usb,yes,29,31 2006.201.04:08:26.41/va/02,07,usb,yes,31,32 2006.201.04:08:26.41/va/03,08,usb,yes,28,29 2006.201.04:08:26.41/va/04,07,usb,yes,32,34 2006.201.04:08:26.41/va/05,04,usb,yes,28,29 2006.201.04:08:26.41/va/06,05,usb,yes,28,28 2006.201.04:08:26.41/va/07,05,usb,yes,28,29 2006.201.04:08:26.41/va/08,04,usb,yes,27,33 2006.201.04:08:26.64/valo/01,524.99,yes,locked 2006.201.04:08:26.64/valo/02,534.99,yes,locked 2006.201.04:08:26.64/valo/03,564.99,yes,locked 2006.201.04:08:26.64/valo/04,624.99,yes,locked 2006.201.04:08:26.64/valo/05,734.99,yes,locked 2006.201.04:08:26.64/valo/06,814.99,yes,locked 2006.201.04:08:26.64/valo/07,864.99,yes,locked 2006.201.04:08:26.64/valo/08,884.99,yes,locked 2006.201.04:08:27.73/vb/01,04,usb,yes,28,28 2006.201.04:08:27.73/vb/02,05,usb,yes,27,28 2006.201.04:08:27.73/vb/03,04,usb,yes,28,31 2006.201.04:08:27.73/vb/04,05,usb,yes,28,27 2006.201.04:08:27.73/vb/05,04,usb,yes,25,27 2006.201.04:08:27.73/vb/06,04,usb,yes,30,26 2006.201.04:08:27.73/vb/07,04,usb,yes,29,29 2006.201.04:08:27.73/vb/08,04,usb,yes,27,30 2006.201.04:08:27.96/vblo/01,629.99,yes,locked 2006.201.04:08:27.96/vblo/02,634.99,yes,locked 2006.201.04:08:27.96/vblo/03,649.99,yes,locked 2006.201.04:08:27.96/vblo/04,679.99,yes,locked 2006.201.04:08:27.96/vblo/05,709.99,yes,locked 2006.201.04:08:27.96/vblo/06,719.99,yes,locked 2006.201.04:08:27.96/vblo/07,734.99,yes,locked 2006.201.04:08:27.96/vblo/08,744.99,yes,locked 2006.201.04:08:28.11/vabw/8 2006.201.04:08:28.26/vbbw/8 2006.201.04:08:28.35/xfe/off,on,15.2 2006.201.04:08:28.74/ifatt/23,28,28,28 2006.201.04:08:29.04/fmout-gps/S +4.53E-07 2006.201.04:08:29.08:!2006.201.04:13:15 2006.201.04:13:15.00:data_valid=off 2006.201.04:13:15.00:"et 2006.201.04:13:15.00:!+3s 2006.201.04:13:18.01:"tape 2006.201.04:13:18.01:postob 2006.201.04:13:18.07/cable/+6.4653E-03 2006.201.04:13:18.07/wx/23.03,1004.1,91 2006.201.04:13:18.13/fmout-gps/S +4.51E-07 2006.201.04:13:18.13:scan_name=201-0422,jd0607,130 2006.201.04:13:18.13:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.201.04:13:19.13#flagr#flagr/antenna,new-source 2006.201.04:13:19.13:checkk5 2006.201.04:13:19.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:13:19.86/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:13:20.21/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:13:20.56/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:13:20.90/chk_obsdata//k5ts1/T2010408??a.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.201.04:13:21.25/chk_obsdata//k5ts2/T2010408??b.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.201.04:13:21.58/chk_obsdata//k5ts3/T2010408??c.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.201.04:13:21.93/chk_obsdata//k5ts4/T2010408??d.dat file size is correct (nominal:1160MB, actual:1160MB). 2006.201.04:13:22.59/k5log//k5ts1_log_newline 2006.201.04:13:23.25/k5log//k5ts2_log_newline 2006.201.04:13:23.90/k5log//k5ts3_log_newline 2006.201.04:13:24.56/k5log//k5ts4_log_newline 2006.201.04:13:24.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:13:24.59:setupk4=1 2006.201.04:13:24.59$setupk4/echo=on 2006.201.04:13:24.59$setupk4/pcalon 2006.201.04:13:24.59$pcalon/"no phase cal control is implemented here 2006.201.04:13:24.59$setupk4/"tpicd=stop 2006.201.04:13:24.59$setupk4/"rec=synch_on 2006.201.04:13:24.59$setupk4/"rec_mode=128 2006.201.04:13:24.59$setupk4/!* 2006.201.04:13:24.59$setupk4/recpk4 2006.201.04:13:24.59$recpk4/recpatch= 2006.201.04:13:24.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:13:24.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:13:24.59$setupk4/vck44 2006.201.04:13:24.59$vck44/valo=1,524.99 2006.201.04:13:24.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.04:13:24.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.04:13:24.59#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:24.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:24.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:24.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:24.59#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:13:24.59#ibcon#first serial, iclass 35, count 0 2006.201.04:13:24.59#ibcon#enter sib2, iclass 35, count 0 2006.201.04:13:24.59#ibcon#flushed, iclass 35, count 0 2006.201.04:13:24.59#ibcon#about to write, iclass 35, count 0 2006.201.04:13:24.59#ibcon#wrote, iclass 35, count 0 2006.201.04:13:24.59#ibcon#about to read 3, iclass 35, count 0 2006.201.04:13:24.61#ibcon#read 3, iclass 35, count 0 2006.201.04:13:24.61#ibcon#about to read 4, iclass 35, count 0 2006.201.04:13:24.61#ibcon#read 4, iclass 35, count 0 2006.201.04:13:24.61#ibcon#about to read 5, iclass 35, count 0 2006.201.04:13:24.61#ibcon#read 5, iclass 35, count 0 2006.201.04:13:24.61#ibcon#about to read 6, iclass 35, count 0 2006.201.04:13:24.61#ibcon#read 6, iclass 35, count 0 2006.201.04:13:24.61#ibcon#end of sib2, iclass 35, count 0 2006.201.04:13:24.61#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:13:24.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:13:24.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:13:24.61#ibcon#*before write, iclass 35, count 0 2006.201.04:13:24.61#ibcon#enter sib2, iclass 35, count 0 2006.201.04:13:24.61#ibcon#flushed, iclass 35, count 0 2006.201.04:13:24.61#ibcon#about to write, iclass 35, count 0 2006.201.04:13:24.61#ibcon#wrote, iclass 35, count 0 2006.201.04:13:24.61#ibcon#about to read 3, iclass 35, count 0 2006.201.04:13:24.66#ibcon#read 3, iclass 35, count 0 2006.201.04:13:24.66#ibcon#about to read 4, iclass 35, count 0 2006.201.04:13:24.66#ibcon#read 4, iclass 35, count 0 2006.201.04:13:24.66#ibcon#about to read 5, iclass 35, count 0 2006.201.04:13:24.66#ibcon#read 5, iclass 35, count 0 2006.201.04:13:24.66#ibcon#about to read 6, iclass 35, count 0 2006.201.04:13:24.66#ibcon#read 6, iclass 35, count 0 2006.201.04:13:24.66#ibcon#end of sib2, iclass 35, count 0 2006.201.04:13:24.66#ibcon#*after write, iclass 35, count 0 2006.201.04:13:24.66#ibcon#*before return 0, iclass 35, count 0 2006.201.04:13:24.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:24.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:24.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:13:24.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:13:24.66$vck44/va=1,8 2006.201.04:13:24.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.04:13:24.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.04:13:24.66#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:24.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:24.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:24.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:24.66#ibcon#enter wrdev, iclass 37, count 2 2006.201.04:13:24.66#ibcon#first serial, iclass 37, count 2 2006.201.04:13:24.66#ibcon#enter sib2, iclass 37, count 2 2006.201.04:13:24.66#ibcon#flushed, iclass 37, count 2 2006.201.04:13:24.66#ibcon#about to write, iclass 37, count 2 2006.201.04:13:24.66#ibcon#wrote, iclass 37, count 2 2006.201.04:13:24.66#ibcon#about to read 3, iclass 37, count 2 2006.201.04:13:24.68#ibcon#read 3, iclass 37, count 2 2006.201.04:13:24.68#ibcon#about to read 4, iclass 37, count 2 2006.201.04:13:24.68#ibcon#read 4, iclass 37, count 2 2006.201.04:13:24.68#ibcon#about to read 5, iclass 37, count 2 2006.201.04:13:24.68#ibcon#read 5, iclass 37, count 2 2006.201.04:13:24.68#ibcon#about to read 6, iclass 37, count 2 2006.201.04:13:24.68#ibcon#read 6, iclass 37, count 2 2006.201.04:13:24.68#ibcon#end of sib2, iclass 37, count 2 2006.201.04:13:24.68#ibcon#*mode == 0, iclass 37, count 2 2006.201.04:13:24.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.04:13:24.68#ibcon#[25=AT01-08\r\n] 2006.201.04:13:24.68#ibcon#*before write, iclass 37, count 2 2006.201.04:13:24.68#ibcon#enter sib2, iclass 37, count 2 2006.201.04:13:24.68#ibcon#flushed, iclass 37, count 2 2006.201.04:13:24.68#ibcon#about to write, iclass 37, count 2 2006.201.04:13:24.68#ibcon#wrote, iclass 37, count 2 2006.201.04:13:24.68#ibcon#about to read 3, iclass 37, count 2 2006.201.04:13:24.71#ibcon#read 3, iclass 37, count 2 2006.201.04:13:24.71#ibcon#about to read 4, iclass 37, count 2 2006.201.04:13:24.71#ibcon#read 4, iclass 37, count 2 2006.201.04:13:24.71#ibcon#about to read 5, iclass 37, count 2 2006.201.04:13:24.71#ibcon#read 5, iclass 37, count 2 2006.201.04:13:24.71#ibcon#about to read 6, iclass 37, count 2 2006.201.04:13:24.71#ibcon#read 6, iclass 37, count 2 2006.201.04:13:24.71#ibcon#end of sib2, iclass 37, count 2 2006.201.04:13:24.71#ibcon#*after write, iclass 37, count 2 2006.201.04:13:24.71#ibcon#*before return 0, iclass 37, count 2 2006.201.04:13:24.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:24.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:24.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.04:13:24.71#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:24.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:24.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:24.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:24.83#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:13:24.83#ibcon#first serial, iclass 37, count 0 2006.201.04:13:24.83#ibcon#enter sib2, iclass 37, count 0 2006.201.04:13:24.83#ibcon#flushed, iclass 37, count 0 2006.201.04:13:24.83#ibcon#about to write, iclass 37, count 0 2006.201.04:13:24.83#ibcon#wrote, iclass 37, count 0 2006.201.04:13:24.83#ibcon#about to read 3, iclass 37, count 0 2006.201.04:13:24.85#ibcon#read 3, iclass 37, count 0 2006.201.04:13:24.85#ibcon#about to read 4, iclass 37, count 0 2006.201.04:13:24.85#ibcon#read 4, iclass 37, count 0 2006.201.04:13:24.85#ibcon#about to read 5, iclass 37, count 0 2006.201.04:13:24.85#ibcon#read 5, iclass 37, count 0 2006.201.04:13:24.85#ibcon#about to read 6, iclass 37, count 0 2006.201.04:13:24.85#ibcon#read 6, iclass 37, count 0 2006.201.04:13:24.85#ibcon#end of sib2, iclass 37, count 0 2006.201.04:13:24.85#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:13:24.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:13:24.85#ibcon#[25=USB\r\n] 2006.201.04:13:24.85#ibcon#*before write, iclass 37, count 0 2006.201.04:13:24.85#ibcon#enter sib2, iclass 37, count 0 2006.201.04:13:24.85#ibcon#flushed, iclass 37, count 0 2006.201.04:13:24.85#ibcon#about to write, iclass 37, count 0 2006.201.04:13:24.85#ibcon#wrote, iclass 37, count 0 2006.201.04:13:24.85#ibcon#about to read 3, iclass 37, count 0 2006.201.04:13:24.88#ibcon#read 3, iclass 37, count 0 2006.201.04:13:24.88#ibcon#about to read 4, iclass 37, count 0 2006.201.04:13:24.88#ibcon#read 4, iclass 37, count 0 2006.201.04:13:24.88#ibcon#about to read 5, iclass 37, count 0 2006.201.04:13:24.88#ibcon#read 5, iclass 37, count 0 2006.201.04:13:24.88#ibcon#about to read 6, iclass 37, count 0 2006.201.04:13:24.88#ibcon#read 6, iclass 37, count 0 2006.201.04:13:24.88#ibcon#end of sib2, iclass 37, count 0 2006.201.04:13:24.88#ibcon#*after write, iclass 37, count 0 2006.201.04:13:24.88#ibcon#*before return 0, iclass 37, count 0 2006.201.04:13:24.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:24.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:24.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:13:24.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:13:24.88$vck44/valo=2,534.99 2006.201.04:13:24.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.04:13:24.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.04:13:24.88#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:24.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:24.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:24.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:24.88#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:13:24.88#ibcon#first serial, iclass 39, count 0 2006.201.04:13:24.88#ibcon#enter sib2, iclass 39, count 0 2006.201.04:13:24.88#ibcon#flushed, iclass 39, count 0 2006.201.04:13:24.88#ibcon#about to write, iclass 39, count 0 2006.201.04:13:24.88#ibcon#wrote, iclass 39, count 0 2006.201.04:13:24.88#ibcon#about to read 3, iclass 39, count 0 2006.201.04:13:24.90#ibcon#read 3, iclass 39, count 0 2006.201.04:13:24.90#ibcon#about to read 4, iclass 39, count 0 2006.201.04:13:24.90#ibcon#read 4, iclass 39, count 0 2006.201.04:13:24.90#ibcon#about to read 5, iclass 39, count 0 2006.201.04:13:24.90#ibcon#read 5, iclass 39, count 0 2006.201.04:13:24.90#ibcon#about to read 6, iclass 39, count 0 2006.201.04:13:24.90#ibcon#read 6, iclass 39, count 0 2006.201.04:13:24.90#ibcon#end of sib2, iclass 39, count 0 2006.201.04:13:24.90#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:13:24.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:13:24.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:13:24.90#ibcon#*before write, iclass 39, count 0 2006.201.04:13:24.90#ibcon#enter sib2, iclass 39, count 0 2006.201.04:13:24.90#ibcon#flushed, iclass 39, count 0 2006.201.04:13:24.90#ibcon#about to write, iclass 39, count 0 2006.201.04:13:24.90#ibcon#wrote, iclass 39, count 0 2006.201.04:13:24.90#ibcon#about to read 3, iclass 39, count 0 2006.201.04:13:24.94#ibcon#read 3, iclass 39, count 0 2006.201.04:13:24.94#ibcon#about to read 4, iclass 39, count 0 2006.201.04:13:24.94#ibcon#read 4, iclass 39, count 0 2006.201.04:13:24.94#ibcon#about to read 5, iclass 39, count 0 2006.201.04:13:24.94#ibcon#read 5, iclass 39, count 0 2006.201.04:13:24.94#ibcon#about to read 6, iclass 39, count 0 2006.201.04:13:24.94#ibcon#read 6, iclass 39, count 0 2006.201.04:13:24.94#ibcon#end of sib2, iclass 39, count 0 2006.201.04:13:24.94#ibcon#*after write, iclass 39, count 0 2006.201.04:13:24.94#ibcon#*before return 0, iclass 39, count 0 2006.201.04:13:24.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:24.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:24.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:13:24.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:13:24.94$vck44/va=2,7 2006.201.04:13:24.94#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.04:13:24.94#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.04:13:24.94#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:24.94#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:25.00#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:25.00#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:25.00#ibcon#enter wrdev, iclass 2, count 2 2006.201.04:13:25.00#ibcon#first serial, iclass 2, count 2 2006.201.04:13:25.00#ibcon#enter sib2, iclass 2, count 2 2006.201.04:13:25.00#ibcon#flushed, iclass 2, count 2 2006.201.04:13:25.00#ibcon#about to write, iclass 2, count 2 2006.201.04:13:25.00#ibcon#wrote, iclass 2, count 2 2006.201.04:13:25.00#ibcon#about to read 3, iclass 2, count 2 2006.201.04:13:25.02#ibcon#read 3, iclass 2, count 2 2006.201.04:13:25.02#ibcon#about to read 4, iclass 2, count 2 2006.201.04:13:25.02#ibcon#read 4, iclass 2, count 2 2006.201.04:13:25.02#ibcon#about to read 5, iclass 2, count 2 2006.201.04:13:25.02#ibcon#read 5, iclass 2, count 2 2006.201.04:13:25.02#ibcon#about to read 6, iclass 2, count 2 2006.201.04:13:25.02#ibcon#read 6, iclass 2, count 2 2006.201.04:13:25.02#ibcon#end of sib2, iclass 2, count 2 2006.201.04:13:25.02#ibcon#*mode == 0, iclass 2, count 2 2006.201.04:13:25.02#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.04:13:25.02#ibcon#[25=AT02-07\r\n] 2006.201.04:13:25.02#ibcon#*before write, iclass 2, count 2 2006.201.04:13:25.02#ibcon#enter sib2, iclass 2, count 2 2006.201.04:13:25.02#ibcon#flushed, iclass 2, count 2 2006.201.04:13:25.02#ibcon#about to write, iclass 2, count 2 2006.201.04:13:25.02#ibcon#wrote, iclass 2, count 2 2006.201.04:13:25.02#ibcon#about to read 3, iclass 2, count 2 2006.201.04:13:25.05#ibcon#read 3, iclass 2, count 2 2006.201.04:13:25.05#ibcon#about to read 4, iclass 2, count 2 2006.201.04:13:25.05#ibcon#read 4, iclass 2, count 2 2006.201.04:13:25.05#ibcon#about to read 5, iclass 2, count 2 2006.201.04:13:25.05#ibcon#read 5, iclass 2, count 2 2006.201.04:13:25.05#ibcon#about to read 6, iclass 2, count 2 2006.201.04:13:25.05#ibcon#read 6, iclass 2, count 2 2006.201.04:13:25.05#ibcon#end of sib2, iclass 2, count 2 2006.201.04:13:25.05#ibcon#*after write, iclass 2, count 2 2006.201.04:13:25.05#ibcon#*before return 0, iclass 2, count 2 2006.201.04:13:25.05#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:25.05#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:25.05#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.04:13:25.05#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:25.05#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:25.17#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:25.17#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:25.17#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:13:25.17#ibcon#first serial, iclass 2, count 0 2006.201.04:13:25.17#ibcon#enter sib2, iclass 2, count 0 2006.201.04:13:25.17#ibcon#flushed, iclass 2, count 0 2006.201.04:13:25.17#ibcon#about to write, iclass 2, count 0 2006.201.04:13:25.17#ibcon#wrote, iclass 2, count 0 2006.201.04:13:25.17#ibcon#about to read 3, iclass 2, count 0 2006.201.04:13:25.19#ibcon#read 3, iclass 2, count 0 2006.201.04:13:25.19#ibcon#about to read 4, iclass 2, count 0 2006.201.04:13:25.19#ibcon#read 4, iclass 2, count 0 2006.201.04:13:25.19#ibcon#about to read 5, iclass 2, count 0 2006.201.04:13:25.19#ibcon#read 5, iclass 2, count 0 2006.201.04:13:25.19#ibcon#about to read 6, iclass 2, count 0 2006.201.04:13:25.19#ibcon#read 6, iclass 2, count 0 2006.201.04:13:25.19#ibcon#end of sib2, iclass 2, count 0 2006.201.04:13:25.19#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:13:25.19#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:13:25.19#ibcon#[25=USB\r\n] 2006.201.04:13:25.19#ibcon#*before write, iclass 2, count 0 2006.201.04:13:25.19#ibcon#enter sib2, iclass 2, count 0 2006.201.04:13:25.19#ibcon#flushed, iclass 2, count 0 2006.201.04:13:25.19#ibcon#about to write, iclass 2, count 0 2006.201.04:13:25.19#ibcon#wrote, iclass 2, count 0 2006.201.04:13:25.19#ibcon#about to read 3, iclass 2, count 0 2006.201.04:13:25.22#ibcon#read 3, iclass 2, count 0 2006.201.04:13:25.22#ibcon#about to read 4, iclass 2, count 0 2006.201.04:13:25.22#ibcon#read 4, iclass 2, count 0 2006.201.04:13:25.22#ibcon#about to read 5, iclass 2, count 0 2006.201.04:13:25.22#ibcon#read 5, iclass 2, count 0 2006.201.04:13:25.22#ibcon#about to read 6, iclass 2, count 0 2006.201.04:13:25.22#ibcon#read 6, iclass 2, count 0 2006.201.04:13:25.22#ibcon#end of sib2, iclass 2, count 0 2006.201.04:13:25.22#ibcon#*after write, iclass 2, count 0 2006.201.04:13:25.22#ibcon#*before return 0, iclass 2, count 0 2006.201.04:13:25.22#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:25.22#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:25.22#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:13:25.22#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:13:25.22$vck44/valo=3,564.99 2006.201.04:13:25.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.04:13:25.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.04:13:25.22#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:25.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:25.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:25.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:25.22#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:13:25.22#ibcon#first serial, iclass 5, count 0 2006.201.04:13:25.22#ibcon#enter sib2, iclass 5, count 0 2006.201.04:13:25.22#ibcon#flushed, iclass 5, count 0 2006.201.04:13:25.22#ibcon#about to write, iclass 5, count 0 2006.201.04:13:25.22#ibcon#wrote, iclass 5, count 0 2006.201.04:13:25.22#ibcon#about to read 3, iclass 5, count 0 2006.201.04:13:25.24#ibcon#read 3, iclass 5, count 0 2006.201.04:13:25.24#ibcon#about to read 4, iclass 5, count 0 2006.201.04:13:25.24#ibcon#read 4, iclass 5, count 0 2006.201.04:13:25.24#ibcon#about to read 5, iclass 5, count 0 2006.201.04:13:25.24#ibcon#read 5, iclass 5, count 0 2006.201.04:13:25.24#ibcon#about to read 6, iclass 5, count 0 2006.201.04:13:25.24#ibcon#read 6, iclass 5, count 0 2006.201.04:13:25.24#ibcon#end of sib2, iclass 5, count 0 2006.201.04:13:25.24#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:13:25.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:13:25.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:13:25.24#ibcon#*before write, iclass 5, count 0 2006.201.04:13:25.24#ibcon#enter sib2, iclass 5, count 0 2006.201.04:13:25.24#ibcon#flushed, iclass 5, count 0 2006.201.04:13:25.24#ibcon#about to write, iclass 5, count 0 2006.201.04:13:25.24#ibcon#wrote, iclass 5, count 0 2006.201.04:13:25.24#ibcon#about to read 3, iclass 5, count 0 2006.201.04:13:25.28#ibcon#read 3, iclass 5, count 0 2006.201.04:13:25.28#ibcon#about to read 4, iclass 5, count 0 2006.201.04:13:25.28#ibcon#read 4, iclass 5, count 0 2006.201.04:13:25.28#ibcon#about to read 5, iclass 5, count 0 2006.201.04:13:25.28#ibcon#read 5, iclass 5, count 0 2006.201.04:13:25.28#ibcon#about to read 6, iclass 5, count 0 2006.201.04:13:25.28#ibcon#read 6, iclass 5, count 0 2006.201.04:13:25.28#ibcon#end of sib2, iclass 5, count 0 2006.201.04:13:25.28#ibcon#*after write, iclass 5, count 0 2006.201.04:13:25.28#ibcon#*before return 0, iclass 5, count 0 2006.201.04:13:25.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:25.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:25.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:13:25.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:13:25.28$vck44/va=3,8 2006.201.04:13:25.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.04:13:25.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.04:13:25.28#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:25.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:25.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:25.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:25.34#ibcon#enter wrdev, iclass 7, count 2 2006.201.04:13:25.34#ibcon#first serial, iclass 7, count 2 2006.201.04:13:25.34#ibcon#enter sib2, iclass 7, count 2 2006.201.04:13:25.34#ibcon#flushed, iclass 7, count 2 2006.201.04:13:25.34#ibcon#about to write, iclass 7, count 2 2006.201.04:13:25.34#ibcon#wrote, iclass 7, count 2 2006.201.04:13:25.34#ibcon#about to read 3, iclass 7, count 2 2006.201.04:13:25.36#ibcon#read 3, iclass 7, count 2 2006.201.04:13:25.36#ibcon#about to read 4, iclass 7, count 2 2006.201.04:13:25.36#ibcon#read 4, iclass 7, count 2 2006.201.04:13:25.36#ibcon#about to read 5, iclass 7, count 2 2006.201.04:13:25.36#ibcon#read 5, iclass 7, count 2 2006.201.04:13:25.36#ibcon#about to read 6, iclass 7, count 2 2006.201.04:13:25.36#ibcon#read 6, iclass 7, count 2 2006.201.04:13:25.36#ibcon#end of sib2, iclass 7, count 2 2006.201.04:13:25.36#ibcon#*mode == 0, iclass 7, count 2 2006.201.04:13:25.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.04:13:25.36#ibcon#[25=AT03-08\r\n] 2006.201.04:13:25.36#ibcon#*before write, iclass 7, count 2 2006.201.04:13:25.36#ibcon#enter sib2, iclass 7, count 2 2006.201.04:13:25.36#ibcon#flushed, iclass 7, count 2 2006.201.04:13:25.36#ibcon#about to write, iclass 7, count 2 2006.201.04:13:25.36#ibcon#wrote, iclass 7, count 2 2006.201.04:13:25.36#ibcon#about to read 3, iclass 7, count 2 2006.201.04:13:25.39#ibcon#read 3, iclass 7, count 2 2006.201.04:13:25.39#ibcon#about to read 4, iclass 7, count 2 2006.201.04:13:25.39#ibcon#read 4, iclass 7, count 2 2006.201.04:13:25.39#ibcon#about to read 5, iclass 7, count 2 2006.201.04:13:25.39#ibcon#read 5, iclass 7, count 2 2006.201.04:13:25.39#ibcon#about to read 6, iclass 7, count 2 2006.201.04:13:25.39#ibcon#read 6, iclass 7, count 2 2006.201.04:13:25.39#ibcon#end of sib2, iclass 7, count 2 2006.201.04:13:25.39#ibcon#*after write, iclass 7, count 2 2006.201.04:13:25.39#ibcon#*before return 0, iclass 7, count 2 2006.201.04:13:25.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:25.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:25.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.04:13:25.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:25.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:25.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:25.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:25.51#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:13:25.51#ibcon#first serial, iclass 7, count 0 2006.201.04:13:25.51#ibcon#enter sib2, iclass 7, count 0 2006.201.04:13:25.51#ibcon#flushed, iclass 7, count 0 2006.201.04:13:25.51#ibcon#about to write, iclass 7, count 0 2006.201.04:13:25.51#ibcon#wrote, iclass 7, count 0 2006.201.04:13:25.51#ibcon#about to read 3, iclass 7, count 0 2006.201.04:13:25.53#ibcon#read 3, iclass 7, count 0 2006.201.04:13:25.53#ibcon#about to read 4, iclass 7, count 0 2006.201.04:13:25.53#ibcon#read 4, iclass 7, count 0 2006.201.04:13:25.53#ibcon#about to read 5, iclass 7, count 0 2006.201.04:13:25.53#ibcon#read 5, iclass 7, count 0 2006.201.04:13:25.53#ibcon#about to read 6, iclass 7, count 0 2006.201.04:13:25.53#ibcon#read 6, iclass 7, count 0 2006.201.04:13:25.53#ibcon#end of sib2, iclass 7, count 0 2006.201.04:13:25.53#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:13:25.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:13:25.53#ibcon#[25=USB\r\n] 2006.201.04:13:25.53#ibcon#*before write, iclass 7, count 0 2006.201.04:13:25.53#ibcon#enter sib2, iclass 7, count 0 2006.201.04:13:25.53#ibcon#flushed, iclass 7, count 0 2006.201.04:13:25.53#ibcon#about to write, iclass 7, count 0 2006.201.04:13:25.53#ibcon#wrote, iclass 7, count 0 2006.201.04:13:25.53#ibcon#about to read 3, iclass 7, count 0 2006.201.04:13:25.56#ibcon#read 3, iclass 7, count 0 2006.201.04:13:25.56#ibcon#about to read 4, iclass 7, count 0 2006.201.04:13:25.56#ibcon#read 4, iclass 7, count 0 2006.201.04:13:25.56#ibcon#about to read 5, iclass 7, count 0 2006.201.04:13:25.56#ibcon#read 5, iclass 7, count 0 2006.201.04:13:25.56#ibcon#about to read 6, iclass 7, count 0 2006.201.04:13:25.56#ibcon#read 6, iclass 7, count 0 2006.201.04:13:25.56#ibcon#end of sib2, iclass 7, count 0 2006.201.04:13:25.56#ibcon#*after write, iclass 7, count 0 2006.201.04:13:25.56#ibcon#*before return 0, iclass 7, count 0 2006.201.04:13:25.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:25.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:25.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:13:25.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:13:25.56$vck44/valo=4,624.99 2006.201.04:13:25.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.04:13:25.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.04:13:25.56#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:25.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:25.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:25.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:25.56#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:13:25.56#ibcon#first serial, iclass 11, count 0 2006.201.04:13:25.56#ibcon#enter sib2, iclass 11, count 0 2006.201.04:13:25.56#ibcon#flushed, iclass 11, count 0 2006.201.04:13:25.56#ibcon#about to write, iclass 11, count 0 2006.201.04:13:25.56#ibcon#wrote, iclass 11, count 0 2006.201.04:13:25.56#ibcon#about to read 3, iclass 11, count 0 2006.201.04:13:25.58#ibcon#read 3, iclass 11, count 0 2006.201.04:13:25.58#ibcon#about to read 4, iclass 11, count 0 2006.201.04:13:25.58#ibcon#read 4, iclass 11, count 0 2006.201.04:13:25.58#ibcon#about to read 5, iclass 11, count 0 2006.201.04:13:25.58#ibcon#read 5, iclass 11, count 0 2006.201.04:13:25.58#ibcon#about to read 6, iclass 11, count 0 2006.201.04:13:25.58#ibcon#read 6, iclass 11, count 0 2006.201.04:13:25.58#ibcon#end of sib2, iclass 11, count 0 2006.201.04:13:25.58#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:13:25.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:13:25.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:13:25.58#ibcon#*before write, iclass 11, count 0 2006.201.04:13:25.58#ibcon#enter sib2, iclass 11, count 0 2006.201.04:13:25.58#ibcon#flushed, iclass 11, count 0 2006.201.04:13:25.58#ibcon#about to write, iclass 11, count 0 2006.201.04:13:25.58#ibcon#wrote, iclass 11, count 0 2006.201.04:13:25.58#ibcon#about to read 3, iclass 11, count 0 2006.201.04:13:25.62#ibcon#read 3, iclass 11, count 0 2006.201.04:13:25.62#ibcon#about to read 4, iclass 11, count 0 2006.201.04:13:25.62#ibcon#read 4, iclass 11, count 0 2006.201.04:13:25.62#ibcon#about to read 5, iclass 11, count 0 2006.201.04:13:25.62#ibcon#read 5, iclass 11, count 0 2006.201.04:13:25.62#ibcon#about to read 6, iclass 11, count 0 2006.201.04:13:25.62#ibcon#read 6, iclass 11, count 0 2006.201.04:13:25.62#ibcon#end of sib2, iclass 11, count 0 2006.201.04:13:25.62#ibcon#*after write, iclass 11, count 0 2006.201.04:13:25.62#ibcon#*before return 0, iclass 11, count 0 2006.201.04:13:25.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:25.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:25.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:13:25.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:13:25.62$vck44/va=4,7 2006.201.04:13:25.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.04:13:25.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.04:13:25.62#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:25.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:25.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:25.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:25.68#ibcon#enter wrdev, iclass 13, count 2 2006.201.04:13:25.68#ibcon#first serial, iclass 13, count 2 2006.201.04:13:25.68#ibcon#enter sib2, iclass 13, count 2 2006.201.04:13:25.68#ibcon#flushed, iclass 13, count 2 2006.201.04:13:25.68#ibcon#about to write, iclass 13, count 2 2006.201.04:13:25.68#ibcon#wrote, iclass 13, count 2 2006.201.04:13:25.68#ibcon#about to read 3, iclass 13, count 2 2006.201.04:13:25.70#ibcon#read 3, iclass 13, count 2 2006.201.04:13:25.70#ibcon#about to read 4, iclass 13, count 2 2006.201.04:13:25.70#ibcon#read 4, iclass 13, count 2 2006.201.04:13:25.70#ibcon#about to read 5, iclass 13, count 2 2006.201.04:13:25.70#ibcon#read 5, iclass 13, count 2 2006.201.04:13:25.70#ibcon#about to read 6, iclass 13, count 2 2006.201.04:13:25.70#ibcon#read 6, iclass 13, count 2 2006.201.04:13:25.70#ibcon#end of sib2, iclass 13, count 2 2006.201.04:13:25.70#ibcon#*mode == 0, iclass 13, count 2 2006.201.04:13:25.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.04:13:25.70#ibcon#[25=AT04-07\r\n] 2006.201.04:13:25.70#ibcon#*before write, iclass 13, count 2 2006.201.04:13:25.70#ibcon#enter sib2, iclass 13, count 2 2006.201.04:13:25.70#ibcon#flushed, iclass 13, count 2 2006.201.04:13:25.70#ibcon#about to write, iclass 13, count 2 2006.201.04:13:25.70#ibcon#wrote, iclass 13, count 2 2006.201.04:13:25.70#ibcon#about to read 3, iclass 13, count 2 2006.201.04:13:25.73#ibcon#read 3, iclass 13, count 2 2006.201.04:13:25.73#ibcon#about to read 4, iclass 13, count 2 2006.201.04:13:25.73#ibcon#read 4, iclass 13, count 2 2006.201.04:13:25.73#ibcon#about to read 5, iclass 13, count 2 2006.201.04:13:25.73#ibcon#read 5, iclass 13, count 2 2006.201.04:13:25.73#ibcon#about to read 6, iclass 13, count 2 2006.201.04:13:25.73#ibcon#read 6, iclass 13, count 2 2006.201.04:13:25.73#ibcon#end of sib2, iclass 13, count 2 2006.201.04:13:25.73#ibcon#*after write, iclass 13, count 2 2006.201.04:13:25.73#ibcon#*before return 0, iclass 13, count 2 2006.201.04:13:25.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:25.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:25.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.04:13:25.73#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:25.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:25.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:25.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:25.85#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:13:25.85#ibcon#first serial, iclass 13, count 0 2006.201.04:13:25.85#ibcon#enter sib2, iclass 13, count 0 2006.201.04:13:25.85#ibcon#flushed, iclass 13, count 0 2006.201.04:13:25.85#ibcon#about to write, iclass 13, count 0 2006.201.04:13:25.85#ibcon#wrote, iclass 13, count 0 2006.201.04:13:25.85#ibcon#about to read 3, iclass 13, count 0 2006.201.04:13:25.87#ibcon#read 3, iclass 13, count 0 2006.201.04:13:25.87#ibcon#about to read 4, iclass 13, count 0 2006.201.04:13:25.87#ibcon#read 4, iclass 13, count 0 2006.201.04:13:25.87#ibcon#about to read 5, iclass 13, count 0 2006.201.04:13:25.87#ibcon#read 5, iclass 13, count 0 2006.201.04:13:25.87#ibcon#about to read 6, iclass 13, count 0 2006.201.04:13:25.87#ibcon#read 6, iclass 13, count 0 2006.201.04:13:25.87#ibcon#end of sib2, iclass 13, count 0 2006.201.04:13:25.87#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:13:25.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:13:25.87#ibcon#[25=USB\r\n] 2006.201.04:13:25.87#ibcon#*before write, iclass 13, count 0 2006.201.04:13:25.87#ibcon#enter sib2, iclass 13, count 0 2006.201.04:13:25.87#ibcon#flushed, iclass 13, count 0 2006.201.04:13:25.87#ibcon#about to write, iclass 13, count 0 2006.201.04:13:25.87#ibcon#wrote, iclass 13, count 0 2006.201.04:13:25.87#ibcon#about to read 3, iclass 13, count 0 2006.201.04:13:25.90#ibcon#read 3, iclass 13, count 0 2006.201.04:13:25.90#ibcon#about to read 4, iclass 13, count 0 2006.201.04:13:25.90#ibcon#read 4, iclass 13, count 0 2006.201.04:13:25.90#ibcon#about to read 5, iclass 13, count 0 2006.201.04:13:25.90#ibcon#read 5, iclass 13, count 0 2006.201.04:13:25.90#ibcon#about to read 6, iclass 13, count 0 2006.201.04:13:25.90#ibcon#read 6, iclass 13, count 0 2006.201.04:13:25.90#ibcon#end of sib2, iclass 13, count 0 2006.201.04:13:25.90#ibcon#*after write, iclass 13, count 0 2006.201.04:13:25.90#ibcon#*before return 0, iclass 13, count 0 2006.201.04:13:25.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:25.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:25.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:13:25.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:13:25.90$vck44/valo=5,734.99 2006.201.04:13:25.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.04:13:25.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.04:13:25.90#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:25.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:25.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:25.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:25.90#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:13:25.90#ibcon#first serial, iclass 15, count 0 2006.201.04:13:25.90#ibcon#enter sib2, iclass 15, count 0 2006.201.04:13:25.90#ibcon#flushed, iclass 15, count 0 2006.201.04:13:25.90#ibcon#about to write, iclass 15, count 0 2006.201.04:13:25.90#ibcon#wrote, iclass 15, count 0 2006.201.04:13:25.90#ibcon#about to read 3, iclass 15, count 0 2006.201.04:13:25.92#ibcon#read 3, iclass 15, count 0 2006.201.04:13:25.92#ibcon#about to read 4, iclass 15, count 0 2006.201.04:13:25.92#ibcon#read 4, iclass 15, count 0 2006.201.04:13:25.92#ibcon#about to read 5, iclass 15, count 0 2006.201.04:13:25.92#ibcon#read 5, iclass 15, count 0 2006.201.04:13:25.92#ibcon#about to read 6, iclass 15, count 0 2006.201.04:13:25.92#ibcon#read 6, iclass 15, count 0 2006.201.04:13:25.92#ibcon#end of sib2, iclass 15, count 0 2006.201.04:13:25.92#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:13:25.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:13:25.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:13:25.92#ibcon#*before write, iclass 15, count 0 2006.201.04:13:25.92#ibcon#enter sib2, iclass 15, count 0 2006.201.04:13:25.92#ibcon#flushed, iclass 15, count 0 2006.201.04:13:25.92#ibcon#about to write, iclass 15, count 0 2006.201.04:13:25.92#ibcon#wrote, iclass 15, count 0 2006.201.04:13:25.92#ibcon#about to read 3, iclass 15, count 0 2006.201.04:13:25.96#ibcon#read 3, iclass 15, count 0 2006.201.04:13:25.96#ibcon#about to read 4, iclass 15, count 0 2006.201.04:13:25.96#ibcon#read 4, iclass 15, count 0 2006.201.04:13:25.96#ibcon#about to read 5, iclass 15, count 0 2006.201.04:13:25.96#ibcon#read 5, iclass 15, count 0 2006.201.04:13:25.96#ibcon#about to read 6, iclass 15, count 0 2006.201.04:13:25.96#ibcon#read 6, iclass 15, count 0 2006.201.04:13:25.96#ibcon#end of sib2, iclass 15, count 0 2006.201.04:13:25.96#ibcon#*after write, iclass 15, count 0 2006.201.04:13:25.96#ibcon#*before return 0, iclass 15, count 0 2006.201.04:13:25.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:25.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:25.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:13:25.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:13:25.96$vck44/va=5,4 2006.201.04:13:25.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.04:13:25.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.04:13:25.96#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:25.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:26.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:26.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:26.02#ibcon#enter wrdev, iclass 17, count 2 2006.201.04:13:26.02#ibcon#first serial, iclass 17, count 2 2006.201.04:13:26.02#ibcon#enter sib2, iclass 17, count 2 2006.201.04:13:26.02#ibcon#flushed, iclass 17, count 2 2006.201.04:13:26.02#ibcon#about to write, iclass 17, count 2 2006.201.04:13:26.02#ibcon#wrote, iclass 17, count 2 2006.201.04:13:26.02#ibcon#about to read 3, iclass 17, count 2 2006.201.04:13:26.04#ibcon#read 3, iclass 17, count 2 2006.201.04:13:26.04#ibcon#about to read 4, iclass 17, count 2 2006.201.04:13:26.04#ibcon#read 4, iclass 17, count 2 2006.201.04:13:26.04#ibcon#about to read 5, iclass 17, count 2 2006.201.04:13:26.04#ibcon#read 5, iclass 17, count 2 2006.201.04:13:26.04#ibcon#about to read 6, iclass 17, count 2 2006.201.04:13:26.04#ibcon#read 6, iclass 17, count 2 2006.201.04:13:26.04#ibcon#end of sib2, iclass 17, count 2 2006.201.04:13:26.04#ibcon#*mode == 0, iclass 17, count 2 2006.201.04:13:26.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.04:13:26.04#ibcon#[25=AT05-04\r\n] 2006.201.04:13:26.04#ibcon#*before write, iclass 17, count 2 2006.201.04:13:26.04#ibcon#enter sib2, iclass 17, count 2 2006.201.04:13:26.04#ibcon#flushed, iclass 17, count 2 2006.201.04:13:26.04#ibcon#about to write, iclass 17, count 2 2006.201.04:13:26.04#ibcon#wrote, iclass 17, count 2 2006.201.04:13:26.04#ibcon#about to read 3, iclass 17, count 2 2006.201.04:13:26.07#ibcon#read 3, iclass 17, count 2 2006.201.04:13:26.07#ibcon#about to read 4, iclass 17, count 2 2006.201.04:13:26.07#ibcon#read 4, iclass 17, count 2 2006.201.04:13:26.07#ibcon#about to read 5, iclass 17, count 2 2006.201.04:13:26.07#ibcon#read 5, iclass 17, count 2 2006.201.04:13:26.07#ibcon#about to read 6, iclass 17, count 2 2006.201.04:13:26.07#ibcon#read 6, iclass 17, count 2 2006.201.04:13:26.07#ibcon#end of sib2, iclass 17, count 2 2006.201.04:13:26.07#ibcon#*after write, iclass 17, count 2 2006.201.04:13:26.07#ibcon#*before return 0, iclass 17, count 2 2006.201.04:13:26.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:26.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:26.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.04:13:26.07#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:26.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:26.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:26.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:26.19#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:13:26.19#ibcon#first serial, iclass 17, count 0 2006.201.04:13:26.19#ibcon#enter sib2, iclass 17, count 0 2006.201.04:13:26.19#ibcon#flushed, iclass 17, count 0 2006.201.04:13:26.19#ibcon#about to write, iclass 17, count 0 2006.201.04:13:26.19#ibcon#wrote, iclass 17, count 0 2006.201.04:13:26.19#ibcon#about to read 3, iclass 17, count 0 2006.201.04:13:26.21#ibcon#read 3, iclass 17, count 0 2006.201.04:13:26.21#ibcon#about to read 4, iclass 17, count 0 2006.201.04:13:26.21#ibcon#read 4, iclass 17, count 0 2006.201.04:13:26.21#ibcon#about to read 5, iclass 17, count 0 2006.201.04:13:26.21#ibcon#read 5, iclass 17, count 0 2006.201.04:13:26.21#ibcon#about to read 6, iclass 17, count 0 2006.201.04:13:26.21#ibcon#read 6, iclass 17, count 0 2006.201.04:13:26.21#ibcon#end of sib2, iclass 17, count 0 2006.201.04:13:26.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:13:26.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:13:26.21#ibcon#[25=USB\r\n] 2006.201.04:13:26.21#ibcon#*before write, iclass 17, count 0 2006.201.04:13:26.21#ibcon#enter sib2, iclass 17, count 0 2006.201.04:13:26.21#ibcon#flushed, iclass 17, count 0 2006.201.04:13:26.21#ibcon#about to write, iclass 17, count 0 2006.201.04:13:26.21#ibcon#wrote, iclass 17, count 0 2006.201.04:13:26.21#ibcon#about to read 3, iclass 17, count 0 2006.201.04:13:26.24#ibcon#read 3, iclass 17, count 0 2006.201.04:13:26.24#ibcon#about to read 4, iclass 17, count 0 2006.201.04:13:26.24#ibcon#read 4, iclass 17, count 0 2006.201.04:13:26.24#ibcon#about to read 5, iclass 17, count 0 2006.201.04:13:26.24#ibcon#read 5, iclass 17, count 0 2006.201.04:13:26.24#ibcon#about to read 6, iclass 17, count 0 2006.201.04:13:26.24#ibcon#read 6, iclass 17, count 0 2006.201.04:13:26.24#ibcon#end of sib2, iclass 17, count 0 2006.201.04:13:26.24#ibcon#*after write, iclass 17, count 0 2006.201.04:13:26.24#ibcon#*before return 0, iclass 17, count 0 2006.201.04:13:26.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:26.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:26.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:13:26.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:13:26.24$vck44/valo=6,814.99 2006.201.04:13:26.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.04:13:26.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.04:13:26.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:26.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:26.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:26.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:26.24#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:13:26.24#ibcon#first serial, iclass 19, count 0 2006.201.04:13:26.24#ibcon#enter sib2, iclass 19, count 0 2006.201.04:13:26.24#ibcon#flushed, iclass 19, count 0 2006.201.04:13:26.24#ibcon#about to write, iclass 19, count 0 2006.201.04:13:26.24#ibcon#wrote, iclass 19, count 0 2006.201.04:13:26.24#ibcon#about to read 3, iclass 19, count 0 2006.201.04:13:26.26#ibcon#read 3, iclass 19, count 0 2006.201.04:13:26.26#ibcon#about to read 4, iclass 19, count 0 2006.201.04:13:26.26#ibcon#read 4, iclass 19, count 0 2006.201.04:13:26.26#ibcon#about to read 5, iclass 19, count 0 2006.201.04:13:26.26#ibcon#read 5, iclass 19, count 0 2006.201.04:13:26.26#ibcon#about to read 6, iclass 19, count 0 2006.201.04:13:26.26#ibcon#read 6, iclass 19, count 0 2006.201.04:13:26.26#ibcon#end of sib2, iclass 19, count 0 2006.201.04:13:26.26#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:13:26.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:13:26.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:13:26.26#ibcon#*before write, iclass 19, count 0 2006.201.04:13:26.26#ibcon#enter sib2, iclass 19, count 0 2006.201.04:13:26.26#ibcon#flushed, iclass 19, count 0 2006.201.04:13:26.26#ibcon#about to write, iclass 19, count 0 2006.201.04:13:26.26#ibcon#wrote, iclass 19, count 0 2006.201.04:13:26.26#ibcon#about to read 3, iclass 19, count 0 2006.201.04:13:26.30#ibcon#read 3, iclass 19, count 0 2006.201.04:13:26.30#ibcon#about to read 4, iclass 19, count 0 2006.201.04:13:26.30#ibcon#read 4, iclass 19, count 0 2006.201.04:13:26.30#ibcon#about to read 5, iclass 19, count 0 2006.201.04:13:26.30#ibcon#read 5, iclass 19, count 0 2006.201.04:13:26.30#ibcon#about to read 6, iclass 19, count 0 2006.201.04:13:26.30#ibcon#read 6, iclass 19, count 0 2006.201.04:13:26.30#ibcon#end of sib2, iclass 19, count 0 2006.201.04:13:26.30#ibcon#*after write, iclass 19, count 0 2006.201.04:13:26.30#ibcon#*before return 0, iclass 19, count 0 2006.201.04:13:26.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:26.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:26.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:13:26.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:13:26.30$vck44/va=6,5 2006.201.04:13:26.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.04:13:26.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.04:13:26.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:26.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:26.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:26.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:26.36#ibcon#enter wrdev, iclass 21, count 2 2006.201.04:13:26.36#ibcon#first serial, iclass 21, count 2 2006.201.04:13:26.36#ibcon#enter sib2, iclass 21, count 2 2006.201.04:13:26.36#ibcon#flushed, iclass 21, count 2 2006.201.04:13:26.36#ibcon#about to write, iclass 21, count 2 2006.201.04:13:26.36#ibcon#wrote, iclass 21, count 2 2006.201.04:13:26.36#ibcon#about to read 3, iclass 21, count 2 2006.201.04:13:26.38#ibcon#read 3, iclass 21, count 2 2006.201.04:13:26.38#ibcon#about to read 4, iclass 21, count 2 2006.201.04:13:26.38#ibcon#read 4, iclass 21, count 2 2006.201.04:13:26.38#ibcon#about to read 5, iclass 21, count 2 2006.201.04:13:26.38#ibcon#read 5, iclass 21, count 2 2006.201.04:13:26.38#ibcon#about to read 6, iclass 21, count 2 2006.201.04:13:26.38#ibcon#read 6, iclass 21, count 2 2006.201.04:13:26.38#ibcon#end of sib2, iclass 21, count 2 2006.201.04:13:26.38#ibcon#*mode == 0, iclass 21, count 2 2006.201.04:13:26.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.04:13:26.38#ibcon#[25=AT06-05\r\n] 2006.201.04:13:26.38#ibcon#*before write, iclass 21, count 2 2006.201.04:13:26.38#ibcon#enter sib2, iclass 21, count 2 2006.201.04:13:26.38#ibcon#flushed, iclass 21, count 2 2006.201.04:13:26.38#ibcon#about to write, iclass 21, count 2 2006.201.04:13:26.38#ibcon#wrote, iclass 21, count 2 2006.201.04:13:26.38#ibcon#about to read 3, iclass 21, count 2 2006.201.04:13:26.41#ibcon#read 3, iclass 21, count 2 2006.201.04:13:26.41#ibcon#about to read 4, iclass 21, count 2 2006.201.04:13:26.41#ibcon#read 4, iclass 21, count 2 2006.201.04:13:26.41#ibcon#about to read 5, iclass 21, count 2 2006.201.04:13:26.41#ibcon#read 5, iclass 21, count 2 2006.201.04:13:26.41#ibcon#about to read 6, iclass 21, count 2 2006.201.04:13:26.41#ibcon#read 6, iclass 21, count 2 2006.201.04:13:26.41#ibcon#end of sib2, iclass 21, count 2 2006.201.04:13:26.41#ibcon#*after write, iclass 21, count 2 2006.201.04:13:26.41#ibcon#*before return 0, iclass 21, count 2 2006.201.04:13:26.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:26.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:26.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.04:13:26.41#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:26.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:26.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:26.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:26.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:13:26.53#ibcon#first serial, iclass 21, count 0 2006.201.04:13:26.53#ibcon#enter sib2, iclass 21, count 0 2006.201.04:13:26.53#ibcon#flushed, iclass 21, count 0 2006.201.04:13:26.53#ibcon#about to write, iclass 21, count 0 2006.201.04:13:26.53#ibcon#wrote, iclass 21, count 0 2006.201.04:13:26.53#ibcon#about to read 3, iclass 21, count 0 2006.201.04:13:26.55#ibcon#read 3, iclass 21, count 0 2006.201.04:13:26.55#ibcon#about to read 4, iclass 21, count 0 2006.201.04:13:26.55#ibcon#read 4, iclass 21, count 0 2006.201.04:13:26.55#ibcon#about to read 5, iclass 21, count 0 2006.201.04:13:26.55#ibcon#read 5, iclass 21, count 0 2006.201.04:13:26.55#ibcon#about to read 6, iclass 21, count 0 2006.201.04:13:26.55#ibcon#read 6, iclass 21, count 0 2006.201.04:13:26.55#ibcon#end of sib2, iclass 21, count 0 2006.201.04:13:26.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:13:26.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:13:26.55#ibcon#[25=USB\r\n] 2006.201.04:13:26.55#ibcon#*before write, iclass 21, count 0 2006.201.04:13:26.55#ibcon#enter sib2, iclass 21, count 0 2006.201.04:13:26.55#ibcon#flushed, iclass 21, count 0 2006.201.04:13:26.55#ibcon#about to write, iclass 21, count 0 2006.201.04:13:26.55#ibcon#wrote, iclass 21, count 0 2006.201.04:13:26.55#ibcon#about to read 3, iclass 21, count 0 2006.201.04:13:26.58#ibcon#read 3, iclass 21, count 0 2006.201.04:13:26.58#ibcon#about to read 4, iclass 21, count 0 2006.201.04:13:26.58#ibcon#read 4, iclass 21, count 0 2006.201.04:13:26.58#ibcon#about to read 5, iclass 21, count 0 2006.201.04:13:26.58#ibcon#read 5, iclass 21, count 0 2006.201.04:13:26.58#ibcon#about to read 6, iclass 21, count 0 2006.201.04:13:26.58#ibcon#read 6, iclass 21, count 0 2006.201.04:13:26.58#ibcon#end of sib2, iclass 21, count 0 2006.201.04:13:26.58#ibcon#*after write, iclass 21, count 0 2006.201.04:13:26.58#ibcon#*before return 0, iclass 21, count 0 2006.201.04:13:26.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:26.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:26.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:13:26.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:13:26.58$vck44/valo=7,864.99 2006.201.04:13:26.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.04:13:26.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.04:13:26.58#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:26.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:26.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:26.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:26.58#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:13:26.58#ibcon#first serial, iclass 23, count 0 2006.201.04:13:26.58#ibcon#enter sib2, iclass 23, count 0 2006.201.04:13:26.58#ibcon#flushed, iclass 23, count 0 2006.201.04:13:26.58#ibcon#about to write, iclass 23, count 0 2006.201.04:13:26.58#ibcon#wrote, iclass 23, count 0 2006.201.04:13:26.58#ibcon#about to read 3, iclass 23, count 0 2006.201.04:13:26.60#ibcon#read 3, iclass 23, count 0 2006.201.04:13:26.60#ibcon#about to read 4, iclass 23, count 0 2006.201.04:13:26.60#ibcon#read 4, iclass 23, count 0 2006.201.04:13:26.60#ibcon#about to read 5, iclass 23, count 0 2006.201.04:13:26.60#ibcon#read 5, iclass 23, count 0 2006.201.04:13:26.60#ibcon#about to read 6, iclass 23, count 0 2006.201.04:13:26.60#ibcon#read 6, iclass 23, count 0 2006.201.04:13:26.60#ibcon#end of sib2, iclass 23, count 0 2006.201.04:13:26.60#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:13:26.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:13:26.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:13:26.60#ibcon#*before write, iclass 23, count 0 2006.201.04:13:26.60#ibcon#enter sib2, iclass 23, count 0 2006.201.04:13:26.60#ibcon#flushed, iclass 23, count 0 2006.201.04:13:26.60#ibcon#about to write, iclass 23, count 0 2006.201.04:13:26.60#ibcon#wrote, iclass 23, count 0 2006.201.04:13:26.60#ibcon#about to read 3, iclass 23, count 0 2006.201.04:13:26.64#ibcon#read 3, iclass 23, count 0 2006.201.04:13:26.64#ibcon#about to read 4, iclass 23, count 0 2006.201.04:13:26.64#ibcon#read 4, iclass 23, count 0 2006.201.04:13:26.64#ibcon#about to read 5, iclass 23, count 0 2006.201.04:13:26.64#ibcon#read 5, iclass 23, count 0 2006.201.04:13:26.64#ibcon#about to read 6, iclass 23, count 0 2006.201.04:13:26.64#ibcon#read 6, iclass 23, count 0 2006.201.04:13:26.64#ibcon#end of sib2, iclass 23, count 0 2006.201.04:13:26.64#ibcon#*after write, iclass 23, count 0 2006.201.04:13:26.64#ibcon#*before return 0, iclass 23, count 0 2006.201.04:13:26.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:26.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:26.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:13:26.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:13:26.64$vck44/va=7,5 2006.201.04:13:26.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.04:13:26.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.04:13:26.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:26.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:26.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:26.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:26.70#ibcon#enter wrdev, iclass 25, count 2 2006.201.04:13:26.70#ibcon#first serial, iclass 25, count 2 2006.201.04:13:26.70#ibcon#enter sib2, iclass 25, count 2 2006.201.04:13:26.70#ibcon#flushed, iclass 25, count 2 2006.201.04:13:26.70#ibcon#about to write, iclass 25, count 2 2006.201.04:13:26.70#ibcon#wrote, iclass 25, count 2 2006.201.04:13:26.70#ibcon#about to read 3, iclass 25, count 2 2006.201.04:13:26.72#ibcon#read 3, iclass 25, count 2 2006.201.04:13:26.72#ibcon#about to read 4, iclass 25, count 2 2006.201.04:13:26.72#ibcon#read 4, iclass 25, count 2 2006.201.04:13:26.72#ibcon#about to read 5, iclass 25, count 2 2006.201.04:13:26.72#ibcon#read 5, iclass 25, count 2 2006.201.04:13:26.72#ibcon#about to read 6, iclass 25, count 2 2006.201.04:13:26.72#ibcon#read 6, iclass 25, count 2 2006.201.04:13:26.72#ibcon#end of sib2, iclass 25, count 2 2006.201.04:13:26.72#ibcon#*mode == 0, iclass 25, count 2 2006.201.04:13:26.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.04:13:26.72#ibcon#[25=AT07-05\r\n] 2006.201.04:13:26.72#ibcon#*before write, iclass 25, count 2 2006.201.04:13:26.72#ibcon#enter sib2, iclass 25, count 2 2006.201.04:13:26.72#ibcon#flushed, iclass 25, count 2 2006.201.04:13:26.72#ibcon#about to write, iclass 25, count 2 2006.201.04:13:26.72#ibcon#wrote, iclass 25, count 2 2006.201.04:13:26.72#ibcon#about to read 3, iclass 25, count 2 2006.201.04:13:26.75#ibcon#read 3, iclass 25, count 2 2006.201.04:13:26.75#ibcon#about to read 4, iclass 25, count 2 2006.201.04:13:26.75#ibcon#read 4, iclass 25, count 2 2006.201.04:13:26.75#ibcon#about to read 5, iclass 25, count 2 2006.201.04:13:26.75#ibcon#read 5, iclass 25, count 2 2006.201.04:13:26.75#ibcon#about to read 6, iclass 25, count 2 2006.201.04:13:26.75#ibcon#read 6, iclass 25, count 2 2006.201.04:13:26.75#ibcon#end of sib2, iclass 25, count 2 2006.201.04:13:26.75#ibcon#*after write, iclass 25, count 2 2006.201.04:13:26.75#ibcon#*before return 0, iclass 25, count 2 2006.201.04:13:26.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:26.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:26.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.04:13:26.75#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:26.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:26.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:26.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:26.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:13:26.87#ibcon#first serial, iclass 25, count 0 2006.201.04:13:26.87#ibcon#enter sib2, iclass 25, count 0 2006.201.04:13:26.87#ibcon#flushed, iclass 25, count 0 2006.201.04:13:26.87#ibcon#about to write, iclass 25, count 0 2006.201.04:13:26.87#ibcon#wrote, iclass 25, count 0 2006.201.04:13:26.87#ibcon#about to read 3, iclass 25, count 0 2006.201.04:13:26.89#ibcon#read 3, iclass 25, count 0 2006.201.04:13:26.89#ibcon#about to read 4, iclass 25, count 0 2006.201.04:13:26.89#ibcon#read 4, iclass 25, count 0 2006.201.04:13:26.89#ibcon#about to read 5, iclass 25, count 0 2006.201.04:13:26.89#ibcon#read 5, iclass 25, count 0 2006.201.04:13:26.89#ibcon#about to read 6, iclass 25, count 0 2006.201.04:13:26.89#ibcon#read 6, iclass 25, count 0 2006.201.04:13:26.89#ibcon#end of sib2, iclass 25, count 0 2006.201.04:13:26.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:13:26.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:13:26.89#ibcon#[25=USB\r\n] 2006.201.04:13:26.89#ibcon#*before write, iclass 25, count 0 2006.201.04:13:26.89#ibcon#enter sib2, iclass 25, count 0 2006.201.04:13:26.89#ibcon#flushed, iclass 25, count 0 2006.201.04:13:26.89#ibcon#about to write, iclass 25, count 0 2006.201.04:13:26.89#ibcon#wrote, iclass 25, count 0 2006.201.04:13:26.89#ibcon#about to read 3, iclass 25, count 0 2006.201.04:13:26.92#ibcon#read 3, iclass 25, count 0 2006.201.04:13:26.92#ibcon#about to read 4, iclass 25, count 0 2006.201.04:13:26.92#ibcon#read 4, iclass 25, count 0 2006.201.04:13:26.92#ibcon#about to read 5, iclass 25, count 0 2006.201.04:13:26.92#ibcon#read 5, iclass 25, count 0 2006.201.04:13:26.92#ibcon#about to read 6, iclass 25, count 0 2006.201.04:13:26.92#ibcon#read 6, iclass 25, count 0 2006.201.04:13:26.92#ibcon#end of sib2, iclass 25, count 0 2006.201.04:13:26.92#ibcon#*after write, iclass 25, count 0 2006.201.04:13:26.92#ibcon#*before return 0, iclass 25, count 0 2006.201.04:13:26.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:26.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:26.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:13:26.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:13:26.92$vck44/valo=8,884.99 2006.201.04:13:26.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.04:13:26.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.04:13:26.92#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:26.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:26.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:26.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:26.92#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:13:26.92#ibcon#first serial, iclass 27, count 0 2006.201.04:13:26.92#ibcon#enter sib2, iclass 27, count 0 2006.201.04:13:26.92#ibcon#flushed, iclass 27, count 0 2006.201.04:13:26.92#ibcon#about to write, iclass 27, count 0 2006.201.04:13:26.92#ibcon#wrote, iclass 27, count 0 2006.201.04:13:26.92#ibcon#about to read 3, iclass 27, count 0 2006.201.04:13:26.94#ibcon#read 3, iclass 27, count 0 2006.201.04:13:26.94#ibcon#about to read 4, iclass 27, count 0 2006.201.04:13:26.94#ibcon#read 4, iclass 27, count 0 2006.201.04:13:26.94#ibcon#about to read 5, iclass 27, count 0 2006.201.04:13:26.94#ibcon#read 5, iclass 27, count 0 2006.201.04:13:26.94#ibcon#about to read 6, iclass 27, count 0 2006.201.04:13:26.94#ibcon#read 6, iclass 27, count 0 2006.201.04:13:26.94#ibcon#end of sib2, iclass 27, count 0 2006.201.04:13:26.94#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:13:26.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:13:26.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:13:26.94#ibcon#*before write, iclass 27, count 0 2006.201.04:13:26.94#ibcon#enter sib2, iclass 27, count 0 2006.201.04:13:26.94#ibcon#flushed, iclass 27, count 0 2006.201.04:13:26.94#ibcon#about to write, iclass 27, count 0 2006.201.04:13:26.94#ibcon#wrote, iclass 27, count 0 2006.201.04:13:26.94#ibcon#about to read 3, iclass 27, count 0 2006.201.04:13:26.98#ibcon#read 3, iclass 27, count 0 2006.201.04:13:26.98#ibcon#about to read 4, iclass 27, count 0 2006.201.04:13:26.98#ibcon#read 4, iclass 27, count 0 2006.201.04:13:26.98#ibcon#about to read 5, iclass 27, count 0 2006.201.04:13:26.98#ibcon#read 5, iclass 27, count 0 2006.201.04:13:26.98#ibcon#about to read 6, iclass 27, count 0 2006.201.04:13:26.98#ibcon#read 6, iclass 27, count 0 2006.201.04:13:26.98#ibcon#end of sib2, iclass 27, count 0 2006.201.04:13:26.98#ibcon#*after write, iclass 27, count 0 2006.201.04:13:26.98#ibcon#*before return 0, iclass 27, count 0 2006.201.04:13:26.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:26.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:26.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:13:26.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:13:26.98$vck44/va=8,4 2006.201.04:13:26.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.04:13:26.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.04:13:26.98#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:26.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:13:27.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:13:27.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:13:27.04#ibcon#enter wrdev, iclass 29, count 2 2006.201.04:13:27.04#ibcon#first serial, iclass 29, count 2 2006.201.04:13:27.04#ibcon#enter sib2, iclass 29, count 2 2006.201.04:13:27.04#ibcon#flushed, iclass 29, count 2 2006.201.04:13:27.04#ibcon#about to write, iclass 29, count 2 2006.201.04:13:27.04#ibcon#wrote, iclass 29, count 2 2006.201.04:13:27.04#ibcon#about to read 3, iclass 29, count 2 2006.201.04:13:27.06#ibcon#read 3, iclass 29, count 2 2006.201.04:13:27.06#ibcon#about to read 4, iclass 29, count 2 2006.201.04:13:27.06#ibcon#read 4, iclass 29, count 2 2006.201.04:13:27.06#ibcon#about to read 5, iclass 29, count 2 2006.201.04:13:27.06#ibcon#read 5, iclass 29, count 2 2006.201.04:13:27.06#ibcon#about to read 6, iclass 29, count 2 2006.201.04:13:27.06#ibcon#read 6, iclass 29, count 2 2006.201.04:13:27.06#ibcon#end of sib2, iclass 29, count 2 2006.201.04:13:27.06#ibcon#*mode == 0, iclass 29, count 2 2006.201.04:13:27.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.04:13:27.06#ibcon#[25=AT08-04\r\n] 2006.201.04:13:27.06#ibcon#*before write, iclass 29, count 2 2006.201.04:13:27.06#ibcon#enter sib2, iclass 29, count 2 2006.201.04:13:27.06#ibcon#flushed, iclass 29, count 2 2006.201.04:13:27.06#ibcon#about to write, iclass 29, count 2 2006.201.04:13:27.06#ibcon#wrote, iclass 29, count 2 2006.201.04:13:27.06#ibcon#about to read 3, iclass 29, count 2 2006.201.04:13:27.09#ibcon#read 3, iclass 29, count 2 2006.201.04:13:27.09#ibcon#about to read 4, iclass 29, count 2 2006.201.04:13:27.09#ibcon#read 4, iclass 29, count 2 2006.201.04:13:27.09#ibcon#about to read 5, iclass 29, count 2 2006.201.04:13:27.09#ibcon#read 5, iclass 29, count 2 2006.201.04:13:27.09#ibcon#about to read 6, iclass 29, count 2 2006.201.04:13:27.09#ibcon#read 6, iclass 29, count 2 2006.201.04:13:27.09#ibcon#end of sib2, iclass 29, count 2 2006.201.04:13:27.09#ibcon#*after write, iclass 29, count 2 2006.201.04:13:27.09#ibcon#*before return 0, iclass 29, count 2 2006.201.04:13:27.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:13:27.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:13:27.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.04:13:27.09#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:27.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:13:27.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:13:27.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:13:27.21#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:13:27.21#ibcon#first serial, iclass 29, count 0 2006.201.04:13:27.21#ibcon#enter sib2, iclass 29, count 0 2006.201.04:13:27.21#ibcon#flushed, iclass 29, count 0 2006.201.04:13:27.21#ibcon#about to write, iclass 29, count 0 2006.201.04:13:27.21#ibcon#wrote, iclass 29, count 0 2006.201.04:13:27.21#ibcon#about to read 3, iclass 29, count 0 2006.201.04:13:27.23#ibcon#read 3, iclass 29, count 0 2006.201.04:13:27.23#ibcon#about to read 4, iclass 29, count 0 2006.201.04:13:27.23#ibcon#read 4, iclass 29, count 0 2006.201.04:13:27.23#ibcon#about to read 5, iclass 29, count 0 2006.201.04:13:27.23#ibcon#read 5, iclass 29, count 0 2006.201.04:13:27.23#ibcon#about to read 6, iclass 29, count 0 2006.201.04:13:27.23#ibcon#read 6, iclass 29, count 0 2006.201.04:13:27.23#ibcon#end of sib2, iclass 29, count 0 2006.201.04:13:27.23#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:13:27.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:13:27.23#ibcon#[25=USB\r\n] 2006.201.04:13:27.23#ibcon#*before write, iclass 29, count 0 2006.201.04:13:27.23#ibcon#enter sib2, iclass 29, count 0 2006.201.04:13:27.23#ibcon#flushed, iclass 29, count 0 2006.201.04:13:27.23#ibcon#about to write, iclass 29, count 0 2006.201.04:13:27.23#ibcon#wrote, iclass 29, count 0 2006.201.04:13:27.23#ibcon#about to read 3, iclass 29, count 0 2006.201.04:13:27.26#ibcon#read 3, iclass 29, count 0 2006.201.04:13:27.26#ibcon#about to read 4, iclass 29, count 0 2006.201.04:13:27.26#ibcon#read 4, iclass 29, count 0 2006.201.04:13:27.26#ibcon#about to read 5, iclass 29, count 0 2006.201.04:13:27.26#ibcon#read 5, iclass 29, count 0 2006.201.04:13:27.26#ibcon#about to read 6, iclass 29, count 0 2006.201.04:13:27.26#ibcon#read 6, iclass 29, count 0 2006.201.04:13:27.26#ibcon#end of sib2, iclass 29, count 0 2006.201.04:13:27.26#ibcon#*after write, iclass 29, count 0 2006.201.04:13:27.26#ibcon#*before return 0, iclass 29, count 0 2006.201.04:13:27.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:13:27.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:13:27.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:13:27.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:13:27.26$vck44/vblo=1,629.99 2006.201.04:13:27.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.04:13:27.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.04:13:27.26#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:27.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:13:27.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:13:27.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:13:27.26#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:13:27.26#ibcon#first serial, iclass 31, count 0 2006.201.04:13:27.26#ibcon#enter sib2, iclass 31, count 0 2006.201.04:13:27.26#ibcon#flushed, iclass 31, count 0 2006.201.04:13:27.26#ibcon#about to write, iclass 31, count 0 2006.201.04:13:27.26#ibcon#wrote, iclass 31, count 0 2006.201.04:13:27.26#ibcon#about to read 3, iclass 31, count 0 2006.201.04:13:27.28#ibcon#read 3, iclass 31, count 0 2006.201.04:13:27.28#ibcon#about to read 4, iclass 31, count 0 2006.201.04:13:27.28#ibcon#read 4, iclass 31, count 0 2006.201.04:13:27.28#ibcon#about to read 5, iclass 31, count 0 2006.201.04:13:27.28#ibcon#read 5, iclass 31, count 0 2006.201.04:13:27.28#ibcon#about to read 6, iclass 31, count 0 2006.201.04:13:27.28#ibcon#read 6, iclass 31, count 0 2006.201.04:13:27.28#ibcon#end of sib2, iclass 31, count 0 2006.201.04:13:27.28#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:13:27.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:13:27.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:13:27.28#ibcon#*before write, iclass 31, count 0 2006.201.04:13:27.28#ibcon#enter sib2, iclass 31, count 0 2006.201.04:13:27.28#ibcon#flushed, iclass 31, count 0 2006.201.04:13:27.28#ibcon#about to write, iclass 31, count 0 2006.201.04:13:27.28#ibcon#wrote, iclass 31, count 0 2006.201.04:13:27.28#ibcon#about to read 3, iclass 31, count 0 2006.201.04:13:27.32#ibcon#read 3, iclass 31, count 0 2006.201.04:13:27.32#ibcon#about to read 4, iclass 31, count 0 2006.201.04:13:27.32#ibcon#read 4, iclass 31, count 0 2006.201.04:13:27.32#ibcon#about to read 5, iclass 31, count 0 2006.201.04:13:27.32#ibcon#read 5, iclass 31, count 0 2006.201.04:13:27.32#ibcon#about to read 6, iclass 31, count 0 2006.201.04:13:27.32#ibcon#read 6, iclass 31, count 0 2006.201.04:13:27.32#ibcon#end of sib2, iclass 31, count 0 2006.201.04:13:27.32#ibcon#*after write, iclass 31, count 0 2006.201.04:13:27.32#ibcon#*before return 0, iclass 31, count 0 2006.201.04:13:27.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:13:27.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:13:27.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:13:27.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:13:27.32$vck44/vb=1,4 2006.201.04:13:27.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.04:13:27.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.04:13:27.32#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:27.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:13:27.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:13:27.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:13:27.32#ibcon#enter wrdev, iclass 33, count 2 2006.201.04:13:27.32#ibcon#first serial, iclass 33, count 2 2006.201.04:13:27.32#ibcon#enter sib2, iclass 33, count 2 2006.201.04:13:27.32#ibcon#flushed, iclass 33, count 2 2006.201.04:13:27.32#ibcon#about to write, iclass 33, count 2 2006.201.04:13:27.32#ibcon#wrote, iclass 33, count 2 2006.201.04:13:27.32#ibcon#about to read 3, iclass 33, count 2 2006.201.04:13:27.34#ibcon#read 3, iclass 33, count 2 2006.201.04:13:27.34#ibcon#about to read 4, iclass 33, count 2 2006.201.04:13:27.34#ibcon#read 4, iclass 33, count 2 2006.201.04:13:27.34#ibcon#about to read 5, iclass 33, count 2 2006.201.04:13:27.34#ibcon#read 5, iclass 33, count 2 2006.201.04:13:27.34#ibcon#about to read 6, iclass 33, count 2 2006.201.04:13:27.34#ibcon#read 6, iclass 33, count 2 2006.201.04:13:27.34#ibcon#end of sib2, iclass 33, count 2 2006.201.04:13:27.34#ibcon#*mode == 0, iclass 33, count 2 2006.201.04:13:27.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.04:13:27.34#ibcon#[27=AT01-04\r\n] 2006.201.04:13:27.34#ibcon#*before write, iclass 33, count 2 2006.201.04:13:27.34#ibcon#enter sib2, iclass 33, count 2 2006.201.04:13:27.34#ibcon#flushed, iclass 33, count 2 2006.201.04:13:27.34#ibcon#about to write, iclass 33, count 2 2006.201.04:13:27.34#ibcon#wrote, iclass 33, count 2 2006.201.04:13:27.34#ibcon#about to read 3, iclass 33, count 2 2006.201.04:13:27.37#ibcon#read 3, iclass 33, count 2 2006.201.04:13:27.37#ibcon#about to read 4, iclass 33, count 2 2006.201.04:13:27.37#ibcon#read 4, iclass 33, count 2 2006.201.04:13:27.37#ibcon#about to read 5, iclass 33, count 2 2006.201.04:13:27.37#ibcon#read 5, iclass 33, count 2 2006.201.04:13:27.37#ibcon#about to read 6, iclass 33, count 2 2006.201.04:13:27.37#ibcon#read 6, iclass 33, count 2 2006.201.04:13:27.37#ibcon#end of sib2, iclass 33, count 2 2006.201.04:13:27.37#ibcon#*after write, iclass 33, count 2 2006.201.04:13:27.37#ibcon#*before return 0, iclass 33, count 2 2006.201.04:13:27.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:13:27.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:13:27.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.04:13:27.37#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:27.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:13:27.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:13:27.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:13:27.49#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:13:27.49#ibcon#first serial, iclass 33, count 0 2006.201.04:13:27.49#ibcon#enter sib2, iclass 33, count 0 2006.201.04:13:27.49#ibcon#flushed, iclass 33, count 0 2006.201.04:13:27.49#ibcon#about to write, iclass 33, count 0 2006.201.04:13:27.49#ibcon#wrote, iclass 33, count 0 2006.201.04:13:27.49#ibcon#about to read 3, iclass 33, count 0 2006.201.04:13:27.51#ibcon#read 3, iclass 33, count 0 2006.201.04:13:27.51#ibcon#about to read 4, iclass 33, count 0 2006.201.04:13:27.51#ibcon#read 4, iclass 33, count 0 2006.201.04:13:27.51#ibcon#about to read 5, iclass 33, count 0 2006.201.04:13:27.51#ibcon#read 5, iclass 33, count 0 2006.201.04:13:27.51#ibcon#about to read 6, iclass 33, count 0 2006.201.04:13:27.51#ibcon#read 6, iclass 33, count 0 2006.201.04:13:27.51#ibcon#end of sib2, iclass 33, count 0 2006.201.04:13:27.51#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:13:27.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:13:27.51#ibcon#[27=USB\r\n] 2006.201.04:13:27.51#ibcon#*before write, iclass 33, count 0 2006.201.04:13:27.51#ibcon#enter sib2, iclass 33, count 0 2006.201.04:13:27.51#ibcon#flushed, iclass 33, count 0 2006.201.04:13:27.51#ibcon#about to write, iclass 33, count 0 2006.201.04:13:27.51#ibcon#wrote, iclass 33, count 0 2006.201.04:13:27.51#ibcon#about to read 3, iclass 33, count 0 2006.201.04:13:27.54#ibcon#read 3, iclass 33, count 0 2006.201.04:13:27.54#ibcon#about to read 4, iclass 33, count 0 2006.201.04:13:27.54#ibcon#read 4, iclass 33, count 0 2006.201.04:13:27.54#ibcon#about to read 5, iclass 33, count 0 2006.201.04:13:27.54#ibcon#read 5, iclass 33, count 0 2006.201.04:13:27.54#ibcon#about to read 6, iclass 33, count 0 2006.201.04:13:27.54#ibcon#read 6, iclass 33, count 0 2006.201.04:13:27.54#ibcon#end of sib2, iclass 33, count 0 2006.201.04:13:27.54#ibcon#*after write, iclass 33, count 0 2006.201.04:13:27.54#ibcon#*before return 0, iclass 33, count 0 2006.201.04:13:27.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:13:27.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:13:27.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:13:27.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:13:27.54$vck44/vblo=2,634.99 2006.201.04:13:27.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.04:13:27.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.04:13:27.54#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:27.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:27.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:27.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:27.54#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:13:27.54#ibcon#first serial, iclass 35, count 0 2006.201.04:13:27.54#ibcon#enter sib2, iclass 35, count 0 2006.201.04:13:27.54#ibcon#flushed, iclass 35, count 0 2006.201.04:13:27.54#ibcon#about to write, iclass 35, count 0 2006.201.04:13:27.54#ibcon#wrote, iclass 35, count 0 2006.201.04:13:27.54#ibcon#about to read 3, iclass 35, count 0 2006.201.04:13:27.56#ibcon#read 3, iclass 35, count 0 2006.201.04:13:27.56#ibcon#about to read 4, iclass 35, count 0 2006.201.04:13:27.56#ibcon#read 4, iclass 35, count 0 2006.201.04:13:27.56#ibcon#about to read 5, iclass 35, count 0 2006.201.04:13:27.56#ibcon#read 5, iclass 35, count 0 2006.201.04:13:27.56#ibcon#about to read 6, iclass 35, count 0 2006.201.04:13:27.56#ibcon#read 6, iclass 35, count 0 2006.201.04:13:27.56#ibcon#end of sib2, iclass 35, count 0 2006.201.04:13:27.56#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:13:27.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:13:27.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:13:27.56#ibcon#*before write, iclass 35, count 0 2006.201.04:13:27.56#ibcon#enter sib2, iclass 35, count 0 2006.201.04:13:27.56#ibcon#flushed, iclass 35, count 0 2006.201.04:13:27.56#ibcon#about to write, iclass 35, count 0 2006.201.04:13:27.56#ibcon#wrote, iclass 35, count 0 2006.201.04:13:27.56#ibcon#about to read 3, iclass 35, count 0 2006.201.04:13:27.60#ibcon#read 3, iclass 35, count 0 2006.201.04:13:27.60#ibcon#about to read 4, iclass 35, count 0 2006.201.04:13:27.60#ibcon#read 4, iclass 35, count 0 2006.201.04:13:27.60#ibcon#about to read 5, iclass 35, count 0 2006.201.04:13:27.60#ibcon#read 5, iclass 35, count 0 2006.201.04:13:27.60#ibcon#about to read 6, iclass 35, count 0 2006.201.04:13:27.60#ibcon#read 6, iclass 35, count 0 2006.201.04:13:27.60#ibcon#end of sib2, iclass 35, count 0 2006.201.04:13:27.60#ibcon#*after write, iclass 35, count 0 2006.201.04:13:27.60#ibcon#*before return 0, iclass 35, count 0 2006.201.04:13:27.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:27.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:13:27.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:13:27.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:13:27.60$vck44/vb=2,5 2006.201.04:13:27.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.04:13:27.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.04:13:27.60#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:27.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:27.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:27.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:27.66#ibcon#enter wrdev, iclass 37, count 2 2006.201.04:13:27.66#ibcon#first serial, iclass 37, count 2 2006.201.04:13:27.66#ibcon#enter sib2, iclass 37, count 2 2006.201.04:13:27.66#ibcon#flushed, iclass 37, count 2 2006.201.04:13:27.66#ibcon#about to write, iclass 37, count 2 2006.201.04:13:27.66#ibcon#wrote, iclass 37, count 2 2006.201.04:13:27.66#ibcon#about to read 3, iclass 37, count 2 2006.201.04:13:27.68#ibcon#read 3, iclass 37, count 2 2006.201.04:13:27.68#ibcon#about to read 4, iclass 37, count 2 2006.201.04:13:27.68#ibcon#read 4, iclass 37, count 2 2006.201.04:13:27.68#ibcon#about to read 5, iclass 37, count 2 2006.201.04:13:27.68#ibcon#read 5, iclass 37, count 2 2006.201.04:13:27.68#ibcon#about to read 6, iclass 37, count 2 2006.201.04:13:27.68#ibcon#read 6, iclass 37, count 2 2006.201.04:13:27.68#ibcon#end of sib2, iclass 37, count 2 2006.201.04:13:27.68#ibcon#*mode == 0, iclass 37, count 2 2006.201.04:13:27.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.04:13:27.68#ibcon#[27=AT02-05\r\n] 2006.201.04:13:27.68#ibcon#*before write, iclass 37, count 2 2006.201.04:13:27.68#ibcon#enter sib2, iclass 37, count 2 2006.201.04:13:27.68#ibcon#flushed, iclass 37, count 2 2006.201.04:13:27.68#ibcon#about to write, iclass 37, count 2 2006.201.04:13:27.68#ibcon#wrote, iclass 37, count 2 2006.201.04:13:27.68#ibcon#about to read 3, iclass 37, count 2 2006.201.04:13:27.71#ibcon#read 3, iclass 37, count 2 2006.201.04:13:27.71#ibcon#about to read 4, iclass 37, count 2 2006.201.04:13:27.71#ibcon#read 4, iclass 37, count 2 2006.201.04:13:27.71#ibcon#about to read 5, iclass 37, count 2 2006.201.04:13:27.71#ibcon#read 5, iclass 37, count 2 2006.201.04:13:27.71#ibcon#about to read 6, iclass 37, count 2 2006.201.04:13:27.71#ibcon#read 6, iclass 37, count 2 2006.201.04:13:27.71#ibcon#end of sib2, iclass 37, count 2 2006.201.04:13:27.71#ibcon#*after write, iclass 37, count 2 2006.201.04:13:27.71#ibcon#*before return 0, iclass 37, count 2 2006.201.04:13:27.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:27.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:13:27.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.04:13:27.71#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:27.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:27.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:27.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:27.83#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:13:27.83#ibcon#first serial, iclass 37, count 0 2006.201.04:13:27.83#ibcon#enter sib2, iclass 37, count 0 2006.201.04:13:27.83#ibcon#flushed, iclass 37, count 0 2006.201.04:13:27.83#ibcon#about to write, iclass 37, count 0 2006.201.04:13:27.83#ibcon#wrote, iclass 37, count 0 2006.201.04:13:27.83#ibcon#about to read 3, iclass 37, count 0 2006.201.04:13:27.85#ibcon#read 3, iclass 37, count 0 2006.201.04:13:27.85#ibcon#about to read 4, iclass 37, count 0 2006.201.04:13:27.85#ibcon#read 4, iclass 37, count 0 2006.201.04:13:27.85#ibcon#about to read 5, iclass 37, count 0 2006.201.04:13:27.85#ibcon#read 5, iclass 37, count 0 2006.201.04:13:27.85#ibcon#about to read 6, iclass 37, count 0 2006.201.04:13:27.85#ibcon#read 6, iclass 37, count 0 2006.201.04:13:27.85#ibcon#end of sib2, iclass 37, count 0 2006.201.04:13:27.85#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:13:27.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:13:27.85#ibcon#[27=USB\r\n] 2006.201.04:13:27.85#ibcon#*before write, iclass 37, count 0 2006.201.04:13:27.85#ibcon#enter sib2, iclass 37, count 0 2006.201.04:13:27.85#ibcon#flushed, iclass 37, count 0 2006.201.04:13:27.85#ibcon#about to write, iclass 37, count 0 2006.201.04:13:27.85#ibcon#wrote, iclass 37, count 0 2006.201.04:13:27.85#ibcon#about to read 3, iclass 37, count 0 2006.201.04:13:27.88#ibcon#read 3, iclass 37, count 0 2006.201.04:13:27.88#ibcon#about to read 4, iclass 37, count 0 2006.201.04:13:27.88#ibcon#read 4, iclass 37, count 0 2006.201.04:13:27.88#ibcon#about to read 5, iclass 37, count 0 2006.201.04:13:27.88#ibcon#read 5, iclass 37, count 0 2006.201.04:13:27.88#ibcon#about to read 6, iclass 37, count 0 2006.201.04:13:27.88#ibcon#read 6, iclass 37, count 0 2006.201.04:13:27.88#ibcon#end of sib2, iclass 37, count 0 2006.201.04:13:27.88#ibcon#*after write, iclass 37, count 0 2006.201.04:13:27.88#ibcon#*before return 0, iclass 37, count 0 2006.201.04:13:27.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:27.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:13:27.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:13:27.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:13:27.88$vck44/vblo=3,649.99 2006.201.04:13:27.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.04:13:27.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.04:13:27.88#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:27.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:27.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:27.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:27.88#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:13:27.88#ibcon#first serial, iclass 39, count 0 2006.201.04:13:27.88#ibcon#enter sib2, iclass 39, count 0 2006.201.04:13:27.88#ibcon#flushed, iclass 39, count 0 2006.201.04:13:27.88#ibcon#about to write, iclass 39, count 0 2006.201.04:13:27.88#ibcon#wrote, iclass 39, count 0 2006.201.04:13:27.88#ibcon#about to read 3, iclass 39, count 0 2006.201.04:13:27.90#ibcon#read 3, iclass 39, count 0 2006.201.04:13:27.90#ibcon#about to read 4, iclass 39, count 0 2006.201.04:13:27.90#ibcon#read 4, iclass 39, count 0 2006.201.04:13:27.90#ibcon#about to read 5, iclass 39, count 0 2006.201.04:13:27.90#ibcon#read 5, iclass 39, count 0 2006.201.04:13:27.90#ibcon#about to read 6, iclass 39, count 0 2006.201.04:13:27.90#ibcon#read 6, iclass 39, count 0 2006.201.04:13:27.90#ibcon#end of sib2, iclass 39, count 0 2006.201.04:13:27.90#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:13:27.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:13:27.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:13:27.90#ibcon#*before write, iclass 39, count 0 2006.201.04:13:27.90#ibcon#enter sib2, iclass 39, count 0 2006.201.04:13:27.90#ibcon#flushed, iclass 39, count 0 2006.201.04:13:27.90#ibcon#about to write, iclass 39, count 0 2006.201.04:13:27.90#ibcon#wrote, iclass 39, count 0 2006.201.04:13:27.90#ibcon#about to read 3, iclass 39, count 0 2006.201.04:13:27.94#ibcon#read 3, iclass 39, count 0 2006.201.04:13:27.94#ibcon#about to read 4, iclass 39, count 0 2006.201.04:13:27.94#ibcon#read 4, iclass 39, count 0 2006.201.04:13:27.94#ibcon#about to read 5, iclass 39, count 0 2006.201.04:13:27.94#ibcon#read 5, iclass 39, count 0 2006.201.04:13:27.94#ibcon#about to read 6, iclass 39, count 0 2006.201.04:13:27.94#ibcon#read 6, iclass 39, count 0 2006.201.04:13:27.94#ibcon#end of sib2, iclass 39, count 0 2006.201.04:13:27.94#ibcon#*after write, iclass 39, count 0 2006.201.04:13:27.94#ibcon#*before return 0, iclass 39, count 0 2006.201.04:13:27.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:27.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:13:27.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:13:27.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:13:27.94$vck44/vb=3,4 2006.201.04:13:27.94#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.04:13:27.94#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.04:13:27.94#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:27.94#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:28.00#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:28.00#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:28.00#ibcon#enter wrdev, iclass 2, count 2 2006.201.04:13:28.00#ibcon#first serial, iclass 2, count 2 2006.201.04:13:28.00#ibcon#enter sib2, iclass 2, count 2 2006.201.04:13:28.00#ibcon#flushed, iclass 2, count 2 2006.201.04:13:28.00#ibcon#about to write, iclass 2, count 2 2006.201.04:13:28.00#ibcon#wrote, iclass 2, count 2 2006.201.04:13:28.00#ibcon#about to read 3, iclass 2, count 2 2006.201.04:13:28.02#ibcon#read 3, iclass 2, count 2 2006.201.04:13:28.02#ibcon#about to read 4, iclass 2, count 2 2006.201.04:13:28.02#ibcon#read 4, iclass 2, count 2 2006.201.04:13:28.02#ibcon#about to read 5, iclass 2, count 2 2006.201.04:13:28.02#ibcon#read 5, iclass 2, count 2 2006.201.04:13:28.02#ibcon#about to read 6, iclass 2, count 2 2006.201.04:13:28.02#ibcon#read 6, iclass 2, count 2 2006.201.04:13:28.02#ibcon#end of sib2, iclass 2, count 2 2006.201.04:13:28.02#ibcon#*mode == 0, iclass 2, count 2 2006.201.04:13:28.02#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.04:13:28.02#ibcon#[27=AT03-04\r\n] 2006.201.04:13:28.02#ibcon#*before write, iclass 2, count 2 2006.201.04:13:28.02#ibcon#enter sib2, iclass 2, count 2 2006.201.04:13:28.02#ibcon#flushed, iclass 2, count 2 2006.201.04:13:28.02#ibcon#about to write, iclass 2, count 2 2006.201.04:13:28.02#ibcon#wrote, iclass 2, count 2 2006.201.04:13:28.02#ibcon#about to read 3, iclass 2, count 2 2006.201.04:13:28.05#ibcon#read 3, iclass 2, count 2 2006.201.04:13:28.05#ibcon#about to read 4, iclass 2, count 2 2006.201.04:13:28.05#ibcon#read 4, iclass 2, count 2 2006.201.04:13:28.05#ibcon#about to read 5, iclass 2, count 2 2006.201.04:13:28.05#ibcon#read 5, iclass 2, count 2 2006.201.04:13:28.05#ibcon#about to read 6, iclass 2, count 2 2006.201.04:13:28.05#ibcon#read 6, iclass 2, count 2 2006.201.04:13:28.05#ibcon#end of sib2, iclass 2, count 2 2006.201.04:13:28.05#ibcon#*after write, iclass 2, count 2 2006.201.04:13:28.05#ibcon#*before return 0, iclass 2, count 2 2006.201.04:13:28.05#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:28.05#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:13:28.05#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.04:13:28.05#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:28.05#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:28.17#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:28.17#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:28.17#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:13:28.17#ibcon#first serial, iclass 2, count 0 2006.201.04:13:28.17#ibcon#enter sib2, iclass 2, count 0 2006.201.04:13:28.17#ibcon#flushed, iclass 2, count 0 2006.201.04:13:28.17#ibcon#about to write, iclass 2, count 0 2006.201.04:13:28.17#ibcon#wrote, iclass 2, count 0 2006.201.04:13:28.17#ibcon#about to read 3, iclass 2, count 0 2006.201.04:13:28.19#ibcon#read 3, iclass 2, count 0 2006.201.04:13:28.19#ibcon#about to read 4, iclass 2, count 0 2006.201.04:13:28.19#ibcon#read 4, iclass 2, count 0 2006.201.04:13:28.19#ibcon#about to read 5, iclass 2, count 0 2006.201.04:13:28.19#ibcon#read 5, iclass 2, count 0 2006.201.04:13:28.19#ibcon#about to read 6, iclass 2, count 0 2006.201.04:13:28.19#ibcon#read 6, iclass 2, count 0 2006.201.04:13:28.19#ibcon#end of sib2, iclass 2, count 0 2006.201.04:13:28.19#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:13:28.19#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:13:28.19#ibcon#[27=USB\r\n] 2006.201.04:13:28.19#ibcon#*before write, iclass 2, count 0 2006.201.04:13:28.19#ibcon#enter sib2, iclass 2, count 0 2006.201.04:13:28.19#ibcon#flushed, iclass 2, count 0 2006.201.04:13:28.19#ibcon#about to write, iclass 2, count 0 2006.201.04:13:28.19#ibcon#wrote, iclass 2, count 0 2006.201.04:13:28.19#ibcon#about to read 3, iclass 2, count 0 2006.201.04:13:28.22#ibcon#read 3, iclass 2, count 0 2006.201.04:13:28.22#ibcon#about to read 4, iclass 2, count 0 2006.201.04:13:28.22#ibcon#read 4, iclass 2, count 0 2006.201.04:13:28.22#ibcon#about to read 5, iclass 2, count 0 2006.201.04:13:28.22#ibcon#read 5, iclass 2, count 0 2006.201.04:13:28.22#ibcon#about to read 6, iclass 2, count 0 2006.201.04:13:28.22#ibcon#read 6, iclass 2, count 0 2006.201.04:13:28.22#ibcon#end of sib2, iclass 2, count 0 2006.201.04:13:28.22#ibcon#*after write, iclass 2, count 0 2006.201.04:13:28.22#ibcon#*before return 0, iclass 2, count 0 2006.201.04:13:28.22#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:28.22#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:13:28.22#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:13:28.22#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:13:28.22$vck44/vblo=4,679.99 2006.201.04:13:28.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.04:13:28.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.04:13:28.22#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:28.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:28.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:28.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:28.22#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:13:28.22#ibcon#first serial, iclass 5, count 0 2006.201.04:13:28.22#ibcon#enter sib2, iclass 5, count 0 2006.201.04:13:28.22#ibcon#flushed, iclass 5, count 0 2006.201.04:13:28.22#ibcon#about to write, iclass 5, count 0 2006.201.04:13:28.22#ibcon#wrote, iclass 5, count 0 2006.201.04:13:28.22#ibcon#about to read 3, iclass 5, count 0 2006.201.04:13:28.24#ibcon#read 3, iclass 5, count 0 2006.201.04:13:28.24#ibcon#about to read 4, iclass 5, count 0 2006.201.04:13:28.24#ibcon#read 4, iclass 5, count 0 2006.201.04:13:28.24#ibcon#about to read 5, iclass 5, count 0 2006.201.04:13:28.24#ibcon#read 5, iclass 5, count 0 2006.201.04:13:28.24#ibcon#about to read 6, iclass 5, count 0 2006.201.04:13:28.24#ibcon#read 6, iclass 5, count 0 2006.201.04:13:28.24#ibcon#end of sib2, iclass 5, count 0 2006.201.04:13:28.24#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:13:28.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:13:28.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:13:28.24#ibcon#*before write, iclass 5, count 0 2006.201.04:13:28.24#ibcon#enter sib2, iclass 5, count 0 2006.201.04:13:28.24#ibcon#flushed, iclass 5, count 0 2006.201.04:13:28.24#ibcon#about to write, iclass 5, count 0 2006.201.04:13:28.24#ibcon#wrote, iclass 5, count 0 2006.201.04:13:28.24#ibcon#about to read 3, iclass 5, count 0 2006.201.04:13:28.28#ibcon#read 3, iclass 5, count 0 2006.201.04:13:28.28#ibcon#about to read 4, iclass 5, count 0 2006.201.04:13:28.28#ibcon#read 4, iclass 5, count 0 2006.201.04:13:28.28#ibcon#about to read 5, iclass 5, count 0 2006.201.04:13:28.28#ibcon#read 5, iclass 5, count 0 2006.201.04:13:28.28#ibcon#about to read 6, iclass 5, count 0 2006.201.04:13:28.28#ibcon#read 6, iclass 5, count 0 2006.201.04:13:28.28#ibcon#end of sib2, iclass 5, count 0 2006.201.04:13:28.28#ibcon#*after write, iclass 5, count 0 2006.201.04:13:28.28#ibcon#*before return 0, iclass 5, count 0 2006.201.04:13:28.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:28.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:13:28.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:13:28.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:13:28.28$vck44/vb=4,5 2006.201.04:13:28.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.04:13:28.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.04:13:28.28#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:28.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:28.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:28.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:28.34#ibcon#enter wrdev, iclass 7, count 2 2006.201.04:13:28.34#ibcon#first serial, iclass 7, count 2 2006.201.04:13:28.34#ibcon#enter sib2, iclass 7, count 2 2006.201.04:13:28.34#ibcon#flushed, iclass 7, count 2 2006.201.04:13:28.34#ibcon#about to write, iclass 7, count 2 2006.201.04:13:28.34#ibcon#wrote, iclass 7, count 2 2006.201.04:13:28.34#ibcon#about to read 3, iclass 7, count 2 2006.201.04:13:28.36#ibcon#read 3, iclass 7, count 2 2006.201.04:13:28.36#ibcon#about to read 4, iclass 7, count 2 2006.201.04:13:28.36#ibcon#read 4, iclass 7, count 2 2006.201.04:13:28.36#ibcon#about to read 5, iclass 7, count 2 2006.201.04:13:28.36#ibcon#read 5, iclass 7, count 2 2006.201.04:13:28.36#ibcon#about to read 6, iclass 7, count 2 2006.201.04:13:28.36#ibcon#read 6, iclass 7, count 2 2006.201.04:13:28.36#ibcon#end of sib2, iclass 7, count 2 2006.201.04:13:28.36#ibcon#*mode == 0, iclass 7, count 2 2006.201.04:13:28.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.04:13:28.36#ibcon#[27=AT04-05\r\n] 2006.201.04:13:28.36#ibcon#*before write, iclass 7, count 2 2006.201.04:13:28.36#ibcon#enter sib2, iclass 7, count 2 2006.201.04:13:28.36#ibcon#flushed, iclass 7, count 2 2006.201.04:13:28.36#ibcon#about to write, iclass 7, count 2 2006.201.04:13:28.36#ibcon#wrote, iclass 7, count 2 2006.201.04:13:28.36#ibcon#about to read 3, iclass 7, count 2 2006.201.04:13:28.39#ibcon#read 3, iclass 7, count 2 2006.201.04:13:28.39#ibcon#about to read 4, iclass 7, count 2 2006.201.04:13:28.39#ibcon#read 4, iclass 7, count 2 2006.201.04:13:28.39#ibcon#about to read 5, iclass 7, count 2 2006.201.04:13:28.39#ibcon#read 5, iclass 7, count 2 2006.201.04:13:28.39#ibcon#about to read 6, iclass 7, count 2 2006.201.04:13:28.39#ibcon#read 6, iclass 7, count 2 2006.201.04:13:28.39#ibcon#end of sib2, iclass 7, count 2 2006.201.04:13:28.39#ibcon#*after write, iclass 7, count 2 2006.201.04:13:28.39#ibcon#*before return 0, iclass 7, count 2 2006.201.04:13:28.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:28.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:13:28.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.04:13:28.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:28.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:28.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:28.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:28.51#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:13:28.51#ibcon#first serial, iclass 7, count 0 2006.201.04:13:28.51#ibcon#enter sib2, iclass 7, count 0 2006.201.04:13:28.51#ibcon#flushed, iclass 7, count 0 2006.201.04:13:28.51#ibcon#about to write, iclass 7, count 0 2006.201.04:13:28.51#ibcon#wrote, iclass 7, count 0 2006.201.04:13:28.51#ibcon#about to read 3, iclass 7, count 0 2006.201.04:13:28.53#ibcon#read 3, iclass 7, count 0 2006.201.04:13:28.53#ibcon#about to read 4, iclass 7, count 0 2006.201.04:13:28.53#ibcon#read 4, iclass 7, count 0 2006.201.04:13:28.53#ibcon#about to read 5, iclass 7, count 0 2006.201.04:13:28.53#ibcon#read 5, iclass 7, count 0 2006.201.04:13:28.53#ibcon#about to read 6, iclass 7, count 0 2006.201.04:13:28.53#ibcon#read 6, iclass 7, count 0 2006.201.04:13:28.53#ibcon#end of sib2, iclass 7, count 0 2006.201.04:13:28.53#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:13:28.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:13:28.53#ibcon#[27=USB\r\n] 2006.201.04:13:28.53#ibcon#*before write, iclass 7, count 0 2006.201.04:13:28.53#ibcon#enter sib2, iclass 7, count 0 2006.201.04:13:28.53#ibcon#flushed, iclass 7, count 0 2006.201.04:13:28.53#ibcon#about to write, iclass 7, count 0 2006.201.04:13:28.53#ibcon#wrote, iclass 7, count 0 2006.201.04:13:28.53#ibcon#about to read 3, iclass 7, count 0 2006.201.04:13:28.56#ibcon#read 3, iclass 7, count 0 2006.201.04:13:28.56#ibcon#about to read 4, iclass 7, count 0 2006.201.04:13:28.56#ibcon#read 4, iclass 7, count 0 2006.201.04:13:28.56#ibcon#about to read 5, iclass 7, count 0 2006.201.04:13:28.56#ibcon#read 5, iclass 7, count 0 2006.201.04:13:28.56#ibcon#about to read 6, iclass 7, count 0 2006.201.04:13:28.56#ibcon#read 6, iclass 7, count 0 2006.201.04:13:28.56#ibcon#end of sib2, iclass 7, count 0 2006.201.04:13:28.56#ibcon#*after write, iclass 7, count 0 2006.201.04:13:28.56#ibcon#*before return 0, iclass 7, count 0 2006.201.04:13:28.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:28.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:13:28.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:13:28.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:13:28.56$vck44/vblo=5,709.99 2006.201.04:13:28.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.04:13:28.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.04:13:28.56#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:28.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:28.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:28.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:28.56#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:13:28.56#ibcon#first serial, iclass 11, count 0 2006.201.04:13:28.56#ibcon#enter sib2, iclass 11, count 0 2006.201.04:13:28.56#ibcon#flushed, iclass 11, count 0 2006.201.04:13:28.56#ibcon#about to write, iclass 11, count 0 2006.201.04:13:28.56#ibcon#wrote, iclass 11, count 0 2006.201.04:13:28.56#ibcon#about to read 3, iclass 11, count 0 2006.201.04:13:28.58#ibcon#read 3, iclass 11, count 0 2006.201.04:13:28.58#ibcon#about to read 4, iclass 11, count 0 2006.201.04:13:28.58#ibcon#read 4, iclass 11, count 0 2006.201.04:13:28.58#ibcon#about to read 5, iclass 11, count 0 2006.201.04:13:28.58#ibcon#read 5, iclass 11, count 0 2006.201.04:13:28.58#ibcon#about to read 6, iclass 11, count 0 2006.201.04:13:28.58#ibcon#read 6, iclass 11, count 0 2006.201.04:13:28.58#ibcon#end of sib2, iclass 11, count 0 2006.201.04:13:28.58#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:13:28.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:13:28.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:13:28.58#ibcon#*before write, iclass 11, count 0 2006.201.04:13:28.58#ibcon#enter sib2, iclass 11, count 0 2006.201.04:13:28.58#ibcon#flushed, iclass 11, count 0 2006.201.04:13:28.58#ibcon#about to write, iclass 11, count 0 2006.201.04:13:28.58#ibcon#wrote, iclass 11, count 0 2006.201.04:13:28.58#ibcon#about to read 3, iclass 11, count 0 2006.201.04:13:28.62#ibcon#read 3, iclass 11, count 0 2006.201.04:13:28.62#ibcon#about to read 4, iclass 11, count 0 2006.201.04:13:28.62#ibcon#read 4, iclass 11, count 0 2006.201.04:13:28.62#ibcon#about to read 5, iclass 11, count 0 2006.201.04:13:28.62#ibcon#read 5, iclass 11, count 0 2006.201.04:13:28.62#ibcon#about to read 6, iclass 11, count 0 2006.201.04:13:28.62#ibcon#read 6, iclass 11, count 0 2006.201.04:13:28.62#ibcon#end of sib2, iclass 11, count 0 2006.201.04:13:28.62#ibcon#*after write, iclass 11, count 0 2006.201.04:13:28.62#ibcon#*before return 0, iclass 11, count 0 2006.201.04:13:28.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:28.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:13:28.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:13:28.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:13:28.62$vck44/vb=5,4 2006.201.04:13:28.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.04:13:28.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.04:13:28.62#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:28.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:28.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:28.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:28.68#ibcon#enter wrdev, iclass 13, count 2 2006.201.04:13:28.68#ibcon#first serial, iclass 13, count 2 2006.201.04:13:28.68#ibcon#enter sib2, iclass 13, count 2 2006.201.04:13:28.68#ibcon#flushed, iclass 13, count 2 2006.201.04:13:28.68#ibcon#about to write, iclass 13, count 2 2006.201.04:13:28.68#ibcon#wrote, iclass 13, count 2 2006.201.04:13:28.68#ibcon#about to read 3, iclass 13, count 2 2006.201.04:13:28.70#ibcon#read 3, iclass 13, count 2 2006.201.04:13:28.70#ibcon#about to read 4, iclass 13, count 2 2006.201.04:13:28.70#ibcon#read 4, iclass 13, count 2 2006.201.04:13:28.70#ibcon#about to read 5, iclass 13, count 2 2006.201.04:13:28.70#ibcon#read 5, iclass 13, count 2 2006.201.04:13:28.70#ibcon#about to read 6, iclass 13, count 2 2006.201.04:13:28.70#ibcon#read 6, iclass 13, count 2 2006.201.04:13:28.70#ibcon#end of sib2, iclass 13, count 2 2006.201.04:13:28.70#ibcon#*mode == 0, iclass 13, count 2 2006.201.04:13:28.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.04:13:28.70#ibcon#[27=AT05-04\r\n] 2006.201.04:13:28.70#ibcon#*before write, iclass 13, count 2 2006.201.04:13:28.70#ibcon#enter sib2, iclass 13, count 2 2006.201.04:13:28.70#ibcon#flushed, iclass 13, count 2 2006.201.04:13:28.70#ibcon#about to write, iclass 13, count 2 2006.201.04:13:28.70#ibcon#wrote, iclass 13, count 2 2006.201.04:13:28.70#ibcon#about to read 3, iclass 13, count 2 2006.201.04:13:28.73#ibcon#read 3, iclass 13, count 2 2006.201.04:13:28.73#ibcon#about to read 4, iclass 13, count 2 2006.201.04:13:28.73#ibcon#read 4, iclass 13, count 2 2006.201.04:13:28.73#ibcon#about to read 5, iclass 13, count 2 2006.201.04:13:28.73#ibcon#read 5, iclass 13, count 2 2006.201.04:13:28.73#ibcon#about to read 6, iclass 13, count 2 2006.201.04:13:28.73#ibcon#read 6, iclass 13, count 2 2006.201.04:13:28.73#ibcon#end of sib2, iclass 13, count 2 2006.201.04:13:28.73#ibcon#*after write, iclass 13, count 2 2006.201.04:13:28.73#ibcon#*before return 0, iclass 13, count 2 2006.201.04:13:28.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:28.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:13:28.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.04:13:28.73#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:28.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:28.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:28.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:28.85#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:13:28.85#ibcon#first serial, iclass 13, count 0 2006.201.04:13:28.85#ibcon#enter sib2, iclass 13, count 0 2006.201.04:13:28.85#ibcon#flushed, iclass 13, count 0 2006.201.04:13:28.85#ibcon#about to write, iclass 13, count 0 2006.201.04:13:28.85#ibcon#wrote, iclass 13, count 0 2006.201.04:13:28.85#ibcon#about to read 3, iclass 13, count 0 2006.201.04:13:28.87#ibcon#read 3, iclass 13, count 0 2006.201.04:13:28.87#ibcon#about to read 4, iclass 13, count 0 2006.201.04:13:28.87#ibcon#read 4, iclass 13, count 0 2006.201.04:13:28.87#ibcon#about to read 5, iclass 13, count 0 2006.201.04:13:28.87#ibcon#read 5, iclass 13, count 0 2006.201.04:13:28.87#ibcon#about to read 6, iclass 13, count 0 2006.201.04:13:28.87#ibcon#read 6, iclass 13, count 0 2006.201.04:13:28.87#ibcon#end of sib2, iclass 13, count 0 2006.201.04:13:28.87#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:13:28.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:13:28.87#ibcon#[27=USB\r\n] 2006.201.04:13:28.87#ibcon#*before write, iclass 13, count 0 2006.201.04:13:28.87#ibcon#enter sib2, iclass 13, count 0 2006.201.04:13:28.87#ibcon#flushed, iclass 13, count 0 2006.201.04:13:28.87#ibcon#about to write, iclass 13, count 0 2006.201.04:13:28.87#ibcon#wrote, iclass 13, count 0 2006.201.04:13:28.87#ibcon#about to read 3, iclass 13, count 0 2006.201.04:13:28.90#ibcon#read 3, iclass 13, count 0 2006.201.04:13:28.90#ibcon#about to read 4, iclass 13, count 0 2006.201.04:13:28.90#ibcon#read 4, iclass 13, count 0 2006.201.04:13:28.90#ibcon#about to read 5, iclass 13, count 0 2006.201.04:13:28.90#ibcon#read 5, iclass 13, count 0 2006.201.04:13:28.90#ibcon#about to read 6, iclass 13, count 0 2006.201.04:13:28.90#ibcon#read 6, iclass 13, count 0 2006.201.04:13:28.90#ibcon#end of sib2, iclass 13, count 0 2006.201.04:13:28.90#ibcon#*after write, iclass 13, count 0 2006.201.04:13:28.90#ibcon#*before return 0, iclass 13, count 0 2006.201.04:13:28.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:28.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:13:28.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:13:28.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:13:28.90$vck44/vblo=6,719.99 2006.201.04:13:28.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.04:13:28.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.04:13:28.90#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:28.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:28.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:28.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:28.90#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:13:28.90#ibcon#first serial, iclass 15, count 0 2006.201.04:13:28.90#ibcon#enter sib2, iclass 15, count 0 2006.201.04:13:28.90#ibcon#flushed, iclass 15, count 0 2006.201.04:13:28.90#ibcon#about to write, iclass 15, count 0 2006.201.04:13:28.90#ibcon#wrote, iclass 15, count 0 2006.201.04:13:28.90#ibcon#about to read 3, iclass 15, count 0 2006.201.04:13:28.92#ibcon#read 3, iclass 15, count 0 2006.201.04:13:28.92#ibcon#about to read 4, iclass 15, count 0 2006.201.04:13:28.92#ibcon#read 4, iclass 15, count 0 2006.201.04:13:28.92#ibcon#about to read 5, iclass 15, count 0 2006.201.04:13:28.92#ibcon#read 5, iclass 15, count 0 2006.201.04:13:28.92#ibcon#about to read 6, iclass 15, count 0 2006.201.04:13:28.92#ibcon#read 6, iclass 15, count 0 2006.201.04:13:28.92#ibcon#end of sib2, iclass 15, count 0 2006.201.04:13:28.92#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:13:28.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:13:28.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:13:28.92#ibcon#*before write, iclass 15, count 0 2006.201.04:13:28.92#ibcon#enter sib2, iclass 15, count 0 2006.201.04:13:28.92#ibcon#flushed, iclass 15, count 0 2006.201.04:13:28.92#ibcon#about to write, iclass 15, count 0 2006.201.04:13:28.92#ibcon#wrote, iclass 15, count 0 2006.201.04:13:28.92#ibcon#about to read 3, iclass 15, count 0 2006.201.04:13:28.96#ibcon#read 3, iclass 15, count 0 2006.201.04:13:28.96#ibcon#about to read 4, iclass 15, count 0 2006.201.04:13:28.96#ibcon#read 4, iclass 15, count 0 2006.201.04:13:28.96#ibcon#about to read 5, iclass 15, count 0 2006.201.04:13:28.96#ibcon#read 5, iclass 15, count 0 2006.201.04:13:28.96#ibcon#about to read 6, iclass 15, count 0 2006.201.04:13:28.96#ibcon#read 6, iclass 15, count 0 2006.201.04:13:28.96#ibcon#end of sib2, iclass 15, count 0 2006.201.04:13:28.96#ibcon#*after write, iclass 15, count 0 2006.201.04:13:28.96#ibcon#*before return 0, iclass 15, count 0 2006.201.04:13:28.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:28.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:13:28.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:13:28.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:13:28.96$vck44/vb=6,4 2006.201.04:13:28.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.04:13:28.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.04:13:28.96#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:28.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:29.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:29.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:29.02#ibcon#enter wrdev, iclass 17, count 2 2006.201.04:13:29.02#ibcon#first serial, iclass 17, count 2 2006.201.04:13:29.02#ibcon#enter sib2, iclass 17, count 2 2006.201.04:13:29.02#ibcon#flushed, iclass 17, count 2 2006.201.04:13:29.02#ibcon#about to write, iclass 17, count 2 2006.201.04:13:29.02#ibcon#wrote, iclass 17, count 2 2006.201.04:13:29.02#ibcon#about to read 3, iclass 17, count 2 2006.201.04:13:29.04#ibcon#read 3, iclass 17, count 2 2006.201.04:13:29.04#ibcon#about to read 4, iclass 17, count 2 2006.201.04:13:29.04#ibcon#read 4, iclass 17, count 2 2006.201.04:13:29.04#ibcon#about to read 5, iclass 17, count 2 2006.201.04:13:29.04#ibcon#read 5, iclass 17, count 2 2006.201.04:13:29.04#ibcon#about to read 6, iclass 17, count 2 2006.201.04:13:29.04#ibcon#read 6, iclass 17, count 2 2006.201.04:13:29.04#ibcon#end of sib2, iclass 17, count 2 2006.201.04:13:29.04#ibcon#*mode == 0, iclass 17, count 2 2006.201.04:13:29.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.04:13:29.04#ibcon#[27=AT06-04\r\n] 2006.201.04:13:29.04#ibcon#*before write, iclass 17, count 2 2006.201.04:13:29.04#ibcon#enter sib2, iclass 17, count 2 2006.201.04:13:29.04#ibcon#flushed, iclass 17, count 2 2006.201.04:13:29.04#ibcon#about to write, iclass 17, count 2 2006.201.04:13:29.04#ibcon#wrote, iclass 17, count 2 2006.201.04:13:29.04#ibcon#about to read 3, iclass 17, count 2 2006.201.04:13:29.07#ibcon#read 3, iclass 17, count 2 2006.201.04:13:29.07#ibcon#about to read 4, iclass 17, count 2 2006.201.04:13:29.07#ibcon#read 4, iclass 17, count 2 2006.201.04:13:29.07#ibcon#about to read 5, iclass 17, count 2 2006.201.04:13:29.07#ibcon#read 5, iclass 17, count 2 2006.201.04:13:29.07#ibcon#about to read 6, iclass 17, count 2 2006.201.04:13:29.07#ibcon#read 6, iclass 17, count 2 2006.201.04:13:29.07#ibcon#end of sib2, iclass 17, count 2 2006.201.04:13:29.07#ibcon#*after write, iclass 17, count 2 2006.201.04:13:29.07#ibcon#*before return 0, iclass 17, count 2 2006.201.04:13:29.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:29.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:13:29.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.04:13:29.07#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:29.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:29.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:29.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:29.19#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:13:29.19#ibcon#first serial, iclass 17, count 0 2006.201.04:13:29.19#ibcon#enter sib2, iclass 17, count 0 2006.201.04:13:29.19#ibcon#flushed, iclass 17, count 0 2006.201.04:13:29.19#ibcon#about to write, iclass 17, count 0 2006.201.04:13:29.19#ibcon#wrote, iclass 17, count 0 2006.201.04:13:29.19#ibcon#about to read 3, iclass 17, count 0 2006.201.04:13:29.21#ibcon#read 3, iclass 17, count 0 2006.201.04:13:29.21#ibcon#about to read 4, iclass 17, count 0 2006.201.04:13:29.21#ibcon#read 4, iclass 17, count 0 2006.201.04:13:29.21#ibcon#about to read 5, iclass 17, count 0 2006.201.04:13:29.21#ibcon#read 5, iclass 17, count 0 2006.201.04:13:29.21#ibcon#about to read 6, iclass 17, count 0 2006.201.04:13:29.21#ibcon#read 6, iclass 17, count 0 2006.201.04:13:29.21#ibcon#end of sib2, iclass 17, count 0 2006.201.04:13:29.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:13:29.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:13:29.21#ibcon#[27=USB\r\n] 2006.201.04:13:29.21#ibcon#*before write, iclass 17, count 0 2006.201.04:13:29.21#ibcon#enter sib2, iclass 17, count 0 2006.201.04:13:29.21#ibcon#flushed, iclass 17, count 0 2006.201.04:13:29.21#ibcon#about to write, iclass 17, count 0 2006.201.04:13:29.21#ibcon#wrote, iclass 17, count 0 2006.201.04:13:29.21#ibcon#about to read 3, iclass 17, count 0 2006.201.04:13:29.24#ibcon#read 3, iclass 17, count 0 2006.201.04:13:29.24#ibcon#about to read 4, iclass 17, count 0 2006.201.04:13:29.24#ibcon#read 4, iclass 17, count 0 2006.201.04:13:29.24#ibcon#about to read 5, iclass 17, count 0 2006.201.04:13:29.24#ibcon#read 5, iclass 17, count 0 2006.201.04:13:29.24#ibcon#about to read 6, iclass 17, count 0 2006.201.04:13:29.24#ibcon#read 6, iclass 17, count 0 2006.201.04:13:29.24#ibcon#end of sib2, iclass 17, count 0 2006.201.04:13:29.24#ibcon#*after write, iclass 17, count 0 2006.201.04:13:29.24#ibcon#*before return 0, iclass 17, count 0 2006.201.04:13:29.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:29.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:13:29.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:13:29.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:13:29.24$vck44/vblo=7,734.99 2006.201.04:13:29.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.04:13:29.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.04:13:29.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:29.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:29.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:29.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:29.24#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:13:29.24#ibcon#first serial, iclass 19, count 0 2006.201.04:13:29.24#ibcon#enter sib2, iclass 19, count 0 2006.201.04:13:29.24#ibcon#flushed, iclass 19, count 0 2006.201.04:13:29.24#ibcon#about to write, iclass 19, count 0 2006.201.04:13:29.24#ibcon#wrote, iclass 19, count 0 2006.201.04:13:29.24#ibcon#about to read 3, iclass 19, count 0 2006.201.04:13:29.26#ibcon#read 3, iclass 19, count 0 2006.201.04:13:29.26#ibcon#about to read 4, iclass 19, count 0 2006.201.04:13:29.26#ibcon#read 4, iclass 19, count 0 2006.201.04:13:29.26#ibcon#about to read 5, iclass 19, count 0 2006.201.04:13:29.26#ibcon#read 5, iclass 19, count 0 2006.201.04:13:29.26#ibcon#about to read 6, iclass 19, count 0 2006.201.04:13:29.26#ibcon#read 6, iclass 19, count 0 2006.201.04:13:29.26#ibcon#end of sib2, iclass 19, count 0 2006.201.04:13:29.26#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:13:29.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:13:29.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:13:29.26#ibcon#*before write, iclass 19, count 0 2006.201.04:13:29.26#ibcon#enter sib2, iclass 19, count 0 2006.201.04:13:29.26#ibcon#flushed, iclass 19, count 0 2006.201.04:13:29.26#ibcon#about to write, iclass 19, count 0 2006.201.04:13:29.26#ibcon#wrote, iclass 19, count 0 2006.201.04:13:29.26#ibcon#about to read 3, iclass 19, count 0 2006.201.04:13:29.30#ibcon#read 3, iclass 19, count 0 2006.201.04:13:29.30#ibcon#about to read 4, iclass 19, count 0 2006.201.04:13:29.30#ibcon#read 4, iclass 19, count 0 2006.201.04:13:29.30#ibcon#about to read 5, iclass 19, count 0 2006.201.04:13:29.30#ibcon#read 5, iclass 19, count 0 2006.201.04:13:29.30#ibcon#about to read 6, iclass 19, count 0 2006.201.04:13:29.30#ibcon#read 6, iclass 19, count 0 2006.201.04:13:29.30#ibcon#end of sib2, iclass 19, count 0 2006.201.04:13:29.30#ibcon#*after write, iclass 19, count 0 2006.201.04:13:29.30#ibcon#*before return 0, iclass 19, count 0 2006.201.04:13:29.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:29.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:13:29.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:13:29.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:13:29.30$vck44/vb=7,4 2006.201.04:13:29.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.04:13:29.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.04:13:29.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:29.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:29.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:29.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:29.36#ibcon#enter wrdev, iclass 21, count 2 2006.201.04:13:29.36#ibcon#first serial, iclass 21, count 2 2006.201.04:13:29.36#ibcon#enter sib2, iclass 21, count 2 2006.201.04:13:29.36#ibcon#flushed, iclass 21, count 2 2006.201.04:13:29.36#ibcon#about to write, iclass 21, count 2 2006.201.04:13:29.36#ibcon#wrote, iclass 21, count 2 2006.201.04:13:29.36#ibcon#about to read 3, iclass 21, count 2 2006.201.04:13:29.38#ibcon#read 3, iclass 21, count 2 2006.201.04:13:29.38#ibcon#about to read 4, iclass 21, count 2 2006.201.04:13:29.38#ibcon#read 4, iclass 21, count 2 2006.201.04:13:29.38#ibcon#about to read 5, iclass 21, count 2 2006.201.04:13:29.38#ibcon#read 5, iclass 21, count 2 2006.201.04:13:29.38#ibcon#about to read 6, iclass 21, count 2 2006.201.04:13:29.38#ibcon#read 6, iclass 21, count 2 2006.201.04:13:29.38#ibcon#end of sib2, iclass 21, count 2 2006.201.04:13:29.38#ibcon#*mode == 0, iclass 21, count 2 2006.201.04:13:29.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.04:13:29.38#ibcon#[27=AT07-04\r\n] 2006.201.04:13:29.38#ibcon#*before write, iclass 21, count 2 2006.201.04:13:29.38#ibcon#enter sib2, iclass 21, count 2 2006.201.04:13:29.38#ibcon#flushed, iclass 21, count 2 2006.201.04:13:29.38#ibcon#about to write, iclass 21, count 2 2006.201.04:13:29.38#ibcon#wrote, iclass 21, count 2 2006.201.04:13:29.38#ibcon#about to read 3, iclass 21, count 2 2006.201.04:13:29.41#ibcon#read 3, iclass 21, count 2 2006.201.04:13:29.41#ibcon#about to read 4, iclass 21, count 2 2006.201.04:13:29.41#ibcon#read 4, iclass 21, count 2 2006.201.04:13:29.41#ibcon#about to read 5, iclass 21, count 2 2006.201.04:13:29.41#ibcon#read 5, iclass 21, count 2 2006.201.04:13:29.41#ibcon#about to read 6, iclass 21, count 2 2006.201.04:13:29.41#ibcon#read 6, iclass 21, count 2 2006.201.04:13:29.41#ibcon#end of sib2, iclass 21, count 2 2006.201.04:13:29.41#ibcon#*after write, iclass 21, count 2 2006.201.04:13:29.41#ibcon#*before return 0, iclass 21, count 2 2006.201.04:13:29.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:29.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:13:29.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.04:13:29.41#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:29.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:29.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:29.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:29.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:13:29.53#ibcon#first serial, iclass 21, count 0 2006.201.04:13:29.53#ibcon#enter sib2, iclass 21, count 0 2006.201.04:13:29.53#ibcon#flushed, iclass 21, count 0 2006.201.04:13:29.53#ibcon#about to write, iclass 21, count 0 2006.201.04:13:29.53#ibcon#wrote, iclass 21, count 0 2006.201.04:13:29.53#ibcon#about to read 3, iclass 21, count 0 2006.201.04:13:29.55#ibcon#read 3, iclass 21, count 0 2006.201.04:13:29.55#ibcon#about to read 4, iclass 21, count 0 2006.201.04:13:29.55#ibcon#read 4, iclass 21, count 0 2006.201.04:13:29.55#ibcon#about to read 5, iclass 21, count 0 2006.201.04:13:29.55#ibcon#read 5, iclass 21, count 0 2006.201.04:13:29.55#ibcon#about to read 6, iclass 21, count 0 2006.201.04:13:29.55#ibcon#read 6, iclass 21, count 0 2006.201.04:13:29.55#ibcon#end of sib2, iclass 21, count 0 2006.201.04:13:29.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:13:29.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:13:29.55#ibcon#[27=USB\r\n] 2006.201.04:13:29.55#ibcon#*before write, iclass 21, count 0 2006.201.04:13:29.55#ibcon#enter sib2, iclass 21, count 0 2006.201.04:13:29.55#ibcon#flushed, iclass 21, count 0 2006.201.04:13:29.55#ibcon#about to write, iclass 21, count 0 2006.201.04:13:29.55#ibcon#wrote, iclass 21, count 0 2006.201.04:13:29.55#ibcon#about to read 3, iclass 21, count 0 2006.201.04:13:29.58#ibcon#read 3, iclass 21, count 0 2006.201.04:13:29.58#ibcon#about to read 4, iclass 21, count 0 2006.201.04:13:29.58#ibcon#read 4, iclass 21, count 0 2006.201.04:13:29.58#ibcon#about to read 5, iclass 21, count 0 2006.201.04:13:29.58#ibcon#read 5, iclass 21, count 0 2006.201.04:13:29.58#ibcon#about to read 6, iclass 21, count 0 2006.201.04:13:29.58#ibcon#read 6, iclass 21, count 0 2006.201.04:13:29.58#ibcon#end of sib2, iclass 21, count 0 2006.201.04:13:29.58#ibcon#*after write, iclass 21, count 0 2006.201.04:13:29.58#ibcon#*before return 0, iclass 21, count 0 2006.201.04:13:29.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:29.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:13:29.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:13:29.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:13:29.58$vck44/vblo=8,744.99 2006.201.04:13:29.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.04:13:29.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.04:13:29.58#ibcon#ireg 17 cls_cnt 0 2006.201.04:13:29.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:29.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:29.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:29.58#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:13:29.58#ibcon#first serial, iclass 23, count 0 2006.201.04:13:29.58#ibcon#enter sib2, iclass 23, count 0 2006.201.04:13:29.58#ibcon#flushed, iclass 23, count 0 2006.201.04:13:29.58#ibcon#about to write, iclass 23, count 0 2006.201.04:13:29.58#ibcon#wrote, iclass 23, count 0 2006.201.04:13:29.58#ibcon#about to read 3, iclass 23, count 0 2006.201.04:13:29.60#ibcon#read 3, iclass 23, count 0 2006.201.04:13:29.60#ibcon#about to read 4, iclass 23, count 0 2006.201.04:13:29.60#ibcon#read 4, iclass 23, count 0 2006.201.04:13:29.60#ibcon#about to read 5, iclass 23, count 0 2006.201.04:13:29.60#ibcon#read 5, iclass 23, count 0 2006.201.04:13:29.60#ibcon#about to read 6, iclass 23, count 0 2006.201.04:13:29.60#ibcon#read 6, iclass 23, count 0 2006.201.04:13:29.60#ibcon#end of sib2, iclass 23, count 0 2006.201.04:13:29.60#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:13:29.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:13:29.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:13:29.60#ibcon#*before write, iclass 23, count 0 2006.201.04:13:29.60#ibcon#enter sib2, iclass 23, count 0 2006.201.04:13:29.60#ibcon#flushed, iclass 23, count 0 2006.201.04:13:29.60#ibcon#about to write, iclass 23, count 0 2006.201.04:13:29.60#ibcon#wrote, iclass 23, count 0 2006.201.04:13:29.60#ibcon#about to read 3, iclass 23, count 0 2006.201.04:13:29.64#ibcon#read 3, iclass 23, count 0 2006.201.04:13:29.64#ibcon#about to read 4, iclass 23, count 0 2006.201.04:13:29.64#ibcon#read 4, iclass 23, count 0 2006.201.04:13:29.64#ibcon#about to read 5, iclass 23, count 0 2006.201.04:13:29.64#ibcon#read 5, iclass 23, count 0 2006.201.04:13:29.64#ibcon#about to read 6, iclass 23, count 0 2006.201.04:13:29.64#ibcon#read 6, iclass 23, count 0 2006.201.04:13:29.64#ibcon#end of sib2, iclass 23, count 0 2006.201.04:13:29.64#ibcon#*after write, iclass 23, count 0 2006.201.04:13:29.64#ibcon#*before return 0, iclass 23, count 0 2006.201.04:13:29.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:29.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:13:29.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:13:29.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:13:29.64$vck44/vb=8,4 2006.201.04:13:29.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.04:13:29.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.04:13:29.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:13:29.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:29.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:29.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:29.70#ibcon#enter wrdev, iclass 25, count 2 2006.201.04:13:29.70#ibcon#first serial, iclass 25, count 2 2006.201.04:13:29.70#ibcon#enter sib2, iclass 25, count 2 2006.201.04:13:29.70#ibcon#flushed, iclass 25, count 2 2006.201.04:13:29.70#ibcon#about to write, iclass 25, count 2 2006.201.04:13:29.70#ibcon#wrote, iclass 25, count 2 2006.201.04:13:29.70#ibcon#about to read 3, iclass 25, count 2 2006.201.04:13:29.72#ibcon#read 3, iclass 25, count 2 2006.201.04:13:29.72#ibcon#about to read 4, iclass 25, count 2 2006.201.04:13:29.72#ibcon#read 4, iclass 25, count 2 2006.201.04:13:29.72#ibcon#about to read 5, iclass 25, count 2 2006.201.04:13:29.72#ibcon#read 5, iclass 25, count 2 2006.201.04:13:29.72#ibcon#about to read 6, iclass 25, count 2 2006.201.04:13:29.72#ibcon#read 6, iclass 25, count 2 2006.201.04:13:29.72#ibcon#end of sib2, iclass 25, count 2 2006.201.04:13:29.72#ibcon#*mode == 0, iclass 25, count 2 2006.201.04:13:29.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.04:13:29.72#ibcon#[27=AT08-04\r\n] 2006.201.04:13:29.72#ibcon#*before write, iclass 25, count 2 2006.201.04:13:29.72#ibcon#enter sib2, iclass 25, count 2 2006.201.04:13:29.72#ibcon#flushed, iclass 25, count 2 2006.201.04:13:29.72#ibcon#about to write, iclass 25, count 2 2006.201.04:13:29.72#ibcon#wrote, iclass 25, count 2 2006.201.04:13:29.72#ibcon#about to read 3, iclass 25, count 2 2006.201.04:13:29.75#ibcon#read 3, iclass 25, count 2 2006.201.04:13:29.75#ibcon#about to read 4, iclass 25, count 2 2006.201.04:13:29.75#ibcon#read 4, iclass 25, count 2 2006.201.04:13:29.75#ibcon#about to read 5, iclass 25, count 2 2006.201.04:13:29.75#ibcon#read 5, iclass 25, count 2 2006.201.04:13:29.75#ibcon#about to read 6, iclass 25, count 2 2006.201.04:13:29.75#ibcon#read 6, iclass 25, count 2 2006.201.04:13:29.75#ibcon#end of sib2, iclass 25, count 2 2006.201.04:13:29.75#ibcon#*after write, iclass 25, count 2 2006.201.04:13:29.75#ibcon#*before return 0, iclass 25, count 2 2006.201.04:13:29.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:29.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:13:29.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.04:13:29.75#ibcon#ireg 7 cls_cnt 0 2006.201.04:13:29.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:29.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:29.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:29.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:13:29.87#ibcon#first serial, iclass 25, count 0 2006.201.04:13:29.87#ibcon#enter sib2, iclass 25, count 0 2006.201.04:13:29.87#ibcon#flushed, iclass 25, count 0 2006.201.04:13:29.87#ibcon#about to write, iclass 25, count 0 2006.201.04:13:29.87#ibcon#wrote, iclass 25, count 0 2006.201.04:13:29.87#ibcon#about to read 3, iclass 25, count 0 2006.201.04:13:29.89#ibcon#read 3, iclass 25, count 0 2006.201.04:13:29.89#ibcon#about to read 4, iclass 25, count 0 2006.201.04:13:29.89#ibcon#read 4, iclass 25, count 0 2006.201.04:13:29.89#ibcon#about to read 5, iclass 25, count 0 2006.201.04:13:29.89#ibcon#read 5, iclass 25, count 0 2006.201.04:13:29.89#ibcon#about to read 6, iclass 25, count 0 2006.201.04:13:29.89#ibcon#read 6, iclass 25, count 0 2006.201.04:13:29.89#ibcon#end of sib2, iclass 25, count 0 2006.201.04:13:29.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:13:29.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:13:29.89#ibcon#[27=USB\r\n] 2006.201.04:13:29.89#ibcon#*before write, iclass 25, count 0 2006.201.04:13:29.89#ibcon#enter sib2, iclass 25, count 0 2006.201.04:13:29.89#ibcon#flushed, iclass 25, count 0 2006.201.04:13:29.89#ibcon#about to write, iclass 25, count 0 2006.201.04:13:29.89#ibcon#wrote, iclass 25, count 0 2006.201.04:13:29.89#ibcon#about to read 3, iclass 25, count 0 2006.201.04:13:29.92#ibcon#read 3, iclass 25, count 0 2006.201.04:13:29.92#ibcon#about to read 4, iclass 25, count 0 2006.201.04:13:29.92#ibcon#read 4, iclass 25, count 0 2006.201.04:13:29.92#ibcon#about to read 5, iclass 25, count 0 2006.201.04:13:29.92#ibcon#read 5, iclass 25, count 0 2006.201.04:13:29.92#ibcon#about to read 6, iclass 25, count 0 2006.201.04:13:29.92#ibcon#read 6, iclass 25, count 0 2006.201.04:13:29.92#ibcon#end of sib2, iclass 25, count 0 2006.201.04:13:29.92#ibcon#*after write, iclass 25, count 0 2006.201.04:13:29.92#ibcon#*before return 0, iclass 25, count 0 2006.201.04:13:29.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:29.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:13:29.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:13:29.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:13:29.92$vck44/vabw=wide 2006.201.04:13:29.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.04:13:29.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.04:13:29.92#ibcon#ireg 8 cls_cnt 0 2006.201.04:13:29.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:29.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:29.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:29.92#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:13:29.92#ibcon#first serial, iclass 27, count 0 2006.201.04:13:29.92#ibcon#enter sib2, iclass 27, count 0 2006.201.04:13:29.92#ibcon#flushed, iclass 27, count 0 2006.201.04:13:29.92#ibcon#about to write, iclass 27, count 0 2006.201.04:13:29.92#ibcon#wrote, iclass 27, count 0 2006.201.04:13:29.92#ibcon#about to read 3, iclass 27, count 0 2006.201.04:13:29.94#ibcon#read 3, iclass 27, count 0 2006.201.04:13:29.94#ibcon#about to read 4, iclass 27, count 0 2006.201.04:13:29.94#ibcon#read 4, iclass 27, count 0 2006.201.04:13:29.94#ibcon#about to read 5, iclass 27, count 0 2006.201.04:13:29.94#ibcon#read 5, iclass 27, count 0 2006.201.04:13:29.94#ibcon#about to read 6, iclass 27, count 0 2006.201.04:13:29.94#ibcon#read 6, iclass 27, count 0 2006.201.04:13:29.94#ibcon#end of sib2, iclass 27, count 0 2006.201.04:13:29.94#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:13:29.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:13:29.94#ibcon#[25=BW32\r\n] 2006.201.04:13:29.94#ibcon#*before write, iclass 27, count 0 2006.201.04:13:29.94#ibcon#enter sib2, iclass 27, count 0 2006.201.04:13:29.94#ibcon#flushed, iclass 27, count 0 2006.201.04:13:29.94#ibcon#about to write, iclass 27, count 0 2006.201.04:13:29.94#ibcon#wrote, iclass 27, count 0 2006.201.04:13:29.94#ibcon#about to read 3, iclass 27, count 0 2006.201.04:13:29.97#ibcon#read 3, iclass 27, count 0 2006.201.04:13:29.97#ibcon#about to read 4, iclass 27, count 0 2006.201.04:13:29.97#ibcon#read 4, iclass 27, count 0 2006.201.04:13:29.97#ibcon#about to read 5, iclass 27, count 0 2006.201.04:13:29.97#ibcon#read 5, iclass 27, count 0 2006.201.04:13:29.97#ibcon#about to read 6, iclass 27, count 0 2006.201.04:13:29.97#ibcon#read 6, iclass 27, count 0 2006.201.04:13:29.97#ibcon#end of sib2, iclass 27, count 0 2006.201.04:13:29.97#ibcon#*after write, iclass 27, count 0 2006.201.04:13:29.97#ibcon#*before return 0, iclass 27, count 0 2006.201.04:13:29.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:29.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:13:29.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:13:29.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:13:29.97$vck44/vbbw=wide 2006.201.04:13:29.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.04:13:29.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.04:13:29.97#ibcon#ireg 8 cls_cnt 0 2006.201.04:13:29.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:13:30.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:13:30.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:13:30.04#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:13:30.04#ibcon#first serial, iclass 29, count 0 2006.201.04:13:30.04#ibcon#enter sib2, iclass 29, count 0 2006.201.04:13:30.04#ibcon#flushed, iclass 29, count 0 2006.201.04:13:30.04#ibcon#about to write, iclass 29, count 0 2006.201.04:13:30.04#ibcon#wrote, iclass 29, count 0 2006.201.04:13:30.04#ibcon#about to read 3, iclass 29, count 0 2006.201.04:13:30.06#ibcon#read 3, iclass 29, count 0 2006.201.04:13:30.06#ibcon#about to read 4, iclass 29, count 0 2006.201.04:13:30.06#ibcon#read 4, iclass 29, count 0 2006.201.04:13:30.06#ibcon#about to read 5, iclass 29, count 0 2006.201.04:13:30.06#ibcon#read 5, iclass 29, count 0 2006.201.04:13:30.06#ibcon#about to read 6, iclass 29, count 0 2006.201.04:13:30.06#ibcon#read 6, iclass 29, count 0 2006.201.04:13:30.06#ibcon#end of sib2, iclass 29, count 0 2006.201.04:13:30.06#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:13:30.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:13:30.06#ibcon#[27=BW32\r\n] 2006.201.04:13:30.06#ibcon#*before write, iclass 29, count 0 2006.201.04:13:30.06#ibcon#enter sib2, iclass 29, count 0 2006.201.04:13:30.06#ibcon#flushed, iclass 29, count 0 2006.201.04:13:30.06#ibcon#about to write, iclass 29, count 0 2006.201.04:13:30.06#ibcon#wrote, iclass 29, count 0 2006.201.04:13:30.06#ibcon#about to read 3, iclass 29, count 0 2006.201.04:13:30.09#ibcon#read 3, iclass 29, count 0 2006.201.04:13:30.09#ibcon#about to read 4, iclass 29, count 0 2006.201.04:13:30.09#ibcon#read 4, iclass 29, count 0 2006.201.04:13:30.09#ibcon#about to read 5, iclass 29, count 0 2006.201.04:13:30.09#ibcon#read 5, iclass 29, count 0 2006.201.04:13:30.09#ibcon#about to read 6, iclass 29, count 0 2006.201.04:13:30.09#ibcon#read 6, iclass 29, count 0 2006.201.04:13:30.09#ibcon#end of sib2, iclass 29, count 0 2006.201.04:13:30.09#ibcon#*after write, iclass 29, count 0 2006.201.04:13:30.09#ibcon#*before return 0, iclass 29, count 0 2006.201.04:13:30.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:13:30.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:13:30.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:13:30.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:13:30.09$setupk4/ifdk4 2006.201.04:13:30.09$ifdk4/lo= 2006.201.04:13:30.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:13:30.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:13:30.09$ifdk4/patch= 2006.201.04:13:30.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:13:30.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:13:30.09$setupk4/!*+20s 2006.201.04:13:31.40#abcon#<5=/05 2.3 4.4 23.03 911004.1\r\n> 2006.201.04:13:31.42#abcon#{5=INTERFACE CLEAR} 2006.201.04:13:31.48#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:13:41.57#abcon#<5=/05 2.3 4.2 23.04 911004.1\r\n> 2006.201.04:13:41.59#abcon#{5=INTERFACE CLEAR} 2006.201.04:13:41.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:13:44.60$setupk4/"tpicd 2006.201.04:13:44.60$setupk4/echo=off 2006.201.04:13:44.60$setupk4/xlog=off 2006.201.04:13:44.60:!2006.201.04:22:21 2006.201.04:14:02.13#trakl#Source acquired 2006.201.04:14:02.13#flagr#flagr/antenna,acquired 2006.201.04:22:21.00:preob 2006.201.04:22:21.13/onsource/TRACKING 2006.201.04:22:21.13:!2006.201.04:22:31 2006.201.04:22:31.00:"tape 2006.201.04:22:31.00:"st=record 2006.201.04:22:31.00:data_valid=on 2006.201.04:22:31.00:midob 2006.201.04:22:32.13/onsource/TRACKING 2006.201.04:22:32.13/wx/23.00,1004.1,90 2006.201.04:22:32.23/cable/+6.4662E-03 2006.201.04:22:33.32/va/01,08,usb,yes,31,34 2006.201.04:22:33.32/va/02,07,usb,yes,34,35 2006.201.04:22:33.32/va/03,08,usb,yes,31,32 2006.201.04:22:33.32/va/04,07,usb,yes,35,37 2006.201.04:22:33.32/va/05,04,usb,yes,31,31 2006.201.04:22:33.32/va/06,05,usb,yes,31,31 2006.201.04:22:33.32/va/07,05,usb,yes,30,31 2006.201.04:22:33.32/va/08,04,usb,yes,30,36 2006.201.04:22:33.55/valo/01,524.99,yes,locked 2006.201.04:22:33.55/valo/02,534.99,yes,locked 2006.201.04:22:33.55/valo/03,564.99,yes,locked 2006.201.04:22:33.55/valo/04,624.99,yes,locked 2006.201.04:22:33.55/valo/05,734.99,yes,locked 2006.201.04:22:33.55/valo/06,814.99,yes,locked 2006.201.04:22:33.55/valo/07,864.99,yes,locked 2006.201.04:22:33.55/valo/08,884.99,yes,locked 2006.201.04:22:34.64/vb/01,04,usb,yes,30,28 2006.201.04:22:34.64/vb/02,05,usb,yes,28,28 2006.201.04:22:34.64/vb/03,04,usb,yes,29,32 2006.201.04:22:34.64/vb/04,05,usb,yes,30,29 2006.201.04:22:34.64/vb/05,04,usb,yes,26,29 2006.201.04:22:34.64/vb/06,04,usb,yes,31,27 2006.201.04:22:34.64/vb/07,04,usb,yes,31,31 2006.201.04:22:34.64/vb/08,04,usb,yes,28,32 2006.201.04:22:34.88/vblo/01,629.99,yes,locked 2006.201.04:22:34.88/vblo/02,634.99,yes,locked 2006.201.04:22:34.88/vblo/03,649.99,yes,locked 2006.201.04:22:34.88/vblo/04,679.99,yes,locked 2006.201.04:22:34.88/vblo/05,709.99,yes,locked 2006.201.04:22:34.88/vblo/06,719.99,yes,locked 2006.201.04:22:34.88/vblo/07,734.99,yes,locked 2006.201.04:22:34.88/vblo/08,744.99,yes,locked 2006.201.04:22:35.03/vabw/8 2006.201.04:22:35.18/vbbw/8 2006.201.04:22:35.27/xfe/off,on,15.2 2006.201.04:22:35.66/ifatt/23,28,28,28 2006.201.04:22:36.05/fmout-gps/S +4.56E-07 2006.201.04:22:36.09:!2006.201.04:24:41 2006.201.04:24:41.00:data_valid=off 2006.201.04:24:41.00:"et 2006.201.04:24:41.00:!+3s 2006.201.04:24:44.01:"tape 2006.201.04:24:44.01:postob 2006.201.04:24:44.08/cable/+6.4651E-03 2006.201.04:24:44.08/wx/22.99,1004.1,90 2006.201.04:24:44.14/fmout-gps/S +4.56E-07 2006.201.04:24:44.14:scan_name=201-0427,jd0607,90 2006.201.04:24:44.14:source=3c274,123049.42,122328.0,2000.0,cw 2006.201.04:24:46.14#flagr#flagr/antenna,new-source 2006.201.04:24:46.14:checkk5 2006.201.04:24:46.49/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:24:46.85/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:24:47.20/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:24:47.55/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:24:47.88/chk_obsdata//k5ts1/T2010422??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.04:24:48.24/chk_obsdata//k5ts2/T2010422??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.04:24:48.58/chk_obsdata//k5ts3/T2010422??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.04:24:48.92/chk_obsdata//k5ts4/T2010422??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.04:24:49.58/k5log//k5ts1_log_newline 2006.201.04:24:50.24/k5log//k5ts2_log_newline 2006.201.04:24:50.90/k5log//k5ts3_log_newline 2006.201.04:24:51.56/k5log//k5ts4_log_newline 2006.201.04:24:51.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:24:51.58:setupk4=1 2006.201.04:24:51.58$setupk4/echo=on 2006.201.04:24:51.58$setupk4/pcalon 2006.201.04:24:51.58$pcalon/"no phase cal control is implemented here 2006.201.04:24:51.58$setupk4/"tpicd=stop 2006.201.04:24:51.58$setupk4/"rec=synch_on 2006.201.04:24:51.58$setupk4/"rec_mode=128 2006.201.04:24:51.58$setupk4/!* 2006.201.04:24:51.58$setupk4/recpk4 2006.201.04:24:51.58$recpk4/recpatch= 2006.201.04:24:51.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:24:51.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:24:51.59$setupk4/vck44 2006.201.04:24:51.59$vck44/valo=1,524.99 2006.201.04:24:51.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.04:24:51.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.04:24:51.59#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:51.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:51.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:51.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:51.59#ibcon#enter wrdev, iclass 40, count 0 2006.201.04:24:51.59#ibcon#first serial, iclass 40, count 0 2006.201.04:24:51.59#ibcon#enter sib2, iclass 40, count 0 2006.201.04:24:51.59#ibcon#flushed, iclass 40, count 0 2006.201.04:24:51.59#ibcon#about to write, iclass 40, count 0 2006.201.04:24:51.59#ibcon#wrote, iclass 40, count 0 2006.201.04:24:51.59#ibcon#about to read 3, iclass 40, count 0 2006.201.04:24:51.61#ibcon#read 3, iclass 40, count 0 2006.201.04:24:51.61#ibcon#about to read 4, iclass 40, count 0 2006.201.04:24:51.61#ibcon#read 4, iclass 40, count 0 2006.201.04:24:51.61#ibcon#about to read 5, iclass 40, count 0 2006.201.04:24:51.61#ibcon#read 5, iclass 40, count 0 2006.201.04:24:51.61#ibcon#about to read 6, iclass 40, count 0 2006.201.04:24:51.61#ibcon#read 6, iclass 40, count 0 2006.201.04:24:51.61#ibcon#end of sib2, iclass 40, count 0 2006.201.04:24:51.61#ibcon#*mode == 0, iclass 40, count 0 2006.201.04:24:51.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.04:24:51.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:24:51.61#ibcon#*before write, iclass 40, count 0 2006.201.04:24:51.61#ibcon#enter sib2, iclass 40, count 0 2006.201.04:24:51.61#ibcon#flushed, iclass 40, count 0 2006.201.04:24:51.61#ibcon#about to write, iclass 40, count 0 2006.201.04:24:51.61#ibcon#wrote, iclass 40, count 0 2006.201.04:24:51.61#ibcon#about to read 3, iclass 40, count 0 2006.201.04:24:51.66#ibcon#read 3, iclass 40, count 0 2006.201.04:24:51.66#ibcon#about to read 4, iclass 40, count 0 2006.201.04:24:51.66#ibcon#read 4, iclass 40, count 0 2006.201.04:24:51.66#ibcon#about to read 5, iclass 40, count 0 2006.201.04:24:51.66#ibcon#read 5, iclass 40, count 0 2006.201.04:24:51.66#ibcon#about to read 6, iclass 40, count 0 2006.201.04:24:51.66#ibcon#read 6, iclass 40, count 0 2006.201.04:24:51.66#ibcon#end of sib2, iclass 40, count 0 2006.201.04:24:51.66#ibcon#*after write, iclass 40, count 0 2006.201.04:24:51.66#ibcon#*before return 0, iclass 40, count 0 2006.201.04:24:51.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:51.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:51.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.04:24:51.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.04:24:51.66$vck44/va=1,8 2006.201.04:24:51.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.04:24:51.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.04:24:51.66#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:51.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:51.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:51.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:51.66#ibcon#enter wrdev, iclass 4, count 2 2006.201.04:24:51.66#ibcon#first serial, iclass 4, count 2 2006.201.04:24:51.66#ibcon#enter sib2, iclass 4, count 2 2006.201.04:24:51.66#ibcon#flushed, iclass 4, count 2 2006.201.04:24:51.66#ibcon#about to write, iclass 4, count 2 2006.201.04:24:51.66#ibcon#wrote, iclass 4, count 2 2006.201.04:24:51.66#ibcon#about to read 3, iclass 4, count 2 2006.201.04:24:51.68#ibcon#read 3, iclass 4, count 2 2006.201.04:24:51.68#ibcon#about to read 4, iclass 4, count 2 2006.201.04:24:51.68#ibcon#read 4, iclass 4, count 2 2006.201.04:24:51.68#ibcon#about to read 5, iclass 4, count 2 2006.201.04:24:51.68#ibcon#read 5, iclass 4, count 2 2006.201.04:24:51.68#ibcon#about to read 6, iclass 4, count 2 2006.201.04:24:51.68#ibcon#read 6, iclass 4, count 2 2006.201.04:24:51.68#ibcon#end of sib2, iclass 4, count 2 2006.201.04:24:51.68#ibcon#*mode == 0, iclass 4, count 2 2006.201.04:24:51.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.04:24:51.68#ibcon#[25=AT01-08\r\n] 2006.201.04:24:51.68#ibcon#*before write, iclass 4, count 2 2006.201.04:24:51.68#ibcon#enter sib2, iclass 4, count 2 2006.201.04:24:51.68#ibcon#flushed, iclass 4, count 2 2006.201.04:24:51.68#ibcon#about to write, iclass 4, count 2 2006.201.04:24:51.68#ibcon#wrote, iclass 4, count 2 2006.201.04:24:51.68#ibcon#about to read 3, iclass 4, count 2 2006.201.04:24:51.71#ibcon#read 3, iclass 4, count 2 2006.201.04:24:51.71#ibcon#about to read 4, iclass 4, count 2 2006.201.04:24:51.71#ibcon#read 4, iclass 4, count 2 2006.201.04:24:51.71#ibcon#about to read 5, iclass 4, count 2 2006.201.04:24:51.71#ibcon#read 5, iclass 4, count 2 2006.201.04:24:51.71#ibcon#about to read 6, iclass 4, count 2 2006.201.04:24:51.71#ibcon#read 6, iclass 4, count 2 2006.201.04:24:51.71#ibcon#end of sib2, iclass 4, count 2 2006.201.04:24:51.71#ibcon#*after write, iclass 4, count 2 2006.201.04:24:51.71#ibcon#*before return 0, iclass 4, count 2 2006.201.04:24:51.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:51.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:51.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.04:24:51.71#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:51.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:51.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:51.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:51.83#ibcon#enter wrdev, iclass 4, count 0 2006.201.04:24:51.83#ibcon#first serial, iclass 4, count 0 2006.201.04:24:51.83#ibcon#enter sib2, iclass 4, count 0 2006.201.04:24:51.83#ibcon#flushed, iclass 4, count 0 2006.201.04:24:51.83#ibcon#about to write, iclass 4, count 0 2006.201.04:24:51.83#ibcon#wrote, iclass 4, count 0 2006.201.04:24:51.83#ibcon#about to read 3, iclass 4, count 0 2006.201.04:24:51.85#ibcon#read 3, iclass 4, count 0 2006.201.04:24:51.85#ibcon#about to read 4, iclass 4, count 0 2006.201.04:24:51.85#ibcon#read 4, iclass 4, count 0 2006.201.04:24:51.85#ibcon#about to read 5, iclass 4, count 0 2006.201.04:24:51.85#ibcon#read 5, iclass 4, count 0 2006.201.04:24:51.85#ibcon#about to read 6, iclass 4, count 0 2006.201.04:24:51.85#ibcon#read 6, iclass 4, count 0 2006.201.04:24:51.85#ibcon#end of sib2, iclass 4, count 0 2006.201.04:24:51.85#ibcon#*mode == 0, iclass 4, count 0 2006.201.04:24:51.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.04:24:51.85#ibcon#[25=USB\r\n] 2006.201.04:24:51.85#ibcon#*before write, iclass 4, count 0 2006.201.04:24:51.85#ibcon#enter sib2, iclass 4, count 0 2006.201.04:24:51.85#ibcon#flushed, iclass 4, count 0 2006.201.04:24:51.85#ibcon#about to write, iclass 4, count 0 2006.201.04:24:51.85#ibcon#wrote, iclass 4, count 0 2006.201.04:24:51.85#ibcon#about to read 3, iclass 4, count 0 2006.201.04:24:51.88#ibcon#read 3, iclass 4, count 0 2006.201.04:24:51.88#ibcon#about to read 4, iclass 4, count 0 2006.201.04:24:51.88#ibcon#read 4, iclass 4, count 0 2006.201.04:24:51.88#ibcon#about to read 5, iclass 4, count 0 2006.201.04:24:51.88#ibcon#read 5, iclass 4, count 0 2006.201.04:24:51.88#ibcon#about to read 6, iclass 4, count 0 2006.201.04:24:51.88#ibcon#read 6, iclass 4, count 0 2006.201.04:24:51.88#ibcon#end of sib2, iclass 4, count 0 2006.201.04:24:51.88#ibcon#*after write, iclass 4, count 0 2006.201.04:24:51.88#ibcon#*before return 0, iclass 4, count 0 2006.201.04:24:51.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:51.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:51.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.04:24:51.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.04:24:51.88$vck44/valo=2,534.99 2006.201.04:24:51.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.04:24:51.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.04:24:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:51.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:51.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:51.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:51.88#ibcon#enter wrdev, iclass 6, count 0 2006.201.04:24:51.88#ibcon#first serial, iclass 6, count 0 2006.201.04:24:51.88#ibcon#enter sib2, iclass 6, count 0 2006.201.04:24:51.88#ibcon#flushed, iclass 6, count 0 2006.201.04:24:51.88#ibcon#about to write, iclass 6, count 0 2006.201.04:24:51.88#ibcon#wrote, iclass 6, count 0 2006.201.04:24:51.88#ibcon#about to read 3, iclass 6, count 0 2006.201.04:24:51.90#ibcon#read 3, iclass 6, count 0 2006.201.04:24:51.90#ibcon#about to read 4, iclass 6, count 0 2006.201.04:24:51.90#ibcon#read 4, iclass 6, count 0 2006.201.04:24:51.90#ibcon#about to read 5, iclass 6, count 0 2006.201.04:24:51.90#ibcon#read 5, iclass 6, count 0 2006.201.04:24:51.90#ibcon#about to read 6, iclass 6, count 0 2006.201.04:24:51.90#ibcon#read 6, iclass 6, count 0 2006.201.04:24:51.90#ibcon#end of sib2, iclass 6, count 0 2006.201.04:24:51.90#ibcon#*mode == 0, iclass 6, count 0 2006.201.04:24:51.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.04:24:51.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:24:51.90#ibcon#*before write, iclass 6, count 0 2006.201.04:24:51.90#ibcon#enter sib2, iclass 6, count 0 2006.201.04:24:51.90#ibcon#flushed, iclass 6, count 0 2006.201.04:24:51.90#ibcon#about to write, iclass 6, count 0 2006.201.04:24:51.90#ibcon#wrote, iclass 6, count 0 2006.201.04:24:51.90#ibcon#about to read 3, iclass 6, count 0 2006.201.04:24:51.94#ibcon#read 3, iclass 6, count 0 2006.201.04:24:51.94#ibcon#about to read 4, iclass 6, count 0 2006.201.04:24:51.94#ibcon#read 4, iclass 6, count 0 2006.201.04:24:51.94#ibcon#about to read 5, iclass 6, count 0 2006.201.04:24:51.94#ibcon#read 5, iclass 6, count 0 2006.201.04:24:51.94#ibcon#about to read 6, iclass 6, count 0 2006.201.04:24:51.94#ibcon#read 6, iclass 6, count 0 2006.201.04:24:51.94#ibcon#end of sib2, iclass 6, count 0 2006.201.04:24:51.94#ibcon#*after write, iclass 6, count 0 2006.201.04:24:51.94#ibcon#*before return 0, iclass 6, count 0 2006.201.04:24:51.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:51.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:51.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.04:24:51.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.04:24:51.94$vck44/va=2,7 2006.201.04:24:51.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.04:24:51.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.04:24:51.94#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:51.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:52.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:52.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:52.00#ibcon#enter wrdev, iclass 10, count 2 2006.201.04:24:52.00#ibcon#first serial, iclass 10, count 2 2006.201.04:24:52.00#ibcon#enter sib2, iclass 10, count 2 2006.201.04:24:52.00#ibcon#flushed, iclass 10, count 2 2006.201.04:24:52.00#ibcon#about to write, iclass 10, count 2 2006.201.04:24:52.00#ibcon#wrote, iclass 10, count 2 2006.201.04:24:52.00#ibcon#about to read 3, iclass 10, count 2 2006.201.04:24:52.02#ibcon#read 3, iclass 10, count 2 2006.201.04:24:52.02#ibcon#about to read 4, iclass 10, count 2 2006.201.04:24:52.02#ibcon#read 4, iclass 10, count 2 2006.201.04:24:52.02#ibcon#about to read 5, iclass 10, count 2 2006.201.04:24:52.02#ibcon#read 5, iclass 10, count 2 2006.201.04:24:52.02#ibcon#about to read 6, iclass 10, count 2 2006.201.04:24:52.02#ibcon#read 6, iclass 10, count 2 2006.201.04:24:52.02#ibcon#end of sib2, iclass 10, count 2 2006.201.04:24:52.02#ibcon#*mode == 0, iclass 10, count 2 2006.201.04:24:52.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.04:24:52.02#ibcon#[25=AT02-07\r\n] 2006.201.04:24:52.02#ibcon#*before write, iclass 10, count 2 2006.201.04:24:52.02#ibcon#enter sib2, iclass 10, count 2 2006.201.04:24:52.02#ibcon#flushed, iclass 10, count 2 2006.201.04:24:52.02#ibcon#about to write, iclass 10, count 2 2006.201.04:24:52.02#ibcon#wrote, iclass 10, count 2 2006.201.04:24:52.02#ibcon#about to read 3, iclass 10, count 2 2006.201.04:24:52.05#ibcon#read 3, iclass 10, count 2 2006.201.04:24:52.05#ibcon#about to read 4, iclass 10, count 2 2006.201.04:24:52.05#ibcon#read 4, iclass 10, count 2 2006.201.04:24:52.05#ibcon#about to read 5, iclass 10, count 2 2006.201.04:24:52.05#ibcon#read 5, iclass 10, count 2 2006.201.04:24:52.05#ibcon#about to read 6, iclass 10, count 2 2006.201.04:24:52.05#ibcon#read 6, iclass 10, count 2 2006.201.04:24:52.05#ibcon#end of sib2, iclass 10, count 2 2006.201.04:24:52.05#ibcon#*after write, iclass 10, count 2 2006.201.04:24:52.05#ibcon#*before return 0, iclass 10, count 2 2006.201.04:24:52.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:52.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:52.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.04:24:52.05#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:52.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:52.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:52.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:52.17#ibcon#enter wrdev, iclass 10, count 0 2006.201.04:24:52.17#ibcon#first serial, iclass 10, count 0 2006.201.04:24:52.17#ibcon#enter sib2, iclass 10, count 0 2006.201.04:24:52.17#ibcon#flushed, iclass 10, count 0 2006.201.04:24:52.17#ibcon#about to write, iclass 10, count 0 2006.201.04:24:52.17#ibcon#wrote, iclass 10, count 0 2006.201.04:24:52.17#ibcon#about to read 3, iclass 10, count 0 2006.201.04:24:52.19#ibcon#read 3, iclass 10, count 0 2006.201.04:24:52.19#ibcon#about to read 4, iclass 10, count 0 2006.201.04:24:52.19#ibcon#read 4, iclass 10, count 0 2006.201.04:24:52.19#ibcon#about to read 5, iclass 10, count 0 2006.201.04:24:52.19#ibcon#read 5, iclass 10, count 0 2006.201.04:24:52.19#ibcon#about to read 6, iclass 10, count 0 2006.201.04:24:52.19#ibcon#read 6, iclass 10, count 0 2006.201.04:24:52.19#ibcon#end of sib2, iclass 10, count 0 2006.201.04:24:52.19#ibcon#*mode == 0, iclass 10, count 0 2006.201.04:24:52.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.04:24:52.19#ibcon#[25=USB\r\n] 2006.201.04:24:52.19#ibcon#*before write, iclass 10, count 0 2006.201.04:24:52.19#ibcon#enter sib2, iclass 10, count 0 2006.201.04:24:52.19#ibcon#flushed, iclass 10, count 0 2006.201.04:24:52.19#ibcon#about to write, iclass 10, count 0 2006.201.04:24:52.19#ibcon#wrote, iclass 10, count 0 2006.201.04:24:52.19#ibcon#about to read 3, iclass 10, count 0 2006.201.04:24:52.22#ibcon#read 3, iclass 10, count 0 2006.201.04:24:52.22#ibcon#about to read 4, iclass 10, count 0 2006.201.04:24:52.22#ibcon#read 4, iclass 10, count 0 2006.201.04:24:52.22#ibcon#about to read 5, iclass 10, count 0 2006.201.04:24:52.22#ibcon#read 5, iclass 10, count 0 2006.201.04:24:52.22#ibcon#about to read 6, iclass 10, count 0 2006.201.04:24:52.22#ibcon#read 6, iclass 10, count 0 2006.201.04:24:52.22#ibcon#end of sib2, iclass 10, count 0 2006.201.04:24:52.22#ibcon#*after write, iclass 10, count 0 2006.201.04:24:52.22#ibcon#*before return 0, iclass 10, count 0 2006.201.04:24:52.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:52.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:52.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.04:24:52.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.04:24:52.22$vck44/valo=3,564.99 2006.201.04:24:52.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.04:24:52.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.04:24:52.22#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:52.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:52.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:52.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:52.22#ibcon#enter wrdev, iclass 12, count 0 2006.201.04:24:52.22#ibcon#first serial, iclass 12, count 0 2006.201.04:24:52.22#ibcon#enter sib2, iclass 12, count 0 2006.201.04:24:52.22#ibcon#flushed, iclass 12, count 0 2006.201.04:24:52.22#ibcon#about to write, iclass 12, count 0 2006.201.04:24:52.22#ibcon#wrote, iclass 12, count 0 2006.201.04:24:52.22#ibcon#about to read 3, iclass 12, count 0 2006.201.04:24:52.24#ibcon#read 3, iclass 12, count 0 2006.201.04:24:52.24#ibcon#about to read 4, iclass 12, count 0 2006.201.04:24:52.24#ibcon#read 4, iclass 12, count 0 2006.201.04:24:52.24#ibcon#about to read 5, iclass 12, count 0 2006.201.04:24:52.24#ibcon#read 5, iclass 12, count 0 2006.201.04:24:52.24#ibcon#about to read 6, iclass 12, count 0 2006.201.04:24:52.24#ibcon#read 6, iclass 12, count 0 2006.201.04:24:52.24#ibcon#end of sib2, iclass 12, count 0 2006.201.04:24:52.24#ibcon#*mode == 0, iclass 12, count 0 2006.201.04:24:52.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.04:24:52.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:24:52.24#ibcon#*before write, iclass 12, count 0 2006.201.04:24:52.24#ibcon#enter sib2, iclass 12, count 0 2006.201.04:24:52.24#ibcon#flushed, iclass 12, count 0 2006.201.04:24:52.24#ibcon#about to write, iclass 12, count 0 2006.201.04:24:52.24#ibcon#wrote, iclass 12, count 0 2006.201.04:24:52.24#ibcon#about to read 3, iclass 12, count 0 2006.201.04:24:52.28#ibcon#read 3, iclass 12, count 0 2006.201.04:24:52.28#ibcon#about to read 4, iclass 12, count 0 2006.201.04:24:52.28#ibcon#read 4, iclass 12, count 0 2006.201.04:24:52.28#ibcon#about to read 5, iclass 12, count 0 2006.201.04:24:52.28#ibcon#read 5, iclass 12, count 0 2006.201.04:24:52.28#ibcon#about to read 6, iclass 12, count 0 2006.201.04:24:52.28#ibcon#read 6, iclass 12, count 0 2006.201.04:24:52.28#ibcon#end of sib2, iclass 12, count 0 2006.201.04:24:52.28#ibcon#*after write, iclass 12, count 0 2006.201.04:24:52.28#ibcon#*before return 0, iclass 12, count 0 2006.201.04:24:52.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:52.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:52.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.04:24:52.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.04:24:52.28$vck44/va=3,8 2006.201.04:24:52.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.04:24:52.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.04:24:52.28#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:52.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:52.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:52.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:52.34#ibcon#enter wrdev, iclass 14, count 2 2006.201.04:24:52.34#ibcon#first serial, iclass 14, count 2 2006.201.04:24:52.34#ibcon#enter sib2, iclass 14, count 2 2006.201.04:24:52.34#ibcon#flushed, iclass 14, count 2 2006.201.04:24:52.34#ibcon#about to write, iclass 14, count 2 2006.201.04:24:52.34#ibcon#wrote, iclass 14, count 2 2006.201.04:24:52.34#ibcon#about to read 3, iclass 14, count 2 2006.201.04:24:52.36#ibcon#read 3, iclass 14, count 2 2006.201.04:24:52.36#ibcon#about to read 4, iclass 14, count 2 2006.201.04:24:52.36#ibcon#read 4, iclass 14, count 2 2006.201.04:24:52.36#ibcon#about to read 5, iclass 14, count 2 2006.201.04:24:52.36#ibcon#read 5, iclass 14, count 2 2006.201.04:24:52.36#ibcon#about to read 6, iclass 14, count 2 2006.201.04:24:52.36#ibcon#read 6, iclass 14, count 2 2006.201.04:24:52.36#ibcon#end of sib2, iclass 14, count 2 2006.201.04:24:52.36#ibcon#*mode == 0, iclass 14, count 2 2006.201.04:24:52.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.04:24:52.36#ibcon#[25=AT03-08\r\n] 2006.201.04:24:52.36#ibcon#*before write, iclass 14, count 2 2006.201.04:24:52.36#ibcon#enter sib2, iclass 14, count 2 2006.201.04:24:52.36#ibcon#flushed, iclass 14, count 2 2006.201.04:24:52.36#ibcon#about to write, iclass 14, count 2 2006.201.04:24:52.36#ibcon#wrote, iclass 14, count 2 2006.201.04:24:52.36#ibcon#about to read 3, iclass 14, count 2 2006.201.04:24:52.39#ibcon#read 3, iclass 14, count 2 2006.201.04:24:52.39#ibcon#about to read 4, iclass 14, count 2 2006.201.04:24:52.39#ibcon#read 4, iclass 14, count 2 2006.201.04:24:52.39#ibcon#about to read 5, iclass 14, count 2 2006.201.04:24:52.39#ibcon#read 5, iclass 14, count 2 2006.201.04:24:52.39#ibcon#about to read 6, iclass 14, count 2 2006.201.04:24:52.39#ibcon#read 6, iclass 14, count 2 2006.201.04:24:52.39#ibcon#end of sib2, iclass 14, count 2 2006.201.04:24:52.39#ibcon#*after write, iclass 14, count 2 2006.201.04:24:52.39#ibcon#*before return 0, iclass 14, count 2 2006.201.04:24:52.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:52.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:52.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.04:24:52.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:52.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:52.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:52.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:52.51#ibcon#enter wrdev, iclass 14, count 0 2006.201.04:24:52.51#ibcon#first serial, iclass 14, count 0 2006.201.04:24:52.51#ibcon#enter sib2, iclass 14, count 0 2006.201.04:24:52.51#ibcon#flushed, iclass 14, count 0 2006.201.04:24:52.51#ibcon#about to write, iclass 14, count 0 2006.201.04:24:52.51#ibcon#wrote, iclass 14, count 0 2006.201.04:24:52.51#ibcon#about to read 3, iclass 14, count 0 2006.201.04:24:52.53#ibcon#read 3, iclass 14, count 0 2006.201.04:24:52.53#ibcon#about to read 4, iclass 14, count 0 2006.201.04:24:52.53#ibcon#read 4, iclass 14, count 0 2006.201.04:24:52.53#ibcon#about to read 5, iclass 14, count 0 2006.201.04:24:52.53#ibcon#read 5, iclass 14, count 0 2006.201.04:24:52.53#ibcon#about to read 6, iclass 14, count 0 2006.201.04:24:52.53#ibcon#read 6, iclass 14, count 0 2006.201.04:24:52.53#ibcon#end of sib2, iclass 14, count 0 2006.201.04:24:52.53#ibcon#*mode == 0, iclass 14, count 0 2006.201.04:24:52.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.04:24:52.53#ibcon#[25=USB\r\n] 2006.201.04:24:52.53#ibcon#*before write, iclass 14, count 0 2006.201.04:24:52.53#ibcon#enter sib2, iclass 14, count 0 2006.201.04:24:52.53#ibcon#flushed, iclass 14, count 0 2006.201.04:24:52.53#ibcon#about to write, iclass 14, count 0 2006.201.04:24:52.53#ibcon#wrote, iclass 14, count 0 2006.201.04:24:52.53#ibcon#about to read 3, iclass 14, count 0 2006.201.04:24:52.56#ibcon#read 3, iclass 14, count 0 2006.201.04:24:52.56#ibcon#about to read 4, iclass 14, count 0 2006.201.04:24:52.56#ibcon#read 4, iclass 14, count 0 2006.201.04:24:52.56#ibcon#about to read 5, iclass 14, count 0 2006.201.04:24:52.56#ibcon#read 5, iclass 14, count 0 2006.201.04:24:52.56#ibcon#about to read 6, iclass 14, count 0 2006.201.04:24:52.56#ibcon#read 6, iclass 14, count 0 2006.201.04:24:52.56#ibcon#end of sib2, iclass 14, count 0 2006.201.04:24:52.56#ibcon#*after write, iclass 14, count 0 2006.201.04:24:52.56#ibcon#*before return 0, iclass 14, count 0 2006.201.04:24:52.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:52.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:52.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.04:24:52.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.04:24:52.56$vck44/valo=4,624.99 2006.201.04:24:52.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.04:24:52.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.04:24:52.56#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:52.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:52.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:52.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:52.56#ibcon#enter wrdev, iclass 16, count 0 2006.201.04:24:52.56#ibcon#first serial, iclass 16, count 0 2006.201.04:24:52.56#ibcon#enter sib2, iclass 16, count 0 2006.201.04:24:52.56#ibcon#flushed, iclass 16, count 0 2006.201.04:24:52.56#ibcon#about to write, iclass 16, count 0 2006.201.04:24:52.56#ibcon#wrote, iclass 16, count 0 2006.201.04:24:52.56#ibcon#about to read 3, iclass 16, count 0 2006.201.04:24:52.58#ibcon#read 3, iclass 16, count 0 2006.201.04:24:52.58#ibcon#about to read 4, iclass 16, count 0 2006.201.04:24:52.58#ibcon#read 4, iclass 16, count 0 2006.201.04:24:52.58#ibcon#about to read 5, iclass 16, count 0 2006.201.04:24:52.58#ibcon#read 5, iclass 16, count 0 2006.201.04:24:52.58#ibcon#about to read 6, iclass 16, count 0 2006.201.04:24:52.58#ibcon#read 6, iclass 16, count 0 2006.201.04:24:52.58#ibcon#end of sib2, iclass 16, count 0 2006.201.04:24:52.58#ibcon#*mode == 0, iclass 16, count 0 2006.201.04:24:52.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.04:24:52.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:24:52.58#ibcon#*before write, iclass 16, count 0 2006.201.04:24:52.58#ibcon#enter sib2, iclass 16, count 0 2006.201.04:24:52.58#ibcon#flushed, iclass 16, count 0 2006.201.04:24:52.58#ibcon#about to write, iclass 16, count 0 2006.201.04:24:52.58#ibcon#wrote, iclass 16, count 0 2006.201.04:24:52.58#ibcon#about to read 3, iclass 16, count 0 2006.201.04:24:52.62#ibcon#read 3, iclass 16, count 0 2006.201.04:24:52.62#ibcon#about to read 4, iclass 16, count 0 2006.201.04:24:52.62#ibcon#read 4, iclass 16, count 0 2006.201.04:24:52.62#ibcon#about to read 5, iclass 16, count 0 2006.201.04:24:52.62#ibcon#read 5, iclass 16, count 0 2006.201.04:24:52.62#ibcon#about to read 6, iclass 16, count 0 2006.201.04:24:52.62#ibcon#read 6, iclass 16, count 0 2006.201.04:24:52.62#ibcon#end of sib2, iclass 16, count 0 2006.201.04:24:52.62#ibcon#*after write, iclass 16, count 0 2006.201.04:24:52.62#ibcon#*before return 0, iclass 16, count 0 2006.201.04:24:52.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:52.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:52.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.04:24:52.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.04:24:52.62$vck44/va=4,7 2006.201.04:24:52.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.04:24:52.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.04:24:52.62#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:52.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:52.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:52.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:52.68#ibcon#enter wrdev, iclass 18, count 2 2006.201.04:24:52.68#ibcon#first serial, iclass 18, count 2 2006.201.04:24:52.68#ibcon#enter sib2, iclass 18, count 2 2006.201.04:24:52.68#ibcon#flushed, iclass 18, count 2 2006.201.04:24:52.68#ibcon#about to write, iclass 18, count 2 2006.201.04:24:52.68#ibcon#wrote, iclass 18, count 2 2006.201.04:24:52.68#ibcon#about to read 3, iclass 18, count 2 2006.201.04:24:52.70#ibcon#read 3, iclass 18, count 2 2006.201.04:24:52.70#ibcon#about to read 4, iclass 18, count 2 2006.201.04:24:52.70#ibcon#read 4, iclass 18, count 2 2006.201.04:24:52.70#ibcon#about to read 5, iclass 18, count 2 2006.201.04:24:52.70#ibcon#read 5, iclass 18, count 2 2006.201.04:24:52.70#ibcon#about to read 6, iclass 18, count 2 2006.201.04:24:52.70#ibcon#read 6, iclass 18, count 2 2006.201.04:24:52.70#ibcon#end of sib2, iclass 18, count 2 2006.201.04:24:52.70#ibcon#*mode == 0, iclass 18, count 2 2006.201.04:24:52.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.04:24:52.70#ibcon#[25=AT04-07\r\n] 2006.201.04:24:52.70#ibcon#*before write, iclass 18, count 2 2006.201.04:24:52.70#ibcon#enter sib2, iclass 18, count 2 2006.201.04:24:52.70#ibcon#flushed, iclass 18, count 2 2006.201.04:24:52.70#ibcon#about to write, iclass 18, count 2 2006.201.04:24:52.70#ibcon#wrote, iclass 18, count 2 2006.201.04:24:52.70#ibcon#about to read 3, iclass 18, count 2 2006.201.04:24:52.73#ibcon#read 3, iclass 18, count 2 2006.201.04:24:52.73#ibcon#about to read 4, iclass 18, count 2 2006.201.04:24:52.73#ibcon#read 4, iclass 18, count 2 2006.201.04:24:52.73#ibcon#about to read 5, iclass 18, count 2 2006.201.04:24:52.73#ibcon#read 5, iclass 18, count 2 2006.201.04:24:52.73#ibcon#about to read 6, iclass 18, count 2 2006.201.04:24:52.73#ibcon#read 6, iclass 18, count 2 2006.201.04:24:52.73#ibcon#end of sib2, iclass 18, count 2 2006.201.04:24:52.73#ibcon#*after write, iclass 18, count 2 2006.201.04:24:52.73#ibcon#*before return 0, iclass 18, count 2 2006.201.04:24:52.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:52.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:52.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.04:24:52.73#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:52.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:52.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:52.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:52.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.04:24:52.85#ibcon#first serial, iclass 18, count 0 2006.201.04:24:52.85#ibcon#enter sib2, iclass 18, count 0 2006.201.04:24:52.85#ibcon#flushed, iclass 18, count 0 2006.201.04:24:52.85#ibcon#about to write, iclass 18, count 0 2006.201.04:24:52.85#ibcon#wrote, iclass 18, count 0 2006.201.04:24:52.85#ibcon#about to read 3, iclass 18, count 0 2006.201.04:24:52.87#ibcon#read 3, iclass 18, count 0 2006.201.04:24:52.87#ibcon#about to read 4, iclass 18, count 0 2006.201.04:24:52.87#ibcon#read 4, iclass 18, count 0 2006.201.04:24:52.87#ibcon#about to read 5, iclass 18, count 0 2006.201.04:24:52.87#ibcon#read 5, iclass 18, count 0 2006.201.04:24:52.87#ibcon#about to read 6, iclass 18, count 0 2006.201.04:24:52.87#ibcon#read 6, iclass 18, count 0 2006.201.04:24:52.87#ibcon#end of sib2, iclass 18, count 0 2006.201.04:24:52.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.04:24:52.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.04:24:52.87#ibcon#[25=USB\r\n] 2006.201.04:24:52.87#ibcon#*before write, iclass 18, count 0 2006.201.04:24:52.87#ibcon#enter sib2, iclass 18, count 0 2006.201.04:24:52.87#ibcon#flushed, iclass 18, count 0 2006.201.04:24:52.87#ibcon#about to write, iclass 18, count 0 2006.201.04:24:52.87#ibcon#wrote, iclass 18, count 0 2006.201.04:24:52.87#ibcon#about to read 3, iclass 18, count 0 2006.201.04:24:52.90#ibcon#read 3, iclass 18, count 0 2006.201.04:24:52.90#ibcon#about to read 4, iclass 18, count 0 2006.201.04:24:52.90#ibcon#read 4, iclass 18, count 0 2006.201.04:24:52.90#ibcon#about to read 5, iclass 18, count 0 2006.201.04:24:52.90#ibcon#read 5, iclass 18, count 0 2006.201.04:24:52.90#ibcon#about to read 6, iclass 18, count 0 2006.201.04:24:52.90#ibcon#read 6, iclass 18, count 0 2006.201.04:24:52.90#ibcon#end of sib2, iclass 18, count 0 2006.201.04:24:52.90#ibcon#*after write, iclass 18, count 0 2006.201.04:24:52.90#ibcon#*before return 0, iclass 18, count 0 2006.201.04:24:52.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:52.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:52.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.04:24:52.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.04:24:52.90$vck44/valo=5,734.99 2006.201.04:24:52.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.04:24:52.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.04:24:52.90#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:52.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:52.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:52.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:52.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.04:24:52.90#ibcon#first serial, iclass 20, count 0 2006.201.04:24:52.90#ibcon#enter sib2, iclass 20, count 0 2006.201.04:24:52.90#ibcon#flushed, iclass 20, count 0 2006.201.04:24:52.90#ibcon#about to write, iclass 20, count 0 2006.201.04:24:52.90#ibcon#wrote, iclass 20, count 0 2006.201.04:24:52.90#ibcon#about to read 3, iclass 20, count 0 2006.201.04:24:52.92#ibcon#read 3, iclass 20, count 0 2006.201.04:24:52.92#ibcon#about to read 4, iclass 20, count 0 2006.201.04:24:52.92#ibcon#read 4, iclass 20, count 0 2006.201.04:24:52.92#ibcon#about to read 5, iclass 20, count 0 2006.201.04:24:52.92#ibcon#read 5, iclass 20, count 0 2006.201.04:24:52.92#ibcon#about to read 6, iclass 20, count 0 2006.201.04:24:52.92#ibcon#read 6, iclass 20, count 0 2006.201.04:24:52.92#ibcon#end of sib2, iclass 20, count 0 2006.201.04:24:52.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.04:24:52.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.04:24:52.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:24:52.92#ibcon#*before write, iclass 20, count 0 2006.201.04:24:52.92#ibcon#enter sib2, iclass 20, count 0 2006.201.04:24:52.92#ibcon#flushed, iclass 20, count 0 2006.201.04:24:52.92#ibcon#about to write, iclass 20, count 0 2006.201.04:24:52.92#ibcon#wrote, iclass 20, count 0 2006.201.04:24:52.92#ibcon#about to read 3, iclass 20, count 0 2006.201.04:24:52.96#ibcon#read 3, iclass 20, count 0 2006.201.04:24:52.96#ibcon#about to read 4, iclass 20, count 0 2006.201.04:24:52.96#ibcon#read 4, iclass 20, count 0 2006.201.04:24:52.96#ibcon#about to read 5, iclass 20, count 0 2006.201.04:24:52.96#ibcon#read 5, iclass 20, count 0 2006.201.04:24:52.96#ibcon#about to read 6, iclass 20, count 0 2006.201.04:24:52.96#ibcon#read 6, iclass 20, count 0 2006.201.04:24:52.96#ibcon#end of sib2, iclass 20, count 0 2006.201.04:24:52.96#ibcon#*after write, iclass 20, count 0 2006.201.04:24:52.96#ibcon#*before return 0, iclass 20, count 0 2006.201.04:24:52.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:52.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:52.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.04:24:52.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.04:24:52.96$vck44/va=5,4 2006.201.04:24:52.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.04:24:52.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.04:24:52.96#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:52.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:53.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:53.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:53.02#ibcon#enter wrdev, iclass 22, count 2 2006.201.04:24:53.02#ibcon#first serial, iclass 22, count 2 2006.201.04:24:53.02#ibcon#enter sib2, iclass 22, count 2 2006.201.04:24:53.02#ibcon#flushed, iclass 22, count 2 2006.201.04:24:53.02#ibcon#about to write, iclass 22, count 2 2006.201.04:24:53.02#ibcon#wrote, iclass 22, count 2 2006.201.04:24:53.02#ibcon#about to read 3, iclass 22, count 2 2006.201.04:24:53.04#ibcon#read 3, iclass 22, count 2 2006.201.04:24:53.04#ibcon#about to read 4, iclass 22, count 2 2006.201.04:24:53.04#ibcon#read 4, iclass 22, count 2 2006.201.04:24:53.04#ibcon#about to read 5, iclass 22, count 2 2006.201.04:24:53.04#ibcon#read 5, iclass 22, count 2 2006.201.04:24:53.04#ibcon#about to read 6, iclass 22, count 2 2006.201.04:24:53.04#ibcon#read 6, iclass 22, count 2 2006.201.04:24:53.04#ibcon#end of sib2, iclass 22, count 2 2006.201.04:24:53.04#ibcon#*mode == 0, iclass 22, count 2 2006.201.04:24:53.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.04:24:53.04#ibcon#[25=AT05-04\r\n] 2006.201.04:24:53.04#ibcon#*before write, iclass 22, count 2 2006.201.04:24:53.04#ibcon#enter sib2, iclass 22, count 2 2006.201.04:24:53.04#ibcon#flushed, iclass 22, count 2 2006.201.04:24:53.04#ibcon#about to write, iclass 22, count 2 2006.201.04:24:53.04#ibcon#wrote, iclass 22, count 2 2006.201.04:24:53.04#ibcon#about to read 3, iclass 22, count 2 2006.201.04:24:53.07#ibcon#read 3, iclass 22, count 2 2006.201.04:24:53.07#ibcon#about to read 4, iclass 22, count 2 2006.201.04:24:53.07#ibcon#read 4, iclass 22, count 2 2006.201.04:24:53.07#ibcon#about to read 5, iclass 22, count 2 2006.201.04:24:53.07#ibcon#read 5, iclass 22, count 2 2006.201.04:24:53.07#ibcon#about to read 6, iclass 22, count 2 2006.201.04:24:53.07#ibcon#read 6, iclass 22, count 2 2006.201.04:24:53.07#ibcon#end of sib2, iclass 22, count 2 2006.201.04:24:53.07#ibcon#*after write, iclass 22, count 2 2006.201.04:24:53.07#ibcon#*before return 0, iclass 22, count 2 2006.201.04:24:53.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:53.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:53.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.04:24:53.07#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:53.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:53.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:53.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:53.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.04:24:53.19#ibcon#first serial, iclass 22, count 0 2006.201.04:24:53.19#ibcon#enter sib2, iclass 22, count 0 2006.201.04:24:53.19#ibcon#flushed, iclass 22, count 0 2006.201.04:24:53.19#ibcon#about to write, iclass 22, count 0 2006.201.04:24:53.19#ibcon#wrote, iclass 22, count 0 2006.201.04:24:53.19#ibcon#about to read 3, iclass 22, count 0 2006.201.04:24:53.21#ibcon#read 3, iclass 22, count 0 2006.201.04:24:53.21#ibcon#about to read 4, iclass 22, count 0 2006.201.04:24:53.21#ibcon#read 4, iclass 22, count 0 2006.201.04:24:53.21#ibcon#about to read 5, iclass 22, count 0 2006.201.04:24:53.21#ibcon#read 5, iclass 22, count 0 2006.201.04:24:53.21#ibcon#about to read 6, iclass 22, count 0 2006.201.04:24:53.21#ibcon#read 6, iclass 22, count 0 2006.201.04:24:53.21#ibcon#end of sib2, iclass 22, count 0 2006.201.04:24:53.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.04:24:53.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.04:24:53.21#ibcon#[25=USB\r\n] 2006.201.04:24:53.21#ibcon#*before write, iclass 22, count 0 2006.201.04:24:53.21#ibcon#enter sib2, iclass 22, count 0 2006.201.04:24:53.21#ibcon#flushed, iclass 22, count 0 2006.201.04:24:53.21#ibcon#about to write, iclass 22, count 0 2006.201.04:24:53.21#ibcon#wrote, iclass 22, count 0 2006.201.04:24:53.21#ibcon#about to read 3, iclass 22, count 0 2006.201.04:24:53.24#ibcon#read 3, iclass 22, count 0 2006.201.04:24:53.24#ibcon#about to read 4, iclass 22, count 0 2006.201.04:24:53.24#ibcon#read 4, iclass 22, count 0 2006.201.04:24:53.24#ibcon#about to read 5, iclass 22, count 0 2006.201.04:24:53.24#ibcon#read 5, iclass 22, count 0 2006.201.04:24:53.24#ibcon#about to read 6, iclass 22, count 0 2006.201.04:24:53.24#ibcon#read 6, iclass 22, count 0 2006.201.04:24:53.24#ibcon#end of sib2, iclass 22, count 0 2006.201.04:24:53.24#ibcon#*after write, iclass 22, count 0 2006.201.04:24:53.24#ibcon#*before return 0, iclass 22, count 0 2006.201.04:24:53.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:53.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:53.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.04:24:53.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.04:24:53.24$vck44/valo=6,814.99 2006.201.04:24:53.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.04:24:53.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.04:24:53.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:53.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:53.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:53.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:53.24#ibcon#enter wrdev, iclass 24, count 0 2006.201.04:24:53.24#ibcon#first serial, iclass 24, count 0 2006.201.04:24:53.24#ibcon#enter sib2, iclass 24, count 0 2006.201.04:24:53.24#ibcon#flushed, iclass 24, count 0 2006.201.04:24:53.24#ibcon#about to write, iclass 24, count 0 2006.201.04:24:53.24#ibcon#wrote, iclass 24, count 0 2006.201.04:24:53.24#ibcon#about to read 3, iclass 24, count 0 2006.201.04:24:53.26#ibcon#read 3, iclass 24, count 0 2006.201.04:24:53.26#ibcon#about to read 4, iclass 24, count 0 2006.201.04:24:53.26#ibcon#read 4, iclass 24, count 0 2006.201.04:24:53.26#ibcon#about to read 5, iclass 24, count 0 2006.201.04:24:53.26#ibcon#read 5, iclass 24, count 0 2006.201.04:24:53.26#ibcon#about to read 6, iclass 24, count 0 2006.201.04:24:53.26#ibcon#read 6, iclass 24, count 0 2006.201.04:24:53.26#ibcon#end of sib2, iclass 24, count 0 2006.201.04:24:53.26#ibcon#*mode == 0, iclass 24, count 0 2006.201.04:24:53.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.04:24:53.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:24:53.26#ibcon#*before write, iclass 24, count 0 2006.201.04:24:53.26#ibcon#enter sib2, iclass 24, count 0 2006.201.04:24:53.26#ibcon#flushed, iclass 24, count 0 2006.201.04:24:53.26#ibcon#about to write, iclass 24, count 0 2006.201.04:24:53.26#ibcon#wrote, iclass 24, count 0 2006.201.04:24:53.26#ibcon#about to read 3, iclass 24, count 0 2006.201.04:24:53.30#ibcon#read 3, iclass 24, count 0 2006.201.04:24:53.30#ibcon#about to read 4, iclass 24, count 0 2006.201.04:24:53.30#ibcon#read 4, iclass 24, count 0 2006.201.04:24:53.30#ibcon#about to read 5, iclass 24, count 0 2006.201.04:24:53.30#ibcon#read 5, iclass 24, count 0 2006.201.04:24:53.30#ibcon#about to read 6, iclass 24, count 0 2006.201.04:24:53.30#ibcon#read 6, iclass 24, count 0 2006.201.04:24:53.30#ibcon#end of sib2, iclass 24, count 0 2006.201.04:24:53.30#ibcon#*after write, iclass 24, count 0 2006.201.04:24:53.30#ibcon#*before return 0, iclass 24, count 0 2006.201.04:24:53.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:53.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:53.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.04:24:53.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.04:24:53.30$vck44/va=6,5 2006.201.04:24:53.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.04:24:53.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.04:24:53.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:53.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:53.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:53.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:53.36#ibcon#enter wrdev, iclass 26, count 2 2006.201.04:24:53.36#ibcon#first serial, iclass 26, count 2 2006.201.04:24:53.36#ibcon#enter sib2, iclass 26, count 2 2006.201.04:24:53.36#ibcon#flushed, iclass 26, count 2 2006.201.04:24:53.36#ibcon#about to write, iclass 26, count 2 2006.201.04:24:53.36#ibcon#wrote, iclass 26, count 2 2006.201.04:24:53.36#ibcon#about to read 3, iclass 26, count 2 2006.201.04:24:53.38#ibcon#read 3, iclass 26, count 2 2006.201.04:24:53.38#ibcon#about to read 4, iclass 26, count 2 2006.201.04:24:53.38#ibcon#read 4, iclass 26, count 2 2006.201.04:24:53.38#ibcon#about to read 5, iclass 26, count 2 2006.201.04:24:53.38#ibcon#read 5, iclass 26, count 2 2006.201.04:24:53.38#ibcon#about to read 6, iclass 26, count 2 2006.201.04:24:53.38#ibcon#read 6, iclass 26, count 2 2006.201.04:24:53.38#ibcon#end of sib2, iclass 26, count 2 2006.201.04:24:53.38#ibcon#*mode == 0, iclass 26, count 2 2006.201.04:24:53.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.04:24:53.38#ibcon#[25=AT06-05\r\n] 2006.201.04:24:53.38#ibcon#*before write, iclass 26, count 2 2006.201.04:24:53.38#ibcon#enter sib2, iclass 26, count 2 2006.201.04:24:53.38#ibcon#flushed, iclass 26, count 2 2006.201.04:24:53.38#ibcon#about to write, iclass 26, count 2 2006.201.04:24:53.38#ibcon#wrote, iclass 26, count 2 2006.201.04:24:53.38#ibcon#about to read 3, iclass 26, count 2 2006.201.04:24:53.41#ibcon#read 3, iclass 26, count 2 2006.201.04:24:53.41#ibcon#about to read 4, iclass 26, count 2 2006.201.04:24:53.41#ibcon#read 4, iclass 26, count 2 2006.201.04:24:53.41#ibcon#about to read 5, iclass 26, count 2 2006.201.04:24:53.41#ibcon#read 5, iclass 26, count 2 2006.201.04:24:53.41#ibcon#about to read 6, iclass 26, count 2 2006.201.04:24:53.41#ibcon#read 6, iclass 26, count 2 2006.201.04:24:53.41#ibcon#end of sib2, iclass 26, count 2 2006.201.04:24:53.41#ibcon#*after write, iclass 26, count 2 2006.201.04:24:53.41#ibcon#*before return 0, iclass 26, count 2 2006.201.04:24:53.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:53.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:53.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.04:24:53.41#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:53.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:53.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:53.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:53.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.04:24:53.53#ibcon#first serial, iclass 26, count 0 2006.201.04:24:53.53#ibcon#enter sib2, iclass 26, count 0 2006.201.04:24:53.53#ibcon#flushed, iclass 26, count 0 2006.201.04:24:53.53#ibcon#about to write, iclass 26, count 0 2006.201.04:24:53.53#ibcon#wrote, iclass 26, count 0 2006.201.04:24:53.53#ibcon#about to read 3, iclass 26, count 0 2006.201.04:24:53.55#ibcon#read 3, iclass 26, count 0 2006.201.04:24:53.55#ibcon#about to read 4, iclass 26, count 0 2006.201.04:24:53.55#ibcon#read 4, iclass 26, count 0 2006.201.04:24:53.55#ibcon#about to read 5, iclass 26, count 0 2006.201.04:24:53.55#ibcon#read 5, iclass 26, count 0 2006.201.04:24:53.55#ibcon#about to read 6, iclass 26, count 0 2006.201.04:24:53.55#ibcon#read 6, iclass 26, count 0 2006.201.04:24:53.55#ibcon#end of sib2, iclass 26, count 0 2006.201.04:24:53.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.04:24:53.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.04:24:53.55#ibcon#[25=USB\r\n] 2006.201.04:24:53.55#ibcon#*before write, iclass 26, count 0 2006.201.04:24:53.55#ibcon#enter sib2, iclass 26, count 0 2006.201.04:24:53.55#ibcon#flushed, iclass 26, count 0 2006.201.04:24:53.55#ibcon#about to write, iclass 26, count 0 2006.201.04:24:53.55#ibcon#wrote, iclass 26, count 0 2006.201.04:24:53.55#ibcon#about to read 3, iclass 26, count 0 2006.201.04:24:53.58#ibcon#read 3, iclass 26, count 0 2006.201.04:24:53.58#ibcon#about to read 4, iclass 26, count 0 2006.201.04:24:53.58#ibcon#read 4, iclass 26, count 0 2006.201.04:24:53.58#ibcon#about to read 5, iclass 26, count 0 2006.201.04:24:53.58#ibcon#read 5, iclass 26, count 0 2006.201.04:24:53.58#ibcon#about to read 6, iclass 26, count 0 2006.201.04:24:53.58#ibcon#read 6, iclass 26, count 0 2006.201.04:24:53.58#ibcon#end of sib2, iclass 26, count 0 2006.201.04:24:53.58#ibcon#*after write, iclass 26, count 0 2006.201.04:24:53.58#ibcon#*before return 0, iclass 26, count 0 2006.201.04:24:53.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:53.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:53.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.04:24:53.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.04:24:53.58$vck44/valo=7,864.99 2006.201.04:24:53.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.04:24:53.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.04:24:53.58#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:53.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:53.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:53.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:53.58#ibcon#enter wrdev, iclass 28, count 0 2006.201.04:24:53.58#ibcon#first serial, iclass 28, count 0 2006.201.04:24:53.58#ibcon#enter sib2, iclass 28, count 0 2006.201.04:24:53.58#ibcon#flushed, iclass 28, count 0 2006.201.04:24:53.58#ibcon#about to write, iclass 28, count 0 2006.201.04:24:53.58#ibcon#wrote, iclass 28, count 0 2006.201.04:24:53.58#ibcon#about to read 3, iclass 28, count 0 2006.201.04:24:53.60#ibcon#read 3, iclass 28, count 0 2006.201.04:24:53.60#ibcon#about to read 4, iclass 28, count 0 2006.201.04:24:53.60#ibcon#read 4, iclass 28, count 0 2006.201.04:24:53.60#ibcon#about to read 5, iclass 28, count 0 2006.201.04:24:53.60#ibcon#read 5, iclass 28, count 0 2006.201.04:24:53.60#ibcon#about to read 6, iclass 28, count 0 2006.201.04:24:53.60#ibcon#read 6, iclass 28, count 0 2006.201.04:24:53.60#ibcon#end of sib2, iclass 28, count 0 2006.201.04:24:53.60#ibcon#*mode == 0, iclass 28, count 0 2006.201.04:24:53.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.04:24:53.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:24:53.60#ibcon#*before write, iclass 28, count 0 2006.201.04:24:53.60#ibcon#enter sib2, iclass 28, count 0 2006.201.04:24:53.60#ibcon#flushed, iclass 28, count 0 2006.201.04:24:53.60#ibcon#about to write, iclass 28, count 0 2006.201.04:24:53.60#ibcon#wrote, iclass 28, count 0 2006.201.04:24:53.60#ibcon#about to read 3, iclass 28, count 0 2006.201.04:24:53.64#ibcon#read 3, iclass 28, count 0 2006.201.04:24:53.64#ibcon#about to read 4, iclass 28, count 0 2006.201.04:24:53.64#ibcon#read 4, iclass 28, count 0 2006.201.04:24:53.64#ibcon#about to read 5, iclass 28, count 0 2006.201.04:24:53.64#ibcon#read 5, iclass 28, count 0 2006.201.04:24:53.64#ibcon#about to read 6, iclass 28, count 0 2006.201.04:24:53.64#ibcon#read 6, iclass 28, count 0 2006.201.04:24:53.64#ibcon#end of sib2, iclass 28, count 0 2006.201.04:24:53.64#ibcon#*after write, iclass 28, count 0 2006.201.04:24:53.64#ibcon#*before return 0, iclass 28, count 0 2006.201.04:24:53.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:53.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:53.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.04:24:53.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.04:24:53.64$vck44/va=7,5 2006.201.04:24:53.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.04:24:53.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.04:24:53.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:53.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:53.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:53.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:53.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.04:24:53.70#ibcon#first serial, iclass 30, count 2 2006.201.04:24:53.70#ibcon#enter sib2, iclass 30, count 2 2006.201.04:24:53.70#ibcon#flushed, iclass 30, count 2 2006.201.04:24:53.70#ibcon#about to write, iclass 30, count 2 2006.201.04:24:53.70#ibcon#wrote, iclass 30, count 2 2006.201.04:24:53.70#ibcon#about to read 3, iclass 30, count 2 2006.201.04:24:53.72#ibcon#read 3, iclass 30, count 2 2006.201.04:24:53.72#ibcon#about to read 4, iclass 30, count 2 2006.201.04:24:53.72#ibcon#read 4, iclass 30, count 2 2006.201.04:24:53.72#ibcon#about to read 5, iclass 30, count 2 2006.201.04:24:53.72#ibcon#read 5, iclass 30, count 2 2006.201.04:24:53.72#ibcon#about to read 6, iclass 30, count 2 2006.201.04:24:53.72#ibcon#read 6, iclass 30, count 2 2006.201.04:24:53.72#ibcon#end of sib2, iclass 30, count 2 2006.201.04:24:53.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.04:24:53.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.04:24:53.72#ibcon#[25=AT07-05\r\n] 2006.201.04:24:53.72#ibcon#*before write, iclass 30, count 2 2006.201.04:24:53.72#ibcon#enter sib2, iclass 30, count 2 2006.201.04:24:53.72#ibcon#flushed, iclass 30, count 2 2006.201.04:24:53.72#ibcon#about to write, iclass 30, count 2 2006.201.04:24:53.72#ibcon#wrote, iclass 30, count 2 2006.201.04:24:53.72#ibcon#about to read 3, iclass 30, count 2 2006.201.04:24:53.75#ibcon#read 3, iclass 30, count 2 2006.201.04:24:53.75#ibcon#about to read 4, iclass 30, count 2 2006.201.04:24:53.75#ibcon#read 4, iclass 30, count 2 2006.201.04:24:53.75#ibcon#about to read 5, iclass 30, count 2 2006.201.04:24:53.75#ibcon#read 5, iclass 30, count 2 2006.201.04:24:53.75#ibcon#about to read 6, iclass 30, count 2 2006.201.04:24:53.75#ibcon#read 6, iclass 30, count 2 2006.201.04:24:53.75#ibcon#end of sib2, iclass 30, count 2 2006.201.04:24:53.75#ibcon#*after write, iclass 30, count 2 2006.201.04:24:53.75#ibcon#*before return 0, iclass 30, count 2 2006.201.04:24:53.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:53.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:53.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.04:24:53.75#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:53.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:53.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:53.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:53.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.04:24:53.87#ibcon#first serial, iclass 30, count 0 2006.201.04:24:53.87#ibcon#enter sib2, iclass 30, count 0 2006.201.04:24:53.87#ibcon#flushed, iclass 30, count 0 2006.201.04:24:53.87#ibcon#about to write, iclass 30, count 0 2006.201.04:24:53.87#ibcon#wrote, iclass 30, count 0 2006.201.04:24:53.87#ibcon#about to read 3, iclass 30, count 0 2006.201.04:24:53.89#ibcon#read 3, iclass 30, count 0 2006.201.04:24:53.89#ibcon#about to read 4, iclass 30, count 0 2006.201.04:24:53.89#ibcon#read 4, iclass 30, count 0 2006.201.04:24:53.89#ibcon#about to read 5, iclass 30, count 0 2006.201.04:24:53.89#ibcon#read 5, iclass 30, count 0 2006.201.04:24:53.89#ibcon#about to read 6, iclass 30, count 0 2006.201.04:24:53.89#ibcon#read 6, iclass 30, count 0 2006.201.04:24:53.89#ibcon#end of sib2, iclass 30, count 0 2006.201.04:24:53.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.04:24:53.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.04:24:53.89#ibcon#[25=USB\r\n] 2006.201.04:24:53.89#ibcon#*before write, iclass 30, count 0 2006.201.04:24:53.89#ibcon#enter sib2, iclass 30, count 0 2006.201.04:24:53.89#ibcon#flushed, iclass 30, count 0 2006.201.04:24:53.89#ibcon#about to write, iclass 30, count 0 2006.201.04:24:53.89#ibcon#wrote, iclass 30, count 0 2006.201.04:24:53.89#ibcon#about to read 3, iclass 30, count 0 2006.201.04:24:53.92#ibcon#read 3, iclass 30, count 0 2006.201.04:24:53.92#ibcon#about to read 4, iclass 30, count 0 2006.201.04:24:53.92#ibcon#read 4, iclass 30, count 0 2006.201.04:24:53.92#ibcon#about to read 5, iclass 30, count 0 2006.201.04:24:53.92#ibcon#read 5, iclass 30, count 0 2006.201.04:24:53.92#ibcon#about to read 6, iclass 30, count 0 2006.201.04:24:53.92#ibcon#read 6, iclass 30, count 0 2006.201.04:24:53.92#ibcon#end of sib2, iclass 30, count 0 2006.201.04:24:53.92#ibcon#*after write, iclass 30, count 0 2006.201.04:24:53.92#ibcon#*before return 0, iclass 30, count 0 2006.201.04:24:53.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:53.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:53.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.04:24:53.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.04:24:53.92$vck44/valo=8,884.99 2006.201.04:24:53.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.04:24:53.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.04:24:53.92#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:53.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:53.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:53.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:53.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.04:24:53.92#ibcon#first serial, iclass 32, count 0 2006.201.04:24:53.92#ibcon#enter sib2, iclass 32, count 0 2006.201.04:24:53.92#ibcon#flushed, iclass 32, count 0 2006.201.04:24:53.92#ibcon#about to write, iclass 32, count 0 2006.201.04:24:53.92#ibcon#wrote, iclass 32, count 0 2006.201.04:24:53.92#ibcon#about to read 3, iclass 32, count 0 2006.201.04:24:53.94#ibcon#read 3, iclass 32, count 0 2006.201.04:24:53.94#ibcon#about to read 4, iclass 32, count 0 2006.201.04:24:53.94#ibcon#read 4, iclass 32, count 0 2006.201.04:24:53.94#ibcon#about to read 5, iclass 32, count 0 2006.201.04:24:53.94#ibcon#read 5, iclass 32, count 0 2006.201.04:24:53.94#ibcon#about to read 6, iclass 32, count 0 2006.201.04:24:53.94#ibcon#read 6, iclass 32, count 0 2006.201.04:24:53.94#ibcon#end of sib2, iclass 32, count 0 2006.201.04:24:53.94#ibcon#*mode == 0, iclass 32, count 0 2006.201.04:24:53.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.04:24:53.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:24:53.94#ibcon#*before write, iclass 32, count 0 2006.201.04:24:53.94#ibcon#enter sib2, iclass 32, count 0 2006.201.04:24:53.94#ibcon#flushed, iclass 32, count 0 2006.201.04:24:53.94#ibcon#about to write, iclass 32, count 0 2006.201.04:24:53.94#ibcon#wrote, iclass 32, count 0 2006.201.04:24:53.94#ibcon#about to read 3, iclass 32, count 0 2006.201.04:24:53.98#ibcon#read 3, iclass 32, count 0 2006.201.04:24:53.98#ibcon#about to read 4, iclass 32, count 0 2006.201.04:24:53.98#ibcon#read 4, iclass 32, count 0 2006.201.04:24:53.98#ibcon#about to read 5, iclass 32, count 0 2006.201.04:24:53.98#ibcon#read 5, iclass 32, count 0 2006.201.04:24:53.98#ibcon#about to read 6, iclass 32, count 0 2006.201.04:24:53.98#ibcon#read 6, iclass 32, count 0 2006.201.04:24:53.98#ibcon#end of sib2, iclass 32, count 0 2006.201.04:24:53.98#ibcon#*after write, iclass 32, count 0 2006.201.04:24:53.98#ibcon#*before return 0, iclass 32, count 0 2006.201.04:24:53.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:53.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:53.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.04:24:53.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.04:24:53.98$vck44/va=8,4 2006.201.04:24:53.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.04:24:53.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.04:24:53.98#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:53.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:24:54.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:24:54.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:24:54.04#ibcon#enter wrdev, iclass 34, count 2 2006.201.04:24:54.04#ibcon#first serial, iclass 34, count 2 2006.201.04:24:54.04#ibcon#enter sib2, iclass 34, count 2 2006.201.04:24:54.04#ibcon#flushed, iclass 34, count 2 2006.201.04:24:54.04#ibcon#about to write, iclass 34, count 2 2006.201.04:24:54.04#ibcon#wrote, iclass 34, count 2 2006.201.04:24:54.04#ibcon#about to read 3, iclass 34, count 2 2006.201.04:24:54.06#ibcon#read 3, iclass 34, count 2 2006.201.04:24:54.06#ibcon#about to read 4, iclass 34, count 2 2006.201.04:24:54.06#ibcon#read 4, iclass 34, count 2 2006.201.04:24:54.06#ibcon#about to read 5, iclass 34, count 2 2006.201.04:24:54.06#ibcon#read 5, iclass 34, count 2 2006.201.04:24:54.06#ibcon#about to read 6, iclass 34, count 2 2006.201.04:24:54.06#ibcon#read 6, iclass 34, count 2 2006.201.04:24:54.06#ibcon#end of sib2, iclass 34, count 2 2006.201.04:24:54.06#ibcon#*mode == 0, iclass 34, count 2 2006.201.04:24:54.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.04:24:54.06#ibcon#[25=AT08-04\r\n] 2006.201.04:24:54.06#ibcon#*before write, iclass 34, count 2 2006.201.04:24:54.06#ibcon#enter sib2, iclass 34, count 2 2006.201.04:24:54.06#ibcon#flushed, iclass 34, count 2 2006.201.04:24:54.06#ibcon#about to write, iclass 34, count 2 2006.201.04:24:54.06#ibcon#wrote, iclass 34, count 2 2006.201.04:24:54.06#ibcon#about to read 3, iclass 34, count 2 2006.201.04:24:54.09#ibcon#read 3, iclass 34, count 2 2006.201.04:24:54.09#ibcon#about to read 4, iclass 34, count 2 2006.201.04:24:54.09#ibcon#read 4, iclass 34, count 2 2006.201.04:24:54.09#ibcon#about to read 5, iclass 34, count 2 2006.201.04:24:54.09#ibcon#read 5, iclass 34, count 2 2006.201.04:24:54.09#ibcon#about to read 6, iclass 34, count 2 2006.201.04:24:54.09#ibcon#read 6, iclass 34, count 2 2006.201.04:24:54.09#ibcon#end of sib2, iclass 34, count 2 2006.201.04:24:54.09#ibcon#*after write, iclass 34, count 2 2006.201.04:24:54.09#ibcon#*before return 0, iclass 34, count 2 2006.201.04:24:54.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:24:54.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:24:54.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.04:24:54.09#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:54.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:24:54.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:24:54.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:24:54.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.04:24:54.21#ibcon#first serial, iclass 34, count 0 2006.201.04:24:54.21#ibcon#enter sib2, iclass 34, count 0 2006.201.04:24:54.21#ibcon#flushed, iclass 34, count 0 2006.201.04:24:54.21#ibcon#about to write, iclass 34, count 0 2006.201.04:24:54.21#ibcon#wrote, iclass 34, count 0 2006.201.04:24:54.21#ibcon#about to read 3, iclass 34, count 0 2006.201.04:24:54.23#ibcon#read 3, iclass 34, count 0 2006.201.04:24:54.23#ibcon#about to read 4, iclass 34, count 0 2006.201.04:24:54.23#ibcon#read 4, iclass 34, count 0 2006.201.04:24:54.23#ibcon#about to read 5, iclass 34, count 0 2006.201.04:24:54.23#ibcon#read 5, iclass 34, count 0 2006.201.04:24:54.23#ibcon#about to read 6, iclass 34, count 0 2006.201.04:24:54.23#ibcon#read 6, iclass 34, count 0 2006.201.04:24:54.23#ibcon#end of sib2, iclass 34, count 0 2006.201.04:24:54.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.04:24:54.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.04:24:54.23#ibcon#[25=USB\r\n] 2006.201.04:24:54.23#ibcon#*before write, iclass 34, count 0 2006.201.04:24:54.23#ibcon#enter sib2, iclass 34, count 0 2006.201.04:24:54.23#ibcon#flushed, iclass 34, count 0 2006.201.04:24:54.23#ibcon#about to write, iclass 34, count 0 2006.201.04:24:54.23#ibcon#wrote, iclass 34, count 0 2006.201.04:24:54.23#ibcon#about to read 3, iclass 34, count 0 2006.201.04:24:54.26#ibcon#read 3, iclass 34, count 0 2006.201.04:24:54.26#ibcon#about to read 4, iclass 34, count 0 2006.201.04:24:54.26#ibcon#read 4, iclass 34, count 0 2006.201.04:24:54.26#ibcon#about to read 5, iclass 34, count 0 2006.201.04:24:54.26#ibcon#read 5, iclass 34, count 0 2006.201.04:24:54.26#ibcon#about to read 6, iclass 34, count 0 2006.201.04:24:54.26#ibcon#read 6, iclass 34, count 0 2006.201.04:24:54.26#ibcon#end of sib2, iclass 34, count 0 2006.201.04:24:54.26#ibcon#*after write, iclass 34, count 0 2006.201.04:24:54.26#ibcon#*before return 0, iclass 34, count 0 2006.201.04:24:54.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:24:54.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:24:54.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.04:24:54.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.04:24:54.26$vck44/vblo=1,629.99 2006.201.04:24:54.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.04:24:54.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.04:24:54.26#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:54.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:24:54.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:24:54.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:24:54.26#ibcon#enter wrdev, iclass 36, count 0 2006.201.04:24:54.26#ibcon#first serial, iclass 36, count 0 2006.201.04:24:54.26#ibcon#enter sib2, iclass 36, count 0 2006.201.04:24:54.26#ibcon#flushed, iclass 36, count 0 2006.201.04:24:54.26#ibcon#about to write, iclass 36, count 0 2006.201.04:24:54.26#ibcon#wrote, iclass 36, count 0 2006.201.04:24:54.26#ibcon#about to read 3, iclass 36, count 0 2006.201.04:24:54.28#ibcon#read 3, iclass 36, count 0 2006.201.04:24:54.28#ibcon#about to read 4, iclass 36, count 0 2006.201.04:24:54.28#ibcon#read 4, iclass 36, count 0 2006.201.04:24:54.28#ibcon#about to read 5, iclass 36, count 0 2006.201.04:24:54.28#ibcon#read 5, iclass 36, count 0 2006.201.04:24:54.28#ibcon#about to read 6, iclass 36, count 0 2006.201.04:24:54.28#ibcon#read 6, iclass 36, count 0 2006.201.04:24:54.28#ibcon#end of sib2, iclass 36, count 0 2006.201.04:24:54.28#ibcon#*mode == 0, iclass 36, count 0 2006.201.04:24:54.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.04:24:54.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:24:54.28#ibcon#*before write, iclass 36, count 0 2006.201.04:24:54.28#ibcon#enter sib2, iclass 36, count 0 2006.201.04:24:54.28#ibcon#flushed, iclass 36, count 0 2006.201.04:24:54.28#ibcon#about to write, iclass 36, count 0 2006.201.04:24:54.28#ibcon#wrote, iclass 36, count 0 2006.201.04:24:54.28#ibcon#about to read 3, iclass 36, count 0 2006.201.04:24:54.32#ibcon#read 3, iclass 36, count 0 2006.201.04:24:54.32#ibcon#about to read 4, iclass 36, count 0 2006.201.04:24:54.32#ibcon#read 4, iclass 36, count 0 2006.201.04:24:54.32#ibcon#about to read 5, iclass 36, count 0 2006.201.04:24:54.32#ibcon#read 5, iclass 36, count 0 2006.201.04:24:54.32#ibcon#about to read 6, iclass 36, count 0 2006.201.04:24:54.32#ibcon#read 6, iclass 36, count 0 2006.201.04:24:54.32#ibcon#end of sib2, iclass 36, count 0 2006.201.04:24:54.32#ibcon#*after write, iclass 36, count 0 2006.201.04:24:54.32#ibcon#*before return 0, iclass 36, count 0 2006.201.04:24:54.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:24:54.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:24:54.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.04:24:54.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.04:24:54.32$vck44/vb=1,4 2006.201.04:24:54.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.04:24:54.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.04:24:54.32#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:54.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:24:54.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:24:54.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:24:54.32#ibcon#enter wrdev, iclass 38, count 2 2006.201.04:24:54.32#ibcon#first serial, iclass 38, count 2 2006.201.04:24:54.32#ibcon#enter sib2, iclass 38, count 2 2006.201.04:24:54.32#ibcon#flushed, iclass 38, count 2 2006.201.04:24:54.32#ibcon#about to write, iclass 38, count 2 2006.201.04:24:54.32#ibcon#wrote, iclass 38, count 2 2006.201.04:24:54.32#ibcon#about to read 3, iclass 38, count 2 2006.201.04:24:54.34#ibcon#read 3, iclass 38, count 2 2006.201.04:24:54.34#ibcon#about to read 4, iclass 38, count 2 2006.201.04:24:54.34#ibcon#read 4, iclass 38, count 2 2006.201.04:24:54.34#ibcon#about to read 5, iclass 38, count 2 2006.201.04:24:54.34#ibcon#read 5, iclass 38, count 2 2006.201.04:24:54.34#ibcon#about to read 6, iclass 38, count 2 2006.201.04:24:54.34#ibcon#read 6, iclass 38, count 2 2006.201.04:24:54.34#ibcon#end of sib2, iclass 38, count 2 2006.201.04:24:54.34#ibcon#*mode == 0, iclass 38, count 2 2006.201.04:24:54.34#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.04:24:54.34#ibcon#[27=AT01-04\r\n] 2006.201.04:24:54.34#ibcon#*before write, iclass 38, count 2 2006.201.04:24:54.34#ibcon#enter sib2, iclass 38, count 2 2006.201.04:24:54.34#ibcon#flushed, iclass 38, count 2 2006.201.04:24:54.34#ibcon#about to write, iclass 38, count 2 2006.201.04:24:54.34#ibcon#wrote, iclass 38, count 2 2006.201.04:24:54.34#ibcon#about to read 3, iclass 38, count 2 2006.201.04:24:54.37#ibcon#read 3, iclass 38, count 2 2006.201.04:24:54.37#ibcon#about to read 4, iclass 38, count 2 2006.201.04:24:54.37#ibcon#read 4, iclass 38, count 2 2006.201.04:24:54.37#ibcon#about to read 5, iclass 38, count 2 2006.201.04:24:54.37#ibcon#read 5, iclass 38, count 2 2006.201.04:24:54.37#ibcon#about to read 6, iclass 38, count 2 2006.201.04:24:54.37#ibcon#read 6, iclass 38, count 2 2006.201.04:24:54.37#ibcon#end of sib2, iclass 38, count 2 2006.201.04:24:54.37#ibcon#*after write, iclass 38, count 2 2006.201.04:24:54.37#ibcon#*before return 0, iclass 38, count 2 2006.201.04:24:54.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:24:54.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:24:54.37#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.04:24:54.37#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:54.37#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:24:54.49#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:24:54.49#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:24:54.49#ibcon#enter wrdev, iclass 38, count 0 2006.201.04:24:54.49#ibcon#first serial, iclass 38, count 0 2006.201.04:24:54.49#ibcon#enter sib2, iclass 38, count 0 2006.201.04:24:54.49#ibcon#flushed, iclass 38, count 0 2006.201.04:24:54.49#ibcon#about to write, iclass 38, count 0 2006.201.04:24:54.49#ibcon#wrote, iclass 38, count 0 2006.201.04:24:54.49#ibcon#about to read 3, iclass 38, count 0 2006.201.04:24:54.51#ibcon#read 3, iclass 38, count 0 2006.201.04:24:54.51#ibcon#about to read 4, iclass 38, count 0 2006.201.04:24:54.51#ibcon#read 4, iclass 38, count 0 2006.201.04:24:54.51#ibcon#about to read 5, iclass 38, count 0 2006.201.04:24:54.51#ibcon#read 5, iclass 38, count 0 2006.201.04:24:54.51#ibcon#about to read 6, iclass 38, count 0 2006.201.04:24:54.51#ibcon#read 6, iclass 38, count 0 2006.201.04:24:54.51#ibcon#end of sib2, iclass 38, count 0 2006.201.04:24:54.51#ibcon#*mode == 0, iclass 38, count 0 2006.201.04:24:54.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.04:24:54.51#ibcon#[27=USB\r\n] 2006.201.04:24:54.51#ibcon#*before write, iclass 38, count 0 2006.201.04:24:54.51#ibcon#enter sib2, iclass 38, count 0 2006.201.04:24:54.51#ibcon#flushed, iclass 38, count 0 2006.201.04:24:54.51#ibcon#about to write, iclass 38, count 0 2006.201.04:24:54.51#ibcon#wrote, iclass 38, count 0 2006.201.04:24:54.51#ibcon#about to read 3, iclass 38, count 0 2006.201.04:24:54.54#ibcon#read 3, iclass 38, count 0 2006.201.04:24:54.54#ibcon#about to read 4, iclass 38, count 0 2006.201.04:24:54.54#ibcon#read 4, iclass 38, count 0 2006.201.04:24:54.54#ibcon#about to read 5, iclass 38, count 0 2006.201.04:24:54.54#ibcon#read 5, iclass 38, count 0 2006.201.04:24:54.54#ibcon#about to read 6, iclass 38, count 0 2006.201.04:24:54.54#ibcon#read 6, iclass 38, count 0 2006.201.04:24:54.54#ibcon#end of sib2, iclass 38, count 0 2006.201.04:24:54.54#ibcon#*after write, iclass 38, count 0 2006.201.04:24:54.54#ibcon#*before return 0, iclass 38, count 0 2006.201.04:24:54.54#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:24:54.54#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:24:54.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.04:24:54.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.04:24:54.54$vck44/vblo=2,634.99 2006.201.04:24:54.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.04:24:54.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.04:24:54.54#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:54.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:54.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:54.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:54.54#ibcon#enter wrdev, iclass 40, count 0 2006.201.04:24:54.54#ibcon#first serial, iclass 40, count 0 2006.201.04:24:54.54#ibcon#enter sib2, iclass 40, count 0 2006.201.04:24:54.54#ibcon#flushed, iclass 40, count 0 2006.201.04:24:54.54#ibcon#about to write, iclass 40, count 0 2006.201.04:24:54.54#ibcon#wrote, iclass 40, count 0 2006.201.04:24:54.54#ibcon#about to read 3, iclass 40, count 0 2006.201.04:24:54.56#ibcon#read 3, iclass 40, count 0 2006.201.04:24:54.56#ibcon#about to read 4, iclass 40, count 0 2006.201.04:24:54.56#ibcon#read 4, iclass 40, count 0 2006.201.04:24:54.56#ibcon#about to read 5, iclass 40, count 0 2006.201.04:24:54.56#ibcon#read 5, iclass 40, count 0 2006.201.04:24:54.56#ibcon#about to read 6, iclass 40, count 0 2006.201.04:24:54.56#ibcon#read 6, iclass 40, count 0 2006.201.04:24:54.56#ibcon#end of sib2, iclass 40, count 0 2006.201.04:24:54.56#ibcon#*mode == 0, iclass 40, count 0 2006.201.04:24:54.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.04:24:54.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:24:54.56#ibcon#*before write, iclass 40, count 0 2006.201.04:24:54.56#ibcon#enter sib2, iclass 40, count 0 2006.201.04:24:54.56#ibcon#flushed, iclass 40, count 0 2006.201.04:24:54.56#ibcon#about to write, iclass 40, count 0 2006.201.04:24:54.56#ibcon#wrote, iclass 40, count 0 2006.201.04:24:54.56#ibcon#about to read 3, iclass 40, count 0 2006.201.04:24:54.60#ibcon#read 3, iclass 40, count 0 2006.201.04:24:54.60#ibcon#about to read 4, iclass 40, count 0 2006.201.04:24:54.60#ibcon#read 4, iclass 40, count 0 2006.201.04:24:54.60#ibcon#about to read 5, iclass 40, count 0 2006.201.04:24:54.60#ibcon#read 5, iclass 40, count 0 2006.201.04:24:54.60#ibcon#about to read 6, iclass 40, count 0 2006.201.04:24:54.60#ibcon#read 6, iclass 40, count 0 2006.201.04:24:54.60#ibcon#end of sib2, iclass 40, count 0 2006.201.04:24:54.60#ibcon#*after write, iclass 40, count 0 2006.201.04:24:54.60#ibcon#*before return 0, iclass 40, count 0 2006.201.04:24:54.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:54.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:24:54.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.04:24:54.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.04:24:54.60$vck44/vb=2,5 2006.201.04:24:54.60#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.04:24:54.60#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.04:24:54.60#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:54.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:54.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:54.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:54.66#ibcon#enter wrdev, iclass 4, count 2 2006.201.04:24:54.66#ibcon#first serial, iclass 4, count 2 2006.201.04:24:54.66#ibcon#enter sib2, iclass 4, count 2 2006.201.04:24:54.66#ibcon#flushed, iclass 4, count 2 2006.201.04:24:54.66#ibcon#about to write, iclass 4, count 2 2006.201.04:24:54.66#ibcon#wrote, iclass 4, count 2 2006.201.04:24:54.66#ibcon#about to read 3, iclass 4, count 2 2006.201.04:24:54.68#ibcon#read 3, iclass 4, count 2 2006.201.04:24:54.68#ibcon#about to read 4, iclass 4, count 2 2006.201.04:24:54.68#ibcon#read 4, iclass 4, count 2 2006.201.04:24:54.68#ibcon#about to read 5, iclass 4, count 2 2006.201.04:24:54.68#ibcon#read 5, iclass 4, count 2 2006.201.04:24:54.68#ibcon#about to read 6, iclass 4, count 2 2006.201.04:24:54.68#ibcon#read 6, iclass 4, count 2 2006.201.04:24:54.68#ibcon#end of sib2, iclass 4, count 2 2006.201.04:24:54.68#ibcon#*mode == 0, iclass 4, count 2 2006.201.04:24:54.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.04:24:54.68#ibcon#[27=AT02-05\r\n] 2006.201.04:24:54.68#ibcon#*before write, iclass 4, count 2 2006.201.04:24:54.68#ibcon#enter sib2, iclass 4, count 2 2006.201.04:24:54.68#ibcon#flushed, iclass 4, count 2 2006.201.04:24:54.68#ibcon#about to write, iclass 4, count 2 2006.201.04:24:54.68#ibcon#wrote, iclass 4, count 2 2006.201.04:24:54.68#ibcon#about to read 3, iclass 4, count 2 2006.201.04:24:54.71#ibcon#read 3, iclass 4, count 2 2006.201.04:24:54.71#ibcon#about to read 4, iclass 4, count 2 2006.201.04:24:54.71#ibcon#read 4, iclass 4, count 2 2006.201.04:24:54.71#ibcon#about to read 5, iclass 4, count 2 2006.201.04:24:54.71#ibcon#read 5, iclass 4, count 2 2006.201.04:24:54.71#ibcon#about to read 6, iclass 4, count 2 2006.201.04:24:54.71#ibcon#read 6, iclass 4, count 2 2006.201.04:24:54.71#ibcon#end of sib2, iclass 4, count 2 2006.201.04:24:54.71#ibcon#*after write, iclass 4, count 2 2006.201.04:24:54.71#ibcon#*before return 0, iclass 4, count 2 2006.201.04:24:54.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:54.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:24:54.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.04:24:54.71#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:54.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:54.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:54.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:54.83#ibcon#enter wrdev, iclass 4, count 0 2006.201.04:24:54.83#ibcon#first serial, iclass 4, count 0 2006.201.04:24:54.83#ibcon#enter sib2, iclass 4, count 0 2006.201.04:24:54.83#ibcon#flushed, iclass 4, count 0 2006.201.04:24:54.83#ibcon#about to write, iclass 4, count 0 2006.201.04:24:54.83#ibcon#wrote, iclass 4, count 0 2006.201.04:24:54.83#ibcon#about to read 3, iclass 4, count 0 2006.201.04:24:54.85#ibcon#read 3, iclass 4, count 0 2006.201.04:24:54.85#ibcon#about to read 4, iclass 4, count 0 2006.201.04:24:54.85#ibcon#read 4, iclass 4, count 0 2006.201.04:24:54.85#ibcon#about to read 5, iclass 4, count 0 2006.201.04:24:54.85#ibcon#read 5, iclass 4, count 0 2006.201.04:24:54.85#ibcon#about to read 6, iclass 4, count 0 2006.201.04:24:54.85#ibcon#read 6, iclass 4, count 0 2006.201.04:24:54.85#ibcon#end of sib2, iclass 4, count 0 2006.201.04:24:54.85#ibcon#*mode == 0, iclass 4, count 0 2006.201.04:24:54.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.04:24:54.85#ibcon#[27=USB\r\n] 2006.201.04:24:54.85#ibcon#*before write, iclass 4, count 0 2006.201.04:24:54.85#ibcon#enter sib2, iclass 4, count 0 2006.201.04:24:54.85#ibcon#flushed, iclass 4, count 0 2006.201.04:24:54.85#ibcon#about to write, iclass 4, count 0 2006.201.04:24:54.85#ibcon#wrote, iclass 4, count 0 2006.201.04:24:54.85#ibcon#about to read 3, iclass 4, count 0 2006.201.04:24:54.88#ibcon#read 3, iclass 4, count 0 2006.201.04:24:54.88#ibcon#about to read 4, iclass 4, count 0 2006.201.04:24:54.88#ibcon#read 4, iclass 4, count 0 2006.201.04:24:54.88#ibcon#about to read 5, iclass 4, count 0 2006.201.04:24:54.88#ibcon#read 5, iclass 4, count 0 2006.201.04:24:54.88#ibcon#about to read 6, iclass 4, count 0 2006.201.04:24:54.88#ibcon#read 6, iclass 4, count 0 2006.201.04:24:54.88#ibcon#end of sib2, iclass 4, count 0 2006.201.04:24:54.88#ibcon#*after write, iclass 4, count 0 2006.201.04:24:54.88#ibcon#*before return 0, iclass 4, count 0 2006.201.04:24:54.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:54.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:24:54.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.04:24:54.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.04:24:54.88$vck44/vblo=3,649.99 2006.201.04:24:54.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.04:24:54.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.04:24:54.88#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:54.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:54.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:54.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:54.88#ibcon#enter wrdev, iclass 6, count 0 2006.201.04:24:54.88#ibcon#first serial, iclass 6, count 0 2006.201.04:24:54.88#ibcon#enter sib2, iclass 6, count 0 2006.201.04:24:54.88#ibcon#flushed, iclass 6, count 0 2006.201.04:24:54.88#ibcon#about to write, iclass 6, count 0 2006.201.04:24:54.88#ibcon#wrote, iclass 6, count 0 2006.201.04:24:54.88#ibcon#about to read 3, iclass 6, count 0 2006.201.04:24:54.90#ibcon#read 3, iclass 6, count 0 2006.201.04:24:54.90#ibcon#about to read 4, iclass 6, count 0 2006.201.04:24:54.90#ibcon#read 4, iclass 6, count 0 2006.201.04:24:54.90#ibcon#about to read 5, iclass 6, count 0 2006.201.04:24:54.90#ibcon#read 5, iclass 6, count 0 2006.201.04:24:54.90#ibcon#about to read 6, iclass 6, count 0 2006.201.04:24:54.90#ibcon#read 6, iclass 6, count 0 2006.201.04:24:54.90#ibcon#end of sib2, iclass 6, count 0 2006.201.04:24:54.90#ibcon#*mode == 0, iclass 6, count 0 2006.201.04:24:54.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.04:24:54.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:24:54.90#ibcon#*before write, iclass 6, count 0 2006.201.04:24:54.90#ibcon#enter sib2, iclass 6, count 0 2006.201.04:24:54.90#ibcon#flushed, iclass 6, count 0 2006.201.04:24:54.90#ibcon#about to write, iclass 6, count 0 2006.201.04:24:54.90#ibcon#wrote, iclass 6, count 0 2006.201.04:24:54.90#ibcon#about to read 3, iclass 6, count 0 2006.201.04:24:54.94#ibcon#read 3, iclass 6, count 0 2006.201.04:24:54.94#ibcon#about to read 4, iclass 6, count 0 2006.201.04:24:54.94#ibcon#read 4, iclass 6, count 0 2006.201.04:24:54.94#ibcon#about to read 5, iclass 6, count 0 2006.201.04:24:54.94#ibcon#read 5, iclass 6, count 0 2006.201.04:24:54.94#ibcon#about to read 6, iclass 6, count 0 2006.201.04:24:54.94#ibcon#read 6, iclass 6, count 0 2006.201.04:24:54.94#ibcon#end of sib2, iclass 6, count 0 2006.201.04:24:54.94#ibcon#*after write, iclass 6, count 0 2006.201.04:24:54.94#ibcon#*before return 0, iclass 6, count 0 2006.201.04:24:54.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:54.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:24:54.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.04:24:54.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.04:24:54.94$vck44/vb=3,4 2006.201.04:24:54.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.04:24:54.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.04:24:54.94#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:54.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:55.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:55.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:55.00#ibcon#enter wrdev, iclass 10, count 2 2006.201.04:24:55.00#ibcon#first serial, iclass 10, count 2 2006.201.04:24:55.00#ibcon#enter sib2, iclass 10, count 2 2006.201.04:24:55.00#ibcon#flushed, iclass 10, count 2 2006.201.04:24:55.00#ibcon#about to write, iclass 10, count 2 2006.201.04:24:55.00#ibcon#wrote, iclass 10, count 2 2006.201.04:24:55.00#ibcon#about to read 3, iclass 10, count 2 2006.201.04:24:55.02#ibcon#read 3, iclass 10, count 2 2006.201.04:24:55.02#ibcon#about to read 4, iclass 10, count 2 2006.201.04:24:55.02#ibcon#read 4, iclass 10, count 2 2006.201.04:24:55.02#ibcon#about to read 5, iclass 10, count 2 2006.201.04:24:55.02#ibcon#read 5, iclass 10, count 2 2006.201.04:24:55.02#ibcon#about to read 6, iclass 10, count 2 2006.201.04:24:55.02#ibcon#read 6, iclass 10, count 2 2006.201.04:24:55.02#ibcon#end of sib2, iclass 10, count 2 2006.201.04:24:55.02#ibcon#*mode == 0, iclass 10, count 2 2006.201.04:24:55.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.04:24:55.02#ibcon#[27=AT03-04\r\n] 2006.201.04:24:55.02#ibcon#*before write, iclass 10, count 2 2006.201.04:24:55.02#ibcon#enter sib2, iclass 10, count 2 2006.201.04:24:55.02#ibcon#flushed, iclass 10, count 2 2006.201.04:24:55.02#ibcon#about to write, iclass 10, count 2 2006.201.04:24:55.02#ibcon#wrote, iclass 10, count 2 2006.201.04:24:55.02#ibcon#about to read 3, iclass 10, count 2 2006.201.04:24:55.05#ibcon#read 3, iclass 10, count 2 2006.201.04:24:55.05#ibcon#about to read 4, iclass 10, count 2 2006.201.04:24:55.05#ibcon#read 4, iclass 10, count 2 2006.201.04:24:55.05#ibcon#about to read 5, iclass 10, count 2 2006.201.04:24:55.05#ibcon#read 5, iclass 10, count 2 2006.201.04:24:55.05#ibcon#about to read 6, iclass 10, count 2 2006.201.04:24:55.05#ibcon#read 6, iclass 10, count 2 2006.201.04:24:55.05#ibcon#end of sib2, iclass 10, count 2 2006.201.04:24:55.05#ibcon#*after write, iclass 10, count 2 2006.201.04:24:55.05#ibcon#*before return 0, iclass 10, count 2 2006.201.04:24:55.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:55.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:24:55.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.04:24:55.05#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:55.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:55.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:55.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:55.17#ibcon#enter wrdev, iclass 10, count 0 2006.201.04:24:55.17#ibcon#first serial, iclass 10, count 0 2006.201.04:24:55.17#ibcon#enter sib2, iclass 10, count 0 2006.201.04:24:55.17#ibcon#flushed, iclass 10, count 0 2006.201.04:24:55.17#ibcon#about to write, iclass 10, count 0 2006.201.04:24:55.17#ibcon#wrote, iclass 10, count 0 2006.201.04:24:55.17#ibcon#about to read 3, iclass 10, count 0 2006.201.04:24:55.19#ibcon#read 3, iclass 10, count 0 2006.201.04:24:55.19#ibcon#about to read 4, iclass 10, count 0 2006.201.04:24:55.19#ibcon#read 4, iclass 10, count 0 2006.201.04:24:55.19#ibcon#about to read 5, iclass 10, count 0 2006.201.04:24:55.19#ibcon#read 5, iclass 10, count 0 2006.201.04:24:55.19#ibcon#about to read 6, iclass 10, count 0 2006.201.04:24:55.19#ibcon#read 6, iclass 10, count 0 2006.201.04:24:55.19#ibcon#end of sib2, iclass 10, count 0 2006.201.04:24:55.19#ibcon#*mode == 0, iclass 10, count 0 2006.201.04:24:55.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.04:24:55.19#ibcon#[27=USB\r\n] 2006.201.04:24:55.19#ibcon#*before write, iclass 10, count 0 2006.201.04:24:55.19#ibcon#enter sib2, iclass 10, count 0 2006.201.04:24:55.19#ibcon#flushed, iclass 10, count 0 2006.201.04:24:55.19#ibcon#about to write, iclass 10, count 0 2006.201.04:24:55.19#ibcon#wrote, iclass 10, count 0 2006.201.04:24:55.19#ibcon#about to read 3, iclass 10, count 0 2006.201.04:24:55.22#ibcon#read 3, iclass 10, count 0 2006.201.04:24:55.22#ibcon#about to read 4, iclass 10, count 0 2006.201.04:24:55.22#ibcon#read 4, iclass 10, count 0 2006.201.04:24:55.22#ibcon#about to read 5, iclass 10, count 0 2006.201.04:24:55.22#ibcon#read 5, iclass 10, count 0 2006.201.04:24:55.22#ibcon#about to read 6, iclass 10, count 0 2006.201.04:24:55.22#ibcon#read 6, iclass 10, count 0 2006.201.04:24:55.22#ibcon#end of sib2, iclass 10, count 0 2006.201.04:24:55.22#ibcon#*after write, iclass 10, count 0 2006.201.04:24:55.22#ibcon#*before return 0, iclass 10, count 0 2006.201.04:24:55.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:55.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:24:55.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.04:24:55.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.04:24:55.22$vck44/vblo=4,679.99 2006.201.04:24:55.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.04:24:55.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.04:24:55.22#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:55.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:55.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:55.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:55.22#ibcon#enter wrdev, iclass 12, count 0 2006.201.04:24:55.22#ibcon#first serial, iclass 12, count 0 2006.201.04:24:55.22#ibcon#enter sib2, iclass 12, count 0 2006.201.04:24:55.22#ibcon#flushed, iclass 12, count 0 2006.201.04:24:55.22#ibcon#about to write, iclass 12, count 0 2006.201.04:24:55.22#ibcon#wrote, iclass 12, count 0 2006.201.04:24:55.22#ibcon#about to read 3, iclass 12, count 0 2006.201.04:24:55.24#ibcon#read 3, iclass 12, count 0 2006.201.04:24:55.24#ibcon#about to read 4, iclass 12, count 0 2006.201.04:24:55.24#ibcon#read 4, iclass 12, count 0 2006.201.04:24:55.24#ibcon#about to read 5, iclass 12, count 0 2006.201.04:24:55.24#ibcon#read 5, iclass 12, count 0 2006.201.04:24:55.24#ibcon#about to read 6, iclass 12, count 0 2006.201.04:24:55.24#ibcon#read 6, iclass 12, count 0 2006.201.04:24:55.24#ibcon#end of sib2, iclass 12, count 0 2006.201.04:24:55.24#ibcon#*mode == 0, iclass 12, count 0 2006.201.04:24:55.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.04:24:55.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:24:55.24#ibcon#*before write, iclass 12, count 0 2006.201.04:24:55.24#ibcon#enter sib2, iclass 12, count 0 2006.201.04:24:55.24#ibcon#flushed, iclass 12, count 0 2006.201.04:24:55.24#ibcon#about to write, iclass 12, count 0 2006.201.04:24:55.24#ibcon#wrote, iclass 12, count 0 2006.201.04:24:55.24#ibcon#about to read 3, iclass 12, count 0 2006.201.04:24:55.28#ibcon#read 3, iclass 12, count 0 2006.201.04:24:55.28#ibcon#about to read 4, iclass 12, count 0 2006.201.04:24:55.28#ibcon#read 4, iclass 12, count 0 2006.201.04:24:55.28#ibcon#about to read 5, iclass 12, count 0 2006.201.04:24:55.28#ibcon#read 5, iclass 12, count 0 2006.201.04:24:55.28#ibcon#about to read 6, iclass 12, count 0 2006.201.04:24:55.28#ibcon#read 6, iclass 12, count 0 2006.201.04:24:55.28#ibcon#end of sib2, iclass 12, count 0 2006.201.04:24:55.28#ibcon#*after write, iclass 12, count 0 2006.201.04:24:55.28#ibcon#*before return 0, iclass 12, count 0 2006.201.04:24:55.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:55.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:24:55.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.04:24:55.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.04:24:55.28$vck44/vb=4,5 2006.201.04:24:55.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.04:24:55.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.04:24:55.28#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:55.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:55.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:55.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:55.34#ibcon#enter wrdev, iclass 14, count 2 2006.201.04:24:55.34#ibcon#first serial, iclass 14, count 2 2006.201.04:24:55.34#ibcon#enter sib2, iclass 14, count 2 2006.201.04:24:55.34#ibcon#flushed, iclass 14, count 2 2006.201.04:24:55.34#ibcon#about to write, iclass 14, count 2 2006.201.04:24:55.34#ibcon#wrote, iclass 14, count 2 2006.201.04:24:55.34#ibcon#about to read 3, iclass 14, count 2 2006.201.04:24:55.36#ibcon#read 3, iclass 14, count 2 2006.201.04:24:55.36#ibcon#about to read 4, iclass 14, count 2 2006.201.04:24:55.36#ibcon#read 4, iclass 14, count 2 2006.201.04:24:55.36#ibcon#about to read 5, iclass 14, count 2 2006.201.04:24:55.36#ibcon#read 5, iclass 14, count 2 2006.201.04:24:55.36#ibcon#about to read 6, iclass 14, count 2 2006.201.04:24:55.36#ibcon#read 6, iclass 14, count 2 2006.201.04:24:55.36#ibcon#end of sib2, iclass 14, count 2 2006.201.04:24:55.36#ibcon#*mode == 0, iclass 14, count 2 2006.201.04:24:55.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.04:24:55.36#ibcon#[27=AT04-05\r\n] 2006.201.04:24:55.36#ibcon#*before write, iclass 14, count 2 2006.201.04:24:55.36#ibcon#enter sib2, iclass 14, count 2 2006.201.04:24:55.36#ibcon#flushed, iclass 14, count 2 2006.201.04:24:55.36#ibcon#about to write, iclass 14, count 2 2006.201.04:24:55.36#ibcon#wrote, iclass 14, count 2 2006.201.04:24:55.36#ibcon#about to read 3, iclass 14, count 2 2006.201.04:24:55.39#ibcon#read 3, iclass 14, count 2 2006.201.04:24:55.39#ibcon#about to read 4, iclass 14, count 2 2006.201.04:24:55.39#ibcon#read 4, iclass 14, count 2 2006.201.04:24:55.39#ibcon#about to read 5, iclass 14, count 2 2006.201.04:24:55.39#ibcon#read 5, iclass 14, count 2 2006.201.04:24:55.39#ibcon#about to read 6, iclass 14, count 2 2006.201.04:24:55.39#ibcon#read 6, iclass 14, count 2 2006.201.04:24:55.39#ibcon#end of sib2, iclass 14, count 2 2006.201.04:24:55.39#ibcon#*after write, iclass 14, count 2 2006.201.04:24:55.39#ibcon#*before return 0, iclass 14, count 2 2006.201.04:24:55.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:55.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:24:55.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.04:24:55.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:55.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:55.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:55.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:55.51#ibcon#enter wrdev, iclass 14, count 0 2006.201.04:24:55.51#ibcon#first serial, iclass 14, count 0 2006.201.04:24:55.51#ibcon#enter sib2, iclass 14, count 0 2006.201.04:24:55.51#ibcon#flushed, iclass 14, count 0 2006.201.04:24:55.51#ibcon#about to write, iclass 14, count 0 2006.201.04:24:55.51#ibcon#wrote, iclass 14, count 0 2006.201.04:24:55.51#ibcon#about to read 3, iclass 14, count 0 2006.201.04:24:55.53#ibcon#read 3, iclass 14, count 0 2006.201.04:24:55.53#ibcon#about to read 4, iclass 14, count 0 2006.201.04:24:55.53#ibcon#read 4, iclass 14, count 0 2006.201.04:24:55.53#ibcon#about to read 5, iclass 14, count 0 2006.201.04:24:55.53#ibcon#read 5, iclass 14, count 0 2006.201.04:24:55.53#ibcon#about to read 6, iclass 14, count 0 2006.201.04:24:55.53#ibcon#read 6, iclass 14, count 0 2006.201.04:24:55.53#ibcon#end of sib2, iclass 14, count 0 2006.201.04:24:55.53#ibcon#*mode == 0, iclass 14, count 0 2006.201.04:24:55.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.04:24:55.53#ibcon#[27=USB\r\n] 2006.201.04:24:55.53#ibcon#*before write, iclass 14, count 0 2006.201.04:24:55.53#ibcon#enter sib2, iclass 14, count 0 2006.201.04:24:55.53#ibcon#flushed, iclass 14, count 0 2006.201.04:24:55.53#ibcon#about to write, iclass 14, count 0 2006.201.04:24:55.53#ibcon#wrote, iclass 14, count 0 2006.201.04:24:55.53#ibcon#about to read 3, iclass 14, count 0 2006.201.04:24:55.56#ibcon#read 3, iclass 14, count 0 2006.201.04:24:55.56#ibcon#about to read 4, iclass 14, count 0 2006.201.04:24:55.56#ibcon#read 4, iclass 14, count 0 2006.201.04:24:55.56#ibcon#about to read 5, iclass 14, count 0 2006.201.04:24:55.56#ibcon#read 5, iclass 14, count 0 2006.201.04:24:55.56#ibcon#about to read 6, iclass 14, count 0 2006.201.04:24:55.56#ibcon#read 6, iclass 14, count 0 2006.201.04:24:55.56#ibcon#end of sib2, iclass 14, count 0 2006.201.04:24:55.56#ibcon#*after write, iclass 14, count 0 2006.201.04:24:55.56#ibcon#*before return 0, iclass 14, count 0 2006.201.04:24:55.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:55.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:24:55.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.04:24:55.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.04:24:55.56$vck44/vblo=5,709.99 2006.201.04:24:55.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.04:24:55.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.04:24:55.56#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:55.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:55.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:55.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:55.56#ibcon#enter wrdev, iclass 16, count 0 2006.201.04:24:55.56#ibcon#first serial, iclass 16, count 0 2006.201.04:24:55.56#ibcon#enter sib2, iclass 16, count 0 2006.201.04:24:55.56#ibcon#flushed, iclass 16, count 0 2006.201.04:24:55.56#ibcon#about to write, iclass 16, count 0 2006.201.04:24:55.56#ibcon#wrote, iclass 16, count 0 2006.201.04:24:55.56#ibcon#about to read 3, iclass 16, count 0 2006.201.04:24:55.58#ibcon#read 3, iclass 16, count 0 2006.201.04:24:55.58#ibcon#about to read 4, iclass 16, count 0 2006.201.04:24:55.58#ibcon#read 4, iclass 16, count 0 2006.201.04:24:55.58#ibcon#about to read 5, iclass 16, count 0 2006.201.04:24:55.58#ibcon#read 5, iclass 16, count 0 2006.201.04:24:55.58#ibcon#about to read 6, iclass 16, count 0 2006.201.04:24:55.58#ibcon#read 6, iclass 16, count 0 2006.201.04:24:55.58#ibcon#end of sib2, iclass 16, count 0 2006.201.04:24:55.58#ibcon#*mode == 0, iclass 16, count 0 2006.201.04:24:55.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.04:24:55.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:24:55.58#ibcon#*before write, iclass 16, count 0 2006.201.04:24:55.58#ibcon#enter sib2, iclass 16, count 0 2006.201.04:24:55.58#ibcon#flushed, iclass 16, count 0 2006.201.04:24:55.58#ibcon#about to write, iclass 16, count 0 2006.201.04:24:55.58#ibcon#wrote, iclass 16, count 0 2006.201.04:24:55.58#ibcon#about to read 3, iclass 16, count 0 2006.201.04:24:55.62#ibcon#read 3, iclass 16, count 0 2006.201.04:24:55.62#ibcon#about to read 4, iclass 16, count 0 2006.201.04:24:55.62#ibcon#read 4, iclass 16, count 0 2006.201.04:24:55.62#ibcon#about to read 5, iclass 16, count 0 2006.201.04:24:55.62#ibcon#read 5, iclass 16, count 0 2006.201.04:24:55.62#ibcon#about to read 6, iclass 16, count 0 2006.201.04:24:55.62#ibcon#read 6, iclass 16, count 0 2006.201.04:24:55.62#ibcon#end of sib2, iclass 16, count 0 2006.201.04:24:55.62#ibcon#*after write, iclass 16, count 0 2006.201.04:24:55.62#ibcon#*before return 0, iclass 16, count 0 2006.201.04:24:55.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:55.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:24:55.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.04:24:55.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.04:24:55.62$vck44/vb=5,4 2006.201.04:24:55.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.04:24:55.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.04:24:55.62#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:55.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:55.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:55.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:55.68#ibcon#enter wrdev, iclass 18, count 2 2006.201.04:24:55.68#ibcon#first serial, iclass 18, count 2 2006.201.04:24:55.68#ibcon#enter sib2, iclass 18, count 2 2006.201.04:24:55.68#ibcon#flushed, iclass 18, count 2 2006.201.04:24:55.68#ibcon#about to write, iclass 18, count 2 2006.201.04:24:55.68#ibcon#wrote, iclass 18, count 2 2006.201.04:24:55.68#ibcon#about to read 3, iclass 18, count 2 2006.201.04:24:55.70#ibcon#read 3, iclass 18, count 2 2006.201.04:24:55.70#ibcon#about to read 4, iclass 18, count 2 2006.201.04:24:55.70#ibcon#read 4, iclass 18, count 2 2006.201.04:24:55.70#ibcon#about to read 5, iclass 18, count 2 2006.201.04:24:55.70#ibcon#read 5, iclass 18, count 2 2006.201.04:24:55.70#ibcon#about to read 6, iclass 18, count 2 2006.201.04:24:55.70#ibcon#read 6, iclass 18, count 2 2006.201.04:24:55.70#ibcon#end of sib2, iclass 18, count 2 2006.201.04:24:55.70#ibcon#*mode == 0, iclass 18, count 2 2006.201.04:24:55.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.04:24:55.70#ibcon#[27=AT05-04\r\n] 2006.201.04:24:55.70#ibcon#*before write, iclass 18, count 2 2006.201.04:24:55.70#ibcon#enter sib2, iclass 18, count 2 2006.201.04:24:55.70#ibcon#flushed, iclass 18, count 2 2006.201.04:24:55.70#ibcon#about to write, iclass 18, count 2 2006.201.04:24:55.70#ibcon#wrote, iclass 18, count 2 2006.201.04:24:55.70#ibcon#about to read 3, iclass 18, count 2 2006.201.04:24:55.73#ibcon#read 3, iclass 18, count 2 2006.201.04:24:55.73#ibcon#about to read 4, iclass 18, count 2 2006.201.04:24:55.73#ibcon#read 4, iclass 18, count 2 2006.201.04:24:55.73#ibcon#about to read 5, iclass 18, count 2 2006.201.04:24:55.73#ibcon#read 5, iclass 18, count 2 2006.201.04:24:55.73#ibcon#about to read 6, iclass 18, count 2 2006.201.04:24:55.73#ibcon#read 6, iclass 18, count 2 2006.201.04:24:55.73#ibcon#end of sib2, iclass 18, count 2 2006.201.04:24:55.73#ibcon#*after write, iclass 18, count 2 2006.201.04:24:55.73#ibcon#*before return 0, iclass 18, count 2 2006.201.04:24:55.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:55.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:24:55.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.04:24:55.73#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:55.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:55.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:55.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:55.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.04:24:55.85#ibcon#first serial, iclass 18, count 0 2006.201.04:24:55.85#ibcon#enter sib2, iclass 18, count 0 2006.201.04:24:55.85#ibcon#flushed, iclass 18, count 0 2006.201.04:24:55.85#ibcon#about to write, iclass 18, count 0 2006.201.04:24:55.85#ibcon#wrote, iclass 18, count 0 2006.201.04:24:55.85#ibcon#about to read 3, iclass 18, count 0 2006.201.04:24:55.87#ibcon#read 3, iclass 18, count 0 2006.201.04:24:55.87#ibcon#about to read 4, iclass 18, count 0 2006.201.04:24:55.87#ibcon#read 4, iclass 18, count 0 2006.201.04:24:55.87#ibcon#about to read 5, iclass 18, count 0 2006.201.04:24:55.87#ibcon#read 5, iclass 18, count 0 2006.201.04:24:55.87#ibcon#about to read 6, iclass 18, count 0 2006.201.04:24:55.87#ibcon#read 6, iclass 18, count 0 2006.201.04:24:55.87#ibcon#end of sib2, iclass 18, count 0 2006.201.04:24:55.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.04:24:55.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.04:24:55.87#ibcon#[27=USB\r\n] 2006.201.04:24:55.87#ibcon#*before write, iclass 18, count 0 2006.201.04:24:55.87#ibcon#enter sib2, iclass 18, count 0 2006.201.04:24:55.87#ibcon#flushed, iclass 18, count 0 2006.201.04:24:55.87#ibcon#about to write, iclass 18, count 0 2006.201.04:24:55.87#ibcon#wrote, iclass 18, count 0 2006.201.04:24:55.87#ibcon#about to read 3, iclass 18, count 0 2006.201.04:24:55.90#ibcon#read 3, iclass 18, count 0 2006.201.04:24:55.90#ibcon#about to read 4, iclass 18, count 0 2006.201.04:24:55.90#ibcon#read 4, iclass 18, count 0 2006.201.04:24:55.90#ibcon#about to read 5, iclass 18, count 0 2006.201.04:24:55.90#ibcon#read 5, iclass 18, count 0 2006.201.04:24:55.90#ibcon#about to read 6, iclass 18, count 0 2006.201.04:24:55.90#ibcon#read 6, iclass 18, count 0 2006.201.04:24:55.90#ibcon#end of sib2, iclass 18, count 0 2006.201.04:24:55.90#ibcon#*after write, iclass 18, count 0 2006.201.04:24:55.90#ibcon#*before return 0, iclass 18, count 0 2006.201.04:24:55.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:55.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:24:55.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.04:24:55.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.04:24:55.90$vck44/vblo=6,719.99 2006.201.04:24:55.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.04:24:55.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.04:24:55.90#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:55.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:55.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:55.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:55.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.04:24:55.90#ibcon#first serial, iclass 20, count 0 2006.201.04:24:55.90#ibcon#enter sib2, iclass 20, count 0 2006.201.04:24:55.90#ibcon#flushed, iclass 20, count 0 2006.201.04:24:55.90#ibcon#about to write, iclass 20, count 0 2006.201.04:24:55.90#ibcon#wrote, iclass 20, count 0 2006.201.04:24:55.90#ibcon#about to read 3, iclass 20, count 0 2006.201.04:24:55.92#ibcon#read 3, iclass 20, count 0 2006.201.04:24:55.92#ibcon#about to read 4, iclass 20, count 0 2006.201.04:24:55.92#ibcon#read 4, iclass 20, count 0 2006.201.04:24:55.92#ibcon#about to read 5, iclass 20, count 0 2006.201.04:24:55.92#ibcon#read 5, iclass 20, count 0 2006.201.04:24:55.92#ibcon#about to read 6, iclass 20, count 0 2006.201.04:24:55.92#ibcon#read 6, iclass 20, count 0 2006.201.04:24:55.92#ibcon#end of sib2, iclass 20, count 0 2006.201.04:24:55.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.04:24:55.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.04:24:55.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:24:55.92#ibcon#*before write, iclass 20, count 0 2006.201.04:24:55.92#ibcon#enter sib2, iclass 20, count 0 2006.201.04:24:55.92#ibcon#flushed, iclass 20, count 0 2006.201.04:24:55.92#ibcon#about to write, iclass 20, count 0 2006.201.04:24:55.92#ibcon#wrote, iclass 20, count 0 2006.201.04:24:55.92#ibcon#about to read 3, iclass 20, count 0 2006.201.04:24:55.96#ibcon#read 3, iclass 20, count 0 2006.201.04:24:55.96#ibcon#about to read 4, iclass 20, count 0 2006.201.04:24:55.96#ibcon#read 4, iclass 20, count 0 2006.201.04:24:55.96#ibcon#about to read 5, iclass 20, count 0 2006.201.04:24:55.96#ibcon#read 5, iclass 20, count 0 2006.201.04:24:55.96#ibcon#about to read 6, iclass 20, count 0 2006.201.04:24:55.96#ibcon#read 6, iclass 20, count 0 2006.201.04:24:55.96#ibcon#end of sib2, iclass 20, count 0 2006.201.04:24:55.96#ibcon#*after write, iclass 20, count 0 2006.201.04:24:55.96#ibcon#*before return 0, iclass 20, count 0 2006.201.04:24:55.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:55.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:24:55.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.04:24:55.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.04:24:55.96$vck44/vb=6,4 2006.201.04:24:55.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.04:24:55.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.04:24:55.96#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:55.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:56.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:56.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:56.02#ibcon#enter wrdev, iclass 22, count 2 2006.201.04:24:56.02#ibcon#first serial, iclass 22, count 2 2006.201.04:24:56.02#ibcon#enter sib2, iclass 22, count 2 2006.201.04:24:56.02#ibcon#flushed, iclass 22, count 2 2006.201.04:24:56.02#ibcon#about to write, iclass 22, count 2 2006.201.04:24:56.02#ibcon#wrote, iclass 22, count 2 2006.201.04:24:56.02#ibcon#about to read 3, iclass 22, count 2 2006.201.04:24:56.04#ibcon#read 3, iclass 22, count 2 2006.201.04:24:56.04#ibcon#about to read 4, iclass 22, count 2 2006.201.04:24:56.04#ibcon#read 4, iclass 22, count 2 2006.201.04:24:56.04#ibcon#about to read 5, iclass 22, count 2 2006.201.04:24:56.04#ibcon#read 5, iclass 22, count 2 2006.201.04:24:56.04#ibcon#about to read 6, iclass 22, count 2 2006.201.04:24:56.04#ibcon#read 6, iclass 22, count 2 2006.201.04:24:56.04#ibcon#end of sib2, iclass 22, count 2 2006.201.04:24:56.04#ibcon#*mode == 0, iclass 22, count 2 2006.201.04:24:56.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.04:24:56.04#ibcon#[27=AT06-04\r\n] 2006.201.04:24:56.04#ibcon#*before write, iclass 22, count 2 2006.201.04:24:56.04#ibcon#enter sib2, iclass 22, count 2 2006.201.04:24:56.04#ibcon#flushed, iclass 22, count 2 2006.201.04:24:56.04#ibcon#about to write, iclass 22, count 2 2006.201.04:24:56.04#ibcon#wrote, iclass 22, count 2 2006.201.04:24:56.04#ibcon#about to read 3, iclass 22, count 2 2006.201.04:24:56.07#ibcon#read 3, iclass 22, count 2 2006.201.04:24:56.07#ibcon#about to read 4, iclass 22, count 2 2006.201.04:24:56.07#ibcon#read 4, iclass 22, count 2 2006.201.04:24:56.07#ibcon#about to read 5, iclass 22, count 2 2006.201.04:24:56.07#ibcon#read 5, iclass 22, count 2 2006.201.04:24:56.07#ibcon#about to read 6, iclass 22, count 2 2006.201.04:24:56.07#ibcon#read 6, iclass 22, count 2 2006.201.04:24:56.07#ibcon#end of sib2, iclass 22, count 2 2006.201.04:24:56.07#ibcon#*after write, iclass 22, count 2 2006.201.04:24:56.07#ibcon#*before return 0, iclass 22, count 2 2006.201.04:24:56.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:56.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:24:56.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.04:24:56.07#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:56.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:56.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:56.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:56.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.04:24:56.19#ibcon#first serial, iclass 22, count 0 2006.201.04:24:56.19#ibcon#enter sib2, iclass 22, count 0 2006.201.04:24:56.19#ibcon#flushed, iclass 22, count 0 2006.201.04:24:56.19#ibcon#about to write, iclass 22, count 0 2006.201.04:24:56.19#ibcon#wrote, iclass 22, count 0 2006.201.04:24:56.19#ibcon#about to read 3, iclass 22, count 0 2006.201.04:24:56.21#ibcon#read 3, iclass 22, count 0 2006.201.04:24:56.21#ibcon#about to read 4, iclass 22, count 0 2006.201.04:24:56.21#ibcon#read 4, iclass 22, count 0 2006.201.04:24:56.21#ibcon#about to read 5, iclass 22, count 0 2006.201.04:24:56.21#ibcon#read 5, iclass 22, count 0 2006.201.04:24:56.21#ibcon#about to read 6, iclass 22, count 0 2006.201.04:24:56.21#ibcon#read 6, iclass 22, count 0 2006.201.04:24:56.21#ibcon#end of sib2, iclass 22, count 0 2006.201.04:24:56.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.04:24:56.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.04:24:56.21#ibcon#[27=USB\r\n] 2006.201.04:24:56.21#ibcon#*before write, iclass 22, count 0 2006.201.04:24:56.21#ibcon#enter sib2, iclass 22, count 0 2006.201.04:24:56.21#ibcon#flushed, iclass 22, count 0 2006.201.04:24:56.21#ibcon#about to write, iclass 22, count 0 2006.201.04:24:56.21#ibcon#wrote, iclass 22, count 0 2006.201.04:24:56.21#ibcon#about to read 3, iclass 22, count 0 2006.201.04:24:56.24#ibcon#read 3, iclass 22, count 0 2006.201.04:24:56.24#ibcon#about to read 4, iclass 22, count 0 2006.201.04:24:56.24#ibcon#read 4, iclass 22, count 0 2006.201.04:24:56.24#ibcon#about to read 5, iclass 22, count 0 2006.201.04:24:56.24#ibcon#read 5, iclass 22, count 0 2006.201.04:24:56.24#ibcon#about to read 6, iclass 22, count 0 2006.201.04:24:56.24#ibcon#read 6, iclass 22, count 0 2006.201.04:24:56.24#ibcon#end of sib2, iclass 22, count 0 2006.201.04:24:56.24#ibcon#*after write, iclass 22, count 0 2006.201.04:24:56.24#ibcon#*before return 0, iclass 22, count 0 2006.201.04:24:56.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:56.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:24:56.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.04:24:56.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.04:24:56.24$vck44/vblo=7,734.99 2006.201.04:24:56.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.04:24:56.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.04:24:56.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:56.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:56.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:56.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:56.24#ibcon#enter wrdev, iclass 24, count 0 2006.201.04:24:56.24#ibcon#first serial, iclass 24, count 0 2006.201.04:24:56.24#ibcon#enter sib2, iclass 24, count 0 2006.201.04:24:56.24#ibcon#flushed, iclass 24, count 0 2006.201.04:24:56.24#ibcon#about to write, iclass 24, count 0 2006.201.04:24:56.24#ibcon#wrote, iclass 24, count 0 2006.201.04:24:56.24#ibcon#about to read 3, iclass 24, count 0 2006.201.04:24:56.26#ibcon#read 3, iclass 24, count 0 2006.201.04:24:56.26#ibcon#about to read 4, iclass 24, count 0 2006.201.04:24:56.26#ibcon#read 4, iclass 24, count 0 2006.201.04:24:56.26#ibcon#about to read 5, iclass 24, count 0 2006.201.04:24:56.26#ibcon#read 5, iclass 24, count 0 2006.201.04:24:56.26#ibcon#about to read 6, iclass 24, count 0 2006.201.04:24:56.26#ibcon#read 6, iclass 24, count 0 2006.201.04:24:56.26#ibcon#end of sib2, iclass 24, count 0 2006.201.04:24:56.26#ibcon#*mode == 0, iclass 24, count 0 2006.201.04:24:56.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.04:24:56.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:24:56.26#ibcon#*before write, iclass 24, count 0 2006.201.04:24:56.26#ibcon#enter sib2, iclass 24, count 0 2006.201.04:24:56.26#ibcon#flushed, iclass 24, count 0 2006.201.04:24:56.26#ibcon#about to write, iclass 24, count 0 2006.201.04:24:56.26#ibcon#wrote, iclass 24, count 0 2006.201.04:24:56.26#ibcon#about to read 3, iclass 24, count 0 2006.201.04:24:56.30#ibcon#read 3, iclass 24, count 0 2006.201.04:24:56.30#ibcon#about to read 4, iclass 24, count 0 2006.201.04:24:56.30#ibcon#read 4, iclass 24, count 0 2006.201.04:24:56.30#ibcon#about to read 5, iclass 24, count 0 2006.201.04:24:56.30#ibcon#read 5, iclass 24, count 0 2006.201.04:24:56.30#ibcon#about to read 6, iclass 24, count 0 2006.201.04:24:56.30#ibcon#read 6, iclass 24, count 0 2006.201.04:24:56.30#ibcon#end of sib2, iclass 24, count 0 2006.201.04:24:56.30#ibcon#*after write, iclass 24, count 0 2006.201.04:24:56.30#ibcon#*before return 0, iclass 24, count 0 2006.201.04:24:56.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:56.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:24:56.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.04:24:56.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.04:24:56.30$vck44/vb=7,4 2006.201.04:24:56.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.04:24:56.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.04:24:56.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:56.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:56.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:56.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:56.36#ibcon#enter wrdev, iclass 26, count 2 2006.201.04:24:56.36#ibcon#first serial, iclass 26, count 2 2006.201.04:24:56.36#ibcon#enter sib2, iclass 26, count 2 2006.201.04:24:56.36#ibcon#flushed, iclass 26, count 2 2006.201.04:24:56.36#ibcon#about to write, iclass 26, count 2 2006.201.04:24:56.36#ibcon#wrote, iclass 26, count 2 2006.201.04:24:56.36#ibcon#about to read 3, iclass 26, count 2 2006.201.04:24:56.38#ibcon#read 3, iclass 26, count 2 2006.201.04:24:56.38#ibcon#about to read 4, iclass 26, count 2 2006.201.04:24:56.38#ibcon#read 4, iclass 26, count 2 2006.201.04:24:56.38#ibcon#about to read 5, iclass 26, count 2 2006.201.04:24:56.38#ibcon#read 5, iclass 26, count 2 2006.201.04:24:56.38#ibcon#about to read 6, iclass 26, count 2 2006.201.04:24:56.38#ibcon#read 6, iclass 26, count 2 2006.201.04:24:56.38#ibcon#end of sib2, iclass 26, count 2 2006.201.04:24:56.38#ibcon#*mode == 0, iclass 26, count 2 2006.201.04:24:56.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.04:24:56.38#ibcon#[27=AT07-04\r\n] 2006.201.04:24:56.38#ibcon#*before write, iclass 26, count 2 2006.201.04:24:56.38#ibcon#enter sib2, iclass 26, count 2 2006.201.04:24:56.38#ibcon#flushed, iclass 26, count 2 2006.201.04:24:56.38#ibcon#about to write, iclass 26, count 2 2006.201.04:24:56.38#ibcon#wrote, iclass 26, count 2 2006.201.04:24:56.38#ibcon#about to read 3, iclass 26, count 2 2006.201.04:24:56.41#ibcon#read 3, iclass 26, count 2 2006.201.04:24:56.41#ibcon#about to read 4, iclass 26, count 2 2006.201.04:24:56.41#ibcon#read 4, iclass 26, count 2 2006.201.04:24:56.41#ibcon#about to read 5, iclass 26, count 2 2006.201.04:24:56.41#ibcon#read 5, iclass 26, count 2 2006.201.04:24:56.41#ibcon#about to read 6, iclass 26, count 2 2006.201.04:24:56.41#ibcon#read 6, iclass 26, count 2 2006.201.04:24:56.41#ibcon#end of sib2, iclass 26, count 2 2006.201.04:24:56.41#ibcon#*after write, iclass 26, count 2 2006.201.04:24:56.41#ibcon#*before return 0, iclass 26, count 2 2006.201.04:24:56.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:56.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:24:56.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.04:24:56.41#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:56.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:56.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:56.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:56.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.04:24:56.53#ibcon#first serial, iclass 26, count 0 2006.201.04:24:56.53#ibcon#enter sib2, iclass 26, count 0 2006.201.04:24:56.53#ibcon#flushed, iclass 26, count 0 2006.201.04:24:56.53#ibcon#about to write, iclass 26, count 0 2006.201.04:24:56.53#ibcon#wrote, iclass 26, count 0 2006.201.04:24:56.53#ibcon#about to read 3, iclass 26, count 0 2006.201.04:24:56.55#ibcon#read 3, iclass 26, count 0 2006.201.04:24:56.55#ibcon#about to read 4, iclass 26, count 0 2006.201.04:24:56.55#ibcon#read 4, iclass 26, count 0 2006.201.04:24:56.55#ibcon#about to read 5, iclass 26, count 0 2006.201.04:24:56.55#ibcon#read 5, iclass 26, count 0 2006.201.04:24:56.55#ibcon#about to read 6, iclass 26, count 0 2006.201.04:24:56.55#ibcon#read 6, iclass 26, count 0 2006.201.04:24:56.55#ibcon#end of sib2, iclass 26, count 0 2006.201.04:24:56.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.04:24:56.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.04:24:56.55#ibcon#[27=USB\r\n] 2006.201.04:24:56.55#ibcon#*before write, iclass 26, count 0 2006.201.04:24:56.55#ibcon#enter sib2, iclass 26, count 0 2006.201.04:24:56.55#ibcon#flushed, iclass 26, count 0 2006.201.04:24:56.55#ibcon#about to write, iclass 26, count 0 2006.201.04:24:56.55#ibcon#wrote, iclass 26, count 0 2006.201.04:24:56.55#ibcon#about to read 3, iclass 26, count 0 2006.201.04:24:56.58#ibcon#read 3, iclass 26, count 0 2006.201.04:24:56.58#ibcon#about to read 4, iclass 26, count 0 2006.201.04:24:56.58#ibcon#read 4, iclass 26, count 0 2006.201.04:24:56.58#ibcon#about to read 5, iclass 26, count 0 2006.201.04:24:56.58#ibcon#read 5, iclass 26, count 0 2006.201.04:24:56.58#ibcon#about to read 6, iclass 26, count 0 2006.201.04:24:56.58#ibcon#read 6, iclass 26, count 0 2006.201.04:24:56.58#ibcon#end of sib2, iclass 26, count 0 2006.201.04:24:56.58#ibcon#*after write, iclass 26, count 0 2006.201.04:24:56.58#ibcon#*before return 0, iclass 26, count 0 2006.201.04:24:56.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:56.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:24:56.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.04:24:56.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.04:24:56.58$vck44/vblo=8,744.99 2006.201.04:24:56.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.04:24:56.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.04:24:56.58#ibcon#ireg 17 cls_cnt 0 2006.201.04:24:56.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:56.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:56.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:56.58#ibcon#enter wrdev, iclass 28, count 0 2006.201.04:24:56.58#ibcon#first serial, iclass 28, count 0 2006.201.04:24:56.58#ibcon#enter sib2, iclass 28, count 0 2006.201.04:24:56.58#ibcon#flushed, iclass 28, count 0 2006.201.04:24:56.58#ibcon#about to write, iclass 28, count 0 2006.201.04:24:56.58#ibcon#wrote, iclass 28, count 0 2006.201.04:24:56.58#ibcon#about to read 3, iclass 28, count 0 2006.201.04:24:56.60#ibcon#read 3, iclass 28, count 0 2006.201.04:24:56.60#ibcon#about to read 4, iclass 28, count 0 2006.201.04:24:56.60#ibcon#read 4, iclass 28, count 0 2006.201.04:24:56.60#ibcon#about to read 5, iclass 28, count 0 2006.201.04:24:56.60#ibcon#read 5, iclass 28, count 0 2006.201.04:24:56.60#ibcon#about to read 6, iclass 28, count 0 2006.201.04:24:56.60#ibcon#read 6, iclass 28, count 0 2006.201.04:24:56.60#ibcon#end of sib2, iclass 28, count 0 2006.201.04:24:56.60#ibcon#*mode == 0, iclass 28, count 0 2006.201.04:24:56.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.04:24:56.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:24:56.60#ibcon#*before write, iclass 28, count 0 2006.201.04:24:56.60#ibcon#enter sib2, iclass 28, count 0 2006.201.04:24:56.60#ibcon#flushed, iclass 28, count 0 2006.201.04:24:56.60#ibcon#about to write, iclass 28, count 0 2006.201.04:24:56.60#ibcon#wrote, iclass 28, count 0 2006.201.04:24:56.60#ibcon#about to read 3, iclass 28, count 0 2006.201.04:24:56.64#ibcon#read 3, iclass 28, count 0 2006.201.04:24:56.64#ibcon#about to read 4, iclass 28, count 0 2006.201.04:24:56.64#ibcon#read 4, iclass 28, count 0 2006.201.04:24:56.64#ibcon#about to read 5, iclass 28, count 0 2006.201.04:24:56.64#ibcon#read 5, iclass 28, count 0 2006.201.04:24:56.64#ibcon#about to read 6, iclass 28, count 0 2006.201.04:24:56.64#ibcon#read 6, iclass 28, count 0 2006.201.04:24:56.64#ibcon#end of sib2, iclass 28, count 0 2006.201.04:24:56.64#ibcon#*after write, iclass 28, count 0 2006.201.04:24:56.64#ibcon#*before return 0, iclass 28, count 0 2006.201.04:24:56.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:56.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:24:56.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.04:24:56.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.04:24:56.64$vck44/vb=8,4 2006.201.04:24:56.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.04:24:56.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.04:24:56.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:24:56.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:56.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:56.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:56.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.04:24:56.70#ibcon#first serial, iclass 30, count 2 2006.201.04:24:56.70#ibcon#enter sib2, iclass 30, count 2 2006.201.04:24:56.70#ibcon#flushed, iclass 30, count 2 2006.201.04:24:56.70#ibcon#about to write, iclass 30, count 2 2006.201.04:24:56.70#ibcon#wrote, iclass 30, count 2 2006.201.04:24:56.70#ibcon#about to read 3, iclass 30, count 2 2006.201.04:24:56.72#ibcon#read 3, iclass 30, count 2 2006.201.04:24:56.72#ibcon#about to read 4, iclass 30, count 2 2006.201.04:24:56.72#ibcon#read 4, iclass 30, count 2 2006.201.04:24:56.72#ibcon#about to read 5, iclass 30, count 2 2006.201.04:24:56.72#ibcon#read 5, iclass 30, count 2 2006.201.04:24:56.72#ibcon#about to read 6, iclass 30, count 2 2006.201.04:24:56.72#ibcon#read 6, iclass 30, count 2 2006.201.04:24:56.72#ibcon#end of sib2, iclass 30, count 2 2006.201.04:24:56.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.04:24:56.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.04:24:56.72#ibcon#[27=AT08-04\r\n] 2006.201.04:24:56.72#ibcon#*before write, iclass 30, count 2 2006.201.04:24:56.72#ibcon#enter sib2, iclass 30, count 2 2006.201.04:24:56.72#ibcon#flushed, iclass 30, count 2 2006.201.04:24:56.72#ibcon#about to write, iclass 30, count 2 2006.201.04:24:56.72#ibcon#wrote, iclass 30, count 2 2006.201.04:24:56.72#ibcon#about to read 3, iclass 30, count 2 2006.201.04:24:56.75#ibcon#read 3, iclass 30, count 2 2006.201.04:24:56.75#ibcon#about to read 4, iclass 30, count 2 2006.201.04:24:56.75#ibcon#read 4, iclass 30, count 2 2006.201.04:24:56.75#ibcon#about to read 5, iclass 30, count 2 2006.201.04:24:56.75#ibcon#read 5, iclass 30, count 2 2006.201.04:24:56.75#ibcon#about to read 6, iclass 30, count 2 2006.201.04:24:56.75#ibcon#read 6, iclass 30, count 2 2006.201.04:24:56.75#ibcon#end of sib2, iclass 30, count 2 2006.201.04:24:56.75#ibcon#*after write, iclass 30, count 2 2006.201.04:24:56.75#ibcon#*before return 0, iclass 30, count 2 2006.201.04:24:56.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:56.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:24:56.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.04:24:56.75#ibcon#ireg 7 cls_cnt 0 2006.201.04:24:56.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:56.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:56.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:56.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.04:24:56.87#ibcon#first serial, iclass 30, count 0 2006.201.04:24:56.87#ibcon#enter sib2, iclass 30, count 0 2006.201.04:24:56.87#ibcon#flushed, iclass 30, count 0 2006.201.04:24:56.87#ibcon#about to write, iclass 30, count 0 2006.201.04:24:56.87#ibcon#wrote, iclass 30, count 0 2006.201.04:24:56.87#ibcon#about to read 3, iclass 30, count 0 2006.201.04:24:56.89#ibcon#read 3, iclass 30, count 0 2006.201.04:24:56.89#ibcon#about to read 4, iclass 30, count 0 2006.201.04:24:56.89#ibcon#read 4, iclass 30, count 0 2006.201.04:24:56.89#ibcon#about to read 5, iclass 30, count 0 2006.201.04:24:56.89#ibcon#read 5, iclass 30, count 0 2006.201.04:24:56.89#ibcon#about to read 6, iclass 30, count 0 2006.201.04:24:56.89#ibcon#read 6, iclass 30, count 0 2006.201.04:24:56.89#ibcon#end of sib2, iclass 30, count 0 2006.201.04:24:56.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.04:24:56.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.04:24:56.89#ibcon#[27=USB\r\n] 2006.201.04:24:56.89#ibcon#*before write, iclass 30, count 0 2006.201.04:24:56.89#ibcon#enter sib2, iclass 30, count 0 2006.201.04:24:56.89#ibcon#flushed, iclass 30, count 0 2006.201.04:24:56.89#ibcon#about to write, iclass 30, count 0 2006.201.04:24:56.89#ibcon#wrote, iclass 30, count 0 2006.201.04:24:56.89#ibcon#about to read 3, iclass 30, count 0 2006.201.04:24:56.92#ibcon#read 3, iclass 30, count 0 2006.201.04:24:56.92#ibcon#about to read 4, iclass 30, count 0 2006.201.04:24:56.92#ibcon#read 4, iclass 30, count 0 2006.201.04:24:56.92#ibcon#about to read 5, iclass 30, count 0 2006.201.04:24:56.92#ibcon#read 5, iclass 30, count 0 2006.201.04:24:56.92#ibcon#about to read 6, iclass 30, count 0 2006.201.04:24:56.92#ibcon#read 6, iclass 30, count 0 2006.201.04:24:56.92#ibcon#end of sib2, iclass 30, count 0 2006.201.04:24:56.92#ibcon#*after write, iclass 30, count 0 2006.201.04:24:56.92#ibcon#*before return 0, iclass 30, count 0 2006.201.04:24:56.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:56.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:24:56.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.04:24:56.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.04:24:56.92$vck44/vabw=wide 2006.201.04:24:56.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.04:24:56.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.04:24:56.92#ibcon#ireg 8 cls_cnt 0 2006.201.04:24:56.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:56.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:56.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:56.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.04:24:56.92#ibcon#first serial, iclass 32, count 0 2006.201.04:24:56.92#ibcon#enter sib2, iclass 32, count 0 2006.201.04:24:56.92#ibcon#flushed, iclass 32, count 0 2006.201.04:24:56.92#ibcon#about to write, iclass 32, count 0 2006.201.04:24:56.92#ibcon#wrote, iclass 32, count 0 2006.201.04:24:56.92#ibcon#about to read 3, iclass 32, count 0 2006.201.04:24:56.94#ibcon#read 3, iclass 32, count 0 2006.201.04:24:56.94#ibcon#about to read 4, iclass 32, count 0 2006.201.04:24:56.94#ibcon#read 4, iclass 32, count 0 2006.201.04:24:56.94#ibcon#about to read 5, iclass 32, count 0 2006.201.04:24:56.94#ibcon#read 5, iclass 32, count 0 2006.201.04:24:56.94#ibcon#about to read 6, iclass 32, count 0 2006.201.04:24:56.94#ibcon#read 6, iclass 32, count 0 2006.201.04:24:56.94#ibcon#end of sib2, iclass 32, count 0 2006.201.04:24:56.94#ibcon#*mode == 0, iclass 32, count 0 2006.201.04:24:56.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.04:24:56.94#ibcon#[25=BW32\r\n] 2006.201.04:24:56.94#ibcon#*before write, iclass 32, count 0 2006.201.04:24:56.94#ibcon#enter sib2, iclass 32, count 0 2006.201.04:24:56.94#ibcon#flushed, iclass 32, count 0 2006.201.04:24:56.94#ibcon#about to write, iclass 32, count 0 2006.201.04:24:56.94#ibcon#wrote, iclass 32, count 0 2006.201.04:24:56.94#ibcon#about to read 3, iclass 32, count 0 2006.201.04:24:56.97#ibcon#read 3, iclass 32, count 0 2006.201.04:24:56.97#ibcon#about to read 4, iclass 32, count 0 2006.201.04:24:56.97#ibcon#read 4, iclass 32, count 0 2006.201.04:24:56.97#ibcon#about to read 5, iclass 32, count 0 2006.201.04:24:56.97#ibcon#read 5, iclass 32, count 0 2006.201.04:24:56.97#ibcon#about to read 6, iclass 32, count 0 2006.201.04:24:56.97#ibcon#read 6, iclass 32, count 0 2006.201.04:24:56.97#ibcon#end of sib2, iclass 32, count 0 2006.201.04:24:56.97#ibcon#*after write, iclass 32, count 0 2006.201.04:24:56.97#ibcon#*before return 0, iclass 32, count 0 2006.201.04:24:56.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:56.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:24:56.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.04:24:56.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.04:24:56.97$vck44/vbbw=wide 2006.201.04:24:56.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.04:24:56.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.04:24:56.97#ibcon#ireg 8 cls_cnt 0 2006.201.04:24:56.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:24:57.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:24:57.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:24:57.04#ibcon#enter wrdev, iclass 34, count 0 2006.201.04:24:57.04#ibcon#first serial, iclass 34, count 0 2006.201.04:24:57.04#ibcon#enter sib2, iclass 34, count 0 2006.201.04:24:57.04#ibcon#flushed, iclass 34, count 0 2006.201.04:24:57.04#ibcon#about to write, iclass 34, count 0 2006.201.04:24:57.04#ibcon#wrote, iclass 34, count 0 2006.201.04:24:57.04#ibcon#about to read 3, iclass 34, count 0 2006.201.04:24:57.06#ibcon#read 3, iclass 34, count 0 2006.201.04:24:57.06#ibcon#about to read 4, iclass 34, count 0 2006.201.04:24:57.06#ibcon#read 4, iclass 34, count 0 2006.201.04:24:57.06#ibcon#about to read 5, iclass 34, count 0 2006.201.04:24:57.06#ibcon#read 5, iclass 34, count 0 2006.201.04:24:57.06#ibcon#about to read 6, iclass 34, count 0 2006.201.04:24:57.06#ibcon#read 6, iclass 34, count 0 2006.201.04:24:57.06#ibcon#end of sib2, iclass 34, count 0 2006.201.04:24:57.06#ibcon#*mode == 0, iclass 34, count 0 2006.201.04:24:57.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.04:24:57.06#ibcon#[27=BW32\r\n] 2006.201.04:24:57.06#ibcon#*before write, iclass 34, count 0 2006.201.04:24:57.06#ibcon#enter sib2, iclass 34, count 0 2006.201.04:24:57.06#ibcon#flushed, iclass 34, count 0 2006.201.04:24:57.06#ibcon#about to write, iclass 34, count 0 2006.201.04:24:57.06#ibcon#wrote, iclass 34, count 0 2006.201.04:24:57.06#ibcon#about to read 3, iclass 34, count 0 2006.201.04:24:57.09#ibcon#read 3, iclass 34, count 0 2006.201.04:24:57.09#ibcon#about to read 4, iclass 34, count 0 2006.201.04:24:57.09#ibcon#read 4, iclass 34, count 0 2006.201.04:24:57.09#ibcon#about to read 5, iclass 34, count 0 2006.201.04:24:57.09#ibcon#read 5, iclass 34, count 0 2006.201.04:24:57.09#ibcon#about to read 6, iclass 34, count 0 2006.201.04:24:57.09#ibcon#read 6, iclass 34, count 0 2006.201.04:24:57.09#ibcon#end of sib2, iclass 34, count 0 2006.201.04:24:57.09#ibcon#*after write, iclass 34, count 0 2006.201.04:24:57.09#ibcon#*before return 0, iclass 34, count 0 2006.201.04:24:57.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:24:57.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:24:57.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.04:24:57.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.04:24:57.09$setupk4/ifdk4 2006.201.04:24:57.09$ifdk4/lo= 2006.201.04:24:57.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:24:57.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:24:57.09$ifdk4/patch= 2006.201.04:24:57.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:24:57.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:24:57.09$setupk4/!*+20s 2006.201.04:24:58.46#abcon#<5=/04 2.8 4.7 22.99 901004.1\r\n> 2006.201.04:24:58.48#abcon#{5=INTERFACE CLEAR} 2006.201.04:24:58.54#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:25:06.14#trakl#Source acquired 2006.201.04:25:08.14#flagr#flagr/antenna,acquired 2006.201.04:25:08.63#abcon#<5=/04 2.8 4.6 22.98 901004.1\r\n> 2006.201.04:25:08.65#abcon#{5=INTERFACE CLEAR} 2006.201.04:25:08.71#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:25:11.59$setupk4/"tpicd 2006.201.04:25:11.59$setupk4/echo=off 2006.201.04:25:11.59$setupk4/xlog=off 2006.201.04:25:11.59:!2006.201.04:27:28 2006.201.04:27:28.00:preob 2006.201.04:27:28.14/onsource/TRACKING 2006.201.04:27:28.14:!2006.201.04:27:38 2006.201.04:27:38.00:"tape 2006.201.04:27:38.00:"st=record 2006.201.04:27:38.00:data_valid=on 2006.201.04:27:38.00:midob 2006.201.04:27:38.14/onsource/TRACKING 2006.201.04:27:38.14/wx/22.98,1004.1,91 2006.201.04:27:38.32/cable/+6.4666E-03 2006.201.04:27:39.41/va/01,08,usb,yes,31,33 2006.201.04:27:39.41/va/02,07,usb,yes,33,34 2006.201.04:27:39.41/va/03,08,usb,yes,30,31 2006.201.04:27:39.41/va/04,07,usb,yes,34,36 2006.201.04:27:39.41/va/05,04,usb,yes,30,31 2006.201.04:27:39.41/va/06,05,usb,yes,30,30 2006.201.04:27:39.41/va/07,05,usb,yes,29,30 2006.201.04:27:39.41/va/08,04,usb,yes,29,35 2006.201.04:27:39.64/valo/01,524.99,yes,locked 2006.201.04:27:39.64/valo/02,534.99,yes,locked 2006.201.04:27:39.64/valo/03,564.99,yes,locked 2006.201.04:27:39.64/valo/04,624.99,yes,locked 2006.201.04:27:39.64/valo/05,734.99,yes,locked 2006.201.04:27:39.64/valo/06,814.99,yes,locked 2006.201.04:27:39.64/valo/07,864.99,yes,locked 2006.201.04:27:39.64/valo/08,884.99,yes,locked 2006.201.04:27:40.73/vb/01,04,usb,yes,35,33 2006.201.04:27:40.73/vb/02,05,usb,yes,34,33 2006.201.04:27:40.73/vb/03,04,usb,yes,35,38 2006.201.04:27:40.73/vb/04,05,usb,yes,35,34 2006.201.04:27:40.73/vb/05,04,usb,yes,31,34 2006.201.04:27:40.73/vb/06,04,usb,yes,36,32 2006.201.04:27:40.73/vb/07,04,usb,yes,35,35 2006.201.04:27:40.73/vb/08,04,usb,yes,32,36 2006.201.04:27:40.97/vblo/01,629.99,yes,locked 2006.201.04:27:40.97/vblo/02,634.99,yes,locked 2006.201.04:27:40.97/vblo/03,649.99,yes,locked 2006.201.04:27:40.97/vblo/04,679.99,yes,locked 2006.201.04:27:40.97/vblo/05,709.99,yes,locked 2006.201.04:27:40.97/vblo/06,719.99,yes,locked 2006.201.04:27:40.97/vblo/07,734.99,yes,locked 2006.201.04:27:40.97/vblo/08,744.99,yes,locked 2006.201.04:27:41.12/vabw/8 2006.201.04:27:41.27/vbbw/8 2006.201.04:27:41.37/xfe/off,on,16.0 2006.201.04:27:41.75/ifatt/23,28,28,28 2006.201.04:27:42.04/fmout-gps/S +4.58E-07 2006.201.04:27:42.08:!2006.201.04:29:08 2006.201.04:29:08.00:data_valid=off 2006.201.04:29:08.00:"et 2006.201.04:29:08.00:!+3s 2006.201.04:29:11.01:"tape 2006.201.04:29:11.01:postob 2006.201.04:29:11.08/cable/+6.4661E-03 2006.201.04:29:11.08/wx/22.98,1004.1,90 2006.201.04:29:11.14/fmout-gps/S +4.58E-07 2006.201.04:29:11.14:scan_name=201-0433,jd0607,90 2006.201.04:29:11.14:source=1611+343,161341.06,341247.9,2000.0,cw 2006.201.04:29:12.13#flagr#flagr/antenna,new-source 2006.201.04:29:12.13:checkk5 2006.201.04:29:12.47/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:29:12.83/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:29:13.19/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:29:13.54/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:29:13.88/chk_obsdata//k5ts1/T2010427??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.04:29:14.23/chk_obsdata//k5ts2/T2010427??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.04:29:14.57/chk_obsdata//k5ts3/T2010427??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.04:29:14.92/chk_obsdata//k5ts4/T2010427??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.04:29:15.59/k5log//k5ts1_log_newline 2006.201.04:29:16.25/k5log//k5ts2_log_newline 2006.201.04:29:16.90/k5log//k5ts3_log_newline 2006.201.04:29:17.56/k5log//k5ts4_log_newline 2006.201.04:29:17.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:29:17.59:setupk4=1 2006.201.04:29:17.59$setupk4/echo=on 2006.201.04:29:17.59$setupk4/pcalon 2006.201.04:29:17.59$pcalon/"no phase cal control is implemented here 2006.201.04:29:17.59$setupk4/"tpicd=stop 2006.201.04:29:17.59$setupk4/"rec=synch_on 2006.201.04:29:17.59$setupk4/"rec_mode=128 2006.201.04:29:17.59$setupk4/!* 2006.201.04:29:17.59$setupk4/recpk4 2006.201.04:29:17.59$recpk4/recpatch= 2006.201.04:29:17.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:29:17.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:29:17.59$setupk4/vck44 2006.201.04:29:17.59$vck44/valo=1,524.99 2006.201.04:29:17.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.04:29:17.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.04:29:17.59#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:17.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:17.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:17.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:17.59#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:29:17.59#ibcon#first serial, iclass 35, count 0 2006.201.04:29:17.59#ibcon#enter sib2, iclass 35, count 0 2006.201.04:29:17.59#ibcon#flushed, iclass 35, count 0 2006.201.04:29:17.59#ibcon#about to write, iclass 35, count 0 2006.201.04:29:17.59#ibcon#wrote, iclass 35, count 0 2006.201.04:29:17.59#ibcon#about to read 3, iclass 35, count 0 2006.201.04:29:17.61#ibcon#read 3, iclass 35, count 0 2006.201.04:29:17.61#ibcon#about to read 4, iclass 35, count 0 2006.201.04:29:17.61#ibcon#read 4, iclass 35, count 0 2006.201.04:29:17.61#ibcon#about to read 5, iclass 35, count 0 2006.201.04:29:17.61#ibcon#read 5, iclass 35, count 0 2006.201.04:29:17.61#ibcon#about to read 6, iclass 35, count 0 2006.201.04:29:17.61#ibcon#read 6, iclass 35, count 0 2006.201.04:29:17.61#ibcon#end of sib2, iclass 35, count 0 2006.201.04:29:17.61#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:29:17.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:29:17.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:29:17.61#ibcon#*before write, iclass 35, count 0 2006.201.04:29:17.61#ibcon#enter sib2, iclass 35, count 0 2006.201.04:29:17.61#ibcon#flushed, iclass 35, count 0 2006.201.04:29:17.61#ibcon#about to write, iclass 35, count 0 2006.201.04:29:17.61#ibcon#wrote, iclass 35, count 0 2006.201.04:29:17.61#ibcon#about to read 3, iclass 35, count 0 2006.201.04:29:17.66#ibcon#read 3, iclass 35, count 0 2006.201.04:29:17.66#ibcon#about to read 4, iclass 35, count 0 2006.201.04:29:17.66#ibcon#read 4, iclass 35, count 0 2006.201.04:29:17.66#ibcon#about to read 5, iclass 35, count 0 2006.201.04:29:17.66#ibcon#read 5, iclass 35, count 0 2006.201.04:29:17.66#ibcon#about to read 6, iclass 35, count 0 2006.201.04:29:17.66#ibcon#read 6, iclass 35, count 0 2006.201.04:29:17.66#ibcon#end of sib2, iclass 35, count 0 2006.201.04:29:17.66#ibcon#*after write, iclass 35, count 0 2006.201.04:29:17.66#ibcon#*before return 0, iclass 35, count 0 2006.201.04:29:17.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:17.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:17.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:29:17.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:29:17.66$vck44/va=1,8 2006.201.04:29:17.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.04:29:17.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.04:29:17.66#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:17.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:17.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:17.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:17.66#ibcon#enter wrdev, iclass 37, count 2 2006.201.04:29:17.66#ibcon#first serial, iclass 37, count 2 2006.201.04:29:17.66#ibcon#enter sib2, iclass 37, count 2 2006.201.04:29:17.66#ibcon#flushed, iclass 37, count 2 2006.201.04:29:17.66#ibcon#about to write, iclass 37, count 2 2006.201.04:29:17.66#ibcon#wrote, iclass 37, count 2 2006.201.04:29:17.66#ibcon#about to read 3, iclass 37, count 2 2006.201.04:29:17.68#ibcon#read 3, iclass 37, count 2 2006.201.04:29:17.68#ibcon#about to read 4, iclass 37, count 2 2006.201.04:29:17.68#ibcon#read 4, iclass 37, count 2 2006.201.04:29:17.68#ibcon#about to read 5, iclass 37, count 2 2006.201.04:29:17.68#ibcon#read 5, iclass 37, count 2 2006.201.04:29:17.68#ibcon#about to read 6, iclass 37, count 2 2006.201.04:29:17.68#ibcon#read 6, iclass 37, count 2 2006.201.04:29:17.68#ibcon#end of sib2, iclass 37, count 2 2006.201.04:29:17.68#ibcon#*mode == 0, iclass 37, count 2 2006.201.04:29:17.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.04:29:17.68#ibcon#[25=AT01-08\r\n] 2006.201.04:29:17.68#ibcon#*before write, iclass 37, count 2 2006.201.04:29:17.68#ibcon#enter sib2, iclass 37, count 2 2006.201.04:29:17.68#ibcon#flushed, iclass 37, count 2 2006.201.04:29:17.68#ibcon#about to write, iclass 37, count 2 2006.201.04:29:17.68#ibcon#wrote, iclass 37, count 2 2006.201.04:29:17.68#ibcon#about to read 3, iclass 37, count 2 2006.201.04:29:17.71#ibcon#read 3, iclass 37, count 2 2006.201.04:29:17.71#ibcon#about to read 4, iclass 37, count 2 2006.201.04:29:17.71#ibcon#read 4, iclass 37, count 2 2006.201.04:29:17.71#ibcon#about to read 5, iclass 37, count 2 2006.201.04:29:17.71#ibcon#read 5, iclass 37, count 2 2006.201.04:29:17.71#ibcon#about to read 6, iclass 37, count 2 2006.201.04:29:17.71#ibcon#read 6, iclass 37, count 2 2006.201.04:29:17.71#ibcon#end of sib2, iclass 37, count 2 2006.201.04:29:17.71#ibcon#*after write, iclass 37, count 2 2006.201.04:29:17.71#ibcon#*before return 0, iclass 37, count 2 2006.201.04:29:17.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:17.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:17.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.04:29:17.71#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:17.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:17.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:17.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:17.83#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:29:17.83#ibcon#first serial, iclass 37, count 0 2006.201.04:29:17.83#ibcon#enter sib2, iclass 37, count 0 2006.201.04:29:17.83#ibcon#flushed, iclass 37, count 0 2006.201.04:29:17.83#ibcon#about to write, iclass 37, count 0 2006.201.04:29:17.83#ibcon#wrote, iclass 37, count 0 2006.201.04:29:17.83#ibcon#about to read 3, iclass 37, count 0 2006.201.04:29:17.85#ibcon#read 3, iclass 37, count 0 2006.201.04:29:17.85#ibcon#about to read 4, iclass 37, count 0 2006.201.04:29:17.85#ibcon#read 4, iclass 37, count 0 2006.201.04:29:17.85#ibcon#about to read 5, iclass 37, count 0 2006.201.04:29:17.85#ibcon#read 5, iclass 37, count 0 2006.201.04:29:17.85#ibcon#about to read 6, iclass 37, count 0 2006.201.04:29:17.85#ibcon#read 6, iclass 37, count 0 2006.201.04:29:17.85#ibcon#end of sib2, iclass 37, count 0 2006.201.04:29:17.85#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:29:17.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:29:17.85#ibcon#[25=USB\r\n] 2006.201.04:29:17.85#ibcon#*before write, iclass 37, count 0 2006.201.04:29:17.85#ibcon#enter sib2, iclass 37, count 0 2006.201.04:29:17.85#ibcon#flushed, iclass 37, count 0 2006.201.04:29:17.85#ibcon#about to write, iclass 37, count 0 2006.201.04:29:17.85#ibcon#wrote, iclass 37, count 0 2006.201.04:29:17.85#ibcon#about to read 3, iclass 37, count 0 2006.201.04:29:17.88#ibcon#read 3, iclass 37, count 0 2006.201.04:29:17.88#ibcon#about to read 4, iclass 37, count 0 2006.201.04:29:17.88#ibcon#read 4, iclass 37, count 0 2006.201.04:29:17.88#ibcon#about to read 5, iclass 37, count 0 2006.201.04:29:17.88#ibcon#read 5, iclass 37, count 0 2006.201.04:29:17.88#ibcon#about to read 6, iclass 37, count 0 2006.201.04:29:17.88#ibcon#read 6, iclass 37, count 0 2006.201.04:29:17.88#ibcon#end of sib2, iclass 37, count 0 2006.201.04:29:17.88#ibcon#*after write, iclass 37, count 0 2006.201.04:29:17.88#ibcon#*before return 0, iclass 37, count 0 2006.201.04:29:17.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:17.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:17.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:29:17.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:29:17.88$vck44/valo=2,534.99 2006.201.04:29:17.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.04:29:17.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.04:29:17.88#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:17.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:17.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:17.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:17.88#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:29:17.88#ibcon#first serial, iclass 39, count 0 2006.201.04:29:17.88#ibcon#enter sib2, iclass 39, count 0 2006.201.04:29:17.88#ibcon#flushed, iclass 39, count 0 2006.201.04:29:17.88#ibcon#about to write, iclass 39, count 0 2006.201.04:29:17.88#ibcon#wrote, iclass 39, count 0 2006.201.04:29:17.88#ibcon#about to read 3, iclass 39, count 0 2006.201.04:29:17.90#ibcon#read 3, iclass 39, count 0 2006.201.04:29:17.90#ibcon#about to read 4, iclass 39, count 0 2006.201.04:29:17.90#ibcon#read 4, iclass 39, count 0 2006.201.04:29:17.90#ibcon#about to read 5, iclass 39, count 0 2006.201.04:29:17.90#ibcon#read 5, iclass 39, count 0 2006.201.04:29:17.90#ibcon#about to read 6, iclass 39, count 0 2006.201.04:29:17.90#ibcon#read 6, iclass 39, count 0 2006.201.04:29:17.90#ibcon#end of sib2, iclass 39, count 0 2006.201.04:29:17.90#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:29:17.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:29:17.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:29:17.90#ibcon#*before write, iclass 39, count 0 2006.201.04:29:17.90#ibcon#enter sib2, iclass 39, count 0 2006.201.04:29:17.90#ibcon#flushed, iclass 39, count 0 2006.201.04:29:17.90#ibcon#about to write, iclass 39, count 0 2006.201.04:29:17.90#ibcon#wrote, iclass 39, count 0 2006.201.04:29:17.90#ibcon#about to read 3, iclass 39, count 0 2006.201.04:29:17.94#ibcon#read 3, iclass 39, count 0 2006.201.04:29:17.94#ibcon#about to read 4, iclass 39, count 0 2006.201.04:29:17.94#ibcon#read 4, iclass 39, count 0 2006.201.04:29:17.94#ibcon#about to read 5, iclass 39, count 0 2006.201.04:29:17.94#ibcon#read 5, iclass 39, count 0 2006.201.04:29:17.94#ibcon#about to read 6, iclass 39, count 0 2006.201.04:29:17.94#ibcon#read 6, iclass 39, count 0 2006.201.04:29:17.94#ibcon#end of sib2, iclass 39, count 0 2006.201.04:29:17.94#ibcon#*after write, iclass 39, count 0 2006.201.04:29:17.94#ibcon#*before return 0, iclass 39, count 0 2006.201.04:29:17.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:17.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:17.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:29:17.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:29:17.94$vck44/va=2,7 2006.201.04:29:17.94#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.04:29:17.94#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.04:29:17.94#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:17.94#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:18.00#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:18.00#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:18.00#ibcon#enter wrdev, iclass 2, count 2 2006.201.04:29:18.00#ibcon#first serial, iclass 2, count 2 2006.201.04:29:18.00#ibcon#enter sib2, iclass 2, count 2 2006.201.04:29:18.00#ibcon#flushed, iclass 2, count 2 2006.201.04:29:18.00#ibcon#about to write, iclass 2, count 2 2006.201.04:29:18.00#ibcon#wrote, iclass 2, count 2 2006.201.04:29:18.00#ibcon#about to read 3, iclass 2, count 2 2006.201.04:29:18.02#ibcon#read 3, iclass 2, count 2 2006.201.04:29:18.02#ibcon#about to read 4, iclass 2, count 2 2006.201.04:29:18.02#ibcon#read 4, iclass 2, count 2 2006.201.04:29:18.02#ibcon#about to read 5, iclass 2, count 2 2006.201.04:29:18.02#ibcon#read 5, iclass 2, count 2 2006.201.04:29:18.02#ibcon#about to read 6, iclass 2, count 2 2006.201.04:29:18.02#ibcon#read 6, iclass 2, count 2 2006.201.04:29:18.02#ibcon#end of sib2, iclass 2, count 2 2006.201.04:29:18.02#ibcon#*mode == 0, iclass 2, count 2 2006.201.04:29:18.02#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.04:29:18.02#ibcon#[25=AT02-07\r\n] 2006.201.04:29:18.02#ibcon#*before write, iclass 2, count 2 2006.201.04:29:18.02#ibcon#enter sib2, iclass 2, count 2 2006.201.04:29:18.02#ibcon#flushed, iclass 2, count 2 2006.201.04:29:18.02#ibcon#about to write, iclass 2, count 2 2006.201.04:29:18.02#ibcon#wrote, iclass 2, count 2 2006.201.04:29:18.02#ibcon#about to read 3, iclass 2, count 2 2006.201.04:29:18.05#ibcon#read 3, iclass 2, count 2 2006.201.04:29:18.05#ibcon#about to read 4, iclass 2, count 2 2006.201.04:29:18.05#ibcon#read 4, iclass 2, count 2 2006.201.04:29:18.05#ibcon#about to read 5, iclass 2, count 2 2006.201.04:29:18.05#ibcon#read 5, iclass 2, count 2 2006.201.04:29:18.05#ibcon#about to read 6, iclass 2, count 2 2006.201.04:29:18.05#ibcon#read 6, iclass 2, count 2 2006.201.04:29:18.05#ibcon#end of sib2, iclass 2, count 2 2006.201.04:29:18.05#ibcon#*after write, iclass 2, count 2 2006.201.04:29:18.05#ibcon#*before return 0, iclass 2, count 2 2006.201.04:29:18.05#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:18.05#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:18.05#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.04:29:18.05#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:18.05#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:18.17#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:18.17#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:18.17#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:29:18.17#ibcon#first serial, iclass 2, count 0 2006.201.04:29:18.17#ibcon#enter sib2, iclass 2, count 0 2006.201.04:29:18.17#ibcon#flushed, iclass 2, count 0 2006.201.04:29:18.17#ibcon#about to write, iclass 2, count 0 2006.201.04:29:18.17#ibcon#wrote, iclass 2, count 0 2006.201.04:29:18.17#ibcon#about to read 3, iclass 2, count 0 2006.201.04:29:18.19#ibcon#read 3, iclass 2, count 0 2006.201.04:29:18.19#ibcon#about to read 4, iclass 2, count 0 2006.201.04:29:18.19#ibcon#read 4, iclass 2, count 0 2006.201.04:29:18.19#ibcon#about to read 5, iclass 2, count 0 2006.201.04:29:18.19#ibcon#read 5, iclass 2, count 0 2006.201.04:29:18.19#ibcon#about to read 6, iclass 2, count 0 2006.201.04:29:18.19#ibcon#read 6, iclass 2, count 0 2006.201.04:29:18.19#ibcon#end of sib2, iclass 2, count 0 2006.201.04:29:18.19#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:29:18.19#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:29:18.19#ibcon#[25=USB\r\n] 2006.201.04:29:18.19#ibcon#*before write, iclass 2, count 0 2006.201.04:29:18.19#ibcon#enter sib2, iclass 2, count 0 2006.201.04:29:18.19#ibcon#flushed, iclass 2, count 0 2006.201.04:29:18.19#ibcon#about to write, iclass 2, count 0 2006.201.04:29:18.19#ibcon#wrote, iclass 2, count 0 2006.201.04:29:18.19#ibcon#about to read 3, iclass 2, count 0 2006.201.04:29:18.22#ibcon#read 3, iclass 2, count 0 2006.201.04:29:18.22#ibcon#about to read 4, iclass 2, count 0 2006.201.04:29:18.22#ibcon#read 4, iclass 2, count 0 2006.201.04:29:18.22#ibcon#about to read 5, iclass 2, count 0 2006.201.04:29:18.22#ibcon#read 5, iclass 2, count 0 2006.201.04:29:18.22#ibcon#about to read 6, iclass 2, count 0 2006.201.04:29:18.22#ibcon#read 6, iclass 2, count 0 2006.201.04:29:18.22#ibcon#end of sib2, iclass 2, count 0 2006.201.04:29:18.22#ibcon#*after write, iclass 2, count 0 2006.201.04:29:18.22#ibcon#*before return 0, iclass 2, count 0 2006.201.04:29:18.22#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:18.22#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:18.22#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:29:18.22#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:29:18.22$vck44/valo=3,564.99 2006.201.04:29:18.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.04:29:18.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.04:29:18.22#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:18.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:18.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:18.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:18.22#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:29:18.22#ibcon#first serial, iclass 5, count 0 2006.201.04:29:18.22#ibcon#enter sib2, iclass 5, count 0 2006.201.04:29:18.22#ibcon#flushed, iclass 5, count 0 2006.201.04:29:18.22#ibcon#about to write, iclass 5, count 0 2006.201.04:29:18.22#ibcon#wrote, iclass 5, count 0 2006.201.04:29:18.22#ibcon#about to read 3, iclass 5, count 0 2006.201.04:29:18.24#ibcon#read 3, iclass 5, count 0 2006.201.04:29:18.24#ibcon#about to read 4, iclass 5, count 0 2006.201.04:29:18.24#ibcon#read 4, iclass 5, count 0 2006.201.04:29:18.24#ibcon#about to read 5, iclass 5, count 0 2006.201.04:29:18.24#ibcon#read 5, iclass 5, count 0 2006.201.04:29:18.24#ibcon#about to read 6, iclass 5, count 0 2006.201.04:29:18.24#ibcon#read 6, iclass 5, count 0 2006.201.04:29:18.24#ibcon#end of sib2, iclass 5, count 0 2006.201.04:29:18.24#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:29:18.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:29:18.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:29:18.24#ibcon#*before write, iclass 5, count 0 2006.201.04:29:18.24#ibcon#enter sib2, iclass 5, count 0 2006.201.04:29:18.24#ibcon#flushed, iclass 5, count 0 2006.201.04:29:18.24#ibcon#about to write, iclass 5, count 0 2006.201.04:29:18.24#ibcon#wrote, iclass 5, count 0 2006.201.04:29:18.24#ibcon#about to read 3, iclass 5, count 0 2006.201.04:29:18.28#ibcon#read 3, iclass 5, count 0 2006.201.04:29:18.28#ibcon#about to read 4, iclass 5, count 0 2006.201.04:29:18.28#ibcon#read 4, iclass 5, count 0 2006.201.04:29:18.28#ibcon#about to read 5, iclass 5, count 0 2006.201.04:29:18.28#ibcon#read 5, iclass 5, count 0 2006.201.04:29:18.28#ibcon#about to read 6, iclass 5, count 0 2006.201.04:29:18.28#ibcon#read 6, iclass 5, count 0 2006.201.04:29:18.28#ibcon#end of sib2, iclass 5, count 0 2006.201.04:29:18.28#ibcon#*after write, iclass 5, count 0 2006.201.04:29:18.28#ibcon#*before return 0, iclass 5, count 0 2006.201.04:29:18.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:18.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:18.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:29:18.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:29:18.28$vck44/va=3,8 2006.201.04:29:18.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.04:29:18.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.04:29:18.28#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:18.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:18.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:18.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:18.34#ibcon#enter wrdev, iclass 7, count 2 2006.201.04:29:18.34#ibcon#first serial, iclass 7, count 2 2006.201.04:29:18.34#ibcon#enter sib2, iclass 7, count 2 2006.201.04:29:18.34#ibcon#flushed, iclass 7, count 2 2006.201.04:29:18.34#ibcon#about to write, iclass 7, count 2 2006.201.04:29:18.34#ibcon#wrote, iclass 7, count 2 2006.201.04:29:18.34#ibcon#about to read 3, iclass 7, count 2 2006.201.04:29:18.36#ibcon#read 3, iclass 7, count 2 2006.201.04:29:18.36#ibcon#about to read 4, iclass 7, count 2 2006.201.04:29:18.36#ibcon#read 4, iclass 7, count 2 2006.201.04:29:18.36#ibcon#about to read 5, iclass 7, count 2 2006.201.04:29:18.36#ibcon#read 5, iclass 7, count 2 2006.201.04:29:18.36#ibcon#about to read 6, iclass 7, count 2 2006.201.04:29:18.36#ibcon#read 6, iclass 7, count 2 2006.201.04:29:18.36#ibcon#end of sib2, iclass 7, count 2 2006.201.04:29:18.36#ibcon#*mode == 0, iclass 7, count 2 2006.201.04:29:18.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.04:29:18.36#ibcon#[25=AT03-08\r\n] 2006.201.04:29:18.36#ibcon#*before write, iclass 7, count 2 2006.201.04:29:18.36#ibcon#enter sib2, iclass 7, count 2 2006.201.04:29:18.36#ibcon#flushed, iclass 7, count 2 2006.201.04:29:18.36#ibcon#about to write, iclass 7, count 2 2006.201.04:29:18.36#ibcon#wrote, iclass 7, count 2 2006.201.04:29:18.36#ibcon#about to read 3, iclass 7, count 2 2006.201.04:29:18.39#ibcon#read 3, iclass 7, count 2 2006.201.04:29:18.39#ibcon#about to read 4, iclass 7, count 2 2006.201.04:29:18.39#ibcon#read 4, iclass 7, count 2 2006.201.04:29:18.39#ibcon#about to read 5, iclass 7, count 2 2006.201.04:29:18.39#ibcon#read 5, iclass 7, count 2 2006.201.04:29:18.39#ibcon#about to read 6, iclass 7, count 2 2006.201.04:29:18.39#ibcon#read 6, iclass 7, count 2 2006.201.04:29:18.39#ibcon#end of sib2, iclass 7, count 2 2006.201.04:29:18.39#ibcon#*after write, iclass 7, count 2 2006.201.04:29:18.39#ibcon#*before return 0, iclass 7, count 2 2006.201.04:29:18.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:18.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:18.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.04:29:18.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:18.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:18.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:18.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:18.51#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:29:18.51#ibcon#first serial, iclass 7, count 0 2006.201.04:29:18.51#ibcon#enter sib2, iclass 7, count 0 2006.201.04:29:18.51#ibcon#flushed, iclass 7, count 0 2006.201.04:29:18.51#ibcon#about to write, iclass 7, count 0 2006.201.04:29:18.51#ibcon#wrote, iclass 7, count 0 2006.201.04:29:18.51#ibcon#about to read 3, iclass 7, count 0 2006.201.04:29:18.53#ibcon#read 3, iclass 7, count 0 2006.201.04:29:18.53#ibcon#about to read 4, iclass 7, count 0 2006.201.04:29:18.53#ibcon#read 4, iclass 7, count 0 2006.201.04:29:18.53#ibcon#about to read 5, iclass 7, count 0 2006.201.04:29:18.53#ibcon#read 5, iclass 7, count 0 2006.201.04:29:18.53#ibcon#about to read 6, iclass 7, count 0 2006.201.04:29:18.53#ibcon#read 6, iclass 7, count 0 2006.201.04:29:18.53#ibcon#end of sib2, iclass 7, count 0 2006.201.04:29:18.53#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:29:18.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:29:18.53#ibcon#[25=USB\r\n] 2006.201.04:29:18.53#ibcon#*before write, iclass 7, count 0 2006.201.04:29:18.53#ibcon#enter sib2, iclass 7, count 0 2006.201.04:29:18.53#ibcon#flushed, iclass 7, count 0 2006.201.04:29:18.53#ibcon#about to write, iclass 7, count 0 2006.201.04:29:18.53#ibcon#wrote, iclass 7, count 0 2006.201.04:29:18.53#ibcon#about to read 3, iclass 7, count 0 2006.201.04:29:18.56#ibcon#read 3, iclass 7, count 0 2006.201.04:29:18.56#ibcon#about to read 4, iclass 7, count 0 2006.201.04:29:18.56#ibcon#read 4, iclass 7, count 0 2006.201.04:29:18.56#ibcon#about to read 5, iclass 7, count 0 2006.201.04:29:18.56#ibcon#read 5, iclass 7, count 0 2006.201.04:29:18.56#ibcon#about to read 6, iclass 7, count 0 2006.201.04:29:18.56#ibcon#read 6, iclass 7, count 0 2006.201.04:29:18.56#ibcon#end of sib2, iclass 7, count 0 2006.201.04:29:18.56#ibcon#*after write, iclass 7, count 0 2006.201.04:29:18.56#ibcon#*before return 0, iclass 7, count 0 2006.201.04:29:18.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:18.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:18.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:29:18.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:29:18.56$vck44/valo=4,624.99 2006.201.04:29:18.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.04:29:18.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.04:29:18.56#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:18.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:18.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:18.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:18.56#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:29:18.56#ibcon#first serial, iclass 11, count 0 2006.201.04:29:18.56#ibcon#enter sib2, iclass 11, count 0 2006.201.04:29:18.56#ibcon#flushed, iclass 11, count 0 2006.201.04:29:18.56#ibcon#about to write, iclass 11, count 0 2006.201.04:29:18.56#ibcon#wrote, iclass 11, count 0 2006.201.04:29:18.56#ibcon#about to read 3, iclass 11, count 0 2006.201.04:29:18.58#ibcon#read 3, iclass 11, count 0 2006.201.04:29:18.58#ibcon#about to read 4, iclass 11, count 0 2006.201.04:29:18.58#ibcon#read 4, iclass 11, count 0 2006.201.04:29:18.58#ibcon#about to read 5, iclass 11, count 0 2006.201.04:29:18.58#ibcon#read 5, iclass 11, count 0 2006.201.04:29:18.58#ibcon#about to read 6, iclass 11, count 0 2006.201.04:29:18.58#ibcon#read 6, iclass 11, count 0 2006.201.04:29:18.58#ibcon#end of sib2, iclass 11, count 0 2006.201.04:29:18.58#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:29:18.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:29:18.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:29:18.58#ibcon#*before write, iclass 11, count 0 2006.201.04:29:18.58#ibcon#enter sib2, iclass 11, count 0 2006.201.04:29:18.58#ibcon#flushed, iclass 11, count 0 2006.201.04:29:18.58#ibcon#about to write, iclass 11, count 0 2006.201.04:29:18.58#ibcon#wrote, iclass 11, count 0 2006.201.04:29:18.58#ibcon#about to read 3, iclass 11, count 0 2006.201.04:29:18.62#ibcon#read 3, iclass 11, count 0 2006.201.04:29:18.62#ibcon#about to read 4, iclass 11, count 0 2006.201.04:29:18.62#ibcon#read 4, iclass 11, count 0 2006.201.04:29:18.62#ibcon#about to read 5, iclass 11, count 0 2006.201.04:29:18.62#ibcon#read 5, iclass 11, count 0 2006.201.04:29:18.62#ibcon#about to read 6, iclass 11, count 0 2006.201.04:29:18.62#ibcon#read 6, iclass 11, count 0 2006.201.04:29:18.62#ibcon#end of sib2, iclass 11, count 0 2006.201.04:29:18.62#ibcon#*after write, iclass 11, count 0 2006.201.04:29:18.62#ibcon#*before return 0, iclass 11, count 0 2006.201.04:29:18.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:18.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:18.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:29:18.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:29:18.62$vck44/va=4,7 2006.201.04:29:18.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.04:29:18.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.04:29:18.62#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:18.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:18.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:18.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:18.68#ibcon#enter wrdev, iclass 13, count 2 2006.201.04:29:18.68#ibcon#first serial, iclass 13, count 2 2006.201.04:29:18.68#ibcon#enter sib2, iclass 13, count 2 2006.201.04:29:18.68#ibcon#flushed, iclass 13, count 2 2006.201.04:29:18.68#ibcon#about to write, iclass 13, count 2 2006.201.04:29:18.68#ibcon#wrote, iclass 13, count 2 2006.201.04:29:18.68#ibcon#about to read 3, iclass 13, count 2 2006.201.04:29:18.70#ibcon#read 3, iclass 13, count 2 2006.201.04:29:18.70#ibcon#about to read 4, iclass 13, count 2 2006.201.04:29:18.70#ibcon#read 4, iclass 13, count 2 2006.201.04:29:18.70#ibcon#about to read 5, iclass 13, count 2 2006.201.04:29:18.70#ibcon#read 5, iclass 13, count 2 2006.201.04:29:18.70#ibcon#about to read 6, iclass 13, count 2 2006.201.04:29:18.70#ibcon#read 6, iclass 13, count 2 2006.201.04:29:18.70#ibcon#end of sib2, iclass 13, count 2 2006.201.04:29:18.70#ibcon#*mode == 0, iclass 13, count 2 2006.201.04:29:18.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.04:29:18.70#ibcon#[25=AT04-07\r\n] 2006.201.04:29:18.70#ibcon#*before write, iclass 13, count 2 2006.201.04:29:18.70#ibcon#enter sib2, iclass 13, count 2 2006.201.04:29:18.70#ibcon#flushed, iclass 13, count 2 2006.201.04:29:18.70#ibcon#about to write, iclass 13, count 2 2006.201.04:29:18.70#ibcon#wrote, iclass 13, count 2 2006.201.04:29:18.70#ibcon#about to read 3, iclass 13, count 2 2006.201.04:29:18.73#ibcon#read 3, iclass 13, count 2 2006.201.04:29:18.73#ibcon#about to read 4, iclass 13, count 2 2006.201.04:29:18.73#ibcon#read 4, iclass 13, count 2 2006.201.04:29:18.73#ibcon#about to read 5, iclass 13, count 2 2006.201.04:29:18.73#ibcon#read 5, iclass 13, count 2 2006.201.04:29:18.73#ibcon#about to read 6, iclass 13, count 2 2006.201.04:29:18.73#ibcon#read 6, iclass 13, count 2 2006.201.04:29:18.73#ibcon#end of sib2, iclass 13, count 2 2006.201.04:29:18.73#ibcon#*after write, iclass 13, count 2 2006.201.04:29:18.73#ibcon#*before return 0, iclass 13, count 2 2006.201.04:29:18.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:18.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:18.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.04:29:18.73#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:18.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:18.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:18.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:18.85#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:29:18.85#ibcon#first serial, iclass 13, count 0 2006.201.04:29:18.85#ibcon#enter sib2, iclass 13, count 0 2006.201.04:29:18.85#ibcon#flushed, iclass 13, count 0 2006.201.04:29:18.85#ibcon#about to write, iclass 13, count 0 2006.201.04:29:18.85#ibcon#wrote, iclass 13, count 0 2006.201.04:29:18.85#ibcon#about to read 3, iclass 13, count 0 2006.201.04:29:18.87#ibcon#read 3, iclass 13, count 0 2006.201.04:29:18.87#ibcon#about to read 4, iclass 13, count 0 2006.201.04:29:18.87#ibcon#read 4, iclass 13, count 0 2006.201.04:29:18.87#ibcon#about to read 5, iclass 13, count 0 2006.201.04:29:18.87#ibcon#read 5, iclass 13, count 0 2006.201.04:29:18.87#ibcon#about to read 6, iclass 13, count 0 2006.201.04:29:18.87#ibcon#read 6, iclass 13, count 0 2006.201.04:29:18.87#ibcon#end of sib2, iclass 13, count 0 2006.201.04:29:18.87#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:29:18.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:29:18.87#ibcon#[25=USB\r\n] 2006.201.04:29:18.87#ibcon#*before write, iclass 13, count 0 2006.201.04:29:18.87#ibcon#enter sib2, iclass 13, count 0 2006.201.04:29:18.87#ibcon#flushed, iclass 13, count 0 2006.201.04:29:18.87#ibcon#about to write, iclass 13, count 0 2006.201.04:29:18.87#ibcon#wrote, iclass 13, count 0 2006.201.04:29:18.87#ibcon#about to read 3, iclass 13, count 0 2006.201.04:29:18.90#ibcon#read 3, iclass 13, count 0 2006.201.04:29:18.90#ibcon#about to read 4, iclass 13, count 0 2006.201.04:29:18.90#ibcon#read 4, iclass 13, count 0 2006.201.04:29:18.90#ibcon#about to read 5, iclass 13, count 0 2006.201.04:29:18.90#ibcon#read 5, iclass 13, count 0 2006.201.04:29:18.90#ibcon#about to read 6, iclass 13, count 0 2006.201.04:29:18.90#ibcon#read 6, iclass 13, count 0 2006.201.04:29:18.90#ibcon#end of sib2, iclass 13, count 0 2006.201.04:29:18.90#ibcon#*after write, iclass 13, count 0 2006.201.04:29:18.90#ibcon#*before return 0, iclass 13, count 0 2006.201.04:29:18.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:18.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:18.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:29:18.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:29:18.90$vck44/valo=5,734.99 2006.201.04:29:18.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.04:29:18.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.04:29:18.90#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:18.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:18.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:18.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:18.90#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:29:18.90#ibcon#first serial, iclass 15, count 0 2006.201.04:29:18.90#ibcon#enter sib2, iclass 15, count 0 2006.201.04:29:18.90#ibcon#flushed, iclass 15, count 0 2006.201.04:29:18.90#ibcon#about to write, iclass 15, count 0 2006.201.04:29:18.90#ibcon#wrote, iclass 15, count 0 2006.201.04:29:18.90#ibcon#about to read 3, iclass 15, count 0 2006.201.04:29:18.92#ibcon#read 3, iclass 15, count 0 2006.201.04:29:18.92#ibcon#about to read 4, iclass 15, count 0 2006.201.04:29:18.92#ibcon#read 4, iclass 15, count 0 2006.201.04:29:18.92#ibcon#about to read 5, iclass 15, count 0 2006.201.04:29:18.92#ibcon#read 5, iclass 15, count 0 2006.201.04:29:18.92#ibcon#about to read 6, iclass 15, count 0 2006.201.04:29:18.92#ibcon#read 6, iclass 15, count 0 2006.201.04:29:18.92#ibcon#end of sib2, iclass 15, count 0 2006.201.04:29:18.92#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:29:18.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:29:18.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:29:18.92#ibcon#*before write, iclass 15, count 0 2006.201.04:29:18.92#ibcon#enter sib2, iclass 15, count 0 2006.201.04:29:18.92#ibcon#flushed, iclass 15, count 0 2006.201.04:29:18.92#ibcon#about to write, iclass 15, count 0 2006.201.04:29:18.92#ibcon#wrote, iclass 15, count 0 2006.201.04:29:18.92#ibcon#about to read 3, iclass 15, count 0 2006.201.04:29:18.96#ibcon#read 3, iclass 15, count 0 2006.201.04:29:18.96#ibcon#about to read 4, iclass 15, count 0 2006.201.04:29:18.96#ibcon#read 4, iclass 15, count 0 2006.201.04:29:18.96#ibcon#about to read 5, iclass 15, count 0 2006.201.04:29:18.96#ibcon#read 5, iclass 15, count 0 2006.201.04:29:18.96#ibcon#about to read 6, iclass 15, count 0 2006.201.04:29:18.96#ibcon#read 6, iclass 15, count 0 2006.201.04:29:18.96#ibcon#end of sib2, iclass 15, count 0 2006.201.04:29:18.96#ibcon#*after write, iclass 15, count 0 2006.201.04:29:18.96#ibcon#*before return 0, iclass 15, count 0 2006.201.04:29:18.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:18.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:18.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:29:18.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:29:18.96$vck44/va=5,4 2006.201.04:29:18.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.04:29:18.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.04:29:18.96#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:18.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:19.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:19.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:19.02#ibcon#enter wrdev, iclass 17, count 2 2006.201.04:29:19.02#ibcon#first serial, iclass 17, count 2 2006.201.04:29:19.02#ibcon#enter sib2, iclass 17, count 2 2006.201.04:29:19.02#ibcon#flushed, iclass 17, count 2 2006.201.04:29:19.02#ibcon#about to write, iclass 17, count 2 2006.201.04:29:19.02#ibcon#wrote, iclass 17, count 2 2006.201.04:29:19.02#ibcon#about to read 3, iclass 17, count 2 2006.201.04:29:19.04#ibcon#read 3, iclass 17, count 2 2006.201.04:29:19.04#ibcon#about to read 4, iclass 17, count 2 2006.201.04:29:19.04#ibcon#read 4, iclass 17, count 2 2006.201.04:29:19.04#ibcon#about to read 5, iclass 17, count 2 2006.201.04:29:19.04#ibcon#read 5, iclass 17, count 2 2006.201.04:29:19.04#ibcon#about to read 6, iclass 17, count 2 2006.201.04:29:19.04#ibcon#read 6, iclass 17, count 2 2006.201.04:29:19.04#ibcon#end of sib2, iclass 17, count 2 2006.201.04:29:19.04#ibcon#*mode == 0, iclass 17, count 2 2006.201.04:29:19.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.04:29:19.04#ibcon#[25=AT05-04\r\n] 2006.201.04:29:19.04#ibcon#*before write, iclass 17, count 2 2006.201.04:29:19.04#ibcon#enter sib2, iclass 17, count 2 2006.201.04:29:19.04#ibcon#flushed, iclass 17, count 2 2006.201.04:29:19.04#ibcon#about to write, iclass 17, count 2 2006.201.04:29:19.04#ibcon#wrote, iclass 17, count 2 2006.201.04:29:19.04#ibcon#about to read 3, iclass 17, count 2 2006.201.04:29:19.07#ibcon#read 3, iclass 17, count 2 2006.201.04:29:19.07#ibcon#about to read 4, iclass 17, count 2 2006.201.04:29:19.07#ibcon#read 4, iclass 17, count 2 2006.201.04:29:19.07#ibcon#about to read 5, iclass 17, count 2 2006.201.04:29:19.07#ibcon#read 5, iclass 17, count 2 2006.201.04:29:19.07#ibcon#about to read 6, iclass 17, count 2 2006.201.04:29:19.07#ibcon#read 6, iclass 17, count 2 2006.201.04:29:19.07#ibcon#end of sib2, iclass 17, count 2 2006.201.04:29:19.07#ibcon#*after write, iclass 17, count 2 2006.201.04:29:19.07#ibcon#*before return 0, iclass 17, count 2 2006.201.04:29:19.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:19.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:19.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.04:29:19.07#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:19.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:19.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:19.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:19.19#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:29:19.19#ibcon#first serial, iclass 17, count 0 2006.201.04:29:19.19#ibcon#enter sib2, iclass 17, count 0 2006.201.04:29:19.19#ibcon#flushed, iclass 17, count 0 2006.201.04:29:19.19#ibcon#about to write, iclass 17, count 0 2006.201.04:29:19.19#ibcon#wrote, iclass 17, count 0 2006.201.04:29:19.19#ibcon#about to read 3, iclass 17, count 0 2006.201.04:29:19.21#ibcon#read 3, iclass 17, count 0 2006.201.04:29:19.21#ibcon#about to read 4, iclass 17, count 0 2006.201.04:29:19.21#ibcon#read 4, iclass 17, count 0 2006.201.04:29:19.21#ibcon#about to read 5, iclass 17, count 0 2006.201.04:29:19.21#ibcon#read 5, iclass 17, count 0 2006.201.04:29:19.21#ibcon#about to read 6, iclass 17, count 0 2006.201.04:29:19.21#ibcon#read 6, iclass 17, count 0 2006.201.04:29:19.21#ibcon#end of sib2, iclass 17, count 0 2006.201.04:29:19.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:29:19.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:29:19.21#ibcon#[25=USB\r\n] 2006.201.04:29:19.21#ibcon#*before write, iclass 17, count 0 2006.201.04:29:19.21#ibcon#enter sib2, iclass 17, count 0 2006.201.04:29:19.21#ibcon#flushed, iclass 17, count 0 2006.201.04:29:19.21#ibcon#about to write, iclass 17, count 0 2006.201.04:29:19.21#ibcon#wrote, iclass 17, count 0 2006.201.04:29:19.21#ibcon#about to read 3, iclass 17, count 0 2006.201.04:29:19.24#ibcon#read 3, iclass 17, count 0 2006.201.04:29:19.24#ibcon#about to read 4, iclass 17, count 0 2006.201.04:29:19.24#ibcon#read 4, iclass 17, count 0 2006.201.04:29:19.24#ibcon#about to read 5, iclass 17, count 0 2006.201.04:29:19.24#ibcon#read 5, iclass 17, count 0 2006.201.04:29:19.24#ibcon#about to read 6, iclass 17, count 0 2006.201.04:29:19.24#ibcon#read 6, iclass 17, count 0 2006.201.04:29:19.24#ibcon#end of sib2, iclass 17, count 0 2006.201.04:29:19.24#ibcon#*after write, iclass 17, count 0 2006.201.04:29:19.24#ibcon#*before return 0, iclass 17, count 0 2006.201.04:29:19.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:19.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:19.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:29:19.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:29:19.24$vck44/valo=6,814.99 2006.201.04:29:19.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.04:29:19.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.04:29:19.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:19.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:19.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:19.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:19.24#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:29:19.24#ibcon#first serial, iclass 19, count 0 2006.201.04:29:19.24#ibcon#enter sib2, iclass 19, count 0 2006.201.04:29:19.24#ibcon#flushed, iclass 19, count 0 2006.201.04:29:19.24#ibcon#about to write, iclass 19, count 0 2006.201.04:29:19.24#ibcon#wrote, iclass 19, count 0 2006.201.04:29:19.24#ibcon#about to read 3, iclass 19, count 0 2006.201.04:29:19.26#ibcon#read 3, iclass 19, count 0 2006.201.04:29:19.26#ibcon#about to read 4, iclass 19, count 0 2006.201.04:29:19.26#ibcon#read 4, iclass 19, count 0 2006.201.04:29:19.26#ibcon#about to read 5, iclass 19, count 0 2006.201.04:29:19.26#ibcon#read 5, iclass 19, count 0 2006.201.04:29:19.26#ibcon#about to read 6, iclass 19, count 0 2006.201.04:29:19.26#ibcon#read 6, iclass 19, count 0 2006.201.04:29:19.26#ibcon#end of sib2, iclass 19, count 0 2006.201.04:29:19.26#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:29:19.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:29:19.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:29:19.26#ibcon#*before write, iclass 19, count 0 2006.201.04:29:19.26#ibcon#enter sib2, iclass 19, count 0 2006.201.04:29:19.26#ibcon#flushed, iclass 19, count 0 2006.201.04:29:19.26#ibcon#about to write, iclass 19, count 0 2006.201.04:29:19.26#ibcon#wrote, iclass 19, count 0 2006.201.04:29:19.26#ibcon#about to read 3, iclass 19, count 0 2006.201.04:29:19.30#ibcon#read 3, iclass 19, count 0 2006.201.04:29:19.30#ibcon#about to read 4, iclass 19, count 0 2006.201.04:29:19.30#ibcon#read 4, iclass 19, count 0 2006.201.04:29:19.30#ibcon#about to read 5, iclass 19, count 0 2006.201.04:29:19.30#ibcon#read 5, iclass 19, count 0 2006.201.04:29:19.30#ibcon#about to read 6, iclass 19, count 0 2006.201.04:29:19.30#ibcon#read 6, iclass 19, count 0 2006.201.04:29:19.30#ibcon#end of sib2, iclass 19, count 0 2006.201.04:29:19.30#ibcon#*after write, iclass 19, count 0 2006.201.04:29:19.30#ibcon#*before return 0, iclass 19, count 0 2006.201.04:29:19.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:19.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:19.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:29:19.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:29:19.30$vck44/va=6,5 2006.201.04:29:19.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.04:29:19.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.04:29:19.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:19.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:19.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:19.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:19.36#ibcon#enter wrdev, iclass 21, count 2 2006.201.04:29:19.36#ibcon#first serial, iclass 21, count 2 2006.201.04:29:19.36#ibcon#enter sib2, iclass 21, count 2 2006.201.04:29:19.36#ibcon#flushed, iclass 21, count 2 2006.201.04:29:19.36#ibcon#about to write, iclass 21, count 2 2006.201.04:29:19.36#ibcon#wrote, iclass 21, count 2 2006.201.04:29:19.36#ibcon#about to read 3, iclass 21, count 2 2006.201.04:29:19.38#ibcon#read 3, iclass 21, count 2 2006.201.04:29:19.38#ibcon#about to read 4, iclass 21, count 2 2006.201.04:29:19.38#ibcon#read 4, iclass 21, count 2 2006.201.04:29:19.38#ibcon#about to read 5, iclass 21, count 2 2006.201.04:29:19.38#ibcon#read 5, iclass 21, count 2 2006.201.04:29:19.38#ibcon#about to read 6, iclass 21, count 2 2006.201.04:29:19.38#ibcon#read 6, iclass 21, count 2 2006.201.04:29:19.38#ibcon#end of sib2, iclass 21, count 2 2006.201.04:29:19.38#ibcon#*mode == 0, iclass 21, count 2 2006.201.04:29:19.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.04:29:19.38#ibcon#[25=AT06-05\r\n] 2006.201.04:29:19.38#ibcon#*before write, iclass 21, count 2 2006.201.04:29:19.38#ibcon#enter sib2, iclass 21, count 2 2006.201.04:29:19.38#ibcon#flushed, iclass 21, count 2 2006.201.04:29:19.38#ibcon#about to write, iclass 21, count 2 2006.201.04:29:19.38#ibcon#wrote, iclass 21, count 2 2006.201.04:29:19.38#ibcon#about to read 3, iclass 21, count 2 2006.201.04:29:19.41#ibcon#read 3, iclass 21, count 2 2006.201.04:29:19.41#ibcon#about to read 4, iclass 21, count 2 2006.201.04:29:19.41#ibcon#read 4, iclass 21, count 2 2006.201.04:29:19.41#ibcon#about to read 5, iclass 21, count 2 2006.201.04:29:19.41#ibcon#read 5, iclass 21, count 2 2006.201.04:29:19.41#ibcon#about to read 6, iclass 21, count 2 2006.201.04:29:19.41#ibcon#read 6, iclass 21, count 2 2006.201.04:29:19.41#ibcon#end of sib2, iclass 21, count 2 2006.201.04:29:19.41#ibcon#*after write, iclass 21, count 2 2006.201.04:29:19.41#ibcon#*before return 0, iclass 21, count 2 2006.201.04:29:19.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:19.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:19.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.04:29:19.41#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:19.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:19.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:19.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:19.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:29:19.53#ibcon#first serial, iclass 21, count 0 2006.201.04:29:19.53#ibcon#enter sib2, iclass 21, count 0 2006.201.04:29:19.53#ibcon#flushed, iclass 21, count 0 2006.201.04:29:19.53#ibcon#about to write, iclass 21, count 0 2006.201.04:29:19.53#ibcon#wrote, iclass 21, count 0 2006.201.04:29:19.53#ibcon#about to read 3, iclass 21, count 0 2006.201.04:29:19.55#ibcon#read 3, iclass 21, count 0 2006.201.04:29:19.55#ibcon#about to read 4, iclass 21, count 0 2006.201.04:29:19.55#ibcon#read 4, iclass 21, count 0 2006.201.04:29:19.55#ibcon#about to read 5, iclass 21, count 0 2006.201.04:29:19.55#ibcon#read 5, iclass 21, count 0 2006.201.04:29:19.55#ibcon#about to read 6, iclass 21, count 0 2006.201.04:29:19.55#ibcon#read 6, iclass 21, count 0 2006.201.04:29:19.55#ibcon#end of sib2, iclass 21, count 0 2006.201.04:29:19.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:29:19.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:29:19.55#ibcon#[25=USB\r\n] 2006.201.04:29:19.55#ibcon#*before write, iclass 21, count 0 2006.201.04:29:19.55#ibcon#enter sib2, iclass 21, count 0 2006.201.04:29:19.55#ibcon#flushed, iclass 21, count 0 2006.201.04:29:19.55#ibcon#about to write, iclass 21, count 0 2006.201.04:29:19.55#ibcon#wrote, iclass 21, count 0 2006.201.04:29:19.55#ibcon#about to read 3, iclass 21, count 0 2006.201.04:29:19.58#ibcon#read 3, iclass 21, count 0 2006.201.04:29:19.58#ibcon#about to read 4, iclass 21, count 0 2006.201.04:29:19.58#ibcon#read 4, iclass 21, count 0 2006.201.04:29:19.58#ibcon#about to read 5, iclass 21, count 0 2006.201.04:29:19.58#ibcon#read 5, iclass 21, count 0 2006.201.04:29:19.58#ibcon#about to read 6, iclass 21, count 0 2006.201.04:29:19.58#ibcon#read 6, iclass 21, count 0 2006.201.04:29:19.58#ibcon#end of sib2, iclass 21, count 0 2006.201.04:29:19.58#ibcon#*after write, iclass 21, count 0 2006.201.04:29:19.58#ibcon#*before return 0, iclass 21, count 0 2006.201.04:29:19.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:19.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:19.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:29:19.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:29:19.58$vck44/valo=7,864.99 2006.201.04:29:19.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.04:29:19.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.04:29:19.58#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:19.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:19.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:19.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:19.58#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:29:19.58#ibcon#first serial, iclass 23, count 0 2006.201.04:29:19.58#ibcon#enter sib2, iclass 23, count 0 2006.201.04:29:19.58#ibcon#flushed, iclass 23, count 0 2006.201.04:29:19.58#ibcon#about to write, iclass 23, count 0 2006.201.04:29:19.58#ibcon#wrote, iclass 23, count 0 2006.201.04:29:19.58#ibcon#about to read 3, iclass 23, count 0 2006.201.04:29:19.60#ibcon#read 3, iclass 23, count 0 2006.201.04:29:19.60#ibcon#about to read 4, iclass 23, count 0 2006.201.04:29:19.60#ibcon#read 4, iclass 23, count 0 2006.201.04:29:19.60#ibcon#about to read 5, iclass 23, count 0 2006.201.04:29:19.60#ibcon#read 5, iclass 23, count 0 2006.201.04:29:19.60#ibcon#about to read 6, iclass 23, count 0 2006.201.04:29:19.60#ibcon#read 6, iclass 23, count 0 2006.201.04:29:19.60#ibcon#end of sib2, iclass 23, count 0 2006.201.04:29:19.60#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:29:19.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:29:19.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:29:19.60#ibcon#*before write, iclass 23, count 0 2006.201.04:29:19.60#ibcon#enter sib2, iclass 23, count 0 2006.201.04:29:19.60#ibcon#flushed, iclass 23, count 0 2006.201.04:29:19.60#ibcon#about to write, iclass 23, count 0 2006.201.04:29:19.60#ibcon#wrote, iclass 23, count 0 2006.201.04:29:19.60#ibcon#about to read 3, iclass 23, count 0 2006.201.04:29:19.64#ibcon#read 3, iclass 23, count 0 2006.201.04:29:19.64#ibcon#about to read 4, iclass 23, count 0 2006.201.04:29:19.64#ibcon#read 4, iclass 23, count 0 2006.201.04:29:19.64#ibcon#about to read 5, iclass 23, count 0 2006.201.04:29:19.64#ibcon#read 5, iclass 23, count 0 2006.201.04:29:19.64#ibcon#about to read 6, iclass 23, count 0 2006.201.04:29:19.64#ibcon#read 6, iclass 23, count 0 2006.201.04:29:19.64#ibcon#end of sib2, iclass 23, count 0 2006.201.04:29:19.64#ibcon#*after write, iclass 23, count 0 2006.201.04:29:19.64#ibcon#*before return 0, iclass 23, count 0 2006.201.04:29:19.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:19.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:19.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:29:19.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:29:19.64$vck44/va=7,5 2006.201.04:29:19.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.04:29:19.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.04:29:19.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:19.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:19.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:19.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:19.70#ibcon#enter wrdev, iclass 25, count 2 2006.201.04:29:19.70#ibcon#first serial, iclass 25, count 2 2006.201.04:29:19.70#ibcon#enter sib2, iclass 25, count 2 2006.201.04:29:19.70#ibcon#flushed, iclass 25, count 2 2006.201.04:29:19.70#ibcon#about to write, iclass 25, count 2 2006.201.04:29:19.70#ibcon#wrote, iclass 25, count 2 2006.201.04:29:19.70#ibcon#about to read 3, iclass 25, count 2 2006.201.04:29:19.72#ibcon#read 3, iclass 25, count 2 2006.201.04:29:19.72#ibcon#about to read 4, iclass 25, count 2 2006.201.04:29:19.72#ibcon#read 4, iclass 25, count 2 2006.201.04:29:19.72#ibcon#about to read 5, iclass 25, count 2 2006.201.04:29:19.72#ibcon#read 5, iclass 25, count 2 2006.201.04:29:19.72#ibcon#about to read 6, iclass 25, count 2 2006.201.04:29:19.72#ibcon#read 6, iclass 25, count 2 2006.201.04:29:19.72#ibcon#end of sib2, iclass 25, count 2 2006.201.04:29:19.72#ibcon#*mode == 0, iclass 25, count 2 2006.201.04:29:19.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.04:29:19.72#ibcon#[25=AT07-05\r\n] 2006.201.04:29:19.72#ibcon#*before write, iclass 25, count 2 2006.201.04:29:19.72#ibcon#enter sib2, iclass 25, count 2 2006.201.04:29:19.72#ibcon#flushed, iclass 25, count 2 2006.201.04:29:19.72#ibcon#about to write, iclass 25, count 2 2006.201.04:29:19.72#ibcon#wrote, iclass 25, count 2 2006.201.04:29:19.72#ibcon#about to read 3, iclass 25, count 2 2006.201.04:29:19.75#ibcon#read 3, iclass 25, count 2 2006.201.04:29:19.75#ibcon#about to read 4, iclass 25, count 2 2006.201.04:29:19.75#ibcon#read 4, iclass 25, count 2 2006.201.04:29:19.75#ibcon#about to read 5, iclass 25, count 2 2006.201.04:29:19.75#ibcon#read 5, iclass 25, count 2 2006.201.04:29:19.75#ibcon#about to read 6, iclass 25, count 2 2006.201.04:29:19.75#ibcon#read 6, iclass 25, count 2 2006.201.04:29:19.75#ibcon#end of sib2, iclass 25, count 2 2006.201.04:29:19.75#ibcon#*after write, iclass 25, count 2 2006.201.04:29:19.75#ibcon#*before return 0, iclass 25, count 2 2006.201.04:29:19.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:19.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:19.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.04:29:19.75#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:19.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:19.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:19.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:19.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:29:19.87#ibcon#first serial, iclass 25, count 0 2006.201.04:29:19.87#ibcon#enter sib2, iclass 25, count 0 2006.201.04:29:19.87#ibcon#flushed, iclass 25, count 0 2006.201.04:29:19.87#ibcon#about to write, iclass 25, count 0 2006.201.04:29:19.87#ibcon#wrote, iclass 25, count 0 2006.201.04:29:19.87#ibcon#about to read 3, iclass 25, count 0 2006.201.04:29:19.89#ibcon#read 3, iclass 25, count 0 2006.201.04:29:19.89#ibcon#about to read 4, iclass 25, count 0 2006.201.04:29:19.89#ibcon#read 4, iclass 25, count 0 2006.201.04:29:19.89#ibcon#about to read 5, iclass 25, count 0 2006.201.04:29:19.89#ibcon#read 5, iclass 25, count 0 2006.201.04:29:19.89#ibcon#about to read 6, iclass 25, count 0 2006.201.04:29:19.89#ibcon#read 6, iclass 25, count 0 2006.201.04:29:19.89#ibcon#end of sib2, iclass 25, count 0 2006.201.04:29:19.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:29:19.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:29:19.89#ibcon#[25=USB\r\n] 2006.201.04:29:19.89#ibcon#*before write, iclass 25, count 0 2006.201.04:29:19.89#ibcon#enter sib2, iclass 25, count 0 2006.201.04:29:19.89#ibcon#flushed, iclass 25, count 0 2006.201.04:29:19.89#ibcon#about to write, iclass 25, count 0 2006.201.04:29:19.89#ibcon#wrote, iclass 25, count 0 2006.201.04:29:19.89#ibcon#about to read 3, iclass 25, count 0 2006.201.04:29:19.92#ibcon#read 3, iclass 25, count 0 2006.201.04:29:19.92#ibcon#about to read 4, iclass 25, count 0 2006.201.04:29:19.92#ibcon#read 4, iclass 25, count 0 2006.201.04:29:19.92#ibcon#about to read 5, iclass 25, count 0 2006.201.04:29:19.92#ibcon#read 5, iclass 25, count 0 2006.201.04:29:19.92#ibcon#about to read 6, iclass 25, count 0 2006.201.04:29:19.92#ibcon#read 6, iclass 25, count 0 2006.201.04:29:19.92#ibcon#end of sib2, iclass 25, count 0 2006.201.04:29:19.92#ibcon#*after write, iclass 25, count 0 2006.201.04:29:19.92#ibcon#*before return 0, iclass 25, count 0 2006.201.04:29:19.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:19.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:19.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:29:19.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:29:19.92$vck44/valo=8,884.99 2006.201.04:29:19.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.04:29:19.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.04:29:19.92#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:19.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:29:19.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:29:19.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:29:19.92#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:29:19.92#ibcon#first serial, iclass 27, count 0 2006.201.04:29:19.92#ibcon#enter sib2, iclass 27, count 0 2006.201.04:29:19.92#ibcon#flushed, iclass 27, count 0 2006.201.04:29:19.92#ibcon#about to write, iclass 27, count 0 2006.201.04:29:19.92#ibcon#wrote, iclass 27, count 0 2006.201.04:29:19.92#ibcon#about to read 3, iclass 27, count 0 2006.201.04:29:19.94#ibcon#read 3, iclass 27, count 0 2006.201.04:29:19.94#ibcon#about to read 4, iclass 27, count 0 2006.201.04:29:19.94#ibcon#read 4, iclass 27, count 0 2006.201.04:29:19.94#ibcon#about to read 5, iclass 27, count 0 2006.201.04:29:19.94#ibcon#read 5, iclass 27, count 0 2006.201.04:29:19.94#ibcon#about to read 6, iclass 27, count 0 2006.201.04:29:19.94#ibcon#read 6, iclass 27, count 0 2006.201.04:29:19.94#ibcon#end of sib2, iclass 27, count 0 2006.201.04:29:19.94#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:29:19.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:29:19.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:29:19.94#ibcon#*before write, iclass 27, count 0 2006.201.04:29:19.94#ibcon#enter sib2, iclass 27, count 0 2006.201.04:29:19.94#ibcon#flushed, iclass 27, count 0 2006.201.04:29:19.94#ibcon#about to write, iclass 27, count 0 2006.201.04:29:19.94#ibcon#wrote, iclass 27, count 0 2006.201.04:29:19.94#ibcon#about to read 3, iclass 27, count 0 2006.201.04:29:19.98#ibcon#read 3, iclass 27, count 0 2006.201.04:29:19.98#ibcon#about to read 4, iclass 27, count 0 2006.201.04:29:19.98#ibcon#read 4, iclass 27, count 0 2006.201.04:29:19.98#ibcon#about to read 5, iclass 27, count 0 2006.201.04:29:19.98#ibcon#read 5, iclass 27, count 0 2006.201.04:29:19.98#ibcon#about to read 6, iclass 27, count 0 2006.201.04:29:19.98#ibcon#read 6, iclass 27, count 0 2006.201.04:29:19.98#ibcon#end of sib2, iclass 27, count 0 2006.201.04:29:19.98#ibcon#*after write, iclass 27, count 0 2006.201.04:29:19.98#ibcon#*before return 0, iclass 27, count 0 2006.201.04:29:19.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:29:19.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:29:19.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:29:19.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:29:19.98$vck44/va=8,4 2006.201.04:29:19.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.04:29:19.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.04:29:19.98#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:19.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:29:20.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:29:20.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:29:20.04#ibcon#enter wrdev, iclass 29, count 2 2006.201.04:29:20.04#ibcon#first serial, iclass 29, count 2 2006.201.04:29:20.04#ibcon#enter sib2, iclass 29, count 2 2006.201.04:29:20.04#ibcon#flushed, iclass 29, count 2 2006.201.04:29:20.04#ibcon#about to write, iclass 29, count 2 2006.201.04:29:20.04#ibcon#wrote, iclass 29, count 2 2006.201.04:29:20.04#ibcon#about to read 3, iclass 29, count 2 2006.201.04:29:20.06#ibcon#read 3, iclass 29, count 2 2006.201.04:29:20.06#ibcon#about to read 4, iclass 29, count 2 2006.201.04:29:20.06#ibcon#read 4, iclass 29, count 2 2006.201.04:29:20.06#ibcon#about to read 5, iclass 29, count 2 2006.201.04:29:20.06#ibcon#read 5, iclass 29, count 2 2006.201.04:29:20.06#ibcon#about to read 6, iclass 29, count 2 2006.201.04:29:20.06#ibcon#read 6, iclass 29, count 2 2006.201.04:29:20.06#ibcon#end of sib2, iclass 29, count 2 2006.201.04:29:20.06#ibcon#*mode == 0, iclass 29, count 2 2006.201.04:29:20.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.04:29:20.06#ibcon#[25=AT08-04\r\n] 2006.201.04:29:20.06#ibcon#*before write, iclass 29, count 2 2006.201.04:29:20.06#ibcon#enter sib2, iclass 29, count 2 2006.201.04:29:20.06#ibcon#flushed, iclass 29, count 2 2006.201.04:29:20.06#ibcon#about to write, iclass 29, count 2 2006.201.04:29:20.06#ibcon#wrote, iclass 29, count 2 2006.201.04:29:20.06#ibcon#about to read 3, iclass 29, count 2 2006.201.04:29:20.09#ibcon#read 3, iclass 29, count 2 2006.201.04:29:20.09#ibcon#about to read 4, iclass 29, count 2 2006.201.04:29:20.09#ibcon#read 4, iclass 29, count 2 2006.201.04:29:20.09#ibcon#about to read 5, iclass 29, count 2 2006.201.04:29:20.09#ibcon#read 5, iclass 29, count 2 2006.201.04:29:20.09#ibcon#about to read 6, iclass 29, count 2 2006.201.04:29:20.09#ibcon#read 6, iclass 29, count 2 2006.201.04:29:20.09#ibcon#end of sib2, iclass 29, count 2 2006.201.04:29:20.09#ibcon#*after write, iclass 29, count 2 2006.201.04:29:20.09#ibcon#*before return 0, iclass 29, count 2 2006.201.04:29:20.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:29:20.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:29:20.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.04:29:20.09#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:20.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:29:20.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:29:20.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:29:20.21#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:29:20.21#ibcon#first serial, iclass 29, count 0 2006.201.04:29:20.21#ibcon#enter sib2, iclass 29, count 0 2006.201.04:29:20.21#ibcon#flushed, iclass 29, count 0 2006.201.04:29:20.21#ibcon#about to write, iclass 29, count 0 2006.201.04:29:20.21#ibcon#wrote, iclass 29, count 0 2006.201.04:29:20.21#ibcon#about to read 3, iclass 29, count 0 2006.201.04:29:20.23#ibcon#read 3, iclass 29, count 0 2006.201.04:29:20.23#ibcon#about to read 4, iclass 29, count 0 2006.201.04:29:20.23#ibcon#read 4, iclass 29, count 0 2006.201.04:29:20.23#ibcon#about to read 5, iclass 29, count 0 2006.201.04:29:20.23#ibcon#read 5, iclass 29, count 0 2006.201.04:29:20.23#ibcon#about to read 6, iclass 29, count 0 2006.201.04:29:20.23#ibcon#read 6, iclass 29, count 0 2006.201.04:29:20.23#ibcon#end of sib2, iclass 29, count 0 2006.201.04:29:20.23#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:29:20.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:29:20.23#ibcon#[25=USB\r\n] 2006.201.04:29:20.23#ibcon#*before write, iclass 29, count 0 2006.201.04:29:20.23#ibcon#enter sib2, iclass 29, count 0 2006.201.04:29:20.23#ibcon#flushed, iclass 29, count 0 2006.201.04:29:20.23#ibcon#about to write, iclass 29, count 0 2006.201.04:29:20.23#ibcon#wrote, iclass 29, count 0 2006.201.04:29:20.23#ibcon#about to read 3, iclass 29, count 0 2006.201.04:29:20.26#ibcon#read 3, iclass 29, count 0 2006.201.04:29:20.26#ibcon#about to read 4, iclass 29, count 0 2006.201.04:29:20.26#ibcon#read 4, iclass 29, count 0 2006.201.04:29:20.26#ibcon#about to read 5, iclass 29, count 0 2006.201.04:29:20.26#ibcon#read 5, iclass 29, count 0 2006.201.04:29:20.26#ibcon#about to read 6, iclass 29, count 0 2006.201.04:29:20.26#ibcon#read 6, iclass 29, count 0 2006.201.04:29:20.26#ibcon#end of sib2, iclass 29, count 0 2006.201.04:29:20.26#ibcon#*after write, iclass 29, count 0 2006.201.04:29:20.26#ibcon#*before return 0, iclass 29, count 0 2006.201.04:29:20.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:29:20.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:29:20.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:29:20.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:29:20.26$vck44/vblo=1,629.99 2006.201.04:29:20.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.04:29:20.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.04:29:20.26#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:20.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:29:20.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:29:20.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:29:20.26#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:29:20.26#ibcon#first serial, iclass 31, count 0 2006.201.04:29:20.26#ibcon#enter sib2, iclass 31, count 0 2006.201.04:29:20.26#ibcon#flushed, iclass 31, count 0 2006.201.04:29:20.26#ibcon#about to write, iclass 31, count 0 2006.201.04:29:20.26#ibcon#wrote, iclass 31, count 0 2006.201.04:29:20.26#ibcon#about to read 3, iclass 31, count 0 2006.201.04:29:20.28#ibcon#read 3, iclass 31, count 0 2006.201.04:29:20.28#ibcon#about to read 4, iclass 31, count 0 2006.201.04:29:20.28#ibcon#read 4, iclass 31, count 0 2006.201.04:29:20.28#ibcon#about to read 5, iclass 31, count 0 2006.201.04:29:20.28#ibcon#read 5, iclass 31, count 0 2006.201.04:29:20.28#ibcon#about to read 6, iclass 31, count 0 2006.201.04:29:20.28#ibcon#read 6, iclass 31, count 0 2006.201.04:29:20.28#ibcon#end of sib2, iclass 31, count 0 2006.201.04:29:20.28#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:29:20.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:29:20.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:29:20.28#ibcon#*before write, iclass 31, count 0 2006.201.04:29:20.28#ibcon#enter sib2, iclass 31, count 0 2006.201.04:29:20.28#ibcon#flushed, iclass 31, count 0 2006.201.04:29:20.28#ibcon#about to write, iclass 31, count 0 2006.201.04:29:20.28#ibcon#wrote, iclass 31, count 0 2006.201.04:29:20.28#ibcon#about to read 3, iclass 31, count 0 2006.201.04:29:20.32#ibcon#read 3, iclass 31, count 0 2006.201.04:29:20.32#ibcon#about to read 4, iclass 31, count 0 2006.201.04:29:20.32#ibcon#read 4, iclass 31, count 0 2006.201.04:29:20.32#ibcon#about to read 5, iclass 31, count 0 2006.201.04:29:20.32#ibcon#read 5, iclass 31, count 0 2006.201.04:29:20.32#ibcon#about to read 6, iclass 31, count 0 2006.201.04:29:20.32#ibcon#read 6, iclass 31, count 0 2006.201.04:29:20.32#ibcon#end of sib2, iclass 31, count 0 2006.201.04:29:20.32#ibcon#*after write, iclass 31, count 0 2006.201.04:29:20.32#ibcon#*before return 0, iclass 31, count 0 2006.201.04:29:20.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:29:20.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:29:20.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:29:20.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:29:20.32$vck44/vb=1,4 2006.201.04:29:20.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.04:29:20.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.04:29:20.32#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:20.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:29:20.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:29:20.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:29:20.32#ibcon#enter wrdev, iclass 33, count 2 2006.201.04:29:20.32#ibcon#first serial, iclass 33, count 2 2006.201.04:29:20.32#ibcon#enter sib2, iclass 33, count 2 2006.201.04:29:20.32#ibcon#flushed, iclass 33, count 2 2006.201.04:29:20.32#ibcon#about to write, iclass 33, count 2 2006.201.04:29:20.32#ibcon#wrote, iclass 33, count 2 2006.201.04:29:20.32#ibcon#about to read 3, iclass 33, count 2 2006.201.04:29:20.34#ibcon#read 3, iclass 33, count 2 2006.201.04:29:20.34#ibcon#about to read 4, iclass 33, count 2 2006.201.04:29:20.34#ibcon#read 4, iclass 33, count 2 2006.201.04:29:20.34#ibcon#about to read 5, iclass 33, count 2 2006.201.04:29:20.34#ibcon#read 5, iclass 33, count 2 2006.201.04:29:20.34#ibcon#about to read 6, iclass 33, count 2 2006.201.04:29:20.34#ibcon#read 6, iclass 33, count 2 2006.201.04:29:20.34#ibcon#end of sib2, iclass 33, count 2 2006.201.04:29:20.34#ibcon#*mode == 0, iclass 33, count 2 2006.201.04:29:20.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.04:29:20.34#ibcon#[27=AT01-04\r\n] 2006.201.04:29:20.34#ibcon#*before write, iclass 33, count 2 2006.201.04:29:20.34#ibcon#enter sib2, iclass 33, count 2 2006.201.04:29:20.34#ibcon#flushed, iclass 33, count 2 2006.201.04:29:20.34#ibcon#about to write, iclass 33, count 2 2006.201.04:29:20.34#ibcon#wrote, iclass 33, count 2 2006.201.04:29:20.34#ibcon#about to read 3, iclass 33, count 2 2006.201.04:29:20.37#ibcon#read 3, iclass 33, count 2 2006.201.04:29:20.37#ibcon#about to read 4, iclass 33, count 2 2006.201.04:29:20.37#ibcon#read 4, iclass 33, count 2 2006.201.04:29:20.37#ibcon#about to read 5, iclass 33, count 2 2006.201.04:29:20.37#ibcon#read 5, iclass 33, count 2 2006.201.04:29:20.37#ibcon#about to read 6, iclass 33, count 2 2006.201.04:29:20.37#ibcon#read 6, iclass 33, count 2 2006.201.04:29:20.37#ibcon#end of sib2, iclass 33, count 2 2006.201.04:29:20.37#ibcon#*after write, iclass 33, count 2 2006.201.04:29:20.37#ibcon#*before return 0, iclass 33, count 2 2006.201.04:29:20.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:29:20.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:29:20.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.04:29:20.37#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:20.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:29:20.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:29:20.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:29:20.49#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:29:20.49#ibcon#first serial, iclass 33, count 0 2006.201.04:29:20.49#ibcon#enter sib2, iclass 33, count 0 2006.201.04:29:20.49#ibcon#flushed, iclass 33, count 0 2006.201.04:29:20.49#ibcon#about to write, iclass 33, count 0 2006.201.04:29:20.49#ibcon#wrote, iclass 33, count 0 2006.201.04:29:20.49#ibcon#about to read 3, iclass 33, count 0 2006.201.04:29:20.51#ibcon#read 3, iclass 33, count 0 2006.201.04:29:20.51#ibcon#about to read 4, iclass 33, count 0 2006.201.04:29:20.51#ibcon#read 4, iclass 33, count 0 2006.201.04:29:20.51#ibcon#about to read 5, iclass 33, count 0 2006.201.04:29:20.51#ibcon#read 5, iclass 33, count 0 2006.201.04:29:20.51#ibcon#about to read 6, iclass 33, count 0 2006.201.04:29:20.51#ibcon#read 6, iclass 33, count 0 2006.201.04:29:20.51#ibcon#end of sib2, iclass 33, count 0 2006.201.04:29:20.51#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:29:20.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:29:20.51#ibcon#[27=USB\r\n] 2006.201.04:29:20.51#ibcon#*before write, iclass 33, count 0 2006.201.04:29:20.51#ibcon#enter sib2, iclass 33, count 0 2006.201.04:29:20.51#ibcon#flushed, iclass 33, count 0 2006.201.04:29:20.51#ibcon#about to write, iclass 33, count 0 2006.201.04:29:20.51#ibcon#wrote, iclass 33, count 0 2006.201.04:29:20.51#ibcon#about to read 3, iclass 33, count 0 2006.201.04:29:20.54#ibcon#read 3, iclass 33, count 0 2006.201.04:29:20.54#ibcon#about to read 4, iclass 33, count 0 2006.201.04:29:20.54#ibcon#read 4, iclass 33, count 0 2006.201.04:29:20.54#ibcon#about to read 5, iclass 33, count 0 2006.201.04:29:20.54#ibcon#read 5, iclass 33, count 0 2006.201.04:29:20.54#ibcon#about to read 6, iclass 33, count 0 2006.201.04:29:20.54#ibcon#read 6, iclass 33, count 0 2006.201.04:29:20.54#ibcon#end of sib2, iclass 33, count 0 2006.201.04:29:20.54#ibcon#*after write, iclass 33, count 0 2006.201.04:29:20.54#ibcon#*before return 0, iclass 33, count 0 2006.201.04:29:20.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:29:20.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:29:20.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:29:20.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:29:20.54$vck44/vblo=2,634.99 2006.201.04:29:20.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.04:29:20.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.04:29:20.54#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:20.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:20.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:20.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:20.54#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:29:20.54#ibcon#first serial, iclass 35, count 0 2006.201.04:29:20.54#ibcon#enter sib2, iclass 35, count 0 2006.201.04:29:20.54#ibcon#flushed, iclass 35, count 0 2006.201.04:29:20.54#ibcon#about to write, iclass 35, count 0 2006.201.04:29:20.54#ibcon#wrote, iclass 35, count 0 2006.201.04:29:20.54#ibcon#about to read 3, iclass 35, count 0 2006.201.04:29:20.56#ibcon#read 3, iclass 35, count 0 2006.201.04:29:20.56#ibcon#about to read 4, iclass 35, count 0 2006.201.04:29:20.56#ibcon#read 4, iclass 35, count 0 2006.201.04:29:20.56#ibcon#about to read 5, iclass 35, count 0 2006.201.04:29:20.56#ibcon#read 5, iclass 35, count 0 2006.201.04:29:20.56#ibcon#about to read 6, iclass 35, count 0 2006.201.04:29:20.56#ibcon#read 6, iclass 35, count 0 2006.201.04:29:20.56#ibcon#end of sib2, iclass 35, count 0 2006.201.04:29:20.56#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:29:20.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:29:20.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:29:20.56#ibcon#*before write, iclass 35, count 0 2006.201.04:29:20.56#ibcon#enter sib2, iclass 35, count 0 2006.201.04:29:20.56#ibcon#flushed, iclass 35, count 0 2006.201.04:29:20.56#ibcon#about to write, iclass 35, count 0 2006.201.04:29:20.56#ibcon#wrote, iclass 35, count 0 2006.201.04:29:20.56#ibcon#about to read 3, iclass 35, count 0 2006.201.04:29:20.60#ibcon#read 3, iclass 35, count 0 2006.201.04:29:20.60#ibcon#about to read 4, iclass 35, count 0 2006.201.04:29:20.60#ibcon#read 4, iclass 35, count 0 2006.201.04:29:20.60#ibcon#about to read 5, iclass 35, count 0 2006.201.04:29:20.60#ibcon#read 5, iclass 35, count 0 2006.201.04:29:20.60#ibcon#about to read 6, iclass 35, count 0 2006.201.04:29:20.60#ibcon#read 6, iclass 35, count 0 2006.201.04:29:20.60#ibcon#end of sib2, iclass 35, count 0 2006.201.04:29:20.60#ibcon#*after write, iclass 35, count 0 2006.201.04:29:20.60#ibcon#*before return 0, iclass 35, count 0 2006.201.04:29:20.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:20.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:29:20.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:29:20.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:29:20.60$vck44/vb=2,5 2006.201.04:29:20.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.04:29:20.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.04:29:20.60#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:20.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:20.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:20.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:20.66#ibcon#enter wrdev, iclass 37, count 2 2006.201.04:29:20.66#ibcon#first serial, iclass 37, count 2 2006.201.04:29:20.66#ibcon#enter sib2, iclass 37, count 2 2006.201.04:29:20.66#ibcon#flushed, iclass 37, count 2 2006.201.04:29:20.66#ibcon#about to write, iclass 37, count 2 2006.201.04:29:20.66#ibcon#wrote, iclass 37, count 2 2006.201.04:29:20.66#ibcon#about to read 3, iclass 37, count 2 2006.201.04:29:20.68#ibcon#read 3, iclass 37, count 2 2006.201.04:29:20.68#ibcon#about to read 4, iclass 37, count 2 2006.201.04:29:20.68#ibcon#read 4, iclass 37, count 2 2006.201.04:29:20.68#ibcon#about to read 5, iclass 37, count 2 2006.201.04:29:20.68#ibcon#read 5, iclass 37, count 2 2006.201.04:29:20.68#ibcon#about to read 6, iclass 37, count 2 2006.201.04:29:20.68#ibcon#read 6, iclass 37, count 2 2006.201.04:29:20.68#ibcon#end of sib2, iclass 37, count 2 2006.201.04:29:20.68#ibcon#*mode == 0, iclass 37, count 2 2006.201.04:29:20.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.04:29:20.68#ibcon#[27=AT02-05\r\n] 2006.201.04:29:20.68#ibcon#*before write, iclass 37, count 2 2006.201.04:29:20.68#ibcon#enter sib2, iclass 37, count 2 2006.201.04:29:20.68#ibcon#flushed, iclass 37, count 2 2006.201.04:29:20.68#ibcon#about to write, iclass 37, count 2 2006.201.04:29:20.68#ibcon#wrote, iclass 37, count 2 2006.201.04:29:20.68#ibcon#about to read 3, iclass 37, count 2 2006.201.04:29:20.71#ibcon#read 3, iclass 37, count 2 2006.201.04:29:20.71#ibcon#about to read 4, iclass 37, count 2 2006.201.04:29:20.71#ibcon#read 4, iclass 37, count 2 2006.201.04:29:20.71#ibcon#about to read 5, iclass 37, count 2 2006.201.04:29:20.71#ibcon#read 5, iclass 37, count 2 2006.201.04:29:20.71#ibcon#about to read 6, iclass 37, count 2 2006.201.04:29:20.71#ibcon#read 6, iclass 37, count 2 2006.201.04:29:20.71#ibcon#end of sib2, iclass 37, count 2 2006.201.04:29:20.71#ibcon#*after write, iclass 37, count 2 2006.201.04:29:20.71#ibcon#*before return 0, iclass 37, count 2 2006.201.04:29:20.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:20.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:29:20.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.04:29:20.71#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:20.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:20.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:20.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:20.83#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:29:20.83#ibcon#first serial, iclass 37, count 0 2006.201.04:29:20.83#ibcon#enter sib2, iclass 37, count 0 2006.201.04:29:20.83#ibcon#flushed, iclass 37, count 0 2006.201.04:29:20.83#ibcon#about to write, iclass 37, count 0 2006.201.04:29:20.83#ibcon#wrote, iclass 37, count 0 2006.201.04:29:20.83#ibcon#about to read 3, iclass 37, count 0 2006.201.04:29:20.85#ibcon#read 3, iclass 37, count 0 2006.201.04:29:20.85#ibcon#about to read 4, iclass 37, count 0 2006.201.04:29:20.85#ibcon#read 4, iclass 37, count 0 2006.201.04:29:20.85#ibcon#about to read 5, iclass 37, count 0 2006.201.04:29:20.85#ibcon#read 5, iclass 37, count 0 2006.201.04:29:20.85#ibcon#about to read 6, iclass 37, count 0 2006.201.04:29:20.85#ibcon#read 6, iclass 37, count 0 2006.201.04:29:20.85#ibcon#end of sib2, iclass 37, count 0 2006.201.04:29:20.85#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:29:20.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:29:20.85#ibcon#[27=USB\r\n] 2006.201.04:29:20.85#ibcon#*before write, iclass 37, count 0 2006.201.04:29:20.85#ibcon#enter sib2, iclass 37, count 0 2006.201.04:29:20.85#ibcon#flushed, iclass 37, count 0 2006.201.04:29:20.85#ibcon#about to write, iclass 37, count 0 2006.201.04:29:20.85#ibcon#wrote, iclass 37, count 0 2006.201.04:29:20.85#ibcon#about to read 3, iclass 37, count 0 2006.201.04:29:20.88#ibcon#read 3, iclass 37, count 0 2006.201.04:29:20.88#ibcon#about to read 4, iclass 37, count 0 2006.201.04:29:20.88#ibcon#read 4, iclass 37, count 0 2006.201.04:29:20.88#ibcon#about to read 5, iclass 37, count 0 2006.201.04:29:20.88#ibcon#read 5, iclass 37, count 0 2006.201.04:29:20.88#ibcon#about to read 6, iclass 37, count 0 2006.201.04:29:20.88#ibcon#read 6, iclass 37, count 0 2006.201.04:29:20.88#ibcon#end of sib2, iclass 37, count 0 2006.201.04:29:20.88#ibcon#*after write, iclass 37, count 0 2006.201.04:29:20.88#ibcon#*before return 0, iclass 37, count 0 2006.201.04:29:20.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:20.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:29:20.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:29:20.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:29:20.88$vck44/vblo=3,649.99 2006.201.04:29:20.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.04:29:20.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.04:29:20.88#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:20.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:20.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:20.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:20.88#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:29:20.88#ibcon#first serial, iclass 39, count 0 2006.201.04:29:20.88#ibcon#enter sib2, iclass 39, count 0 2006.201.04:29:20.88#ibcon#flushed, iclass 39, count 0 2006.201.04:29:20.88#ibcon#about to write, iclass 39, count 0 2006.201.04:29:20.88#ibcon#wrote, iclass 39, count 0 2006.201.04:29:20.88#ibcon#about to read 3, iclass 39, count 0 2006.201.04:29:20.90#ibcon#read 3, iclass 39, count 0 2006.201.04:29:20.90#ibcon#about to read 4, iclass 39, count 0 2006.201.04:29:20.90#ibcon#read 4, iclass 39, count 0 2006.201.04:29:20.90#ibcon#about to read 5, iclass 39, count 0 2006.201.04:29:20.90#ibcon#read 5, iclass 39, count 0 2006.201.04:29:20.90#ibcon#about to read 6, iclass 39, count 0 2006.201.04:29:20.90#ibcon#read 6, iclass 39, count 0 2006.201.04:29:20.90#ibcon#end of sib2, iclass 39, count 0 2006.201.04:29:20.90#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:29:20.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:29:20.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:29:20.90#ibcon#*before write, iclass 39, count 0 2006.201.04:29:20.90#ibcon#enter sib2, iclass 39, count 0 2006.201.04:29:20.90#ibcon#flushed, iclass 39, count 0 2006.201.04:29:20.90#ibcon#about to write, iclass 39, count 0 2006.201.04:29:20.90#ibcon#wrote, iclass 39, count 0 2006.201.04:29:20.90#ibcon#about to read 3, iclass 39, count 0 2006.201.04:29:20.94#ibcon#read 3, iclass 39, count 0 2006.201.04:29:20.94#ibcon#about to read 4, iclass 39, count 0 2006.201.04:29:20.94#ibcon#read 4, iclass 39, count 0 2006.201.04:29:20.94#ibcon#about to read 5, iclass 39, count 0 2006.201.04:29:20.94#ibcon#read 5, iclass 39, count 0 2006.201.04:29:20.94#ibcon#about to read 6, iclass 39, count 0 2006.201.04:29:20.94#ibcon#read 6, iclass 39, count 0 2006.201.04:29:20.94#ibcon#end of sib2, iclass 39, count 0 2006.201.04:29:20.94#ibcon#*after write, iclass 39, count 0 2006.201.04:29:20.94#ibcon#*before return 0, iclass 39, count 0 2006.201.04:29:20.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:20.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:29:20.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:29:20.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:29:20.94$vck44/vb=3,4 2006.201.04:29:20.94#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.04:29:20.94#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.04:29:20.94#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:20.94#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:21.00#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:21.00#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:21.00#ibcon#enter wrdev, iclass 2, count 2 2006.201.04:29:21.00#ibcon#first serial, iclass 2, count 2 2006.201.04:29:21.00#ibcon#enter sib2, iclass 2, count 2 2006.201.04:29:21.00#ibcon#flushed, iclass 2, count 2 2006.201.04:29:21.00#ibcon#about to write, iclass 2, count 2 2006.201.04:29:21.00#ibcon#wrote, iclass 2, count 2 2006.201.04:29:21.00#ibcon#about to read 3, iclass 2, count 2 2006.201.04:29:21.02#ibcon#read 3, iclass 2, count 2 2006.201.04:29:21.02#ibcon#about to read 4, iclass 2, count 2 2006.201.04:29:21.02#ibcon#read 4, iclass 2, count 2 2006.201.04:29:21.02#ibcon#about to read 5, iclass 2, count 2 2006.201.04:29:21.02#ibcon#read 5, iclass 2, count 2 2006.201.04:29:21.02#ibcon#about to read 6, iclass 2, count 2 2006.201.04:29:21.02#ibcon#read 6, iclass 2, count 2 2006.201.04:29:21.02#ibcon#end of sib2, iclass 2, count 2 2006.201.04:29:21.02#ibcon#*mode == 0, iclass 2, count 2 2006.201.04:29:21.02#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.04:29:21.02#ibcon#[27=AT03-04\r\n] 2006.201.04:29:21.02#ibcon#*before write, iclass 2, count 2 2006.201.04:29:21.02#ibcon#enter sib2, iclass 2, count 2 2006.201.04:29:21.02#ibcon#flushed, iclass 2, count 2 2006.201.04:29:21.02#ibcon#about to write, iclass 2, count 2 2006.201.04:29:21.02#ibcon#wrote, iclass 2, count 2 2006.201.04:29:21.02#ibcon#about to read 3, iclass 2, count 2 2006.201.04:29:21.05#ibcon#read 3, iclass 2, count 2 2006.201.04:29:21.05#ibcon#about to read 4, iclass 2, count 2 2006.201.04:29:21.05#ibcon#read 4, iclass 2, count 2 2006.201.04:29:21.05#ibcon#about to read 5, iclass 2, count 2 2006.201.04:29:21.05#ibcon#read 5, iclass 2, count 2 2006.201.04:29:21.05#ibcon#about to read 6, iclass 2, count 2 2006.201.04:29:21.05#ibcon#read 6, iclass 2, count 2 2006.201.04:29:21.05#ibcon#end of sib2, iclass 2, count 2 2006.201.04:29:21.05#ibcon#*after write, iclass 2, count 2 2006.201.04:29:21.05#ibcon#*before return 0, iclass 2, count 2 2006.201.04:29:21.05#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:21.05#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:29:21.05#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.04:29:21.05#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:21.05#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:21.17#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:21.17#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:21.17#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:29:21.17#ibcon#first serial, iclass 2, count 0 2006.201.04:29:21.17#ibcon#enter sib2, iclass 2, count 0 2006.201.04:29:21.17#ibcon#flushed, iclass 2, count 0 2006.201.04:29:21.17#ibcon#about to write, iclass 2, count 0 2006.201.04:29:21.17#ibcon#wrote, iclass 2, count 0 2006.201.04:29:21.17#ibcon#about to read 3, iclass 2, count 0 2006.201.04:29:21.19#ibcon#read 3, iclass 2, count 0 2006.201.04:29:21.19#ibcon#about to read 4, iclass 2, count 0 2006.201.04:29:21.19#ibcon#read 4, iclass 2, count 0 2006.201.04:29:21.19#ibcon#about to read 5, iclass 2, count 0 2006.201.04:29:21.19#ibcon#read 5, iclass 2, count 0 2006.201.04:29:21.19#ibcon#about to read 6, iclass 2, count 0 2006.201.04:29:21.19#ibcon#read 6, iclass 2, count 0 2006.201.04:29:21.19#ibcon#end of sib2, iclass 2, count 0 2006.201.04:29:21.19#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:29:21.19#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:29:21.19#ibcon#[27=USB\r\n] 2006.201.04:29:21.19#ibcon#*before write, iclass 2, count 0 2006.201.04:29:21.19#ibcon#enter sib2, iclass 2, count 0 2006.201.04:29:21.19#ibcon#flushed, iclass 2, count 0 2006.201.04:29:21.19#ibcon#about to write, iclass 2, count 0 2006.201.04:29:21.19#ibcon#wrote, iclass 2, count 0 2006.201.04:29:21.19#ibcon#about to read 3, iclass 2, count 0 2006.201.04:29:21.22#ibcon#read 3, iclass 2, count 0 2006.201.04:29:21.22#ibcon#about to read 4, iclass 2, count 0 2006.201.04:29:21.22#ibcon#read 4, iclass 2, count 0 2006.201.04:29:21.22#ibcon#about to read 5, iclass 2, count 0 2006.201.04:29:21.22#ibcon#read 5, iclass 2, count 0 2006.201.04:29:21.22#ibcon#about to read 6, iclass 2, count 0 2006.201.04:29:21.22#ibcon#read 6, iclass 2, count 0 2006.201.04:29:21.22#ibcon#end of sib2, iclass 2, count 0 2006.201.04:29:21.22#ibcon#*after write, iclass 2, count 0 2006.201.04:29:21.22#ibcon#*before return 0, iclass 2, count 0 2006.201.04:29:21.22#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:21.22#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:29:21.22#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:29:21.22#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:29:21.22$vck44/vblo=4,679.99 2006.201.04:29:21.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.04:29:21.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.04:29:21.22#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:21.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:21.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:21.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:21.22#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:29:21.22#ibcon#first serial, iclass 5, count 0 2006.201.04:29:21.22#ibcon#enter sib2, iclass 5, count 0 2006.201.04:29:21.22#ibcon#flushed, iclass 5, count 0 2006.201.04:29:21.22#ibcon#about to write, iclass 5, count 0 2006.201.04:29:21.22#ibcon#wrote, iclass 5, count 0 2006.201.04:29:21.22#ibcon#about to read 3, iclass 5, count 0 2006.201.04:29:21.24#ibcon#read 3, iclass 5, count 0 2006.201.04:29:21.24#ibcon#about to read 4, iclass 5, count 0 2006.201.04:29:21.24#ibcon#read 4, iclass 5, count 0 2006.201.04:29:21.24#ibcon#about to read 5, iclass 5, count 0 2006.201.04:29:21.24#ibcon#read 5, iclass 5, count 0 2006.201.04:29:21.24#ibcon#about to read 6, iclass 5, count 0 2006.201.04:29:21.24#ibcon#read 6, iclass 5, count 0 2006.201.04:29:21.24#ibcon#end of sib2, iclass 5, count 0 2006.201.04:29:21.24#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:29:21.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:29:21.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:29:21.24#ibcon#*before write, iclass 5, count 0 2006.201.04:29:21.24#ibcon#enter sib2, iclass 5, count 0 2006.201.04:29:21.24#ibcon#flushed, iclass 5, count 0 2006.201.04:29:21.24#ibcon#about to write, iclass 5, count 0 2006.201.04:29:21.24#ibcon#wrote, iclass 5, count 0 2006.201.04:29:21.24#ibcon#about to read 3, iclass 5, count 0 2006.201.04:29:21.28#ibcon#read 3, iclass 5, count 0 2006.201.04:29:21.28#ibcon#about to read 4, iclass 5, count 0 2006.201.04:29:21.28#ibcon#read 4, iclass 5, count 0 2006.201.04:29:21.28#ibcon#about to read 5, iclass 5, count 0 2006.201.04:29:21.28#ibcon#read 5, iclass 5, count 0 2006.201.04:29:21.28#ibcon#about to read 6, iclass 5, count 0 2006.201.04:29:21.28#ibcon#read 6, iclass 5, count 0 2006.201.04:29:21.28#ibcon#end of sib2, iclass 5, count 0 2006.201.04:29:21.28#ibcon#*after write, iclass 5, count 0 2006.201.04:29:21.28#ibcon#*before return 0, iclass 5, count 0 2006.201.04:29:21.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:21.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:29:21.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:29:21.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:29:21.28$vck44/vb=4,5 2006.201.04:29:21.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.04:29:21.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.04:29:21.28#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:21.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:21.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:21.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:21.34#ibcon#enter wrdev, iclass 7, count 2 2006.201.04:29:21.34#ibcon#first serial, iclass 7, count 2 2006.201.04:29:21.34#ibcon#enter sib2, iclass 7, count 2 2006.201.04:29:21.34#ibcon#flushed, iclass 7, count 2 2006.201.04:29:21.34#ibcon#about to write, iclass 7, count 2 2006.201.04:29:21.34#ibcon#wrote, iclass 7, count 2 2006.201.04:29:21.34#ibcon#about to read 3, iclass 7, count 2 2006.201.04:29:21.36#ibcon#read 3, iclass 7, count 2 2006.201.04:29:21.36#ibcon#about to read 4, iclass 7, count 2 2006.201.04:29:21.36#ibcon#read 4, iclass 7, count 2 2006.201.04:29:21.36#ibcon#about to read 5, iclass 7, count 2 2006.201.04:29:21.36#ibcon#read 5, iclass 7, count 2 2006.201.04:29:21.36#ibcon#about to read 6, iclass 7, count 2 2006.201.04:29:21.36#ibcon#read 6, iclass 7, count 2 2006.201.04:29:21.36#ibcon#end of sib2, iclass 7, count 2 2006.201.04:29:21.36#ibcon#*mode == 0, iclass 7, count 2 2006.201.04:29:21.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.04:29:21.36#ibcon#[27=AT04-05\r\n] 2006.201.04:29:21.36#ibcon#*before write, iclass 7, count 2 2006.201.04:29:21.36#ibcon#enter sib2, iclass 7, count 2 2006.201.04:29:21.36#ibcon#flushed, iclass 7, count 2 2006.201.04:29:21.36#ibcon#about to write, iclass 7, count 2 2006.201.04:29:21.36#ibcon#wrote, iclass 7, count 2 2006.201.04:29:21.36#ibcon#about to read 3, iclass 7, count 2 2006.201.04:29:21.39#ibcon#read 3, iclass 7, count 2 2006.201.04:29:21.39#ibcon#about to read 4, iclass 7, count 2 2006.201.04:29:21.39#ibcon#read 4, iclass 7, count 2 2006.201.04:29:21.39#ibcon#about to read 5, iclass 7, count 2 2006.201.04:29:21.39#ibcon#read 5, iclass 7, count 2 2006.201.04:29:21.39#ibcon#about to read 6, iclass 7, count 2 2006.201.04:29:21.39#ibcon#read 6, iclass 7, count 2 2006.201.04:29:21.39#ibcon#end of sib2, iclass 7, count 2 2006.201.04:29:21.39#ibcon#*after write, iclass 7, count 2 2006.201.04:29:21.39#ibcon#*before return 0, iclass 7, count 2 2006.201.04:29:21.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:21.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:29:21.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.04:29:21.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:21.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:21.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:21.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:21.51#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:29:21.51#ibcon#first serial, iclass 7, count 0 2006.201.04:29:21.51#ibcon#enter sib2, iclass 7, count 0 2006.201.04:29:21.51#ibcon#flushed, iclass 7, count 0 2006.201.04:29:21.51#ibcon#about to write, iclass 7, count 0 2006.201.04:29:21.51#ibcon#wrote, iclass 7, count 0 2006.201.04:29:21.51#ibcon#about to read 3, iclass 7, count 0 2006.201.04:29:21.53#ibcon#read 3, iclass 7, count 0 2006.201.04:29:21.53#ibcon#about to read 4, iclass 7, count 0 2006.201.04:29:21.53#ibcon#read 4, iclass 7, count 0 2006.201.04:29:21.53#ibcon#about to read 5, iclass 7, count 0 2006.201.04:29:21.53#ibcon#read 5, iclass 7, count 0 2006.201.04:29:21.53#ibcon#about to read 6, iclass 7, count 0 2006.201.04:29:21.53#ibcon#read 6, iclass 7, count 0 2006.201.04:29:21.53#ibcon#end of sib2, iclass 7, count 0 2006.201.04:29:21.53#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:29:21.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:29:21.53#ibcon#[27=USB\r\n] 2006.201.04:29:21.53#ibcon#*before write, iclass 7, count 0 2006.201.04:29:21.53#ibcon#enter sib2, iclass 7, count 0 2006.201.04:29:21.53#ibcon#flushed, iclass 7, count 0 2006.201.04:29:21.53#ibcon#about to write, iclass 7, count 0 2006.201.04:29:21.53#ibcon#wrote, iclass 7, count 0 2006.201.04:29:21.53#ibcon#about to read 3, iclass 7, count 0 2006.201.04:29:21.56#ibcon#read 3, iclass 7, count 0 2006.201.04:29:21.56#ibcon#about to read 4, iclass 7, count 0 2006.201.04:29:21.56#ibcon#read 4, iclass 7, count 0 2006.201.04:29:21.56#ibcon#about to read 5, iclass 7, count 0 2006.201.04:29:21.56#ibcon#read 5, iclass 7, count 0 2006.201.04:29:21.56#ibcon#about to read 6, iclass 7, count 0 2006.201.04:29:21.56#ibcon#read 6, iclass 7, count 0 2006.201.04:29:21.56#ibcon#end of sib2, iclass 7, count 0 2006.201.04:29:21.56#ibcon#*after write, iclass 7, count 0 2006.201.04:29:21.56#ibcon#*before return 0, iclass 7, count 0 2006.201.04:29:21.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:21.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:29:21.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:29:21.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:29:21.56$vck44/vblo=5,709.99 2006.201.04:29:21.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.04:29:21.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.04:29:21.56#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:21.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:21.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:21.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:21.56#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:29:21.56#ibcon#first serial, iclass 11, count 0 2006.201.04:29:21.56#ibcon#enter sib2, iclass 11, count 0 2006.201.04:29:21.56#ibcon#flushed, iclass 11, count 0 2006.201.04:29:21.56#ibcon#about to write, iclass 11, count 0 2006.201.04:29:21.56#ibcon#wrote, iclass 11, count 0 2006.201.04:29:21.56#ibcon#about to read 3, iclass 11, count 0 2006.201.04:29:21.58#ibcon#read 3, iclass 11, count 0 2006.201.04:29:21.58#ibcon#about to read 4, iclass 11, count 0 2006.201.04:29:21.58#ibcon#read 4, iclass 11, count 0 2006.201.04:29:21.58#ibcon#about to read 5, iclass 11, count 0 2006.201.04:29:21.58#ibcon#read 5, iclass 11, count 0 2006.201.04:29:21.58#ibcon#about to read 6, iclass 11, count 0 2006.201.04:29:21.58#ibcon#read 6, iclass 11, count 0 2006.201.04:29:21.58#ibcon#end of sib2, iclass 11, count 0 2006.201.04:29:21.58#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:29:21.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:29:21.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:29:21.58#ibcon#*before write, iclass 11, count 0 2006.201.04:29:21.58#ibcon#enter sib2, iclass 11, count 0 2006.201.04:29:21.58#ibcon#flushed, iclass 11, count 0 2006.201.04:29:21.58#ibcon#about to write, iclass 11, count 0 2006.201.04:29:21.58#ibcon#wrote, iclass 11, count 0 2006.201.04:29:21.58#ibcon#about to read 3, iclass 11, count 0 2006.201.04:29:21.62#ibcon#read 3, iclass 11, count 0 2006.201.04:29:21.62#ibcon#about to read 4, iclass 11, count 0 2006.201.04:29:21.62#ibcon#read 4, iclass 11, count 0 2006.201.04:29:21.62#ibcon#about to read 5, iclass 11, count 0 2006.201.04:29:21.62#ibcon#read 5, iclass 11, count 0 2006.201.04:29:21.62#ibcon#about to read 6, iclass 11, count 0 2006.201.04:29:21.62#ibcon#read 6, iclass 11, count 0 2006.201.04:29:21.62#ibcon#end of sib2, iclass 11, count 0 2006.201.04:29:21.62#ibcon#*after write, iclass 11, count 0 2006.201.04:29:21.62#ibcon#*before return 0, iclass 11, count 0 2006.201.04:29:21.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:21.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:29:21.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:29:21.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:29:21.62$vck44/vb=5,4 2006.201.04:29:21.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.04:29:21.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.04:29:21.62#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:21.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:21.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:21.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:21.68#ibcon#enter wrdev, iclass 13, count 2 2006.201.04:29:21.68#ibcon#first serial, iclass 13, count 2 2006.201.04:29:21.68#ibcon#enter sib2, iclass 13, count 2 2006.201.04:29:21.68#ibcon#flushed, iclass 13, count 2 2006.201.04:29:21.68#ibcon#about to write, iclass 13, count 2 2006.201.04:29:21.68#ibcon#wrote, iclass 13, count 2 2006.201.04:29:21.68#ibcon#about to read 3, iclass 13, count 2 2006.201.04:29:21.70#ibcon#read 3, iclass 13, count 2 2006.201.04:29:21.70#ibcon#about to read 4, iclass 13, count 2 2006.201.04:29:21.70#ibcon#read 4, iclass 13, count 2 2006.201.04:29:21.70#ibcon#about to read 5, iclass 13, count 2 2006.201.04:29:21.70#ibcon#read 5, iclass 13, count 2 2006.201.04:29:21.70#ibcon#about to read 6, iclass 13, count 2 2006.201.04:29:21.70#ibcon#read 6, iclass 13, count 2 2006.201.04:29:21.70#ibcon#end of sib2, iclass 13, count 2 2006.201.04:29:21.70#ibcon#*mode == 0, iclass 13, count 2 2006.201.04:29:21.70#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.04:29:21.70#ibcon#[27=AT05-04\r\n] 2006.201.04:29:21.70#ibcon#*before write, iclass 13, count 2 2006.201.04:29:21.70#ibcon#enter sib2, iclass 13, count 2 2006.201.04:29:21.70#ibcon#flushed, iclass 13, count 2 2006.201.04:29:21.70#ibcon#about to write, iclass 13, count 2 2006.201.04:29:21.70#ibcon#wrote, iclass 13, count 2 2006.201.04:29:21.70#ibcon#about to read 3, iclass 13, count 2 2006.201.04:29:21.73#ibcon#read 3, iclass 13, count 2 2006.201.04:29:21.73#ibcon#about to read 4, iclass 13, count 2 2006.201.04:29:21.73#ibcon#read 4, iclass 13, count 2 2006.201.04:29:21.73#ibcon#about to read 5, iclass 13, count 2 2006.201.04:29:21.73#ibcon#read 5, iclass 13, count 2 2006.201.04:29:21.73#ibcon#about to read 6, iclass 13, count 2 2006.201.04:29:21.73#ibcon#read 6, iclass 13, count 2 2006.201.04:29:21.73#ibcon#end of sib2, iclass 13, count 2 2006.201.04:29:21.73#ibcon#*after write, iclass 13, count 2 2006.201.04:29:21.73#ibcon#*before return 0, iclass 13, count 2 2006.201.04:29:21.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:21.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:29:21.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.04:29:21.73#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:21.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:21.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:21.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:21.85#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:29:21.85#ibcon#first serial, iclass 13, count 0 2006.201.04:29:21.85#ibcon#enter sib2, iclass 13, count 0 2006.201.04:29:21.85#ibcon#flushed, iclass 13, count 0 2006.201.04:29:21.85#ibcon#about to write, iclass 13, count 0 2006.201.04:29:21.85#ibcon#wrote, iclass 13, count 0 2006.201.04:29:21.85#ibcon#about to read 3, iclass 13, count 0 2006.201.04:29:21.87#ibcon#read 3, iclass 13, count 0 2006.201.04:29:21.87#ibcon#about to read 4, iclass 13, count 0 2006.201.04:29:21.87#ibcon#read 4, iclass 13, count 0 2006.201.04:29:21.87#ibcon#about to read 5, iclass 13, count 0 2006.201.04:29:21.87#ibcon#read 5, iclass 13, count 0 2006.201.04:29:21.87#ibcon#about to read 6, iclass 13, count 0 2006.201.04:29:21.87#ibcon#read 6, iclass 13, count 0 2006.201.04:29:21.87#ibcon#end of sib2, iclass 13, count 0 2006.201.04:29:21.87#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:29:21.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:29:21.87#ibcon#[27=USB\r\n] 2006.201.04:29:21.87#ibcon#*before write, iclass 13, count 0 2006.201.04:29:21.87#ibcon#enter sib2, iclass 13, count 0 2006.201.04:29:21.87#ibcon#flushed, iclass 13, count 0 2006.201.04:29:21.87#ibcon#about to write, iclass 13, count 0 2006.201.04:29:21.87#ibcon#wrote, iclass 13, count 0 2006.201.04:29:21.87#ibcon#about to read 3, iclass 13, count 0 2006.201.04:29:21.90#ibcon#read 3, iclass 13, count 0 2006.201.04:29:21.90#ibcon#about to read 4, iclass 13, count 0 2006.201.04:29:21.90#ibcon#read 4, iclass 13, count 0 2006.201.04:29:21.90#ibcon#about to read 5, iclass 13, count 0 2006.201.04:29:21.90#ibcon#read 5, iclass 13, count 0 2006.201.04:29:21.90#ibcon#about to read 6, iclass 13, count 0 2006.201.04:29:21.90#ibcon#read 6, iclass 13, count 0 2006.201.04:29:21.90#ibcon#end of sib2, iclass 13, count 0 2006.201.04:29:21.90#ibcon#*after write, iclass 13, count 0 2006.201.04:29:21.90#ibcon#*before return 0, iclass 13, count 0 2006.201.04:29:21.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:21.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:29:21.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:29:21.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:29:21.90$vck44/vblo=6,719.99 2006.201.04:29:21.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.04:29:21.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.04:29:21.90#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:21.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:21.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:21.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:21.90#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:29:21.90#ibcon#first serial, iclass 15, count 0 2006.201.04:29:21.90#ibcon#enter sib2, iclass 15, count 0 2006.201.04:29:21.90#ibcon#flushed, iclass 15, count 0 2006.201.04:29:21.90#ibcon#about to write, iclass 15, count 0 2006.201.04:29:21.90#ibcon#wrote, iclass 15, count 0 2006.201.04:29:21.90#ibcon#about to read 3, iclass 15, count 0 2006.201.04:29:21.92#ibcon#read 3, iclass 15, count 0 2006.201.04:29:21.92#ibcon#about to read 4, iclass 15, count 0 2006.201.04:29:21.92#ibcon#read 4, iclass 15, count 0 2006.201.04:29:21.92#ibcon#about to read 5, iclass 15, count 0 2006.201.04:29:21.92#ibcon#read 5, iclass 15, count 0 2006.201.04:29:21.92#ibcon#about to read 6, iclass 15, count 0 2006.201.04:29:21.92#ibcon#read 6, iclass 15, count 0 2006.201.04:29:21.92#ibcon#end of sib2, iclass 15, count 0 2006.201.04:29:21.92#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:29:21.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:29:21.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:29:21.92#ibcon#*before write, iclass 15, count 0 2006.201.04:29:21.92#ibcon#enter sib2, iclass 15, count 0 2006.201.04:29:21.92#ibcon#flushed, iclass 15, count 0 2006.201.04:29:21.92#ibcon#about to write, iclass 15, count 0 2006.201.04:29:21.92#ibcon#wrote, iclass 15, count 0 2006.201.04:29:21.92#ibcon#about to read 3, iclass 15, count 0 2006.201.04:29:21.96#ibcon#read 3, iclass 15, count 0 2006.201.04:29:21.96#ibcon#about to read 4, iclass 15, count 0 2006.201.04:29:21.96#ibcon#read 4, iclass 15, count 0 2006.201.04:29:21.96#ibcon#about to read 5, iclass 15, count 0 2006.201.04:29:21.96#ibcon#read 5, iclass 15, count 0 2006.201.04:29:21.96#ibcon#about to read 6, iclass 15, count 0 2006.201.04:29:21.96#ibcon#read 6, iclass 15, count 0 2006.201.04:29:21.96#ibcon#end of sib2, iclass 15, count 0 2006.201.04:29:21.96#ibcon#*after write, iclass 15, count 0 2006.201.04:29:21.96#ibcon#*before return 0, iclass 15, count 0 2006.201.04:29:21.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:21.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:29:21.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:29:21.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:29:21.96$vck44/vb=6,4 2006.201.04:29:21.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.04:29:21.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.04:29:21.96#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:21.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:22.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:22.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:22.02#ibcon#enter wrdev, iclass 17, count 2 2006.201.04:29:22.02#ibcon#first serial, iclass 17, count 2 2006.201.04:29:22.02#ibcon#enter sib2, iclass 17, count 2 2006.201.04:29:22.02#ibcon#flushed, iclass 17, count 2 2006.201.04:29:22.02#ibcon#about to write, iclass 17, count 2 2006.201.04:29:22.02#ibcon#wrote, iclass 17, count 2 2006.201.04:29:22.02#ibcon#about to read 3, iclass 17, count 2 2006.201.04:29:22.04#ibcon#read 3, iclass 17, count 2 2006.201.04:29:22.04#ibcon#about to read 4, iclass 17, count 2 2006.201.04:29:22.04#ibcon#read 4, iclass 17, count 2 2006.201.04:29:22.04#ibcon#about to read 5, iclass 17, count 2 2006.201.04:29:22.04#ibcon#read 5, iclass 17, count 2 2006.201.04:29:22.04#ibcon#about to read 6, iclass 17, count 2 2006.201.04:29:22.04#ibcon#read 6, iclass 17, count 2 2006.201.04:29:22.04#ibcon#end of sib2, iclass 17, count 2 2006.201.04:29:22.04#ibcon#*mode == 0, iclass 17, count 2 2006.201.04:29:22.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.04:29:22.04#ibcon#[27=AT06-04\r\n] 2006.201.04:29:22.04#ibcon#*before write, iclass 17, count 2 2006.201.04:29:22.04#ibcon#enter sib2, iclass 17, count 2 2006.201.04:29:22.04#ibcon#flushed, iclass 17, count 2 2006.201.04:29:22.04#ibcon#about to write, iclass 17, count 2 2006.201.04:29:22.04#ibcon#wrote, iclass 17, count 2 2006.201.04:29:22.04#ibcon#about to read 3, iclass 17, count 2 2006.201.04:29:22.07#ibcon#read 3, iclass 17, count 2 2006.201.04:29:22.07#ibcon#about to read 4, iclass 17, count 2 2006.201.04:29:22.07#ibcon#read 4, iclass 17, count 2 2006.201.04:29:22.07#ibcon#about to read 5, iclass 17, count 2 2006.201.04:29:22.07#ibcon#read 5, iclass 17, count 2 2006.201.04:29:22.07#ibcon#about to read 6, iclass 17, count 2 2006.201.04:29:22.07#ibcon#read 6, iclass 17, count 2 2006.201.04:29:22.07#ibcon#end of sib2, iclass 17, count 2 2006.201.04:29:22.07#ibcon#*after write, iclass 17, count 2 2006.201.04:29:22.07#ibcon#*before return 0, iclass 17, count 2 2006.201.04:29:22.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:22.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:29:22.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.04:29:22.07#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:22.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:22.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:22.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:22.19#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:29:22.19#ibcon#first serial, iclass 17, count 0 2006.201.04:29:22.19#ibcon#enter sib2, iclass 17, count 0 2006.201.04:29:22.19#ibcon#flushed, iclass 17, count 0 2006.201.04:29:22.19#ibcon#about to write, iclass 17, count 0 2006.201.04:29:22.19#ibcon#wrote, iclass 17, count 0 2006.201.04:29:22.19#ibcon#about to read 3, iclass 17, count 0 2006.201.04:29:22.21#ibcon#read 3, iclass 17, count 0 2006.201.04:29:22.21#ibcon#about to read 4, iclass 17, count 0 2006.201.04:29:22.21#ibcon#read 4, iclass 17, count 0 2006.201.04:29:22.21#ibcon#about to read 5, iclass 17, count 0 2006.201.04:29:22.21#ibcon#read 5, iclass 17, count 0 2006.201.04:29:22.21#ibcon#about to read 6, iclass 17, count 0 2006.201.04:29:22.21#ibcon#read 6, iclass 17, count 0 2006.201.04:29:22.21#ibcon#end of sib2, iclass 17, count 0 2006.201.04:29:22.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:29:22.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:29:22.21#ibcon#[27=USB\r\n] 2006.201.04:29:22.21#ibcon#*before write, iclass 17, count 0 2006.201.04:29:22.21#ibcon#enter sib2, iclass 17, count 0 2006.201.04:29:22.21#ibcon#flushed, iclass 17, count 0 2006.201.04:29:22.21#ibcon#about to write, iclass 17, count 0 2006.201.04:29:22.21#ibcon#wrote, iclass 17, count 0 2006.201.04:29:22.21#ibcon#about to read 3, iclass 17, count 0 2006.201.04:29:22.24#ibcon#read 3, iclass 17, count 0 2006.201.04:29:22.24#ibcon#about to read 4, iclass 17, count 0 2006.201.04:29:22.24#ibcon#read 4, iclass 17, count 0 2006.201.04:29:22.24#ibcon#about to read 5, iclass 17, count 0 2006.201.04:29:22.24#ibcon#read 5, iclass 17, count 0 2006.201.04:29:22.24#ibcon#about to read 6, iclass 17, count 0 2006.201.04:29:22.24#ibcon#read 6, iclass 17, count 0 2006.201.04:29:22.24#ibcon#end of sib2, iclass 17, count 0 2006.201.04:29:22.24#ibcon#*after write, iclass 17, count 0 2006.201.04:29:22.24#ibcon#*before return 0, iclass 17, count 0 2006.201.04:29:22.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:22.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:29:22.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:29:22.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:29:22.24$vck44/vblo=7,734.99 2006.201.04:29:22.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.04:29:22.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.04:29:22.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:22.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:22.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:22.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:22.24#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:29:22.24#ibcon#first serial, iclass 19, count 0 2006.201.04:29:22.24#ibcon#enter sib2, iclass 19, count 0 2006.201.04:29:22.24#ibcon#flushed, iclass 19, count 0 2006.201.04:29:22.24#ibcon#about to write, iclass 19, count 0 2006.201.04:29:22.24#ibcon#wrote, iclass 19, count 0 2006.201.04:29:22.24#ibcon#about to read 3, iclass 19, count 0 2006.201.04:29:22.26#ibcon#read 3, iclass 19, count 0 2006.201.04:29:22.26#ibcon#about to read 4, iclass 19, count 0 2006.201.04:29:22.26#ibcon#read 4, iclass 19, count 0 2006.201.04:29:22.26#ibcon#about to read 5, iclass 19, count 0 2006.201.04:29:22.26#ibcon#read 5, iclass 19, count 0 2006.201.04:29:22.26#ibcon#about to read 6, iclass 19, count 0 2006.201.04:29:22.26#ibcon#read 6, iclass 19, count 0 2006.201.04:29:22.26#ibcon#end of sib2, iclass 19, count 0 2006.201.04:29:22.26#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:29:22.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:29:22.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:29:22.26#ibcon#*before write, iclass 19, count 0 2006.201.04:29:22.26#ibcon#enter sib2, iclass 19, count 0 2006.201.04:29:22.26#ibcon#flushed, iclass 19, count 0 2006.201.04:29:22.26#ibcon#about to write, iclass 19, count 0 2006.201.04:29:22.26#ibcon#wrote, iclass 19, count 0 2006.201.04:29:22.26#ibcon#about to read 3, iclass 19, count 0 2006.201.04:29:22.30#ibcon#read 3, iclass 19, count 0 2006.201.04:29:22.30#ibcon#about to read 4, iclass 19, count 0 2006.201.04:29:22.30#ibcon#read 4, iclass 19, count 0 2006.201.04:29:22.30#ibcon#about to read 5, iclass 19, count 0 2006.201.04:29:22.30#ibcon#read 5, iclass 19, count 0 2006.201.04:29:22.30#ibcon#about to read 6, iclass 19, count 0 2006.201.04:29:22.30#ibcon#read 6, iclass 19, count 0 2006.201.04:29:22.30#ibcon#end of sib2, iclass 19, count 0 2006.201.04:29:22.30#ibcon#*after write, iclass 19, count 0 2006.201.04:29:22.30#ibcon#*before return 0, iclass 19, count 0 2006.201.04:29:22.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:22.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:29:22.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:29:22.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:29:22.30$vck44/vb=7,4 2006.201.04:29:22.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.04:29:22.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.04:29:22.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:22.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:22.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:22.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:22.36#ibcon#enter wrdev, iclass 21, count 2 2006.201.04:29:22.36#ibcon#first serial, iclass 21, count 2 2006.201.04:29:22.36#ibcon#enter sib2, iclass 21, count 2 2006.201.04:29:22.36#ibcon#flushed, iclass 21, count 2 2006.201.04:29:22.36#ibcon#about to write, iclass 21, count 2 2006.201.04:29:22.36#ibcon#wrote, iclass 21, count 2 2006.201.04:29:22.36#ibcon#about to read 3, iclass 21, count 2 2006.201.04:29:22.38#ibcon#read 3, iclass 21, count 2 2006.201.04:29:22.38#ibcon#about to read 4, iclass 21, count 2 2006.201.04:29:22.38#ibcon#read 4, iclass 21, count 2 2006.201.04:29:22.38#ibcon#about to read 5, iclass 21, count 2 2006.201.04:29:22.38#ibcon#read 5, iclass 21, count 2 2006.201.04:29:22.38#ibcon#about to read 6, iclass 21, count 2 2006.201.04:29:22.38#ibcon#read 6, iclass 21, count 2 2006.201.04:29:22.38#ibcon#end of sib2, iclass 21, count 2 2006.201.04:29:22.38#ibcon#*mode == 0, iclass 21, count 2 2006.201.04:29:22.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.04:29:22.38#ibcon#[27=AT07-04\r\n] 2006.201.04:29:22.38#ibcon#*before write, iclass 21, count 2 2006.201.04:29:22.38#ibcon#enter sib2, iclass 21, count 2 2006.201.04:29:22.38#ibcon#flushed, iclass 21, count 2 2006.201.04:29:22.38#ibcon#about to write, iclass 21, count 2 2006.201.04:29:22.38#ibcon#wrote, iclass 21, count 2 2006.201.04:29:22.38#ibcon#about to read 3, iclass 21, count 2 2006.201.04:29:22.41#ibcon#read 3, iclass 21, count 2 2006.201.04:29:22.41#ibcon#about to read 4, iclass 21, count 2 2006.201.04:29:22.41#ibcon#read 4, iclass 21, count 2 2006.201.04:29:22.41#ibcon#about to read 5, iclass 21, count 2 2006.201.04:29:22.41#ibcon#read 5, iclass 21, count 2 2006.201.04:29:22.41#ibcon#about to read 6, iclass 21, count 2 2006.201.04:29:22.41#ibcon#read 6, iclass 21, count 2 2006.201.04:29:22.41#ibcon#end of sib2, iclass 21, count 2 2006.201.04:29:22.41#ibcon#*after write, iclass 21, count 2 2006.201.04:29:22.41#ibcon#*before return 0, iclass 21, count 2 2006.201.04:29:22.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:22.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:29:22.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.04:29:22.41#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:22.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:22.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:22.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:22.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:29:22.53#ibcon#first serial, iclass 21, count 0 2006.201.04:29:22.53#ibcon#enter sib2, iclass 21, count 0 2006.201.04:29:22.53#ibcon#flushed, iclass 21, count 0 2006.201.04:29:22.53#ibcon#about to write, iclass 21, count 0 2006.201.04:29:22.53#ibcon#wrote, iclass 21, count 0 2006.201.04:29:22.53#ibcon#about to read 3, iclass 21, count 0 2006.201.04:29:22.55#ibcon#read 3, iclass 21, count 0 2006.201.04:29:22.55#ibcon#about to read 4, iclass 21, count 0 2006.201.04:29:22.55#ibcon#read 4, iclass 21, count 0 2006.201.04:29:22.55#ibcon#about to read 5, iclass 21, count 0 2006.201.04:29:22.55#ibcon#read 5, iclass 21, count 0 2006.201.04:29:22.55#ibcon#about to read 6, iclass 21, count 0 2006.201.04:29:22.55#ibcon#read 6, iclass 21, count 0 2006.201.04:29:22.55#ibcon#end of sib2, iclass 21, count 0 2006.201.04:29:22.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:29:22.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:29:22.55#ibcon#[27=USB\r\n] 2006.201.04:29:22.55#ibcon#*before write, iclass 21, count 0 2006.201.04:29:22.55#ibcon#enter sib2, iclass 21, count 0 2006.201.04:29:22.55#ibcon#flushed, iclass 21, count 0 2006.201.04:29:22.55#ibcon#about to write, iclass 21, count 0 2006.201.04:29:22.55#ibcon#wrote, iclass 21, count 0 2006.201.04:29:22.55#ibcon#about to read 3, iclass 21, count 0 2006.201.04:29:22.58#ibcon#read 3, iclass 21, count 0 2006.201.04:29:22.58#ibcon#about to read 4, iclass 21, count 0 2006.201.04:29:22.58#ibcon#read 4, iclass 21, count 0 2006.201.04:29:22.58#ibcon#about to read 5, iclass 21, count 0 2006.201.04:29:22.58#ibcon#read 5, iclass 21, count 0 2006.201.04:29:22.58#ibcon#about to read 6, iclass 21, count 0 2006.201.04:29:22.58#ibcon#read 6, iclass 21, count 0 2006.201.04:29:22.58#ibcon#end of sib2, iclass 21, count 0 2006.201.04:29:22.58#ibcon#*after write, iclass 21, count 0 2006.201.04:29:22.58#ibcon#*before return 0, iclass 21, count 0 2006.201.04:29:22.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:22.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:29:22.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:29:22.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:29:22.58$vck44/vblo=8,744.99 2006.201.04:29:22.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.04:29:22.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.04:29:22.58#ibcon#ireg 17 cls_cnt 0 2006.201.04:29:22.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:22.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:22.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:22.58#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:29:22.58#ibcon#first serial, iclass 23, count 0 2006.201.04:29:22.58#ibcon#enter sib2, iclass 23, count 0 2006.201.04:29:22.58#ibcon#flushed, iclass 23, count 0 2006.201.04:29:22.58#ibcon#about to write, iclass 23, count 0 2006.201.04:29:22.58#ibcon#wrote, iclass 23, count 0 2006.201.04:29:22.58#ibcon#about to read 3, iclass 23, count 0 2006.201.04:29:22.60#ibcon#read 3, iclass 23, count 0 2006.201.04:29:22.60#ibcon#about to read 4, iclass 23, count 0 2006.201.04:29:22.60#ibcon#read 4, iclass 23, count 0 2006.201.04:29:22.60#ibcon#about to read 5, iclass 23, count 0 2006.201.04:29:22.60#ibcon#read 5, iclass 23, count 0 2006.201.04:29:22.60#ibcon#about to read 6, iclass 23, count 0 2006.201.04:29:22.60#ibcon#read 6, iclass 23, count 0 2006.201.04:29:22.60#ibcon#end of sib2, iclass 23, count 0 2006.201.04:29:22.60#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:29:22.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:29:22.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:29:22.60#ibcon#*before write, iclass 23, count 0 2006.201.04:29:22.60#ibcon#enter sib2, iclass 23, count 0 2006.201.04:29:22.60#ibcon#flushed, iclass 23, count 0 2006.201.04:29:22.60#ibcon#about to write, iclass 23, count 0 2006.201.04:29:22.60#ibcon#wrote, iclass 23, count 0 2006.201.04:29:22.60#ibcon#about to read 3, iclass 23, count 0 2006.201.04:29:22.64#ibcon#read 3, iclass 23, count 0 2006.201.04:29:22.64#ibcon#about to read 4, iclass 23, count 0 2006.201.04:29:22.64#ibcon#read 4, iclass 23, count 0 2006.201.04:29:22.64#ibcon#about to read 5, iclass 23, count 0 2006.201.04:29:22.64#ibcon#read 5, iclass 23, count 0 2006.201.04:29:22.64#ibcon#about to read 6, iclass 23, count 0 2006.201.04:29:22.64#ibcon#read 6, iclass 23, count 0 2006.201.04:29:22.64#ibcon#end of sib2, iclass 23, count 0 2006.201.04:29:22.64#ibcon#*after write, iclass 23, count 0 2006.201.04:29:22.64#ibcon#*before return 0, iclass 23, count 0 2006.201.04:29:22.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:22.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:29:22.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:29:22.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:29:22.64$vck44/vb=8,4 2006.201.04:29:22.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.04:29:22.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.04:29:22.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:29:22.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:22.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:22.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:22.70#ibcon#enter wrdev, iclass 25, count 2 2006.201.04:29:22.70#ibcon#first serial, iclass 25, count 2 2006.201.04:29:22.70#ibcon#enter sib2, iclass 25, count 2 2006.201.04:29:22.70#ibcon#flushed, iclass 25, count 2 2006.201.04:29:22.70#ibcon#about to write, iclass 25, count 2 2006.201.04:29:22.70#ibcon#wrote, iclass 25, count 2 2006.201.04:29:22.70#ibcon#about to read 3, iclass 25, count 2 2006.201.04:29:22.72#ibcon#read 3, iclass 25, count 2 2006.201.04:29:22.72#ibcon#about to read 4, iclass 25, count 2 2006.201.04:29:22.72#ibcon#read 4, iclass 25, count 2 2006.201.04:29:22.72#ibcon#about to read 5, iclass 25, count 2 2006.201.04:29:22.72#ibcon#read 5, iclass 25, count 2 2006.201.04:29:22.72#ibcon#about to read 6, iclass 25, count 2 2006.201.04:29:22.72#ibcon#read 6, iclass 25, count 2 2006.201.04:29:22.72#ibcon#end of sib2, iclass 25, count 2 2006.201.04:29:22.72#ibcon#*mode == 0, iclass 25, count 2 2006.201.04:29:22.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.04:29:22.72#ibcon#[27=AT08-04\r\n] 2006.201.04:29:22.72#ibcon#*before write, iclass 25, count 2 2006.201.04:29:22.72#ibcon#enter sib2, iclass 25, count 2 2006.201.04:29:22.72#ibcon#flushed, iclass 25, count 2 2006.201.04:29:22.72#ibcon#about to write, iclass 25, count 2 2006.201.04:29:22.72#ibcon#wrote, iclass 25, count 2 2006.201.04:29:22.72#ibcon#about to read 3, iclass 25, count 2 2006.201.04:29:22.75#ibcon#read 3, iclass 25, count 2 2006.201.04:29:22.75#ibcon#about to read 4, iclass 25, count 2 2006.201.04:29:22.75#ibcon#read 4, iclass 25, count 2 2006.201.04:29:22.75#ibcon#about to read 5, iclass 25, count 2 2006.201.04:29:22.75#ibcon#read 5, iclass 25, count 2 2006.201.04:29:22.75#ibcon#about to read 6, iclass 25, count 2 2006.201.04:29:22.75#ibcon#read 6, iclass 25, count 2 2006.201.04:29:22.75#ibcon#end of sib2, iclass 25, count 2 2006.201.04:29:22.75#ibcon#*after write, iclass 25, count 2 2006.201.04:29:22.75#ibcon#*before return 0, iclass 25, count 2 2006.201.04:29:22.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:22.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:29:22.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.04:29:22.75#ibcon#ireg 7 cls_cnt 0 2006.201.04:29:22.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:22.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:22.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:22.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:29:22.87#ibcon#first serial, iclass 25, count 0 2006.201.04:29:22.87#ibcon#enter sib2, iclass 25, count 0 2006.201.04:29:22.87#ibcon#flushed, iclass 25, count 0 2006.201.04:29:22.87#ibcon#about to write, iclass 25, count 0 2006.201.04:29:22.87#ibcon#wrote, iclass 25, count 0 2006.201.04:29:22.87#ibcon#about to read 3, iclass 25, count 0 2006.201.04:29:22.88#abcon#<5=/05 2.6 4.4 22.98 911004.1\r\n> 2006.201.04:29:22.89#ibcon#read 3, iclass 25, count 0 2006.201.04:29:22.89#ibcon#about to read 4, iclass 25, count 0 2006.201.04:29:22.89#ibcon#read 4, iclass 25, count 0 2006.201.04:29:22.89#ibcon#about to read 5, iclass 25, count 0 2006.201.04:29:22.89#ibcon#read 5, iclass 25, count 0 2006.201.04:29:22.89#ibcon#about to read 6, iclass 25, count 0 2006.201.04:29:22.89#ibcon#read 6, iclass 25, count 0 2006.201.04:29:22.89#ibcon#end of sib2, iclass 25, count 0 2006.201.04:29:22.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:29:22.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:29:22.89#ibcon#[27=USB\r\n] 2006.201.04:29:22.89#ibcon#*before write, iclass 25, count 0 2006.201.04:29:22.89#ibcon#enter sib2, iclass 25, count 0 2006.201.04:29:22.89#ibcon#flushed, iclass 25, count 0 2006.201.04:29:22.89#ibcon#about to write, iclass 25, count 0 2006.201.04:29:22.89#ibcon#wrote, iclass 25, count 0 2006.201.04:29:22.89#ibcon#about to read 3, iclass 25, count 0 2006.201.04:29:22.90#abcon#{5=INTERFACE CLEAR} 2006.201.04:29:22.92#ibcon#read 3, iclass 25, count 0 2006.201.04:29:22.92#ibcon#about to read 4, iclass 25, count 0 2006.201.04:29:22.92#ibcon#read 4, iclass 25, count 0 2006.201.04:29:22.92#ibcon#about to read 5, iclass 25, count 0 2006.201.04:29:22.92#ibcon#read 5, iclass 25, count 0 2006.201.04:29:22.92#ibcon#about to read 6, iclass 25, count 0 2006.201.04:29:22.92#ibcon#read 6, iclass 25, count 0 2006.201.04:29:22.92#ibcon#end of sib2, iclass 25, count 0 2006.201.04:29:22.92#ibcon#*after write, iclass 25, count 0 2006.201.04:29:22.92#ibcon#*before return 0, iclass 25, count 0 2006.201.04:29:22.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:22.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:29:22.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:29:22.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:29:22.92$vck44/vabw=wide 2006.201.04:29:22.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.04:29:22.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.04:29:22.92#ibcon#ireg 8 cls_cnt 0 2006.201.04:29:22.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:29:22.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:29:22.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:29:22.92#ibcon#enter wrdev, iclass 30, count 0 2006.201.04:29:22.92#ibcon#first serial, iclass 30, count 0 2006.201.04:29:22.92#ibcon#enter sib2, iclass 30, count 0 2006.201.04:29:22.92#ibcon#flushed, iclass 30, count 0 2006.201.04:29:22.92#ibcon#about to write, iclass 30, count 0 2006.201.04:29:22.92#ibcon#wrote, iclass 30, count 0 2006.201.04:29:22.92#ibcon#about to read 3, iclass 30, count 0 2006.201.04:29:22.94#ibcon#read 3, iclass 30, count 0 2006.201.04:29:22.94#ibcon#about to read 4, iclass 30, count 0 2006.201.04:29:22.94#ibcon#read 4, iclass 30, count 0 2006.201.04:29:22.94#ibcon#about to read 5, iclass 30, count 0 2006.201.04:29:22.94#ibcon#read 5, iclass 30, count 0 2006.201.04:29:22.94#ibcon#about to read 6, iclass 30, count 0 2006.201.04:29:22.94#ibcon#read 6, iclass 30, count 0 2006.201.04:29:22.94#ibcon#end of sib2, iclass 30, count 0 2006.201.04:29:22.94#ibcon#*mode == 0, iclass 30, count 0 2006.201.04:29:22.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.04:29:22.94#ibcon#[25=BW32\r\n] 2006.201.04:29:22.94#ibcon#*before write, iclass 30, count 0 2006.201.04:29:22.94#ibcon#enter sib2, iclass 30, count 0 2006.201.04:29:22.94#ibcon#flushed, iclass 30, count 0 2006.201.04:29:22.94#ibcon#about to write, iclass 30, count 0 2006.201.04:29:22.94#ibcon#wrote, iclass 30, count 0 2006.201.04:29:22.94#ibcon#about to read 3, iclass 30, count 0 2006.201.04:29:22.96#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:29:22.97#ibcon#read 3, iclass 30, count 0 2006.201.04:29:22.97#ibcon#about to read 4, iclass 30, count 0 2006.201.04:29:22.97#ibcon#read 4, iclass 30, count 0 2006.201.04:29:22.97#ibcon#about to read 5, iclass 30, count 0 2006.201.04:29:22.97#ibcon#read 5, iclass 30, count 0 2006.201.04:29:22.97#ibcon#about to read 6, iclass 30, count 0 2006.201.04:29:22.97#ibcon#read 6, iclass 30, count 0 2006.201.04:29:22.97#ibcon#end of sib2, iclass 30, count 0 2006.201.04:29:22.97#ibcon#*after write, iclass 30, count 0 2006.201.04:29:22.97#ibcon#*before return 0, iclass 30, count 0 2006.201.04:29:22.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:29:22.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:29:22.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.04:29:22.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.04:29:22.97$vck44/vbbw=wide 2006.201.04:29:22.97#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.04:29:22.97#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.04:29:22.97#ibcon#ireg 8 cls_cnt 0 2006.201.04:29:22.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:29:23.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:29:23.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:29:23.04#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:29:23.04#ibcon#first serial, iclass 33, count 0 2006.201.04:29:23.04#ibcon#enter sib2, iclass 33, count 0 2006.201.04:29:23.04#ibcon#flushed, iclass 33, count 0 2006.201.04:29:23.04#ibcon#about to write, iclass 33, count 0 2006.201.04:29:23.04#ibcon#wrote, iclass 33, count 0 2006.201.04:29:23.04#ibcon#about to read 3, iclass 33, count 0 2006.201.04:29:23.06#ibcon#read 3, iclass 33, count 0 2006.201.04:29:23.06#ibcon#about to read 4, iclass 33, count 0 2006.201.04:29:23.06#ibcon#read 4, iclass 33, count 0 2006.201.04:29:23.06#ibcon#about to read 5, iclass 33, count 0 2006.201.04:29:23.06#ibcon#read 5, iclass 33, count 0 2006.201.04:29:23.06#ibcon#about to read 6, iclass 33, count 0 2006.201.04:29:23.06#ibcon#read 6, iclass 33, count 0 2006.201.04:29:23.06#ibcon#end of sib2, iclass 33, count 0 2006.201.04:29:23.06#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:29:23.06#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:29:23.06#ibcon#[27=BW32\r\n] 2006.201.04:29:23.06#ibcon#*before write, iclass 33, count 0 2006.201.04:29:23.06#ibcon#enter sib2, iclass 33, count 0 2006.201.04:29:23.06#ibcon#flushed, iclass 33, count 0 2006.201.04:29:23.06#ibcon#about to write, iclass 33, count 0 2006.201.04:29:23.06#ibcon#wrote, iclass 33, count 0 2006.201.04:29:23.06#ibcon#about to read 3, iclass 33, count 0 2006.201.04:29:23.09#ibcon#read 3, iclass 33, count 0 2006.201.04:29:23.09#ibcon#about to read 4, iclass 33, count 0 2006.201.04:29:23.09#ibcon#read 4, iclass 33, count 0 2006.201.04:29:23.09#ibcon#about to read 5, iclass 33, count 0 2006.201.04:29:23.09#ibcon#read 5, iclass 33, count 0 2006.201.04:29:23.09#ibcon#about to read 6, iclass 33, count 0 2006.201.04:29:23.09#ibcon#read 6, iclass 33, count 0 2006.201.04:29:23.09#ibcon#end of sib2, iclass 33, count 0 2006.201.04:29:23.09#ibcon#*after write, iclass 33, count 0 2006.201.04:29:23.09#ibcon#*before return 0, iclass 33, count 0 2006.201.04:29:23.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:29:23.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:29:23.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:29:23.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:29:23.09$setupk4/ifdk4 2006.201.04:29:23.09$ifdk4/lo= 2006.201.04:29:23.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:29:23.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:29:23.09$ifdk4/patch= 2006.201.04:29:23.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:29:23.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:29:23.09$setupk4/!*+20s 2006.201.04:29:33.05#abcon#<5=/05 2.6 4.4 22.98 911004.1\r\n> 2006.201.04:29:33.07#abcon#{5=INTERFACE CLEAR} 2006.201.04:29:33.13#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:29:37.60$setupk4/"tpicd 2006.201.04:29:37.60$setupk4/echo=off 2006.201.04:29:37.60$setupk4/xlog=off 2006.201.04:29:37.60:!2006.201.04:33:15 2006.201.04:29:40.13#trakl#Source acquired 2006.201.04:29:40.13#flagr#flagr/antenna,acquired 2006.201.04:33:15.00:preob 2006.201.04:33:15.14/onsource/TRACKING 2006.201.04:33:15.14:!2006.201.04:33:25 2006.201.04:33:25.00:"tape 2006.201.04:33:25.00:"st=record 2006.201.04:33:25.00:data_valid=on 2006.201.04:33:25.00:midob 2006.201.04:33:25.14/onsource/TRACKING 2006.201.04:33:25.14/wx/22.98,1004.0,91 2006.201.04:33:25.23/cable/+6.4643E-03 2006.201.04:33:26.32/va/01,08,usb,yes,32,34 2006.201.04:33:26.32/va/02,07,usb,yes,35,35 2006.201.04:33:26.32/va/03,08,usb,yes,31,33 2006.201.04:33:26.32/va/04,07,usb,yes,36,38 2006.201.04:33:26.32/va/05,04,usb,yes,32,32 2006.201.04:33:26.32/va/06,05,usb,yes,32,32 2006.201.04:33:26.32/va/07,05,usb,yes,31,32 2006.201.04:33:26.32/va/08,04,usb,yes,30,37 2006.201.04:33:26.55/valo/01,524.99,yes,locked 2006.201.04:33:26.55/valo/02,534.99,yes,locked 2006.201.04:33:26.55/valo/03,564.99,yes,locked 2006.201.04:33:26.55/valo/04,624.99,yes,locked 2006.201.04:33:26.55/valo/05,734.99,yes,locked 2006.201.04:33:26.55/valo/06,814.99,yes,locked 2006.201.04:33:26.55/valo/07,864.99,yes,locked 2006.201.04:33:26.55/valo/08,884.99,yes,locked 2006.201.04:33:27.64/vb/01,04,usb,yes,31,28 2006.201.04:33:27.64/vb/02,05,usb,yes,29,29 2006.201.04:33:27.64/vb/03,04,usb,yes,30,33 2006.201.04:33:27.64/vb/04,05,usb,yes,30,29 2006.201.04:33:27.64/vb/05,04,usb,yes,27,29 2006.201.04:33:27.64/vb/06,04,usb,yes,32,28 2006.201.04:33:27.64/vb/07,04,usb,yes,31,31 2006.201.04:33:27.64/vb/08,04,usb,yes,29,32 2006.201.04:33:27.87/vblo/01,629.99,yes,locked 2006.201.04:33:27.87/vblo/02,634.99,yes,locked 2006.201.04:33:27.87/vblo/03,649.99,yes,locked 2006.201.04:33:27.87/vblo/04,679.99,yes,locked 2006.201.04:33:27.87/vblo/05,709.99,yes,locked 2006.201.04:33:27.87/vblo/06,719.99,yes,locked 2006.201.04:33:27.87/vblo/07,734.99,yes,locked 2006.201.04:33:27.87/vblo/08,744.99,yes,locked 2006.201.04:33:28.02/vabw/8 2006.201.04:33:28.17/vbbw/8 2006.201.04:33:28.26/xfe/off,on,15.0 2006.201.04:33:28.63/ifatt/23,28,28,28 2006.201.04:33:29.04/fmout-gps/S +4.56E-07 2006.201.04:33:29.07:!2006.201.04:34:55 2006.201.04:34:55.00:data_valid=off 2006.201.04:34:55.00:"et 2006.201.04:34:55.00:!+3s 2006.201.04:34:58.01:"tape 2006.201.04:34:58.01:postob 2006.201.04:34:58.07/cable/+6.4632E-03 2006.201.04:34:58.07/wx/22.99,1003.9,91 2006.201.04:34:58.13/fmout-gps/S +4.55E-07 2006.201.04:34:58.13:scan_name=201-0435,jd0607,370 2006.201.04:34:58.13:source=1308+326,131028.66,322043.8,2000.0,cw 2006.201.04:34:59.14#flagr#flagr/antenna,new-source 2006.201.04:34:59.14:checkk5 2006.201.04:34:59.49/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:34:59.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:35:00.31/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:35:00.71/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:35:01.11/chk_obsdata//k5ts1/T2010433??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.04:35:01.50/chk_obsdata//k5ts2/T2010433??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.04:35:01.91/chk_obsdata//k5ts3/T2010433??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.04:35:02.31/chk_obsdata//k5ts4/T2010433??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.04:35:03.05/k5log//k5ts1_log_newline 2006.201.04:35:03.77/k5log//k5ts2_log_newline 2006.201.04:35:04.48/k5log//k5ts3_log_newline 2006.201.04:35:05.20/k5log//k5ts4_log_newline 2006.201.04:35:05.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:35:05.22:setupk4=1 2006.201.04:35:05.22$setupk4/echo=on 2006.201.04:35:05.22$setupk4/pcalon 2006.201.04:35:05.22$pcalon/"no phase cal control is implemented here 2006.201.04:35:05.22$setupk4/"tpicd=stop 2006.201.04:35:05.22$setupk4/"rec=synch_on 2006.201.04:35:05.22$setupk4/"rec_mode=128 2006.201.04:35:05.22$setupk4/!* 2006.201.04:35:05.22$setupk4/recpk4 2006.201.04:35:05.22$recpk4/recpatch= 2006.201.04:35:05.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:35:05.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:35:05.23$setupk4/vck44 2006.201.04:35:05.23$vck44/valo=1,524.99 2006.201.04:35:05.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.04:35:05.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.04:35:05.23#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:05.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:05.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:05.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:05.23#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:35:05.23#ibcon#first serial, iclass 21, count 0 2006.201.04:35:05.23#ibcon#enter sib2, iclass 21, count 0 2006.201.04:35:05.23#ibcon#flushed, iclass 21, count 0 2006.201.04:35:05.23#ibcon#about to write, iclass 21, count 0 2006.201.04:35:05.23#ibcon#wrote, iclass 21, count 0 2006.201.04:35:05.23#ibcon#about to read 3, iclass 21, count 0 2006.201.04:35:05.25#ibcon#read 3, iclass 21, count 0 2006.201.04:35:05.25#ibcon#about to read 4, iclass 21, count 0 2006.201.04:35:05.25#ibcon#read 4, iclass 21, count 0 2006.201.04:35:05.25#ibcon#about to read 5, iclass 21, count 0 2006.201.04:35:05.25#ibcon#read 5, iclass 21, count 0 2006.201.04:35:05.25#ibcon#about to read 6, iclass 21, count 0 2006.201.04:35:05.25#ibcon#read 6, iclass 21, count 0 2006.201.04:35:05.25#ibcon#end of sib2, iclass 21, count 0 2006.201.04:35:05.25#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:35:05.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:35:05.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:35:05.25#ibcon#*before write, iclass 21, count 0 2006.201.04:35:05.25#ibcon#enter sib2, iclass 21, count 0 2006.201.04:35:05.25#ibcon#flushed, iclass 21, count 0 2006.201.04:35:05.25#ibcon#about to write, iclass 21, count 0 2006.201.04:35:05.25#ibcon#wrote, iclass 21, count 0 2006.201.04:35:05.25#ibcon#about to read 3, iclass 21, count 0 2006.201.04:35:05.30#ibcon#read 3, iclass 21, count 0 2006.201.04:35:05.30#ibcon#about to read 4, iclass 21, count 0 2006.201.04:35:05.30#ibcon#read 4, iclass 21, count 0 2006.201.04:35:05.30#ibcon#about to read 5, iclass 21, count 0 2006.201.04:35:05.30#ibcon#read 5, iclass 21, count 0 2006.201.04:35:05.30#ibcon#about to read 6, iclass 21, count 0 2006.201.04:35:05.30#ibcon#read 6, iclass 21, count 0 2006.201.04:35:05.30#ibcon#end of sib2, iclass 21, count 0 2006.201.04:35:05.30#ibcon#*after write, iclass 21, count 0 2006.201.04:35:05.30#ibcon#*before return 0, iclass 21, count 0 2006.201.04:35:05.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:05.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:05.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:35:05.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:35:05.30$vck44/va=1,8 2006.201.04:35:05.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.04:35:05.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.04:35:05.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:05.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:05.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:05.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:05.30#ibcon#enter wrdev, iclass 23, count 2 2006.201.04:35:05.30#ibcon#first serial, iclass 23, count 2 2006.201.04:35:05.30#ibcon#enter sib2, iclass 23, count 2 2006.201.04:35:05.30#ibcon#flushed, iclass 23, count 2 2006.201.04:35:05.30#ibcon#about to write, iclass 23, count 2 2006.201.04:35:05.30#ibcon#wrote, iclass 23, count 2 2006.201.04:35:05.30#ibcon#about to read 3, iclass 23, count 2 2006.201.04:35:05.32#ibcon#read 3, iclass 23, count 2 2006.201.04:35:05.32#ibcon#about to read 4, iclass 23, count 2 2006.201.04:35:05.32#ibcon#read 4, iclass 23, count 2 2006.201.04:35:05.32#ibcon#about to read 5, iclass 23, count 2 2006.201.04:35:05.32#ibcon#read 5, iclass 23, count 2 2006.201.04:35:05.32#ibcon#about to read 6, iclass 23, count 2 2006.201.04:35:05.32#ibcon#read 6, iclass 23, count 2 2006.201.04:35:05.32#ibcon#end of sib2, iclass 23, count 2 2006.201.04:35:05.32#ibcon#*mode == 0, iclass 23, count 2 2006.201.04:35:05.32#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.04:35:05.32#ibcon#[25=AT01-08\r\n] 2006.201.04:35:05.32#ibcon#*before write, iclass 23, count 2 2006.201.04:35:05.32#ibcon#enter sib2, iclass 23, count 2 2006.201.04:35:05.32#ibcon#flushed, iclass 23, count 2 2006.201.04:35:05.32#ibcon#about to write, iclass 23, count 2 2006.201.04:35:05.32#ibcon#wrote, iclass 23, count 2 2006.201.04:35:05.32#ibcon#about to read 3, iclass 23, count 2 2006.201.04:35:05.35#ibcon#read 3, iclass 23, count 2 2006.201.04:35:05.35#ibcon#about to read 4, iclass 23, count 2 2006.201.04:35:05.35#ibcon#read 4, iclass 23, count 2 2006.201.04:35:05.35#ibcon#about to read 5, iclass 23, count 2 2006.201.04:35:05.35#ibcon#read 5, iclass 23, count 2 2006.201.04:35:05.35#ibcon#about to read 6, iclass 23, count 2 2006.201.04:35:05.35#ibcon#read 6, iclass 23, count 2 2006.201.04:35:05.35#ibcon#end of sib2, iclass 23, count 2 2006.201.04:35:05.35#ibcon#*after write, iclass 23, count 2 2006.201.04:35:05.35#ibcon#*before return 0, iclass 23, count 2 2006.201.04:35:05.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:05.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:05.35#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.04:35:05.35#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:05.35#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:05.47#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:05.47#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:05.47#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:35:05.47#ibcon#first serial, iclass 23, count 0 2006.201.04:35:05.47#ibcon#enter sib2, iclass 23, count 0 2006.201.04:35:05.47#ibcon#flushed, iclass 23, count 0 2006.201.04:35:05.47#ibcon#about to write, iclass 23, count 0 2006.201.04:35:05.47#ibcon#wrote, iclass 23, count 0 2006.201.04:35:05.47#ibcon#about to read 3, iclass 23, count 0 2006.201.04:35:05.49#ibcon#read 3, iclass 23, count 0 2006.201.04:35:05.49#ibcon#about to read 4, iclass 23, count 0 2006.201.04:35:05.49#ibcon#read 4, iclass 23, count 0 2006.201.04:35:05.49#ibcon#about to read 5, iclass 23, count 0 2006.201.04:35:05.49#ibcon#read 5, iclass 23, count 0 2006.201.04:35:05.49#ibcon#about to read 6, iclass 23, count 0 2006.201.04:35:05.49#ibcon#read 6, iclass 23, count 0 2006.201.04:35:05.49#ibcon#end of sib2, iclass 23, count 0 2006.201.04:35:05.49#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:35:05.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:35:05.49#ibcon#[25=USB\r\n] 2006.201.04:35:05.49#ibcon#*before write, iclass 23, count 0 2006.201.04:35:05.49#ibcon#enter sib2, iclass 23, count 0 2006.201.04:35:05.49#ibcon#flushed, iclass 23, count 0 2006.201.04:35:05.49#ibcon#about to write, iclass 23, count 0 2006.201.04:35:05.49#ibcon#wrote, iclass 23, count 0 2006.201.04:35:05.49#ibcon#about to read 3, iclass 23, count 0 2006.201.04:35:05.52#ibcon#read 3, iclass 23, count 0 2006.201.04:35:05.52#ibcon#about to read 4, iclass 23, count 0 2006.201.04:35:05.52#ibcon#read 4, iclass 23, count 0 2006.201.04:35:05.52#ibcon#about to read 5, iclass 23, count 0 2006.201.04:35:05.52#ibcon#read 5, iclass 23, count 0 2006.201.04:35:05.52#ibcon#about to read 6, iclass 23, count 0 2006.201.04:35:05.52#ibcon#read 6, iclass 23, count 0 2006.201.04:35:05.52#ibcon#end of sib2, iclass 23, count 0 2006.201.04:35:05.52#ibcon#*after write, iclass 23, count 0 2006.201.04:35:05.52#ibcon#*before return 0, iclass 23, count 0 2006.201.04:35:05.52#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:05.52#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:05.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:35:05.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:35:05.52$vck44/valo=2,534.99 2006.201.04:35:05.52#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.04:35:05.52#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.04:35:05.52#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:05.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:05.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:05.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:05.52#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:35:05.52#ibcon#first serial, iclass 25, count 0 2006.201.04:35:05.52#ibcon#enter sib2, iclass 25, count 0 2006.201.04:35:05.52#ibcon#flushed, iclass 25, count 0 2006.201.04:35:05.52#ibcon#about to write, iclass 25, count 0 2006.201.04:35:05.52#ibcon#wrote, iclass 25, count 0 2006.201.04:35:05.52#ibcon#about to read 3, iclass 25, count 0 2006.201.04:35:05.54#ibcon#read 3, iclass 25, count 0 2006.201.04:35:05.54#ibcon#about to read 4, iclass 25, count 0 2006.201.04:35:05.54#ibcon#read 4, iclass 25, count 0 2006.201.04:35:05.54#ibcon#about to read 5, iclass 25, count 0 2006.201.04:35:05.54#ibcon#read 5, iclass 25, count 0 2006.201.04:35:05.54#ibcon#about to read 6, iclass 25, count 0 2006.201.04:35:05.54#ibcon#read 6, iclass 25, count 0 2006.201.04:35:05.54#ibcon#end of sib2, iclass 25, count 0 2006.201.04:35:05.54#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:35:05.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:35:05.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:35:05.54#ibcon#*before write, iclass 25, count 0 2006.201.04:35:05.54#ibcon#enter sib2, iclass 25, count 0 2006.201.04:35:05.54#ibcon#flushed, iclass 25, count 0 2006.201.04:35:05.54#ibcon#about to write, iclass 25, count 0 2006.201.04:35:05.54#ibcon#wrote, iclass 25, count 0 2006.201.04:35:05.54#ibcon#about to read 3, iclass 25, count 0 2006.201.04:35:05.58#ibcon#read 3, iclass 25, count 0 2006.201.04:35:05.58#ibcon#about to read 4, iclass 25, count 0 2006.201.04:35:05.58#ibcon#read 4, iclass 25, count 0 2006.201.04:35:05.58#ibcon#about to read 5, iclass 25, count 0 2006.201.04:35:05.58#ibcon#read 5, iclass 25, count 0 2006.201.04:35:05.58#ibcon#about to read 6, iclass 25, count 0 2006.201.04:35:05.58#ibcon#read 6, iclass 25, count 0 2006.201.04:35:05.58#ibcon#end of sib2, iclass 25, count 0 2006.201.04:35:05.58#ibcon#*after write, iclass 25, count 0 2006.201.04:35:05.58#ibcon#*before return 0, iclass 25, count 0 2006.201.04:35:05.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:05.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:05.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:35:05.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:35:05.58$vck44/va=2,7 2006.201.04:35:05.58#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.04:35:05.58#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.04:35:05.58#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:05.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:05.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:05.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:05.64#ibcon#enter wrdev, iclass 27, count 2 2006.201.04:35:05.64#ibcon#first serial, iclass 27, count 2 2006.201.04:35:05.64#ibcon#enter sib2, iclass 27, count 2 2006.201.04:35:05.64#ibcon#flushed, iclass 27, count 2 2006.201.04:35:05.64#ibcon#about to write, iclass 27, count 2 2006.201.04:35:05.64#ibcon#wrote, iclass 27, count 2 2006.201.04:35:05.64#ibcon#about to read 3, iclass 27, count 2 2006.201.04:35:05.66#ibcon#read 3, iclass 27, count 2 2006.201.04:35:05.66#ibcon#about to read 4, iclass 27, count 2 2006.201.04:35:05.66#ibcon#read 4, iclass 27, count 2 2006.201.04:35:05.66#ibcon#about to read 5, iclass 27, count 2 2006.201.04:35:05.66#ibcon#read 5, iclass 27, count 2 2006.201.04:35:05.66#ibcon#about to read 6, iclass 27, count 2 2006.201.04:35:05.66#ibcon#read 6, iclass 27, count 2 2006.201.04:35:05.66#ibcon#end of sib2, iclass 27, count 2 2006.201.04:35:05.66#ibcon#*mode == 0, iclass 27, count 2 2006.201.04:35:05.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.04:35:05.66#ibcon#[25=AT02-07\r\n] 2006.201.04:35:05.66#ibcon#*before write, iclass 27, count 2 2006.201.04:35:05.66#ibcon#enter sib2, iclass 27, count 2 2006.201.04:35:05.66#ibcon#flushed, iclass 27, count 2 2006.201.04:35:05.66#ibcon#about to write, iclass 27, count 2 2006.201.04:35:05.66#ibcon#wrote, iclass 27, count 2 2006.201.04:35:05.66#ibcon#about to read 3, iclass 27, count 2 2006.201.04:35:05.69#ibcon#read 3, iclass 27, count 2 2006.201.04:35:05.69#ibcon#about to read 4, iclass 27, count 2 2006.201.04:35:05.69#ibcon#read 4, iclass 27, count 2 2006.201.04:35:05.69#ibcon#about to read 5, iclass 27, count 2 2006.201.04:35:05.69#ibcon#read 5, iclass 27, count 2 2006.201.04:35:05.69#ibcon#about to read 6, iclass 27, count 2 2006.201.04:35:05.69#ibcon#read 6, iclass 27, count 2 2006.201.04:35:05.69#ibcon#end of sib2, iclass 27, count 2 2006.201.04:35:05.69#ibcon#*after write, iclass 27, count 2 2006.201.04:35:05.69#ibcon#*before return 0, iclass 27, count 2 2006.201.04:35:05.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:05.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:05.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.04:35:05.69#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:05.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:05.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:05.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:05.81#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:35:05.81#ibcon#first serial, iclass 27, count 0 2006.201.04:35:05.81#ibcon#enter sib2, iclass 27, count 0 2006.201.04:35:05.81#ibcon#flushed, iclass 27, count 0 2006.201.04:35:05.81#ibcon#about to write, iclass 27, count 0 2006.201.04:35:05.81#ibcon#wrote, iclass 27, count 0 2006.201.04:35:05.81#ibcon#about to read 3, iclass 27, count 0 2006.201.04:35:05.83#ibcon#read 3, iclass 27, count 0 2006.201.04:35:05.83#ibcon#about to read 4, iclass 27, count 0 2006.201.04:35:05.83#ibcon#read 4, iclass 27, count 0 2006.201.04:35:05.83#ibcon#about to read 5, iclass 27, count 0 2006.201.04:35:05.83#ibcon#read 5, iclass 27, count 0 2006.201.04:35:05.83#ibcon#about to read 6, iclass 27, count 0 2006.201.04:35:05.83#ibcon#read 6, iclass 27, count 0 2006.201.04:35:05.83#ibcon#end of sib2, iclass 27, count 0 2006.201.04:35:05.83#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:35:05.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:35:05.83#ibcon#[25=USB\r\n] 2006.201.04:35:05.83#ibcon#*before write, iclass 27, count 0 2006.201.04:35:05.83#ibcon#enter sib2, iclass 27, count 0 2006.201.04:35:05.83#ibcon#flushed, iclass 27, count 0 2006.201.04:35:05.83#ibcon#about to write, iclass 27, count 0 2006.201.04:35:05.83#ibcon#wrote, iclass 27, count 0 2006.201.04:35:05.83#ibcon#about to read 3, iclass 27, count 0 2006.201.04:35:05.86#ibcon#read 3, iclass 27, count 0 2006.201.04:35:05.86#ibcon#about to read 4, iclass 27, count 0 2006.201.04:35:05.86#ibcon#read 4, iclass 27, count 0 2006.201.04:35:05.86#ibcon#about to read 5, iclass 27, count 0 2006.201.04:35:05.86#ibcon#read 5, iclass 27, count 0 2006.201.04:35:05.86#ibcon#about to read 6, iclass 27, count 0 2006.201.04:35:05.86#ibcon#read 6, iclass 27, count 0 2006.201.04:35:05.86#ibcon#end of sib2, iclass 27, count 0 2006.201.04:35:05.86#ibcon#*after write, iclass 27, count 0 2006.201.04:35:05.86#ibcon#*before return 0, iclass 27, count 0 2006.201.04:35:05.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:05.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:05.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:35:05.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:35:05.86$vck44/valo=3,564.99 2006.201.04:35:05.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.04:35:05.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.04:35:05.86#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:05.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:05.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:05.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:05.86#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:35:05.86#ibcon#first serial, iclass 29, count 0 2006.201.04:35:05.86#ibcon#enter sib2, iclass 29, count 0 2006.201.04:35:05.86#ibcon#flushed, iclass 29, count 0 2006.201.04:35:05.86#ibcon#about to write, iclass 29, count 0 2006.201.04:35:05.86#ibcon#wrote, iclass 29, count 0 2006.201.04:35:05.86#ibcon#about to read 3, iclass 29, count 0 2006.201.04:35:05.88#ibcon#read 3, iclass 29, count 0 2006.201.04:35:05.88#ibcon#about to read 4, iclass 29, count 0 2006.201.04:35:05.88#ibcon#read 4, iclass 29, count 0 2006.201.04:35:05.88#ibcon#about to read 5, iclass 29, count 0 2006.201.04:35:05.88#ibcon#read 5, iclass 29, count 0 2006.201.04:35:05.88#ibcon#about to read 6, iclass 29, count 0 2006.201.04:35:05.88#ibcon#read 6, iclass 29, count 0 2006.201.04:35:05.88#ibcon#end of sib2, iclass 29, count 0 2006.201.04:35:05.88#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:35:05.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:35:05.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:35:05.88#ibcon#*before write, iclass 29, count 0 2006.201.04:35:05.88#ibcon#enter sib2, iclass 29, count 0 2006.201.04:35:05.88#ibcon#flushed, iclass 29, count 0 2006.201.04:35:05.88#ibcon#about to write, iclass 29, count 0 2006.201.04:35:05.88#ibcon#wrote, iclass 29, count 0 2006.201.04:35:05.88#ibcon#about to read 3, iclass 29, count 0 2006.201.04:35:05.92#ibcon#read 3, iclass 29, count 0 2006.201.04:35:05.92#ibcon#about to read 4, iclass 29, count 0 2006.201.04:35:05.92#ibcon#read 4, iclass 29, count 0 2006.201.04:35:05.92#ibcon#about to read 5, iclass 29, count 0 2006.201.04:35:05.92#ibcon#read 5, iclass 29, count 0 2006.201.04:35:05.92#ibcon#about to read 6, iclass 29, count 0 2006.201.04:35:05.92#ibcon#read 6, iclass 29, count 0 2006.201.04:35:05.92#ibcon#end of sib2, iclass 29, count 0 2006.201.04:35:05.92#ibcon#*after write, iclass 29, count 0 2006.201.04:35:05.92#ibcon#*before return 0, iclass 29, count 0 2006.201.04:35:05.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:05.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:05.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:35:05.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:35:05.92$vck44/va=3,8 2006.201.04:35:05.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.04:35:05.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.04:35:05.92#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:05.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:05.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:05.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:05.98#ibcon#enter wrdev, iclass 31, count 2 2006.201.04:35:05.98#ibcon#first serial, iclass 31, count 2 2006.201.04:35:05.98#ibcon#enter sib2, iclass 31, count 2 2006.201.04:35:05.98#ibcon#flushed, iclass 31, count 2 2006.201.04:35:05.98#ibcon#about to write, iclass 31, count 2 2006.201.04:35:05.98#ibcon#wrote, iclass 31, count 2 2006.201.04:35:05.98#ibcon#about to read 3, iclass 31, count 2 2006.201.04:35:06.00#ibcon#read 3, iclass 31, count 2 2006.201.04:35:06.00#ibcon#about to read 4, iclass 31, count 2 2006.201.04:35:06.00#ibcon#read 4, iclass 31, count 2 2006.201.04:35:06.00#ibcon#about to read 5, iclass 31, count 2 2006.201.04:35:06.00#ibcon#read 5, iclass 31, count 2 2006.201.04:35:06.00#ibcon#about to read 6, iclass 31, count 2 2006.201.04:35:06.00#ibcon#read 6, iclass 31, count 2 2006.201.04:35:06.00#ibcon#end of sib2, iclass 31, count 2 2006.201.04:35:06.00#ibcon#*mode == 0, iclass 31, count 2 2006.201.04:35:06.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.04:35:06.00#ibcon#[25=AT03-08\r\n] 2006.201.04:35:06.00#ibcon#*before write, iclass 31, count 2 2006.201.04:35:06.00#ibcon#enter sib2, iclass 31, count 2 2006.201.04:35:06.00#ibcon#flushed, iclass 31, count 2 2006.201.04:35:06.00#ibcon#about to write, iclass 31, count 2 2006.201.04:35:06.00#ibcon#wrote, iclass 31, count 2 2006.201.04:35:06.00#ibcon#about to read 3, iclass 31, count 2 2006.201.04:35:06.03#ibcon#read 3, iclass 31, count 2 2006.201.04:35:06.03#ibcon#about to read 4, iclass 31, count 2 2006.201.04:35:06.03#ibcon#read 4, iclass 31, count 2 2006.201.04:35:06.03#ibcon#about to read 5, iclass 31, count 2 2006.201.04:35:06.03#ibcon#read 5, iclass 31, count 2 2006.201.04:35:06.03#ibcon#about to read 6, iclass 31, count 2 2006.201.04:35:06.03#ibcon#read 6, iclass 31, count 2 2006.201.04:35:06.03#ibcon#end of sib2, iclass 31, count 2 2006.201.04:35:06.03#ibcon#*after write, iclass 31, count 2 2006.201.04:35:06.03#ibcon#*before return 0, iclass 31, count 2 2006.201.04:35:06.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:06.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:06.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.04:35:06.03#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:06.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:06.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:06.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:06.15#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:35:06.15#ibcon#first serial, iclass 31, count 0 2006.201.04:35:06.15#ibcon#enter sib2, iclass 31, count 0 2006.201.04:35:06.15#ibcon#flushed, iclass 31, count 0 2006.201.04:35:06.15#ibcon#about to write, iclass 31, count 0 2006.201.04:35:06.15#ibcon#wrote, iclass 31, count 0 2006.201.04:35:06.15#ibcon#about to read 3, iclass 31, count 0 2006.201.04:35:06.17#ibcon#read 3, iclass 31, count 0 2006.201.04:35:06.17#ibcon#about to read 4, iclass 31, count 0 2006.201.04:35:06.17#ibcon#read 4, iclass 31, count 0 2006.201.04:35:06.17#ibcon#about to read 5, iclass 31, count 0 2006.201.04:35:06.17#ibcon#read 5, iclass 31, count 0 2006.201.04:35:06.17#ibcon#about to read 6, iclass 31, count 0 2006.201.04:35:06.17#ibcon#read 6, iclass 31, count 0 2006.201.04:35:06.17#ibcon#end of sib2, iclass 31, count 0 2006.201.04:35:06.17#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:35:06.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:35:06.17#ibcon#[25=USB\r\n] 2006.201.04:35:06.17#ibcon#*before write, iclass 31, count 0 2006.201.04:35:06.17#ibcon#enter sib2, iclass 31, count 0 2006.201.04:35:06.17#ibcon#flushed, iclass 31, count 0 2006.201.04:35:06.17#ibcon#about to write, iclass 31, count 0 2006.201.04:35:06.17#ibcon#wrote, iclass 31, count 0 2006.201.04:35:06.17#ibcon#about to read 3, iclass 31, count 0 2006.201.04:35:06.20#ibcon#read 3, iclass 31, count 0 2006.201.04:35:06.20#ibcon#about to read 4, iclass 31, count 0 2006.201.04:35:06.20#ibcon#read 4, iclass 31, count 0 2006.201.04:35:06.20#ibcon#about to read 5, iclass 31, count 0 2006.201.04:35:06.20#ibcon#read 5, iclass 31, count 0 2006.201.04:35:06.20#ibcon#about to read 6, iclass 31, count 0 2006.201.04:35:06.20#ibcon#read 6, iclass 31, count 0 2006.201.04:35:06.20#ibcon#end of sib2, iclass 31, count 0 2006.201.04:35:06.20#ibcon#*after write, iclass 31, count 0 2006.201.04:35:06.20#ibcon#*before return 0, iclass 31, count 0 2006.201.04:35:06.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:06.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:06.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:35:06.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:35:06.20$vck44/valo=4,624.99 2006.201.04:35:06.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.04:35:06.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.04:35:06.20#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:06.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:06.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:06.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:06.20#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:35:06.20#ibcon#first serial, iclass 33, count 0 2006.201.04:35:06.20#ibcon#enter sib2, iclass 33, count 0 2006.201.04:35:06.20#ibcon#flushed, iclass 33, count 0 2006.201.04:35:06.20#ibcon#about to write, iclass 33, count 0 2006.201.04:35:06.20#ibcon#wrote, iclass 33, count 0 2006.201.04:35:06.20#ibcon#about to read 3, iclass 33, count 0 2006.201.04:35:06.22#ibcon#read 3, iclass 33, count 0 2006.201.04:35:06.22#ibcon#about to read 4, iclass 33, count 0 2006.201.04:35:06.22#ibcon#read 4, iclass 33, count 0 2006.201.04:35:06.22#ibcon#about to read 5, iclass 33, count 0 2006.201.04:35:06.22#ibcon#read 5, iclass 33, count 0 2006.201.04:35:06.22#ibcon#about to read 6, iclass 33, count 0 2006.201.04:35:06.22#ibcon#read 6, iclass 33, count 0 2006.201.04:35:06.22#ibcon#end of sib2, iclass 33, count 0 2006.201.04:35:06.22#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:35:06.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:35:06.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:35:06.22#ibcon#*before write, iclass 33, count 0 2006.201.04:35:06.22#ibcon#enter sib2, iclass 33, count 0 2006.201.04:35:06.22#ibcon#flushed, iclass 33, count 0 2006.201.04:35:06.22#ibcon#about to write, iclass 33, count 0 2006.201.04:35:06.22#ibcon#wrote, iclass 33, count 0 2006.201.04:35:06.22#ibcon#about to read 3, iclass 33, count 0 2006.201.04:35:06.26#ibcon#read 3, iclass 33, count 0 2006.201.04:35:06.26#ibcon#about to read 4, iclass 33, count 0 2006.201.04:35:06.26#ibcon#read 4, iclass 33, count 0 2006.201.04:35:06.26#ibcon#about to read 5, iclass 33, count 0 2006.201.04:35:06.26#ibcon#read 5, iclass 33, count 0 2006.201.04:35:06.26#ibcon#about to read 6, iclass 33, count 0 2006.201.04:35:06.26#ibcon#read 6, iclass 33, count 0 2006.201.04:35:06.26#ibcon#end of sib2, iclass 33, count 0 2006.201.04:35:06.26#ibcon#*after write, iclass 33, count 0 2006.201.04:35:06.26#ibcon#*before return 0, iclass 33, count 0 2006.201.04:35:06.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:06.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:06.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:35:06.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:35:06.26$vck44/va=4,7 2006.201.04:35:06.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.04:35:06.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.04:35:06.26#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:06.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:06.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:06.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:06.32#ibcon#enter wrdev, iclass 35, count 2 2006.201.04:35:06.32#ibcon#first serial, iclass 35, count 2 2006.201.04:35:06.32#ibcon#enter sib2, iclass 35, count 2 2006.201.04:35:06.32#ibcon#flushed, iclass 35, count 2 2006.201.04:35:06.32#ibcon#about to write, iclass 35, count 2 2006.201.04:35:06.32#ibcon#wrote, iclass 35, count 2 2006.201.04:35:06.32#ibcon#about to read 3, iclass 35, count 2 2006.201.04:35:06.34#ibcon#read 3, iclass 35, count 2 2006.201.04:35:06.34#ibcon#about to read 4, iclass 35, count 2 2006.201.04:35:06.34#ibcon#read 4, iclass 35, count 2 2006.201.04:35:06.34#ibcon#about to read 5, iclass 35, count 2 2006.201.04:35:06.34#ibcon#read 5, iclass 35, count 2 2006.201.04:35:06.34#ibcon#about to read 6, iclass 35, count 2 2006.201.04:35:06.34#ibcon#read 6, iclass 35, count 2 2006.201.04:35:06.34#ibcon#end of sib2, iclass 35, count 2 2006.201.04:35:06.34#ibcon#*mode == 0, iclass 35, count 2 2006.201.04:35:06.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.04:35:06.34#ibcon#[25=AT04-07\r\n] 2006.201.04:35:06.34#ibcon#*before write, iclass 35, count 2 2006.201.04:35:06.34#ibcon#enter sib2, iclass 35, count 2 2006.201.04:35:06.34#ibcon#flushed, iclass 35, count 2 2006.201.04:35:06.34#ibcon#about to write, iclass 35, count 2 2006.201.04:35:06.34#ibcon#wrote, iclass 35, count 2 2006.201.04:35:06.34#ibcon#about to read 3, iclass 35, count 2 2006.201.04:35:06.37#ibcon#read 3, iclass 35, count 2 2006.201.04:35:06.43#ibcon#about to read 4, iclass 35, count 2 2006.201.04:35:06.43#ibcon#read 4, iclass 35, count 2 2006.201.04:35:06.43#ibcon#about to read 5, iclass 35, count 2 2006.201.04:35:06.43#ibcon#read 5, iclass 35, count 2 2006.201.04:35:06.43#ibcon#about to read 6, iclass 35, count 2 2006.201.04:35:06.43#ibcon#read 6, iclass 35, count 2 2006.201.04:35:06.43#ibcon#end of sib2, iclass 35, count 2 2006.201.04:35:06.43#ibcon#*after write, iclass 35, count 2 2006.201.04:35:06.44#ibcon#*before return 0, iclass 35, count 2 2006.201.04:35:06.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:06.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:06.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.04:35:06.44#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:06.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:06.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:06.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:06.56#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:35:06.56#ibcon#first serial, iclass 35, count 0 2006.201.04:35:06.56#ibcon#enter sib2, iclass 35, count 0 2006.201.04:35:06.56#ibcon#flushed, iclass 35, count 0 2006.201.04:35:06.56#ibcon#about to write, iclass 35, count 0 2006.201.04:35:06.56#ibcon#wrote, iclass 35, count 0 2006.201.04:35:06.56#ibcon#about to read 3, iclass 35, count 0 2006.201.04:35:06.58#ibcon#read 3, iclass 35, count 0 2006.201.04:35:06.58#ibcon#about to read 4, iclass 35, count 0 2006.201.04:35:06.58#ibcon#read 4, iclass 35, count 0 2006.201.04:35:06.58#ibcon#about to read 5, iclass 35, count 0 2006.201.04:35:06.58#ibcon#read 5, iclass 35, count 0 2006.201.04:35:06.58#ibcon#about to read 6, iclass 35, count 0 2006.201.04:35:06.58#ibcon#read 6, iclass 35, count 0 2006.201.04:35:06.58#ibcon#end of sib2, iclass 35, count 0 2006.201.04:35:06.58#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:35:06.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:35:06.58#ibcon#[25=USB\r\n] 2006.201.04:35:06.58#ibcon#*before write, iclass 35, count 0 2006.201.04:35:06.58#ibcon#enter sib2, iclass 35, count 0 2006.201.04:35:06.58#ibcon#flushed, iclass 35, count 0 2006.201.04:35:06.58#ibcon#about to write, iclass 35, count 0 2006.201.04:35:06.58#ibcon#wrote, iclass 35, count 0 2006.201.04:35:06.58#ibcon#about to read 3, iclass 35, count 0 2006.201.04:35:06.61#ibcon#read 3, iclass 35, count 0 2006.201.04:35:06.61#ibcon#about to read 4, iclass 35, count 0 2006.201.04:35:06.61#ibcon#read 4, iclass 35, count 0 2006.201.04:35:06.61#ibcon#about to read 5, iclass 35, count 0 2006.201.04:35:06.61#ibcon#read 5, iclass 35, count 0 2006.201.04:35:06.61#ibcon#about to read 6, iclass 35, count 0 2006.201.04:35:06.61#ibcon#read 6, iclass 35, count 0 2006.201.04:35:06.61#ibcon#end of sib2, iclass 35, count 0 2006.201.04:35:06.61#ibcon#*after write, iclass 35, count 0 2006.201.04:35:06.61#ibcon#*before return 0, iclass 35, count 0 2006.201.04:35:06.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:06.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:06.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:35:06.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:35:06.61$vck44/valo=5,734.99 2006.201.04:35:06.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.04:35:06.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.04:35:06.61#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:06.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:06.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:06.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:06.61#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:35:06.61#ibcon#first serial, iclass 37, count 0 2006.201.04:35:06.61#ibcon#enter sib2, iclass 37, count 0 2006.201.04:35:06.61#ibcon#flushed, iclass 37, count 0 2006.201.04:35:06.61#ibcon#about to write, iclass 37, count 0 2006.201.04:35:06.61#ibcon#wrote, iclass 37, count 0 2006.201.04:35:06.61#ibcon#about to read 3, iclass 37, count 0 2006.201.04:35:06.63#ibcon#read 3, iclass 37, count 0 2006.201.04:35:06.63#ibcon#about to read 4, iclass 37, count 0 2006.201.04:35:06.63#ibcon#read 4, iclass 37, count 0 2006.201.04:35:06.63#ibcon#about to read 5, iclass 37, count 0 2006.201.04:35:06.63#ibcon#read 5, iclass 37, count 0 2006.201.04:35:06.63#ibcon#about to read 6, iclass 37, count 0 2006.201.04:35:06.63#ibcon#read 6, iclass 37, count 0 2006.201.04:35:06.63#ibcon#end of sib2, iclass 37, count 0 2006.201.04:35:06.63#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:35:06.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:35:06.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:35:06.63#ibcon#*before write, iclass 37, count 0 2006.201.04:35:06.63#ibcon#enter sib2, iclass 37, count 0 2006.201.04:35:06.63#ibcon#flushed, iclass 37, count 0 2006.201.04:35:06.63#ibcon#about to write, iclass 37, count 0 2006.201.04:35:06.63#ibcon#wrote, iclass 37, count 0 2006.201.04:35:06.63#ibcon#about to read 3, iclass 37, count 0 2006.201.04:35:06.67#ibcon#read 3, iclass 37, count 0 2006.201.04:35:06.67#ibcon#about to read 4, iclass 37, count 0 2006.201.04:35:06.67#ibcon#read 4, iclass 37, count 0 2006.201.04:35:06.67#ibcon#about to read 5, iclass 37, count 0 2006.201.04:35:06.67#ibcon#read 5, iclass 37, count 0 2006.201.04:35:06.67#ibcon#about to read 6, iclass 37, count 0 2006.201.04:35:06.67#ibcon#read 6, iclass 37, count 0 2006.201.04:35:06.67#ibcon#end of sib2, iclass 37, count 0 2006.201.04:35:06.67#ibcon#*after write, iclass 37, count 0 2006.201.04:35:06.67#ibcon#*before return 0, iclass 37, count 0 2006.201.04:35:06.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:06.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:06.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:35:06.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:35:06.67$vck44/va=5,4 2006.201.04:35:06.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.04:35:06.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.04:35:06.67#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:06.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:06.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:06.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:06.73#ibcon#enter wrdev, iclass 39, count 2 2006.201.04:35:06.73#ibcon#first serial, iclass 39, count 2 2006.201.04:35:06.73#ibcon#enter sib2, iclass 39, count 2 2006.201.04:35:06.73#ibcon#flushed, iclass 39, count 2 2006.201.04:35:06.73#ibcon#about to write, iclass 39, count 2 2006.201.04:35:06.73#ibcon#wrote, iclass 39, count 2 2006.201.04:35:06.73#ibcon#about to read 3, iclass 39, count 2 2006.201.04:35:06.75#ibcon#read 3, iclass 39, count 2 2006.201.04:35:06.75#ibcon#about to read 4, iclass 39, count 2 2006.201.04:35:06.75#ibcon#read 4, iclass 39, count 2 2006.201.04:35:06.75#ibcon#about to read 5, iclass 39, count 2 2006.201.04:35:06.75#ibcon#read 5, iclass 39, count 2 2006.201.04:35:06.75#ibcon#about to read 6, iclass 39, count 2 2006.201.04:35:06.75#ibcon#read 6, iclass 39, count 2 2006.201.04:35:06.75#ibcon#end of sib2, iclass 39, count 2 2006.201.04:35:06.75#ibcon#*mode == 0, iclass 39, count 2 2006.201.04:35:06.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.04:35:06.75#ibcon#[25=AT05-04\r\n] 2006.201.04:35:06.75#ibcon#*before write, iclass 39, count 2 2006.201.04:35:06.75#ibcon#enter sib2, iclass 39, count 2 2006.201.04:35:06.75#ibcon#flushed, iclass 39, count 2 2006.201.04:35:06.75#ibcon#about to write, iclass 39, count 2 2006.201.04:35:06.75#ibcon#wrote, iclass 39, count 2 2006.201.04:35:06.75#ibcon#about to read 3, iclass 39, count 2 2006.201.04:35:06.78#ibcon#read 3, iclass 39, count 2 2006.201.04:35:06.78#ibcon#about to read 4, iclass 39, count 2 2006.201.04:35:06.78#ibcon#read 4, iclass 39, count 2 2006.201.04:35:06.78#ibcon#about to read 5, iclass 39, count 2 2006.201.04:35:06.78#ibcon#read 5, iclass 39, count 2 2006.201.04:35:06.78#ibcon#about to read 6, iclass 39, count 2 2006.201.04:35:06.78#ibcon#read 6, iclass 39, count 2 2006.201.04:35:06.78#ibcon#end of sib2, iclass 39, count 2 2006.201.04:35:06.78#ibcon#*after write, iclass 39, count 2 2006.201.04:35:06.78#ibcon#*before return 0, iclass 39, count 2 2006.201.04:35:06.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:06.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:06.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.04:35:06.78#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:06.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:06.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:06.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:06.90#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:35:06.90#ibcon#first serial, iclass 39, count 0 2006.201.04:35:06.90#ibcon#enter sib2, iclass 39, count 0 2006.201.04:35:06.90#ibcon#flushed, iclass 39, count 0 2006.201.04:35:06.90#ibcon#about to write, iclass 39, count 0 2006.201.04:35:06.90#ibcon#wrote, iclass 39, count 0 2006.201.04:35:06.90#ibcon#about to read 3, iclass 39, count 0 2006.201.04:35:06.92#ibcon#read 3, iclass 39, count 0 2006.201.04:35:06.92#ibcon#about to read 4, iclass 39, count 0 2006.201.04:35:06.92#ibcon#read 4, iclass 39, count 0 2006.201.04:35:06.92#ibcon#about to read 5, iclass 39, count 0 2006.201.04:35:06.92#ibcon#read 5, iclass 39, count 0 2006.201.04:35:06.92#ibcon#about to read 6, iclass 39, count 0 2006.201.04:35:06.92#ibcon#read 6, iclass 39, count 0 2006.201.04:35:06.92#ibcon#end of sib2, iclass 39, count 0 2006.201.04:35:06.92#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:35:06.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:35:06.92#ibcon#[25=USB\r\n] 2006.201.04:35:06.92#ibcon#*before write, iclass 39, count 0 2006.201.04:35:06.92#ibcon#enter sib2, iclass 39, count 0 2006.201.04:35:06.92#ibcon#flushed, iclass 39, count 0 2006.201.04:35:06.92#ibcon#about to write, iclass 39, count 0 2006.201.04:35:06.92#ibcon#wrote, iclass 39, count 0 2006.201.04:35:06.92#ibcon#about to read 3, iclass 39, count 0 2006.201.04:35:06.95#ibcon#read 3, iclass 39, count 0 2006.201.04:35:06.95#ibcon#about to read 4, iclass 39, count 0 2006.201.04:35:06.95#ibcon#read 4, iclass 39, count 0 2006.201.04:35:06.95#ibcon#about to read 5, iclass 39, count 0 2006.201.04:35:06.95#ibcon#read 5, iclass 39, count 0 2006.201.04:35:06.95#ibcon#about to read 6, iclass 39, count 0 2006.201.04:35:06.95#ibcon#read 6, iclass 39, count 0 2006.201.04:35:06.95#ibcon#end of sib2, iclass 39, count 0 2006.201.04:35:06.95#ibcon#*after write, iclass 39, count 0 2006.201.04:35:06.95#ibcon#*before return 0, iclass 39, count 0 2006.201.04:35:06.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:06.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:06.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:35:06.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:35:06.95$vck44/valo=6,814.99 2006.201.04:35:06.95#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.04:35:06.95#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.04:35:06.95#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:06.95#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:06.95#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:06.95#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:06.95#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:35:06.95#ibcon#first serial, iclass 2, count 0 2006.201.04:35:06.95#ibcon#enter sib2, iclass 2, count 0 2006.201.04:35:06.95#ibcon#flushed, iclass 2, count 0 2006.201.04:35:06.95#ibcon#about to write, iclass 2, count 0 2006.201.04:35:06.95#ibcon#wrote, iclass 2, count 0 2006.201.04:35:06.95#ibcon#about to read 3, iclass 2, count 0 2006.201.04:35:06.97#ibcon#read 3, iclass 2, count 0 2006.201.04:35:06.97#ibcon#about to read 4, iclass 2, count 0 2006.201.04:35:06.97#ibcon#read 4, iclass 2, count 0 2006.201.04:35:06.97#ibcon#about to read 5, iclass 2, count 0 2006.201.04:35:06.97#ibcon#read 5, iclass 2, count 0 2006.201.04:35:06.97#ibcon#about to read 6, iclass 2, count 0 2006.201.04:35:06.97#ibcon#read 6, iclass 2, count 0 2006.201.04:35:06.97#ibcon#end of sib2, iclass 2, count 0 2006.201.04:35:06.97#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:35:06.97#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:35:06.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:35:06.97#ibcon#*before write, iclass 2, count 0 2006.201.04:35:06.97#ibcon#enter sib2, iclass 2, count 0 2006.201.04:35:06.97#ibcon#flushed, iclass 2, count 0 2006.201.04:35:06.97#ibcon#about to write, iclass 2, count 0 2006.201.04:35:06.97#ibcon#wrote, iclass 2, count 0 2006.201.04:35:06.97#ibcon#about to read 3, iclass 2, count 0 2006.201.04:35:07.01#ibcon#read 3, iclass 2, count 0 2006.201.04:35:07.01#ibcon#about to read 4, iclass 2, count 0 2006.201.04:35:07.01#ibcon#read 4, iclass 2, count 0 2006.201.04:35:07.01#ibcon#about to read 5, iclass 2, count 0 2006.201.04:35:07.01#ibcon#read 5, iclass 2, count 0 2006.201.04:35:07.01#ibcon#about to read 6, iclass 2, count 0 2006.201.04:35:07.01#ibcon#read 6, iclass 2, count 0 2006.201.04:35:07.01#ibcon#end of sib2, iclass 2, count 0 2006.201.04:35:07.01#ibcon#*after write, iclass 2, count 0 2006.201.04:35:07.01#ibcon#*before return 0, iclass 2, count 0 2006.201.04:35:07.01#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:07.01#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:07.01#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:35:07.01#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:35:07.01$vck44/va=6,5 2006.201.04:35:07.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.04:35:07.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.04:35:07.01#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:07.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:07.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:07.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:07.07#ibcon#enter wrdev, iclass 5, count 2 2006.201.04:35:07.07#ibcon#first serial, iclass 5, count 2 2006.201.04:35:07.07#ibcon#enter sib2, iclass 5, count 2 2006.201.04:35:07.07#ibcon#flushed, iclass 5, count 2 2006.201.04:35:07.07#ibcon#about to write, iclass 5, count 2 2006.201.04:35:07.07#ibcon#wrote, iclass 5, count 2 2006.201.04:35:07.07#ibcon#about to read 3, iclass 5, count 2 2006.201.04:35:07.09#ibcon#read 3, iclass 5, count 2 2006.201.04:35:07.09#ibcon#about to read 4, iclass 5, count 2 2006.201.04:35:07.09#ibcon#read 4, iclass 5, count 2 2006.201.04:35:07.09#ibcon#about to read 5, iclass 5, count 2 2006.201.04:35:07.09#ibcon#read 5, iclass 5, count 2 2006.201.04:35:07.09#ibcon#about to read 6, iclass 5, count 2 2006.201.04:35:07.09#ibcon#read 6, iclass 5, count 2 2006.201.04:35:07.09#ibcon#end of sib2, iclass 5, count 2 2006.201.04:35:07.09#ibcon#*mode == 0, iclass 5, count 2 2006.201.04:35:07.09#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.04:35:07.09#ibcon#[25=AT06-05\r\n] 2006.201.04:35:07.09#ibcon#*before write, iclass 5, count 2 2006.201.04:35:07.09#ibcon#enter sib2, iclass 5, count 2 2006.201.04:35:07.09#ibcon#flushed, iclass 5, count 2 2006.201.04:35:07.09#ibcon#about to write, iclass 5, count 2 2006.201.04:35:07.09#ibcon#wrote, iclass 5, count 2 2006.201.04:35:07.09#ibcon#about to read 3, iclass 5, count 2 2006.201.04:35:07.12#ibcon#read 3, iclass 5, count 2 2006.201.04:35:07.12#ibcon#about to read 4, iclass 5, count 2 2006.201.04:35:07.12#ibcon#read 4, iclass 5, count 2 2006.201.04:35:07.12#ibcon#about to read 5, iclass 5, count 2 2006.201.04:35:07.12#ibcon#read 5, iclass 5, count 2 2006.201.04:35:07.12#ibcon#about to read 6, iclass 5, count 2 2006.201.04:35:07.12#ibcon#read 6, iclass 5, count 2 2006.201.04:35:07.12#ibcon#end of sib2, iclass 5, count 2 2006.201.04:35:07.12#ibcon#*after write, iclass 5, count 2 2006.201.04:35:07.12#ibcon#*before return 0, iclass 5, count 2 2006.201.04:35:07.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:07.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:07.12#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.04:35:07.12#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:07.12#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:07.24#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:07.24#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:07.24#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:35:07.24#ibcon#first serial, iclass 5, count 0 2006.201.04:35:07.24#ibcon#enter sib2, iclass 5, count 0 2006.201.04:35:07.24#ibcon#flushed, iclass 5, count 0 2006.201.04:35:07.24#ibcon#about to write, iclass 5, count 0 2006.201.04:35:07.24#ibcon#wrote, iclass 5, count 0 2006.201.04:35:07.24#ibcon#about to read 3, iclass 5, count 0 2006.201.04:35:07.26#ibcon#read 3, iclass 5, count 0 2006.201.04:35:07.26#ibcon#about to read 4, iclass 5, count 0 2006.201.04:35:07.26#ibcon#read 4, iclass 5, count 0 2006.201.04:35:07.26#ibcon#about to read 5, iclass 5, count 0 2006.201.04:35:07.26#ibcon#read 5, iclass 5, count 0 2006.201.04:35:07.26#ibcon#about to read 6, iclass 5, count 0 2006.201.04:35:07.26#ibcon#read 6, iclass 5, count 0 2006.201.04:35:07.26#ibcon#end of sib2, iclass 5, count 0 2006.201.04:35:07.26#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:35:07.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:35:07.26#ibcon#[25=USB\r\n] 2006.201.04:35:07.26#ibcon#*before write, iclass 5, count 0 2006.201.04:35:07.26#ibcon#enter sib2, iclass 5, count 0 2006.201.04:35:07.26#ibcon#flushed, iclass 5, count 0 2006.201.04:35:07.26#ibcon#about to write, iclass 5, count 0 2006.201.04:35:07.26#ibcon#wrote, iclass 5, count 0 2006.201.04:35:07.26#ibcon#about to read 3, iclass 5, count 0 2006.201.04:35:07.29#ibcon#read 3, iclass 5, count 0 2006.201.04:35:07.29#ibcon#about to read 4, iclass 5, count 0 2006.201.04:35:07.29#ibcon#read 4, iclass 5, count 0 2006.201.04:35:07.29#ibcon#about to read 5, iclass 5, count 0 2006.201.04:35:07.29#ibcon#read 5, iclass 5, count 0 2006.201.04:35:07.29#ibcon#about to read 6, iclass 5, count 0 2006.201.04:35:07.29#ibcon#read 6, iclass 5, count 0 2006.201.04:35:07.29#ibcon#end of sib2, iclass 5, count 0 2006.201.04:35:07.29#ibcon#*after write, iclass 5, count 0 2006.201.04:35:07.29#ibcon#*before return 0, iclass 5, count 0 2006.201.04:35:07.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:07.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:07.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:35:07.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:35:07.29$vck44/valo=7,864.99 2006.201.04:35:07.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.04:35:07.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.04:35:07.29#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:07.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:07.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:07.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:07.29#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:35:07.29#ibcon#first serial, iclass 7, count 0 2006.201.04:35:07.29#ibcon#enter sib2, iclass 7, count 0 2006.201.04:35:07.29#ibcon#flushed, iclass 7, count 0 2006.201.04:35:07.29#ibcon#about to write, iclass 7, count 0 2006.201.04:35:07.29#ibcon#wrote, iclass 7, count 0 2006.201.04:35:07.29#ibcon#about to read 3, iclass 7, count 0 2006.201.04:35:07.31#ibcon#read 3, iclass 7, count 0 2006.201.04:35:07.31#ibcon#about to read 4, iclass 7, count 0 2006.201.04:35:07.31#ibcon#read 4, iclass 7, count 0 2006.201.04:35:07.31#ibcon#about to read 5, iclass 7, count 0 2006.201.04:35:07.31#ibcon#read 5, iclass 7, count 0 2006.201.04:35:07.31#ibcon#about to read 6, iclass 7, count 0 2006.201.04:35:07.31#ibcon#read 6, iclass 7, count 0 2006.201.04:35:07.31#ibcon#end of sib2, iclass 7, count 0 2006.201.04:35:07.31#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:35:07.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:35:07.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:35:07.31#ibcon#*before write, iclass 7, count 0 2006.201.04:35:07.31#ibcon#enter sib2, iclass 7, count 0 2006.201.04:35:07.31#ibcon#flushed, iclass 7, count 0 2006.201.04:35:07.31#ibcon#about to write, iclass 7, count 0 2006.201.04:35:07.31#ibcon#wrote, iclass 7, count 0 2006.201.04:35:07.31#ibcon#about to read 3, iclass 7, count 0 2006.201.04:35:07.35#ibcon#read 3, iclass 7, count 0 2006.201.04:35:07.35#ibcon#about to read 4, iclass 7, count 0 2006.201.04:35:07.35#ibcon#read 4, iclass 7, count 0 2006.201.04:35:07.35#ibcon#about to read 5, iclass 7, count 0 2006.201.04:35:07.35#ibcon#read 5, iclass 7, count 0 2006.201.04:35:07.35#ibcon#about to read 6, iclass 7, count 0 2006.201.04:35:07.35#ibcon#read 6, iclass 7, count 0 2006.201.04:35:07.35#ibcon#end of sib2, iclass 7, count 0 2006.201.04:35:07.35#ibcon#*after write, iclass 7, count 0 2006.201.04:35:07.35#ibcon#*before return 0, iclass 7, count 0 2006.201.04:35:07.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:07.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:07.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:35:07.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:35:07.35$vck44/va=7,5 2006.201.04:35:07.35#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.04:35:07.35#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.04:35:07.35#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:07.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:07.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:07.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:07.41#ibcon#enter wrdev, iclass 11, count 2 2006.201.04:35:07.41#ibcon#first serial, iclass 11, count 2 2006.201.04:35:07.41#ibcon#enter sib2, iclass 11, count 2 2006.201.04:35:07.41#ibcon#flushed, iclass 11, count 2 2006.201.04:35:07.41#ibcon#about to write, iclass 11, count 2 2006.201.04:35:07.41#ibcon#wrote, iclass 11, count 2 2006.201.04:35:07.41#ibcon#about to read 3, iclass 11, count 2 2006.201.04:35:07.43#ibcon#read 3, iclass 11, count 2 2006.201.04:35:07.43#ibcon#about to read 4, iclass 11, count 2 2006.201.04:35:07.43#ibcon#read 4, iclass 11, count 2 2006.201.04:35:07.43#ibcon#about to read 5, iclass 11, count 2 2006.201.04:35:07.43#ibcon#read 5, iclass 11, count 2 2006.201.04:35:07.43#ibcon#about to read 6, iclass 11, count 2 2006.201.04:35:07.43#ibcon#read 6, iclass 11, count 2 2006.201.04:35:07.43#ibcon#end of sib2, iclass 11, count 2 2006.201.04:35:07.43#ibcon#*mode == 0, iclass 11, count 2 2006.201.04:35:07.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.04:35:07.43#ibcon#[25=AT07-05\r\n] 2006.201.04:35:07.43#ibcon#*before write, iclass 11, count 2 2006.201.04:35:07.43#ibcon#enter sib2, iclass 11, count 2 2006.201.04:35:07.43#ibcon#flushed, iclass 11, count 2 2006.201.04:35:07.43#ibcon#about to write, iclass 11, count 2 2006.201.04:35:07.43#ibcon#wrote, iclass 11, count 2 2006.201.04:35:07.43#ibcon#about to read 3, iclass 11, count 2 2006.201.04:35:07.46#ibcon#read 3, iclass 11, count 2 2006.201.04:35:07.46#ibcon#about to read 4, iclass 11, count 2 2006.201.04:35:07.46#ibcon#read 4, iclass 11, count 2 2006.201.04:35:07.52#ibcon#about to read 5, iclass 11, count 2 2006.201.04:35:07.52#ibcon#read 5, iclass 11, count 2 2006.201.04:35:07.52#ibcon#about to read 6, iclass 11, count 2 2006.201.04:35:07.52#ibcon#read 6, iclass 11, count 2 2006.201.04:35:07.52#ibcon#end of sib2, iclass 11, count 2 2006.201.04:35:07.52#ibcon#*after write, iclass 11, count 2 2006.201.04:35:07.52#ibcon#*before return 0, iclass 11, count 2 2006.201.04:35:07.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:07.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:07.52#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.04:35:07.52#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:07.52#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:07.64#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:07.64#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:07.64#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:35:07.64#ibcon#first serial, iclass 11, count 0 2006.201.04:35:07.64#ibcon#enter sib2, iclass 11, count 0 2006.201.04:35:07.64#ibcon#flushed, iclass 11, count 0 2006.201.04:35:07.64#ibcon#about to write, iclass 11, count 0 2006.201.04:35:07.64#ibcon#wrote, iclass 11, count 0 2006.201.04:35:07.64#ibcon#about to read 3, iclass 11, count 0 2006.201.04:35:07.66#ibcon#read 3, iclass 11, count 0 2006.201.04:35:07.66#ibcon#about to read 4, iclass 11, count 0 2006.201.04:35:07.66#ibcon#read 4, iclass 11, count 0 2006.201.04:35:07.66#ibcon#about to read 5, iclass 11, count 0 2006.201.04:35:07.66#ibcon#read 5, iclass 11, count 0 2006.201.04:35:07.66#ibcon#about to read 6, iclass 11, count 0 2006.201.04:35:07.66#ibcon#read 6, iclass 11, count 0 2006.201.04:35:07.66#ibcon#end of sib2, iclass 11, count 0 2006.201.04:35:07.66#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:35:07.66#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:35:07.66#ibcon#[25=USB\r\n] 2006.201.04:35:07.66#ibcon#*before write, iclass 11, count 0 2006.201.04:35:07.66#ibcon#enter sib2, iclass 11, count 0 2006.201.04:35:07.66#ibcon#flushed, iclass 11, count 0 2006.201.04:35:07.66#ibcon#about to write, iclass 11, count 0 2006.201.04:35:07.66#ibcon#wrote, iclass 11, count 0 2006.201.04:35:07.66#ibcon#about to read 3, iclass 11, count 0 2006.201.04:35:07.69#ibcon#read 3, iclass 11, count 0 2006.201.04:35:07.69#ibcon#about to read 4, iclass 11, count 0 2006.201.04:35:07.69#ibcon#read 4, iclass 11, count 0 2006.201.04:35:07.69#ibcon#about to read 5, iclass 11, count 0 2006.201.04:35:07.69#ibcon#read 5, iclass 11, count 0 2006.201.04:35:07.69#ibcon#about to read 6, iclass 11, count 0 2006.201.04:35:07.69#ibcon#read 6, iclass 11, count 0 2006.201.04:35:07.69#ibcon#end of sib2, iclass 11, count 0 2006.201.04:35:07.69#ibcon#*after write, iclass 11, count 0 2006.201.04:35:07.69#ibcon#*before return 0, iclass 11, count 0 2006.201.04:35:07.69#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:07.69#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:07.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:35:07.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:35:07.69$vck44/valo=8,884.99 2006.201.04:35:07.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.04:35:07.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.04:35:07.69#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:07.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:07.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:07.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:07.69#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:35:07.69#ibcon#first serial, iclass 13, count 0 2006.201.04:35:07.69#ibcon#enter sib2, iclass 13, count 0 2006.201.04:35:07.69#ibcon#flushed, iclass 13, count 0 2006.201.04:35:07.69#ibcon#about to write, iclass 13, count 0 2006.201.04:35:07.69#ibcon#wrote, iclass 13, count 0 2006.201.04:35:07.69#ibcon#about to read 3, iclass 13, count 0 2006.201.04:35:07.71#ibcon#read 3, iclass 13, count 0 2006.201.04:35:07.71#ibcon#about to read 4, iclass 13, count 0 2006.201.04:35:07.71#ibcon#read 4, iclass 13, count 0 2006.201.04:35:07.71#ibcon#about to read 5, iclass 13, count 0 2006.201.04:35:07.71#ibcon#read 5, iclass 13, count 0 2006.201.04:35:07.71#ibcon#about to read 6, iclass 13, count 0 2006.201.04:35:07.71#ibcon#read 6, iclass 13, count 0 2006.201.04:35:07.71#ibcon#end of sib2, iclass 13, count 0 2006.201.04:35:07.71#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:35:07.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:35:07.71#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:35:07.71#ibcon#*before write, iclass 13, count 0 2006.201.04:35:07.71#ibcon#enter sib2, iclass 13, count 0 2006.201.04:35:07.71#ibcon#flushed, iclass 13, count 0 2006.201.04:35:07.71#ibcon#about to write, iclass 13, count 0 2006.201.04:35:07.71#ibcon#wrote, iclass 13, count 0 2006.201.04:35:07.71#ibcon#about to read 3, iclass 13, count 0 2006.201.04:35:07.75#ibcon#read 3, iclass 13, count 0 2006.201.04:35:07.75#ibcon#about to read 4, iclass 13, count 0 2006.201.04:35:07.75#ibcon#read 4, iclass 13, count 0 2006.201.04:35:07.75#ibcon#about to read 5, iclass 13, count 0 2006.201.04:35:07.75#ibcon#read 5, iclass 13, count 0 2006.201.04:35:07.75#ibcon#about to read 6, iclass 13, count 0 2006.201.04:35:07.75#ibcon#read 6, iclass 13, count 0 2006.201.04:35:07.75#ibcon#end of sib2, iclass 13, count 0 2006.201.04:35:07.75#ibcon#*after write, iclass 13, count 0 2006.201.04:35:07.75#ibcon#*before return 0, iclass 13, count 0 2006.201.04:35:07.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:07.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:07.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:35:07.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:35:07.75$vck44/va=8,4 2006.201.04:35:07.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.04:35:07.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.04:35:07.75#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:07.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:35:07.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:35:07.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:35:07.81#ibcon#enter wrdev, iclass 15, count 2 2006.201.04:35:07.81#ibcon#first serial, iclass 15, count 2 2006.201.04:35:07.81#ibcon#enter sib2, iclass 15, count 2 2006.201.04:35:07.81#ibcon#flushed, iclass 15, count 2 2006.201.04:35:07.81#ibcon#about to write, iclass 15, count 2 2006.201.04:35:07.81#ibcon#wrote, iclass 15, count 2 2006.201.04:35:07.81#ibcon#about to read 3, iclass 15, count 2 2006.201.04:35:07.83#ibcon#read 3, iclass 15, count 2 2006.201.04:35:07.83#ibcon#about to read 4, iclass 15, count 2 2006.201.04:35:07.83#ibcon#read 4, iclass 15, count 2 2006.201.04:35:07.83#ibcon#about to read 5, iclass 15, count 2 2006.201.04:35:07.83#ibcon#read 5, iclass 15, count 2 2006.201.04:35:07.83#ibcon#about to read 6, iclass 15, count 2 2006.201.04:35:07.83#ibcon#read 6, iclass 15, count 2 2006.201.04:35:07.83#ibcon#end of sib2, iclass 15, count 2 2006.201.04:35:07.83#ibcon#*mode == 0, iclass 15, count 2 2006.201.04:35:07.83#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.04:35:07.83#ibcon#[25=AT08-04\r\n] 2006.201.04:35:07.83#ibcon#*before write, iclass 15, count 2 2006.201.04:35:07.83#ibcon#enter sib2, iclass 15, count 2 2006.201.04:35:07.83#ibcon#flushed, iclass 15, count 2 2006.201.04:35:07.83#ibcon#about to write, iclass 15, count 2 2006.201.04:35:07.83#ibcon#wrote, iclass 15, count 2 2006.201.04:35:07.83#ibcon#about to read 3, iclass 15, count 2 2006.201.04:35:07.86#ibcon#read 3, iclass 15, count 2 2006.201.04:35:07.86#ibcon#about to read 4, iclass 15, count 2 2006.201.04:35:07.86#ibcon#read 4, iclass 15, count 2 2006.201.04:35:07.86#ibcon#about to read 5, iclass 15, count 2 2006.201.04:35:07.86#ibcon#read 5, iclass 15, count 2 2006.201.04:35:07.86#ibcon#about to read 6, iclass 15, count 2 2006.201.04:35:07.86#ibcon#read 6, iclass 15, count 2 2006.201.04:35:07.86#ibcon#end of sib2, iclass 15, count 2 2006.201.04:35:07.86#ibcon#*after write, iclass 15, count 2 2006.201.04:35:07.86#ibcon#*before return 0, iclass 15, count 2 2006.201.04:35:07.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:35:07.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:35:07.86#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.04:35:07.86#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:07.86#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:35:07.98#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:35:07.98#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:35:07.98#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:35:07.98#ibcon#first serial, iclass 15, count 0 2006.201.04:35:07.98#ibcon#enter sib2, iclass 15, count 0 2006.201.04:35:07.98#ibcon#flushed, iclass 15, count 0 2006.201.04:35:07.98#ibcon#about to write, iclass 15, count 0 2006.201.04:35:07.98#ibcon#wrote, iclass 15, count 0 2006.201.04:35:07.98#ibcon#about to read 3, iclass 15, count 0 2006.201.04:35:08.00#ibcon#read 3, iclass 15, count 0 2006.201.04:35:08.00#ibcon#about to read 4, iclass 15, count 0 2006.201.04:35:08.00#ibcon#read 4, iclass 15, count 0 2006.201.04:35:08.00#ibcon#about to read 5, iclass 15, count 0 2006.201.04:35:08.00#ibcon#read 5, iclass 15, count 0 2006.201.04:35:08.00#ibcon#about to read 6, iclass 15, count 0 2006.201.04:35:08.00#ibcon#read 6, iclass 15, count 0 2006.201.04:35:08.00#ibcon#end of sib2, iclass 15, count 0 2006.201.04:35:08.00#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:35:08.00#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:35:08.00#ibcon#[25=USB\r\n] 2006.201.04:35:08.00#ibcon#*before write, iclass 15, count 0 2006.201.04:35:08.00#ibcon#enter sib2, iclass 15, count 0 2006.201.04:35:08.00#ibcon#flushed, iclass 15, count 0 2006.201.04:35:08.00#ibcon#about to write, iclass 15, count 0 2006.201.04:35:08.00#ibcon#wrote, iclass 15, count 0 2006.201.04:35:08.00#ibcon#about to read 3, iclass 15, count 0 2006.201.04:35:08.03#ibcon#read 3, iclass 15, count 0 2006.201.04:35:08.03#ibcon#about to read 4, iclass 15, count 0 2006.201.04:35:08.03#ibcon#read 4, iclass 15, count 0 2006.201.04:35:08.03#ibcon#about to read 5, iclass 15, count 0 2006.201.04:35:08.03#ibcon#read 5, iclass 15, count 0 2006.201.04:35:08.03#ibcon#about to read 6, iclass 15, count 0 2006.201.04:35:08.03#ibcon#read 6, iclass 15, count 0 2006.201.04:35:08.03#ibcon#end of sib2, iclass 15, count 0 2006.201.04:35:08.03#ibcon#*after write, iclass 15, count 0 2006.201.04:35:08.03#ibcon#*before return 0, iclass 15, count 0 2006.201.04:35:08.03#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:35:08.03#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:35:08.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:35:08.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:35:08.03$vck44/vblo=1,629.99 2006.201.04:35:08.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.04:35:08.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.04:35:08.03#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:08.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:35:08.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:35:08.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:35:08.03#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:35:08.03#ibcon#first serial, iclass 17, count 0 2006.201.04:35:08.03#ibcon#enter sib2, iclass 17, count 0 2006.201.04:35:08.03#ibcon#flushed, iclass 17, count 0 2006.201.04:35:08.03#ibcon#about to write, iclass 17, count 0 2006.201.04:35:08.03#ibcon#wrote, iclass 17, count 0 2006.201.04:35:08.03#ibcon#about to read 3, iclass 17, count 0 2006.201.04:35:08.05#ibcon#read 3, iclass 17, count 0 2006.201.04:35:08.05#ibcon#about to read 4, iclass 17, count 0 2006.201.04:35:08.05#ibcon#read 4, iclass 17, count 0 2006.201.04:35:08.05#ibcon#about to read 5, iclass 17, count 0 2006.201.04:35:08.05#ibcon#read 5, iclass 17, count 0 2006.201.04:35:08.05#ibcon#about to read 6, iclass 17, count 0 2006.201.04:35:08.05#ibcon#read 6, iclass 17, count 0 2006.201.04:35:08.05#ibcon#end of sib2, iclass 17, count 0 2006.201.04:35:08.05#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:35:08.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:35:08.05#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:35:08.05#ibcon#*before write, iclass 17, count 0 2006.201.04:35:08.05#ibcon#enter sib2, iclass 17, count 0 2006.201.04:35:08.05#ibcon#flushed, iclass 17, count 0 2006.201.04:35:08.05#ibcon#about to write, iclass 17, count 0 2006.201.04:35:08.05#ibcon#wrote, iclass 17, count 0 2006.201.04:35:08.05#ibcon#about to read 3, iclass 17, count 0 2006.201.04:35:08.09#ibcon#read 3, iclass 17, count 0 2006.201.04:35:08.09#ibcon#about to read 4, iclass 17, count 0 2006.201.04:35:08.09#ibcon#read 4, iclass 17, count 0 2006.201.04:35:08.09#ibcon#about to read 5, iclass 17, count 0 2006.201.04:35:08.09#ibcon#read 5, iclass 17, count 0 2006.201.04:35:08.09#ibcon#about to read 6, iclass 17, count 0 2006.201.04:35:08.09#ibcon#read 6, iclass 17, count 0 2006.201.04:35:08.09#ibcon#end of sib2, iclass 17, count 0 2006.201.04:35:08.09#ibcon#*after write, iclass 17, count 0 2006.201.04:35:08.09#ibcon#*before return 0, iclass 17, count 0 2006.201.04:35:08.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:35:08.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:35:08.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:35:08.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:35:08.09$vck44/vb=1,4 2006.201.04:35:08.09#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.04:35:08.09#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.04:35:08.09#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:08.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:35:08.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:35:08.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:35:08.09#ibcon#enter wrdev, iclass 19, count 2 2006.201.04:35:08.09#ibcon#first serial, iclass 19, count 2 2006.201.04:35:08.09#ibcon#enter sib2, iclass 19, count 2 2006.201.04:35:08.09#ibcon#flushed, iclass 19, count 2 2006.201.04:35:08.09#ibcon#about to write, iclass 19, count 2 2006.201.04:35:08.09#ibcon#wrote, iclass 19, count 2 2006.201.04:35:08.09#ibcon#about to read 3, iclass 19, count 2 2006.201.04:35:08.11#ibcon#read 3, iclass 19, count 2 2006.201.04:35:08.11#ibcon#about to read 4, iclass 19, count 2 2006.201.04:35:08.11#ibcon#read 4, iclass 19, count 2 2006.201.04:35:08.11#ibcon#about to read 5, iclass 19, count 2 2006.201.04:35:08.11#ibcon#read 5, iclass 19, count 2 2006.201.04:35:08.11#ibcon#about to read 6, iclass 19, count 2 2006.201.04:35:08.11#ibcon#read 6, iclass 19, count 2 2006.201.04:35:08.11#ibcon#end of sib2, iclass 19, count 2 2006.201.04:35:08.11#ibcon#*mode == 0, iclass 19, count 2 2006.201.04:35:08.11#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.04:35:08.11#ibcon#[27=AT01-04\r\n] 2006.201.04:35:08.11#ibcon#*before write, iclass 19, count 2 2006.201.04:35:08.11#ibcon#enter sib2, iclass 19, count 2 2006.201.04:35:08.11#ibcon#flushed, iclass 19, count 2 2006.201.04:35:08.11#ibcon#about to write, iclass 19, count 2 2006.201.04:35:08.11#ibcon#wrote, iclass 19, count 2 2006.201.04:35:08.11#ibcon#about to read 3, iclass 19, count 2 2006.201.04:35:08.14#ibcon#read 3, iclass 19, count 2 2006.201.04:35:08.14#ibcon#about to read 4, iclass 19, count 2 2006.201.04:35:08.14#ibcon#read 4, iclass 19, count 2 2006.201.04:35:08.14#ibcon#about to read 5, iclass 19, count 2 2006.201.04:35:08.14#ibcon#read 5, iclass 19, count 2 2006.201.04:35:08.14#ibcon#about to read 6, iclass 19, count 2 2006.201.04:35:08.14#ibcon#read 6, iclass 19, count 2 2006.201.04:35:08.14#ibcon#end of sib2, iclass 19, count 2 2006.201.04:35:08.14#ibcon#*after write, iclass 19, count 2 2006.201.04:35:08.14#ibcon#*before return 0, iclass 19, count 2 2006.201.04:35:08.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:35:08.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:35:08.14#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.04:35:08.14#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:08.14#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:35:08.26#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:35:08.26#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:35:08.26#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:35:08.26#ibcon#first serial, iclass 19, count 0 2006.201.04:35:08.26#ibcon#enter sib2, iclass 19, count 0 2006.201.04:35:08.26#ibcon#flushed, iclass 19, count 0 2006.201.04:35:08.26#ibcon#about to write, iclass 19, count 0 2006.201.04:35:08.26#ibcon#wrote, iclass 19, count 0 2006.201.04:35:08.26#ibcon#about to read 3, iclass 19, count 0 2006.201.04:35:08.28#ibcon#read 3, iclass 19, count 0 2006.201.04:35:08.28#ibcon#about to read 4, iclass 19, count 0 2006.201.04:35:08.28#ibcon#read 4, iclass 19, count 0 2006.201.04:35:08.28#ibcon#about to read 5, iclass 19, count 0 2006.201.04:35:08.28#ibcon#read 5, iclass 19, count 0 2006.201.04:35:08.28#ibcon#about to read 6, iclass 19, count 0 2006.201.04:35:08.28#ibcon#read 6, iclass 19, count 0 2006.201.04:35:08.28#ibcon#end of sib2, iclass 19, count 0 2006.201.04:35:08.28#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:35:08.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:35:08.28#ibcon#[27=USB\r\n] 2006.201.04:35:08.28#ibcon#*before write, iclass 19, count 0 2006.201.04:35:08.28#ibcon#enter sib2, iclass 19, count 0 2006.201.04:35:08.28#ibcon#flushed, iclass 19, count 0 2006.201.04:35:08.28#ibcon#about to write, iclass 19, count 0 2006.201.04:35:08.28#ibcon#wrote, iclass 19, count 0 2006.201.04:35:08.28#ibcon#about to read 3, iclass 19, count 0 2006.201.04:35:08.31#ibcon#read 3, iclass 19, count 0 2006.201.04:35:08.31#ibcon#about to read 4, iclass 19, count 0 2006.201.04:35:08.31#ibcon#read 4, iclass 19, count 0 2006.201.04:35:08.31#ibcon#about to read 5, iclass 19, count 0 2006.201.04:35:08.31#ibcon#read 5, iclass 19, count 0 2006.201.04:35:08.31#ibcon#about to read 6, iclass 19, count 0 2006.201.04:35:08.31#ibcon#read 6, iclass 19, count 0 2006.201.04:35:08.31#ibcon#end of sib2, iclass 19, count 0 2006.201.04:35:08.31#ibcon#*after write, iclass 19, count 0 2006.201.04:35:08.31#ibcon#*before return 0, iclass 19, count 0 2006.201.04:35:08.31#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:35:08.31#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:35:08.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:35:08.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:35:08.31$vck44/vblo=2,634.99 2006.201.04:35:08.31#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.04:35:08.31#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.04:35:08.31#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:08.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:08.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:08.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:08.31#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:35:08.31#ibcon#first serial, iclass 21, count 0 2006.201.04:35:08.31#ibcon#enter sib2, iclass 21, count 0 2006.201.04:35:08.31#ibcon#flushed, iclass 21, count 0 2006.201.04:35:08.31#ibcon#about to write, iclass 21, count 0 2006.201.04:35:08.31#ibcon#wrote, iclass 21, count 0 2006.201.04:35:08.31#ibcon#about to read 3, iclass 21, count 0 2006.201.04:35:08.33#ibcon#read 3, iclass 21, count 0 2006.201.04:35:08.33#ibcon#about to read 4, iclass 21, count 0 2006.201.04:35:08.33#ibcon#read 4, iclass 21, count 0 2006.201.04:35:08.33#ibcon#about to read 5, iclass 21, count 0 2006.201.04:35:08.33#ibcon#read 5, iclass 21, count 0 2006.201.04:35:08.33#ibcon#about to read 6, iclass 21, count 0 2006.201.04:35:08.33#ibcon#read 6, iclass 21, count 0 2006.201.04:35:08.33#ibcon#end of sib2, iclass 21, count 0 2006.201.04:35:08.33#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:35:08.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:35:08.33#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:35:08.33#ibcon#*before write, iclass 21, count 0 2006.201.04:35:08.33#ibcon#enter sib2, iclass 21, count 0 2006.201.04:35:08.33#ibcon#flushed, iclass 21, count 0 2006.201.04:35:08.33#ibcon#about to write, iclass 21, count 0 2006.201.04:35:08.33#ibcon#wrote, iclass 21, count 0 2006.201.04:35:08.33#ibcon#about to read 3, iclass 21, count 0 2006.201.04:35:08.37#ibcon#read 3, iclass 21, count 0 2006.201.04:35:08.37#ibcon#about to read 4, iclass 21, count 0 2006.201.04:35:08.37#ibcon#read 4, iclass 21, count 0 2006.201.04:35:08.37#ibcon#about to read 5, iclass 21, count 0 2006.201.04:35:08.37#ibcon#read 5, iclass 21, count 0 2006.201.04:35:08.37#ibcon#about to read 6, iclass 21, count 0 2006.201.04:35:08.37#ibcon#read 6, iclass 21, count 0 2006.201.04:35:08.37#ibcon#end of sib2, iclass 21, count 0 2006.201.04:35:08.37#ibcon#*after write, iclass 21, count 0 2006.201.04:35:08.37#ibcon#*before return 0, iclass 21, count 0 2006.201.04:35:08.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:08.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:35:08.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:35:08.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:35:08.37$vck44/vb=2,5 2006.201.04:35:08.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.04:35:08.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.04:35:08.37#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:08.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:08.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:08.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:08.43#ibcon#enter wrdev, iclass 23, count 2 2006.201.04:35:08.43#ibcon#first serial, iclass 23, count 2 2006.201.04:35:08.43#ibcon#enter sib2, iclass 23, count 2 2006.201.04:35:08.43#ibcon#flushed, iclass 23, count 2 2006.201.04:35:08.43#ibcon#about to write, iclass 23, count 2 2006.201.04:35:08.43#ibcon#wrote, iclass 23, count 2 2006.201.04:35:08.43#ibcon#about to read 3, iclass 23, count 2 2006.201.04:35:08.45#ibcon#read 3, iclass 23, count 2 2006.201.04:35:08.45#ibcon#about to read 4, iclass 23, count 2 2006.201.04:35:08.45#ibcon#read 4, iclass 23, count 2 2006.201.04:35:08.45#ibcon#about to read 5, iclass 23, count 2 2006.201.04:35:08.45#ibcon#read 5, iclass 23, count 2 2006.201.04:35:08.45#ibcon#about to read 6, iclass 23, count 2 2006.201.04:35:08.45#ibcon#read 6, iclass 23, count 2 2006.201.04:35:08.45#ibcon#end of sib2, iclass 23, count 2 2006.201.04:35:08.45#ibcon#*mode == 0, iclass 23, count 2 2006.201.04:35:08.45#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.04:35:08.45#ibcon#[27=AT02-05\r\n] 2006.201.04:35:08.45#ibcon#*before write, iclass 23, count 2 2006.201.04:35:08.45#ibcon#enter sib2, iclass 23, count 2 2006.201.04:35:08.45#ibcon#flushed, iclass 23, count 2 2006.201.04:35:08.45#ibcon#about to write, iclass 23, count 2 2006.201.04:35:08.45#ibcon#wrote, iclass 23, count 2 2006.201.04:35:08.45#ibcon#about to read 3, iclass 23, count 2 2006.201.04:35:08.59#ibcon#read 3, iclass 23, count 2 2006.201.04:35:08.59#ibcon#about to read 4, iclass 23, count 2 2006.201.04:35:08.59#ibcon#read 4, iclass 23, count 2 2006.201.04:35:08.59#ibcon#about to read 5, iclass 23, count 2 2006.201.04:35:08.59#ibcon#read 5, iclass 23, count 2 2006.201.04:35:08.59#ibcon#about to read 6, iclass 23, count 2 2006.201.04:35:08.60#ibcon#read 6, iclass 23, count 2 2006.201.04:35:08.60#ibcon#end of sib2, iclass 23, count 2 2006.201.04:35:08.60#ibcon#*after write, iclass 23, count 2 2006.201.04:35:08.60#ibcon#*before return 0, iclass 23, count 2 2006.201.04:35:08.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:08.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:35:08.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.04:35:08.60#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:08.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:08.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:08.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:08.72#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:35:08.72#ibcon#first serial, iclass 23, count 0 2006.201.04:35:08.72#ibcon#enter sib2, iclass 23, count 0 2006.201.04:35:08.72#ibcon#flushed, iclass 23, count 0 2006.201.04:35:08.72#ibcon#about to write, iclass 23, count 0 2006.201.04:35:08.72#ibcon#wrote, iclass 23, count 0 2006.201.04:35:08.72#ibcon#about to read 3, iclass 23, count 0 2006.201.04:35:08.74#ibcon#read 3, iclass 23, count 0 2006.201.04:35:08.74#ibcon#about to read 4, iclass 23, count 0 2006.201.04:35:08.74#ibcon#read 4, iclass 23, count 0 2006.201.04:35:08.74#ibcon#about to read 5, iclass 23, count 0 2006.201.04:35:08.74#ibcon#read 5, iclass 23, count 0 2006.201.04:35:08.74#ibcon#about to read 6, iclass 23, count 0 2006.201.04:35:08.74#ibcon#read 6, iclass 23, count 0 2006.201.04:35:08.74#ibcon#end of sib2, iclass 23, count 0 2006.201.04:35:08.74#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:35:08.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:35:08.74#ibcon#[27=USB\r\n] 2006.201.04:35:08.74#ibcon#*before write, iclass 23, count 0 2006.201.04:35:08.74#ibcon#enter sib2, iclass 23, count 0 2006.201.04:35:08.74#ibcon#flushed, iclass 23, count 0 2006.201.04:35:08.74#ibcon#about to write, iclass 23, count 0 2006.201.04:35:08.74#ibcon#wrote, iclass 23, count 0 2006.201.04:35:08.74#ibcon#about to read 3, iclass 23, count 0 2006.201.04:35:08.77#ibcon#read 3, iclass 23, count 0 2006.201.04:35:08.77#ibcon#about to read 4, iclass 23, count 0 2006.201.04:35:08.77#ibcon#read 4, iclass 23, count 0 2006.201.04:35:08.77#ibcon#about to read 5, iclass 23, count 0 2006.201.04:35:08.77#ibcon#read 5, iclass 23, count 0 2006.201.04:35:08.77#ibcon#about to read 6, iclass 23, count 0 2006.201.04:35:08.77#ibcon#read 6, iclass 23, count 0 2006.201.04:35:08.77#ibcon#end of sib2, iclass 23, count 0 2006.201.04:35:08.77#ibcon#*after write, iclass 23, count 0 2006.201.04:35:08.77#ibcon#*before return 0, iclass 23, count 0 2006.201.04:35:08.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:08.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:35:08.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:35:08.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:35:08.77$vck44/vblo=3,649.99 2006.201.04:35:08.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.04:35:08.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.04:35:08.77#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:08.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:08.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:08.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:08.77#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:35:08.77#ibcon#first serial, iclass 25, count 0 2006.201.04:35:08.77#ibcon#enter sib2, iclass 25, count 0 2006.201.04:35:08.77#ibcon#flushed, iclass 25, count 0 2006.201.04:35:08.77#ibcon#about to write, iclass 25, count 0 2006.201.04:35:08.77#ibcon#wrote, iclass 25, count 0 2006.201.04:35:08.77#ibcon#about to read 3, iclass 25, count 0 2006.201.04:35:08.79#ibcon#read 3, iclass 25, count 0 2006.201.04:35:08.79#ibcon#about to read 4, iclass 25, count 0 2006.201.04:35:08.79#ibcon#read 4, iclass 25, count 0 2006.201.04:35:08.79#ibcon#about to read 5, iclass 25, count 0 2006.201.04:35:08.79#ibcon#read 5, iclass 25, count 0 2006.201.04:35:08.79#ibcon#about to read 6, iclass 25, count 0 2006.201.04:35:08.79#ibcon#read 6, iclass 25, count 0 2006.201.04:35:08.79#ibcon#end of sib2, iclass 25, count 0 2006.201.04:35:08.79#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:35:08.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:35:08.79#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:35:08.79#ibcon#*before write, iclass 25, count 0 2006.201.04:35:08.79#ibcon#enter sib2, iclass 25, count 0 2006.201.04:35:08.79#ibcon#flushed, iclass 25, count 0 2006.201.04:35:08.79#ibcon#about to write, iclass 25, count 0 2006.201.04:35:08.79#ibcon#wrote, iclass 25, count 0 2006.201.04:35:08.79#ibcon#about to read 3, iclass 25, count 0 2006.201.04:35:08.83#ibcon#read 3, iclass 25, count 0 2006.201.04:35:08.83#ibcon#about to read 4, iclass 25, count 0 2006.201.04:35:08.83#ibcon#read 4, iclass 25, count 0 2006.201.04:35:08.83#ibcon#about to read 5, iclass 25, count 0 2006.201.04:35:08.83#ibcon#read 5, iclass 25, count 0 2006.201.04:35:08.83#ibcon#about to read 6, iclass 25, count 0 2006.201.04:35:08.83#ibcon#read 6, iclass 25, count 0 2006.201.04:35:08.83#ibcon#end of sib2, iclass 25, count 0 2006.201.04:35:08.83#ibcon#*after write, iclass 25, count 0 2006.201.04:35:08.83#ibcon#*before return 0, iclass 25, count 0 2006.201.04:35:08.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:08.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:35:08.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:35:08.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:35:08.83$vck44/vb=3,4 2006.201.04:35:08.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.04:35:08.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.04:35:08.83#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:08.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:08.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:08.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:08.89#ibcon#enter wrdev, iclass 27, count 2 2006.201.04:35:08.89#ibcon#first serial, iclass 27, count 2 2006.201.04:35:08.89#ibcon#enter sib2, iclass 27, count 2 2006.201.04:35:08.89#ibcon#flushed, iclass 27, count 2 2006.201.04:35:08.89#ibcon#about to write, iclass 27, count 2 2006.201.04:35:08.89#ibcon#wrote, iclass 27, count 2 2006.201.04:35:08.89#ibcon#about to read 3, iclass 27, count 2 2006.201.04:35:08.91#ibcon#read 3, iclass 27, count 2 2006.201.04:35:08.91#ibcon#about to read 4, iclass 27, count 2 2006.201.04:35:08.91#ibcon#read 4, iclass 27, count 2 2006.201.04:35:08.91#ibcon#about to read 5, iclass 27, count 2 2006.201.04:35:08.91#ibcon#read 5, iclass 27, count 2 2006.201.04:35:08.91#ibcon#about to read 6, iclass 27, count 2 2006.201.04:35:08.91#ibcon#read 6, iclass 27, count 2 2006.201.04:35:08.91#ibcon#end of sib2, iclass 27, count 2 2006.201.04:35:08.91#ibcon#*mode == 0, iclass 27, count 2 2006.201.04:35:08.91#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.04:35:08.91#ibcon#[27=AT03-04\r\n] 2006.201.04:35:08.91#ibcon#*before write, iclass 27, count 2 2006.201.04:35:08.91#ibcon#enter sib2, iclass 27, count 2 2006.201.04:35:08.91#ibcon#flushed, iclass 27, count 2 2006.201.04:35:08.91#ibcon#about to write, iclass 27, count 2 2006.201.04:35:08.91#ibcon#wrote, iclass 27, count 2 2006.201.04:35:08.91#ibcon#about to read 3, iclass 27, count 2 2006.201.04:35:08.94#ibcon#read 3, iclass 27, count 2 2006.201.04:35:08.94#ibcon#about to read 4, iclass 27, count 2 2006.201.04:35:08.94#ibcon#read 4, iclass 27, count 2 2006.201.04:35:08.94#ibcon#about to read 5, iclass 27, count 2 2006.201.04:35:08.94#ibcon#read 5, iclass 27, count 2 2006.201.04:35:08.94#ibcon#about to read 6, iclass 27, count 2 2006.201.04:35:08.94#ibcon#read 6, iclass 27, count 2 2006.201.04:35:08.94#ibcon#end of sib2, iclass 27, count 2 2006.201.04:35:08.94#ibcon#*after write, iclass 27, count 2 2006.201.04:35:08.94#ibcon#*before return 0, iclass 27, count 2 2006.201.04:35:08.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:08.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:35:08.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.04:35:08.94#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:08.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:09.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:09.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:09.06#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:35:09.06#ibcon#first serial, iclass 27, count 0 2006.201.04:35:09.06#ibcon#enter sib2, iclass 27, count 0 2006.201.04:35:09.06#ibcon#flushed, iclass 27, count 0 2006.201.04:35:09.06#ibcon#about to write, iclass 27, count 0 2006.201.04:35:09.06#ibcon#wrote, iclass 27, count 0 2006.201.04:35:09.06#ibcon#about to read 3, iclass 27, count 0 2006.201.04:35:09.08#ibcon#read 3, iclass 27, count 0 2006.201.04:35:09.08#ibcon#about to read 4, iclass 27, count 0 2006.201.04:35:09.08#ibcon#read 4, iclass 27, count 0 2006.201.04:35:09.08#ibcon#about to read 5, iclass 27, count 0 2006.201.04:35:09.08#ibcon#read 5, iclass 27, count 0 2006.201.04:35:09.08#ibcon#about to read 6, iclass 27, count 0 2006.201.04:35:09.08#ibcon#read 6, iclass 27, count 0 2006.201.04:35:09.08#ibcon#end of sib2, iclass 27, count 0 2006.201.04:35:09.08#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:35:09.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:35:09.08#ibcon#[27=USB\r\n] 2006.201.04:35:09.08#ibcon#*before write, iclass 27, count 0 2006.201.04:35:09.08#ibcon#enter sib2, iclass 27, count 0 2006.201.04:35:09.08#ibcon#flushed, iclass 27, count 0 2006.201.04:35:09.08#ibcon#about to write, iclass 27, count 0 2006.201.04:35:09.08#ibcon#wrote, iclass 27, count 0 2006.201.04:35:09.08#ibcon#about to read 3, iclass 27, count 0 2006.201.04:35:09.11#ibcon#read 3, iclass 27, count 0 2006.201.04:35:09.11#ibcon#about to read 4, iclass 27, count 0 2006.201.04:35:09.11#ibcon#read 4, iclass 27, count 0 2006.201.04:35:09.11#ibcon#about to read 5, iclass 27, count 0 2006.201.04:35:09.11#ibcon#read 5, iclass 27, count 0 2006.201.04:35:09.11#ibcon#about to read 6, iclass 27, count 0 2006.201.04:35:09.11#ibcon#read 6, iclass 27, count 0 2006.201.04:35:09.11#ibcon#end of sib2, iclass 27, count 0 2006.201.04:35:09.11#ibcon#*after write, iclass 27, count 0 2006.201.04:35:09.11#ibcon#*before return 0, iclass 27, count 0 2006.201.04:35:09.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:09.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:35:09.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:35:09.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:35:09.11$vck44/vblo=4,679.99 2006.201.04:35:09.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.04:35:09.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.04:35:09.11#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:09.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:09.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:09.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:09.11#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:35:09.11#ibcon#first serial, iclass 29, count 0 2006.201.04:35:09.11#ibcon#enter sib2, iclass 29, count 0 2006.201.04:35:09.11#ibcon#flushed, iclass 29, count 0 2006.201.04:35:09.11#ibcon#about to write, iclass 29, count 0 2006.201.04:35:09.11#ibcon#wrote, iclass 29, count 0 2006.201.04:35:09.11#ibcon#about to read 3, iclass 29, count 0 2006.201.04:35:09.13#ibcon#read 3, iclass 29, count 0 2006.201.04:35:09.13#ibcon#about to read 4, iclass 29, count 0 2006.201.04:35:09.13#ibcon#read 4, iclass 29, count 0 2006.201.04:35:09.13#ibcon#about to read 5, iclass 29, count 0 2006.201.04:35:09.13#ibcon#read 5, iclass 29, count 0 2006.201.04:35:09.13#ibcon#about to read 6, iclass 29, count 0 2006.201.04:35:09.13#ibcon#read 6, iclass 29, count 0 2006.201.04:35:09.13#ibcon#end of sib2, iclass 29, count 0 2006.201.04:35:09.13#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:35:09.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:35:09.13#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:35:09.13#ibcon#*before write, iclass 29, count 0 2006.201.04:35:09.13#ibcon#enter sib2, iclass 29, count 0 2006.201.04:35:09.13#ibcon#flushed, iclass 29, count 0 2006.201.04:35:09.13#ibcon#about to write, iclass 29, count 0 2006.201.04:35:09.13#ibcon#wrote, iclass 29, count 0 2006.201.04:35:09.13#ibcon#about to read 3, iclass 29, count 0 2006.201.04:35:09.17#ibcon#read 3, iclass 29, count 0 2006.201.04:35:09.17#ibcon#about to read 4, iclass 29, count 0 2006.201.04:35:09.17#ibcon#read 4, iclass 29, count 0 2006.201.04:35:09.17#ibcon#about to read 5, iclass 29, count 0 2006.201.04:35:09.17#ibcon#read 5, iclass 29, count 0 2006.201.04:35:09.17#ibcon#about to read 6, iclass 29, count 0 2006.201.04:35:09.17#ibcon#read 6, iclass 29, count 0 2006.201.04:35:09.17#ibcon#end of sib2, iclass 29, count 0 2006.201.04:35:09.17#ibcon#*after write, iclass 29, count 0 2006.201.04:35:09.17#ibcon#*before return 0, iclass 29, count 0 2006.201.04:35:09.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:09.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:35:09.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:35:09.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:35:09.17$vck44/vb=4,5 2006.201.04:35:09.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.04:35:09.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.04:35:09.17#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:09.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:09.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:09.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:09.23#ibcon#enter wrdev, iclass 31, count 2 2006.201.04:35:09.23#ibcon#first serial, iclass 31, count 2 2006.201.04:35:09.23#ibcon#enter sib2, iclass 31, count 2 2006.201.04:35:09.23#ibcon#flushed, iclass 31, count 2 2006.201.04:35:09.23#ibcon#about to write, iclass 31, count 2 2006.201.04:35:09.23#ibcon#wrote, iclass 31, count 2 2006.201.04:35:09.23#ibcon#about to read 3, iclass 31, count 2 2006.201.04:35:09.25#ibcon#read 3, iclass 31, count 2 2006.201.04:35:09.25#ibcon#about to read 4, iclass 31, count 2 2006.201.04:35:09.25#ibcon#read 4, iclass 31, count 2 2006.201.04:35:09.25#ibcon#about to read 5, iclass 31, count 2 2006.201.04:35:09.25#ibcon#read 5, iclass 31, count 2 2006.201.04:35:09.25#ibcon#about to read 6, iclass 31, count 2 2006.201.04:35:09.25#ibcon#read 6, iclass 31, count 2 2006.201.04:35:09.25#ibcon#end of sib2, iclass 31, count 2 2006.201.04:35:09.25#ibcon#*mode == 0, iclass 31, count 2 2006.201.04:35:09.25#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.04:35:09.25#ibcon#[27=AT04-05\r\n] 2006.201.04:35:09.25#ibcon#*before write, iclass 31, count 2 2006.201.04:35:09.25#ibcon#enter sib2, iclass 31, count 2 2006.201.04:35:09.25#ibcon#flushed, iclass 31, count 2 2006.201.04:35:09.25#ibcon#about to write, iclass 31, count 2 2006.201.04:35:09.25#ibcon#wrote, iclass 31, count 2 2006.201.04:35:09.25#ibcon#about to read 3, iclass 31, count 2 2006.201.04:35:09.28#ibcon#read 3, iclass 31, count 2 2006.201.04:35:09.28#ibcon#about to read 4, iclass 31, count 2 2006.201.04:35:09.28#ibcon#read 4, iclass 31, count 2 2006.201.04:35:09.28#ibcon#about to read 5, iclass 31, count 2 2006.201.04:35:09.28#ibcon#read 5, iclass 31, count 2 2006.201.04:35:09.28#ibcon#about to read 6, iclass 31, count 2 2006.201.04:35:09.28#ibcon#read 6, iclass 31, count 2 2006.201.04:35:09.28#ibcon#end of sib2, iclass 31, count 2 2006.201.04:35:09.28#ibcon#*after write, iclass 31, count 2 2006.201.04:35:09.28#ibcon#*before return 0, iclass 31, count 2 2006.201.04:35:09.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:09.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:35:09.28#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.04:35:09.28#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:09.28#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:09.40#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:09.40#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:09.40#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:35:09.40#ibcon#first serial, iclass 31, count 0 2006.201.04:35:09.40#ibcon#enter sib2, iclass 31, count 0 2006.201.04:35:09.40#ibcon#flushed, iclass 31, count 0 2006.201.04:35:09.40#ibcon#about to write, iclass 31, count 0 2006.201.04:35:09.40#ibcon#wrote, iclass 31, count 0 2006.201.04:35:09.40#ibcon#about to read 3, iclass 31, count 0 2006.201.04:35:09.42#ibcon#read 3, iclass 31, count 0 2006.201.04:35:09.42#ibcon#about to read 4, iclass 31, count 0 2006.201.04:35:09.42#ibcon#read 4, iclass 31, count 0 2006.201.04:35:09.42#ibcon#about to read 5, iclass 31, count 0 2006.201.04:35:09.42#ibcon#read 5, iclass 31, count 0 2006.201.04:35:09.42#ibcon#about to read 6, iclass 31, count 0 2006.201.04:35:09.42#ibcon#read 6, iclass 31, count 0 2006.201.04:35:09.42#ibcon#end of sib2, iclass 31, count 0 2006.201.04:35:09.42#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:35:09.42#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:35:09.42#ibcon#[27=USB\r\n] 2006.201.04:35:09.42#ibcon#*before write, iclass 31, count 0 2006.201.04:35:09.42#ibcon#enter sib2, iclass 31, count 0 2006.201.04:35:09.42#ibcon#flushed, iclass 31, count 0 2006.201.04:35:09.42#ibcon#about to write, iclass 31, count 0 2006.201.04:35:09.42#ibcon#wrote, iclass 31, count 0 2006.201.04:35:09.42#ibcon#about to read 3, iclass 31, count 0 2006.201.04:35:09.45#ibcon#read 3, iclass 31, count 0 2006.201.04:35:09.45#ibcon#about to read 4, iclass 31, count 0 2006.201.04:35:09.45#ibcon#read 4, iclass 31, count 0 2006.201.04:35:09.45#ibcon#about to read 5, iclass 31, count 0 2006.201.04:35:09.45#ibcon#read 5, iclass 31, count 0 2006.201.04:35:09.45#ibcon#about to read 6, iclass 31, count 0 2006.201.04:35:09.45#ibcon#read 6, iclass 31, count 0 2006.201.04:35:09.45#ibcon#end of sib2, iclass 31, count 0 2006.201.04:35:09.45#ibcon#*after write, iclass 31, count 0 2006.201.04:35:09.45#ibcon#*before return 0, iclass 31, count 0 2006.201.04:35:09.45#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:09.45#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:35:09.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:35:09.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:35:09.45$vck44/vblo=5,709.99 2006.201.04:35:09.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.04:35:09.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.04:35:09.45#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:09.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:09.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:09.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:09.45#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:35:09.45#ibcon#first serial, iclass 33, count 0 2006.201.04:35:09.45#ibcon#enter sib2, iclass 33, count 0 2006.201.04:35:09.45#ibcon#flushed, iclass 33, count 0 2006.201.04:35:09.45#ibcon#about to write, iclass 33, count 0 2006.201.04:35:09.45#ibcon#wrote, iclass 33, count 0 2006.201.04:35:09.45#ibcon#about to read 3, iclass 33, count 0 2006.201.04:35:09.47#ibcon#read 3, iclass 33, count 0 2006.201.04:35:09.47#ibcon#about to read 4, iclass 33, count 0 2006.201.04:35:09.47#ibcon#read 4, iclass 33, count 0 2006.201.04:35:09.47#ibcon#about to read 5, iclass 33, count 0 2006.201.04:35:09.47#ibcon#read 5, iclass 33, count 0 2006.201.04:35:09.47#ibcon#about to read 6, iclass 33, count 0 2006.201.04:35:09.47#ibcon#read 6, iclass 33, count 0 2006.201.04:35:09.47#ibcon#end of sib2, iclass 33, count 0 2006.201.04:35:09.47#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:35:09.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:35:09.47#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:35:09.47#ibcon#*before write, iclass 33, count 0 2006.201.04:35:09.47#ibcon#enter sib2, iclass 33, count 0 2006.201.04:35:09.47#ibcon#flushed, iclass 33, count 0 2006.201.04:35:09.47#ibcon#about to write, iclass 33, count 0 2006.201.04:35:09.47#ibcon#wrote, iclass 33, count 0 2006.201.04:35:09.47#ibcon#about to read 3, iclass 33, count 0 2006.201.04:35:09.51#ibcon#read 3, iclass 33, count 0 2006.201.04:35:09.51#ibcon#about to read 4, iclass 33, count 0 2006.201.04:35:09.51#ibcon#read 4, iclass 33, count 0 2006.201.04:35:09.51#ibcon#about to read 5, iclass 33, count 0 2006.201.04:35:09.51#ibcon#read 5, iclass 33, count 0 2006.201.04:35:09.51#ibcon#about to read 6, iclass 33, count 0 2006.201.04:35:09.51#ibcon#read 6, iclass 33, count 0 2006.201.04:35:09.51#ibcon#end of sib2, iclass 33, count 0 2006.201.04:35:09.51#ibcon#*after write, iclass 33, count 0 2006.201.04:35:09.51#ibcon#*before return 0, iclass 33, count 0 2006.201.04:35:09.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:09.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:35:09.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:35:09.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:35:09.51$vck44/vb=5,4 2006.201.04:35:09.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.04:35:09.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.04:35:09.51#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:09.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:09.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:09.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:09.57#ibcon#enter wrdev, iclass 35, count 2 2006.201.04:35:09.57#ibcon#first serial, iclass 35, count 2 2006.201.04:35:09.57#ibcon#enter sib2, iclass 35, count 2 2006.201.04:35:09.57#ibcon#flushed, iclass 35, count 2 2006.201.04:35:09.57#ibcon#about to write, iclass 35, count 2 2006.201.04:35:09.57#ibcon#wrote, iclass 35, count 2 2006.201.04:35:09.57#ibcon#about to read 3, iclass 35, count 2 2006.201.04:35:09.59#ibcon#read 3, iclass 35, count 2 2006.201.04:35:09.59#ibcon#about to read 4, iclass 35, count 2 2006.201.04:35:09.59#ibcon#read 4, iclass 35, count 2 2006.201.04:35:09.59#ibcon#about to read 5, iclass 35, count 2 2006.201.04:35:09.59#ibcon#read 5, iclass 35, count 2 2006.201.04:35:09.59#ibcon#about to read 6, iclass 35, count 2 2006.201.04:35:09.59#ibcon#read 6, iclass 35, count 2 2006.201.04:35:09.59#ibcon#end of sib2, iclass 35, count 2 2006.201.04:35:09.59#ibcon#*mode == 0, iclass 35, count 2 2006.201.04:35:09.59#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.04:35:09.59#ibcon#[27=AT05-04\r\n] 2006.201.04:35:09.59#ibcon#*before write, iclass 35, count 2 2006.201.04:35:09.59#ibcon#enter sib2, iclass 35, count 2 2006.201.04:35:09.59#ibcon#flushed, iclass 35, count 2 2006.201.04:35:09.59#ibcon#about to write, iclass 35, count 2 2006.201.04:35:09.59#ibcon#wrote, iclass 35, count 2 2006.201.04:35:09.59#ibcon#about to read 3, iclass 35, count 2 2006.201.04:35:09.64#ibcon#read 3, iclass 35, count 2 2006.201.04:35:09.64#ibcon#about to read 4, iclass 35, count 2 2006.201.04:35:09.65#ibcon#read 4, iclass 35, count 2 2006.201.04:35:09.65#ibcon#about to read 5, iclass 35, count 2 2006.201.04:35:09.65#ibcon#read 5, iclass 35, count 2 2006.201.04:35:09.65#ibcon#about to read 6, iclass 35, count 2 2006.201.04:35:09.65#ibcon#read 6, iclass 35, count 2 2006.201.04:35:09.65#ibcon#end of sib2, iclass 35, count 2 2006.201.04:35:09.65#ibcon#*after write, iclass 35, count 2 2006.201.04:35:09.65#ibcon#*before return 0, iclass 35, count 2 2006.201.04:35:09.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:09.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:35:09.65#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.04:35:09.65#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:09.65#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:09.77#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:09.77#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:09.77#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:35:09.77#ibcon#first serial, iclass 35, count 0 2006.201.04:35:09.77#ibcon#enter sib2, iclass 35, count 0 2006.201.04:35:09.77#ibcon#flushed, iclass 35, count 0 2006.201.04:35:09.77#ibcon#about to write, iclass 35, count 0 2006.201.04:35:09.77#ibcon#wrote, iclass 35, count 0 2006.201.04:35:09.77#ibcon#about to read 3, iclass 35, count 0 2006.201.04:35:09.79#ibcon#read 3, iclass 35, count 0 2006.201.04:35:09.79#ibcon#about to read 4, iclass 35, count 0 2006.201.04:35:09.79#ibcon#read 4, iclass 35, count 0 2006.201.04:35:09.79#ibcon#about to read 5, iclass 35, count 0 2006.201.04:35:09.79#ibcon#read 5, iclass 35, count 0 2006.201.04:35:09.79#ibcon#about to read 6, iclass 35, count 0 2006.201.04:35:09.79#ibcon#read 6, iclass 35, count 0 2006.201.04:35:09.79#ibcon#end of sib2, iclass 35, count 0 2006.201.04:35:09.79#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:35:09.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:35:09.79#ibcon#[27=USB\r\n] 2006.201.04:35:09.79#ibcon#*before write, iclass 35, count 0 2006.201.04:35:09.79#ibcon#enter sib2, iclass 35, count 0 2006.201.04:35:09.79#ibcon#flushed, iclass 35, count 0 2006.201.04:35:09.79#ibcon#about to write, iclass 35, count 0 2006.201.04:35:09.79#ibcon#wrote, iclass 35, count 0 2006.201.04:35:09.79#ibcon#about to read 3, iclass 35, count 0 2006.201.04:35:09.82#ibcon#read 3, iclass 35, count 0 2006.201.04:35:09.82#ibcon#about to read 4, iclass 35, count 0 2006.201.04:35:09.82#ibcon#read 4, iclass 35, count 0 2006.201.04:35:09.82#ibcon#about to read 5, iclass 35, count 0 2006.201.04:35:09.82#ibcon#read 5, iclass 35, count 0 2006.201.04:35:09.82#ibcon#about to read 6, iclass 35, count 0 2006.201.04:35:09.82#ibcon#read 6, iclass 35, count 0 2006.201.04:35:09.82#ibcon#end of sib2, iclass 35, count 0 2006.201.04:35:09.82#ibcon#*after write, iclass 35, count 0 2006.201.04:35:09.82#ibcon#*before return 0, iclass 35, count 0 2006.201.04:35:09.82#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:09.82#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:35:09.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:35:09.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:35:09.82$vck44/vblo=6,719.99 2006.201.04:35:09.82#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.04:35:09.82#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.04:35:09.82#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:09.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:09.82#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:09.82#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:09.82#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:35:09.82#ibcon#first serial, iclass 37, count 0 2006.201.04:35:09.82#ibcon#enter sib2, iclass 37, count 0 2006.201.04:35:09.82#ibcon#flushed, iclass 37, count 0 2006.201.04:35:09.82#ibcon#about to write, iclass 37, count 0 2006.201.04:35:09.82#ibcon#wrote, iclass 37, count 0 2006.201.04:35:09.82#ibcon#about to read 3, iclass 37, count 0 2006.201.04:35:09.84#ibcon#read 3, iclass 37, count 0 2006.201.04:35:09.84#ibcon#about to read 4, iclass 37, count 0 2006.201.04:35:09.84#ibcon#read 4, iclass 37, count 0 2006.201.04:35:09.84#ibcon#about to read 5, iclass 37, count 0 2006.201.04:35:09.84#ibcon#read 5, iclass 37, count 0 2006.201.04:35:09.84#ibcon#about to read 6, iclass 37, count 0 2006.201.04:35:09.84#ibcon#read 6, iclass 37, count 0 2006.201.04:35:09.84#ibcon#end of sib2, iclass 37, count 0 2006.201.04:35:09.84#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:35:09.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:35:09.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:35:09.84#ibcon#*before write, iclass 37, count 0 2006.201.04:35:09.84#ibcon#enter sib2, iclass 37, count 0 2006.201.04:35:09.84#ibcon#flushed, iclass 37, count 0 2006.201.04:35:09.84#ibcon#about to write, iclass 37, count 0 2006.201.04:35:09.84#ibcon#wrote, iclass 37, count 0 2006.201.04:35:09.84#ibcon#about to read 3, iclass 37, count 0 2006.201.04:35:09.88#ibcon#read 3, iclass 37, count 0 2006.201.04:35:09.88#ibcon#about to read 4, iclass 37, count 0 2006.201.04:35:09.88#ibcon#read 4, iclass 37, count 0 2006.201.04:35:09.88#ibcon#about to read 5, iclass 37, count 0 2006.201.04:35:09.88#ibcon#read 5, iclass 37, count 0 2006.201.04:35:09.88#ibcon#about to read 6, iclass 37, count 0 2006.201.04:35:09.88#ibcon#read 6, iclass 37, count 0 2006.201.04:35:09.88#ibcon#end of sib2, iclass 37, count 0 2006.201.04:35:09.88#ibcon#*after write, iclass 37, count 0 2006.201.04:35:09.88#ibcon#*before return 0, iclass 37, count 0 2006.201.04:35:09.88#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:09.88#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:35:09.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:35:09.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:35:09.88$vck44/vb=6,4 2006.201.04:35:09.88#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.04:35:09.88#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.04:35:09.88#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:09.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:09.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:09.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:09.94#ibcon#enter wrdev, iclass 39, count 2 2006.201.04:35:09.94#ibcon#first serial, iclass 39, count 2 2006.201.04:35:09.94#ibcon#enter sib2, iclass 39, count 2 2006.201.04:35:09.94#ibcon#flushed, iclass 39, count 2 2006.201.04:35:09.94#ibcon#about to write, iclass 39, count 2 2006.201.04:35:09.94#ibcon#wrote, iclass 39, count 2 2006.201.04:35:09.94#ibcon#about to read 3, iclass 39, count 2 2006.201.04:35:09.96#ibcon#read 3, iclass 39, count 2 2006.201.04:35:09.96#ibcon#about to read 4, iclass 39, count 2 2006.201.04:35:09.96#ibcon#read 4, iclass 39, count 2 2006.201.04:35:09.96#ibcon#about to read 5, iclass 39, count 2 2006.201.04:35:09.96#ibcon#read 5, iclass 39, count 2 2006.201.04:35:09.96#ibcon#about to read 6, iclass 39, count 2 2006.201.04:35:09.96#ibcon#read 6, iclass 39, count 2 2006.201.04:35:09.96#ibcon#end of sib2, iclass 39, count 2 2006.201.04:35:09.96#ibcon#*mode == 0, iclass 39, count 2 2006.201.04:35:09.96#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.04:35:09.96#ibcon#[27=AT06-04\r\n] 2006.201.04:35:09.96#ibcon#*before write, iclass 39, count 2 2006.201.04:35:09.96#ibcon#enter sib2, iclass 39, count 2 2006.201.04:35:09.96#ibcon#flushed, iclass 39, count 2 2006.201.04:35:09.96#ibcon#about to write, iclass 39, count 2 2006.201.04:35:09.96#ibcon#wrote, iclass 39, count 2 2006.201.04:35:09.96#ibcon#about to read 3, iclass 39, count 2 2006.201.04:35:09.99#ibcon#read 3, iclass 39, count 2 2006.201.04:35:09.99#ibcon#about to read 4, iclass 39, count 2 2006.201.04:35:09.99#ibcon#read 4, iclass 39, count 2 2006.201.04:35:09.99#ibcon#about to read 5, iclass 39, count 2 2006.201.04:35:09.99#ibcon#read 5, iclass 39, count 2 2006.201.04:35:09.99#ibcon#about to read 6, iclass 39, count 2 2006.201.04:35:09.99#ibcon#read 6, iclass 39, count 2 2006.201.04:35:09.99#ibcon#end of sib2, iclass 39, count 2 2006.201.04:35:09.99#ibcon#*after write, iclass 39, count 2 2006.201.04:35:09.99#ibcon#*before return 0, iclass 39, count 2 2006.201.04:35:09.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:09.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:35:09.99#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.04:35:09.99#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:09.99#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:10.11#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:10.11#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:10.11#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:35:10.11#ibcon#first serial, iclass 39, count 0 2006.201.04:35:10.11#ibcon#enter sib2, iclass 39, count 0 2006.201.04:35:10.11#ibcon#flushed, iclass 39, count 0 2006.201.04:35:10.11#ibcon#about to write, iclass 39, count 0 2006.201.04:35:10.11#ibcon#wrote, iclass 39, count 0 2006.201.04:35:10.11#ibcon#about to read 3, iclass 39, count 0 2006.201.04:35:10.13#ibcon#read 3, iclass 39, count 0 2006.201.04:35:10.13#ibcon#about to read 4, iclass 39, count 0 2006.201.04:35:10.13#ibcon#read 4, iclass 39, count 0 2006.201.04:35:10.13#ibcon#about to read 5, iclass 39, count 0 2006.201.04:35:10.13#ibcon#read 5, iclass 39, count 0 2006.201.04:35:10.13#ibcon#about to read 6, iclass 39, count 0 2006.201.04:35:10.13#ibcon#read 6, iclass 39, count 0 2006.201.04:35:10.13#ibcon#end of sib2, iclass 39, count 0 2006.201.04:35:10.13#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:35:10.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:35:10.13#ibcon#[27=USB\r\n] 2006.201.04:35:10.13#ibcon#*before write, iclass 39, count 0 2006.201.04:35:10.13#ibcon#enter sib2, iclass 39, count 0 2006.201.04:35:10.13#ibcon#flushed, iclass 39, count 0 2006.201.04:35:10.13#ibcon#about to write, iclass 39, count 0 2006.201.04:35:10.13#ibcon#wrote, iclass 39, count 0 2006.201.04:35:10.13#ibcon#about to read 3, iclass 39, count 0 2006.201.04:35:10.16#ibcon#read 3, iclass 39, count 0 2006.201.04:35:10.16#ibcon#about to read 4, iclass 39, count 0 2006.201.04:35:10.16#ibcon#read 4, iclass 39, count 0 2006.201.04:35:10.16#ibcon#about to read 5, iclass 39, count 0 2006.201.04:35:10.16#ibcon#read 5, iclass 39, count 0 2006.201.04:35:10.16#ibcon#about to read 6, iclass 39, count 0 2006.201.04:35:10.16#ibcon#read 6, iclass 39, count 0 2006.201.04:35:10.16#ibcon#end of sib2, iclass 39, count 0 2006.201.04:35:10.16#ibcon#*after write, iclass 39, count 0 2006.201.04:35:10.16#ibcon#*before return 0, iclass 39, count 0 2006.201.04:35:10.16#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:10.16#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:35:10.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:35:10.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:35:10.16$vck44/vblo=7,734.99 2006.201.04:35:10.16#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.04:35:10.16#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.04:35:10.16#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:10.16#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:10.16#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:10.16#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:10.16#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:35:10.16#ibcon#first serial, iclass 2, count 0 2006.201.04:35:10.16#ibcon#enter sib2, iclass 2, count 0 2006.201.04:35:10.16#ibcon#flushed, iclass 2, count 0 2006.201.04:35:10.16#ibcon#about to write, iclass 2, count 0 2006.201.04:35:10.16#ibcon#wrote, iclass 2, count 0 2006.201.04:35:10.16#ibcon#about to read 3, iclass 2, count 0 2006.201.04:35:10.18#ibcon#read 3, iclass 2, count 0 2006.201.04:35:10.18#ibcon#about to read 4, iclass 2, count 0 2006.201.04:35:10.18#ibcon#read 4, iclass 2, count 0 2006.201.04:35:10.18#ibcon#about to read 5, iclass 2, count 0 2006.201.04:35:10.18#ibcon#read 5, iclass 2, count 0 2006.201.04:35:10.18#ibcon#about to read 6, iclass 2, count 0 2006.201.04:35:10.18#ibcon#read 6, iclass 2, count 0 2006.201.04:35:10.18#ibcon#end of sib2, iclass 2, count 0 2006.201.04:35:10.18#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:35:10.18#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:35:10.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:35:10.18#ibcon#*before write, iclass 2, count 0 2006.201.04:35:10.18#ibcon#enter sib2, iclass 2, count 0 2006.201.04:35:10.18#ibcon#flushed, iclass 2, count 0 2006.201.04:35:10.18#ibcon#about to write, iclass 2, count 0 2006.201.04:35:10.18#ibcon#wrote, iclass 2, count 0 2006.201.04:35:10.18#ibcon#about to read 3, iclass 2, count 0 2006.201.04:35:10.22#ibcon#read 3, iclass 2, count 0 2006.201.04:35:10.22#ibcon#about to read 4, iclass 2, count 0 2006.201.04:35:10.22#ibcon#read 4, iclass 2, count 0 2006.201.04:35:10.22#ibcon#about to read 5, iclass 2, count 0 2006.201.04:35:10.22#ibcon#read 5, iclass 2, count 0 2006.201.04:35:10.22#ibcon#about to read 6, iclass 2, count 0 2006.201.04:35:10.22#ibcon#read 6, iclass 2, count 0 2006.201.04:35:10.22#ibcon#end of sib2, iclass 2, count 0 2006.201.04:35:10.22#ibcon#*after write, iclass 2, count 0 2006.201.04:35:10.22#ibcon#*before return 0, iclass 2, count 0 2006.201.04:35:10.22#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:10.22#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:35:10.22#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:35:10.22#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:35:10.22$vck44/vb=7,4 2006.201.04:35:10.22#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.04:35:10.22#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.04:35:10.22#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:10.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:10.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:10.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:10.28#ibcon#enter wrdev, iclass 5, count 2 2006.201.04:35:10.28#ibcon#first serial, iclass 5, count 2 2006.201.04:35:10.28#ibcon#enter sib2, iclass 5, count 2 2006.201.04:35:10.28#ibcon#flushed, iclass 5, count 2 2006.201.04:35:10.28#ibcon#about to write, iclass 5, count 2 2006.201.04:35:10.28#ibcon#wrote, iclass 5, count 2 2006.201.04:35:10.28#ibcon#about to read 3, iclass 5, count 2 2006.201.04:35:10.30#ibcon#read 3, iclass 5, count 2 2006.201.04:35:10.30#ibcon#about to read 4, iclass 5, count 2 2006.201.04:35:10.30#ibcon#read 4, iclass 5, count 2 2006.201.04:35:10.30#ibcon#about to read 5, iclass 5, count 2 2006.201.04:35:10.30#ibcon#read 5, iclass 5, count 2 2006.201.04:35:10.30#ibcon#about to read 6, iclass 5, count 2 2006.201.04:35:10.30#ibcon#read 6, iclass 5, count 2 2006.201.04:35:10.30#ibcon#end of sib2, iclass 5, count 2 2006.201.04:35:10.30#ibcon#*mode == 0, iclass 5, count 2 2006.201.04:35:10.30#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.04:35:10.30#ibcon#[27=AT07-04\r\n] 2006.201.04:35:10.30#ibcon#*before write, iclass 5, count 2 2006.201.04:35:10.30#ibcon#enter sib2, iclass 5, count 2 2006.201.04:35:10.30#ibcon#flushed, iclass 5, count 2 2006.201.04:35:10.30#ibcon#about to write, iclass 5, count 2 2006.201.04:35:10.30#ibcon#wrote, iclass 5, count 2 2006.201.04:35:10.30#ibcon#about to read 3, iclass 5, count 2 2006.201.04:35:10.33#ibcon#read 3, iclass 5, count 2 2006.201.04:35:10.33#ibcon#about to read 4, iclass 5, count 2 2006.201.04:35:10.33#ibcon#read 4, iclass 5, count 2 2006.201.04:35:10.33#ibcon#about to read 5, iclass 5, count 2 2006.201.04:35:10.33#ibcon#read 5, iclass 5, count 2 2006.201.04:35:10.33#ibcon#about to read 6, iclass 5, count 2 2006.201.04:35:10.33#ibcon#read 6, iclass 5, count 2 2006.201.04:35:10.33#ibcon#end of sib2, iclass 5, count 2 2006.201.04:35:10.33#ibcon#*after write, iclass 5, count 2 2006.201.04:35:10.33#ibcon#*before return 0, iclass 5, count 2 2006.201.04:35:10.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:10.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:35:10.33#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.04:35:10.33#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:10.33#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:10.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:10.45#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:10.45#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:35:10.45#ibcon#first serial, iclass 5, count 0 2006.201.04:35:10.45#ibcon#enter sib2, iclass 5, count 0 2006.201.04:35:10.45#ibcon#flushed, iclass 5, count 0 2006.201.04:35:10.45#ibcon#about to write, iclass 5, count 0 2006.201.04:35:10.45#ibcon#wrote, iclass 5, count 0 2006.201.04:35:10.45#ibcon#about to read 3, iclass 5, count 0 2006.201.04:35:10.47#ibcon#read 3, iclass 5, count 0 2006.201.04:35:10.47#ibcon#about to read 4, iclass 5, count 0 2006.201.04:35:10.47#ibcon#read 4, iclass 5, count 0 2006.201.04:35:10.47#ibcon#about to read 5, iclass 5, count 0 2006.201.04:35:10.47#ibcon#read 5, iclass 5, count 0 2006.201.04:35:10.47#ibcon#about to read 6, iclass 5, count 0 2006.201.04:35:10.47#ibcon#read 6, iclass 5, count 0 2006.201.04:35:10.47#ibcon#end of sib2, iclass 5, count 0 2006.201.04:35:10.47#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:35:10.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:35:10.47#ibcon#[27=USB\r\n] 2006.201.04:35:10.47#ibcon#*before write, iclass 5, count 0 2006.201.04:35:10.47#ibcon#enter sib2, iclass 5, count 0 2006.201.04:35:10.47#ibcon#flushed, iclass 5, count 0 2006.201.04:35:10.47#ibcon#about to write, iclass 5, count 0 2006.201.04:35:10.47#ibcon#wrote, iclass 5, count 0 2006.201.04:35:10.47#ibcon#about to read 3, iclass 5, count 0 2006.201.04:35:10.50#ibcon#read 3, iclass 5, count 0 2006.201.04:35:10.50#ibcon#about to read 4, iclass 5, count 0 2006.201.04:35:10.50#ibcon#read 4, iclass 5, count 0 2006.201.04:35:10.50#ibcon#about to read 5, iclass 5, count 0 2006.201.04:35:10.50#ibcon#read 5, iclass 5, count 0 2006.201.04:35:10.50#ibcon#about to read 6, iclass 5, count 0 2006.201.04:35:10.50#ibcon#read 6, iclass 5, count 0 2006.201.04:35:10.50#ibcon#end of sib2, iclass 5, count 0 2006.201.04:35:10.50#ibcon#*after write, iclass 5, count 0 2006.201.04:35:10.50#ibcon#*before return 0, iclass 5, count 0 2006.201.04:35:10.50#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:10.50#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:35:10.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:35:10.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:35:10.50$vck44/vblo=8,744.99 2006.201.04:35:10.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.04:35:10.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.04:35:10.50#ibcon#ireg 17 cls_cnt 0 2006.201.04:35:10.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:10.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:10.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:10.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:35:10.50#ibcon#first serial, iclass 7, count 0 2006.201.04:35:10.50#ibcon#enter sib2, iclass 7, count 0 2006.201.04:35:10.50#ibcon#flushed, iclass 7, count 0 2006.201.04:35:10.50#ibcon#about to write, iclass 7, count 0 2006.201.04:35:10.50#ibcon#wrote, iclass 7, count 0 2006.201.04:35:10.50#ibcon#about to read 3, iclass 7, count 0 2006.201.04:35:10.52#ibcon#read 3, iclass 7, count 0 2006.201.04:35:10.52#ibcon#about to read 4, iclass 7, count 0 2006.201.04:35:10.52#ibcon#read 4, iclass 7, count 0 2006.201.04:35:10.52#ibcon#about to read 5, iclass 7, count 0 2006.201.04:35:10.52#ibcon#read 5, iclass 7, count 0 2006.201.04:35:10.52#ibcon#about to read 6, iclass 7, count 0 2006.201.04:35:10.52#ibcon#read 6, iclass 7, count 0 2006.201.04:35:10.52#ibcon#end of sib2, iclass 7, count 0 2006.201.04:35:10.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:35:10.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:35:10.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:35:10.52#ibcon#*before write, iclass 7, count 0 2006.201.04:35:10.52#ibcon#enter sib2, iclass 7, count 0 2006.201.04:35:10.52#ibcon#flushed, iclass 7, count 0 2006.201.04:35:10.52#ibcon#about to write, iclass 7, count 0 2006.201.04:35:10.52#ibcon#wrote, iclass 7, count 0 2006.201.04:35:10.52#ibcon#about to read 3, iclass 7, count 0 2006.201.04:35:10.56#ibcon#read 3, iclass 7, count 0 2006.201.04:35:10.56#ibcon#about to read 4, iclass 7, count 0 2006.201.04:35:10.56#ibcon#read 4, iclass 7, count 0 2006.201.04:35:10.56#ibcon#about to read 5, iclass 7, count 0 2006.201.04:35:10.56#ibcon#read 5, iclass 7, count 0 2006.201.04:35:10.56#ibcon#about to read 6, iclass 7, count 0 2006.201.04:35:10.56#ibcon#read 6, iclass 7, count 0 2006.201.04:35:10.56#ibcon#end of sib2, iclass 7, count 0 2006.201.04:35:10.56#ibcon#*after write, iclass 7, count 0 2006.201.04:35:10.56#ibcon#*before return 0, iclass 7, count 0 2006.201.04:35:10.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:10.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:35:10.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:35:10.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:35:10.56$vck44/vb=8,4 2006.201.04:35:10.56#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.04:35:10.56#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.04:35:10.56#ibcon#ireg 11 cls_cnt 2 2006.201.04:35:10.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:10.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:10.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:10.62#ibcon#enter wrdev, iclass 11, count 2 2006.201.04:35:10.62#ibcon#first serial, iclass 11, count 2 2006.201.04:35:10.62#ibcon#enter sib2, iclass 11, count 2 2006.201.04:35:10.62#ibcon#flushed, iclass 11, count 2 2006.201.04:35:10.62#ibcon#about to write, iclass 11, count 2 2006.201.04:35:10.62#ibcon#wrote, iclass 11, count 2 2006.201.04:35:10.62#ibcon#about to read 3, iclass 11, count 2 2006.201.04:35:10.64#ibcon#read 3, iclass 11, count 2 2006.201.04:35:10.64#ibcon#about to read 4, iclass 11, count 2 2006.201.04:35:10.64#ibcon#read 4, iclass 11, count 2 2006.201.04:35:10.64#ibcon#about to read 5, iclass 11, count 2 2006.201.04:35:10.64#ibcon#read 5, iclass 11, count 2 2006.201.04:35:10.64#ibcon#about to read 6, iclass 11, count 2 2006.201.04:35:10.64#ibcon#read 6, iclass 11, count 2 2006.201.04:35:10.64#ibcon#end of sib2, iclass 11, count 2 2006.201.04:35:10.64#ibcon#*mode == 0, iclass 11, count 2 2006.201.04:35:10.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.04:35:10.64#ibcon#[27=AT08-04\r\n] 2006.201.04:35:10.64#ibcon#*before write, iclass 11, count 2 2006.201.04:35:10.64#ibcon#enter sib2, iclass 11, count 2 2006.201.04:35:10.64#ibcon#flushed, iclass 11, count 2 2006.201.04:35:10.64#ibcon#about to write, iclass 11, count 2 2006.201.04:35:10.64#ibcon#wrote, iclass 11, count 2 2006.201.04:35:10.64#ibcon#about to read 3, iclass 11, count 2 2006.201.04:35:10.67#ibcon#read 3, iclass 11, count 2 2006.201.04:35:10.67#ibcon#about to read 4, iclass 11, count 2 2006.201.04:35:10.67#ibcon#read 4, iclass 11, count 2 2006.201.04:35:10.71#ibcon#about to read 5, iclass 11, count 2 2006.201.04:35:10.71#ibcon#read 5, iclass 11, count 2 2006.201.04:35:10.71#ibcon#about to read 6, iclass 11, count 2 2006.201.04:35:10.71#ibcon#read 6, iclass 11, count 2 2006.201.04:35:10.71#ibcon#end of sib2, iclass 11, count 2 2006.201.04:35:10.71#ibcon#*after write, iclass 11, count 2 2006.201.04:35:10.71#ibcon#*before return 0, iclass 11, count 2 2006.201.04:35:10.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:10.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:35:10.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.04:35:10.71#ibcon#ireg 7 cls_cnt 0 2006.201.04:35:10.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:10.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:10.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:10.83#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:35:10.83#ibcon#first serial, iclass 11, count 0 2006.201.04:35:10.83#ibcon#enter sib2, iclass 11, count 0 2006.201.04:35:10.83#ibcon#flushed, iclass 11, count 0 2006.201.04:35:10.83#ibcon#about to write, iclass 11, count 0 2006.201.04:35:10.83#ibcon#wrote, iclass 11, count 0 2006.201.04:35:10.83#ibcon#about to read 3, iclass 11, count 0 2006.201.04:35:10.85#ibcon#read 3, iclass 11, count 0 2006.201.04:35:10.85#ibcon#about to read 4, iclass 11, count 0 2006.201.04:35:10.85#ibcon#read 4, iclass 11, count 0 2006.201.04:35:10.85#ibcon#about to read 5, iclass 11, count 0 2006.201.04:35:10.85#ibcon#read 5, iclass 11, count 0 2006.201.04:35:10.85#ibcon#about to read 6, iclass 11, count 0 2006.201.04:35:10.85#ibcon#read 6, iclass 11, count 0 2006.201.04:35:10.85#ibcon#end of sib2, iclass 11, count 0 2006.201.04:35:10.85#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:35:10.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:35:10.85#ibcon#[27=USB\r\n] 2006.201.04:35:10.85#ibcon#*before write, iclass 11, count 0 2006.201.04:35:10.85#ibcon#enter sib2, iclass 11, count 0 2006.201.04:35:10.85#ibcon#flushed, iclass 11, count 0 2006.201.04:35:10.85#ibcon#about to write, iclass 11, count 0 2006.201.04:35:10.85#ibcon#wrote, iclass 11, count 0 2006.201.04:35:10.85#ibcon#about to read 3, iclass 11, count 0 2006.201.04:35:10.88#ibcon#read 3, iclass 11, count 0 2006.201.04:35:10.88#ibcon#about to read 4, iclass 11, count 0 2006.201.04:35:10.88#ibcon#read 4, iclass 11, count 0 2006.201.04:35:10.88#ibcon#about to read 5, iclass 11, count 0 2006.201.04:35:10.88#ibcon#read 5, iclass 11, count 0 2006.201.04:35:10.88#ibcon#about to read 6, iclass 11, count 0 2006.201.04:35:10.88#ibcon#read 6, iclass 11, count 0 2006.201.04:35:10.88#ibcon#end of sib2, iclass 11, count 0 2006.201.04:35:10.88#ibcon#*after write, iclass 11, count 0 2006.201.04:35:10.88#ibcon#*before return 0, iclass 11, count 0 2006.201.04:35:10.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:10.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:35:10.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:35:10.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:35:10.88$vck44/vabw=wide 2006.201.04:35:10.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.04:35:10.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.04:35:10.88#ibcon#ireg 8 cls_cnt 0 2006.201.04:35:10.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:10.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:10.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:10.88#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:35:10.88#ibcon#first serial, iclass 13, count 0 2006.201.04:35:10.88#ibcon#enter sib2, iclass 13, count 0 2006.201.04:35:10.88#ibcon#flushed, iclass 13, count 0 2006.201.04:35:10.88#ibcon#about to write, iclass 13, count 0 2006.201.04:35:10.88#ibcon#wrote, iclass 13, count 0 2006.201.04:35:10.88#ibcon#about to read 3, iclass 13, count 0 2006.201.04:35:10.90#ibcon#read 3, iclass 13, count 0 2006.201.04:35:10.90#ibcon#about to read 4, iclass 13, count 0 2006.201.04:35:10.90#ibcon#read 4, iclass 13, count 0 2006.201.04:35:10.90#ibcon#about to read 5, iclass 13, count 0 2006.201.04:35:10.90#ibcon#read 5, iclass 13, count 0 2006.201.04:35:10.90#ibcon#about to read 6, iclass 13, count 0 2006.201.04:35:10.90#ibcon#read 6, iclass 13, count 0 2006.201.04:35:10.90#ibcon#end of sib2, iclass 13, count 0 2006.201.04:35:10.90#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:35:10.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:35:10.90#ibcon#[25=BW32\r\n] 2006.201.04:35:10.90#ibcon#*before write, iclass 13, count 0 2006.201.04:35:10.90#ibcon#enter sib2, iclass 13, count 0 2006.201.04:35:10.90#ibcon#flushed, iclass 13, count 0 2006.201.04:35:10.90#ibcon#about to write, iclass 13, count 0 2006.201.04:35:10.90#ibcon#wrote, iclass 13, count 0 2006.201.04:35:10.90#ibcon#about to read 3, iclass 13, count 0 2006.201.04:35:10.93#ibcon#read 3, iclass 13, count 0 2006.201.04:35:10.93#ibcon#about to read 4, iclass 13, count 0 2006.201.04:35:10.93#ibcon#read 4, iclass 13, count 0 2006.201.04:35:10.93#ibcon#about to read 5, iclass 13, count 0 2006.201.04:35:10.93#ibcon#read 5, iclass 13, count 0 2006.201.04:35:10.93#ibcon#about to read 6, iclass 13, count 0 2006.201.04:35:10.93#ibcon#read 6, iclass 13, count 0 2006.201.04:35:10.93#ibcon#end of sib2, iclass 13, count 0 2006.201.04:35:10.93#ibcon#*after write, iclass 13, count 0 2006.201.04:35:10.93#ibcon#*before return 0, iclass 13, count 0 2006.201.04:35:10.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:10.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:35:10.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:35:10.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:35:10.93$vck44/vbbw=wide 2006.201.04:35:10.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.04:35:10.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.04:35:10.93#ibcon#ireg 8 cls_cnt 0 2006.201.04:35:10.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:35:11.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:35:11.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:35:11.00#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:35:11.00#ibcon#first serial, iclass 15, count 0 2006.201.04:35:11.00#ibcon#enter sib2, iclass 15, count 0 2006.201.04:35:11.00#ibcon#flushed, iclass 15, count 0 2006.201.04:35:11.00#ibcon#about to write, iclass 15, count 0 2006.201.04:35:11.00#ibcon#wrote, iclass 15, count 0 2006.201.04:35:11.00#ibcon#about to read 3, iclass 15, count 0 2006.201.04:35:11.02#ibcon#read 3, iclass 15, count 0 2006.201.04:35:11.02#ibcon#about to read 4, iclass 15, count 0 2006.201.04:35:11.02#ibcon#read 4, iclass 15, count 0 2006.201.04:35:11.02#ibcon#about to read 5, iclass 15, count 0 2006.201.04:35:11.02#ibcon#read 5, iclass 15, count 0 2006.201.04:35:11.02#ibcon#about to read 6, iclass 15, count 0 2006.201.04:35:11.02#ibcon#read 6, iclass 15, count 0 2006.201.04:35:11.02#ibcon#end of sib2, iclass 15, count 0 2006.201.04:35:11.02#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:35:11.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:35:11.02#ibcon#[27=BW32\r\n] 2006.201.04:35:11.02#ibcon#*before write, iclass 15, count 0 2006.201.04:35:11.02#ibcon#enter sib2, iclass 15, count 0 2006.201.04:35:11.02#ibcon#flushed, iclass 15, count 0 2006.201.04:35:11.02#ibcon#about to write, iclass 15, count 0 2006.201.04:35:11.02#ibcon#wrote, iclass 15, count 0 2006.201.04:35:11.02#ibcon#about to read 3, iclass 15, count 0 2006.201.04:35:11.05#ibcon#read 3, iclass 15, count 0 2006.201.04:35:11.05#ibcon#about to read 4, iclass 15, count 0 2006.201.04:35:11.05#ibcon#read 4, iclass 15, count 0 2006.201.04:35:11.05#ibcon#about to read 5, iclass 15, count 0 2006.201.04:35:11.05#ibcon#read 5, iclass 15, count 0 2006.201.04:35:11.05#ibcon#about to read 6, iclass 15, count 0 2006.201.04:35:11.05#ibcon#read 6, iclass 15, count 0 2006.201.04:35:11.05#ibcon#end of sib2, iclass 15, count 0 2006.201.04:35:11.05#ibcon#*after write, iclass 15, count 0 2006.201.04:35:11.05#ibcon#*before return 0, iclass 15, count 0 2006.201.04:35:11.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:35:11.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:35:11.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:35:11.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:35:11.05$setupk4/ifdk4 2006.201.04:35:11.05$ifdk4/lo= 2006.201.04:35:11.05$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:35:11.05$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:35:11.05$ifdk4/patch= 2006.201.04:35:11.05$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:35:11.05$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:35:11.05$setupk4/!*+20s 2006.201.04:35:11.48#abcon#<5=/04 2.9 5.2 22.99 911003.9\r\n> 2006.201.04:35:11.50#abcon#{5=INTERFACE CLEAR} 2006.201.04:35:11.56#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:35:21.14#trakl#Source acquired 2006.201.04:35:21.65#abcon#<5=/04 2.9 5.2 22.99 911003.9\r\n> 2006.201.04:35:21.67#abcon#{5=INTERFACE CLEAR} 2006.201.04:35:21.73#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:35:22.14#flagr#flagr/antenna,acquired 2006.201.04:35:25.23$setupk4/"tpicd 2006.201.04:35:25.23$setupk4/echo=off 2006.201.04:35:25.23$setupk4/xlog=off 2006.201.04:35:25.23:!2006.201.04:35:42 2006.201.04:35:42.00:preob 2006.201.04:35:42.14/onsource/TRACKING 2006.201.04:35:42.14:!2006.201.04:35:52 2006.201.04:35:52.00:"tape 2006.201.04:35:52.00:"st=record 2006.201.04:35:52.00:data_valid=on 2006.201.04:35:52.00:midob 2006.201.04:35:52.14/onsource/TRACKING 2006.201.04:35:52.14/wx/22.99,1003.9,91 2006.201.04:35:52.35/cable/+6.4667E-03 2006.201.04:35:53.44/va/01,08,usb,yes,28,30 2006.201.04:35:53.44/va/02,07,usb,yes,30,31 2006.201.04:35:53.44/va/03,08,usb,yes,27,28 2006.201.04:35:53.44/va/04,07,usb,yes,31,33 2006.201.04:35:53.44/va/05,04,usb,yes,27,28 2006.201.04:35:53.44/va/06,05,usb,yes,27,27 2006.201.04:35:53.44/va/07,05,usb,yes,27,28 2006.201.04:35:53.44/va/08,04,usb,yes,26,32 2006.201.04:35:53.67/valo/01,524.99,yes,locked 2006.201.04:35:53.67/valo/02,534.99,yes,locked 2006.201.04:35:53.67/valo/03,564.99,yes,locked 2006.201.04:35:53.67/valo/04,624.99,yes,locked 2006.201.04:35:53.67/valo/05,734.99,yes,locked 2006.201.04:35:53.67/valo/06,814.99,yes,locked 2006.201.04:35:53.67/valo/07,864.99,yes,locked 2006.201.04:35:53.67/valo/08,884.99,yes,locked 2006.201.04:35:54.76/vb/01,04,usb,yes,28,26 2006.201.04:35:54.76/vb/02,05,usb,yes,27,26 2006.201.04:35:54.76/vb/03,04,usb,yes,27,30 2006.201.04:35:54.76/vb/04,05,usb,yes,28,27 2006.201.04:35:54.76/vb/05,04,usb,yes,24,27 2006.201.04:35:54.76/vb/06,04,usb,yes,29,25 2006.201.04:35:54.76/vb/07,04,usb,yes,28,28 2006.201.04:35:54.76/vb/08,04,usb,yes,26,29 2006.201.04:35:55.00/vblo/01,629.99,yes,locked 2006.201.04:35:55.00/vblo/02,634.99,yes,locked 2006.201.04:35:55.00/vblo/03,649.99,yes,locked 2006.201.04:35:55.00/vblo/04,679.99,yes,locked 2006.201.04:35:55.00/vblo/05,709.99,yes,locked 2006.201.04:35:55.00/vblo/06,719.99,yes,locked 2006.201.04:35:55.00/vblo/07,734.99,yes,locked 2006.201.04:35:55.00/vblo/08,744.99,yes,locked 2006.201.04:35:55.15/vabw/8 2006.201.04:35:55.30/vbbw/8 2006.201.04:35:55.39/xfe/off,on,15.0 2006.201.04:35:55.77/ifatt/23,28,28,28 2006.201.04:35:56.04/fmout-gps/S +4.55E-07 2006.201.04:35:56.07:!2006.201.04:42:02 2006.201.04:42:02.00:data_valid=off 2006.201.04:42:02.00:"et 2006.201.04:42:02.00:!+3s 2006.201.04:42:05.01:"tape 2006.201.04:42:05.01:postob 2006.201.04:42:05.08/cable/+6.4657E-03 2006.201.04:42:05.08/wx/23.00,1004.1,90 2006.201.04:42:05.14/fmout-gps/S +4.55E-07 2006.201.04:42:05.14:scan_name=201-0448,jd0607,60 2006.201.04:42:05.14:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.201.04:42:07.14#flagr#flagr/antenna,new-source 2006.201.04:42:07.14:checkk5 2006.201.04:42:07.57/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:42:07.97/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:42:08.40/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:42:08.78/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:42:09.17/chk_obsdata//k5ts1/T2010435??a.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.201.04:42:09.56/chk_obsdata//k5ts2/T2010435??b.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.201.04:42:09.98/chk_obsdata//k5ts3/T2010435??c.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.201.04:42:10.37/chk_obsdata//k5ts4/T2010435??d.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.201.04:42:11.09/k5log//k5ts1_log_newline 2006.201.04:42:11.81/k5log//k5ts2_log_newline 2006.201.04:42:12.52/k5log//k5ts3_log_newline 2006.201.04:42:13.24/k5log//k5ts4_log_newline 2006.201.04:42:13.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:42:13.26:setupk4=1 2006.201.04:42:13.26$setupk4/echo=on 2006.201.04:42:13.26$setupk4/pcalon 2006.201.04:42:13.26$pcalon/"no phase cal control is implemented here 2006.201.04:42:13.26$setupk4/"tpicd=stop 2006.201.04:42:13.26$setupk4/"rec=synch_on 2006.201.04:42:13.26$setupk4/"rec_mode=128 2006.201.04:42:13.26$setupk4/!* 2006.201.04:42:13.26$setupk4/recpk4 2006.201.04:42:13.26$recpk4/recpatch= 2006.201.04:42:13.27$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:42:13.27$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:42:13.27$setupk4/vck44 2006.201.04:42:13.27$vck44/valo=1,524.99 2006.201.04:42:13.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.04:42:13.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.04:42:13.27#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:13.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:13.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:13.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:13.27#ibcon#enter wrdev, iclass 6, count 0 2006.201.04:42:13.27#ibcon#first serial, iclass 6, count 0 2006.201.04:42:13.27#ibcon#enter sib2, iclass 6, count 0 2006.201.04:42:13.27#ibcon#flushed, iclass 6, count 0 2006.201.04:42:13.27#ibcon#about to write, iclass 6, count 0 2006.201.04:42:13.27#ibcon#wrote, iclass 6, count 0 2006.201.04:42:13.27#ibcon#about to read 3, iclass 6, count 0 2006.201.04:42:13.29#ibcon#read 3, iclass 6, count 0 2006.201.04:42:13.29#ibcon#about to read 4, iclass 6, count 0 2006.201.04:42:13.29#ibcon#read 4, iclass 6, count 0 2006.201.04:42:13.29#ibcon#about to read 5, iclass 6, count 0 2006.201.04:42:13.29#ibcon#read 5, iclass 6, count 0 2006.201.04:42:13.29#ibcon#about to read 6, iclass 6, count 0 2006.201.04:42:13.29#ibcon#read 6, iclass 6, count 0 2006.201.04:42:13.29#ibcon#end of sib2, iclass 6, count 0 2006.201.04:42:13.29#ibcon#*mode == 0, iclass 6, count 0 2006.201.04:42:13.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.04:42:13.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:42:13.29#ibcon#*before write, iclass 6, count 0 2006.201.04:42:13.29#ibcon#enter sib2, iclass 6, count 0 2006.201.04:42:13.29#ibcon#flushed, iclass 6, count 0 2006.201.04:42:13.29#ibcon#about to write, iclass 6, count 0 2006.201.04:42:13.29#ibcon#wrote, iclass 6, count 0 2006.201.04:42:13.29#ibcon#about to read 3, iclass 6, count 0 2006.201.04:42:13.34#ibcon#read 3, iclass 6, count 0 2006.201.04:42:13.34#ibcon#about to read 4, iclass 6, count 0 2006.201.04:42:13.34#ibcon#read 4, iclass 6, count 0 2006.201.04:42:13.34#ibcon#about to read 5, iclass 6, count 0 2006.201.04:42:13.34#ibcon#read 5, iclass 6, count 0 2006.201.04:42:13.34#ibcon#about to read 6, iclass 6, count 0 2006.201.04:42:13.34#ibcon#read 6, iclass 6, count 0 2006.201.04:42:13.34#ibcon#end of sib2, iclass 6, count 0 2006.201.04:42:13.34#ibcon#*after write, iclass 6, count 0 2006.201.04:42:13.34#ibcon#*before return 0, iclass 6, count 0 2006.201.04:42:13.34#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:13.34#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:13.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.04:42:13.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.04:42:13.34$vck44/va=1,8 2006.201.04:42:13.34#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.04:42:13.34#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.04:42:13.34#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:13.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:13.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:13.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:13.34#ibcon#enter wrdev, iclass 10, count 2 2006.201.04:42:13.34#ibcon#first serial, iclass 10, count 2 2006.201.04:42:13.34#ibcon#enter sib2, iclass 10, count 2 2006.201.04:42:13.34#ibcon#flushed, iclass 10, count 2 2006.201.04:42:13.34#ibcon#about to write, iclass 10, count 2 2006.201.04:42:13.34#ibcon#wrote, iclass 10, count 2 2006.201.04:42:13.34#ibcon#about to read 3, iclass 10, count 2 2006.201.04:42:13.36#ibcon#read 3, iclass 10, count 2 2006.201.04:42:13.36#ibcon#about to read 4, iclass 10, count 2 2006.201.04:42:13.36#ibcon#read 4, iclass 10, count 2 2006.201.04:42:13.36#ibcon#about to read 5, iclass 10, count 2 2006.201.04:42:13.36#ibcon#read 5, iclass 10, count 2 2006.201.04:42:13.36#ibcon#about to read 6, iclass 10, count 2 2006.201.04:42:13.36#ibcon#read 6, iclass 10, count 2 2006.201.04:42:13.36#ibcon#end of sib2, iclass 10, count 2 2006.201.04:42:13.36#ibcon#*mode == 0, iclass 10, count 2 2006.201.04:42:13.36#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.04:42:13.36#ibcon#[25=AT01-08\r\n] 2006.201.04:42:13.36#ibcon#*before write, iclass 10, count 2 2006.201.04:42:13.36#ibcon#enter sib2, iclass 10, count 2 2006.201.04:42:13.36#ibcon#flushed, iclass 10, count 2 2006.201.04:42:13.36#ibcon#about to write, iclass 10, count 2 2006.201.04:42:13.36#ibcon#wrote, iclass 10, count 2 2006.201.04:42:13.36#ibcon#about to read 3, iclass 10, count 2 2006.201.04:42:13.39#ibcon#read 3, iclass 10, count 2 2006.201.04:42:13.39#ibcon#about to read 4, iclass 10, count 2 2006.201.04:42:13.39#ibcon#read 4, iclass 10, count 2 2006.201.04:42:13.39#ibcon#about to read 5, iclass 10, count 2 2006.201.04:42:13.39#ibcon#read 5, iclass 10, count 2 2006.201.04:42:13.39#ibcon#about to read 6, iclass 10, count 2 2006.201.04:42:13.39#ibcon#read 6, iclass 10, count 2 2006.201.04:42:13.39#ibcon#end of sib2, iclass 10, count 2 2006.201.04:42:13.39#ibcon#*after write, iclass 10, count 2 2006.201.04:42:13.39#ibcon#*before return 0, iclass 10, count 2 2006.201.04:42:13.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:13.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:13.39#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.04:42:13.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:13.39#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:13.51#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:13.51#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:13.51#ibcon#enter wrdev, iclass 10, count 0 2006.201.04:42:13.51#ibcon#first serial, iclass 10, count 0 2006.201.04:42:13.51#ibcon#enter sib2, iclass 10, count 0 2006.201.04:42:13.51#ibcon#flushed, iclass 10, count 0 2006.201.04:42:13.51#ibcon#about to write, iclass 10, count 0 2006.201.04:42:13.51#ibcon#wrote, iclass 10, count 0 2006.201.04:42:13.51#ibcon#about to read 3, iclass 10, count 0 2006.201.04:42:13.53#ibcon#read 3, iclass 10, count 0 2006.201.04:42:13.53#ibcon#about to read 4, iclass 10, count 0 2006.201.04:42:13.53#ibcon#read 4, iclass 10, count 0 2006.201.04:42:13.53#ibcon#about to read 5, iclass 10, count 0 2006.201.04:42:13.53#ibcon#read 5, iclass 10, count 0 2006.201.04:42:13.53#ibcon#about to read 6, iclass 10, count 0 2006.201.04:42:13.53#ibcon#read 6, iclass 10, count 0 2006.201.04:42:13.53#ibcon#end of sib2, iclass 10, count 0 2006.201.04:42:13.53#ibcon#*mode == 0, iclass 10, count 0 2006.201.04:42:13.53#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.04:42:13.53#ibcon#[25=USB\r\n] 2006.201.04:42:13.53#ibcon#*before write, iclass 10, count 0 2006.201.04:42:13.53#ibcon#enter sib2, iclass 10, count 0 2006.201.04:42:13.53#ibcon#flushed, iclass 10, count 0 2006.201.04:42:13.53#ibcon#about to write, iclass 10, count 0 2006.201.04:42:13.53#ibcon#wrote, iclass 10, count 0 2006.201.04:42:13.53#ibcon#about to read 3, iclass 10, count 0 2006.201.04:42:13.56#ibcon#read 3, iclass 10, count 0 2006.201.04:42:13.56#ibcon#about to read 4, iclass 10, count 0 2006.201.04:42:13.56#ibcon#read 4, iclass 10, count 0 2006.201.04:42:13.56#ibcon#about to read 5, iclass 10, count 0 2006.201.04:42:13.56#ibcon#read 5, iclass 10, count 0 2006.201.04:42:13.56#ibcon#about to read 6, iclass 10, count 0 2006.201.04:42:13.56#ibcon#read 6, iclass 10, count 0 2006.201.04:42:13.56#ibcon#end of sib2, iclass 10, count 0 2006.201.04:42:13.56#ibcon#*after write, iclass 10, count 0 2006.201.04:42:13.56#ibcon#*before return 0, iclass 10, count 0 2006.201.04:42:13.56#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:13.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:13.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.04:42:13.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.04:42:13.56$vck44/valo=2,534.99 2006.201.04:42:13.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.04:42:13.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.04:42:13.56#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:13.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:13.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:13.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:13.56#ibcon#enter wrdev, iclass 12, count 0 2006.201.04:42:13.56#ibcon#first serial, iclass 12, count 0 2006.201.04:42:13.56#ibcon#enter sib2, iclass 12, count 0 2006.201.04:42:13.56#ibcon#flushed, iclass 12, count 0 2006.201.04:42:13.56#ibcon#about to write, iclass 12, count 0 2006.201.04:42:13.56#ibcon#wrote, iclass 12, count 0 2006.201.04:42:13.56#ibcon#about to read 3, iclass 12, count 0 2006.201.04:42:13.58#ibcon#read 3, iclass 12, count 0 2006.201.04:42:13.58#ibcon#about to read 4, iclass 12, count 0 2006.201.04:42:13.58#ibcon#read 4, iclass 12, count 0 2006.201.04:42:13.58#ibcon#about to read 5, iclass 12, count 0 2006.201.04:42:13.58#ibcon#read 5, iclass 12, count 0 2006.201.04:42:13.58#ibcon#about to read 6, iclass 12, count 0 2006.201.04:42:13.58#ibcon#read 6, iclass 12, count 0 2006.201.04:42:13.58#ibcon#end of sib2, iclass 12, count 0 2006.201.04:42:13.58#ibcon#*mode == 0, iclass 12, count 0 2006.201.04:42:13.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.04:42:13.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:42:13.58#ibcon#*before write, iclass 12, count 0 2006.201.04:42:13.58#ibcon#enter sib2, iclass 12, count 0 2006.201.04:42:13.58#ibcon#flushed, iclass 12, count 0 2006.201.04:42:13.58#ibcon#about to write, iclass 12, count 0 2006.201.04:42:13.58#ibcon#wrote, iclass 12, count 0 2006.201.04:42:13.58#ibcon#about to read 3, iclass 12, count 0 2006.201.04:42:13.62#ibcon#read 3, iclass 12, count 0 2006.201.04:42:13.62#ibcon#about to read 4, iclass 12, count 0 2006.201.04:42:13.62#ibcon#read 4, iclass 12, count 0 2006.201.04:42:13.62#ibcon#about to read 5, iclass 12, count 0 2006.201.04:42:13.62#ibcon#read 5, iclass 12, count 0 2006.201.04:42:13.62#ibcon#about to read 6, iclass 12, count 0 2006.201.04:42:13.62#ibcon#read 6, iclass 12, count 0 2006.201.04:42:13.62#ibcon#end of sib2, iclass 12, count 0 2006.201.04:42:13.62#ibcon#*after write, iclass 12, count 0 2006.201.04:42:13.62#ibcon#*before return 0, iclass 12, count 0 2006.201.04:42:13.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:13.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:13.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.04:42:13.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.04:42:13.62$vck44/va=2,7 2006.201.04:42:13.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.04:42:13.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.04:42:13.62#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:13.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:13.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:13.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:13.68#ibcon#enter wrdev, iclass 14, count 2 2006.201.04:42:13.68#ibcon#first serial, iclass 14, count 2 2006.201.04:42:13.68#ibcon#enter sib2, iclass 14, count 2 2006.201.04:42:13.68#ibcon#flushed, iclass 14, count 2 2006.201.04:42:13.68#ibcon#about to write, iclass 14, count 2 2006.201.04:42:13.68#ibcon#wrote, iclass 14, count 2 2006.201.04:42:13.68#ibcon#about to read 3, iclass 14, count 2 2006.201.04:42:13.70#ibcon#read 3, iclass 14, count 2 2006.201.04:42:13.70#ibcon#about to read 4, iclass 14, count 2 2006.201.04:42:13.70#ibcon#read 4, iclass 14, count 2 2006.201.04:42:13.70#ibcon#about to read 5, iclass 14, count 2 2006.201.04:42:13.70#ibcon#read 5, iclass 14, count 2 2006.201.04:42:13.70#ibcon#about to read 6, iclass 14, count 2 2006.201.04:42:13.70#ibcon#read 6, iclass 14, count 2 2006.201.04:42:13.70#ibcon#end of sib2, iclass 14, count 2 2006.201.04:42:13.70#ibcon#*mode == 0, iclass 14, count 2 2006.201.04:42:13.70#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.04:42:13.70#ibcon#[25=AT02-07\r\n] 2006.201.04:42:13.70#ibcon#*before write, iclass 14, count 2 2006.201.04:42:13.70#ibcon#enter sib2, iclass 14, count 2 2006.201.04:42:13.70#ibcon#flushed, iclass 14, count 2 2006.201.04:42:13.70#ibcon#about to write, iclass 14, count 2 2006.201.04:42:13.70#ibcon#wrote, iclass 14, count 2 2006.201.04:42:13.70#ibcon#about to read 3, iclass 14, count 2 2006.201.04:42:13.73#ibcon#read 3, iclass 14, count 2 2006.201.04:42:13.73#ibcon#about to read 4, iclass 14, count 2 2006.201.04:42:13.73#ibcon#read 4, iclass 14, count 2 2006.201.04:42:13.73#ibcon#about to read 5, iclass 14, count 2 2006.201.04:42:13.73#ibcon#read 5, iclass 14, count 2 2006.201.04:42:13.73#ibcon#about to read 6, iclass 14, count 2 2006.201.04:42:13.73#ibcon#read 6, iclass 14, count 2 2006.201.04:42:13.73#ibcon#end of sib2, iclass 14, count 2 2006.201.04:42:13.73#ibcon#*after write, iclass 14, count 2 2006.201.04:42:13.73#ibcon#*before return 0, iclass 14, count 2 2006.201.04:42:13.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:13.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:13.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.04:42:13.73#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:13.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:13.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:13.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:13.85#ibcon#enter wrdev, iclass 14, count 0 2006.201.04:42:13.85#ibcon#first serial, iclass 14, count 0 2006.201.04:42:13.85#ibcon#enter sib2, iclass 14, count 0 2006.201.04:42:13.85#ibcon#flushed, iclass 14, count 0 2006.201.04:42:13.85#ibcon#about to write, iclass 14, count 0 2006.201.04:42:13.85#ibcon#wrote, iclass 14, count 0 2006.201.04:42:13.85#ibcon#about to read 3, iclass 14, count 0 2006.201.04:42:13.87#ibcon#read 3, iclass 14, count 0 2006.201.04:42:13.87#ibcon#about to read 4, iclass 14, count 0 2006.201.04:42:13.87#ibcon#read 4, iclass 14, count 0 2006.201.04:42:13.87#ibcon#about to read 5, iclass 14, count 0 2006.201.04:42:13.87#ibcon#read 5, iclass 14, count 0 2006.201.04:42:13.87#ibcon#about to read 6, iclass 14, count 0 2006.201.04:42:13.87#ibcon#read 6, iclass 14, count 0 2006.201.04:42:13.87#ibcon#end of sib2, iclass 14, count 0 2006.201.04:42:13.87#ibcon#*mode == 0, iclass 14, count 0 2006.201.04:42:13.87#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.04:42:13.87#ibcon#[25=USB\r\n] 2006.201.04:42:13.87#ibcon#*before write, iclass 14, count 0 2006.201.04:42:13.87#ibcon#enter sib2, iclass 14, count 0 2006.201.04:42:13.87#ibcon#flushed, iclass 14, count 0 2006.201.04:42:13.87#ibcon#about to write, iclass 14, count 0 2006.201.04:42:13.87#ibcon#wrote, iclass 14, count 0 2006.201.04:42:13.87#ibcon#about to read 3, iclass 14, count 0 2006.201.04:42:13.90#ibcon#read 3, iclass 14, count 0 2006.201.04:42:13.90#ibcon#about to read 4, iclass 14, count 0 2006.201.04:42:13.90#ibcon#read 4, iclass 14, count 0 2006.201.04:42:13.90#ibcon#about to read 5, iclass 14, count 0 2006.201.04:42:13.90#ibcon#read 5, iclass 14, count 0 2006.201.04:42:13.90#ibcon#about to read 6, iclass 14, count 0 2006.201.04:42:13.90#ibcon#read 6, iclass 14, count 0 2006.201.04:42:13.90#ibcon#end of sib2, iclass 14, count 0 2006.201.04:42:13.90#ibcon#*after write, iclass 14, count 0 2006.201.04:42:13.90#ibcon#*before return 0, iclass 14, count 0 2006.201.04:42:13.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:13.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:13.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.04:42:13.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.04:42:13.90$vck44/valo=3,564.99 2006.201.04:42:13.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.04:42:13.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.04:42:13.90#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:13.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:13.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:13.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:13.90#ibcon#enter wrdev, iclass 16, count 0 2006.201.04:42:13.90#ibcon#first serial, iclass 16, count 0 2006.201.04:42:13.90#ibcon#enter sib2, iclass 16, count 0 2006.201.04:42:13.90#ibcon#flushed, iclass 16, count 0 2006.201.04:42:13.90#ibcon#about to write, iclass 16, count 0 2006.201.04:42:13.90#ibcon#wrote, iclass 16, count 0 2006.201.04:42:13.90#ibcon#about to read 3, iclass 16, count 0 2006.201.04:42:13.92#ibcon#read 3, iclass 16, count 0 2006.201.04:42:13.92#ibcon#about to read 4, iclass 16, count 0 2006.201.04:42:13.92#ibcon#read 4, iclass 16, count 0 2006.201.04:42:13.92#ibcon#about to read 5, iclass 16, count 0 2006.201.04:42:13.92#ibcon#read 5, iclass 16, count 0 2006.201.04:42:13.92#ibcon#about to read 6, iclass 16, count 0 2006.201.04:42:13.92#ibcon#read 6, iclass 16, count 0 2006.201.04:42:13.92#ibcon#end of sib2, iclass 16, count 0 2006.201.04:42:13.92#ibcon#*mode == 0, iclass 16, count 0 2006.201.04:42:13.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.04:42:13.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:42:13.92#ibcon#*before write, iclass 16, count 0 2006.201.04:42:13.92#ibcon#enter sib2, iclass 16, count 0 2006.201.04:42:13.92#ibcon#flushed, iclass 16, count 0 2006.201.04:42:13.92#ibcon#about to write, iclass 16, count 0 2006.201.04:42:13.92#ibcon#wrote, iclass 16, count 0 2006.201.04:42:13.92#ibcon#about to read 3, iclass 16, count 0 2006.201.04:42:13.96#ibcon#read 3, iclass 16, count 0 2006.201.04:42:13.96#ibcon#about to read 4, iclass 16, count 0 2006.201.04:42:13.96#ibcon#read 4, iclass 16, count 0 2006.201.04:42:13.96#ibcon#about to read 5, iclass 16, count 0 2006.201.04:42:13.96#ibcon#read 5, iclass 16, count 0 2006.201.04:42:13.96#ibcon#about to read 6, iclass 16, count 0 2006.201.04:42:13.96#ibcon#read 6, iclass 16, count 0 2006.201.04:42:13.96#ibcon#end of sib2, iclass 16, count 0 2006.201.04:42:13.96#ibcon#*after write, iclass 16, count 0 2006.201.04:42:13.96#ibcon#*before return 0, iclass 16, count 0 2006.201.04:42:13.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:13.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:13.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.04:42:13.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.04:42:13.96$vck44/va=3,8 2006.201.04:42:13.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.04:42:13.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.04:42:13.96#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:13.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:14.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:14.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:14.02#ibcon#enter wrdev, iclass 18, count 2 2006.201.04:42:14.02#ibcon#first serial, iclass 18, count 2 2006.201.04:42:14.02#ibcon#enter sib2, iclass 18, count 2 2006.201.04:42:14.02#ibcon#flushed, iclass 18, count 2 2006.201.04:42:14.02#ibcon#about to write, iclass 18, count 2 2006.201.04:42:14.02#ibcon#wrote, iclass 18, count 2 2006.201.04:42:14.02#ibcon#about to read 3, iclass 18, count 2 2006.201.04:42:14.04#ibcon#read 3, iclass 18, count 2 2006.201.04:42:14.04#ibcon#about to read 4, iclass 18, count 2 2006.201.04:42:14.04#ibcon#read 4, iclass 18, count 2 2006.201.04:42:14.04#ibcon#about to read 5, iclass 18, count 2 2006.201.04:42:14.04#ibcon#read 5, iclass 18, count 2 2006.201.04:42:14.04#ibcon#about to read 6, iclass 18, count 2 2006.201.04:42:14.04#ibcon#read 6, iclass 18, count 2 2006.201.04:42:14.04#ibcon#end of sib2, iclass 18, count 2 2006.201.04:42:14.04#ibcon#*mode == 0, iclass 18, count 2 2006.201.04:42:14.04#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.04:42:14.04#ibcon#[25=AT03-08\r\n] 2006.201.04:42:14.04#ibcon#*before write, iclass 18, count 2 2006.201.04:42:14.04#ibcon#enter sib2, iclass 18, count 2 2006.201.04:42:14.04#ibcon#flushed, iclass 18, count 2 2006.201.04:42:14.04#ibcon#about to write, iclass 18, count 2 2006.201.04:42:14.04#ibcon#wrote, iclass 18, count 2 2006.201.04:42:14.04#ibcon#about to read 3, iclass 18, count 2 2006.201.04:42:14.07#ibcon#read 3, iclass 18, count 2 2006.201.04:42:14.07#ibcon#about to read 4, iclass 18, count 2 2006.201.04:42:14.07#ibcon#read 4, iclass 18, count 2 2006.201.04:42:14.07#ibcon#about to read 5, iclass 18, count 2 2006.201.04:42:14.07#ibcon#read 5, iclass 18, count 2 2006.201.04:42:14.07#ibcon#about to read 6, iclass 18, count 2 2006.201.04:42:14.07#ibcon#read 6, iclass 18, count 2 2006.201.04:42:14.07#ibcon#end of sib2, iclass 18, count 2 2006.201.04:42:14.07#ibcon#*after write, iclass 18, count 2 2006.201.04:42:14.07#ibcon#*before return 0, iclass 18, count 2 2006.201.04:42:14.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:14.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:14.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.04:42:14.07#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:14.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:14.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:14.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:14.19#ibcon#enter wrdev, iclass 18, count 0 2006.201.04:42:14.19#ibcon#first serial, iclass 18, count 0 2006.201.04:42:14.19#ibcon#enter sib2, iclass 18, count 0 2006.201.04:42:14.19#ibcon#flushed, iclass 18, count 0 2006.201.04:42:14.19#ibcon#about to write, iclass 18, count 0 2006.201.04:42:14.19#ibcon#wrote, iclass 18, count 0 2006.201.04:42:14.19#ibcon#about to read 3, iclass 18, count 0 2006.201.04:42:14.21#ibcon#read 3, iclass 18, count 0 2006.201.04:42:14.21#ibcon#about to read 4, iclass 18, count 0 2006.201.04:42:14.21#ibcon#read 4, iclass 18, count 0 2006.201.04:42:14.21#ibcon#about to read 5, iclass 18, count 0 2006.201.04:42:14.21#ibcon#read 5, iclass 18, count 0 2006.201.04:42:14.21#ibcon#about to read 6, iclass 18, count 0 2006.201.04:42:14.21#ibcon#read 6, iclass 18, count 0 2006.201.04:42:14.21#ibcon#end of sib2, iclass 18, count 0 2006.201.04:42:14.21#ibcon#*mode == 0, iclass 18, count 0 2006.201.04:42:14.21#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.04:42:14.21#ibcon#[25=USB\r\n] 2006.201.04:42:14.21#ibcon#*before write, iclass 18, count 0 2006.201.04:42:14.21#ibcon#enter sib2, iclass 18, count 0 2006.201.04:42:14.21#ibcon#flushed, iclass 18, count 0 2006.201.04:42:14.21#ibcon#about to write, iclass 18, count 0 2006.201.04:42:14.21#ibcon#wrote, iclass 18, count 0 2006.201.04:42:14.21#ibcon#about to read 3, iclass 18, count 0 2006.201.04:42:14.24#ibcon#read 3, iclass 18, count 0 2006.201.04:42:14.24#ibcon#about to read 4, iclass 18, count 0 2006.201.04:42:14.24#ibcon#read 4, iclass 18, count 0 2006.201.04:42:14.24#ibcon#about to read 5, iclass 18, count 0 2006.201.04:42:14.24#ibcon#read 5, iclass 18, count 0 2006.201.04:42:14.24#ibcon#about to read 6, iclass 18, count 0 2006.201.04:42:14.24#ibcon#read 6, iclass 18, count 0 2006.201.04:42:14.24#ibcon#end of sib2, iclass 18, count 0 2006.201.04:42:14.24#ibcon#*after write, iclass 18, count 0 2006.201.04:42:14.24#ibcon#*before return 0, iclass 18, count 0 2006.201.04:42:14.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:14.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:14.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.04:42:14.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.04:42:14.24$vck44/valo=4,624.99 2006.201.04:42:14.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.04:42:14.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.04:42:14.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:14.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:14.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:14.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:14.24#ibcon#enter wrdev, iclass 20, count 0 2006.201.04:42:14.24#ibcon#first serial, iclass 20, count 0 2006.201.04:42:14.24#ibcon#enter sib2, iclass 20, count 0 2006.201.04:42:14.24#ibcon#flushed, iclass 20, count 0 2006.201.04:42:14.24#ibcon#about to write, iclass 20, count 0 2006.201.04:42:14.24#ibcon#wrote, iclass 20, count 0 2006.201.04:42:14.24#ibcon#about to read 3, iclass 20, count 0 2006.201.04:42:14.26#ibcon#read 3, iclass 20, count 0 2006.201.04:42:14.26#ibcon#about to read 4, iclass 20, count 0 2006.201.04:42:14.26#ibcon#read 4, iclass 20, count 0 2006.201.04:42:14.26#ibcon#about to read 5, iclass 20, count 0 2006.201.04:42:14.26#ibcon#read 5, iclass 20, count 0 2006.201.04:42:14.26#ibcon#about to read 6, iclass 20, count 0 2006.201.04:42:14.26#ibcon#read 6, iclass 20, count 0 2006.201.04:42:14.26#ibcon#end of sib2, iclass 20, count 0 2006.201.04:42:14.26#ibcon#*mode == 0, iclass 20, count 0 2006.201.04:42:14.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.04:42:14.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:42:14.26#ibcon#*before write, iclass 20, count 0 2006.201.04:42:14.26#ibcon#enter sib2, iclass 20, count 0 2006.201.04:42:14.26#ibcon#flushed, iclass 20, count 0 2006.201.04:42:14.26#ibcon#about to write, iclass 20, count 0 2006.201.04:42:14.26#ibcon#wrote, iclass 20, count 0 2006.201.04:42:14.26#ibcon#about to read 3, iclass 20, count 0 2006.201.04:42:14.30#ibcon#read 3, iclass 20, count 0 2006.201.04:42:14.30#ibcon#about to read 4, iclass 20, count 0 2006.201.04:42:14.30#ibcon#read 4, iclass 20, count 0 2006.201.04:42:14.30#ibcon#about to read 5, iclass 20, count 0 2006.201.04:42:14.30#ibcon#read 5, iclass 20, count 0 2006.201.04:42:14.30#ibcon#about to read 6, iclass 20, count 0 2006.201.04:42:14.30#ibcon#read 6, iclass 20, count 0 2006.201.04:42:14.30#ibcon#end of sib2, iclass 20, count 0 2006.201.04:42:14.30#ibcon#*after write, iclass 20, count 0 2006.201.04:42:14.30#ibcon#*before return 0, iclass 20, count 0 2006.201.04:42:14.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:14.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:14.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.04:42:14.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.04:42:14.30$vck44/va=4,7 2006.201.04:42:14.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.04:42:14.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.04:42:14.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:14.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:14.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:14.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:14.36#ibcon#enter wrdev, iclass 22, count 2 2006.201.04:42:14.36#ibcon#first serial, iclass 22, count 2 2006.201.04:42:14.36#ibcon#enter sib2, iclass 22, count 2 2006.201.04:42:14.36#ibcon#flushed, iclass 22, count 2 2006.201.04:42:14.36#ibcon#about to write, iclass 22, count 2 2006.201.04:42:14.36#ibcon#wrote, iclass 22, count 2 2006.201.04:42:14.36#ibcon#about to read 3, iclass 22, count 2 2006.201.04:42:14.38#ibcon#read 3, iclass 22, count 2 2006.201.04:42:14.38#ibcon#about to read 4, iclass 22, count 2 2006.201.04:42:14.38#ibcon#read 4, iclass 22, count 2 2006.201.04:42:14.38#ibcon#about to read 5, iclass 22, count 2 2006.201.04:42:14.38#ibcon#read 5, iclass 22, count 2 2006.201.04:42:14.38#ibcon#about to read 6, iclass 22, count 2 2006.201.04:42:14.38#ibcon#read 6, iclass 22, count 2 2006.201.04:42:14.38#ibcon#end of sib2, iclass 22, count 2 2006.201.04:42:14.38#ibcon#*mode == 0, iclass 22, count 2 2006.201.04:42:14.38#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.04:42:14.38#ibcon#[25=AT04-07\r\n] 2006.201.04:42:14.38#ibcon#*before write, iclass 22, count 2 2006.201.04:42:14.38#ibcon#enter sib2, iclass 22, count 2 2006.201.04:42:14.38#ibcon#flushed, iclass 22, count 2 2006.201.04:42:14.38#ibcon#about to write, iclass 22, count 2 2006.201.04:42:14.38#ibcon#wrote, iclass 22, count 2 2006.201.04:42:14.38#ibcon#about to read 3, iclass 22, count 2 2006.201.04:42:14.41#ibcon#read 3, iclass 22, count 2 2006.201.04:42:14.44#ibcon#about to read 4, iclass 22, count 2 2006.201.04:42:14.44#ibcon#read 4, iclass 22, count 2 2006.201.04:42:14.44#ibcon#about to read 5, iclass 22, count 2 2006.201.04:42:14.44#ibcon#read 5, iclass 22, count 2 2006.201.04:42:14.44#ibcon#about to read 6, iclass 22, count 2 2006.201.04:42:14.44#ibcon#read 6, iclass 22, count 2 2006.201.04:42:14.44#ibcon#end of sib2, iclass 22, count 2 2006.201.04:42:14.44#ibcon#*after write, iclass 22, count 2 2006.201.04:42:14.44#ibcon#*before return 0, iclass 22, count 2 2006.201.04:42:14.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:14.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:14.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.04:42:14.44#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:14.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:14.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:14.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:14.56#ibcon#enter wrdev, iclass 22, count 0 2006.201.04:42:14.56#ibcon#first serial, iclass 22, count 0 2006.201.04:42:14.56#ibcon#enter sib2, iclass 22, count 0 2006.201.04:42:14.56#ibcon#flushed, iclass 22, count 0 2006.201.04:42:14.56#ibcon#about to write, iclass 22, count 0 2006.201.04:42:14.56#ibcon#wrote, iclass 22, count 0 2006.201.04:42:14.56#ibcon#about to read 3, iclass 22, count 0 2006.201.04:42:14.58#ibcon#read 3, iclass 22, count 0 2006.201.04:42:14.58#ibcon#about to read 4, iclass 22, count 0 2006.201.04:42:14.58#ibcon#read 4, iclass 22, count 0 2006.201.04:42:14.58#ibcon#about to read 5, iclass 22, count 0 2006.201.04:42:14.58#ibcon#read 5, iclass 22, count 0 2006.201.04:42:14.58#ibcon#about to read 6, iclass 22, count 0 2006.201.04:42:14.58#ibcon#read 6, iclass 22, count 0 2006.201.04:42:14.58#ibcon#end of sib2, iclass 22, count 0 2006.201.04:42:14.58#ibcon#*mode == 0, iclass 22, count 0 2006.201.04:42:14.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.04:42:14.58#ibcon#[25=USB\r\n] 2006.201.04:42:14.58#ibcon#*before write, iclass 22, count 0 2006.201.04:42:14.58#ibcon#enter sib2, iclass 22, count 0 2006.201.04:42:14.58#ibcon#flushed, iclass 22, count 0 2006.201.04:42:14.58#ibcon#about to write, iclass 22, count 0 2006.201.04:42:14.58#ibcon#wrote, iclass 22, count 0 2006.201.04:42:14.58#ibcon#about to read 3, iclass 22, count 0 2006.201.04:42:14.61#ibcon#read 3, iclass 22, count 0 2006.201.04:42:14.61#ibcon#about to read 4, iclass 22, count 0 2006.201.04:42:14.61#ibcon#read 4, iclass 22, count 0 2006.201.04:42:14.61#ibcon#about to read 5, iclass 22, count 0 2006.201.04:42:14.61#ibcon#read 5, iclass 22, count 0 2006.201.04:42:14.61#ibcon#about to read 6, iclass 22, count 0 2006.201.04:42:14.61#ibcon#read 6, iclass 22, count 0 2006.201.04:42:14.61#ibcon#end of sib2, iclass 22, count 0 2006.201.04:42:14.61#ibcon#*after write, iclass 22, count 0 2006.201.04:42:14.61#ibcon#*before return 0, iclass 22, count 0 2006.201.04:42:14.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:14.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:14.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.04:42:14.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.04:42:14.61$vck44/valo=5,734.99 2006.201.04:42:14.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.04:42:14.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.04:42:14.61#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:14.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:14.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:14.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:14.61#ibcon#enter wrdev, iclass 24, count 0 2006.201.04:42:14.61#ibcon#first serial, iclass 24, count 0 2006.201.04:42:14.61#ibcon#enter sib2, iclass 24, count 0 2006.201.04:42:14.61#ibcon#flushed, iclass 24, count 0 2006.201.04:42:14.61#ibcon#about to write, iclass 24, count 0 2006.201.04:42:14.61#ibcon#wrote, iclass 24, count 0 2006.201.04:42:14.61#ibcon#about to read 3, iclass 24, count 0 2006.201.04:42:14.63#ibcon#read 3, iclass 24, count 0 2006.201.04:42:14.63#ibcon#about to read 4, iclass 24, count 0 2006.201.04:42:14.63#ibcon#read 4, iclass 24, count 0 2006.201.04:42:14.63#ibcon#about to read 5, iclass 24, count 0 2006.201.04:42:14.63#ibcon#read 5, iclass 24, count 0 2006.201.04:42:14.63#ibcon#about to read 6, iclass 24, count 0 2006.201.04:42:14.63#ibcon#read 6, iclass 24, count 0 2006.201.04:42:14.63#ibcon#end of sib2, iclass 24, count 0 2006.201.04:42:14.63#ibcon#*mode == 0, iclass 24, count 0 2006.201.04:42:14.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.04:42:14.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:42:14.63#ibcon#*before write, iclass 24, count 0 2006.201.04:42:14.63#ibcon#enter sib2, iclass 24, count 0 2006.201.04:42:14.63#ibcon#flushed, iclass 24, count 0 2006.201.04:42:14.63#ibcon#about to write, iclass 24, count 0 2006.201.04:42:14.63#ibcon#wrote, iclass 24, count 0 2006.201.04:42:14.63#ibcon#about to read 3, iclass 24, count 0 2006.201.04:42:14.67#ibcon#read 3, iclass 24, count 0 2006.201.04:42:14.67#ibcon#about to read 4, iclass 24, count 0 2006.201.04:42:14.67#ibcon#read 4, iclass 24, count 0 2006.201.04:42:14.67#ibcon#about to read 5, iclass 24, count 0 2006.201.04:42:14.67#ibcon#read 5, iclass 24, count 0 2006.201.04:42:14.67#ibcon#about to read 6, iclass 24, count 0 2006.201.04:42:14.67#ibcon#read 6, iclass 24, count 0 2006.201.04:42:14.67#ibcon#end of sib2, iclass 24, count 0 2006.201.04:42:14.67#ibcon#*after write, iclass 24, count 0 2006.201.04:42:14.67#ibcon#*before return 0, iclass 24, count 0 2006.201.04:42:14.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:14.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:14.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.04:42:14.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.04:42:14.67$vck44/va=5,4 2006.201.04:42:14.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.04:42:14.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.04:42:14.67#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:14.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:14.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:14.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:14.73#ibcon#enter wrdev, iclass 26, count 2 2006.201.04:42:14.73#ibcon#first serial, iclass 26, count 2 2006.201.04:42:14.73#ibcon#enter sib2, iclass 26, count 2 2006.201.04:42:14.73#ibcon#flushed, iclass 26, count 2 2006.201.04:42:14.73#ibcon#about to write, iclass 26, count 2 2006.201.04:42:14.73#ibcon#wrote, iclass 26, count 2 2006.201.04:42:14.73#ibcon#about to read 3, iclass 26, count 2 2006.201.04:42:14.75#ibcon#read 3, iclass 26, count 2 2006.201.04:42:14.75#ibcon#about to read 4, iclass 26, count 2 2006.201.04:42:14.75#ibcon#read 4, iclass 26, count 2 2006.201.04:42:14.75#ibcon#about to read 5, iclass 26, count 2 2006.201.04:42:14.75#ibcon#read 5, iclass 26, count 2 2006.201.04:42:14.75#ibcon#about to read 6, iclass 26, count 2 2006.201.04:42:14.75#ibcon#read 6, iclass 26, count 2 2006.201.04:42:14.75#ibcon#end of sib2, iclass 26, count 2 2006.201.04:42:14.75#ibcon#*mode == 0, iclass 26, count 2 2006.201.04:42:14.75#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.04:42:14.75#ibcon#[25=AT05-04\r\n] 2006.201.04:42:14.75#ibcon#*before write, iclass 26, count 2 2006.201.04:42:14.75#ibcon#enter sib2, iclass 26, count 2 2006.201.04:42:14.75#ibcon#flushed, iclass 26, count 2 2006.201.04:42:14.75#ibcon#about to write, iclass 26, count 2 2006.201.04:42:14.75#ibcon#wrote, iclass 26, count 2 2006.201.04:42:14.75#ibcon#about to read 3, iclass 26, count 2 2006.201.04:42:14.78#ibcon#read 3, iclass 26, count 2 2006.201.04:42:14.78#ibcon#about to read 4, iclass 26, count 2 2006.201.04:42:14.78#ibcon#read 4, iclass 26, count 2 2006.201.04:42:14.78#ibcon#about to read 5, iclass 26, count 2 2006.201.04:42:14.78#ibcon#read 5, iclass 26, count 2 2006.201.04:42:14.78#ibcon#about to read 6, iclass 26, count 2 2006.201.04:42:14.78#ibcon#read 6, iclass 26, count 2 2006.201.04:42:14.78#ibcon#end of sib2, iclass 26, count 2 2006.201.04:42:14.78#ibcon#*after write, iclass 26, count 2 2006.201.04:42:14.78#ibcon#*before return 0, iclass 26, count 2 2006.201.04:42:14.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:14.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:14.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.04:42:14.78#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:14.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:14.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:14.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:14.90#ibcon#enter wrdev, iclass 26, count 0 2006.201.04:42:14.90#ibcon#first serial, iclass 26, count 0 2006.201.04:42:14.90#ibcon#enter sib2, iclass 26, count 0 2006.201.04:42:14.90#ibcon#flushed, iclass 26, count 0 2006.201.04:42:14.90#ibcon#about to write, iclass 26, count 0 2006.201.04:42:14.90#ibcon#wrote, iclass 26, count 0 2006.201.04:42:14.90#ibcon#about to read 3, iclass 26, count 0 2006.201.04:42:14.92#ibcon#read 3, iclass 26, count 0 2006.201.04:42:14.92#ibcon#about to read 4, iclass 26, count 0 2006.201.04:42:14.92#ibcon#read 4, iclass 26, count 0 2006.201.04:42:14.92#ibcon#about to read 5, iclass 26, count 0 2006.201.04:42:14.92#ibcon#read 5, iclass 26, count 0 2006.201.04:42:14.92#ibcon#about to read 6, iclass 26, count 0 2006.201.04:42:14.92#ibcon#read 6, iclass 26, count 0 2006.201.04:42:14.92#ibcon#end of sib2, iclass 26, count 0 2006.201.04:42:14.92#ibcon#*mode == 0, iclass 26, count 0 2006.201.04:42:14.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.04:42:14.92#ibcon#[25=USB\r\n] 2006.201.04:42:14.92#ibcon#*before write, iclass 26, count 0 2006.201.04:42:14.92#ibcon#enter sib2, iclass 26, count 0 2006.201.04:42:14.92#ibcon#flushed, iclass 26, count 0 2006.201.04:42:14.92#ibcon#about to write, iclass 26, count 0 2006.201.04:42:14.92#ibcon#wrote, iclass 26, count 0 2006.201.04:42:14.92#ibcon#about to read 3, iclass 26, count 0 2006.201.04:42:14.95#ibcon#read 3, iclass 26, count 0 2006.201.04:42:14.95#ibcon#about to read 4, iclass 26, count 0 2006.201.04:42:14.95#ibcon#read 4, iclass 26, count 0 2006.201.04:42:14.95#ibcon#about to read 5, iclass 26, count 0 2006.201.04:42:14.95#ibcon#read 5, iclass 26, count 0 2006.201.04:42:14.95#ibcon#about to read 6, iclass 26, count 0 2006.201.04:42:14.95#ibcon#read 6, iclass 26, count 0 2006.201.04:42:14.95#ibcon#end of sib2, iclass 26, count 0 2006.201.04:42:14.95#ibcon#*after write, iclass 26, count 0 2006.201.04:42:14.95#ibcon#*before return 0, iclass 26, count 0 2006.201.04:42:14.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:14.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:14.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.04:42:14.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.04:42:14.95$vck44/valo=6,814.99 2006.201.04:42:14.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.04:42:14.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.04:42:14.95#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:14.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:14.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:14.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:14.95#ibcon#enter wrdev, iclass 28, count 0 2006.201.04:42:14.95#ibcon#first serial, iclass 28, count 0 2006.201.04:42:14.95#ibcon#enter sib2, iclass 28, count 0 2006.201.04:42:14.95#ibcon#flushed, iclass 28, count 0 2006.201.04:42:14.95#ibcon#about to write, iclass 28, count 0 2006.201.04:42:14.95#ibcon#wrote, iclass 28, count 0 2006.201.04:42:14.95#ibcon#about to read 3, iclass 28, count 0 2006.201.04:42:14.97#ibcon#read 3, iclass 28, count 0 2006.201.04:42:14.97#ibcon#about to read 4, iclass 28, count 0 2006.201.04:42:14.97#ibcon#read 4, iclass 28, count 0 2006.201.04:42:14.97#ibcon#about to read 5, iclass 28, count 0 2006.201.04:42:14.97#ibcon#read 5, iclass 28, count 0 2006.201.04:42:14.97#ibcon#about to read 6, iclass 28, count 0 2006.201.04:42:14.97#ibcon#read 6, iclass 28, count 0 2006.201.04:42:14.97#ibcon#end of sib2, iclass 28, count 0 2006.201.04:42:14.97#ibcon#*mode == 0, iclass 28, count 0 2006.201.04:42:14.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.04:42:14.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:42:14.97#ibcon#*before write, iclass 28, count 0 2006.201.04:42:14.97#ibcon#enter sib2, iclass 28, count 0 2006.201.04:42:14.97#ibcon#flushed, iclass 28, count 0 2006.201.04:42:14.97#ibcon#about to write, iclass 28, count 0 2006.201.04:42:14.97#ibcon#wrote, iclass 28, count 0 2006.201.04:42:14.97#ibcon#about to read 3, iclass 28, count 0 2006.201.04:42:15.01#ibcon#read 3, iclass 28, count 0 2006.201.04:42:15.01#ibcon#about to read 4, iclass 28, count 0 2006.201.04:42:15.01#ibcon#read 4, iclass 28, count 0 2006.201.04:42:15.01#ibcon#about to read 5, iclass 28, count 0 2006.201.04:42:15.01#ibcon#read 5, iclass 28, count 0 2006.201.04:42:15.01#ibcon#about to read 6, iclass 28, count 0 2006.201.04:42:15.01#ibcon#read 6, iclass 28, count 0 2006.201.04:42:15.01#ibcon#end of sib2, iclass 28, count 0 2006.201.04:42:15.01#ibcon#*after write, iclass 28, count 0 2006.201.04:42:15.01#ibcon#*before return 0, iclass 28, count 0 2006.201.04:42:15.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:15.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:15.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.04:42:15.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.04:42:15.01$vck44/va=6,5 2006.201.04:42:15.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.04:42:15.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.04:42:15.01#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:15.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:15.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:15.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:15.07#ibcon#enter wrdev, iclass 30, count 2 2006.201.04:42:15.07#ibcon#first serial, iclass 30, count 2 2006.201.04:42:15.07#ibcon#enter sib2, iclass 30, count 2 2006.201.04:42:15.07#ibcon#flushed, iclass 30, count 2 2006.201.04:42:15.07#ibcon#about to write, iclass 30, count 2 2006.201.04:42:15.07#ibcon#wrote, iclass 30, count 2 2006.201.04:42:15.07#ibcon#about to read 3, iclass 30, count 2 2006.201.04:42:15.09#ibcon#read 3, iclass 30, count 2 2006.201.04:42:15.09#ibcon#about to read 4, iclass 30, count 2 2006.201.04:42:15.09#ibcon#read 4, iclass 30, count 2 2006.201.04:42:15.09#ibcon#about to read 5, iclass 30, count 2 2006.201.04:42:15.09#ibcon#read 5, iclass 30, count 2 2006.201.04:42:15.09#ibcon#about to read 6, iclass 30, count 2 2006.201.04:42:15.09#ibcon#read 6, iclass 30, count 2 2006.201.04:42:15.09#ibcon#end of sib2, iclass 30, count 2 2006.201.04:42:15.09#ibcon#*mode == 0, iclass 30, count 2 2006.201.04:42:15.09#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.04:42:15.09#ibcon#[25=AT06-05\r\n] 2006.201.04:42:15.09#ibcon#*before write, iclass 30, count 2 2006.201.04:42:15.09#ibcon#enter sib2, iclass 30, count 2 2006.201.04:42:15.09#ibcon#flushed, iclass 30, count 2 2006.201.04:42:15.09#ibcon#about to write, iclass 30, count 2 2006.201.04:42:15.09#ibcon#wrote, iclass 30, count 2 2006.201.04:42:15.09#ibcon#about to read 3, iclass 30, count 2 2006.201.04:42:15.12#ibcon#read 3, iclass 30, count 2 2006.201.04:42:15.12#ibcon#about to read 4, iclass 30, count 2 2006.201.04:42:15.12#ibcon#read 4, iclass 30, count 2 2006.201.04:42:15.12#ibcon#about to read 5, iclass 30, count 2 2006.201.04:42:15.12#ibcon#read 5, iclass 30, count 2 2006.201.04:42:15.12#ibcon#about to read 6, iclass 30, count 2 2006.201.04:42:15.12#ibcon#read 6, iclass 30, count 2 2006.201.04:42:15.12#ibcon#end of sib2, iclass 30, count 2 2006.201.04:42:15.12#ibcon#*after write, iclass 30, count 2 2006.201.04:42:15.12#ibcon#*before return 0, iclass 30, count 2 2006.201.04:42:15.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:15.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:15.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.04:42:15.12#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:15.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:15.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:15.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:15.24#ibcon#enter wrdev, iclass 30, count 0 2006.201.04:42:15.24#ibcon#first serial, iclass 30, count 0 2006.201.04:42:15.24#ibcon#enter sib2, iclass 30, count 0 2006.201.04:42:15.24#ibcon#flushed, iclass 30, count 0 2006.201.04:42:15.24#ibcon#about to write, iclass 30, count 0 2006.201.04:42:15.24#ibcon#wrote, iclass 30, count 0 2006.201.04:42:15.24#ibcon#about to read 3, iclass 30, count 0 2006.201.04:42:15.26#ibcon#read 3, iclass 30, count 0 2006.201.04:42:15.26#ibcon#about to read 4, iclass 30, count 0 2006.201.04:42:15.26#ibcon#read 4, iclass 30, count 0 2006.201.04:42:15.26#ibcon#about to read 5, iclass 30, count 0 2006.201.04:42:15.26#ibcon#read 5, iclass 30, count 0 2006.201.04:42:15.26#ibcon#about to read 6, iclass 30, count 0 2006.201.04:42:15.26#ibcon#read 6, iclass 30, count 0 2006.201.04:42:15.26#ibcon#end of sib2, iclass 30, count 0 2006.201.04:42:15.26#ibcon#*mode == 0, iclass 30, count 0 2006.201.04:42:15.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.04:42:15.26#ibcon#[25=USB\r\n] 2006.201.04:42:15.26#ibcon#*before write, iclass 30, count 0 2006.201.04:42:15.26#ibcon#enter sib2, iclass 30, count 0 2006.201.04:42:15.26#ibcon#flushed, iclass 30, count 0 2006.201.04:42:15.26#ibcon#about to write, iclass 30, count 0 2006.201.04:42:15.26#ibcon#wrote, iclass 30, count 0 2006.201.04:42:15.26#ibcon#about to read 3, iclass 30, count 0 2006.201.04:42:15.29#ibcon#read 3, iclass 30, count 0 2006.201.04:42:15.29#ibcon#about to read 4, iclass 30, count 0 2006.201.04:42:15.29#ibcon#read 4, iclass 30, count 0 2006.201.04:42:15.29#ibcon#about to read 5, iclass 30, count 0 2006.201.04:42:15.29#ibcon#read 5, iclass 30, count 0 2006.201.04:42:15.29#ibcon#about to read 6, iclass 30, count 0 2006.201.04:42:15.29#ibcon#read 6, iclass 30, count 0 2006.201.04:42:15.29#ibcon#end of sib2, iclass 30, count 0 2006.201.04:42:15.29#ibcon#*after write, iclass 30, count 0 2006.201.04:42:15.29#ibcon#*before return 0, iclass 30, count 0 2006.201.04:42:15.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:15.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:15.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.04:42:15.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.04:42:15.29$vck44/valo=7,864.99 2006.201.04:42:15.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.04:42:15.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.04:42:15.29#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:15.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:15.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:15.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:15.29#ibcon#enter wrdev, iclass 32, count 0 2006.201.04:42:15.29#ibcon#first serial, iclass 32, count 0 2006.201.04:42:15.29#ibcon#enter sib2, iclass 32, count 0 2006.201.04:42:15.29#ibcon#flushed, iclass 32, count 0 2006.201.04:42:15.29#ibcon#about to write, iclass 32, count 0 2006.201.04:42:15.29#ibcon#wrote, iclass 32, count 0 2006.201.04:42:15.29#ibcon#about to read 3, iclass 32, count 0 2006.201.04:42:15.31#ibcon#read 3, iclass 32, count 0 2006.201.04:42:15.31#ibcon#about to read 4, iclass 32, count 0 2006.201.04:42:15.31#ibcon#read 4, iclass 32, count 0 2006.201.04:42:15.31#ibcon#about to read 5, iclass 32, count 0 2006.201.04:42:15.31#ibcon#read 5, iclass 32, count 0 2006.201.04:42:15.31#ibcon#about to read 6, iclass 32, count 0 2006.201.04:42:15.31#ibcon#read 6, iclass 32, count 0 2006.201.04:42:15.31#ibcon#end of sib2, iclass 32, count 0 2006.201.04:42:15.31#ibcon#*mode == 0, iclass 32, count 0 2006.201.04:42:15.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.04:42:15.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:42:15.31#ibcon#*before write, iclass 32, count 0 2006.201.04:42:15.31#ibcon#enter sib2, iclass 32, count 0 2006.201.04:42:15.31#ibcon#flushed, iclass 32, count 0 2006.201.04:42:15.31#ibcon#about to write, iclass 32, count 0 2006.201.04:42:15.31#ibcon#wrote, iclass 32, count 0 2006.201.04:42:15.31#ibcon#about to read 3, iclass 32, count 0 2006.201.04:42:15.35#ibcon#read 3, iclass 32, count 0 2006.201.04:42:15.35#ibcon#about to read 4, iclass 32, count 0 2006.201.04:42:15.35#ibcon#read 4, iclass 32, count 0 2006.201.04:42:15.35#ibcon#about to read 5, iclass 32, count 0 2006.201.04:42:15.35#ibcon#read 5, iclass 32, count 0 2006.201.04:42:15.35#ibcon#about to read 6, iclass 32, count 0 2006.201.04:42:15.35#ibcon#read 6, iclass 32, count 0 2006.201.04:42:15.35#ibcon#end of sib2, iclass 32, count 0 2006.201.04:42:15.35#ibcon#*after write, iclass 32, count 0 2006.201.04:42:15.35#ibcon#*before return 0, iclass 32, count 0 2006.201.04:42:15.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:15.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:15.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.04:42:15.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.04:42:15.35$vck44/va=7,5 2006.201.04:42:15.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.04:42:15.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.04:42:15.35#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:15.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:15.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:15.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:15.41#ibcon#enter wrdev, iclass 34, count 2 2006.201.04:42:15.41#ibcon#first serial, iclass 34, count 2 2006.201.04:42:15.41#ibcon#enter sib2, iclass 34, count 2 2006.201.04:42:15.41#ibcon#flushed, iclass 34, count 2 2006.201.04:42:15.41#ibcon#about to write, iclass 34, count 2 2006.201.04:42:15.41#ibcon#wrote, iclass 34, count 2 2006.201.04:42:15.41#ibcon#about to read 3, iclass 34, count 2 2006.201.04:42:15.43#ibcon#read 3, iclass 34, count 2 2006.201.04:42:15.43#ibcon#about to read 4, iclass 34, count 2 2006.201.04:42:15.43#ibcon#read 4, iclass 34, count 2 2006.201.04:42:15.43#ibcon#about to read 5, iclass 34, count 2 2006.201.04:42:15.43#ibcon#read 5, iclass 34, count 2 2006.201.04:42:15.43#ibcon#about to read 6, iclass 34, count 2 2006.201.04:42:15.43#ibcon#read 6, iclass 34, count 2 2006.201.04:42:15.43#ibcon#end of sib2, iclass 34, count 2 2006.201.04:42:15.43#ibcon#*mode == 0, iclass 34, count 2 2006.201.04:42:15.43#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.04:42:15.43#ibcon#[25=AT07-05\r\n] 2006.201.04:42:15.43#ibcon#*before write, iclass 34, count 2 2006.201.04:42:15.43#ibcon#enter sib2, iclass 34, count 2 2006.201.04:42:15.43#ibcon#flushed, iclass 34, count 2 2006.201.04:42:15.43#ibcon#about to write, iclass 34, count 2 2006.201.04:42:15.50#ibcon#wrote, iclass 34, count 2 2006.201.04:42:15.50#ibcon#about to read 3, iclass 34, count 2 2006.201.04:42:15.53#ibcon#read 3, iclass 34, count 2 2006.201.04:42:15.53#ibcon#about to read 4, iclass 34, count 2 2006.201.04:42:15.53#ibcon#read 4, iclass 34, count 2 2006.201.04:42:15.53#ibcon#about to read 5, iclass 34, count 2 2006.201.04:42:15.53#ibcon#read 5, iclass 34, count 2 2006.201.04:42:15.53#ibcon#about to read 6, iclass 34, count 2 2006.201.04:42:15.53#ibcon#read 6, iclass 34, count 2 2006.201.04:42:15.53#ibcon#end of sib2, iclass 34, count 2 2006.201.04:42:15.53#ibcon#*after write, iclass 34, count 2 2006.201.04:42:15.53#ibcon#*before return 0, iclass 34, count 2 2006.201.04:42:15.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:15.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:15.53#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.04:42:15.53#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:15.53#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:15.65#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:15.65#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:15.65#ibcon#enter wrdev, iclass 34, count 0 2006.201.04:42:15.65#ibcon#first serial, iclass 34, count 0 2006.201.04:42:15.65#ibcon#enter sib2, iclass 34, count 0 2006.201.04:42:15.65#ibcon#flushed, iclass 34, count 0 2006.201.04:42:15.65#ibcon#about to write, iclass 34, count 0 2006.201.04:42:15.65#ibcon#wrote, iclass 34, count 0 2006.201.04:42:15.65#ibcon#about to read 3, iclass 34, count 0 2006.201.04:42:15.67#ibcon#read 3, iclass 34, count 0 2006.201.04:42:15.67#ibcon#about to read 4, iclass 34, count 0 2006.201.04:42:15.67#ibcon#read 4, iclass 34, count 0 2006.201.04:42:15.67#ibcon#about to read 5, iclass 34, count 0 2006.201.04:42:15.67#ibcon#read 5, iclass 34, count 0 2006.201.04:42:15.67#ibcon#about to read 6, iclass 34, count 0 2006.201.04:42:15.67#ibcon#read 6, iclass 34, count 0 2006.201.04:42:15.67#ibcon#end of sib2, iclass 34, count 0 2006.201.04:42:15.67#ibcon#*mode == 0, iclass 34, count 0 2006.201.04:42:15.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.04:42:15.67#ibcon#[25=USB\r\n] 2006.201.04:42:15.67#ibcon#*before write, iclass 34, count 0 2006.201.04:42:15.67#ibcon#enter sib2, iclass 34, count 0 2006.201.04:42:15.67#ibcon#flushed, iclass 34, count 0 2006.201.04:42:15.67#ibcon#about to write, iclass 34, count 0 2006.201.04:42:15.67#ibcon#wrote, iclass 34, count 0 2006.201.04:42:15.67#ibcon#about to read 3, iclass 34, count 0 2006.201.04:42:15.70#ibcon#read 3, iclass 34, count 0 2006.201.04:42:15.70#ibcon#about to read 4, iclass 34, count 0 2006.201.04:42:15.70#ibcon#read 4, iclass 34, count 0 2006.201.04:42:15.70#ibcon#about to read 5, iclass 34, count 0 2006.201.04:42:15.70#ibcon#read 5, iclass 34, count 0 2006.201.04:42:15.70#ibcon#about to read 6, iclass 34, count 0 2006.201.04:42:15.70#ibcon#read 6, iclass 34, count 0 2006.201.04:42:15.70#ibcon#end of sib2, iclass 34, count 0 2006.201.04:42:15.70#ibcon#*after write, iclass 34, count 0 2006.201.04:42:15.70#ibcon#*before return 0, iclass 34, count 0 2006.201.04:42:15.70#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:15.70#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:15.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.04:42:15.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.04:42:15.70$vck44/valo=8,884.99 2006.201.04:42:15.70#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.04:42:15.70#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.04:42:15.70#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:15.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:42:15.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:42:15.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:42:15.70#ibcon#enter wrdev, iclass 36, count 0 2006.201.04:42:15.70#ibcon#first serial, iclass 36, count 0 2006.201.04:42:15.70#ibcon#enter sib2, iclass 36, count 0 2006.201.04:42:15.70#ibcon#flushed, iclass 36, count 0 2006.201.04:42:15.70#ibcon#about to write, iclass 36, count 0 2006.201.04:42:15.70#ibcon#wrote, iclass 36, count 0 2006.201.04:42:15.70#ibcon#about to read 3, iclass 36, count 0 2006.201.04:42:15.72#ibcon#read 3, iclass 36, count 0 2006.201.04:42:15.72#ibcon#about to read 4, iclass 36, count 0 2006.201.04:42:15.72#ibcon#read 4, iclass 36, count 0 2006.201.04:42:15.72#ibcon#about to read 5, iclass 36, count 0 2006.201.04:42:15.72#ibcon#read 5, iclass 36, count 0 2006.201.04:42:15.72#ibcon#about to read 6, iclass 36, count 0 2006.201.04:42:15.72#ibcon#read 6, iclass 36, count 0 2006.201.04:42:15.72#ibcon#end of sib2, iclass 36, count 0 2006.201.04:42:15.72#ibcon#*mode == 0, iclass 36, count 0 2006.201.04:42:15.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.04:42:15.72#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:42:15.72#ibcon#*before write, iclass 36, count 0 2006.201.04:42:15.72#ibcon#enter sib2, iclass 36, count 0 2006.201.04:42:15.72#ibcon#flushed, iclass 36, count 0 2006.201.04:42:15.72#ibcon#about to write, iclass 36, count 0 2006.201.04:42:15.72#ibcon#wrote, iclass 36, count 0 2006.201.04:42:15.72#ibcon#about to read 3, iclass 36, count 0 2006.201.04:42:15.76#ibcon#read 3, iclass 36, count 0 2006.201.04:42:15.76#ibcon#about to read 4, iclass 36, count 0 2006.201.04:42:15.76#ibcon#read 4, iclass 36, count 0 2006.201.04:42:15.76#ibcon#about to read 5, iclass 36, count 0 2006.201.04:42:15.76#ibcon#read 5, iclass 36, count 0 2006.201.04:42:15.76#ibcon#about to read 6, iclass 36, count 0 2006.201.04:42:15.76#ibcon#read 6, iclass 36, count 0 2006.201.04:42:15.76#ibcon#end of sib2, iclass 36, count 0 2006.201.04:42:15.76#ibcon#*after write, iclass 36, count 0 2006.201.04:42:15.76#ibcon#*before return 0, iclass 36, count 0 2006.201.04:42:15.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:42:15.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.04:42:15.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.04:42:15.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.04:42:15.76$vck44/va=8,4 2006.201.04:42:15.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.04:42:15.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.04:42:15.76#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:15.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:42:15.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:42:15.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:42:15.82#ibcon#enter wrdev, iclass 38, count 2 2006.201.04:42:15.82#ibcon#first serial, iclass 38, count 2 2006.201.04:42:15.82#ibcon#enter sib2, iclass 38, count 2 2006.201.04:42:15.82#ibcon#flushed, iclass 38, count 2 2006.201.04:42:15.82#ibcon#about to write, iclass 38, count 2 2006.201.04:42:15.82#ibcon#wrote, iclass 38, count 2 2006.201.04:42:15.82#ibcon#about to read 3, iclass 38, count 2 2006.201.04:42:15.84#ibcon#read 3, iclass 38, count 2 2006.201.04:42:15.84#ibcon#about to read 4, iclass 38, count 2 2006.201.04:42:15.84#ibcon#read 4, iclass 38, count 2 2006.201.04:42:15.84#ibcon#about to read 5, iclass 38, count 2 2006.201.04:42:15.84#ibcon#read 5, iclass 38, count 2 2006.201.04:42:15.84#ibcon#about to read 6, iclass 38, count 2 2006.201.04:42:15.84#ibcon#read 6, iclass 38, count 2 2006.201.04:42:15.84#ibcon#end of sib2, iclass 38, count 2 2006.201.04:42:15.84#ibcon#*mode == 0, iclass 38, count 2 2006.201.04:42:15.84#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.04:42:15.84#ibcon#[25=AT08-04\r\n] 2006.201.04:42:15.84#ibcon#*before write, iclass 38, count 2 2006.201.04:42:15.84#ibcon#enter sib2, iclass 38, count 2 2006.201.04:42:15.84#ibcon#flushed, iclass 38, count 2 2006.201.04:42:15.84#ibcon#about to write, iclass 38, count 2 2006.201.04:42:15.84#ibcon#wrote, iclass 38, count 2 2006.201.04:42:15.84#ibcon#about to read 3, iclass 38, count 2 2006.201.04:42:15.87#ibcon#read 3, iclass 38, count 2 2006.201.04:42:15.87#ibcon#about to read 4, iclass 38, count 2 2006.201.04:42:15.87#ibcon#read 4, iclass 38, count 2 2006.201.04:42:15.87#ibcon#about to read 5, iclass 38, count 2 2006.201.04:42:15.87#ibcon#read 5, iclass 38, count 2 2006.201.04:42:15.87#ibcon#about to read 6, iclass 38, count 2 2006.201.04:42:15.87#ibcon#read 6, iclass 38, count 2 2006.201.04:42:15.87#ibcon#end of sib2, iclass 38, count 2 2006.201.04:42:15.87#ibcon#*after write, iclass 38, count 2 2006.201.04:42:15.87#ibcon#*before return 0, iclass 38, count 2 2006.201.04:42:15.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:42:15.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.04:42:15.87#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.04:42:15.87#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:15.87#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:42:15.99#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:42:15.99#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:42:15.99#ibcon#enter wrdev, iclass 38, count 0 2006.201.04:42:15.99#ibcon#first serial, iclass 38, count 0 2006.201.04:42:15.99#ibcon#enter sib2, iclass 38, count 0 2006.201.04:42:15.99#ibcon#flushed, iclass 38, count 0 2006.201.04:42:15.99#ibcon#about to write, iclass 38, count 0 2006.201.04:42:15.99#ibcon#wrote, iclass 38, count 0 2006.201.04:42:15.99#ibcon#about to read 3, iclass 38, count 0 2006.201.04:42:16.01#ibcon#read 3, iclass 38, count 0 2006.201.04:42:16.01#ibcon#about to read 4, iclass 38, count 0 2006.201.04:42:16.01#ibcon#read 4, iclass 38, count 0 2006.201.04:42:16.01#ibcon#about to read 5, iclass 38, count 0 2006.201.04:42:16.01#ibcon#read 5, iclass 38, count 0 2006.201.04:42:16.01#ibcon#about to read 6, iclass 38, count 0 2006.201.04:42:16.01#ibcon#read 6, iclass 38, count 0 2006.201.04:42:16.01#ibcon#end of sib2, iclass 38, count 0 2006.201.04:42:16.01#ibcon#*mode == 0, iclass 38, count 0 2006.201.04:42:16.01#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.04:42:16.01#ibcon#[25=USB\r\n] 2006.201.04:42:16.01#ibcon#*before write, iclass 38, count 0 2006.201.04:42:16.01#ibcon#enter sib2, iclass 38, count 0 2006.201.04:42:16.01#ibcon#flushed, iclass 38, count 0 2006.201.04:42:16.01#ibcon#about to write, iclass 38, count 0 2006.201.04:42:16.01#ibcon#wrote, iclass 38, count 0 2006.201.04:42:16.01#ibcon#about to read 3, iclass 38, count 0 2006.201.04:42:16.04#ibcon#read 3, iclass 38, count 0 2006.201.04:42:16.04#ibcon#about to read 4, iclass 38, count 0 2006.201.04:42:16.04#ibcon#read 4, iclass 38, count 0 2006.201.04:42:16.04#ibcon#about to read 5, iclass 38, count 0 2006.201.04:42:16.04#ibcon#read 5, iclass 38, count 0 2006.201.04:42:16.04#ibcon#about to read 6, iclass 38, count 0 2006.201.04:42:16.04#ibcon#read 6, iclass 38, count 0 2006.201.04:42:16.04#ibcon#end of sib2, iclass 38, count 0 2006.201.04:42:16.04#ibcon#*after write, iclass 38, count 0 2006.201.04:42:16.04#ibcon#*before return 0, iclass 38, count 0 2006.201.04:42:16.04#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:42:16.04#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.04:42:16.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.04:42:16.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.04:42:16.04$vck44/vblo=1,629.99 2006.201.04:42:16.04#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.04:42:16.04#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.04:42:16.04#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:16.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:16.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:16.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:16.04#ibcon#enter wrdev, iclass 40, count 0 2006.201.04:42:16.04#ibcon#first serial, iclass 40, count 0 2006.201.04:42:16.04#ibcon#enter sib2, iclass 40, count 0 2006.201.04:42:16.04#ibcon#flushed, iclass 40, count 0 2006.201.04:42:16.04#ibcon#about to write, iclass 40, count 0 2006.201.04:42:16.04#ibcon#wrote, iclass 40, count 0 2006.201.04:42:16.04#ibcon#about to read 3, iclass 40, count 0 2006.201.04:42:16.06#ibcon#read 3, iclass 40, count 0 2006.201.04:42:16.06#ibcon#about to read 4, iclass 40, count 0 2006.201.04:42:16.06#ibcon#read 4, iclass 40, count 0 2006.201.04:42:16.06#ibcon#about to read 5, iclass 40, count 0 2006.201.04:42:16.06#ibcon#read 5, iclass 40, count 0 2006.201.04:42:16.06#ibcon#about to read 6, iclass 40, count 0 2006.201.04:42:16.06#ibcon#read 6, iclass 40, count 0 2006.201.04:42:16.06#ibcon#end of sib2, iclass 40, count 0 2006.201.04:42:16.06#ibcon#*mode == 0, iclass 40, count 0 2006.201.04:42:16.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.04:42:16.06#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:42:16.06#ibcon#*before write, iclass 40, count 0 2006.201.04:42:16.06#ibcon#enter sib2, iclass 40, count 0 2006.201.04:42:16.06#ibcon#flushed, iclass 40, count 0 2006.201.04:42:16.06#ibcon#about to write, iclass 40, count 0 2006.201.04:42:16.06#ibcon#wrote, iclass 40, count 0 2006.201.04:42:16.06#ibcon#about to read 3, iclass 40, count 0 2006.201.04:42:16.10#ibcon#read 3, iclass 40, count 0 2006.201.04:42:16.10#ibcon#about to read 4, iclass 40, count 0 2006.201.04:42:16.10#ibcon#read 4, iclass 40, count 0 2006.201.04:42:16.10#ibcon#about to read 5, iclass 40, count 0 2006.201.04:42:16.10#ibcon#read 5, iclass 40, count 0 2006.201.04:42:16.10#ibcon#about to read 6, iclass 40, count 0 2006.201.04:42:16.10#ibcon#read 6, iclass 40, count 0 2006.201.04:42:16.10#ibcon#end of sib2, iclass 40, count 0 2006.201.04:42:16.10#ibcon#*after write, iclass 40, count 0 2006.201.04:42:16.10#ibcon#*before return 0, iclass 40, count 0 2006.201.04:42:16.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:16.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:16.10#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.04:42:16.10#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.04:42:16.10$vck44/vb=1,4 2006.201.04:42:16.10#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.04:42:16.10#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.04:42:16.10#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:16.10#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:42:16.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:42:16.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:42:16.10#ibcon#enter wrdev, iclass 4, count 2 2006.201.04:42:16.10#ibcon#first serial, iclass 4, count 2 2006.201.04:42:16.10#ibcon#enter sib2, iclass 4, count 2 2006.201.04:42:16.10#ibcon#flushed, iclass 4, count 2 2006.201.04:42:16.10#ibcon#about to write, iclass 4, count 2 2006.201.04:42:16.10#ibcon#wrote, iclass 4, count 2 2006.201.04:42:16.10#ibcon#about to read 3, iclass 4, count 2 2006.201.04:42:16.12#ibcon#read 3, iclass 4, count 2 2006.201.04:42:16.12#ibcon#about to read 4, iclass 4, count 2 2006.201.04:42:16.12#ibcon#read 4, iclass 4, count 2 2006.201.04:42:16.12#ibcon#about to read 5, iclass 4, count 2 2006.201.04:42:16.12#ibcon#read 5, iclass 4, count 2 2006.201.04:42:16.12#ibcon#about to read 6, iclass 4, count 2 2006.201.04:42:16.12#ibcon#read 6, iclass 4, count 2 2006.201.04:42:16.12#ibcon#end of sib2, iclass 4, count 2 2006.201.04:42:16.12#ibcon#*mode == 0, iclass 4, count 2 2006.201.04:42:16.12#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.04:42:16.12#ibcon#[27=AT01-04\r\n] 2006.201.04:42:16.12#ibcon#*before write, iclass 4, count 2 2006.201.04:42:16.12#ibcon#enter sib2, iclass 4, count 2 2006.201.04:42:16.12#ibcon#flushed, iclass 4, count 2 2006.201.04:42:16.12#ibcon#about to write, iclass 4, count 2 2006.201.04:42:16.12#ibcon#wrote, iclass 4, count 2 2006.201.04:42:16.12#ibcon#about to read 3, iclass 4, count 2 2006.201.04:42:16.15#ibcon#read 3, iclass 4, count 2 2006.201.04:42:16.15#ibcon#about to read 4, iclass 4, count 2 2006.201.04:42:16.15#ibcon#read 4, iclass 4, count 2 2006.201.04:42:16.15#ibcon#about to read 5, iclass 4, count 2 2006.201.04:42:16.15#ibcon#read 5, iclass 4, count 2 2006.201.04:42:16.15#ibcon#about to read 6, iclass 4, count 2 2006.201.04:42:16.15#ibcon#read 6, iclass 4, count 2 2006.201.04:42:16.15#ibcon#end of sib2, iclass 4, count 2 2006.201.04:42:16.15#ibcon#*after write, iclass 4, count 2 2006.201.04:42:16.15#ibcon#*before return 0, iclass 4, count 2 2006.201.04:42:16.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:42:16.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.04:42:16.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.04:42:16.15#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:16.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:42:16.27#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:42:16.27#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:42:16.27#ibcon#enter wrdev, iclass 4, count 0 2006.201.04:42:16.27#ibcon#first serial, iclass 4, count 0 2006.201.04:42:16.27#ibcon#enter sib2, iclass 4, count 0 2006.201.04:42:16.27#ibcon#flushed, iclass 4, count 0 2006.201.04:42:16.27#ibcon#about to write, iclass 4, count 0 2006.201.04:42:16.27#ibcon#wrote, iclass 4, count 0 2006.201.04:42:16.27#ibcon#about to read 3, iclass 4, count 0 2006.201.04:42:16.29#ibcon#read 3, iclass 4, count 0 2006.201.04:42:16.29#ibcon#about to read 4, iclass 4, count 0 2006.201.04:42:16.29#ibcon#read 4, iclass 4, count 0 2006.201.04:42:16.29#ibcon#about to read 5, iclass 4, count 0 2006.201.04:42:16.29#ibcon#read 5, iclass 4, count 0 2006.201.04:42:16.29#ibcon#about to read 6, iclass 4, count 0 2006.201.04:42:16.29#ibcon#read 6, iclass 4, count 0 2006.201.04:42:16.29#ibcon#end of sib2, iclass 4, count 0 2006.201.04:42:16.29#ibcon#*mode == 0, iclass 4, count 0 2006.201.04:42:16.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.04:42:16.29#ibcon#[27=USB\r\n] 2006.201.04:42:16.29#ibcon#*before write, iclass 4, count 0 2006.201.04:42:16.29#ibcon#enter sib2, iclass 4, count 0 2006.201.04:42:16.29#ibcon#flushed, iclass 4, count 0 2006.201.04:42:16.29#ibcon#about to write, iclass 4, count 0 2006.201.04:42:16.29#ibcon#wrote, iclass 4, count 0 2006.201.04:42:16.29#ibcon#about to read 3, iclass 4, count 0 2006.201.04:42:16.32#ibcon#read 3, iclass 4, count 0 2006.201.04:42:16.32#ibcon#about to read 4, iclass 4, count 0 2006.201.04:42:16.32#ibcon#read 4, iclass 4, count 0 2006.201.04:42:16.32#ibcon#about to read 5, iclass 4, count 0 2006.201.04:42:16.32#ibcon#read 5, iclass 4, count 0 2006.201.04:42:16.32#ibcon#about to read 6, iclass 4, count 0 2006.201.04:42:16.32#ibcon#read 6, iclass 4, count 0 2006.201.04:42:16.32#ibcon#end of sib2, iclass 4, count 0 2006.201.04:42:16.32#ibcon#*after write, iclass 4, count 0 2006.201.04:42:16.32#ibcon#*before return 0, iclass 4, count 0 2006.201.04:42:16.32#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:42:16.32#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.04:42:16.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.04:42:16.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.04:42:16.32$vck44/vblo=2,634.99 2006.201.04:42:16.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.04:42:16.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.04:42:16.32#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:16.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:16.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:16.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:16.32#ibcon#enter wrdev, iclass 6, count 0 2006.201.04:42:16.32#ibcon#first serial, iclass 6, count 0 2006.201.04:42:16.32#ibcon#enter sib2, iclass 6, count 0 2006.201.04:42:16.32#ibcon#flushed, iclass 6, count 0 2006.201.04:42:16.32#ibcon#about to write, iclass 6, count 0 2006.201.04:42:16.32#ibcon#wrote, iclass 6, count 0 2006.201.04:42:16.32#ibcon#about to read 3, iclass 6, count 0 2006.201.04:42:16.34#ibcon#read 3, iclass 6, count 0 2006.201.04:42:16.34#ibcon#about to read 4, iclass 6, count 0 2006.201.04:42:16.34#ibcon#read 4, iclass 6, count 0 2006.201.04:42:16.34#ibcon#about to read 5, iclass 6, count 0 2006.201.04:42:16.34#ibcon#read 5, iclass 6, count 0 2006.201.04:42:16.34#ibcon#about to read 6, iclass 6, count 0 2006.201.04:42:16.34#ibcon#read 6, iclass 6, count 0 2006.201.04:42:16.34#ibcon#end of sib2, iclass 6, count 0 2006.201.04:42:16.34#ibcon#*mode == 0, iclass 6, count 0 2006.201.04:42:16.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.04:42:16.34#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:42:16.34#ibcon#*before write, iclass 6, count 0 2006.201.04:42:16.34#ibcon#enter sib2, iclass 6, count 0 2006.201.04:42:16.34#ibcon#flushed, iclass 6, count 0 2006.201.04:42:16.34#ibcon#about to write, iclass 6, count 0 2006.201.04:42:16.34#ibcon#wrote, iclass 6, count 0 2006.201.04:42:16.34#ibcon#about to read 3, iclass 6, count 0 2006.201.04:42:16.38#ibcon#read 3, iclass 6, count 0 2006.201.04:42:16.38#ibcon#about to read 4, iclass 6, count 0 2006.201.04:42:16.38#ibcon#read 4, iclass 6, count 0 2006.201.04:42:16.38#ibcon#about to read 5, iclass 6, count 0 2006.201.04:42:16.38#ibcon#read 5, iclass 6, count 0 2006.201.04:42:16.38#ibcon#about to read 6, iclass 6, count 0 2006.201.04:42:16.38#ibcon#read 6, iclass 6, count 0 2006.201.04:42:16.38#ibcon#end of sib2, iclass 6, count 0 2006.201.04:42:16.38#ibcon#*after write, iclass 6, count 0 2006.201.04:42:16.38#ibcon#*before return 0, iclass 6, count 0 2006.201.04:42:16.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:16.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.04:42:16.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.04:42:16.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.04:42:16.38$vck44/vb=2,5 2006.201.04:42:16.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.04:42:16.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.04:42:16.38#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:16.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:16.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:16.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:16.44#ibcon#enter wrdev, iclass 10, count 2 2006.201.04:42:16.44#ibcon#first serial, iclass 10, count 2 2006.201.04:42:16.44#ibcon#enter sib2, iclass 10, count 2 2006.201.04:42:16.44#ibcon#flushed, iclass 10, count 2 2006.201.04:42:16.44#ibcon#about to write, iclass 10, count 2 2006.201.04:42:16.44#ibcon#wrote, iclass 10, count 2 2006.201.04:42:16.44#ibcon#about to read 3, iclass 10, count 2 2006.201.04:42:16.46#ibcon#read 3, iclass 10, count 2 2006.201.04:42:16.46#ibcon#about to read 4, iclass 10, count 2 2006.201.04:42:16.46#ibcon#read 4, iclass 10, count 2 2006.201.04:42:16.46#ibcon#about to read 5, iclass 10, count 2 2006.201.04:42:16.46#ibcon#read 5, iclass 10, count 2 2006.201.04:42:16.46#ibcon#about to read 6, iclass 10, count 2 2006.201.04:42:16.46#ibcon#read 6, iclass 10, count 2 2006.201.04:42:16.46#ibcon#end of sib2, iclass 10, count 2 2006.201.04:42:16.46#ibcon#*mode == 0, iclass 10, count 2 2006.201.04:42:16.46#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.04:42:16.46#ibcon#[27=AT02-05\r\n] 2006.201.04:42:16.46#ibcon#*before write, iclass 10, count 2 2006.201.04:42:16.46#ibcon#enter sib2, iclass 10, count 2 2006.201.04:42:16.46#ibcon#flushed, iclass 10, count 2 2006.201.04:42:16.46#ibcon#about to write, iclass 10, count 2 2006.201.04:42:16.46#ibcon#wrote, iclass 10, count 2 2006.201.04:42:16.46#ibcon#about to read 3, iclass 10, count 2 2006.201.04:42:16.49#ibcon#read 3, iclass 10, count 2 2006.201.04:42:16.49#ibcon#about to read 4, iclass 10, count 2 2006.201.04:42:16.56#ibcon#read 4, iclass 10, count 2 2006.201.04:42:16.56#ibcon#about to read 5, iclass 10, count 2 2006.201.04:42:16.56#ibcon#read 5, iclass 10, count 2 2006.201.04:42:16.56#ibcon#about to read 6, iclass 10, count 2 2006.201.04:42:16.56#ibcon#read 6, iclass 10, count 2 2006.201.04:42:16.56#ibcon#end of sib2, iclass 10, count 2 2006.201.04:42:16.56#ibcon#*after write, iclass 10, count 2 2006.201.04:42:16.56#ibcon#*before return 0, iclass 10, count 2 2006.201.04:42:16.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:16.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.04:42:16.56#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.04:42:16.56#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:16.56#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:16.68#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:16.68#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:16.68#ibcon#enter wrdev, iclass 10, count 0 2006.201.04:42:16.68#ibcon#first serial, iclass 10, count 0 2006.201.04:42:16.68#ibcon#enter sib2, iclass 10, count 0 2006.201.04:42:16.68#ibcon#flushed, iclass 10, count 0 2006.201.04:42:16.68#ibcon#about to write, iclass 10, count 0 2006.201.04:42:16.68#ibcon#wrote, iclass 10, count 0 2006.201.04:42:16.68#ibcon#about to read 3, iclass 10, count 0 2006.201.04:42:16.70#ibcon#read 3, iclass 10, count 0 2006.201.04:42:16.70#ibcon#about to read 4, iclass 10, count 0 2006.201.04:42:16.70#ibcon#read 4, iclass 10, count 0 2006.201.04:42:16.70#ibcon#about to read 5, iclass 10, count 0 2006.201.04:42:16.70#ibcon#read 5, iclass 10, count 0 2006.201.04:42:16.70#ibcon#about to read 6, iclass 10, count 0 2006.201.04:42:16.70#ibcon#read 6, iclass 10, count 0 2006.201.04:42:16.70#ibcon#end of sib2, iclass 10, count 0 2006.201.04:42:16.70#ibcon#*mode == 0, iclass 10, count 0 2006.201.04:42:16.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.04:42:16.70#ibcon#[27=USB\r\n] 2006.201.04:42:16.70#ibcon#*before write, iclass 10, count 0 2006.201.04:42:16.70#ibcon#enter sib2, iclass 10, count 0 2006.201.04:42:16.70#ibcon#flushed, iclass 10, count 0 2006.201.04:42:16.70#ibcon#about to write, iclass 10, count 0 2006.201.04:42:16.70#ibcon#wrote, iclass 10, count 0 2006.201.04:42:16.70#ibcon#about to read 3, iclass 10, count 0 2006.201.04:42:16.73#ibcon#read 3, iclass 10, count 0 2006.201.04:42:16.73#ibcon#about to read 4, iclass 10, count 0 2006.201.04:42:16.73#ibcon#read 4, iclass 10, count 0 2006.201.04:42:16.73#ibcon#about to read 5, iclass 10, count 0 2006.201.04:42:16.73#ibcon#read 5, iclass 10, count 0 2006.201.04:42:16.73#ibcon#about to read 6, iclass 10, count 0 2006.201.04:42:16.73#ibcon#read 6, iclass 10, count 0 2006.201.04:42:16.73#ibcon#end of sib2, iclass 10, count 0 2006.201.04:42:16.73#ibcon#*after write, iclass 10, count 0 2006.201.04:42:16.73#ibcon#*before return 0, iclass 10, count 0 2006.201.04:42:16.73#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:16.73#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.04:42:16.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.04:42:16.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.04:42:16.73$vck44/vblo=3,649.99 2006.201.04:42:16.73#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.04:42:16.73#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.04:42:16.73#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:16.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:16.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:16.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:16.73#ibcon#enter wrdev, iclass 12, count 0 2006.201.04:42:16.73#ibcon#first serial, iclass 12, count 0 2006.201.04:42:16.73#ibcon#enter sib2, iclass 12, count 0 2006.201.04:42:16.73#ibcon#flushed, iclass 12, count 0 2006.201.04:42:16.73#ibcon#about to write, iclass 12, count 0 2006.201.04:42:16.73#ibcon#wrote, iclass 12, count 0 2006.201.04:42:16.73#ibcon#about to read 3, iclass 12, count 0 2006.201.04:42:16.75#ibcon#read 3, iclass 12, count 0 2006.201.04:42:16.75#ibcon#about to read 4, iclass 12, count 0 2006.201.04:42:16.75#ibcon#read 4, iclass 12, count 0 2006.201.04:42:16.75#ibcon#about to read 5, iclass 12, count 0 2006.201.04:42:16.75#ibcon#read 5, iclass 12, count 0 2006.201.04:42:16.75#ibcon#about to read 6, iclass 12, count 0 2006.201.04:42:16.75#ibcon#read 6, iclass 12, count 0 2006.201.04:42:16.75#ibcon#end of sib2, iclass 12, count 0 2006.201.04:42:16.75#ibcon#*mode == 0, iclass 12, count 0 2006.201.04:42:16.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.04:42:16.75#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:42:16.75#ibcon#*before write, iclass 12, count 0 2006.201.04:42:16.75#ibcon#enter sib2, iclass 12, count 0 2006.201.04:42:16.75#ibcon#flushed, iclass 12, count 0 2006.201.04:42:16.75#ibcon#about to write, iclass 12, count 0 2006.201.04:42:16.75#ibcon#wrote, iclass 12, count 0 2006.201.04:42:16.75#ibcon#about to read 3, iclass 12, count 0 2006.201.04:42:16.79#ibcon#read 3, iclass 12, count 0 2006.201.04:42:16.79#ibcon#about to read 4, iclass 12, count 0 2006.201.04:42:16.79#ibcon#read 4, iclass 12, count 0 2006.201.04:42:16.79#ibcon#about to read 5, iclass 12, count 0 2006.201.04:42:16.79#ibcon#read 5, iclass 12, count 0 2006.201.04:42:16.79#ibcon#about to read 6, iclass 12, count 0 2006.201.04:42:16.79#ibcon#read 6, iclass 12, count 0 2006.201.04:42:16.79#ibcon#end of sib2, iclass 12, count 0 2006.201.04:42:16.79#ibcon#*after write, iclass 12, count 0 2006.201.04:42:16.79#ibcon#*before return 0, iclass 12, count 0 2006.201.04:42:16.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:16.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.04:42:16.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.04:42:16.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.04:42:16.79$vck44/vb=3,4 2006.201.04:42:16.79#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.04:42:16.79#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.04:42:16.79#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:16.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:16.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:16.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:16.85#ibcon#enter wrdev, iclass 14, count 2 2006.201.04:42:16.85#ibcon#first serial, iclass 14, count 2 2006.201.04:42:16.85#ibcon#enter sib2, iclass 14, count 2 2006.201.04:42:16.85#ibcon#flushed, iclass 14, count 2 2006.201.04:42:16.85#ibcon#about to write, iclass 14, count 2 2006.201.04:42:16.85#ibcon#wrote, iclass 14, count 2 2006.201.04:42:16.85#ibcon#about to read 3, iclass 14, count 2 2006.201.04:42:16.87#ibcon#read 3, iclass 14, count 2 2006.201.04:42:16.87#ibcon#about to read 4, iclass 14, count 2 2006.201.04:42:16.87#ibcon#read 4, iclass 14, count 2 2006.201.04:42:16.87#ibcon#about to read 5, iclass 14, count 2 2006.201.04:42:16.87#ibcon#read 5, iclass 14, count 2 2006.201.04:42:16.87#ibcon#about to read 6, iclass 14, count 2 2006.201.04:42:16.87#ibcon#read 6, iclass 14, count 2 2006.201.04:42:16.87#ibcon#end of sib2, iclass 14, count 2 2006.201.04:42:16.87#ibcon#*mode == 0, iclass 14, count 2 2006.201.04:42:16.87#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.04:42:16.87#ibcon#[27=AT03-04\r\n] 2006.201.04:42:16.87#ibcon#*before write, iclass 14, count 2 2006.201.04:42:16.87#ibcon#enter sib2, iclass 14, count 2 2006.201.04:42:16.87#ibcon#flushed, iclass 14, count 2 2006.201.04:42:16.87#ibcon#about to write, iclass 14, count 2 2006.201.04:42:16.87#ibcon#wrote, iclass 14, count 2 2006.201.04:42:16.87#ibcon#about to read 3, iclass 14, count 2 2006.201.04:42:16.90#ibcon#read 3, iclass 14, count 2 2006.201.04:42:16.90#ibcon#about to read 4, iclass 14, count 2 2006.201.04:42:16.90#ibcon#read 4, iclass 14, count 2 2006.201.04:42:16.90#ibcon#about to read 5, iclass 14, count 2 2006.201.04:42:16.90#ibcon#read 5, iclass 14, count 2 2006.201.04:42:16.90#ibcon#about to read 6, iclass 14, count 2 2006.201.04:42:16.90#ibcon#read 6, iclass 14, count 2 2006.201.04:42:16.90#ibcon#end of sib2, iclass 14, count 2 2006.201.04:42:16.90#ibcon#*after write, iclass 14, count 2 2006.201.04:42:16.90#ibcon#*before return 0, iclass 14, count 2 2006.201.04:42:16.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:16.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.04:42:16.90#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.04:42:16.90#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:16.90#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:17.02#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:17.02#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:17.02#ibcon#enter wrdev, iclass 14, count 0 2006.201.04:42:17.02#ibcon#first serial, iclass 14, count 0 2006.201.04:42:17.02#ibcon#enter sib2, iclass 14, count 0 2006.201.04:42:17.02#ibcon#flushed, iclass 14, count 0 2006.201.04:42:17.02#ibcon#about to write, iclass 14, count 0 2006.201.04:42:17.02#ibcon#wrote, iclass 14, count 0 2006.201.04:42:17.02#ibcon#about to read 3, iclass 14, count 0 2006.201.04:42:17.04#ibcon#read 3, iclass 14, count 0 2006.201.04:42:17.04#ibcon#about to read 4, iclass 14, count 0 2006.201.04:42:17.04#ibcon#read 4, iclass 14, count 0 2006.201.04:42:17.04#ibcon#about to read 5, iclass 14, count 0 2006.201.04:42:17.04#ibcon#read 5, iclass 14, count 0 2006.201.04:42:17.04#ibcon#about to read 6, iclass 14, count 0 2006.201.04:42:17.04#ibcon#read 6, iclass 14, count 0 2006.201.04:42:17.04#ibcon#end of sib2, iclass 14, count 0 2006.201.04:42:17.04#ibcon#*mode == 0, iclass 14, count 0 2006.201.04:42:17.04#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.04:42:17.04#ibcon#[27=USB\r\n] 2006.201.04:42:17.04#ibcon#*before write, iclass 14, count 0 2006.201.04:42:17.04#ibcon#enter sib2, iclass 14, count 0 2006.201.04:42:17.04#ibcon#flushed, iclass 14, count 0 2006.201.04:42:17.04#ibcon#about to write, iclass 14, count 0 2006.201.04:42:17.04#ibcon#wrote, iclass 14, count 0 2006.201.04:42:17.04#ibcon#about to read 3, iclass 14, count 0 2006.201.04:42:17.07#ibcon#read 3, iclass 14, count 0 2006.201.04:42:17.07#ibcon#about to read 4, iclass 14, count 0 2006.201.04:42:17.07#ibcon#read 4, iclass 14, count 0 2006.201.04:42:17.07#ibcon#about to read 5, iclass 14, count 0 2006.201.04:42:17.07#ibcon#read 5, iclass 14, count 0 2006.201.04:42:17.07#ibcon#about to read 6, iclass 14, count 0 2006.201.04:42:17.07#ibcon#read 6, iclass 14, count 0 2006.201.04:42:17.07#ibcon#end of sib2, iclass 14, count 0 2006.201.04:42:17.07#ibcon#*after write, iclass 14, count 0 2006.201.04:42:17.07#ibcon#*before return 0, iclass 14, count 0 2006.201.04:42:17.07#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:17.07#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.04:42:17.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.04:42:17.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.04:42:17.07$vck44/vblo=4,679.99 2006.201.04:42:17.07#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.04:42:17.07#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.04:42:17.07#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:17.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:17.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:17.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:17.07#ibcon#enter wrdev, iclass 16, count 0 2006.201.04:42:17.07#ibcon#first serial, iclass 16, count 0 2006.201.04:42:17.07#ibcon#enter sib2, iclass 16, count 0 2006.201.04:42:17.07#ibcon#flushed, iclass 16, count 0 2006.201.04:42:17.07#ibcon#about to write, iclass 16, count 0 2006.201.04:42:17.07#ibcon#wrote, iclass 16, count 0 2006.201.04:42:17.07#ibcon#about to read 3, iclass 16, count 0 2006.201.04:42:17.09#ibcon#read 3, iclass 16, count 0 2006.201.04:42:17.09#ibcon#about to read 4, iclass 16, count 0 2006.201.04:42:17.09#ibcon#read 4, iclass 16, count 0 2006.201.04:42:17.09#ibcon#about to read 5, iclass 16, count 0 2006.201.04:42:17.09#ibcon#read 5, iclass 16, count 0 2006.201.04:42:17.09#ibcon#about to read 6, iclass 16, count 0 2006.201.04:42:17.09#ibcon#read 6, iclass 16, count 0 2006.201.04:42:17.09#ibcon#end of sib2, iclass 16, count 0 2006.201.04:42:17.09#ibcon#*mode == 0, iclass 16, count 0 2006.201.04:42:17.09#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.04:42:17.09#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:42:17.09#ibcon#*before write, iclass 16, count 0 2006.201.04:42:17.09#ibcon#enter sib2, iclass 16, count 0 2006.201.04:42:17.09#ibcon#flushed, iclass 16, count 0 2006.201.04:42:17.09#ibcon#about to write, iclass 16, count 0 2006.201.04:42:17.09#ibcon#wrote, iclass 16, count 0 2006.201.04:42:17.09#ibcon#about to read 3, iclass 16, count 0 2006.201.04:42:17.13#ibcon#read 3, iclass 16, count 0 2006.201.04:42:17.13#ibcon#about to read 4, iclass 16, count 0 2006.201.04:42:17.13#ibcon#read 4, iclass 16, count 0 2006.201.04:42:17.13#ibcon#about to read 5, iclass 16, count 0 2006.201.04:42:17.13#ibcon#read 5, iclass 16, count 0 2006.201.04:42:17.13#ibcon#about to read 6, iclass 16, count 0 2006.201.04:42:17.13#ibcon#read 6, iclass 16, count 0 2006.201.04:42:17.13#ibcon#end of sib2, iclass 16, count 0 2006.201.04:42:17.13#ibcon#*after write, iclass 16, count 0 2006.201.04:42:17.13#ibcon#*before return 0, iclass 16, count 0 2006.201.04:42:17.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:17.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.04:42:17.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.04:42:17.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.04:42:17.13$vck44/vb=4,5 2006.201.04:42:17.13#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.04:42:17.13#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.04:42:17.13#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:17.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:17.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:17.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:17.19#ibcon#enter wrdev, iclass 18, count 2 2006.201.04:42:17.19#ibcon#first serial, iclass 18, count 2 2006.201.04:42:17.19#ibcon#enter sib2, iclass 18, count 2 2006.201.04:42:17.19#ibcon#flushed, iclass 18, count 2 2006.201.04:42:17.19#ibcon#about to write, iclass 18, count 2 2006.201.04:42:17.19#ibcon#wrote, iclass 18, count 2 2006.201.04:42:17.19#ibcon#about to read 3, iclass 18, count 2 2006.201.04:42:17.21#ibcon#read 3, iclass 18, count 2 2006.201.04:42:17.21#ibcon#about to read 4, iclass 18, count 2 2006.201.04:42:17.21#ibcon#read 4, iclass 18, count 2 2006.201.04:42:17.21#ibcon#about to read 5, iclass 18, count 2 2006.201.04:42:17.21#ibcon#read 5, iclass 18, count 2 2006.201.04:42:17.21#ibcon#about to read 6, iclass 18, count 2 2006.201.04:42:17.21#ibcon#read 6, iclass 18, count 2 2006.201.04:42:17.21#ibcon#end of sib2, iclass 18, count 2 2006.201.04:42:17.21#ibcon#*mode == 0, iclass 18, count 2 2006.201.04:42:17.21#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.04:42:17.21#ibcon#[27=AT04-05\r\n] 2006.201.04:42:17.21#ibcon#*before write, iclass 18, count 2 2006.201.04:42:17.21#ibcon#enter sib2, iclass 18, count 2 2006.201.04:42:17.21#ibcon#flushed, iclass 18, count 2 2006.201.04:42:17.21#ibcon#about to write, iclass 18, count 2 2006.201.04:42:17.21#ibcon#wrote, iclass 18, count 2 2006.201.04:42:17.21#ibcon#about to read 3, iclass 18, count 2 2006.201.04:42:17.24#ibcon#read 3, iclass 18, count 2 2006.201.04:42:17.24#ibcon#about to read 4, iclass 18, count 2 2006.201.04:42:17.24#ibcon#read 4, iclass 18, count 2 2006.201.04:42:17.24#ibcon#about to read 5, iclass 18, count 2 2006.201.04:42:17.24#ibcon#read 5, iclass 18, count 2 2006.201.04:42:17.24#ibcon#about to read 6, iclass 18, count 2 2006.201.04:42:17.24#ibcon#read 6, iclass 18, count 2 2006.201.04:42:17.24#ibcon#end of sib2, iclass 18, count 2 2006.201.04:42:17.24#ibcon#*after write, iclass 18, count 2 2006.201.04:42:17.24#ibcon#*before return 0, iclass 18, count 2 2006.201.04:42:17.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:17.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.04:42:17.24#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.04:42:17.24#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:17.24#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:17.36#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:17.36#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:17.36#ibcon#enter wrdev, iclass 18, count 0 2006.201.04:42:17.36#ibcon#first serial, iclass 18, count 0 2006.201.04:42:17.36#ibcon#enter sib2, iclass 18, count 0 2006.201.04:42:17.36#ibcon#flushed, iclass 18, count 0 2006.201.04:42:17.36#ibcon#about to write, iclass 18, count 0 2006.201.04:42:17.36#ibcon#wrote, iclass 18, count 0 2006.201.04:42:17.36#ibcon#about to read 3, iclass 18, count 0 2006.201.04:42:17.38#ibcon#read 3, iclass 18, count 0 2006.201.04:42:17.38#ibcon#about to read 4, iclass 18, count 0 2006.201.04:42:17.38#ibcon#read 4, iclass 18, count 0 2006.201.04:42:17.38#ibcon#about to read 5, iclass 18, count 0 2006.201.04:42:17.38#ibcon#read 5, iclass 18, count 0 2006.201.04:42:17.38#ibcon#about to read 6, iclass 18, count 0 2006.201.04:42:17.38#ibcon#read 6, iclass 18, count 0 2006.201.04:42:17.38#ibcon#end of sib2, iclass 18, count 0 2006.201.04:42:17.38#ibcon#*mode == 0, iclass 18, count 0 2006.201.04:42:17.38#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.04:42:17.38#ibcon#[27=USB\r\n] 2006.201.04:42:17.38#ibcon#*before write, iclass 18, count 0 2006.201.04:42:17.38#ibcon#enter sib2, iclass 18, count 0 2006.201.04:42:17.38#ibcon#flushed, iclass 18, count 0 2006.201.04:42:17.38#ibcon#about to write, iclass 18, count 0 2006.201.04:42:17.38#ibcon#wrote, iclass 18, count 0 2006.201.04:42:17.38#ibcon#about to read 3, iclass 18, count 0 2006.201.04:42:17.41#ibcon#read 3, iclass 18, count 0 2006.201.04:42:17.41#ibcon#about to read 4, iclass 18, count 0 2006.201.04:42:17.41#ibcon#read 4, iclass 18, count 0 2006.201.04:42:17.41#ibcon#about to read 5, iclass 18, count 0 2006.201.04:42:17.41#ibcon#read 5, iclass 18, count 0 2006.201.04:42:17.41#ibcon#about to read 6, iclass 18, count 0 2006.201.04:42:17.41#ibcon#read 6, iclass 18, count 0 2006.201.04:42:17.41#ibcon#end of sib2, iclass 18, count 0 2006.201.04:42:17.41#ibcon#*after write, iclass 18, count 0 2006.201.04:42:17.41#ibcon#*before return 0, iclass 18, count 0 2006.201.04:42:17.41#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:17.41#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.04:42:17.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.04:42:17.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.04:42:17.41$vck44/vblo=5,709.99 2006.201.04:42:17.41#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.04:42:17.41#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.04:42:17.41#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:17.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:17.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:17.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:17.41#ibcon#enter wrdev, iclass 20, count 0 2006.201.04:42:17.41#ibcon#first serial, iclass 20, count 0 2006.201.04:42:17.41#ibcon#enter sib2, iclass 20, count 0 2006.201.04:42:17.41#ibcon#flushed, iclass 20, count 0 2006.201.04:42:17.41#ibcon#about to write, iclass 20, count 0 2006.201.04:42:17.41#ibcon#wrote, iclass 20, count 0 2006.201.04:42:17.41#ibcon#about to read 3, iclass 20, count 0 2006.201.04:42:17.43#ibcon#read 3, iclass 20, count 0 2006.201.04:42:17.43#ibcon#about to read 4, iclass 20, count 0 2006.201.04:42:17.43#ibcon#read 4, iclass 20, count 0 2006.201.04:42:17.43#ibcon#about to read 5, iclass 20, count 0 2006.201.04:42:17.43#ibcon#read 5, iclass 20, count 0 2006.201.04:42:17.43#ibcon#about to read 6, iclass 20, count 0 2006.201.04:42:17.43#ibcon#read 6, iclass 20, count 0 2006.201.04:42:17.43#ibcon#end of sib2, iclass 20, count 0 2006.201.04:42:17.43#ibcon#*mode == 0, iclass 20, count 0 2006.201.04:42:17.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.04:42:17.43#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:42:17.43#ibcon#*before write, iclass 20, count 0 2006.201.04:42:17.43#ibcon#enter sib2, iclass 20, count 0 2006.201.04:42:17.43#ibcon#flushed, iclass 20, count 0 2006.201.04:42:17.43#ibcon#about to write, iclass 20, count 0 2006.201.04:42:17.43#ibcon#wrote, iclass 20, count 0 2006.201.04:42:17.43#ibcon#about to read 3, iclass 20, count 0 2006.201.04:42:17.47#ibcon#read 3, iclass 20, count 0 2006.201.04:42:17.47#ibcon#about to read 4, iclass 20, count 0 2006.201.04:42:17.47#ibcon#read 4, iclass 20, count 0 2006.201.04:42:17.47#ibcon#about to read 5, iclass 20, count 0 2006.201.04:42:17.47#ibcon#read 5, iclass 20, count 0 2006.201.04:42:17.47#ibcon#about to read 6, iclass 20, count 0 2006.201.04:42:17.47#ibcon#read 6, iclass 20, count 0 2006.201.04:42:17.47#ibcon#end of sib2, iclass 20, count 0 2006.201.04:42:17.47#ibcon#*after write, iclass 20, count 0 2006.201.04:42:17.47#ibcon#*before return 0, iclass 20, count 0 2006.201.04:42:17.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:17.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.04:42:17.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.04:42:17.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.04:42:17.47$vck44/vb=5,4 2006.201.04:42:17.47#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.04:42:17.47#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.04:42:17.47#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:17.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:17.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:17.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:17.53#ibcon#enter wrdev, iclass 22, count 2 2006.201.04:42:17.53#ibcon#first serial, iclass 22, count 2 2006.201.04:42:17.53#ibcon#enter sib2, iclass 22, count 2 2006.201.04:42:17.53#ibcon#flushed, iclass 22, count 2 2006.201.04:42:17.53#ibcon#about to write, iclass 22, count 2 2006.201.04:42:17.53#ibcon#wrote, iclass 22, count 2 2006.201.04:42:17.53#ibcon#about to read 3, iclass 22, count 2 2006.201.04:42:17.55#ibcon#read 3, iclass 22, count 2 2006.201.04:42:17.55#ibcon#about to read 4, iclass 22, count 2 2006.201.04:42:17.55#ibcon#read 4, iclass 22, count 2 2006.201.04:42:17.55#ibcon#about to read 5, iclass 22, count 2 2006.201.04:42:17.55#ibcon#read 5, iclass 22, count 2 2006.201.04:42:17.55#ibcon#about to read 6, iclass 22, count 2 2006.201.04:42:17.55#ibcon#read 6, iclass 22, count 2 2006.201.04:42:17.55#ibcon#end of sib2, iclass 22, count 2 2006.201.04:42:17.55#ibcon#*mode == 0, iclass 22, count 2 2006.201.04:42:17.55#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.04:42:17.55#ibcon#[27=AT05-04\r\n] 2006.201.04:42:17.55#ibcon#*before write, iclass 22, count 2 2006.201.04:42:17.55#ibcon#enter sib2, iclass 22, count 2 2006.201.04:42:17.55#ibcon#flushed, iclass 22, count 2 2006.201.04:42:17.55#ibcon#about to write, iclass 22, count 2 2006.201.04:42:17.55#ibcon#wrote, iclass 22, count 2 2006.201.04:42:17.55#ibcon#about to read 3, iclass 22, count 2 2006.201.04:42:17.58#ibcon#read 3, iclass 22, count 2 2006.201.04:42:17.63#ibcon#about to read 4, iclass 22, count 2 2006.201.04:42:17.63#ibcon#read 4, iclass 22, count 2 2006.201.04:42:17.63#ibcon#about to read 5, iclass 22, count 2 2006.201.04:42:17.63#ibcon#read 5, iclass 22, count 2 2006.201.04:42:17.63#ibcon#about to read 6, iclass 22, count 2 2006.201.04:42:17.63#ibcon#read 6, iclass 22, count 2 2006.201.04:42:17.63#ibcon#end of sib2, iclass 22, count 2 2006.201.04:42:17.63#ibcon#*after write, iclass 22, count 2 2006.201.04:42:17.63#ibcon#*before return 0, iclass 22, count 2 2006.201.04:42:17.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:17.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.04:42:17.63#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.04:42:17.63#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:17.63#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:17.75#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:17.75#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:17.75#ibcon#enter wrdev, iclass 22, count 0 2006.201.04:42:17.75#ibcon#first serial, iclass 22, count 0 2006.201.04:42:17.75#ibcon#enter sib2, iclass 22, count 0 2006.201.04:42:17.75#ibcon#flushed, iclass 22, count 0 2006.201.04:42:17.75#ibcon#about to write, iclass 22, count 0 2006.201.04:42:17.75#ibcon#wrote, iclass 22, count 0 2006.201.04:42:17.75#ibcon#about to read 3, iclass 22, count 0 2006.201.04:42:17.77#ibcon#read 3, iclass 22, count 0 2006.201.04:42:17.77#ibcon#about to read 4, iclass 22, count 0 2006.201.04:42:17.77#ibcon#read 4, iclass 22, count 0 2006.201.04:42:17.77#ibcon#about to read 5, iclass 22, count 0 2006.201.04:42:17.77#ibcon#read 5, iclass 22, count 0 2006.201.04:42:17.77#ibcon#about to read 6, iclass 22, count 0 2006.201.04:42:17.77#ibcon#read 6, iclass 22, count 0 2006.201.04:42:17.77#ibcon#end of sib2, iclass 22, count 0 2006.201.04:42:17.77#ibcon#*mode == 0, iclass 22, count 0 2006.201.04:42:17.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.04:42:17.77#ibcon#[27=USB\r\n] 2006.201.04:42:17.77#ibcon#*before write, iclass 22, count 0 2006.201.04:42:17.77#ibcon#enter sib2, iclass 22, count 0 2006.201.04:42:17.77#ibcon#flushed, iclass 22, count 0 2006.201.04:42:17.77#ibcon#about to write, iclass 22, count 0 2006.201.04:42:17.77#ibcon#wrote, iclass 22, count 0 2006.201.04:42:17.77#ibcon#about to read 3, iclass 22, count 0 2006.201.04:42:17.80#ibcon#read 3, iclass 22, count 0 2006.201.04:42:17.80#ibcon#about to read 4, iclass 22, count 0 2006.201.04:42:17.80#ibcon#read 4, iclass 22, count 0 2006.201.04:42:17.80#ibcon#about to read 5, iclass 22, count 0 2006.201.04:42:17.80#ibcon#read 5, iclass 22, count 0 2006.201.04:42:17.80#ibcon#about to read 6, iclass 22, count 0 2006.201.04:42:17.80#ibcon#read 6, iclass 22, count 0 2006.201.04:42:17.80#ibcon#end of sib2, iclass 22, count 0 2006.201.04:42:17.80#ibcon#*after write, iclass 22, count 0 2006.201.04:42:17.80#ibcon#*before return 0, iclass 22, count 0 2006.201.04:42:17.80#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:17.80#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.04:42:17.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.04:42:17.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.04:42:17.80$vck44/vblo=6,719.99 2006.201.04:42:17.80#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.04:42:17.80#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.04:42:17.80#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:17.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:17.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:17.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:17.80#ibcon#enter wrdev, iclass 24, count 0 2006.201.04:42:17.80#ibcon#first serial, iclass 24, count 0 2006.201.04:42:17.80#ibcon#enter sib2, iclass 24, count 0 2006.201.04:42:17.80#ibcon#flushed, iclass 24, count 0 2006.201.04:42:17.80#ibcon#about to write, iclass 24, count 0 2006.201.04:42:17.80#ibcon#wrote, iclass 24, count 0 2006.201.04:42:17.80#ibcon#about to read 3, iclass 24, count 0 2006.201.04:42:17.82#ibcon#read 3, iclass 24, count 0 2006.201.04:42:17.82#ibcon#about to read 4, iclass 24, count 0 2006.201.04:42:17.82#ibcon#read 4, iclass 24, count 0 2006.201.04:42:17.82#ibcon#about to read 5, iclass 24, count 0 2006.201.04:42:17.82#ibcon#read 5, iclass 24, count 0 2006.201.04:42:17.82#ibcon#about to read 6, iclass 24, count 0 2006.201.04:42:17.82#ibcon#read 6, iclass 24, count 0 2006.201.04:42:17.82#ibcon#end of sib2, iclass 24, count 0 2006.201.04:42:17.82#ibcon#*mode == 0, iclass 24, count 0 2006.201.04:42:17.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.04:42:17.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:42:17.82#ibcon#*before write, iclass 24, count 0 2006.201.04:42:17.82#ibcon#enter sib2, iclass 24, count 0 2006.201.04:42:17.82#ibcon#flushed, iclass 24, count 0 2006.201.04:42:17.82#ibcon#about to write, iclass 24, count 0 2006.201.04:42:17.82#ibcon#wrote, iclass 24, count 0 2006.201.04:42:17.82#ibcon#about to read 3, iclass 24, count 0 2006.201.04:42:17.86#ibcon#read 3, iclass 24, count 0 2006.201.04:42:17.86#ibcon#about to read 4, iclass 24, count 0 2006.201.04:42:17.86#ibcon#read 4, iclass 24, count 0 2006.201.04:42:17.86#ibcon#about to read 5, iclass 24, count 0 2006.201.04:42:17.86#ibcon#read 5, iclass 24, count 0 2006.201.04:42:17.86#ibcon#about to read 6, iclass 24, count 0 2006.201.04:42:17.86#ibcon#read 6, iclass 24, count 0 2006.201.04:42:17.86#ibcon#end of sib2, iclass 24, count 0 2006.201.04:42:17.86#ibcon#*after write, iclass 24, count 0 2006.201.04:42:17.86#ibcon#*before return 0, iclass 24, count 0 2006.201.04:42:17.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:17.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.04:42:17.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.04:42:17.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.04:42:17.86$vck44/vb=6,4 2006.201.04:42:17.86#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.04:42:17.86#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.04:42:17.86#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:17.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:17.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:17.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:17.92#ibcon#enter wrdev, iclass 26, count 2 2006.201.04:42:17.92#ibcon#first serial, iclass 26, count 2 2006.201.04:42:17.92#ibcon#enter sib2, iclass 26, count 2 2006.201.04:42:17.92#ibcon#flushed, iclass 26, count 2 2006.201.04:42:17.92#ibcon#about to write, iclass 26, count 2 2006.201.04:42:17.92#ibcon#wrote, iclass 26, count 2 2006.201.04:42:17.92#ibcon#about to read 3, iclass 26, count 2 2006.201.04:42:17.94#ibcon#read 3, iclass 26, count 2 2006.201.04:42:17.94#ibcon#about to read 4, iclass 26, count 2 2006.201.04:42:17.94#ibcon#read 4, iclass 26, count 2 2006.201.04:42:17.94#ibcon#about to read 5, iclass 26, count 2 2006.201.04:42:17.94#ibcon#read 5, iclass 26, count 2 2006.201.04:42:17.94#ibcon#about to read 6, iclass 26, count 2 2006.201.04:42:17.94#ibcon#read 6, iclass 26, count 2 2006.201.04:42:17.94#ibcon#end of sib2, iclass 26, count 2 2006.201.04:42:17.94#ibcon#*mode == 0, iclass 26, count 2 2006.201.04:42:17.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.04:42:17.94#ibcon#[27=AT06-04\r\n] 2006.201.04:42:17.94#ibcon#*before write, iclass 26, count 2 2006.201.04:42:17.94#ibcon#enter sib2, iclass 26, count 2 2006.201.04:42:17.94#ibcon#flushed, iclass 26, count 2 2006.201.04:42:17.94#ibcon#about to write, iclass 26, count 2 2006.201.04:42:17.94#ibcon#wrote, iclass 26, count 2 2006.201.04:42:17.94#ibcon#about to read 3, iclass 26, count 2 2006.201.04:42:17.97#ibcon#read 3, iclass 26, count 2 2006.201.04:42:17.97#ibcon#about to read 4, iclass 26, count 2 2006.201.04:42:17.97#ibcon#read 4, iclass 26, count 2 2006.201.04:42:17.97#ibcon#about to read 5, iclass 26, count 2 2006.201.04:42:17.97#ibcon#read 5, iclass 26, count 2 2006.201.04:42:17.97#ibcon#about to read 6, iclass 26, count 2 2006.201.04:42:17.97#ibcon#read 6, iclass 26, count 2 2006.201.04:42:17.97#ibcon#end of sib2, iclass 26, count 2 2006.201.04:42:17.97#ibcon#*after write, iclass 26, count 2 2006.201.04:42:17.97#ibcon#*before return 0, iclass 26, count 2 2006.201.04:42:17.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:17.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.04:42:17.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.04:42:17.97#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:17.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:18.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:18.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:18.09#ibcon#enter wrdev, iclass 26, count 0 2006.201.04:42:18.09#ibcon#first serial, iclass 26, count 0 2006.201.04:42:18.09#ibcon#enter sib2, iclass 26, count 0 2006.201.04:42:18.09#ibcon#flushed, iclass 26, count 0 2006.201.04:42:18.09#ibcon#about to write, iclass 26, count 0 2006.201.04:42:18.09#ibcon#wrote, iclass 26, count 0 2006.201.04:42:18.09#ibcon#about to read 3, iclass 26, count 0 2006.201.04:42:18.11#ibcon#read 3, iclass 26, count 0 2006.201.04:42:18.11#ibcon#about to read 4, iclass 26, count 0 2006.201.04:42:18.11#ibcon#read 4, iclass 26, count 0 2006.201.04:42:18.11#ibcon#about to read 5, iclass 26, count 0 2006.201.04:42:18.11#ibcon#read 5, iclass 26, count 0 2006.201.04:42:18.11#ibcon#about to read 6, iclass 26, count 0 2006.201.04:42:18.11#ibcon#read 6, iclass 26, count 0 2006.201.04:42:18.11#ibcon#end of sib2, iclass 26, count 0 2006.201.04:42:18.11#ibcon#*mode == 0, iclass 26, count 0 2006.201.04:42:18.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.04:42:18.11#ibcon#[27=USB\r\n] 2006.201.04:42:18.11#ibcon#*before write, iclass 26, count 0 2006.201.04:42:18.11#ibcon#enter sib2, iclass 26, count 0 2006.201.04:42:18.11#ibcon#flushed, iclass 26, count 0 2006.201.04:42:18.11#ibcon#about to write, iclass 26, count 0 2006.201.04:42:18.11#ibcon#wrote, iclass 26, count 0 2006.201.04:42:18.11#ibcon#about to read 3, iclass 26, count 0 2006.201.04:42:18.14#ibcon#read 3, iclass 26, count 0 2006.201.04:42:18.14#ibcon#about to read 4, iclass 26, count 0 2006.201.04:42:18.14#ibcon#read 4, iclass 26, count 0 2006.201.04:42:18.14#ibcon#about to read 5, iclass 26, count 0 2006.201.04:42:18.14#ibcon#read 5, iclass 26, count 0 2006.201.04:42:18.14#ibcon#about to read 6, iclass 26, count 0 2006.201.04:42:18.14#ibcon#read 6, iclass 26, count 0 2006.201.04:42:18.14#ibcon#end of sib2, iclass 26, count 0 2006.201.04:42:18.14#ibcon#*after write, iclass 26, count 0 2006.201.04:42:18.14#ibcon#*before return 0, iclass 26, count 0 2006.201.04:42:18.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:18.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.04:42:18.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.04:42:18.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.04:42:18.14$vck44/vblo=7,734.99 2006.201.04:42:18.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.04:42:18.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.04:42:18.14#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:18.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:18.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:18.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:18.14#ibcon#enter wrdev, iclass 28, count 0 2006.201.04:42:18.14#ibcon#first serial, iclass 28, count 0 2006.201.04:42:18.14#ibcon#enter sib2, iclass 28, count 0 2006.201.04:42:18.14#ibcon#flushed, iclass 28, count 0 2006.201.04:42:18.14#ibcon#about to write, iclass 28, count 0 2006.201.04:42:18.14#ibcon#wrote, iclass 28, count 0 2006.201.04:42:18.14#ibcon#about to read 3, iclass 28, count 0 2006.201.04:42:18.16#ibcon#read 3, iclass 28, count 0 2006.201.04:42:18.16#ibcon#about to read 4, iclass 28, count 0 2006.201.04:42:18.16#ibcon#read 4, iclass 28, count 0 2006.201.04:42:18.16#ibcon#about to read 5, iclass 28, count 0 2006.201.04:42:18.16#ibcon#read 5, iclass 28, count 0 2006.201.04:42:18.16#ibcon#about to read 6, iclass 28, count 0 2006.201.04:42:18.16#ibcon#read 6, iclass 28, count 0 2006.201.04:42:18.16#ibcon#end of sib2, iclass 28, count 0 2006.201.04:42:18.16#ibcon#*mode == 0, iclass 28, count 0 2006.201.04:42:18.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.04:42:18.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:42:18.16#ibcon#*before write, iclass 28, count 0 2006.201.04:42:18.16#ibcon#enter sib2, iclass 28, count 0 2006.201.04:42:18.16#ibcon#flushed, iclass 28, count 0 2006.201.04:42:18.16#ibcon#about to write, iclass 28, count 0 2006.201.04:42:18.16#ibcon#wrote, iclass 28, count 0 2006.201.04:42:18.16#ibcon#about to read 3, iclass 28, count 0 2006.201.04:42:18.20#ibcon#read 3, iclass 28, count 0 2006.201.04:42:18.20#ibcon#about to read 4, iclass 28, count 0 2006.201.04:42:18.20#ibcon#read 4, iclass 28, count 0 2006.201.04:42:18.20#ibcon#about to read 5, iclass 28, count 0 2006.201.04:42:18.20#ibcon#read 5, iclass 28, count 0 2006.201.04:42:18.20#ibcon#about to read 6, iclass 28, count 0 2006.201.04:42:18.20#ibcon#read 6, iclass 28, count 0 2006.201.04:42:18.20#ibcon#end of sib2, iclass 28, count 0 2006.201.04:42:18.20#ibcon#*after write, iclass 28, count 0 2006.201.04:42:18.20#ibcon#*before return 0, iclass 28, count 0 2006.201.04:42:18.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:18.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.04:42:18.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.04:42:18.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.04:42:18.20$vck44/vb=7,4 2006.201.04:42:18.20#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.04:42:18.20#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.04:42:18.20#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:18.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:18.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:18.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:18.26#ibcon#enter wrdev, iclass 30, count 2 2006.201.04:42:18.26#ibcon#first serial, iclass 30, count 2 2006.201.04:42:18.26#ibcon#enter sib2, iclass 30, count 2 2006.201.04:42:18.26#ibcon#flushed, iclass 30, count 2 2006.201.04:42:18.26#ibcon#about to write, iclass 30, count 2 2006.201.04:42:18.26#ibcon#wrote, iclass 30, count 2 2006.201.04:42:18.26#ibcon#about to read 3, iclass 30, count 2 2006.201.04:42:18.28#ibcon#read 3, iclass 30, count 2 2006.201.04:42:18.28#ibcon#about to read 4, iclass 30, count 2 2006.201.04:42:18.28#ibcon#read 4, iclass 30, count 2 2006.201.04:42:18.28#ibcon#about to read 5, iclass 30, count 2 2006.201.04:42:18.28#ibcon#read 5, iclass 30, count 2 2006.201.04:42:18.28#ibcon#about to read 6, iclass 30, count 2 2006.201.04:42:18.28#ibcon#read 6, iclass 30, count 2 2006.201.04:42:18.28#ibcon#end of sib2, iclass 30, count 2 2006.201.04:42:18.28#ibcon#*mode == 0, iclass 30, count 2 2006.201.04:42:18.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.04:42:18.28#ibcon#[27=AT07-04\r\n] 2006.201.04:42:18.28#ibcon#*before write, iclass 30, count 2 2006.201.04:42:18.28#ibcon#enter sib2, iclass 30, count 2 2006.201.04:42:18.28#ibcon#flushed, iclass 30, count 2 2006.201.04:42:18.28#ibcon#about to write, iclass 30, count 2 2006.201.04:42:18.28#ibcon#wrote, iclass 30, count 2 2006.201.04:42:18.28#ibcon#about to read 3, iclass 30, count 2 2006.201.04:42:18.31#ibcon#read 3, iclass 30, count 2 2006.201.04:42:18.31#ibcon#about to read 4, iclass 30, count 2 2006.201.04:42:18.31#ibcon#read 4, iclass 30, count 2 2006.201.04:42:18.31#ibcon#about to read 5, iclass 30, count 2 2006.201.04:42:18.31#ibcon#read 5, iclass 30, count 2 2006.201.04:42:18.31#ibcon#about to read 6, iclass 30, count 2 2006.201.04:42:18.31#ibcon#read 6, iclass 30, count 2 2006.201.04:42:18.31#ibcon#end of sib2, iclass 30, count 2 2006.201.04:42:18.31#ibcon#*after write, iclass 30, count 2 2006.201.04:42:18.31#ibcon#*before return 0, iclass 30, count 2 2006.201.04:42:18.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:18.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.04:42:18.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.04:42:18.31#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:18.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:18.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:18.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:18.43#ibcon#enter wrdev, iclass 30, count 0 2006.201.04:42:18.43#ibcon#first serial, iclass 30, count 0 2006.201.04:42:18.43#ibcon#enter sib2, iclass 30, count 0 2006.201.04:42:18.43#ibcon#flushed, iclass 30, count 0 2006.201.04:42:18.43#ibcon#about to write, iclass 30, count 0 2006.201.04:42:18.43#ibcon#wrote, iclass 30, count 0 2006.201.04:42:18.43#ibcon#about to read 3, iclass 30, count 0 2006.201.04:42:18.45#ibcon#read 3, iclass 30, count 0 2006.201.04:42:18.45#ibcon#about to read 4, iclass 30, count 0 2006.201.04:42:18.45#ibcon#read 4, iclass 30, count 0 2006.201.04:42:18.45#ibcon#about to read 5, iclass 30, count 0 2006.201.04:42:18.45#ibcon#read 5, iclass 30, count 0 2006.201.04:42:18.45#ibcon#about to read 6, iclass 30, count 0 2006.201.04:42:18.45#ibcon#read 6, iclass 30, count 0 2006.201.04:42:18.45#ibcon#end of sib2, iclass 30, count 0 2006.201.04:42:18.45#ibcon#*mode == 0, iclass 30, count 0 2006.201.04:42:18.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.04:42:18.45#ibcon#[27=USB\r\n] 2006.201.04:42:18.45#ibcon#*before write, iclass 30, count 0 2006.201.04:42:18.45#ibcon#enter sib2, iclass 30, count 0 2006.201.04:42:18.45#ibcon#flushed, iclass 30, count 0 2006.201.04:42:18.45#ibcon#about to write, iclass 30, count 0 2006.201.04:42:18.45#ibcon#wrote, iclass 30, count 0 2006.201.04:42:18.45#ibcon#about to read 3, iclass 30, count 0 2006.201.04:42:18.48#ibcon#read 3, iclass 30, count 0 2006.201.04:42:18.48#ibcon#about to read 4, iclass 30, count 0 2006.201.04:42:18.48#ibcon#read 4, iclass 30, count 0 2006.201.04:42:18.48#ibcon#about to read 5, iclass 30, count 0 2006.201.04:42:18.48#ibcon#read 5, iclass 30, count 0 2006.201.04:42:18.48#ibcon#about to read 6, iclass 30, count 0 2006.201.04:42:18.48#ibcon#read 6, iclass 30, count 0 2006.201.04:42:18.48#ibcon#end of sib2, iclass 30, count 0 2006.201.04:42:18.48#ibcon#*after write, iclass 30, count 0 2006.201.04:42:18.48#ibcon#*before return 0, iclass 30, count 0 2006.201.04:42:18.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:18.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.04:42:18.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.04:42:18.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.04:42:18.48$vck44/vblo=8,744.99 2006.201.04:42:18.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.04:42:18.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.04:42:18.48#ibcon#ireg 17 cls_cnt 0 2006.201.04:42:18.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:18.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:18.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:18.48#ibcon#enter wrdev, iclass 32, count 0 2006.201.04:42:18.48#ibcon#first serial, iclass 32, count 0 2006.201.04:42:18.48#ibcon#enter sib2, iclass 32, count 0 2006.201.04:42:18.48#ibcon#flushed, iclass 32, count 0 2006.201.04:42:18.48#ibcon#about to write, iclass 32, count 0 2006.201.04:42:18.48#ibcon#wrote, iclass 32, count 0 2006.201.04:42:18.48#ibcon#about to read 3, iclass 32, count 0 2006.201.04:42:18.50#ibcon#read 3, iclass 32, count 0 2006.201.04:42:18.50#ibcon#about to read 4, iclass 32, count 0 2006.201.04:42:18.50#ibcon#read 4, iclass 32, count 0 2006.201.04:42:18.50#ibcon#about to read 5, iclass 32, count 0 2006.201.04:42:18.50#ibcon#read 5, iclass 32, count 0 2006.201.04:42:18.50#ibcon#about to read 6, iclass 32, count 0 2006.201.04:42:18.50#ibcon#read 6, iclass 32, count 0 2006.201.04:42:18.50#ibcon#end of sib2, iclass 32, count 0 2006.201.04:42:18.50#ibcon#*mode == 0, iclass 32, count 0 2006.201.04:42:18.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.04:42:18.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:42:18.50#ibcon#*before write, iclass 32, count 0 2006.201.04:42:18.50#ibcon#enter sib2, iclass 32, count 0 2006.201.04:42:18.50#ibcon#flushed, iclass 32, count 0 2006.201.04:42:18.50#ibcon#about to write, iclass 32, count 0 2006.201.04:42:18.50#ibcon#wrote, iclass 32, count 0 2006.201.04:42:18.50#ibcon#about to read 3, iclass 32, count 0 2006.201.04:42:18.54#ibcon#read 3, iclass 32, count 0 2006.201.04:42:18.54#ibcon#about to read 4, iclass 32, count 0 2006.201.04:42:18.54#ibcon#read 4, iclass 32, count 0 2006.201.04:42:18.54#ibcon#about to read 5, iclass 32, count 0 2006.201.04:42:18.54#ibcon#read 5, iclass 32, count 0 2006.201.04:42:18.54#ibcon#about to read 6, iclass 32, count 0 2006.201.04:42:18.54#ibcon#read 6, iclass 32, count 0 2006.201.04:42:18.54#ibcon#end of sib2, iclass 32, count 0 2006.201.04:42:18.54#ibcon#*after write, iclass 32, count 0 2006.201.04:42:18.54#ibcon#*before return 0, iclass 32, count 0 2006.201.04:42:18.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:18.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.04:42:18.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.04:42:18.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.04:42:18.54$vck44/vb=8,4 2006.201.04:42:18.54#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.04:42:18.54#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.04:42:18.54#ibcon#ireg 11 cls_cnt 2 2006.201.04:42:18.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:18.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:18.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:18.60#ibcon#enter wrdev, iclass 34, count 2 2006.201.04:42:18.60#ibcon#first serial, iclass 34, count 2 2006.201.04:42:18.60#ibcon#enter sib2, iclass 34, count 2 2006.201.04:42:18.60#ibcon#flushed, iclass 34, count 2 2006.201.04:42:18.60#ibcon#about to write, iclass 34, count 2 2006.201.04:42:18.60#ibcon#wrote, iclass 34, count 2 2006.201.04:42:18.60#ibcon#about to read 3, iclass 34, count 2 2006.201.04:42:18.62#ibcon#read 3, iclass 34, count 2 2006.201.04:42:18.62#ibcon#about to read 4, iclass 34, count 2 2006.201.04:42:18.62#ibcon#read 4, iclass 34, count 2 2006.201.04:42:18.62#ibcon#about to read 5, iclass 34, count 2 2006.201.04:42:18.62#ibcon#read 5, iclass 34, count 2 2006.201.04:42:18.62#ibcon#about to read 6, iclass 34, count 2 2006.201.04:42:18.62#ibcon#read 6, iclass 34, count 2 2006.201.04:42:18.62#ibcon#end of sib2, iclass 34, count 2 2006.201.04:42:18.62#ibcon#*mode == 0, iclass 34, count 2 2006.201.04:42:18.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.04:42:18.62#ibcon#[27=AT08-04\r\n] 2006.201.04:42:18.62#ibcon#*before write, iclass 34, count 2 2006.201.04:42:18.62#ibcon#enter sib2, iclass 34, count 2 2006.201.04:42:18.62#ibcon#flushed, iclass 34, count 2 2006.201.04:42:18.62#ibcon#about to write, iclass 34, count 2 2006.201.04:42:18.68#ibcon#wrote, iclass 34, count 2 2006.201.04:42:18.68#ibcon#about to read 3, iclass 34, count 2 2006.201.04:42:18.72#ibcon#read 3, iclass 34, count 2 2006.201.04:42:18.72#ibcon#about to read 4, iclass 34, count 2 2006.201.04:42:18.72#ibcon#read 4, iclass 34, count 2 2006.201.04:42:18.72#ibcon#about to read 5, iclass 34, count 2 2006.201.04:42:18.72#ibcon#read 5, iclass 34, count 2 2006.201.04:42:18.72#ibcon#about to read 6, iclass 34, count 2 2006.201.04:42:18.72#ibcon#read 6, iclass 34, count 2 2006.201.04:42:18.72#ibcon#end of sib2, iclass 34, count 2 2006.201.04:42:18.72#ibcon#*after write, iclass 34, count 2 2006.201.04:42:18.72#ibcon#*before return 0, iclass 34, count 2 2006.201.04:42:18.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:18.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.04:42:18.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.04:42:18.72#ibcon#ireg 7 cls_cnt 0 2006.201.04:42:18.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:18.78#abcon#<5=/04 3.3 5.8 22.99 911004.1\r\n> 2006.201.04:42:18.80#abcon#{5=INTERFACE CLEAR} 2006.201.04:42:18.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:18.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:18.84#ibcon#enter wrdev, iclass 34, count 0 2006.201.04:42:18.84#ibcon#first serial, iclass 34, count 0 2006.201.04:42:18.84#ibcon#enter sib2, iclass 34, count 0 2006.201.04:42:18.84#ibcon#flushed, iclass 34, count 0 2006.201.04:42:18.84#ibcon#about to write, iclass 34, count 0 2006.201.04:42:18.84#ibcon#wrote, iclass 34, count 0 2006.201.04:42:18.84#ibcon#about to read 3, iclass 34, count 0 2006.201.04:42:18.86#ibcon#read 3, iclass 34, count 0 2006.201.04:42:18.86#ibcon#about to read 4, iclass 34, count 0 2006.201.04:42:18.86#ibcon#read 4, iclass 34, count 0 2006.201.04:42:18.86#ibcon#about to read 5, iclass 34, count 0 2006.201.04:42:18.86#ibcon#read 5, iclass 34, count 0 2006.201.04:42:18.86#ibcon#about to read 6, iclass 34, count 0 2006.201.04:42:18.86#ibcon#read 6, iclass 34, count 0 2006.201.04:42:18.86#ibcon#end of sib2, iclass 34, count 0 2006.201.04:42:18.86#ibcon#*mode == 0, iclass 34, count 0 2006.201.04:42:18.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.04:42:18.86#ibcon#[27=USB\r\n] 2006.201.04:42:18.86#ibcon#*before write, iclass 34, count 0 2006.201.04:42:18.86#ibcon#enter sib2, iclass 34, count 0 2006.201.04:42:18.86#ibcon#flushed, iclass 34, count 0 2006.201.04:42:18.86#ibcon#about to write, iclass 34, count 0 2006.201.04:42:18.86#ibcon#wrote, iclass 34, count 0 2006.201.04:42:18.86#ibcon#about to read 3, iclass 34, count 0 2006.201.04:42:18.86#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:42:18.89#ibcon#read 3, iclass 34, count 0 2006.201.04:42:18.89#ibcon#about to read 4, iclass 34, count 0 2006.201.04:42:18.89#ibcon#read 4, iclass 34, count 0 2006.201.04:42:18.89#ibcon#about to read 5, iclass 34, count 0 2006.201.04:42:18.89#ibcon#read 5, iclass 34, count 0 2006.201.04:42:18.89#ibcon#about to read 6, iclass 34, count 0 2006.201.04:42:18.89#ibcon#read 6, iclass 34, count 0 2006.201.04:42:18.89#ibcon#end of sib2, iclass 34, count 0 2006.201.04:42:18.89#ibcon#*after write, iclass 34, count 0 2006.201.04:42:18.89#ibcon#*before return 0, iclass 34, count 0 2006.201.04:42:18.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:18.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.04:42:18.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.04:42:18.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.04:42:18.89$vck44/vabw=wide 2006.201.04:42:18.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.04:42:18.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.04:42:18.89#ibcon#ireg 8 cls_cnt 0 2006.201.04:42:18.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:18.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:18.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:18.89#ibcon#enter wrdev, iclass 40, count 0 2006.201.04:42:18.89#ibcon#first serial, iclass 40, count 0 2006.201.04:42:18.89#ibcon#enter sib2, iclass 40, count 0 2006.201.04:42:18.89#ibcon#flushed, iclass 40, count 0 2006.201.04:42:18.89#ibcon#about to write, iclass 40, count 0 2006.201.04:42:18.89#ibcon#wrote, iclass 40, count 0 2006.201.04:42:18.89#ibcon#about to read 3, iclass 40, count 0 2006.201.04:42:18.91#ibcon#read 3, iclass 40, count 0 2006.201.04:42:18.91#ibcon#about to read 4, iclass 40, count 0 2006.201.04:42:18.91#ibcon#read 4, iclass 40, count 0 2006.201.04:42:18.91#ibcon#about to read 5, iclass 40, count 0 2006.201.04:42:18.91#ibcon#read 5, iclass 40, count 0 2006.201.04:42:18.91#ibcon#about to read 6, iclass 40, count 0 2006.201.04:42:18.91#ibcon#read 6, iclass 40, count 0 2006.201.04:42:18.91#ibcon#end of sib2, iclass 40, count 0 2006.201.04:42:18.91#ibcon#*mode == 0, iclass 40, count 0 2006.201.04:42:18.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.04:42:18.91#ibcon#[25=BW32\r\n] 2006.201.04:42:18.91#ibcon#*before write, iclass 40, count 0 2006.201.04:42:18.91#ibcon#enter sib2, iclass 40, count 0 2006.201.04:42:18.91#ibcon#flushed, iclass 40, count 0 2006.201.04:42:18.91#ibcon#about to write, iclass 40, count 0 2006.201.04:42:18.91#ibcon#wrote, iclass 40, count 0 2006.201.04:42:18.91#ibcon#about to read 3, iclass 40, count 0 2006.201.04:42:18.94#ibcon#read 3, iclass 40, count 0 2006.201.04:42:18.94#ibcon#about to read 4, iclass 40, count 0 2006.201.04:42:18.94#ibcon#read 4, iclass 40, count 0 2006.201.04:42:18.94#ibcon#about to read 5, iclass 40, count 0 2006.201.04:42:18.94#ibcon#read 5, iclass 40, count 0 2006.201.04:42:18.94#ibcon#about to read 6, iclass 40, count 0 2006.201.04:42:18.94#ibcon#read 6, iclass 40, count 0 2006.201.04:42:18.94#ibcon#end of sib2, iclass 40, count 0 2006.201.04:42:18.94#ibcon#*after write, iclass 40, count 0 2006.201.04:42:18.94#ibcon#*before return 0, iclass 40, count 0 2006.201.04:42:18.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:18.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:42:18.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.04:42:18.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.04:42:18.94$vck44/vbbw=wide 2006.201.04:42:18.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.04:42:18.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.04:42:18.94#ibcon#ireg 8 cls_cnt 0 2006.201.04:42:18.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:42:19.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:42:19.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:42:19.01#ibcon#enter wrdev, iclass 4, count 0 2006.201.04:42:19.01#ibcon#first serial, iclass 4, count 0 2006.201.04:42:19.01#ibcon#enter sib2, iclass 4, count 0 2006.201.04:42:19.01#ibcon#flushed, iclass 4, count 0 2006.201.04:42:19.01#ibcon#about to write, iclass 4, count 0 2006.201.04:42:19.01#ibcon#wrote, iclass 4, count 0 2006.201.04:42:19.01#ibcon#about to read 3, iclass 4, count 0 2006.201.04:42:19.03#ibcon#read 3, iclass 4, count 0 2006.201.04:42:19.03#ibcon#about to read 4, iclass 4, count 0 2006.201.04:42:19.03#ibcon#read 4, iclass 4, count 0 2006.201.04:42:19.03#ibcon#about to read 5, iclass 4, count 0 2006.201.04:42:19.03#ibcon#read 5, iclass 4, count 0 2006.201.04:42:19.03#ibcon#about to read 6, iclass 4, count 0 2006.201.04:42:19.03#ibcon#read 6, iclass 4, count 0 2006.201.04:42:19.03#ibcon#end of sib2, iclass 4, count 0 2006.201.04:42:19.03#ibcon#*mode == 0, iclass 4, count 0 2006.201.04:42:19.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.04:42:19.03#ibcon#[27=BW32\r\n] 2006.201.04:42:19.03#ibcon#*before write, iclass 4, count 0 2006.201.04:42:19.03#ibcon#enter sib2, iclass 4, count 0 2006.201.04:42:19.03#ibcon#flushed, iclass 4, count 0 2006.201.04:42:19.03#ibcon#about to write, iclass 4, count 0 2006.201.04:42:19.03#ibcon#wrote, iclass 4, count 0 2006.201.04:42:19.03#ibcon#about to read 3, iclass 4, count 0 2006.201.04:42:19.06#ibcon#read 3, iclass 4, count 0 2006.201.04:42:19.06#ibcon#about to read 4, iclass 4, count 0 2006.201.04:42:19.06#ibcon#read 4, iclass 4, count 0 2006.201.04:42:19.06#ibcon#about to read 5, iclass 4, count 0 2006.201.04:42:19.06#ibcon#read 5, iclass 4, count 0 2006.201.04:42:19.06#ibcon#about to read 6, iclass 4, count 0 2006.201.04:42:19.06#ibcon#read 6, iclass 4, count 0 2006.201.04:42:19.06#ibcon#end of sib2, iclass 4, count 0 2006.201.04:42:19.06#ibcon#*after write, iclass 4, count 0 2006.201.04:42:19.06#ibcon#*before return 0, iclass 4, count 0 2006.201.04:42:19.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:42:19.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:42:19.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.04:42:19.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.04:42:19.06$setupk4/ifdk4 2006.201.04:42:19.06$ifdk4/lo= 2006.201.04:42:19.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:42:19.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:42:19.06$ifdk4/patch= 2006.201.04:42:19.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:42:19.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:42:19.06$setupk4/!*+20s 2006.201.04:42:28.95#abcon#<5=/04 3.3 5.8 22.99 901004.1\r\n> 2006.201.04:42:28.97#abcon#{5=INTERFACE CLEAR} 2006.201.04:42:29.03#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:42:33.27$setupk4/"tpicd 2006.201.04:42:33.27$setupk4/echo=off 2006.201.04:42:33.27$setupk4/xlog=off 2006.201.04:42:33.27:!2006.201.04:48:31 2006.201.04:43:00.14#trakl#Source acquired 2006.201.04:43:02.14#flagr#flagr/antenna,acquired 2006.201.04:48:31.00:preob 2006.201.04:48:31.14/onsource/TRACKING 2006.201.04:48:31.14:!2006.201.04:48:41 2006.201.04:48:41.00:"tape 2006.201.04:48:41.00:"st=record 2006.201.04:48:41.00:data_valid=on 2006.201.04:48:41.00:midob 2006.201.04:48:41.14/onsource/TRACKING 2006.201.04:48:41.14/wx/22.97,1003.9,89 2006.201.04:48:41.28/cable/+6.4661E-03 2006.201.04:48:42.37/va/01,08,usb,yes,29,31 2006.201.04:48:42.37/va/02,07,usb,yes,31,32 2006.201.04:48:42.37/va/03,08,usb,yes,28,29 2006.201.04:48:42.37/va/04,07,usb,yes,32,34 2006.201.04:48:42.37/va/05,04,usb,yes,28,29 2006.201.04:48:42.37/va/06,05,usb,yes,28,28 2006.201.04:48:42.37/va/07,05,usb,yes,28,29 2006.201.04:48:42.37/va/08,04,usb,yes,27,33 2006.201.04:48:42.60/valo/01,524.99,yes,locked 2006.201.04:48:42.60/valo/02,534.99,yes,locked 2006.201.04:48:42.60/valo/03,564.99,yes,locked 2006.201.04:48:42.60/valo/04,624.99,yes,locked 2006.201.04:48:42.60/valo/05,734.99,yes,locked 2006.201.04:48:42.60/valo/06,814.99,yes,locked 2006.201.04:48:42.60/valo/07,864.99,yes,locked 2006.201.04:48:42.60/valo/08,884.99,yes,locked 2006.201.04:48:43.69/vb/01,04,usb,yes,29,27 2006.201.04:48:43.69/vb/02,05,usb,yes,28,28 2006.201.04:48:43.69/vb/03,04,usb,yes,28,32 2006.201.04:48:43.69/vb/04,05,usb,yes,29,28 2006.201.04:48:43.69/vb/05,04,usb,yes,25,28 2006.201.04:48:43.69/vb/06,04,usb,yes,30,26 2006.201.04:48:43.69/vb/07,04,usb,yes,30,29 2006.201.04:48:43.69/vb/08,04,usb,yes,27,30 2006.201.04:48:43.92/vblo/01,629.99,yes,locked 2006.201.04:48:43.92/vblo/02,634.99,yes,locked 2006.201.04:48:43.92/vblo/03,649.99,yes,locked 2006.201.04:48:43.92/vblo/04,679.99,yes,locked 2006.201.04:48:43.92/vblo/05,709.99,yes,locked 2006.201.04:48:43.92/vblo/06,719.99,yes,locked 2006.201.04:48:43.92/vblo/07,734.99,yes,locked 2006.201.04:48:43.92/vblo/08,744.99,yes,locked 2006.201.04:48:44.07/vabw/8 2006.201.04:48:44.22/vbbw/8 2006.201.04:48:44.31/xfe/off,on,15.2 2006.201.04:48:44.69/ifatt/23,28,28,28 2006.201.04:48:45.05/fmout-gps/S +4.53E-07 2006.201.04:48:45.09:!2006.201.04:49:41 2006.201.04:49:41.00:data_valid=off 2006.201.04:49:41.00:"et 2006.201.04:49:41.00:!+3s 2006.201.04:49:44.02:"tape 2006.201.04:49:44.02:postob 2006.201.04:49:44.24/cable/+6.4665E-03 2006.201.04:49:44.24/wx/22.97,1003.9,90 2006.201.04:49:44.30/fmout-gps/S +4.53E-07 2006.201.04:49:44.30:scan_name=201-0452,jd0607,50 2006.201.04:49:44.30:source=0552+398,055530.81,394849.2,2000.0,cw 2006.201.04:49:45.14#flagr#flagr/antenna,new-source 2006.201.04:49:45.14:checkk5 2006.201.04:49:45.55/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:49:45.94/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:49:46.37/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:49:46.77/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:49:47.14/chk_obsdata//k5ts1/T2010448??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.04:49:47.55/chk_obsdata//k5ts2/T2010448??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.04:49:47.95/chk_obsdata//k5ts3/T2010448??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.04:49:48.34/chk_obsdata//k5ts4/T2010448??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.04:49:49.06/k5log//k5ts1_log_newline 2006.201.04:49:49.77/k5log//k5ts2_log_newline 2006.201.04:49:50.50/k5log//k5ts3_log_newline 2006.201.04:49:51.20/k5log//k5ts4_log_newline 2006.201.04:49:51.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:49:51.22:setupk4=1 2006.201.04:49:51.22$setupk4/echo=on 2006.201.04:49:51.23$setupk4/pcalon 2006.201.04:49:51.23$pcalon/"no phase cal control is implemented here 2006.201.04:49:51.23$setupk4/"tpicd=stop 2006.201.04:49:51.23$setupk4/"rec=synch_on 2006.201.04:49:51.23$setupk4/"rec_mode=128 2006.201.04:49:51.23$setupk4/!* 2006.201.04:49:51.23$setupk4/recpk4 2006.201.04:49:51.23$recpk4/recpatch= 2006.201.04:49:51.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:49:51.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:49:51.23$setupk4/vck44 2006.201.04:49:51.23$vck44/valo=1,524.99 2006.201.04:49:51.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.04:49:51.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.04:49:51.23#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:51.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:51.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:51.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:51.23#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:49:51.23#ibcon#first serial, iclass 5, count 0 2006.201.04:49:51.23#ibcon#enter sib2, iclass 5, count 0 2006.201.04:49:51.23#ibcon#flushed, iclass 5, count 0 2006.201.04:49:51.23#ibcon#about to write, iclass 5, count 0 2006.201.04:49:51.23#ibcon#wrote, iclass 5, count 0 2006.201.04:49:51.23#ibcon#about to read 3, iclass 5, count 0 2006.201.04:49:51.25#ibcon#read 3, iclass 5, count 0 2006.201.04:49:51.25#ibcon#about to read 4, iclass 5, count 0 2006.201.04:49:51.25#ibcon#read 4, iclass 5, count 0 2006.201.04:49:51.25#ibcon#about to read 5, iclass 5, count 0 2006.201.04:49:51.25#ibcon#read 5, iclass 5, count 0 2006.201.04:49:51.25#ibcon#about to read 6, iclass 5, count 0 2006.201.04:49:51.25#ibcon#read 6, iclass 5, count 0 2006.201.04:49:51.25#ibcon#end of sib2, iclass 5, count 0 2006.201.04:49:51.25#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:49:51.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:49:51.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:49:51.25#ibcon#*before write, iclass 5, count 0 2006.201.04:49:51.25#ibcon#enter sib2, iclass 5, count 0 2006.201.04:49:51.25#ibcon#flushed, iclass 5, count 0 2006.201.04:49:51.25#ibcon#about to write, iclass 5, count 0 2006.201.04:49:51.25#ibcon#wrote, iclass 5, count 0 2006.201.04:49:51.25#ibcon#about to read 3, iclass 5, count 0 2006.201.04:49:51.30#ibcon#read 3, iclass 5, count 0 2006.201.04:49:51.30#ibcon#about to read 4, iclass 5, count 0 2006.201.04:49:51.30#ibcon#read 4, iclass 5, count 0 2006.201.04:49:51.30#ibcon#about to read 5, iclass 5, count 0 2006.201.04:49:51.30#ibcon#read 5, iclass 5, count 0 2006.201.04:49:51.30#ibcon#about to read 6, iclass 5, count 0 2006.201.04:49:51.30#ibcon#read 6, iclass 5, count 0 2006.201.04:49:51.30#ibcon#end of sib2, iclass 5, count 0 2006.201.04:49:51.30#ibcon#*after write, iclass 5, count 0 2006.201.04:49:51.30#ibcon#*before return 0, iclass 5, count 0 2006.201.04:49:51.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:51.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:51.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:49:51.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:49:51.30$vck44/va=1,8 2006.201.04:49:51.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.04:49:51.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.04:49:51.30#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:51.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:51.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:51.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:51.30#ibcon#enter wrdev, iclass 7, count 2 2006.201.04:49:51.30#ibcon#first serial, iclass 7, count 2 2006.201.04:49:51.30#ibcon#enter sib2, iclass 7, count 2 2006.201.04:49:51.30#ibcon#flushed, iclass 7, count 2 2006.201.04:49:51.30#ibcon#about to write, iclass 7, count 2 2006.201.04:49:51.30#ibcon#wrote, iclass 7, count 2 2006.201.04:49:51.30#ibcon#about to read 3, iclass 7, count 2 2006.201.04:49:51.32#ibcon#read 3, iclass 7, count 2 2006.201.04:49:51.32#ibcon#about to read 4, iclass 7, count 2 2006.201.04:49:51.32#ibcon#read 4, iclass 7, count 2 2006.201.04:49:51.32#ibcon#about to read 5, iclass 7, count 2 2006.201.04:49:51.32#ibcon#read 5, iclass 7, count 2 2006.201.04:49:51.32#ibcon#about to read 6, iclass 7, count 2 2006.201.04:49:51.32#ibcon#read 6, iclass 7, count 2 2006.201.04:49:51.32#ibcon#end of sib2, iclass 7, count 2 2006.201.04:49:51.32#ibcon#*mode == 0, iclass 7, count 2 2006.201.04:49:51.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.04:49:51.32#ibcon#[25=AT01-08\r\n] 2006.201.04:49:51.32#ibcon#*before write, iclass 7, count 2 2006.201.04:49:51.32#ibcon#enter sib2, iclass 7, count 2 2006.201.04:49:51.32#ibcon#flushed, iclass 7, count 2 2006.201.04:49:51.32#ibcon#about to write, iclass 7, count 2 2006.201.04:49:51.32#ibcon#wrote, iclass 7, count 2 2006.201.04:49:51.32#ibcon#about to read 3, iclass 7, count 2 2006.201.04:49:51.35#ibcon#read 3, iclass 7, count 2 2006.201.04:49:51.35#ibcon#about to read 4, iclass 7, count 2 2006.201.04:49:51.35#ibcon#read 4, iclass 7, count 2 2006.201.04:49:51.35#ibcon#about to read 5, iclass 7, count 2 2006.201.04:49:51.35#ibcon#read 5, iclass 7, count 2 2006.201.04:49:51.35#ibcon#about to read 6, iclass 7, count 2 2006.201.04:49:51.35#ibcon#read 6, iclass 7, count 2 2006.201.04:49:51.35#ibcon#end of sib2, iclass 7, count 2 2006.201.04:49:51.35#ibcon#*after write, iclass 7, count 2 2006.201.04:49:51.35#ibcon#*before return 0, iclass 7, count 2 2006.201.04:49:51.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:51.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:51.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.04:49:51.35#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:51.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:51.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:51.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:51.47#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:49:51.47#ibcon#first serial, iclass 7, count 0 2006.201.04:49:51.47#ibcon#enter sib2, iclass 7, count 0 2006.201.04:49:51.47#ibcon#flushed, iclass 7, count 0 2006.201.04:49:51.47#ibcon#about to write, iclass 7, count 0 2006.201.04:49:51.47#ibcon#wrote, iclass 7, count 0 2006.201.04:49:51.47#ibcon#about to read 3, iclass 7, count 0 2006.201.04:49:51.49#ibcon#read 3, iclass 7, count 0 2006.201.04:49:51.49#ibcon#about to read 4, iclass 7, count 0 2006.201.04:49:51.49#ibcon#read 4, iclass 7, count 0 2006.201.04:49:51.49#ibcon#about to read 5, iclass 7, count 0 2006.201.04:49:51.49#ibcon#read 5, iclass 7, count 0 2006.201.04:49:51.49#ibcon#about to read 6, iclass 7, count 0 2006.201.04:49:51.49#ibcon#read 6, iclass 7, count 0 2006.201.04:49:51.49#ibcon#end of sib2, iclass 7, count 0 2006.201.04:49:51.49#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:49:51.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:49:51.49#ibcon#[25=USB\r\n] 2006.201.04:49:51.49#ibcon#*before write, iclass 7, count 0 2006.201.04:49:51.49#ibcon#enter sib2, iclass 7, count 0 2006.201.04:49:51.49#ibcon#flushed, iclass 7, count 0 2006.201.04:49:51.49#ibcon#about to write, iclass 7, count 0 2006.201.04:49:51.49#ibcon#wrote, iclass 7, count 0 2006.201.04:49:51.49#ibcon#about to read 3, iclass 7, count 0 2006.201.04:49:51.52#ibcon#read 3, iclass 7, count 0 2006.201.04:49:51.52#ibcon#about to read 4, iclass 7, count 0 2006.201.04:49:51.52#ibcon#read 4, iclass 7, count 0 2006.201.04:49:51.52#ibcon#about to read 5, iclass 7, count 0 2006.201.04:49:51.52#ibcon#read 5, iclass 7, count 0 2006.201.04:49:51.52#ibcon#about to read 6, iclass 7, count 0 2006.201.04:49:51.52#ibcon#read 6, iclass 7, count 0 2006.201.04:49:51.52#ibcon#end of sib2, iclass 7, count 0 2006.201.04:49:51.52#ibcon#*after write, iclass 7, count 0 2006.201.04:49:51.52#ibcon#*before return 0, iclass 7, count 0 2006.201.04:49:51.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:51.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:51.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:49:51.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:49:51.52$vck44/valo=2,534.99 2006.201.04:49:51.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.04:49:51.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.04:49:51.52#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:51.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:51.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:51.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:51.52#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:49:51.52#ibcon#first serial, iclass 11, count 0 2006.201.04:49:51.52#ibcon#enter sib2, iclass 11, count 0 2006.201.04:49:51.52#ibcon#flushed, iclass 11, count 0 2006.201.04:49:51.52#ibcon#about to write, iclass 11, count 0 2006.201.04:49:51.52#ibcon#wrote, iclass 11, count 0 2006.201.04:49:51.52#ibcon#about to read 3, iclass 11, count 0 2006.201.04:49:51.54#ibcon#read 3, iclass 11, count 0 2006.201.04:49:51.54#ibcon#about to read 4, iclass 11, count 0 2006.201.04:49:51.54#ibcon#read 4, iclass 11, count 0 2006.201.04:49:51.54#ibcon#about to read 5, iclass 11, count 0 2006.201.04:49:51.54#ibcon#read 5, iclass 11, count 0 2006.201.04:49:51.54#ibcon#about to read 6, iclass 11, count 0 2006.201.04:49:51.54#ibcon#read 6, iclass 11, count 0 2006.201.04:49:51.54#ibcon#end of sib2, iclass 11, count 0 2006.201.04:49:51.54#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:49:51.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:49:51.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:49:51.54#ibcon#*before write, iclass 11, count 0 2006.201.04:49:51.54#ibcon#enter sib2, iclass 11, count 0 2006.201.04:49:51.54#ibcon#flushed, iclass 11, count 0 2006.201.04:49:51.54#ibcon#about to write, iclass 11, count 0 2006.201.04:49:51.54#ibcon#wrote, iclass 11, count 0 2006.201.04:49:51.54#ibcon#about to read 3, iclass 11, count 0 2006.201.04:49:51.58#ibcon#read 3, iclass 11, count 0 2006.201.04:49:51.58#ibcon#about to read 4, iclass 11, count 0 2006.201.04:49:51.58#ibcon#read 4, iclass 11, count 0 2006.201.04:49:51.58#ibcon#about to read 5, iclass 11, count 0 2006.201.04:49:51.58#ibcon#read 5, iclass 11, count 0 2006.201.04:49:51.58#ibcon#about to read 6, iclass 11, count 0 2006.201.04:49:51.58#ibcon#read 6, iclass 11, count 0 2006.201.04:49:51.58#ibcon#end of sib2, iclass 11, count 0 2006.201.04:49:51.58#ibcon#*after write, iclass 11, count 0 2006.201.04:49:51.58#ibcon#*before return 0, iclass 11, count 0 2006.201.04:49:51.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:51.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:51.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:49:51.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:49:51.58$vck44/va=2,7 2006.201.04:49:51.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.04:49:51.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.04:49:51.58#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:51.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:51.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:51.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:51.64#ibcon#enter wrdev, iclass 13, count 2 2006.201.04:49:51.64#ibcon#first serial, iclass 13, count 2 2006.201.04:49:51.64#ibcon#enter sib2, iclass 13, count 2 2006.201.04:49:51.64#ibcon#flushed, iclass 13, count 2 2006.201.04:49:51.64#ibcon#about to write, iclass 13, count 2 2006.201.04:49:51.64#ibcon#wrote, iclass 13, count 2 2006.201.04:49:51.64#ibcon#about to read 3, iclass 13, count 2 2006.201.04:49:51.66#ibcon#read 3, iclass 13, count 2 2006.201.04:49:51.66#ibcon#about to read 4, iclass 13, count 2 2006.201.04:49:51.66#ibcon#read 4, iclass 13, count 2 2006.201.04:49:51.66#ibcon#about to read 5, iclass 13, count 2 2006.201.04:49:51.66#ibcon#read 5, iclass 13, count 2 2006.201.04:49:51.66#ibcon#about to read 6, iclass 13, count 2 2006.201.04:49:51.66#ibcon#read 6, iclass 13, count 2 2006.201.04:49:51.66#ibcon#end of sib2, iclass 13, count 2 2006.201.04:49:51.66#ibcon#*mode == 0, iclass 13, count 2 2006.201.04:49:51.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.04:49:51.66#ibcon#[25=AT02-07\r\n] 2006.201.04:49:51.66#ibcon#*before write, iclass 13, count 2 2006.201.04:49:51.66#ibcon#enter sib2, iclass 13, count 2 2006.201.04:49:51.66#ibcon#flushed, iclass 13, count 2 2006.201.04:49:51.66#ibcon#about to write, iclass 13, count 2 2006.201.04:49:51.66#ibcon#wrote, iclass 13, count 2 2006.201.04:49:51.66#ibcon#about to read 3, iclass 13, count 2 2006.201.04:49:51.69#ibcon#read 3, iclass 13, count 2 2006.201.04:49:51.69#ibcon#about to read 4, iclass 13, count 2 2006.201.04:49:51.69#ibcon#read 4, iclass 13, count 2 2006.201.04:49:51.69#ibcon#about to read 5, iclass 13, count 2 2006.201.04:49:51.69#ibcon#read 5, iclass 13, count 2 2006.201.04:49:51.69#ibcon#about to read 6, iclass 13, count 2 2006.201.04:49:51.69#ibcon#read 6, iclass 13, count 2 2006.201.04:49:51.69#ibcon#end of sib2, iclass 13, count 2 2006.201.04:49:51.69#ibcon#*after write, iclass 13, count 2 2006.201.04:49:51.69#ibcon#*before return 0, iclass 13, count 2 2006.201.04:49:51.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:51.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:51.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.04:49:51.69#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:51.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:51.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:51.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:51.81#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:49:51.81#ibcon#first serial, iclass 13, count 0 2006.201.04:49:51.81#ibcon#enter sib2, iclass 13, count 0 2006.201.04:49:51.81#ibcon#flushed, iclass 13, count 0 2006.201.04:49:51.81#ibcon#about to write, iclass 13, count 0 2006.201.04:49:51.81#ibcon#wrote, iclass 13, count 0 2006.201.04:49:51.81#ibcon#about to read 3, iclass 13, count 0 2006.201.04:49:51.83#ibcon#read 3, iclass 13, count 0 2006.201.04:49:51.83#ibcon#about to read 4, iclass 13, count 0 2006.201.04:49:51.83#ibcon#read 4, iclass 13, count 0 2006.201.04:49:51.83#ibcon#about to read 5, iclass 13, count 0 2006.201.04:49:51.83#ibcon#read 5, iclass 13, count 0 2006.201.04:49:51.83#ibcon#about to read 6, iclass 13, count 0 2006.201.04:49:51.83#ibcon#read 6, iclass 13, count 0 2006.201.04:49:51.83#ibcon#end of sib2, iclass 13, count 0 2006.201.04:49:51.83#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:49:51.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:49:51.83#ibcon#[25=USB\r\n] 2006.201.04:49:51.83#ibcon#*before write, iclass 13, count 0 2006.201.04:49:51.83#ibcon#enter sib2, iclass 13, count 0 2006.201.04:49:51.83#ibcon#flushed, iclass 13, count 0 2006.201.04:49:51.83#ibcon#about to write, iclass 13, count 0 2006.201.04:49:51.83#ibcon#wrote, iclass 13, count 0 2006.201.04:49:51.83#ibcon#about to read 3, iclass 13, count 0 2006.201.04:49:51.86#ibcon#read 3, iclass 13, count 0 2006.201.04:49:51.86#ibcon#about to read 4, iclass 13, count 0 2006.201.04:49:51.86#ibcon#read 4, iclass 13, count 0 2006.201.04:49:51.86#ibcon#about to read 5, iclass 13, count 0 2006.201.04:49:51.86#ibcon#read 5, iclass 13, count 0 2006.201.04:49:51.86#ibcon#about to read 6, iclass 13, count 0 2006.201.04:49:51.86#ibcon#read 6, iclass 13, count 0 2006.201.04:49:51.86#ibcon#end of sib2, iclass 13, count 0 2006.201.04:49:51.86#ibcon#*after write, iclass 13, count 0 2006.201.04:49:51.86#ibcon#*before return 0, iclass 13, count 0 2006.201.04:49:51.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:51.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:51.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:49:51.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:49:51.86$vck44/valo=3,564.99 2006.201.04:49:51.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.04:49:51.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.04:49:51.86#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:51.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:51.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:51.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:51.86#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:49:51.86#ibcon#first serial, iclass 15, count 0 2006.201.04:49:51.86#ibcon#enter sib2, iclass 15, count 0 2006.201.04:49:51.86#ibcon#flushed, iclass 15, count 0 2006.201.04:49:51.86#ibcon#about to write, iclass 15, count 0 2006.201.04:49:51.86#ibcon#wrote, iclass 15, count 0 2006.201.04:49:51.86#ibcon#about to read 3, iclass 15, count 0 2006.201.04:49:51.88#ibcon#read 3, iclass 15, count 0 2006.201.04:49:51.88#ibcon#about to read 4, iclass 15, count 0 2006.201.04:49:51.88#ibcon#read 4, iclass 15, count 0 2006.201.04:49:51.88#ibcon#about to read 5, iclass 15, count 0 2006.201.04:49:51.88#ibcon#read 5, iclass 15, count 0 2006.201.04:49:51.88#ibcon#about to read 6, iclass 15, count 0 2006.201.04:49:51.88#ibcon#read 6, iclass 15, count 0 2006.201.04:49:51.88#ibcon#end of sib2, iclass 15, count 0 2006.201.04:49:51.88#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:49:51.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:49:51.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:49:51.88#ibcon#*before write, iclass 15, count 0 2006.201.04:49:51.88#ibcon#enter sib2, iclass 15, count 0 2006.201.04:49:51.88#ibcon#flushed, iclass 15, count 0 2006.201.04:49:51.88#ibcon#about to write, iclass 15, count 0 2006.201.04:49:51.88#ibcon#wrote, iclass 15, count 0 2006.201.04:49:51.88#ibcon#about to read 3, iclass 15, count 0 2006.201.04:49:51.92#ibcon#read 3, iclass 15, count 0 2006.201.04:49:51.92#ibcon#about to read 4, iclass 15, count 0 2006.201.04:49:51.92#ibcon#read 4, iclass 15, count 0 2006.201.04:49:51.92#ibcon#about to read 5, iclass 15, count 0 2006.201.04:49:51.92#ibcon#read 5, iclass 15, count 0 2006.201.04:49:51.92#ibcon#about to read 6, iclass 15, count 0 2006.201.04:49:51.92#ibcon#read 6, iclass 15, count 0 2006.201.04:49:51.92#ibcon#end of sib2, iclass 15, count 0 2006.201.04:49:51.92#ibcon#*after write, iclass 15, count 0 2006.201.04:49:51.92#ibcon#*before return 0, iclass 15, count 0 2006.201.04:49:51.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:51.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:51.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:49:51.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:49:51.92$vck44/va=3,8 2006.201.04:49:51.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.04:49:51.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.04:49:51.92#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:51.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:51.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:51.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:51.98#ibcon#enter wrdev, iclass 17, count 2 2006.201.04:49:51.98#ibcon#first serial, iclass 17, count 2 2006.201.04:49:51.98#ibcon#enter sib2, iclass 17, count 2 2006.201.04:49:51.98#ibcon#flushed, iclass 17, count 2 2006.201.04:49:51.98#ibcon#about to write, iclass 17, count 2 2006.201.04:49:51.98#ibcon#wrote, iclass 17, count 2 2006.201.04:49:51.98#ibcon#about to read 3, iclass 17, count 2 2006.201.04:49:52.00#ibcon#read 3, iclass 17, count 2 2006.201.04:49:52.00#ibcon#about to read 4, iclass 17, count 2 2006.201.04:49:52.00#ibcon#read 4, iclass 17, count 2 2006.201.04:49:52.00#ibcon#about to read 5, iclass 17, count 2 2006.201.04:49:52.00#ibcon#read 5, iclass 17, count 2 2006.201.04:49:52.00#ibcon#about to read 6, iclass 17, count 2 2006.201.04:49:52.00#ibcon#read 6, iclass 17, count 2 2006.201.04:49:52.00#ibcon#end of sib2, iclass 17, count 2 2006.201.04:49:52.00#ibcon#*mode == 0, iclass 17, count 2 2006.201.04:49:52.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.04:49:52.00#ibcon#[25=AT03-08\r\n] 2006.201.04:49:52.00#ibcon#*before write, iclass 17, count 2 2006.201.04:49:52.00#ibcon#enter sib2, iclass 17, count 2 2006.201.04:49:52.00#ibcon#flushed, iclass 17, count 2 2006.201.04:49:52.00#ibcon#about to write, iclass 17, count 2 2006.201.04:49:52.00#ibcon#wrote, iclass 17, count 2 2006.201.04:49:52.00#ibcon#about to read 3, iclass 17, count 2 2006.201.04:49:52.03#ibcon#read 3, iclass 17, count 2 2006.201.04:49:52.03#ibcon#about to read 4, iclass 17, count 2 2006.201.04:49:52.03#ibcon#read 4, iclass 17, count 2 2006.201.04:49:52.03#ibcon#about to read 5, iclass 17, count 2 2006.201.04:49:52.03#ibcon#read 5, iclass 17, count 2 2006.201.04:49:52.03#ibcon#about to read 6, iclass 17, count 2 2006.201.04:49:52.03#ibcon#read 6, iclass 17, count 2 2006.201.04:49:52.03#ibcon#end of sib2, iclass 17, count 2 2006.201.04:49:52.03#ibcon#*after write, iclass 17, count 2 2006.201.04:49:52.03#ibcon#*before return 0, iclass 17, count 2 2006.201.04:49:52.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:52.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:52.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.04:49:52.03#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:52.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:52.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:52.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:52.15#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:49:52.15#ibcon#first serial, iclass 17, count 0 2006.201.04:49:52.15#ibcon#enter sib2, iclass 17, count 0 2006.201.04:49:52.15#ibcon#flushed, iclass 17, count 0 2006.201.04:49:52.15#ibcon#about to write, iclass 17, count 0 2006.201.04:49:52.15#ibcon#wrote, iclass 17, count 0 2006.201.04:49:52.15#ibcon#about to read 3, iclass 17, count 0 2006.201.04:49:52.17#ibcon#read 3, iclass 17, count 0 2006.201.04:49:52.17#ibcon#about to read 4, iclass 17, count 0 2006.201.04:49:52.17#ibcon#read 4, iclass 17, count 0 2006.201.04:49:52.17#ibcon#about to read 5, iclass 17, count 0 2006.201.04:49:52.17#ibcon#read 5, iclass 17, count 0 2006.201.04:49:52.17#ibcon#about to read 6, iclass 17, count 0 2006.201.04:49:52.17#ibcon#read 6, iclass 17, count 0 2006.201.04:49:52.17#ibcon#end of sib2, iclass 17, count 0 2006.201.04:49:52.17#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:49:52.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:49:52.17#ibcon#[25=USB\r\n] 2006.201.04:49:52.17#ibcon#*before write, iclass 17, count 0 2006.201.04:49:52.17#ibcon#enter sib2, iclass 17, count 0 2006.201.04:49:52.17#ibcon#flushed, iclass 17, count 0 2006.201.04:49:52.17#ibcon#about to write, iclass 17, count 0 2006.201.04:49:52.17#ibcon#wrote, iclass 17, count 0 2006.201.04:49:52.17#ibcon#about to read 3, iclass 17, count 0 2006.201.04:49:52.20#ibcon#read 3, iclass 17, count 0 2006.201.04:49:52.20#ibcon#about to read 4, iclass 17, count 0 2006.201.04:49:52.20#ibcon#read 4, iclass 17, count 0 2006.201.04:49:52.20#ibcon#about to read 5, iclass 17, count 0 2006.201.04:49:52.20#ibcon#read 5, iclass 17, count 0 2006.201.04:49:52.20#ibcon#about to read 6, iclass 17, count 0 2006.201.04:49:52.20#ibcon#read 6, iclass 17, count 0 2006.201.04:49:52.20#ibcon#end of sib2, iclass 17, count 0 2006.201.04:49:52.20#ibcon#*after write, iclass 17, count 0 2006.201.04:49:52.20#ibcon#*before return 0, iclass 17, count 0 2006.201.04:49:52.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:52.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:52.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:49:52.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:49:52.20$vck44/valo=4,624.99 2006.201.04:49:52.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.04:49:52.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.04:49:52.20#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:52.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:52.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:52.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:52.20#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:49:52.20#ibcon#first serial, iclass 19, count 0 2006.201.04:49:52.20#ibcon#enter sib2, iclass 19, count 0 2006.201.04:49:52.20#ibcon#flushed, iclass 19, count 0 2006.201.04:49:52.20#ibcon#about to write, iclass 19, count 0 2006.201.04:49:52.20#ibcon#wrote, iclass 19, count 0 2006.201.04:49:52.20#ibcon#about to read 3, iclass 19, count 0 2006.201.04:49:52.22#ibcon#read 3, iclass 19, count 0 2006.201.04:49:52.22#ibcon#about to read 4, iclass 19, count 0 2006.201.04:49:52.22#ibcon#read 4, iclass 19, count 0 2006.201.04:49:52.22#ibcon#about to read 5, iclass 19, count 0 2006.201.04:49:52.22#ibcon#read 5, iclass 19, count 0 2006.201.04:49:52.22#ibcon#about to read 6, iclass 19, count 0 2006.201.04:49:52.22#ibcon#read 6, iclass 19, count 0 2006.201.04:49:52.22#ibcon#end of sib2, iclass 19, count 0 2006.201.04:49:52.22#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:49:52.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:49:52.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:49:52.22#ibcon#*before write, iclass 19, count 0 2006.201.04:49:52.22#ibcon#enter sib2, iclass 19, count 0 2006.201.04:49:52.22#ibcon#flushed, iclass 19, count 0 2006.201.04:49:52.22#ibcon#about to write, iclass 19, count 0 2006.201.04:49:52.22#ibcon#wrote, iclass 19, count 0 2006.201.04:49:52.22#ibcon#about to read 3, iclass 19, count 0 2006.201.04:49:52.26#ibcon#read 3, iclass 19, count 0 2006.201.04:49:52.26#ibcon#about to read 4, iclass 19, count 0 2006.201.04:49:52.26#ibcon#read 4, iclass 19, count 0 2006.201.04:49:52.26#ibcon#about to read 5, iclass 19, count 0 2006.201.04:49:52.26#ibcon#read 5, iclass 19, count 0 2006.201.04:49:52.26#ibcon#about to read 6, iclass 19, count 0 2006.201.04:49:52.26#ibcon#read 6, iclass 19, count 0 2006.201.04:49:52.26#ibcon#end of sib2, iclass 19, count 0 2006.201.04:49:52.26#ibcon#*after write, iclass 19, count 0 2006.201.04:49:52.26#ibcon#*before return 0, iclass 19, count 0 2006.201.04:49:52.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:52.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:52.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:49:52.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:49:52.26$vck44/va=4,7 2006.201.04:49:52.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.04:49:52.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.04:49:52.26#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:52.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:52.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:52.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:52.32#ibcon#enter wrdev, iclass 21, count 2 2006.201.04:49:52.32#ibcon#first serial, iclass 21, count 2 2006.201.04:49:52.32#ibcon#enter sib2, iclass 21, count 2 2006.201.04:49:52.32#ibcon#flushed, iclass 21, count 2 2006.201.04:49:52.32#ibcon#about to write, iclass 21, count 2 2006.201.04:49:52.32#ibcon#wrote, iclass 21, count 2 2006.201.04:49:52.32#ibcon#about to read 3, iclass 21, count 2 2006.201.04:49:52.34#ibcon#read 3, iclass 21, count 2 2006.201.04:49:52.34#ibcon#about to read 4, iclass 21, count 2 2006.201.04:49:52.34#ibcon#read 4, iclass 21, count 2 2006.201.04:49:52.34#ibcon#about to read 5, iclass 21, count 2 2006.201.04:49:52.34#ibcon#read 5, iclass 21, count 2 2006.201.04:49:52.34#ibcon#about to read 6, iclass 21, count 2 2006.201.04:49:52.34#ibcon#read 6, iclass 21, count 2 2006.201.04:49:52.34#ibcon#end of sib2, iclass 21, count 2 2006.201.04:49:52.34#ibcon#*mode == 0, iclass 21, count 2 2006.201.04:49:52.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.04:49:52.34#ibcon#[25=AT04-07\r\n] 2006.201.04:49:52.34#ibcon#*before write, iclass 21, count 2 2006.201.04:49:52.34#ibcon#enter sib2, iclass 21, count 2 2006.201.04:49:52.34#ibcon#flushed, iclass 21, count 2 2006.201.04:49:52.34#ibcon#about to write, iclass 21, count 2 2006.201.04:49:52.34#ibcon#wrote, iclass 21, count 2 2006.201.04:49:52.34#ibcon#about to read 3, iclass 21, count 2 2006.201.04:49:52.37#ibcon#read 3, iclass 21, count 2 2006.201.04:49:52.37#ibcon#about to read 4, iclass 21, count 2 2006.201.04:49:52.43#ibcon#read 4, iclass 21, count 2 2006.201.04:49:52.43#ibcon#about to read 5, iclass 21, count 2 2006.201.04:49:52.43#ibcon#read 5, iclass 21, count 2 2006.201.04:49:52.43#ibcon#about to read 6, iclass 21, count 2 2006.201.04:49:52.43#ibcon#read 6, iclass 21, count 2 2006.201.04:49:52.43#ibcon#end of sib2, iclass 21, count 2 2006.201.04:49:52.43#ibcon#*after write, iclass 21, count 2 2006.201.04:49:52.43#ibcon#*before return 0, iclass 21, count 2 2006.201.04:49:52.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:52.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:52.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.04:49:52.43#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:52.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:52.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:52.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:52.55#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:49:52.55#ibcon#first serial, iclass 21, count 0 2006.201.04:49:52.55#ibcon#enter sib2, iclass 21, count 0 2006.201.04:49:52.55#ibcon#flushed, iclass 21, count 0 2006.201.04:49:52.55#ibcon#about to write, iclass 21, count 0 2006.201.04:49:52.55#ibcon#wrote, iclass 21, count 0 2006.201.04:49:52.55#ibcon#about to read 3, iclass 21, count 0 2006.201.04:49:52.57#ibcon#read 3, iclass 21, count 0 2006.201.04:49:52.57#ibcon#about to read 4, iclass 21, count 0 2006.201.04:49:52.57#ibcon#read 4, iclass 21, count 0 2006.201.04:49:52.57#ibcon#about to read 5, iclass 21, count 0 2006.201.04:49:52.57#ibcon#read 5, iclass 21, count 0 2006.201.04:49:52.57#ibcon#about to read 6, iclass 21, count 0 2006.201.04:49:52.57#ibcon#read 6, iclass 21, count 0 2006.201.04:49:52.57#ibcon#end of sib2, iclass 21, count 0 2006.201.04:49:52.57#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:49:52.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:49:52.57#ibcon#[25=USB\r\n] 2006.201.04:49:52.57#ibcon#*before write, iclass 21, count 0 2006.201.04:49:52.57#ibcon#enter sib2, iclass 21, count 0 2006.201.04:49:52.57#ibcon#flushed, iclass 21, count 0 2006.201.04:49:52.57#ibcon#about to write, iclass 21, count 0 2006.201.04:49:52.57#ibcon#wrote, iclass 21, count 0 2006.201.04:49:52.57#ibcon#about to read 3, iclass 21, count 0 2006.201.04:49:52.60#ibcon#read 3, iclass 21, count 0 2006.201.04:49:52.60#ibcon#about to read 4, iclass 21, count 0 2006.201.04:49:52.60#ibcon#read 4, iclass 21, count 0 2006.201.04:49:52.60#ibcon#about to read 5, iclass 21, count 0 2006.201.04:49:52.60#ibcon#read 5, iclass 21, count 0 2006.201.04:49:52.60#ibcon#about to read 6, iclass 21, count 0 2006.201.04:49:52.60#ibcon#read 6, iclass 21, count 0 2006.201.04:49:52.60#ibcon#end of sib2, iclass 21, count 0 2006.201.04:49:52.60#ibcon#*after write, iclass 21, count 0 2006.201.04:49:52.60#ibcon#*before return 0, iclass 21, count 0 2006.201.04:49:52.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:52.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:52.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:49:52.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:49:52.60$vck44/valo=5,734.99 2006.201.04:49:52.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.04:49:52.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.04:49:52.60#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:52.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:52.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:52.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:52.60#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:49:52.60#ibcon#first serial, iclass 23, count 0 2006.201.04:49:52.60#ibcon#enter sib2, iclass 23, count 0 2006.201.04:49:52.60#ibcon#flushed, iclass 23, count 0 2006.201.04:49:52.60#ibcon#about to write, iclass 23, count 0 2006.201.04:49:52.60#ibcon#wrote, iclass 23, count 0 2006.201.04:49:52.60#ibcon#about to read 3, iclass 23, count 0 2006.201.04:49:52.62#ibcon#read 3, iclass 23, count 0 2006.201.04:49:52.62#ibcon#about to read 4, iclass 23, count 0 2006.201.04:49:52.62#ibcon#read 4, iclass 23, count 0 2006.201.04:49:52.62#ibcon#about to read 5, iclass 23, count 0 2006.201.04:49:52.62#ibcon#read 5, iclass 23, count 0 2006.201.04:49:52.62#ibcon#about to read 6, iclass 23, count 0 2006.201.04:49:52.62#ibcon#read 6, iclass 23, count 0 2006.201.04:49:52.62#ibcon#end of sib2, iclass 23, count 0 2006.201.04:49:52.62#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:49:52.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:49:52.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:49:52.62#ibcon#*before write, iclass 23, count 0 2006.201.04:49:52.62#ibcon#enter sib2, iclass 23, count 0 2006.201.04:49:52.62#ibcon#flushed, iclass 23, count 0 2006.201.04:49:52.62#ibcon#about to write, iclass 23, count 0 2006.201.04:49:52.62#ibcon#wrote, iclass 23, count 0 2006.201.04:49:52.62#ibcon#about to read 3, iclass 23, count 0 2006.201.04:49:52.66#ibcon#read 3, iclass 23, count 0 2006.201.04:49:52.66#ibcon#about to read 4, iclass 23, count 0 2006.201.04:49:52.66#ibcon#read 4, iclass 23, count 0 2006.201.04:49:52.66#ibcon#about to read 5, iclass 23, count 0 2006.201.04:49:52.66#ibcon#read 5, iclass 23, count 0 2006.201.04:49:52.66#ibcon#about to read 6, iclass 23, count 0 2006.201.04:49:52.66#ibcon#read 6, iclass 23, count 0 2006.201.04:49:52.66#ibcon#end of sib2, iclass 23, count 0 2006.201.04:49:52.66#ibcon#*after write, iclass 23, count 0 2006.201.04:49:52.66#ibcon#*before return 0, iclass 23, count 0 2006.201.04:49:52.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:52.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:52.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:49:52.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:49:52.66$vck44/va=5,4 2006.201.04:49:52.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.04:49:52.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.04:49:52.66#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:52.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:52.72#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:52.72#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:52.72#ibcon#enter wrdev, iclass 25, count 2 2006.201.04:49:52.72#ibcon#first serial, iclass 25, count 2 2006.201.04:49:52.72#ibcon#enter sib2, iclass 25, count 2 2006.201.04:49:52.72#ibcon#flushed, iclass 25, count 2 2006.201.04:49:52.72#ibcon#about to write, iclass 25, count 2 2006.201.04:49:52.72#ibcon#wrote, iclass 25, count 2 2006.201.04:49:52.72#ibcon#about to read 3, iclass 25, count 2 2006.201.04:49:52.74#ibcon#read 3, iclass 25, count 2 2006.201.04:49:52.74#ibcon#about to read 4, iclass 25, count 2 2006.201.04:49:52.74#ibcon#read 4, iclass 25, count 2 2006.201.04:49:52.74#ibcon#about to read 5, iclass 25, count 2 2006.201.04:49:52.74#ibcon#read 5, iclass 25, count 2 2006.201.04:49:52.74#ibcon#about to read 6, iclass 25, count 2 2006.201.04:49:52.74#ibcon#read 6, iclass 25, count 2 2006.201.04:49:52.74#ibcon#end of sib2, iclass 25, count 2 2006.201.04:49:52.74#ibcon#*mode == 0, iclass 25, count 2 2006.201.04:49:52.74#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.04:49:52.74#ibcon#[25=AT05-04\r\n] 2006.201.04:49:52.74#ibcon#*before write, iclass 25, count 2 2006.201.04:49:52.74#ibcon#enter sib2, iclass 25, count 2 2006.201.04:49:52.74#ibcon#flushed, iclass 25, count 2 2006.201.04:49:52.74#ibcon#about to write, iclass 25, count 2 2006.201.04:49:52.74#ibcon#wrote, iclass 25, count 2 2006.201.04:49:52.74#ibcon#about to read 3, iclass 25, count 2 2006.201.04:49:52.77#ibcon#read 3, iclass 25, count 2 2006.201.04:49:52.77#ibcon#about to read 4, iclass 25, count 2 2006.201.04:49:52.77#ibcon#read 4, iclass 25, count 2 2006.201.04:49:52.77#ibcon#about to read 5, iclass 25, count 2 2006.201.04:49:52.77#ibcon#read 5, iclass 25, count 2 2006.201.04:49:52.77#ibcon#about to read 6, iclass 25, count 2 2006.201.04:49:52.77#ibcon#read 6, iclass 25, count 2 2006.201.04:49:52.77#ibcon#end of sib2, iclass 25, count 2 2006.201.04:49:52.77#ibcon#*after write, iclass 25, count 2 2006.201.04:49:52.77#ibcon#*before return 0, iclass 25, count 2 2006.201.04:49:52.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:52.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:52.77#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.04:49:52.77#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:52.77#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:52.89#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:52.89#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:52.89#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:49:52.89#ibcon#first serial, iclass 25, count 0 2006.201.04:49:52.89#ibcon#enter sib2, iclass 25, count 0 2006.201.04:49:52.89#ibcon#flushed, iclass 25, count 0 2006.201.04:49:52.89#ibcon#about to write, iclass 25, count 0 2006.201.04:49:52.89#ibcon#wrote, iclass 25, count 0 2006.201.04:49:52.89#ibcon#about to read 3, iclass 25, count 0 2006.201.04:49:52.91#ibcon#read 3, iclass 25, count 0 2006.201.04:49:52.91#ibcon#about to read 4, iclass 25, count 0 2006.201.04:49:52.91#ibcon#read 4, iclass 25, count 0 2006.201.04:49:52.91#ibcon#about to read 5, iclass 25, count 0 2006.201.04:49:52.91#ibcon#read 5, iclass 25, count 0 2006.201.04:49:52.91#ibcon#about to read 6, iclass 25, count 0 2006.201.04:49:52.91#ibcon#read 6, iclass 25, count 0 2006.201.04:49:52.91#ibcon#end of sib2, iclass 25, count 0 2006.201.04:49:52.91#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:49:52.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:49:52.91#ibcon#[25=USB\r\n] 2006.201.04:49:52.91#ibcon#*before write, iclass 25, count 0 2006.201.04:49:52.91#ibcon#enter sib2, iclass 25, count 0 2006.201.04:49:52.91#ibcon#flushed, iclass 25, count 0 2006.201.04:49:52.91#ibcon#about to write, iclass 25, count 0 2006.201.04:49:52.91#ibcon#wrote, iclass 25, count 0 2006.201.04:49:52.91#ibcon#about to read 3, iclass 25, count 0 2006.201.04:49:52.94#ibcon#read 3, iclass 25, count 0 2006.201.04:49:52.94#ibcon#about to read 4, iclass 25, count 0 2006.201.04:49:52.94#ibcon#read 4, iclass 25, count 0 2006.201.04:49:52.94#ibcon#about to read 5, iclass 25, count 0 2006.201.04:49:52.94#ibcon#read 5, iclass 25, count 0 2006.201.04:49:52.94#ibcon#about to read 6, iclass 25, count 0 2006.201.04:49:52.94#ibcon#read 6, iclass 25, count 0 2006.201.04:49:52.94#ibcon#end of sib2, iclass 25, count 0 2006.201.04:49:52.94#ibcon#*after write, iclass 25, count 0 2006.201.04:49:52.94#ibcon#*before return 0, iclass 25, count 0 2006.201.04:49:52.94#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:52.94#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:52.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:49:52.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:49:52.94$vck44/valo=6,814.99 2006.201.04:49:52.94#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.04:49:52.94#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.04:49:52.94#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:52.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:52.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:52.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:52.94#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:49:52.94#ibcon#first serial, iclass 27, count 0 2006.201.04:49:52.94#ibcon#enter sib2, iclass 27, count 0 2006.201.04:49:52.94#ibcon#flushed, iclass 27, count 0 2006.201.04:49:52.94#ibcon#about to write, iclass 27, count 0 2006.201.04:49:52.94#ibcon#wrote, iclass 27, count 0 2006.201.04:49:52.94#ibcon#about to read 3, iclass 27, count 0 2006.201.04:49:52.96#ibcon#read 3, iclass 27, count 0 2006.201.04:49:52.96#ibcon#about to read 4, iclass 27, count 0 2006.201.04:49:52.96#ibcon#read 4, iclass 27, count 0 2006.201.04:49:52.96#ibcon#about to read 5, iclass 27, count 0 2006.201.04:49:52.96#ibcon#read 5, iclass 27, count 0 2006.201.04:49:52.96#ibcon#about to read 6, iclass 27, count 0 2006.201.04:49:52.96#ibcon#read 6, iclass 27, count 0 2006.201.04:49:52.96#ibcon#end of sib2, iclass 27, count 0 2006.201.04:49:52.96#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:49:52.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:49:52.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:49:52.96#ibcon#*before write, iclass 27, count 0 2006.201.04:49:52.96#ibcon#enter sib2, iclass 27, count 0 2006.201.04:49:52.96#ibcon#flushed, iclass 27, count 0 2006.201.04:49:52.96#ibcon#about to write, iclass 27, count 0 2006.201.04:49:52.96#ibcon#wrote, iclass 27, count 0 2006.201.04:49:52.96#ibcon#about to read 3, iclass 27, count 0 2006.201.04:49:53.00#ibcon#read 3, iclass 27, count 0 2006.201.04:49:53.00#ibcon#about to read 4, iclass 27, count 0 2006.201.04:49:53.00#ibcon#read 4, iclass 27, count 0 2006.201.04:49:53.00#ibcon#about to read 5, iclass 27, count 0 2006.201.04:49:53.00#ibcon#read 5, iclass 27, count 0 2006.201.04:49:53.00#ibcon#about to read 6, iclass 27, count 0 2006.201.04:49:53.00#ibcon#read 6, iclass 27, count 0 2006.201.04:49:53.00#ibcon#end of sib2, iclass 27, count 0 2006.201.04:49:53.00#ibcon#*after write, iclass 27, count 0 2006.201.04:49:53.00#ibcon#*before return 0, iclass 27, count 0 2006.201.04:49:53.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:53.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:53.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:49:53.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:49:53.00$vck44/va=6,5 2006.201.04:49:53.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.04:49:53.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.04:49:53.00#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:53.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:53.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:53.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:53.06#ibcon#enter wrdev, iclass 29, count 2 2006.201.04:49:53.06#ibcon#first serial, iclass 29, count 2 2006.201.04:49:53.06#ibcon#enter sib2, iclass 29, count 2 2006.201.04:49:53.06#ibcon#flushed, iclass 29, count 2 2006.201.04:49:53.06#ibcon#about to write, iclass 29, count 2 2006.201.04:49:53.06#ibcon#wrote, iclass 29, count 2 2006.201.04:49:53.06#ibcon#about to read 3, iclass 29, count 2 2006.201.04:49:53.08#ibcon#read 3, iclass 29, count 2 2006.201.04:49:53.08#ibcon#about to read 4, iclass 29, count 2 2006.201.04:49:53.08#ibcon#read 4, iclass 29, count 2 2006.201.04:49:53.08#ibcon#about to read 5, iclass 29, count 2 2006.201.04:49:53.08#ibcon#read 5, iclass 29, count 2 2006.201.04:49:53.08#ibcon#about to read 6, iclass 29, count 2 2006.201.04:49:53.08#ibcon#read 6, iclass 29, count 2 2006.201.04:49:53.08#ibcon#end of sib2, iclass 29, count 2 2006.201.04:49:53.08#ibcon#*mode == 0, iclass 29, count 2 2006.201.04:49:53.08#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.04:49:53.08#ibcon#[25=AT06-05\r\n] 2006.201.04:49:53.08#ibcon#*before write, iclass 29, count 2 2006.201.04:49:53.08#ibcon#enter sib2, iclass 29, count 2 2006.201.04:49:53.08#ibcon#flushed, iclass 29, count 2 2006.201.04:49:53.08#ibcon#about to write, iclass 29, count 2 2006.201.04:49:53.08#ibcon#wrote, iclass 29, count 2 2006.201.04:49:53.08#ibcon#about to read 3, iclass 29, count 2 2006.201.04:49:53.11#ibcon#read 3, iclass 29, count 2 2006.201.04:49:53.11#ibcon#about to read 4, iclass 29, count 2 2006.201.04:49:53.11#ibcon#read 4, iclass 29, count 2 2006.201.04:49:53.11#ibcon#about to read 5, iclass 29, count 2 2006.201.04:49:53.11#ibcon#read 5, iclass 29, count 2 2006.201.04:49:53.11#ibcon#about to read 6, iclass 29, count 2 2006.201.04:49:53.11#ibcon#read 6, iclass 29, count 2 2006.201.04:49:53.11#ibcon#end of sib2, iclass 29, count 2 2006.201.04:49:53.11#ibcon#*after write, iclass 29, count 2 2006.201.04:49:53.11#ibcon#*before return 0, iclass 29, count 2 2006.201.04:49:53.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:53.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:53.11#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.04:49:53.11#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:53.11#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:53.23#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:53.23#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:53.23#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:49:53.23#ibcon#first serial, iclass 29, count 0 2006.201.04:49:53.23#ibcon#enter sib2, iclass 29, count 0 2006.201.04:49:53.23#ibcon#flushed, iclass 29, count 0 2006.201.04:49:53.23#ibcon#about to write, iclass 29, count 0 2006.201.04:49:53.23#ibcon#wrote, iclass 29, count 0 2006.201.04:49:53.23#ibcon#about to read 3, iclass 29, count 0 2006.201.04:49:53.25#ibcon#read 3, iclass 29, count 0 2006.201.04:49:53.25#ibcon#about to read 4, iclass 29, count 0 2006.201.04:49:53.25#ibcon#read 4, iclass 29, count 0 2006.201.04:49:53.25#ibcon#about to read 5, iclass 29, count 0 2006.201.04:49:53.25#ibcon#read 5, iclass 29, count 0 2006.201.04:49:53.25#ibcon#about to read 6, iclass 29, count 0 2006.201.04:49:53.25#ibcon#read 6, iclass 29, count 0 2006.201.04:49:53.25#ibcon#end of sib2, iclass 29, count 0 2006.201.04:49:53.25#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:49:53.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:49:53.25#ibcon#[25=USB\r\n] 2006.201.04:49:53.25#ibcon#*before write, iclass 29, count 0 2006.201.04:49:53.25#ibcon#enter sib2, iclass 29, count 0 2006.201.04:49:53.25#ibcon#flushed, iclass 29, count 0 2006.201.04:49:53.25#ibcon#about to write, iclass 29, count 0 2006.201.04:49:53.25#ibcon#wrote, iclass 29, count 0 2006.201.04:49:53.25#ibcon#about to read 3, iclass 29, count 0 2006.201.04:49:53.28#ibcon#read 3, iclass 29, count 0 2006.201.04:49:53.28#ibcon#about to read 4, iclass 29, count 0 2006.201.04:49:53.28#ibcon#read 4, iclass 29, count 0 2006.201.04:49:53.28#ibcon#about to read 5, iclass 29, count 0 2006.201.04:49:53.28#ibcon#read 5, iclass 29, count 0 2006.201.04:49:53.28#ibcon#about to read 6, iclass 29, count 0 2006.201.04:49:53.28#ibcon#read 6, iclass 29, count 0 2006.201.04:49:53.28#ibcon#end of sib2, iclass 29, count 0 2006.201.04:49:53.28#ibcon#*after write, iclass 29, count 0 2006.201.04:49:53.28#ibcon#*before return 0, iclass 29, count 0 2006.201.04:49:53.28#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:53.28#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:53.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:49:53.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:49:53.28$vck44/valo=7,864.99 2006.201.04:49:53.28#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.04:49:53.28#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.04:49:53.28#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:53.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:53.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:53.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:53.28#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:49:53.28#ibcon#first serial, iclass 31, count 0 2006.201.04:49:53.28#ibcon#enter sib2, iclass 31, count 0 2006.201.04:49:53.28#ibcon#flushed, iclass 31, count 0 2006.201.04:49:53.28#ibcon#about to write, iclass 31, count 0 2006.201.04:49:53.28#ibcon#wrote, iclass 31, count 0 2006.201.04:49:53.28#ibcon#about to read 3, iclass 31, count 0 2006.201.04:49:53.30#ibcon#read 3, iclass 31, count 0 2006.201.04:49:53.30#ibcon#about to read 4, iclass 31, count 0 2006.201.04:49:53.30#ibcon#read 4, iclass 31, count 0 2006.201.04:49:53.30#ibcon#about to read 5, iclass 31, count 0 2006.201.04:49:53.30#ibcon#read 5, iclass 31, count 0 2006.201.04:49:53.30#ibcon#about to read 6, iclass 31, count 0 2006.201.04:49:53.30#ibcon#read 6, iclass 31, count 0 2006.201.04:49:53.30#ibcon#end of sib2, iclass 31, count 0 2006.201.04:49:53.30#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:49:53.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:49:53.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:49:53.30#ibcon#*before write, iclass 31, count 0 2006.201.04:49:53.30#ibcon#enter sib2, iclass 31, count 0 2006.201.04:49:53.30#ibcon#flushed, iclass 31, count 0 2006.201.04:49:53.30#ibcon#about to write, iclass 31, count 0 2006.201.04:49:53.30#ibcon#wrote, iclass 31, count 0 2006.201.04:49:53.30#ibcon#about to read 3, iclass 31, count 0 2006.201.04:49:53.34#ibcon#read 3, iclass 31, count 0 2006.201.04:49:53.34#ibcon#about to read 4, iclass 31, count 0 2006.201.04:49:53.34#ibcon#read 4, iclass 31, count 0 2006.201.04:49:53.34#ibcon#about to read 5, iclass 31, count 0 2006.201.04:49:53.34#ibcon#read 5, iclass 31, count 0 2006.201.04:49:53.34#ibcon#about to read 6, iclass 31, count 0 2006.201.04:49:53.34#ibcon#read 6, iclass 31, count 0 2006.201.04:49:53.34#ibcon#end of sib2, iclass 31, count 0 2006.201.04:49:53.34#ibcon#*after write, iclass 31, count 0 2006.201.04:49:53.34#ibcon#*before return 0, iclass 31, count 0 2006.201.04:49:53.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:53.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:53.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:49:53.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:49:53.34$vck44/va=7,5 2006.201.04:49:53.34#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.04:49:53.34#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.04:49:53.34#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:53.34#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:53.40#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:53.40#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:53.40#ibcon#enter wrdev, iclass 33, count 2 2006.201.04:49:53.40#ibcon#first serial, iclass 33, count 2 2006.201.04:49:53.40#ibcon#enter sib2, iclass 33, count 2 2006.201.04:49:53.40#ibcon#flushed, iclass 33, count 2 2006.201.04:49:53.40#ibcon#about to write, iclass 33, count 2 2006.201.04:49:53.40#ibcon#wrote, iclass 33, count 2 2006.201.04:49:53.40#ibcon#about to read 3, iclass 33, count 2 2006.201.04:49:53.42#ibcon#read 3, iclass 33, count 2 2006.201.04:49:53.42#ibcon#about to read 4, iclass 33, count 2 2006.201.04:49:53.42#ibcon#read 4, iclass 33, count 2 2006.201.04:49:53.42#ibcon#about to read 5, iclass 33, count 2 2006.201.04:49:53.42#ibcon#read 5, iclass 33, count 2 2006.201.04:49:53.42#ibcon#about to read 6, iclass 33, count 2 2006.201.04:49:53.42#ibcon#read 6, iclass 33, count 2 2006.201.04:49:53.42#ibcon#end of sib2, iclass 33, count 2 2006.201.04:49:53.42#ibcon#*mode == 0, iclass 33, count 2 2006.201.04:49:53.42#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.04:49:53.42#ibcon#[25=AT07-05\r\n] 2006.201.04:49:53.42#ibcon#*before write, iclass 33, count 2 2006.201.04:49:53.42#ibcon#enter sib2, iclass 33, count 2 2006.201.04:49:53.42#ibcon#flushed, iclass 33, count 2 2006.201.04:49:53.42#ibcon#about to write, iclass 33, count 2 2006.201.04:49:53.42#ibcon#wrote, iclass 33, count 2 2006.201.04:49:53.42#ibcon#about to read 3, iclass 33, count 2 2006.201.04:49:53.45#ibcon#read 3, iclass 33, count 2 2006.201.04:49:53.48#ibcon#about to read 4, iclass 33, count 2 2006.201.04:49:53.48#ibcon#read 4, iclass 33, count 2 2006.201.04:49:53.48#ibcon#about to read 5, iclass 33, count 2 2006.201.04:49:53.48#ibcon#read 5, iclass 33, count 2 2006.201.04:49:53.48#ibcon#about to read 6, iclass 33, count 2 2006.201.04:49:53.48#ibcon#read 6, iclass 33, count 2 2006.201.04:49:53.48#ibcon#end of sib2, iclass 33, count 2 2006.201.04:49:53.48#ibcon#*after write, iclass 33, count 2 2006.201.04:49:53.48#ibcon#*before return 0, iclass 33, count 2 2006.201.04:49:53.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:53.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:53.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.04:49:53.48#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:53.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:53.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:53.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:53.60#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:49:53.60#ibcon#first serial, iclass 33, count 0 2006.201.04:49:53.60#ibcon#enter sib2, iclass 33, count 0 2006.201.04:49:53.60#ibcon#flushed, iclass 33, count 0 2006.201.04:49:53.60#ibcon#about to write, iclass 33, count 0 2006.201.04:49:53.60#ibcon#wrote, iclass 33, count 0 2006.201.04:49:53.60#ibcon#about to read 3, iclass 33, count 0 2006.201.04:49:53.62#ibcon#read 3, iclass 33, count 0 2006.201.04:49:53.62#ibcon#about to read 4, iclass 33, count 0 2006.201.04:49:53.62#ibcon#read 4, iclass 33, count 0 2006.201.04:49:53.62#ibcon#about to read 5, iclass 33, count 0 2006.201.04:49:53.62#ibcon#read 5, iclass 33, count 0 2006.201.04:49:53.62#ibcon#about to read 6, iclass 33, count 0 2006.201.04:49:53.62#ibcon#read 6, iclass 33, count 0 2006.201.04:49:53.62#ibcon#end of sib2, iclass 33, count 0 2006.201.04:49:53.62#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:49:53.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:49:53.62#ibcon#[25=USB\r\n] 2006.201.04:49:53.62#ibcon#*before write, iclass 33, count 0 2006.201.04:49:53.62#ibcon#enter sib2, iclass 33, count 0 2006.201.04:49:53.62#ibcon#flushed, iclass 33, count 0 2006.201.04:49:53.62#ibcon#about to write, iclass 33, count 0 2006.201.04:49:53.62#ibcon#wrote, iclass 33, count 0 2006.201.04:49:53.62#ibcon#about to read 3, iclass 33, count 0 2006.201.04:49:53.65#ibcon#read 3, iclass 33, count 0 2006.201.04:49:53.65#ibcon#about to read 4, iclass 33, count 0 2006.201.04:49:53.65#ibcon#read 4, iclass 33, count 0 2006.201.04:49:53.65#ibcon#about to read 5, iclass 33, count 0 2006.201.04:49:53.65#ibcon#read 5, iclass 33, count 0 2006.201.04:49:53.65#ibcon#about to read 6, iclass 33, count 0 2006.201.04:49:53.65#ibcon#read 6, iclass 33, count 0 2006.201.04:49:53.65#ibcon#end of sib2, iclass 33, count 0 2006.201.04:49:53.65#ibcon#*after write, iclass 33, count 0 2006.201.04:49:53.65#ibcon#*before return 0, iclass 33, count 0 2006.201.04:49:53.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:53.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:53.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:49:53.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:49:53.65$vck44/valo=8,884.99 2006.201.04:49:53.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.04:49:53.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.04:49:53.65#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:53.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:49:53.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:49:53.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:49:53.65#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:49:53.65#ibcon#first serial, iclass 35, count 0 2006.201.04:49:53.65#ibcon#enter sib2, iclass 35, count 0 2006.201.04:49:53.65#ibcon#flushed, iclass 35, count 0 2006.201.04:49:53.65#ibcon#about to write, iclass 35, count 0 2006.201.04:49:53.65#ibcon#wrote, iclass 35, count 0 2006.201.04:49:53.65#ibcon#about to read 3, iclass 35, count 0 2006.201.04:49:53.67#ibcon#read 3, iclass 35, count 0 2006.201.04:49:53.67#ibcon#about to read 4, iclass 35, count 0 2006.201.04:49:53.67#ibcon#read 4, iclass 35, count 0 2006.201.04:49:53.67#ibcon#about to read 5, iclass 35, count 0 2006.201.04:49:53.67#ibcon#read 5, iclass 35, count 0 2006.201.04:49:53.67#ibcon#about to read 6, iclass 35, count 0 2006.201.04:49:53.67#ibcon#read 6, iclass 35, count 0 2006.201.04:49:53.67#ibcon#end of sib2, iclass 35, count 0 2006.201.04:49:53.67#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:49:53.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:49:53.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:49:53.67#ibcon#*before write, iclass 35, count 0 2006.201.04:49:53.67#ibcon#enter sib2, iclass 35, count 0 2006.201.04:49:53.67#ibcon#flushed, iclass 35, count 0 2006.201.04:49:53.67#ibcon#about to write, iclass 35, count 0 2006.201.04:49:53.67#ibcon#wrote, iclass 35, count 0 2006.201.04:49:53.67#ibcon#about to read 3, iclass 35, count 0 2006.201.04:49:53.71#ibcon#read 3, iclass 35, count 0 2006.201.04:49:53.71#ibcon#about to read 4, iclass 35, count 0 2006.201.04:49:53.71#ibcon#read 4, iclass 35, count 0 2006.201.04:49:53.71#ibcon#about to read 5, iclass 35, count 0 2006.201.04:49:53.71#ibcon#read 5, iclass 35, count 0 2006.201.04:49:53.71#ibcon#about to read 6, iclass 35, count 0 2006.201.04:49:53.71#ibcon#read 6, iclass 35, count 0 2006.201.04:49:53.71#ibcon#end of sib2, iclass 35, count 0 2006.201.04:49:53.71#ibcon#*after write, iclass 35, count 0 2006.201.04:49:53.71#ibcon#*before return 0, iclass 35, count 0 2006.201.04:49:53.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:49:53.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.04:49:53.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:49:53.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:49:53.71$vck44/va=8,4 2006.201.04:49:53.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.04:49:53.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.04:49:53.71#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:53.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:49:53.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:49:53.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:49:53.77#ibcon#enter wrdev, iclass 37, count 2 2006.201.04:49:53.77#ibcon#first serial, iclass 37, count 2 2006.201.04:49:53.77#ibcon#enter sib2, iclass 37, count 2 2006.201.04:49:53.77#ibcon#flushed, iclass 37, count 2 2006.201.04:49:53.77#ibcon#about to write, iclass 37, count 2 2006.201.04:49:53.77#ibcon#wrote, iclass 37, count 2 2006.201.04:49:53.77#ibcon#about to read 3, iclass 37, count 2 2006.201.04:49:53.79#ibcon#read 3, iclass 37, count 2 2006.201.04:49:53.79#ibcon#about to read 4, iclass 37, count 2 2006.201.04:49:53.79#ibcon#read 4, iclass 37, count 2 2006.201.04:49:53.79#ibcon#about to read 5, iclass 37, count 2 2006.201.04:49:53.79#ibcon#read 5, iclass 37, count 2 2006.201.04:49:53.79#ibcon#about to read 6, iclass 37, count 2 2006.201.04:49:53.79#ibcon#read 6, iclass 37, count 2 2006.201.04:49:53.79#ibcon#end of sib2, iclass 37, count 2 2006.201.04:49:53.79#ibcon#*mode == 0, iclass 37, count 2 2006.201.04:49:53.79#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.04:49:53.79#ibcon#[25=AT08-04\r\n] 2006.201.04:49:53.79#ibcon#*before write, iclass 37, count 2 2006.201.04:49:53.79#ibcon#enter sib2, iclass 37, count 2 2006.201.04:49:53.79#ibcon#flushed, iclass 37, count 2 2006.201.04:49:53.79#ibcon#about to write, iclass 37, count 2 2006.201.04:49:53.79#ibcon#wrote, iclass 37, count 2 2006.201.04:49:53.79#ibcon#about to read 3, iclass 37, count 2 2006.201.04:49:53.82#ibcon#read 3, iclass 37, count 2 2006.201.04:49:53.82#ibcon#about to read 4, iclass 37, count 2 2006.201.04:49:53.82#ibcon#read 4, iclass 37, count 2 2006.201.04:49:53.82#ibcon#about to read 5, iclass 37, count 2 2006.201.04:49:53.82#ibcon#read 5, iclass 37, count 2 2006.201.04:49:53.82#ibcon#about to read 6, iclass 37, count 2 2006.201.04:49:53.82#ibcon#read 6, iclass 37, count 2 2006.201.04:49:53.82#ibcon#end of sib2, iclass 37, count 2 2006.201.04:49:53.82#ibcon#*after write, iclass 37, count 2 2006.201.04:49:53.82#ibcon#*before return 0, iclass 37, count 2 2006.201.04:49:53.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:49:53.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.04:49:53.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.04:49:53.82#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:53.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:49:53.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:49:53.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:49:53.94#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:49:53.94#ibcon#first serial, iclass 37, count 0 2006.201.04:49:53.94#ibcon#enter sib2, iclass 37, count 0 2006.201.04:49:53.94#ibcon#flushed, iclass 37, count 0 2006.201.04:49:53.94#ibcon#about to write, iclass 37, count 0 2006.201.04:49:53.94#ibcon#wrote, iclass 37, count 0 2006.201.04:49:53.94#ibcon#about to read 3, iclass 37, count 0 2006.201.04:49:53.96#ibcon#read 3, iclass 37, count 0 2006.201.04:49:53.96#ibcon#about to read 4, iclass 37, count 0 2006.201.04:49:53.96#ibcon#read 4, iclass 37, count 0 2006.201.04:49:53.96#ibcon#about to read 5, iclass 37, count 0 2006.201.04:49:53.96#ibcon#read 5, iclass 37, count 0 2006.201.04:49:53.96#ibcon#about to read 6, iclass 37, count 0 2006.201.04:49:53.96#ibcon#read 6, iclass 37, count 0 2006.201.04:49:53.96#ibcon#end of sib2, iclass 37, count 0 2006.201.04:49:53.96#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:49:53.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:49:53.96#ibcon#[25=USB\r\n] 2006.201.04:49:53.96#ibcon#*before write, iclass 37, count 0 2006.201.04:49:53.96#ibcon#enter sib2, iclass 37, count 0 2006.201.04:49:53.96#ibcon#flushed, iclass 37, count 0 2006.201.04:49:53.96#ibcon#about to write, iclass 37, count 0 2006.201.04:49:53.96#ibcon#wrote, iclass 37, count 0 2006.201.04:49:53.96#ibcon#about to read 3, iclass 37, count 0 2006.201.04:49:53.99#ibcon#read 3, iclass 37, count 0 2006.201.04:49:53.99#ibcon#about to read 4, iclass 37, count 0 2006.201.04:49:53.99#ibcon#read 4, iclass 37, count 0 2006.201.04:49:53.99#ibcon#about to read 5, iclass 37, count 0 2006.201.04:49:53.99#ibcon#read 5, iclass 37, count 0 2006.201.04:49:53.99#ibcon#about to read 6, iclass 37, count 0 2006.201.04:49:53.99#ibcon#read 6, iclass 37, count 0 2006.201.04:49:53.99#ibcon#end of sib2, iclass 37, count 0 2006.201.04:49:53.99#ibcon#*after write, iclass 37, count 0 2006.201.04:49:53.99#ibcon#*before return 0, iclass 37, count 0 2006.201.04:49:53.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:49:53.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.04:49:53.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:49:53.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:49:53.99$vck44/vblo=1,629.99 2006.201.04:49:53.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.04:49:53.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.04:49:53.99#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:53.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:53.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:53.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:53.99#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:49:53.99#ibcon#first serial, iclass 39, count 0 2006.201.04:49:53.99#ibcon#enter sib2, iclass 39, count 0 2006.201.04:49:53.99#ibcon#flushed, iclass 39, count 0 2006.201.04:49:53.99#ibcon#about to write, iclass 39, count 0 2006.201.04:49:53.99#ibcon#wrote, iclass 39, count 0 2006.201.04:49:53.99#ibcon#about to read 3, iclass 39, count 0 2006.201.04:49:54.01#ibcon#read 3, iclass 39, count 0 2006.201.04:49:54.01#ibcon#about to read 4, iclass 39, count 0 2006.201.04:49:54.01#ibcon#read 4, iclass 39, count 0 2006.201.04:49:54.01#ibcon#about to read 5, iclass 39, count 0 2006.201.04:49:54.01#ibcon#read 5, iclass 39, count 0 2006.201.04:49:54.01#ibcon#about to read 6, iclass 39, count 0 2006.201.04:49:54.01#ibcon#read 6, iclass 39, count 0 2006.201.04:49:54.01#ibcon#end of sib2, iclass 39, count 0 2006.201.04:49:54.01#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:49:54.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:49:54.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:49:54.01#ibcon#*before write, iclass 39, count 0 2006.201.04:49:54.01#ibcon#enter sib2, iclass 39, count 0 2006.201.04:49:54.01#ibcon#flushed, iclass 39, count 0 2006.201.04:49:54.01#ibcon#about to write, iclass 39, count 0 2006.201.04:49:54.01#ibcon#wrote, iclass 39, count 0 2006.201.04:49:54.01#ibcon#about to read 3, iclass 39, count 0 2006.201.04:49:54.05#ibcon#read 3, iclass 39, count 0 2006.201.04:49:54.05#ibcon#about to read 4, iclass 39, count 0 2006.201.04:49:54.05#ibcon#read 4, iclass 39, count 0 2006.201.04:49:54.05#ibcon#about to read 5, iclass 39, count 0 2006.201.04:49:54.05#ibcon#read 5, iclass 39, count 0 2006.201.04:49:54.05#ibcon#about to read 6, iclass 39, count 0 2006.201.04:49:54.05#ibcon#read 6, iclass 39, count 0 2006.201.04:49:54.05#ibcon#end of sib2, iclass 39, count 0 2006.201.04:49:54.05#ibcon#*after write, iclass 39, count 0 2006.201.04:49:54.05#ibcon#*before return 0, iclass 39, count 0 2006.201.04:49:54.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:54.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:54.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:49:54.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:49:54.05$vck44/vb=1,4 2006.201.04:49:54.05#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.04:49:54.05#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.04:49:54.05#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:54.05#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:49:54.05#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:49:54.05#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:49:54.05#ibcon#enter wrdev, iclass 2, count 2 2006.201.04:49:54.05#ibcon#first serial, iclass 2, count 2 2006.201.04:49:54.05#ibcon#enter sib2, iclass 2, count 2 2006.201.04:49:54.05#ibcon#flushed, iclass 2, count 2 2006.201.04:49:54.05#ibcon#about to write, iclass 2, count 2 2006.201.04:49:54.05#ibcon#wrote, iclass 2, count 2 2006.201.04:49:54.05#ibcon#about to read 3, iclass 2, count 2 2006.201.04:49:54.07#ibcon#read 3, iclass 2, count 2 2006.201.04:49:54.07#ibcon#about to read 4, iclass 2, count 2 2006.201.04:49:54.07#ibcon#read 4, iclass 2, count 2 2006.201.04:49:54.07#ibcon#about to read 5, iclass 2, count 2 2006.201.04:49:54.07#ibcon#read 5, iclass 2, count 2 2006.201.04:49:54.07#ibcon#about to read 6, iclass 2, count 2 2006.201.04:49:54.07#ibcon#read 6, iclass 2, count 2 2006.201.04:49:54.07#ibcon#end of sib2, iclass 2, count 2 2006.201.04:49:54.07#ibcon#*mode == 0, iclass 2, count 2 2006.201.04:49:54.07#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.04:49:54.07#ibcon#[27=AT01-04\r\n] 2006.201.04:49:54.07#ibcon#*before write, iclass 2, count 2 2006.201.04:49:54.07#ibcon#enter sib2, iclass 2, count 2 2006.201.04:49:54.07#ibcon#flushed, iclass 2, count 2 2006.201.04:49:54.07#ibcon#about to write, iclass 2, count 2 2006.201.04:49:54.07#ibcon#wrote, iclass 2, count 2 2006.201.04:49:54.07#ibcon#about to read 3, iclass 2, count 2 2006.201.04:49:54.10#ibcon#read 3, iclass 2, count 2 2006.201.04:49:54.10#ibcon#about to read 4, iclass 2, count 2 2006.201.04:49:54.10#ibcon#read 4, iclass 2, count 2 2006.201.04:49:54.10#ibcon#about to read 5, iclass 2, count 2 2006.201.04:49:54.10#ibcon#read 5, iclass 2, count 2 2006.201.04:49:54.10#ibcon#about to read 6, iclass 2, count 2 2006.201.04:49:54.10#ibcon#read 6, iclass 2, count 2 2006.201.04:49:54.10#ibcon#end of sib2, iclass 2, count 2 2006.201.04:49:54.10#ibcon#*after write, iclass 2, count 2 2006.201.04:49:54.10#ibcon#*before return 0, iclass 2, count 2 2006.201.04:49:54.10#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:49:54.10#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.04:49:54.10#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.04:49:54.10#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:54.10#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:49:54.22#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:49:54.22#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:49:54.22#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:49:54.22#ibcon#first serial, iclass 2, count 0 2006.201.04:49:54.22#ibcon#enter sib2, iclass 2, count 0 2006.201.04:49:54.22#ibcon#flushed, iclass 2, count 0 2006.201.04:49:54.22#ibcon#about to write, iclass 2, count 0 2006.201.04:49:54.22#ibcon#wrote, iclass 2, count 0 2006.201.04:49:54.22#ibcon#about to read 3, iclass 2, count 0 2006.201.04:49:54.24#ibcon#read 3, iclass 2, count 0 2006.201.04:49:54.24#ibcon#about to read 4, iclass 2, count 0 2006.201.04:49:54.24#ibcon#read 4, iclass 2, count 0 2006.201.04:49:54.24#ibcon#about to read 5, iclass 2, count 0 2006.201.04:49:54.24#ibcon#read 5, iclass 2, count 0 2006.201.04:49:54.24#ibcon#about to read 6, iclass 2, count 0 2006.201.04:49:54.24#ibcon#read 6, iclass 2, count 0 2006.201.04:49:54.24#ibcon#end of sib2, iclass 2, count 0 2006.201.04:49:54.24#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:49:54.24#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:49:54.24#ibcon#[27=USB\r\n] 2006.201.04:49:54.24#ibcon#*before write, iclass 2, count 0 2006.201.04:49:54.24#ibcon#enter sib2, iclass 2, count 0 2006.201.04:49:54.24#ibcon#flushed, iclass 2, count 0 2006.201.04:49:54.24#ibcon#about to write, iclass 2, count 0 2006.201.04:49:54.24#ibcon#wrote, iclass 2, count 0 2006.201.04:49:54.24#ibcon#about to read 3, iclass 2, count 0 2006.201.04:49:54.27#ibcon#read 3, iclass 2, count 0 2006.201.04:49:54.27#ibcon#about to read 4, iclass 2, count 0 2006.201.04:49:54.27#ibcon#read 4, iclass 2, count 0 2006.201.04:49:54.27#ibcon#about to read 5, iclass 2, count 0 2006.201.04:49:54.27#ibcon#read 5, iclass 2, count 0 2006.201.04:49:54.27#ibcon#about to read 6, iclass 2, count 0 2006.201.04:49:54.27#ibcon#read 6, iclass 2, count 0 2006.201.04:49:54.27#ibcon#end of sib2, iclass 2, count 0 2006.201.04:49:54.27#ibcon#*after write, iclass 2, count 0 2006.201.04:49:54.27#ibcon#*before return 0, iclass 2, count 0 2006.201.04:49:54.27#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:49:54.27#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.04:49:54.27#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:49:54.27#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:49:54.27$vck44/vblo=2,634.99 2006.201.04:49:54.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.04:49:54.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.04:49:54.27#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:54.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:54.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:54.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:54.27#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:49:54.27#ibcon#first serial, iclass 5, count 0 2006.201.04:49:54.27#ibcon#enter sib2, iclass 5, count 0 2006.201.04:49:54.27#ibcon#flushed, iclass 5, count 0 2006.201.04:49:54.27#ibcon#about to write, iclass 5, count 0 2006.201.04:49:54.27#ibcon#wrote, iclass 5, count 0 2006.201.04:49:54.27#ibcon#about to read 3, iclass 5, count 0 2006.201.04:49:54.29#ibcon#read 3, iclass 5, count 0 2006.201.04:49:54.29#ibcon#about to read 4, iclass 5, count 0 2006.201.04:49:54.29#ibcon#read 4, iclass 5, count 0 2006.201.04:49:54.29#ibcon#about to read 5, iclass 5, count 0 2006.201.04:49:54.29#ibcon#read 5, iclass 5, count 0 2006.201.04:49:54.29#ibcon#about to read 6, iclass 5, count 0 2006.201.04:49:54.29#ibcon#read 6, iclass 5, count 0 2006.201.04:49:54.29#ibcon#end of sib2, iclass 5, count 0 2006.201.04:49:54.29#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:49:54.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:49:54.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:49:54.29#ibcon#*before write, iclass 5, count 0 2006.201.04:49:54.29#ibcon#enter sib2, iclass 5, count 0 2006.201.04:49:54.29#ibcon#flushed, iclass 5, count 0 2006.201.04:49:54.29#ibcon#about to write, iclass 5, count 0 2006.201.04:49:54.29#ibcon#wrote, iclass 5, count 0 2006.201.04:49:54.29#ibcon#about to read 3, iclass 5, count 0 2006.201.04:49:54.33#ibcon#read 3, iclass 5, count 0 2006.201.04:49:54.33#ibcon#about to read 4, iclass 5, count 0 2006.201.04:49:54.33#ibcon#read 4, iclass 5, count 0 2006.201.04:49:54.33#ibcon#about to read 5, iclass 5, count 0 2006.201.04:49:54.33#ibcon#read 5, iclass 5, count 0 2006.201.04:49:54.33#ibcon#about to read 6, iclass 5, count 0 2006.201.04:49:54.33#ibcon#read 6, iclass 5, count 0 2006.201.04:49:54.33#ibcon#end of sib2, iclass 5, count 0 2006.201.04:49:54.33#ibcon#*after write, iclass 5, count 0 2006.201.04:49:54.33#ibcon#*before return 0, iclass 5, count 0 2006.201.04:49:54.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:54.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.04:49:54.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:49:54.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:49:54.33$vck44/vb=2,5 2006.201.04:49:54.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.04:49:54.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.04:49:54.33#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:54.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:54.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:54.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:54.39#ibcon#enter wrdev, iclass 7, count 2 2006.201.04:49:54.39#ibcon#first serial, iclass 7, count 2 2006.201.04:49:54.39#ibcon#enter sib2, iclass 7, count 2 2006.201.04:49:54.39#ibcon#flushed, iclass 7, count 2 2006.201.04:49:54.39#ibcon#about to write, iclass 7, count 2 2006.201.04:49:54.39#ibcon#wrote, iclass 7, count 2 2006.201.04:49:54.39#ibcon#about to read 3, iclass 7, count 2 2006.201.04:49:54.41#ibcon#read 3, iclass 7, count 2 2006.201.04:49:54.41#ibcon#about to read 4, iclass 7, count 2 2006.201.04:49:54.41#ibcon#read 4, iclass 7, count 2 2006.201.04:49:54.41#ibcon#about to read 5, iclass 7, count 2 2006.201.04:49:54.41#ibcon#read 5, iclass 7, count 2 2006.201.04:49:54.41#ibcon#about to read 6, iclass 7, count 2 2006.201.04:49:54.41#ibcon#read 6, iclass 7, count 2 2006.201.04:49:54.41#ibcon#end of sib2, iclass 7, count 2 2006.201.04:49:54.41#ibcon#*mode == 0, iclass 7, count 2 2006.201.04:49:54.41#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.04:49:54.41#ibcon#[27=AT02-05\r\n] 2006.201.04:49:54.41#ibcon#*before write, iclass 7, count 2 2006.201.04:49:54.41#ibcon#enter sib2, iclass 7, count 2 2006.201.04:49:54.41#ibcon#flushed, iclass 7, count 2 2006.201.04:49:54.41#ibcon#about to write, iclass 7, count 2 2006.201.04:49:54.41#ibcon#wrote, iclass 7, count 2 2006.201.04:49:54.41#ibcon#about to read 3, iclass 7, count 2 2006.201.04:49:54.44#ibcon#read 3, iclass 7, count 2 2006.201.04:49:54.44#ibcon#about to read 4, iclass 7, count 2 2006.201.04:49:54.44#ibcon#read 4, iclass 7, count 2 2006.201.04:49:54.44#ibcon#about to read 5, iclass 7, count 2 2006.201.04:49:54.44#ibcon#read 5, iclass 7, count 2 2006.201.04:49:54.44#ibcon#about to read 6, iclass 7, count 2 2006.201.04:49:54.44#ibcon#read 6, iclass 7, count 2 2006.201.04:49:54.44#ibcon#end of sib2, iclass 7, count 2 2006.201.04:49:54.44#ibcon#*after write, iclass 7, count 2 2006.201.04:49:54.44#ibcon#*before return 0, iclass 7, count 2 2006.201.04:49:54.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:54.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.04:49:54.54#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.04:49:54.54#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:54.54#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:54.66#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:54.66#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:54.66#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:49:54.66#ibcon#first serial, iclass 7, count 0 2006.201.04:49:54.66#ibcon#enter sib2, iclass 7, count 0 2006.201.04:49:54.66#ibcon#flushed, iclass 7, count 0 2006.201.04:49:54.66#ibcon#about to write, iclass 7, count 0 2006.201.04:49:54.66#ibcon#wrote, iclass 7, count 0 2006.201.04:49:54.66#ibcon#about to read 3, iclass 7, count 0 2006.201.04:49:54.68#ibcon#read 3, iclass 7, count 0 2006.201.04:49:54.68#ibcon#about to read 4, iclass 7, count 0 2006.201.04:49:54.68#ibcon#read 4, iclass 7, count 0 2006.201.04:49:54.68#ibcon#about to read 5, iclass 7, count 0 2006.201.04:49:54.68#ibcon#read 5, iclass 7, count 0 2006.201.04:49:54.68#ibcon#about to read 6, iclass 7, count 0 2006.201.04:49:54.68#ibcon#read 6, iclass 7, count 0 2006.201.04:49:54.68#ibcon#end of sib2, iclass 7, count 0 2006.201.04:49:54.68#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:49:54.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:49:54.68#ibcon#[27=USB\r\n] 2006.201.04:49:54.68#ibcon#*before write, iclass 7, count 0 2006.201.04:49:54.68#ibcon#enter sib2, iclass 7, count 0 2006.201.04:49:54.68#ibcon#flushed, iclass 7, count 0 2006.201.04:49:54.68#ibcon#about to write, iclass 7, count 0 2006.201.04:49:54.68#ibcon#wrote, iclass 7, count 0 2006.201.04:49:54.68#ibcon#about to read 3, iclass 7, count 0 2006.201.04:49:54.71#ibcon#read 3, iclass 7, count 0 2006.201.04:49:54.71#ibcon#about to read 4, iclass 7, count 0 2006.201.04:49:54.71#ibcon#read 4, iclass 7, count 0 2006.201.04:49:54.71#ibcon#about to read 5, iclass 7, count 0 2006.201.04:49:54.71#ibcon#read 5, iclass 7, count 0 2006.201.04:49:54.71#ibcon#about to read 6, iclass 7, count 0 2006.201.04:49:54.71#ibcon#read 6, iclass 7, count 0 2006.201.04:49:54.71#ibcon#end of sib2, iclass 7, count 0 2006.201.04:49:54.71#ibcon#*after write, iclass 7, count 0 2006.201.04:49:54.71#ibcon#*before return 0, iclass 7, count 0 2006.201.04:49:54.71#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:54.71#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.04:49:54.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:49:54.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:49:54.71$vck44/vblo=3,649.99 2006.201.04:49:54.71#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.04:49:54.71#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.04:49:54.71#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:54.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:54.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:54.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:54.71#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:49:54.71#ibcon#first serial, iclass 11, count 0 2006.201.04:49:54.71#ibcon#enter sib2, iclass 11, count 0 2006.201.04:49:54.71#ibcon#flushed, iclass 11, count 0 2006.201.04:49:54.71#ibcon#about to write, iclass 11, count 0 2006.201.04:49:54.71#ibcon#wrote, iclass 11, count 0 2006.201.04:49:54.71#ibcon#about to read 3, iclass 11, count 0 2006.201.04:49:54.73#ibcon#read 3, iclass 11, count 0 2006.201.04:49:54.73#ibcon#about to read 4, iclass 11, count 0 2006.201.04:49:54.73#ibcon#read 4, iclass 11, count 0 2006.201.04:49:54.73#ibcon#about to read 5, iclass 11, count 0 2006.201.04:49:54.73#ibcon#read 5, iclass 11, count 0 2006.201.04:49:54.73#ibcon#about to read 6, iclass 11, count 0 2006.201.04:49:54.73#ibcon#read 6, iclass 11, count 0 2006.201.04:49:54.73#ibcon#end of sib2, iclass 11, count 0 2006.201.04:49:54.73#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:49:54.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:49:54.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:49:54.73#ibcon#*before write, iclass 11, count 0 2006.201.04:49:54.73#ibcon#enter sib2, iclass 11, count 0 2006.201.04:49:54.73#ibcon#flushed, iclass 11, count 0 2006.201.04:49:54.73#ibcon#about to write, iclass 11, count 0 2006.201.04:49:54.73#ibcon#wrote, iclass 11, count 0 2006.201.04:49:54.73#ibcon#about to read 3, iclass 11, count 0 2006.201.04:49:54.77#ibcon#read 3, iclass 11, count 0 2006.201.04:49:54.77#ibcon#about to read 4, iclass 11, count 0 2006.201.04:49:54.77#ibcon#read 4, iclass 11, count 0 2006.201.04:49:54.77#ibcon#about to read 5, iclass 11, count 0 2006.201.04:49:54.77#ibcon#read 5, iclass 11, count 0 2006.201.04:49:54.77#ibcon#about to read 6, iclass 11, count 0 2006.201.04:49:54.77#ibcon#read 6, iclass 11, count 0 2006.201.04:49:54.77#ibcon#end of sib2, iclass 11, count 0 2006.201.04:49:54.77#ibcon#*after write, iclass 11, count 0 2006.201.04:49:54.77#ibcon#*before return 0, iclass 11, count 0 2006.201.04:49:54.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:54.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.04:49:54.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:49:54.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:49:54.77$vck44/vb=3,4 2006.201.04:49:54.77#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.04:49:54.77#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.04:49:54.77#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:54.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:54.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:54.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:54.83#ibcon#enter wrdev, iclass 13, count 2 2006.201.04:49:54.83#ibcon#first serial, iclass 13, count 2 2006.201.04:49:54.83#ibcon#enter sib2, iclass 13, count 2 2006.201.04:49:54.83#ibcon#flushed, iclass 13, count 2 2006.201.04:49:54.83#ibcon#about to write, iclass 13, count 2 2006.201.04:49:54.83#ibcon#wrote, iclass 13, count 2 2006.201.04:49:54.83#ibcon#about to read 3, iclass 13, count 2 2006.201.04:49:54.85#ibcon#read 3, iclass 13, count 2 2006.201.04:49:54.85#ibcon#about to read 4, iclass 13, count 2 2006.201.04:49:54.85#ibcon#read 4, iclass 13, count 2 2006.201.04:49:54.85#ibcon#about to read 5, iclass 13, count 2 2006.201.04:49:54.85#ibcon#read 5, iclass 13, count 2 2006.201.04:49:54.85#ibcon#about to read 6, iclass 13, count 2 2006.201.04:49:54.85#ibcon#read 6, iclass 13, count 2 2006.201.04:49:54.85#ibcon#end of sib2, iclass 13, count 2 2006.201.04:49:54.85#ibcon#*mode == 0, iclass 13, count 2 2006.201.04:49:54.85#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.04:49:54.85#ibcon#[27=AT03-04\r\n] 2006.201.04:49:54.85#ibcon#*before write, iclass 13, count 2 2006.201.04:49:54.85#ibcon#enter sib2, iclass 13, count 2 2006.201.04:49:54.85#ibcon#flushed, iclass 13, count 2 2006.201.04:49:54.85#ibcon#about to write, iclass 13, count 2 2006.201.04:49:54.85#ibcon#wrote, iclass 13, count 2 2006.201.04:49:54.85#ibcon#about to read 3, iclass 13, count 2 2006.201.04:49:54.88#ibcon#read 3, iclass 13, count 2 2006.201.04:49:54.88#ibcon#about to read 4, iclass 13, count 2 2006.201.04:49:54.88#ibcon#read 4, iclass 13, count 2 2006.201.04:49:54.88#ibcon#about to read 5, iclass 13, count 2 2006.201.04:49:54.88#ibcon#read 5, iclass 13, count 2 2006.201.04:49:54.88#ibcon#about to read 6, iclass 13, count 2 2006.201.04:49:54.88#ibcon#read 6, iclass 13, count 2 2006.201.04:49:54.88#ibcon#end of sib2, iclass 13, count 2 2006.201.04:49:54.88#ibcon#*after write, iclass 13, count 2 2006.201.04:49:54.88#ibcon#*before return 0, iclass 13, count 2 2006.201.04:49:54.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:54.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.04:49:54.88#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.04:49:54.88#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:54.88#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:55.00#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:55.00#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:55.00#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:49:55.00#ibcon#first serial, iclass 13, count 0 2006.201.04:49:55.00#ibcon#enter sib2, iclass 13, count 0 2006.201.04:49:55.00#ibcon#flushed, iclass 13, count 0 2006.201.04:49:55.00#ibcon#about to write, iclass 13, count 0 2006.201.04:49:55.00#ibcon#wrote, iclass 13, count 0 2006.201.04:49:55.00#ibcon#about to read 3, iclass 13, count 0 2006.201.04:49:55.02#ibcon#read 3, iclass 13, count 0 2006.201.04:49:55.02#ibcon#about to read 4, iclass 13, count 0 2006.201.04:49:55.02#ibcon#read 4, iclass 13, count 0 2006.201.04:49:55.02#ibcon#about to read 5, iclass 13, count 0 2006.201.04:49:55.02#ibcon#read 5, iclass 13, count 0 2006.201.04:49:55.02#ibcon#about to read 6, iclass 13, count 0 2006.201.04:49:55.02#ibcon#read 6, iclass 13, count 0 2006.201.04:49:55.02#ibcon#end of sib2, iclass 13, count 0 2006.201.04:49:55.02#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:49:55.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:49:55.02#ibcon#[27=USB\r\n] 2006.201.04:49:55.02#ibcon#*before write, iclass 13, count 0 2006.201.04:49:55.02#ibcon#enter sib2, iclass 13, count 0 2006.201.04:49:55.02#ibcon#flushed, iclass 13, count 0 2006.201.04:49:55.02#ibcon#about to write, iclass 13, count 0 2006.201.04:49:55.02#ibcon#wrote, iclass 13, count 0 2006.201.04:49:55.02#ibcon#about to read 3, iclass 13, count 0 2006.201.04:49:55.05#ibcon#read 3, iclass 13, count 0 2006.201.04:49:55.05#ibcon#about to read 4, iclass 13, count 0 2006.201.04:49:55.05#ibcon#read 4, iclass 13, count 0 2006.201.04:49:55.05#ibcon#about to read 5, iclass 13, count 0 2006.201.04:49:55.05#ibcon#read 5, iclass 13, count 0 2006.201.04:49:55.05#ibcon#about to read 6, iclass 13, count 0 2006.201.04:49:55.05#ibcon#read 6, iclass 13, count 0 2006.201.04:49:55.05#ibcon#end of sib2, iclass 13, count 0 2006.201.04:49:55.05#ibcon#*after write, iclass 13, count 0 2006.201.04:49:55.05#ibcon#*before return 0, iclass 13, count 0 2006.201.04:49:55.05#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:55.05#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.04:49:55.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:49:55.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:49:55.05$vck44/vblo=4,679.99 2006.201.04:49:55.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.04:49:55.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.04:49:55.05#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:55.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:55.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:55.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:55.05#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:49:55.05#ibcon#first serial, iclass 15, count 0 2006.201.04:49:55.05#ibcon#enter sib2, iclass 15, count 0 2006.201.04:49:55.05#ibcon#flushed, iclass 15, count 0 2006.201.04:49:55.05#ibcon#about to write, iclass 15, count 0 2006.201.04:49:55.05#ibcon#wrote, iclass 15, count 0 2006.201.04:49:55.05#ibcon#about to read 3, iclass 15, count 0 2006.201.04:49:55.07#ibcon#read 3, iclass 15, count 0 2006.201.04:49:55.07#ibcon#about to read 4, iclass 15, count 0 2006.201.04:49:55.07#ibcon#read 4, iclass 15, count 0 2006.201.04:49:55.07#ibcon#about to read 5, iclass 15, count 0 2006.201.04:49:55.07#ibcon#read 5, iclass 15, count 0 2006.201.04:49:55.07#ibcon#about to read 6, iclass 15, count 0 2006.201.04:49:55.07#ibcon#read 6, iclass 15, count 0 2006.201.04:49:55.07#ibcon#end of sib2, iclass 15, count 0 2006.201.04:49:55.07#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:49:55.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:49:55.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:49:55.07#ibcon#*before write, iclass 15, count 0 2006.201.04:49:55.07#ibcon#enter sib2, iclass 15, count 0 2006.201.04:49:55.07#ibcon#flushed, iclass 15, count 0 2006.201.04:49:55.07#ibcon#about to write, iclass 15, count 0 2006.201.04:49:55.07#ibcon#wrote, iclass 15, count 0 2006.201.04:49:55.07#ibcon#about to read 3, iclass 15, count 0 2006.201.04:49:55.11#ibcon#read 3, iclass 15, count 0 2006.201.04:49:55.11#ibcon#about to read 4, iclass 15, count 0 2006.201.04:49:55.11#ibcon#read 4, iclass 15, count 0 2006.201.04:49:55.11#ibcon#about to read 5, iclass 15, count 0 2006.201.04:49:55.11#ibcon#read 5, iclass 15, count 0 2006.201.04:49:55.11#ibcon#about to read 6, iclass 15, count 0 2006.201.04:49:55.11#ibcon#read 6, iclass 15, count 0 2006.201.04:49:55.11#ibcon#end of sib2, iclass 15, count 0 2006.201.04:49:55.11#ibcon#*after write, iclass 15, count 0 2006.201.04:49:55.11#ibcon#*before return 0, iclass 15, count 0 2006.201.04:49:55.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:55.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.04:49:55.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:49:55.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:49:55.11$vck44/vb=4,5 2006.201.04:49:55.11#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.04:49:55.11#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.04:49:55.11#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:55.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:55.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:55.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:55.17#ibcon#enter wrdev, iclass 17, count 2 2006.201.04:49:55.17#ibcon#first serial, iclass 17, count 2 2006.201.04:49:55.17#ibcon#enter sib2, iclass 17, count 2 2006.201.04:49:55.17#ibcon#flushed, iclass 17, count 2 2006.201.04:49:55.17#ibcon#about to write, iclass 17, count 2 2006.201.04:49:55.17#ibcon#wrote, iclass 17, count 2 2006.201.04:49:55.17#ibcon#about to read 3, iclass 17, count 2 2006.201.04:49:55.19#ibcon#read 3, iclass 17, count 2 2006.201.04:49:55.19#ibcon#about to read 4, iclass 17, count 2 2006.201.04:49:55.19#ibcon#read 4, iclass 17, count 2 2006.201.04:49:55.19#ibcon#about to read 5, iclass 17, count 2 2006.201.04:49:55.19#ibcon#read 5, iclass 17, count 2 2006.201.04:49:55.19#ibcon#about to read 6, iclass 17, count 2 2006.201.04:49:55.19#ibcon#read 6, iclass 17, count 2 2006.201.04:49:55.19#ibcon#end of sib2, iclass 17, count 2 2006.201.04:49:55.19#ibcon#*mode == 0, iclass 17, count 2 2006.201.04:49:55.19#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.04:49:55.19#ibcon#[27=AT04-05\r\n] 2006.201.04:49:55.19#ibcon#*before write, iclass 17, count 2 2006.201.04:49:55.19#ibcon#enter sib2, iclass 17, count 2 2006.201.04:49:55.19#ibcon#flushed, iclass 17, count 2 2006.201.04:49:55.19#ibcon#about to write, iclass 17, count 2 2006.201.04:49:55.19#ibcon#wrote, iclass 17, count 2 2006.201.04:49:55.19#ibcon#about to read 3, iclass 17, count 2 2006.201.04:49:55.22#ibcon#read 3, iclass 17, count 2 2006.201.04:49:55.22#ibcon#about to read 4, iclass 17, count 2 2006.201.04:49:55.22#ibcon#read 4, iclass 17, count 2 2006.201.04:49:55.22#ibcon#about to read 5, iclass 17, count 2 2006.201.04:49:55.22#ibcon#read 5, iclass 17, count 2 2006.201.04:49:55.22#ibcon#about to read 6, iclass 17, count 2 2006.201.04:49:55.22#ibcon#read 6, iclass 17, count 2 2006.201.04:49:55.22#ibcon#end of sib2, iclass 17, count 2 2006.201.04:49:55.22#ibcon#*after write, iclass 17, count 2 2006.201.04:49:55.22#ibcon#*before return 0, iclass 17, count 2 2006.201.04:49:55.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:55.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.04:49:55.22#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.04:49:55.22#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:55.22#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:55.34#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:55.34#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:55.34#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:49:55.34#ibcon#first serial, iclass 17, count 0 2006.201.04:49:55.34#ibcon#enter sib2, iclass 17, count 0 2006.201.04:49:55.34#ibcon#flushed, iclass 17, count 0 2006.201.04:49:55.34#ibcon#about to write, iclass 17, count 0 2006.201.04:49:55.34#ibcon#wrote, iclass 17, count 0 2006.201.04:49:55.34#ibcon#about to read 3, iclass 17, count 0 2006.201.04:49:55.36#ibcon#read 3, iclass 17, count 0 2006.201.04:49:55.36#ibcon#about to read 4, iclass 17, count 0 2006.201.04:49:55.36#ibcon#read 4, iclass 17, count 0 2006.201.04:49:55.36#ibcon#about to read 5, iclass 17, count 0 2006.201.04:49:55.36#ibcon#read 5, iclass 17, count 0 2006.201.04:49:55.36#ibcon#about to read 6, iclass 17, count 0 2006.201.04:49:55.36#ibcon#read 6, iclass 17, count 0 2006.201.04:49:55.36#ibcon#end of sib2, iclass 17, count 0 2006.201.04:49:55.36#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:49:55.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:49:55.36#ibcon#[27=USB\r\n] 2006.201.04:49:55.36#ibcon#*before write, iclass 17, count 0 2006.201.04:49:55.36#ibcon#enter sib2, iclass 17, count 0 2006.201.04:49:55.36#ibcon#flushed, iclass 17, count 0 2006.201.04:49:55.36#ibcon#about to write, iclass 17, count 0 2006.201.04:49:55.36#ibcon#wrote, iclass 17, count 0 2006.201.04:49:55.36#ibcon#about to read 3, iclass 17, count 0 2006.201.04:49:55.39#ibcon#read 3, iclass 17, count 0 2006.201.04:49:55.39#ibcon#about to read 4, iclass 17, count 0 2006.201.04:49:55.39#ibcon#read 4, iclass 17, count 0 2006.201.04:49:55.39#ibcon#about to read 5, iclass 17, count 0 2006.201.04:49:55.39#ibcon#read 5, iclass 17, count 0 2006.201.04:49:55.39#ibcon#about to read 6, iclass 17, count 0 2006.201.04:49:55.39#ibcon#read 6, iclass 17, count 0 2006.201.04:49:55.39#ibcon#end of sib2, iclass 17, count 0 2006.201.04:49:55.39#ibcon#*after write, iclass 17, count 0 2006.201.04:49:55.39#ibcon#*before return 0, iclass 17, count 0 2006.201.04:49:55.39#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:55.39#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.04:49:55.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:49:55.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:49:55.39$vck44/vblo=5,709.99 2006.201.04:49:55.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.04:49:55.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.04:49:55.39#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:55.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:55.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:55.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:55.39#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:49:55.39#ibcon#first serial, iclass 19, count 0 2006.201.04:49:55.39#ibcon#enter sib2, iclass 19, count 0 2006.201.04:49:55.39#ibcon#flushed, iclass 19, count 0 2006.201.04:49:55.39#ibcon#about to write, iclass 19, count 0 2006.201.04:49:55.39#ibcon#wrote, iclass 19, count 0 2006.201.04:49:55.39#ibcon#about to read 3, iclass 19, count 0 2006.201.04:49:55.41#ibcon#read 3, iclass 19, count 0 2006.201.04:49:55.41#ibcon#about to read 4, iclass 19, count 0 2006.201.04:49:55.41#ibcon#read 4, iclass 19, count 0 2006.201.04:49:55.41#ibcon#about to read 5, iclass 19, count 0 2006.201.04:49:55.41#ibcon#read 5, iclass 19, count 0 2006.201.04:49:55.41#ibcon#about to read 6, iclass 19, count 0 2006.201.04:49:55.41#ibcon#read 6, iclass 19, count 0 2006.201.04:49:55.41#ibcon#end of sib2, iclass 19, count 0 2006.201.04:49:55.41#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:49:55.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:49:55.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:49:55.41#ibcon#*before write, iclass 19, count 0 2006.201.04:49:55.41#ibcon#enter sib2, iclass 19, count 0 2006.201.04:49:55.41#ibcon#flushed, iclass 19, count 0 2006.201.04:49:55.41#ibcon#about to write, iclass 19, count 0 2006.201.04:49:55.41#ibcon#wrote, iclass 19, count 0 2006.201.04:49:55.41#ibcon#about to read 3, iclass 19, count 0 2006.201.04:49:55.45#ibcon#read 3, iclass 19, count 0 2006.201.04:49:55.45#ibcon#about to read 4, iclass 19, count 0 2006.201.04:49:55.45#ibcon#read 4, iclass 19, count 0 2006.201.04:49:55.45#ibcon#about to read 5, iclass 19, count 0 2006.201.04:49:55.45#ibcon#read 5, iclass 19, count 0 2006.201.04:49:55.45#ibcon#about to read 6, iclass 19, count 0 2006.201.04:49:55.45#ibcon#read 6, iclass 19, count 0 2006.201.04:49:55.45#ibcon#end of sib2, iclass 19, count 0 2006.201.04:49:55.45#ibcon#*after write, iclass 19, count 0 2006.201.04:49:55.45#ibcon#*before return 0, iclass 19, count 0 2006.201.04:49:55.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:55.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.04:49:55.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:49:55.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:49:55.45$vck44/vb=5,4 2006.201.04:49:55.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.04:49:55.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.04:49:55.45#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:55.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:55.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:55.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:55.51#ibcon#enter wrdev, iclass 21, count 2 2006.201.04:49:55.51#ibcon#first serial, iclass 21, count 2 2006.201.04:49:55.51#ibcon#enter sib2, iclass 21, count 2 2006.201.04:49:55.51#ibcon#flushed, iclass 21, count 2 2006.201.04:49:55.51#ibcon#about to write, iclass 21, count 2 2006.201.04:49:55.51#ibcon#wrote, iclass 21, count 2 2006.201.04:49:55.51#ibcon#about to read 3, iclass 21, count 2 2006.201.04:49:55.53#ibcon#read 3, iclass 21, count 2 2006.201.04:49:55.53#ibcon#about to read 4, iclass 21, count 2 2006.201.04:49:55.53#ibcon#read 4, iclass 21, count 2 2006.201.04:49:55.53#ibcon#about to read 5, iclass 21, count 2 2006.201.04:49:55.53#ibcon#read 5, iclass 21, count 2 2006.201.04:49:55.53#ibcon#about to read 6, iclass 21, count 2 2006.201.04:49:55.53#ibcon#read 6, iclass 21, count 2 2006.201.04:49:55.53#ibcon#end of sib2, iclass 21, count 2 2006.201.04:49:55.53#ibcon#*mode == 0, iclass 21, count 2 2006.201.04:49:55.53#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.04:49:55.53#ibcon#[27=AT05-04\r\n] 2006.201.04:49:55.53#ibcon#*before write, iclass 21, count 2 2006.201.04:49:55.53#ibcon#enter sib2, iclass 21, count 2 2006.201.04:49:55.53#ibcon#flushed, iclass 21, count 2 2006.201.04:49:55.53#ibcon#about to write, iclass 21, count 2 2006.201.04:49:55.53#ibcon#wrote, iclass 21, count 2 2006.201.04:49:55.53#ibcon#about to read 3, iclass 21, count 2 2006.201.04:49:55.56#ibcon#read 3, iclass 21, count 2 2006.201.04:49:55.56#ibcon#about to read 4, iclass 21, count 2 2006.201.04:49:55.62#ibcon#read 4, iclass 21, count 2 2006.201.04:49:55.62#ibcon#about to read 5, iclass 21, count 2 2006.201.04:49:55.62#ibcon#read 5, iclass 21, count 2 2006.201.04:49:55.62#ibcon#about to read 6, iclass 21, count 2 2006.201.04:49:55.62#ibcon#read 6, iclass 21, count 2 2006.201.04:49:55.62#ibcon#end of sib2, iclass 21, count 2 2006.201.04:49:55.62#ibcon#*after write, iclass 21, count 2 2006.201.04:49:55.62#ibcon#*before return 0, iclass 21, count 2 2006.201.04:49:55.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:55.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.04:49:55.62#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.04:49:55.62#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:55.62#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:55.74#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:55.74#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:55.74#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:49:55.74#ibcon#first serial, iclass 21, count 0 2006.201.04:49:55.74#ibcon#enter sib2, iclass 21, count 0 2006.201.04:49:55.74#ibcon#flushed, iclass 21, count 0 2006.201.04:49:55.74#ibcon#about to write, iclass 21, count 0 2006.201.04:49:55.74#ibcon#wrote, iclass 21, count 0 2006.201.04:49:55.74#ibcon#about to read 3, iclass 21, count 0 2006.201.04:49:55.76#ibcon#read 3, iclass 21, count 0 2006.201.04:49:55.76#ibcon#about to read 4, iclass 21, count 0 2006.201.04:49:55.76#ibcon#read 4, iclass 21, count 0 2006.201.04:49:55.76#ibcon#about to read 5, iclass 21, count 0 2006.201.04:49:55.76#ibcon#read 5, iclass 21, count 0 2006.201.04:49:55.76#ibcon#about to read 6, iclass 21, count 0 2006.201.04:49:55.76#ibcon#read 6, iclass 21, count 0 2006.201.04:49:55.76#ibcon#end of sib2, iclass 21, count 0 2006.201.04:49:55.76#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:49:55.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:49:55.76#ibcon#[27=USB\r\n] 2006.201.04:49:55.76#ibcon#*before write, iclass 21, count 0 2006.201.04:49:55.76#ibcon#enter sib2, iclass 21, count 0 2006.201.04:49:55.76#ibcon#flushed, iclass 21, count 0 2006.201.04:49:55.76#ibcon#about to write, iclass 21, count 0 2006.201.04:49:55.76#ibcon#wrote, iclass 21, count 0 2006.201.04:49:55.76#ibcon#about to read 3, iclass 21, count 0 2006.201.04:49:55.79#ibcon#read 3, iclass 21, count 0 2006.201.04:49:55.79#ibcon#about to read 4, iclass 21, count 0 2006.201.04:49:55.79#ibcon#read 4, iclass 21, count 0 2006.201.04:49:55.79#ibcon#about to read 5, iclass 21, count 0 2006.201.04:49:55.79#ibcon#read 5, iclass 21, count 0 2006.201.04:49:55.79#ibcon#about to read 6, iclass 21, count 0 2006.201.04:49:55.79#ibcon#read 6, iclass 21, count 0 2006.201.04:49:55.79#ibcon#end of sib2, iclass 21, count 0 2006.201.04:49:55.79#ibcon#*after write, iclass 21, count 0 2006.201.04:49:55.79#ibcon#*before return 0, iclass 21, count 0 2006.201.04:49:55.79#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:55.79#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.04:49:55.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:49:55.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:49:55.79$vck44/vblo=6,719.99 2006.201.04:49:55.79#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.04:49:55.79#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.04:49:55.79#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:55.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:55.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:55.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:55.79#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:49:55.79#ibcon#first serial, iclass 23, count 0 2006.201.04:49:55.79#ibcon#enter sib2, iclass 23, count 0 2006.201.04:49:55.79#ibcon#flushed, iclass 23, count 0 2006.201.04:49:55.79#ibcon#about to write, iclass 23, count 0 2006.201.04:49:55.79#ibcon#wrote, iclass 23, count 0 2006.201.04:49:55.79#ibcon#about to read 3, iclass 23, count 0 2006.201.04:49:55.81#ibcon#read 3, iclass 23, count 0 2006.201.04:49:55.81#ibcon#about to read 4, iclass 23, count 0 2006.201.04:49:55.81#ibcon#read 4, iclass 23, count 0 2006.201.04:49:55.81#ibcon#about to read 5, iclass 23, count 0 2006.201.04:49:55.81#ibcon#read 5, iclass 23, count 0 2006.201.04:49:55.81#ibcon#about to read 6, iclass 23, count 0 2006.201.04:49:55.81#ibcon#read 6, iclass 23, count 0 2006.201.04:49:55.81#ibcon#end of sib2, iclass 23, count 0 2006.201.04:49:55.81#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:49:55.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:49:55.81#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:49:55.81#ibcon#*before write, iclass 23, count 0 2006.201.04:49:55.81#ibcon#enter sib2, iclass 23, count 0 2006.201.04:49:55.81#ibcon#flushed, iclass 23, count 0 2006.201.04:49:55.81#ibcon#about to write, iclass 23, count 0 2006.201.04:49:55.81#ibcon#wrote, iclass 23, count 0 2006.201.04:49:55.81#ibcon#about to read 3, iclass 23, count 0 2006.201.04:49:55.85#ibcon#read 3, iclass 23, count 0 2006.201.04:49:55.85#ibcon#about to read 4, iclass 23, count 0 2006.201.04:49:55.85#ibcon#read 4, iclass 23, count 0 2006.201.04:49:55.85#ibcon#about to read 5, iclass 23, count 0 2006.201.04:49:55.85#ibcon#read 5, iclass 23, count 0 2006.201.04:49:55.85#ibcon#about to read 6, iclass 23, count 0 2006.201.04:49:55.85#ibcon#read 6, iclass 23, count 0 2006.201.04:49:55.85#ibcon#end of sib2, iclass 23, count 0 2006.201.04:49:55.85#ibcon#*after write, iclass 23, count 0 2006.201.04:49:55.85#ibcon#*before return 0, iclass 23, count 0 2006.201.04:49:55.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:55.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.04:49:55.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:49:55.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:49:55.85$vck44/vb=6,4 2006.201.04:49:55.85#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.04:49:55.85#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.04:49:55.85#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:55.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:55.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:55.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:55.91#ibcon#enter wrdev, iclass 25, count 2 2006.201.04:49:55.91#ibcon#first serial, iclass 25, count 2 2006.201.04:49:55.91#ibcon#enter sib2, iclass 25, count 2 2006.201.04:49:55.91#ibcon#flushed, iclass 25, count 2 2006.201.04:49:55.91#ibcon#about to write, iclass 25, count 2 2006.201.04:49:55.91#ibcon#wrote, iclass 25, count 2 2006.201.04:49:55.91#ibcon#about to read 3, iclass 25, count 2 2006.201.04:49:55.93#ibcon#read 3, iclass 25, count 2 2006.201.04:49:55.93#ibcon#about to read 4, iclass 25, count 2 2006.201.04:49:55.93#ibcon#read 4, iclass 25, count 2 2006.201.04:49:55.93#ibcon#about to read 5, iclass 25, count 2 2006.201.04:49:55.93#ibcon#read 5, iclass 25, count 2 2006.201.04:49:55.93#ibcon#about to read 6, iclass 25, count 2 2006.201.04:49:55.93#ibcon#read 6, iclass 25, count 2 2006.201.04:49:55.93#ibcon#end of sib2, iclass 25, count 2 2006.201.04:49:55.93#ibcon#*mode == 0, iclass 25, count 2 2006.201.04:49:55.93#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.04:49:55.93#ibcon#[27=AT06-04\r\n] 2006.201.04:49:55.93#ibcon#*before write, iclass 25, count 2 2006.201.04:49:55.93#ibcon#enter sib2, iclass 25, count 2 2006.201.04:49:55.93#ibcon#flushed, iclass 25, count 2 2006.201.04:49:55.93#ibcon#about to write, iclass 25, count 2 2006.201.04:49:55.93#ibcon#wrote, iclass 25, count 2 2006.201.04:49:55.93#ibcon#about to read 3, iclass 25, count 2 2006.201.04:49:55.96#ibcon#read 3, iclass 25, count 2 2006.201.04:49:55.96#ibcon#about to read 4, iclass 25, count 2 2006.201.04:49:55.96#ibcon#read 4, iclass 25, count 2 2006.201.04:49:55.96#ibcon#about to read 5, iclass 25, count 2 2006.201.04:49:55.96#ibcon#read 5, iclass 25, count 2 2006.201.04:49:55.96#ibcon#about to read 6, iclass 25, count 2 2006.201.04:49:55.96#ibcon#read 6, iclass 25, count 2 2006.201.04:49:55.96#ibcon#end of sib2, iclass 25, count 2 2006.201.04:49:55.96#ibcon#*after write, iclass 25, count 2 2006.201.04:49:55.96#ibcon#*before return 0, iclass 25, count 2 2006.201.04:49:55.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:55.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.04:49:55.96#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.04:49:55.96#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:55.96#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:56.08#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:56.08#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:56.08#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:49:56.08#ibcon#first serial, iclass 25, count 0 2006.201.04:49:56.08#ibcon#enter sib2, iclass 25, count 0 2006.201.04:49:56.08#ibcon#flushed, iclass 25, count 0 2006.201.04:49:56.08#ibcon#about to write, iclass 25, count 0 2006.201.04:49:56.08#ibcon#wrote, iclass 25, count 0 2006.201.04:49:56.08#ibcon#about to read 3, iclass 25, count 0 2006.201.04:49:56.10#ibcon#read 3, iclass 25, count 0 2006.201.04:49:56.10#ibcon#about to read 4, iclass 25, count 0 2006.201.04:49:56.10#ibcon#read 4, iclass 25, count 0 2006.201.04:49:56.10#ibcon#about to read 5, iclass 25, count 0 2006.201.04:49:56.10#ibcon#read 5, iclass 25, count 0 2006.201.04:49:56.10#ibcon#about to read 6, iclass 25, count 0 2006.201.04:49:56.10#ibcon#read 6, iclass 25, count 0 2006.201.04:49:56.10#ibcon#end of sib2, iclass 25, count 0 2006.201.04:49:56.10#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:49:56.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:49:56.10#ibcon#[27=USB\r\n] 2006.201.04:49:56.10#ibcon#*before write, iclass 25, count 0 2006.201.04:49:56.10#ibcon#enter sib2, iclass 25, count 0 2006.201.04:49:56.10#ibcon#flushed, iclass 25, count 0 2006.201.04:49:56.10#ibcon#about to write, iclass 25, count 0 2006.201.04:49:56.10#ibcon#wrote, iclass 25, count 0 2006.201.04:49:56.10#ibcon#about to read 3, iclass 25, count 0 2006.201.04:49:56.13#ibcon#read 3, iclass 25, count 0 2006.201.04:49:56.13#ibcon#about to read 4, iclass 25, count 0 2006.201.04:49:56.13#ibcon#read 4, iclass 25, count 0 2006.201.04:49:56.13#ibcon#about to read 5, iclass 25, count 0 2006.201.04:49:56.13#ibcon#read 5, iclass 25, count 0 2006.201.04:49:56.13#ibcon#about to read 6, iclass 25, count 0 2006.201.04:49:56.13#ibcon#read 6, iclass 25, count 0 2006.201.04:49:56.13#ibcon#end of sib2, iclass 25, count 0 2006.201.04:49:56.13#ibcon#*after write, iclass 25, count 0 2006.201.04:49:56.13#ibcon#*before return 0, iclass 25, count 0 2006.201.04:49:56.13#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:56.13#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.04:49:56.13#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:49:56.13#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:49:56.13$vck44/vblo=7,734.99 2006.201.04:49:56.13#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.04:49:56.13#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.04:49:56.13#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:56.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:56.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:56.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:56.13#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:49:56.13#ibcon#first serial, iclass 27, count 0 2006.201.04:49:56.13#ibcon#enter sib2, iclass 27, count 0 2006.201.04:49:56.13#ibcon#flushed, iclass 27, count 0 2006.201.04:49:56.13#ibcon#about to write, iclass 27, count 0 2006.201.04:49:56.13#ibcon#wrote, iclass 27, count 0 2006.201.04:49:56.13#ibcon#about to read 3, iclass 27, count 0 2006.201.04:49:56.15#ibcon#read 3, iclass 27, count 0 2006.201.04:49:56.15#ibcon#about to read 4, iclass 27, count 0 2006.201.04:49:56.15#ibcon#read 4, iclass 27, count 0 2006.201.04:49:56.15#ibcon#about to read 5, iclass 27, count 0 2006.201.04:49:56.15#ibcon#read 5, iclass 27, count 0 2006.201.04:49:56.15#ibcon#about to read 6, iclass 27, count 0 2006.201.04:49:56.15#ibcon#read 6, iclass 27, count 0 2006.201.04:49:56.15#ibcon#end of sib2, iclass 27, count 0 2006.201.04:49:56.15#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:49:56.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:49:56.15#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:49:56.15#ibcon#*before write, iclass 27, count 0 2006.201.04:49:56.15#ibcon#enter sib2, iclass 27, count 0 2006.201.04:49:56.15#ibcon#flushed, iclass 27, count 0 2006.201.04:49:56.15#ibcon#about to write, iclass 27, count 0 2006.201.04:49:56.15#ibcon#wrote, iclass 27, count 0 2006.201.04:49:56.15#ibcon#about to read 3, iclass 27, count 0 2006.201.04:49:56.19#ibcon#read 3, iclass 27, count 0 2006.201.04:49:56.19#ibcon#about to read 4, iclass 27, count 0 2006.201.04:49:56.19#ibcon#read 4, iclass 27, count 0 2006.201.04:49:56.19#ibcon#about to read 5, iclass 27, count 0 2006.201.04:49:56.19#ibcon#read 5, iclass 27, count 0 2006.201.04:49:56.19#ibcon#about to read 6, iclass 27, count 0 2006.201.04:49:56.19#ibcon#read 6, iclass 27, count 0 2006.201.04:49:56.19#ibcon#end of sib2, iclass 27, count 0 2006.201.04:49:56.19#ibcon#*after write, iclass 27, count 0 2006.201.04:49:56.19#ibcon#*before return 0, iclass 27, count 0 2006.201.04:49:56.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:56.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.04:49:56.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:49:56.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:49:56.19$vck44/vb=7,4 2006.201.04:49:56.19#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.04:49:56.19#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.04:49:56.19#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:56.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:56.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:56.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:56.25#ibcon#enter wrdev, iclass 29, count 2 2006.201.04:49:56.25#ibcon#first serial, iclass 29, count 2 2006.201.04:49:56.25#ibcon#enter sib2, iclass 29, count 2 2006.201.04:49:56.25#ibcon#flushed, iclass 29, count 2 2006.201.04:49:56.25#ibcon#about to write, iclass 29, count 2 2006.201.04:49:56.25#ibcon#wrote, iclass 29, count 2 2006.201.04:49:56.25#ibcon#about to read 3, iclass 29, count 2 2006.201.04:49:56.27#ibcon#read 3, iclass 29, count 2 2006.201.04:49:56.27#ibcon#about to read 4, iclass 29, count 2 2006.201.04:49:56.27#ibcon#read 4, iclass 29, count 2 2006.201.04:49:56.27#ibcon#about to read 5, iclass 29, count 2 2006.201.04:49:56.27#ibcon#read 5, iclass 29, count 2 2006.201.04:49:56.27#ibcon#about to read 6, iclass 29, count 2 2006.201.04:49:56.27#ibcon#read 6, iclass 29, count 2 2006.201.04:49:56.27#ibcon#end of sib2, iclass 29, count 2 2006.201.04:49:56.27#ibcon#*mode == 0, iclass 29, count 2 2006.201.04:49:56.27#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.04:49:56.27#ibcon#[27=AT07-04\r\n] 2006.201.04:49:56.27#ibcon#*before write, iclass 29, count 2 2006.201.04:49:56.27#ibcon#enter sib2, iclass 29, count 2 2006.201.04:49:56.27#ibcon#flushed, iclass 29, count 2 2006.201.04:49:56.27#ibcon#about to write, iclass 29, count 2 2006.201.04:49:56.27#ibcon#wrote, iclass 29, count 2 2006.201.04:49:56.27#ibcon#about to read 3, iclass 29, count 2 2006.201.04:49:56.30#ibcon#read 3, iclass 29, count 2 2006.201.04:49:56.30#ibcon#about to read 4, iclass 29, count 2 2006.201.04:49:56.30#ibcon#read 4, iclass 29, count 2 2006.201.04:49:56.30#ibcon#about to read 5, iclass 29, count 2 2006.201.04:49:56.30#ibcon#read 5, iclass 29, count 2 2006.201.04:49:56.30#ibcon#about to read 6, iclass 29, count 2 2006.201.04:49:56.30#ibcon#read 6, iclass 29, count 2 2006.201.04:49:56.30#ibcon#end of sib2, iclass 29, count 2 2006.201.04:49:56.30#ibcon#*after write, iclass 29, count 2 2006.201.04:49:56.30#ibcon#*before return 0, iclass 29, count 2 2006.201.04:49:56.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:56.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.04:49:56.30#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.04:49:56.30#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:56.30#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:56.42#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:56.42#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:56.42#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:49:56.42#ibcon#first serial, iclass 29, count 0 2006.201.04:49:56.42#ibcon#enter sib2, iclass 29, count 0 2006.201.04:49:56.42#ibcon#flushed, iclass 29, count 0 2006.201.04:49:56.42#ibcon#about to write, iclass 29, count 0 2006.201.04:49:56.42#ibcon#wrote, iclass 29, count 0 2006.201.04:49:56.42#ibcon#about to read 3, iclass 29, count 0 2006.201.04:49:56.44#ibcon#read 3, iclass 29, count 0 2006.201.04:49:56.44#ibcon#about to read 4, iclass 29, count 0 2006.201.04:49:56.44#ibcon#read 4, iclass 29, count 0 2006.201.04:49:56.44#ibcon#about to read 5, iclass 29, count 0 2006.201.04:49:56.44#ibcon#read 5, iclass 29, count 0 2006.201.04:49:56.44#ibcon#about to read 6, iclass 29, count 0 2006.201.04:49:56.44#ibcon#read 6, iclass 29, count 0 2006.201.04:49:56.44#ibcon#end of sib2, iclass 29, count 0 2006.201.04:49:56.44#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:49:56.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:49:56.44#ibcon#[27=USB\r\n] 2006.201.04:49:56.44#ibcon#*before write, iclass 29, count 0 2006.201.04:49:56.44#ibcon#enter sib2, iclass 29, count 0 2006.201.04:49:56.44#ibcon#flushed, iclass 29, count 0 2006.201.04:49:56.44#ibcon#about to write, iclass 29, count 0 2006.201.04:49:56.44#ibcon#wrote, iclass 29, count 0 2006.201.04:49:56.44#ibcon#about to read 3, iclass 29, count 0 2006.201.04:49:56.47#ibcon#read 3, iclass 29, count 0 2006.201.04:49:56.47#ibcon#about to read 4, iclass 29, count 0 2006.201.04:49:56.47#ibcon#read 4, iclass 29, count 0 2006.201.04:49:56.47#ibcon#about to read 5, iclass 29, count 0 2006.201.04:49:56.47#ibcon#read 5, iclass 29, count 0 2006.201.04:49:56.47#ibcon#about to read 6, iclass 29, count 0 2006.201.04:49:56.47#ibcon#read 6, iclass 29, count 0 2006.201.04:49:56.47#ibcon#end of sib2, iclass 29, count 0 2006.201.04:49:56.47#ibcon#*after write, iclass 29, count 0 2006.201.04:49:56.47#ibcon#*before return 0, iclass 29, count 0 2006.201.04:49:56.47#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:56.47#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.04:49:56.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:49:56.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:49:56.47$vck44/vblo=8,744.99 2006.201.04:49:56.47#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.04:49:56.47#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.04:49:56.47#ibcon#ireg 17 cls_cnt 0 2006.201.04:49:56.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:56.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:56.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:56.47#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:49:56.47#ibcon#first serial, iclass 31, count 0 2006.201.04:49:56.47#ibcon#enter sib2, iclass 31, count 0 2006.201.04:49:56.47#ibcon#flushed, iclass 31, count 0 2006.201.04:49:56.47#ibcon#about to write, iclass 31, count 0 2006.201.04:49:56.47#ibcon#wrote, iclass 31, count 0 2006.201.04:49:56.47#ibcon#about to read 3, iclass 31, count 0 2006.201.04:49:56.49#ibcon#read 3, iclass 31, count 0 2006.201.04:49:56.49#ibcon#about to read 4, iclass 31, count 0 2006.201.04:49:56.49#ibcon#read 4, iclass 31, count 0 2006.201.04:49:56.49#ibcon#about to read 5, iclass 31, count 0 2006.201.04:49:56.49#ibcon#read 5, iclass 31, count 0 2006.201.04:49:56.49#ibcon#about to read 6, iclass 31, count 0 2006.201.04:49:56.49#ibcon#read 6, iclass 31, count 0 2006.201.04:49:56.49#ibcon#end of sib2, iclass 31, count 0 2006.201.04:49:56.49#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:49:56.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:49:56.49#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:49:56.49#ibcon#*before write, iclass 31, count 0 2006.201.04:49:56.49#ibcon#enter sib2, iclass 31, count 0 2006.201.04:49:56.49#ibcon#flushed, iclass 31, count 0 2006.201.04:49:56.49#ibcon#about to write, iclass 31, count 0 2006.201.04:49:56.49#ibcon#wrote, iclass 31, count 0 2006.201.04:49:56.49#ibcon#about to read 3, iclass 31, count 0 2006.201.04:49:56.53#ibcon#read 3, iclass 31, count 0 2006.201.04:49:56.53#ibcon#about to read 4, iclass 31, count 0 2006.201.04:49:56.53#ibcon#read 4, iclass 31, count 0 2006.201.04:49:56.53#ibcon#about to read 5, iclass 31, count 0 2006.201.04:49:56.53#ibcon#read 5, iclass 31, count 0 2006.201.04:49:56.53#ibcon#about to read 6, iclass 31, count 0 2006.201.04:49:56.53#ibcon#read 6, iclass 31, count 0 2006.201.04:49:56.53#ibcon#end of sib2, iclass 31, count 0 2006.201.04:49:56.53#ibcon#*after write, iclass 31, count 0 2006.201.04:49:56.53#ibcon#*before return 0, iclass 31, count 0 2006.201.04:49:56.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:56.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:49:56.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:49:56.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:49:56.53$vck44/vb=8,4 2006.201.04:49:56.53#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.04:49:56.53#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.04:49:56.53#ibcon#ireg 11 cls_cnt 2 2006.201.04:49:56.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:56.58#abcon#<5=/04 2.6 5.0 22.97 891003.9\r\n> 2006.201.04:49:56.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:56.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:56.59#ibcon#enter wrdev, iclass 33, count 2 2006.201.04:49:56.59#ibcon#first serial, iclass 33, count 2 2006.201.04:49:56.59#ibcon#enter sib2, iclass 33, count 2 2006.201.04:49:56.59#ibcon#flushed, iclass 33, count 2 2006.201.04:49:56.59#ibcon#about to write, iclass 33, count 2 2006.201.04:49:56.59#ibcon#wrote, iclass 33, count 2 2006.201.04:49:56.59#ibcon#about to read 3, iclass 33, count 2 2006.201.04:49:56.60#abcon#{5=INTERFACE CLEAR} 2006.201.04:49:56.61#ibcon#read 3, iclass 33, count 2 2006.201.04:49:56.61#ibcon#about to read 4, iclass 33, count 2 2006.201.04:49:56.61#ibcon#read 4, iclass 33, count 2 2006.201.04:49:56.61#ibcon#about to read 5, iclass 33, count 2 2006.201.04:49:56.61#ibcon#read 5, iclass 33, count 2 2006.201.04:49:56.61#ibcon#about to read 6, iclass 33, count 2 2006.201.04:49:56.61#ibcon#read 6, iclass 33, count 2 2006.201.04:49:56.61#ibcon#end of sib2, iclass 33, count 2 2006.201.04:49:56.61#ibcon#*mode == 0, iclass 33, count 2 2006.201.04:49:56.61#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.04:49:56.61#ibcon#[27=AT08-04\r\n] 2006.201.04:49:56.61#ibcon#*before write, iclass 33, count 2 2006.201.04:49:56.61#ibcon#enter sib2, iclass 33, count 2 2006.201.04:49:56.61#ibcon#flushed, iclass 33, count 2 2006.201.04:49:56.61#ibcon#about to write, iclass 33, count 2 2006.201.04:49:56.61#ibcon#wrote, iclass 33, count 2 2006.201.04:49:56.61#ibcon#about to read 3, iclass 33, count 2 2006.201.04:49:56.64#ibcon#read 3, iclass 33, count 2 2006.201.04:49:56.64#ibcon#about to read 4, iclass 33, count 2 2006.201.04:49:56.64#ibcon#read 4, iclass 33, count 2 2006.201.04:49:56.64#ibcon#about to read 5, iclass 33, count 2 2006.201.04:49:56.64#ibcon#read 5, iclass 33, count 2 2006.201.04:49:56.64#ibcon#about to read 6, iclass 33, count 2 2006.201.04:49:56.64#ibcon#read 6, iclass 33, count 2 2006.201.04:49:56.68#ibcon#end of sib2, iclass 33, count 2 2006.201.04:49:56.68#ibcon#*after write, iclass 33, count 2 2006.201.04:49:56.68#ibcon#*before return 0, iclass 33, count 2 2006.201.04:49:56.66#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:49:56.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:56.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.04:49:56.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.04:49:56.68#ibcon#ireg 7 cls_cnt 0 2006.201.04:49:56.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:56.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:56.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:56.80#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:49:56.80#ibcon#first serial, iclass 33, count 0 2006.201.04:49:56.80#ibcon#enter sib2, iclass 33, count 0 2006.201.04:49:56.80#ibcon#flushed, iclass 33, count 0 2006.201.04:49:56.80#ibcon#about to write, iclass 33, count 0 2006.201.04:49:56.80#ibcon#wrote, iclass 33, count 0 2006.201.04:49:56.80#ibcon#about to read 3, iclass 33, count 0 2006.201.04:49:56.82#ibcon#read 3, iclass 33, count 0 2006.201.04:49:56.82#ibcon#about to read 4, iclass 33, count 0 2006.201.04:49:56.82#ibcon#read 4, iclass 33, count 0 2006.201.04:49:56.82#ibcon#about to read 5, iclass 33, count 0 2006.201.04:49:56.82#ibcon#read 5, iclass 33, count 0 2006.201.04:49:56.82#ibcon#about to read 6, iclass 33, count 0 2006.201.04:49:56.82#ibcon#read 6, iclass 33, count 0 2006.201.04:49:56.82#ibcon#end of sib2, iclass 33, count 0 2006.201.04:49:56.82#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:49:56.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:49:56.82#ibcon#[27=USB\r\n] 2006.201.04:49:56.82#ibcon#*before write, iclass 33, count 0 2006.201.04:49:56.82#ibcon#enter sib2, iclass 33, count 0 2006.201.04:49:56.82#ibcon#flushed, iclass 33, count 0 2006.201.04:49:56.82#ibcon#about to write, iclass 33, count 0 2006.201.04:49:56.82#ibcon#wrote, iclass 33, count 0 2006.201.04:49:56.82#ibcon#about to read 3, iclass 33, count 0 2006.201.04:49:56.85#ibcon#read 3, iclass 33, count 0 2006.201.04:49:56.85#ibcon#about to read 4, iclass 33, count 0 2006.201.04:49:56.85#ibcon#read 4, iclass 33, count 0 2006.201.04:49:56.85#ibcon#about to read 5, iclass 33, count 0 2006.201.04:49:56.85#ibcon#read 5, iclass 33, count 0 2006.201.04:49:56.85#ibcon#about to read 6, iclass 33, count 0 2006.201.04:49:56.85#ibcon#read 6, iclass 33, count 0 2006.201.04:49:56.85#ibcon#end of sib2, iclass 33, count 0 2006.201.04:49:56.85#ibcon#*after write, iclass 33, count 0 2006.201.04:49:56.85#ibcon#*before return 0, iclass 33, count 0 2006.201.04:49:56.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:56.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.04:49:56.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:49:56.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:49:56.85$vck44/vabw=wide 2006.201.04:49:56.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.04:49:56.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.04:49:56.85#ibcon#ireg 8 cls_cnt 0 2006.201.04:49:56.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:56.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:56.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:56.85#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:49:56.85#ibcon#first serial, iclass 39, count 0 2006.201.04:49:56.85#ibcon#enter sib2, iclass 39, count 0 2006.201.04:49:56.85#ibcon#flushed, iclass 39, count 0 2006.201.04:49:56.85#ibcon#about to write, iclass 39, count 0 2006.201.04:49:56.85#ibcon#wrote, iclass 39, count 0 2006.201.04:49:56.85#ibcon#about to read 3, iclass 39, count 0 2006.201.04:49:56.87#ibcon#read 3, iclass 39, count 0 2006.201.04:49:56.87#ibcon#about to read 4, iclass 39, count 0 2006.201.04:49:56.87#ibcon#read 4, iclass 39, count 0 2006.201.04:49:56.87#ibcon#about to read 5, iclass 39, count 0 2006.201.04:49:56.87#ibcon#read 5, iclass 39, count 0 2006.201.04:49:56.87#ibcon#about to read 6, iclass 39, count 0 2006.201.04:49:56.87#ibcon#read 6, iclass 39, count 0 2006.201.04:49:56.87#ibcon#end of sib2, iclass 39, count 0 2006.201.04:49:56.87#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:49:56.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:49:56.87#ibcon#[25=BW32\r\n] 2006.201.04:49:56.87#ibcon#*before write, iclass 39, count 0 2006.201.04:49:56.87#ibcon#enter sib2, iclass 39, count 0 2006.201.04:49:56.87#ibcon#flushed, iclass 39, count 0 2006.201.04:49:56.87#ibcon#about to write, iclass 39, count 0 2006.201.04:49:56.87#ibcon#wrote, iclass 39, count 0 2006.201.04:49:56.87#ibcon#about to read 3, iclass 39, count 0 2006.201.04:49:56.90#ibcon#read 3, iclass 39, count 0 2006.201.04:49:56.90#ibcon#about to read 4, iclass 39, count 0 2006.201.04:49:56.90#ibcon#read 4, iclass 39, count 0 2006.201.04:49:56.90#ibcon#about to read 5, iclass 39, count 0 2006.201.04:49:56.90#ibcon#read 5, iclass 39, count 0 2006.201.04:49:56.90#ibcon#about to read 6, iclass 39, count 0 2006.201.04:49:56.90#ibcon#read 6, iclass 39, count 0 2006.201.04:49:56.90#ibcon#end of sib2, iclass 39, count 0 2006.201.04:49:56.90#ibcon#*after write, iclass 39, count 0 2006.201.04:49:56.90#ibcon#*before return 0, iclass 39, count 0 2006.201.04:49:56.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:56.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.04:49:56.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:49:56.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:49:56.90$vck44/vbbw=wide 2006.201.04:49:56.90#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.04:49:56.90#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.04:49:56.90#ibcon#ireg 8 cls_cnt 0 2006.201.04:49:56.90#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:49:56.97#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:49:56.97#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:49:56.97#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:49:56.97#ibcon#first serial, iclass 2, count 0 2006.201.04:49:56.97#ibcon#enter sib2, iclass 2, count 0 2006.201.04:49:56.97#ibcon#flushed, iclass 2, count 0 2006.201.04:49:56.97#ibcon#about to write, iclass 2, count 0 2006.201.04:49:56.97#ibcon#wrote, iclass 2, count 0 2006.201.04:49:56.97#ibcon#about to read 3, iclass 2, count 0 2006.201.04:49:56.99#ibcon#read 3, iclass 2, count 0 2006.201.04:49:56.99#ibcon#about to read 4, iclass 2, count 0 2006.201.04:49:56.99#ibcon#read 4, iclass 2, count 0 2006.201.04:49:56.99#ibcon#about to read 5, iclass 2, count 0 2006.201.04:49:56.99#ibcon#read 5, iclass 2, count 0 2006.201.04:49:56.99#ibcon#about to read 6, iclass 2, count 0 2006.201.04:49:56.99#ibcon#read 6, iclass 2, count 0 2006.201.04:49:56.99#ibcon#end of sib2, iclass 2, count 0 2006.201.04:49:56.99#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:49:56.99#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:49:56.99#ibcon#[27=BW32\r\n] 2006.201.04:49:56.99#ibcon#*before write, iclass 2, count 0 2006.201.04:49:56.99#ibcon#enter sib2, iclass 2, count 0 2006.201.04:49:56.99#ibcon#flushed, iclass 2, count 0 2006.201.04:49:56.99#ibcon#about to write, iclass 2, count 0 2006.201.04:49:56.99#ibcon#wrote, iclass 2, count 0 2006.201.04:49:56.99#ibcon#about to read 3, iclass 2, count 0 2006.201.04:49:57.02#ibcon#read 3, iclass 2, count 0 2006.201.04:49:57.02#ibcon#about to read 4, iclass 2, count 0 2006.201.04:49:57.02#ibcon#read 4, iclass 2, count 0 2006.201.04:49:57.02#ibcon#about to read 5, iclass 2, count 0 2006.201.04:49:57.02#ibcon#read 5, iclass 2, count 0 2006.201.04:49:57.02#ibcon#about to read 6, iclass 2, count 0 2006.201.04:49:57.02#ibcon#read 6, iclass 2, count 0 2006.201.04:49:57.02#ibcon#end of sib2, iclass 2, count 0 2006.201.04:49:57.02#ibcon#*after write, iclass 2, count 0 2006.201.04:49:57.02#ibcon#*before return 0, iclass 2, count 0 2006.201.04:49:57.02#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:49:57.02#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:49:57.02#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:49:57.02#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:49:57.02$setupk4/ifdk4 2006.201.04:49:57.02$ifdk4/lo= 2006.201.04:49:57.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:49:57.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:49:57.02$ifdk4/patch= 2006.201.04:49:57.02$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:49:57.02$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:49:57.02$setupk4/!*+20s 2006.201.04:50:06.78#abcon#<5=/04 2.6 5.0 22.97 891003.9\r\n> 2006.201.04:50:06.80#abcon#{5=INTERFACE CLEAR} 2006.201.04:50:06.86#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:50:11.24$setupk4/"tpicd 2006.201.04:50:11.24$setupk4/echo=off 2006.201.04:50:11.24$setupk4/xlog=off 2006.201.04:50:11.24:!2006.201.04:51:54 2006.201.04:50:16.14#trakl#Source acquired 2006.201.04:50:17.14#flagr#flagr/antenna,acquired 2006.201.04:51:54.00:preob 2006.201.04:51:54.14/onsource/TRACKING 2006.201.04:51:54.14:!2006.201.04:52:04 2006.201.04:52:04.00:"tape 2006.201.04:52:04.00:"st=record 2006.201.04:52:04.00:data_valid=on 2006.201.04:52:04.00:midob 2006.201.04:52:05.14/onsource/TRACKING 2006.201.04:52:05.14/wx/22.98,1003.8,89 2006.201.04:52:05.30/cable/+6.4642E-03 2006.201.04:52:06.39/va/01,08,usb,yes,28,30 2006.201.04:52:06.39/va/02,07,usb,yes,31,31 2006.201.04:52:06.39/va/03,08,usb,yes,27,29 2006.201.04:52:06.39/va/04,07,usb,yes,31,33 2006.201.04:52:06.39/va/05,04,usb,yes,28,28 2006.201.04:52:06.39/va/06,05,usb,yes,28,28 2006.201.04:52:06.39/va/07,05,usb,yes,27,28 2006.201.04:52:06.39/va/08,04,usb,yes,27,32 2006.201.04:52:06.62/valo/01,524.99,yes,locked 2006.201.04:52:06.62/valo/02,534.99,yes,locked 2006.201.04:52:06.62/valo/03,564.99,yes,locked 2006.201.04:52:06.62/valo/04,624.99,yes,locked 2006.201.04:52:06.62/valo/05,734.99,yes,locked 2006.201.04:52:06.62/valo/06,814.99,yes,locked 2006.201.04:52:06.62/valo/07,864.99,yes,locked 2006.201.04:52:06.62/valo/08,884.99,yes,locked 2006.201.04:52:07.71/vb/01,04,usb,yes,29,27 2006.201.04:52:07.71/vb/02,05,usb,yes,27,27 2006.201.04:52:07.71/vb/03,04,usb,yes,28,31 2006.201.04:52:07.71/vb/04,05,usb,yes,28,27 2006.201.04:52:07.71/vb/05,04,usb,yes,25,27 2006.201.04:52:07.71/vb/06,04,usb,yes,29,25 2006.201.04:52:07.71/vb/07,04,usb,yes,29,29 2006.201.04:52:07.71/vb/08,04,usb,yes,27,30 2006.201.04:52:07.95/vblo/01,629.99,yes,locked 2006.201.04:52:07.95/vblo/02,634.99,yes,locked 2006.201.04:52:07.95/vblo/03,649.99,yes,locked 2006.201.04:52:07.95/vblo/04,679.99,yes,locked 2006.201.04:52:07.95/vblo/05,709.99,yes,locked 2006.201.04:52:07.95/vblo/06,719.99,yes,locked 2006.201.04:52:07.95/vblo/07,734.99,yes,locked 2006.201.04:52:07.95/vblo/08,744.99,yes,locked 2006.201.04:52:08.10/vabw/8 2006.201.04:52:08.25/vbbw/8 2006.201.04:52:08.34/xfe/off,on,15.2 2006.201.04:52:08.72/ifatt/23,28,28,28 2006.201.04:52:09.05/fmout-gps/S +4.53E-07 2006.201.04:52:09.09:!2006.201.04:52:54 2006.201.04:52:54.00:data_valid=off 2006.201.04:52:54.00:"et 2006.201.04:52:54.00:!+3s 2006.201.04:52:57.01:"tape 2006.201.04:52:57.01:postob 2006.201.04:52:57.18/cable/+6.4643E-03 2006.201.04:52:57.18/wx/22.98,1003.8,89 2006.201.04:52:57.24/fmout-gps/S +4.53E-07 2006.201.04:52:57.24:scan_name=201-0455,jd0607,100 2006.201.04:52:57.24:source=0528+134,053056.42,133155.1,2000.0,cw 2006.201.04:52:58.14#flagr#flagr/antenna,new-source 2006.201.04:52:58.14:checkk5 2006.201.04:52:58.49/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:52:58.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:52:59.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:52:59.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:53:00.07/chk_obsdata//k5ts1/T2010452??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.04:53:00.48/chk_obsdata//k5ts2/T2010452??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.04:53:00.88/chk_obsdata//k5ts3/T2010452??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.04:53:01.30/chk_obsdata//k5ts4/T2010452??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.04:53:02.03/k5log//k5ts1_log_newline 2006.201.04:53:02.74/k5log//k5ts2_log_newline 2006.201.04:53:03.45/k5log//k5ts3_log_newline 2006.201.04:53:04.17/k5log//k5ts4_log_newline 2006.201.04:53:04.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:53:04.20:setupk4=1 2006.201.04:53:04.20$setupk4/echo=on 2006.201.04:53:04.20$setupk4/pcalon 2006.201.04:53:04.20$pcalon/"no phase cal control is implemented here 2006.201.04:53:04.20$setupk4/"tpicd=stop 2006.201.04:53:04.20$setupk4/"rec=synch_on 2006.201.04:53:04.20$setupk4/"rec_mode=128 2006.201.04:53:04.20$setupk4/!* 2006.201.04:53:04.20$setupk4/recpk4 2006.201.04:53:04.20$recpk4/recpatch= 2006.201.04:53:04.20$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:53:04.20$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:53:04.20$setupk4/vck44 2006.201.04:53:04.20$vck44/valo=1,524.99 2006.201.04:53:04.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.04:53:04.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.04:53:04.20#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:04.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:04.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:04.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:04.20#ibcon#enter wrdev, iclass 10, count 0 2006.201.04:53:04.20#ibcon#first serial, iclass 10, count 0 2006.201.04:53:04.20#ibcon#enter sib2, iclass 10, count 0 2006.201.04:53:04.20#ibcon#flushed, iclass 10, count 0 2006.201.04:53:04.20#ibcon#about to write, iclass 10, count 0 2006.201.04:53:04.20#ibcon#wrote, iclass 10, count 0 2006.201.04:53:04.20#ibcon#about to read 3, iclass 10, count 0 2006.201.04:53:04.22#ibcon#read 3, iclass 10, count 0 2006.201.04:53:04.22#ibcon#about to read 4, iclass 10, count 0 2006.201.04:53:04.22#ibcon#read 4, iclass 10, count 0 2006.201.04:53:04.22#ibcon#about to read 5, iclass 10, count 0 2006.201.04:53:04.22#ibcon#read 5, iclass 10, count 0 2006.201.04:53:04.22#ibcon#about to read 6, iclass 10, count 0 2006.201.04:53:04.22#ibcon#read 6, iclass 10, count 0 2006.201.04:53:04.22#ibcon#end of sib2, iclass 10, count 0 2006.201.04:53:04.22#ibcon#*mode == 0, iclass 10, count 0 2006.201.04:53:04.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.04:53:04.22#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:53:04.22#ibcon#*before write, iclass 10, count 0 2006.201.04:53:04.22#ibcon#enter sib2, iclass 10, count 0 2006.201.04:53:04.22#ibcon#flushed, iclass 10, count 0 2006.201.04:53:04.22#ibcon#about to write, iclass 10, count 0 2006.201.04:53:04.22#ibcon#wrote, iclass 10, count 0 2006.201.04:53:04.22#ibcon#about to read 3, iclass 10, count 0 2006.201.04:53:04.27#ibcon#read 3, iclass 10, count 0 2006.201.04:53:04.27#ibcon#about to read 4, iclass 10, count 0 2006.201.04:53:04.27#ibcon#read 4, iclass 10, count 0 2006.201.04:53:04.27#ibcon#about to read 5, iclass 10, count 0 2006.201.04:53:04.27#ibcon#read 5, iclass 10, count 0 2006.201.04:53:04.27#ibcon#about to read 6, iclass 10, count 0 2006.201.04:53:04.27#ibcon#read 6, iclass 10, count 0 2006.201.04:53:04.27#ibcon#end of sib2, iclass 10, count 0 2006.201.04:53:04.27#ibcon#*after write, iclass 10, count 0 2006.201.04:53:04.27#ibcon#*before return 0, iclass 10, count 0 2006.201.04:53:04.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:04.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:04.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.04:53:04.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.04:53:04.27$vck44/va=1,8 2006.201.04:53:04.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.04:53:04.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.04:53:04.27#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:04.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:04.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:04.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:04.27#ibcon#enter wrdev, iclass 12, count 2 2006.201.04:53:04.27#ibcon#first serial, iclass 12, count 2 2006.201.04:53:04.27#ibcon#enter sib2, iclass 12, count 2 2006.201.04:53:04.27#ibcon#flushed, iclass 12, count 2 2006.201.04:53:04.27#ibcon#about to write, iclass 12, count 2 2006.201.04:53:04.27#ibcon#wrote, iclass 12, count 2 2006.201.04:53:04.27#ibcon#about to read 3, iclass 12, count 2 2006.201.04:53:04.29#ibcon#read 3, iclass 12, count 2 2006.201.04:53:04.29#ibcon#about to read 4, iclass 12, count 2 2006.201.04:53:04.29#ibcon#read 4, iclass 12, count 2 2006.201.04:53:04.29#ibcon#about to read 5, iclass 12, count 2 2006.201.04:53:04.29#ibcon#read 5, iclass 12, count 2 2006.201.04:53:04.29#ibcon#about to read 6, iclass 12, count 2 2006.201.04:53:04.29#ibcon#read 6, iclass 12, count 2 2006.201.04:53:04.29#ibcon#end of sib2, iclass 12, count 2 2006.201.04:53:04.29#ibcon#*mode == 0, iclass 12, count 2 2006.201.04:53:04.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.04:53:04.29#ibcon#[25=AT01-08\r\n] 2006.201.04:53:04.29#ibcon#*before write, iclass 12, count 2 2006.201.04:53:04.29#ibcon#enter sib2, iclass 12, count 2 2006.201.04:53:04.29#ibcon#flushed, iclass 12, count 2 2006.201.04:53:04.29#ibcon#about to write, iclass 12, count 2 2006.201.04:53:04.29#ibcon#wrote, iclass 12, count 2 2006.201.04:53:04.29#ibcon#about to read 3, iclass 12, count 2 2006.201.04:53:04.32#ibcon#read 3, iclass 12, count 2 2006.201.04:53:04.32#ibcon#about to read 4, iclass 12, count 2 2006.201.04:53:04.32#ibcon#read 4, iclass 12, count 2 2006.201.04:53:04.32#ibcon#about to read 5, iclass 12, count 2 2006.201.04:53:04.32#ibcon#read 5, iclass 12, count 2 2006.201.04:53:04.32#ibcon#about to read 6, iclass 12, count 2 2006.201.04:53:04.32#ibcon#read 6, iclass 12, count 2 2006.201.04:53:04.32#ibcon#end of sib2, iclass 12, count 2 2006.201.04:53:04.32#ibcon#*after write, iclass 12, count 2 2006.201.04:53:04.32#ibcon#*before return 0, iclass 12, count 2 2006.201.04:53:04.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:04.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:04.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.04:53:04.32#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:04.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:04.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:04.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:04.44#ibcon#enter wrdev, iclass 12, count 0 2006.201.04:53:04.44#ibcon#first serial, iclass 12, count 0 2006.201.04:53:04.44#ibcon#enter sib2, iclass 12, count 0 2006.201.04:53:04.44#ibcon#flushed, iclass 12, count 0 2006.201.04:53:04.44#ibcon#about to write, iclass 12, count 0 2006.201.04:53:04.44#ibcon#wrote, iclass 12, count 0 2006.201.04:53:04.44#ibcon#about to read 3, iclass 12, count 0 2006.201.04:53:04.46#ibcon#read 3, iclass 12, count 0 2006.201.04:53:04.46#ibcon#about to read 4, iclass 12, count 0 2006.201.04:53:04.46#ibcon#read 4, iclass 12, count 0 2006.201.04:53:04.46#ibcon#about to read 5, iclass 12, count 0 2006.201.04:53:04.46#ibcon#read 5, iclass 12, count 0 2006.201.04:53:04.46#ibcon#about to read 6, iclass 12, count 0 2006.201.04:53:04.46#ibcon#read 6, iclass 12, count 0 2006.201.04:53:04.46#ibcon#end of sib2, iclass 12, count 0 2006.201.04:53:04.46#ibcon#*mode == 0, iclass 12, count 0 2006.201.04:53:04.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.04:53:04.46#ibcon#[25=USB\r\n] 2006.201.04:53:04.46#ibcon#*before write, iclass 12, count 0 2006.201.04:53:04.46#ibcon#enter sib2, iclass 12, count 0 2006.201.04:53:04.46#ibcon#flushed, iclass 12, count 0 2006.201.04:53:04.46#ibcon#about to write, iclass 12, count 0 2006.201.04:53:04.46#ibcon#wrote, iclass 12, count 0 2006.201.04:53:04.46#ibcon#about to read 3, iclass 12, count 0 2006.201.04:53:04.49#ibcon#read 3, iclass 12, count 0 2006.201.04:53:04.49#ibcon#about to read 4, iclass 12, count 0 2006.201.04:53:04.49#ibcon#read 4, iclass 12, count 0 2006.201.04:53:04.49#ibcon#about to read 5, iclass 12, count 0 2006.201.04:53:04.49#ibcon#read 5, iclass 12, count 0 2006.201.04:53:04.49#ibcon#about to read 6, iclass 12, count 0 2006.201.04:53:04.49#ibcon#read 6, iclass 12, count 0 2006.201.04:53:04.49#ibcon#end of sib2, iclass 12, count 0 2006.201.04:53:04.49#ibcon#*after write, iclass 12, count 0 2006.201.04:53:04.49#ibcon#*before return 0, iclass 12, count 0 2006.201.04:53:04.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:04.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:04.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.04:53:04.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.04:53:04.49$vck44/valo=2,534.99 2006.201.04:53:04.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.04:53:04.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.04:53:04.49#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:04.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:04.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:04.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:04.49#ibcon#enter wrdev, iclass 14, count 0 2006.201.04:53:04.49#ibcon#first serial, iclass 14, count 0 2006.201.04:53:04.49#ibcon#enter sib2, iclass 14, count 0 2006.201.04:53:04.49#ibcon#flushed, iclass 14, count 0 2006.201.04:53:04.49#ibcon#about to write, iclass 14, count 0 2006.201.04:53:04.49#ibcon#wrote, iclass 14, count 0 2006.201.04:53:04.49#ibcon#about to read 3, iclass 14, count 0 2006.201.04:53:04.51#ibcon#read 3, iclass 14, count 0 2006.201.04:53:04.51#ibcon#about to read 4, iclass 14, count 0 2006.201.04:53:04.51#ibcon#read 4, iclass 14, count 0 2006.201.04:53:04.51#ibcon#about to read 5, iclass 14, count 0 2006.201.04:53:04.51#ibcon#read 5, iclass 14, count 0 2006.201.04:53:04.51#ibcon#about to read 6, iclass 14, count 0 2006.201.04:53:04.51#ibcon#read 6, iclass 14, count 0 2006.201.04:53:04.51#ibcon#end of sib2, iclass 14, count 0 2006.201.04:53:04.51#ibcon#*mode == 0, iclass 14, count 0 2006.201.04:53:04.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.04:53:04.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:53:04.51#ibcon#*before write, iclass 14, count 0 2006.201.04:53:04.51#ibcon#enter sib2, iclass 14, count 0 2006.201.04:53:04.51#ibcon#flushed, iclass 14, count 0 2006.201.04:53:04.51#ibcon#about to write, iclass 14, count 0 2006.201.04:53:04.51#ibcon#wrote, iclass 14, count 0 2006.201.04:53:04.51#ibcon#about to read 3, iclass 14, count 0 2006.201.04:53:04.55#ibcon#read 3, iclass 14, count 0 2006.201.04:53:04.55#ibcon#about to read 4, iclass 14, count 0 2006.201.04:53:04.55#ibcon#read 4, iclass 14, count 0 2006.201.04:53:04.55#ibcon#about to read 5, iclass 14, count 0 2006.201.04:53:04.55#ibcon#read 5, iclass 14, count 0 2006.201.04:53:04.55#ibcon#about to read 6, iclass 14, count 0 2006.201.04:53:04.55#ibcon#read 6, iclass 14, count 0 2006.201.04:53:04.55#ibcon#end of sib2, iclass 14, count 0 2006.201.04:53:04.55#ibcon#*after write, iclass 14, count 0 2006.201.04:53:04.55#ibcon#*before return 0, iclass 14, count 0 2006.201.04:53:04.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:04.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:04.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.04:53:04.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.04:53:04.55$vck44/va=2,7 2006.201.04:53:04.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.04:53:04.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.04:53:04.55#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:04.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:04.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:04.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:04.61#ibcon#enter wrdev, iclass 16, count 2 2006.201.04:53:04.61#ibcon#first serial, iclass 16, count 2 2006.201.04:53:04.61#ibcon#enter sib2, iclass 16, count 2 2006.201.04:53:04.61#ibcon#flushed, iclass 16, count 2 2006.201.04:53:04.61#ibcon#about to write, iclass 16, count 2 2006.201.04:53:04.61#ibcon#wrote, iclass 16, count 2 2006.201.04:53:04.61#ibcon#about to read 3, iclass 16, count 2 2006.201.04:53:04.63#ibcon#read 3, iclass 16, count 2 2006.201.04:53:04.63#ibcon#about to read 4, iclass 16, count 2 2006.201.04:53:04.63#ibcon#read 4, iclass 16, count 2 2006.201.04:53:04.63#ibcon#about to read 5, iclass 16, count 2 2006.201.04:53:04.63#ibcon#read 5, iclass 16, count 2 2006.201.04:53:04.63#ibcon#about to read 6, iclass 16, count 2 2006.201.04:53:04.63#ibcon#read 6, iclass 16, count 2 2006.201.04:53:04.63#ibcon#end of sib2, iclass 16, count 2 2006.201.04:53:04.63#ibcon#*mode == 0, iclass 16, count 2 2006.201.04:53:04.63#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.04:53:04.63#ibcon#[25=AT02-07\r\n] 2006.201.04:53:04.63#ibcon#*before write, iclass 16, count 2 2006.201.04:53:04.63#ibcon#enter sib2, iclass 16, count 2 2006.201.04:53:04.63#ibcon#flushed, iclass 16, count 2 2006.201.04:53:04.63#ibcon#about to write, iclass 16, count 2 2006.201.04:53:04.63#ibcon#wrote, iclass 16, count 2 2006.201.04:53:04.63#ibcon#about to read 3, iclass 16, count 2 2006.201.04:53:04.66#ibcon#read 3, iclass 16, count 2 2006.201.04:53:04.66#ibcon#about to read 4, iclass 16, count 2 2006.201.04:53:04.66#ibcon#read 4, iclass 16, count 2 2006.201.04:53:04.66#ibcon#about to read 5, iclass 16, count 2 2006.201.04:53:04.66#ibcon#read 5, iclass 16, count 2 2006.201.04:53:04.66#ibcon#about to read 6, iclass 16, count 2 2006.201.04:53:04.66#ibcon#read 6, iclass 16, count 2 2006.201.04:53:04.66#ibcon#end of sib2, iclass 16, count 2 2006.201.04:53:04.66#ibcon#*after write, iclass 16, count 2 2006.201.04:53:04.66#ibcon#*before return 0, iclass 16, count 2 2006.201.04:53:04.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:04.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:04.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.04:53:04.66#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:04.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:04.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:04.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:04.78#ibcon#enter wrdev, iclass 16, count 0 2006.201.04:53:04.78#ibcon#first serial, iclass 16, count 0 2006.201.04:53:04.78#ibcon#enter sib2, iclass 16, count 0 2006.201.04:53:04.78#ibcon#flushed, iclass 16, count 0 2006.201.04:53:04.78#ibcon#about to write, iclass 16, count 0 2006.201.04:53:04.78#ibcon#wrote, iclass 16, count 0 2006.201.04:53:04.78#ibcon#about to read 3, iclass 16, count 0 2006.201.04:53:04.80#ibcon#read 3, iclass 16, count 0 2006.201.04:53:04.80#ibcon#about to read 4, iclass 16, count 0 2006.201.04:53:04.80#ibcon#read 4, iclass 16, count 0 2006.201.04:53:04.80#ibcon#about to read 5, iclass 16, count 0 2006.201.04:53:04.80#ibcon#read 5, iclass 16, count 0 2006.201.04:53:04.80#ibcon#about to read 6, iclass 16, count 0 2006.201.04:53:04.80#ibcon#read 6, iclass 16, count 0 2006.201.04:53:04.80#ibcon#end of sib2, iclass 16, count 0 2006.201.04:53:04.80#ibcon#*mode == 0, iclass 16, count 0 2006.201.04:53:04.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.04:53:04.80#ibcon#[25=USB\r\n] 2006.201.04:53:04.80#ibcon#*before write, iclass 16, count 0 2006.201.04:53:04.80#ibcon#enter sib2, iclass 16, count 0 2006.201.04:53:04.80#ibcon#flushed, iclass 16, count 0 2006.201.04:53:04.80#ibcon#about to write, iclass 16, count 0 2006.201.04:53:04.80#ibcon#wrote, iclass 16, count 0 2006.201.04:53:04.80#ibcon#about to read 3, iclass 16, count 0 2006.201.04:53:04.83#ibcon#read 3, iclass 16, count 0 2006.201.04:53:04.83#ibcon#about to read 4, iclass 16, count 0 2006.201.04:53:04.83#ibcon#read 4, iclass 16, count 0 2006.201.04:53:04.83#ibcon#about to read 5, iclass 16, count 0 2006.201.04:53:04.83#ibcon#read 5, iclass 16, count 0 2006.201.04:53:04.83#ibcon#about to read 6, iclass 16, count 0 2006.201.04:53:04.83#ibcon#read 6, iclass 16, count 0 2006.201.04:53:04.83#ibcon#end of sib2, iclass 16, count 0 2006.201.04:53:04.83#ibcon#*after write, iclass 16, count 0 2006.201.04:53:04.83#ibcon#*before return 0, iclass 16, count 0 2006.201.04:53:04.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:04.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:04.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.04:53:04.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.04:53:04.83$vck44/valo=3,564.99 2006.201.04:53:04.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.04:53:04.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.04:53:04.83#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:04.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:04.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:04.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:04.83#ibcon#enter wrdev, iclass 18, count 0 2006.201.04:53:04.83#ibcon#first serial, iclass 18, count 0 2006.201.04:53:04.83#ibcon#enter sib2, iclass 18, count 0 2006.201.04:53:04.83#ibcon#flushed, iclass 18, count 0 2006.201.04:53:04.83#ibcon#about to write, iclass 18, count 0 2006.201.04:53:04.83#ibcon#wrote, iclass 18, count 0 2006.201.04:53:04.83#ibcon#about to read 3, iclass 18, count 0 2006.201.04:53:04.85#ibcon#read 3, iclass 18, count 0 2006.201.04:53:04.85#ibcon#about to read 4, iclass 18, count 0 2006.201.04:53:04.85#ibcon#read 4, iclass 18, count 0 2006.201.04:53:04.85#ibcon#about to read 5, iclass 18, count 0 2006.201.04:53:04.85#ibcon#read 5, iclass 18, count 0 2006.201.04:53:04.85#ibcon#about to read 6, iclass 18, count 0 2006.201.04:53:04.85#ibcon#read 6, iclass 18, count 0 2006.201.04:53:04.85#ibcon#end of sib2, iclass 18, count 0 2006.201.04:53:04.85#ibcon#*mode == 0, iclass 18, count 0 2006.201.04:53:04.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.04:53:04.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:53:04.85#ibcon#*before write, iclass 18, count 0 2006.201.04:53:04.85#ibcon#enter sib2, iclass 18, count 0 2006.201.04:53:04.85#ibcon#flushed, iclass 18, count 0 2006.201.04:53:04.85#ibcon#about to write, iclass 18, count 0 2006.201.04:53:04.85#ibcon#wrote, iclass 18, count 0 2006.201.04:53:04.85#ibcon#about to read 3, iclass 18, count 0 2006.201.04:53:04.89#ibcon#read 3, iclass 18, count 0 2006.201.04:53:04.89#ibcon#about to read 4, iclass 18, count 0 2006.201.04:53:04.89#ibcon#read 4, iclass 18, count 0 2006.201.04:53:04.89#ibcon#about to read 5, iclass 18, count 0 2006.201.04:53:04.89#ibcon#read 5, iclass 18, count 0 2006.201.04:53:04.89#ibcon#about to read 6, iclass 18, count 0 2006.201.04:53:04.89#ibcon#read 6, iclass 18, count 0 2006.201.04:53:04.89#ibcon#end of sib2, iclass 18, count 0 2006.201.04:53:04.89#ibcon#*after write, iclass 18, count 0 2006.201.04:53:04.89#ibcon#*before return 0, iclass 18, count 0 2006.201.04:53:04.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:04.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:04.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.04:53:04.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.04:53:04.89$vck44/va=3,8 2006.201.04:53:04.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.04:53:04.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.04:53:04.89#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:04.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:04.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:04.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:04.95#ibcon#enter wrdev, iclass 20, count 2 2006.201.04:53:04.95#ibcon#first serial, iclass 20, count 2 2006.201.04:53:04.95#ibcon#enter sib2, iclass 20, count 2 2006.201.04:53:04.95#ibcon#flushed, iclass 20, count 2 2006.201.04:53:04.95#ibcon#about to write, iclass 20, count 2 2006.201.04:53:04.95#ibcon#wrote, iclass 20, count 2 2006.201.04:53:04.95#ibcon#about to read 3, iclass 20, count 2 2006.201.04:53:04.97#ibcon#read 3, iclass 20, count 2 2006.201.04:53:04.97#ibcon#about to read 4, iclass 20, count 2 2006.201.04:53:04.97#ibcon#read 4, iclass 20, count 2 2006.201.04:53:04.97#ibcon#about to read 5, iclass 20, count 2 2006.201.04:53:04.97#ibcon#read 5, iclass 20, count 2 2006.201.04:53:04.97#ibcon#about to read 6, iclass 20, count 2 2006.201.04:53:04.97#ibcon#read 6, iclass 20, count 2 2006.201.04:53:04.97#ibcon#end of sib2, iclass 20, count 2 2006.201.04:53:04.97#ibcon#*mode == 0, iclass 20, count 2 2006.201.04:53:04.97#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.04:53:04.97#ibcon#[25=AT03-08\r\n] 2006.201.04:53:04.97#ibcon#*before write, iclass 20, count 2 2006.201.04:53:04.97#ibcon#enter sib2, iclass 20, count 2 2006.201.04:53:04.97#ibcon#flushed, iclass 20, count 2 2006.201.04:53:04.97#ibcon#about to write, iclass 20, count 2 2006.201.04:53:04.97#ibcon#wrote, iclass 20, count 2 2006.201.04:53:04.97#ibcon#about to read 3, iclass 20, count 2 2006.201.04:53:05.00#ibcon#read 3, iclass 20, count 2 2006.201.04:53:05.00#ibcon#about to read 4, iclass 20, count 2 2006.201.04:53:05.00#ibcon#read 4, iclass 20, count 2 2006.201.04:53:05.00#ibcon#about to read 5, iclass 20, count 2 2006.201.04:53:05.00#ibcon#read 5, iclass 20, count 2 2006.201.04:53:05.00#ibcon#about to read 6, iclass 20, count 2 2006.201.04:53:05.00#ibcon#read 6, iclass 20, count 2 2006.201.04:53:05.00#ibcon#end of sib2, iclass 20, count 2 2006.201.04:53:05.00#ibcon#*after write, iclass 20, count 2 2006.201.04:53:05.00#ibcon#*before return 0, iclass 20, count 2 2006.201.04:53:05.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:05.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:05.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.04:53:05.00#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:05.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:05.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:05.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:05.12#ibcon#enter wrdev, iclass 20, count 0 2006.201.04:53:05.12#ibcon#first serial, iclass 20, count 0 2006.201.04:53:05.12#ibcon#enter sib2, iclass 20, count 0 2006.201.04:53:05.12#ibcon#flushed, iclass 20, count 0 2006.201.04:53:05.12#ibcon#about to write, iclass 20, count 0 2006.201.04:53:05.12#ibcon#wrote, iclass 20, count 0 2006.201.04:53:05.12#ibcon#about to read 3, iclass 20, count 0 2006.201.04:53:05.14#ibcon#read 3, iclass 20, count 0 2006.201.04:53:05.14#ibcon#about to read 4, iclass 20, count 0 2006.201.04:53:05.14#ibcon#read 4, iclass 20, count 0 2006.201.04:53:05.14#ibcon#about to read 5, iclass 20, count 0 2006.201.04:53:05.14#ibcon#read 5, iclass 20, count 0 2006.201.04:53:05.14#ibcon#about to read 6, iclass 20, count 0 2006.201.04:53:05.14#ibcon#read 6, iclass 20, count 0 2006.201.04:53:05.14#ibcon#end of sib2, iclass 20, count 0 2006.201.04:53:05.14#ibcon#*mode == 0, iclass 20, count 0 2006.201.04:53:05.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.04:53:05.14#ibcon#[25=USB\r\n] 2006.201.04:53:05.14#ibcon#*before write, iclass 20, count 0 2006.201.04:53:05.14#ibcon#enter sib2, iclass 20, count 0 2006.201.04:53:05.14#ibcon#flushed, iclass 20, count 0 2006.201.04:53:05.14#ibcon#about to write, iclass 20, count 0 2006.201.04:53:05.14#ibcon#wrote, iclass 20, count 0 2006.201.04:53:05.14#ibcon#about to read 3, iclass 20, count 0 2006.201.04:53:05.17#ibcon#read 3, iclass 20, count 0 2006.201.04:53:05.17#ibcon#about to read 4, iclass 20, count 0 2006.201.04:53:05.17#ibcon#read 4, iclass 20, count 0 2006.201.04:53:05.17#ibcon#about to read 5, iclass 20, count 0 2006.201.04:53:05.17#ibcon#read 5, iclass 20, count 0 2006.201.04:53:05.17#ibcon#about to read 6, iclass 20, count 0 2006.201.04:53:05.17#ibcon#read 6, iclass 20, count 0 2006.201.04:53:05.17#ibcon#end of sib2, iclass 20, count 0 2006.201.04:53:05.17#ibcon#*after write, iclass 20, count 0 2006.201.04:53:05.17#ibcon#*before return 0, iclass 20, count 0 2006.201.04:53:05.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:05.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:05.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.04:53:05.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.04:53:05.17$vck44/valo=4,624.99 2006.201.04:53:05.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.04:53:05.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.04:53:05.17#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:05.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:05.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:05.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:05.17#ibcon#enter wrdev, iclass 22, count 0 2006.201.04:53:05.17#ibcon#first serial, iclass 22, count 0 2006.201.04:53:05.17#ibcon#enter sib2, iclass 22, count 0 2006.201.04:53:05.17#ibcon#flushed, iclass 22, count 0 2006.201.04:53:05.17#ibcon#about to write, iclass 22, count 0 2006.201.04:53:05.17#ibcon#wrote, iclass 22, count 0 2006.201.04:53:05.17#ibcon#about to read 3, iclass 22, count 0 2006.201.04:53:05.19#ibcon#read 3, iclass 22, count 0 2006.201.04:53:05.19#ibcon#about to read 4, iclass 22, count 0 2006.201.04:53:05.19#ibcon#read 4, iclass 22, count 0 2006.201.04:53:05.19#ibcon#about to read 5, iclass 22, count 0 2006.201.04:53:05.19#ibcon#read 5, iclass 22, count 0 2006.201.04:53:05.19#ibcon#about to read 6, iclass 22, count 0 2006.201.04:53:05.19#ibcon#read 6, iclass 22, count 0 2006.201.04:53:05.19#ibcon#end of sib2, iclass 22, count 0 2006.201.04:53:05.19#ibcon#*mode == 0, iclass 22, count 0 2006.201.04:53:05.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.04:53:05.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:53:05.19#ibcon#*before write, iclass 22, count 0 2006.201.04:53:05.19#ibcon#enter sib2, iclass 22, count 0 2006.201.04:53:05.19#ibcon#flushed, iclass 22, count 0 2006.201.04:53:05.19#ibcon#about to write, iclass 22, count 0 2006.201.04:53:05.19#ibcon#wrote, iclass 22, count 0 2006.201.04:53:05.19#ibcon#about to read 3, iclass 22, count 0 2006.201.04:53:05.23#ibcon#read 3, iclass 22, count 0 2006.201.04:53:05.23#ibcon#about to read 4, iclass 22, count 0 2006.201.04:53:05.23#ibcon#read 4, iclass 22, count 0 2006.201.04:53:05.23#ibcon#about to read 5, iclass 22, count 0 2006.201.04:53:05.23#ibcon#read 5, iclass 22, count 0 2006.201.04:53:05.23#ibcon#about to read 6, iclass 22, count 0 2006.201.04:53:05.23#ibcon#read 6, iclass 22, count 0 2006.201.04:53:05.23#ibcon#end of sib2, iclass 22, count 0 2006.201.04:53:05.23#ibcon#*after write, iclass 22, count 0 2006.201.04:53:05.23#ibcon#*before return 0, iclass 22, count 0 2006.201.04:53:05.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:05.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:05.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.04:53:05.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.04:53:05.23$vck44/va=4,7 2006.201.04:53:05.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.04:53:05.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.04:53:05.23#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:05.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:05.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:05.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:05.29#ibcon#enter wrdev, iclass 24, count 2 2006.201.04:53:05.29#ibcon#first serial, iclass 24, count 2 2006.201.04:53:05.29#ibcon#enter sib2, iclass 24, count 2 2006.201.04:53:05.29#ibcon#flushed, iclass 24, count 2 2006.201.04:53:05.29#ibcon#about to write, iclass 24, count 2 2006.201.04:53:05.29#ibcon#wrote, iclass 24, count 2 2006.201.04:53:05.29#ibcon#about to read 3, iclass 24, count 2 2006.201.04:53:05.31#ibcon#read 3, iclass 24, count 2 2006.201.04:53:05.31#ibcon#about to read 4, iclass 24, count 2 2006.201.04:53:05.31#ibcon#read 4, iclass 24, count 2 2006.201.04:53:05.31#ibcon#about to read 5, iclass 24, count 2 2006.201.04:53:05.31#ibcon#read 5, iclass 24, count 2 2006.201.04:53:05.31#ibcon#about to read 6, iclass 24, count 2 2006.201.04:53:05.31#ibcon#read 6, iclass 24, count 2 2006.201.04:53:05.31#ibcon#end of sib2, iclass 24, count 2 2006.201.04:53:05.31#ibcon#*mode == 0, iclass 24, count 2 2006.201.04:53:05.31#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.04:53:05.31#ibcon#[25=AT04-07\r\n] 2006.201.04:53:05.31#ibcon#*before write, iclass 24, count 2 2006.201.04:53:05.31#ibcon#enter sib2, iclass 24, count 2 2006.201.04:53:05.31#ibcon#flushed, iclass 24, count 2 2006.201.04:53:05.31#ibcon#about to write, iclass 24, count 2 2006.201.04:53:05.31#ibcon#wrote, iclass 24, count 2 2006.201.04:53:05.31#ibcon#about to read 3, iclass 24, count 2 2006.201.04:53:05.34#ibcon#read 3, iclass 24, count 2 2006.201.04:53:05.34#ibcon#about to read 4, iclass 24, count 2 2006.201.04:53:05.34#ibcon#read 4, iclass 24, count 2 2006.201.04:53:05.34#ibcon#about to read 5, iclass 24, count 2 2006.201.04:53:05.34#ibcon#read 5, iclass 24, count 2 2006.201.04:53:05.34#ibcon#about to read 6, iclass 24, count 2 2006.201.04:53:05.34#ibcon#read 6, iclass 24, count 2 2006.201.04:53:05.34#ibcon#end of sib2, iclass 24, count 2 2006.201.04:53:05.34#ibcon#*after write, iclass 24, count 2 2006.201.04:53:05.34#ibcon#*before return 0, iclass 24, count 2 2006.201.04:53:05.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:05.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:05.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.04:53:05.34#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:05.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:05.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:05.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:05.46#ibcon#enter wrdev, iclass 24, count 0 2006.201.04:53:05.46#ibcon#first serial, iclass 24, count 0 2006.201.04:53:05.46#ibcon#enter sib2, iclass 24, count 0 2006.201.04:53:05.46#ibcon#flushed, iclass 24, count 0 2006.201.04:53:05.46#ibcon#about to write, iclass 24, count 0 2006.201.04:53:05.46#ibcon#wrote, iclass 24, count 0 2006.201.04:53:05.46#ibcon#about to read 3, iclass 24, count 0 2006.201.04:53:05.48#ibcon#read 3, iclass 24, count 0 2006.201.04:53:05.48#ibcon#about to read 4, iclass 24, count 0 2006.201.04:53:05.48#ibcon#read 4, iclass 24, count 0 2006.201.04:53:05.48#ibcon#about to read 5, iclass 24, count 0 2006.201.04:53:05.48#ibcon#read 5, iclass 24, count 0 2006.201.04:53:05.48#ibcon#about to read 6, iclass 24, count 0 2006.201.04:53:05.48#ibcon#read 6, iclass 24, count 0 2006.201.04:53:05.48#ibcon#end of sib2, iclass 24, count 0 2006.201.04:53:05.48#ibcon#*mode == 0, iclass 24, count 0 2006.201.04:53:05.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.04:53:05.48#ibcon#[25=USB\r\n] 2006.201.04:53:05.48#ibcon#*before write, iclass 24, count 0 2006.201.04:53:05.48#ibcon#enter sib2, iclass 24, count 0 2006.201.04:53:05.48#ibcon#flushed, iclass 24, count 0 2006.201.04:53:05.48#ibcon#about to write, iclass 24, count 0 2006.201.04:53:05.48#ibcon#wrote, iclass 24, count 0 2006.201.04:53:05.48#ibcon#about to read 3, iclass 24, count 0 2006.201.04:53:05.51#ibcon#read 3, iclass 24, count 0 2006.201.04:53:05.51#ibcon#about to read 4, iclass 24, count 0 2006.201.04:53:05.51#ibcon#read 4, iclass 24, count 0 2006.201.04:53:05.51#ibcon#about to read 5, iclass 24, count 0 2006.201.04:53:05.51#ibcon#read 5, iclass 24, count 0 2006.201.04:53:05.51#ibcon#about to read 6, iclass 24, count 0 2006.201.04:53:05.51#ibcon#read 6, iclass 24, count 0 2006.201.04:53:05.51#ibcon#end of sib2, iclass 24, count 0 2006.201.04:53:05.51#ibcon#*after write, iclass 24, count 0 2006.201.04:53:05.51#ibcon#*before return 0, iclass 24, count 0 2006.201.04:53:05.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:05.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:05.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.04:53:05.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.04:53:05.51$vck44/valo=5,734.99 2006.201.04:53:05.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.04:53:05.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.04:53:05.51#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:05.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:05.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:05.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:05.51#ibcon#enter wrdev, iclass 26, count 0 2006.201.04:53:05.51#ibcon#first serial, iclass 26, count 0 2006.201.04:53:05.51#ibcon#enter sib2, iclass 26, count 0 2006.201.04:53:05.51#ibcon#flushed, iclass 26, count 0 2006.201.04:53:05.51#ibcon#about to write, iclass 26, count 0 2006.201.04:53:05.51#ibcon#wrote, iclass 26, count 0 2006.201.04:53:05.51#ibcon#about to read 3, iclass 26, count 0 2006.201.04:53:05.53#ibcon#read 3, iclass 26, count 0 2006.201.04:53:05.53#ibcon#about to read 4, iclass 26, count 0 2006.201.04:53:05.53#ibcon#read 4, iclass 26, count 0 2006.201.04:53:05.53#ibcon#about to read 5, iclass 26, count 0 2006.201.04:53:05.53#ibcon#read 5, iclass 26, count 0 2006.201.04:53:05.53#ibcon#about to read 6, iclass 26, count 0 2006.201.04:53:05.53#ibcon#read 6, iclass 26, count 0 2006.201.04:53:05.53#ibcon#end of sib2, iclass 26, count 0 2006.201.04:53:05.53#ibcon#*mode == 0, iclass 26, count 0 2006.201.04:53:05.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.04:53:05.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:53:05.53#ibcon#*before write, iclass 26, count 0 2006.201.04:53:05.53#ibcon#enter sib2, iclass 26, count 0 2006.201.04:53:05.53#ibcon#flushed, iclass 26, count 0 2006.201.04:53:05.53#ibcon#about to write, iclass 26, count 0 2006.201.04:53:05.53#ibcon#wrote, iclass 26, count 0 2006.201.04:53:05.53#ibcon#about to read 3, iclass 26, count 0 2006.201.04:53:05.57#ibcon#read 3, iclass 26, count 0 2006.201.04:53:05.57#ibcon#about to read 4, iclass 26, count 0 2006.201.04:53:05.57#ibcon#read 4, iclass 26, count 0 2006.201.04:53:05.57#ibcon#about to read 5, iclass 26, count 0 2006.201.04:53:05.57#ibcon#read 5, iclass 26, count 0 2006.201.04:53:05.57#ibcon#about to read 6, iclass 26, count 0 2006.201.04:53:05.57#ibcon#read 6, iclass 26, count 0 2006.201.04:53:05.57#ibcon#end of sib2, iclass 26, count 0 2006.201.04:53:05.57#ibcon#*after write, iclass 26, count 0 2006.201.04:53:05.57#ibcon#*before return 0, iclass 26, count 0 2006.201.04:53:05.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:05.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:05.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.04:53:05.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.04:53:05.57$vck44/va=5,4 2006.201.04:53:05.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.04:53:05.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.04:53:05.57#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:05.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:05.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:05.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:05.63#ibcon#enter wrdev, iclass 28, count 2 2006.201.04:53:05.63#ibcon#first serial, iclass 28, count 2 2006.201.04:53:05.63#ibcon#enter sib2, iclass 28, count 2 2006.201.04:53:05.63#ibcon#flushed, iclass 28, count 2 2006.201.04:53:05.63#ibcon#about to write, iclass 28, count 2 2006.201.04:53:05.63#ibcon#wrote, iclass 28, count 2 2006.201.04:53:05.63#ibcon#about to read 3, iclass 28, count 2 2006.201.04:53:05.65#ibcon#read 3, iclass 28, count 2 2006.201.04:53:05.65#ibcon#about to read 4, iclass 28, count 2 2006.201.04:53:05.65#ibcon#read 4, iclass 28, count 2 2006.201.04:53:05.65#ibcon#about to read 5, iclass 28, count 2 2006.201.04:53:05.65#ibcon#read 5, iclass 28, count 2 2006.201.04:53:05.65#ibcon#about to read 6, iclass 28, count 2 2006.201.04:53:05.65#ibcon#read 6, iclass 28, count 2 2006.201.04:53:05.65#ibcon#end of sib2, iclass 28, count 2 2006.201.04:53:05.65#ibcon#*mode == 0, iclass 28, count 2 2006.201.04:53:05.65#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.04:53:05.65#ibcon#[25=AT05-04\r\n] 2006.201.04:53:05.65#ibcon#*before write, iclass 28, count 2 2006.201.04:53:05.65#ibcon#enter sib2, iclass 28, count 2 2006.201.04:53:05.65#ibcon#flushed, iclass 28, count 2 2006.201.04:53:05.65#ibcon#about to write, iclass 28, count 2 2006.201.04:53:05.65#ibcon#wrote, iclass 28, count 2 2006.201.04:53:05.65#ibcon#about to read 3, iclass 28, count 2 2006.201.04:53:05.68#ibcon#read 3, iclass 28, count 2 2006.201.04:53:05.68#ibcon#about to read 4, iclass 28, count 2 2006.201.04:53:05.68#ibcon#read 4, iclass 28, count 2 2006.201.04:53:05.68#ibcon#about to read 5, iclass 28, count 2 2006.201.04:53:05.68#ibcon#read 5, iclass 28, count 2 2006.201.04:53:05.68#ibcon#about to read 6, iclass 28, count 2 2006.201.04:53:05.68#ibcon#read 6, iclass 28, count 2 2006.201.04:53:05.68#ibcon#end of sib2, iclass 28, count 2 2006.201.04:53:05.68#ibcon#*after write, iclass 28, count 2 2006.201.04:53:05.68#ibcon#*before return 0, iclass 28, count 2 2006.201.04:53:05.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:05.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:05.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.04:53:05.68#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:05.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:05.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:05.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:05.80#ibcon#enter wrdev, iclass 28, count 0 2006.201.04:53:05.80#ibcon#first serial, iclass 28, count 0 2006.201.04:53:05.80#ibcon#enter sib2, iclass 28, count 0 2006.201.04:53:05.80#ibcon#flushed, iclass 28, count 0 2006.201.04:53:05.80#ibcon#about to write, iclass 28, count 0 2006.201.04:53:05.80#ibcon#wrote, iclass 28, count 0 2006.201.04:53:05.80#ibcon#about to read 3, iclass 28, count 0 2006.201.04:53:05.82#ibcon#read 3, iclass 28, count 0 2006.201.04:53:05.82#ibcon#about to read 4, iclass 28, count 0 2006.201.04:53:05.82#ibcon#read 4, iclass 28, count 0 2006.201.04:53:05.82#ibcon#about to read 5, iclass 28, count 0 2006.201.04:53:05.82#ibcon#read 5, iclass 28, count 0 2006.201.04:53:05.82#ibcon#about to read 6, iclass 28, count 0 2006.201.04:53:05.82#ibcon#read 6, iclass 28, count 0 2006.201.04:53:05.82#ibcon#end of sib2, iclass 28, count 0 2006.201.04:53:05.82#ibcon#*mode == 0, iclass 28, count 0 2006.201.04:53:05.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.04:53:05.82#ibcon#[25=USB\r\n] 2006.201.04:53:05.82#ibcon#*before write, iclass 28, count 0 2006.201.04:53:05.82#ibcon#enter sib2, iclass 28, count 0 2006.201.04:53:05.82#ibcon#flushed, iclass 28, count 0 2006.201.04:53:05.82#ibcon#about to write, iclass 28, count 0 2006.201.04:53:05.82#ibcon#wrote, iclass 28, count 0 2006.201.04:53:05.82#ibcon#about to read 3, iclass 28, count 0 2006.201.04:53:05.85#ibcon#read 3, iclass 28, count 0 2006.201.04:53:05.85#ibcon#about to read 4, iclass 28, count 0 2006.201.04:53:05.85#ibcon#read 4, iclass 28, count 0 2006.201.04:53:05.85#ibcon#about to read 5, iclass 28, count 0 2006.201.04:53:05.85#ibcon#read 5, iclass 28, count 0 2006.201.04:53:05.85#ibcon#about to read 6, iclass 28, count 0 2006.201.04:53:05.85#ibcon#read 6, iclass 28, count 0 2006.201.04:53:05.85#ibcon#end of sib2, iclass 28, count 0 2006.201.04:53:05.85#ibcon#*after write, iclass 28, count 0 2006.201.04:53:05.85#ibcon#*before return 0, iclass 28, count 0 2006.201.04:53:05.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:05.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:05.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.04:53:05.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.04:53:05.85$vck44/valo=6,814.99 2006.201.04:53:05.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.04:53:05.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.04:53:05.85#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:05.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:05.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:05.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:05.85#ibcon#enter wrdev, iclass 30, count 0 2006.201.04:53:05.85#ibcon#first serial, iclass 30, count 0 2006.201.04:53:05.85#ibcon#enter sib2, iclass 30, count 0 2006.201.04:53:05.85#ibcon#flushed, iclass 30, count 0 2006.201.04:53:05.85#ibcon#about to write, iclass 30, count 0 2006.201.04:53:05.85#ibcon#wrote, iclass 30, count 0 2006.201.04:53:05.85#ibcon#about to read 3, iclass 30, count 0 2006.201.04:53:05.87#ibcon#read 3, iclass 30, count 0 2006.201.04:53:05.87#ibcon#about to read 4, iclass 30, count 0 2006.201.04:53:05.87#ibcon#read 4, iclass 30, count 0 2006.201.04:53:05.87#ibcon#about to read 5, iclass 30, count 0 2006.201.04:53:05.87#ibcon#read 5, iclass 30, count 0 2006.201.04:53:05.87#ibcon#about to read 6, iclass 30, count 0 2006.201.04:53:05.87#ibcon#read 6, iclass 30, count 0 2006.201.04:53:05.87#ibcon#end of sib2, iclass 30, count 0 2006.201.04:53:05.87#ibcon#*mode == 0, iclass 30, count 0 2006.201.04:53:05.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.04:53:05.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:53:05.87#ibcon#*before write, iclass 30, count 0 2006.201.04:53:05.87#ibcon#enter sib2, iclass 30, count 0 2006.201.04:53:05.87#ibcon#flushed, iclass 30, count 0 2006.201.04:53:05.87#ibcon#about to write, iclass 30, count 0 2006.201.04:53:05.87#ibcon#wrote, iclass 30, count 0 2006.201.04:53:05.87#ibcon#about to read 3, iclass 30, count 0 2006.201.04:53:05.91#ibcon#read 3, iclass 30, count 0 2006.201.04:53:05.91#ibcon#about to read 4, iclass 30, count 0 2006.201.04:53:05.91#ibcon#read 4, iclass 30, count 0 2006.201.04:53:05.91#ibcon#about to read 5, iclass 30, count 0 2006.201.04:53:05.91#ibcon#read 5, iclass 30, count 0 2006.201.04:53:05.91#ibcon#about to read 6, iclass 30, count 0 2006.201.04:53:05.91#ibcon#read 6, iclass 30, count 0 2006.201.04:53:05.91#ibcon#end of sib2, iclass 30, count 0 2006.201.04:53:05.91#ibcon#*after write, iclass 30, count 0 2006.201.04:53:05.91#ibcon#*before return 0, iclass 30, count 0 2006.201.04:53:05.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:05.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:05.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.04:53:05.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.04:53:05.91$vck44/va=6,5 2006.201.04:53:05.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.04:53:05.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.04:53:05.91#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:05.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:05.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:05.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:05.97#ibcon#enter wrdev, iclass 32, count 2 2006.201.04:53:05.97#ibcon#first serial, iclass 32, count 2 2006.201.04:53:05.97#ibcon#enter sib2, iclass 32, count 2 2006.201.04:53:05.97#ibcon#flushed, iclass 32, count 2 2006.201.04:53:05.97#ibcon#about to write, iclass 32, count 2 2006.201.04:53:05.97#ibcon#wrote, iclass 32, count 2 2006.201.04:53:05.97#ibcon#about to read 3, iclass 32, count 2 2006.201.04:53:05.99#ibcon#read 3, iclass 32, count 2 2006.201.04:53:05.99#ibcon#about to read 4, iclass 32, count 2 2006.201.04:53:05.99#ibcon#read 4, iclass 32, count 2 2006.201.04:53:05.99#ibcon#about to read 5, iclass 32, count 2 2006.201.04:53:05.99#ibcon#read 5, iclass 32, count 2 2006.201.04:53:05.99#ibcon#about to read 6, iclass 32, count 2 2006.201.04:53:05.99#ibcon#read 6, iclass 32, count 2 2006.201.04:53:05.99#ibcon#end of sib2, iclass 32, count 2 2006.201.04:53:05.99#ibcon#*mode == 0, iclass 32, count 2 2006.201.04:53:05.99#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.04:53:05.99#ibcon#[25=AT06-05\r\n] 2006.201.04:53:05.99#ibcon#*before write, iclass 32, count 2 2006.201.04:53:05.99#ibcon#enter sib2, iclass 32, count 2 2006.201.04:53:05.99#ibcon#flushed, iclass 32, count 2 2006.201.04:53:05.99#ibcon#about to write, iclass 32, count 2 2006.201.04:53:05.99#ibcon#wrote, iclass 32, count 2 2006.201.04:53:05.99#ibcon#about to read 3, iclass 32, count 2 2006.201.04:53:06.02#ibcon#read 3, iclass 32, count 2 2006.201.04:53:06.02#ibcon#about to read 4, iclass 32, count 2 2006.201.04:53:06.02#ibcon#read 4, iclass 32, count 2 2006.201.04:53:06.02#ibcon#about to read 5, iclass 32, count 2 2006.201.04:53:06.02#ibcon#read 5, iclass 32, count 2 2006.201.04:53:06.02#ibcon#about to read 6, iclass 32, count 2 2006.201.04:53:06.02#ibcon#read 6, iclass 32, count 2 2006.201.04:53:06.02#ibcon#end of sib2, iclass 32, count 2 2006.201.04:53:06.02#ibcon#*after write, iclass 32, count 2 2006.201.04:53:06.02#ibcon#*before return 0, iclass 32, count 2 2006.201.04:53:06.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:06.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:06.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.04:53:06.02#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:06.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:06.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:06.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:06.14#ibcon#enter wrdev, iclass 32, count 0 2006.201.04:53:06.14#ibcon#first serial, iclass 32, count 0 2006.201.04:53:06.14#ibcon#enter sib2, iclass 32, count 0 2006.201.04:53:06.14#ibcon#flushed, iclass 32, count 0 2006.201.04:53:06.14#ibcon#about to write, iclass 32, count 0 2006.201.04:53:06.14#ibcon#wrote, iclass 32, count 0 2006.201.04:53:06.14#ibcon#about to read 3, iclass 32, count 0 2006.201.04:53:06.16#ibcon#read 3, iclass 32, count 0 2006.201.04:53:06.16#ibcon#about to read 4, iclass 32, count 0 2006.201.04:53:06.16#ibcon#read 4, iclass 32, count 0 2006.201.04:53:06.16#ibcon#about to read 5, iclass 32, count 0 2006.201.04:53:06.16#ibcon#read 5, iclass 32, count 0 2006.201.04:53:06.16#ibcon#about to read 6, iclass 32, count 0 2006.201.04:53:06.16#ibcon#read 6, iclass 32, count 0 2006.201.04:53:06.16#ibcon#end of sib2, iclass 32, count 0 2006.201.04:53:06.16#ibcon#*mode == 0, iclass 32, count 0 2006.201.04:53:06.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.04:53:06.16#ibcon#[25=USB\r\n] 2006.201.04:53:06.16#ibcon#*before write, iclass 32, count 0 2006.201.04:53:06.16#ibcon#enter sib2, iclass 32, count 0 2006.201.04:53:06.16#ibcon#flushed, iclass 32, count 0 2006.201.04:53:06.16#ibcon#about to write, iclass 32, count 0 2006.201.04:53:06.16#ibcon#wrote, iclass 32, count 0 2006.201.04:53:06.16#ibcon#about to read 3, iclass 32, count 0 2006.201.04:53:06.19#ibcon#read 3, iclass 32, count 0 2006.201.04:53:06.19#ibcon#about to read 4, iclass 32, count 0 2006.201.04:53:06.19#ibcon#read 4, iclass 32, count 0 2006.201.04:53:06.19#ibcon#about to read 5, iclass 32, count 0 2006.201.04:53:06.19#ibcon#read 5, iclass 32, count 0 2006.201.04:53:06.19#ibcon#about to read 6, iclass 32, count 0 2006.201.04:53:06.19#ibcon#read 6, iclass 32, count 0 2006.201.04:53:06.19#ibcon#end of sib2, iclass 32, count 0 2006.201.04:53:06.19#ibcon#*after write, iclass 32, count 0 2006.201.04:53:06.19#ibcon#*before return 0, iclass 32, count 0 2006.201.04:53:06.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:06.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:06.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.04:53:06.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.04:53:06.19$vck44/valo=7,864.99 2006.201.04:53:06.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.04:53:06.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.04:53:06.19#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:06.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:06.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:06.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:06.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.04:53:06.19#ibcon#first serial, iclass 34, count 0 2006.201.04:53:06.19#ibcon#enter sib2, iclass 34, count 0 2006.201.04:53:06.19#ibcon#flushed, iclass 34, count 0 2006.201.04:53:06.19#ibcon#about to write, iclass 34, count 0 2006.201.04:53:06.19#ibcon#wrote, iclass 34, count 0 2006.201.04:53:06.19#ibcon#about to read 3, iclass 34, count 0 2006.201.04:53:06.21#ibcon#read 3, iclass 34, count 0 2006.201.04:53:06.21#ibcon#about to read 4, iclass 34, count 0 2006.201.04:53:06.21#ibcon#read 4, iclass 34, count 0 2006.201.04:53:06.21#ibcon#about to read 5, iclass 34, count 0 2006.201.04:53:06.21#ibcon#read 5, iclass 34, count 0 2006.201.04:53:06.21#ibcon#about to read 6, iclass 34, count 0 2006.201.04:53:06.21#ibcon#read 6, iclass 34, count 0 2006.201.04:53:06.21#ibcon#end of sib2, iclass 34, count 0 2006.201.04:53:06.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.04:53:06.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.04:53:06.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:53:06.21#ibcon#*before write, iclass 34, count 0 2006.201.04:53:06.21#ibcon#enter sib2, iclass 34, count 0 2006.201.04:53:06.21#ibcon#flushed, iclass 34, count 0 2006.201.04:53:06.21#ibcon#about to write, iclass 34, count 0 2006.201.04:53:06.21#ibcon#wrote, iclass 34, count 0 2006.201.04:53:06.21#ibcon#about to read 3, iclass 34, count 0 2006.201.04:53:06.25#ibcon#read 3, iclass 34, count 0 2006.201.04:53:06.25#ibcon#about to read 4, iclass 34, count 0 2006.201.04:53:06.25#ibcon#read 4, iclass 34, count 0 2006.201.04:53:06.25#ibcon#about to read 5, iclass 34, count 0 2006.201.04:53:06.25#ibcon#read 5, iclass 34, count 0 2006.201.04:53:06.25#ibcon#about to read 6, iclass 34, count 0 2006.201.04:53:06.25#ibcon#read 6, iclass 34, count 0 2006.201.04:53:06.25#ibcon#end of sib2, iclass 34, count 0 2006.201.04:53:06.25#ibcon#*after write, iclass 34, count 0 2006.201.04:53:06.25#ibcon#*before return 0, iclass 34, count 0 2006.201.04:53:06.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:06.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:06.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.04:53:06.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.04:53:06.25$vck44/va=7,5 2006.201.04:53:06.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.04:53:06.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.04:53:06.25#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:06.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:06.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:06.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:06.31#ibcon#enter wrdev, iclass 36, count 2 2006.201.04:53:06.31#ibcon#first serial, iclass 36, count 2 2006.201.04:53:06.31#ibcon#enter sib2, iclass 36, count 2 2006.201.04:53:06.31#ibcon#flushed, iclass 36, count 2 2006.201.04:53:06.31#ibcon#about to write, iclass 36, count 2 2006.201.04:53:06.31#ibcon#wrote, iclass 36, count 2 2006.201.04:53:06.31#ibcon#about to read 3, iclass 36, count 2 2006.201.04:53:06.33#ibcon#read 3, iclass 36, count 2 2006.201.04:53:06.33#ibcon#about to read 4, iclass 36, count 2 2006.201.04:53:06.33#ibcon#read 4, iclass 36, count 2 2006.201.04:53:06.33#ibcon#about to read 5, iclass 36, count 2 2006.201.04:53:06.33#ibcon#read 5, iclass 36, count 2 2006.201.04:53:06.33#ibcon#about to read 6, iclass 36, count 2 2006.201.04:53:06.33#ibcon#read 6, iclass 36, count 2 2006.201.04:53:06.33#ibcon#end of sib2, iclass 36, count 2 2006.201.04:53:06.33#ibcon#*mode == 0, iclass 36, count 2 2006.201.04:53:06.33#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.04:53:06.33#ibcon#[25=AT07-05\r\n] 2006.201.04:53:06.33#ibcon#*before write, iclass 36, count 2 2006.201.04:53:06.33#ibcon#enter sib2, iclass 36, count 2 2006.201.04:53:06.33#ibcon#flushed, iclass 36, count 2 2006.201.04:53:06.33#ibcon#about to write, iclass 36, count 2 2006.201.04:53:06.33#ibcon#wrote, iclass 36, count 2 2006.201.04:53:06.33#ibcon#about to read 3, iclass 36, count 2 2006.201.04:53:06.36#ibcon#read 3, iclass 36, count 2 2006.201.04:53:06.36#ibcon#about to read 4, iclass 36, count 2 2006.201.04:53:06.36#ibcon#read 4, iclass 36, count 2 2006.201.04:53:06.36#ibcon#about to read 5, iclass 36, count 2 2006.201.04:53:06.36#ibcon#read 5, iclass 36, count 2 2006.201.04:53:06.36#ibcon#about to read 6, iclass 36, count 2 2006.201.04:53:06.36#ibcon#read 6, iclass 36, count 2 2006.201.04:53:06.36#ibcon#end of sib2, iclass 36, count 2 2006.201.04:53:06.36#ibcon#*after write, iclass 36, count 2 2006.201.04:53:06.36#ibcon#*before return 0, iclass 36, count 2 2006.201.04:53:06.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:06.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:06.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.04:53:06.36#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:06.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:06.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:06.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:06.48#ibcon#enter wrdev, iclass 36, count 0 2006.201.04:53:06.48#ibcon#first serial, iclass 36, count 0 2006.201.04:53:06.48#ibcon#enter sib2, iclass 36, count 0 2006.201.04:53:06.48#ibcon#flushed, iclass 36, count 0 2006.201.04:53:06.48#ibcon#about to write, iclass 36, count 0 2006.201.04:53:06.48#ibcon#wrote, iclass 36, count 0 2006.201.04:53:06.48#ibcon#about to read 3, iclass 36, count 0 2006.201.04:53:06.50#ibcon#read 3, iclass 36, count 0 2006.201.04:53:06.50#ibcon#about to read 4, iclass 36, count 0 2006.201.04:53:06.50#ibcon#read 4, iclass 36, count 0 2006.201.04:53:06.50#ibcon#about to read 5, iclass 36, count 0 2006.201.04:53:06.50#ibcon#read 5, iclass 36, count 0 2006.201.04:53:06.50#ibcon#about to read 6, iclass 36, count 0 2006.201.04:53:06.50#ibcon#read 6, iclass 36, count 0 2006.201.04:53:06.50#ibcon#end of sib2, iclass 36, count 0 2006.201.04:53:06.50#ibcon#*mode == 0, iclass 36, count 0 2006.201.04:53:06.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.04:53:06.50#ibcon#[25=USB\r\n] 2006.201.04:53:06.50#ibcon#*before write, iclass 36, count 0 2006.201.04:53:06.50#ibcon#enter sib2, iclass 36, count 0 2006.201.04:53:06.50#ibcon#flushed, iclass 36, count 0 2006.201.04:53:06.50#ibcon#about to write, iclass 36, count 0 2006.201.04:53:06.50#ibcon#wrote, iclass 36, count 0 2006.201.04:53:06.50#ibcon#about to read 3, iclass 36, count 0 2006.201.04:53:06.53#ibcon#read 3, iclass 36, count 0 2006.201.04:53:06.53#ibcon#about to read 4, iclass 36, count 0 2006.201.04:53:06.53#ibcon#read 4, iclass 36, count 0 2006.201.04:53:06.53#ibcon#about to read 5, iclass 36, count 0 2006.201.04:53:06.53#ibcon#read 5, iclass 36, count 0 2006.201.04:53:06.53#ibcon#about to read 6, iclass 36, count 0 2006.201.04:53:06.53#ibcon#read 6, iclass 36, count 0 2006.201.04:53:06.53#ibcon#end of sib2, iclass 36, count 0 2006.201.04:53:06.53#ibcon#*after write, iclass 36, count 0 2006.201.04:53:06.53#ibcon#*before return 0, iclass 36, count 0 2006.201.04:53:06.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:06.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:06.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.04:53:06.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.04:53:06.53$vck44/valo=8,884.99 2006.201.04:53:06.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.04:53:06.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.04:53:06.53#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:06.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:06.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:06.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:06.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.04:53:06.53#ibcon#first serial, iclass 38, count 0 2006.201.04:53:06.53#ibcon#enter sib2, iclass 38, count 0 2006.201.04:53:06.53#ibcon#flushed, iclass 38, count 0 2006.201.04:53:06.53#ibcon#about to write, iclass 38, count 0 2006.201.04:53:06.53#ibcon#wrote, iclass 38, count 0 2006.201.04:53:06.53#ibcon#about to read 3, iclass 38, count 0 2006.201.04:53:06.55#ibcon#read 3, iclass 38, count 0 2006.201.04:53:06.55#ibcon#about to read 4, iclass 38, count 0 2006.201.04:53:06.55#ibcon#read 4, iclass 38, count 0 2006.201.04:53:06.55#ibcon#about to read 5, iclass 38, count 0 2006.201.04:53:06.55#ibcon#read 5, iclass 38, count 0 2006.201.04:53:06.55#ibcon#about to read 6, iclass 38, count 0 2006.201.04:53:06.55#ibcon#read 6, iclass 38, count 0 2006.201.04:53:06.55#ibcon#end of sib2, iclass 38, count 0 2006.201.04:53:06.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.04:53:06.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.04:53:06.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:53:06.55#ibcon#*before write, iclass 38, count 0 2006.201.04:53:06.55#ibcon#enter sib2, iclass 38, count 0 2006.201.04:53:06.55#ibcon#flushed, iclass 38, count 0 2006.201.04:53:06.55#ibcon#about to write, iclass 38, count 0 2006.201.04:53:06.55#ibcon#wrote, iclass 38, count 0 2006.201.04:53:06.55#ibcon#about to read 3, iclass 38, count 0 2006.201.04:53:06.59#ibcon#read 3, iclass 38, count 0 2006.201.04:53:06.59#ibcon#about to read 4, iclass 38, count 0 2006.201.04:53:06.59#ibcon#read 4, iclass 38, count 0 2006.201.04:53:06.59#ibcon#about to read 5, iclass 38, count 0 2006.201.04:53:06.59#ibcon#read 5, iclass 38, count 0 2006.201.04:53:06.64#ibcon#about to read 6, iclass 38, count 0 2006.201.04:53:06.64#ibcon#read 6, iclass 38, count 0 2006.201.04:53:06.64#ibcon#end of sib2, iclass 38, count 0 2006.201.04:53:06.64#ibcon#*after write, iclass 38, count 0 2006.201.04:53:06.64#ibcon#*before return 0, iclass 38, count 0 2006.201.04:53:06.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:06.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:06.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.04:53:06.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.04:53:06.64$vck44/va=8,4 2006.201.04:53:06.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.04:53:06.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.04:53:06.64#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:06.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.04:53:06.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.04:53:06.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.04:53:06.65#ibcon#enter wrdev, iclass 40, count 2 2006.201.04:53:06.65#ibcon#first serial, iclass 40, count 2 2006.201.04:53:06.65#ibcon#enter sib2, iclass 40, count 2 2006.201.04:53:06.65#ibcon#flushed, iclass 40, count 2 2006.201.04:53:06.65#ibcon#about to write, iclass 40, count 2 2006.201.04:53:06.65#ibcon#wrote, iclass 40, count 2 2006.201.04:53:06.65#ibcon#about to read 3, iclass 40, count 2 2006.201.04:53:06.67#ibcon#read 3, iclass 40, count 2 2006.201.04:53:06.67#ibcon#about to read 4, iclass 40, count 2 2006.201.04:53:06.67#ibcon#read 4, iclass 40, count 2 2006.201.04:53:06.67#ibcon#about to read 5, iclass 40, count 2 2006.201.04:53:06.67#ibcon#read 5, iclass 40, count 2 2006.201.04:53:06.67#ibcon#about to read 6, iclass 40, count 2 2006.201.04:53:06.67#ibcon#read 6, iclass 40, count 2 2006.201.04:53:06.67#ibcon#end of sib2, iclass 40, count 2 2006.201.04:53:06.67#ibcon#*mode == 0, iclass 40, count 2 2006.201.04:53:06.67#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.04:53:06.67#ibcon#[25=AT08-04\r\n] 2006.201.04:53:06.67#ibcon#*before write, iclass 40, count 2 2006.201.04:53:06.67#ibcon#enter sib2, iclass 40, count 2 2006.201.04:53:06.67#ibcon#flushed, iclass 40, count 2 2006.201.04:53:06.67#ibcon#about to write, iclass 40, count 2 2006.201.04:53:06.67#ibcon#wrote, iclass 40, count 2 2006.201.04:53:06.67#ibcon#about to read 3, iclass 40, count 2 2006.201.04:53:06.70#ibcon#read 3, iclass 40, count 2 2006.201.04:53:06.70#ibcon#about to read 4, iclass 40, count 2 2006.201.04:53:06.70#ibcon#read 4, iclass 40, count 2 2006.201.04:53:06.70#ibcon#about to read 5, iclass 40, count 2 2006.201.04:53:06.70#ibcon#read 5, iclass 40, count 2 2006.201.04:53:06.70#ibcon#about to read 6, iclass 40, count 2 2006.201.04:53:06.70#ibcon#read 6, iclass 40, count 2 2006.201.04:53:06.70#ibcon#end of sib2, iclass 40, count 2 2006.201.04:53:06.70#ibcon#*after write, iclass 40, count 2 2006.201.04:53:06.70#ibcon#*before return 0, iclass 40, count 2 2006.201.04:53:06.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.04:53:06.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.04:53:06.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.04:53:06.70#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:06.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.04:53:06.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.04:53:06.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.04:53:06.82#ibcon#enter wrdev, iclass 40, count 0 2006.201.04:53:06.82#ibcon#first serial, iclass 40, count 0 2006.201.04:53:06.82#ibcon#enter sib2, iclass 40, count 0 2006.201.04:53:06.82#ibcon#flushed, iclass 40, count 0 2006.201.04:53:06.82#ibcon#about to write, iclass 40, count 0 2006.201.04:53:06.82#ibcon#wrote, iclass 40, count 0 2006.201.04:53:06.82#ibcon#about to read 3, iclass 40, count 0 2006.201.04:53:06.84#ibcon#read 3, iclass 40, count 0 2006.201.04:53:06.84#ibcon#about to read 4, iclass 40, count 0 2006.201.04:53:06.84#ibcon#read 4, iclass 40, count 0 2006.201.04:53:06.84#ibcon#about to read 5, iclass 40, count 0 2006.201.04:53:06.84#ibcon#read 5, iclass 40, count 0 2006.201.04:53:06.84#ibcon#about to read 6, iclass 40, count 0 2006.201.04:53:06.84#ibcon#read 6, iclass 40, count 0 2006.201.04:53:06.84#ibcon#end of sib2, iclass 40, count 0 2006.201.04:53:06.84#ibcon#*mode == 0, iclass 40, count 0 2006.201.04:53:06.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.04:53:06.84#ibcon#[25=USB\r\n] 2006.201.04:53:06.84#ibcon#*before write, iclass 40, count 0 2006.201.04:53:06.84#ibcon#enter sib2, iclass 40, count 0 2006.201.04:53:06.84#ibcon#flushed, iclass 40, count 0 2006.201.04:53:06.84#ibcon#about to write, iclass 40, count 0 2006.201.04:53:06.84#ibcon#wrote, iclass 40, count 0 2006.201.04:53:06.84#ibcon#about to read 3, iclass 40, count 0 2006.201.04:53:06.87#ibcon#read 3, iclass 40, count 0 2006.201.04:53:06.87#ibcon#about to read 4, iclass 40, count 0 2006.201.04:53:06.87#ibcon#read 4, iclass 40, count 0 2006.201.04:53:06.87#ibcon#about to read 5, iclass 40, count 0 2006.201.04:53:06.87#ibcon#read 5, iclass 40, count 0 2006.201.04:53:06.87#ibcon#about to read 6, iclass 40, count 0 2006.201.04:53:06.87#ibcon#read 6, iclass 40, count 0 2006.201.04:53:06.87#ibcon#end of sib2, iclass 40, count 0 2006.201.04:53:06.87#ibcon#*after write, iclass 40, count 0 2006.201.04:53:06.87#ibcon#*before return 0, iclass 40, count 0 2006.201.04:53:06.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.04:53:06.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.04:53:06.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.04:53:06.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.04:53:06.87$vck44/vblo=1,629.99 2006.201.04:53:06.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.04:53:06.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.04:53:06.87#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:06.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:53:06.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:53:06.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:53:06.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.04:53:06.87#ibcon#first serial, iclass 4, count 0 2006.201.04:53:06.87#ibcon#enter sib2, iclass 4, count 0 2006.201.04:53:06.87#ibcon#flushed, iclass 4, count 0 2006.201.04:53:06.87#ibcon#about to write, iclass 4, count 0 2006.201.04:53:06.87#ibcon#wrote, iclass 4, count 0 2006.201.04:53:06.87#ibcon#about to read 3, iclass 4, count 0 2006.201.04:53:06.89#ibcon#read 3, iclass 4, count 0 2006.201.04:53:06.89#ibcon#about to read 4, iclass 4, count 0 2006.201.04:53:06.89#ibcon#read 4, iclass 4, count 0 2006.201.04:53:06.89#ibcon#about to read 5, iclass 4, count 0 2006.201.04:53:06.89#ibcon#read 5, iclass 4, count 0 2006.201.04:53:06.89#ibcon#about to read 6, iclass 4, count 0 2006.201.04:53:06.89#ibcon#read 6, iclass 4, count 0 2006.201.04:53:06.89#ibcon#end of sib2, iclass 4, count 0 2006.201.04:53:06.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.04:53:06.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.04:53:06.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:53:06.89#ibcon#*before write, iclass 4, count 0 2006.201.04:53:06.89#ibcon#enter sib2, iclass 4, count 0 2006.201.04:53:06.89#ibcon#flushed, iclass 4, count 0 2006.201.04:53:06.89#ibcon#about to write, iclass 4, count 0 2006.201.04:53:06.89#ibcon#wrote, iclass 4, count 0 2006.201.04:53:06.89#ibcon#about to read 3, iclass 4, count 0 2006.201.04:53:06.93#ibcon#read 3, iclass 4, count 0 2006.201.04:53:06.93#ibcon#about to read 4, iclass 4, count 0 2006.201.04:53:06.93#ibcon#read 4, iclass 4, count 0 2006.201.04:53:06.93#ibcon#about to read 5, iclass 4, count 0 2006.201.04:53:06.93#ibcon#read 5, iclass 4, count 0 2006.201.04:53:06.93#ibcon#about to read 6, iclass 4, count 0 2006.201.04:53:06.93#ibcon#read 6, iclass 4, count 0 2006.201.04:53:06.93#ibcon#end of sib2, iclass 4, count 0 2006.201.04:53:06.93#ibcon#*after write, iclass 4, count 0 2006.201.04:53:06.93#ibcon#*before return 0, iclass 4, count 0 2006.201.04:53:06.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:53:06.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.04:53:06.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.04:53:06.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.04:53:06.93$vck44/vb=1,4 2006.201.04:53:06.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.04:53:06.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.04:53:06.93#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:06.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.04:53:06.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.04:53:06.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.04:53:06.93#ibcon#enter wrdev, iclass 6, count 2 2006.201.04:53:06.93#ibcon#first serial, iclass 6, count 2 2006.201.04:53:06.93#ibcon#enter sib2, iclass 6, count 2 2006.201.04:53:06.93#ibcon#flushed, iclass 6, count 2 2006.201.04:53:06.93#ibcon#about to write, iclass 6, count 2 2006.201.04:53:06.93#ibcon#wrote, iclass 6, count 2 2006.201.04:53:06.93#ibcon#about to read 3, iclass 6, count 2 2006.201.04:53:06.95#ibcon#read 3, iclass 6, count 2 2006.201.04:53:06.95#ibcon#about to read 4, iclass 6, count 2 2006.201.04:53:06.95#ibcon#read 4, iclass 6, count 2 2006.201.04:53:06.95#ibcon#about to read 5, iclass 6, count 2 2006.201.04:53:06.95#ibcon#read 5, iclass 6, count 2 2006.201.04:53:06.95#ibcon#about to read 6, iclass 6, count 2 2006.201.04:53:06.95#ibcon#read 6, iclass 6, count 2 2006.201.04:53:06.95#ibcon#end of sib2, iclass 6, count 2 2006.201.04:53:06.95#ibcon#*mode == 0, iclass 6, count 2 2006.201.04:53:06.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.04:53:06.95#ibcon#[27=AT01-04\r\n] 2006.201.04:53:06.95#ibcon#*before write, iclass 6, count 2 2006.201.04:53:06.95#ibcon#enter sib2, iclass 6, count 2 2006.201.04:53:06.95#ibcon#flushed, iclass 6, count 2 2006.201.04:53:06.95#ibcon#about to write, iclass 6, count 2 2006.201.04:53:06.95#ibcon#wrote, iclass 6, count 2 2006.201.04:53:06.95#ibcon#about to read 3, iclass 6, count 2 2006.201.04:53:06.98#ibcon#read 3, iclass 6, count 2 2006.201.04:53:06.98#ibcon#about to read 4, iclass 6, count 2 2006.201.04:53:06.98#ibcon#read 4, iclass 6, count 2 2006.201.04:53:06.98#ibcon#about to read 5, iclass 6, count 2 2006.201.04:53:06.98#ibcon#read 5, iclass 6, count 2 2006.201.04:53:06.98#ibcon#about to read 6, iclass 6, count 2 2006.201.04:53:06.98#ibcon#read 6, iclass 6, count 2 2006.201.04:53:06.98#ibcon#end of sib2, iclass 6, count 2 2006.201.04:53:06.98#ibcon#*after write, iclass 6, count 2 2006.201.04:53:06.98#ibcon#*before return 0, iclass 6, count 2 2006.201.04:53:06.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.04:53:06.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.04:53:06.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.04:53:06.98#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:06.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.04:53:07.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.04:53:07.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.04:53:07.10#ibcon#enter wrdev, iclass 6, count 0 2006.201.04:53:07.10#ibcon#first serial, iclass 6, count 0 2006.201.04:53:07.10#ibcon#enter sib2, iclass 6, count 0 2006.201.04:53:07.10#ibcon#flushed, iclass 6, count 0 2006.201.04:53:07.10#ibcon#about to write, iclass 6, count 0 2006.201.04:53:07.10#ibcon#wrote, iclass 6, count 0 2006.201.04:53:07.10#ibcon#about to read 3, iclass 6, count 0 2006.201.04:53:07.12#ibcon#read 3, iclass 6, count 0 2006.201.04:53:07.12#ibcon#about to read 4, iclass 6, count 0 2006.201.04:53:07.12#ibcon#read 4, iclass 6, count 0 2006.201.04:53:07.12#ibcon#about to read 5, iclass 6, count 0 2006.201.04:53:07.12#ibcon#read 5, iclass 6, count 0 2006.201.04:53:07.12#ibcon#about to read 6, iclass 6, count 0 2006.201.04:53:07.12#ibcon#read 6, iclass 6, count 0 2006.201.04:53:07.12#ibcon#end of sib2, iclass 6, count 0 2006.201.04:53:07.12#ibcon#*mode == 0, iclass 6, count 0 2006.201.04:53:07.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.04:53:07.12#ibcon#[27=USB\r\n] 2006.201.04:53:07.12#ibcon#*before write, iclass 6, count 0 2006.201.04:53:07.12#ibcon#enter sib2, iclass 6, count 0 2006.201.04:53:07.12#ibcon#flushed, iclass 6, count 0 2006.201.04:53:07.12#ibcon#about to write, iclass 6, count 0 2006.201.04:53:07.12#ibcon#wrote, iclass 6, count 0 2006.201.04:53:07.12#ibcon#about to read 3, iclass 6, count 0 2006.201.04:53:07.15#ibcon#read 3, iclass 6, count 0 2006.201.04:53:07.15#ibcon#about to read 4, iclass 6, count 0 2006.201.04:53:07.15#ibcon#read 4, iclass 6, count 0 2006.201.04:53:07.15#ibcon#about to read 5, iclass 6, count 0 2006.201.04:53:07.15#ibcon#read 5, iclass 6, count 0 2006.201.04:53:07.15#ibcon#about to read 6, iclass 6, count 0 2006.201.04:53:07.15#ibcon#read 6, iclass 6, count 0 2006.201.04:53:07.15#ibcon#end of sib2, iclass 6, count 0 2006.201.04:53:07.15#ibcon#*after write, iclass 6, count 0 2006.201.04:53:07.15#ibcon#*before return 0, iclass 6, count 0 2006.201.04:53:07.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.04:53:07.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.04:53:07.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.04:53:07.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.04:53:07.15$vck44/vblo=2,634.99 2006.201.04:53:07.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.04:53:07.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.04:53:07.15#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:07.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:07.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:07.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:07.15#ibcon#enter wrdev, iclass 10, count 0 2006.201.04:53:07.15#ibcon#first serial, iclass 10, count 0 2006.201.04:53:07.15#ibcon#enter sib2, iclass 10, count 0 2006.201.04:53:07.15#ibcon#flushed, iclass 10, count 0 2006.201.04:53:07.15#ibcon#about to write, iclass 10, count 0 2006.201.04:53:07.15#ibcon#wrote, iclass 10, count 0 2006.201.04:53:07.15#ibcon#about to read 3, iclass 10, count 0 2006.201.04:53:07.17#ibcon#read 3, iclass 10, count 0 2006.201.04:53:07.17#ibcon#about to read 4, iclass 10, count 0 2006.201.04:53:07.17#ibcon#read 4, iclass 10, count 0 2006.201.04:53:07.17#ibcon#about to read 5, iclass 10, count 0 2006.201.04:53:07.17#ibcon#read 5, iclass 10, count 0 2006.201.04:53:07.17#ibcon#about to read 6, iclass 10, count 0 2006.201.04:53:07.17#ibcon#read 6, iclass 10, count 0 2006.201.04:53:07.17#ibcon#end of sib2, iclass 10, count 0 2006.201.04:53:07.17#ibcon#*mode == 0, iclass 10, count 0 2006.201.04:53:07.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.04:53:07.17#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:53:07.17#ibcon#*before write, iclass 10, count 0 2006.201.04:53:07.17#ibcon#enter sib2, iclass 10, count 0 2006.201.04:53:07.17#ibcon#flushed, iclass 10, count 0 2006.201.04:53:07.17#ibcon#about to write, iclass 10, count 0 2006.201.04:53:07.17#ibcon#wrote, iclass 10, count 0 2006.201.04:53:07.17#ibcon#about to read 3, iclass 10, count 0 2006.201.04:53:07.21#ibcon#read 3, iclass 10, count 0 2006.201.04:53:07.21#ibcon#about to read 4, iclass 10, count 0 2006.201.04:53:07.21#ibcon#read 4, iclass 10, count 0 2006.201.04:53:07.21#ibcon#about to read 5, iclass 10, count 0 2006.201.04:53:07.21#ibcon#read 5, iclass 10, count 0 2006.201.04:53:07.21#ibcon#about to read 6, iclass 10, count 0 2006.201.04:53:07.21#ibcon#read 6, iclass 10, count 0 2006.201.04:53:07.21#ibcon#end of sib2, iclass 10, count 0 2006.201.04:53:07.21#ibcon#*after write, iclass 10, count 0 2006.201.04:53:07.21#ibcon#*before return 0, iclass 10, count 0 2006.201.04:53:07.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:07.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.04:53:07.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.04:53:07.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.04:53:07.21$vck44/vb=2,5 2006.201.04:53:07.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.04:53:07.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.04:53:07.21#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:07.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:07.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:07.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:07.27#ibcon#enter wrdev, iclass 12, count 2 2006.201.04:53:07.27#ibcon#first serial, iclass 12, count 2 2006.201.04:53:07.27#ibcon#enter sib2, iclass 12, count 2 2006.201.04:53:07.27#ibcon#flushed, iclass 12, count 2 2006.201.04:53:07.27#ibcon#about to write, iclass 12, count 2 2006.201.04:53:07.27#ibcon#wrote, iclass 12, count 2 2006.201.04:53:07.27#ibcon#about to read 3, iclass 12, count 2 2006.201.04:53:07.29#ibcon#read 3, iclass 12, count 2 2006.201.04:53:07.29#ibcon#about to read 4, iclass 12, count 2 2006.201.04:53:07.29#ibcon#read 4, iclass 12, count 2 2006.201.04:53:07.29#ibcon#about to read 5, iclass 12, count 2 2006.201.04:53:07.29#ibcon#read 5, iclass 12, count 2 2006.201.04:53:07.29#ibcon#about to read 6, iclass 12, count 2 2006.201.04:53:07.29#ibcon#read 6, iclass 12, count 2 2006.201.04:53:07.29#ibcon#end of sib2, iclass 12, count 2 2006.201.04:53:07.29#ibcon#*mode == 0, iclass 12, count 2 2006.201.04:53:07.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.04:53:07.29#ibcon#[27=AT02-05\r\n] 2006.201.04:53:07.29#ibcon#*before write, iclass 12, count 2 2006.201.04:53:07.29#ibcon#enter sib2, iclass 12, count 2 2006.201.04:53:07.29#ibcon#flushed, iclass 12, count 2 2006.201.04:53:07.29#ibcon#about to write, iclass 12, count 2 2006.201.04:53:07.29#ibcon#wrote, iclass 12, count 2 2006.201.04:53:07.29#ibcon#about to read 3, iclass 12, count 2 2006.201.04:53:07.32#ibcon#read 3, iclass 12, count 2 2006.201.04:53:07.32#ibcon#about to read 4, iclass 12, count 2 2006.201.04:53:07.32#ibcon#read 4, iclass 12, count 2 2006.201.04:53:07.32#ibcon#about to read 5, iclass 12, count 2 2006.201.04:53:07.32#ibcon#read 5, iclass 12, count 2 2006.201.04:53:07.32#ibcon#about to read 6, iclass 12, count 2 2006.201.04:53:07.32#ibcon#read 6, iclass 12, count 2 2006.201.04:53:07.32#ibcon#end of sib2, iclass 12, count 2 2006.201.04:53:07.32#ibcon#*after write, iclass 12, count 2 2006.201.04:53:07.32#ibcon#*before return 0, iclass 12, count 2 2006.201.04:53:07.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:07.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.04:53:07.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.04:53:07.32#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:07.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:07.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:07.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:07.44#ibcon#enter wrdev, iclass 12, count 0 2006.201.04:53:07.44#ibcon#first serial, iclass 12, count 0 2006.201.04:53:07.44#ibcon#enter sib2, iclass 12, count 0 2006.201.04:53:07.44#ibcon#flushed, iclass 12, count 0 2006.201.04:53:07.44#ibcon#about to write, iclass 12, count 0 2006.201.04:53:07.44#ibcon#wrote, iclass 12, count 0 2006.201.04:53:07.44#ibcon#about to read 3, iclass 12, count 0 2006.201.04:53:07.46#ibcon#read 3, iclass 12, count 0 2006.201.04:53:07.46#ibcon#about to read 4, iclass 12, count 0 2006.201.04:53:07.46#ibcon#read 4, iclass 12, count 0 2006.201.04:53:07.46#ibcon#about to read 5, iclass 12, count 0 2006.201.04:53:07.46#ibcon#read 5, iclass 12, count 0 2006.201.04:53:07.46#ibcon#about to read 6, iclass 12, count 0 2006.201.04:53:07.46#ibcon#read 6, iclass 12, count 0 2006.201.04:53:07.46#ibcon#end of sib2, iclass 12, count 0 2006.201.04:53:07.46#ibcon#*mode == 0, iclass 12, count 0 2006.201.04:53:07.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.04:53:07.46#ibcon#[27=USB\r\n] 2006.201.04:53:07.46#ibcon#*before write, iclass 12, count 0 2006.201.04:53:07.46#ibcon#enter sib2, iclass 12, count 0 2006.201.04:53:07.46#ibcon#flushed, iclass 12, count 0 2006.201.04:53:07.46#ibcon#about to write, iclass 12, count 0 2006.201.04:53:07.46#ibcon#wrote, iclass 12, count 0 2006.201.04:53:07.46#ibcon#about to read 3, iclass 12, count 0 2006.201.04:53:07.49#ibcon#read 3, iclass 12, count 0 2006.201.04:53:07.49#ibcon#about to read 4, iclass 12, count 0 2006.201.04:53:07.49#ibcon#read 4, iclass 12, count 0 2006.201.04:53:07.49#ibcon#about to read 5, iclass 12, count 0 2006.201.04:53:07.49#ibcon#read 5, iclass 12, count 0 2006.201.04:53:07.49#ibcon#about to read 6, iclass 12, count 0 2006.201.04:53:07.49#ibcon#read 6, iclass 12, count 0 2006.201.04:53:07.49#ibcon#end of sib2, iclass 12, count 0 2006.201.04:53:07.49#ibcon#*after write, iclass 12, count 0 2006.201.04:53:07.49#ibcon#*before return 0, iclass 12, count 0 2006.201.04:53:07.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:07.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.04:53:07.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.04:53:07.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.04:53:07.49$vck44/vblo=3,649.99 2006.201.04:53:07.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.04:53:07.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.04:53:07.49#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:07.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:07.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:07.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:07.49#ibcon#enter wrdev, iclass 14, count 0 2006.201.04:53:07.49#ibcon#first serial, iclass 14, count 0 2006.201.04:53:07.49#ibcon#enter sib2, iclass 14, count 0 2006.201.04:53:07.49#ibcon#flushed, iclass 14, count 0 2006.201.04:53:07.49#ibcon#about to write, iclass 14, count 0 2006.201.04:53:07.49#ibcon#wrote, iclass 14, count 0 2006.201.04:53:07.49#ibcon#about to read 3, iclass 14, count 0 2006.201.04:53:07.51#ibcon#read 3, iclass 14, count 0 2006.201.04:53:07.51#ibcon#about to read 4, iclass 14, count 0 2006.201.04:53:07.51#ibcon#read 4, iclass 14, count 0 2006.201.04:53:07.51#ibcon#about to read 5, iclass 14, count 0 2006.201.04:53:07.51#ibcon#read 5, iclass 14, count 0 2006.201.04:53:07.51#ibcon#about to read 6, iclass 14, count 0 2006.201.04:53:07.51#ibcon#read 6, iclass 14, count 0 2006.201.04:53:07.51#ibcon#end of sib2, iclass 14, count 0 2006.201.04:53:07.51#ibcon#*mode == 0, iclass 14, count 0 2006.201.04:53:07.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.04:53:07.51#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:53:07.51#ibcon#*before write, iclass 14, count 0 2006.201.04:53:07.51#ibcon#enter sib2, iclass 14, count 0 2006.201.04:53:07.51#ibcon#flushed, iclass 14, count 0 2006.201.04:53:07.51#ibcon#about to write, iclass 14, count 0 2006.201.04:53:07.51#ibcon#wrote, iclass 14, count 0 2006.201.04:53:07.51#ibcon#about to read 3, iclass 14, count 0 2006.201.04:53:07.55#ibcon#read 3, iclass 14, count 0 2006.201.04:53:07.55#ibcon#about to read 4, iclass 14, count 0 2006.201.04:53:07.55#ibcon#read 4, iclass 14, count 0 2006.201.04:53:07.55#ibcon#about to read 5, iclass 14, count 0 2006.201.04:53:07.55#ibcon#read 5, iclass 14, count 0 2006.201.04:53:07.55#ibcon#about to read 6, iclass 14, count 0 2006.201.04:53:07.55#ibcon#read 6, iclass 14, count 0 2006.201.04:53:07.55#ibcon#end of sib2, iclass 14, count 0 2006.201.04:53:07.55#ibcon#*after write, iclass 14, count 0 2006.201.04:53:07.55#ibcon#*before return 0, iclass 14, count 0 2006.201.04:53:07.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:07.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.04:53:07.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.04:53:07.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.04:53:07.55$vck44/vb=3,4 2006.201.04:53:07.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.04:53:07.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.04:53:07.55#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:07.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:07.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:07.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:07.61#ibcon#enter wrdev, iclass 16, count 2 2006.201.04:53:07.61#ibcon#first serial, iclass 16, count 2 2006.201.04:53:07.61#ibcon#enter sib2, iclass 16, count 2 2006.201.04:53:07.61#ibcon#flushed, iclass 16, count 2 2006.201.04:53:07.61#ibcon#about to write, iclass 16, count 2 2006.201.04:53:07.61#ibcon#wrote, iclass 16, count 2 2006.201.04:53:07.61#ibcon#about to read 3, iclass 16, count 2 2006.201.04:53:07.63#ibcon#read 3, iclass 16, count 2 2006.201.04:53:07.63#ibcon#about to read 4, iclass 16, count 2 2006.201.04:53:07.63#ibcon#read 4, iclass 16, count 2 2006.201.04:53:07.63#ibcon#about to read 5, iclass 16, count 2 2006.201.04:53:07.63#ibcon#read 5, iclass 16, count 2 2006.201.04:53:07.63#ibcon#about to read 6, iclass 16, count 2 2006.201.04:53:07.63#ibcon#read 6, iclass 16, count 2 2006.201.04:53:07.63#ibcon#end of sib2, iclass 16, count 2 2006.201.04:53:07.63#ibcon#*mode == 0, iclass 16, count 2 2006.201.04:53:07.63#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.04:53:07.63#ibcon#[27=AT03-04\r\n] 2006.201.04:53:07.63#ibcon#*before write, iclass 16, count 2 2006.201.04:53:07.63#ibcon#enter sib2, iclass 16, count 2 2006.201.04:53:07.63#ibcon#flushed, iclass 16, count 2 2006.201.04:53:07.63#ibcon#about to write, iclass 16, count 2 2006.201.04:53:07.63#ibcon#wrote, iclass 16, count 2 2006.201.04:53:07.63#ibcon#about to read 3, iclass 16, count 2 2006.201.04:53:07.66#ibcon#read 3, iclass 16, count 2 2006.201.04:53:07.66#ibcon#about to read 4, iclass 16, count 2 2006.201.04:53:07.66#ibcon#read 4, iclass 16, count 2 2006.201.04:53:07.71#ibcon#about to read 5, iclass 16, count 2 2006.201.04:53:07.71#ibcon#read 5, iclass 16, count 2 2006.201.04:53:07.71#ibcon#about to read 6, iclass 16, count 2 2006.201.04:53:07.71#ibcon#read 6, iclass 16, count 2 2006.201.04:53:07.71#ibcon#end of sib2, iclass 16, count 2 2006.201.04:53:07.71#ibcon#*after write, iclass 16, count 2 2006.201.04:53:07.71#ibcon#*before return 0, iclass 16, count 2 2006.201.04:53:07.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:07.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.04:53:07.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.04:53:07.71#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:07.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:07.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:07.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:07.83#ibcon#enter wrdev, iclass 16, count 0 2006.201.04:53:07.83#ibcon#first serial, iclass 16, count 0 2006.201.04:53:07.83#ibcon#enter sib2, iclass 16, count 0 2006.201.04:53:07.83#ibcon#flushed, iclass 16, count 0 2006.201.04:53:07.83#ibcon#about to write, iclass 16, count 0 2006.201.04:53:07.83#ibcon#wrote, iclass 16, count 0 2006.201.04:53:07.83#ibcon#about to read 3, iclass 16, count 0 2006.201.04:53:07.85#ibcon#read 3, iclass 16, count 0 2006.201.04:53:07.85#ibcon#about to read 4, iclass 16, count 0 2006.201.04:53:07.85#ibcon#read 4, iclass 16, count 0 2006.201.04:53:07.85#ibcon#about to read 5, iclass 16, count 0 2006.201.04:53:07.85#ibcon#read 5, iclass 16, count 0 2006.201.04:53:07.85#ibcon#about to read 6, iclass 16, count 0 2006.201.04:53:07.85#ibcon#read 6, iclass 16, count 0 2006.201.04:53:07.85#ibcon#end of sib2, iclass 16, count 0 2006.201.04:53:07.85#ibcon#*mode == 0, iclass 16, count 0 2006.201.04:53:07.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.04:53:07.85#ibcon#[27=USB\r\n] 2006.201.04:53:07.85#ibcon#*before write, iclass 16, count 0 2006.201.04:53:07.85#ibcon#enter sib2, iclass 16, count 0 2006.201.04:53:07.85#ibcon#flushed, iclass 16, count 0 2006.201.04:53:07.85#ibcon#about to write, iclass 16, count 0 2006.201.04:53:07.85#ibcon#wrote, iclass 16, count 0 2006.201.04:53:07.85#ibcon#about to read 3, iclass 16, count 0 2006.201.04:53:07.88#ibcon#read 3, iclass 16, count 0 2006.201.04:53:07.88#ibcon#about to read 4, iclass 16, count 0 2006.201.04:53:07.88#ibcon#read 4, iclass 16, count 0 2006.201.04:53:07.88#ibcon#about to read 5, iclass 16, count 0 2006.201.04:53:07.88#ibcon#read 5, iclass 16, count 0 2006.201.04:53:07.88#ibcon#about to read 6, iclass 16, count 0 2006.201.04:53:07.88#ibcon#read 6, iclass 16, count 0 2006.201.04:53:07.88#ibcon#end of sib2, iclass 16, count 0 2006.201.04:53:07.88#ibcon#*after write, iclass 16, count 0 2006.201.04:53:07.88#ibcon#*before return 0, iclass 16, count 0 2006.201.04:53:07.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:07.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.04:53:07.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.04:53:07.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.04:53:07.88$vck44/vblo=4,679.99 2006.201.04:53:07.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.04:53:07.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.04:53:07.88#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:07.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:07.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:07.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:07.88#ibcon#enter wrdev, iclass 18, count 0 2006.201.04:53:07.88#ibcon#first serial, iclass 18, count 0 2006.201.04:53:07.88#ibcon#enter sib2, iclass 18, count 0 2006.201.04:53:07.88#ibcon#flushed, iclass 18, count 0 2006.201.04:53:07.88#ibcon#about to write, iclass 18, count 0 2006.201.04:53:07.88#ibcon#wrote, iclass 18, count 0 2006.201.04:53:07.88#ibcon#about to read 3, iclass 18, count 0 2006.201.04:53:07.90#ibcon#read 3, iclass 18, count 0 2006.201.04:53:07.90#ibcon#about to read 4, iclass 18, count 0 2006.201.04:53:07.90#ibcon#read 4, iclass 18, count 0 2006.201.04:53:07.90#ibcon#about to read 5, iclass 18, count 0 2006.201.04:53:07.90#ibcon#read 5, iclass 18, count 0 2006.201.04:53:07.90#ibcon#about to read 6, iclass 18, count 0 2006.201.04:53:07.90#ibcon#read 6, iclass 18, count 0 2006.201.04:53:07.90#ibcon#end of sib2, iclass 18, count 0 2006.201.04:53:07.90#ibcon#*mode == 0, iclass 18, count 0 2006.201.04:53:07.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.04:53:07.90#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:53:07.90#ibcon#*before write, iclass 18, count 0 2006.201.04:53:07.90#ibcon#enter sib2, iclass 18, count 0 2006.201.04:53:07.90#ibcon#flushed, iclass 18, count 0 2006.201.04:53:07.90#ibcon#about to write, iclass 18, count 0 2006.201.04:53:07.90#ibcon#wrote, iclass 18, count 0 2006.201.04:53:07.90#ibcon#about to read 3, iclass 18, count 0 2006.201.04:53:07.94#ibcon#read 3, iclass 18, count 0 2006.201.04:53:07.94#ibcon#about to read 4, iclass 18, count 0 2006.201.04:53:07.94#ibcon#read 4, iclass 18, count 0 2006.201.04:53:07.94#ibcon#about to read 5, iclass 18, count 0 2006.201.04:53:07.94#ibcon#read 5, iclass 18, count 0 2006.201.04:53:07.94#ibcon#about to read 6, iclass 18, count 0 2006.201.04:53:07.94#ibcon#read 6, iclass 18, count 0 2006.201.04:53:07.94#ibcon#end of sib2, iclass 18, count 0 2006.201.04:53:07.94#ibcon#*after write, iclass 18, count 0 2006.201.04:53:07.94#ibcon#*before return 0, iclass 18, count 0 2006.201.04:53:07.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:07.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.04:53:07.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.04:53:07.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.04:53:07.94$vck44/vb=4,5 2006.201.04:53:07.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.04:53:07.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.04:53:07.94#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:07.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:08.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:08.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:08.00#ibcon#enter wrdev, iclass 20, count 2 2006.201.04:53:08.00#ibcon#first serial, iclass 20, count 2 2006.201.04:53:08.00#ibcon#enter sib2, iclass 20, count 2 2006.201.04:53:08.00#ibcon#flushed, iclass 20, count 2 2006.201.04:53:08.00#ibcon#about to write, iclass 20, count 2 2006.201.04:53:08.00#ibcon#wrote, iclass 20, count 2 2006.201.04:53:08.00#ibcon#about to read 3, iclass 20, count 2 2006.201.04:53:08.02#ibcon#read 3, iclass 20, count 2 2006.201.04:53:08.02#ibcon#about to read 4, iclass 20, count 2 2006.201.04:53:08.02#ibcon#read 4, iclass 20, count 2 2006.201.04:53:08.02#ibcon#about to read 5, iclass 20, count 2 2006.201.04:53:08.02#ibcon#read 5, iclass 20, count 2 2006.201.04:53:08.02#ibcon#about to read 6, iclass 20, count 2 2006.201.04:53:08.02#ibcon#read 6, iclass 20, count 2 2006.201.04:53:08.02#ibcon#end of sib2, iclass 20, count 2 2006.201.04:53:08.02#ibcon#*mode == 0, iclass 20, count 2 2006.201.04:53:08.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.04:53:08.02#ibcon#[27=AT04-05\r\n] 2006.201.04:53:08.02#ibcon#*before write, iclass 20, count 2 2006.201.04:53:08.02#ibcon#enter sib2, iclass 20, count 2 2006.201.04:53:08.02#ibcon#flushed, iclass 20, count 2 2006.201.04:53:08.02#ibcon#about to write, iclass 20, count 2 2006.201.04:53:08.02#ibcon#wrote, iclass 20, count 2 2006.201.04:53:08.02#ibcon#about to read 3, iclass 20, count 2 2006.201.04:53:08.05#ibcon#read 3, iclass 20, count 2 2006.201.04:53:08.05#ibcon#about to read 4, iclass 20, count 2 2006.201.04:53:08.05#ibcon#read 4, iclass 20, count 2 2006.201.04:53:08.05#ibcon#about to read 5, iclass 20, count 2 2006.201.04:53:08.05#ibcon#read 5, iclass 20, count 2 2006.201.04:53:08.05#ibcon#about to read 6, iclass 20, count 2 2006.201.04:53:08.05#ibcon#read 6, iclass 20, count 2 2006.201.04:53:08.05#ibcon#end of sib2, iclass 20, count 2 2006.201.04:53:08.05#ibcon#*after write, iclass 20, count 2 2006.201.04:53:08.05#ibcon#*before return 0, iclass 20, count 2 2006.201.04:53:08.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:08.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.04:53:08.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.04:53:08.05#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:08.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:08.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:08.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:08.17#ibcon#enter wrdev, iclass 20, count 0 2006.201.04:53:08.17#ibcon#first serial, iclass 20, count 0 2006.201.04:53:08.17#ibcon#enter sib2, iclass 20, count 0 2006.201.04:53:08.17#ibcon#flushed, iclass 20, count 0 2006.201.04:53:08.17#ibcon#about to write, iclass 20, count 0 2006.201.04:53:08.17#ibcon#wrote, iclass 20, count 0 2006.201.04:53:08.17#ibcon#about to read 3, iclass 20, count 0 2006.201.04:53:08.19#ibcon#read 3, iclass 20, count 0 2006.201.04:53:08.19#ibcon#about to read 4, iclass 20, count 0 2006.201.04:53:08.19#ibcon#read 4, iclass 20, count 0 2006.201.04:53:08.19#ibcon#about to read 5, iclass 20, count 0 2006.201.04:53:08.19#ibcon#read 5, iclass 20, count 0 2006.201.04:53:08.19#ibcon#about to read 6, iclass 20, count 0 2006.201.04:53:08.19#ibcon#read 6, iclass 20, count 0 2006.201.04:53:08.19#ibcon#end of sib2, iclass 20, count 0 2006.201.04:53:08.19#ibcon#*mode == 0, iclass 20, count 0 2006.201.04:53:08.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.04:53:08.19#ibcon#[27=USB\r\n] 2006.201.04:53:08.19#ibcon#*before write, iclass 20, count 0 2006.201.04:53:08.19#ibcon#enter sib2, iclass 20, count 0 2006.201.04:53:08.19#ibcon#flushed, iclass 20, count 0 2006.201.04:53:08.19#ibcon#about to write, iclass 20, count 0 2006.201.04:53:08.19#ibcon#wrote, iclass 20, count 0 2006.201.04:53:08.19#ibcon#about to read 3, iclass 20, count 0 2006.201.04:53:08.22#ibcon#read 3, iclass 20, count 0 2006.201.04:53:08.22#ibcon#about to read 4, iclass 20, count 0 2006.201.04:53:08.22#ibcon#read 4, iclass 20, count 0 2006.201.04:53:08.22#ibcon#about to read 5, iclass 20, count 0 2006.201.04:53:08.22#ibcon#read 5, iclass 20, count 0 2006.201.04:53:08.22#ibcon#about to read 6, iclass 20, count 0 2006.201.04:53:08.22#ibcon#read 6, iclass 20, count 0 2006.201.04:53:08.22#ibcon#end of sib2, iclass 20, count 0 2006.201.04:53:08.22#ibcon#*after write, iclass 20, count 0 2006.201.04:53:08.22#ibcon#*before return 0, iclass 20, count 0 2006.201.04:53:08.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:08.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.04:53:08.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.04:53:08.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.04:53:08.22$vck44/vblo=5,709.99 2006.201.04:53:08.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.04:53:08.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.04:53:08.22#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:08.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:08.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:08.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:08.22#ibcon#enter wrdev, iclass 22, count 0 2006.201.04:53:08.22#ibcon#first serial, iclass 22, count 0 2006.201.04:53:08.22#ibcon#enter sib2, iclass 22, count 0 2006.201.04:53:08.22#ibcon#flushed, iclass 22, count 0 2006.201.04:53:08.22#ibcon#about to write, iclass 22, count 0 2006.201.04:53:08.22#ibcon#wrote, iclass 22, count 0 2006.201.04:53:08.22#ibcon#about to read 3, iclass 22, count 0 2006.201.04:53:08.24#ibcon#read 3, iclass 22, count 0 2006.201.04:53:08.24#ibcon#about to read 4, iclass 22, count 0 2006.201.04:53:08.24#ibcon#read 4, iclass 22, count 0 2006.201.04:53:08.24#ibcon#about to read 5, iclass 22, count 0 2006.201.04:53:08.24#ibcon#read 5, iclass 22, count 0 2006.201.04:53:08.24#ibcon#about to read 6, iclass 22, count 0 2006.201.04:53:08.24#ibcon#read 6, iclass 22, count 0 2006.201.04:53:08.24#ibcon#end of sib2, iclass 22, count 0 2006.201.04:53:08.24#ibcon#*mode == 0, iclass 22, count 0 2006.201.04:53:08.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.04:53:08.24#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:53:08.24#ibcon#*before write, iclass 22, count 0 2006.201.04:53:08.24#ibcon#enter sib2, iclass 22, count 0 2006.201.04:53:08.24#ibcon#flushed, iclass 22, count 0 2006.201.04:53:08.24#ibcon#about to write, iclass 22, count 0 2006.201.04:53:08.24#ibcon#wrote, iclass 22, count 0 2006.201.04:53:08.24#ibcon#about to read 3, iclass 22, count 0 2006.201.04:53:08.28#ibcon#read 3, iclass 22, count 0 2006.201.04:53:08.28#ibcon#about to read 4, iclass 22, count 0 2006.201.04:53:08.28#ibcon#read 4, iclass 22, count 0 2006.201.04:53:08.28#ibcon#about to read 5, iclass 22, count 0 2006.201.04:53:08.28#ibcon#read 5, iclass 22, count 0 2006.201.04:53:08.28#ibcon#about to read 6, iclass 22, count 0 2006.201.04:53:08.28#ibcon#read 6, iclass 22, count 0 2006.201.04:53:08.28#ibcon#end of sib2, iclass 22, count 0 2006.201.04:53:08.28#ibcon#*after write, iclass 22, count 0 2006.201.04:53:08.28#ibcon#*before return 0, iclass 22, count 0 2006.201.04:53:08.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:08.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.04:53:08.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.04:53:08.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.04:53:08.28$vck44/vb=5,4 2006.201.04:53:08.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.04:53:08.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.04:53:08.28#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:08.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:08.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:08.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:08.34#ibcon#enter wrdev, iclass 24, count 2 2006.201.04:53:08.34#ibcon#first serial, iclass 24, count 2 2006.201.04:53:08.34#ibcon#enter sib2, iclass 24, count 2 2006.201.04:53:08.34#ibcon#flushed, iclass 24, count 2 2006.201.04:53:08.34#ibcon#about to write, iclass 24, count 2 2006.201.04:53:08.34#ibcon#wrote, iclass 24, count 2 2006.201.04:53:08.34#ibcon#about to read 3, iclass 24, count 2 2006.201.04:53:08.36#ibcon#read 3, iclass 24, count 2 2006.201.04:53:08.36#ibcon#about to read 4, iclass 24, count 2 2006.201.04:53:08.36#ibcon#read 4, iclass 24, count 2 2006.201.04:53:08.36#ibcon#about to read 5, iclass 24, count 2 2006.201.04:53:08.36#ibcon#read 5, iclass 24, count 2 2006.201.04:53:08.36#ibcon#about to read 6, iclass 24, count 2 2006.201.04:53:08.36#ibcon#read 6, iclass 24, count 2 2006.201.04:53:08.36#ibcon#end of sib2, iclass 24, count 2 2006.201.04:53:08.36#ibcon#*mode == 0, iclass 24, count 2 2006.201.04:53:08.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.04:53:08.36#ibcon#[27=AT05-04\r\n] 2006.201.04:53:08.36#ibcon#*before write, iclass 24, count 2 2006.201.04:53:08.36#ibcon#enter sib2, iclass 24, count 2 2006.201.04:53:08.36#ibcon#flushed, iclass 24, count 2 2006.201.04:53:08.36#ibcon#about to write, iclass 24, count 2 2006.201.04:53:08.36#ibcon#wrote, iclass 24, count 2 2006.201.04:53:08.36#ibcon#about to read 3, iclass 24, count 2 2006.201.04:53:08.39#ibcon#read 3, iclass 24, count 2 2006.201.04:53:08.39#ibcon#about to read 4, iclass 24, count 2 2006.201.04:53:08.39#ibcon#read 4, iclass 24, count 2 2006.201.04:53:08.39#ibcon#about to read 5, iclass 24, count 2 2006.201.04:53:08.39#ibcon#read 5, iclass 24, count 2 2006.201.04:53:08.39#ibcon#about to read 6, iclass 24, count 2 2006.201.04:53:08.39#ibcon#read 6, iclass 24, count 2 2006.201.04:53:08.39#ibcon#end of sib2, iclass 24, count 2 2006.201.04:53:08.39#ibcon#*after write, iclass 24, count 2 2006.201.04:53:08.39#ibcon#*before return 0, iclass 24, count 2 2006.201.04:53:08.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:08.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.04:53:08.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.04:53:08.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:08.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:08.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:08.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:08.51#ibcon#enter wrdev, iclass 24, count 0 2006.201.04:53:08.51#ibcon#first serial, iclass 24, count 0 2006.201.04:53:08.51#ibcon#enter sib2, iclass 24, count 0 2006.201.04:53:08.51#ibcon#flushed, iclass 24, count 0 2006.201.04:53:08.51#ibcon#about to write, iclass 24, count 0 2006.201.04:53:08.51#ibcon#wrote, iclass 24, count 0 2006.201.04:53:08.51#ibcon#about to read 3, iclass 24, count 0 2006.201.04:53:08.53#ibcon#read 3, iclass 24, count 0 2006.201.04:53:08.53#ibcon#about to read 4, iclass 24, count 0 2006.201.04:53:08.53#ibcon#read 4, iclass 24, count 0 2006.201.04:53:08.53#ibcon#about to read 5, iclass 24, count 0 2006.201.04:53:08.53#ibcon#read 5, iclass 24, count 0 2006.201.04:53:08.53#ibcon#about to read 6, iclass 24, count 0 2006.201.04:53:08.53#ibcon#read 6, iclass 24, count 0 2006.201.04:53:08.53#ibcon#end of sib2, iclass 24, count 0 2006.201.04:53:08.53#ibcon#*mode == 0, iclass 24, count 0 2006.201.04:53:08.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.04:53:08.53#ibcon#[27=USB\r\n] 2006.201.04:53:08.53#ibcon#*before write, iclass 24, count 0 2006.201.04:53:08.53#ibcon#enter sib2, iclass 24, count 0 2006.201.04:53:08.53#ibcon#flushed, iclass 24, count 0 2006.201.04:53:08.53#ibcon#about to write, iclass 24, count 0 2006.201.04:53:08.53#ibcon#wrote, iclass 24, count 0 2006.201.04:53:08.53#ibcon#about to read 3, iclass 24, count 0 2006.201.04:53:08.56#ibcon#read 3, iclass 24, count 0 2006.201.04:53:08.56#ibcon#about to read 4, iclass 24, count 0 2006.201.04:53:08.56#ibcon#read 4, iclass 24, count 0 2006.201.04:53:08.56#ibcon#about to read 5, iclass 24, count 0 2006.201.04:53:08.56#ibcon#read 5, iclass 24, count 0 2006.201.04:53:08.56#ibcon#about to read 6, iclass 24, count 0 2006.201.04:53:08.56#ibcon#read 6, iclass 24, count 0 2006.201.04:53:08.56#ibcon#end of sib2, iclass 24, count 0 2006.201.04:53:08.56#ibcon#*after write, iclass 24, count 0 2006.201.04:53:08.56#ibcon#*before return 0, iclass 24, count 0 2006.201.04:53:08.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:08.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.04:53:08.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.04:53:08.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.04:53:08.56$vck44/vblo=6,719.99 2006.201.04:53:08.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.04:53:08.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.04:53:08.56#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:08.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:08.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:08.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:08.56#ibcon#enter wrdev, iclass 26, count 0 2006.201.04:53:08.56#ibcon#first serial, iclass 26, count 0 2006.201.04:53:08.56#ibcon#enter sib2, iclass 26, count 0 2006.201.04:53:08.56#ibcon#flushed, iclass 26, count 0 2006.201.04:53:08.56#ibcon#about to write, iclass 26, count 0 2006.201.04:53:08.56#ibcon#wrote, iclass 26, count 0 2006.201.04:53:08.56#ibcon#about to read 3, iclass 26, count 0 2006.201.04:53:08.58#ibcon#read 3, iclass 26, count 0 2006.201.04:53:08.58#ibcon#about to read 4, iclass 26, count 0 2006.201.04:53:08.58#ibcon#read 4, iclass 26, count 0 2006.201.04:53:08.58#ibcon#about to read 5, iclass 26, count 0 2006.201.04:53:08.58#ibcon#read 5, iclass 26, count 0 2006.201.04:53:08.58#ibcon#about to read 6, iclass 26, count 0 2006.201.04:53:08.58#ibcon#read 6, iclass 26, count 0 2006.201.04:53:08.58#ibcon#end of sib2, iclass 26, count 0 2006.201.04:53:08.58#ibcon#*mode == 0, iclass 26, count 0 2006.201.04:53:08.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.04:53:08.58#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:53:08.58#ibcon#*before write, iclass 26, count 0 2006.201.04:53:08.58#ibcon#enter sib2, iclass 26, count 0 2006.201.04:53:08.58#ibcon#flushed, iclass 26, count 0 2006.201.04:53:08.58#ibcon#about to write, iclass 26, count 0 2006.201.04:53:08.58#ibcon#wrote, iclass 26, count 0 2006.201.04:53:08.58#ibcon#about to read 3, iclass 26, count 0 2006.201.04:53:08.62#ibcon#read 3, iclass 26, count 0 2006.201.04:53:08.62#ibcon#about to read 4, iclass 26, count 0 2006.201.04:53:08.62#ibcon#read 4, iclass 26, count 0 2006.201.04:53:08.62#ibcon#about to read 5, iclass 26, count 0 2006.201.04:53:08.62#ibcon#read 5, iclass 26, count 0 2006.201.04:53:08.62#ibcon#about to read 6, iclass 26, count 0 2006.201.04:53:08.62#ibcon#read 6, iclass 26, count 0 2006.201.04:53:08.62#ibcon#end of sib2, iclass 26, count 0 2006.201.04:53:08.62#ibcon#*after write, iclass 26, count 0 2006.201.04:53:08.62#ibcon#*before return 0, iclass 26, count 0 2006.201.04:53:08.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:08.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.04:53:08.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.04:53:08.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.04:53:08.62$vck44/vb=6,4 2006.201.04:53:08.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.04:53:08.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.04:53:08.62#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:08.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:08.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:08.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:08.68#ibcon#enter wrdev, iclass 28, count 2 2006.201.04:53:08.68#ibcon#first serial, iclass 28, count 2 2006.201.04:53:08.68#ibcon#enter sib2, iclass 28, count 2 2006.201.04:53:08.68#ibcon#flushed, iclass 28, count 2 2006.201.04:53:08.68#ibcon#about to write, iclass 28, count 2 2006.201.04:53:08.68#ibcon#wrote, iclass 28, count 2 2006.201.04:53:08.68#ibcon#about to read 3, iclass 28, count 2 2006.201.04:53:08.70#ibcon#read 3, iclass 28, count 2 2006.201.04:53:08.70#ibcon#about to read 4, iclass 28, count 2 2006.201.04:53:08.70#ibcon#read 4, iclass 28, count 2 2006.201.04:53:08.70#ibcon#about to read 5, iclass 28, count 2 2006.201.04:53:08.70#ibcon#read 5, iclass 28, count 2 2006.201.04:53:08.70#ibcon#about to read 6, iclass 28, count 2 2006.201.04:53:08.70#ibcon#read 6, iclass 28, count 2 2006.201.04:53:08.70#ibcon#end of sib2, iclass 28, count 2 2006.201.04:53:08.70#ibcon#*mode == 0, iclass 28, count 2 2006.201.04:53:08.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.04:53:08.70#ibcon#[27=AT06-04\r\n] 2006.201.04:53:08.70#ibcon#*before write, iclass 28, count 2 2006.201.04:53:08.70#ibcon#enter sib2, iclass 28, count 2 2006.201.04:53:08.70#ibcon#flushed, iclass 28, count 2 2006.201.04:53:08.70#ibcon#about to write, iclass 28, count 2 2006.201.04:53:08.82#ibcon#wrote, iclass 28, count 2 2006.201.04:53:08.82#ibcon#about to read 3, iclass 28, count 2 2006.201.04:53:08.85#ibcon#read 3, iclass 28, count 2 2006.201.04:53:08.85#ibcon#about to read 4, iclass 28, count 2 2006.201.04:53:08.85#ibcon#read 4, iclass 28, count 2 2006.201.04:53:08.85#ibcon#about to read 5, iclass 28, count 2 2006.201.04:53:08.85#ibcon#read 5, iclass 28, count 2 2006.201.04:53:08.85#ibcon#about to read 6, iclass 28, count 2 2006.201.04:53:08.85#ibcon#read 6, iclass 28, count 2 2006.201.04:53:08.85#ibcon#end of sib2, iclass 28, count 2 2006.201.04:53:08.85#ibcon#*after write, iclass 28, count 2 2006.201.04:53:08.85#ibcon#*before return 0, iclass 28, count 2 2006.201.04:53:08.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:08.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.04:53:08.85#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.04:53:08.85#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:08.85#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:08.97#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:08.97#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:08.97#ibcon#enter wrdev, iclass 28, count 0 2006.201.04:53:08.97#ibcon#first serial, iclass 28, count 0 2006.201.04:53:08.97#ibcon#enter sib2, iclass 28, count 0 2006.201.04:53:08.97#ibcon#flushed, iclass 28, count 0 2006.201.04:53:08.97#ibcon#about to write, iclass 28, count 0 2006.201.04:53:08.97#ibcon#wrote, iclass 28, count 0 2006.201.04:53:08.97#ibcon#about to read 3, iclass 28, count 0 2006.201.04:53:08.99#ibcon#read 3, iclass 28, count 0 2006.201.04:53:08.99#ibcon#about to read 4, iclass 28, count 0 2006.201.04:53:08.99#ibcon#read 4, iclass 28, count 0 2006.201.04:53:08.99#ibcon#about to read 5, iclass 28, count 0 2006.201.04:53:08.99#ibcon#read 5, iclass 28, count 0 2006.201.04:53:08.99#ibcon#about to read 6, iclass 28, count 0 2006.201.04:53:08.99#ibcon#read 6, iclass 28, count 0 2006.201.04:53:08.99#ibcon#end of sib2, iclass 28, count 0 2006.201.04:53:08.99#ibcon#*mode == 0, iclass 28, count 0 2006.201.04:53:08.99#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.04:53:08.99#ibcon#[27=USB\r\n] 2006.201.04:53:08.99#ibcon#*before write, iclass 28, count 0 2006.201.04:53:08.99#ibcon#enter sib2, iclass 28, count 0 2006.201.04:53:08.99#ibcon#flushed, iclass 28, count 0 2006.201.04:53:08.99#ibcon#about to write, iclass 28, count 0 2006.201.04:53:08.99#ibcon#wrote, iclass 28, count 0 2006.201.04:53:08.99#ibcon#about to read 3, iclass 28, count 0 2006.201.04:53:09.02#ibcon#read 3, iclass 28, count 0 2006.201.04:53:09.02#ibcon#about to read 4, iclass 28, count 0 2006.201.04:53:09.02#ibcon#read 4, iclass 28, count 0 2006.201.04:53:09.02#ibcon#about to read 5, iclass 28, count 0 2006.201.04:53:09.02#ibcon#read 5, iclass 28, count 0 2006.201.04:53:09.02#ibcon#about to read 6, iclass 28, count 0 2006.201.04:53:09.02#ibcon#read 6, iclass 28, count 0 2006.201.04:53:09.02#ibcon#end of sib2, iclass 28, count 0 2006.201.04:53:09.02#ibcon#*after write, iclass 28, count 0 2006.201.04:53:09.02#ibcon#*before return 0, iclass 28, count 0 2006.201.04:53:09.02#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:09.02#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.04:53:09.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.04:53:09.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.04:53:09.02$vck44/vblo=7,734.99 2006.201.04:53:09.02#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.04:53:09.02#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.04:53:09.02#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:09.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:09.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:09.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:09.02#ibcon#enter wrdev, iclass 30, count 0 2006.201.04:53:09.02#ibcon#first serial, iclass 30, count 0 2006.201.04:53:09.02#ibcon#enter sib2, iclass 30, count 0 2006.201.04:53:09.02#ibcon#flushed, iclass 30, count 0 2006.201.04:53:09.02#ibcon#about to write, iclass 30, count 0 2006.201.04:53:09.02#ibcon#wrote, iclass 30, count 0 2006.201.04:53:09.02#ibcon#about to read 3, iclass 30, count 0 2006.201.04:53:09.04#ibcon#read 3, iclass 30, count 0 2006.201.04:53:09.04#ibcon#about to read 4, iclass 30, count 0 2006.201.04:53:09.04#ibcon#read 4, iclass 30, count 0 2006.201.04:53:09.04#ibcon#about to read 5, iclass 30, count 0 2006.201.04:53:09.04#ibcon#read 5, iclass 30, count 0 2006.201.04:53:09.04#ibcon#about to read 6, iclass 30, count 0 2006.201.04:53:09.04#ibcon#read 6, iclass 30, count 0 2006.201.04:53:09.04#ibcon#end of sib2, iclass 30, count 0 2006.201.04:53:09.04#ibcon#*mode == 0, iclass 30, count 0 2006.201.04:53:09.04#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.04:53:09.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:53:09.04#ibcon#*before write, iclass 30, count 0 2006.201.04:53:09.04#ibcon#enter sib2, iclass 30, count 0 2006.201.04:53:09.04#ibcon#flushed, iclass 30, count 0 2006.201.04:53:09.04#ibcon#about to write, iclass 30, count 0 2006.201.04:53:09.04#ibcon#wrote, iclass 30, count 0 2006.201.04:53:09.04#ibcon#about to read 3, iclass 30, count 0 2006.201.04:53:09.08#ibcon#read 3, iclass 30, count 0 2006.201.04:53:09.08#ibcon#about to read 4, iclass 30, count 0 2006.201.04:53:09.08#ibcon#read 4, iclass 30, count 0 2006.201.04:53:09.08#ibcon#about to read 5, iclass 30, count 0 2006.201.04:53:09.08#ibcon#read 5, iclass 30, count 0 2006.201.04:53:09.08#ibcon#about to read 6, iclass 30, count 0 2006.201.04:53:09.08#ibcon#read 6, iclass 30, count 0 2006.201.04:53:09.08#ibcon#end of sib2, iclass 30, count 0 2006.201.04:53:09.08#ibcon#*after write, iclass 30, count 0 2006.201.04:53:09.08#ibcon#*before return 0, iclass 30, count 0 2006.201.04:53:09.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:09.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.04:53:09.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.04:53:09.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.04:53:09.08$vck44/vb=7,4 2006.201.04:53:09.08#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.04:53:09.08#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.04:53:09.08#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:09.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:09.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:09.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:09.14#ibcon#enter wrdev, iclass 32, count 2 2006.201.04:53:09.14#ibcon#first serial, iclass 32, count 2 2006.201.04:53:09.14#ibcon#enter sib2, iclass 32, count 2 2006.201.04:53:09.14#ibcon#flushed, iclass 32, count 2 2006.201.04:53:09.14#ibcon#about to write, iclass 32, count 2 2006.201.04:53:09.14#ibcon#wrote, iclass 32, count 2 2006.201.04:53:09.14#ibcon#about to read 3, iclass 32, count 2 2006.201.04:53:09.16#ibcon#read 3, iclass 32, count 2 2006.201.04:53:09.16#ibcon#about to read 4, iclass 32, count 2 2006.201.04:53:09.16#ibcon#read 4, iclass 32, count 2 2006.201.04:53:09.16#ibcon#about to read 5, iclass 32, count 2 2006.201.04:53:09.16#ibcon#read 5, iclass 32, count 2 2006.201.04:53:09.16#ibcon#about to read 6, iclass 32, count 2 2006.201.04:53:09.16#ibcon#read 6, iclass 32, count 2 2006.201.04:53:09.16#ibcon#end of sib2, iclass 32, count 2 2006.201.04:53:09.16#ibcon#*mode == 0, iclass 32, count 2 2006.201.04:53:09.16#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.04:53:09.16#ibcon#[27=AT07-04\r\n] 2006.201.04:53:09.16#ibcon#*before write, iclass 32, count 2 2006.201.04:53:09.16#ibcon#enter sib2, iclass 32, count 2 2006.201.04:53:09.16#ibcon#flushed, iclass 32, count 2 2006.201.04:53:09.16#ibcon#about to write, iclass 32, count 2 2006.201.04:53:09.16#ibcon#wrote, iclass 32, count 2 2006.201.04:53:09.16#ibcon#about to read 3, iclass 32, count 2 2006.201.04:53:09.19#ibcon#read 3, iclass 32, count 2 2006.201.04:53:09.19#ibcon#about to read 4, iclass 32, count 2 2006.201.04:53:09.19#ibcon#read 4, iclass 32, count 2 2006.201.04:53:09.19#ibcon#about to read 5, iclass 32, count 2 2006.201.04:53:09.19#ibcon#read 5, iclass 32, count 2 2006.201.04:53:09.19#ibcon#about to read 6, iclass 32, count 2 2006.201.04:53:09.19#ibcon#read 6, iclass 32, count 2 2006.201.04:53:09.19#ibcon#end of sib2, iclass 32, count 2 2006.201.04:53:09.19#ibcon#*after write, iclass 32, count 2 2006.201.04:53:09.19#ibcon#*before return 0, iclass 32, count 2 2006.201.04:53:09.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:09.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.04:53:09.19#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.04:53:09.19#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:09.19#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:09.31#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:09.31#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:09.31#ibcon#enter wrdev, iclass 32, count 0 2006.201.04:53:09.31#ibcon#first serial, iclass 32, count 0 2006.201.04:53:09.31#ibcon#enter sib2, iclass 32, count 0 2006.201.04:53:09.31#ibcon#flushed, iclass 32, count 0 2006.201.04:53:09.31#ibcon#about to write, iclass 32, count 0 2006.201.04:53:09.31#ibcon#wrote, iclass 32, count 0 2006.201.04:53:09.31#ibcon#about to read 3, iclass 32, count 0 2006.201.04:53:09.33#ibcon#read 3, iclass 32, count 0 2006.201.04:53:09.33#ibcon#about to read 4, iclass 32, count 0 2006.201.04:53:09.33#ibcon#read 4, iclass 32, count 0 2006.201.04:53:09.33#ibcon#about to read 5, iclass 32, count 0 2006.201.04:53:09.33#ibcon#read 5, iclass 32, count 0 2006.201.04:53:09.33#ibcon#about to read 6, iclass 32, count 0 2006.201.04:53:09.33#ibcon#read 6, iclass 32, count 0 2006.201.04:53:09.33#ibcon#end of sib2, iclass 32, count 0 2006.201.04:53:09.33#ibcon#*mode == 0, iclass 32, count 0 2006.201.04:53:09.33#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.04:53:09.33#ibcon#[27=USB\r\n] 2006.201.04:53:09.33#ibcon#*before write, iclass 32, count 0 2006.201.04:53:09.33#ibcon#enter sib2, iclass 32, count 0 2006.201.04:53:09.33#ibcon#flushed, iclass 32, count 0 2006.201.04:53:09.33#ibcon#about to write, iclass 32, count 0 2006.201.04:53:09.33#ibcon#wrote, iclass 32, count 0 2006.201.04:53:09.33#ibcon#about to read 3, iclass 32, count 0 2006.201.04:53:09.36#ibcon#read 3, iclass 32, count 0 2006.201.04:53:09.36#ibcon#about to read 4, iclass 32, count 0 2006.201.04:53:09.36#ibcon#read 4, iclass 32, count 0 2006.201.04:53:09.36#ibcon#about to read 5, iclass 32, count 0 2006.201.04:53:09.36#ibcon#read 5, iclass 32, count 0 2006.201.04:53:09.36#ibcon#about to read 6, iclass 32, count 0 2006.201.04:53:09.36#ibcon#read 6, iclass 32, count 0 2006.201.04:53:09.36#ibcon#end of sib2, iclass 32, count 0 2006.201.04:53:09.36#ibcon#*after write, iclass 32, count 0 2006.201.04:53:09.36#ibcon#*before return 0, iclass 32, count 0 2006.201.04:53:09.36#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:09.36#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.04:53:09.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.04:53:09.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.04:53:09.36$vck44/vblo=8,744.99 2006.201.04:53:09.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.04:53:09.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.04:53:09.36#ibcon#ireg 17 cls_cnt 0 2006.201.04:53:09.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:09.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:09.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:09.36#ibcon#enter wrdev, iclass 34, count 0 2006.201.04:53:09.36#ibcon#first serial, iclass 34, count 0 2006.201.04:53:09.36#ibcon#enter sib2, iclass 34, count 0 2006.201.04:53:09.36#ibcon#flushed, iclass 34, count 0 2006.201.04:53:09.36#ibcon#about to write, iclass 34, count 0 2006.201.04:53:09.36#ibcon#wrote, iclass 34, count 0 2006.201.04:53:09.36#ibcon#about to read 3, iclass 34, count 0 2006.201.04:53:09.38#ibcon#read 3, iclass 34, count 0 2006.201.04:53:09.38#ibcon#about to read 4, iclass 34, count 0 2006.201.04:53:09.38#ibcon#read 4, iclass 34, count 0 2006.201.04:53:09.38#ibcon#about to read 5, iclass 34, count 0 2006.201.04:53:09.38#ibcon#read 5, iclass 34, count 0 2006.201.04:53:09.38#ibcon#about to read 6, iclass 34, count 0 2006.201.04:53:09.38#ibcon#read 6, iclass 34, count 0 2006.201.04:53:09.38#ibcon#end of sib2, iclass 34, count 0 2006.201.04:53:09.38#ibcon#*mode == 0, iclass 34, count 0 2006.201.04:53:09.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.04:53:09.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:53:09.38#ibcon#*before write, iclass 34, count 0 2006.201.04:53:09.38#ibcon#enter sib2, iclass 34, count 0 2006.201.04:53:09.38#ibcon#flushed, iclass 34, count 0 2006.201.04:53:09.38#ibcon#about to write, iclass 34, count 0 2006.201.04:53:09.38#ibcon#wrote, iclass 34, count 0 2006.201.04:53:09.38#ibcon#about to read 3, iclass 34, count 0 2006.201.04:53:09.42#ibcon#read 3, iclass 34, count 0 2006.201.04:53:09.42#ibcon#about to read 4, iclass 34, count 0 2006.201.04:53:09.42#ibcon#read 4, iclass 34, count 0 2006.201.04:53:09.42#ibcon#about to read 5, iclass 34, count 0 2006.201.04:53:09.42#ibcon#read 5, iclass 34, count 0 2006.201.04:53:09.42#ibcon#about to read 6, iclass 34, count 0 2006.201.04:53:09.42#ibcon#read 6, iclass 34, count 0 2006.201.04:53:09.42#ibcon#end of sib2, iclass 34, count 0 2006.201.04:53:09.42#ibcon#*after write, iclass 34, count 0 2006.201.04:53:09.42#ibcon#*before return 0, iclass 34, count 0 2006.201.04:53:09.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:09.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.04:53:09.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.04:53:09.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.04:53:09.42$vck44/vb=8,4 2006.201.04:53:09.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.04:53:09.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.04:53:09.42#ibcon#ireg 11 cls_cnt 2 2006.201.04:53:09.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:09.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:09.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:09.48#ibcon#enter wrdev, iclass 36, count 2 2006.201.04:53:09.48#ibcon#first serial, iclass 36, count 2 2006.201.04:53:09.48#ibcon#enter sib2, iclass 36, count 2 2006.201.04:53:09.48#ibcon#flushed, iclass 36, count 2 2006.201.04:53:09.48#ibcon#about to write, iclass 36, count 2 2006.201.04:53:09.48#ibcon#wrote, iclass 36, count 2 2006.201.04:53:09.48#ibcon#about to read 3, iclass 36, count 2 2006.201.04:53:09.50#ibcon#read 3, iclass 36, count 2 2006.201.04:53:09.50#ibcon#about to read 4, iclass 36, count 2 2006.201.04:53:09.50#ibcon#read 4, iclass 36, count 2 2006.201.04:53:09.50#ibcon#about to read 5, iclass 36, count 2 2006.201.04:53:09.50#ibcon#read 5, iclass 36, count 2 2006.201.04:53:09.50#ibcon#about to read 6, iclass 36, count 2 2006.201.04:53:09.50#ibcon#read 6, iclass 36, count 2 2006.201.04:53:09.50#ibcon#end of sib2, iclass 36, count 2 2006.201.04:53:09.50#ibcon#*mode == 0, iclass 36, count 2 2006.201.04:53:09.50#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.04:53:09.50#ibcon#[27=AT08-04\r\n] 2006.201.04:53:09.50#ibcon#*before write, iclass 36, count 2 2006.201.04:53:09.50#ibcon#enter sib2, iclass 36, count 2 2006.201.04:53:09.50#ibcon#flushed, iclass 36, count 2 2006.201.04:53:09.50#ibcon#about to write, iclass 36, count 2 2006.201.04:53:09.50#ibcon#wrote, iclass 36, count 2 2006.201.04:53:09.50#ibcon#about to read 3, iclass 36, count 2 2006.201.04:53:09.53#ibcon#read 3, iclass 36, count 2 2006.201.04:53:09.53#ibcon#about to read 4, iclass 36, count 2 2006.201.04:53:09.53#ibcon#read 4, iclass 36, count 2 2006.201.04:53:09.53#ibcon#about to read 5, iclass 36, count 2 2006.201.04:53:09.53#ibcon#read 5, iclass 36, count 2 2006.201.04:53:09.53#ibcon#about to read 6, iclass 36, count 2 2006.201.04:53:09.53#ibcon#read 6, iclass 36, count 2 2006.201.04:53:09.53#ibcon#end of sib2, iclass 36, count 2 2006.201.04:53:09.53#ibcon#*after write, iclass 36, count 2 2006.201.04:53:09.53#ibcon#*before return 0, iclass 36, count 2 2006.201.04:53:09.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:09.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.04:53:09.53#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.04:53:09.53#ibcon#ireg 7 cls_cnt 0 2006.201.04:53:09.53#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:09.65#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:09.65#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:09.65#ibcon#enter wrdev, iclass 36, count 0 2006.201.04:53:09.65#ibcon#first serial, iclass 36, count 0 2006.201.04:53:09.65#ibcon#enter sib2, iclass 36, count 0 2006.201.04:53:09.65#ibcon#flushed, iclass 36, count 0 2006.201.04:53:09.65#ibcon#about to write, iclass 36, count 0 2006.201.04:53:09.65#ibcon#wrote, iclass 36, count 0 2006.201.04:53:09.65#ibcon#about to read 3, iclass 36, count 0 2006.201.04:53:09.67#ibcon#read 3, iclass 36, count 0 2006.201.04:53:09.67#ibcon#about to read 4, iclass 36, count 0 2006.201.04:53:09.67#ibcon#read 4, iclass 36, count 0 2006.201.04:53:09.67#ibcon#about to read 5, iclass 36, count 0 2006.201.04:53:09.67#ibcon#read 5, iclass 36, count 0 2006.201.04:53:09.67#ibcon#about to read 6, iclass 36, count 0 2006.201.04:53:09.67#ibcon#read 6, iclass 36, count 0 2006.201.04:53:09.67#ibcon#end of sib2, iclass 36, count 0 2006.201.04:53:09.67#ibcon#*mode == 0, iclass 36, count 0 2006.201.04:53:09.67#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.04:53:09.67#ibcon#[27=USB\r\n] 2006.201.04:53:09.67#ibcon#*before write, iclass 36, count 0 2006.201.04:53:09.67#ibcon#enter sib2, iclass 36, count 0 2006.201.04:53:09.67#ibcon#flushed, iclass 36, count 0 2006.201.04:53:09.67#ibcon#about to write, iclass 36, count 0 2006.201.04:53:09.67#ibcon#wrote, iclass 36, count 0 2006.201.04:53:09.67#ibcon#about to read 3, iclass 36, count 0 2006.201.04:53:09.70#ibcon#read 3, iclass 36, count 0 2006.201.04:53:09.70#ibcon#about to read 4, iclass 36, count 0 2006.201.04:53:09.70#ibcon#read 4, iclass 36, count 0 2006.201.04:53:09.70#ibcon#about to read 5, iclass 36, count 0 2006.201.04:53:09.70#ibcon#read 5, iclass 36, count 0 2006.201.04:53:09.70#ibcon#about to read 6, iclass 36, count 0 2006.201.04:53:09.70#ibcon#read 6, iclass 36, count 0 2006.201.04:53:09.70#ibcon#end of sib2, iclass 36, count 0 2006.201.04:53:09.70#ibcon#*after write, iclass 36, count 0 2006.201.04:53:09.70#ibcon#*before return 0, iclass 36, count 0 2006.201.04:53:09.70#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:09.70#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.04:53:09.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.04:53:09.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.04:53:09.70$vck44/vabw=wide 2006.201.04:53:09.70#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.04:53:09.70#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.04:53:09.70#ibcon#ireg 8 cls_cnt 0 2006.201.04:53:09.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:09.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:09.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:09.70#ibcon#enter wrdev, iclass 38, count 0 2006.201.04:53:09.70#ibcon#first serial, iclass 38, count 0 2006.201.04:53:09.70#ibcon#enter sib2, iclass 38, count 0 2006.201.04:53:09.70#ibcon#flushed, iclass 38, count 0 2006.201.04:53:09.70#ibcon#about to write, iclass 38, count 0 2006.201.04:53:09.70#ibcon#wrote, iclass 38, count 0 2006.201.04:53:09.70#ibcon#about to read 3, iclass 38, count 0 2006.201.04:53:09.72#ibcon#read 3, iclass 38, count 0 2006.201.04:53:09.72#ibcon#about to read 4, iclass 38, count 0 2006.201.04:53:09.72#ibcon#read 4, iclass 38, count 0 2006.201.04:53:09.72#ibcon#about to read 5, iclass 38, count 0 2006.201.04:53:09.72#ibcon#read 5, iclass 38, count 0 2006.201.04:53:09.72#ibcon#about to read 6, iclass 38, count 0 2006.201.04:53:09.72#ibcon#read 6, iclass 38, count 0 2006.201.04:53:09.72#ibcon#end of sib2, iclass 38, count 0 2006.201.04:53:09.72#ibcon#*mode == 0, iclass 38, count 0 2006.201.04:53:09.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.04:53:09.72#ibcon#[25=BW32\r\n] 2006.201.04:53:09.72#ibcon#*before write, iclass 38, count 0 2006.201.04:53:09.72#ibcon#enter sib2, iclass 38, count 0 2006.201.04:53:09.72#ibcon#flushed, iclass 38, count 0 2006.201.04:53:09.72#ibcon#about to write, iclass 38, count 0 2006.201.04:53:09.72#ibcon#wrote, iclass 38, count 0 2006.201.04:53:09.72#ibcon#about to read 3, iclass 38, count 0 2006.201.04:53:09.75#ibcon#read 3, iclass 38, count 0 2006.201.04:53:09.75#ibcon#about to read 4, iclass 38, count 0 2006.201.04:53:09.75#ibcon#read 4, iclass 38, count 0 2006.201.04:53:09.75#ibcon#about to read 5, iclass 38, count 0 2006.201.04:53:09.75#ibcon#read 5, iclass 38, count 0 2006.201.04:53:09.75#ibcon#about to read 6, iclass 38, count 0 2006.201.04:53:09.75#ibcon#read 6, iclass 38, count 0 2006.201.04:53:09.75#ibcon#end of sib2, iclass 38, count 0 2006.201.04:53:09.75#ibcon#*after write, iclass 38, count 0 2006.201.04:53:09.75#ibcon#*before return 0, iclass 38, count 0 2006.201.04:53:09.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:09.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.04:53:09.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.04:53:09.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.04:53:09.75$vck44/vbbw=wide 2006.201.04:53:09.75#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.04:53:09.75#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.04:53:09.75#ibcon#ireg 8 cls_cnt 0 2006.201.04:53:09.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:53:09.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:53:09.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:53:09.82#ibcon#enter wrdev, iclass 40, count 0 2006.201.04:53:09.82#ibcon#first serial, iclass 40, count 0 2006.201.04:53:09.82#ibcon#enter sib2, iclass 40, count 0 2006.201.04:53:09.82#ibcon#flushed, iclass 40, count 0 2006.201.04:53:09.82#ibcon#about to write, iclass 40, count 0 2006.201.04:53:09.82#ibcon#wrote, iclass 40, count 0 2006.201.04:53:09.82#ibcon#about to read 3, iclass 40, count 0 2006.201.04:53:09.84#ibcon#read 3, iclass 40, count 0 2006.201.04:53:09.84#ibcon#about to read 4, iclass 40, count 0 2006.201.04:53:09.84#ibcon#read 4, iclass 40, count 0 2006.201.04:53:09.84#ibcon#about to read 5, iclass 40, count 0 2006.201.04:53:09.84#ibcon#read 5, iclass 40, count 0 2006.201.04:53:09.84#ibcon#about to read 6, iclass 40, count 0 2006.201.04:53:09.84#ibcon#read 6, iclass 40, count 0 2006.201.04:53:09.84#ibcon#end of sib2, iclass 40, count 0 2006.201.04:53:09.84#ibcon#*mode == 0, iclass 40, count 0 2006.201.04:53:09.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.04:53:09.84#ibcon#[27=BW32\r\n] 2006.201.04:53:09.84#ibcon#*before write, iclass 40, count 0 2006.201.04:53:09.84#ibcon#enter sib2, iclass 40, count 0 2006.201.04:53:09.84#ibcon#flushed, iclass 40, count 0 2006.201.04:53:09.84#ibcon#about to write, iclass 40, count 0 2006.201.04:53:09.84#ibcon#wrote, iclass 40, count 0 2006.201.04:53:09.84#ibcon#about to read 3, iclass 40, count 0 2006.201.04:53:09.84#abcon#<5=/04 2.6 5.6 22.99 881003.8\r\n> 2006.201.04:53:09.87#ibcon#read 3, iclass 40, count 0 2006.201.04:53:09.88#ibcon#about to read 4, iclass 40, count 0 2006.201.04:53:09.88#ibcon#read 4, iclass 40, count 0 2006.201.04:53:09.88#ibcon#about to read 5, iclass 40, count 0 2006.201.04:53:09.89#ibcon#read 5, iclass 40, count 0 2006.201.04:53:09.89#ibcon#about to read 6, iclass 40, count 0 2006.201.04:53:09.89#ibcon#read 6, iclass 40, count 0 2006.201.04:53:09.89#ibcon#end of sib2, iclass 40, count 0 2006.201.04:53:09.89#ibcon#*after write, iclass 40, count 0 2006.201.04:53:09.89#ibcon#*before return 0, iclass 40, count 0 2006.201.04:53:09.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:53:09.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.04:53:09.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.04:53:09.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.04:53:09.89$setupk4/ifdk4 2006.201.04:53:09.89$ifdk4/lo= 2006.201.04:53:09.89$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:53:09.89$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:53:09.89$ifdk4/patch= 2006.201.04:53:09.89$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:53:09.89$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:53:09.89$setupk4/!*+20s 2006.201.04:53:09.91#abcon#{5=INTERFACE CLEAR} 2006.201.04:53:09.97#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:53:16.14#trakl#Source acquired 2006.201.04:53:17.14#flagr#flagr/antenna,acquired 2006.201.04:53:20.06#abcon#<5=/04 2.6 5.6 22.99 891003.8\r\n> 2006.201.04:53:20.08#abcon#{5=INTERFACE CLEAR} 2006.201.04:53:20.14#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:53:24.21$setupk4/"tpicd 2006.201.04:53:24.21$setupk4/echo=off 2006.201.04:53:24.21$setupk4/xlog=off 2006.201.04:53:24.21:!2006.201.04:55:11 2006.201.04:55:11.00:preob 2006.201.04:55:12.13/onsource/TRACKING 2006.201.04:55:12.13:!2006.201.04:55:21 2006.201.04:55:21.00:"tape 2006.201.04:55:21.00:"st=record 2006.201.04:55:21.00:data_valid=on 2006.201.04:55:21.00:midob 2006.201.04:55:21.13/onsource/TRACKING 2006.201.04:55:21.13/wx/23.03,1003.8,88 2006.201.04:55:21.35/cable/+6.4681E-03 2006.201.04:55:22.44/va/01,08,usb,yes,29,32 2006.201.04:55:22.44/va/02,07,usb,yes,32,32 2006.201.04:55:22.44/va/03,08,usb,yes,28,30 2006.201.04:55:22.44/va/04,07,usb,yes,33,34 2006.201.04:55:22.44/va/05,04,usb,yes,29,29 2006.201.04:55:22.44/va/06,05,usb,yes,29,29 2006.201.04:55:22.44/va/07,05,usb,yes,28,29 2006.201.04:55:22.44/va/08,04,usb,yes,28,33 2006.201.04:55:22.67/valo/01,524.99,yes,locked 2006.201.04:55:22.67/valo/02,534.99,yes,locked 2006.201.04:55:22.67/valo/03,564.99,yes,locked 2006.201.04:55:22.67/valo/04,624.99,yes,locked 2006.201.04:55:22.67/valo/05,734.99,yes,locked 2006.201.04:55:22.67/valo/06,814.99,yes,locked 2006.201.04:55:22.67/valo/07,864.99,yes,locked 2006.201.04:55:22.67/valo/08,884.99,yes,locked 2006.201.04:55:23.76/vb/01,04,usb,yes,29,27 2006.201.04:55:23.76/vb/02,05,usb,yes,28,28 2006.201.04:55:23.76/vb/03,04,usb,yes,29,32 2006.201.04:55:23.76/vb/04,05,usb,yes,29,28 2006.201.04:55:23.76/vb/05,04,usb,yes,25,28 2006.201.04:55:23.76/vb/06,04,usb,yes,30,26 2006.201.04:55:23.76/vb/07,04,usb,yes,30,30 2006.201.04:55:23.76/vb/08,04,usb,yes,27,31 2006.201.04:55:23.99/vblo/01,629.99,yes,locked 2006.201.04:55:23.99/vblo/02,634.99,yes,locked 2006.201.04:55:23.99/vblo/03,649.99,yes,locked 2006.201.04:55:23.99/vblo/04,679.99,yes,locked 2006.201.04:55:23.99/vblo/05,709.99,yes,locked 2006.201.04:55:23.99/vblo/06,719.99,yes,locked 2006.201.04:55:23.99/vblo/07,734.99,yes,locked 2006.201.04:55:23.99/vblo/08,744.99,yes,locked 2006.201.04:55:24.14/vabw/8 2006.201.04:55:24.29/vbbw/8 2006.201.04:55:24.38/xfe/off,on,15.5 2006.201.04:55:24.76/ifatt/23,28,28,28 2006.201.04:55:25.05/fmout-gps/S +4.50E-07 2006.201.04:55:25.08:!2006.201.04:57:01 2006.201.04:57:01.00:data_valid=off 2006.201.04:57:01.00:"et 2006.201.04:57:01.00:!+3s 2006.201.04:57:04.01:"tape 2006.201.04:57:04.01:postob 2006.201.04:57:04.19/cable/+6.4676E-03 2006.201.04:57:04.19/wx/23.08,1003.8,88 2006.201.04:57:04.25/fmout-gps/S +4.51E-07 2006.201.04:57:04.25:scan_name=201-0500,jd0607,120 2006.201.04:57:04.25:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.201.04:57:06.14#flagr#flagr/antenna,new-source 2006.201.04:57:06.14:checkk5 2006.201.04:57:06.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.04:57:06.93/chk_autoobs//k5ts2/ autoobs is running! 2006.201.04:57:07.34/chk_autoobs//k5ts3/ autoobs is running! 2006.201.04:57:07.73/chk_autoobs//k5ts4/ autoobs is running! 2006.201.04:57:08.14/chk_obsdata//k5ts1/T2010455??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.04:57:08.54/chk_obsdata//k5ts2/T2010455??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.04:57:08.93/chk_obsdata//k5ts3/T2010455??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.04:57:09.33/chk_obsdata//k5ts4/T2010455??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.04:57:10.06/k5log//k5ts1_log_newline 2006.201.04:57:10.78/k5log//k5ts2_log_newline 2006.201.04:57:11.49/k5log//k5ts3_log_newline 2006.201.04:57:12.21/k5log//k5ts4_log_newline 2006.201.04:57:12.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.04:57:12.23:setupk4=1 2006.201.04:57:12.23$setupk4/echo=on 2006.201.04:57:12.23$setupk4/pcalon 2006.201.04:57:12.23$pcalon/"no phase cal control is implemented here 2006.201.04:57:12.23$setupk4/"tpicd=stop 2006.201.04:57:12.23$setupk4/"rec=synch_on 2006.201.04:57:12.23$setupk4/"rec_mode=128 2006.201.04:57:12.23$setupk4/!* 2006.201.04:57:12.23$setupk4/recpk4 2006.201.04:57:12.23$recpk4/recpatch= 2006.201.04:57:12.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.04:57:12.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.04:57:12.24$setupk4/vck44 2006.201.04:57:12.24$vck44/valo=1,524.99 2006.201.04:57:12.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.04:57:12.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.04:57:12.24#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:12.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:12.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:12.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:12.24#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:57:12.24#ibcon#first serial, iclass 33, count 0 2006.201.04:57:12.24#ibcon#enter sib2, iclass 33, count 0 2006.201.04:57:12.24#ibcon#flushed, iclass 33, count 0 2006.201.04:57:12.24#ibcon#about to write, iclass 33, count 0 2006.201.04:57:12.24#ibcon#wrote, iclass 33, count 0 2006.201.04:57:12.24#ibcon#about to read 3, iclass 33, count 0 2006.201.04:57:12.26#ibcon#read 3, iclass 33, count 0 2006.201.04:57:12.26#ibcon#about to read 4, iclass 33, count 0 2006.201.04:57:12.26#ibcon#read 4, iclass 33, count 0 2006.201.04:57:12.26#ibcon#about to read 5, iclass 33, count 0 2006.201.04:57:12.26#ibcon#read 5, iclass 33, count 0 2006.201.04:57:12.26#ibcon#about to read 6, iclass 33, count 0 2006.201.04:57:12.26#ibcon#read 6, iclass 33, count 0 2006.201.04:57:12.26#ibcon#end of sib2, iclass 33, count 0 2006.201.04:57:12.26#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:57:12.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:57:12.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.04:57:12.26#ibcon#*before write, iclass 33, count 0 2006.201.04:57:12.26#ibcon#enter sib2, iclass 33, count 0 2006.201.04:57:12.26#ibcon#flushed, iclass 33, count 0 2006.201.04:57:12.26#ibcon#about to write, iclass 33, count 0 2006.201.04:57:12.26#ibcon#wrote, iclass 33, count 0 2006.201.04:57:12.26#ibcon#about to read 3, iclass 33, count 0 2006.201.04:57:12.31#ibcon#read 3, iclass 33, count 0 2006.201.04:57:12.31#ibcon#about to read 4, iclass 33, count 0 2006.201.04:57:12.31#ibcon#read 4, iclass 33, count 0 2006.201.04:57:12.31#ibcon#about to read 5, iclass 33, count 0 2006.201.04:57:12.31#ibcon#read 5, iclass 33, count 0 2006.201.04:57:12.31#ibcon#about to read 6, iclass 33, count 0 2006.201.04:57:12.31#ibcon#read 6, iclass 33, count 0 2006.201.04:57:12.31#ibcon#end of sib2, iclass 33, count 0 2006.201.04:57:12.31#ibcon#*after write, iclass 33, count 0 2006.201.04:57:12.31#ibcon#*before return 0, iclass 33, count 0 2006.201.04:57:12.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:12.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:12.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:57:12.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:57:12.31$vck44/va=1,8 2006.201.04:57:12.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.04:57:12.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.04:57:12.31#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:12.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:12.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:12.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:12.31#ibcon#enter wrdev, iclass 35, count 2 2006.201.04:57:12.31#ibcon#first serial, iclass 35, count 2 2006.201.04:57:12.31#ibcon#enter sib2, iclass 35, count 2 2006.201.04:57:12.31#ibcon#flushed, iclass 35, count 2 2006.201.04:57:12.31#ibcon#about to write, iclass 35, count 2 2006.201.04:57:12.31#ibcon#wrote, iclass 35, count 2 2006.201.04:57:12.31#ibcon#about to read 3, iclass 35, count 2 2006.201.04:57:12.33#ibcon#read 3, iclass 35, count 2 2006.201.04:57:12.33#ibcon#about to read 4, iclass 35, count 2 2006.201.04:57:12.33#ibcon#read 4, iclass 35, count 2 2006.201.04:57:12.33#ibcon#about to read 5, iclass 35, count 2 2006.201.04:57:12.33#ibcon#read 5, iclass 35, count 2 2006.201.04:57:12.33#ibcon#about to read 6, iclass 35, count 2 2006.201.04:57:12.33#ibcon#read 6, iclass 35, count 2 2006.201.04:57:12.33#ibcon#end of sib2, iclass 35, count 2 2006.201.04:57:12.33#ibcon#*mode == 0, iclass 35, count 2 2006.201.04:57:12.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.04:57:12.33#ibcon#[25=AT01-08\r\n] 2006.201.04:57:12.33#ibcon#*before write, iclass 35, count 2 2006.201.04:57:12.33#ibcon#enter sib2, iclass 35, count 2 2006.201.04:57:12.33#ibcon#flushed, iclass 35, count 2 2006.201.04:57:12.33#ibcon#about to write, iclass 35, count 2 2006.201.04:57:12.33#ibcon#wrote, iclass 35, count 2 2006.201.04:57:12.33#ibcon#about to read 3, iclass 35, count 2 2006.201.04:57:12.36#ibcon#read 3, iclass 35, count 2 2006.201.04:57:12.36#ibcon#about to read 4, iclass 35, count 2 2006.201.04:57:12.36#ibcon#read 4, iclass 35, count 2 2006.201.04:57:12.36#ibcon#about to read 5, iclass 35, count 2 2006.201.04:57:12.36#ibcon#read 5, iclass 35, count 2 2006.201.04:57:12.36#ibcon#about to read 6, iclass 35, count 2 2006.201.04:57:12.36#ibcon#read 6, iclass 35, count 2 2006.201.04:57:12.36#ibcon#end of sib2, iclass 35, count 2 2006.201.04:57:12.36#ibcon#*after write, iclass 35, count 2 2006.201.04:57:12.36#ibcon#*before return 0, iclass 35, count 2 2006.201.04:57:12.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:12.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:12.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.04:57:12.36#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:12.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:12.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:12.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:12.48#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:57:12.48#ibcon#first serial, iclass 35, count 0 2006.201.04:57:12.48#ibcon#enter sib2, iclass 35, count 0 2006.201.04:57:12.48#ibcon#flushed, iclass 35, count 0 2006.201.04:57:12.48#ibcon#about to write, iclass 35, count 0 2006.201.04:57:12.48#ibcon#wrote, iclass 35, count 0 2006.201.04:57:12.48#ibcon#about to read 3, iclass 35, count 0 2006.201.04:57:12.50#ibcon#read 3, iclass 35, count 0 2006.201.04:57:12.50#ibcon#about to read 4, iclass 35, count 0 2006.201.04:57:12.50#ibcon#read 4, iclass 35, count 0 2006.201.04:57:12.50#ibcon#about to read 5, iclass 35, count 0 2006.201.04:57:12.50#ibcon#read 5, iclass 35, count 0 2006.201.04:57:12.50#ibcon#about to read 6, iclass 35, count 0 2006.201.04:57:12.50#ibcon#read 6, iclass 35, count 0 2006.201.04:57:12.50#ibcon#end of sib2, iclass 35, count 0 2006.201.04:57:12.50#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:57:12.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:57:12.50#ibcon#[25=USB\r\n] 2006.201.04:57:12.50#ibcon#*before write, iclass 35, count 0 2006.201.04:57:12.50#ibcon#enter sib2, iclass 35, count 0 2006.201.04:57:12.50#ibcon#flushed, iclass 35, count 0 2006.201.04:57:12.50#ibcon#about to write, iclass 35, count 0 2006.201.04:57:12.50#ibcon#wrote, iclass 35, count 0 2006.201.04:57:12.50#ibcon#about to read 3, iclass 35, count 0 2006.201.04:57:12.53#ibcon#read 3, iclass 35, count 0 2006.201.04:57:12.53#ibcon#about to read 4, iclass 35, count 0 2006.201.04:57:12.53#ibcon#read 4, iclass 35, count 0 2006.201.04:57:12.53#ibcon#about to read 5, iclass 35, count 0 2006.201.04:57:12.53#ibcon#read 5, iclass 35, count 0 2006.201.04:57:12.53#ibcon#about to read 6, iclass 35, count 0 2006.201.04:57:12.53#ibcon#read 6, iclass 35, count 0 2006.201.04:57:12.53#ibcon#end of sib2, iclass 35, count 0 2006.201.04:57:12.53#ibcon#*after write, iclass 35, count 0 2006.201.04:57:12.53#ibcon#*before return 0, iclass 35, count 0 2006.201.04:57:12.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:12.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:12.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:57:12.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:57:12.53$vck44/valo=2,534.99 2006.201.04:57:12.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.04:57:12.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.04:57:12.53#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:12.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:12.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:12.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:12.53#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:57:12.53#ibcon#first serial, iclass 37, count 0 2006.201.04:57:12.53#ibcon#enter sib2, iclass 37, count 0 2006.201.04:57:12.53#ibcon#flushed, iclass 37, count 0 2006.201.04:57:12.53#ibcon#about to write, iclass 37, count 0 2006.201.04:57:12.53#ibcon#wrote, iclass 37, count 0 2006.201.04:57:12.53#ibcon#about to read 3, iclass 37, count 0 2006.201.04:57:12.55#ibcon#read 3, iclass 37, count 0 2006.201.04:57:12.55#ibcon#about to read 4, iclass 37, count 0 2006.201.04:57:12.55#ibcon#read 4, iclass 37, count 0 2006.201.04:57:12.55#ibcon#about to read 5, iclass 37, count 0 2006.201.04:57:12.55#ibcon#read 5, iclass 37, count 0 2006.201.04:57:12.55#ibcon#about to read 6, iclass 37, count 0 2006.201.04:57:12.55#ibcon#read 6, iclass 37, count 0 2006.201.04:57:12.55#ibcon#end of sib2, iclass 37, count 0 2006.201.04:57:12.55#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:57:12.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:57:12.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.04:57:12.55#ibcon#*before write, iclass 37, count 0 2006.201.04:57:12.55#ibcon#enter sib2, iclass 37, count 0 2006.201.04:57:12.55#ibcon#flushed, iclass 37, count 0 2006.201.04:57:12.55#ibcon#about to write, iclass 37, count 0 2006.201.04:57:12.55#ibcon#wrote, iclass 37, count 0 2006.201.04:57:12.55#ibcon#about to read 3, iclass 37, count 0 2006.201.04:57:12.59#ibcon#read 3, iclass 37, count 0 2006.201.04:57:12.59#ibcon#about to read 4, iclass 37, count 0 2006.201.04:57:12.59#ibcon#read 4, iclass 37, count 0 2006.201.04:57:12.59#ibcon#about to read 5, iclass 37, count 0 2006.201.04:57:12.59#ibcon#read 5, iclass 37, count 0 2006.201.04:57:12.59#ibcon#about to read 6, iclass 37, count 0 2006.201.04:57:12.59#ibcon#read 6, iclass 37, count 0 2006.201.04:57:12.59#ibcon#end of sib2, iclass 37, count 0 2006.201.04:57:12.59#ibcon#*after write, iclass 37, count 0 2006.201.04:57:12.59#ibcon#*before return 0, iclass 37, count 0 2006.201.04:57:12.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:12.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:12.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:57:12.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:57:12.59$vck44/va=2,7 2006.201.04:57:12.59#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.04:57:12.59#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.04:57:12.59#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:12.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:12.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:12.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:12.65#ibcon#enter wrdev, iclass 39, count 2 2006.201.04:57:12.65#ibcon#first serial, iclass 39, count 2 2006.201.04:57:12.65#ibcon#enter sib2, iclass 39, count 2 2006.201.04:57:12.65#ibcon#flushed, iclass 39, count 2 2006.201.04:57:12.65#ibcon#about to write, iclass 39, count 2 2006.201.04:57:12.65#ibcon#wrote, iclass 39, count 2 2006.201.04:57:12.65#ibcon#about to read 3, iclass 39, count 2 2006.201.04:57:12.67#ibcon#read 3, iclass 39, count 2 2006.201.04:57:12.67#ibcon#about to read 4, iclass 39, count 2 2006.201.04:57:12.67#ibcon#read 4, iclass 39, count 2 2006.201.04:57:12.67#ibcon#about to read 5, iclass 39, count 2 2006.201.04:57:12.67#ibcon#read 5, iclass 39, count 2 2006.201.04:57:12.67#ibcon#about to read 6, iclass 39, count 2 2006.201.04:57:12.67#ibcon#read 6, iclass 39, count 2 2006.201.04:57:12.67#ibcon#end of sib2, iclass 39, count 2 2006.201.04:57:12.67#ibcon#*mode == 0, iclass 39, count 2 2006.201.04:57:12.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.04:57:12.67#ibcon#[25=AT02-07\r\n] 2006.201.04:57:12.67#ibcon#*before write, iclass 39, count 2 2006.201.04:57:12.67#ibcon#enter sib2, iclass 39, count 2 2006.201.04:57:12.67#ibcon#flushed, iclass 39, count 2 2006.201.04:57:12.67#ibcon#about to write, iclass 39, count 2 2006.201.04:57:12.67#ibcon#wrote, iclass 39, count 2 2006.201.04:57:12.67#ibcon#about to read 3, iclass 39, count 2 2006.201.04:57:12.70#ibcon#read 3, iclass 39, count 2 2006.201.04:57:12.70#ibcon#about to read 4, iclass 39, count 2 2006.201.04:57:12.70#ibcon#read 4, iclass 39, count 2 2006.201.04:57:12.70#ibcon#about to read 5, iclass 39, count 2 2006.201.04:57:12.70#ibcon#read 5, iclass 39, count 2 2006.201.04:57:12.70#ibcon#about to read 6, iclass 39, count 2 2006.201.04:57:12.70#ibcon#read 6, iclass 39, count 2 2006.201.04:57:12.70#ibcon#end of sib2, iclass 39, count 2 2006.201.04:57:12.70#ibcon#*after write, iclass 39, count 2 2006.201.04:57:12.70#ibcon#*before return 0, iclass 39, count 2 2006.201.04:57:12.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:12.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:12.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.04:57:12.70#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:12.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:12.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:12.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:12.82#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:57:12.82#ibcon#first serial, iclass 39, count 0 2006.201.04:57:12.82#ibcon#enter sib2, iclass 39, count 0 2006.201.04:57:12.82#ibcon#flushed, iclass 39, count 0 2006.201.04:57:12.82#ibcon#about to write, iclass 39, count 0 2006.201.04:57:12.82#ibcon#wrote, iclass 39, count 0 2006.201.04:57:12.82#ibcon#about to read 3, iclass 39, count 0 2006.201.04:57:12.84#ibcon#read 3, iclass 39, count 0 2006.201.04:57:12.84#ibcon#about to read 4, iclass 39, count 0 2006.201.04:57:12.84#ibcon#read 4, iclass 39, count 0 2006.201.04:57:12.84#ibcon#about to read 5, iclass 39, count 0 2006.201.04:57:12.84#ibcon#read 5, iclass 39, count 0 2006.201.04:57:12.84#ibcon#about to read 6, iclass 39, count 0 2006.201.04:57:12.84#ibcon#read 6, iclass 39, count 0 2006.201.04:57:12.84#ibcon#end of sib2, iclass 39, count 0 2006.201.04:57:12.84#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:57:12.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:57:12.84#ibcon#[25=USB\r\n] 2006.201.04:57:12.84#ibcon#*before write, iclass 39, count 0 2006.201.04:57:12.84#ibcon#enter sib2, iclass 39, count 0 2006.201.04:57:12.84#ibcon#flushed, iclass 39, count 0 2006.201.04:57:12.84#ibcon#about to write, iclass 39, count 0 2006.201.04:57:12.84#ibcon#wrote, iclass 39, count 0 2006.201.04:57:12.84#ibcon#about to read 3, iclass 39, count 0 2006.201.04:57:12.87#ibcon#read 3, iclass 39, count 0 2006.201.04:57:12.87#ibcon#about to read 4, iclass 39, count 0 2006.201.04:57:12.87#ibcon#read 4, iclass 39, count 0 2006.201.04:57:12.87#ibcon#about to read 5, iclass 39, count 0 2006.201.04:57:12.87#ibcon#read 5, iclass 39, count 0 2006.201.04:57:12.87#ibcon#about to read 6, iclass 39, count 0 2006.201.04:57:12.87#ibcon#read 6, iclass 39, count 0 2006.201.04:57:12.87#ibcon#end of sib2, iclass 39, count 0 2006.201.04:57:12.87#ibcon#*after write, iclass 39, count 0 2006.201.04:57:12.87#ibcon#*before return 0, iclass 39, count 0 2006.201.04:57:12.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:12.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:12.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:57:12.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:57:12.87$vck44/valo=3,564.99 2006.201.04:57:12.87#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.04:57:12.87#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.04:57:12.87#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:12.87#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:12.87#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:12.87#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:12.87#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:57:12.87#ibcon#first serial, iclass 2, count 0 2006.201.04:57:12.87#ibcon#enter sib2, iclass 2, count 0 2006.201.04:57:12.87#ibcon#flushed, iclass 2, count 0 2006.201.04:57:12.87#ibcon#about to write, iclass 2, count 0 2006.201.04:57:12.87#ibcon#wrote, iclass 2, count 0 2006.201.04:57:12.87#ibcon#about to read 3, iclass 2, count 0 2006.201.04:57:12.89#ibcon#read 3, iclass 2, count 0 2006.201.04:57:12.89#ibcon#about to read 4, iclass 2, count 0 2006.201.04:57:12.89#ibcon#read 4, iclass 2, count 0 2006.201.04:57:12.89#ibcon#about to read 5, iclass 2, count 0 2006.201.04:57:12.89#ibcon#read 5, iclass 2, count 0 2006.201.04:57:12.89#ibcon#about to read 6, iclass 2, count 0 2006.201.04:57:12.89#ibcon#read 6, iclass 2, count 0 2006.201.04:57:12.89#ibcon#end of sib2, iclass 2, count 0 2006.201.04:57:12.89#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:57:12.89#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:57:12.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.04:57:12.89#ibcon#*before write, iclass 2, count 0 2006.201.04:57:12.89#ibcon#enter sib2, iclass 2, count 0 2006.201.04:57:12.89#ibcon#flushed, iclass 2, count 0 2006.201.04:57:12.89#ibcon#about to write, iclass 2, count 0 2006.201.04:57:12.89#ibcon#wrote, iclass 2, count 0 2006.201.04:57:12.89#ibcon#about to read 3, iclass 2, count 0 2006.201.04:57:12.93#ibcon#read 3, iclass 2, count 0 2006.201.04:57:12.93#ibcon#about to read 4, iclass 2, count 0 2006.201.04:57:12.93#ibcon#read 4, iclass 2, count 0 2006.201.04:57:12.93#ibcon#about to read 5, iclass 2, count 0 2006.201.04:57:12.93#ibcon#read 5, iclass 2, count 0 2006.201.04:57:12.93#ibcon#about to read 6, iclass 2, count 0 2006.201.04:57:12.93#ibcon#read 6, iclass 2, count 0 2006.201.04:57:12.93#ibcon#end of sib2, iclass 2, count 0 2006.201.04:57:12.93#ibcon#*after write, iclass 2, count 0 2006.201.04:57:12.93#ibcon#*before return 0, iclass 2, count 0 2006.201.04:57:12.93#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:12.93#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:12.93#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:57:12.93#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:57:12.93$vck44/va=3,8 2006.201.04:57:12.93#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.04:57:12.93#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.04:57:12.93#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:12.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:12.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:12.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:12.99#ibcon#enter wrdev, iclass 5, count 2 2006.201.04:57:12.99#ibcon#first serial, iclass 5, count 2 2006.201.04:57:12.99#ibcon#enter sib2, iclass 5, count 2 2006.201.04:57:12.99#ibcon#flushed, iclass 5, count 2 2006.201.04:57:12.99#ibcon#about to write, iclass 5, count 2 2006.201.04:57:12.99#ibcon#wrote, iclass 5, count 2 2006.201.04:57:12.99#ibcon#about to read 3, iclass 5, count 2 2006.201.04:57:13.01#ibcon#read 3, iclass 5, count 2 2006.201.04:57:13.01#ibcon#about to read 4, iclass 5, count 2 2006.201.04:57:13.01#ibcon#read 4, iclass 5, count 2 2006.201.04:57:13.01#ibcon#about to read 5, iclass 5, count 2 2006.201.04:57:13.01#ibcon#read 5, iclass 5, count 2 2006.201.04:57:13.01#ibcon#about to read 6, iclass 5, count 2 2006.201.04:57:13.01#ibcon#read 6, iclass 5, count 2 2006.201.04:57:13.01#ibcon#end of sib2, iclass 5, count 2 2006.201.04:57:13.01#ibcon#*mode == 0, iclass 5, count 2 2006.201.04:57:13.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.04:57:13.01#ibcon#[25=AT03-08\r\n] 2006.201.04:57:13.01#ibcon#*before write, iclass 5, count 2 2006.201.04:57:13.01#ibcon#enter sib2, iclass 5, count 2 2006.201.04:57:13.01#ibcon#flushed, iclass 5, count 2 2006.201.04:57:13.01#ibcon#about to write, iclass 5, count 2 2006.201.04:57:13.01#ibcon#wrote, iclass 5, count 2 2006.201.04:57:13.01#ibcon#about to read 3, iclass 5, count 2 2006.201.04:57:13.04#ibcon#read 3, iclass 5, count 2 2006.201.04:57:13.04#ibcon#about to read 4, iclass 5, count 2 2006.201.04:57:13.04#ibcon#read 4, iclass 5, count 2 2006.201.04:57:13.04#ibcon#about to read 5, iclass 5, count 2 2006.201.04:57:13.04#ibcon#read 5, iclass 5, count 2 2006.201.04:57:13.04#ibcon#about to read 6, iclass 5, count 2 2006.201.04:57:13.04#ibcon#read 6, iclass 5, count 2 2006.201.04:57:13.04#ibcon#end of sib2, iclass 5, count 2 2006.201.04:57:13.04#ibcon#*after write, iclass 5, count 2 2006.201.04:57:13.04#ibcon#*before return 0, iclass 5, count 2 2006.201.04:57:13.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:13.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:13.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.04:57:13.04#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:13.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:13.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:13.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:13.16#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:57:13.16#ibcon#first serial, iclass 5, count 0 2006.201.04:57:13.16#ibcon#enter sib2, iclass 5, count 0 2006.201.04:57:13.16#ibcon#flushed, iclass 5, count 0 2006.201.04:57:13.16#ibcon#about to write, iclass 5, count 0 2006.201.04:57:13.16#ibcon#wrote, iclass 5, count 0 2006.201.04:57:13.16#ibcon#about to read 3, iclass 5, count 0 2006.201.04:57:13.18#ibcon#read 3, iclass 5, count 0 2006.201.04:57:13.18#ibcon#about to read 4, iclass 5, count 0 2006.201.04:57:13.18#ibcon#read 4, iclass 5, count 0 2006.201.04:57:13.18#ibcon#about to read 5, iclass 5, count 0 2006.201.04:57:13.18#ibcon#read 5, iclass 5, count 0 2006.201.04:57:13.18#ibcon#about to read 6, iclass 5, count 0 2006.201.04:57:13.18#ibcon#read 6, iclass 5, count 0 2006.201.04:57:13.18#ibcon#end of sib2, iclass 5, count 0 2006.201.04:57:13.18#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:57:13.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:57:13.18#ibcon#[25=USB\r\n] 2006.201.04:57:13.18#ibcon#*before write, iclass 5, count 0 2006.201.04:57:13.18#ibcon#enter sib2, iclass 5, count 0 2006.201.04:57:13.18#ibcon#flushed, iclass 5, count 0 2006.201.04:57:13.18#ibcon#about to write, iclass 5, count 0 2006.201.04:57:13.18#ibcon#wrote, iclass 5, count 0 2006.201.04:57:13.18#ibcon#about to read 3, iclass 5, count 0 2006.201.04:57:13.21#ibcon#read 3, iclass 5, count 0 2006.201.04:57:13.21#ibcon#about to read 4, iclass 5, count 0 2006.201.04:57:13.21#ibcon#read 4, iclass 5, count 0 2006.201.04:57:13.21#ibcon#about to read 5, iclass 5, count 0 2006.201.04:57:13.21#ibcon#read 5, iclass 5, count 0 2006.201.04:57:13.21#ibcon#about to read 6, iclass 5, count 0 2006.201.04:57:13.21#ibcon#read 6, iclass 5, count 0 2006.201.04:57:13.21#ibcon#end of sib2, iclass 5, count 0 2006.201.04:57:13.21#ibcon#*after write, iclass 5, count 0 2006.201.04:57:13.21#ibcon#*before return 0, iclass 5, count 0 2006.201.04:57:13.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:13.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:13.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:57:13.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:57:13.21$vck44/valo=4,624.99 2006.201.04:57:13.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.04:57:13.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.04:57:13.21#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:13.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:13.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:13.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:13.21#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:57:13.21#ibcon#first serial, iclass 7, count 0 2006.201.04:57:13.21#ibcon#enter sib2, iclass 7, count 0 2006.201.04:57:13.21#ibcon#flushed, iclass 7, count 0 2006.201.04:57:13.21#ibcon#about to write, iclass 7, count 0 2006.201.04:57:13.21#ibcon#wrote, iclass 7, count 0 2006.201.04:57:13.21#ibcon#about to read 3, iclass 7, count 0 2006.201.04:57:13.23#ibcon#read 3, iclass 7, count 0 2006.201.04:57:13.23#ibcon#about to read 4, iclass 7, count 0 2006.201.04:57:13.23#ibcon#read 4, iclass 7, count 0 2006.201.04:57:13.23#ibcon#about to read 5, iclass 7, count 0 2006.201.04:57:13.23#ibcon#read 5, iclass 7, count 0 2006.201.04:57:13.23#ibcon#about to read 6, iclass 7, count 0 2006.201.04:57:13.23#ibcon#read 6, iclass 7, count 0 2006.201.04:57:13.23#ibcon#end of sib2, iclass 7, count 0 2006.201.04:57:13.23#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:57:13.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:57:13.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.04:57:13.23#ibcon#*before write, iclass 7, count 0 2006.201.04:57:13.23#ibcon#enter sib2, iclass 7, count 0 2006.201.04:57:13.23#ibcon#flushed, iclass 7, count 0 2006.201.04:57:13.23#ibcon#about to write, iclass 7, count 0 2006.201.04:57:13.23#ibcon#wrote, iclass 7, count 0 2006.201.04:57:13.23#ibcon#about to read 3, iclass 7, count 0 2006.201.04:57:13.27#ibcon#read 3, iclass 7, count 0 2006.201.04:57:13.27#ibcon#about to read 4, iclass 7, count 0 2006.201.04:57:13.27#ibcon#read 4, iclass 7, count 0 2006.201.04:57:13.27#ibcon#about to read 5, iclass 7, count 0 2006.201.04:57:13.27#ibcon#read 5, iclass 7, count 0 2006.201.04:57:13.27#ibcon#about to read 6, iclass 7, count 0 2006.201.04:57:13.27#ibcon#read 6, iclass 7, count 0 2006.201.04:57:13.27#ibcon#end of sib2, iclass 7, count 0 2006.201.04:57:13.27#ibcon#*after write, iclass 7, count 0 2006.201.04:57:13.27#ibcon#*before return 0, iclass 7, count 0 2006.201.04:57:13.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:13.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:13.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:57:13.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:57:13.27$vck44/va=4,7 2006.201.04:57:13.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.04:57:13.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.04:57:13.27#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:13.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:13.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:13.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:13.33#ibcon#enter wrdev, iclass 11, count 2 2006.201.04:57:13.33#ibcon#first serial, iclass 11, count 2 2006.201.04:57:13.33#ibcon#enter sib2, iclass 11, count 2 2006.201.04:57:13.33#ibcon#flushed, iclass 11, count 2 2006.201.04:57:13.33#ibcon#about to write, iclass 11, count 2 2006.201.04:57:13.33#ibcon#wrote, iclass 11, count 2 2006.201.04:57:13.33#ibcon#about to read 3, iclass 11, count 2 2006.201.04:57:13.35#ibcon#read 3, iclass 11, count 2 2006.201.04:57:13.35#ibcon#about to read 4, iclass 11, count 2 2006.201.04:57:13.35#ibcon#read 4, iclass 11, count 2 2006.201.04:57:13.35#ibcon#about to read 5, iclass 11, count 2 2006.201.04:57:13.35#ibcon#read 5, iclass 11, count 2 2006.201.04:57:13.35#ibcon#about to read 6, iclass 11, count 2 2006.201.04:57:13.35#ibcon#read 6, iclass 11, count 2 2006.201.04:57:13.35#ibcon#end of sib2, iclass 11, count 2 2006.201.04:57:13.35#ibcon#*mode == 0, iclass 11, count 2 2006.201.04:57:13.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.04:57:13.35#ibcon#[25=AT04-07\r\n] 2006.201.04:57:13.35#ibcon#*before write, iclass 11, count 2 2006.201.04:57:13.35#ibcon#enter sib2, iclass 11, count 2 2006.201.04:57:13.35#ibcon#flushed, iclass 11, count 2 2006.201.04:57:13.35#ibcon#about to write, iclass 11, count 2 2006.201.04:57:13.35#ibcon#wrote, iclass 11, count 2 2006.201.04:57:13.35#ibcon#about to read 3, iclass 11, count 2 2006.201.04:57:13.38#ibcon#read 3, iclass 11, count 2 2006.201.04:57:13.38#ibcon#about to read 4, iclass 11, count 2 2006.201.04:57:13.38#ibcon#read 4, iclass 11, count 2 2006.201.04:57:13.39#ibcon#about to read 5, iclass 11, count 2 2006.201.04:57:13.39#ibcon#read 5, iclass 11, count 2 2006.201.04:57:13.39#ibcon#about to read 6, iclass 11, count 2 2006.201.04:57:13.39#ibcon#read 6, iclass 11, count 2 2006.201.04:57:13.39#ibcon#end of sib2, iclass 11, count 2 2006.201.04:57:13.39#ibcon#*after write, iclass 11, count 2 2006.201.04:57:13.39#ibcon#*before return 0, iclass 11, count 2 2006.201.04:57:13.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:13.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:13.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.04:57:13.39#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:13.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:13.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:13.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:13.52#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:57:13.52#ibcon#first serial, iclass 11, count 0 2006.201.04:57:13.52#ibcon#enter sib2, iclass 11, count 0 2006.201.04:57:13.52#ibcon#flushed, iclass 11, count 0 2006.201.04:57:13.52#ibcon#about to write, iclass 11, count 0 2006.201.04:57:13.52#ibcon#wrote, iclass 11, count 0 2006.201.04:57:13.52#ibcon#about to read 3, iclass 11, count 0 2006.201.04:57:13.54#ibcon#read 3, iclass 11, count 0 2006.201.04:57:13.54#ibcon#about to read 4, iclass 11, count 0 2006.201.04:57:13.54#ibcon#read 4, iclass 11, count 0 2006.201.04:57:13.54#ibcon#about to read 5, iclass 11, count 0 2006.201.04:57:13.54#ibcon#read 5, iclass 11, count 0 2006.201.04:57:13.54#ibcon#about to read 6, iclass 11, count 0 2006.201.04:57:13.54#ibcon#read 6, iclass 11, count 0 2006.201.04:57:13.54#ibcon#end of sib2, iclass 11, count 0 2006.201.04:57:13.54#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:57:13.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:57:13.54#ibcon#[25=USB\r\n] 2006.201.04:57:13.54#ibcon#*before write, iclass 11, count 0 2006.201.04:57:13.54#ibcon#enter sib2, iclass 11, count 0 2006.201.04:57:13.54#ibcon#flushed, iclass 11, count 0 2006.201.04:57:13.54#ibcon#about to write, iclass 11, count 0 2006.201.04:57:13.54#ibcon#wrote, iclass 11, count 0 2006.201.04:57:13.54#ibcon#about to read 3, iclass 11, count 0 2006.201.04:57:13.57#ibcon#read 3, iclass 11, count 0 2006.201.04:57:13.57#ibcon#about to read 4, iclass 11, count 0 2006.201.04:57:13.57#ibcon#read 4, iclass 11, count 0 2006.201.04:57:13.57#ibcon#about to read 5, iclass 11, count 0 2006.201.04:57:13.57#ibcon#read 5, iclass 11, count 0 2006.201.04:57:13.57#ibcon#about to read 6, iclass 11, count 0 2006.201.04:57:13.57#ibcon#read 6, iclass 11, count 0 2006.201.04:57:13.57#ibcon#end of sib2, iclass 11, count 0 2006.201.04:57:13.57#ibcon#*after write, iclass 11, count 0 2006.201.04:57:13.57#ibcon#*before return 0, iclass 11, count 0 2006.201.04:57:13.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:13.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:13.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:57:13.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:57:13.57$vck44/valo=5,734.99 2006.201.04:57:13.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.04:57:13.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.04:57:13.57#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:13.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:13.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:13.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:13.57#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:57:13.57#ibcon#first serial, iclass 13, count 0 2006.201.04:57:13.57#ibcon#enter sib2, iclass 13, count 0 2006.201.04:57:13.57#ibcon#flushed, iclass 13, count 0 2006.201.04:57:13.57#ibcon#about to write, iclass 13, count 0 2006.201.04:57:13.57#ibcon#wrote, iclass 13, count 0 2006.201.04:57:13.57#ibcon#about to read 3, iclass 13, count 0 2006.201.04:57:13.59#ibcon#read 3, iclass 13, count 0 2006.201.04:57:13.59#ibcon#about to read 4, iclass 13, count 0 2006.201.04:57:13.59#ibcon#read 4, iclass 13, count 0 2006.201.04:57:13.59#ibcon#about to read 5, iclass 13, count 0 2006.201.04:57:13.59#ibcon#read 5, iclass 13, count 0 2006.201.04:57:13.59#ibcon#about to read 6, iclass 13, count 0 2006.201.04:57:13.59#ibcon#read 6, iclass 13, count 0 2006.201.04:57:13.59#ibcon#end of sib2, iclass 13, count 0 2006.201.04:57:13.59#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:57:13.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:57:13.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.04:57:13.59#ibcon#*before write, iclass 13, count 0 2006.201.04:57:13.59#ibcon#enter sib2, iclass 13, count 0 2006.201.04:57:13.59#ibcon#flushed, iclass 13, count 0 2006.201.04:57:13.59#ibcon#about to write, iclass 13, count 0 2006.201.04:57:13.59#ibcon#wrote, iclass 13, count 0 2006.201.04:57:13.59#ibcon#about to read 3, iclass 13, count 0 2006.201.04:57:13.63#ibcon#read 3, iclass 13, count 0 2006.201.04:57:13.63#ibcon#about to read 4, iclass 13, count 0 2006.201.04:57:13.63#ibcon#read 4, iclass 13, count 0 2006.201.04:57:13.63#ibcon#about to read 5, iclass 13, count 0 2006.201.04:57:13.63#ibcon#read 5, iclass 13, count 0 2006.201.04:57:13.63#ibcon#about to read 6, iclass 13, count 0 2006.201.04:57:13.63#ibcon#read 6, iclass 13, count 0 2006.201.04:57:13.63#ibcon#end of sib2, iclass 13, count 0 2006.201.04:57:13.63#ibcon#*after write, iclass 13, count 0 2006.201.04:57:13.63#ibcon#*before return 0, iclass 13, count 0 2006.201.04:57:13.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:13.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:13.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:57:13.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:57:13.63$vck44/va=5,4 2006.201.04:57:13.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.04:57:13.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.04:57:13.63#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:13.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:13.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:13.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:13.69#ibcon#enter wrdev, iclass 15, count 2 2006.201.04:57:13.69#ibcon#first serial, iclass 15, count 2 2006.201.04:57:13.69#ibcon#enter sib2, iclass 15, count 2 2006.201.04:57:13.69#ibcon#flushed, iclass 15, count 2 2006.201.04:57:13.69#ibcon#about to write, iclass 15, count 2 2006.201.04:57:13.69#ibcon#wrote, iclass 15, count 2 2006.201.04:57:13.69#ibcon#about to read 3, iclass 15, count 2 2006.201.04:57:13.71#ibcon#read 3, iclass 15, count 2 2006.201.04:57:13.71#ibcon#about to read 4, iclass 15, count 2 2006.201.04:57:13.71#ibcon#read 4, iclass 15, count 2 2006.201.04:57:13.71#ibcon#about to read 5, iclass 15, count 2 2006.201.04:57:13.71#ibcon#read 5, iclass 15, count 2 2006.201.04:57:13.71#ibcon#about to read 6, iclass 15, count 2 2006.201.04:57:13.71#ibcon#read 6, iclass 15, count 2 2006.201.04:57:13.71#ibcon#end of sib2, iclass 15, count 2 2006.201.04:57:13.71#ibcon#*mode == 0, iclass 15, count 2 2006.201.04:57:13.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.04:57:13.71#ibcon#[25=AT05-04\r\n] 2006.201.04:57:13.71#ibcon#*before write, iclass 15, count 2 2006.201.04:57:13.71#ibcon#enter sib2, iclass 15, count 2 2006.201.04:57:13.71#ibcon#flushed, iclass 15, count 2 2006.201.04:57:13.71#ibcon#about to write, iclass 15, count 2 2006.201.04:57:13.71#ibcon#wrote, iclass 15, count 2 2006.201.04:57:13.71#ibcon#about to read 3, iclass 15, count 2 2006.201.04:57:13.74#ibcon#read 3, iclass 15, count 2 2006.201.04:57:13.74#ibcon#about to read 4, iclass 15, count 2 2006.201.04:57:13.74#ibcon#read 4, iclass 15, count 2 2006.201.04:57:13.74#ibcon#about to read 5, iclass 15, count 2 2006.201.04:57:13.74#ibcon#read 5, iclass 15, count 2 2006.201.04:57:13.74#ibcon#about to read 6, iclass 15, count 2 2006.201.04:57:13.74#ibcon#read 6, iclass 15, count 2 2006.201.04:57:13.74#ibcon#end of sib2, iclass 15, count 2 2006.201.04:57:13.74#ibcon#*after write, iclass 15, count 2 2006.201.04:57:13.74#ibcon#*before return 0, iclass 15, count 2 2006.201.04:57:13.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:13.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:13.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.04:57:13.74#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:13.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:13.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:13.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:13.86#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:57:13.86#ibcon#first serial, iclass 15, count 0 2006.201.04:57:13.86#ibcon#enter sib2, iclass 15, count 0 2006.201.04:57:13.86#ibcon#flushed, iclass 15, count 0 2006.201.04:57:13.86#ibcon#about to write, iclass 15, count 0 2006.201.04:57:13.86#ibcon#wrote, iclass 15, count 0 2006.201.04:57:13.86#ibcon#about to read 3, iclass 15, count 0 2006.201.04:57:13.88#ibcon#read 3, iclass 15, count 0 2006.201.04:57:13.88#ibcon#about to read 4, iclass 15, count 0 2006.201.04:57:13.88#ibcon#read 4, iclass 15, count 0 2006.201.04:57:13.88#ibcon#about to read 5, iclass 15, count 0 2006.201.04:57:13.88#ibcon#read 5, iclass 15, count 0 2006.201.04:57:13.88#ibcon#about to read 6, iclass 15, count 0 2006.201.04:57:13.88#ibcon#read 6, iclass 15, count 0 2006.201.04:57:13.88#ibcon#end of sib2, iclass 15, count 0 2006.201.04:57:13.88#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:57:13.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:57:13.88#ibcon#[25=USB\r\n] 2006.201.04:57:13.88#ibcon#*before write, iclass 15, count 0 2006.201.04:57:13.88#ibcon#enter sib2, iclass 15, count 0 2006.201.04:57:13.88#ibcon#flushed, iclass 15, count 0 2006.201.04:57:13.88#ibcon#about to write, iclass 15, count 0 2006.201.04:57:13.88#ibcon#wrote, iclass 15, count 0 2006.201.04:57:13.88#ibcon#about to read 3, iclass 15, count 0 2006.201.04:57:13.91#ibcon#read 3, iclass 15, count 0 2006.201.04:57:13.91#ibcon#about to read 4, iclass 15, count 0 2006.201.04:57:13.91#ibcon#read 4, iclass 15, count 0 2006.201.04:57:13.91#ibcon#about to read 5, iclass 15, count 0 2006.201.04:57:13.91#ibcon#read 5, iclass 15, count 0 2006.201.04:57:13.91#ibcon#about to read 6, iclass 15, count 0 2006.201.04:57:13.91#ibcon#read 6, iclass 15, count 0 2006.201.04:57:13.91#ibcon#end of sib2, iclass 15, count 0 2006.201.04:57:13.91#ibcon#*after write, iclass 15, count 0 2006.201.04:57:13.91#ibcon#*before return 0, iclass 15, count 0 2006.201.04:57:13.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:13.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:13.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:57:13.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:57:13.91$vck44/valo=6,814.99 2006.201.04:57:13.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.04:57:13.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.04:57:13.91#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:13.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:13.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:13.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:13.91#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:57:13.91#ibcon#first serial, iclass 17, count 0 2006.201.04:57:13.91#ibcon#enter sib2, iclass 17, count 0 2006.201.04:57:13.91#ibcon#flushed, iclass 17, count 0 2006.201.04:57:13.91#ibcon#about to write, iclass 17, count 0 2006.201.04:57:13.91#ibcon#wrote, iclass 17, count 0 2006.201.04:57:13.91#ibcon#about to read 3, iclass 17, count 0 2006.201.04:57:13.93#ibcon#read 3, iclass 17, count 0 2006.201.04:57:13.93#ibcon#about to read 4, iclass 17, count 0 2006.201.04:57:13.93#ibcon#read 4, iclass 17, count 0 2006.201.04:57:13.93#ibcon#about to read 5, iclass 17, count 0 2006.201.04:57:13.93#ibcon#read 5, iclass 17, count 0 2006.201.04:57:13.93#ibcon#about to read 6, iclass 17, count 0 2006.201.04:57:13.93#ibcon#read 6, iclass 17, count 0 2006.201.04:57:13.93#ibcon#end of sib2, iclass 17, count 0 2006.201.04:57:13.93#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:57:13.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:57:13.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.04:57:13.93#ibcon#*before write, iclass 17, count 0 2006.201.04:57:13.93#ibcon#enter sib2, iclass 17, count 0 2006.201.04:57:13.93#ibcon#flushed, iclass 17, count 0 2006.201.04:57:13.93#ibcon#about to write, iclass 17, count 0 2006.201.04:57:13.93#ibcon#wrote, iclass 17, count 0 2006.201.04:57:13.93#ibcon#about to read 3, iclass 17, count 0 2006.201.04:57:13.97#ibcon#read 3, iclass 17, count 0 2006.201.04:57:13.97#ibcon#about to read 4, iclass 17, count 0 2006.201.04:57:13.97#ibcon#read 4, iclass 17, count 0 2006.201.04:57:13.97#ibcon#about to read 5, iclass 17, count 0 2006.201.04:57:13.97#ibcon#read 5, iclass 17, count 0 2006.201.04:57:13.97#ibcon#about to read 6, iclass 17, count 0 2006.201.04:57:13.97#ibcon#read 6, iclass 17, count 0 2006.201.04:57:13.97#ibcon#end of sib2, iclass 17, count 0 2006.201.04:57:13.97#ibcon#*after write, iclass 17, count 0 2006.201.04:57:13.97#ibcon#*before return 0, iclass 17, count 0 2006.201.04:57:13.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:13.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:13.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:57:13.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:57:13.97$vck44/va=6,5 2006.201.04:57:13.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.04:57:13.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.04:57:13.97#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:13.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:14.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:14.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:14.03#ibcon#enter wrdev, iclass 19, count 2 2006.201.04:57:14.03#ibcon#first serial, iclass 19, count 2 2006.201.04:57:14.03#ibcon#enter sib2, iclass 19, count 2 2006.201.04:57:14.03#ibcon#flushed, iclass 19, count 2 2006.201.04:57:14.03#ibcon#about to write, iclass 19, count 2 2006.201.04:57:14.03#ibcon#wrote, iclass 19, count 2 2006.201.04:57:14.03#ibcon#about to read 3, iclass 19, count 2 2006.201.04:57:14.05#ibcon#read 3, iclass 19, count 2 2006.201.04:57:14.05#ibcon#about to read 4, iclass 19, count 2 2006.201.04:57:14.05#ibcon#read 4, iclass 19, count 2 2006.201.04:57:14.05#ibcon#about to read 5, iclass 19, count 2 2006.201.04:57:14.05#ibcon#read 5, iclass 19, count 2 2006.201.04:57:14.05#ibcon#about to read 6, iclass 19, count 2 2006.201.04:57:14.05#ibcon#read 6, iclass 19, count 2 2006.201.04:57:14.05#ibcon#end of sib2, iclass 19, count 2 2006.201.04:57:14.05#ibcon#*mode == 0, iclass 19, count 2 2006.201.04:57:14.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.04:57:14.05#ibcon#[25=AT06-05\r\n] 2006.201.04:57:14.05#ibcon#*before write, iclass 19, count 2 2006.201.04:57:14.05#ibcon#enter sib2, iclass 19, count 2 2006.201.04:57:14.05#ibcon#flushed, iclass 19, count 2 2006.201.04:57:14.05#ibcon#about to write, iclass 19, count 2 2006.201.04:57:14.05#ibcon#wrote, iclass 19, count 2 2006.201.04:57:14.05#ibcon#about to read 3, iclass 19, count 2 2006.201.04:57:14.06#abcon#<5=/04 2.6 5.6 23.09 881003.7\r\n> 2006.201.04:57:14.08#abcon#{5=INTERFACE CLEAR} 2006.201.04:57:14.08#ibcon#read 3, iclass 19, count 2 2006.201.04:57:14.08#ibcon#about to read 4, iclass 19, count 2 2006.201.04:57:14.08#ibcon#read 4, iclass 19, count 2 2006.201.04:57:14.08#ibcon#about to read 5, iclass 19, count 2 2006.201.04:57:14.08#ibcon#read 5, iclass 19, count 2 2006.201.04:57:14.08#ibcon#about to read 6, iclass 19, count 2 2006.201.04:57:14.08#ibcon#read 6, iclass 19, count 2 2006.201.04:57:14.08#ibcon#end of sib2, iclass 19, count 2 2006.201.04:57:14.08#ibcon#*after write, iclass 19, count 2 2006.201.04:57:14.08#ibcon#*before return 0, iclass 19, count 2 2006.201.04:57:14.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:14.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:14.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.04:57:14.08#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:14.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:14.14#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:57:14.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:14.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:14.20#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:57:14.20#ibcon#first serial, iclass 19, count 0 2006.201.04:57:14.20#ibcon#enter sib2, iclass 19, count 0 2006.201.04:57:14.20#ibcon#flushed, iclass 19, count 0 2006.201.04:57:14.20#ibcon#about to write, iclass 19, count 0 2006.201.04:57:14.20#ibcon#wrote, iclass 19, count 0 2006.201.04:57:14.20#ibcon#about to read 3, iclass 19, count 0 2006.201.04:57:14.22#ibcon#read 3, iclass 19, count 0 2006.201.04:57:14.22#ibcon#about to read 4, iclass 19, count 0 2006.201.04:57:14.22#ibcon#read 4, iclass 19, count 0 2006.201.04:57:14.22#ibcon#about to read 5, iclass 19, count 0 2006.201.04:57:14.22#ibcon#read 5, iclass 19, count 0 2006.201.04:57:14.22#ibcon#about to read 6, iclass 19, count 0 2006.201.04:57:14.22#ibcon#read 6, iclass 19, count 0 2006.201.04:57:14.22#ibcon#end of sib2, iclass 19, count 0 2006.201.04:57:14.22#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:57:14.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:57:14.22#ibcon#[25=USB\r\n] 2006.201.04:57:14.22#ibcon#*before write, iclass 19, count 0 2006.201.04:57:14.22#ibcon#enter sib2, iclass 19, count 0 2006.201.04:57:14.22#ibcon#flushed, iclass 19, count 0 2006.201.04:57:14.22#ibcon#about to write, iclass 19, count 0 2006.201.04:57:14.22#ibcon#wrote, iclass 19, count 0 2006.201.04:57:14.22#ibcon#about to read 3, iclass 19, count 0 2006.201.04:57:14.25#ibcon#read 3, iclass 19, count 0 2006.201.04:57:14.25#ibcon#about to read 4, iclass 19, count 0 2006.201.04:57:14.25#ibcon#read 4, iclass 19, count 0 2006.201.04:57:14.25#ibcon#about to read 5, iclass 19, count 0 2006.201.04:57:14.25#ibcon#read 5, iclass 19, count 0 2006.201.04:57:14.25#ibcon#about to read 6, iclass 19, count 0 2006.201.04:57:14.25#ibcon#read 6, iclass 19, count 0 2006.201.04:57:14.25#ibcon#end of sib2, iclass 19, count 0 2006.201.04:57:14.25#ibcon#*after write, iclass 19, count 0 2006.201.04:57:14.25#ibcon#*before return 0, iclass 19, count 0 2006.201.04:57:14.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:14.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:14.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:57:14.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:57:14.25$vck44/valo=7,864.99 2006.201.04:57:14.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.04:57:14.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.04:57:14.25#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:14.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:14.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:14.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:14.25#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:57:14.25#ibcon#first serial, iclass 25, count 0 2006.201.04:57:14.25#ibcon#enter sib2, iclass 25, count 0 2006.201.04:57:14.25#ibcon#flushed, iclass 25, count 0 2006.201.04:57:14.25#ibcon#about to write, iclass 25, count 0 2006.201.04:57:14.25#ibcon#wrote, iclass 25, count 0 2006.201.04:57:14.25#ibcon#about to read 3, iclass 25, count 0 2006.201.04:57:14.27#ibcon#read 3, iclass 25, count 0 2006.201.04:57:14.27#ibcon#about to read 4, iclass 25, count 0 2006.201.04:57:14.27#ibcon#read 4, iclass 25, count 0 2006.201.04:57:14.27#ibcon#about to read 5, iclass 25, count 0 2006.201.04:57:14.27#ibcon#read 5, iclass 25, count 0 2006.201.04:57:14.27#ibcon#about to read 6, iclass 25, count 0 2006.201.04:57:14.27#ibcon#read 6, iclass 25, count 0 2006.201.04:57:14.27#ibcon#end of sib2, iclass 25, count 0 2006.201.04:57:14.27#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:57:14.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:57:14.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.04:57:14.27#ibcon#*before write, iclass 25, count 0 2006.201.04:57:14.27#ibcon#enter sib2, iclass 25, count 0 2006.201.04:57:14.27#ibcon#flushed, iclass 25, count 0 2006.201.04:57:14.27#ibcon#about to write, iclass 25, count 0 2006.201.04:57:14.27#ibcon#wrote, iclass 25, count 0 2006.201.04:57:14.27#ibcon#about to read 3, iclass 25, count 0 2006.201.04:57:14.31#ibcon#read 3, iclass 25, count 0 2006.201.04:57:14.31#ibcon#about to read 4, iclass 25, count 0 2006.201.04:57:14.31#ibcon#read 4, iclass 25, count 0 2006.201.04:57:14.31#ibcon#about to read 5, iclass 25, count 0 2006.201.04:57:14.31#ibcon#read 5, iclass 25, count 0 2006.201.04:57:14.31#ibcon#about to read 6, iclass 25, count 0 2006.201.04:57:14.31#ibcon#read 6, iclass 25, count 0 2006.201.04:57:14.31#ibcon#end of sib2, iclass 25, count 0 2006.201.04:57:14.31#ibcon#*after write, iclass 25, count 0 2006.201.04:57:14.31#ibcon#*before return 0, iclass 25, count 0 2006.201.04:57:14.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:14.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:14.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:57:14.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:57:14.31$vck44/va=7,5 2006.201.04:57:14.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.04:57:14.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.04:57:14.31#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:14.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:14.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:14.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:14.37#ibcon#enter wrdev, iclass 27, count 2 2006.201.04:57:14.37#ibcon#first serial, iclass 27, count 2 2006.201.04:57:14.37#ibcon#enter sib2, iclass 27, count 2 2006.201.04:57:14.37#ibcon#flushed, iclass 27, count 2 2006.201.04:57:14.37#ibcon#about to write, iclass 27, count 2 2006.201.04:57:14.37#ibcon#wrote, iclass 27, count 2 2006.201.04:57:14.37#ibcon#about to read 3, iclass 27, count 2 2006.201.04:57:14.39#ibcon#read 3, iclass 27, count 2 2006.201.04:57:14.39#ibcon#about to read 4, iclass 27, count 2 2006.201.04:57:14.39#ibcon#read 4, iclass 27, count 2 2006.201.04:57:14.39#ibcon#about to read 5, iclass 27, count 2 2006.201.04:57:14.39#ibcon#read 5, iclass 27, count 2 2006.201.04:57:14.39#ibcon#about to read 6, iclass 27, count 2 2006.201.04:57:14.39#ibcon#read 6, iclass 27, count 2 2006.201.04:57:14.39#ibcon#end of sib2, iclass 27, count 2 2006.201.04:57:14.39#ibcon#*mode == 0, iclass 27, count 2 2006.201.04:57:14.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.04:57:14.39#ibcon#[25=AT07-05\r\n] 2006.201.04:57:14.39#ibcon#*before write, iclass 27, count 2 2006.201.04:57:14.47#ibcon#enter sib2, iclass 27, count 2 2006.201.04:57:14.47#ibcon#flushed, iclass 27, count 2 2006.201.04:57:14.47#ibcon#about to write, iclass 27, count 2 2006.201.04:57:14.47#ibcon#wrote, iclass 27, count 2 2006.201.04:57:14.47#ibcon#about to read 3, iclass 27, count 2 2006.201.04:57:14.51#ibcon#read 3, iclass 27, count 2 2006.201.04:57:14.51#ibcon#about to read 4, iclass 27, count 2 2006.201.04:57:14.51#ibcon#read 4, iclass 27, count 2 2006.201.04:57:14.51#ibcon#about to read 5, iclass 27, count 2 2006.201.04:57:14.51#ibcon#read 5, iclass 27, count 2 2006.201.04:57:14.51#ibcon#about to read 6, iclass 27, count 2 2006.201.04:57:14.51#ibcon#read 6, iclass 27, count 2 2006.201.04:57:14.51#ibcon#end of sib2, iclass 27, count 2 2006.201.04:57:14.51#ibcon#*after write, iclass 27, count 2 2006.201.04:57:14.51#ibcon#*before return 0, iclass 27, count 2 2006.201.04:57:14.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:14.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:14.51#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.04:57:14.51#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:14.51#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:14.63#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:14.63#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:14.63#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:57:14.63#ibcon#first serial, iclass 27, count 0 2006.201.04:57:14.63#ibcon#enter sib2, iclass 27, count 0 2006.201.04:57:14.63#ibcon#flushed, iclass 27, count 0 2006.201.04:57:14.63#ibcon#about to write, iclass 27, count 0 2006.201.04:57:14.63#ibcon#wrote, iclass 27, count 0 2006.201.04:57:14.63#ibcon#about to read 3, iclass 27, count 0 2006.201.04:57:14.65#ibcon#read 3, iclass 27, count 0 2006.201.04:57:14.65#ibcon#about to read 4, iclass 27, count 0 2006.201.04:57:14.65#ibcon#read 4, iclass 27, count 0 2006.201.04:57:14.65#ibcon#about to read 5, iclass 27, count 0 2006.201.04:57:14.65#ibcon#read 5, iclass 27, count 0 2006.201.04:57:14.65#ibcon#about to read 6, iclass 27, count 0 2006.201.04:57:14.65#ibcon#read 6, iclass 27, count 0 2006.201.04:57:14.65#ibcon#end of sib2, iclass 27, count 0 2006.201.04:57:14.65#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:57:14.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:57:14.65#ibcon#[25=USB\r\n] 2006.201.04:57:14.65#ibcon#*before write, iclass 27, count 0 2006.201.04:57:14.65#ibcon#enter sib2, iclass 27, count 0 2006.201.04:57:14.65#ibcon#flushed, iclass 27, count 0 2006.201.04:57:14.65#ibcon#about to write, iclass 27, count 0 2006.201.04:57:14.65#ibcon#wrote, iclass 27, count 0 2006.201.04:57:14.65#ibcon#about to read 3, iclass 27, count 0 2006.201.04:57:14.68#ibcon#read 3, iclass 27, count 0 2006.201.04:57:14.68#ibcon#about to read 4, iclass 27, count 0 2006.201.04:57:14.68#ibcon#read 4, iclass 27, count 0 2006.201.04:57:14.68#ibcon#about to read 5, iclass 27, count 0 2006.201.04:57:14.68#ibcon#read 5, iclass 27, count 0 2006.201.04:57:14.68#ibcon#about to read 6, iclass 27, count 0 2006.201.04:57:14.68#ibcon#read 6, iclass 27, count 0 2006.201.04:57:14.68#ibcon#end of sib2, iclass 27, count 0 2006.201.04:57:14.68#ibcon#*after write, iclass 27, count 0 2006.201.04:57:14.68#ibcon#*before return 0, iclass 27, count 0 2006.201.04:57:14.68#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:14.68#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:14.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:57:14.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:57:14.68$vck44/valo=8,884.99 2006.201.04:57:14.68#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.04:57:14.68#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.04:57:14.68#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:14.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:14.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:14.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:14.68#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:57:14.68#ibcon#first serial, iclass 29, count 0 2006.201.04:57:14.68#ibcon#enter sib2, iclass 29, count 0 2006.201.04:57:14.68#ibcon#flushed, iclass 29, count 0 2006.201.04:57:14.68#ibcon#about to write, iclass 29, count 0 2006.201.04:57:14.68#ibcon#wrote, iclass 29, count 0 2006.201.04:57:14.68#ibcon#about to read 3, iclass 29, count 0 2006.201.04:57:14.70#ibcon#read 3, iclass 29, count 0 2006.201.04:57:14.70#ibcon#about to read 4, iclass 29, count 0 2006.201.04:57:14.70#ibcon#read 4, iclass 29, count 0 2006.201.04:57:14.70#ibcon#about to read 5, iclass 29, count 0 2006.201.04:57:14.70#ibcon#read 5, iclass 29, count 0 2006.201.04:57:14.70#ibcon#about to read 6, iclass 29, count 0 2006.201.04:57:14.70#ibcon#read 6, iclass 29, count 0 2006.201.04:57:14.70#ibcon#end of sib2, iclass 29, count 0 2006.201.04:57:14.70#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:57:14.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:57:14.70#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.04:57:14.70#ibcon#*before write, iclass 29, count 0 2006.201.04:57:14.70#ibcon#enter sib2, iclass 29, count 0 2006.201.04:57:14.70#ibcon#flushed, iclass 29, count 0 2006.201.04:57:14.70#ibcon#about to write, iclass 29, count 0 2006.201.04:57:14.70#ibcon#wrote, iclass 29, count 0 2006.201.04:57:14.70#ibcon#about to read 3, iclass 29, count 0 2006.201.04:57:14.74#ibcon#read 3, iclass 29, count 0 2006.201.04:57:14.74#ibcon#about to read 4, iclass 29, count 0 2006.201.04:57:14.74#ibcon#read 4, iclass 29, count 0 2006.201.04:57:14.74#ibcon#about to read 5, iclass 29, count 0 2006.201.04:57:14.74#ibcon#read 5, iclass 29, count 0 2006.201.04:57:14.74#ibcon#about to read 6, iclass 29, count 0 2006.201.04:57:14.74#ibcon#read 6, iclass 29, count 0 2006.201.04:57:14.74#ibcon#end of sib2, iclass 29, count 0 2006.201.04:57:14.74#ibcon#*after write, iclass 29, count 0 2006.201.04:57:14.74#ibcon#*before return 0, iclass 29, count 0 2006.201.04:57:14.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:14.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:14.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:57:14.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:57:14.74$vck44/va=8,4 2006.201.04:57:14.74#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.04:57:14.74#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.04:57:14.74#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:14.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:57:14.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:57:14.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:57:14.80#ibcon#enter wrdev, iclass 31, count 2 2006.201.04:57:14.80#ibcon#first serial, iclass 31, count 2 2006.201.04:57:14.80#ibcon#enter sib2, iclass 31, count 2 2006.201.04:57:14.80#ibcon#flushed, iclass 31, count 2 2006.201.04:57:14.80#ibcon#about to write, iclass 31, count 2 2006.201.04:57:14.80#ibcon#wrote, iclass 31, count 2 2006.201.04:57:14.80#ibcon#about to read 3, iclass 31, count 2 2006.201.04:57:14.82#ibcon#read 3, iclass 31, count 2 2006.201.04:57:14.82#ibcon#about to read 4, iclass 31, count 2 2006.201.04:57:14.82#ibcon#read 4, iclass 31, count 2 2006.201.04:57:14.82#ibcon#about to read 5, iclass 31, count 2 2006.201.04:57:14.82#ibcon#read 5, iclass 31, count 2 2006.201.04:57:14.82#ibcon#about to read 6, iclass 31, count 2 2006.201.04:57:14.82#ibcon#read 6, iclass 31, count 2 2006.201.04:57:14.82#ibcon#end of sib2, iclass 31, count 2 2006.201.04:57:14.82#ibcon#*mode == 0, iclass 31, count 2 2006.201.04:57:14.82#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.04:57:14.82#ibcon#[25=AT08-04\r\n] 2006.201.04:57:14.82#ibcon#*before write, iclass 31, count 2 2006.201.04:57:14.82#ibcon#enter sib2, iclass 31, count 2 2006.201.04:57:14.82#ibcon#flushed, iclass 31, count 2 2006.201.04:57:14.82#ibcon#about to write, iclass 31, count 2 2006.201.04:57:14.82#ibcon#wrote, iclass 31, count 2 2006.201.04:57:14.82#ibcon#about to read 3, iclass 31, count 2 2006.201.04:57:14.85#ibcon#read 3, iclass 31, count 2 2006.201.04:57:14.85#ibcon#about to read 4, iclass 31, count 2 2006.201.04:57:14.85#ibcon#read 4, iclass 31, count 2 2006.201.04:57:14.85#ibcon#about to read 5, iclass 31, count 2 2006.201.04:57:14.85#ibcon#read 5, iclass 31, count 2 2006.201.04:57:14.85#ibcon#about to read 6, iclass 31, count 2 2006.201.04:57:14.85#ibcon#read 6, iclass 31, count 2 2006.201.04:57:14.85#ibcon#end of sib2, iclass 31, count 2 2006.201.04:57:14.85#ibcon#*after write, iclass 31, count 2 2006.201.04:57:14.85#ibcon#*before return 0, iclass 31, count 2 2006.201.04:57:14.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:57:14.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.04:57:14.85#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.04:57:14.85#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:14.85#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:57:14.97#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:57:14.97#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:57:14.97#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:57:14.97#ibcon#first serial, iclass 31, count 0 2006.201.04:57:14.97#ibcon#enter sib2, iclass 31, count 0 2006.201.04:57:14.97#ibcon#flushed, iclass 31, count 0 2006.201.04:57:14.97#ibcon#about to write, iclass 31, count 0 2006.201.04:57:14.97#ibcon#wrote, iclass 31, count 0 2006.201.04:57:14.97#ibcon#about to read 3, iclass 31, count 0 2006.201.04:57:14.99#ibcon#read 3, iclass 31, count 0 2006.201.04:57:14.99#ibcon#about to read 4, iclass 31, count 0 2006.201.04:57:14.99#ibcon#read 4, iclass 31, count 0 2006.201.04:57:14.99#ibcon#about to read 5, iclass 31, count 0 2006.201.04:57:14.99#ibcon#read 5, iclass 31, count 0 2006.201.04:57:14.99#ibcon#about to read 6, iclass 31, count 0 2006.201.04:57:14.99#ibcon#read 6, iclass 31, count 0 2006.201.04:57:14.99#ibcon#end of sib2, iclass 31, count 0 2006.201.04:57:14.99#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:57:14.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:57:14.99#ibcon#[25=USB\r\n] 2006.201.04:57:14.99#ibcon#*before write, iclass 31, count 0 2006.201.04:57:14.99#ibcon#enter sib2, iclass 31, count 0 2006.201.04:57:14.99#ibcon#flushed, iclass 31, count 0 2006.201.04:57:14.99#ibcon#about to write, iclass 31, count 0 2006.201.04:57:14.99#ibcon#wrote, iclass 31, count 0 2006.201.04:57:14.99#ibcon#about to read 3, iclass 31, count 0 2006.201.04:57:15.02#ibcon#read 3, iclass 31, count 0 2006.201.04:57:15.02#ibcon#about to read 4, iclass 31, count 0 2006.201.04:57:15.02#ibcon#read 4, iclass 31, count 0 2006.201.04:57:15.02#ibcon#about to read 5, iclass 31, count 0 2006.201.04:57:15.02#ibcon#read 5, iclass 31, count 0 2006.201.04:57:15.02#ibcon#about to read 6, iclass 31, count 0 2006.201.04:57:15.02#ibcon#read 6, iclass 31, count 0 2006.201.04:57:15.02#ibcon#end of sib2, iclass 31, count 0 2006.201.04:57:15.02#ibcon#*after write, iclass 31, count 0 2006.201.04:57:15.02#ibcon#*before return 0, iclass 31, count 0 2006.201.04:57:15.02#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:57:15.02#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.04:57:15.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:57:15.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:57:15.02$vck44/vblo=1,629.99 2006.201.04:57:15.02#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.04:57:15.02#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.04:57:15.02#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:15.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:15.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:15.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:15.02#ibcon#enter wrdev, iclass 33, count 0 2006.201.04:57:15.02#ibcon#first serial, iclass 33, count 0 2006.201.04:57:15.02#ibcon#enter sib2, iclass 33, count 0 2006.201.04:57:15.02#ibcon#flushed, iclass 33, count 0 2006.201.04:57:15.02#ibcon#about to write, iclass 33, count 0 2006.201.04:57:15.02#ibcon#wrote, iclass 33, count 0 2006.201.04:57:15.02#ibcon#about to read 3, iclass 33, count 0 2006.201.04:57:15.04#ibcon#read 3, iclass 33, count 0 2006.201.04:57:15.04#ibcon#about to read 4, iclass 33, count 0 2006.201.04:57:15.04#ibcon#read 4, iclass 33, count 0 2006.201.04:57:15.04#ibcon#about to read 5, iclass 33, count 0 2006.201.04:57:15.04#ibcon#read 5, iclass 33, count 0 2006.201.04:57:15.04#ibcon#about to read 6, iclass 33, count 0 2006.201.04:57:15.04#ibcon#read 6, iclass 33, count 0 2006.201.04:57:15.04#ibcon#end of sib2, iclass 33, count 0 2006.201.04:57:15.04#ibcon#*mode == 0, iclass 33, count 0 2006.201.04:57:15.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.04:57:15.04#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.04:57:15.04#ibcon#*before write, iclass 33, count 0 2006.201.04:57:15.04#ibcon#enter sib2, iclass 33, count 0 2006.201.04:57:15.04#ibcon#flushed, iclass 33, count 0 2006.201.04:57:15.04#ibcon#about to write, iclass 33, count 0 2006.201.04:57:15.04#ibcon#wrote, iclass 33, count 0 2006.201.04:57:15.04#ibcon#about to read 3, iclass 33, count 0 2006.201.04:57:15.08#ibcon#read 3, iclass 33, count 0 2006.201.04:57:15.08#ibcon#about to read 4, iclass 33, count 0 2006.201.04:57:15.08#ibcon#read 4, iclass 33, count 0 2006.201.04:57:15.08#ibcon#about to read 5, iclass 33, count 0 2006.201.04:57:15.08#ibcon#read 5, iclass 33, count 0 2006.201.04:57:15.08#ibcon#about to read 6, iclass 33, count 0 2006.201.04:57:15.08#ibcon#read 6, iclass 33, count 0 2006.201.04:57:15.08#ibcon#end of sib2, iclass 33, count 0 2006.201.04:57:15.08#ibcon#*after write, iclass 33, count 0 2006.201.04:57:15.08#ibcon#*before return 0, iclass 33, count 0 2006.201.04:57:15.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:15.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.04:57:15.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.04:57:15.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.04:57:15.08$vck44/vb=1,4 2006.201.04:57:15.08#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.04:57:15.08#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.04:57:15.08#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:15.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:15.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:15.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:15.08#ibcon#enter wrdev, iclass 35, count 2 2006.201.04:57:15.08#ibcon#first serial, iclass 35, count 2 2006.201.04:57:15.08#ibcon#enter sib2, iclass 35, count 2 2006.201.04:57:15.08#ibcon#flushed, iclass 35, count 2 2006.201.04:57:15.08#ibcon#about to write, iclass 35, count 2 2006.201.04:57:15.08#ibcon#wrote, iclass 35, count 2 2006.201.04:57:15.08#ibcon#about to read 3, iclass 35, count 2 2006.201.04:57:15.10#ibcon#read 3, iclass 35, count 2 2006.201.04:57:15.10#ibcon#about to read 4, iclass 35, count 2 2006.201.04:57:15.10#ibcon#read 4, iclass 35, count 2 2006.201.04:57:15.10#ibcon#about to read 5, iclass 35, count 2 2006.201.04:57:15.10#ibcon#read 5, iclass 35, count 2 2006.201.04:57:15.10#ibcon#about to read 6, iclass 35, count 2 2006.201.04:57:15.10#ibcon#read 6, iclass 35, count 2 2006.201.04:57:15.10#ibcon#end of sib2, iclass 35, count 2 2006.201.04:57:15.10#ibcon#*mode == 0, iclass 35, count 2 2006.201.04:57:15.10#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.04:57:15.10#ibcon#[27=AT01-04\r\n] 2006.201.04:57:15.10#ibcon#*before write, iclass 35, count 2 2006.201.04:57:15.10#ibcon#enter sib2, iclass 35, count 2 2006.201.04:57:15.10#ibcon#flushed, iclass 35, count 2 2006.201.04:57:15.10#ibcon#about to write, iclass 35, count 2 2006.201.04:57:15.10#ibcon#wrote, iclass 35, count 2 2006.201.04:57:15.10#ibcon#about to read 3, iclass 35, count 2 2006.201.04:57:15.13#ibcon#read 3, iclass 35, count 2 2006.201.04:57:15.13#ibcon#about to read 4, iclass 35, count 2 2006.201.04:57:15.13#ibcon#read 4, iclass 35, count 2 2006.201.04:57:15.13#ibcon#about to read 5, iclass 35, count 2 2006.201.04:57:15.13#ibcon#read 5, iclass 35, count 2 2006.201.04:57:15.13#ibcon#about to read 6, iclass 35, count 2 2006.201.04:57:15.13#ibcon#read 6, iclass 35, count 2 2006.201.04:57:15.13#ibcon#end of sib2, iclass 35, count 2 2006.201.04:57:15.13#ibcon#*after write, iclass 35, count 2 2006.201.04:57:15.13#ibcon#*before return 0, iclass 35, count 2 2006.201.04:57:15.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:15.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.04:57:15.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.04:57:15.13#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:15.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:15.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:15.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:15.25#ibcon#enter wrdev, iclass 35, count 0 2006.201.04:57:15.25#ibcon#first serial, iclass 35, count 0 2006.201.04:57:15.25#ibcon#enter sib2, iclass 35, count 0 2006.201.04:57:15.25#ibcon#flushed, iclass 35, count 0 2006.201.04:57:15.25#ibcon#about to write, iclass 35, count 0 2006.201.04:57:15.25#ibcon#wrote, iclass 35, count 0 2006.201.04:57:15.25#ibcon#about to read 3, iclass 35, count 0 2006.201.04:57:15.27#ibcon#read 3, iclass 35, count 0 2006.201.04:57:15.27#ibcon#about to read 4, iclass 35, count 0 2006.201.04:57:15.27#ibcon#read 4, iclass 35, count 0 2006.201.04:57:15.27#ibcon#about to read 5, iclass 35, count 0 2006.201.04:57:15.27#ibcon#read 5, iclass 35, count 0 2006.201.04:57:15.27#ibcon#about to read 6, iclass 35, count 0 2006.201.04:57:15.27#ibcon#read 6, iclass 35, count 0 2006.201.04:57:15.27#ibcon#end of sib2, iclass 35, count 0 2006.201.04:57:15.27#ibcon#*mode == 0, iclass 35, count 0 2006.201.04:57:15.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.04:57:15.27#ibcon#[27=USB\r\n] 2006.201.04:57:15.27#ibcon#*before write, iclass 35, count 0 2006.201.04:57:15.27#ibcon#enter sib2, iclass 35, count 0 2006.201.04:57:15.27#ibcon#flushed, iclass 35, count 0 2006.201.04:57:15.27#ibcon#about to write, iclass 35, count 0 2006.201.04:57:15.27#ibcon#wrote, iclass 35, count 0 2006.201.04:57:15.27#ibcon#about to read 3, iclass 35, count 0 2006.201.04:57:15.30#ibcon#read 3, iclass 35, count 0 2006.201.04:57:15.30#ibcon#about to read 4, iclass 35, count 0 2006.201.04:57:15.30#ibcon#read 4, iclass 35, count 0 2006.201.04:57:15.30#ibcon#about to read 5, iclass 35, count 0 2006.201.04:57:15.30#ibcon#read 5, iclass 35, count 0 2006.201.04:57:15.30#ibcon#about to read 6, iclass 35, count 0 2006.201.04:57:15.30#ibcon#read 6, iclass 35, count 0 2006.201.04:57:15.30#ibcon#end of sib2, iclass 35, count 0 2006.201.04:57:15.30#ibcon#*after write, iclass 35, count 0 2006.201.04:57:15.30#ibcon#*before return 0, iclass 35, count 0 2006.201.04:57:15.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:15.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.04:57:15.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.04:57:15.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.04:57:15.30$vck44/vblo=2,634.99 2006.201.04:57:15.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.04:57:15.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.04:57:15.30#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:15.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:15.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:15.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:15.30#ibcon#enter wrdev, iclass 37, count 0 2006.201.04:57:15.30#ibcon#first serial, iclass 37, count 0 2006.201.04:57:15.30#ibcon#enter sib2, iclass 37, count 0 2006.201.04:57:15.30#ibcon#flushed, iclass 37, count 0 2006.201.04:57:15.30#ibcon#about to write, iclass 37, count 0 2006.201.04:57:15.30#ibcon#wrote, iclass 37, count 0 2006.201.04:57:15.30#ibcon#about to read 3, iclass 37, count 0 2006.201.04:57:15.32#ibcon#read 3, iclass 37, count 0 2006.201.04:57:15.32#ibcon#about to read 4, iclass 37, count 0 2006.201.04:57:15.32#ibcon#read 4, iclass 37, count 0 2006.201.04:57:15.32#ibcon#about to read 5, iclass 37, count 0 2006.201.04:57:15.32#ibcon#read 5, iclass 37, count 0 2006.201.04:57:15.32#ibcon#about to read 6, iclass 37, count 0 2006.201.04:57:15.32#ibcon#read 6, iclass 37, count 0 2006.201.04:57:15.32#ibcon#end of sib2, iclass 37, count 0 2006.201.04:57:15.32#ibcon#*mode == 0, iclass 37, count 0 2006.201.04:57:15.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.04:57:15.32#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.04:57:15.32#ibcon#*before write, iclass 37, count 0 2006.201.04:57:15.32#ibcon#enter sib2, iclass 37, count 0 2006.201.04:57:15.32#ibcon#flushed, iclass 37, count 0 2006.201.04:57:15.32#ibcon#about to write, iclass 37, count 0 2006.201.04:57:15.32#ibcon#wrote, iclass 37, count 0 2006.201.04:57:15.32#ibcon#about to read 3, iclass 37, count 0 2006.201.04:57:15.36#ibcon#read 3, iclass 37, count 0 2006.201.04:57:15.36#ibcon#about to read 4, iclass 37, count 0 2006.201.04:57:15.36#ibcon#read 4, iclass 37, count 0 2006.201.04:57:15.36#ibcon#about to read 5, iclass 37, count 0 2006.201.04:57:15.36#ibcon#read 5, iclass 37, count 0 2006.201.04:57:15.36#ibcon#about to read 6, iclass 37, count 0 2006.201.04:57:15.36#ibcon#read 6, iclass 37, count 0 2006.201.04:57:15.36#ibcon#end of sib2, iclass 37, count 0 2006.201.04:57:15.36#ibcon#*after write, iclass 37, count 0 2006.201.04:57:15.36#ibcon#*before return 0, iclass 37, count 0 2006.201.04:57:15.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:15.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.04:57:15.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.04:57:15.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.04:57:15.36$vck44/vb=2,5 2006.201.04:57:15.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.04:57:15.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.04:57:15.36#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:15.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:15.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:15.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:15.42#ibcon#enter wrdev, iclass 39, count 2 2006.201.04:57:15.42#ibcon#first serial, iclass 39, count 2 2006.201.04:57:15.42#ibcon#enter sib2, iclass 39, count 2 2006.201.04:57:15.42#ibcon#flushed, iclass 39, count 2 2006.201.04:57:15.42#ibcon#about to write, iclass 39, count 2 2006.201.04:57:15.42#ibcon#wrote, iclass 39, count 2 2006.201.04:57:15.42#ibcon#about to read 3, iclass 39, count 2 2006.201.04:57:15.44#ibcon#read 3, iclass 39, count 2 2006.201.04:57:15.44#ibcon#about to read 4, iclass 39, count 2 2006.201.04:57:15.44#ibcon#read 4, iclass 39, count 2 2006.201.04:57:15.44#ibcon#about to read 5, iclass 39, count 2 2006.201.04:57:15.44#ibcon#read 5, iclass 39, count 2 2006.201.04:57:15.44#ibcon#about to read 6, iclass 39, count 2 2006.201.04:57:15.44#ibcon#read 6, iclass 39, count 2 2006.201.04:57:15.44#ibcon#end of sib2, iclass 39, count 2 2006.201.04:57:15.44#ibcon#*mode == 0, iclass 39, count 2 2006.201.04:57:15.44#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.04:57:15.44#ibcon#[27=AT02-05\r\n] 2006.201.04:57:15.44#ibcon#*before write, iclass 39, count 2 2006.201.04:57:15.44#ibcon#enter sib2, iclass 39, count 2 2006.201.04:57:15.44#ibcon#flushed, iclass 39, count 2 2006.201.04:57:15.44#ibcon#about to write, iclass 39, count 2 2006.201.04:57:15.44#ibcon#wrote, iclass 39, count 2 2006.201.04:57:15.44#ibcon#about to read 3, iclass 39, count 2 2006.201.04:57:15.54#ibcon#read 3, iclass 39, count 2 2006.201.04:57:15.54#ibcon#about to read 4, iclass 39, count 2 2006.201.04:57:15.54#ibcon#read 4, iclass 39, count 2 2006.201.04:57:15.54#ibcon#about to read 5, iclass 39, count 2 2006.201.04:57:15.54#ibcon#read 5, iclass 39, count 2 2006.201.04:57:15.54#ibcon#about to read 6, iclass 39, count 2 2006.201.04:57:15.54#ibcon#read 6, iclass 39, count 2 2006.201.04:57:15.54#ibcon#end of sib2, iclass 39, count 2 2006.201.04:57:15.54#ibcon#*after write, iclass 39, count 2 2006.201.04:57:15.54#ibcon#*before return 0, iclass 39, count 2 2006.201.04:57:15.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:15.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.04:57:15.54#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.04:57:15.54#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:15.54#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:15.66#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:15.66#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:15.66#ibcon#enter wrdev, iclass 39, count 0 2006.201.04:57:15.66#ibcon#first serial, iclass 39, count 0 2006.201.04:57:15.66#ibcon#enter sib2, iclass 39, count 0 2006.201.04:57:15.66#ibcon#flushed, iclass 39, count 0 2006.201.04:57:15.66#ibcon#about to write, iclass 39, count 0 2006.201.04:57:15.66#ibcon#wrote, iclass 39, count 0 2006.201.04:57:15.66#ibcon#about to read 3, iclass 39, count 0 2006.201.04:57:15.68#ibcon#read 3, iclass 39, count 0 2006.201.04:57:15.68#ibcon#about to read 4, iclass 39, count 0 2006.201.04:57:15.68#ibcon#read 4, iclass 39, count 0 2006.201.04:57:15.68#ibcon#about to read 5, iclass 39, count 0 2006.201.04:57:15.68#ibcon#read 5, iclass 39, count 0 2006.201.04:57:15.68#ibcon#about to read 6, iclass 39, count 0 2006.201.04:57:15.68#ibcon#read 6, iclass 39, count 0 2006.201.04:57:15.68#ibcon#end of sib2, iclass 39, count 0 2006.201.04:57:15.68#ibcon#*mode == 0, iclass 39, count 0 2006.201.04:57:15.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.04:57:15.68#ibcon#[27=USB\r\n] 2006.201.04:57:15.68#ibcon#*before write, iclass 39, count 0 2006.201.04:57:15.68#ibcon#enter sib2, iclass 39, count 0 2006.201.04:57:15.68#ibcon#flushed, iclass 39, count 0 2006.201.04:57:15.68#ibcon#about to write, iclass 39, count 0 2006.201.04:57:15.68#ibcon#wrote, iclass 39, count 0 2006.201.04:57:15.68#ibcon#about to read 3, iclass 39, count 0 2006.201.04:57:15.71#ibcon#read 3, iclass 39, count 0 2006.201.04:57:15.71#ibcon#about to read 4, iclass 39, count 0 2006.201.04:57:15.71#ibcon#read 4, iclass 39, count 0 2006.201.04:57:15.71#ibcon#about to read 5, iclass 39, count 0 2006.201.04:57:15.71#ibcon#read 5, iclass 39, count 0 2006.201.04:57:15.71#ibcon#about to read 6, iclass 39, count 0 2006.201.04:57:15.71#ibcon#read 6, iclass 39, count 0 2006.201.04:57:15.71#ibcon#end of sib2, iclass 39, count 0 2006.201.04:57:15.71#ibcon#*after write, iclass 39, count 0 2006.201.04:57:15.71#ibcon#*before return 0, iclass 39, count 0 2006.201.04:57:15.71#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:15.71#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.04:57:15.71#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.04:57:15.71#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.04:57:15.71$vck44/vblo=3,649.99 2006.201.04:57:15.71#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.04:57:15.71#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.04:57:15.71#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:15.71#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:15.71#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:15.71#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:15.71#ibcon#enter wrdev, iclass 2, count 0 2006.201.04:57:15.71#ibcon#first serial, iclass 2, count 0 2006.201.04:57:15.71#ibcon#enter sib2, iclass 2, count 0 2006.201.04:57:15.71#ibcon#flushed, iclass 2, count 0 2006.201.04:57:15.71#ibcon#about to write, iclass 2, count 0 2006.201.04:57:15.71#ibcon#wrote, iclass 2, count 0 2006.201.04:57:15.71#ibcon#about to read 3, iclass 2, count 0 2006.201.04:57:15.73#ibcon#read 3, iclass 2, count 0 2006.201.04:57:15.73#ibcon#about to read 4, iclass 2, count 0 2006.201.04:57:15.73#ibcon#read 4, iclass 2, count 0 2006.201.04:57:15.73#ibcon#about to read 5, iclass 2, count 0 2006.201.04:57:15.73#ibcon#read 5, iclass 2, count 0 2006.201.04:57:15.73#ibcon#about to read 6, iclass 2, count 0 2006.201.04:57:15.73#ibcon#read 6, iclass 2, count 0 2006.201.04:57:15.73#ibcon#end of sib2, iclass 2, count 0 2006.201.04:57:15.73#ibcon#*mode == 0, iclass 2, count 0 2006.201.04:57:15.73#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.04:57:15.73#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.04:57:15.73#ibcon#*before write, iclass 2, count 0 2006.201.04:57:15.73#ibcon#enter sib2, iclass 2, count 0 2006.201.04:57:15.73#ibcon#flushed, iclass 2, count 0 2006.201.04:57:15.73#ibcon#about to write, iclass 2, count 0 2006.201.04:57:15.73#ibcon#wrote, iclass 2, count 0 2006.201.04:57:15.73#ibcon#about to read 3, iclass 2, count 0 2006.201.04:57:15.77#ibcon#read 3, iclass 2, count 0 2006.201.04:57:15.77#ibcon#about to read 4, iclass 2, count 0 2006.201.04:57:15.77#ibcon#read 4, iclass 2, count 0 2006.201.04:57:15.77#ibcon#about to read 5, iclass 2, count 0 2006.201.04:57:15.77#ibcon#read 5, iclass 2, count 0 2006.201.04:57:15.77#ibcon#about to read 6, iclass 2, count 0 2006.201.04:57:15.77#ibcon#read 6, iclass 2, count 0 2006.201.04:57:15.77#ibcon#end of sib2, iclass 2, count 0 2006.201.04:57:15.77#ibcon#*after write, iclass 2, count 0 2006.201.04:57:15.77#ibcon#*before return 0, iclass 2, count 0 2006.201.04:57:15.77#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:15.77#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.04:57:15.77#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.04:57:15.77#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.04:57:15.77$vck44/vb=3,4 2006.201.04:57:15.77#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.04:57:15.77#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.04:57:15.77#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:15.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:15.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:15.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:15.83#ibcon#enter wrdev, iclass 5, count 2 2006.201.04:57:15.83#ibcon#first serial, iclass 5, count 2 2006.201.04:57:15.83#ibcon#enter sib2, iclass 5, count 2 2006.201.04:57:15.83#ibcon#flushed, iclass 5, count 2 2006.201.04:57:15.83#ibcon#about to write, iclass 5, count 2 2006.201.04:57:15.83#ibcon#wrote, iclass 5, count 2 2006.201.04:57:15.83#ibcon#about to read 3, iclass 5, count 2 2006.201.04:57:15.85#ibcon#read 3, iclass 5, count 2 2006.201.04:57:15.85#ibcon#about to read 4, iclass 5, count 2 2006.201.04:57:15.85#ibcon#read 4, iclass 5, count 2 2006.201.04:57:15.85#ibcon#about to read 5, iclass 5, count 2 2006.201.04:57:15.85#ibcon#read 5, iclass 5, count 2 2006.201.04:57:15.85#ibcon#about to read 6, iclass 5, count 2 2006.201.04:57:15.85#ibcon#read 6, iclass 5, count 2 2006.201.04:57:15.85#ibcon#end of sib2, iclass 5, count 2 2006.201.04:57:15.85#ibcon#*mode == 0, iclass 5, count 2 2006.201.04:57:15.85#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.04:57:15.85#ibcon#[27=AT03-04\r\n] 2006.201.04:57:15.85#ibcon#*before write, iclass 5, count 2 2006.201.04:57:15.85#ibcon#enter sib2, iclass 5, count 2 2006.201.04:57:15.85#ibcon#flushed, iclass 5, count 2 2006.201.04:57:15.85#ibcon#about to write, iclass 5, count 2 2006.201.04:57:15.85#ibcon#wrote, iclass 5, count 2 2006.201.04:57:15.85#ibcon#about to read 3, iclass 5, count 2 2006.201.04:57:15.88#ibcon#read 3, iclass 5, count 2 2006.201.04:57:15.88#ibcon#about to read 4, iclass 5, count 2 2006.201.04:57:15.88#ibcon#read 4, iclass 5, count 2 2006.201.04:57:15.88#ibcon#about to read 5, iclass 5, count 2 2006.201.04:57:15.88#ibcon#read 5, iclass 5, count 2 2006.201.04:57:15.88#ibcon#about to read 6, iclass 5, count 2 2006.201.04:57:15.88#ibcon#read 6, iclass 5, count 2 2006.201.04:57:15.88#ibcon#end of sib2, iclass 5, count 2 2006.201.04:57:15.88#ibcon#*after write, iclass 5, count 2 2006.201.04:57:15.88#ibcon#*before return 0, iclass 5, count 2 2006.201.04:57:15.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:15.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.04:57:15.88#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.04:57:15.88#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:15.88#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:16.00#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:16.00#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:16.00#ibcon#enter wrdev, iclass 5, count 0 2006.201.04:57:16.00#ibcon#first serial, iclass 5, count 0 2006.201.04:57:16.00#ibcon#enter sib2, iclass 5, count 0 2006.201.04:57:16.00#ibcon#flushed, iclass 5, count 0 2006.201.04:57:16.00#ibcon#about to write, iclass 5, count 0 2006.201.04:57:16.00#ibcon#wrote, iclass 5, count 0 2006.201.04:57:16.00#ibcon#about to read 3, iclass 5, count 0 2006.201.04:57:16.02#ibcon#read 3, iclass 5, count 0 2006.201.04:57:16.02#ibcon#about to read 4, iclass 5, count 0 2006.201.04:57:16.02#ibcon#read 4, iclass 5, count 0 2006.201.04:57:16.02#ibcon#about to read 5, iclass 5, count 0 2006.201.04:57:16.02#ibcon#read 5, iclass 5, count 0 2006.201.04:57:16.02#ibcon#about to read 6, iclass 5, count 0 2006.201.04:57:16.02#ibcon#read 6, iclass 5, count 0 2006.201.04:57:16.02#ibcon#end of sib2, iclass 5, count 0 2006.201.04:57:16.02#ibcon#*mode == 0, iclass 5, count 0 2006.201.04:57:16.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.04:57:16.02#ibcon#[27=USB\r\n] 2006.201.04:57:16.02#ibcon#*before write, iclass 5, count 0 2006.201.04:57:16.02#ibcon#enter sib2, iclass 5, count 0 2006.201.04:57:16.02#ibcon#flushed, iclass 5, count 0 2006.201.04:57:16.02#ibcon#about to write, iclass 5, count 0 2006.201.04:57:16.02#ibcon#wrote, iclass 5, count 0 2006.201.04:57:16.02#ibcon#about to read 3, iclass 5, count 0 2006.201.04:57:16.05#ibcon#read 3, iclass 5, count 0 2006.201.04:57:16.05#ibcon#about to read 4, iclass 5, count 0 2006.201.04:57:16.05#ibcon#read 4, iclass 5, count 0 2006.201.04:57:16.05#ibcon#about to read 5, iclass 5, count 0 2006.201.04:57:16.05#ibcon#read 5, iclass 5, count 0 2006.201.04:57:16.05#ibcon#about to read 6, iclass 5, count 0 2006.201.04:57:16.05#ibcon#read 6, iclass 5, count 0 2006.201.04:57:16.05#ibcon#end of sib2, iclass 5, count 0 2006.201.04:57:16.05#ibcon#*after write, iclass 5, count 0 2006.201.04:57:16.05#ibcon#*before return 0, iclass 5, count 0 2006.201.04:57:16.05#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:16.05#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.04:57:16.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.04:57:16.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.04:57:16.05$vck44/vblo=4,679.99 2006.201.04:57:16.05#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.04:57:16.05#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.04:57:16.05#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:16.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:16.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:16.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:16.05#ibcon#enter wrdev, iclass 7, count 0 2006.201.04:57:16.05#ibcon#first serial, iclass 7, count 0 2006.201.04:57:16.05#ibcon#enter sib2, iclass 7, count 0 2006.201.04:57:16.05#ibcon#flushed, iclass 7, count 0 2006.201.04:57:16.05#ibcon#about to write, iclass 7, count 0 2006.201.04:57:16.05#ibcon#wrote, iclass 7, count 0 2006.201.04:57:16.05#ibcon#about to read 3, iclass 7, count 0 2006.201.04:57:16.07#ibcon#read 3, iclass 7, count 0 2006.201.04:57:16.07#ibcon#about to read 4, iclass 7, count 0 2006.201.04:57:16.07#ibcon#read 4, iclass 7, count 0 2006.201.04:57:16.07#ibcon#about to read 5, iclass 7, count 0 2006.201.04:57:16.07#ibcon#read 5, iclass 7, count 0 2006.201.04:57:16.07#ibcon#about to read 6, iclass 7, count 0 2006.201.04:57:16.07#ibcon#read 6, iclass 7, count 0 2006.201.04:57:16.07#ibcon#end of sib2, iclass 7, count 0 2006.201.04:57:16.07#ibcon#*mode == 0, iclass 7, count 0 2006.201.04:57:16.07#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.04:57:16.07#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.04:57:16.07#ibcon#*before write, iclass 7, count 0 2006.201.04:57:16.07#ibcon#enter sib2, iclass 7, count 0 2006.201.04:57:16.07#ibcon#flushed, iclass 7, count 0 2006.201.04:57:16.07#ibcon#about to write, iclass 7, count 0 2006.201.04:57:16.07#ibcon#wrote, iclass 7, count 0 2006.201.04:57:16.07#ibcon#about to read 3, iclass 7, count 0 2006.201.04:57:16.11#ibcon#read 3, iclass 7, count 0 2006.201.04:57:16.11#ibcon#about to read 4, iclass 7, count 0 2006.201.04:57:16.11#ibcon#read 4, iclass 7, count 0 2006.201.04:57:16.11#ibcon#about to read 5, iclass 7, count 0 2006.201.04:57:16.11#ibcon#read 5, iclass 7, count 0 2006.201.04:57:16.11#ibcon#about to read 6, iclass 7, count 0 2006.201.04:57:16.11#ibcon#read 6, iclass 7, count 0 2006.201.04:57:16.11#ibcon#end of sib2, iclass 7, count 0 2006.201.04:57:16.11#ibcon#*after write, iclass 7, count 0 2006.201.04:57:16.11#ibcon#*before return 0, iclass 7, count 0 2006.201.04:57:16.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:16.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.04:57:16.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.04:57:16.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.04:57:16.11$vck44/vb=4,5 2006.201.04:57:16.11#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.04:57:16.11#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.04:57:16.11#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:16.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:16.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:16.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:16.17#ibcon#enter wrdev, iclass 11, count 2 2006.201.04:57:16.17#ibcon#first serial, iclass 11, count 2 2006.201.04:57:16.17#ibcon#enter sib2, iclass 11, count 2 2006.201.04:57:16.17#ibcon#flushed, iclass 11, count 2 2006.201.04:57:16.17#ibcon#about to write, iclass 11, count 2 2006.201.04:57:16.17#ibcon#wrote, iclass 11, count 2 2006.201.04:57:16.17#ibcon#about to read 3, iclass 11, count 2 2006.201.04:57:16.19#ibcon#read 3, iclass 11, count 2 2006.201.04:57:16.19#ibcon#about to read 4, iclass 11, count 2 2006.201.04:57:16.19#ibcon#read 4, iclass 11, count 2 2006.201.04:57:16.19#ibcon#about to read 5, iclass 11, count 2 2006.201.04:57:16.19#ibcon#read 5, iclass 11, count 2 2006.201.04:57:16.19#ibcon#about to read 6, iclass 11, count 2 2006.201.04:57:16.19#ibcon#read 6, iclass 11, count 2 2006.201.04:57:16.19#ibcon#end of sib2, iclass 11, count 2 2006.201.04:57:16.19#ibcon#*mode == 0, iclass 11, count 2 2006.201.04:57:16.19#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.04:57:16.19#ibcon#[27=AT04-05\r\n] 2006.201.04:57:16.19#ibcon#*before write, iclass 11, count 2 2006.201.04:57:16.19#ibcon#enter sib2, iclass 11, count 2 2006.201.04:57:16.19#ibcon#flushed, iclass 11, count 2 2006.201.04:57:16.19#ibcon#about to write, iclass 11, count 2 2006.201.04:57:16.19#ibcon#wrote, iclass 11, count 2 2006.201.04:57:16.19#ibcon#about to read 3, iclass 11, count 2 2006.201.04:57:16.22#ibcon#read 3, iclass 11, count 2 2006.201.04:57:16.22#ibcon#about to read 4, iclass 11, count 2 2006.201.04:57:16.22#ibcon#read 4, iclass 11, count 2 2006.201.04:57:16.22#ibcon#about to read 5, iclass 11, count 2 2006.201.04:57:16.22#ibcon#read 5, iclass 11, count 2 2006.201.04:57:16.22#ibcon#about to read 6, iclass 11, count 2 2006.201.04:57:16.22#ibcon#read 6, iclass 11, count 2 2006.201.04:57:16.22#ibcon#end of sib2, iclass 11, count 2 2006.201.04:57:16.22#ibcon#*after write, iclass 11, count 2 2006.201.04:57:16.22#ibcon#*before return 0, iclass 11, count 2 2006.201.04:57:16.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:16.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.04:57:16.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.04:57:16.22#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:16.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:16.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:16.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:16.34#ibcon#enter wrdev, iclass 11, count 0 2006.201.04:57:16.34#ibcon#first serial, iclass 11, count 0 2006.201.04:57:16.34#ibcon#enter sib2, iclass 11, count 0 2006.201.04:57:16.34#ibcon#flushed, iclass 11, count 0 2006.201.04:57:16.34#ibcon#about to write, iclass 11, count 0 2006.201.04:57:16.34#ibcon#wrote, iclass 11, count 0 2006.201.04:57:16.34#ibcon#about to read 3, iclass 11, count 0 2006.201.04:57:16.36#ibcon#read 3, iclass 11, count 0 2006.201.04:57:16.36#ibcon#about to read 4, iclass 11, count 0 2006.201.04:57:16.36#ibcon#read 4, iclass 11, count 0 2006.201.04:57:16.36#ibcon#about to read 5, iclass 11, count 0 2006.201.04:57:16.36#ibcon#read 5, iclass 11, count 0 2006.201.04:57:16.36#ibcon#about to read 6, iclass 11, count 0 2006.201.04:57:16.36#ibcon#read 6, iclass 11, count 0 2006.201.04:57:16.36#ibcon#end of sib2, iclass 11, count 0 2006.201.04:57:16.36#ibcon#*mode == 0, iclass 11, count 0 2006.201.04:57:16.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.04:57:16.36#ibcon#[27=USB\r\n] 2006.201.04:57:16.36#ibcon#*before write, iclass 11, count 0 2006.201.04:57:16.36#ibcon#enter sib2, iclass 11, count 0 2006.201.04:57:16.36#ibcon#flushed, iclass 11, count 0 2006.201.04:57:16.36#ibcon#about to write, iclass 11, count 0 2006.201.04:57:16.36#ibcon#wrote, iclass 11, count 0 2006.201.04:57:16.36#ibcon#about to read 3, iclass 11, count 0 2006.201.04:57:16.39#ibcon#read 3, iclass 11, count 0 2006.201.04:57:16.39#ibcon#about to read 4, iclass 11, count 0 2006.201.04:57:16.39#ibcon#read 4, iclass 11, count 0 2006.201.04:57:16.39#ibcon#about to read 5, iclass 11, count 0 2006.201.04:57:16.39#ibcon#read 5, iclass 11, count 0 2006.201.04:57:16.39#ibcon#about to read 6, iclass 11, count 0 2006.201.04:57:16.39#ibcon#read 6, iclass 11, count 0 2006.201.04:57:16.39#ibcon#end of sib2, iclass 11, count 0 2006.201.04:57:16.39#ibcon#*after write, iclass 11, count 0 2006.201.04:57:16.39#ibcon#*before return 0, iclass 11, count 0 2006.201.04:57:16.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:16.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.04:57:16.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.04:57:16.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.04:57:16.39$vck44/vblo=5,709.99 2006.201.04:57:16.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.04:57:16.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.04:57:16.39#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:16.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:16.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:16.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:16.39#ibcon#enter wrdev, iclass 13, count 0 2006.201.04:57:16.39#ibcon#first serial, iclass 13, count 0 2006.201.04:57:16.39#ibcon#enter sib2, iclass 13, count 0 2006.201.04:57:16.39#ibcon#flushed, iclass 13, count 0 2006.201.04:57:16.39#ibcon#about to write, iclass 13, count 0 2006.201.04:57:16.39#ibcon#wrote, iclass 13, count 0 2006.201.04:57:16.39#ibcon#about to read 3, iclass 13, count 0 2006.201.04:57:16.41#ibcon#read 3, iclass 13, count 0 2006.201.04:57:16.41#ibcon#about to read 4, iclass 13, count 0 2006.201.04:57:16.41#ibcon#read 4, iclass 13, count 0 2006.201.04:57:16.41#ibcon#about to read 5, iclass 13, count 0 2006.201.04:57:16.41#ibcon#read 5, iclass 13, count 0 2006.201.04:57:16.41#ibcon#about to read 6, iclass 13, count 0 2006.201.04:57:16.41#ibcon#read 6, iclass 13, count 0 2006.201.04:57:16.41#ibcon#end of sib2, iclass 13, count 0 2006.201.04:57:16.41#ibcon#*mode == 0, iclass 13, count 0 2006.201.04:57:16.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.04:57:16.41#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.04:57:16.41#ibcon#*before write, iclass 13, count 0 2006.201.04:57:16.41#ibcon#enter sib2, iclass 13, count 0 2006.201.04:57:16.41#ibcon#flushed, iclass 13, count 0 2006.201.04:57:16.41#ibcon#about to write, iclass 13, count 0 2006.201.04:57:16.41#ibcon#wrote, iclass 13, count 0 2006.201.04:57:16.41#ibcon#about to read 3, iclass 13, count 0 2006.201.04:57:16.45#ibcon#read 3, iclass 13, count 0 2006.201.04:57:16.45#ibcon#about to read 4, iclass 13, count 0 2006.201.04:57:16.45#ibcon#read 4, iclass 13, count 0 2006.201.04:57:16.45#ibcon#about to read 5, iclass 13, count 0 2006.201.04:57:16.45#ibcon#read 5, iclass 13, count 0 2006.201.04:57:16.45#ibcon#about to read 6, iclass 13, count 0 2006.201.04:57:16.45#ibcon#read 6, iclass 13, count 0 2006.201.04:57:16.45#ibcon#end of sib2, iclass 13, count 0 2006.201.04:57:16.45#ibcon#*after write, iclass 13, count 0 2006.201.04:57:16.45#ibcon#*before return 0, iclass 13, count 0 2006.201.04:57:16.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:16.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.04:57:16.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.04:57:16.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.04:57:16.45$vck44/vb=5,4 2006.201.04:57:16.45#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.04:57:16.45#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.04:57:16.45#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:16.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:16.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:16.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:16.51#ibcon#enter wrdev, iclass 15, count 2 2006.201.04:57:16.51#ibcon#first serial, iclass 15, count 2 2006.201.04:57:16.51#ibcon#enter sib2, iclass 15, count 2 2006.201.04:57:16.51#ibcon#flushed, iclass 15, count 2 2006.201.04:57:16.51#ibcon#about to write, iclass 15, count 2 2006.201.04:57:16.51#ibcon#wrote, iclass 15, count 2 2006.201.04:57:16.51#ibcon#about to read 3, iclass 15, count 2 2006.201.04:57:16.53#ibcon#read 3, iclass 15, count 2 2006.201.04:57:16.53#ibcon#about to read 4, iclass 15, count 2 2006.201.04:57:16.53#ibcon#read 4, iclass 15, count 2 2006.201.04:57:16.53#ibcon#about to read 5, iclass 15, count 2 2006.201.04:57:16.53#ibcon#read 5, iclass 15, count 2 2006.201.04:57:16.53#ibcon#about to read 6, iclass 15, count 2 2006.201.04:57:16.53#ibcon#read 6, iclass 15, count 2 2006.201.04:57:16.53#ibcon#end of sib2, iclass 15, count 2 2006.201.04:57:16.53#ibcon#*mode == 0, iclass 15, count 2 2006.201.04:57:16.53#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.04:57:16.53#ibcon#[27=AT05-04\r\n] 2006.201.04:57:16.53#ibcon#*before write, iclass 15, count 2 2006.201.04:57:16.53#ibcon#enter sib2, iclass 15, count 2 2006.201.04:57:16.53#ibcon#flushed, iclass 15, count 2 2006.201.04:57:16.53#ibcon#about to write, iclass 15, count 2 2006.201.04:57:16.53#ibcon#wrote, iclass 15, count 2 2006.201.04:57:16.53#ibcon#about to read 3, iclass 15, count 2 2006.201.04:57:16.56#ibcon#read 3, iclass 15, count 2 2006.201.04:57:16.56#ibcon#about to read 4, iclass 15, count 2 2006.201.04:57:16.56#ibcon#read 4, iclass 15, count 2 2006.201.04:57:16.63#ibcon#about to read 5, iclass 15, count 2 2006.201.04:57:16.63#ibcon#read 5, iclass 15, count 2 2006.201.04:57:16.63#ibcon#about to read 6, iclass 15, count 2 2006.201.04:57:16.63#ibcon#read 6, iclass 15, count 2 2006.201.04:57:16.63#ibcon#end of sib2, iclass 15, count 2 2006.201.04:57:16.63#ibcon#*after write, iclass 15, count 2 2006.201.04:57:16.63#ibcon#*before return 0, iclass 15, count 2 2006.201.04:57:16.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:16.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.04:57:16.63#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.04:57:16.64#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:16.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:16.75#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:16.75#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:16.75#ibcon#enter wrdev, iclass 15, count 0 2006.201.04:57:16.75#ibcon#first serial, iclass 15, count 0 2006.201.04:57:16.75#ibcon#enter sib2, iclass 15, count 0 2006.201.04:57:16.75#ibcon#flushed, iclass 15, count 0 2006.201.04:57:16.75#ibcon#about to write, iclass 15, count 0 2006.201.04:57:16.75#ibcon#wrote, iclass 15, count 0 2006.201.04:57:16.75#ibcon#about to read 3, iclass 15, count 0 2006.201.04:57:16.77#ibcon#read 3, iclass 15, count 0 2006.201.04:57:16.77#ibcon#about to read 4, iclass 15, count 0 2006.201.04:57:16.77#ibcon#read 4, iclass 15, count 0 2006.201.04:57:16.77#ibcon#about to read 5, iclass 15, count 0 2006.201.04:57:16.77#ibcon#read 5, iclass 15, count 0 2006.201.04:57:16.77#ibcon#about to read 6, iclass 15, count 0 2006.201.04:57:16.77#ibcon#read 6, iclass 15, count 0 2006.201.04:57:16.77#ibcon#end of sib2, iclass 15, count 0 2006.201.04:57:16.77#ibcon#*mode == 0, iclass 15, count 0 2006.201.04:57:16.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.04:57:16.77#ibcon#[27=USB\r\n] 2006.201.04:57:16.77#ibcon#*before write, iclass 15, count 0 2006.201.04:57:16.77#ibcon#enter sib2, iclass 15, count 0 2006.201.04:57:16.77#ibcon#flushed, iclass 15, count 0 2006.201.04:57:16.77#ibcon#about to write, iclass 15, count 0 2006.201.04:57:16.77#ibcon#wrote, iclass 15, count 0 2006.201.04:57:16.77#ibcon#about to read 3, iclass 15, count 0 2006.201.04:57:16.80#ibcon#read 3, iclass 15, count 0 2006.201.04:57:16.80#ibcon#about to read 4, iclass 15, count 0 2006.201.04:57:16.80#ibcon#read 4, iclass 15, count 0 2006.201.04:57:16.80#ibcon#about to read 5, iclass 15, count 0 2006.201.04:57:16.80#ibcon#read 5, iclass 15, count 0 2006.201.04:57:16.80#ibcon#about to read 6, iclass 15, count 0 2006.201.04:57:16.80#ibcon#read 6, iclass 15, count 0 2006.201.04:57:16.80#ibcon#end of sib2, iclass 15, count 0 2006.201.04:57:16.80#ibcon#*after write, iclass 15, count 0 2006.201.04:57:16.80#ibcon#*before return 0, iclass 15, count 0 2006.201.04:57:16.80#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:16.80#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.04:57:16.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.04:57:16.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.04:57:16.80$vck44/vblo=6,719.99 2006.201.04:57:16.80#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.04:57:16.80#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.04:57:16.80#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:16.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:16.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:16.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:16.80#ibcon#enter wrdev, iclass 17, count 0 2006.201.04:57:16.80#ibcon#first serial, iclass 17, count 0 2006.201.04:57:16.80#ibcon#enter sib2, iclass 17, count 0 2006.201.04:57:16.80#ibcon#flushed, iclass 17, count 0 2006.201.04:57:16.80#ibcon#about to write, iclass 17, count 0 2006.201.04:57:16.80#ibcon#wrote, iclass 17, count 0 2006.201.04:57:16.80#ibcon#about to read 3, iclass 17, count 0 2006.201.04:57:16.82#ibcon#read 3, iclass 17, count 0 2006.201.04:57:16.82#ibcon#about to read 4, iclass 17, count 0 2006.201.04:57:16.82#ibcon#read 4, iclass 17, count 0 2006.201.04:57:16.82#ibcon#about to read 5, iclass 17, count 0 2006.201.04:57:16.82#ibcon#read 5, iclass 17, count 0 2006.201.04:57:16.82#ibcon#about to read 6, iclass 17, count 0 2006.201.04:57:16.82#ibcon#read 6, iclass 17, count 0 2006.201.04:57:16.82#ibcon#end of sib2, iclass 17, count 0 2006.201.04:57:16.82#ibcon#*mode == 0, iclass 17, count 0 2006.201.04:57:16.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.04:57:16.82#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.04:57:16.82#ibcon#*before write, iclass 17, count 0 2006.201.04:57:16.82#ibcon#enter sib2, iclass 17, count 0 2006.201.04:57:16.82#ibcon#flushed, iclass 17, count 0 2006.201.04:57:16.82#ibcon#about to write, iclass 17, count 0 2006.201.04:57:16.82#ibcon#wrote, iclass 17, count 0 2006.201.04:57:16.82#ibcon#about to read 3, iclass 17, count 0 2006.201.04:57:16.86#ibcon#read 3, iclass 17, count 0 2006.201.04:57:16.86#ibcon#about to read 4, iclass 17, count 0 2006.201.04:57:16.86#ibcon#read 4, iclass 17, count 0 2006.201.04:57:16.86#ibcon#about to read 5, iclass 17, count 0 2006.201.04:57:16.86#ibcon#read 5, iclass 17, count 0 2006.201.04:57:16.86#ibcon#about to read 6, iclass 17, count 0 2006.201.04:57:16.86#ibcon#read 6, iclass 17, count 0 2006.201.04:57:16.86#ibcon#end of sib2, iclass 17, count 0 2006.201.04:57:16.86#ibcon#*after write, iclass 17, count 0 2006.201.04:57:16.86#ibcon#*before return 0, iclass 17, count 0 2006.201.04:57:16.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:16.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.04:57:16.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.04:57:16.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.04:57:16.86$vck44/vb=6,4 2006.201.04:57:16.86#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.04:57:16.86#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.04:57:16.86#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:16.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:16.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:16.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:16.92#ibcon#enter wrdev, iclass 19, count 2 2006.201.04:57:16.92#ibcon#first serial, iclass 19, count 2 2006.201.04:57:16.92#ibcon#enter sib2, iclass 19, count 2 2006.201.04:57:16.92#ibcon#flushed, iclass 19, count 2 2006.201.04:57:16.92#ibcon#about to write, iclass 19, count 2 2006.201.04:57:16.92#ibcon#wrote, iclass 19, count 2 2006.201.04:57:16.92#ibcon#about to read 3, iclass 19, count 2 2006.201.04:57:16.94#ibcon#read 3, iclass 19, count 2 2006.201.04:57:16.94#ibcon#about to read 4, iclass 19, count 2 2006.201.04:57:16.94#ibcon#read 4, iclass 19, count 2 2006.201.04:57:16.94#ibcon#about to read 5, iclass 19, count 2 2006.201.04:57:16.94#ibcon#read 5, iclass 19, count 2 2006.201.04:57:16.94#ibcon#about to read 6, iclass 19, count 2 2006.201.04:57:16.94#ibcon#read 6, iclass 19, count 2 2006.201.04:57:16.94#ibcon#end of sib2, iclass 19, count 2 2006.201.04:57:16.94#ibcon#*mode == 0, iclass 19, count 2 2006.201.04:57:16.94#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.04:57:16.94#ibcon#[27=AT06-04\r\n] 2006.201.04:57:16.94#ibcon#*before write, iclass 19, count 2 2006.201.04:57:16.94#ibcon#enter sib2, iclass 19, count 2 2006.201.04:57:16.94#ibcon#flushed, iclass 19, count 2 2006.201.04:57:16.94#ibcon#about to write, iclass 19, count 2 2006.201.04:57:16.94#ibcon#wrote, iclass 19, count 2 2006.201.04:57:16.94#ibcon#about to read 3, iclass 19, count 2 2006.201.04:57:16.97#ibcon#read 3, iclass 19, count 2 2006.201.04:57:16.97#ibcon#about to read 4, iclass 19, count 2 2006.201.04:57:16.97#ibcon#read 4, iclass 19, count 2 2006.201.04:57:16.97#ibcon#about to read 5, iclass 19, count 2 2006.201.04:57:16.97#ibcon#read 5, iclass 19, count 2 2006.201.04:57:16.97#ibcon#about to read 6, iclass 19, count 2 2006.201.04:57:16.97#ibcon#read 6, iclass 19, count 2 2006.201.04:57:16.97#ibcon#end of sib2, iclass 19, count 2 2006.201.04:57:16.97#ibcon#*after write, iclass 19, count 2 2006.201.04:57:16.97#ibcon#*before return 0, iclass 19, count 2 2006.201.04:57:16.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:16.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.04:57:16.97#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.04:57:16.97#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:16.97#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:17.09#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:17.09#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:17.09#ibcon#enter wrdev, iclass 19, count 0 2006.201.04:57:17.09#ibcon#first serial, iclass 19, count 0 2006.201.04:57:17.09#ibcon#enter sib2, iclass 19, count 0 2006.201.04:57:17.09#ibcon#flushed, iclass 19, count 0 2006.201.04:57:17.09#ibcon#about to write, iclass 19, count 0 2006.201.04:57:17.09#ibcon#wrote, iclass 19, count 0 2006.201.04:57:17.09#ibcon#about to read 3, iclass 19, count 0 2006.201.04:57:17.11#ibcon#read 3, iclass 19, count 0 2006.201.04:57:17.11#ibcon#about to read 4, iclass 19, count 0 2006.201.04:57:17.11#ibcon#read 4, iclass 19, count 0 2006.201.04:57:17.11#ibcon#about to read 5, iclass 19, count 0 2006.201.04:57:17.11#ibcon#read 5, iclass 19, count 0 2006.201.04:57:17.11#ibcon#about to read 6, iclass 19, count 0 2006.201.04:57:17.11#ibcon#read 6, iclass 19, count 0 2006.201.04:57:17.11#ibcon#end of sib2, iclass 19, count 0 2006.201.04:57:17.11#ibcon#*mode == 0, iclass 19, count 0 2006.201.04:57:17.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.04:57:17.11#ibcon#[27=USB\r\n] 2006.201.04:57:17.11#ibcon#*before write, iclass 19, count 0 2006.201.04:57:17.11#ibcon#enter sib2, iclass 19, count 0 2006.201.04:57:17.11#ibcon#flushed, iclass 19, count 0 2006.201.04:57:17.11#ibcon#about to write, iclass 19, count 0 2006.201.04:57:17.11#ibcon#wrote, iclass 19, count 0 2006.201.04:57:17.11#ibcon#about to read 3, iclass 19, count 0 2006.201.04:57:17.14#ibcon#read 3, iclass 19, count 0 2006.201.04:57:17.14#ibcon#about to read 4, iclass 19, count 0 2006.201.04:57:17.14#ibcon#read 4, iclass 19, count 0 2006.201.04:57:17.14#ibcon#about to read 5, iclass 19, count 0 2006.201.04:57:17.14#ibcon#read 5, iclass 19, count 0 2006.201.04:57:17.14#ibcon#about to read 6, iclass 19, count 0 2006.201.04:57:17.14#ibcon#read 6, iclass 19, count 0 2006.201.04:57:17.14#ibcon#end of sib2, iclass 19, count 0 2006.201.04:57:17.14#ibcon#*after write, iclass 19, count 0 2006.201.04:57:17.14#ibcon#*before return 0, iclass 19, count 0 2006.201.04:57:17.14#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:17.14#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.04:57:17.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.04:57:17.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.04:57:17.14$vck44/vblo=7,734.99 2006.201.04:57:17.14#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.04:57:17.14#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.04:57:17.14#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:17.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:57:17.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:57:17.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:57:17.14#ibcon#enter wrdev, iclass 21, count 0 2006.201.04:57:17.14#ibcon#first serial, iclass 21, count 0 2006.201.04:57:17.14#ibcon#enter sib2, iclass 21, count 0 2006.201.04:57:17.14#ibcon#flushed, iclass 21, count 0 2006.201.04:57:17.14#ibcon#about to write, iclass 21, count 0 2006.201.04:57:17.14#ibcon#wrote, iclass 21, count 0 2006.201.04:57:17.14#ibcon#about to read 3, iclass 21, count 0 2006.201.04:57:17.16#ibcon#read 3, iclass 21, count 0 2006.201.04:57:17.16#ibcon#about to read 4, iclass 21, count 0 2006.201.04:57:17.16#ibcon#read 4, iclass 21, count 0 2006.201.04:57:17.16#ibcon#about to read 5, iclass 21, count 0 2006.201.04:57:17.16#ibcon#read 5, iclass 21, count 0 2006.201.04:57:17.16#ibcon#about to read 6, iclass 21, count 0 2006.201.04:57:17.16#ibcon#read 6, iclass 21, count 0 2006.201.04:57:17.16#ibcon#end of sib2, iclass 21, count 0 2006.201.04:57:17.16#ibcon#*mode == 0, iclass 21, count 0 2006.201.04:57:17.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.04:57:17.16#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.04:57:17.16#ibcon#*before write, iclass 21, count 0 2006.201.04:57:17.16#ibcon#enter sib2, iclass 21, count 0 2006.201.04:57:17.16#ibcon#flushed, iclass 21, count 0 2006.201.04:57:17.16#ibcon#about to write, iclass 21, count 0 2006.201.04:57:17.16#ibcon#wrote, iclass 21, count 0 2006.201.04:57:17.16#ibcon#about to read 3, iclass 21, count 0 2006.201.04:57:17.20#ibcon#read 3, iclass 21, count 0 2006.201.04:57:17.20#ibcon#about to read 4, iclass 21, count 0 2006.201.04:57:17.20#ibcon#read 4, iclass 21, count 0 2006.201.04:57:17.20#ibcon#about to read 5, iclass 21, count 0 2006.201.04:57:17.20#ibcon#read 5, iclass 21, count 0 2006.201.04:57:17.20#ibcon#about to read 6, iclass 21, count 0 2006.201.04:57:17.20#ibcon#read 6, iclass 21, count 0 2006.201.04:57:17.20#ibcon#end of sib2, iclass 21, count 0 2006.201.04:57:17.20#ibcon#*after write, iclass 21, count 0 2006.201.04:57:17.20#ibcon#*before return 0, iclass 21, count 0 2006.201.04:57:17.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:57:17.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.04:57:17.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.04:57:17.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.04:57:17.20$vck44/vb=7,4 2006.201.04:57:17.20#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.04:57:17.20#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.04:57:17.20#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:17.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:57:17.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:57:17.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:57:17.26#ibcon#enter wrdev, iclass 23, count 2 2006.201.04:57:17.26#ibcon#first serial, iclass 23, count 2 2006.201.04:57:17.26#ibcon#enter sib2, iclass 23, count 2 2006.201.04:57:17.26#ibcon#flushed, iclass 23, count 2 2006.201.04:57:17.26#ibcon#about to write, iclass 23, count 2 2006.201.04:57:17.26#ibcon#wrote, iclass 23, count 2 2006.201.04:57:17.26#ibcon#about to read 3, iclass 23, count 2 2006.201.04:57:17.28#ibcon#read 3, iclass 23, count 2 2006.201.04:57:17.28#ibcon#about to read 4, iclass 23, count 2 2006.201.04:57:17.28#ibcon#read 4, iclass 23, count 2 2006.201.04:57:17.28#ibcon#about to read 5, iclass 23, count 2 2006.201.04:57:17.28#ibcon#read 5, iclass 23, count 2 2006.201.04:57:17.28#ibcon#about to read 6, iclass 23, count 2 2006.201.04:57:17.28#ibcon#read 6, iclass 23, count 2 2006.201.04:57:17.28#ibcon#end of sib2, iclass 23, count 2 2006.201.04:57:17.28#ibcon#*mode == 0, iclass 23, count 2 2006.201.04:57:17.28#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.04:57:17.28#ibcon#[27=AT07-04\r\n] 2006.201.04:57:17.28#ibcon#*before write, iclass 23, count 2 2006.201.04:57:17.28#ibcon#enter sib2, iclass 23, count 2 2006.201.04:57:17.28#ibcon#flushed, iclass 23, count 2 2006.201.04:57:17.28#ibcon#about to write, iclass 23, count 2 2006.201.04:57:17.28#ibcon#wrote, iclass 23, count 2 2006.201.04:57:17.28#ibcon#about to read 3, iclass 23, count 2 2006.201.04:57:17.31#ibcon#read 3, iclass 23, count 2 2006.201.04:57:17.31#ibcon#about to read 4, iclass 23, count 2 2006.201.04:57:17.31#ibcon#read 4, iclass 23, count 2 2006.201.04:57:17.31#ibcon#about to read 5, iclass 23, count 2 2006.201.04:57:17.31#ibcon#read 5, iclass 23, count 2 2006.201.04:57:17.31#ibcon#about to read 6, iclass 23, count 2 2006.201.04:57:17.31#ibcon#read 6, iclass 23, count 2 2006.201.04:57:17.31#ibcon#end of sib2, iclass 23, count 2 2006.201.04:57:17.31#ibcon#*after write, iclass 23, count 2 2006.201.04:57:17.31#ibcon#*before return 0, iclass 23, count 2 2006.201.04:57:17.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:57:17.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.04:57:17.31#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.04:57:17.31#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:17.31#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:57:17.43#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:57:17.43#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:57:17.43#ibcon#enter wrdev, iclass 23, count 0 2006.201.04:57:17.43#ibcon#first serial, iclass 23, count 0 2006.201.04:57:17.43#ibcon#enter sib2, iclass 23, count 0 2006.201.04:57:17.43#ibcon#flushed, iclass 23, count 0 2006.201.04:57:17.43#ibcon#about to write, iclass 23, count 0 2006.201.04:57:17.43#ibcon#wrote, iclass 23, count 0 2006.201.04:57:17.43#ibcon#about to read 3, iclass 23, count 0 2006.201.04:57:17.45#ibcon#read 3, iclass 23, count 0 2006.201.04:57:17.45#ibcon#about to read 4, iclass 23, count 0 2006.201.04:57:17.45#ibcon#read 4, iclass 23, count 0 2006.201.04:57:17.45#ibcon#about to read 5, iclass 23, count 0 2006.201.04:57:17.45#ibcon#read 5, iclass 23, count 0 2006.201.04:57:17.45#ibcon#about to read 6, iclass 23, count 0 2006.201.04:57:17.45#ibcon#read 6, iclass 23, count 0 2006.201.04:57:17.45#ibcon#end of sib2, iclass 23, count 0 2006.201.04:57:17.45#ibcon#*mode == 0, iclass 23, count 0 2006.201.04:57:17.45#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.04:57:17.45#ibcon#[27=USB\r\n] 2006.201.04:57:17.45#ibcon#*before write, iclass 23, count 0 2006.201.04:57:17.45#ibcon#enter sib2, iclass 23, count 0 2006.201.04:57:17.45#ibcon#flushed, iclass 23, count 0 2006.201.04:57:17.45#ibcon#about to write, iclass 23, count 0 2006.201.04:57:17.45#ibcon#wrote, iclass 23, count 0 2006.201.04:57:17.45#ibcon#about to read 3, iclass 23, count 0 2006.201.04:57:17.48#ibcon#read 3, iclass 23, count 0 2006.201.04:57:17.48#ibcon#about to read 4, iclass 23, count 0 2006.201.04:57:17.48#ibcon#read 4, iclass 23, count 0 2006.201.04:57:17.48#ibcon#about to read 5, iclass 23, count 0 2006.201.04:57:17.48#ibcon#read 5, iclass 23, count 0 2006.201.04:57:17.48#ibcon#about to read 6, iclass 23, count 0 2006.201.04:57:17.48#ibcon#read 6, iclass 23, count 0 2006.201.04:57:17.48#ibcon#end of sib2, iclass 23, count 0 2006.201.04:57:17.48#ibcon#*after write, iclass 23, count 0 2006.201.04:57:17.48#ibcon#*before return 0, iclass 23, count 0 2006.201.04:57:17.48#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:57:17.48#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.04:57:17.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.04:57:17.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.04:57:17.48$vck44/vblo=8,744.99 2006.201.04:57:17.48#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.04:57:17.48#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.04:57:17.48#ibcon#ireg 17 cls_cnt 0 2006.201.04:57:17.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:17.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:17.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:17.48#ibcon#enter wrdev, iclass 25, count 0 2006.201.04:57:17.48#ibcon#first serial, iclass 25, count 0 2006.201.04:57:17.48#ibcon#enter sib2, iclass 25, count 0 2006.201.04:57:17.48#ibcon#flushed, iclass 25, count 0 2006.201.04:57:17.48#ibcon#about to write, iclass 25, count 0 2006.201.04:57:17.48#ibcon#wrote, iclass 25, count 0 2006.201.04:57:17.48#ibcon#about to read 3, iclass 25, count 0 2006.201.04:57:17.50#ibcon#read 3, iclass 25, count 0 2006.201.04:57:17.50#ibcon#about to read 4, iclass 25, count 0 2006.201.04:57:17.50#ibcon#read 4, iclass 25, count 0 2006.201.04:57:17.50#ibcon#about to read 5, iclass 25, count 0 2006.201.04:57:17.50#ibcon#read 5, iclass 25, count 0 2006.201.04:57:17.50#ibcon#about to read 6, iclass 25, count 0 2006.201.04:57:17.50#ibcon#read 6, iclass 25, count 0 2006.201.04:57:17.50#ibcon#end of sib2, iclass 25, count 0 2006.201.04:57:17.50#ibcon#*mode == 0, iclass 25, count 0 2006.201.04:57:17.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.04:57:17.50#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.04:57:17.50#ibcon#*before write, iclass 25, count 0 2006.201.04:57:17.50#ibcon#enter sib2, iclass 25, count 0 2006.201.04:57:17.50#ibcon#flushed, iclass 25, count 0 2006.201.04:57:17.50#ibcon#about to write, iclass 25, count 0 2006.201.04:57:17.50#ibcon#wrote, iclass 25, count 0 2006.201.04:57:17.50#ibcon#about to read 3, iclass 25, count 0 2006.201.04:57:17.54#ibcon#read 3, iclass 25, count 0 2006.201.04:57:17.54#ibcon#about to read 4, iclass 25, count 0 2006.201.04:57:17.54#ibcon#read 4, iclass 25, count 0 2006.201.04:57:17.54#ibcon#about to read 5, iclass 25, count 0 2006.201.04:57:17.54#ibcon#read 5, iclass 25, count 0 2006.201.04:57:17.54#ibcon#about to read 6, iclass 25, count 0 2006.201.04:57:17.54#ibcon#read 6, iclass 25, count 0 2006.201.04:57:17.54#ibcon#end of sib2, iclass 25, count 0 2006.201.04:57:17.54#ibcon#*after write, iclass 25, count 0 2006.201.04:57:17.54#ibcon#*before return 0, iclass 25, count 0 2006.201.04:57:17.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:17.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.04:57:17.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.04:57:17.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.04:57:17.54$vck44/vb=8,4 2006.201.04:57:17.54#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.04:57:17.54#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.04:57:17.54#ibcon#ireg 11 cls_cnt 2 2006.201.04:57:17.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:17.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:17.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:17.60#ibcon#enter wrdev, iclass 27, count 2 2006.201.04:57:17.60#ibcon#first serial, iclass 27, count 2 2006.201.04:57:17.60#ibcon#enter sib2, iclass 27, count 2 2006.201.04:57:17.60#ibcon#flushed, iclass 27, count 2 2006.201.04:57:17.60#ibcon#about to write, iclass 27, count 2 2006.201.04:57:17.60#ibcon#wrote, iclass 27, count 2 2006.201.04:57:17.60#ibcon#about to read 3, iclass 27, count 2 2006.201.04:57:17.62#ibcon#read 3, iclass 27, count 2 2006.201.04:57:17.62#ibcon#about to read 4, iclass 27, count 2 2006.201.04:57:17.62#ibcon#read 4, iclass 27, count 2 2006.201.04:57:17.62#ibcon#about to read 5, iclass 27, count 2 2006.201.04:57:17.62#ibcon#read 5, iclass 27, count 2 2006.201.04:57:17.62#ibcon#about to read 6, iclass 27, count 2 2006.201.04:57:17.62#ibcon#read 6, iclass 27, count 2 2006.201.04:57:17.62#ibcon#end of sib2, iclass 27, count 2 2006.201.04:57:17.62#ibcon#*mode == 0, iclass 27, count 2 2006.201.04:57:17.62#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.04:57:17.62#ibcon#[27=AT08-04\r\n] 2006.201.04:57:17.62#ibcon#*before write, iclass 27, count 2 2006.201.04:57:17.62#ibcon#enter sib2, iclass 27, count 2 2006.201.04:57:17.62#ibcon#flushed, iclass 27, count 2 2006.201.04:57:17.62#ibcon#about to write, iclass 27, count 2 2006.201.04:57:17.62#ibcon#wrote, iclass 27, count 2 2006.201.04:57:17.62#ibcon#about to read 3, iclass 27, count 2 2006.201.04:57:17.65#ibcon#read 3, iclass 27, count 2 2006.201.04:57:17.68#ibcon#about to read 4, iclass 27, count 2 2006.201.04:57:17.68#ibcon#read 4, iclass 27, count 2 2006.201.04:57:17.68#ibcon#about to read 5, iclass 27, count 2 2006.201.04:57:17.68#ibcon#read 5, iclass 27, count 2 2006.201.04:57:17.68#ibcon#about to read 6, iclass 27, count 2 2006.201.04:57:17.68#ibcon#read 6, iclass 27, count 2 2006.201.04:57:17.68#ibcon#end of sib2, iclass 27, count 2 2006.201.04:57:17.68#ibcon#*after write, iclass 27, count 2 2006.201.04:57:17.68#ibcon#*before return 0, iclass 27, count 2 2006.201.04:57:17.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:17.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.04:57:17.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.04:57:17.69#ibcon#ireg 7 cls_cnt 0 2006.201.04:57:17.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:17.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:17.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:17.81#ibcon#enter wrdev, iclass 27, count 0 2006.201.04:57:17.81#ibcon#first serial, iclass 27, count 0 2006.201.04:57:17.81#ibcon#enter sib2, iclass 27, count 0 2006.201.04:57:17.81#ibcon#flushed, iclass 27, count 0 2006.201.04:57:17.81#ibcon#about to write, iclass 27, count 0 2006.201.04:57:17.81#ibcon#wrote, iclass 27, count 0 2006.201.04:57:17.81#ibcon#about to read 3, iclass 27, count 0 2006.201.04:57:17.83#ibcon#read 3, iclass 27, count 0 2006.201.04:57:17.83#ibcon#about to read 4, iclass 27, count 0 2006.201.04:57:17.83#ibcon#read 4, iclass 27, count 0 2006.201.04:57:17.83#ibcon#about to read 5, iclass 27, count 0 2006.201.04:57:17.83#ibcon#read 5, iclass 27, count 0 2006.201.04:57:17.83#ibcon#about to read 6, iclass 27, count 0 2006.201.04:57:17.83#ibcon#read 6, iclass 27, count 0 2006.201.04:57:17.83#ibcon#end of sib2, iclass 27, count 0 2006.201.04:57:17.83#ibcon#*mode == 0, iclass 27, count 0 2006.201.04:57:17.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.04:57:17.83#ibcon#[27=USB\r\n] 2006.201.04:57:17.83#ibcon#*before write, iclass 27, count 0 2006.201.04:57:17.83#ibcon#enter sib2, iclass 27, count 0 2006.201.04:57:17.83#ibcon#flushed, iclass 27, count 0 2006.201.04:57:17.83#ibcon#about to write, iclass 27, count 0 2006.201.04:57:17.83#ibcon#wrote, iclass 27, count 0 2006.201.04:57:17.83#ibcon#about to read 3, iclass 27, count 0 2006.201.04:57:17.86#ibcon#read 3, iclass 27, count 0 2006.201.04:57:17.86#ibcon#about to read 4, iclass 27, count 0 2006.201.04:57:17.86#ibcon#read 4, iclass 27, count 0 2006.201.04:57:17.86#ibcon#about to read 5, iclass 27, count 0 2006.201.04:57:17.86#ibcon#read 5, iclass 27, count 0 2006.201.04:57:17.86#ibcon#about to read 6, iclass 27, count 0 2006.201.04:57:17.86#ibcon#read 6, iclass 27, count 0 2006.201.04:57:17.86#ibcon#end of sib2, iclass 27, count 0 2006.201.04:57:17.86#ibcon#*after write, iclass 27, count 0 2006.201.04:57:17.86#ibcon#*before return 0, iclass 27, count 0 2006.201.04:57:17.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:17.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.04:57:17.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.04:57:17.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.04:57:17.86$vck44/vabw=wide 2006.201.04:57:17.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.04:57:17.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.04:57:17.86#ibcon#ireg 8 cls_cnt 0 2006.201.04:57:17.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:17.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:17.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:17.86#ibcon#enter wrdev, iclass 29, count 0 2006.201.04:57:17.86#ibcon#first serial, iclass 29, count 0 2006.201.04:57:17.86#ibcon#enter sib2, iclass 29, count 0 2006.201.04:57:17.86#ibcon#flushed, iclass 29, count 0 2006.201.04:57:17.86#ibcon#about to write, iclass 29, count 0 2006.201.04:57:17.86#ibcon#wrote, iclass 29, count 0 2006.201.04:57:17.86#ibcon#about to read 3, iclass 29, count 0 2006.201.04:57:17.88#ibcon#read 3, iclass 29, count 0 2006.201.04:57:17.88#ibcon#about to read 4, iclass 29, count 0 2006.201.04:57:17.88#ibcon#read 4, iclass 29, count 0 2006.201.04:57:17.88#ibcon#about to read 5, iclass 29, count 0 2006.201.04:57:17.88#ibcon#read 5, iclass 29, count 0 2006.201.04:57:17.88#ibcon#about to read 6, iclass 29, count 0 2006.201.04:57:17.88#ibcon#read 6, iclass 29, count 0 2006.201.04:57:17.88#ibcon#end of sib2, iclass 29, count 0 2006.201.04:57:17.88#ibcon#*mode == 0, iclass 29, count 0 2006.201.04:57:17.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.04:57:17.88#ibcon#[25=BW32\r\n] 2006.201.04:57:17.88#ibcon#*before write, iclass 29, count 0 2006.201.04:57:17.88#ibcon#enter sib2, iclass 29, count 0 2006.201.04:57:17.88#ibcon#flushed, iclass 29, count 0 2006.201.04:57:17.88#ibcon#about to write, iclass 29, count 0 2006.201.04:57:17.88#ibcon#wrote, iclass 29, count 0 2006.201.04:57:17.88#ibcon#about to read 3, iclass 29, count 0 2006.201.04:57:17.91#ibcon#read 3, iclass 29, count 0 2006.201.04:57:17.91#ibcon#about to read 4, iclass 29, count 0 2006.201.04:57:17.91#ibcon#read 4, iclass 29, count 0 2006.201.04:57:17.91#ibcon#about to read 5, iclass 29, count 0 2006.201.04:57:17.91#ibcon#read 5, iclass 29, count 0 2006.201.04:57:17.91#ibcon#about to read 6, iclass 29, count 0 2006.201.04:57:17.91#ibcon#read 6, iclass 29, count 0 2006.201.04:57:17.91#ibcon#end of sib2, iclass 29, count 0 2006.201.04:57:17.91#ibcon#*after write, iclass 29, count 0 2006.201.04:57:17.91#ibcon#*before return 0, iclass 29, count 0 2006.201.04:57:17.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:17.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.04:57:17.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.04:57:17.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.04:57:17.91$vck44/vbbw=wide 2006.201.04:57:17.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.04:57:17.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.04:57:17.91#ibcon#ireg 8 cls_cnt 0 2006.201.04:57:17.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:57:17.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:57:17.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:57:17.98#ibcon#enter wrdev, iclass 31, count 0 2006.201.04:57:17.98#ibcon#first serial, iclass 31, count 0 2006.201.04:57:17.98#ibcon#enter sib2, iclass 31, count 0 2006.201.04:57:17.98#ibcon#flushed, iclass 31, count 0 2006.201.04:57:17.98#ibcon#about to write, iclass 31, count 0 2006.201.04:57:17.98#ibcon#wrote, iclass 31, count 0 2006.201.04:57:17.98#ibcon#about to read 3, iclass 31, count 0 2006.201.04:57:18.00#ibcon#read 3, iclass 31, count 0 2006.201.04:57:18.00#ibcon#about to read 4, iclass 31, count 0 2006.201.04:57:18.00#ibcon#read 4, iclass 31, count 0 2006.201.04:57:18.00#ibcon#about to read 5, iclass 31, count 0 2006.201.04:57:18.00#ibcon#read 5, iclass 31, count 0 2006.201.04:57:18.00#ibcon#about to read 6, iclass 31, count 0 2006.201.04:57:18.00#ibcon#read 6, iclass 31, count 0 2006.201.04:57:18.00#ibcon#end of sib2, iclass 31, count 0 2006.201.04:57:18.00#ibcon#*mode == 0, iclass 31, count 0 2006.201.04:57:18.00#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.04:57:18.00#ibcon#[27=BW32\r\n] 2006.201.04:57:18.00#ibcon#*before write, iclass 31, count 0 2006.201.04:57:18.00#ibcon#enter sib2, iclass 31, count 0 2006.201.04:57:18.00#ibcon#flushed, iclass 31, count 0 2006.201.04:57:18.00#ibcon#about to write, iclass 31, count 0 2006.201.04:57:18.00#ibcon#wrote, iclass 31, count 0 2006.201.04:57:18.00#ibcon#about to read 3, iclass 31, count 0 2006.201.04:57:18.03#ibcon#read 3, iclass 31, count 0 2006.201.04:57:18.03#ibcon#about to read 4, iclass 31, count 0 2006.201.04:57:18.03#ibcon#read 4, iclass 31, count 0 2006.201.04:57:18.03#ibcon#about to read 5, iclass 31, count 0 2006.201.04:57:18.03#ibcon#read 5, iclass 31, count 0 2006.201.04:57:18.03#ibcon#about to read 6, iclass 31, count 0 2006.201.04:57:18.03#ibcon#read 6, iclass 31, count 0 2006.201.04:57:18.03#ibcon#end of sib2, iclass 31, count 0 2006.201.04:57:18.03#ibcon#*after write, iclass 31, count 0 2006.201.04:57:18.03#ibcon#*before return 0, iclass 31, count 0 2006.201.04:57:18.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:57:18.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.04:57:18.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.04:57:18.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.04:57:18.03$setupk4/ifdk4 2006.201.04:57:18.03$ifdk4/lo= 2006.201.04:57:18.03$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.04:57:18.03$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.04:57:18.03$ifdk4/patch= 2006.201.04:57:18.03$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.04:57:18.03$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.04:57:18.03$setupk4/!*+20s 2006.201.04:57:24.23#abcon#<5=/04 2.6 5.6 23.09 891003.8\r\n> 2006.201.04:57:24.25#abcon#{5=INTERFACE CLEAR} 2006.201.04:57:24.31#abcon#[5=S1D000X0/0*\r\n] 2006.201.04:57:32.24$setupk4/"tpicd 2006.201.04:57:32.24$setupk4/echo=off 2006.201.04:57:32.24$setupk4/xlog=off 2006.201.04:57:32.24:!2006.201.05:00:38 2006.201.04:58:02.14#trakl#Source acquired 2006.201.04:58:04.14#flagr#flagr/antenna,acquired 2006.201.05:00:38.00:preob 2006.201.05:00:38.14/onsource/TRACKING 2006.201.05:00:38.14:!2006.201.05:00:48 2006.201.05:00:48.00:"tape 2006.201.05:00:48.00:"st=record 2006.201.05:00:48.00:data_valid=on 2006.201.05:00:48.00:midob 2006.201.05:00:49.14/onsource/TRACKING 2006.201.05:00:49.14/wx/23.21,1003.8,88 2006.201.05:00:49.36/cable/+6.4663E-03 2006.201.05:00:50.45/va/01,08,usb,yes,30,32 2006.201.05:00:50.45/va/02,07,usb,yes,32,33 2006.201.05:00:50.45/va/03,08,usb,yes,29,30 2006.201.05:00:50.45/va/04,07,usb,yes,33,35 2006.201.05:00:50.45/va/05,04,usb,yes,29,30 2006.201.05:00:50.45/va/06,05,usb,yes,29,29 2006.201.05:00:50.45/va/07,05,usb,yes,28,30 2006.201.05:00:50.45/va/08,04,usb,yes,28,34 2006.201.05:00:50.68/valo/01,524.99,yes,locked 2006.201.05:00:50.68/valo/02,534.99,yes,locked 2006.201.05:00:50.68/valo/03,564.99,yes,locked 2006.201.05:00:50.68/valo/04,624.99,yes,locked 2006.201.05:00:50.68/valo/05,734.99,yes,locked 2006.201.05:00:50.68/valo/06,814.99,yes,locked 2006.201.05:00:50.68/valo/07,864.99,yes,locked 2006.201.05:00:50.68/valo/08,884.99,yes,locked 2006.201.05:00:51.77/vb/01,04,usb,yes,29,27 2006.201.05:00:51.77/vb/02,05,usb,yes,28,27 2006.201.05:00:51.77/vb/03,04,usb,yes,29,32 2006.201.05:00:51.77/vb/04,05,usb,yes,29,28 2006.201.05:00:51.77/vb/05,04,usb,yes,25,28 2006.201.05:00:51.77/vb/06,04,usb,yes,30,26 2006.201.05:00:51.77/vb/07,04,usb,yes,30,29 2006.201.05:00:51.77/vb/08,04,usb,yes,27,31 2006.201.05:00:52.00/vblo/01,629.99,yes,locked 2006.201.05:00:52.00/vblo/02,634.99,yes,locked 2006.201.05:00:52.00/vblo/03,649.99,yes,locked 2006.201.05:00:52.00/vblo/04,679.99,yes,locked 2006.201.05:00:52.00/vblo/05,709.99,yes,locked 2006.201.05:00:52.00/vblo/06,719.99,yes,locked 2006.201.05:00:52.00/vblo/07,734.99,yes,locked 2006.201.05:00:52.00/vblo/08,744.99,yes,locked 2006.201.05:00:52.15/vabw/8 2006.201.05:00:52.30/vbbw/8 2006.201.05:00:52.39/xfe/off,on,15.2 2006.201.05:00:52.78/ifatt/23,28,28,28 2006.201.05:00:53.05/fmout-gps/S +4.49E-07 2006.201.05:00:53.09:!2006.201.05:02:48 2006.201.05:02:48.00:data_valid=off 2006.201.05:02:48.00:"et 2006.201.05:02:48.00:!+3s 2006.201.05:02:51.02:"tape 2006.201.05:02:51.02:postob 2006.201.05:02:51.15/cable/+6.4663E-03 2006.201.05:02:51.15/wx/23.27,1003.9,88 2006.201.05:02:51.21/fmout-gps/S +4.48E-07 2006.201.05:02:51.21:scan_name=201-0504,jd0607,90 2006.201.05:02:51.21:source=3c274,123049.42,122328.0,2000.0,cw 2006.201.05:02:52.14#flagr#flagr/antenna,new-source 2006.201.05:02:52.14:checkk5 2006.201.05:02:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:02:52.93/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:02:53.33/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:02:53.72/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:02:54.12/chk_obsdata//k5ts1/T2010500??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.201.05:02:54.52/chk_obsdata//k5ts2/T2010500??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.201.05:02:54.93/chk_obsdata//k5ts3/T2010500??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.201.05:02:55.34/chk_obsdata//k5ts4/T2010500??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.201.05:02:56.07/k5log//k5ts1_log_newline 2006.201.05:02:56.79/k5log//k5ts2_log_newline 2006.201.05:02:57.51/k5log//k5ts3_log_newline 2006.201.05:02:58.22/k5log//k5ts4_log_newline 2006.201.05:02:58.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:02:58.24:setupk4=1 2006.201.05:02:58.24$setupk4/echo=on 2006.201.05:02:58.24$setupk4/pcalon 2006.201.05:02:58.24$pcalon/"no phase cal control is implemented here 2006.201.05:02:58.24$setupk4/"tpicd=stop 2006.201.05:02:58.24$setupk4/"rec=synch_on 2006.201.05:02:58.24$setupk4/"rec_mode=128 2006.201.05:02:58.24$setupk4/!* 2006.201.05:02:58.24$setupk4/recpk4 2006.201.05:02:58.24$recpk4/recpatch= 2006.201.05:02:58.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:02:58.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:02:58.25$setupk4/vck44 2006.201.05:02:58.25$vck44/valo=1,524.99 2006.201.05:02:58.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.05:02:58.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.05:02:58.25#ibcon#ireg 17 cls_cnt 0 2006.201.05:02:58.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:02:58.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:02:58.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:02:58.25#ibcon#enter wrdev, iclass 24, count 0 2006.201.05:02:58.25#ibcon#first serial, iclass 24, count 0 2006.201.05:02:58.25#ibcon#enter sib2, iclass 24, count 0 2006.201.05:02:58.25#ibcon#flushed, iclass 24, count 0 2006.201.05:02:58.25#ibcon#about to write, iclass 24, count 0 2006.201.05:02:58.25#ibcon#wrote, iclass 24, count 0 2006.201.05:02:58.25#ibcon#about to read 3, iclass 24, count 0 2006.201.05:02:58.27#ibcon#read 3, iclass 24, count 0 2006.201.05:02:58.27#ibcon#about to read 4, iclass 24, count 0 2006.201.05:02:58.27#ibcon#read 4, iclass 24, count 0 2006.201.05:02:58.27#ibcon#about to read 5, iclass 24, count 0 2006.201.05:02:58.27#ibcon#read 5, iclass 24, count 0 2006.201.05:02:58.27#ibcon#about to read 6, iclass 24, count 0 2006.201.05:02:58.27#ibcon#read 6, iclass 24, count 0 2006.201.05:02:58.27#ibcon#end of sib2, iclass 24, count 0 2006.201.05:02:58.27#ibcon#*mode == 0, iclass 24, count 0 2006.201.05:02:58.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.05:02:58.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:02:58.27#ibcon#*before write, iclass 24, count 0 2006.201.05:02:58.27#ibcon#enter sib2, iclass 24, count 0 2006.201.05:02:58.27#ibcon#flushed, iclass 24, count 0 2006.201.05:02:58.27#ibcon#about to write, iclass 24, count 0 2006.201.05:02:58.27#ibcon#wrote, iclass 24, count 0 2006.201.05:02:58.27#ibcon#about to read 3, iclass 24, count 0 2006.201.05:02:58.32#ibcon#read 3, iclass 24, count 0 2006.201.05:02:58.32#ibcon#about to read 4, iclass 24, count 0 2006.201.05:02:58.32#ibcon#read 4, iclass 24, count 0 2006.201.05:02:58.32#ibcon#about to read 5, iclass 24, count 0 2006.201.05:02:58.32#ibcon#read 5, iclass 24, count 0 2006.201.05:02:58.32#ibcon#about to read 6, iclass 24, count 0 2006.201.05:02:58.32#ibcon#read 6, iclass 24, count 0 2006.201.05:02:58.32#ibcon#end of sib2, iclass 24, count 0 2006.201.05:02:58.32#ibcon#*after write, iclass 24, count 0 2006.201.05:02:58.32#ibcon#*before return 0, iclass 24, count 0 2006.201.05:02:58.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:02:58.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:02:58.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.05:02:58.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.05:02:58.32$vck44/va=1,8 2006.201.05:02:58.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.05:02:58.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.05:02:58.32#ibcon#ireg 11 cls_cnt 2 2006.201.05:02:58.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:02:58.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:02:58.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:02:58.32#ibcon#enter wrdev, iclass 26, count 2 2006.201.05:02:58.32#ibcon#first serial, iclass 26, count 2 2006.201.05:02:58.32#ibcon#enter sib2, iclass 26, count 2 2006.201.05:02:58.32#ibcon#flushed, iclass 26, count 2 2006.201.05:02:58.32#ibcon#about to write, iclass 26, count 2 2006.201.05:02:58.32#ibcon#wrote, iclass 26, count 2 2006.201.05:02:58.32#ibcon#about to read 3, iclass 26, count 2 2006.201.05:02:58.34#ibcon#read 3, iclass 26, count 2 2006.201.05:02:58.34#ibcon#about to read 4, iclass 26, count 2 2006.201.05:02:58.34#ibcon#read 4, iclass 26, count 2 2006.201.05:02:58.34#ibcon#about to read 5, iclass 26, count 2 2006.201.05:02:58.34#ibcon#read 5, iclass 26, count 2 2006.201.05:02:58.34#ibcon#about to read 6, iclass 26, count 2 2006.201.05:02:58.34#ibcon#read 6, iclass 26, count 2 2006.201.05:02:58.34#ibcon#end of sib2, iclass 26, count 2 2006.201.05:02:58.34#ibcon#*mode == 0, iclass 26, count 2 2006.201.05:02:58.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.05:02:58.34#ibcon#[25=AT01-08\r\n] 2006.201.05:02:58.34#ibcon#*before write, iclass 26, count 2 2006.201.05:02:58.34#ibcon#enter sib2, iclass 26, count 2 2006.201.05:02:58.34#ibcon#flushed, iclass 26, count 2 2006.201.05:02:58.34#ibcon#about to write, iclass 26, count 2 2006.201.05:02:58.34#ibcon#wrote, iclass 26, count 2 2006.201.05:02:58.34#ibcon#about to read 3, iclass 26, count 2 2006.201.05:02:58.37#ibcon#read 3, iclass 26, count 2 2006.201.05:02:58.37#ibcon#about to read 4, iclass 26, count 2 2006.201.05:02:58.37#ibcon#read 4, iclass 26, count 2 2006.201.05:02:58.37#ibcon#about to read 5, iclass 26, count 2 2006.201.05:02:58.37#ibcon#read 5, iclass 26, count 2 2006.201.05:02:58.37#ibcon#about to read 6, iclass 26, count 2 2006.201.05:02:58.37#ibcon#read 6, iclass 26, count 2 2006.201.05:02:58.37#ibcon#end of sib2, iclass 26, count 2 2006.201.05:02:58.37#ibcon#*after write, iclass 26, count 2 2006.201.05:02:58.37#ibcon#*before return 0, iclass 26, count 2 2006.201.05:02:58.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:02:58.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:02:58.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.05:02:58.37#ibcon#ireg 7 cls_cnt 0 2006.201.05:02:58.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:02:58.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:02:58.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:02:58.49#ibcon#enter wrdev, iclass 26, count 0 2006.201.05:02:58.49#ibcon#first serial, iclass 26, count 0 2006.201.05:02:58.49#ibcon#enter sib2, iclass 26, count 0 2006.201.05:02:58.49#ibcon#flushed, iclass 26, count 0 2006.201.05:02:58.49#ibcon#about to write, iclass 26, count 0 2006.201.05:02:58.49#ibcon#wrote, iclass 26, count 0 2006.201.05:02:58.49#ibcon#about to read 3, iclass 26, count 0 2006.201.05:02:58.51#ibcon#read 3, iclass 26, count 0 2006.201.05:02:58.51#ibcon#about to read 4, iclass 26, count 0 2006.201.05:02:58.51#ibcon#read 4, iclass 26, count 0 2006.201.05:02:58.51#ibcon#about to read 5, iclass 26, count 0 2006.201.05:02:58.51#ibcon#read 5, iclass 26, count 0 2006.201.05:02:58.51#ibcon#about to read 6, iclass 26, count 0 2006.201.05:02:58.51#ibcon#read 6, iclass 26, count 0 2006.201.05:02:58.51#ibcon#end of sib2, iclass 26, count 0 2006.201.05:02:58.51#ibcon#*mode == 0, iclass 26, count 0 2006.201.05:02:58.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.05:02:58.51#ibcon#[25=USB\r\n] 2006.201.05:02:58.51#ibcon#*before write, iclass 26, count 0 2006.201.05:02:58.51#ibcon#enter sib2, iclass 26, count 0 2006.201.05:02:58.51#ibcon#flushed, iclass 26, count 0 2006.201.05:02:58.51#ibcon#about to write, iclass 26, count 0 2006.201.05:02:58.51#ibcon#wrote, iclass 26, count 0 2006.201.05:02:58.51#ibcon#about to read 3, iclass 26, count 0 2006.201.05:02:58.54#ibcon#read 3, iclass 26, count 0 2006.201.05:02:58.54#ibcon#about to read 4, iclass 26, count 0 2006.201.05:02:58.54#ibcon#read 4, iclass 26, count 0 2006.201.05:02:58.54#ibcon#about to read 5, iclass 26, count 0 2006.201.05:02:58.54#ibcon#read 5, iclass 26, count 0 2006.201.05:02:58.54#ibcon#about to read 6, iclass 26, count 0 2006.201.05:02:58.54#ibcon#read 6, iclass 26, count 0 2006.201.05:02:58.54#ibcon#end of sib2, iclass 26, count 0 2006.201.05:02:58.54#ibcon#*after write, iclass 26, count 0 2006.201.05:02:58.54#ibcon#*before return 0, iclass 26, count 0 2006.201.05:02:58.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:02:58.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:02:58.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.05:02:58.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.05:02:58.54$vck44/valo=2,534.99 2006.201.05:02:58.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.05:02:58.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.05:02:58.54#ibcon#ireg 17 cls_cnt 0 2006.201.05:02:58.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:02:58.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:02:58.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:02:58.54#ibcon#enter wrdev, iclass 28, count 0 2006.201.05:02:58.54#ibcon#first serial, iclass 28, count 0 2006.201.05:02:58.54#ibcon#enter sib2, iclass 28, count 0 2006.201.05:02:58.54#ibcon#flushed, iclass 28, count 0 2006.201.05:02:58.54#ibcon#about to write, iclass 28, count 0 2006.201.05:02:58.54#ibcon#wrote, iclass 28, count 0 2006.201.05:02:58.54#ibcon#about to read 3, iclass 28, count 0 2006.201.05:02:58.56#ibcon#read 3, iclass 28, count 0 2006.201.05:02:58.56#ibcon#about to read 4, iclass 28, count 0 2006.201.05:02:58.56#ibcon#read 4, iclass 28, count 0 2006.201.05:02:58.56#ibcon#about to read 5, iclass 28, count 0 2006.201.05:02:58.56#ibcon#read 5, iclass 28, count 0 2006.201.05:02:58.56#ibcon#about to read 6, iclass 28, count 0 2006.201.05:02:58.56#ibcon#read 6, iclass 28, count 0 2006.201.05:02:58.56#ibcon#end of sib2, iclass 28, count 0 2006.201.05:02:58.56#ibcon#*mode == 0, iclass 28, count 0 2006.201.05:02:58.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.05:02:58.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:02:58.56#ibcon#*before write, iclass 28, count 0 2006.201.05:02:58.56#ibcon#enter sib2, iclass 28, count 0 2006.201.05:02:58.56#ibcon#flushed, iclass 28, count 0 2006.201.05:02:58.56#ibcon#about to write, iclass 28, count 0 2006.201.05:02:58.56#ibcon#wrote, iclass 28, count 0 2006.201.05:02:58.56#ibcon#about to read 3, iclass 28, count 0 2006.201.05:02:58.60#ibcon#read 3, iclass 28, count 0 2006.201.05:02:58.60#ibcon#about to read 4, iclass 28, count 0 2006.201.05:02:58.60#ibcon#read 4, iclass 28, count 0 2006.201.05:02:58.60#ibcon#about to read 5, iclass 28, count 0 2006.201.05:02:58.60#ibcon#read 5, iclass 28, count 0 2006.201.05:02:58.60#ibcon#about to read 6, iclass 28, count 0 2006.201.05:02:58.60#ibcon#read 6, iclass 28, count 0 2006.201.05:02:58.60#ibcon#end of sib2, iclass 28, count 0 2006.201.05:02:58.60#ibcon#*after write, iclass 28, count 0 2006.201.05:02:58.60#ibcon#*before return 0, iclass 28, count 0 2006.201.05:02:58.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:02:58.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:02:58.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.05:02:58.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.05:02:58.60$vck44/va=2,7 2006.201.05:02:58.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.05:02:58.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.05:02:58.60#ibcon#ireg 11 cls_cnt 2 2006.201.05:02:58.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:02:58.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:02:58.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:02:58.66#ibcon#enter wrdev, iclass 30, count 2 2006.201.05:02:58.66#ibcon#first serial, iclass 30, count 2 2006.201.05:02:58.66#ibcon#enter sib2, iclass 30, count 2 2006.201.05:02:58.66#ibcon#flushed, iclass 30, count 2 2006.201.05:02:58.66#ibcon#about to write, iclass 30, count 2 2006.201.05:02:58.66#ibcon#wrote, iclass 30, count 2 2006.201.05:02:58.66#ibcon#about to read 3, iclass 30, count 2 2006.201.05:02:58.68#ibcon#read 3, iclass 30, count 2 2006.201.05:02:58.68#ibcon#about to read 4, iclass 30, count 2 2006.201.05:02:58.68#ibcon#read 4, iclass 30, count 2 2006.201.05:02:58.68#ibcon#about to read 5, iclass 30, count 2 2006.201.05:02:58.68#ibcon#read 5, iclass 30, count 2 2006.201.05:02:58.68#ibcon#about to read 6, iclass 30, count 2 2006.201.05:02:58.68#ibcon#read 6, iclass 30, count 2 2006.201.05:02:58.68#ibcon#end of sib2, iclass 30, count 2 2006.201.05:02:58.68#ibcon#*mode == 0, iclass 30, count 2 2006.201.05:02:58.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.05:02:58.68#ibcon#[25=AT02-07\r\n] 2006.201.05:02:58.68#ibcon#*before write, iclass 30, count 2 2006.201.05:02:58.68#ibcon#enter sib2, iclass 30, count 2 2006.201.05:02:58.68#ibcon#flushed, iclass 30, count 2 2006.201.05:02:58.68#ibcon#about to write, iclass 30, count 2 2006.201.05:02:58.68#ibcon#wrote, iclass 30, count 2 2006.201.05:02:58.68#ibcon#about to read 3, iclass 30, count 2 2006.201.05:02:58.71#ibcon#read 3, iclass 30, count 2 2006.201.05:02:58.71#ibcon#about to read 4, iclass 30, count 2 2006.201.05:02:58.71#ibcon#read 4, iclass 30, count 2 2006.201.05:02:58.71#ibcon#about to read 5, iclass 30, count 2 2006.201.05:02:58.71#ibcon#read 5, iclass 30, count 2 2006.201.05:02:58.71#ibcon#about to read 6, iclass 30, count 2 2006.201.05:02:58.71#ibcon#read 6, iclass 30, count 2 2006.201.05:02:58.71#ibcon#end of sib2, iclass 30, count 2 2006.201.05:02:58.71#ibcon#*after write, iclass 30, count 2 2006.201.05:02:58.71#ibcon#*before return 0, iclass 30, count 2 2006.201.05:02:58.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:02:58.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:02:58.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.05:02:58.71#ibcon#ireg 7 cls_cnt 0 2006.201.05:02:58.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:02:58.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:02:58.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:02:58.83#ibcon#enter wrdev, iclass 30, count 0 2006.201.05:02:58.83#ibcon#first serial, iclass 30, count 0 2006.201.05:02:58.83#ibcon#enter sib2, iclass 30, count 0 2006.201.05:02:58.83#ibcon#flushed, iclass 30, count 0 2006.201.05:02:58.83#ibcon#about to write, iclass 30, count 0 2006.201.05:02:58.83#ibcon#wrote, iclass 30, count 0 2006.201.05:02:58.83#ibcon#about to read 3, iclass 30, count 0 2006.201.05:02:58.85#ibcon#read 3, iclass 30, count 0 2006.201.05:02:58.85#ibcon#about to read 4, iclass 30, count 0 2006.201.05:02:58.85#ibcon#read 4, iclass 30, count 0 2006.201.05:02:58.85#ibcon#about to read 5, iclass 30, count 0 2006.201.05:02:58.85#ibcon#read 5, iclass 30, count 0 2006.201.05:02:58.85#ibcon#about to read 6, iclass 30, count 0 2006.201.05:02:58.85#ibcon#read 6, iclass 30, count 0 2006.201.05:02:58.85#ibcon#end of sib2, iclass 30, count 0 2006.201.05:02:58.85#ibcon#*mode == 0, iclass 30, count 0 2006.201.05:02:58.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.05:02:58.85#ibcon#[25=USB\r\n] 2006.201.05:02:58.85#ibcon#*before write, iclass 30, count 0 2006.201.05:02:58.85#ibcon#enter sib2, iclass 30, count 0 2006.201.05:02:58.85#ibcon#flushed, iclass 30, count 0 2006.201.05:02:58.85#ibcon#about to write, iclass 30, count 0 2006.201.05:02:58.85#ibcon#wrote, iclass 30, count 0 2006.201.05:02:58.85#ibcon#about to read 3, iclass 30, count 0 2006.201.05:02:58.88#ibcon#read 3, iclass 30, count 0 2006.201.05:02:58.88#ibcon#about to read 4, iclass 30, count 0 2006.201.05:02:58.88#ibcon#read 4, iclass 30, count 0 2006.201.05:02:58.88#ibcon#about to read 5, iclass 30, count 0 2006.201.05:02:58.88#ibcon#read 5, iclass 30, count 0 2006.201.05:02:58.88#ibcon#about to read 6, iclass 30, count 0 2006.201.05:02:58.88#ibcon#read 6, iclass 30, count 0 2006.201.05:02:58.88#ibcon#end of sib2, iclass 30, count 0 2006.201.05:02:58.88#ibcon#*after write, iclass 30, count 0 2006.201.05:02:58.88#ibcon#*before return 0, iclass 30, count 0 2006.201.05:02:58.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:02:58.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:02:58.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.05:02:58.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.05:02:58.88$vck44/valo=3,564.99 2006.201.05:02:58.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.05:02:58.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.05:02:58.88#ibcon#ireg 17 cls_cnt 0 2006.201.05:02:58.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:02:58.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:02:58.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:02:58.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.05:02:58.88#ibcon#first serial, iclass 32, count 0 2006.201.05:02:58.88#ibcon#enter sib2, iclass 32, count 0 2006.201.05:02:58.88#ibcon#flushed, iclass 32, count 0 2006.201.05:02:58.88#ibcon#about to write, iclass 32, count 0 2006.201.05:02:58.88#ibcon#wrote, iclass 32, count 0 2006.201.05:02:58.88#ibcon#about to read 3, iclass 32, count 0 2006.201.05:02:58.90#ibcon#read 3, iclass 32, count 0 2006.201.05:02:58.90#ibcon#about to read 4, iclass 32, count 0 2006.201.05:02:58.90#ibcon#read 4, iclass 32, count 0 2006.201.05:02:58.90#ibcon#about to read 5, iclass 32, count 0 2006.201.05:02:58.90#ibcon#read 5, iclass 32, count 0 2006.201.05:02:58.90#ibcon#about to read 6, iclass 32, count 0 2006.201.05:02:58.90#ibcon#read 6, iclass 32, count 0 2006.201.05:02:58.90#ibcon#end of sib2, iclass 32, count 0 2006.201.05:02:58.90#ibcon#*mode == 0, iclass 32, count 0 2006.201.05:02:58.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.05:02:58.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:02:58.90#ibcon#*before write, iclass 32, count 0 2006.201.05:02:58.90#ibcon#enter sib2, iclass 32, count 0 2006.201.05:02:58.90#ibcon#flushed, iclass 32, count 0 2006.201.05:02:58.90#ibcon#about to write, iclass 32, count 0 2006.201.05:02:58.90#ibcon#wrote, iclass 32, count 0 2006.201.05:02:58.90#ibcon#about to read 3, iclass 32, count 0 2006.201.05:02:58.94#ibcon#read 3, iclass 32, count 0 2006.201.05:02:58.94#ibcon#about to read 4, iclass 32, count 0 2006.201.05:02:58.94#ibcon#read 4, iclass 32, count 0 2006.201.05:02:58.94#ibcon#about to read 5, iclass 32, count 0 2006.201.05:02:58.94#ibcon#read 5, iclass 32, count 0 2006.201.05:02:58.94#ibcon#about to read 6, iclass 32, count 0 2006.201.05:02:58.94#ibcon#read 6, iclass 32, count 0 2006.201.05:02:58.94#ibcon#end of sib2, iclass 32, count 0 2006.201.05:02:58.94#ibcon#*after write, iclass 32, count 0 2006.201.05:02:58.94#ibcon#*before return 0, iclass 32, count 0 2006.201.05:02:58.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:02:58.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:02:58.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.05:02:58.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.05:02:58.94$vck44/va=3,8 2006.201.05:02:58.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.05:02:58.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.05:02:58.94#ibcon#ireg 11 cls_cnt 2 2006.201.05:02:58.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:02:59.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:02:59.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:02:59.00#ibcon#enter wrdev, iclass 34, count 2 2006.201.05:02:59.00#ibcon#first serial, iclass 34, count 2 2006.201.05:02:59.00#ibcon#enter sib2, iclass 34, count 2 2006.201.05:02:59.00#ibcon#flushed, iclass 34, count 2 2006.201.05:02:59.00#ibcon#about to write, iclass 34, count 2 2006.201.05:02:59.00#ibcon#wrote, iclass 34, count 2 2006.201.05:02:59.00#ibcon#about to read 3, iclass 34, count 2 2006.201.05:02:59.02#ibcon#read 3, iclass 34, count 2 2006.201.05:02:59.02#ibcon#about to read 4, iclass 34, count 2 2006.201.05:02:59.02#ibcon#read 4, iclass 34, count 2 2006.201.05:02:59.02#ibcon#about to read 5, iclass 34, count 2 2006.201.05:02:59.02#ibcon#read 5, iclass 34, count 2 2006.201.05:02:59.02#ibcon#about to read 6, iclass 34, count 2 2006.201.05:02:59.02#ibcon#read 6, iclass 34, count 2 2006.201.05:02:59.02#ibcon#end of sib2, iclass 34, count 2 2006.201.05:02:59.02#ibcon#*mode == 0, iclass 34, count 2 2006.201.05:02:59.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.05:02:59.02#ibcon#[25=AT03-08\r\n] 2006.201.05:02:59.02#ibcon#*before write, iclass 34, count 2 2006.201.05:02:59.02#ibcon#enter sib2, iclass 34, count 2 2006.201.05:02:59.02#ibcon#flushed, iclass 34, count 2 2006.201.05:02:59.02#ibcon#about to write, iclass 34, count 2 2006.201.05:02:59.02#ibcon#wrote, iclass 34, count 2 2006.201.05:02:59.02#ibcon#about to read 3, iclass 34, count 2 2006.201.05:02:59.05#ibcon#read 3, iclass 34, count 2 2006.201.05:02:59.05#ibcon#about to read 4, iclass 34, count 2 2006.201.05:02:59.05#ibcon#read 4, iclass 34, count 2 2006.201.05:02:59.05#ibcon#about to read 5, iclass 34, count 2 2006.201.05:02:59.05#ibcon#read 5, iclass 34, count 2 2006.201.05:02:59.05#ibcon#about to read 6, iclass 34, count 2 2006.201.05:02:59.05#ibcon#read 6, iclass 34, count 2 2006.201.05:02:59.05#ibcon#end of sib2, iclass 34, count 2 2006.201.05:02:59.05#ibcon#*after write, iclass 34, count 2 2006.201.05:02:59.05#ibcon#*before return 0, iclass 34, count 2 2006.201.05:02:59.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:02:59.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:02:59.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.05:02:59.05#ibcon#ireg 7 cls_cnt 0 2006.201.05:02:59.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:02:59.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:02:59.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:02:59.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.05:02:59.17#ibcon#first serial, iclass 34, count 0 2006.201.05:02:59.17#ibcon#enter sib2, iclass 34, count 0 2006.201.05:02:59.17#ibcon#flushed, iclass 34, count 0 2006.201.05:02:59.17#ibcon#about to write, iclass 34, count 0 2006.201.05:02:59.17#ibcon#wrote, iclass 34, count 0 2006.201.05:02:59.17#ibcon#about to read 3, iclass 34, count 0 2006.201.05:02:59.19#ibcon#read 3, iclass 34, count 0 2006.201.05:02:59.19#ibcon#about to read 4, iclass 34, count 0 2006.201.05:02:59.19#ibcon#read 4, iclass 34, count 0 2006.201.05:02:59.19#ibcon#about to read 5, iclass 34, count 0 2006.201.05:02:59.19#ibcon#read 5, iclass 34, count 0 2006.201.05:02:59.19#ibcon#about to read 6, iclass 34, count 0 2006.201.05:02:59.19#ibcon#read 6, iclass 34, count 0 2006.201.05:02:59.19#ibcon#end of sib2, iclass 34, count 0 2006.201.05:02:59.19#ibcon#*mode == 0, iclass 34, count 0 2006.201.05:02:59.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.05:02:59.19#ibcon#[25=USB\r\n] 2006.201.05:02:59.19#ibcon#*before write, iclass 34, count 0 2006.201.05:02:59.19#ibcon#enter sib2, iclass 34, count 0 2006.201.05:02:59.19#ibcon#flushed, iclass 34, count 0 2006.201.05:02:59.19#ibcon#about to write, iclass 34, count 0 2006.201.05:02:59.19#ibcon#wrote, iclass 34, count 0 2006.201.05:02:59.19#ibcon#about to read 3, iclass 34, count 0 2006.201.05:02:59.22#ibcon#read 3, iclass 34, count 0 2006.201.05:02:59.22#ibcon#about to read 4, iclass 34, count 0 2006.201.05:02:59.22#ibcon#read 4, iclass 34, count 0 2006.201.05:02:59.22#ibcon#about to read 5, iclass 34, count 0 2006.201.05:02:59.22#ibcon#read 5, iclass 34, count 0 2006.201.05:02:59.22#ibcon#about to read 6, iclass 34, count 0 2006.201.05:02:59.22#ibcon#read 6, iclass 34, count 0 2006.201.05:02:59.22#ibcon#end of sib2, iclass 34, count 0 2006.201.05:02:59.22#ibcon#*after write, iclass 34, count 0 2006.201.05:02:59.22#ibcon#*before return 0, iclass 34, count 0 2006.201.05:02:59.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:02:59.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:02:59.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.05:02:59.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.05:02:59.22$vck44/valo=4,624.99 2006.201.05:02:59.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.05:02:59.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.05:02:59.22#ibcon#ireg 17 cls_cnt 0 2006.201.05:02:59.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:02:59.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:02:59.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:02:59.22#ibcon#enter wrdev, iclass 36, count 0 2006.201.05:02:59.22#ibcon#first serial, iclass 36, count 0 2006.201.05:02:59.22#ibcon#enter sib2, iclass 36, count 0 2006.201.05:02:59.22#ibcon#flushed, iclass 36, count 0 2006.201.05:02:59.22#ibcon#about to write, iclass 36, count 0 2006.201.05:02:59.22#ibcon#wrote, iclass 36, count 0 2006.201.05:02:59.22#ibcon#about to read 3, iclass 36, count 0 2006.201.05:02:59.24#ibcon#read 3, iclass 36, count 0 2006.201.05:02:59.24#ibcon#about to read 4, iclass 36, count 0 2006.201.05:02:59.24#ibcon#read 4, iclass 36, count 0 2006.201.05:02:59.24#ibcon#about to read 5, iclass 36, count 0 2006.201.05:02:59.24#ibcon#read 5, iclass 36, count 0 2006.201.05:02:59.24#ibcon#about to read 6, iclass 36, count 0 2006.201.05:02:59.24#ibcon#read 6, iclass 36, count 0 2006.201.05:02:59.24#ibcon#end of sib2, iclass 36, count 0 2006.201.05:02:59.24#ibcon#*mode == 0, iclass 36, count 0 2006.201.05:02:59.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.05:02:59.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:02:59.24#ibcon#*before write, iclass 36, count 0 2006.201.05:02:59.24#ibcon#enter sib2, iclass 36, count 0 2006.201.05:02:59.24#ibcon#flushed, iclass 36, count 0 2006.201.05:02:59.24#ibcon#about to write, iclass 36, count 0 2006.201.05:02:59.24#ibcon#wrote, iclass 36, count 0 2006.201.05:02:59.24#ibcon#about to read 3, iclass 36, count 0 2006.201.05:02:59.28#ibcon#read 3, iclass 36, count 0 2006.201.05:02:59.28#ibcon#about to read 4, iclass 36, count 0 2006.201.05:02:59.28#ibcon#read 4, iclass 36, count 0 2006.201.05:02:59.28#ibcon#about to read 5, iclass 36, count 0 2006.201.05:02:59.28#ibcon#read 5, iclass 36, count 0 2006.201.05:02:59.28#ibcon#about to read 6, iclass 36, count 0 2006.201.05:02:59.28#ibcon#read 6, iclass 36, count 0 2006.201.05:02:59.28#ibcon#end of sib2, iclass 36, count 0 2006.201.05:02:59.28#ibcon#*after write, iclass 36, count 0 2006.201.05:02:59.28#ibcon#*before return 0, iclass 36, count 0 2006.201.05:02:59.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:02:59.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:02:59.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.05:02:59.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.05:02:59.28$vck44/va=4,7 2006.201.05:02:59.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.05:02:59.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.05:02:59.28#ibcon#ireg 11 cls_cnt 2 2006.201.05:02:59.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:02:59.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:02:59.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:02:59.34#ibcon#enter wrdev, iclass 38, count 2 2006.201.05:02:59.34#ibcon#first serial, iclass 38, count 2 2006.201.05:02:59.34#ibcon#enter sib2, iclass 38, count 2 2006.201.05:02:59.34#ibcon#flushed, iclass 38, count 2 2006.201.05:02:59.34#ibcon#about to write, iclass 38, count 2 2006.201.05:02:59.34#ibcon#wrote, iclass 38, count 2 2006.201.05:02:59.34#ibcon#about to read 3, iclass 38, count 2 2006.201.05:02:59.36#ibcon#read 3, iclass 38, count 2 2006.201.05:02:59.36#ibcon#about to read 4, iclass 38, count 2 2006.201.05:02:59.36#ibcon#read 4, iclass 38, count 2 2006.201.05:02:59.36#ibcon#about to read 5, iclass 38, count 2 2006.201.05:02:59.36#ibcon#read 5, iclass 38, count 2 2006.201.05:02:59.36#ibcon#about to read 6, iclass 38, count 2 2006.201.05:02:59.36#ibcon#read 6, iclass 38, count 2 2006.201.05:02:59.36#ibcon#end of sib2, iclass 38, count 2 2006.201.05:02:59.36#ibcon#*mode == 0, iclass 38, count 2 2006.201.05:02:59.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.05:02:59.36#ibcon#[25=AT04-07\r\n] 2006.201.05:02:59.36#ibcon#*before write, iclass 38, count 2 2006.201.05:02:59.36#ibcon#enter sib2, iclass 38, count 2 2006.201.05:02:59.36#ibcon#flushed, iclass 38, count 2 2006.201.05:02:59.36#ibcon#about to write, iclass 38, count 2 2006.201.05:02:59.36#ibcon#wrote, iclass 38, count 2 2006.201.05:02:59.36#ibcon#about to read 3, iclass 38, count 2 2006.201.05:02:59.39#ibcon#read 3, iclass 38, count 2 2006.201.05:02:59.40#ibcon#about to read 4, iclass 38, count 2 2006.201.05:02:59.40#ibcon#read 4, iclass 38, count 2 2006.201.05:02:59.40#ibcon#about to read 5, iclass 38, count 2 2006.201.05:02:59.40#ibcon#read 5, iclass 38, count 2 2006.201.05:02:59.40#ibcon#about to read 6, iclass 38, count 2 2006.201.05:02:59.40#ibcon#read 6, iclass 38, count 2 2006.201.05:02:59.40#ibcon#end of sib2, iclass 38, count 2 2006.201.05:02:59.40#ibcon#*after write, iclass 38, count 2 2006.201.05:02:59.40#ibcon#*before return 0, iclass 38, count 2 2006.201.05:02:59.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:02:59.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:02:59.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.05:02:59.40#ibcon#ireg 7 cls_cnt 0 2006.201.05:02:59.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:02:59.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:02:59.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:02:59.52#ibcon#enter wrdev, iclass 38, count 0 2006.201.05:02:59.52#ibcon#first serial, iclass 38, count 0 2006.201.05:02:59.52#ibcon#enter sib2, iclass 38, count 0 2006.201.05:02:59.52#ibcon#flushed, iclass 38, count 0 2006.201.05:02:59.52#ibcon#about to write, iclass 38, count 0 2006.201.05:02:59.52#ibcon#wrote, iclass 38, count 0 2006.201.05:02:59.52#ibcon#about to read 3, iclass 38, count 0 2006.201.05:02:59.54#ibcon#read 3, iclass 38, count 0 2006.201.05:02:59.54#ibcon#about to read 4, iclass 38, count 0 2006.201.05:02:59.54#ibcon#read 4, iclass 38, count 0 2006.201.05:02:59.54#ibcon#about to read 5, iclass 38, count 0 2006.201.05:02:59.54#ibcon#read 5, iclass 38, count 0 2006.201.05:02:59.54#ibcon#about to read 6, iclass 38, count 0 2006.201.05:02:59.54#ibcon#read 6, iclass 38, count 0 2006.201.05:02:59.54#ibcon#end of sib2, iclass 38, count 0 2006.201.05:02:59.54#ibcon#*mode == 0, iclass 38, count 0 2006.201.05:02:59.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.05:02:59.54#ibcon#[25=USB\r\n] 2006.201.05:02:59.54#ibcon#*before write, iclass 38, count 0 2006.201.05:02:59.54#ibcon#enter sib2, iclass 38, count 0 2006.201.05:02:59.54#ibcon#flushed, iclass 38, count 0 2006.201.05:02:59.54#ibcon#about to write, iclass 38, count 0 2006.201.05:02:59.54#ibcon#wrote, iclass 38, count 0 2006.201.05:02:59.54#ibcon#about to read 3, iclass 38, count 0 2006.201.05:02:59.57#ibcon#read 3, iclass 38, count 0 2006.201.05:02:59.57#ibcon#about to read 4, iclass 38, count 0 2006.201.05:02:59.57#ibcon#read 4, iclass 38, count 0 2006.201.05:02:59.57#ibcon#about to read 5, iclass 38, count 0 2006.201.05:02:59.57#ibcon#read 5, iclass 38, count 0 2006.201.05:02:59.57#ibcon#about to read 6, iclass 38, count 0 2006.201.05:02:59.57#ibcon#read 6, iclass 38, count 0 2006.201.05:02:59.57#ibcon#end of sib2, iclass 38, count 0 2006.201.05:02:59.57#ibcon#*after write, iclass 38, count 0 2006.201.05:02:59.57#ibcon#*before return 0, iclass 38, count 0 2006.201.05:02:59.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:02:59.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:02:59.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.05:02:59.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.05:02:59.57$vck44/valo=5,734.99 2006.201.05:02:59.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.05:02:59.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.05:02:59.57#ibcon#ireg 17 cls_cnt 0 2006.201.05:02:59.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:02:59.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:02:59.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:02:59.57#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:02:59.57#ibcon#first serial, iclass 40, count 0 2006.201.05:02:59.57#ibcon#enter sib2, iclass 40, count 0 2006.201.05:02:59.57#ibcon#flushed, iclass 40, count 0 2006.201.05:02:59.57#ibcon#about to write, iclass 40, count 0 2006.201.05:02:59.57#ibcon#wrote, iclass 40, count 0 2006.201.05:02:59.57#ibcon#about to read 3, iclass 40, count 0 2006.201.05:02:59.59#ibcon#read 3, iclass 40, count 0 2006.201.05:02:59.59#ibcon#about to read 4, iclass 40, count 0 2006.201.05:02:59.59#ibcon#read 4, iclass 40, count 0 2006.201.05:02:59.59#ibcon#about to read 5, iclass 40, count 0 2006.201.05:02:59.59#ibcon#read 5, iclass 40, count 0 2006.201.05:02:59.59#ibcon#about to read 6, iclass 40, count 0 2006.201.05:02:59.59#ibcon#read 6, iclass 40, count 0 2006.201.05:02:59.59#ibcon#end of sib2, iclass 40, count 0 2006.201.05:02:59.59#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:02:59.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:02:59.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:02:59.59#ibcon#*before write, iclass 40, count 0 2006.201.05:02:59.59#ibcon#enter sib2, iclass 40, count 0 2006.201.05:02:59.59#ibcon#flushed, iclass 40, count 0 2006.201.05:02:59.59#ibcon#about to write, iclass 40, count 0 2006.201.05:02:59.59#ibcon#wrote, iclass 40, count 0 2006.201.05:02:59.59#ibcon#about to read 3, iclass 40, count 0 2006.201.05:02:59.63#ibcon#read 3, iclass 40, count 0 2006.201.05:02:59.63#ibcon#about to read 4, iclass 40, count 0 2006.201.05:02:59.63#ibcon#read 4, iclass 40, count 0 2006.201.05:02:59.63#ibcon#about to read 5, iclass 40, count 0 2006.201.05:02:59.63#ibcon#read 5, iclass 40, count 0 2006.201.05:02:59.63#ibcon#about to read 6, iclass 40, count 0 2006.201.05:02:59.63#ibcon#read 6, iclass 40, count 0 2006.201.05:02:59.63#ibcon#end of sib2, iclass 40, count 0 2006.201.05:02:59.63#ibcon#*after write, iclass 40, count 0 2006.201.05:02:59.63#ibcon#*before return 0, iclass 40, count 0 2006.201.05:02:59.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:02:59.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:02:59.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:02:59.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:02:59.63$vck44/va=5,4 2006.201.05:02:59.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.05:02:59.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.05:02:59.63#ibcon#ireg 11 cls_cnt 2 2006.201.05:02:59.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:02:59.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:02:59.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:02:59.69#ibcon#enter wrdev, iclass 4, count 2 2006.201.05:02:59.69#ibcon#first serial, iclass 4, count 2 2006.201.05:02:59.69#ibcon#enter sib2, iclass 4, count 2 2006.201.05:02:59.69#ibcon#flushed, iclass 4, count 2 2006.201.05:02:59.69#ibcon#about to write, iclass 4, count 2 2006.201.05:02:59.69#ibcon#wrote, iclass 4, count 2 2006.201.05:02:59.69#ibcon#about to read 3, iclass 4, count 2 2006.201.05:02:59.71#ibcon#read 3, iclass 4, count 2 2006.201.05:02:59.71#ibcon#about to read 4, iclass 4, count 2 2006.201.05:02:59.71#ibcon#read 4, iclass 4, count 2 2006.201.05:02:59.71#ibcon#about to read 5, iclass 4, count 2 2006.201.05:02:59.71#ibcon#read 5, iclass 4, count 2 2006.201.05:02:59.71#ibcon#about to read 6, iclass 4, count 2 2006.201.05:02:59.71#ibcon#read 6, iclass 4, count 2 2006.201.05:02:59.71#ibcon#end of sib2, iclass 4, count 2 2006.201.05:02:59.71#ibcon#*mode == 0, iclass 4, count 2 2006.201.05:02:59.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.05:02:59.71#ibcon#[25=AT05-04\r\n] 2006.201.05:02:59.71#ibcon#*before write, iclass 4, count 2 2006.201.05:02:59.71#ibcon#enter sib2, iclass 4, count 2 2006.201.05:02:59.71#ibcon#flushed, iclass 4, count 2 2006.201.05:02:59.71#ibcon#about to write, iclass 4, count 2 2006.201.05:02:59.71#ibcon#wrote, iclass 4, count 2 2006.201.05:02:59.71#ibcon#about to read 3, iclass 4, count 2 2006.201.05:02:59.74#ibcon#read 3, iclass 4, count 2 2006.201.05:02:59.74#ibcon#about to read 4, iclass 4, count 2 2006.201.05:02:59.74#ibcon#read 4, iclass 4, count 2 2006.201.05:02:59.74#ibcon#about to read 5, iclass 4, count 2 2006.201.05:02:59.74#ibcon#read 5, iclass 4, count 2 2006.201.05:02:59.74#ibcon#about to read 6, iclass 4, count 2 2006.201.05:02:59.74#ibcon#read 6, iclass 4, count 2 2006.201.05:02:59.74#ibcon#end of sib2, iclass 4, count 2 2006.201.05:02:59.74#ibcon#*after write, iclass 4, count 2 2006.201.05:02:59.74#ibcon#*before return 0, iclass 4, count 2 2006.201.05:02:59.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:02:59.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:02:59.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.05:02:59.74#ibcon#ireg 7 cls_cnt 0 2006.201.05:02:59.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:02:59.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:02:59.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:02:59.86#ibcon#enter wrdev, iclass 4, count 0 2006.201.05:02:59.86#ibcon#first serial, iclass 4, count 0 2006.201.05:02:59.86#ibcon#enter sib2, iclass 4, count 0 2006.201.05:02:59.86#ibcon#flushed, iclass 4, count 0 2006.201.05:02:59.86#ibcon#about to write, iclass 4, count 0 2006.201.05:02:59.86#ibcon#wrote, iclass 4, count 0 2006.201.05:02:59.86#ibcon#about to read 3, iclass 4, count 0 2006.201.05:02:59.88#ibcon#read 3, iclass 4, count 0 2006.201.05:02:59.88#ibcon#about to read 4, iclass 4, count 0 2006.201.05:02:59.88#ibcon#read 4, iclass 4, count 0 2006.201.05:02:59.88#ibcon#about to read 5, iclass 4, count 0 2006.201.05:02:59.88#ibcon#read 5, iclass 4, count 0 2006.201.05:02:59.88#ibcon#about to read 6, iclass 4, count 0 2006.201.05:02:59.88#ibcon#read 6, iclass 4, count 0 2006.201.05:02:59.88#ibcon#end of sib2, iclass 4, count 0 2006.201.05:02:59.88#ibcon#*mode == 0, iclass 4, count 0 2006.201.05:02:59.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.05:02:59.88#ibcon#[25=USB\r\n] 2006.201.05:02:59.88#ibcon#*before write, iclass 4, count 0 2006.201.05:02:59.88#ibcon#enter sib2, iclass 4, count 0 2006.201.05:02:59.88#ibcon#flushed, iclass 4, count 0 2006.201.05:02:59.88#ibcon#about to write, iclass 4, count 0 2006.201.05:02:59.88#ibcon#wrote, iclass 4, count 0 2006.201.05:02:59.88#ibcon#about to read 3, iclass 4, count 0 2006.201.05:02:59.91#ibcon#read 3, iclass 4, count 0 2006.201.05:02:59.91#ibcon#about to read 4, iclass 4, count 0 2006.201.05:02:59.91#ibcon#read 4, iclass 4, count 0 2006.201.05:02:59.91#ibcon#about to read 5, iclass 4, count 0 2006.201.05:02:59.91#ibcon#read 5, iclass 4, count 0 2006.201.05:02:59.91#ibcon#about to read 6, iclass 4, count 0 2006.201.05:02:59.91#ibcon#read 6, iclass 4, count 0 2006.201.05:02:59.91#ibcon#end of sib2, iclass 4, count 0 2006.201.05:02:59.91#ibcon#*after write, iclass 4, count 0 2006.201.05:02:59.91#ibcon#*before return 0, iclass 4, count 0 2006.201.05:02:59.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:02:59.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:02:59.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.05:02:59.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.05:02:59.91$vck44/valo=6,814.99 2006.201.05:02:59.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.05:02:59.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.05:02:59.91#ibcon#ireg 17 cls_cnt 0 2006.201.05:02:59.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:02:59.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:02:59.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:02:59.91#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:02:59.91#ibcon#first serial, iclass 6, count 0 2006.201.05:02:59.91#ibcon#enter sib2, iclass 6, count 0 2006.201.05:02:59.91#ibcon#flushed, iclass 6, count 0 2006.201.05:02:59.91#ibcon#about to write, iclass 6, count 0 2006.201.05:02:59.91#ibcon#wrote, iclass 6, count 0 2006.201.05:02:59.91#ibcon#about to read 3, iclass 6, count 0 2006.201.05:02:59.93#ibcon#read 3, iclass 6, count 0 2006.201.05:02:59.93#ibcon#about to read 4, iclass 6, count 0 2006.201.05:02:59.93#ibcon#read 4, iclass 6, count 0 2006.201.05:02:59.93#ibcon#about to read 5, iclass 6, count 0 2006.201.05:02:59.93#ibcon#read 5, iclass 6, count 0 2006.201.05:02:59.93#ibcon#about to read 6, iclass 6, count 0 2006.201.05:02:59.93#ibcon#read 6, iclass 6, count 0 2006.201.05:02:59.93#ibcon#end of sib2, iclass 6, count 0 2006.201.05:02:59.93#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:02:59.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:02:59.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:02:59.93#ibcon#*before write, iclass 6, count 0 2006.201.05:02:59.93#ibcon#enter sib2, iclass 6, count 0 2006.201.05:02:59.93#ibcon#flushed, iclass 6, count 0 2006.201.05:02:59.93#ibcon#about to write, iclass 6, count 0 2006.201.05:02:59.93#ibcon#wrote, iclass 6, count 0 2006.201.05:02:59.93#ibcon#about to read 3, iclass 6, count 0 2006.201.05:02:59.97#ibcon#read 3, iclass 6, count 0 2006.201.05:02:59.97#ibcon#about to read 4, iclass 6, count 0 2006.201.05:02:59.97#ibcon#read 4, iclass 6, count 0 2006.201.05:02:59.97#ibcon#about to read 5, iclass 6, count 0 2006.201.05:02:59.97#ibcon#read 5, iclass 6, count 0 2006.201.05:02:59.97#ibcon#about to read 6, iclass 6, count 0 2006.201.05:02:59.97#ibcon#read 6, iclass 6, count 0 2006.201.05:02:59.97#ibcon#end of sib2, iclass 6, count 0 2006.201.05:02:59.97#ibcon#*after write, iclass 6, count 0 2006.201.05:02:59.97#ibcon#*before return 0, iclass 6, count 0 2006.201.05:02:59.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:02:59.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:02:59.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:02:59.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:02:59.97$vck44/va=6,5 2006.201.05:02:59.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.05:02:59.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.05:02:59.97#ibcon#ireg 11 cls_cnt 2 2006.201.05:02:59.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:00.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:00.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:00.03#ibcon#enter wrdev, iclass 10, count 2 2006.201.05:03:00.03#ibcon#first serial, iclass 10, count 2 2006.201.05:03:00.03#ibcon#enter sib2, iclass 10, count 2 2006.201.05:03:00.03#ibcon#flushed, iclass 10, count 2 2006.201.05:03:00.03#ibcon#about to write, iclass 10, count 2 2006.201.05:03:00.03#ibcon#wrote, iclass 10, count 2 2006.201.05:03:00.03#ibcon#about to read 3, iclass 10, count 2 2006.201.05:03:00.05#ibcon#read 3, iclass 10, count 2 2006.201.05:03:00.05#ibcon#about to read 4, iclass 10, count 2 2006.201.05:03:00.05#ibcon#read 4, iclass 10, count 2 2006.201.05:03:00.05#ibcon#about to read 5, iclass 10, count 2 2006.201.05:03:00.05#ibcon#read 5, iclass 10, count 2 2006.201.05:03:00.05#ibcon#about to read 6, iclass 10, count 2 2006.201.05:03:00.05#ibcon#read 6, iclass 10, count 2 2006.201.05:03:00.05#ibcon#end of sib2, iclass 10, count 2 2006.201.05:03:00.05#ibcon#*mode == 0, iclass 10, count 2 2006.201.05:03:00.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.05:03:00.05#ibcon#[25=AT06-05\r\n] 2006.201.05:03:00.05#ibcon#*before write, iclass 10, count 2 2006.201.05:03:00.05#ibcon#enter sib2, iclass 10, count 2 2006.201.05:03:00.05#ibcon#flushed, iclass 10, count 2 2006.201.05:03:00.05#ibcon#about to write, iclass 10, count 2 2006.201.05:03:00.05#ibcon#wrote, iclass 10, count 2 2006.201.05:03:00.05#ibcon#about to read 3, iclass 10, count 2 2006.201.05:03:00.07#abcon#<5=/04 2.9 6.8 23.27 891003.9\r\n> 2006.201.05:03:00.08#ibcon#read 3, iclass 10, count 2 2006.201.05:03:00.08#ibcon#about to read 4, iclass 10, count 2 2006.201.05:03:00.08#ibcon#read 4, iclass 10, count 2 2006.201.05:03:00.08#ibcon#about to read 5, iclass 10, count 2 2006.201.05:03:00.08#ibcon#read 5, iclass 10, count 2 2006.201.05:03:00.08#ibcon#about to read 6, iclass 10, count 2 2006.201.05:03:00.08#ibcon#read 6, iclass 10, count 2 2006.201.05:03:00.08#ibcon#end of sib2, iclass 10, count 2 2006.201.05:03:00.08#ibcon#*after write, iclass 10, count 2 2006.201.05:03:00.08#ibcon#*before return 0, iclass 10, count 2 2006.201.05:03:00.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:00.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:00.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.05:03:00.08#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:00.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:00.09#abcon#{5=INTERFACE CLEAR} 2006.201.05:03:00.15#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:03:00.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:00.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:00.20#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:03:00.20#ibcon#first serial, iclass 10, count 0 2006.201.05:03:00.20#ibcon#enter sib2, iclass 10, count 0 2006.201.05:03:00.20#ibcon#flushed, iclass 10, count 0 2006.201.05:03:00.20#ibcon#about to write, iclass 10, count 0 2006.201.05:03:00.20#ibcon#wrote, iclass 10, count 0 2006.201.05:03:00.20#ibcon#about to read 3, iclass 10, count 0 2006.201.05:03:00.22#ibcon#read 3, iclass 10, count 0 2006.201.05:03:00.22#ibcon#about to read 4, iclass 10, count 0 2006.201.05:03:00.22#ibcon#read 4, iclass 10, count 0 2006.201.05:03:00.22#ibcon#about to read 5, iclass 10, count 0 2006.201.05:03:00.22#ibcon#read 5, iclass 10, count 0 2006.201.05:03:00.22#ibcon#about to read 6, iclass 10, count 0 2006.201.05:03:00.22#ibcon#read 6, iclass 10, count 0 2006.201.05:03:00.22#ibcon#end of sib2, iclass 10, count 0 2006.201.05:03:00.22#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:03:00.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:03:00.22#ibcon#[25=USB\r\n] 2006.201.05:03:00.22#ibcon#*before write, iclass 10, count 0 2006.201.05:03:00.22#ibcon#enter sib2, iclass 10, count 0 2006.201.05:03:00.22#ibcon#flushed, iclass 10, count 0 2006.201.05:03:00.22#ibcon#about to write, iclass 10, count 0 2006.201.05:03:00.22#ibcon#wrote, iclass 10, count 0 2006.201.05:03:00.22#ibcon#about to read 3, iclass 10, count 0 2006.201.05:03:00.25#ibcon#read 3, iclass 10, count 0 2006.201.05:03:00.25#ibcon#about to read 4, iclass 10, count 0 2006.201.05:03:00.25#ibcon#read 4, iclass 10, count 0 2006.201.05:03:00.25#ibcon#about to read 5, iclass 10, count 0 2006.201.05:03:00.25#ibcon#read 5, iclass 10, count 0 2006.201.05:03:00.25#ibcon#about to read 6, iclass 10, count 0 2006.201.05:03:00.25#ibcon#read 6, iclass 10, count 0 2006.201.05:03:00.25#ibcon#end of sib2, iclass 10, count 0 2006.201.05:03:00.25#ibcon#*after write, iclass 10, count 0 2006.201.05:03:00.25#ibcon#*before return 0, iclass 10, count 0 2006.201.05:03:00.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:00.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:00.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:03:00.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:03:00.25$vck44/valo=7,864.99 2006.201.05:03:00.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.05:03:00.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.05:03:00.25#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:00.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:00.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:00.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:00.25#ibcon#enter wrdev, iclass 16, count 0 2006.201.05:03:00.25#ibcon#first serial, iclass 16, count 0 2006.201.05:03:00.25#ibcon#enter sib2, iclass 16, count 0 2006.201.05:03:00.25#ibcon#flushed, iclass 16, count 0 2006.201.05:03:00.25#ibcon#about to write, iclass 16, count 0 2006.201.05:03:00.25#ibcon#wrote, iclass 16, count 0 2006.201.05:03:00.25#ibcon#about to read 3, iclass 16, count 0 2006.201.05:03:00.27#ibcon#read 3, iclass 16, count 0 2006.201.05:03:00.27#ibcon#about to read 4, iclass 16, count 0 2006.201.05:03:00.27#ibcon#read 4, iclass 16, count 0 2006.201.05:03:00.27#ibcon#about to read 5, iclass 16, count 0 2006.201.05:03:00.27#ibcon#read 5, iclass 16, count 0 2006.201.05:03:00.27#ibcon#about to read 6, iclass 16, count 0 2006.201.05:03:00.27#ibcon#read 6, iclass 16, count 0 2006.201.05:03:00.27#ibcon#end of sib2, iclass 16, count 0 2006.201.05:03:00.27#ibcon#*mode == 0, iclass 16, count 0 2006.201.05:03:00.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.05:03:00.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:03:00.27#ibcon#*before write, iclass 16, count 0 2006.201.05:03:00.27#ibcon#enter sib2, iclass 16, count 0 2006.201.05:03:00.27#ibcon#flushed, iclass 16, count 0 2006.201.05:03:00.27#ibcon#about to write, iclass 16, count 0 2006.201.05:03:00.27#ibcon#wrote, iclass 16, count 0 2006.201.05:03:00.27#ibcon#about to read 3, iclass 16, count 0 2006.201.05:03:00.31#ibcon#read 3, iclass 16, count 0 2006.201.05:03:00.31#ibcon#about to read 4, iclass 16, count 0 2006.201.05:03:00.31#ibcon#read 4, iclass 16, count 0 2006.201.05:03:00.31#ibcon#about to read 5, iclass 16, count 0 2006.201.05:03:00.31#ibcon#read 5, iclass 16, count 0 2006.201.05:03:00.31#ibcon#about to read 6, iclass 16, count 0 2006.201.05:03:00.31#ibcon#read 6, iclass 16, count 0 2006.201.05:03:00.31#ibcon#end of sib2, iclass 16, count 0 2006.201.05:03:00.31#ibcon#*after write, iclass 16, count 0 2006.201.05:03:00.31#ibcon#*before return 0, iclass 16, count 0 2006.201.05:03:00.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:00.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:00.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.05:03:00.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.05:03:00.31$vck44/va=7,5 2006.201.05:03:00.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.05:03:00.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.05:03:00.31#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:00.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:00.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:00.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:00.37#ibcon#enter wrdev, iclass 18, count 2 2006.201.05:03:00.37#ibcon#first serial, iclass 18, count 2 2006.201.05:03:00.37#ibcon#enter sib2, iclass 18, count 2 2006.201.05:03:00.37#ibcon#flushed, iclass 18, count 2 2006.201.05:03:00.37#ibcon#about to write, iclass 18, count 2 2006.201.05:03:00.37#ibcon#wrote, iclass 18, count 2 2006.201.05:03:00.37#ibcon#about to read 3, iclass 18, count 2 2006.201.05:03:00.39#ibcon#read 3, iclass 18, count 2 2006.201.05:03:00.39#ibcon#about to read 4, iclass 18, count 2 2006.201.05:03:00.39#ibcon#read 4, iclass 18, count 2 2006.201.05:03:00.39#ibcon#about to read 5, iclass 18, count 2 2006.201.05:03:00.39#ibcon#read 5, iclass 18, count 2 2006.201.05:03:00.39#ibcon#about to read 6, iclass 18, count 2 2006.201.05:03:00.39#ibcon#read 6, iclass 18, count 2 2006.201.05:03:00.39#ibcon#end of sib2, iclass 18, count 2 2006.201.05:03:00.39#ibcon#*mode == 0, iclass 18, count 2 2006.201.05:03:00.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.05:03:00.39#ibcon#[25=AT07-05\r\n] 2006.201.05:03:00.39#ibcon#*before write, iclass 18, count 2 2006.201.05:03:00.39#ibcon#enter sib2, iclass 18, count 2 2006.201.05:03:00.39#ibcon#flushed, iclass 18, count 2 2006.201.05:03:00.39#ibcon#about to write, iclass 18, count 2 2006.201.05:03:00.39#ibcon#wrote, iclass 18, count 2 2006.201.05:03:00.39#ibcon#about to read 3, iclass 18, count 2 2006.201.05:03:00.45#ibcon#read 3, iclass 18, count 2 2006.201.05:03:00.45#ibcon#about to read 4, iclass 18, count 2 2006.201.05:03:00.45#ibcon#read 4, iclass 18, count 2 2006.201.05:03:00.45#ibcon#about to read 5, iclass 18, count 2 2006.201.05:03:00.45#ibcon#read 5, iclass 18, count 2 2006.201.05:03:00.45#ibcon#about to read 6, iclass 18, count 2 2006.201.05:03:00.45#ibcon#read 6, iclass 18, count 2 2006.201.05:03:00.45#ibcon#end of sib2, iclass 18, count 2 2006.201.05:03:00.45#ibcon#*after write, iclass 18, count 2 2006.201.05:03:00.45#ibcon#*before return 0, iclass 18, count 2 2006.201.05:03:00.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:00.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:00.46#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.05:03:00.46#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:00.46#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:00.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:00.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:00.57#ibcon#enter wrdev, iclass 18, count 0 2006.201.05:03:00.57#ibcon#first serial, iclass 18, count 0 2006.201.05:03:00.57#ibcon#enter sib2, iclass 18, count 0 2006.201.05:03:00.57#ibcon#flushed, iclass 18, count 0 2006.201.05:03:00.57#ibcon#about to write, iclass 18, count 0 2006.201.05:03:00.57#ibcon#wrote, iclass 18, count 0 2006.201.05:03:00.57#ibcon#about to read 3, iclass 18, count 0 2006.201.05:03:00.59#ibcon#read 3, iclass 18, count 0 2006.201.05:03:00.59#ibcon#about to read 4, iclass 18, count 0 2006.201.05:03:00.59#ibcon#read 4, iclass 18, count 0 2006.201.05:03:00.59#ibcon#about to read 5, iclass 18, count 0 2006.201.05:03:00.59#ibcon#read 5, iclass 18, count 0 2006.201.05:03:00.59#ibcon#about to read 6, iclass 18, count 0 2006.201.05:03:00.59#ibcon#read 6, iclass 18, count 0 2006.201.05:03:00.59#ibcon#end of sib2, iclass 18, count 0 2006.201.05:03:00.59#ibcon#*mode == 0, iclass 18, count 0 2006.201.05:03:00.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.05:03:00.59#ibcon#[25=USB\r\n] 2006.201.05:03:00.59#ibcon#*before write, iclass 18, count 0 2006.201.05:03:00.59#ibcon#enter sib2, iclass 18, count 0 2006.201.05:03:00.59#ibcon#flushed, iclass 18, count 0 2006.201.05:03:00.59#ibcon#about to write, iclass 18, count 0 2006.201.05:03:00.59#ibcon#wrote, iclass 18, count 0 2006.201.05:03:00.59#ibcon#about to read 3, iclass 18, count 0 2006.201.05:03:00.62#ibcon#read 3, iclass 18, count 0 2006.201.05:03:00.62#ibcon#about to read 4, iclass 18, count 0 2006.201.05:03:00.62#ibcon#read 4, iclass 18, count 0 2006.201.05:03:00.62#ibcon#about to read 5, iclass 18, count 0 2006.201.05:03:00.62#ibcon#read 5, iclass 18, count 0 2006.201.05:03:00.62#ibcon#about to read 6, iclass 18, count 0 2006.201.05:03:00.62#ibcon#read 6, iclass 18, count 0 2006.201.05:03:00.62#ibcon#end of sib2, iclass 18, count 0 2006.201.05:03:00.62#ibcon#*after write, iclass 18, count 0 2006.201.05:03:00.62#ibcon#*before return 0, iclass 18, count 0 2006.201.05:03:00.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:00.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:00.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.05:03:00.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.05:03:00.62$vck44/valo=8,884.99 2006.201.05:03:00.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.05:03:00.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.05:03:00.62#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:00.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:00.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:00.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:00.62#ibcon#enter wrdev, iclass 20, count 0 2006.201.05:03:00.62#ibcon#first serial, iclass 20, count 0 2006.201.05:03:00.62#ibcon#enter sib2, iclass 20, count 0 2006.201.05:03:00.62#ibcon#flushed, iclass 20, count 0 2006.201.05:03:00.62#ibcon#about to write, iclass 20, count 0 2006.201.05:03:00.62#ibcon#wrote, iclass 20, count 0 2006.201.05:03:00.62#ibcon#about to read 3, iclass 20, count 0 2006.201.05:03:00.64#ibcon#read 3, iclass 20, count 0 2006.201.05:03:00.64#ibcon#about to read 4, iclass 20, count 0 2006.201.05:03:00.64#ibcon#read 4, iclass 20, count 0 2006.201.05:03:00.64#ibcon#about to read 5, iclass 20, count 0 2006.201.05:03:00.64#ibcon#read 5, iclass 20, count 0 2006.201.05:03:00.64#ibcon#about to read 6, iclass 20, count 0 2006.201.05:03:00.64#ibcon#read 6, iclass 20, count 0 2006.201.05:03:00.64#ibcon#end of sib2, iclass 20, count 0 2006.201.05:03:00.64#ibcon#*mode == 0, iclass 20, count 0 2006.201.05:03:00.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.05:03:00.64#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:03:00.64#ibcon#*before write, iclass 20, count 0 2006.201.05:03:00.64#ibcon#enter sib2, iclass 20, count 0 2006.201.05:03:00.64#ibcon#flushed, iclass 20, count 0 2006.201.05:03:00.64#ibcon#about to write, iclass 20, count 0 2006.201.05:03:00.64#ibcon#wrote, iclass 20, count 0 2006.201.05:03:00.64#ibcon#about to read 3, iclass 20, count 0 2006.201.05:03:00.68#ibcon#read 3, iclass 20, count 0 2006.201.05:03:00.68#ibcon#about to read 4, iclass 20, count 0 2006.201.05:03:00.68#ibcon#read 4, iclass 20, count 0 2006.201.05:03:00.68#ibcon#about to read 5, iclass 20, count 0 2006.201.05:03:00.68#ibcon#read 5, iclass 20, count 0 2006.201.05:03:00.68#ibcon#about to read 6, iclass 20, count 0 2006.201.05:03:00.68#ibcon#read 6, iclass 20, count 0 2006.201.05:03:00.68#ibcon#end of sib2, iclass 20, count 0 2006.201.05:03:00.68#ibcon#*after write, iclass 20, count 0 2006.201.05:03:00.68#ibcon#*before return 0, iclass 20, count 0 2006.201.05:03:00.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:00.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:00.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.05:03:00.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.05:03:00.68$vck44/va=8,4 2006.201.05:03:00.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.05:03:00.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.05:03:00.68#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:00.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:03:00.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:03:00.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:03:00.74#ibcon#enter wrdev, iclass 22, count 2 2006.201.05:03:00.74#ibcon#first serial, iclass 22, count 2 2006.201.05:03:00.74#ibcon#enter sib2, iclass 22, count 2 2006.201.05:03:00.74#ibcon#flushed, iclass 22, count 2 2006.201.05:03:00.74#ibcon#about to write, iclass 22, count 2 2006.201.05:03:00.74#ibcon#wrote, iclass 22, count 2 2006.201.05:03:00.74#ibcon#about to read 3, iclass 22, count 2 2006.201.05:03:00.76#ibcon#read 3, iclass 22, count 2 2006.201.05:03:00.76#ibcon#about to read 4, iclass 22, count 2 2006.201.05:03:00.76#ibcon#read 4, iclass 22, count 2 2006.201.05:03:00.76#ibcon#about to read 5, iclass 22, count 2 2006.201.05:03:00.76#ibcon#read 5, iclass 22, count 2 2006.201.05:03:00.76#ibcon#about to read 6, iclass 22, count 2 2006.201.05:03:00.76#ibcon#read 6, iclass 22, count 2 2006.201.05:03:00.76#ibcon#end of sib2, iclass 22, count 2 2006.201.05:03:00.76#ibcon#*mode == 0, iclass 22, count 2 2006.201.05:03:00.76#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.05:03:00.76#ibcon#[25=AT08-04\r\n] 2006.201.05:03:00.76#ibcon#*before write, iclass 22, count 2 2006.201.05:03:00.76#ibcon#enter sib2, iclass 22, count 2 2006.201.05:03:00.76#ibcon#flushed, iclass 22, count 2 2006.201.05:03:00.76#ibcon#about to write, iclass 22, count 2 2006.201.05:03:00.76#ibcon#wrote, iclass 22, count 2 2006.201.05:03:00.76#ibcon#about to read 3, iclass 22, count 2 2006.201.05:03:00.79#ibcon#read 3, iclass 22, count 2 2006.201.05:03:00.79#ibcon#about to read 4, iclass 22, count 2 2006.201.05:03:00.79#ibcon#read 4, iclass 22, count 2 2006.201.05:03:00.79#ibcon#about to read 5, iclass 22, count 2 2006.201.05:03:00.79#ibcon#read 5, iclass 22, count 2 2006.201.05:03:00.79#ibcon#about to read 6, iclass 22, count 2 2006.201.05:03:00.79#ibcon#read 6, iclass 22, count 2 2006.201.05:03:00.79#ibcon#end of sib2, iclass 22, count 2 2006.201.05:03:00.79#ibcon#*after write, iclass 22, count 2 2006.201.05:03:00.79#ibcon#*before return 0, iclass 22, count 2 2006.201.05:03:00.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:03:00.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:03:00.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.05:03:00.79#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:00.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:03:00.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:03:00.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:03:00.91#ibcon#enter wrdev, iclass 22, count 0 2006.201.05:03:00.91#ibcon#first serial, iclass 22, count 0 2006.201.05:03:00.91#ibcon#enter sib2, iclass 22, count 0 2006.201.05:03:00.91#ibcon#flushed, iclass 22, count 0 2006.201.05:03:00.91#ibcon#about to write, iclass 22, count 0 2006.201.05:03:00.91#ibcon#wrote, iclass 22, count 0 2006.201.05:03:00.91#ibcon#about to read 3, iclass 22, count 0 2006.201.05:03:00.93#ibcon#read 3, iclass 22, count 0 2006.201.05:03:00.93#ibcon#about to read 4, iclass 22, count 0 2006.201.05:03:00.93#ibcon#read 4, iclass 22, count 0 2006.201.05:03:00.93#ibcon#about to read 5, iclass 22, count 0 2006.201.05:03:00.93#ibcon#read 5, iclass 22, count 0 2006.201.05:03:00.93#ibcon#about to read 6, iclass 22, count 0 2006.201.05:03:00.93#ibcon#read 6, iclass 22, count 0 2006.201.05:03:00.93#ibcon#end of sib2, iclass 22, count 0 2006.201.05:03:00.93#ibcon#*mode == 0, iclass 22, count 0 2006.201.05:03:00.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.05:03:00.93#ibcon#[25=USB\r\n] 2006.201.05:03:00.93#ibcon#*before write, iclass 22, count 0 2006.201.05:03:00.93#ibcon#enter sib2, iclass 22, count 0 2006.201.05:03:00.93#ibcon#flushed, iclass 22, count 0 2006.201.05:03:00.93#ibcon#about to write, iclass 22, count 0 2006.201.05:03:00.93#ibcon#wrote, iclass 22, count 0 2006.201.05:03:00.93#ibcon#about to read 3, iclass 22, count 0 2006.201.05:03:00.96#ibcon#read 3, iclass 22, count 0 2006.201.05:03:00.96#ibcon#about to read 4, iclass 22, count 0 2006.201.05:03:00.96#ibcon#read 4, iclass 22, count 0 2006.201.05:03:00.96#ibcon#about to read 5, iclass 22, count 0 2006.201.05:03:00.96#ibcon#read 5, iclass 22, count 0 2006.201.05:03:00.96#ibcon#about to read 6, iclass 22, count 0 2006.201.05:03:00.96#ibcon#read 6, iclass 22, count 0 2006.201.05:03:00.96#ibcon#end of sib2, iclass 22, count 0 2006.201.05:03:00.96#ibcon#*after write, iclass 22, count 0 2006.201.05:03:00.96#ibcon#*before return 0, iclass 22, count 0 2006.201.05:03:00.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:03:00.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:03:00.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.05:03:00.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.05:03:00.96$vck44/vblo=1,629.99 2006.201.05:03:00.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.05:03:00.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.05:03:00.96#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:00.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:03:00.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:03:00.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:03:00.96#ibcon#enter wrdev, iclass 24, count 0 2006.201.05:03:00.96#ibcon#first serial, iclass 24, count 0 2006.201.05:03:00.96#ibcon#enter sib2, iclass 24, count 0 2006.201.05:03:00.96#ibcon#flushed, iclass 24, count 0 2006.201.05:03:00.96#ibcon#about to write, iclass 24, count 0 2006.201.05:03:00.96#ibcon#wrote, iclass 24, count 0 2006.201.05:03:00.96#ibcon#about to read 3, iclass 24, count 0 2006.201.05:03:00.98#ibcon#read 3, iclass 24, count 0 2006.201.05:03:00.98#ibcon#about to read 4, iclass 24, count 0 2006.201.05:03:00.98#ibcon#read 4, iclass 24, count 0 2006.201.05:03:00.98#ibcon#about to read 5, iclass 24, count 0 2006.201.05:03:00.98#ibcon#read 5, iclass 24, count 0 2006.201.05:03:00.98#ibcon#about to read 6, iclass 24, count 0 2006.201.05:03:00.98#ibcon#read 6, iclass 24, count 0 2006.201.05:03:00.98#ibcon#end of sib2, iclass 24, count 0 2006.201.05:03:00.98#ibcon#*mode == 0, iclass 24, count 0 2006.201.05:03:00.98#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.05:03:00.98#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:03:00.98#ibcon#*before write, iclass 24, count 0 2006.201.05:03:00.98#ibcon#enter sib2, iclass 24, count 0 2006.201.05:03:00.98#ibcon#flushed, iclass 24, count 0 2006.201.05:03:00.98#ibcon#about to write, iclass 24, count 0 2006.201.05:03:00.98#ibcon#wrote, iclass 24, count 0 2006.201.05:03:00.98#ibcon#about to read 3, iclass 24, count 0 2006.201.05:03:01.02#ibcon#read 3, iclass 24, count 0 2006.201.05:03:01.02#ibcon#about to read 4, iclass 24, count 0 2006.201.05:03:01.02#ibcon#read 4, iclass 24, count 0 2006.201.05:03:01.02#ibcon#about to read 5, iclass 24, count 0 2006.201.05:03:01.02#ibcon#read 5, iclass 24, count 0 2006.201.05:03:01.02#ibcon#about to read 6, iclass 24, count 0 2006.201.05:03:01.02#ibcon#read 6, iclass 24, count 0 2006.201.05:03:01.02#ibcon#end of sib2, iclass 24, count 0 2006.201.05:03:01.02#ibcon#*after write, iclass 24, count 0 2006.201.05:03:01.02#ibcon#*before return 0, iclass 24, count 0 2006.201.05:03:01.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:03:01.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:03:01.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.05:03:01.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.05:03:01.02$vck44/vb=1,4 2006.201.05:03:01.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.05:03:01.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.05:03:01.02#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:01.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:03:01.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:03:01.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:03:01.02#ibcon#enter wrdev, iclass 26, count 2 2006.201.05:03:01.02#ibcon#first serial, iclass 26, count 2 2006.201.05:03:01.02#ibcon#enter sib2, iclass 26, count 2 2006.201.05:03:01.02#ibcon#flushed, iclass 26, count 2 2006.201.05:03:01.02#ibcon#about to write, iclass 26, count 2 2006.201.05:03:01.02#ibcon#wrote, iclass 26, count 2 2006.201.05:03:01.02#ibcon#about to read 3, iclass 26, count 2 2006.201.05:03:01.04#ibcon#read 3, iclass 26, count 2 2006.201.05:03:01.04#ibcon#about to read 4, iclass 26, count 2 2006.201.05:03:01.04#ibcon#read 4, iclass 26, count 2 2006.201.05:03:01.04#ibcon#about to read 5, iclass 26, count 2 2006.201.05:03:01.04#ibcon#read 5, iclass 26, count 2 2006.201.05:03:01.04#ibcon#about to read 6, iclass 26, count 2 2006.201.05:03:01.04#ibcon#read 6, iclass 26, count 2 2006.201.05:03:01.04#ibcon#end of sib2, iclass 26, count 2 2006.201.05:03:01.04#ibcon#*mode == 0, iclass 26, count 2 2006.201.05:03:01.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.05:03:01.04#ibcon#[27=AT01-04\r\n] 2006.201.05:03:01.04#ibcon#*before write, iclass 26, count 2 2006.201.05:03:01.04#ibcon#enter sib2, iclass 26, count 2 2006.201.05:03:01.04#ibcon#flushed, iclass 26, count 2 2006.201.05:03:01.04#ibcon#about to write, iclass 26, count 2 2006.201.05:03:01.04#ibcon#wrote, iclass 26, count 2 2006.201.05:03:01.04#ibcon#about to read 3, iclass 26, count 2 2006.201.05:03:01.07#ibcon#read 3, iclass 26, count 2 2006.201.05:03:01.07#ibcon#about to read 4, iclass 26, count 2 2006.201.05:03:01.07#ibcon#read 4, iclass 26, count 2 2006.201.05:03:01.07#ibcon#about to read 5, iclass 26, count 2 2006.201.05:03:01.07#ibcon#read 5, iclass 26, count 2 2006.201.05:03:01.07#ibcon#about to read 6, iclass 26, count 2 2006.201.05:03:01.07#ibcon#read 6, iclass 26, count 2 2006.201.05:03:01.07#ibcon#end of sib2, iclass 26, count 2 2006.201.05:03:01.07#ibcon#*after write, iclass 26, count 2 2006.201.05:03:01.07#ibcon#*before return 0, iclass 26, count 2 2006.201.05:03:01.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:03:01.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:03:01.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.05:03:01.07#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:01.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:03:01.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:03:01.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:03:01.19#ibcon#enter wrdev, iclass 26, count 0 2006.201.05:03:01.19#ibcon#first serial, iclass 26, count 0 2006.201.05:03:01.19#ibcon#enter sib2, iclass 26, count 0 2006.201.05:03:01.19#ibcon#flushed, iclass 26, count 0 2006.201.05:03:01.19#ibcon#about to write, iclass 26, count 0 2006.201.05:03:01.19#ibcon#wrote, iclass 26, count 0 2006.201.05:03:01.19#ibcon#about to read 3, iclass 26, count 0 2006.201.05:03:01.21#ibcon#read 3, iclass 26, count 0 2006.201.05:03:01.21#ibcon#about to read 4, iclass 26, count 0 2006.201.05:03:01.21#ibcon#read 4, iclass 26, count 0 2006.201.05:03:01.21#ibcon#about to read 5, iclass 26, count 0 2006.201.05:03:01.21#ibcon#read 5, iclass 26, count 0 2006.201.05:03:01.21#ibcon#about to read 6, iclass 26, count 0 2006.201.05:03:01.21#ibcon#read 6, iclass 26, count 0 2006.201.05:03:01.21#ibcon#end of sib2, iclass 26, count 0 2006.201.05:03:01.21#ibcon#*mode == 0, iclass 26, count 0 2006.201.05:03:01.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.05:03:01.21#ibcon#[27=USB\r\n] 2006.201.05:03:01.21#ibcon#*before write, iclass 26, count 0 2006.201.05:03:01.21#ibcon#enter sib2, iclass 26, count 0 2006.201.05:03:01.21#ibcon#flushed, iclass 26, count 0 2006.201.05:03:01.21#ibcon#about to write, iclass 26, count 0 2006.201.05:03:01.21#ibcon#wrote, iclass 26, count 0 2006.201.05:03:01.21#ibcon#about to read 3, iclass 26, count 0 2006.201.05:03:01.24#ibcon#read 3, iclass 26, count 0 2006.201.05:03:01.24#ibcon#about to read 4, iclass 26, count 0 2006.201.05:03:01.24#ibcon#read 4, iclass 26, count 0 2006.201.05:03:01.24#ibcon#about to read 5, iclass 26, count 0 2006.201.05:03:01.24#ibcon#read 5, iclass 26, count 0 2006.201.05:03:01.24#ibcon#about to read 6, iclass 26, count 0 2006.201.05:03:01.24#ibcon#read 6, iclass 26, count 0 2006.201.05:03:01.24#ibcon#end of sib2, iclass 26, count 0 2006.201.05:03:01.24#ibcon#*after write, iclass 26, count 0 2006.201.05:03:01.24#ibcon#*before return 0, iclass 26, count 0 2006.201.05:03:01.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:03:01.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:03:01.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.05:03:01.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.05:03:01.24$vck44/vblo=2,634.99 2006.201.05:03:01.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.05:03:01.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.05:03:01.24#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:01.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:03:01.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:03:01.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:03:01.24#ibcon#enter wrdev, iclass 28, count 0 2006.201.05:03:01.24#ibcon#first serial, iclass 28, count 0 2006.201.05:03:01.24#ibcon#enter sib2, iclass 28, count 0 2006.201.05:03:01.24#ibcon#flushed, iclass 28, count 0 2006.201.05:03:01.24#ibcon#about to write, iclass 28, count 0 2006.201.05:03:01.24#ibcon#wrote, iclass 28, count 0 2006.201.05:03:01.24#ibcon#about to read 3, iclass 28, count 0 2006.201.05:03:01.26#ibcon#read 3, iclass 28, count 0 2006.201.05:03:01.26#ibcon#about to read 4, iclass 28, count 0 2006.201.05:03:01.26#ibcon#read 4, iclass 28, count 0 2006.201.05:03:01.26#ibcon#about to read 5, iclass 28, count 0 2006.201.05:03:01.26#ibcon#read 5, iclass 28, count 0 2006.201.05:03:01.26#ibcon#about to read 6, iclass 28, count 0 2006.201.05:03:01.26#ibcon#read 6, iclass 28, count 0 2006.201.05:03:01.26#ibcon#end of sib2, iclass 28, count 0 2006.201.05:03:01.26#ibcon#*mode == 0, iclass 28, count 0 2006.201.05:03:01.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.05:03:01.26#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:03:01.26#ibcon#*before write, iclass 28, count 0 2006.201.05:03:01.26#ibcon#enter sib2, iclass 28, count 0 2006.201.05:03:01.26#ibcon#flushed, iclass 28, count 0 2006.201.05:03:01.26#ibcon#about to write, iclass 28, count 0 2006.201.05:03:01.26#ibcon#wrote, iclass 28, count 0 2006.201.05:03:01.26#ibcon#about to read 3, iclass 28, count 0 2006.201.05:03:01.30#ibcon#read 3, iclass 28, count 0 2006.201.05:03:01.30#ibcon#about to read 4, iclass 28, count 0 2006.201.05:03:01.30#ibcon#read 4, iclass 28, count 0 2006.201.05:03:01.30#ibcon#about to read 5, iclass 28, count 0 2006.201.05:03:01.30#ibcon#read 5, iclass 28, count 0 2006.201.05:03:01.30#ibcon#about to read 6, iclass 28, count 0 2006.201.05:03:01.30#ibcon#read 6, iclass 28, count 0 2006.201.05:03:01.30#ibcon#end of sib2, iclass 28, count 0 2006.201.05:03:01.30#ibcon#*after write, iclass 28, count 0 2006.201.05:03:01.30#ibcon#*before return 0, iclass 28, count 0 2006.201.05:03:01.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:03:01.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:03:01.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.05:03:01.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.05:03:01.30$vck44/vb=2,5 2006.201.05:03:01.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.05:03:01.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.05:03:01.30#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:01.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:03:01.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:03:01.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:03:01.36#ibcon#enter wrdev, iclass 30, count 2 2006.201.05:03:01.36#ibcon#first serial, iclass 30, count 2 2006.201.05:03:01.36#ibcon#enter sib2, iclass 30, count 2 2006.201.05:03:01.36#ibcon#flushed, iclass 30, count 2 2006.201.05:03:01.36#ibcon#about to write, iclass 30, count 2 2006.201.05:03:01.36#ibcon#wrote, iclass 30, count 2 2006.201.05:03:01.36#ibcon#about to read 3, iclass 30, count 2 2006.201.05:03:01.38#ibcon#read 3, iclass 30, count 2 2006.201.05:03:01.38#ibcon#about to read 4, iclass 30, count 2 2006.201.05:03:01.38#ibcon#read 4, iclass 30, count 2 2006.201.05:03:01.38#ibcon#about to read 5, iclass 30, count 2 2006.201.05:03:01.38#ibcon#read 5, iclass 30, count 2 2006.201.05:03:01.38#ibcon#about to read 6, iclass 30, count 2 2006.201.05:03:01.38#ibcon#read 6, iclass 30, count 2 2006.201.05:03:01.38#ibcon#end of sib2, iclass 30, count 2 2006.201.05:03:01.38#ibcon#*mode == 0, iclass 30, count 2 2006.201.05:03:01.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.05:03:01.38#ibcon#[27=AT02-05\r\n] 2006.201.05:03:01.38#ibcon#*before write, iclass 30, count 2 2006.201.05:03:01.38#ibcon#enter sib2, iclass 30, count 2 2006.201.05:03:01.38#ibcon#flushed, iclass 30, count 2 2006.201.05:03:01.38#ibcon#about to write, iclass 30, count 2 2006.201.05:03:01.38#ibcon#wrote, iclass 30, count 2 2006.201.05:03:01.38#ibcon#about to read 3, iclass 30, count 2 2006.201.05:03:01.41#ibcon#read 3, iclass 30, count 2 2006.201.05:03:01.51#ibcon#about to read 4, iclass 30, count 2 2006.201.05:03:01.51#ibcon#read 4, iclass 30, count 2 2006.201.05:03:01.51#ibcon#about to read 5, iclass 30, count 2 2006.201.05:03:01.52#ibcon#read 5, iclass 30, count 2 2006.201.05:03:01.52#ibcon#about to read 6, iclass 30, count 2 2006.201.05:03:01.52#ibcon#read 6, iclass 30, count 2 2006.201.05:03:01.52#ibcon#end of sib2, iclass 30, count 2 2006.201.05:03:01.52#ibcon#*after write, iclass 30, count 2 2006.201.05:03:01.52#ibcon#*before return 0, iclass 30, count 2 2006.201.05:03:01.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:03:01.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:03:01.52#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.05:03:01.52#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:01.52#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:03:01.64#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:03:01.64#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:03:01.64#ibcon#enter wrdev, iclass 30, count 0 2006.201.05:03:01.64#ibcon#first serial, iclass 30, count 0 2006.201.05:03:01.64#ibcon#enter sib2, iclass 30, count 0 2006.201.05:03:01.64#ibcon#flushed, iclass 30, count 0 2006.201.05:03:01.64#ibcon#about to write, iclass 30, count 0 2006.201.05:03:01.64#ibcon#wrote, iclass 30, count 0 2006.201.05:03:01.64#ibcon#about to read 3, iclass 30, count 0 2006.201.05:03:01.66#ibcon#read 3, iclass 30, count 0 2006.201.05:03:01.66#ibcon#about to read 4, iclass 30, count 0 2006.201.05:03:01.66#ibcon#read 4, iclass 30, count 0 2006.201.05:03:01.66#ibcon#about to read 5, iclass 30, count 0 2006.201.05:03:01.66#ibcon#read 5, iclass 30, count 0 2006.201.05:03:01.66#ibcon#about to read 6, iclass 30, count 0 2006.201.05:03:01.66#ibcon#read 6, iclass 30, count 0 2006.201.05:03:01.66#ibcon#end of sib2, iclass 30, count 0 2006.201.05:03:01.66#ibcon#*mode == 0, iclass 30, count 0 2006.201.05:03:01.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.05:03:01.66#ibcon#[27=USB\r\n] 2006.201.05:03:01.66#ibcon#*before write, iclass 30, count 0 2006.201.05:03:01.66#ibcon#enter sib2, iclass 30, count 0 2006.201.05:03:01.66#ibcon#flushed, iclass 30, count 0 2006.201.05:03:01.66#ibcon#about to write, iclass 30, count 0 2006.201.05:03:01.66#ibcon#wrote, iclass 30, count 0 2006.201.05:03:01.66#ibcon#about to read 3, iclass 30, count 0 2006.201.05:03:01.69#ibcon#read 3, iclass 30, count 0 2006.201.05:03:01.69#ibcon#about to read 4, iclass 30, count 0 2006.201.05:03:01.69#ibcon#read 4, iclass 30, count 0 2006.201.05:03:01.69#ibcon#about to read 5, iclass 30, count 0 2006.201.05:03:01.69#ibcon#read 5, iclass 30, count 0 2006.201.05:03:01.69#ibcon#about to read 6, iclass 30, count 0 2006.201.05:03:01.69#ibcon#read 6, iclass 30, count 0 2006.201.05:03:01.69#ibcon#end of sib2, iclass 30, count 0 2006.201.05:03:01.69#ibcon#*after write, iclass 30, count 0 2006.201.05:03:01.69#ibcon#*before return 0, iclass 30, count 0 2006.201.05:03:01.69#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:03:01.69#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:03:01.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.05:03:01.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.05:03:01.69$vck44/vblo=3,649.99 2006.201.05:03:01.69#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.05:03:01.69#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.05:03:01.69#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:01.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:03:01.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:03:01.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:03:01.69#ibcon#enter wrdev, iclass 32, count 0 2006.201.05:03:01.69#ibcon#first serial, iclass 32, count 0 2006.201.05:03:01.69#ibcon#enter sib2, iclass 32, count 0 2006.201.05:03:01.69#ibcon#flushed, iclass 32, count 0 2006.201.05:03:01.69#ibcon#about to write, iclass 32, count 0 2006.201.05:03:01.69#ibcon#wrote, iclass 32, count 0 2006.201.05:03:01.69#ibcon#about to read 3, iclass 32, count 0 2006.201.05:03:01.71#ibcon#read 3, iclass 32, count 0 2006.201.05:03:01.71#ibcon#about to read 4, iclass 32, count 0 2006.201.05:03:01.71#ibcon#read 4, iclass 32, count 0 2006.201.05:03:01.71#ibcon#about to read 5, iclass 32, count 0 2006.201.05:03:01.71#ibcon#read 5, iclass 32, count 0 2006.201.05:03:01.71#ibcon#about to read 6, iclass 32, count 0 2006.201.05:03:01.71#ibcon#read 6, iclass 32, count 0 2006.201.05:03:01.71#ibcon#end of sib2, iclass 32, count 0 2006.201.05:03:01.71#ibcon#*mode == 0, iclass 32, count 0 2006.201.05:03:01.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.05:03:01.71#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:03:01.71#ibcon#*before write, iclass 32, count 0 2006.201.05:03:01.71#ibcon#enter sib2, iclass 32, count 0 2006.201.05:03:01.71#ibcon#flushed, iclass 32, count 0 2006.201.05:03:01.71#ibcon#about to write, iclass 32, count 0 2006.201.05:03:01.71#ibcon#wrote, iclass 32, count 0 2006.201.05:03:01.71#ibcon#about to read 3, iclass 32, count 0 2006.201.05:03:01.75#ibcon#read 3, iclass 32, count 0 2006.201.05:03:01.75#ibcon#about to read 4, iclass 32, count 0 2006.201.05:03:01.75#ibcon#read 4, iclass 32, count 0 2006.201.05:03:01.75#ibcon#about to read 5, iclass 32, count 0 2006.201.05:03:01.75#ibcon#read 5, iclass 32, count 0 2006.201.05:03:01.75#ibcon#about to read 6, iclass 32, count 0 2006.201.05:03:01.75#ibcon#read 6, iclass 32, count 0 2006.201.05:03:01.75#ibcon#end of sib2, iclass 32, count 0 2006.201.05:03:01.75#ibcon#*after write, iclass 32, count 0 2006.201.05:03:01.75#ibcon#*before return 0, iclass 32, count 0 2006.201.05:03:01.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:03:01.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:03:01.75#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.05:03:01.75#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.05:03:01.75$vck44/vb=3,4 2006.201.05:03:01.75#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.05:03:01.75#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.05:03:01.75#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:01.75#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:03:01.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:03:01.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:03:01.81#ibcon#enter wrdev, iclass 34, count 2 2006.201.05:03:01.81#ibcon#first serial, iclass 34, count 2 2006.201.05:03:01.81#ibcon#enter sib2, iclass 34, count 2 2006.201.05:03:01.81#ibcon#flushed, iclass 34, count 2 2006.201.05:03:01.81#ibcon#about to write, iclass 34, count 2 2006.201.05:03:01.81#ibcon#wrote, iclass 34, count 2 2006.201.05:03:01.81#ibcon#about to read 3, iclass 34, count 2 2006.201.05:03:01.83#ibcon#read 3, iclass 34, count 2 2006.201.05:03:01.83#ibcon#about to read 4, iclass 34, count 2 2006.201.05:03:01.83#ibcon#read 4, iclass 34, count 2 2006.201.05:03:01.83#ibcon#about to read 5, iclass 34, count 2 2006.201.05:03:01.83#ibcon#read 5, iclass 34, count 2 2006.201.05:03:01.83#ibcon#about to read 6, iclass 34, count 2 2006.201.05:03:01.83#ibcon#read 6, iclass 34, count 2 2006.201.05:03:01.83#ibcon#end of sib2, iclass 34, count 2 2006.201.05:03:01.83#ibcon#*mode == 0, iclass 34, count 2 2006.201.05:03:01.83#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.05:03:01.83#ibcon#[27=AT03-04\r\n] 2006.201.05:03:01.83#ibcon#*before write, iclass 34, count 2 2006.201.05:03:01.83#ibcon#enter sib2, iclass 34, count 2 2006.201.05:03:01.83#ibcon#flushed, iclass 34, count 2 2006.201.05:03:01.83#ibcon#about to write, iclass 34, count 2 2006.201.05:03:01.83#ibcon#wrote, iclass 34, count 2 2006.201.05:03:01.83#ibcon#about to read 3, iclass 34, count 2 2006.201.05:03:01.86#ibcon#read 3, iclass 34, count 2 2006.201.05:03:01.86#ibcon#about to read 4, iclass 34, count 2 2006.201.05:03:01.86#ibcon#read 4, iclass 34, count 2 2006.201.05:03:01.86#ibcon#about to read 5, iclass 34, count 2 2006.201.05:03:01.86#ibcon#read 5, iclass 34, count 2 2006.201.05:03:01.86#ibcon#about to read 6, iclass 34, count 2 2006.201.05:03:01.86#ibcon#read 6, iclass 34, count 2 2006.201.05:03:01.86#ibcon#end of sib2, iclass 34, count 2 2006.201.05:03:01.86#ibcon#*after write, iclass 34, count 2 2006.201.05:03:01.86#ibcon#*before return 0, iclass 34, count 2 2006.201.05:03:01.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:03:01.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:03:01.86#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.05:03:01.86#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:01.86#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:03:01.98#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:03:01.98#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:03:01.98#ibcon#enter wrdev, iclass 34, count 0 2006.201.05:03:01.98#ibcon#first serial, iclass 34, count 0 2006.201.05:03:01.98#ibcon#enter sib2, iclass 34, count 0 2006.201.05:03:01.98#ibcon#flushed, iclass 34, count 0 2006.201.05:03:01.98#ibcon#about to write, iclass 34, count 0 2006.201.05:03:01.98#ibcon#wrote, iclass 34, count 0 2006.201.05:03:01.98#ibcon#about to read 3, iclass 34, count 0 2006.201.05:03:02.00#ibcon#read 3, iclass 34, count 0 2006.201.05:03:02.00#ibcon#about to read 4, iclass 34, count 0 2006.201.05:03:02.00#ibcon#read 4, iclass 34, count 0 2006.201.05:03:02.00#ibcon#about to read 5, iclass 34, count 0 2006.201.05:03:02.00#ibcon#read 5, iclass 34, count 0 2006.201.05:03:02.00#ibcon#about to read 6, iclass 34, count 0 2006.201.05:03:02.00#ibcon#read 6, iclass 34, count 0 2006.201.05:03:02.00#ibcon#end of sib2, iclass 34, count 0 2006.201.05:03:02.00#ibcon#*mode == 0, iclass 34, count 0 2006.201.05:03:02.00#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.05:03:02.00#ibcon#[27=USB\r\n] 2006.201.05:03:02.00#ibcon#*before write, iclass 34, count 0 2006.201.05:03:02.00#ibcon#enter sib2, iclass 34, count 0 2006.201.05:03:02.00#ibcon#flushed, iclass 34, count 0 2006.201.05:03:02.00#ibcon#about to write, iclass 34, count 0 2006.201.05:03:02.00#ibcon#wrote, iclass 34, count 0 2006.201.05:03:02.00#ibcon#about to read 3, iclass 34, count 0 2006.201.05:03:02.03#ibcon#read 3, iclass 34, count 0 2006.201.05:03:02.03#ibcon#about to read 4, iclass 34, count 0 2006.201.05:03:02.03#ibcon#read 4, iclass 34, count 0 2006.201.05:03:02.03#ibcon#about to read 5, iclass 34, count 0 2006.201.05:03:02.03#ibcon#read 5, iclass 34, count 0 2006.201.05:03:02.03#ibcon#about to read 6, iclass 34, count 0 2006.201.05:03:02.03#ibcon#read 6, iclass 34, count 0 2006.201.05:03:02.03#ibcon#end of sib2, iclass 34, count 0 2006.201.05:03:02.03#ibcon#*after write, iclass 34, count 0 2006.201.05:03:02.03#ibcon#*before return 0, iclass 34, count 0 2006.201.05:03:02.03#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:03:02.03#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:03:02.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.05:03:02.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.05:03:02.03$vck44/vblo=4,679.99 2006.201.05:03:02.03#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.05:03:02.03#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.05:03:02.03#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:02.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:03:02.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:03:02.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:03:02.03#ibcon#enter wrdev, iclass 36, count 0 2006.201.05:03:02.03#ibcon#first serial, iclass 36, count 0 2006.201.05:03:02.03#ibcon#enter sib2, iclass 36, count 0 2006.201.05:03:02.03#ibcon#flushed, iclass 36, count 0 2006.201.05:03:02.03#ibcon#about to write, iclass 36, count 0 2006.201.05:03:02.03#ibcon#wrote, iclass 36, count 0 2006.201.05:03:02.03#ibcon#about to read 3, iclass 36, count 0 2006.201.05:03:02.05#ibcon#read 3, iclass 36, count 0 2006.201.05:03:02.05#ibcon#about to read 4, iclass 36, count 0 2006.201.05:03:02.05#ibcon#read 4, iclass 36, count 0 2006.201.05:03:02.05#ibcon#about to read 5, iclass 36, count 0 2006.201.05:03:02.05#ibcon#read 5, iclass 36, count 0 2006.201.05:03:02.05#ibcon#about to read 6, iclass 36, count 0 2006.201.05:03:02.05#ibcon#read 6, iclass 36, count 0 2006.201.05:03:02.05#ibcon#end of sib2, iclass 36, count 0 2006.201.05:03:02.05#ibcon#*mode == 0, iclass 36, count 0 2006.201.05:03:02.05#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.05:03:02.05#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:03:02.05#ibcon#*before write, iclass 36, count 0 2006.201.05:03:02.05#ibcon#enter sib2, iclass 36, count 0 2006.201.05:03:02.05#ibcon#flushed, iclass 36, count 0 2006.201.05:03:02.05#ibcon#about to write, iclass 36, count 0 2006.201.05:03:02.05#ibcon#wrote, iclass 36, count 0 2006.201.05:03:02.05#ibcon#about to read 3, iclass 36, count 0 2006.201.05:03:02.09#ibcon#read 3, iclass 36, count 0 2006.201.05:03:02.09#ibcon#about to read 4, iclass 36, count 0 2006.201.05:03:02.09#ibcon#read 4, iclass 36, count 0 2006.201.05:03:02.09#ibcon#about to read 5, iclass 36, count 0 2006.201.05:03:02.09#ibcon#read 5, iclass 36, count 0 2006.201.05:03:02.09#ibcon#about to read 6, iclass 36, count 0 2006.201.05:03:02.09#ibcon#read 6, iclass 36, count 0 2006.201.05:03:02.09#ibcon#end of sib2, iclass 36, count 0 2006.201.05:03:02.09#ibcon#*after write, iclass 36, count 0 2006.201.05:03:02.09#ibcon#*before return 0, iclass 36, count 0 2006.201.05:03:02.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:03:02.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:03:02.09#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.05:03:02.09#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.05:03:02.09$vck44/vb=4,5 2006.201.05:03:02.09#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.05:03:02.09#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.05:03:02.09#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:02.09#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:03:02.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:03:02.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:03:02.15#ibcon#enter wrdev, iclass 38, count 2 2006.201.05:03:02.15#ibcon#first serial, iclass 38, count 2 2006.201.05:03:02.15#ibcon#enter sib2, iclass 38, count 2 2006.201.05:03:02.15#ibcon#flushed, iclass 38, count 2 2006.201.05:03:02.15#ibcon#about to write, iclass 38, count 2 2006.201.05:03:02.15#ibcon#wrote, iclass 38, count 2 2006.201.05:03:02.15#ibcon#about to read 3, iclass 38, count 2 2006.201.05:03:02.17#ibcon#read 3, iclass 38, count 2 2006.201.05:03:02.17#ibcon#about to read 4, iclass 38, count 2 2006.201.05:03:02.17#ibcon#read 4, iclass 38, count 2 2006.201.05:03:02.17#ibcon#about to read 5, iclass 38, count 2 2006.201.05:03:02.17#ibcon#read 5, iclass 38, count 2 2006.201.05:03:02.17#ibcon#about to read 6, iclass 38, count 2 2006.201.05:03:02.17#ibcon#read 6, iclass 38, count 2 2006.201.05:03:02.17#ibcon#end of sib2, iclass 38, count 2 2006.201.05:03:02.17#ibcon#*mode == 0, iclass 38, count 2 2006.201.05:03:02.17#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.05:03:02.17#ibcon#[27=AT04-05\r\n] 2006.201.05:03:02.17#ibcon#*before write, iclass 38, count 2 2006.201.05:03:02.17#ibcon#enter sib2, iclass 38, count 2 2006.201.05:03:02.17#ibcon#flushed, iclass 38, count 2 2006.201.05:03:02.17#ibcon#about to write, iclass 38, count 2 2006.201.05:03:02.17#ibcon#wrote, iclass 38, count 2 2006.201.05:03:02.17#ibcon#about to read 3, iclass 38, count 2 2006.201.05:03:02.20#ibcon#read 3, iclass 38, count 2 2006.201.05:03:02.20#ibcon#about to read 4, iclass 38, count 2 2006.201.05:03:02.20#ibcon#read 4, iclass 38, count 2 2006.201.05:03:02.20#ibcon#about to read 5, iclass 38, count 2 2006.201.05:03:02.20#ibcon#read 5, iclass 38, count 2 2006.201.05:03:02.20#ibcon#about to read 6, iclass 38, count 2 2006.201.05:03:02.20#ibcon#read 6, iclass 38, count 2 2006.201.05:03:02.20#ibcon#end of sib2, iclass 38, count 2 2006.201.05:03:02.20#ibcon#*after write, iclass 38, count 2 2006.201.05:03:02.20#ibcon#*before return 0, iclass 38, count 2 2006.201.05:03:02.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:03:02.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:03:02.20#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.05:03:02.20#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:02.20#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:03:02.32#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:03:02.32#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:03:02.32#ibcon#enter wrdev, iclass 38, count 0 2006.201.05:03:02.32#ibcon#first serial, iclass 38, count 0 2006.201.05:03:02.32#ibcon#enter sib2, iclass 38, count 0 2006.201.05:03:02.32#ibcon#flushed, iclass 38, count 0 2006.201.05:03:02.32#ibcon#about to write, iclass 38, count 0 2006.201.05:03:02.32#ibcon#wrote, iclass 38, count 0 2006.201.05:03:02.32#ibcon#about to read 3, iclass 38, count 0 2006.201.05:03:02.34#ibcon#read 3, iclass 38, count 0 2006.201.05:03:02.34#ibcon#about to read 4, iclass 38, count 0 2006.201.05:03:02.34#ibcon#read 4, iclass 38, count 0 2006.201.05:03:02.34#ibcon#about to read 5, iclass 38, count 0 2006.201.05:03:02.34#ibcon#read 5, iclass 38, count 0 2006.201.05:03:02.34#ibcon#about to read 6, iclass 38, count 0 2006.201.05:03:02.34#ibcon#read 6, iclass 38, count 0 2006.201.05:03:02.34#ibcon#end of sib2, iclass 38, count 0 2006.201.05:03:02.34#ibcon#*mode == 0, iclass 38, count 0 2006.201.05:03:02.34#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.05:03:02.34#ibcon#[27=USB\r\n] 2006.201.05:03:02.34#ibcon#*before write, iclass 38, count 0 2006.201.05:03:02.34#ibcon#enter sib2, iclass 38, count 0 2006.201.05:03:02.34#ibcon#flushed, iclass 38, count 0 2006.201.05:03:02.34#ibcon#about to write, iclass 38, count 0 2006.201.05:03:02.34#ibcon#wrote, iclass 38, count 0 2006.201.05:03:02.34#ibcon#about to read 3, iclass 38, count 0 2006.201.05:03:02.37#ibcon#read 3, iclass 38, count 0 2006.201.05:03:02.37#ibcon#about to read 4, iclass 38, count 0 2006.201.05:03:02.37#ibcon#read 4, iclass 38, count 0 2006.201.05:03:02.37#ibcon#about to read 5, iclass 38, count 0 2006.201.05:03:02.37#ibcon#read 5, iclass 38, count 0 2006.201.05:03:02.37#ibcon#about to read 6, iclass 38, count 0 2006.201.05:03:02.37#ibcon#read 6, iclass 38, count 0 2006.201.05:03:02.37#ibcon#end of sib2, iclass 38, count 0 2006.201.05:03:02.37#ibcon#*after write, iclass 38, count 0 2006.201.05:03:02.37#ibcon#*before return 0, iclass 38, count 0 2006.201.05:03:02.37#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:03:02.37#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:03:02.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.05:03:02.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.05:03:02.37$vck44/vblo=5,709.99 2006.201.05:03:02.37#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.05:03:02.37#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.05:03:02.37#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:02.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:03:02.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:03:02.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:03:02.37#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:03:02.37#ibcon#first serial, iclass 40, count 0 2006.201.05:03:02.37#ibcon#enter sib2, iclass 40, count 0 2006.201.05:03:02.37#ibcon#flushed, iclass 40, count 0 2006.201.05:03:02.37#ibcon#about to write, iclass 40, count 0 2006.201.05:03:02.37#ibcon#wrote, iclass 40, count 0 2006.201.05:03:02.37#ibcon#about to read 3, iclass 40, count 0 2006.201.05:03:02.39#ibcon#read 3, iclass 40, count 0 2006.201.05:03:02.39#ibcon#about to read 4, iclass 40, count 0 2006.201.05:03:02.39#ibcon#read 4, iclass 40, count 0 2006.201.05:03:02.39#ibcon#about to read 5, iclass 40, count 0 2006.201.05:03:02.39#ibcon#read 5, iclass 40, count 0 2006.201.05:03:02.39#ibcon#about to read 6, iclass 40, count 0 2006.201.05:03:02.39#ibcon#read 6, iclass 40, count 0 2006.201.05:03:02.39#ibcon#end of sib2, iclass 40, count 0 2006.201.05:03:02.39#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:03:02.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:03:02.39#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:03:02.39#ibcon#*before write, iclass 40, count 0 2006.201.05:03:02.39#ibcon#enter sib2, iclass 40, count 0 2006.201.05:03:02.39#ibcon#flushed, iclass 40, count 0 2006.201.05:03:02.39#ibcon#about to write, iclass 40, count 0 2006.201.05:03:02.39#ibcon#wrote, iclass 40, count 0 2006.201.05:03:02.39#ibcon#about to read 3, iclass 40, count 0 2006.201.05:03:02.43#ibcon#read 3, iclass 40, count 0 2006.201.05:03:02.43#ibcon#about to read 4, iclass 40, count 0 2006.201.05:03:02.43#ibcon#read 4, iclass 40, count 0 2006.201.05:03:02.43#ibcon#about to read 5, iclass 40, count 0 2006.201.05:03:02.43#ibcon#read 5, iclass 40, count 0 2006.201.05:03:02.43#ibcon#about to read 6, iclass 40, count 0 2006.201.05:03:02.43#ibcon#read 6, iclass 40, count 0 2006.201.05:03:02.43#ibcon#end of sib2, iclass 40, count 0 2006.201.05:03:02.43#ibcon#*after write, iclass 40, count 0 2006.201.05:03:02.43#ibcon#*before return 0, iclass 40, count 0 2006.201.05:03:02.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:03:02.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:03:02.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:03:02.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:03:02.43$vck44/vb=5,4 2006.201.05:03:02.43#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.05:03:02.43#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.05:03:02.43#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:02.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:03:02.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:03:02.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:03:02.49#ibcon#enter wrdev, iclass 4, count 2 2006.201.05:03:02.49#ibcon#first serial, iclass 4, count 2 2006.201.05:03:02.49#ibcon#enter sib2, iclass 4, count 2 2006.201.05:03:02.49#ibcon#flushed, iclass 4, count 2 2006.201.05:03:02.49#ibcon#about to write, iclass 4, count 2 2006.201.05:03:02.49#ibcon#wrote, iclass 4, count 2 2006.201.05:03:02.49#ibcon#about to read 3, iclass 4, count 2 2006.201.05:03:02.51#ibcon#read 3, iclass 4, count 2 2006.201.05:03:02.51#ibcon#about to read 4, iclass 4, count 2 2006.201.05:03:02.51#ibcon#read 4, iclass 4, count 2 2006.201.05:03:02.51#ibcon#about to read 5, iclass 4, count 2 2006.201.05:03:02.51#ibcon#read 5, iclass 4, count 2 2006.201.05:03:02.51#ibcon#about to read 6, iclass 4, count 2 2006.201.05:03:02.51#ibcon#read 6, iclass 4, count 2 2006.201.05:03:02.51#ibcon#end of sib2, iclass 4, count 2 2006.201.05:03:02.51#ibcon#*mode == 0, iclass 4, count 2 2006.201.05:03:02.51#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.05:03:02.51#ibcon#[27=AT05-04\r\n] 2006.201.05:03:02.51#ibcon#*before write, iclass 4, count 2 2006.201.05:03:02.51#ibcon#enter sib2, iclass 4, count 2 2006.201.05:03:02.51#ibcon#flushed, iclass 4, count 2 2006.201.05:03:02.51#ibcon#about to write, iclass 4, count 2 2006.201.05:03:02.51#ibcon#wrote, iclass 4, count 2 2006.201.05:03:02.51#ibcon#about to read 3, iclass 4, count 2 2006.201.05:03:02.54#ibcon#read 3, iclass 4, count 2 2006.201.05:03:02.65#ibcon#about to read 4, iclass 4, count 2 2006.201.05:03:02.65#ibcon#read 4, iclass 4, count 2 2006.201.05:03:02.65#ibcon#about to read 5, iclass 4, count 2 2006.201.05:03:02.65#ibcon#read 5, iclass 4, count 2 2006.201.05:03:02.65#ibcon#about to read 6, iclass 4, count 2 2006.201.05:03:02.65#ibcon#read 6, iclass 4, count 2 2006.201.05:03:02.65#ibcon#end of sib2, iclass 4, count 2 2006.201.05:03:02.65#ibcon#*after write, iclass 4, count 2 2006.201.05:03:02.65#ibcon#*before return 0, iclass 4, count 2 2006.201.05:03:02.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:03:02.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:03:02.65#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.05:03:02.65#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:02.65#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:03:02.77#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:03:02.77#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:03:02.77#ibcon#enter wrdev, iclass 4, count 0 2006.201.05:03:02.77#ibcon#first serial, iclass 4, count 0 2006.201.05:03:02.77#ibcon#enter sib2, iclass 4, count 0 2006.201.05:03:02.77#ibcon#flushed, iclass 4, count 0 2006.201.05:03:02.77#ibcon#about to write, iclass 4, count 0 2006.201.05:03:02.77#ibcon#wrote, iclass 4, count 0 2006.201.05:03:02.77#ibcon#about to read 3, iclass 4, count 0 2006.201.05:03:02.79#ibcon#read 3, iclass 4, count 0 2006.201.05:03:02.79#ibcon#about to read 4, iclass 4, count 0 2006.201.05:03:02.79#ibcon#read 4, iclass 4, count 0 2006.201.05:03:02.79#ibcon#about to read 5, iclass 4, count 0 2006.201.05:03:02.79#ibcon#read 5, iclass 4, count 0 2006.201.05:03:02.79#ibcon#about to read 6, iclass 4, count 0 2006.201.05:03:02.79#ibcon#read 6, iclass 4, count 0 2006.201.05:03:02.79#ibcon#end of sib2, iclass 4, count 0 2006.201.05:03:02.79#ibcon#*mode == 0, iclass 4, count 0 2006.201.05:03:02.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.05:03:02.79#ibcon#[27=USB\r\n] 2006.201.05:03:02.79#ibcon#*before write, iclass 4, count 0 2006.201.05:03:02.79#ibcon#enter sib2, iclass 4, count 0 2006.201.05:03:02.79#ibcon#flushed, iclass 4, count 0 2006.201.05:03:02.79#ibcon#about to write, iclass 4, count 0 2006.201.05:03:02.79#ibcon#wrote, iclass 4, count 0 2006.201.05:03:02.79#ibcon#about to read 3, iclass 4, count 0 2006.201.05:03:02.82#ibcon#read 3, iclass 4, count 0 2006.201.05:03:02.82#ibcon#about to read 4, iclass 4, count 0 2006.201.05:03:02.82#ibcon#read 4, iclass 4, count 0 2006.201.05:03:02.82#ibcon#about to read 5, iclass 4, count 0 2006.201.05:03:02.82#ibcon#read 5, iclass 4, count 0 2006.201.05:03:02.82#ibcon#about to read 6, iclass 4, count 0 2006.201.05:03:02.82#ibcon#read 6, iclass 4, count 0 2006.201.05:03:02.82#ibcon#end of sib2, iclass 4, count 0 2006.201.05:03:02.82#ibcon#*after write, iclass 4, count 0 2006.201.05:03:02.82#ibcon#*before return 0, iclass 4, count 0 2006.201.05:03:02.82#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:03:02.82#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:03:02.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.05:03:02.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.05:03:02.82$vck44/vblo=6,719.99 2006.201.05:03:02.82#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.05:03:02.82#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.05:03:02.82#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:02.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:03:02.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:03:02.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:03:02.82#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:03:02.82#ibcon#first serial, iclass 6, count 0 2006.201.05:03:02.82#ibcon#enter sib2, iclass 6, count 0 2006.201.05:03:02.82#ibcon#flushed, iclass 6, count 0 2006.201.05:03:02.82#ibcon#about to write, iclass 6, count 0 2006.201.05:03:02.82#ibcon#wrote, iclass 6, count 0 2006.201.05:03:02.82#ibcon#about to read 3, iclass 6, count 0 2006.201.05:03:02.84#ibcon#read 3, iclass 6, count 0 2006.201.05:03:02.84#ibcon#about to read 4, iclass 6, count 0 2006.201.05:03:02.84#ibcon#read 4, iclass 6, count 0 2006.201.05:03:02.84#ibcon#about to read 5, iclass 6, count 0 2006.201.05:03:02.84#ibcon#read 5, iclass 6, count 0 2006.201.05:03:02.84#ibcon#about to read 6, iclass 6, count 0 2006.201.05:03:02.84#ibcon#read 6, iclass 6, count 0 2006.201.05:03:02.84#ibcon#end of sib2, iclass 6, count 0 2006.201.05:03:02.84#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:03:02.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:03:02.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:03:02.84#ibcon#*before write, iclass 6, count 0 2006.201.05:03:02.84#ibcon#enter sib2, iclass 6, count 0 2006.201.05:03:02.84#ibcon#flushed, iclass 6, count 0 2006.201.05:03:02.84#ibcon#about to write, iclass 6, count 0 2006.201.05:03:02.84#ibcon#wrote, iclass 6, count 0 2006.201.05:03:02.84#ibcon#about to read 3, iclass 6, count 0 2006.201.05:03:02.88#ibcon#read 3, iclass 6, count 0 2006.201.05:03:02.88#ibcon#about to read 4, iclass 6, count 0 2006.201.05:03:02.88#ibcon#read 4, iclass 6, count 0 2006.201.05:03:02.88#ibcon#about to read 5, iclass 6, count 0 2006.201.05:03:02.88#ibcon#read 5, iclass 6, count 0 2006.201.05:03:02.88#ibcon#about to read 6, iclass 6, count 0 2006.201.05:03:02.88#ibcon#read 6, iclass 6, count 0 2006.201.05:03:02.88#ibcon#end of sib2, iclass 6, count 0 2006.201.05:03:02.88#ibcon#*after write, iclass 6, count 0 2006.201.05:03:02.88#ibcon#*before return 0, iclass 6, count 0 2006.201.05:03:02.88#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:03:02.88#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:03:02.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:03:02.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:03:02.88$vck44/vb=6,4 2006.201.05:03:02.88#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.05:03:02.88#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.05:03:02.88#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:02.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:02.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:02.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:02.94#ibcon#enter wrdev, iclass 10, count 2 2006.201.05:03:02.94#ibcon#first serial, iclass 10, count 2 2006.201.05:03:02.94#ibcon#enter sib2, iclass 10, count 2 2006.201.05:03:02.94#ibcon#flushed, iclass 10, count 2 2006.201.05:03:02.94#ibcon#about to write, iclass 10, count 2 2006.201.05:03:02.94#ibcon#wrote, iclass 10, count 2 2006.201.05:03:02.94#ibcon#about to read 3, iclass 10, count 2 2006.201.05:03:02.96#ibcon#read 3, iclass 10, count 2 2006.201.05:03:02.96#ibcon#about to read 4, iclass 10, count 2 2006.201.05:03:02.96#ibcon#read 4, iclass 10, count 2 2006.201.05:03:02.96#ibcon#about to read 5, iclass 10, count 2 2006.201.05:03:02.96#ibcon#read 5, iclass 10, count 2 2006.201.05:03:02.96#ibcon#about to read 6, iclass 10, count 2 2006.201.05:03:02.96#ibcon#read 6, iclass 10, count 2 2006.201.05:03:02.96#ibcon#end of sib2, iclass 10, count 2 2006.201.05:03:02.96#ibcon#*mode == 0, iclass 10, count 2 2006.201.05:03:02.96#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.05:03:02.96#ibcon#[27=AT06-04\r\n] 2006.201.05:03:02.96#ibcon#*before write, iclass 10, count 2 2006.201.05:03:02.96#ibcon#enter sib2, iclass 10, count 2 2006.201.05:03:02.96#ibcon#flushed, iclass 10, count 2 2006.201.05:03:02.96#ibcon#about to write, iclass 10, count 2 2006.201.05:03:02.96#ibcon#wrote, iclass 10, count 2 2006.201.05:03:02.96#ibcon#about to read 3, iclass 10, count 2 2006.201.05:03:02.99#ibcon#read 3, iclass 10, count 2 2006.201.05:03:02.99#ibcon#about to read 4, iclass 10, count 2 2006.201.05:03:02.99#ibcon#read 4, iclass 10, count 2 2006.201.05:03:02.99#ibcon#about to read 5, iclass 10, count 2 2006.201.05:03:02.99#ibcon#read 5, iclass 10, count 2 2006.201.05:03:02.99#ibcon#about to read 6, iclass 10, count 2 2006.201.05:03:02.99#ibcon#read 6, iclass 10, count 2 2006.201.05:03:02.99#ibcon#end of sib2, iclass 10, count 2 2006.201.05:03:02.99#ibcon#*after write, iclass 10, count 2 2006.201.05:03:02.99#ibcon#*before return 0, iclass 10, count 2 2006.201.05:03:02.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:02.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:03:02.99#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.05:03:02.99#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:02.99#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:03.11#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:03.11#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:03.11#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:03:03.11#ibcon#first serial, iclass 10, count 0 2006.201.05:03:03.11#ibcon#enter sib2, iclass 10, count 0 2006.201.05:03:03.11#ibcon#flushed, iclass 10, count 0 2006.201.05:03:03.11#ibcon#about to write, iclass 10, count 0 2006.201.05:03:03.11#ibcon#wrote, iclass 10, count 0 2006.201.05:03:03.11#ibcon#about to read 3, iclass 10, count 0 2006.201.05:03:03.13#ibcon#read 3, iclass 10, count 0 2006.201.05:03:03.13#ibcon#about to read 4, iclass 10, count 0 2006.201.05:03:03.13#ibcon#read 4, iclass 10, count 0 2006.201.05:03:03.13#ibcon#about to read 5, iclass 10, count 0 2006.201.05:03:03.13#ibcon#read 5, iclass 10, count 0 2006.201.05:03:03.13#ibcon#about to read 6, iclass 10, count 0 2006.201.05:03:03.13#ibcon#read 6, iclass 10, count 0 2006.201.05:03:03.13#ibcon#end of sib2, iclass 10, count 0 2006.201.05:03:03.13#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:03:03.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:03:03.13#ibcon#[27=USB\r\n] 2006.201.05:03:03.13#ibcon#*before write, iclass 10, count 0 2006.201.05:03:03.13#ibcon#enter sib2, iclass 10, count 0 2006.201.05:03:03.13#ibcon#flushed, iclass 10, count 0 2006.201.05:03:03.13#ibcon#about to write, iclass 10, count 0 2006.201.05:03:03.13#ibcon#wrote, iclass 10, count 0 2006.201.05:03:03.13#ibcon#about to read 3, iclass 10, count 0 2006.201.05:03:03.16#ibcon#read 3, iclass 10, count 0 2006.201.05:03:03.16#ibcon#about to read 4, iclass 10, count 0 2006.201.05:03:03.16#ibcon#read 4, iclass 10, count 0 2006.201.05:03:03.16#ibcon#about to read 5, iclass 10, count 0 2006.201.05:03:03.16#ibcon#read 5, iclass 10, count 0 2006.201.05:03:03.16#ibcon#about to read 6, iclass 10, count 0 2006.201.05:03:03.16#ibcon#read 6, iclass 10, count 0 2006.201.05:03:03.16#ibcon#end of sib2, iclass 10, count 0 2006.201.05:03:03.16#ibcon#*after write, iclass 10, count 0 2006.201.05:03:03.16#ibcon#*before return 0, iclass 10, count 0 2006.201.05:03:03.16#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:03.16#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:03:03.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:03:03.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:03:03.16$vck44/vblo=7,734.99 2006.201.05:03:03.16#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.05:03:03.16#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.05:03:03.16#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:03.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:03:03.16#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:03:03.16#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:03:03.16#ibcon#enter wrdev, iclass 12, count 0 2006.201.05:03:03.16#ibcon#first serial, iclass 12, count 0 2006.201.05:03:03.16#ibcon#enter sib2, iclass 12, count 0 2006.201.05:03:03.16#ibcon#flushed, iclass 12, count 0 2006.201.05:03:03.16#ibcon#about to write, iclass 12, count 0 2006.201.05:03:03.16#ibcon#wrote, iclass 12, count 0 2006.201.05:03:03.16#ibcon#about to read 3, iclass 12, count 0 2006.201.05:03:03.18#ibcon#read 3, iclass 12, count 0 2006.201.05:03:03.18#ibcon#about to read 4, iclass 12, count 0 2006.201.05:03:03.18#ibcon#read 4, iclass 12, count 0 2006.201.05:03:03.18#ibcon#about to read 5, iclass 12, count 0 2006.201.05:03:03.18#ibcon#read 5, iclass 12, count 0 2006.201.05:03:03.18#ibcon#about to read 6, iclass 12, count 0 2006.201.05:03:03.18#ibcon#read 6, iclass 12, count 0 2006.201.05:03:03.18#ibcon#end of sib2, iclass 12, count 0 2006.201.05:03:03.18#ibcon#*mode == 0, iclass 12, count 0 2006.201.05:03:03.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.05:03:03.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:03:03.18#ibcon#*before write, iclass 12, count 0 2006.201.05:03:03.18#ibcon#enter sib2, iclass 12, count 0 2006.201.05:03:03.18#ibcon#flushed, iclass 12, count 0 2006.201.05:03:03.18#ibcon#about to write, iclass 12, count 0 2006.201.05:03:03.18#ibcon#wrote, iclass 12, count 0 2006.201.05:03:03.18#ibcon#about to read 3, iclass 12, count 0 2006.201.05:03:03.22#ibcon#read 3, iclass 12, count 0 2006.201.05:03:03.22#ibcon#about to read 4, iclass 12, count 0 2006.201.05:03:03.22#ibcon#read 4, iclass 12, count 0 2006.201.05:03:03.22#ibcon#about to read 5, iclass 12, count 0 2006.201.05:03:03.22#ibcon#read 5, iclass 12, count 0 2006.201.05:03:03.22#ibcon#about to read 6, iclass 12, count 0 2006.201.05:03:03.22#ibcon#read 6, iclass 12, count 0 2006.201.05:03:03.22#ibcon#end of sib2, iclass 12, count 0 2006.201.05:03:03.22#ibcon#*after write, iclass 12, count 0 2006.201.05:03:03.22#ibcon#*before return 0, iclass 12, count 0 2006.201.05:03:03.22#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:03:03.22#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:03:03.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.05:03:03.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.05:03:03.22$vck44/vb=7,4 2006.201.05:03:03.22#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.05:03:03.22#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.05:03:03.22#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:03.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:03:03.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:03:03.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:03:03.28#ibcon#enter wrdev, iclass 14, count 2 2006.201.05:03:03.28#ibcon#first serial, iclass 14, count 2 2006.201.05:03:03.28#ibcon#enter sib2, iclass 14, count 2 2006.201.05:03:03.28#ibcon#flushed, iclass 14, count 2 2006.201.05:03:03.28#ibcon#about to write, iclass 14, count 2 2006.201.05:03:03.28#ibcon#wrote, iclass 14, count 2 2006.201.05:03:03.28#ibcon#about to read 3, iclass 14, count 2 2006.201.05:03:03.30#ibcon#read 3, iclass 14, count 2 2006.201.05:03:03.30#ibcon#about to read 4, iclass 14, count 2 2006.201.05:03:03.30#ibcon#read 4, iclass 14, count 2 2006.201.05:03:03.30#ibcon#about to read 5, iclass 14, count 2 2006.201.05:03:03.30#ibcon#read 5, iclass 14, count 2 2006.201.05:03:03.30#ibcon#about to read 6, iclass 14, count 2 2006.201.05:03:03.30#ibcon#read 6, iclass 14, count 2 2006.201.05:03:03.30#ibcon#end of sib2, iclass 14, count 2 2006.201.05:03:03.30#ibcon#*mode == 0, iclass 14, count 2 2006.201.05:03:03.30#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.05:03:03.30#ibcon#[27=AT07-04\r\n] 2006.201.05:03:03.30#ibcon#*before write, iclass 14, count 2 2006.201.05:03:03.30#ibcon#enter sib2, iclass 14, count 2 2006.201.05:03:03.30#ibcon#flushed, iclass 14, count 2 2006.201.05:03:03.30#ibcon#about to write, iclass 14, count 2 2006.201.05:03:03.30#ibcon#wrote, iclass 14, count 2 2006.201.05:03:03.30#ibcon#about to read 3, iclass 14, count 2 2006.201.05:03:03.33#ibcon#read 3, iclass 14, count 2 2006.201.05:03:03.33#ibcon#about to read 4, iclass 14, count 2 2006.201.05:03:03.33#ibcon#read 4, iclass 14, count 2 2006.201.05:03:03.33#ibcon#about to read 5, iclass 14, count 2 2006.201.05:03:03.33#ibcon#read 5, iclass 14, count 2 2006.201.05:03:03.33#ibcon#about to read 6, iclass 14, count 2 2006.201.05:03:03.33#ibcon#read 6, iclass 14, count 2 2006.201.05:03:03.33#ibcon#end of sib2, iclass 14, count 2 2006.201.05:03:03.33#ibcon#*after write, iclass 14, count 2 2006.201.05:03:03.33#ibcon#*before return 0, iclass 14, count 2 2006.201.05:03:03.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:03:03.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:03:03.33#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.05:03:03.33#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:03.33#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:03:03.45#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:03:03.45#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:03:03.45#ibcon#enter wrdev, iclass 14, count 0 2006.201.05:03:03.45#ibcon#first serial, iclass 14, count 0 2006.201.05:03:03.45#ibcon#enter sib2, iclass 14, count 0 2006.201.05:03:03.45#ibcon#flushed, iclass 14, count 0 2006.201.05:03:03.45#ibcon#about to write, iclass 14, count 0 2006.201.05:03:03.45#ibcon#wrote, iclass 14, count 0 2006.201.05:03:03.45#ibcon#about to read 3, iclass 14, count 0 2006.201.05:03:03.47#ibcon#read 3, iclass 14, count 0 2006.201.05:03:03.47#ibcon#about to read 4, iclass 14, count 0 2006.201.05:03:03.47#ibcon#read 4, iclass 14, count 0 2006.201.05:03:03.47#ibcon#about to read 5, iclass 14, count 0 2006.201.05:03:03.47#ibcon#read 5, iclass 14, count 0 2006.201.05:03:03.47#ibcon#about to read 6, iclass 14, count 0 2006.201.05:03:03.47#ibcon#read 6, iclass 14, count 0 2006.201.05:03:03.47#ibcon#end of sib2, iclass 14, count 0 2006.201.05:03:03.47#ibcon#*mode == 0, iclass 14, count 0 2006.201.05:03:03.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.05:03:03.47#ibcon#[27=USB\r\n] 2006.201.05:03:03.47#ibcon#*before write, iclass 14, count 0 2006.201.05:03:03.47#ibcon#enter sib2, iclass 14, count 0 2006.201.05:03:03.47#ibcon#flushed, iclass 14, count 0 2006.201.05:03:03.47#ibcon#about to write, iclass 14, count 0 2006.201.05:03:03.47#ibcon#wrote, iclass 14, count 0 2006.201.05:03:03.47#ibcon#about to read 3, iclass 14, count 0 2006.201.05:03:03.50#ibcon#read 3, iclass 14, count 0 2006.201.05:03:03.50#ibcon#about to read 4, iclass 14, count 0 2006.201.05:03:03.50#ibcon#read 4, iclass 14, count 0 2006.201.05:03:03.50#ibcon#about to read 5, iclass 14, count 0 2006.201.05:03:03.50#ibcon#read 5, iclass 14, count 0 2006.201.05:03:03.50#ibcon#about to read 6, iclass 14, count 0 2006.201.05:03:03.50#ibcon#read 6, iclass 14, count 0 2006.201.05:03:03.50#ibcon#end of sib2, iclass 14, count 0 2006.201.05:03:03.50#ibcon#*after write, iclass 14, count 0 2006.201.05:03:03.50#ibcon#*before return 0, iclass 14, count 0 2006.201.05:03:03.50#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:03:03.50#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:03:03.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.05:03:03.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.05:03:03.50$vck44/vblo=8,744.99 2006.201.05:03:03.50#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.05:03:03.50#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.05:03:03.50#ibcon#ireg 17 cls_cnt 0 2006.201.05:03:03.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:03.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:03.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:03.50#ibcon#enter wrdev, iclass 16, count 0 2006.201.05:03:03.50#ibcon#first serial, iclass 16, count 0 2006.201.05:03:03.50#ibcon#enter sib2, iclass 16, count 0 2006.201.05:03:03.50#ibcon#flushed, iclass 16, count 0 2006.201.05:03:03.50#ibcon#about to write, iclass 16, count 0 2006.201.05:03:03.50#ibcon#wrote, iclass 16, count 0 2006.201.05:03:03.50#ibcon#about to read 3, iclass 16, count 0 2006.201.05:03:03.52#ibcon#read 3, iclass 16, count 0 2006.201.05:03:03.52#ibcon#about to read 4, iclass 16, count 0 2006.201.05:03:03.52#ibcon#read 4, iclass 16, count 0 2006.201.05:03:03.52#ibcon#about to read 5, iclass 16, count 0 2006.201.05:03:03.52#ibcon#read 5, iclass 16, count 0 2006.201.05:03:03.52#ibcon#about to read 6, iclass 16, count 0 2006.201.05:03:03.52#ibcon#read 6, iclass 16, count 0 2006.201.05:03:03.52#ibcon#end of sib2, iclass 16, count 0 2006.201.05:03:03.52#ibcon#*mode == 0, iclass 16, count 0 2006.201.05:03:03.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.05:03:03.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:03:03.52#ibcon#*before write, iclass 16, count 0 2006.201.05:03:03.52#ibcon#enter sib2, iclass 16, count 0 2006.201.05:03:03.52#ibcon#flushed, iclass 16, count 0 2006.201.05:03:03.52#ibcon#about to write, iclass 16, count 0 2006.201.05:03:03.52#ibcon#wrote, iclass 16, count 0 2006.201.05:03:03.52#ibcon#about to read 3, iclass 16, count 0 2006.201.05:03:03.56#ibcon#read 3, iclass 16, count 0 2006.201.05:03:03.56#ibcon#about to read 4, iclass 16, count 0 2006.201.05:03:03.56#ibcon#read 4, iclass 16, count 0 2006.201.05:03:03.56#ibcon#about to read 5, iclass 16, count 0 2006.201.05:03:03.56#ibcon#read 5, iclass 16, count 0 2006.201.05:03:03.56#ibcon#about to read 6, iclass 16, count 0 2006.201.05:03:03.56#ibcon#read 6, iclass 16, count 0 2006.201.05:03:03.56#ibcon#end of sib2, iclass 16, count 0 2006.201.05:03:03.56#ibcon#*after write, iclass 16, count 0 2006.201.05:03:03.56#ibcon#*before return 0, iclass 16, count 0 2006.201.05:03:03.56#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:03.56#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:03:03.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.05:03:03.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.05:03:03.56$vck44/vb=8,4 2006.201.05:03:03.56#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.05:03:03.56#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.05:03:03.56#ibcon#ireg 11 cls_cnt 2 2006.201.05:03:03.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:03.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:03.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:03.62#ibcon#enter wrdev, iclass 18, count 2 2006.201.05:03:03.62#ibcon#first serial, iclass 18, count 2 2006.201.05:03:03.62#ibcon#enter sib2, iclass 18, count 2 2006.201.05:03:03.62#ibcon#flushed, iclass 18, count 2 2006.201.05:03:03.62#ibcon#about to write, iclass 18, count 2 2006.201.05:03:03.62#ibcon#wrote, iclass 18, count 2 2006.201.05:03:03.62#ibcon#about to read 3, iclass 18, count 2 2006.201.05:03:03.64#ibcon#read 3, iclass 18, count 2 2006.201.05:03:03.64#ibcon#about to read 4, iclass 18, count 2 2006.201.05:03:03.64#ibcon#read 4, iclass 18, count 2 2006.201.05:03:03.64#ibcon#about to read 5, iclass 18, count 2 2006.201.05:03:03.64#ibcon#read 5, iclass 18, count 2 2006.201.05:03:03.64#ibcon#about to read 6, iclass 18, count 2 2006.201.05:03:03.64#ibcon#read 6, iclass 18, count 2 2006.201.05:03:03.64#ibcon#end of sib2, iclass 18, count 2 2006.201.05:03:03.64#ibcon#*mode == 0, iclass 18, count 2 2006.201.05:03:03.64#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.05:03:03.64#ibcon#[27=AT08-04\r\n] 2006.201.05:03:03.64#ibcon#*before write, iclass 18, count 2 2006.201.05:03:03.64#ibcon#enter sib2, iclass 18, count 2 2006.201.05:03:03.64#ibcon#flushed, iclass 18, count 2 2006.201.05:03:03.64#ibcon#about to write, iclass 18, count 2 2006.201.05:03:03.64#ibcon#wrote, iclass 18, count 2 2006.201.05:03:03.64#ibcon#about to read 3, iclass 18, count 2 2006.201.05:03:03.67#ibcon#read 3, iclass 18, count 2 2006.201.05:03:03.67#ibcon#about to read 4, iclass 18, count 2 2006.201.05:03:03.67#ibcon#read 4, iclass 18, count 2 2006.201.05:03:03.67#ibcon#about to read 5, iclass 18, count 2 2006.201.05:03:03.67#ibcon#read 5, iclass 18, count 2 2006.201.05:03:03.67#ibcon#about to read 6, iclass 18, count 2 2006.201.05:03:03.68#ibcon#read 6, iclass 18, count 2 2006.201.05:03:03.68#ibcon#end of sib2, iclass 18, count 2 2006.201.05:03:03.68#ibcon#*after write, iclass 18, count 2 2006.201.05:03:03.68#ibcon#*before return 0, iclass 18, count 2 2006.201.05:03:03.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:03.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:03:03.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.05:03:03.68#ibcon#ireg 7 cls_cnt 0 2006.201.05:03:03.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:03.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:03.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:03.80#ibcon#enter wrdev, iclass 18, count 0 2006.201.05:03:03.80#ibcon#first serial, iclass 18, count 0 2006.201.05:03:03.80#ibcon#enter sib2, iclass 18, count 0 2006.201.05:03:03.80#ibcon#flushed, iclass 18, count 0 2006.201.05:03:03.80#ibcon#about to write, iclass 18, count 0 2006.201.05:03:03.80#ibcon#wrote, iclass 18, count 0 2006.201.05:03:03.80#ibcon#about to read 3, iclass 18, count 0 2006.201.05:03:03.82#ibcon#read 3, iclass 18, count 0 2006.201.05:03:03.82#ibcon#about to read 4, iclass 18, count 0 2006.201.05:03:03.82#ibcon#read 4, iclass 18, count 0 2006.201.05:03:03.82#ibcon#about to read 5, iclass 18, count 0 2006.201.05:03:03.82#ibcon#read 5, iclass 18, count 0 2006.201.05:03:03.82#ibcon#about to read 6, iclass 18, count 0 2006.201.05:03:03.82#ibcon#read 6, iclass 18, count 0 2006.201.05:03:03.82#ibcon#end of sib2, iclass 18, count 0 2006.201.05:03:03.82#ibcon#*mode == 0, iclass 18, count 0 2006.201.05:03:03.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.05:03:03.82#ibcon#[27=USB\r\n] 2006.201.05:03:03.82#ibcon#*before write, iclass 18, count 0 2006.201.05:03:03.82#ibcon#enter sib2, iclass 18, count 0 2006.201.05:03:03.82#ibcon#flushed, iclass 18, count 0 2006.201.05:03:03.82#ibcon#about to write, iclass 18, count 0 2006.201.05:03:03.82#ibcon#wrote, iclass 18, count 0 2006.201.05:03:03.82#ibcon#about to read 3, iclass 18, count 0 2006.201.05:03:03.85#ibcon#read 3, iclass 18, count 0 2006.201.05:03:03.85#ibcon#about to read 4, iclass 18, count 0 2006.201.05:03:03.85#ibcon#read 4, iclass 18, count 0 2006.201.05:03:03.85#ibcon#about to read 5, iclass 18, count 0 2006.201.05:03:03.85#ibcon#read 5, iclass 18, count 0 2006.201.05:03:03.85#ibcon#about to read 6, iclass 18, count 0 2006.201.05:03:03.85#ibcon#read 6, iclass 18, count 0 2006.201.05:03:03.85#ibcon#end of sib2, iclass 18, count 0 2006.201.05:03:03.85#ibcon#*after write, iclass 18, count 0 2006.201.05:03:03.85#ibcon#*before return 0, iclass 18, count 0 2006.201.05:03:03.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:03.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:03:03.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.05:03:03.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.05:03:03.85$vck44/vabw=wide 2006.201.05:03:03.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.05:03:03.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.05:03:03.85#ibcon#ireg 8 cls_cnt 0 2006.201.05:03:03.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:03.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:03.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:03.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.05:03:03.85#ibcon#first serial, iclass 20, count 0 2006.201.05:03:03.85#ibcon#enter sib2, iclass 20, count 0 2006.201.05:03:03.85#ibcon#flushed, iclass 20, count 0 2006.201.05:03:03.85#ibcon#about to write, iclass 20, count 0 2006.201.05:03:03.85#ibcon#wrote, iclass 20, count 0 2006.201.05:03:03.85#ibcon#about to read 3, iclass 20, count 0 2006.201.05:03:03.87#ibcon#read 3, iclass 20, count 0 2006.201.05:03:03.87#ibcon#about to read 4, iclass 20, count 0 2006.201.05:03:03.87#ibcon#read 4, iclass 20, count 0 2006.201.05:03:03.87#ibcon#about to read 5, iclass 20, count 0 2006.201.05:03:03.87#ibcon#read 5, iclass 20, count 0 2006.201.05:03:03.87#ibcon#about to read 6, iclass 20, count 0 2006.201.05:03:03.87#ibcon#read 6, iclass 20, count 0 2006.201.05:03:03.87#ibcon#end of sib2, iclass 20, count 0 2006.201.05:03:03.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.05:03:03.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.05:03:03.87#ibcon#[25=BW32\r\n] 2006.201.05:03:03.87#ibcon#*before write, iclass 20, count 0 2006.201.05:03:03.87#ibcon#enter sib2, iclass 20, count 0 2006.201.05:03:03.87#ibcon#flushed, iclass 20, count 0 2006.201.05:03:03.87#ibcon#about to write, iclass 20, count 0 2006.201.05:03:03.87#ibcon#wrote, iclass 20, count 0 2006.201.05:03:03.87#ibcon#about to read 3, iclass 20, count 0 2006.201.05:03:03.90#ibcon#read 3, iclass 20, count 0 2006.201.05:03:03.90#ibcon#about to read 4, iclass 20, count 0 2006.201.05:03:03.90#ibcon#read 4, iclass 20, count 0 2006.201.05:03:03.90#ibcon#about to read 5, iclass 20, count 0 2006.201.05:03:03.90#ibcon#read 5, iclass 20, count 0 2006.201.05:03:03.90#ibcon#about to read 6, iclass 20, count 0 2006.201.05:03:03.90#ibcon#read 6, iclass 20, count 0 2006.201.05:03:03.90#ibcon#end of sib2, iclass 20, count 0 2006.201.05:03:03.90#ibcon#*after write, iclass 20, count 0 2006.201.05:03:03.90#ibcon#*before return 0, iclass 20, count 0 2006.201.05:03:03.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:03.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:03:03.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.05:03:03.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.05:03:03.90$vck44/vbbw=wide 2006.201.05:03:03.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.05:03:03.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.05:03:03.90#ibcon#ireg 8 cls_cnt 0 2006.201.05:03:03.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:03:03.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:03:03.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:03:03.97#ibcon#enter wrdev, iclass 22, count 0 2006.201.05:03:03.97#ibcon#first serial, iclass 22, count 0 2006.201.05:03:03.97#ibcon#enter sib2, iclass 22, count 0 2006.201.05:03:03.97#ibcon#flushed, iclass 22, count 0 2006.201.05:03:03.97#ibcon#about to write, iclass 22, count 0 2006.201.05:03:03.97#ibcon#wrote, iclass 22, count 0 2006.201.05:03:03.97#ibcon#about to read 3, iclass 22, count 0 2006.201.05:03:03.99#ibcon#read 3, iclass 22, count 0 2006.201.05:03:03.99#ibcon#about to read 4, iclass 22, count 0 2006.201.05:03:03.99#ibcon#read 4, iclass 22, count 0 2006.201.05:03:03.99#ibcon#about to read 5, iclass 22, count 0 2006.201.05:03:03.99#ibcon#read 5, iclass 22, count 0 2006.201.05:03:03.99#ibcon#about to read 6, iclass 22, count 0 2006.201.05:03:03.99#ibcon#read 6, iclass 22, count 0 2006.201.05:03:03.99#ibcon#end of sib2, iclass 22, count 0 2006.201.05:03:03.99#ibcon#*mode == 0, iclass 22, count 0 2006.201.05:03:03.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.05:03:03.99#ibcon#[27=BW32\r\n] 2006.201.05:03:03.99#ibcon#*before write, iclass 22, count 0 2006.201.05:03:03.99#ibcon#enter sib2, iclass 22, count 0 2006.201.05:03:03.99#ibcon#flushed, iclass 22, count 0 2006.201.05:03:03.99#ibcon#about to write, iclass 22, count 0 2006.201.05:03:03.99#ibcon#wrote, iclass 22, count 0 2006.201.05:03:03.99#ibcon#about to read 3, iclass 22, count 0 2006.201.05:03:04.02#ibcon#read 3, iclass 22, count 0 2006.201.05:03:04.02#ibcon#about to read 4, iclass 22, count 0 2006.201.05:03:04.02#ibcon#read 4, iclass 22, count 0 2006.201.05:03:04.02#ibcon#about to read 5, iclass 22, count 0 2006.201.05:03:04.02#ibcon#read 5, iclass 22, count 0 2006.201.05:03:04.02#ibcon#about to read 6, iclass 22, count 0 2006.201.05:03:04.02#ibcon#read 6, iclass 22, count 0 2006.201.05:03:04.02#ibcon#end of sib2, iclass 22, count 0 2006.201.05:03:04.02#ibcon#*after write, iclass 22, count 0 2006.201.05:03:04.02#ibcon#*before return 0, iclass 22, count 0 2006.201.05:03:04.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:03:04.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:03:04.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.05:03:04.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.05:03:04.02$setupk4/ifdk4 2006.201.05:03:04.02$ifdk4/lo= 2006.201.05:03:04.02$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:03:04.02$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:03:04.02$ifdk4/patch= 2006.201.05:03:04.02$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:03:04.02$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:03:04.02$setupk4/!*+20s 2006.201.05:03:10.24#abcon#<5=/04 3.0 6.8 23.27 891004.0\r\n> 2006.201.05:03:10.26#abcon#{5=INTERFACE CLEAR} 2006.201.05:03:10.32#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:03:15.13#trakl#Source acquired 2006.201.05:03:15.13#flagr#flagr/antenna,acquired 2006.201.05:03:18.25$setupk4/"tpicd 2006.201.05:03:18.25$setupk4/echo=off 2006.201.05:03:18.25$setupk4/xlog=off 2006.201.05:03:18.25:!2006.201.05:04:35 2006.201.05:04:35.00:preob 2006.201.05:04:35.13/onsource/TRACKING 2006.201.05:04:35.13:!2006.201.05:04:45 2006.201.05:04:45.00:"tape 2006.201.05:04:45.00:"st=record 2006.201.05:04:45.00:data_valid=on 2006.201.05:04:45.00:midob 2006.201.05:04:45.13/onsource/TRACKING 2006.201.05:04:45.13/wx/23.28,1003.9,90 2006.201.05:04:45.23/cable/+6.4656E-03 2006.201.05:04:46.32/va/01,08,usb,yes,30,33 2006.201.05:04:46.32/va/02,07,usb,yes,33,34 2006.201.05:04:46.32/va/03,08,usb,yes,30,31 2006.201.05:04:46.32/va/04,07,usb,yes,34,36 2006.201.05:04:46.32/va/05,04,usb,yes,30,30 2006.201.05:04:46.32/va/06,05,usb,yes,30,30 2006.201.05:04:46.32/va/07,05,usb,yes,29,30 2006.201.05:04:46.32/va/08,04,usb,yes,28,34 2006.201.05:04:46.55/valo/01,524.99,yes,locked 2006.201.05:04:46.55/valo/02,534.99,yes,locked 2006.201.05:04:46.55/valo/03,564.99,yes,locked 2006.201.05:04:46.55/valo/04,624.99,yes,locked 2006.201.05:04:46.55/valo/05,734.99,yes,locked 2006.201.05:04:46.55/valo/06,814.99,yes,locked 2006.201.05:04:46.55/valo/07,864.99,yes,locked 2006.201.05:04:46.55/valo/08,884.99,yes,locked 2006.201.05:04:47.64/vb/01,04,usb,yes,36,33 2006.201.05:04:47.64/vb/02,05,usb,yes,34,33 2006.201.05:04:47.64/vb/03,04,usb,yes,35,38 2006.201.05:04:47.64/vb/04,05,usb,yes,35,34 2006.201.05:04:47.64/vb/05,04,usb,yes,31,34 2006.201.05:04:47.64/vb/06,04,usb,yes,36,32 2006.201.05:04:47.64/vb/07,04,usb,yes,36,36 2006.201.05:04:47.64/vb/08,04,usb,yes,33,37 2006.201.05:04:47.88/vblo/01,629.99,yes,locked 2006.201.05:04:47.88/vblo/02,634.99,yes,locked 2006.201.05:04:47.88/vblo/03,649.99,yes,locked 2006.201.05:04:47.88/vblo/04,679.99,yes,locked 2006.201.05:04:47.88/vblo/05,709.99,yes,locked 2006.201.05:04:47.88/vblo/06,719.99,yes,locked 2006.201.05:04:47.88/vblo/07,734.99,yes,locked 2006.201.05:04:47.88/vblo/08,744.99,yes,locked 2006.201.05:04:48.03/vabw/8 2006.201.05:04:48.18/vbbw/8 2006.201.05:04:48.30/xfe/off,on,15.2 2006.201.05:04:48.67/ifatt/23,28,28,28 2006.201.05:04:49.05/fmout-gps/S +4.48E-07 2006.201.05:04:49.08:!2006.201.05:06:15 2006.201.05:06:15.00:data_valid=off 2006.201.05:06:15.00:"et 2006.201.05:06:15.00:!+3s 2006.201.05:06:18.01:"tape 2006.201.05:06:18.01:postob 2006.201.05:06:18.23/cable/+6.4657E-03 2006.201.05:06:18.23/wx/23.28,1003.8,90 2006.201.05:06:18.29/fmout-gps/S +4.47E-07 2006.201.05:06:18.29:scan_name=201-0513,jd0607,70 2006.201.05:06:18.29:source=1611+343,161341.06,341247.9,2000.0,cw 2006.201.05:06:19.14#flagr#flagr/antenna,new-source 2006.201.05:06:19.14:checkk5 2006.201.05:06:19.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:06:19.94/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:06:20.35/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:06:20.75/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:06:21.13/chk_obsdata//k5ts1/T2010504??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.05:06:21.56/chk_obsdata//k5ts2/T2010504??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.05:06:21.97/chk_obsdata//k5ts3/T2010504??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.05:06:22.36/chk_obsdata//k5ts4/T2010504??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.05:06:23.09/k5log//k5ts1_log_newline 2006.201.05:06:23.81/k5log//k5ts2_log_newline 2006.201.05:06:24.51/k5log//k5ts3_log_newline 2006.201.05:06:25.22/k5log//k5ts4_log_newline 2006.201.05:06:25.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:06:25.24:setupk4=1 2006.201.05:06:25.24$setupk4/echo=on 2006.201.05:06:25.24$setupk4/pcalon 2006.201.05:06:25.24$pcalon/"no phase cal control is implemented here 2006.201.05:06:25.24$setupk4/"tpicd=stop 2006.201.05:06:25.24$setupk4/"rec=synch_on 2006.201.05:06:25.24$setupk4/"rec_mode=128 2006.201.05:06:25.24$setupk4/!* 2006.201.05:06:25.24$setupk4/recpk4 2006.201.05:06:25.24$recpk4/recpatch= 2006.201.05:06:25.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:06:25.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:06:25.25$setupk4/vck44 2006.201.05:06:25.25$vck44/valo=1,524.99 2006.201.05:06:25.25#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.05:06:25.25#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.05:06:25.25#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:25.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:25.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:25.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:25.25#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:06:25.25#ibcon#first serial, iclass 35, count 0 2006.201.05:06:25.25#ibcon#enter sib2, iclass 35, count 0 2006.201.05:06:25.25#ibcon#flushed, iclass 35, count 0 2006.201.05:06:25.25#ibcon#about to write, iclass 35, count 0 2006.201.05:06:25.25#ibcon#wrote, iclass 35, count 0 2006.201.05:06:25.25#ibcon#about to read 3, iclass 35, count 0 2006.201.05:06:25.27#ibcon#read 3, iclass 35, count 0 2006.201.05:06:25.27#ibcon#about to read 4, iclass 35, count 0 2006.201.05:06:25.27#ibcon#read 4, iclass 35, count 0 2006.201.05:06:25.27#ibcon#about to read 5, iclass 35, count 0 2006.201.05:06:25.27#ibcon#read 5, iclass 35, count 0 2006.201.05:06:25.27#ibcon#about to read 6, iclass 35, count 0 2006.201.05:06:25.27#ibcon#read 6, iclass 35, count 0 2006.201.05:06:25.27#ibcon#end of sib2, iclass 35, count 0 2006.201.05:06:25.27#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:06:25.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:06:25.27#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:06:25.27#ibcon#*before write, iclass 35, count 0 2006.201.05:06:25.27#ibcon#enter sib2, iclass 35, count 0 2006.201.05:06:25.27#ibcon#flushed, iclass 35, count 0 2006.201.05:06:25.27#ibcon#about to write, iclass 35, count 0 2006.201.05:06:25.27#ibcon#wrote, iclass 35, count 0 2006.201.05:06:25.27#ibcon#about to read 3, iclass 35, count 0 2006.201.05:06:25.32#ibcon#read 3, iclass 35, count 0 2006.201.05:06:25.32#ibcon#about to read 4, iclass 35, count 0 2006.201.05:06:25.32#ibcon#read 4, iclass 35, count 0 2006.201.05:06:25.32#ibcon#about to read 5, iclass 35, count 0 2006.201.05:06:25.32#ibcon#read 5, iclass 35, count 0 2006.201.05:06:25.32#ibcon#about to read 6, iclass 35, count 0 2006.201.05:06:25.32#ibcon#read 6, iclass 35, count 0 2006.201.05:06:25.32#ibcon#end of sib2, iclass 35, count 0 2006.201.05:06:25.32#ibcon#*after write, iclass 35, count 0 2006.201.05:06:25.32#ibcon#*before return 0, iclass 35, count 0 2006.201.05:06:25.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:25.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:25.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:06:25.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:06:25.32$vck44/va=1,8 2006.201.05:06:25.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.05:06:25.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.05:06:25.32#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:25.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:25.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:25.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:25.32#ibcon#enter wrdev, iclass 37, count 2 2006.201.05:06:25.32#ibcon#first serial, iclass 37, count 2 2006.201.05:06:25.32#ibcon#enter sib2, iclass 37, count 2 2006.201.05:06:25.32#ibcon#flushed, iclass 37, count 2 2006.201.05:06:25.32#ibcon#about to write, iclass 37, count 2 2006.201.05:06:25.32#ibcon#wrote, iclass 37, count 2 2006.201.05:06:25.32#ibcon#about to read 3, iclass 37, count 2 2006.201.05:06:25.34#ibcon#read 3, iclass 37, count 2 2006.201.05:06:25.34#ibcon#about to read 4, iclass 37, count 2 2006.201.05:06:25.34#ibcon#read 4, iclass 37, count 2 2006.201.05:06:25.34#ibcon#about to read 5, iclass 37, count 2 2006.201.05:06:25.34#ibcon#read 5, iclass 37, count 2 2006.201.05:06:25.34#ibcon#about to read 6, iclass 37, count 2 2006.201.05:06:25.34#ibcon#read 6, iclass 37, count 2 2006.201.05:06:25.34#ibcon#end of sib2, iclass 37, count 2 2006.201.05:06:25.34#ibcon#*mode == 0, iclass 37, count 2 2006.201.05:06:25.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.05:06:25.34#ibcon#[25=AT01-08\r\n] 2006.201.05:06:25.34#ibcon#*before write, iclass 37, count 2 2006.201.05:06:25.34#ibcon#enter sib2, iclass 37, count 2 2006.201.05:06:25.34#ibcon#flushed, iclass 37, count 2 2006.201.05:06:25.34#ibcon#about to write, iclass 37, count 2 2006.201.05:06:25.34#ibcon#wrote, iclass 37, count 2 2006.201.05:06:25.34#ibcon#about to read 3, iclass 37, count 2 2006.201.05:06:25.37#ibcon#read 3, iclass 37, count 2 2006.201.05:06:25.37#ibcon#about to read 4, iclass 37, count 2 2006.201.05:06:25.37#ibcon#read 4, iclass 37, count 2 2006.201.05:06:25.37#ibcon#about to read 5, iclass 37, count 2 2006.201.05:06:25.37#ibcon#read 5, iclass 37, count 2 2006.201.05:06:25.37#ibcon#about to read 6, iclass 37, count 2 2006.201.05:06:25.37#ibcon#read 6, iclass 37, count 2 2006.201.05:06:25.37#ibcon#end of sib2, iclass 37, count 2 2006.201.05:06:25.37#ibcon#*after write, iclass 37, count 2 2006.201.05:06:25.37#ibcon#*before return 0, iclass 37, count 2 2006.201.05:06:25.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:25.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:25.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.05:06:25.37#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:25.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:25.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:25.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:25.49#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:06:25.49#ibcon#first serial, iclass 37, count 0 2006.201.05:06:25.49#ibcon#enter sib2, iclass 37, count 0 2006.201.05:06:25.49#ibcon#flushed, iclass 37, count 0 2006.201.05:06:25.49#ibcon#about to write, iclass 37, count 0 2006.201.05:06:25.49#ibcon#wrote, iclass 37, count 0 2006.201.05:06:25.49#ibcon#about to read 3, iclass 37, count 0 2006.201.05:06:25.51#ibcon#read 3, iclass 37, count 0 2006.201.05:06:25.51#ibcon#about to read 4, iclass 37, count 0 2006.201.05:06:25.51#ibcon#read 4, iclass 37, count 0 2006.201.05:06:25.51#ibcon#about to read 5, iclass 37, count 0 2006.201.05:06:25.51#ibcon#read 5, iclass 37, count 0 2006.201.05:06:25.51#ibcon#about to read 6, iclass 37, count 0 2006.201.05:06:25.51#ibcon#read 6, iclass 37, count 0 2006.201.05:06:25.51#ibcon#end of sib2, iclass 37, count 0 2006.201.05:06:25.51#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:06:25.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:06:25.51#ibcon#[25=USB\r\n] 2006.201.05:06:25.51#ibcon#*before write, iclass 37, count 0 2006.201.05:06:25.51#ibcon#enter sib2, iclass 37, count 0 2006.201.05:06:25.51#ibcon#flushed, iclass 37, count 0 2006.201.05:06:25.51#ibcon#about to write, iclass 37, count 0 2006.201.05:06:25.51#ibcon#wrote, iclass 37, count 0 2006.201.05:06:25.51#ibcon#about to read 3, iclass 37, count 0 2006.201.05:06:25.54#ibcon#read 3, iclass 37, count 0 2006.201.05:06:25.54#ibcon#about to read 4, iclass 37, count 0 2006.201.05:06:25.54#ibcon#read 4, iclass 37, count 0 2006.201.05:06:25.54#ibcon#about to read 5, iclass 37, count 0 2006.201.05:06:25.54#ibcon#read 5, iclass 37, count 0 2006.201.05:06:25.54#ibcon#about to read 6, iclass 37, count 0 2006.201.05:06:25.54#ibcon#read 6, iclass 37, count 0 2006.201.05:06:25.54#ibcon#end of sib2, iclass 37, count 0 2006.201.05:06:25.54#ibcon#*after write, iclass 37, count 0 2006.201.05:06:25.54#ibcon#*before return 0, iclass 37, count 0 2006.201.05:06:25.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:25.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:25.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:06:25.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:06:25.54$vck44/valo=2,534.99 2006.201.05:06:25.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.05:06:25.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.05:06:25.54#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:25.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:25.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:25.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:25.54#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:06:25.54#ibcon#first serial, iclass 39, count 0 2006.201.05:06:25.54#ibcon#enter sib2, iclass 39, count 0 2006.201.05:06:25.54#ibcon#flushed, iclass 39, count 0 2006.201.05:06:25.54#ibcon#about to write, iclass 39, count 0 2006.201.05:06:25.54#ibcon#wrote, iclass 39, count 0 2006.201.05:06:25.54#ibcon#about to read 3, iclass 39, count 0 2006.201.05:06:25.56#ibcon#read 3, iclass 39, count 0 2006.201.05:06:25.56#ibcon#about to read 4, iclass 39, count 0 2006.201.05:06:25.56#ibcon#read 4, iclass 39, count 0 2006.201.05:06:25.56#ibcon#about to read 5, iclass 39, count 0 2006.201.05:06:25.56#ibcon#read 5, iclass 39, count 0 2006.201.05:06:25.56#ibcon#about to read 6, iclass 39, count 0 2006.201.05:06:25.56#ibcon#read 6, iclass 39, count 0 2006.201.05:06:25.56#ibcon#end of sib2, iclass 39, count 0 2006.201.05:06:25.56#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:06:25.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:06:25.56#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:06:25.56#ibcon#*before write, iclass 39, count 0 2006.201.05:06:25.56#ibcon#enter sib2, iclass 39, count 0 2006.201.05:06:25.56#ibcon#flushed, iclass 39, count 0 2006.201.05:06:25.56#ibcon#about to write, iclass 39, count 0 2006.201.05:06:25.56#ibcon#wrote, iclass 39, count 0 2006.201.05:06:25.56#ibcon#about to read 3, iclass 39, count 0 2006.201.05:06:25.60#ibcon#read 3, iclass 39, count 0 2006.201.05:06:25.60#ibcon#about to read 4, iclass 39, count 0 2006.201.05:06:25.60#ibcon#read 4, iclass 39, count 0 2006.201.05:06:25.60#ibcon#about to read 5, iclass 39, count 0 2006.201.05:06:25.60#ibcon#read 5, iclass 39, count 0 2006.201.05:06:25.60#ibcon#about to read 6, iclass 39, count 0 2006.201.05:06:25.60#ibcon#read 6, iclass 39, count 0 2006.201.05:06:25.60#ibcon#end of sib2, iclass 39, count 0 2006.201.05:06:25.60#ibcon#*after write, iclass 39, count 0 2006.201.05:06:25.60#ibcon#*before return 0, iclass 39, count 0 2006.201.05:06:25.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:25.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:25.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:06:25.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:06:25.60$vck44/va=2,7 2006.201.05:06:25.60#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.05:06:25.60#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.05:06:25.60#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:25.60#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:25.66#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:25.66#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:25.66#ibcon#enter wrdev, iclass 2, count 2 2006.201.05:06:25.66#ibcon#first serial, iclass 2, count 2 2006.201.05:06:25.66#ibcon#enter sib2, iclass 2, count 2 2006.201.05:06:25.66#ibcon#flushed, iclass 2, count 2 2006.201.05:06:25.66#ibcon#about to write, iclass 2, count 2 2006.201.05:06:25.66#ibcon#wrote, iclass 2, count 2 2006.201.05:06:25.66#ibcon#about to read 3, iclass 2, count 2 2006.201.05:06:25.68#ibcon#read 3, iclass 2, count 2 2006.201.05:06:25.68#ibcon#about to read 4, iclass 2, count 2 2006.201.05:06:25.68#ibcon#read 4, iclass 2, count 2 2006.201.05:06:25.68#ibcon#about to read 5, iclass 2, count 2 2006.201.05:06:25.68#ibcon#read 5, iclass 2, count 2 2006.201.05:06:25.68#ibcon#about to read 6, iclass 2, count 2 2006.201.05:06:25.68#ibcon#read 6, iclass 2, count 2 2006.201.05:06:25.68#ibcon#end of sib2, iclass 2, count 2 2006.201.05:06:25.68#ibcon#*mode == 0, iclass 2, count 2 2006.201.05:06:25.68#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.05:06:25.68#ibcon#[25=AT02-07\r\n] 2006.201.05:06:25.68#ibcon#*before write, iclass 2, count 2 2006.201.05:06:25.68#ibcon#enter sib2, iclass 2, count 2 2006.201.05:06:25.68#ibcon#flushed, iclass 2, count 2 2006.201.05:06:25.68#ibcon#about to write, iclass 2, count 2 2006.201.05:06:25.68#ibcon#wrote, iclass 2, count 2 2006.201.05:06:25.68#ibcon#about to read 3, iclass 2, count 2 2006.201.05:06:25.71#ibcon#read 3, iclass 2, count 2 2006.201.05:06:25.71#ibcon#about to read 4, iclass 2, count 2 2006.201.05:06:25.71#ibcon#read 4, iclass 2, count 2 2006.201.05:06:25.71#ibcon#about to read 5, iclass 2, count 2 2006.201.05:06:25.71#ibcon#read 5, iclass 2, count 2 2006.201.05:06:25.71#ibcon#about to read 6, iclass 2, count 2 2006.201.05:06:25.71#ibcon#read 6, iclass 2, count 2 2006.201.05:06:25.71#ibcon#end of sib2, iclass 2, count 2 2006.201.05:06:25.71#ibcon#*after write, iclass 2, count 2 2006.201.05:06:25.71#ibcon#*before return 0, iclass 2, count 2 2006.201.05:06:25.71#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:25.71#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:25.71#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.05:06:25.71#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:25.71#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:25.83#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:25.83#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:25.83#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:06:25.83#ibcon#first serial, iclass 2, count 0 2006.201.05:06:25.83#ibcon#enter sib2, iclass 2, count 0 2006.201.05:06:25.83#ibcon#flushed, iclass 2, count 0 2006.201.05:06:25.83#ibcon#about to write, iclass 2, count 0 2006.201.05:06:25.83#ibcon#wrote, iclass 2, count 0 2006.201.05:06:25.83#ibcon#about to read 3, iclass 2, count 0 2006.201.05:06:25.85#ibcon#read 3, iclass 2, count 0 2006.201.05:06:25.85#ibcon#about to read 4, iclass 2, count 0 2006.201.05:06:25.85#ibcon#read 4, iclass 2, count 0 2006.201.05:06:25.85#ibcon#about to read 5, iclass 2, count 0 2006.201.05:06:25.85#ibcon#read 5, iclass 2, count 0 2006.201.05:06:25.85#ibcon#about to read 6, iclass 2, count 0 2006.201.05:06:25.85#ibcon#read 6, iclass 2, count 0 2006.201.05:06:25.85#ibcon#end of sib2, iclass 2, count 0 2006.201.05:06:25.85#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:06:25.85#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:06:25.85#ibcon#[25=USB\r\n] 2006.201.05:06:25.85#ibcon#*before write, iclass 2, count 0 2006.201.05:06:25.85#ibcon#enter sib2, iclass 2, count 0 2006.201.05:06:25.85#ibcon#flushed, iclass 2, count 0 2006.201.05:06:25.85#ibcon#about to write, iclass 2, count 0 2006.201.05:06:25.85#ibcon#wrote, iclass 2, count 0 2006.201.05:06:25.85#ibcon#about to read 3, iclass 2, count 0 2006.201.05:06:25.88#ibcon#read 3, iclass 2, count 0 2006.201.05:06:25.88#ibcon#about to read 4, iclass 2, count 0 2006.201.05:06:25.88#ibcon#read 4, iclass 2, count 0 2006.201.05:06:25.88#ibcon#about to read 5, iclass 2, count 0 2006.201.05:06:25.88#ibcon#read 5, iclass 2, count 0 2006.201.05:06:25.88#ibcon#about to read 6, iclass 2, count 0 2006.201.05:06:25.88#ibcon#read 6, iclass 2, count 0 2006.201.05:06:25.88#ibcon#end of sib2, iclass 2, count 0 2006.201.05:06:25.88#ibcon#*after write, iclass 2, count 0 2006.201.05:06:25.88#ibcon#*before return 0, iclass 2, count 0 2006.201.05:06:25.88#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:25.88#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:25.88#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:06:25.88#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:06:25.88$vck44/valo=3,564.99 2006.201.05:06:25.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.05:06:25.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.05:06:25.88#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:25.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:25.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:25.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:25.88#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:06:25.88#ibcon#first serial, iclass 5, count 0 2006.201.05:06:25.88#ibcon#enter sib2, iclass 5, count 0 2006.201.05:06:25.88#ibcon#flushed, iclass 5, count 0 2006.201.05:06:25.88#ibcon#about to write, iclass 5, count 0 2006.201.05:06:25.88#ibcon#wrote, iclass 5, count 0 2006.201.05:06:25.88#ibcon#about to read 3, iclass 5, count 0 2006.201.05:06:25.90#ibcon#read 3, iclass 5, count 0 2006.201.05:06:25.90#ibcon#about to read 4, iclass 5, count 0 2006.201.05:06:25.90#ibcon#read 4, iclass 5, count 0 2006.201.05:06:25.90#ibcon#about to read 5, iclass 5, count 0 2006.201.05:06:25.90#ibcon#read 5, iclass 5, count 0 2006.201.05:06:25.90#ibcon#about to read 6, iclass 5, count 0 2006.201.05:06:25.90#ibcon#read 6, iclass 5, count 0 2006.201.05:06:25.90#ibcon#end of sib2, iclass 5, count 0 2006.201.05:06:25.90#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:06:25.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:06:25.90#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:06:25.90#ibcon#*before write, iclass 5, count 0 2006.201.05:06:25.90#ibcon#enter sib2, iclass 5, count 0 2006.201.05:06:25.90#ibcon#flushed, iclass 5, count 0 2006.201.05:06:25.90#ibcon#about to write, iclass 5, count 0 2006.201.05:06:25.90#ibcon#wrote, iclass 5, count 0 2006.201.05:06:25.90#ibcon#about to read 3, iclass 5, count 0 2006.201.05:06:25.94#ibcon#read 3, iclass 5, count 0 2006.201.05:06:25.94#ibcon#about to read 4, iclass 5, count 0 2006.201.05:06:25.94#ibcon#read 4, iclass 5, count 0 2006.201.05:06:25.94#ibcon#about to read 5, iclass 5, count 0 2006.201.05:06:25.94#ibcon#read 5, iclass 5, count 0 2006.201.05:06:25.94#ibcon#about to read 6, iclass 5, count 0 2006.201.05:06:25.94#ibcon#read 6, iclass 5, count 0 2006.201.05:06:25.94#ibcon#end of sib2, iclass 5, count 0 2006.201.05:06:25.94#ibcon#*after write, iclass 5, count 0 2006.201.05:06:25.94#ibcon#*before return 0, iclass 5, count 0 2006.201.05:06:25.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:25.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:25.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:06:25.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:06:25.94$vck44/va=3,8 2006.201.05:06:25.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.05:06:25.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.05:06:25.94#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:25.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:26.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:26.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:26.00#ibcon#enter wrdev, iclass 7, count 2 2006.201.05:06:26.00#ibcon#first serial, iclass 7, count 2 2006.201.05:06:26.00#ibcon#enter sib2, iclass 7, count 2 2006.201.05:06:26.00#ibcon#flushed, iclass 7, count 2 2006.201.05:06:26.00#ibcon#about to write, iclass 7, count 2 2006.201.05:06:26.00#ibcon#wrote, iclass 7, count 2 2006.201.05:06:26.00#ibcon#about to read 3, iclass 7, count 2 2006.201.05:06:26.02#ibcon#read 3, iclass 7, count 2 2006.201.05:06:26.02#ibcon#about to read 4, iclass 7, count 2 2006.201.05:06:26.02#ibcon#read 4, iclass 7, count 2 2006.201.05:06:26.02#ibcon#about to read 5, iclass 7, count 2 2006.201.05:06:26.02#ibcon#read 5, iclass 7, count 2 2006.201.05:06:26.02#ibcon#about to read 6, iclass 7, count 2 2006.201.05:06:26.02#ibcon#read 6, iclass 7, count 2 2006.201.05:06:26.02#ibcon#end of sib2, iclass 7, count 2 2006.201.05:06:26.02#ibcon#*mode == 0, iclass 7, count 2 2006.201.05:06:26.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.05:06:26.02#ibcon#[25=AT03-08\r\n] 2006.201.05:06:26.02#ibcon#*before write, iclass 7, count 2 2006.201.05:06:26.02#ibcon#enter sib2, iclass 7, count 2 2006.201.05:06:26.02#ibcon#flushed, iclass 7, count 2 2006.201.05:06:26.02#ibcon#about to write, iclass 7, count 2 2006.201.05:06:26.02#ibcon#wrote, iclass 7, count 2 2006.201.05:06:26.02#ibcon#about to read 3, iclass 7, count 2 2006.201.05:06:26.05#ibcon#read 3, iclass 7, count 2 2006.201.05:06:26.05#ibcon#about to read 4, iclass 7, count 2 2006.201.05:06:26.05#ibcon#read 4, iclass 7, count 2 2006.201.05:06:26.05#ibcon#about to read 5, iclass 7, count 2 2006.201.05:06:26.05#ibcon#read 5, iclass 7, count 2 2006.201.05:06:26.05#ibcon#about to read 6, iclass 7, count 2 2006.201.05:06:26.05#ibcon#read 6, iclass 7, count 2 2006.201.05:06:26.05#ibcon#end of sib2, iclass 7, count 2 2006.201.05:06:26.05#ibcon#*after write, iclass 7, count 2 2006.201.05:06:26.05#ibcon#*before return 0, iclass 7, count 2 2006.201.05:06:26.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:26.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:26.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.05:06:26.05#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:26.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:26.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:26.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:26.17#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:06:26.17#ibcon#first serial, iclass 7, count 0 2006.201.05:06:26.17#ibcon#enter sib2, iclass 7, count 0 2006.201.05:06:26.17#ibcon#flushed, iclass 7, count 0 2006.201.05:06:26.17#ibcon#about to write, iclass 7, count 0 2006.201.05:06:26.17#ibcon#wrote, iclass 7, count 0 2006.201.05:06:26.17#ibcon#about to read 3, iclass 7, count 0 2006.201.05:06:26.19#ibcon#read 3, iclass 7, count 0 2006.201.05:06:26.19#ibcon#about to read 4, iclass 7, count 0 2006.201.05:06:26.19#ibcon#read 4, iclass 7, count 0 2006.201.05:06:26.19#ibcon#about to read 5, iclass 7, count 0 2006.201.05:06:26.19#ibcon#read 5, iclass 7, count 0 2006.201.05:06:26.19#ibcon#about to read 6, iclass 7, count 0 2006.201.05:06:26.19#ibcon#read 6, iclass 7, count 0 2006.201.05:06:26.19#ibcon#end of sib2, iclass 7, count 0 2006.201.05:06:26.19#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:06:26.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:06:26.19#ibcon#[25=USB\r\n] 2006.201.05:06:26.19#ibcon#*before write, iclass 7, count 0 2006.201.05:06:26.19#ibcon#enter sib2, iclass 7, count 0 2006.201.05:06:26.19#ibcon#flushed, iclass 7, count 0 2006.201.05:06:26.19#ibcon#about to write, iclass 7, count 0 2006.201.05:06:26.19#ibcon#wrote, iclass 7, count 0 2006.201.05:06:26.19#ibcon#about to read 3, iclass 7, count 0 2006.201.05:06:26.22#ibcon#read 3, iclass 7, count 0 2006.201.05:06:26.22#ibcon#about to read 4, iclass 7, count 0 2006.201.05:06:26.22#ibcon#read 4, iclass 7, count 0 2006.201.05:06:26.22#ibcon#about to read 5, iclass 7, count 0 2006.201.05:06:26.22#ibcon#read 5, iclass 7, count 0 2006.201.05:06:26.22#ibcon#about to read 6, iclass 7, count 0 2006.201.05:06:26.22#ibcon#read 6, iclass 7, count 0 2006.201.05:06:26.22#ibcon#end of sib2, iclass 7, count 0 2006.201.05:06:26.22#ibcon#*after write, iclass 7, count 0 2006.201.05:06:26.22#ibcon#*before return 0, iclass 7, count 0 2006.201.05:06:26.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:26.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:26.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:06:26.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:06:26.22$vck44/valo=4,624.99 2006.201.05:06:26.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.05:06:26.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.05:06:26.22#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:26.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:26.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:26.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:26.22#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:06:26.22#ibcon#first serial, iclass 11, count 0 2006.201.05:06:26.22#ibcon#enter sib2, iclass 11, count 0 2006.201.05:06:26.22#ibcon#flushed, iclass 11, count 0 2006.201.05:06:26.22#ibcon#about to write, iclass 11, count 0 2006.201.05:06:26.22#ibcon#wrote, iclass 11, count 0 2006.201.05:06:26.22#ibcon#about to read 3, iclass 11, count 0 2006.201.05:06:26.24#ibcon#read 3, iclass 11, count 0 2006.201.05:06:26.24#ibcon#about to read 4, iclass 11, count 0 2006.201.05:06:26.24#ibcon#read 4, iclass 11, count 0 2006.201.05:06:26.24#ibcon#about to read 5, iclass 11, count 0 2006.201.05:06:26.24#ibcon#read 5, iclass 11, count 0 2006.201.05:06:26.24#ibcon#about to read 6, iclass 11, count 0 2006.201.05:06:26.24#ibcon#read 6, iclass 11, count 0 2006.201.05:06:26.24#ibcon#end of sib2, iclass 11, count 0 2006.201.05:06:26.24#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:06:26.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:06:26.24#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:06:26.24#ibcon#*before write, iclass 11, count 0 2006.201.05:06:26.24#ibcon#enter sib2, iclass 11, count 0 2006.201.05:06:26.24#ibcon#flushed, iclass 11, count 0 2006.201.05:06:26.24#ibcon#about to write, iclass 11, count 0 2006.201.05:06:26.24#ibcon#wrote, iclass 11, count 0 2006.201.05:06:26.24#ibcon#about to read 3, iclass 11, count 0 2006.201.05:06:26.28#ibcon#read 3, iclass 11, count 0 2006.201.05:06:26.28#ibcon#about to read 4, iclass 11, count 0 2006.201.05:06:26.28#ibcon#read 4, iclass 11, count 0 2006.201.05:06:26.28#ibcon#about to read 5, iclass 11, count 0 2006.201.05:06:26.28#ibcon#read 5, iclass 11, count 0 2006.201.05:06:26.28#ibcon#about to read 6, iclass 11, count 0 2006.201.05:06:26.28#ibcon#read 6, iclass 11, count 0 2006.201.05:06:26.28#ibcon#end of sib2, iclass 11, count 0 2006.201.05:06:26.28#ibcon#*after write, iclass 11, count 0 2006.201.05:06:26.28#ibcon#*before return 0, iclass 11, count 0 2006.201.05:06:26.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:26.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:26.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:06:26.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:06:26.28$vck44/va=4,7 2006.201.05:06:26.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.05:06:26.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.05:06:26.28#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:26.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:26.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:26.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:26.34#ibcon#enter wrdev, iclass 13, count 2 2006.201.05:06:26.34#ibcon#first serial, iclass 13, count 2 2006.201.05:06:26.34#ibcon#enter sib2, iclass 13, count 2 2006.201.05:06:26.34#ibcon#flushed, iclass 13, count 2 2006.201.05:06:26.34#ibcon#about to write, iclass 13, count 2 2006.201.05:06:26.34#ibcon#wrote, iclass 13, count 2 2006.201.05:06:26.34#ibcon#about to read 3, iclass 13, count 2 2006.201.05:06:26.36#ibcon#read 3, iclass 13, count 2 2006.201.05:06:26.36#ibcon#about to read 4, iclass 13, count 2 2006.201.05:06:26.36#ibcon#read 4, iclass 13, count 2 2006.201.05:06:26.36#ibcon#about to read 5, iclass 13, count 2 2006.201.05:06:26.36#ibcon#read 5, iclass 13, count 2 2006.201.05:06:26.36#ibcon#about to read 6, iclass 13, count 2 2006.201.05:06:26.36#ibcon#read 6, iclass 13, count 2 2006.201.05:06:26.36#ibcon#end of sib2, iclass 13, count 2 2006.201.05:06:26.36#ibcon#*mode == 0, iclass 13, count 2 2006.201.05:06:26.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.05:06:26.36#ibcon#[25=AT04-07\r\n] 2006.201.05:06:26.36#ibcon#*before write, iclass 13, count 2 2006.201.05:06:26.36#ibcon#enter sib2, iclass 13, count 2 2006.201.05:06:26.36#ibcon#flushed, iclass 13, count 2 2006.201.05:06:26.36#ibcon#about to write, iclass 13, count 2 2006.201.05:06:26.36#ibcon#wrote, iclass 13, count 2 2006.201.05:06:26.36#ibcon#about to read 3, iclass 13, count 2 2006.201.05:06:26.39#ibcon#read 3, iclass 13, count 2 2006.201.05:06:26.39#ibcon#about to read 4, iclass 13, count 2 2006.201.05:06:26.39#ibcon#read 4, iclass 13, count 2 2006.201.05:06:26.39#ibcon#about to read 5, iclass 13, count 2 2006.201.05:06:26.39#ibcon#read 5, iclass 13, count 2 2006.201.05:06:26.39#ibcon#about to read 6, iclass 13, count 2 2006.201.05:06:26.39#ibcon#read 6, iclass 13, count 2 2006.201.05:06:26.39#ibcon#end of sib2, iclass 13, count 2 2006.201.05:06:26.39#ibcon#*after write, iclass 13, count 2 2006.201.05:06:26.39#ibcon#*before return 0, iclass 13, count 2 2006.201.05:06:26.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:26.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:26.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.05:06:26.39#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:26.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:26.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:26.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:26.51#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:06:26.51#ibcon#first serial, iclass 13, count 0 2006.201.05:06:26.51#ibcon#enter sib2, iclass 13, count 0 2006.201.05:06:26.51#ibcon#flushed, iclass 13, count 0 2006.201.05:06:26.51#ibcon#about to write, iclass 13, count 0 2006.201.05:06:26.51#ibcon#wrote, iclass 13, count 0 2006.201.05:06:26.51#ibcon#about to read 3, iclass 13, count 0 2006.201.05:06:26.53#ibcon#read 3, iclass 13, count 0 2006.201.05:06:26.53#ibcon#about to read 4, iclass 13, count 0 2006.201.05:06:26.53#ibcon#read 4, iclass 13, count 0 2006.201.05:06:26.53#ibcon#about to read 5, iclass 13, count 0 2006.201.05:06:26.53#ibcon#read 5, iclass 13, count 0 2006.201.05:06:26.53#ibcon#about to read 6, iclass 13, count 0 2006.201.05:06:26.53#ibcon#read 6, iclass 13, count 0 2006.201.05:06:26.53#ibcon#end of sib2, iclass 13, count 0 2006.201.05:06:26.53#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:06:26.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:06:26.53#ibcon#[25=USB\r\n] 2006.201.05:06:26.53#ibcon#*before write, iclass 13, count 0 2006.201.05:06:26.53#ibcon#enter sib2, iclass 13, count 0 2006.201.05:06:26.53#ibcon#flushed, iclass 13, count 0 2006.201.05:06:26.53#ibcon#about to write, iclass 13, count 0 2006.201.05:06:26.53#ibcon#wrote, iclass 13, count 0 2006.201.05:06:26.53#ibcon#about to read 3, iclass 13, count 0 2006.201.05:06:26.56#ibcon#read 3, iclass 13, count 0 2006.201.05:06:26.56#ibcon#about to read 4, iclass 13, count 0 2006.201.05:06:26.56#ibcon#read 4, iclass 13, count 0 2006.201.05:06:26.56#ibcon#about to read 5, iclass 13, count 0 2006.201.05:06:26.56#ibcon#read 5, iclass 13, count 0 2006.201.05:06:26.56#ibcon#about to read 6, iclass 13, count 0 2006.201.05:06:26.56#ibcon#read 6, iclass 13, count 0 2006.201.05:06:26.56#ibcon#end of sib2, iclass 13, count 0 2006.201.05:06:26.56#ibcon#*after write, iclass 13, count 0 2006.201.05:06:26.56#ibcon#*before return 0, iclass 13, count 0 2006.201.05:06:26.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:26.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:26.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:06:26.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:06:26.56$vck44/valo=5,734.99 2006.201.05:06:26.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.05:06:26.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.05:06:26.56#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:26.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:26.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:26.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:26.56#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:06:26.56#ibcon#first serial, iclass 15, count 0 2006.201.05:06:26.56#ibcon#enter sib2, iclass 15, count 0 2006.201.05:06:26.56#ibcon#flushed, iclass 15, count 0 2006.201.05:06:26.56#ibcon#about to write, iclass 15, count 0 2006.201.05:06:26.56#ibcon#wrote, iclass 15, count 0 2006.201.05:06:26.56#ibcon#about to read 3, iclass 15, count 0 2006.201.05:06:26.58#ibcon#read 3, iclass 15, count 0 2006.201.05:06:26.58#ibcon#about to read 4, iclass 15, count 0 2006.201.05:06:26.58#ibcon#read 4, iclass 15, count 0 2006.201.05:06:26.58#ibcon#about to read 5, iclass 15, count 0 2006.201.05:06:26.58#ibcon#read 5, iclass 15, count 0 2006.201.05:06:26.58#ibcon#about to read 6, iclass 15, count 0 2006.201.05:06:26.58#ibcon#read 6, iclass 15, count 0 2006.201.05:06:26.58#ibcon#end of sib2, iclass 15, count 0 2006.201.05:06:26.58#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:06:26.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:06:26.58#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:06:26.58#ibcon#*before write, iclass 15, count 0 2006.201.05:06:26.58#ibcon#enter sib2, iclass 15, count 0 2006.201.05:06:26.58#ibcon#flushed, iclass 15, count 0 2006.201.05:06:26.58#ibcon#about to write, iclass 15, count 0 2006.201.05:06:26.58#ibcon#wrote, iclass 15, count 0 2006.201.05:06:26.58#ibcon#about to read 3, iclass 15, count 0 2006.201.05:06:26.62#ibcon#read 3, iclass 15, count 0 2006.201.05:06:26.62#ibcon#about to read 4, iclass 15, count 0 2006.201.05:06:26.62#ibcon#read 4, iclass 15, count 0 2006.201.05:06:26.62#ibcon#about to read 5, iclass 15, count 0 2006.201.05:06:26.62#ibcon#read 5, iclass 15, count 0 2006.201.05:06:26.62#ibcon#about to read 6, iclass 15, count 0 2006.201.05:06:26.62#ibcon#read 6, iclass 15, count 0 2006.201.05:06:26.62#ibcon#end of sib2, iclass 15, count 0 2006.201.05:06:26.62#ibcon#*after write, iclass 15, count 0 2006.201.05:06:26.62#ibcon#*before return 0, iclass 15, count 0 2006.201.05:06:26.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:26.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:26.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:06:26.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:06:26.62$vck44/va=5,4 2006.201.05:06:26.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.05:06:26.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.05:06:26.62#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:26.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:26.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:26.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:26.68#ibcon#enter wrdev, iclass 17, count 2 2006.201.05:06:26.68#ibcon#first serial, iclass 17, count 2 2006.201.05:06:26.68#ibcon#enter sib2, iclass 17, count 2 2006.201.05:06:26.68#ibcon#flushed, iclass 17, count 2 2006.201.05:06:26.68#ibcon#about to write, iclass 17, count 2 2006.201.05:06:26.68#ibcon#wrote, iclass 17, count 2 2006.201.05:06:26.68#ibcon#about to read 3, iclass 17, count 2 2006.201.05:06:26.70#ibcon#read 3, iclass 17, count 2 2006.201.05:06:26.70#ibcon#about to read 4, iclass 17, count 2 2006.201.05:06:26.70#ibcon#read 4, iclass 17, count 2 2006.201.05:06:26.70#ibcon#about to read 5, iclass 17, count 2 2006.201.05:06:26.70#ibcon#read 5, iclass 17, count 2 2006.201.05:06:26.70#ibcon#about to read 6, iclass 17, count 2 2006.201.05:06:26.70#ibcon#read 6, iclass 17, count 2 2006.201.05:06:26.70#ibcon#end of sib2, iclass 17, count 2 2006.201.05:06:26.70#ibcon#*mode == 0, iclass 17, count 2 2006.201.05:06:26.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.05:06:26.70#ibcon#[25=AT05-04\r\n] 2006.201.05:06:26.70#ibcon#*before write, iclass 17, count 2 2006.201.05:06:26.70#ibcon#enter sib2, iclass 17, count 2 2006.201.05:06:26.70#ibcon#flushed, iclass 17, count 2 2006.201.05:06:26.70#ibcon#about to write, iclass 17, count 2 2006.201.05:06:26.70#ibcon#wrote, iclass 17, count 2 2006.201.05:06:26.70#ibcon#about to read 3, iclass 17, count 2 2006.201.05:06:26.73#ibcon#read 3, iclass 17, count 2 2006.201.05:06:26.73#ibcon#about to read 4, iclass 17, count 2 2006.201.05:06:26.73#ibcon#read 4, iclass 17, count 2 2006.201.05:06:26.73#ibcon#about to read 5, iclass 17, count 2 2006.201.05:06:26.73#ibcon#read 5, iclass 17, count 2 2006.201.05:06:26.73#ibcon#about to read 6, iclass 17, count 2 2006.201.05:06:26.73#ibcon#read 6, iclass 17, count 2 2006.201.05:06:26.73#ibcon#end of sib2, iclass 17, count 2 2006.201.05:06:26.73#ibcon#*after write, iclass 17, count 2 2006.201.05:06:26.73#ibcon#*before return 0, iclass 17, count 2 2006.201.05:06:26.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:26.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:26.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.05:06:26.73#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:26.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:26.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:26.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:26.85#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:06:26.85#ibcon#first serial, iclass 17, count 0 2006.201.05:06:26.85#ibcon#enter sib2, iclass 17, count 0 2006.201.05:06:26.85#ibcon#flushed, iclass 17, count 0 2006.201.05:06:26.85#ibcon#about to write, iclass 17, count 0 2006.201.05:06:26.85#ibcon#wrote, iclass 17, count 0 2006.201.05:06:26.85#ibcon#about to read 3, iclass 17, count 0 2006.201.05:06:26.87#ibcon#read 3, iclass 17, count 0 2006.201.05:06:26.87#ibcon#about to read 4, iclass 17, count 0 2006.201.05:06:26.87#ibcon#read 4, iclass 17, count 0 2006.201.05:06:26.87#ibcon#about to read 5, iclass 17, count 0 2006.201.05:06:26.87#ibcon#read 5, iclass 17, count 0 2006.201.05:06:26.87#ibcon#about to read 6, iclass 17, count 0 2006.201.05:06:26.87#ibcon#read 6, iclass 17, count 0 2006.201.05:06:26.87#ibcon#end of sib2, iclass 17, count 0 2006.201.05:06:26.87#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:06:26.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:06:26.87#ibcon#[25=USB\r\n] 2006.201.05:06:26.87#ibcon#*before write, iclass 17, count 0 2006.201.05:06:26.87#ibcon#enter sib2, iclass 17, count 0 2006.201.05:06:26.87#ibcon#flushed, iclass 17, count 0 2006.201.05:06:26.87#ibcon#about to write, iclass 17, count 0 2006.201.05:06:26.87#ibcon#wrote, iclass 17, count 0 2006.201.05:06:26.87#ibcon#about to read 3, iclass 17, count 0 2006.201.05:06:26.90#ibcon#read 3, iclass 17, count 0 2006.201.05:06:26.90#ibcon#about to read 4, iclass 17, count 0 2006.201.05:06:26.90#ibcon#read 4, iclass 17, count 0 2006.201.05:06:26.90#ibcon#about to read 5, iclass 17, count 0 2006.201.05:06:26.90#ibcon#read 5, iclass 17, count 0 2006.201.05:06:26.90#ibcon#about to read 6, iclass 17, count 0 2006.201.05:06:26.90#ibcon#read 6, iclass 17, count 0 2006.201.05:06:26.90#ibcon#end of sib2, iclass 17, count 0 2006.201.05:06:26.90#ibcon#*after write, iclass 17, count 0 2006.201.05:06:26.90#ibcon#*before return 0, iclass 17, count 0 2006.201.05:06:26.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:26.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:26.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:06:26.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:06:26.90$vck44/valo=6,814.99 2006.201.05:06:26.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.05:06:26.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.05:06:26.90#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:26.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:26.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:26.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:26.90#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:06:26.90#ibcon#first serial, iclass 19, count 0 2006.201.05:06:26.90#ibcon#enter sib2, iclass 19, count 0 2006.201.05:06:26.90#ibcon#flushed, iclass 19, count 0 2006.201.05:06:26.90#ibcon#about to write, iclass 19, count 0 2006.201.05:06:26.90#ibcon#wrote, iclass 19, count 0 2006.201.05:06:26.90#ibcon#about to read 3, iclass 19, count 0 2006.201.05:06:26.92#ibcon#read 3, iclass 19, count 0 2006.201.05:06:26.92#ibcon#about to read 4, iclass 19, count 0 2006.201.05:06:26.92#ibcon#read 4, iclass 19, count 0 2006.201.05:06:26.92#ibcon#about to read 5, iclass 19, count 0 2006.201.05:06:26.92#ibcon#read 5, iclass 19, count 0 2006.201.05:06:26.92#ibcon#about to read 6, iclass 19, count 0 2006.201.05:06:26.92#ibcon#read 6, iclass 19, count 0 2006.201.05:06:26.92#ibcon#end of sib2, iclass 19, count 0 2006.201.05:06:26.92#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:06:26.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:06:26.92#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:06:26.92#ibcon#*before write, iclass 19, count 0 2006.201.05:06:26.92#ibcon#enter sib2, iclass 19, count 0 2006.201.05:06:26.92#ibcon#flushed, iclass 19, count 0 2006.201.05:06:26.92#ibcon#about to write, iclass 19, count 0 2006.201.05:06:26.92#ibcon#wrote, iclass 19, count 0 2006.201.05:06:26.92#ibcon#about to read 3, iclass 19, count 0 2006.201.05:06:26.96#ibcon#read 3, iclass 19, count 0 2006.201.05:06:26.96#ibcon#about to read 4, iclass 19, count 0 2006.201.05:06:26.96#ibcon#read 4, iclass 19, count 0 2006.201.05:06:26.96#ibcon#about to read 5, iclass 19, count 0 2006.201.05:06:26.96#ibcon#read 5, iclass 19, count 0 2006.201.05:06:26.96#ibcon#about to read 6, iclass 19, count 0 2006.201.05:06:26.96#ibcon#read 6, iclass 19, count 0 2006.201.05:06:26.96#ibcon#end of sib2, iclass 19, count 0 2006.201.05:06:26.96#ibcon#*after write, iclass 19, count 0 2006.201.05:06:26.96#ibcon#*before return 0, iclass 19, count 0 2006.201.05:06:26.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:26.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:26.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:06:26.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:06:26.96$vck44/va=6,5 2006.201.05:06:26.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.05:06:26.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.05:06:26.96#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:26.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:27.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:27.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:27.02#ibcon#enter wrdev, iclass 21, count 2 2006.201.05:06:27.02#ibcon#first serial, iclass 21, count 2 2006.201.05:06:27.02#ibcon#enter sib2, iclass 21, count 2 2006.201.05:06:27.02#ibcon#flushed, iclass 21, count 2 2006.201.05:06:27.02#ibcon#about to write, iclass 21, count 2 2006.201.05:06:27.02#ibcon#wrote, iclass 21, count 2 2006.201.05:06:27.02#ibcon#about to read 3, iclass 21, count 2 2006.201.05:06:27.04#ibcon#read 3, iclass 21, count 2 2006.201.05:06:27.04#ibcon#about to read 4, iclass 21, count 2 2006.201.05:06:27.04#ibcon#read 4, iclass 21, count 2 2006.201.05:06:27.04#ibcon#about to read 5, iclass 21, count 2 2006.201.05:06:27.04#ibcon#read 5, iclass 21, count 2 2006.201.05:06:27.04#ibcon#about to read 6, iclass 21, count 2 2006.201.05:06:27.04#ibcon#read 6, iclass 21, count 2 2006.201.05:06:27.04#ibcon#end of sib2, iclass 21, count 2 2006.201.05:06:27.04#ibcon#*mode == 0, iclass 21, count 2 2006.201.05:06:27.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.05:06:27.04#ibcon#[25=AT06-05\r\n] 2006.201.05:06:27.04#ibcon#*before write, iclass 21, count 2 2006.201.05:06:27.04#ibcon#enter sib2, iclass 21, count 2 2006.201.05:06:27.04#ibcon#flushed, iclass 21, count 2 2006.201.05:06:27.04#ibcon#about to write, iclass 21, count 2 2006.201.05:06:27.04#ibcon#wrote, iclass 21, count 2 2006.201.05:06:27.04#ibcon#about to read 3, iclass 21, count 2 2006.201.05:06:27.07#ibcon#read 3, iclass 21, count 2 2006.201.05:06:27.07#ibcon#about to read 4, iclass 21, count 2 2006.201.05:06:27.07#ibcon#read 4, iclass 21, count 2 2006.201.05:06:27.07#ibcon#about to read 5, iclass 21, count 2 2006.201.05:06:27.07#ibcon#read 5, iclass 21, count 2 2006.201.05:06:27.07#ibcon#about to read 6, iclass 21, count 2 2006.201.05:06:27.07#ibcon#read 6, iclass 21, count 2 2006.201.05:06:27.07#ibcon#end of sib2, iclass 21, count 2 2006.201.05:06:27.07#ibcon#*after write, iclass 21, count 2 2006.201.05:06:27.07#ibcon#*before return 0, iclass 21, count 2 2006.201.05:06:27.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:27.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:27.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.05:06:27.07#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:27.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:27.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:27.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:27.19#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:06:27.19#ibcon#first serial, iclass 21, count 0 2006.201.05:06:27.19#ibcon#enter sib2, iclass 21, count 0 2006.201.05:06:27.19#ibcon#flushed, iclass 21, count 0 2006.201.05:06:27.19#ibcon#about to write, iclass 21, count 0 2006.201.05:06:27.19#ibcon#wrote, iclass 21, count 0 2006.201.05:06:27.19#ibcon#about to read 3, iclass 21, count 0 2006.201.05:06:27.21#ibcon#read 3, iclass 21, count 0 2006.201.05:06:27.21#ibcon#about to read 4, iclass 21, count 0 2006.201.05:06:27.21#ibcon#read 4, iclass 21, count 0 2006.201.05:06:27.21#ibcon#about to read 5, iclass 21, count 0 2006.201.05:06:27.21#ibcon#read 5, iclass 21, count 0 2006.201.05:06:27.21#ibcon#about to read 6, iclass 21, count 0 2006.201.05:06:27.21#ibcon#read 6, iclass 21, count 0 2006.201.05:06:27.21#ibcon#end of sib2, iclass 21, count 0 2006.201.05:06:27.21#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:06:27.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:06:27.21#ibcon#[25=USB\r\n] 2006.201.05:06:27.21#ibcon#*before write, iclass 21, count 0 2006.201.05:06:27.21#ibcon#enter sib2, iclass 21, count 0 2006.201.05:06:27.21#ibcon#flushed, iclass 21, count 0 2006.201.05:06:27.21#ibcon#about to write, iclass 21, count 0 2006.201.05:06:27.21#ibcon#wrote, iclass 21, count 0 2006.201.05:06:27.21#ibcon#about to read 3, iclass 21, count 0 2006.201.05:06:27.24#ibcon#read 3, iclass 21, count 0 2006.201.05:06:27.24#ibcon#about to read 4, iclass 21, count 0 2006.201.05:06:27.24#ibcon#read 4, iclass 21, count 0 2006.201.05:06:27.24#ibcon#about to read 5, iclass 21, count 0 2006.201.05:06:27.24#ibcon#read 5, iclass 21, count 0 2006.201.05:06:27.24#ibcon#about to read 6, iclass 21, count 0 2006.201.05:06:27.24#ibcon#read 6, iclass 21, count 0 2006.201.05:06:27.24#ibcon#end of sib2, iclass 21, count 0 2006.201.05:06:27.24#ibcon#*after write, iclass 21, count 0 2006.201.05:06:27.24#ibcon#*before return 0, iclass 21, count 0 2006.201.05:06:27.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:27.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:27.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:06:27.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:06:27.24$vck44/valo=7,864.99 2006.201.05:06:27.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.05:06:27.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.05:06:27.24#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:27.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:27.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:27.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:27.24#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:06:27.24#ibcon#first serial, iclass 23, count 0 2006.201.05:06:27.24#ibcon#enter sib2, iclass 23, count 0 2006.201.05:06:27.24#ibcon#flushed, iclass 23, count 0 2006.201.05:06:27.24#ibcon#about to write, iclass 23, count 0 2006.201.05:06:27.24#ibcon#wrote, iclass 23, count 0 2006.201.05:06:27.24#ibcon#about to read 3, iclass 23, count 0 2006.201.05:06:27.26#ibcon#read 3, iclass 23, count 0 2006.201.05:06:27.26#ibcon#about to read 4, iclass 23, count 0 2006.201.05:06:27.26#ibcon#read 4, iclass 23, count 0 2006.201.05:06:27.26#ibcon#about to read 5, iclass 23, count 0 2006.201.05:06:27.26#ibcon#read 5, iclass 23, count 0 2006.201.05:06:27.26#ibcon#about to read 6, iclass 23, count 0 2006.201.05:06:27.26#ibcon#read 6, iclass 23, count 0 2006.201.05:06:27.26#ibcon#end of sib2, iclass 23, count 0 2006.201.05:06:27.26#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:06:27.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:06:27.26#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:06:27.26#ibcon#*before write, iclass 23, count 0 2006.201.05:06:27.26#ibcon#enter sib2, iclass 23, count 0 2006.201.05:06:27.26#ibcon#flushed, iclass 23, count 0 2006.201.05:06:27.26#ibcon#about to write, iclass 23, count 0 2006.201.05:06:27.26#ibcon#wrote, iclass 23, count 0 2006.201.05:06:27.26#ibcon#about to read 3, iclass 23, count 0 2006.201.05:06:27.30#ibcon#read 3, iclass 23, count 0 2006.201.05:06:27.30#ibcon#about to read 4, iclass 23, count 0 2006.201.05:06:27.30#ibcon#read 4, iclass 23, count 0 2006.201.05:06:27.30#ibcon#about to read 5, iclass 23, count 0 2006.201.05:06:27.30#ibcon#read 5, iclass 23, count 0 2006.201.05:06:27.30#ibcon#about to read 6, iclass 23, count 0 2006.201.05:06:27.30#ibcon#read 6, iclass 23, count 0 2006.201.05:06:27.30#ibcon#end of sib2, iclass 23, count 0 2006.201.05:06:27.30#ibcon#*after write, iclass 23, count 0 2006.201.05:06:27.30#ibcon#*before return 0, iclass 23, count 0 2006.201.05:06:27.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:27.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:27.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:06:27.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:06:27.30$vck44/va=7,5 2006.201.05:06:27.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.05:06:27.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.05:06:27.30#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:27.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:27.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:27.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:27.36#ibcon#enter wrdev, iclass 25, count 2 2006.201.05:06:27.36#ibcon#first serial, iclass 25, count 2 2006.201.05:06:27.36#ibcon#enter sib2, iclass 25, count 2 2006.201.05:06:27.36#ibcon#flushed, iclass 25, count 2 2006.201.05:06:27.36#ibcon#about to write, iclass 25, count 2 2006.201.05:06:27.36#ibcon#wrote, iclass 25, count 2 2006.201.05:06:27.36#ibcon#about to read 3, iclass 25, count 2 2006.201.05:06:27.38#ibcon#read 3, iclass 25, count 2 2006.201.05:06:27.38#ibcon#about to read 4, iclass 25, count 2 2006.201.05:06:27.38#ibcon#read 4, iclass 25, count 2 2006.201.05:06:27.38#ibcon#about to read 5, iclass 25, count 2 2006.201.05:06:27.38#ibcon#read 5, iclass 25, count 2 2006.201.05:06:27.38#ibcon#about to read 6, iclass 25, count 2 2006.201.05:06:27.38#ibcon#read 6, iclass 25, count 2 2006.201.05:06:27.38#ibcon#end of sib2, iclass 25, count 2 2006.201.05:06:27.38#ibcon#*mode == 0, iclass 25, count 2 2006.201.05:06:27.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.05:06:27.38#ibcon#[25=AT07-05\r\n] 2006.201.05:06:27.38#ibcon#*before write, iclass 25, count 2 2006.201.05:06:27.38#ibcon#enter sib2, iclass 25, count 2 2006.201.05:06:27.38#ibcon#flushed, iclass 25, count 2 2006.201.05:06:27.38#ibcon#about to write, iclass 25, count 2 2006.201.05:06:27.38#ibcon#wrote, iclass 25, count 2 2006.201.05:06:27.38#ibcon#about to read 3, iclass 25, count 2 2006.201.05:06:27.41#ibcon#read 3, iclass 25, count 2 2006.201.05:06:27.41#ibcon#about to read 4, iclass 25, count 2 2006.201.05:06:27.41#ibcon#read 4, iclass 25, count 2 2006.201.05:06:27.41#ibcon#about to read 5, iclass 25, count 2 2006.201.05:06:27.41#ibcon#read 5, iclass 25, count 2 2006.201.05:06:27.41#ibcon#about to read 6, iclass 25, count 2 2006.201.05:06:27.41#ibcon#read 6, iclass 25, count 2 2006.201.05:06:27.41#ibcon#end of sib2, iclass 25, count 2 2006.201.05:06:27.41#ibcon#*after write, iclass 25, count 2 2006.201.05:06:27.41#ibcon#*before return 0, iclass 25, count 2 2006.201.05:06:27.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:27.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:27.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.05:06:27.41#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:27.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:27.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:27.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:27.53#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:06:27.53#ibcon#first serial, iclass 25, count 0 2006.201.05:06:27.53#ibcon#enter sib2, iclass 25, count 0 2006.201.05:06:27.53#ibcon#flushed, iclass 25, count 0 2006.201.05:06:27.53#ibcon#about to write, iclass 25, count 0 2006.201.05:06:27.53#ibcon#wrote, iclass 25, count 0 2006.201.05:06:27.53#ibcon#about to read 3, iclass 25, count 0 2006.201.05:06:27.55#ibcon#read 3, iclass 25, count 0 2006.201.05:06:27.55#ibcon#about to read 4, iclass 25, count 0 2006.201.05:06:27.55#ibcon#read 4, iclass 25, count 0 2006.201.05:06:27.55#ibcon#about to read 5, iclass 25, count 0 2006.201.05:06:27.55#ibcon#read 5, iclass 25, count 0 2006.201.05:06:27.55#ibcon#about to read 6, iclass 25, count 0 2006.201.05:06:27.55#ibcon#read 6, iclass 25, count 0 2006.201.05:06:27.55#ibcon#end of sib2, iclass 25, count 0 2006.201.05:06:27.55#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:06:27.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:06:27.55#ibcon#[25=USB\r\n] 2006.201.05:06:27.55#ibcon#*before write, iclass 25, count 0 2006.201.05:06:27.55#ibcon#enter sib2, iclass 25, count 0 2006.201.05:06:27.55#ibcon#flushed, iclass 25, count 0 2006.201.05:06:27.55#ibcon#about to write, iclass 25, count 0 2006.201.05:06:27.55#ibcon#wrote, iclass 25, count 0 2006.201.05:06:27.55#ibcon#about to read 3, iclass 25, count 0 2006.201.05:06:27.58#ibcon#read 3, iclass 25, count 0 2006.201.05:06:27.58#ibcon#about to read 4, iclass 25, count 0 2006.201.05:06:27.58#ibcon#read 4, iclass 25, count 0 2006.201.05:06:27.58#ibcon#about to read 5, iclass 25, count 0 2006.201.05:06:27.58#ibcon#read 5, iclass 25, count 0 2006.201.05:06:27.58#ibcon#about to read 6, iclass 25, count 0 2006.201.05:06:27.58#ibcon#read 6, iclass 25, count 0 2006.201.05:06:27.58#ibcon#end of sib2, iclass 25, count 0 2006.201.05:06:27.58#ibcon#*after write, iclass 25, count 0 2006.201.05:06:27.58#ibcon#*before return 0, iclass 25, count 0 2006.201.05:06:27.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:27.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:27.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:06:27.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:06:27.58$vck44/valo=8,884.99 2006.201.05:06:27.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.05:06:27.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.05:06:27.58#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:27.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:27.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:27.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:27.58#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:06:27.58#ibcon#first serial, iclass 27, count 0 2006.201.05:06:27.58#ibcon#enter sib2, iclass 27, count 0 2006.201.05:06:27.58#ibcon#flushed, iclass 27, count 0 2006.201.05:06:27.58#ibcon#about to write, iclass 27, count 0 2006.201.05:06:27.58#ibcon#wrote, iclass 27, count 0 2006.201.05:06:27.58#ibcon#about to read 3, iclass 27, count 0 2006.201.05:06:27.60#ibcon#read 3, iclass 27, count 0 2006.201.05:06:27.60#ibcon#about to read 4, iclass 27, count 0 2006.201.05:06:27.60#ibcon#read 4, iclass 27, count 0 2006.201.05:06:27.60#ibcon#about to read 5, iclass 27, count 0 2006.201.05:06:27.60#ibcon#read 5, iclass 27, count 0 2006.201.05:06:27.60#ibcon#about to read 6, iclass 27, count 0 2006.201.05:06:27.60#ibcon#read 6, iclass 27, count 0 2006.201.05:06:27.60#ibcon#end of sib2, iclass 27, count 0 2006.201.05:06:27.60#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:06:27.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:06:27.60#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:06:27.60#ibcon#*before write, iclass 27, count 0 2006.201.05:06:27.60#ibcon#enter sib2, iclass 27, count 0 2006.201.05:06:27.60#ibcon#flushed, iclass 27, count 0 2006.201.05:06:27.60#ibcon#about to write, iclass 27, count 0 2006.201.05:06:27.60#ibcon#wrote, iclass 27, count 0 2006.201.05:06:27.60#ibcon#about to read 3, iclass 27, count 0 2006.201.05:06:27.64#ibcon#read 3, iclass 27, count 0 2006.201.05:06:27.64#ibcon#about to read 4, iclass 27, count 0 2006.201.05:06:27.64#ibcon#read 4, iclass 27, count 0 2006.201.05:06:27.64#ibcon#about to read 5, iclass 27, count 0 2006.201.05:06:27.64#ibcon#read 5, iclass 27, count 0 2006.201.05:06:27.64#ibcon#about to read 6, iclass 27, count 0 2006.201.05:06:27.64#ibcon#read 6, iclass 27, count 0 2006.201.05:06:27.64#ibcon#end of sib2, iclass 27, count 0 2006.201.05:06:27.64#ibcon#*after write, iclass 27, count 0 2006.201.05:06:27.64#ibcon#*before return 0, iclass 27, count 0 2006.201.05:06:27.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:27.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:27.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:06:27.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:06:27.64$vck44/va=8,4 2006.201.05:06:27.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.05:06:27.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.05:06:27.64#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:27.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:06:27.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:06:27.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:06:27.70#ibcon#enter wrdev, iclass 29, count 2 2006.201.05:06:27.70#ibcon#first serial, iclass 29, count 2 2006.201.05:06:27.70#ibcon#enter sib2, iclass 29, count 2 2006.201.05:06:27.70#ibcon#flushed, iclass 29, count 2 2006.201.05:06:27.70#ibcon#about to write, iclass 29, count 2 2006.201.05:06:27.70#ibcon#wrote, iclass 29, count 2 2006.201.05:06:27.70#ibcon#about to read 3, iclass 29, count 2 2006.201.05:06:27.72#ibcon#read 3, iclass 29, count 2 2006.201.05:06:27.72#ibcon#about to read 4, iclass 29, count 2 2006.201.05:06:27.72#ibcon#read 4, iclass 29, count 2 2006.201.05:06:27.72#ibcon#about to read 5, iclass 29, count 2 2006.201.05:06:27.72#ibcon#read 5, iclass 29, count 2 2006.201.05:06:27.72#ibcon#about to read 6, iclass 29, count 2 2006.201.05:06:27.72#ibcon#read 6, iclass 29, count 2 2006.201.05:06:27.72#ibcon#end of sib2, iclass 29, count 2 2006.201.05:06:27.72#ibcon#*mode == 0, iclass 29, count 2 2006.201.05:06:27.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.05:06:27.72#ibcon#[25=AT08-04\r\n] 2006.201.05:06:27.72#ibcon#*before write, iclass 29, count 2 2006.201.05:06:27.72#ibcon#enter sib2, iclass 29, count 2 2006.201.05:06:27.72#ibcon#flushed, iclass 29, count 2 2006.201.05:06:27.72#ibcon#about to write, iclass 29, count 2 2006.201.05:06:27.72#ibcon#wrote, iclass 29, count 2 2006.201.05:06:27.72#ibcon#about to read 3, iclass 29, count 2 2006.201.05:06:27.75#ibcon#read 3, iclass 29, count 2 2006.201.05:06:27.75#ibcon#about to read 4, iclass 29, count 2 2006.201.05:06:27.75#ibcon#read 4, iclass 29, count 2 2006.201.05:06:27.75#ibcon#about to read 5, iclass 29, count 2 2006.201.05:06:27.75#ibcon#read 5, iclass 29, count 2 2006.201.05:06:27.75#ibcon#about to read 6, iclass 29, count 2 2006.201.05:06:27.75#ibcon#read 6, iclass 29, count 2 2006.201.05:06:27.75#ibcon#end of sib2, iclass 29, count 2 2006.201.05:06:27.75#ibcon#*after write, iclass 29, count 2 2006.201.05:06:27.75#ibcon#*before return 0, iclass 29, count 2 2006.201.05:06:27.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:06:27.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:06:27.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.05:06:27.75#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:27.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:06:27.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:06:27.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:06:27.87#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:06:27.87#ibcon#first serial, iclass 29, count 0 2006.201.05:06:27.87#ibcon#enter sib2, iclass 29, count 0 2006.201.05:06:27.87#ibcon#flushed, iclass 29, count 0 2006.201.05:06:27.87#ibcon#about to write, iclass 29, count 0 2006.201.05:06:27.87#ibcon#wrote, iclass 29, count 0 2006.201.05:06:27.87#ibcon#about to read 3, iclass 29, count 0 2006.201.05:06:27.89#ibcon#read 3, iclass 29, count 0 2006.201.05:06:27.89#ibcon#about to read 4, iclass 29, count 0 2006.201.05:06:27.89#ibcon#read 4, iclass 29, count 0 2006.201.05:06:27.89#ibcon#about to read 5, iclass 29, count 0 2006.201.05:06:27.89#ibcon#read 5, iclass 29, count 0 2006.201.05:06:27.89#ibcon#about to read 6, iclass 29, count 0 2006.201.05:06:27.89#ibcon#read 6, iclass 29, count 0 2006.201.05:06:27.89#ibcon#end of sib2, iclass 29, count 0 2006.201.05:06:27.89#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:06:27.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:06:27.89#ibcon#[25=USB\r\n] 2006.201.05:06:27.89#ibcon#*before write, iclass 29, count 0 2006.201.05:06:27.89#ibcon#enter sib2, iclass 29, count 0 2006.201.05:06:27.89#ibcon#flushed, iclass 29, count 0 2006.201.05:06:27.89#ibcon#about to write, iclass 29, count 0 2006.201.05:06:27.89#ibcon#wrote, iclass 29, count 0 2006.201.05:06:27.89#ibcon#about to read 3, iclass 29, count 0 2006.201.05:06:27.92#ibcon#read 3, iclass 29, count 0 2006.201.05:06:27.92#ibcon#about to read 4, iclass 29, count 0 2006.201.05:06:27.92#ibcon#read 4, iclass 29, count 0 2006.201.05:06:27.92#ibcon#about to read 5, iclass 29, count 0 2006.201.05:06:27.92#ibcon#read 5, iclass 29, count 0 2006.201.05:06:27.92#ibcon#about to read 6, iclass 29, count 0 2006.201.05:06:27.92#ibcon#read 6, iclass 29, count 0 2006.201.05:06:27.92#ibcon#end of sib2, iclass 29, count 0 2006.201.05:06:27.92#ibcon#*after write, iclass 29, count 0 2006.201.05:06:27.92#ibcon#*before return 0, iclass 29, count 0 2006.201.05:06:27.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:06:27.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:06:27.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:06:27.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:06:27.92$vck44/vblo=1,629.99 2006.201.05:06:27.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.05:06:27.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.05:06:27.92#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:27.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:06:27.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:06:27.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:06:27.92#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:06:27.92#ibcon#first serial, iclass 31, count 0 2006.201.05:06:27.92#ibcon#enter sib2, iclass 31, count 0 2006.201.05:06:27.92#ibcon#flushed, iclass 31, count 0 2006.201.05:06:27.92#ibcon#about to write, iclass 31, count 0 2006.201.05:06:27.92#ibcon#wrote, iclass 31, count 0 2006.201.05:06:27.92#ibcon#about to read 3, iclass 31, count 0 2006.201.05:06:27.94#ibcon#read 3, iclass 31, count 0 2006.201.05:06:27.94#ibcon#about to read 4, iclass 31, count 0 2006.201.05:06:27.94#ibcon#read 4, iclass 31, count 0 2006.201.05:06:27.94#ibcon#about to read 5, iclass 31, count 0 2006.201.05:06:27.94#ibcon#read 5, iclass 31, count 0 2006.201.05:06:27.94#ibcon#about to read 6, iclass 31, count 0 2006.201.05:06:27.94#ibcon#read 6, iclass 31, count 0 2006.201.05:06:27.94#ibcon#end of sib2, iclass 31, count 0 2006.201.05:06:27.94#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:06:27.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:06:27.94#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:06:27.94#ibcon#*before write, iclass 31, count 0 2006.201.05:06:27.94#ibcon#enter sib2, iclass 31, count 0 2006.201.05:06:27.94#ibcon#flushed, iclass 31, count 0 2006.201.05:06:27.94#ibcon#about to write, iclass 31, count 0 2006.201.05:06:27.94#ibcon#wrote, iclass 31, count 0 2006.201.05:06:27.94#ibcon#about to read 3, iclass 31, count 0 2006.201.05:06:27.98#ibcon#read 3, iclass 31, count 0 2006.201.05:06:27.98#ibcon#about to read 4, iclass 31, count 0 2006.201.05:06:27.98#ibcon#read 4, iclass 31, count 0 2006.201.05:06:27.98#ibcon#about to read 5, iclass 31, count 0 2006.201.05:06:27.98#ibcon#read 5, iclass 31, count 0 2006.201.05:06:27.98#ibcon#about to read 6, iclass 31, count 0 2006.201.05:06:27.98#ibcon#read 6, iclass 31, count 0 2006.201.05:06:27.98#ibcon#end of sib2, iclass 31, count 0 2006.201.05:06:27.98#ibcon#*after write, iclass 31, count 0 2006.201.05:06:27.98#ibcon#*before return 0, iclass 31, count 0 2006.201.05:06:27.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:06:27.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:06:27.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:06:27.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:06:27.98$vck44/vb=1,4 2006.201.05:06:27.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.05:06:27.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.05:06:27.98#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:27.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:06:27.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:06:27.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:06:27.98#ibcon#enter wrdev, iclass 33, count 2 2006.201.05:06:27.98#ibcon#first serial, iclass 33, count 2 2006.201.05:06:27.98#ibcon#enter sib2, iclass 33, count 2 2006.201.05:06:27.98#ibcon#flushed, iclass 33, count 2 2006.201.05:06:27.98#ibcon#about to write, iclass 33, count 2 2006.201.05:06:27.98#ibcon#wrote, iclass 33, count 2 2006.201.05:06:27.98#ibcon#about to read 3, iclass 33, count 2 2006.201.05:06:28.00#ibcon#read 3, iclass 33, count 2 2006.201.05:06:28.00#ibcon#about to read 4, iclass 33, count 2 2006.201.05:06:28.00#ibcon#read 4, iclass 33, count 2 2006.201.05:06:28.00#ibcon#about to read 5, iclass 33, count 2 2006.201.05:06:28.00#ibcon#read 5, iclass 33, count 2 2006.201.05:06:28.00#ibcon#about to read 6, iclass 33, count 2 2006.201.05:06:28.00#ibcon#read 6, iclass 33, count 2 2006.201.05:06:28.00#ibcon#end of sib2, iclass 33, count 2 2006.201.05:06:28.00#ibcon#*mode == 0, iclass 33, count 2 2006.201.05:06:28.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.05:06:28.00#ibcon#[27=AT01-04\r\n] 2006.201.05:06:28.00#ibcon#*before write, iclass 33, count 2 2006.201.05:06:28.00#ibcon#enter sib2, iclass 33, count 2 2006.201.05:06:28.00#ibcon#flushed, iclass 33, count 2 2006.201.05:06:28.00#ibcon#about to write, iclass 33, count 2 2006.201.05:06:28.00#ibcon#wrote, iclass 33, count 2 2006.201.05:06:28.00#ibcon#about to read 3, iclass 33, count 2 2006.201.05:06:28.03#ibcon#read 3, iclass 33, count 2 2006.201.05:06:28.03#ibcon#about to read 4, iclass 33, count 2 2006.201.05:06:28.03#ibcon#read 4, iclass 33, count 2 2006.201.05:06:28.03#ibcon#about to read 5, iclass 33, count 2 2006.201.05:06:28.03#ibcon#read 5, iclass 33, count 2 2006.201.05:06:28.03#ibcon#about to read 6, iclass 33, count 2 2006.201.05:06:28.03#ibcon#read 6, iclass 33, count 2 2006.201.05:06:28.03#ibcon#end of sib2, iclass 33, count 2 2006.201.05:06:28.03#ibcon#*after write, iclass 33, count 2 2006.201.05:06:28.03#ibcon#*before return 0, iclass 33, count 2 2006.201.05:06:28.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:06:28.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:06:28.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.05:06:28.03#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:28.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:06:28.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:06:28.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:06:28.15#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:06:28.15#ibcon#first serial, iclass 33, count 0 2006.201.05:06:28.15#ibcon#enter sib2, iclass 33, count 0 2006.201.05:06:28.15#ibcon#flushed, iclass 33, count 0 2006.201.05:06:28.15#ibcon#about to write, iclass 33, count 0 2006.201.05:06:28.15#ibcon#wrote, iclass 33, count 0 2006.201.05:06:28.15#ibcon#about to read 3, iclass 33, count 0 2006.201.05:06:28.17#ibcon#read 3, iclass 33, count 0 2006.201.05:06:28.17#ibcon#about to read 4, iclass 33, count 0 2006.201.05:06:28.17#ibcon#read 4, iclass 33, count 0 2006.201.05:06:28.17#ibcon#about to read 5, iclass 33, count 0 2006.201.05:06:28.17#ibcon#read 5, iclass 33, count 0 2006.201.05:06:28.17#ibcon#about to read 6, iclass 33, count 0 2006.201.05:06:28.17#ibcon#read 6, iclass 33, count 0 2006.201.05:06:28.17#ibcon#end of sib2, iclass 33, count 0 2006.201.05:06:28.17#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:06:28.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:06:28.17#ibcon#[27=USB\r\n] 2006.201.05:06:28.17#ibcon#*before write, iclass 33, count 0 2006.201.05:06:28.17#ibcon#enter sib2, iclass 33, count 0 2006.201.05:06:28.17#ibcon#flushed, iclass 33, count 0 2006.201.05:06:28.17#ibcon#about to write, iclass 33, count 0 2006.201.05:06:28.17#ibcon#wrote, iclass 33, count 0 2006.201.05:06:28.17#ibcon#about to read 3, iclass 33, count 0 2006.201.05:06:28.20#ibcon#read 3, iclass 33, count 0 2006.201.05:06:28.20#ibcon#about to read 4, iclass 33, count 0 2006.201.05:06:28.20#ibcon#read 4, iclass 33, count 0 2006.201.05:06:28.20#ibcon#about to read 5, iclass 33, count 0 2006.201.05:06:28.20#ibcon#read 5, iclass 33, count 0 2006.201.05:06:28.20#ibcon#about to read 6, iclass 33, count 0 2006.201.05:06:28.20#ibcon#read 6, iclass 33, count 0 2006.201.05:06:28.20#ibcon#end of sib2, iclass 33, count 0 2006.201.05:06:28.20#ibcon#*after write, iclass 33, count 0 2006.201.05:06:28.20#ibcon#*before return 0, iclass 33, count 0 2006.201.05:06:28.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:06:28.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:06:28.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:06:28.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:06:28.20$vck44/vblo=2,634.99 2006.201.05:06:28.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.05:06:28.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.05:06:28.20#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:28.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:28.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:28.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:28.20#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:06:28.20#ibcon#first serial, iclass 35, count 0 2006.201.05:06:28.20#ibcon#enter sib2, iclass 35, count 0 2006.201.05:06:28.20#ibcon#flushed, iclass 35, count 0 2006.201.05:06:28.20#ibcon#about to write, iclass 35, count 0 2006.201.05:06:28.20#ibcon#wrote, iclass 35, count 0 2006.201.05:06:28.20#ibcon#about to read 3, iclass 35, count 0 2006.201.05:06:28.22#ibcon#read 3, iclass 35, count 0 2006.201.05:06:28.22#ibcon#about to read 4, iclass 35, count 0 2006.201.05:06:28.22#ibcon#read 4, iclass 35, count 0 2006.201.05:06:28.22#ibcon#about to read 5, iclass 35, count 0 2006.201.05:06:28.22#ibcon#read 5, iclass 35, count 0 2006.201.05:06:28.22#ibcon#about to read 6, iclass 35, count 0 2006.201.05:06:28.22#ibcon#read 6, iclass 35, count 0 2006.201.05:06:28.22#ibcon#end of sib2, iclass 35, count 0 2006.201.05:06:28.22#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:06:28.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:06:28.22#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:06:28.22#ibcon#*before write, iclass 35, count 0 2006.201.05:06:28.22#ibcon#enter sib2, iclass 35, count 0 2006.201.05:06:28.22#ibcon#flushed, iclass 35, count 0 2006.201.05:06:28.22#ibcon#about to write, iclass 35, count 0 2006.201.05:06:28.22#ibcon#wrote, iclass 35, count 0 2006.201.05:06:28.22#ibcon#about to read 3, iclass 35, count 0 2006.201.05:06:28.26#ibcon#read 3, iclass 35, count 0 2006.201.05:06:28.26#ibcon#about to read 4, iclass 35, count 0 2006.201.05:06:28.26#ibcon#read 4, iclass 35, count 0 2006.201.05:06:28.26#ibcon#about to read 5, iclass 35, count 0 2006.201.05:06:28.26#ibcon#read 5, iclass 35, count 0 2006.201.05:06:28.26#ibcon#about to read 6, iclass 35, count 0 2006.201.05:06:28.26#ibcon#read 6, iclass 35, count 0 2006.201.05:06:28.26#ibcon#end of sib2, iclass 35, count 0 2006.201.05:06:28.26#ibcon#*after write, iclass 35, count 0 2006.201.05:06:28.26#ibcon#*before return 0, iclass 35, count 0 2006.201.05:06:28.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:28.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:06:28.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:06:28.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:06:28.26$vck44/vb=2,5 2006.201.05:06:28.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.05:06:28.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.05:06:28.26#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:28.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:28.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:28.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:28.32#ibcon#enter wrdev, iclass 37, count 2 2006.201.05:06:28.32#ibcon#first serial, iclass 37, count 2 2006.201.05:06:28.32#ibcon#enter sib2, iclass 37, count 2 2006.201.05:06:28.32#ibcon#flushed, iclass 37, count 2 2006.201.05:06:28.32#ibcon#about to write, iclass 37, count 2 2006.201.05:06:28.32#ibcon#wrote, iclass 37, count 2 2006.201.05:06:28.32#ibcon#about to read 3, iclass 37, count 2 2006.201.05:06:28.34#ibcon#read 3, iclass 37, count 2 2006.201.05:06:28.34#ibcon#about to read 4, iclass 37, count 2 2006.201.05:06:28.34#ibcon#read 4, iclass 37, count 2 2006.201.05:06:28.34#ibcon#about to read 5, iclass 37, count 2 2006.201.05:06:28.34#ibcon#read 5, iclass 37, count 2 2006.201.05:06:28.34#ibcon#about to read 6, iclass 37, count 2 2006.201.05:06:28.34#ibcon#read 6, iclass 37, count 2 2006.201.05:06:28.34#ibcon#end of sib2, iclass 37, count 2 2006.201.05:06:28.34#ibcon#*mode == 0, iclass 37, count 2 2006.201.05:06:28.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.05:06:28.34#ibcon#[27=AT02-05\r\n] 2006.201.05:06:28.34#ibcon#*before write, iclass 37, count 2 2006.201.05:06:28.34#ibcon#enter sib2, iclass 37, count 2 2006.201.05:06:28.34#ibcon#flushed, iclass 37, count 2 2006.201.05:06:28.34#ibcon#about to write, iclass 37, count 2 2006.201.05:06:28.34#ibcon#wrote, iclass 37, count 2 2006.201.05:06:28.34#ibcon#about to read 3, iclass 37, count 2 2006.201.05:06:28.37#ibcon#read 3, iclass 37, count 2 2006.201.05:06:28.37#ibcon#about to read 4, iclass 37, count 2 2006.201.05:06:28.37#ibcon#read 4, iclass 37, count 2 2006.201.05:06:28.37#ibcon#about to read 5, iclass 37, count 2 2006.201.05:06:28.37#ibcon#read 5, iclass 37, count 2 2006.201.05:06:28.37#ibcon#about to read 6, iclass 37, count 2 2006.201.05:06:28.37#ibcon#read 6, iclass 37, count 2 2006.201.05:06:28.37#ibcon#end of sib2, iclass 37, count 2 2006.201.05:06:28.37#ibcon#*after write, iclass 37, count 2 2006.201.05:06:28.37#ibcon#*before return 0, iclass 37, count 2 2006.201.05:06:28.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:28.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:06:28.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.05:06:28.37#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:28.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:28.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:28.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:28.49#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:06:28.49#ibcon#first serial, iclass 37, count 0 2006.201.05:06:28.49#ibcon#enter sib2, iclass 37, count 0 2006.201.05:06:28.49#ibcon#flushed, iclass 37, count 0 2006.201.05:06:28.49#ibcon#about to write, iclass 37, count 0 2006.201.05:06:28.49#ibcon#wrote, iclass 37, count 0 2006.201.05:06:28.49#ibcon#about to read 3, iclass 37, count 0 2006.201.05:06:28.51#ibcon#read 3, iclass 37, count 0 2006.201.05:06:28.51#ibcon#about to read 4, iclass 37, count 0 2006.201.05:06:28.51#ibcon#read 4, iclass 37, count 0 2006.201.05:06:28.51#ibcon#about to read 5, iclass 37, count 0 2006.201.05:06:28.51#ibcon#read 5, iclass 37, count 0 2006.201.05:06:28.51#ibcon#about to read 6, iclass 37, count 0 2006.201.05:06:28.51#ibcon#read 6, iclass 37, count 0 2006.201.05:06:28.51#ibcon#end of sib2, iclass 37, count 0 2006.201.05:06:28.51#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:06:28.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:06:28.51#ibcon#[27=USB\r\n] 2006.201.05:06:28.51#ibcon#*before write, iclass 37, count 0 2006.201.05:06:28.51#ibcon#enter sib2, iclass 37, count 0 2006.201.05:06:28.51#ibcon#flushed, iclass 37, count 0 2006.201.05:06:28.51#ibcon#about to write, iclass 37, count 0 2006.201.05:06:28.51#ibcon#wrote, iclass 37, count 0 2006.201.05:06:28.51#ibcon#about to read 3, iclass 37, count 0 2006.201.05:06:28.54#ibcon#read 3, iclass 37, count 0 2006.201.05:06:28.54#ibcon#about to read 4, iclass 37, count 0 2006.201.05:06:28.54#ibcon#read 4, iclass 37, count 0 2006.201.05:06:28.54#ibcon#about to read 5, iclass 37, count 0 2006.201.05:06:28.54#ibcon#read 5, iclass 37, count 0 2006.201.05:06:28.54#ibcon#about to read 6, iclass 37, count 0 2006.201.05:06:28.54#ibcon#read 6, iclass 37, count 0 2006.201.05:06:28.54#ibcon#end of sib2, iclass 37, count 0 2006.201.05:06:28.54#ibcon#*after write, iclass 37, count 0 2006.201.05:06:28.54#ibcon#*before return 0, iclass 37, count 0 2006.201.05:06:28.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:28.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:06:28.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:06:28.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:06:28.54$vck44/vblo=3,649.99 2006.201.05:06:28.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.05:06:28.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.05:06:28.54#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:28.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:28.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:28.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:28.54#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:06:28.54#ibcon#first serial, iclass 39, count 0 2006.201.05:06:28.54#ibcon#enter sib2, iclass 39, count 0 2006.201.05:06:28.54#ibcon#flushed, iclass 39, count 0 2006.201.05:06:28.54#ibcon#about to write, iclass 39, count 0 2006.201.05:06:28.54#ibcon#wrote, iclass 39, count 0 2006.201.05:06:28.54#ibcon#about to read 3, iclass 39, count 0 2006.201.05:06:28.56#ibcon#read 3, iclass 39, count 0 2006.201.05:06:28.56#ibcon#about to read 4, iclass 39, count 0 2006.201.05:06:28.56#ibcon#read 4, iclass 39, count 0 2006.201.05:06:28.56#ibcon#about to read 5, iclass 39, count 0 2006.201.05:06:28.56#ibcon#read 5, iclass 39, count 0 2006.201.05:06:28.56#ibcon#about to read 6, iclass 39, count 0 2006.201.05:06:28.56#ibcon#read 6, iclass 39, count 0 2006.201.05:06:28.56#ibcon#end of sib2, iclass 39, count 0 2006.201.05:06:28.56#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:06:28.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:06:28.56#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:06:28.56#ibcon#*before write, iclass 39, count 0 2006.201.05:06:28.56#ibcon#enter sib2, iclass 39, count 0 2006.201.05:06:28.56#ibcon#flushed, iclass 39, count 0 2006.201.05:06:28.56#ibcon#about to write, iclass 39, count 0 2006.201.05:06:28.56#ibcon#wrote, iclass 39, count 0 2006.201.05:06:28.56#ibcon#about to read 3, iclass 39, count 0 2006.201.05:06:28.60#ibcon#read 3, iclass 39, count 0 2006.201.05:06:28.60#ibcon#about to read 4, iclass 39, count 0 2006.201.05:06:28.60#ibcon#read 4, iclass 39, count 0 2006.201.05:06:28.60#ibcon#about to read 5, iclass 39, count 0 2006.201.05:06:28.60#ibcon#read 5, iclass 39, count 0 2006.201.05:06:28.60#ibcon#about to read 6, iclass 39, count 0 2006.201.05:06:28.60#ibcon#read 6, iclass 39, count 0 2006.201.05:06:28.60#ibcon#end of sib2, iclass 39, count 0 2006.201.05:06:28.60#ibcon#*after write, iclass 39, count 0 2006.201.05:06:28.60#ibcon#*before return 0, iclass 39, count 0 2006.201.05:06:28.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:28.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:06:28.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:06:28.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:06:28.60$vck44/vb=3,4 2006.201.05:06:28.60#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.05:06:28.60#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.05:06:28.60#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:28.60#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:28.66#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:28.66#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:28.66#ibcon#enter wrdev, iclass 2, count 2 2006.201.05:06:28.66#ibcon#first serial, iclass 2, count 2 2006.201.05:06:28.66#ibcon#enter sib2, iclass 2, count 2 2006.201.05:06:28.66#ibcon#flushed, iclass 2, count 2 2006.201.05:06:28.66#ibcon#about to write, iclass 2, count 2 2006.201.05:06:28.69#ibcon#wrote, iclass 2, count 2 2006.201.05:06:28.69#ibcon#about to read 3, iclass 2, count 2 2006.201.05:06:28.72#ibcon#read 3, iclass 2, count 2 2006.201.05:06:28.72#ibcon#about to read 4, iclass 2, count 2 2006.201.05:06:28.72#ibcon#read 4, iclass 2, count 2 2006.201.05:06:28.72#ibcon#about to read 5, iclass 2, count 2 2006.201.05:06:28.72#ibcon#read 5, iclass 2, count 2 2006.201.05:06:28.72#ibcon#about to read 6, iclass 2, count 2 2006.201.05:06:28.72#ibcon#read 6, iclass 2, count 2 2006.201.05:06:28.72#ibcon#end of sib2, iclass 2, count 2 2006.201.05:06:28.72#ibcon#*mode == 0, iclass 2, count 2 2006.201.05:06:28.72#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.05:06:28.72#ibcon#[27=AT03-04\r\n] 2006.201.05:06:28.72#ibcon#*before write, iclass 2, count 2 2006.201.05:06:28.72#ibcon#enter sib2, iclass 2, count 2 2006.201.05:06:28.72#ibcon#flushed, iclass 2, count 2 2006.201.05:06:28.72#ibcon#about to write, iclass 2, count 2 2006.201.05:06:28.72#ibcon#wrote, iclass 2, count 2 2006.201.05:06:28.72#ibcon#about to read 3, iclass 2, count 2 2006.201.05:06:28.75#ibcon#read 3, iclass 2, count 2 2006.201.05:06:28.75#ibcon#about to read 4, iclass 2, count 2 2006.201.05:06:28.75#ibcon#read 4, iclass 2, count 2 2006.201.05:06:28.75#ibcon#about to read 5, iclass 2, count 2 2006.201.05:06:28.75#ibcon#read 5, iclass 2, count 2 2006.201.05:06:28.75#ibcon#about to read 6, iclass 2, count 2 2006.201.05:06:28.75#ibcon#read 6, iclass 2, count 2 2006.201.05:06:28.75#ibcon#end of sib2, iclass 2, count 2 2006.201.05:06:28.75#ibcon#*after write, iclass 2, count 2 2006.201.05:06:28.75#ibcon#*before return 0, iclass 2, count 2 2006.201.05:06:28.75#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:28.75#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:06:28.75#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.05:06:28.75#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:28.75#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:28.87#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:28.87#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:28.87#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:06:28.87#ibcon#first serial, iclass 2, count 0 2006.201.05:06:28.87#ibcon#enter sib2, iclass 2, count 0 2006.201.05:06:28.87#ibcon#flushed, iclass 2, count 0 2006.201.05:06:28.87#ibcon#about to write, iclass 2, count 0 2006.201.05:06:28.87#ibcon#wrote, iclass 2, count 0 2006.201.05:06:28.87#ibcon#about to read 3, iclass 2, count 0 2006.201.05:06:28.89#ibcon#read 3, iclass 2, count 0 2006.201.05:06:28.89#ibcon#about to read 4, iclass 2, count 0 2006.201.05:06:28.89#ibcon#read 4, iclass 2, count 0 2006.201.05:06:28.89#ibcon#about to read 5, iclass 2, count 0 2006.201.05:06:28.89#ibcon#read 5, iclass 2, count 0 2006.201.05:06:28.89#ibcon#about to read 6, iclass 2, count 0 2006.201.05:06:28.89#ibcon#read 6, iclass 2, count 0 2006.201.05:06:28.89#ibcon#end of sib2, iclass 2, count 0 2006.201.05:06:28.89#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:06:28.89#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:06:28.89#ibcon#[27=USB\r\n] 2006.201.05:06:28.89#ibcon#*before write, iclass 2, count 0 2006.201.05:06:28.89#ibcon#enter sib2, iclass 2, count 0 2006.201.05:06:28.89#ibcon#flushed, iclass 2, count 0 2006.201.05:06:28.89#ibcon#about to write, iclass 2, count 0 2006.201.05:06:28.89#ibcon#wrote, iclass 2, count 0 2006.201.05:06:28.89#ibcon#about to read 3, iclass 2, count 0 2006.201.05:06:28.92#ibcon#read 3, iclass 2, count 0 2006.201.05:06:28.92#ibcon#about to read 4, iclass 2, count 0 2006.201.05:06:28.92#ibcon#read 4, iclass 2, count 0 2006.201.05:06:28.92#ibcon#about to read 5, iclass 2, count 0 2006.201.05:06:28.92#ibcon#read 5, iclass 2, count 0 2006.201.05:06:28.92#ibcon#about to read 6, iclass 2, count 0 2006.201.05:06:28.92#ibcon#read 6, iclass 2, count 0 2006.201.05:06:28.92#ibcon#end of sib2, iclass 2, count 0 2006.201.05:06:28.92#ibcon#*after write, iclass 2, count 0 2006.201.05:06:28.92#ibcon#*before return 0, iclass 2, count 0 2006.201.05:06:28.92#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:28.92#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:06:28.92#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:06:28.92#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:06:28.92$vck44/vblo=4,679.99 2006.201.05:06:28.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.05:06:28.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.05:06:28.92#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:28.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:28.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:28.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:28.92#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:06:28.92#ibcon#first serial, iclass 5, count 0 2006.201.05:06:28.92#ibcon#enter sib2, iclass 5, count 0 2006.201.05:06:28.92#ibcon#flushed, iclass 5, count 0 2006.201.05:06:28.92#ibcon#about to write, iclass 5, count 0 2006.201.05:06:28.92#ibcon#wrote, iclass 5, count 0 2006.201.05:06:28.92#ibcon#about to read 3, iclass 5, count 0 2006.201.05:06:28.94#ibcon#read 3, iclass 5, count 0 2006.201.05:06:28.94#ibcon#about to read 4, iclass 5, count 0 2006.201.05:06:28.94#ibcon#read 4, iclass 5, count 0 2006.201.05:06:28.94#ibcon#about to read 5, iclass 5, count 0 2006.201.05:06:28.94#ibcon#read 5, iclass 5, count 0 2006.201.05:06:28.94#ibcon#about to read 6, iclass 5, count 0 2006.201.05:06:28.94#ibcon#read 6, iclass 5, count 0 2006.201.05:06:28.94#ibcon#end of sib2, iclass 5, count 0 2006.201.05:06:28.94#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:06:28.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:06:28.94#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:06:28.94#ibcon#*before write, iclass 5, count 0 2006.201.05:06:28.94#ibcon#enter sib2, iclass 5, count 0 2006.201.05:06:28.94#ibcon#flushed, iclass 5, count 0 2006.201.05:06:28.94#ibcon#about to write, iclass 5, count 0 2006.201.05:06:28.94#ibcon#wrote, iclass 5, count 0 2006.201.05:06:28.94#ibcon#about to read 3, iclass 5, count 0 2006.201.05:06:28.98#ibcon#read 3, iclass 5, count 0 2006.201.05:06:28.98#ibcon#about to read 4, iclass 5, count 0 2006.201.05:06:28.98#ibcon#read 4, iclass 5, count 0 2006.201.05:06:28.98#ibcon#about to read 5, iclass 5, count 0 2006.201.05:06:28.98#ibcon#read 5, iclass 5, count 0 2006.201.05:06:28.98#ibcon#about to read 6, iclass 5, count 0 2006.201.05:06:28.98#ibcon#read 6, iclass 5, count 0 2006.201.05:06:28.98#ibcon#end of sib2, iclass 5, count 0 2006.201.05:06:28.98#ibcon#*after write, iclass 5, count 0 2006.201.05:06:28.98#ibcon#*before return 0, iclass 5, count 0 2006.201.05:06:28.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:28.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:06:28.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:06:28.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:06:28.98$vck44/vb=4,5 2006.201.05:06:28.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.05:06:28.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.05:06:28.98#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:28.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:29.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:29.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:29.04#ibcon#enter wrdev, iclass 7, count 2 2006.201.05:06:29.04#ibcon#first serial, iclass 7, count 2 2006.201.05:06:29.04#ibcon#enter sib2, iclass 7, count 2 2006.201.05:06:29.04#ibcon#flushed, iclass 7, count 2 2006.201.05:06:29.04#ibcon#about to write, iclass 7, count 2 2006.201.05:06:29.04#ibcon#wrote, iclass 7, count 2 2006.201.05:06:29.04#ibcon#about to read 3, iclass 7, count 2 2006.201.05:06:29.06#ibcon#read 3, iclass 7, count 2 2006.201.05:06:29.06#ibcon#about to read 4, iclass 7, count 2 2006.201.05:06:29.06#ibcon#read 4, iclass 7, count 2 2006.201.05:06:29.06#ibcon#about to read 5, iclass 7, count 2 2006.201.05:06:29.06#ibcon#read 5, iclass 7, count 2 2006.201.05:06:29.06#ibcon#about to read 6, iclass 7, count 2 2006.201.05:06:29.06#ibcon#read 6, iclass 7, count 2 2006.201.05:06:29.06#ibcon#end of sib2, iclass 7, count 2 2006.201.05:06:29.06#ibcon#*mode == 0, iclass 7, count 2 2006.201.05:06:29.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.05:06:29.06#ibcon#[27=AT04-05\r\n] 2006.201.05:06:29.06#ibcon#*before write, iclass 7, count 2 2006.201.05:06:29.06#ibcon#enter sib2, iclass 7, count 2 2006.201.05:06:29.06#ibcon#flushed, iclass 7, count 2 2006.201.05:06:29.06#ibcon#about to write, iclass 7, count 2 2006.201.05:06:29.06#ibcon#wrote, iclass 7, count 2 2006.201.05:06:29.06#ibcon#about to read 3, iclass 7, count 2 2006.201.05:06:29.09#ibcon#read 3, iclass 7, count 2 2006.201.05:06:29.09#ibcon#about to read 4, iclass 7, count 2 2006.201.05:06:29.09#ibcon#read 4, iclass 7, count 2 2006.201.05:06:29.09#ibcon#about to read 5, iclass 7, count 2 2006.201.05:06:29.09#ibcon#read 5, iclass 7, count 2 2006.201.05:06:29.09#ibcon#about to read 6, iclass 7, count 2 2006.201.05:06:29.09#ibcon#read 6, iclass 7, count 2 2006.201.05:06:29.09#ibcon#end of sib2, iclass 7, count 2 2006.201.05:06:29.09#ibcon#*after write, iclass 7, count 2 2006.201.05:06:29.09#ibcon#*before return 0, iclass 7, count 2 2006.201.05:06:29.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:29.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:06:29.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.05:06:29.09#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:29.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:29.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:29.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:29.21#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:06:29.21#ibcon#first serial, iclass 7, count 0 2006.201.05:06:29.21#ibcon#enter sib2, iclass 7, count 0 2006.201.05:06:29.21#ibcon#flushed, iclass 7, count 0 2006.201.05:06:29.21#ibcon#about to write, iclass 7, count 0 2006.201.05:06:29.21#ibcon#wrote, iclass 7, count 0 2006.201.05:06:29.21#ibcon#about to read 3, iclass 7, count 0 2006.201.05:06:29.23#ibcon#read 3, iclass 7, count 0 2006.201.05:06:29.23#ibcon#about to read 4, iclass 7, count 0 2006.201.05:06:29.23#ibcon#read 4, iclass 7, count 0 2006.201.05:06:29.23#ibcon#about to read 5, iclass 7, count 0 2006.201.05:06:29.23#ibcon#read 5, iclass 7, count 0 2006.201.05:06:29.23#ibcon#about to read 6, iclass 7, count 0 2006.201.05:06:29.23#ibcon#read 6, iclass 7, count 0 2006.201.05:06:29.23#ibcon#end of sib2, iclass 7, count 0 2006.201.05:06:29.23#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:06:29.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:06:29.23#ibcon#[27=USB\r\n] 2006.201.05:06:29.23#ibcon#*before write, iclass 7, count 0 2006.201.05:06:29.23#ibcon#enter sib2, iclass 7, count 0 2006.201.05:06:29.23#ibcon#flushed, iclass 7, count 0 2006.201.05:06:29.23#ibcon#about to write, iclass 7, count 0 2006.201.05:06:29.23#ibcon#wrote, iclass 7, count 0 2006.201.05:06:29.23#ibcon#about to read 3, iclass 7, count 0 2006.201.05:06:29.26#ibcon#read 3, iclass 7, count 0 2006.201.05:06:29.26#ibcon#about to read 4, iclass 7, count 0 2006.201.05:06:29.26#ibcon#read 4, iclass 7, count 0 2006.201.05:06:29.26#ibcon#about to read 5, iclass 7, count 0 2006.201.05:06:29.26#ibcon#read 5, iclass 7, count 0 2006.201.05:06:29.26#ibcon#about to read 6, iclass 7, count 0 2006.201.05:06:29.26#ibcon#read 6, iclass 7, count 0 2006.201.05:06:29.26#ibcon#end of sib2, iclass 7, count 0 2006.201.05:06:29.26#ibcon#*after write, iclass 7, count 0 2006.201.05:06:29.26#ibcon#*before return 0, iclass 7, count 0 2006.201.05:06:29.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:29.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:06:29.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:06:29.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:06:29.26$vck44/vblo=5,709.99 2006.201.05:06:29.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.05:06:29.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.05:06:29.26#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:29.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:29.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:29.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:29.26#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:06:29.26#ibcon#first serial, iclass 11, count 0 2006.201.05:06:29.26#ibcon#enter sib2, iclass 11, count 0 2006.201.05:06:29.26#ibcon#flushed, iclass 11, count 0 2006.201.05:06:29.26#ibcon#about to write, iclass 11, count 0 2006.201.05:06:29.26#ibcon#wrote, iclass 11, count 0 2006.201.05:06:29.26#ibcon#about to read 3, iclass 11, count 0 2006.201.05:06:29.28#ibcon#read 3, iclass 11, count 0 2006.201.05:06:29.28#ibcon#about to read 4, iclass 11, count 0 2006.201.05:06:29.28#ibcon#read 4, iclass 11, count 0 2006.201.05:06:29.28#ibcon#about to read 5, iclass 11, count 0 2006.201.05:06:29.28#ibcon#read 5, iclass 11, count 0 2006.201.05:06:29.28#ibcon#about to read 6, iclass 11, count 0 2006.201.05:06:29.28#ibcon#read 6, iclass 11, count 0 2006.201.05:06:29.28#ibcon#end of sib2, iclass 11, count 0 2006.201.05:06:29.28#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:06:29.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:06:29.28#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:06:29.28#ibcon#*before write, iclass 11, count 0 2006.201.05:06:29.28#ibcon#enter sib2, iclass 11, count 0 2006.201.05:06:29.28#ibcon#flushed, iclass 11, count 0 2006.201.05:06:29.28#ibcon#about to write, iclass 11, count 0 2006.201.05:06:29.28#ibcon#wrote, iclass 11, count 0 2006.201.05:06:29.28#ibcon#about to read 3, iclass 11, count 0 2006.201.05:06:29.32#ibcon#read 3, iclass 11, count 0 2006.201.05:06:29.32#ibcon#about to read 4, iclass 11, count 0 2006.201.05:06:29.32#ibcon#read 4, iclass 11, count 0 2006.201.05:06:29.32#ibcon#about to read 5, iclass 11, count 0 2006.201.05:06:29.32#ibcon#read 5, iclass 11, count 0 2006.201.05:06:29.32#ibcon#about to read 6, iclass 11, count 0 2006.201.05:06:29.32#ibcon#read 6, iclass 11, count 0 2006.201.05:06:29.32#ibcon#end of sib2, iclass 11, count 0 2006.201.05:06:29.32#ibcon#*after write, iclass 11, count 0 2006.201.05:06:29.32#ibcon#*before return 0, iclass 11, count 0 2006.201.05:06:29.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:29.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:06:29.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:06:29.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:06:29.32$vck44/vb=5,4 2006.201.05:06:29.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.05:06:29.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.05:06:29.32#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:29.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:29.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:29.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:29.38#ibcon#enter wrdev, iclass 13, count 2 2006.201.05:06:29.38#ibcon#first serial, iclass 13, count 2 2006.201.05:06:29.38#ibcon#enter sib2, iclass 13, count 2 2006.201.05:06:29.38#ibcon#flushed, iclass 13, count 2 2006.201.05:06:29.38#ibcon#about to write, iclass 13, count 2 2006.201.05:06:29.38#ibcon#wrote, iclass 13, count 2 2006.201.05:06:29.38#ibcon#about to read 3, iclass 13, count 2 2006.201.05:06:29.40#ibcon#read 3, iclass 13, count 2 2006.201.05:06:29.40#ibcon#about to read 4, iclass 13, count 2 2006.201.05:06:29.40#ibcon#read 4, iclass 13, count 2 2006.201.05:06:29.40#ibcon#about to read 5, iclass 13, count 2 2006.201.05:06:29.40#ibcon#read 5, iclass 13, count 2 2006.201.05:06:29.40#ibcon#about to read 6, iclass 13, count 2 2006.201.05:06:29.40#ibcon#read 6, iclass 13, count 2 2006.201.05:06:29.40#ibcon#end of sib2, iclass 13, count 2 2006.201.05:06:29.40#ibcon#*mode == 0, iclass 13, count 2 2006.201.05:06:29.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.05:06:29.40#ibcon#[27=AT05-04\r\n] 2006.201.05:06:29.40#ibcon#*before write, iclass 13, count 2 2006.201.05:06:29.40#ibcon#enter sib2, iclass 13, count 2 2006.201.05:06:29.40#ibcon#flushed, iclass 13, count 2 2006.201.05:06:29.40#ibcon#about to write, iclass 13, count 2 2006.201.05:06:29.40#ibcon#wrote, iclass 13, count 2 2006.201.05:06:29.40#ibcon#about to read 3, iclass 13, count 2 2006.201.05:06:29.43#ibcon#read 3, iclass 13, count 2 2006.201.05:06:29.43#ibcon#about to read 4, iclass 13, count 2 2006.201.05:06:29.43#ibcon#read 4, iclass 13, count 2 2006.201.05:06:29.43#ibcon#about to read 5, iclass 13, count 2 2006.201.05:06:29.43#ibcon#read 5, iclass 13, count 2 2006.201.05:06:29.43#ibcon#about to read 6, iclass 13, count 2 2006.201.05:06:29.43#ibcon#read 6, iclass 13, count 2 2006.201.05:06:29.43#ibcon#end of sib2, iclass 13, count 2 2006.201.05:06:29.43#ibcon#*after write, iclass 13, count 2 2006.201.05:06:29.43#ibcon#*before return 0, iclass 13, count 2 2006.201.05:06:29.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:29.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:06:29.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.05:06:29.43#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:29.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:29.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:29.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:29.55#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:06:29.55#ibcon#first serial, iclass 13, count 0 2006.201.05:06:29.55#ibcon#enter sib2, iclass 13, count 0 2006.201.05:06:29.55#ibcon#flushed, iclass 13, count 0 2006.201.05:06:29.55#ibcon#about to write, iclass 13, count 0 2006.201.05:06:29.55#ibcon#wrote, iclass 13, count 0 2006.201.05:06:29.55#ibcon#about to read 3, iclass 13, count 0 2006.201.05:06:29.57#ibcon#read 3, iclass 13, count 0 2006.201.05:06:29.57#ibcon#about to read 4, iclass 13, count 0 2006.201.05:06:29.57#ibcon#read 4, iclass 13, count 0 2006.201.05:06:29.57#ibcon#about to read 5, iclass 13, count 0 2006.201.05:06:29.57#ibcon#read 5, iclass 13, count 0 2006.201.05:06:29.57#ibcon#about to read 6, iclass 13, count 0 2006.201.05:06:29.57#ibcon#read 6, iclass 13, count 0 2006.201.05:06:29.57#ibcon#end of sib2, iclass 13, count 0 2006.201.05:06:29.57#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:06:29.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:06:29.57#ibcon#[27=USB\r\n] 2006.201.05:06:29.57#ibcon#*before write, iclass 13, count 0 2006.201.05:06:29.57#ibcon#enter sib2, iclass 13, count 0 2006.201.05:06:29.57#ibcon#flushed, iclass 13, count 0 2006.201.05:06:29.57#ibcon#about to write, iclass 13, count 0 2006.201.05:06:29.57#ibcon#wrote, iclass 13, count 0 2006.201.05:06:29.57#ibcon#about to read 3, iclass 13, count 0 2006.201.05:06:29.60#ibcon#read 3, iclass 13, count 0 2006.201.05:06:29.60#ibcon#about to read 4, iclass 13, count 0 2006.201.05:06:29.60#ibcon#read 4, iclass 13, count 0 2006.201.05:06:29.60#ibcon#about to read 5, iclass 13, count 0 2006.201.05:06:29.60#ibcon#read 5, iclass 13, count 0 2006.201.05:06:29.60#ibcon#about to read 6, iclass 13, count 0 2006.201.05:06:29.60#ibcon#read 6, iclass 13, count 0 2006.201.05:06:29.60#ibcon#end of sib2, iclass 13, count 0 2006.201.05:06:29.60#ibcon#*after write, iclass 13, count 0 2006.201.05:06:29.60#ibcon#*before return 0, iclass 13, count 0 2006.201.05:06:29.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:29.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:06:29.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:06:29.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:06:29.60$vck44/vblo=6,719.99 2006.201.05:06:29.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.05:06:29.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.05:06:29.60#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:29.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:29.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:29.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:29.60#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:06:29.60#ibcon#first serial, iclass 15, count 0 2006.201.05:06:29.60#ibcon#enter sib2, iclass 15, count 0 2006.201.05:06:29.60#ibcon#flushed, iclass 15, count 0 2006.201.05:06:29.60#ibcon#about to write, iclass 15, count 0 2006.201.05:06:29.60#ibcon#wrote, iclass 15, count 0 2006.201.05:06:29.60#ibcon#about to read 3, iclass 15, count 0 2006.201.05:06:29.62#ibcon#read 3, iclass 15, count 0 2006.201.05:06:29.62#ibcon#about to read 4, iclass 15, count 0 2006.201.05:06:29.62#ibcon#read 4, iclass 15, count 0 2006.201.05:06:29.62#ibcon#about to read 5, iclass 15, count 0 2006.201.05:06:29.62#ibcon#read 5, iclass 15, count 0 2006.201.05:06:29.62#ibcon#about to read 6, iclass 15, count 0 2006.201.05:06:29.62#ibcon#read 6, iclass 15, count 0 2006.201.05:06:29.62#ibcon#end of sib2, iclass 15, count 0 2006.201.05:06:29.62#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:06:29.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:06:29.62#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:06:29.62#ibcon#*before write, iclass 15, count 0 2006.201.05:06:29.62#ibcon#enter sib2, iclass 15, count 0 2006.201.05:06:29.62#ibcon#flushed, iclass 15, count 0 2006.201.05:06:29.62#ibcon#about to write, iclass 15, count 0 2006.201.05:06:29.62#ibcon#wrote, iclass 15, count 0 2006.201.05:06:29.62#ibcon#about to read 3, iclass 15, count 0 2006.201.05:06:29.66#ibcon#read 3, iclass 15, count 0 2006.201.05:06:29.66#ibcon#about to read 4, iclass 15, count 0 2006.201.05:06:29.66#ibcon#read 4, iclass 15, count 0 2006.201.05:06:29.66#ibcon#about to read 5, iclass 15, count 0 2006.201.05:06:29.66#ibcon#read 5, iclass 15, count 0 2006.201.05:06:29.66#ibcon#about to read 6, iclass 15, count 0 2006.201.05:06:29.66#ibcon#read 6, iclass 15, count 0 2006.201.05:06:29.66#ibcon#end of sib2, iclass 15, count 0 2006.201.05:06:29.66#ibcon#*after write, iclass 15, count 0 2006.201.05:06:29.66#ibcon#*before return 0, iclass 15, count 0 2006.201.05:06:29.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:29.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:06:29.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:06:29.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:06:29.66$vck44/vb=6,4 2006.201.05:06:29.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.05:06:29.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.05:06:29.66#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:29.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:29.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:29.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:29.72#ibcon#enter wrdev, iclass 17, count 2 2006.201.05:06:29.72#ibcon#first serial, iclass 17, count 2 2006.201.05:06:29.72#ibcon#enter sib2, iclass 17, count 2 2006.201.05:06:29.72#ibcon#flushed, iclass 17, count 2 2006.201.05:06:29.72#ibcon#about to write, iclass 17, count 2 2006.201.05:06:29.72#ibcon#wrote, iclass 17, count 2 2006.201.05:06:29.72#ibcon#about to read 3, iclass 17, count 2 2006.201.05:06:29.74#ibcon#read 3, iclass 17, count 2 2006.201.05:06:29.74#ibcon#about to read 4, iclass 17, count 2 2006.201.05:06:29.74#ibcon#read 4, iclass 17, count 2 2006.201.05:06:29.74#ibcon#about to read 5, iclass 17, count 2 2006.201.05:06:29.74#ibcon#read 5, iclass 17, count 2 2006.201.05:06:29.74#ibcon#about to read 6, iclass 17, count 2 2006.201.05:06:29.74#ibcon#read 6, iclass 17, count 2 2006.201.05:06:29.74#ibcon#end of sib2, iclass 17, count 2 2006.201.05:06:29.74#ibcon#*mode == 0, iclass 17, count 2 2006.201.05:06:29.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.05:06:29.74#ibcon#[27=AT06-04\r\n] 2006.201.05:06:29.74#ibcon#*before write, iclass 17, count 2 2006.201.05:06:29.74#ibcon#enter sib2, iclass 17, count 2 2006.201.05:06:29.74#ibcon#flushed, iclass 17, count 2 2006.201.05:06:29.74#ibcon#about to write, iclass 17, count 2 2006.201.05:06:29.74#ibcon#wrote, iclass 17, count 2 2006.201.05:06:29.74#ibcon#about to read 3, iclass 17, count 2 2006.201.05:06:29.77#ibcon#read 3, iclass 17, count 2 2006.201.05:06:29.77#ibcon#about to read 4, iclass 17, count 2 2006.201.05:06:29.77#ibcon#read 4, iclass 17, count 2 2006.201.05:06:29.81#ibcon#about to read 5, iclass 17, count 2 2006.201.05:06:29.81#ibcon#read 5, iclass 17, count 2 2006.201.05:06:29.81#ibcon#about to read 6, iclass 17, count 2 2006.201.05:06:29.81#ibcon#read 6, iclass 17, count 2 2006.201.05:06:29.81#ibcon#end of sib2, iclass 17, count 2 2006.201.05:06:29.81#ibcon#*after write, iclass 17, count 2 2006.201.05:06:29.81#ibcon#*before return 0, iclass 17, count 2 2006.201.05:06:29.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:29.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:06:29.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.05:06:29.81#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:29.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:29.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:29.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:29.93#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:06:29.93#ibcon#first serial, iclass 17, count 0 2006.201.05:06:29.93#ibcon#enter sib2, iclass 17, count 0 2006.201.05:06:29.93#ibcon#flushed, iclass 17, count 0 2006.201.05:06:29.93#ibcon#about to write, iclass 17, count 0 2006.201.05:06:29.93#ibcon#wrote, iclass 17, count 0 2006.201.05:06:29.93#ibcon#about to read 3, iclass 17, count 0 2006.201.05:06:29.95#ibcon#read 3, iclass 17, count 0 2006.201.05:06:29.95#ibcon#about to read 4, iclass 17, count 0 2006.201.05:06:29.95#ibcon#read 4, iclass 17, count 0 2006.201.05:06:29.95#ibcon#about to read 5, iclass 17, count 0 2006.201.05:06:29.95#ibcon#read 5, iclass 17, count 0 2006.201.05:06:29.95#ibcon#about to read 6, iclass 17, count 0 2006.201.05:06:29.95#ibcon#read 6, iclass 17, count 0 2006.201.05:06:29.95#ibcon#end of sib2, iclass 17, count 0 2006.201.05:06:29.95#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:06:29.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:06:29.95#ibcon#[27=USB\r\n] 2006.201.05:06:29.95#ibcon#*before write, iclass 17, count 0 2006.201.05:06:29.95#ibcon#enter sib2, iclass 17, count 0 2006.201.05:06:29.95#ibcon#flushed, iclass 17, count 0 2006.201.05:06:29.95#ibcon#about to write, iclass 17, count 0 2006.201.05:06:29.95#ibcon#wrote, iclass 17, count 0 2006.201.05:06:29.95#ibcon#about to read 3, iclass 17, count 0 2006.201.05:06:29.98#ibcon#read 3, iclass 17, count 0 2006.201.05:06:29.98#ibcon#about to read 4, iclass 17, count 0 2006.201.05:06:29.98#ibcon#read 4, iclass 17, count 0 2006.201.05:06:29.98#ibcon#about to read 5, iclass 17, count 0 2006.201.05:06:29.98#ibcon#read 5, iclass 17, count 0 2006.201.05:06:29.98#ibcon#about to read 6, iclass 17, count 0 2006.201.05:06:29.98#ibcon#read 6, iclass 17, count 0 2006.201.05:06:29.98#ibcon#end of sib2, iclass 17, count 0 2006.201.05:06:29.98#ibcon#*after write, iclass 17, count 0 2006.201.05:06:29.98#ibcon#*before return 0, iclass 17, count 0 2006.201.05:06:29.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:29.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:06:29.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:06:29.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:06:29.98$vck44/vblo=7,734.99 2006.201.05:06:29.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.05:06:29.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.05:06:29.98#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:29.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:29.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:29.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:29.98#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:06:29.98#ibcon#first serial, iclass 19, count 0 2006.201.05:06:29.98#ibcon#enter sib2, iclass 19, count 0 2006.201.05:06:29.98#ibcon#flushed, iclass 19, count 0 2006.201.05:06:29.98#ibcon#about to write, iclass 19, count 0 2006.201.05:06:29.98#ibcon#wrote, iclass 19, count 0 2006.201.05:06:29.98#ibcon#about to read 3, iclass 19, count 0 2006.201.05:06:30.00#ibcon#read 3, iclass 19, count 0 2006.201.05:06:30.00#ibcon#about to read 4, iclass 19, count 0 2006.201.05:06:30.00#ibcon#read 4, iclass 19, count 0 2006.201.05:06:30.00#ibcon#about to read 5, iclass 19, count 0 2006.201.05:06:30.00#ibcon#read 5, iclass 19, count 0 2006.201.05:06:30.00#ibcon#about to read 6, iclass 19, count 0 2006.201.05:06:30.00#ibcon#read 6, iclass 19, count 0 2006.201.05:06:30.00#ibcon#end of sib2, iclass 19, count 0 2006.201.05:06:30.00#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:06:30.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:06:30.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:06:30.00#ibcon#*before write, iclass 19, count 0 2006.201.05:06:30.00#ibcon#enter sib2, iclass 19, count 0 2006.201.05:06:30.00#ibcon#flushed, iclass 19, count 0 2006.201.05:06:30.00#ibcon#about to write, iclass 19, count 0 2006.201.05:06:30.00#ibcon#wrote, iclass 19, count 0 2006.201.05:06:30.00#ibcon#about to read 3, iclass 19, count 0 2006.201.05:06:30.04#ibcon#read 3, iclass 19, count 0 2006.201.05:06:30.04#ibcon#about to read 4, iclass 19, count 0 2006.201.05:06:30.04#ibcon#read 4, iclass 19, count 0 2006.201.05:06:30.04#ibcon#about to read 5, iclass 19, count 0 2006.201.05:06:30.04#ibcon#read 5, iclass 19, count 0 2006.201.05:06:30.04#ibcon#about to read 6, iclass 19, count 0 2006.201.05:06:30.04#ibcon#read 6, iclass 19, count 0 2006.201.05:06:30.04#ibcon#end of sib2, iclass 19, count 0 2006.201.05:06:30.04#ibcon#*after write, iclass 19, count 0 2006.201.05:06:30.04#ibcon#*before return 0, iclass 19, count 0 2006.201.05:06:30.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:30.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:06:30.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:06:30.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:06:30.04$vck44/vb=7,4 2006.201.05:06:30.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.05:06:30.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.05:06:30.04#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:30.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:30.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:30.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:30.10#ibcon#enter wrdev, iclass 21, count 2 2006.201.05:06:30.10#ibcon#first serial, iclass 21, count 2 2006.201.05:06:30.10#ibcon#enter sib2, iclass 21, count 2 2006.201.05:06:30.10#ibcon#flushed, iclass 21, count 2 2006.201.05:06:30.10#ibcon#about to write, iclass 21, count 2 2006.201.05:06:30.10#ibcon#wrote, iclass 21, count 2 2006.201.05:06:30.10#ibcon#about to read 3, iclass 21, count 2 2006.201.05:06:30.12#ibcon#read 3, iclass 21, count 2 2006.201.05:06:30.12#ibcon#about to read 4, iclass 21, count 2 2006.201.05:06:30.12#ibcon#read 4, iclass 21, count 2 2006.201.05:06:30.12#ibcon#about to read 5, iclass 21, count 2 2006.201.05:06:30.12#ibcon#read 5, iclass 21, count 2 2006.201.05:06:30.12#ibcon#about to read 6, iclass 21, count 2 2006.201.05:06:30.12#ibcon#read 6, iclass 21, count 2 2006.201.05:06:30.12#ibcon#end of sib2, iclass 21, count 2 2006.201.05:06:30.12#ibcon#*mode == 0, iclass 21, count 2 2006.201.05:06:30.12#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.05:06:30.12#ibcon#[27=AT07-04\r\n] 2006.201.05:06:30.12#ibcon#*before write, iclass 21, count 2 2006.201.05:06:30.12#ibcon#enter sib2, iclass 21, count 2 2006.201.05:06:30.12#ibcon#flushed, iclass 21, count 2 2006.201.05:06:30.12#ibcon#about to write, iclass 21, count 2 2006.201.05:06:30.12#ibcon#wrote, iclass 21, count 2 2006.201.05:06:30.12#ibcon#about to read 3, iclass 21, count 2 2006.201.05:06:30.15#ibcon#read 3, iclass 21, count 2 2006.201.05:06:30.15#ibcon#about to read 4, iclass 21, count 2 2006.201.05:06:30.15#ibcon#read 4, iclass 21, count 2 2006.201.05:06:30.15#ibcon#about to read 5, iclass 21, count 2 2006.201.05:06:30.15#ibcon#read 5, iclass 21, count 2 2006.201.05:06:30.15#ibcon#about to read 6, iclass 21, count 2 2006.201.05:06:30.15#ibcon#read 6, iclass 21, count 2 2006.201.05:06:30.15#ibcon#end of sib2, iclass 21, count 2 2006.201.05:06:30.15#ibcon#*after write, iclass 21, count 2 2006.201.05:06:30.15#ibcon#*before return 0, iclass 21, count 2 2006.201.05:06:30.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:30.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:06:30.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.05:06:30.15#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:30.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:30.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:30.27#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:30.27#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:06:30.27#ibcon#first serial, iclass 21, count 0 2006.201.05:06:30.27#ibcon#enter sib2, iclass 21, count 0 2006.201.05:06:30.27#ibcon#flushed, iclass 21, count 0 2006.201.05:06:30.27#ibcon#about to write, iclass 21, count 0 2006.201.05:06:30.27#ibcon#wrote, iclass 21, count 0 2006.201.05:06:30.27#ibcon#about to read 3, iclass 21, count 0 2006.201.05:06:30.29#ibcon#read 3, iclass 21, count 0 2006.201.05:06:30.29#ibcon#about to read 4, iclass 21, count 0 2006.201.05:06:30.29#ibcon#read 4, iclass 21, count 0 2006.201.05:06:30.29#ibcon#about to read 5, iclass 21, count 0 2006.201.05:06:30.29#ibcon#read 5, iclass 21, count 0 2006.201.05:06:30.29#ibcon#about to read 6, iclass 21, count 0 2006.201.05:06:30.29#ibcon#read 6, iclass 21, count 0 2006.201.05:06:30.29#ibcon#end of sib2, iclass 21, count 0 2006.201.05:06:30.29#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:06:30.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:06:30.29#ibcon#[27=USB\r\n] 2006.201.05:06:30.29#ibcon#*before write, iclass 21, count 0 2006.201.05:06:30.29#ibcon#enter sib2, iclass 21, count 0 2006.201.05:06:30.29#ibcon#flushed, iclass 21, count 0 2006.201.05:06:30.29#ibcon#about to write, iclass 21, count 0 2006.201.05:06:30.29#ibcon#wrote, iclass 21, count 0 2006.201.05:06:30.29#ibcon#about to read 3, iclass 21, count 0 2006.201.05:06:30.32#ibcon#read 3, iclass 21, count 0 2006.201.05:06:30.32#ibcon#about to read 4, iclass 21, count 0 2006.201.05:06:30.32#ibcon#read 4, iclass 21, count 0 2006.201.05:06:30.32#ibcon#about to read 5, iclass 21, count 0 2006.201.05:06:30.32#ibcon#read 5, iclass 21, count 0 2006.201.05:06:30.32#ibcon#about to read 6, iclass 21, count 0 2006.201.05:06:30.32#ibcon#read 6, iclass 21, count 0 2006.201.05:06:30.32#ibcon#end of sib2, iclass 21, count 0 2006.201.05:06:30.32#ibcon#*after write, iclass 21, count 0 2006.201.05:06:30.32#ibcon#*before return 0, iclass 21, count 0 2006.201.05:06:30.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:30.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:06:30.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:06:30.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:06:30.32$vck44/vblo=8,744.99 2006.201.05:06:30.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.05:06:30.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.05:06:30.32#ibcon#ireg 17 cls_cnt 0 2006.201.05:06:30.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:30.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:30.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:30.32#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:06:30.32#ibcon#first serial, iclass 23, count 0 2006.201.05:06:30.32#ibcon#enter sib2, iclass 23, count 0 2006.201.05:06:30.32#ibcon#flushed, iclass 23, count 0 2006.201.05:06:30.32#ibcon#about to write, iclass 23, count 0 2006.201.05:06:30.32#ibcon#wrote, iclass 23, count 0 2006.201.05:06:30.32#ibcon#about to read 3, iclass 23, count 0 2006.201.05:06:30.34#ibcon#read 3, iclass 23, count 0 2006.201.05:06:30.34#ibcon#about to read 4, iclass 23, count 0 2006.201.05:06:30.34#ibcon#read 4, iclass 23, count 0 2006.201.05:06:30.34#ibcon#about to read 5, iclass 23, count 0 2006.201.05:06:30.34#ibcon#read 5, iclass 23, count 0 2006.201.05:06:30.34#ibcon#about to read 6, iclass 23, count 0 2006.201.05:06:30.34#ibcon#read 6, iclass 23, count 0 2006.201.05:06:30.34#ibcon#end of sib2, iclass 23, count 0 2006.201.05:06:30.34#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:06:30.34#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:06:30.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:06:30.34#ibcon#*before write, iclass 23, count 0 2006.201.05:06:30.34#ibcon#enter sib2, iclass 23, count 0 2006.201.05:06:30.34#ibcon#flushed, iclass 23, count 0 2006.201.05:06:30.34#ibcon#about to write, iclass 23, count 0 2006.201.05:06:30.34#ibcon#wrote, iclass 23, count 0 2006.201.05:06:30.34#ibcon#about to read 3, iclass 23, count 0 2006.201.05:06:30.38#ibcon#read 3, iclass 23, count 0 2006.201.05:06:30.38#ibcon#about to read 4, iclass 23, count 0 2006.201.05:06:30.38#ibcon#read 4, iclass 23, count 0 2006.201.05:06:30.38#ibcon#about to read 5, iclass 23, count 0 2006.201.05:06:30.38#ibcon#read 5, iclass 23, count 0 2006.201.05:06:30.38#ibcon#about to read 6, iclass 23, count 0 2006.201.05:06:30.38#ibcon#read 6, iclass 23, count 0 2006.201.05:06:30.38#ibcon#end of sib2, iclass 23, count 0 2006.201.05:06:30.38#ibcon#*after write, iclass 23, count 0 2006.201.05:06:30.38#ibcon#*before return 0, iclass 23, count 0 2006.201.05:06:30.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:30.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:06:30.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:06:30.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:06:30.38$vck44/vb=8,4 2006.201.05:06:30.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.05:06:30.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.05:06:30.38#ibcon#ireg 11 cls_cnt 2 2006.201.05:06:30.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:30.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:30.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:30.44#ibcon#enter wrdev, iclass 25, count 2 2006.201.05:06:30.44#ibcon#first serial, iclass 25, count 2 2006.201.05:06:30.44#ibcon#enter sib2, iclass 25, count 2 2006.201.05:06:30.44#ibcon#flushed, iclass 25, count 2 2006.201.05:06:30.44#ibcon#about to write, iclass 25, count 2 2006.201.05:06:30.44#ibcon#wrote, iclass 25, count 2 2006.201.05:06:30.44#ibcon#about to read 3, iclass 25, count 2 2006.201.05:06:30.46#ibcon#read 3, iclass 25, count 2 2006.201.05:06:30.46#ibcon#about to read 4, iclass 25, count 2 2006.201.05:06:30.46#ibcon#read 4, iclass 25, count 2 2006.201.05:06:30.46#ibcon#about to read 5, iclass 25, count 2 2006.201.05:06:30.46#ibcon#read 5, iclass 25, count 2 2006.201.05:06:30.46#ibcon#about to read 6, iclass 25, count 2 2006.201.05:06:30.46#ibcon#read 6, iclass 25, count 2 2006.201.05:06:30.46#ibcon#end of sib2, iclass 25, count 2 2006.201.05:06:30.46#ibcon#*mode == 0, iclass 25, count 2 2006.201.05:06:30.46#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.05:06:30.46#ibcon#[27=AT08-04\r\n] 2006.201.05:06:30.46#ibcon#*before write, iclass 25, count 2 2006.201.05:06:30.46#ibcon#enter sib2, iclass 25, count 2 2006.201.05:06:30.46#ibcon#flushed, iclass 25, count 2 2006.201.05:06:30.46#ibcon#about to write, iclass 25, count 2 2006.201.05:06:30.46#ibcon#wrote, iclass 25, count 2 2006.201.05:06:30.46#ibcon#about to read 3, iclass 25, count 2 2006.201.05:06:30.49#ibcon#read 3, iclass 25, count 2 2006.201.05:06:30.49#ibcon#about to read 4, iclass 25, count 2 2006.201.05:06:30.49#ibcon#read 4, iclass 25, count 2 2006.201.05:06:30.49#ibcon#about to read 5, iclass 25, count 2 2006.201.05:06:30.49#ibcon#read 5, iclass 25, count 2 2006.201.05:06:30.49#ibcon#about to read 6, iclass 25, count 2 2006.201.05:06:30.49#ibcon#read 6, iclass 25, count 2 2006.201.05:06:30.49#ibcon#end of sib2, iclass 25, count 2 2006.201.05:06:30.49#ibcon#*after write, iclass 25, count 2 2006.201.05:06:30.49#ibcon#*before return 0, iclass 25, count 2 2006.201.05:06:30.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:30.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:06:30.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.05:06:30.49#ibcon#ireg 7 cls_cnt 0 2006.201.05:06:30.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:30.61#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:30.61#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:30.61#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:06:30.61#ibcon#first serial, iclass 25, count 0 2006.201.05:06:30.61#ibcon#enter sib2, iclass 25, count 0 2006.201.05:06:30.61#ibcon#flushed, iclass 25, count 0 2006.201.05:06:30.61#ibcon#about to write, iclass 25, count 0 2006.201.05:06:30.61#ibcon#wrote, iclass 25, count 0 2006.201.05:06:30.61#ibcon#about to read 3, iclass 25, count 0 2006.201.05:06:30.63#ibcon#read 3, iclass 25, count 0 2006.201.05:06:30.63#ibcon#about to read 4, iclass 25, count 0 2006.201.05:06:30.63#ibcon#read 4, iclass 25, count 0 2006.201.05:06:30.63#ibcon#about to read 5, iclass 25, count 0 2006.201.05:06:30.63#ibcon#read 5, iclass 25, count 0 2006.201.05:06:30.63#ibcon#about to read 6, iclass 25, count 0 2006.201.05:06:30.63#ibcon#read 6, iclass 25, count 0 2006.201.05:06:30.63#ibcon#end of sib2, iclass 25, count 0 2006.201.05:06:30.63#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:06:30.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:06:30.63#ibcon#[27=USB\r\n] 2006.201.05:06:30.63#ibcon#*before write, iclass 25, count 0 2006.201.05:06:30.63#ibcon#enter sib2, iclass 25, count 0 2006.201.05:06:30.63#ibcon#flushed, iclass 25, count 0 2006.201.05:06:30.63#ibcon#about to write, iclass 25, count 0 2006.201.05:06:30.63#ibcon#wrote, iclass 25, count 0 2006.201.05:06:30.63#ibcon#about to read 3, iclass 25, count 0 2006.201.05:06:30.66#ibcon#read 3, iclass 25, count 0 2006.201.05:06:30.66#ibcon#about to read 4, iclass 25, count 0 2006.201.05:06:30.66#ibcon#read 4, iclass 25, count 0 2006.201.05:06:30.66#ibcon#about to read 5, iclass 25, count 0 2006.201.05:06:30.66#ibcon#read 5, iclass 25, count 0 2006.201.05:06:30.66#ibcon#about to read 6, iclass 25, count 0 2006.201.05:06:30.66#ibcon#read 6, iclass 25, count 0 2006.201.05:06:30.66#ibcon#end of sib2, iclass 25, count 0 2006.201.05:06:30.66#ibcon#*after write, iclass 25, count 0 2006.201.05:06:30.66#ibcon#*before return 0, iclass 25, count 0 2006.201.05:06:30.66#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:30.66#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:06:30.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:06:30.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:06:30.66$vck44/vabw=wide 2006.201.05:06:30.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.05:06:30.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.05:06:30.66#ibcon#ireg 8 cls_cnt 0 2006.201.05:06:30.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:30.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:30.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:30.66#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:06:30.66#ibcon#first serial, iclass 27, count 0 2006.201.05:06:30.66#ibcon#enter sib2, iclass 27, count 0 2006.201.05:06:30.66#ibcon#flushed, iclass 27, count 0 2006.201.05:06:30.66#ibcon#about to write, iclass 27, count 0 2006.201.05:06:30.66#ibcon#wrote, iclass 27, count 0 2006.201.05:06:30.66#ibcon#about to read 3, iclass 27, count 0 2006.201.05:06:30.68#ibcon#read 3, iclass 27, count 0 2006.201.05:06:30.68#ibcon#about to read 4, iclass 27, count 0 2006.201.05:06:30.68#ibcon#read 4, iclass 27, count 0 2006.201.05:06:30.68#ibcon#about to read 5, iclass 27, count 0 2006.201.05:06:30.68#ibcon#read 5, iclass 27, count 0 2006.201.05:06:30.68#ibcon#about to read 6, iclass 27, count 0 2006.201.05:06:30.68#ibcon#read 6, iclass 27, count 0 2006.201.05:06:30.68#ibcon#end of sib2, iclass 27, count 0 2006.201.05:06:30.68#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:06:30.68#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:06:30.68#ibcon#[25=BW32\r\n] 2006.201.05:06:30.68#ibcon#*before write, iclass 27, count 0 2006.201.05:06:30.68#ibcon#enter sib2, iclass 27, count 0 2006.201.05:06:30.68#ibcon#flushed, iclass 27, count 0 2006.201.05:06:30.68#ibcon#about to write, iclass 27, count 0 2006.201.05:06:30.68#ibcon#wrote, iclass 27, count 0 2006.201.05:06:30.68#ibcon#about to read 3, iclass 27, count 0 2006.201.05:06:30.71#ibcon#read 3, iclass 27, count 0 2006.201.05:06:30.71#ibcon#about to read 4, iclass 27, count 0 2006.201.05:06:30.71#ibcon#read 4, iclass 27, count 0 2006.201.05:06:30.71#ibcon#about to read 5, iclass 27, count 0 2006.201.05:06:30.71#ibcon#read 5, iclass 27, count 0 2006.201.05:06:30.71#ibcon#about to read 6, iclass 27, count 0 2006.201.05:06:30.71#ibcon#read 6, iclass 27, count 0 2006.201.05:06:30.71#ibcon#end of sib2, iclass 27, count 0 2006.201.05:06:30.71#ibcon#*after write, iclass 27, count 0 2006.201.05:06:30.71#ibcon#*before return 0, iclass 27, count 0 2006.201.05:06:30.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:30.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:06:30.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:06:30.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:06:30.71$vck44/vbbw=wide 2006.201.05:06:30.71#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:06:30.71#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:06:30.71#ibcon#ireg 8 cls_cnt 0 2006.201.05:06:30.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:06:30.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:06:30.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:06:30.78#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:06:30.78#ibcon#first serial, iclass 29, count 0 2006.201.05:06:30.78#ibcon#enter sib2, iclass 29, count 0 2006.201.05:06:30.78#ibcon#flushed, iclass 29, count 0 2006.201.05:06:30.78#ibcon#about to write, iclass 29, count 0 2006.201.05:06:30.78#ibcon#wrote, iclass 29, count 0 2006.201.05:06:30.78#ibcon#about to read 3, iclass 29, count 0 2006.201.05:06:30.80#ibcon#read 3, iclass 29, count 0 2006.201.05:06:30.80#ibcon#about to read 4, iclass 29, count 0 2006.201.05:06:30.80#ibcon#read 4, iclass 29, count 0 2006.201.05:06:30.80#ibcon#about to read 5, iclass 29, count 0 2006.201.05:06:30.80#ibcon#read 5, iclass 29, count 0 2006.201.05:06:30.80#ibcon#about to read 6, iclass 29, count 0 2006.201.05:06:30.80#ibcon#read 6, iclass 29, count 0 2006.201.05:06:30.80#ibcon#end of sib2, iclass 29, count 0 2006.201.05:06:30.80#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:06:30.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:06:30.80#ibcon#[27=BW32\r\n] 2006.201.05:06:30.80#ibcon#*before write, iclass 29, count 0 2006.201.05:06:30.80#ibcon#enter sib2, iclass 29, count 0 2006.201.05:06:30.80#ibcon#flushed, iclass 29, count 0 2006.201.05:06:30.80#ibcon#about to write, iclass 29, count 0 2006.201.05:06:30.80#ibcon#wrote, iclass 29, count 0 2006.201.05:06:30.80#ibcon#about to read 3, iclass 29, count 0 2006.201.05:06:30.89#ibcon#read 3, iclass 29, count 0 2006.201.05:06:30.89#ibcon#about to read 4, iclass 29, count 0 2006.201.05:06:30.89#ibcon#read 4, iclass 29, count 0 2006.201.05:06:30.89#ibcon#about to read 5, iclass 29, count 0 2006.201.05:06:30.89#ibcon#read 5, iclass 29, count 0 2006.201.05:06:30.89#ibcon#about to read 6, iclass 29, count 0 2006.201.05:06:30.89#ibcon#read 6, iclass 29, count 0 2006.201.05:06:30.89#ibcon#end of sib2, iclass 29, count 0 2006.201.05:06:30.89#ibcon#*after write, iclass 29, count 0 2006.201.05:06:30.89#ibcon#*before return 0, iclass 29, count 0 2006.201.05:06:30.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:06:30.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:06:30.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:06:30.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:06:30.90$setupk4/ifdk4 2006.201.05:06:30.90$ifdk4/lo= 2006.201.05:06:30.90$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:06:30.90$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:06:30.90$ifdk4/patch= 2006.201.05:06:30.90$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:06:30.90$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:06:30.90$setupk4/!*+20s 2006.201.05:06:33.64#abcon#<5=/05 3.6 6.8 23.28 901003.8\r\n> 2006.201.05:06:33.66#abcon#{5=INTERFACE CLEAR} 2006.201.05:06:33.72#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:06:43.81#abcon#<5=/05 3.6 6.8 23.28 901003.8\r\n> 2006.201.05:06:43.83#abcon#{5=INTERFACE CLEAR} 2006.201.05:06:43.89#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:06:45.25$setupk4/"tpicd 2006.201.05:06:45.25$setupk4/echo=off 2006.201.05:06:45.25$setupk4/xlog=off 2006.201.05:06:45.25:!2006.201.05:13:42 2006.201.05:06:47.14#trakl#Source acquired 2006.201.05:06:48.14#flagr#flagr/antenna,acquired 2006.201.05:13:42.00:preob 2006.201.05:13:43.14/onsource/TRACKING 2006.201.05:13:43.14:!2006.201.05:13:52 2006.201.05:13:52.00:"tape 2006.201.05:13:52.00:"st=record 2006.201.05:13:52.00:data_valid=on 2006.201.05:13:52.01:midob 2006.201.05:13:53.14/onsource/TRACKING 2006.201.05:13:53.14/wx/23.34,1003.7,89 2006.201.05:13:53.23/cable/+6.4644E-03 2006.201.05:13:54.32/va/01,08,usb,yes,30,32 2006.201.05:13:54.32/va/02,07,usb,yes,32,33 2006.201.05:13:54.32/va/03,08,usb,yes,29,30 2006.201.05:13:54.32/va/04,07,usb,yes,33,35 2006.201.05:13:54.32/va/05,04,usb,yes,29,30 2006.201.05:13:54.32/va/06,05,usb,yes,29,29 2006.201.05:13:54.32/va/07,05,usb,yes,29,30 2006.201.05:13:54.32/va/08,04,usb,yes,28,34 2006.201.05:13:54.55/valo/01,524.99,yes,locked 2006.201.05:13:54.55/valo/02,534.99,yes,locked 2006.201.05:13:54.55/valo/03,564.99,yes,locked 2006.201.05:13:54.55/valo/04,624.99,yes,locked 2006.201.05:13:54.55/valo/05,734.99,yes,locked 2006.201.05:13:54.55/valo/06,814.99,yes,locked 2006.201.05:13:54.55/valo/07,864.99,yes,locked 2006.201.05:13:54.55/valo/08,884.99,yes,locked 2006.201.05:13:55.64/vb/01,04,usb,yes,30,28 2006.201.05:13:55.64/vb/02,05,usb,yes,28,28 2006.201.05:13:55.64/vb/03,04,usb,yes,29,32 2006.201.05:13:55.64/vb/04,05,usb,yes,29,28 2006.201.05:13:55.64/vb/05,04,usb,yes,26,28 2006.201.05:13:55.64/vb/06,04,usb,yes,30,27 2006.201.05:13:55.64/vb/07,04,usb,yes,30,30 2006.201.05:13:55.64/vb/08,04,usb,yes,28,31 2006.201.05:13:55.87/vblo/01,629.99,yes,locked 2006.201.05:13:55.87/vblo/02,634.99,yes,locked 2006.201.05:13:55.87/vblo/03,649.99,yes,locked 2006.201.05:13:55.87/vblo/04,679.99,yes,locked 2006.201.05:13:55.87/vblo/05,709.99,yes,locked 2006.201.05:13:55.87/vblo/06,719.99,yes,locked 2006.201.05:13:55.87/vblo/07,734.99,yes,locked 2006.201.05:13:55.87/vblo/08,744.99,yes,locked 2006.201.05:13:56.02/vabw/8 2006.201.05:13:56.17/vbbw/8 2006.201.05:13:56.37/xfe/off,on,15.2 2006.201.05:13:56.75/ifatt/23,28,28,28 2006.201.05:13:57.04/fmout-gps/S +4.49E-07 2006.201.05:13:57.08:!2006.201.05:15:02 2006.201.05:15:02.00:data_valid=off 2006.201.05:15:02.00:"et 2006.201.05:15:02.00:!+3s 2006.201.05:15:05.02:"tape 2006.201.05:15:05.02:postob 2006.201.05:15:05.22/cable/+6.4653E-03 2006.201.05:15:05.22/wx/23.34,1003.8,90 2006.201.05:15:05.28/fmout-gps/S +4.48E-07 2006.201.05:15:05.28:scan_name=201-0524,jd0607,220 2006.201.05:15:05.28:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.201.05:15:06.14#flagr#flagr/antenna,new-source 2006.201.05:15:06.14:checkk5 2006.201.05:15:06.55/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:15:06.94/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:15:07.34/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:15:07.75/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:15:08.15/chk_obsdata//k5ts1/T2010513??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.05:15:08.55/chk_obsdata//k5ts2/T2010513??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.05:15:08.95/chk_obsdata//k5ts3/T2010513??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.05:15:09.38/chk_obsdata//k5ts4/T2010513??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.05:15:10.12/k5log//k5ts1_log_newline 2006.201.05:15:10.84/k5log//k5ts2_log_newline 2006.201.05:15:11.54/k5log//k5ts3_log_newline 2006.201.05:15:12.26/k5log//k5ts4_log_newline 2006.201.05:15:12.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:15:12.28:setupk4=1 2006.201.05:15:12.28$setupk4/echo=on 2006.201.05:15:12.28$setupk4/pcalon 2006.201.05:15:12.29$pcalon/"no phase cal control is implemented here 2006.201.05:15:12.29$setupk4/"tpicd=stop 2006.201.05:15:12.29$setupk4/"rec=synch_on 2006.201.05:15:12.29$setupk4/"rec_mode=128 2006.201.05:15:12.29$setupk4/!* 2006.201.05:15:12.29$setupk4/recpk4 2006.201.05:15:12.29$recpk4/recpatch= 2006.201.05:15:12.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:15:12.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:15:12.29$setupk4/vck44 2006.201.05:15:12.29$vck44/valo=1,524.99 2006.201.05:15:12.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.05:15:12.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.05:15:12.29#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:12.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:12.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:12.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:12.29#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:15:12.29#ibcon#first serial, iclass 17, count 0 2006.201.05:15:12.29#ibcon#enter sib2, iclass 17, count 0 2006.201.05:15:12.29#ibcon#flushed, iclass 17, count 0 2006.201.05:15:12.29#ibcon#about to write, iclass 17, count 0 2006.201.05:15:12.29#ibcon#wrote, iclass 17, count 0 2006.201.05:15:12.29#ibcon#about to read 3, iclass 17, count 0 2006.201.05:15:12.31#ibcon#read 3, iclass 17, count 0 2006.201.05:15:12.31#ibcon#about to read 4, iclass 17, count 0 2006.201.05:15:12.31#ibcon#read 4, iclass 17, count 0 2006.201.05:15:12.31#ibcon#about to read 5, iclass 17, count 0 2006.201.05:15:12.31#ibcon#read 5, iclass 17, count 0 2006.201.05:15:12.31#ibcon#about to read 6, iclass 17, count 0 2006.201.05:15:12.31#ibcon#read 6, iclass 17, count 0 2006.201.05:15:12.31#ibcon#end of sib2, iclass 17, count 0 2006.201.05:15:12.31#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:15:12.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:15:12.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:15:12.31#ibcon#*before write, iclass 17, count 0 2006.201.05:15:12.31#ibcon#enter sib2, iclass 17, count 0 2006.201.05:15:12.31#ibcon#flushed, iclass 17, count 0 2006.201.05:15:12.31#ibcon#about to write, iclass 17, count 0 2006.201.05:15:12.31#ibcon#wrote, iclass 17, count 0 2006.201.05:15:12.31#ibcon#about to read 3, iclass 17, count 0 2006.201.05:15:12.36#ibcon#read 3, iclass 17, count 0 2006.201.05:15:12.36#ibcon#about to read 4, iclass 17, count 0 2006.201.05:15:12.36#ibcon#read 4, iclass 17, count 0 2006.201.05:15:12.36#ibcon#about to read 5, iclass 17, count 0 2006.201.05:15:12.36#ibcon#read 5, iclass 17, count 0 2006.201.05:15:12.36#ibcon#about to read 6, iclass 17, count 0 2006.201.05:15:12.36#ibcon#read 6, iclass 17, count 0 2006.201.05:15:12.36#ibcon#end of sib2, iclass 17, count 0 2006.201.05:15:12.36#ibcon#*after write, iclass 17, count 0 2006.201.05:15:12.36#ibcon#*before return 0, iclass 17, count 0 2006.201.05:15:12.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:12.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:12.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:15:12.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:15:12.36$vck44/va=1,8 2006.201.05:15:12.36#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.05:15:12.36#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.05:15:12.36#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:12.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:12.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:12.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:12.36#ibcon#enter wrdev, iclass 19, count 2 2006.201.05:15:12.36#ibcon#first serial, iclass 19, count 2 2006.201.05:15:12.36#ibcon#enter sib2, iclass 19, count 2 2006.201.05:15:12.36#ibcon#flushed, iclass 19, count 2 2006.201.05:15:12.36#ibcon#about to write, iclass 19, count 2 2006.201.05:15:12.36#ibcon#wrote, iclass 19, count 2 2006.201.05:15:12.36#ibcon#about to read 3, iclass 19, count 2 2006.201.05:15:12.38#ibcon#read 3, iclass 19, count 2 2006.201.05:15:12.38#ibcon#about to read 4, iclass 19, count 2 2006.201.05:15:12.38#ibcon#read 4, iclass 19, count 2 2006.201.05:15:12.38#ibcon#about to read 5, iclass 19, count 2 2006.201.05:15:12.38#ibcon#read 5, iclass 19, count 2 2006.201.05:15:12.38#ibcon#about to read 6, iclass 19, count 2 2006.201.05:15:12.38#ibcon#read 6, iclass 19, count 2 2006.201.05:15:12.38#ibcon#end of sib2, iclass 19, count 2 2006.201.05:15:12.38#ibcon#*mode == 0, iclass 19, count 2 2006.201.05:15:12.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.05:15:12.38#ibcon#[25=AT01-08\r\n] 2006.201.05:15:12.38#ibcon#*before write, iclass 19, count 2 2006.201.05:15:12.38#ibcon#enter sib2, iclass 19, count 2 2006.201.05:15:12.38#ibcon#flushed, iclass 19, count 2 2006.201.05:15:12.38#ibcon#about to write, iclass 19, count 2 2006.201.05:15:12.38#ibcon#wrote, iclass 19, count 2 2006.201.05:15:12.38#ibcon#about to read 3, iclass 19, count 2 2006.201.05:15:12.41#ibcon#read 3, iclass 19, count 2 2006.201.05:15:12.41#ibcon#about to read 4, iclass 19, count 2 2006.201.05:15:12.41#ibcon#read 4, iclass 19, count 2 2006.201.05:15:12.41#ibcon#about to read 5, iclass 19, count 2 2006.201.05:15:12.41#ibcon#read 5, iclass 19, count 2 2006.201.05:15:12.41#ibcon#about to read 6, iclass 19, count 2 2006.201.05:15:12.41#ibcon#read 6, iclass 19, count 2 2006.201.05:15:12.41#ibcon#end of sib2, iclass 19, count 2 2006.201.05:15:12.41#ibcon#*after write, iclass 19, count 2 2006.201.05:15:12.41#ibcon#*before return 0, iclass 19, count 2 2006.201.05:15:12.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:12.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:12.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.05:15:12.41#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:12.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:12.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:12.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:12.53#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:15:12.53#ibcon#first serial, iclass 19, count 0 2006.201.05:15:12.53#ibcon#enter sib2, iclass 19, count 0 2006.201.05:15:12.53#ibcon#flushed, iclass 19, count 0 2006.201.05:15:12.53#ibcon#about to write, iclass 19, count 0 2006.201.05:15:12.53#ibcon#wrote, iclass 19, count 0 2006.201.05:15:12.53#ibcon#about to read 3, iclass 19, count 0 2006.201.05:15:12.55#ibcon#read 3, iclass 19, count 0 2006.201.05:15:12.55#ibcon#about to read 4, iclass 19, count 0 2006.201.05:15:12.55#ibcon#read 4, iclass 19, count 0 2006.201.05:15:12.55#ibcon#about to read 5, iclass 19, count 0 2006.201.05:15:12.55#ibcon#read 5, iclass 19, count 0 2006.201.05:15:12.55#ibcon#about to read 6, iclass 19, count 0 2006.201.05:15:12.55#ibcon#read 6, iclass 19, count 0 2006.201.05:15:12.55#ibcon#end of sib2, iclass 19, count 0 2006.201.05:15:12.55#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:15:12.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:15:12.55#ibcon#[25=USB\r\n] 2006.201.05:15:12.55#ibcon#*before write, iclass 19, count 0 2006.201.05:15:12.55#ibcon#enter sib2, iclass 19, count 0 2006.201.05:15:12.55#ibcon#flushed, iclass 19, count 0 2006.201.05:15:12.55#ibcon#about to write, iclass 19, count 0 2006.201.05:15:12.55#ibcon#wrote, iclass 19, count 0 2006.201.05:15:12.55#ibcon#about to read 3, iclass 19, count 0 2006.201.05:15:12.58#ibcon#read 3, iclass 19, count 0 2006.201.05:15:12.58#ibcon#about to read 4, iclass 19, count 0 2006.201.05:15:12.58#ibcon#read 4, iclass 19, count 0 2006.201.05:15:12.58#ibcon#about to read 5, iclass 19, count 0 2006.201.05:15:12.58#ibcon#read 5, iclass 19, count 0 2006.201.05:15:12.58#ibcon#about to read 6, iclass 19, count 0 2006.201.05:15:12.58#ibcon#read 6, iclass 19, count 0 2006.201.05:15:12.58#ibcon#end of sib2, iclass 19, count 0 2006.201.05:15:12.58#ibcon#*after write, iclass 19, count 0 2006.201.05:15:12.58#ibcon#*before return 0, iclass 19, count 0 2006.201.05:15:12.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:12.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:12.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:15:12.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:15:12.58$vck44/valo=2,534.99 2006.201.05:15:12.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.05:15:12.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.05:15:12.58#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:12.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:12.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:12.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:12.58#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:15:12.58#ibcon#first serial, iclass 21, count 0 2006.201.05:15:12.58#ibcon#enter sib2, iclass 21, count 0 2006.201.05:15:12.58#ibcon#flushed, iclass 21, count 0 2006.201.05:15:12.58#ibcon#about to write, iclass 21, count 0 2006.201.05:15:12.58#ibcon#wrote, iclass 21, count 0 2006.201.05:15:12.58#ibcon#about to read 3, iclass 21, count 0 2006.201.05:15:12.60#ibcon#read 3, iclass 21, count 0 2006.201.05:15:12.60#ibcon#about to read 4, iclass 21, count 0 2006.201.05:15:12.60#ibcon#read 4, iclass 21, count 0 2006.201.05:15:12.60#ibcon#about to read 5, iclass 21, count 0 2006.201.05:15:12.60#ibcon#read 5, iclass 21, count 0 2006.201.05:15:12.60#ibcon#about to read 6, iclass 21, count 0 2006.201.05:15:12.60#ibcon#read 6, iclass 21, count 0 2006.201.05:15:12.60#ibcon#end of sib2, iclass 21, count 0 2006.201.05:15:12.60#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:15:12.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:15:12.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:15:12.60#ibcon#*before write, iclass 21, count 0 2006.201.05:15:12.60#ibcon#enter sib2, iclass 21, count 0 2006.201.05:15:12.60#ibcon#flushed, iclass 21, count 0 2006.201.05:15:12.60#ibcon#about to write, iclass 21, count 0 2006.201.05:15:12.60#ibcon#wrote, iclass 21, count 0 2006.201.05:15:12.60#ibcon#about to read 3, iclass 21, count 0 2006.201.05:15:12.64#ibcon#read 3, iclass 21, count 0 2006.201.05:15:12.64#ibcon#about to read 4, iclass 21, count 0 2006.201.05:15:12.64#ibcon#read 4, iclass 21, count 0 2006.201.05:15:12.64#ibcon#about to read 5, iclass 21, count 0 2006.201.05:15:12.64#ibcon#read 5, iclass 21, count 0 2006.201.05:15:12.64#ibcon#about to read 6, iclass 21, count 0 2006.201.05:15:12.64#ibcon#read 6, iclass 21, count 0 2006.201.05:15:12.64#ibcon#end of sib2, iclass 21, count 0 2006.201.05:15:12.64#ibcon#*after write, iclass 21, count 0 2006.201.05:15:12.64#ibcon#*before return 0, iclass 21, count 0 2006.201.05:15:12.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:12.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:12.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:15:12.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:15:12.64$vck44/va=2,7 2006.201.05:15:12.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.05:15:12.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.05:15:12.64#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:12.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:12.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:12.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:12.70#ibcon#enter wrdev, iclass 23, count 2 2006.201.05:15:12.70#ibcon#first serial, iclass 23, count 2 2006.201.05:15:12.70#ibcon#enter sib2, iclass 23, count 2 2006.201.05:15:12.70#ibcon#flushed, iclass 23, count 2 2006.201.05:15:12.70#ibcon#about to write, iclass 23, count 2 2006.201.05:15:12.70#ibcon#wrote, iclass 23, count 2 2006.201.05:15:12.70#ibcon#about to read 3, iclass 23, count 2 2006.201.05:15:12.72#ibcon#read 3, iclass 23, count 2 2006.201.05:15:12.72#ibcon#about to read 4, iclass 23, count 2 2006.201.05:15:12.72#ibcon#read 4, iclass 23, count 2 2006.201.05:15:12.72#ibcon#about to read 5, iclass 23, count 2 2006.201.05:15:12.72#ibcon#read 5, iclass 23, count 2 2006.201.05:15:12.72#ibcon#about to read 6, iclass 23, count 2 2006.201.05:15:12.72#ibcon#read 6, iclass 23, count 2 2006.201.05:15:12.72#ibcon#end of sib2, iclass 23, count 2 2006.201.05:15:12.72#ibcon#*mode == 0, iclass 23, count 2 2006.201.05:15:12.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.05:15:12.72#ibcon#[25=AT02-07\r\n] 2006.201.05:15:12.72#ibcon#*before write, iclass 23, count 2 2006.201.05:15:12.72#ibcon#enter sib2, iclass 23, count 2 2006.201.05:15:12.72#ibcon#flushed, iclass 23, count 2 2006.201.05:15:12.72#ibcon#about to write, iclass 23, count 2 2006.201.05:15:12.72#ibcon#wrote, iclass 23, count 2 2006.201.05:15:12.72#ibcon#about to read 3, iclass 23, count 2 2006.201.05:15:12.75#ibcon#read 3, iclass 23, count 2 2006.201.05:15:12.75#ibcon#about to read 4, iclass 23, count 2 2006.201.05:15:12.75#ibcon#read 4, iclass 23, count 2 2006.201.05:15:12.75#ibcon#about to read 5, iclass 23, count 2 2006.201.05:15:12.75#ibcon#read 5, iclass 23, count 2 2006.201.05:15:12.75#ibcon#about to read 6, iclass 23, count 2 2006.201.05:15:12.75#ibcon#read 6, iclass 23, count 2 2006.201.05:15:12.75#ibcon#end of sib2, iclass 23, count 2 2006.201.05:15:12.75#ibcon#*after write, iclass 23, count 2 2006.201.05:15:12.75#ibcon#*before return 0, iclass 23, count 2 2006.201.05:15:12.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:12.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:12.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.05:15:12.75#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:12.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:12.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:12.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:12.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:15:12.87#ibcon#first serial, iclass 23, count 0 2006.201.05:15:12.87#ibcon#enter sib2, iclass 23, count 0 2006.201.05:15:12.87#ibcon#flushed, iclass 23, count 0 2006.201.05:15:12.87#ibcon#about to write, iclass 23, count 0 2006.201.05:15:12.87#ibcon#wrote, iclass 23, count 0 2006.201.05:15:12.87#ibcon#about to read 3, iclass 23, count 0 2006.201.05:15:12.89#ibcon#read 3, iclass 23, count 0 2006.201.05:15:12.89#ibcon#about to read 4, iclass 23, count 0 2006.201.05:15:12.89#ibcon#read 4, iclass 23, count 0 2006.201.05:15:12.89#ibcon#about to read 5, iclass 23, count 0 2006.201.05:15:12.89#ibcon#read 5, iclass 23, count 0 2006.201.05:15:12.89#ibcon#about to read 6, iclass 23, count 0 2006.201.05:15:12.89#ibcon#read 6, iclass 23, count 0 2006.201.05:15:12.89#ibcon#end of sib2, iclass 23, count 0 2006.201.05:15:12.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:15:12.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:15:12.89#ibcon#[25=USB\r\n] 2006.201.05:15:12.89#ibcon#*before write, iclass 23, count 0 2006.201.05:15:12.89#ibcon#enter sib2, iclass 23, count 0 2006.201.05:15:12.89#ibcon#flushed, iclass 23, count 0 2006.201.05:15:12.89#ibcon#about to write, iclass 23, count 0 2006.201.05:15:12.89#ibcon#wrote, iclass 23, count 0 2006.201.05:15:12.89#ibcon#about to read 3, iclass 23, count 0 2006.201.05:15:12.92#ibcon#read 3, iclass 23, count 0 2006.201.05:15:12.92#ibcon#about to read 4, iclass 23, count 0 2006.201.05:15:12.92#ibcon#read 4, iclass 23, count 0 2006.201.05:15:12.92#ibcon#about to read 5, iclass 23, count 0 2006.201.05:15:12.92#ibcon#read 5, iclass 23, count 0 2006.201.05:15:12.92#ibcon#about to read 6, iclass 23, count 0 2006.201.05:15:12.92#ibcon#read 6, iclass 23, count 0 2006.201.05:15:12.92#ibcon#end of sib2, iclass 23, count 0 2006.201.05:15:12.92#ibcon#*after write, iclass 23, count 0 2006.201.05:15:12.92#ibcon#*before return 0, iclass 23, count 0 2006.201.05:15:12.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:12.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:12.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:15:12.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:15:12.92$vck44/valo=3,564.99 2006.201.05:15:12.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.05:15:12.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.05:15:12.92#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:12.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:12.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:12.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:12.92#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:15:12.92#ibcon#first serial, iclass 25, count 0 2006.201.05:15:12.92#ibcon#enter sib2, iclass 25, count 0 2006.201.05:15:12.92#ibcon#flushed, iclass 25, count 0 2006.201.05:15:12.92#ibcon#about to write, iclass 25, count 0 2006.201.05:15:12.92#ibcon#wrote, iclass 25, count 0 2006.201.05:15:12.92#ibcon#about to read 3, iclass 25, count 0 2006.201.05:15:12.94#ibcon#read 3, iclass 25, count 0 2006.201.05:15:12.94#ibcon#about to read 4, iclass 25, count 0 2006.201.05:15:12.94#ibcon#read 4, iclass 25, count 0 2006.201.05:15:12.94#ibcon#about to read 5, iclass 25, count 0 2006.201.05:15:12.94#ibcon#read 5, iclass 25, count 0 2006.201.05:15:12.94#ibcon#about to read 6, iclass 25, count 0 2006.201.05:15:12.94#ibcon#read 6, iclass 25, count 0 2006.201.05:15:12.94#ibcon#end of sib2, iclass 25, count 0 2006.201.05:15:12.94#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:15:12.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:15:12.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:15:12.94#ibcon#*before write, iclass 25, count 0 2006.201.05:15:12.94#ibcon#enter sib2, iclass 25, count 0 2006.201.05:15:12.94#ibcon#flushed, iclass 25, count 0 2006.201.05:15:12.94#ibcon#about to write, iclass 25, count 0 2006.201.05:15:12.94#ibcon#wrote, iclass 25, count 0 2006.201.05:15:12.94#ibcon#about to read 3, iclass 25, count 0 2006.201.05:15:12.98#ibcon#read 3, iclass 25, count 0 2006.201.05:15:12.98#ibcon#about to read 4, iclass 25, count 0 2006.201.05:15:12.98#ibcon#read 4, iclass 25, count 0 2006.201.05:15:12.98#ibcon#about to read 5, iclass 25, count 0 2006.201.05:15:12.98#ibcon#read 5, iclass 25, count 0 2006.201.05:15:12.98#ibcon#about to read 6, iclass 25, count 0 2006.201.05:15:12.98#ibcon#read 6, iclass 25, count 0 2006.201.05:15:12.98#ibcon#end of sib2, iclass 25, count 0 2006.201.05:15:12.98#ibcon#*after write, iclass 25, count 0 2006.201.05:15:12.98#ibcon#*before return 0, iclass 25, count 0 2006.201.05:15:12.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:12.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:12.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:15:12.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:15:12.98$vck44/va=3,8 2006.201.05:15:12.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.05:15:12.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.05:15:12.98#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:12.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:13.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:13.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:13.04#ibcon#enter wrdev, iclass 27, count 2 2006.201.05:15:13.04#ibcon#first serial, iclass 27, count 2 2006.201.05:15:13.04#ibcon#enter sib2, iclass 27, count 2 2006.201.05:15:13.04#ibcon#flushed, iclass 27, count 2 2006.201.05:15:13.04#ibcon#about to write, iclass 27, count 2 2006.201.05:15:13.04#ibcon#wrote, iclass 27, count 2 2006.201.05:15:13.04#ibcon#about to read 3, iclass 27, count 2 2006.201.05:15:13.06#ibcon#read 3, iclass 27, count 2 2006.201.05:15:13.06#ibcon#about to read 4, iclass 27, count 2 2006.201.05:15:13.06#ibcon#read 4, iclass 27, count 2 2006.201.05:15:13.06#ibcon#about to read 5, iclass 27, count 2 2006.201.05:15:13.06#ibcon#read 5, iclass 27, count 2 2006.201.05:15:13.06#ibcon#about to read 6, iclass 27, count 2 2006.201.05:15:13.06#ibcon#read 6, iclass 27, count 2 2006.201.05:15:13.06#ibcon#end of sib2, iclass 27, count 2 2006.201.05:15:13.06#ibcon#*mode == 0, iclass 27, count 2 2006.201.05:15:13.06#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.05:15:13.06#ibcon#[25=AT03-08\r\n] 2006.201.05:15:13.06#ibcon#*before write, iclass 27, count 2 2006.201.05:15:13.06#ibcon#enter sib2, iclass 27, count 2 2006.201.05:15:13.06#ibcon#flushed, iclass 27, count 2 2006.201.05:15:13.06#ibcon#about to write, iclass 27, count 2 2006.201.05:15:13.06#ibcon#wrote, iclass 27, count 2 2006.201.05:15:13.06#ibcon#about to read 3, iclass 27, count 2 2006.201.05:15:13.09#ibcon#read 3, iclass 27, count 2 2006.201.05:15:13.09#ibcon#about to read 4, iclass 27, count 2 2006.201.05:15:13.09#ibcon#read 4, iclass 27, count 2 2006.201.05:15:13.09#ibcon#about to read 5, iclass 27, count 2 2006.201.05:15:13.09#ibcon#read 5, iclass 27, count 2 2006.201.05:15:13.09#ibcon#about to read 6, iclass 27, count 2 2006.201.05:15:13.09#ibcon#read 6, iclass 27, count 2 2006.201.05:15:13.09#ibcon#end of sib2, iclass 27, count 2 2006.201.05:15:13.09#ibcon#*after write, iclass 27, count 2 2006.201.05:15:13.09#ibcon#*before return 0, iclass 27, count 2 2006.201.05:15:13.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:13.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:13.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.05:15:13.09#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:13.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:13.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:13.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:13.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:15:13.21#ibcon#first serial, iclass 27, count 0 2006.201.05:15:13.21#ibcon#enter sib2, iclass 27, count 0 2006.201.05:15:13.21#ibcon#flushed, iclass 27, count 0 2006.201.05:15:13.21#ibcon#about to write, iclass 27, count 0 2006.201.05:15:13.21#ibcon#wrote, iclass 27, count 0 2006.201.05:15:13.21#ibcon#about to read 3, iclass 27, count 0 2006.201.05:15:13.23#ibcon#read 3, iclass 27, count 0 2006.201.05:15:13.23#ibcon#about to read 4, iclass 27, count 0 2006.201.05:15:13.23#ibcon#read 4, iclass 27, count 0 2006.201.05:15:13.23#ibcon#about to read 5, iclass 27, count 0 2006.201.05:15:13.23#ibcon#read 5, iclass 27, count 0 2006.201.05:15:13.23#ibcon#about to read 6, iclass 27, count 0 2006.201.05:15:13.23#ibcon#read 6, iclass 27, count 0 2006.201.05:15:13.23#ibcon#end of sib2, iclass 27, count 0 2006.201.05:15:13.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:15:13.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:15:13.23#ibcon#[25=USB\r\n] 2006.201.05:15:13.23#ibcon#*before write, iclass 27, count 0 2006.201.05:15:13.23#ibcon#enter sib2, iclass 27, count 0 2006.201.05:15:13.23#ibcon#flushed, iclass 27, count 0 2006.201.05:15:13.23#ibcon#about to write, iclass 27, count 0 2006.201.05:15:13.23#ibcon#wrote, iclass 27, count 0 2006.201.05:15:13.23#ibcon#about to read 3, iclass 27, count 0 2006.201.05:15:13.26#ibcon#read 3, iclass 27, count 0 2006.201.05:15:13.26#ibcon#about to read 4, iclass 27, count 0 2006.201.05:15:13.26#ibcon#read 4, iclass 27, count 0 2006.201.05:15:13.26#ibcon#about to read 5, iclass 27, count 0 2006.201.05:15:13.26#ibcon#read 5, iclass 27, count 0 2006.201.05:15:13.26#ibcon#about to read 6, iclass 27, count 0 2006.201.05:15:13.26#ibcon#read 6, iclass 27, count 0 2006.201.05:15:13.26#ibcon#end of sib2, iclass 27, count 0 2006.201.05:15:13.26#ibcon#*after write, iclass 27, count 0 2006.201.05:15:13.26#ibcon#*before return 0, iclass 27, count 0 2006.201.05:15:13.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:13.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:13.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:15:13.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:15:13.26$vck44/valo=4,624.99 2006.201.05:15:13.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:15:13.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:15:13.26#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:13.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:13.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:13.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:13.26#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:15:13.26#ibcon#first serial, iclass 29, count 0 2006.201.05:15:13.26#ibcon#enter sib2, iclass 29, count 0 2006.201.05:15:13.26#ibcon#flushed, iclass 29, count 0 2006.201.05:15:13.26#ibcon#about to write, iclass 29, count 0 2006.201.05:15:13.26#ibcon#wrote, iclass 29, count 0 2006.201.05:15:13.26#ibcon#about to read 3, iclass 29, count 0 2006.201.05:15:13.28#ibcon#read 3, iclass 29, count 0 2006.201.05:15:13.28#ibcon#about to read 4, iclass 29, count 0 2006.201.05:15:13.28#ibcon#read 4, iclass 29, count 0 2006.201.05:15:13.28#ibcon#about to read 5, iclass 29, count 0 2006.201.05:15:13.28#ibcon#read 5, iclass 29, count 0 2006.201.05:15:13.28#ibcon#about to read 6, iclass 29, count 0 2006.201.05:15:13.28#ibcon#read 6, iclass 29, count 0 2006.201.05:15:13.28#ibcon#end of sib2, iclass 29, count 0 2006.201.05:15:13.28#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:15:13.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:15:13.28#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:15:13.28#ibcon#*before write, iclass 29, count 0 2006.201.05:15:13.28#ibcon#enter sib2, iclass 29, count 0 2006.201.05:15:13.28#ibcon#flushed, iclass 29, count 0 2006.201.05:15:13.28#ibcon#about to write, iclass 29, count 0 2006.201.05:15:13.28#ibcon#wrote, iclass 29, count 0 2006.201.05:15:13.28#ibcon#about to read 3, iclass 29, count 0 2006.201.05:15:13.32#ibcon#read 3, iclass 29, count 0 2006.201.05:15:13.32#ibcon#about to read 4, iclass 29, count 0 2006.201.05:15:13.32#ibcon#read 4, iclass 29, count 0 2006.201.05:15:13.32#ibcon#about to read 5, iclass 29, count 0 2006.201.05:15:13.32#ibcon#read 5, iclass 29, count 0 2006.201.05:15:13.32#ibcon#about to read 6, iclass 29, count 0 2006.201.05:15:13.32#ibcon#read 6, iclass 29, count 0 2006.201.05:15:13.32#ibcon#end of sib2, iclass 29, count 0 2006.201.05:15:13.32#ibcon#*after write, iclass 29, count 0 2006.201.05:15:13.32#ibcon#*before return 0, iclass 29, count 0 2006.201.05:15:13.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:13.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:13.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:15:13.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:15:13.32$vck44/va=4,7 2006.201.05:15:13.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.05:15:13.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.05:15:13.32#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:13.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:13.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:13.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:13.38#ibcon#enter wrdev, iclass 31, count 2 2006.201.05:15:13.38#ibcon#first serial, iclass 31, count 2 2006.201.05:15:13.38#ibcon#enter sib2, iclass 31, count 2 2006.201.05:15:13.38#ibcon#flushed, iclass 31, count 2 2006.201.05:15:13.38#ibcon#about to write, iclass 31, count 2 2006.201.05:15:13.38#ibcon#wrote, iclass 31, count 2 2006.201.05:15:13.38#ibcon#about to read 3, iclass 31, count 2 2006.201.05:15:13.40#ibcon#read 3, iclass 31, count 2 2006.201.05:15:13.40#ibcon#about to read 4, iclass 31, count 2 2006.201.05:15:13.40#ibcon#read 4, iclass 31, count 2 2006.201.05:15:13.40#ibcon#about to read 5, iclass 31, count 2 2006.201.05:15:13.40#ibcon#read 5, iclass 31, count 2 2006.201.05:15:13.40#ibcon#about to read 6, iclass 31, count 2 2006.201.05:15:13.40#ibcon#read 6, iclass 31, count 2 2006.201.05:15:13.40#ibcon#end of sib2, iclass 31, count 2 2006.201.05:15:13.40#ibcon#*mode == 0, iclass 31, count 2 2006.201.05:15:13.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.05:15:13.40#ibcon#[25=AT04-07\r\n] 2006.201.05:15:13.40#ibcon#*before write, iclass 31, count 2 2006.201.05:15:13.40#ibcon#enter sib2, iclass 31, count 2 2006.201.05:15:13.40#ibcon#flushed, iclass 31, count 2 2006.201.05:15:13.40#ibcon#about to write, iclass 31, count 2 2006.201.05:15:13.40#ibcon#wrote, iclass 31, count 2 2006.201.05:15:13.40#ibcon#about to read 3, iclass 31, count 2 2006.201.05:15:13.43#ibcon#read 3, iclass 31, count 2 2006.201.05:15:15.10#ibcon#about to read 4, iclass 31, count 2 2006.201.05:15:15.10#ibcon#read 4, iclass 31, count 2 2006.201.05:15:15.10#ibcon#about to read 5, iclass 31, count 2 2006.201.05:15:15.10#ibcon#read 5, iclass 31, count 2 2006.201.05:15:15.10#ibcon#about to read 6, iclass 31, count 2 2006.201.05:15:15.10#ibcon#read 6, iclass 31, count 2 2006.201.05:15:15.10#ibcon#end of sib2, iclass 31, count 2 2006.201.05:15:15.10#ibcon#*after write, iclass 31, count 2 2006.201.05:15:15.10#ibcon#*before return 0, iclass 31, count 2 2006.201.05:15:15.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:15.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:15.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.05:15:15.10#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:15.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:15.21#abcon#<5=/05 3.1 5.3 23.34 901003.8\r\n> 2006.201.05:15:15.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:15.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:15.22#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:15:15.22#ibcon#first serial, iclass 31, count 0 2006.201.05:15:15.22#ibcon#enter sib2, iclass 31, count 0 2006.201.05:15:15.22#ibcon#flushed, iclass 31, count 0 2006.201.05:15:15.22#ibcon#about to write, iclass 31, count 0 2006.201.05:15:15.22#ibcon#wrote, iclass 31, count 0 2006.201.05:15:15.22#ibcon#about to read 3, iclass 31, count 0 2006.201.05:15:15.23#abcon#{5=INTERFACE CLEAR} 2006.201.05:15:15.24#ibcon#read 3, iclass 31, count 0 2006.201.05:15:15.24#ibcon#about to read 4, iclass 31, count 0 2006.201.05:15:15.24#ibcon#read 4, iclass 31, count 0 2006.201.05:15:15.24#ibcon#about to read 5, iclass 31, count 0 2006.201.05:15:15.24#ibcon#read 5, iclass 31, count 0 2006.201.05:15:15.24#ibcon#about to read 6, iclass 31, count 0 2006.201.05:15:15.24#ibcon#read 6, iclass 31, count 0 2006.201.05:15:15.24#ibcon#end of sib2, iclass 31, count 0 2006.201.05:15:15.24#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:15:15.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:15:15.24#ibcon#[25=USB\r\n] 2006.201.05:15:15.24#ibcon#*before write, iclass 31, count 0 2006.201.05:15:15.24#ibcon#enter sib2, iclass 31, count 0 2006.201.05:15:15.24#ibcon#flushed, iclass 31, count 0 2006.201.05:15:15.24#ibcon#about to write, iclass 31, count 0 2006.201.05:15:15.24#ibcon#wrote, iclass 31, count 0 2006.201.05:15:15.24#ibcon#about to read 3, iclass 31, count 0 2006.201.05:15:15.27#ibcon#read 3, iclass 31, count 0 2006.201.05:15:15.27#ibcon#about to read 4, iclass 31, count 0 2006.201.05:15:15.27#ibcon#read 4, iclass 31, count 0 2006.201.05:15:15.27#ibcon#about to read 5, iclass 31, count 0 2006.201.05:15:15.27#ibcon#read 5, iclass 31, count 0 2006.201.05:15:15.27#ibcon#about to read 6, iclass 31, count 0 2006.201.05:15:15.27#ibcon#read 6, iclass 31, count 0 2006.201.05:15:15.27#ibcon#end of sib2, iclass 31, count 0 2006.201.05:15:15.27#ibcon#*after write, iclass 31, count 0 2006.201.05:15:15.27#ibcon#*before return 0, iclass 31, count 0 2006.201.05:15:15.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:15.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:15.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:15:15.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:15:15.27$vck44/valo=5,734.99 2006.201.05:15:15.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.05:15:15.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.05:15:15.27#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:15.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:15.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:15.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:15.27#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:15:15.27#ibcon#first serial, iclass 37, count 0 2006.201.05:15:15.27#ibcon#enter sib2, iclass 37, count 0 2006.201.05:15:15.27#ibcon#flushed, iclass 37, count 0 2006.201.05:15:15.27#ibcon#about to write, iclass 37, count 0 2006.201.05:15:15.27#ibcon#wrote, iclass 37, count 0 2006.201.05:15:15.27#ibcon#about to read 3, iclass 37, count 0 2006.201.05:15:15.29#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:15:15.29#ibcon#read 3, iclass 37, count 0 2006.201.05:15:15.29#ibcon#about to read 4, iclass 37, count 0 2006.201.05:15:15.29#ibcon#read 4, iclass 37, count 0 2006.201.05:15:15.29#ibcon#about to read 5, iclass 37, count 0 2006.201.05:15:15.29#ibcon#read 5, iclass 37, count 0 2006.201.05:15:15.29#ibcon#about to read 6, iclass 37, count 0 2006.201.05:15:15.29#ibcon#read 6, iclass 37, count 0 2006.201.05:15:15.29#ibcon#end of sib2, iclass 37, count 0 2006.201.05:15:15.29#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:15:15.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:15:15.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:15:15.29#ibcon#*before write, iclass 37, count 0 2006.201.05:15:15.29#ibcon#enter sib2, iclass 37, count 0 2006.201.05:15:15.29#ibcon#flushed, iclass 37, count 0 2006.201.05:15:15.29#ibcon#about to write, iclass 37, count 0 2006.201.05:15:15.29#ibcon#wrote, iclass 37, count 0 2006.201.05:15:15.29#ibcon#about to read 3, iclass 37, count 0 2006.201.05:15:15.33#ibcon#read 3, iclass 37, count 0 2006.201.05:15:15.33#ibcon#about to read 4, iclass 37, count 0 2006.201.05:15:15.33#ibcon#read 4, iclass 37, count 0 2006.201.05:15:15.33#ibcon#about to read 5, iclass 37, count 0 2006.201.05:15:15.33#ibcon#read 5, iclass 37, count 0 2006.201.05:15:15.33#ibcon#about to read 6, iclass 37, count 0 2006.201.05:15:15.33#ibcon#read 6, iclass 37, count 0 2006.201.05:15:15.33#ibcon#end of sib2, iclass 37, count 0 2006.201.05:15:15.33#ibcon#*after write, iclass 37, count 0 2006.201.05:15:15.33#ibcon#*before return 0, iclass 37, count 0 2006.201.05:15:15.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:15.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:15.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:15:15.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:15:15.33$vck44/va=5,4 2006.201.05:15:15.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.05:15:15.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.05:15:15.33#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:15.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:15.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:15.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:15.39#ibcon#enter wrdev, iclass 39, count 2 2006.201.05:15:15.39#ibcon#first serial, iclass 39, count 2 2006.201.05:15:15.39#ibcon#enter sib2, iclass 39, count 2 2006.201.05:15:15.39#ibcon#flushed, iclass 39, count 2 2006.201.05:15:15.39#ibcon#about to write, iclass 39, count 2 2006.201.05:15:15.39#ibcon#wrote, iclass 39, count 2 2006.201.05:15:15.39#ibcon#about to read 3, iclass 39, count 2 2006.201.05:15:15.41#ibcon#read 3, iclass 39, count 2 2006.201.05:15:15.41#ibcon#about to read 4, iclass 39, count 2 2006.201.05:15:15.41#ibcon#read 4, iclass 39, count 2 2006.201.05:15:15.41#ibcon#about to read 5, iclass 39, count 2 2006.201.05:15:15.41#ibcon#read 5, iclass 39, count 2 2006.201.05:15:15.41#ibcon#about to read 6, iclass 39, count 2 2006.201.05:15:15.41#ibcon#read 6, iclass 39, count 2 2006.201.05:15:15.41#ibcon#end of sib2, iclass 39, count 2 2006.201.05:15:15.41#ibcon#*mode == 0, iclass 39, count 2 2006.201.05:15:15.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.05:15:15.41#ibcon#[25=AT05-04\r\n] 2006.201.05:15:15.41#ibcon#*before write, iclass 39, count 2 2006.201.05:15:15.41#ibcon#enter sib2, iclass 39, count 2 2006.201.05:15:15.41#ibcon#flushed, iclass 39, count 2 2006.201.05:15:15.41#ibcon#about to write, iclass 39, count 2 2006.201.05:15:15.41#ibcon#wrote, iclass 39, count 2 2006.201.05:15:15.41#ibcon#about to read 3, iclass 39, count 2 2006.201.05:15:15.44#ibcon#read 3, iclass 39, count 2 2006.201.05:15:15.44#ibcon#about to read 4, iclass 39, count 2 2006.201.05:15:15.44#ibcon#read 4, iclass 39, count 2 2006.201.05:15:15.44#ibcon#about to read 5, iclass 39, count 2 2006.201.05:15:15.44#ibcon#read 5, iclass 39, count 2 2006.201.05:15:15.44#ibcon#about to read 6, iclass 39, count 2 2006.201.05:15:15.44#ibcon#read 6, iclass 39, count 2 2006.201.05:15:15.44#ibcon#end of sib2, iclass 39, count 2 2006.201.05:15:15.44#ibcon#*after write, iclass 39, count 2 2006.201.05:15:15.44#ibcon#*before return 0, iclass 39, count 2 2006.201.05:15:15.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:15.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:15.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.05:15:15.44#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:15.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:15.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:15.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:15.56#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:15:15.56#ibcon#first serial, iclass 39, count 0 2006.201.05:15:15.56#ibcon#enter sib2, iclass 39, count 0 2006.201.05:15:15.56#ibcon#flushed, iclass 39, count 0 2006.201.05:15:15.56#ibcon#about to write, iclass 39, count 0 2006.201.05:15:15.56#ibcon#wrote, iclass 39, count 0 2006.201.05:15:15.56#ibcon#about to read 3, iclass 39, count 0 2006.201.05:15:15.58#ibcon#read 3, iclass 39, count 0 2006.201.05:15:15.58#ibcon#about to read 4, iclass 39, count 0 2006.201.05:15:15.58#ibcon#read 4, iclass 39, count 0 2006.201.05:15:15.58#ibcon#about to read 5, iclass 39, count 0 2006.201.05:15:15.58#ibcon#read 5, iclass 39, count 0 2006.201.05:15:15.58#ibcon#about to read 6, iclass 39, count 0 2006.201.05:15:15.58#ibcon#read 6, iclass 39, count 0 2006.201.05:15:15.58#ibcon#end of sib2, iclass 39, count 0 2006.201.05:15:15.58#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:15:15.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:15:15.58#ibcon#[25=USB\r\n] 2006.201.05:15:15.58#ibcon#*before write, iclass 39, count 0 2006.201.05:15:15.58#ibcon#enter sib2, iclass 39, count 0 2006.201.05:15:15.58#ibcon#flushed, iclass 39, count 0 2006.201.05:15:15.58#ibcon#about to write, iclass 39, count 0 2006.201.05:15:15.58#ibcon#wrote, iclass 39, count 0 2006.201.05:15:15.58#ibcon#about to read 3, iclass 39, count 0 2006.201.05:15:15.61#ibcon#read 3, iclass 39, count 0 2006.201.05:15:15.61#ibcon#about to read 4, iclass 39, count 0 2006.201.05:15:15.61#ibcon#read 4, iclass 39, count 0 2006.201.05:15:15.61#ibcon#about to read 5, iclass 39, count 0 2006.201.05:15:15.61#ibcon#read 5, iclass 39, count 0 2006.201.05:15:15.61#ibcon#about to read 6, iclass 39, count 0 2006.201.05:15:15.61#ibcon#read 6, iclass 39, count 0 2006.201.05:15:15.61#ibcon#end of sib2, iclass 39, count 0 2006.201.05:15:15.61#ibcon#*after write, iclass 39, count 0 2006.201.05:15:15.61#ibcon#*before return 0, iclass 39, count 0 2006.201.05:15:15.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:15.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:15.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:15:15.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:15:15.61$vck44/valo=6,814.99 2006.201.05:15:15.61#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.05:15:15.61#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.05:15:15.61#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:15.61#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:15.61#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:15.61#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:15.61#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:15:15.61#ibcon#first serial, iclass 2, count 0 2006.201.05:15:15.61#ibcon#enter sib2, iclass 2, count 0 2006.201.05:15:15.61#ibcon#flushed, iclass 2, count 0 2006.201.05:15:15.61#ibcon#about to write, iclass 2, count 0 2006.201.05:15:15.61#ibcon#wrote, iclass 2, count 0 2006.201.05:15:15.61#ibcon#about to read 3, iclass 2, count 0 2006.201.05:15:15.63#ibcon#read 3, iclass 2, count 0 2006.201.05:15:15.63#ibcon#about to read 4, iclass 2, count 0 2006.201.05:15:15.63#ibcon#read 4, iclass 2, count 0 2006.201.05:15:15.63#ibcon#about to read 5, iclass 2, count 0 2006.201.05:15:15.63#ibcon#read 5, iclass 2, count 0 2006.201.05:15:15.63#ibcon#about to read 6, iclass 2, count 0 2006.201.05:15:15.63#ibcon#read 6, iclass 2, count 0 2006.201.05:15:15.63#ibcon#end of sib2, iclass 2, count 0 2006.201.05:15:15.63#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:15:15.63#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:15:15.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:15:15.63#ibcon#*before write, iclass 2, count 0 2006.201.05:15:15.63#ibcon#enter sib2, iclass 2, count 0 2006.201.05:15:15.63#ibcon#flushed, iclass 2, count 0 2006.201.05:15:15.63#ibcon#about to write, iclass 2, count 0 2006.201.05:15:15.63#ibcon#wrote, iclass 2, count 0 2006.201.05:15:15.63#ibcon#about to read 3, iclass 2, count 0 2006.201.05:15:15.67#ibcon#read 3, iclass 2, count 0 2006.201.05:15:15.67#ibcon#about to read 4, iclass 2, count 0 2006.201.05:15:15.67#ibcon#read 4, iclass 2, count 0 2006.201.05:15:15.67#ibcon#about to read 5, iclass 2, count 0 2006.201.05:15:15.67#ibcon#read 5, iclass 2, count 0 2006.201.05:15:15.67#ibcon#about to read 6, iclass 2, count 0 2006.201.05:15:15.67#ibcon#read 6, iclass 2, count 0 2006.201.05:15:15.67#ibcon#end of sib2, iclass 2, count 0 2006.201.05:15:15.67#ibcon#*after write, iclass 2, count 0 2006.201.05:15:15.67#ibcon#*before return 0, iclass 2, count 0 2006.201.05:15:15.67#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:15.67#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:15.67#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:15:15.67#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:15:15.67$vck44/va=6,5 2006.201.05:15:15.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.05:15:15.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.05:15:15.67#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:15.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:15.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:15.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:15.73#ibcon#enter wrdev, iclass 5, count 2 2006.201.05:15:15.73#ibcon#first serial, iclass 5, count 2 2006.201.05:15:15.73#ibcon#enter sib2, iclass 5, count 2 2006.201.05:15:15.73#ibcon#flushed, iclass 5, count 2 2006.201.05:15:15.73#ibcon#about to write, iclass 5, count 2 2006.201.05:15:15.73#ibcon#wrote, iclass 5, count 2 2006.201.05:15:15.73#ibcon#about to read 3, iclass 5, count 2 2006.201.05:15:15.75#ibcon#read 3, iclass 5, count 2 2006.201.05:15:15.75#ibcon#about to read 4, iclass 5, count 2 2006.201.05:15:15.75#ibcon#read 4, iclass 5, count 2 2006.201.05:15:15.75#ibcon#about to read 5, iclass 5, count 2 2006.201.05:15:15.75#ibcon#read 5, iclass 5, count 2 2006.201.05:15:15.75#ibcon#about to read 6, iclass 5, count 2 2006.201.05:15:15.75#ibcon#read 6, iclass 5, count 2 2006.201.05:15:15.75#ibcon#end of sib2, iclass 5, count 2 2006.201.05:15:15.75#ibcon#*mode == 0, iclass 5, count 2 2006.201.05:15:15.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.05:15:15.75#ibcon#[25=AT06-05\r\n] 2006.201.05:15:15.75#ibcon#*before write, iclass 5, count 2 2006.201.05:15:15.75#ibcon#enter sib2, iclass 5, count 2 2006.201.05:15:15.75#ibcon#flushed, iclass 5, count 2 2006.201.05:15:15.75#ibcon#about to write, iclass 5, count 2 2006.201.05:15:15.75#ibcon#wrote, iclass 5, count 2 2006.201.05:15:15.75#ibcon#about to read 3, iclass 5, count 2 2006.201.05:15:15.78#ibcon#read 3, iclass 5, count 2 2006.201.05:15:15.78#ibcon#about to read 4, iclass 5, count 2 2006.201.05:15:15.78#ibcon#read 4, iclass 5, count 2 2006.201.05:15:15.78#ibcon#about to read 5, iclass 5, count 2 2006.201.05:15:15.78#ibcon#read 5, iclass 5, count 2 2006.201.05:15:15.78#ibcon#about to read 6, iclass 5, count 2 2006.201.05:15:15.78#ibcon#read 6, iclass 5, count 2 2006.201.05:15:15.78#ibcon#end of sib2, iclass 5, count 2 2006.201.05:15:15.78#ibcon#*after write, iclass 5, count 2 2006.201.05:15:15.78#ibcon#*before return 0, iclass 5, count 2 2006.201.05:15:15.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:15.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:15.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.05:15:15.78#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:15.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:15.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:15.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:15.90#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:15:15.90#ibcon#first serial, iclass 5, count 0 2006.201.05:15:15.90#ibcon#enter sib2, iclass 5, count 0 2006.201.05:15:15.90#ibcon#flushed, iclass 5, count 0 2006.201.05:15:15.90#ibcon#about to write, iclass 5, count 0 2006.201.05:15:15.90#ibcon#wrote, iclass 5, count 0 2006.201.05:15:15.90#ibcon#about to read 3, iclass 5, count 0 2006.201.05:15:15.92#ibcon#read 3, iclass 5, count 0 2006.201.05:15:15.92#ibcon#about to read 4, iclass 5, count 0 2006.201.05:15:15.92#ibcon#read 4, iclass 5, count 0 2006.201.05:15:15.92#ibcon#about to read 5, iclass 5, count 0 2006.201.05:15:15.92#ibcon#read 5, iclass 5, count 0 2006.201.05:15:15.92#ibcon#about to read 6, iclass 5, count 0 2006.201.05:15:15.92#ibcon#read 6, iclass 5, count 0 2006.201.05:15:15.92#ibcon#end of sib2, iclass 5, count 0 2006.201.05:15:15.92#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:15:15.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:15:15.92#ibcon#[25=USB\r\n] 2006.201.05:15:15.92#ibcon#*before write, iclass 5, count 0 2006.201.05:15:15.92#ibcon#enter sib2, iclass 5, count 0 2006.201.05:15:15.92#ibcon#flushed, iclass 5, count 0 2006.201.05:15:15.92#ibcon#about to write, iclass 5, count 0 2006.201.05:15:15.92#ibcon#wrote, iclass 5, count 0 2006.201.05:15:15.92#ibcon#about to read 3, iclass 5, count 0 2006.201.05:15:15.95#ibcon#read 3, iclass 5, count 0 2006.201.05:15:15.95#ibcon#about to read 4, iclass 5, count 0 2006.201.05:15:15.95#ibcon#read 4, iclass 5, count 0 2006.201.05:15:15.95#ibcon#about to read 5, iclass 5, count 0 2006.201.05:15:15.95#ibcon#read 5, iclass 5, count 0 2006.201.05:15:15.95#ibcon#about to read 6, iclass 5, count 0 2006.201.05:15:15.95#ibcon#read 6, iclass 5, count 0 2006.201.05:15:15.95#ibcon#end of sib2, iclass 5, count 0 2006.201.05:15:15.95#ibcon#*after write, iclass 5, count 0 2006.201.05:15:15.95#ibcon#*before return 0, iclass 5, count 0 2006.201.05:15:15.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:15.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:15.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:15:15.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:15:15.95$vck44/valo=7,864.99 2006.201.05:15:15.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.05:15:15.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.05:15:15.95#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:15.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:15.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:15.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:15.95#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:15:15.95#ibcon#first serial, iclass 7, count 0 2006.201.05:15:15.95#ibcon#enter sib2, iclass 7, count 0 2006.201.05:15:15.95#ibcon#flushed, iclass 7, count 0 2006.201.05:15:15.95#ibcon#about to write, iclass 7, count 0 2006.201.05:15:15.95#ibcon#wrote, iclass 7, count 0 2006.201.05:15:15.95#ibcon#about to read 3, iclass 7, count 0 2006.201.05:15:15.97#ibcon#read 3, iclass 7, count 0 2006.201.05:15:15.97#ibcon#about to read 4, iclass 7, count 0 2006.201.05:15:15.97#ibcon#read 4, iclass 7, count 0 2006.201.05:15:15.97#ibcon#about to read 5, iclass 7, count 0 2006.201.05:15:15.97#ibcon#read 5, iclass 7, count 0 2006.201.05:15:15.97#ibcon#about to read 6, iclass 7, count 0 2006.201.05:15:15.97#ibcon#read 6, iclass 7, count 0 2006.201.05:15:15.97#ibcon#end of sib2, iclass 7, count 0 2006.201.05:15:15.97#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:15:15.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:15:15.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:15:15.97#ibcon#*before write, iclass 7, count 0 2006.201.05:15:15.97#ibcon#enter sib2, iclass 7, count 0 2006.201.05:15:15.97#ibcon#flushed, iclass 7, count 0 2006.201.05:15:15.97#ibcon#about to write, iclass 7, count 0 2006.201.05:15:15.97#ibcon#wrote, iclass 7, count 0 2006.201.05:15:15.97#ibcon#about to read 3, iclass 7, count 0 2006.201.05:15:16.01#ibcon#read 3, iclass 7, count 0 2006.201.05:15:16.01#ibcon#about to read 4, iclass 7, count 0 2006.201.05:15:16.01#ibcon#read 4, iclass 7, count 0 2006.201.05:15:16.01#ibcon#about to read 5, iclass 7, count 0 2006.201.05:15:16.01#ibcon#read 5, iclass 7, count 0 2006.201.05:15:16.01#ibcon#about to read 6, iclass 7, count 0 2006.201.05:15:16.01#ibcon#read 6, iclass 7, count 0 2006.201.05:15:16.01#ibcon#end of sib2, iclass 7, count 0 2006.201.05:15:16.01#ibcon#*after write, iclass 7, count 0 2006.201.05:15:16.01#ibcon#*before return 0, iclass 7, count 0 2006.201.05:15:16.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:16.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:16.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:15:16.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:15:16.01$vck44/va=7,5 2006.201.05:15:16.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.05:15:16.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.05:15:16.01#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:16.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:16.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:16.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:16.07#ibcon#enter wrdev, iclass 11, count 2 2006.201.05:15:16.07#ibcon#first serial, iclass 11, count 2 2006.201.05:15:16.07#ibcon#enter sib2, iclass 11, count 2 2006.201.05:15:16.07#ibcon#flushed, iclass 11, count 2 2006.201.05:15:16.07#ibcon#about to write, iclass 11, count 2 2006.201.05:15:16.07#ibcon#wrote, iclass 11, count 2 2006.201.05:15:16.07#ibcon#about to read 3, iclass 11, count 2 2006.201.05:15:16.09#ibcon#read 3, iclass 11, count 2 2006.201.05:15:16.09#ibcon#about to read 4, iclass 11, count 2 2006.201.05:15:16.09#ibcon#read 4, iclass 11, count 2 2006.201.05:15:16.09#ibcon#about to read 5, iclass 11, count 2 2006.201.05:15:16.09#ibcon#read 5, iclass 11, count 2 2006.201.05:15:16.09#ibcon#about to read 6, iclass 11, count 2 2006.201.05:15:16.09#ibcon#read 6, iclass 11, count 2 2006.201.05:15:16.09#ibcon#end of sib2, iclass 11, count 2 2006.201.05:15:16.09#ibcon#*mode == 0, iclass 11, count 2 2006.201.05:15:16.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.05:15:16.09#ibcon#[25=AT07-05\r\n] 2006.201.05:15:16.09#ibcon#*before write, iclass 11, count 2 2006.201.05:15:16.09#ibcon#enter sib2, iclass 11, count 2 2006.201.05:15:16.09#ibcon#flushed, iclass 11, count 2 2006.201.05:15:16.09#ibcon#about to write, iclass 11, count 2 2006.201.05:15:16.09#ibcon#wrote, iclass 11, count 2 2006.201.05:15:16.09#ibcon#about to read 3, iclass 11, count 2 2006.201.05:15:16.12#ibcon#read 3, iclass 11, count 2 2006.201.05:15:16.12#ibcon#about to read 4, iclass 11, count 2 2006.201.05:15:16.17#ibcon#read 4, iclass 11, count 2 2006.201.05:15:16.17#ibcon#about to read 5, iclass 11, count 2 2006.201.05:15:16.17#ibcon#read 5, iclass 11, count 2 2006.201.05:15:16.17#ibcon#about to read 6, iclass 11, count 2 2006.201.05:15:16.17#ibcon#read 6, iclass 11, count 2 2006.201.05:15:16.17#ibcon#end of sib2, iclass 11, count 2 2006.201.05:15:16.17#ibcon#*after write, iclass 11, count 2 2006.201.05:15:16.17#ibcon#*before return 0, iclass 11, count 2 2006.201.05:15:16.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:16.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:16.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.05:15:16.18#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:16.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:16.29#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:16.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:16.29#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:15:16.29#ibcon#first serial, iclass 11, count 0 2006.201.05:15:16.29#ibcon#enter sib2, iclass 11, count 0 2006.201.05:15:16.29#ibcon#flushed, iclass 11, count 0 2006.201.05:15:16.29#ibcon#about to write, iclass 11, count 0 2006.201.05:15:16.29#ibcon#wrote, iclass 11, count 0 2006.201.05:15:16.29#ibcon#about to read 3, iclass 11, count 0 2006.201.05:15:16.31#ibcon#read 3, iclass 11, count 0 2006.201.05:15:16.31#ibcon#about to read 4, iclass 11, count 0 2006.201.05:15:16.31#ibcon#read 4, iclass 11, count 0 2006.201.05:15:16.31#ibcon#about to read 5, iclass 11, count 0 2006.201.05:15:16.31#ibcon#read 5, iclass 11, count 0 2006.201.05:15:16.31#ibcon#about to read 6, iclass 11, count 0 2006.201.05:15:16.31#ibcon#read 6, iclass 11, count 0 2006.201.05:15:16.31#ibcon#end of sib2, iclass 11, count 0 2006.201.05:15:16.31#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:15:16.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:15:16.31#ibcon#[25=USB\r\n] 2006.201.05:15:16.31#ibcon#*before write, iclass 11, count 0 2006.201.05:15:16.31#ibcon#enter sib2, iclass 11, count 0 2006.201.05:15:16.31#ibcon#flushed, iclass 11, count 0 2006.201.05:15:16.31#ibcon#about to write, iclass 11, count 0 2006.201.05:15:16.31#ibcon#wrote, iclass 11, count 0 2006.201.05:15:16.31#ibcon#about to read 3, iclass 11, count 0 2006.201.05:15:16.34#ibcon#read 3, iclass 11, count 0 2006.201.05:15:16.34#ibcon#about to read 4, iclass 11, count 0 2006.201.05:15:16.34#ibcon#read 4, iclass 11, count 0 2006.201.05:15:16.34#ibcon#about to read 5, iclass 11, count 0 2006.201.05:15:16.34#ibcon#read 5, iclass 11, count 0 2006.201.05:15:16.34#ibcon#about to read 6, iclass 11, count 0 2006.201.05:15:16.34#ibcon#read 6, iclass 11, count 0 2006.201.05:15:16.34#ibcon#end of sib2, iclass 11, count 0 2006.201.05:15:16.34#ibcon#*after write, iclass 11, count 0 2006.201.05:15:16.34#ibcon#*before return 0, iclass 11, count 0 2006.201.05:15:16.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:16.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:16.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:15:16.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:15:16.34$vck44/valo=8,884.99 2006.201.05:15:16.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.05:15:16.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.05:15:16.34#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:16.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:16.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:16.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:16.34#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:15:16.34#ibcon#first serial, iclass 13, count 0 2006.201.05:15:16.34#ibcon#enter sib2, iclass 13, count 0 2006.201.05:15:16.34#ibcon#flushed, iclass 13, count 0 2006.201.05:15:16.34#ibcon#about to write, iclass 13, count 0 2006.201.05:15:16.34#ibcon#wrote, iclass 13, count 0 2006.201.05:15:16.34#ibcon#about to read 3, iclass 13, count 0 2006.201.05:15:16.36#ibcon#read 3, iclass 13, count 0 2006.201.05:15:16.36#ibcon#about to read 4, iclass 13, count 0 2006.201.05:15:16.36#ibcon#read 4, iclass 13, count 0 2006.201.05:15:16.36#ibcon#about to read 5, iclass 13, count 0 2006.201.05:15:16.36#ibcon#read 5, iclass 13, count 0 2006.201.05:15:16.36#ibcon#about to read 6, iclass 13, count 0 2006.201.05:15:16.36#ibcon#read 6, iclass 13, count 0 2006.201.05:15:16.36#ibcon#end of sib2, iclass 13, count 0 2006.201.05:15:16.36#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:15:16.36#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:15:16.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:15:16.36#ibcon#*before write, iclass 13, count 0 2006.201.05:15:16.36#ibcon#enter sib2, iclass 13, count 0 2006.201.05:15:16.36#ibcon#flushed, iclass 13, count 0 2006.201.05:15:16.36#ibcon#about to write, iclass 13, count 0 2006.201.05:15:16.36#ibcon#wrote, iclass 13, count 0 2006.201.05:15:16.36#ibcon#about to read 3, iclass 13, count 0 2006.201.05:15:16.40#ibcon#read 3, iclass 13, count 0 2006.201.05:15:16.40#ibcon#about to read 4, iclass 13, count 0 2006.201.05:15:16.40#ibcon#read 4, iclass 13, count 0 2006.201.05:15:16.40#ibcon#about to read 5, iclass 13, count 0 2006.201.05:15:16.40#ibcon#read 5, iclass 13, count 0 2006.201.05:15:16.40#ibcon#about to read 6, iclass 13, count 0 2006.201.05:15:16.40#ibcon#read 6, iclass 13, count 0 2006.201.05:15:16.40#ibcon#end of sib2, iclass 13, count 0 2006.201.05:15:16.40#ibcon#*after write, iclass 13, count 0 2006.201.05:15:16.40#ibcon#*before return 0, iclass 13, count 0 2006.201.05:15:16.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:16.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:16.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:15:16.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:15:16.40$vck44/va=8,4 2006.201.05:15:16.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.05:15:16.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.05:15:16.40#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:16.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:15:16.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:15:16.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:15:16.46#ibcon#enter wrdev, iclass 15, count 2 2006.201.05:15:16.46#ibcon#first serial, iclass 15, count 2 2006.201.05:15:16.46#ibcon#enter sib2, iclass 15, count 2 2006.201.05:15:16.46#ibcon#flushed, iclass 15, count 2 2006.201.05:15:16.46#ibcon#about to write, iclass 15, count 2 2006.201.05:15:16.46#ibcon#wrote, iclass 15, count 2 2006.201.05:15:16.46#ibcon#about to read 3, iclass 15, count 2 2006.201.05:15:16.48#ibcon#read 3, iclass 15, count 2 2006.201.05:15:16.48#ibcon#about to read 4, iclass 15, count 2 2006.201.05:15:16.48#ibcon#read 4, iclass 15, count 2 2006.201.05:15:16.48#ibcon#about to read 5, iclass 15, count 2 2006.201.05:15:16.48#ibcon#read 5, iclass 15, count 2 2006.201.05:15:16.48#ibcon#about to read 6, iclass 15, count 2 2006.201.05:15:16.48#ibcon#read 6, iclass 15, count 2 2006.201.05:15:16.48#ibcon#end of sib2, iclass 15, count 2 2006.201.05:15:16.48#ibcon#*mode == 0, iclass 15, count 2 2006.201.05:15:16.48#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.05:15:16.48#ibcon#[25=AT08-04\r\n] 2006.201.05:15:16.48#ibcon#*before write, iclass 15, count 2 2006.201.05:15:16.48#ibcon#enter sib2, iclass 15, count 2 2006.201.05:15:16.48#ibcon#flushed, iclass 15, count 2 2006.201.05:15:16.48#ibcon#about to write, iclass 15, count 2 2006.201.05:15:16.48#ibcon#wrote, iclass 15, count 2 2006.201.05:15:16.48#ibcon#about to read 3, iclass 15, count 2 2006.201.05:15:16.51#ibcon#read 3, iclass 15, count 2 2006.201.05:15:16.51#ibcon#about to read 4, iclass 15, count 2 2006.201.05:15:16.51#ibcon#read 4, iclass 15, count 2 2006.201.05:15:16.51#ibcon#about to read 5, iclass 15, count 2 2006.201.05:15:16.51#ibcon#read 5, iclass 15, count 2 2006.201.05:15:16.51#ibcon#about to read 6, iclass 15, count 2 2006.201.05:15:16.51#ibcon#read 6, iclass 15, count 2 2006.201.05:15:16.51#ibcon#end of sib2, iclass 15, count 2 2006.201.05:15:16.51#ibcon#*after write, iclass 15, count 2 2006.201.05:15:16.51#ibcon#*before return 0, iclass 15, count 2 2006.201.05:15:16.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:15:16.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:15:16.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.05:15:16.51#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:16.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:15:16.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:15:16.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:15:16.63#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:15:16.63#ibcon#first serial, iclass 15, count 0 2006.201.05:15:16.63#ibcon#enter sib2, iclass 15, count 0 2006.201.05:15:16.63#ibcon#flushed, iclass 15, count 0 2006.201.05:15:16.63#ibcon#about to write, iclass 15, count 0 2006.201.05:15:16.63#ibcon#wrote, iclass 15, count 0 2006.201.05:15:16.63#ibcon#about to read 3, iclass 15, count 0 2006.201.05:15:16.65#ibcon#read 3, iclass 15, count 0 2006.201.05:15:16.65#ibcon#about to read 4, iclass 15, count 0 2006.201.05:15:16.65#ibcon#read 4, iclass 15, count 0 2006.201.05:15:16.65#ibcon#about to read 5, iclass 15, count 0 2006.201.05:15:16.65#ibcon#read 5, iclass 15, count 0 2006.201.05:15:16.65#ibcon#about to read 6, iclass 15, count 0 2006.201.05:15:16.65#ibcon#read 6, iclass 15, count 0 2006.201.05:15:16.65#ibcon#end of sib2, iclass 15, count 0 2006.201.05:15:16.65#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:15:16.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:15:16.65#ibcon#[25=USB\r\n] 2006.201.05:15:16.65#ibcon#*before write, iclass 15, count 0 2006.201.05:15:16.65#ibcon#enter sib2, iclass 15, count 0 2006.201.05:15:16.65#ibcon#flushed, iclass 15, count 0 2006.201.05:15:16.65#ibcon#about to write, iclass 15, count 0 2006.201.05:15:16.65#ibcon#wrote, iclass 15, count 0 2006.201.05:15:16.65#ibcon#about to read 3, iclass 15, count 0 2006.201.05:15:16.68#ibcon#read 3, iclass 15, count 0 2006.201.05:15:16.68#ibcon#about to read 4, iclass 15, count 0 2006.201.05:15:16.68#ibcon#read 4, iclass 15, count 0 2006.201.05:15:16.68#ibcon#about to read 5, iclass 15, count 0 2006.201.05:15:16.68#ibcon#read 5, iclass 15, count 0 2006.201.05:15:16.68#ibcon#about to read 6, iclass 15, count 0 2006.201.05:15:16.68#ibcon#read 6, iclass 15, count 0 2006.201.05:15:16.68#ibcon#end of sib2, iclass 15, count 0 2006.201.05:15:16.68#ibcon#*after write, iclass 15, count 0 2006.201.05:15:16.68#ibcon#*before return 0, iclass 15, count 0 2006.201.05:15:16.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:15:16.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:15:16.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:15:16.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:15:16.68$vck44/vblo=1,629.99 2006.201.05:15:16.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.05:15:16.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.05:15:16.68#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:16.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:16.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:16.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:16.68#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:15:16.68#ibcon#first serial, iclass 17, count 0 2006.201.05:15:16.68#ibcon#enter sib2, iclass 17, count 0 2006.201.05:15:16.68#ibcon#flushed, iclass 17, count 0 2006.201.05:15:16.68#ibcon#about to write, iclass 17, count 0 2006.201.05:15:16.68#ibcon#wrote, iclass 17, count 0 2006.201.05:15:16.68#ibcon#about to read 3, iclass 17, count 0 2006.201.05:15:16.70#ibcon#read 3, iclass 17, count 0 2006.201.05:15:16.70#ibcon#about to read 4, iclass 17, count 0 2006.201.05:15:16.70#ibcon#read 4, iclass 17, count 0 2006.201.05:15:16.70#ibcon#about to read 5, iclass 17, count 0 2006.201.05:15:16.70#ibcon#read 5, iclass 17, count 0 2006.201.05:15:16.70#ibcon#about to read 6, iclass 17, count 0 2006.201.05:15:16.70#ibcon#read 6, iclass 17, count 0 2006.201.05:15:16.70#ibcon#end of sib2, iclass 17, count 0 2006.201.05:15:16.70#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:15:16.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:15:16.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:15:16.70#ibcon#*before write, iclass 17, count 0 2006.201.05:15:16.70#ibcon#enter sib2, iclass 17, count 0 2006.201.05:15:16.70#ibcon#flushed, iclass 17, count 0 2006.201.05:15:16.70#ibcon#about to write, iclass 17, count 0 2006.201.05:15:16.70#ibcon#wrote, iclass 17, count 0 2006.201.05:15:16.70#ibcon#about to read 3, iclass 17, count 0 2006.201.05:15:16.74#ibcon#read 3, iclass 17, count 0 2006.201.05:15:16.74#ibcon#about to read 4, iclass 17, count 0 2006.201.05:15:16.74#ibcon#read 4, iclass 17, count 0 2006.201.05:15:16.74#ibcon#about to read 5, iclass 17, count 0 2006.201.05:15:16.74#ibcon#read 5, iclass 17, count 0 2006.201.05:15:16.74#ibcon#about to read 6, iclass 17, count 0 2006.201.05:15:16.74#ibcon#read 6, iclass 17, count 0 2006.201.05:15:16.74#ibcon#end of sib2, iclass 17, count 0 2006.201.05:15:16.74#ibcon#*after write, iclass 17, count 0 2006.201.05:15:16.74#ibcon#*before return 0, iclass 17, count 0 2006.201.05:15:16.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:16.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:15:16.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:15:16.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:15:16.74$vck44/vb=1,4 2006.201.05:15:16.74#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.05:15:16.74#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.05:15:16.74#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:16.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:16.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:16.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:16.74#ibcon#enter wrdev, iclass 19, count 2 2006.201.05:15:16.74#ibcon#first serial, iclass 19, count 2 2006.201.05:15:16.74#ibcon#enter sib2, iclass 19, count 2 2006.201.05:15:16.74#ibcon#flushed, iclass 19, count 2 2006.201.05:15:16.74#ibcon#about to write, iclass 19, count 2 2006.201.05:15:16.74#ibcon#wrote, iclass 19, count 2 2006.201.05:15:16.74#ibcon#about to read 3, iclass 19, count 2 2006.201.05:15:16.76#ibcon#read 3, iclass 19, count 2 2006.201.05:15:16.76#ibcon#about to read 4, iclass 19, count 2 2006.201.05:15:16.76#ibcon#read 4, iclass 19, count 2 2006.201.05:15:16.76#ibcon#about to read 5, iclass 19, count 2 2006.201.05:15:16.76#ibcon#read 5, iclass 19, count 2 2006.201.05:15:16.76#ibcon#about to read 6, iclass 19, count 2 2006.201.05:15:16.76#ibcon#read 6, iclass 19, count 2 2006.201.05:15:16.76#ibcon#end of sib2, iclass 19, count 2 2006.201.05:15:16.76#ibcon#*mode == 0, iclass 19, count 2 2006.201.05:15:16.76#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.05:15:16.76#ibcon#[27=AT01-04\r\n] 2006.201.05:15:16.76#ibcon#*before write, iclass 19, count 2 2006.201.05:15:16.76#ibcon#enter sib2, iclass 19, count 2 2006.201.05:15:16.76#ibcon#flushed, iclass 19, count 2 2006.201.05:15:16.76#ibcon#about to write, iclass 19, count 2 2006.201.05:15:16.76#ibcon#wrote, iclass 19, count 2 2006.201.05:15:16.76#ibcon#about to read 3, iclass 19, count 2 2006.201.05:15:16.79#ibcon#read 3, iclass 19, count 2 2006.201.05:15:16.79#ibcon#about to read 4, iclass 19, count 2 2006.201.05:15:16.79#ibcon#read 4, iclass 19, count 2 2006.201.05:15:16.79#ibcon#about to read 5, iclass 19, count 2 2006.201.05:15:16.79#ibcon#read 5, iclass 19, count 2 2006.201.05:15:16.79#ibcon#about to read 6, iclass 19, count 2 2006.201.05:15:16.79#ibcon#read 6, iclass 19, count 2 2006.201.05:15:16.79#ibcon#end of sib2, iclass 19, count 2 2006.201.05:15:16.79#ibcon#*after write, iclass 19, count 2 2006.201.05:15:16.79#ibcon#*before return 0, iclass 19, count 2 2006.201.05:15:16.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:16.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:15:16.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.05:15:16.79#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:16.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:16.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:16.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:16.91#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:15:16.91#ibcon#first serial, iclass 19, count 0 2006.201.05:15:16.91#ibcon#enter sib2, iclass 19, count 0 2006.201.05:15:16.91#ibcon#flushed, iclass 19, count 0 2006.201.05:15:16.91#ibcon#about to write, iclass 19, count 0 2006.201.05:15:16.91#ibcon#wrote, iclass 19, count 0 2006.201.05:15:16.91#ibcon#about to read 3, iclass 19, count 0 2006.201.05:15:16.93#ibcon#read 3, iclass 19, count 0 2006.201.05:15:16.93#ibcon#about to read 4, iclass 19, count 0 2006.201.05:15:16.93#ibcon#read 4, iclass 19, count 0 2006.201.05:15:16.93#ibcon#about to read 5, iclass 19, count 0 2006.201.05:15:16.93#ibcon#read 5, iclass 19, count 0 2006.201.05:15:16.93#ibcon#about to read 6, iclass 19, count 0 2006.201.05:15:16.93#ibcon#read 6, iclass 19, count 0 2006.201.05:15:16.93#ibcon#end of sib2, iclass 19, count 0 2006.201.05:15:16.93#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:15:16.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:15:16.93#ibcon#[27=USB\r\n] 2006.201.05:15:16.93#ibcon#*before write, iclass 19, count 0 2006.201.05:15:16.93#ibcon#enter sib2, iclass 19, count 0 2006.201.05:15:16.93#ibcon#flushed, iclass 19, count 0 2006.201.05:15:16.93#ibcon#about to write, iclass 19, count 0 2006.201.05:15:16.93#ibcon#wrote, iclass 19, count 0 2006.201.05:15:16.93#ibcon#about to read 3, iclass 19, count 0 2006.201.05:15:16.96#ibcon#read 3, iclass 19, count 0 2006.201.05:15:16.96#ibcon#about to read 4, iclass 19, count 0 2006.201.05:15:16.96#ibcon#read 4, iclass 19, count 0 2006.201.05:15:16.96#ibcon#about to read 5, iclass 19, count 0 2006.201.05:15:16.96#ibcon#read 5, iclass 19, count 0 2006.201.05:15:16.96#ibcon#about to read 6, iclass 19, count 0 2006.201.05:15:16.96#ibcon#read 6, iclass 19, count 0 2006.201.05:15:16.96#ibcon#end of sib2, iclass 19, count 0 2006.201.05:15:16.96#ibcon#*after write, iclass 19, count 0 2006.201.05:15:16.96#ibcon#*before return 0, iclass 19, count 0 2006.201.05:15:16.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:16.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:15:16.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:15:16.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:15:16.96$vck44/vblo=2,634.99 2006.201.05:15:16.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.05:15:16.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.05:15:16.96#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:16.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:16.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:16.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:16.96#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:15:16.96#ibcon#first serial, iclass 21, count 0 2006.201.05:15:16.96#ibcon#enter sib2, iclass 21, count 0 2006.201.05:15:16.96#ibcon#flushed, iclass 21, count 0 2006.201.05:15:16.96#ibcon#about to write, iclass 21, count 0 2006.201.05:15:16.96#ibcon#wrote, iclass 21, count 0 2006.201.05:15:16.96#ibcon#about to read 3, iclass 21, count 0 2006.201.05:15:16.98#ibcon#read 3, iclass 21, count 0 2006.201.05:15:16.98#ibcon#about to read 4, iclass 21, count 0 2006.201.05:15:16.98#ibcon#read 4, iclass 21, count 0 2006.201.05:15:16.98#ibcon#about to read 5, iclass 21, count 0 2006.201.05:15:16.98#ibcon#read 5, iclass 21, count 0 2006.201.05:15:16.98#ibcon#about to read 6, iclass 21, count 0 2006.201.05:15:16.98#ibcon#read 6, iclass 21, count 0 2006.201.05:15:16.98#ibcon#end of sib2, iclass 21, count 0 2006.201.05:15:16.98#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:15:16.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:15:16.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:15:16.98#ibcon#*before write, iclass 21, count 0 2006.201.05:15:16.98#ibcon#enter sib2, iclass 21, count 0 2006.201.05:15:16.98#ibcon#flushed, iclass 21, count 0 2006.201.05:15:16.98#ibcon#about to write, iclass 21, count 0 2006.201.05:15:16.98#ibcon#wrote, iclass 21, count 0 2006.201.05:15:16.98#ibcon#about to read 3, iclass 21, count 0 2006.201.05:15:17.02#ibcon#read 3, iclass 21, count 0 2006.201.05:15:17.02#ibcon#about to read 4, iclass 21, count 0 2006.201.05:15:17.02#ibcon#read 4, iclass 21, count 0 2006.201.05:15:17.02#ibcon#about to read 5, iclass 21, count 0 2006.201.05:15:17.02#ibcon#read 5, iclass 21, count 0 2006.201.05:15:17.02#ibcon#about to read 6, iclass 21, count 0 2006.201.05:15:17.02#ibcon#read 6, iclass 21, count 0 2006.201.05:15:17.02#ibcon#end of sib2, iclass 21, count 0 2006.201.05:15:17.02#ibcon#*after write, iclass 21, count 0 2006.201.05:15:17.02#ibcon#*before return 0, iclass 21, count 0 2006.201.05:15:17.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:17.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:15:17.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:15:17.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:15:17.02$vck44/vb=2,5 2006.201.05:15:17.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.05:15:17.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.05:15:17.02#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:17.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:17.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:17.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:17.08#ibcon#enter wrdev, iclass 23, count 2 2006.201.05:15:17.08#ibcon#first serial, iclass 23, count 2 2006.201.05:15:17.08#ibcon#enter sib2, iclass 23, count 2 2006.201.05:15:17.08#ibcon#flushed, iclass 23, count 2 2006.201.05:15:17.08#ibcon#about to write, iclass 23, count 2 2006.201.05:15:17.08#ibcon#wrote, iclass 23, count 2 2006.201.05:15:17.08#ibcon#about to read 3, iclass 23, count 2 2006.201.05:15:17.10#ibcon#read 3, iclass 23, count 2 2006.201.05:15:17.10#ibcon#about to read 4, iclass 23, count 2 2006.201.05:15:17.10#ibcon#read 4, iclass 23, count 2 2006.201.05:15:17.10#ibcon#about to read 5, iclass 23, count 2 2006.201.05:15:17.10#ibcon#read 5, iclass 23, count 2 2006.201.05:15:17.10#ibcon#about to read 6, iclass 23, count 2 2006.201.05:15:17.10#ibcon#read 6, iclass 23, count 2 2006.201.05:15:17.10#ibcon#end of sib2, iclass 23, count 2 2006.201.05:15:17.10#ibcon#*mode == 0, iclass 23, count 2 2006.201.05:15:17.10#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.05:15:17.10#ibcon#[27=AT02-05\r\n] 2006.201.05:15:17.10#ibcon#*before write, iclass 23, count 2 2006.201.05:15:17.10#ibcon#enter sib2, iclass 23, count 2 2006.201.05:15:17.10#ibcon#flushed, iclass 23, count 2 2006.201.05:15:17.10#ibcon#about to write, iclass 23, count 2 2006.201.05:15:17.10#ibcon#wrote, iclass 23, count 2 2006.201.05:15:17.10#ibcon#about to read 3, iclass 23, count 2 2006.201.05:15:17.13#ibcon#read 3, iclass 23, count 2 2006.201.05:15:17.22#ibcon#about to read 4, iclass 23, count 2 2006.201.05:15:17.22#ibcon#read 4, iclass 23, count 2 2006.201.05:15:17.22#ibcon#about to read 5, iclass 23, count 2 2006.201.05:15:17.22#ibcon#read 5, iclass 23, count 2 2006.201.05:15:17.22#ibcon#about to read 6, iclass 23, count 2 2006.201.05:15:17.22#ibcon#read 6, iclass 23, count 2 2006.201.05:15:17.22#ibcon#end of sib2, iclass 23, count 2 2006.201.05:15:17.22#ibcon#*after write, iclass 23, count 2 2006.201.05:15:17.22#ibcon#*before return 0, iclass 23, count 2 2006.201.05:15:17.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:17.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:15:17.22#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.05:15:17.23#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:17.23#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:17.34#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:17.34#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:17.34#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:15:17.34#ibcon#first serial, iclass 23, count 0 2006.201.05:15:17.34#ibcon#enter sib2, iclass 23, count 0 2006.201.05:15:17.34#ibcon#flushed, iclass 23, count 0 2006.201.05:15:17.34#ibcon#about to write, iclass 23, count 0 2006.201.05:15:17.34#ibcon#wrote, iclass 23, count 0 2006.201.05:15:17.34#ibcon#about to read 3, iclass 23, count 0 2006.201.05:15:17.36#ibcon#read 3, iclass 23, count 0 2006.201.05:15:17.36#ibcon#about to read 4, iclass 23, count 0 2006.201.05:15:17.36#ibcon#read 4, iclass 23, count 0 2006.201.05:15:17.36#ibcon#about to read 5, iclass 23, count 0 2006.201.05:15:17.36#ibcon#read 5, iclass 23, count 0 2006.201.05:15:17.36#ibcon#about to read 6, iclass 23, count 0 2006.201.05:15:17.36#ibcon#read 6, iclass 23, count 0 2006.201.05:15:17.36#ibcon#end of sib2, iclass 23, count 0 2006.201.05:15:17.36#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:15:17.36#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:15:17.36#ibcon#[27=USB\r\n] 2006.201.05:15:17.36#ibcon#*before write, iclass 23, count 0 2006.201.05:15:17.36#ibcon#enter sib2, iclass 23, count 0 2006.201.05:15:17.36#ibcon#flushed, iclass 23, count 0 2006.201.05:15:17.36#ibcon#about to write, iclass 23, count 0 2006.201.05:15:17.36#ibcon#wrote, iclass 23, count 0 2006.201.05:15:17.36#ibcon#about to read 3, iclass 23, count 0 2006.201.05:15:17.39#ibcon#read 3, iclass 23, count 0 2006.201.05:15:17.39#ibcon#about to read 4, iclass 23, count 0 2006.201.05:15:17.39#ibcon#read 4, iclass 23, count 0 2006.201.05:15:17.39#ibcon#about to read 5, iclass 23, count 0 2006.201.05:15:17.39#ibcon#read 5, iclass 23, count 0 2006.201.05:15:17.39#ibcon#about to read 6, iclass 23, count 0 2006.201.05:15:17.39#ibcon#read 6, iclass 23, count 0 2006.201.05:15:17.39#ibcon#end of sib2, iclass 23, count 0 2006.201.05:15:17.39#ibcon#*after write, iclass 23, count 0 2006.201.05:15:17.39#ibcon#*before return 0, iclass 23, count 0 2006.201.05:15:17.39#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:17.39#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:15:17.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:15:17.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:15:17.39$vck44/vblo=3,649.99 2006.201.05:15:17.39#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.05:15:17.39#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.05:15:17.39#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:17.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:17.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:17.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:17.39#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:15:17.39#ibcon#first serial, iclass 25, count 0 2006.201.05:15:17.39#ibcon#enter sib2, iclass 25, count 0 2006.201.05:15:17.39#ibcon#flushed, iclass 25, count 0 2006.201.05:15:17.39#ibcon#about to write, iclass 25, count 0 2006.201.05:15:17.39#ibcon#wrote, iclass 25, count 0 2006.201.05:15:17.39#ibcon#about to read 3, iclass 25, count 0 2006.201.05:15:17.41#ibcon#read 3, iclass 25, count 0 2006.201.05:15:17.41#ibcon#about to read 4, iclass 25, count 0 2006.201.05:15:17.41#ibcon#read 4, iclass 25, count 0 2006.201.05:15:17.41#ibcon#about to read 5, iclass 25, count 0 2006.201.05:15:17.41#ibcon#read 5, iclass 25, count 0 2006.201.05:15:17.41#ibcon#about to read 6, iclass 25, count 0 2006.201.05:15:17.41#ibcon#read 6, iclass 25, count 0 2006.201.05:15:17.41#ibcon#end of sib2, iclass 25, count 0 2006.201.05:15:17.41#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:15:17.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:15:17.41#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:15:17.41#ibcon#*before write, iclass 25, count 0 2006.201.05:15:17.41#ibcon#enter sib2, iclass 25, count 0 2006.201.05:15:17.41#ibcon#flushed, iclass 25, count 0 2006.201.05:15:17.41#ibcon#about to write, iclass 25, count 0 2006.201.05:15:17.41#ibcon#wrote, iclass 25, count 0 2006.201.05:15:17.41#ibcon#about to read 3, iclass 25, count 0 2006.201.05:15:17.45#ibcon#read 3, iclass 25, count 0 2006.201.05:15:17.45#ibcon#about to read 4, iclass 25, count 0 2006.201.05:15:17.45#ibcon#read 4, iclass 25, count 0 2006.201.05:15:17.45#ibcon#about to read 5, iclass 25, count 0 2006.201.05:15:17.45#ibcon#read 5, iclass 25, count 0 2006.201.05:15:17.45#ibcon#about to read 6, iclass 25, count 0 2006.201.05:15:17.45#ibcon#read 6, iclass 25, count 0 2006.201.05:15:17.45#ibcon#end of sib2, iclass 25, count 0 2006.201.05:15:17.45#ibcon#*after write, iclass 25, count 0 2006.201.05:15:17.45#ibcon#*before return 0, iclass 25, count 0 2006.201.05:15:17.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:17.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:15:17.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:15:17.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:15:17.45$vck44/vb=3,4 2006.201.05:15:17.45#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.05:15:17.45#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.05:15:17.45#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:17.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:17.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:17.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:17.51#ibcon#enter wrdev, iclass 27, count 2 2006.201.05:15:17.51#ibcon#first serial, iclass 27, count 2 2006.201.05:15:17.51#ibcon#enter sib2, iclass 27, count 2 2006.201.05:15:17.51#ibcon#flushed, iclass 27, count 2 2006.201.05:15:17.51#ibcon#about to write, iclass 27, count 2 2006.201.05:15:17.51#ibcon#wrote, iclass 27, count 2 2006.201.05:15:17.51#ibcon#about to read 3, iclass 27, count 2 2006.201.05:15:17.53#ibcon#read 3, iclass 27, count 2 2006.201.05:15:17.53#ibcon#about to read 4, iclass 27, count 2 2006.201.05:15:17.53#ibcon#read 4, iclass 27, count 2 2006.201.05:15:17.53#ibcon#about to read 5, iclass 27, count 2 2006.201.05:15:17.53#ibcon#read 5, iclass 27, count 2 2006.201.05:15:17.53#ibcon#about to read 6, iclass 27, count 2 2006.201.05:15:17.53#ibcon#read 6, iclass 27, count 2 2006.201.05:15:17.53#ibcon#end of sib2, iclass 27, count 2 2006.201.05:15:17.53#ibcon#*mode == 0, iclass 27, count 2 2006.201.05:15:17.53#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.05:15:17.53#ibcon#[27=AT03-04\r\n] 2006.201.05:15:17.53#ibcon#*before write, iclass 27, count 2 2006.201.05:15:17.53#ibcon#enter sib2, iclass 27, count 2 2006.201.05:15:17.53#ibcon#flushed, iclass 27, count 2 2006.201.05:15:17.53#ibcon#about to write, iclass 27, count 2 2006.201.05:15:17.53#ibcon#wrote, iclass 27, count 2 2006.201.05:15:17.53#ibcon#about to read 3, iclass 27, count 2 2006.201.05:15:17.56#ibcon#read 3, iclass 27, count 2 2006.201.05:15:17.56#ibcon#about to read 4, iclass 27, count 2 2006.201.05:15:17.56#ibcon#read 4, iclass 27, count 2 2006.201.05:15:17.56#ibcon#about to read 5, iclass 27, count 2 2006.201.05:15:17.56#ibcon#read 5, iclass 27, count 2 2006.201.05:15:17.56#ibcon#about to read 6, iclass 27, count 2 2006.201.05:15:17.56#ibcon#read 6, iclass 27, count 2 2006.201.05:15:17.56#ibcon#end of sib2, iclass 27, count 2 2006.201.05:15:17.56#ibcon#*after write, iclass 27, count 2 2006.201.05:15:17.56#ibcon#*before return 0, iclass 27, count 2 2006.201.05:15:17.56#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:17.56#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:15:17.56#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.05:15:17.56#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:17.56#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:17.68#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:17.68#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:17.68#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:15:17.68#ibcon#first serial, iclass 27, count 0 2006.201.05:15:17.68#ibcon#enter sib2, iclass 27, count 0 2006.201.05:15:17.68#ibcon#flushed, iclass 27, count 0 2006.201.05:15:17.68#ibcon#about to write, iclass 27, count 0 2006.201.05:15:17.68#ibcon#wrote, iclass 27, count 0 2006.201.05:15:17.68#ibcon#about to read 3, iclass 27, count 0 2006.201.05:15:17.70#ibcon#read 3, iclass 27, count 0 2006.201.05:15:17.70#ibcon#about to read 4, iclass 27, count 0 2006.201.05:15:17.70#ibcon#read 4, iclass 27, count 0 2006.201.05:15:17.70#ibcon#about to read 5, iclass 27, count 0 2006.201.05:15:17.70#ibcon#read 5, iclass 27, count 0 2006.201.05:15:17.70#ibcon#about to read 6, iclass 27, count 0 2006.201.05:15:17.70#ibcon#read 6, iclass 27, count 0 2006.201.05:15:17.70#ibcon#end of sib2, iclass 27, count 0 2006.201.05:15:17.70#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:15:17.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:15:17.70#ibcon#[27=USB\r\n] 2006.201.05:15:17.70#ibcon#*before write, iclass 27, count 0 2006.201.05:15:17.70#ibcon#enter sib2, iclass 27, count 0 2006.201.05:15:17.70#ibcon#flushed, iclass 27, count 0 2006.201.05:15:17.70#ibcon#about to write, iclass 27, count 0 2006.201.05:15:17.70#ibcon#wrote, iclass 27, count 0 2006.201.05:15:17.70#ibcon#about to read 3, iclass 27, count 0 2006.201.05:15:17.73#ibcon#read 3, iclass 27, count 0 2006.201.05:15:17.73#ibcon#about to read 4, iclass 27, count 0 2006.201.05:15:17.73#ibcon#read 4, iclass 27, count 0 2006.201.05:15:17.73#ibcon#about to read 5, iclass 27, count 0 2006.201.05:15:17.73#ibcon#read 5, iclass 27, count 0 2006.201.05:15:17.73#ibcon#about to read 6, iclass 27, count 0 2006.201.05:15:17.73#ibcon#read 6, iclass 27, count 0 2006.201.05:15:17.73#ibcon#end of sib2, iclass 27, count 0 2006.201.05:15:17.73#ibcon#*after write, iclass 27, count 0 2006.201.05:15:17.73#ibcon#*before return 0, iclass 27, count 0 2006.201.05:15:17.73#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:17.73#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:15:17.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:15:17.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:15:17.73$vck44/vblo=4,679.99 2006.201.05:15:17.73#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:15:17.73#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:15:17.73#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:17.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:17.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:17.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:17.73#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:15:17.73#ibcon#first serial, iclass 29, count 0 2006.201.05:15:17.73#ibcon#enter sib2, iclass 29, count 0 2006.201.05:15:17.73#ibcon#flushed, iclass 29, count 0 2006.201.05:15:17.73#ibcon#about to write, iclass 29, count 0 2006.201.05:15:17.73#ibcon#wrote, iclass 29, count 0 2006.201.05:15:17.73#ibcon#about to read 3, iclass 29, count 0 2006.201.05:15:17.75#ibcon#read 3, iclass 29, count 0 2006.201.05:15:17.75#ibcon#about to read 4, iclass 29, count 0 2006.201.05:15:17.75#ibcon#read 4, iclass 29, count 0 2006.201.05:15:17.75#ibcon#about to read 5, iclass 29, count 0 2006.201.05:15:17.75#ibcon#read 5, iclass 29, count 0 2006.201.05:15:17.75#ibcon#about to read 6, iclass 29, count 0 2006.201.05:15:17.75#ibcon#read 6, iclass 29, count 0 2006.201.05:15:17.75#ibcon#end of sib2, iclass 29, count 0 2006.201.05:15:17.75#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:15:17.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:15:17.75#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:15:17.75#ibcon#*before write, iclass 29, count 0 2006.201.05:15:17.75#ibcon#enter sib2, iclass 29, count 0 2006.201.05:15:17.75#ibcon#flushed, iclass 29, count 0 2006.201.05:15:17.75#ibcon#about to write, iclass 29, count 0 2006.201.05:15:17.75#ibcon#wrote, iclass 29, count 0 2006.201.05:15:17.75#ibcon#about to read 3, iclass 29, count 0 2006.201.05:15:17.79#ibcon#read 3, iclass 29, count 0 2006.201.05:15:17.79#ibcon#about to read 4, iclass 29, count 0 2006.201.05:15:17.79#ibcon#read 4, iclass 29, count 0 2006.201.05:15:17.79#ibcon#about to read 5, iclass 29, count 0 2006.201.05:15:17.79#ibcon#read 5, iclass 29, count 0 2006.201.05:15:17.79#ibcon#about to read 6, iclass 29, count 0 2006.201.05:15:17.79#ibcon#read 6, iclass 29, count 0 2006.201.05:15:17.79#ibcon#end of sib2, iclass 29, count 0 2006.201.05:15:17.79#ibcon#*after write, iclass 29, count 0 2006.201.05:15:17.79#ibcon#*before return 0, iclass 29, count 0 2006.201.05:15:17.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:17.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:15:17.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:15:17.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:15:17.79$vck44/vb=4,5 2006.201.05:15:17.79#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.05:15:17.79#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.05:15:17.79#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:17.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:17.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:17.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:17.85#ibcon#enter wrdev, iclass 31, count 2 2006.201.05:15:17.85#ibcon#first serial, iclass 31, count 2 2006.201.05:15:17.85#ibcon#enter sib2, iclass 31, count 2 2006.201.05:15:17.85#ibcon#flushed, iclass 31, count 2 2006.201.05:15:17.85#ibcon#about to write, iclass 31, count 2 2006.201.05:15:17.85#ibcon#wrote, iclass 31, count 2 2006.201.05:15:17.85#ibcon#about to read 3, iclass 31, count 2 2006.201.05:15:17.87#ibcon#read 3, iclass 31, count 2 2006.201.05:15:17.87#ibcon#about to read 4, iclass 31, count 2 2006.201.05:15:17.87#ibcon#read 4, iclass 31, count 2 2006.201.05:15:17.87#ibcon#about to read 5, iclass 31, count 2 2006.201.05:15:17.87#ibcon#read 5, iclass 31, count 2 2006.201.05:15:17.87#ibcon#about to read 6, iclass 31, count 2 2006.201.05:15:17.87#ibcon#read 6, iclass 31, count 2 2006.201.05:15:17.87#ibcon#end of sib2, iclass 31, count 2 2006.201.05:15:17.87#ibcon#*mode == 0, iclass 31, count 2 2006.201.05:15:17.87#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.05:15:17.87#ibcon#[27=AT04-05\r\n] 2006.201.05:15:17.87#ibcon#*before write, iclass 31, count 2 2006.201.05:15:17.87#ibcon#enter sib2, iclass 31, count 2 2006.201.05:15:17.87#ibcon#flushed, iclass 31, count 2 2006.201.05:15:17.87#ibcon#about to write, iclass 31, count 2 2006.201.05:15:17.87#ibcon#wrote, iclass 31, count 2 2006.201.05:15:17.87#ibcon#about to read 3, iclass 31, count 2 2006.201.05:15:17.90#ibcon#read 3, iclass 31, count 2 2006.201.05:15:17.90#ibcon#about to read 4, iclass 31, count 2 2006.201.05:15:17.90#ibcon#read 4, iclass 31, count 2 2006.201.05:15:17.90#ibcon#about to read 5, iclass 31, count 2 2006.201.05:15:17.90#ibcon#read 5, iclass 31, count 2 2006.201.05:15:17.90#ibcon#about to read 6, iclass 31, count 2 2006.201.05:15:17.90#ibcon#read 6, iclass 31, count 2 2006.201.05:15:17.90#ibcon#end of sib2, iclass 31, count 2 2006.201.05:15:17.90#ibcon#*after write, iclass 31, count 2 2006.201.05:15:17.90#ibcon#*before return 0, iclass 31, count 2 2006.201.05:15:17.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:17.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:15:17.90#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.05:15:17.90#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:17.90#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:18.02#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:18.02#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:18.02#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:15:18.02#ibcon#first serial, iclass 31, count 0 2006.201.05:15:18.02#ibcon#enter sib2, iclass 31, count 0 2006.201.05:15:18.02#ibcon#flushed, iclass 31, count 0 2006.201.05:15:18.02#ibcon#about to write, iclass 31, count 0 2006.201.05:15:18.02#ibcon#wrote, iclass 31, count 0 2006.201.05:15:18.02#ibcon#about to read 3, iclass 31, count 0 2006.201.05:15:18.04#ibcon#read 3, iclass 31, count 0 2006.201.05:15:18.04#ibcon#about to read 4, iclass 31, count 0 2006.201.05:15:18.04#ibcon#read 4, iclass 31, count 0 2006.201.05:15:18.04#ibcon#about to read 5, iclass 31, count 0 2006.201.05:15:18.04#ibcon#read 5, iclass 31, count 0 2006.201.05:15:18.04#ibcon#about to read 6, iclass 31, count 0 2006.201.05:15:18.04#ibcon#read 6, iclass 31, count 0 2006.201.05:15:18.04#ibcon#end of sib2, iclass 31, count 0 2006.201.05:15:18.04#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:15:18.04#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:15:18.04#ibcon#[27=USB\r\n] 2006.201.05:15:18.04#ibcon#*before write, iclass 31, count 0 2006.201.05:15:18.04#ibcon#enter sib2, iclass 31, count 0 2006.201.05:15:18.04#ibcon#flushed, iclass 31, count 0 2006.201.05:15:18.04#ibcon#about to write, iclass 31, count 0 2006.201.05:15:18.04#ibcon#wrote, iclass 31, count 0 2006.201.05:15:18.04#ibcon#about to read 3, iclass 31, count 0 2006.201.05:15:18.07#ibcon#read 3, iclass 31, count 0 2006.201.05:15:18.07#ibcon#about to read 4, iclass 31, count 0 2006.201.05:15:18.07#ibcon#read 4, iclass 31, count 0 2006.201.05:15:18.07#ibcon#about to read 5, iclass 31, count 0 2006.201.05:15:18.07#ibcon#read 5, iclass 31, count 0 2006.201.05:15:18.07#ibcon#about to read 6, iclass 31, count 0 2006.201.05:15:18.07#ibcon#read 6, iclass 31, count 0 2006.201.05:15:18.07#ibcon#end of sib2, iclass 31, count 0 2006.201.05:15:18.07#ibcon#*after write, iclass 31, count 0 2006.201.05:15:18.07#ibcon#*before return 0, iclass 31, count 0 2006.201.05:15:18.07#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:18.07#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:15:18.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:15:18.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:15:18.07$vck44/vblo=5,709.99 2006.201.05:15:18.07#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.05:15:18.07#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.05:15:18.07#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:18.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:15:18.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:15:18.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:15:18.07#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:15:18.07#ibcon#first serial, iclass 33, count 0 2006.201.05:15:18.07#ibcon#enter sib2, iclass 33, count 0 2006.201.05:15:18.07#ibcon#flushed, iclass 33, count 0 2006.201.05:15:18.07#ibcon#about to write, iclass 33, count 0 2006.201.05:15:18.07#ibcon#wrote, iclass 33, count 0 2006.201.05:15:18.07#ibcon#about to read 3, iclass 33, count 0 2006.201.05:15:18.09#ibcon#read 3, iclass 33, count 0 2006.201.05:15:18.09#ibcon#about to read 4, iclass 33, count 0 2006.201.05:15:18.09#ibcon#read 4, iclass 33, count 0 2006.201.05:15:18.09#ibcon#about to read 5, iclass 33, count 0 2006.201.05:15:18.09#ibcon#read 5, iclass 33, count 0 2006.201.05:15:18.09#ibcon#about to read 6, iclass 33, count 0 2006.201.05:15:18.09#ibcon#read 6, iclass 33, count 0 2006.201.05:15:18.09#ibcon#end of sib2, iclass 33, count 0 2006.201.05:15:18.09#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:15:18.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:15:18.09#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:15:18.09#ibcon#*before write, iclass 33, count 0 2006.201.05:15:18.09#ibcon#enter sib2, iclass 33, count 0 2006.201.05:15:18.09#ibcon#flushed, iclass 33, count 0 2006.201.05:15:18.09#ibcon#about to write, iclass 33, count 0 2006.201.05:15:18.09#ibcon#wrote, iclass 33, count 0 2006.201.05:15:18.09#ibcon#about to read 3, iclass 33, count 0 2006.201.05:15:18.13#ibcon#read 3, iclass 33, count 0 2006.201.05:15:18.13#ibcon#about to read 4, iclass 33, count 0 2006.201.05:15:18.13#ibcon#read 4, iclass 33, count 0 2006.201.05:15:18.13#ibcon#about to read 5, iclass 33, count 0 2006.201.05:15:18.13#ibcon#read 5, iclass 33, count 0 2006.201.05:15:18.13#ibcon#about to read 6, iclass 33, count 0 2006.201.05:15:18.13#ibcon#read 6, iclass 33, count 0 2006.201.05:15:18.13#ibcon#end of sib2, iclass 33, count 0 2006.201.05:15:18.13#ibcon#*after write, iclass 33, count 0 2006.201.05:15:18.13#ibcon#*before return 0, iclass 33, count 0 2006.201.05:15:18.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:15:18.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:15:18.13#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:15:18.13#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:15:18.13$vck44/vb=5,4 2006.201.05:15:18.13#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.05:15:18.13#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.05:15:18.13#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:18.13#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:15:18.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:15:18.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:15:18.19#ibcon#enter wrdev, iclass 35, count 2 2006.201.05:15:18.19#ibcon#first serial, iclass 35, count 2 2006.201.05:15:18.19#ibcon#enter sib2, iclass 35, count 2 2006.201.05:15:18.19#ibcon#flushed, iclass 35, count 2 2006.201.05:15:18.19#ibcon#about to write, iclass 35, count 2 2006.201.05:15:18.19#ibcon#wrote, iclass 35, count 2 2006.201.05:15:18.19#ibcon#about to read 3, iclass 35, count 2 2006.201.05:15:18.21#ibcon#read 3, iclass 35, count 2 2006.201.05:15:18.21#ibcon#about to read 4, iclass 35, count 2 2006.201.05:15:18.21#ibcon#read 4, iclass 35, count 2 2006.201.05:15:18.21#ibcon#about to read 5, iclass 35, count 2 2006.201.05:15:18.21#ibcon#read 5, iclass 35, count 2 2006.201.05:15:18.21#ibcon#about to read 6, iclass 35, count 2 2006.201.05:15:18.21#ibcon#read 6, iclass 35, count 2 2006.201.05:15:18.21#ibcon#end of sib2, iclass 35, count 2 2006.201.05:15:18.21#ibcon#*mode == 0, iclass 35, count 2 2006.201.05:15:18.21#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.05:15:18.21#ibcon#[27=AT05-04\r\n] 2006.201.05:15:18.21#ibcon#*before write, iclass 35, count 2 2006.201.05:15:18.21#ibcon#enter sib2, iclass 35, count 2 2006.201.05:15:18.21#ibcon#flushed, iclass 35, count 2 2006.201.05:15:18.21#ibcon#about to write, iclass 35, count 2 2006.201.05:15:18.21#ibcon#wrote, iclass 35, count 2 2006.201.05:15:18.21#ibcon#about to read 3, iclass 35, count 2 2006.201.05:15:18.24#ibcon#read 3, iclass 35, count 2 2006.201.05:15:18.24#ibcon#about to read 4, iclass 35, count 2 2006.201.05:15:18.24#ibcon#read 4, iclass 35, count 2 2006.201.05:15:18.24#ibcon#about to read 5, iclass 35, count 2 2006.201.05:15:18.24#ibcon#read 5, iclass 35, count 2 2006.201.05:15:18.24#ibcon#about to read 6, iclass 35, count 2 2006.201.05:15:18.24#ibcon#read 6, iclass 35, count 2 2006.201.05:15:18.24#ibcon#end of sib2, iclass 35, count 2 2006.201.05:15:18.24#ibcon#*after write, iclass 35, count 2 2006.201.05:15:18.24#ibcon#*before return 0, iclass 35, count 2 2006.201.05:15:18.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:15:18.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:15:18.24#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.05:15:18.24#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:18.24#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:15:18.36#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:15:18.36#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:15:18.36#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:15:18.36#ibcon#first serial, iclass 35, count 0 2006.201.05:15:18.36#ibcon#enter sib2, iclass 35, count 0 2006.201.05:15:18.36#ibcon#flushed, iclass 35, count 0 2006.201.05:15:18.36#ibcon#about to write, iclass 35, count 0 2006.201.05:15:18.36#ibcon#wrote, iclass 35, count 0 2006.201.05:15:18.36#ibcon#about to read 3, iclass 35, count 0 2006.201.05:15:18.38#ibcon#read 3, iclass 35, count 0 2006.201.05:15:18.38#ibcon#about to read 4, iclass 35, count 0 2006.201.05:15:18.38#ibcon#read 4, iclass 35, count 0 2006.201.05:15:18.38#ibcon#about to read 5, iclass 35, count 0 2006.201.05:15:18.38#ibcon#read 5, iclass 35, count 0 2006.201.05:15:18.38#ibcon#about to read 6, iclass 35, count 0 2006.201.05:15:18.38#ibcon#read 6, iclass 35, count 0 2006.201.05:15:18.38#ibcon#end of sib2, iclass 35, count 0 2006.201.05:15:18.38#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:15:18.38#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:15:18.38#ibcon#[27=USB\r\n] 2006.201.05:15:18.38#ibcon#*before write, iclass 35, count 0 2006.201.05:15:18.38#ibcon#enter sib2, iclass 35, count 0 2006.201.05:15:18.38#ibcon#flushed, iclass 35, count 0 2006.201.05:15:18.38#ibcon#about to write, iclass 35, count 0 2006.201.05:15:18.38#ibcon#wrote, iclass 35, count 0 2006.201.05:15:18.38#ibcon#about to read 3, iclass 35, count 0 2006.201.05:15:18.41#ibcon#read 3, iclass 35, count 0 2006.201.05:15:18.41#ibcon#about to read 4, iclass 35, count 0 2006.201.05:15:18.41#ibcon#read 4, iclass 35, count 0 2006.201.05:15:18.41#ibcon#about to read 5, iclass 35, count 0 2006.201.05:15:18.41#ibcon#read 5, iclass 35, count 0 2006.201.05:15:18.41#ibcon#about to read 6, iclass 35, count 0 2006.201.05:15:18.41#ibcon#read 6, iclass 35, count 0 2006.201.05:15:18.41#ibcon#end of sib2, iclass 35, count 0 2006.201.05:15:18.41#ibcon#*after write, iclass 35, count 0 2006.201.05:15:18.41#ibcon#*before return 0, iclass 35, count 0 2006.201.05:15:18.41#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:15:18.41#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:15:18.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:15:18.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:15:18.41$vck44/vblo=6,719.99 2006.201.05:15:18.41#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.05:15:18.41#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.05:15:18.41#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:18.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:18.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:18.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:18.41#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:15:18.41#ibcon#first serial, iclass 37, count 0 2006.201.05:15:18.41#ibcon#enter sib2, iclass 37, count 0 2006.201.05:15:18.41#ibcon#flushed, iclass 37, count 0 2006.201.05:15:18.41#ibcon#about to write, iclass 37, count 0 2006.201.05:15:18.41#ibcon#wrote, iclass 37, count 0 2006.201.05:15:18.41#ibcon#about to read 3, iclass 37, count 0 2006.201.05:15:18.43#ibcon#read 3, iclass 37, count 0 2006.201.05:15:18.43#ibcon#about to read 4, iclass 37, count 0 2006.201.05:15:18.43#ibcon#read 4, iclass 37, count 0 2006.201.05:15:18.43#ibcon#about to read 5, iclass 37, count 0 2006.201.05:15:18.43#ibcon#read 5, iclass 37, count 0 2006.201.05:15:18.43#ibcon#about to read 6, iclass 37, count 0 2006.201.05:15:18.43#ibcon#read 6, iclass 37, count 0 2006.201.05:15:18.43#ibcon#end of sib2, iclass 37, count 0 2006.201.05:15:18.43#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:15:18.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:15:18.43#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:15:18.43#ibcon#*before write, iclass 37, count 0 2006.201.05:15:18.43#ibcon#enter sib2, iclass 37, count 0 2006.201.05:15:18.43#ibcon#flushed, iclass 37, count 0 2006.201.05:15:18.43#ibcon#about to write, iclass 37, count 0 2006.201.05:15:18.43#ibcon#wrote, iclass 37, count 0 2006.201.05:15:18.43#ibcon#about to read 3, iclass 37, count 0 2006.201.05:15:18.47#ibcon#read 3, iclass 37, count 0 2006.201.05:15:18.47#ibcon#about to read 4, iclass 37, count 0 2006.201.05:15:18.47#ibcon#read 4, iclass 37, count 0 2006.201.05:15:18.47#ibcon#about to read 5, iclass 37, count 0 2006.201.05:15:18.47#ibcon#read 5, iclass 37, count 0 2006.201.05:15:18.47#ibcon#about to read 6, iclass 37, count 0 2006.201.05:15:18.47#ibcon#read 6, iclass 37, count 0 2006.201.05:15:18.47#ibcon#end of sib2, iclass 37, count 0 2006.201.05:15:18.47#ibcon#*after write, iclass 37, count 0 2006.201.05:15:18.47#ibcon#*before return 0, iclass 37, count 0 2006.201.05:15:18.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:18.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:15:18.47#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:15:18.47#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:15:18.47$vck44/vb=6,4 2006.201.05:15:18.47#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.05:15:18.47#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.05:15:18.47#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:18.47#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:18.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:18.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:18.53#ibcon#enter wrdev, iclass 39, count 2 2006.201.05:15:18.53#ibcon#first serial, iclass 39, count 2 2006.201.05:15:18.53#ibcon#enter sib2, iclass 39, count 2 2006.201.05:15:18.53#ibcon#flushed, iclass 39, count 2 2006.201.05:15:18.53#ibcon#about to write, iclass 39, count 2 2006.201.05:15:18.53#ibcon#wrote, iclass 39, count 2 2006.201.05:15:18.53#ibcon#about to read 3, iclass 39, count 2 2006.201.05:15:18.55#ibcon#read 3, iclass 39, count 2 2006.201.05:15:18.55#ibcon#about to read 4, iclass 39, count 2 2006.201.05:15:18.55#ibcon#read 4, iclass 39, count 2 2006.201.05:15:18.55#ibcon#about to read 5, iclass 39, count 2 2006.201.05:15:18.55#ibcon#read 5, iclass 39, count 2 2006.201.05:15:18.55#ibcon#about to read 6, iclass 39, count 2 2006.201.05:15:18.55#ibcon#read 6, iclass 39, count 2 2006.201.05:15:18.55#ibcon#end of sib2, iclass 39, count 2 2006.201.05:15:18.55#ibcon#*mode == 0, iclass 39, count 2 2006.201.05:15:18.55#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.05:15:18.55#ibcon#[27=AT06-04\r\n] 2006.201.05:15:18.55#ibcon#*before write, iclass 39, count 2 2006.201.05:15:18.55#ibcon#enter sib2, iclass 39, count 2 2006.201.05:15:18.55#ibcon#flushed, iclass 39, count 2 2006.201.05:15:18.55#ibcon#about to write, iclass 39, count 2 2006.201.05:15:18.55#ibcon#wrote, iclass 39, count 2 2006.201.05:15:18.55#ibcon#about to read 3, iclass 39, count 2 2006.201.05:15:18.58#ibcon#read 3, iclass 39, count 2 2006.201.05:15:18.58#ibcon#about to read 4, iclass 39, count 2 2006.201.05:15:18.58#ibcon#read 4, iclass 39, count 2 2006.201.05:15:18.58#ibcon#about to read 5, iclass 39, count 2 2006.201.05:15:18.58#ibcon#read 5, iclass 39, count 2 2006.201.05:15:18.58#ibcon#about to read 6, iclass 39, count 2 2006.201.05:15:18.58#ibcon#read 6, iclass 39, count 2 2006.201.05:15:18.58#ibcon#end of sib2, iclass 39, count 2 2006.201.05:15:18.58#ibcon#*after write, iclass 39, count 2 2006.201.05:15:18.58#ibcon#*before return 0, iclass 39, count 2 2006.201.05:15:18.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:18.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:15:18.58#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.05:15:18.58#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:18.58#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:18.70#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:18.70#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:18.70#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:15:18.70#ibcon#first serial, iclass 39, count 0 2006.201.05:15:18.70#ibcon#enter sib2, iclass 39, count 0 2006.201.05:15:18.70#ibcon#flushed, iclass 39, count 0 2006.201.05:15:18.70#ibcon#about to write, iclass 39, count 0 2006.201.05:15:18.70#ibcon#wrote, iclass 39, count 0 2006.201.05:15:18.70#ibcon#about to read 3, iclass 39, count 0 2006.201.05:15:18.72#ibcon#read 3, iclass 39, count 0 2006.201.05:15:18.72#ibcon#about to read 4, iclass 39, count 0 2006.201.05:15:18.72#ibcon#read 4, iclass 39, count 0 2006.201.05:15:18.72#ibcon#about to read 5, iclass 39, count 0 2006.201.05:15:18.72#ibcon#read 5, iclass 39, count 0 2006.201.05:15:18.72#ibcon#about to read 6, iclass 39, count 0 2006.201.05:15:18.72#ibcon#read 6, iclass 39, count 0 2006.201.05:15:18.72#ibcon#end of sib2, iclass 39, count 0 2006.201.05:15:18.72#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:15:18.72#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:15:18.72#ibcon#[27=USB\r\n] 2006.201.05:15:18.72#ibcon#*before write, iclass 39, count 0 2006.201.05:15:18.72#ibcon#enter sib2, iclass 39, count 0 2006.201.05:15:18.72#ibcon#flushed, iclass 39, count 0 2006.201.05:15:18.72#ibcon#about to write, iclass 39, count 0 2006.201.05:15:18.72#ibcon#wrote, iclass 39, count 0 2006.201.05:15:18.72#ibcon#about to read 3, iclass 39, count 0 2006.201.05:15:18.75#ibcon#read 3, iclass 39, count 0 2006.201.05:15:18.75#ibcon#about to read 4, iclass 39, count 0 2006.201.05:15:18.75#ibcon#read 4, iclass 39, count 0 2006.201.05:15:18.75#ibcon#about to read 5, iclass 39, count 0 2006.201.05:15:18.75#ibcon#read 5, iclass 39, count 0 2006.201.05:15:18.75#ibcon#about to read 6, iclass 39, count 0 2006.201.05:15:18.75#ibcon#read 6, iclass 39, count 0 2006.201.05:15:18.75#ibcon#end of sib2, iclass 39, count 0 2006.201.05:15:18.75#ibcon#*after write, iclass 39, count 0 2006.201.05:15:18.75#ibcon#*before return 0, iclass 39, count 0 2006.201.05:15:18.75#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:18.75#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:15:18.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:15:18.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:15:18.75$vck44/vblo=7,734.99 2006.201.05:15:18.75#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.05:15:18.75#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.05:15:18.75#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:18.75#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:18.75#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:18.75#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:18.75#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:15:18.75#ibcon#first serial, iclass 2, count 0 2006.201.05:15:18.75#ibcon#enter sib2, iclass 2, count 0 2006.201.05:15:18.75#ibcon#flushed, iclass 2, count 0 2006.201.05:15:18.75#ibcon#about to write, iclass 2, count 0 2006.201.05:15:18.75#ibcon#wrote, iclass 2, count 0 2006.201.05:15:18.75#ibcon#about to read 3, iclass 2, count 0 2006.201.05:15:18.77#ibcon#read 3, iclass 2, count 0 2006.201.05:15:18.77#ibcon#about to read 4, iclass 2, count 0 2006.201.05:15:18.77#ibcon#read 4, iclass 2, count 0 2006.201.05:15:18.77#ibcon#about to read 5, iclass 2, count 0 2006.201.05:15:18.77#ibcon#read 5, iclass 2, count 0 2006.201.05:15:18.77#ibcon#about to read 6, iclass 2, count 0 2006.201.05:15:18.77#ibcon#read 6, iclass 2, count 0 2006.201.05:15:18.77#ibcon#end of sib2, iclass 2, count 0 2006.201.05:15:18.77#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:15:18.77#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:15:18.77#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:15:18.77#ibcon#*before write, iclass 2, count 0 2006.201.05:15:18.77#ibcon#enter sib2, iclass 2, count 0 2006.201.05:15:18.77#ibcon#flushed, iclass 2, count 0 2006.201.05:15:18.77#ibcon#about to write, iclass 2, count 0 2006.201.05:15:18.77#ibcon#wrote, iclass 2, count 0 2006.201.05:15:18.77#ibcon#about to read 3, iclass 2, count 0 2006.201.05:15:18.81#ibcon#read 3, iclass 2, count 0 2006.201.05:15:18.81#ibcon#about to read 4, iclass 2, count 0 2006.201.05:15:18.81#ibcon#read 4, iclass 2, count 0 2006.201.05:15:18.81#ibcon#about to read 5, iclass 2, count 0 2006.201.05:15:18.81#ibcon#read 5, iclass 2, count 0 2006.201.05:15:18.81#ibcon#about to read 6, iclass 2, count 0 2006.201.05:15:18.81#ibcon#read 6, iclass 2, count 0 2006.201.05:15:18.81#ibcon#end of sib2, iclass 2, count 0 2006.201.05:15:18.81#ibcon#*after write, iclass 2, count 0 2006.201.05:15:18.81#ibcon#*before return 0, iclass 2, count 0 2006.201.05:15:18.81#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:18.81#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:15:18.81#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:15:18.81#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:15:18.81$vck44/vb=7,4 2006.201.05:15:18.81#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.05:15:18.81#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.05:15:18.81#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:18.81#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:18.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:18.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:18.87#ibcon#enter wrdev, iclass 5, count 2 2006.201.05:15:18.87#ibcon#first serial, iclass 5, count 2 2006.201.05:15:18.87#ibcon#enter sib2, iclass 5, count 2 2006.201.05:15:18.87#ibcon#flushed, iclass 5, count 2 2006.201.05:15:18.87#ibcon#about to write, iclass 5, count 2 2006.201.05:15:18.87#ibcon#wrote, iclass 5, count 2 2006.201.05:15:18.87#ibcon#about to read 3, iclass 5, count 2 2006.201.05:15:18.89#ibcon#read 3, iclass 5, count 2 2006.201.05:15:18.89#ibcon#about to read 4, iclass 5, count 2 2006.201.05:15:18.89#ibcon#read 4, iclass 5, count 2 2006.201.05:15:18.89#ibcon#about to read 5, iclass 5, count 2 2006.201.05:15:18.89#ibcon#read 5, iclass 5, count 2 2006.201.05:15:18.89#ibcon#about to read 6, iclass 5, count 2 2006.201.05:15:18.89#ibcon#read 6, iclass 5, count 2 2006.201.05:15:18.89#ibcon#end of sib2, iclass 5, count 2 2006.201.05:15:18.89#ibcon#*mode == 0, iclass 5, count 2 2006.201.05:15:18.89#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.05:15:18.89#ibcon#[27=AT07-04\r\n] 2006.201.05:15:18.89#ibcon#*before write, iclass 5, count 2 2006.201.05:15:18.89#ibcon#enter sib2, iclass 5, count 2 2006.201.05:15:18.89#ibcon#flushed, iclass 5, count 2 2006.201.05:15:18.89#ibcon#about to write, iclass 5, count 2 2006.201.05:15:18.89#ibcon#wrote, iclass 5, count 2 2006.201.05:15:18.89#ibcon#about to read 3, iclass 5, count 2 2006.201.05:15:18.92#ibcon#read 3, iclass 5, count 2 2006.201.05:15:18.92#ibcon#about to read 4, iclass 5, count 2 2006.201.05:15:18.92#ibcon#read 4, iclass 5, count 2 2006.201.05:15:18.92#ibcon#about to read 5, iclass 5, count 2 2006.201.05:15:18.92#ibcon#read 5, iclass 5, count 2 2006.201.05:15:18.92#ibcon#about to read 6, iclass 5, count 2 2006.201.05:15:18.92#ibcon#read 6, iclass 5, count 2 2006.201.05:15:18.92#ibcon#end of sib2, iclass 5, count 2 2006.201.05:15:18.92#ibcon#*after write, iclass 5, count 2 2006.201.05:15:18.92#ibcon#*before return 0, iclass 5, count 2 2006.201.05:15:18.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:18.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:15:18.92#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.05:15:18.92#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:18.92#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:19.04#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:19.04#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:19.04#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:15:19.04#ibcon#first serial, iclass 5, count 0 2006.201.05:15:19.04#ibcon#enter sib2, iclass 5, count 0 2006.201.05:15:19.04#ibcon#flushed, iclass 5, count 0 2006.201.05:15:19.04#ibcon#about to write, iclass 5, count 0 2006.201.05:15:19.04#ibcon#wrote, iclass 5, count 0 2006.201.05:15:19.04#ibcon#about to read 3, iclass 5, count 0 2006.201.05:15:19.06#ibcon#read 3, iclass 5, count 0 2006.201.05:15:19.06#ibcon#about to read 4, iclass 5, count 0 2006.201.05:15:19.06#ibcon#read 4, iclass 5, count 0 2006.201.05:15:19.06#ibcon#about to read 5, iclass 5, count 0 2006.201.05:15:19.06#ibcon#read 5, iclass 5, count 0 2006.201.05:15:19.06#ibcon#about to read 6, iclass 5, count 0 2006.201.05:15:19.06#ibcon#read 6, iclass 5, count 0 2006.201.05:15:19.06#ibcon#end of sib2, iclass 5, count 0 2006.201.05:15:19.06#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:15:19.06#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:15:19.06#ibcon#[27=USB\r\n] 2006.201.05:15:19.06#ibcon#*before write, iclass 5, count 0 2006.201.05:15:19.06#ibcon#enter sib2, iclass 5, count 0 2006.201.05:15:19.06#ibcon#flushed, iclass 5, count 0 2006.201.05:15:19.06#ibcon#about to write, iclass 5, count 0 2006.201.05:15:19.06#ibcon#wrote, iclass 5, count 0 2006.201.05:15:19.06#ibcon#about to read 3, iclass 5, count 0 2006.201.05:15:19.09#ibcon#read 3, iclass 5, count 0 2006.201.05:15:19.09#ibcon#about to read 4, iclass 5, count 0 2006.201.05:15:19.09#ibcon#read 4, iclass 5, count 0 2006.201.05:15:19.09#ibcon#about to read 5, iclass 5, count 0 2006.201.05:15:19.09#ibcon#read 5, iclass 5, count 0 2006.201.05:15:19.09#ibcon#about to read 6, iclass 5, count 0 2006.201.05:15:19.09#ibcon#read 6, iclass 5, count 0 2006.201.05:15:19.09#ibcon#end of sib2, iclass 5, count 0 2006.201.05:15:19.09#ibcon#*after write, iclass 5, count 0 2006.201.05:15:19.09#ibcon#*before return 0, iclass 5, count 0 2006.201.05:15:19.09#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:19.09#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:15:19.09#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:15:19.09#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:15:19.09$vck44/vblo=8,744.99 2006.201.05:15:19.09#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.05:15:19.09#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.05:15:19.09#ibcon#ireg 17 cls_cnt 0 2006.201.05:15:19.09#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:19.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:19.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:19.09#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:15:19.09#ibcon#first serial, iclass 7, count 0 2006.201.05:15:19.09#ibcon#enter sib2, iclass 7, count 0 2006.201.05:15:19.09#ibcon#flushed, iclass 7, count 0 2006.201.05:15:19.09#ibcon#about to write, iclass 7, count 0 2006.201.05:15:19.09#ibcon#wrote, iclass 7, count 0 2006.201.05:15:19.09#ibcon#about to read 3, iclass 7, count 0 2006.201.05:15:19.11#ibcon#read 3, iclass 7, count 0 2006.201.05:15:19.11#ibcon#about to read 4, iclass 7, count 0 2006.201.05:15:19.11#ibcon#read 4, iclass 7, count 0 2006.201.05:15:19.11#ibcon#about to read 5, iclass 7, count 0 2006.201.05:15:19.11#ibcon#read 5, iclass 7, count 0 2006.201.05:15:19.11#ibcon#about to read 6, iclass 7, count 0 2006.201.05:15:19.11#ibcon#read 6, iclass 7, count 0 2006.201.05:15:19.11#ibcon#end of sib2, iclass 7, count 0 2006.201.05:15:19.11#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:15:19.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:15:19.11#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:15:19.11#ibcon#*before write, iclass 7, count 0 2006.201.05:15:19.11#ibcon#enter sib2, iclass 7, count 0 2006.201.05:15:19.11#ibcon#flushed, iclass 7, count 0 2006.201.05:15:19.11#ibcon#about to write, iclass 7, count 0 2006.201.05:15:19.11#ibcon#wrote, iclass 7, count 0 2006.201.05:15:19.11#ibcon#about to read 3, iclass 7, count 0 2006.201.05:15:19.15#ibcon#read 3, iclass 7, count 0 2006.201.05:15:19.15#ibcon#about to read 4, iclass 7, count 0 2006.201.05:15:19.15#ibcon#read 4, iclass 7, count 0 2006.201.05:15:19.15#ibcon#about to read 5, iclass 7, count 0 2006.201.05:15:19.15#ibcon#read 5, iclass 7, count 0 2006.201.05:15:19.15#ibcon#about to read 6, iclass 7, count 0 2006.201.05:15:19.15#ibcon#read 6, iclass 7, count 0 2006.201.05:15:19.15#ibcon#end of sib2, iclass 7, count 0 2006.201.05:15:19.15#ibcon#*after write, iclass 7, count 0 2006.201.05:15:19.15#ibcon#*before return 0, iclass 7, count 0 2006.201.05:15:19.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:19.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:15:19.15#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:15:19.15#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:15:19.15$vck44/vb=8,4 2006.201.05:15:19.15#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.05:15:19.15#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.05:15:19.15#ibcon#ireg 11 cls_cnt 2 2006.201.05:15:19.15#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:19.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:19.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:19.21#ibcon#enter wrdev, iclass 11, count 2 2006.201.05:15:19.21#ibcon#first serial, iclass 11, count 2 2006.201.05:15:19.21#ibcon#enter sib2, iclass 11, count 2 2006.201.05:15:19.21#ibcon#flushed, iclass 11, count 2 2006.201.05:15:19.21#ibcon#about to write, iclass 11, count 2 2006.201.05:15:19.21#ibcon#wrote, iclass 11, count 2 2006.201.05:15:19.21#ibcon#about to read 3, iclass 11, count 2 2006.201.05:15:19.23#ibcon#read 3, iclass 11, count 2 2006.201.05:15:19.23#ibcon#about to read 4, iclass 11, count 2 2006.201.05:15:19.23#ibcon#read 4, iclass 11, count 2 2006.201.05:15:19.23#ibcon#about to read 5, iclass 11, count 2 2006.201.05:15:19.23#ibcon#read 5, iclass 11, count 2 2006.201.05:15:19.23#ibcon#about to read 6, iclass 11, count 2 2006.201.05:15:19.23#ibcon#read 6, iclass 11, count 2 2006.201.05:15:19.23#ibcon#end of sib2, iclass 11, count 2 2006.201.05:15:19.23#ibcon#*mode == 0, iclass 11, count 2 2006.201.05:15:19.23#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.05:15:19.23#ibcon#[27=AT08-04\r\n] 2006.201.05:15:19.23#ibcon#*before write, iclass 11, count 2 2006.201.05:15:19.23#ibcon#enter sib2, iclass 11, count 2 2006.201.05:15:19.23#ibcon#flushed, iclass 11, count 2 2006.201.05:15:19.23#ibcon#about to write, iclass 11, count 2 2006.201.05:15:19.23#ibcon#wrote, iclass 11, count 2 2006.201.05:15:19.23#ibcon#about to read 3, iclass 11, count 2 2006.201.05:15:19.26#ibcon#read 3, iclass 11, count 2 2006.201.05:15:19.26#ibcon#about to read 4, iclass 11, count 2 2006.201.05:15:19.26#ibcon#read 4, iclass 11, count 2 2006.201.05:15:19.26#ibcon#about to read 5, iclass 11, count 2 2006.201.05:15:19.26#ibcon#read 5, iclass 11, count 2 2006.201.05:15:19.26#ibcon#about to read 6, iclass 11, count 2 2006.201.05:15:19.26#ibcon#read 6, iclass 11, count 2 2006.201.05:15:19.26#ibcon#end of sib2, iclass 11, count 2 2006.201.05:15:19.26#ibcon#*after write, iclass 11, count 2 2006.201.05:15:19.26#ibcon#*before return 0, iclass 11, count 2 2006.201.05:15:19.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:19.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:15:19.26#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.05:15:19.26#ibcon#ireg 7 cls_cnt 0 2006.201.05:15:19.26#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:19.38#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:19.38#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:19.38#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:15:19.38#ibcon#first serial, iclass 11, count 0 2006.201.05:15:19.38#ibcon#enter sib2, iclass 11, count 0 2006.201.05:15:19.38#ibcon#flushed, iclass 11, count 0 2006.201.05:15:19.38#ibcon#about to write, iclass 11, count 0 2006.201.05:15:19.38#ibcon#wrote, iclass 11, count 0 2006.201.05:15:19.38#ibcon#about to read 3, iclass 11, count 0 2006.201.05:15:19.40#ibcon#read 3, iclass 11, count 0 2006.201.05:15:19.40#ibcon#about to read 4, iclass 11, count 0 2006.201.05:15:19.40#ibcon#read 4, iclass 11, count 0 2006.201.05:15:19.40#ibcon#about to read 5, iclass 11, count 0 2006.201.05:15:19.40#ibcon#read 5, iclass 11, count 0 2006.201.05:15:19.40#ibcon#about to read 6, iclass 11, count 0 2006.201.05:15:19.40#ibcon#read 6, iclass 11, count 0 2006.201.05:15:19.40#ibcon#end of sib2, iclass 11, count 0 2006.201.05:15:19.40#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:15:19.40#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:15:19.40#ibcon#[27=USB\r\n] 2006.201.05:15:19.40#ibcon#*before write, iclass 11, count 0 2006.201.05:15:19.40#ibcon#enter sib2, iclass 11, count 0 2006.201.05:15:19.40#ibcon#flushed, iclass 11, count 0 2006.201.05:15:19.40#ibcon#about to write, iclass 11, count 0 2006.201.05:15:19.40#ibcon#wrote, iclass 11, count 0 2006.201.05:15:19.40#ibcon#about to read 3, iclass 11, count 0 2006.201.05:15:19.43#ibcon#read 3, iclass 11, count 0 2006.201.05:15:19.43#ibcon#about to read 4, iclass 11, count 0 2006.201.05:15:19.43#ibcon#read 4, iclass 11, count 0 2006.201.05:15:19.43#ibcon#about to read 5, iclass 11, count 0 2006.201.05:15:19.43#ibcon#read 5, iclass 11, count 0 2006.201.05:15:19.43#ibcon#about to read 6, iclass 11, count 0 2006.201.05:15:19.43#ibcon#read 6, iclass 11, count 0 2006.201.05:15:19.43#ibcon#end of sib2, iclass 11, count 0 2006.201.05:15:19.43#ibcon#*after write, iclass 11, count 0 2006.201.05:15:19.43#ibcon#*before return 0, iclass 11, count 0 2006.201.05:15:19.43#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:19.43#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:15:19.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:15:19.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:15:19.43$vck44/vabw=wide 2006.201.05:15:19.43#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.05:15:19.43#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.05:15:19.43#ibcon#ireg 8 cls_cnt 0 2006.201.05:15:19.43#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:19.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:19.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:19.43#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:15:19.43#ibcon#first serial, iclass 13, count 0 2006.201.05:15:19.43#ibcon#enter sib2, iclass 13, count 0 2006.201.05:15:19.43#ibcon#flushed, iclass 13, count 0 2006.201.05:15:19.43#ibcon#about to write, iclass 13, count 0 2006.201.05:15:19.43#ibcon#wrote, iclass 13, count 0 2006.201.05:15:19.43#ibcon#about to read 3, iclass 13, count 0 2006.201.05:15:19.45#ibcon#read 3, iclass 13, count 0 2006.201.05:15:19.45#ibcon#about to read 4, iclass 13, count 0 2006.201.05:15:19.45#ibcon#read 4, iclass 13, count 0 2006.201.05:15:19.45#ibcon#about to read 5, iclass 13, count 0 2006.201.05:15:19.45#ibcon#read 5, iclass 13, count 0 2006.201.05:15:19.45#ibcon#about to read 6, iclass 13, count 0 2006.201.05:15:19.45#ibcon#read 6, iclass 13, count 0 2006.201.05:15:19.45#ibcon#end of sib2, iclass 13, count 0 2006.201.05:15:19.45#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:15:19.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:15:19.45#ibcon#[25=BW32\r\n] 2006.201.05:15:19.45#ibcon#*before write, iclass 13, count 0 2006.201.05:15:19.45#ibcon#enter sib2, iclass 13, count 0 2006.201.05:15:19.45#ibcon#flushed, iclass 13, count 0 2006.201.05:15:19.45#ibcon#about to write, iclass 13, count 0 2006.201.05:15:19.45#ibcon#wrote, iclass 13, count 0 2006.201.05:15:19.45#ibcon#about to read 3, iclass 13, count 0 2006.201.05:15:19.48#ibcon#read 3, iclass 13, count 0 2006.201.05:15:19.48#ibcon#about to read 4, iclass 13, count 0 2006.201.05:15:19.48#ibcon#read 4, iclass 13, count 0 2006.201.05:15:19.48#ibcon#about to read 5, iclass 13, count 0 2006.201.05:15:19.48#ibcon#read 5, iclass 13, count 0 2006.201.05:15:19.48#ibcon#about to read 6, iclass 13, count 0 2006.201.05:15:19.48#ibcon#read 6, iclass 13, count 0 2006.201.05:15:19.48#ibcon#end of sib2, iclass 13, count 0 2006.201.05:15:19.48#ibcon#*after write, iclass 13, count 0 2006.201.05:15:19.48#ibcon#*before return 0, iclass 13, count 0 2006.201.05:15:19.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:19.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:15:19.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:15:19.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:15:19.48$vck44/vbbw=wide 2006.201.05:15:19.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.05:15:19.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.05:15:19.48#ibcon#ireg 8 cls_cnt 0 2006.201.05:15:19.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:15:19.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:15:19.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:15:19.55#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:15:19.55#ibcon#first serial, iclass 15, count 0 2006.201.05:15:19.55#ibcon#enter sib2, iclass 15, count 0 2006.201.05:15:19.55#ibcon#flushed, iclass 15, count 0 2006.201.05:15:19.55#ibcon#about to write, iclass 15, count 0 2006.201.05:15:19.55#ibcon#wrote, iclass 15, count 0 2006.201.05:15:19.55#ibcon#about to read 3, iclass 15, count 0 2006.201.05:15:19.57#ibcon#read 3, iclass 15, count 0 2006.201.05:15:19.57#ibcon#about to read 4, iclass 15, count 0 2006.201.05:15:19.57#ibcon#read 4, iclass 15, count 0 2006.201.05:15:19.57#ibcon#about to read 5, iclass 15, count 0 2006.201.05:15:19.57#ibcon#read 5, iclass 15, count 0 2006.201.05:15:19.57#ibcon#about to read 6, iclass 15, count 0 2006.201.05:15:19.57#ibcon#read 6, iclass 15, count 0 2006.201.05:15:19.57#ibcon#end of sib2, iclass 15, count 0 2006.201.05:15:19.57#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:15:19.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:15:19.57#ibcon#[27=BW32\r\n] 2006.201.05:15:19.57#ibcon#*before write, iclass 15, count 0 2006.201.05:15:19.57#ibcon#enter sib2, iclass 15, count 0 2006.201.05:15:19.57#ibcon#flushed, iclass 15, count 0 2006.201.05:15:19.57#ibcon#about to write, iclass 15, count 0 2006.201.05:15:19.57#ibcon#wrote, iclass 15, count 0 2006.201.05:15:19.57#ibcon#about to read 3, iclass 15, count 0 2006.201.05:15:19.60#ibcon#read 3, iclass 15, count 0 2006.201.05:15:19.60#ibcon#about to read 4, iclass 15, count 0 2006.201.05:15:19.60#ibcon#read 4, iclass 15, count 0 2006.201.05:15:19.60#ibcon#about to read 5, iclass 15, count 0 2006.201.05:15:19.60#ibcon#read 5, iclass 15, count 0 2006.201.05:15:19.60#ibcon#about to read 6, iclass 15, count 0 2006.201.05:15:19.60#ibcon#read 6, iclass 15, count 0 2006.201.05:15:19.60#ibcon#end of sib2, iclass 15, count 0 2006.201.05:15:19.60#ibcon#*after write, iclass 15, count 0 2006.201.05:15:19.60#ibcon#*before return 0, iclass 15, count 0 2006.201.05:15:19.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:15:19.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:15:19.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:15:19.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:15:19.60$setupk4/ifdk4 2006.201.05:15:19.60$ifdk4/lo= 2006.201.05:15:19.60$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:15:19.60$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:15:19.60$ifdk4/patch= 2006.201.05:15:19.60$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:15:19.60$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:15:19.60$setupk4/!*+20s 2006.201.05:15:25.38#abcon#<5=/05 3.1 5.3 23.34 901003.8\r\n> 2006.201.05:15:25.40#abcon#{5=INTERFACE CLEAR} 2006.201.05:15:25.46#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:15:32.30$setupk4/"tpicd 2006.201.05:15:32.30$setupk4/echo=off 2006.201.05:15:32.30$setupk4/xlog=off 2006.201.05:15:32.30:!2006.201.05:24:19 2006.201.05:15:34.14#trakl#Source acquired 2006.201.05:15:35.14#flagr#flagr/antenna,acquired 2006.201.05:24:19.00:preob 2006.201.05:24:19.14/onsource/TRACKING 2006.201.05:24:19.14:!2006.201.05:24:29 2006.201.05:24:29.00:"tape 2006.201.05:24:29.00:"st=record 2006.201.05:24:29.00:data_valid=on 2006.201.05:24:29.00:midob 2006.201.05:24:29.14/onsource/TRACKING 2006.201.05:24:29.14/wx/23.27,1003.7,90 2006.201.05:24:29.22/cable/+6.4660E-03 2006.201.05:24:30.31/va/01,08,usb,yes,28,30 2006.201.05:24:30.31/va/02,07,usb,yes,30,31 2006.201.05:24:30.31/va/03,08,usb,yes,27,28 2006.201.05:24:30.31/va/04,07,usb,yes,31,33 2006.201.05:24:30.31/va/05,04,usb,yes,27,28 2006.201.05:24:30.31/va/06,05,usb,yes,27,27 2006.201.05:24:30.31/va/07,05,usb,yes,26,28 2006.201.05:24:30.31/va/08,04,usb,yes,26,32 2006.201.05:24:30.54/valo/01,524.99,yes,locked 2006.201.05:24:30.54/valo/02,534.99,yes,locked 2006.201.05:24:30.54/valo/03,564.99,yes,locked 2006.201.05:24:30.54/valo/04,624.99,yes,locked 2006.201.05:24:30.54/valo/05,734.99,yes,locked 2006.201.05:24:30.54/valo/06,814.99,yes,locked 2006.201.05:24:30.54/valo/07,864.99,yes,locked 2006.201.05:24:30.54/valo/08,884.99,yes,locked 2006.201.05:24:31.63/vb/01,04,usb,yes,28,26 2006.201.05:24:31.63/vb/02,05,usb,yes,27,27 2006.201.05:24:31.63/vb/03,04,usb,yes,28,31 2006.201.05:24:31.63/vb/04,05,usb,yes,28,27 2006.201.05:24:31.63/vb/05,04,usb,yes,25,27 2006.201.05:24:31.63/vb/06,04,usb,yes,29,25 2006.201.05:24:31.63/vb/07,04,usb,yes,29,29 2006.201.05:24:31.63/vb/08,04,usb,yes,26,30 2006.201.05:24:31.87/vblo/01,629.99,yes,locked 2006.201.05:24:31.87/vblo/02,634.99,yes,locked 2006.201.05:24:31.87/vblo/03,649.99,yes,locked 2006.201.05:24:31.87/vblo/04,679.99,yes,locked 2006.201.05:24:31.87/vblo/05,709.99,yes,locked 2006.201.05:24:31.87/vblo/06,719.99,yes,locked 2006.201.05:24:31.87/vblo/07,734.99,yes,locked 2006.201.05:24:31.87/vblo/08,744.99,yes,locked 2006.201.05:24:32.02/vabw/8 2006.201.05:24:32.17/vbbw/8 2006.201.05:24:32.26/xfe/off,on,15.5 2006.201.05:24:32.63/ifatt/23,28,28,28 2006.201.05:24:33.04/fmout-gps/S +4.48E-07 2006.201.05:24:33.08:!2006.201.05:28:09 2006.201.05:28:09.00:data_valid=off 2006.201.05:28:09.00:"et 2006.201.05:28:09.00:!+3s 2006.201.05:28:12.02:"tape 2006.201.05:28:12.02:postob 2006.201.05:28:12.23/cable/+6.4658E-03 2006.201.05:28:12.23/wx/23.21,1003.6,91 2006.201.05:28:12.29/fmout-gps/S +4.48E-07 2006.201.05:28:12.29:scan_name=201-0531,jd0607,40 2006.201.05:28:12.29:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.201.05:28:14.13#flagr#flagr/antenna,new-source 2006.201.05:28:14.13:checkk5 2006.201.05:28:14.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:28:14.92/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:28:15.34/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:28:15.76/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:28:16.14/chk_obsdata//k5ts1/T2010524??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.05:28:16.56/chk_obsdata//k5ts2/T2010524??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.05:28:16.96/chk_obsdata//k5ts3/T2010524??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.05:28:17.37/chk_obsdata//k5ts4/T2010524??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.05:28:18.09/k5log//k5ts1_log_newline 2006.201.05:28:18.79/k5log//k5ts2_log_newline 2006.201.05:28:19.51/k5log//k5ts3_log_newline 2006.201.05:28:20.23/k5log//k5ts4_log_newline 2006.201.05:28:20.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:28:20.25:setupk4=1 2006.201.05:28:20.25$setupk4/echo=on 2006.201.05:28:20.25$setupk4/pcalon 2006.201.05:28:20.25$pcalon/"no phase cal control is implemented here 2006.201.05:28:20.25$setupk4/"tpicd=stop 2006.201.05:28:20.25$setupk4/"rec=synch_on 2006.201.05:28:20.25$setupk4/"rec_mode=128 2006.201.05:28:20.25$setupk4/!* 2006.201.05:28:20.25$setupk4/recpk4 2006.201.05:28:20.25$recpk4/recpatch= 2006.201.05:28:20.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:28:20.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:28:20.26$setupk4/vck44 2006.201.05:28:20.26$vck44/valo=1,524.99 2006.201.05:28:20.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.05:28:20.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.05:28:20.26#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:20.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:20.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:20.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:20.26#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:28:20.26#ibcon#first serial, iclass 31, count 0 2006.201.05:28:20.26#ibcon#enter sib2, iclass 31, count 0 2006.201.05:28:20.26#ibcon#flushed, iclass 31, count 0 2006.201.05:28:20.26#ibcon#about to write, iclass 31, count 0 2006.201.05:28:20.26#ibcon#wrote, iclass 31, count 0 2006.201.05:28:20.26#ibcon#about to read 3, iclass 31, count 0 2006.201.05:28:20.28#ibcon#read 3, iclass 31, count 0 2006.201.05:28:20.28#ibcon#about to read 4, iclass 31, count 0 2006.201.05:28:20.28#ibcon#read 4, iclass 31, count 0 2006.201.05:28:20.28#ibcon#about to read 5, iclass 31, count 0 2006.201.05:28:20.28#ibcon#read 5, iclass 31, count 0 2006.201.05:28:20.28#ibcon#about to read 6, iclass 31, count 0 2006.201.05:28:20.28#ibcon#read 6, iclass 31, count 0 2006.201.05:28:20.28#ibcon#end of sib2, iclass 31, count 0 2006.201.05:28:20.28#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:28:20.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:28:20.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:28:20.28#ibcon#*before write, iclass 31, count 0 2006.201.05:28:20.28#ibcon#enter sib2, iclass 31, count 0 2006.201.05:28:20.28#ibcon#flushed, iclass 31, count 0 2006.201.05:28:20.28#ibcon#about to write, iclass 31, count 0 2006.201.05:28:20.28#ibcon#wrote, iclass 31, count 0 2006.201.05:28:20.28#ibcon#about to read 3, iclass 31, count 0 2006.201.05:28:20.33#ibcon#read 3, iclass 31, count 0 2006.201.05:28:20.33#ibcon#about to read 4, iclass 31, count 0 2006.201.05:28:20.33#ibcon#read 4, iclass 31, count 0 2006.201.05:28:20.33#ibcon#about to read 5, iclass 31, count 0 2006.201.05:28:20.33#ibcon#read 5, iclass 31, count 0 2006.201.05:28:20.33#ibcon#about to read 6, iclass 31, count 0 2006.201.05:28:20.33#ibcon#read 6, iclass 31, count 0 2006.201.05:28:20.33#ibcon#end of sib2, iclass 31, count 0 2006.201.05:28:20.33#ibcon#*after write, iclass 31, count 0 2006.201.05:28:20.33#ibcon#*before return 0, iclass 31, count 0 2006.201.05:28:20.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:20.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:20.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:28:20.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:28:20.33$vck44/va=1,8 2006.201.05:28:20.33#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.05:28:20.33#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.05:28:20.33#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:20.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:20.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:20.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:20.33#ibcon#enter wrdev, iclass 33, count 2 2006.201.05:28:20.33#ibcon#first serial, iclass 33, count 2 2006.201.05:28:20.33#ibcon#enter sib2, iclass 33, count 2 2006.201.05:28:20.33#ibcon#flushed, iclass 33, count 2 2006.201.05:28:20.33#ibcon#about to write, iclass 33, count 2 2006.201.05:28:20.33#ibcon#wrote, iclass 33, count 2 2006.201.05:28:20.33#ibcon#about to read 3, iclass 33, count 2 2006.201.05:28:20.35#ibcon#read 3, iclass 33, count 2 2006.201.05:28:20.35#ibcon#about to read 4, iclass 33, count 2 2006.201.05:28:20.35#ibcon#read 4, iclass 33, count 2 2006.201.05:28:20.35#ibcon#about to read 5, iclass 33, count 2 2006.201.05:28:20.35#ibcon#read 5, iclass 33, count 2 2006.201.05:28:20.35#ibcon#about to read 6, iclass 33, count 2 2006.201.05:28:20.35#ibcon#read 6, iclass 33, count 2 2006.201.05:28:20.35#ibcon#end of sib2, iclass 33, count 2 2006.201.05:28:20.35#ibcon#*mode == 0, iclass 33, count 2 2006.201.05:28:20.35#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.05:28:20.35#ibcon#[25=AT01-08\r\n] 2006.201.05:28:20.35#ibcon#*before write, iclass 33, count 2 2006.201.05:28:20.35#ibcon#enter sib2, iclass 33, count 2 2006.201.05:28:20.35#ibcon#flushed, iclass 33, count 2 2006.201.05:28:20.35#ibcon#about to write, iclass 33, count 2 2006.201.05:28:20.35#ibcon#wrote, iclass 33, count 2 2006.201.05:28:20.35#ibcon#about to read 3, iclass 33, count 2 2006.201.05:28:20.38#ibcon#read 3, iclass 33, count 2 2006.201.05:28:20.38#ibcon#about to read 4, iclass 33, count 2 2006.201.05:28:20.38#ibcon#read 4, iclass 33, count 2 2006.201.05:28:20.38#ibcon#about to read 5, iclass 33, count 2 2006.201.05:28:20.38#ibcon#read 5, iclass 33, count 2 2006.201.05:28:20.38#ibcon#about to read 6, iclass 33, count 2 2006.201.05:28:20.38#ibcon#read 6, iclass 33, count 2 2006.201.05:28:20.38#ibcon#end of sib2, iclass 33, count 2 2006.201.05:28:20.38#ibcon#*after write, iclass 33, count 2 2006.201.05:28:20.38#ibcon#*before return 0, iclass 33, count 2 2006.201.05:28:20.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:20.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:20.38#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.05:28:20.38#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:20.38#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:20.50#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:20.50#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:20.50#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:28:20.50#ibcon#first serial, iclass 33, count 0 2006.201.05:28:20.50#ibcon#enter sib2, iclass 33, count 0 2006.201.05:28:20.50#ibcon#flushed, iclass 33, count 0 2006.201.05:28:20.50#ibcon#about to write, iclass 33, count 0 2006.201.05:28:20.50#ibcon#wrote, iclass 33, count 0 2006.201.05:28:20.50#ibcon#about to read 3, iclass 33, count 0 2006.201.05:28:20.52#ibcon#read 3, iclass 33, count 0 2006.201.05:28:20.52#ibcon#about to read 4, iclass 33, count 0 2006.201.05:28:20.52#ibcon#read 4, iclass 33, count 0 2006.201.05:28:20.52#ibcon#about to read 5, iclass 33, count 0 2006.201.05:28:20.52#ibcon#read 5, iclass 33, count 0 2006.201.05:28:20.52#ibcon#about to read 6, iclass 33, count 0 2006.201.05:28:20.52#ibcon#read 6, iclass 33, count 0 2006.201.05:28:20.52#ibcon#end of sib2, iclass 33, count 0 2006.201.05:28:20.52#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:28:20.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:28:20.52#ibcon#[25=USB\r\n] 2006.201.05:28:20.52#ibcon#*before write, iclass 33, count 0 2006.201.05:28:20.52#ibcon#enter sib2, iclass 33, count 0 2006.201.05:28:20.52#ibcon#flushed, iclass 33, count 0 2006.201.05:28:20.52#ibcon#about to write, iclass 33, count 0 2006.201.05:28:20.52#ibcon#wrote, iclass 33, count 0 2006.201.05:28:20.52#ibcon#about to read 3, iclass 33, count 0 2006.201.05:28:20.55#ibcon#read 3, iclass 33, count 0 2006.201.05:28:20.55#ibcon#about to read 4, iclass 33, count 0 2006.201.05:28:20.55#ibcon#read 4, iclass 33, count 0 2006.201.05:28:20.55#ibcon#about to read 5, iclass 33, count 0 2006.201.05:28:20.55#ibcon#read 5, iclass 33, count 0 2006.201.05:28:20.55#ibcon#about to read 6, iclass 33, count 0 2006.201.05:28:20.55#ibcon#read 6, iclass 33, count 0 2006.201.05:28:20.55#ibcon#end of sib2, iclass 33, count 0 2006.201.05:28:20.55#ibcon#*after write, iclass 33, count 0 2006.201.05:28:20.55#ibcon#*before return 0, iclass 33, count 0 2006.201.05:28:20.55#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:20.55#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:20.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:28:20.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:28:20.55$vck44/valo=2,534.99 2006.201.05:28:20.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.05:28:20.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.05:28:20.55#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:20.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:20.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:20.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:20.55#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:28:20.55#ibcon#first serial, iclass 35, count 0 2006.201.05:28:20.55#ibcon#enter sib2, iclass 35, count 0 2006.201.05:28:20.55#ibcon#flushed, iclass 35, count 0 2006.201.05:28:20.55#ibcon#about to write, iclass 35, count 0 2006.201.05:28:20.55#ibcon#wrote, iclass 35, count 0 2006.201.05:28:20.55#ibcon#about to read 3, iclass 35, count 0 2006.201.05:28:20.57#ibcon#read 3, iclass 35, count 0 2006.201.05:28:20.57#ibcon#about to read 4, iclass 35, count 0 2006.201.05:28:20.57#ibcon#read 4, iclass 35, count 0 2006.201.05:28:20.57#ibcon#about to read 5, iclass 35, count 0 2006.201.05:28:20.57#ibcon#read 5, iclass 35, count 0 2006.201.05:28:20.57#ibcon#about to read 6, iclass 35, count 0 2006.201.05:28:20.57#ibcon#read 6, iclass 35, count 0 2006.201.05:28:20.57#ibcon#end of sib2, iclass 35, count 0 2006.201.05:28:20.57#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:28:20.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:28:20.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:28:20.57#ibcon#*before write, iclass 35, count 0 2006.201.05:28:20.57#ibcon#enter sib2, iclass 35, count 0 2006.201.05:28:20.57#ibcon#flushed, iclass 35, count 0 2006.201.05:28:20.57#ibcon#about to write, iclass 35, count 0 2006.201.05:28:20.57#ibcon#wrote, iclass 35, count 0 2006.201.05:28:20.57#ibcon#about to read 3, iclass 35, count 0 2006.201.05:28:20.61#ibcon#read 3, iclass 35, count 0 2006.201.05:28:20.61#ibcon#about to read 4, iclass 35, count 0 2006.201.05:28:20.61#ibcon#read 4, iclass 35, count 0 2006.201.05:28:20.61#ibcon#about to read 5, iclass 35, count 0 2006.201.05:28:20.61#ibcon#read 5, iclass 35, count 0 2006.201.05:28:20.61#ibcon#about to read 6, iclass 35, count 0 2006.201.05:28:20.61#ibcon#read 6, iclass 35, count 0 2006.201.05:28:20.61#ibcon#end of sib2, iclass 35, count 0 2006.201.05:28:20.61#ibcon#*after write, iclass 35, count 0 2006.201.05:28:20.61#ibcon#*before return 0, iclass 35, count 0 2006.201.05:28:20.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:20.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:20.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:28:20.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:28:20.61$vck44/va=2,7 2006.201.05:28:20.61#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.05:28:20.61#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.05:28:20.61#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:20.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:20.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:20.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:20.67#ibcon#enter wrdev, iclass 37, count 2 2006.201.05:28:20.67#ibcon#first serial, iclass 37, count 2 2006.201.05:28:20.67#ibcon#enter sib2, iclass 37, count 2 2006.201.05:28:20.67#ibcon#flushed, iclass 37, count 2 2006.201.05:28:20.67#ibcon#about to write, iclass 37, count 2 2006.201.05:28:20.67#ibcon#wrote, iclass 37, count 2 2006.201.05:28:20.67#ibcon#about to read 3, iclass 37, count 2 2006.201.05:28:20.69#ibcon#read 3, iclass 37, count 2 2006.201.05:28:20.69#ibcon#about to read 4, iclass 37, count 2 2006.201.05:28:20.69#ibcon#read 4, iclass 37, count 2 2006.201.05:28:20.69#ibcon#about to read 5, iclass 37, count 2 2006.201.05:28:20.69#ibcon#read 5, iclass 37, count 2 2006.201.05:28:20.69#ibcon#about to read 6, iclass 37, count 2 2006.201.05:28:20.69#ibcon#read 6, iclass 37, count 2 2006.201.05:28:20.69#ibcon#end of sib2, iclass 37, count 2 2006.201.05:28:20.69#ibcon#*mode == 0, iclass 37, count 2 2006.201.05:28:20.69#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.05:28:20.69#ibcon#[25=AT02-07\r\n] 2006.201.05:28:20.69#ibcon#*before write, iclass 37, count 2 2006.201.05:28:20.69#ibcon#enter sib2, iclass 37, count 2 2006.201.05:28:20.69#ibcon#flushed, iclass 37, count 2 2006.201.05:28:20.69#ibcon#about to write, iclass 37, count 2 2006.201.05:28:20.69#ibcon#wrote, iclass 37, count 2 2006.201.05:28:20.69#ibcon#about to read 3, iclass 37, count 2 2006.201.05:28:20.72#ibcon#read 3, iclass 37, count 2 2006.201.05:28:20.72#ibcon#about to read 4, iclass 37, count 2 2006.201.05:28:20.72#ibcon#read 4, iclass 37, count 2 2006.201.05:28:20.72#ibcon#about to read 5, iclass 37, count 2 2006.201.05:28:20.72#ibcon#read 5, iclass 37, count 2 2006.201.05:28:20.72#ibcon#about to read 6, iclass 37, count 2 2006.201.05:28:20.72#ibcon#read 6, iclass 37, count 2 2006.201.05:28:20.72#ibcon#end of sib2, iclass 37, count 2 2006.201.05:28:20.72#ibcon#*after write, iclass 37, count 2 2006.201.05:28:20.72#ibcon#*before return 0, iclass 37, count 2 2006.201.05:28:20.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:20.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:20.72#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.05:28:20.72#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:20.72#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:20.84#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:20.84#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:20.84#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:28:20.84#ibcon#first serial, iclass 37, count 0 2006.201.05:28:20.84#ibcon#enter sib2, iclass 37, count 0 2006.201.05:28:20.84#ibcon#flushed, iclass 37, count 0 2006.201.05:28:20.84#ibcon#about to write, iclass 37, count 0 2006.201.05:28:20.84#ibcon#wrote, iclass 37, count 0 2006.201.05:28:20.84#ibcon#about to read 3, iclass 37, count 0 2006.201.05:28:20.86#ibcon#read 3, iclass 37, count 0 2006.201.05:28:20.86#ibcon#about to read 4, iclass 37, count 0 2006.201.05:28:20.86#ibcon#read 4, iclass 37, count 0 2006.201.05:28:20.86#ibcon#about to read 5, iclass 37, count 0 2006.201.05:28:20.86#ibcon#read 5, iclass 37, count 0 2006.201.05:28:20.86#ibcon#about to read 6, iclass 37, count 0 2006.201.05:28:20.86#ibcon#read 6, iclass 37, count 0 2006.201.05:28:20.86#ibcon#end of sib2, iclass 37, count 0 2006.201.05:28:20.86#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:28:20.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:28:20.86#ibcon#[25=USB\r\n] 2006.201.05:28:20.86#ibcon#*before write, iclass 37, count 0 2006.201.05:28:20.86#ibcon#enter sib2, iclass 37, count 0 2006.201.05:28:20.86#ibcon#flushed, iclass 37, count 0 2006.201.05:28:20.86#ibcon#about to write, iclass 37, count 0 2006.201.05:28:20.86#ibcon#wrote, iclass 37, count 0 2006.201.05:28:20.86#ibcon#about to read 3, iclass 37, count 0 2006.201.05:28:20.89#ibcon#read 3, iclass 37, count 0 2006.201.05:28:20.89#ibcon#about to read 4, iclass 37, count 0 2006.201.05:28:20.89#ibcon#read 4, iclass 37, count 0 2006.201.05:28:20.89#ibcon#about to read 5, iclass 37, count 0 2006.201.05:28:20.89#ibcon#read 5, iclass 37, count 0 2006.201.05:28:20.89#ibcon#about to read 6, iclass 37, count 0 2006.201.05:28:20.89#ibcon#read 6, iclass 37, count 0 2006.201.05:28:20.89#ibcon#end of sib2, iclass 37, count 0 2006.201.05:28:20.89#ibcon#*after write, iclass 37, count 0 2006.201.05:28:20.89#ibcon#*before return 0, iclass 37, count 0 2006.201.05:28:20.89#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:20.89#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:20.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:28:20.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:28:20.89$vck44/valo=3,564.99 2006.201.05:28:20.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.05:28:20.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.05:28:20.89#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:20.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:20.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:20.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:20.89#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:28:20.89#ibcon#first serial, iclass 39, count 0 2006.201.05:28:20.89#ibcon#enter sib2, iclass 39, count 0 2006.201.05:28:20.89#ibcon#flushed, iclass 39, count 0 2006.201.05:28:20.89#ibcon#about to write, iclass 39, count 0 2006.201.05:28:20.89#ibcon#wrote, iclass 39, count 0 2006.201.05:28:20.89#ibcon#about to read 3, iclass 39, count 0 2006.201.05:28:20.91#ibcon#read 3, iclass 39, count 0 2006.201.05:28:20.91#ibcon#about to read 4, iclass 39, count 0 2006.201.05:28:20.91#ibcon#read 4, iclass 39, count 0 2006.201.05:28:20.91#ibcon#about to read 5, iclass 39, count 0 2006.201.05:28:20.91#ibcon#read 5, iclass 39, count 0 2006.201.05:28:20.91#ibcon#about to read 6, iclass 39, count 0 2006.201.05:28:20.91#ibcon#read 6, iclass 39, count 0 2006.201.05:28:20.91#ibcon#end of sib2, iclass 39, count 0 2006.201.05:28:20.91#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:28:20.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:28:20.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:28:20.91#ibcon#*before write, iclass 39, count 0 2006.201.05:28:20.91#ibcon#enter sib2, iclass 39, count 0 2006.201.05:28:20.91#ibcon#flushed, iclass 39, count 0 2006.201.05:28:20.91#ibcon#about to write, iclass 39, count 0 2006.201.05:28:20.91#ibcon#wrote, iclass 39, count 0 2006.201.05:28:20.91#ibcon#about to read 3, iclass 39, count 0 2006.201.05:28:20.95#ibcon#read 3, iclass 39, count 0 2006.201.05:28:20.95#ibcon#about to read 4, iclass 39, count 0 2006.201.05:28:20.95#ibcon#read 4, iclass 39, count 0 2006.201.05:28:20.95#ibcon#about to read 5, iclass 39, count 0 2006.201.05:28:20.95#ibcon#read 5, iclass 39, count 0 2006.201.05:28:20.95#ibcon#about to read 6, iclass 39, count 0 2006.201.05:28:20.95#ibcon#read 6, iclass 39, count 0 2006.201.05:28:20.95#ibcon#end of sib2, iclass 39, count 0 2006.201.05:28:20.95#ibcon#*after write, iclass 39, count 0 2006.201.05:28:20.95#ibcon#*before return 0, iclass 39, count 0 2006.201.05:28:20.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:20.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:20.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:28:20.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:28:20.95$vck44/va=3,8 2006.201.05:28:20.95#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.05:28:20.95#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.05:28:20.95#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:20.95#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:21.01#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:21.01#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:21.01#ibcon#enter wrdev, iclass 2, count 2 2006.201.05:28:21.01#ibcon#first serial, iclass 2, count 2 2006.201.05:28:21.01#ibcon#enter sib2, iclass 2, count 2 2006.201.05:28:21.01#ibcon#flushed, iclass 2, count 2 2006.201.05:28:21.01#ibcon#about to write, iclass 2, count 2 2006.201.05:28:21.01#ibcon#wrote, iclass 2, count 2 2006.201.05:28:21.01#ibcon#about to read 3, iclass 2, count 2 2006.201.05:28:21.03#ibcon#read 3, iclass 2, count 2 2006.201.05:28:21.03#ibcon#about to read 4, iclass 2, count 2 2006.201.05:28:21.03#ibcon#read 4, iclass 2, count 2 2006.201.05:28:21.03#ibcon#about to read 5, iclass 2, count 2 2006.201.05:28:21.03#ibcon#read 5, iclass 2, count 2 2006.201.05:28:21.03#ibcon#about to read 6, iclass 2, count 2 2006.201.05:28:21.03#ibcon#read 6, iclass 2, count 2 2006.201.05:28:21.03#ibcon#end of sib2, iclass 2, count 2 2006.201.05:28:21.03#ibcon#*mode == 0, iclass 2, count 2 2006.201.05:28:21.03#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.05:28:21.03#ibcon#[25=AT03-08\r\n] 2006.201.05:28:21.03#ibcon#*before write, iclass 2, count 2 2006.201.05:28:21.03#ibcon#enter sib2, iclass 2, count 2 2006.201.05:28:21.03#ibcon#flushed, iclass 2, count 2 2006.201.05:28:21.03#ibcon#about to write, iclass 2, count 2 2006.201.05:28:21.03#ibcon#wrote, iclass 2, count 2 2006.201.05:28:21.03#ibcon#about to read 3, iclass 2, count 2 2006.201.05:28:21.06#ibcon#read 3, iclass 2, count 2 2006.201.05:28:21.06#ibcon#about to read 4, iclass 2, count 2 2006.201.05:28:21.06#ibcon#read 4, iclass 2, count 2 2006.201.05:28:21.06#ibcon#about to read 5, iclass 2, count 2 2006.201.05:28:21.06#ibcon#read 5, iclass 2, count 2 2006.201.05:28:21.06#ibcon#about to read 6, iclass 2, count 2 2006.201.05:28:21.06#ibcon#read 6, iclass 2, count 2 2006.201.05:28:21.06#ibcon#end of sib2, iclass 2, count 2 2006.201.05:28:21.06#ibcon#*after write, iclass 2, count 2 2006.201.05:28:21.06#ibcon#*before return 0, iclass 2, count 2 2006.201.05:28:21.06#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:21.06#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:21.06#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.05:28:21.06#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:21.06#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:21.18#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:21.18#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:21.18#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:28:21.18#ibcon#first serial, iclass 2, count 0 2006.201.05:28:21.18#ibcon#enter sib2, iclass 2, count 0 2006.201.05:28:21.18#ibcon#flushed, iclass 2, count 0 2006.201.05:28:21.18#ibcon#about to write, iclass 2, count 0 2006.201.05:28:21.18#ibcon#wrote, iclass 2, count 0 2006.201.05:28:21.18#ibcon#about to read 3, iclass 2, count 0 2006.201.05:28:21.20#ibcon#read 3, iclass 2, count 0 2006.201.05:28:21.20#ibcon#about to read 4, iclass 2, count 0 2006.201.05:28:21.20#ibcon#read 4, iclass 2, count 0 2006.201.05:28:21.20#ibcon#about to read 5, iclass 2, count 0 2006.201.05:28:21.20#ibcon#read 5, iclass 2, count 0 2006.201.05:28:21.20#ibcon#about to read 6, iclass 2, count 0 2006.201.05:28:21.20#ibcon#read 6, iclass 2, count 0 2006.201.05:28:21.20#ibcon#end of sib2, iclass 2, count 0 2006.201.05:28:21.20#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:28:21.20#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:28:21.20#ibcon#[25=USB\r\n] 2006.201.05:28:21.20#ibcon#*before write, iclass 2, count 0 2006.201.05:28:21.20#ibcon#enter sib2, iclass 2, count 0 2006.201.05:28:21.20#ibcon#flushed, iclass 2, count 0 2006.201.05:28:21.20#ibcon#about to write, iclass 2, count 0 2006.201.05:28:21.20#ibcon#wrote, iclass 2, count 0 2006.201.05:28:21.20#ibcon#about to read 3, iclass 2, count 0 2006.201.05:28:21.22#abcon#<5=/05 3.2 5.1 23.21 901003.6\r\n> 2006.201.05:28:21.23#ibcon#read 3, iclass 2, count 0 2006.201.05:28:21.23#ibcon#about to read 4, iclass 2, count 0 2006.201.05:28:21.23#ibcon#read 4, iclass 2, count 0 2006.201.05:28:21.23#ibcon#about to read 5, iclass 2, count 0 2006.201.05:28:21.23#ibcon#read 5, iclass 2, count 0 2006.201.05:28:21.23#ibcon#about to read 6, iclass 2, count 0 2006.201.05:28:21.23#ibcon#read 6, iclass 2, count 0 2006.201.05:28:21.23#ibcon#end of sib2, iclass 2, count 0 2006.201.05:28:21.23#ibcon#*after write, iclass 2, count 0 2006.201.05:28:21.23#ibcon#*before return 0, iclass 2, count 0 2006.201.05:28:21.23#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:21.23#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:21.23#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:28:21.23#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:28:21.23$vck44/valo=4,624.99 2006.201.05:28:21.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.05:28:21.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.05:28:21.23#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:21.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:28:21.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:28:21.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:28:21.23#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:28:21.23#ibcon#first serial, iclass 10, count 0 2006.201.05:28:21.23#ibcon#enter sib2, iclass 10, count 0 2006.201.05:28:21.23#ibcon#flushed, iclass 10, count 0 2006.201.05:28:21.23#ibcon#about to write, iclass 10, count 0 2006.201.05:28:21.23#ibcon#wrote, iclass 10, count 0 2006.201.05:28:21.23#ibcon#about to read 3, iclass 10, count 0 2006.201.05:28:21.24#abcon#{5=INTERFACE CLEAR} 2006.201.05:28:21.25#ibcon#read 3, iclass 10, count 0 2006.201.05:28:21.25#ibcon#about to read 4, iclass 10, count 0 2006.201.05:28:21.25#ibcon#read 4, iclass 10, count 0 2006.201.05:28:21.25#ibcon#about to read 5, iclass 10, count 0 2006.201.05:28:21.25#ibcon#read 5, iclass 10, count 0 2006.201.05:28:21.25#ibcon#about to read 6, iclass 10, count 0 2006.201.05:28:21.25#ibcon#read 6, iclass 10, count 0 2006.201.05:28:21.25#ibcon#end of sib2, iclass 10, count 0 2006.201.05:28:21.25#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:28:21.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:28:21.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:28:21.25#ibcon#*before write, iclass 10, count 0 2006.201.05:28:21.25#ibcon#enter sib2, iclass 10, count 0 2006.201.05:28:21.25#ibcon#flushed, iclass 10, count 0 2006.201.05:28:21.25#ibcon#about to write, iclass 10, count 0 2006.201.05:28:21.25#ibcon#wrote, iclass 10, count 0 2006.201.05:28:21.25#ibcon#about to read 3, iclass 10, count 0 2006.201.05:28:21.29#ibcon#read 3, iclass 10, count 0 2006.201.05:28:21.29#ibcon#about to read 4, iclass 10, count 0 2006.201.05:28:21.29#ibcon#read 4, iclass 10, count 0 2006.201.05:28:21.29#ibcon#about to read 5, iclass 10, count 0 2006.201.05:28:21.29#ibcon#read 5, iclass 10, count 0 2006.201.05:28:21.29#ibcon#about to read 6, iclass 10, count 0 2006.201.05:28:21.29#ibcon#read 6, iclass 10, count 0 2006.201.05:28:21.29#ibcon#end of sib2, iclass 10, count 0 2006.201.05:28:21.29#ibcon#*after write, iclass 10, count 0 2006.201.05:28:21.29#ibcon#*before return 0, iclass 10, count 0 2006.201.05:28:21.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:28:21.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:28:21.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:28:21.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:28:21.29$vck44/va=4,7 2006.201.05:28:21.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.05:28:21.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.05:28:21.29#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:21.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:21.30#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:28:21.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:21.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:21.35#ibcon#enter wrdev, iclass 13, count 2 2006.201.05:28:21.35#ibcon#first serial, iclass 13, count 2 2006.201.05:28:21.35#ibcon#enter sib2, iclass 13, count 2 2006.201.05:28:21.35#ibcon#flushed, iclass 13, count 2 2006.201.05:28:21.35#ibcon#about to write, iclass 13, count 2 2006.201.05:28:21.35#ibcon#wrote, iclass 13, count 2 2006.201.05:28:21.35#ibcon#about to read 3, iclass 13, count 2 2006.201.05:28:21.37#ibcon#read 3, iclass 13, count 2 2006.201.05:28:21.37#ibcon#about to read 4, iclass 13, count 2 2006.201.05:28:21.37#ibcon#read 4, iclass 13, count 2 2006.201.05:28:21.37#ibcon#about to read 5, iclass 13, count 2 2006.201.05:28:21.37#ibcon#read 5, iclass 13, count 2 2006.201.05:28:21.37#ibcon#about to read 6, iclass 13, count 2 2006.201.05:28:21.37#ibcon#read 6, iclass 13, count 2 2006.201.05:28:21.37#ibcon#end of sib2, iclass 13, count 2 2006.201.05:28:21.37#ibcon#*mode == 0, iclass 13, count 2 2006.201.05:28:21.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.05:28:21.37#ibcon#[25=AT04-07\r\n] 2006.201.05:28:21.37#ibcon#*before write, iclass 13, count 2 2006.201.05:28:21.37#ibcon#enter sib2, iclass 13, count 2 2006.201.05:28:21.37#ibcon#flushed, iclass 13, count 2 2006.201.05:28:21.37#ibcon#about to write, iclass 13, count 2 2006.201.05:28:21.37#ibcon#wrote, iclass 13, count 2 2006.201.05:28:21.43#ibcon#about to read 3, iclass 13, count 2 2006.201.05:28:21.43#ibcon#read 3, iclass 13, count 2 2006.201.05:28:21.43#ibcon#about to read 4, iclass 13, count 2 2006.201.05:28:21.43#ibcon#read 4, iclass 13, count 2 2006.201.05:28:21.43#ibcon#about to read 5, iclass 13, count 2 2006.201.05:28:21.43#ibcon#read 5, iclass 13, count 2 2006.201.05:28:21.43#ibcon#about to read 6, iclass 13, count 2 2006.201.05:28:21.43#ibcon#read 6, iclass 13, count 2 2006.201.05:28:21.43#ibcon#end of sib2, iclass 13, count 2 2006.201.05:28:21.43#ibcon#*after write, iclass 13, count 2 2006.201.05:28:21.43#ibcon#*before return 0, iclass 13, count 2 2006.201.05:28:21.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:21.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:21.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.05:28:21.43#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:21.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:21.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:21.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:21.55#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:28:21.55#ibcon#first serial, iclass 13, count 0 2006.201.05:28:21.55#ibcon#enter sib2, iclass 13, count 0 2006.201.05:28:21.55#ibcon#flushed, iclass 13, count 0 2006.201.05:28:21.55#ibcon#about to write, iclass 13, count 0 2006.201.05:28:21.55#ibcon#wrote, iclass 13, count 0 2006.201.05:28:21.55#ibcon#about to read 3, iclass 13, count 0 2006.201.05:28:21.57#ibcon#read 3, iclass 13, count 0 2006.201.05:28:21.57#ibcon#about to read 4, iclass 13, count 0 2006.201.05:28:21.57#ibcon#read 4, iclass 13, count 0 2006.201.05:28:21.57#ibcon#about to read 5, iclass 13, count 0 2006.201.05:28:21.57#ibcon#read 5, iclass 13, count 0 2006.201.05:28:21.57#ibcon#about to read 6, iclass 13, count 0 2006.201.05:28:21.57#ibcon#read 6, iclass 13, count 0 2006.201.05:28:21.57#ibcon#end of sib2, iclass 13, count 0 2006.201.05:28:21.57#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:28:21.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:28:21.57#ibcon#[25=USB\r\n] 2006.201.05:28:21.57#ibcon#*before write, iclass 13, count 0 2006.201.05:28:21.57#ibcon#enter sib2, iclass 13, count 0 2006.201.05:28:21.57#ibcon#flushed, iclass 13, count 0 2006.201.05:28:21.57#ibcon#about to write, iclass 13, count 0 2006.201.05:28:21.57#ibcon#wrote, iclass 13, count 0 2006.201.05:28:21.57#ibcon#about to read 3, iclass 13, count 0 2006.201.05:28:21.60#ibcon#read 3, iclass 13, count 0 2006.201.05:28:21.60#ibcon#about to read 4, iclass 13, count 0 2006.201.05:28:21.60#ibcon#read 4, iclass 13, count 0 2006.201.05:28:21.60#ibcon#about to read 5, iclass 13, count 0 2006.201.05:28:21.60#ibcon#read 5, iclass 13, count 0 2006.201.05:28:21.60#ibcon#about to read 6, iclass 13, count 0 2006.201.05:28:21.60#ibcon#read 6, iclass 13, count 0 2006.201.05:28:21.60#ibcon#end of sib2, iclass 13, count 0 2006.201.05:28:21.60#ibcon#*after write, iclass 13, count 0 2006.201.05:28:21.60#ibcon#*before return 0, iclass 13, count 0 2006.201.05:28:21.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:21.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:21.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:28:21.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:28:21.60$vck44/valo=5,734.99 2006.201.05:28:21.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.05:28:21.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.05:28:21.60#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:21.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:21.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:21.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:21.60#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:28:21.60#ibcon#first serial, iclass 15, count 0 2006.201.05:28:21.60#ibcon#enter sib2, iclass 15, count 0 2006.201.05:28:21.60#ibcon#flushed, iclass 15, count 0 2006.201.05:28:21.60#ibcon#about to write, iclass 15, count 0 2006.201.05:28:21.60#ibcon#wrote, iclass 15, count 0 2006.201.05:28:21.60#ibcon#about to read 3, iclass 15, count 0 2006.201.05:28:21.62#ibcon#read 3, iclass 15, count 0 2006.201.05:28:21.62#ibcon#about to read 4, iclass 15, count 0 2006.201.05:28:21.62#ibcon#read 4, iclass 15, count 0 2006.201.05:28:21.62#ibcon#about to read 5, iclass 15, count 0 2006.201.05:28:21.62#ibcon#read 5, iclass 15, count 0 2006.201.05:28:21.62#ibcon#about to read 6, iclass 15, count 0 2006.201.05:28:21.62#ibcon#read 6, iclass 15, count 0 2006.201.05:28:21.62#ibcon#end of sib2, iclass 15, count 0 2006.201.05:28:21.62#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:28:21.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:28:21.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:28:21.62#ibcon#*before write, iclass 15, count 0 2006.201.05:28:21.62#ibcon#enter sib2, iclass 15, count 0 2006.201.05:28:21.62#ibcon#flushed, iclass 15, count 0 2006.201.05:28:21.62#ibcon#about to write, iclass 15, count 0 2006.201.05:28:21.62#ibcon#wrote, iclass 15, count 0 2006.201.05:28:21.62#ibcon#about to read 3, iclass 15, count 0 2006.201.05:28:21.66#ibcon#read 3, iclass 15, count 0 2006.201.05:28:21.66#ibcon#about to read 4, iclass 15, count 0 2006.201.05:28:21.66#ibcon#read 4, iclass 15, count 0 2006.201.05:28:21.66#ibcon#about to read 5, iclass 15, count 0 2006.201.05:28:21.66#ibcon#read 5, iclass 15, count 0 2006.201.05:28:21.66#ibcon#about to read 6, iclass 15, count 0 2006.201.05:28:21.66#ibcon#read 6, iclass 15, count 0 2006.201.05:28:21.66#ibcon#end of sib2, iclass 15, count 0 2006.201.05:28:21.66#ibcon#*after write, iclass 15, count 0 2006.201.05:28:21.66#ibcon#*before return 0, iclass 15, count 0 2006.201.05:28:21.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:21.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:21.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:28:21.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:28:21.66$vck44/va=5,4 2006.201.05:28:21.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.05:28:21.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.05:28:21.66#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:21.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:21.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:21.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:21.72#ibcon#enter wrdev, iclass 17, count 2 2006.201.05:28:21.72#ibcon#first serial, iclass 17, count 2 2006.201.05:28:21.72#ibcon#enter sib2, iclass 17, count 2 2006.201.05:28:21.72#ibcon#flushed, iclass 17, count 2 2006.201.05:28:21.72#ibcon#about to write, iclass 17, count 2 2006.201.05:28:21.72#ibcon#wrote, iclass 17, count 2 2006.201.05:28:21.72#ibcon#about to read 3, iclass 17, count 2 2006.201.05:28:21.74#ibcon#read 3, iclass 17, count 2 2006.201.05:28:21.74#ibcon#about to read 4, iclass 17, count 2 2006.201.05:28:21.74#ibcon#read 4, iclass 17, count 2 2006.201.05:28:21.74#ibcon#about to read 5, iclass 17, count 2 2006.201.05:28:21.74#ibcon#read 5, iclass 17, count 2 2006.201.05:28:21.74#ibcon#about to read 6, iclass 17, count 2 2006.201.05:28:21.74#ibcon#read 6, iclass 17, count 2 2006.201.05:28:21.74#ibcon#end of sib2, iclass 17, count 2 2006.201.05:28:21.74#ibcon#*mode == 0, iclass 17, count 2 2006.201.05:28:21.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.05:28:21.74#ibcon#[25=AT05-04\r\n] 2006.201.05:28:21.74#ibcon#*before write, iclass 17, count 2 2006.201.05:28:21.74#ibcon#enter sib2, iclass 17, count 2 2006.201.05:28:21.74#ibcon#flushed, iclass 17, count 2 2006.201.05:28:21.74#ibcon#about to write, iclass 17, count 2 2006.201.05:28:21.74#ibcon#wrote, iclass 17, count 2 2006.201.05:28:21.74#ibcon#about to read 3, iclass 17, count 2 2006.201.05:28:21.77#ibcon#read 3, iclass 17, count 2 2006.201.05:28:21.77#ibcon#about to read 4, iclass 17, count 2 2006.201.05:28:21.77#ibcon#read 4, iclass 17, count 2 2006.201.05:28:21.77#ibcon#about to read 5, iclass 17, count 2 2006.201.05:28:21.77#ibcon#read 5, iclass 17, count 2 2006.201.05:28:21.77#ibcon#about to read 6, iclass 17, count 2 2006.201.05:28:21.77#ibcon#read 6, iclass 17, count 2 2006.201.05:28:21.77#ibcon#end of sib2, iclass 17, count 2 2006.201.05:28:21.77#ibcon#*after write, iclass 17, count 2 2006.201.05:28:21.77#ibcon#*before return 0, iclass 17, count 2 2006.201.05:28:21.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:21.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:21.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.05:28:21.77#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:21.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:21.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:21.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:21.89#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:28:21.89#ibcon#first serial, iclass 17, count 0 2006.201.05:28:21.89#ibcon#enter sib2, iclass 17, count 0 2006.201.05:28:21.89#ibcon#flushed, iclass 17, count 0 2006.201.05:28:21.89#ibcon#about to write, iclass 17, count 0 2006.201.05:28:21.89#ibcon#wrote, iclass 17, count 0 2006.201.05:28:21.89#ibcon#about to read 3, iclass 17, count 0 2006.201.05:28:21.91#ibcon#read 3, iclass 17, count 0 2006.201.05:28:21.91#ibcon#about to read 4, iclass 17, count 0 2006.201.05:28:21.91#ibcon#read 4, iclass 17, count 0 2006.201.05:28:21.91#ibcon#about to read 5, iclass 17, count 0 2006.201.05:28:21.91#ibcon#read 5, iclass 17, count 0 2006.201.05:28:21.91#ibcon#about to read 6, iclass 17, count 0 2006.201.05:28:21.91#ibcon#read 6, iclass 17, count 0 2006.201.05:28:21.91#ibcon#end of sib2, iclass 17, count 0 2006.201.05:28:21.91#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:28:21.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:28:21.91#ibcon#[25=USB\r\n] 2006.201.05:28:21.91#ibcon#*before write, iclass 17, count 0 2006.201.05:28:21.91#ibcon#enter sib2, iclass 17, count 0 2006.201.05:28:21.91#ibcon#flushed, iclass 17, count 0 2006.201.05:28:21.91#ibcon#about to write, iclass 17, count 0 2006.201.05:28:21.91#ibcon#wrote, iclass 17, count 0 2006.201.05:28:21.91#ibcon#about to read 3, iclass 17, count 0 2006.201.05:28:21.94#ibcon#read 3, iclass 17, count 0 2006.201.05:28:21.94#ibcon#about to read 4, iclass 17, count 0 2006.201.05:28:21.94#ibcon#read 4, iclass 17, count 0 2006.201.05:28:21.94#ibcon#about to read 5, iclass 17, count 0 2006.201.05:28:21.94#ibcon#read 5, iclass 17, count 0 2006.201.05:28:21.94#ibcon#about to read 6, iclass 17, count 0 2006.201.05:28:21.94#ibcon#read 6, iclass 17, count 0 2006.201.05:28:21.94#ibcon#end of sib2, iclass 17, count 0 2006.201.05:28:21.94#ibcon#*after write, iclass 17, count 0 2006.201.05:28:21.94#ibcon#*before return 0, iclass 17, count 0 2006.201.05:28:21.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:21.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:21.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:28:21.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:28:21.94$vck44/valo=6,814.99 2006.201.05:28:21.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.05:28:21.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.05:28:21.94#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:21.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:21.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:21.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:21.94#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:28:21.94#ibcon#first serial, iclass 19, count 0 2006.201.05:28:21.94#ibcon#enter sib2, iclass 19, count 0 2006.201.05:28:21.94#ibcon#flushed, iclass 19, count 0 2006.201.05:28:21.94#ibcon#about to write, iclass 19, count 0 2006.201.05:28:21.94#ibcon#wrote, iclass 19, count 0 2006.201.05:28:21.94#ibcon#about to read 3, iclass 19, count 0 2006.201.05:28:21.96#ibcon#read 3, iclass 19, count 0 2006.201.05:28:21.96#ibcon#about to read 4, iclass 19, count 0 2006.201.05:28:21.96#ibcon#read 4, iclass 19, count 0 2006.201.05:28:21.96#ibcon#about to read 5, iclass 19, count 0 2006.201.05:28:21.96#ibcon#read 5, iclass 19, count 0 2006.201.05:28:21.96#ibcon#about to read 6, iclass 19, count 0 2006.201.05:28:21.96#ibcon#read 6, iclass 19, count 0 2006.201.05:28:21.96#ibcon#end of sib2, iclass 19, count 0 2006.201.05:28:21.96#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:28:21.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:28:21.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:28:21.96#ibcon#*before write, iclass 19, count 0 2006.201.05:28:21.96#ibcon#enter sib2, iclass 19, count 0 2006.201.05:28:21.96#ibcon#flushed, iclass 19, count 0 2006.201.05:28:21.96#ibcon#about to write, iclass 19, count 0 2006.201.05:28:21.96#ibcon#wrote, iclass 19, count 0 2006.201.05:28:21.96#ibcon#about to read 3, iclass 19, count 0 2006.201.05:28:22.00#ibcon#read 3, iclass 19, count 0 2006.201.05:28:22.00#ibcon#about to read 4, iclass 19, count 0 2006.201.05:28:22.00#ibcon#read 4, iclass 19, count 0 2006.201.05:28:22.00#ibcon#about to read 5, iclass 19, count 0 2006.201.05:28:22.00#ibcon#read 5, iclass 19, count 0 2006.201.05:28:22.00#ibcon#about to read 6, iclass 19, count 0 2006.201.05:28:22.00#ibcon#read 6, iclass 19, count 0 2006.201.05:28:22.00#ibcon#end of sib2, iclass 19, count 0 2006.201.05:28:22.00#ibcon#*after write, iclass 19, count 0 2006.201.05:28:22.00#ibcon#*before return 0, iclass 19, count 0 2006.201.05:28:22.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:22.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:22.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:28:22.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:28:22.00$vck44/va=6,5 2006.201.05:28:22.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.05:28:22.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.05:28:22.00#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:22.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:22.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:22.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:22.06#ibcon#enter wrdev, iclass 21, count 2 2006.201.05:28:22.06#ibcon#first serial, iclass 21, count 2 2006.201.05:28:22.06#ibcon#enter sib2, iclass 21, count 2 2006.201.05:28:22.06#ibcon#flushed, iclass 21, count 2 2006.201.05:28:22.06#ibcon#about to write, iclass 21, count 2 2006.201.05:28:22.06#ibcon#wrote, iclass 21, count 2 2006.201.05:28:22.06#ibcon#about to read 3, iclass 21, count 2 2006.201.05:28:22.08#ibcon#read 3, iclass 21, count 2 2006.201.05:28:22.08#ibcon#about to read 4, iclass 21, count 2 2006.201.05:28:22.08#ibcon#read 4, iclass 21, count 2 2006.201.05:28:22.08#ibcon#about to read 5, iclass 21, count 2 2006.201.05:28:22.08#ibcon#read 5, iclass 21, count 2 2006.201.05:28:22.08#ibcon#about to read 6, iclass 21, count 2 2006.201.05:28:22.08#ibcon#read 6, iclass 21, count 2 2006.201.05:28:22.08#ibcon#end of sib2, iclass 21, count 2 2006.201.05:28:22.08#ibcon#*mode == 0, iclass 21, count 2 2006.201.05:28:22.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.05:28:22.08#ibcon#[25=AT06-05\r\n] 2006.201.05:28:22.08#ibcon#*before write, iclass 21, count 2 2006.201.05:28:22.08#ibcon#enter sib2, iclass 21, count 2 2006.201.05:28:22.08#ibcon#flushed, iclass 21, count 2 2006.201.05:28:22.08#ibcon#about to write, iclass 21, count 2 2006.201.05:28:22.08#ibcon#wrote, iclass 21, count 2 2006.201.05:28:22.08#ibcon#about to read 3, iclass 21, count 2 2006.201.05:28:22.11#ibcon#read 3, iclass 21, count 2 2006.201.05:28:22.11#ibcon#about to read 4, iclass 21, count 2 2006.201.05:28:22.11#ibcon#read 4, iclass 21, count 2 2006.201.05:28:22.11#ibcon#about to read 5, iclass 21, count 2 2006.201.05:28:22.11#ibcon#read 5, iclass 21, count 2 2006.201.05:28:22.11#ibcon#about to read 6, iclass 21, count 2 2006.201.05:28:22.11#ibcon#read 6, iclass 21, count 2 2006.201.05:28:22.11#ibcon#end of sib2, iclass 21, count 2 2006.201.05:28:22.11#ibcon#*after write, iclass 21, count 2 2006.201.05:28:22.11#ibcon#*before return 0, iclass 21, count 2 2006.201.05:28:22.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:22.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:22.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.05:28:22.11#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:22.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:22.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:22.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:22.23#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:28:22.23#ibcon#first serial, iclass 21, count 0 2006.201.05:28:22.23#ibcon#enter sib2, iclass 21, count 0 2006.201.05:28:22.23#ibcon#flushed, iclass 21, count 0 2006.201.05:28:22.23#ibcon#about to write, iclass 21, count 0 2006.201.05:28:22.23#ibcon#wrote, iclass 21, count 0 2006.201.05:28:22.23#ibcon#about to read 3, iclass 21, count 0 2006.201.05:28:22.25#ibcon#read 3, iclass 21, count 0 2006.201.05:28:22.25#ibcon#about to read 4, iclass 21, count 0 2006.201.05:28:22.25#ibcon#read 4, iclass 21, count 0 2006.201.05:28:22.25#ibcon#about to read 5, iclass 21, count 0 2006.201.05:28:22.25#ibcon#read 5, iclass 21, count 0 2006.201.05:28:22.25#ibcon#about to read 6, iclass 21, count 0 2006.201.05:28:22.25#ibcon#read 6, iclass 21, count 0 2006.201.05:28:22.25#ibcon#end of sib2, iclass 21, count 0 2006.201.05:28:22.25#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:28:22.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:28:22.25#ibcon#[25=USB\r\n] 2006.201.05:28:22.25#ibcon#*before write, iclass 21, count 0 2006.201.05:28:22.25#ibcon#enter sib2, iclass 21, count 0 2006.201.05:28:22.25#ibcon#flushed, iclass 21, count 0 2006.201.05:28:22.25#ibcon#about to write, iclass 21, count 0 2006.201.05:28:22.25#ibcon#wrote, iclass 21, count 0 2006.201.05:28:22.25#ibcon#about to read 3, iclass 21, count 0 2006.201.05:28:22.28#ibcon#read 3, iclass 21, count 0 2006.201.05:28:22.28#ibcon#about to read 4, iclass 21, count 0 2006.201.05:28:22.28#ibcon#read 4, iclass 21, count 0 2006.201.05:28:22.28#ibcon#about to read 5, iclass 21, count 0 2006.201.05:28:22.28#ibcon#read 5, iclass 21, count 0 2006.201.05:28:22.28#ibcon#about to read 6, iclass 21, count 0 2006.201.05:28:22.28#ibcon#read 6, iclass 21, count 0 2006.201.05:28:22.28#ibcon#end of sib2, iclass 21, count 0 2006.201.05:28:22.28#ibcon#*after write, iclass 21, count 0 2006.201.05:28:22.28#ibcon#*before return 0, iclass 21, count 0 2006.201.05:28:22.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:22.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:22.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:28:22.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:28:22.28$vck44/valo=7,864.99 2006.201.05:28:22.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.05:28:22.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.05:28:22.28#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:22.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:22.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:22.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:22.28#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:28:22.28#ibcon#first serial, iclass 23, count 0 2006.201.05:28:22.28#ibcon#enter sib2, iclass 23, count 0 2006.201.05:28:22.28#ibcon#flushed, iclass 23, count 0 2006.201.05:28:22.28#ibcon#about to write, iclass 23, count 0 2006.201.05:28:22.28#ibcon#wrote, iclass 23, count 0 2006.201.05:28:22.28#ibcon#about to read 3, iclass 23, count 0 2006.201.05:28:22.30#ibcon#read 3, iclass 23, count 0 2006.201.05:28:22.30#ibcon#about to read 4, iclass 23, count 0 2006.201.05:28:22.30#ibcon#read 4, iclass 23, count 0 2006.201.05:28:22.30#ibcon#about to read 5, iclass 23, count 0 2006.201.05:28:22.30#ibcon#read 5, iclass 23, count 0 2006.201.05:28:22.30#ibcon#about to read 6, iclass 23, count 0 2006.201.05:28:22.30#ibcon#read 6, iclass 23, count 0 2006.201.05:28:22.30#ibcon#end of sib2, iclass 23, count 0 2006.201.05:28:22.30#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:28:22.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:28:22.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:28:22.30#ibcon#*before write, iclass 23, count 0 2006.201.05:28:22.30#ibcon#enter sib2, iclass 23, count 0 2006.201.05:28:22.30#ibcon#flushed, iclass 23, count 0 2006.201.05:28:22.30#ibcon#about to write, iclass 23, count 0 2006.201.05:28:22.30#ibcon#wrote, iclass 23, count 0 2006.201.05:28:22.30#ibcon#about to read 3, iclass 23, count 0 2006.201.05:28:22.34#ibcon#read 3, iclass 23, count 0 2006.201.05:28:22.34#ibcon#about to read 4, iclass 23, count 0 2006.201.05:28:22.34#ibcon#read 4, iclass 23, count 0 2006.201.05:28:22.34#ibcon#about to read 5, iclass 23, count 0 2006.201.05:28:22.34#ibcon#read 5, iclass 23, count 0 2006.201.05:28:22.34#ibcon#about to read 6, iclass 23, count 0 2006.201.05:28:22.34#ibcon#read 6, iclass 23, count 0 2006.201.05:28:22.34#ibcon#end of sib2, iclass 23, count 0 2006.201.05:28:22.34#ibcon#*after write, iclass 23, count 0 2006.201.05:28:22.34#ibcon#*before return 0, iclass 23, count 0 2006.201.05:28:22.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:22.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:22.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:28:22.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:28:22.34$vck44/va=7,5 2006.201.05:28:22.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.05:28:22.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.05:28:22.34#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:22.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:22.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:22.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:22.40#ibcon#enter wrdev, iclass 25, count 2 2006.201.05:28:22.40#ibcon#first serial, iclass 25, count 2 2006.201.05:28:22.40#ibcon#enter sib2, iclass 25, count 2 2006.201.05:28:22.40#ibcon#flushed, iclass 25, count 2 2006.201.05:28:22.40#ibcon#about to write, iclass 25, count 2 2006.201.05:28:22.40#ibcon#wrote, iclass 25, count 2 2006.201.05:28:22.40#ibcon#about to read 3, iclass 25, count 2 2006.201.05:28:22.42#ibcon#read 3, iclass 25, count 2 2006.201.05:28:22.42#ibcon#about to read 4, iclass 25, count 2 2006.201.05:28:22.42#ibcon#read 4, iclass 25, count 2 2006.201.05:28:22.42#ibcon#about to read 5, iclass 25, count 2 2006.201.05:28:22.42#ibcon#read 5, iclass 25, count 2 2006.201.05:28:22.42#ibcon#about to read 6, iclass 25, count 2 2006.201.05:28:22.42#ibcon#read 6, iclass 25, count 2 2006.201.05:28:22.42#ibcon#end of sib2, iclass 25, count 2 2006.201.05:28:22.42#ibcon#*mode == 0, iclass 25, count 2 2006.201.05:28:22.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.05:28:22.42#ibcon#[25=AT07-05\r\n] 2006.201.05:28:22.42#ibcon#*before write, iclass 25, count 2 2006.201.05:28:22.42#ibcon#enter sib2, iclass 25, count 2 2006.201.05:28:22.42#ibcon#flushed, iclass 25, count 2 2006.201.05:28:22.42#ibcon#about to write, iclass 25, count 2 2006.201.05:28:22.48#ibcon#wrote, iclass 25, count 2 2006.201.05:28:22.48#ibcon#about to read 3, iclass 25, count 2 2006.201.05:28:22.51#ibcon#read 3, iclass 25, count 2 2006.201.05:28:22.51#ibcon#about to read 4, iclass 25, count 2 2006.201.05:28:22.51#ibcon#read 4, iclass 25, count 2 2006.201.05:28:22.51#ibcon#about to read 5, iclass 25, count 2 2006.201.05:28:22.51#ibcon#read 5, iclass 25, count 2 2006.201.05:28:22.51#ibcon#about to read 6, iclass 25, count 2 2006.201.05:28:22.51#ibcon#read 6, iclass 25, count 2 2006.201.05:28:22.51#ibcon#end of sib2, iclass 25, count 2 2006.201.05:28:22.51#ibcon#*after write, iclass 25, count 2 2006.201.05:28:22.51#ibcon#*before return 0, iclass 25, count 2 2006.201.05:28:22.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:22.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:22.51#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.05:28:22.51#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:22.51#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:22.63#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:22.63#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:22.63#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:28:22.63#ibcon#first serial, iclass 25, count 0 2006.201.05:28:22.63#ibcon#enter sib2, iclass 25, count 0 2006.201.05:28:22.63#ibcon#flushed, iclass 25, count 0 2006.201.05:28:22.63#ibcon#about to write, iclass 25, count 0 2006.201.05:28:22.63#ibcon#wrote, iclass 25, count 0 2006.201.05:28:22.63#ibcon#about to read 3, iclass 25, count 0 2006.201.05:28:22.65#ibcon#read 3, iclass 25, count 0 2006.201.05:28:22.65#ibcon#about to read 4, iclass 25, count 0 2006.201.05:28:22.65#ibcon#read 4, iclass 25, count 0 2006.201.05:28:22.65#ibcon#about to read 5, iclass 25, count 0 2006.201.05:28:22.65#ibcon#read 5, iclass 25, count 0 2006.201.05:28:22.65#ibcon#about to read 6, iclass 25, count 0 2006.201.05:28:22.65#ibcon#read 6, iclass 25, count 0 2006.201.05:28:22.65#ibcon#end of sib2, iclass 25, count 0 2006.201.05:28:22.65#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:28:22.65#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:28:22.65#ibcon#[25=USB\r\n] 2006.201.05:28:22.65#ibcon#*before write, iclass 25, count 0 2006.201.05:28:22.65#ibcon#enter sib2, iclass 25, count 0 2006.201.05:28:22.65#ibcon#flushed, iclass 25, count 0 2006.201.05:28:22.65#ibcon#about to write, iclass 25, count 0 2006.201.05:28:22.65#ibcon#wrote, iclass 25, count 0 2006.201.05:28:22.65#ibcon#about to read 3, iclass 25, count 0 2006.201.05:28:22.68#ibcon#read 3, iclass 25, count 0 2006.201.05:28:22.68#ibcon#about to read 4, iclass 25, count 0 2006.201.05:28:22.68#ibcon#read 4, iclass 25, count 0 2006.201.05:28:22.68#ibcon#about to read 5, iclass 25, count 0 2006.201.05:28:22.68#ibcon#read 5, iclass 25, count 0 2006.201.05:28:22.68#ibcon#about to read 6, iclass 25, count 0 2006.201.05:28:22.68#ibcon#read 6, iclass 25, count 0 2006.201.05:28:22.68#ibcon#end of sib2, iclass 25, count 0 2006.201.05:28:22.68#ibcon#*after write, iclass 25, count 0 2006.201.05:28:22.68#ibcon#*before return 0, iclass 25, count 0 2006.201.05:28:22.68#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:22.68#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:22.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:28:22.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:28:22.68$vck44/valo=8,884.99 2006.201.05:28:22.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.05:28:22.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.05:28:22.68#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:22.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:22.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:22.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:22.68#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:28:22.68#ibcon#first serial, iclass 27, count 0 2006.201.05:28:22.68#ibcon#enter sib2, iclass 27, count 0 2006.201.05:28:22.68#ibcon#flushed, iclass 27, count 0 2006.201.05:28:22.68#ibcon#about to write, iclass 27, count 0 2006.201.05:28:22.68#ibcon#wrote, iclass 27, count 0 2006.201.05:28:22.68#ibcon#about to read 3, iclass 27, count 0 2006.201.05:28:22.70#ibcon#read 3, iclass 27, count 0 2006.201.05:28:22.70#ibcon#about to read 4, iclass 27, count 0 2006.201.05:28:22.70#ibcon#read 4, iclass 27, count 0 2006.201.05:28:22.70#ibcon#about to read 5, iclass 27, count 0 2006.201.05:28:22.70#ibcon#read 5, iclass 27, count 0 2006.201.05:28:22.70#ibcon#about to read 6, iclass 27, count 0 2006.201.05:28:22.70#ibcon#read 6, iclass 27, count 0 2006.201.05:28:22.70#ibcon#end of sib2, iclass 27, count 0 2006.201.05:28:22.70#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:28:22.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:28:22.70#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:28:22.70#ibcon#*before write, iclass 27, count 0 2006.201.05:28:22.70#ibcon#enter sib2, iclass 27, count 0 2006.201.05:28:22.70#ibcon#flushed, iclass 27, count 0 2006.201.05:28:22.70#ibcon#about to write, iclass 27, count 0 2006.201.05:28:22.70#ibcon#wrote, iclass 27, count 0 2006.201.05:28:22.70#ibcon#about to read 3, iclass 27, count 0 2006.201.05:28:22.74#ibcon#read 3, iclass 27, count 0 2006.201.05:28:22.74#ibcon#about to read 4, iclass 27, count 0 2006.201.05:28:22.74#ibcon#read 4, iclass 27, count 0 2006.201.05:28:22.74#ibcon#about to read 5, iclass 27, count 0 2006.201.05:28:22.74#ibcon#read 5, iclass 27, count 0 2006.201.05:28:22.74#ibcon#about to read 6, iclass 27, count 0 2006.201.05:28:22.74#ibcon#read 6, iclass 27, count 0 2006.201.05:28:22.74#ibcon#end of sib2, iclass 27, count 0 2006.201.05:28:22.74#ibcon#*after write, iclass 27, count 0 2006.201.05:28:22.74#ibcon#*before return 0, iclass 27, count 0 2006.201.05:28:22.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:22.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:22.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:28:22.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:28:22.74$vck44/va=8,4 2006.201.05:28:22.74#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.05:28:22.74#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.05:28:22.74#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:22.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:28:22.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:28:22.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:28:22.80#ibcon#enter wrdev, iclass 29, count 2 2006.201.05:28:22.80#ibcon#first serial, iclass 29, count 2 2006.201.05:28:22.80#ibcon#enter sib2, iclass 29, count 2 2006.201.05:28:22.80#ibcon#flushed, iclass 29, count 2 2006.201.05:28:22.80#ibcon#about to write, iclass 29, count 2 2006.201.05:28:22.80#ibcon#wrote, iclass 29, count 2 2006.201.05:28:22.80#ibcon#about to read 3, iclass 29, count 2 2006.201.05:28:22.82#ibcon#read 3, iclass 29, count 2 2006.201.05:28:22.82#ibcon#about to read 4, iclass 29, count 2 2006.201.05:28:22.82#ibcon#read 4, iclass 29, count 2 2006.201.05:28:22.82#ibcon#about to read 5, iclass 29, count 2 2006.201.05:28:22.82#ibcon#read 5, iclass 29, count 2 2006.201.05:28:22.82#ibcon#about to read 6, iclass 29, count 2 2006.201.05:28:22.82#ibcon#read 6, iclass 29, count 2 2006.201.05:28:22.82#ibcon#end of sib2, iclass 29, count 2 2006.201.05:28:22.82#ibcon#*mode == 0, iclass 29, count 2 2006.201.05:28:22.82#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.05:28:22.82#ibcon#[25=AT08-04\r\n] 2006.201.05:28:22.82#ibcon#*before write, iclass 29, count 2 2006.201.05:28:22.82#ibcon#enter sib2, iclass 29, count 2 2006.201.05:28:22.82#ibcon#flushed, iclass 29, count 2 2006.201.05:28:22.82#ibcon#about to write, iclass 29, count 2 2006.201.05:28:22.82#ibcon#wrote, iclass 29, count 2 2006.201.05:28:22.82#ibcon#about to read 3, iclass 29, count 2 2006.201.05:28:22.85#ibcon#read 3, iclass 29, count 2 2006.201.05:28:22.85#ibcon#about to read 4, iclass 29, count 2 2006.201.05:28:22.85#ibcon#read 4, iclass 29, count 2 2006.201.05:28:22.85#ibcon#about to read 5, iclass 29, count 2 2006.201.05:28:22.85#ibcon#read 5, iclass 29, count 2 2006.201.05:28:22.85#ibcon#about to read 6, iclass 29, count 2 2006.201.05:28:22.85#ibcon#read 6, iclass 29, count 2 2006.201.05:28:22.85#ibcon#end of sib2, iclass 29, count 2 2006.201.05:28:22.85#ibcon#*after write, iclass 29, count 2 2006.201.05:28:22.85#ibcon#*before return 0, iclass 29, count 2 2006.201.05:28:22.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:28:22.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:28:22.85#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.05:28:22.85#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:22.85#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:28:22.97#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:28:22.97#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:28:22.97#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:28:22.97#ibcon#first serial, iclass 29, count 0 2006.201.05:28:22.97#ibcon#enter sib2, iclass 29, count 0 2006.201.05:28:22.97#ibcon#flushed, iclass 29, count 0 2006.201.05:28:22.97#ibcon#about to write, iclass 29, count 0 2006.201.05:28:22.97#ibcon#wrote, iclass 29, count 0 2006.201.05:28:22.97#ibcon#about to read 3, iclass 29, count 0 2006.201.05:28:22.99#ibcon#read 3, iclass 29, count 0 2006.201.05:28:22.99#ibcon#about to read 4, iclass 29, count 0 2006.201.05:28:22.99#ibcon#read 4, iclass 29, count 0 2006.201.05:28:22.99#ibcon#about to read 5, iclass 29, count 0 2006.201.05:28:22.99#ibcon#read 5, iclass 29, count 0 2006.201.05:28:22.99#ibcon#about to read 6, iclass 29, count 0 2006.201.05:28:22.99#ibcon#read 6, iclass 29, count 0 2006.201.05:28:22.99#ibcon#end of sib2, iclass 29, count 0 2006.201.05:28:22.99#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:28:22.99#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:28:22.99#ibcon#[25=USB\r\n] 2006.201.05:28:22.99#ibcon#*before write, iclass 29, count 0 2006.201.05:28:22.99#ibcon#enter sib2, iclass 29, count 0 2006.201.05:28:22.99#ibcon#flushed, iclass 29, count 0 2006.201.05:28:22.99#ibcon#about to write, iclass 29, count 0 2006.201.05:28:22.99#ibcon#wrote, iclass 29, count 0 2006.201.05:28:22.99#ibcon#about to read 3, iclass 29, count 0 2006.201.05:28:23.02#ibcon#read 3, iclass 29, count 0 2006.201.05:28:23.02#ibcon#about to read 4, iclass 29, count 0 2006.201.05:28:23.02#ibcon#read 4, iclass 29, count 0 2006.201.05:28:23.02#ibcon#about to read 5, iclass 29, count 0 2006.201.05:28:23.02#ibcon#read 5, iclass 29, count 0 2006.201.05:28:23.02#ibcon#about to read 6, iclass 29, count 0 2006.201.05:28:23.02#ibcon#read 6, iclass 29, count 0 2006.201.05:28:23.02#ibcon#end of sib2, iclass 29, count 0 2006.201.05:28:23.02#ibcon#*after write, iclass 29, count 0 2006.201.05:28:23.02#ibcon#*before return 0, iclass 29, count 0 2006.201.05:28:23.02#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:28:23.02#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:28:23.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:28:23.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:28:23.02$vck44/vblo=1,629.99 2006.201.05:28:23.02#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.05:28:23.02#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.05:28:23.02#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:23.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:23.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:23.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:23.02#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:28:23.02#ibcon#first serial, iclass 31, count 0 2006.201.05:28:23.02#ibcon#enter sib2, iclass 31, count 0 2006.201.05:28:23.02#ibcon#flushed, iclass 31, count 0 2006.201.05:28:23.02#ibcon#about to write, iclass 31, count 0 2006.201.05:28:23.02#ibcon#wrote, iclass 31, count 0 2006.201.05:28:23.02#ibcon#about to read 3, iclass 31, count 0 2006.201.05:28:23.04#ibcon#read 3, iclass 31, count 0 2006.201.05:28:23.04#ibcon#about to read 4, iclass 31, count 0 2006.201.05:28:23.04#ibcon#read 4, iclass 31, count 0 2006.201.05:28:23.04#ibcon#about to read 5, iclass 31, count 0 2006.201.05:28:23.04#ibcon#read 5, iclass 31, count 0 2006.201.05:28:23.04#ibcon#about to read 6, iclass 31, count 0 2006.201.05:28:23.04#ibcon#read 6, iclass 31, count 0 2006.201.05:28:23.04#ibcon#end of sib2, iclass 31, count 0 2006.201.05:28:23.04#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:28:23.04#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:28:23.04#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:28:23.04#ibcon#*before write, iclass 31, count 0 2006.201.05:28:23.04#ibcon#enter sib2, iclass 31, count 0 2006.201.05:28:23.04#ibcon#flushed, iclass 31, count 0 2006.201.05:28:23.04#ibcon#about to write, iclass 31, count 0 2006.201.05:28:23.04#ibcon#wrote, iclass 31, count 0 2006.201.05:28:23.04#ibcon#about to read 3, iclass 31, count 0 2006.201.05:28:23.08#ibcon#read 3, iclass 31, count 0 2006.201.05:28:23.08#ibcon#about to read 4, iclass 31, count 0 2006.201.05:28:23.08#ibcon#read 4, iclass 31, count 0 2006.201.05:28:23.08#ibcon#about to read 5, iclass 31, count 0 2006.201.05:28:23.08#ibcon#read 5, iclass 31, count 0 2006.201.05:28:23.08#ibcon#about to read 6, iclass 31, count 0 2006.201.05:28:23.08#ibcon#read 6, iclass 31, count 0 2006.201.05:28:23.08#ibcon#end of sib2, iclass 31, count 0 2006.201.05:28:23.08#ibcon#*after write, iclass 31, count 0 2006.201.05:28:23.08#ibcon#*before return 0, iclass 31, count 0 2006.201.05:28:23.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:23.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:28:23.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:28:23.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:28:23.08$vck44/vb=1,4 2006.201.05:28:23.08#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.05:28:23.08#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.05:28:23.08#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:23.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:23.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:23.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:23.08#ibcon#enter wrdev, iclass 33, count 2 2006.201.05:28:23.08#ibcon#first serial, iclass 33, count 2 2006.201.05:28:23.08#ibcon#enter sib2, iclass 33, count 2 2006.201.05:28:23.08#ibcon#flushed, iclass 33, count 2 2006.201.05:28:23.08#ibcon#about to write, iclass 33, count 2 2006.201.05:28:23.08#ibcon#wrote, iclass 33, count 2 2006.201.05:28:23.08#ibcon#about to read 3, iclass 33, count 2 2006.201.05:28:23.10#ibcon#read 3, iclass 33, count 2 2006.201.05:28:23.10#ibcon#about to read 4, iclass 33, count 2 2006.201.05:28:23.10#ibcon#read 4, iclass 33, count 2 2006.201.05:28:23.10#ibcon#about to read 5, iclass 33, count 2 2006.201.05:28:23.10#ibcon#read 5, iclass 33, count 2 2006.201.05:28:23.10#ibcon#about to read 6, iclass 33, count 2 2006.201.05:28:23.10#ibcon#read 6, iclass 33, count 2 2006.201.05:28:23.10#ibcon#end of sib2, iclass 33, count 2 2006.201.05:28:23.10#ibcon#*mode == 0, iclass 33, count 2 2006.201.05:28:23.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.05:28:23.10#ibcon#[27=AT01-04\r\n] 2006.201.05:28:23.10#ibcon#*before write, iclass 33, count 2 2006.201.05:28:23.10#ibcon#enter sib2, iclass 33, count 2 2006.201.05:28:23.10#ibcon#flushed, iclass 33, count 2 2006.201.05:28:23.10#ibcon#about to write, iclass 33, count 2 2006.201.05:28:23.10#ibcon#wrote, iclass 33, count 2 2006.201.05:28:23.10#ibcon#about to read 3, iclass 33, count 2 2006.201.05:28:23.13#ibcon#read 3, iclass 33, count 2 2006.201.05:28:23.13#ibcon#about to read 4, iclass 33, count 2 2006.201.05:28:23.13#ibcon#read 4, iclass 33, count 2 2006.201.05:28:23.13#ibcon#about to read 5, iclass 33, count 2 2006.201.05:28:23.13#ibcon#read 5, iclass 33, count 2 2006.201.05:28:23.13#ibcon#about to read 6, iclass 33, count 2 2006.201.05:28:23.13#ibcon#read 6, iclass 33, count 2 2006.201.05:28:23.13#ibcon#end of sib2, iclass 33, count 2 2006.201.05:28:23.13#ibcon#*after write, iclass 33, count 2 2006.201.05:28:23.13#ibcon#*before return 0, iclass 33, count 2 2006.201.05:28:23.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:23.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:28:23.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.05:28:23.13#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:23.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:23.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:23.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:23.25#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:28:23.25#ibcon#first serial, iclass 33, count 0 2006.201.05:28:23.25#ibcon#enter sib2, iclass 33, count 0 2006.201.05:28:23.25#ibcon#flushed, iclass 33, count 0 2006.201.05:28:23.25#ibcon#about to write, iclass 33, count 0 2006.201.05:28:23.25#ibcon#wrote, iclass 33, count 0 2006.201.05:28:23.25#ibcon#about to read 3, iclass 33, count 0 2006.201.05:28:23.27#ibcon#read 3, iclass 33, count 0 2006.201.05:28:23.27#ibcon#about to read 4, iclass 33, count 0 2006.201.05:28:23.27#ibcon#read 4, iclass 33, count 0 2006.201.05:28:23.27#ibcon#about to read 5, iclass 33, count 0 2006.201.05:28:23.27#ibcon#read 5, iclass 33, count 0 2006.201.05:28:23.27#ibcon#about to read 6, iclass 33, count 0 2006.201.05:28:23.27#ibcon#read 6, iclass 33, count 0 2006.201.05:28:23.27#ibcon#end of sib2, iclass 33, count 0 2006.201.05:28:23.27#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:28:23.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:28:23.27#ibcon#[27=USB\r\n] 2006.201.05:28:23.27#ibcon#*before write, iclass 33, count 0 2006.201.05:28:23.27#ibcon#enter sib2, iclass 33, count 0 2006.201.05:28:23.27#ibcon#flushed, iclass 33, count 0 2006.201.05:28:23.27#ibcon#about to write, iclass 33, count 0 2006.201.05:28:23.27#ibcon#wrote, iclass 33, count 0 2006.201.05:28:23.27#ibcon#about to read 3, iclass 33, count 0 2006.201.05:28:23.30#ibcon#read 3, iclass 33, count 0 2006.201.05:28:23.30#ibcon#about to read 4, iclass 33, count 0 2006.201.05:28:23.30#ibcon#read 4, iclass 33, count 0 2006.201.05:28:23.30#ibcon#about to read 5, iclass 33, count 0 2006.201.05:28:23.30#ibcon#read 5, iclass 33, count 0 2006.201.05:28:23.30#ibcon#about to read 6, iclass 33, count 0 2006.201.05:28:23.30#ibcon#read 6, iclass 33, count 0 2006.201.05:28:23.30#ibcon#end of sib2, iclass 33, count 0 2006.201.05:28:23.30#ibcon#*after write, iclass 33, count 0 2006.201.05:28:23.30#ibcon#*before return 0, iclass 33, count 0 2006.201.05:28:23.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:23.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:28:23.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:28:23.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:28:23.30$vck44/vblo=2,634.99 2006.201.05:28:23.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.05:28:23.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.05:28:23.30#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:23.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:23.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:23.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:23.30#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:28:23.30#ibcon#first serial, iclass 35, count 0 2006.201.05:28:23.30#ibcon#enter sib2, iclass 35, count 0 2006.201.05:28:23.30#ibcon#flushed, iclass 35, count 0 2006.201.05:28:23.30#ibcon#about to write, iclass 35, count 0 2006.201.05:28:23.30#ibcon#wrote, iclass 35, count 0 2006.201.05:28:23.30#ibcon#about to read 3, iclass 35, count 0 2006.201.05:28:23.32#ibcon#read 3, iclass 35, count 0 2006.201.05:28:23.32#ibcon#about to read 4, iclass 35, count 0 2006.201.05:28:23.32#ibcon#read 4, iclass 35, count 0 2006.201.05:28:23.32#ibcon#about to read 5, iclass 35, count 0 2006.201.05:28:23.32#ibcon#read 5, iclass 35, count 0 2006.201.05:28:23.32#ibcon#about to read 6, iclass 35, count 0 2006.201.05:28:23.32#ibcon#read 6, iclass 35, count 0 2006.201.05:28:23.32#ibcon#end of sib2, iclass 35, count 0 2006.201.05:28:23.32#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:28:23.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:28:23.32#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:28:23.32#ibcon#*before write, iclass 35, count 0 2006.201.05:28:23.32#ibcon#enter sib2, iclass 35, count 0 2006.201.05:28:23.32#ibcon#flushed, iclass 35, count 0 2006.201.05:28:23.32#ibcon#about to write, iclass 35, count 0 2006.201.05:28:23.32#ibcon#wrote, iclass 35, count 0 2006.201.05:28:23.32#ibcon#about to read 3, iclass 35, count 0 2006.201.05:28:23.36#ibcon#read 3, iclass 35, count 0 2006.201.05:28:23.36#ibcon#about to read 4, iclass 35, count 0 2006.201.05:28:23.36#ibcon#read 4, iclass 35, count 0 2006.201.05:28:23.36#ibcon#about to read 5, iclass 35, count 0 2006.201.05:28:23.36#ibcon#read 5, iclass 35, count 0 2006.201.05:28:23.36#ibcon#about to read 6, iclass 35, count 0 2006.201.05:28:23.36#ibcon#read 6, iclass 35, count 0 2006.201.05:28:23.36#ibcon#end of sib2, iclass 35, count 0 2006.201.05:28:23.36#ibcon#*after write, iclass 35, count 0 2006.201.05:28:23.36#ibcon#*before return 0, iclass 35, count 0 2006.201.05:28:23.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:23.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:28:23.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:28:23.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:28:23.36$vck44/vb=2,5 2006.201.05:28:23.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.05:28:23.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.05:28:23.36#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:23.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:23.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:23.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:23.42#ibcon#enter wrdev, iclass 37, count 2 2006.201.05:28:23.42#ibcon#first serial, iclass 37, count 2 2006.201.05:28:23.42#ibcon#enter sib2, iclass 37, count 2 2006.201.05:28:23.42#ibcon#flushed, iclass 37, count 2 2006.201.05:28:23.42#ibcon#about to write, iclass 37, count 2 2006.201.05:28:23.42#ibcon#wrote, iclass 37, count 2 2006.201.05:28:23.42#ibcon#about to read 3, iclass 37, count 2 2006.201.05:28:23.44#ibcon#read 3, iclass 37, count 2 2006.201.05:28:23.44#ibcon#about to read 4, iclass 37, count 2 2006.201.05:28:23.44#ibcon#read 4, iclass 37, count 2 2006.201.05:28:23.44#ibcon#about to read 5, iclass 37, count 2 2006.201.05:28:23.44#ibcon#read 5, iclass 37, count 2 2006.201.05:28:23.44#ibcon#about to read 6, iclass 37, count 2 2006.201.05:28:23.44#ibcon#read 6, iclass 37, count 2 2006.201.05:28:23.44#ibcon#end of sib2, iclass 37, count 2 2006.201.05:28:23.44#ibcon#*mode == 0, iclass 37, count 2 2006.201.05:28:23.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.05:28:23.44#ibcon#[27=AT02-05\r\n] 2006.201.05:28:23.44#ibcon#*before write, iclass 37, count 2 2006.201.05:28:23.44#ibcon#enter sib2, iclass 37, count 2 2006.201.05:28:23.44#ibcon#flushed, iclass 37, count 2 2006.201.05:28:23.44#ibcon#about to write, iclass 37, count 2 2006.201.05:28:23.44#ibcon#wrote, iclass 37, count 2 2006.201.05:28:23.44#ibcon#about to read 3, iclass 37, count 2 2006.201.05:28:23.47#ibcon#read 3, iclass 37, count 2 2006.201.05:28:23.47#ibcon#about to read 4, iclass 37, count 2 2006.201.05:28:23.47#ibcon#read 4, iclass 37, count 2 2006.201.05:28:23.47#ibcon#about to read 5, iclass 37, count 2 2006.201.05:28:23.47#ibcon#read 5, iclass 37, count 2 2006.201.05:28:23.47#ibcon#about to read 6, iclass 37, count 2 2006.201.05:28:23.47#ibcon#read 6, iclass 37, count 2 2006.201.05:28:23.47#ibcon#end of sib2, iclass 37, count 2 2006.201.05:28:23.47#ibcon#*after write, iclass 37, count 2 2006.201.05:28:23.47#ibcon#*before return 0, iclass 37, count 2 2006.201.05:28:23.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:23.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:28:23.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.05:28:23.47#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:23.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:23.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:23.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:23.59#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:28:23.59#ibcon#first serial, iclass 37, count 0 2006.201.05:28:23.59#ibcon#enter sib2, iclass 37, count 0 2006.201.05:28:23.59#ibcon#flushed, iclass 37, count 0 2006.201.05:28:23.59#ibcon#about to write, iclass 37, count 0 2006.201.05:28:23.61#ibcon#wrote, iclass 37, count 0 2006.201.05:28:23.61#ibcon#about to read 3, iclass 37, count 0 2006.201.05:28:23.63#ibcon#read 3, iclass 37, count 0 2006.201.05:28:23.63#ibcon#about to read 4, iclass 37, count 0 2006.201.05:28:23.63#ibcon#read 4, iclass 37, count 0 2006.201.05:28:23.63#ibcon#about to read 5, iclass 37, count 0 2006.201.05:28:23.63#ibcon#read 5, iclass 37, count 0 2006.201.05:28:23.63#ibcon#about to read 6, iclass 37, count 0 2006.201.05:28:23.63#ibcon#read 6, iclass 37, count 0 2006.201.05:28:23.63#ibcon#end of sib2, iclass 37, count 0 2006.201.05:28:23.63#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:28:23.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:28:23.63#ibcon#[27=USB\r\n] 2006.201.05:28:23.63#ibcon#*before write, iclass 37, count 0 2006.201.05:28:23.63#ibcon#enter sib2, iclass 37, count 0 2006.201.05:28:23.63#ibcon#flushed, iclass 37, count 0 2006.201.05:28:23.63#ibcon#about to write, iclass 37, count 0 2006.201.05:28:23.63#ibcon#wrote, iclass 37, count 0 2006.201.05:28:23.63#ibcon#about to read 3, iclass 37, count 0 2006.201.05:28:23.66#ibcon#read 3, iclass 37, count 0 2006.201.05:28:23.66#ibcon#about to read 4, iclass 37, count 0 2006.201.05:28:23.66#ibcon#read 4, iclass 37, count 0 2006.201.05:28:23.66#ibcon#about to read 5, iclass 37, count 0 2006.201.05:28:23.66#ibcon#read 5, iclass 37, count 0 2006.201.05:28:23.66#ibcon#about to read 6, iclass 37, count 0 2006.201.05:28:23.66#ibcon#read 6, iclass 37, count 0 2006.201.05:28:23.66#ibcon#end of sib2, iclass 37, count 0 2006.201.05:28:23.66#ibcon#*after write, iclass 37, count 0 2006.201.05:28:23.66#ibcon#*before return 0, iclass 37, count 0 2006.201.05:28:23.66#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:23.66#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:28:23.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:28:23.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:28:23.66$vck44/vblo=3,649.99 2006.201.05:28:23.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.05:28:23.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.05:28:23.66#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:23.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:23.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:23.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:23.66#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:28:23.66#ibcon#first serial, iclass 39, count 0 2006.201.05:28:23.66#ibcon#enter sib2, iclass 39, count 0 2006.201.05:28:23.66#ibcon#flushed, iclass 39, count 0 2006.201.05:28:23.66#ibcon#about to write, iclass 39, count 0 2006.201.05:28:23.66#ibcon#wrote, iclass 39, count 0 2006.201.05:28:23.66#ibcon#about to read 3, iclass 39, count 0 2006.201.05:28:23.68#ibcon#read 3, iclass 39, count 0 2006.201.05:28:23.68#ibcon#about to read 4, iclass 39, count 0 2006.201.05:28:23.68#ibcon#read 4, iclass 39, count 0 2006.201.05:28:23.68#ibcon#about to read 5, iclass 39, count 0 2006.201.05:28:23.68#ibcon#read 5, iclass 39, count 0 2006.201.05:28:23.68#ibcon#about to read 6, iclass 39, count 0 2006.201.05:28:23.68#ibcon#read 6, iclass 39, count 0 2006.201.05:28:23.68#ibcon#end of sib2, iclass 39, count 0 2006.201.05:28:23.68#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:28:23.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:28:23.68#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:28:23.68#ibcon#*before write, iclass 39, count 0 2006.201.05:28:23.68#ibcon#enter sib2, iclass 39, count 0 2006.201.05:28:23.68#ibcon#flushed, iclass 39, count 0 2006.201.05:28:23.68#ibcon#about to write, iclass 39, count 0 2006.201.05:28:23.68#ibcon#wrote, iclass 39, count 0 2006.201.05:28:23.68#ibcon#about to read 3, iclass 39, count 0 2006.201.05:28:23.72#ibcon#read 3, iclass 39, count 0 2006.201.05:28:23.72#ibcon#about to read 4, iclass 39, count 0 2006.201.05:28:23.72#ibcon#read 4, iclass 39, count 0 2006.201.05:28:23.72#ibcon#about to read 5, iclass 39, count 0 2006.201.05:28:23.72#ibcon#read 5, iclass 39, count 0 2006.201.05:28:23.72#ibcon#about to read 6, iclass 39, count 0 2006.201.05:28:23.72#ibcon#read 6, iclass 39, count 0 2006.201.05:28:23.72#ibcon#end of sib2, iclass 39, count 0 2006.201.05:28:23.72#ibcon#*after write, iclass 39, count 0 2006.201.05:28:23.72#ibcon#*before return 0, iclass 39, count 0 2006.201.05:28:23.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:23.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:28:23.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:28:23.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:28:23.72$vck44/vb=3,4 2006.201.05:28:23.72#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.05:28:23.72#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.05:28:23.72#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:23.72#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:23.78#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:23.78#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:23.78#ibcon#enter wrdev, iclass 2, count 2 2006.201.05:28:23.78#ibcon#first serial, iclass 2, count 2 2006.201.05:28:23.78#ibcon#enter sib2, iclass 2, count 2 2006.201.05:28:23.78#ibcon#flushed, iclass 2, count 2 2006.201.05:28:23.78#ibcon#about to write, iclass 2, count 2 2006.201.05:28:23.78#ibcon#wrote, iclass 2, count 2 2006.201.05:28:23.78#ibcon#about to read 3, iclass 2, count 2 2006.201.05:28:23.80#ibcon#read 3, iclass 2, count 2 2006.201.05:28:23.80#ibcon#about to read 4, iclass 2, count 2 2006.201.05:28:23.80#ibcon#read 4, iclass 2, count 2 2006.201.05:28:23.80#ibcon#about to read 5, iclass 2, count 2 2006.201.05:28:23.80#ibcon#read 5, iclass 2, count 2 2006.201.05:28:23.80#ibcon#about to read 6, iclass 2, count 2 2006.201.05:28:23.80#ibcon#read 6, iclass 2, count 2 2006.201.05:28:23.80#ibcon#end of sib2, iclass 2, count 2 2006.201.05:28:23.80#ibcon#*mode == 0, iclass 2, count 2 2006.201.05:28:23.80#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.05:28:23.80#ibcon#[27=AT03-04\r\n] 2006.201.05:28:23.80#ibcon#*before write, iclass 2, count 2 2006.201.05:28:23.80#ibcon#enter sib2, iclass 2, count 2 2006.201.05:28:23.80#ibcon#flushed, iclass 2, count 2 2006.201.05:28:23.80#ibcon#about to write, iclass 2, count 2 2006.201.05:28:23.80#ibcon#wrote, iclass 2, count 2 2006.201.05:28:23.80#ibcon#about to read 3, iclass 2, count 2 2006.201.05:28:23.83#ibcon#read 3, iclass 2, count 2 2006.201.05:28:23.83#ibcon#about to read 4, iclass 2, count 2 2006.201.05:28:23.83#ibcon#read 4, iclass 2, count 2 2006.201.05:28:23.83#ibcon#about to read 5, iclass 2, count 2 2006.201.05:28:23.83#ibcon#read 5, iclass 2, count 2 2006.201.05:28:23.83#ibcon#about to read 6, iclass 2, count 2 2006.201.05:28:23.83#ibcon#read 6, iclass 2, count 2 2006.201.05:28:23.83#ibcon#end of sib2, iclass 2, count 2 2006.201.05:28:23.83#ibcon#*after write, iclass 2, count 2 2006.201.05:28:23.83#ibcon#*before return 0, iclass 2, count 2 2006.201.05:28:23.83#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:23.83#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:28:23.83#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.05:28:23.83#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:23.83#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:23.95#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:23.95#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:23.95#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:28:23.95#ibcon#first serial, iclass 2, count 0 2006.201.05:28:23.95#ibcon#enter sib2, iclass 2, count 0 2006.201.05:28:23.95#ibcon#flushed, iclass 2, count 0 2006.201.05:28:23.95#ibcon#about to write, iclass 2, count 0 2006.201.05:28:23.95#ibcon#wrote, iclass 2, count 0 2006.201.05:28:23.95#ibcon#about to read 3, iclass 2, count 0 2006.201.05:28:23.97#ibcon#read 3, iclass 2, count 0 2006.201.05:28:23.97#ibcon#about to read 4, iclass 2, count 0 2006.201.05:28:23.97#ibcon#read 4, iclass 2, count 0 2006.201.05:28:23.97#ibcon#about to read 5, iclass 2, count 0 2006.201.05:28:23.97#ibcon#read 5, iclass 2, count 0 2006.201.05:28:23.97#ibcon#about to read 6, iclass 2, count 0 2006.201.05:28:23.97#ibcon#read 6, iclass 2, count 0 2006.201.05:28:23.97#ibcon#end of sib2, iclass 2, count 0 2006.201.05:28:23.97#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:28:23.97#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:28:23.97#ibcon#[27=USB\r\n] 2006.201.05:28:23.97#ibcon#*before write, iclass 2, count 0 2006.201.05:28:23.97#ibcon#enter sib2, iclass 2, count 0 2006.201.05:28:23.97#ibcon#flushed, iclass 2, count 0 2006.201.05:28:23.97#ibcon#about to write, iclass 2, count 0 2006.201.05:28:23.97#ibcon#wrote, iclass 2, count 0 2006.201.05:28:23.97#ibcon#about to read 3, iclass 2, count 0 2006.201.05:28:24.00#ibcon#read 3, iclass 2, count 0 2006.201.05:28:24.00#ibcon#about to read 4, iclass 2, count 0 2006.201.05:28:24.00#ibcon#read 4, iclass 2, count 0 2006.201.05:28:24.00#ibcon#about to read 5, iclass 2, count 0 2006.201.05:28:24.00#ibcon#read 5, iclass 2, count 0 2006.201.05:28:24.00#ibcon#about to read 6, iclass 2, count 0 2006.201.05:28:24.00#ibcon#read 6, iclass 2, count 0 2006.201.05:28:24.00#ibcon#end of sib2, iclass 2, count 0 2006.201.05:28:24.00#ibcon#*after write, iclass 2, count 0 2006.201.05:28:24.00#ibcon#*before return 0, iclass 2, count 0 2006.201.05:28:24.00#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:24.00#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:28:24.00#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:28:24.00#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:28:24.00$vck44/vblo=4,679.99 2006.201.05:28:24.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.05:28:24.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.05:28:24.00#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:24.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:28:24.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:28:24.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:28:24.00#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:28:24.00#ibcon#first serial, iclass 5, count 0 2006.201.05:28:24.00#ibcon#enter sib2, iclass 5, count 0 2006.201.05:28:24.00#ibcon#flushed, iclass 5, count 0 2006.201.05:28:24.00#ibcon#about to write, iclass 5, count 0 2006.201.05:28:24.00#ibcon#wrote, iclass 5, count 0 2006.201.05:28:24.00#ibcon#about to read 3, iclass 5, count 0 2006.201.05:28:24.02#ibcon#read 3, iclass 5, count 0 2006.201.05:28:24.02#ibcon#about to read 4, iclass 5, count 0 2006.201.05:28:24.02#ibcon#read 4, iclass 5, count 0 2006.201.05:28:24.02#ibcon#about to read 5, iclass 5, count 0 2006.201.05:28:24.02#ibcon#read 5, iclass 5, count 0 2006.201.05:28:24.02#ibcon#about to read 6, iclass 5, count 0 2006.201.05:28:24.02#ibcon#read 6, iclass 5, count 0 2006.201.05:28:24.02#ibcon#end of sib2, iclass 5, count 0 2006.201.05:28:24.02#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:28:24.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:28:24.02#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:28:24.02#ibcon#*before write, iclass 5, count 0 2006.201.05:28:24.02#ibcon#enter sib2, iclass 5, count 0 2006.201.05:28:24.02#ibcon#flushed, iclass 5, count 0 2006.201.05:28:24.02#ibcon#about to write, iclass 5, count 0 2006.201.05:28:24.02#ibcon#wrote, iclass 5, count 0 2006.201.05:28:24.02#ibcon#about to read 3, iclass 5, count 0 2006.201.05:28:24.06#ibcon#read 3, iclass 5, count 0 2006.201.05:28:24.06#ibcon#about to read 4, iclass 5, count 0 2006.201.05:28:24.06#ibcon#read 4, iclass 5, count 0 2006.201.05:28:24.06#ibcon#about to read 5, iclass 5, count 0 2006.201.05:28:24.06#ibcon#read 5, iclass 5, count 0 2006.201.05:28:24.06#ibcon#about to read 6, iclass 5, count 0 2006.201.05:28:24.06#ibcon#read 6, iclass 5, count 0 2006.201.05:28:24.06#ibcon#end of sib2, iclass 5, count 0 2006.201.05:28:24.06#ibcon#*after write, iclass 5, count 0 2006.201.05:28:24.06#ibcon#*before return 0, iclass 5, count 0 2006.201.05:28:24.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:28:24.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:28:24.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:28:24.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:28:24.06$vck44/vb=4,5 2006.201.05:28:24.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.05:28:24.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.05:28:24.06#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:24.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:28:24.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:28:24.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:28:24.12#ibcon#enter wrdev, iclass 7, count 2 2006.201.05:28:24.12#ibcon#first serial, iclass 7, count 2 2006.201.05:28:24.12#ibcon#enter sib2, iclass 7, count 2 2006.201.05:28:24.12#ibcon#flushed, iclass 7, count 2 2006.201.05:28:24.12#ibcon#about to write, iclass 7, count 2 2006.201.05:28:24.12#ibcon#wrote, iclass 7, count 2 2006.201.05:28:24.12#ibcon#about to read 3, iclass 7, count 2 2006.201.05:28:24.14#ibcon#read 3, iclass 7, count 2 2006.201.05:28:24.14#ibcon#about to read 4, iclass 7, count 2 2006.201.05:28:24.14#ibcon#read 4, iclass 7, count 2 2006.201.05:28:24.14#ibcon#about to read 5, iclass 7, count 2 2006.201.05:28:24.14#ibcon#read 5, iclass 7, count 2 2006.201.05:28:24.14#ibcon#about to read 6, iclass 7, count 2 2006.201.05:28:24.14#ibcon#read 6, iclass 7, count 2 2006.201.05:28:24.14#ibcon#end of sib2, iclass 7, count 2 2006.201.05:28:24.14#ibcon#*mode == 0, iclass 7, count 2 2006.201.05:28:24.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.05:28:24.14#ibcon#[27=AT04-05\r\n] 2006.201.05:28:24.14#ibcon#*before write, iclass 7, count 2 2006.201.05:28:24.14#ibcon#enter sib2, iclass 7, count 2 2006.201.05:28:24.14#ibcon#flushed, iclass 7, count 2 2006.201.05:28:24.14#ibcon#about to write, iclass 7, count 2 2006.201.05:28:24.14#ibcon#wrote, iclass 7, count 2 2006.201.05:28:24.14#ibcon#about to read 3, iclass 7, count 2 2006.201.05:28:24.17#ibcon#read 3, iclass 7, count 2 2006.201.05:28:24.17#ibcon#about to read 4, iclass 7, count 2 2006.201.05:28:24.17#ibcon#read 4, iclass 7, count 2 2006.201.05:28:24.17#ibcon#about to read 5, iclass 7, count 2 2006.201.05:28:24.17#ibcon#read 5, iclass 7, count 2 2006.201.05:28:24.17#ibcon#about to read 6, iclass 7, count 2 2006.201.05:28:24.17#ibcon#read 6, iclass 7, count 2 2006.201.05:28:24.17#ibcon#end of sib2, iclass 7, count 2 2006.201.05:28:24.17#ibcon#*after write, iclass 7, count 2 2006.201.05:28:24.17#ibcon#*before return 0, iclass 7, count 2 2006.201.05:28:24.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:28:24.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:28:24.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.05:28:24.17#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:24.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:28:24.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:28:24.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:28:24.29#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:28:24.29#ibcon#first serial, iclass 7, count 0 2006.201.05:28:24.29#ibcon#enter sib2, iclass 7, count 0 2006.201.05:28:24.29#ibcon#flushed, iclass 7, count 0 2006.201.05:28:24.29#ibcon#about to write, iclass 7, count 0 2006.201.05:28:24.29#ibcon#wrote, iclass 7, count 0 2006.201.05:28:24.29#ibcon#about to read 3, iclass 7, count 0 2006.201.05:28:24.31#ibcon#read 3, iclass 7, count 0 2006.201.05:28:24.31#ibcon#about to read 4, iclass 7, count 0 2006.201.05:28:24.31#ibcon#read 4, iclass 7, count 0 2006.201.05:28:24.31#ibcon#about to read 5, iclass 7, count 0 2006.201.05:28:24.31#ibcon#read 5, iclass 7, count 0 2006.201.05:28:24.31#ibcon#about to read 6, iclass 7, count 0 2006.201.05:28:24.31#ibcon#read 6, iclass 7, count 0 2006.201.05:28:24.31#ibcon#end of sib2, iclass 7, count 0 2006.201.05:28:24.31#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:28:24.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:28:24.31#ibcon#[27=USB\r\n] 2006.201.05:28:24.31#ibcon#*before write, iclass 7, count 0 2006.201.05:28:24.31#ibcon#enter sib2, iclass 7, count 0 2006.201.05:28:24.31#ibcon#flushed, iclass 7, count 0 2006.201.05:28:24.31#ibcon#about to write, iclass 7, count 0 2006.201.05:28:24.31#ibcon#wrote, iclass 7, count 0 2006.201.05:28:24.31#ibcon#about to read 3, iclass 7, count 0 2006.201.05:28:24.34#ibcon#read 3, iclass 7, count 0 2006.201.05:28:24.34#ibcon#about to read 4, iclass 7, count 0 2006.201.05:28:24.34#ibcon#read 4, iclass 7, count 0 2006.201.05:28:24.34#ibcon#about to read 5, iclass 7, count 0 2006.201.05:28:24.34#ibcon#read 5, iclass 7, count 0 2006.201.05:28:24.34#ibcon#about to read 6, iclass 7, count 0 2006.201.05:28:24.34#ibcon#read 6, iclass 7, count 0 2006.201.05:28:24.34#ibcon#end of sib2, iclass 7, count 0 2006.201.05:28:24.34#ibcon#*after write, iclass 7, count 0 2006.201.05:28:24.34#ibcon#*before return 0, iclass 7, count 0 2006.201.05:28:24.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:28:24.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:28:24.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:28:24.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:28:24.34$vck44/vblo=5,709.99 2006.201.05:28:24.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.05:28:24.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.05:28:24.34#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:24.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:28:24.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:28:24.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:28:24.34#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:28:24.34#ibcon#first serial, iclass 11, count 0 2006.201.05:28:24.34#ibcon#enter sib2, iclass 11, count 0 2006.201.05:28:24.34#ibcon#flushed, iclass 11, count 0 2006.201.05:28:24.34#ibcon#about to write, iclass 11, count 0 2006.201.05:28:24.34#ibcon#wrote, iclass 11, count 0 2006.201.05:28:24.34#ibcon#about to read 3, iclass 11, count 0 2006.201.05:28:24.36#ibcon#read 3, iclass 11, count 0 2006.201.05:28:24.36#ibcon#about to read 4, iclass 11, count 0 2006.201.05:28:24.36#ibcon#read 4, iclass 11, count 0 2006.201.05:28:24.36#ibcon#about to read 5, iclass 11, count 0 2006.201.05:28:24.36#ibcon#read 5, iclass 11, count 0 2006.201.05:28:24.36#ibcon#about to read 6, iclass 11, count 0 2006.201.05:28:24.36#ibcon#read 6, iclass 11, count 0 2006.201.05:28:24.36#ibcon#end of sib2, iclass 11, count 0 2006.201.05:28:24.36#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:28:24.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:28:24.36#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:28:24.36#ibcon#*before write, iclass 11, count 0 2006.201.05:28:24.36#ibcon#enter sib2, iclass 11, count 0 2006.201.05:28:24.36#ibcon#flushed, iclass 11, count 0 2006.201.05:28:24.36#ibcon#about to write, iclass 11, count 0 2006.201.05:28:24.36#ibcon#wrote, iclass 11, count 0 2006.201.05:28:24.36#ibcon#about to read 3, iclass 11, count 0 2006.201.05:28:24.40#ibcon#read 3, iclass 11, count 0 2006.201.05:28:24.40#ibcon#about to read 4, iclass 11, count 0 2006.201.05:28:24.40#ibcon#read 4, iclass 11, count 0 2006.201.05:28:24.40#ibcon#about to read 5, iclass 11, count 0 2006.201.05:28:24.40#ibcon#read 5, iclass 11, count 0 2006.201.05:28:24.40#ibcon#about to read 6, iclass 11, count 0 2006.201.05:28:24.40#ibcon#read 6, iclass 11, count 0 2006.201.05:28:24.40#ibcon#end of sib2, iclass 11, count 0 2006.201.05:28:24.40#ibcon#*after write, iclass 11, count 0 2006.201.05:28:24.40#ibcon#*before return 0, iclass 11, count 0 2006.201.05:28:24.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:28:24.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:28:24.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:28:24.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:28:24.40$vck44/vb=5,4 2006.201.05:28:24.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.05:28:24.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.05:28:24.40#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:24.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:24.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:24.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:24.46#ibcon#enter wrdev, iclass 13, count 2 2006.201.05:28:24.46#ibcon#first serial, iclass 13, count 2 2006.201.05:28:24.46#ibcon#enter sib2, iclass 13, count 2 2006.201.05:28:24.46#ibcon#flushed, iclass 13, count 2 2006.201.05:28:24.46#ibcon#about to write, iclass 13, count 2 2006.201.05:28:24.46#ibcon#wrote, iclass 13, count 2 2006.201.05:28:24.46#ibcon#about to read 3, iclass 13, count 2 2006.201.05:28:24.48#ibcon#read 3, iclass 13, count 2 2006.201.05:28:24.48#ibcon#about to read 4, iclass 13, count 2 2006.201.05:28:24.48#ibcon#read 4, iclass 13, count 2 2006.201.05:28:24.48#ibcon#about to read 5, iclass 13, count 2 2006.201.05:28:24.48#ibcon#read 5, iclass 13, count 2 2006.201.05:28:24.48#ibcon#about to read 6, iclass 13, count 2 2006.201.05:28:24.48#ibcon#read 6, iclass 13, count 2 2006.201.05:28:24.48#ibcon#end of sib2, iclass 13, count 2 2006.201.05:28:24.48#ibcon#*mode == 0, iclass 13, count 2 2006.201.05:28:24.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.05:28:24.48#ibcon#[27=AT05-04\r\n] 2006.201.05:28:24.48#ibcon#*before write, iclass 13, count 2 2006.201.05:28:24.48#ibcon#enter sib2, iclass 13, count 2 2006.201.05:28:24.48#ibcon#flushed, iclass 13, count 2 2006.201.05:28:24.48#ibcon#about to write, iclass 13, count 2 2006.201.05:28:24.48#ibcon#wrote, iclass 13, count 2 2006.201.05:28:24.48#ibcon#about to read 3, iclass 13, count 2 2006.201.05:28:24.51#ibcon#read 3, iclass 13, count 2 2006.201.05:28:24.51#ibcon#about to read 4, iclass 13, count 2 2006.201.05:28:24.51#ibcon#read 4, iclass 13, count 2 2006.201.05:28:24.51#ibcon#about to read 5, iclass 13, count 2 2006.201.05:28:24.51#ibcon#read 5, iclass 13, count 2 2006.201.05:28:24.51#ibcon#about to read 6, iclass 13, count 2 2006.201.05:28:24.51#ibcon#read 6, iclass 13, count 2 2006.201.05:28:24.51#ibcon#end of sib2, iclass 13, count 2 2006.201.05:28:24.51#ibcon#*after write, iclass 13, count 2 2006.201.05:28:24.51#ibcon#*before return 0, iclass 13, count 2 2006.201.05:28:24.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:24.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:28:24.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.05:28:24.51#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:24.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:24.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:24.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:24.63#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:28:24.63#ibcon#first serial, iclass 13, count 0 2006.201.05:28:24.63#ibcon#enter sib2, iclass 13, count 0 2006.201.05:28:24.63#ibcon#flushed, iclass 13, count 0 2006.201.05:28:24.63#ibcon#about to write, iclass 13, count 0 2006.201.05:28:24.63#ibcon#wrote, iclass 13, count 0 2006.201.05:28:24.63#ibcon#about to read 3, iclass 13, count 0 2006.201.05:28:24.65#ibcon#read 3, iclass 13, count 0 2006.201.05:28:24.65#ibcon#about to read 4, iclass 13, count 0 2006.201.05:28:24.65#ibcon#read 4, iclass 13, count 0 2006.201.05:28:24.65#ibcon#about to read 5, iclass 13, count 0 2006.201.05:28:24.65#ibcon#read 5, iclass 13, count 0 2006.201.05:28:24.65#ibcon#about to read 6, iclass 13, count 0 2006.201.05:28:24.65#ibcon#read 6, iclass 13, count 0 2006.201.05:28:24.65#ibcon#end of sib2, iclass 13, count 0 2006.201.05:28:24.65#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:28:24.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:28:24.65#ibcon#[27=USB\r\n] 2006.201.05:28:24.65#ibcon#*before write, iclass 13, count 0 2006.201.05:28:24.65#ibcon#enter sib2, iclass 13, count 0 2006.201.05:28:24.65#ibcon#flushed, iclass 13, count 0 2006.201.05:28:24.65#ibcon#about to write, iclass 13, count 0 2006.201.05:28:24.65#ibcon#wrote, iclass 13, count 0 2006.201.05:28:24.65#ibcon#about to read 3, iclass 13, count 0 2006.201.05:28:24.68#ibcon#read 3, iclass 13, count 0 2006.201.05:28:24.68#ibcon#about to read 4, iclass 13, count 0 2006.201.05:28:24.68#ibcon#read 4, iclass 13, count 0 2006.201.05:28:24.68#ibcon#about to read 5, iclass 13, count 0 2006.201.05:28:24.68#ibcon#read 5, iclass 13, count 0 2006.201.05:28:24.68#ibcon#about to read 6, iclass 13, count 0 2006.201.05:28:24.68#ibcon#read 6, iclass 13, count 0 2006.201.05:28:24.68#ibcon#end of sib2, iclass 13, count 0 2006.201.05:28:24.68#ibcon#*after write, iclass 13, count 0 2006.201.05:28:24.68#ibcon#*before return 0, iclass 13, count 0 2006.201.05:28:24.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:24.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:28:24.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:28:24.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:28:24.68$vck44/vblo=6,719.99 2006.201.05:28:24.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.05:28:24.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.05:28:24.68#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:24.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:24.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:24.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:24.68#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:28:24.68#ibcon#first serial, iclass 15, count 0 2006.201.05:28:24.68#ibcon#enter sib2, iclass 15, count 0 2006.201.05:28:24.68#ibcon#flushed, iclass 15, count 0 2006.201.05:28:24.68#ibcon#about to write, iclass 15, count 0 2006.201.05:28:24.68#ibcon#wrote, iclass 15, count 0 2006.201.05:28:24.68#ibcon#about to read 3, iclass 15, count 0 2006.201.05:28:24.70#ibcon#read 3, iclass 15, count 0 2006.201.05:28:24.70#ibcon#about to read 4, iclass 15, count 0 2006.201.05:28:24.70#ibcon#read 4, iclass 15, count 0 2006.201.05:28:24.70#ibcon#about to read 5, iclass 15, count 0 2006.201.05:28:24.70#ibcon#read 5, iclass 15, count 0 2006.201.05:28:24.70#ibcon#about to read 6, iclass 15, count 0 2006.201.05:28:24.70#ibcon#read 6, iclass 15, count 0 2006.201.05:28:24.70#ibcon#end of sib2, iclass 15, count 0 2006.201.05:28:24.70#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:28:24.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:28:24.70#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:28:24.70#ibcon#*before write, iclass 15, count 0 2006.201.05:28:24.70#ibcon#enter sib2, iclass 15, count 0 2006.201.05:28:24.70#ibcon#flushed, iclass 15, count 0 2006.201.05:28:24.70#ibcon#about to write, iclass 15, count 0 2006.201.05:28:24.70#ibcon#wrote, iclass 15, count 0 2006.201.05:28:24.70#ibcon#about to read 3, iclass 15, count 0 2006.201.05:28:24.74#ibcon#read 3, iclass 15, count 0 2006.201.05:28:24.74#ibcon#about to read 4, iclass 15, count 0 2006.201.05:28:24.74#ibcon#read 4, iclass 15, count 0 2006.201.05:28:24.74#ibcon#about to read 5, iclass 15, count 0 2006.201.05:28:24.74#ibcon#read 5, iclass 15, count 0 2006.201.05:28:24.74#ibcon#about to read 6, iclass 15, count 0 2006.201.05:28:24.74#ibcon#read 6, iclass 15, count 0 2006.201.05:28:24.74#ibcon#end of sib2, iclass 15, count 0 2006.201.05:28:24.74#ibcon#*after write, iclass 15, count 0 2006.201.05:28:24.74#ibcon#*before return 0, iclass 15, count 0 2006.201.05:28:24.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:24.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:28:24.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:28:24.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:28:24.76$vck44/vb=6,4 2006.201.05:28:24.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.05:28:24.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.05:28:24.76#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:24.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:24.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:24.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:24.80#ibcon#enter wrdev, iclass 17, count 2 2006.201.05:28:24.80#ibcon#first serial, iclass 17, count 2 2006.201.05:28:24.80#ibcon#enter sib2, iclass 17, count 2 2006.201.05:28:24.80#ibcon#flushed, iclass 17, count 2 2006.201.05:28:24.80#ibcon#about to write, iclass 17, count 2 2006.201.05:28:24.80#ibcon#wrote, iclass 17, count 2 2006.201.05:28:24.80#ibcon#about to read 3, iclass 17, count 2 2006.201.05:28:24.82#ibcon#read 3, iclass 17, count 2 2006.201.05:28:24.82#ibcon#about to read 4, iclass 17, count 2 2006.201.05:28:24.82#ibcon#read 4, iclass 17, count 2 2006.201.05:28:24.82#ibcon#about to read 5, iclass 17, count 2 2006.201.05:28:24.82#ibcon#read 5, iclass 17, count 2 2006.201.05:28:24.82#ibcon#about to read 6, iclass 17, count 2 2006.201.05:28:24.82#ibcon#read 6, iclass 17, count 2 2006.201.05:28:24.82#ibcon#end of sib2, iclass 17, count 2 2006.201.05:28:24.82#ibcon#*mode == 0, iclass 17, count 2 2006.201.05:28:24.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.05:28:24.82#ibcon#[27=AT06-04\r\n] 2006.201.05:28:24.82#ibcon#*before write, iclass 17, count 2 2006.201.05:28:24.82#ibcon#enter sib2, iclass 17, count 2 2006.201.05:28:24.82#ibcon#flushed, iclass 17, count 2 2006.201.05:28:24.82#ibcon#about to write, iclass 17, count 2 2006.201.05:28:24.82#ibcon#wrote, iclass 17, count 2 2006.201.05:28:24.82#ibcon#about to read 3, iclass 17, count 2 2006.201.05:28:24.85#ibcon#read 3, iclass 17, count 2 2006.201.05:28:24.85#ibcon#about to read 4, iclass 17, count 2 2006.201.05:28:24.85#ibcon#read 4, iclass 17, count 2 2006.201.05:28:24.85#ibcon#about to read 5, iclass 17, count 2 2006.201.05:28:24.85#ibcon#read 5, iclass 17, count 2 2006.201.05:28:24.85#ibcon#about to read 6, iclass 17, count 2 2006.201.05:28:24.85#ibcon#read 6, iclass 17, count 2 2006.201.05:28:24.85#ibcon#end of sib2, iclass 17, count 2 2006.201.05:28:24.85#ibcon#*after write, iclass 17, count 2 2006.201.05:28:24.85#ibcon#*before return 0, iclass 17, count 2 2006.201.05:28:24.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:24.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:28:24.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.05:28:24.85#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:24.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:24.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:24.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:24.97#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:28:24.97#ibcon#first serial, iclass 17, count 0 2006.201.05:28:24.97#ibcon#enter sib2, iclass 17, count 0 2006.201.05:28:24.97#ibcon#flushed, iclass 17, count 0 2006.201.05:28:24.97#ibcon#about to write, iclass 17, count 0 2006.201.05:28:24.97#ibcon#wrote, iclass 17, count 0 2006.201.05:28:24.97#ibcon#about to read 3, iclass 17, count 0 2006.201.05:28:24.99#ibcon#read 3, iclass 17, count 0 2006.201.05:28:24.99#ibcon#about to read 4, iclass 17, count 0 2006.201.05:28:24.99#ibcon#read 4, iclass 17, count 0 2006.201.05:28:24.99#ibcon#about to read 5, iclass 17, count 0 2006.201.05:28:24.99#ibcon#read 5, iclass 17, count 0 2006.201.05:28:24.99#ibcon#about to read 6, iclass 17, count 0 2006.201.05:28:24.99#ibcon#read 6, iclass 17, count 0 2006.201.05:28:24.99#ibcon#end of sib2, iclass 17, count 0 2006.201.05:28:24.99#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:28:24.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:28:24.99#ibcon#[27=USB\r\n] 2006.201.05:28:24.99#ibcon#*before write, iclass 17, count 0 2006.201.05:28:24.99#ibcon#enter sib2, iclass 17, count 0 2006.201.05:28:24.99#ibcon#flushed, iclass 17, count 0 2006.201.05:28:24.99#ibcon#about to write, iclass 17, count 0 2006.201.05:28:24.99#ibcon#wrote, iclass 17, count 0 2006.201.05:28:24.99#ibcon#about to read 3, iclass 17, count 0 2006.201.05:28:25.02#ibcon#read 3, iclass 17, count 0 2006.201.05:28:25.02#ibcon#about to read 4, iclass 17, count 0 2006.201.05:28:25.02#ibcon#read 4, iclass 17, count 0 2006.201.05:28:25.02#ibcon#about to read 5, iclass 17, count 0 2006.201.05:28:25.02#ibcon#read 5, iclass 17, count 0 2006.201.05:28:25.02#ibcon#about to read 6, iclass 17, count 0 2006.201.05:28:25.02#ibcon#read 6, iclass 17, count 0 2006.201.05:28:25.02#ibcon#end of sib2, iclass 17, count 0 2006.201.05:28:25.02#ibcon#*after write, iclass 17, count 0 2006.201.05:28:25.02#ibcon#*before return 0, iclass 17, count 0 2006.201.05:28:25.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:25.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:28:25.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:28:25.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:28:25.02$vck44/vblo=7,734.99 2006.201.05:28:25.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.05:28:25.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.05:28:25.02#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:25.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:25.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:25.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:25.02#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:28:25.02#ibcon#first serial, iclass 19, count 0 2006.201.05:28:25.02#ibcon#enter sib2, iclass 19, count 0 2006.201.05:28:25.02#ibcon#flushed, iclass 19, count 0 2006.201.05:28:25.02#ibcon#about to write, iclass 19, count 0 2006.201.05:28:25.02#ibcon#wrote, iclass 19, count 0 2006.201.05:28:25.02#ibcon#about to read 3, iclass 19, count 0 2006.201.05:28:25.04#ibcon#read 3, iclass 19, count 0 2006.201.05:28:25.04#ibcon#about to read 4, iclass 19, count 0 2006.201.05:28:25.04#ibcon#read 4, iclass 19, count 0 2006.201.05:28:25.04#ibcon#about to read 5, iclass 19, count 0 2006.201.05:28:25.04#ibcon#read 5, iclass 19, count 0 2006.201.05:28:25.04#ibcon#about to read 6, iclass 19, count 0 2006.201.05:28:25.04#ibcon#read 6, iclass 19, count 0 2006.201.05:28:25.04#ibcon#end of sib2, iclass 19, count 0 2006.201.05:28:25.04#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:28:25.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:28:25.04#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:28:25.04#ibcon#*before write, iclass 19, count 0 2006.201.05:28:25.04#ibcon#enter sib2, iclass 19, count 0 2006.201.05:28:25.04#ibcon#flushed, iclass 19, count 0 2006.201.05:28:25.04#ibcon#about to write, iclass 19, count 0 2006.201.05:28:25.04#ibcon#wrote, iclass 19, count 0 2006.201.05:28:25.04#ibcon#about to read 3, iclass 19, count 0 2006.201.05:28:25.08#ibcon#read 3, iclass 19, count 0 2006.201.05:28:25.08#ibcon#about to read 4, iclass 19, count 0 2006.201.05:28:25.08#ibcon#read 4, iclass 19, count 0 2006.201.05:28:25.08#ibcon#about to read 5, iclass 19, count 0 2006.201.05:28:25.08#ibcon#read 5, iclass 19, count 0 2006.201.05:28:25.08#ibcon#about to read 6, iclass 19, count 0 2006.201.05:28:25.08#ibcon#read 6, iclass 19, count 0 2006.201.05:28:25.08#ibcon#end of sib2, iclass 19, count 0 2006.201.05:28:25.08#ibcon#*after write, iclass 19, count 0 2006.201.05:28:25.08#ibcon#*before return 0, iclass 19, count 0 2006.201.05:28:25.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:25.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:28:25.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:28:25.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:28:25.08$vck44/vb=7,4 2006.201.05:28:25.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.05:28:25.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.05:28:25.08#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:25.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:25.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:25.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:25.14#ibcon#enter wrdev, iclass 21, count 2 2006.201.05:28:25.14#ibcon#first serial, iclass 21, count 2 2006.201.05:28:25.14#ibcon#enter sib2, iclass 21, count 2 2006.201.05:28:25.14#ibcon#flushed, iclass 21, count 2 2006.201.05:28:25.14#ibcon#about to write, iclass 21, count 2 2006.201.05:28:25.14#ibcon#wrote, iclass 21, count 2 2006.201.05:28:25.14#ibcon#about to read 3, iclass 21, count 2 2006.201.05:28:25.16#ibcon#read 3, iclass 21, count 2 2006.201.05:28:25.16#ibcon#about to read 4, iclass 21, count 2 2006.201.05:28:25.16#ibcon#read 4, iclass 21, count 2 2006.201.05:28:25.16#ibcon#about to read 5, iclass 21, count 2 2006.201.05:28:25.16#ibcon#read 5, iclass 21, count 2 2006.201.05:28:25.16#ibcon#about to read 6, iclass 21, count 2 2006.201.05:28:25.16#ibcon#read 6, iclass 21, count 2 2006.201.05:28:25.16#ibcon#end of sib2, iclass 21, count 2 2006.201.05:28:25.16#ibcon#*mode == 0, iclass 21, count 2 2006.201.05:28:25.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.05:28:25.16#ibcon#[27=AT07-04\r\n] 2006.201.05:28:25.16#ibcon#*before write, iclass 21, count 2 2006.201.05:28:25.16#ibcon#enter sib2, iclass 21, count 2 2006.201.05:28:25.16#ibcon#flushed, iclass 21, count 2 2006.201.05:28:25.16#ibcon#about to write, iclass 21, count 2 2006.201.05:28:25.16#ibcon#wrote, iclass 21, count 2 2006.201.05:28:25.16#ibcon#about to read 3, iclass 21, count 2 2006.201.05:28:25.19#ibcon#read 3, iclass 21, count 2 2006.201.05:28:25.19#ibcon#about to read 4, iclass 21, count 2 2006.201.05:28:25.19#ibcon#read 4, iclass 21, count 2 2006.201.05:28:25.19#ibcon#about to read 5, iclass 21, count 2 2006.201.05:28:25.19#ibcon#read 5, iclass 21, count 2 2006.201.05:28:25.19#ibcon#about to read 6, iclass 21, count 2 2006.201.05:28:25.19#ibcon#read 6, iclass 21, count 2 2006.201.05:28:25.19#ibcon#end of sib2, iclass 21, count 2 2006.201.05:28:25.19#ibcon#*after write, iclass 21, count 2 2006.201.05:28:25.19#ibcon#*before return 0, iclass 21, count 2 2006.201.05:28:25.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:25.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:28:25.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.05:28:25.19#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:25.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:25.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:25.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:25.31#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:28:25.31#ibcon#first serial, iclass 21, count 0 2006.201.05:28:25.31#ibcon#enter sib2, iclass 21, count 0 2006.201.05:28:25.31#ibcon#flushed, iclass 21, count 0 2006.201.05:28:25.31#ibcon#about to write, iclass 21, count 0 2006.201.05:28:25.31#ibcon#wrote, iclass 21, count 0 2006.201.05:28:25.31#ibcon#about to read 3, iclass 21, count 0 2006.201.05:28:25.33#ibcon#read 3, iclass 21, count 0 2006.201.05:28:25.33#ibcon#about to read 4, iclass 21, count 0 2006.201.05:28:25.33#ibcon#read 4, iclass 21, count 0 2006.201.05:28:25.33#ibcon#about to read 5, iclass 21, count 0 2006.201.05:28:25.33#ibcon#read 5, iclass 21, count 0 2006.201.05:28:25.33#ibcon#about to read 6, iclass 21, count 0 2006.201.05:28:25.33#ibcon#read 6, iclass 21, count 0 2006.201.05:28:25.33#ibcon#end of sib2, iclass 21, count 0 2006.201.05:28:25.33#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:28:25.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:28:25.33#ibcon#[27=USB\r\n] 2006.201.05:28:25.33#ibcon#*before write, iclass 21, count 0 2006.201.05:28:25.33#ibcon#enter sib2, iclass 21, count 0 2006.201.05:28:25.33#ibcon#flushed, iclass 21, count 0 2006.201.05:28:25.33#ibcon#about to write, iclass 21, count 0 2006.201.05:28:25.33#ibcon#wrote, iclass 21, count 0 2006.201.05:28:25.33#ibcon#about to read 3, iclass 21, count 0 2006.201.05:28:25.36#ibcon#read 3, iclass 21, count 0 2006.201.05:28:25.36#ibcon#about to read 4, iclass 21, count 0 2006.201.05:28:25.36#ibcon#read 4, iclass 21, count 0 2006.201.05:28:25.36#ibcon#about to read 5, iclass 21, count 0 2006.201.05:28:25.36#ibcon#read 5, iclass 21, count 0 2006.201.05:28:25.36#ibcon#about to read 6, iclass 21, count 0 2006.201.05:28:25.36#ibcon#read 6, iclass 21, count 0 2006.201.05:28:25.36#ibcon#end of sib2, iclass 21, count 0 2006.201.05:28:25.36#ibcon#*after write, iclass 21, count 0 2006.201.05:28:25.36#ibcon#*before return 0, iclass 21, count 0 2006.201.05:28:25.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:25.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:28:25.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:28:25.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:28:25.36$vck44/vblo=8,744.99 2006.201.05:28:25.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.05:28:25.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.05:28:25.36#ibcon#ireg 17 cls_cnt 0 2006.201.05:28:25.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:25.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:25.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:25.36#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:28:25.36#ibcon#first serial, iclass 23, count 0 2006.201.05:28:25.36#ibcon#enter sib2, iclass 23, count 0 2006.201.05:28:25.36#ibcon#flushed, iclass 23, count 0 2006.201.05:28:25.36#ibcon#about to write, iclass 23, count 0 2006.201.05:28:25.36#ibcon#wrote, iclass 23, count 0 2006.201.05:28:25.36#ibcon#about to read 3, iclass 23, count 0 2006.201.05:28:25.38#ibcon#read 3, iclass 23, count 0 2006.201.05:28:25.38#ibcon#about to read 4, iclass 23, count 0 2006.201.05:28:25.38#ibcon#read 4, iclass 23, count 0 2006.201.05:28:25.38#ibcon#about to read 5, iclass 23, count 0 2006.201.05:28:25.38#ibcon#read 5, iclass 23, count 0 2006.201.05:28:25.38#ibcon#about to read 6, iclass 23, count 0 2006.201.05:28:25.38#ibcon#read 6, iclass 23, count 0 2006.201.05:28:25.38#ibcon#end of sib2, iclass 23, count 0 2006.201.05:28:25.38#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:28:25.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:28:25.38#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:28:25.38#ibcon#*before write, iclass 23, count 0 2006.201.05:28:25.38#ibcon#enter sib2, iclass 23, count 0 2006.201.05:28:25.38#ibcon#flushed, iclass 23, count 0 2006.201.05:28:25.38#ibcon#about to write, iclass 23, count 0 2006.201.05:28:25.38#ibcon#wrote, iclass 23, count 0 2006.201.05:28:25.38#ibcon#about to read 3, iclass 23, count 0 2006.201.05:28:25.42#ibcon#read 3, iclass 23, count 0 2006.201.05:28:25.42#ibcon#about to read 4, iclass 23, count 0 2006.201.05:28:25.42#ibcon#read 4, iclass 23, count 0 2006.201.05:28:25.42#ibcon#about to read 5, iclass 23, count 0 2006.201.05:28:25.42#ibcon#read 5, iclass 23, count 0 2006.201.05:28:25.42#ibcon#about to read 6, iclass 23, count 0 2006.201.05:28:25.42#ibcon#read 6, iclass 23, count 0 2006.201.05:28:25.42#ibcon#end of sib2, iclass 23, count 0 2006.201.05:28:25.42#ibcon#*after write, iclass 23, count 0 2006.201.05:28:25.42#ibcon#*before return 0, iclass 23, count 0 2006.201.05:28:25.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:25.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:28:25.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:28:25.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:28:25.42$vck44/vb=8,4 2006.201.05:28:25.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.05:28:25.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.05:28:25.42#ibcon#ireg 11 cls_cnt 2 2006.201.05:28:25.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:25.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:25.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:25.48#ibcon#enter wrdev, iclass 25, count 2 2006.201.05:28:25.48#ibcon#first serial, iclass 25, count 2 2006.201.05:28:25.48#ibcon#enter sib2, iclass 25, count 2 2006.201.05:28:25.48#ibcon#flushed, iclass 25, count 2 2006.201.05:28:25.48#ibcon#about to write, iclass 25, count 2 2006.201.05:28:25.48#ibcon#wrote, iclass 25, count 2 2006.201.05:28:25.48#ibcon#about to read 3, iclass 25, count 2 2006.201.05:28:25.50#ibcon#read 3, iclass 25, count 2 2006.201.05:28:25.50#ibcon#about to read 4, iclass 25, count 2 2006.201.05:28:25.50#ibcon#read 4, iclass 25, count 2 2006.201.05:28:25.50#ibcon#about to read 5, iclass 25, count 2 2006.201.05:28:25.50#ibcon#read 5, iclass 25, count 2 2006.201.05:28:25.50#ibcon#about to read 6, iclass 25, count 2 2006.201.05:28:25.50#ibcon#read 6, iclass 25, count 2 2006.201.05:28:25.50#ibcon#end of sib2, iclass 25, count 2 2006.201.05:28:25.50#ibcon#*mode == 0, iclass 25, count 2 2006.201.05:28:25.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.05:28:25.50#ibcon#[27=AT08-04\r\n] 2006.201.05:28:25.50#ibcon#*before write, iclass 25, count 2 2006.201.05:28:25.50#ibcon#enter sib2, iclass 25, count 2 2006.201.05:28:25.50#ibcon#flushed, iclass 25, count 2 2006.201.05:28:25.50#ibcon#about to write, iclass 25, count 2 2006.201.05:28:25.50#ibcon#wrote, iclass 25, count 2 2006.201.05:28:25.50#ibcon#about to read 3, iclass 25, count 2 2006.201.05:28:25.53#ibcon#read 3, iclass 25, count 2 2006.201.05:28:25.53#ibcon#about to read 4, iclass 25, count 2 2006.201.05:28:25.53#ibcon#read 4, iclass 25, count 2 2006.201.05:28:25.53#ibcon#about to read 5, iclass 25, count 2 2006.201.05:28:25.53#ibcon#read 5, iclass 25, count 2 2006.201.05:28:25.53#ibcon#about to read 6, iclass 25, count 2 2006.201.05:28:25.53#ibcon#read 6, iclass 25, count 2 2006.201.05:28:25.53#ibcon#end of sib2, iclass 25, count 2 2006.201.05:28:25.53#ibcon#*after write, iclass 25, count 2 2006.201.05:28:25.53#ibcon#*before return 0, iclass 25, count 2 2006.201.05:28:25.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:25.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:28:25.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.05:28:25.53#ibcon#ireg 7 cls_cnt 0 2006.201.05:28:25.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:25.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:25.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:25.65#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:28:25.65#ibcon#first serial, iclass 25, count 0 2006.201.05:28:25.65#ibcon#enter sib2, iclass 25, count 0 2006.201.05:28:25.65#ibcon#flushed, iclass 25, count 0 2006.201.05:28:25.65#ibcon#about to write, iclass 25, count 0 2006.201.05:28:25.65#ibcon#wrote, iclass 25, count 0 2006.201.05:28:25.65#ibcon#about to read 3, iclass 25, count 0 2006.201.05:28:25.67#ibcon#read 3, iclass 25, count 0 2006.201.05:28:25.67#ibcon#about to read 4, iclass 25, count 0 2006.201.05:28:25.67#ibcon#read 4, iclass 25, count 0 2006.201.05:28:25.67#ibcon#about to read 5, iclass 25, count 0 2006.201.05:28:25.67#ibcon#read 5, iclass 25, count 0 2006.201.05:28:25.67#ibcon#about to read 6, iclass 25, count 0 2006.201.05:28:25.67#ibcon#read 6, iclass 25, count 0 2006.201.05:28:25.67#ibcon#end of sib2, iclass 25, count 0 2006.201.05:28:25.67#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:28:25.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:28:25.67#ibcon#[27=USB\r\n] 2006.201.05:28:25.67#ibcon#*before write, iclass 25, count 0 2006.201.05:28:25.67#ibcon#enter sib2, iclass 25, count 0 2006.201.05:28:25.67#ibcon#flushed, iclass 25, count 0 2006.201.05:28:25.67#ibcon#about to write, iclass 25, count 0 2006.201.05:28:25.67#ibcon#wrote, iclass 25, count 0 2006.201.05:28:25.67#ibcon#about to read 3, iclass 25, count 0 2006.201.05:28:25.70#ibcon#read 3, iclass 25, count 0 2006.201.05:28:25.70#ibcon#about to read 4, iclass 25, count 0 2006.201.05:28:25.70#ibcon#read 4, iclass 25, count 0 2006.201.05:28:25.70#ibcon#about to read 5, iclass 25, count 0 2006.201.05:28:25.70#ibcon#read 5, iclass 25, count 0 2006.201.05:28:25.70#ibcon#about to read 6, iclass 25, count 0 2006.201.05:28:25.70#ibcon#read 6, iclass 25, count 0 2006.201.05:28:25.70#ibcon#end of sib2, iclass 25, count 0 2006.201.05:28:25.70#ibcon#*after write, iclass 25, count 0 2006.201.05:28:25.70#ibcon#*before return 0, iclass 25, count 0 2006.201.05:28:25.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:25.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:28:25.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:28:25.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:28:25.70$vck44/vabw=wide 2006.201.05:28:25.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.05:28:25.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.05:28:25.70#ibcon#ireg 8 cls_cnt 0 2006.201.05:28:25.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:25.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:25.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:25.70#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:28:25.70#ibcon#first serial, iclass 27, count 0 2006.201.05:28:25.70#ibcon#enter sib2, iclass 27, count 0 2006.201.05:28:25.70#ibcon#flushed, iclass 27, count 0 2006.201.05:28:25.70#ibcon#about to write, iclass 27, count 0 2006.201.05:28:25.70#ibcon#wrote, iclass 27, count 0 2006.201.05:28:25.70#ibcon#about to read 3, iclass 27, count 0 2006.201.05:28:25.72#ibcon#read 3, iclass 27, count 0 2006.201.05:28:25.72#ibcon#about to read 4, iclass 27, count 0 2006.201.05:28:25.72#ibcon#read 4, iclass 27, count 0 2006.201.05:28:25.72#ibcon#about to read 5, iclass 27, count 0 2006.201.05:28:25.72#ibcon#read 5, iclass 27, count 0 2006.201.05:28:25.72#ibcon#about to read 6, iclass 27, count 0 2006.201.05:28:25.72#ibcon#read 6, iclass 27, count 0 2006.201.05:28:25.72#ibcon#end of sib2, iclass 27, count 0 2006.201.05:28:25.72#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:28:25.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:28:25.72#ibcon#[25=BW32\r\n] 2006.201.05:28:25.72#ibcon#*before write, iclass 27, count 0 2006.201.05:28:25.72#ibcon#enter sib2, iclass 27, count 0 2006.201.05:28:25.72#ibcon#flushed, iclass 27, count 0 2006.201.05:28:25.72#ibcon#about to write, iclass 27, count 0 2006.201.05:28:25.72#ibcon#wrote, iclass 27, count 0 2006.201.05:28:25.72#ibcon#about to read 3, iclass 27, count 0 2006.201.05:28:25.75#ibcon#read 3, iclass 27, count 0 2006.201.05:28:25.75#ibcon#about to read 4, iclass 27, count 0 2006.201.05:28:25.75#ibcon#read 4, iclass 27, count 0 2006.201.05:28:25.75#ibcon#about to read 5, iclass 27, count 0 2006.201.05:28:25.75#ibcon#read 5, iclass 27, count 0 2006.201.05:28:25.75#ibcon#about to read 6, iclass 27, count 0 2006.201.05:28:25.75#ibcon#read 6, iclass 27, count 0 2006.201.05:28:25.75#ibcon#end of sib2, iclass 27, count 0 2006.201.05:28:25.75#ibcon#*after write, iclass 27, count 0 2006.201.05:28:25.75#ibcon#*before return 0, iclass 27, count 0 2006.201.05:28:25.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:25.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:28:25.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:28:25.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:28:25.75$vck44/vbbw=wide 2006.201.05:28:25.75#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:28:25.75#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:28:25.75#ibcon#ireg 8 cls_cnt 0 2006.201.05:28:25.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:28:25.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:28:25.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:28:25.82#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:28:25.82#ibcon#first serial, iclass 29, count 0 2006.201.05:28:25.82#ibcon#enter sib2, iclass 29, count 0 2006.201.05:28:25.82#ibcon#flushed, iclass 29, count 0 2006.201.05:28:25.82#ibcon#about to write, iclass 29, count 0 2006.201.05:28:25.82#ibcon#wrote, iclass 29, count 0 2006.201.05:28:25.82#ibcon#about to read 3, iclass 29, count 0 2006.201.05:28:25.84#ibcon#read 3, iclass 29, count 0 2006.201.05:28:25.84#ibcon#about to read 4, iclass 29, count 0 2006.201.05:28:25.84#ibcon#read 4, iclass 29, count 0 2006.201.05:28:25.84#ibcon#about to read 5, iclass 29, count 0 2006.201.05:28:25.84#ibcon#read 5, iclass 29, count 0 2006.201.05:28:25.84#ibcon#about to read 6, iclass 29, count 0 2006.201.05:28:25.84#ibcon#read 6, iclass 29, count 0 2006.201.05:28:25.84#ibcon#end of sib2, iclass 29, count 0 2006.201.05:28:25.84#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:28:25.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:28:25.84#ibcon#[27=BW32\r\n] 2006.201.05:28:25.84#ibcon#*before write, iclass 29, count 0 2006.201.05:28:25.84#ibcon#enter sib2, iclass 29, count 0 2006.201.05:28:25.84#ibcon#flushed, iclass 29, count 0 2006.201.05:28:25.84#ibcon#about to write, iclass 29, count 0 2006.201.05:28:25.84#ibcon#wrote, iclass 29, count 0 2006.201.05:28:25.84#ibcon#about to read 3, iclass 29, count 0 2006.201.05:28:25.87#ibcon#read 3, iclass 29, count 0 2006.201.05:28:25.87#ibcon#about to read 4, iclass 29, count 0 2006.201.05:28:25.87#ibcon#read 4, iclass 29, count 0 2006.201.05:28:25.87#ibcon#about to read 5, iclass 29, count 0 2006.201.05:28:25.87#ibcon#read 5, iclass 29, count 0 2006.201.05:28:25.87#ibcon#about to read 6, iclass 29, count 0 2006.201.05:28:25.87#ibcon#read 6, iclass 29, count 0 2006.201.05:28:25.87#ibcon#end of sib2, iclass 29, count 0 2006.201.05:28:25.87#ibcon#*after write, iclass 29, count 0 2006.201.05:28:25.87#ibcon#*before return 0, iclass 29, count 0 2006.201.05:28:25.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:28:25.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:28:25.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:28:25.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:28:25.87$setupk4/ifdk4 2006.201.05:28:25.87$ifdk4/lo= 2006.201.05:28:25.87$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:28:25.87$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:28:25.87$ifdk4/patch= 2006.201.05:28:25.87$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:28:25.87$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:28:25.87$setupk4/!*+20s 2006.201.05:28:31.39#abcon#<5=/05 3.3 5.1 23.21 901003.6\r\n> 2006.201.05:28:31.41#abcon#{5=INTERFACE CLEAR} 2006.201.05:28:31.47#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:28:40.26$setupk4/"tpicd 2006.201.05:28:40.26$setupk4/echo=off 2006.201.05:28:40.26$setupk4/xlog=off 2006.201.05:28:40.26:!2006.201.05:31:26 2006.201.05:28:41.13#trakl#Source acquired 2006.201.05:28:42.13#flagr#flagr/antenna,acquired 2006.201.05:31:26.00:preob 2006.201.05:31:26.14/onsource/TRACKING 2006.201.05:31:26.14:!2006.201.05:31:36 2006.201.05:31:36.00:"tape 2006.201.05:31:36.00:"st=record 2006.201.05:31:36.00:data_valid=on 2006.201.05:31:36.00:midob 2006.201.05:31:36.14/onsource/TRACKING 2006.201.05:31:36.14/wx/23.17,1003.6,91 2006.201.05:31:36.32/cable/+6.4656E-03 2006.201.05:31:37.41/va/01,08,usb,yes,35,38 2006.201.05:31:37.41/va/02,07,usb,yes,38,39 2006.201.05:31:37.41/va/03,08,usb,yes,34,36 2006.201.05:31:37.41/va/04,07,usb,yes,39,41 2006.201.05:31:37.41/va/05,04,usb,yes,34,35 2006.201.05:31:37.41/va/06,05,usb,yes,35,34 2006.201.05:31:37.41/va/07,05,usb,yes,34,35 2006.201.05:31:37.41/va/08,04,usb,yes,33,40 2006.201.05:31:37.64/valo/01,524.99,yes,locked 2006.201.05:31:37.64/valo/02,534.99,yes,locked 2006.201.05:31:37.64/valo/03,564.99,yes,locked 2006.201.05:31:37.64/valo/04,624.99,yes,locked 2006.201.05:31:37.64/valo/05,734.99,yes,locked 2006.201.05:31:37.64/valo/06,814.99,yes,locked 2006.201.05:31:37.64/valo/07,864.99,yes,locked 2006.201.05:31:37.64/valo/08,884.99,yes,locked 2006.201.05:31:38.73/vb/01,04,usb,yes,32,30 2006.201.05:31:38.73/vb/02,05,usb,yes,30,30 2006.201.05:31:38.73/vb/03,04,usb,yes,31,35 2006.201.05:31:38.73/vb/04,05,usb,yes,32,31 2006.201.05:31:38.73/vb/05,04,usb,yes,28,31 2006.201.05:31:38.73/vb/06,04,usb,yes,33,29 2006.201.05:31:38.73/vb/07,04,usb,yes,33,33 2006.201.05:31:38.73/vb/08,04,usb,yes,30,34 2006.201.05:31:38.97/vblo/01,629.99,yes,locked 2006.201.05:31:38.97/vblo/02,634.99,yes,locked 2006.201.05:31:38.97/vblo/03,649.99,yes,locked 2006.201.05:31:38.97/vblo/04,679.99,yes,locked 2006.201.05:31:38.97/vblo/05,709.99,yes,locked 2006.201.05:31:38.97/vblo/06,719.99,yes,locked 2006.201.05:31:38.97/vblo/07,734.99,yes,locked 2006.201.05:31:38.97/vblo/08,744.99,yes,locked 2006.201.05:31:39.12/vabw/8 2006.201.05:31:39.27/vbbw/8 2006.201.05:31:39.36/xfe/off,on,15.2 2006.201.05:31:39.75/ifatt/23,28,28,28 2006.201.05:31:40.05/fmout-gps/S +4.49E-07 2006.201.05:31:40.09:!2006.201.05:32:16 2006.201.05:32:16.00:data_valid=off 2006.201.05:32:16.00:"et 2006.201.05:32:16.00:!+3s 2006.201.05:32:19.02:"tape 2006.201.05:32:19.02:postob 2006.201.05:32:19.14/cable/+6.4643E-03 2006.201.05:32:19.14/wx/23.16,1003.6,91 2006.201.05:32:19.20/fmout-gps/S +4.49E-07 2006.201.05:32:19.20:scan_name=201-0533,jd0607,110 2006.201.05:32:19.20:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.201.05:32:21.14#flagr#flagr/antenna,new-source 2006.201.05:32:21.14:checkk5 2006.201.05:32:21.54/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:32:21.95/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:32:22.37/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:32:22.77/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:32:23.16/chk_obsdata//k5ts1/T2010531??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.05:32:23.56/chk_obsdata//k5ts2/T2010531??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.05:32:23.96/chk_obsdata//k5ts3/T2010531??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.05:32:24.36/chk_obsdata//k5ts4/T2010531??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.05:32:25.09/k5log//k5ts1_log_newline 2006.201.05:32:25.83/k5log//k5ts2_log_newline 2006.201.05:32:26.55/k5log//k5ts3_log_newline 2006.201.05:32:27.23/k5log//k5ts4_log_newline 2006.201.05:32:27.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:32:27.25:setupk4=1 2006.201.05:32:27.25$setupk4/echo=on 2006.201.05:32:27.25$setupk4/pcalon 2006.201.05:32:27.25$pcalon/"no phase cal control is implemented here 2006.201.05:32:27.25$setupk4/"tpicd=stop 2006.201.05:32:27.25$setupk4/"rec=synch_on 2006.201.05:32:27.25$setupk4/"rec_mode=128 2006.201.05:32:27.25$setupk4/!* 2006.201.05:32:27.25$setupk4/recpk4 2006.201.05:32:27.25$recpk4/recpatch= 2006.201.05:32:27.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:32:27.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:32:27.26$setupk4/vck44 2006.201.05:32:27.26$vck44/valo=1,524.99 2006.201.05:32:27.26#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.05:32:27.26#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.05:32:27.26#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:27.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:27.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:27.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:27.26#ibcon#enter wrdev, iclass 22, count 0 2006.201.05:32:27.26#ibcon#first serial, iclass 22, count 0 2006.201.05:32:27.26#ibcon#enter sib2, iclass 22, count 0 2006.201.05:32:27.26#ibcon#flushed, iclass 22, count 0 2006.201.05:32:27.26#ibcon#about to write, iclass 22, count 0 2006.201.05:32:27.26#ibcon#wrote, iclass 22, count 0 2006.201.05:32:27.26#ibcon#about to read 3, iclass 22, count 0 2006.201.05:32:27.28#ibcon#read 3, iclass 22, count 0 2006.201.05:32:27.28#ibcon#about to read 4, iclass 22, count 0 2006.201.05:32:27.28#ibcon#read 4, iclass 22, count 0 2006.201.05:32:27.28#ibcon#about to read 5, iclass 22, count 0 2006.201.05:32:27.28#ibcon#read 5, iclass 22, count 0 2006.201.05:32:27.28#ibcon#about to read 6, iclass 22, count 0 2006.201.05:32:27.28#ibcon#read 6, iclass 22, count 0 2006.201.05:32:27.28#ibcon#end of sib2, iclass 22, count 0 2006.201.05:32:27.28#ibcon#*mode == 0, iclass 22, count 0 2006.201.05:32:27.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.05:32:27.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:32:27.28#ibcon#*before write, iclass 22, count 0 2006.201.05:32:27.28#ibcon#enter sib2, iclass 22, count 0 2006.201.05:32:27.28#ibcon#flushed, iclass 22, count 0 2006.201.05:32:27.28#ibcon#about to write, iclass 22, count 0 2006.201.05:32:27.28#ibcon#wrote, iclass 22, count 0 2006.201.05:32:27.28#ibcon#about to read 3, iclass 22, count 0 2006.201.05:32:27.33#ibcon#read 3, iclass 22, count 0 2006.201.05:32:27.33#ibcon#about to read 4, iclass 22, count 0 2006.201.05:32:27.33#ibcon#read 4, iclass 22, count 0 2006.201.05:32:27.33#ibcon#about to read 5, iclass 22, count 0 2006.201.05:32:27.33#ibcon#read 5, iclass 22, count 0 2006.201.05:32:27.33#ibcon#about to read 6, iclass 22, count 0 2006.201.05:32:27.33#ibcon#read 6, iclass 22, count 0 2006.201.05:32:27.33#ibcon#end of sib2, iclass 22, count 0 2006.201.05:32:27.33#ibcon#*after write, iclass 22, count 0 2006.201.05:32:27.33#ibcon#*before return 0, iclass 22, count 0 2006.201.05:32:27.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:27.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:27.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.05:32:27.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.05:32:27.33$vck44/va=1,8 2006.201.05:32:27.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.05:32:27.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.05:32:27.33#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:27.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:27.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:27.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:27.33#ibcon#enter wrdev, iclass 24, count 2 2006.201.05:32:27.33#ibcon#first serial, iclass 24, count 2 2006.201.05:32:27.33#ibcon#enter sib2, iclass 24, count 2 2006.201.05:32:27.33#ibcon#flushed, iclass 24, count 2 2006.201.05:32:27.33#ibcon#about to write, iclass 24, count 2 2006.201.05:32:27.33#ibcon#wrote, iclass 24, count 2 2006.201.05:32:27.33#ibcon#about to read 3, iclass 24, count 2 2006.201.05:32:27.35#ibcon#read 3, iclass 24, count 2 2006.201.05:32:27.35#ibcon#about to read 4, iclass 24, count 2 2006.201.05:32:27.35#ibcon#read 4, iclass 24, count 2 2006.201.05:32:27.35#ibcon#about to read 5, iclass 24, count 2 2006.201.05:32:27.35#ibcon#read 5, iclass 24, count 2 2006.201.05:32:27.35#ibcon#about to read 6, iclass 24, count 2 2006.201.05:32:27.35#ibcon#read 6, iclass 24, count 2 2006.201.05:32:27.35#ibcon#end of sib2, iclass 24, count 2 2006.201.05:32:27.35#ibcon#*mode == 0, iclass 24, count 2 2006.201.05:32:27.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.05:32:27.35#ibcon#[25=AT01-08\r\n] 2006.201.05:32:27.35#ibcon#*before write, iclass 24, count 2 2006.201.05:32:27.35#ibcon#enter sib2, iclass 24, count 2 2006.201.05:32:27.35#ibcon#flushed, iclass 24, count 2 2006.201.05:32:27.35#ibcon#about to write, iclass 24, count 2 2006.201.05:32:27.35#ibcon#wrote, iclass 24, count 2 2006.201.05:32:27.35#ibcon#about to read 3, iclass 24, count 2 2006.201.05:32:27.38#ibcon#read 3, iclass 24, count 2 2006.201.05:32:27.38#ibcon#about to read 4, iclass 24, count 2 2006.201.05:32:27.38#ibcon#read 4, iclass 24, count 2 2006.201.05:32:27.38#ibcon#about to read 5, iclass 24, count 2 2006.201.05:32:27.38#ibcon#read 5, iclass 24, count 2 2006.201.05:32:27.38#ibcon#about to read 6, iclass 24, count 2 2006.201.05:32:27.38#ibcon#read 6, iclass 24, count 2 2006.201.05:32:27.38#ibcon#end of sib2, iclass 24, count 2 2006.201.05:32:27.38#ibcon#*after write, iclass 24, count 2 2006.201.05:32:27.38#ibcon#*before return 0, iclass 24, count 2 2006.201.05:32:27.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:27.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:27.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.05:32:27.38#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:27.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:27.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:27.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:27.50#ibcon#enter wrdev, iclass 24, count 0 2006.201.05:32:27.50#ibcon#first serial, iclass 24, count 0 2006.201.05:32:27.50#ibcon#enter sib2, iclass 24, count 0 2006.201.05:32:27.50#ibcon#flushed, iclass 24, count 0 2006.201.05:32:27.50#ibcon#about to write, iclass 24, count 0 2006.201.05:32:27.50#ibcon#wrote, iclass 24, count 0 2006.201.05:32:27.50#ibcon#about to read 3, iclass 24, count 0 2006.201.05:32:27.52#ibcon#read 3, iclass 24, count 0 2006.201.05:32:27.52#ibcon#about to read 4, iclass 24, count 0 2006.201.05:32:27.52#ibcon#read 4, iclass 24, count 0 2006.201.05:32:27.52#ibcon#about to read 5, iclass 24, count 0 2006.201.05:32:27.52#ibcon#read 5, iclass 24, count 0 2006.201.05:32:27.52#ibcon#about to read 6, iclass 24, count 0 2006.201.05:32:27.52#ibcon#read 6, iclass 24, count 0 2006.201.05:32:27.52#ibcon#end of sib2, iclass 24, count 0 2006.201.05:32:27.52#ibcon#*mode == 0, iclass 24, count 0 2006.201.05:32:27.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.05:32:27.52#ibcon#[25=USB\r\n] 2006.201.05:32:27.52#ibcon#*before write, iclass 24, count 0 2006.201.05:32:27.52#ibcon#enter sib2, iclass 24, count 0 2006.201.05:32:27.52#ibcon#flushed, iclass 24, count 0 2006.201.05:32:27.52#ibcon#about to write, iclass 24, count 0 2006.201.05:32:27.52#ibcon#wrote, iclass 24, count 0 2006.201.05:32:27.52#ibcon#about to read 3, iclass 24, count 0 2006.201.05:32:27.55#ibcon#read 3, iclass 24, count 0 2006.201.05:32:27.55#ibcon#about to read 4, iclass 24, count 0 2006.201.05:32:27.55#ibcon#read 4, iclass 24, count 0 2006.201.05:32:27.55#ibcon#about to read 5, iclass 24, count 0 2006.201.05:32:27.55#ibcon#read 5, iclass 24, count 0 2006.201.05:32:27.55#ibcon#about to read 6, iclass 24, count 0 2006.201.05:32:27.55#ibcon#read 6, iclass 24, count 0 2006.201.05:32:27.55#ibcon#end of sib2, iclass 24, count 0 2006.201.05:32:27.55#ibcon#*after write, iclass 24, count 0 2006.201.05:32:27.55#ibcon#*before return 0, iclass 24, count 0 2006.201.05:32:27.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:27.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:27.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.05:32:27.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.05:32:27.55$vck44/valo=2,534.99 2006.201.05:32:27.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.05:32:27.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.05:32:27.55#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:27.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:27.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:27.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:27.55#ibcon#enter wrdev, iclass 26, count 0 2006.201.05:32:27.55#ibcon#first serial, iclass 26, count 0 2006.201.05:32:27.55#ibcon#enter sib2, iclass 26, count 0 2006.201.05:32:27.55#ibcon#flushed, iclass 26, count 0 2006.201.05:32:27.55#ibcon#about to write, iclass 26, count 0 2006.201.05:32:27.55#ibcon#wrote, iclass 26, count 0 2006.201.05:32:27.55#ibcon#about to read 3, iclass 26, count 0 2006.201.05:32:27.57#ibcon#read 3, iclass 26, count 0 2006.201.05:32:27.57#ibcon#about to read 4, iclass 26, count 0 2006.201.05:32:27.57#ibcon#read 4, iclass 26, count 0 2006.201.05:32:27.57#ibcon#about to read 5, iclass 26, count 0 2006.201.05:32:27.57#ibcon#read 5, iclass 26, count 0 2006.201.05:32:27.57#ibcon#about to read 6, iclass 26, count 0 2006.201.05:32:27.57#ibcon#read 6, iclass 26, count 0 2006.201.05:32:27.57#ibcon#end of sib2, iclass 26, count 0 2006.201.05:32:27.57#ibcon#*mode == 0, iclass 26, count 0 2006.201.05:32:27.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.05:32:27.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:32:27.57#ibcon#*before write, iclass 26, count 0 2006.201.05:32:27.57#ibcon#enter sib2, iclass 26, count 0 2006.201.05:32:27.57#ibcon#flushed, iclass 26, count 0 2006.201.05:32:27.57#ibcon#about to write, iclass 26, count 0 2006.201.05:32:27.57#ibcon#wrote, iclass 26, count 0 2006.201.05:32:27.57#ibcon#about to read 3, iclass 26, count 0 2006.201.05:32:27.61#ibcon#read 3, iclass 26, count 0 2006.201.05:32:27.61#ibcon#about to read 4, iclass 26, count 0 2006.201.05:32:27.61#ibcon#read 4, iclass 26, count 0 2006.201.05:32:27.61#ibcon#about to read 5, iclass 26, count 0 2006.201.05:32:27.61#ibcon#read 5, iclass 26, count 0 2006.201.05:32:27.61#ibcon#about to read 6, iclass 26, count 0 2006.201.05:32:27.61#ibcon#read 6, iclass 26, count 0 2006.201.05:32:27.61#ibcon#end of sib2, iclass 26, count 0 2006.201.05:32:27.61#ibcon#*after write, iclass 26, count 0 2006.201.05:32:27.61#ibcon#*before return 0, iclass 26, count 0 2006.201.05:32:27.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:27.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:27.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.05:32:27.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.05:32:27.61$vck44/va=2,7 2006.201.05:32:27.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.05:32:27.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.05:32:27.61#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:27.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:27.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:27.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:27.67#ibcon#enter wrdev, iclass 28, count 2 2006.201.05:32:27.67#ibcon#first serial, iclass 28, count 2 2006.201.05:32:27.67#ibcon#enter sib2, iclass 28, count 2 2006.201.05:32:27.67#ibcon#flushed, iclass 28, count 2 2006.201.05:32:27.67#ibcon#about to write, iclass 28, count 2 2006.201.05:32:27.67#ibcon#wrote, iclass 28, count 2 2006.201.05:32:27.67#ibcon#about to read 3, iclass 28, count 2 2006.201.05:32:27.69#ibcon#read 3, iclass 28, count 2 2006.201.05:32:27.69#ibcon#about to read 4, iclass 28, count 2 2006.201.05:32:27.69#ibcon#read 4, iclass 28, count 2 2006.201.05:32:27.69#ibcon#about to read 5, iclass 28, count 2 2006.201.05:32:27.69#ibcon#read 5, iclass 28, count 2 2006.201.05:32:27.69#ibcon#about to read 6, iclass 28, count 2 2006.201.05:32:27.69#ibcon#read 6, iclass 28, count 2 2006.201.05:32:27.69#ibcon#end of sib2, iclass 28, count 2 2006.201.05:32:27.69#ibcon#*mode == 0, iclass 28, count 2 2006.201.05:32:27.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.05:32:27.69#ibcon#[25=AT02-07\r\n] 2006.201.05:32:27.69#ibcon#*before write, iclass 28, count 2 2006.201.05:32:27.69#ibcon#enter sib2, iclass 28, count 2 2006.201.05:32:27.69#ibcon#flushed, iclass 28, count 2 2006.201.05:32:27.69#ibcon#about to write, iclass 28, count 2 2006.201.05:32:27.69#ibcon#wrote, iclass 28, count 2 2006.201.05:32:27.69#ibcon#about to read 3, iclass 28, count 2 2006.201.05:32:27.72#ibcon#read 3, iclass 28, count 2 2006.201.05:32:27.72#ibcon#about to read 4, iclass 28, count 2 2006.201.05:32:27.72#ibcon#read 4, iclass 28, count 2 2006.201.05:32:27.72#ibcon#about to read 5, iclass 28, count 2 2006.201.05:32:27.72#ibcon#read 5, iclass 28, count 2 2006.201.05:32:27.72#ibcon#about to read 6, iclass 28, count 2 2006.201.05:32:27.72#ibcon#read 6, iclass 28, count 2 2006.201.05:32:27.72#ibcon#end of sib2, iclass 28, count 2 2006.201.05:32:27.72#ibcon#*after write, iclass 28, count 2 2006.201.05:32:27.72#ibcon#*before return 0, iclass 28, count 2 2006.201.05:32:27.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:27.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:27.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.05:32:27.72#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:27.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:27.84#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:27.84#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:27.84#ibcon#enter wrdev, iclass 28, count 0 2006.201.05:32:27.84#ibcon#first serial, iclass 28, count 0 2006.201.05:32:27.84#ibcon#enter sib2, iclass 28, count 0 2006.201.05:32:27.84#ibcon#flushed, iclass 28, count 0 2006.201.05:32:27.84#ibcon#about to write, iclass 28, count 0 2006.201.05:32:27.84#ibcon#wrote, iclass 28, count 0 2006.201.05:32:27.84#ibcon#about to read 3, iclass 28, count 0 2006.201.05:32:27.86#ibcon#read 3, iclass 28, count 0 2006.201.05:32:27.86#ibcon#about to read 4, iclass 28, count 0 2006.201.05:32:27.86#ibcon#read 4, iclass 28, count 0 2006.201.05:32:27.86#ibcon#about to read 5, iclass 28, count 0 2006.201.05:32:27.86#ibcon#read 5, iclass 28, count 0 2006.201.05:32:27.86#ibcon#about to read 6, iclass 28, count 0 2006.201.05:32:27.86#ibcon#read 6, iclass 28, count 0 2006.201.05:32:27.86#ibcon#end of sib2, iclass 28, count 0 2006.201.05:32:27.86#ibcon#*mode == 0, iclass 28, count 0 2006.201.05:32:27.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.05:32:27.86#ibcon#[25=USB\r\n] 2006.201.05:32:27.86#ibcon#*before write, iclass 28, count 0 2006.201.05:32:27.86#ibcon#enter sib2, iclass 28, count 0 2006.201.05:32:27.86#ibcon#flushed, iclass 28, count 0 2006.201.05:32:27.86#ibcon#about to write, iclass 28, count 0 2006.201.05:32:27.86#ibcon#wrote, iclass 28, count 0 2006.201.05:32:27.86#ibcon#about to read 3, iclass 28, count 0 2006.201.05:32:27.89#ibcon#read 3, iclass 28, count 0 2006.201.05:32:27.89#ibcon#about to read 4, iclass 28, count 0 2006.201.05:32:27.89#ibcon#read 4, iclass 28, count 0 2006.201.05:32:27.89#ibcon#about to read 5, iclass 28, count 0 2006.201.05:32:27.89#ibcon#read 5, iclass 28, count 0 2006.201.05:32:27.89#ibcon#about to read 6, iclass 28, count 0 2006.201.05:32:27.89#ibcon#read 6, iclass 28, count 0 2006.201.05:32:27.89#ibcon#end of sib2, iclass 28, count 0 2006.201.05:32:27.89#ibcon#*after write, iclass 28, count 0 2006.201.05:32:27.89#ibcon#*before return 0, iclass 28, count 0 2006.201.05:32:27.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:27.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:27.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.05:32:27.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.05:32:27.89$vck44/valo=3,564.99 2006.201.05:32:27.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.05:32:27.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.05:32:27.89#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:27.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:27.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:27.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:27.89#ibcon#enter wrdev, iclass 30, count 0 2006.201.05:32:27.89#ibcon#first serial, iclass 30, count 0 2006.201.05:32:27.89#ibcon#enter sib2, iclass 30, count 0 2006.201.05:32:27.89#ibcon#flushed, iclass 30, count 0 2006.201.05:32:27.89#ibcon#about to write, iclass 30, count 0 2006.201.05:32:27.89#ibcon#wrote, iclass 30, count 0 2006.201.05:32:27.89#ibcon#about to read 3, iclass 30, count 0 2006.201.05:32:27.91#ibcon#read 3, iclass 30, count 0 2006.201.05:32:27.91#ibcon#about to read 4, iclass 30, count 0 2006.201.05:32:27.91#ibcon#read 4, iclass 30, count 0 2006.201.05:32:27.91#ibcon#about to read 5, iclass 30, count 0 2006.201.05:32:27.91#ibcon#read 5, iclass 30, count 0 2006.201.05:32:27.91#ibcon#about to read 6, iclass 30, count 0 2006.201.05:32:27.91#ibcon#read 6, iclass 30, count 0 2006.201.05:32:27.91#ibcon#end of sib2, iclass 30, count 0 2006.201.05:32:27.91#ibcon#*mode == 0, iclass 30, count 0 2006.201.05:32:27.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.05:32:27.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:32:27.91#ibcon#*before write, iclass 30, count 0 2006.201.05:32:27.91#ibcon#enter sib2, iclass 30, count 0 2006.201.05:32:27.91#ibcon#flushed, iclass 30, count 0 2006.201.05:32:27.91#ibcon#about to write, iclass 30, count 0 2006.201.05:32:27.91#ibcon#wrote, iclass 30, count 0 2006.201.05:32:27.91#ibcon#about to read 3, iclass 30, count 0 2006.201.05:32:27.95#ibcon#read 3, iclass 30, count 0 2006.201.05:32:27.95#ibcon#about to read 4, iclass 30, count 0 2006.201.05:32:27.95#ibcon#read 4, iclass 30, count 0 2006.201.05:32:27.95#ibcon#about to read 5, iclass 30, count 0 2006.201.05:32:27.95#ibcon#read 5, iclass 30, count 0 2006.201.05:32:27.95#ibcon#about to read 6, iclass 30, count 0 2006.201.05:32:27.95#ibcon#read 6, iclass 30, count 0 2006.201.05:32:27.95#ibcon#end of sib2, iclass 30, count 0 2006.201.05:32:27.95#ibcon#*after write, iclass 30, count 0 2006.201.05:32:27.95#ibcon#*before return 0, iclass 30, count 0 2006.201.05:32:27.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:27.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:27.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.05:32:27.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.05:32:27.95$vck44/va=3,8 2006.201.05:32:27.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.05:32:27.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.05:32:27.95#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:27.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:28.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:28.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:28.01#ibcon#enter wrdev, iclass 32, count 2 2006.201.05:32:28.01#ibcon#first serial, iclass 32, count 2 2006.201.05:32:28.01#ibcon#enter sib2, iclass 32, count 2 2006.201.05:32:28.01#ibcon#flushed, iclass 32, count 2 2006.201.05:32:28.01#ibcon#about to write, iclass 32, count 2 2006.201.05:32:28.01#ibcon#wrote, iclass 32, count 2 2006.201.05:32:28.01#ibcon#about to read 3, iclass 32, count 2 2006.201.05:32:28.03#ibcon#read 3, iclass 32, count 2 2006.201.05:32:28.03#ibcon#about to read 4, iclass 32, count 2 2006.201.05:32:28.03#ibcon#read 4, iclass 32, count 2 2006.201.05:32:28.03#ibcon#about to read 5, iclass 32, count 2 2006.201.05:32:28.03#ibcon#read 5, iclass 32, count 2 2006.201.05:32:28.03#ibcon#about to read 6, iclass 32, count 2 2006.201.05:32:28.03#ibcon#read 6, iclass 32, count 2 2006.201.05:32:28.03#ibcon#end of sib2, iclass 32, count 2 2006.201.05:32:28.03#ibcon#*mode == 0, iclass 32, count 2 2006.201.05:32:28.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.05:32:28.03#ibcon#[25=AT03-08\r\n] 2006.201.05:32:28.03#ibcon#*before write, iclass 32, count 2 2006.201.05:32:28.03#ibcon#enter sib2, iclass 32, count 2 2006.201.05:32:28.03#ibcon#flushed, iclass 32, count 2 2006.201.05:32:28.03#ibcon#about to write, iclass 32, count 2 2006.201.05:32:28.03#ibcon#wrote, iclass 32, count 2 2006.201.05:32:28.03#ibcon#about to read 3, iclass 32, count 2 2006.201.05:32:28.06#ibcon#read 3, iclass 32, count 2 2006.201.05:32:28.06#ibcon#about to read 4, iclass 32, count 2 2006.201.05:32:28.06#ibcon#read 4, iclass 32, count 2 2006.201.05:32:28.06#ibcon#about to read 5, iclass 32, count 2 2006.201.05:32:28.06#ibcon#read 5, iclass 32, count 2 2006.201.05:32:28.06#ibcon#about to read 6, iclass 32, count 2 2006.201.05:32:28.06#ibcon#read 6, iclass 32, count 2 2006.201.05:32:28.06#ibcon#end of sib2, iclass 32, count 2 2006.201.05:32:28.06#ibcon#*after write, iclass 32, count 2 2006.201.05:32:28.06#ibcon#*before return 0, iclass 32, count 2 2006.201.05:32:28.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:28.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:28.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.05:32:28.06#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:28.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:28.18#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:28.18#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:28.18#ibcon#enter wrdev, iclass 32, count 0 2006.201.05:32:28.18#ibcon#first serial, iclass 32, count 0 2006.201.05:32:28.18#ibcon#enter sib2, iclass 32, count 0 2006.201.05:32:28.18#ibcon#flushed, iclass 32, count 0 2006.201.05:32:28.18#ibcon#about to write, iclass 32, count 0 2006.201.05:32:28.18#ibcon#wrote, iclass 32, count 0 2006.201.05:32:28.18#ibcon#about to read 3, iclass 32, count 0 2006.201.05:32:28.20#ibcon#read 3, iclass 32, count 0 2006.201.05:32:28.20#ibcon#about to read 4, iclass 32, count 0 2006.201.05:32:28.20#ibcon#read 4, iclass 32, count 0 2006.201.05:32:28.20#ibcon#about to read 5, iclass 32, count 0 2006.201.05:32:28.20#ibcon#read 5, iclass 32, count 0 2006.201.05:32:28.20#ibcon#about to read 6, iclass 32, count 0 2006.201.05:32:28.20#ibcon#read 6, iclass 32, count 0 2006.201.05:32:28.20#ibcon#end of sib2, iclass 32, count 0 2006.201.05:32:28.20#ibcon#*mode == 0, iclass 32, count 0 2006.201.05:32:28.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.05:32:28.20#ibcon#[25=USB\r\n] 2006.201.05:32:28.20#ibcon#*before write, iclass 32, count 0 2006.201.05:32:28.20#ibcon#enter sib2, iclass 32, count 0 2006.201.05:32:28.20#ibcon#flushed, iclass 32, count 0 2006.201.05:32:28.20#ibcon#about to write, iclass 32, count 0 2006.201.05:32:28.20#ibcon#wrote, iclass 32, count 0 2006.201.05:32:28.20#ibcon#about to read 3, iclass 32, count 0 2006.201.05:32:28.23#ibcon#read 3, iclass 32, count 0 2006.201.05:32:28.23#ibcon#about to read 4, iclass 32, count 0 2006.201.05:32:28.23#ibcon#read 4, iclass 32, count 0 2006.201.05:32:28.23#ibcon#about to read 5, iclass 32, count 0 2006.201.05:32:28.23#ibcon#read 5, iclass 32, count 0 2006.201.05:32:28.23#ibcon#about to read 6, iclass 32, count 0 2006.201.05:32:28.23#ibcon#read 6, iclass 32, count 0 2006.201.05:32:28.23#ibcon#end of sib2, iclass 32, count 0 2006.201.05:32:28.23#ibcon#*after write, iclass 32, count 0 2006.201.05:32:28.23#ibcon#*before return 0, iclass 32, count 0 2006.201.05:32:28.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:28.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:28.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.05:32:28.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.05:32:28.23$vck44/valo=4,624.99 2006.201.05:32:28.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.05:32:28.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.05:32:28.23#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:28.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:28.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:28.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:28.23#ibcon#enter wrdev, iclass 34, count 0 2006.201.05:32:28.23#ibcon#first serial, iclass 34, count 0 2006.201.05:32:28.23#ibcon#enter sib2, iclass 34, count 0 2006.201.05:32:28.23#ibcon#flushed, iclass 34, count 0 2006.201.05:32:28.23#ibcon#about to write, iclass 34, count 0 2006.201.05:32:28.23#ibcon#wrote, iclass 34, count 0 2006.201.05:32:28.23#ibcon#about to read 3, iclass 34, count 0 2006.201.05:32:28.25#ibcon#read 3, iclass 34, count 0 2006.201.05:32:28.25#ibcon#about to read 4, iclass 34, count 0 2006.201.05:32:28.25#ibcon#read 4, iclass 34, count 0 2006.201.05:32:28.25#ibcon#about to read 5, iclass 34, count 0 2006.201.05:32:28.25#ibcon#read 5, iclass 34, count 0 2006.201.05:32:28.25#ibcon#about to read 6, iclass 34, count 0 2006.201.05:32:28.25#ibcon#read 6, iclass 34, count 0 2006.201.05:32:28.25#ibcon#end of sib2, iclass 34, count 0 2006.201.05:32:28.25#ibcon#*mode == 0, iclass 34, count 0 2006.201.05:32:28.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.05:32:28.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:32:28.25#ibcon#*before write, iclass 34, count 0 2006.201.05:32:28.25#ibcon#enter sib2, iclass 34, count 0 2006.201.05:32:28.25#ibcon#flushed, iclass 34, count 0 2006.201.05:32:28.25#ibcon#about to write, iclass 34, count 0 2006.201.05:32:28.25#ibcon#wrote, iclass 34, count 0 2006.201.05:32:28.25#ibcon#about to read 3, iclass 34, count 0 2006.201.05:32:28.29#ibcon#read 3, iclass 34, count 0 2006.201.05:32:28.29#ibcon#about to read 4, iclass 34, count 0 2006.201.05:32:28.29#ibcon#read 4, iclass 34, count 0 2006.201.05:32:28.29#ibcon#about to read 5, iclass 34, count 0 2006.201.05:32:28.29#ibcon#read 5, iclass 34, count 0 2006.201.05:32:28.29#ibcon#about to read 6, iclass 34, count 0 2006.201.05:32:28.29#ibcon#read 6, iclass 34, count 0 2006.201.05:32:28.29#ibcon#end of sib2, iclass 34, count 0 2006.201.05:32:28.29#ibcon#*after write, iclass 34, count 0 2006.201.05:32:28.29#ibcon#*before return 0, iclass 34, count 0 2006.201.05:32:28.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:28.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:28.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.05:32:28.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.05:32:28.29$vck44/va=4,7 2006.201.05:32:28.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.05:32:28.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.05:32:28.29#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:28.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:28.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:28.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:28.35#ibcon#enter wrdev, iclass 36, count 2 2006.201.05:32:28.35#ibcon#first serial, iclass 36, count 2 2006.201.05:32:28.35#ibcon#enter sib2, iclass 36, count 2 2006.201.05:32:28.35#ibcon#flushed, iclass 36, count 2 2006.201.05:32:28.35#ibcon#about to write, iclass 36, count 2 2006.201.05:32:28.35#ibcon#wrote, iclass 36, count 2 2006.201.05:32:28.35#ibcon#about to read 3, iclass 36, count 2 2006.201.05:32:28.37#ibcon#read 3, iclass 36, count 2 2006.201.05:32:28.37#ibcon#about to read 4, iclass 36, count 2 2006.201.05:32:28.37#ibcon#read 4, iclass 36, count 2 2006.201.05:32:28.37#ibcon#about to read 5, iclass 36, count 2 2006.201.05:32:28.37#ibcon#read 5, iclass 36, count 2 2006.201.05:32:28.37#ibcon#about to read 6, iclass 36, count 2 2006.201.05:32:28.37#ibcon#read 6, iclass 36, count 2 2006.201.05:32:28.37#ibcon#end of sib2, iclass 36, count 2 2006.201.05:32:28.37#ibcon#*mode == 0, iclass 36, count 2 2006.201.05:32:28.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.05:32:28.37#ibcon#[25=AT04-07\r\n] 2006.201.05:32:28.37#ibcon#*before write, iclass 36, count 2 2006.201.05:32:28.37#ibcon#enter sib2, iclass 36, count 2 2006.201.05:32:28.37#ibcon#flushed, iclass 36, count 2 2006.201.05:32:28.37#ibcon#about to write, iclass 36, count 2 2006.201.05:32:28.37#ibcon#wrote, iclass 36, count 2 2006.201.05:32:28.37#ibcon#about to read 3, iclass 36, count 2 2006.201.05:32:28.40#ibcon#read 3, iclass 36, count 2 2006.201.05:32:28.40#ibcon#about to read 4, iclass 36, count 2 2006.201.05:32:28.40#ibcon#read 4, iclass 36, count 2 2006.201.05:32:28.40#ibcon#about to read 5, iclass 36, count 2 2006.201.05:32:28.40#ibcon#read 5, iclass 36, count 2 2006.201.05:32:28.40#ibcon#about to read 6, iclass 36, count 2 2006.201.05:32:28.40#ibcon#read 6, iclass 36, count 2 2006.201.05:32:28.40#ibcon#end of sib2, iclass 36, count 2 2006.201.05:32:28.40#ibcon#*after write, iclass 36, count 2 2006.201.05:32:28.40#ibcon#*before return 0, iclass 36, count 2 2006.201.05:32:28.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:28.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:28.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.05:32:28.40#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:28.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:28.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:28.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:28.52#ibcon#enter wrdev, iclass 36, count 0 2006.201.05:32:28.52#ibcon#first serial, iclass 36, count 0 2006.201.05:32:28.52#ibcon#enter sib2, iclass 36, count 0 2006.201.05:32:28.52#ibcon#flushed, iclass 36, count 0 2006.201.05:32:28.52#ibcon#about to write, iclass 36, count 0 2006.201.05:32:28.52#ibcon#wrote, iclass 36, count 0 2006.201.05:32:28.52#ibcon#about to read 3, iclass 36, count 0 2006.201.05:32:28.54#ibcon#read 3, iclass 36, count 0 2006.201.05:32:28.54#ibcon#about to read 4, iclass 36, count 0 2006.201.05:32:28.54#ibcon#read 4, iclass 36, count 0 2006.201.05:32:28.54#ibcon#about to read 5, iclass 36, count 0 2006.201.05:32:28.54#ibcon#read 5, iclass 36, count 0 2006.201.05:32:28.54#ibcon#about to read 6, iclass 36, count 0 2006.201.05:32:28.54#ibcon#read 6, iclass 36, count 0 2006.201.05:32:28.54#ibcon#end of sib2, iclass 36, count 0 2006.201.05:32:28.54#ibcon#*mode == 0, iclass 36, count 0 2006.201.05:32:28.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.05:32:28.54#ibcon#[25=USB\r\n] 2006.201.05:32:28.54#ibcon#*before write, iclass 36, count 0 2006.201.05:32:28.54#ibcon#enter sib2, iclass 36, count 0 2006.201.05:32:28.54#ibcon#flushed, iclass 36, count 0 2006.201.05:32:28.54#ibcon#about to write, iclass 36, count 0 2006.201.05:32:28.54#ibcon#wrote, iclass 36, count 0 2006.201.05:32:28.54#ibcon#about to read 3, iclass 36, count 0 2006.201.05:32:28.57#ibcon#read 3, iclass 36, count 0 2006.201.05:32:28.57#ibcon#about to read 4, iclass 36, count 0 2006.201.05:32:28.57#ibcon#read 4, iclass 36, count 0 2006.201.05:32:28.57#ibcon#about to read 5, iclass 36, count 0 2006.201.05:32:28.57#ibcon#read 5, iclass 36, count 0 2006.201.05:32:28.57#ibcon#about to read 6, iclass 36, count 0 2006.201.05:32:28.57#ibcon#read 6, iclass 36, count 0 2006.201.05:32:28.57#ibcon#end of sib2, iclass 36, count 0 2006.201.05:32:28.57#ibcon#*after write, iclass 36, count 0 2006.201.05:32:28.57#ibcon#*before return 0, iclass 36, count 0 2006.201.05:32:28.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:28.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:28.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.05:32:28.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.05:32:28.57$vck44/valo=5,734.99 2006.201.05:32:28.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.05:32:28.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.05:32:28.57#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:28.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:29.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:29.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:29.13#ibcon#enter wrdev, iclass 38, count 0 2006.201.05:32:29.13#ibcon#first serial, iclass 38, count 0 2006.201.05:32:29.13#ibcon#enter sib2, iclass 38, count 0 2006.201.05:32:29.13#ibcon#flushed, iclass 38, count 0 2006.201.05:32:29.13#ibcon#about to write, iclass 38, count 0 2006.201.05:32:29.13#ibcon#wrote, iclass 38, count 0 2006.201.05:32:29.13#ibcon#about to read 3, iclass 38, count 0 2006.201.05:32:29.15#ibcon#read 3, iclass 38, count 0 2006.201.05:32:29.15#ibcon#about to read 4, iclass 38, count 0 2006.201.05:32:29.15#ibcon#read 4, iclass 38, count 0 2006.201.05:32:29.15#ibcon#about to read 5, iclass 38, count 0 2006.201.05:32:29.15#ibcon#read 5, iclass 38, count 0 2006.201.05:32:29.15#ibcon#about to read 6, iclass 38, count 0 2006.201.05:32:29.15#ibcon#read 6, iclass 38, count 0 2006.201.05:32:29.15#ibcon#end of sib2, iclass 38, count 0 2006.201.05:32:29.15#ibcon#*mode == 0, iclass 38, count 0 2006.201.05:32:29.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.05:32:29.15#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:32:29.15#ibcon#*before write, iclass 38, count 0 2006.201.05:32:29.15#ibcon#enter sib2, iclass 38, count 0 2006.201.05:32:29.15#ibcon#flushed, iclass 38, count 0 2006.201.05:32:29.15#ibcon#about to write, iclass 38, count 0 2006.201.05:32:29.15#ibcon#wrote, iclass 38, count 0 2006.201.05:32:29.15#ibcon#about to read 3, iclass 38, count 0 2006.201.05:32:29.19#ibcon#read 3, iclass 38, count 0 2006.201.05:32:29.19#ibcon#about to read 4, iclass 38, count 0 2006.201.05:32:29.19#ibcon#read 4, iclass 38, count 0 2006.201.05:32:29.19#ibcon#about to read 5, iclass 38, count 0 2006.201.05:32:29.19#ibcon#read 5, iclass 38, count 0 2006.201.05:32:29.19#ibcon#about to read 6, iclass 38, count 0 2006.201.05:32:29.19#ibcon#read 6, iclass 38, count 0 2006.201.05:32:29.19#ibcon#end of sib2, iclass 38, count 0 2006.201.05:32:29.19#ibcon#*after write, iclass 38, count 0 2006.201.05:32:29.19#ibcon#*before return 0, iclass 38, count 0 2006.201.05:32:29.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:29.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:29.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.05:32:29.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.05:32:29.19$vck44/va=5,4 2006.201.05:32:29.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.05:32:29.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.05:32:29.19#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:29.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:29.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:29.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:29.19#ibcon#enter wrdev, iclass 40, count 2 2006.201.05:32:29.19#ibcon#first serial, iclass 40, count 2 2006.201.05:32:29.19#ibcon#enter sib2, iclass 40, count 2 2006.201.05:32:29.19#ibcon#flushed, iclass 40, count 2 2006.201.05:32:29.19#ibcon#about to write, iclass 40, count 2 2006.201.05:32:29.19#ibcon#wrote, iclass 40, count 2 2006.201.05:32:29.19#ibcon#about to read 3, iclass 40, count 2 2006.201.05:32:29.21#ibcon#read 3, iclass 40, count 2 2006.201.05:32:29.21#ibcon#about to read 4, iclass 40, count 2 2006.201.05:32:29.21#ibcon#read 4, iclass 40, count 2 2006.201.05:32:29.21#ibcon#about to read 5, iclass 40, count 2 2006.201.05:32:29.21#ibcon#read 5, iclass 40, count 2 2006.201.05:32:29.21#ibcon#about to read 6, iclass 40, count 2 2006.201.05:32:29.21#ibcon#read 6, iclass 40, count 2 2006.201.05:32:29.21#ibcon#end of sib2, iclass 40, count 2 2006.201.05:32:29.21#ibcon#*mode == 0, iclass 40, count 2 2006.201.05:32:29.21#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.05:32:29.21#ibcon#[25=AT05-04\r\n] 2006.201.05:32:29.21#ibcon#*before write, iclass 40, count 2 2006.201.05:32:29.21#ibcon#enter sib2, iclass 40, count 2 2006.201.05:32:29.21#ibcon#flushed, iclass 40, count 2 2006.201.05:32:29.21#ibcon#about to write, iclass 40, count 2 2006.201.05:32:29.21#ibcon#wrote, iclass 40, count 2 2006.201.05:32:29.21#ibcon#about to read 3, iclass 40, count 2 2006.201.05:32:29.24#ibcon#read 3, iclass 40, count 2 2006.201.05:32:29.24#ibcon#about to read 4, iclass 40, count 2 2006.201.05:32:29.24#ibcon#read 4, iclass 40, count 2 2006.201.05:32:29.24#ibcon#about to read 5, iclass 40, count 2 2006.201.05:32:29.24#ibcon#read 5, iclass 40, count 2 2006.201.05:32:29.24#ibcon#about to read 6, iclass 40, count 2 2006.201.05:32:29.24#ibcon#read 6, iclass 40, count 2 2006.201.05:32:29.24#ibcon#end of sib2, iclass 40, count 2 2006.201.05:32:29.24#ibcon#*after write, iclass 40, count 2 2006.201.05:32:29.24#ibcon#*before return 0, iclass 40, count 2 2006.201.05:32:29.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:29.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:29.24#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.05:32:29.24#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:29.24#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:29.36#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:29.36#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:29.36#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:32:29.36#ibcon#first serial, iclass 40, count 0 2006.201.05:32:29.36#ibcon#enter sib2, iclass 40, count 0 2006.201.05:32:29.36#ibcon#flushed, iclass 40, count 0 2006.201.05:32:29.36#ibcon#about to write, iclass 40, count 0 2006.201.05:32:29.36#ibcon#wrote, iclass 40, count 0 2006.201.05:32:29.36#ibcon#about to read 3, iclass 40, count 0 2006.201.05:32:29.38#ibcon#read 3, iclass 40, count 0 2006.201.05:32:29.38#ibcon#about to read 4, iclass 40, count 0 2006.201.05:32:29.38#ibcon#read 4, iclass 40, count 0 2006.201.05:32:29.38#ibcon#about to read 5, iclass 40, count 0 2006.201.05:32:29.38#ibcon#read 5, iclass 40, count 0 2006.201.05:32:29.38#ibcon#about to read 6, iclass 40, count 0 2006.201.05:32:29.38#ibcon#read 6, iclass 40, count 0 2006.201.05:32:29.38#ibcon#end of sib2, iclass 40, count 0 2006.201.05:32:29.38#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:32:29.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:32:29.38#ibcon#[25=USB\r\n] 2006.201.05:32:29.38#ibcon#*before write, iclass 40, count 0 2006.201.05:32:29.38#ibcon#enter sib2, iclass 40, count 0 2006.201.05:32:29.38#ibcon#flushed, iclass 40, count 0 2006.201.05:32:29.38#ibcon#about to write, iclass 40, count 0 2006.201.05:32:29.38#ibcon#wrote, iclass 40, count 0 2006.201.05:32:29.38#ibcon#about to read 3, iclass 40, count 0 2006.201.05:32:29.41#ibcon#read 3, iclass 40, count 0 2006.201.05:32:29.41#ibcon#about to read 4, iclass 40, count 0 2006.201.05:32:29.41#ibcon#read 4, iclass 40, count 0 2006.201.05:32:29.41#ibcon#about to read 5, iclass 40, count 0 2006.201.05:32:29.41#ibcon#read 5, iclass 40, count 0 2006.201.05:32:29.41#ibcon#about to read 6, iclass 40, count 0 2006.201.05:32:29.41#ibcon#read 6, iclass 40, count 0 2006.201.05:32:29.41#ibcon#end of sib2, iclass 40, count 0 2006.201.05:32:29.41#ibcon#*after write, iclass 40, count 0 2006.201.05:32:29.41#ibcon#*before return 0, iclass 40, count 0 2006.201.05:32:29.41#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:29.41#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:29.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:32:29.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:32:29.41$vck44/valo=6,814.99 2006.201.05:32:29.41#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.05:32:29.41#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.05:32:29.41#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:29.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:29.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:29.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:29.41#ibcon#enter wrdev, iclass 4, count 0 2006.201.05:32:29.41#ibcon#first serial, iclass 4, count 0 2006.201.05:32:29.41#ibcon#enter sib2, iclass 4, count 0 2006.201.05:32:29.41#ibcon#flushed, iclass 4, count 0 2006.201.05:32:29.41#ibcon#about to write, iclass 4, count 0 2006.201.05:32:29.41#ibcon#wrote, iclass 4, count 0 2006.201.05:32:29.41#ibcon#about to read 3, iclass 4, count 0 2006.201.05:32:29.43#ibcon#read 3, iclass 4, count 0 2006.201.05:32:29.43#ibcon#about to read 4, iclass 4, count 0 2006.201.05:32:29.43#ibcon#read 4, iclass 4, count 0 2006.201.05:32:29.43#ibcon#about to read 5, iclass 4, count 0 2006.201.05:32:29.43#ibcon#read 5, iclass 4, count 0 2006.201.05:32:29.43#ibcon#about to read 6, iclass 4, count 0 2006.201.05:32:29.43#ibcon#read 6, iclass 4, count 0 2006.201.05:32:29.43#ibcon#end of sib2, iclass 4, count 0 2006.201.05:32:29.43#ibcon#*mode == 0, iclass 4, count 0 2006.201.05:32:29.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.05:32:29.43#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:32:29.43#ibcon#*before write, iclass 4, count 0 2006.201.05:32:29.43#ibcon#enter sib2, iclass 4, count 0 2006.201.05:32:29.43#ibcon#flushed, iclass 4, count 0 2006.201.05:32:29.43#ibcon#about to write, iclass 4, count 0 2006.201.05:32:29.43#ibcon#wrote, iclass 4, count 0 2006.201.05:32:29.43#ibcon#about to read 3, iclass 4, count 0 2006.201.05:32:29.47#ibcon#read 3, iclass 4, count 0 2006.201.05:32:29.47#ibcon#about to read 4, iclass 4, count 0 2006.201.05:32:29.47#ibcon#read 4, iclass 4, count 0 2006.201.05:32:29.47#ibcon#about to read 5, iclass 4, count 0 2006.201.05:32:29.47#ibcon#read 5, iclass 4, count 0 2006.201.05:32:29.47#ibcon#about to read 6, iclass 4, count 0 2006.201.05:32:29.47#ibcon#read 6, iclass 4, count 0 2006.201.05:32:29.47#ibcon#end of sib2, iclass 4, count 0 2006.201.05:32:29.47#ibcon#*after write, iclass 4, count 0 2006.201.05:32:29.47#ibcon#*before return 0, iclass 4, count 0 2006.201.05:32:29.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:29.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:29.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.05:32:29.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.05:32:29.47$vck44/va=6,5 2006.201.05:32:29.47#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.05:32:29.47#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.05:32:29.47#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:29.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:29.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:29.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:29.53#ibcon#enter wrdev, iclass 6, count 2 2006.201.05:32:29.53#ibcon#first serial, iclass 6, count 2 2006.201.05:32:29.53#ibcon#enter sib2, iclass 6, count 2 2006.201.05:32:29.53#ibcon#flushed, iclass 6, count 2 2006.201.05:32:29.53#ibcon#about to write, iclass 6, count 2 2006.201.05:32:29.53#ibcon#wrote, iclass 6, count 2 2006.201.05:32:29.53#ibcon#about to read 3, iclass 6, count 2 2006.201.05:32:29.55#ibcon#read 3, iclass 6, count 2 2006.201.05:32:29.55#ibcon#about to read 4, iclass 6, count 2 2006.201.05:32:29.55#ibcon#read 4, iclass 6, count 2 2006.201.05:32:29.55#ibcon#about to read 5, iclass 6, count 2 2006.201.05:32:29.55#ibcon#read 5, iclass 6, count 2 2006.201.05:32:29.55#ibcon#about to read 6, iclass 6, count 2 2006.201.05:32:29.55#ibcon#read 6, iclass 6, count 2 2006.201.05:32:29.55#ibcon#end of sib2, iclass 6, count 2 2006.201.05:32:29.55#ibcon#*mode == 0, iclass 6, count 2 2006.201.05:32:29.55#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.05:32:29.55#ibcon#[25=AT06-05\r\n] 2006.201.05:32:29.55#ibcon#*before write, iclass 6, count 2 2006.201.05:32:29.55#ibcon#enter sib2, iclass 6, count 2 2006.201.05:32:29.55#ibcon#flushed, iclass 6, count 2 2006.201.05:32:29.55#ibcon#about to write, iclass 6, count 2 2006.201.05:32:29.55#ibcon#wrote, iclass 6, count 2 2006.201.05:32:29.55#ibcon#about to read 3, iclass 6, count 2 2006.201.05:32:29.58#ibcon#read 3, iclass 6, count 2 2006.201.05:32:29.58#ibcon#about to read 4, iclass 6, count 2 2006.201.05:32:29.58#ibcon#read 4, iclass 6, count 2 2006.201.05:32:29.58#ibcon#about to read 5, iclass 6, count 2 2006.201.05:32:29.58#ibcon#read 5, iclass 6, count 2 2006.201.05:32:29.58#ibcon#about to read 6, iclass 6, count 2 2006.201.05:32:29.58#ibcon#read 6, iclass 6, count 2 2006.201.05:32:29.58#ibcon#end of sib2, iclass 6, count 2 2006.201.05:32:29.58#ibcon#*after write, iclass 6, count 2 2006.201.05:32:29.58#ibcon#*before return 0, iclass 6, count 2 2006.201.05:32:29.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:29.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:29.58#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.05:32:29.58#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:29.58#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:29.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:29.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:29.70#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:32:29.70#ibcon#first serial, iclass 6, count 0 2006.201.05:32:29.70#ibcon#enter sib2, iclass 6, count 0 2006.201.05:32:29.70#ibcon#flushed, iclass 6, count 0 2006.201.05:32:29.70#ibcon#about to write, iclass 6, count 0 2006.201.05:32:29.70#ibcon#wrote, iclass 6, count 0 2006.201.05:32:29.70#ibcon#about to read 3, iclass 6, count 0 2006.201.05:32:29.72#ibcon#read 3, iclass 6, count 0 2006.201.05:32:29.72#ibcon#about to read 4, iclass 6, count 0 2006.201.05:32:29.72#ibcon#read 4, iclass 6, count 0 2006.201.05:32:29.72#ibcon#about to read 5, iclass 6, count 0 2006.201.05:32:29.72#ibcon#read 5, iclass 6, count 0 2006.201.05:32:29.72#ibcon#about to read 6, iclass 6, count 0 2006.201.05:32:29.72#ibcon#read 6, iclass 6, count 0 2006.201.05:32:29.72#ibcon#end of sib2, iclass 6, count 0 2006.201.05:32:29.72#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:32:29.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:32:29.72#ibcon#[25=USB\r\n] 2006.201.05:32:29.72#ibcon#*before write, iclass 6, count 0 2006.201.05:32:29.72#ibcon#enter sib2, iclass 6, count 0 2006.201.05:32:29.72#ibcon#flushed, iclass 6, count 0 2006.201.05:32:29.72#ibcon#about to write, iclass 6, count 0 2006.201.05:32:29.72#ibcon#wrote, iclass 6, count 0 2006.201.05:32:29.72#ibcon#about to read 3, iclass 6, count 0 2006.201.05:32:29.75#ibcon#read 3, iclass 6, count 0 2006.201.05:32:29.75#ibcon#about to read 4, iclass 6, count 0 2006.201.05:32:29.75#ibcon#read 4, iclass 6, count 0 2006.201.05:32:29.75#ibcon#about to read 5, iclass 6, count 0 2006.201.05:32:29.75#ibcon#read 5, iclass 6, count 0 2006.201.05:32:29.75#ibcon#about to read 6, iclass 6, count 0 2006.201.05:32:29.75#ibcon#read 6, iclass 6, count 0 2006.201.05:32:29.75#ibcon#end of sib2, iclass 6, count 0 2006.201.05:32:29.75#ibcon#*after write, iclass 6, count 0 2006.201.05:32:29.75#ibcon#*before return 0, iclass 6, count 0 2006.201.05:32:29.75#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:29.75#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:29.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:32:29.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:32:29.75$vck44/valo=7,864.99 2006.201.05:32:29.75#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.05:32:29.75#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.05:32:29.75#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:29.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:29.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:29.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:29.75#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:32:29.75#ibcon#first serial, iclass 10, count 0 2006.201.05:32:29.75#ibcon#enter sib2, iclass 10, count 0 2006.201.05:32:29.75#ibcon#flushed, iclass 10, count 0 2006.201.05:32:29.75#ibcon#about to write, iclass 10, count 0 2006.201.05:32:29.75#ibcon#wrote, iclass 10, count 0 2006.201.05:32:29.75#ibcon#about to read 3, iclass 10, count 0 2006.201.05:32:29.77#ibcon#read 3, iclass 10, count 0 2006.201.05:32:29.77#ibcon#about to read 4, iclass 10, count 0 2006.201.05:32:29.77#ibcon#read 4, iclass 10, count 0 2006.201.05:32:29.77#ibcon#about to read 5, iclass 10, count 0 2006.201.05:32:29.77#ibcon#read 5, iclass 10, count 0 2006.201.05:32:29.77#ibcon#about to read 6, iclass 10, count 0 2006.201.05:32:29.77#ibcon#read 6, iclass 10, count 0 2006.201.05:32:29.77#ibcon#end of sib2, iclass 10, count 0 2006.201.05:32:29.77#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:32:29.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:32:29.77#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:32:29.77#ibcon#*before write, iclass 10, count 0 2006.201.05:32:29.77#ibcon#enter sib2, iclass 10, count 0 2006.201.05:32:29.77#ibcon#flushed, iclass 10, count 0 2006.201.05:32:29.77#ibcon#about to write, iclass 10, count 0 2006.201.05:32:29.77#ibcon#wrote, iclass 10, count 0 2006.201.05:32:29.77#ibcon#about to read 3, iclass 10, count 0 2006.201.05:32:29.81#ibcon#read 3, iclass 10, count 0 2006.201.05:32:29.81#ibcon#about to read 4, iclass 10, count 0 2006.201.05:32:29.81#ibcon#read 4, iclass 10, count 0 2006.201.05:32:29.81#ibcon#about to read 5, iclass 10, count 0 2006.201.05:32:29.81#ibcon#read 5, iclass 10, count 0 2006.201.05:32:29.81#ibcon#about to read 6, iclass 10, count 0 2006.201.05:32:29.81#ibcon#read 6, iclass 10, count 0 2006.201.05:32:29.81#ibcon#end of sib2, iclass 10, count 0 2006.201.05:32:29.81#ibcon#*after write, iclass 10, count 0 2006.201.05:32:29.81#ibcon#*before return 0, iclass 10, count 0 2006.201.05:32:29.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:29.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:29.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:32:29.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:32:29.81$vck44/va=7,5 2006.201.05:32:29.81#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.05:32:29.81#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.05:32:29.81#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:29.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:29.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:29.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:29.87#ibcon#enter wrdev, iclass 12, count 2 2006.201.05:32:29.87#ibcon#first serial, iclass 12, count 2 2006.201.05:32:29.87#ibcon#enter sib2, iclass 12, count 2 2006.201.05:32:29.87#ibcon#flushed, iclass 12, count 2 2006.201.05:32:29.87#ibcon#about to write, iclass 12, count 2 2006.201.05:32:29.87#ibcon#wrote, iclass 12, count 2 2006.201.05:32:29.87#ibcon#about to read 3, iclass 12, count 2 2006.201.05:32:29.89#ibcon#read 3, iclass 12, count 2 2006.201.05:32:29.89#ibcon#about to read 4, iclass 12, count 2 2006.201.05:32:29.89#ibcon#read 4, iclass 12, count 2 2006.201.05:32:29.89#ibcon#about to read 5, iclass 12, count 2 2006.201.05:32:29.89#ibcon#read 5, iclass 12, count 2 2006.201.05:32:29.89#ibcon#about to read 6, iclass 12, count 2 2006.201.05:32:29.89#ibcon#read 6, iclass 12, count 2 2006.201.05:32:29.89#ibcon#end of sib2, iclass 12, count 2 2006.201.05:32:29.89#ibcon#*mode == 0, iclass 12, count 2 2006.201.05:32:29.89#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.05:32:29.89#ibcon#[25=AT07-05\r\n] 2006.201.05:32:29.89#ibcon#*before write, iclass 12, count 2 2006.201.05:32:29.89#ibcon#enter sib2, iclass 12, count 2 2006.201.05:32:29.89#ibcon#flushed, iclass 12, count 2 2006.201.05:32:29.89#ibcon#about to write, iclass 12, count 2 2006.201.05:32:29.89#ibcon#wrote, iclass 12, count 2 2006.201.05:32:29.89#ibcon#about to read 3, iclass 12, count 2 2006.201.05:32:29.92#ibcon#read 3, iclass 12, count 2 2006.201.05:32:29.92#ibcon#about to read 4, iclass 12, count 2 2006.201.05:32:29.92#ibcon#read 4, iclass 12, count 2 2006.201.05:32:29.92#ibcon#about to read 5, iclass 12, count 2 2006.201.05:32:29.92#ibcon#read 5, iclass 12, count 2 2006.201.05:32:29.92#ibcon#about to read 6, iclass 12, count 2 2006.201.05:32:29.92#ibcon#read 6, iclass 12, count 2 2006.201.05:32:29.92#ibcon#end of sib2, iclass 12, count 2 2006.201.05:32:29.92#ibcon#*after write, iclass 12, count 2 2006.201.05:32:29.92#ibcon#*before return 0, iclass 12, count 2 2006.201.05:32:29.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:29.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:29.92#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.05:32:29.92#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:29.92#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:30.04#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:30.04#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:30.04#ibcon#enter wrdev, iclass 12, count 0 2006.201.05:32:30.04#ibcon#first serial, iclass 12, count 0 2006.201.05:32:30.04#ibcon#enter sib2, iclass 12, count 0 2006.201.05:32:30.04#ibcon#flushed, iclass 12, count 0 2006.201.05:32:30.04#ibcon#about to write, iclass 12, count 0 2006.201.05:32:30.04#ibcon#wrote, iclass 12, count 0 2006.201.05:32:30.04#ibcon#about to read 3, iclass 12, count 0 2006.201.05:32:30.06#ibcon#read 3, iclass 12, count 0 2006.201.05:32:30.06#ibcon#about to read 4, iclass 12, count 0 2006.201.05:32:30.06#ibcon#read 4, iclass 12, count 0 2006.201.05:32:30.06#ibcon#about to read 5, iclass 12, count 0 2006.201.05:32:30.06#ibcon#read 5, iclass 12, count 0 2006.201.05:32:30.06#ibcon#about to read 6, iclass 12, count 0 2006.201.05:32:30.06#ibcon#read 6, iclass 12, count 0 2006.201.05:32:30.06#ibcon#end of sib2, iclass 12, count 0 2006.201.05:32:30.06#ibcon#*mode == 0, iclass 12, count 0 2006.201.05:32:30.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.05:32:30.06#ibcon#[25=USB\r\n] 2006.201.05:32:30.06#ibcon#*before write, iclass 12, count 0 2006.201.05:32:30.06#ibcon#enter sib2, iclass 12, count 0 2006.201.05:32:30.06#ibcon#flushed, iclass 12, count 0 2006.201.05:32:30.06#ibcon#about to write, iclass 12, count 0 2006.201.05:32:30.06#ibcon#wrote, iclass 12, count 0 2006.201.05:32:30.06#ibcon#about to read 3, iclass 12, count 0 2006.201.05:32:30.09#ibcon#read 3, iclass 12, count 0 2006.201.05:32:30.09#ibcon#about to read 4, iclass 12, count 0 2006.201.05:32:30.09#ibcon#read 4, iclass 12, count 0 2006.201.05:32:30.09#ibcon#about to read 5, iclass 12, count 0 2006.201.05:32:30.09#ibcon#read 5, iclass 12, count 0 2006.201.05:32:30.09#ibcon#about to read 6, iclass 12, count 0 2006.201.05:32:30.09#ibcon#read 6, iclass 12, count 0 2006.201.05:32:30.09#ibcon#end of sib2, iclass 12, count 0 2006.201.05:32:30.09#ibcon#*after write, iclass 12, count 0 2006.201.05:32:30.09#ibcon#*before return 0, iclass 12, count 0 2006.201.05:32:30.09#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:30.09#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:30.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.05:32:30.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.05:32:30.09$vck44/valo=8,884.99 2006.201.05:32:30.09#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.05:32:30.09#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.05:32:30.09#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:30.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:30.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:30.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:30.09#ibcon#enter wrdev, iclass 14, count 0 2006.201.05:32:30.09#ibcon#first serial, iclass 14, count 0 2006.201.05:32:30.09#ibcon#enter sib2, iclass 14, count 0 2006.201.05:32:30.09#ibcon#flushed, iclass 14, count 0 2006.201.05:32:30.09#ibcon#about to write, iclass 14, count 0 2006.201.05:32:30.09#ibcon#wrote, iclass 14, count 0 2006.201.05:32:30.09#ibcon#about to read 3, iclass 14, count 0 2006.201.05:32:30.11#ibcon#read 3, iclass 14, count 0 2006.201.05:32:30.11#ibcon#about to read 4, iclass 14, count 0 2006.201.05:32:30.11#ibcon#read 4, iclass 14, count 0 2006.201.05:32:30.11#ibcon#about to read 5, iclass 14, count 0 2006.201.05:32:30.11#ibcon#read 5, iclass 14, count 0 2006.201.05:32:30.11#ibcon#about to read 6, iclass 14, count 0 2006.201.05:32:30.11#ibcon#read 6, iclass 14, count 0 2006.201.05:32:30.11#ibcon#end of sib2, iclass 14, count 0 2006.201.05:32:30.11#ibcon#*mode == 0, iclass 14, count 0 2006.201.05:32:30.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.05:32:30.11#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:32:30.11#ibcon#*before write, iclass 14, count 0 2006.201.05:32:30.11#ibcon#enter sib2, iclass 14, count 0 2006.201.05:32:30.11#ibcon#flushed, iclass 14, count 0 2006.201.05:32:30.11#ibcon#about to write, iclass 14, count 0 2006.201.05:32:30.11#ibcon#wrote, iclass 14, count 0 2006.201.05:32:30.11#ibcon#about to read 3, iclass 14, count 0 2006.201.05:32:30.15#ibcon#read 3, iclass 14, count 0 2006.201.05:32:30.15#ibcon#about to read 4, iclass 14, count 0 2006.201.05:32:30.15#ibcon#read 4, iclass 14, count 0 2006.201.05:32:30.15#ibcon#about to read 5, iclass 14, count 0 2006.201.05:32:30.15#ibcon#read 5, iclass 14, count 0 2006.201.05:32:30.15#ibcon#about to read 6, iclass 14, count 0 2006.201.05:32:30.15#ibcon#read 6, iclass 14, count 0 2006.201.05:32:30.15#ibcon#end of sib2, iclass 14, count 0 2006.201.05:32:30.15#ibcon#*after write, iclass 14, count 0 2006.201.05:32:30.15#ibcon#*before return 0, iclass 14, count 0 2006.201.05:32:30.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:30.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:30.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.05:32:30.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.05:32:30.15$vck44/va=8,4 2006.201.05:32:30.15#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.05:32:30.15#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.05:32:30.15#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:30.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:32:30.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:32:30.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:32:30.21#ibcon#enter wrdev, iclass 16, count 2 2006.201.05:32:30.21#ibcon#first serial, iclass 16, count 2 2006.201.05:32:30.21#ibcon#enter sib2, iclass 16, count 2 2006.201.05:32:30.21#ibcon#flushed, iclass 16, count 2 2006.201.05:32:30.21#ibcon#about to write, iclass 16, count 2 2006.201.05:32:30.21#ibcon#wrote, iclass 16, count 2 2006.201.05:32:30.21#ibcon#about to read 3, iclass 16, count 2 2006.201.05:32:30.23#ibcon#read 3, iclass 16, count 2 2006.201.05:32:30.23#ibcon#about to read 4, iclass 16, count 2 2006.201.05:32:30.23#ibcon#read 4, iclass 16, count 2 2006.201.05:32:30.23#ibcon#about to read 5, iclass 16, count 2 2006.201.05:32:30.23#ibcon#read 5, iclass 16, count 2 2006.201.05:32:30.23#ibcon#about to read 6, iclass 16, count 2 2006.201.05:32:30.23#ibcon#read 6, iclass 16, count 2 2006.201.05:32:30.23#ibcon#end of sib2, iclass 16, count 2 2006.201.05:32:30.23#ibcon#*mode == 0, iclass 16, count 2 2006.201.05:32:30.23#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.05:32:30.23#ibcon#[25=AT08-04\r\n] 2006.201.05:32:30.23#ibcon#*before write, iclass 16, count 2 2006.201.05:32:30.23#ibcon#enter sib2, iclass 16, count 2 2006.201.05:32:30.23#ibcon#flushed, iclass 16, count 2 2006.201.05:32:30.23#ibcon#about to write, iclass 16, count 2 2006.201.05:32:30.23#ibcon#wrote, iclass 16, count 2 2006.201.05:32:30.23#ibcon#about to read 3, iclass 16, count 2 2006.201.05:32:30.26#ibcon#read 3, iclass 16, count 2 2006.201.05:32:30.26#ibcon#about to read 4, iclass 16, count 2 2006.201.05:32:30.26#ibcon#read 4, iclass 16, count 2 2006.201.05:32:30.26#ibcon#about to read 5, iclass 16, count 2 2006.201.05:32:30.26#ibcon#read 5, iclass 16, count 2 2006.201.05:32:30.26#ibcon#about to read 6, iclass 16, count 2 2006.201.05:32:30.26#ibcon#read 6, iclass 16, count 2 2006.201.05:32:30.26#ibcon#end of sib2, iclass 16, count 2 2006.201.05:32:30.26#ibcon#*after write, iclass 16, count 2 2006.201.05:32:30.26#ibcon#*before return 0, iclass 16, count 2 2006.201.05:32:30.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:32:30.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:32:30.26#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.05:32:30.26#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:30.26#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:32:30.38#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:32:30.38#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:32:30.38#ibcon#enter wrdev, iclass 16, count 0 2006.201.05:32:30.38#ibcon#first serial, iclass 16, count 0 2006.201.05:32:30.38#ibcon#enter sib2, iclass 16, count 0 2006.201.05:32:30.38#ibcon#flushed, iclass 16, count 0 2006.201.05:32:30.38#ibcon#about to write, iclass 16, count 0 2006.201.05:32:30.38#ibcon#wrote, iclass 16, count 0 2006.201.05:32:30.38#ibcon#about to read 3, iclass 16, count 0 2006.201.05:32:30.40#ibcon#read 3, iclass 16, count 0 2006.201.05:32:30.40#ibcon#about to read 4, iclass 16, count 0 2006.201.05:32:30.40#ibcon#read 4, iclass 16, count 0 2006.201.05:32:30.40#ibcon#about to read 5, iclass 16, count 0 2006.201.05:32:30.40#ibcon#read 5, iclass 16, count 0 2006.201.05:32:30.40#ibcon#about to read 6, iclass 16, count 0 2006.201.05:32:30.40#ibcon#read 6, iclass 16, count 0 2006.201.05:32:30.40#ibcon#end of sib2, iclass 16, count 0 2006.201.05:32:30.40#ibcon#*mode == 0, iclass 16, count 0 2006.201.05:32:30.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.05:32:30.40#ibcon#[25=USB\r\n] 2006.201.05:32:30.40#ibcon#*before write, iclass 16, count 0 2006.201.05:32:30.40#ibcon#enter sib2, iclass 16, count 0 2006.201.05:32:30.40#ibcon#flushed, iclass 16, count 0 2006.201.05:32:30.40#ibcon#about to write, iclass 16, count 0 2006.201.05:32:30.40#ibcon#wrote, iclass 16, count 0 2006.201.05:32:30.40#ibcon#about to read 3, iclass 16, count 0 2006.201.05:32:30.43#ibcon#read 3, iclass 16, count 0 2006.201.05:32:30.43#ibcon#about to read 4, iclass 16, count 0 2006.201.05:32:30.43#ibcon#read 4, iclass 16, count 0 2006.201.05:32:30.43#ibcon#about to read 5, iclass 16, count 0 2006.201.05:32:30.43#ibcon#read 5, iclass 16, count 0 2006.201.05:32:30.43#ibcon#about to read 6, iclass 16, count 0 2006.201.05:32:30.43#ibcon#read 6, iclass 16, count 0 2006.201.05:32:30.43#ibcon#end of sib2, iclass 16, count 0 2006.201.05:32:30.43#ibcon#*after write, iclass 16, count 0 2006.201.05:32:30.43#ibcon#*before return 0, iclass 16, count 0 2006.201.05:32:30.43#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:32:30.43#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:32:30.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.05:32:30.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.05:32:30.43$vck44/vblo=1,629.99 2006.201.05:32:30.43#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.05:32:30.43#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.05:32:30.43#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:30.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:32:30.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:32:30.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:32:30.43#ibcon#enter wrdev, iclass 18, count 0 2006.201.05:32:30.43#ibcon#first serial, iclass 18, count 0 2006.201.05:32:30.43#ibcon#enter sib2, iclass 18, count 0 2006.201.05:32:30.43#ibcon#flushed, iclass 18, count 0 2006.201.05:32:30.43#ibcon#about to write, iclass 18, count 0 2006.201.05:32:30.43#ibcon#wrote, iclass 18, count 0 2006.201.05:32:30.43#ibcon#about to read 3, iclass 18, count 0 2006.201.05:32:30.45#ibcon#read 3, iclass 18, count 0 2006.201.05:32:30.45#ibcon#about to read 4, iclass 18, count 0 2006.201.05:32:30.45#ibcon#read 4, iclass 18, count 0 2006.201.05:32:30.45#ibcon#about to read 5, iclass 18, count 0 2006.201.05:32:30.45#ibcon#read 5, iclass 18, count 0 2006.201.05:32:30.45#ibcon#about to read 6, iclass 18, count 0 2006.201.05:32:30.45#ibcon#read 6, iclass 18, count 0 2006.201.05:32:30.45#ibcon#end of sib2, iclass 18, count 0 2006.201.05:32:30.45#ibcon#*mode == 0, iclass 18, count 0 2006.201.05:32:30.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.05:32:30.45#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:32:30.45#ibcon#*before write, iclass 18, count 0 2006.201.05:32:30.45#ibcon#enter sib2, iclass 18, count 0 2006.201.05:32:30.45#ibcon#flushed, iclass 18, count 0 2006.201.05:32:30.45#ibcon#about to write, iclass 18, count 0 2006.201.05:32:30.45#ibcon#wrote, iclass 18, count 0 2006.201.05:32:30.45#ibcon#about to read 3, iclass 18, count 0 2006.201.05:32:30.49#ibcon#read 3, iclass 18, count 0 2006.201.05:32:30.49#ibcon#about to read 4, iclass 18, count 0 2006.201.05:32:30.49#ibcon#read 4, iclass 18, count 0 2006.201.05:32:30.49#ibcon#about to read 5, iclass 18, count 0 2006.201.05:32:30.49#ibcon#read 5, iclass 18, count 0 2006.201.05:32:30.49#ibcon#about to read 6, iclass 18, count 0 2006.201.05:32:30.49#ibcon#read 6, iclass 18, count 0 2006.201.05:32:30.49#ibcon#end of sib2, iclass 18, count 0 2006.201.05:32:30.49#ibcon#*after write, iclass 18, count 0 2006.201.05:32:30.49#ibcon#*before return 0, iclass 18, count 0 2006.201.05:32:30.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:32:30.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:32:30.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.05:32:30.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.05:32:30.49$vck44/vb=1,4 2006.201.05:32:30.49#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.05:32:30.49#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.05:32:30.49#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:30.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:32:30.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:32:30.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:32:30.49#ibcon#enter wrdev, iclass 20, count 2 2006.201.05:32:30.49#ibcon#first serial, iclass 20, count 2 2006.201.05:32:30.49#ibcon#enter sib2, iclass 20, count 2 2006.201.05:32:30.49#ibcon#flushed, iclass 20, count 2 2006.201.05:32:30.49#ibcon#about to write, iclass 20, count 2 2006.201.05:32:30.49#ibcon#wrote, iclass 20, count 2 2006.201.05:32:30.49#ibcon#about to read 3, iclass 20, count 2 2006.201.05:32:30.51#ibcon#read 3, iclass 20, count 2 2006.201.05:32:30.51#ibcon#about to read 4, iclass 20, count 2 2006.201.05:32:30.51#ibcon#read 4, iclass 20, count 2 2006.201.05:32:30.51#ibcon#about to read 5, iclass 20, count 2 2006.201.05:32:30.51#ibcon#read 5, iclass 20, count 2 2006.201.05:32:30.51#ibcon#about to read 6, iclass 20, count 2 2006.201.05:32:30.51#ibcon#read 6, iclass 20, count 2 2006.201.05:32:30.51#ibcon#end of sib2, iclass 20, count 2 2006.201.05:32:30.51#ibcon#*mode == 0, iclass 20, count 2 2006.201.05:32:30.51#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.05:32:30.51#ibcon#[27=AT01-04\r\n] 2006.201.05:32:30.51#ibcon#*before write, iclass 20, count 2 2006.201.05:32:30.51#ibcon#enter sib2, iclass 20, count 2 2006.201.05:32:30.51#ibcon#flushed, iclass 20, count 2 2006.201.05:32:30.51#ibcon#about to write, iclass 20, count 2 2006.201.05:32:30.51#ibcon#wrote, iclass 20, count 2 2006.201.05:32:30.51#ibcon#about to read 3, iclass 20, count 2 2006.201.05:32:30.54#ibcon#read 3, iclass 20, count 2 2006.201.05:32:30.54#ibcon#about to read 4, iclass 20, count 2 2006.201.05:32:30.54#ibcon#read 4, iclass 20, count 2 2006.201.05:32:30.54#ibcon#about to read 5, iclass 20, count 2 2006.201.05:32:30.54#ibcon#read 5, iclass 20, count 2 2006.201.05:32:30.54#ibcon#about to read 6, iclass 20, count 2 2006.201.05:32:30.54#ibcon#read 6, iclass 20, count 2 2006.201.05:32:30.54#ibcon#end of sib2, iclass 20, count 2 2006.201.05:32:30.54#ibcon#*after write, iclass 20, count 2 2006.201.05:32:30.54#ibcon#*before return 0, iclass 20, count 2 2006.201.05:32:30.54#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:32:30.54#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:32:30.54#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.05:32:30.54#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:30.54#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:32:30.66#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:32:30.66#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:32:30.66#ibcon#enter wrdev, iclass 20, count 0 2006.201.05:32:30.66#ibcon#first serial, iclass 20, count 0 2006.201.05:32:30.66#ibcon#enter sib2, iclass 20, count 0 2006.201.05:32:30.66#ibcon#flushed, iclass 20, count 0 2006.201.05:32:30.66#ibcon#about to write, iclass 20, count 0 2006.201.05:32:30.66#ibcon#wrote, iclass 20, count 0 2006.201.05:32:30.66#ibcon#about to read 3, iclass 20, count 0 2006.201.05:32:30.68#ibcon#read 3, iclass 20, count 0 2006.201.05:32:30.68#ibcon#about to read 4, iclass 20, count 0 2006.201.05:32:30.68#ibcon#read 4, iclass 20, count 0 2006.201.05:32:30.68#ibcon#about to read 5, iclass 20, count 0 2006.201.05:32:30.68#ibcon#read 5, iclass 20, count 0 2006.201.05:32:30.68#ibcon#about to read 6, iclass 20, count 0 2006.201.05:32:30.68#ibcon#read 6, iclass 20, count 0 2006.201.05:32:30.68#ibcon#end of sib2, iclass 20, count 0 2006.201.05:32:30.68#ibcon#*mode == 0, iclass 20, count 0 2006.201.05:32:30.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.05:32:30.68#ibcon#[27=USB\r\n] 2006.201.05:32:30.68#ibcon#*before write, iclass 20, count 0 2006.201.05:32:30.68#ibcon#enter sib2, iclass 20, count 0 2006.201.05:32:30.68#ibcon#flushed, iclass 20, count 0 2006.201.05:32:30.68#ibcon#about to write, iclass 20, count 0 2006.201.05:32:30.68#ibcon#wrote, iclass 20, count 0 2006.201.05:32:30.68#ibcon#about to read 3, iclass 20, count 0 2006.201.05:32:30.71#ibcon#read 3, iclass 20, count 0 2006.201.05:32:30.71#ibcon#about to read 4, iclass 20, count 0 2006.201.05:32:30.71#ibcon#read 4, iclass 20, count 0 2006.201.05:32:30.71#ibcon#about to read 5, iclass 20, count 0 2006.201.05:32:30.71#ibcon#read 5, iclass 20, count 0 2006.201.05:32:30.71#ibcon#about to read 6, iclass 20, count 0 2006.201.05:32:30.71#ibcon#read 6, iclass 20, count 0 2006.201.05:32:30.71#ibcon#end of sib2, iclass 20, count 0 2006.201.05:32:30.71#ibcon#*after write, iclass 20, count 0 2006.201.05:32:30.71#ibcon#*before return 0, iclass 20, count 0 2006.201.05:32:30.71#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:32:30.71#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:32:30.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.05:32:30.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.05:32:30.71$vck44/vblo=2,634.99 2006.201.05:32:30.71#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.05:32:30.71#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.05:32:30.71#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:30.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:30.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:30.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:30.71#ibcon#enter wrdev, iclass 22, count 0 2006.201.05:32:30.71#ibcon#first serial, iclass 22, count 0 2006.201.05:32:30.71#ibcon#enter sib2, iclass 22, count 0 2006.201.05:32:30.71#ibcon#flushed, iclass 22, count 0 2006.201.05:32:30.71#ibcon#about to write, iclass 22, count 0 2006.201.05:32:30.71#ibcon#wrote, iclass 22, count 0 2006.201.05:32:30.71#ibcon#about to read 3, iclass 22, count 0 2006.201.05:32:30.73#ibcon#read 3, iclass 22, count 0 2006.201.05:32:30.73#ibcon#about to read 4, iclass 22, count 0 2006.201.05:32:30.73#ibcon#read 4, iclass 22, count 0 2006.201.05:32:30.73#ibcon#about to read 5, iclass 22, count 0 2006.201.05:32:30.73#ibcon#read 5, iclass 22, count 0 2006.201.05:32:30.73#ibcon#about to read 6, iclass 22, count 0 2006.201.05:32:30.73#ibcon#read 6, iclass 22, count 0 2006.201.05:32:30.73#ibcon#end of sib2, iclass 22, count 0 2006.201.05:32:30.73#ibcon#*mode == 0, iclass 22, count 0 2006.201.05:32:30.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.05:32:30.73#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:32:30.73#ibcon#*before write, iclass 22, count 0 2006.201.05:32:30.73#ibcon#enter sib2, iclass 22, count 0 2006.201.05:32:30.73#ibcon#flushed, iclass 22, count 0 2006.201.05:32:30.73#ibcon#about to write, iclass 22, count 0 2006.201.05:32:30.73#ibcon#wrote, iclass 22, count 0 2006.201.05:32:30.73#ibcon#about to read 3, iclass 22, count 0 2006.201.05:32:30.77#ibcon#read 3, iclass 22, count 0 2006.201.05:32:30.77#ibcon#about to read 4, iclass 22, count 0 2006.201.05:32:30.77#ibcon#read 4, iclass 22, count 0 2006.201.05:32:30.77#ibcon#about to read 5, iclass 22, count 0 2006.201.05:32:30.77#ibcon#read 5, iclass 22, count 0 2006.201.05:32:30.77#ibcon#about to read 6, iclass 22, count 0 2006.201.05:32:30.77#ibcon#read 6, iclass 22, count 0 2006.201.05:32:30.77#ibcon#end of sib2, iclass 22, count 0 2006.201.05:32:30.77#ibcon#*after write, iclass 22, count 0 2006.201.05:32:30.77#ibcon#*before return 0, iclass 22, count 0 2006.201.05:32:30.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:30.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:32:30.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.05:32:30.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.05:32:30.77$vck44/vb=2,5 2006.201.05:32:30.77#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.05:32:30.77#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.05:32:30.77#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:30.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:30.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:30.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:30.83#ibcon#enter wrdev, iclass 24, count 2 2006.201.05:32:30.83#ibcon#first serial, iclass 24, count 2 2006.201.05:32:30.83#ibcon#enter sib2, iclass 24, count 2 2006.201.05:32:30.83#ibcon#flushed, iclass 24, count 2 2006.201.05:32:30.83#ibcon#about to write, iclass 24, count 2 2006.201.05:32:30.83#ibcon#wrote, iclass 24, count 2 2006.201.05:32:30.83#ibcon#about to read 3, iclass 24, count 2 2006.201.05:32:30.85#ibcon#read 3, iclass 24, count 2 2006.201.05:32:30.85#ibcon#about to read 4, iclass 24, count 2 2006.201.05:32:30.85#ibcon#read 4, iclass 24, count 2 2006.201.05:32:30.85#ibcon#about to read 5, iclass 24, count 2 2006.201.05:32:30.85#ibcon#read 5, iclass 24, count 2 2006.201.05:32:30.85#ibcon#about to read 6, iclass 24, count 2 2006.201.05:32:30.85#ibcon#read 6, iclass 24, count 2 2006.201.05:32:30.85#ibcon#end of sib2, iclass 24, count 2 2006.201.05:32:30.85#ibcon#*mode == 0, iclass 24, count 2 2006.201.05:32:30.85#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.05:32:30.85#ibcon#[27=AT02-05\r\n] 2006.201.05:32:30.85#ibcon#*before write, iclass 24, count 2 2006.201.05:32:30.85#ibcon#enter sib2, iclass 24, count 2 2006.201.05:32:30.85#ibcon#flushed, iclass 24, count 2 2006.201.05:32:30.85#ibcon#about to write, iclass 24, count 2 2006.201.05:32:30.85#ibcon#wrote, iclass 24, count 2 2006.201.05:32:30.85#ibcon#about to read 3, iclass 24, count 2 2006.201.05:32:30.88#ibcon#read 3, iclass 24, count 2 2006.201.05:32:30.88#ibcon#about to read 4, iclass 24, count 2 2006.201.05:32:30.88#ibcon#read 4, iclass 24, count 2 2006.201.05:32:30.88#ibcon#about to read 5, iclass 24, count 2 2006.201.05:32:30.88#ibcon#read 5, iclass 24, count 2 2006.201.05:32:30.88#ibcon#about to read 6, iclass 24, count 2 2006.201.05:32:30.88#ibcon#read 6, iclass 24, count 2 2006.201.05:32:30.88#ibcon#end of sib2, iclass 24, count 2 2006.201.05:32:30.88#ibcon#*after write, iclass 24, count 2 2006.201.05:32:30.88#ibcon#*before return 0, iclass 24, count 2 2006.201.05:32:30.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:30.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:32:30.88#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.05:32:30.88#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:30.88#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:31.00#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:31.00#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:31.00#ibcon#enter wrdev, iclass 24, count 0 2006.201.05:32:31.00#ibcon#first serial, iclass 24, count 0 2006.201.05:32:31.00#ibcon#enter sib2, iclass 24, count 0 2006.201.05:32:31.00#ibcon#flushed, iclass 24, count 0 2006.201.05:32:31.00#ibcon#about to write, iclass 24, count 0 2006.201.05:32:31.00#ibcon#wrote, iclass 24, count 0 2006.201.05:32:31.00#ibcon#about to read 3, iclass 24, count 0 2006.201.05:32:31.02#ibcon#read 3, iclass 24, count 0 2006.201.05:32:31.02#ibcon#about to read 4, iclass 24, count 0 2006.201.05:32:31.02#ibcon#read 4, iclass 24, count 0 2006.201.05:32:31.02#ibcon#about to read 5, iclass 24, count 0 2006.201.05:32:31.02#ibcon#read 5, iclass 24, count 0 2006.201.05:32:31.02#ibcon#about to read 6, iclass 24, count 0 2006.201.05:32:31.02#ibcon#read 6, iclass 24, count 0 2006.201.05:32:31.02#ibcon#end of sib2, iclass 24, count 0 2006.201.05:32:31.02#ibcon#*mode == 0, iclass 24, count 0 2006.201.05:32:31.02#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.05:32:31.02#ibcon#[27=USB\r\n] 2006.201.05:32:31.02#ibcon#*before write, iclass 24, count 0 2006.201.05:32:31.02#ibcon#enter sib2, iclass 24, count 0 2006.201.05:32:31.02#ibcon#flushed, iclass 24, count 0 2006.201.05:32:31.02#ibcon#about to write, iclass 24, count 0 2006.201.05:32:31.02#ibcon#wrote, iclass 24, count 0 2006.201.05:32:31.02#ibcon#about to read 3, iclass 24, count 0 2006.201.05:32:31.05#ibcon#read 3, iclass 24, count 0 2006.201.05:32:31.05#ibcon#about to read 4, iclass 24, count 0 2006.201.05:32:31.05#ibcon#read 4, iclass 24, count 0 2006.201.05:32:31.05#ibcon#about to read 5, iclass 24, count 0 2006.201.05:32:31.05#ibcon#read 5, iclass 24, count 0 2006.201.05:32:31.05#ibcon#about to read 6, iclass 24, count 0 2006.201.05:32:31.05#ibcon#read 6, iclass 24, count 0 2006.201.05:32:31.05#ibcon#end of sib2, iclass 24, count 0 2006.201.05:32:31.05#ibcon#*after write, iclass 24, count 0 2006.201.05:32:31.05#ibcon#*before return 0, iclass 24, count 0 2006.201.05:32:31.05#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:31.05#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:32:31.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.05:32:31.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.05:32:31.05$vck44/vblo=3,649.99 2006.201.05:32:31.05#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.05:32:31.05#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.05:32:31.05#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:31.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:31.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:31.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:31.05#ibcon#enter wrdev, iclass 26, count 0 2006.201.05:32:31.05#ibcon#first serial, iclass 26, count 0 2006.201.05:32:31.05#ibcon#enter sib2, iclass 26, count 0 2006.201.05:32:31.05#ibcon#flushed, iclass 26, count 0 2006.201.05:32:31.05#ibcon#about to write, iclass 26, count 0 2006.201.05:32:31.05#ibcon#wrote, iclass 26, count 0 2006.201.05:32:31.05#ibcon#about to read 3, iclass 26, count 0 2006.201.05:32:31.07#ibcon#read 3, iclass 26, count 0 2006.201.05:32:31.07#ibcon#about to read 4, iclass 26, count 0 2006.201.05:32:31.07#ibcon#read 4, iclass 26, count 0 2006.201.05:32:31.07#ibcon#about to read 5, iclass 26, count 0 2006.201.05:32:31.07#ibcon#read 5, iclass 26, count 0 2006.201.05:32:31.07#ibcon#about to read 6, iclass 26, count 0 2006.201.05:32:31.07#ibcon#read 6, iclass 26, count 0 2006.201.05:32:31.07#ibcon#end of sib2, iclass 26, count 0 2006.201.05:32:31.07#ibcon#*mode == 0, iclass 26, count 0 2006.201.05:32:31.07#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.05:32:31.07#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:32:31.07#ibcon#*before write, iclass 26, count 0 2006.201.05:32:31.07#ibcon#enter sib2, iclass 26, count 0 2006.201.05:32:31.07#ibcon#flushed, iclass 26, count 0 2006.201.05:32:31.07#ibcon#about to write, iclass 26, count 0 2006.201.05:32:31.07#ibcon#wrote, iclass 26, count 0 2006.201.05:32:31.07#ibcon#about to read 3, iclass 26, count 0 2006.201.05:32:31.11#ibcon#read 3, iclass 26, count 0 2006.201.05:32:31.11#ibcon#about to read 4, iclass 26, count 0 2006.201.05:32:31.11#ibcon#read 4, iclass 26, count 0 2006.201.05:32:31.11#ibcon#about to read 5, iclass 26, count 0 2006.201.05:32:31.11#ibcon#read 5, iclass 26, count 0 2006.201.05:32:31.11#ibcon#about to read 6, iclass 26, count 0 2006.201.05:32:31.11#ibcon#read 6, iclass 26, count 0 2006.201.05:32:31.11#ibcon#end of sib2, iclass 26, count 0 2006.201.05:32:31.11#ibcon#*after write, iclass 26, count 0 2006.201.05:32:31.11#ibcon#*before return 0, iclass 26, count 0 2006.201.05:32:31.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:31.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:32:31.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.05:32:31.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.05:32:31.11$vck44/vb=3,4 2006.201.05:32:31.11#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.05:32:31.11#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.05:32:31.11#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:31.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:31.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:31.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:31.17#ibcon#enter wrdev, iclass 28, count 2 2006.201.05:32:31.17#ibcon#first serial, iclass 28, count 2 2006.201.05:32:31.17#ibcon#enter sib2, iclass 28, count 2 2006.201.05:32:31.17#ibcon#flushed, iclass 28, count 2 2006.201.05:32:31.17#ibcon#about to write, iclass 28, count 2 2006.201.05:32:31.17#ibcon#wrote, iclass 28, count 2 2006.201.05:32:31.17#ibcon#about to read 3, iclass 28, count 2 2006.201.05:32:31.19#ibcon#read 3, iclass 28, count 2 2006.201.05:32:31.19#ibcon#about to read 4, iclass 28, count 2 2006.201.05:32:31.19#ibcon#read 4, iclass 28, count 2 2006.201.05:32:31.19#ibcon#about to read 5, iclass 28, count 2 2006.201.05:32:31.19#ibcon#read 5, iclass 28, count 2 2006.201.05:32:31.19#ibcon#about to read 6, iclass 28, count 2 2006.201.05:32:31.19#ibcon#read 6, iclass 28, count 2 2006.201.05:32:31.19#ibcon#end of sib2, iclass 28, count 2 2006.201.05:32:31.19#ibcon#*mode == 0, iclass 28, count 2 2006.201.05:32:31.19#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.05:32:31.19#ibcon#[27=AT03-04\r\n] 2006.201.05:32:31.19#ibcon#*before write, iclass 28, count 2 2006.201.05:32:31.19#ibcon#enter sib2, iclass 28, count 2 2006.201.05:32:31.19#ibcon#flushed, iclass 28, count 2 2006.201.05:32:31.19#ibcon#about to write, iclass 28, count 2 2006.201.05:32:31.19#ibcon#wrote, iclass 28, count 2 2006.201.05:32:31.19#ibcon#about to read 3, iclass 28, count 2 2006.201.05:32:31.22#ibcon#read 3, iclass 28, count 2 2006.201.05:32:31.28#ibcon#about to read 4, iclass 28, count 2 2006.201.05:32:31.28#ibcon#read 4, iclass 28, count 2 2006.201.05:32:31.28#ibcon#about to read 5, iclass 28, count 2 2006.201.05:32:31.28#ibcon#read 5, iclass 28, count 2 2006.201.05:32:31.28#ibcon#about to read 6, iclass 28, count 2 2006.201.05:32:31.28#ibcon#read 6, iclass 28, count 2 2006.201.05:32:31.28#ibcon#end of sib2, iclass 28, count 2 2006.201.05:32:31.28#ibcon#*after write, iclass 28, count 2 2006.201.05:32:31.28#ibcon#*before return 0, iclass 28, count 2 2006.201.05:32:31.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:31.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:32:31.28#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.05:32:31.28#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:31.28#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:31.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:31.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:31.40#ibcon#enter wrdev, iclass 28, count 0 2006.201.05:32:31.40#ibcon#first serial, iclass 28, count 0 2006.201.05:32:31.40#ibcon#enter sib2, iclass 28, count 0 2006.201.05:32:31.40#ibcon#flushed, iclass 28, count 0 2006.201.05:32:31.40#ibcon#about to write, iclass 28, count 0 2006.201.05:32:31.40#ibcon#wrote, iclass 28, count 0 2006.201.05:32:31.40#ibcon#about to read 3, iclass 28, count 0 2006.201.05:32:31.42#ibcon#read 3, iclass 28, count 0 2006.201.05:32:31.42#ibcon#about to read 4, iclass 28, count 0 2006.201.05:32:31.42#ibcon#read 4, iclass 28, count 0 2006.201.05:32:31.42#ibcon#about to read 5, iclass 28, count 0 2006.201.05:32:31.42#ibcon#read 5, iclass 28, count 0 2006.201.05:32:31.42#ibcon#about to read 6, iclass 28, count 0 2006.201.05:32:31.42#ibcon#read 6, iclass 28, count 0 2006.201.05:32:31.42#ibcon#end of sib2, iclass 28, count 0 2006.201.05:32:31.42#ibcon#*mode == 0, iclass 28, count 0 2006.201.05:32:31.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.05:32:31.42#ibcon#[27=USB\r\n] 2006.201.05:32:31.42#ibcon#*before write, iclass 28, count 0 2006.201.05:32:31.42#ibcon#enter sib2, iclass 28, count 0 2006.201.05:32:31.42#ibcon#flushed, iclass 28, count 0 2006.201.05:32:31.42#ibcon#about to write, iclass 28, count 0 2006.201.05:32:31.42#ibcon#wrote, iclass 28, count 0 2006.201.05:32:31.42#ibcon#about to read 3, iclass 28, count 0 2006.201.05:32:31.45#ibcon#read 3, iclass 28, count 0 2006.201.05:32:31.45#ibcon#about to read 4, iclass 28, count 0 2006.201.05:32:31.45#ibcon#read 4, iclass 28, count 0 2006.201.05:32:31.45#ibcon#about to read 5, iclass 28, count 0 2006.201.05:32:31.45#ibcon#read 5, iclass 28, count 0 2006.201.05:32:31.45#ibcon#about to read 6, iclass 28, count 0 2006.201.05:32:31.45#ibcon#read 6, iclass 28, count 0 2006.201.05:32:31.45#ibcon#end of sib2, iclass 28, count 0 2006.201.05:32:31.45#ibcon#*after write, iclass 28, count 0 2006.201.05:32:31.45#ibcon#*before return 0, iclass 28, count 0 2006.201.05:32:31.45#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:31.45#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:32:31.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.05:32:31.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.05:32:31.45$vck44/vblo=4,679.99 2006.201.05:32:31.45#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.05:32:31.45#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.05:32:31.45#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:31.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:31.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:31.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:31.45#ibcon#enter wrdev, iclass 30, count 0 2006.201.05:32:31.45#ibcon#first serial, iclass 30, count 0 2006.201.05:32:31.45#ibcon#enter sib2, iclass 30, count 0 2006.201.05:32:31.45#ibcon#flushed, iclass 30, count 0 2006.201.05:32:31.45#ibcon#about to write, iclass 30, count 0 2006.201.05:32:31.45#ibcon#wrote, iclass 30, count 0 2006.201.05:32:31.45#ibcon#about to read 3, iclass 30, count 0 2006.201.05:32:31.47#ibcon#read 3, iclass 30, count 0 2006.201.05:32:31.47#ibcon#about to read 4, iclass 30, count 0 2006.201.05:32:31.47#ibcon#read 4, iclass 30, count 0 2006.201.05:32:31.47#ibcon#about to read 5, iclass 30, count 0 2006.201.05:32:31.47#ibcon#read 5, iclass 30, count 0 2006.201.05:32:31.47#ibcon#about to read 6, iclass 30, count 0 2006.201.05:32:31.47#ibcon#read 6, iclass 30, count 0 2006.201.05:32:31.47#ibcon#end of sib2, iclass 30, count 0 2006.201.05:32:31.47#ibcon#*mode == 0, iclass 30, count 0 2006.201.05:32:31.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.05:32:31.47#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:32:31.47#ibcon#*before write, iclass 30, count 0 2006.201.05:32:31.47#ibcon#enter sib2, iclass 30, count 0 2006.201.05:32:31.47#ibcon#flushed, iclass 30, count 0 2006.201.05:32:31.47#ibcon#about to write, iclass 30, count 0 2006.201.05:32:31.47#ibcon#wrote, iclass 30, count 0 2006.201.05:32:31.47#ibcon#about to read 3, iclass 30, count 0 2006.201.05:32:31.51#ibcon#read 3, iclass 30, count 0 2006.201.05:32:31.51#ibcon#about to read 4, iclass 30, count 0 2006.201.05:32:31.51#ibcon#read 4, iclass 30, count 0 2006.201.05:32:31.51#ibcon#about to read 5, iclass 30, count 0 2006.201.05:32:31.51#ibcon#read 5, iclass 30, count 0 2006.201.05:32:31.51#ibcon#about to read 6, iclass 30, count 0 2006.201.05:32:31.51#ibcon#read 6, iclass 30, count 0 2006.201.05:32:31.51#ibcon#end of sib2, iclass 30, count 0 2006.201.05:32:31.51#ibcon#*after write, iclass 30, count 0 2006.201.05:32:31.51#ibcon#*before return 0, iclass 30, count 0 2006.201.05:32:31.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:31.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:32:31.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.05:32:31.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.05:32:31.51$vck44/vb=4,5 2006.201.05:32:31.51#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.05:32:31.51#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.05:32:31.51#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:31.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:31.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:31.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:31.57#ibcon#enter wrdev, iclass 32, count 2 2006.201.05:32:31.57#ibcon#first serial, iclass 32, count 2 2006.201.05:32:31.57#ibcon#enter sib2, iclass 32, count 2 2006.201.05:32:31.57#ibcon#flushed, iclass 32, count 2 2006.201.05:32:31.57#ibcon#about to write, iclass 32, count 2 2006.201.05:32:31.57#ibcon#wrote, iclass 32, count 2 2006.201.05:32:31.57#ibcon#about to read 3, iclass 32, count 2 2006.201.05:32:31.59#ibcon#read 3, iclass 32, count 2 2006.201.05:32:31.59#ibcon#about to read 4, iclass 32, count 2 2006.201.05:32:31.59#ibcon#read 4, iclass 32, count 2 2006.201.05:32:31.59#ibcon#about to read 5, iclass 32, count 2 2006.201.05:32:31.59#ibcon#read 5, iclass 32, count 2 2006.201.05:32:31.59#ibcon#about to read 6, iclass 32, count 2 2006.201.05:32:31.59#ibcon#read 6, iclass 32, count 2 2006.201.05:32:31.59#ibcon#end of sib2, iclass 32, count 2 2006.201.05:32:31.59#ibcon#*mode == 0, iclass 32, count 2 2006.201.05:32:31.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.05:32:31.59#ibcon#[27=AT04-05\r\n] 2006.201.05:32:31.59#ibcon#*before write, iclass 32, count 2 2006.201.05:32:31.59#ibcon#enter sib2, iclass 32, count 2 2006.201.05:32:31.59#ibcon#flushed, iclass 32, count 2 2006.201.05:32:31.59#ibcon#about to write, iclass 32, count 2 2006.201.05:32:31.59#ibcon#wrote, iclass 32, count 2 2006.201.05:32:31.59#ibcon#about to read 3, iclass 32, count 2 2006.201.05:32:31.62#ibcon#read 3, iclass 32, count 2 2006.201.05:32:31.62#ibcon#about to read 4, iclass 32, count 2 2006.201.05:32:31.62#ibcon#read 4, iclass 32, count 2 2006.201.05:32:31.62#ibcon#about to read 5, iclass 32, count 2 2006.201.05:32:31.62#ibcon#read 5, iclass 32, count 2 2006.201.05:32:31.62#ibcon#about to read 6, iclass 32, count 2 2006.201.05:32:31.62#ibcon#read 6, iclass 32, count 2 2006.201.05:32:31.62#ibcon#end of sib2, iclass 32, count 2 2006.201.05:32:31.62#ibcon#*after write, iclass 32, count 2 2006.201.05:32:31.62#ibcon#*before return 0, iclass 32, count 2 2006.201.05:32:31.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:31.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:32:31.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.05:32:31.62#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:31.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:31.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:31.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:31.74#ibcon#enter wrdev, iclass 32, count 0 2006.201.05:32:31.74#ibcon#first serial, iclass 32, count 0 2006.201.05:32:31.74#ibcon#enter sib2, iclass 32, count 0 2006.201.05:32:31.74#ibcon#flushed, iclass 32, count 0 2006.201.05:32:31.74#ibcon#about to write, iclass 32, count 0 2006.201.05:32:31.74#ibcon#wrote, iclass 32, count 0 2006.201.05:32:31.74#ibcon#about to read 3, iclass 32, count 0 2006.201.05:32:31.76#ibcon#read 3, iclass 32, count 0 2006.201.05:32:31.76#ibcon#about to read 4, iclass 32, count 0 2006.201.05:32:31.76#ibcon#read 4, iclass 32, count 0 2006.201.05:32:31.76#ibcon#about to read 5, iclass 32, count 0 2006.201.05:32:31.76#ibcon#read 5, iclass 32, count 0 2006.201.05:32:31.76#ibcon#about to read 6, iclass 32, count 0 2006.201.05:32:31.76#ibcon#read 6, iclass 32, count 0 2006.201.05:32:31.76#ibcon#end of sib2, iclass 32, count 0 2006.201.05:32:31.76#ibcon#*mode == 0, iclass 32, count 0 2006.201.05:32:31.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.05:32:31.76#ibcon#[27=USB\r\n] 2006.201.05:32:31.76#ibcon#*before write, iclass 32, count 0 2006.201.05:32:31.76#ibcon#enter sib2, iclass 32, count 0 2006.201.05:32:31.76#ibcon#flushed, iclass 32, count 0 2006.201.05:32:31.76#ibcon#about to write, iclass 32, count 0 2006.201.05:32:31.76#ibcon#wrote, iclass 32, count 0 2006.201.05:32:31.76#ibcon#about to read 3, iclass 32, count 0 2006.201.05:32:31.79#ibcon#read 3, iclass 32, count 0 2006.201.05:32:31.79#ibcon#about to read 4, iclass 32, count 0 2006.201.05:32:31.79#ibcon#read 4, iclass 32, count 0 2006.201.05:32:31.79#ibcon#about to read 5, iclass 32, count 0 2006.201.05:32:31.79#ibcon#read 5, iclass 32, count 0 2006.201.05:32:31.79#ibcon#about to read 6, iclass 32, count 0 2006.201.05:32:31.79#ibcon#read 6, iclass 32, count 0 2006.201.05:32:31.79#ibcon#end of sib2, iclass 32, count 0 2006.201.05:32:31.79#ibcon#*after write, iclass 32, count 0 2006.201.05:32:31.79#ibcon#*before return 0, iclass 32, count 0 2006.201.05:32:31.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:31.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:32:31.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.05:32:31.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.05:32:31.79$vck44/vblo=5,709.99 2006.201.05:32:31.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.05:32:31.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.05:32:31.79#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:31.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:31.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:31.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:31.79#ibcon#enter wrdev, iclass 34, count 0 2006.201.05:32:31.79#ibcon#first serial, iclass 34, count 0 2006.201.05:32:31.79#ibcon#enter sib2, iclass 34, count 0 2006.201.05:32:31.79#ibcon#flushed, iclass 34, count 0 2006.201.05:32:31.79#ibcon#about to write, iclass 34, count 0 2006.201.05:32:31.79#ibcon#wrote, iclass 34, count 0 2006.201.05:32:31.79#ibcon#about to read 3, iclass 34, count 0 2006.201.05:32:31.81#ibcon#read 3, iclass 34, count 0 2006.201.05:32:31.81#ibcon#about to read 4, iclass 34, count 0 2006.201.05:32:31.81#ibcon#read 4, iclass 34, count 0 2006.201.05:32:31.81#ibcon#about to read 5, iclass 34, count 0 2006.201.05:32:31.81#ibcon#read 5, iclass 34, count 0 2006.201.05:32:31.81#ibcon#about to read 6, iclass 34, count 0 2006.201.05:32:31.81#ibcon#read 6, iclass 34, count 0 2006.201.05:32:31.81#ibcon#end of sib2, iclass 34, count 0 2006.201.05:32:31.81#ibcon#*mode == 0, iclass 34, count 0 2006.201.05:32:31.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.05:32:31.81#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:32:31.81#ibcon#*before write, iclass 34, count 0 2006.201.05:32:31.81#ibcon#enter sib2, iclass 34, count 0 2006.201.05:32:31.81#ibcon#flushed, iclass 34, count 0 2006.201.05:32:31.81#ibcon#about to write, iclass 34, count 0 2006.201.05:32:31.81#ibcon#wrote, iclass 34, count 0 2006.201.05:32:31.81#ibcon#about to read 3, iclass 34, count 0 2006.201.05:32:31.85#ibcon#read 3, iclass 34, count 0 2006.201.05:32:31.85#ibcon#about to read 4, iclass 34, count 0 2006.201.05:32:31.85#ibcon#read 4, iclass 34, count 0 2006.201.05:32:31.85#ibcon#about to read 5, iclass 34, count 0 2006.201.05:32:31.85#ibcon#read 5, iclass 34, count 0 2006.201.05:32:31.85#ibcon#about to read 6, iclass 34, count 0 2006.201.05:32:31.85#ibcon#read 6, iclass 34, count 0 2006.201.05:32:31.85#ibcon#end of sib2, iclass 34, count 0 2006.201.05:32:31.85#ibcon#*after write, iclass 34, count 0 2006.201.05:32:31.85#ibcon#*before return 0, iclass 34, count 0 2006.201.05:32:31.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:31.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:32:31.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.05:32:31.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.05:32:31.85$vck44/vb=5,4 2006.201.05:32:31.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.05:32:31.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.05:32:31.85#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:31.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:31.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:31.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:31.91#ibcon#enter wrdev, iclass 36, count 2 2006.201.05:32:31.91#ibcon#first serial, iclass 36, count 2 2006.201.05:32:31.91#ibcon#enter sib2, iclass 36, count 2 2006.201.05:32:31.91#ibcon#flushed, iclass 36, count 2 2006.201.05:32:31.91#ibcon#about to write, iclass 36, count 2 2006.201.05:32:31.91#ibcon#wrote, iclass 36, count 2 2006.201.05:32:31.91#ibcon#about to read 3, iclass 36, count 2 2006.201.05:32:31.93#ibcon#read 3, iclass 36, count 2 2006.201.05:32:31.93#ibcon#about to read 4, iclass 36, count 2 2006.201.05:32:31.93#ibcon#read 4, iclass 36, count 2 2006.201.05:32:31.93#ibcon#about to read 5, iclass 36, count 2 2006.201.05:32:31.93#ibcon#read 5, iclass 36, count 2 2006.201.05:32:31.93#ibcon#about to read 6, iclass 36, count 2 2006.201.05:32:31.93#ibcon#read 6, iclass 36, count 2 2006.201.05:32:31.93#ibcon#end of sib2, iclass 36, count 2 2006.201.05:32:31.93#ibcon#*mode == 0, iclass 36, count 2 2006.201.05:32:31.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.05:32:31.93#ibcon#[27=AT05-04\r\n] 2006.201.05:32:31.93#ibcon#*before write, iclass 36, count 2 2006.201.05:32:31.93#ibcon#enter sib2, iclass 36, count 2 2006.201.05:32:31.93#ibcon#flushed, iclass 36, count 2 2006.201.05:32:31.93#ibcon#about to write, iclass 36, count 2 2006.201.05:32:31.93#ibcon#wrote, iclass 36, count 2 2006.201.05:32:31.93#ibcon#about to read 3, iclass 36, count 2 2006.201.05:32:31.96#ibcon#read 3, iclass 36, count 2 2006.201.05:32:31.96#ibcon#about to read 4, iclass 36, count 2 2006.201.05:32:31.96#ibcon#read 4, iclass 36, count 2 2006.201.05:32:31.96#ibcon#about to read 5, iclass 36, count 2 2006.201.05:32:31.96#ibcon#read 5, iclass 36, count 2 2006.201.05:32:31.96#ibcon#about to read 6, iclass 36, count 2 2006.201.05:32:31.96#ibcon#read 6, iclass 36, count 2 2006.201.05:32:31.96#ibcon#end of sib2, iclass 36, count 2 2006.201.05:32:31.96#ibcon#*after write, iclass 36, count 2 2006.201.05:32:31.96#ibcon#*before return 0, iclass 36, count 2 2006.201.05:32:31.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:31.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:32:31.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.05:32:31.96#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:31.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:32.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:32.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:32.08#ibcon#enter wrdev, iclass 36, count 0 2006.201.05:32:32.08#ibcon#first serial, iclass 36, count 0 2006.201.05:32:32.08#ibcon#enter sib2, iclass 36, count 0 2006.201.05:32:32.08#ibcon#flushed, iclass 36, count 0 2006.201.05:32:32.08#ibcon#about to write, iclass 36, count 0 2006.201.05:32:32.08#ibcon#wrote, iclass 36, count 0 2006.201.05:32:32.08#ibcon#about to read 3, iclass 36, count 0 2006.201.05:32:32.10#ibcon#read 3, iclass 36, count 0 2006.201.05:32:32.10#ibcon#about to read 4, iclass 36, count 0 2006.201.05:32:32.10#ibcon#read 4, iclass 36, count 0 2006.201.05:32:32.10#ibcon#about to read 5, iclass 36, count 0 2006.201.05:32:32.10#ibcon#read 5, iclass 36, count 0 2006.201.05:32:32.10#ibcon#about to read 6, iclass 36, count 0 2006.201.05:32:32.10#ibcon#read 6, iclass 36, count 0 2006.201.05:32:32.10#ibcon#end of sib2, iclass 36, count 0 2006.201.05:32:32.10#ibcon#*mode == 0, iclass 36, count 0 2006.201.05:32:32.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.05:32:32.10#ibcon#[27=USB\r\n] 2006.201.05:32:32.10#ibcon#*before write, iclass 36, count 0 2006.201.05:32:32.10#ibcon#enter sib2, iclass 36, count 0 2006.201.05:32:32.10#ibcon#flushed, iclass 36, count 0 2006.201.05:32:32.10#ibcon#about to write, iclass 36, count 0 2006.201.05:32:32.10#ibcon#wrote, iclass 36, count 0 2006.201.05:32:32.10#ibcon#about to read 3, iclass 36, count 0 2006.201.05:32:32.13#ibcon#read 3, iclass 36, count 0 2006.201.05:32:32.13#ibcon#about to read 4, iclass 36, count 0 2006.201.05:32:32.13#ibcon#read 4, iclass 36, count 0 2006.201.05:32:32.13#ibcon#about to read 5, iclass 36, count 0 2006.201.05:32:32.13#ibcon#read 5, iclass 36, count 0 2006.201.05:32:32.13#ibcon#about to read 6, iclass 36, count 0 2006.201.05:32:32.13#ibcon#read 6, iclass 36, count 0 2006.201.05:32:32.13#ibcon#end of sib2, iclass 36, count 0 2006.201.05:32:32.13#ibcon#*after write, iclass 36, count 0 2006.201.05:32:32.13#ibcon#*before return 0, iclass 36, count 0 2006.201.05:32:32.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:32.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:32:32.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.05:32:32.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.05:32:32.13$vck44/vblo=6,719.99 2006.201.05:32:32.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.05:32:32.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.05:32:32.13#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:32.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:32.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:32.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:32.13#ibcon#enter wrdev, iclass 38, count 0 2006.201.05:32:32.13#ibcon#first serial, iclass 38, count 0 2006.201.05:32:32.13#ibcon#enter sib2, iclass 38, count 0 2006.201.05:32:32.13#ibcon#flushed, iclass 38, count 0 2006.201.05:32:32.13#ibcon#about to write, iclass 38, count 0 2006.201.05:32:32.13#ibcon#wrote, iclass 38, count 0 2006.201.05:32:32.13#ibcon#about to read 3, iclass 38, count 0 2006.201.05:32:32.15#ibcon#read 3, iclass 38, count 0 2006.201.05:32:32.15#ibcon#about to read 4, iclass 38, count 0 2006.201.05:32:32.15#ibcon#read 4, iclass 38, count 0 2006.201.05:32:32.15#ibcon#about to read 5, iclass 38, count 0 2006.201.05:32:32.15#ibcon#read 5, iclass 38, count 0 2006.201.05:32:32.15#ibcon#about to read 6, iclass 38, count 0 2006.201.05:32:32.15#ibcon#read 6, iclass 38, count 0 2006.201.05:32:32.15#ibcon#end of sib2, iclass 38, count 0 2006.201.05:32:32.15#ibcon#*mode == 0, iclass 38, count 0 2006.201.05:32:32.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.05:32:32.15#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:32:32.15#ibcon#*before write, iclass 38, count 0 2006.201.05:32:32.15#ibcon#enter sib2, iclass 38, count 0 2006.201.05:32:32.15#ibcon#flushed, iclass 38, count 0 2006.201.05:32:32.15#ibcon#about to write, iclass 38, count 0 2006.201.05:32:32.15#ibcon#wrote, iclass 38, count 0 2006.201.05:32:32.15#ibcon#about to read 3, iclass 38, count 0 2006.201.05:32:32.19#ibcon#read 3, iclass 38, count 0 2006.201.05:32:32.19#ibcon#about to read 4, iclass 38, count 0 2006.201.05:32:32.19#ibcon#read 4, iclass 38, count 0 2006.201.05:32:32.19#ibcon#about to read 5, iclass 38, count 0 2006.201.05:32:32.19#ibcon#read 5, iclass 38, count 0 2006.201.05:32:32.19#ibcon#about to read 6, iclass 38, count 0 2006.201.05:32:32.19#ibcon#read 6, iclass 38, count 0 2006.201.05:32:32.19#ibcon#end of sib2, iclass 38, count 0 2006.201.05:32:32.19#ibcon#*after write, iclass 38, count 0 2006.201.05:32:32.19#ibcon#*before return 0, iclass 38, count 0 2006.201.05:32:32.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:32.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:32:32.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.05:32:32.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.05:32:32.19$vck44/vb=6,4 2006.201.05:32:32.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.05:32:32.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.05:32:32.19#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:32.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:32.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:32.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:32.25#ibcon#enter wrdev, iclass 40, count 2 2006.201.05:32:32.25#ibcon#first serial, iclass 40, count 2 2006.201.05:32:32.25#ibcon#enter sib2, iclass 40, count 2 2006.201.05:32:32.25#ibcon#flushed, iclass 40, count 2 2006.201.05:32:32.25#ibcon#about to write, iclass 40, count 2 2006.201.05:32:32.25#ibcon#wrote, iclass 40, count 2 2006.201.05:32:32.25#ibcon#about to read 3, iclass 40, count 2 2006.201.05:32:32.27#ibcon#read 3, iclass 40, count 2 2006.201.05:32:32.27#ibcon#about to read 4, iclass 40, count 2 2006.201.05:32:32.27#ibcon#read 4, iclass 40, count 2 2006.201.05:32:32.27#ibcon#about to read 5, iclass 40, count 2 2006.201.05:32:32.27#ibcon#read 5, iclass 40, count 2 2006.201.05:32:32.27#ibcon#about to read 6, iclass 40, count 2 2006.201.05:32:32.27#ibcon#read 6, iclass 40, count 2 2006.201.05:32:32.27#ibcon#end of sib2, iclass 40, count 2 2006.201.05:32:32.27#ibcon#*mode == 0, iclass 40, count 2 2006.201.05:32:32.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.05:32:32.27#ibcon#[27=AT06-04\r\n] 2006.201.05:32:32.27#ibcon#*before write, iclass 40, count 2 2006.201.05:32:32.27#ibcon#enter sib2, iclass 40, count 2 2006.201.05:32:32.27#ibcon#flushed, iclass 40, count 2 2006.201.05:32:32.27#ibcon#about to write, iclass 40, count 2 2006.201.05:32:32.27#ibcon#wrote, iclass 40, count 2 2006.201.05:32:32.27#ibcon#about to read 3, iclass 40, count 2 2006.201.05:32:32.30#ibcon#read 3, iclass 40, count 2 2006.201.05:32:32.30#ibcon#about to read 4, iclass 40, count 2 2006.201.05:32:32.30#ibcon#read 4, iclass 40, count 2 2006.201.05:32:32.30#ibcon#about to read 5, iclass 40, count 2 2006.201.05:32:32.30#ibcon#read 5, iclass 40, count 2 2006.201.05:32:32.30#ibcon#about to read 6, iclass 40, count 2 2006.201.05:32:32.30#ibcon#read 6, iclass 40, count 2 2006.201.05:32:32.30#ibcon#end of sib2, iclass 40, count 2 2006.201.05:32:32.30#ibcon#*after write, iclass 40, count 2 2006.201.05:32:32.34#ibcon#*before return 0, iclass 40, count 2 2006.201.05:32:32.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:32.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:32:32.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.05:32:32.34#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:32.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:32.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:32.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:32.46#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:32:32.46#ibcon#first serial, iclass 40, count 0 2006.201.05:32:32.46#ibcon#enter sib2, iclass 40, count 0 2006.201.05:32:32.46#ibcon#flushed, iclass 40, count 0 2006.201.05:32:32.46#ibcon#about to write, iclass 40, count 0 2006.201.05:32:32.46#ibcon#wrote, iclass 40, count 0 2006.201.05:32:32.46#ibcon#about to read 3, iclass 40, count 0 2006.201.05:32:32.48#ibcon#read 3, iclass 40, count 0 2006.201.05:32:32.48#ibcon#about to read 4, iclass 40, count 0 2006.201.05:32:32.48#ibcon#read 4, iclass 40, count 0 2006.201.05:32:32.48#ibcon#about to read 5, iclass 40, count 0 2006.201.05:32:32.48#ibcon#read 5, iclass 40, count 0 2006.201.05:32:32.48#ibcon#about to read 6, iclass 40, count 0 2006.201.05:32:32.48#ibcon#read 6, iclass 40, count 0 2006.201.05:32:32.48#ibcon#end of sib2, iclass 40, count 0 2006.201.05:32:32.48#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:32:32.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:32:32.48#ibcon#[27=USB\r\n] 2006.201.05:32:32.48#ibcon#*before write, iclass 40, count 0 2006.201.05:32:32.48#ibcon#enter sib2, iclass 40, count 0 2006.201.05:32:32.48#ibcon#flushed, iclass 40, count 0 2006.201.05:32:32.48#ibcon#about to write, iclass 40, count 0 2006.201.05:32:32.48#ibcon#wrote, iclass 40, count 0 2006.201.05:32:32.48#ibcon#about to read 3, iclass 40, count 0 2006.201.05:32:32.51#ibcon#read 3, iclass 40, count 0 2006.201.05:32:32.51#ibcon#about to read 4, iclass 40, count 0 2006.201.05:32:32.51#ibcon#read 4, iclass 40, count 0 2006.201.05:32:32.51#ibcon#about to read 5, iclass 40, count 0 2006.201.05:32:32.51#ibcon#read 5, iclass 40, count 0 2006.201.05:32:32.51#ibcon#about to read 6, iclass 40, count 0 2006.201.05:32:32.51#ibcon#read 6, iclass 40, count 0 2006.201.05:32:32.51#ibcon#end of sib2, iclass 40, count 0 2006.201.05:32:32.51#ibcon#*after write, iclass 40, count 0 2006.201.05:32:32.51#ibcon#*before return 0, iclass 40, count 0 2006.201.05:32:32.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:32.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:32:32.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:32:32.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:32:32.51$vck44/vblo=7,734.99 2006.201.05:32:32.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.05:32:32.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.05:32:32.51#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:32.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:32.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:32.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:32.51#ibcon#enter wrdev, iclass 4, count 0 2006.201.05:32:32.51#ibcon#first serial, iclass 4, count 0 2006.201.05:32:32.51#ibcon#enter sib2, iclass 4, count 0 2006.201.05:32:32.51#ibcon#flushed, iclass 4, count 0 2006.201.05:32:32.51#ibcon#about to write, iclass 4, count 0 2006.201.05:32:32.51#ibcon#wrote, iclass 4, count 0 2006.201.05:32:32.51#ibcon#about to read 3, iclass 4, count 0 2006.201.05:32:32.53#ibcon#read 3, iclass 4, count 0 2006.201.05:32:32.53#ibcon#about to read 4, iclass 4, count 0 2006.201.05:32:32.53#ibcon#read 4, iclass 4, count 0 2006.201.05:32:32.53#ibcon#about to read 5, iclass 4, count 0 2006.201.05:32:32.53#ibcon#read 5, iclass 4, count 0 2006.201.05:32:32.53#ibcon#about to read 6, iclass 4, count 0 2006.201.05:32:32.53#ibcon#read 6, iclass 4, count 0 2006.201.05:32:32.53#ibcon#end of sib2, iclass 4, count 0 2006.201.05:32:32.53#ibcon#*mode == 0, iclass 4, count 0 2006.201.05:32:32.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.05:32:32.53#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:32:32.53#ibcon#*before write, iclass 4, count 0 2006.201.05:32:32.53#ibcon#enter sib2, iclass 4, count 0 2006.201.05:32:32.53#ibcon#flushed, iclass 4, count 0 2006.201.05:32:32.53#ibcon#about to write, iclass 4, count 0 2006.201.05:32:32.53#ibcon#wrote, iclass 4, count 0 2006.201.05:32:32.53#ibcon#about to read 3, iclass 4, count 0 2006.201.05:32:32.57#ibcon#read 3, iclass 4, count 0 2006.201.05:32:32.57#ibcon#about to read 4, iclass 4, count 0 2006.201.05:32:32.57#ibcon#read 4, iclass 4, count 0 2006.201.05:32:32.57#ibcon#about to read 5, iclass 4, count 0 2006.201.05:32:32.57#ibcon#read 5, iclass 4, count 0 2006.201.05:32:32.57#ibcon#about to read 6, iclass 4, count 0 2006.201.05:32:32.57#ibcon#read 6, iclass 4, count 0 2006.201.05:32:32.57#ibcon#end of sib2, iclass 4, count 0 2006.201.05:32:32.57#ibcon#*after write, iclass 4, count 0 2006.201.05:32:32.57#ibcon#*before return 0, iclass 4, count 0 2006.201.05:32:32.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:32.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:32:32.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.05:32:32.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.05:32:32.57$vck44/vb=7,4 2006.201.05:32:32.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.05:32:32.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.05:32:32.57#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:32.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:32.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:32.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:32.63#ibcon#enter wrdev, iclass 6, count 2 2006.201.05:32:32.63#ibcon#first serial, iclass 6, count 2 2006.201.05:32:32.63#ibcon#enter sib2, iclass 6, count 2 2006.201.05:32:32.63#ibcon#flushed, iclass 6, count 2 2006.201.05:32:32.63#ibcon#about to write, iclass 6, count 2 2006.201.05:32:32.63#ibcon#wrote, iclass 6, count 2 2006.201.05:32:32.63#ibcon#about to read 3, iclass 6, count 2 2006.201.05:32:32.65#ibcon#read 3, iclass 6, count 2 2006.201.05:32:32.65#ibcon#about to read 4, iclass 6, count 2 2006.201.05:32:32.65#ibcon#read 4, iclass 6, count 2 2006.201.05:32:32.65#ibcon#about to read 5, iclass 6, count 2 2006.201.05:32:32.65#ibcon#read 5, iclass 6, count 2 2006.201.05:32:32.65#ibcon#about to read 6, iclass 6, count 2 2006.201.05:32:32.65#ibcon#read 6, iclass 6, count 2 2006.201.05:32:32.65#ibcon#end of sib2, iclass 6, count 2 2006.201.05:32:32.65#ibcon#*mode == 0, iclass 6, count 2 2006.201.05:32:32.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.05:32:32.65#ibcon#[27=AT07-04\r\n] 2006.201.05:32:32.65#ibcon#*before write, iclass 6, count 2 2006.201.05:32:32.65#ibcon#enter sib2, iclass 6, count 2 2006.201.05:32:32.65#ibcon#flushed, iclass 6, count 2 2006.201.05:32:32.65#ibcon#about to write, iclass 6, count 2 2006.201.05:32:32.65#ibcon#wrote, iclass 6, count 2 2006.201.05:32:32.65#ibcon#about to read 3, iclass 6, count 2 2006.201.05:32:32.68#ibcon#read 3, iclass 6, count 2 2006.201.05:32:32.68#ibcon#about to read 4, iclass 6, count 2 2006.201.05:32:32.68#ibcon#read 4, iclass 6, count 2 2006.201.05:32:32.68#ibcon#about to read 5, iclass 6, count 2 2006.201.05:32:32.68#ibcon#read 5, iclass 6, count 2 2006.201.05:32:32.68#ibcon#about to read 6, iclass 6, count 2 2006.201.05:32:32.68#ibcon#read 6, iclass 6, count 2 2006.201.05:32:32.68#ibcon#end of sib2, iclass 6, count 2 2006.201.05:32:32.68#ibcon#*after write, iclass 6, count 2 2006.201.05:32:32.68#ibcon#*before return 0, iclass 6, count 2 2006.201.05:32:32.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:32.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:32:32.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.05:32:32.68#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:32.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:32.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:32.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:32.80#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:32:32.80#ibcon#first serial, iclass 6, count 0 2006.201.05:32:32.80#ibcon#enter sib2, iclass 6, count 0 2006.201.05:32:32.80#ibcon#flushed, iclass 6, count 0 2006.201.05:32:32.80#ibcon#about to write, iclass 6, count 0 2006.201.05:32:32.80#ibcon#wrote, iclass 6, count 0 2006.201.05:32:32.80#ibcon#about to read 3, iclass 6, count 0 2006.201.05:32:32.82#ibcon#read 3, iclass 6, count 0 2006.201.05:32:32.82#ibcon#about to read 4, iclass 6, count 0 2006.201.05:32:32.82#ibcon#read 4, iclass 6, count 0 2006.201.05:32:32.82#ibcon#about to read 5, iclass 6, count 0 2006.201.05:32:32.82#ibcon#read 5, iclass 6, count 0 2006.201.05:32:32.82#ibcon#about to read 6, iclass 6, count 0 2006.201.05:32:32.82#ibcon#read 6, iclass 6, count 0 2006.201.05:32:32.82#ibcon#end of sib2, iclass 6, count 0 2006.201.05:32:32.82#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:32:32.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:32:32.82#ibcon#[27=USB\r\n] 2006.201.05:32:32.82#ibcon#*before write, iclass 6, count 0 2006.201.05:32:32.82#ibcon#enter sib2, iclass 6, count 0 2006.201.05:32:32.82#ibcon#flushed, iclass 6, count 0 2006.201.05:32:32.82#ibcon#about to write, iclass 6, count 0 2006.201.05:32:32.82#ibcon#wrote, iclass 6, count 0 2006.201.05:32:32.82#ibcon#about to read 3, iclass 6, count 0 2006.201.05:32:32.85#ibcon#read 3, iclass 6, count 0 2006.201.05:32:32.85#ibcon#about to read 4, iclass 6, count 0 2006.201.05:32:32.85#ibcon#read 4, iclass 6, count 0 2006.201.05:32:32.85#ibcon#about to read 5, iclass 6, count 0 2006.201.05:32:32.85#ibcon#read 5, iclass 6, count 0 2006.201.05:32:32.85#ibcon#about to read 6, iclass 6, count 0 2006.201.05:32:32.85#ibcon#read 6, iclass 6, count 0 2006.201.05:32:32.85#ibcon#end of sib2, iclass 6, count 0 2006.201.05:32:32.85#ibcon#*after write, iclass 6, count 0 2006.201.05:32:32.85#ibcon#*before return 0, iclass 6, count 0 2006.201.05:32:32.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:32.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:32:32.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:32:32.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:32:32.85$vck44/vblo=8,744.99 2006.201.05:32:32.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.05:32:32.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.05:32:32.85#ibcon#ireg 17 cls_cnt 0 2006.201.05:32:32.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:32.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:32.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:32.85#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:32:32.85#ibcon#first serial, iclass 10, count 0 2006.201.05:32:32.85#ibcon#enter sib2, iclass 10, count 0 2006.201.05:32:32.85#ibcon#flushed, iclass 10, count 0 2006.201.05:32:32.85#ibcon#about to write, iclass 10, count 0 2006.201.05:32:32.85#ibcon#wrote, iclass 10, count 0 2006.201.05:32:32.85#ibcon#about to read 3, iclass 10, count 0 2006.201.05:32:32.87#ibcon#read 3, iclass 10, count 0 2006.201.05:32:32.87#ibcon#about to read 4, iclass 10, count 0 2006.201.05:32:32.87#ibcon#read 4, iclass 10, count 0 2006.201.05:32:32.87#ibcon#about to read 5, iclass 10, count 0 2006.201.05:32:32.87#ibcon#read 5, iclass 10, count 0 2006.201.05:32:32.87#ibcon#about to read 6, iclass 10, count 0 2006.201.05:32:32.87#ibcon#read 6, iclass 10, count 0 2006.201.05:32:32.87#ibcon#end of sib2, iclass 10, count 0 2006.201.05:32:32.87#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:32:32.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:32:32.87#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:32:32.87#ibcon#*before write, iclass 10, count 0 2006.201.05:32:32.87#ibcon#enter sib2, iclass 10, count 0 2006.201.05:32:32.87#ibcon#flushed, iclass 10, count 0 2006.201.05:32:32.87#ibcon#about to write, iclass 10, count 0 2006.201.05:32:32.87#ibcon#wrote, iclass 10, count 0 2006.201.05:32:32.87#ibcon#about to read 3, iclass 10, count 0 2006.201.05:32:32.91#ibcon#read 3, iclass 10, count 0 2006.201.05:32:32.91#ibcon#about to read 4, iclass 10, count 0 2006.201.05:32:32.91#ibcon#read 4, iclass 10, count 0 2006.201.05:32:32.91#ibcon#about to read 5, iclass 10, count 0 2006.201.05:32:32.91#ibcon#read 5, iclass 10, count 0 2006.201.05:32:32.91#ibcon#about to read 6, iclass 10, count 0 2006.201.05:32:32.91#ibcon#read 6, iclass 10, count 0 2006.201.05:32:32.91#ibcon#end of sib2, iclass 10, count 0 2006.201.05:32:32.91#ibcon#*after write, iclass 10, count 0 2006.201.05:32:32.91#ibcon#*before return 0, iclass 10, count 0 2006.201.05:32:32.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:32.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:32:32.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:32:32.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:32:32.91$vck44/vb=8,4 2006.201.05:32:32.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.05:32:32.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.05:32:32.91#ibcon#ireg 11 cls_cnt 2 2006.201.05:32:32.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:32.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:32.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:32.97#ibcon#enter wrdev, iclass 12, count 2 2006.201.05:32:32.97#ibcon#first serial, iclass 12, count 2 2006.201.05:32:32.97#ibcon#enter sib2, iclass 12, count 2 2006.201.05:32:32.97#ibcon#flushed, iclass 12, count 2 2006.201.05:32:32.97#ibcon#about to write, iclass 12, count 2 2006.201.05:32:32.97#ibcon#wrote, iclass 12, count 2 2006.201.05:32:32.97#ibcon#about to read 3, iclass 12, count 2 2006.201.05:32:32.99#ibcon#read 3, iclass 12, count 2 2006.201.05:32:32.99#ibcon#about to read 4, iclass 12, count 2 2006.201.05:32:32.99#ibcon#read 4, iclass 12, count 2 2006.201.05:32:32.99#ibcon#about to read 5, iclass 12, count 2 2006.201.05:32:32.99#ibcon#read 5, iclass 12, count 2 2006.201.05:32:32.99#ibcon#about to read 6, iclass 12, count 2 2006.201.05:32:32.99#ibcon#read 6, iclass 12, count 2 2006.201.05:32:32.99#ibcon#end of sib2, iclass 12, count 2 2006.201.05:32:32.99#ibcon#*mode == 0, iclass 12, count 2 2006.201.05:32:32.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.05:32:32.99#ibcon#[27=AT08-04\r\n] 2006.201.05:32:32.99#ibcon#*before write, iclass 12, count 2 2006.201.05:32:32.99#ibcon#enter sib2, iclass 12, count 2 2006.201.05:32:32.99#ibcon#flushed, iclass 12, count 2 2006.201.05:32:32.99#ibcon#about to write, iclass 12, count 2 2006.201.05:32:32.99#ibcon#wrote, iclass 12, count 2 2006.201.05:32:32.99#ibcon#about to read 3, iclass 12, count 2 2006.201.05:32:33.02#ibcon#read 3, iclass 12, count 2 2006.201.05:32:33.02#ibcon#about to read 4, iclass 12, count 2 2006.201.05:32:33.02#ibcon#read 4, iclass 12, count 2 2006.201.05:32:33.02#ibcon#about to read 5, iclass 12, count 2 2006.201.05:32:33.02#ibcon#read 5, iclass 12, count 2 2006.201.05:32:33.02#ibcon#about to read 6, iclass 12, count 2 2006.201.05:32:33.02#ibcon#read 6, iclass 12, count 2 2006.201.05:32:33.02#ibcon#end of sib2, iclass 12, count 2 2006.201.05:32:33.02#ibcon#*after write, iclass 12, count 2 2006.201.05:32:33.02#ibcon#*before return 0, iclass 12, count 2 2006.201.05:32:33.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:33.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:32:33.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.05:32:33.02#ibcon#ireg 7 cls_cnt 0 2006.201.05:32:33.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:33.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:33.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:33.14#ibcon#enter wrdev, iclass 12, count 0 2006.201.05:32:33.14#ibcon#first serial, iclass 12, count 0 2006.201.05:32:33.14#ibcon#enter sib2, iclass 12, count 0 2006.201.05:32:33.14#ibcon#flushed, iclass 12, count 0 2006.201.05:32:33.14#ibcon#about to write, iclass 12, count 0 2006.201.05:32:33.14#ibcon#wrote, iclass 12, count 0 2006.201.05:32:33.14#ibcon#about to read 3, iclass 12, count 0 2006.201.05:32:33.16#ibcon#read 3, iclass 12, count 0 2006.201.05:32:33.16#ibcon#about to read 4, iclass 12, count 0 2006.201.05:32:33.16#ibcon#read 4, iclass 12, count 0 2006.201.05:32:33.16#ibcon#about to read 5, iclass 12, count 0 2006.201.05:32:33.16#ibcon#read 5, iclass 12, count 0 2006.201.05:32:33.16#ibcon#about to read 6, iclass 12, count 0 2006.201.05:32:33.16#ibcon#read 6, iclass 12, count 0 2006.201.05:32:33.16#ibcon#end of sib2, iclass 12, count 0 2006.201.05:32:33.16#ibcon#*mode == 0, iclass 12, count 0 2006.201.05:32:33.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.05:32:33.16#ibcon#[27=USB\r\n] 2006.201.05:32:33.16#ibcon#*before write, iclass 12, count 0 2006.201.05:32:33.16#ibcon#enter sib2, iclass 12, count 0 2006.201.05:32:33.16#ibcon#flushed, iclass 12, count 0 2006.201.05:32:33.16#ibcon#about to write, iclass 12, count 0 2006.201.05:32:33.16#ibcon#wrote, iclass 12, count 0 2006.201.05:32:33.16#ibcon#about to read 3, iclass 12, count 0 2006.201.05:32:33.19#ibcon#read 3, iclass 12, count 0 2006.201.05:32:33.19#ibcon#about to read 4, iclass 12, count 0 2006.201.05:32:33.19#ibcon#read 4, iclass 12, count 0 2006.201.05:32:33.19#ibcon#about to read 5, iclass 12, count 0 2006.201.05:32:33.19#ibcon#read 5, iclass 12, count 0 2006.201.05:32:33.19#ibcon#about to read 6, iclass 12, count 0 2006.201.05:32:33.19#ibcon#read 6, iclass 12, count 0 2006.201.05:32:33.19#ibcon#end of sib2, iclass 12, count 0 2006.201.05:32:33.19#ibcon#*after write, iclass 12, count 0 2006.201.05:32:33.19#ibcon#*before return 0, iclass 12, count 0 2006.201.05:32:33.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:33.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:32:33.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.05:32:33.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.05:32:33.19$vck44/vabw=wide 2006.201.05:32:33.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.05:32:33.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.05:32:33.19#ibcon#ireg 8 cls_cnt 0 2006.201.05:32:33.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:33.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:33.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:33.19#ibcon#enter wrdev, iclass 14, count 0 2006.201.05:32:33.19#ibcon#first serial, iclass 14, count 0 2006.201.05:32:33.19#ibcon#enter sib2, iclass 14, count 0 2006.201.05:32:33.19#ibcon#flushed, iclass 14, count 0 2006.201.05:32:33.19#ibcon#about to write, iclass 14, count 0 2006.201.05:32:33.19#ibcon#wrote, iclass 14, count 0 2006.201.05:32:33.19#ibcon#about to read 3, iclass 14, count 0 2006.201.05:32:33.21#ibcon#read 3, iclass 14, count 0 2006.201.05:32:33.21#ibcon#about to read 4, iclass 14, count 0 2006.201.05:32:33.21#ibcon#read 4, iclass 14, count 0 2006.201.05:32:33.21#ibcon#about to read 5, iclass 14, count 0 2006.201.05:32:33.21#ibcon#read 5, iclass 14, count 0 2006.201.05:32:33.21#ibcon#about to read 6, iclass 14, count 0 2006.201.05:32:33.21#ibcon#read 6, iclass 14, count 0 2006.201.05:32:33.21#ibcon#end of sib2, iclass 14, count 0 2006.201.05:32:33.21#ibcon#*mode == 0, iclass 14, count 0 2006.201.05:32:33.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.05:32:33.21#ibcon#[25=BW32\r\n] 2006.201.05:32:33.21#ibcon#*before write, iclass 14, count 0 2006.201.05:32:33.21#ibcon#enter sib2, iclass 14, count 0 2006.201.05:32:33.21#ibcon#flushed, iclass 14, count 0 2006.201.05:32:33.21#ibcon#about to write, iclass 14, count 0 2006.201.05:32:33.21#ibcon#wrote, iclass 14, count 0 2006.201.05:32:33.21#ibcon#about to read 3, iclass 14, count 0 2006.201.05:32:33.24#ibcon#read 3, iclass 14, count 0 2006.201.05:32:33.24#ibcon#about to read 4, iclass 14, count 0 2006.201.05:32:33.24#ibcon#read 4, iclass 14, count 0 2006.201.05:32:33.24#ibcon#about to read 5, iclass 14, count 0 2006.201.05:32:33.24#ibcon#read 5, iclass 14, count 0 2006.201.05:32:33.24#ibcon#about to read 6, iclass 14, count 0 2006.201.05:32:33.24#ibcon#read 6, iclass 14, count 0 2006.201.05:32:33.24#ibcon#end of sib2, iclass 14, count 0 2006.201.05:32:33.24#ibcon#*after write, iclass 14, count 0 2006.201.05:32:33.24#ibcon#*before return 0, iclass 14, count 0 2006.201.05:32:33.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:33.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:32:33.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.05:32:33.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.05:32:33.24$vck44/vbbw=wide 2006.201.05:32:33.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.05:32:33.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.05:32:33.24#ibcon#ireg 8 cls_cnt 0 2006.201.05:32:33.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:32:33.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:32:33.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:32:33.31#ibcon#enter wrdev, iclass 16, count 0 2006.201.05:32:33.31#ibcon#first serial, iclass 16, count 0 2006.201.05:32:33.31#ibcon#enter sib2, iclass 16, count 0 2006.201.05:32:33.31#ibcon#flushed, iclass 16, count 0 2006.201.05:32:33.31#ibcon#about to write, iclass 16, count 0 2006.201.05:32:33.31#ibcon#wrote, iclass 16, count 0 2006.201.05:32:33.31#ibcon#about to read 3, iclass 16, count 0 2006.201.05:32:33.33#ibcon#read 3, iclass 16, count 0 2006.201.05:32:33.33#ibcon#about to read 4, iclass 16, count 0 2006.201.05:32:33.33#ibcon#read 4, iclass 16, count 0 2006.201.05:32:33.33#ibcon#about to read 5, iclass 16, count 0 2006.201.05:32:33.33#ibcon#read 5, iclass 16, count 0 2006.201.05:32:33.33#ibcon#about to read 6, iclass 16, count 0 2006.201.05:32:33.33#ibcon#read 6, iclass 16, count 0 2006.201.05:32:33.33#ibcon#end of sib2, iclass 16, count 0 2006.201.05:32:33.33#ibcon#*mode == 0, iclass 16, count 0 2006.201.05:32:33.33#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.05:32:33.33#ibcon#[27=BW32\r\n] 2006.201.05:32:33.33#ibcon#*before write, iclass 16, count 0 2006.201.05:32:33.33#ibcon#enter sib2, iclass 16, count 0 2006.201.05:32:33.33#ibcon#flushed, iclass 16, count 0 2006.201.05:32:33.33#ibcon#about to write, iclass 16, count 0 2006.201.05:32:33.33#ibcon#wrote, iclass 16, count 0 2006.201.05:32:33.33#ibcon#about to read 3, iclass 16, count 0 2006.201.05:32:33.36#ibcon#read 3, iclass 16, count 0 2006.201.05:32:33.36#ibcon#about to read 4, iclass 16, count 0 2006.201.05:32:33.36#ibcon#read 4, iclass 16, count 0 2006.201.05:32:33.41#ibcon#about to read 5, iclass 16, count 0 2006.201.05:32:33.41#ibcon#read 5, iclass 16, count 0 2006.201.05:32:33.41#ibcon#about to read 6, iclass 16, count 0 2006.201.05:32:33.41#ibcon#read 6, iclass 16, count 0 2006.201.05:32:33.41#ibcon#end of sib2, iclass 16, count 0 2006.201.05:32:33.41#ibcon#*after write, iclass 16, count 0 2006.201.05:32:33.41#ibcon#*before return 0, iclass 16, count 0 2006.201.05:32:33.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:32:33.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:32:33.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.05:32:33.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.05:32:33.41$setupk4/ifdk4 2006.201.05:32:33.41$ifdk4/lo= 2006.201.05:32:33.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:32:33.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:32:33.41$ifdk4/patch= 2006.201.05:32:33.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:32:33.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:32:33.42$setupk4/!*+20s 2006.201.05:32:35.55#abcon#<5=/05 2.9 5.0 23.16 911003.6\r\n> 2006.201.05:32:35.57#abcon#{5=INTERFACE CLEAR} 2006.201.05:32:35.63#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:32:45.72#abcon#<5=/05 2.9 5.0 23.16 911003.6\r\n> 2006.201.05:32:45.74#abcon#{5=INTERFACE CLEAR} 2006.201.05:32:45.80#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:32:47.26$setupk4/"tpicd 2006.201.05:32:47.26$setupk4/echo=off 2006.201.05:32:47.26$setupk4/xlog=off 2006.201.05:32:47.26:!2006.201.05:33:09 2006.201.05:32:52.14#trakl#Source acquired 2006.201.05:32:52.14#flagr#flagr/antenna,acquired 2006.201.05:33:09.00:preob 2006.201.05:33:09.14/onsource/TRACKING 2006.201.05:33:09.14:!2006.201.05:33:19 2006.201.05:33:19.00:"tape 2006.201.05:33:19.00:"st=record 2006.201.05:33:19.00:data_valid=on 2006.201.05:33:19.00:midob 2006.201.05:33:19.14/onsource/TRACKING 2006.201.05:33:19.14/wx/23.16,1003.6,91 2006.201.05:33:19.27/cable/+6.4657E-03 2006.201.05:33:20.36/va/01,08,usb,yes,31,33 2006.201.05:33:20.36/va/02,07,usb,yes,34,34 2006.201.05:33:20.36/va/03,08,usb,yes,30,32 2006.201.05:33:20.36/va/04,07,usb,yes,35,36 2006.201.05:33:20.36/va/05,04,usb,yes,31,31 2006.201.05:33:20.36/va/06,05,usb,yes,31,31 2006.201.05:33:20.36/va/07,05,usb,yes,30,31 2006.201.05:33:20.36/va/08,04,usb,yes,29,36 2006.201.05:33:20.59/valo/01,524.99,yes,locked 2006.201.05:33:20.59/valo/02,534.99,yes,locked 2006.201.05:33:20.59/valo/03,564.99,yes,locked 2006.201.05:33:20.59/valo/04,624.99,yes,locked 2006.201.05:33:20.59/valo/05,734.99,yes,locked 2006.201.05:33:20.59/valo/06,814.99,yes,locked 2006.201.05:33:20.59/valo/07,864.99,yes,locked 2006.201.05:33:20.59/valo/08,884.99,yes,locked 2006.201.05:33:21.68/vb/01,04,usb,yes,30,28 2006.201.05:33:21.68/vb/02,05,usb,yes,28,28 2006.201.05:33:21.68/vb/03,04,usb,yes,29,32 2006.201.05:33:21.68/vb/04,05,usb,yes,30,28 2006.201.05:33:21.68/vb/05,04,usb,yes,26,28 2006.201.05:33:21.68/vb/06,04,usb,yes,30,27 2006.201.05:33:21.68/vb/07,04,usb,yes,30,30 2006.201.05:33:21.68/vb/08,04,usb,yes,28,31 2006.201.05:33:21.92/vblo/01,629.99,yes,locked 2006.201.05:33:21.92/vblo/02,634.99,yes,locked 2006.201.05:33:21.92/vblo/03,649.99,yes,locked 2006.201.05:33:21.92/vblo/04,679.99,yes,locked 2006.201.05:33:21.92/vblo/05,709.99,yes,locked 2006.201.05:33:21.92/vblo/06,719.99,yes,locked 2006.201.05:33:21.92/vblo/07,734.99,yes,locked 2006.201.05:33:21.92/vblo/08,744.99,yes,locked 2006.201.05:33:22.07/vabw/8 2006.201.05:33:22.22/vbbw/8 2006.201.05:33:22.31/xfe/off,on,14.7 2006.201.05:33:22.68/ifatt/23,28,28,28 2006.201.05:33:23.05/fmout-gps/S +4.50E-07 2006.201.05:33:23.09:!2006.201.05:35:09 2006.201.05:35:09.00:data_valid=off 2006.201.05:35:09.00:"et 2006.201.05:35:09.00:!+3s 2006.201.05:35:12.01:"tape 2006.201.05:35:12.01:postob 2006.201.05:35:12.07/cable/+6.4680E-03 2006.201.05:35:12.07/wx/23.14,1003.6,91 2006.201.05:35:12.13/fmout-gps/S +4.50E-07 2006.201.05:35:12.13:scan_name=201-0539,jd0607,70 2006.201.05:35:12.13:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.201.05:35:13.14#flagr#flagr/antenna,new-source 2006.201.05:35:13.14:checkk5 2006.201.05:35:13.56/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:35:13.96/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:35:14.37/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:35:14.76/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:35:15.16/chk_obsdata//k5ts1/T2010533??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.05:35:15.54/chk_obsdata//k5ts2/T2010533??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.05:35:15.97/chk_obsdata//k5ts3/T2010533??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.05:35:16.38/chk_obsdata//k5ts4/T2010533??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.05:35:17.08/k5log//k5ts1_log_newline 2006.201.05:35:17.82/k5log//k5ts2_log_newline 2006.201.05:35:18.54/k5log//k5ts3_log_newline 2006.201.05:35:19.23/k5log//k5ts4_log_newline 2006.201.05:35:19.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:35:19.25:setupk4=1 2006.201.05:35:19.25$setupk4/echo=on 2006.201.05:35:19.25$setupk4/pcalon 2006.201.05:35:19.25$pcalon/"no phase cal control is implemented here 2006.201.05:35:19.25$setupk4/"tpicd=stop 2006.201.05:35:19.26$setupk4/"rec=synch_on 2006.201.05:35:19.26$setupk4/"rec_mode=128 2006.201.05:35:19.26$setupk4/!* 2006.201.05:35:19.26$setupk4/recpk4 2006.201.05:35:19.26$recpk4/recpatch= 2006.201.05:35:19.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:35:19.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:35:19.26$setupk4/vck44 2006.201.05:35:19.26$vck44/valo=1,524.99 2006.201.05:35:19.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.05:35:19.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.05:35:19.26#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:19.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:19.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:19.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:19.26#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:35:19.26#ibcon#first serial, iclass 17, count 0 2006.201.05:35:19.26#ibcon#enter sib2, iclass 17, count 0 2006.201.05:35:19.26#ibcon#flushed, iclass 17, count 0 2006.201.05:35:19.26#ibcon#about to write, iclass 17, count 0 2006.201.05:35:19.26#ibcon#wrote, iclass 17, count 0 2006.201.05:35:19.26#ibcon#about to read 3, iclass 17, count 0 2006.201.05:35:19.28#ibcon#read 3, iclass 17, count 0 2006.201.05:35:19.28#ibcon#about to read 4, iclass 17, count 0 2006.201.05:35:19.28#ibcon#read 4, iclass 17, count 0 2006.201.05:35:19.28#ibcon#about to read 5, iclass 17, count 0 2006.201.05:35:19.28#ibcon#read 5, iclass 17, count 0 2006.201.05:35:19.28#ibcon#about to read 6, iclass 17, count 0 2006.201.05:35:19.28#ibcon#read 6, iclass 17, count 0 2006.201.05:35:19.28#ibcon#end of sib2, iclass 17, count 0 2006.201.05:35:19.28#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:35:19.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:35:19.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:35:19.28#ibcon#*before write, iclass 17, count 0 2006.201.05:35:19.28#ibcon#enter sib2, iclass 17, count 0 2006.201.05:35:19.28#ibcon#flushed, iclass 17, count 0 2006.201.05:35:19.28#ibcon#about to write, iclass 17, count 0 2006.201.05:35:19.28#ibcon#wrote, iclass 17, count 0 2006.201.05:35:19.28#ibcon#about to read 3, iclass 17, count 0 2006.201.05:35:19.33#ibcon#read 3, iclass 17, count 0 2006.201.05:35:19.33#ibcon#about to read 4, iclass 17, count 0 2006.201.05:35:19.33#ibcon#read 4, iclass 17, count 0 2006.201.05:35:19.33#ibcon#about to read 5, iclass 17, count 0 2006.201.05:35:19.33#ibcon#read 5, iclass 17, count 0 2006.201.05:35:19.33#ibcon#about to read 6, iclass 17, count 0 2006.201.05:35:19.33#ibcon#read 6, iclass 17, count 0 2006.201.05:35:19.33#ibcon#end of sib2, iclass 17, count 0 2006.201.05:35:19.33#ibcon#*after write, iclass 17, count 0 2006.201.05:35:19.33#ibcon#*before return 0, iclass 17, count 0 2006.201.05:35:19.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:19.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:19.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:35:19.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:35:19.33$vck44/va=1,8 2006.201.05:35:19.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.05:35:19.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.05:35:19.33#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:19.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:19.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:19.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:19.33#ibcon#enter wrdev, iclass 19, count 2 2006.201.05:35:19.33#ibcon#first serial, iclass 19, count 2 2006.201.05:35:19.33#ibcon#enter sib2, iclass 19, count 2 2006.201.05:35:19.33#ibcon#flushed, iclass 19, count 2 2006.201.05:35:19.33#ibcon#about to write, iclass 19, count 2 2006.201.05:35:19.33#ibcon#wrote, iclass 19, count 2 2006.201.05:35:19.33#ibcon#about to read 3, iclass 19, count 2 2006.201.05:35:19.35#ibcon#read 3, iclass 19, count 2 2006.201.05:35:19.35#ibcon#about to read 4, iclass 19, count 2 2006.201.05:35:19.35#ibcon#read 4, iclass 19, count 2 2006.201.05:35:19.35#ibcon#about to read 5, iclass 19, count 2 2006.201.05:35:19.35#ibcon#read 5, iclass 19, count 2 2006.201.05:35:19.35#ibcon#about to read 6, iclass 19, count 2 2006.201.05:35:19.35#ibcon#read 6, iclass 19, count 2 2006.201.05:35:19.35#ibcon#end of sib2, iclass 19, count 2 2006.201.05:35:19.35#ibcon#*mode == 0, iclass 19, count 2 2006.201.05:35:19.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.05:35:19.35#ibcon#[25=AT01-08\r\n] 2006.201.05:35:19.35#ibcon#*before write, iclass 19, count 2 2006.201.05:35:19.35#ibcon#enter sib2, iclass 19, count 2 2006.201.05:35:19.35#ibcon#flushed, iclass 19, count 2 2006.201.05:35:19.35#ibcon#about to write, iclass 19, count 2 2006.201.05:35:19.35#ibcon#wrote, iclass 19, count 2 2006.201.05:35:19.35#ibcon#about to read 3, iclass 19, count 2 2006.201.05:35:19.38#ibcon#read 3, iclass 19, count 2 2006.201.05:35:19.38#ibcon#about to read 4, iclass 19, count 2 2006.201.05:35:19.38#ibcon#read 4, iclass 19, count 2 2006.201.05:35:19.38#ibcon#about to read 5, iclass 19, count 2 2006.201.05:35:19.38#ibcon#read 5, iclass 19, count 2 2006.201.05:35:19.38#ibcon#about to read 6, iclass 19, count 2 2006.201.05:35:19.38#ibcon#read 6, iclass 19, count 2 2006.201.05:35:19.38#ibcon#end of sib2, iclass 19, count 2 2006.201.05:35:19.38#ibcon#*after write, iclass 19, count 2 2006.201.05:35:19.38#ibcon#*before return 0, iclass 19, count 2 2006.201.05:35:19.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:19.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:19.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.05:35:19.38#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:19.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:19.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:19.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:19.50#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:35:19.50#ibcon#first serial, iclass 19, count 0 2006.201.05:35:19.50#ibcon#enter sib2, iclass 19, count 0 2006.201.05:35:19.50#ibcon#flushed, iclass 19, count 0 2006.201.05:35:19.50#ibcon#about to write, iclass 19, count 0 2006.201.05:35:19.50#ibcon#wrote, iclass 19, count 0 2006.201.05:35:19.50#ibcon#about to read 3, iclass 19, count 0 2006.201.05:35:19.52#ibcon#read 3, iclass 19, count 0 2006.201.05:35:19.52#ibcon#about to read 4, iclass 19, count 0 2006.201.05:35:19.52#ibcon#read 4, iclass 19, count 0 2006.201.05:35:19.52#ibcon#about to read 5, iclass 19, count 0 2006.201.05:35:19.52#ibcon#read 5, iclass 19, count 0 2006.201.05:35:19.52#ibcon#about to read 6, iclass 19, count 0 2006.201.05:35:19.52#ibcon#read 6, iclass 19, count 0 2006.201.05:35:19.52#ibcon#end of sib2, iclass 19, count 0 2006.201.05:35:19.52#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:35:19.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:35:19.52#ibcon#[25=USB\r\n] 2006.201.05:35:19.52#ibcon#*before write, iclass 19, count 0 2006.201.05:35:19.52#ibcon#enter sib2, iclass 19, count 0 2006.201.05:35:19.52#ibcon#flushed, iclass 19, count 0 2006.201.05:35:19.52#ibcon#about to write, iclass 19, count 0 2006.201.05:35:19.52#ibcon#wrote, iclass 19, count 0 2006.201.05:35:19.52#ibcon#about to read 3, iclass 19, count 0 2006.201.05:35:19.55#ibcon#read 3, iclass 19, count 0 2006.201.05:35:19.55#ibcon#about to read 4, iclass 19, count 0 2006.201.05:35:19.55#ibcon#read 4, iclass 19, count 0 2006.201.05:35:19.55#ibcon#about to read 5, iclass 19, count 0 2006.201.05:35:19.55#ibcon#read 5, iclass 19, count 0 2006.201.05:35:19.55#ibcon#about to read 6, iclass 19, count 0 2006.201.05:35:19.55#ibcon#read 6, iclass 19, count 0 2006.201.05:35:19.55#ibcon#end of sib2, iclass 19, count 0 2006.201.05:35:19.55#ibcon#*after write, iclass 19, count 0 2006.201.05:35:19.55#ibcon#*before return 0, iclass 19, count 0 2006.201.05:35:19.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:19.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:19.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:35:19.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:35:19.55$vck44/valo=2,534.99 2006.201.05:35:19.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.05:35:19.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.05:35:19.55#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:19.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:19.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:19.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:19.55#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:35:19.55#ibcon#first serial, iclass 21, count 0 2006.201.05:35:19.55#ibcon#enter sib2, iclass 21, count 0 2006.201.05:35:19.55#ibcon#flushed, iclass 21, count 0 2006.201.05:35:19.55#ibcon#about to write, iclass 21, count 0 2006.201.05:35:19.55#ibcon#wrote, iclass 21, count 0 2006.201.05:35:19.55#ibcon#about to read 3, iclass 21, count 0 2006.201.05:35:19.57#ibcon#read 3, iclass 21, count 0 2006.201.05:35:19.57#ibcon#about to read 4, iclass 21, count 0 2006.201.05:35:19.57#ibcon#read 4, iclass 21, count 0 2006.201.05:35:19.57#ibcon#about to read 5, iclass 21, count 0 2006.201.05:35:19.57#ibcon#read 5, iclass 21, count 0 2006.201.05:35:19.57#ibcon#about to read 6, iclass 21, count 0 2006.201.05:35:19.57#ibcon#read 6, iclass 21, count 0 2006.201.05:35:19.57#ibcon#end of sib2, iclass 21, count 0 2006.201.05:35:19.57#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:35:19.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:35:19.57#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:35:19.57#ibcon#*before write, iclass 21, count 0 2006.201.05:35:19.57#ibcon#enter sib2, iclass 21, count 0 2006.201.05:35:19.57#ibcon#flushed, iclass 21, count 0 2006.201.05:35:19.57#ibcon#about to write, iclass 21, count 0 2006.201.05:35:19.57#ibcon#wrote, iclass 21, count 0 2006.201.05:35:19.57#ibcon#about to read 3, iclass 21, count 0 2006.201.05:35:19.61#ibcon#read 3, iclass 21, count 0 2006.201.05:35:19.61#ibcon#about to read 4, iclass 21, count 0 2006.201.05:35:19.61#ibcon#read 4, iclass 21, count 0 2006.201.05:35:19.61#ibcon#about to read 5, iclass 21, count 0 2006.201.05:35:19.61#ibcon#read 5, iclass 21, count 0 2006.201.05:35:19.61#ibcon#about to read 6, iclass 21, count 0 2006.201.05:35:19.61#ibcon#read 6, iclass 21, count 0 2006.201.05:35:19.61#ibcon#end of sib2, iclass 21, count 0 2006.201.05:35:19.61#ibcon#*after write, iclass 21, count 0 2006.201.05:35:19.61#ibcon#*before return 0, iclass 21, count 0 2006.201.05:35:19.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:19.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:19.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:35:19.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:35:19.61$vck44/va=2,7 2006.201.05:35:19.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.05:35:19.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.05:35:19.61#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:19.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:19.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:19.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:19.67#ibcon#enter wrdev, iclass 23, count 2 2006.201.05:35:19.67#ibcon#first serial, iclass 23, count 2 2006.201.05:35:19.67#ibcon#enter sib2, iclass 23, count 2 2006.201.05:35:19.67#ibcon#flushed, iclass 23, count 2 2006.201.05:35:19.67#ibcon#about to write, iclass 23, count 2 2006.201.05:35:19.67#ibcon#wrote, iclass 23, count 2 2006.201.05:35:19.67#ibcon#about to read 3, iclass 23, count 2 2006.201.05:35:19.69#ibcon#read 3, iclass 23, count 2 2006.201.05:35:19.69#ibcon#about to read 4, iclass 23, count 2 2006.201.05:35:19.69#ibcon#read 4, iclass 23, count 2 2006.201.05:35:19.69#ibcon#about to read 5, iclass 23, count 2 2006.201.05:35:19.69#ibcon#read 5, iclass 23, count 2 2006.201.05:35:19.69#ibcon#about to read 6, iclass 23, count 2 2006.201.05:35:19.69#ibcon#read 6, iclass 23, count 2 2006.201.05:35:19.69#ibcon#end of sib2, iclass 23, count 2 2006.201.05:35:19.69#ibcon#*mode == 0, iclass 23, count 2 2006.201.05:35:19.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.05:35:19.69#ibcon#[25=AT02-07\r\n] 2006.201.05:35:19.69#ibcon#*before write, iclass 23, count 2 2006.201.05:35:19.69#ibcon#enter sib2, iclass 23, count 2 2006.201.05:35:19.69#ibcon#flushed, iclass 23, count 2 2006.201.05:35:19.69#ibcon#about to write, iclass 23, count 2 2006.201.05:35:19.69#ibcon#wrote, iclass 23, count 2 2006.201.05:35:19.69#ibcon#about to read 3, iclass 23, count 2 2006.201.05:35:19.72#ibcon#read 3, iclass 23, count 2 2006.201.05:35:19.72#ibcon#about to read 4, iclass 23, count 2 2006.201.05:35:19.72#ibcon#read 4, iclass 23, count 2 2006.201.05:35:19.72#ibcon#about to read 5, iclass 23, count 2 2006.201.05:35:19.72#ibcon#read 5, iclass 23, count 2 2006.201.05:35:19.72#ibcon#about to read 6, iclass 23, count 2 2006.201.05:35:19.72#ibcon#read 6, iclass 23, count 2 2006.201.05:35:19.72#ibcon#end of sib2, iclass 23, count 2 2006.201.05:35:19.72#ibcon#*after write, iclass 23, count 2 2006.201.05:35:19.72#ibcon#*before return 0, iclass 23, count 2 2006.201.05:35:19.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:19.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:19.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.05:35:19.72#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:19.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:19.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:19.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:19.84#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:35:19.84#ibcon#first serial, iclass 23, count 0 2006.201.05:35:19.84#ibcon#enter sib2, iclass 23, count 0 2006.201.05:35:19.84#ibcon#flushed, iclass 23, count 0 2006.201.05:35:19.84#ibcon#about to write, iclass 23, count 0 2006.201.05:35:19.84#ibcon#wrote, iclass 23, count 0 2006.201.05:35:19.84#ibcon#about to read 3, iclass 23, count 0 2006.201.05:35:19.86#ibcon#read 3, iclass 23, count 0 2006.201.05:35:19.86#ibcon#about to read 4, iclass 23, count 0 2006.201.05:35:19.86#ibcon#read 4, iclass 23, count 0 2006.201.05:35:19.86#ibcon#about to read 5, iclass 23, count 0 2006.201.05:35:19.86#ibcon#read 5, iclass 23, count 0 2006.201.05:35:19.86#ibcon#about to read 6, iclass 23, count 0 2006.201.05:35:19.86#ibcon#read 6, iclass 23, count 0 2006.201.05:35:19.86#ibcon#end of sib2, iclass 23, count 0 2006.201.05:35:19.86#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:35:19.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:35:19.86#ibcon#[25=USB\r\n] 2006.201.05:35:19.86#ibcon#*before write, iclass 23, count 0 2006.201.05:35:19.86#ibcon#enter sib2, iclass 23, count 0 2006.201.05:35:19.86#ibcon#flushed, iclass 23, count 0 2006.201.05:35:19.86#ibcon#about to write, iclass 23, count 0 2006.201.05:35:19.86#ibcon#wrote, iclass 23, count 0 2006.201.05:35:19.86#ibcon#about to read 3, iclass 23, count 0 2006.201.05:35:19.89#ibcon#read 3, iclass 23, count 0 2006.201.05:35:19.89#ibcon#about to read 4, iclass 23, count 0 2006.201.05:35:19.89#ibcon#read 4, iclass 23, count 0 2006.201.05:35:19.89#ibcon#about to read 5, iclass 23, count 0 2006.201.05:35:19.89#ibcon#read 5, iclass 23, count 0 2006.201.05:35:19.89#ibcon#about to read 6, iclass 23, count 0 2006.201.05:35:19.89#ibcon#read 6, iclass 23, count 0 2006.201.05:35:19.89#ibcon#end of sib2, iclass 23, count 0 2006.201.05:35:19.89#ibcon#*after write, iclass 23, count 0 2006.201.05:35:19.89#ibcon#*before return 0, iclass 23, count 0 2006.201.05:35:19.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:19.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:19.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:35:19.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:35:19.89$vck44/valo=3,564.99 2006.201.05:35:19.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.05:35:19.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.05:35:19.89#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:19.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:19.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:19.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:19.89#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:35:19.89#ibcon#first serial, iclass 25, count 0 2006.201.05:35:19.89#ibcon#enter sib2, iclass 25, count 0 2006.201.05:35:19.89#ibcon#flushed, iclass 25, count 0 2006.201.05:35:19.89#ibcon#about to write, iclass 25, count 0 2006.201.05:35:19.89#ibcon#wrote, iclass 25, count 0 2006.201.05:35:19.89#ibcon#about to read 3, iclass 25, count 0 2006.201.05:35:19.91#ibcon#read 3, iclass 25, count 0 2006.201.05:35:19.91#ibcon#about to read 4, iclass 25, count 0 2006.201.05:35:19.91#ibcon#read 4, iclass 25, count 0 2006.201.05:35:19.91#ibcon#about to read 5, iclass 25, count 0 2006.201.05:35:19.91#ibcon#read 5, iclass 25, count 0 2006.201.05:35:19.91#ibcon#about to read 6, iclass 25, count 0 2006.201.05:35:19.91#ibcon#read 6, iclass 25, count 0 2006.201.05:35:19.91#ibcon#end of sib2, iclass 25, count 0 2006.201.05:35:19.91#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:35:19.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:35:19.91#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:35:19.91#ibcon#*before write, iclass 25, count 0 2006.201.05:35:19.91#ibcon#enter sib2, iclass 25, count 0 2006.201.05:35:19.91#ibcon#flushed, iclass 25, count 0 2006.201.05:35:19.91#ibcon#about to write, iclass 25, count 0 2006.201.05:35:19.91#ibcon#wrote, iclass 25, count 0 2006.201.05:35:19.91#ibcon#about to read 3, iclass 25, count 0 2006.201.05:35:19.95#ibcon#read 3, iclass 25, count 0 2006.201.05:35:19.95#ibcon#about to read 4, iclass 25, count 0 2006.201.05:35:19.95#ibcon#read 4, iclass 25, count 0 2006.201.05:35:19.95#ibcon#about to read 5, iclass 25, count 0 2006.201.05:35:19.95#ibcon#read 5, iclass 25, count 0 2006.201.05:35:19.95#ibcon#about to read 6, iclass 25, count 0 2006.201.05:35:19.95#ibcon#read 6, iclass 25, count 0 2006.201.05:35:19.95#ibcon#end of sib2, iclass 25, count 0 2006.201.05:35:19.95#ibcon#*after write, iclass 25, count 0 2006.201.05:35:19.95#ibcon#*before return 0, iclass 25, count 0 2006.201.05:35:19.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:19.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:19.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:35:19.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:35:19.95$vck44/va=3,8 2006.201.05:35:19.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.05:35:19.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.05:35:19.95#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:19.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:20.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:20.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:20.01#ibcon#enter wrdev, iclass 27, count 2 2006.201.05:35:20.01#ibcon#first serial, iclass 27, count 2 2006.201.05:35:20.01#ibcon#enter sib2, iclass 27, count 2 2006.201.05:35:20.01#ibcon#flushed, iclass 27, count 2 2006.201.05:35:20.01#ibcon#about to write, iclass 27, count 2 2006.201.05:35:20.01#ibcon#wrote, iclass 27, count 2 2006.201.05:35:20.01#ibcon#about to read 3, iclass 27, count 2 2006.201.05:35:20.03#ibcon#read 3, iclass 27, count 2 2006.201.05:35:20.03#ibcon#about to read 4, iclass 27, count 2 2006.201.05:35:20.03#ibcon#read 4, iclass 27, count 2 2006.201.05:35:20.03#ibcon#about to read 5, iclass 27, count 2 2006.201.05:35:20.03#ibcon#read 5, iclass 27, count 2 2006.201.05:35:20.03#ibcon#about to read 6, iclass 27, count 2 2006.201.05:35:20.03#ibcon#read 6, iclass 27, count 2 2006.201.05:35:20.03#ibcon#end of sib2, iclass 27, count 2 2006.201.05:35:20.03#ibcon#*mode == 0, iclass 27, count 2 2006.201.05:35:20.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.05:35:20.03#ibcon#[25=AT03-08\r\n] 2006.201.05:35:20.03#ibcon#*before write, iclass 27, count 2 2006.201.05:35:20.03#ibcon#enter sib2, iclass 27, count 2 2006.201.05:35:20.03#ibcon#flushed, iclass 27, count 2 2006.201.05:35:20.03#ibcon#about to write, iclass 27, count 2 2006.201.05:35:20.03#ibcon#wrote, iclass 27, count 2 2006.201.05:35:20.03#ibcon#about to read 3, iclass 27, count 2 2006.201.05:35:20.06#ibcon#read 3, iclass 27, count 2 2006.201.05:35:20.06#ibcon#about to read 4, iclass 27, count 2 2006.201.05:35:20.06#ibcon#read 4, iclass 27, count 2 2006.201.05:35:20.06#ibcon#about to read 5, iclass 27, count 2 2006.201.05:35:20.06#ibcon#read 5, iclass 27, count 2 2006.201.05:35:20.06#ibcon#about to read 6, iclass 27, count 2 2006.201.05:35:20.06#ibcon#read 6, iclass 27, count 2 2006.201.05:35:20.06#ibcon#end of sib2, iclass 27, count 2 2006.201.05:35:20.06#ibcon#*after write, iclass 27, count 2 2006.201.05:35:20.06#ibcon#*before return 0, iclass 27, count 2 2006.201.05:35:20.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:20.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:20.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.05:35:20.06#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:20.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:20.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:20.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:20.18#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:35:20.18#ibcon#first serial, iclass 27, count 0 2006.201.05:35:20.18#ibcon#enter sib2, iclass 27, count 0 2006.201.05:35:20.18#ibcon#flushed, iclass 27, count 0 2006.201.05:35:20.18#ibcon#about to write, iclass 27, count 0 2006.201.05:35:20.18#ibcon#wrote, iclass 27, count 0 2006.201.05:35:20.18#ibcon#about to read 3, iclass 27, count 0 2006.201.05:35:20.20#ibcon#read 3, iclass 27, count 0 2006.201.05:35:20.20#ibcon#about to read 4, iclass 27, count 0 2006.201.05:35:20.20#ibcon#read 4, iclass 27, count 0 2006.201.05:35:20.20#ibcon#about to read 5, iclass 27, count 0 2006.201.05:35:20.20#ibcon#read 5, iclass 27, count 0 2006.201.05:35:20.20#ibcon#about to read 6, iclass 27, count 0 2006.201.05:35:20.20#ibcon#read 6, iclass 27, count 0 2006.201.05:35:20.20#ibcon#end of sib2, iclass 27, count 0 2006.201.05:35:20.20#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:35:20.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:35:20.20#ibcon#[25=USB\r\n] 2006.201.05:35:20.20#ibcon#*before write, iclass 27, count 0 2006.201.05:35:20.20#ibcon#enter sib2, iclass 27, count 0 2006.201.05:35:20.20#ibcon#flushed, iclass 27, count 0 2006.201.05:35:20.20#ibcon#about to write, iclass 27, count 0 2006.201.05:35:20.20#ibcon#wrote, iclass 27, count 0 2006.201.05:35:20.20#ibcon#about to read 3, iclass 27, count 0 2006.201.05:35:20.23#ibcon#read 3, iclass 27, count 0 2006.201.05:35:20.23#ibcon#about to read 4, iclass 27, count 0 2006.201.05:35:20.23#ibcon#read 4, iclass 27, count 0 2006.201.05:35:20.23#ibcon#about to read 5, iclass 27, count 0 2006.201.05:35:20.23#ibcon#read 5, iclass 27, count 0 2006.201.05:35:20.23#ibcon#about to read 6, iclass 27, count 0 2006.201.05:35:20.23#ibcon#read 6, iclass 27, count 0 2006.201.05:35:20.23#ibcon#end of sib2, iclass 27, count 0 2006.201.05:35:20.23#ibcon#*after write, iclass 27, count 0 2006.201.05:35:20.23#ibcon#*before return 0, iclass 27, count 0 2006.201.05:35:20.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:20.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:20.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:35:20.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:35:20.23$vck44/valo=4,624.99 2006.201.05:35:20.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:35:20.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:35:20.23#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:20.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:20.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:20.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:20.23#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:35:20.23#ibcon#first serial, iclass 29, count 0 2006.201.05:35:20.23#ibcon#enter sib2, iclass 29, count 0 2006.201.05:35:20.23#ibcon#flushed, iclass 29, count 0 2006.201.05:35:20.23#ibcon#about to write, iclass 29, count 0 2006.201.05:35:20.23#ibcon#wrote, iclass 29, count 0 2006.201.05:35:20.23#ibcon#about to read 3, iclass 29, count 0 2006.201.05:35:20.25#ibcon#read 3, iclass 29, count 0 2006.201.05:35:20.25#ibcon#about to read 4, iclass 29, count 0 2006.201.05:35:20.25#ibcon#read 4, iclass 29, count 0 2006.201.05:35:20.25#ibcon#about to read 5, iclass 29, count 0 2006.201.05:35:20.25#ibcon#read 5, iclass 29, count 0 2006.201.05:35:20.25#ibcon#about to read 6, iclass 29, count 0 2006.201.05:35:20.25#ibcon#read 6, iclass 29, count 0 2006.201.05:35:20.25#ibcon#end of sib2, iclass 29, count 0 2006.201.05:35:20.25#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:35:20.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:35:20.25#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:35:20.25#ibcon#*before write, iclass 29, count 0 2006.201.05:35:20.25#ibcon#enter sib2, iclass 29, count 0 2006.201.05:35:20.25#ibcon#flushed, iclass 29, count 0 2006.201.05:35:20.25#ibcon#about to write, iclass 29, count 0 2006.201.05:35:20.25#ibcon#wrote, iclass 29, count 0 2006.201.05:35:20.25#ibcon#about to read 3, iclass 29, count 0 2006.201.05:35:20.29#ibcon#read 3, iclass 29, count 0 2006.201.05:35:20.29#ibcon#about to read 4, iclass 29, count 0 2006.201.05:35:20.29#ibcon#read 4, iclass 29, count 0 2006.201.05:35:20.29#ibcon#about to read 5, iclass 29, count 0 2006.201.05:35:20.29#ibcon#read 5, iclass 29, count 0 2006.201.05:35:20.29#ibcon#about to read 6, iclass 29, count 0 2006.201.05:35:20.29#ibcon#read 6, iclass 29, count 0 2006.201.05:35:20.29#ibcon#end of sib2, iclass 29, count 0 2006.201.05:35:20.29#ibcon#*after write, iclass 29, count 0 2006.201.05:35:20.29#ibcon#*before return 0, iclass 29, count 0 2006.201.05:35:20.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:20.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:20.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:35:20.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:35:20.29$vck44/va=4,7 2006.201.05:35:20.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.05:35:20.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.05:35:20.29#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:20.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:20.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:20.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:20.35#ibcon#enter wrdev, iclass 31, count 2 2006.201.05:35:20.35#ibcon#first serial, iclass 31, count 2 2006.201.05:35:20.35#ibcon#enter sib2, iclass 31, count 2 2006.201.05:35:20.35#ibcon#flushed, iclass 31, count 2 2006.201.05:35:20.35#ibcon#about to write, iclass 31, count 2 2006.201.05:35:20.35#ibcon#wrote, iclass 31, count 2 2006.201.05:35:20.35#ibcon#about to read 3, iclass 31, count 2 2006.201.05:35:20.37#ibcon#read 3, iclass 31, count 2 2006.201.05:35:20.37#ibcon#about to read 4, iclass 31, count 2 2006.201.05:35:20.37#ibcon#read 4, iclass 31, count 2 2006.201.05:35:20.37#ibcon#about to read 5, iclass 31, count 2 2006.201.05:35:20.37#ibcon#read 5, iclass 31, count 2 2006.201.05:35:20.37#ibcon#about to read 6, iclass 31, count 2 2006.201.05:35:20.37#ibcon#read 6, iclass 31, count 2 2006.201.05:35:20.37#ibcon#end of sib2, iclass 31, count 2 2006.201.05:35:20.37#ibcon#*mode == 0, iclass 31, count 2 2006.201.05:35:20.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.05:35:20.37#ibcon#[25=AT04-07\r\n] 2006.201.05:35:20.37#ibcon#*before write, iclass 31, count 2 2006.201.05:35:20.37#ibcon#enter sib2, iclass 31, count 2 2006.201.05:35:20.37#ibcon#flushed, iclass 31, count 2 2006.201.05:35:20.37#ibcon#about to write, iclass 31, count 2 2006.201.05:35:20.37#ibcon#wrote, iclass 31, count 2 2006.201.05:35:20.37#ibcon#about to read 3, iclass 31, count 2 2006.201.05:35:20.40#ibcon#read 3, iclass 31, count 2 2006.201.05:35:20.43#ibcon#about to read 4, iclass 31, count 2 2006.201.05:35:20.43#ibcon#read 4, iclass 31, count 2 2006.201.05:35:20.43#ibcon#about to read 5, iclass 31, count 2 2006.201.05:35:20.43#ibcon#read 5, iclass 31, count 2 2006.201.05:35:20.43#ibcon#about to read 6, iclass 31, count 2 2006.201.05:35:20.43#ibcon#read 6, iclass 31, count 2 2006.201.05:35:20.43#ibcon#end of sib2, iclass 31, count 2 2006.201.05:35:20.43#ibcon#*after write, iclass 31, count 2 2006.201.05:35:20.43#ibcon#*before return 0, iclass 31, count 2 2006.201.05:35:20.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:20.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:20.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.05:35:20.43#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:20.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:20.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:20.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:20.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:35:20.55#ibcon#first serial, iclass 31, count 0 2006.201.05:35:20.55#ibcon#enter sib2, iclass 31, count 0 2006.201.05:35:20.55#ibcon#flushed, iclass 31, count 0 2006.201.05:35:20.55#ibcon#about to write, iclass 31, count 0 2006.201.05:35:20.55#ibcon#wrote, iclass 31, count 0 2006.201.05:35:20.55#ibcon#about to read 3, iclass 31, count 0 2006.201.05:35:20.57#ibcon#read 3, iclass 31, count 0 2006.201.05:35:20.57#ibcon#about to read 4, iclass 31, count 0 2006.201.05:35:20.57#ibcon#read 4, iclass 31, count 0 2006.201.05:35:20.57#ibcon#about to read 5, iclass 31, count 0 2006.201.05:35:20.57#ibcon#read 5, iclass 31, count 0 2006.201.05:35:20.57#ibcon#about to read 6, iclass 31, count 0 2006.201.05:35:20.57#ibcon#read 6, iclass 31, count 0 2006.201.05:35:20.57#ibcon#end of sib2, iclass 31, count 0 2006.201.05:35:20.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:35:20.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:35:20.57#ibcon#[25=USB\r\n] 2006.201.05:35:20.57#ibcon#*before write, iclass 31, count 0 2006.201.05:35:20.57#ibcon#enter sib2, iclass 31, count 0 2006.201.05:35:20.57#ibcon#flushed, iclass 31, count 0 2006.201.05:35:20.57#ibcon#about to write, iclass 31, count 0 2006.201.05:35:20.57#ibcon#wrote, iclass 31, count 0 2006.201.05:35:20.57#ibcon#about to read 3, iclass 31, count 0 2006.201.05:35:20.60#ibcon#read 3, iclass 31, count 0 2006.201.05:35:20.60#ibcon#about to read 4, iclass 31, count 0 2006.201.05:35:20.60#ibcon#read 4, iclass 31, count 0 2006.201.05:35:20.60#ibcon#about to read 5, iclass 31, count 0 2006.201.05:35:20.60#ibcon#read 5, iclass 31, count 0 2006.201.05:35:20.60#ibcon#about to read 6, iclass 31, count 0 2006.201.05:35:20.60#ibcon#read 6, iclass 31, count 0 2006.201.05:35:20.60#ibcon#end of sib2, iclass 31, count 0 2006.201.05:35:20.60#ibcon#*after write, iclass 31, count 0 2006.201.05:35:20.60#ibcon#*before return 0, iclass 31, count 0 2006.201.05:35:20.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:20.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:20.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:35:20.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:35:20.60$vck44/valo=5,734.99 2006.201.05:35:20.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.05:35:20.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.05:35:20.60#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:20.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:20.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:20.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:20.60#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:35:20.60#ibcon#first serial, iclass 33, count 0 2006.201.05:35:20.60#ibcon#enter sib2, iclass 33, count 0 2006.201.05:35:20.60#ibcon#flushed, iclass 33, count 0 2006.201.05:35:20.60#ibcon#about to write, iclass 33, count 0 2006.201.05:35:20.60#ibcon#wrote, iclass 33, count 0 2006.201.05:35:20.60#ibcon#about to read 3, iclass 33, count 0 2006.201.05:35:20.62#ibcon#read 3, iclass 33, count 0 2006.201.05:35:20.62#ibcon#about to read 4, iclass 33, count 0 2006.201.05:35:20.62#ibcon#read 4, iclass 33, count 0 2006.201.05:35:20.62#ibcon#about to read 5, iclass 33, count 0 2006.201.05:35:20.62#ibcon#read 5, iclass 33, count 0 2006.201.05:35:20.62#ibcon#about to read 6, iclass 33, count 0 2006.201.05:35:20.62#ibcon#read 6, iclass 33, count 0 2006.201.05:35:20.62#ibcon#end of sib2, iclass 33, count 0 2006.201.05:35:20.62#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:35:20.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:35:20.62#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:35:20.62#ibcon#*before write, iclass 33, count 0 2006.201.05:35:20.62#ibcon#enter sib2, iclass 33, count 0 2006.201.05:35:20.62#ibcon#flushed, iclass 33, count 0 2006.201.05:35:20.62#ibcon#about to write, iclass 33, count 0 2006.201.05:35:20.62#ibcon#wrote, iclass 33, count 0 2006.201.05:35:20.62#ibcon#about to read 3, iclass 33, count 0 2006.201.05:35:20.66#ibcon#read 3, iclass 33, count 0 2006.201.05:35:20.66#ibcon#about to read 4, iclass 33, count 0 2006.201.05:35:20.66#ibcon#read 4, iclass 33, count 0 2006.201.05:35:20.66#ibcon#about to read 5, iclass 33, count 0 2006.201.05:35:20.66#ibcon#read 5, iclass 33, count 0 2006.201.05:35:20.66#ibcon#about to read 6, iclass 33, count 0 2006.201.05:35:20.66#ibcon#read 6, iclass 33, count 0 2006.201.05:35:20.66#ibcon#end of sib2, iclass 33, count 0 2006.201.05:35:20.66#ibcon#*after write, iclass 33, count 0 2006.201.05:35:20.66#ibcon#*before return 0, iclass 33, count 0 2006.201.05:35:20.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:20.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:20.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:35:20.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:35:20.66$vck44/va=5,4 2006.201.05:35:20.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.05:35:20.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.05:35:20.66#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:20.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:20.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:20.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:20.72#ibcon#enter wrdev, iclass 35, count 2 2006.201.05:35:20.72#ibcon#first serial, iclass 35, count 2 2006.201.05:35:20.72#ibcon#enter sib2, iclass 35, count 2 2006.201.05:35:20.72#ibcon#flushed, iclass 35, count 2 2006.201.05:35:20.72#ibcon#about to write, iclass 35, count 2 2006.201.05:35:20.72#ibcon#wrote, iclass 35, count 2 2006.201.05:35:20.72#ibcon#about to read 3, iclass 35, count 2 2006.201.05:35:20.74#ibcon#read 3, iclass 35, count 2 2006.201.05:35:20.74#ibcon#about to read 4, iclass 35, count 2 2006.201.05:35:20.74#ibcon#read 4, iclass 35, count 2 2006.201.05:35:20.74#ibcon#about to read 5, iclass 35, count 2 2006.201.05:35:20.74#ibcon#read 5, iclass 35, count 2 2006.201.05:35:20.74#ibcon#about to read 6, iclass 35, count 2 2006.201.05:35:20.74#ibcon#read 6, iclass 35, count 2 2006.201.05:35:20.74#ibcon#end of sib2, iclass 35, count 2 2006.201.05:35:20.74#ibcon#*mode == 0, iclass 35, count 2 2006.201.05:35:20.74#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.05:35:20.74#ibcon#[25=AT05-04\r\n] 2006.201.05:35:20.74#ibcon#*before write, iclass 35, count 2 2006.201.05:35:20.74#ibcon#enter sib2, iclass 35, count 2 2006.201.05:35:20.74#ibcon#flushed, iclass 35, count 2 2006.201.05:35:20.74#ibcon#about to write, iclass 35, count 2 2006.201.05:35:20.74#ibcon#wrote, iclass 35, count 2 2006.201.05:35:20.74#ibcon#about to read 3, iclass 35, count 2 2006.201.05:35:20.77#ibcon#read 3, iclass 35, count 2 2006.201.05:35:20.77#ibcon#about to read 4, iclass 35, count 2 2006.201.05:35:20.77#ibcon#read 4, iclass 35, count 2 2006.201.05:35:20.77#ibcon#about to read 5, iclass 35, count 2 2006.201.05:35:20.77#ibcon#read 5, iclass 35, count 2 2006.201.05:35:20.77#ibcon#about to read 6, iclass 35, count 2 2006.201.05:35:20.77#ibcon#read 6, iclass 35, count 2 2006.201.05:35:20.77#ibcon#end of sib2, iclass 35, count 2 2006.201.05:35:20.77#ibcon#*after write, iclass 35, count 2 2006.201.05:35:20.77#ibcon#*before return 0, iclass 35, count 2 2006.201.05:35:20.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:20.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:20.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.05:35:20.77#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:20.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:20.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:20.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:20.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:35:20.89#ibcon#first serial, iclass 35, count 0 2006.201.05:35:20.89#ibcon#enter sib2, iclass 35, count 0 2006.201.05:35:20.89#ibcon#flushed, iclass 35, count 0 2006.201.05:35:20.89#ibcon#about to write, iclass 35, count 0 2006.201.05:35:20.89#ibcon#wrote, iclass 35, count 0 2006.201.05:35:20.89#ibcon#about to read 3, iclass 35, count 0 2006.201.05:35:20.91#ibcon#read 3, iclass 35, count 0 2006.201.05:35:20.91#ibcon#about to read 4, iclass 35, count 0 2006.201.05:35:20.91#ibcon#read 4, iclass 35, count 0 2006.201.05:35:20.91#ibcon#about to read 5, iclass 35, count 0 2006.201.05:35:20.91#ibcon#read 5, iclass 35, count 0 2006.201.05:35:20.91#ibcon#about to read 6, iclass 35, count 0 2006.201.05:35:20.91#ibcon#read 6, iclass 35, count 0 2006.201.05:35:20.91#ibcon#end of sib2, iclass 35, count 0 2006.201.05:35:20.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:35:20.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:35:20.91#ibcon#[25=USB\r\n] 2006.201.05:35:20.91#ibcon#*before write, iclass 35, count 0 2006.201.05:35:20.91#ibcon#enter sib2, iclass 35, count 0 2006.201.05:35:20.91#ibcon#flushed, iclass 35, count 0 2006.201.05:35:20.91#ibcon#about to write, iclass 35, count 0 2006.201.05:35:20.91#ibcon#wrote, iclass 35, count 0 2006.201.05:35:20.91#ibcon#about to read 3, iclass 35, count 0 2006.201.05:35:20.94#ibcon#read 3, iclass 35, count 0 2006.201.05:35:20.94#ibcon#about to read 4, iclass 35, count 0 2006.201.05:35:20.94#ibcon#read 4, iclass 35, count 0 2006.201.05:35:20.94#ibcon#about to read 5, iclass 35, count 0 2006.201.05:35:20.94#ibcon#read 5, iclass 35, count 0 2006.201.05:35:20.94#ibcon#about to read 6, iclass 35, count 0 2006.201.05:35:20.94#ibcon#read 6, iclass 35, count 0 2006.201.05:35:20.94#ibcon#end of sib2, iclass 35, count 0 2006.201.05:35:20.94#ibcon#*after write, iclass 35, count 0 2006.201.05:35:20.94#ibcon#*before return 0, iclass 35, count 0 2006.201.05:35:20.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:20.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:20.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:35:20.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:35:20.94$vck44/valo=6,814.99 2006.201.05:35:20.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.05:35:20.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.05:35:20.94#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:20.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:20.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:20.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:20.94#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:35:20.94#ibcon#first serial, iclass 37, count 0 2006.201.05:35:20.94#ibcon#enter sib2, iclass 37, count 0 2006.201.05:35:20.94#ibcon#flushed, iclass 37, count 0 2006.201.05:35:20.94#ibcon#about to write, iclass 37, count 0 2006.201.05:35:20.94#ibcon#wrote, iclass 37, count 0 2006.201.05:35:20.94#ibcon#about to read 3, iclass 37, count 0 2006.201.05:35:20.96#ibcon#read 3, iclass 37, count 0 2006.201.05:35:20.96#ibcon#about to read 4, iclass 37, count 0 2006.201.05:35:20.96#ibcon#read 4, iclass 37, count 0 2006.201.05:35:20.96#ibcon#about to read 5, iclass 37, count 0 2006.201.05:35:20.96#ibcon#read 5, iclass 37, count 0 2006.201.05:35:20.96#ibcon#about to read 6, iclass 37, count 0 2006.201.05:35:20.96#ibcon#read 6, iclass 37, count 0 2006.201.05:35:20.96#ibcon#end of sib2, iclass 37, count 0 2006.201.05:35:20.96#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:35:20.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:35:20.96#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:35:20.96#ibcon#*before write, iclass 37, count 0 2006.201.05:35:20.96#ibcon#enter sib2, iclass 37, count 0 2006.201.05:35:20.96#ibcon#flushed, iclass 37, count 0 2006.201.05:35:20.96#ibcon#about to write, iclass 37, count 0 2006.201.05:35:20.96#ibcon#wrote, iclass 37, count 0 2006.201.05:35:20.96#ibcon#about to read 3, iclass 37, count 0 2006.201.05:35:21.00#ibcon#read 3, iclass 37, count 0 2006.201.05:35:21.00#ibcon#about to read 4, iclass 37, count 0 2006.201.05:35:21.00#ibcon#read 4, iclass 37, count 0 2006.201.05:35:21.00#ibcon#about to read 5, iclass 37, count 0 2006.201.05:35:21.00#ibcon#read 5, iclass 37, count 0 2006.201.05:35:21.00#ibcon#about to read 6, iclass 37, count 0 2006.201.05:35:21.00#ibcon#read 6, iclass 37, count 0 2006.201.05:35:21.00#ibcon#end of sib2, iclass 37, count 0 2006.201.05:35:21.00#ibcon#*after write, iclass 37, count 0 2006.201.05:35:21.00#ibcon#*before return 0, iclass 37, count 0 2006.201.05:35:21.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:21.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:21.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:35:21.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:35:21.00$vck44/va=6,5 2006.201.05:35:21.00#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.05:35:21.00#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.05:35:21.00#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:21.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:21.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:21.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:21.06#ibcon#enter wrdev, iclass 39, count 2 2006.201.05:35:21.06#ibcon#first serial, iclass 39, count 2 2006.201.05:35:21.06#ibcon#enter sib2, iclass 39, count 2 2006.201.05:35:21.06#ibcon#flushed, iclass 39, count 2 2006.201.05:35:21.06#ibcon#about to write, iclass 39, count 2 2006.201.05:35:21.06#ibcon#wrote, iclass 39, count 2 2006.201.05:35:21.06#ibcon#about to read 3, iclass 39, count 2 2006.201.05:35:21.08#ibcon#read 3, iclass 39, count 2 2006.201.05:35:21.08#ibcon#about to read 4, iclass 39, count 2 2006.201.05:35:21.08#ibcon#read 4, iclass 39, count 2 2006.201.05:35:21.08#ibcon#about to read 5, iclass 39, count 2 2006.201.05:35:21.08#ibcon#read 5, iclass 39, count 2 2006.201.05:35:21.08#ibcon#about to read 6, iclass 39, count 2 2006.201.05:35:21.08#ibcon#read 6, iclass 39, count 2 2006.201.05:35:21.08#ibcon#end of sib2, iclass 39, count 2 2006.201.05:35:21.08#ibcon#*mode == 0, iclass 39, count 2 2006.201.05:35:21.08#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.05:35:21.08#ibcon#[25=AT06-05\r\n] 2006.201.05:35:21.08#ibcon#*before write, iclass 39, count 2 2006.201.05:35:21.08#ibcon#enter sib2, iclass 39, count 2 2006.201.05:35:21.08#ibcon#flushed, iclass 39, count 2 2006.201.05:35:21.08#ibcon#about to write, iclass 39, count 2 2006.201.05:35:21.08#ibcon#wrote, iclass 39, count 2 2006.201.05:35:21.08#ibcon#about to read 3, iclass 39, count 2 2006.201.05:35:21.11#ibcon#read 3, iclass 39, count 2 2006.201.05:35:21.11#ibcon#about to read 4, iclass 39, count 2 2006.201.05:35:21.11#ibcon#read 4, iclass 39, count 2 2006.201.05:35:21.11#ibcon#about to read 5, iclass 39, count 2 2006.201.05:35:21.11#ibcon#read 5, iclass 39, count 2 2006.201.05:35:21.11#ibcon#about to read 6, iclass 39, count 2 2006.201.05:35:21.11#ibcon#read 6, iclass 39, count 2 2006.201.05:35:21.11#ibcon#end of sib2, iclass 39, count 2 2006.201.05:35:21.11#ibcon#*after write, iclass 39, count 2 2006.201.05:35:21.11#ibcon#*before return 0, iclass 39, count 2 2006.201.05:35:21.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:21.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:21.11#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.05:35:21.11#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:21.11#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:21.23#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:21.23#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:21.23#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:35:21.23#ibcon#first serial, iclass 39, count 0 2006.201.05:35:21.23#ibcon#enter sib2, iclass 39, count 0 2006.201.05:35:21.23#ibcon#flushed, iclass 39, count 0 2006.201.05:35:21.23#ibcon#about to write, iclass 39, count 0 2006.201.05:35:21.23#ibcon#wrote, iclass 39, count 0 2006.201.05:35:21.23#ibcon#about to read 3, iclass 39, count 0 2006.201.05:35:21.25#ibcon#read 3, iclass 39, count 0 2006.201.05:35:21.25#ibcon#about to read 4, iclass 39, count 0 2006.201.05:35:21.25#ibcon#read 4, iclass 39, count 0 2006.201.05:35:21.25#ibcon#about to read 5, iclass 39, count 0 2006.201.05:35:21.25#ibcon#read 5, iclass 39, count 0 2006.201.05:35:21.25#ibcon#about to read 6, iclass 39, count 0 2006.201.05:35:21.25#ibcon#read 6, iclass 39, count 0 2006.201.05:35:21.25#ibcon#end of sib2, iclass 39, count 0 2006.201.05:35:21.25#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:35:21.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:35:21.25#ibcon#[25=USB\r\n] 2006.201.05:35:21.25#ibcon#*before write, iclass 39, count 0 2006.201.05:35:21.25#ibcon#enter sib2, iclass 39, count 0 2006.201.05:35:21.25#ibcon#flushed, iclass 39, count 0 2006.201.05:35:21.25#ibcon#about to write, iclass 39, count 0 2006.201.05:35:21.25#ibcon#wrote, iclass 39, count 0 2006.201.05:35:21.25#ibcon#about to read 3, iclass 39, count 0 2006.201.05:35:21.28#ibcon#read 3, iclass 39, count 0 2006.201.05:35:21.28#ibcon#about to read 4, iclass 39, count 0 2006.201.05:35:21.28#ibcon#read 4, iclass 39, count 0 2006.201.05:35:21.28#ibcon#about to read 5, iclass 39, count 0 2006.201.05:35:21.28#ibcon#read 5, iclass 39, count 0 2006.201.05:35:21.28#ibcon#about to read 6, iclass 39, count 0 2006.201.05:35:21.28#ibcon#read 6, iclass 39, count 0 2006.201.05:35:21.28#ibcon#end of sib2, iclass 39, count 0 2006.201.05:35:21.28#ibcon#*after write, iclass 39, count 0 2006.201.05:35:21.28#ibcon#*before return 0, iclass 39, count 0 2006.201.05:35:21.28#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:21.28#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:21.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:35:21.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:35:21.28$vck44/valo=7,864.99 2006.201.05:35:21.28#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.05:35:21.28#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.05:35:21.28#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:21.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:21.28#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:21.28#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:21.28#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:35:21.28#ibcon#first serial, iclass 2, count 0 2006.201.05:35:21.28#ibcon#enter sib2, iclass 2, count 0 2006.201.05:35:21.28#ibcon#flushed, iclass 2, count 0 2006.201.05:35:21.28#ibcon#about to write, iclass 2, count 0 2006.201.05:35:21.28#ibcon#wrote, iclass 2, count 0 2006.201.05:35:21.28#ibcon#about to read 3, iclass 2, count 0 2006.201.05:35:21.30#ibcon#read 3, iclass 2, count 0 2006.201.05:35:21.30#ibcon#about to read 4, iclass 2, count 0 2006.201.05:35:21.30#ibcon#read 4, iclass 2, count 0 2006.201.05:35:21.30#ibcon#about to read 5, iclass 2, count 0 2006.201.05:35:21.30#ibcon#read 5, iclass 2, count 0 2006.201.05:35:21.30#ibcon#about to read 6, iclass 2, count 0 2006.201.05:35:21.30#ibcon#read 6, iclass 2, count 0 2006.201.05:35:21.30#ibcon#end of sib2, iclass 2, count 0 2006.201.05:35:21.30#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:35:21.30#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:35:21.30#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:35:21.30#ibcon#*before write, iclass 2, count 0 2006.201.05:35:21.30#ibcon#enter sib2, iclass 2, count 0 2006.201.05:35:21.30#ibcon#flushed, iclass 2, count 0 2006.201.05:35:21.30#ibcon#about to write, iclass 2, count 0 2006.201.05:35:21.30#ibcon#wrote, iclass 2, count 0 2006.201.05:35:21.30#ibcon#about to read 3, iclass 2, count 0 2006.201.05:35:21.34#ibcon#read 3, iclass 2, count 0 2006.201.05:35:21.34#ibcon#about to read 4, iclass 2, count 0 2006.201.05:35:21.34#ibcon#read 4, iclass 2, count 0 2006.201.05:35:21.34#ibcon#about to read 5, iclass 2, count 0 2006.201.05:35:21.34#ibcon#read 5, iclass 2, count 0 2006.201.05:35:21.34#ibcon#about to read 6, iclass 2, count 0 2006.201.05:35:21.34#ibcon#read 6, iclass 2, count 0 2006.201.05:35:21.34#ibcon#end of sib2, iclass 2, count 0 2006.201.05:35:21.34#ibcon#*after write, iclass 2, count 0 2006.201.05:35:21.34#ibcon#*before return 0, iclass 2, count 0 2006.201.05:35:21.34#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:21.34#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:21.34#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:35:21.34#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:35:21.34$vck44/va=7,5 2006.201.05:35:21.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.05:35:21.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.05:35:21.34#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:21.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:21.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:21.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:21.40#ibcon#enter wrdev, iclass 5, count 2 2006.201.05:35:21.40#ibcon#first serial, iclass 5, count 2 2006.201.05:35:21.40#ibcon#enter sib2, iclass 5, count 2 2006.201.05:35:21.40#ibcon#flushed, iclass 5, count 2 2006.201.05:35:21.40#ibcon#about to write, iclass 5, count 2 2006.201.05:35:21.40#ibcon#wrote, iclass 5, count 2 2006.201.05:35:21.40#ibcon#about to read 3, iclass 5, count 2 2006.201.05:35:21.42#ibcon#read 3, iclass 5, count 2 2006.201.05:35:21.42#ibcon#about to read 4, iclass 5, count 2 2006.201.05:35:21.42#ibcon#read 4, iclass 5, count 2 2006.201.05:35:21.42#ibcon#about to read 5, iclass 5, count 2 2006.201.05:35:21.42#ibcon#read 5, iclass 5, count 2 2006.201.05:35:21.42#ibcon#about to read 6, iclass 5, count 2 2006.201.05:35:21.42#ibcon#read 6, iclass 5, count 2 2006.201.05:35:21.42#ibcon#end of sib2, iclass 5, count 2 2006.201.05:35:21.42#ibcon#*mode == 0, iclass 5, count 2 2006.201.05:35:21.42#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.05:35:21.42#ibcon#[25=AT07-05\r\n] 2006.201.05:35:21.42#ibcon#*before write, iclass 5, count 2 2006.201.05:35:21.51#ibcon#enter sib2, iclass 5, count 2 2006.201.05:35:21.51#ibcon#flushed, iclass 5, count 2 2006.201.05:35:21.51#ibcon#about to write, iclass 5, count 2 2006.201.05:35:21.51#ibcon#wrote, iclass 5, count 2 2006.201.05:35:21.51#ibcon#about to read 3, iclass 5, count 2 2006.201.05:35:21.54#ibcon#read 3, iclass 5, count 2 2006.201.05:35:21.54#ibcon#about to read 4, iclass 5, count 2 2006.201.05:35:21.54#ibcon#read 4, iclass 5, count 2 2006.201.05:35:21.54#ibcon#about to read 5, iclass 5, count 2 2006.201.05:35:21.54#ibcon#read 5, iclass 5, count 2 2006.201.05:35:21.54#ibcon#about to read 6, iclass 5, count 2 2006.201.05:35:21.54#ibcon#read 6, iclass 5, count 2 2006.201.05:35:21.54#ibcon#end of sib2, iclass 5, count 2 2006.201.05:35:21.54#ibcon#*after write, iclass 5, count 2 2006.201.05:35:21.54#ibcon#*before return 0, iclass 5, count 2 2006.201.05:35:21.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:21.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:21.54#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.05:35:21.54#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:21.54#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:21.66#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:21.66#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:21.66#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:35:21.66#ibcon#first serial, iclass 5, count 0 2006.201.05:35:21.66#ibcon#enter sib2, iclass 5, count 0 2006.201.05:35:21.66#ibcon#flushed, iclass 5, count 0 2006.201.05:35:21.66#ibcon#about to write, iclass 5, count 0 2006.201.05:35:21.66#ibcon#wrote, iclass 5, count 0 2006.201.05:35:21.66#ibcon#about to read 3, iclass 5, count 0 2006.201.05:35:21.68#ibcon#read 3, iclass 5, count 0 2006.201.05:35:21.68#ibcon#about to read 4, iclass 5, count 0 2006.201.05:35:21.68#ibcon#read 4, iclass 5, count 0 2006.201.05:35:21.68#ibcon#about to read 5, iclass 5, count 0 2006.201.05:35:21.68#ibcon#read 5, iclass 5, count 0 2006.201.05:35:21.68#ibcon#about to read 6, iclass 5, count 0 2006.201.05:35:21.68#ibcon#read 6, iclass 5, count 0 2006.201.05:35:21.68#ibcon#end of sib2, iclass 5, count 0 2006.201.05:35:21.68#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:35:21.68#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:35:21.68#ibcon#[25=USB\r\n] 2006.201.05:35:21.68#ibcon#*before write, iclass 5, count 0 2006.201.05:35:21.68#ibcon#enter sib2, iclass 5, count 0 2006.201.05:35:21.68#ibcon#flushed, iclass 5, count 0 2006.201.05:35:21.68#ibcon#about to write, iclass 5, count 0 2006.201.05:35:21.68#ibcon#wrote, iclass 5, count 0 2006.201.05:35:21.68#ibcon#about to read 3, iclass 5, count 0 2006.201.05:35:21.71#ibcon#read 3, iclass 5, count 0 2006.201.05:35:21.71#ibcon#about to read 4, iclass 5, count 0 2006.201.05:35:21.71#ibcon#read 4, iclass 5, count 0 2006.201.05:35:21.71#ibcon#about to read 5, iclass 5, count 0 2006.201.05:35:21.71#ibcon#read 5, iclass 5, count 0 2006.201.05:35:21.71#ibcon#about to read 6, iclass 5, count 0 2006.201.05:35:21.71#ibcon#read 6, iclass 5, count 0 2006.201.05:35:21.71#ibcon#end of sib2, iclass 5, count 0 2006.201.05:35:21.71#ibcon#*after write, iclass 5, count 0 2006.201.05:35:21.71#ibcon#*before return 0, iclass 5, count 0 2006.201.05:35:21.71#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:21.71#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:21.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:35:21.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:35:21.71$vck44/valo=8,884.99 2006.201.05:35:21.71#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.05:35:21.71#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.05:35:21.71#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:21.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:21.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:21.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:21.71#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:35:21.71#ibcon#first serial, iclass 7, count 0 2006.201.05:35:21.71#ibcon#enter sib2, iclass 7, count 0 2006.201.05:35:21.71#ibcon#flushed, iclass 7, count 0 2006.201.05:35:21.71#ibcon#about to write, iclass 7, count 0 2006.201.05:35:21.71#ibcon#wrote, iclass 7, count 0 2006.201.05:35:21.71#ibcon#about to read 3, iclass 7, count 0 2006.201.05:35:21.73#ibcon#read 3, iclass 7, count 0 2006.201.05:35:21.73#ibcon#about to read 4, iclass 7, count 0 2006.201.05:35:21.73#ibcon#read 4, iclass 7, count 0 2006.201.05:35:21.73#ibcon#about to read 5, iclass 7, count 0 2006.201.05:35:21.73#ibcon#read 5, iclass 7, count 0 2006.201.05:35:21.73#ibcon#about to read 6, iclass 7, count 0 2006.201.05:35:21.73#ibcon#read 6, iclass 7, count 0 2006.201.05:35:21.73#ibcon#end of sib2, iclass 7, count 0 2006.201.05:35:21.73#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:35:21.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:35:21.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:35:21.73#ibcon#*before write, iclass 7, count 0 2006.201.05:35:21.73#ibcon#enter sib2, iclass 7, count 0 2006.201.05:35:21.73#ibcon#flushed, iclass 7, count 0 2006.201.05:35:21.73#ibcon#about to write, iclass 7, count 0 2006.201.05:35:21.73#ibcon#wrote, iclass 7, count 0 2006.201.05:35:21.73#ibcon#about to read 3, iclass 7, count 0 2006.201.05:35:21.77#ibcon#read 3, iclass 7, count 0 2006.201.05:35:21.77#ibcon#about to read 4, iclass 7, count 0 2006.201.05:35:21.77#ibcon#read 4, iclass 7, count 0 2006.201.05:35:21.77#ibcon#about to read 5, iclass 7, count 0 2006.201.05:35:21.77#ibcon#read 5, iclass 7, count 0 2006.201.05:35:21.77#ibcon#about to read 6, iclass 7, count 0 2006.201.05:35:21.77#ibcon#read 6, iclass 7, count 0 2006.201.05:35:21.77#ibcon#end of sib2, iclass 7, count 0 2006.201.05:35:21.77#ibcon#*after write, iclass 7, count 0 2006.201.05:35:21.77#ibcon#*before return 0, iclass 7, count 0 2006.201.05:35:21.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:21.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:21.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:35:21.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:35:21.77$vck44/va=8,4 2006.201.05:35:21.77#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.05:35:21.77#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.05:35:21.77#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:21.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:35:21.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:35:21.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:35:21.83#ibcon#enter wrdev, iclass 11, count 2 2006.201.05:35:21.83#ibcon#first serial, iclass 11, count 2 2006.201.05:35:21.83#ibcon#enter sib2, iclass 11, count 2 2006.201.05:35:21.83#ibcon#flushed, iclass 11, count 2 2006.201.05:35:21.83#ibcon#about to write, iclass 11, count 2 2006.201.05:35:21.83#ibcon#wrote, iclass 11, count 2 2006.201.05:35:21.83#ibcon#about to read 3, iclass 11, count 2 2006.201.05:35:21.85#ibcon#read 3, iclass 11, count 2 2006.201.05:35:21.85#ibcon#about to read 4, iclass 11, count 2 2006.201.05:35:21.85#ibcon#read 4, iclass 11, count 2 2006.201.05:35:21.85#ibcon#about to read 5, iclass 11, count 2 2006.201.05:35:21.85#ibcon#read 5, iclass 11, count 2 2006.201.05:35:21.85#ibcon#about to read 6, iclass 11, count 2 2006.201.05:35:21.85#ibcon#read 6, iclass 11, count 2 2006.201.05:35:21.85#ibcon#end of sib2, iclass 11, count 2 2006.201.05:35:21.85#ibcon#*mode == 0, iclass 11, count 2 2006.201.05:35:21.85#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.05:35:21.85#ibcon#[25=AT08-04\r\n] 2006.201.05:35:21.85#ibcon#*before write, iclass 11, count 2 2006.201.05:35:21.85#ibcon#enter sib2, iclass 11, count 2 2006.201.05:35:21.85#ibcon#flushed, iclass 11, count 2 2006.201.05:35:21.85#ibcon#about to write, iclass 11, count 2 2006.201.05:35:21.85#ibcon#wrote, iclass 11, count 2 2006.201.05:35:21.85#ibcon#about to read 3, iclass 11, count 2 2006.201.05:35:21.88#ibcon#read 3, iclass 11, count 2 2006.201.05:35:21.88#ibcon#about to read 4, iclass 11, count 2 2006.201.05:35:21.88#ibcon#read 4, iclass 11, count 2 2006.201.05:35:21.88#ibcon#about to read 5, iclass 11, count 2 2006.201.05:35:21.88#ibcon#read 5, iclass 11, count 2 2006.201.05:35:21.88#ibcon#about to read 6, iclass 11, count 2 2006.201.05:35:21.88#ibcon#read 6, iclass 11, count 2 2006.201.05:35:21.88#ibcon#end of sib2, iclass 11, count 2 2006.201.05:35:21.88#ibcon#*after write, iclass 11, count 2 2006.201.05:35:21.88#ibcon#*before return 0, iclass 11, count 2 2006.201.05:35:21.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:35:21.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:35:21.88#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.05:35:21.88#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:21.88#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:35:22.00#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:35:22.00#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:35:22.00#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:35:22.00#ibcon#first serial, iclass 11, count 0 2006.201.05:35:22.00#ibcon#enter sib2, iclass 11, count 0 2006.201.05:35:22.00#ibcon#flushed, iclass 11, count 0 2006.201.05:35:22.00#ibcon#about to write, iclass 11, count 0 2006.201.05:35:22.00#ibcon#wrote, iclass 11, count 0 2006.201.05:35:22.00#ibcon#about to read 3, iclass 11, count 0 2006.201.05:35:22.02#ibcon#read 3, iclass 11, count 0 2006.201.05:35:22.02#ibcon#about to read 4, iclass 11, count 0 2006.201.05:35:22.02#ibcon#read 4, iclass 11, count 0 2006.201.05:35:22.02#ibcon#about to read 5, iclass 11, count 0 2006.201.05:35:22.02#ibcon#read 5, iclass 11, count 0 2006.201.05:35:22.02#ibcon#about to read 6, iclass 11, count 0 2006.201.05:35:22.02#ibcon#read 6, iclass 11, count 0 2006.201.05:35:22.02#ibcon#end of sib2, iclass 11, count 0 2006.201.05:35:22.02#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:35:22.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:35:22.02#ibcon#[25=USB\r\n] 2006.201.05:35:22.02#ibcon#*before write, iclass 11, count 0 2006.201.05:35:22.02#ibcon#enter sib2, iclass 11, count 0 2006.201.05:35:22.02#ibcon#flushed, iclass 11, count 0 2006.201.05:35:22.02#ibcon#about to write, iclass 11, count 0 2006.201.05:35:22.02#ibcon#wrote, iclass 11, count 0 2006.201.05:35:22.02#ibcon#about to read 3, iclass 11, count 0 2006.201.05:35:22.05#ibcon#read 3, iclass 11, count 0 2006.201.05:35:22.05#ibcon#about to read 4, iclass 11, count 0 2006.201.05:35:22.05#ibcon#read 4, iclass 11, count 0 2006.201.05:35:22.05#ibcon#about to read 5, iclass 11, count 0 2006.201.05:35:22.05#ibcon#read 5, iclass 11, count 0 2006.201.05:35:22.05#ibcon#about to read 6, iclass 11, count 0 2006.201.05:35:22.05#ibcon#read 6, iclass 11, count 0 2006.201.05:35:22.05#ibcon#end of sib2, iclass 11, count 0 2006.201.05:35:22.05#ibcon#*after write, iclass 11, count 0 2006.201.05:35:22.05#ibcon#*before return 0, iclass 11, count 0 2006.201.05:35:22.05#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:35:22.05#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:35:22.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:35:22.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:35:22.05$vck44/vblo=1,629.99 2006.201.05:35:22.05#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.05:35:22.05#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.05:35:22.05#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:22.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:35:22.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:35:22.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:35:22.05#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:35:22.05#ibcon#first serial, iclass 13, count 0 2006.201.05:35:22.05#ibcon#enter sib2, iclass 13, count 0 2006.201.05:35:22.05#ibcon#flushed, iclass 13, count 0 2006.201.05:35:22.05#ibcon#about to write, iclass 13, count 0 2006.201.05:35:22.05#ibcon#wrote, iclass 13, count 0 2006.201.05:35:22.05#ibcon#about to read 3, iclass 13, count 0 2006.201.05:35:22.07#ibcon#read 3, iclass 13, count 0 2006.201.05:35:22.07#ibcon#about to read 4, iclass 13, count 0 2006.201.05:35:22.07#ibcon#read 4, iclass 13, count 0 2006.201.05:35:22.07#ibcon#about to read 5, iclass 13, count 0 2006.201.05:35:22.07#ibcon#read 5, iclass 13, count 0 2006.201.05:35:22.07#ibcon#about to read 6, iclass 13, count 0 2006.201.05:35:22.07#ibcon#read 6, iclass 13, count 0 2006.201.05:35:22.07#ibcon#end of sib2, iclass 13, count 0 2006.201.05:35:22.07#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:35:22.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:35:22.07#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:35:22.07#ibcon#*before write, iclass 13, count 0 2006.201.05:35:22.07#ibcon#enter sib2, iclass 13, count 0 2006.201.05:35:22.07#ibcon#flushed, iclass 13, count 0 2006.201.05:35:22.07#ibcon#about to write, iclass 13, count 0 2006.201.05:35:22.07#ibcon#wrote, iclass 13, count 0 2006.201.05:35:22.07#ibcon#about to read 3, iclass 13, count 0 2006.201.05:35:22.11#ibcon#read 3, iclass 13, count 0 2006.201.05:35:22.11#ibcon#about to read 4, iclass 13, count 0 2006.201.05:35:22.11#ibcon#read 4, iclass 13, count 0 2006.201.05:35:22.11#ibcon#about to read 5, iclass 13, count 0 2006.201.05:35:22.11#ibcon#read 5, iclass 13, count 0 2006.201.05:35:22.11#ibcon#about to read 6, iclass 13, count 0 2006.201.05:35:22.11#ibcon#read 6, iclass 13, count 0 2006.201.05:35:22.11#ibcon#end of sib2, iclass 13, count 0 2006.201.05:35:22.11#ibcon#*after write, iclass 13, count 0 2006.201.05:35:22.11#ibcon#*before return 0, iclass 13, count 0 2006.201.05:35:22.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:35:22.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:35:22.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:35:22.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:35:22.11$vck44/vb=1,4 2006.201.05:35:22.11#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.05:35:22.11#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.05:35:22.11#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:22.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:35:22.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:35:22.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:35:22.11#ibcon#enter wrdev, iclass 15, count 2 2006.201.05:35:22.11#ibcon#first serial, iclass 15, count 2 2006.201.05:35:22.11#ibcon#enter sib2, iclass 15, count 2 2006.201.05:35:22.11#ibcon#flushed, iclass 15, count 2 2006.201.05:35:22.11#ibcon#about to write, iclass 15, count 2 2006.201.05:35:22.11#ibcon#wrote, iclass 15, count 2 2006.201.05:35:22.11#ibcon#about to read 3, iclass 15, count 2 2006.201.05:35:22.13#ibcon#read 3, iclass 15, count 2 2006.201.05:35:22.13#ibcon#about to read 4, iclass 15, count 2 2006.201.05:35:22.13#ibcon#read 4, iclass 15, count 2 2006.201.05:35:22.13#ibcon#about to read 5, iclass 15, count 2 2006.201.05:35:22.13#ibcon#read 5, iclass 15, count 2 2006.201.05:35:22.13#ibcon#about to read 6, iclass 15, count 2 2006.201.05:35:22.13#ibcon#read 6, iclass 15, count 2 2006.201.05:35:22.13#ibcon#end of sib2, iclass 15, count 2 2006.201.05:35:22.13#ibcon#*mode == 0, iclass 15, count 2 2006.201.05:35:22.13#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.05:35:22.13#ibcon#[27=AT01-04\r\n] 2006.201.05:35:22.13#ibcon#*before write, iclass 15, count 2 2006.201.05:35:22.13#ibcon#enter sib2, iclass 15, count 2 2006.201.05:35:22.13#ibcon#flushed, iclass 15, count 2 2006.201.05:35:22.13#ibcon#about to write, iclass 15, count 2 2006.201.05:35:22.13#ibcon#wrote, iclass 15, count 2 2006.201.05:35:22.13#ibcon#about to read 3, iclass 15, count 2 2006.201.05:35:22.16#ibcon#read 3, iclass 15, count 2 2006.201.05:35:22.16#ibcon#about to read 4, iclass 15, count 2 2006.201.05:35:22.16#ibcon#read 4, iclass 15, count 2 2006.201.05:35:22.16#ibcon#about to read 5, iclass 15, count 2 2006.201.05:35:22.16#ibcon#read 5, iclass 15, count 2 2006.201.05:35:22.16#ibcon#about to read 6, iclass 15, count 2 2006.201.05:35:22.16#ibcon#read 6, iclass 15, count 2 2006.201.05:35:22.16#ibcon#end of sib2, iclass 15, count 2 2006.201.05:35:22.16#ibcon#*after write, iclass 15, count 2 2006.201.05:35:22.16#ibcon#*before return 0, iclass 15, count 2 2006.201.05:35:22.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:35:22.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:35:22.16#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.05:35:22.16#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:22.16#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:35:22.28#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:35:22.28#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:35:22.28#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:35:22.28#ibcon#first serial, iclass 15, count 0 2006.201.05:35:22.28#ibcon#enter sib2, iclass 15, count 0 2006.201.05:35:22.28#ibcon#flushed, iclass 15, count 0 2006.201.05:35:22.28#ibcon#about to write, iclass 15, count 0 2006.201.05:35:22.28#ibcon#wrote, iclass 15, count 0 2006.201.05:35:22.28#ibcon#about to read 3, iclass 15, count 0 2006.201.05:35:22.30#ibcon#read 3, iclass 15, count 0 2006.201.05:35:22.30#ibcon#about to read 4, iclass 15, count 0 2006.201.05:35:22.30#ibcon#read 4, iclass 15, count 0 2006.201.05:35:22.30#ibcon#about to read 5, iclass 15, count 0 2006.201.05:35:22.30#ibcon#read 5, iclass 15, count 0 2006.201.05:35:22.30#ibcon#about to read 6, iclass 15, count 0 2006.201.05:35:22.30#ibcon#read 6, iclass 15, count 0 2006.201.05:35:22.30#ibcon#end of sib2, iclass 15, count 0 2006.201.05:35:22.30#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:35:22.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:35:22.30#ibcon#[27=USB\r\n] 2006.201.05:35:22.30#ibcon#*before write, iclass 15, count 0 2006.201.05:35:22.30#ibcon#enter sib2, iclass 15, count 0 2006.201.05:35:22.30#ibcon#flushed, iclass 15, count 0 2006.201.05:35:22.30#ibcon#about to write, iclass 15, count 0 2006.201.05:35:22.30#ibcon#wrote, iclass 15, count 0 2006.201.05:35:22.30#ibcon#about to read 3, iclass 15, count 0 2006.201.05:35:22.33#ibcon#read 3, iclass 15, count 0 2006.201.05:35:22.33#ibcon#about to read 4, iclass 15, count 0 2006.201.05:35:22.33#ibcon#read 4, iclass 15, count 0 2006.201.05:35:22.33#ibcon#about to read 5, iclass 15, count 0 2006.201.05:35:22.33#ibcon#read 5, iclass 15, count 0 2006.201.05:35:22.33#ibcon#about to read 6, iclass 15, count 0 2006.201.05:35:22.33#ibcon#read 6, iclass 15, count 0 2006.201.05:35:22.33#ibcon#end of sib2, iclass 15, count 0 2006.201.05:35:22.33#ibcon#*after write, iclass 15, count 0 2006.201.05:35:22.33#ibcon#*before return 0, iclass 15, count 0 2006.201.05:35:22.33#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:35:22.33#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:35:22.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:35:22.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:35:22.33$vck44/vblo=2,634.99 2006.201.05:35:22.33#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.05:35:22.33#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.05:35:22.33#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:22.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:22.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:22.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:22.33#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:35:22.33#ibcon#first serial, iclass 17, count 0 2006.201.05:35:22.33#ibcon#enter sib2, iclass 17, count 0 2006.201.05:35:22.33#ibcon#flushed, iclass 17, count 0 2006.201.05:35:22.33#ibcon#about to write, iclass 17, count 0 2006.201.05:35:22.33#ibcon#wrote, iclass 17, count 0 2006.201.05:35:22.33#ibcon#about to read 3, iclass 17, count 0 2006.201.05:35:22.35#ibcon#read 3, iclass 17, count 0 2006.201.05:35:22.35#ibcon#about to read 4, iclass 17, count 0 2006.201.05:35:22.35#ibcon#read 4, iclass 17, count 0 2006.201.05:35:22.35#ibcon#about to read 5, iclass 17, count 0 2006.201.05:35:22.35#ibcon#read 5, iclass 17, count 0 2006.201.05:35:22.35#ibcon#about to read 6, iclass 17, count 0 2006.201.05:35:22.35#ibcon#read 6, iclass 17, count 0 2006.201.05:35:22.35#ibcon#end of sib2, iclass 17, count 0 2006.201.05:35:22.35#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:35:22.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:35:22.35#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:35:22.35#ibcon#*before write, iclass 17, count 0 2006.201.05:35:22.35#ibcon#enter sib2, iclass 17, count 0 2006.201.05:35:22.35#ibcon#flushed, iclass 17, count 0 2006.201.05:35:22.35#ibcon#about to write, iclass 17, count 0 2006.201.05:35:22.35#ibcon#wrote, iclass 17, count 0 2006.201.05:35:22.35#ibcon#about to read 3, iclass 17, count 0 2006.201.05:35:22.39#ibcon#read 3, iclass 17, count 0 2006.201.05:35:22.39#ibcon#about to read 4, iclass 17, count 0 2006.201.05:35:22.39#ibcon#read 4, iclass 17, count 0 2006.201.05:35:22.39#ibcon#about to read 5, iclass 17, count 0 2006.201.05:35:22.39#ibcon#read 5, iclass 17, count 0 2006.201.05:35:22.39#ibcon#about to read 6, iclass 17, count 0 2006.201.05:35:22.39#ibcon#read 6, iclass 17, count 0 2006.201.05:35:22.39#ibcon#end of sib2, iclass 17, count 0 2006.201.05:35:22.39#ibcon#*after write, iclass 17, count 0 2006.201.05:35:22.39#ibcon#*before return 0, iclass 17, count 0 2006.201.05:35:22.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:22.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:35:22.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:35:22.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:35:22.39$vck44/vb=2,5 2006.201.05:35:22.39#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.05:35:22.39#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.05:35:22.39#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:22.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:22.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:22.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:22.45#ibcon#enter wrdev, iclass 19, count 2 2006.201.05:35:22.45#ibcon#first serial, iclass 19, count 2 2006.201.05:35:22.45#ibcon#enter sib2, iclass 19, count 2 2006.201.05:35:22.45#ibcon#flushed, iclass 19, count 2 2006.201.05:35:22.45#ibcon#about to write, iclass 19, count 2 2006.201.05:35:22.45#ibcon#wrote, iclass 19, count 2 2006.201.05:35:22.45#ibcon#about to read 3, iclass 19, count 2 2006.201.05:35:22.47#ibcon#read 3, iclass 19, count 2 2006.201.05:35:22.47#ibcon#about to read 4, iclass 19, count 2 2006.201.05:35:22.47#ibcon#read 4, iclass 19, count 2 2006.201.05:35:22.47#ibcon#about to read 5, iclass 19, count 2 2006.201.05:35:22.47#ibcon#read 5, iclass 19, count 2 2006.201.05:35:22.47#ibcon#about to read 6, iclass 19, count 2 2006.201.05:35:22.47#ibcon#read 6, iclass 19, count 2 2006.201.05:35:22.47#ibcon#end of sib2, iclass 19, count 2 2006.201.05:35:22.47#ibcon#*mode == 0, iclass 19, count 2 2006.201.05:35:22.47#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.05:35:22.47#ibcon#[27=AT02-05\r\n] 2006.201.05:35:22.47#ibcon#*before write, iclass 19, count 2 2006.201.05:35:22.47#ibcon#enter sib2, iclass 19, count 2 2006.201.05:35:22.47#ibcon#flushed, iclass 19, count 2 2006.201.05:35:22.47#ibcon#about to write, iclass 19, count 2 2006.201.05:35:22.47#ibcon#wrote, iclass 19, count 2 2006.201.05:35:22.47#ibcon#about to read 3, iclass 19, count 2 2006.201.05:35:22.50#ibcon#read 3, iclass 19, count 2 2006.201.05:35:22.57#ibcon#about to read 4, iclass 19, count 2 2006.201.05:35:22.57#ibcon#read 4, iclass 19, count 2 2006.201.05:35:22.57#ibcon#about to read 5, iclass 19, count 2 2006.201.05:35:22.57#ibcon#read 5, iclass 19, count 2 2006.201.05:35:22.57#ibcon#about to read 6, iclass 19, count 2 2006.201.05:35:22.57#ibcon#read 6, iclass 19, count 2 2006.201.05:35:22.58#ibcon#end of sib2, iclass 19, count 2 2006.201.05:35:22.58#ibcon#*after write, iclass 19, count 2 2006.201.05:35:22.58#ibcon#*before return 0, iclass 19, count 2 2006.201.05:35:22.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:22.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:35:22.58#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.05:35:22.58#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:22.58#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:22.70#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:22.70#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:22.70#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:35:22.70#ibcon#first serial, iclass 19, count 0 2006.201.05:35:22.70#ibcon#enter sib2, iclass 19, count 0 2006.201.05:35:22.70#ibcon#flushed, iclass 19, count 0 2006.201.05:35:22.70#ibcon#about to write, iclass 19, count 0 2006.201.05:35:22.70#ibcon#wrote, iclass 19, count 0 2006.201.05:35:22.70#ibcon#about to read 3, iclass 19, count 0 2006.201.05:35:22.72#ibcon#read 3, iclass 19, count 0 2006.201.05:35:22.72#ibcon#about to read 4, iclass 19, count 0 2006.201.05:35:22.72#ibcon#read 4, iclass 19, count 0 2006.201.05:35:22.72#ibcon#about to read 5, iclass 19, count 0 2006.201.05:35:22.72#ibcon#read 5, iclass 19, count 0 2006.201.05:35:22.72#ibcon#about to read 6, iclass 19, count 0 2006.201.05:35:22.72#ibcon#read 6, iclass 19, count 0 2006.201.05:35:22.72#ibcon#end of sib2, iclass 19, count 0 2006.201.05:35:22.72#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:35:22.72#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:35:22.72#ibcon#[27=USB\r\n] 2006.201.05:35:22.72#ibcon#*before write, iclass 19, count 0 2006.201.05:35:22.72#ibcon#enter sib2, iclass 19, count 0 2006.201.05:35:22.72#ibcon#flushed, iclass 19, count 0 2006.201.05:35:22.72#ibcon#about to write, iclass 19, count 0 2006.201.05:35:22.72#ibcon#wrote, iclass 19, count 0 2006.201.05:35:22.72#ibcon#about to read 3, iclass 19, count 0 2006.201.05:35:22.75#ibcon#read 3, iclass 19, count 0 2006.201.05:35:22.75#ibcon#about to read 4, iclass 19, count 0 2006.201.05:35:22.75#ibcon#read 4, iclass 19, count 0 2006.201.05:35:22.75#ibcon#about to read 5, iclass 19, count 0 2006.201.05:35:22.75#ibcon#read 5, iclass 19, count 0 2006.201.05:35:22.75#ibcon#about to read 6, iclass 19, count 0 2006.201.05:35:22.75#ibcon#read 6, iclass 19, count 0 2006.201.05:35:22.75#ibcon#end of sib2, iclass 19, count 0 2006.201.05:35:22.75#ibcon#*after write, iclass 19, count 0 2006.201.05:35:22.75#ibcon#*before return 0, iclass 19, count 0 2006.201.05:35:22.75#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:22.75#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:35:22.75#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:35:22.75#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:35:22.75$vck44/vblo=3,649.99 2006.201.05:35:22.75#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.05:35:22.75#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.05:35:22.75#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:22.75#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:22.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:22.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:22.75#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:35:22.75#ibcon#first serial, iclass 21, count 0 2006.201.05:35:22.75#ibcon#enter sib2, iclass 21, count 0 2006.201.05:35:22.75#ibcon#flushed, iclass 21, count 0 2006.201.05:35:22.75#ibcon#about to write, iclass 21, count 0 2006.201.05:35:22.75#ibcon#wrote, iclass 21, count 0 2006.201.05:35:22.75#ibcon#about to read 3, iclass 21, count 0 2006.201.05:35:22.77#ibcon#read 3, iclass 21, count 0 2006.201.05:35:22.77#ibcon#about to read 4, iclass 21, count 0 2006.201.05:35:22.77#ibcon#read 4, iclass 21, count 0 2006.201.05:35:22.77#ibcon#about to read 5, iclass 21, count 0 2006.201.05:35:22.77#ibcon#read 5, iclass 21, count 0 2006.201.05:35:22.77#ibcon#about to read 6, iclass 21, count 0 2006.201.05:35:22.77#ibcon#read 6, iclass 21, count 0 2006.201.05:35:22.77#ibcon#end of sib2, iclass 21, count 0 2006.201.05:35:22.77#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:35:22.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:35:22.77#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:35:22.77#ibcon#*before write, iclass 21, count 0 2006.201.05:35:22.77#ibcon#enter sib2, iclass 21, count 0 2006.201.05:35:22.77#ibcon#flushed, iclass 21, count 0 2006.201.05:35:22.77#ibcon#about to write, iclass 21, count 0 2006.201.05:35:22.77#ibcon#wrote, iclass 21, count 0 2006.201.05:35:22.77#ibcon#about to read 3, iclass 21, count 0 2006.201.05:35:22.81#ibcon#read 3, iclass 21, count 0 2006.201.05:35:22.81#ibcon#about to read 4, iclass 21, count 0 2006.201.05:35:22.81#ibcon#read 4, iclass 21, count 0 2006.201.05:35:22.81#ibcon#about to read 5, iclass 21, count 0 2006.201.05:35:22.81#ibcon#read 5, iclass 21, count 0 2006.201.05:35:22.81#ibcon#about to read 6, iclass 21, count 0 2006.201.05:35:22.81#ibcon#read 6, iclass 21, count 0 2006.201.05:35:22.81#ibcon#end of sib2, iclass 21, count 0 2006.201.05:35:22.81#ibcon#*after write, iclass 21, count 0 2006.201.05:35:22.81#ibcon#*before return 0, iclass 21, count 0 2006.201.05:35:22.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:22.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:35:22.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:35:22.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:35:22.81$vck44/vb=3,4 2006.201.05:35:22.81#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.05:35:22.81#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.05:35:22.81#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:22.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:22.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:22.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:22.87#ibcon#enter wrdev, iclass 23, count 2 2006.201.05:35:22.87#ibcon#first serial, iclass 23, count 2 2006.201.05:35:22.87#ibcon#enter sib2, iclass 23, count 2 2006.201.05:35:22.87#ibcon#flushed, iclass 23, count 2 2006.201.05:35:22.87#ibcon#about to write, iclass 23, count 2 2006.201.05:35:22.87#ibcon#wrote, iclass 23, count 2 2006.201.05:35:22.87#ibcon#about to read 3, iclass 23, count 2 2006.201.05:35:22.89#ibcon#read 3, iclass 23, count 2 2006.201.05:35:22.89#ibcon#about to read 4, iclass 23, count 2 2006.201.05:35:22.89#ibcon#read 4, iclass 23, count 2 2006.201.05:35:22.89#ibcon#about to read 5, iclass 23, count 2 2006.201.05:35:22.89#ibcon#read 5, iclass 23, count 2 2006.201.05:35:22.89#ibcon#about to read 6, iclass 23, count 2 2006.201.05:35:22.89#ibcon#read 6, iclass 23, count 2 2006.201.05:35:22.89#ibcon#end of sib2, iclass 23, count 2 2006.201.05:35:22.89#ibcon#*mode == 0, iclass 23, count 2 2006.201.05:35:22.89#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.05:35:22.89#ibcon#[27=AT03-04\r\n] 2006.201.05:35:22.89#ibcon#*before write, iclass 23, count 2 2006.201.05:35:22.89#ibcon#enter sib2, iclass 23, count 2 2006.201.05:35:22.89#ibcon#flushed, iclass 23, count 2 2006.201.05:35:22.89#ibcon#about to write, iclass 23, count 2 2006.201.05:35:22.89#ibcon#wrote, iclass 23, count 2 2006.201.05:35:22.89#ibcon#about to read 3, iclass 23, count 2 2006.201.05:35:22.92#ibcon#read 3, iclass 23, count 2 2006.201.05:35:22.92#ibcon#about to read 4, iclass 23, count 2 2006.201.05:35:22.92#ibcon#read 4, iclass 23, count 2 2006.201.05:35:22.92#ibcon#about to read 5, iclass 23, count 2 2006.201.05:35:22.92#ibcon#read 5, iclass 23, count 2 2006.201.05:35:22.92#ibcon#about to read 6, iclass 23, count 2 2006.201.05:35:22.92#ibcon#read 6, iclass 23, count 2 2006.201.05:35:22.92#ibcon#end of sib2, iclass 23, count 2 2006.201.05:35:22.92#ibcon#*after write, iclass 23, count 2 2006.201.05:35:22.92#ibcon#*before return 0, iclass 23, count 2 2006.201.05:35:22.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:22.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:35:22.92#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.05:35:22.92#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:22.92#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:23.04#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:23.04#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:23.04#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:35:23.04#ibcon#first serial, iclass 23, count 0 2006.201.05:35:23.04#ibcon#enter sib2, iclass 23, count 0 2006.201.05:35:23.04#ibcon#flushed, iclass 23, count 0 2006.201.05:35:23.04#ibcon#about to write, iclass 23, count 0 2006.201.05:35:23.04#ibcon#wrote, iclass 23, count 0 2006.201.05:35:23.04#ibcon#about to read 3, iclass 23, count 0 2006.201.05:35:23.06#ibcon#read 3, iclass 23, count 0 2006.201.05:35:23.06#ibcon#about to read 4, iclass 23, count 0 2006.201.05:35:23.06#ibcon#read 4, iclass 23, count 0 2006.201.05:35:23.06#ibcon#about to read 5, iclass 23, count 0 2006.201.05:35:23.06#ibcon#read 5, iclass 23, count 0 2006.201.05:35:23.06#ibcon#about to read 6, iclass 23, count 0 2006.201.05:35:23.06#ibcon#read 6, iclass 23, count 0 2006.201.05:35:23.06#ibcon#end of sib2, iclass 23, count 0 2006.201.05:35:23.06#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:35:23.06#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:35:23.06#ibcon#[27=USB\r\n] 2006.201.05:35:23.06#ibcon#*before write, iclass 23, count 0 2006.201.05:35:23.06#ibcon#enter sib2, iclass 23, count 0 2006.201.05:35:23.06#ibcon#flushed, iclass 23, count 0 2006.201.05:35:23.06#ibcon#about to write, iclass 23, count 0 2006.201.05:35:23.06#ibcon#wrote, iclass 23, count 0 2006.201.05:35:23.06#ibcon#about to read 3, iclass 23, count 0 2006.201.05:35:23.09#ibcon#read 3, iclass 23, count 0 2006.201.05:35:23.09#ibcon#about to read 4, iclass 23, count 0 2006.201.05:35:23.09#ibcon#read 4, iclass 23, count 0 2006.201.05:35:23.09#ibcon#about to read 5, iclass 23, count 0 2006.201.05:35:23.09#ibcon#read 5, iclass 23, count 0 2006.201.05:35:23.09#ibcon#about to read 6, iclass 23, count 0 2006.201.05:35:23.09#ibcon#read 6, iclass 23, count 0 2006.201.05:35:23.09#ibcon#end of sib2, iclass 23, count 0 2006.201.05:35:23.09#ibcon#*after write, iclass 23, count 0 2006.201.05:35:23.09#ibcon#*before return 0, iclass 23, count 0 2006.201.05:35:23.09#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:23.09#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:35:23.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:35:23.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:35:23.09$vck44/vblo=4,679.99 2006.201.05:35:23.09#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.05:35:23.09#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.05:35:23.09#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:23.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:23.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:23.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:23.09#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:35:23.09#ibcon#first serial, iclass 25, count 0 2006.201.05:35:23.09#ibcon#enter sib2, iclass 25, count 0 2006.201.05:35:23.09#ibcon#flushed, iclass 25, count 0 2006.201.05:35:23.09#ibcon#about to write, iclass 25, count 0 2006.201.05:35:23.09#ibcon#wrote, iclass 25, count 0 2006.201.05:35:23.09#ibcon#about to read 3, iclass 25, count 0 2006.201.05:35:23.11#ibcon#read 3, iclass 25, count 0 2006.201.05:35:23.11#ibcon#about to read 4, iclass 25, count 0 2006.201.05:35:23.11#ibcon#read 4, iclass 25, count 0 2006.201.05:35:23.11#ibcon#about to read 5, iclass 25, count 0 2006.201.05:35:23.11#ibcon#read 5, iclass 25, count 0 2006.201.05:35:23.11#ibcon#about to read 6, iclass 25, count 0 2006.201.05:35:23.11#ibcon#read 6, iclass 25, count 0 2006.201.05:35:23.11#ibcon#end of sib2, iclass 25, count 0 2006.201.05:35:23.11#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:35:23.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:35:23.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:35:23.11#ibcon#*before write, iclass 25, count 0 2006.201.05:35:23.11#ibcon#enter sib2, iclass 25, count 0 2006.201.05:35:23.11#ibcon#flushed, iclass 25, count 0 2006.201.05:35:23.11#ibcon#about to write, iclass 25, count 0 2006.201.05:35:23.11#ibcon#wrote, iclass 25, count 0 2006.201.05:35:23.11#ibcon#about to read 3, iclass 25, count 0 2006.201.05:35:23.16#ibcon#read 3, iclass 25, count 0 2006.201.05:35:23.16#ibcon#about to read 4, iclass 25, count 0 2006.201.05:35:23.16#ibcon#read 4, iclass 25, count 0 2006.201.05:35:23.16#ibcon#about to read 5, iclass 25, count 0 2006.201.05:35:23.16#ibcon#read 5, iclass 25, count 0 2006.201.05:35:23.16#ibcon#about to read 6, iclass 25, count 0 2006.201.05:35:23.16#ibcon#read 6, iclass 25, count 0 2006.201.05:35:23.16#ibcon#end of sib2, iclass 25, count 0 2006.201.05:35:23.16#ibcon#*after write, iclass 25, count 0 2006.201.05:35:23.16#ibcon#*before return 0, iclass 25, count 0 2006.201.05:35:23.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:23.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:35:23.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:35:23.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:35:23.16$vck44/vb=4,5 2006.201.05:35:23.16#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.05:35:23.16#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.05:35:23.16#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:23.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:23.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:23.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:23.21#ibcon#enter wrdev, iclass 27, count 2 2006.201.05:35:23.21#ibcon#first serial, iclass 27, count 2 2006.201.05:35:23.21#ibcon#enter sib2, iclass 27, count 2 2006.201.05:35:23.21#ibcon#flushed, iclass 27, count 2 2006.201.05:35:23.21#ibcon#about to write, iclass 27, count 2 2006.201.05:35:23.21#ibcon#wrote, iclass 27, count 2 2006.201.05:35:23.21#ibcon#about to read 3, iclass 27, count 2 2006.201.05:35:23.23#ibcon#read 3, iclass 27, count 2 2006.201.05:35:23.23#ibcon#about to read 4, iclass 27, count 2 2006.201.05:35:23.23#ibcon#read 4, iclass 27, count 2 2006.201.05:35:23.23#ibcon#about to read 5, iclass 27, count 2 2006.201.05:35:23.23#ibcon#read 5, iclass 27, count 2 2006.201.05:35:23.23#ibcon#about to read 6, iclass 27, count 2 2006.201.05:35:23.23#ibcon#read 6, iclass 27, count 2 2006.201.05:35:23.23#ibcon#end of sib2, iclass 27, count 2 2006.201.05:35:23.23#ibcon#*mode == 0, iclass 27, count 2 2006.201.05:35:23.23#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.05:35:23.23#ibcon#[27=AT04-05\r\n] 2006.201.05:35:23.23#ibcon#*before write, iclass 27, count 2 2006.201.05:35:23.23#ibcon#enter sib2, iclass 27, count 2 2006.201.05:35:23.23#ibcon#flushed, iclass 27, count 2 2006.201.05:35:23.23#ibcon#about to write, iclass 27, count 2 2006.201.05:35:23.23#ibcon#wrote, iclass 27, count 2 2006.201.05:35:23.23#ibcon#about to read 3, iclass 27, count 2 2006.201.05:35:23.26#ibcon#read 3, iclass 27, count 2 2006.201.05:35:23.26#ibcon#about to read 4, iclass 27, count 2 2006.201.05:35:23.26#ibcon#read 4, iclass 27, count 2 2006.201.05:35:23.26#ibcon#about to read 5, iclass 27, count 2 2006.201.05:35:23.26#ibcon#read 5, iclass 27, count 2 2006.201.05:35:23.26#ibcon#about to read 6, iclass 27, count 2 2006.201.05:35:23.26#ibcon#read 6, iclass 27, count 2 2006.201.05:35:23.26#ibcon#end of sib2, iclass 27, count 2 2006.201.05:35:23.26#ibcon#*after write, iclass 27, count 2 2006.201.05:35:23.26#ibcon#*before return 0, iclass 27, count 2 2006.201.05:35:23.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:23.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:35:23.26#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.05:35:23.26#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:23.26#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:23.38#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:23.38#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:23.38#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:35:23.38#ibcon#first serial, iclass 27, count 0 2006.201.05:35:23.38#ibcon#enter sib2, iclass 27, count 0 2006.201.05:35:23.38#ibcon#flushed, iclass 27, count 0 2006.201.05:35:23.38#ibcon#about to write, iclass 27, count 0 2006.201.05:35:23.38#ibcon#wrote, iclass 27, count 0 2006.201.05:35:23.38#ibcon#about to read 3, iclass 27, count 0 2006.201.05:35:23.40#ibcon#read 3, iclass 27, count 0 2006.201.05:35:23.40#ibcon#about to read 4, iclass 27, count 0 2006.201.05:35:23.40#ibcon#read 4, iclass 27, count 0 2006.201.05:35:23.40#ibcon#about to read 5, iclass 27, count 0 2006.201.05:35:23.40#ibcon#read 5, iclass 27, count 0 2006.201.05:35:23.40#ibcon#about to read 6, iclass 27, count 0 2006.201.05:35:23.40#ibcon#read 6, iclass 27, count 0 2006.201.05:35:23.40#ibcon#end of sib2, iclass 27, count 0 2006.201.05:35:23.40#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:35:23.40#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:35:23.40#ibcon#[27=USB\r\n] 2006.201.05:35:23.40#ibcon#*before write, iclass 27, count 0 2006.201.05:35:23.40#ibcon#enter sib2, iclass 27, count 0 2006.201.05:35:23.40#ibcon#flushed, iclass 27, count 0 2006.201.05:35:23.40#ibcon#about to write, iclass 27, count 0 2006.201.05:35:23.40#ibcon#wrote, iclass 27, count 0 2006.201.05:35:23.40#ibcon#about to read 3, iclass 27, count 0 2006.201.05:35:23.43#ibcon#read 3, iclass 27, count 0 2006.201.05:35:23.43#ibcon#about to read 4, iclass 27, count 0 2006.201.05:35:23.43#ibcon#read 4, iclass 27, count 0 2006.201.05:35:23.43#ibcon#about to read 5, iclass 27, count 0 2006.201.05:35:23.43#ibcon#read 5, iclass 27, count 0 2006.201.05:35:23.43#ibcon#about to read 6, iclass 27, count 0 2006.201.05:35:23.43#ibcon#read 6, iclass 27, count 0 2006.201.05:35:23.43#ibcon#end of sib2, iclass 27, count 0 2006.201.05:35:23.43#ibcon#*after write, iclass 27, count 0 2006.201.05:35:23.43#ibcon#*before return 0, iclass 27, count 0 2006.201.05:35:23.43#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:23.43#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:35:23.43#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:35:23.43#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:35:23.43$vck44/vblo=5,709.99 2006.201.05:35:23.43#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:35:23.43#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:35:23.43#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:23.43#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:23.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:23.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:23.43#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:35:23.43#ibcon#first serial, iclass 29, count 0 2006.201.05:35:23.43#ibcon#enter sib2, iclass 29, count 0 2006.201.05:35:23.43#ibcon#flushed, iclass 29, count 0 2006.201.05:35:23.43#ibcon#about to write, iclass 29, count 0 2006.201.05:35:23.43#ibcon#wrote, iclass 29, count 0 2006.201.05:35:23.43#ibcon#about to read 3, iclass 29, count 0 2006.201.05:35:23.45#ibcon#read 3, iclass 29, count 0 2006.201.05:35:23.45#ibcon#about to read 4, iclass 29, count 0 2006.201.05:35:23.45#ibcon#read 4, iclass 29, count 0 2006.201.05:35:23.45#ibcon#about to read 5, iclass 29, count 0 2006.201.05:35:23.45#ibcon#read 5, iclass 29, count 0 2006.201.05:35:23.45#ibcon#about to read 6, iclass 29, count 0 2006.201.05:35:23.45#ibcon#read 6, iclass 29, count 0 2006.201.05:35:23.45#ibcon#end of sib2, iclass 29, count 0 2006.201.05:35:23.45#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:35:23.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:35:23.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:35:23.45#ibcon#*before write, iclass 29, count 0 2006.201.05:35:23.45#ibcon#enter sib2, iclass 29, count 0 2006.201.05:35:23.45#ibcon#flushed, iclass 29, count 0 2006.201.05:35:23.45#ibcon#about to write, iclass 29, count 0 2006.201.05:35:23.45#ibcon#wrote, iclass 29, count 0 2006.201.05:35:23.45#ibcon#about to read 3, iclass 29, count 0 2006.201.05:35:23.49#ibcon#read 3, iclass 29, count 0 2006.201.05:35:23.49#ibcon#about to read 4, iclass 29, count 0 2006.201.05:35:23.49#ibcon#read 4, iclass 29, count 0 2006.201.05:35:23.49#ibcon#about to read 5, iclass 29, count 0 2006.201.05:35:23.49#ibcon#read 5, iclass 29, count 0 2006.201.05:35:23.49#ibcon#about to read 6, iclass 29, count 0 2006.201.05:35:23.49#ibcon#read 6, iclass 29, count 0 2006.201.05:35:23.49#ibcon#end of sib2, iclass 29, count 0 2006.201.05:35:23.49#ibcon#*after write, iclass 29, count 0 2006.201.05:35:23.49#ibcon#*before return 0, iclass 29, count 0 2006.201.05:35:23.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:23.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:35:23.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:35:23.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:35:23.49$vck44/vb=5,4 2006.201.05:35:23.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.05:35:23.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.05:35:23.49#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:23.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:23.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:23.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:23.55#ibcon#enter wrdev, iclass 31, count 2 2006.201.05:35:23.55#ibcon#first serial, iclass 31, count 2 2006.201.05:35:23.55#ibcon#enter sib2, iclass 31, count 2 2006.201.05:35:23.55#ibcon#flushed, iclass 31, count 2 2006.201.05:35:23.55#ibcon#about to write, iclass 31, count 2 2006.201.05:35:23.55#ibcon#wrote, iclass 31, count 2 2006.201.05:35:23.55#ibcon#about to read 3, iclass 31, count 2 2006.201.05:35:23.57#ibcon#read 3, iclass 31, count 2 2006.201.05:35:23.57#ibcon#about to read 4, iclass 31, count 2 2006.201.05:35:23.57#ibcon#read 4, iclass 31, count 2 2006.201.05:35:23.57#ibcon#about to read 5, iclass 31, count 2 2006.201.05:35:23.57#ibcon#read 5, iclass 31, count 2 2006.201.05:35:23.57#ibcon#about to read 6, iclass 31, count 2 2006.201.05:35:23.57#ibcon#read 6, iclass 31, count 2 2006.201.05:35:23.57#ibcon#end of sib2, iclass 31, count 2 2006.201.05:35:23.57#ibcon#*mode == 0, iclass 31, count 2 2006.201.05:35:23.57#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.05:35:23.57#ibcon#[27=AT05-04\r\n] 2006.201.05:35:23.57#ibcon#*before write, iclass 31, count 2 2006.201.05:35:23.57#ibcon#enter sib2, iclass 31, count 2 2006.201.05:35:23.57#ibcon#flushed, iclass 31, count 2 2006.201.05:35:23.57#ibcon#about to write, iclass 31, count 2 2006.201.05:35:23.57#ibcon#wrote, iclass 31, count 2 2006.201.05:35:23.57#ibcon#about to read 3, iclass 31, count 2 2006.201.05:35:23.60#ibcon#read 3, iclass 31, count 2 2006.201.05:35:23.60#ibcon#about to read 4, iclass 31, count 2 2006.201.05:35:23.60#ibcon#read 4, iclass 31, count 2 2006.201.05:35:23.60#ibcon#about to read 5, iclass 31, count 2 2006.201.05:35:23.60#ibcon#read 5, iclass 31, count 2 2006.201.05:35:23.60#ibcon#about to read 6, iclass 31, count 2 2006.201.05:35:23.60#ibcon#read 6, iclass 31, count 2 2006.201.05:35:23.60#ibcon#end of sib2, iclass 31, count 2 2006.201.05:35:23.60#ibcon#*after write, iclass 31, count 2 2006.201.05:35:23.60#ibcon#*before return 0, iclass 31, count 2 2006.201.05:35:23.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:23.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:35:23.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.05:35:23.60#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:23.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:23.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:23.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:23.72#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:35:23.72#ibcon#first serial, iclass 31, count 0 2006.201.05:35:23.72#ibcon#enter sib2, iclass 31, count 0 2006.201.05:35:23.72#ibcon#flushed, iclass 31, count 0 2006.201.05:35:23.72#ibcon#about to write, iclass 31, count 0 2006.201.05:35:23.72#ibcon#wrote, iclass 31, count 0 2006.201.05:35:23.72#ibcon#about to read 3, iclass 31, count 0 2006.201.05:35:23.74#ibcon#read 3, iclass 31, count 0 2006.201.05:35:23.74#ibcon#about to read 4, iclass 31, count 0 2006.201.05:35:23.74#ibcon#read 4, iclass 31, count 0 2006.201.05:35:23.74#ibcon#about to read 5, iclass 31, count 0 2006.201.05:35:23.74#ibcon#read 5, iclass 31, count 0 2006.201.05:35:23.74#ibcon#about to read 6, iclass 31, count 0 2006.201.05:35:23.74#ibcon#read 6, iclass 31, count 0 2006.201.05:35:23.74#ibcon#end of sib2, iclass 31, count 0 2006.201.05:35:23.74#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:35:23.74#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:35:23.74#ibcon#[27=USB\r\n] 2006.201.05:35:23.74#ibcon#*before write, iclass 31, count 0 2006.201.05:35:23.74#ibcon#enter sib2, iclass 31, count 0 2006.201.05:35:23.74#ibcon#flushed, iclass 31, count 0 2006.201.05:35:23.74#ibcon#about to write, iclass 31, count 0 2006.201.05:35:23.74#ibcon#wrote, iclass 31, count 0 2006.201.05:35:23.74#ibcon#about to read 3, iclass 31, count 0 2006.201.05:35:23.77#ibcon#read 3, iclass 31, count 0 2006.201.05:35:23.77#ibcon#about to read 4, iclass 31, count 0 2006.201.05:35:23.77#ibcon#read 4, iclass 31, count 0 2006.201.05:35:23.77#ibcon#about to read 5, iclass 31, count 0 2006.201.05:35:23.77#ibcon#read 5, iclass 31, count 0 2006.201.05:35:23.77#ibcon#about to read 6, iclass 31, count 0 2006.201.05:35:23.77#ibcon#read 6, iclass 31, count 0 2006.201.05:35:23.77#ibcon#end of sib2, iclass 31, count 0 2006.201.05:35:23.77#ibcon#*after write, iclass 31, count 0 2006.201.05:35:23.77#ibcon#*before return 0, iclass 31, count 0 2006.201.05:35:23.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:23.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:35:23.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:35:23.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:35:23.77$vck44/vblo=6,719.99 2006.201.05:35:23.77#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.05:35:23.77#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.05:35:23.77#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:23.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:23.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:23.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:23.77#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:35:23.77#ibcon#first serial, iclass 33, count 0 2006.201.05:35:23.77#ibcon#enter sib2, iclass 33, count 0 2006.201.05:35:23.77#ibcon#flushed, iclass 33, count 0 2006.201.05:35:23.77#ibcon#about to write, iclass 33, count 0 2006.201.05:35:23.77#ibcon#wrote, iclass 33, count 0 2006.201.05:35:23.77#ibcon#about to read 3, iclass 33, count 0 2006.201.05:35:23.79#ibcon#read 3, iclass 33, count 0 2006.201.05:35:23.79#ibcon#about to read 4, iclass 33, count 0 2006.201.05:35:23.79#ibcon#read 4, iclass 33, count 0 2006.201.05:35:23.79#ibcon#about to read 5, iclass 33, count 0 2006.201.05:35:23.79#ibcon#read 5, iclass 33, count 0 2006.201.05:35:23.79#ibcon#about to read 6, iclass 33, count 0 2006.201.05:35:23.79#ibcon#read 6, iclass 33, count 0 2006.201.05:35:23.79#ibcon#end of sib2, iclass 33, count 0 2006.201.05:35:23.79#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:35:23.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:35:23.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:35:23.79#ibcon#*before write, iclass 33, count 0 2006.201.05:35:23.79#ibcon#enter sib2, iclass 33, count 0 2006.201.05:35:23.79#ibcon#flushed, iclass 33, count 0 2006.201.05:35:23.79#ibcon#about to write, iclass 33, count 0 2006.201.05:35:23.79#ibcon#wrote, iclass 33, count 0 2006.201.05:35:23.79#ibcon#about to read 3, iclass 33, count 0 2006.201.05:35:23.83#ibcon#read 3, iclass 33, count 0 2006.201.05:35:23.83#ibcon#about to read 4, iclass 33, count 0 2006.201.05:35:23.83#ibcon#read 4, iclass 33, count 0 2006.201.05:35:23.83#ibcon#about to read 5, iclass 33, count 0 2006.201.05:35:23.83#ibcon#read 5, iclass 33, count 0 2006.201.05:35:23.83#ibcon#about to read 6, iclass 33, count 0 2006.201.05:35:23.83#ibcon#read 6, iclass 33, count 0 2006.201.05:35:23.83#ibcon#end of sib2, iclass 33, count 0 2006.201.05:35:23.83#ibcon#*after write, iclass 33, count 0 2006.201.05:35:23.83#ibcon#*before return 0, iclass 33, count 0 2006.201.05:35:23.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:23.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:35:23.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:35:23.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:35:23.83$vck44/vb=6,4 2006.201.05:35:23.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.05:35:23.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.05:35:23.83#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:23.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:23.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:23.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:23.89#ibcon#enter wrdev, iclass 35, count 2 2006.201.05:35:23.89#ibcon#first serial, iclass 35, count 2 2006.201.05:35:23.89#ibcon#enter sib2, iclass 35, count 2 2006.201.05:35:23.89#ibcon#flushed, iclass 35, count 2 2006.201.05:35:23.89#ibcon#about to write, iclass 35, count 2 2006.201.05:35:23.89#ibcon#wrote, iclass 35, count 2 2006.201.05:35:23.89#ibcon#about to read 3, iclass 35, count 2 2006.201.05:35:23.91#ibcon#read 3, iclass 35, count 2 2006.201.05:35:23.91#ibcon#about to read 4, iclass 35, count 2 2006.201.05:35:23.91#ibcon#read 4, iclass 35, count 2 2006.201.05:35:23.91#ibcon#about to read 5, iclass 35, count 2 2006.201.05:35:23.91#ibcon#read 5, iclass 35, count 2 2006.201.05:35:23.91#ibcon#about to read 6, iclass 35, count 2 2006.201.05:35:23.91#ibcon#read 6, iclass 35, count 2 2006.201.05:35:23.91#ibcon#end of sib2, iclass 35, count 2 2006.201.05:35:23.91#ibcon#*mode == 0, iclass 35, count 2 2006.201.05:35:23.91#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.05:35:23.91#ibcon#[27=AT06-04\r\n] 2006.201.05:35:23.91#ibcon#*before write, iclass 35, count 2 2006.201.05:35:23.91#ibcon#enter sib2, iclass 35, count 2 2006.201.05:35:23.91#ibcon#flushed, iclass 35, count 2 2006.201.05:35:23.91#ibcon#about to write, iclass 35, count 2 2006.201.05:35:23.91#ibcon#wrote, iclass 35, count 2 2006.201.05:35:23.91#ibcon#about to read 3, iclass 35, count 2 2006.201.05:35:23.94#ibcon#read 3, iclass 35, count 2 2006.201.05:35:23.94#ibcon#about to read 4, iclass 35, count 2 2006.201.05:35:23.94#ibcon#read 4, iclass 35, count 2 2006.201.05:35:23.94#ibcon#about to read 5, iclass 35, count 2 2006.201.05:35:23.94#ibcon#read 5, iclass 35, count 2 2006.201.05:35:23.94#ibcon#about to read 6, iclass 35, count 2 2006.201.05:35:23.94#ibcon#read 6, iclass 35, count 2 2006.201.05:35:23.94#ibcon#end of sib2, iclass 35, count 2 2006.201.05:35:23.94#ibcon#*after write, iclass 35, count 2 2006.201.05:35:23.94#ibcon#*before return 0, iclass 35, count 2 2006.201.05:35:23.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:23.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:35:23.94#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.05:35:23.94#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:23.94#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:24.06#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:24.06#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:24.06#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:35:24.06#ibcon#first serial, iclass 35, count 0 2006.201.05:35:24.06#ibcon#enter sib2, iclass 35, count 0 2006.201.05:35:24.06#ibcon#flushed, iclass 35, count 0 2006.201.05:35:24.06#ibcon#about to write, iclass 35, count 0 2006.201.05:35:24.06#ibcon#wrote, iclass 35, count 0 2006.201.05:35:24.06#ibcon#about to read 3, iclass 35, count 0 2006.201.05:35:24.08#ibcon#read 3, iclass 35, count 0 2006.201.05:35:24.08#ibcon#about to read 4, iclass 35, count 0 2006.201.05:35:24.08#ibcon#read 4, iclass 35, count 0 2006.201.05:35:24.08#ibcon#about to read 5, iclass 35, count 0 2006.201.05:35:24.08#ibcon#read 5, iclass 35, count 0 2006.201.05:35:24.08#ibcon#about to read 6, iclass 35, count 0 2006.201.05:35:24.08#ibcon#read 6, iclass 35, count 0 2006.201.05:35:24.08#ibcon#end of sib2, iclass 35, count 0 2006.201.05:35:24.08#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:35:24.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:35:24.08#ibcon#[27=USB\r\n] 2006.201.05:35:24.08#ibcon#*before write, iclass 35, count 0 2006.201.05:35:24.08#ibcon#enter sib2, iclass 35, count 0 2006.201.05:35:24.08#ibcon#flushed, iclass 35, count 0 2006.201.05:35:24.08#ibcon#about to write, iclass 35, count 0 2006.201.05:35:24.08#ibcon#wrote, iclass 35, count 0 2006.201.05:35:24.08#ibcon#about to read 3, iclass 35, count 0 2006.201.05:35:24.11#ibcon#read 3, iclass 35, count 0 2006.201.05:35:24.11#ibcon#about to read 4, iclass 35, count 0 2006.201.05:35:24.11#ibcon#read 4, iclass 35, count 0 2006.201.05:35:24.11#ibcon#about to read 5, iclass 35, count 0 2006.201.05:35:24.11#ibcon#read 5, iclass 35, count 0 2006.201.05:35:24.11#ibcon#about to read 6, iclass 35, count 0 2006.201.05:35:24.11#ibcon#read 6, iclass 35, count 0 2006.201.05:35:24.11#ibcon#end of sib2, iclass 35, count 0 2006.201.05:35:24.11#ibcon#*after write, iclass 35, count 0 2006.201.05:35:24.11#ibcon#*before return 0, iclass 35, count 0 2006.201.05:35:24.11#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:24.11#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:35:24.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:35:24.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:35:24.11$vck44/vblo=7,734.99 2006.201.05:35:24.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.05:35:24.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.05:35:24.11#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:24.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:24.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:24.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:24.11#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:35:24.11#ibcon#first serial, iclass 37, count 0 2006.201.05:35:24.11#ibcon#enter sib2, iclass 37, count 0 2006.201.05:35:24.11#ibcon#flushed, iclass 37, count 0 2006.201.05:35:24.11#ibcon#about to write, iclass 37, count 0 2006.201.05:35:24.11#ibcon#wrote, iclass 37, count 0 2006.201.05:35:24.11#ibcon#about to read 3, iclass 37, count 0 2006.201.05:35:24.13#ibcon#read 3, iclass 37, count 0 2006.201.05:35:24.13#ibcon#about to read 4, iclass 37, count 0 2006.201.05:35:24.13#ibcon#read 4, iclass 37, count 0 2006.201.05:35:24.13#ibcon#about to read 5, iclass 37, count 0 2006.201.05:35:24.13#ibcon#read 5, iclass 37, count 0 2006.201.05:35:24.13#ibcon#about to read 6, iclass 37, count 0 2006.201.05:35:24.13#ibcon#read 6, iclass 37, count 0 2006.201.05:35:24.13#ibcon#end of sib2, iclass 37, count 0 2006.201.05:35:24.13#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:35:24.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:35:24.13#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:35:24.13#ibcon#*before write, iclass 37, count 0 2006.201.05:35:24.13#ibcon#enter sib2, iclass 37, count 0 2006.201.05:35:24.13#ibcon#flushed, iclass 37, count 0 2006.201.05:35:24.13#ibcon#about to write, iclass 37, count 0 2006.201.05:35:24.13#ibcon#wrote, iclass 37, count 0 2006.201.05:35:24.13#ibcon#about to read 3, iclass 37, count 0 2006.201.05:35:24.17#ibcon#read 3, iclass 37, count 0 2006.201.05:35:24.17#ibcon#about to read 4, iclass 37, count 0 2006.201.05:35:24.17#ibcon#read 4, iclass 37, count 0 2006.201.05:35:24.17#ibcon#about to read 5, iclass 37, count 0 2006.201.05:35:24.17#ibcon#read 5, iclass 37, count 0 2006.201.05:35:24.17#ibcon#about to read 6, iclass 37, count 0 2006.201.05:35:24.17#ibcon#read 6, iclass 37, count 0 2006.201.05:35:24.17#ibcon#end of sib2, iclass 37, count 0 2006.201.05:35:24.17#ibcon#*after write, iclass 37, count 0 2006.201.05:35:24.17#ibcon#*before return 0, iclass 37, count 0 2006.201.05:35:24.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:24.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:35:24.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:35:24.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:35:24.17$vck44/vb=7,4 2006.201.05:35:24.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.05:35:24.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.05:35:24.17#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:24.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:24.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:24.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:24.23#ibcon#enter wrdev, iclass 39, count 2 2006.201.05:35:24.23#ibcon#first serial, iclass 39, count 2 2006.201.05:35:24.23#ibcon#enter sib2, iclass 39, count 2 2006.201.05:35:24.23#ibcon#flushed, iclass 39, count 2 2006.201.05:35:24.23#ibcon#about to write, iclass 39, count 2 2006.201.05:35:24.23#ibcon#wrote, iclass 39, count 2 2006.201.05:35:24.23#ibcon#about to read 3, iclass 39, count 2 2006.201.05:35:24.25#ibcon#read 3, iclass 39, count 2 2006.201.05:35:24.25#ibcon#about to read 4, iclass 39, count 2 2006.201.05:35:24.25#ibcon#read 4, iclass 39, count 2 2006.201.05:35:24.25#ibcon#about to read 5, iclass 39, count 2 2006.201.05:35:24.25#ibcon#read 5, iclass 39, count 2 2006.201.05:35:24.25#ibcon#about to read 6, iclass 39, count 2 2006.201.05:35:24.25#ibcon#read 6, iclass 39, count 2 2006.201.05:35:24.25#ibcon#end of sib2, iclass 39, count 2 2006.201.05:35:24.25#ibcon#*mode == 0, iclass 39, count 2 2006.201.05:35:24.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.05:35:24.25#ibcon#[27=AT07-04\r\n] 2006.201.05:35:24.25#ibcon#*before write, iclass 39, count 2 2006.201.05:35:24.25#ibcon#enter sib2, iclass 39, count 2 2006.201.05:35:24.25#ibcon#flushed, iclass 39, count 2 2006.201.05:35:24.25#ibcon#about to write, iclass 39, count 2 2006.201.05:35:24.25#ibcon#wrote, iclass 39, count 2 2006.201.05:35:24.25#ibcon#about to read 3, iclass 39, count 2 2006.201.05:35:24.28#ibcon#read 3, iclass 39, count 2 2006.201.05:35:24.28#ibcon#about to read 4, iclass 39, count 2 2006.201.05:35:24.28#ibcon#read 4, iclass 39, count 2 2006.201.05:35:24.28#ibcon#about to read 5, iclass 39, count 2 2006.201.05:35:24.28#ibcon#read 5, iclass 39, count 2 2006.201.05:35:24.28#ibcon#about to read 6, iclass 39, count 2 2006.201.05:35:24.28#ibcon#read 6, iclass 39, count 2 2006.201.05:35:24.28#ibcon#end of sib2, iclass 39, count 2 2006.201.05:35:24.28#ibcon#*after write, iclass 39, count 2 2006.201.05:35:24.28#ibcon#*before return 0, iclass 39, count 2 2006.201.05:35:24.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:24.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:35:24.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.05:35:24.28#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:24.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:24.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:24.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:24.40#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:35:24.40#ibcon#first serial, iclass 39, count 0 2006.201.05:35:24.40#ibcon#enter sib2, iclass 39, count 0 2006.201.05:35:24.40#ibcon#flushed, iclass 39, count 0 2006.201.05:35:24.40#ibcon#about to write, iclass 39, count 0 2006.201.05:35:24.40#ibcon#wrote, iclass 39, count 0 2006.201.05:35:24.40#ibcon#about to read 3, iclass 39, count 0 2006.201.05:35:24.42#ibcon#read 3, iclass 39, count 0 2006.201.05:35:24.42#ibcon#about to read 4, iclass 39, count 0 2006.201.05:35:24.42#ibcon#read 4, iclass 39, count 0 2006.201.05:35:24.42#ibcon#about to read 5, iclass 39, count 0 2006.201.05:35:24.42#ibcon#read 5, iclass 39, count 0 2006.201.05:35:24.42#ibcon#about to read 6, iclass 39, count 0 2006.201.05:35:24.42#ibcon#read 6, iclass 39, count 0 2006.201.05:35:24.42#ibcon#end of sib2, iclass 39, count 0 2006.201.05:35:24.42#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:35:24.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:35:24.42#ibcon#[27=USB\r\n] 2006.201.05:35:24.42#ibcon#*before write, iclass 39, count 0 2006.201.05:35:24.42#ibcon#enter sib2, iclass 39, count 0 2006.201.05:35:24.42#ibcon#flushed, iclass 39, count 0 2006.201.05:35:24.42#ibcon#about to write, iclass 39, count 0 2006.201.05:35:24.42#ibcon#wrote, iclass 39, count 0 2006.201.05:35:24.42#ibcon#about to read 3, iclass 39, count 0 2006.201.05:35:24.45#ibcon#read 3, iclass 39, count 0 2006.201.05:35:24.45#ibcon#about to read 4, iclass 39, count 0 2006.201.05:35:24.45#ibcon#read 4, iclass 39, count 0 2006.201.05:35:24.45#ibcon#about to read 5, iclass 39, count 0 2006.201.05:35:24.45#ibcon#read 5, iclass 39, count 0 2006.201.05:35:24.45#ibcon#about to read 6, iclass 39, count 0 2006.201.05:35:24.45#ibcon#read 6, iclass 39, count 0 2006.201.05:35:24.45#ibcon#end of sib2, iclass 39, count 0 2006.201.05:35:24.45#ibcon#*after write, iclass 39, count 0 2006.201.05:35:24.45#ibcon#*before return 0, iclass 39, count 0 2006.201.05:35:24.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:24.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:35:24.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:35:24.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:35:24.45$vck44/vblo=8,744.99 2006.201.05:35:24.45#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.05:35:24.45#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.05:35:24.45#ibcon#ireg 17 cls_cnt 0 2006.201.05:35:24.45#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:24.45#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:24.45#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:24.45#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:35:24.45#ibcon#first serial, iclass 2, count 0 2006.201.05:35:24.45#ibcon#enter sib2, iclass 2, count 0 2006.201.05:35:24.45#ibcon#flushed, iclass 2, count 0 2006.201.05:35:24.45#ibcon#about to write, iclass 2, count 0 2006.201.05:35:24.45#ibcon#wrote, iclass 2, count 0 2006.201.05:35:24.45#ibcon#about to read 3, iclass 2, count 0 2006.201.05:35:24.47#ibcon#read 3, iclass 2, count 0 2006.201.05:35:24.47#ibcon#about to read 4, iclass 2, count 0 2006.201.05:35:24.47#ibcon#read 4, iclass 2, count 0 2006.201.05:35:24.47#ibcon#about to read 5, iclass 2, count 0 2006.201.05:35:24.47#ibcon#read 5, iclass 2, count 0 2006.201.05:35:24.47#ibcon#about to read 6, iclass 2, count 0 2006.201.05:35:24.47#ibcon#read 6, iclass 2, count 0 2006.201.05:35:24.47#ibcon#end of sib2, iclass 2, count 0 2006.201.05:35:24.47#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:35:24.47#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:35:24.47#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:35:24.47#ibcon#*before write, iclass 2, count 0 2006.201.05:35:24.47#ibcon#enter sib2, iclass 2, count 0 2006.201.05:35:24.47#ibcon#flushed, iclass 2, count 0 2006.201.05:35:24.47#ibcon#about to write, iclass 2, count 0 2006.201.05:35:24.47#ibcon#wrote, iclass 2, count 0 2006.201.05:35:24.47#ibcon#about to read 3, iclass 2, count 0 2006.201.05:35:24.51#ibcon#read 3, iclass 2, count 0 2006.201.05:35:24.51#ibcon#about to read 4, iclass 2, count 0 2006.201.05:35:24.51#ibcon#read 4, iclass 2, count 0 2006.201.05:35:24.51#ibcon#about to read 5, iclass 2, count 0 2006.201.05:35:24.51#ibcon#read 5, iclass 2, count 0 2006.201.05:35:24.51#ibcon#about to read 6, iclass 2, count 0 2006.201.05:35:24.51#ibcon#read 6, iclass 2, count 0 2006.201.05:35:24.51#ibcon#end of sib2, iclass 2, count 0 2006.201.05:35:24.51#ibcon#*after write, iclass 2, count 0 2006.201.05:35:24.51#ibcon#*before return 0, iclass 2, count 0 2006.201.05:35:24.51#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:24.51#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:35:24.51#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:35:24.51#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:35:24.51$vck44/vb=8,4 2006.201.05:35:24.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.05:35:24.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.05:35:24.51#ibcon#ireg 11 cls_cnt 2 2006.201.05:35:24.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:24.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:24.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:24.57#ibcon#enter wrdev, iclass 5, count 2 2006.201.05:35:24.57#ibcon#first serial, iclass 5, count 2 2006.201.05:35:24.57#ibcon#enter sib2, iclass 5, count 2 2006.201.05:35:24.57#ibcon#flushed, iclass 5, count 2 2006.201.05:35:24.57#ibcon#about to write, iclass 5, count 2 2006.201.05:35:24.57#ibcon#wrote, iclass 5, count 2 2006.201.05:35:24.57#ibcon#about to read 3, iclass 5, count 2 2006.201.05:35:24.59#ibcon#read 3, iclass 5, count 2 2006.201.05:35:24.59#ibcon#about to read 4, iclass 5, count 2 2006.201.05:35:24.59#ibcon#read 4, iclass 5, count 2 2006.201.05:35:24.59#ibcon#about to read 5, iclass 5, count 2 2006.201.05:35:24.59#ibcon#read 5, iclass 5, count 2 2006.201.05:35:24.59#ibcon#about to read 6, iclass 5, count 2 2006.201.05:35:24.59#ibcon#read 6, iclass 5, count 2 2006.201.05:35:24.59#ibcon#end of sib2, iclass 5, count 2 2006.201.05:35:24.59#ibcon#*mode == 0, iclass 5, count 2 2006.201.05:35:24.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.05:35:24.59#ibcon#[27=AT08-04\r\n] 2006.201.05:35:24.59#ibcon#*before write, iclass 5, count 2 2006.201.05:35:24.59#ibcon#enter sib2, iclass 5, count 2 2006.201.05:35:24.59#ibcon#flushed, iclass 5, count 2 2006.201.05:35:24.59#ibcon#about to write, iclass 5, count 2 2006.201.05:35:24.59#ibcon#wrote, iclass 5, count 2 2006.201.05:35:24.59#ibcon#about to read 3, iclass 5, count 2 2006.201.05:35:24.62#ibcon#read 3, iclass 5, count 2 2006.201.05:35:24.62#ibcon#about to read 4, iclass 5, count 2 2006.201.05:35:24.62#ibcon#read 4, iclass 5, count 2 2006.201.05:35:24.62#ibcon#about to read 5, iclass 5, count 2 2006.201.05:35:24.62#ibcon#read 5, iclass 5, count 2 2006.201.05:35:24.62#ibcon#about to read 6, iclass 5, count 2 2006.201.05:35:24.62#ibcon#read 6, iclass 5, count 2 2006.201.05:35:24.62#ibcon#end of sib2, iclass 5, count 2 2006.201.05:35:24.62#ibcon#*after write, iclass 5, count 2 2006.201.05:35:24.62#ibcon#*before return 0, iclass 5, count 2 2006.201.05:35:24.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:24.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:35:24.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.05:35:24.62#ibcon#ireg 7 cls_cnt 0 2006.201.05:35:24.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:24.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:24.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:24.74#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:35:24.74#ibcon#first serial, iclass 5, count 0 2006.201.05:35:24.74#ibcon#enter sib2, iclass 5, count 0 2006.201.05:35:24.74#ibcon#flushed, iclass 5, count 0 2006.201.05:35:24.74#ibcon#about to write, iclass 5, count 0 2006.201.05:35:24.74#ibcon#wrote, iclass 5, count 0 2006.201.05:35:24.74#ibcon#about to read 3, iclass 5, count 0 2006.201.05:35:24.76#ibcon#read 3, iclass 5, count 0 2006.201.05:35:24.76#ibcon#about to read 4, iclass 5, count 0 2006.201.05:35:24.76#ibcon#read 4, iclass 5, count 0 2006.201.05:35:24.76#ibcon#about to read 5, iclass 5, count 0 2006.201.05:35:24.76#ibcon#read 5, iclass 5, count 0 2006.201.05:35:24.76#ibcon#about to read 6, iclass 5, count 0 2006.201.05:35:24.76#ibcon#read 6, iclass 5, count 0 2006.201.05:35:24.76#ibcon#end of sib2, iclass 5, count 0 2006.201.05:35:24.76#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:35:24.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:35:24.76#ibcon#[27=USB\r\n] 2006.201.05:35:24.76#ibcon#*before write, iclass 5, count 0 2006.201.05:35:24.76#ibcon#enter sib2, iclass 5, count 0 2006.201.05:35:24.76#ibcon#flushed, iclass 5, count 0 2006.201.05:35:24.76#ibcon#about to write, iclass 5, count 0 2006.201.05:35:24.76#ibcon#wrote, iclass 5, count 0 2006.201.05:35:24.76#ibcon#about to read 3, iclass 5, count 0 2006.201.05:35:24.79#ibcon#read 3, iclass 5, count 0 2006.201.05:35:24.79#ibcon#about to read 4, iclass 5, count 0 2006.201.05:35:24.79#ibcon#read 4, iclass 5, count 0 2006.201.05:35:24.79#ibcon#about to read 5, iclass 5, count 0 2006.201.05:35:24.79#ibcon#read 5, iclass 5, count 0 2006.201.05:35:24.79#ibcon#about to read 6, iclass 5, count 0 2006.201.05:35:24.79#ibcon#read 6, iclass 5, count 0 2006.201.05:35:24.79#ibcon#end of sib2, iclass 5, count 0 2006.201.05:35:24.79#ibcon#*after write, iclass 5, count 0 2006.201.05:35:24.79#ibcon#*before return 0, iclass 5, count 0 2006.201.05:35:24.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:24.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:35:24.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:35:24.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:35:24.79$vck44/vabw=wide 2006.201.05:35:24.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.05:35:24.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.05:35:24.79#ibcon#ireg 8 cls_cnt 0 2006.201.05:35:24.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:24.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:24.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:24.79#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:35:24.79#ibcon#first serial, iclass 7, count 0 2006.201.05:35:24.79#ibcon#enter sib2, iclass 7, count 0 2006.201.05:35:24.79#ibcon#flushed, iclass 7, count 0 2006.201.05:35:24.79#ibcon#about to write, iclass 7, count 0 2006.201.05:35:24.79#ibcon#wrote, iclass 7, count 0 2006.201.05:35:24.79#ibcon#about to read 3, iclass 7, count 0 2006.201.05:35:24.81#ibcon#read 3, iclass 7, count 0 2006.201.05:35:24.81#ibcon#about to read 4, iclass 7, count 0 2006.201.05:35:24.81#ibcon#read 4, iclass 7, count 0 2006.201.05:35:24.81#ibcon#about to read 5, iclass 7, count 0 2006.201.05:35:24.81#ibcon#read 5, iclass 7, count 0 2006.201.05:35:24.81#ibcon#about to read 6, iclass 7, count 0 2006.201.05:35:24.81#ibcon#read 6, iclass 7, count 0 2006.201.05:35:24.81#ibcon#end of sib2, iclass 7, count 0 2006.201.05:35:24.81#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:35:24.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:35:24.81#ibcon#[25=BW32\r\n] 2006.201.05:35:24.81#ibcon#*before write, iclass 7, count 0 2006.201.05:35:24.81#ibcon#enter sib2, iclass 7, count 0 2006.201.05:35:24.81#ibcon#flushed, iclass 7, count 0 2006.201.05:35:24.81#ibcon#about to write, iclass 7, count 0 2006.201.05:35:24.81#ibcon#wrote, iclass 7, count 0 2006.201.05:35:24.81#ibcon#about to read 3, iclass 7, count 0 2006.201.05:35:24.84#ibcon#read 3, iclass 7, count 0 2006.201.05:35:24.84#ibcon#about to read 4, iclass 7, count 0 2006.201.05:35:24.84#ibcon#read 4, iclass 7, count 0 2006.201.05:35:24.84#ibcon#about to read 5, iclass 7, count 0 2006.201.05:35:24.84#ibcon#read 5, iclass 7, count 0 2006.201.05:35:24.84#ibcon#about to read 6, iclass 7, count 0 2006.201.05:35:24.84#ibcon#read 6, iclass 7, count 0 2006.201.05:35:24.84#ibcon#end of sib2, iclass 7, count 0 2006.201.05:35:24.84#ibcon#*after write, iclass 7, count 0 2006.201.05:35:24.84#ibcon#*before return 0, iclass 7, count 0 2006.201.05:35:24.84#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:24.84#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:35:24.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:35:24.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:35:24.84$vck44/vbbw=wide 2006.201.05:35:24.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.05:35:24.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.05:35:24.84#ibcon#ireg 8 cls_cnt 0 2006.201.05:35:24.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:35:24.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:35:24.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:35:24.91#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:35:24.91#ibcon#first serial, iclass 11, count 0 2006.201.05:35:24.91#ibcon#enter sib2, iclass 11, count 0 2006.201.05:35:24.91#ibcon#flushed, iclass 11, count 0 2006.201.05:35:24.91#ibcon#about to write, iclass 11, count 0 2006.201.05:35:24.91#ibcon#wrote, iclass 11, count 0 2006.201.05:35:24.91#ibcon#about to read 3, iclass 11, count 0 2006.201.05:35:24.93#ibcon#read 3, iclass 11, count 0 2006.201.05:35:24.93#ibcon#about to read 4, iclass 11, count 0 2006.201.05:35:24.93#ibcon#read 4, iclass 11, count 0 2006.201.05:35:24.93#ibcon#about to read 5, iclass 11, count 0 2006.201.05:35:24.93#ibcon#read 5, iclass 11, count 0 2006.201.05:35:24.93#ibcon#about to read 6, iclass 11, count 0 2006.201.05:35:24.93#ibcon#read 6, iclass 11, count 0 2006.201.05:35:24.93#ibcon#end of sib2, iclass 11, count 0 2006.201.05:35:24.93#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:35:24.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:35:24.93#ibcon#[27=BW32\r\n] 2006.201.05:35:24.93#ibcon#*before write, iclass 11, count 0 2006.201.05:35:24.93#ibcon#enter sib2, iclass 11, count 0 2006.201.05:35:24.93#ibcon#flushed, iclass 11, count 0 2006.201.05:35:24.93#ibcon#about to write, iclass 11, count 0 2006.201.05:35:24.93#ibcon#wrote, iclass 11, count 0 2006.201.05:35:24.93#ibcon#about to read 3, iclass 11, count 0 2006.201.05:35:24.96#ibcon#read 3, iclass 11, count 0 2006.201.05:35:24.96#ibcon#about to read 4, iclass 11, count 0 2006.201.05:35:24.96#ibcon#read 4, iclass 11, count 0 2006.201.05:35:24.96#ibcon#about to read 5, iclass 11, count 0 2006.201.05:35:24.96#ibcon#read 5, iclass 11, count 0 2006.201.05:35:24.96#ibcon#about to read 6, iclass 11, count 0 2006.201.05:35:24.96#ibcon#read 6, iclass 11, count 0 2006.201.05:35:24.96#ibcon#end of sib2, iclass 11, count 0 2006.201.05:35:24.96#ibcon#*after write, iclass 11, count 0 2006.201.05:35:24.96#ibcon#*before return 0, iclass 11, count 0 2006.201.05:35:24.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:35:24.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:35:24.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:35:24.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:35:24.96$setupk4/ifdk4 2006.201.05:35:24.96$ifdk4/lo= 2006.201.05:35:24.96$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:35:24.96$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:35:24.96$ifdk4/patch= 2006.201.05:35:24.96$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:35:24.96$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:35:24.96$setupk4/!*+20s 2006.201.05:35:28.44#abcon#<5=/04 2.6 4.7 23.13 901003.7\r\n> 2006.201.05:35:28.46#abcon#{5=INTERFACE CLEAR} 2006.201.05:35:28.52#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:35:35.14#trakl#Source acquired 2006.201.05:35:35.14#flagr#flagr/antenna,acquired 2006.201.05:35:38.61#abcon#<5=/04 2.6 4.7 23.13 901003.7\r\n> 2006.201.05:35:38.63#abcon#{5=INTERFACE CLEAR} 2006.201.05:35:38.69#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:35:39.27$setupk4/"tpicd 2006.201.05:35:39.27$setupk4/echo=off 2006.201.05:35:39.27$setupk4/xlog=off 2006.201.05:35:39.27:!2006.201.05:39:06 2006.201.05:39:06.00:preob 2006.201.05:39:06.14/onsource/TRACKING 2006.201.05:39:06.14:!2006.201.05:39:16 2006.201.05:39:16.00:"tape 2006.201.05:39:16.00:"st=record 2006.201.05:39:16.00:data_valid=on 2006.201.05:39:16.00:midob 2006.201.05:39:17.14/onsource/TRACKING 2006.201.05:39:17.14/wx/23.10,1003.7,91 2006.201.05:39:17.35/cable/+6.4672E-03 2006.201.05:39:18.44/va/01,08,usb,yes,30,32 2006.201.05:39:18.44/va/02,07,usb,yes,33,33 2006.201.05:39:18.44/va/03,08,usb,yes,29,31 2006.201.05:39:18.44/va/04,07,usb,yes,34,35 2006.201.05:39:18.44/va/05,04,usb,yes,30,30 2006.201.05:39:18.44/va/06,05,usb,yes,30,30 2006.201.05:39:18.44/va/07,05,usb,yes,29,30 2006.201.05:39:18.44/va/08,04,usb,yes,29,34 2006.201.05:39:18.67/valo/01,524.99,yes,locked 2006.201.05:39:18.67/valo/02,534.99,yes,locked 2006.201.05:39:18.67/valo/03,564.99,yes,locked 2006.201.05:39:18.67/valo/04,624.99,yes,locked 2006.201.05:39:18.67/valo/05,734.99,yes,locked 2006.201.05:39:18.67/valo/06,814.99,yes,locked 2006.201.05:39:18.67/valo/07,864.99,yes,locked 2006.201.05:39:18.67/valo/08,884.99,yes,locked 2006.201.05:39:19.76/vb/01,04,usb,yes,30,28 2006.201.05:39:19.76/vb/02,05,usb,yes,28,28 2006.201.05:39:19.76/vb/03,04,usb,yes,29,32 2006.201.05:39:19.76/vb/04,05,usb,yes,29,28 2006.201.05:39:19.76/vb/05,04,usb,yes,26,28 2006.201.05:39:19.76/vb/06,04,usb,yes,30,26 2006.201.05:39:19.76/vb/07,04,usb,yes,30,30 2006.201.05:39:19.76/vb/08,04,usb,yes,28,31 2006.201.05:39:19.99/vblo/01,629.99,yes,locked 2006.201.05:39:19.99/vblo/02,634.99,yes,locked 2006.201.05:39:19.99/vblo/03,649.99,yes,locked 2006.201.05:39:19.99/vblo/04,679.99,yes,locked 2006.201.05:39:19.99/vblo/05,709.99,yes,locked 2006.201.05:39:19.99/vblo/06,719.99,yes,locked 2006.201.05:39:19.99/vblo/07,734.99,yes,locked 2006.201.05:39:19.99/vblo/08,744.99,yes,locked 2006.201.05:39:20.14/vabw/8 2006.201.05:39:20.29/vbbw/8 2006.201.05:39:20.38/xfe/off,on,15.2 2006.201.05:39:20.75/ifatt/23,28,28,28 2006.201.05:39:21.05/fmout-gps/S +4.52E-07 2006.201.05:39:21.09:!2006.201.05:40:26 2006.201.05:40:26.00:data_valid=off 2006.201.05:40:26.00:"et 2006.201.05:40:26.00:!+3s 2006.201.05:40:29.02:"tape 2006.201.05:40:29.02:postob 2006.201.05:40:29.12/cable/+6.4660E-03 2006.201.05:40:29.12/wx/23.09,1003.7,90 2006.201.05:40:29.18/fmout-gps/S +4.54E-07 2006.201.05:40:29.18:scan_name=201-0542,jd0607,50 2006.201.05:40:29.18:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.201.05:40:31.14#flagr#flagr/antenna,new-source 2006.201.05:40:31.14:checkk5 2006.201.05:40:31.55/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:40:31.96/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:40:32.37/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:40:32.76/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:40:33.14/chk_obsdata//k5ts1/T2010539??a.dat file size is correct (nominal:280MB, actual:280MB). 2006.201.05:40:33.55/chk_obsdata//k5ts2/T2010539??b.dat file size is correct (nominal:280MB, actual:280MB). 2006.201.05:40:33.95/chk_obsdata//k5ts3/T2010539??c.dat file size is correct (nominal:280MB, actual:280MB). 2006.201.05:40:34.37/chk_obsdata//k5ts4/T2010539??d.dat file size is correct (nominal:280MB, actual:280MB). 2006.201.05:40:35.10/k5log//k5ts1_log_newline 2006.201.05:40:35.82/k5log//k5ts2_log_newline 2006.201.05:40:36.56/k5log//k5ts3_log_newline 2006.201.05:40:37.30/k5log//k5ts4_log_newline 2006.201.05:40:37.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:40:37.32:setupk4=1 2006.201.05:40:37.32$setupk4/echo=on 2006.201.05:40:37.32$setupk4/pcalon 2006.201.05:40:37.32$pcalon/"no phase cal control is implemented here 2006.201.05:40:37.32$setupk4/"tpicd=stop 2006.201.05:40:37.32$setupk4/"rec=synch_on 2006.201.05:40:37.32$setupk4/"rec_mode=128 2006.201.05:40:37.32$setupk4/!* 2006.201.05:40:37.32$setupk4/recpk4 2006.201.05:40:37.33$recpk4/recpatch= 2006.201.05:40:37.33$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:40:37.33$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:40:37.33$setupk4/vck44 2006.201.05:40:37.33$vck44/valo=1,524.99 2006.201.05:40:37.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.05:40:37.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.05:40:37.33#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:37.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:37.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:37.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:37.33#ibcon#enter wrdev, iclass 32, count 0 2006.201.05:40:37.33#ibcon#first serial, iclass 32, count 0 2006.201.05:40:37.33#ibcon#enter sib2, iclass 32, count 0 2006.201.05:40:37.33#ibcon#flushed, iclass 32, count 0 2006.201.05:40:37.33#ibcon#about to write, iclass 32, count 0 2006.201.05:40:37.33#ibcon#wrote, iclass 32, count 0 2006.201.05:40:37.33#ibcon#about to read 3, iclass 32, count 0 2006.201.05:40:37.35#ibcon#read 3, iclass 32, count 0 2006.201.05:40:37.35#ibcon#about to read 4, iclass 32, count 0 2006.201.05:40:37.35#ibcon#read 4, iclass 32, count 0 2006.201.05:40:37.35#ibcon#about to read 5, iclass 32, count 0 2006.201.05:40:37.35#ibcon#read 5, iclass 32, count 0 2006.201.05:40:37.35#ibcon#about to read 6, iclass 32, count 0 2006.201.05:40:37.35#ibcon#read 6, iclass 32, count 0 2006.201.05:40:37.35#ibcon#end of sib2, iclass 32, count 0 2006.201.05:40:37.35#ibcon#*mode == 0, iclass 32, count 0 2006.201.05:40:37.35#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.05:40:37.35#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:40:37.35#ibcon#*before write, iclass 32, count 0 2006.201.05:40:37.35#ibcon#enter sib2, iclass 32, count 0 2006.201.05:40:37.35#ibcon#flushed, iclass 32, count 0 2006.201.05:40:37.35#ibcon#about to write, iclass 32, count 0 2006.201.05:40:37.35#ibcon#wrote, iclass 32, count 0 2006.201.05:40:37.35#ibcon#about to read 3, iclass 32, count 0 2006.201.05:40:37.40#ibcon#read 3, iclass 32, count 0 2006.201.05:40:37.40#ibcon#about to read 4, iclass 32, count 0 2006.201.05:40:37.40#ibcon#read 4, iclass 32, count 0 2006.201.05:40:37.40#ibcon#about to read 5, iclass 32, count 0 2006.201.05:40:37.40#ibcon#read 5, iclass 32, count 0 2006.201.05:40:37.40#ibcon#about to read 6, iclass 32, count 0 2006.201.05:40:37.40#ibcon#read 6, iclass 32, count 0 2006.201.05:40:37.40#ibcon#end of sib2, iclass 32, count 0 2006.201.05:40:37.40#ibcon#*after write, iclass 32, count 0 2006.201.05:40:37.40#ibcon#*before return 0, iclass 32, count 0 2006.201.05:40:37.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:37.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:37.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.05:40:37.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.05:40:37.40$vck44/va=1,8 2006.201.05:40:37.40#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.05:40:37.40#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.05:40:37.40#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:37.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:37.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:37.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:37.40#ibcon#enter wrdev, iclass 34, count 2 2006.201.05:40:37.40#ibcon#first serial, iclass 34, count 2 2006.201.05:40:37.40#ibcon#enter sib2, iclass 34, count 2 2006.201.05:40:37.40#ibcon#flushed, iclass 34, count 2 2006.201.05:40:37.40#ibcon#about to write, iclass 34, count 2 2006.201.05:40:37.40#ibcon#wrote, iclass 34, count 2 2006.201.05:40:37.40#ibcon#about to read 3, iclass 34, count 2 2006.201.05:40:37.42#ibcon#read 3, iclass 34, count 2 2006.201.05:40:37.42#ibcon#about to read 4, iclass 34, count 2 2006.201.05:40:37.42#ibcon#read 4, iclass 34, count 2 2006.201.05:40:37.42#ibcon#about to read 5, iclass 34, count 2 2006.201.05:40:37.42#ibcon#read 5, iclass 34, count 2 2006.201.05:40:37.42#ibcon#about to read 6, iclass 34, count 2 2006.201.05:40:37.42#ibcon#read 6, iclass 34, count 2 2006.201.05:40:37.42#ibcon#end of sib2, iclass 34, count 2 2006.201.05:40:37.42#ibcon#*mode == 0, iclass 34, count 2 2006.201.05:40:37.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.05:40:37.42#ibcon#[25=AT01-08\r\n] 2006.201.05:40:37.42#ibcon#*before write, iclass 34, count 2 2006.201.05:40:37.42#ibcon#enter sib2, iclass 34, count 2 2006.201.05:40:37.42#ibcon#flushed, iclass 34, count 2 2006.201.05:40:37.42#ibcon#about to write, iclass 34, count 2 2006.201.05:40:37.42#ibcon#wrote, iclass 34, count 2 2006.201.05:40:37.42#ibcon#about to read 3, iclass 34, count 2 2006.201.05:40:37.45#ibcon#read 3, iclass 34, count 2 2006.201.05:40:37.45#ibcon#about to read 4, iclass 34, count 2 2006.201.05:40:37.45#ibcon#read 4, iclass 34, count 2 2006.201.05:40:37.45#ibcon#about to read 5, iclass 34, count 2 2006.201.05:40:37.45#ibcon#read 5, iclass 34, count 2 2006.201.05:40:37.45#ibcon#about to read 6, iclass 34, count 2 2006.201.05:40:37.45#ibcon#read 6, iclass 34, count 2 2006.201.05:40:37.45#ibcon#end of sib2, iclass 34, count 2 2006.201.05:40:37.45#ibcon#*after write, iclass 34, count 2 2006.201.05:40:37.45#ibcon#*before return 0, iclass 34, count 2 2006.201.05:40:37.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:37.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:37.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.05:40:37.45#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:37.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:37.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:37.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:37.57#ibcon#enter wrdev, iclass 34, count 0 2006.201.05:40:37.57#ibcon#first serial, iclass 34, count 0 2006.201.05:40:37.57#ibcon#enter sib2, iclass 34, count 0 2006.201.05:40:37.57#ibcon#flushed, iclass 34, count 0 2006.201.05:40:37.57#ibcon#about to write, iclass 34, count 0 2006.201.05:40:37.57#ibcon#wrote, iclass 34, count 0 2006.201.05:40:37.57#ibcon#about to read 3, iclass 34, count 0 2006.201.05:40:37.59#ibcon#read 3, iclass 34, count 0 2006.201.05:40:37.59#ibcon#about to read 4, iclass 34, count 0 2006.201.05:40:37.59#ibcon#read 4, iclass 34, count 0 2006.201.05:40:37.59#ibcon#about to read 5, iclass 34, count 0 2006.201.05:40:37.59#ibcon#read 5, iclass 34, count 0 2006.201.05:40:37.59#ibcon#about to read 6, iclass 34, count 0 2006.201.05:40:37.59#ibcon#read 6, iclass 34, count 0 2006.201.05:40:37.59#ibcon#end of sib2, iclass 34, count 0 2006.201.05:40:37.59#ibcon#*mode == 0, iclass 34, count 0 2006.201.05:40:37.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.05:40:37.59#ibcon#[25=USB\r\n] 2006.201.05:40:37.59#ibcon#*before write, iclass 34, count 0 2006.201.05:40:37.59#ibcon#enter sib2, iclass 34, count 0 2006.201.05:40:37.59#ibcon#flushed, iclass 34, count 0 2006.201.05:40:37.59#ibcon#about to write, iclass 34, count 0 2006.201.05:40:37.59#ibcon#wrote, iclass 34, count 0 2006.201.05:40:37.59#ibcon#about to read 3, iclass 34, count 0 2006.201.05:40:37.62#ibcon#read 3, iclass 34, count 0 2006.201.05:40:37.62#ibcon#about to read 4, iclass 34, count 0 2006.201.05:40:37.62#ibcon#read 4, iclass 34, count 0 2006.201.05:40:37.62#ibcon#about to read 5, iclass 34, count 0 2006.201.05:40:37.62#ibcon#read 5, iclass 34, count 0 2006.201.05:40:37.62#ibcon#about to read 6, iclass 34, count 0 2006.201.05:40:37.62#ibcon#read 6, iclass 34, count 0 2006.201.05:40:37.62#ibcon#end of sib2, iclass 34, count 0 2006.201.05:40:37.62#ibcon#*after write, iclass 34, count 0 2006.201.05:40:37.62#ibcon#*before return 0, iclass 34, count 0 2006.201.05:40:37.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:37.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:37.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.05:40:37.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.05:40:37.62$vck44/valo=2,534.99 2006.201.05:40:37.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.05:40:37.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.05:40:37.62#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:37.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:37.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:37.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:37.62#ibcon#enter wrdev, iclass 36, count 0 2006.201.05:40:37.62#ibcon#first serial, iclass 36, count 0 2006.201.05:40:37.62#ibcon#enter sib2, iclass 36, count 0 2006.201.05:40:37.62#ibcon#flushed, iclass 36, count 0 2006.201.05:40:37.62#ibcon#about to write, iclass 36, count 0 2006.201.05:40:37.62#ibcon#wrote, iclass 36, count 0 2006.201.05:40:37.62#ibcon#about to read 3, iclass 36, count 0 2006.201.05:40:37.64#ibcon#read 3, iclass 36, count 0 2006.201.05:40:37.64#ibcon#about to read 4, iclass 36, count 0 2006.201.05:40:37.64#ibcon#read 4, iclass 36, count 0 2006.201.05:40:37.64#ibcon#about to read 5, iclass 36, count 0 2006.201.05:40:37.64#ibcon#read 5, iclass 36, count 0 2006.201.05:40:37.64#ibcon#about to read 6, iclass 36, count 0 2006.201.05:40:37.64#ibcon#read 6, iclass 36, count 0 2006.201.05:40:37.64#ibcon#end of sib2, iclass 36, count 0 2006.201.05:40:37.64#ibcon#*mode == 0, iclass 36, count 0 2006.201.05:40:37.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.05:40:37.64#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:40:37.64#ibcon#*before write, iclass 36, count 0 2006.201.05:40:37.64#ibcon#enter sib2, iclass 36, count 0 2006.201.05:40:37.64#ibcon#flushed, iclass 36, count 0 2006.201.05:40:37.64#ibcon#about to write, iclass 36, count 0 2006.201.05:40:37.64#ibcon#wrote, iclass 36, count 0 2006.201.05:40:37.64#ibcon#about to read 3, iclass 36, count 0 2006.201.05:40:37.68#ibcon#read 3, iclass 36, count 0 2006.201.05:40:37.68#ibcon#about to read 4, iclass 36, count 0 2006.201.05:40:37.68#ibcon#read 4, iclass 36, count 0 2006.201.05:40:37.68#ibcon#about to read 5, iclass 36, count 0 2006.201.05:40:37.68#ibcon#read 5, iclass 36, count 0 2006.201.05:40:37.68#ibcon#about to read 6, iclass 36, count 0 2006.201.05:40:37.68#ibcon#read 6, iclass 36, count 0 2006.201.05:40:37.68#ibcon#end of sib2, iclass 36, count 0 2006.201.05:40:37.68#ibcon#*after write, iclass 36, count 0 2006.201.05:40:37.68#ibcon#*before return 0, iclass 36, count 0 2006.201.05:40:37.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:37.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:37.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.05:40:37.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.05:40:37.68$vck44/va=2,7 2006.201.05:40:37.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.05:40:37.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.05:40:37.68#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:37.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:37.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:37.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:37.74#ibcon#enter wrdev, iclass 38, count 2 2006.201.05:40:37.74#ibcon#first serial, iclass 38, count 2 2006.201.05:40:37.74#ibcon#enter sib2, iclass 38, count 2 2006.201.05:40:37.74#ibcon#flushed, iclass 38, count 2 2006.201.05:40:37.74#ibcon#about to write, iclass 38, count 2 2006.201.05:40:37.74#ibcon#wrote, iclass 38, count 2 2006.201.05:40:37.74#ibcon#about to read 3, iclass 38, count 2 2006.201.05:40:37.76#ibcon#read 3, iclass 38, count 2 2006.201.05:40:37.76#ibcon#about to read 4, iclass 38, count 2 2006.201.05:40:37.76#ibcon#read 4, iclass 38, count 2 2006.201.05:40:37.76#ibcon#about to read 5, iclass 38, count 2 2006.201.05:40:37.76#ibcon#read 5, iclass 38, count 2 2006.201.05:40:37.76#ibcon#about to read 6, iclass 38, count 2 2006.201.05:40:37.76#ibcon#read 6, iclass 38, count 2 2006.201.05:40:37.76#ibcon#end of sib2, iclass 38, count 2 2006.201.05:40:37.76#ibcon#*mode == 0, iclass 38, count 2 2006.201.05:40:37.76#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.05:40:37.76#ibcon#[25=AT02-07\r\n] 2006.201.05:40:37.76#ibcon#*before write, iclass 38, count 2 2006.201.05:40:37.76#ibcon#enter sib2, iclass 38, count 2 2006.201.05:40:37.76#ibcon#flushed, iclass 38, count 2 2006.201.05:40:37.76#ibcon#about to write, iclass 38, count 2 2006.201.05:40:37.76#ibcon#wrote, iclass 38, count 2 2006.201.05:40:37.76#ibcon#about to read 3, iclass 38, count 2 2006.201.05:40:37.79#ibcon#read 3, iclass 38, count 2 2006.201.05:40:37.79#ibcon#about to read 4, iclass 38, count 2 2006.201.05:40:37.79#ibcon#read 4, iclass 38, count 2 2006.201.05:40:37.79#ibcon#about to read 5, iclass 38, count 2 2006.201.05:40:37.79#ibcon#read 5, iclass 38, count 2 2006.201.05:40:37.79#ibcon#about to read 6, iclass 38, count 2 2006.201.05:40:37.79#ibcon#read 6, iclass 38, count 2 2006.201.05:40:37.79#ibcon#end of sib2, iclass 38, count 2 2006.201.05:40:37.79#ibcon#*after write, iclass 38, count 2 2006.201.05:40:37.79#ibcon#*before return 0, iclass 38, count 2 2006.201.05:40:37.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:37.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:37.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.05:40:37.79#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:37.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:37.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:37.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:37.91#ibcon#enter wrdev, iclass 38, count 0 2006.201.05:40:37.91#ibcon#first serial, iclass 38, count 0 2006.201.05:40:37.91#ibcon#enter sib2, iclass 38, count 0 2006.201.05:40:37.91#ibcon#flushed, iclass 38, count 0 2006.201.05:40:37.91#ibcon#about to write, iclass 38, count 0 2006.201.05:40:37.91#ibcon#wrote, iclass 38, count 0 2006.201.05:40:37.91#ibcon#about to read 3, iclass 38, count 0 2006.201.05:40:37.93#ibcon#read 3, iclass 38, count 0 2006.201.05:40:37.93#ibcon#about to read 4, iclass 38, count 0 2006.201.05:40:37.93#ibcon#read 4, iclass 38, count 0 2006.201.05:40:37.93#ibcon#about to read 5, iclass 38, count 0 2006.201.05:40:37.93#ibcon#read 5, iclass 38, count 0 2006.201.05:40:37.93#ibcon#about to read 6, iclass 38, count 0 2006.201.05:40:37.93#ibcon#read 6, iclass 38, count 0 2006.201.05:40:37.93#ibcon#end of sib2, iclass 38, count 0 2006.201.05:40:37.93#ibcon#*mode == 0, iclass 38, count 0 2006.201.05:40:37.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.05:40:37.93#ibcon#[25=USB\r\n] 2006.201.05:40:37.93#ibcon#*before write, iclass 38, count 0 2006.201.05:40:37.93#ibcon#enter sib2, iclass 38, count 0 2006.201.05:40:37.93#ibcon#flushed, iclass 38, count 0 2006.201.05:40:37.93#ibcon#about to write, iclass 38, count 0 2006.201.05:40:37.93#ibcon#wrote, iclass 38, count 0 2006.201.05:40:37.93#ibcon#about to read 3, iclass 38, count 0 2006.201.05:40:37.96#ibcon#read 3, iclass 38, count 0 2006.201.05:40:37.96#ibcon#about to read 4, iclass 38, count 0 2006.201.05:40:37.96#ibcon#read 4, iclass 38, count 0 2006.201.05:40:37.96#ibcon#about to read 5, iclass 38, count 0 2006.201.05:40:37.96#ibcon#read 5, iclass 38, count 0 2006.201.05:40:37.96#ibcon#about to read 6, iclass 38, count 0 2006.201.05:40:37.96#ibcon#read 6, iclass 38, count 0 2006.201.05:40:37.96#ibcon#end of sib2, iclass 38, count 0 2006.201.05:40:37.96#ibcon#*after write, iclass 38, count 0 2006.201.05:40:37.96#ibcon#*before return 0, iclass 38, count 0 2006.201.05:40:37.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:37.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:37.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.05:40:37.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.05:40:37.96$vck44/valo=3,564.99 2006.201.05:40:37.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.05:40:37.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.05:40:37.96#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:37.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:37.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:37.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:37.96#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:40:37.96#ibcon#first serial, iclass 40, count 0 2006.201.05:40:37.96#ibcon#enter sib2, iclass 40, count 0 2006.201.05:40:37.96#ibcon#flushed, iclass 40, count 0 2006.201.05:40:37.96#ibcon#about to write, iclass 40, count 0 2006.201.05:40:37.96#ibcon#wrote, iclass 40, count 0 2006.201.05:40:37.96#ibcon#about to read 3, iclass 40, count 0 2006.201.05:40:37.98#ibcon#read 3, iclass 40, count 0 2006.201.05:40:37.98#ibcon#about to read 4, iclass 40, count 0 2006.201.05:40:37.98#ibcon#read 4, iclass 40, count 0 2006.201.05:40:37.98#ibcon#about to read 5, iclass 40, count 0 2006.201.05:40:37.98#ibcon#read 5, iclass 40, count 0 2006.201.05:40:37.98#ibcon#about to read 6, iclass 40, count 0 2006.201.05:40:37.98#ibcon#read 6, iclass 40, count 0 2006.201.05:40:37.98#ibcon#end of sib2, iclass 40, count 0 2006.201.05:40:37.98#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:40:37.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:40:37.98#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:40:37.98#ibcon#*before write, iclass 40, count 0 2006.201.05:40:37.98#ibcon#enter sib2, iclass 40, count 0 2006.201.05:40:37.98#ibcon#flushed, iclass 40, count 0 2006.201.05:40:37.98#ibcon#about to write, iclass 40, count 0 2006.201.05:40:37.98#ibcon#wrote, iclass 40, count 0 2006.201.05:40:37.98#ibcon#about to read 3, iclass 40, count 0 2006.201.05:40:38.02#ibcon#read 3, iclass 40, count 0 2006.201.05:40:38.02#ibcon#about to read 4, iclass 40, count 0 2006.201.05:40:38.02#ibcon#read 4, iclass 40, count 0 2006.201.05:40:38.02#ibcon#about to read 5, iclass 40, count 0 2006.201.05:40:38.02#ibcon#read 5, iclass 40, count 0 2006.201.05:40:38.02#ibcon#about to read 6, iclass 40, count 0 2006.201.05:40:38.02#ibcon#read 6, iclass 40, count 0 2006.201.05:40:38.02#ibcon#end of sib2, iclass 40, count 0 2006.201.05:40:38.02#ibcon#*after write, iclass 40, count 0 2006.201.05:40:38.02#ibcon#*before return 0, iclass 40, count 0 2006.201.05:40:38.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:38.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:38.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:40:38.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:40:38.02$vck44/va=3,8 2006.201.05:40:38.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.05:40:38.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.05:40:38.02#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:38.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:38.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:38.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:38.08#ibcon#enter wrdev, iclass 4, count 2 2006.201.05:40:38.08#ibcon#first serial, iclass 4, count 2 2006.201.05:40:38.08#ibcon#enter sib2, iclass 4, count 2 2006.201.05:40:38.08#ibcon#flushed, iclass 4, count 2 2006.201.05:40:38.08#ibcon#about to write, iclass 4, count 2 2006.201.05:40:38.08#ibcon#wrote, iclass 4, count 2 2006.201.05:40:38.08#ibcon#about to read 3, iclass 4, count 2 2006.201.05:40:38.10#ibcon#read 3, iclass 4, count 2 2006.201.05:40:38.10#ibcon#about to read 4, iclass 4, count 2 2006.201.05:40:38.10#ibcon#read 4, iclass 4, count 2 2006.201.05:40:38.10#ibcon#about to read 5, iclass 4, count 2 2006.201.05:40:38.10#ibcon#read 5, iclass 4, count 2 2006.201.05:40:38.10#ibcon#about to read 6, iclass 4, count 2 2006.201.05:40:38.10#ibcon#read 6, iclass 4, count 2 2006.201.05:40:38.10#ibcon#end of sib2, iclass 4, count 2 2006.201.05:40:38.10#ibcon#*mode == 0, iclass 4, count 2 2006.201.05:40:38.10#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.05:40:38.10#ibcon#[25=AT03-08\r\n] 2006.201.05:40:38.10#ibcon#*before write, iclass 4, count 2 2006.201.05:40:38.10#ibcon#enter sib2, iclass 4, count 2 2006.201.05:40:38.10#ibcon#flushed, iclass 4, count 2 2006.201.05:40:38.10#ibcon#about to write, iclass 4, count 2 2006.201.05:40:38.10#ibcon#wrote, iclass 4, count 2 2006.201.05:40:38.10#ibcon#about to read 3, iclass 4, count 2 2006.201.05:40:38.13#ibcon#read 3, iclass 4, count 2 2006.201.05:40:38.13#ibcon#about to read 4, iclass 4, count 2 2006.201.05:40:38.13#ibcon#read 4, iclass 4, count 2 2006.201.05:40:38.13#ibcon#about to read 5, iclass 4, count 2 2006.201.05:40:38.13#ibcon#read 5, iclass 4, count 2 2006.201.05:40:38.13#ibcon#about to read 6, iclass 4, count 2 2006.201.05:40:38.13#ibcon#read 6, iclass 4, count 2 2006.201.05:40:38.13#ibcon#end of sib2, iclass 4, count 2 2006.201.05:40:38.13#ibcon#*after write, iclass 4, count 2 2006.201.05:40:38.13#ibcon#*before return 0, iclass 4, count 2 2006.201.05:40:38.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:38.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:38.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.05:40:38.13#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:38.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:38.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:38.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:38.25#ibcon#enter wrdev, iclass 4, count 0 2006.201.05:40:38.25#ibcon#first serial, iclass 4, count 0 2006.201.05:40:38.25#ibcon#enter sib2, iclass 4, count 0 2006.201.05:40:38.25#ibcon#flushed, iclass 4, count 0 2006.201.05:40:38.25#ibcon#about to write, iclass 4, count 0 2006.201.05:40:38.25#ibcon#wrote, iclass 4, count 0 2006.201.05:40:38.25#ibcon#about to read 3, iclass 4, count 0 2006.201.05:40:38.27#ibcon#read 3, iclass 4, count 0 2006.201.05:40:38.27#ibcon#about to read 4, iclass 4, count 0 2006.201.05:40:38.27#ibcon#read 4, iclass 4, count 0 2006.201.05:40:38.27#ibcon#about to read 5, iclass 4, count 0 2006.201.05:40:38.27#ibcon#read 5, iclass 4, count 0 2006.201.05:40:38.27#ibcon#about to read 6, iclass 4, count 0 2006.201.05:40:38.27#ibcon#read 6, iclass 4, count 0 2006.201.05:40:38.27#ibcon#end of sib2, iclass 4, count 0 2006.201.05:40:38.27#ibcon#*mode == 0, iclass 4, count 0 2006.201.05:40:38.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.05:40:38.27#ibcon#[25=USB\r\n] 2006.201.05:40:38.27#ibcon#*before write, iclass 4, count 0 2006.201.05:40:38.27#ibcon#enter sib2, iclass 4, count 0 2006.201.05:40:38.27#ibcon#flushed, iclass 4, count 0 2006.201.05:40:38.27#ibcon#about to write, iclass 4, count 0 2006.201.05:40:38.27#ibcon#wrote, iclass 4, count 0 2006.201.05:40:38.27#ibcon#about to read 3, iclass 4, count 0 2006.201.05:40:38.30#ibcon#read 3, iclass 4, count 0 2006.201.05:40:38.30#ibcon#about to read 4, iclass 4, count 0 2006.201.05:40:38.30#ibcon#read 4, iclass 4, count 0 2006.201.05:40:38.30#ibcon#about to read 5, iclass 4, count 0 2006.201.05:40:38.30#ibcon#read 5, iclass 4, count 0 2006.201.05:40:38.30#ibcon#about to read 6, iclass 4, count 0 2006.201.05:40:38.30#ibcon#read 6, iclass 4, count 0 2006.201.05:40:38.30#ibcon#end of sib2, iclass 4, count 0 2006.201.05:40:38.30#ibcon#*after write, iclass 4, count 0 2006.201.05:40:38.30#ibcon#*before return 0, iclass 4, count 0 2006.201.05:40:38.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:38.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:38.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.05:40:38.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.05:40:38.30$vck44/valo=4,624.99 2006.201.05:40:38.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.05:40:38.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.05:40:38.30#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:38.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:38.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:38.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:38.30#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:40:38.30#ibcon#first serial, iclass 6, count 0 2006.201.05:40:38.30#ibcon#enter sib2, iclass 6, count 0 2006.201.05:40:38.30#ibcon#flushed, iclass 6, count 0 2006.201.05:40:38.30#ibcon#about to write, iclass 6, count 0 2006.201.05:40:38.30#ibcon#wrote, iclass 6, count 0 2006.201.05:40:38.30#ibcon#about to read 3, iclass 6, count 0 2006.201.05:40:38.32#ibcon#read 3, iclass 6, count 0 2006.201.05:40:38.32#ibcon#about to read 4, iclass 6, count 0 2006.201.05:40:38.32#ibcon#read 4, iclass 6, count 0 2006.201.05:40:38.32#ibcon#about to read 5, iclass 6, count 0 2006.201.05:40:38.32#ibcon#read 5, iclass 6, count 0 2006.201.05:40:38.32#ibcon#about to read 6, iclass 6, count 0 2006.201.05:40:38.32#ibcon#read 6, iclass 6, count 0 2006.201.05:40:38.32#ibcon#end of sib2, iclass 6, count 0 2006.201.05:40:38.32#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:40:38.32#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:40:38.32#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:40:38.32#ibcon#*before write, iclass 6, count 0 2006.201.05:40:38.32#ibcon#enter sib2, iclass 6, count 0 2006.201.05:40:38.32#ibcon#flushed, iclass 6, count 0 2006.201.05:40:38.32#ibcon#about to write, iclass 6, count 0 2006.201.05:40:38.32#ibcon#wrote, iclass 6, count 0 2006.201.05:40:38.32#ibcon#about to read 3, iclass 6, count 0 2006.201.05:40:38.36#ibcon#read 3, iclass 6, count 0 2006.201.05:40:38.36#ibcon#about to read 4, iclass 6, count 0 2006.201.05:40:38.36#ibcon#read 4, iclass 6, count 0 2006.201.05:40:38.36#ibcon#about to read 5, iclass 6, count 0 2006.201.05:40:38.36#ibcon#read 5, iclass 6, count 0 2006.201.05:40:38.36#ibcon#about to read 6, iclass 6, count 0 2006.201.05:40:38.36#ibcon#read 6, iclass 6, count 0 2006.201.05:40:38.36#ibcon#end of sib2, iclass 6, count 0 2006.201.05:40:38.36#ibcon#*after write, iclass 6, count 0 2006.201.05:40:38.36#ibcon#*before return 0, iclass 6, count 0 2006.201.05:40:38.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:38.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:38.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:40:38.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:40:38.36$vck44/va=4,7 2006.201.05:40:38.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.05:40:38.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.05:40:38.36#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:38.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:38.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:38.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:38.42#ibcon#enter wrdev, iclass 10, count 2 2006.201.05:40:38.42#ibcon#first serial, iclass 10, count 2 2006.201.05:40:38.42#ibcon#enter sib2, iclass 10, count 2 2006.201.05:40:38.42#ibcon#flushed, iclass 10, count 2 2006.201.05:40:38.42#ibcon#about to write, iclass 10, count 2 2006.201.05:40:38.42#ibcon#wrote, iclass 10, count 2 2006.201.05:40:38.42#ibcon#about to read 3, iclass 10, count 2 2006.201.05:40:38.44#ibcon#read 3, iclass 10, count 2 2006.201.05:40:38.44#ibcon#about to read 4, iclass 10, count 2 2006.201.05:40:38.44#ibcon#read 4, iclass 10, count 2 2006.201.05:40:38.44#ibcon#about to read 5, iclass 10, count 2 2006.201.05:40:38.44#ibcon#read 5, iclass 10, count 2 2006.201.05:40:38.44#ibcon#about to read 6, iclass 10, count 2 2006.201.05:40:38.44#ibcon#read 6, iclass 10, count 2 2006.201.05:40:38.44#ibcon#end of sib2, iclass 10, count 2 2006.201.05:40:38.44#ibcon#*mode == 0, iclass 10, count 2 2006.201.05:40:38.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.05:40:38.44#ibcon#[25=AT04-07\r\n] 2006.201.05:40:38.44#ibcon#*before write, iclass 10, count 2 2006.201.05:40:38.44#ibcon#enter sib2, iclass 10, count 2 2006.201.05:40:38.44#ibcon#flushed, iclass 10, count 2 2006.201.05:40:38.44#ibcon#about to write, iclass 10, count 2 2006.201.05:40:38.44#ibcon#wrote, iclass 10, count 2 2006.201.05:40:38.44#ibcon#about to read 3, iclass 10, count 2 2006.201.05:40:38.47#ibcon#read 3, iclass 10, count 2 2006.201.05:40:38.47#ibcon#about to read 4, iclass 10, count 2 2006.201.05:40:38.54#ibcon#read 4, iclass 10, count 2 2006.201.05:40:38.54#ibcon#about to read 5, iclass 10, count 2 2006.201.05:40:38.54#ibcon#read 5, iclass 10, count 2 2006.201.05:40:38.54#ibcon#about to read 6, iclass 10, count 2 2006.201.05:40:38.54#ibcon#read 6, iclass 10, count 2 2006.201.05:40:38.54#ibcon#end of sib2, iclass 10, count 2 2006.201.05:40:38.54#ibcon#*after write, iclass 10, count 2 2006.201.05:40:38.54#ibcon#*before return 0, iclass 10, count 2 2006.201.05:40:38.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:38.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:38.54#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.05:40:38.54#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:38.54#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:38.66#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:38.66#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:38.66#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:40:38.66#ibcon#first serial, iclass 10, count 0 2006.201.05:40:38.66#ibcon#enter sib2, iclass 10, count 0 2006.201.05:40:38.66#ibcon#flushed, iclass 10, count 0 2006.201.05:40:38.66#ibcon#about to write, iclass 10, count 0 2006.201.05:40:38.66#ibcon#wrote, iclass 10, count 0 2006.201.05:40:38.66#ibcon#about to read 3, iclass 10, count 0 2006.201.05:40:38.68#ibcon#read 3, iclass 10, count 0 2006.201.05:40:38.68#ibcon#about to read 4, iclass 10, count 0 2006.201.05:40:38.68#ibcon#read 4, iclass 10, count 0 2006.201.05:40:38.68#ibcon#about to read 5, iclass 10, count 0 2006.201.05:40:38.68#ibcon#read 5, iclass 10, count 0 2006.201.05:40:38.68#ibcon#about to read 6, iclass 10, count 0 2006.201.05:40:38.68#ibcon#read 6, iclass 10, count 0 2006.201.05:40:38.68#ibcon#end of sib2, iclass 10, count 0 2006.201.05:40:38.68#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:40:38.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:40:38.68#ibcon#[25=USB\r\n] 2006.201.05:40:38.68#ibcon#*before write, iclass 10, count 0 2006.201.05:40:38.68#ibcon#enter sib2, iclass 10, count 0 2006.201.05:40:38.68#ibcon#flushed, iclass 10, count 0 2006.201.05:40:38.68#ibcon#about to write, iclass 10, count 0 2006.201.05:40:38.68#ibcon#wrote, iclass 10, count 0 2006.201.05:40:38.68#ibcon#about to read 3, iclass 10, count 0 2006.201.05:40:38.71#ibcon#read 3, iclass 10, count 0 2006.201.05:40:38.71#ibcon#about to read 4, iclass 10, count 0 2006.201.05:40:38.71#ibcon#read 4, iclass 10, count 0 2006.201.05:40:38.71#ibcon#about to read 5, iclass 10, count 0 2006.201.05:40:38.71#ibcon#read 5, iclass 10, count 0 2006.201.05:40:38.71#ibcon#about to read 6, iclass 10, count 0 2006.201.05:40:38.71#ibcon#read 6, iclass 10, count 0 2006.201.05:40:38.71#ibcon#end of sib2, iclass 10, count 0 2006.201.05:40:38.71#ibcon#*after write, iclass 10, count 0 2006.201.05:40:38.71#ibcon#*before return 0, iclass 10, count 0 2006.201.05:40:38.71#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:38.71#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:38.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:40:38.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:40:38.71$vck44/valo=5,734.99 2006.201.05:40:38.71#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.05:40:38.71#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.05:40:38.71#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:38.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:38.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:38.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:38.71#ibcon#enter wrdev, iclass 12, count 0 2006.201.05:40:38.71#ibcon#first serial, iclass 12, count 0 2006.201.05:40:38.71#ibcon#enter sib2, iclass 12, count 0 2006.201.05:40:38.71#ibcon#flushed, iclass 12, count 0 2006.201.05:40:38.71#ibcon#about to write, iclass 12, count 0 2006.201.05:40:38.71#ibcon#wrote, iclass 12, count 0 2006.201.05:40:38.71#ibcon#about to read 3, iclass 12, count 0 2006.201.05:40:38.73#ibcon#read 3, iclass 12, count 0 2006.201.05:40:38.73#ibcon#about to read 4, iclass 12, count 0 2006.201.05:40:38.73#ibcon#read 4, iclass 12, count 0 2006.201.05:40:38.73#ibcon#about to read 5, iclass 12, count 0 2006.201.05:40:38.73#ibcon#read 5, iclass 12, count 0 2006.201.05:40:38.73#ibcon#about to read 6, iclass 12, count 0 2006.201.05:40:38.73#ibcon#read 6, iclass 12, count 0 2006.201.05:40:38.73#ibcon#end of sib2, iclass 12, count 0 2006.201.05:40:38.73#ibcon#*mode == 0, iclass 12, count 0 2006.201.05:40:38.73#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.05:40:38.73#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:40:38.73#ibcon#*before write, iclass 12, count 0 2006.201.05:40:38.73#ibcon#enter sib2, iclass 12, count 0 2006.201.05:40:38.73#ibcon#flushed, iclass 12, count 0 2006.201.05:40:38.73#ibcon#about to write, iclass 12, count 0 2006.201.05:40:38.73#ibcon#wrote, iclass 12, count 0 2006.201.05:40:38.73#ibcon#about to read 3, iclass 12, count 0 2006.201.05:40:38.77#ibcon#read 3, iclass 12, count 0 2006.201.05:40:38.77#ibcon#about to read 4, iclass 12, count 0 2006.201.05:40:38.77#ibcon#read 4, iclass 12, count 0 2006.201.05:40:38.77#ibcon#about to read 5, iclass 12, count 0 2006.201.05:40:38.77#ibcon#read 5, iclass 12, count 0 2006.201.05:40:38.77#ibcon#about to read 6, iclass 12, count 0 2006.201.05:40:38.77#ibcon#read 6, iclass 12, count 0 2006.201.05:40:38.77#ibcon#end of sib2, iclass 12, count 0 2006.201.05:40:38.77#ibcon#*after write, iclass 12, count 0 2006.201.05:40:38.77#ibcon#*before return 0, iclass 12, count 0 2006.201.05:40:38.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:38.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:38.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.05:40:38.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.05:40:38.77$vck44/va=5,4 2006.201.05:40:38.77#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.05:40:38.77#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.05:40:38.77#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:38.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:38.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:38.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:38.83#ibcon#enter wrdev, iclass 14, count 2 2006.201.05:40:38.83#ibcon#first serial, iclass 14, count 2 2006.201.05:40:38.83#ibcon#enter sib2, iclass 14, count 2 2006.201.05:40:38.83#ibcon#flushed, iclass 14, count 2 2006.201.05:40:38.83#ibcon#about to write, iclass 14, count 2 2006.201.05:40:38.83#ibcon#wrote, iclass 14, count 2 2006.201.05:40:38.83#ibcon#about to read 3, iclass 14, count 2 2006.201.05:40:38.85#ibcon#read 3, iclass 14, count 2 2006.201.05:40:38.85#ibcon#about to read 4, iclass 14, count 2 2006.201.05:40:38.85#ibcon#read 4, iclass 14, count 2 2006.201.05:40:38.85#ibcon#about to read 5, iclass 14, count 2 2006.201.05:40:38.85#ibcon#read 5, iclass 14, count 2 2006.201.05:40:38.85#ibcon#about to read 6, iclass 14, count 2 2006.201.05:40:38.85#ibcon#read 6, iclass 14, count 2 2006.201.05:40:38.85#ibcon#end of sib2, iclass 14, count 2 2006.201.05:40:38.85#ibcon#*mode == 0, iclass 14, count 2 2006.201.05:40:38.85#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.05:40:38.85#ibcon#[25=AT05-04\r\n] 2006.201.05:40:38.85#ibcon#*before write, iclass 14, count 2 2006.201.05:40:38.85#ibcon#enter sib2, iclass 14, count 2 2006.201.05:40:38.85#ibcon#flushed, iclass 14, count 2 2006.201.05:40:38.85#ibcon#about to write, iclass 14, count 2 2006.201.05:40:38.85#ibcon#wrote, iclass 14, count 2 2006.201.05:40:38.85#ibcon#about to read 3, iclass 14, count 2 2006.201.05:40:38.88#ibcon#read 3, iclass 14, count 2 2006.201.05:40:38.88#ibcon#about to read 4, iclass 14, count 2 2006.201.05:40:38.88#ibcon#read 4, iclass 14, count 2 2006.201.05:40:38.88#ibcon#about to read 5, iclass 14, count 2 2006.201.05:40:38.88#ibcon#read 5, iclass 14, count 2 2006.201.05:40:38.88#ibcon#about to read 6, iclass 14, count 2 2006.201.05:40:38.88#ibcon#read 6, iclass 14, count 2 2006.201.05:40:38.88#ibcon#end of sib2, iclass 14, count 2 2006.201.05:40:38.88#ibcon#*after write, iclass 14, count 2 2006.201.05:40:38.88#ibcon#*before return 0, iclass 14, count 2 2006.201.05:40:38.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:38.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:38.88#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.05:40:38.88#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:38.88#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:39.00#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:39.00#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:39.00#ibcon#enter wrdev, iclass 14, count 0 2006.201.05:40:39.00#ibcon#first serial, iclass 14, count 0 2006.201.05:40:39.00#ibcon#enter sib2, iclass 14, count 0 2006.201.05:40:39.00#ibcon#flushed, iclass 14, count 0 2006.201.05:40:39.00#ibcon#about to write, iclass 14, count 0 2006.201.05:40:39.00#ibcon#wrote, iclass 14, count 0 2006.201.05:40:39.00#ibcon#about to read 3, iclass 14, count 0 2006.201.05:40:39.02#ibcon#read 3, iclass 14, count 0 2006.201.05:40:39.02#ibcon#about to read 4, iclass 14, count 0 2006.201.05:40:39.02#ibcon#read 4, iclass 14, count 0 2006.201.05:40:39.02#ibcon#about to read 5, iclass 14, count 0 2006.201.05:40:39.02#ibcon#read 5, iclass 14, count 0 2006.201.05:40:39.02#ibcon#about to read 6, iclass 14, count 0 2006.201.05:40:39.02#ibcon#read 6, iclass 14, count 0 2006.201.05:40:39.02#ibcon#end of sib2, iclass 14, count 0 2006.201.05:40:39.02#ibcon#*mode == 0, iclass 14, count 0 2006.201.05:40:39.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.05:40:39.02#ibcon#[25=USB\r\n] 2006.201.05:40:39.02#ibcon#*before write, iclass 14, count 0 2006.201.05:40:39.02#ibcon#enter sib2, iclass 14, count 0 2006.201.05:40:39.02#ibcon#flushed, iclass 14, count 0 2006.201.05:40:39.02#ibcon#about to write, iclass 14, count 0 2006.201.05:40:39.02#ibcon#wrote, iclass 14, count 0 2006.201.05:40:39.02#ibcon#about to read 3, iclass 14, count 0 2006.201.05:40:39.05#ibcon#read 3, iclass 14, count 0 2006.201.05:40:39.05#ibcon#about to read 4, iclass 14, count 0 2006.201.05:40:39.05#ibcon#read 4, iclass 14, count 0 2006.201.05:40:39.05#ibcon#about to read 5, iclass 14, count 0 2006.201.05:40:39.05#ibcon#read 5, iclass 14, count 0 2006.201.05:40:39.05#ibcon#about to read 6, iclass 14, count 0 2006.201.05:40:39.05#ibcon#read 6, iclass 14, count 0 2006.201.05:40:39.05#ibcon#end of sib2, iclass 14, count 0 2006.201.05:40:39.05#ibcon#*after write, iclass 14, count 0 2006.201.05:40:39.05#ibcon#*before return 0, iclass 14, count 0 2006.201.05:40:39.05#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:39.05#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:39.05#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.05:40:39.05#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.05:40:39.05$vck44/valo=6,814.99 2006.201.05:40:39.05#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.05:40:39.05#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.05:40:39.05#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:39.05#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:39.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:39.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:39.05#ibcon#enter wrdev, iclass 16, count 0 2006.201.05:40:39.05#ibcon#first serial, iclass 16, count 0 2006.201.05:40:39.05#ibcon#enter sib2, iclass 16, count 0 2006.201.05:40:39.05#ibcon#flushed, iclass 16, count 0 2006.201.05:40:39.05#ibcon#about to write, iclass 16, count 0 2006.201.05:40:39.05#ibcon#wrote, iclass 16, count 0 2006.201.05:40:39.05#ibcon#about to read 3, iclass 16, count 0 2006.201.05:40:39.07#ibcon#read 3, iclass 16, count 0 2006.201.05:40:39.07#ibcon#about to read 4, iclass 16, count 0 2006.201.05:40:39.07#ibcon#read 4, iclass 16, count 0 2006.201.05:40:39.07#ibcon#about to read 5, iclass 16, count 0 2006.201.05:40:39.07#ibcon#read 5, iclass 16, count 0 2006.201.05:40:39.07#ibcon#about to read 6, iclass 16, count 0 2006.201.05:40:39.07#ibcon#read 6, iclass 16, count 0 2006.201.05:40:39.07#ibcon#end of sib2, iclass 16, count 0 2006.201.05:40:39.07#ibcon#*mode == 0, iclass 16, count 0 2006.201.05:40:39.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.05:40:39.07#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:40:39.07#ibcon#*before write, iclass 16, count 0 2006.201.05:40:39.07#ibcon#enter sib2, iclass 16, count 0 2006.201.05:40:39.07#ibcon#flushed, iclass 16, count 0 2006.201.05:40:39.07#ibcon#about to write, iclass 16, count 0 2006.201.05:40:39.07#ibcon#wrote, iclass 16, count 0 2006.201.05:40:39.07#ibcon#about to read 3, iclass 16, count 0 2006.201.05:40:39.11#ibcon#read 3, iclass 16, count 0 2006.201.05:40:39.11#ibcon#about to read 4, iclass 16, count 0 2006.201.05:40:39.11#ibcon#read 4, iclass 16, count 0 2006.201.05:40:39.11#ibcon#about to read 5, iclass 16, count 0 2006.201.05:40:39.11#ibcon#read 5, iclass 16, count 0 2006.201.05:40:39.11#ibcon#about to read 6, iclass 16, count 0 2006.201.05:40:39.11#ibcon#read 6, iclass 16, count 0 2006.201.05:40:39.11#ibcon#end of sib2, iclass 16, count 0 2006.201.05:40:39.11#ibcon#*after write, iclass 16, count 0 2006.201.05:40:39.11#ibcon#*before return 0, iclass 16, count 0 2006.201.05:40:39.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:39.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:39.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.05:40:39.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.05:40:39.11$vck44/va=6,5 2006.201.05:40:39.11#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.05:40:39.11#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.05:40:39.11#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:39.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:39.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:39.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:39.17#ibcon#enter wrdev, iclass 18, count 2 2006.201.05:40:39.17#ibcon#first serial, iclass 18, count 2 2006.201.05:40:39.17#ibcon#enter sib2, iclass 18, count 2 2006.201.05:40:39.17#ibcon#flushed, iclass 18, count 2 2006.201.05:40:39.17#ibcon#about to write, iclass 18, count 2 2006.201.05:40:39.17#ibcon#wrote, iclass 18, count 2 2006.201.05:40:39.17#ibcon#about to read 3, iclass 18, count 2 2006.201.05:40:39.19#ibcon#read 3, iclass 18, count 2 2006.201.05:40:39.19#ibcon#about to read 4, iclass 18, count 2 2006.201.05:40:39.19#ibcon#read 4, iclass 18, count 2 2006.201.05:40:39.19#ibcon#about to read 5, iclass 18, count 2 2006.201.05:40:39.19#ibcon#read 5, iclass 18, count 2 2006.201.05:40:39.19#ibcon#about to read 6, iclass 18, count 2 2006.201.05:40:39.19#ibcon#read 6, iclass 18, count 2 2006.201.05:40:39.19#ibcon#end of sib2, iclass 18, count 2 2006.201.05:40:39.19#ibcon#*mode == 0, iclass 18, count 2 2006.201.05:40:39.19#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.05:40:39.19#ibcon#[25=AT06-05\r\n] 2006.201.05:40:39.19#ibcon#*before write, iclass 18, count 2 2006.201.05:40:39.19#ibcon#enter sib2, iclass 18, count 2 2006.201.05:40:39.19#ibcon#flushed, iclass 18, count 2 2006.201.05:40:39.19#ibcon#about to write, iclass 18, count 2 2006.201.05:40:39.19#ibcon#wrote, iclass 18, count 2 2006.201.05:40:39.19#ibcon#about to read 3, iclass 18, count 2 2006.201.05:40:39.22#ibcon#read 3, iclass 18, count 2 2006.201.05:40:39.22#ibcon#about to read 4, iclass 18, count 2 2006.201.05:40:39.22#ibcon#read 4, iclass 18, count 2 2006.201.05:40:39.22#ibcon#about to read 5, iclass 18, count 2 2006.201.05:40:39.22#ibcon#read 5, iclass 18, count 2 2006.201.05:40:39.22#ibcon#about to read 6, iclass 18, count 2 2006.201.05:40:39.22#ibcon#read 6, iclass 18, count 2 2006.201.05:40:39.22#ibcon#end of sib2, iclass 18, count 2 2006.201.05:40:39.22#ibcon#*after write, iclass 18, count 2 2006.201.05:40:39.22#ibcon#*before return 0, iclass 18, count 2 2006.201.05:40:39.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:39.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:39.22#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.05:40:39.22#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:39.22#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:39.34#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:39.34#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:39.34#ibcon#enter wrdev, iclass 18, count 0 2006.201.05:40:39.34#ibcon#first serial, iclass 18, count 0 2006.201.05:40:39.34#ibcon#enter sib2, iclass 18, count 0 2006.201.05:40:39.34#ibcon#flushed, iclass 18, count 0 2006.201.05:40:39.34#ibcon#about to write, iclass 18, count 0 2006.201.05:40:39.34#ibcon#wrote, iclass 18, count 0 2006.201.05:40:39.34#ibcon#about to read 3, iclass 18, count 0 2006.201.05:40:39.36#ibcon#read 3, iclass 18, count 0 2006.201.05:40:39.36#ibcon#about to read 4, iclass 18, count 0 2006.201.05:40:39.36#ibcon#read 4, iclass 18, count 0 2006.201.05:40:39.36#ibcon#about to read 5, iclass 18, count 0 2006.201.05:40:39.36#ibcon#read 5, iclass 18, count 0 2006.201.05:40:39.36#ibcon#about to read 6, iclass 18, count 0 2006.201.05:40:39.36#ibcon#read 6, iclass 18, count 0 2006.201.05:40:39.36#ibcon#end of sib2, iclass 18, count 0 2006.201.05:40:39.36#ibcon#*mode == 0, iclass 18, count 0 2006.201.05:40:39.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.05:40:39.36#ibcon#[25=USB\r\n] 2006.201.05:40:39.36#ibcon#*before write, iclass 18, count 0 2006.201.05:40:39.36#ibcon#enter sib2, iclass 18, count 0 2006.201.05:40:39.36#ibcon#flushed, iclass 18, count 0 2006.201.05:40:39.36#ibcon#about to write, iclass 18, count 0 2006.201.05:40:39.36#ibcon#wrote, iclass 18, count 0 2006.201.05:40:39.36#ibcon#about to read 3, iclass 18, count 0 2006.201.05:40:39.39#ibcon#read 3, iclass 18, count 0 2006.201.05:40:39.39#ibcon#about to read 4, iclass 18, count 0 2006.201.05:40:39.39#ibcon#read 4, iclass 18, count 0 2006.201.05:40:39.39#ibcon#about to read 5, iclass 18, count 0 2006.201.05:40:39.39#ibcon#read 5, iclass 18, count 0 2006.201.05:40:39.39#ibcon#about to read 6, iclass 18, count 0 2006.201.05:40:39.39#ibcon#read 6, iclass 18, count 0 2006.201.05:40:39.39#ibcon#end of sib2, iclass 18, count 0 2006.201.05:40:39.39#ibcon#*after write, iclass 18, count 0 2006.201.05:40:39.39#ibcon#*before return 0, iclass 18, count 0 2006.201.05:40:39.39#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:39.39#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:39.39#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.05:40:39.39#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.05:40:39.39$vck44/valo=7,864.99 2006.201.05:40:39.39#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.05:40:39.39#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.05:40:39.39#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:39.39#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:39.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:39.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:39.39#ibcon#enter wrdev, iclass 20, count 0 2006.201.05:40:39.39#ibcon#first serial, iclass 20, count 0 2006.201.05:40:39.39#ibcon#enter sib2, iclass 20, count 0 2006.201.05:40:39.39#ibcon#flushed, iclass 20, count 0 2006.201.05:40:39.39#ibcon#about to write, iclass 20, count 0 2006.201.05:40:39.39#ibcon#wrote, iclass 20, count 0 2006.201.05:40:39.39#ibcon#about to read 3, iclass 20, count 0 2006.201.05:40:39.41#ibcon#read 3, iclass 20, count 0 2006.201.05:40:39.41#ibcon#about to read 4, iclass 20, count 0 2006.201.05:40:39.41#ibcon#read 4, iclass 20, count 0 2006.201.05:40:39.41#ibcon#about to read 5, iclass 20, count 0 2006.201.05:40:39.41#ibcon#read 5, iclass 20, count 0 2006.201.05:40:39.41#ibcon#about to read 6, iclass 20, count 0 2006.201.05:40:39.41#ibcon#read 6, iclass 20, count 0 2006.201.05:40:39.41#ibcon#end of sib2, iclass 20, count 0 2006.201.05:40:39.41#ibcon#*mode == 0, iclass 20, count 0 2006.201.05:40:39.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.05:40:39.41#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:40:39.41#ibcon#*before write, iclass 20, count 0 2006.201.05:40:39.41#ibcon#enter sib2, iclass 20, count 0 2006.201.05:40:39.41#ibcon#flushed, iclass 20, count 0 2006.201.05:40:39.41#ibcon#about to write, iclass 20, count 0 2006.201.05:40:39.41#ibcon#wrote, iclass 20, count 0 2006.201.05:40:39.41#ibcon#about to read 3, iclass 20, count 0 2006.201.05:40:39.45#ibcon#read 3, iclass 20, count 0 2006.201.05:40:39.45#ibcon#about to read 4, iclass 20, count 0 2006.201.05:40:39.45#ibcon#read 4, iclass 20, count 0 2006.201.05:40:39.45#ibcon#about to read 5, iclass 20, count 0 2006.201.05:40:39.45#ibcon#read 5, iclass 20, count 0 2006.201.05:40:39.45#ibcon#about to read 6, iclass 20, count 0 2006.201.05:40:39.45#ibcon#read 6, iclass 20, count 0 2006.201.05:40:39.45#ibcon#end of sib2, iclass 20, count 0 2006.201.05:40:39.45#ibcon#*after write, iclass 20, count 0 2006.201.05:40:39.45#ibcon#*before return 0, iclass 20, count 0 2006.201.05:40:39.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:39.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:39.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.05:40:39.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.05:40:39.45$vck44/va=7,5 2006.201.05:40:39.45#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.05:40:39.45#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.05:40:39.45#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:39.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:39.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:39.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:39.51#ibcon#enter wrdev, iclass 22, count 2 2006.201.05:40:39.51#ibcon#first serial, iclass 22, count 2 2006.201.05:40:39.51#ibcon#enter sib2, iclass 22, count 2 2006.201.05:40:39.51#ibcon#flushed, iclass 22, count 2 2006.201.05:40:39.51#ibcon#about to write, iclass 22, count 2 2006.201.05:40:39.51#ibcon#wrote, iclass 22, count 2 2006.201.05:40:39.51#ibcon#about to read 3, iclass 22, count 2 2006.201.05:40:39.53#ibcon#read 3, iclass 22, count 2 2006.201.05:40:39.53#ibcon#about to read 4, iclass 22, count 2 2006.201.05:40:39.53#ibcon#read 4, iclass 22, count 2 2006.201.05:40:39.53#ibcon#about to read 5, iclass 22, count 2 2006.201.05:40:39.53#ibcon#read 5, iclass 22, count 2 2006.201.05:40:39.53#ibcon#about to read 6, iclass 22, count 2 2006.201.05:40:39.53#ibcon#read 6, iclass 22, count 2 2006.201.05:40:39.53#ibcon#end of sib2, iclass 22, count 2 2006.201.05:40:39.53#ibcon#*mode == 0, iclass 22, count 2 2006.201.05:40:39.53#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.05:40:39.53#ibcon#[25=AT07-05\r\n] 2006.201.05:40:39.53#ibcon#*before write, iclass 22, count 2 2006.201.05:40:39.53#ibcon#enter sib2, iclass 22, count 2 2006.201.05:40:39.53#ibcon#flushed, iclass 22, count 2 2006.201.05:40:39.53#ibcon#about to write, iclass 22, count 2 2006.201.05:40:39.53#ibcon#wrote, iclass 22, count 2 2006.201.05:40:39.53#ibcon#about to read 3, iclass 22, count 2 2006.201.05:40:39.56#ibcon#read 3, iclass 22, count 2 2006.201.05:40:39.65#ibcon#about to read 4, iclass 22, count 2 2006.201.05:40:39.65#ibcon#read 4, iclass 22, count 2 2006.201.05:40:39.65#ibcon#about to read 5, iclass 22, count 2 2006.201.05:40:39.65#ibcon#read 5, iclass 22, count 2 2006.201.05:40:39.65#ibcon#about to read 6, iclass 22, count 2 2006.201.05:40:39.65#ibcon#read 6, iclass 22, count 2 2006.201.05:40:39.65#ibcon#end of sib2, iclass 22, count 2 2006.201.05:40:39.65#ibcon#*after write, iclass 22, count 2 2006.201.05:40:39.65#ibcon#*before return 0, iclass 22, count 2 2006.201.05:40:39.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:39.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:39.65#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.05:40:39.65#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:39.65#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:39.77#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:39.77#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:39.77#ibcon#enter wrdev, iclass 22, count 0 2006.201.05:40:39.77#ibcon#first serial, iclass 22, count 0 2006.201.05:40:39.77#ibcon#enter sib2, iclass 22, count 0 2006.201.05:40:39.77#ibcon#flushed, iclass 22, count 0 2006.201.05:40:39.77#ibcon#about to write, iclass 22, count 0 2006.201.05:40:39.77#ibcon#wrote, iclass 22, count 0 2006.201.05:40:39.77#ibcon#about to read 3, iclass 22, count 0 2006.201.05:40:39.79#ibcon#read 3, iclass 22, count 0 2006.201.05:40:39.79#ibcon#about to read 4, iclass 22, count 0 2006.201.05:40:39.79#ibcon#read 4, iclass 22, count 0 2006.201.05:40:39.79#ibcon#about to read 5, iclass 22, count 0 2006.201.05:40:39.79#ibcon#read 5, iclass 22, count 0 2006.201.05:40:39.79#ibcon#about to read 6, iclass 22, count 0 2006.201.05:40:39.79#ibcon#read 6, iclass 22, count 0 2006.201.05:40:39.79#ibcon#end of sib2, iclass 22, count 0 2006.201.05:40:39.79#ibcon#*mode == 0, iclass 22, count 0 2006.201.05:40:39.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.05:40:39.79#ibcon#[25=USB\r\n] 2006.201.05:40:39.79#ibcon#*before write, iclass 22, count 0 2006.201.05:40:39.79#ibcon#enter sib2, iclass 22, count 0 2006.201.05:40:39.79#ibcon#flushed, iclass 22, count 0 2006.201.05:40:39.79#ibcon#about to write, iclass 22, count 0 2006.201.05:40:39.79#ibcon#wrote, iclass 22, count 0 2006.201.05:40:39.79#ibcon#about to read 3, iclass 22, count 0 2006.201.05:40:39.82#ibcon#read 3, iclass 22, count 0 2006.201.05:40:39.82#ibcon#about to read 4, iclass 22, count 0 2006.201.05:40:39.82#ibcon#read 4, iclass 22, count 0 2006.201.05:40:39.82#ibcon#about to read 5, iclass 22, count 0 2006.201.05:40:39.82#ibcon#read 5, iclass 22, count 0 2006.201.05:40:39.82#ibcon#about to read 6, iclass 22, count 0 2006.201.05:40:39.82#ibcon#read 6, iclass 22, count 0 2006.201.05:40:39.82#ibcon#end of sib2, iclass 22, count 0 2006.201.05:40:39.82#ibcon#*after write, iclass 22, count 0 2006.201.05:40:39.82#ibcon#*before return 0, iclass 22, count 0 2006.201.05:40:39.82#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:39.82#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:39.82#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.05:40:39.82#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.05:40:39.82$vck44/valo=8,884.99 2006.201.05:40:39.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.05:40:39.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.05:40:39.82#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:39.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:39.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:39.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:39.82#ibcon#enter wrdev, iclass 24, count 0 2006.201.05:40:39.82#ibcon#first serial, iclass 24, count 0 2006.201.05:40:39.82#ibcon#enter sib2, iclass 24, count 0 2006.201.05:40:39.82#ibcon#flushed, iclass 24, count 0 2006.201.05:40:39.82#ibcon#about to write, iclass 24, count 0 2006.201.05:40:39.82#ibcon#wrote, iclass 24, count 0 2006.201.05:40:39.82#ibcon#about to read 3, iclass 24, count 0 2006.201.05:40:39.84#ibcon#read 3, iclass 24, count 0 2006.201.05:40:39.84#ibcon#about to read 4, iclass 24, count 0 2006.201.05:40:39.84#ibcon#read 4, iclass 24, count 0 2006.201.05:40:39.84#ibcon#about to read 5, iclass 24, count 0 2006.201.05:40:39.84#ibcon#read 5, iclass 24, count 0 2006.201.05:40:39.84#ibcon#about to read 6, iclass 24, count 0 2006.201.05:40:39.84#ibcon#read 6, iclass 24, count 0 2006.201.05:40:39.84#ibcon#end of sib2, iclass 24, count 0 2006.201.05:40:39.84#ibcon#*mode == 0, iclass 24, count 0 2006.201.05:40:39.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.05:40:39.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:40:39.84#ibcon#*before write, iclass 24, count 0 2006.201.05:40:39.84#ibcon#enter sib2, iclass 24, count 0 2006.201.05:40:39.84#ibcon#flushed, iclass 24, count 0 2006.201.05:40:39.84#ibcon#about to write, iclass 24, count 0 2006.201.05:40:39.84#ibcon#wrote, iclass 24, count 0 2006.201.05:40:39.84#ibcon#about to read 3, iclass 24, count 0 2006.201.05:40:39.88#ibcon#read 3, iclass 24, count 0 2006.201.05:40:39.88#ibcon#about to read 4, iclass 24, count 0 2006.201.05:40:39.88#ibcon#read 4, iclass 24, count 0 2006.201.05:40:39.88#ibcon#about to read 5, iclass 24, count 0 2006.201.05:40:39.88#ibcon#read 5, iclass 24, count 0 2006.201.05:40:39.88#ibcon#about to read 6, iclass 24, count 0 2006.201.05:40:39.88#ibcon#read 6, iclass 24, count 0 2006.201.05:40:39.88#ibcon#end of sib2, iclass 24, count 0 2006.201.05:40:39.88#ibcon#*after write, iclass 24, count 0 2006.201.05:40:39.88#ibcon#*before return 0, iclass 24, count 0 2006.201.05:40:39.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:39.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:39.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.05:40:39.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.05:40:39.88$vck44/va=8,4 2006.201.05:40:39.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.05:40:39.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.05:40:39.88#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:39.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:40:39.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:40:39.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:40:39.94#ibcon#enter wrdev, iclass 26, count 2 2006.201.05:40:39.94#ibcon#first serial, iclass 26, count 2 2006.201.05:40:39.94#ibcon#enter sib2, iclass 26, count 2 2006.201.05:40:39.94#ibcon#flushed, iclass 26, count 2 2006.201.05:40:39.94#ibcon#about to write, iclass 26, count 2 2006.201.05:40:39.94#ibcon#wrote, iclass 26, count 2 2006.201.05:40:39.94#ibcon#about to read 3, iclass 26, count 2 2006.201.05:40:39.96#ibcon#read 3, iclass 26, count 2 2006.201.05:40:39.96#ibcon#about to read 4, iclass 26, count 2 2006.201.05:40:39.96#ibcon#read 4, iclass 26, count 2 2006.201.05:40:39.96#ibcon#about to read 5, iclass 26, count 2 2006.201.05:40:39.96#ibcon#read 5, iclass 26, count 2 2006.201.05:40:39.96#ibcon#about to read 6, iclass 26, count 2 2006.201.05:40:39.96#ibcon#read 6, iclass 26, count 2 2006.201.05:40:39.96#ibcon#end of sib2, iclass 26, count 2 2006.201.05:40:39.96#ibcon#*mode == 0, iclass 26, count 2 2006.201.05:40:39.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.05:40:39.96#ibcon#[25=AT08-04\r\n] 2006.201.05:40:39.96#ibcon#*before write, iclass 26, count 2 2006.201.05:40:39.96#ibcon#enter sib2, iclass 26, count 2 2006.201.05:40:39.96#ibcon#flushed, iclass 26, count 2 2006.201.05:40:39.96#ibcon#about to write, iclass 26, count 2 2006.201.05:40:39.96#ibcon#wrote, iclass 26, count 2 2006.201.05:40:39.96#ibcon#about to read 3, iclass 26, count 2 2006.201.05:40:39.99#ibcon#read 3, iclass 26, count 2 2006.201.05:40:39.99#ibcon#about to read 4, iclass 26, count 2 2006.201.05:40:39.99#ibcon#read 4, iclass 26, count 2 2006.201.05:40:39.99#ibcon#about to read 5, iclass 26, count 2 2006.201.05:40:39.99#ibcon#read 5, iclass 26, count 2 2006.201.05:40:39.99#ibcon#about to read 6, iclass 26, count 2 2006.201.05:40:39.99#ibcon#read 6, iclass 26, count 2 2006.201.05:40:39.99#ibcon#end of sib2, iclass 26, count 2 2006.201.05:40:39.99#ibcon#*after write, iclass 26, count 2 2006.201.05:40:39.99#ibcon#*before return 0, iclass 26, count 2 2006.201.05:40:39.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:40:39.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.05:40:39.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.05:40:39.99#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:39.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:40:40.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:40:40.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:40:40.11#ibcon#enter wrdev, iclass 26, count 0 2006.201.05:40:40.11#ibcon#first serial, iclass 26, count 0 2006.201.05:40:40.11#ibcon#enter sib2, iclass 26, count 0 2006.201.05:40:40.11#ibcon#flushed, iclass 26, count 0 2006.201.05:40:40.11#ibcon#about to write, iclass 26, count 0 2006.201.05:40:40.11#ibcon#wrote, iclass 26, count 0 2006.201.05:40:40.11#ibcon#about to read 3, iclass 26, count 0 2006.201.05:40:40.13#ibcon#read 3, iclass 26, count 0 2006.201.05:40:40.13#ibcon#about to read 4, iclass 26, count 0 2006.201.05:40:40.13#ibcon#read 4, iclass 26, count 0 2006.201.05:40:40.13#ibcon#about to read 5, iclass 26, count 0 2006.201.05:40:40.13#ibcon#read 5, iclass 26, count 0 2006.201.05:40:40.13#ibcon#about to read 6, iclass 26, count 0 2006.201.05:40:40.13#ibcon#read 6, iclass 26, count 0 2006.201.05:40:40.13#ibcon#end of sib2, iclass 26, count 0 2006.201.05:40:40.13#ibcon#*mode == 0, iclass 26, count 0 2006.201.05:40:40.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.05:40:40.13#ibcon#[25=USB\r\n] 2006.201.05:40:40.13#ibcon#*before write, iclass 26, count 0 2006.201.05:40:40.13#ibcon#enter sib2, iclass 26, count 0 2006.201.05:40:40.13#ibcon#flushed, iclass 26, count 0 2006.201.05:40:40.13#ibcon#about to write, iclass 26, count 0 2006.201.05:40:40.13#ibcon#wrote, iclass 26, count 0 2006.201.05:40:40.13#ibcon#about to read 3, iclass 26, count 0 2006.201.05:40:40.16#ibcon#read 3, iclass 26, count 0 2006.201.05:40:40.16#ibcon#about to read 4, iclass 26, count 0 2006.201.05:40:40.16#ibcon#read 4, iclass 26, count 0 2006.201.05:40:40.16#ibcon#about to read 5, iclass 26, count 0 2006.201.05:40:40.16#ibcon#read 5, iclass 26, count 0 2006.201.05:40:40.16#ibcon#about to read 6, iclass 26, count 0 2006.201.05:40:40.16#ibcon#read 6, iclass 26, count 0 2006.201.05:40:40.16#ibcon#end of sib2, iclass 26, count 0 2006.201.05:40:40.16#ibcon#*after write, iclass 26, count 0 2006.201.05:40:40.16#ibcon#*before return 0, iclass 26, count 0 2006.201.05:40:40.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:40:40.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.05:40:40.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.05:40:40.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.05:40:40.16$vck44/vblo=1,629.99 2006.201.05:40:40.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.05:40:40.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.05:40:40.16#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:40.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:40:40.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:40:40.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:40:40.16#ibcon#enter wrdev, iclass 28, count 0 2006.201.05:40:40.16#ibcon#first serial, iclass 28, count 0 2006.201.05:40:40.16#ibcon#enter sib2, iclass 28, count 0 2006.201.05:40:40.16#ibcon#flushed, iclass 28, count 0 2006.201.05:40:40.16#ibcon#about to write, iclass 28, count 0 2006.201.05:40:40.16#ibcon#wrote, iclass 28, count 0 2006.201.05:40:40.16#ibcon#about to read 3, iclass 28, count 0 2006.201.05:40:40.18#ibcon#read 3, iclass 28, count 0 2006.201.05:40:40.18#ibcon#about to read 4, iclass 28, count 0 2006.201.05:40:40.18#ibcon#read 4, iclass 28, count 0 2006.201.05:40:40.18#ibcon#about to read 5, iclass 28, count 0 2006.201.05:40:40.18#ibcon#read 5, iclass 28, count 0 2006.201.05:40:40.18#ibcon#about to read 6, iclass 28, count 0 2006.201.05:40:40.18#ibcon#read 6, iclass 28, count 0 2006.201.05:40:40.18#ibcon#end of sib2, iclass 28, count 0 2006.201.05:40:40.18#ibcon#*mode == 0, iclass 28, count 0 2006.201.05:40:40.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.05:40:40.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:40:40.18#ibcon#*before write, iclass 28, count 0 2006.201.05:40:40.18#ibcon#enter sib2, iclass 28, count 0 2006.201.05:40:40.18#ibcon#flushed, iclass 28, count 0 2006.201.05:40:40.18#ibcon#about to write, iclass 28, count 0 2006.201.05:40:40.18#ibcon#wrote, iclass 28, count 0 2006.201.05:40:40.18#ibcon#about to read 3, iclass 28, count 0 2006.201.05:40:40.22#ibcon#read 3, iclass 28, count 0 2006.201.05:40:40.22#ibcon#about to read 4, iclass 28, count 0 2006.201.05:40:40.22#ibcon#read 4, iclass 28, count 0 2006.201.05:40:40.22#ibcon#about to read 5, iclass 28, count 0 2006.201.05:40:40.22#ibcon#read 5, iclass 28, count 0 2006.201.05:40:40.22#ibcon#about to read 6, iclass 28, count 0 2006.201.05:40:40.22#ibcon#read 6, iclass 28, count 0 2006.201.05:40:40.22#ibcon#end of sib2, iclass 28, count 0 2006.201.05:40:40.22#ibcon#*after write, iclass 28, count 0 2006.201.05:40:40.22#ibcon#*before return 0, iclass 28, count 0 2006.201.05:40:40.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:40:40.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.05:40:40.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.05:40:40.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.05:40:40.22$vck44/vb=1,4 2006.201.05:40:40.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.05:40:40.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.05:40:40.22#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:40.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:40:40.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:40:40.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:40:40.22#ibcon#enter wrdev, iclass 30, count 2 2006.201.05:40:40.22#ibcon#first serial, iclass 30, count 2 2006.201.05:40:40.22#ibcon#enter sib2, iclass 30, count 2 2006.201.05:40:40.22#ibcon#flushed, iclass 30, count 2 2006.201.05:40:40.22#ibcon#about to write, iclass 30, count 2 2006.201.05:40:40.22#ibcon#wrote, iclass 30, count 2 2006.201.05:40:40.22#ibcon#about to read 3, iclass 30, count 2 2006.201.05:40:40.24#ibcon#read 3, iclass 30, count 2 2006.201.05:40:40.24#ibcon#about to read 4, iclass 30, count 2 2006.201.05:40:40.24#ibcon#read 4, iclass 30, count 2 2006.201.05:40:40.24#ibcon#about to read 5, iclass 30, count 2 2006.201.05:40:40.24#ibcon#read 5, iclass 30, count 2 2006.201.05:40:40.24#ibcon#about to read 6, iclass 30, count 2 2006.201.05:40:40.24#ibcon#read 6, iclass 30, count 2 2006.201.05:40:40.24#ibcon#end of sib2, iclass 30, count 2 2006.201.05:40:40.24#ibcon#*mode == 0, iclass 30, count 2 2006.201.05:40:40.24#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.05:40:40.24#ibcon#[27=AT01-04\r\n] 2006.201.05:40:40.24#ibcon#*before write, iclass 30, count 2 2006.201.05:40:40.24#ibcon#enter sib2, iclass 30, count 2 2006.201.05:40:40.24#ibcon#flushed, iclass 30, count 2 2006.201.05:40:40.24#ibcon#about to write, iclass 30, count 2 2006.201.05:40:40.24#ibcon#wrote, iclass 30, count 2 2006.201.05:40:40.24#ibcon#about to read 3, iclass 30, count 2 2006.201.05:40:40.27#ibcon#read 3, iclass 30, count 2 2006.201.05:40:40.27#ibcon#about to read 4, iclass 30, count 2 2006.201.05:40:40.27#ibcon#read 4, iclass 30, count 2 2006.201.05:40:40.27#ibcon#about to read 5, iclass 30, count 2 2006.201.05:40:40.27#ibcon#read 5, iclass 30, count 2 2006.201.05:40:40.27#ibcon#about to read 6, iclass 30, count 2 2006.201.05:40:40.27#ibcon#read 6, iclass 30, count 2 2006.201.05:40:40.27#ibcon#end of sib2, iclass 30, count 2 2006.201.05:40:40.27#ibcon#*after write, iclass 30, count 2 2006.201.05:40:40.27#ibcon#*before return 0, iclass 30, count 2 2006.201.05:40:40.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:40:40.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.05:40:40.27#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.05:40:40.27#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:40.27#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:40:40.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:40:40.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:40:40.39#ibcon#enter wrdev, iclass 30, count 0 2006.201.05:40:40.39#ibcon#first serial, iclass 30, count 0 2006.201.05:40:40.39#ibcon#enter sib2, iclass 30, count 0 2006.201.05:40:40.39#ibcon#flushed, iclass 30, count 0 2006.201.05:40:40.39#ibcon#about to write, iclass 30, count 0 2006.201.05:40:40.39#ibcon#wrote, iclass 30, count 0 2006.201.05:40:40.39#ibcon#about to read 3, iclass 30, count 0 2006.201.05:40:40.41#ibcon#read 3, iclass 30, count 0 2006.201.05:40:40.41#ibcon#about to read 4, iclass 30, count 0 2006.201.05:40:40.41#ibcon#read 4, iclass 30, count 0 2006.201.05:40:40.41#ibcon#about to read 5, iclass 30, count 0 2006.201.05:40:40.41#ibcon#read 5, iclass 30, count 0 2006.201.05:40:40.41#ibcon#about to read 6, iclass 30, count 0 2006.201.05:40:40.41#ibcon#read 6, iclass 30, count 0 2006.201.05:40:40.41#ibcon#end of sib2, iclass 30, count 0 2006.201.05:40:40.41#ibcon#*mode == 0, iclass 30, count 0 2006.201.05:40:40.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.05:40:40.41#ibcon#[27=USB\r\n] 2006.201.05:40:40.41#ibcon#*before write, iclass 30, count 0 2006.201.05:40:40.41#ibcon#enter sib2, iclass 30, count 0 2006.201.05:40:40.41#ibcon#flushed, iclass 30, count 0 2006.201.05:40:40.41#ibcon#about to write, iclass 30, count 0 2006.201.05:40:40.41#ibcon#wrote, iclass 30, count 0 2006.201.05:40:40.41#ibcon#about to read 3, iclass 30, count 0 2006.201.05:40:40.44#ibcon#read 3, iclass 30, count 0 2006.201.05:40:40.44#ibcon#about to read 4, iclass 30, count 0 2006.201.05:40:40.44#ibcon#read 4, iclass 30, count 0 2006.201.05:40:40.44#ibcon#about to read 5, iclass 30, count 0 2006.201.05:40:40.44#ibcon#read 5, iclass 30, count 0 2006.201.05:40:40.44#ibcon#about to read 6, iclass 30, count 0 2006.201.05:40:40.44#ibcon#read 6, iclass 30, count 0 2006.201.05:40:40.44#ibcon#end of sib2, iclass 30, count 0 2006.201.05:40:40.44#ibcon#*after write, iclass 30, count 0 2006.201.05:40:40.44#ibcon#*before return 0, iclass 30, count 0 2006.201.05:40:40.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:40:40.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.05:40:40.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.05:40:40.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.05:40:40.44$vck44/vblo=2,634.99 2006.201.05:40:40.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.05:40:40.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.05:40:40.44#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:40.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:40.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:40.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:40.44#ibcon#enter wrdev, iclass 32, count 0 2006.201.05:40:40.44#ibcon#first serial, iclass 32, count 0 2006.201.05:40:40.44#ibcon#enter sib2, iclass 32, count 0 2006.201.05:40:40.44#ibcon#flushed, iclass 32, count 0 2006.201.05:40:40.44#ibcon#about to write, iclass 32, count 0 2006.201.05:40:40.44#ibcon#wrote, iclass 32, count 0 2006.201.05:40:40.44#ibcon#about to read 3, iclass 32, count 0 2006.201.05:40:40.46#ibcon#read 3, iclass 32, count 0 2006.201.05:40:40.46#ibcon#about to read 4, iclass 32, count 0 2006.201.05:40:40.46#ibcon#read 4, iclass 32, count 0 2006.201.05:40:40.46#ibcon#about to read 5, iclass 32, count 0 2006.201.05:40:40.46#ibcon#read 5, iclass 32, count 0 2006.201.05:40:40.46#ibcon#about to read 6, iclass 32, count 0 2006.201.05:40:40.46#ibcon#read 6, iclass 32, count 0 2006.201.05:40:40.46#ibcon#end of sib2, iclass 32, count 0 2006.201.05:40:40.46#ibcon#*mode == 0, iclass 32, count 0 2006.201.05:40:40.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.05:40:40.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:40:40.46#ibcon#*before write, iclass 32, count 0 2006.201.05:40:40.46#ibcon#enter sib2, iclass 32, count 0 2006.201.05:40:40.46#ibcon#flushed, iclass 32, count 0 2006.201.05:40:40.46#ibcon#about to write, iclass 32, count 0 2006.201.05:40:40.71#ibcon#wrote, iclass 32, count 0 2006.201.05:40:40.71#ibcon#about to read 3, iclass 32, count 0 2006.201.05:40:40.76#ibcon#read 3, iclass 32, count 0 2006.201.05:40:40.76#ibcon#about to read 4, iclass 32, count 0 2006.201.05:40:40.76#ibcon#read 4, iclass 32, count 0 2006.201.05:40:40.76#ibcon#about to read 5, iclass 32, count 0 2006.201.05:40:40.76#ibcon#read 5, iclass 32, count 0 2006.201.05:40:40.76#ibcon#about to read 6, iclass 32, count 0 2006.201.05:40:40.76#ibcon#read 6, iclass 32, count 0 2006.201.05:40:40.76#ibcon#end of sib2, iclass 32, count 0 2006.201.05:40:40.76#ibcon#*after write, iclass 32, count 0 2006.201.05:40:40.76#ibcon#*before return 0, iclass 32, count 0 2006.201.05:40:40.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:40.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.05:40:40.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.05:40:40.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.05:40:40.76$vck44/vb=2,5 2006.201.05:40:40.76#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.05:40:40.76#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.05:40:40.76#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:40.76#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:40.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:40.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:40.76#ibcon#enter wrdev, iclass 34, count 2 2006.201.05:40:40.76#ibcon#first serial, iclass 34, count 2 2006.201.05:40:40.76#ibcon#enter sib2, iclass 34, count 2 2006.201.05:40:40.76#ibcon#flushed, iclass 34, count 2 2006.201.05:40:40.76#ibcon#about to write, iclass 34, count 2 2006.201.05:40:40.76#ibcon#wrote, iclass 34, count 2 2006.201.05:40:40.76#ibcon#about to read 3, iclass 34, count 2 2006.201.05:40:40.78#ibcon#read 3, iclass 34, count 2 2006.201.05:40:40.78#ibcon#about to read 4, iclass 34, count 2 2006.201.05:40:40.78#ibcon#read 4, iclass 34, count 2 2006.201.05:40:40.78#ibcon#about to read 5, iclass 34, count 2 2006.201.05:40:40.78#ibcon#read 5, iclass 34, count 2 2006.201.05:40:40.78#ibcon#about to read 6, iclass 34, count 2 2006.201.05:40:40.78#ibcon#read 6, iclass 34, count 2 2006.201.05:40:40.78#ibcon#end of sib2, iclass 34, count 2 2006.201.05:40:40.78#ibcon#*mode == 0, iclass 34, count 2 2006.201.05:40:40.78#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.05:40:40.78#ibcon#[27=AT02-05\r\n] 2006.201.05:40:40.78#ibcon#*before write, iclass 34, count 2 2006.201.05:40:40.78#ibcon#enter sib2, iclass 34, count 2 2006.201.05:40:40.78#ibcon#flushed, iclass 34, count 2 2006.201.05:40:40.78#ibcon#about to write, iclass 34, count 2 2006.201.05:40:40.78#ibcon#wrote, iclass 34, count 2 2006.201.05:40:40.78#ibcon#about to read 3, iclass 34, count 2 2006.201.05:40:40.81#ibcon#read 3, iclass 34, count 2 2006.201.05:40:40.81#ibcon#about to read 4, iclass 34, count 2 2006.201.05:40:40.81#ibcon#read 4, iclass 34, count 2 2006.201.05:40:40.81#ibcon#about to read 5, iclass 34, count 2 2006.201.05:40:40.81#ibcon#read 5, iclass 34, count 2 2006.201.05:40:40.81#ibcon#about to read 6, iclass 34, count 2 2006.201.05:40:40.81#ibcon#read 6, iclass 34, count 2 2006.201.05:40:40.81#ibcon#end of sib2, iclass 34, count 2 2006.201.05:40:40.81#ibcon#*after write, iclass 34, count 2 2006.201.05:40:40.81#ibcon#*before return 0, iclass 34, count 2 2006.201.05:40:40.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:40.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.05:40:40.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.05:40:40.81#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:40.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:40.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:40.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:40.93#ibcon#enter wrdev, iclass 34, count 0 2006.201.05:40:40.93#ibcon#first serial, iclass 34, count 0 2006.201.05:40:40.93#ibcon#enter sib2, iclass 34, count 0 2006.201.05:40:40.93#ibcon#flushed, iclass 34, count 0 2006.201.05:40:40.93#ibcon#about to write, iclass 34, count 0 2006.201.05:40:40.93#ibcon#wrote, iclass 34, count 0 2006.201.05:40:40.93#ibcon#about to read 3, iclass 34, count 0 2006.201.05:40:40.95#ibcon#read 3, iclass 34, count 0 2006.201.05:40:40.95#ibcon#about to read 4, iclass 34, count 0 2006.201.05:40:40.95#ibcon#read 4, iclass 34, count 0 2006.201.05:40:40.95#ibcon#about to read 5, iclass 34, count 0 2006.201.05:40:40.95#ibcon#read 5, iclass 34, count 0 2006.201.05:40:40.95#ibcon#about to read 6, iclass 34, count 0 2006.201.05:40:40.95#ibcon#read 6, iclass 34, count 0 2006.201.05:40:40.95#ibcon#end of sib2, iclass 34, count 0 2006.201.05:40:40.95#ibcon#*mode == 0, iclass 34, count 0 2006.201.05:40:40.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.05:40:40.95#ibcon#[27=USB\r\n] 2006.201.05:40:40.95#ibcon#*before write, iclass 34, count 0 2006.201.05:40:40.95#ibcon#enter sib2, iclass 34, count 0 2006.201.05:40:40.95#ibcon#flushed, iclass 34, count 0 2006.201.05:40:40.95#ibcon#about to write, iclass 34, count 0 2006.201.05:40:40.95#ibcon#wrote, iclass 34, count 0 2006.201.05:40:40.95#ibcon#about to read 3, iclass 34, count 0 2006.201.05:40:40.98#ibcon#read 3, iclass 34, count 0 2006.201.05:40:40.98#ibcon#about to read 4, iclass 34, count 0 2006.201.05:40:40.98#ibcon#read 4, iclass 34, count 0 2006.201.05:40:40.98#ibcon#about to read 5, iclass 34, count 0 2006.201.05:40:40.98#ibcon#read 5, iclass 34, count 0 2006.201.05:40:40.98#ibcon#about to read 6, iclass 34, count 0 2006.201.05:40:40.98#ibcon#read 6, iclass 34, count 0 2006.201.05:40:40.98#ibcon#end of sib2, iclass 34, count 0 2006.201.05:40:40.98#ibcon#*after write, iclass 34, count 0 2006.201.05:40:40.98#ibcon#*before return 0, iclass 34, count 0 2006.201.05:40:40.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:40.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.05:40:40.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.05:40:40.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.05:40:40.98$vck44/vblo=3,649.99 2006.201.05:40:40.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.05:40:40.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.05:40:40.98#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:40.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:40.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:40.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:40.98#ibcon#enter wrdev, iclass 36, count 0 2006.201.05:40:40.98#ibcon#first serial, iclass 36, count 0 2006.201.05:40:40.98#ibcon#enter sib2, iclass 36, count 0 2006.201.05:40:40.98#ibcon#flushed, iclass 36, count 0 2006.201.05:40:40.98#ibcon#about to write, iclass 36, count 0 2006.201.05:40:40.98#ibcon#wrote, iclass 36, count 0 2006.201.05:40:40.98#ibcon#about to read 3, iclass 36, count 0 2006.201.05:40:41.00#ibcon#read 3, iclass 36, count 0 2006.201.05:40:41.00#ibcon#about to read 4, iclass 36, count 0 2006.201.05:40:41.00#ibcon#read 4, iclass 36, count 0 2006.201.05:40:41.00#ibcon#about to read 5, iclass 36, count 0 2006.201.05:40:41.00#ibcon#read 5, iclass 36, count 0 2006.201.05:40:41.00#ibcon#about to read 6, iclass 36, count 0 2006.201.05:40:41.00#ibcon#read 6, iclass 36, count 0 2006.201.05:40:41.00#ibcon#end of sib2, iclass 36, count 0 2006.201.05:40:41.00#ibcon#*mode == 0, iclass 36, count 0 2006.201.05:40:41.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.05:40:41.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:40:41.00#ibcon#*before write, iclass 36, count 0 2006.201.05:40:41.00#ibcon#enter sib2, iclass 36, count 0 2006.201.05:40:41.00#ibcon#flushed, iclass 36, count 0 2006.201.05:40:41.00#ibcon#about to write, iclass 36, count 0 2006.201.05:40:41.00#ibcon#wrote, iclass 36, count 0 2006.201.05:40:41.00#ibcon#about to read 3, iclass 36, count 0 2006.201.05:40:41.04#ibcon#read 3, iclass 36, count 0 2006.201.05:40:41.04#ibcon#about to read 4, iclass 36, count 0 2006.201.05:40:41.04#ibcon#read 4, iclass 36, count 0 2006.201.05:40:41.04#ibcon#about to read 5, iclass 36, count 0 2006.201.05:40:41.04#ibcon#read 5, iclass 36, count 0 2006.201.05:40:41.04#ibcon#about to read 6, iclass 36, count 0 2006.201.05:40:41.04#ibcon#read 6, iclass 36, count 0 2006.201.05:40:41.04#ibcon#end of sib2, iclass 36, count 0 2006.201.05:40:41.04#ibcon#*after write, iclass 36, count 0 2006.201.05:40:41.04#ibcon#*before return 0, iclass 36, count 0 2006.201.05:40:41.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:41.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.05:40:41.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.05:40:41.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.05:40:41.04$vck44/vb=3,4 2006.201.05:40:41.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.05:40:41.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.05:40:41.04#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:41.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:41.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:41.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:41.10#ibcon#enter wrdev, iclass 38, count 2 2006.201.05:40:41.10#ibcon#first serial, iclass 38, count 2 2006.201.05:40:41.10#ibcon#enter sib2, iclass 38, count 2 2006.201.05:40:41.10#ibcon#flushed, iclass 38, count 2 2006.201.05:40:41.10#ibcon#about to write, iclass 38, count 2 2006.201.05:40:41.10#ibcon#wrote, iclass 38, count 2 2006.201.05:40:41.10#ibcon#about to read 3, iclass 38, count 2 2006.201.05:40:41.12#ibcon#read 3, iclass 38, count 2 2006.201.05:40:41.12#ibcon#about to read 4, iclass 38, count 2 2006.201.05:40:41.12#ibcon#read 4, iclass 38, count 2 2006.201.05:40:41.12#ibcon#about to read 5, iclass 38, count 2 2006.201.05:40:41.12#ibcon#read 5, iclass 38, count 2 2006.201.05:40:41.12#ibcon#about to read 6, iclass 38, count 2 2006.201.05:40:41.12#ibcon#read 6, iclass 38, count 2 2006.201.05:40:41.12#ibcon#end of sib2, iclass 38, count 2 2006.201.05:40:41.12#ibcon#*mode == 0, iclass 38, count 2 2006.201.05:40:41.12#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.05:40:41.12#ibcon#[27=AT03-04\r\n] 2006.201.05:40:41.12#ibcon#*before write, iclass 38, count 2 2006.201.05:40:41.12#ibcon#enter sib2, iclass 38, count 2 2006.201.05:40:41.12#ibcon#flushed, iclass 38, count 2 2006.201.05:40:41.12#ibcon#about to write, iclass 38, count 2 2006.201.05:40:41.12#ibcon#wrote, iclass 38, count 2 2006.201.05:40:41.12#ibcon#about to read 3, iclass 38, count 2 2006.201.05:40:41.15#ibcon#read 3, iclass 38, count 2 2006.201.05:40:41.15#ibcon#about to read 4, iclass 38, count 2 2006.201.05:40:41.15#ibcon#read 4, iclass 38, count 2 2006.201.05:40:41.15#ibcon#about to read 5, iclass 38, count 2 2006.201.05:40:41.15#ibcon#read 5, iclass 38, count 2 2006.201.05:40:41.15#ibcon#about to read 6, iclass 38, count 2 2006.201.05:40:41.15#ibcon#read 6, iclass 38, count 2 2006.201.05:40:41.15#ibcon#end of sib2, iclass 38, count 2 2006.201.05:40:41.15#ibcon#*after write, iclass 38, count 2 2006.201.05:40:41.15#ibcon#*before return 0, iclass 38, count 2 2006.201.05:40:41.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:41.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.05:40:41.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.05:40:41.15#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:41.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:41.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:41.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:41.27#ibcon#enter wrdev, iclass 38, count 0 2006.201.05:40:41.27#ibcon#first serial, iclass 38, count 0 2006.201.05:40:41.27#ibcon#enter sib2, iclass 38, count 0 2006.201.05:40:41.27#ibcon#flushed, iclass 38, count 0 2006.201.05:40:41.27#ibcon#about to write, iclass 38, count 0 2006.201.05:40:41.27#ibcon#wrote, iclass 38, count 0 2006.201.05:40:41.27#ibcon#about to read 3, iclass 38, count 0 2006.201.05:40:41.29#ibcon#read 3, iclass 38, count 0 2006.201.05:40:41.29#ibcon#about to read 4, iclass 38, count 0 2006.201.05:40:41.29#ibcon#read 4, iclass 38, count 0 2006.201.05:40:41.29#ibcon#about to read 5, iclass 38, count 0 2006.201.05:40:41.29#ibcon#read 5, iclass 38, count 0 2006.201.05:40:41.29#ibcon#about to read 6, iclass 38, count 0 2006.201.05:40:41.29#ibcon#read 6, iclass 38, count 0 2006.201.05:40:41.29#ibcon#end of sib2, iclass 38, count 0 2006.201.05:40:41.29#ibcon#*mode == 0, iclass 38, count 0 2006.201.05:40:41.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.05:40:41.29#ibcon#[27=USB\r\n] 2006.201.05:40:41.29#ibcon#*before write, iclass 38, count 0 2006.201.05:40:41.29#ibcon#enter sib2, iclass 38, count 0 2006.201.05:40:41.29#ibcon#flushed, iclass 38, count 0 2006.201.05:40:41.29#ibcon#about to write, iclass 38, count 0 2006.201.05:40:41.29#ibcon#wrote, iclass 38, count 0 2006.201.05:40:41.29#ibcon#about to read 3, iclass 38, count 0 2006.201.05:40:41.32#ibcon#read 3, iclass 38, count 0 2006.201.05:40:41.32#ibcon#about to read 4, iclass 38, count 0 2006.201.05:40:41.32#ibcon#read 4, iclass 38, count 0 2006.201.05:40:41.32#ibcon#about to read 5, iclass 38, count 0 2006.201.05:40:41.32#ibcon#read 5, iclass 38, count 0 2006.201.05:40:41.32#ibcon#about to read 6, iclass 38, count 0 2006.201.05:40:41.32#ibcon#read 6, iclass 38, count 0 2006.201.05:40:41.32#ibcon#end of sib2, iclass 38, count 0 2006.201.05:40:41.32#ibcon#*after write, iclass 38, count 0 2006.201.05:40:41.32#ibcon#*before return 0, iclass 38, count 0 2006.201.05:40:41.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:41.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.05:40:41.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.05:40:41.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.05:40:41.32$vck44/vblo=4,679.99 2006.201.05:40:41.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.05:40:41.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.05:40:41.32#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:41.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:41.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:41.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:41.32#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:40:41.32#ibcon#first serial, iclass 40, count 0 2006.201.05:40:41.32#ibcon#enter sib2, iclass 40, count 0 2006.201.05:40:41.32#ibcon#flushed, iclass 40, count 0 2006.201.05:40:41.32#ibcon#about to write, iclass 40, count 0 2006.201.05:40:41.32#ibcon#wrote, iclass 40, count 0 2006.201.05:40:41.32#ibcon#about to read 3, iclass 40, count 0 2006.201.05:40:41.34#ibcon#read 3, iclass 40, count 0 2006.201.05:40:41.34#ibcon#about to read 4, iclass 40, count 0 2006.201.05:40:41.34#ibcon#read 4, iclass 40, count 0 2006.201.05:40:41.34#ibcon#about to read 5, iclass 40, count 0 2006.201.05:40:41.34#ibcon#read 5, iclass 40, count 0 2006.201.05:40:41.34#ibcon#about to read 6, iclass 40, count 0 2006.201.05:40:41.34#ibcon#read 6, iclass 40, count 0 2006.201.05:40:41.34#ibcon#end of sib2, iclass 40, count 0 2006.201.05:40:41.34#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:40:41.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:40:41.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:40:41.34#ibcon#*before write, iclass 40, count 0 2006.201.05:40:41.34#ibcon#enter sib2, iclass 40, count 0 2006.201.05:40:41.34#ibcon#flushed, iclass 40, count 0 2006.201.05:40:41.34#ibcon#about to write, iclass 40, count 0 2006.201.05:40:41.34#ibcon#wrote, iclass 40, count 0 2006.201.05:40:41.34#ibcon#about to read 3, iclass 40, count 0 2006.201.05:40:41.38#ibcon#read 3, iclass 40, count 0 2006.201.05:40:41.38#ibcon#about to read 4, iclass 40, count 0 2006.201.05:40:41.38#ibcon#read 4, iclass 40, count 0 2006.201.05:40:41.38#ibcon#about to read 5, iclass 40, count 0 2006.201.05:40:41.38#ibcon#read 5, iclass 40, count 0 2006.201.05:40:41.38#ibcon#about to read 6, iclass 40, count 0 2006.201.05:40:41.38#ibcon#read 6, iclass 40, count 0 2006.201.05:40:41.38#ibcon#end of sib2, iclass 40, count 0 2006.201.05:40:41.38#ibcon#*after write, iclass 40, count 0 2006.201.05:40:41.38#ibcon#*before return 0, iclass 40, count 0 2006.201.05:40:41.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:41.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:40:41.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:40:41.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:40:41.38$vck44/vb=4,5 2006.201.05:40:41.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.05:40:41.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.05:40:41.38#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:41.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:41.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:41.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:41.44#ibcon#enter wrdev, iclass 4, count 2 2006.201.05:40:41.44#ibcon#first serial, iclass 4, count 2 2006.201.05:40:41.44#ibcon#enter sib2, iclass 4, count 2 2006.201.05:40:41.44#ibcon#flushed, iclass 4, count 2 2006.201.05:40:41.44#ibcon#about to write, iclass 4, count 2 2006.201.05:40:41.44#ibcon#wrote, iclass 4, count 2 2006.201.05:40:41.44#ibcon#about to read 3, iclass 4, count 2 2006.201.05:40:41.46#ibcon#read 3, iclass 4, count 2 2006.201.05:40:41.46#ibcon#about to read 4, iclass 4, count 2 2006.201.05:40:41.46#ibcon#read 4, iclass 4, count 2 2006.201.05:40:41.46#ibcon#about to read 5, iclass 4, count 2 2006.201.05:40:41.46#ibcon#read 5, iclass 4, count 2 2006.201.05:40:41.46#ibcon#about to read 6, iclass 4, count 2 2006.201.05:40:41.46#ibcon#read 6, iclass 4, count 2 2006.201.05:40:41.46#ibcon#end of sib2, iclass 4, count 2 2006.201.05:40:41.46#ibcon#*mode == 0, iclass 4, count 2 2006.201.05:40:41.46#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.05:40:41.46#ibcon#[27=AT04-05\r\n] 2006.201.05:40:41.46#ibcon#*before write, iclass 4, count 2 2006.201.05:40:41.46#ibcon#enter sib2, iclass 4, count 2 2006.201.05:40:41.46#ibcon#flushed, iclass 4, count 2 2006.201.05:40:41.46#ibcon#about to write, iclass 4, count 2 2006.201.05:40:41.46#ibcon#wrote, iclass 4, count 2 2006.201.05:40:41.46#ibcon#about to read 3, iclass 4, count 2 2006.201.05:40:41.49#ibcon#read 3, iclass 4, count 2 2006.201.05:40:41.49#ibcon#about to read 4, iclass 4, count 2 2006.201.05:40:41.49#ibcon#read 4, iclass 4, count 2 2006.201.05:40:41.49#ibcon#about to read 5, iclass 4, count 2 2006.201.05:40:41.49#ibcon#read 5, iclass 4, count 2 2006.201.05:40:41.49#ibcon#about to read 6, iclass 4, count 2 2006.201.05:40:41.49#ibcon#read 6, iclass 4, count 2 2006.201.05:40:41.49#ibcon#end of sib2, iclass 4, count 2 2006.201.05:40:41.49#ibcon#*after write, iclass 4, count 2 2006.201.05:40:41.49#ibcon#*before return 0, iclass 4, count 2 2006.201.05:40:41.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:41.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.05:40:41.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.05:40:41.49#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:41.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:41.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:41.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:41.61#ibcon#enter wrdev, iclass 4, count 0 2006.201.05:40:41.61#ibcon#first serial, iclass 4, count 0 2006.201.05:40:41.61#ibcon#enter sib2, iclass 4, count 0 2006.201.05:40:41.61#ibcon#flushed, iclass 4, count 0 2006.201.05:40:41.61#ibcon#about to write, iclass 4, count 0 2006.201.05:40:41.61#ibcon#wrote, iclass 4, count 0 2006.201.05:40:41.61#ibcon#about to read 3, iclass 4, count 0 2006.201.05:40:41.63#ibcon#read 3, iclass 4, count 0 2006.201.05:40:41.63#ibcon#about to read 4, iclass 4, count 0 2006.201.05:40:41.63#ibcon#read 4, iclass 4, count 0 2006.201.05:40:41.63#ibcon#about to read 5, iclass 4, count 0 2006.201.05:40:41.63#ibcon#read 5, iclass 4, count 0 2006.201.05:40:41.63#ibcon#about to read 6, iclass 4, count 0 2006.201.05:40:41.63#ibcon#read 6, iclass 4, count 0 2006.201.05:40:41.63#ibcon#end of sib2, iclass 4, count 0 2006.201.05:40:41.63#ibcon#*mode == 0, iclass 4, count 0 2006.201.05:40:41.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.05:40:41.63#ibcon#[27=USB\r\n] 2006.201.05:40:41.63#ibcon#*before write, iclass 4, count 0 2006.201.05:40:41.63#ibcon#enter sib2, iclass 4, count 0 2006.201.05:40:41.63#ibcon#flushed, iclass 4, count 0 2006.201.05:40:41.63#ibcon#about to write, iclass 4, count 0 2006.201.05:40:41.63#ibcon#wrote, iclass 4, count 0 2006.201.05:40:41.63#ibcon#about to read 3, iclass 4, count 0 2006.201.05:40:41.66#ibcon#read 3, iclass 4, count 0 2006.201.05:40:41.66#ibcon#about to read 4, iclass 4, count 0 2006.201.05:40:41.66#ibcon#read 4, iclass 4, count 0 2006.201.05:40:41.66#ibcon#about to read 5, iclass 4, count 0 2006.201.05:40:41.66#ibcon#read 5, iclass 4, count 0 2006.201.05:40:41.66#ibcon#about to read 6, iclass 4, count 0 2006.201.05:40:41.66#ibcon#read 6, iclass 4, count 0 2006.201.05:40:41.66#ibcon#end of sib2, iclass 4, count 0 2006.201.05:40:41.66#ibcon#*after write, iclass 4, count 0 2006.201.05:40:41.66#ibcon#*before return 0, iclass 4, count 0 2006.201.05:40:41.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:41.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.05:40:41.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.05:40:41.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.05:40:41.66$vck44/vblo=5,709.99 2006.201.05:40:41.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.05:40:41.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.05:40:41.66#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:41.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:41.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:41.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:41.66#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:40:41.66#ibcon#first serial, iclass 6, count 0 2006.201.05:40:41.66#ibcon#enter sib2, iclass 6, count 0 2006.201.05:40:41.66#ibcon#flushed, iclass 6, count 0 2006.201.05:40:41.66#ibcon#about to write, iclass 6, count 0 2006.201.05:40:41.66#ibcon#wrote, iclass 6, count 0 2006.201.05:40:41.66#ibcon#about to read 3, iclass 6, count 0 2006.201.05:40:41.68#ibcon#read 3, iclass 6, count 0 2006.201.05:40:41.68#ibcon#about to read 4, iclass 6, count 0 2006.201.05:40:41.68#ibcon#read 4, iclass 6, count 0 2006.201.05:40:41.68#ibcon#about to read 5, iclass 6, count 0 2006.201.05:40:41.68#ibcon#read 5, iclass 6, count 0 2006.201.05:40:41.68#ibcon#about to read 6, iclass 6, count 0 2006.201.05:40:41.68#ibcon#read 6, iclass 6, count 0 2006.201.05:40:41.68#ibcon#end of sib2, iclass 6, count 0 2006.201.05:40:41.68#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:40:41.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:40:41.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:40:41.68#ibcon#*before write, iclass 6, count 0 2006.201.05:40:41.68#ibcon#enter sib2, iclass 6, count 0 2006.201.05:40:41.68#ibcon#flushed, iclass 6, count 0 2006.201.05:40:41.68#ibcon#about to write, iclass 6, count 0 2006.201.05:40:41.68#ibcon#wrote, iclass 6, count 0 2006.201.05:40:41.68#ibcon#about to read 3, iclass 6, count 0 2006.201.05:40:41.72#ibcon#read 3, iclass 6, count 0 2006.201.05:40:41.72#ibcon#about to read 4, iclass 6, count 0 2006.201.05:40:41.72#ibcon#read 4, iclass 6, count 0 2006.201.05:40:41.72#ibcon#about to read 5, iclass 6, count 0 2006.201.05:40:41.72#ibcon#read 5, iclass 6, count 0 2006.201.05:40:41.72#ibcon#about to read 6, iclass 6, count 0 2006.201.05:40:41.72#ibcon#read 6, iclass 6, count 0 2006.201.05:40:41.72#ibcon#end of sib2, iclass 6, count 0 2006.201.05:40:41.72#ibcon#*after write, iclass 6, count 0 2006.201.05:40:41.72#ibcon#*before return 0, iclass 6, count 0 2006.201.05:40:41.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:41.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.05:40:41.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:40:41.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:40:41.72$vck44/vb=5,4 2006.201.05:40:41.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.05:40:41.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.05:40:41.72#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:41.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:41.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:41.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:41.78#ibcon#enter wrdev, iclass 10, count 2 2006.201.05:40:41.78#ibcon#first serial, iclass 10, count 2 2006.201.05:40:41.78#ibcon#enter sib2, iclass 10, count 2 2006.201.05:40:41.78#ibcon#flushed, iclass 10, count 2 2006.201.05:40:41.78#ibcon#about to write, iclass 10, count 2 2006.201.05:40:41.78#ibcon#wrote, iclass 10, count 2 2006.201.05:40:41.78#ibcon#about to read 3, iclass 10, count 2 2006.201.05:40:41.80#ibcon#read 3, iclass 10, count 2 2006.201.05:40:41.80#ibcon#about to read 4, iclass 10, count 2 2006.201.05:40:41.80#ibcon#read 4, iclass 10, count 2 2006.201.05:40:41.80#ibcon#about to read 5, iclass 10, count 2 2006.201.05:40:41.80#ibcon#read 5, iclass 10, count 2 2006.201.05:40:41.80#ibcon#about to read 6, iclass 10, count 2 2006.201.05:40:41.82#ibcon#read 6, iclass 10, count 2 2006.201.05:40:41.82#ibcon#end of sib2, iclass 10, count 2 2006.201.05:40:41.82#ibcon#*mode == 0, iclass 10, count 2 2006.201.05:40:41.82#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.05:40:41.82#ibcon#[27=AT05-04\r\n] 2006.201.05:40:41.82#ibcon#*before write, iclass 10, count 2 2006.201.05:40:41.82#ibcon#enter sib2, iclass 10, count 2 2006.201.05:40:41.82#ibcon#flushed, iclass 10, count 2 2006.201.05:40:41.82#ibcon#about to write, iclass 10, count 2 2006.201.05:40:41.82#ibcon#wrote, iclass 10, count 2 2006.201.05:40:41.82#ibcon#about to read 3, iclass 10, count 2 2006.201.05:40:41.86#ibcon#read 3, iclass 10, count 2 2006.201.05:40:41.86#ibcon#about to read 4, iclass 10, count 2 2006.201.05:40:41.86#ibcon#read 4, iclass 10, count 2 2006.201.05:40:41.86#ibcon#about to read 5, iclass 10, count 2 2006.201.05:40:41.86#ibcon#read 5, iclass 10, count 2 2006.201.05:40:41.86#ibcon#about to read 6, iclass 10, count 2 2006.201.05:40:41.86#ibcon#read 6, iclass 10, count 2 2006.201.05:40:41.86#ibcon#end of sib2, iclass 10, count 2 2006.201.05:40:41.86#ibcon#*after write, iclass 10, count 2 2006.201.05:40:41.86#ibcon#*before return 0, iclass 10, count 2 2006.201.05:40:41.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:41.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.05:40:41.86#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.05:40:41.86#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:41.86#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:41.98#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:41.98#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:41.98#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:40:41.98#ibcon#first serial, iclass 10, count 0 2006.201.05:40:41.98#ibcon#enter sib2, iclass 10, count 0 2006.201.05:40:41.98#ibcon#flushed, iclass 10, count 0 2006.201.05:40:41.98#ibcon#about to write, iclass 10, count 0 2006.201.05:40:41.98#ibcon#wrote, iclass 10, count 0 2006.201.05:40:41.98#ibcon#about to read 3, iclass 10, count 0 2006.201.05:40:42.00#ibcon#read 3, iclass 10, count 0 2006.201.05:40:42.00#ibcon#about to read 4, iclass 10, count 0 2006.201.05:40:42.00#ibcon#read 4, iclass 10, count 0 2006.201.05:40:42.00#ibcon#about to read 5, iclass 10, count 0 2006.201.05:40:42.00#ibcon#read 5, iclass 10, count 0 2006.201.05:40:42.00#ibcon#about to read 6, iclass 10, count 0 2006.201.05:40:42.00#ibcon#read 6, iclass 10, count 0 2006.201.05:40:42.00#ibcon#end of sib2, iclass 10, count 0 2006.201.05:40:42.00#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:40:42.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:40:42.00#ibcon#[27=USB\r\n] 2006.201.05:40:42.00#ibcon#*before write, iclass 10, count 0 2006.201.05:40:42.00#ibcon#enter sib2, iclass 10, count 0 2006.201.05:40:42.00#ibcon#flushed, iclass 10, count 0 2006.201.05:40:42.00#ibcon#about to write, iclass 10, count 0 2006.201.05:40:42.00#ibcon#wrote, iclass 10, count 0 2006.201.05:40:42.00#ibcon#about to read 3, iclass 10, count 0 2006.201.05:40:42.03#ibcon#read 3, iclass 10, count 0 2006.201.05:40:42.03#ibcon#about to read 4, iclass 10, count 0 2006.201.05:40:42.03#ibcon#read 4, iclass 10, count 0 2006.201.05:40:42.03#ibcon#about to read 5, iclass 10, count 0 2006.201.05:40:42.03#ibcon#read 5, iclass 10, count 0 2006.201.05:40:42.03#ibcon#about to read 6, iclass 10, count 0 2006.201.05:40:42.03#ibcon#read 6, iclass 10, count 0 2006.201.05:40:42.03#ibcon#end of sib2, iclass 10, count 0 2006.201.05:40:42.03#ibcon#*after write, iclass 10, count 0 2006.201.05:40:42.03#ibcon#*before return 0, iclass 10, count 0 2006.201.05:40:42.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:42.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.05:40:42.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:40:42.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:40:42.03$vck44/vblo=6,719.99 2006.201.05:40:42.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.05:40:42.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.05:40:42.03#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:42.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:42.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:42.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:42.03#ibcon#enter wrdev, iclass 12, count 0 2006.201.05:40:42.03#ibcon#first serial, iclass 12, count 0 2006.201.05:40:42.03#ibcon#enter sib2, iclass 12, count 0 2006.201.05:40:42.03#ibcon#flushed, iclass 12, count 0 2006.201.05:40:42.03#ibcon#about to write, iclass 12, count 0 2006.201.05:40:42.03#ibcon#wrote, iclass 12, count 0 2006.201.05:40:42.03#ibcon#about to read 3, iclass 12, count 0 2006.201.05:40:42.05#ibcon#read 3, iclass 12, count 0 2006.201.05:40:42.05#ibcon#about to read 4, iclass 12, count 0 2006.201.05:40:42.05#ibcon#read 4, iclass 12, count 0 2006.201.05:40:42.05#ibcon#about to read 5, iclass 12, count 0 2006.201.05:40:42.05#ibcon#read 5, iclass 12, count 0 2006.201.05:40:42.05#ibcon#about to read 6, iclass 12, count 0 2006.201.05:40:42.05#ibcon#read 6, iclass 12, count 0 2006.201.05:40:42.05#ibcon#end of sib2, iclass 12, count 0 2006.201.05:40:42.05#ibcon#*mode == 0, iclass 12, count 0 2006.201.05:40:42.05#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.05:40:42.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:40:42.05#ibcon#*before write, iclass 12, count 0 2006.201.05:40:42.05#ibcon#enter sib2, iclass 12, count 0 2006.201.05:40:42.05#ibcon#flushed, iclass 12, count 0 2006.201.05:40:42.05#ibcon#about to write, iclass 12, count 0 2006.201.05:40:42.05#ibcon#wrote, iclass 12, count 0 2006.201.05:40:42.05#ibcon#about to read 3, iclass 12, count 0 2006.201.05:40:42.09#ibcon#read 3, iclass 12, count 0 2006.201.05:40:42.09#ibcon#about to read 4, iclass 12, count 0 2006.201.05:40:42.09#ibcon#read 4, iclass 12, count 0 2006.201.05:40:42.09#ibcon#about to read 5, iclass 12, count 0 2006.201.05:40:42.09#ibcon#read 5, iclass 12, count 0 2006.201.05:40:42.09#ibcon#about to read 6, iclass 12, count 0 2006.201.05:40:42.09#ibcon#read 6, iclass 12, count 0 2006.201.05:40:42.09#ibcon#end of sib2, iclass 12, count 0 2006.201.05:40:42.09#ibcon#*after write, iclass 12, count 0 2006.201.05:40:42.09#ibcon#*before return 0, iclass 12, count 0 2006.201.05:40:42.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:42.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.05:40:42.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.05:40:42.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.05:40:42.09$vck44/vb=6,4 2006.201.05:40:42.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.05:40:42.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.05:40:42.09#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:42.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:42.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:42.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:42.15#ibcon#enter wrdev, iclass 14, count 2 2006.201.05:40:42.15#ibcon#first serial, iclass 14, count 2 2006.201.05:40:42.15#ibcon#enter sib2, iclass 14, count 2 2006.201.05:40:42.15#ibcon#flushed, iclass 14, count 2 2006.201.05:40:42.15#ibcon#about to write, iclass 14, count 2 2006.201.05:40:42.15#ibcon#wrote, iclass 14, count 2 2006.201.05:40:42.15#ibcon#about to read 3, iclass 14, count 2 2006.201.05:40:42.17#ibcon#read 3, iclass 14, count 2 2006.201.05:40:42.17#ibcon#about to read 4, iclass 14, count 2 2006.201.05:40:42.17#ibcon#read 4, iclass 14, count 2 2006.201.05:40:42.17#ibcon#about to read 5, iclass 14, count 2 2006.201.05:40:42.17#ibcon#read 5, iclass 14, count 2 2006.201.05:40:42.17#ibcon#about to read 6, iclass 14, count 2 2006.201.05:40:42.17#ibcon#read 6, iclass 14, count 2 2006.201.05:40:42.17#ibcon#end of sib2, iclass 14, count 2 2006.201.05:40:42.17#ibcon#*mode == 0, iclass 14, count 2 2006.201.05:40:42.17#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.05:40:42.17#ibcon#[27=AT06-04\r\n] 2006.201.05:40:42.17#ibcon#*before write, iclass 14, count 2 2006.201.05:40:42.17#ibcon#enter sib2, iclass 14, count 2 2006.201.05:40:42.17#ibcon#flushed, iclass 14, count 2 2006.201.05:40:42.17#ibcon#about to write, iclass 14, count 2 2006.201.05:40:42.17#ibcon#wrote, iclass 14, count 2 2006.201.05:40:42.17#ibcon#about to read 3, iclass 14, count 2 2006.201.05:40:42.20#ibcon#read 3, iclass 14, count 2 2006.201.05:40:42.20#ibcon#about to read 4, iclass 14, count 2 2006.201.05:40:42.20#ibcon#read 4, iclass 14, count 2 2006.201.05:40:42.20#ibcon#about to read 5, iclass 14, count 2 2006.201.05:40:42.20#ibcon#read 5, iclass 14, count 2 2006.201.05:40:42.20#ibcon#about to read 6, iclass 14, count 2 2006.201.05:40:42.20#ibcon#read 6, iclass 14, count 2 2006.201.05:40:42.20#ibcon#end of sib2, iclass 14, count 2 2006.201.05:40:42.20#ibcon#*after write, iclass 14, count 2 2006.201.05:40:42.20#ibcon#*before return 0, iclass 14, count 2 2006.201.05:40:42.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:42.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.05:40:42.20#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.05:40:42.20#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:42.20#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:42.32#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:42.32#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:42.32#ibcon#enter wrdev, iclass 14, count 0 2006.201.05:40:42.32#ibcon#first serial, iclass 14, count 0 2006.201.05:40:42.32#ibcon#enter sib2, iclass 14, count 0 2006.201.05:40:42.32#ibcon#flushed, iclass 14, count 0 2006.201.05:40:42.32#ibcon#about to write, iclass 14, count 0 2006.201.05:40:42.32#ibcon#wrote, iclass 14, count 0 2006.201.05:40:42.32#ibcon#about to read 3, iclass 14, count 0 2006.201.05:40:42.34#ibcon#read 3, iclass 14, count 0 2006.201.05:40:42.34#ibcon#about to read 4, iclass 14, count 0 2006.201.05:40:42.34#ibcon#read 4, iclass 14, count 0 2006.201.05:40:42.34#ibcon#about to read 5, iclass 14, count 0 2006.201.05:40:42.34#ibcon#read 5, iclass 14, count 0 2006.201.05:40:42.34#ibcon#about to read 6, iclass 14, count 0 2006.201.05:40:42.34#ibcon#read 6, iclass 14, count 0 2006.201.05:40:42.34#ibcon#end of sib2, iclass 14, count 0 2006.201.05:40:42.34#ibcon#*mode == 0, iclass 14, count 0 2006.201.05:40:42.34#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.05:40:42.34#ibcon#[27=USB\r\n] 2006.201.05:40:42.34#ibcon#*before write, iclass 14, count 0 2006.201.05:40:42.34#ibcon#enter sib2, iclass 14, count 0 2006.201.05:40:42.34#ibcon#flushed, iclass 14, count 0 2006.201.05:40:42.34#ibcon#about to write, iclass 14, count 0 2006.201.05:40:42.34#ibcon#wrote, iclass 14, count 0 2006.201.05:40:42.34#ibcon#about to read 3, iclass 14, count 0 2006.201.05:40:42.37#ibcon#read 3, iclass 14, count 0 2006.201.05:40:42.37#ibcon#about to read 4, iclass 14, count 0 2006.201.05:40:42.37#ibcon#read 4, iclass 14, count 0 2006.201.05:40:42.37#ibcon#about to read 5, iclass 14, count 0 2006.201.05:40:42.37#ibcon#read 5, iclass 14, count 0 2006.201.05:40:42.37#ibcon#about to read 6, iclass 14, count 0 2006.201.05:40:42.37#ibcon#read 6, iclass 14, count 0 2006.201.05:40:42.37#ibcon#end of sib2, iclass 14, count 0 2006.201.05:40:42.37#ibcon#*after write, iclass 14, count 0 2006.201.05:40:42.37#ibcon#*before return 0, iclass 14, count 0 2006.201.05:40:42.37#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:42.37#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.05:40:42.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.05:40:42.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.05:40:42.37$vck44/vblo=7,734.99 2006.201.05:40:42.37#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.05:40:42.37#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.05:40:42.37#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:42.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:42.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:42.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:42.37#ibcon#enter wrdev, iclass 16, count 0 2006.201.05:40:42.37#ibcon#first serial, iclass 16, count 0 2006.201.05:40:42.37#ibcon#enter sib2, iclass 16, count 0 2006.201.05:40:42.37#ibcon#flushed, iclass 16, count 0 2006.201.05:40:42.37#ibcon#about to write, iclass 16, count 0 2006.201.05:40:42.37#ibcon#wrote, iclass 16, count 0 2006.201.05:40:42.37#ibcon#about to read 3, iclass 16, count 0 2006.201.05:40:42.39#ibcon#read 3, iclass 16, count 0 2006.201.05:40:42.39#ibcon#about to read 4, iclass 16, count 0 2006.201.05:40:42.39#ibcon#read 4, iclass 16, count 0 2006.201.05:40:42.39#ibcon#about to read 5, iclass 16, count 0 2006.201.05:40:42.39#ibcon#read 5, iclass 16, count 0 2006.201.05:40:42.39#ibcon#about to read 6, iclass 16, count 0 2006.201.05:40:42.39#ibcon#read 6, iclass 16, count 0 2006.201.05:40:42.39#ibcon#end of sib2, iclass 16, count 0 2006.201.05:40:42.39#ibcon#*mode == 0, iclass 16, count 0 2006.201.05:40:42.39#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.05:40:42.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:40:42.39#ibcon#*before write, iclass 16, count 0 2006.201.05:40:42.39#ibcon#enter sib2, iclass 16, count 0 2006.201.05:40:42.39#ibcon#flushed, iclass 16, count 0 2006.201.05:40:42.39#ibcon#about to write, iclass 16, count 0 2006.201.05:40:42.39#ibcon#wrote, iclass 16, count 0 2006.201.05:40:42.39#ibcon#about to read 3, iclass 16, count 0 2006.201.05:40:42.43#ibcon#read 3, iclass 16, count 0 2006.201.05:40:42.43#ibcon#about to read 4, iclass 16, count 0 2006.201.05:40:42.43#ibcon#read 4, iclass 16, count 0 2006.201.05:40:42.43#ibcon#about to read 5, iclass 16, count 0 2006.201.05:40:42.43#ibcon#read 5, iclass 16, count 0 2006.201.05:40:42.43#ibcon#about to read 6, iclass 16, count 0 2006.201.05:40:42.43#ibcon#read 6, iclass 16, count 0 2006.201.05:40:42.43#ibcon#end of sib2, iclass 16, count 0 2006.201.05:40:42.43#ibcon#*after write, iclass 16, count 0 2006.201.05:40:42.43#ibcon#*before return 0, iclass 16, count 0 2006.201.05:40:42.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:42.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.05:40:42.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.05:40:42.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.05:40:42.43$vck44/vb=7,4 2006.201.05:40:42.43#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.05:40:42.43#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.05:40:42.43#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:42.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:42.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:42.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:42.49#ibcon#enter wrdev, iclass 18, count 2 2006.201.05:40:42.49#ibcon#first serial, iclass 18, count 2 2006.201.05:40:42.49#ibcon#enter sib2, iclass 18, count 2 2006.201.05:40:42.49#ibcon#flushed, iclass 18, count 2 2006.201.05:40:42.49#ibcon#about to write, iclass 18, count 2 2006.201.05:40:42.49#ibcon#wrote, iclass 18, count 2 2006.201.05:40:42.49#ibcon#about to read 3, iclass 18, count 2 2006.201.05:40:42.51#ibcon#read 3, iclass 18, count 2 2006.201.05:40:42.51#ibcon#about to read 4, iclass 18, count 2 2006.201.05:40:42.51#ibcon#read 4, iclass 18, count 2 2006.201.05:40:42.51#ibcon#about to read 5, iclass 18, count 2 2006.201.05:40:42.51#ibcon#read 5, iclass 18, count 2 2006.201.05:40:42.51#ibcon#about to read 6, iclass 18, count 2 2006.201.05:40:42.51#ibcon#read 6, iclass 18, count 2 2006.201.05:40:42.51#ibcon#end of sib2, iclass 18, count 2 2006.201.05:40:42.51#ibcon#*mode == 0, iclass 18, count 2 2006.201.05:40:42.51#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.05:40:42.51#ibcon#[27=AT07-04\r\n] 2006.201.05:40:42.51#ibcon#*before write, iclass 18, count 2 2006.201.05:40:42.51#ibcon#enter sib2, iclass 18, count 2 2006.201.05:40:42.51#ibcon#flushed, iclass 18, count 2 2006.201.05:40:42.51#ibcon#about to write, iclass 18, count 2 2006.201.05:40:42.51#ibcon#wrote, iclass 18, count 2 2006.201.05:40:42.51#ibcon#about to read 3, iclass 18, count 2 2006.201.05:40:42.54#ibcon#read 3, iclass 18, count 2 2006.201.05:40:42.54#ibcon#about to read 4, iclass 18, count 2 2006.201.05:40:42.54#ibcon#read 4, iclass 18, count 2 2006.201.05:40:42.54#ibcon#about to read 5, iclass 18, count 2 2006.201.05:40:42.54#ibcon#read 5, iclass 18, count 2 2006.201.05:40:42.54#ibcon#about to read 6, iclass 18, count 2 2006.201.05:40:42.54#ibcon#read 6, iclass 18, count 2 2006.201.05:40:42.54#ibcon#end of sib2, iclass 18, count 2 2006.201.05:40:42.54#ibcon#*after write, iclass 18, count 2 2006.201.05:40:42.54#ibcon#*before return 0, iclass 18, count 2 2006.201.05:40:42.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:42.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.05:40:42.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.05:40:42.54#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:42.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:42.66#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:42.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:42.66#ibcon#enter wrdev, iclass 18, count 0 2006.201.05:40:42.66#ibcon#first serial, iclass 18, count 0 2006.201.05:40:42.66#ibcon#enter sib2, iclass 18, count 0 2006.201.05:40:42.66#ibcon#flushed, iclass 18, count 0 2006.201.05:40:42.66#ibcon#about to write, iclass 18, count 0 2006.201.05:40:42.66#ibcon#wrote, iclass 18, count 0 2006.201.05:40:42.66#ibcon#about to read 3, iclass 18, count 0 2006.201.05:40:42.68#ibcon#read 3, iclass 18, count 0 2006.201.05:40:42.68#ibcon#about to read 4, iclass 18, count 0 2006.201.05:40:42.68#ibcon#read 4, iclass 18, count 0 2006.201.05:40:42.68#ibcon#about to read 5, iclass 18, count 0 2006.201.05:40:42.68#ibcon#read 5, iclass 18, count 0 2006.201.05:40:42.68#ibcon#about to read 6, iclass 18, count 0 2006.201.05:40:42.68#ibcon#read 6, iclass 18, count 0 2006.201.05:40:42.68#ibcon#end of sib2, iclass 18, count 0 2006.201.05:40:42.68#ibcon#*mode == 0, iclass 18, count 0 2006.201.05:40:42.68#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.05:40:42.68#ibcon#[27=USB\r\n] 2006.201.05:40:42.68#ibcon#*before write, iclass 18, count 0 2006.201.05:40:42.68#ibcon#enter sib2, iclass 18, count 0 2006.201.05:40:42.68#ibcon#flushed, iclass 18, count 0 2006.201.05:40:42.68#ibcon#about to write, iclass 18, count 0 2006.201.05:40:42.68#ibcon#wrote, iclass 18, count 0 2006.201.05:40:42.68#ibcon#about to read 3, iclass 18, count 0 2006.201.05:40:42.71#ibcon#read 3, iclass 18, count 0 2006.201.05:40:42.71#ibcon#about to read 4, iclass 18, count 0 2006.201.05:40:42.71#ibcon#read 4, iclass 18, count 0 2006.201.05:40:42.71#ibcon#about to read 5, iclass 18, count 0 2006.201.05:40:42.71#ibcon#read 5, iclass 18, count 0 2006.201.05:40:42.71#ibcon#about to read 6, iclass 18, count 0 2006.201.05:40:42.71#ibcon#read 6, iclass 18, count 0 2006.201.05:40:42.71#ibcon#end of sib2, iclass 18, count 0 2006.201.05:40:42.71#ibcon#*after write, iclass 18, count 0 2006.201.05:40:42.71#ibcon#*before return 0, iclass 18, count 0 2006.201.05:40:42.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:42.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.05:40:42.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.05:40:42.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.05:40:42.71$vck44/vblo=8,744.99 2006.201.05:40:42.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.05:40:42.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.05:40:42.71#ibcon#ireg 17 cls_cnt 0 2006.201.05:40:42.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:42.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:42.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:42.71#ibcon#enter wrdev, iclass 20, count 0 2006.201.05:40:42.71#ibcon#first serial, iclass 20, count 0 2006.201.05:40:42.71#ibcon#enter sib2, iclass 20, count 0 2006.201.05:40:42.71#ibcon#flushed, iclass 20, count 0 2006.201.05:40:42.71#ibcon#about to write, iclass 20, count 0 2006.201.05:40:42.71#ibcon#wrote, iclass 20, count 0 2006.201.05:40:42.71#ibcon#about to read 3, iclass 20, count 0 2006.201.05:40:42.73#ibcon#read 3, iclass 20, count 0 2006.201.05:40:42.73#ibcon#about to read 4, iclass 20, count 0 2006.201.05:40:42.73#ibcon#read 4, iclass 20, count 0 2006.201.05:40:42.73#ibcon#about to read 5, iclass 20, count 0 2006.201.05:40:42.73#ibcon#read 5, iclass 20, count 0 2006.201.05:40:42.73#ibcon#about to read 6, iclass 20, count 0 2006.201.05:40:42.73#ibcon#read 6, iclass 20, count 0 2006.201.05:40:42.73#ibcon#end of sib2, iclass 20, count 0 2006.201.05:40:42.73#ibcon#*mode == 0, iclass 20, count 0 2006.201.05:40:42.73#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.05:40:42.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:40:42.73#ibcon#*before write, iclass 20, count 0 2006.201.05:40:42.73#ibcon#enter sib2, iclass 20, count 0 2006.201.05:40:42.73#ibcon#flushed, iclass 20, count 0 2006.201.05:40:42.73#ibcon#about to write, iclass 20, count 0 2006.201.05:40:42.73#ibcon#wrote, iclass 20, count 0 2006.201.05:40:42.73#ibcon#about to read 3, iclass 20, count 0 2006.201.05:40:42.77#ibcon#read 3, iclass 20, count 0 2006.201.05:40:42.77#ibcon#about to read 4, iclass 20, count 0 2006.201.05:40:42.77#ibcon#read 4, iclass 20, count 0 2006.201.05:40:42.77#ibcon#about to read 5, iclass 20, count 0 2006.201.05:40:42.77#ibcon#read 5, iclass 20, count 0 2006.201.05:40:42.77#ibcon#about to read 6, iclass 20, count 0 2006.201.05:40:42.77#ibcon#read 6, iclass 20, count 0 2006.201.05:40:42.77#ibcon#end of sib2, iclass 20, count 0 2006.201.05:40:42.77#ibcon#*after write, iclass 20, count 0 2006.201.05:40:42.77#ibcon#*before return 0, iclass 20, count 0 2006.201.05:40:42.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:42.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.05:40:42.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.05:40:42.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.05:40:42.77$vck44/vb=8,4 2006.201.05:40:42.77#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.05:40:42.77#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.05:40:42.77#ibcon#ireg 11 cls_cnt 2 2006.201.05:40:42.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:42.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:42.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:42.83#ibcon#enter wrdev, iclass 22, count 2 2006.201.05:40:42.83#ibcon#first serial, iclass 22, count 2 2006.201.05:40:42.83#ibcon#enter sib2, iclass 22, count 2 2006.201.05:40:42.83#ibcon#flushed, iclass 22, count 2 2006.201.05:40:42.83#ibcon#about to write, iclass 22, count 2 2006.201.05:40:42.83#ibcon#wrote, iclass 22, count 2 2006.201.05:40:42.83#ibcon#about to read 3, iclass 22, count 2 2006.201.05:40:42.85#ibcon#read 3, iclass 22, count 2 2006.201.05:40:42.85#ibcon#about to read 4, iclass 22, count 2 2006.201.05:40:42.85#ibcon#read 4, iclass 22, count 2 2006.201.05:40:42.85#ibcon#about to read 5, iclass 22, count 2 2006.201.05:40:42.85#ibcon#read 5, iclass 22, count 2 2006.201.05:40:42.85#ibcon#about to read 6, iclass 22, count 2 2006.201.05:40:42.85#ibcon#read 6, iclass 22, count 2 2006.201.05:40:42.85#ibcon#end of sib2, iclass 22, count 2 2006.201.05:40:42.85#ibcon#*mode == 0, iclass 22, count 2 2006.201.05:40:42.85#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.05:40:42.85#ibcon#[27=AT08-04\r\n] 2006.201.05:40:42.85#ibcon#*before write, iclass 22, count 2 2006.201.05:40:42.85#ibcon#enter sib2, iclass 22, count 2 2006.201.05:40:42.85#ibcon#flushed, iclass 22, count 2 2006.201.05:40:42.85#ibcon#about to write, iclass 22, count 2 2006.201.05:40:42.85#ibcon#wrote, iclass 22, count 2 2006.201.05:40:42.85#ibcon#about to read 3, iclass 22, count 2 2006.201.05:40:42.88#ibcon#read 3, iclass 22, count 2 2006.201.05:40:42.88#ibcon#about to read 4, iclass 22, count 2 2006.201.05:40:42.88#ibcon#read 4, iclass 22, count 2 2006.201.05:40:42.88#ibcon#about to read 5, iclass 22, count 2 2006.201.05:40:42.88#ibcon#read 5, iclass 22, count 2 2006.201.05:40:42.88#ibcon#about to read 6, iclass 22, count 2 2006.201.05:40:42.88#ibcon#read 6, iclass 22, count 2 2006.201.05:40:42.88#ibcon#end of sib2, iclass 22, count 2 2006.201.05:40:42.88#ibcon#*after write, iclass 22, count 2 2006.201.05:40:42.88#ibcon#*before return 0, iclass 22, count 2 2006.201.05:40:42.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:42.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.05:40:42.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.05:40:42.88#ibcon#ireg 7 cls_cnt 0 2006.201.05:40:42.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:43.00#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:43.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:43.00#ibcon#enter wrdev, iclass 22, count 0 2006.201.05:40:43.00#ibcon#first serial, iclass 22, count 0 2006.201.05:40:43.00#ibcon#enter sib2, iclass 22, count 0 2006.201.05:40:43.00#ibcon#flushed, iclass 22, count 0 2006.201.05:40:43.00#ibcon#about to write, iclass 22, count 0 2006.201.05:40:43.00#ibcon#wrote, iclass 22, count 0 2006.201.05:40:43.00#ibcon#about to read 3, iclass 22, count 0 2006.201.05:40:43.02#ibcon#read 3, iclass 22, count 0 2006.201.05:40:43.02#ibcon#about to read 4, iclass 22, count 0 2006.201.05:40:43.02#ibcon#read 4, iclass 22, count 0 2006.201.05:40:43.02#ibcon#about to read 5, iclass 22, count 0 2006.201.05:40:43.02#ibcon#read 5, iclass 22, count 0 2006.201.05:40:43.02#ibcon#about to read 6, iclass 22, count 0 2006.201.05:40:43.02#ibcon#read 6, iclass 22, count 0 2006.201.05:40:43.02#ibcon#end of sib2, iclass 22, count 0 2006.201.05:40:43.02#ibcon#*mode == 0, iclass 22, count 0 2006.201.05:40:43.02#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.05:40:43.02#ibcon#[27=USB\r\n] 2006.201.05:40:43.02#ibcon#*before write, iclass 22, count 0 2006.201.05:40:43.02#ibcon#enter sib2, iclass 22, count 0 2006.201.05:40:43.02#ibcon#flushed, iclass 22, count 0 2006.201.05:40:43.02#ibcon#about to write, iclass 22, count 0 2006.201.05:40:43.02#ibcon#wrote, iclass 22, count 0 2006.201.05:40:43.02#ibcon#about to read 3, iclass 22, count 0 2006.201.05:40:43.05#ibcon#read 3, iclass 22, count 0 2006.201.05:40:43.05#ibcon#about to read 4, iclass 22, count 0 2006.201.05:40:43.05#ibcon#read 4, iclass 22, count 0 2006.201.05:40:43.05#ibcon#about to read 5, iclass 22, count 0 2006.201.05:40:43.05#ibcon#read 5, iclass 22, count 0 2006.201.05:40:43.05#ibcon#about to read 6, iclass 22, count 0 2006.201.05:40:43.05#ibcon#read 6, iclass 22, count 0 2006.201.05:40:43.05#ibcon#end of sib2, iclass 22, count 0 2006.201.05:40:43.05#ibcon#*after write, iclass 22, count 0 2006.201.05:40:43.05#ibcon#*before return 0, iclass 22, count 0 2006.201.05:40:43.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:43.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.05:40:43.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.05:40:43.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.05:40:43.05$vck44/vabw=wide 2006.201.05:40:43.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.05:40:43.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.05:40:43.05#ibcon#ireg 8 cls_cnt 0 2006.201.05:40:43.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:43.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:43.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:43.05#ibcon#enter wrdev, iclass 24, count 0 2006.201.05:40:43.05#ibcon#first serial, iclass 24, count 0 2006.201.05:40:43.05#ibcon#enter sib2, iclass 24, count 0 2006.201.05:40:43.05#ibcon#flushed, iclass 24, count 0 2006.201.05:40:43.05#ibcon#about to write, iclass 24, count 0 2006.201.05:40:43.05#ibcon#wrote, iclass 24, count 0 2006.201.05:40:43.05#ibcon#about to read 3, iclass 24, count 0 2006.201.05:40:43.07#ibcon#read 3, iclass 24, count 0 2006.201.05:40:43.07#ibcon#about to read 4, iclass 24, count 0 2006.201.05:40:43.07#ibcon#read 4, iclass 24, count 0 2006.201.05:40:43.07#ibcon#about to read 5, iclass 24, count 0 2006.201.05:40:43.07#ibcon#read 5, iclass 24, count 0 2006.201.05:40:43.07#ibcon#about to read 6, iclass 24, count 0 2006.201.05:40:43.07#ibcon#read 6, iclass 24, count 0 2006.201.05:40:43.07#ibcon#end of sib2, iclass 24, count 0 2006.201.05:40:43.07#ibcon#*mode == 0, iclass 24, count 0 2006.201.05:40:43.07#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.05:40:43.07#ibcon#[25=BW32\r\n] 2006.201.05:40:43.07#ibcon#*before write, iclass 24, count 0 2006.201.05:40:43.07#ibcon#enter sib2, iclass 24, count 0 2006.201.05:40:43.07#ibcon#flushed, iclass 24, count 0 2006.201.05:40:43.07#ibcon#about to write, iclass 24, count 0 2006.201.05:40:43.07#ibcon#wrote, iclass 24, count 0 2006.201.05:40:43.07#ibcon#about to read 3, iclass 24, count 0 2006.201.05:40:43.10#ibcon#read 3, iclass 24, count 0 2006.201.05:40:43.10#ibcon#about to read 4, iclass 24, count 0 2006.201.05:40:43.10#ibcon#read 4, iclass 24, count 0 2006.201.05:40:43.10#ibcon#about to read 5, iclass 24, count 0 2006.201.05:40:43.10#ibcon#read 5, iclass 24, count 0 2006.201.05:40:43.10#ibcon#about to read 6, iclass 24, count 0 2006.201.05:40:43.10#ibcon#read 6, iclass 24, count 0 2006.201.05:40:43.10#ibcon#end of sib2, iclass 24, count 0 2006.201.05:40:43.10#ibcon#*after write, iclass 24, count 0 2006.201.05:40:43.10#ibcon#*before return 0, iclass 24, count 0 2006.201.05:40:43.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:43.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.05:40:43.10#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.05:40:43.10#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.05:40:43.10$vck44/vbbw=wide 2006.201.05:40:43.10#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.05:40:43.10#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.05:40:43.10#ibcon#ireg 8 cls_cnt 0 2006.201.05:40:43.10#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:40:43.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:40:43.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:40:43.17#ibcon#enter wrdev, iclass 26, count 0 2006.201.05:40:43.17#ibcon#first serial, iclass 26, count 0 2006.201.05:40:43.17#ibcon#enter sib2, iclass 26, count 0 2006.201.05:40:43.17#ibcon#flushed, iclass 26, count 0 2006.201.05:40:43.17#ibcon#about to write, iclass 26, count 0 2006.201.05:40:43.17#ibcon#wrote, iclass 26, count 0 2006.201.05:40:43.17#ibcon#about to read 3, iclass 26, count 0 2006.201.05:40:43.19#ibcon#read 3, iclass 26, count 0 2006.201.05:40:43.19#ibcon#about to read 4, iclass 26, count 0 2006.201.05:40:43.19#ibcon#read 4, iclass 26, count 0 2006.201.05:40:43.19#ibcon#about to read 5, iclass 26, count 0 2006.201.05:40:43.19#ibcon#read 5, iclass 26, count 0 2006.201.05:40:43.19#ibcon#about to read 6, iclass 26, count 0 2006.201.05:40:43.19#ibcon#read 6, iclass 26, count 0 2006.201.05:40:43.19#ibcon#end of sib2, iclass 26, count 0 2006.201.05:40:43.19#ibcon#*mode == 0, iclass 26, count 0 2006.201.05:40:43.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.05:40:43.19#ibcon#[27=BW32\r\n] 2006.201.05:40:43.19#ibcon#*before write, iclass 26, count 0 2006.201.05:40:43.19#ibcon#enter sib2, iclass 26, count 0 2006.201.05:40:43.19#ibcon#flushed, iclass 26, count 0 2006.201.05:40:43.19#ibcon#about to write, iclass 26, count 0 2006.201.05:40:43.19#ibcon#wrote, iclass 26, count 0 2006.201.05:40:43.19#ibcon#about to read 3, iclass 26, count 0 2006.201.05:40:43.22#ibcon#read 3, iclass 26, count 0 2006.201.05:40:43.22#ibcon#about to read 4, iclass 26, count 0 2006.201.05:40:43.22#ibcon#read 4, iclass 26, count 0 2006.201.05:40:43.22#ibcon#about to read 5, iclass 26, count 0 2006.201.05:40:43.22#ibcon#read 5, iclass 26, count 0 2006.201.05:40:43.22#ibcon#about to read 6, iclass 26, count 0 2006.201.05:40:43.22#ibcon#read 6, iclass 26, count 0 2006.201.05:40:43.22#ibcon#end of sib2, iclass 26, count 0 2006.201.05:40:43.22#ibcon#*after write, iclass 26, count 0 2006.201.05:40:43.22#ibcon#*before return 0, iclass 26, count 0 2006.201.05:40:43.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:40:43.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:40:43.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.05:40:43.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.05:40:43.22$setupk4/ifdk4 2006.201.05:40:43.22$ifdk4/lo= 2006.201.05:40:43.22$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:40:43.22$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:40:43.22$ifdk4/patch= 2006.201.05:40:43.22$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:40:43.22$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:40:43.22$setupk4/!*+20s 2006.201.05:40:43.71#abcon#<5=/04 2.1 3.9 23.08 901003.6\r\n> 2006.201.05:40:43.73#abcon#{5=INTERFACE CLEAR} 2006.201.05:40:43.79#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:40:53.88#abcon#<5=/04 2.1 3.9 23.08 911003.6\r\n> 2006.201.05:40:53.90#abcon#{5=INTERFACE CLEAR} 2006.201.05:40:53.96#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:40:57.33$setupk4/"tpicd 2006.201.05:40:57.33$setupk4/echo=off 2006.201.05:40:57.33$setupk4/xlog=off 2006.201.05:40:57.33:!2006.201.05:42:36 2006.201.05:41:00.14#trakl#Source acquired 2006.201.05:41:02.14#flagr#flagr/antenna,acquired 2006.201.05:42:36.00:preob 2006.201.05:42:36.14/onsource/TRACKING 2006.201.05:42:36.14:!2006.201.05:42:46 2006.201.05:42:46.00:"tape 2006.201.05:42:46.00:"st=record 2006.201.05:42:46.00:data_valid=on 2006.201.05:42:46.00:midob 2006.201.05:42:47.14/onsource/TRACKING 2006.201.05:42:47.14/wx/23.07,1003.6,90 2006.201.05:42:47.23/cable/+6.4662E-03 2006.201.05:42:48.32/va/01,08,usb,yes,29,31 2006.201.05:42:48.32/va/02,07,usb,yes,31,32 2006.201.05:42:48.32/va/03,08,usb,yes,28,29 2006.201.05:42:48.32/va/04,07,usb,yes,32,34 2006.201.05:42:48.32/va/05,04,usb,yes,28,29 2006.201.05:42:48.32/va/06,05,usb,yes,28,28 2006.201.05:42:48.32/va/07,05,usb,yes,28,29 2006.201.05:42:48.32/va/08,04,usb,yes,27,33 2006.201.05:42:48.55/valo/01,524.99,yes,locked 2006.201.05:42:48.55/valo/02,534.99,yes,locked 2006.201.05:42:48.55/valo/03,564.99,yes,locked 2006.201.05:42:48.55/valo/04,624.99,yes,locked 2006.201.05:42:48.55/valo/05,734.99,yes,locked 2006.201.05:42:48.55/valo/06,814.99,yes,locked 2006.201.05:42:48.55/valo/07,864.99,yes,locked 2006.201.05:42:48.55/valo/08,884.99,yes,locked 2006.201.05:42:49.64/vb/01,04,usb,yes,29,27 2006.201.05:42:49.64/vb/02,05,usb,yes,28,27 2006.201.05:42:49.64/vb/03,04,usb,yes,28,31 2006.201.05:42:49.64/vb/04,05,usb,yes,29,28 2006.201.05:42:49.64/vb/05,04,usb,yes,25,28 2006.201.05:42:49.64/vb/06,04,usb,yes,30,26 2006.201.05:42:49.64/vb/07,04,usb,yes,30,29 2006.201.05:42:49.64/vb/08,04,usb,yes,27,30 2006.201.05:42:49.87/vblo/01,629.99,yes,locked 2006.201.05:42:49.87/vblo/02,634.99,yes,locked 2006.201.05:42:49.87/vblo/03,649.99,yes,locked 2006.201.05:42:49.87/vblo/04,679.99,yes,locked 2006.201.05:42:49.87/vblo/05,709.99,yes,locked 2006.201.05:42:49.87/vblo/06,719.99,yes,locked 2006.201.05:42:49.87/vblo/07,734.99,yes,locked 2006.201.05:42:49.87/vblo/08,744.99,yes,locked 2006.201.05:42:50.02/vabw/8 2006.201.05:42:50.17/vbbw/8 2006.201.05:42:50.35/xfe/off,on,16.2 2006.201.05:42:50.72/ifatt/23,28,28,28 2006.201.05:42:51.05/fmout-gps/S +4.54E-07 2006.201.05:42:51.09:!2006.201.05:43:36 2006.201.05:43:36.00:data_valid=off 2006.201.05:43:36.00:"et 2006.201.05:43:36.00:!+3s 2006.201.05:43:39.01:"tape 2006.201.05:43:39.01:postob 2006.201.05:43:39.08/cable/+6.4670E-03 2006.201.05:43:39.08/wx/23.05,1003.6,91 2006.201.05:43:39.14/fmout-gps/S +4.55E-07 2006.201.05:43:39.14:scan_name=201-0546,jd0607,110 2006.201.05:43:39.14:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.201.05:43:40.14#flagr#flagr/antenna,new-source 2006.201.05:43:40.14:checkk5 2006.201.05:43:40.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:43:40.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:43:41.33/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:43:41.73/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:43:42.13/chk_obsdata//k5ts1/T2010542??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.05:43:42.53/chk_obsdata//k5ts2/T2010542??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.05:43:42.95/chk_obsdata//k5ts3/T2010542??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.05:43:43.37/chk_obsdata//k5ts4/T2010542??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.05:43:44.10/k5log//k5ts1_log_newline 2006.201.05:43:44.81/k5log//k5ts2_log_newline 2006.201.05:43:45.52/k5log//k5ts3_log_newline 2006.201.05:43:46.25/k5log//k5ts4_log_newline 2006.201.05:43:46.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:43:46.27:setupk4=1 2006.201.05:43:46.27$setupk4/echo=on 2006.201.05:43:46.27$setupk4/pcalon 2006.201.05:43:46.27$pcalon/"no phase cal control is implemented here 2006.201.05:43:46.27$setupk4/"tpicd=stop 2006.201.05:43:46.27$setupk4/"rec=synch_on 2006.201.05:43:46.27$setupk4/"rec_mode=128 2006.201.05:43:46.27$setupk4/!* 2006.201.05:43:46.27$setupk4/recpk4 2006.201.05:43:46.27$recpk4/recpatch= 2006.201.05:43:46.28$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:43:46.28$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:43:46.28$setupk4/vck44 2006.201.05:43:46.28$vck44/valo=1,524.99 2006.201.05:43:46.28#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.05:43:46.28#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.05:43:46.28#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:46.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:46.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:46.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:46.28#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:43:46.28#ibcon#first serial, iclass 31, count 0 2006.201.05:43:46.28#ibcon#enter sib2, iclass 31, count 0 2006.201.05:43:46.28#ibcon#flushed, iclass 31, count 0 2006.201.05:43:46.28#ibcon#about to write, iclass 31, count 0 2006.201.05:43:46.28#ibcon#wrote, iclass 31, count 0 2006.201.05:43:46.28#ibcon#about to read 3, iclass 31, count 0 2006.201.05:43:46.30#ibcon#read 3, iclass 31, count 0 2006.201.05:43:46.30#ibcon#about to read 4, iclass 31, count 0 2006.201.05:43:46.30#ibcon#read 4, iclass 31, count 0 2006.201.05:43:46.30#ibcon#about to read 5, iclass 31, count 0 2006.201.05:43:46.30#ibcon#read 5, iclass 31, count 0 2006.201.05:43:46.30#ibcon#about to read 6, iclass 31, count 0 2006.201.05:43:46.30#ibcon#read 6, iclass 31, count 0 2006.201.05:43:46.30#ibcon#end of sib2, iclass 31, count 0 2006.201.05:43:46.30#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:43:46.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:43:46.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:43:46.30#ibcon#*before write, iclass 31, count 0 2006.201.05:43:46.30#ibcon#enter sib2, iclass 31, count 0 2006.201.05:43:46.30#ibcon#flushed, iclass 31, count 0 2006.201.05:43:46.30#ibcon#about to write, iclass 31, count 0 2006.201.05:43:46.30#ibcon#wrote, iclass 31, count 0 2006.201.05:43:46.30#ibcon#about to read 3, iclass 31, count 0 2006.201.05:43:46.35#ibcon#read 3, iclass 31, count 0 2006.201.05:43:46.35#ibcon#about to read 4, iclass 31, count 0 2006.201.05:43:46.35#ibcon#read 4, iclass 31, count 0 2006.201.05:43:46.35#ibcon#about to read 5, iclass 31, count 0 2006.201.05:43:46.35#ibcon#read 5, iclass 31, count 0 2006.201.05:43:46.35#ibcon#about to read 6, iclass 31, count 0 2006.201.05:43:46.35#ibcon#read 6, iclass 31, count 0 2006.201.05:43:46.35#ibcon#end of sib2, iclass 31, count 0 2006.201.05:43:46.35#ibcon#*after write, iclass 31, count 0 2006.201.05:43:46.35#ibcon#*before return 0, iclass 31, count 0 2006.201.05:43:46.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:46.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:46.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:43:46.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:43:46.35$vck44/va=1,8 2006.201.05:43:46.35#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.05:43:46.35#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.05:43:46.35#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:46.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:46.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:46.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:46.35#ibcon#enter wrdev, iclass 33, count 2 2006.201.05:43:46.35#ibcon#first serial, iclass 33, count 2 2006.201.05:43:46.35#ibcon#enter sib2, iclass 33, count 2 2006.201.05:43:46.35#ibcon#flushed, iclass 33, count 2 2006.201.05:43:46.35#ibcon#about to write, iclass 33, count 2 2006.201.05:43:46.35#ibcon#wrote, iclass 33, count 2 2006.201.05:43:46.35#ibcon#about to read 3, iclass 33, count 2 2006.201.05:43:46.37#ibcon#read 3, iclass 33, count 2 2006.201.05:43:46.37#ibcon#about to read 4, iclass 33, count 2 2006.201.05:43:46.37#ibcon#read 4, iclass 33, count 2 2006.201.05:43:46.37#ibcon#about to read 5, iclass 33, count 2 2006.201.05:43:46.37#ibcon#read 5, iclass 33, count 2 2006.201.05:43:46.37#ibcon#about to read 6, iclass 33, count 2 2006.201.05:43:46.37#ibcon#read 6, iclass 33, count 2 2006.201.05:43:46.37#ibcon#end of sib2, iclass 33, count 2 2006.201.05:43:46.37#ibcon#*mode == 0, iclass 33, count 2 2006.201.05:43:46.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.05:43:46.37#ibcon#[25=AT01-08\r\n] 2006.201.05:43:46.37#ibcon#*before write, iclass 33, count 2 2006.201.05:43:46.37#ibcon#enter sib2, iclass 33, count 2 2006.201.05:43:46.37#ibcon#flushed, iclass 33, count 2 2006.201.05:43:46.37#ibcon#about to write, iclass 33, count 2 2006.201.05:43:46.37#ibcon#wrote, iclass 33, count 2 2006.201.05:43:46.37#ibcon#about to read 3, iclass 33, count 2 2006.201.05:43:46.40#ibcon#read 3, iclass 33, count 2 2006.201.05:43:46.40#ibcon#about to read 4, iclass 33, count 2 2006.201.05:43:46.40#ibcon#read 4, iclass 33, count 2 2006.201.05:43:46.40#ibcon#about to read 5, iclass 33, count 2 2006.201.05:43:46.40#ibcon#read 5, iclass 33, count 2 2006.201.05:43:46.40#ibcon#about to read 6, iclass 33, count 2 2006.201.05:43:46.40#ibcon#read 6, iclass 33, count 2 2006.201.05:43:46.40#ibcon#end of sib2, iclass 33, count 2 2006.201.05:43:46.40#ibcon#*after write, iclass 33, count 2 2006.201.05:43:46.40#ibcon#*before return 0, iclass 33, count 2 2006.201.05:43:46.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:46.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:46.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.05:43:46.40#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:46.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:46.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:46.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:46.52#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:43:46.52#ibcon#first serial, iclass 33, count 0 2006.201.05:43:46.52#ibcon#enter sib2, iclass 33, count 0 2006.201.05:43:46.52#ibcon#flushed, iclass 33, count 0 2006.201.05:43:46.52#ibcon#about to write, iclass 33, count 0 2006.201.05:43:46.52#ibcon#wrote, iclass 33, count 0 2006.201.05:43:46.52#ibcon#about to read 3, iclass 33, count 0 2006.201.05:43:46.54#ibcon#read 3, iclass 33, count 0 2006.201.05:43:46.54#ibcon#about to read 4, iclass 33, count 0 2006.201.05:43:46.54#ibcon#read 4, iclass 33, count 0 2006.201.05:43:46.54#ibcon#about to read 5, iclass 33, count 0 2006.201.05:43:46.54#ibcon#read 5, iclass 33, count 0 2006.201.05:43:46.54#ibcon#about to read 6, iclass 33, count 0 2006.201.05:43:46.54#ibcon#read 6, iclass 33, count 0 2006.201.05:43:46.54#ibcon#end of sib2, iclass 33, count 0 2006.201.05:43:46.54#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:43:46.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:43:46.54#ibcon#[25=USB\r\n] 2006.201.05:43:46.54#ibcon#*before write, iclass 33, count 0 2006.201.05:43:46.54#ibcon#enter sib2, iclass 33, count 0 2006.201.05:43:46.54#ibcon#flushed, iclass 33, count 0 2006.201.05:43:46.54#ibcon#about to write, iclass 33, count 0 2006.201.05:43:46.54#ibcon#wrote, iclass 33, count 0 2006.201.05:43:46.54#ibcon#about to read 3, iclass 33, count 0 2006.201.05:43:46.57#ibcon#read 3, iclass 33, count 0 2006.201.05:43:46.57#ibcon#about to read 4, iclass 33, count 0 2006.201.05:43:46.57#ibcon#read 4, iclass 33, count 0 2006.201.05:43:46.57#ibcon#about to read 5, iclass 33, count 0 2006.201.05:43:46.57#ibcon#read 5, iclass 33, count 0 2006.201.05:43:46.57#ibcon#about to read 6, iclass 33, count 0 2006.201.05:43:46.57#ibcon#read 6, iclass 33, count 0 2006.201.05:43:46.57#ibcon#end of sib2, iclass 33, count 0 2006.201.05:43:46.57#ibcon#*after write, iclass 33, count 0 2006.201.05:43:46.57#ibcon#*before return 0, iclass 33, count 0 2006.201.05:43:46.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:46.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:46.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:43:46.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:43:46.57$vck44/valo=2,534.99 2006.201.05:43:46.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.05:43:46.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.05:43:46.57#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:46.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:46.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:46.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:46.57#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:43:46.57#ibcon#first serial, iclass 35, count 0 2006.201.05:43:46.57#ibcon#enter sib2, iclass 35, count 0 2006.201.05:43:46.57#ibcon#flushed, iclass 35, count 0 2006.201.05:43:46.57#ibcon#about to write, iclass 35, count 0 2006.201.05:43:46.57#ibcon#wrote, iclass 35, count 0 2006.201.05:43:46.57#ibcon#about to read 3, iclass 35, count 0 2006.201.05:43:46.59#ibcon#read 3, iclass 35, count 0 2006.201.05:43:46.59#ibcon#about to read 4, iclass 35, count 0 2006.201.05:43:46.59#ibcon#read 4, iclass 35, count 0 2006.201.05:43:46.59#ibcon#about to read 5, iclass 35, count 0 2006.201.05:43:46.59#ibcon#read 5, iclass 35, count 0 2006.201.05:43:46.59#ibcon#about to read 6, iclass 35, count 0 2006.201.05:43:46.59#ibcon#read 6, iclass 35, count 0 2006.201.05:43:46.59#ibcon#end of sib2, iclass 35, count 0 2006.201.05:43:46.59#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:43:46.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:43:46.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:43:46.59#ibcon#*before write, iclass 35, count 0 2006.201.05:43:46.59#ibcon#enter sib2, iclass 35, count 0 2006.201.05:43:46.59#ibcon#flushed, iclass 35, count 0 2006.201.05:43:46.59#ibcon#about to write, iclass 35, count 0 2006.201.05:43:46.59#ibcon#wrote, iclass 35, count 0 2006.201.05:43:46.59#ibcon#about to read 3, iclass 35, count 0 2006.201.05:43:46.63#ibcon#read 3, iclass 35, count 0 2006.201.05:43:46.63#ibcon#about to read 4, iclass 35, count 0 2006.201.05:43:46.63#ibcon#read 4, iclass 35, count 0 2006.201.05:43:46.63#ibcon#about to read 5, iclass 35, count 0 2006.201.05:43:46.63#ibcon#read 5, iclass 35, count 0 2006.201.05:43:46.63#ibcon#about to read 6, iclass 35, count 0 2006.201.05:43:46.63#ibcon#read 6, iclass 35, count 0 2006.201.05:43:46.63#ibcon#end of sib2, iclass 35, count 0 2006.201.05:43:46.63#ibcon#*after write, iclass 35, count 0 2006.201.05:43:46.63#ibcon#*before return 0, iclass 35, count 0 2006.201.05:43:46.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:46.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:46.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:43:46.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:43:46.63$vck44/va=2,7 2006.201.05:43:46.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.05:43:46.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.05:43:46.63#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:46.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:46.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:46.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:46.69#ibcon#enter wrdev, iclass 37, count 2 2006.201.05:43:46.69#ibcon#first serial, iclass 37, count 2 2006.201.05:43:46.69#ibcon#enter sib2, iclass 37, count 2 2006.201.05:43:46.69#ibcon#flushed, iclass 37, count 2 2006.201.05:43:46.69#ibcon#about to write, iclass 37, count 2 2006.201.05:43:46.69#ibcon#wrote, iclass 37, count 2 2006.201.05:43:46.69#ibcon#about to read 3, iclass 37, count 2 2006.201.05:43:46.71#ibcon#read 3, iclass 37, count 2 2006.201.05:43:46.71#ibcon#about to read 4, iclass 37, count 2 2006.201.05:43:46.71#ibcon#read 4, iclass 37, count 2 2006.201.05:43:46.71#ibcon#about to read 5, iclass 37, count 2 2006.201.05:43:46.71#ibcon#read 5, iclass 37, count 2 2006.201.05:43:46.71#ibcon#about to read 6, iclass 37, count 2 2006.201.05:43:46.71#ibcon#read 6, iclass 37, count 2 2006.201.05:43:46.71#ibcon#end of sib2, iclass 37, count 2 2006.201.05:43:46.71#ibcon#*mode == 0, iclass 37, count 2 2006.201.05:43:46.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.05:43:46.71#ibcon#[25=AT02-07\r\n] 2006.201.05:43:46.71#ibcon#*before write, iclass 37, count 2 2006.201.05:43:46.71#ibcon#enter sib2, iclass 37, count 2 2006.201.05:43:46.71#ibcon#flushed, iclass 37, count 2 2006.201.05:43:46.71#ibcon#about to write, iclass 37, count 2 2006.201.05:43:46.71#ibcon#wrote, iclass 37, count 2 2006.201.05:43:46.71#ibcon#about to read 3, iclass 37, count 2 2006.201.05:43:46.74#ibcon#read 3, iclass 37, count 2 2006.201.05:43:46.74#ibcon#about to read 4, iclass 37, count 2 2006.201.05:43:46.74#ibcon#read 4, iclass 37, count 2 2006.201.05:43:46.74#ibcon#about to read 5, iclass 37, count 2 2006.201.05:43:46.74#ibcon#read 5, iclass 37, count 2 2006.201.05:43:46.74#ibcon#about to read 6, iclass 37, count 2 2006.201.05:43:46.74#ibcon#read 6, iclass 37, count 2 2006.201.05:43:46.74#ibcon#end of sib2, iclass 37, count 2 2006.201.05:43:46.74#ibcon#*after write, iclass 37, count 2 2006.201.05:43:46.74#ibcon#*before return 0, iclass 37, count 2 2006.201.05:43:46.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:46.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:46.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.05:43:46.74#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:46.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:46.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:46.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:46.86#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:43:46.86#ibcon#first serial, iclass 37, count 0 2006.201.05:43:46.86#ibcon#enter sib2, iclass 37, count 0 2006.201.05:43:46.86#ibcon#flushed, iclass 37, count 0 2006.201.05:43:46.86#ibcon#about to write, iclass 37, count 0 2006.201.05:43:46.86#ibcon#wrote, iclass 37, count 0 2006.201.05:43:46.86#ibcon#about to read 3, iclass 37, count 0 2006.201.05:43:46.88#ibcon#read 3, iclass 37, count 0 2006.201.05:43:46.88#ibcon#about to read 4, iclass 37, count 0 2006.201.05:43:46.88#ibcon#read 4, iclass 37, count 0 2006.201.05:43:46.88#ibcon#about to read 5, iclass 37, count 0 2006.201.05:43:46.88#ibcon#read 5, iclass 37, count 0 2006.201.05:43:46.88#ibcon#about to read 6, iclass 37, count 0 2006.201.05:43:46.88#ibcon#read 6, iclass 37, count 0 2006.201.05:43:46.88#ibcon#end of sib2, iclass 37, count 0 2006.201.05:43:46.88#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:43:46.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:43:46.88#ibcon#[25=USB\r\n] 2006.201.05:43:46.88#ibcon#*before write, iclass 37, count 0 2006.201.05:43:46.88#ibcon#enter sib2, iclass 37, count 0 2006.201.05:43:46.88#ibcon#flushed, iclass 37, count 0 2006.201.05:43:46.88#ibcon#about to write, iclass 37, count 0 2006.201.05:43:46.88#ibcon#wrote, iclass 37, count 0 2006.201.05:43:46.88#ibcon#about to read 3, iclass 37, count 0 2006.201.05:43:46.91#ibcon#read 3, iclass 37, count 0 2006.201.05:43:46.91#ibcon#about to read 4, iclass 37, count 0 2006.201.05:43:46.91#ibcon#read 4, iclass 37, count 0 2006.201.05:43:46.91#ibcon#about to read 5, iclass 37, count 0 2006.201.05:43:46.91#ibcon#read 5, iclass 37, count 0 2006.201.05:43:46.91#ibcon#about to read 6, iclass 37, count 0 2006.201.05:43:46.91#ibcon#read 6, iclass 37, count 0 2006.201.05:43:46.91#ibcon#end of sib2, iclass 37, count 0 2006.201.05:43:46.91#ibcon#*after write, iclass 37, count 0 2006.201.05:43:46.91#ibcon#*before return 0, iclass 37, count 0 2006.201.05:43:46.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:46.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:46.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:43:46.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:43:46.91$vck44/valo=3,564.99 2006.201.05:43:46.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.05:43:46.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.05:43:46.91#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:46.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:43:46.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:43:46.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:43:46.91#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:43:46.91#ibcon#first serial, iclass 40, count 0 2006.201.05:43:46.91#ibcon#enter sib2, iclass 40, count 0 2006.201.05:43:46.91#ibcon#flushed, iclass 40, count 0 2006.201.05:43:46.91#ibcon#about to write, iclass 40, count 0 2006.201.05:43:46.91#ibcon#wrote, iclass 40, count 0 2006.201.05:43:46.91#ibcon#about to read 3, iclass 40, count 0 2006.201.05:43:46.92#abcon#<5=/04 2.4 4.7 23.05 901003.6\r\n> 2006.201.05:43:46.93#ibcon#read 3, iclass 40, count 0 2006.201.05:43:46.93#ibcon#about to read 4, iclass 40, count 0 2006.201.05:43:46.93#ibcon#read 4, iclass 40, count 0 2006.201.05:43:46.93#ibcon#about to read 5, iclass 40, count 0 2006.201.05:43:46.93#ibcon#read 5, iclass 40, count 0 2006.201.05:43:46.93#ibcon#about to read 6, iclass 40, count 0 2006.201.05:43:46.93#ibcon#read 6, iclass 40, count 0 2006.201.05:43:46.93#ibcon#end of sib2, iclass 40, count 0 2006.201.05:43:46.93#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:43:46.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:43:46.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:43:46.93#ibcon#*before write, iclass 40, count 0 2006.201.05:43:46.93#ibcon#enter sib2, iclass 40, count 0 2006.201.05:43:46.93#ibcon#flushed, iclass 40, count 0 2006.201.05:43:46.93#ibcon#about to write, iclass 40, count 0 2006.201.05:43:46.93#ibcon#wrote, iclass 40, count 0 2006.201.05:43:46.93#ibcon#about to read 3, iclass 40, count 0 2006.201.05:43:46.94#abcon#{5=INTERFACE CLEAR} 2006.201.05:43:46.97#ibcon#read 3, iclass 40, count 0 2006.201.05:43:46.97#ibcon#about to read 4, iclass 40, count 0 2006.201.05:43:46.97#ibcon#read 4, iclass 40, count 0 2006.201.05:43:46.97#ibcon#about to read 5, iclass 40, count 0 2006.201.05:43:46.97#ibcon#read 5, iclass 40, count 0 2006.201.05:43:46.97#ibcon#about to read 6, iclass 40, count 0 2006.201.05:43:46.97#ibcon#read 6, iclass 40, count 0 2006.201.05:43:46.97#ibcon#end of sib2, iclass 40, count 0 2006.201.05:43:46.97#ibcon#*after write, iclass 40, count 0 2006.201.05:43:46.97#ibcon#*before return 0, iclass 40, count 0 2006.201.05:43:46.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:43:46.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:43:46.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:43:46.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:43:46.97$vck44/va=3,8 2006.201.05:43:46.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.05:43:46.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.05:43:46.97#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:46.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:43:47.00#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:43:47.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:43:47.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:43:47.03#ibcon#enter wrdev, iclass 6, count 2 2006.201.05:43:47.03#ibcon#first serial, iclass 6, count 2 2006.201.05:43:47.03#ibcon#enter sib2, iclass 6, count 2 2006.201.05:43:47.03#ibcon#flushed, iclass 6, count 2 2006.201.05:43:47.03#ibcon#about to write, iclass 6, count 2 2006.201.05:43:47.03#ibcon#wrote, iclass 6, count 2 2006.201.05:43:47.03#ibcon#about to read 3, iclass 6, count 2 2006.201.05:43:47.05#ibcon#read 3, iclass 6, count 2 2006.201.05:43:47.05#ibcon#about to read 4, iclass 6, count 2 2006.201.05:43:47.05#ibcon#read 4, iclass 6, count 2 2006.201.05:43:47.05#ibcon#about to read 5, iclass 6, count 2 2006.201.05:43:47.05#ibcon#read 5, iclass 6, count 2 2006.201.05:43:47.05#ibcon#about to read 6, iclass 6, count 2 2006.201.05:43:47.05#ibcon#read 6, iclass 6, count 2 2006.201.05:43:47.05#ibcon#end of sib2, iclass 6, count 2 2006.201.05:43:47.05#ibcon#*mode == 0, iclass 6, count 2 2006.201.05:43:47.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.05:43:47.05#ibcon#[25=AT03-08\r\n] 2006.201.05:43:47.05#ibcon#*before write, iclass 6, count 2 2006.201.05:43:47.05#ibcon#enter sib2, iclass 6, count 2 2006.201.05:43:47.05#ibcon#flushed, iclass 6, count 2 2006.201.05:43:47.05#ibcon#about to write, iclass 6, count 2 2006.201.05:43:47.05#ibcon#wrote, iclass 6, count 2 2006.201.05:43:47.05#ibcon#about to read 3, iclass 6, count 2 2006.201.05:43:47.08#ibcon#read 3, iclass 6, count 2 2006.201.05:43:47.08#ibcon#about to read 4, iclass 6, count 2 2006.201.05:43:47.08#ibcon#read 4, iclass 6, count 2 2006.201.05:43:47.08#ibcon#about to read 5, iclass 6, count 2 2006.201.05:43:47.08#ibcon#read 5, iclass 6, count 2 2006.201.05:43:47.08#ibcon#about to read 6, iclass 6, count 2 2006.201.05:43:47.08#ibcon#read 6, iclass 6, count 2 2006.201.05:43:47.08#ibcon#end of sib2, iclass 6, count 2 2006.201.05:43:47.08#ibcon#*after write, iclass 6, count 2 2006.201.05:43:47.08#ibcon#*before return 0, iclass 6, count 2 2006.201.05:43:47.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:43:47.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:43:47.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.05:43:47.08#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:47.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:43:47.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:43:47.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:43:47.20#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:43:47.20#ibcon#first serial, iclass 6, count 0 2006.201.05:43:47.20#ibcon#enter sib2, iclass 6, count 0 2006.201.05:43:47.20#ibcon#flushed, iclass 6, count 0 2006.201.05:43:47.20#ibcon#about to write, iclass 6, count 0 2006.201.05:43:47.20#ibcon#wrote, iclass 6, count 0 2006.201.05:43:47.20#ibcon#about to read 3, iclass 6, count 0 2006.201.05:43:47.22#ibcon#read 3, iclass 6, count 0 2006.201.05:43:47.22#ibcon#about to read 4, iclass 6, count 0 2006.201.05:43:47.22#ibcon#read 4, iclass 6, count 0 2006.201.05:43:47.22#ibcon#about to read 5, iclass 6, count 0 2006.201.05:43:47.22#ibcon#read 5, iclass 6, count 0 2006.201.05:43:47.22#ibcon#about to read 6, iclass 6, count 0 2006.201.05:43:47.22#ibcon#read 6, iclass 6, count 0 2006.201.05:43:47.22#ibcon#end of sib2, iclass 6, count 0 2006.201.05:43:47.22#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:43:47.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:43:47.22#ibcon#[25=USB\r\n] 2006.201.05:43:47.22#ibcon#*before write, iclass 6, count 0 2006.201.05:43:47.22#ibcon#enter sib2, iclass 6, count 0 2006.201.05:43:47.22#ibcon#flushed, iclass 6, count 0 2006.201.05:43:47.22#ibcon#about to write, iclass 6, count 0 2006.201.05:43:47.22#ibcon#wrote, iclass 6, count 0 2006.201.05:43:47.22#ibcon#about to read 3, iclass 6, count 0 2006.201.05:43:47.25#ibcon#read 3, iclass 6, count 0 2006.201.05:43:47.25#ibcon#about to read 4, iclass 6, count 0 2006.201.05:43:47.25#ibcon#read 4, iclass 6, count 0 2006.201.05:43:47.25#ibcon#about to read 5, iclass 6, count 0 2006.201.05:43:47.25#ibcon#read 5, iclass 6, count 0 2006.201.05:43:47.25#ibcon#about to read 6, iclass 6, count 0 2006.201.05:43:47.25#ibcon#read 6, iclass 6, count 0 2006.201.05:43:47.25#ibcon#end of sib2, iclass 6, count 0 2006.201.05:43:47.25#ibcon#*after write, iclass 6, count 0 2006.201.05:43:47.25#ibcon#*before return 0, iclass 6, count 0 2006.201.05:43:47.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:43:47.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:43:47.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:43:47.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:43:47.25$vck44/valo=4,624.99 2006.201.05:43:47.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.05:43:47.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.05:43:47.25#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:47.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:47.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:47.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:47.25#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:43:47.25#ibcon#first serial, iclass 11, count 0 2006.201.05:43:47.25#ibcon#enter sib2, iclass 11, count 0 2006.201.05:43:47.25#ibcon#flushed, iclass 11, count 0 2006.201.05:43:47.25#ibcon#about to write, iclass 11, count 0 2006.201.05:43:47.25#ibcon#wrote, iclass 11, count 0 2006.201.05:43:47.25#ibcon#about to read 3, iclass 11, count 0 2006.201.05:43:47.27#ibcon#read 3, iclass 11, count 0 2006.201.05:43:47.27#ibcon#about to read 4, iclass 11, count 0 2006.201.05:43:47.27#ibcon#read 4, iclass 11, count 0 2006.201.05:43:47.27#ibcon#about to read 5, iclass 11, count 0 2006.201.05:43:47.27#ibcon#read 5, iclass 11, count 0 2006.201.05:43:47.27#ibcon#about to read 6, iclass 11, count 0 2006.201.05:43:47.27#ibcon#read 6, iclass 11, count 0 2006.201.05:43:47.27#ibcon#end of sib2, iclass 11, count 0 2006.201.05:43:47.27#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:43:47.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:43:47.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:43:47.27#ibcon#*before write, iclass 11, count 0 2006.201.05:43:47.27#ibcon#enter sib2, iclass 11, count 0 2006.201.05:43:47.27#ibcon#flushed, iclass 11, count 0 2006.201.05:43:47.27#ibcon#about to write, iclass 11, count 0 2006.201.05:43:47.27#ibcon#wrote, iclass 11, count 0 2006.201.05:43:47.27#ibcon#about to read 3, iclass 11, count 0 2006.201.05:43:47.31#ibcon#read 3, iclass 11, count 0 2006.201.05:43:47.31#ibcon#about to read 4, iclass 11, count 0 2006.201.05:43:47.31#ibcon#read 4, iclass 11, count 0 2006.201.05:43:47.31#ibcon#about to read 5, iclass 11, count 0 2006.201.05:43:47.31#ibcon#read 5, iclass 11, count 0 2006.201.05:43:47.31#ibcon#about to read 6, iclass 11, count 0 2006.201.05:43:47.31#ibcon#read 6, iclass 11, count 0 2006.201.05:43:47.31#ibcon#end of sib2, iclass 11, count 0 2006.201.05:43:47.31#ibcon#*after write, iclass 11, count 0 2006.201.05:43:47.31#ibcon#*before return 0, iclass 11, count 0 2006.201.05:43:47.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:47.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:47.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:43:47.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:43:47.31$vck44/va=4,7 2006.201.05:43:47.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.05:43:47.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.05:43:47.31#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:47.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:47.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:47.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:47.37#ibcon#enter wrdev, iclass 13, count 2 2006.201.05:43:47.37#ibcon#first serial, iclass 13, count 2 2006.201.05:43:47.37#ibcon#enter sib2, iclass 13, count 2 2006.201.05:43:47.37#ibcon#flushed, iclass 13, count 2 2006.201.05:43:47.37#ibcon#about to write, iclass 13, count 2 2006.201.05:43:47.37#ibcon#wrote, iclass 13, count 2 2006.201.05:43:47.37#ibcon#about to read 3, iclass 13, count 2 2006.201.05:43:47.39#ibcon#read 3, iclass 13, count 2 2006.201.05:43:47.39#ibcon#about to read 4, iclass 13, count 2 2006.201.05:43:47.39#ibcon#read 4, iclass 13, count 2 2006.201.05:43:47.39#ibcon#about to read 5, iclass 13, count 2 2006.201.05:43:47.39#ibcon#read 5, iclass 13, count 2 2006.201.05:43:47.39#ibcon#about to read 6, iclass 13, count 2 2006.201.05:43:47.39#ibcon#read 6, iclass 13, count 2 2006.201.05:43:47.39#ibcon#end of sib2, iclass 13, count 2 2006.201.05:43:47.39#ibcon#*mode == 0, iclass 13, count 2 2006.201.05:43:47.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.05:43:47.39#ibcon#[25=AT04-07\r\n] 2006.201.05:43:47.39#ibcon#*before write, iclass 13, count 2 2006.201.05:43:47.39#ibcon#enter sib2, iclass 13, count 2 2006.201.05:43:47.39#ibcon#flushed, iclass 13, count 2 2006.201.05:43:47.39#ibcon#about to write, iclass 13, count 2 2006.201.05:43:47.39#ibcon#wrote, iclass 13, count 2 2006.201.05:43:47.47#ibcon#about to read 3, iclass 13, count 2 2006.201.05:43:47.48#ibcon#read 3, iclass 13, count 2 2006.201.05:43:47.48#ibcon#about to read 4, iclass 13, count 2 2006.201.05:43:47.48#ibcon#read 4, iclass 13, count 2 2006.201.05:43:47.48#ibcon#about to read 5, iclass 13, count 2 2006.201.05:43:47.48#ibcon#read 5, iclass 13, count 2 2006.201.05:43:47.48#ibcon#about to read 6, iclass 13, count 2 2006.201.05:43:47.48#ibcon#read 6, iclass 13, count 2 2006.201.05:43:47.48#ibcon#end of sib2, iclass 13, count 2 2006.201.05:43:47.48#ibcon#*after write, iclass 13, count 2 2006.201.05:43:47.48#ibcon#*before return 0, iclass 13, count 2 2006.201.05:43:47.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:47.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:47.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.05:43:47.48#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:47.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:47.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:47.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:47.60#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:43:47.60#ibcon#first serial, iclass 13, count 0 2006.201.05:43:47.60#ibcon#enter sib2, iclass 13, count 0 2006.201.05:43:47.60#ibcon#flushed, iclass 13, count 0 2006.201.05:43:47.60#ibcon#about to write, iclass 13, count 0 2006.201.05:43:47.60#ibcon#wrote, iclass 13, count 0 2006.201.05:43:47.60#ibcon#about to read 3, iclass 13, count 0 2006.201.05:43:47.62#ibcon#read 3, iclass 13, count 0 2006.201.05:43:47.62#ibcon#about to read 4, iclass 13, count 0 2006.201.05:43:47.62#ibcon#read 4, iclass 13, count 0 2006.201.05:43:47.62#ibcon#about to read 5, iclass 13, count 0 2006.201.05:43:47.62#ibcon#read 5, iclass 13, count 0 2006.201.05:43:47.62#ibcon#about to read 6, iclass 13, count 0 2006.201.05:43:47.62#ibcon#read 6, iclass 13, count 0 2006.201.05:43:47.62#ibcon#end of sib2, iclass 13, count 0 2006.201.05:43:47.62#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:43:47.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:43:47.62#ibcon#[25=USB\r\n] 2006.201.05:43:47.62#ibcon#*before write, iclass 13, count 0 2006.201.05:43:47.62#ibcon#enter sib2, iclass 13, count 0 2006.201.05:43:47.62#ibcon#flushed, iclass 13, count 0 2006.201.05:43:47.62#ibcon#about to write, iclass 13, count 0 2006.201.05:43:47.62#ibcon#wrote, iclass 13, count 0 2006.201.05:43:47.62#ibcon#about to read 3, iclass 13, count 0 2006.201.05:43:47.65#ibcon#read 3, iclass 13, count 0 2006.201.05:43:47.65#ibcon#about to read 4, iclass 13, count 0 2006.201.05:43:47.65#ibcon#read 4, iclass 13, count 0 2006.201.05:43:47.65#ibcon#about to read 5, iclass 13, count 0 2006.201.05:43:47.65#ibcon#read 5, iclass 13, count 0 2006.201.05:43:47.65#ibcon#about to read 6, iclass 13, count 0 2006.201.05:43:47.65#ibcon#read 6, iclass 13, count 0 2006.201.05:43:47.65#ibcon#end of sib2, iclass 13, count 0 2006.201.05:43:47.65#ibcon#*after write, iclass 13, count 0 2006.201.05:43:47.65#ibcon#*before return 0, iclass 13, count 0 2006.201.05:43:47.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:47.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:47.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:43:47.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:43:47.65$vck44/valo=5,734.99 2006.201.05:43:47.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.05:43:47.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.05:43:47.65#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:47.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:47.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:47.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:47.65#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:43:47.65#ibcon#first serial, iclass 15, count 0 2006.201.05:43:47.65#ibcon#enter sib2, iclass 15, count 0 2006.201.05:43:47.65#ibcon#flushed, iclass 15, count 0 2006.201.05:43:47.65#ibcon#about to write, iclass 15, count 0 2006.201.05:43:47.65#ibcon#wrote, iclass 15, count 0 2006.201.05:43:47.65#ibcon#about to read 3, iclass 15, count 0 2006.201.05:43:47.67#ibcon#read 3, iclass 15, count 0 2006.201.05:43:47.67#ibcon#about to read 4, iclass 15, count 0 2006.201.05:43:47.67#ibcon#read 4, iclass 15, count 0 2006.201.05:43:47.67#ibcon#about to read 5, iclass 15, count 0 2006.201.05:43:47.67#ibcon#read 5, iclass 15, count 0 2006.201.05:43:47.67#ibcon#about to read 6, iclass 15, count 0 2006.201.05:43:47.67#ibcon#read 6, iclass 15, count 0 2006.201.05:43:47.67#ibcon#end of sib2, iclass 15, count 0 2006.201.05:43:47.67#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:43:47.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:43:47.67#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:43:47.67#ibcon#*before write, iclass 15, count 0 2006.201.05:43:47.67#ibcon#enter sib2, iclass 15, count 0 2006.201.05:43:47.67#ibcon#flushed, iclass 15, count 0 2006.201.05:43:47.67#ibcon#about to write, iclass 15, count 0 2006.201.05:43:47.67#ibcon#wrote, iclass 15, count 0 2006.201.05:43:47.67#ibcon#about to read 3, iclass 15, count 0 2006.201.05:43:47.71#ibcon#read 3, iclass 15, count 0 2006.201.05:43:47.71#ibcon#about to read 4, iclass 15, count 0 2006.201.05:43:47.71#ibcon#read 4, iclass 15, count 0 2006.201.05:43:47.71#ibcon#about to read 5, iclass 15, count 0 2006.201.05:43:47.71#ibcon#read 5, iclass 15, count 0 2006.201.05:43:47.71#ibcon#about to read 6, iclass 15, count 0 2006.201.05:43:47.71#ibcon#read 6, iclass 15, count 0 2006.201.05:43:47.71#ibcon#end of sib2, iclass 15, count 0 2006.201.05:43:47.71#ibcon#*after write, iclass 15, count 0 2006.201.05:43:47.71#ibcon#*before return 0, iclass 15, count 0 2006.201.05:43:47.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:47.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:47.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:43:47.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:43:47.71$vck44/va=5,4 2006.201.05:43:47.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.05:43:47.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.05:43:47.71#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:47.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:47.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:47.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:47.77#ibcon#enter wrdev, iclass 17, count 2 2006.201.05:43:47.77#ibcon#first serial, iclass 17, count 2 2006.201.05:43:47.77#ibcon#enter sib2, iclass 17, count 2 2006.201.05:43:47.77#ibcon#flushed, iclass 17, count 2 2006.201.05:43:47.77#ibcon#about to write, iclass 17, count 2 2006.201.05:43:47.77#ibcon#wrote, iclass 17, count 2 2006.201.05:43:47.77#ibcon#about to read 3, iclass 17, count 2 2006.201.05:43:47.79#ibcon#read 3, iclass 17, count 2 2006.201.05:43:47.79#ibcon#about to read 4, iclass 17, count 2 2006.201.05:43:47.79#ibcon#read 4, iclass 17, count 2 2006.201.05:43:47.79#ibcon#about to read 5, iclass 17, count 2 2006.201.05:43:47.79#ibcon#read 5, iclass 17, count 2 2006.201.05:43:47.79#ibcon#about to read 6, iclass 17, count 2 2006.201.05:43:47.79#ibcon#read 6, iclass 17, count 2 2006.201.05:43:47.79#ibcon#end of sib2, iclass 17, count 2 2006.201.05:43:47.79#ibcon#*mode == 0, iclass 17, count 2 2006.201.05:43:47.79#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.05:43:47.79#ibcon#[25=AT05-04\r\n] 2006.201.05:43:47.79#ibcon#*before write, iclass 17, count 2 2006.201.05:43:47.79#ibcon#enter sib2, iclass 17, count 2 2006.201.05:43:47.79#ibcon#flushed, iclass 17, count 2 2006.201.05:43:47.79#ibcon#about to write, iclass 17, count 2 2006.201.05:43:47.79#ibcon#wrote, iclass 17, count 2 2006.201.05:43:47.79#ibcon#about to read 3, iclass 17, count 2 2006.201.05:43:47.82#ibcon#read 3, iclass 17, count 2 2006.201.05:43:47.82#ibcon#about to read 4, iclass 17, count 2 2006.201.05:43:47.82#ibcon#read 4, iclass 17, count 2 2006.201.05:43:47.82#ibcon#about to read 5, iclass 17, count 2 2006.201.05:43:47.82#ibcon#read 5, iclass 17, count 2 2006.201.05:43:47.82#ibcon#about to read 6, iclass 17, count 2 2006.201.05:43:47.82#ibcon#read 6, iclass 17, count 2 2006.201.05:43:47.82#ibcon#end of sib2, iclass 17, count 2 2006.201.05:43:47.82#ibcon#*after write, iclass 17, count 2 2006.201.05:43:47.82#ibcon#*before return 0, iclass 17, count 2 2006.201.05:43:47.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:47.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:47.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.05:43:47.82#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:47.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:47.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:47.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:47.94#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:43:47.94#ibcon#first serial, iclass 17, count 0 2006.201.05:43:47.94#ibcon#enter sib2, iclass 17, count 0 2006.201.05:43:47.94#ibcon#flushed, iclass 17, count 0 2006.201.05:43:47.94#ibcon#about to write, iclass 17, count 0 2006.201.05:43:47.94#ibcon#wrote, iclass 17, count 0 2006.201.05:43:47.94#ibcon#about to read 3, iclass 17, count 0 2006.201.05:43:47.96#ibcon#read 3, iclass 17, count 0 2006.201.05:43:47.96#ibcon#about to read 4, iclass 17, count 0 2006.201.05:43:47.96#ibcon#read 4, iclass 17, count 0 2006.201.05:43:47.96#ibcon#about to read 5, iclass 17, count 0 2006.201.05:43:47.96#ibcon#read 5, iclass 17, count 0 2006.201.05:43:47.96#ibcon#about to read 6, iclass 17, count 0 2006.201.05:43:47.96#ibcon#read 6, iclass 17, count 0 2006.201.05:43:47.96#ibcon#end of sib2, iclass 17, count 0 2006.201.05:43:47.96#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:43:47.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:43:47.96#ibcon#[25=USB\r\n] 2006.201.05:43:47.96#ibcon#*before write, iclass 17, count 0 2006.201.05:43:47.96#ibcon#enter sib2, iclass 17, count 0 2006.201.05:43:47.96#ibcon#flushed, iclass 17, count 0 2006.201.05:43:47.96#ibcon#about to write, iclass 17, count 0 2006.201.05:43:47.96#ibcon#wrote, iclass 17, count 0 2006.201.05:43:47.96#ibcon#about to read 3, iclass 17, count 0 2006.201.05:43:47.99#ibcon#read 3, iclass 17, count 0 2006.201.05:43:47.99#ibcon#about to read 4, iclass 17, count 0 2006.201.05:43:47.99#ibcon#read 4, iclass 17, count 0 2006.201.05:43:47.99#ibcon#about to read 5, iclass 17, count 0 2006.201.05:43:47.99#ibcon#read 5, iclass 17, count 0 2006.201.05:43:47.99#ibcon#about to read 6, iclass 17, count 0 2006.201.05:43:47.99#ibcon#read 6, iclass 17, count 0 2006.201.05:43:47.99#ibcon#end of sib2, iclass 17, count 0 2006.201.05:43:47.99#ibcon#*after write, iclass 17, count 0 2006.201.05:43:47.99#ibcon#*before return 0, iclass 17, count 0 2006.201.05:43:47.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:47.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:47.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:43:47.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:43:47.99$vck44/valo=6,814.99 2006.201.05:43:47.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.05:43:47.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.05:43:47.99#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:47.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:47.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:47.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:47.99#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:43:47.99#ibcon#first serial, iclass 19, count 0 2006.201.05:43:47.99#ibcon#enter sib2, iclass 19, count 0 2006.201.05:43:47.99#ibcon#flushed, iclass 19, count 0 2006.201.05:43:47.99#ibcon#about to write, iclass 19, count 0 2006.201.05:43:47.99#ibcon#wrote, iclass 19, count 0 2006.201.05:43:47.99#ibcon#about to read 3, iclass 19, count 0 2006.201.05:43:48.01#ibcon#read 3, iclass 19, count 0 2006.201.05:43:48.01#ibcon#about to read 4, iclass 19, count 0 2006.201.05:43:48.01#ibcon#read 4, iclass 19, count 0 2006.201.05:43:48.01#ibcon#about to read 5, iclass 19, count 0 2006.201.05:43:48.01#ibcon#read 5, iclass 19, count 0 2006.201.05:43:48.01#ibcon#about to read 6, iclass 19, count 0 2006.201.05:43:48.01#ibcon#read 6, iclass 19, count 0 2006.201.05:43:48.01#ibcon#end of sib2, iclass 19, count 0 2006.201.05:43:48.01#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:43:48.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:43:48.01#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:43:48.01#ibcon#*before write, iclass 19, count 0 2006.201.05:43:48.01#ibcon#enter sib2, iclass 19, count 0 2006.201.05:43:48.01#ibcon#flushed, iclass 19, count 0 2006.201.05:43:48.01#ibcon#about to write, iclass 19, count 0 2006.201.05:43:48.01#ibcon#wrote, iclass 19, count 0 2006.201.05:43:48.01#ibcon#about to read 3, iclass 19, count 0 2006.201.05:43:48.05#ibcon#read 3, iclass 19, count 0 2006.201.05:43:48.05#ibcon#about to read 4, iclass 19, count 0 2006.201.05:43:48.05#ibcon#read 4, iclass 19, count 0 2006.201.05:43:48.05#ibcon#about to read 5, iclass 19, count 0 2006.201.05:43:48.05#ibcon#read 5, iclass 19, count 0 2006.201.05:43:48.05#ibcon#about to read 6, iclass 19, count 0 2006.201.05:43:48.05#ibcon#read 6, iclass 19, count 0 2006.201.05:43:48.05#ibcon#end of sib2, iclass 19, count 0 2006.201.05:43:48.05#ibcon#*after write, iclass 19, count 0 2006.201.05:43:48.05#ibcon#*before return 0, iclass 19, count 0 2006.201.05:43:48.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:48.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:48.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:43:48.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:43:48.05$vck44/va=6,5 2006.201.05:43:48.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.05:43:48.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.05:43:48.05#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:48.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:48.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:48.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:48.11#ibcon#enter wrdev, iclass 21, count 2 2006.201.05:43:48.11#ibcon#first serial, iclass 21, count 2 2006.201.05:43:48.11#ibcon#enter sib2, iclass 21, count 2 2006.201.05:43:48.11#ibcon#flushed, iclass 21, count 2 2006.201.05:43:48.11#ibcon#about to write, iclass 21, count 2 2006.201.05:43:48.11#ibcon#wrote, iclass 21, count 2 2006.201.05:43:48.11#ibcon#about to read 3, iclass 21, count 2 2006.201.05:43:48.13#ibcon#read 3, iclass 21, count 2 2006.201.05:43:48.13#ibcon#about to read 4, iclass 21, count 2 2006.201.05:43:48.13#ibcon#read 4, iclass 21, count 2 2006.201.05:43:48.13#ibcon#about to read 5, iclass 21, count 2 2006.201.05:43:48.13#ibcon#read 5, iclass 21, count 2 2006.201.05:43:48.13#ibcon#about to read 6, iclass 21, count 2 2006.201.05:43:48.13#ibcon#read 6, iclass 21, count 2 2006.201.05:43:48.13#ibcon#end of sib2, iclass 21, count 2 2006.201.05:43:48.13#ibcon#*mode == 0, iclass 21, count 2 2006.201.05:43:48.13#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.05:43:48.13#ibcon#[25=AT06-05\r\n] 2006.201.05:43:48.13#ibcon#*before write, iclass 21, count 2 2006.201.05:43:48.13#ibcon#enter sib2, iclass 21, count 2 2006.201.05:43:48.13#ibcon#flushed, iclass 21, count 2 2006.201.05:43:48.13#ibcon#about to write, iclass 21, count 2 2006.201.05:43:48.13#ibcon#wrote, iclass 21, count 2 2006.201.05:43:48.13#ibcon#about to read 3, iclass 21, count 2 2006.201.05:43:48.16#ibcon#read 3, iclass 21, count 2 2006.201.05:43:48.16#ibcon#about to read 4, iclass 21, count 2 2006.201.05:43:48.16#ibcon#read 4, iclass 21, count 2 2006.201.05:43:48.16#ibcon#about to read 5, iclass 21, count 2 2006.201.05:43:48.16#ibcon#read 5, iclass 21, count 2 2006.201.05:43:48.16#ibcon#about to read 6, iclass 21, count 2 2006.201.05:43:48.16#ibcon#read 6, iclass 21, count 2 2006.201.05:43:48.16#ibcon#end of sib2, iclass 21, count 2 2006.201.05:43:48.16#ibcon#*after write, iclass 21, count 2 2006.201.05:43:48.16#ibcon#*before return 0, iclass 21, count 2 2006.201.05:43:48.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:48.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:48.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.05:43:48.16#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:48.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:48.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:48.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:48.28#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:43:48.28#ibcon#first serial, iclass 21, count 0 2006.201.05:43:48.28#ibcon#enter sib2, iclass 21, count 0 2006.201.05:43:48.28#ibcon#flushed, iclass 21, count 0 2006.201.05:43:48.28#ibcon#about to write, iclass 21, count 0 2006.201.05:43:48.28#ibcon#wrote, iclass 21, count 0 2006.201.05:43:48.28#ibcon#about to read 3, iclass 21, count 0 2006.201.05:43:48.30#ibcon#read 3, iclass 21, count 0 2006.201.05:43:48.30#ibcon#about to read 4, iclass 21, count 0 2006.201.05:43:48.30#ibcon#read 4, iclass 21, count 0 2006.201.05:43:48.30#ibcon#about to read 5, iclass 21, count 0 2006.201.05:43:48.30#ibcon#read 5, iclass 21, count 0 2006.201.05:43:48.30#ibcon#about to read 6, iclass 21, count 0 2006.201.05:43:48.30#ibcon#read 6, iclass 21, count 0 2006.201.05:43:48.30#ibcon#end of sib2, iclass 21, count 0 2006.201.05:43:48.30#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:43:48.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:43:48.30#ibcon#[25=USB\r\n] 2006.201.05:43:48.30#ibcon#*before write, iclass 21, count 0 2006.201.05:43:48.30#ibcon#enter sib2, iclass 21, count 0 2006.201.05:43:48.30#ibcon#flushed, iclass 21, count 0 2006.201.05:43:48.30#ibcon#about to write, iclass 21, count 0 2006.201.05:43:48.30#ibcon#wrote, iclass 21, count 0 2006.201.05:43:48.30#ibcon#about to read 3, iclass 21, count 0 2006.201.05:43:48.33#ibcon#read 3, iclass 21, count 0 2006.201.05:43:48.33#ibcon#about to read 4, iclass 21, count 0 2006.201.05:43:48.33#ibcon#read 4, iclass 21, count 0 2006.201.05:43:48.33#ibcon#about to read 5, iclass 21, count 0 2006.201.05:43:48.33#ibcon#read 5, iclass 21, count 0 2006.201.05:43:48.33#ibcon#about to read 6, iclass 21, count 0 2006.201.05:43:48.33#ibcon#read 6, iclass 21, count 0 2006.201.05:43:48.33#ibcon#end of sib2, iclass 21, count 0 2006.201.05:43:48.33#ibcon#*after write, iclass 21, count 0 2006.201.05:43:48.33#ibcon#*before return 0, iclass 21, count 0 2006.201.05:43:48.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:48.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:48.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:43:48.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:43:48.33$vck44/valo=7,864.99 2006.201.05:43:48.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.05:43:48.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.05:43:48.33#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:48.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:48.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:48.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:48.33#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:43:48.33#ibcon#first serial, iclass 23, count 0 2006.201.05:43:48.33#ibcon#enter sib2, iclass 23, count 0 2006.201.05:43:48.33#ibcon#flushed, iclass 23, count 0 2006.201.05:43:48.33#ibcon#about to write, iclass 23, count 0 2006.201.05:43:48.33#ibcon#wrote, iclass 23, count 0 2006.201.05:43:48.33#ibcon#about to read 3, iclass 23, count 0 2006.201.05:43:48.35#ibcon#read 3, iclass 23, count 0 2006.201.05:43:48.35#ibcon#about to read 4, iclass 23, count 0 2006.201.05:43:48.35#ibcon#read 4, iclass 23, count 0 2006.201.05:43:48.35#ibcon#about to read 5, iclass 23, count 0 2006.201.05:43:48.35#ibcon#read 5, iclass 23, count 0 2006.201.05:43:48.35#ibcon#about to read 6, iclass 23, count 0 2006.201.05:43:48.35#ibcon#read 6, iclass 23, count 0 2006.201.05:43:48.35#ibcon#end of sib2, iclass 23, count 0 2006.201.05:43:48.35#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:43:48.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:43:48.35#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:43:48.35#ibcon#*before write, iclass 23, count 0 2006.201.05:43:48.35#ibcon#enter sib2, iclass 23, count 0 2006.201.05:43:48.35#ibcon#flushed, iclass 23, count 0 2006.201.05:43:48.35#ibcon#about to write, iclass 23, count 0 2006.201.05:43:48.35#ibcon#wrote, iclass 23, count 0 2006.201.05:43:48.35#ibcon#about to read 3, iclass 23, count 0 2006.201.05:43:48.39#ibcon#read 3, iclass 23, count 0 2006.201.05:43:48.39#ibcon#about to read 4, iclass 23, count 0 2006.201.05:43:48.39#ibcon#read 4, iclass 23, count 0 2006.201.05:43:48.39#ibcon#about to read 5, iclass 23, count 0 2006.201.05:43:48.39#ibcon#read 5, iclass 23, count 0 2006.201.05:43:48.39#ibcon#about to read 6, iclass 23, count 0 2006.201.05:43:48.39#ibcon#read 6, iclass 23, count 0 2006.201.05:43:48.39#ibcon#end of sib2, iclass 23, count 0 2006.201.05:43:48.39#ibcon#*after write, iclass 23, count 0 2006.201.05:43:48.39#ibcon#*before return 0, iclass 23, count 0 2006.201.05:43:48.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:48.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:48.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:43:48.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:43:48.39$vck44/va=7,5 2006.201.05:43:48.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.05:43:48.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.05:43:48.39#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:48.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:48.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:48.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:48.45#ibcon#enter wrdev, iclass 25, count 2 2006.201.05:43:48.45#ibcon#first serial, iclass 25, count 2 2006.201.05:43:48.45#ibcon#enter sib2, iclass 25, count 2 2006.201.05:43:48.45#ibcon#flushed, iclass 25, count 2 2006.201.05:43:48.45#ibcon#about to write, iclass 25, count 2 2006.201.05:43:48.45#ibcon#wrote, iclass 25, count 2 2006.201.05:43:48.45#ibcon#about to read 3, iclass 25, count 2 2006.201.05:43:48.47#ibcon#read 3, iclass 25, count 2 2006.201.05:43:48.47#ibcon#about to read 4, iclass 25, count 2 2006.201.05:43:48.47#ibcon#read 4, iclass 25, count 2 2006.201.05:43:48.47#ibcon#about to read 5, iclass 25, count 2 2006.201.05:43:48.47#ibcon#read 5, iclass 25, count 2 2006.201.05:43:48.47#ibcon#about to read 6, iclass 25, count 2 2006.201.05:43:48.47#ibcon#read 6, iclass 25, count 2 2006.201.05:43:48.47#ibcon#end of sib2, iclass 25, count 2 2006.201.05:43:48.47#ibcon#*mode == 0, iclass 25, count 2 2006.201.05:43:48.47#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.05:43:48.47#ibcon#[25=AT07-05\r\n] 2006.201.05:43:48.47#ibcon#*before write, iclass 25, count 2 2006.201.05:43:48.47#ibcon#enter sib2, iclass 25, count 2 2006.201.05:43:48.47#ibcon#flushed, iclass 25, count 2 2006.201.05:43:48.47#ibcon#about to write, iclass 25, count 2 2006.201.05:43:48.47#ibcon#wrote, iclass 25, count 2 2006.201.05:43:48.47#ibcon#about to read 3, iclass 25, count 2 2006.201.05:43:48.50#ibcon#read 3, iclass 25, count 2 2006.201.05:43:48.50#ibcon#about to read 4, iclass 25, count 2 2006.201.05:43:48.50#ibcon#read 4, iclass 25, count 2 2006.201.05:43:48.50#ibcon#about to read 5, iclass 25, count 2 2006.201.05:43:48.50#ibcon#read 5, iclass 25, count 2 2006.201.05:43:48.50#ibcon#about to read 6, iclass 25, count 2 2006.201.05:43:48.50#ibcon#read 6, iclass 25, count 2 2006.201.05:43:48.50#ibcon#end of sib2, iclass 25, count 2 2006.201.05:43:48.50#ibcon#*after write, iclass 25, count 2 2006.201.05:43:48.50#ibcon#*before return 0, iclass 25, count 2 2006.201.05:43:48.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:48.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:48.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.05:43:48.50#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:48.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:48.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:48.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:48.62#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:43:48.62#ibcon#first serial, iclass 25, count 0 2006.201.05:43:48.62#ibcon#enter sib2, iclass 25, count 0 2006.201.05:43:48.62#ibcon#flushed, iclass 25, count 0 2006.201.05:43:48.62#ibcon#about to write, iclass 25, count 0 2006.201.05:43:48.62#ibcon#wrote, iclass 25, count 0 2006.201.05:43:48.62#ibcon#about to read 3, iclass 25, count 0 2006.201.05:43:48.64#ibcon#read 3, iclass 25, count 0 2006.201.05:43:48.64#ibcon#about to read 4, iclass 25, count 0 2006.201.05:43:48.64#ibcon#read 4, iclass 25, count 0 2006.201.05:43:48.64#ibcon#about to read 5, iclass 25, count 0 2006.201.05:43:48.64#ibcon#read 5, iclass 25, count 0 2006.201.05:43:48.64#ibcon#about to read 6, iclass 25, count 0 2006.201.05:43:48.64#ibcon#read 6, iclass 25, count 0 2006.201.05:43:48.64#ibcon#end of sib2, iclass 25, count 0 2006.201.05:43:48.64#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:43:48.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:43:48.64#ibcon#[25=USB\r\n] 2006.201.05:43:48.64#ibcon#*before write, iclass 25, count 0 2006.201.05:43:48.64#ibcon#enter sib2, iclass 25, count 0 2006.201.05:43:48.64#ibcon#flushed, iclass 25, count 0 2006.201.05:43:48.64#ibcon#about to write, iclass 25, count 0 2006.201.05:43:48.64#ibcon#wrote, iclass 25, count 0 2006.201.05:43:48.64#ibcon#about to read 3, iclass 25, count 0 2006.201.05:43:48.67#ibcon#read 3, iclass 25, count 0 2006.201.05:43:48.67#ibcon#about to read 4, iclass 25, count 0 2006.201.05:43:48.67#ibcon#read 4, iclass 25, count 0 2006.201.05:43:48.67#ibcon#about to read 5, iclass 25, count 0 2006.201.05:43:48.67#ibcon#read 5, iclass 25, count 0 2006.201.05:43:48.67#ibcon#about to read 6, iclass 25, count 0 2006.201.05:43:48.67#ibcon#read 6, iclass 25, count 0 2006.201.05:43:48.67#ibcon#end of sib2, iclass 25, count 0 2006.201.05:43:48.67#ibcon#*after write, iclass 25, count 0 2006.201.05:43:48.67#ibcon#*before return 0, iclass 25, count 0 2006.201.05:43:48.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:48.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:48.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:43:48.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:43:48.67$vck44/valo=8,884.99 2006.201.05:43:48.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.05:43:48.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.05:43:48.67#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:48.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:48.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:48.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:48.67#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:43:48.67#ibcon#first serial, iclass 27, count 0 2006.201.05:43:48.67#ibcon#enter sib2, iclass 27, count 0 2006.201.05:43:48.67#ibcon#flushed, iclass 27, count 0 2006.201.05:43:48.67#ibcon#about to write, iclass 27, count 0 2006.201.05:43:48.67#ibcon#wrote, iclass 27, count 0 2006.201.05:43:48.67#ibcon#about to read 3, iclass 27, count 0 2006.201.05:43:48.69#ibcon#read 3, iclass 27, count 0 2006.201.05:43:48.69#ibcon#about to read 4, iclass 27, count 0 2006.201.05:43:48.69#ibcon#read 4, iclass 27, count 0 2006.201.05:43:48.69#ibcon#about to read 5, iclass 27, count 0 2006.201.05:43:48.69#ibcon#read 5, iclass 27, count 0 2006.201.05:43:48.69#ibcon#about to read 6, iclass 27, count 0 2006.201.05:43:48.69#ibcon#read 6, iclass 27, count 0 2006.201.05:43:48.69#ibcon#end of sib2, iclass 27, count 0 2006.201.05:43:48.69#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:43:48.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:43:48.69#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:43:48.69#ibcon#*before write, iclass 27, count 0 2006.201.05:43:48.69#ibcon#enter sib2, iclass 27, count 0 2006.201.05:43:48.69#ibcon#flushed, iclass 27, count 0 2006.201.05:43:48.69#ibcon#about to write, iclass 27, count 0 2006.201.05:43:48.69#ibcon#wrote, iclass 27, count 0 2006.201.05:43:48.69#ibcon#about to read 3, iclass 27, count 0 2006.201.05:43:48.73#ibcon#read 3, iclass 27, count 0 2006.201.05:43:48.73#ibcon#about to read 4, iclass 27, count 0 2006.201.05:43:48.73#ibcon#read 4, iclass 27, count 0 2006.201.05:43:48.73#ibcon#about to read 5, iclass 27, count 0 2006.201.05:43:48.73#ibcon#read 5, iclass 27, count 0 2006.201.05:43:48.73#ibcon#about to read 6, iclass 27, count 0 2006.201.05:43:48.73#ibcon#read 6, iclass 27, count 0 2006.201.05:43:48.73#ibcon#end of sib2, iclass 27, count 0 2006.201.05:43:48.73#ibcon#*after write, iclass 27, count 0 2006.201.05:43:48.73#ibcon#*before return 0, iclass 27, count 0 2006.201.05:43:48.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:48.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:48.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:43:48.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:43:48.73$vck44/va=8,4 2006.201.05:43:48.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.05:43:48.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.05:43:48.73#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:48.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:43:48.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:43:48.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:43:48.79#ibcon#enter wrdev, iclass 29, count 2 2006.201.05:43:48.79#ibcon#first serial, iclass 29, count 2 2006.201.05:43:48.79#ibcon#enter sib2, iclass 29, count 2 2006.201.05:43:48.79#ibcon#flushed, iclass 29, count 2 2006.201.05:43:48.79#ibcon#about to write, iclass 29, count 2 2006.201.05:43:48.79#ibcon#wrote, iclass 29, count 2 2006.201.05:43:48.79#ibcon#about to read 3, iclass 29, count 2 2006.201.05:43:48.81#ibcon#read 3, iclass 29, count 2 2006.201.05:43:48.81#ibcon#about to read 4, iclass 29, count 2 2006.201.05:43:48.81#ibcon#read 4, iclass 29, count 2 2006.201.05:43:48.81#ibcon#about to read 5, iclass 29, count 2 2006.201.05:43:48.81#ibcon#read 5, iclass 29, count 2 2006.201.05:43:48.81#ibcon#about to read 6, iclass 29, count 2 2006.201.05:43:48.81#ibcon#read 6, iclass 29, count 2 2006.201.05:43:48.81#ibcon#end of sib2, iclass 29, count 2 2006.201.05:43:48.81#ibcon#*mode == 0, iclass 29, count 2 2006.201.05:43:48.81#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.05:43:48.81#ibcon#[25=AT08-04\r\n] 2006.201.05:43:48.81#ibcon#*before write, iclass 29, count 2 2006.201.05:43:48.81#ibcon#enter sib2, iclass 29, count 2 2006.201.05:43:48.81#ibcon#flushed, iclass 29, count 2 2006.201.05:43:48.81#ibcon#about to write, iclass 29, count 2 2006.201.05:43:48.81#ibcon#wrote, iclass 29, count 2 2006.201.05:43:48.81#ibcon#about to read 3, iclass 29, count 2 2006.201.05:43:48.84#ibcon#read 3, iclass 29, count 2 2006.201.05:43:48.84#ibcon#about to read 4, iclass 29, count 2 2006.201.05:43:48.84#ibcon#read 4, iclass 29, count 2 2006.201.05:43:48.84#ibcon#about to read 5, iclass 29, count 2 2006.201.05:43:48.84#ibcon#read 5, iclass 29, count 2 2006.201.05:43:48.84#ibcon#about to read 6, iclass 29, count 2 2006.201.05:43:48.84#ibcon#read 6, iclass 29, count 2 2006.201.05:43:48.84#ibcon#end of sib2, iclass 29, count 2 2006.201.05:43:48.84#ibcon#*after write, iclass 29, count 2 2006.201.05:43:48.84#ibcon#*before return 0, iclass 29, count 2 2006.201.05:43:48.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:43:48.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.05:43:48.84#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.05:43:48.84#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:48.84#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:43:48.96#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:43:48.96#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:43:48.96#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:43:48.96#ibcon#first serial, iclass 29, count 0 2006.201.05:43:48.96#ibcon#enter sib2, iclass 29, count 0 2006.201.05:43:48.96#ibcon#flushed, iclass 29, count 0 2006.201.05:43:48.96#ibcon#about to write, iclass 29, count 0 2006.201.05:43:48.96#ibcon#wrote, iclass 29, count 0 2006.201.05:43:48.96#ibcon#about to read 3, iclass 29, count 0 2006.201.05:43:48.98#ibcon#read 3, iclass 29, count 0 2006.201.05:43:48.98#ibcon#about to read 4, iclass 29, count 0 2006.201.05:43:48.98#ibcon#read 4, iclass 29, count 0 2006.201.05:43:48.98#ibcon#about to read 5, iclass 29, count 0 2006.201.05:43:48.98#ibcon#read 5, iclass 29, count 0 2006.201.05:43:48.98#ibcon#about to read 6, iclass 29, count 0 2006.201.05:43:48.98#ibcon#read 6, iclass 29, count 0 2006.201.05:43:48.98#ibcon#end of sib2, iclass 29, count 0 2006.201.05:43:48.98#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:43:48.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:43:48.98#ibcon#[25=USB\r\n] 2006.201.05:43:48.98#ibcon#*before write, iclass 29, count 0 2006.201.05:43:48.98#ibcon#enter sib2, iclass 29, count 0 2006.201.05:43:48.98#ibcon#flushed, iclass 29, count 0 2006.201.05:43:48.98#ibcon#about to write, iclass 29, count 0 2006.201.05:43:48.98#ibcon#wrote, iclass 29, count 0 2006.201.05:43:48.98#ibcon#about to read 3, iclass 29, count 0 2006.201.05:43:49.01#ibcon#read 3, iclass 29, count 0 2006.201.05:43:49.01#ibcon#about to read 4, iclass 29, count 0 2006.201.05:43:49.01#ibcon#read 4, iclass 29, count 0 2006.201.05:43:49.01#ibcon#about to read 5, iclass 29, count 0 2006.201.05:43:49.01#ibcon#read 5, iclass 29, count 0 2006.201.05:43:49.01#ibcon#about to read 6, iclass 29, count 0 2006.201.05:43:49.01#ibcon#read 6, iclass 29, count 0 2006.201.05:43:49.01#ibcon#end of sib2, iclass 29, count 0 2006.201.05:43:49.01#ibcon#*after write, iclass 29, count 0 2006.201.05:43:49.01#ibcon#*before return 0, iclass 29, count 0 2006.201.05:43:49.01#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:43:49.01#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.05:43:49.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:43:49.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:43:49.01$vck44/vblo=1,629.99 2006.201.05:43:49.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.05:43:49.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.05:43:49.01#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:49.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:49.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:49.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:49.01#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:43:49.01#ibcon#first serial, iclass 31, count 0 2006.201.05:43:49.01#ibcon#enter sib2, iclass 31, count 0 2006.201.05:43:49.01#ibcon#flushed, iclass 31, count 0 2006.201.05:43:49.01#ibcon#about to write, iclass 31, count 0 2006.201.05:43:49.01#ibcon#wrote, iclass 31, count 0 2006.201.05:43:49.01#ibcon#about to read 3, iclass 31, count 0 2006.201.05:43:49.03#ibcon#read 3, iclass 31, count 0 2006.201.05:43:49.03#ibcon#about to read 4, iclass 31, count 0 2006.201.05:43:49.03#ibcon#read 4, iclass 31, count 0 2006.201.05:43:49.03#ibcon#about to read 5, iclass 31, count 0 2006.201.05:43:49.03#ibcon#read 5, iclass 31, count 0 2006.201.05:43:49.03#ibcon#about to read 6, iclass 31, count 0 2006.201.05:43:49.03#ibcon#read 6, iclass 31, count 0 2006.201.05:43:49.03#ibcon#end of sib2, iclass 31, count 0 2006.201.05:43:49.03#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:43:49.03#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:43:49.03#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:43:49.03#ibcon#*before write, iclass 31, count 0 2006.201.05:43:49.03#ibcon#enter sib2, iclass 31, count 0 2006.201.05:43:49.03#ibcon#flushed, iclass 31, count 0 2006.201.05:43:49.03#ibcon#about to write, iclass 31, count 0 2006.201.05:43:49.03#ibcon#wrote, iclass 31, count 0 2006.201.05:43:49.03#ibcon#about to read 3, iclass 31, count 0 2006.201.05:43:49.07#ibcon#read 3, iclass 31, count 0 2006.201.05:43:49.07#ibcon#about to read 4, iclass 31, count 0 2006.201.05:43:49.07#ibcon#read 4, iclass 31, count 0 2006.201.05:43:49.07#ibcon#about to read 5, iclass 31, count 0 2006.201.05:43:49.07#ibcon#read 5, iclass 31, count 0 2006.201.05:43:49.07#ibcon#about to read 6, iclass 31, count 0 2006.201.05:43:49.07#ibcon#read 6, iclass 31, count 0 2006.201.05:43:49.07#ibcon#end of sib2, iclass 31, count 0 2006.201.05:43:49.07#ibcon#*after write, iclass 31, count 0 2006.201.05:43:49.07#ibcon#*before return 0, iclass 31, count 0 2006.201.05:43:49.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:49.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.05:43:49.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:43:49.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:43:49.07$vck44/vb=1,4 2006.201.05:43:49.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.05:43:49.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.05:43:49.07#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:49.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:49.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:49.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:49.07#ibcon#enter wrdev, iclass 33, count 2 2006.201.05:43:49.07#ibcon#first serial, iclass 33, count 2 2006.201.05:43:49.07#ibcon#enter sib2, iclass 33, count 2 2006.201.05:43:49.07#ibcon#flushed, iclass 33, count 2 2006.201.05:43:49.07#ibcon#about to write, iclass 33, count 2 2006.201.05:43:49.07#ibcon#wrote, iclass 33, count 2 2006.201.05:43:49.07#ibcon#about to read 3, iclass 33, count 2 2006.201.05:43:49.09#ibcon#read 3, iclass 33, count 2 2006.201.05:43:49.09#ibcon#about to read 4, iclass 33, count 2 2006.201.05:43:49.09#ibcon#read 4, iclass 33, count 2 2006.201.05:43:49.09#ibcon#about to read 5, iclass 33, count 2 2006.201.05:43:49.09#ibcon#read 5, iclass 33, count 2 2006.201.05:43:49.09#ibcon#about to read 6, iclass 33, count 2 2006.201.05:43:49.09#ibcon#read 6, iclass 33, count 2 2006.201.05:43:49.09#ibcon#end of sib2, iclass 33, count 2 2006.201.05:43:49.09#ibcon#*mode == 0, iclass 33, count 2 2006.201.05:43:49.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.05:43:49.09#ibcon#[27=AT01-04\r\n] 2006.201.05:43:49.09#ibcon#*before write, iclass 33, count 2 2006.201.05:43:49.09#ibcon#enter sib2, iclass 33, count 2 2006.201.05:43:49.09#ibcon#flushed, iclass 33, count 2 2006.201.05:43:49.09#ibcon#about to write, iclass 33, count 2 2006.201.05:43:49.09#ibcon#wrote, iclass 33, count 2 2006.201.05:43:49.09#ibcon#about to read 3, iclass 33, count 2 2006.201.05:43:49.12#ibcon#read 3, iclass 33, count 2 2006.201.05:43:49.12#ibcon#about to read 4, iclass 33, count 2 2006.201.05:43:49.12#ibcon#read 4, iclass 33, count 2 2006.201.05:43:49.12#ibcon#about to read 5, iclass 33, count 2 2006.201.05:43:49.12#ibcon#read 5, iclass 33, count 2 2006.201.05:43:49.12#ibcon#about to read 6, iclass 33, count 2 2006.201.05:43:49.12#ibcon#read 6, iclass 33, count 2 2006.201.05:43:49.12#ibcon#end of sib2, iclass 33, count 2 2006.201.05:43:49.12#ibcon#*after write, iclass 33, count 2 2006.201.05:43:49.12#ibcon#*before return 0, iclass 33, count 2 2006.201.05:43:49.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:49.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.05:43:49.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.05:43:49.12#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:49.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:49.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:49.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:49.24#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:43:49.24#ibcon#first serial, iclass 33, count 0 2006.201.05:43:49.24#ibcon#enter sib2, iclass 33, count 0 2006.201.05:43:49.24#ibcon#flushed, iclass 33, count 0 2006.201.05:43:49.24#ibcon#about to write, iclass 33, count 0 2006.201.05:43:49.24#ibcon#wrote, iclass 33, count 0 2006.201.05:43:49.24#ibcon#about to read 3, iclass 33, count 0 2006.201.05:43:49.26#ibcon#read 3, iclass 33, count 0 2006.201.05:43:49.26#ibcon#about to read 4, iclass 33, count 0 2006.201.05:43:49.26#ibcon#read 4, iclass 33, count 0 2006.201.05:43:49.26#ibcon#about to read 5, iclass 33, count 0 2006.201.05:43:49.26#ibcon#read 5, iclass 33, count 0 2006.201.05:43:49.26#ibcon#about to read 6, iclass 33, count 0 2006.201.05:43:49.26#ibcon#read 6, iclass 33, count 0 2006.201.05:43:49.26#ibcon#end of sib2, iclass 33, count 0 2006.201.05:43:49.26#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:43:49.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:43:49.26#ibcon#[27=USB\r\n] 2006.201.05:43:49.26#ibcon#*before write, iclass 33, count 0 2006.201.05:43:49.26#ibcon#enter sib2, iclass 33, count 0 2006.201.05:43:49.26#ibcon#flushed, iclass 33, count 0 2006.201.05:43:49.26#ibcon#about to write, iclass 33, count 0 2006.201.05:43:49.26#ibcon#wrote, iclass 33, count 0 2006.201.05:43:49.26#ibcon#about to read 3, iclass 33, count 0 2006.201.05:43:49.29#ibcon#read 3, iclass 33, count 0 2006.201.05:43:49.29#ibcon#about to read 4, iclass 33, count 0 2006.201.05:43:49.29#ibcon#read 4, iclass 33, count 0 2006.201.05:43:49.29#ibcon#about to read 5, iclass 33, count 0 2006.201.05:43:49.29#ibcon#read 5, iclass 33, count 0 2006.201.05:43:49.29#ibcon#about to read 6, iclass 33, count 0 2006.201.05:43:49.29#ibcon#read 6, iclass 33, count 0 2006.201.05:43:49.29#ibcon#end of sib2, iclass 33, count 0 2006.201.05:43:49.29#ibcon#*after write, iclass 33, count 0 2006.201.05:43:49.29#ibcon#*before return 0, iclass 33, count 0 2006.201.05:43:49.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:49.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.05:43:49.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:43:49.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:43:49.29$vck44/vblo=2,634.99 2006.201.05:43:49.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.05:43:49.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.05:43:49.29#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:49.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:49.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:49.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:49.29#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:43:49.29#ibcon#first serial, iclass 35, count 0 2006.201.05:43:49.29#ibcon#enter sib2, iclass 35, count 0 2006.201.05:43:49.29#ibcon#flushed, iclass 35, count 0 2006.201.05:43:49.29#ibcon#about to write, iclass 35, count 0 2006.201.05:43:49.29#ibcon#wrote, iclass 35, count 0 2006.201.05:43:49.29#ibcon#about to read 3, iclass 35, count 0 2006.201.05:43:49.31#ibcon#read 3, iclass 35, count 0 2006.201.05:43:49.31#ibcon#about to read 4, iclass 35, count 0 2006.201.05:43:49.31#ibcon#read 4, iclass 35, count 0 2006.201.05:43:49.31#ibcon#about to read 5, iclass 35, count 0 2006.201.05:43:49.31#ibcon#read 5, iclass 35, count 0 2006.201.05:43:49.31#ibcon#about to read 6, iclass 35, count 0 2006.201.05:43:49.31#ibcon#read 6, iclass 35, count 0 2006.201.05:43:49.31#ibcon#end of sib2, iclass 35, count 0 2006.201.05:43:49.31#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:43:49.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:43:49.31#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:43:49.31#ibcon#*before write, iclass 35, count 0 2006.201.05:43:49.31#ibcon#enter sib2, iclass 35, count 0 2006.201.05:43:49.31#ibcon#flushed, iclass 35, count 0 2006.201.05:43:49.31#ibcon#about to write, iclass 35, count 0 2006.201.05:43:49.31#ibcon#wrote, iclass 35, count 0 2006.201.05:43:49.31#ibcon#about to read 3, iclass 35, count 0 2006.201.05:43:49.35#ibcon#read 3, iclass 35, count 0 2006.201.05:43:49.35#ibcon#about to read 4, iclass 35, count 0 2006.201.05:43:49.35#ibcon#read 4, iclass 35, count 0 2006.201.05:43:49.35#ibcon#about to read 5, iclass 35, count 0 2006.201.05:43:49.35#ibcon#read 5, iclass 35, count 0 2006.201.05:43:49.35#ibcon#about to read 6, iclass 35, count 0 2006.201.05:43:49.35#ibcon#read 6, iclass 35, count 0 2006.201.05:43:49.35#ibcon#end of sib2, iclass 35, count 0 2006.201.05:43:49.35#ibcon#*after write, iclass 35, count 0 2006.201.05:43:49.35#ibcon#*before return 0, iclass 35, count 0 2006.201.05:43:49.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:49.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.05:43:49.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:43:49.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:43:49.35$vck44/vb=2,5 2006.201.05:43:49.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.05:43:49.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.05:43:49.35#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:49.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:49.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:49.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:49.41#ibcon#enter wrdev, iclass 37, count 2 2006.201.05:43:49.41#ibcon#first serial, iclass 37, count 2 2006.201.05:43:49.41#ibcon#enter sib2, iclass 37, count 2 2006.201.05:43:49.41#ibcon#flushed, iclass 37, count 2 2006.201.05:43:49.41#ibcon#about to write, iclass 37, count 2 2006.201.05:43:49.41#ibcon#wrote, iclass 37, count 2 2006.201.05:43:49.41#ibcon#about to read 3, iclass 37, count 2 2006.201.05:43:49.43#ibcon#read 3, iclass 37, count 2 2006.201.05:43:49.43#ibcon#about to read 4, iclass 37, count 2 2006.201.05:43:49.43#ibcon#read 4, iclass 37, count 2 2006.201.05:43:49.43#ibcon#about to read 5, iclass 37, count 2 2006.201.05:43:49.43#ibcon#read 5, iclass 37, count 2 2006.201.05:43:49.43#ibcon#about to read 6, iclass 37, count 2 2006.201.05:43:49.43#ibcon#read 6, iclass 37, count 2 2006.201.05:43:49.43#ibcon#end of sib2, iclass 37, count 2 2006.201.05:43:49.43#ibcon#*mode == 0, iclass 37, count 2 2006.201.05:43:49.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.05:43:49.43#ibcon#[27=AT02-05\r\n] 2006.201.05:43:49.43#ibcon#*before write, iclass 37, count 2 2006.201.05:43:49.43#ibcon#enter sib2, iclass 37, count 2 2006.201.05:43:49.43#ibcon#flushed, iclass 37, count 2 2006.201.05:43:49.43#ibcon#about to write, iclass 37, count 2 2006.201.05:43:49.43#ibcon#wrote, iclass 37, count 2 2006.201.05:43:49.43#ibcon#about to read 3, iclass 37, count 2 2006.201.05:43:49.46#ibcon#read 3, iclass 37, count 2 2006.201.05:43:49.46#ibcon#about to read 4, iclass 37, count 2 2006.201.05:43:49.46#ibcon#read 4, iclass 37, count 2 2006.201.05:43:49.46#ibcon#about to read 5, iclass 37, count 2 2006.201.05:43:49.46#ibcon#read 5, iclass 37, count 2 2006.201.05:43:49.46#ibcon#about to read 6, iclass 37, count 2 2006.201.05:43:49.46#ibcon#read 6, iclass 37, count 2 2006.201.05:43:49.46#ibcon#end of sib2, iclass 37, count 2 2006.201.05:43:49.46#ibcon#*after write, iclass 37, count 2 2006.201.05:43:49.46#ibcon#*before return 0, iclass 37, count 2 2006.201.05:43:49.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:49.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.05:43:49.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.05:43:49.46#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:49.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:49.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:49.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:49.58#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:43:49.58#ibcon#first serial, iclass 37, count 0 2006.201.05:43:49.58#ibcon#enter sib2, iclass 37, count 0 2006.201.05:43:49.58#ibcon#flushed, iclass 37, count 0 2006.201.05:43:49.58#ibcon#about to write, iclass 37, count 0 2006.201.05:43:49.58#ibcon#wrote, iclass 37, count 0 2006.201.05:43:49.58#ibcon#about to read 3, iclass 37, count 0 2006.201.05:43:49.60#ibcon#read 3, iclass 37, count 0 2006.201.05:43:49.60#ibcon#about to read 4, iclass 37, count 0 2006.201.05:43:49.60#ibcon#read 4, iclass 37, count 0 2006.201.05:43:49.60#ibcon#about to read 5, iclass 37, count 0 2006.201.05:43:49.60#ibcon#read 5, iclass 37, count 0 2006.201.05:43:49.60#ibcon#about to read 6, iclass 37, count 0 2006.201.05:43:49.60#ibcon#read 6, iclass 37, count 0 2006.201.05:43:49.60#ibcon#end of sib2, iclass 37, count 0 2006.201.05:43:49.60#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:43:49.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:43:49.60#ibcon#[27=USB\r\n] 2006.201.05:43:49.60#ibcon#*before write, iclass 37, count 0 2006.201.05:43:49.60#ibcon#enter sib2, iclass 37, count 0 2006.201.05:43:49.60#ibcon#flushed, iclass 37, count 0 2006.201.05:43:49.60#ibcon#about to write, iclass 37, count 0 2006.201.05:43:49.60#ibcon#wrote, iclass 37, count 0 2006.201.05:43:49.60#ibcon#about to read 3, iclass 37, count 0 2006.201.05:43:49.63#ibcon#read 3, iclass 37, count 0 2006.201.05:43:49.63#ibcon#about to read 4, iclass 37, count 0 2006.201.05:43:49.63#ibcon#read 4, iclass 37, count 0 2006.201.05:43:49.63#ibcon#about to read 5, iclass 37, count 0 2006.201.05:43:49.63#ibcon#read 5, iclass 37, count 0 2006.201.05:43:49.63#ibcon#about to read 6, iclass 37, count 0 2006.201.05:43:49.63#ibcon#read 6, iclass 37, count 0 2006.201.05:43:49.63#ibcon#end of sib2, iclass 37, count 0 2006.201.05:43:49.63#ibcon#*after write, iclass 37, count 0 2006.201.05:43:49.63#ibcon#*before return 0, iclass 37, count 0 2006.201.05:43:49.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:49.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.05:43:49.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:43:49.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:43:49.63$vck44/vblo=3,649.99 2006.201.05:43:49.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.05:43:49.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.05:43:49.63#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:49.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:43:49.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:43:49.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:43:49.63#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:43:49.63#ibcon#first serial, iclass 39, count 0 2006.201.05:43:49.63#ibcon#enter sib2, iclass 39, count 0 2006.201.05:43:49.63#ibcon#flushed, iclass 39, count 0 2006.201.05:43:49.63#ibcon#about to write, iclass 39, count 0 2006.201.05:43:49.63#ibcon#wrote, iclass 39, count 0 2006.201.05:43:49.63#ibcon#about to read 3, iclass 39, count 0 2006.201.05:43:49.65#ibcon#read 3, iclass 39, count 0 2006.201.05:43:49.65#ibcon#about to read 4, iclass 39, count 0 2006.201.05:43:49.65#ibcon#read 4, iclass 39, count 0 2006.201.05:43:49.65#ibcon#about to read 5, iclass 39, count 0 2006.201.05:43:49.65#ibcon#read 5, iclass 39, count 0 2006.201.05:43:49.65#ibcon#about to read 6, iclass 39, count 0 2006.201.05:43:49.65#ibcon#read 6, iclass 39, count 0 2006.201.05:43:49.65#ibcon#end of sib2, iclass 39, count 0 2006.201.05:43:49.65#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:43:49.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:43:49.65#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:43:49.65#ibcon#*before write, iclass 39, count 0 2006.201.05:43:49.65#ibcon#enter sib2, iclass 39, count 0 2006.201.05:43:49.65#ibcon#flushed, iclass 39, count 0 2006.201.05:43:49.65#ibcon#about to write, iclass 39, count 0 2006.201.05:43:49.65#ibcon#wrote, iclass 39, count 0 2006.201.05:43:49.65#ibcon#about to read 3, iclass 39, count 0 2006.201.05:43:49.69#ibcon#read 3, iclass 39, count 0 2006.201.05:43:49.69#ibcon#about to read 4, iclass 39, count 0 2006.201.05:43:49.69#ibcon#read 4, iclass 39, count 0 2006.201.05:43:49.69#ibcon#about to read 5, iclass 39, count 0 2006.201.05:43:49.69#ibcon#read 5, iclass 39, count 0 2006.201.05:43:49.75#ibcon#about to read 6, iclass 39, count 0 2006.201.05:43:49.75#ibcon#read 6, iclass 39, count 0 2006.201.05:43:49.75#ibcon#end of sib2, iclass 39, count 0 2006.201.05:43:49.75#ibcon#*after write, iclass 39, count 0 2006.201.05:43:49.75#ibcon#*before return 0, iclass 39, count 0 2006.201.05:43:49.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:43:49.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.05:43:49.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:43:49.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:43:49.75$vck44/vb=3,4 2006.201.05:43:49.75#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.05:43:49.75#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.05:43:49.75#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:49.75#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:43:49.75#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:43:49.75#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:43:49.75#ibcon#enter wrdev, iclass 2, count 2 2006.201.05:43:49.75#ibcon#first serial, iclass 2, count 2 2006.201.05:43:49.75#ibcon#enter sib2, iclass 2, count 2 2006.201.05:43:49.75#ibcon#flushed, iclass 2, count 2 2006.201.05:43:49.75#ibcon#about to write, iclass 2, count 2 2006.201.05:43:49.75#ibcon#wrote, iclass 2, count 2 2006.201.05:43:49.75#ibcon#about to read 3, iclass 2, count 2 2006.201.05:43:49.77#ibcon#read 3, iclass 2, count 2 2006.201.05:43:49.77#ibcon#about to read 4, iclass 2, count 2 2006.201.05:43:49.77#ibcon#read 4, iclass 2, count 2 2006.201.05:43:49.77#ibcon#about to read 5, iclass 2, count 2 2006.201.05:43:49.77#ibcon#read 5, iclass 2, count 2 2006.201.05:43:49.77#ibcon#about to read 6, iclass 2, count 2 2006.201.05:43:49.77#ibcon#read 6, iclass 2, count 2 2006.201.05:43:49.77#ibcon#end of sib2, iclass 2, count 2 2006.201.05:43:49.77#ibcon#*mode == 0, iclass 2, count 2 2006.201.05:43:49.77#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.05:43:49.77#ibcon#[27=AT03-04\r\n] 2006.201.05:43:49.77#ibcon#*before write, iclass 2, count 2 2006.201.05:43:49.77#ibcon#enter sib2, iclass 2, count 2 2006.201.05:43:49.77#ibcon#flushed, iclass 2, count 2 2006.201.05:43:49.77#ibcon#about to write, iclass 2, count 2 2006.201.05:43:49.77#ibcon#wrote, iclass 2, count 2 2006.201.05:43:49.77#ibcon#about to read 3, iclass 2, count 2 2006.201.05:43:49.80#ibcon#read 3, iclass 2, count 2 2006.201.05:43:49.80#ibcon#about to read 4, iclass 2, count 2 2006.201.05:43:49.80#ibcon#read 4, iclass 2, count 2 2006.201.05:43:49.80#ibcon#about to read 5, iclass 2, count 2 2006.201.05:43:49.80#ibcon#read 5, iclass 2, count 2 2006.201.05:43:49.80#ibcon#about to read 6, iclass 2, count 2 2006.201.05:43:49.80#ibcon#read 6, iclass 2, count 2 2006.201.05:43:49.80#ibcon#end of sib2, iclass 2, count 2 2006.201.05:43:49.80#ibcon#*after write, iclass 2, count 2 2006.201.05:43:49.80#ibcon#*before return 0, iclass 2, count 2 2006.201.05:43:49.80#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:43:49.80#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.05:43:49.80#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.05:43:49.80#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:49.80#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:43:49.92#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:43:49.92#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:43:49.92#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:43:49.92#ibcon#first serial, iclass 2, count 0 2006.201.05:43:49.92#ibcon#enter sib2, iclass 2, count 0 2006.201.05:43:49.92#ibcon#flushed, iclass 2, count 0 2006.201.05:43:49.92#ibcon#about to write, iclass 2, count 0 2006.201.05:43:49.92#ibcon#wrote, iclass 2, count 0 2006.201.05:43:49.92#ibcon#about to read 3, iclass 2, count 0 2006.201.05:43:49.94#ibcon#read 3, iclass 2, count 0 2006.201.05:43:49.94#ibcon#about to read 4, iclass 2, count 0 2006.201.05:43:49.94#ibcon#read 4, iclass 2, count 0 2006.201.05:43:49.94#ibcon#about to read 5, iclass 2, count 0 2006.201.05:43:49.94#ibcon#read 5, iclass 2, count 0 2006.201.05:43:49.94#ibcon#about to read 6, iclass 2, count 0 2006.201.05:43:49.94#ibcon#read 6, iclass 2, count 0 2006.201.05:43:49.94#ibcon#end of sib2, iclass 2, count 0 2006.201.05:43:49.94#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:43:49.94#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:43:49.94#ibcon#[27=USB\r\n] 2006.201.05:43:49.94#ibcon#*before write, iclass 2, count 0 2006.201.05:43:49.94#ibcon#enter sib2, iclass 2, count 0 2006.201.05:43:49.94#ibcon#flushed, iclass 2, count 0 2006.201.05:43:49.94#ibcon#about to write, iclass 2, count 0 2006.201.05:43:49.94#ibcon#wrote, iclass 2, count 0 2006.201.05:43:49.94#ibcon#about to read 3, iclass 2, count 0 2006.201.05:43:49.97#ibcon#read 3, iclass 2, count 0 2006.201.05:43:49.97#ibcon#about to read 4, iclass 2, count 0 2006.201.05:43:49.97#ibcon#read 4, iclass 2, count 0 2006.201.05:43:49.97#ibcon#about to read 5, iclass 2, count 0 2006.201.05:43:49.97#ibcon#read 5, iclass 2, count 0 2006.201.05:43:49.97#ibcon#about to read 6, iclass 2, count 0 2006.201.05:43:49.97#ibcon#read 6, iclass 2, count 0 2006.201.05:43:49.97#ibcon#end of sib2, iclass 2, count 0 2006.201.05:43:49.97#ibcon#*after write, iclass 2, count 0 2006.201.05:43:49.97#ibcon#*before return 0, iclass 2, count 0 2006.201.05:43:49.97#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:43:49.97#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.05:43:49.97#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:43:49.97#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:43:49.97$vck44/vblo=4,679.99 2006.201.05:43:49.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.05:43:49.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.05:43:49.97#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:49.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:43:49.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:43:49.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:43:49.97#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:43:49.97#ibcon#first serial, iclass 5, count 0 2006.201.05:43:49.97#ibcon#enter sib2, iclass 5, count 0 2006.201.05:43:49.97#ibcon#flushed, iclass 5, count 0 2006.201.05:43:49.97#ibcon#about to write, iclass 5, count 0 2006.201.05:43:49.97#ibcon#wrote, iclass 5, count 0 2006.201.05:43:49.97#ibcon#about to read 3, iclass 5, count 0 2006.201.05:43:49.99#ibcon#read 3, iclass 5, count 0 2006.201.05:43:49.99#ibcon#about to read 4, iclass 5, count 0 2006.201.05:43:49.99#ibcon#read 4, iclass 5, count 0 2006.201.05:43:49.99#ibcon#about to read 5, iclass 5, count 0 2006.201.05:43:49.99#ibcon#read 5, iclass 5, count 0 2006.201.05:43:49.99#ibcon#about to read 6, iclass 5, count 0 2006.201.05:43:49.99#ibcon#read 6, iclass 5, count 0 2006.201.05:43:49.99#ibcon#end of sib2, iclass 5, count 0 2006.201.05:43:49.99#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:43:49.99#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:43:49.99#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:43:49.99#ibcon#*before write, iclass 5, count 0 2006.201.05:43:49.99#ibcon#enter sib2, iclass 5, count 0 2006.201.05:43:49.99#ibcon#flushed, iclass 5, count 0 2006.201.05:43:49.99#ibcon#about to write, iclass 5, count 0 2006.201.05:43:49.99#ibcon#wrote, iclass 5, count 0 2006.201.05:43:49.99#ibcon#about to read 3, iclass 5, count 0 2006.201.05:43:50.03#ibcon#read 3, iclass 5, count 0 2006.201.05:43:50.03#ibcon#about to read 4, iclass 5, count 0 2006.201.05:43:50.03#ibcon#read 4, iclass 5, count 0 2006.201.05:43:50.03#ibcon#about to read 5, iclass 5, count 0 2006.201.05:43:50.03#ibcon#read 5, iclass 5, count 0 2006.201.05:43:50.03#ibcon#about to read 6, iclass 5, count 0 2006.201.05:43:50.03#ibcon#read 6, iclass 5, count 0 2006.201.05:43:50.03#ibcon#end of sib2, iclass 5, count 0 2006.201.05:43:50.03#ibcon#*after write, iclass 5, count 0 2006.201.05:43:50.03#ibcon#*before return 0, iclass 5, count 0 2006.201.05:43:50.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:43:50.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:43:50.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:43:50.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:43:50.03$vck44/vb=4,5 2006.201.05:43:50.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.05:43:50.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.05:43:50.03#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:50.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:43:50.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:43:50.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:43:50.09#ibcon#enter wrdev, iclass 7, count 2 2006.201.05:43:50.09#ibcon#first serial, iclass 7, count 2 2006.201.05:43:50.09#ibcon#enter sib2, iclass 7, count 2 2006.201.05:43:50.09#ibcon#flushed, iclass 7, count 2 2006.201.05:43:50.09#ibcon#about to write, iclass 7, count 2 2006.201.05:43:50.09#ibcon#wrote, iclass 7, count 2 2006.201.05:43:50.09#ibcon#about to read 3, iclass 7, count 2 2006.201.05:43:50.11#ibcon#read 3, iclass 7, count 2 2006.201.05:43:50.11#ibcon#about to read 4, iclass 7, count 2 2006.201.05:43:50.11#ibcon#read 4, iclass 7, count 2 2006.201.05:43:50.11#ibcon#about to read 5, iclass 7, count 2 2006.201.05:43:50.11#ibcon#read 5, iclass 7, count 2 2006.201.05:43:50.11#ibcon#about to read 6, iclass 7, count 2 2006.201.05:43:50.11#ibcon#read 6, iclass 7, count 2 2006.201.05:43:50.11#ibcon#end of sib2, iclass 7, count 2 2006.201.05:43:50.11#ibcon#*mode == 0, iclass 7, count 2 2006.201.05:43:50.11#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.05:43:50.11#ibcon#[27=AT04-05\r\n] 2006.201.05:43:50.11#ibcon#*before write, iclass 7, count 2 2006.201.05:43:50.11#ibcon#enter sib2, iclass 7, count 2 2006.201.05:43:50.11#ibcon#flushed, iclass 7, count 2 2006.201.05:43:50.11#ibcon#about to write, iclass 7, count 2 2006.201.05:43:50.11#ibcon#wrote, iclass 7, count 2 2006.201.05:43:50.11#ibcon#about to read 3, iclass 7, count 2 2006.201.05:43:50.14#ibcon#read 3, iclass 7, count 2 2006.201.05:43:50.14#ibcon#about to read 4, iclass 7, count 2 2006.201.05:43:50.14#ibcon#read 4, iclass 7, count 2 2006.201.05:43:50.14#ibcon#about to read 5, iclass 7, count 2 2006.201.05:43:50.14#ibcon#read 5, iclass 7, count 2 2006.201.05:43:50.14#ibcon#about to read 6, iclass 7, count 2 2006.201.05:43:50.14#ibcon#read 6, iclass 7, count 2 2006.201.05:43:50.14#ibcon#end of sib2, iclass 7, count 2 2006.201.05:43:50.14#ibcon#*after write, iclass 7, count 2 2006.201.05:43:50.14#ibcon#*before return 0, iclass 7, count 2 2006.201.05:43:50.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:43:50.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.05:43:50.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.05:43:50.14#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:50.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:43:50.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:43:50.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:43:50.26#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:43:50.26#ibcon#first serial, iclass 7, count 0 2006.201.05:43:50.26#ibcon#enter sib2, iclass 7, count 0 2006.201.05:43:50.26#ibcon#flushed, iclass 7, count 0 2006.201.05:43:50.26#ibcon#about to write, iclass 7, count 0 2006.201.05:43:50.26#ibcon#wrote, iclass 7, count 0 2006.201.05:43:50.26#ibcon#about to read 3, iclass 7, count 0 2006.201.05:43:50.28#ibcon#read 3, iclass 7, count 0 2006.201.05:43:50.28#ibcon#about to read 4, iclass 7, count 0 2006.201.05:43:50.28#ibcon#read 4, iclass 7, count 0 2006.201.05:43:50.28#ibcon#about to read 5, iclass 7, count 0 2006.201.05:43:50.28#ibcon#read 5, iclass 7, count 0 2006.201.05:43:50.28#ibcon#about to read 6, iclass 7, count 0 2006.201.05:43:50.28#ibcon#read 6, iclass 7, count 0 2006.201.05:43:50.28#ibcon#end of sib2, iclass 7, count 0 2006.201.05:43:50.28#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:43:50.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:43:50.28#ibcon#[27=USB\r\n] 2006.201.05:43:50.28#ibcon#*before write, iclass 7, count 0 2006.201.05:43:50.28#ibcon#enter sib2, iclass 7, count 0 2006.201.05:43:50.28#ibcon#flushed, iclass 7, count 0 2006.201.05:43:50.28#ibcon#about to write, iclass 7, count 0 2006.201.05:43:50.28#ibcon#wrote, iclass 7, count 0 2006.201.05:43:50.28#ibcon#about to read 3, iclass 7, count 0 2006.201.05:43:50.31#ibcon#read 3, iclass 7, count 0 2006.201.05:43:50.31#ibcon#about to read 4, iclass 7, count 0 2006.201.05:43:50.31#ibcon#read 4, iclass 7, count 0 2006.201.05:43:50.31#ibcon#about to read 5, iclass 7, count 0 2006.201.05:43:50.31#ibcon#read 5, iclass 7, count 0 2006.201.05:43:50.31#ibcon#about to read 6, iclass 7, count 0 2006.201.05:43:50.31#ibcon#read 6, iclass 7, count 0 2006.201.05:43:50.31#ibcon#end of sib2, iclass 7, count 0 2006.201.05:43:50.31#ibcon#*after write, iclass 7, count 0 2006.201.05:43:50.31#ibcon#*before return 0, iclass 7, count 0 2006.201.05:43:50.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:43:50.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.05:43:50.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:43:50.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:43:50.31$vck44/vblo=5,709.99 2006.201.05:43:50.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.05:43:50.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.05:43:50.31#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:50.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:50.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:50.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:50.31#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:43:50.31#ibcon#first serial, iclass 11, count 0 2006.201.05:43:50.31#ibcon#enter sib2, iclass 11, count 0 2006.201.05:43:50.31#ibcon#flushed, iclass 11, count 0 2006.201.05:43:50.31#ibcon#about to write, iclass 11, count 0 2006.201.05:43:50.31#ibcon#wrote, iclass 11, count 0 2006.201.05:43:50.31#ibcon#about to read 3, iclass 11, count 0 2006.201.05:43:50.33#ibcon#read 3, iclass 11, count 0 2006.201.05:43:50.33#ibcon#about to read 4, iclass 11, count 0 2006.201.05:43:50.33#ibcon#read 4, iclass 11, count 0 2006.201.05:43:50.33#ibcon#about to read 5, iclass 11, count 0 2006.201.05:43:50.33#ibcon#read 5, iclass 11, count 0 2006.201.05:43:50.33#ibcon#about to read 6, iclass 11, count 0 2006.201.05:43:50.33#ibcon#read 6, iclass 11, count 0 2006.201.05:43:50.33#ibcon#end of sib2, iclass 11, count 0 2006.201.05:43:50.33#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:43:50.33#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:43:50.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:43:50.33#ibcon#*before write, iclass 11, count 0 2006.201.05:43:50.33#ibcon#enter sib2, iclass 11, count 0 2006.201.05:43:50.33#ibcon#flushed, iclass 11, count 0 2006.201.05:43:50.33#ibcon#about to write, iclass 11, count 0 2006.201.05:43:50.33#ibcon#wrote, iclass 11, count 0 2006.201.05:43:50.33#ibcon#about to read 3, iclass 11, count 0 2006.201.05:43:50.37#ibcon#read 3, iclass 11, count 0 2006.201.05:43:50.37#ibcon#about to read 4, iclass 11, count 0 2006.201.05:43:50.37#ibcon#read 4, iclass 11, count 0 2006.201.05:43:50.37#ibcon#about to read 5, iclass 11, count 0 2006.201.05:43:50.37#ibcon#read 5, iclass 11, count 0 2006.201.05:43:50.37#ibcon#about to read 6, iclass 11, count 0 2006.201.05:43:50.37#ibcon#read 6, iclass 11, count 0 2006.201.05:43:50.37#ibcon#end of sib2, iclass 11, count 0 2006.201.05:43:50.37#ibcon#*after write, iclass 11, count 0 2006.201.05:43:50.37#ibcon#*before return 0, iclass 11, count 0 2006.201.05:43:50.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:50.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.05:43:50.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:43:50.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:43:50.37$vck44/vb=5,4 2006.201.05:43:50.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.05:43:50.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.05:43:50.37#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:50.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:50.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:50.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:50.43#ibcon#enter wrdev, iclass 13, count 2 2006.201.05:43:50.43#ibcon#first serial, iclass 13, count 2 2006.201.05:43:50.43#ibcon#enter sib2, iclass 13, count 2 2006.201.05:43:50.43#ibcon#flushed, iclass 13, count 2 2006.201.05:43:50.43#ibcon#about to write, iclass 13, count 2 2006.201.05:43:50.43#ibcon#wrote, iclass 13, count 2 2006.201.05:43:50.43#ibcon#about to read 3, iclass 13, count 2 2006.201.05:43:50.45#ibcon#read 3, iclass 13, count 2 2006.201.05:43:50.45#ibcon#about to read 4, iclass 13, count 2 2006.201.05:43:50.45#ibcon#read 4, iclass 13, count 2 2006.201.05:43:50.45#ibcon#about to read 5, iclass 13, count 2 2006.201.05:43:50.45#ibcon#read 5, iclass 13, count 2 2006.201.05:43:50.45#ibcon#about to read 6, iclass 13, count 2 2006.201.05:43:50.45#ibcon#read 6, iclass 13, count 2 2006.201.05:43:50.45#ibcon#end of sib2, iclass 13, count 2 2006.201.05:43:50.45#ibcon#*mode == 0, iclass 13, count 2 2006.201.05:43:50.45#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.05:43:50.45#ibcon#[27=AT05-04\r\n] 2006.201.05:43:50.45#ibcon#*before write, iclass 13, count 2 2006.201.05:43:50.45#ibcon#enter sib2, iclass 13, count 2 2006.201.05:43:50.45#ibcon#flushed, iclass 13, count 2 2006.201.05:43:50.45#ibcon#about to write, iclass 13, count 2 2006.201.05:43:50.45#ibcon#wrote, iclass 13, count 2 2006.201.05:43:50.45#ibcon#about to read 3, iclass 13, count 2 2006.201.05:43:50.48#ibcon#read 3, iclass 13, count 2 2006.201.05:43:50.48#ibcon#about to read 4, iclass 13, count 2 2006.201.05:43:50.48#ibcon#read 4, iclass 13, count 2 2006.201.05:43:50.48#ibcon#about to read 5, iclass 13, count 2 2006.201.05:43:50.48#ibcon#read 5, iclass 13, count 2 2006.201.05:43:50.48#ibcon#about to read 6, iclass 13, count 2 2006.201.05:43:50.48#ibcon#read 6, iclass 13, count 2 2006.201.05:43:50.48#ibcon#end of sib2, iclass 13, count 2 2006.201.05:43:50.48#ibcon#*after write, iclass 13, count 2 2006.201.05:43:50.48#ibcon#*before return 0, iclass 13, count 2 2006.201.05:43:50.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:50.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.05:43:50.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.05:43:50.48#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:50.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:50.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:50.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:50.60#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:43:50.60#ibcon#first serial, iclass 13, count 0 2006.201.05:43:50.60#ibcon#enter sib2, iclass 13, count 0 2006.201.05:43:50.60#ibcon#flushed, iclass 13, count 0 2006.201.05:43:50.60#ibcon#about to write, iclass 13, count 0 2006.201.05:43:50.60#ibcon#wrote, iclass 13, count 0 2006.201.05:43:50.60#ibcon#about to read 3, iclass 13, count 0 2006.201.05:43:50.62#ibcon#read 3, iclass 13, count 0 2006.201.05:43:50.62#ibcon#about to read 4, iclass 13, count 0 2006.201.05:43:50.62#ibcon#read 4, iclass 13, count 0 2006.201.05:43:50.62#ibcon#about to read 5, iclass 13, count 0 2006.201.05:43:50.62#ibcon#read 5, iclass 13, count 0 2006.201.05:43:50.62#ibcon#about to read 6, iclass 13, count 0 2006.201.05:43:50.62#ibcon#read 6, iclass 13, count 0 2006.201.05:43:50.62#ibcon#end of sib2, iclass 13, count 0 2006.201.05:43:50.62#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:43:50.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:43:50.62#ibcon#[27=USB\r\n] 2006.201.05:43:50.62#ibcon#*before write, iclass 13, count 0 2006.201.05:43:50.62#ibcon#enter sib2, iclass 13, count 0 2006.201.05:43:50.62#ibcon#flushed, iclass 13, count 0 2006.201.05:43:50.62#ibcon#about to write, iclass 13, count 0 2006.201.05:43:50.62#ibcon#wrote, iclass 13, count 0 2006.201.05:43:50.62#ibcon#about to read 3, iclass 13, count 0 2006.201.05:43:50.65#ibcon#read 3, iclass 13, count 0 2006.201.05:43:50.65#ibcon#about to read 4, iclass 13, count 0 2006.201.05:43:50.65#ibcon#read 4, iclass 13, count 0 2006.201.05:43:50.65#ibcon#about to read 5, iclass 13, count 0 2006.201.05:43:50.65#ibcon#read 5, iclass 13, count 0 2006.201.05:43:50.65#ibcon#about to read 6, iclass 13, count 0 2006.201.05:43:50.65#ibcon#read 6, iclass 13, count 0 2006.201.05:43:50.65#ibcon#end of sib2, iclass 13, count 0 2006.201.05:43:50.65#ibcon#*after write, iclass 13, count 0 2006.201.05:43:50.65#ibcon#*before return 0, iclass 13, count 0 2006.201.05:43:50.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:50.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.05:43:50.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:43:50.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:43:50.65$vck44/vblo=6,719.99 2006.201.05:43:50.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.05:43:50.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.05:43:50.65#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:50.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:50.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:50.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:50.65#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:43:50.65#ibcon#first serial, iclass 15, count 0 2006.201.05:43:50.65#ibcon#enter sib2, iclass 15, count 0 2006.201.05:43:50.65#ibcon#flushed, iclass 15, count 0 2006.201.05:43:50.65#ibcon#about to write, iclass 15, count 0 2006.201.05:43:50.65#ibcon#wrote, iclass 15, count 0 2006.201.05:43:50.65#ibcon#about to read 3, iclass 15, count 0 2006.201.05:43:50.67#ibcon#read 3, iclass 15, count 0 2006.201.05:43:50.67#ibcon#about to read 4, iclass 15, count 0 2006.201.05:43:50.67#ibcon#read 4, iclass 15, count 0 2006.201.05:43:50.67#ibcon#about to read 5, iclass 15, count 0 2006.201.05:43:50.67#ibcon#read 5, iclass 15, count 0 2006.201.05:43:50.67#ibcon#about to read 6, iclass 15, count 0 2006.201.05:43:50.67#ibcon#read 6, iclass 15, count 0 2006.201.05:43:50.67#ibcon#end of sib2, iclass 15, count 0 2006.201.05:43:50.67#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:43:50.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:43:50.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:43:50.67#ibcon#*before write, iclass 15, count 0 2006.201.05:43:50.67#ibcon#enter sib2, iclass 15, count 0 2006.201.05:43:50.67#ibcon#flushed, iclass 15, count 0 2006.201.05:43:50.67#ibcon#about to write, iclass 15, count 0 2006.201.05:43:50.67#ibcon#wrote, iclass 15, count 0 2006.201.05:43:50.67#ibcon#about to read 3, iclass 15, count 0 2006.201.05:43:50.71#ibcon#read 3, iclass 15, count 0 2006.201.05:43:50.71#ibcon#about to read 4, iclass 15, count 0 2006.201.05:43:50.71#ibcon#read 4, iclass 15, count 0 2006.201.05:43:50.71#ibcon#about to read 5, iclass 15, count 0 2006.201.05:43:50.71#ibcon#read 5, iclass 15, count 0 2006.201.05:43:50.71#ibcon#about to read 6, iclass 15, count 0 2006.201.05:43:50.71#ibcon#read 6, iclass 15, count 0 2006.201.05:43:50.71#ibcon#end of sib2, iclass 15, count 0 2006.201.05:43:50.71#ibcon#*after write, iclass 15, count 0 2006.201.05:43:50.71#ibcon#*before return 0, iclass 15, count 0 2006.201.05:43:50.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:50.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.05:43:50.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:43:50.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:43:50.71$vck44/vb=6,4 2006.201.05:43:50.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.05:43:50.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.05:43:50.71#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:50.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:50.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:50.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:50.77#ibcon#enter wrdev, iclass 17, count 2 2006.201.05:43:50.77#ibcon#first serial, iclass 17, count 2 2006.201.05:43:50.77#ibcon#enter sib2, iclass 17, count 2 2006.201.05:43:50.77#ibcon#flushed, iclass 17, count 2 2006.201.05:43:50.77#ibcon#about to write, iclass 17, count 2 2006.201.05:43:50.77#ibcon#wrote, iclass 17, count 2 2006.201.05:43:50.77#ibcon#about to read 3, iclass 17, count 2 2006.201.05:43:50.79#ibcon#read 3, iclass 17, count 2 2006.201.05:43:50.79#ibcon#about to read 4, iclass 17, count 2 2006.201.05:43:50.79#ibcon#read 4, iclass 17, count 2 2006.201.05:43:50.79#ibcon#about to read 5, iclass 17, count 2 2006.201.05:43:50.79#ibcon#read 5, iclass 17, count 2 2006.201.05:43:50.79#ibcon#about to read 6, iclass 17, count 2 2006.201.05:43:50.79#ibcon#read 6, iclass 17, count 2 2006.201.05:43:50.79#ibcon#end of sib2, iclass 17, count 2 2006.201.05:43:50.79#ibcon#*mode == 0, iclass 17, count 2 2006.201.05:43:50.79#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.05:43:50.79#ibcon#[27=AT06-04\r\n] 2006.201.05:43:50.79#ibcon#*before write, iclass 17, count 2 2006.201.05:43:50.79#ibcon#enter sib2, iclass 17, count 2 2006.201.05:43:50.79#ibcon#flushed, iclass 17, count 2 2006.201.05:43:50.79#ibcon#about to write, iclass 17, count 2 2006.201.05:43:50.79#ibcon#wrote, iclass 17, count 2 2006.201.05:43:50.79#ibcon#about to read 3, iclass 17, count 2 2006.201.05:43:50.83#ibcon#read 3, iclass 17, count 2 2006.201.05:43:50.83#ibcon#about to read 4, iclass 17, count 2 2006.201.05:43:50.83#ibcon#read 4, iclass 17, count 2 2006.201.05:43:50.83#ibcon#about to read 5, iclass 17, count 2 2006.201.05:43:50.84#ibcon#read 5, iclass 17, count 2 2006.201.05:43:50.84#ibcon#about to read 6, iclass 17, count 2 2006.201.05:43:50.84#ibcon#read 6, iclass 17, count 2 2006.201.05:43:50.84#ibcon#end of sib2, iclass 17, count 2 2006.201.05:43:50.84#ibcon#*after write, iclass 17, count 2 2006.201.05:43:50.84#ibcon#*before return 0, iclass 17, count 2 2006.201.05:43:50.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:50.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.05:43:50.84#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.05:43:50.84#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:50.84#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:50.96#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:50.96#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:50.96#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:43:50.96#ibcon#first serial, iclass 17, count 0 2006.201.05:43:50.96#ibcon#enter sib2, iclass 17, count 0 2006.201.05:43:50.96#ibcon#flushed, iclass 17, count 0 2006.201.05:43:50.96#ibcon#about to write, iclass 17, count 0 2006.201.05:43:50.96#ibcon#wrote, iclass 17, count 0 2006.201.05:43:50.96#ibcon#about to read 3, iclass 17, count 0 2006.201.05:43:50.98#ibcon#read 3, iclass 17, count 0 2006.201.05:43:50.98#ibcon#about to read 4, iclass 17, count 0 2006.201.05:43:50.98#ibcon#read 4, iclass 17, count 0 2006.201.05:43:50.98#ibcon#about to read 5, iclass 17, count 0 2006.201.05:43:50.98#ibcon#read 5, iclass 17, count 0 2006.201.05:43:50.98#ibcon#about to read 6, iclass 17, count 0 2006.201.05:43:50.98#ibcon#read 6, iclass 17, count 0 2006.201.05:43:50.98#ibcon#end of sib2, iclass 17, count 0 2006.201.05:43:50.98#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:43:50.98#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:43:50.98#ibcon#[27=USB\r\n] 2006.201.05:43:50.98#ibcon#*before write, iclass 17, count 0 2006.201.05:43:50.98#ibcon#enter sib2, iclass 17, count 0 2006.201.05:43:50.98#ibcon#flushed, iclass 17, count 0 2006.201.05:43:50.98#ibcon#about to write, iclass 17, count 0 2006.201.05:43:50.98#ibcon#wrote, iclass 17, count 0 2006.201.05:43:50.98#ibcon#about to read 3, iclass 17, count 0 2006.201.05:43:51.01#ibcon#read 3, iclass 17, count 0 2006.201.05:43:51.01#ibcon#about to read 4, iclass 17, count 0 2006.201.05:43:51.01#ibcon#read 4, iclass 17, count 0 2006.201.05:43:51.01#ibcon#about to read 5, iclass 17, count 0 2006.201.05:43:51.01#ibcon#read 5, iclass 17, count 0 2006.201.05:43:51.01#ibcon#about to read 6, iclass 17, count 0 2006.201.05:43:51.01#ibcon#read 6, iclass 17, count 0 2006.201.05:43:51.01#ibcon#end of sib2, iclass 17, count 0 2006.201.05:43:51.01#ibcon#*after write, iclass 17, count 0 2006.201.05:43:51.01#ibcon#*before return 0, iclass 17, count 0 2006.201.05:43:51.01#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:51.01#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.05:43:51.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:43:51.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:43:51.01$vck44/vblo=7,734.99 2006.201.05:43:51.01#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.05:43:51.01#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.05:43:51.01#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:51.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:51.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:51.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:51.01#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:43:51.01#ibcon#first serial, iclass 19, count 0 2006.201.05:43:51.01#ibcon#enter sib2, iclass 19, count 0 2006.201.05:43:51.01#ibcon#flushed, iclass 19, count 0 2006.201.05:43:51.01#ibcon#about to write, iclass 19, count 0 2006.201.05:43:51.01#ibcon#wrote, iclass 19, count 0 2006.201.05:43:51.01#ibcon#about to read 3, iclass 19, count 0 2006.201.05:43:51.03#ibcon#read 3, iclass 19, count 0 2006.201.05:43:51.03#ibcon#about to read 4, iclass 19, count 0 2006.201.05:43:51.03#ibcon#read 4, iclass 19, count 0 2006.201.05:43:51.03#ibcon#about to read 5, iclass 19, count 0 2006.201.05:43:51.03#ibcon#read 5, iclass 19, count 0 2006.201.05:43:51.03#ibcon#about to read 6, iclass 19, count 0 2006.201.05:43:51.03#ibcon#read 6, iclass 19, count 0 2006.201.05:43:51.03#ibcon#end of sib2, iclass 19, count 0 2006.201.05:43:51.03#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:43:51.03#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:43:51.03#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:43:51.03#ibcon#*before write, iclass 19, count 0 2006.201.05:43:51.03#ibcon#enter sib2, iclass 19, count 0 2006.201.05:43:51.03#ibcon#flushed, iclass 19, count 0 2006.201.05:43:51.03#ibcon#about to write, iclass 19, count 0 2006.201.05:43:51.03#ibcon#wrote, iclass 19, count 0 2006.201.05:43:51.03#ibcon#about to read 3, iclass 19, count 0 2006.201.05:43:51.07#ibcon#read 3, iclass 19, count 0 2006.201.05:43:51.07#ibcon#about to read 4, iclass 19, count 0 2006.201.05:43:51.07#ibcon#read 4, iclass 19, count 0 2006.201.05:43:51.07#ibcon#about to read 5, iclass 19, count 0 2006.201.05:43:51.07#ibcon#read 5, iclass 19, count 0 2006.201.05:43:51.07#ibcon#about to read 6, iclass 19, count 0 2006.201.05:43:51.07#ibcon#read 6, iclass 19, count 0 2006.201.05:43:51.07#ibcon#end of sib2, iclass 19, count 0 2006.201.05:43:51.07#ibcon#*after write, iclass 19, count 0 2006.201.05:43:51.07#ibcon#*before return 0, iclass 19, count 0 2006.201.05:43:51.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:51.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.05:43:51.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:43:51.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:43:51.07$vck44/vb=7,4 2006.201.05:43:51.07#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.05:43:51.07#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.05:43:51.07#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:51.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:51.13#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:51.13#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:51.13#ibcon#enter wrdev, iclass 21, count 2 2006.201.05:43:51.13#ibcon#first serial, iclass 21, count 2 2006.201.05:43:51.13#ibcon#enter sib2, iclass 21, count 2 2006.201.05:43:51.13#ibcon#flushed, iclass 21, count 2 2006.201.05:43:51.13#ibcon#about to write, iclass 21, count 2 2006.201.05:43:51.13#ibcon#wrote, iclass 21, count 2 2006.201.05:43:51.13#ibcon#about to read 3, iclass 21, count 2 2006.201.05:43:51.15#ibcon#read 3, iclass 21, count 2 2006.201.05:43:51.15#ibcon#about to read 4, iclass 21, count 2 2006.201.05:43:51.15#ibcon#read 4, iclass 21, count 2 2006.201.05:43:51.15#ibcon#about to read 5, iclass 21, count 2 2006.201.05:43:51.15#ibcon#read 5, iclass 21, count 2 2006.201.05:43:51.15#ibcon#about to read 6, iclass 21, count 2 2006.201.05:43:51.15#ibcon#read 6, iclass 21, count 2 2006.201.05:43:51.15#ibcon#end of sib2, iclass 21, count 2 2006.201.05:43:51.15#ibcon#*mode == 0, iclass 21, count 2 2006.201.05:43:51.15#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.05:43:51.15#ibcon#[27=AT07-04\r\n] 2006.201.05:43:51.15#ibcon#*before write, iclass 21, count 2 2006.201.05:43:51.15#ibcon#enter sib2, iclass 21, count 2 2006.201.05:43:51.15#ibcon#flushed, iclass 21, count 2 2006.201.05:43:51.15#ibcon#about to write, iclass 21, count 2 2006.201.05:43:51.15#ibcon#wrote, iclass 21, count 2 2006.201.05:43:51.15#ibcon#about to read 3, iclass 21, count 2 2006.201.05:43:51.18#ibcon#read 3, iclass 21, count 2 2006.201.05:43:51.18#ibcon#about to read 4, iclass 21, count 2 2006.201.05:43:51.18#ibcon#read 4, iclass 21, count 2 2006.201.05:43:51.18#ibcon#about to read 5, iclass 21, count 2 2006.201.05:43:51.18#ibcon#read 5, iclass 21, count 2 2006.201.05:43:51.18#ibcon#about to read 6, iclass 21, count 2 2006.201.05:43:51.18#ibcon#read 6, iclass 21, count 2 2006.201.05:43:51.18#ibcon#end of sib2, iclass 21, count 2 2006.201.05:43:51.18#ibcon#*after write, iclass 21, count 2 2006.201.05:43:51.18#ibcon#*before return 0, iclass 21, count 2 2006.201.05:43:51.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:51.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.05:43:51.18#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.05:43:51.18#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:51.18#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:51.30#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:51.30#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:51.30#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:43:51.30#ibcon#first serial, iclass 21, count 0 2006.201.05:43:51.30#ibcon#enter sib2, iclass 21, count 0 2006.201.05:43:51.30#ibcon#flushed, iclass 21, count 0 2006.201.05:43:51.30#ibcon#about to write, iclass 21, count 0 2006.201.05:43:51.30#ibcon#wrote, iclass 21, count 0 2006.201.05:43:51.30#ibcon#about to read 3, iclass 21, count 0 2006.201.05:43:51.32#ibcon#read 3, iclass 21, count 0 2006.201.05:43:51.32#ibcon#about to read 4, iclass 21, count 0 2006.201.05:43:51.32#ibcon#read 4, iclass 21, count 0 2006.201.05:43:51.32#ibcon#about to read 5, iclass 21, count 0 2006.201.05:43:51.32#ibcon#read 5, iclass 21, count 0 2006.201.05:43:51.32#ibcon#about to read 6, iclass 21, count 0 2006.201.05:43:51.32#ibcon#read 6, iclass 21, count 0 2006.201.05:43:51.32#ibcon#end of sib2, iclass 21, count 0 2006.201.05:43:51.32#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:43:51.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:43:51.32#ibcon#[27=USB\r\n] 2006.201.05:43:51.32#ibcon#*before write, iclass 21, count 0 2006.201.05:43:51.32#ibcon#enter sib2, iclass 21, count 0 2006.201.05:43:51.32#ibcon#flushed, iclass 21, count 0 2006.201.05:43:51.32#ibcon#about to write, iclass 21, count 0 2006.201.05:43:51.32#ibcon#wrote, iclass 21, count 0 2006.201.05:43:51.32#ibcon#about to read 3, iclass 21, count 0 2006.201.05:43:51.35#ibcon#read 3, iclass 21, count 0 2006.201.05:43:51.35#ibcon#about to read 4, iclass 21, count 0 2006.201.05:43:51.35#ibcon#read 4, iclass 21, count 0 2006.201.05:43:51.35#ibcon#about to read 5, iclass 21, count 0 2006.201.05:43:51.35#ibcon#read 5, iclass 21, count 0 2006.201.05:43:51.35#ibcon#about to read 6, iclass 21, count 0 2006.201.05:43:51.35#ibcon#read 6, iclass 21, count 0 2006.201.05:43:51.35#ibcon#end of sib2, iclass 21, count 0 2006.201.05:43:51.35#ibcon#*after write, iclass 21, count 0 2006.201.05:43:51.35#ibcon#*before return 0, iclass 21, count 0 2006.201.05:43:51.35#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:51.35#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.05:43:51.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:43:51.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:43:51.35$vck44/vblo=8,744.99 2006.201.05:43:51.35#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.05:43:51.35#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.05:43:51.35#ibcon#ireg 17 cls_cnt 0 2006.201.05:43:51.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:51.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:51.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:51.35#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:43:51.35#ibcon#first serial, iclass 23, count 0 2006.201.05:43:51.35#ibcon#enter sib2, iclass 23, count 0 2006.201.05:43:51.35#ibcon#flushed, iclass 23, count 0 2006.201.05:43:51.35#ibcon#about to write, iclass 23, count 0 2006.201.05:43:51.35#ibcon#wrote, iclass 23, count 0 2006.201.05:43:51.35#ibcon#about to read 3, iclass 23, count 0 2006.201.05:43:51.37#ibcon#read 3, iclass 23, count 0 2006.201.05:43:51.37#ibcon#about to read 4, iclass 23, count 0 2006.201.05:43:51.37#ibcon#read 4, iclass 23, count 0 2006.201.05:43:51.37#ibcon#about to read 5, iclass 23, count 0 2006.201.05:43:51.37#ibcon#read 5, iclass 23, count 0 2006.201.05:43:51.37#ibcon#about to read 6, iclass 23, count 0 2006.201.05:43:51.37#ibcon#read 6, iclass 23, count 0 2006.201.05:43:51.37#ibcon#end of sib2, iclass 23, count 0 2006.201.05:43:51.37#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:43:51.37#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:43:51.37#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:43:51.37#ibcon#*before write, iclass 23, count 0 2006.201.05:43:51.37#ibcon#enter sib2, iclass 23, count 0 2006.201.05:43:51.37#ibcon#flushed, iclass 23, count 0 2006.201.05:43:51.37#ibcon#about to write, iclass 23, count 0 2006.201.05:43:51.37#ibcon#wrote, iclass 23, count 0 2006.201.05:43:51.37#ibcon#about to read 3, iclass 23, count 0 2006.201.05:43:51.41#ibcon#read 3, iclass 23, count 0 2006.201.05:43:51.41#ibcon#about to read 4, iclass 23, count 0 2006.201.05:43:51.41#ibcon#read 4, iclass 23, count 0 2006.201.05:43:51.41#ibcon#about to read 5, iclass 23, count 0 2006.201.05:43:51.41#ibcon#read 5, iclass 23, count 0 2006.201.05:43:51.41#ibcon#about to read 6, iclass 23, count 0 2006.201.05:43:51.41#ibcon#read 6, iclass 23, count 0 2006.201.05:43:51.41#ibcon#end of sib2, iclass 23, count 0 2006.201.05:43:51.41#ibcon#*after write, iclass 23, count 0 2006.201.05:43:51.41#ibcon#*before return 0, iclass 23, count 0 2006.201.05:43:51.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:51.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.05:43:51.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:43:51.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:43:51.41$vck44/vb=8,4 2006.201.05:43:51.41#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.05:43:51.41#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.05:43:51.41#ibcon#ireg 11 cls_cnt 2 2006.201.05:43:51.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:51.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:51.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:51.47#ibcon#enter wrdev, iclass 25, count 2 2006.201.05:43:51.47#ibcon#first serial, iclass 25, count 2 2006.201.05:43:51.47#ibcon#enter sib2, iclass 25, count 2 2006.201.05:43:51.47#ibcon#flushed, iclass 25, count 2 2006.201.05:43:51.47#ibcon#about to write, iclass 25, count 2 2006.201.05:43:51.47#ibcon#wrote, iclass 25, count 2 2006.201.05:43:51.47#ibcon#about to read 3, iclass 25, count 2 2006.201.05:43:51.49#ibcon#read 3, iclass 25, count 2 2006.201.05:43:51.49#ibcon#about to read 4, iclass 25, count 2 2006.201.05:43:51.49#ibcon#read 4, iclass 25, count 2 2006.201.05:43:51.49#ibcon#about to read 5, iclass 25, count 2 2006.201.05:43:51.49#ibcon#read 5, iclass 25, count 2 2006.201.05:43:51.49#ibcon#about to read 6, iclass 25, count 2 2006.201.05:43:51.49#ibcon#read 6, iclass 25, count 2 2006.201.05:43:51.49#ibcon#end of sib2, iclass 25, count 2 2006.201.05:43:51.49#ibcon#*mode == 0, iclass 25, count 2 2006.201.05:43:51.49#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.05:43:51.49#ibcon#[27=AT08-04\r\n] 2006.201.05:43:51.49#ibcon#*before write, iclass 25, count 2 2006.201.05:43:51.49#ibcon#enter sib2, iclass 25, count 2 2006.201.05:43:51.49#ibcon#flushed, iclass 25, count 2 2006.201.05:43:51.49#ibcon#about to write, iclass 25, count 2 2006.201.05:43:51.49#ibcon#wrote, iclass 25, count 2 2006.201.05:43:51.49#ibcon#about to read 3, iclass 25, count 2 2006.201.05:43:51.52#ibcon#read 3, iclass 25, count 2 2006.201.05:43:51.52#ibcon#about to read 4, iclass 25, count 2 2006.201.05:43:51.52#ibcon#read 4, iclass 25, count 2 2006.201.05:43:51.52#ibcon#about to read 5, iclass 25, count 2 2006.201.05:43:51.52#ibcon#read 5, iclass 25, count 2 2006.201.05:43:51.52#ibcon#about to read 6, iclass 25, count 2 2006.201.05:43:51.52#ibcon#read 6, iclass 25, count 2 2006.201.05:43:51.52#ibcon#end of sib2, iclass 25, count 2 2006.201.05:43:51.52#ibcon#*after write, iclass 25, count 2 2006.201.05:43:51.52#ibcon#*before return 0, iclass 25, count 2 2006.201.05:43:51.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:51.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.05:43:51.52#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.05:43:51.52#ibcon#ireg 7 cls_cnt 0 2006.201.05:43:51.52#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:51.64#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:51.64#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:51.64#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:43:51.64#ibcon#first serial, iclass 25, count 0 2006.201.05:43:51.64#ibcon#enter sib2, iclass 25, count 0 2006.201.05:43:51.64#ibcon#flushed, iclass 25, count 0 2006.201.05:43:51.64#ibcon#about to write, iclass 25, count 0 2006.201.05:43:51.64#ibcon#wrote, iclass 25, count 0 2006.201.05:43:51.64#ibcon#about to read 3, iclass 25, count 0 2006.201.05:43:51.66#ibcon#read 3, iclass 25, count 0 2006.201.05:43:51.66#ibcon#about to read 4, iclass 25, count 0 2006.201.05:43:51.66#ibcon#read 4, iclass 25, count 0 2006.201.05:43:51.66#ibcon#about to read 5, iclass 25, count 0 2006.201.05:43:51.66#ibcon#read 5, iclass 25, count 0 2006.201.05:43:51.66#ibcon#about to read 6, iclass 25, count 0 2006.201.05:43:51.66#ibcon#read 6, iclass 25, count 0 2006.201.05:43:51.66#ibcon#end of sib2, iclass 25, count 0 2006.201.05:43:51.66#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:43:51.66#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:43:51.66#ibcon#[27=USB\r\n] 2006.201.05:43:51.66#ibcon#*before write, iclass 25, count 0 2006.201.05:43:51.66#ibcon#enter sib2, iclass 25, count 0 2006.201.05:43:51.66#ibcon#flushed, iclass 25, count 0 2006.201.05:43:51.66#ibcon#about to write, iclass 25, count 0 2006.201.05:43:51.66#ibcon#wrote, iclass 25, count 0 2006.201.05:43:51.66#ibcon#about to read 3, iclass 25, count 0 2006.201.05:43:51.69#ibcon#read 3, iclass 25, count 0 2006.201.05:43:51.69#ibcon#about to read 4, iclass 25, count 0 2006.201.05:43:51.69#ibcon#read 4, iclass 25, count 0 2006.201.05:43:51.69#ibcon#about to read 5, iclass 25, count 0 2006.201.05:43:51.69#ibcon#read 5, iclass 25, count 0 2006.201.05:43:51.69#ibcon#about to read 6, iclass 25, count 0 2006.201.05:43:51.69#ibcon#read 6, iclass 25, count 0 2006.201.05:43:51.69#ibcon#end of sib2, iclass 25, count 0 2006.201.05:43:51.69#ibcon#*after write, iclass 25, count 0 2006.201.05:43:51.69#ibcon#*before return 0, iclass 25, count 0 2006.201.05:43:51.69#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:51.69#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.05:43:51.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:43:51.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:43:51.69$vck44/vabw=wide 2006.201.05:43:51.69#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.05:43:51.69#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.05:43:51.69#ibcon#ireg 8 cls_cnt 0 2006.201.05:43:51.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:51.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:51.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:51.69#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:43:51.69#ibcon#first serial, iclass 27, count 0 2006.201.05:43:51.69#ibcon#enter sib2, iclass 27, count 0 2006.201.05:43:51.69#ibcon#flushed, iclass 27, count 0 2006.201.05:43:51.69#ibcon#about to write, iclass 27, count 0 2006.201.05:43:51.69#ibcon#wrote, iclass 27, count 0 2006.201.05:43:51.69#ibcon#about to read 3, iclass 27, count 0 2006.201.05:43:51.71#ibcon#read 3, iclass 27, count 0 2006.201.05:43:51.71#ibcon#about to read 4, iclass 27, count 0 2006.201.05:43:51.71#ibcon#read 4, iclass 27, count 0 2006.201.05:43:51.71#ibcon#about to read 5, iclass 27, count 0 2006.201.05:43:51.71#ibcon#read 5, iclass 27, count 0 2006.201.05:43:51.71#ibcon#about to read 6, iclass 27, count 0 2006.201.05:43:51.71#ibcon#read 6, iclass 27, count 0 2006.201.05:43:51.71#ibcon#end of sib2, iclass 27, count 0 2006.201.05:43:51.71#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:43:51.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:43:51.71#ibcon#[25=BW32\r\n] 2006.201.05:43:51.71#ibcon#*before write, iclass 27, count 0 2006.201.05:43:51.71#ibcon#enter sib2, iclass 27, count 0 2006.201.05:43:51.71#ibcon#flushed, iclass 27, count 0 2006.201.05:43:51.71#ibcon#about to write, iclass 27, count 0 2006.201.05:43:51.71#ibcon#wrote, iclass 27, count 0 2006.201.05:43:51.71#ibcon#about to read 3, iclass 27, count 0 2006.201.05:43:51.74#ibcon#read 3, iclass 27, count 0 2006.201.05:43:51.74#ibcon#about to read 4, iclass 27, count 0 2006.201.05:43:51.74#ibcon#read 4, iclass 27, count 0 2006.201.05:43:51.74#ibcon#about to read 5, iclass 27, count 0 2006.201.05:43:51.74#ibcon#read 5, iclass 27, count 0 2006.201.05:43:51.74#ibcon#about to read 6, iclass 27, count 0 2006.201.05:43:51.74#ibcon#read 6, iclass 27, count 0 2006.201.05:43:51.74#ibcon#end of sib2, iclass 27, count 0 2006.201.05:43:51.74#ibcon#*after write, iclass 27, count 0 2006.201.05:43:51.74#ibcon#*before return 0, iclass 27, count 0 2006.201.05:43:51.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:51.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.05:43:51.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:43:51.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:43:51.74$vck44/vbbw=wide 2006.201.05:43:51.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:43:51.74#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:43:51.74#ibcon#ireg 8 cls_cnt 0 2006.201.05:43:51.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:43:51.81#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:43:51.81#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:43:51.81#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:43:51.81#ibcon#first serial, iclass 29, count 0 2006.201.05:43:51.81#ibcon#enter sib2, iclass 29, count 0 2006.201.05:43:51.81#ibcon#flushed, iclass 29, count 0 2006.201.05:43:51.81#ibcon#about to write, iclass 29, count 0 2006.201.05:43:51.81#ibcon#wrote, iclass 29, count 0 2006.201.05:43:51.81#ibcon#about to read 3, iclass 29, count 0 2006.201.05:43:51.83#ibcon#read 3, iclass 29, count 0 2006.201.05:43:51.83#ibcon#about to read 4, iclass 29, count 0 2006.201.05:43:51.83#ibcon#read 4, iclass 29, count 0 2006.201.05:43:51.83#ibcon#about to read 5, iclass 29, count 0 2006.201.05:43:51.83#ibcon#read 5, iclass 29, count 0 2006.201.05:43:51.83#ibcon#about to read 6, iclass 29, count 0 2006.201.05:43:51.83#ibcon#read 6, iclass 29, count 0 2006.201.05:43:51.83#ibcon#end of sib2, iclass 29, count 0 2006.201.05:43:51.83#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:43:51.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:43:51.83#ibcon#[27=BW32\r\n] 2006.201.05:43:51.83#ibcon#*before write, iclass 29, count 0 2006.201.05:43:51.83#ibcon#enter sib2, iclass 29, count 0 2006.201.05:43:51.83#ibcon#flushed, iclass 29, count 0 2006.201.05:43:51.83#ibcon#about to write, iclass 29, count 0 2006.201.05:43:51.83#ibcon#wrote, iclass 29, count 0 2006.201.05:43:51.83#ibcon#about to read 3, iclass 29, count 0 2006.201.05:43:51.86#ibcon#read 3, iclass 29, count 0 2006.201.05:43:51.86#ibcon#about to read 4, iclass 29, count 0 2006.201.05:43:51.86#ibcon#read 4, iclass 29, count 0 2006.201.05:43:51.86#ibcon#about to read 5, iclass 29, count 0 2006.201.05:43:51.86#ibcon#read 5, iclass 29, count 0 2006.201.05:43:51.86#ibcon#about to read 6, iclass 29, count 0 2006.201.05:43:51.86#ibcon#read 6, iclass 29, count 0 2006.201.05:43:51.86#ibcon#end of sib2, iclass 29, count 0 2006.201.05:43:51.86#ibcon#*after write, iclass 29, count 0 2006.201.05:43:51.91#ibcon#*before return 0, iclass 29, count 0 2006.201.05:43:51.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:43:51.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:43:51.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:43:51.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:43:51.91$setupk4/ifdk4 2006.201.05:43:51.91$ifdk4/lo= 2006.201.05:43:51.91$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:43:51.91$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:43:51.92$ifdk4/patch= 2006.201.05:43:51.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:43:51.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:43:51.92$setupk4/!*+20s 2006.201.05:43:57.09#abcon#<5=/04 2.4 4.7 23.05 901003.5\r\n> 2006.201.05:43:57.11#abcon#{5=INTERFACE CLEAR} 2006.201.05:43:57.17#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:44:06.28$setupk4/"tpicd 2006.201.05:44:06.28$setupk4/echo=off 2006.201.05:44:06.28$setupk4/xlog=off 2006.201.05:44:06.28:!2006.201.05:46:40 2006.201.05:44:41.14#trakl#Source acquired 2006.201.05:44:41.14#flagr#flagr/antenna,acquired 2006.201.05:46:40.00:preob 2006.201.05:46:40.13/onsource/TRACKING 2006.201.05:46:40.13:!2006.201.05:46:50 2006.201.05:46:50.00:"tape 2006.201.05:46:50.00:"st=record 2006.201.05:46:50.00:data_valid=on 2006.201.05:46:50.00:midob 2006.201.05:46:50.13/onsource/TRACKING 2006.201.05:46:50.13/wx/23.03,1003.5,92 2006.201.05:46:50.33/cable/+6.4657E-03 2006.201.05:46:51.42/va/01,08,usb,yes,29,32 2006.201.05:46:51.42/va/02,07,usb,yes,32,32 2006.201.05:46:51.42/va/03,08,usb,yes,29,30 2006.201.05:46:51.42/va/04,07,usb,yes,33,34 2006.201.05:46:51.42/va/05,04,usb,yes,29,29 2006.201.05:46:51.42/va/06,05,usb,yes,29,29 2006.201.05:46:51.42/va/07,05,usb,yes,28,29 2006.201.05:46:51.42/va/08,04,usb,yes,28,34 2006.201.05:46:51.65/valo/01,524.99,yes,locked 2006.201.05:46:51.65/valo/02,534.99,yes,locked 2006.201.05:46:51.65/valo/03,564.99,yes,locked 2006.201.05:46:51.65/valo/04,624.99,yes,locked 2006.201.05:46:51.65/valo/05,734.99,yes,locked 2006.201.05:46:51.65/valo/06,814.99,yes,locked 2006.201.05:46:51.65/valo/07,864.99,yes,locked 2006.201.05:46:51.65/valo/08,884.99,yes,locked 2006.201.05:46:52.74/vb/01,04,usb,yes,28,27 2006.201.05:46:52.74/vb/02,05,usb,yes,27,27 2006.201.05:46:52.74/vb/03,04,usb,yes,28,31 2006.201.05:46:52.74/vb/04,05,usb,yes,28,27 2006.201.05:46:52.74/vb/05,04,usb,yes,25,27 2006.201.05:46:52.74/vb/06,04,usb,yes,29,25 2006.201.05:46:52.74/vb/07,04,usb,yes,29,29 2006.201.05:46:52.74/vb/08,04,usb,yes,26,30 2006.201.05:46:52.97/vblo/01,629.99,yes,locked 2006.201.05:46:52.97/vblo/02,634.99,yes,locked 2006.201.05:46:52.97/vblo/03,649.99,yes,locked 2006.201.05:46:52.97/vblo/04,679.99,yes,locked 2006.201.05:46:52.97/vblo/05,709.99,yes,locked 2006.201.05:46:52.97/vblo/06,719.99,yes,locked 2006.201.05:46:52.97/vblo/07,734.99,yes,locked 2006.201.05:46:52.97/vblo/08,744.99,yes,locked 2006.201.05:46:53.12/vabw/8 2006.201.05:46:53.27/vbbw/8 2006.201.05:46:53.36/xfe/off,on,15.0 2006.201.05:46:53.75/ifatt/23,28,28,28 2006.201.05:46:54.05/fmout-gps/S +4.54E-07 2006.201.05:46:54.09:!2006.201.05:48:40 2006.201.05:48:40.00:data_valid=off 2006.201.05:48:40.00:"et 2006.201.05:48:40.00:!+3s 2006.201.05:48:43.02:"tape 2006.201.05:48:43.02:postob 2006.201.05:48:43.09/cable/+6.4672E-03 2006.201.05:48:43.09/wx/23.04,1003.5,90 2006.201.05:48:43.15/fmout-gps/S +4.53E-07 2006.201.05:48:43.15:scan_name=201-0550,jd0607,90 2006.201.05:48:43.15:source=3c274,123049.42,122328.0,2000.0,ccw 2006.201.05:48:44.14#flagr#flagr/antenna,new-source 2006.201.05:48:44.14:checkk5 2006.201.05:48:44.56/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:48:44.95/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:48:45.36/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:48:45.77/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:48:46.89/chk_obsdata//k5ts1/T2010546??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.201.05:48:47.27/chk_obsdata//k5ts2/T2010546??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.201.05:48:47.64/chk_obsdata//k5ts3/T2010546??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.201.05:48:48.02/chk_obsdata//k5ts4/T2010546??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.201.05:48:48.71/k5log//k5ts1_log_newline 2006.201.05:48:49.44/k5log//k5ts2_log_newline 2006.201.05:48:50.14/k5log//k5ts3_log_newline 2006.201.05:48:50.84/k5log//k5ts4_log_newline 2006.201.05:48:50.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:48:50.86:setupk4=1 2006.201.05:48:50.86$setupk4/echo=on 2006.201.05:48:50.86$setupk4/pcalon 2006.201.05:48:50.86$pcalon/"no phase cal control is implemented here 2006.201.05:48:50.86$setupk4/"tpicd=stop 2006.201.05:48:50.86$setupk4/"rec=synch_on 2006.201.05:48:50.86$setupk4/"rec_mode=128 2006.201.05:48:50.86$setupk4/!* 2006.201.05:48:50.86$setupk4/recpk4 2006.201.05:48:50.86$recpk4/recpatch= 2006.201.05:48:50.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:48:50.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:48:50.87$setupk4/vck44 2006.201.05:48:50.87$vck44/valo=1,524.99 2006.201.05:48:50.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.05:48:50.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.05:48:50.87#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:50.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:50.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:50.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:50.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.05:48:50.87#ibcon#first serial, iclass 4, count 0 2006.201.05:48:50.87#ibcon#enter sib2, iclass 4, count 0 2006.201.05:48:50.87#ibcon#flushed, iclass 4, count 0 2006.201.05:48:50.87#ibcon#about to write, iclass 4, count 0 2006.201.05:48:50.87#ibcon#wrote, iclass 4, count 0 2006.201.05:48:50.87#ibcon#about to read 3, iclass 4, count 0 2006.201.05:48:50.91#ibcon#read 3, iclass 4, count 0 2006.201.05:48:50.91#ibcon#about to read 4, iclass 4, count 0 2006.201.05:48:50.91#ibcon#read 4, iclass 4, count 0 2006.201.05:48:50.91#ibcon#about to read 5, iclass 4, count 0 2006.201.05:48:50.91#ibcon#read 5, iclass 4, count 0 2006.201.05:48:50.91#ibcon#about to read 6, iclass 4, count 0 2006.201.05:48:50.91#ibcon#read 6, iclass 4, count 0 2006.201.05:48:50.91#ibcon#end of sib2, iclass 4, count 0 2006.201.05:48:50.91#ibcon#*mode == 0, iclass 4, count 0 2006.201.05:48:50.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.05:48:50.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:48:50.91#ibcon#*before write, iclass 4, count 0 2006.201.05:48:50.91#ibcon#enter sib2, iclass 4, count 0 2006.201.05:48:50.91#ibcon#flushed, iclass 4, count 0 2006.201.05:48:50.91#ibcon#about to write, iclass 4, count 0 2006.201.05:48:50.91#ibcon#wrote, iclass 4, count 0 2006.201.05:48:50.91#ibcon#about to read 3, iclass 4, count 0 2006.201.05:48:50.96#ibcon#read 3, iclass 4, count 0 2006.201.05:48:50.96#ibcon#about to read 4, iclass 4, count 0 2006.201.05:48:50.96#ibcon#read 4, iclass 4, count 0 2006.201.05:48:50.96#ibcon#about to read 5, iclass 4, count 0 2006.201.05:48:50.96#ibcon#read 5, iclass 4, count 0 2006.201.05:48:50.96#ibcon#about to read 6, iclass 4, count 0 2006.201.05:48:50.96#ibcon#read 6, iclass 4, count 0 2006.201.05:48:50.96#ibcon#end of sib2, iclass 4, count 0 2006.201.05:48:50.96#ibcon#*after write, iclass 4, count 0 2006.201.05:48:50.96#ibcon#*before return 0, iclass 4, count 0 2006.201.05:48:50.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:50.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:50.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.05:48:50.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.05:48:50.96$vck44/va=1,8 2006.201.05:48:50.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.05:48:50.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.05:48:50.96#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:50.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:50.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:50.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:50.96#ibcon#enter wrdev, iclass 6, count 2 2006.201.05:48:50.96#ibcon#first serial, iclass 6, count 2 2006.201.05:48:50.96#ibcon#enter sib2, iclass 6, count 2 2006.201.05:48:50.96#ibcon#flushed, iclass 6, count 2 2006.201.05:48:50.96#ibcon#about to write, iclass 6, count 2 2006.201.05:48:50.96#ibcon#wrote, iclass 6, count 2 2006.201.05:48:50.96#ibcon#about to read 3, iclass 6, count 2 2006.201.05:48:50.98#ibcon#read 3, iclass 6, count 2 2006.201.05:48:50.98#ibcon#about to read 4, iclass 6, count 2 2006.201.05:48:50.98#ibcon#read 4, iclass 6, count 2 2006.201.05:48:50.98#ibcon#about to read 5, iclass 6, count 2 2006.201.05:48:50.98#ibcon#read 5, iclass 6, count 2 2006.201.05:48:50.98#ibcon#about to read 6, iclass 6, count 2 2006.201.05:48:50.98#ibcon#read 6, iclass 6, count 2 2006.201.05:48:50.98#ibcon#end of sib2, iclass 6, count 2 2006.201.05:48:50.98#ibcon#*mode == 0, iclass 6, count 2 2006.201.05:48:50.98#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.05:48:50.98#ibcon#[25=AT01-08\r\n] 2006.201.05:48:50.98#ibcon#*before write, iclass 6, count 2 2006.201.05:48:50.98#ibcon#enter sib2, iclass 6, count 2 2006.201.05:48:50.98#ibcon#flushed, iclass 6, count 2 2006.201.05:48:50.98#ibcon#about to write, iclass 6, count 2 2006.201.05:48:50.98#ibcon#wrote, iclass 6, count 2 2006.201.05:48:50.98#ibcon#about to read 3, iclass 6, count 2 2006.201.05:48:51.01#ibcon#read 3, iclass 6, count 2 2006.201.05:48:51.01#ibcon#about to read 4, iclass 6, count 2 2006.201.05:48:51.01#ibcon#read 4, iclass 6, count 2 2006.201.05:48:51.01#ibcon#about to read 5, iclass 6, count 2 2006.201.05:48:51.01#ibcon#read 5, iclass 6, count 2 2006.201.05:48:51.01#ibcon#about to read 6, iclass 6, count 2 2006.201.05:48:51.01#ibcon#read 6, iclass 6, count 2 2006.201.05:48:51.01#ibcon#end of sib2, iclass 6, count 2 2006.201.05:48:51.01#ibcon#*after write, iclass 6, count 2 2006.201.05:48:51.01#ibcon#*before return 0, iclass 6, count 2 2006.201.05:48:51.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:51.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:51.01#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.05:48:51.01#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:51.01#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:51.13#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:51.13#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:51.13#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:48:51.13#ibcon#first serial, iclass 6, count 0 2006.201.05:48:51.13#ibcon#enter sib2, iclass 6, count 0 2006.201.05:48:51.13#ibcon#flushed, iclass 6, count 0 2006.201.05:48:51.13#ibcon#about to write, iclass 6, count 0 2006.201.05:48:51.13#ibcon#wrote, iclass 6, count 0 2006.201.05:48:51.13#ibcon#about to read 3, iclass 6, count 0 2006.201.05:48:51.15#ibcon#read 3, iclass 6, count 0 2006.201.05:48:51.15#ibcon#about to read 4, iclass 6, count 0 2006.201.05:48:51.15#ibcon#read 4, iclass 6, count 0 2006.201.05:48:51.15#ibcon#about to read 5, iclass 6, count 0 2006.201.05:48:51.15#ibcon#read 5, iclass 6, count 0 2006.201.05:48:51.15#ibcon#about to read 6, iclass 6, count 0 2006.201.05:48:51.15#ibcon#read 6, iclass 6, count 0 2006.201.05:48:51.15#ibcon#end of sib2, iclass 6, count 0 2006.201.05:48:51.15#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:48:51.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:48:51.15#ibcon#[25=USB\r\n] 2006.201.05:48:51.15#ibcon#*before write, iclass 6, count 0 2006.201.05:48:51.15#ibcon#enter sib2, iclass 6, count 0 2006.201.05:48:51.15#ibcon#flushed, iclass 6, count 0 2006.201.05:48:51.15#ibcon#about to write, iclass 6, count 0 2006.201.05:48:51.15#ibcon#wrote, iclass 6, count 0 2006.201.05:48:51.15#ibcon#about to read 3, iclass 6, count 0 2006.201.05:48:51.18#ibcon#read 3, iclass 6, count 0 2006.201.05:48:51.18#ibcon#about to read 4, iclass 6, count 0 2006.201.05:48:51.18#ibcon#read 4, iclass 6, count 0 2006.201.05:48:51.18#ibcon#about to read 5, iclass 6, count 0 2006.201.05:48:51.18#ibcon#read 5, iclass 6, count 0 2006.201.05:48:51.18#ibcon#about to read 6, iclass 6, count 0 2006.201.05:48:51.18#ibcon#read 6, iclass 6, count 0 2006.201.05:48:51.18#ibcon#end of sib2, iclass 6, count 0 2006.201.05:48:51.18#ibcon#*after write, iclass 6, count 0 2006.201.05:48:51.18#ibcon#*before return 0, iclass 6, count 0 2006.201.05:48:51.18#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:51.18#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:51.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:48:51.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:48:51.18$vck44/valo=2,534.99 2006.201.05:48:51.18#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.05:48:51.18#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.05:48:51.18#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:51.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:51.18#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:51.18#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:51.18#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:48:51.18#ibcon#first serial, iclass 10, count 0 2006.201.05:48:51.18#ibcon#enter sib2, iclass 10, count 0 2006.201.05:48:51.18#ibcon#flushed, iclass 10, count 0 2006.201.05:48:51.18#ibcon#about to write, iclass 10, count 0 2006.201.05:48:51.18#ibcon#wrote, iclass 10, count 0 2006.201.05:48:51.18#ibcon#about to read 3, iclass 10, count 0 2006.201.05:48:51.20#ibcon#read 3, iclass 10, count 0 2006.201.05:48:51.20#ibcon#about to read 4, iclass 10, count 0 2006.201.05:48:51.20#ibcon#read 4, iclass 10, count 0 2006.201.05:48:51.20#ibcon#about to read 5, iclass 10, count 0 2006.201.05:48:51.20#ibcon#read 5, iclass 10, count 0 2006.201.05:48:51.20#ibcon#about to read 6, iclass 10, count 0 2006.201.05:48:51.20#ibcon#read 6, iclass 10, count 0 2006.201.05:48:51.20#ibcon#end of sib2, iclass 10, count 0 2006.201.05:48:51.20#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:48:51.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:48:51.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:48:51.20#ibcon#*before write, iclass 10, count 0 2006.201.05:48:51.20#ibcon#enter sib2, iclass 10, count 0 2006.201.05:48:51.20#ibcon#flushed, iclass 10, count 0 2006.201.05:48:51.20#ibcon#about to write, iclass 10, count 0 2006.201.05:48:51.20#ibcon#wrote, iclass 10, count 0 2006.201.05:48:51.20#ibcon#about to read 3, iclass 10, count 0 2006.201.05:48:51.24#ibcon#read 3, iclass 10, count 0 2006.201.05:48:51.24#ibcon#about to read 4, iclass 10, count 0 2006.201.05:48:51.24#ibcon#read 4, iclass 10, count 0 2006.201.05:48:51.24#ibcon#about to read 5, iclass 10, count 0 2006.201.05:48:51.24#ibcon#read 5, iclass 10, count 0 2006.201.05:48:51.24#ibcon#about to read 6, iclass 10, count 0 2006.201.05:48:51.24#ibcon#read 6, iclass 10, count 0 2006.201.05:48:51.24#ibcon#end of sib2, iclass 10, count 0 2006.201.05:48:51.24#ibcon#*after write, iclass 10, count 0 2006.201.05:48:51.24#ibcon#*before return 0, iclass 10, count 0 2006.201.05:48:51.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:51.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:51.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:48:51.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:48:51.24$vck44/va=2,7 2006.201.05:48:51.24#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.05:48:51.24#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.05:48:51.24#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:51.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:51.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:51.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:51.30#ibcon#enter wrdev, iclass 12, count 2 2006.201.05:48:51.30#ibcon#first serial, iclass 12, count 2 2006.201.05:48:51.30#ibcon#enter sib2, iclass 12, count 2 2006.201.05:48:51.30#ibcon#flushed, iclass 12, count 2 2006.201.05:48:51.30#ibcon#about to write, iclass 12, count 2 2006.201.05:48:51.30#ibcon#wrote, iclass 12, count 2 2006.201.05:48:51.30#ibcon#about to read 3, iclass 12, count 2 2006.201.05:48:51.32#ibcon#read 3, iclass 12, count 2 2006.201.05:48:51.32#ibcon#about to read 4, iclass 12, count 2 2006.201.05:48:51.32#ibcon#read 4, iclass 12, count 2 2006.201.05:48:51.32#ibcon#about to read 5, iclass 12, count 2 2006.201.05:48:51.32#ibcon#read 5, iclass 12, count 2 2006.201.05:48:51.32#ibcon#about to read 6, iclass 12, count 2 2006.201.05:48:51.32#ibcon#read 6, iclass 12, count 2 2006.201.05:48:51.32#ibcon#end of sib2, iclass 12, count 2 2006.201.05:48:51.32#ibcon#*mode == 0, iclass 12, count 2 2006.201.05:48:51.32#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.05:48:51.32#ibcon#[25=AT02-07\r\n] 2006.201.05:48:51.32#ibcon#*before write, iclass 12, count 2 2006.201.05:48:51.32#ibcon#enter sib2, iclass 12, count 2 2006.201.05:48:51.32#ibcon#flushed, iclass 12, count 2 2006.201.05:48:51.32#ibcon#about to write, iclass 12, count 2 2006.201.05:48:51.32#ibcon#wrote, iclass 12, count 2 2006.201.05:48:51.32#ibcon#about to read 3, iclass 12, count 2 2006.201.05:48:51.35#ibcon#read 3, iclass 12, count 2 2006.201.05:48:51.35#ibcon#about to read 4, iclass 12, count 2 2006.201.05:48:51.35#ibcon#read 4, iclass 12, count 2 2006.201.05:48:51.35#ibcon#about to read 5, iclass 12, count 2 2006.201.05:48:51.35#ibcon#read 5, iclass 12, count 2 2006.201.05:48:51.35#ibcon#about to read 6, iclass 12, count 2 2006.201.05:48:51.35#ibcon#read 6, iclass 12, count 2 2006.201.05:48:51.35#ibcon#end of sib2, iclass 12, count 2 2006.201.05:48:51.35#ibcon#*after write, iclass 12, count 2 2006.201.05:48:51.35#ibcon#*before return 0, iclass 12, count 2 2006.201.05:48:51.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:51.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:51.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.05:48:51.35#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:51.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:51.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:51.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:51.47#ibcon#enter wrdev, iclass 12, count 0 2006.201.05:48:51.47#ibcon#first serial, iclass 12, count 0 2006.201.05:48:51.47#ibcon#enter sib2, iclass 12, count 0 2006.201.05:48:51.47#ibcon#flushed, iclass 12, count 0 2006.201.05:48:51.47#ibcon#about to write, iclass 12, count 0 2006.201.05:48:51.47#ibcon#wrote, iclass 12, count 0 2006.201.05:48:51.47#ibcon#about to read 3, iclass 12, count 0 2006.201.05:48:51.49#ibcon#read 3, iclass 12, count 0 2006.201.05:48:51.49#ibcon#about to read 4, iclass 12, count 0 2006.201.05:48:51.49#ibcon#read 4, iclass 12, count 0 2006.201.05:48:51.49#ibcon#about to read 5, iclass 12, count 0 2006.201.05:48:51.49#ibcon#read 5, iclass 12, count 0 2006.201.05:48:51.49#ibcon#about to read 6, iclass 12, count 0 2006.201.05:48:51.49#ibcon#read 6, iclass 12, count 0 2006.201.05:48:51.49#ibcon#end of sib2, iclass 12, count 0 2006.201.05:48:51.49#ibcon#*mode == 0, iclass 12, count 0 2006.201.05:48:51.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.05:48:51.49#ibcon#[25=USB\r\n] 2006.201.05:48:51.49#ibcon#*before write, iclass 12, count 0 2006.201.05:48:51.49#ibcon#enter sib2, iclass 12, count 0 2006.201.05:48:51.49#ibcon#flushed, iclass 12, count 0 2006.201.05:48:51.49#ibcon#about to write, iclass 12, count 0 2006.201.05:48:51.49#ibcon#wrote, iclass 12, count 0 2006.201.05:48:51.49#ibcon#about to read 3, iclass 12, count 0 2006.201.05:48:51.52#ibcon#read 3, iclass 12, count 0 2006.201.05:48:51.52#ibcon#about to read 4, iclass 12, count 0 2006.201.05:48:51.52#ibcon#read 4, iclass 12, count 0 2006.201.05:48:51.52#ibcon#about to read 5, iclass 12, count 0 2006.201.05:48:51.52#ibcon#read 5, iclass 12, count 0 2006.201.05:48:51.52#ibcon#about to read 6, iclass 12, count 0 2006.201.05:48:51.52#ibcon#read 6, iclass 12, count 0 2006.201.05:48:51.52#ibcon#end of sib2, iclass 12, count 0 2006.201.05:48:51.52#ibcon#*after write, iclass 12, count 0 2006.201.05:48:51.52#ibcon#*before return 0, iclass 12, count 0 2006.201.05:48:51.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:51.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:51.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.05:48:51.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.05:48:51.52$vck44/valo=3,564.99 2006.201.05:48:51.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.05:48:51.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.05:48:51.52#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:51.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:51.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:51.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:51.52#ibcon#enter wrdev, iclass 14, count 0 2006.201.05:48:51.52#ibcon#first serial, iclass 14, count 0 2006.201.05:48:51.52#ibcon#enter sib2, iclass 14, count 0 2006.201.05:48:51.52#ibcon#flushed, iclass 14, count 0 2006.201.05:48:51.52#ibcon#about to write, iclass 14, count 0 2006.201.05:48:51.52#ibcon#wrote, iclass 14, count 0 2006.201.05:48:51.52#ibcon#about to read 3, iclass 14, count 0 2006.201.05:48:51.54#ibcon#read 3, iclass 14, count 0 2006.201.05:48:51.54#ibcon#about to read 4, iclass 14, count 0 2006.201.05:48:51.54#ibcon#read 4, iclass 14, count 0 2006.201.05:48:51.54#ibcon#about to read 5, iclass 14, count 0 2006.201.05:48:51.54#ibcon#read 5, iclass 14, count 0 2006.201.05:48:51.54#ibcon#about to read 6, iclass 14, count 0 2006.201.05:48:51.54#ibcon#read 6, iclass 14, count 0 2006.201.05:48:51.54#ibcon#end of sib2, iclass 14, count 0 2006.201.05:48:51.54#ibcon#*mode == 0, iclass 14, count 0 2006.201.05:48:51.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.05:48:51.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:48:51.54#ibcon#*before write, iclass 14, count 0 2006.201.05:48:51.54#ibcon#enter sib2, iclass 14, count 0 2006.201.05:48:51.54#ibcon#flushed, iclass 14, count 0 2006.201.05:48:51.54#ibcon#about to write, iclass 14, count 0 2006.201.05:48:51.54#ibcon#wrote, iclass 14, count 0 2006.201.05:48:51.54#ibcon#about to read 3, iclass 14, count 0 2006.201.05:48:51.58#ibcon#read 3, iclass 14, count 0 2006.201.05:48:51.58#ibcon#about to read 4, iclass 14, count 0 2006.201.05:48:51.58#ibcon#read 4, iclass 14, count 0 2006.201.05:48:51.58#ibcon#about to read 5, iclass 14, count 0 2006.201.05:48:51.58#ibcon#read 5, iclass 14, count 0 2006.201.05:48:51.58#ibcon#about to read 6, iclass 14, count 0 2006.201.05:48:51.58#ibcon#read 6, iclass 14, count 0 2006.201.05:48:51.58#ibcon#end of sib2, iclass 14, count 0 2006.201.05:48:51.58#ibcon#*after write, iclass 14, count 0 2006.201.05:48:51.58#ibcon#*before return 0, iclass 14, count 0 2006.201.05:48:51.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:51.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:51.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.05:48:51.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.05:48:51.58$vck44/va=3,8 2006.201.05:48:51.58#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.05:48:51.58#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.05:48:51.58#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:51.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:51.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:51.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:51.64#ibcon#enter wrdev, iclass 16, count 2 2006.201.05:48:51.64#ibcon#first serial, iclass 16, count 2 2006.201.05:48:51.64#ibcon#enter sib2, iclass 16, count 2 2006.201.05:48:51.64#ibcon#flushed, iclass 16, count 2 2006.201.05:48:51.64#ibcon#about to write, iclass 16, count 2 2006.201.05:48:51.64#ibcon#wrote, iclass 16, count 2 2006.201.05:48:51.64#ibcon#about to read 3, iclass 16, count 2 2006.201.05:48:51.66#ibcon#read 3, iclass 16, count 2 2006.201.05:48:51.66#ibcon#about to read 4, iclass 16, count 2 2006.201.05:48:51.66#ibcon#read 4, iclass 16, count 2 2006.201.05:48:51.66#ibcon#about to read 5, iclass 16, count 2 2006.201.05:48:51.66#ibcon#read 5, iclass 16, count 2 2006.201.05:48:51.66#ibcon#about to read 6, iclass 16, count 2 2006.201.05:48:51.66#ibcon#read 6, iclass 16, count 2 2006.201.05:48:51.66#ibcon#end of sib2, iclass 16, count 2 2006.201.05:48:51.66#ibcon#*mode == 0, iclass 16, count 2 2006.201.05:48:51.66#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.05:48:51.66#ibcon#[25=AT03-08\r\n] 2006.201.05:48:51.66#ibcon#*before write, iclass 16, count 2 2006.201.05:48:51.66#ibcon#enter sib2, iclass 16, count 2 2006.201.05:48:51.66#ibcon#flushed, iclass 16, count 2 2006.201.05:48:51.66#ibcon#about to write, iclass 16, count 2 2006.201.05:48:51.66#ibcon#wrote, iclass 16, count 2 2006.201.05:48:51.66#ibcon#about to read 3, iclass 16, count 2 2006.201.05:48:51.69#ibcon#read 3, iclass 16, count 2 2006.201.05:48:51.69#ibcon#about to read 4, iclass 16, count 2 2006.201.05:48:51.69#ibcon#read 4, iclass 16, count 2 2006.201.05:48:51.69#ibcon#about to read 5, iclass 16, count 2 2006.201.05:48:51.69#ibcon#read 5, iclass 16, count 2 2006.201.05:48:51.69#ibcon#about to read 6, iclass 16, count 2 2006.201.05:48:51.69#ibcon#read 6, iclass 16, count 2 2006.201.05:48:51.69#ibcon#end of sib2, iclass 16, count 2 2006.201.05:48:51.69#ibcon#*after write, iclass 16, count 2 2006.201.05:48:51.69#ibcon#*before return 0, iclass 16, count 2 2006.201.05:48:51.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:51.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:51.69#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.05:48:51.69#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:51.69#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:51.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:51.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:51.81#ibcon#enter wrdev, iclass 16, count 0 2006.201.05:48:51.81#ibcon#first serial, iclass 16, count 0 2006.201.05:48:51.81#ibcon#enter sib2, iclass 16, count 0 2006.201.05:48:51.81#ibcon#flushed, iclass 16, count 0 2006.201.05:48:51.81#ibcon#about to write, iclass 16, count 0 2006.201.05:48:51.81#ibcon#wrote, iclass 16, count 0 2006.201.05:48:51.81#ibcon#about to read 3, iclass 16, count 0 2006.201.05:48:51.83#ibcon#read 3, iclass 16, count 0 2006.201.05:48:51.83#ibcon#about to read 4, iclass 16, count 0 2006.201.05:48:51.83#ibcon#read 4, iclass 16, count 0 2006.201.05:48:51.83#ibcon#about to read 5, iclass 16, count 0 2006.201.05:48:51.83#ibcon#read 5, iclass 16, count 0 2006.201.05:48:51.83#ibcon#about to read 6, iclass 16, count 0 2006.201.05:48:51.83#ibcon#read 6, iclass 16, count 0 2006.201.05:48:51.83#ibcon#end of sib2, iclass 16, count 0 2006.201.05:48:51.83#ibcon#*mode == 0, iclass 16, count 0 2006.201.05:48:51.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.05:48:51.83#ibcon#[25=USB\r\n] 2006.201.05:48:51.83#ibcon#*before write, iclass 16, count 0 2006.201.05:48:51.83#ibcon#enter sib2, iclass 16, count 0 2006.201.05:48:51.83#ibcon#flushed, iclass 16, count 0 2006.201.05:48:51.83#ibcon#about to write, iclass 16, count 0 2006.201.05:48:51.83#ibcon#wrote, iclass 16, count 0 2006.201.05:48:51.83#ibcon#about to read 3, iclass 16, count 0 2006.201.05:48:51.86#ibcon#read 3, iclass 16, count 0 2006.201.05:48:51.86#ibcon#about to read 4, iclass 16, count 0 2006.201.05:48:51.86#ibcon#read 4, iclass 16, count 0 2006.201.05:48:51.86#ibcon#about to read 5, iclass 16, count 0 2006.201.05:48:51.86#ibcon#read 5, iclass 16, count 0 2006.201.05:48:51.86#ibcon#about to read 6, iclass 16, count 0 2006.201.05:48:51.86#ibcon#read 6, iclass 16, count 0 2006.201.05:48:51.86#ibcon#end of sib2, iclass 16, count 0 2006.201.05:48:51.86#ibcon#*after write, iclass 16, count 0 2006.201.05:48:51.86#ibcon#*before return 0, iclass 16, count 0 2006.201.05:48:51.86#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:51.86#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:51.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.05:48:51.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.05:48:51.86$vck44/valo=4,624.99 2006.201.05:48:51.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.05:48:51.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.05:48:51.86#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:51.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:51.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:51.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:51.86#ibcon#enter wrdev, iclass 18, count 0 2006.201.05:48:51.86#ibcon#first serial, iclass 18, count 0 2006.201.05:48:51.86#ibcon#enter sib2, iclass 18, count 0 2006.201.05:48:51.86#ibcon#flushed, iclass 18, count 0 2006.201.05:48:51.86#ibcon#about to write, iclass 18, count 0 2006.201.05:48:51.86#ibcon#wrote, iclass 18, count 0 2006.201.05:48:51.86#ibcon#about to read 3, iclass 18, count 0 2006.201.05:48:51.88#ibcon#read 3, iclass 18, count 0 2006.201.05:48:51.88#ibcon#about to read 4, iclass 18, count 0 2006.201.05:48:51.88#ibcon#read 4, iclass 18, count 0 2006.201.05:48:51.88#ibcon#about to read 5, iclass 18, count 0 2006.201.05:48:51.88#ibcon#read 5, iclass 18, count 0 2006.201.05:48:51.88#ibcon#about to read 6, iclass 18, count 0 2006.201.05:48:51.88#ibcon#read 6, iclass 18, count 0 2006.201.05:48:51.88#ibcon#end of sib2, iclass 18, count 0 2006.201.05:48:51.88#ibcon#*mode == 0, iclass 18, count 0 2006.201.05:48:51.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.05:48:51.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:48:51.88#ibcon#*before write, iclass 18, count 0 2006.201.05:48:51.88#ibcon#enter sib2, iclass 18, count 0 2006.201.05:48:51.88#ibcon#flushed, iclass 18, count 0 2006.201.05:48:51.88#ibcon#about to write, iclass 18, count 0 2006.201.05:48:51.88#ibcon#wrote, iclass 18, count 0 2006.201.05:48:51.88#ibcon#about to read 3, iclass 18, count 0 2006.201.05:48:51.92#ibcon#read 3, iclass 18, count 0 2006.201.05:48:51.92#ibcon#about to read 4, iclass 18, count 0 2006.201.05:48:51.92#ibcon#read 4, iclass 18, count 0 2006.201.05:48:51.92#ibcon#about to read 5, iclass 18, count 0 2006.201.05:48:51.92#ibcon#read 5, iclass 18, count 0 2006.201.05:48:51.92#ibcon#about to read 6, iclass 18, count 0 2006.201.05:48:51.92#ibcon#read 6, iclass 18, count 0 2006.201.05:48:51.92#ibcon#end of sib2, iclass 18, count 0 2006.201.05:48:51.92#ibcon#*after write, iclass 18, count 0 2006.201.05:48:51.92#ibcon#*before return 0, iclass 18, count 0 2006.201.05:48:51.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:51.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:51.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.05:48:51.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.05:48:51.92$vck44/va=4,7 2006.201.05:48:51.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.05:48:51.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.05:48:51.92#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:51.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:51.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:51.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:51.98#ibcon#enter wrdev, iclass 20, count 2 2006.201.05:48:51.98#ibcon#first serial, iclass 20, count 2 2006.201.05:48:51.98#ibcon#enter sib2, iclass 20, count 2 2006.201.05:48:51.98#ibcon#flushed, iclass 20, count 2 2006.201.05:48:51.98#ibcon#about to write, iclass 20, count 2 2006.201.05:48:51.98#ibcon#wrote, iclass 20, count 2 2006.201.05:48:51.98#ibcon#about to read 3, iclass 20, count 2 2006.201.05:48:52.00#ibcon#read 3, iclass 20, count 2 2006.201.05:48:52.00#ibcon#about to read 4, iclass 20, count 2 2006.201.05:48:52.00#ibcon#read 4, iclass 20, count 2 2006.201.05:48:52.00#ibcon#about to read 5, iclass 20, count 2 2006.201.05:48:52.00#ibcon#read 5, iclass 20, count 2 2006.201.05:48:52.00#ibcon#about to read 6, iclass 20, count 2 2006.201.05:48:52.00#ibcon#read 6, iclass 20, count 2 2006.201.05:48:52.00#ibcon#end of sib2, iclass 20, count 2 2006.201.05:48:52.00#ibcon#*mode == 0, iclass 20, count 2 2006.201.05:48:52.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.05:48:52.00#ibcon#[25=AT04-07\r\n] 2006.201.05:48:52.00#ibcon#*before write, iclass 20, count 2 2006.201.05:48:52.00#ibcon#enter sib2, iclass 20, count 2 2006.201.05:48:52.00#ibcon#flushed, iclass 20, count 2 2006.201.05:48:52.00#ibcon#about to write, iclass 20, count 2 2006.201.05:48:52.00#ibcon#wrote, iclass 20, count 2 2006.201.05:48:52.00#ibcon#about to read 3, iclass 20, count 2 2006.201.05:48:52.02#abcon#<5=/04 2.5 4.7 23.03 901003.5\r\n> 2006.201.05:48:52.03#ibcon#read 3, iclass 20, count 2 2006.201.05:48:52.03#ibcon#about to read 4, iclass 20, count 2 2006.201.05:48:52.03#ibcon#read 4, iclass 20, count 2 2006.201.05:48:52.03#ibcon#about to read 5, iclass 20, count 2 2006.201.05:48:52.03#ibcon#read 5, iclass 20, count 2 2006.201.05:48:52.03#ibcon#about to read 6, iclass 20, count 2 2006.201.05:48:52.03#ibcon#read 6, iclass 20, count 2 2006.201.05:48:52.03#ibcon#end of sib2, iclass 20, count 2 2006.201.05:48:52.03#ibcon#*after write, iclass 20, count 2 2006.201.05:48:52.03#ibcon#*before return 0, iclass 20, count 2 2006.201.05:48:52.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:52.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:52.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.05:48:52.03#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:52.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:52.04#abcon#{5=INTERFACE CLEAR} 2006.201.05:48:52.10#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:48:52.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:52.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:52.15#ibcon#enter wrdev, iclass 20, count 0 2006.201.05:48:52.15#ibcon#first serial, iclass 20, count 0 2006.201.05:48:52.15#ibcon#enter sib2, iclass 20, count 0 2006.201.05:48:52.15#ibcon#flushed, iclass 20, count 0 2006.201.05:48:52.15#ibcon#about to write, iclass 20, count 0 2006.201.05:48:52.15#ibcon#wrote, iclass 20, count 0 2006.201.05:48:52.15#ibcon#about to read 3, iclass 20, count 0 2006.201.05:48:52.17#ibcon#read 3, iclass 20, count 0 2006.201.05:48:52.17#ibcon#about to read 4, iclass 20, count 0 2006.201.05:48:52.17#ibcon#read 4, iclass 20, count 0 2006.201.05:48:52.17#ibcon#about to read 5, iclass 20, count 0 2006.201.05:48:52.17#ibcon#read 5, iclass 20, count 0 2006.201.05:48:52.17#ibcon#about to read 6, iclass 20, count 0 2006.201.05:48:52.17#ibcon#read 6, iclass 20, count 0 2006.201.05:48:52.17#ibcon#end of sib2, iclass 20, count 0 2006.201.05:48:52.17#ibcon#*mode == 0, iclass 20, count 0 2006.201.05:48:52.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.05:48:52.17#ibcon#[25=USB\r\n] 2006.201.05:48:52.17#ibcon#*before write, iclass 20, count 0 2006.201.05:48:52.17#ibcon#enter sib2, iclass 20, count 0 2006.201.05:48:52.17#ibcon#flushed, iclass 20, count 0 2006.201.05:48:52.17#ibcon#about to write, iclass 20, count 0 2006.201.05:48:52.17#ibcon#wrote, iclass 20, count 0 2006.201.05:48:52.17#ibcon#about to read 3, iclass 20, count 0 2006.201.05:48:52.21#ibcon#read 3, iclass 20, count 0 2006.201.05:48:52.21#ibcon#about to read 4, iclass 20, count 0 2006.201.05:48:52.21#ibcon#read 4, iclass 20, count 0 2006.201.05:48:52.21#ibcon#about to read 5, iclass 20, count 0 2006.201.05:48:52.21#ibcon#read 5, iclass 20, count 0 2006.201.05:48:52.21#ibcon#about to read 6, iclass 20, count 0 2006.201.05:48:52.21#ibcon#read 6, iclass 20, count 0 2006.201.05:48:52.21#ibcon#end of sib2, iclass 20, count 0 2006.201.05:48:52.21#ibcon#*after write, iclass 20, count 0 2006.201.05:48:52.21#ibcon#*before return 0, iclass 20, count 0 2006.201.05:48:52.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:52.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:52.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.05:48:52.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.05:48:52.21$vck44/valo=5,734.99 2006.201.05:48:52.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.05:48:52.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.05:48:52.21#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:52.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:52.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:52.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:52.21#ibcon#enter wrdev, iclass 26, count 0 2006.201.05:48:52.21#ibcon#first serial, iclass 26, count 0 2006.201.05:48:52.21#ibcon#enter sib2, iclass 26, count 0 2006.201.05:48:52.21#ibcon#flushed, iclass 26, count 0 2006.201.05:48:52.21#ibcon#about to write, iclass 26, count 0 2006.201.05:48:52.21#ibcon#wrote, iclass 26, count 0 2006.201.05:48:52.21#ibcon#about to read 3, iclass 26, count 0 2006.201.05:48:52.23#ibcon#read 3, iclass 26, count 0 2006.201.05:48:52.23#ibcon#about to read 4, iclass 26, count 0 2006.201.05:48:52.23#ibcon#read 4, iclass 26, count 0 2006.201.05:48:52.23#ibcon#about to read 5, iclass 26, count 0 2006.201.05:48:52.23#ibcon#read 5, iclass 26, count 0 2006.201.05:48:52.23#ibcon#about to read 6, iclass 26, count 0 2006.201.05:48:52.23#ibcon#read 6, iclass 26, count 0 2006.201.05:48:52.23#ibcon#end of sib2, iclass 26, count 0 2006.201.05:48:52.23#ibcon#*mode == 0, iclass 26, count 0 2006.201.05:48:52.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.05:48:52.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:48:52.23#ibcon#*before write, iclass 26, count 0 2006.201.05:48:52.23#ibcon#enter sib2, iclass 26, count 0 2006.201.05:48:52.23#ibcon#flushed, iclass 26, count 0 2006.201.05:48:52.23#ibcon#about to write, iclass 26, count 0 2006.201.05:48:52.23#ibcon#wrote, iclass 26, count 0 2006.201.05:48:52.23#ibcon#about to read 3, iclass 26, count 0 2006.201.05:48:52.27#ibcon#read 3, iclass 26, count 0 2006.201.05:48:52.27#ibcon#about to read 4, iclass 26, count 0 2006.201.05:48:52.27#ibcon#read 4, iclass 26, count 0 2006.201.05:48:52.27#ibcon#about to read 5, iclass 26, count 0 2006.201.05:48:52.27#ibcon#read 5, iclass 26, count 0 2006.201.05:48:52.27#ibcon#about to read 6, iclass 26, count 0 2006.201.05:48:52.27#ibcon#read 6, iclass 26, count 0 2006.201.05:48:52.27#ibcon#end of sib2, iclass 26, count 0 2006.201.05:48:52.27#ibcon#*after write, iclass 26, count 0 2006.201.05:48:52.27#ibcon#*before return 0, iclass 26, count 0 2006.201.05:48:52.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:52.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:52.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.05:48:52.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.05:48:52.27$vck44/va=5,4 2006.201.05:48:52.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.05:48:52.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.05:48:52.27#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:52.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:52.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:52.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:52.33#ibcon#enter wrdev, iclass 28, count 2 2006.201.05:48:52.33#ibcon#first serial, iclass 28, count 2 2006.201.05:48:52.33#ibcon#enter sib2, iclass 28, count 2 2006.201.05:48:52.33#ibcon#flushed, iclass 28, count 2 2006.201.05:48:52.33#ibcon#about to write, iclass 28, count 2 2006.201.05:48:52.33#ibcon#wrote, iclass 28, count 2 2006.201.05:48:52.33#ibcon#about to read 3, iclass 28, count 2 2006.201.05:48:52.35#ibcon#read 3, iclass 28, count 2 2006.201.05:48:52.35#ibcon#about to read 4, iclass 28, count 2 2006.201.05:48:52.35#ibcon#read 4, iclass 28, count 2 2006.201.05:48:52.35#ibcon#about to read 5, iclass 28, count 2 2006.201.05:48:52.35#ibcon#read 5, iclass 28, count 2 2006.201.05:48:52.35#ibcon#about to read 6, iclass 28, count 2 2006.201.05:48:52.35#ibcon#read 6, iclass 28, count 2 2006.201.05:48:52.35#ibcon#end of sib2, iclass 28, count 2 2006.201.05:48:52.35#ibcon#*mode == 0, iclass 28, count 2 2006.201.05:48:52.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.05:48:52.35#ibcon#[25=AT05-04\r\n] 2006.201.05:48:52.35#ibcon#*before write, iclass 28, count 2 2006.201.05:48:52.35#ibcon#enter sib2, iclass 28, count 2 2006.201.05:48:52.35#ibcon#flushed, iclass 28, count 2 2006.201.05:48:52.35#ibcon#about to write, iclass 28, count 2 2006.201.05:48:52.35#ibcon#wrote, iclass 28, count 2 2006.201.05:48:52.35#ibcon#about to read 3, iclass 28, count 2 2006.201.05:48:52.38#ibcon#read 3, iclass 28, count 2 2006.201.05:48:52.38#ibcon#about to read 4, iclass 28, count 2 2006.201.05:48:52.38#ibcon#read 4, iclass 28, count 2 2006.201.05:48:52.38#ibcon#about to read 5, iclass 28, count 2 2006.201.05:48:52.38#ibcon#read 5, iclass 28, count 2 2006.201.05:48:52.38#ibcon#about to read 6, iclass 28, count 2 2006.201.05:48:52.38#ibcon#read 6, iclass 28, count 2 2006.201.05:48:52.38#ibcon#end of sib2, iclass 28, count 2 2006.201.05:48:52.38#ibcon#*after write, iclass 28, count 2 2006.201.05:48:52.38#ibcon#*before return 0, iclass 28, count 2 2006.201.05:48:52.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:52.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:52.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.05:48:52.38#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:52.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:52.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:52.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:52.50#ibcon#enter wrdev, iclass 28, count 0 2006.201.05:48:52.50#ibcon#first serial, iclass 28, count 0 2006.201.05:48:52.50#ibcon#enter sib2, iclass 28, count 0 2006.201.05:48:52.50#ibcon#flushed, iclass 28, count 0 2006.201.05:48:52.50#ibcon#about to write, iclass 28, count 0 2006.201.05:48:52.50#ibcon#wrote, iclass 28, count 0 2006.201.05:48:52.50#ibcon#about to read 3, iclass 28, count 0 2006.201.05:48:52.52#ibcon#read 3, iclass 28, count 0 2006.201.05:48:52.52#ibcon#about to read 4, iclass 28, count 0 2006.201.05:48:52.52#ibcon#read 4, iclass 28, count 0 2006.201.05:48:52.52#ibcon#about to read 5, iclass 28, count 0 2006.201.05:48:52.52#ibcon#read 5, iclass 28, count 0 2006.201.05:48:52.52#ibcon#about to read 6, iclass 28, count 0 2006.201.05:48:52.52#ibcon#read 6, iclass 28, count 0 2006.201.05:48:52.52#ibcon#end of sib2, iclass 28, count 0 2006.201.05:48:52.52#ibcon#*mode == 0, iclass 28, count 0 2006.201.05:48:52.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.05:48:52.52#ibcon#[25=USB\r\n] 2006.201.05:48:52.52#ibcon#*before write, iclass 28, count 0 2006.201.05:48:52.52#ibcon#enter sib2, iclass 28, count 0 2006.201.05:48:52.52#ibcon#flushed, iclass 28, count 0 2006.201.05:48:52.52#ibcon#about to write, iclass 28, count 0 2006.201.05:48:52.52#ibcon#wrote, iclass 28, count 0 2006.201.05:48:52.52#ibcon#about to read 3, iclass 28, count 0 2006.201.05:48:52.55#ibcon#read 3, iclass 28, count 0 2006.201.05:48:52.55#ibcon#about to read 4, iclass 28, count 0 2006.201.05:48:52.55#ibcon#read 4, iclass 28, count 0 2006.201.05:48:52.55#ibcon#about to read 5, iclass 28, count 0 2006.201.05:48:52.55#ibcon#read 5, iclass 28, count 0 2006.201.05:48:52.55#ibcon#about to read 6, iclass 28, count 0 2006.201.05:48:52.55#ibcon#read 6, iclass 28, count 0 2006.201.05:48:52.55#ibcon#end of sib2, iclass 28, count 0 2006.201.05:48:52.55#ibcon#*after write, iclass 28, count 0 2006.201.05:48:52.55#ibcon#*before return 0, iclass 28, count 0 2006.201.05:48:52.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:52.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:52.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.05:48:52.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.05:48:52.55$vck44/valo=6,814.99 2006.201.05:48:52.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.05:48:52.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.05:48:52.55#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:52.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:52.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:52.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:52.55#ibcon#enter wrdev, iclass 30, count 0 2006.201.05:48:52.55#ibcon#first serial, iclass 30, count 0 2006.201.05:48:52.55#ibcon#enter sib2, iclass 30, count 0 2006.201.05:48:52.55#ibcon#flushed, iclass 30, count 0 2006.201.05:48:52.55#ibcon#about to write, iclass 30, count 0 2006.201.05:48:52.55#ibcon#wrote, iclass 30, count 0 2006.201.05:48:52.55#ibcon#about to read 3, iclass 30, count 0 2006.201.05:48:52.57#ibcon#read 3, iclass 30, count 0 2006.201.05:48:52.57#ibcon#about to read 4, iclass 30, count 0 2006.201.05:48:52.57#ibcon#read 4, iclass 30, count 0 2006.201.05:48:52.57#ibcon#about to read 5, iclass 30, count 0 2006.201.05:48:52.57#ibcon#read 5, iclass 30, count 0 2006.201.05:48:52.57#ibcon#about to read 6, iclass 30, count 0 2006.201.05:48:52.57#ibcon#read 6, iclass 30, count 0 2006.201.05:48:52.57#ibcon#end of sib2, iclass 30, count 0 2006.201.05:48:52.57#ibcon#*mode == 0, iclass 30, count 0 2006.201.05:48:52.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.05:48:52.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:48:52.57#ibcon#*before write, iclass 30, count 0 2006.201.05:48:52.57#ibcon#enter sib2, iclass 30, count 0 2006.201.05:48:52.57#ibcon#flushed, iclass 30, count 0 2006.201.05:48:52.57#ibcon#about to write, iclass 30, count 0 2006.201.05:48:52.57#ibcon#wrote, iclass 30, count 0 2006.201.05:48:52.57#ibcon#about to read 3, iclass 30, count 0 2006.201.05:48:52.61#ibcon#read 3, iclass 30, count 0 2006.201.05:48:52.61#ibcon#about to read 4, iclass 30, count 0 2006.201.05:48:52.61#ibcon#read 4, iclass 30, count 0 2006.201.05:48:52.61#ibcon#about to read 5, iclass 30, count 0 2006.201.05:48:52.61#ibcon#read 5, iclass 30, count 0 2006.201.05:48:52.61#ibcon#about to read 6, iclass 30, count 0 2006.201.05:48:52.61#ibcon#read 6, iclass 30, count 0 2006.201.05:48:52.61#ibcon#end of sib2, iclass 30, count 0 2006.201.05:48:52.61#ibcon#*after write, iclass 30, count 0 2006.201.05:48:52.61#ibcon#*before return 0, iclass 30, count 0 2006.201.05:48:52.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:52.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:52.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.05:48:52.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.05:48:52.61$vck44/va=6,5 2006.201.05:48:52.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.05:48:52.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.05:48:52.61#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:52.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:52.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:52.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:52.67#ibcon#enter wrdev, iclass 32, count 2 2006.201.05:48:52.67#ibcon#first serial, iclass 32, count 2 2006.201.05:48:52.67#ibcon#enter sib2, iclass 32, count 2 2006.201.05:48:52.67#ibcon#flushed, iclass 32, count 2 2006.201.05:48:52.67#ibcon#about to write, iclass 32, count 2 2006.201.05:48:52.67#ibcon#wrote, iclass 32, count 2 2006.201.05:48:52.67#ibcon#about to read 3, iclass 32, count 2 2006.201.05:48:52.69#ibcon#read 3, iclass 32, count 2 2006.201.05:48:52.69#ibcon#about to read 4, iclass 32, count 2 2006.201.05:48:52.69#ibcon#read 4, iclass 32, count 2 2006.201.05:48:52.69#ibcon#about to read 5, iclass 32, count 2 2006.201.05:48:52.69#ibcon#read 5, iclass 32, count 2 2006.201.05:48:52.69#ibcon#about to read 6, iclass 32, count 2 2006.201.05:48:52.69#ibcon#read 6, iclass 32, count 2 2006.201.05:48:52.69#ibcon#end of sib2, iclass 32, count 2 2006.201.05:48:52.69#ibcon#*mode == 0, iclass 32, count 2 2006.201.05:48:52.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.05:48:52.69#ibcon#[25=AT06-05\r\n] 2006.201.05:48:52.69#ibcon#*before write, iclass 32, count 2 2006.201.05:48:52.69#ibcon#enter sib2, iclass 32, count 2 2006.201.05:48:52.69#ibcon#flushed, iclass 32, count 2 2006.201.05:48:52.69#ibcon#about to write, iclass 32, count 2 2006.201.05:48:52.69#ibcon#wrote, iclass 32, count 2 2006.201.05:48:52.69#ibcon#about to read 3, iclass 32, count 2 2006.201.05:48:52.72#ibcon#read 3, iclass 32, count 2 2006.201.05:48:52.72#ibcon#about to read 4, iclass 32, count 2 2006.201.05:48:52.72#ibcon#read 4, iclass 32, count 2 2006.201.05:48:52.72#ibcon#about to read 5, iclass 32, count 2 2006.201.05:48:52.72#ibcon#read 5, iclass 32, count 2 2006.201.05:48:52.72#ibcon#about to read 6, iclass 32, count 2 2006.201.05:48:52.72#ibcon#read 6, iclass 32, count 2 2006.201.05:48:52.72#ibcon#end of sib2, iclass 32, count 2 2006.201.05:48:52.72#ibcon#*after write, iclass 32, count 2 2006.201.05:48:52.72#ibcon#*before return 0, iclass 32, count 2 2006.201.05:48:52.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:52.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:52.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.05:48:52.72#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:52.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:52.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:52.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:52.84#ibcon#enter wrdev, iclass 32, count 0 2006.201.05:48:52.84#ibcon#first serial, iclass 32, count 0 2006.201.05:48:52.84#ibcon#enter sib2, iclass 32, count 0 2006.201.05:48:52.84#ibcon#flushed, iclass 32, count 0 2006.201.05:48:52.84#ibcon#about to write, iclass 32, count 0 2006.201.05:48:52.84#ibcon#wrote, iclass 32, count 0 2006.201.05:48:52.84#ibcon#about to read 3, iclass 32, count 0 2006.201.05:48:52.86#ibcon#read 3, iclass 32, count 0 2006.201.05:48:52.86#ibcon#about to read 4, iclass 32, count 0 2006.201.05:48:52.86#ibcon#read 4, iclass 32, count 0 2006.201.05:48:52.86#ibcon#about to read 5, iclass 32, count 0 2006.201.05:48:52.86#ibcon#read 5, iclass 32, count 0 2006.201.05:48:52.86#ibcon#about to read 6, iclass 32, count 0 2006.201.05:48:52.86#ibcon#read 6, iclass 32, count 0 2006.201.05:48:52.86#ibcon#end of sib2, iclass 32, count 0 2006.201.05:48:52.86#ibcon#*mode == 0, iclass 32, count 0 2006.201.05:48:52.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.05:48:52.86#ibcon#[25=USB\r\n] 2006.201.05:48:52.86#ibcon#*before write, iclass 32, count 0 2006.201.05:48:52.86#ibcon#enter sib2, iclass 32, count 0 2006.201.05:48:52.86#ibcon#flushed, iclass 32, count 0 2006.201.05:48:52.86#ibcon#about to write, iclass 32, count 0 2006.201.05:48:52.86#ibcon#wrote, iclass 32, count 0 2006.201.05:48:52.86#ibcon#about to read 3, iclass 32, count 0 2006.201.05:48:52.89#ibcon#read 3, iclass 32, count 0 2006.201.05:48:52.89#ibcon#about to read 4, iclass 32, count 0 2006.201.05:48:52.89#ibcon#read 4, iclass 32, count 0 2006.201.05:48:52.89#ibcon#about to read 5, iclass 32, count 0 2006.201.05:48:52.89#ibcon#read 5, iclass 32, count 0 2006.201.05:48:52.89#ibcon#about to read 6, iclass 32, count 0 2006.201.05:48:52.89#ibcon#read 6, iclass 32, count 0 2006.201.05:48:52.89#ibcon#end of sib2, iclass 32, count 0 2006.201.05:48:52.89#ibcon#*after write, iclass 32, count 0 2006.201.05:48:52.89#ibcon#*before return 0, iclass 32, count 0 2006.201.05:48:52.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:52.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:52.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.05:48:52.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.05:48:52.89$vck44/valo=7,864.99 2006.201.05:48:52.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.05:48:52.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.05:48:52.89#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:52.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:52.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:52.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:52.89#ibcon#enter wrdev, iclass 34, count 0 2006.201.05:48:52.89#ibcon#first serial, iclass 34, count 0 2006.201.05:48:52.89#ibcon#enter sib2, iclass 34, count 0 2006.201.05:48:52.89#ibcon#flushed, iclass 34, count 0 2006.201.05:48:52.89#ibcon#about to write, iclass 34, count 0 2006.201.05:48:52.89#ibcon#wrote, iclass 34, count 0 2006.201.05:48:52.89#ibcon#about to read 3, iclass 34, count 0 2006.201.05:48:52.91#ibcon#read 3, iclass 34, count 0 2006.201.05:48:52.91#ibcon#about to read 4, iclass 34, count 0 2006.201.05:48:52.91#ibcon#read 4, iclass 34, count 0 2006.201.05:48:52.91#ibcon#about to read 5, iclass 34, count 0 2006.201.05:48:52.91#ibcon#read 5, iclass 34, count 0 2006.201.05:48:52.91#ibcon#about to read 6, iclass 34, count 0 2006.201.05:48:52.91#ibcon#read 6, iclass 34, count 0 2006.201.05:48:52.91#ibcon#end of sib2, iclass 34, count 0 2006.201.05:48:52.91#ibcon#*mode == 0, iclass 34, count 0 2006.201.05:48:52.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.05:48:52.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:48:52.91#ibcon#*before write, iclass 34, count 0 2006.201.05:48:52.91#ibcon#enter sib2, iclass 34, count 0 2006.201.05:48:52.91#ibcon#flushed, iclass 34, count 0 2006.201.05:48:52.91#ibcon#about to write, iclass 34, count 0 2006.201.05:48:52.91#ibcon#wrote, iclass 34, count 0 2006.201.05:48:52.91#ibcon#about to read 3, iclass 34, count 0 2006.201.05:48:52.95#ibcon#read 3, iclass 34, count 0 2006.201.05:48:52.95#ibcon#about to read 4, iclass 34, count 0 2006.201.05:48:52.95#ibcon#read 4, iclass 34, count 0 2006.201.05:48:52.95#ibcon#about to read 5, iclass 34, count 0 2006.201.05:48:52.95#ibcon#read 5, iclass 34, count 0 2006.201.05:48:52.95#ibcon#about to read 6, iclass 34, count 0 2006.201.05:48:52.95#ibcon#read 6, iclass 34, count 0 2006.201.05:48:52.95#ibcon#end of sib2, iclass 34, count 0 2006.201.05:48:52.95#ibcon#*after write, iclass 34, count 0 2006.201.05:48:52.95#ibcon#*before return 0, iclass 34, count 0 2006.201.05:48:52.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:52.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:52.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.05:48:52.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.05:48:52.95$vck44/va=7,5 2006.201.05:48:52.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.05:48:52.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.05:48:52.95#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:52.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:53.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:53.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:53.01#ibcon#enter wrdev, iclass 36, count 2 2006.201.05:48:53.01#ibcon#first serial, iclass 36, count 2 2006.201.05:48:53.01#ibcon#enter sib2, iclass 36, count 2 2006.201.05:48:53.01#ibcon#flushed, iclass 36, count 2 2006.201.05:48:53.01#ibcon#about to write, iclass 36, count 2 2006.201.05:48:53.01#ibcon#wrote, iclass 36, count 2 2006.201.05:48:53.01#ibcon#about to read 3, iclass 36, count 2 2006.201.05:48:53.03#ibcon#read 3, iclass 36, count 2 2006.201.05:48:53.03#ibcon#about to read 4, iclass 36, count 2 2006.201.05:48:53.03#ibcon#read 4, iclass 36, count 2 2006.201.05:48:53.03#ibcon#about to read 5, iclass 36, count 2 2006.201.05:48:53.03#ibcon#read 5, iclass 36, count 2 2006.201.05:48:53.03#ibcon#about to read 6, iclass 36, count 2 2006.201.05:48:53.03#ibcon#read 6, iclass 36, count 2 2006.201.05:48:53.03#ibcon#end of sib2, iclass 36, count 2 2006.201.05:48:53.03#ibcon#*mode == 0, iclass 36, count 2 2006.201.05:48:53.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.05:48:53.03#ibcon#[25=AT07-05\r\n] 2006.201.05:48:53.03#ibcon#*before write, iclass 36, count 2 2006.201.05:48:53.03#ibcon#enter sib2, iclass 36, count 2 2006.201.05:48:53.03#ibcon#flushed, iclass 36, count 2 2006.201.05:48:53.03#ibcon#about to write, iclass 36, count 2 2006.201.05:48:53.03#ibcon#wrote, iclass 36, count 2 2006.201.05:48:53.03#ibcon#about to read 3, iclass 36, count 2 2006.201.05:48:53.06#ibcon#read 3, iclass 36, count 2 2006.201.05:48:53.06#ibcon#about to read 4, iclass 36, count 2 2006.201.05:48:53.06#ibcon#read 4, iclass 36, count 2 2006.201.05:48:53.06#ibcon#about to read 5, iclass 36, count 2 2006.201.05:48:53.06#ibcon#read 5, iclass 36, count 2 2006.201.05:48:53.06#ibcon#about to read 6, iclass 36, count 2 2006.201.05:48:53.06#ibcon#read 6, iclass 36, count 2 2006.201.05:48:53.06#ibcon#end of sib2, iclass 36, count 2 2006.201.05:48:53.06#ibcon#*after write, iclass 36, count 2 2006.201.05:48:53.06#ibcon#*before return 0, iclass 36, count 2 2006.201.05:48:53.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:53.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:53.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.05:48:53.06#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:53.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:53.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:53.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:53.18#ibcon#enter wrdev, iclass 36, count 0 2006.201.05:48:53.18#ibcon#first serial, iclass 36, count 0 2006.201.05:48:53.18#ibcon#enter sib2, iclass 36, count 0 2006.201.05:48:53.18#ibcon#flushed, iclass 36, count 0 2006.201.05:48:53.18#ibcon#about to write, iclass 36, count 0 2006.201.05:48:53.18#ibcon#wrote, iclass 36, count 0 2006.201.05:48:53.18#ibcon#about to read 3, iclass 36, count 0 2006.201.05:48:53.20#ibcon#read 3, iclass 36, count 0 2006.201.05:48:53.20#ibcon#about to read 4, iclass 36, count 0 2006.201.05:48:53.20#ibcon#read 4, iclass 36, count 0 2006.201.05:48:53.20#ibcon#about to read 5, iclass 36, count 0 2006.201.05:48:53.20#ibcon#read 5, iclass 36, count 0 2006.201.05:48:53.20#ibcon#about to read 6, iclass 36, count 0 2006.201.05:48:53.20#ibcon#read 6, iclass 36, count 0 2006.201.05:48:53.20#ibcon#end of sib2, iclass 36, count 0 2006.201.05:48:53.20#ibcon#*mode == 0, iclass 36, count 0 2006.201.05:48:53.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.05:48:53.20#ibcon#[25=USB\r\n] 2006.201.05:48:53.20#ibcon#*before write, iclass 36, count 0 2006.201.05:48:53.20#ibcon#enter sib2, iclass 36, count 0 2006.201.05:48:53.20#ibcon#flushed, iclass 36, count 0 2006.201.05:48:53.20#ibcon#about to write, iclass 36, count 0 2006.201.05:48:53.20#ibcon#wrote, iclass 36, count 0 2006.201.05:48:53.20#ibcon#about to read 3, iclass 36, count 0 2006.201.05:48:53.23#ibcon#read 3, iclass 36, count 0 2006.201.05:48:53.23#ibcon#about to read 4, iclass 36, count 0 2006.201.05:48:53.23#ibcon#read 4, iclass 36, count 0 2006.201.05:48:53.23#ibcon#about to read 5, iclass 36, count 0 2006.201.05:48:53.23#ibcon#read 5, iclass 36, count 0 2006.201.05:48:53.23#ibcon#about to read 6, iclass 36, count 0 2006.201.05:48:53.23#ibcon#read 6, iclass 36, count 0 2006.201.05:48:53.23#ibcon#end of sib2, iclass 36, count 0 2006.201.05:48:53.23#ibcon#*after write, iclass 36, count 0 2006.201.05:48:53.23#ibcon#*before return 0, iclass 36, count 0 2006.201.05:48:53.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:53.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:53.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.05:48:53.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.05:48:53.23$vck44/valo=8,884.99 2006.201.05:48:53.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.05:48:53.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.05:48:53.23#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:53.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:53.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:53.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:53.23#ibcon#enter wrdev, iclass 38, count 0 2006.201.05:48:53.23#ibcon#first serial, iclass 38, count 0 2006.201.05:48:53.23#ibcon#enter sib2, iclass 38, count 0 2006.201.05:48:53.23#ibcon#flushed, iclass 38, count 0 2006.201.05:48:53.23#ibcon#about to write, iclass 38, count 0 2006.201.05:48:53.23#ibcon#wrote, iclass 38, count 0 2006.201.05:48:53.23#ibcon#about to read 3, iclass 38, count 0 2006.201.05:48:53.25#ibcon#read 3, iclass 38, count 0 2006.201.05:48:53.25#ibcon#about to read 4, iclass 38, count 0 2006.201.05:48:53.25#ibcon#read 4, iclass 38, count 0 2006.201.05:48:53.25#ibcon#about to read 5, iclass 38, count 0 2006.201.05:48:53.25#ibcon#read 5, iclass 38, count 0 2006.201.05:48:53.25#ibcon#about to read 6, iclass 38, count 0 2006.201.05:48:53.25#ibcon#read 6, iclass 38, count 0 2006.201.05:48:53.25#ibcon#end of sib2, iclass 38, count 0 2006.201.05:48:53.25#ibcon#*mode == 0, iclass 38, count 0 2006.201.05:48:53.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.05:48:53.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:48:53.25#ibcon#*before write, iclass 38, count 0 2006.201.05:48:53.25#ibcon#enter sib2, iclass 38, count 0 2006.201.05:48:53.25#ibcon#flushed, iclass 38, count 0 2006.201.05:48:53.25#ibcon#about to write, iclass 38, count 0 2006.201.05:48:53.25#ibcon#wrote, iclass 38, count 0 2006.201.05:48:53.25#ibcon#about to read 3, iclass 38, count 0 2006.201.05:48:53.29#ibcon#read 3, iclass 38, count 0 2006.201.05:48:53.29#ibcon#about to read 4, iclass 38, count 0 2006.201.05:48:53.29#ibcon#read 4, iclass 38, count 0 2006.201.05:48:53.29#ibcon#about to read 5, iclass 38, count 0 2006.201.05:48:53.29#ibcon#read 5, iclass 38, count 0 2006.201.05:48:53.29#ibcon#about to read 6, iclass 38, count 0 2006.201.05:48:53.29#ibcon#read 6, iclass 38, count 0 2006.201.05:48:53.29#ibcon#end of sib2, iclass 38, count 0 2006.201.05:48:53.29#ibcon#*after write, iclass 38, count 0 2006.201.05:48:53.29#ibcon#*before return 0, iclass 38, count 0 2006.201.05:48:53.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:53.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:53.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.05:48:53.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.05:48:53.29$vck44/va=8,4 2006.201.05:48:53.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.05:48:53.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.05:48:53.29#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:53.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:48:53.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:48:53.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:48:53.35#ibcon#enter wrdev, iclass 40, count 2 2006.201.05:48:53.35#ibcon#first serial, iclass 40, count 2 2006.201.05:48:53.35#ibcon#enter sib2, iclass 40, count 2 2006.201.05:48:53.35#ibcon#flushed, iclass 40, count 2 2006.201.05:48:53.35#ibcon#about to write, iclass 40, count 2 2006.201.05:48:53.35#ibcon#wrote, iclass 40, count 2 2006.201.05:48:53.35#ibcon#about to read 3, iclass 40, count 2 2006.201.05:48:53.37#ibcon#read 3, iclass 40, count 2 2006.201.05:48:53.37#ibcon#about to read 4, iclass 40, count 2 2006.201.05:48:53.37#ibcon#read 4, iclass 40, count 2 2006.201.05:48:53.37#ibcon#about to read 5, iclass 40, count 2 2006.201.05:48:53.37#ibcon#read 5, iclass 40, count 2 2006.201.05:48:53.37#ibcon#about to read 6, iclass 40, count 2 2006.201.05:48:53.37#ibcon#read 6, iclass 40, count 2 2006.201.05:48:53.37#ibcon#end of sib2, iclass 40, count 2 2006.201.05:48:53.37#ibcon#*mode == 0, iclass 40, count 2 2006.201.05:48:53.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.05:48:53.37#ibcon#[25=AT08-04\r\n] 2006.201.05:48:53.37#ibcon#*before write, iclass 40, count 2 2006.201.05:48:53.37#ibcon#enter sib2, iclass 40, count 2 2006.201.05:48:53.37#ibcon#flushed, iclass 40, count 2 2006.201.05:48:53.37#ibcon#about to write, iclass 40, count 2 2006.201.05:48:53.37#ibcon#wrote, iclass 40, count 2 2006.201.05:48:53.37#ibcon#about to read 3, iclass 40, count 2 2006.201.05:48:53.40#ibcon#read 3, iclass 40, count 2 2006.201.05:48:53.40#ibcon#about to read 4, iclass 40, count 2 2006.201.05:48:53.40#ibcon#read 4, iclass 40, count 2 2006.201.05:48:53.40#ibcon#about to read 5, iclass 40, count 2 2006.201.05:48:53.40#ibcon#read 5, iclass 40, count 2 2006.201.05:48:53.40#ibcon#about to read 6, iclass 40, count 2 2006.201.05:48:53.40#ibcon#read 6, iclass 40, count 2 2006.201.05:48:53.40#ibcon#end of sib2, iclass 40, count 2 2006.201.05:48:53.40#ibcon#*after write, iclass 40, count 2 2006.201.05:48:53.40#ibcon#*before return 0, iclass 40, count 2 2006.201.05:48:53.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:48:53.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.05:48:53.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.05:48:53.40#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:53.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:48:53.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:48:53.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:48:53.52#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:48:53.52#ibcon#first serial, iclass 40, count 0 2006.201.05:48:53.52#ibcon#enter sib2, iclass 40, count 0 2006.201.05:48:53.52#ibcon#flushed, iclass 40, count 0 2006.201.05:48:53.52#ibcon#about to write, iclass 40, count 0 2006.201.05:48:53.52#ibcon#wrote, iclass 40, count 0 2006.201.05:48:53.52#ibcon#about to read 3, iclass 40, count 0 2006.201.05:48:53.54#ibcon#read 3, iclass 40, count 0 2006.201.05:48:53.54#ibcon#about to read 4, iclass 40, count 0 2006.201.05:48:53.54#ibcon#read 4, iclass 40, count 0 2006.201.05:48:53.54#ibcon#about to read 5, iclass 40, count 0 2006.201.05:48:53.54#ibcon#read 5, iclass 40, count 0 2006.201.05:48:53.54#ibcon#about to read 6, iclass 40, count 0 2006.201.05:48:53.54#ibcon#read 6, iclass 40, count 0 2006.201.05:48:53.54#ibcon#end of sib2, iclass 40, count 0 2006.201.05:48:53.54#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:48:53.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:48:53.54#ibcon#[25=USB\r\n] 2006.201.05:48:53.54#ibcon#*before write, iclass 40, count 0 2006.201.05:48:53.54#ibcon#enter sib2, iclass 40, count 0 2006.201.05:48:53.54#ibcon#flushed, iclass 40, count 0 2006.201.05:48:53.54#ibcon#about to write, iclass 40, count 0 2006.201.05:48:53.54#ibcon#wrote, iclass 40, count 0 2006.201.05:48:53.54#ibcon#about to read 3, iclass 40, count 0 2006.201.05:48:53.57#ibcon#read 3, iclass 40, count 0 2006.201.05:48:53.57#ibcon#about to read 4, iclass 40, count 0 2006.201.05:48:53.57#ibcon#read 4, iclass 40, count 0 2006.201.05:48:53.57#ibcon#about to read 5, iclass 40, count 0 2006.201.05:48:53.57#ibcon#read 5, iclass 40, count 0 2006.201.05:48:53.57#ibcon#about to read 6, iclass 40, count 0 2006.201.05:48:53.57#ibcon#read 6, iclass 40, count 0 2006.201.05:48:53.57#ibcon#end of sib2, iclass 40, count 0 2006.201.05:48:53.57#ibcon#*after write, iclass 40, count 0 2006.201.05:48:53.57#ibcon#*before return 0, iclass 40, count 0 2006.201.05:48:53.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:48:53.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.05:48:53.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:48:53.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:48:53.57$vck44/vblo=1,629.99 2006.201.05:48:53.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.05:48:53.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.05:48:53.57#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:53.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:53.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:53.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:53.57#ibcon#enter wrdev, iclass 4, count 0 2006.201.05:48:53.57#ibcon#first serial, iclass 4, count 0 2006.201.05:48:53.57#ibcon#enter sib2, iclass 4, count 0 2006.201.05:48:53.57#ibcon#flushed, iclass 4, count 0 2006.201.05:48:53.57#ibcon#about to write, iclass 4, count 0 2006.201.05:48:53.57#ibcon#wrote, iclass 4, count 0 2006.201.05:48:53.57#ibcon#about to read 3, iclass 4, count 0 2006.201.05:48:53.59#ibcon#read 3, iclass 4, count 0 2006.201.05:48:53.59#ibcon#about to read 4, iclass 4, count 0 2006.201.05:48:53.59#ibcon#read 4, iclass 4, count 0 2006.201.05:48:53.59#ibcon#about to read 5, iclass 4, count 0 2006.201.05:48:53.59#ibcon#read 5, iclass 4, count 0 2006.201.05:48:53.59#ibcon#about to read 6, iclass 4, count 0 2006.201.05:48:53.59#ibcon#read 6, iclass 4, count 0 2006.201.05:48:53.59#ibcon#end of sib2, iclass 4, count 0 2006.201.05:48:53.59#ibcon#*mode == 0, iclass 4, count 0 2006.201.05:48:53.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.05:48:53.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:48:53.59#ibcon#*before write, iclass 4, count 0 2006.201.05:48:53.59#ibcon#enter sib2, iclass 4, count 0 2006.201.05:48:53.59#ibcon#flushed, iclass 4, count 0 2006.201.05:48:53.59#ibcon#about to write, iclass 4, count 0 2006.201.05:48:53.59#ibcon#wrote, iclass 4, count 0 2006.201.05:48:53.59#ibcon#about to read 3, iclass 4, count 0 2006.201.05:48:53.63#ibcon#read 3, iclass 4, count 0 2006.201.05:48:53.63#ibcon#about to read 4, iclass 4, count 0 2006.201.05:48:53.63#ibcon#read 4, iclass 4, count 0 2006.201.05:48:53.63#ibcon#about to read 5, iclass 4, count 0 2006.201.05:48:53.63#ibcon#read 5, iclass 4, count 0 2006.201.05:48:53.63#ibcon#about to read 6, iclass 4, count 0 2006.201.05:48:53.63#ibcon#read 6, iclass 4, count 0 2006.201.05:48:53.63#ibcon#end of sib2, iclass 4, count 0 2006.201.05:48:53.63#ibcon#*after write, iclass 4, count 0 2006.201.05:48:53.63#ibcon#*before return 0, iclass 4, count 0 2006.201.05:48:53.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:53.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.05:48:53.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.05:48:53.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.05:48:53.63$vck44/vb=1,4 2006.201.05:48:53.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.05:48:53.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.05:48:53.63#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:53.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:53.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:53.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:53.63#ibcon#enter wrdev, iclass 6, count 2 2006.201.05:48:53.63#ibcon#first serial, iclass 6, count 2 2006.201.05:48:53.63#ibcon#enter sib2, iclass 6, count 2 2006.201.05:48:53.63#ibcon#flushed, iclass 6, count 2 2006.201.05:48:53.63#ibcon#about to write, iclass 6, count 2 2006.201.05:48:53.63#ibcon#wrote, iclass 6, count 2 2006.201.05:48:53.63#ibcon#about to read 3, iclass 6, count 2 2006.201.05:48:53.65#ibcon#read 3, iclass 6, count 2 2006.201.05:48:53.65#ibcon#about to read 4, iclass 6, count 2 2006.201.05:48:53.65#ibcon#read 4, iclass 6, count 2 2006.201.05:48:53.65#ibcon#about to read 5, iclass 6, count 2 2006.201.05:48:53.65#ibcon#read 5, iclass 6, count 2 2006.201.05:48:53.65#ibcon#about to read 6, iclass 6, count 2 2006.201.05:48:53.65#ibcon#read 6, iclass 6, count 2 2006.201.05:48:53.65#ibcon#end of sib2, iclass 6, count 2 2006.201.05:48:53.65#ibcon#*mode == 0, iclass 6, count 2 2006.201.05:48:53.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.05:48:53.65#ibcon#[27=AT01-04\r\n] 2006.201.05:48:53.65#ibcon#*before write, iclass 6, count 2 2006.201.05:48:53.65#ibcon#enter sib2, iclass 6, count 2 2006.201.05:48:53.65#ibcon#flushed, iclass 6, count 2 2006.201.05:48:53.65#ibcon#about to write, iclass 6, count 2 2006.201.05:48:53.65#ibcon#wrote, iclass 6, count 2 2006.201.05:48:53.65#ibcon#about to read 3, iclass 6, count 2 2006.201.05:48:53.69#ibcon#read 3, iclass 6, count 2 2006.201.05:48:53.69#ibcon#about to read 4, iclass 6, count 2 2006.201.05:48:53.69#ibcon#read 4, iclass 6, count 2 2006.201.05:48:53.69#ibcon#about to read 5, iclass 6, count 2 2006.201.05:48:53.69#ibcon#read 5, iclass 6, count 2 2006.201.05:48:53.69#ibcon#about to read 6, iclass 6, count 2 2006.201.05:48:53.69#ibcon#read 6, iclass 6, count 2 2006.201.05:48:53.69#ibcon#end of sib2, iclass 6, count 2 2006.201.05:48:53.69#ibcon#*after write, iclass 6, count 2 2006.201.05:48:53.69#ibcon#*before return 0, iclass 6, count 2 2006.201.05:48:53.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:53.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.05:48:53.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.05:48:53.69#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:53.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:53.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:53.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:53.81#ibcon#enter wrdev, iclass 6, count 0 2006.201.05:48:53.81#ibcon#first serial, iclass 6, count 0 2006.201.05:48:53.81#ibcon#enter sib2, iclass 6, count 0 2006.201.05:48:53.81#ibcon#flushed, iclass 6, count 0 2006.201.05:48:53.81#ibcon#about to write, iclass 6, count 0 2006.201.05:48:53.81#ibcon#wrote, iclass 6, count 0 2006.201.05:48:53.81#ibcon#about to read 3, iclass 6, count 0 2006.201.05:48:53.83#ibcon#read 3, iclass 6, count 0 2006.201.05:48:53.83#ibcon#about to read 4, iclass 6, count 0 2006.201.05:48:53.83#ibcon#read 4, iclass 6, count 0 2006.201.05:48:53.83#ibcon#about to read 5, iclass 6, count 0 2006.201.05:48:53.83#ibcon#read 5, iclass 6, count 0 2006.201.05:48:53.83#ibcon#about to read 6, iclass 6, count 0 2006.201.05:48:53.83#ibcon#read 6, iclass 6, count 0 2006.201.05:48:53.83#ibcon#end of sib2, iclass 6, count 0 2006.201.05:48:53.83#ibcon#*mode == 0, iclass 6, count 0 2006.201.05:48:53.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.05:48:53.83#ibcon#[27=USB\r\n] 2006.201.05:48:53.83#ibcon#*before write, iclass 6, count 0 2006.201.05:48:53.83#ibcon#enter sib2, iclass 6, count 0 2006.201.05:48:53.83#ibcon#flushed, iclass 6, count 0 2006.201.05:48:53.83#ibcon#about to write, iclass 6, count 0 2006.201.05:48:53.83#ibcon#wrote, iclass 6, count 0 2006.201.05:48:53.83#ibcon#about to read 3, iclass 6, count 0 2006.201.05:48:53.86#ibcon#read 3, iclass 6, count 0 2006.201.05:48:53.86#ibcon#about to read 4, iclass 6, count 0 2006.201.05:48:53.86#ibcon#read 4, iclass 6, count 0 2006.201.05:48:53.86#ibcon#about to read 5, iclass 6, count 0 2006.201.05:48:53.86#ibcon#read 5, iclass 6, count 0 2006.201.05:48:53.86#ibcon#about to read 6, iclass 6, count 0 2006.201.05:48:53.86#ibcon#read 6, iclass 6, count 0 2006.201.05:48:53.86#ibcon#end of sib2, iclass 6, count 0 2006.201.05:48:53.86#ibcon#*after write, iclass 6, count 0 2006.201.05:48:53.86#ibcon#*before return 0, iclass 6, count 0 2006.201.05:48:53.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:53.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.05:48:53.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.05:48:53.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.05:48:53.86$vck44/vblo=2,634.99 2006.201.05:48:53.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.05:48:53.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.05:48:53.86#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:53.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:53.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:53.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:53.86#ibcon#enter wrdev, iclass 10, count 0 2006.201.05:48:53.86#ibcon#first serial, iclass 10, count 0 2006.201.05:48:53.86#ibcon#enter sib2, iclass 10, count 0 2006.201.05:48:53.86#ibcon#flushed, iclass 10, count 0 2006.201.05:48:53.86#ibcon#about to write, iclass 10, count 0 2006.201.05:48:53.86#ibcon#wrote, iclass 10, count 0 2006.201.05:48:53.86#ibcon#about to read 3, iclass 10, count 0 2006.201.05:48:53.88#ibcon#read 3, iclass 10, count 0 2006.201.05:48:53.88#ibcon#about to read 4, iclass 10, count 0 2006.201.05:48:53.88#ibcon#read 4, iclass 10, count 0 2006.201.05:48:53.88#ibcon#about to read 5, iclass 10, count 0 2006.201.05:48:53.88#ibcon#read 5, iclass 10, count 0 2006.201.05:48:53.88#ibcon#about to read 6, iclass 10, count 0 2006.201.05:48:53.88#ibcon#read 6, iclass 10, count 0 2006.201.05:48:53.88#ibcon#end of sib2, iclass 10, count 0 2006.201.05:48:53.88#ibcon#*mode == 0, iclass 10, count 0 2006.201.05:48:53.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.05:48:53.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:48:53.88#ibcon#*before write, iclass 10, count 0 2006.201.05:48:53.88#ibcon#enter sib2, iclass 10, count 0 2006.201.05:48:53.88#ibcon#flushed, iclass 10, count 0 2006.201.05:48:53.88#ibcon#about to write, iclass 10, count 0 2006.201.05:48:53.88#ibcon#wrote, iclass 10, count 0 2006.201.05:48:53.88#ibcon#about to read 3, iclass 10, count 0 2006.201.05:48:53.92#ibcon#read 3, iclass 10, count 0 2006.201.05:48:53.92#ibcon#about to read 4, iclass 10, count 0 2006.201.05:48:53.92#ibcon#read 4, iclass 10, count 0 2006.201.05:48:53.92#ibcon#about to read 5, iclass 10, count 0 2006.201.05:48:53.92#ibcon#read 5, iclass 10, count 0 2006.201.05:48:53.92#ibcon#about to read 6, iclass 10, count 0 2006.201.05:48:53.92#ibcon#read 6, iclass 10, count 0 2006.201.05:48:53.92#ibcon#end of sib2, iclass 10, count 0 2006.201.05:48:53.92#ibcon#*after write, iclass 10, count 0 2006.201.05:48:53.92#ibcon#*before return 0, iclass 10, count 0 2006.201.05:48:53.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:53.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.05:48:53.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.05:48:53.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.05:48:53.92$vck44/vb=2,5 2006.201.05:48:53.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.05:48:53.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.05:48:53.92#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:53.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:53.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:53.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:53.98#ibcon#enter wrdev, iclass 12, count 2 2006.201.05:48:53.98#ibcon#first serial, iclass 12, count 2 2006.201.05:48:53.98#ibcon#enter sib2, iclass 12, count 2 2006.201.05:48:53.98#ibcon#flushed, iclass 12, count 2 2006.201.05:48:53.98#ibcon#about to write, iclass 12, count 2 2006.201.05:48:53.98#ibcon#wrote, iclass 12, count 2 2006.201.05:48:53.98#ibcon#about to read 3, iclass 12, count 2 2006.201.05:48:54.00#ibcon#read 3, iclass 12, count 2 2006.201.05:48:54.00#ibcon#about to read 4, iclass 12, count 2 2006.201.05:48:54.00#ibcon#read 4, iclass 12, count 2 2006.201.05:48:54.00#ibcon#about to read 5, iclass 12, count 2 2006.201.05:48:54.00#ibcon#read 5, iclass 12, count 2 2006.201.05:48:54.00#ibcon#about to read 6, iclass 12, count 2 2006.201.05:48:54.00#ibcon#read 6, iclass 12, count 2 2006.201.05:48:54.00#ibcon#end of sib2, iclass 12, count 2 2006.201.05:48:54.00#ibcon#*mode == 0, iclass 12, count 2 2006.201.05:48:54.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.05:48:54.00#ibcon#[27=AT02-05\r\n] 2006.201.05:48:54.00#ibcon#*before write, iclass 12, count 2 2006.201.05:48:54.00#ibcon#enter sib2, iclass 12, count 2 2006.201.05:48:54.00#ibcon#flushed, iclass 12, count 2 2006.201.05:48:54.00#ibcon#about to write, iclass 12, count 2 2006.201.05:48:54.00#ibcon#wrote, iclass 12, count 2 2006.201.05:48:54.00#ibcon#about to read 3, iclass 12, count 2 2006.201.05:48:54.03#ibcon#read 3, iclass 12, count 2 2006.201.05:48:54.03#ibcon#about to read 4, iclass 12, count 2 2006.201.05:48:54.03#ibcon#read 4, iclass 12, count 2 2006.201.05:48:54.03#ibcon#about to read 5, iclass 12, count 2 2006.201.05:48:54.03#ibcon#read 5, iclass 12, count 2 2006.201.05:48:54.03#ibcon#about to read 6, iclass 12, count 2 2006.201.05:48:54.03#ibcon#read 6, iclass 12, count 2 2006.201.05:48:54.03#ibcon#end of sib2, iclass 12, count 2 2006.201.05:48:54.03#ibcon#*after write, iclass 12, count 2 2006.201.05:48:54.03#ibcon#*before return 0, iclass 12, count 2 2006.201.05:48:54.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:54.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.05:48:54.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.05:48:54.03#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:54.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:54.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:54.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:54.15#ibcon#enter wrdev, iclass 12, count 0 2006.201.05:48:54.15#ibcon#first serial, iclass 12, count 0 2006.201.05:48:54.15#ibcon#enter sib2, iclass 12, count 0 2006.201.05:48:54.15#ibcon#flushed, iclass 12, count 0 2006.201.05:48:54.15#ibcon#about to write, iclass 12, count 0 2006.201.05:48:54.15#ibcon#wrote, iclass 12, count 0 2006.201.05:48:54.15#ibcon#about to read 3, iclass 12, count 0 2006.201.05:48:54.17#ibcon#read 3, iclass 12, count 0 2006.201.05:48:54.17#ibcon#about to read 4, iclass 12, count 0 2006.201.05:48:54.17#ibcon#read 4, iclass 12, count 0 2006.201.05:48:54.17#ibcon#about to read 5, iclass 12, count 0 2006.201.05:48:54.17#ibcon#read 5, iclass 12, count 0 2006.201.05:48:54.17#ibcon#about to read 6, iclass 12, count 0 2006.201.05:48:54.17#ibcon#read 6, iclass 12, count 0 2006.201.05:48:54.17#ibcon#end of sib2, iclass 12, count 0 2006.201.05:48:54.17#ibcon#*mode == 0, iclass 12, count 0 2006.201.05:48:54.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.05:48:54.17#ibcon#[27=USB\r\n] 2006.201.05:48:54.17#ibcon#*before write, iclass 12, count 0 2006.201.05:48:54.17#ibcon#enter sib2, iclass 12, count 0 2006.201.05:48:54.17#ibcon#flushed, iclass 12, count 0 2006.201.05:48:54.17#ibcon#about to write, iclass 12, count 0 2006.201.05:48:54.17#ibcon#wrote, iclass 12, count 0 2006.201.05:48:54.17#ibcon#about to read 3, iclass 12, count 0 2006.201.05:48:54.20#ibcon#read 3, iclass 12, count 0 2006.201.05:48:54.20#ibcon#about to read 4, iclass 12, count 0 2006.201.05:48:54.20#ibcon#read 4, iclass 12, count 0 2006.201.05:48:54.20#ibcon#about to read 5, iclass 12, count 0 2006.201.05:48:54.20#ibcon#read 5, iclass 12, count 0 2006.201.05:48:54.20#ibcon#about to read 6, iclass 12, count 0 2006.201.05:48:54.20#ibcon#read 6, iclass 12, count 0 2006.201.05:48:54.20#ibcon#end of sib2, iclass 12, count 0 2006.201.05:48:54.20#ibcon#*after write, iclass 12, count 0 2006.201.05:48:54.20#ibcon#*before return 0, iclass 12, count 0 2006.201.05:48:54.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:54.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.05:48:54.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.05:48:54.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.05:48:54.20$vck44/vblo=3,649.99 2006.201.05:48:54.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.05:48:54.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.05:48:54.20#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:54.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:54.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:54.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:54.20#ibcon#enter wrdev, iclass 14, count 0 2006.201.05:48:54.20#ibcon#first serial, iclass 14, count 0 2006.201.05:48:54.20#ibcon#enter sib2, iclass 14, count 0 2006.201.05:48:54.20#ibcon#flushed, iclass 14, count 0 2006.201.05:48:54.20#ibcon#about to write, iclass 14, count 0 2006.201.05:48:54.20#ibcon#wrote, iclass 14, count 0 2006.201.05:48:54.20#ibcon#about to read 3, iclass 14, count 0 2006.201.05:48:54.22#ibcon#read 3, iclass 14, count 0 2006.201.05:48:54.22#ibcon#about to read 4, iclass 14, count 0 2006.201.05:48:54.22#ibcon#read 4, iclass 14, count 0 2006.201.05:48:54.22#ibcon#about to read 5, iclass 14, count 0 2006.201.05:48:54.22#ibcon#read 5, iclass 14, count 0 2006.201.05:48:54.22#ibcon#about to read 6, iclass 14, count 0 2006.201.05:48:54.22#ibcon#read 6, iclass 14, count 0 2006.201.05:48:54.22#ibcon#end of sib2, iclass 14, count 0 2006.201.05:48:54.22#ibcon#*mode == 0, iclass 14, count 0 2006.201.05:48:54.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.05:48:54.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:48:54.22#ibcon#*before write, iclass 14, count 0 2006.201.05:48:54.22#ibcon#enter sib2, iclass 14, count 0 2006.201.05:48:54.22#ibcon#flushed, iclass 14, count 0 2006.201.05:48:54.22#ibcon#about to write, iclass 14, count 0 2006.201.05:48:54.22#ibcon#wrote, iclass 14, count 0 2006.201.05:48:54.22#ibcon#about to read 3, iclass 14, count 0 2006.201.05:48:54.26#ibcon#read 3, iclass 14, count 0 2006.201.05:48:54.26#ibcon#about to read 4, iclass 14, count 0 2006.201.05:48:54.26#ibcon#read 4, iclass 14, count 0 2006.201.05:48:54.26#ibcon#about to read 5, iclass 14, count 0 2006.201.05:48:54.26#ibcon#read 5, iclass 14, count 0 2006.201.05:48:54.26#ibcon#about to read 6, iclass 14, count 0 2006.201.05:48:54.26#ibcon#read 6, iclass 14, count 0 2006.201.05:48:54.26#ibcon#end of sib2, iclass 14, count 0 2006.201.05:48:54.26#ibcon#*after write, iclass 14, count 0 2006.201.05:48:54.26#ibcon#*before return 0, iclass 14, count 0 2006.201.05:48:54.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:54.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.05:48:54.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.05:48:54.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.05:48:54.26$vck44/vb=3,4 2006.201.05:48:54.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.05:48:54.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.05:48:54.26#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:54.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:54.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:54.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:54.32#ibcon#enter wrdev, iclass 16, count 2 2006.201.05:48:54.32#ibcon#first serial, iclass 16, count 2 2006.201.05:48:54.32#ibcon#enter sib2, iclass 16, count 2 2006.201.05:48:54.32#ibcon#flushed, iclass 16, count 2 2006.201.05:48:54.32#ibcon#about to write, iclass 16, count 2 2006.201.05:48:54.32#ibcon#wrote, iclass 16, count 2 2006.201.05:48:54.32#ibcon#about to read 3, iclass 16, count 2 2006.201.05:48:54.34#ibcon#read 3, iclass 16, count 2 2006.201.05:48:54.34#ibcon#about to read 4, iclass 16, count 2 2006.201.05:48:54.34#ibcon#read 4, iclass 16, count 2 2006.201.05:48:54.34#ibcon#about to read 5, iclass 16, count 2 2006.201.05:48:54.34#ibcon#read 5, iclass 16, count 2 2006.201.05:48:54.34#ibcon#about to read 6, iclass 16, count 2 2006.201.05:48:54.34#ibcon#read 6, iclass 16, count 2 2006.201.05:48:54.34#ibcon#end of sib2, iclass 16, count 2 2006.201.05:48:54.34#ibcon#*mode == 0, iclass 16, count 2 2006.201.05:48:54.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.05:48:54.34#ibcon#[27=AT03-04\r\n] 2006.201.05:48:54.34#ibcon#*before write, iclass 16, count 2 2006.201.05:48:54.34#ibcon#enter sib2, iclass 16, count 2 2006.201.05:48:54.34#ibcon#flushed, iclass 16, count 2 2006.201.05:48:54.34#ibcon#about to write, iclass 16, count 2 2006.201.05:48:54.34#ibcon#wrote, iclass 16, count 2 2006.201.05:48:54.34#ibcon#about to read 3, iclass 16, count 2 2006.201.05:48:54.37#ibcon#read 3, iclass 16, count 2 2006.201.05:48:54.37#ibcon#about to read 4, iclass 16, count 2 2006.201.05:48:54.37#ibcon#read 4, iclass 16, count 2 2006.201.05:48:54.37#ibcon#about to read 5, iclass 16, count 2 2006.201.05:48:54.37#ibcon#read 5, iclass 16, count 2 2006.201.05:48:54.37#ibcon#about to read 6, iclass 16, count 2 2006.201.05:48:54.37#ibcon#read 6, iclass 16, count 2 2006.201.05:48:54.37#ibcon#end of sib2, iclass 16, count 2 2006.201.05:48:54.37#ibcon#*after write, iclass 16, count 2 2006.201.05:48:54.37#ibcon#*before return 0, iclass 16, count 2 2006.201.05:48:54.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:54.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.05:48:54.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.05:48:54.37#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:54.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:54.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:54.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:54.49#ibcon#enter wrdev, iclass 16, count 0 2006.201.05:48:54.49#ibcon#first serial, iclass 16, count 0 2006.201.05:48:54.49#ibcon#enter sib2, iclass 16, count 0 2006.201.05:48:54.49#ibcon#flushed, iclass 16, count 0 2006.201.05:48:54.49#ibcon#about to write, iclass 16, count 0 2006.201.05:48:54.49#ibcon#wrote, iclass 16, count 0 2006.201.05:48:54.49#ibcon#about to read 3, iclass 16, count 0 2006.201.05:48:54.51#ibcon#read 3, iclass 16, count 0 2006.201.05:48:54.51#ibcon#about to read 4, iclass 16, count 0 2006.201.05:48:54.51#ibcon#read 4, iclass 16, count 0 2006.201.05:48:54.51#ibcon#about to read 5, iclass 16, count 0 2006.201.05:48:54.51#ibcon#read 5, iclass 16, count 0 2006.201.05:48:54.51#ibcon#about to read 6, iclass 16, count 0 2006.201.05:48:54.51#ibcon#read 6, iclass 16, count 0 2006.201.05:48:54.51#ibcon#end of sib2, iclass 16, count 0 2006.201.05:48:54.51#ibcon#*mode == 0, iclass 16, count 0 2006.201.05:48:54.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.05:48:54.51#ibcon#[27=USB\r\n] 2006.201.05:48:54.51#ibcon#*before write, iclass 16, count 0 2006.201.05:48:54.51#ibcon#enter sib2, iclass 16, count 0 2006.201.05:48:54.51#ibcon#flushed, iclass 16, count 0 2006.201.05:48:54.51#ibcon#about to write, iclass 16, count 0 2006.201.05:48:54.51#ibcon#wrote, iclass 16, count 0 2006.201.05:48:54.51#ibcon#about to read 3, iclass 16, count 0 2006.201.05:48:54.54#ibcon#read 3, iclass 16, count 0 2006.201.05:48:54.54#ibcon#about to read 4, iclass 16, count 0 2006.201.05:48:54.54#ibcon#read 4, iclass 16, count 0 2006.201.05:48:54.54#ibcon#about to read 5, iclass 16, count 0 2006.201.05:48:54.54#ibcon#read 5, iclass 16, count 0 2006.201.05:48:54.54#ibcon#about to read 6, iclass 16, count 0 2006.201.05:48:54.54#ibcon#read 6, iclass 16, count 0 2006.201.05:48:54.54#ibcon#end of sib2, iclass 16, count 0 2006.201.05:48:54.54#ibcon#*after write, iclass 16, count 0 2006.201.05:48:54.54#ibcon#*before return 0, iclass 16, count 0 2006.201.05:48:54.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:54.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.05:48:54.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.05:48:54.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.05:48:54.54$vck44/vblo=4,679.99 2006.201.05:48:54.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.05:48:54.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.05:48:54.54#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:54.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:54.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:54.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:54.54#ibcon#enter wrdev, iclass 18, count 0 2006.201.05:48:54.54#ibcon#first serial, iclass 18, count 0 2006.201.05:48:54.54#ibcon#enter sib2, iclass 18, count 0 2006.201.05:48:54.54#ibcon#flushed, iclass 18, count 0 2006.201.05:48:54.54#ibcon#about to write, iclass 18, count 0 2006.201.05:48:54.54#ibcon#wrote, iclass 18, count 0 2006.201.05:48:54.54#ibcon#about to read 3, iclass 18, count 0 2006.201.05:48:54.56#ibcon#read 3, iclass 18, count 0 2006.201.05:48:54.56#ibcon#about to read 4, iclass 18, count 0 2006.201.05:48:54.56#ibcon#read 4, iclass 18, count 0 2006.201.05:48:54.56#ibcon#about to read 5, iclass 18, count 0 2006.201.05:48:54.56#ibcon#read 5, iclass 18, count 0 2006.201.05:48:54.56#ibcon#about to read 6, iclass 18, count 0 2006.201.05:48:54.56#ibcon#read 6, iclass 18, count 0 2006.201.05:48:54.56#ibcon#end of sib2, iclass 18, count 0 2006.201.05:48:54.56#ibcon#*mode == 0, iclass 18, count 0 2006.201.05:48:54.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.05:48:54.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:48:54.56#ibcon#*before write, iclass 18, count 0 2006.201.05:48:54.56#ibcon#enter sib2, iclass 18, count 0 2006.201.05:48:54.56#ibcon#flushed, iclass 18, count 0 2006.201.05:48:54.56#ibcon#about to write, iclass 18, count 0 2006.201.05:48:54.56#ibcon#wrote, iclass 18, count 0 2006.201.05:48:54.56#ibcon#about to read 3, iclass 18, count 0 2006.201.05:48:54.60#ibcon#read 3, iclass 18, count 0 2006.201.05:48:54.60#ibcon#about to read 4, iclass 18, count 0 2006.201.05:48:54.60#ibcon#read 4, iclass 18, count 0 2006.201.05:48:54.60#ibcon#about to read 5, iclass 18, count 0 2006.201.05:48:54.60#ibcon#read 5, iclass 18, count 0 2006.201.05:48:54.60#ibcon#about to read 6, iclass 18, count 0 2006.201.05:48:54.60#ibcon#read 6, iclass 18, count 0 2006.201.05:48:54.60#ibcon#end of sib2, iclass 18, count 0 2006.201.05:48:54.60#ibcon#*after write, iclass 18, count 0 2006.201.05:48:54.60#ibcon#*before return 0, iclass 18, count 0 2006.201.05:48:54.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:54.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.05:48:54.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.05:48:54.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.05:48:54.60$vck44/vb=4,5 2006.201.05:48:54.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.05:48:54.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.05:48:54.60#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:54.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:54.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:54.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:54.66#ibcon#enter wrdev, iclass 20, count 2 2006.201.05:48:54.66#ibcon#first serial, iclass 20, count 2 2006.201.05:48:54.66#ibcon#enter sib2, iclass 20, count 2 2006.201.05:48:54.66#ibcon#flushed, iclass 20, count 2 2006.201.05:48:54.66#ibcon#about to write, iclass 20, count 2 2006.201.05:48:54.66#ibcon#wrote, iclass 20, count 2 2006.201.05:48:54.66#ibcon#about to read 3, iclass 20, count 2 2006.201.05:48:54.68#ibcon#read 3, iclass 20, count 2 2006.201.05:48:54.68#ibcon#about to read 4, iclass 20, count 2 2006.201.05:48:54.68#ibcon#read 4, iclass 20, count 2 2006.201.05:48:54.68#ibcon#about to read 5, iclass 20, count 2 2006.201.05:48:54.68#ibcon#read 5, iclass 20, count 2 2006.201.05:48:54.68#ibcon#about to read 6, iclass 20, count 2 2006.201.05:48:54.68#ibcon#read 6, iclass 20, count 2 2006.201.05:48:54.68#ibcon#end of sib2, iclass 20, count 2 2006.201.05:48:54.68#ibcon#*mode == 0, iclass 20, count 2 2006.201.05:48:54.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.05:48:54.68#ibcon#[27=AT04-05\r\n] 2006.201.05:48:54.68#ibcon#*before write, iclass 20, count 2 2006.201.05:48:54.68#ibcon#enter sib2, iclass 20, count 2 2006.201.05:48:54.68#ibcon#flushed, iclass 20, count 2 2006.201.05:48:54.68#ibcon#about to write, iclass 20, count 2 2006.201.05:48:54.68#ibcon#wrote, iclass 20, count 2 2006.201.05:48:54.68#ibcon#about to read 3, iclass 20, count 2 2006.201.05:48:54.71#ibcon#read 3, iclass 20, count 2 2006.201.05:48:54.71#ibcon#about to read 4, iclass 20, count 2 2006.201.05:48:54.71#ibcon#read 4, iclass 20, count 2 2006.201.05:48:54.71#ibcon#about to read 5, iclass 20, count 2 2006.201.05:48:54.71#ibcon#read 5, iclass 20, count 2 2006.201.05:48:54.71#ibcon#about to read 6, iclass 20, count 2 2006.201.05:48:54.71#ibcon#read 6, iclass 20, count 2 2006.201.05:48:54.71#ibcon#end of sib2, iclass 20, count 2 2006.201.05:48:54.71#ibcon#*after write, iclass 20, count 2 2006.201.05:48:54.71#ibcon#*before return 0, iclass 20, count 2 2006.201.05:48:54.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:54.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.05:48:54.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.05:48:54.71#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:54.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:54.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:54.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:54.83#ibcon#enter wrdev, iclass 20, count 0 2006.201.05:48:54.83#ibcon#first serial, iclass 20, count 0 2006.201.05:48:54.83#ibcon#enter sib2, iclass 20, count 0 2006.201.05:48:54.83#ibcon#flushed, iclass 20, count 0 2006.201.05:48:54.83#ibcon#about to write, iclass 20, count 0 2006.201.05:48:54.83#ibcon#wrote, iclass 20, count 0 2006.201.05:48:54.83#ibcon#about to read 3, iclass 20, count 0 2006.201.05:48:54.85#ibcon#read 3, iclass 20, count 0 2006.201.05:48:54.85#ibcon#about to read 4, iclass 20, count 0 2006.201.05:48:54.85#ibcon#read 4, iclass 20, count 0 2006.201.05:48:54.85#ibcon#about to read 5, iclass 20, count 0 2006.201.05:48:54.85#ibcon#read 5, iclass 20, count 0 2006.201.05:48:54.85#ibcon#about to read 6, iclass 20, count 0 2006.201.05:48:54.85#ibcon#read 6, iclass 20, count 0 2006.201.05:48:54.85#ibcon#end of sib2, iclass 20, count 0 2006.201.05:48:54.85#ibcon#*mode == 0, iclass 20, count 0 2006.201.05:48:54.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.05:48:54.85#ibcon#[27=USB\r\n] 2006.201.05:48:54.85#ibcon#*before write, iclass 20, count 0 2006.201.05:48:54.85#ibcon#enter sib2, iclass 20, count 0 2006.201.05:48:54.85#ibcon#flushed, iclass 20, count 0 2006.201.05:48:54.85#ibcon#about to write, iclass 20, count 0 2006.201.05:48:54.85#ibcon#wrote, iclass 20, count 0 2006.201.05:48:54.85#ibcon#about to read 3, iclass 20, count 0 2006.201.05:48:54.88#ibcon#read 3, iclass 20, count 0 2006.201.05:48:54.88#ibcon#about to read 4, iclass 20, count 0 2006.201.05:48:54.88#ibcon#read 4, iclass 20, count 0 2006.201.05:48:54.88#ibcon#about to read 5, iclass 20, count 0 2006.201.05:48:54.88#ibcon#read 5, iclass 20, count 0 2006.201.05:48:54.88#ibcon#about to read 6, iclass 20, count 0 2006.201.05:48:54.88#ibcon#read 6, iclass 20, count 0 2006.201.05:48:54.88#ibcon#end of sib2, iclass 20, count 0 2006.201.05:48:54.88#ibcon#*after write, iclass 20, count 0 2006.201.05:48:54.88#ibcon#*before return 0, iclass 20, count 0 2006.201.05:48:54.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:54.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.05:48:54.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.05:48:54.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.05:48:54.88$vck44/vblo=5,709.99 2006.201.05:48:54.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.05:48:54.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.05:48:54.88#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:54.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:48:54.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:48:54.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:48:54.88#ibcon#enter wrdev, iclass 22, count 0 2006.201.05:48:54.88#ibcon#first serial, iclass 22, count 0 2006.201.05:48:54.88#ibcon#enter sib2, iclass 22, count 0 2006.201.05:48:54.88#ibcon#flushed, iclass 22, count 0 2006.201.05:48:54.88#ibcon#about to write, iclass 22, count 0 2006.201.05:48:54.88#ibcon#wrote, iclass 22, count 0 2006.201.05:48:54.88#ibcon#about to read 3, iclass 22, count 0 2006.201.05:48:54.90#ibcon#read 3, iclass 22, count 0 2006.201.05:48:54.90#ibcon#about to read 4, iclass 22, count 0 2006.201.05:48:54.90#ibcon#read 4, iclass 22, count 0 2006.201.05:48:54.90#ibcon#about to read 5, iclass 22, count 0 2006.201.05:48:54.90#ibcon#read 5, iclass 22, count 0 2006.201.05:48:54.90#ibcon#about to read 6, iclass 22, count 0 2006.201.05:48:54.90#ibcon#read 6, iclass 22, count 0 2006.201.05:48:54.90#ibcon#end of sib2, iclass 22, count 0 2006.201.05:48:54.90#ibcon#*mode == 0, iclass 22, count 0 2006.201.05:48:54.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.05:48:54.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:48:54.90#ibcon#*before write, iclass 22, count 0 2006.201.05:48:54.90#ibcon#enter sib2, iclass 22, count 0 2006.201.05:48:54.90#ibcon#flushed, iclass 22, count 0 2006.201.05:48:54.90#ibcon#about to write, iclass 22, count 0 2006.201.05:48:54.90#ibcon#wrote, iclass 22, count 0 2006.201.05:48:54.90#ibcon#about to read 3, iclass 22, count 0 2006.201.05:48:54.94#ibcon#read 3, iclass 22, count 0 2006.201.05:48:54.94#ibcon#about to read 4, iclass 22, count 0 2006.201.05:48:54.94#ibcon#read 4, iclass 22, count 0 2006.201.05:48:54.94#ibcon#about to read 5, iclass 22, count 0 2006.201.05:48:54.94#ibcon#read 5, iclass 22, count 0 2006.201.05:48:54.94#ibcon#about to read 6, iclass 22, count 0 2006.201.05:48:54.94#ibcon#read 6, iclass 22, count 0 2006.201.05:48:54.94#ibcon#end of sib2, iclass 22, count 0 2006.201.05:48:54.94#ibcon#*after write, iclass 22, count 0 2006.201.05:48:54.94#ibcon#*before return 0, iclass 22, count 0 2006.201.05:48:54.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:48:54.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.05:48:54.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.05:48:54.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.05:48:54.94$vck44/vb=5,4 2006.201.05:48:54.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.05:48:54.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.05:48:54.94#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:54.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:48:55.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:48:55.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:48:55.00#ibcon#enter wrdev, iclass 24, count 2 2006.201.05:48:55.00#ibcon#first serial, iclass 24, count 2 2006.201.05:48:55.00#ibcon#enter sib2, iclass 24, count 2 2006.201.05:48:55.00#ibcon#flushed, iclass 24, count 2 2006.201.05:48:55.00#ibcon#about to write, iclass 24, count 2 2006.201.05:48:55.00#ibcon#wrote, iclass 24, count 2 2006.201.05:48:55.00#ibcon#about to read 3, iclass 24, count 2 2006.201.05:48:55.02#ibcon#read 3, iclass 24, count 2 2006.201.05:48:55.02#ibcon#about to read 4, iclass 24, count 2 2006.201.05:48:55.02#ibcon#read 4, iclass 24, count 2 2006.201.05:48:55.02#ibcon#about to read 5, iclass 24, count 2 2006.201.05:48:55.02#ibcon#read 5, iclass 24, count 2 2006.201.05:48:55.02#ibcon#about to read 6, iclass 24, count 2 2006.201.05:48:55.02#ibcon#read 6, iclass 24, count 2 2006.201.05:48:55.02#ibcon#end of sib2, iclass 24, count 2 2006.201.05:48:55.02#ibcon#*mode == 0, iclass 24, count 2 2006.201.05:48:55.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.05:48:55.02#ibcon#[27=AT05-04\r\n] 2006.201.05:48:55.02#ibcon#*before write, iclass 24, count 2 2006.201.05:48:55.02#ibcon#enter sib2, iclass 24, count 2 2006.201.05:48:55.02#ibcon#flushed, iclass 24, count 2 2006.201.05:48:55.02#ibcon#about to write, iclass 24, count 2 2006.201.05:48:55.02#ibcon#wrote, iclass 24, count 2 2006.201.05:48:55.02#ibcon#about to read 3, iclass 24, count 2 2006.201.05:48:55.05#ibcon#read 3, iclass 24, count 2 2006.201.05:48:55.05#ibcon#about to read 4, iclass 24, count 2 2006.201.05:48:55.05#ibcon#read 4, iclass 24, count 2 2006.201.05:48:55.05#ibcon#about to read 5, iclass 24, count 2 2006.201.05:48:55.05#ibcon#read 5, iclass 24, count 2 2006.201.05:48:55.05#ibcon#about to read 6, iclass 24, count 2 2006.201.05:48:55.05#ibcon#read 6, iclass 24, count 2 2006.201.05:48:55.05#ibcon#end of sib2, iclass 24, count 2 2006.201.05:48:55.05#ibcon#*after write, iclass 24, count 2 2006.201.05:48:55.05#ibcon#*before return 0, iclass 24, count 2 2006.201.05:48:55.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:48:55.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.05:48:55.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.05:48:55.05#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:55.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:48:55.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:48:55.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:48:55.17#ibcon#enter wrdev, iclass 24, count 0 2006.201.05:48:55.17#ibcon#first serial, iclass 24, count 0 2006.201.05:48:55.17#ibcon#enter sib2, iclass 24, count 0 2006.201.05:48:55.17#ibcon#flushed, iclass 24, count 0 2006.201.05:48:55.17#ibcon#about to write, iclass 24, count 0 2006.201.05:48:55.17#ibcon#wrote, iclass 24, count 0 2006.201.05:48:55.17#ibcon#about to read 3, iclass 24, count 0 2006.201.05:48:55.19#ibcon#read 3, iclass 24, count 0 2006.201.05:48:55.19#ibcon#about to read 4, iclass 24, count 0 2006.201.05:48:55.19#ibcon#read 4, iclass 24, count 0 2006.201.05:48:55.19#ibcon#about to read 5, iclass 24, count 0 2006.201.05:48:55.19#ibcon#read 5, iclass 24, count 0 2006.201.05:48:55.19#ibcon#about to read 6, iclass 24, count 0 2006.201.05:48:55.19#ibcon#read 6, iclass 24, count 0 2006.201.05:48:55.19#ibcon#end of sib2, iclass 24, count 0 2006.201.05:48:55.19#ibcon#*mode == 0, iclass 24, count 0 2006.201.05:48:55.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.05:48:55.19#ibcon#[27=USB\r\n] 2006.201.05:48:55.19#ibcon#*before write, iclass 24, count 0 2006.201.05:48:55.19#ibcon#enter sib2, iclass 24, count 0 2006.201.05:48:55.19#ibcon#flushed, iclass 24, count 0 2006.201.05:48:55.19#ibcon#about to write, iclass 24, count 0 2006.201.05:48:55.19#ibcon#wrote, iclass 24, count 0 2006.201.05:48:55.19#ibcon#about to read 3, iclass 24, count 0 2006.201.05:48:55.22#ibcon#read 3, iclass 24, count 0 2006.201.05:48:55.22#ibcon#about to read 4, iclass 24, count 0 2006.201.05:48:55.22#ibcon#read 4, iclass 24, count 0 2006.201.05:48:55.22#ibcon#about to read 5, iclass 24, count 0 2006.201.05:48:55.22#ibcon#read 5, iclass 24, count 0 2006.201.05:48:55.22#ibcon#about to read 6, iclass 24, count 0 2006.201.05:48:55.22#ibcon#read 6, iclass 24, count 0 2006.201.05:48:55.22#ibcon#end of sib2, iclass 24, count 0 2006.201.05:48:55.22#ibcon#*after write, iclass 24, count 0 2006.201.05:48:55.22#ibcon#*before return 0, iclass 24, count 0 2006.201.05:48:55.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:48:55.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.05:48:55.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.05:48:55.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.05:48:55.22$vck44/vblo=6,719.99 2006.201.05:48:55.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.05:48:55.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.05:48:55.22#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:55.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:55.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:55.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:55.22#ibcon#enter wrdev, iclass 26, count 0 2006.201.05:48:55.22#ibcon#first serial, iclass 26, count 0 2006.201.05:48:55.22#ibcon#enter sib2, iclass 26, count 0 2006.201.05:48:55.22#ibcon#flushed, iclass 26, count 0 2006.201.05:48:55.22#ibcon#about to write, iclass 26, count 0 2006.201.05:48:55.22#ibcon#wrote, iclass 26, count 0 2006.201.05:48:55.22#ibcon#about to read 3, iclass 26, count 0 2006.201.05:48:55.24#ibcon#read 3, iclass 26, count 0 2006.201.05:48:55.24#ibcon#about to read 4, iclass 26, count 0 2006.201.05:48:55.24#ibcon#read 4, iclass 26, count 0 2006.201.05:48:55.24#ibcon#about to read 5, iclass 26, count 0 2006.201.05:48:55.24#ibcon#read 5, iclass 26, count 0 2006.201.05:48:55.24#ibcon#about to read 6, iclass 26, count 0 2006.201.05:48:55.24#ibcon#read 6, iclass 26, count 0 2006.201.05:48:55.24#ibcon#end of sib2, iclass 26, count 0 2006.201.05:48:55.24#ibcon#*mode == 0, iclass 26, count 0 2006.201.05:48:55.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.05:48:55.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:48:55.24#ibcon#*before write, iclass 26, count 0 2006.201.05:48:55.24#ibcon#enter sib2, iclass 26, count 0 2006.201.05:48:55.24#ibcon#flushed, iclass 26, count 0 2006.201.05:48:55.24#ibcon#about to write, iclass 26, count 0 2006.201.05:48:55.24#ibcon#wrote, iclass 26, count 0 2006.201.05:48:55.24#ibcon#about to read 3, iclass 26, count 0 2006.201.05:48:55.28#ibcon#read 3, iclass 26, count 0 2006.201.05:48:55.28#ibcon#about to read 4, iclass 26, count 0 2006.201.05:48:55.28#ibcon#read 4, iclass 26, count 0 2006.201.05:48:55.28#ibcon#about to read 5, iclass 26, count 0 2006.201.05:48:55.28#ibcon#read 5, iclass 26, count 0 2006.201.05:48:55.28#ibcon#about to read 6, iclass 26, count 0 2006.201.05:48:55.28#ibcon#read 6, iclass 26, count 0 2006.201.05:48:55.28#ibcon#end of sib2, iclass 26, count 0 2006.201.05:48:55.28#ibcon#*after write, iclass 26, count 0 2006.201.05:48:55.28#ibcon#*before return 0, iclass 26, count 0 2006.201.05:48:55.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:55.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.05:48:55.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.05:48:55.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.05:48:55.28$vck44/vb=6,4 2006.201.05:48:55.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.05:48:55.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.05:48:55.28#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:55.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:55.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:55.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:55.34#ibcon#enter wrdev, iclass 28, count 2 2006.201.05:48:55.34#ibcon#first serial, iclass 28, count 2 2006.201.05:48:55.34#ibcon#enter sib2, iclass 28, count 2 2006.201.05:48:55.34#ibcon#flushed, iclass 28, count 2 2006.201.05:48:55.34#ibcon#about to write, iclass 28, count 2 2006.201.05:48:55.34#ibcon#wrote, iclass 28, count 2 2006.201.05:48:55.34#ibcon#about to read 3, iclass 28, count 2 2006.201.05:48:55.36#ibcon#read 3, iclass 28, count 2 2006.201.05:48:55.36#ibcon#about to read 4, iclass 28, count 2 2006.201.05:48:55.36#ibcon#read 4, iclass 28, count 2 2006.201.05:48:55.36#ibcon#about to read 5, iclass 28, count 2 2006.201.05:48:55.36#ibcon#read 5, iclass 28, count 2 2006.201.05:48:55.36#ibcon#about to read 6, iclass 28, count 2 2006.201.05:48:55.36#ibcon#read 6, iclass 28, count 2 2006.201.05:48:55.36#ibcon#end of sib2, iclass 28, count 2 2006.201.05:48:55.36#ibcon#*mode == 0, iclass 28, count 2 2006.201.05:48:55.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.05:48:55.36#ibcon#[27=AT06-04\r\n] 2006.201.05:48:55.36#ibcon#*before write, iclass 28, count 2 2006.201.05:48:55.36#ibcon#enter sib2, iclass 28, count 2 2006.201.05:48:55.36#ibcon#flushed, iclass 28, count 2 2006.201.05:48:55.36#ibcon#about to write, iclass 28, count 2 2006.201.05:48:55.36#ibcon#wrote, iclass 28, count 2 2006.201.05:48:55.36#ibcon#about to read 3, iclass 28, count 2 2006.201.05:48:55.39#ibcon#read 3, iclass 28, count 2 2006.201.05:48:55.39#ibcon#about to read 4, iclass 28, count 2 2006.201.05:48:55.39#ibcon#read 4, iclass 28, count 2 2006.201.05:48:55.39#ibcon#about to read 5, iclass 28, count 2 2006.201.05:48:55.39#ibcon#read 5, iclass 28, count 2 2006.201.05:48:55.39#ibcon#about to read 6, iclass 28, count 2 2006.201.05:48:55.39#ibcon#read 6, iclass 28, count 2 2006.201.05:48:55.39#ibcon#end of sib2, iclass 28, count 2 2006.201.05:48:55.39#ibcon#*after write, iclass 28, count 2 2006.201.05:48:55.39#ibcon#*before return 0, iclass 28, count 2 2006.201.05:48:55.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:55.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.05:48:55.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.05:48:55.39#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:55.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:55.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:55.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:55.51#ibcon#enter wrdev, iclass 28, count 0 2006.201.05:48:55.51#ibcon#first serial, iclass 28, count 0 2006.201.05:48:55.51#ibcon#enter sib2, iclass 28, count 0 2006.201.05:48:55.51#ibcon#flushed, iclass 28, count 0 2006.201.05:48:55.51#ibcon#about to write, iclass 28, count 0 2006.201.05:48:55.51#ibcon#wrote, iclass 28, count 0 2006.201.05:48:55.51#ibcon#about to read 3, iclass 28, count 0 2006.201.05:48:55.53#ibcon#read 3, iclass 28, count 0 2006.201.05:48:55.53#ibcon#about to read 4, iclass 28, count 0 2006.201.05:48:55.53#ibcon#read 4, iclass 28, count 0 2006.201.05:48:55.53#ibcon#about to read 5, iclass 28, count 0 2006.201.05:48:55.53#ibcon#read 5, iclass 28, count 0 2006.201.05:48:55.53#ibcon#about to read 6, iclass 28, count 0 2006.201.05:48:55.53#ibcon#read 6, iclass 28, count 0 2006.201.05:48:55.53#ibcon#end of sib2, iclass 28, count 0 2006.201.05:48:55.53#ibcon#*mode == 0, iclass 28, count 0 2006.201.05:48:55.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.05:48:55.53#ibcon#[27=USB\r\n] 2006.201.05:48:55.53#ibcon#*before write, iclass 28, count 0 2006.201.05:48:55.53#ibcon#enter sib2, iclass 28, count 0 2006.201.05:48:55.53#ibcon#flushed, iclass 28, count 0 2006.201.05:48:55.53#ibcon#about to write, iclass 28, count 0 2006.201.05:48:55.53#ibcon#wrote, iclass 28, count 0 2006.201.05:48:55.53#ibcon#about to read 3, iclass 28, count 0 2006.201.05:48:55.56#ibcon#read 3, iclass 28, count 0 2006.201.05:48:55.56#ibcon#about to read 4, iclass 28, count 0 2006.201.05:48:55.56#ibcon#read 4, iclass 28, count 0 2006.201.05:48:55.56#ibcon#about to read 5, iclass 28, count 0 2006.201.05:48:55.56#ibcon#read 5, iclass 28, count 0 2006.201.05:48:55.56#ibcon#about to read 6, iclass 28, count 0 2006.201.05:48:55.56#ibcon#read 6, iclass 28, count 0 2006.201.05:48:55.56#ibcon#end of sib2, iclass 28, count 0 2006.201.05:48:55.56#ibcon#*after write, iclass 28, count 0 2006.201.05:48:55.56#ibcon#*before return 0, iclass 28, count 0 2006.201.05:48:55.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:55.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.05:48:55.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.05:48:55.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.05:48:55.56$vck44/vblo=7,734.99 2006.201.05:48:55.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.05:48:55.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.05:48:55.56#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:55.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:55.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:55.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:55.56#ibcon#enter wrdev, iclass 30, count 0 2006.201.05:48:55.56#ibcon#first serial, iclass 30, count 0 2006.201.05:48:55.56#ibcon#enter sib2, iclass 30, count 0 2006.201.05:48:55.56#ibcon#flushed, iclass 30, count 0 2006.201.05:48:55.56#ibcon#about to write, iclass 30, count 0 2006.201.05:48:55.56#ibcon#wrote, iclass 30, count 0 2006.201.05:48:55.56#ibcon#about to read 3, iclass 30, count 0 2006.201.05:48:55.58#ibcon#read 3, iclass 30, count 0 2006.201.05:48:55.58#ibcon#about to read 4, iclass 30, count 0 2006.201.05:48:55.58#ibcon#read 4, iclass 30, count 0 2006.201.05:48:55.58#ibcon#about to read 5, iclass 30, count 0 2006.201.05:48:55.58#ibcon#read 5, iclass 30, count 0 2006.201.05:48:55.58#ibcon#about to read 6, iclass 30, count 0 2006.201.05:48:55.58#ibcon#read 6, iclass 30, count 0 2006.201.05:48:55.58#ibcon#end of sib2, iclass 30, count 0 2006.201.05:48:55.58#ibcon#*mode == 0, iclass 30, count 0 2006.201.05:48:55.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.05:48:55.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:48:55.58#ibcon#*before write, iclass 30, count 0 2006.201.05:48:55.58#ibcon#enter sib2, iclass 30, count 0 2006.201.05:48:55.58#ibcon#flushed, iclass 30, count 0 2006.201.05:48:55.58#ibcon#about to write, iclass 30, count 0 2006.201.05:48:55.58#ibcon#wrote, iclass 30, count 0 2006.201.05:48:55.58#ibcon#about to read 3, iclass 30, count 0 2006.201.05:48:55.62#ibcon#read 3, iclass 30, count 0 2006.201.05:48:55.62#ibcon#about to read 4, iclass 30, count 0 2006.201.05:48:55.62#ibcon#read 4, iclass 30, count 0 2006.201.05:48:55.62#ibcon#about to read 5, iclass 30, count 0 2006.201.05:48:55.62#ibcon#read 5, iclass 30, count 0 2006.201.05:48:55.62#ibcon#about to read 6, iclass 30, count 0 2006.201.05:48:55.62#ibcon#read 6, iclass 30, count 0 2006.201.05:48:55.62#ibcon#end of sib2, iclass 30, count 0 2006.201.05:48:55.62#ibcon#*after write, iclass 30, count 0 2006.201.05:48:55.62#ibcon#*before return 0, iclass 30, count 0 2006.201.05:48:55.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:55.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.05:48:55.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.05:48:55.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.05:48:55.62$vck44/vb=7,4 2006.201.05:48:55.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.05:48:55.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.05:48:55.62#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:55.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:55.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:55.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:55.68#ibcon#enter wrdev, iclass 32, count 2 2006.201.05:48:55.68#ibcon#first serial, iclass 32, count 2 2006.201.05:48:55.68#ibcon#enter sib2, iclass 32, count 2 2006.201.05:48:55.68#ibcon#flushed, iclass 32, count 2 2006.201.05:48:55.68#ibcon#about to write, iclass 32, count 2 2006.201.05:48:55.68#ibcon#wrote, iclass 32, count 2 2006.201.05:48:55.68#ibcon#about to read 3, iclass 32, count 2 2006.201.05:48:55.70#ibcon#read 3, iclass 32, count 2 2006.201.05:48:55.70#ibcon#about to read 4, iclass 32, count 2 2006.201.05:48:55.70#ibcon#read 4, iclass 32, count 2 2006.201.05:48:55.70#ibcon#about to read 5, iclass 32, count 2 2006.201.05:48:55.70#ibcon#read 5, iclass 32, count 2 2006.201.05:48:55.70#ibcon#about to read 6, iclass 32, count 2 2006.201.05:48:55.70#ibcon#read 6, iclass 32, count 2 2006.201.05:48:55.70#ibcon#end of sib2, iclass 32, count 2 2006.201.05:48:55.70#ibcon#*mode == 0, iclass 32, count 2 2006.201.05:48:55.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.05:48:55.70#ibcon#[27=AT07-04\r\n] 2006.201.05:48:55.70#ibcon#*before write, iclass 32, count 2 2006.201.05:48:55.70#ibcon#enter sib2, iclass 32, count 2 2006.201.05:48:55.70#ibcon#flushed, iclass 32, count 2 2006.201.05:48:55.70#ibcon#about to write, iclass 32, count 2 2006.201.05:48:55.70#ibcon#wrote, iclass 32, count 2 2006.201.05:48:55.70#ibcon#about to read 3, iclass 32, count 2 2006.201.05:48:55.73#ibcon#read 3, iclass 32, count 2 2006.201.05:48:55.73#ibcon#about to read 4, iclass 32, count 2 2006.201.05:48:55.73#ibcon#read 4, iclass 32, count 2 2006.201.05:48:55.73#ibcon#about to read 5, iclass 32, count 2 2006.201.05:48:55.73#ibcon#read 5, iclass 32, count 2 2006.201.05:48:55.73#ibcon#about to read 6, iclass 32, count 2 2006.201.05:48:55.73#ibcon#read 6, iclass 32, count 2 2006.201.05:48:55.73#ibcon#end of sib2, iclass 32, count 2 2006.201.05:48:55.73#ibcon#*after write, iclass 32, count 2 2006.201.05:48:55.73#ibcon#*before return 0, iclass 32, count 2 2006.201.05:48:55.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:55.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.05:48:55.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.05:48:55.73#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:55.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:55.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:55.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:55.85#ibcon#enter wrdev, iclass 32, count 0 2006.201.05:48:55.85#ibcon#first serial, iclass 32, count 0 2006.201.05:48:55.85#ibcon#enter sib2, iclass 32, count 0 2006.201.05:48:55.85#ibcon#flushed, iclass 32, count 0 2006.201.05:48:55.85#ibcon#about to write, iclass 32, count 0 2006.201.05:48:55.85#ibcon#wrote, iclass 32, count 0 2006.201.05:48:55.85#ibcon#about to read 3, iclass 32, count 0 2006.201.05:48:55.87#ibcon#read 3, iclass 32, count 0 2006.201.05:48:55.87#ibcon#about to read 4, iclass 32, count 0 2006.201.05:48:55.87#ibcon#read 4, iclass 32, count 0 2006.201.05:48:55.87#ibcon#about to read 5, iclass 32, count 0 2006.201.05:48:55.87#ibcon#read 5, iclass 32, count 0 2006.201.05:48:55.87#ibcon#about to read 6, iclass 32, count 0 2006.201.05:48:55.87#ibcon#read 6, iclass 32, count 0 2006.201.05:48:55.87#ibcon#end of sib2, iclass 32, count 0 2006.201.05:48:55.87#ibcon#*mode == 0, iclass 32, count 0 2006.201.05:48:55.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.05:48:55.87#ibcon#[27=USB\r\n] 2006.201.05:48:55.87#ibcon#*before write, iclass 32, count 0 2006.201.05:48:55.87#ibcon#enter sib2, iclass 32, count 0 2006.201.05:48:55.87#ibcon#flushed, iclass 32, count 0 2006.201.05:48:55.87#ibcon#about to write, iclass 32, count 0 2006.201.05:48:55.87#ibcon#wrote, iclass 32, count 0 2006.201.05:48:55.87#ibcon#about to read 3, iclass 32, count 0 2006.201.05:48:55.91#ibcon#read 3, iclass 32, count 0 2006.201.05:48:55.91#ibcon#about to read 4, iclass 32, count 0 2006.201.05:48:55.91#ibcon#read 4, iclass 32, count 0 2006.201.05:48:55.91#ibcon#about to read 5, iclass 32, count 0 2006.201.05:48:55.91#ibcon#read 5, iclass 32, count 0 2006.201.05:48:55.91#ibcon#about to read 6, iclass 32, count 0 2006.201.05:48:55.91#ibcon#read 6, iclass 32, count 0 2006.201.05:48:55.91#ibcon#end of sib2, iclass 32, count 0 2006.201.05:48:55.91#ibcon#*after write, iclass 32, count 0 2006.201.05:48:55.91#ibcon#*before return 0, iclass 32, count 0 2006.201.05:48:55.91#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:55.91#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.05:48:55.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.05:48:55.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.05:48:55.91$vck44/vblo=8,744.99 2006.201.05:48:55.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.05:48:55.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.05:48:55.91#ibcon#ireg 17 cls_cnt 0 2006.201.05:48:55.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:55.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:55.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:55.91#ibcon#enter wrdev, iclass 34, count 0 2006.201.05:48:55.91#ibcon#first serial, iclass 34, count 0 2006.201.05:48:55.91#ibcon#enter sib2, iclass 34, count 0 2006.201.05:48:55.91#ibcon#flushed, iclass 34, count 0 2006.201.05:48:55.91#ibcon#about to write, iclass 34, count 0 2006.201.05:48:55.91#ibcon#wrote, iclass 34, count 0 2006.201.05:48:55.91#ibcon#about to read 3, iclass 34, count 0 2006.201.05:48:55.93#ibcon#read 3, iclass 34, count 0 2006.201.05:48:55.93#ibcon#about to read 4, iclass 34, count 0 2006.201.05:48:55.93#ibcon#read 4, iclass 34, count 0 2006.201.05:48:55.93#ibcon#about to read 5, iclass 34, count 0 2006.201.05:48:55.93#ibcon#read 5, iclass 34, count 0 2006.201.05:48:55.93#ibcon#about to read 6, iclass 34, count 0 2006.201.05:48:55.93#ibcon#read 6, iclass 34, count 0 2006.201.05:48:55.93#ibcon#end of sib2, iclass 34, count 0 2006.201.05:48:55.93#ibcon#*mode == 0, iclass 34, count 0 2006.201.05:48:55.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.05:48:55.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:48:55.93#ibcon#*before write, iclass 34, count 0 2006.201.05:48:55.93#ibcon#enter sib2, iclass 34, count 0 2006.201.05:48:55.93#ibcon#flushed, iclass 34, count 0 2006.201.05:48:55.93#ibcon#about to write, iclass 34, count 0 2006.201.05:48:55.93#ibcon#wrote, iclass 34, count 0 2006.201.05:48:55.93#ibcon#about to read 3, iclass 34, count 0 2006.201.05:48:55.97#ibcon#read 3, iclass 34, count 0 2006.201.05:48:55.97#ibcon#about to read 4, iclass 34, count 0 2006.201.05:48:55.97#ibcon#read 4, iclass 34, count 0 2006.201.05:48:55.97#ibcon#about to read 5, iclass 34, count 0 2006.201.05:48:55.97#ibcon#read 5, iclass 34, count 0 2006.201.05:48:55.97#ibcon#about to read 6, iclass 34, count 0 2006.201.05:48:55.97#ibcon#read 6, iclass 34, count 0 2006.201.05:48:55.97#ibcon#end of sib2, iclass 34, count 0 2006.201.05:48:55.97#ibcon#*after write, iclass 34, count 0 2006.201.05:48:55.97#ibcon#*before return 0, iclass 34, count 0 2006.201.05:48:55.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:55.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.05:48:55.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.05:48:55.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.05:48:55.97$vck44/vb=8,4 2006.201.05:48:55.97#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.05:48:55.97#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.05:48:55.97#ibcon#ireg 11 cls_cnt 2 2006.201.05:48:55.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:56.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:56.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:56.03#ibcon#enter wrdev, iclass 36, count 2 2006.201.05:48:56.03#ibcon#first serial, iclass 36, count 2 2006.201.05:48:56.03#ibcon#enter sib2, iclass 36, count 2 2006.201.05:48:56.03#ibcon#flushed, iclass 36, count 2 2006.201.05:48:56.03#ibcon#about to write, iclass 36, count 2 2006.201.05:48:56.03#ibcon#wrote, iclass 36, count 2 2006.201.05:48:56.03#ibcon#about to read 3, iclass 36, count 2 2006.201.05:48:56.05#ibcon#read 3, iclass 36, count 2 2006.201.05:48:56.05#ibcon#about to read 4, iclass 36, count 2 2006.201.05:48:56.05#ibcon#read 4, iclass 36, count 2 2006.201.05:48:56.05#ibcon#about to read 5, iclass 36, count 2 2006.201.05:48:56.05#ibcon#read 5, iclass 36, count 2 2006.201.05:48:56.05#ibcon#about to read 6, iclass 36, count 2 2006.201.05:48:56.05#ibcon#read 6, iclass 36, count 2 2006.201.05:48:56.05#ibcon#end of sib2, iclass 36, count 2 2006.201.05:48:56.05#ibcon#*mode == 0, iclass 36, count 2 2006.201.05:48:56.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.05:48:56.05#ibcon#[27=AT08-04\r\n] 2006.201.05:48:56.05#ibcon#*before write, iclass 36, count 2 2006.201.05:48:56.05#ibcon#enter sib2, iclass 36, count 2 2006.201.05:48:56.05#ibcon#flushed, iclass 36, count 2 2006.201.05:48:56.05#ibcon#about to write, iclass 36, count 2 2006.201.05:48:56.05#ibcon#wrote, iclass 36, count 2 2006.201.05:48:56.05#ibcon#about to read 3, iclass 36, count 2 2006.201.05:48:56.08#ibcon#read 3, iclass 36, count 2 2006.201.05:48:56.08#ibcon#about to read 4, iclass 36, count 2 2006.201.05:48:56.08#ibcon#read 4, iclass 36, count 2 2006.201.05:48:56.08#ibcon#about to read 5, iclass 36, count 2 2006.201.05:48:56.08#ibcon#read 5, iclass 36, count 2 2006.201.05:48:56.08#ibcon#about to read 6, iclass 36, count 2 2006.201.05:48:56.08#ibcon#read 6, iclass 36, count 2 2006.201.05:48:56.08#ibcon#end of sib2, iclass 36, count 2 2006.201.05:48:56.08#ibcon#*after write, iclass 36, count 2 2006.201.05:48:56.08#ibcon#*before return 0, iclass 36, count 2 2006.201.05:48:56.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:56.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.05:48:56.08#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.05:48:56.08#ibcon#ireg 7 cls_cnt 0 2006.201.05:48:56.08#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:56.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:56.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:56.20#ibcon#enter wrdev, iclass 36, count 0 2006.201.05:48:56.20#ibcon#first serial, iclass 36, count 0 2006.201.05:48:56.20#ibcon#enter sib2, iclass 36, count 0 2006.201.05:48:56.20#ibcon#flushed, iclass 36, count 0 2006.201.05:48:56.20#ibcon#about to write, iclass 36, count 0 2006.201.05:48:56.20#ibcon#wrote, iclass 36, count 0 2006.201.05:48:56.20#ibcon#about to read 3, iclass 36, count 0 2006.201.05:48:56.22#ibcon#read 3, iclass 36, count 0 2006.201.05:48:56.22#ibcon#about to read 4, iclass 36, count 0 2006.201.05:48:56.22#ibcon#read 4, iclass 36, count 0 2006.201.05:48:56.22#ibcon#about to read 5, iclass 36, count 0 2006.201.05:48:56.22#ibcon#read 5, iclass 36, count 0 2006.201.05:48:56.22#ibcon#about to read 6, iclass 36, count 0 2006.201.05:48:56.22#ibcon#read 6, iclass 36, count 0 2006.201.05:48:56.22#ibcon#end of sib2, iclass 36, count 0 2006.201.05:48:56.22#ibcon#*mode == 0, iclass 36, count 0 2006.201.05:48:56.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.05:48:56.22#ibcon#[27=USB\r\n] 2006.201.05:48:56.22#ibcon#*before write, iclass 36, count 0 2006.201.05:48:56.22#ibcon#enter sib2, iclass 36, count 0 2006.201.05:48:56.22#ibcon#flushed, iclass 36, count 0 2006.201.05:48:56.22#ibcon#about to write, iclass 36, count 0 2006.201.05:48:56.22#ibcon#wrote, iclass 36, count 0 2006.201.05:48:56.22#ibcon#about to read 3, iclass 36, count 0 2006.201.05:48:56.25#ibcon#read 3, iclass 36, count 0 2006.201.05:48:56.25#ibcon#about to read 4, iclass 36, count 0 2006.201.05:48:56.25#ibcon#read 4, iclass 36, count 0 2006.201.05:48:56.25#ibcon#about to read 5, iclass 36, count 0 2006.201.05:48:56.25#ibcon#read 5, iclass 36, count 0 2006.201.05:48:56.25#ibcon#about to read 6, iclass 36, count 0 2006.201.05:48:56.25#ibcon#read 6, iclass 36, count 0 2006.201.05:48:56.25#ibcon#end of sib2, iclass 36, count 0 2006.201.05:48:56.25#ibcon#*after write, iclass 36, count 0 2006.201.05:48:56.25#ibcon#*before return 0, iclass 36, count 0 2006.201.05:48:56.25#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:56.25#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.05:48:56.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.05:48:56.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.05:48:56.25$vck44/vabw=wide 2006.201.05:48:56.25#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.05:48:56.25#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.05:48:56.25#ibcon#ireg 8 cls_cnt 0 2006.201.05:48:56.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:56.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:56.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:56.25#ibcon#enter wrdev, iclass 38, count 0 2006.201.05:48:56.25#ibcon#first serial, iclass 38, count 0 2006.201.05:48:56.25#ibcon#enter sib2, iclass 38, count 0 2006.201.05:48:56.25#ibcon#flushed, iclass 38, count 0 2006.201.05:48:56.25#ibcon#about to write, iclass 38, count 0 2006.201.05:48:56.25#ibcon#wrote, iclass 38, count 0 2006.201.05:48:56.25#ibcon#about to read 3, iclass 38, count 0 2006.201.05:48:56.27#ibcon#read 3, iclass 38, count 0 2006.201.05:48:56.27#ibcon#about to read 4, iclass 38, count 0 2006.201.05:48:56.27#ibcon#read 4, iclass 38, count 0 2006.201.05:48:56.27#ibcon#about to read 5, iclass 38, count 0 2006.201.05:48:56.27#ibcon#read 5, iclass 38, count 0 2006.201.05:48:56.27#ibcon#about to read 6, iclass 38, count 0 2006.201.05:48:56.27#ibcon#read 6, iclass 38, count 0 2006.201.05:48:56.27#ibcon#end of sib2, iclass 38, count 0 2006.201.05:48:56.27#ibcon#*mode == 0, iclass 38, count 0 2006.201.05:48:56.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.05:48:56.27#ibcon#[25=BW32\r\n] 2006.201.05:48:56.27#ibcon#*before write, iclass 38, count 0 2006.201.05:48:56.27#ibcon#enter sib2, iclass 38, count 0 2006.201.05:48:56.27#ibcon#flushed, iclass 38, count 0 2006.201.05:48:56.27#ibcon#about to write, iclass 38, count 0 2006.201.05:48:56.27#ibcon#wrote, iclass 38, count 0 2006.201.05:48:56.27#ibcon#about to read 3, iclass 38, count 0 2006.201.05:48:56.30#ibcon#read 3, iclass 38, count 0 2006.201.05:48:56.30#ibcon#about to read 4, iclass 38, count 0 2006.201.05:48:56.30#ibcon#read 4, iclass 38, count 0 2006.201.05:48:56.30#ibcon#about to read 5, iclass 38, count 0 2006.201.05:48:56.30#ibcon#read 5, iclass 38, count 0 2006.201.05:48:56.30#ibcon#about to read 6, iclass 38, count 0 2006.201.05:48:56.30#ibcon#read 6, iclass 38, count 0 2006.201.05:48:56.30#ibcon#end of sib2, iclass 38, count 0 2006.201.05:48:56.30#ibcon#*after write, iclass 38, count 0 2006.201.05:48:56.30#ibcon#*before return 0, iclass 38, count 0 2006.201.05:48:56.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:56.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.05:48:56.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.05:48:56.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.05:48:56.30$vck44/vbbw=wide 2006.201.05:48:56.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.05:48:56.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.05:48:56.30#ibcon#ireg 8 cls_cnt 0 2006.201.05:48:56.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:48:56.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:48:56.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:48:56.37#ibcon#enter wrdev, iclass 40, count 0 2006.201.05:48:56.37#ibcon#first serial, iclass 40, count 0 2006.201.05:48:56.37#ibcon#enter sib2, iclass 40, count 0 2006.201.05:48:56.37#ibcon#flushed, iclass 40, count 0 2006.201.05:48:56.37#ibcon#about to write, iclass 40, count 0 2006.201.05:48:56.37#ibcon#wrote, iclass 40, count 0 2006.201.05:48:56.37#ibcon#about to read 3, iclass 40, count 0 2006.201.05:48:56.39#ibcon#read 3, iclass 40, count 0 2006.201.05:48:56.39#ibcon#about to read 4, iclass 40, count 0 2006.201.05:48:56.39#ibcon#read 4, iclass 40, count 0 2006.201.05:48:56.39#ibcon#about to read 5, iclass 40, count 0 2006.201.05:48:56.39#ibcon#read 5, iclass 40, count 0 2006.201.05:48:56.39#ibcon#about to read 6, iclass 40, count 0 2006.201.05:48:56.39#ibcon#read 6, iclass 40, count 0 2006.201.05:48:56.39#ibcon#end of sib2, iclass 40, count 0 2006.201.05:48:56.39#ibcon#*mode == 0, iclass 40, count 0 2006.201.05:48:56.39#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.05:48:56.39#ibcon#[27=BW32\r\n] 2006.201.05:48:56.39#ibcon#*before write, iclass 40, count 0 2006.201.05:48:56.39#ibcon#enter sib2, iclass 40, count 0 2006.201.05:48:56.39#ibcon#flushed, iclass 40, count 0 2006.201.05:48:56.39#ibcon#about to write, iclass 40, count 0 2006.201.05:48:56.39#ibcon#wrote, iclass 40, count 0 2006.201.05:48:56.39#ibcon#about to read 3, iclass 40, count 0 2006.201.05:48:56.42#ibcon#read 3, iclass 40, count 0 2006.201.05:48:56.42#ibcon#about to read 4, iclass 40, count 0 2006.201.05:48:56.42#ibcon#read 4, iclass 40, count 0 2006.201.05:48:56.42#ibcon#about to read 5, iclass 40, count 0 2006.201.05:48:56.42#ibcon#read 5, iclass 40, count 0 2006.201.05:48:56.42#ibcon#about to read 6, iclass 40, count 0 2006.201.05:48:56.42#ibcon#read 6, iclass 40, count 0 2006.201.05:48:56.42#ibcon#end of sib2, iclass 40, count 0 2006.201.05:48:56.42#ibcon#*after write, iclass 40, count 0 2006.201.05:48:56.42#ibcon#*before return 0, iclass 40, count 0 2006.201.05:48:56.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:48:56.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.05:48:56.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.05:48:56.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.05:48:56.42$setupk4/ifdk4 2006.201.05:48:56.42$ifdk4/lo= 2006.201.05:48:56.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:48:56.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:48:56.42$ifdk4/patch= 2006.201.05:48:56.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:48:56.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:48:56.42$setupk4/!*+20s 2006.201.05:49:02.19#abcon#<5=/04 2.6 4.7 23.03 901003.4\r\n> 2006.201.05:49:02.22#abcon#{5=INTERFACE CLEAR} 2006.201.05:49:02.28#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:49:04.14#trakl#Source acquired 2006.201.05:49:06.14#flagr#flagr/antenna,acquired 2006.201.05:49:10.87$setupk4/"tpicd 2006.201.05:49:10.87$setupk4/echo=off 2006.201.05:49:10.87$setupk4/xlog=off 2006.201.05:49:10.87:!2006.201.05:50:17 2006.201.05:50:17.00:preob 2006.201.05:50:17.14/onsource/TRACKING 2006.201.05:50:17.14:!2006.201.05:50:27 2006.201.05:50:27.01:"tape 2006.201.05:50:27.01:"st=record 2006.201.05:50:27.01:data_valid=on 2006.201.05:50:27.01:midob 2006.201.05:50:28.14/onsource/TRACKING 2006.201.05:50:28.14/wx/23.02,1003.4,90 2006.201.05:50:28.34/cable/+6.4650E-03 2006.201.05:50:29.43/va/01,08,usb,yes,31,33 2006.201.05:50:29.43/va/02,07,usb,yes,33,34 2006.201.05:50:29.43/va/03,08,usb,yes,30,31 2006.201.05:50:29.43/va/04,07,usb,yes,34,36 2006.201.05:50:29.43/va/05,04,usb,yes,30,30 2006.201.05:50:29.43/va/06,05,usb,yes,30,30 2006.201.05:50:29.43/va/07,05,usb,yes,29,30 2006.201.05:50:29.43/va/08,04,usb,yes,29,35 2006.201.05:50:29.66/valo/01,524.99,yes,locked 2006.201.05:50:29.66/valo/02,534.99,yes,locked 2006.201.05:50:29.66/valo/03,564.99,yes,locked 2006.201.05:50:29.66/valo/04,624.99,yes,locked 2006.201.05:50:29.66/valo/05,734.99,yes,locked 2006.201.05:50:29.66/valo/06,814.99,yes,locked 2006.201.05:50:29.66/valo/07,864.99,yes,locked 2006.201.05:50:29.66/valo/08,884.99,yes,locked 2006.201.05:50:30.75/vb/01,04,usb,yes,35,33 2006.201.05:50:30.75/vb/02,05,usb,yes,33,33 2006.201.05:50:30.75/vb/03,04,usb,yes,34,38 2006.201.05:50:30.75/vb/04,05,usb,yes,35,34 2006.201.05:50:30.75/vb/05,04,usb,yes,31,33 2006.201.05:50:30.75/vb/06,04,usb,yes,35,31 2006.201.05:50:30.75/vb/07,04,usb,yes,35,35 2006.201.05:50:30.75/vb/08,04,usb,yes,32,36 2006.201.05:50:30.99/vblo/01,629.99,yes,locked 2006.201.05:50:30.99/vblo/02,634.99,yes,locked 2006.201.05:50:30.99/vblo/03,649.99,yes,locked 2006.201.05:50:30.99/vblo/04,679.99,yes,locked 2006.201.05:50:30.99/vblo/05,709.99,yes,locked 2006.201.05:50:30.99/vblo/06,719.99,yes,locked 2006.201.05:50:30.99/vblo/07,734.99,yes,locked 2006.201.05:50:30.99/vblo/08,744.99,yes,locked 2006.201.05:50:31.14/vabw/8 2006.201.05:50:31.29/vbbw/8 2006.201.05:50:31.44/xfe/off,on,14.5 2006.201.05:50:31.81/ifatt/23,28,28,28 2006.201.05:50:32.04/fmout-gps/S +4.52E-07 2006.201.05:50:32.09:!2006.201.05:51:57 2006.201.05:51:57.00:data_valid=off 2006.201.05:51:57.00:"et 2006.201.05:51:57.00:!+3s 2006.201.05:52:00.02:"tape 2006.201.05:52:00.02:postob 2006.201.05:52:00.14/cable/+6.4652E-03 2006.201.05:52:00.14/wx/23.02,1003.4,90 2006.201.05:52:00.20/fmout-gps/S +4.51E-07 2006.201.05:52:00.20:scan_name=201-0600,jd0607,40 2006.201.05:52:00.20:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.201.05:52:01.14#flagr#flagr/antenna,new-source 2006.201.05:52:01.14:checkk5 2006.201.05:52:01.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.05:52:01.92/chk_autoobs//k5ts2/ autoobs is running! 2006.201.05:52:02.31/chk_autoobs//k5ts3/ autoobs is running! 2006.201.05:52:02.69/chk_autoobs//k5ts4/ autoobs is running! 2006.201.05:52:03.06/chk_obsdata//k5ts1/T2010550??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.05:52:03.44/chk_obsdata//k5ts2/T2010550??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.05:52:03.82/chk_obsdata//k5ts3/T2010550??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.05:52:04.19/chk_obsdata//k5ts4/T2010550??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.05:52:04.88/k5log//k5ts1_log_newline 2006.201.05:52:05.58/k5log//k5ts2_log_newline 2006.201.05:52:06.28/k5log//k5ts3_log_newline 2006.201.05:52:07.00/k5log//k5ts4_log_newline 2006.201.05:52:07.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.05:52:07.02:setupk4=1 2006.201.05:52:07.02$setupk4/echo=on 2006.201.05:52:07.02$setupk4/pcalon 2006.201.05:52:07.02$pcalon/"no phase cal control is implemented here 2006.201.05:52:07.02$setupk4/"tpicd=stop 2006.201.05:52:07.02$setupk4/"rec=synch_on 2006.201.05:52:07.02$setupk4/"rec_mode=128 2006.201.05:52:07.02$setupk4/!* 2006.201.05:52:07.02$setupk4/recpk4 2006.201.05:52:07.02$recpk4/recpatch= 2006.201.05:52:07.03$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.05:52:07.03$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.05:52:07.03$setupk4/vck44 2006.201.05:52:07.03$vck44/valo=1,524.99 2006.201.05:52:07.03#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.05:52:07.03#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.05:52:07.03#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:07.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:07.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:07.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:07.03#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:52:07.03#ibcon#first serial, iclass 13, count 0 2006.201.05:52:07.03#ibcon#enter sib2, iclass 13, count 0 2006.201.05:52:07.03#ibcon#flushed, iclass 13, count 0 2006.201.05:52:07.03#ibcon#about to write, iclass 13, count 0 2006.201.05:52:07.03#ibcon#wrote, iclass 13, count 0 2006.201.05:52:07.03#ibcon#about to read 3, iclass 13, count 0 2006.201.05:52:07.07#ibcon#read 3, iclass 13, count 0 2006.201.05:52:07.07#ibcon#about to read 4, iclass 13, count 0 2006.201.05:52:07.07#ibcon#read 4, iclass 13, count 0 2006.201.05:52:07.07#ibcon#about to read 5, iclass 13, count 0 2006.201.05:52:07.07#ibcon#read 5, iclass 13, count 0 2006.201.05:52:07.07#ibcon#about to read 6, iclass 13, count 0 2006.201.05:52:07.07#ibcon#read 6, iclass 13, count 0 2006.201.05:52:07.07#ibcon#end of sib2, iclass 13, count 0 2006.201.05:52:07.07#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:52:07.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:52:07.07#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.05:52:07.07#ibcon#*before write, iclass 13, count 0 2006.201.05:52:07.07#ibcon#enter sib2, iclass 13, count 0 2006.201.05:52:07.07#ibcon#flushed, iclass 13, count 0 2006.201.05:52:07.07#ibcon#about to write, iclass 13, count 0 2006.201.05:52:07.07#ibcon#wrote, iclass 13, count 0 2006.201.05:52:07.07#ibcon#about to read 3, iclass 13, count 0 2006.201.05:52:07.12#ibcon#read 3, iclass 13, count 0 2006.201.05:52:07.12#ibcon#about to read 4, iclass 13, count 0 2006.201.05:52:07.12#ibcon#read 4, iclass 13, count 0 2006.201.05:52:07.12#ibcon#about to read 5, iclass 13, count 0 2006.201.05:52:07.12#ibcon#read 5, iclass 13, count 0 2006.201.05:52:07.12#ibcon#about to read 6, iclass 13, count 0 2006.201.05:52:07.12#ibcon#read 6, iclass 13, count 0 2006.201.05:52:07.12#ibcon#end of sib2, iclass 13, count 0 2006.201.05:52:07.12#ibcon#*after write, iclass 13, count 0 2006.201.05:52:07.12#ibcon#*before return 0, iclass 13, count 0 2006.201.05:52:07.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:07.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:07.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:52:07.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:52:07.12$vck44/va=1,8 2006.201.05:52:07.12#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.05:52:07.12#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.05:52:07.12#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:07.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:07.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:07.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:07.12#ibcon#enter wrdev, iclass 15, count 2 2006.201.05:52:07.12#ibcon#first serial, iclass 15, count 2 2006.201.05:52:07.12#ibcon#enter sib2, iclass 15, count 2 2006.201.05:52:07.12#ibcon#flushed, iclass 15, count 2 2006.201.05:52:07.12#ibcon#about to write, iclass 15, count 2 2006.201.05:52:07.12#ibcon#wrote, iclass 15, count 2 2006.201.05:52:07.12#ibcon#about to read 3, iclass 15, count 2 2006.201.05:52:07.14#ibcon#read 3, iclass 15, count 2 2006.201.05:52:07.14#ibcon#about to read 4, iclass 15, count 2 2006.201.05:52:07.14#ibcon#read 4, iclass 15, count 2 2006.201.05:52:07.14#ibcon#about to read 5, iclass 15, count 2 2006.201.05:52:07.14#ibcon#read 5, iclass 15, count 2 2006.201.05:52:07.14#ibcon#about to read 6, iclass 15, count 2 2006.201.05:52:07.14#ibcon#read 6, iclass 15, count 2 2006.201.05:52:07.14#ibcon#end of sib2, iclass 15, count 2 2006.201.05:52:07.14#ibcon#*mode == 0, iclass 15, count 2 2006.201.05:52:07.14#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.05:52:07.14#ibcon#[25=AT01-08\r\n] 2006.201.05:52:07.14#ibcon#*before write, iclass 15, count 2 2006.201.05:52:07.14#ibcon#enter sib2, iclass 15, count 2 2006.201.05:52:07.14#ibcon#flushed, iclass 15, count 2 2006.201.05:52:07.14#ibcon#about to write, iclass 15, count 2 2006.201.05:52:07.14#ibcon#wrote, iclass 15, count 2 2006.201.05:52:07.14#ibcon#about to read 3, iclass 15, count 2 2006.201.05:52:07.17#ibcon#read 3, iclass 15, count 2 2006.201.05:52:07.17#ibcon#about to read 4, iclass 15, count 2 2006.201.05:52:07.17#ibcon#read 4, iclass 15, count 2 2006.201.05:52:07.17#ibcon#about to read 5, iclass 15, count 2 2006.201.05:52:07.17#ibcon#read 5, iclass 15, count 2 2006.201.05:52:07.17#ibcon#about to read 6, iclass 15, count 2 2006.201.05:52:07.17#ibcon#read 6, iclass 15, count 2 2006.201.05:52:07.17#ibcon#end of sib2, iclass 15, count 2 2006.201.05:52:07.17#ibcon#*after write, iclass 15, count 2 2006.201.05:52:07.17#ibcon#*before return 0, iclass 15, count 2 2006.201.05:52:07.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:07.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:07.17#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.05:52:07.17#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:07.17#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:07.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:07.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:07.29#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:52:07.29#ibcon#first serial, iclass 15, count 0 2006.201.05:52:07.29#ibcon#enter sib2, iclass 15, count 0 2006.201.05:52:07.29#ibcon#flushed, iclass 15, count 0 2006.201.05:52:07.29#ibcon#about to write, iclass 15, count 0 2006.201.05:52:07.29#ibcon#wrote, iclass 15, count 0 2006.201.05:52:07.29#ibcon#about to read 3, iclass 15, count 0 2006.201.05:52:07.31#ibcon#read 3, iclass 15, count 0 2006.201.05:52:07.31#ibcon#about to read 4, iclass 15, count 0 2006.201.05:52:07.31#ibcon#read 4, iclass 15, count 0 2006.201.05:52:07.31#ibcon#about to read 5, iclass 15, count 0 2006.201.05:52:07.31#ibcon#read 5, iclass 15, count 0 2006.201.05:52:07.31#ibcon#about to read 6, iclass 15, count 0 2006.201.05:52:07.31#ibcon#read 6, iclass 15, count 0 2006.201.05:52:07.31#ibcon#end of sib2, iclass 15, count 0 2006.201.05:52:07.31#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:52:07.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:52:07.31#ibcon#[25=USB\r\n] 2006.201.05:52:07.31#ibcon#*before write, iclass 15, count 0 2006.201.05:52:07.31#ibcon#enter sib2, iclass 15, count 0 2006.201.05:52:07.31#ibcon#flushed, iclass 15, count 0 2006.201.05:52:07.31#ibcon#about to write, iclass 15, count 0 2006.201.05:52:07.31#ibcon#wrote, iclass 15, count 0 2006.201.05:52:07.31#ibcon#about to read 3, iclass 15, count 0 2006.201.05:52:07.34#ibcon#read 3, iclass 15, count 0 2006.201.05:52:07.34#ibcon#about to read 4, iclass 15, count 0 2006.201.05:52:07.34#ibcon#read 4, iclass 15, count 0 2006.201.05:52:07.34#ibcon#about to read 5, iclass 15, count 0 2006.201.05:52:07.34#ibcon#read 5, iclass 15, count 0 2006.201.05:52:07.34#ibcon#about to read 6, iclass 15, count 0 2006.201.05:52:07.34#ibcon#read 6, iclass 15, count 0 2006.201.05:52:07.34#ibcon#end of sib2, iclass 15, count 0 2006.201.05:52:07.34#ibcon#*after write, iclass 15, count 0 2006.201.05:52:07.34#ibcon#*before return 0, iclass 15, count 0 2006.201.05:52:07.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:07.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:07.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:52:07.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:52:07.34$vck44/valo=2,534.99 2006.201.05:52:07.34#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.05:52:07.34#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.05:52:07.34#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:07.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:07.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:07.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:07.34#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:52:07.34#ibcon#first serial, iclass 17, count 0 2006.201.05:52:07.34#ibcon#enter sib2, iclass 17, count 0 2006.201.05:52:07.34#ibcon#flushed, iclass 17, count 0 2006.201.05:52:07.34#ibcon#about to write, iclass 17, count 0 2006.201.05:52:07.34#ibcon#wrote, iclass 17, count 0 2006.201.05:52:07.34#ibcon#about to read 3, iclass 17, count 0 2006.201.05:52:07.36#ibcon#read 3, iclass 17, count 0 2006.201.05:52:07.36#ibcon#about to read 4, iclass 17, count 0 2006.201.05:52:07.36#ibcon#read 4, iclass 17, count 0 2006.201.05:52:07.36#ibcon#about to read 5, iclass 17, count 0 2006.201.05:52:07.36#ibcon#read 5, iclass 17, count 0 2006.201.05:52:07.36#ibcon#about to read 6, iclass 17, count 0 2006.201.05:52:07.36#ibcon#read 6, iclass 17, count 0 2006.201.05:52:07.36#ibcon#end of sib2, iclass 17, count 0 2006.201.05:52:07.36#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:52:07.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:52:07.36#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.05:52:07.36#ibcon#*before write, iclass 17, count 0 2006.201.05:52:07.36#ibcon#enter sib2, iclass 17, count 0 2006.201.05:52:07.36#ibcon#flushed, iclass 17, count 0 2006.201.05:52:07.36#ibcon#about to write, iclass 17, count 0 2006.201.05:52:07.36#ibcon#wrote, iclass 17, count 0 2006.201.05:52:07.36#ibcon#about to read 3, iclass 17, count 0 2006.201.05:52:07.40#ibcon#read 3, iclass 17, count 0 2006.201.05:52:07.40#ibcon#about to read 4, iclass 17, count 0 2006.201.05:52:07.40#ibcon#read 4, iclass 17, count 0 2006.201.05:52:07.40#ibcon#about to read 5, iclass 17, count 0 2006.201.05:52:07.40#ibcon#read 5, iclass 17, count 0 2006.201.05:52:07.40#ibcon#about to read 6, iclass 17, count 0 2006.201.05:52:07.40#ibcon#read 6, iclass 17, count 0 2006.201.05:52:07.40#ibcon#end of sib2, iclass 17, count 0 2006.201.05:52:07.40#ibcon#*after write, iclass 17, count 0 2006.201.05:52:07.40#ibcon#*before return 0, iclass 17, count 0 2006.201.05:52:07.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:07.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:07.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:52:07.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:52:07.40$vck44/va=2,7 2006.201.05:52:07.40#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.05:52:07.40#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.05:52:07.40#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:07.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:07.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:07.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:07.46#ibcon#enter wrdev, iclass 19, count 2 2006.201.05:52:07.46#ibcon#first serial, iclass 19, count 2 2006.201.05:52:07.46#ibcon#enter sib2, iclass 19, count 2 2006.201.05:52:07.46#ibcon#flushed, iclass 19, count 2 2006.201.05:52:07.46#ibcon#about to write, iclass 19, count 2 2006.201.05:52:07.46#ibcon#wrote, iclass 19, count 2 2006.201.05:52:07.46#ibcon#about to read 3, iclass 19, count 2 2006.201.05:52:07.48#ibcon#read 3, iclass 19, count 2 2006.201.05:52:07.48#ibcon#about to read 4, iclass 19, count 2 2006.201.05:52:07.48#ibcon#read 4, iclass 19, count 2 2006.201.05:52:07.48#ibcon#about to read 5, iclass 19, count 2 2006.201.05:52:07.48#ibcon#read 5, iclass 19, count 2 2006.201.05:52:07.48#ibcon#about to read 6, iclass 19, count 2 2006.201.05:52:07.48#ibcon#read 6, iclass 19, count 2 2006.201.05:52:07.48#ibcon#end of sib2, iclass 19, count 2 2006.201.05:52:07.48#ibcon#*mode == 0, iclass 19, count 2 2006.201.05:52:07.48#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.05:52:07.48#ibcon#[25=AT02-07\r\n] 2006.201.05:52:07.48#ibcon#*before write, iclass 19, count 2 2006.201.05:52:07.48#ibcon#enter sib2, iclass 19, count 2 2006.201.05:52:07.48#ibcon#flushed, iclass 19, count 2 2006.201.05:52:07.48#ibcon#about to write, iclass 19, count 2 2006.201.05:52:07.48#ibcon#wrote, iclass 19, count 2 2006.201.05:52:07.48#ibcon#about to read 3, iclass 19, count 2 2006.201.05:52:07.51#ibcon#read 3, iclass 19, count 2 2006.201.05:52:07.51#ibcon#about to read 4, iclass 19, count 2 2006.201.05:52:07.51#ibcon#read 4, iclass 19, count 2 2006.201.05:52:07.51#ibcon#about to read 5, iclass 19, count 2 2006.201.05:52:07.51#ibcon#read 5, iclass 19, count 2 2006.201.05:52:07.51#ibcon#about to read 6, iclass 19, count 2 2006.201.05:52:07.51#ibcon#read 6, iclass 19, count 2 2006.201.05:52:07.51#ibcon#end of sib2, iclass 19, count 2 2006.201.05:52:07.51#ibcon#*after write, iclass 19, count 2 2006.201.05:52:07.51#ibcon#*before return 0, iclass 19, count 2 2006.201.05:52:07.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:07.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:07.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.05:52:07.51#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:07.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:07.63#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:07.63#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:07.63#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:52:07.63#ibcon#first serial, iclass 19, count 0 2006.201.05:52:07.63#ibcon#enter sib2, iclass 19, count 0 2006.201.05:52:07.63#ibcon#flushed, iclass 19, count 0 2006.201.05:52:07.63#ibcon#about to write, iclass 19, count 0 2006.201.05:52:07.63#ibcon#wrote, iclass 19, count 0 2006.201.05:52:07.63#ibcon#about to read 3, iclass 19, count 0 2006.201.05:52:07.65#ibcon#read 3, iclass 19, count 0 2006.201.05:52:07.65#ibcon#about to read 4, iclass 19, count 0 2006.201.05:52:07.65#ibcon#read 4, iclass 19, count 0 2006.201.05:52:07.65#ibcon#about to read 5, iclass 19, count 0 2006.201.05:52:07.65#ibcon#read 5, iclass 19, count 0 2006.201.05:52:07.65#ibcon#about to read 6, iclass 19, count 0 2006.201.05:52:07.65#ibcon#read 6, iclass 19, count 0 2006.201.05:52:07.65#ibcon#end of sib2, iclass 19, count 0 2006.201.05:52:07.65#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:52:07.65#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:52:07.65#ibcon#[25=USB\r\n] 2006.201.05:52:07.65#ibcon#*before write, iclass 19, count 0 2006.201.05:52:07.65#ibcon#enter sib2, iclass 19, count 0 2006.201.05:52:07.65#ibcon#flushed, iclass 19, count 0 2006.201.05:52:07.65#ibcon#about to write, iclass 19, count 0 2006.201.05:52:07.65#ibcon#wrote, iclass 19, count 0 2006.201.05:52:07.65#ibcon#about to read 3, iclass 19, count 0 2006.201.05:52:07.68#ibcon#read 3, iclass 19, count 0 2006.201.05:52:07.68#ibcon#about to read 4, iclass 19, count 0 2006.201.05:52:07.68#ibcon#read 4, iclass 19, count 0 2006.201.05:52:07.68#ibcon#about to read 5, iclass 19, count 0 2006.201.05:52:07.68#ibcon#read 5, iclass 19, count 0 2006.201.05:52:07.68#ibcon#about to read 6, iclass 19, count 0 2006.201.05:52:07.68#ibcon#read 6, iclass 19, count 0 2006.201.05:52:07.68#ibcon#end of sib2, iclass 19, count 0 2006.201.05:52:07.68#ibcon#*after write, iclass 19, count 0 2006.201.05:52:07.68#ibcon#*before return 0, iclass 19, count 0 2006.201.05:52:07.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:07.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:07.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:52:07.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:52:07.68$vck44/valo=3,564.99 2006.201.05:52:07.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.05:52:07.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.05:52:07.68#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:07.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:07.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:07.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:07.68#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:52:07.68#ibcon#first serial, iclass 21, count 0 2006.201.05:52:07.68#ibcon#enter sib2, iclass 21, count 0 2006.201.05:52:07.68#ibcon#flushed, iclass 21, count 0 2006.201.05:52:07.68#ibcon#about to write, iclass 21, count 0 2006.201.05:52:07.68#ibcon#wrote, iclass 21, count 0 2006.201.05:52:07.68#ibcon#about to read 3, iclass 21, count 0 2006.201.05:52:07.70#ibcon#read 3, iclass 21, count 0 2006.201.05:52:07.70#ibcon#about to read 4, iclass 21, count 0 2006.201.05:52:07.70#ibcon#read 4, iclass 21, count 0 2006.201.05:52:07.70#ibcon#about to read 5, iclass 21, count 0 2006.201.05:52:07.70#ibcon#read 5, iclass 21, count 0 2006.201.05:52:07.70#ibcon#about to read 6, iclass 21, count 0 2006.201.05:52:07.70#ibcon#read 6, iclass 21, count 0 2006.201.05:52:07.70#ibcon#end of sib2, iclass 21, count 0 2006.201.05:52:07.70#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:52:07.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:52:07.70#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.05:52:07.70#ibcon#*before write, iclass 21, count 0 2006.201.05:52:07.70#ibcon#enter sib2, iclass 21, count 0 2006.201.05:52:07.70#ibcon#flushed, iclass 21, count 0 2006.201.05:52:07.70#ibcon#about to write, iclass 21, count 0 2006.201.05:52:07.70#ibcon#wrote, iclass 21, count 0 2006.201.05:52:07.70#ibcon#about to read 3, iclass 21, count 0 2006.201.05:52:07.74#ibcon#read 3, iclass 21, count 0 2006.201.05:52:07.74#ibcon#about to read 4, iclass 21, count 0 2006.201.05:52:07.74#ibcon#read 4, iclass 21, count 0 2006.201.05:52:07.74#ibcon#about to read 5, iclass 21, count 0 2006.201.05:52:07.74#ibcon#read 5, iclass 21, count 0 2006.201.05:52:07.74#ibcon#about to read 6, iclass 21, count 0 2006.201.05:52:07.74#ibcon#read 6, iclass 21, count 0 2006.201.05:52:07.74#ibcon#end of sib2, iclass 21, count 0 2006.201.05:52:07.74#ibcon#*after write, iclass 21, count 0 2006.201.05:52:07.74#ibcon#*before return 0, iclass 21, count 0 2006.201.05:52:07.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:07.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:07.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:52:07.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:52:07.74$vck44/va=3,8 2006.201.05:52:07.74#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.05:52:07.74#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.05:52:07.74#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:07.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:07.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:07.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:07.80#ibcon#enter wrdev, iclass 23, count 2 2006.201.05:52:07.80#ibcon#first serial, iclass 23, count 2 2006.201.05:52:07.80#ibcon#enter sib2, iclass 23, count 2 2006.201.05:52:07.80#ibcon#flushed, iclass 23, count 2 2006.201.05:52:07.80#ibcon#about to write, iclass 23, count 2 2006.201.05:52:07.80#ibcon#wrote, iclass 23, count 2 2006.201.05:52:07.80#ibcon#about to read 3, iclass 23, count 2 2006.201.05:52:07.82#ibcon#read 3, iclass 23, count 2 2006.201.05:52:07.82#ibcon#about to read 4, iclass 23, count 2 2006.201.05:52:07.82#ibcon#read 4, iclass 23, count 2 2006.201.05:52:07.82#ibcon#about to read 5, iclass 23, count 2 2006.201.05:52:07.82#ibcon#read 5, iclass 23, count 2 2006.201.05:52:07.82#ibcon#about to read 6, iclass 23, count 2 2006.201.05:52:07.82#ibcon#read 6, iclass 23, count 2 2006.201.05:52:07.82#ibcon#end of sib2, iclass 23, count 2 2006.201.05:52:07.82#ibcon#*mode == 0, iclass 23, count 2 2006.201.05:52:07.82#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.05:52:07.82#ibcon#[25=AT03-08\r\n] 2006.201.05:52:07.82#ibcon#*before write, iclass 23, count 2 2006.201.05:52:07.82#ibcon#enter sib2, iclass 23, count 2 2006.201.05:52:07.82#ibcon#flushed, iclass 23, count 2 2006.201.05:52:07.82#ibcon#about to write, iclass 23, count 2 2006.201.05:52:07.82#ibcon#wrote, iclass 23, count 2 2006.201.05:52:07.82#ibcon#about to read 3, iclass 23, count 2 2006.201.05:52:07.85#ibcon#read 3, iclass 23, count 2 2006.201.05:52:07.85#ibcon#about to read 4, iclass 23, count 2 2006.201.05:52:07.85#ibcon#read 4, iclass 23, count 2 2006.201.05:52:07.85#ibcon#about to read 5, iclass 23, count 2 2006.201.05:52:07.85#ibcon#read 5, iclass 23, count 2 2006.201.05:52:07.85#ibcon#about to read 6, iclass 23, count 2 2006.201.05:52:07.85#ibcon#read 6, iclass 23, count 2 2006.201.05:52:07.85#ibcon#end of sib2, iclass 23, count 2 2006.201.05:52:07.85#ibcon#*after write, iclass 23, count 2 2006.201.05:52:07.85#ibcon#*before return 0, iclass 23, count 2 2006.201.05:52:07.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:07.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:07.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.05:52:07.85#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:07.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:07.97#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:07.97#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:07.97#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:52:07.97#ibcon#first serial, iclass 23, count 0 2006.201.05:52:07.97#ibcon#enter sib2, iclass 23, count 0 2006.201.05:52:07.97#ibcon#flushed, iclass 23, count 0 2006.201.05:52:07.97#ibcon#about to write, iclass 23, count 0 2006.201.05:52:07.97#ibcon#wrote, iclass 23, count 0 2006.201.05:52:07.97#ibcon#about to read 3, iclass 23, count 0 2006.201.05:52:07.99#ibcon#read 3, iclass 23, count 0 2006.201.05:52:07.99#ibcon#about to read 4, iclass 23, count 0 2006.201.05:52:07.99#ibcon#read 4, iclass 23, count 0 2006.201.05:52:07.99#ibcon#about to read 5, iclass 23, count 0 2006.201.05:52:07.99#ibcon#read 5, iclass 23, count 0 2006.201.05:52:07.99#ibcon#about to read 6, iclass 23, count 0 2006.201.05:52:07.99#ibcon#read 6, iclass 23, count 0 2006.201.05:52:07.99#ibcon#end of sib2, iclass 23, count 0 2006.201.05:52:07.99#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:52:07.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:52:07.99#ibcon#[25=USB\r\n] 2006.201.05:52:07.99#ibcon#*before write, iclass 23, count 0 2006.201.05:52:07.99#ibcon#enter sib2, iclass 23, count 0 2006.201.05:52:07.99#ibcon#flushed, iclass 23, count 0 2006.201.05:52:07.99#ibcon#about to write, iclass 23, count 0 2006.201.05:52:07.99#ibcon#wrote, iclass 23, count 0 2006.201.05:52:07.99#ibcon#about to read 3, iclass 23, count 0 2006.201.05:52:08.02#ibcon#read 3, iclass 23, count 0 2006.201.05:52:08.02#ibcon#about to read 4, iclass 23, count 0 2006.201.05:52:08.02#ibcon#read 4, iclass 23, count 0 2006.201.05:52:08.02#ibcon#about to read 5, iclass 23, count 0 2006.201.05:52:08.02#ibcon#read 5, iclass 23, count 0 2006.201.05:52:08.02#ibcon#about to read 6, iclass 23, count 0 2006.201.05:52:08.02#ibcon#read 6, iclass 23, count 0 2006.201.05:52:08.02#ibcon#end of sib2, iclass 23, count 0 2006.201.05:52:08.02#ibcon#*after write, iclass 23, count 0 2006.201.05:52:08.02#ibcon#*before return 0, iclass 23, count 0 2006.201.05:52:08.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:08.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:08.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:52:08.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:52:08.02$vck44/valo=4,624.99 2006.201.05:52:08.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.05:52:08.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.05:52:08.02#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:08.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:08.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:08.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:08.02#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:52:08.02#ibcon#first serial, iclass 25, count 0 2006.201.05:52:08.02#ibcon#enter sib2, iclass 25, count 0 2006.201.05:52:08.02#ibcon#flushed, iclass 25, count 0 2006.201.05:52:08.02#ibcon#about to write, iclass 25, count 0 2006.201.05:52:08.02#ibcon#wrote, iclass 25, count 0 2006.201.05:52:08.02#ibcon#about to read 3, iclass 25, count 0 2006.201.05:52:08.04#ibcon#read 3, iclass 25, count 0 2006.201.05:52:08.04#ibcon#about to read 4, iclass 25, count 0 2006.201.05:52:08.04#ibcon#read 4, iclass 25, count 0 2006.201.05:52:08.04#ibcon#about to read 5, iclass 25, count 0 2006.201.05:52:08.04#ibcon#read 5, iclass 25, count 0 2006.201.05:52:08.04#ibcon#about to read 6, iclass 25, count 0 2006.201.05:52:08.04#ibcon#read 6, iclass 25, count 0 2006.201.05:52:08.04#ibcon#end of sib2, iclass 25, count 0 2006.201.05:52:08.04#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:52:08.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:52:08.04#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.05:52:08.04#ibcon#*before write, iclass 25, count 0 2006.201.05:52:08.04#ibcon#enter sib2, iclass 25, count 0 2006.201.05:52:08.04#ibcon#flushed, iclass 25, count 0 2006.201.05:52:08.04#ibcon#about to write, iclass 25, count 0 2006.201.05:52:08.04#ibcon#wrote, iclass 25, count 0 2006.201.05:52:08.04#ibcon#about to read 3, iclass 25, count 0 2006.201.05:52:08.08#ibcon#read 3, iclass 25, count 0 2006.201.05:52:08.08#ibcon#about to read 4, iclass 25, count 0 2006.201.05:52:08.08#ibcon#read 4, iclass 25, count 0 2006.201.05:52:08.08#ibcon#about to read 5, iclass 25, count 0 2006.201.05:52:08.08#ibcon#read 5, iclass 25, count 0 2006.201.05:52:08.08#ibcon#about to read 6, iclass 25, count 0 2006.201.05:52:08.08#ibcon#read 6, iclass 25, count 0 2006.201.05:52:08.08#ibcon#end of sib2, iclass 25, count 0 2006.201.05:52:08.08#ibcon#*after write, iclass 25, count 0 2006.201.05:52:08.08#ibcon#*before return 0, iclass 25, count 0 2006.201.05:52:08.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:08.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:08.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:52:08.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:52:08.08$vck44/va=4,7 2006.201.05:52:08.08#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.05:52:08.08#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.05:52:08.08#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:08.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:08.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:08.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:08.14#ibcon#enter wrdev, iclass 27, count 2 2006.201.05:52:08.14#ibcon#first serial, iclass 27, count 2 2006.201.05:52:08.14#ibcon#enter sib2, iclass 27, count 2 2006.201.05:52:08.14#ibcon#flushed, iclass 27, count 2 2006.201.05:52:08.14#ibcon#about to write, iclass 27, count 2 2006.201.05:52:08.14#ibcon#wrote, iclass 27, count 2 2006.201.05:52:08.14#ibcon#about to read 3, iclass 27, count 2 2006.201.05:52:08.16#ibcon#read 3, iclass 27, count 2 2006.201.05:52:08.16#ibcon#about to read 4, iclass 27, count 2 2006.201.05:52:08.16#ibcon#read 4, iclass 27, count 2 2006.201.05:52:08.16#ibcon#about to read 5, iclass 27, count 2 2006.201.05:52:08.16#ibcon#read 5, iclass 27, count 2 2006.201.05:52:08.16#ibcon#about to read 6, iclass 27, count 2 2006.201.05:52:08.16#ibcon#read 6, iclass 27, count 2 2006.201.05:52:08.16#ibcon#end of sib2, iclass 27, count 2 2006.201.05:52:08.16#ibcon#*mode == 0, iclass 27, count 2 2006.201.05:52:08.16#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.05:52:08.16#ibcon#[25=AT04-07\r\n] 2006.201.05:52:08.16#ibcon#*before write, iclass 27, count 2 2006.201.05:52:08.16#ibcon#enter sib2, iclass 27, count 2 2006.201.05:52:08.16#ibcon#flushed, iclass 27, count 2 2006.201.05:52:08.16#ibcon#about to write, iclass 27, count 2 2006.201.05:52:08.16#ibcon#wrote, iclass 27, count 2 2006.201.05:52:08.16#ibcon#about to read 3, iclass 27, count 2 2006.201.05:52:08.19#ibcon#read 3, iclass 27, count 2 2006.201.05:52:08.19#ibcon#about to read 4, iclass 27, count 2 2006.201.05:52:08.19#ibcon#read 4, iclass 27, count 2 2006.201.05:52:08.19#ibcon#about to read 5, iclass 27, count 2 2006.201.05:52:08.19#ibcon#read 5, iclass 27, count 2 2006.201.05:52:08.19#ibcon#about to read 6, iclass 27, count 2 2006.201.05:52:08.19#ibcon#read 6, iclass 27, count 2 2006.201.05:52:08.19#ibcon#end of sib2, iclass 27, count 2 2006.201.05:52:08.19#ibcon#*after write, iclass 27, count 2 2006.201.05:52:08.19#ibcon#*before return 0, iclass 27, count 2 2006.201.05:52:08.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:08.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:08.19#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.05:52:08.19#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:08.19#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:08.31#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:08.31#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:08.31#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:52:08.31#ibcon#first serial, iclass 27, count 0 2006.201.05:52:08.31#ibcon#enter sib2, iclass 27, count 0 2006.201.05:52:08.31#ibcon#flushed, iclass 27, count 0 2006.201.05:52:08.31#ibcon#about to write, iclass 27, count 0 2006.201.05:52:08.31#ibcon#wrote, iclass 27, count 0 2006.201.05:52:08.31#ibcon#about to read 3, iclass 27, count 0 2006.201.05:52:08.33#ibcon#read 3, iclass 27, count 0 2006.201.05:52:08.33#ibcon#about to read 4, iclass 27, count 0 2006.201.05:52:08.33#ibcon#read 4, iclass 27, count 0 2006.201.05:52:08.33#ibcon#about to read 5, iclass 27, count 0 2006.201.05:52:08.33#ibcon#read 5, iclass 27, count 0 2006.201.05:52:08.33#ibcon#about to read 6, iclass 27, count 0 2006.201.05:52:08.33#ibcon#read 6, iclass 27, count 0 2006.201.05:52:08.33#ibcon#end of sib2, iclass 27, count 0 2006.201.05:52:08.33#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:52:08.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:52:08.33#ibcon#[25=USB\r\n] 2006.201.05:52:08.33#ibcon#*before write, iclass 27, count 0 2006.201.05:52:08.33#ibcon#enter sib2, iclass 27, count 0 2006.201.05:52:08.33#ibcon#flushed, iclass 27, count 0 2006.201.05:52:08.33#ibcon#about to write, iclass 27, count 0 2006.201.05:52:08.33#ibcon#wrote, iclass 27, count 0 2006.201.05:52:08.33#ibcon#about to read 3, iclass 27, count 0 2006.201.05:52:08.36#ibcon#read 3, iclass 27, count 0 2006.201.05:52:08.36#ibcon#about to read 4, iclass 27, count 0 2006.201.05:52:08.36#ibcon#read 4, iclass 27, count 0 2006.201.05:52:08.36#ibcon#about to read 5, iclass 27, count 0 2006.201.05:52:08.36#ibcon#read 5, iclass 27, count 0 2006.201.05:52:08.36#ibcon#about to read 6, iclass 27, count 0 2006.201.05:52:08.36#ibcon#read 6, iclass 27, count 0 2006.201.05:52:08.36#ibcon#end of sib2, iclass 27, count 0 2006.201.05:52:08.36#ibcon#*after write, iclass 27, count 0 2006.201.05:52:08.36#ibcon#*before return 0, iclass 27, count 0 2006.201.05:52:08.36#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:08.36#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:08.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:52:08.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:52:08.36$vck44/valo=5,734.99 2006.201.05:52:08.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:52:08.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:52:08.36#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:08.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:08.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:08.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:08.36#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:52:08.36#ibcon#first serial, iclass 29, count 0 2006.201.05:52:08.36#ibcon#enter sib2, iclass 29, count 0 2006.201.05:52:08.36#ibcon#flushed, iclass 29, count 0 2006.201.05:52:08.36#ibcon#about to write, iclass 29, count 0 2006.201.05:52:08.36#ibcon#wrote, iclass 29, count 0 2006.201.05:52:08.36#ibcon#about to read 3, iclass 29, count 0 2006.201.05:52:08.38#ibcon#read 3, iclass 29, count 0 2006.201.05:52:08.38#ibcon#about to read 4, iclass 29, count 0 2006.201.05:52:08.38#ibcon#read 4, iclass 29, count 0 2006.201.05:52:08.38#ibcon#about to read 5, iclass 29, count 0 2006.201.05:52:08.38#ibcon#read 5, iclass 29, count 0 2006.201.05:52:08.38#ibcon#about to read 6, iclass 29, count 0 2006.201.05:52:08.38#ibcon#read 6, iclass 29, count 0 2006.201.05:52:08.38#ibcon#end of sib2, iclass 29, count 0 2006.201.05:52:08.38#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:52:08.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:52:08.38#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.05:52:08.38#ibcon#*before write, iclass 29, count 0 2006.201.05:52:08.38#ibcon#enter sib2, iclass 29, count 0 2006.201.05:52:08.38#ibcon#flushed, iclass 29, count 0 2006.201.05:52:08.38#ibcon#about to write, iclass 29, count 0 2006.201.05:52:08.38#ibcon#wrote, iclass 29, count 0 2006.201.05:52:08.38#ibcon#about to read 3, iclass 29, count 0 2006.201.05:52:08.42#ibcon#read 3, iclass 29, count 0 2006.201.05:52:08.42#ibcon#about to read 4, iclass 29, count 0 2006.201.05:52:08.42#ibcon#read 4, iclass 29, count 0 2006.201.05:52:08.42#ibcon#about to read 5, iclass 29, count 0 2006.201.05:52:08.42#ibcon#read 5, iclass 29, count 0 2006.201.05:52:08.42#ibcon#about to read 6, iclass 29, count 0 2006.201.05:52:08.42#ibcon#read 6, iclass 29, count 0 2006.201.05:52:08.42#ibcon#end of sib2, iclass 29, count 0 2006.201.05:52:08.42#ibcon#*after write, iclass 29, count 0 2006.201.05:52:08.42#ibcon#*before return 0, iclass 29, count 0 2006.201.05:52:08.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:08.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:08.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:52:08.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:52:08.42$vck44/va=5,4 2006.201.05:52:08.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.05:52:08.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.05:52:08.42#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:08.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:08.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:08.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:08.48#ibcon#enter wrdev, iclass 31, count 2 2006.201.05:52:08.48#ibcon#first serial, iclass 31, count 2 2006.201.05:52:08.48#ibcon#enter sib2, iclass 31, count 2 2006.201.05:52:08.48#ibcon#flushed, iclass 31, count 2 2006.201.05:52:08.48#ibcon#about to write, iclass 31, count 2 2006.201.05:52:08.48#ibcon#wrote, iclass 31, count 2 2006.201.05:52:08.48#ibcon#about to read 3, iclass 31, count 2 2006.201.05:52:08.50#ibcon#read 3, iclass 31, count 2 2006.201.05:52:08.50#ibcon#about to read 4, iclass 31, count 2 2006.201.05:52:08.50#ibcon#read 4, iclass 31, count 2 2006.201.05:52:08.50#ibcon#about to read 5, iclass 31, count 2 2006.201.05:52:08.50#ibcon#read 5, iclass 31, count 2 2006.201.05:52:08.50#ibcon#about to read 6, iclass 31, count 2 2006.201.05:52:08.50#ibcon#read 6, iclass 31, count 2 2006.201.05:52:08.50#ibcon#end of sib2, iclass 31, count 2 2006.201.05:52:08.50#ibcon#*mode == 0, iclass 31, count 2 2006.201.05:52:08.50#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.05:52:08.50#ibcon#[25=AT05-04\r\n] 2006.201.05:52:08.50#ibcon#*before write, iclass 31, count 2 2006.201.05:52:08.50#ibcon#enter sib2, iclass 31, count 2 2006.201.05:52:08.50#ibcon#flushed, iclass 31, count 2 2006.201.05:52:08.50#ibcon#about to write, iclass 31, count 2 2006.201.05:52:08.50#ibcon#wrote, iclass 31, count 2 2006.201.05:52:08.50#ibcon#about to read 3, iclass 31, count 2 2006.201.05:52:08.53#ibcon#read 3, iclass 31, count 2 2006.201.05:52:08.53#ibcon#about to read 4, iclass 31, count 2 2006.201.05:52:08.53#ibcon#read 4, iclass 31, count 2 2006.201.05:52:08.53#ibcon#about to read 5, iclass 31, count 2 2006.201.05:52:08.53#ibcon#read 5, iclass 31, count 2 2006.201.05:52:08.53#ibcon#about to read 6, iclass 31, count 2 2006.201.05:52:08.53#ibcon#read 6, iclass 31, count 2 2006.201.05:52:08.53#ibcon#end of sib2, iclass 31, count 2 2006.201.05:52:08.53#ibcon#*after write, iclass 31, count 2 2006.201.05:52:08.53#ibcon#*before return 0, iclass 31, count 2 2006.201.05:52:08.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:08.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:08.53#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.05:52:08.53#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:08.53#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:08.65#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:08.65#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:08.65#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:52:08.65#ibcon#first serial, iclass 31, count 0 2006.201.05:52:08.65#ibcon#enter sib2, iclass 31, count 0 2006.201.05:52:08.65#ibcon#flushed, iclass 31, count 0 2006.201.05:52:08.65#ibcon#about to write, iclass 31, count 0 2006.201.05:52:08.65#ibcon#wrote, iclass 31, count 0 2006.201.05:52:08.65#ibcon#about to read 3, iclass 31, count 0 2006.201.05:52:08.67#ibcon#read 3, iclass 31, count 0 2006.201.05:52:08.67#ibcon#about to read 4, iclass 31, count 0 2006.201.05:52:08.67#ibcon#read 4, iclass 31, count 0 2006.201.05:52:08.67#ibcon#about to read 5, iclass 31, count 0 2006.201.05:52:08.67#ibcon#read 5, iclass 31, count 0 2006.201.05:52:08.67#ibcon#about to read 6, iclass 31, count 0 2006.201.05:52:08.67#ibcon#read 6, iclass 31, count 0 2006.201.05:52:08.67#ibcon#end of sib2, iclass 31, count 0 2006.201.05:52:08.67#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:52:08.67#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:52:08.67#ibcon#[25=USB\r\n] 2006.201.05:52:08.67#ibcon#*before write, iclass 31, count 0 2006.201.05:52:08.67#ibcon#enter sib2, iclass 31, count 0 2006.201.05:52:08.67#ibcon#flushed, iclass 31, count 0 2006.201.05:52:08.67#ibcon#about to write, iclass 31, count 0 2006.201.05:52:08.67#ibcon#wrote, iclass 31, count 0 2006.201.05:52:08.67#ibcon#about to read 3, iclass 31, count 0 2006.201.05:52:08.70#ibcon#read 3, iclass 31, count 0 2006.201.05:52:08.70#ibcon#about to read 4, iclass 31, count 0 2006.201.05:52:08.70#ibcon#read 4, iclass 31, count 0 2006.201.05:52:08.70#ibcon#about to read 5, iclass 31, count 0 2006.201.05:52:08.70#ibcon#read 5, iclass 31, count 0 2006.201.05:52:08.70#ibcon#about to read 6, iclass 31, count 0 2006.201.05:52:08.70#ibcon#read 6, iclass 31, count 0 2006.201.05:52:08.70#ibcon#end of sib2, iclass 31, count 0 2006.201.05:52:08.70#ibcon#*after write, iclass 31, count 0 2006.201.05:52:08.70#ibcon#*before return 0, iclass 31, count 0 2006.201.05:52:08.70#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:08.70#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:08.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:52:08.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:52:08.70$vck44/valo=6,814.99 2006.201.05:52:08.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.05:52:08.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.05:52:08.70#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:08.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:08.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:08.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:08.70#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:52:08.70#ibcon#first serial, iclass 33, count 0 2006.201.05:52:08.70#ibcon#enter sib2, iclass 33, count 0 2006.201.05:52:08.70#ibcon#flushed, iclass 33, count 0 2006.201.05:52:08.70#ibcon#about to write, iclass 33, count 0 2006.201.05:52:08.70#ibcon#wrote, iclass 33, count 0 2006.201.05:52:08.70#ibcon#about to read 3, iclass 33, count 0 2006.201.05:52:08.72#ibcon#read 3, iclass 33, count 0 2006.201.05:52:08.72#ibcon#about to read 4, iclass 33, count 0 2006.201.05:52:08.72#ibcon#read 4, iclass 33, count 0 2006.201.05:52:08.72#ibcon#about to read 5, iclass 33, count 0 2006.201.05:52:08.72#ibcon#read 5, iclass 33, count 0 2006.201.05:52:08.72#ibcon#about to read 6, iclass 33, count 0 2006.201.05:52:08.72#ibcon#read 6, iclass 33, count 0 2006.201.05:52:08.72#ibcon#end of sib2, iclass 33, count 0 2006.201.05:52:08.72#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:52:08.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:52:08.72#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.05:52:08.72#ibcon#*before write, iclass 33, count 0 2006.201.05:52:08.72#ibcon#enter sib2, iclass 33, count 0 2006.201.05:52:08.72#ibcon#flushed, iclass 33, count 0 2006.201.05:52:08.72#ibcon#about to write, iclass 33, count 0 2006.201.05:52:08.72#ibcon#wrote, iclass 33, count 0 2006.201.05:52:08.72#ibcon#about to read 3, iclass 33, count 0 2006.201.05:52:08.76#ibcon#read 3, iclass 33, count 0 2006.201.05:52:08.76#ibcon#about to read 4, iclass 33, count 0 2006.201.05:52:08.76#ibcon#read 4, iclass 33, count 0 2006.201.05:52:08.76#ibcon#about to read 5, iclass 33, count 0 2006.201.05:52:08.76#ibcon#read 5, iclass 33, count 0 2006.201.05:52:08.76#ibcon#about to read 6, iclass 33, count 0 2006.201.05:52:08.76#ibcon#read 6, iclass 33, count 0 2006.201.05:52:08.76#ibcon#end of sib2, iclass 33, count 0 2006.201.05:52:08.76#ibcon#*after write, iclass 33, count 0 2006.201.05:52:08.76#ibcon#*before return 0, iclass 33, count 0 2006.201.05:52:08.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:08.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:08.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:52:08.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:52:08.76$vck44/va=6,5 2006.201.05:52:08.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.05:52:08.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.05:52:08.76#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:08.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:08.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:08.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:08.82#ibcon#enter wrdev, iclass 35, count 2 2006.201.05:52:08.82#ibcon#first serial, iclass 35, count 2 2006.201.05:52:08.82#ibcon#enter sib2, iclass 35, count 2 2006.201.05:52:08.82#ibcon#flushed, iclass 35, count 2 2006.201.05:52:08.82#ibcon#about to write, iclass 35, count 2 2006.201.05:52:08.82#ibcon#wrote, iclass 35, count 2 2006.201.05:52:08.82#ibcon#about to read 3, iclass 35, count 2 2006.201.05:52:08.84#ibcon#read 3, iclass 35, count 2 2006.201.05:52:08.84#ibcon#about to read 4, iclass 35, count 2 2006.201.05:52:08.84#ibcon#read 4, iclass 35, count 2 2006.201.05:52:08.84#ibcon#about to read 5, iclass 35, count 2 2006.201.05:52:08.84#ibcon#read 5, iclass 35, count 2 2006.201.05:52:08.84#ibcon#about to read 6, iclass 35, count 2 2006.201.05:52:08.84#ibcon#read 6, iclass 35, count 2 2006.201.05:52:08.84#ibcon#end of sib2, iclass 35, count 2 2006.201.05:52:08.84#ibcon#*mode == 0, iclass 35, count 2 2006.201.05:52:08.84#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.05:52:08.84#ibcon#[25=AT06-05\r\n] 2006.201.05:52:08.84#ibcon#*before write, iclass 35, count 2 2006.201.05:52:08.84#ibcon#enter sib2, iclass 35, count 2 2006.201.05:52:08.84#ibcon#flushed, iclass 35, count 2 2006.201.05:52:08.84#ibcon#about to write, iclass 35, count 2 2006.201.05:52:08.84#ibcon#wrote, iclass 35, count 2 2006.201.05:52:08.84#ibcon#about to read 3, iclass 35, count 2 2006.201.05:52:08.87#ibcon#read 3, iclass 35, count 2 2006.201.05:52:08.87#ibcon#about to read 4, iclass 35, count 2 2006.201.05:52:08.87#ibcon#read 4, iclass 35, count 2 2006.201.05:52:08.87#ibcon#about to read 5, iclass 35, count 2 2006.201.05:52:08.87#ibcon#read 5, iclass 35, count 2 2006.201.05:52:08.87#ibcon#about to read 6, iclass 35, count 2 2006.201.05:52:08.87#ibcon#read 6, iclass 35, count 2 2006.201.05:52:08.87#ibcon#end of sib2, iclass 35, count 2 2006.201.05:52:08.87#ibcon#*after write, iclass 35, count 2 2006.201.05:52:08.87#ibcon#*before return 0, iclass 35, count 2 2006.201.05:52:08.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:08.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:08.87#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.05:52:08.87#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:08.87#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:08.99#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:08.99#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:08.99#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:52:08.99#ibcon#first serial, iclass 35, count 0 2006.201.05:52:08.99#ibcon#enter sib2, iclass 35, count 0 2006.201.05:52:08.99#ibcon#flushed, iclass 35, count 0 2006.201.05:52:08.99#ibcon#about to write, iclass 35, count 0 2006.201.05:52:08.99#ibcon#wrote, iclass 35, count 0 2006.201.05:52:08.99#ibcon#about to read 3, iclass 35, count 0 2006.201.05:52:09.01#ibcon#read 3, iclass 35, count 0 2006.201.05:52:09.01#ibcon#about to read 4, iclass 35, count 0 2006.201.05:52:09.01#ibcon#read 4, iclass 35, count 0 2006.201.05:52:09.01#ibcon#about to read 5, iclass 35, count 0 2006.201.05:52:09.01#ibcon#read 5, iclass 35, count 0 2006.201.05:52:09.01#ibcon#about to read 6, iclass 35, count 0 2006.201.05:52:09.01#ibcon#read 6, iclass 35, count 0 2006.201.05:52:09.01#ibcon#end of sib2, iclass 35, count 0 2006.201.05:52:09.01#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:52:09.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:52:09.01#ibcon#[25=USB\r\n] 2006.201.05:52:09.01#ibcon#*before write, iclass 35, count 0 2006.201.05:52:09.01#ibcon#enter sib2, iclass 35, count 0 2006.201.05:52:09.01#ibcon#flushed, iclass 35, count 0 2006.201.05:52:09.01#ibcon#about to write, iclass 35, count 0 2006.201.05:52:09.01#ibcon#wrote, iclass 35, count 0 2006.201.05:52:09.01#ibcon#about to read 3, iclass 35, count 0 2006.201.05:52:09.04#ibcon#read 3, iclass 35, count 0 2006.201.05:52:09.04#ibcon#about to read 4, iclass 35, count 0 2006.201.05:52:09.04#ibcon#read 4, iclass 35, count 0 2006.201.05:52:09.04#ibcon#about to read 5, iclass 35, count 0 2006.201.05:52:09.04#ibcon#read 5, iclass 35, count 0 2006.201.05:52:09.04#ibcon#about to read 6, iclass 35, count 0 2006.201.05:52:09.04#ibcon#read 6, iclass 35, count 0 2006.201.05:52:09.04#ibcon#end of sib2, iclass 35, count 0 2006.201.05:52:09.04#ibcon#*after write, iclass 35, count 0 2006.201.05:52:09.04#ibcon#*before return 0, iclass 35, count 0 2006.201.05:52:09.04#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:09.04#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:09.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:52:09.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:52:09.04$vck44/valo=7,864.99 2006.201.05:52:09.04#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.05:52:09.04#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.05:52:09.04#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:09.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:09.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:09.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:09.04#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:52:09.04#ibcon#first serial, iclass 37, count 0 2006.201.05:52:09.04#ibcon#enter sib2, iclass 37, count 0 2006.201.05:52:09.04#ibcon#flushed, iclass 37, count 0 2006.201.05:52:09.04#ibcon#about to write, iclass 37, count 0 2006.201.05:52:09.04#ibcon#wrote, iclass 37, count 0 2006.201.05:52:09.04#ibcon#about to read 3, iclass 37, count 0 2006.201.05:52:09.06#ibcon#read 3, iclass 37, count 0 2006.201.05:52:09.06#ibcon#about to read 4, iclass 37, count 0 2006.201.05:52:09.06#ibcon#read 4, iclass 37, count 0 2006.201.05:52:09.06#ibcon#about to read 5, iclass 37, count 0 2006.201.05:52:09.06#ibcon#read 5, iclass 37, count 0 2006.201.05:52:09.06#ibcon#about to read 6, iclass 37, count 0 2006.201.05:52:09.06#ibcon#read 6, iclass 37, count 0 2006.201.05:52:09.06#ibcon#end of sib2, iclass 37, count 0 2006.201.05:52:09.06#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:52:09.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:52:09.06#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.05:52:09.06#ibcon#*before write, iclass 37, count 0 2006.201.05:52:09.06#ibcon#enter sib2, iclass 37, count 0 2006.201.05:52:09.06#ibcon#flushed, iclass 37, count 0 2006.201.05:52:09.06#ibcon#about to write, iclass 37, count 0 2006.201.05:52:09.06#ibcon#wrote, iclass 37, count 0 2006.201.05:52:09.06#ibcon#about to read 3, iclass 37, count 0 2006.201.05:52:09.11#ibcon#read 3, iclass 37, count 0 2006.201.05:52:09.11#ibcon#about to read 4, iclass 37, count 0 2006.201.05:52:09.11#ibcon#read 4, iclass 37, count 0 2006.201.05:52:09.11#ibcon#about to read 5, iclass 37, count 0 2006.201.05:52:09.11#ibcon#read 5, iclass 37, count 0 2006.201.05:52:09.11#ibcon#about to read 6, iclass 37, count 0 2006.201.05:52:09.11#ibcon#read 6, iclass 37, count 0 2006.201.05:52:09.11#ibcon#end of sib2, iclass 37, count 0 2006.201.05:52:09.11#ibcon#*after write, iclass 37, count 0 2006.201.05:52:09.11#ibcon#*before return 0, iclass 37, count 0 2006.201.05:52:09.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:09.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:09.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:52:09.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:52:09.11$vck44/va=7,5 2006.201.05:52:09.11#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.05:52:09.11#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.05:52:09.11#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:09.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:09.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:09.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:09.16#ibcon#enter wrdev, iclass 39, count 2 2006.201.05:52:09.16#ibcon#first serial, iclass 39, count 2 2006.201.05:52:09.16#ibcon#enter sib2, iclass 39, count 2 2006.201.05:52:09.16#ibcon#flushed, iclass 39, count 2 2006.201.05:52:09.16#ibcon#about to write, iclass 39, count 2 2006.201.05:52:09.16#ibcon#wrote, iclass 39, count 2 2006.201.05:52:09.16#ibcon#about to read 3, iclass 39, count 2 2006.201.05:52:09.18#ibcon#read 3, iclass 39, count 2 2006.201.05:52:09.18#ibcon#about to read 4, iclass 39, count 2 2006.201.05:52:09.18#ibcon#read 4, iclass 39, count 2 2006.201.05:52:09.18#ibcon#about to read 5, iclass 39, count 2 2006.201.05:52:09.18#ibcon#read 5, iclass 39, count 2 2006.201.05:52:09.18#ibcon#about to read 6, iclass 39, count 2 2006.201.05:52:09.18#ibcon#read 6, iclass 39, count 2 2006.201.05:52:09.18#ibcon#end of sib2, iclass 39, count 2 2006.201.05:52:09.18#ibcon#*mode == 0, iclass 39, count 2 2006.201.05:52:09.18#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.05:52:09.18#ibcon#[25=AT07-05\r\n] 2006.201.05:52:09.18#ibcon#*before write, iclass 39, count 2 2006.201.05:52:09.18#ibcon#enter sib2, iclass 39, count 2 2006.201.05:52:09.18#ibcon#flushed, iclass 39, count 2 2006.201.05:52:09.18#ibcon#about to write, iclass 39, count 2 2006.201.05:52:09.18#ibcon#wrote, iclass 39, count 2 2006.201.05:52:09.18#ibcon#about to read 3, iclass 39, count 2 2006.201.05:52:09.21#ibcon#read 3, iclass 39, count 2 2006.201.05:52:09.21#ibcon#about to read 4, iclass 39, count 2 2006.201.05:52:09.21#ibcon#read 4, iclass 39, count 2 2006.201.05:52:09.21#ibcon#about to read 5, iclass 39, count 2 2006.201.05:52:09.21#ibcon#read 5, iclass 39, count 2 2006.201.05:52:09.21#ibcon#about to read 6, iclass 39, count 2 2006.201.05:52:09.21#ibcon#read 6, iclass 39, count 2 2006.201.05:52:09.21#ibcon#end of sib2, iclass 39, count 2 2006.201.05:52:09.21#ibcon#*after write, iclass 39, count 2 2006.201.05:52:09.21#ibcon#*before return 0, iclass 39, count 2 2006.201.05:52:09.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:09.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:09.21#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.05:52:09.21#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:09.21#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:09.33#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:09.33#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:09.33#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:52:09.33#ibcon#first serial, iclass 39, count 0 2006.201.05:52:09.33#ibcon#enter sib2, iclass 39, count 0 2006.201.05:52:09.33#ibcon#flushed, iclass 39, count 0 2006.201.05:52:09.33#ibcon#about to write, iclass 39, count 0 2006.201.05:52:09.33#ibcon#wrote, iclass 39, count 0 2006.201.05:52:09.33#ibcon#about to read 3, iclass 39, count 0 2006.201.05:52:09.35#ibcon#read 3, iclass 39, count 0 2006.201.05:52:09.35#ibcon#about to read 4, iclass 39, count 0 2006.201.05:52:09.35#ibcon#read 4, iclass 39, count 0 2006.201.05:52:09.35#ibcon#about to read 5, iclass 39, count 0 2006.201.05:52:09.35#ibcon#read 5, iclass 39, count 0 2006.201.05:52:09.35#ibcon#about to read 6, iclass 39, count 0 2006.201.05:52:09.35#ibcon#read 6, iclass 39, count 0 2006.201.05:52:09.35#ibcon#end of sib2, iclass 39, count 0 2006.201.05:52:09.35#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:52:09.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:52:09.35#ibcon#[25=USB\r\n] 2006.201.05:52:09.35#ibcon#*before write, iclass 39, count 0 2006.201.05:52:09.35#ibcon#enter sib2, iclass 39, count 0 2006.201.05:52:09.35#ibcon#flushed, iclass 39, count 0 2006.201.05:52:09.35#ibcon#about to write, iclass 39, count 0 2006.201.05:52:09.35#ibcon#wrote, iclass 39, count 0 2006.201.05:52:09.35#ibcon#about to read 3, iclass 39, count 0 2006.201.05:52:09.38#ibcon#read 3, iclass 39, count 0 2006.201.05:52:09.38#ibcon#about to read 4, iclass 39, count 0 2006.201.05:52:09.38#ibcon#read 4, iclass 39, count 0 2006.201.05:52:09.38#ibcon#about to read 5, iclass 39, count 0 2006.201.05:52:09.38#ibcon#read 5, iclass 39, count 0 2006.201.05:52:09.38#ibcon#about to read 6, iclass 39, count 0 2006.201.05:52:09.38#ibcon#read 6, iclass 39, count 0 2006.201.05:52:09.38#ibcon#end of sib2, iclass 39, count 0 2006.201.05:52:09.38#ibcon#*after write, iclass 39, count 0 2006.201.05:52:09.38#ibcon#*before return 0, iclass 39, count 0 2006.201.05:52:09.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:09.38#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:09.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:52:09.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:52:09.38$vck44/valo=8,884.99 2006.201.05:52:09.38#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.05:52:09.38#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.05:52:09.38#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:09.38#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:09.38#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:09.38#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:09.38#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:52:09.38#ibcon#first serial, iclass 2, count 0 2006.201.05:52:09.38#ibcon#enter sib2, iclass 2, count 0 2006.201.05:52:09.38#ibcon#flushed, iclass 2, count 0 2006.201.05:52:09.38#ibcon#about to write, iclass 2, count 0 2006.201.05:52:09.38#ibcon#wrote, iclass 2, count 0 2006.201.05:52:09.38#ibcon#about to read 3, iclass 2, count 0 2006.201.05:52:09.40#ibcon#read 3, iclass 2, count 0 2006.201.05:52:09.40#ibcon#about to read 4, iclass 2, count 0 2006.201.05:52:09.40#ibcon#read 4, iclass 2, count 0 2006.201.05:52:09.40#ibcon#about to read 5, iclass 2, count 0 2006.201.05:52:09.40#ibcon#read 5, iclass 2, count 0 2006.201.05:52:09.40#ibcon#about to read 6, iclass 2, count 0 2006.201.05:52:09.40#ibcon#read 6, iclass 2, count 0 2006.201.05:52:09.40#ibcon#end of sib2, iclass 2, count 0 2006.201.05:52:09.40#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:52:09.40#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:52:09.40#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.05:52:09.40#ibcon#*before write, iclass 2, count 0 2006.201.05:52:09.40#ibcon#enter sib2, iclass 2, count 0 2006.201.05:52:09.40#ibcon#flushed, iclass 2, count 0 2006.201.05:52:09.40#ibcon#about to write, iclass 2, count 0 2006.201.05:52:09.40#ibcon#wrote, iclass 2, count 0 2006.201.05:52:09.40#ibcon#about to read 3, iclass 2, count 0 2006.201.05:52:09.44#ibcon#read 3, iclass 2, count 0 2006.201.05:52:09.44#ibcon#about to read 4, iclass 2, count 0 2006.201.05:52:09.44#ibcon#read 4, iclass 2, count 0 2006.201.05:52:09.44#ibcon#about to read 5, iclass 2, count 0 2006.201.05:52:09.44#ibcon#read 5, iclass 2, count 0 2006.201.05:52:09.44#ibcon#about to read 6, iclass 2, count 0 2006.201.05:52:09.44#ibcon#read 6, iclass 2, count 0 2006.201.05:52:09.44#ibcon#end of sib2, iclass 2, count 0 2006.201.05:52:09.44#ibcon#*after write, iclass 2, count 0 2006.201.05:52:09.44#ibcon#*before return 0, iclass 2, count 0 2006.201.05:52:09.44#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:09.44#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:09.44#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:52:09.44#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:52:09.44$vck44/va=8,4 2006.201.05:52:09.44#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.05:52:09.44#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.05:52:09.44#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:09.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:52:09.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:52:09.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:52:09.50#ibcon#enter wrdev, iclass 5, count 2 2006.201.05:52:09.50#ibcon#first serial, iclass 5, count 2 2006.201.05:52:09.50#ibcon#enter sib2, iclass 5, count 2 2006.201.05:52:09.50#ibcon#flushed, iclass 5, count 2 2006.201.05:52:09.50#ibcon#about to write, iclass 5, count 2 2006.201.05:52:09.50#ibcon#wrote, iclass 5, count 2 2006.201.05:52:09.50#ibcon#about to read 3, iclass 5, count 2 2006.201.05:52:09.52#ibcon#read 3, iclass 5, count 2 2006.201.05:52:09.52#ibcon#about to read 4, iclass 5, count 2 2006.201.05:52:09.52#ibcon#read 4, iclass 5, count 2 2006.201.05:52:09.52#ibcon#about to read 5, iclass 5, count 2 2006.201.05:52:09.52#ibcon#read 5, iclass 5, count 2 2006.201.05:52:09.52#ibcon#about to read 6, iclass 5, count 2 2006.201.05:52:09.52#ibcon#read 6, iclass 5, count 2 2006.201.05:52:09.52#ibcon#end of sib2, iclass 5, count 2 2006.201.05:52:09.52#ibcon#*mode == 0, iclass 5, count 2 2006.201.05:52:09.52#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.05:52:09.52#ibcon#[25=AT08-04\r\n] 2006.201.05:52:09.52#ibcon#*before write, iclass 5, count 2 2006.201.05:52:09.52#ibcon#enter sib2, iclass 5, count 2 2006.201.05:52:09.52#ibcon#flushed, iclass 5, count 2 2006.201.05:52:09.52#ibcon#about to write, iclass 5, count 2 2006.201.05:52:09.52#ibcon#wrote, iclass 5, count 2 2006.201.05:52:09.52#ibcon#about to read 3, iclass 5, count 2 2006.201.05:52:09.55#ibcon#read 3, iclass 5, count 2 2006.201.05:52:09.55#ibcon#about to read 4, iclass 5, count 2 2006.201.05:52:09.55#ibcon#read 4, iclass 5, count 2 2006.201.05:52:09.55#ibcon#about to read 5, iclass 5, count 2 2006.201.05:52:09.55#ibcon#read 5, iclass 5, count 2 2006.201.05:52:09.55#ibcon#about to read 6, iclass 5, count 2 2006.201.05:52:09.55#ibcon#read 6, iclass 5, count 2 2006.201.05:52:09.55#ibcon#end of sib2, iclass 5, count 2 2006.201.05:52:09.55#ibcon#*after write, iclass 5, count 2 2006.201.05:52:09.55#ibcon#*before return 0, iclass 5, count 2 2006.201.05:52:09.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:52:09.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.05:52:09.55#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.05:52:09.55#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:09.55#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:52:09.67#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:52:09.67#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:52:09.67#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:52:09.67#ibcon#first serial, iclass 5, count 0 2006.201.05:52:09.67#ibcon#enter sib2, iclass 5, count 0 2006.201.05:52:09.67#ibcon#flushed, iclass 5, count 0 2006.201.05:52:09.67#ibcon#about to write, iclass 5, count 0 2006.201.05:52:09.67#ibcon#wrote, iclass 5, count 0 2006.201.05:52:09.67#ibcon#about to read 3, iclass 5, count 0 2006.201.05:52:09.69#ibcon#read 3, iclass 5, count 0 2006.201.05:52:09.69#ibcon#about to read 4, iclass 5, count 0 2006.201.05:52:09.69#ibcon#read 4, iclass 5, count 0 2006.201.05:52:09.69#ibcon#about to read 5, iclass 5, count 0 2006.201.05:52:09.69#ibcon#read 5, iclass 5, count 0 2006.201.05:52:09.69#ibcon#about to read 6, iclass 5, count 0 2006.201.05:52:09.69#ibcon#read 6, iclass 5, count 0 2006.201.05:52:09.69#ibcon#end of sib2, iclass 5, count 0 2006.201.05:52:09.69#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:52:09.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:52:09.69#ibcon#[25=USB\r\n] 2006.201.05:52:09.69#ibcon#*before write, iclass 5, count 0 2006.201.05:52:09.69#ibcon#enter sib2, iclass 5, count 0 2006.201.05:52:09.69#ibcon#flushed, iclass 5, count 0 2006.201.05:52:09.69#ibcon#about to write, iclass 5, count 0 2006.201.05:52:09.69#ibcon#wrote, iclass 5, count 0 2006.201.05:52:09.69#ibcon#about to read 3, iclass 5, count 0 2006.201.05:52:09.72#ibcon#read 3, iclass 5, count 0 2006.201.05:52:09.72#ibcon#about to read 4, iclass 5, count 0 2006.201.05:52:09.72#ibcon#read 4, iclass 5, count 0 2006.201.05:52:09.72#ibcon#about to read 5, iclass 5, count 0 2006.201.05:52:09.72#ibcon#read 5, iclass 5, count 0 2006.201.05:52:09.72#ibcon#about to read 6, iclass 5, count 0 2006.201.05:52:09.72#ibcon#read 6, iclass 5, count 0 2006.201.05:52:09.72#ibcon#end of sib2, iclass 5, count 0 2006.201.05:52:09.72#ibcon#*after write, iclass 5, count 0 2006.201.05:52:09.72#ibcon#*before return 0, iclass 5, count 0 2006.201.05:52:09.72#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:52:09.72#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.05:52:09.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:52:09.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:52:09.72$vck44/vblo=1,629.99 2006.201.05:52:09.72#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.05:52:09.72#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.05:52:09.72#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:09.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:52:09.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:52:09.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:52:09.72#ibcon#enter wrdev, iclass 7, count 0 2006.201.05:52:09.72#ibcon#first serial, iclass 7, count 0 2006.201.05:52:09.72#ibcon#enter sib2, iclass 7, count 0 2006.201.05:52:09.72#ibcon#flushed, iclass 7, count 0 2006.201.05:52:09.72#ibcon#about to write, iclass 7, count 0 2006.201.05:52:09.72#ibcon#wrote, iclass 7, count 0 2006.201.05:52:09.72#ibcon#about to read 3, iclass 7, count 0 2006.201.05:52:09.74#ibcon#read 3, iclass 7, count 0 2006.201.05:52:09.74#ibcon#about to read 4, iclass 7, count 0 2006.201.05:52:09.74#ibcon#read 4, iclass 7, count 0 2006.201.05:52:09.74#ibcon#about to read 5, iclass 7, count 0 2006.201.05:52:09.74#ibcon#read 5, iclass 7, count 0 2006.201.05:52:09.74#ibcon#about to read 6, iclass 7, count 0 2006.201.05:52:09.74#ibcon#read 6, iclass 7, count 0 2006.201.05:52:09.74#ibcon#end of sib2, iclass 7, count 0 2006.201.05:52:09.74#ibcon#*mode == 0, iclass 7, count 0 2006.201.05:52:09.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.05:52:09.74#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.05:52:09.74#ibcon#*before write, iclass 7, count 0 2006.201.05:52:09.74#ibcon#enter sib2, iclass 7, count 0 2006.201.05:52:09.74#ibcon#flushed, iclass 7, count 0 2006.201.05:52:09.74#ibcon#about to write, iclass 7, count 0 2006.201.05:52:09.74#ibcon#wrote, iclass 7, count 0 2006.201.05:52:09.74#ibcon#about to read 3, iclass 7, count 0 2006.201.05:52:09.78#ibcon#read 3, iclass 7, count 0 2006.201.05:52:09.78#ibcon#about to read 4, iclass 7, count 0 2006.201.05:52:09.78#ibcon#read 4, iclass 7, count 0 2006.201.05:52:09.78#ibcon#about to read 5, iclass 7, count 0 2006.201.05:52:09.78#ibcon#read 5, iclass 7, count 0 2006.201.05:52:09.78#ibcon#about to read 6, iclass 7, count 0 2006.201.05:52:09.78#ibcon#read 6, iclass 7, count 0 2006.201.05:52:09.78#ibcon#end of sib2, iclass 7, count 0 2006.201.05:52:09.78#ibcon#*after write, iclass 7, count 0 2006.201.05:52:09.78#ibcon#*before return 0, iclass 7, count 0 2006.201.05:52:09.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:52:09.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.05:52:09.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.05:52:09.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.05:52:09.78$vck44/vb=1,4 2006.201.05:52:09.78#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.05:52:09.78#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.05:52:09.78#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:09.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:52:09.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:52:09.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:52:09.78#ibcon#enter wrdev, iclass 11, count 2 2006.201.05:52:09.78#ibcon#first serial, iclass 11, count 2 2006.201.05:52:09.78#ibcon#enter sib2, iclass 11, count 2 2006.201.05:52:09.78#ibcon#flushed, iclass 11, count 2 2006.201.05:52:09.78#ibcon#about to write, iclass 11, count 2 2006.201.05:52:09.78#ibcon#wrote, iclass 11, count 2 2006.201.05:52:09.78#ibcon#about to read 3, iclass 11, count 2 2006.201.05:52:09.80#ibcon#read 3, iclass 11, count 2 2006.201.05:52:09.80#ibcon#about to read 4, iclass 11, count 2 2006.201.05:52:09.80#ibcon#read 4, iclass 11, count 2 2006.201.05:52:09.80#ibcon#about to read 5, iclass 11, count 2 2006.201.05:52:09.80#ibcon#read 5, iclass 11, count 2 2006.201.05:52:09.80#ibcon#about to read 6, iclass 11, count 2 2006.201.05:52:09.80#ibcon#read 6, iclass 11, count 2 2006.201.05:52:09.80#ibcon#end of sib2, iclass 11, count 2 2006.201.05:52:09.80#ibcon#*mode == 0, iclass 11, count 2 2006.201.05:52:09.80#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.05:52:09.80#ibcon#[27=AT01-04\r\n] 2006.201.05:52:09.80#ibcon#*before write, iclass 11, count 2 2006.201.05:52:09.80#ibcon#enter sib2, iclass 11, count 2 2006.201.05:52:09.80#ibcon#flushed, iclass 11, count 2 2006.201.05:52:09.80#ibcon#about to write, iclass 11, count 2 2006.201.05:52:09.80#ibcon#wrote, iclass 11, count 2 2006.201.05:52:09.80#ibcon#about to read 3, iclass 11, count 2 2006.201.05:52:09.83#ibcon#read 3, iclass 11, count 2 2006.201.05:52:09.83#ibcon#about to read 4, iclass 11, count 2 2006.201.05:52:09.83#ibcon#read 4, iclass 11, count 2 2006.201.05:52:09.83#ibcon#about to read 5, iclass 11, count 2 2006.201.05:52:09.83#ibcon#read 5, iclass 11, count 2 2006.201.05:52:09.83#ibcon#about to read 6, iclass 11, count 2 2006.201.05:52:09.83#ibcon#read 6, iclass 11, count 2 2006.201.05:52:09.83#ibcon#end of sib2, iclass 11, count 2 2006.201.05:52:09.83#ibcon#*after write, iclass 11, count 2 2006.201.05:52:09.83#ibcon#*before return 0, iclass 11, count 2 2006.201.05:52:09.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:52:09.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.05:52:09.83#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.05:52:09.83#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:09.83#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:52:09.95#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:52:09.95#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:52:09.95#ibcon#enter wrdev, iclass 11, count 0 2006.201.05:52:09.95#ibcon#first serial, iclass 11, count 0 2006.201.05:52:09.95#ibcon#enter sib2, iclass 11, count 0 2006.201.05:52:09.95#ibcon#flushed, iclass 11, count 0 2006.201.05:52:09.95#ibcon#about to write, iclass 11, count 0 2006.201.05:52:09.95#ibcon#wrote, iclass 11, count 0 2006.201.05:52:09.95#ibcon#about to read 3, iclass 11, count 0 2006.201.05:52:09.97#ibcon#read 3, iclass 11, count 0 2006.201.05:52:09.97#ibcon#about to read 4, iclass 11, count 0 2006.201.05:52:09.97#ibcon#read 4, iclass 11, count 0 2006.201.05:52:09.97#ibcon#about to read 5, iclass 11, count 0 2006.201.05:52:09.97#ibcon#read 5, iclass 11, count 0 2006.201.05:52:09.97#ibcon#about to read 6, iclass 11, count 0 2006.201.05:52:09.97#ibcon#read 6, iclass 11, count 0 2006.201.05:52:09.97#ibcon#end of sib2, iclass 11, count 0 2006.201.05:52:09.97#ibcon#*mode == 0, iclass 11, count 0 2006.201.05:52:09.97#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.05:52:09.97#ibcon#[27=USB\r\n] 2006.201.05:52:09.97#ibcon#*before write, iclass 11, count 0 2006.201.05:52:09.97#ibcon#enter sib2, iclass 11, count 0 2006.201.05:52:09.97#ibcon#flushed, iclass 11, count 0 2006.201.05:52:09.97#ibcon#about to write, iclass 11, count 0 2006.201.05:52:09.97#ibcon#wrote, iclass 11, count 0 2006.201.05:52:09.97#ibcon#about to read 3, iclass 11, count 0 2006.201.05:52:10.00#ibcon#read 3, iclass 11, count 0 2006.201.05:52:10.00#ibcon#about to read 4, iclass 11, count 0 2006.201.05:52:10.00#ibcon#read 4, iclass 11, count 0 2006.201.05:52:10.00#ibcon#about to read 5, iclass 11, count 0 2006.201.05:52:10.00#ibcon#read 5, iclass 11, count 0 2006.201.05:52:10.00#ibcon#about to read 6, iclass 11, count 0 2006.201.05:52:10.00#ibcon#read 6, iclass 11, count 0 2006.201.05:52:10.00#ibcon#end of sib2, iclass 11, count 0 2006.201.05:52:10.00#ibcon#*after write, iclass 11, count 0 2006.201.05:52:10.00#ibcon#*before return 0, iclass 11, count 0 2006.201.05:52:10.00#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:52:10.00#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.05:52:10.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.05:52:10.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.05:52:10.00$vck44/vblo=2,634.99 2006.201.05:52:10.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.05:52:10.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.05:52:10.00#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:10.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:10.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:10.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:10.00#ibcon#enter wrdev, iclass 13, count 0 2006.201.05:52:10.00#ibcon#first serial, iclass 13, count 0 2006.201.05:52:10.00#ibcon#enter sib2, iclass 13, count 0 2006.201.05:52:10.00#ibcon#flushed, iclass 13, count 0 2006.201.05:52:10.00#ibcon#about to write, iclass 13, count 0 2006.201.05:52:10.00#ibcon#wrote, iclass 13, count 0 2006.201.05:52:10.00#ibcon#about to read 3, iclass 13, count 0 2006.201.05:52:10.02#ibcon#read 3, iclass 13, count 0 2006.201.05:52:10.02#ibcon#about to read 4, iclass 13, count 0 2006.201.05:52:10.02#ibcon#read 4, iclass 13, count 0 2006.201.05:52:10.02#ibcon#about to read 5, iclass 13, count 0 2006.201.05:52:10.02#ibcon#read 5, iclass 13, count 0 2006.201.05:52:10.02#ibcon#about to read 6, iclass 13, count 0 2006.201.05:52:10.02#ibcon#read 6, iclass 13, count 0 2006.201.05:52:10.02#ibcon#end of sib2, iclass 13, count 0 2006.201.05:52:10.02#ibcon#*mode == 0, iclass 13, count 0 2006.201.05:52:10.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.05:52:10.02#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.05:52:10.02#ibcon#*before write, iclass 13, count 0 2006.201.05:52:10.02#ibcon#enter sib2, iclass 13, count 0 2006.201.05:52:10.02#ibcon#flushed, iclass 13, count 0 2006.201.05:52:10.02#ibcon#about to write, iclass 13, count 0 2006.201.05:52:10.02#ibcon#wrote, iclass 13, count 0 2006.201.05:52:10.02#ibcon#about to read 3, iclass 13, count 0 2006.201.05:52:10.06#ibcon#read 3, iclass 13, count 0 2006.201.05:52:10.06#ibcon#about to read 4, iclass 13, count 0 2006.201.05:52:10.06#ibcon#read 4, iclass 13, count 0 2006.201.05:52:10.06#ibcon#about to read 5, iclass 13, count 0 2006.201.05:52:10.06#ibcon#read 5, iclass 13, count 0 2006.201.05:52:10.06#ibcon#about to read 6, iclass 13, count 0 2006.201.05:52:10.06#ibcon#read 6, iclass 13, count 0 2006.201.05:52:10.06#ibcon#end of sib2, iclass 13, count 0 2006.201.05:52:10.06#ibcon#*after write, iclass 13, count 0 2006.201.05:52:10.06#ibcon#*before return 0, iclass 13, count 0 2006.201.05:52:10.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:10.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.05:52:10.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.05:52:10.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.05:52:10.06$vck44/vb=2,5 2006.201.05:52:10.06#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.05:52:10.06#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.05:52:10.06#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:10.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:10.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:10.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:10.12#ibcon#enter wrdev, iclass 15, count 2 2006.201.05:52:10.12#ibcon#first serial, iclass 15, count 2 2006.201.05:52:10.12#ibcon#enter sib2, iclass 15, count 2 2006.201.05:52:10.12#ibcon#flushed, iclass 15, count 2 2006.201.05:52:10.12#ibcon#about to write, iclass 15, count 2 2006.201.05:52:10.12#ibcon#wrote, iclass 15, count 2 2006.201.05:52:10.12#ibcon#about to read 3, iclass 15, count 2 2006.201.05:52:10.14#ibcon#read 3, iclass 15, count 2 2006.201.05:52:10.14#ibcon#about to read 4, iclass 15, count 2 2006.201.05:52:10.14#ibcon#read 4, iclass 15, count 2 2006.201.05:52:10.14#ibcon#about to read 5, iclass 15, count 2 2006.201.05:52:10.14#ibcon#read 5, iclass 15, count 2 2006.201.05:52:10.14#ibcon#about to read 6, iclass 15, count 2 2006.201.05:52:10.14#ibcon#read 6, iclass 15, count 2 2006.201.05:52:10.14#ibcon#end of sib2, iclass 15, count 2 2006.201.05:52:10.14#ibcon#*mode == 0, iclass 15, count 2 2006.201.05:52:10.14#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.05:52:10.14#ibcon#[27=AT02-05\r\n] 2006.201.05:52:10.14#ibcon#*before write, iclass 15, count 2 2006.201.05:52:10.14#ibcon#enter sib2, iclass 15, count 2 2006.201.05:52:10.14#ibcon#flushed, iclass 15, count 2 2006.201.05:52:10.14#ibcon#about to write, iclass 15, count 2 2006.201.05:52:10.14#ibcon#wrote, iclass 15, count 2 2006.201.05:52:10.14#ibcon#about to read 3, iclass 15, count 2 2006.201.05:52:10.17#ibcon#read 3, iclass 15, count 2 2006.201.05:52:10.17#ibcon#about to read 4, iclass 15, count 2 2006.201.05:52:10.17#ibcon#read 4, iclass 15, count 2 2006.201.05:52:10.17#ibcon#about to read 5, iclass 15, count 2 2006.201.05:52:10.17#ibcon#read 5, iclass 15, count 2 2006.201.05:52:10.17#ibcon#about to read 6, iclass 15, count 2 2006.201.05:52:10.17#ibcon#read 6, iclass 15, count 2 2006.201.05:52:10.17#ibcon#end of sib2, iclass 15, count 2 2006.201.05:52:10.17#ibcon#*after write, iclass 15, count 2 2006.201.05:52:10.17#ibcon#*before return 0, iclass 15, count 2 2006.201.05:52:10.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:10.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.05:52:10.17#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.05:52:10.17#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:10.17#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:10.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:10.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:10.29#ibcon#enter wrdev, iclass 15, count 0 2006.201.05:52:10.29#ibcon#first serial, iclass 15, count 0 2006.201.05:52:10.29#ibcon#enter sib2, iclass 15, count 0 2006.201.05:52:10.29#ibcon#flushed, iclass 15, count 0 2006.201.05:52:10.29#ibcon#about to write, iclass 15, count 0 2006.201.05:52:10.29#ibcon#wrote, iclass 15, count 0 2006.201.05:52:10.29#ibcon#about to read 3, iclass 15, count 0 2006.201.05:52:10.31#ibcon#read 3, iclass 15, count 0 2006.201.05:52:10.31#ibcon#about to read 4, iclass 15, count 0 2006.201.05:52:10.31#ibcon#read 4, iclass 15, count 0 2006.201.05:52:10.31#ibcon#about to read 5, iclass 15, count 0 2006.201.05:52:10.31#ibcon#read 5, iclass 15, count 0 2006.201.05:52:10.31#ibcon#about to read 6, iclass 15, count 0 2006.201.05:52:10.31#ibcon#read 6, iclass 15, count 0 2006.201.05:52:10.31#ibcon#end of sib2, iclass 15, count 0 2006.201.05:52:10.31#ibcon#*mode == 0, iclass 15, count 0 2006.201.05:52:10.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.05:52:10.31#ibcon#[27=USB\r\n] 2006.201.05:52:10.31#ibcon#*before write, iclass 15, count 0 2006.201.05:52:10.31#ibcon#enter sib2, iclass 15, count 0 2006.201.05:52:10.31#ibcon#flushed, iclass 15, count 0 2006.201.05:52:10.31#ibcon#about to write, iclass 15, count 0 2006.201.05:52:10.31#ibcon#wrote, iclass 15, count 0 2006.201.05:52:10.31#ibcon#about to read 3, iclass 15, count 0 2006.201.05:52:10.34#ibcon#read 3, iclass 15, count 0 2006.201.05:52:10.34#ibcon#about to read 4, iclass 15, count 0 2006.201.05:52:10.34#ibcon#read 4, iclass 15, count 0 2006.201.05:52:10.34#ibcon#about to read 5, iclass 15, count 0 2006.201.05:52:10.34#ibcon#read 5, iclass 15, count 0 2006.201.05:52:10.34#ibcon#about to read 6, iclass 15, count 0 2006.201.05:52:10.34#ibcon#read 6, iclass 15, count 0 2006.201.05:52:10.34#ibcon#end of sib2, iclass 15, count 0 2006.201.05:52:10.34#ibcon#*after write, iclass 15, count 0 2006.201.05:52:10.34#ibcon#*before return 0, iclass 15, count 0 2006.201.05:52:10.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:10.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.05:52:10.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.05:52:10.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.05:52:10.34$vck44/vblo=3,649.99 2006.201.05:52:10.34#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.05:52:10.34#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.05:52:10.34#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:10.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:10.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:10.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:10.34#ibcon#enter wrdev, iclass 17, count 0 2006.201.05:52:10.34#ibcon#first serial, iclass 17, count 0 2006.201.05:52:10.34#ibcon#enter sib2, iclass 17, count 0 2006.201.05:52:10.34#ibcon#flushed, iclass 17, count 0 2006.201.05:52:10.34#ibcon#about to write, iclass 17, count 0 2006.201.05:52:10.34#ibcon#wrote, iclass 17, count 0 2006.201.05:52:10.34#ibcon#about to read 3, iclass 17, count 0 2006.201.05:52:10.36#ibcon#read 3, iclass 17, count 0 2006.201.05:52:10.36#ibcon#about to read 4, iclass 17, count 0 2006.201.05:52:10.36#ibcon#read 4, iclass 17, count 0 2006.201.05:52:10.36#ibcon#about to read 5, iclass 17, count 0 2006.201.05:52:10.36#ibcon#read 5, iclass 17, count 0 2006.201.05:52:10.36#ibcon#about to read 6, iclass 17, count 0 2006.201.05:52:10.36#ibcon#read 6, iclass 17, count 0 2006.201.05:52:10.36#ibcon#end of sib2, iclass 17, count 0 2006.201.05:52:10.36#ibcon#*mode == 0, iclass 17, count 0 2006.201.05:52:10.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.05:52:10.36#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.05:52:10.36#ibcon#*before write, iclass 17, count 0 2006.201.05:52:10.36#ibcon#enter sib2, iclass 17, count 0 2006.201.05:52:10.36#ibcon#flushed, iclass 17, count 0 2006.201.05:52:10.36#ibcon#about to write, iclass 17, count 0 2006.201.05:52:10.36#ibcon#wrote, iclass 17, count 0 2006.201.05:52:10.36#ibcon#about to read 3, iclass 17, count 0 2006.201.05:52:10.40#ibcon#read 3, iclass 17, count 0 2006.201.05:52:10.40#ibcon#about to read 4, iclass 17, count 0 2006.201.05:52:10.40#ibcon#read 4, iclass 17, count 0 2006.201.05:52:10.40#ibcon#about to read 5, iclass 17, count 0 2006.201.05:52:10.40#ibcon#read 5, iclass 17, count 0 2006.201.05:52:10.40#ibcon#about to read 6, iclass 17, count 0 2006.201.05:52:10.40#ibcon#read 6, iclass 17, count 0 2006.201.05:52:10.40#ibcon#end of sib2, iclass 17, count 0 2006.201.05:52:10.40#ibcon#*after write, iclass 17, count 0 2006.201.05:52:10.40#ibcon#*before return 0, iclass 17, count 0 2006.201.05:52:10.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:10.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.05:52:10.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.05:52:10.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.05:52:10.40$vck44/vb=3,4 2006.201.05:52:10.40#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.05:52:10.40#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.05:52:10.40#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:10.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:10.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:10.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:10.46#ibcon#enter wrdev, iclass 19, count 2 2006.201.05:52:10.46#ibcon#first serial, iclass 19, count 2 2006.201.05:52:10.46#ibcon#enter sib2, iclass 19, count 2 2006.201.05:52:10.46#ibcon#flushed, iclass 19, count 2 2006.201.05:52:10.46#ibcon#about to write, iclass 19, count 2 2006.201.05:52:10.46#ibcon#wrote, iclass 19, count 2 2006.201.05:52:10.46#ibcon#about to read 3, iclass 19, count 2 2006.201.05:52:10.49#ibcon#read 3, iclass 19, count 2 2006.201.05:52:10.49#ibcon#about to read 4, iclass 19, count 2 2006.201.05:52:10.49#ibcon#read 4, iclass 19, count 2 2006.201.05:52:10.49#ibcon#about to read 5, iclass 19, count 2 2006.201.05:52:10.49#ibcon#read 5, iclass 19, count 2 2006.201.05:52:10.49#ibcon#about to read 6, iclass 19, count 2 2006.201.05:52:10.49#ibcon#read 6, iclass 19, count 2 2006.201.05:52:10.49#ibcon#end of sib2, iclass 19, count 2 2006.201.05:52:10.49#ibcon#*mode == 0, iclass 19, count 2 2006.201.05:52:10.49#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.05:52:10.49#ibcon#[27=AT03-04\r\n] 2006.201.05:52:10.49#ibcon#*before write, iclass 19, count 2 2006.201.05:52:10.49#ibcon#enter sib2, iclass 19, count 2 2006.201.05:52:10.49#ibcon#flushed, iclass 19, count 2 2006.201.05:52:10.49#ibcon#about to write, iclass 19, count 2 2006.201.05:52:10.49#ibcon#wrote, iclass 19, count 2 2006.201.05:52:10.49#ibcon#about to read 3, iclass 19, count 2 2006.201.05:52:10.53#ibcon#read 3, iclass 19, count 2 2006.201.05:52:10.53#ibcon#about to read 4, iclass 19, count 2 2006.201.05:52:10.53#ibcon#read 4, iclass 19, count 2 2006.201.05:52:10.53#ibcon#about to read 5, iclass 19, count 2 2006.201.05:52:10.53#ibcon#read 5, iclass 19, count 2 2006.201.05:52:10.53#ibcon#about to read 6, iclass 19, count 2 2006.201.05:52:10.53#ibcon#read 6, iclass 19, count 2 2006.201.05:52:10.53#ibcon#end of sib2, iclass 19, count 2 2006.201.05:52:10.53#ibcon#*after write, iclass 19, count 2 2006.201.05:52:10.53#ibcon#*before return 0, iclass 19, count 2 2006.201.05:52:10.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:10.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.05:52:10.53#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.05:52:10.53#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:10.53#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:10.65#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:10.65#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:10.65#ibcon#enter wrdev, iclass 19, count 0 2006.201.05:52:10.65#ibcon#first serial, iclass 19, count 0 2006.201.05:52:10.65#ibcon#enter sib2, iclass 19, count 0 2006.201.05:52:10.65#ibcon#flushed, iclass 19, count 0 2006.201.05:52:10.65#ibcon#about to write, iclass 19, count 0 2006.201.05:52:10.65#ibcon#wrote, iclass 19, count 0 2006.201.05:52:10.65#ibcon#about to read 3, iclass 19, count 0 2006.201.05:52:10.67#ibcon#read 3, iclass 19, count 0 2006.201.05:52:10.67#ibcon#about to read 4, iclass 19, count 0 2006.201.05:52:10.67#ibcon#read 4, iclass 19, count 0 2006.201.05:52:10.67#ibcon#about to read 5, iclass 19, count 0 2006.201.05:52:10.67#ibcon#read 5, iclass 19, count 0 2006.201.05:52:10.67#ibcon#about to read 6, iclass 19, count 0 2006.201.05:52:10.67#ibcon#read 6, iclass 19, count 0 2006.201.05:52:10.67#ibcon#end of sib2, iclass 19, count 0 2006.201.05:52:10.67#ibcon#*mode == 0, iclass 19, count 0 2006.201.05:52:10.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.05:52:10.67#ibcon#[27=USB\r\n] 2006.201.05:52:10.67#ibcon#*before write, iclass 19, count 0 2006.201.05:52:10.67#ibcon#enter sib2, iclass 19, count 0 2006.201.05:52:10.67#ibcon#flushed, iclass 19, count 0 2006.201.05:52:10.67#ibcon#about to write, iclass 19, count 0 2006.201.05:52:10.67#ibcon#wrote, iclass 19, count 0 2006.201.05:52:10.67#ibcon#about to read 3, iclass 19, count 0 2006.201.05:52:10.70#ibcon#read 3, iclass 19, count 0 2006.201.05:52:10.70#ibcon#about to read 4, iclass 19, count 0 2006.201.05:52:10.70#ibcon#read 4, iclass 19, count 0 2006.201.05:52:10.70#ibcon#about to read 5, iclass 19, count 0 2006.201.05:52:10.70#ibcon#read 5, iclass 19, count 0 2006.201.05:52:10.70#ibcon#about to read 6, iclass 19, count 0 2006.201.05:52:10.70#ibcon#read 6, iclass 19, count 0 2006.201.05:52:10.70#ibcon#end of sib2, iclass 19, count 0 2006.201.05:52:10.70#ibcon#*after write, iclass 19, count 0 2006.201.05:52:10.70#ibcon#*before return 0, iclass 19, count 0 2006.201.05:52:10.70#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:10.70#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.05:52:10.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.05:52:10.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.05:52:10.70$vck44/vblo=4,679.99 2006.201.05:52:10.70#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.05:52:10.70#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.05:52:10.70#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:10.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:10.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:10.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:10.70#ibcon#enter wrdev, iclass 21, count 0 2006.201.05:52:10.70#ibcon#first serial, iclass 21, count 0 2006.201.05:52:10.70#ibcon#enter sib2, iclass 21, count 0 2006.201.05:52:10.70#ibcon#flushed, iclass 21, count 0 2006.201.05:52:10.70#ibcon#about to write, iclass 21, count 0 2006.201.05:52:10.70#ibcon#wrote, iclass 21, count 0 2006.201.05:52:10.70#ibcon#about to read 3, iclass 21, count 0 2006.201.05:52:10.72#ibcon#read 3, iclass 21, count 0 2006.201.05:52:10.72#ibcon#about to read 4, iclass 21, count 0 2006.201.05:52:10.72#ibcon#read 4, iclass 21, count 0 2006.201.05:52:10.72#ibcon#about to read 5, iclass 21, count 0 2006.201.05:52:10.72#ibcon#read 5, iclass 21, count 0 2006.201.05:52:10.72#ibcon#about to read 6, iclass 21, count 0 2006.201.05:52:10.72#ibcon#read 6, iclass 21, count 0 2006.201.05:52:10.72#ibcon#end of sib2, iclass 21, count 0 2006.201.05:52:10.72#ibcon#*mode == 0, iclass 21, count 0 2006.201.05:52:10.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.05:52:10.72#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.05:52:10.72#ibcon#*before write, iclass 21, count 0 2006.201.05:52:10.72#ibcon#enter sib2, iclass 21, count 0 2006.201.05:52:10.72#ibcon#flushed, iclass 21, count 0 2006.201.05:52:10.72#ibcon#about to write, iclass 21, count 0 2006.201.05:52:10.72#ibcon#wrote, iclass 21, count 0 2006.201.05:52:10.72#ibcon#about to read 3, iclass 21, count 0 2006.201.05:52:10.76#ibcon#read 3, iclass 21, count 0 2006.201.05:52:10.76#ibcon#about to read 4, iclass 21, count 0 2006.201.05:52:10.76#ibcon#read 4, iclass 21, count 0 2006.201.05:52:10.76#ibcon#about to read 5, iclass 21, count 0 2006.201.05:52:10.76#ibcon#read 5, iclass 21, count 0 2006.201.05:52:10.76#ibcon#about to read 6, iclass 21, count 0 2006.201.05:52:10.76#ibcon#read 6, iclass 21, count 0 2006.201.05:52:10.76#ibcon#end of sib2, iclass 21, count 0 2006.201.05:52:10.76#ibcon#*after write, iclass 21, count 0 2006.201.05:52:10.76#ibcon#*before return 0, iclass 21, count 0 2006.201.05:52:10.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:10.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.05:52:10.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.05:52:10.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.05:52:10.76$vck44/vb=4,5 2006.201.05:52:10.76#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.05:52:10.76#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.05:52:10.76#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:10.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:10.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:10.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:10.82#ibcon#enter wrdev, iclass 23, count 2 2006.201.05:52:10.82#ibcon#first serial, iclass 23, count 2 2006.201.05:52:10.82#ibcon#enter sib2, iclass 23, count 2 2006.201.05:52:10.82#ibcon#flushed, iclass 23, count 2 2006.201.05:52:10.82#ibcon#about to write, iclass 23, count 2 2006.201.05:52:10.82#ibcon#wrote, iclass 23, count 2 2006.201.05:52:10.82#ibcon#about to read 3, iclass 23, count 2 2006.201.05:52:10.84#ibcon#read 3, iclass 23, count 2 2006.201.05:52:10.84#ibcon#about to read 4, iclass 23, count 2 2006.201.05:52:10.84#ibcon#read 4, iclass 23, count 2 2006.201.05:52:10.84#ibcon#about to read 5, iclass 23, count 2 2006.201.05:52:10.84#ibcon#read 5, iclass 23, count 2 2006.201.05:52:10.84#ibcon#about to read 6, iclass 23, count 2 2006.201.05:52:10.84#ibcon#read 6, iclass 23, count 2 2006.201.05:52:10.84#ibcon#end of sib2, iclass 23, count 2 2006.201.05:52:10.84#ibcon#*mode == 0, iclass 23, count 2 2006.201.05:52:10.84#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.05:52:10.84#ibcon#[27=AT04-05\r\n] 2006.201.05:52:10.84#ibcon#*before write, iclass 23, count 2 2006.201.05:52:10.84#ibcon#enter sib2, iclass 23, count 2 2006.201.05:52:10.84#ibcon#flushed, iclass 23, count 2 2006.201.05:52:10.84#ibcon#about to write, iclass 23, count 2 2006.201.05:52:10.84#ibcon#wrote, iclass 23, count 2 2006.201.05:52:10.84#ibcon#about to read 3, iclass 23, count 2 2006.201.05:52:10.87#ibcon#read 3, iclass 23, count 2 2006.201.05:52:10.87#ibcon#about to read 4, iclass 23, count 2 2006.201.05:52:10.87#ibcon#read 4, iclass 23, count 2 2006.201.05:52:10.87#ibcon#about to read 5, iclass 23, count 2 2006.201.05:52:10.87#ibcon#read 5, iclass 23, count 2 2006.201.05:52:10.87#ibcon#about to read 6, iclass 23, count 2 2006.201.05:52:10.87#ibcon#read 6, iclass 23, count 2 2006.201.05:52:10.87#ibcon#end of sib2, iclass 23, count 2 2006.201.05:52:10.87#ibcon#*after write, iclass 23, count 2 2006.201.05:52:10.87#ibcon#*before return 0, iclass 23, count 2 2006.201.05:52:10.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:10.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.05:52:10.87#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.05:52:10.87#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:10.87#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:10.99#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:10.99#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:10.99#ibcon#enter wrdev, iclass 23, count 0 2006.201.05:52:10.99#ibcon#first serial, iclass 23, count 0 2006.201.05:52:10.99#ibcon#enter sib2, iclass 23, count 0 2006.201.05:52:10.99#ibcon#flushed, iclass 23, count 0 2006.201.05:52:10.99#ibcon#about to write, iclass 23, count 0 2006.201.05:52:10.99#ibcon#wrote, iclass 23, count 0 2006.201.05:52:10.99#ibcon#about to read 3, iclass 23, count 0 2006.201.05:52:11.01#ibcon#read 3, iclass 23, count 0 2006.201.05:52:11.01#ibcon#about to read 4, iclass 23, count 0 2006.201.05:52:11.01#ibcon#read 4, iclass 23, count 0 2006.201.05:52:11.01#ibcon#about to read 5, iclass 23, count 0 2006.201.05:52:11.01#ibcon#read 5, iclass 23, count 0 2006.201.05:52:11.01#ibcon#about to read 6, iclass 23, count 0 2006.201.05:52:11.01#ibcon#read 6, iclass 23, count 0 2006.201.05:52:11.01#ibcon#end of sib2, iclass 23, count 0 2006.201.05:52:11.01#ibcon#*mode == 0, iclass 23, count 0 2006.201.05:52:11.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.05:52:11.01#ibcon#[27=USB\r\n] 2006.201.05:52:11.01#ibcon#*before write, iclass 23, count 0 2006.201.05:52:11.01#ibcon#enter sib2, iclass 23, count 0 2006.201.05:52:11.01#ibcon#flushed, iclass 23, count 0 2006.201.05:52:11.01#ibcon#about to write, iclass 23, count 0 2006.201.05:52:11.01#ibcon#wrote, iclass 23, count 0 2006.201.05:52:11.01#ibcon#about to read 3, iclass 23, count 0 2006.201.05:52:11.04#ibcon#read 3, iclass 23, count 0 2006.201.05:52:11.04#ibcon#about to read 4, iclass 23, count 0 2006.201.05:52:11.04#ibcon#read 4, iclass 23, count 0 2006.201.05:52:11.04#ibcon#about to read 5, iclass 23, count 0 2006.201.05:52:11.04#ibcon#read 5, iclass 23, count 0 2006.201.05:52:11.04#ibcon#about to read 6, iclass 23, count 0 2006.201.05:52:11.04#ibcon#read 6, iclass 23, count 0 2006.201.05:52:11.04#ibcon#end of sib2, iclass 23, count 0 2006.201.05:52:11.04#ibcon#*after write, iclass 23, count 0 2006.201.05:52:11.04#ibcon#*before return 0, iclass 23, count 0 2006.201.05:52:11.04#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:11.04#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.05:52:11.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.05:52:11.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.05:52:11.04$vck44/vblo=5,709.99 2006.201.05:52:11.04#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.05:52:11.04#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.05:52:11.04#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:11.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:11.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:11.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:11.04#ibcon#enter wrdev, iclass 25, count 0 2006.201.05:52:11.04#ibcon#first serial, iclass 25, count 0 2006.201.05:52:11.04#ibcon#enter sib2, iclass 25, count 0 2006.201.05:52:11.04#ibcon#flushed, iclass 25, count 0 2006.201.05:52:11.04#ibcon#about to write, iclass 25, count 0 2006.201.05:52:11.04#ibcon#wrote, iclass 25, count 0 2006.201.05:52:11.04#ibcon#about to read 3, iclass 25, count 0 2006.201.05:52:11.06#ibcon#read 3, iclass 25, count 0 2006.201.05:52:11.06#ibcon#about to read 4, iclass 25, count 0 2006.201.05:52:11.06#ibcon#read 4, iclass 25, count 0 2006.201.05:52:11.06#ibcon#about to read 5, iclass 25, count 0 2006.201.05:52:11.06#ibcon#read 5, iclass 25, count 0 2006.201.05:52:11.06#ibcon#about to read 6, iclass 25, count 0 2006.201.05:52:11.06#ibcon#read 6, iclass 25, count 0 2006.201.05:52:11.06#ibcon#end of sib2, iclass 25, count 0 2006.201.05:52:11.06#ibcon#*mode == 0, iclass 25, count 0 2006.201.05:52:11.06#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.05:52:11.06#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.05:52:11.06#ibcon#*before write, iclass 25, count 0 2006.201.05:52:11.06#ibcon#enter sib2, iclass 25, count 0 2006.201.05:52:11.06#ibcon#flushed, iclass 25, count 0 2006.201.05:52:11.06#ibcon#about to write, iclass 25, count 0 2006.201.05:52:11.06#ibcon#wrote, iclass 25, count 0 2006.201.05:52:11.06#ibcon#about to read 3, iclass 25, count 0 2006.201.05:52:11.10#ibcon#read 3, iclass 25, count 0 2006.201.05:52:11.10#ibcon#about to read 4, iclass 25, count 0 2006.201.05:52:11.10#ibcon#read 4, iclass 25, count 0 2006.201.05:52:11.10#ibcon#about to read 5, iclass 25, count 0 2006.201.05:52:11.10#ibcon#read 5, iclass 25, count 0 2006.201.05:52:11.10#ibcon#about to read 6, iclass 25, count 0 2006.201.05:52:11.10#ibcon#read 6, iclass 25, count 0 2006.201.05:52:11.10#ibcon#end of sib2, iclass 25, count 0 2006.201.05:52:11.10#ibcon#*after write, iclass 25, count 0 2006.201.05:52:11.10#ibcon#*before return 0, iclass 25, count 0 2006.201.05:52:11.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:11.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.05:52:11.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.05:52:11.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.05:52:11.10$vck44/vb=5,4 2006.201.05:52:11.10#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.05:52:11.10#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.05:52:11.10#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:11.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:11.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:11.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:11.16#ibcon#enter wrdev, iclass 27, count 2 2006.201.05:52:11.16#ibcon#first serial, iclass 27, count 2 2006.201.05:52:11.16#ibcon#enter sib2, iclass 27, count 2 2006.201.05:52:11.16#ibcon#flushed, iclass 27, count 2 2006.201.05:52:11.16#ibcon#about to write, iclass 27, count 2 2006.201.05:52:11.16#ibcon#wrote, iclass 27, count 2 2006.201.05:52:11.16#ibcon#about to read 3, iclass 27, count 2 2006.201.05:52:11.18#ibcon#read 3, iclass 27, count 2 2006.201.05:52:11.18#ibcon#about to read 4, iclass 27, count 2 2006.201.05:52:11.18#ibcon#read 4, iclass 27, count 2 2006.201.05:52:11.18#ibcon#about to read 5, iclass 27, count 2 2006.201.05:52:11.18#ibcon#read 5, iclass 27, count 2 2006.201.05:52:11.18#ibcon#about to read 6, iclass 27, count 2 2006.201.05:52:11.18#ibcon#read 6, iclass 27, count 2 2006.201.05:52:11.18#ibcon#end of sib2, iclass 27, count 2 2006.201.05:52:11.18#ibcon#*mode == 0, iclass 27, count 2 2006.201.05:52:11.18#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.05:52:11.18#ibcon#[27=AT05-04\r\n] 2006.201.05:52:11.18#ibcon#*before write, iclass 27, count 2 2006.201.05:52:11.18#ibcon#enter sib2, iclass 27, count 2 2006.201.05:52:11.18#ibcon#flushed, iclass 27, count 2 2006.201.05:52:11.18#ibcon#about to write, iclass 27, count 2 2006.201.05:52:11.18#ibcon#wrote, iclass 27, count 2 2006.201.05:52:11.18#ibcon#about to read 3, iclass 27, count 2 2006.201.05:52:11.21#ibcon#read 3, iclass 27, count 2 2006.201.05:52:11.21#ibcon#about to read 4, iclass 27, count 2 2006.201.05:52:11.21#ibcon#read 4, iclass 27, count 2 2006.201.05:52:11.21#ibcon#about to read 5, iclass 27, count 2 2006.201.05:52:11.21#ibcon#read 5, iclass 27, count 2 2006.201.05:52:11.21#ibcon#about to read 6, iclass 27, count 2 2006.201.05:52:11.21#ibcon#read 6, iclass 27, count 2 2006.201.05:52:11.21#ibcon#end of sib2, iclass 27, count 2 2006.201.05:52:11.21#ibcon#*after write, iclass 27, count 2 2006.201.05:52:11.21#ibcon#*before return 0, iclass 27, count 2 2006.201.05:52:11.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:11.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.05:52:11.21#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.05:52:11.21#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:11.21#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:11.33#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:11.33#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:11.33#ibcon#enter wrdev, iclass 27, count 0 2006.201.05:52:11.33#ibcon#first serial, iclass 27, count 0 2006.201.05:52:11.33#ibcon#enter sib2, iclass 27, count 0 2006.201.05:52:11.33#ibcon#flushed, iclass 27, count 0 2006.201.05:52:11.33#ibcon#about to write, iclass 27, count 0 2006.201.05:52:11.33#ibcon#wrote, iclass 27, count 0 2006.201.05:52:11.33#ibcon#about to read 3, iclass 27, count 0 2006.201.05:52:11.35#ibcon#read 3, iclass 27, count 0 2006.201.05:52:11.35#ibcon#about to read 4, iclass 27, count 0 2006.201.05:52:11.35#ibcon#read 4, iclass 27, count 0 2006.201.05:52:11.35#ibcon#about to read 5, iclass 27, count 0 2006.201.05:52:11.35#ibcon#read 5, iclass 27, count 0 2006.201.05:52:11.35#ibcon#about to read 6, iclass 27, count 0 2006.201.05:52:11.35#ibcon#read 6, iclass 27, count 0 2006.201.05:52:11.35#ibcon#end of sib2, iclass 27, count 0 2006.201.05:52:11.35#ibcon#*mode == 0, iclass 27, count 0 2006.201.05:52:11.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.05:52:11.35#ibcon#[27=USB\r\n] 2006.201.05:52:11.35#ibcon#*before write, iclass 27, count 0 2006.201.05:52:11.35#ibcon#enter sib2, iclass 27, count 0 2006.201.05:52:11.35#ibcon#flushed, iclass 27, count 0 2006.201.05:52:11.35#ibcon#about to write, iclass 27, count 0 2006.201.05:52:11.35#ibcon#wrote, iclass 27, count 0 2006.201.05:52:11.35#ibcon#about to read 3, iclass 27, count 0 2006.201.05:52:11.38#ibcon#read 3, iclass 27, count 0 2006.201.05:52:11.38#ibcon#about to read 4, iclass 27, count 0 2006.201.05:52:11.38#ibcon#read 4, iclass 27, count 0 2006.201.05:52:11.38#ibcon#about to read 5, iclass 27, count 0 2006.201.05:52:11.38#ibcon#read 5, iclass 27, count 0 2006.201.05:52:11.38#ibcon#about to read 6, iclass 27, count 0 2006.201.05:52:11.38#ibcon#read 6, iclass 27, count 0 2006.201.05:52:11.38#ibcon#end of sib2, iclass 27, count 0 2006.201.05:52:11.38#ibcon#*after write, iclass 27, count 0 2006.201.05:52:11.38#ibcon#*before return 0, iclass 27, count 0 2006.201.05:52:11.38#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:11.38#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.05:52:11.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.05:52:11.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.05:52:11.38$vck44/vblo=6,719.99 2006.201.05:52:11.38#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.05:52:11.38#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.05:52:11.38#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:11.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:11.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:11.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:11.38#ibcon#enter wrdev, iclass 29, count 0 2006.201.05:52:11.38#ibcon#first serial, iclass 29, count 0 2006.201.05:52:11.38#ibcon#enter sib2, iclass 29, count 0 2006.201.05:52:11.38#ibcon#flushed, iclass 29, count 0 2006.201.05:52:11.38#ibcon#about to write, iclass 29, count 0 2006.201.05:52:11.38#ibcon#wrote, iclass 29, count 0 2006.201.05:52:11.38#ibcon#about to read 3, iclass 29, count 0 2006.201.05:52:11.40#ibcon#read 3, iclass 29, count 0 2006.201.05:52:11.40#ibcon#about to read 4, iclass 29, count 0 2006.201.05:52:11.40#ibcon#read 4, iclass 29, count 0 2006.201.05:52:11.40#ibcon#about to read 5, iclass 29, count 0 2006.201.05:52:11.40#ibcon#read 5, iclass 29, count 0 2006.201.05:52:11.40#ibcon#about to read 6, iclass 29, count 0 2006.201.05:52:11.40#ibcon#read 6, iclass 29, count 0 2006.201.05:52:11.40#ibcon#end of sib2, iclass 29, count 0 2006.201.05:52:11.40#ibcon#*mode == 0, iclass 29, count 0 2006.201.05:52:11.40#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.05:52:11.40#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.05:52:11.40#ibcon#*before write, iclass 29, count 0 2006.201.05:52:11.40#ibcon#enter sib2, iclass 29, count 0 2006.201.05:52:11.40#ibcon#flushed, iclass 29, count 0 2006.201.05:52:11.40#ibcon#about to write, iclass 29, count 0 2006.201.05:52:11.40#ibcon#wrote, iclass 29, count 0 2006.201.05:52:11.40#ibcon#about to read 3, iclass 29, count 0 2006.201.05:52:11.44#ibcon#read 3, iclass 29, count 0 2006.201.05:52:11.44#ibcon#about to read 4, iclass 29, count 0 2006.201.05:52:11.44#ibcon#read 4, iclass 29, count 0 2006.201.05:52:11.44#ibcon#about to read 5, iclass 29, count 0 2006.201.05:52:11.44#ibcon#read 5, iclass 29, count 0 2006.201.05:52:11.44#ibcon#about to read 6, iclass 29, count 0 2006.201.05:52:11.44#ibcon#read 6, iclass 29, count 0 2006.201.05:52:11.44#ibcon#end of sib2, iclass 29, count 0 2006.201.05:52:11.44#ibcon#*after write, iclass 29, count 0 2006.201.05:52:11.44#ibcon#*before return 0, iclass 29, count 0 2006.201.05:52:11.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:11.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.05:52:11.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.05:52:11.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.05:52:11.44$vck44/vb=6,4 2006.201.05:52:11.44#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.05:52:11.44#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.05:52:11.44#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:11.44#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:11.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:11.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:11.50#ibcon#enter wrdev, iclass 31, count 2 2006.201.05:52:11.50#ibcon#first serial, iclass 31, count 2 2006.201.05:52:11.50#ibcon#enter sib2, iclass 31, count 2 2006.201.05:52:11.50#ibcon#flushed, iclass 31, count 2 2006.201.05:52:11.50#ibcon#about to write, iclass 31, count 2 2006.201.05:52:11.50#ibcon#wrote, iclass 31, count 2 2006.201.05:52:11.50#ibcon#about to read 3, iclass 31, count 2 2006.201.05:52:11.52#ibcon#read 3, iclass 31, count 2 2006.201.05:52:11.52#ibcon#about to read 4, iclass 31, count 2 2006.201.05:52:11.52#ibcon#read 4, iclass 31, count 2 2006.201.05:52:11.52#ibcon#about to read 5, iclass 31, count 2 2006.201.05:52:11.52#ibcon#read 5, iclass 31, count 2 2006.201.05:52:11.52#ibcon#about to read 6, iclass 31, count 2 2006.201.05:52:11.52#ibcon#read 6, iclass 31, count 2 2006.201.05:52:11.52#ibcon#end of sib2, iclass 31, count 2 2006.201.05:52:11.52#ibcon#*mode == 0, iclass 31, count 2 2006.201.05:52:11.52#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.05:52:11.52#ibcon#[27=AT06-04\r\n] 2006.201.05:52:11.52#ibcon#*before write, iclass 31, count 2 2006.201.05:52:11.52#ibcon#enter sib2, iclass 31, count 2 2006.201.05:52:11.52#ibcon#flushed, iclass 31, count 2 2006.201.05:52:11.52#ibcon#about to write, iclass 31, count 2 2006.201.05:52:11.52#ibcon#wrote, iclass 31, count 2 2006.201.05:52:11.52#ibcon#about to read 3, iclass 31, count 2 2006.201.05:52:11.55#ibcon#read 3, iclass 31, count 2 2006.201.05:52:11.55#ibcon#about to read 4, iclass 31, count 2 2006.201.05:52:11.55#ibcon#read 4, iclass 31, count 2 2006.201.05:52:11.55#ibcon#about to read 5, iclass 31, count 2 2006.201.05:52:11.55#ibcon#read 5, iclass 31, count 2 2006.201.05:52:11.55#ibcon#about to read 6, iclass 31, count 2 2006.201.05:52:11.55#ibcon#read 6, iclass 31, count 2 2006.201.05:52:11.55#ibcon#end of sib2, iclass 31, count 2 2006.201.05:52:11.55#ibcon#*after write, iclass 31, count 2 2006.201.05:52:11.55#ibcon#*before return 0, iclass 31, count 2 2006.201.05:52:11.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:11.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.05:52:11.55#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.05:52:11.55#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:11.55#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:11.67#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:11.67#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:11.67#ibcon#enter wrdev, iclass 31, count 0 2006.201.05:52:11.67#ibcon#first serial, iclass 31, count 0 2006.201.05:52:11.67#ibcon#enter sib2, iclass 31, count 0 2006.201.05:52:11.67#ibcon#flushed, iclass 31, count 0 2006.201.05:52:11.67#ibcon#about to write, iclass 31, count 0 2006.201.05:52:11.67#ibcon#wrote, iclass 31, count 0 2006.201.05:52:11.67#ibcon#about to read 3, iclass 31, count 0 2006.201.05:52:11.69#ibcon#read 3, iclass 31, count 0 2006.201.05:52:11.69#ibcon#about to read 4, iclass 31, count 0 2006.201.05:52:11.69#ibcon#read 4, iclass 31, count 0 2006.201.05:52:11.69#ibcon#about to read 5, iclass 31, count 0 2006.201.05:52:11.69#ibcon#read 5, iclass 31, count 0 2006.201.05:52:11.69#ibcon#about to read 6, iclass 31, count 0 2006.201.05:52:11.69#ibcon#read 6, iclass 31, count 0 2006.201.05:52:11.69#ibcon#end of sib2, iclass 31, count 0 2006.201.05:52:11.69#ibcon#*mode == 0, iclass 31, count 0 2006.201.05:52:11.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.05:52:11.69#ibcon#[27=USB\r\n] 2006.201.05:52:11.69#ibcon#*before write, iclass 31, count 0 2006.201.05:52:11.69#ibcon#enter sib2, iclass 31, count 0 2006.201.05:52:11.69#ibcon#flushed, iclass 31, count 0 2006.201.05:52:11.69#ibcon#about to write, iclass 31, count 0 2006.201.05:52:11.69#ibcon#wrote, iclass 31, count 0 2006.201.05:52:11.69#ibcon#about to read 3, iclass 31, count 0 2006.201.05:52:11.72#ibcon#read 3, iclass 31, count 0 2006.201.05:52:11.72#ibcon#about to read 4, iclass 31, count 0 2006.201.05:52:11.72#ibcon#read 4, iclass 31, count 0 2006.201.05:52:11.72#ibcon#about to read 5, iclass 31, count 0 2006.201.05:52:11.72#ibcon#read 5, iclass 31, count 0 2006.201.05:52:11.72#ibcon#about to read 6, iclass 31, count 0 2006.201.05:52:11.72#ibcon#read 6, iclass 31, count 0 2006.201.05:52:11.72#ibcon#end of sib2, iclass 31, count 0 2006.201.05:52:11.72#ibcon#*after write, iclass 31, count 0 2006.201.05:52:11.72#ibcon#*before return 0, iclass 31, count 0 2006.201.05:52:11.72#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:11.72#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.05:52:11.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.05:52:11.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.05:52:11.72$vck44/vblo=7,734.99 2006.201.05:52:11.72#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.05:52:11.72#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.05:52:11.72#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:11.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:11.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:11.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:11.72#ibcon#enter wrdev, iclass 33, count 0 2006.201.05:52:11.72#ibcon#first serial, iclass 33, count 0 2006.201.05:52:11.72#ibcon#enter sib2, iclass 33, count 0 2006.201.05:52:11.72#ibcon#flushed, iclass 33, count 0 2006.201.05:52:11.72#ibcon#about to write, iclass 33, count 0 2006.201.05:52:11.72#ibcon#wrote, iclass 33, count 0 2006.201.05:52:11.72#ibcon#about to read 3, iclass 33, count 0 2006.201.05:52:11.74#ibcon#read 3, iclass 33, count 0 2006.201.05:52:11.74#ibcon#about to read 4, iclass 33, count 0 2006.201.05:52:11.74#ibcon#read 4, iclass 33, count 0 2006.201.05:52:11.74#ibcon#about to read 5, iclass 33, count 0 2006.201.05:52:11.74#ibcon#read 5, iclass 33, count 0 2006.201.05:52:11.74#ibcon#about to read 6, iclass 33, count 0 2006.201.05:52:11.74#ibcon#read 6, iclass 33, count 0 2006.201.05:52:11.74#ibcon#end of sib2, iclass 33, count 0 2006.201.05:52:11.74#ibcon#*mode == 0, iclass 33, count 0 2006.201.05:52:11.74#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.05:52:11.74#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.05:52:11.74#ibcon#*before write, iclass 33, count 0 2006.201.05:52:11.74#ibcon#enter sib2, iclass 33, count 0 2006.201.05:52:11.74#ibcon#flushed, iclass 33, count 0 2006.201.05:52:11.74#ibcon#about to write, iclass 33, count 0 2006.201.05:52:11.74#ibcon#wrote, iclass 33, count 0 2006.201.05:52:11.74#ibcon#about to read 3, iclass 33, count 0 2006.201.05:52:11.78#ibcon#read 3, iclass 33, count 0 2006.201.05:52:11.78#ibcon#about to read 4, iclass 33, count 0 2006.201.05:52:11.78#ibcon#read 4, iclass 33, count 0 2006.201.05:52:11.78#ibcon#about to read 5, iclass 33, count 0 2006.201.05:52:11.78#ibcon#read 5, iclass 33, count 0 2006.201.05:52:11.78#ibcon#about to read 6, iclass 33, count 0 2006.201.05:52:11.78#ibcon#read 6, iclass 33, count 0 2006.201.05:52:11.78#ibcon#end of sib2, iclass 33, count 0 2006.201.05:52:11.78#ibcon#*after write, iclass 33, count 0 2006.201.05:52:11.78#ibcon#*before return 0, iclass 33, count 0 2006.201.05:52:11.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:11.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.05:52:11.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.05:52:11.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.05:52:11.78$vck44/vb=7,4 2006.201.05:52:11.78#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.05:52:11.78#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.05:52:11.78#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:11.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:11.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:11.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:11.84#ibcon#enter wrdev, iclass 35, count 2 2006.201.05:52:11.84#ibcon#first serial, iclass 35, count 2 2006.201.05:52:11.84#ibcon#enter sib2, iclass 35, count 2 2006.201.05:52:11.84#ibcon#flushed, iclass 35, count 2 2006.201.05:52:11.84#ibcon#about to write, iclass 35, count 2 2006.201.05:52:11.84#ibcon#wrote, iclass 35, count 2 2006.201.05:52:11.84#ibcon#about to read 3, iclass 35, count 2 2006.201.05:52:11.86#ibcon#read 3, iclass 35, count 2 2006.201.05:52:11.86#ibcon#about to read 4, iclass 35, count 2 2006.201.05:52:11.86#ibcon#read 4, iclass 35, count 2 2006.201.05:52:11.86#ibcon#about to read 5, iclass 35, count 2 2006.201.05:52:11.86#ibcon#read 5, iclass 35, count 2 2006.201.05:52:11.86#ibcon#about to read 6, iclass 35, count 2 2006.201.05:52:11.86#ibcon#read 6, iclass 35, count 2 2006.201.05:52:11.86#ibcon#end of sib2, iclass 35, count 2 2006.201.05:52:11.86#ibcon#*mode == 0, iclass 35, count 2 2006.201.05:52:11.86#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.05:52:11.86#ibcon#[27=AT07-04\r\n] 2006.201.05:52:11.86#ibcon#*before write, iclass 35, count 2 2006.201.05:52:11.86#ibcon#enter sib2, iclass 35, count 2 2006.201.05:52:11.86#ibcon#flushed, iclass 35, count 2 2006.201.05:52:11.86#ibcon#about to write, iclass 35, count 2 2006.201.05:52:11.86#ibcon#wrote, iclass 35, count 2 2006.201.05:52:11.86#ibcon#about to read 3, iclass 35, count 2 2006.201.05:52:11.91#ibcon#read 3, iclass 35, count 2 2006.201.05:52:11.91#ibcon#about to read 4, iclass 35, count 2 2006.201.05:52:11.91#ibcon#read 4, iclass 35, count 2 2006.201.05:52:11.91#ibcon#about to read 5, iclass 35, count 2 2006.201.05:52:11.91#ibcon#read 5, iclass 35, count 2 2006.201.05:52:11.91#ibcon#about to read 6, iclass 35, count 2 2006.201.05:52:11.91#ibcon#read 6, iclass 35, count 2 2006.201.05:52:11.91#ibcon#end of sib2, iclass 35, count 2 2006.201.05:52:11.91#ibcon#*after write, iclass 35, count 2 2006.201.05:52:11.91#ibcon#*before return 0, iclass 35, count 2 2006.201.05:52:11.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:11.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.05:52:11.91#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.05:52:11.91#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:11.91#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:12.03#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:12.03#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:12.03#ibcon#enter wrdev, iclass 35, count 0 2006.201.05:52:12.03#ibcon#first serial, iclass 35, count 0 2006.201.05:52:12.03#ibcon#enter sib2, iclass 35, count 0 2006.201.05:52:12.03#ibcon#flushed, iclass 35, count 0 2006.201.05:52:12.03#ibcon#about to write, iclass 35, count 0 2006.201.05:52:12.03#ibcon#wrote, iclass 35, count 0 2006.201.05:52:12.03#ibcon#about to read 3, iclass 35, count 0 2006.201.05:52:12.05#ibcon#read 3, iclass 35, count 0 2006.201.05:52:12.05#ibcon#about to read 4, iclass 35, count 0 2006.201.05:52:12.05#ibcon#read 4, iclass 35, count 0 2006.201.05:52:12.05#ibcon#about to read 5, iclass 35, count 0 2006.201.05:52:12.05#ibcon#read 5, iclass 35, count 0 2006.201.05:52:12.05#ibcon#about to read 6, iclass 35, count 0 2006.201.05:52:12.05#ibcon#read 6, iclass 35, count 0 2006.201.05:52:12.05#ibcon#end of sib2, iclass 35, count 0 2006.201.05:52:12.05#ibcon#*mode == 0, iclass 35, count 0 2006.201.05:52:12.05#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.05:52:12.05#ibcon#[27=USB\r\n] 2006.201.05:52:12.05#ibcon#*before write, iclass 35, count 0 2006.201.05:52:12.05#ibcon#enter sib2, iclass 35, count 0 2006.201.05:52:12.05#ibcon#flushed, iclass 35, count 0 2006.201.05:52:12.05#ibcon#about to write, iclass 35, count 0 2006.201.05:52:12.05#ibcon#wrote, iclass 35, count 0 2006.201.05:52:12.05#ibcon#about to read 3, iclass 35, count 0 2006.201.05:52:12.08#ibcon#read 3, iclass 35, count 0 2006.201.05:52:12.08#ibcon#about to read 4, iclass 35, count 0 2006.201.05:52:12.08#ibcon#read 4, iclass 35, count 0 2006.201.05:52:12.08#ibcon#about to read 5, iclass 35, count 0 2006.201.05:52:12.08#ibcon#read 5, iclass 35, count 0 2006.201.05:52:12.08#ibcon#about to read 6, iclass 35, count 0 2006.201.05:52:12.08#ibcon#read 6, iclass 35, count 0 2006.201.05:52:12.08#ibcon#end of sib2, iclass 35, count 0 2006.201.05:52:12.08#ibcon#*after write, iclass 35, count 0 2006.201.05:52:12.08#ibcon#*before return 0, iclass 35, count 0 2006.201.05:52:12.08#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:12.08#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.05:52:12.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.05:52:12.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.05:52:12.08$vck44/vblo=8,744.99 2006.201.05:52:12.08#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.05:52:12.08#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.05:52:12.08#ibcon#ireg 17 cls_cnt 0 2006.201.05:52:12.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:12.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:12.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:12.08#ibcon#enter wrdev, iclass 37, count 0 2006.201.05:52:12.08#ibcon#first serial, iclass 37, count 0 2006.201.05:52:12.08#ibcon#enter sib2, iclass 37, count 0 2006.201.05:52:12.08#ibcon#flushed, iclass 37, count 0 2006.201.05:52:12.08#ibcon#about to write, iclass 37, count 0 2006.201.05:52:12.08#ibcon#wrote, iclass 37, count 0 2006.201.05:52:12.08#ibcon#about to read 3, iclass 37, count 0 2006.201.05:52:12.10#ibcon#read 3, iclass 37, count 0 2006.201.05:52:12.10#ibcon#about to read 4, iclass 37, count 0 2006.201.05:52:12.10#ibcon#read 4, iclass 37, count 0 2006.201.05:52:12.10#ibcon#about to read 5, iclass 37, count 0 2006.201.05:52:12.10#ibcon#read 5, iclass 37, count 0 2006.201.05:52:12.10#ibcon#about to read 6, iclass 37, count 0 2006.201.05:52:12.10#ibcon#read 6, iclass 37, count 0 2006.201.05:52:12.10#ibcon#end of sib2, iclass 37, count 0 2006.201.05:52:12.10#ibcon#*mode == 0, iclass 37, count 0 2006.201.05:52:12.10#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.05:52:12.10#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.05:52:12.10#ibcon#*before write, iclass 37, count 0 2006.201.05:52:12.10#ibcon#enter sib2, iclass 37, count 0 2006.201.05:52:12.10#ibcon#flushed, iclass 37, count 0 2006.201.05:52:12.10#ibcon#about to write, iclass 37, count 0 2006.201.05:52:12.10#ibcon#wrote, iclass 37, count 0 2006.201.05:52:12.10#ibcon#about to read 3, iclass 37, count 0 2006.201.05:52:12.14#ibcon#read 3, iclass 37, count 0 2006.201.05:52:12.14#ibcon#about to read 4, iclass 37, count 0 2006.201.05:52:12.14#ibcon#read 4, iclass 37, count 0 2006.201.05:52:12.14#ibcon#about to read 5, iclass 37, count 0 2006.201.05:52:12.14#ibcon#read 5, iclass 37, count 0 2006.201.05:52:12.14#ibcon#about to read 6, iclass 37, count 0 2006.201.05:52:12.14#ibcon#read 6, iclass 37, count 0 2006.201.05:52:12.14#ibcon#end of sib2, iclass 37, count 0 2006.201.05:52:12.14#ibcon#*after write, iclass 37, count 0 2006.201.05:52:12.14#ibcon#*before return 0, iclass 37, count 0 2006.201.05:52:12.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:12.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.05:52:12.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.05:52:12.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.05:52:12.14$vck44/vb=8,4 2006.201.05:52:12.14#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.05:52:12.14#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.05:52:12.14#ibcon#ireg 11 cls_cnt 2 2006.201.05:52:12.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:12.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:12.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:12.20#ibcon#enter wrdev, iclass 39, count 2 2006.201.05:52:12.20#ibcon#first serial, iclass 39, count 2 2006.201.05:52:12.20#ibcon#enter sib2, iclass 39, count 2 2006.201.05:52:12.20#ibcon#flushed, iclass 39, count 2 2006.201.05:52:12.20#ibcon#about to write, iclass 39, count 2 2006.201.05:52:12.20#ibcon#wrote, iclass 39, count 2 2006.201.05:52:12.20#ibcon#about to read 3, iclass 39, count 2 2006.201.05:52:12.22#ibcon#read 3, iclass 39, count 2 2006.201.05:52:12.22#ibcon#about to read 4, iclass 39, count 2 2006.201.05:52:12.22#ibcon#read 4, iclass 39, count 2 2006.201.05:52:12.22#ibcon#about to read 5, iclass 39, count 2 2006.201.05:52:12.22#ibcon#read 5, iclass 39, count 2 2006.201.05:52:12.22#ibcon#about to read 6, iclass 39, count 2 2006.201.05:52:12.22#ibcon#read 6, iclass 39, count 2 2006.201.05:52:12.22#ibcon#end of sib2, iclass 39, count 2 2006.201.05:52:12.22#ibcon#*mode == 0, iclass 39, count 2 2006.201.05:52:12.22#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.05:52:12.22#ibcon#[27=AT08-04\r\n] 2006.201.05:52:12.22#ibcon#*before write, iclass 39, count 2 2006.201.05:52:12.22#ibcon#enter sib2, iclass 39, count 2 2006.201.05:52:12.22#ibcon#flushed, iclass 39, count 2 2006.201.05:52:12.22#ibcon#about to write, iclass 39, count 2 2006.201.05:52:12.22#ibcon#wrote, iclass 39, count 2 2006.201.05:52:12.22#ibcon#about to read 3, iclass 39, count 2 2006.201.05:52:12.25#ibcon#read 3, iclass 39, count 2 2006.201.05:52:12.25#ibcon#about to read 4, iclass 39, count 2 2006.201.05:52:12.25#ibcon#read 4, iclass 39, count 2 2006.201.05:52:12.25#ibcon#about to read 5, iclass 39, count 2 2006.201.05:52:12.25#ibcon#read 5, iclass 39, count 2 2006.201.05:52:12.25#ibcon#about to read 6, iclass 39, count 2 2006.201.05:52:12.25#ibcon#read 6, iclass 39, count 2 2006.201.05:52:12.25#ibcon#end of sib2, iclass 39, count 2 2006.201.05:52:12.25#ibcon#*after write, iclass 39, count 2 2006.201.05:52:12.25#ibcon#*before return 0, iclass 39, count 2 2006.201.05:52:12.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:12.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.05:52:12.25#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.05:52:12.25#ibcon#ireg 7 cls_cnt 0 2006.201.05:52:12.25#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:12.37#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:12.37#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:12.37#ibcon#enter wrdev, iclass 39, count 0 2006.201.05:52:12.37#ibcon#first serial, iclass 39, count 0 2006.201.05:52:12.37#ibcon#enter sib2, iclass 39, count 0 2006.201.05:52:12.37#ibcon#flushed, iclass 39, count 0 2006.201.05:52:12.37#ibcon#about to write, iclass 39, count 0 2006.201.05:52:12.37#ibcon#wrote, iclass 39, count 0 2006.201.05:52:12.37#ibcon#about to read 3, iclass 39, count 0 2006.201.05:52:12.39#ibcon#read 3, iclass 39, count 0 2006.201.05:52:12.39#ibcon#about to read 4, iclass 39, count 0 2006.201.05:52:12.39#ibcon#read 4, iclass 39, count 0 2006.201.05:52:12.39#ibcon#about to read 5, iclass 39, count 0 2006.201.05:52:12.39#ibcon#read 5, iclass 39, count 0 2006.201.05:52:12.39#ibcon#about to read 6, iclass 39, count 0 2006.201.05:52:12.39#ibcon#read 6, iclass 39, count 0 2006.201.05:52:12.39#ibcon#end of sib2, iclass 39, count 0 2006.201.05:52:12.39#ibcon#*mode == 0, iclass 39, count 0 2006.201.05:52:12.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.05:52:12.39#ibcon#[27=USB\r\n] 2006.201.05:52:12.39#ibcon#*before write, iclass 39, count 0 2006.201.05:52:12.39#ibcon#enter sib2, iclass 39, count 0 2006.201.05:52:12.39#ibcon#flushed, iclass 39, count 0 2006.201.05:52:12.39#ibcon#about to write, iclass 39, count 0 2006.201.05:52:12.39#ibcon#wrote, iclass 39, count 0 2006.201.05:52:12.39#ibcon#about to read 3, iclass 39, count 0 2006.201.05:52:12.42#ibcon#read 3, iclass 39, count 0 2006.201.05:52:12.42#ibcon#about to read 4, iclass 39, count 0 2006.201.05:52:12.42#ibcon#read 4, iclass 39, count 0 2006.201.05:52:12.42#ibcon#about to read 5, iclass 39, count 0 2006.201.05:52:12.42#ibcon#read 5, iclass 39, count 0 2006.201.05:52:12.42#ibcon#about to read 6, iclass 39, count 0 2006.201.05:52:12.42#ibcon#read 6, iclass 39, count 0 2006.201.05:52:12.42#ibcon#end of sib2, iclass 39, count 0 2006.201.05:52:12.42#ibcon#*after write, iclass 39, count 0 2006.201.05:52:12.42#ibcon#*before return 0, iclass 39, count 0 2006.201.05:52:12.42#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:12.42#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.05:52:12.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.05:52:12.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.05:52:12.42$vck44/vabw=wide 2006.201.05:52:12.42#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.05:52:12.42#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.05:52:12.42#ibcon#ireg 8 cls_cnt 0 2006.201.05:52:12.42#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:12.42#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:12.42#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:12.42#ibcon#enter wrdev, iclass 2, count 0 2006.201.05:52:12.42#ibcon#first serial, iclass 2, count 0 2006.201.05:52:12.42#ibcon#enter sib2, iclass 2, count 0 2006.201.05:52:12.42#ibcon#flushed, iclass 2, count 0 2006.201.05:52:12.42#ibcon#about to write, iclass 2, count 0 2006.201.05:52:12.42#ibcon#wrote, iclass 2, count 0 2006.201.05:52:12.42#ibcon#about to read 3, iclass 2, count 0 2006.201.05:52:12.44#ibcon#read 3, iclass 2, count 0 2006.201.05:52:12.44#ibcon#about to read 4, iclass 2, count 0 2006.201.05:52:12.44#ibcon#read 4, iclass 2, count 0 2006.201.05:52:12.44#ibcon#about to read 5, iclass 2, count 0 2006.201.05:52:12.44#ibcon#read 5, iclass 2, count 0 2006.201.05:52:12.44#ibcon#about to read 6, iclass 2, count 0 2006.201.05:52:12.44#ibcon#read 6, iclass 2, count 0 2006.201.05:52:12.44#ibcon#end of sib2, iclass 2, count 0 2006.201.05:52:12.44#ibcon#*mode == 0, iclass 2, count 0 2006.201.05:52:12.44#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.05:52:12.44#ibcon#[25=BW32\r\n] 2006.201.05:52:12.44#ibcon#*before write, iclass 2, count 0 2006.201.05:52:12.44#ibcon#enter sib2, iclass 2, count 0 2006.201.05:52:12.44#ibcon#flushed, iclass 2, count 0 2006.201.05:52:12.44#ibcon#about to write, iclass 2, count 0 2006.201.05:52:12.44#ibcon#wrote, iclass 2, count 0 2006.201.05:52:12.44#ibcon#about to read 3, iclass 2, count 0 2006.201.05:52:12.47#ibcon#read 3, iclass 2, count 0 2006.201.05:52:12.47#ibcon#about to read 4, iclass 2, count 0 2006.201.05:52:12.47#ibcon#read 4, iclass 2, count 0 2006.201.05:52:12.47#ibcon#about to read 5, iclass 2, count 0 2006.201.05:52:12.47#ibcon#read 5, iclass 2, count 0 2006.201.05:52:12.47#ibcon#about to read 6, iclass 2, count 0 2006.201.05:52:12.47#ibcon#read 6, iclass 2, count 0 2006.201.05:52:12.47#ibcon#end of sib2, iclass 2, count 0 2006.201.05:52:12.47#ibcon#*after write, iclass 2, count 0 2006.201.05:52:12.47#ibcon#*before return 0, iclass 2, count 0 2006.201.05:52:12.47#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:12.47#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.05:52:12.47#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.05:52:12.47#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.05:52:12.47$vck44/vbbw=wide 2006.201.05:52:12.47#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.05:52:12.47#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.05:52:12.47#ibcon#ireg 8 cls_cnt 0 2006.201.05:52:12.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:52:12.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:52:12.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:52:12.54#ibcon#enter wrdev, iclass 5, count 0 2006.201.05:52:12.54#ibcon#first serial, iclass 5, count 0 2006.201.05:52:12.54#ibcon#enter sib2, iclass 5, count 0 2006.201.05:52:12.54#ibcon#flushed, iclass 5, count 0 2006.201.05:52:12.54#ibcon#about to write, iclass 5, count 0 2006.201.05:52:12.54#ibcon#wrote, iclass 5, count 0 2006.201.05:52:12.54#ibcon#about to read 3, iclass 5, count 0 2006.201.05:52:12.56#ibcon#read 3, iclass 5, count 0 2006.201.05:52:12.56#ibcon#about to read 4, iclass 5, count 0 2006.201.05:52:12.56#ibcon#read 4, iclass 5, count 0 2006.201.05:52:12.56#ibcon#about to read 5, iclass 5, count 0 2006.201.05:52:12.56#ibcon#read 5, iclass 5, count 0 2006.201.05:52:12.56#ibcon#about to read 6, iclass 5, count 0 2006.201.05:52:12.56#ibcon#read 6, iclass 5, count 0 2006.201.05:52:12.56#ibcon#end of sib2, iclass 5, count 0 2006.201.05:52:12.56#ibcon#*mode == 0, iclass 5, count 0 2006.201.05:52:12.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.05:52:12.56#ibcon#[27=BW32\r\n] 2006.201.05:52:12.56#ibcon#*before write, iclass 5, count 0 2006.201.05:52:12.56#ibcon#enter sib2, iclass 5, count 0 2006.201.05:52:12.56#ibcon#flushed, iclass 5, count 0 2006.201.05:52:12.56#ibcon#about to write, iclass 5, count 0 2006.201.05:52:12.56#ibcon#wrote, iclass 5, count 0 2006.201.05:52:12.56#ibcon#about to read 3, iclass 5, count 0 2006.201.05:52:12.59#ibcon#read 3, iclass 5, count 0 2006.201.05:52:12.59#ibcon#about to read 4, iclass 5, count 0 2006.201.05:52:12.59#ibcon#read 4, iclass 5, count 0 2006.201.05:52:12.59#ibcon#about to read 5, iclass 5, count 0 2006.201.05:52:12.59#ibcon#read 5, iclass 5, count 0 2006.201.05:52:12.59#ibcon#about to read 6, iclass 5, count 0 2006.201.05:52:12.59#ibcon#read 6, iclass 5, count 0 2006.201.05:52:12.59#ibcon#end of sib2, iclass 5, count 0 2006.201.05:52:12.59#ibcon#*after write, iclass 5, count 0 2006.201.05:52:12.59#ibcon#*before return 0, iclass 5, count 0 2006.201.05:52:12.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:52:12.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.05:52:12.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.05:52:12.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.05:52:12.59$setupk4/ifdk4 2006.201.05:52:12.59$ifdk4/lo= 2006.201.05:52:12.59$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.05:52:12.59$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.05:52:12.59$ifdk4/patch= 2006.201.05:52:12.59$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.05:52:12.59$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.05:52:12.59$setupk4/!*+20s 2006.201.05:52:15.74#abcon#<5=/04 2.7 5.0 23.02 901003.4\r\n> 2006.201.05:52:15.76#abcon#{5=INTERFACE CLEAR} 2006.201.05:52:15.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:52:25.91#abcon#<5=/04 2.6 5.0 23.02 901003.4\r\n> 2006.201.05:52:25.93#abcon#{5=INTERFACE CLEAR} 2006.201.05:52:25.99#abcon#[5=S1D000X0/0*\r\n] 2006.201.05:52:27.03$setupk4/"tpicd 2006.201.05:52:27.03$setupk4/echo=off 2006.201.05:52:27.03$setupk4/xlog=off 2006.201.05:52:27.03:!2006.201.05:59:55 2006.201.05:52:57.14#trakl#Source acquired 2006.201.05:52:59.14#flagr#flagr/antenna,acquired 2006.201.05:59:55.00:preob 2006.201.05:59:55.14/onsource/TRACKING 2006.201.05:59:55.14:!2006.201.06:00:05 2006.201.06:00:05.00:"tape 2006.201.06:00:05.00:"st=record 2006.201.06:00:05.00:data_valid=on 2006.201.06:00:05.00:midob 2006.201.06:00:05.14/onsource/TRACKING 2006.201.06:00:05.14/wx/23.00,1003.3,89 2006.201.06:00:05.31/cable/+6.4654E-03 2006.201.06:00:06.40/va/01,08,usb,yes,28,30 2006.201.06:00:06.40/va/02,07,usb,yes,30,31 2006.201.06:00:06.40/va/03,08,usb,yes,27,28 2006.201.06:00:06.40/va/04,07,usb,yes,31,33 2006.201.06:00:06.40/va/05,04,usb,yes,27,28 2006.201.06:00:06.40/va/06,05,usb,yes,28,27 2006.201.06:00:06.40/va/07,05,usb,yes,27,28 2006.201.06:00:06.40/va/08,04,usb,yes,26,32 2006.201.06:00:06.63/valo/01,524.99,yes,locked 2006.201.06:00:06.63/valo/02,534.99,yes,locked 2006.201.06:00:06.63/valo/03,564.99,yes,locked 2006.201.06:00:06.63/valo/04,624.99,yes,locked 2006.201.06:00:06.63/valo/05,734.99,yes,locked 2006.201.06:00:06.63/valo/06,814.99,yes,locked 2006.201.06:00:06.63/valo/07,864.99,yes,locked 2006.201.06:00:06.63/valo/08,884.99,yes,locked 2006.201.06:00:07.72/vb/01,04,usb,yes,28,26 2006.201.06:00:07.72/vb/02,05,usb,yes,27,27 2006.201.06:00:07.72/vb/03,04,usb,yes,28,31 2006.201.06:00:07.72/vb/04,05,usb,yes,28,27 2006.201.06:00:07.72/vb/05,04,usb,yes,25,27 2006.201.06:00:07.72/vb/06,04,usb,yes,29,25 2006.201.06:00:07.72/vb/07,04,usb,yes,29,29 2006.201.06:00:07.72/vb/08,04,usb,yes,26,30 2006.201.06:00:07.96/vblo/01,629.99,yes,locked 2006.201.06:00:07.96/vblo/02,634.99,yes,locked 2006.201.06:00:07.96/vblo/03,649.99,yes,locked 2006.201.06:00:07.96/vblo/04,679.99,yes,locked 2006.201.06:00:07.96/vblo/05,709.99,yes,locked 2006.201.06:00:07.96/vblo/06,719.99,yes,locked 2006.201.06:00:07.96/vblo/07,734.99,yes,locked 2006.201.06:00:07.96/vblo/08,744.99,yes,locked 2006.201.06:00:08.11/vabw/8 2006.201.06:00:08.26/vbbw/8 2006.201.06:00:08.35/xfe/off,on,15.0 2006.201.06:00:08.74/ifatt/23,28,28,28 2006.201.06:00:09.05/fmout-gps/S +4.49E-07 2006.201.06:00:09.12:!2006.201.06:00:45 2006.201.06:00:45.00:data_valid=off 2006.201.06:00:45.00:"et 2006.201.06:00:45.00:!+3s 2006.201.06:00:48.02:"tape 2006.201.06:00:48.02:postob 2006.201.06:00:48.14/cable/+6.4663E-03 2006.201.06:00:48.14/wx/22.99,1003.3,89 2006.201.06:00:48.20/fmout-gps/S +4.50E-07 2006.201.06:00:48.20:scan_name=201-0602,jd0607,390 2006.201.06:00:48.20:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.201.06:00:50.14#flagr#flagr/antenna,new-source 2006.201.06:00:50.14:checkk5 2006.201.06:00:50.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.06:00:50.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.06:00:51.31/chk_autoobs//k5ts3/ autoobs is running! 2006.201.06:00:51.69/chk_autoobs//k5ts4/ autoobs is running! 2006.201.06:00:52.06/chk_obsdata//k5ts1/T2010600??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.06:00:52.43/chk_obsdata//k5ts2/T2010600??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.06:00:52.82/chk_obsdata//k5ts3/T2010600??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.06:00:53.19/chk_obsdata//k5ts4/T2010600??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.06:00:53.89/k5log//k5ts1_log_newline 2006.201.06:00:54.58/k5log//k5ts2_log_newline 2006.201.06:00:55.29/k5log//k5ts3_log_newline 2006.201.06:00:56.00/k5log//k5ts4_log_newline 2006.201.06:00:56.03/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.06:00:56.03:setupk4=1 2006.201.06:00:56.03$setupk4/echo=on 2006.201.06:00:56.03$setupk4/pcalon 2006.201.06:00:56.03$pcalon/"no phase cal control is implemented here 2006.201.06:00:56.03$setupk4/"tpicd=stop 2006.201.06:00:56.03$setupk4/"rec=synch_on 2006.201.06:00:56.03$setupk4/"rec_mode=128 2006.201.06:00:56.03$setupk4/!* 2006.201.06:00:56.03$setupk4/recpk4 2006.201.06:00:56.03$recpk4/recpatch= 2006.201.06:00:56.03$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.06:00:56.03$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.06:00:56.03$setupk4/vck44 2006.201.06:00:56.03$vck44/valo=1,524.99 2006.201.06:00:56.03#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.06:00:56.03#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.06:00:56.03#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:56.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:56.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:56.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:56.03#ibcon#enter wrdev, iclass 40, count 0 2006.201.06:00:56.03#ibcon#first serial, iclass 40, count 0 2006.201.06:00:56.03#ibcon#enter sib2, iclass 40, count 0 2006.201.06:00:56.03#ibcon#flushed, iclass 40, count 0 2006.201.06:00:56.03#ibcon#about to write, iclass 40, count 0 2006.201.06:00:56.03#ibcon#wrote, iclass 40, count 0 2006.201.06:00:56.03#ibcon#about to read 3, iclass 40, count 0 2006.201.06:00:56.07#ibcon#read 3, iclass 40, count 0 2006.201.06:00:56.07#ibcon#about to read 4, iclass 40, count 0 2006.201.06:00:56.07#ibcon#read 4, iclass 40, count 0 2006.201.06:00:56.07#ibcon#about to read 5, iclass 40, count 0 2006.201.06:00:56.07#ibcon#read 5, iclass 40, count 0 2006.201.06:00:56.07#ibcon#about to read 6, iclass 40, count 0 2006.201.06:00:56.07#ibcon#read 6, iclass 40, count 0 2006.201.06:00:56.07#ibcon#end of sib2, iclass 40, count 0 2006.201.06:00:56.07#ibcon#*mode == 0, iclass 40, count 0 2006.201.06:00:56.07#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.06:00:56.07#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.06:00:56.07#ibcon#*before write, iclass 40, count 0 2006.201.06:00:56.07#ibcon#enter sib2, iclass 40, count 0 2006.201.06:00:56.07#ibcon#flushed, iclass 40, count 0 2006.201.06:00:56.07#ibcon#about to write, iclass 40, count 0 2006.201.06:00:56.07#ibcon#wrote, iclass 40, count 0 2006.201.06:00:56.07#ibcon#about to read 3, iclass 40, count 0 2006.201.06:00:56.12#ibcon#read 3, iclass 40, count 0 2006.201.06:00:56.12#ibcon#about to read 4, iclass 40, count 0 2006.201.06:00:56.12#ibcon#read 4, iclass 40, count 0 2006.201.06:00:56.12#ibcon#about to read 5, iclass 40, count 0 2006.201.06:00:56.12#ibcon#read 5, iclass 40, count 0 2006.201.06:00:56.12#ibcon#about to read 6, iclass 40, count 0 2006.201.06:00:56.12#ibcon#read 6, iclass 40, count 0 2006.201.06:00:56.12#ibcon#end of sib2, iclass 40, count 0 2006.201.06:00:56.12#ibcon#*after write, iclass 40, count 0 2006.201.06:00:56.12#ibcon#*before return 0, iclass 40, count 0 2006.201.06:00:56.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:56.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:56.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.06:00:56.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.06:00:56.12$vck44/va=1,8 2006.201.06:00:56.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.06:00:56.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.06:00:56.12#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:56.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:56.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:56.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:56.12#ibcon#enter wrdev, iclass 4, count 2 2006.201.06:00:56.12#ibcon#first serial, iclass 4, count 2 2006.201.06:00:56.12#ibcon#enter sib2, iclass 4, count 2 2006.201.06:00:56.12#ibcon#flushed, iclass 4, count 2 2006.201.06:00:56.12#ibcon#about to write, iclass 4, count 2 2006.201.06:00:56.12#ibcon#wrote, iclass 4, count 2 2006.201.06:00:56.12#ibcon#about to read 3, iclass 4, count 2 2006.201.06:00:56.14#ibcon#read 3, iclass 4, count 2 2006.201.06:00:56.14#ibcon#about to read 4, iclass 4, count 2 2006.201.06:00:56.14#ibcon#read 4, iclass 4, count 2 2006.201.06:00:56.14#ibcon#about to read 5, iclass 4, count 2 2006.201.06:00:56.14#ibcon#read 5, iclass 4, count 2 2006.201.06:00:56.14#ibcon#about to read 6, iclass 4, count 2 2006.201.06:00:56.14#ibcon#read 6, iclass 4, count 2 2006.201.06:00:56.14#ibcon#end of sib2, iclass 4, count 2 2006.201.06:00:56.14#ibcon#*mode == 0, iclass 4, count 2 2006.201.06:00:56.14#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.06:00:56.14#ibcon#[25=AT01-08\r\n] 2006.201.06:00:56.14#ibcon#*before write, iclass 4, count 2 2006.201.06:00:56.14#ibcon#enter sib2, iclass 4, count 2 2006.201.06:00:56.14#ibcon#flushed, iclass 4, count 2 2006.201.06:00:56.14#ibcon#about to write, iclass 4, count 2 2006.201.06:00:56.14#ibcon#wrote, iclass 4, count 2 2006.201.06:00:56.14#ibcon#about to read 3, iclass 4, count 2 2006.201.06:00:56.18#ibcon#read 3, iclass 4, count 2 2006.201.06:00:56.18#ibcon#about to read 4, iclass 4, count 2 2006.201.06:00:56.18#ibcon#read 4, iclass 4, count 2 2006.201.06:00:56.18#ibcon#about to read 5, iclass 4, count 2 2006.201.06:00:56.18#ibcon#read 5, iclass 4, count 2 2006.201.06:00:56.18#ibcon#about to read 6, iclass 4, count 2 2006.201.06:00:56.18#ibcon#read 6, iclass 4, count 2 2006.201.06:00:56.18#ibcon#end of sib2, iclass 4, count 2 2006.201.06:00:56.18#ibcon#*after write, iclass 4, count 2 2006.201.06:00:56.18#ibcon#*before return 0, iclass 4, count 2 2006.201.06:00:56.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:56.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:56.18#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.06:00:56.18#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:56.18#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:56.30#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:56.30#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:56.30#ibcon#enter wrdev, iclass 4, count 0 2006.201.06:00:56.30#ibcon#first serial, iclass 4, count 0 2006.201.06:00:56.30#ibcon#enter sib2, iclass 4, count 0 2006.201.06:00:56.30#ibcon#flushed, iclass 4, count 0 2006.201.06:00:56.30#ibcon#about to write, iclass 4, count 0 2006.201.06:00:56.30#ibcon#wrote, iclass 4, count 0 2006.201.06:00:56.30#ibcon#about to read 3, iclass 4, count 0 2006.201.06:00:56.32#ibcon#read 3, iclass 4, count 0 2006.201.06:00:56.32#ibcon#about to read 4, iclass 4, count 0 2006.201.06:00:56.32#ibcon#read 4, iclass 4, count 0 2006.201.06:00:56.32#ibcon#about to read 5, iclass 4, count 0 2006.201.06:00:56.32#ibcon#read 5, iclass 4, count 0 2006.201.06:00:56.32#ibcon#about to read 6, iclass 4, count 0 2006.201.06:00:56.32#ibcon#read 6, iclass 4, count 0 2006.201.06:00:56.32#ibcon#end of sib2, iclass 4, count 0 2006.201.06:00:56.32#ibcon#*mode == 0, iclass 4, count 0 2006.201.06:00:56.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.06:00:56.32#ibcon#[25=USB\r\n] 2006.201.06:00:56.32#ibcon#*before write, iclass 4, count 0 2006.201.06:00:56.32#ibcon#enter sib2, iclass 4, count 0 2006.201.06:00:56.32#ibcon#flushed, iclass 4, count 0 2006.201.06:00:56.32#ibcon#about to write, iclass 4, count 0 2006.201.06:00:56.32#ibcon#wrote, iclass 4, count 0 2006.201.06:00:56.32#ibcon#about to read 3, iclass 4, count 0 2006.201.06:00:56.35#ibcon#read 3, iclass 4, count 0 2006.201.06:00:56.35#ibcon#about to read 4, iclass 4, count 0 2006.201.06:00:56.35#ibcon#read 4, iclass 4, count 0 2006.201.06:00:56.35#ibcon#about to read 5, iclass 4, count 0 2006.201.06:00:56.35#ibcon#read 5, iclass 4, count 0 2006.201.06:00:56.35#ibcon#about to read 6, iclass 4, count 0 2006.201.06:00:56.35#ibcon#read 6, iclass 4, count 0 2006.201.06:00:56.35#ibcon#end of sib2, iclass 4, count 0 2006.201.06:00:56.35#ibcon#*after write, iclass 4, count 0 2006.201.06:00:56.35#ibcon#*before return 0, iclass 4, count 0 2006.201.06:00:56.35#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:56.35#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:56.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.06:00:56.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.06:00:56.35$vck44/valo=2,534.99 2006.201.06:00:56.35#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.06:00:56.35#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.06:00:56.35#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:56.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:56.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:56.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:56.35#ibcon#enter wrdev, iclass 6, count 0 2006.201.06:00:56.35#ibcon#first serial, iclass 6, count 0 2006.201.06:00:56.35#ibcon#enter sib2, iclass 6, count 0 2006.201.06:00:56.35#ibcon#flushed, iclass 6, count 0 2006.201.06:00:56.35#ibcon#about to write, iclass 6, count 0 2006.201.06:00:56.35#ibcon#wrote, iclass 6, count 0 2006.201.06:00:56.35#ibcon#about to read 3, iclass 6, count 0 2006.201.06:00:56.37#ibcon#read 3, iclass 6, count 0 2006.201.06:00:56.37#ibcon#about to read 4, iclass 6, count 0 2006.201.06:00:56.37#ibcon#read 4, iclass 6, count 0 2006.201.06:00:56.37#ibcon#about to read 5, iclass 6, count 0 2006.201.06:00:56.37#ibcon#read 5, iclass 6, count 0 2006.201.06:00:56.37#ibcon#about to read 6, iclass 6, count 0 2006.201.06:00:56.37#ibcon#read 6, iclass 6, count 0 2006.201.06:00:56.37#ibcon#end of sib2, iclass 6, count 0 2006.201.06:00:56.37#ibcon#*mode == 0, iclass 6, count 0 2006.201.06:00:56.37#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.06:00:56.37#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.06:00:56.37#ibcon#*before write, iclass 6, count 0 2006.201.06:00:56.37#ibcon#enter sib2, iclass 6, count 0 2006.201.06:00:56.37#ibcon#flushed, iclass 6, count 0 2006.201.06:00:56.37#ibcon#about to write, iclass 6, count 0 2006.201.06:00:56.37#ibcon#wrote, iclass 6, count 0 2006.201.06:00:56.37#ibcon#about to read 3, iclass 6, count 0 2006.201.06:00:56.41#ibcon#read 3, iclass 6, count 0 2006.201.06:00:56.41#ibcon#about to read 4, iclass 6, count 0 2006.201.06:00:56.41#ibcon#read 4, iclass 6, count 0 2006.201.06:00:56.41#ibcon#about to read 5, iclass 6, count 0 2006.201.06:00:56.41#ibcon#read 5, iclass 6, count 0 2006.201.06:00:56.41#ibcon#about to read 6, iclass 6, count 0 2006.201.06:00:56.41#ibcon#read 6, iclass 6, count 0 2006.201.06:00:56.41#ibcon#end of sib2, iclass 6, count 0 2006.201.06:00:56.41#ibcon#*after write, iclass 6, count 0 2006.201.06:00:56.41#ibcon#*before return 0, iclass 6, count 0 2006.201.06:00:56.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:56.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:56.41#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.06:00:56.41#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.06:00:56.41$vck44/va=2,7 2006.201.06:00:56.41#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.06:00:56.41#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.06:00:56.41#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:56.41#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:56.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:56.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:56.47#ibcon#enter wrdev, iclass 10, count 2 2006.201.06:00:56.47#ibcon#first serial, iclass 10, count 2 2006.201.06:00:56.47#ibcon#enter sib2, iclass 10, count 2 2006.201.06:00:56.47#ibcon#flushed, iclass 10, count 2 2006.201.06:00:56.47#ibcon#about to write, iclass 10, count 2 2006.201.06:00:56.47#ibcon#wrote, iclass 10, count 2 2006.201.06:00:56.47#ibcon#about to read 3, iclass 10, count 2 2006.201.06:00:56.49#ibcon#read 3, iclass 10, count 2 2006.201.06:00:56.49#ibcon#about to read 4, iclass 10, count 2 2006.201.06:00:56.49#ibcon#read 4, iclass 10, count 2 2006.201.06:00:56.49#ibcon#about to read 5, iclass 10, count 2 2006.201.06:00:56.49#ibcon#read 5, iclass 10, count 2 2006.201.06:00:56.49#ibcon#about to read 6, iclass 10, count 2 2006.201.06:00:56.49#ibcon#read 6, iclass 10, count 2 2006.201.06:00:56.49#ibcon#end of sib2, iclass 10, count 2 2006.201.06:00:56.49#ibcon#*mode == 0, iclass 10, count 2 2006.201.06:00:56.49#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.06:00:56.49#ibcon#[25=AT02-07\r\n] 2006.201.06:00:56.49#ibcon#*before write, iclass 10, count 2 2006.201.06:00:56.49#ibcon#enter sib2, iclass 10, count 2 2006.201.06:00:56.49#ibcon#flushed, iclass 10, count 2 2006.201.06:00:56.49#ibcon#about to write, iclass 10, count 2 2006.201.06:00:56.49#ibcon#wrote, iclass 10, count 2 2006.201.06:00:56.49#ibcon#about to read 3, iclass 10, count 2 2006.201.06:00:56.52#ibcon#read 3, iclass 10, count 2 2006.201.06:00:56.52#ibcon#about to read 4, iclass 10, count 2 2006.201.06:00:56.52#ibcon#read 4, iclass 10, count 2 2006.201.06:00:56.52#ibcon#about to read 5, iclass 10, count 2 2006.201.06:00:56.52#ibcon#read 5, iclass 10, count 2 2006.201.06:00:56.52#ibcon#about to read 6, iclass 10, count 2 2006.201.06:00:56.52#ibcon#read 6, iclass 10, count 2 2006.201.06:00:56.52#ibcon#end of sib2, iclass 10, count 2 2006.201.06:00:56.52#ibcon#*after write, iclass 10, count 2 2006.201.06:00:56.52#ibcon#*before return 0, iclass 10, count 2 2006.201.06:00:56.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:56.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:56.52#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.06:00:56.52#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:56.52#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:56.64#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:56.64#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:56.64#ibcon#enter wrdev, iclass 10, count 0 2006.201.06:00:56.64#ibcon#first serial, iclass 10, count 0 2006.201.06:00:56.64#ibcon#enter sib2, iclass 10, count 0 2006.201.06:00:56.64#ibcon#flushed, iclass 10, count 0 2006.201.06:00:56.64#ibcon#about to write, iclass 10, count 0 2006.201.06:00:56.64#ibcon#wrote, iclass 10, count 0 2006.201.06:00:56.64#ibcon#about to read 3, iclass 10, count 0 2006.201.06:00:56.66#ibcon#read 3, iclass 10, count 0 2006.201.06:00:56.66#ibcon#about to read 4, iclass 10, count 0 2006.201.06:00:56.66#ibcon#read 4, iclass 10, count 0 2006.201.06:00:56.66#ibcon#about to read 5, iclass 10, count 0 2006.201.06:00:56.66#ibcon#read 5, iclass 10, count 0 2006.201.06:00:56.66#ibcon#about to read 6, iclass 10, count 0 2006.201.06:00:56.66#ibcon#read 6, iclass 10, count 0 2006.201.06:00:56.66#ibcon#end of sib2, iclass 10, count 0 2006.201.06:00:56.66#ibcon#*mode == 0, iclass 10, count 0 2006.201.06:00:56.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.06:00:56.66#ibcon#[25=USB\r\n] 2006.201.06:00:56.66#ibcon#*before write, iclass 10, count 0 2006.201.06:00:56.66#ibcon#enter sib2, iclass 10, count 0 2006.201.06:00:56.66#ibcon#flushed, iclass 10, count 0 2006.201.06:00:56.66#ibcon#about to write, iclass 10, count 0 2006.201.06:00:56.66#ibcon#wrote, iclass 10, count 0 2006.201.06:00:56.66#ibcon#about to read 3, iclass 10, count 0 2006.201.06:00:56.69#ibcon#read 3, iclass 10, count 0 2006.201.06:00:56.69#ibcon#about to read 4, iclass 10, count 0 2006.201.06:00:56.69#ibcon#read 4, iclass 10, count 0 2006.201.06:00:56.69#ibcon#about to read 5, iclass 10, count 0 2006.201.06:00:56.69#ibcon#read 5, iclass 10, count 0 2006.201.06:00:56.69#ibcon#about to read 6, iclass 10, count 0 2006.201.06:00:56.69#ibcon#read 6, iclass 10, count 0 2006.201.06:00:56.69#ibcon#end of sib2, iclass 10, count 0 2006.201.06:00:56.69#ibcon#*after write, iclass 10, count 0 2006.201.06:00:56.69#ibcon#*before return 0, iclass 10, count 0 2006.201.06:00:56.69#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:56.69#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:56.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.06:00:56.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.06:00:56.69$vck44/valo=3,564.99 2006.201.06:00:56.69#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.06:00:56.69#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.06:00:56.69#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:56.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:56.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:56.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:56.69#ibcon#enter wrdev, iclass 12, count 0 2006.201.06:00:56.69#ibcon#first serial, iclass 12, count 0 2006.201.06:00:56.69#ibcon#enter sib2, iclass 12, count 0 2006.201.06:00:56.69#ibcon#flushed, iclass 12, count 0 2006.201.06:00:56.69#ibcon#about to write, iclass 12, count 0 2006.201.06:00:56.69#ibcon#wrote, iclass 12, count 0 2006.201.06:00:56.69#ibcon#about to read 3, iclass 12, count 0 2006.201.06:00:56.71#ibcon#read 3, iclass 12, count 0 2006.201.06:00:56.71#ibcon#about to read 4, iclass 12, count 0 2006.201.06:00:56.71#ibcon#read 4, iclass 12, count 0 2006.201.06:00:56.71#ibcon#about to read 5, iclass 12, count 0 2006.201.06:00:56.71#ibcon#read 5, iclass 12, count 0 2006.201.06:00:56.71#ibcon#about to read 6, iclass 12, count 0 2006.201.06:00:56.71#ibcon#read 6, iclass 12, count 0 2006.201.06:00:56.71#ibcon#end of sib2, iclass 12, count 0 2006.201.06:00:56.71#ibcon#*mode == 0, iclass 12, count 0 2006.201.06:00:56.71#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.06:00:56.71#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.06:00:56.71#ibcon#*before write, iclass 12, count 0 2006.201.06:00:56.71#ibcon#enter sib2, iclass 12, count 0 2006.201.06:00:56.71#ibcon#flushed, iclass 12, count 0 2006.201.06:00:56.71#ibcon#about to write, iclass 12, count 0 2006.201.06:00:56.71#ibcon#wrote, iclass 12, count 0 2006.201.06:00:56.71#ibcon#about to read 3, iclass 12, count 0 2006.201.06:00:56.75#ibcon#read 3, iclass 12, count 0 2006.201.06:00:56.75#ibcon#about to read 4, iclass 12, count 0 2006.201.06:00:56.75#ibcon#read 4, iclass 12, count 0 2006.201.06:00:56.75#ibcon#about to read 5, iclass 12, count 0 2006.201.06:00:56.75#ibcon#read 5, iclass 12, count 0 2006.201.06:00:56.75#ibcon#about to read 6, iclass 12, count 0 2006.201.06:00:56.75#ibcon#read 6, iclass 12, count 0 2006.201.06:00:56.75#ibcon#end of sib2, iclass 12, count 0 2006.201.06:00:56.75#ibcon#*after write, iclass 12, count 0 2006.201.06:00:56.75#ibcon#*before return 0, iclass 12, count 0 2006.201.06:00:56.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:56.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:56.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.06:00:56.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.06:00:56.75$vck44/va=3,8 2006.201.06:00:56.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.06:00:56.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.06:00:56.75#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:56.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:56.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:56.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:56.81#ibcon#enter wrdev, iclass 14, count 2 2006.201.06:00:56.81#ibcon#first serial, iclass 14, count 2 2006.201.06:00:56.81#ibcon#enter sib2, iclass 14, count 2 2006.201.06:00:56.81#ibcon#flushed, iclass 14, count 2 2006.201.06:00:56.81#ibcon#about to write, iclass 14, count 2 2006.201.06:00:56.81#ibcon#wrote, iclass 14, count 2 2006.201.06:00:56.81#ibcon#about to read 3, iclass 14, count 2 2006.201.06:00:56.83#ibcon#read 3, iclass 14, count 2 2006.201.06:00:56.83#ibcon#about to read 4, iclass 14, count 2 2006.201.06:00:56.83#ibcon#read 4, iclass 14, count 2 2006.201.06:00:56.83#ibcon#about to read 5, iclass 14, count 2 2006.201.06:00:56.83#ibcon#read 5, iclass 14, count 2 2006.201.06:00:56.83#ibcon#about to read 6, iclass 14, count 2 2006.201.06:00:56.83#ibcon#read 6, iclass 14, count 2 2006.201.06:00:56.83#ibcon#end of sib2, iclass 14, count 2 2006.201.06:00:56.83#ibcon#*mode == 0, iclass 14, count 2 2006.201.06:00:56.83#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.06:00:56.83#ibcon#[25=AT03-08\r\n] 2006.201.06:00:56.83#ibcon#*before write, iclass 14, count 2 2006.201.06:00:56.83#ibcon#enter sib2, iclass 14, count 2 2006.201.06:00:56.83#ibcon#flushed, iclass 14, count 2 2006.201.06:00:56.83#ibcon#about to write, iclass 14, count 2 2006.201.06:00:56.83#ibcon#wrote, iclass 14, count 2 2006.201.06:00:56.83#ibcon#about to read 3, iclass 14, count 2 2006.201.06:00:56.86#ibcon#read 3, iclass 14, count 2 2006.201.06:00:56.86#ibcon#about to read 4, iclass 14, count 2 2006.201.06:00:56.86#ibcon#read 4, iclass 14, count 2 2006.201.06:00:56.86#ibcon#about to read 5, iclass 14, count 2 2006.201.06:00:56.86#ibcon#read 5, iclass 14, count 2 2006.201.06:00:56.86#ibcon#about to read 6, iclass 14, count 2 2006.201.06:00:56.86#ibcon#read 6, iclass 14, count 2 2006.201.06:00:56.86#ibcon#end of sib2, iclass 14, count 2 2006.201.06:00:56.86#ibcon#*after write, iclass 14, count 2 2006.201.06:00:56.86#ibcon#*before return 0, iclass 14, count 2 2006.201.06:00:56.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:56.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:56.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.06:00:56.86#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:56.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:00:56.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:00:56.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:00:56.98#ibcon#enter wrdev, iclass 14, count 0 2006.201.06:00:56.98#ibcon#first serial, iclass 14, count 0 2006.201.06:00:56.98#ibcon#enter sib2, iclass 14, count 0 2006.201.06:00:56.98#ibcon#flushed, iclass 14, count 0 2006.201.06:00:56.98#ibcon#about to write, iclass 14, count 0 2006.201.06:00:56.98#ibcon#wrote, iclass 14, count 0 2006.201.06:00:56.98#ibcon#about to read 3, iclass 14, count 0 2006.201.06:00:57.00#ibcon#read 3, iclass 14, count 0 2006.201.06:00:57.00#ibcon#about to read 4, iclass 14, count 0 2006.201.06:00:57.00#ibcon#read 4, iclass 14, count 0 2006.201.06:00:57.00#ibcon#about to read 5, iclass 14, count 0 2006.201.06:00:57.00#ibcon#read 5, iclass 14, count 0 2006.201.06:00:57.00#ibcon#about to read 6, iclass 14, count 0 2006.201.06:00:57.00#ibcon#read 6, iclass 14, count 0 2006.201.06:00:57.00#ibcon#end of sib2, iclass 14, count 0 2006.201.06:00:57.00#ibcon#*mode == 0, iclass 14, count 0 2006.201.06:00:57.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.06:00:57.00#ibcon#[25=USB\r\n] 2006.201.06:00:57.00#ibcon#*before write, iclass 14, count 0 2006.201.06:00:57.00#ibcon#enter sib2, iclass 14, count 0 2006.201.06:00:57.00#ibcon#flushed, iclass 14, count 0 2006.201.06:00:57.00#ibcon#about to write, iclass 14, count 0 2006.201.06:00:57.00#ibcon#wrote, iclass 14, count 0 2006.201.06:00:57.00#ibcon#about to read 3, iclass 14, count 0 2006.201.06:00:57.03#ibcon#read 3, iclass 14, count 0 2006.201.06:00:57.03#ibcon#about to read 4, iclass 14, count 0 2006.201.06:00:57.03#ibcon#read 4, iclass 14, count 0 2006.201.06:00:57.03#ibcon#about to read 5, iclass 14, count 0 2006.201.06:00:57.03#ibcon#read 5, iclass 14, count 0 2006.201.06:00:57.03#ibcon#about to read 6, iclass 14, count 0 2006.201.06:00:57.03#ibcon#read 6, iclass 14, count 0 2006.201.06:00:57.03#ibcon#end of sib2, iclass 14, count 0 2006.201.06:00:57.03#ibcon#*after write, iclass 14, count 0 2006.201.06:00:57.03#ibcon#*before return 0, iclass 14, count 0 2006.201.06:00:57.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:00:57.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:00:57.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.06:00:57.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.06:00:57.03$vck44/valo=4,624.99 2006.201.06:00:57.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.06:00:57.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.06:00:57.03#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:57.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:00:57.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:00:57.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:00:57.03#ibcon#enter wrdev, iclass 16, count 0 2006.201.06:00:57.03#ibcon#first serial, iclass 16, count 0 2006.201.06:00:57.03#ibcon#enter sib2, iclass 16, count 0 2006.201.06:00:57.03#ibcon#flushed, iclass 16, count 0 2006.201.06:00:57.03#ibcon#about to write, iclass 16, count 0 2006.201.06:00:57.03#ibcon#wrote, iclass 16, count 0 2006.201.06:00:57.03#ibcon#about to read 3, iclass 16, count 0 2006.201.06:00:57.05#ibcon#read 3, iclass 16, count 0 2006.201.06:00:57.05#ibcon#about to read 4, iclass 16, count 0 2006.201.06:00:57.05#ibcon#read 4, iclass 16, count 0 2006.201.06:00:57.05#ibcon#about to read 5, iclass 16, count 0 2006.201.06:00:57.05#ibcon#read 5, iclass 16, count 0 2006.201.06:00:57.05#ibcon#about to read 6, iclass 16, count 0 2006.201.06:00:57.05#ibcon#read 6, iclass 16, count 0 2006.201.06:00:57.05#ibcon#end of sib2, iclass 16, count 0 2006.201.06:00:57.05#ibcon#*mode == 0, iclass 16, count 0 2006.201.06:00:57.05#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.06:00:57.05#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.06:00:57.05#ibcon#*before write, iclass 16, count 0 2006.201.06:00:57.05#ibcon#enter sib2, iclass 16, count 0 2006.201.06:00:57.05#ibcon#flushed, iclass 16, count 0 2006.201.06:00:57.05#ibcon#about to write, iclass 16, count 0 2006.201.06:00:57.05#ibcon#wrote, iclass 16, count 0 2006.201.06:00:57.05#ibcon#about to read 3, iclass 16, count 0 2006.201.06:00:57.09#ibcon#read 3, iclass 16, count 0 2006.201.06:00:57.09#ibcon#about to read 4, iclass 16, count 0 2006.201.06:00:57.09#ibcon#read 4, iclass 16, count 0 2006.201.06:00:57.09#ibcon#about to read 5, iclass 16, count 0 2006.201.06:00:57.09#ibcon#read 5, iclass 16, count 0 2006.201.06:00:57.09#ibcon#about to read 6, iclass 16, count 0 2006.201.06:00:57.09#ibcon#read 6, iclass 16, count 0 2006.201.06:00:57.09#ibcon#end of sib2, iclass 16, count 0 2006.201.06:00:57.09#ibcon#*after write, iclass 16, count 0 2006.201.06:00:57.09#ibcon#*before return 0, iclass 16, count 0 2006.201.06:00:57.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:00:57.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:00:57.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.06:00:57.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.06:00:57.09$vck44/va=4,7 2006.201.06:00:57.09#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.06:00:57.09#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.06:00:57.09#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:57.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:00:57.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:00:57.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:00:57.15#ibcon#enter wrdev, iclass 18, count 2 2006.201.06:00:57.15#ibcon#first serial, iclass 18, count 2 2006.201.06:00:57.15#ibcon#enter sib2, iclass 18, count 2 2006.201.06:00:57.15#ibcon#flushed, iclass 18, count 2 2006.201.06:00:57.15#ibcon#about to write, iclass 18, count 2 2006.201.06:00:57.15#ibcon#wrote, iclass 18, count 2 2006.201.06:00:57.15#ibcon#about to read 3, iclass 18, count 2 2006.201.06:00:57.17#ibcon#read 3, iclass 18, count 2 2006.201.06:00:57.17#ibcon#about to read 4, iclass 18, count 2 2006.201.06:00:57.17#ibcon#read 4, iclass 18, count 2 2006.201.06:00:57.17#ibcon#about to read 5, iclass 18, count 2 2006.201.06:00:57.17#ibcon#read 5, iclass 18, count 2 2006.201.06:00:57.17#ibcon#about to read 6, iclass 18, count 2 2006.201.06:00:57.17#ibcon#read 6, iclass 18, count 2 2006.201.06:00:57.17#ibcon#end of sib2, iclass 18, count 2 2006.201.06:00:57.17#ibcon#*mode == 0, iclass 18, count 2 2006.201.06:00:57.17#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.06:00:57.17#ibcon#[25=AT04-07\r\n] 2006.201.06:00:57.17#ibcon#*before write, iclass 18, count 2 2006.201.06:00:57.17#ibcon#enter sib2, iclass 18, count 2 2006.201.06:00:57.17#ibcon#flushed, iclass 18, count 2 2006.201.06:00:57.17#ibcon#about to write, iclass 18, count 2 2006.201.06:00:57.17#ibcon#wrote, iclass 18, count 2 2006.201.06:00:57.17#ibcon#about to read 3, iclass 18, count 2 2006.201.06:00:57.20#ibcon#read 3, iclass 18, count 2 2006.201.06:00:57.20#ibcon#about to read 4, iclass 18, count 2 2006.201.06:00:57.20#ibcon#read 4, iclass 18, count 2 2006.201.06:00:57.20#ibcon#about to read 5, iclass 18, count 2 2006.201.06:00:57.20#ibcon#read 5, iclass 18, count 2 2006.201.06:00:57.20#ibcon#about to read 6, iclass 18, count 2 2006.201.06:00:57.20#ibcon#read 6, iclass 18, count 2 2006.201.06:00:57.20#ibcon#end of sib2, iclass 18, count 2 2006.201.06:00:57.20#ibcon#*after write, iclass 18, count 2 2006.201.06:00:57.20#ibcon#*before return 0, iclass 18, count 2 2006.201.06:00:57.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:00:57.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:00:57.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.06:00:57.20#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:57.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:00:57.32#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:00:57.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:00:57.32#ibcon#enter wrdev, iclass 18, count 0 2006.201.06:00:57.32#ibcon#first serial, iclass 18, count 0 2006.201.06:00:57.32#ibcon#enter sib2, iclass 18, count 0 2006.201.06:00:57.32#ibcon#flushed, iclass 18, count 0 2006.201.06:00:57.32#ibcon#about to write, iclass 18, count 0 2006.201.06:00:57.32#ibcon#wrote, iclass 18, count 0 2006.201.06:00:57.32#ibcon#about to read 3, iclass 18, count 0 2006.201.06:00:57.34#ibcon#read 3, iclass 18, count 0 2006.201.06:00:57.34#ibcon#about to read 4, iclass 18, count 0 2006.201.06:00:57.34#ibcon#read 4, iclass 18, count 0 2006.201.06:00:57.34#ibcon#about to read 5, iclass 18, count 0 2006.201.06:00:57.34#ibcon#read 5, iclass 18, count 0 2006.201.06:00:57.34#ibcon#about to read 6, iclass 18, count 0 2006.201.06:00:57.34#ibcon#read 6, iclass 18, count 0 2006.201.06:00:57.34#ibcon#end of sib2, iclass 18, count 0 2006.201.06:00:57.34#ibcon#*mode == 0, iclass 18, count 0 2006.201.06:00:57.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.06:00:57.34#ibcon#[25=USB\r\n] 2006.201.06:00:57.34#ibcon#*before write, iclass 18, count 0 2006.201.06:00:57.34#ibcon#enter sib2, iclass 18, count 0 2006.201.06:00:57.34#ibcon#flushed, iclass 18, count 0 2006.201.06:00:57.34#ibcon#about to write, iclass 18, count 0 2006.201.06:00:57.34#ibcon#wrote, iclass 18, count 0 2006.201.06:00:57.34#ibcon#about to read 3, iclass 18, count 0 2006.201.06:00:57.37#ibcon#read 3, iclass 18, count 0 2006.201.06:00:57.37#ibcon#about to read 4, iclass 18, count 0 2006.201.06:00:57.37#ibcon#read 4, iclass 18, count 0 2006.201.06:00:57.37#ibcon#about to read 5, iclass 18, count 0 2006.201.06:00:57.37#ibcon#read 5, iclass 18, count 0 2006.201.06:00:57.37#ibcon#about to read 6, iclass 18, count 0 2006.201.06:00:57.37#ibcon#read 6, iclass 18, count 0 2006.201.06:00:57.37#ibcon#end of sib2, iclass 18, count 0 2006.201.06:00:57.37#ibcon#*after write, iclass 18, count 0 2006.201.06:00:57.37#ibcon#*before return 0, iclass 18, count 0 2006.201.06:00:57.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:00:57.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:00:57.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.06:00:57.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.06:00:57.37$vck44/valo=5,734.99 2006.201.06:00:57.37#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.06:00:57.37#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.06:00:57.37#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:57.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:00:57.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:00:57.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:00:57.37#ibcon#enter wrdev, iclass 20, count 0 2006.201.06:00:57.37#ibcon#first serial, iclass 20, count 0 2006.201.06:00:57.37#ibcon#enter sib2, iclass 20, count 0 2006.201.06:00:57.37#ibcon#flushed, iclass 20, count 0 2006.201.06:00:57.37#ibcon#about to write, iclass 20, count 0 2006.201.06:00:57.37#ibcon#wrote, iclass 20, count 0 2006.201.06:00:57.37#ibcon#about to read 3, iclass 20, count 0 2006.201.06:00:57.39#ibcon#read 3, iclass 20, count 0 2006.201.06:00:57.39#ibcon#about to read 4, iclass 20, count 0 2006.201.06:00:57.39#ibcon#read 4, iclass 20, count 0 2006.201.06:00:57.39#ibcon#about to read 5, iclass 20, count 0 2006.201.06:00:57.39#ibcon#read 5, iclass 20, count 0 2006.201.06:00:57.39#ibcon#about to read 6, iclass 20, count 0 2006.201.06:00:57.39#ibcon#read 6, iclass 20, count 0 2006.201.06:00:57.39#ibcon#end of sib2, iclass 20, count 0 2006.201.06:00:57.39#ibcon#*mode == 0, iclass 20, count 0 2006.201.06:00:57.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.06:00:57.39#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.06:00:57.39#ibcon#*before write, iclass 20, count 0 2006.201.06:00:57.39#ibcon#enter sib2, iclass 20, count 0 2006.201.06:00:57.39#ibcon#flushed, iclass 20, count 0 2006.201.06:00:57.39#ibcon#about to write, iclass 20, count 0 2006.201.06:00:57.39#ibcon#wrote, iclass 20, count 0 2006.201.06:00:57.39#ibcon#about to read 3, iclass 20, count 0 2006.201.06:00:57.43#ibcon#read 3, iclass 20, count 0 2006.201.06:00:57.43#ibcon#about to read 4, iclass 20, count 0 2006.201.06:00:57.43#ibcon#read 4, iclass 20, count 0 2006.201.06:00:57.43#ibcon#about to read 5, iclass 20, count 0 2006.201.06:00:57.43#ibcon#read 5, iclass 20, count 0 2006.201.06:00:57.43#ibcon#about to read 6, iclass 20, count 0 2006.201.06:00:57.43#ibcon#read 6, iclass 20, count 0 2006.201.06:00:57.43#ibcon#end of sib2, iclass 20, count 0 2006.201.06:00:57.43#ibcon#*after write, iclass 20, count 0 2006.201.06:00:57.43#ibcon#*before return 0, iclass 20, count 0 2006.201.06:00:57.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:00:57.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:00:57.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.06:00:57.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.06:00:57.43$vck44/va=5,4 2006.201.06:00:57.43#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.06:00:57.43#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.06:00:57.43#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:57.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:00:57.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:00:57.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:00:57.49#ibcon#enter wrdev, iclass 22, count 2 2006.201.06:00:57.49#ibcon#first serial, iclass 22, count 2 2006.201.06:00:57.49#ibcon#enter sib2, iclass 22, count 2 2006.201.06:00:57.49#ibcon#flushed, iclass 22, count 2 2006.201.06:00:57.49#ibcon#about to write, iclass 22, count 2 2006.201.06:00:57.49#ibcon#wrote, iclass 22, count 2 2006.201.06:00:57.49#ibcon#about to read 3, iclass 22, count 2 2006.201.06:00:57.51#ibcon#read 3, iclass 22, count 2 2006.201.06:00:57.51#ibcon#about to read 4, iclass 22, count 2 2006.201.06:00:57.51#ibcon#read 4, iclass 22, count 2 2006.201.06:00:57.51#ibcon#about to read 5, iclass 22, count 2 2006.201.06:00:57.51#ibcon#read 5, iclass 22, count 2 2006.201.06:00:57.51#ibcon#about to read 6, iclass 22, count 2 2006.201.06:00:57.51#ibcon#read 6, iclass 22, count 2 2006.201.06:00:57.51#ibcon#end of sib2, iclass 22, count 2 2006.201.06:00:57.51#ibcon#*mode == 0, iclass 22, count 2 2006.201.06:00:57.51#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.06:00:57.51#ibcon#[25=AT05-04\r\n] 2006.201.06:00:57.51#ibcon#*before write, iclass 22, count 2 2006.201.06:00:57.51#ibcon#enter sib2, iclass 22, count 2 2006.201.06:00:57.51#ibcon#flushed, iclass 22, count 2 2006.201.06:00:57.51#ibcon#about to write, iclass 22, count 2 2006.201.06:00:57.51#ibcon#wrote, iclass 22, count 2 2006.201.06:00:57.51#ibcon#about to read 3, iclass 22, count 2 2006.201.06:00:57.54#ibcon#read 3, iclass 22, count 2 2006.201.06:00:57.54#ibcon#about to read 4, iclass 22, count 2 2006.201.06:00:57.54#ibcon#read 4, iclass 22, count 2 2006.201.06:00:57.54#ibcon#about to read 5, iclass 22, count 2 2006.201.06:00:57.54#ibcon#read 5, iclass 22, count 2 2006.201.06:00:57.54#ibcon#about to read 6, iclass 22, count 2 2006.201.06:00:57.54#ibcon#read 6, iclass 22, count 2 2006.201.06:00:57.54#ibcon#end of sib2, iclass 22, count 2 2006.201.06:00:57.54#ibcon#*after write, iclass 22, count 2 2006.201.06:00:57.54#ibcon#*before return 0, iclass 22, count 2 2006.201.06:00:57.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:00:57.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:00:57.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.06:00:57.54#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:57.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:00:57.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:00:57.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:00:57.66#ibcon#enter wrdev, iclass 22, count 0 2006.201.06:00:57.66#ibcon#first serial, iclass 22, count 0 2006.201.06:00:57.66#ibcon#enter sib2, iclass 22, count 0 2006.201.06:00:57.66#ibcon#flushed, iclass 22, count 0 2006.201.06:00:57.66#ibcon#about to write, iclass 22, count 0 2006.201.06:00:57.66#ibcon#wrote, iclass 22, count 0 2006.201.06:00:57.66#ibcon#about to read 3, iclass 22, count 0 2006.201.06:00:57.68#ibcon#read 3, iclass 22, count 0 2006.201.06:00:57.68#ibcon#about to read 4, iclass 22, count 0 2006.201.06:00:57.68#ibcon#read 4, iclass 22, count 0 2006.201.06:00:57.68#ibcon#about to read 5, iclass 22, count 0 2006.201.06:00:57.68#ibcon#read 5, iclass 22, count 0 2006.201.06:00:57.68#ibcon#about to read 6, iclass 22, count 0 2006.201.06:00:57.68#ibcon#read 6, iclass 22, count 0 2006.201.06:00:57.68#ibcon#end of sib2, iclass 22, count 0 2006.201.06:00:57.68#ibcon#*mode == 0, iclass 22, count 0 2006.201.06:00:57.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.06:00:57.68#ibcon#[25=USB\r\n] 2006.201.06:00:57.68#ibcon#*before write, iclass 22, count 0 2006.201.06:00:57.68#ibcon#enter sib2, iclass 22, count 0 2006.201.06:00:57.68#ibcon#flushed, iclass 22, count 0 2006.201.06:00:57.68#ibcon#about to write, iclass 22, count 0 2006.201.06:00:57.68#ibcon#wrote, iclass 22, count 0 2006.201.06:00:57.68#ibcon#about to read 3, iclass 22, count 0 2006.201.06:00:57.71#ibcon#read 3, iclass 22, count 0 2006.201.06:00:57.71#ibcon#about to read 4, iclass 22, count 0 2006.201.06:00:57.71#ibcon#read 4, iclass 22, count 0 2006.201.06:00:57.71#ibcon#about to read 5, iclass 22, count 0 2006.201.06:00:57.71#ibcon#read 5, iclass 22, count 0 2006.201.06:00:57.71#ibcon#about to read 6, iclass 22, count 0 2006.201.06:00:57.71#ibcon#read 6, iclass 22, count 0 2006.201.06:00:57.71#ibcon#end of sib2, iclass 22, count 0 2006.201.06:00:57.71#ibcon#*after write, iclass 22, count 0 2006.201.06:00:57.71#ibcon#*before return 0, iclass 22, count 0 2006.201.06:00:57.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:00:57.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:00:57.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.06:00:57.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.06:00:57.71$vck44/valo=6,814.99 2006.201.06:00:57.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.06:00:57.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.06:00:57.71#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:57.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:00:57.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:00:57.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:00:57.71#ibcon#enter wrdev, iclass 24, count 0 2006.201.06:00:57.71#ibcon#first serial, iclass 24, count 0 2006.201.06:00:57.71#ibcon#enter sib2, iclass 24, count 0 2006.201.06:00:57.71#ibcon#flushed, iclass 24, count 0 2006.201.06:00:57.71#ibcon#about to write, iclass 24, count 0 2006.201.06:00:57.71#ibcon#wrote, iclass 24, count 0 2006.201.06:00:57.71#ibcon#about to read 3, iclass 24, count 0 2006.201.06:00:57.73#ibcon#read 3, iclass 24, count 0 2006.201.06:00:57.73#ibcon#about to read 4, iclass 24, count 0 2006.201.06:00:57.73#ibcon#read 4, iclass 24, count 0 2006.201.06:00:57.73#ibcon#about to read 5, iclass 24, count 0 2006.201.06:00:57.73#ibcon#read 5, iclass 24, count 0 2006.201.06:00:57.73#ibcon#about to read 6, iclass 24, count 0 2006.201.06:00:57.73#ibcon#read 6, iclass 24, count 0 2006.201.06:00:57.73#ibcon#end of sib2, iclass 24, count 0 2006.201.06:00:57.73#ibcon#*mode == 0, iclass 24, count 0 2006.201.06:00:57.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.06:00:57.73#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.06:00:57.73#ibcon#*before write, iclass 24, count 0 2006.201.06:00:57.73#ibcon#enter sib2, iclass 24, count 0 2006.201.06:00:57.73#ibcon#flushed, iclass 24, count 0 2006.201.06:00:57.73#ibcon#about to write, iclass 24, count 0 2006.201.06:00:57.73#ibcon#wrote, iclass 24, count 0 2006.201.06:00:57.73#ibcon#about to read 3, iclass 24, count 0 2006.201.06:00:57.77#ibcon#read 3, iclass 24, count 0 2006.201.06:00:57.77#ibcon#about to read 4, iclass 24, count 0 2006.201.06:00:57.77#ibcon#read 4, iclass 24, count 0 2006.201.06:00:57.77#ibcon#about to read 5, iclass 24, count 0 2006.201.06:00:57.77#ibcon#read 5, iclass 24, count 0 2006.201.06:00:57.77#ibcon#about to read 6, iclass 24, count 0 2006.201.06:00:57.77#ibcon#read 6, iclass 24, count 0 2006.201.06:00:57.77#ibcon#end of sib2, iclass 24, count 0 2006.201.06:00:57.77#ibcon#*after write, iclass 24, count 0 2006.201.06:00:57.77#ibcon#*before return 0, iclass 24, count 0 2006.201.06:00:57.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:00:57.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:00:57.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.06:00:57.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.06:00:57.77$vck44/va=6,5 2006.201.06:00:57.77#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.06:00:57.77#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.06:00:57.77#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:57.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:00:57.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:00:57.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:00:57.83#ibcon#enter wrdev, iclass 26, count 2 2006.201.06:00:57.83#ibcon#first serial, iclass 26, count 2 2006.201.06:00:57.83#ibcon#enter sib2, iclass 26, count 2 2006.201.06:00:57.83#ibcon#flushed, iclass 26, count 2 2006.201.06:00:57.83#ibcon#about to write, iclass 26, count 2 2006.201.06:00:57.83#ibcon#wrote, iclass 26, count 2 2006.201.06:00:57.83#ibcon#about to read 3, iclass 26, count 2 2006.201.06:00:57.85#ibcon#read 3, iclass 26, count 2 2006.201.06:00:57.85#ibcon#about to read 4, iclass 26, count 2 2006.201.06:00:57.85#ibcon#read 4, iclass 26, count 2 2006.201.06:00:57.85#ibcon#about to read 5, iclass 26, count 2 2006.201.06:00:57.85#ibcon#read 5, iclass 26, count 2 2006.201.06:00:57.85#ibcon#about to read 6, iclass 26, count 2 2006.201.06:00:57.85#ibcon#read 6, iclass 26, count 2 2006.201.06:00:57.85#ibcon#end of sib2, iclass 26, count 2 2006.201.06:00:57.85#ibcon#*mode == 0, iclass 26, count 2 2006.201.06:00:57.85#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.06:00:57.85#ibcon#[25=AT06-05\r\n] 2006.201.06:00:57.85#ibcon#*before write, iclass 26, count 2 2006.201.06:00:57.85#ibcon#enter sib2, iclass 26, count 2 2006.201.06:00:57.85#ibcon#flushed, iclass 26, count 2 2006.201.06:00:57.85#ibcon#about to write, iclass 26, count 2 2006.201.06:00:57.85#ibcon#wrote, iclass 26, count 2 2006.201.06:00:57.85#ibcon#about to read 3, iclass 26, count 2 2006.201.06:00:57.88#ibcon#read 3, iclass 26, count 2 2006.201.06:00:57.88#ibcon#about to read 4, iclass 26, count 2 2006.201.06:00:57.88#ibcon#read 4, iclass 26, count 2 2006.201.06:00:57.88#ibcon#about to read 5, iclass 26, count 2 2006.201.06:00:57.88#ibcon#read 5, iclass 26, count 2 2006.201.06:00:57.88#ibcon#about to read 6, iclass 26, count 2 2006.201.06:00:57.88#ibcon#read 6, iclass 26, count 2 2006.201.06:00:57.88#ibcon#end of sib2, iclass 26, count 2 2006.201.06:00:57.88#ibcon#*after write, iclass 26, count 2 2006.201.06:00:57.88#ibcon#*before return 0, iclass 26, count 2 2006.201.06:00:57.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:00:57.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:00:57.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.06:00:57.88#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:57.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:00:58.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:00:58.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:00:58.00#ibcon#enter wrdev, iclass 26, count 0 2006.201.06:00:58.00#ibcon#first serial, iclass 26, count 0 2006.201.06:00:58.00#ibcon#enter sib2, iclass 26, count 0 2006.201.06:00:58.00#ibcon#flushed, iclass 26, count 0 2006.201.06:00:58.00#ibcon#about to write, iclass 26, count 0 2006.201.06:00:58.00#ibcon#wrote, iclass 26, count 0 2006.201.06:00:58.00#ibcon#about to read 3, iclass 26, count 0 2006.201.06:00:58.02#ibcon#read 3, iclass 26, count 0 2006.201.06:00:58.02#ibcon#about to read 4, iclass 26, count 0 2006.201.06:00:58.02#ibcon#read 4, iclass 26, count 0 2006.201.06:00:58.02#ibcon#about to read 5, iclass 26, count 0 2006.201.06:00:58.02#ibcon#read 5, iclass 26, count 0 2006.201.06:00:58.02#ibcon#about to read 6, iclass 26, count 0 2006.201.06:00:58.02#ibcon#read 6, iclass 26, count 0 2006.201.06:00:58.02#ibcon#end of sib2, iclass 26, count 0 2006.201.06:00:58.02#ibcon#*mode == 0, iclass 26, count 0 2006.201.06:00:58.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.06:00:58.02#ibcon#[25=USB\r\n] 2006.201.06:00:58.02#ibcon#*before write, iclass 26, count 0 2006.201.06:00:58.02#ibcon#enter sib2, iclass 26, count 0 2006.201.06:00:58.02#ibcon#flushed, iclass 26, count 0 2006.201.06:00:58.02#ibcon#about to write, iclass 26, count 0 2006.201.06:00:58.02#ibcon#wrote, iclass 26, count 0 2006.201.06:00:58.02#ibcon#about to read 3, iclass 26, count 0 2006.201.06:00:58.05#ibcon#read 3, iclass 26, count 0 2006.201.06:00:58.05#ibcon#about to read 4, iclass 26, count 0 2006.201.06:00:58.05#ibcon#read 4, iclass 26, count 0 2006.201.06:00:58.05#ibcon#about to read 5, iclass 26, count 0 2006.201.06:00:58.05#ibcon#read 5, iclass 26, count 0 2006.201.06:00:58.05#ibcon#about to read 6, iclass 26, count 0 2006.201.06:00:58.05#ibcon#read 6, iclass 26, count 0 2006.201.06:00:58.05#ibcon#end of sib2, iclass 26, count 0 2006.201.06:00:58.05#ibcon#*after write, iclass 26, count 0 2006.201.06:00:58.05#ibcon#*before return 0, iclass 26, count 0 2006.201.06:00:58.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:00:58.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:00:58.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.06:00:58.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.06:00:58.05$vck44/valo=7,864.99 2006.201.06:00:58.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.06:00:58.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.06:00:58.05#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:58.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:00:58.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:00:58.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:00:58.05#ibcon#enter wrdev, iclass 28, count 0 2006.201.06:00:58.05#ibcon#first serial, iclass 28, count 0 2006.201.06:00:58.05#ibcon#enter sib2, iclass 28, count 0 2006.201.06:00:58.05#ibcon#flushed, iclass 28, count 0 2006.201.06:00:58.05#ibcon#about to write, iclass 28, count 0 2006.201.06:00:58.05#ibcon#wrote, iclass 28, count 0 2006.201.06:00:58.05#ibcon#about to read 3, iclass 28, count 0 2006.201.06:00:58.07#ibcon#read 3, iclass 28, count 0 2006.201.06:00:58.07#ibcon#about to read 4, iclass 28, count 0 2006.201.06:00:58.07#ibcon#read 4, iclass 28, count 0 2006.201.06:00:58.07#ibcon#about to read 5, iclass 28, count 0 2006.201.06:00:58.07#ibcon#read 5, iclass 28, count 0 2006.201.06:00:58.07#ibcon#about to read 6, iclass 28, count 0 2006.201.06:00:58.07#ibcon#read 6, iclass 28, count 0 2006.201.06:00:58.07#ibcon#end of sib2, iclass 28, count 0 2006.201.06:00:58.07#ibcon#*mode == 0, iclass 28, count 0 2006.201.06:00:58.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.06:00:58.07#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.06:00:58.07#ibcon#*before write, iclass 28, count 0 2006.201.06:00:58.07#ibcon#enter sib2, iclass 28, count 0 2006.201.06:00:58.07#ibcon#flushed, iclass 28, count 0 2006.201.06:00:58.07#ibcon#about to write, iclass 28, count 0 2006.201.06:00:58.07#ibcon#wrote, iclass 28, count 0 2006.201.06:00:58.07#ibcon#about to read 3, iclass 28, count 0 2006.201.06:00:58.11#ibcon#read 3, iclass 28, count 0 2006.201.06:00:58.11#ibcon#about to read 4, iclass 28, count 0 2006.201.06:00:58.11#ibcon#read 4, iclass 28, count 0 2006.201.06:00:58.11#ibcon#about to read 5, iclass 28, count 0 2006.201.06:00:58.11#ibcon#read 5, iclass 28, count 0 2006.201.06:00:58.11#ibcon#about to read 6, iclass 28, count 0 2006.201.06:00:58.11#ibcon#read 6, iclass 28, count 0 2006.201.06:00:58.11#ibcon#end of sib2, iclass 28, count 0 2006.201.06:00:58.11#ibcon#*after write, iclass 28, count 0 2006.201.06:00:58.11#ibcon#*before return 0, iclass 28, count 0 2006.201.06:00:58.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:00:58.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:00:58.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.06:00:58.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.06:00:58.11$vck44/va=7,5 2006.201.06:00:58.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.06:00:58.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.06:00:58.11#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:58.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:00:58.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:00:58.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:00:58.17#ibcon#enter wrdev, iclass 30, count 2 2006.201.06:00:58.17#ibcon#first serial, iclass 30, count 2 2006.201.06:00:58.17#ibcon#enter sib2, iclass 30, count 2 2006.201.06:00:58.17#ibcon#flushed, iclass 30, count 2 2006.201.06:00:58.17#ibcon#about to write, iclass 30, count 2 2006.201.06:00:58.17#ibcon#wrote, iclass 30, count 2 2006.201.06:00:58.17#ibcon#about to read 3, iclass 30, count 2 2006.201.06:00:58.19#ibcon#read 3, iclass 30, count 2 2006.201.06:00:58.19#ibcon#about to read 4, iclass 30, count 2 2006.201.06:00:58.19#ibcon#read 4, iclass 30, count 2 2006.201.06:00:58.19#ibcon#about to read 5, iclass 30, count 2 2006.201.06:00:58.19#ibcon#read 5, iclass 30, count 2 2006.201.06:00:58.19#ibcon#about to read 6, iclass 30, count 2 2006.201.06:00:58.19#ibcon#read 6, iclass 30, count 2 2006.201.06:00:58.19#ibcon#end of sib2, iclass 30, count 2 2006.201.06:00:58.19#ibcon#*mode == 0, iclass 30, count 2 2006.201.06:00:58.19#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.06:00:58.19#ibcon#[25=AT07-05\r\n] 2006.201.06:00:58.19#ibcon#*before write, iclass 30, count 2 2006.201.06:00:58.19#ibcon#enter sib2, iclass 30, count 2 2006.201.06:00:58.19#ibcon#flushed, iclass 30, count 2 2006.201.06:00:58.19#ibcon#about to write, iclass 30, count 2 2006.201.06:00:58.19#ibcon#wrote, iclass 30, count 2 2006.201.06:00:58.19#ibcon#about to read 3, iclass 30, count 2 2006.201.06:00:58.22#ibcon#read 3, iclass 30, count 2 2006.201.06:00:58.22#ibcon#about to read 4, iclass 30, count 2 2006.201.06:00:58.22#ibcon#read 4, iclass 30, count 2 2006.201.06:00:58.22#ibcon#about to read 5, iclass 30, count 2 2006.201.06:00:58.22#ibcon#read 5, iclass 30, count 2 2006.201.06:00:58.22#ibcon#about to read 6, iclass 30, count 2 2006.201.06:00:58.22#ibcon#read 6, iclass 30, count 2 2006.201.06:00:58.22#ibcon#end of sib2, iclass 30, count 2 2006.201.06:00:58.22#ibcon#*after write, iclass 30, count 2 2006.201.06:00:58.22#ibcon#*before return 0, iclass 30, count 2 2006.201.06:00:58.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:00:58.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:00:58.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.06:00:58.22#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:58.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:00:58.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:00:58.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:00:58.34#ibcon#enter wrdev, iclass 30, count 0 2006.201.06:00:58.34#ibcon#first serial, iclass 30, count 0 2006.201.06:00:58.34#ibcon#enter sib2, iclass 30, count 0 2006.201.06:00:58.34#ibcon#flushed, iclass 30, count 0 2006.201.06:00:58.34#ibcon#about to write, iclass 30, count 0 2006.201.06:00:58.34#ibcon#wrote, iclass 30, count 0 2006.201.06:00:58.34#ibcon#about to read 3, iclass 30, count 0 2006.201.06:00:58.36#ibcon#read 3, iclass 30, count 0 2006.201.06:00:58.36#ibcon#about to read 4, iclass 30, count 0 2006.201.06:00:58.36#ibcon#read 4, iclass 30, count 0 2006.201.06:00:58.36#ibcon#about to read 5, iclass 30, count 0 2006.201.06:00:58.36#ibcon#read 5, iclass 30, count 0 2006.201.06:00:58.36#ibcon#about to read 6, iclass 30, count 0 2006.201.06:00:58.36#ibcon#read 6, iclass 30, count 0 2006.201.06:00:58.36#ibcon#end of sib2, iclass 30, count 0 2006.201.06:00:58.36#ibcon#*mode == 0, iclass 30, count 0 2006.201.06:00:58.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.06:00:58.36#ibcon#[25=USB\r\n] 2006.201.06:00:58.36#ibcon#*before write, iclass 30, count 0 2006.201.06:00:58.36#ibcon#enter sib2, iclass 30, count 0 2006.201.06:00:58.36#ibcon#flushed, iclass 30, count 0 2006.201.06:00:58.36#ibcon#about to write, iclass 30, count 0 2006.201.06:00:58.36#ibcon#wrote, iclass 30, count 0 2006.201.06:00:58.36#ibcon#about to read 3, iclass 30, count 0 2006.201.06:00:58.39#ibcon#read 3, iclass 30, count 0 2006.201.06:00:58.39#ibcon#about to read 4, iclass 30, count 0 2006.201.06:00:58.39#ibcon#read 4, iclass 30, count 0 2006.201.06:00:58.39#ibcon#about to read 5, iclass 30, count 0 2006.201.06:00:58.39#ibcon#read 5, iclass 30, count 0 2006.201.06:00:58.39#ibcon#about to read 6, iclass 30, count 0 2006.201.06:00:58.39#ibcon#read 6, iclass 30, count 0 2006.201.06:00:58.39#ibcon#end of sib2, iclass 30, count 0 2006.201.06:00:58.39#ibcon#*after write, iclass 30, count 0 2006.201.06:00:58.39#ibcon#*before return 0, iclass 30, count 0 2006.201.06:00:58.39#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:00:58.39#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:00:58.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.06:00:58.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.06:00:58.39$vck44/valo=8,884.99 2006.201.06:00:58.39#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.06:00:58.39#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.06:00:58.39#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:58.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:00:58.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:00:58.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:00:58.39#ibcon#enter wrdev, iclass 32, count 0 2006.201.06:00:58.39#ibcon#first serial, iclass 32, count 0 2006.201.06:00:58.39#ibcon#enter sib2, iclass 32, count 0 2006.201.06:00:58.39#ibcon#flushed, iclass 32, count 0 2006.201.06:00:58.39#ibcon#about to write, iclass 32, count 0 2006.201.06:00:58.39#ibcon#wrote, iclass 32, count 0 2006.201.06:00:58.39#ibcon#about to read 3, iclass 32, count 0 2006.201.06:00:58.41#ibcon#read 3, iclass 32, count 0 2006.201.06:00:58.41#ibcon#about to read 4, iclass 32, count 0 2006.201.06:00:58.41#ibcon#read 4, iclass 32, count 0 2006.201.06:00:58.41#ibcon#about to read 5, iclass 32, count 0 2006.201.06:00:58.41#ibcon#read 5, iclass 32, count 0 2006.201.06:00:58.41#ibcon#about to read 6, iclass 32, count 0 2006.201.06:00:58.41#ibcon#read 6, iclass 32, count 0 2006.201.06:00:58.41#ibcon#end of sib2, iclass 32, count 0 2006.201.06:00:58.41#ibcon#*mode == 0, iclass 32, count 0 2006.201.06:00:58.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.06:00:58.41#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.06:00:58.41#ibcon#*before write, iclass 32, count 0 2006.201.06:00:58.41#ibcon#enter sib2, iclass 32, count 0 2006.201.06:00:58.41#ibcon#flushed, iclass 32, count 0 2006.201.06:00:58.41#ibcon#about to write, iclass 32, count 0 2006.201.06:00:58.41#ibcon#wrote, iclass 32, count 0 2006.201.06:00:58.41#ibcon#about to read 3, iclass 32, count 0 2006.201.06:00:58.45#ibcon#read 3, iclass 32, count 0 2006.201.06:00:58.45#ibcon#about to read 4, iclass 32, count 0 2006.201.06:00:58.45#ibcon#read 4, iclass 32, count 0 2006.201.06:00:58.45#ibcon#about to read 5, iclass 32, count 0 2006.201.06:00:58.45#ibcon#read 5, iclass 32, count 0 2006.201.06:00:58.45#ibcon#about to read 6, iclass 32, count 0 2006.201.06:00:58.45#ibcon#read 6, iclass 32, count 0 2006.201.06:00:58.45#ibcon#end of sib2, iclass 32, count 0 2006.201.06:00:58.45#ibcon#*after write, iclass 32, count 0 2006.201.06:00:58.45#ibcon#*before return 0, iclass 32, count 0 2006.201.06:00:58.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:00:58.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:00:58.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.06:00:58.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.06:00:58.45$vck44/va=8,4 2006.201.06:00:58.45#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.06:00:58.45#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.06:00:58.45#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:58.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:00:58.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:00:58.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:00:58.51#ibcon#enter wrdev, iclass 34, count 2 2006.201.06:00:58.51#ibcon#first serial, iclass 34, count 2 2006.201.06:00:58.51#ibcon#enter sib2, iclass 34, count 2 2006.201.06:00:58.51#ibcon#flushed, iclass 34, count 2 2006.201.06:00:58.51#ibcon#about to write, iclass 34, count 2 2006.201.06:00:58.51#ibcon#wrote, iclass 34, count 2 2006.201.06:00:58.51#ibcon#about to read 3, iclass 34, count 2 2006.201.06:00:58.53#ibcon#read 3, iclass 34, count 2 2006.201.06:00:58.53#ibcon#about to read 4, iclass 34, count 2 2006.201.06:00:58.53#ibcon#read 4, iclass 34, count 2 2006.201.06:00:58.53#ibcon#about to read 5, iclass 34, count 2 2006.201.06:00:58.53#ibcon#read 5, iclass 34, count 2 2006.201.06:00:58.53#ibcon#about to read 6, iclass 34, count 2 2006.201.06:00:58.53#ibcon#read 6, iclass 34, count 2 2006.201.06:00:58.53#ibcon#end of sib2, iclass 34, count 2 2006.201.06:00:58.53#ibcon#*mode == 0, iclass 34, count 2 2006.201.06:00:58.53#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.06:00:58.53#ibcon#[25=AT08-04\r\n] 2006.201.06:00:58.53#ibcon#*before write, iclass 34, count 2 2006.201.06:00:58.53#ibcon#enter sib2, iclass 34, count 2 2006.201.06:00:58.53#ibcon#flushed, iclass 34, count 2 2006.201.06:00:58.53#ibcon#about to write, iclass 34, count 2 2006.201.06:00:58.53#ibcon#wrote, iclass 34, count 2 2006.201.06:00:58.53#ibcon#about to read 3, iclass 34, count 2 2006.201.06:00:58.56#ibcon#read 3, iclass 34, count 2 2006.201.06:00:58.56#ibcon#about to read 4, iclass 34, count 2 2006.201.06:00:58.56#ibcon#read 4, iclass 34, count 2 2006.201.06:00:58.56#ibcon#about to read 5, iclass 34, count 2 2006.201.06:00:58.56#ibcon#read 5, iclass 34, count 2 2006.201.06:00:58.56#ibcon#about to read 6, iclass 34, count 2 2006.201.06:00:58.56#ibcon#read 6, iclass 34, count 2 2006.201.06:00:58.56#ibcon#end of sib2, iclass 34, count 2 2006.201.06:00:58.56#ibcon#*after write, iclass 34, count 2 2006.201.06:00:58.56#ibcon#*before return 0, iclass 34, count 2 2006.201.06:00:58.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:00:58.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:00:58.56#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.06:00:58.56#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:58.56#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:00:58.68#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:00:58.68#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:00:58.68#ibcon#enter wrdev, iclass 34, count 0 2006.201.06:00:58.68#ibcon#first serial, iclass 34, count 0 2006.201.06:00:58.68#ibcon#enter sib2, iclass 34, count 0 2006.201.06:00:58.68#ibcon#flushed, iclass 34, count 0 2006.201.06:00:58.68#ibcon#about to write, iclass 34, count 0 2006.201.06:00:58.68#ibcon#wrote, iclass 34, count 0 2006.201.06:00:58.68#ibcon#about to read 3, iclass 34, count 0 2006.201.06:00:58.70#ibcon#read 3, iclass 34, count 0 2006.201.06:00:58.70#ibcon#about to read 4, iclass 34, count 0 2006.201.06:00:58.70#ibcon#read 4, iclass 34, count 0 2006.201.06:00:58.70#ibcon#about to read 5, iclass 34, count 0 2006.201.06:00:58.70#ibcon#read 5, iclass 34, count 0 2006.201.06:00:58.70#ibcon#about to read 6, iclass 34, count 0 2006.201.06:00:58.70#ibcon#read 6, iclass 34, count 0 2006.201.06:00:58.70#ibcon#end of sib2, iclass 34, count 0 2006.201.06:00:58.70#ibcon#*mode == 0, iclass 34, count 0 2006.201.06:00:58.70#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.06:00:58.70#ibcon#[25=USB\r\n] 2006.201.06:00:58.70#ibcon#*before write, iclass 34, count 0 2006.201.06:00:58.70#ibcon#enter sib2, iclass 34, count 0 2006.201.06:00:58.70#ibcon#flushed, iclass 34, count 0 2006.201.06:00:58.70#ibcon#about to write, iclass 34, count 0 2006.201.06:00:58.70#ibcon#wrote, iclass 34, count 0 2006.201.06:00:58.70#ibcon#about to read 3, iclass 34, count 0 2006.201.06:00:58.73#ibcon#read 3, iclass 34, count 0 2006.201.06:00:58.73#ibcon#about to read 4, iclass 34, count 0 2006.201.06:00:58.73#ibcon#read 4, iclass 34, count 0 2006.201.06:00:58.73#ibcon#about to read 5, iclass 34, count 0 2006.201.06:00:58.73#ibcon#read 5, iclass 34, count 0 2006.201.06:00:58.73#ibcon#about to read 6, iclass 34, count 0 2006.201.06:00:58.73#ibcon#read 6, iclass 34, count 0 2006.201.06:00:58.73#ibcon#end of sib2, iclass 34, count 0 2006.201.06:00:58.73#ibcon#*after write, iclass 34, count 0 2006.201.06:00:58.73#ibcon#*before return 0, iclass 34, count 0 2006.201.06:00:58.73#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:00:58.73#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:00:58.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.06:00:58.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.06:00:58.73$vck44/vblo=1,629.99 2006.201.06:00:58.73#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.06:00:58.73#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.06:00:58.73#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:58.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:00:58.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:00:58.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:00:58.73#ibcon#enter wrdev, iclass 36, count 0 2006.201.06:00:58.73#ibcon#first serial, iclass 36, count 0 2006.201.06:00:58.73#ibcon#enter sib2, iclass 36, count 0 2006.201.06:00:58.73#ibcon#flushed, iclass 36, count 0 2006.201.06:00:58.73#ibcon#about to write, iclass 36, count 0 2006.201.06:00:58.73#ibcon#wrote, iclass 36, count 0 2006.201.06:00:58.73#ibcon#about to read 3, iclass 36, count 0 2006.201.06:00:58.76#ibcon#read 3, iclass 36, count 0 2006.201.06:00:58.76#ibcon#about to read 4, iclass 36, count 0 2006.201.06:00:58.76#ibcon#read 4, iclass 36, count 0 2006.201.06:00:58.76#ibcon#about to read 5, iclass 36, count 0 2006.201.06:00:58.76#ibcon#read 5, iclass 36, count 0 2006.201.06:00:58.76#ibcon#about to read 6, iclass 36, count 0 2006.201.06:00:58.76#ibcon#read 6, iclass 36, count 0 2006.201.06:00:58.76#ibcon#end of sib2, iclass 36, count 0 2006.201.06:00:58.76#ibcon#*mode == 0, iclass 36, count 0 2006.201.06:00:58.76#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.06:00:58.76#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.06:00:58.76#ibcon#*before write, iclass 36, count 0 2006.201.06:00:58.76#ibcon#enter sib2, iclass 36, count 0 2006.201.06:00:58.76#ibcon#flushed, iclass 36, count 0 2006.201.06:00:58.76#ibcon#about to write, iclass 36, count 0 2006.201.06:00:58.76#ibcon#wrote, iclass 36, count 0 2006.201.06:00:58.76#ibcon#about to read 3, iclass 36, count 0 2006.201.06:00:58.80#ibcon#read 3, iclass 36, count 0 2006.201.06:00:58.80#ibcon#about to read 4, iclass 36, count 0 2006.201.06:00:58.80#ibcon#read 4, iclass 36, count 0 2006.201.06:00:58.80#ibcon#about to read 5, iclass 36, count 0 2006.201.06:00:58.80#ibcon#read 5, iclass 36, count 0 2006.201.06:00:58.80#ibcon#about to read 6, iclass 36, count 0 2006.201.06:00:58.80#ibcon#read 6, iclass 36, count 0 2006.201.06:00:58.80#ibcon#end of sib2, iclass 36, count 0 2006.201.06:00:58.80#ibcon#*after write, iclass 36, count 0 2006.201.06:00:58.80#ibcon#*before return 0, iclass 36, count 0 2006.201.06:00:58.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:00:58.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:00:58.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.06:00:58.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.06:00:58.80$vck44/vb=1,4 2006.201.06:00:58.80#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.06:00:58.80#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.06:00:58.80#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:58.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:00:58.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:00:58.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:00:58.80#ibcon#enter wrdev, iclass 38, count 2 2006.201.06:00:58.80#ibcon#first serial, iclass 38, count 2 2006.201.06:00:58.80#ibcon#enter sib2, iclass 38, count 2 2006.201.06:00:58.80#ibcon#flushed, iclass 38, count 2 2006.201.06:00:58.80#ibcon#about to write, iclass 38, count 2 2006.201.06:00:58.80#ibcon#wrote, iclass 38, count 2 2006.201.06:00:58.80#ibcon#about to read 3, iclass 38, count 2 2006.201.06:00:58.82#ibcon#read 3, iclass 38, count 2 2006.201.06:00:58.82#ibcon#about to read 4, iclass 38, count 2 2006.201.06:00:58.82#ibcon#read 4, iclass 38, count 2 2006.201.06:00:58.82#ibcon#about to read 5, iclass 38, count 2 2006.201.06:00:58.82#ibcon#read 5, iclass 38, count 2 2006.201.06:00:58.82#ibcon#about to read 6, iclass 38, count 2 2006.201.06:00:58.82#ibcon#read 6, iclass 38, count 2 2006.201.06:00:58.82#ibcon#end of sib2, iclass 38, count 2 2006.201.06:00:58.82#ibcon#*mode == 0, iclass 38, count 2 2006.201.06:00:58.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.06:00:58.82#ibcon#[27=AT01-04\r\n] 2006.201.06:00:58.82#ibcon#*before write, iclass 38, count 2 2006.201.06:00:58.82#ibcon#enter sib2, iclass 38, count 2 2006.201.06:00:58.82#ibcon#flushed, iclass 38, count 2 2006.201.06:00:58.82#ibcon#about to write, iclass 38, count 2 2006.201.06:00:58.82#ibcon#wrote, iclass 38, count 2 2006.201.06:00:58.82#ibcon#about to read 3, iclass 38, count 2 2006.201.06:00:58.85#ibcon#read 3, iclass 38, count 2 2006.201.06:00:58.85#ibcon#about to read 4, iclass 38, count 2 2006.201.06:00:58.85#ibcon#read 4, iclass 38, count 2 2006.201.06:00:58.85#ibcon#about to read 5, iclass 38, count 2 2006.201.06:00:58.85#ibcon#read 5, iclass 38, count 2 2006.201.06:00:58.85#ibcon#about to read 6, iclass 38, count 2 2006.201.06:00:58.85#ibcon#read 6, iclass 38, count 2 2006.201.06:00:58.85#ibcon#end of sib2, iclass 38, count 2 2006.201.06:00:58.85#ibcon#*after write, iclass 38, count 2 2006.201.06:00:58.85#ibcon#*before return 0, iclass 38, count 2 2006.201.06:00:58.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:00:58.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:00:58.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.06:00:58.85#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:58.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:00:58.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:00:58.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:00:58.97#ibcon#enter wrdev, iclass 38, count 0 2006.201.06:00:58.97#ibcon#first serial, iclass 38, count 0 2006.201.06:00:58.97#ibcon#enter sib2, iclass 38, count 0 2006.201.06:00:58.97#ibcon#flushed, iclass 38, count 0 2006.201.06:00:58.97#ibcon#about to write, iclass 38, count 0 2006.201.06:00:58.97#ibcon#wrote, iclass 38, count 0 2006.201.06:00:58.97#ibcon#about to read 3, iclass 38, count 0 2006.201.06:00:58.99#ibcon#read 3, iclass 38, count 0 2006.201.06:00:58.99#ibcon#about to read 4, iclass 38, count 0 2006.201.06:00:58.99#ibcon#read 4, iclass 38, count 0 2006.201.06:00:58.99#ibcon#about to read 5, iclass 38, count 0 2006.201.06:00:58.99#ibcon#read 5, iclass 38, count 0 2006.201.06:00:58.99#ibcon#about to read 6, iclass 38, count 0 2006.201.06:00:58.99#ibcon#read 6, iclass 38, count 0 2006.201.06:00:58.99#ibcon#end of sib2, iclass 38, count 0 2006.201.06:00:58.99#ibcon#*mode == 0, iclass 38, count 0 2006.201.06:00:58.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.06:00:58.99#ibcon#[27=USB\r\n] 2006.201.06:00:58.99#ibcon#*before write, iclass 38, count 0 2006.201.06:00:58.99#ibcon#enter sib2, iclass 38, count 0 2006.201.06:00:58.99#ibcon#flushed, iclass 38, count 0 2006.201.06:00:58.99#ibcon#about to write, iclass 38, count 0 2006.201.06:00:58.99#ibcon#wrote, iclass 38, count 0 2006.201.06:00:58.99#ibcon#about to read 3, iclass 38, count 0 2006.201.06:00:59.02#ibcon#read 3, iclass 38, count 0 2006.201.06:00:59.02#ibcon#about to read 4, iclass 38, count 0 2006.201.06:00:59.02#ibcon#read 4, iclass 38, count 0 2006.201.06:00:59.02#ibcon#about to read 5, iclass 38, count 0 2006.201.06:00:59.02#ibcon#read 5, iclass 38, count 0 2006.201.06:00:59.02#ibcon#about to read 6, iclass 38, count 0 2006.201.06:00:59.02#ibcon#read 6, iclass 38, count 0 2006.201.06:00:59.02#ibcon#end of sib2, iclass 38, count 0 2006.201.06:00:59.02#ibcon#*after write, iclass 38, count 0 2006.201.06:00:59.02#ibcon#*before return 0, iclass 38, count 0 2006.201.06:00:59.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:00:59.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:00:59.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.06:00:59.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.06:00:59.02$vck44/vblo=2,634.99 2006.201.06:00:59.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.06:00:59.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.06:00:59.02#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:59.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:59.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:59.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:59.02#ibcon#enter wrdev, iclass 40, count 0 2006.201.06:00:59.02#ibcon#first serial, iclass 40, count 0 2006.201.06:00:59.02#ibcon#enter sib2, iclass 40, count 0 2006.201.06:00:59.02#ibcon#flushed, iclass 40, count 0 2006.201.06:00:59.02#ibcon#about to write, iclass 40, count 0 2006.201.06:00:59.02#ibcon#wrote, iclass 40, count 0 2006.201.06:00:59.02#ibcon#about to read 3, iclass 40, count 0 2006.201.06:00:59.04#ibcon#read 3, iclass 40, count 0 2006.201.06:00:59.04#ibcon#about to read 4, iclass 40, count 0 2006.201.06:00:59.04#ibcon#read 4, iclass 40, count 0 2006.201.06:00:59.04#ibcon#about to read 5, iclass 40, count 0 2006.201.06:00:59.04#ibcon#read 5, iclass 40, count 0 2006.201.06:00:59.04#ibcon#about to read 6, iclass 40, count 0 2006.201.06:00:59.04#ibcon#read 6, iclass 40, count 0 2006.201.06:00:59.04#ibcon#end of sib2, iclass 40, count 0 2006.201.06:00:59.04#ibcon#*mode == 0, iclass 40, count 0 2006.201.06:00:59.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.06:00:59.04#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.06:00:59.04#ibcon#*before write, iclass 40, count 0 2006.201.06:00:59.04#ibcon#enter sib2, iclass 40, count 0 2006.201.06:00:59.04#ibcon#flushed, iclass 40, count 0 2006.201.06:00:59.04#ibcon#about to write, iclass 40, count 0 2006.201.06:00:59.04#ibcon#wrote, iclass 40, count 0 2006.201.06:00:59.04#ibcon#about to read 3, iclass 40, count 0 2006.201.06:00:59.08#ibcon#read 3, iclass 40, count 0 2006.201.06:00:59.08#ibcon#about to read 4, iclass 40, count 0 2006.201.06:00:59.08#ibcon#read 4, iclass 40, count 0 2006.201.06:00:59.08#ibcon#about to read 5, iclass 40, count 0 2006.201.06:00:59.08#ibcon#read 5, iclass 40, count 0 2006.201.06:00:59.08#ibcon#about to read 6, iclass 40, count 0 2006.201.06:00:59.08#ibcon#read 6, iclass 40, count 0 2006.201.06:00:59.08#ibcon#end of sib2, iclass 40, count 0 2006.201.06:00:59.08#ibcon#*after write, iclass 40, count 0 2006.201.06:00:59.08#ibcon#*before return 0, iclass 40, count 0 2006.201.06:00:59.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:59.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:00:59.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.06:00:59.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.06:00:59.08$vck44/vb=2,5 2006.201.06:00:59.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.06:00:59.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.06:00:59.08#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:59.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:59.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:59.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:59.14#ibcon#enter wrdev, iclass 4, count 2 2006.201.06:00:59.14#ibcon#first serial, iclass 4, count 2 2006.201.06:00:59.14#ibcon#enter sib2, iclass 4, count 2 2006.201.06:00:59.14#ibcon#flushed, iclass 4, count 2 2006.201.06:00:59.14#ibcon#about to write, iclass 4, count 2 2006.201.06:00:59.14#ibcon#wrote, iclass 4, count 2 2006.201.06:00:59.14#ibcon#about to read 3, iclass 4, count 2 2006.201.06:00:59.16#ibcon#read 3, iclass 4, count 2 2006.201.06:00:59.16#ibcon#about to read 4, iclass 4, count 2 2006.201.06:00:59.16#ibcon#read 4, iclass 4, count 2 2006.201.06:00:59.16#ibcon#about to read 5, iclass 4, count 2 2006.201.06:00:59.16#ibcon#read 5, iclass 4, count 2 2006.201.06:00:59.16#ibcon#about to read 6, iclass 4, count 2 2006.201.06:00:59.16#ibcon#read 6, iclass 4, count 2 2006.201.06:00:59.16#ibcon#end of sib2, iclass 4, count 2 2006.201.06:00:59.16#ibcon#*mode == 0, iclass 4, count 2 2006.201.06:00:59.16#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.06:00:59.16#ibcon#[27=AT02-05\r\n] 2006.201.06:00:59.16#ibcon#*before write, iclass 4, count 2 2006.201.06:00:59.16#ibcon#enter sib2, iclass 4, count 2 2006.201.06:00:59.16#ibcon#flushed, iclass 4, count 2 2006.201.06:00:59.16#ibcon#about to write, iclass 4, count 2 2006.201.06:00:59.16#ibcon#wrote, iclass 4, count 2 2006.201.06:00:59.16#ibcon#about to read 3, iclass 4, count 2 2006.201.06:00:59.19#ibcon#read 3, iclass 4, count 2 2006.201.06:00:59.19#ibcon#about to read 4, iclass 4, count 2 2006.201.06:00:59.19#ibcon#read 4, iclass 4, count 2 2006.201.06:00:59.19#ibcon#about to read 5, iclass 4, count 2 2006.201.06:00:59.19#ibcon#read 5, iclass 4, count 2 2006.201.06:00:59.19#ibcon#about to read 6, iclass 4, count 2 2006.201.06:00:59.19#ibcon#read 6, iclass 4, count 2 2006.201.06:00:59.19#ibcon#end of sib2, iclass 4, count 2 2006.201.06:00:59.19#ibcon#*after write, iclass 4, count 2 2006.201.06:00:59.19#ibcon#*before return 0, iclass 4, count 2 2006.201.06:00:59.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:59.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:00:59.19#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.06:00:59.19#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:59.19#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:59.31#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:59.31#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:59.31#ibcon#enter wrdev, iclass 4, count 0 2006.201.06:00:59.31#ibcon#first serial, iclass 4, count 0 2006.201.06:00:59.31#ibcon#enter sib2, iclass 4, count 0 2006.201.06:00:59.31#ibcon#flushed, iclass 4, count 0 2006.201.06:00:59.31#ibcon#about to write, iclass 4, count 0 2006.201.06:00:59.31#ibcon#wrote, iclass 4, count 0 2006.201.06:00:59.31#ibcon#about to read 3, iclass 4, count 0 2006.201.06:00:59.33#ibcon#read 3, iclass 4, count 0 2006.201.06:00:59.33#ibcon#about to read 4, iclass 4, count 0 2006.201.06:00:59.33#ibcon#read 4, iclass 4, count 0 2006.201.06:00:59.33#ibcon#about to read 5, iclass 4, count 0 2006.201.06:00:59.33#ibcon#read 5, iclass 4, count 0 2006.201.06:00:59.33#ibcon#about to read 6, iclass 4, count 0 2006.201.06:00:59.33#ibcon#read 6, iclass 4, count 0 2006.201.06:00:59.33#ibcon#end of sib2, iclass 4, count 0 2006.201.06:00:59.33#ibcon#*mode == 0, iclass 4, count 0 2006.201.06:00:59.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.06:00:59.33#ibcon#[27=USB\r\n] 2006.201.06:00:59.33#ibcon#*before write, iclass 4, count 0 2006.201.06:00:59.33#ibcon#enter sib2, iclass 4, count 0 2006.201.06:00:59.33#ibcon#flushed, iclass 4, count 0 2006.201.06:00:59.33#ibcon#about to write, iclass 4, count 0 2006.201.06:00:59.33#ibcon#wrote, iclass 4, count 0 2006.201.06:00:59.33#ibcon#about to read 3, iclass 4, count 0 2006.201.06:00:59.36#ibcon#read 3, iclass 4, count 0 2006.201.06:00:59.36#ibcon#about to read 4, iclass 4, count 0 2006.201.06:00:59.36#ibcon#read 4, iclass 4, count 0 2006.201.06:00:59.36#ibcon#about to read 5, iclass 4, count 0 2006.201.06:00:59.36#ibcon#read 5, iclass 4, count 0 2006.201.06:00:59.36#ibcon#about to read 6, iclass 4, count 0 2006.201.06:00:59.36#ibcon#read 6, iclass 4, count 0 2006.201.06:00:59.36#ibcon#end of sib2, iclass 4, count 0 2006.201.06:00:59.36#ibcon#*after write, iclass 4, count 0 2006.201.06:00:59.36#ibcon#*before return 0, iclass 4, count 0 2006.201.06:00:59.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:59.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:00:59.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.06:00:59.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.06:00:59.36$vck44/vblo=3,649.99 2006.201.06:00:59.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.06:00:59.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.06:00:59.36#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:59.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:59.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:59.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:59.36#ibcon#enter wrdev, iclass 6, count 0 2006.201.06:00:59.36#ibcon#first serial, iclass 6, count 0 2006.201.06:00:59.36#ibcon#enter sib2, iclass 6, count 0 2006.201.06:00:59.36#ibcon#flushed, iclass 6, count 0 2006.201.06:00:59.36#ibcon#about to write, iclass 6, count 0 2006.201.06:00:59.36#ibcon#wrote, iclass 6, count 0 2006.201.06:00:59.36#ibcon#about to read 3, iclass 6, count 0 2006.201.06:00:59.38#ibcon#read 3, iclass 6, count 0 2006.201.06:00:59.38#ibcon#about to read 4, iclass 6, count 0 2006.201.06:00:59.38#ibcon#read 4, iclass 6, count 0 2006.201.06:00:59.38#ibcon#about to read 5, iclass 6, count 0 2006.201.06:00:59.38#ibcon#read 5, iclass 6, count 0 2006.201.06:00:59.38#ibcon#about to read 6, iclass 6, count 0 2006.201.06:00:59.38#ibcon#read 6, iclass 6, count 0 2006.201.06:00:59.38#ibcon#end of sib2, iclass 6, count 0 2006.201.06:00:59.38#ibcon#*mode == 0, iclass 6, count 0 2006.201.06:00:59.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.06:00:59.38#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.06:00:59.38#ibcon#*before write, iclass 6, count 0 2006.201.06:00:59.38#ibcon#enter sib2, iclass 6, count 0 2006.201.06:00:59.38#ibcon#flushed, iclass 6, count 0 2006.201.06:00:59.38#ibcon#about to write, iclass 6, count 0 2006.201.06:00:59.38#ibcon#wrote, iclass 6, count 0 2006.201.06:00:59.38#ibcon#about to read 3, iclass 6, count 0 2006.201.06:00:59.42#ibcon#read 3, iclass 6, count 0 2006.201.06:00:59.42#ibcon#about to read 4, iclass 6, count 0 2006.201.06:00:59.42#ibcon#read 4, iclass 6, count 0 2006.201.06:00:59.42#ibcon#about to read 5, iclass 6, count 0 2006.201.06:00:59.42#ibcon#read 5, iclass 6, count 0 2006.201.06:00:59.42#ibcon#about to read 6, iclass 6, count 0 2006.201.06:00:59.42#ibcon#read 6, iclass 6, count 0 2006.201.06:00:59.42#ibcon#end of sib2, iclass 6, count 0 2006.201.06:00:59.42#ibcon#*after write, iclass 6, count 0 2006.201.06:00:59.42#ibcon#*before return 0, iclass 6, count 0 2006.201.06:00:59.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:59.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:00:59.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.06:00:59.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.06:00:59.42$vck44/vb=3,4 2006.201.06:00:59.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.06:00:59.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.06:00:59.42#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:59.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:59.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:59.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:59.48#ibcon#enter wrdev, iclass 10, count 2 2006.201.06:00:59.48#ibcon#first serial, iclass 10, count 2 2006.201.06:00:59.48#ibcon#enter sib2, iclass 10, count 2 2006.201.06:00:59.48#ibcon#flushed, iclass 10, count 2 2006.201.06:00:59.48#ibcon#about to write, iclass 10, count 2 2006.201.06:00:59.48#ibcon#wrote, iclass 10, count 2 2006.201.06:00:59.48#ibcon#about to read 3, iclass 10, count 2 2006.201.06:00:59.50#ibcon#read 3, iclass 10, count 2 2006.201.06:00:59.50#ibcon#about to read 4, iclass 10, count 2 2006.201.06:00:59.50#ibcon#read 4, iclass 10, count 2 2006.201.06:00:59.50#ibcon#about to read 5, iclass 10, count 2 2006.201.06:00:59.50#ibcon#read 5, iclass 10, count 2 2006.201.06:00:59.50#ibcon#about to read 6, iclass 10, count 2 2006.201.06:00:59.50#ibcon#read 6, iclass 10, count 2 2006.201.06:00:59.50#ibcon#end of sib2, iclass 10, count 2 2006.201.06:00:59.50#ibcon#*mode == 0, iclass 10, count 2 2006.201.06:00:59.50#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.06:00:59.50#ibcon#[27=AT03-04\r\n] 2006.201.06:00:59.50#ibcon#*before write, iclass 10, count 2 2006.201.06:00:59.50#ibcon#enter sib2, iclass 10, count 2 2006.201.06:00:59.50#ibcon#flushed, iclass 10, count 2 2006.201.06:00:59.50#ibcon#about to write, iclass 10, count 2 2006.201.06:00:59.50#ibcon#wrote, iclass 10, count 2 2006.201.06:00:59.50#ibcon#about to read 3, iclass 10, count 2 2006.201.06:00:59.53#ibcon#read 3, iclass 10, count 2 2006.201.06:00:59.53#ibcon#about to read 4, iclass 10, count 2 2006.201.06:00:59.53#ibcon#read 4, iclass 10, count 2 2006.201.06:00:59.53#ibcon#about to read 5, iclass 10, count 2 2006.201.06:00:59.53#ibcon#read 5, iclass 10, count 2 2006.201.06:00:59.53#ibcon#about to read 6, iclass 10, count 2 2006.201.06:00:59.53#ibcon#read 6, iclass 10, count 2 2006.201.06:00:59.53#ibcon#end of sib2, iclass 10, count 2 2006.201.06:00:59.53#ibcon#*after write, iclass 10, count 2 2006.201.06:00:59.53#ibcon#*before return 0, iclass 10, count 2 2006.201.06:00:59.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:59.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:00:59.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.06:00:59.53#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:59.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:59.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:59.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:59.65#ibcon#enter wrdev, iclass 10, count 0 2006.201.06:00:59.65#ibcon#first serial, iclass 10, count 0 2006.201.06:00:59.65#ibcon#enter sib2, iclass 10, count 0 2006.201.06:00:59.65#ibcon#flushed, iclass 10, count 0 2006.201.06:00:59.65#ibcon#about to write, iclass 10, count 0 2006.201.06:00:59.65#ibcon#wrote, iclass 10, count 0 2006.201.06:00:59.65#ibcon#about to read 3, iclass 10, count 0 2006.201.06:00:59.67#ibcon#read 3, iclass 10, count 0 2006.201.06:00:59.67#ibcon#about to read 4, iclass 10, count 0 2006.201.06:00:59.67#ibcon#read 4, iclass 10, count 0 2006.201.06:00:59.67#ibcon#about to read 5, iclass 10, count 0 2006.201.06:00:59.67#ibcon#read 5, iclass 10, count 0 2006.201.06:00:59.67#ibcon#about to read 6, iclass 10, count 0 2006.201.06:00:59.67#ibcon#read 6, iclass 10, count 0 2006.201.06:00:59.67#ibcon#end of sib2, iclass 10, count 0 2006.201.06:00:59.67#ibcon#*mode == 0, iclass 10, count 0 2006.201.06:00:59.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.06:00:59.67#ibcon#[27=USB\r\n] 2006.201.06:00:59.67#ibcon#*before write, iclass 10, count 0 2006.201.06:00:59.67#ibcon#enter sib2, iclass 10, count 0 2006.201.06:00:59.67#ibcon#flushed, iclass 10, count 0 2006.201.06:00:59.67#ibcon#about to write, iclass 10, count 0 2006.201.06:00:59.67#ibcon#wrote, iclass 10, count 0 2006.201.06:00:59.67#ibcon#about to read 3, iclass 10, count 0 2006.201.06:00:59.70#ibcon#read 3, iclass 10, count 0 2006.201.06:00:59.70#ibcon#about to read 4, iclass 10, count 0 2006.201.06:00:59.70#ibcon#read 4, iclass 10, count 0 2006.201.06:00:59.70#ibcon#about to read 5, iclass 10, count 0 2006.201.06:00:59.70#ibcon#read 5, iclass 10, count 0 2006.201.06:00:59.70#ibcon#about to read 6, iclass 10, count 0 2006.201.06:00:59.70#ibcon#read 6, iclass 10, count 0 2006.201.06:00:59.70#ibcon#end of sib2, iclass 10, count 0 2006.201.06:00:59.70#ibcon#*after write, iclass 10, count 0 2006.201.06:00:59.70#ibcon#*before return 0, iclass 10, count 0 2006.201.06:00:59.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:59.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:00:59.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.06:00:59.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.06:00:59.70$vck44/vblo=4,679.99 2006.201.06:00:59.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.06:00:59.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.06:00:59.70#ibcon#ireg 17 cls_cnt 0 2006.201.06:00:59.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:59.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:59.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:59.70#ibcon#enter wrdev, iclass 12, count 0 2006.201.06:00:59.70#ibcon#first serial, iclass 12, count 0 2006.201.06:00:59.70#ibcon#enter sib2, iclass 12, count 0 2006.201.06:00:59.70#ibcon#flushed, iclass 12, count 0 2006.201.06:00:59.70#ibcon#about to write, iclass 12, count 0 2006.201.06:00:59.70#ibcon#wrote, iclass 12, count 0 2006.201.06:00:59.70#ibcon#about to read 3, iclass 12, count 0 2006.201.06:00:59.72#ibcon#read 3, iclass 12, count 0 2006.201.06:00:59.72#ibcon#about to read 4, iclass 12, count 0 2006.201.06:00:59.72#ibcon#read 4, iclass 12, count 0 2006.201.06:00:59.72#ibcon#about to read 5, iclass 12, count 0 2006.201.06:00:59.72#ibcon#read 5, iclass 12, count 0 2006.201.06:00:59.72#ibcon#about to read 6, iclass 12, count 0 2006.201.06:00:59.72#ibcon#read 6, iclass 12, count 0 2006.201.06:00:59.72#ibcon#end of sib2, iclass 12, count 0 2006.201.06:00:59.72#ibcon#*mode == 0, iclass 12, count 0 2006.201.06:00:59.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.06:00:59.72#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.06:00:59.72#ibcon#*before write, iclass 12, count 0 2006.201.06:00:59.72#ibcon#enter sib2, iclass 12, count 0 2006.201.06:00:59.72#ibcon#flushed, iclass 12, count 0 2006.201.06:00:59.72#ibcon#about to write, iclass 12, count 0 2006.201.06:00:59.72#ibcon#wrote, iclass 12, count 0 2006.201.06:00:59.72#ibcon#about to read 3, iclass 12, count 0 2006.201.06:00:59.76#ibcon#read 3, iclass 12, count 0 2006.201.06:00:59.76#ibcon#about to read 4, iclass 12, count 0 2006.201.06:00:59.76#ibcon#read 4, iclass 12, count 0 2006.201.06:00:59.76#ibcon#about to read 5, iclass 12, count 0 2006.201.06:00:59.76#ibcon#read 5, iclass 12, count 0 2006.201.06:00:59.76#ibcon#about to read 6, iclass 12, count 0 2006.201.06:00:59.76#ibcon#read 6, iclass 12, count 0 2006.201.06:00:59.76#ibcon#end of sib2, iclass 12, count 0 2006.201.06:00:59.76#ibcon#*after write, iclass 12, count 0 2006.201.06:00:59.76#ibcon#*before return 0, iclass 12, count 0 2006.201.06:00:59.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:59.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:00:59.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.06:00:59.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.06:00:59.76$vck44/vb=4,5 2006.201.06:00:59.76#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.06:00:59.76#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.06:00:59.76#ibcon#ireg 11 cls_cnt 2 2006.201.06:00:59.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:59.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:59.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:59.82#ibcon#enter wrdev, iclass 14, count 2 2006.201.06:00:59.82#ibcon#first serial, iclass 14, count 2 2006.201.06:00:59.82#ibcon#enter sib2, iclass 14, count 2 2006.201.06:00:59.82#ibcon#flushed, iclass 14, count 2 2006.201.06:00:59.82#ibcon#about to write, iclass 14, count 2 2006.201.06:00:59.82#ibcon#wrote, iclass 14, count 2 2006.201.06:00:59.82#ibcon#about to read 3, iclass 14, count 2 2006.201.06:00:59.84#ibcon#read 3, iclass 14, count 2 2006.201.06:00:59.84#ibcon#about to read 4, iclass 14, count 2 2006.201.06:00:59.84#ibcon#read 4, iclass 14, count 2 2006.201.06:00:59.84#ibcon#about to read 5, iclass 14, count 2 2006.201.06:00:59.84#ibcon#read 5, iclass 14, count 2 2006.201.06:00:59.84#ibcon#about to read 6, iclass 14, count 2 2006.201.06:00:59.84#ibcon#read 6, iclass 14, count 2 2006.201.06:00:59.84#ibcon#end of sib2, iclass 14, count 2 2006.201.06:00:59.84#ibcon#*mode == 0, iclass 14, count 2 2006.201.06:00:59.84#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.06:00:59.84#ibcon#[27=AT04-05\r\n] 2006.201.06:00:59.84#ibcon#*before write, iclass 14, count 2 2006.201.06:00:59.84#ibcon#enter sib2, iclass 14, count 2 2006.201.06:00:59.84#ibcon#flushed, iclass 14, count 2 2006.201.06:00:59.84#ibcon#about to write, iclass 14, count 2 2006.201.06:00:59.84#ibcon#wrote, iclass 14, count 2 2006.201.06:00:59.84#ibcon#about to read 3, iclass 14, count 2 2006.201.06:00:59.87#ibcon#read 3, iclass 14, count 2 2006.201.06:00:59.87#ibcon#about to read 4, iclass 14, count 2 2006.201.06:00:59.87#ibcon#read 4, iclass 14, count 2 2006.201.06:00:59.87#ibcon#about to read 5, iclass 14, count 2 2006.201.06:00:59.87#ibcon#read 5, iclass 14, count 2 2006.201.06:00:59.87#ibcon#about to read 6, iclass 14, count 2 2006.201.06:00:59.87#ibcon#read 6, iclass 14, count 2 2006.201.06:00:59.87#ibcon#end of sib2, iclass 14, count 2 2006.201.06:00:59.87#ibcon#*after write, iclass 14, count 2 2006.201.06:00:59.87#ibcon#*before return 0, iclass 14, count 2 2006.201.06:00:59.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:59.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:00:59.87#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.06:00:59.87#ibcon#ireg 7 cls_cnt 0 2006.201.06:00:59.87#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:00:59.99#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:00:59.99#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:00:59.99#ibcon#enter wrdev, iclass 14, count 0 2006.201.06:00:59.99#ibcon#first serial, iclass 14, count 0 2006.201.06:00:59.99#ibcon#enter sib2, iclass 14, count 0 2006.201.06:00:59.99#ibcon#flushed, iclass 14, count 0 2006.201.06:00:59.99#ibcon#about to write, iclass 14, count 0 2006.201.06:00:59.99#ibcon#wrote, iclass 14, count 0 2006.201.06:00:59.99#ibcon#about to read 3, iclass 14, count 0 2006.201.06:01:00.01#ibcon#read 3, iclass 14, count 0 2006.201.06:01:00.01#ibcon#about to read 4, iclass 14, count 0 2006.201.06:01:00.01#ibcon#read 4, iclass 14, count 0 2006.201.06:01:00.01#ibcon#about to read 5, iclass 14, count 0 2006.201.06:01:00.01#ibcon#read 5, iclass 14, count 0 2006.201.06:01:00.01#ibcon#about to read 6, iclass 14, count 0 2006.201.06:01:00.01#ibcon#read 6, iclass 14, count 0 2006.201.06:01:00.01#ibcon#end of sib2, iclass 14, count 0 2006.201.06:01:00.01#ibcon#*mode == 0, iclass 14, count 0 2006.201.06:01:00.01#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.06:01:00.01#ibcon#[27=USB\r\n] 2006.201.06:01:00.01#ibcon#*before write, iclass 14, count 0 2006.201.06:01:00.01#ibcon#enter sib2, iclass 14, count 0 2006.201.06:01:00.01#ibcon#flushed, iclass 14, count 0 2006.201.06:01:00.01#ibcon#about to write, iclass 14, count 0 2006.201.06:01:00.01#ibcon#wrote, iclass 14, count 0 2006.201.06:01:00.01#ibcon#about to read 3, iclass 14, count 0 2006.201.06:01:00.04#ibcon#read 3, iclass 14, count 0 2006.201.06:01:00.04#ibcon#about to read 4, iclass 14, count 0 2006.201.06:01:00.04#ibcon#read 4, iclass 14, count 0 2006.201.06:01:00.04#ibcon#about to read 5, iclass 14, count 0 2006.201.06:01:00.04#ibcon#read 5, iclass 14, count 0 2006.201.06:01:00.04#ibcon#about to read 6, iclass 14, count 0 2006.201.06:01:00.04#ibcon#read 6, iclass 14, count 0 2006.201.06:01:00.04#ibcon#end of sib2, iclass 14, count 0 2006.201.06:01:00.04#ibcon#*after write, iclass 14, count 0 2006.201.06:01:00.04#ibcon#*before return 0, iclass 14, count 0 2006.201.06:01:00.04#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:01:00.04#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:01:00.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.06:01:00.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.06:01:00.04$vck44/vblo=5,709.99 2006.201.06:01:00.04#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.06:01:00.04#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.06:01:00.04#ibcon#ireg 17 cls_cnt 0 2006.201.06:01:00.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:01:00.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:01:00.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:01:00.04#ibcon#enter wrdev, iclass 16, count 0 2006.201.06:01:00.04#ibcon#first serial, iclass 16, count 0 2006.201.06:01:00.04#ibcon#enter sib2, iclass 16, count 0 2006.201.06:01:00.04#ibcon#flushed, iclass 16, count 0 2006.201.06:01:00.04#ibcon#about to write, iclass 16, count 0 2006.201.06:01:00.04#ibcon#wrote, iclass 16, count 0 2006.201.06:01:00.04#ibcon#about to read 3, iclass 16, count 0 2006.201.06:01:00.06#ibcon#read 3, iclass 16, count 0 2006.201.06:01:00.06#ibcon#about to read 4, iclass 16, count 0 2006.201.06:01:00.06#ibcon#read 4, iclass 16, count 0 2006.201.06:01:00.06#ibcon#about to read 5, iclass 16, count 0 2006.201.06:01:00.06#ibcon#read 5, iclass 16, count 0 2006.201.06:01:00.06#ibcon#about to read 6, iclass 16, count 0 2006.201.06:01:00.06#ibcon#read 6, iclass 16, count 0 2006.201.06:01:00.06#ibcon#end of sib2, iclass 16, count 0 2006.201.06:01:00.06#ibcon#*mode == 0, iclass 16, count 0 2006.201.06:01:00.06#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.06:01:00.06#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.06:01:00.06#ibcon#*before write, iclass 16, count 0 2006.201.06:01:00.06#ibcon#enter sib2, iclass 16, count 0 2006.201.06:01:00.06#ibcon#flushed, iclass 16, count 0 2006.201.06:01:00.06#ibcon#about to write, iclass 16, count 0 2006.201.06:01:00.06#ibcon#wrote, iclass 16, count 0 2006.201.06:01:00.06#ibcon#about to read 3, iclass 16, count 0 2006.201.06:01:00.10#ibcon#read 3, iclass 16, count 0 2006.201.06:01:00.10#ibcon#about to read 4, iclass 16, count 0 2006.201.06:01:00.10#ibcon#read 4, iclass 16, count 0 2006.201.06:01:00.10#ibcon#about to read 5, iclass 16, count 0 2006.201.06:01:00.10#ibcon#read 5, iclass 16, count 0 2006.201.06:01:00.10#ibcon#about to read 6, iclass 16, count 0 2006.201.06:01:00.10#ibcon#read 6, iclass 16, count 0 2006.201.06:01:00.10#ibcon#end of sib2, iclass 16, count 0 2006.201.06:01:00.10#ibcon#*after write, iclass 16, count 0 2006.201.06:01:00.10#ibcon#*before return 0, iclass 16, count 0 2006.201.06:01:00.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:01:00.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:01:00.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.06:01:00.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.06:01:00.10$vck44/vb=5,4 2006.201.06:01:00.10#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.06:01:00.10#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.06:01:00.10#ibcon#ireg 11 cls_cnt 2 2006.201.06:01:00.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:01:00.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:01:00.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:01:00.16#ibcon#enter wrdev, iclass 18, count 2 2006.201.06:01:00.16#ibcon#first serial, iclass 18, count 2 2006.201.06:01:00.16#ibcon#enter sib2, iclass 18, count 2 2006.201.06:01:00.16#ibcon#flushed, iclass 18, count 2 2006.201.06:01:00.16#ibcon#about to write, iclass 18, count 2 2006.201.06:01:00.16#ibcon#wrote, iclass 18, count 2 2006.201.06:01:00.16#ibcon#about to read 3, iclass 18, count 2 2006.201.06:01:00.18#ibcon#read 3, iclass 18, count 2 2006.201.06:01:00.18#ibcon#about to read 4, iclass 18, count 2 2006.201.06:01:00.18#ibcon#read 4, iclass 18, count 2 2006.201.06:01:00.18#ibcon#about to read 5, iclass 18, count 2 2006.201.06:01:00.18#ibcon#read 5, iclass 18, count 2 2006.201.06:01:00.18#ibcon#about to read 6, iclass 18, count 2 2006.201.06:01:00.18#ibcon#read 6, iclass 18, count 2 2006.201.06:01:00.18#ibcon#end of sib2, iclass 18, count 2 2006.201.06:01:00.18#ibcon#*mode == 0, iclass 18, count 2 2006.201.06:01:00.18#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.06:01:00.18#ibcon#[27=AT05-04\r\n] 2006.201.06:01:00.18#ibcon#*before write, iclass 18, count 2 2006.201.06:01:00.18#ibcon#enter sib2, iclass 18, count 2 2006.201.06:01:00.18#ibcon#flushed, iclass 18, count 2 2006.201.06:01:00.18#ibcon#about to write, iclass 18, count 2 2006.201.06:01:00.18#ibcon#wrote, iclass 18, count 2 2006.201.06:01:00.18#ibcon#about to read 3, iclass 18, count 2 2006.201.06:01:00.21#ibcon#read 3, iclass 18, count 2 2006.201.06:01:00.21#ibcon#about to read 4, iclass 18, count 2 2006.201.06:01:00.21#ibcon#read 4, iclass 18, count 2 2006.201.06:01:00.21#ibcon#about to read 5, iclass 18, count 2 2006.201.06:01:00.21#ibcon#read 5, iclass 18, count 2 2006.201.06:01:00.21#ibcon#about to read 6, iclass 18, count 2 2006.201.06:01:00.21#ibcon#read 6, iclass 18, count 2 2006.201.06:01:00.21#ibcon#end of sib2, iclass 18, count 2 2006.201.06:01:00.21#ibcon#*after write, iclass 18, count 2 2006.201.06:01:00.21#ibcon#*before return 0, iclass 18, count 2 2006.201.06:01:00.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:01:00.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:01:00.21#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.06:01:00.21#ibcon#ireg 7 cls_cnt 0 2006.201.06:01:00.21#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:01:00.33#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:01:00.33#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:01:00.33#ibcon#enter wrdev, iclass 18, count 0 2006.201.06:01:00.33#ibcon#first serial, iclass 18, count 0 2006.201.06:01:00.33#ibcon#enter sib2, iclass 18, count 0 2006.201.06:01:00.33#ibcon#flushed, iclass 18, count 0 2006.201.06:01:00.33#ibcon#about to write, iclass 18, count 0 2006.201.06:01:00.33#ibcon#wrote, iclass 18, count 0 2006.201.06:01:00.33#ibcon#about to read 3, iclass 18, count 0 2006.201.06:01:00.35#ibcon#read 3, iclass 18, count 0 2006.201.06:01:00.35#ibcon#about to read 4, iclass 18, count 0 2006.201.06:01:00.35#ibcon#read 4, iclass 18, count 0 2006.201.06:01:00.35#ibcon#about to read 5, iclass 18, count 0 2006.201.06:01:00.35#ibcon#read 5, iclass 18, count 0 2006.201.06:01:00.35#ibcon#about to read 6, iclass 18, count 0 2006.201.06:01:00.35#ibcon#read 6, iclass 18, count 0 2006.201.06:01:00.35#ibcon#end of sib2, iclass 18, count 0 2006.201.06:01:00.35#ibcon#*mode == 0, iclass 18, count 0 2006.201.06:01:00.35#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.06:01:00.35#ibcon#[27=USB\r\n] 2006.201.06:01:00.35#ibcon#*before write, iclass 18, count 0 2006.201.06:01:00.35#ibcon#enter sib2, iclass 18, count 0 2006.201.06:01:00.35#ibcon#flushed, iclass 18, count 0 2006.201.06:01:00.35#ibcon#about to write, iclass 18, count 0 2006.201.06:01:00.35#ibcon#wrote, iclass 18, count 0 2006.201.06:01:00.35#ibcon#about to read 3, iclass 18, count 0 2006.201.06:01:00.38#ibcon#read 3, iclass 18, count 0 2006.201.06:01:00.38#ibcon#about to read 4, iclass 18, count 0 2006.201.06:01:00.38#ibcon#read 4, iclass 18, count 0 2006.201.06:01:00.38#ibcon#about to read 5, iclass 18, count 0 2006.201.06:01:00.38#ibcon#read 5, iclass 18, count 0 2006.201.06:01:00.38#ibcon#about to read 6, iclass 18, count 0 2006.201.06:01:00.38#ibcon#read 6, iclass 18, count 0 2006.201.06:01:00.38#ibcon#end of sib2, iclass 18, count 0 2006.201.06:01:00.38#ibcon#*after write, iclass 18, count 0 2006.201.06:01:00.38#ibcon#*before return 0, iclass 18, count 0 2006.201.06:01:00.38#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:01:00.38#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:01:00.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.06:01:00.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.06:01:00.38$vck44/vblo=6,719.99 2006.201.06:01:00.38#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.06:01:00.38#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.06:01:00.38#ibcon#ireg 17 cls_cnt 0 2006.201.06:01:00.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:01:00.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:01:00.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:01:00.38#ibcon#enter wrdev, iclass 20, count 0 2006.201.06:01:00.38#ibcon#first serial, iclass 20, count 0 2006.201.06:01:00.38#ibcon#enter sib2, iclass 20, count 0 2006.201.06:01:00.38#ibcon#flushed, iclass 20, count 0 2006.201.06:01:00.38#ibcon#about to write, iclass 20, count 0 2006.201.06:01:00.38#ibcon#wrote, iclass 20, count 0 2006.201.06:01:00.38#ibcon#about to read 3, iclass 20, count 0 2006.201.06:01:00.40#ibcon#read 3, iclass 20, count 0 2006.201.06:01:00.40#ibcon#about to read 4, iclass 20, count 0 2006.201.06:01:00.40#ibcon#read 4, iclass 20, count 0 2006.201.06:01:00.40#ibcon#about to read 5, iclass 20, count 0 2006.201.06:01:00.40#ibcon#read 5, iclass 20, count 0 2006.201.06:01:00.40#ibcon#about to read 6, iclass 20, count 0 2006.201.06:01:00.40#ibcon#read 6, iclass 20, count 0 2006.201.06:01:00.40#ibcon#end of sib2, iclass 20, count 0 2006.201.06:01:00.40#ibcon#*mode == 0, iclass 20, count 0 2006.201.06:01:00.40#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.06:01:00.40#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.06:01:00.40#ibcon#*before write, iclass 20, count 0 2006.201.06:01:00.40#ibcon#enter sib2, iclass 20, count 0 2006.201.06:01:00.40#ibcon#flushed, iclass 20, count 0 2006.201.06:01:00.40#ibcon#about to write, iclass 20, count 0 2006.201.06:01:00.40#ibcon#wrote, iclass 20, count 0 2006.201.06:01:00.40#ibcon#about to read 3, iclass 20, count 0 2006.201.06:01:00.44#ibcon#read 3, iclass 20, count 0 2006.201.06:01:00.44#ibcon#about to read 4, iclass 20, count 0 2006.201.06:01:00.44#ibcon#read 4, iclass 20, count 0 2006.201.06:01:00.44#ibcon#about to read 5, iclass 20, count 0 2006.201.06:01:00.44#ibcon#read 5, iclass 20, count 0 2006.201.06:01:00.44#ibcon#about to read 6, iclass 20, count 0 2006.201.06:01:00.44#ibcon#read 6, iclass 20, count 0 2006.201.06:01:00.44#ibcon#end of sib2, iclass 20, count 0 2006.201.06:01:00.44#ibcon#*after write, iclass 20, count 0 2006.201.06:01:00.44#ibcon#*before return 0, iclass 20, count 0 2006.201.06:01:00.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:01:00.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:01:00.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.06:01:00.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.06:01:00.44$vck44/vb=6,4 2006.201.06:01:00.44#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.06:01:00.44#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.06:01:00.44#ibcon#ireg 11 cls_cnt 2 2006.201.06:01:00.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:01:00.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:01:00.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:01:00.50#ibcon#enter wrdev, iclass 22, count 2 2006.201.06:01:00.50#ibcon#first serial, iclass 22, count 2 2006.201.06:01:00.50#ibcon#enter sib2, iclass 22, count 2 2006.201.06:01:00.50#ibcon#flushed, iclass 22, count 2 2006.201.06:01:00.50#ibcon#about to write, iclass 22, count 2 2006.201.06:01:00.50#ibcon#wrote, iclass 22, count 2 2006.201.06:01:00.50#ibcon#about to read 3, iclass 22, count 2 2006.201.06:01:00.52#ibcon#read 3, iclass 22, count 2 2006.201.06:01:00.52#ibcon#about to read 4, iclass 22, count 2 2006.201.06:01:00.52#ibcon#read 4, iclass 22, count 2 2006.201.06:01:00.52#ibcon#about to read 5, iclass 22, count 2 2006.201.06:01:00.52#ibcon#read 5, iclass 22, count 2 2006.201.06:01:00.52#ibcon#about to read 6, iclass 22, count 2 2006.201.06:01:00.52#ibcon#read 6, iclass 22, count 2 2006.201.06:01:00.52#ibcon#end of sib2, iclass 22, count 2 2006.201.06:01:00.52#ibcon#*mode == 0, iclass 22, count 2 2006.201.06:01:00.52#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.06:01:00.52#ibcon#[27=AT06-04\r\n] 2006.201.06:01:00.52#ibcon#*before write, iclass 22, count 2 2006.201.06:01:00.52#ibcon#enter sib2, iclass 22, count 2 2006.201.06:01:00.52#ibcon#flushed, iclass 22, count 2 2006.201.06:01:00.52#ibcon#about to write, iclass 22, count 2 2006.201.06:01:00.52#ibcon#wrote, iclass 22, count 2 2006.201.06:01:00.52#ibcon#about to read 3, iclass 22, count 2 2006.201.06:01:00.55#ibcon#read 3, iclass 22, count 2 2006.201.06:01:00.55#ibcon#about to read 4, iclass 22, count 2 2006.201.06:01:00.55#ibcon#read 4, iclass 22, count 2 2006.201.06:01:00.55#ibcon#about to read 5, iclass 22, count 2 2006.201.06:01:00.55#ibcon#read 5, iclass 22, count 2 2006.201.06:01:00.55#ibcon#about to read 6, iclass 22, count 2 2006.201.06:01:00.55#ibcon#read 6, iclass 22, count 2 2006.201.06:01:00.55#ibcon#end of sib2, iclass 22, count 2 2006.201.06:01:00.55#ibcon#*after write, iclass 22, count 2 2006.201.06:01:00.55#ibcon#*before return 0, iclass 22, count 2 2006.201.06:01:00.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:01:00.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:01:00.55#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.06:01:00.55#ibcon#ireg 7 cls_cnt 0 2006.201.06:01:00.55#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:01:00.67#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:01:00.67#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:01:00.67#ibcon#enter wrdev, iclass 22, count 0 2006.201.06:01:00.67#ibcon#first serial, iclass 22, count 0 2006.201.06:01:00.67#ibcon#enter sib2, iclass 22, count 0 2006.201.06:01:00.67#ibcon#flushed, iclass 22, count 0 2006.201.06:01:00.67#ibcon#about to write, iclass 22, count 0 2006.201.06:01:00.67#ibcon#wrote, iclass 22, count 0 2006.201.06:01:00.67#ibcon#about to read 3, iclass 22, count 0 2006.201.06:01:00.69#ibcon#read 3, iclass 22, count 0 2006.201.06:01:00.69#ibcon#about to read 4, iclass 22, count 0 2006.201.06:01:00.69#ibcon#read 4, iclass 22, count 0 2006.201.06:01:00.69#ibcon#about to read 5, iclass 22, count 0 2006.201.06:01:00.69#ibcon#read 5, iclass 22, count 0 2006.201.06:01:00.69#ibcon#about to read 6, iclass 22, count 0 2006.201.06:01:00.69#ibcon#read 6, iclass 22, count 0 2006.201.06:01:00.69#ibcon#end of sib2, iclass 22, count 0 2006.201.06:01:00.69#ibcon#*mode == 0, iclass 22, count 0 2006.201.06:01:00.69#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.06:01:00.69#ibcon#[27=USB\r\n] 2006.201.06:01:00.69#ibcon#*before write, iclass 22, count 0 2006.201.06:01:00.69#ibcon#enter sib2, iclass 22, count 0 2006.201.06:01:00.69#ibcon#flushed, iclass 22, count 0 2006.201.06:01:00.69#ibcon#about to write, iclass 22, count 0 2006.201.06:01:00.69#ibcon#wrote, iclass 22, count 0 2006.201.06:01:00.69#ibcon#about to read 3, iclass 22, count 0 2006.201.06:01:00.72#ibcon#read 3, iclass 22, count 0 2006.201.06:01:00.72#ibcon#about to read 4, iclass 22, count 0 2006.201.06:01:00.72#ibcon#read 4, iclass 22, count 0 2006.201.06:01:00.72#ibcon#about to read 5, iclass 22, count 0 2006.201.06:01:00.72#ibcon#read 5, iclass 22, count 0 2006.201.06:01:00.72#ibcon#about to read 6, iclass 22, count 0 2006.201.06:01:00.72#ibcon#read 6, iclass 22, count 0 2006.201.06:01:00.72#ibcon#end of sib2, iclass 22, count 0 2006.201.06:01:00.72#ibcon#*after write, iclass 22, count 0 2006.201.06:01:00.72#ibcon#*before return 0, iclass 22, count 0 2006.201.06:01:00.72#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:01:00.72#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:01:00.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.06:01:00.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.06:01:00.72$vck44/vblo=7,734.99 2006.201.06:01:00.72#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.06:01:00.72#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.06:01:00.72#ibcon#ireg 17 cls_cnt 0 2006.201.06:01:00.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:01:00.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:01:00.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:01:00.72#ibcon#enter wrdev, iclass 24, count 0 2006.201.06:01:00.72#ibcon#first serial, iclass 24, count 0 2006.201.06:01:00.72#ibcon#enter sib2, iclass 24, count 0 2006.201.06:01:00.72#ibcon#flushed, iclass 24, count 0 2006.201.06:01:00.72#ibcon#about to write, iclass 24, count 0 2006.201.06:01:00.72#ibcon#wrote, iclass 24, count 0 2006.201.06:01:00.72#ibcon#about to read 3, iclass 24, count 0 2006.201.06:01:00.74#ibcon#read 3, iclass 24, count 0 2006.201.06:01:00.74#ibcon#about to read 4, iclass 24, count 0 2006.201.06:01:00.74#ibcon#read 4, iclass 24, count 0 2006.201.06:01:00.74#ibcon#about to read 5, iclass 24, count 0 2006.201.06:01:00.74#ibcon#read 5, iclass 24, count 0 2006.201.06:01:00.74#ibcon#about to read 6, iclass 24, count 0 2006.201.06:01:00.74#ibcon#read 6, iclass 24, count 0 2006.201.06:01:00.74#ibcon#end of sib2, iclass 24, count 0 2006.201.06:01:00.74#ibcon#*mode == 0, iclass 24, count 0 2006.201.06:01:00.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.06:01:00.74#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.06:01:00.74#ibcon#*before write, iclass 24, count 0 2006.201.06:01:00.74#ibcon#enter sib2, iclass 24, count 0 2006.201.06:01:00.74#ibcon#flushed, iclass 24, count 0 2006.201.06:01:00.74#ibcon#about to write, iclass 24, count 0 2006.201.06:01:00.74#ibcon#wrote, iclass 24, count 0 2006.201.06:01:00.74#ibcon#about to read 3, iclass 24, count 0 2006.201.06:01:00.78#ibcon#read 3, iclass 24, count 0 2006.201.06:01:00.78#ibcon#about to read 4, iclass 24, count 0 2006.201.06:01:00.78#ibcon#read 4, iclass 24, count 0 2006.201.06:01:00.78#ibcon#about to read 5, iclass 24, count 0 2006.201.06:01:00.78#ibcon#read 5, iclass 24, count 0 2006.201.06:01:00.78#ibcon#about to read 6, iclass 24, count 0 2006.201.06:01:00.78#ibcon#read 6, iclass 24, count 0 2006.201.06:01:00.78#ibcon#end of sib2, iclass 24, count 0 2006.201.06:01:00.78#ibcon#*after write, iclass 24, count 0 2006.201.06:01:00.78#ibcon#*before return 0, iclass 24, count 0 2006.201.06:01:00.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:01:00.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:01:00.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.06:01:00.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.06:01:00.78$vck44/vb=7,4 2006.201.06:01:00.78#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.06:01:00.78#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.06:01:00.78#ibcon#ireg 11 cls_cnt 2 2006.201.06:01:00.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:01:00.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:01:00.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:01:00.84#ibcon#enter wrdev, iclass 26, count 2 2006.201.06:01:00.84#ibcon#first serial, iclass 26, count 2 2006.201.06:01:00.84#ibcon#enter sib2, iclass 26, count 2 2006.201.06:01:00.84#ibcon#flushed, iclass 26, count 2 2006.201.06:01:00.84#ibcon#about to write, iclass 26, count 2 2006.201.06:01:00.84#ibcon#wrote, iclass 26, count 2 2006.201.06:01:00.84#ibcon#about to read 3, iclass 26, count 2 2006.201.06:01:00.86#ibcon#read 3, iclass 26, count 2 2006.201.06:01:00.86#ibcon#about to read 4, iclass 26, count 2 2006.201.06:01:00.86#ibcon#read 4, iclass 26, count 2 2006.201.06:01:00.86#ibcon#about to read 5, iclass 26, count 2 2006.201.06:01:00.86#ibcon#read 5, iclass 26, count 2 2006.201.06:01:00.86#ibcon#about to read 6, iclass 26, count 2 2006.201.06:01:00.86#ibcon#read 6, iclass 26, count 2 2006.201.06:01:00.86#ibcon#end of sib2, iclass 26, count 2 2006.201.06:01:00.86#ibcon#*mode == 0, iclass 26, count 2 2006.201.06:01:00.86#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.06:01:00.86#ibcon#[27=AT07-04\r\n] 2006.201.06:01:00.86#ibcon#*before write, iclass 26, count 2 2006.201.06:01:00.86#ibcon#enter sib2, iclass 26, count 2 2006.201.06:01:00.86#ibcon#flushed, iclass 26, count 2 2006.201.06:01:00.86#ibcon#about to write, iclass 26, count 2 2006.201.06:01:00.86#ibcon#wrote, iclass 26, count 2 2006.201.06:01:00.86#ibcon#about to read 3, iclass 26, count 2 2006.201.06:01:00.89#ibcon#read 3, iclass 26, count 2 2006.201.06:01:00.89#ibcon#about to read 4, iclass 26, count 2 2006.201.06:01:00.89#ibcon#read 4, iclass 26, count 2 2006.201.06:01:00.89#ibcon#about to read 5, iclass 26, count 2 2006.201.06:01:00.89#ibcon#read 5, iclass 26, count 2 2006.201.06:01:00.89#ibcon#about to read 6, iclass 26, count 2 2006.201.06:01:00.89#ibcon#read 6, iclass 26, count 2 2006.201.06:01:00.89#ibcon#end of sib2, iclass 26, count 2 2006.201.06:01:00.89#ibcon#*after write, iclass 26, count 2 2006.201.06:01:00.89#ibcon#*before return 0, iclass 26, count 2 2006.201.06:01:00.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:01:00.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:01:00.89#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.06:01:00.89#ibcon#ireg 7 cls_cnt 0 2006.201.06:01:00.89#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:01:01.01#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:01:01.01#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:01:01.01#ibcon#enter wrdev, iclass 26, count 0 2006.201.06:01:01.01#ibcon#first serial, iclass 26, count 0 2006.201.06:01:01.01#ibcon#enter sib2, iclass 26, count 0 2006.201.06:01:01.01#ibcon#flushed, iclass 26, count 0 2006.201.06:01:01.01#ibcon#about to write, iclass 26, count 0 2006.201.06:01:01.01#ibcon#wrote, iclass 26, count 0 2006.201.06:01:01.01#ibcon#about to read 3, iclass 26, count 0 2006.201.06:01:01.03#ibcon#read 3, iclass 26, count 0 2006.201.06:01:01.03#ibcon#about to read 4, iclass 26, count 0 2006.201.06:01:01.03#ibcon#read 4, iclass 26, count 0 2006.201.06:01:01.03#ibcon#about to read 5, iclass 26, count 0 2006.201.06:01:01.03#ibcon#read 5, iclass 26, count 0 2006.201.06:01:01.03#ibcon#about to read 6, iclass 26, count 0 2006.201.06:01:01.03#ibcon#read 6, iclass 26, count 0 2006.201.06:01:01.03#ibcon#end of sib2, iclass 26, count 0 2006.201.06:01:01.03#ibcon#*mode == 0, iclass 26, count 0 2006.201.06:01:01.03#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.06:01:01.03#ibcon#[27=USB\r\n] 2006.201.06:01:01.03#ibcon#*before write, iclass 26, count 0 2006.201.06:01:01.03#ibcon#enter sib2, iclass 26, count 0 2006.201.06:01:01.03#ibcon#flushed, iclass 26, count 0 2006.201.06:01:01.03#ibcon#about to write, iclass 26, count 0 2006.201.06:01:01.03#ibcon#wrote, iclass 26, count 0 2006.201.06:01:01.03#ibcon#about to read 3, iclass 26, count 0 2006.201.06:01:01.06#ibcon#read 3, iclass 26, count 0 2006.201.06:01:01.06#ibcon#about to read 4, iclass 26, count 0 2006.201.06:01:01.06#ibcon#read 4, iclass 26, count 0 2006.201.06:01:01.06#ibcon#about to read 5, iclass 26, count 0 2006.201.06:01:01.06#ibcon#read 5, iclass 26, count 0 2006.201.06:01:01.06#ibcon#about to read 6, iclass 26, count 0 2006.201.06:01:01.06#ibcon#read 6, iclass 26, count 0 2006.201.06:01:01.06#ibcon#end of sib2, iclass 26, count 0 2006.201.06:01:01.06#ibcon#*after write, iclass 26, count 0 2006.201.06:01:01.06#ibcon#*before return 0, iclass 26, count 0 2006.201.06:01:01.06#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:01:01.06#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:01:01.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.06:01:01.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.06:01:01.06$vck44/vblo=8,744.99 2006.201.06:01:01.06#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.06:01:01.06#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.06:01:01.06#ibcon#ireg 17 cls_cnt 0 2006.201.06:01:01.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:01:01.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:01:01.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:01:01.06#ibcon#enter wrdev, iclass 28, count 0 2006.201.06:01:01.06#ibcon#first serial, iclass 28, count 0 2006.201.06:01:01.06#ibcon#enter sib2, iclass 28, count 0 2006.201.06:01:01.06#ibcon#flushed, iclass 28, count 0 2006.201.06:01:01.06#ibcon#about to write, iclass 28, count 0 2006.201.06:01:01.06#ibcon#wrote, iclass 28, count 0 2006.201.06:01:01.06#ibcon#about to read 3, iclass 28, count 0 2006.201.06:01:01.08#ibcon#read 3, iclass 28, count 0 2006.201.06:01:01.08#ibcon#about to read 4, iclass 28, count 0 2006.201.06:01:01.08#ibcon#read 4, iclass 28, count 0 2006.201.06:01:01.08#ibcon#about to read 5, iclass 28, count 0 2006.201.06:01:01.08#ibcon#read 5, iclass 28, count 0 2006.201.06:01:01.08#ibcon#about to read 6, iclass 28, count 0 2006.201.06:01:01.08#ibcon#read 6, iclass 28, count 0 2006.201.06:01:01.08#ibcon#end of sib2, iclass 28, count 0 2006.201.06:01:01.08#ibcon#*mode == 0, iclass 28, count 0 2006.201.06:01:01.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.06:01:01.08#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.06:01:01.08#ibcon#*before write, iclass 28, count 0 2006.201.06:01:01.08#ibcon#enter sib2, iclass 28, count 0 2006.201.06:01:01.08#ibcon#flushed, iclass 28, count 0 2006.201.06:01:01.08#ibcon#about to write, iclass 28, count 0 2006.201.06:01:01.08#ibcon#wrote, iclass 28, count 0 2006.201.06:01:01.08#ibcon#about to read 3, iclass 28, count 0 2006.201.06:01:01.12#ibcon#read 3, iclass 28, count 0 2006.201.06:01:01.12#ibcon#about to read 4, iclass 28, count 0 2006.201.06:01:01.12#ibcon#read 4, iclass 28, count 0 2006.201.06:01:01.12#ibcon#about to read 5, iclass 28, count 0 2006.201.06:01:01.12#ibcon#read 5, iclass 28, count 0 2006.201.06:01:01.12#ibcon#about to read 6, iclass 28, count 0 2006.201.06:01:01.12#ibcon#read 6, iclass 28, count 0 2006.201.06:01:01.12#ibcon#end of sib2, iclass 28, count 0 2006.201.06:01:01.12#ibcon#*after write, iclass 28, count 0 2006.201.06:01:01.12#ibcon#*before return 0, iclass 28, count 0 2006.201.06:01:01.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:01:01.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:01:01.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.06:01:01.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.06:01:01.12$vck44/vb=8,4 2006.201.06:01:01.12#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.06:01:01.12#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.06:01:01.12#ibcon#ireg 11 cls_cnt 2 2006.201.06:01:01.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:01:01.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:01:01.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:01:01.18#ibcon#enter wrdev, iclass 30, count 2 2006.201.06:01:01.18#ibcon#first serial, iclass 30, count 2 2006.201.06:01:01.18#ibcon#enter sib2, iclass 30, count 2 2006.201.06:01:01.18#ibcon#flushed, iclass 30, count 2 2006.201.06:01:01.18#ibcon#about to write, iclass 30, count 2 2006.201.06:01:01.18#ibcon#wrote, iclass 30, count 2 2006.201.06:01:01.18#ibcon#about to read 3, iclass 30, count 2 2006.201.06:01:01.20#ibcon#read 3, iclass 30, count 2 2006.201.06:01:01.20#ibcon#about to read 4, iclass 30, count 2 2006.201.06:01:01.20#ibcon#read 4, iclass 30, count 2 2006.201.06:01:01.20#ibcon#about to read 5, iclass 30, count 2 2006.201.06:01:01.20#ibcon#read 5, iclass 30, count 2 2006.201.06:01:01.20#ibcon#about to read 6, iclass 30, count 2 2006.201.06:01:01.20#ibcon#read 6, iclass 30, count 2 2006.201.06:01:01.20#ibcon#end of sib2, iclass 30, count 2 2006.201.06:01:01.20#ibcon#*mode == 0, iclass 30, count 2 2006.201.06:01:01.20#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.06:01:01.20#ibcon#[27=AT08-04\r\n] 2006.201.06:01:01.20#ibcon#*before write, iclass 30, count 2 2006.201.06:01:01.20#ibcon#enter sib2, iclass 30, count 2 2006.201.06:01:01.20#ibcon#flushed, iclass 30, count 2 2006.201.06:01:01.20#ibcon#about to write, iclass 30, count 2 2006.201.06:01:01.20#ibcon#wrote, iclass 30, count 2 2006.201.06:01:01.20#ibcon#about to read 3, iclass 30, count 2 2006.201.06:01:01.23#ibcon#read 3, iclass 30, count 2 2006.201.06:01:01.23#ibcon#about to read 4, iclass 30, count 2 2006.201.06:01:01.23#ibcon#read 4, iclass 30, count 2 2006.201.06:01:01.23#ibcon#about to read 5, iclass 30, count 2 2006.201.06:01:01.23#ibcon#read 5, iclass 30, count 2 2006.201.06:01:01.23#ibcon#about to read 6, iclass 30, count 2 2006.201.06:01:01.23#ibcon#read 6, iclass 30, count 2 2006.201.06:01:01.23#ibcon#end of sib2, iclass 30, count 2 2006.201.06:01:01.23#ibcon#*after write, iclass 30, count 2 2006.201.06:01:01.23#ibcon#*before return 0, iclass 30, count 2 2006.201.06:01:01.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:01:01.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:01:01.23#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.06:01:01.23#ibcon#ireg 7 cls_cnt 0 2006.201.06:01:01.23#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:01:01.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:01:01.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:01:01.35#ibcon#enter wrdev, iclass 30, count 0 2006.201.06:01:01.35#ibcon#first serial, iclass 30, count 0 2006.201.06:01:01.35#ibcon#enter sib2, iclass 30, count 0 2006.201.06:01:01.35#ibcon#flushed, iclass 30, count 0 2006.201.06:01:01.35#ibcon#about to write, iclass 30, count 0 2006.201.06:01:01.35#ibcon#wrote, iclass 30, count 0 2006.201.06:01:01.35#ibcon#about to read 3, iclass 30, count 0 2006.201.06:01:01.37#ibcon#read 3, iclass 30, count 0 2006.201.06:01:01.37#ibcon#about to read 4, iclass 30, count 0 2006.201.06:01:01.37#ibcon#read 4, iclass 30, count 0 2006.201.06:01:01.37#ibcon#about to read 5, iclass 30, count 0 2006.201.06:01:01.37#ibcon#read 5, iclass 30, count 0 2006.201.06:01:01.37#ibcon#about to read 6, iclass 30, count 0 2006.201.06:01:01.37#ibcon#read 6, iclass 30, count 0 2006.201.06:01:01.37#ibcon#end of sib2, iclass 30, count 0 2006.201.06:01:01.37#ibcon#*mode == 0, iclass 30, count 0 2006.201.06:01:01.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.06:01:01.37#ibcon#[27=USB\r\n] 2006.201.06:01:01.37#ibcon#*before write, iclass 30, count 0 2006.201.06:01:01.37#ibcon#enter sib2, iclass 30, count 0 2006.201.06:01:01.37#ibcon#flushed, iclass 30, count 0 2006.201.06:01:01.37#ibcon#about to write, iclass 30, count 0 2006.201.06:01:01.37#ibcon#wrote, iclass 30, count 0 2006.201.06:01:01.37#ibcon#about to read 3, iclass 30, count 0 2006.201.06:01:01.40#ibcon#read 3, iclass 30, count 0 2006.201.06:01:01.40#ibcon#about to read 4, iclass 30, count 0 2006.201.06:01:01.40#ibcon#read 4, iclass 30, count 0 2006.201.06:01:01.40#ibcon#about to read 5, iclass 30, count 0 2006.201.06:01:01.40#ibcon#read 5, iclass 30, count 0 2006.201.06:01:01.40#ibcon#about to read 6, iclass 30, count 0 2006.201.06:01:01.40#ibcon#read 6, iclass 30, count 0 2006.201.06:01:01.40#ibcon#end of sib2, iclass 30, count 0 2006.201.06:01:01.40#ibcon#*after write, iclass 30, count 0 2006.201.06:01:01.40#ibcon#*before return 0, iclass 30, count 0 2006.201.06:01:01.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:01:01.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:01:01.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.06:01:01.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.06:01:01.40$vck44/vabw=wide 2006.201.06:01:01.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.06:01:01.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.06:01:01.40#ibcon#ireg 8 cls_cnt 0 2006.201.06:01:01.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:01:01.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:01:01.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:01:01.40#ibcon#enter wrdev, iclass 32, count 0 2006.201.06:01:01.40#ibcon#first serial, iclass 32, count 0 2006.201.06:01:01.40#ibcon#enter sib2, iclass 32, count 0 2006.201.06:01:01.40#ibcon#flushed, iclass 32, count 0 2006.201.06:01:01.40#ibcon#about to write, iclass 32, count 0 2006.201.06:01:01.40#ibcon#wrote, iclass 32, count 0 2006.201.06:01:01.40#ibcon#about to read 3, iclass 32, count 0 2006.201.06:01:01.42#ibcon#read 3, iclass 32, count 0 2006.201.06:01:01.42#ibcon#about to read 4, iclass 32, count 0 2006.201.06:01:01.42#ibcon#read 4, iclass 32, count 0 2006.201.06:01:01.42#ibcon#about to read 5, iclass 32, count 0 2006.201.06:01:01.42#ibcon#read 5, iclass 32, count 0 2006.201.06:01:01.42#ibcon#about to read 6, iclass 32, count 0 2006.201.06:01:01.42#ibcon#read 6, iclass 32, count 0 2006.201.06:01:01.42#ibcon#end of sib2, iclass 32, count 0 2006.201.06:01:01.42#ibcon#*mode == 0, iclass 32, count 0 2006.201.06:01:01.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.06:01:01.42#ibcon#[25=BW32\r\n] 2006.201.06:01:01.42#ibcon#*before write, iclass 32, count 0 2006.201.06:01:01.42#ibcon#enter sib2, iclass 32, count 0 2006.201.06:01:01.42#ibcon#flushed, iclass 32, count 0 2006.201.06:01:01.42#ibcon#about to write, iclass 32, count 0 2006.201.06:01:01.42#ibcon#wrote, iclass 32, count 0 2006.201.06:01:01.42#ibcon#about to read 3, iclass 32, count 0 2006.201.06:01:01.45#ibcon#read 3, iclass 32, count 0 2006.201.06:01:01.45#ibcon#about to read 4, iclass 32, count 0 2006.201.06:01:01.45#ibcon#read 4, iclass 32, count 0 2006.201.06:01:01.45#ibcon#about to read 5, iclass 32, count 0 2006.201.06:01:01.45#ibcon#read 5, iclass 32, count 0 2006.201.06:01:01.45#ibcon#about to read 6, iclass 32, count 0 2006.201.06:01:01.45#ibcon#read 6, iclass 32, count 0 2006.201.06:01:01.45#ibcon#end of sib2, iclass 32, count 0 2006.201.06:01:01.45#ibcon#*after write, iclass 32, count 0 2006.201.06:01:01.45#ibcon#*before return 0, iclass 32, count 0 2006.201.06:01:01.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:01:01.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:01:01.45#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.06:01:01.45#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.06:01:01.45$vck44/vbbw=wide 2006.201.06:01:01.45#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.06:01:01.45#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.06:01:01.45#ibcon#ireg 8 cls_cnt 0 2006.201.06:01:01.45#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:01:01.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:01:01.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:01:01.52#ibcon#enter wrdev, iclass 34, count 0 2006.201.06:01:01.52#ibcon#first serial, iclass 34, count 0 2006.201.06:01:01.52#ibcon#enter sib2, iclass 34, count 0 2006.201.06:01:01.52#ibcon#flushed, iclass 34, count 0 2006.201.06:01:01.52#ibcon#about to write, iclass 34, count 0 2006.201.06:01:01.52#ibcon#wrote, iclass 34, count 0 2006.201.06:01:01.52#ibcon#about to read 3, iclass 34, count 0 2006.201.06:01:01.54#ibcon#read 3, iclass 34, count 0 2006.201.06:01:01.54#ibcon#about to read 4, iclass 34, count 0 2006.201.06:01:01.54#ibcon#read 4, iclass 34, count 0 2006.201.06:01:01.54#ibcon#about to read 5, iclass 34, count 0 2006.201.06:01:01.54#ibcon#read 5, iclass 34, count 0 2006.201.06:01:01.54#ibcon#about to read 6, iclass 34, count 0 2006.201.06:01:01.54#ibcon#read 6, iclass 34, count 0 2006.201.06:01:01.54#ibcon#end of sib2, iclass 34, count 0 2006.201.06:01:01.54#ibcon#*mode == 0, iclass 34, count 0 2006.201.06:01:01.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.06:01:01.54#ibcon#[27=BW32\r\n] 2006.201.06:01:01.54#ibcon#*before write, iclass 34, count 0 2006.201.06:01:01.54#ibcon#enter sib2, iclass 34, count 0 2006.201.06:01:01.54#ibcon#flushed, iclass 34, count 0 2006.201.06:01:01.54#ibcon#about to write, iclass 34, count 0 2006.201.06:01:01.54#ibcon#wrote, iclass 34, count 0 2006.201.06:01:01.54#ibcon#about to read 3, iclass 34, count 0 2006.201.06:01:01.57#ibcon#read 3, iclass 34, count 0 2006.201.06:01:01.57#ibcon#about to read 4, iclass 34, count 0 2006.201.06:01:01.57#ibcon#read 4, iclass 34, count 0 2006.201.06:01:01.57#ibcon#about to read 5, iclass 34, count 0 2006.201.06:01:01.57#ibcon#read 5, iclass 34, count 0 2006.201.06:01:01.57#ibcon#about to read 6, iclass 34, count 0 2006.201.06:01:01.57#ibcon#read 6, iclass 34, count 0 2006.201.06:01:01.57#ibcon#end of sib2, iclass 34, count 0 2006.201.06:01:01.57#ibcon#*after write, iclass 34, count 0 2006.201.06:01:01.57#ibcon#*before return 0, iclass 34, count 0 2006.201.06:01:01.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:01:01.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:01:01.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.06:01:01.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.06:01:01.57$setupk4/ifdk4 2006.201.06:01:01.57$ifdk4/lo= 2006.201.06:01:01.57$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.06:01:01.57$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.06:01:01.57$ifdk4/patch= 2006.201.06:01:01.57$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.06:01:01.57$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.06:01:01.57$setupk4/!*+20s 2006.201.06:01:04.69#abcon#<5=/04 2.5 4.5 22.99 891003.3\r\n> 2006.201.06:01:04.71#abcon#{5=INTERFACE CLEAR} 2006.201.06:01:04.77#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:01:15.04#abcon#<5=/04 2.5 4.4 22.98 891003.3\r\n> 2006.201.06:01:15.06#abcon#{5=INTERFACE CLEAR} 2006.201.06:01:15.12#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:01:16.04$setupk4/"tpicd 2006.201.06:01:16.04$setupk4/echo=off 2006.201.06:01:16.04$setupk4/xlog=off 2006.201.06:01:16.04:!2006.201.06:01:54 2006.201.06:01:19.14#trakl#Source acquired 2006.201.06:01:21.14#flagr#flagr/antenna,acquired 2006.201.06:01:54.00:preob 2006.201.06:01:55.14/onsource/TRACKING 2006.201.06:01:55.14:!2006.201.06:02:04 2006.201.06:02:04.00:"tape 2006.201.06:02:04.00:"st=record 2006.201.06:02:04.00:data_valid=on 2006.201.06:02:04.00:midob 2006.201.06:02:04.13/onsource/TRACKING 2006.201.06:02:04.13/wx/22.98,1003.3,89 2006.201.06:02:04.23/cable/+6.4666E-03 2006.201.06:02:05.32/va/01,08,usb,yes,31,34 2006.201.06:02:05.32/va/02,07,usb,yes,34,35 2006.201.06:02:05.32/va/03,08,usb,yes,30,32 2006.201.06:02:05.32/va/04,07,usb,yes,35,37 2006.201.06:02:05.32/va/05,04,usb,yes,31,31 2006.201.06:02:05.32/va/06,05,usb,yes,31,31 2006.201.06:02:05.32/va/07,05,usb,yes,30,31 2006.201.06:02:05.32/va/08,04,usb,yes,30,36 2006.201.06:02:05.55/valo/01,524.99,yes,locked 2006.201.06:02:05.55/valo/02,534.99,yes,locked 2006.201.06:02:05.55/valo/03,564.99,yes,locked 2006.201.06:02:05.55/valo/04,624.99,yes,locked 2006.201.06:02:05.55/valo/05,734.99,yes,locked 2006.201.06:02:05.55/valo/06,814.99,yes,locked 2006.201.06:02:05.55/valo/07,864.99,yes,locked 2006.201.06:02:05.55/valo/08,884.99,yes,locked 2006.201.06:02:06.64/vb/01,04,usb,yes,30,28 2006.201.06:02:06.64/vb/02,05,usb,yes,29,28 2006.201.06:02:06.64/vb/03,04,usb,yes,30,33 2006.201.06:02:06.64/vb/04,05,usb,yes,30,29 2006.201.06:02:06.64/vb/05,04,usb,yes,26,29 2006.201.06:02:06.64/vb/06,04,usb,yes,31,27 2006.201.06:02:06.64/vb/07,04,usb,yes,31,31 2006.201.06:02:06.64/vb/08,04,usb,yes,28,32 2006.201.06:02:06.87/vblo/01,629.99,yes,locked 2006.201.06:02:06.87/vblo/02,634.99,yes,locked 2006.201.06:02:06.87/vblo/03,649.99,yes,locked 2006.201.06:02:06.87/vblo/04,679.99,yes,locked 2006.201.06:02:06.87/vblo/05,709.99,yes,locked 2006.201.06:02:06.87/vblo/06,719.99,yes,locked 2006.201.06:02:06.87/vblo/07,734.99,yes,locked 2006.201.06:02:06.87/vblo/08,744.99,yes,locked 2006.201.06:02:07.02/vabw/8 2006.201.06:02:07.17/vbbw/8 2006.201.06:02:07.26/xfe/off,on,15.0 2006.201.06:02:07.63/ifatt/23,28,28,28 2006.201.06:02:08.05/fmout-gps/S +4.49E-07 2006.201.06:02:08.12:!2006.201.06:08:34 2006.201.06:08:34.00:data_valid=off 2006.201.06:08:34.00:"et 2006.201.06:08:34.00:!+3s 2006.201.06:08:37.02:"tape 2006.201.06:08:37.02:postob 2006.201.06:08:37.20/cable/+6.4666E-03 2006.201.06:08:37.20/wx/22.95,1003.3,89 2006.201.06:08:37.28/fmout-gps/S +4.50E-07 2006.201.06:08:37.28:scan_name=201-0616,jd0607,420 2006.201.06:08:37.28:source=1418+546,141946.60,542314.8,2000.0,cw 2006.201.06:08:38.14#flagr#flagr/antenna,new-source 2006.201.06:08:38.14:checkk5 2006.201.06:08:38.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.06:08:38.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.06:08:39.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.06:08:39.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.06:08:40.02/chk_obsdata//k5ts1/T2010602??a.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.201.06:08:40.38/chk_obsdata//k5ts2/T2010602??b.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.201.06:08:40.75/chk_obsdata//k5ts3/T2010602??c.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.201.06:08:41.12/chk_obsdata//k5ts4/T2010602??d.dat file size is correct (nominal:1560MB, actual:1556MB). 2006.201.06:08:41.80/k5log//k5ts1_log_newline 2006.201.06:08:42.50/k5log//k5ts2_log_newline 2006.201.06:08:43.19/k5log//k5ts3_log_newline 2006.201.06:08:43.87/k5log//k5ts4_log_newline 2006.201.06:08:43.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.06:08:43.90:setupk4=1 2006.201.06:08:43.90$setupk4/echo=on 2006.201.06:08:43.90$setupk4/pcalon 2006.201.06:08:43.90$pcalon/"no phase cal control is implemented here 2006.201.06:08:43.90$setupk4/"tpicd=stop 2006.201.06:08:43.90$setupk4/"rec=synch_on 2006.201.06:08:43.90$setupk4/"rec_mode=128 2006.201.06:08:43.90$setupk4/!* 2006.201.06:08:43.90$setupk4/recpk4 2006.201.06:08:43.90$recpk4/recpatch= 2006.201.06:08:43.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.06:08:43.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.06:08:43.90$setupk4/vck44 2006.201.06:08:43.90$vck44/valo=1,524.99 2006.201.06:08:43.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.06:08:43.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.06:08:43.90#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:43.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:43.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:43.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:43.90#ibcon#enter wrdev, iclass 5, count 0 2006.201.06:08:43.90#ibcon#first serial, iclass 5, count 0 2006.201.06:08:43.90#ibcon#enter sib2, iclass 5, count 0 2006.201.06:08:43.90#ibcon#flushed, iclass 5, count 0 2006.201.06:08:43.90#ibcon#about to write, iclass 5, count 0 2006.201.06:08:43.90#ibcon#wrote, iclass 5, count 0 2006.201.06:08:43.90#ibcon#about to read 3, iclass 5, count 0 2006.201.06:08:43.92#ibcon#read 3, iclass 5, count 0 2006.201.06:08:43.92#ibcon#about to read 4, iclass 5, count 0 2006.201.06:08:43.92#ibcon#read 4, iclass 5, count 0 2006.201.06:08:43.92#ibcon#about to read 5, iclass 5, count 0 2006.201.06:08:43.92#ibcon#read 5, iclass 5, count 0 2006.201.06:08:43.92#ibcon#about to read 6, iclass 5, count 0 2006.201.06:08:43.92#ibcon#read 6, iclass 5, count 0 2006.201.06:08:43.92#ibcon#end of sib2, iclass 5, count 0 2006.201.06:08:43.92#ibcon#*mode == 0, iclass 5, count 0 2006.201.06:08:43.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.06:08:43.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.06:08:43.92#ibcon#*before write, iclass 5, count 0 2006.201.06:08:43.92#ibcon#enter sib2, iclass 5, count 0 2006.201.06:08:43.92#ibcon#flushed, iclass 5, count 0 2006.201.06:08:43.92#ibcon#about to write, iclass 5, count 0 2006.201.06:08:43.92#ibcon#wrote, iclass 5, count 0 2006.201.06:08:43.92#ibcon#about to read 3, iclass 5, count 0 2006.201.06:08:43.97#ibcon#read 3, iclass 5, count 0 2006.201.06:08:43.97#ibcon#about to read 4, iclass 5, count 0 2006.201.06:08:43.97#ibcon#read 4, iclass 5, count 0 2006.201.06:08:43.97#ibcon#about to read 5, iclass 5, count 0 2006.201.06:08:43.97#ibcon#read 5, iclass 5, count 0 2006.201.06:08:43.97#ibcon#about to read 6, iclass 5, count 0 2006.201.06:08:43.97#ibcon#read 6, iclass 5, count 0 2006.201.06:08:43.97#ibcon#end of sib2, iclass 5, count 0 2006.201.06:08:43.97#ibcon#*after write, iclass 5, count 0 2006.201.06:08:43.97#ibcon#*before return 0, iclass 5, count 0 2006.201.06:08:43.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:43.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:43.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.06:08:43.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.06:08:43.97$vck44/va=1,8 2006.201.06:08:43.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.06:08:43.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.06:08:43.97#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:43.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:43.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:43.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:43.97#ibcon#enter wrdev, iclass 7, count 2 2006.201.06:08:43.97#ibcon#first serial, iclass 7, count 2 2006.201.06:08:43.97#ibcon#enter sib2, iclass 7, count 2 2006.201.06:08:43.97#ibcon#flushed, iclass 7, count 2 2006.201.06:08:43.97#ibcon#about to write, iclass 7, count 2 2006.201.06:08:43.97#ibcon#wrote, iclass 7, count 2 2006.201.06:08:43.97#ibcon#about to read 3, iclass 7, count 2 2006.201.06:08:43.99#ibcon#read 3, iclass 7, count 2 2006.201.06:08:43.99#ibcon#about to read 4, iclass 7, count 2 2006.201.06:08:43.99#ibcon#read 4, iclass 7, count 2 2006.201.06:08:43.99#ibcon#about to read 5, iclass 7, count 2 2006.201.06:08:43.99#ibcon#read 5, iclass 7, count 2 2006.201.06:08:43.99#ibcon#about to read 6, iclass 7, count 2 2006.201.06:08:43.99#ibcon#read 6, iclass 7, count 2 2006.201.06:08:43.99#ibcon#end of sib2, iclass 7, count 2 2006.201.06:08:43.99#ibcon#*mode == 0, iclass 7, count 2 2006.201.06:08:43.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.06:08:43.99#ibcon#[25=AT01-08\r\n] 2006.201.06:08:43.99#ibcon#*before write, iclass 7, count 2 2006.201.06:08:43.99#ibcon#enter sib2, iclass 7, count 2 2006.201.06:08:43.99#ibcon#flushed, iclass 7, count 2 2006.201.06:08:43.99#ibcon#about to write, iclass 7, count 2 2006.201.06:08:43.99#ibcon#wrote, iclass 7, count 2 2006.201.06:08:43.99#ibcon#about to read 3, iclass 7, count 2 2006.201.06:08:44.02#ibcon#read 3, iclass 7, count 2 2006.201.06:08:44.02#ibcon#about to read 4, iclass 7, count 2 2006.201.06:08:44.02#ibcon#read 4, iclass 7, count 2 2006.201.06:08:44.02#ibcon#about to read 5, iclass 7, count 2 2006.201.06:08:44.02#ibcon#read 5, iclass 7, count 2 2006.201.06:08:44.02#ibcon#about to read 6, iclass 7, count 2 2006.201.06:08:44.02#ibcon#read 6, iclass 7, count 2 2006.201.06:08:44.02#ibcon#end of sib2, iclass 7, count 2 2006.201.06:08:44.02#ibcon#*after write, iclass 7, count 2 2006.201.06:08:44.02#ibcon#*before return 0, iclass 7, count 2 2006.201.06:08:44.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:44.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:44.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.06:08:44.02#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:44.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:44.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:44.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:44.14#ibcon#enter wrdev, iclass 7, count 0 2006.201.06:08:44.14#ibcon#first serial, iclass 7, count 0 2006.201.06:08:44.14#ibcon#enter sib2, iclass 7, count 0 2006.201.06:08:44.14#ibcon#flushed, iclass 7, count 0 2006.201.06:08:44.14#ibcon#about to write, iclass 7, count 0 2006.201.06:08:44.14#ibcon#wrote, iclass 7, count 0 2006.201.06:08:44.14#ibcon#about to read 3, iclass 7, count 0 2006.201.06:08:44.16#ibcon#read 3, iclass 7, count 0 2006.201.06:08:44.16#ibcon#about to read 4, iclass 7, count 0 2006.201.06:08:44.16#ibcon#read 4, iclass 7, count 0 2006.201.06:08:44.16#ibcon#about to read 5, iclass 7, count 0 2006.201.06:08:44.16#ibcon#read 5, iclass 7, count 0 2006.201.06:08:44.16#ibcon#about to read 6, iclass 7, count 0 2006.201.06:08:44.16#ibcon#read 6, iclass 7, count 0 2006.201.06:08:44.16#ibcon#end of sib2, iclass 7, count 0 2006.201.06:08:44.16#ibcon#*mode == 0, iclass 7, count 0 2006.201.06:08:44.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.06:08:44.16#ibcon#[25=USB\r\n] 2006.201.06:08:44.16#ibcon#*before write, iclass 7, count 0 2006.201.06:08:44.16#ibcon#enter sib2, iclass 7, count 0 2006.201.06:08:44.16#ibcon#flushed, iclass 7, count 0 2006.201.06:08:44.16#ibcon#about to write, iclass 7, count 0 2006.201.06:08:44.16#ibcon#wrote, iclass 7, count 0 2006.201.06:08:44.16#ibcon#about to read 3, iclass 7, count 0 2006.201.06:08:44.19#ibcon#read 3, iclass 7, count 0 2006.201.06:08:44.19#ibcon#about to read 4, iclass 7, count 0 2006.201.06:08:44.19#ibcon#read 4, iclass 7, count 0 2006.201.06:08:44.19#ibcon#about to read 5, iclass 7, count 0 2006.201.06:08:44.19#ibcon#read 5, iclass 7, count 0 2006.201.06:08:44.19#ibcon#about to read 6, iclass 7, count 0 2006.201.06:08:44.19#ibcon#read 6, iclass 7, count 0 2006.201.06:08:44.19#ibcon#end of sib2, iclass 7, count 0 2006.201.06:08:44.19#ibcon#*after write, iclass 7, count 0 2006.201.06:08:44.19#ibcon#*before return 0, iclass 7, count 0 2006.201.06:08:44.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:44.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:44.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.06:08:44.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.06:08:44.19$vck44/valo=2,534.99 2006.201.06:08:44.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.06:08:44.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.06:08:44.19#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:44.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:44.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:44.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:44.19#ibcon#enter wrdev, iclass 11, count 0 2006.201.06:08:44.19#ibcon#first serial, iclass 11, count 0 2006.201.06:08:44.19#ibcon#enter sib2, iclass 11, count 0 2006.201.06:08:44.19#ibcon#flushed, iclass 11, count 0 2006.201.06:08:44.19#ibcon#about to write, iclass 11, count 0 2006.201.06:08:44.19#ibcon#wrote, iclass 11, count 0 2006.201.06:08:44.19#ibcon#about to read 3, iclass 11, count 0 2006.201.06:08:44.21#ibcon#read 3, iclass 11, count 0 2006.201.06:08:44.21#ibcon#about to read 4, iclass 11, count 0 2006.201.06:08:44.21#ibcon#read 4, iclass 11, count 0 2006.201.06:08:44.21#ibcon#about to read 5, iclass 11, count 0 2006.201.06:08:44.21#ibcon#read 5, iclass 11, count 0 2006.201.06:08:44.21#ibcon#about to read 6, iclass 11, count 0 2006.201.06:08:44.21#ibcon#read 6, iclass 11, count 0 2006.201.06:08:44.21#ibcon#end of sib2, iclass 11, count 0 2006.201.06:08:44.21#ibcon#*mode == 0, iclass 11, count 0 2006.201.06:08:44.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.06:08:44.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.06:08:44.21#ibcon#*before write, iclass 11, count 0 2006.201.06:08:44.21#ibcon#enter sib2, iclass 11, count 0 2006.201.06:08:44.21#ibcon#flushed, iclass 11, count 0 2006.201.06:08:44.21#ibcon#about to write, iclass 11, count 0 2006.201.06:08:44.21#ibcon#wrote, iclass 11, count 0 2006.201.06:08:44.21#ibcon#about to read 3, iclass 11, count 0 2006.201.06:08:44.26#ibcon#read 3, iclass 11, count 0 2006.201.06:08:44.26#ibcon#about to read 4, iclass 11, count 0 2006.201.06:08:44.26#ibcon#read 4, iclass 11, count 0 2006.201.06:08:44.26#ibcon#about to read 5, iclass 11, count 0 2006.201.06:08:44.26#ibcon#read 5, iclass 11, count 0 2006.201.06:08:44.26#ibcon#about to read 6, iclass 11, count 0 2006.201.06:08:44.26#ibcon#read 6, iclass 11, count 0 2006.201.06:08:44.26#ibcon#end of sib2, iclass 11, count 0 2006.201.06:08:44.26#ibcon#*after write, iclass 11, count 0 2006.201.06:08:44.26#ibcon#*before return 0, iclass 11, count 0 2006.201.06:08:44.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:44.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:44.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.06:08:44.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.06:08:44.26$vck44/va=2,7 2006.201.06:08:44.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.06:08:44.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.06:08:44.26#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:44.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:44.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:44.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:44.31#ibcon#enter wrdev, iclass 13, count 2 2006.201.06:08:44.31#ibcon#first serial, iclass 13, count 2 2006.201.06:08:44.31#ibcon#enter sib2, iclass 13, count 2 2006.201.06:08:44.31#ibcon#flushed, iclass 13, count 2 2006.201.06:08:44.31#ibcon#about to write, iclass 13, count 2 2006.201.06:08:44.31#ibcon#wrote, iclass 13, count 2 2006.201.06:08:44.31#ibcon#about to read 3, iclass 13, count 2 2006.201.06:08:44.33#ibcon#read 3, iclass 13, count 2 2006.201.06:08:44.33#ibcon#about to read 4, iclass 13, count 2 2006.201.06:08:44.33#ibcon#read 4, iclass 13, count 2 2006.201.06:08:44.33#ibcon#about to read 5, iclass 13, count 2 2006.201.06:08:44.33#ibcon#read 5, iclass 13, count 2 2006.201.06:08:44.33#ibcon#about to read 6, iclass 13, count 2 2006.201.06:08:44.33#ibcon#read 6, iclass 13, count 2 2006.201.06:08:44.33#ibcon#end of sib2, iclass 13, count 2 2006.201.06:08:44.33#ibcon#*mode == 0, iclass 13, count 2 2006.201.06:08:44.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.06:08:44.33#ibcon#[25=AT02-07\r\n] 2006.201.06:08:44.33#ibcon#*before write, iclass 13, count 2 2006.201.06:08:44.33#ibcon#enter sib2, iclass 13, count 2 2006.201.06:08:44.33#ibcon#flushed, iclass 13, count 2 2006.201.06:08:44.33#ibcon#about to write, iclass 13, count 2 2006.201.06:08:44.33#ibcon#wrote, iclass 13, count 2 2006.201.06:08:44.33#ibcon#about to read 3, iclass 13, count 2 2006.201.06:08:44.36#ibcon#read 3, iclass 13, count 2 2006.201.06:08:44.36#ibcon#about to read 4, iclass 13, count 2 2006.201.06:08:44.36#ibcon#read 4, iclass 13, count 2 2006.201.06:08:44.36#ibcon#about to read 5, iclass 13, count 2 2006.201.06:08:44.36#ibcon#read 5, iclass 13, count 2 2006.201.06:08:44.36#ibcon#about to read 6, iclass 13, count 2 2006.201.06:08:44.36#ibcon#read 6, iclass 13, count 2 2006.201.06:08:44.36#ibcon#end of sib2, iclass 13, count 2 2006.201.06:08:44.36#ibcon#*after write, iclass 13, count 2 2006.201.06:08:44.36#ibcon#*before return 0, iclass 13, count 2 2006.201.06:08:44.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:44.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:44.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.06:08:44.36#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:44.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:44.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:44.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:44.48#ibcon#enter wrdev, iclass 13, count 0 2006.201.06:08:44.48#ibcon#first serial, iclass 13, count 0 2006.201.06:08:44.48#ibcon#enter sib2, iclass 13, count 0 2006.201.06:08:44.48#ibcon#flushed, iclass 13, count 0 2006.201.06:08:44.48#ibcon#about to write, iclass 13, count 0 2006.201.06:08:44.48#ibcon#wrote, iclass 13, count 0 2006.201.06:08:44.48#ibcon#about to read 3, iclass 13, count 0 2006.201.06:08:44.50#ibcon#read 3, iclass 13, count 0 2006.201.06:08:44.50#ibcon#about to read 4, iclass 13, count 0 2006.201.06:08:44.50#ibcon#read 4, iclass 13, count 0 2006.201.06:08:44.50#ibcon#about to read 5, iclass 13, count 0 2006.201.06:08:44.50#ibcon#read 5, iclass 13, count 0 2006.201.06:08:44.50#ibcon#about to read 6, iclass 13, count 0 2006.201.06:08:44.50#ibcon#read 6, iclass 13, count 0 2006.201.06:08:44.50#ibcon#end of sib2, iclass 13, count 0 2006.201.06:08:44.50#ibcon#*mode == 0, iclass 13, count 0 2006.201.06:08:44.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.06:08:44.50#ibcon#[25=USB\r\n] 2006.201.06:08:44.50#ibcon#*before write, iclass 13, count 0 2006.201.06:08:44.50#ibcon#enter sib2, iclass 13, count 0 2006.201.06:08:44.50#ibcon#flushed, iclass 13, count 0 2006.201.06:08:44.50#ibcon#about to write, iclass 13, count 0 2006.201.06:08:44.50#ibcon#wrote, iclass 13, count 0 2006.201.06:08:44.50#ibcon#about to read 3, iclass 13, count 0 2006.201.06:08:44.53#ibcon#read 3, iclass 13, count 0 2006.201.06:08:44.53#ibcon#about to read 4, iclass 13, count 0 2006.201.06:08:44.53#ibcon#read 4, iclass 13, count 0 2006.201.06:08:44.53#ibcon#about to read 5, iclass 13, count 0 2006.201.06:08:44.53#ibcon#read 5, iclass 13, count 0 2006.201.06:08:44.53#ibcon#about to read 6, iclass 13, count 0 2006.201.06:08:44.53#ibcon#read 6, iclass 13, count 0 2006.201.06:08:44.53#ibcon#end of sib2, iclass 13, count 0 2006.201.06:08:44.53#ibcon#*after write, iclass 13, count 0 2006.201.06:08:44.53#ibcon#*before return 0, iclass 13, count 0 2006.201.06:08:44.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:44.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:44.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.06:08:44.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.06:08:44.53$vck44/valo=3,564.99 2006.201.06:08:44.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.06:08:44.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.06:08:44.53#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:44.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:44.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:44.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:44.53#ibcon#enter wrdev, iclass 15, count 0 2006.201.06:08:44.53#ibcon#first serial, iclass 15, count 0 2006.201.06:08:44.53#ibcon#enter sib2, iclass 15, count 0 2006.201.06:08:44.53#ibcon#flushed, iclass 15, count 0 2006.201.06:08:44.53#ibcon#about to write, iclass 15, count 0 2006.201.06:08:44.53#ibcon#wrote, iclass 15, count 0 2006.201.06:08:44.53#ibcon#about to read 3, iclass 15, count 0 2006.201.06:08:44.55#ibcon#read 3, iclass 15, count 0 2006.201.06:08:44.55#ibcon#about to read 4, iclass 15, count 0 2006.201.06:08:44.55#ibcon#read 4, iclass 15, count 0 2006.201.06:08:44.55#ibcon#about to read 5, iclass 15, count 0 2006.201.06:08:44.55#ibcon#read 5, iclass 15, count 0 2006.201.06:08:44.55#ibcon#about to read 6, iclass 15, count 0 2006.201.06:08:44.55#ibcon#read 6, iclass 15, count 0 2006.201.06:08:44.55#ibcon#end of sib2, iclass 15, count 0 2006.201.06:08:44.55#ibcon#*mode == 0, iclass 15, count 0 2006.201.06:08:44.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.06:08:44.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.06:08:44.55#ibcon#*before write, iclass 15, count 0 2006.201.06:08:44.55#ibcon#enter sib2, iclass 15, count 0 2006.201.06:08:44.55#ibcon#flushed, iclass 15, count 0 2006.201.06:08:44.55#ibcon#about to write, iclass 15, count 0 2006.201.06:08:44.55#ibcon#wrote, iclass 15, count 0 2006.201.06:08:44.55#ibcon#about to read 3, iclass 15, count 0 2006.201.06:08:44.60#ibcon#read 3, iclass 15, count 0 2006.201.06:08:44.60#ibcon#about to read 4, iclass 15, count 0 2006.201.06:08:44.60#ibcon#read 4, iclass 15, count 0 2006.201.06:08:44.60#ibcon#about to read 5, iclass 15, count 0 2006.201.06:08:44.60#ibcon#read 5, iclass 15, count 0 2006.201.06:08:44.60#ibcon#about to read 6, iclass 15, count 0 2006.201.06:08:44.60#ibcon#read 6, iclass 15, count 0 2006.201.06:08:44.60#ibcon#end of sib2, iclass 15, count 0 2006.201.06:08:44.60#ibcon#*after write, iclass 15, count 0 2006.201.06:08:44.60#ibcon#*before return 0, iclass 15, count 0 2006.201.06:08:44.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:44.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:44.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.06:08:44.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.06:08:44.60$vck44/va=3,8 2006.201.06:08:44.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.06:08:44.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.06:08:44.60#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:44.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:44.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:44.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:44.65#ibcon#enter wrdev, iclass 17, count 2 2006.201.06:08:44.65#ibcon#first serial, iclass 17, count 2 2006.201.06:08:44.65#ibcon#enter sib2, iclass 17, count 2 2006.201.06:08:44.65#ibcon#flushed, iclass 17, count 2 2006.201.06:08:44.65#ibcon#about to write, iclass 17, count 2 2006.201.06:08:44.65#ibcon#wrote, iclass 17, count 2 2006.201.06:08:44.65#ibcon#about to read 3, iclass 17, count 2 2006.201.06:08:44.67#ibcon#read 3, iclass 17, count 2 2006.201.06:08:44.67#ibcon#about to read 4, iclass 17, count 2 2006.201.06:08:44.67#ibcon#read 4, iclass 17, count 2 2006.201.06:08:44.67#ibcon#about to read 5, iclass 17, count 2 2006.201.06:08:44.67#ibcon#read 5, iclass 17, count 2 2006.201.06:08:44.67#ibcon#about to read 6, iclass 17, count 2 2006.201.06:08:44.67#ibcon#read 6, iclass 17, count 2 2006.201.06:08:44.67#ibcon#end of sib2, iclass 17, count 2 2006.201.06:08:44.67#ibcon#*mode == 0, iclass 17, count 2 2006.201.06:08:44.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.06:08:44.67#ibcon#[25=AT03-08\r\n] 2006.201.06:08:44.67#ibcon#*before write, iclass 17, count 2 2006.201.06:08:44.67#ibcon#enter sib2, iclass 17, count 2 2006.201.06:08:44.67#ibcon#flushed, iclass 17, count 2 2006.201.06:08:44.67#ibcon#about to write, iclass 17, count 2 2006.201.06:08:44.67#ibcon#wrote, iclass 17, count 2 2006.201.06:08:44.67#ibcon#about to read 3, iclass 17, count 2 2006.201.06:08:44.70#ibcon#read 3, iclass 17, count 2 2006.201.06:08:44.70#ibcon#about to read 4, iclass 17, count 2 2006.201.06:08:44.70#ibcon#read 4, iclass 17, count 2 2006.201.06:08:44.70#ibcon#about to read 5, iclass 17, count 2 2006.201.06:08:44.70#ibcon#read 5, iclass 17, count 2 2006.201.06:08:44.70#ibcon#about to read 6, iclass 17, count 2 2006.201.06:08:44.70#ibcon#read 6, iclass 17, count 2 2006.201.06:08:44.70#ibcon#end of sib2, iclass 17, count 2 2006.201.06:08:44.70#ibcon#*after write, iclass 17, count 2 2006.201.06:08:44.70#ibcon#*before return 0, iclass 17, count 2 2006.201.06:08:44.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:44.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:44.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.06:08:44.70#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:44.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:44.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:44.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:44.82#ibcon#enter wrdev, iclass 17, count 0 2006.201.06:08:44.82#ibcon#first serial, iclass 17, count 0 2006.201.06:08:44.82#ibcon#enter sib2, iclass 17, count 0 2006.201.06:08:44.82#ibcon#flushed, iclass 17, count 0 2006.201.06:08:44.82#ibcon#about to write, iclass 17, count 0 2006.201.06:08:44.82#ibcon#wrote, iclass 17, count 0 2006.201.06:08:44.82#ibcon#about to read 3, iclass 17, count 0 2006.201.06:08:44.84#ibcon#read 3, iclass 17, count 0 2006.201.06:08:44.84#ibcon#about to read 4, iclass 17, count 0 2006.201.06:08:44.84#ibcon#read 4, iclass 17, count 0 2006.201.06:08:44.84#ibcon#about to read 5, iclass 17, count 0 2006.201.06:08:44.84#ibcon#read 5, iclass 17, count 0 2006.201.06:08:44.84#ibcon#about to read 6, iclass 17, count 0 2006.201.06:08:44.84#ibcon#read 6, iclass 17, count 0 2006.201.06:08:44.84#ibcon#end of sib2, iclass 17, count 0 2006.201.06:08:44.84#ibcon#*mode == 0, iclass 17, count 0 2006.201.06:08:44.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.06:08:44.84#ibcon#[25=USB\r\n] 2006.201.06:08:44.84#ibcon#*before write, iclass 17, count 0 2006.201.06:08:44.84#ibcon#enter sib2, iclass 17, count 0 2006.201.06:08:44.84#ibcon#flushed, iclass 17, count 0 2006.201.06:08:44.84#ibcon#about to write, iclass 17, count 0 2006.201.06:08:44.84#ibcon#wrote, iclass 17, count 0 2006.201.06:08:44.84#ibcon#about to read 3, iclass 17, count 0 2006.201.06:08:44.87#ibcon#read 3, iclass 17, count 0 2006.201.06:08:44.87#ibcon#about to read 4, iclass 17, count 0 2006.201.06:08:44.87#ibcon#read 4, iclass 17, count 0 2006.201.06:08:44.87#ibcon#about to read 5, iclass 17, count 0 2006.201.06:08:44.87#ibcon#read 5, iclass 17, count 0 2006.201.06:08:44.87#ibcon#about to read 6, iclass 17, count 0 2006.201.06:08:44.87#ibcon#read 6, iclass 17, count 0 2006.201.06:08:44.87#ibcon#end of sib2, iclass 17, count 0 2006.201.06:08:44.87#ibcon#*after write, iclass 17, count 0 2006.201.06:08:44.87#ibcon#*before return 0, iclass 17, count 0 2006.201.06:08:44.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:44.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:44.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.06:08:44.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.06:08:44.87$vck44/valo=4,624.99 2006.201.06:08:44.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.06:08:44.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.06:08:44.87#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:44.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:44.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:44.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:44.87#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:08:44.87#ibcon#first serial, iclass 19, count 0 2006.201.06:08:44.87#ibcon#enter sib2, iclass 19, count 0 2006.201.06:08:44.87#ibcon#flushed, iclass 19, count 0 2006.201.06:08:44.87#ibcon#about to write, iclass 19, count 0 2006.201.06:08:44.87#ibcon#wrote, iclass 19, count 0 2006.201.06:08:44.87#ibcon#about to read 3, iclass 19, count 0 2006.201.06:08:44.89#ibcon#read 3, iclass 19, count 0 2006.201.06:08:44.89#ibcon#about to read 4, iclass 19, count 0 2006.201.06:08:44.89#ibcon#read 4, iclass 19, count 0 2006.201.06:08:44.89#ibcon#about to read 5, iclass 19, count 0 2006.201.06:08:44.89#ibcon#read 5, iclass 19, count 0 2006.201.06:08:44.89#ibcon#about to read 6, iclass 19, count 0 2006.201.06:08:44.89#ibcon#read 6, iclass 19, count 0 2006.201.06:08:44.89#ibcon#end of sib2, iclass 19, count 0 2006.201.06:08:44.89#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:08:44.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:08:44.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.06:08:44.89#ibcon#*before write, iclass 19, count 0 2006.201.06:08:44.89#ibcon#enter sib2, iclass 19, count 0 2006.201.06:08:44.89#ibcon#flushed, iclass 19, count 0 2006.201.06:08:44.89#ibcon#about to write, iclass 19, count 0 2006.201.06:08:44.89#ibcon#wrote, iclass 19, count 0 2006.201.06:08:44.89#ibcon#about to read 3, iclass 19, count 0 2006.201.06:08:44.94#ibcon#read 3, iclass 19, count 0 2006.201.06:08:44.94#ibcon#about to read 4, iclass 19, count 0 2006.201.06:08:44.94#ibcon#read 4, iclass 19, count 0 2006.201.06:08:44.94#ibcon#about to read 5, iclass 19, count 0 2006.201.06:08:44.94#ibcon#read 5, iclass 19, count 0 2006.201.06:08:44.94#ibcon#about to read 6, iclass 19, count 0 2006.201.06:08:44.94#ibcon#read 6, iclass 19, count 0 2006.201.06:08:44.94#ibcon#end of sib2, iclass 19, count 0 2006.201.06:08:44.94#ibcon#*after write, iclass 19, count 0 2006.201.06:08:44.94#ibcon#*before return 0, iclass 19, count 0 2006.201.06:08:44.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:44.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:44.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:08:44.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:08:44.94$vck44/va=4,7 2006.201.06:08:44.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.06:08:44.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.06:08:44.94#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:44.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:44.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:44.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:44.99#ibcon#enter wrdev, iclass 21, count 2 2006.201.06:08:44.99#ibcon#first serial, iclass 21, count 2 2006.201.06:08:44.99#ibcon#enter sib2, iclass 21, count 2 2006.201.06:08:44.99#ibcon#flushed, iclass 21, count 2 2006.201.06:08:44.99#ibcon#about to write, iclass 21, count 2 2006.201.06:08:44.99#ibcon#wrote, iclass 21, count 2 2006.201.06:08:44.99#ibcon#about to read 3, iclass 21, count 2 2006.201.06:08:45.01#ibcon#read 3, iclass 21, count 2 2006.201.06:08:45.01#ibcon#about to read 4, iclass 21, count 2 2006.201.06:08:45.01#ibcon#read 4, iclass 21, count 2 2006.201.06:08:45.01#ibcon#about to read 5, iclass 21, count 2 2006.201.06:08:45.01#ibcon#read 5, iclass 21, count 2 2006.201.06:08:45.01#ibcon#about to read 6, iclass 21, count 2 2006.201.06:08:45.01#ibcon#read 6, iclass 21, count 2 2006.201.06:08:45.01#ibcon#end of sib2, iclass 21, count 2 2006.201.06:08:45.01#ibcon#*mode == 0, iclass 21, count 2 2006.201.06:08:45.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.06:08:45.01#ibcon#[25=AT04-07\r\n] 2006.201.06:08:45.01#ibcon#*before write, iclass 21, count 2 2006.201.06:08:45.01#ibcon#enter sib2, iclass 21, count 2 2006.201.06:08:45.01#ibcon#flushed, iclass 21, count 2 2006.201.06:08:45.01#ibcon#about to write, iclass 21, count 2 2006.201.06:08:45.01#ibcon#wrote, iclass 21, count 2 2006.201.06:08:45.01#ibcon#about to read 3, iclass 21, count 2 2006.201.06:08:45.04#ibcon#read 3, iclass 21, count 2 2006.201.06:08:45.04#ibcon#about to read 4, iclass 21, count 2 2006.201.06:08:45.04#ibcon#read 4, iclass 21, count 2 2006.201.06:08:45.04#ibcon#about to read 5, iclass 21, count 2 2006.201.06:08:45.04#ibcon#read 5, iclass 21, count 2 2006.201.06:08:45.04#ibcon#about to read 6, iclass 21, count 2 2006.201.06:08:45.04#ibcon#read 6, iclass 21, count 2 2006.201.06:08:45.04#ibcon#end of sib2, iclass 21, count 2 2006.201.06:08:45.04#ibcon#*after write, iclass 21, count 2 2006.201.06:08:45.04#ibcon#*before return 0, iclass 21, count 2 2006.201.06:08:45.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:45.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:45.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.06:08:45.04#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:45.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:45.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:45.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:45.16#ibcon#enter wrdev, iclass 21, count 0 2006.201.06:08:45.16#ibcon#first serial, iclass 21, count 0 2006.201.06:08:45.16#ibcon#enter sib2, iclass 21, count 0 2006.201.06:08:45.16#ibcon#flushed, iclass 21, count 0 2006.201.06:08:45.16#ibcon#about to write, iclass 21, count 0 2006.201.06:08:45.16#ibcon#wrote, iclass 21, count 0 2006.201.06:08:45.16#ibcon#about to read 3, iclass 21, count 0 2006.201.06:08:45.18#ibcon#read 3, iclass 21, count 0 2006.201.06:08:45.18#ibcon#about to read 4, iclass 21, count 0 2006.201.06:08:45.18#ibcon#read 4, iclass 21, count 0 2006.201.06:08:45.18#ibcon#about to read 5, iclass 21, count 0 2006.201.06:08:45.18#ibcon#read 5, iclass 21, count 0 2006.201.06:08:45.18#ibcon#about to read 6, iclass 21, count 0 2006.201.06:08:45.18#ibcon#read 6, iclass 21, count 0 2006.201.06:08:45.18#ibcon#end of sib2, iclass 21, count 0 2006.201.06:08:45.18#ibcon#*mode == 0, iclass 21, count 0 2006.201.06:08:45.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.06:08:45.18#ibcon#[25=USB\r\n] 2006.201.06:08:45.18#ibcon#*before write, iclass 21, count 0 2006.201.06:08:45.18#ibcon#enter sib2, iclass 21, count 0 2006.201.06:08:45.18#ibcon#flushed, iclass 21, count 0 2006.201.06:08:45.18#ibcon#about to write, iclass 21, count 0 2006.201.06:08:45.18#ibcon#wrote, iclass 21, count 0 2006.201.06:08:45.18#ibcon#about to read 3, iclass 21, count 0 2006.201.06:08:45.21#ibcon#read 3, iclass 21, count 0 2006.201.06:08:45.21#ibcon#about to read 4, iclass 21, count 0 2006.201.06:08:45.21#ibcon#read 4, iclass 21, count 0 2006.201.06:08:45.21#ibcon#about to read 5, iclass 21, count 0 2006.201.06:08:45.21#ibcon#read 5, iclass 21, count 0 2006.201.06:08:45.21#ibcon#about to read 6, iclass 21, count 0 2006.201.06:08:45.21#ibcon#read 6, iclass 21, count 0 2006.201.06:08:45.21#ibcon#end of sib2, iclass 21, count 0 2006.201.06:08:45.21#ibcon#*after write, iclass 21, count 0 2006.201.06:08:45.21#ibcon#*before return 0, iclass 21, count 0 2006.201.06:08:45.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:45.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:45.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.06:08:45.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.06:08:45.21$vck44/valo=5,734.99 2006.201.06:08:45.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.06:08:45.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.06:08:45.21#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:45.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:45.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:45.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:45.21#ibcon#enter wrdev, iclass 23, count 0 2006.201.06:08:45.21#ibcon#first serial, iclass 23, count 0 2006.201.06:08:45.21#ibcon#enter sib2, iclass 23, count 0 2006.201.06:08:45.21#ibcon#flushed, iclass 23, count 0 2006.201.06:08:45.21#ibcon#about to write, iclass 23, count 0 2006.201.06:08:45.21#ibcon#wrote, iclass 23, count 0 2006.201.06:08:45.21#ibcon#about to read 3, iclass 23, count 0 2006.201.06:08:45.23#ibcon#read 3, iclass 23, count 0 2006.201.06:08:45.23#ibcon#about to read 4, iclass 23, count 0 2006.201.06:08:45.23#ibcon#read 4, iclass 23, count 0 2006.201.06:08:45.23#ibcon#about to read 5, iclass 23, count 0 2006.201.06:08:45.23#ibcon#read 5, iclass 23, count 0 2006.201.06:08:45.23#ibcon#about to read 6, iclass 23, count 0 2006.201.06:08:45.23#ibcon#read 6, iclass 23, count 0 2006.201.06:08:45.23#ibcon#end of sib2, iclass 23, count 0 2006.201.06:08:45.23#ibcon#*mode == 0, iclass 23, count 0 2006.201.06:08:45.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.06:08:45.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.06:08:45.23#ibcon#*before write, iclass 23, count 0 2006.201.06:08:45.23#ibcon#enter sib2, iclass 23, count 0 2006.201.06:08:45.23#ibcon#flushed, iclass 23, count 0 2006.201.06:08:45.23#ibcon#about to write, iclass 23, count 0 2006.201.06:08:45.23#ibcon#wrote, iclass 23, count 0 2006.201.06:08:45.23#ibcon#about to read 3, iclass 23, count 0 2006.201.06:08:45.27#ibcon#read 3, iclass 23, count 0 2006.201.06:08:45.27#ibcon#about to read 4, iclass 23, count 0 2006.201.06:08:45.27#ibcon#read 4, iclass 23, count 0 2006.201.06:08:45.27#ibcon#about to read 5, iclass 23, count 0 2006.201.06:08:45.27#ibcon#read 5, iclass 23, count 0 2006.201.06:08:45.27#ibcon#about to read 6, iclass 23, count 0 2006.201.06:08:45.27#ibcon#read 6, iclass 23, count 0 2006.201.06:08:45.27#ibcon#end of sib2, iclass 23, count 0 2006.201.06:08:45.27#ibcon#*after write, iclass 23, count 0 2006.201.06:08:45.27#ibcon#*before return 0, iclass 23, count 0 2006.201.06:08:45.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:45.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:45.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.06:08:45.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.06:08:45.27$vck44/va=5,4 2006.201.06:08:45.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.06:08:45.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.06:08:45.27#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:45.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:45.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:45.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:45.33#ibcon#enter wrdev, iclass 25, count 2 2006.201.06:08:45.33#ibcon#first serial, iclass 25, count 2 2006.201.06:08:45.33#ibcon#enter sib2, iclass 25, count 2 2006.201.06:08:45.33#ibcon#flushed, iclass 25, count 2 2006.201.06:08:45.33#ibcon#about to write, iclass 25, count 2 2006.201.06:08:45.33#ibcon#wrote, iclass 25, count 2 2006.201.06:08:45.33#ibcon#about to read 3, iclass 25, count 2 2006.201.06:08:45.35#ibcon#read 3, iclass 25, count 2 2006.201.06:08:45.35#ibcon#about to read 4, iclass 25, count 2 2006.201.06:08:45.35#ibcon#read 4, iclass 25, count 2 2006.201.06:08:45.35#ibcon#about to read 5, iclass 25, count 2 2006.201.06:08:45.35#ibcon#read 5, iclass 25, count 2 2006.201.06:08:45.35#ibcon#about to read 6, iclass 25, count 2 2006.201.06:08:45.35#ibcon#read 6, iclass 25, count 2 2006.201.06:08:45.35#ibcon#end of sib2, iclass 25, count 2 2006.201.06:08:45.35#ibcon#*mode == 0, iclass 25, count 2 2006.201.06:08:45.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.06:08:45.35#ibcon#[25=AT05-04\r\n] 2006.201.06:08:45.35#ibcon#*before write, iclass 25, count 2 2006.201.06:08:45.35#ibcon#enter sib2, iclass 25, count 2 2006.201.06:08:45.35#ibcon#flushed, iclass 25, count 2 2006.201.06:08:45.35#ibcon#about to write, iclass 25, count 2 2006.201.06:08:45.35#ibcon#wrote, iclass 25, count 2 2006.201.06:08:45.35#ibcon#about to read 3, iclass 25, count 2 2006.201.06:08:45.38#ibcon#read 3, iclass 25, count 2 2006.201.06:08:45.38#ibcon#about to read 4, iclass 25, count 2 2006.201.06:08:45.38#ibcon#read 4, iclass 25, count 2 2006.201.06:08:45.38#ibcon#about to read 5, iclass 25, count 2 2006.201.06:08:45.38#ibcon#read 5, iclass 25, count 2 2006.201.06:08:45.38#ibcon#about to read 6, iclass 25, count 2 2006.201.06:08:45.38#ibcon#read 6, iclass 25, count 2 2006.201.06:08:45.38#ibcon#end of sib2, iclass 25, count 2 2006.201.06:08:45.38#ibcon#*after write, iclass 25, count 2 2006.201.06:08:45.38#ibcon#*before return 0, iclass 25, count 2 2006.201.06:08:45.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:45.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:45.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.06:08:45.38#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:45.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:45.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:45.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:45.50#ibcon#enter wrdev, iclass 25, count 0 2006.201.06:08:45.50#ibcon#first serial, iclass 25, count 0 2006.201.06:08:45.50#ibcon#enter sib2, iclass 25, count 0 2006.201.06:08:45.50#ibcon#flushed, iclass 25, count 0 2006.201.06:08:45.50#ibcon#about to write, iclass 25, count 0 2006.201.06:08:45.50#ibcon#wrote, iclass 25, count 0 2006.201.06:08:45.50#ibcon#about to read 3, iclass 25, count 0 2006.201.06:08:45.52#ibcon#read 3, iclass 25, count 0 2006.201.06:08:45.52#ibcon#about to read 4, iclass 25, count 0 2006.201.06:08:45.52#ibcon#read 4, iclass 25, count 0 2006.201.06:08:45.52#ibcon#about to read 5, iclass 25, count 0 2006.201.06:08:45.52#ibcon#read 5, iclass 25, count 0 2006.201.06:08:45.52#ibcon#about to read 6, iclass 25, count 0 2006.201.06:08:45.52#ibcon#read 6, iclass 25, count 0 2006.201.06:08:45.52#ibcon#end of sib2, iclass 25, count 0 2006.201.06:08:45.52#ibcon#*mode == 0, iclass 25, count 0 2006.201.06:08:45.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.06:08:45.52#ibcon#[25=USB\r\n] 2006.201.06:08:45.52#ibcon#*before write, iclass 25, count 0 2006.201.06:08:45.52#ibcon#enter sib2, iclass 25, count 0 2006.201.06:08:45.52#ibcon#flushed, iclass 25, count 0 2006.201.06:08:45.52#ibcon#about to write, iclass 25, count 0 2006.201.06:08:45.52#ibcon#wrote, iclass 25, count 0 2006.201.06:08:45.52#ibcon#about to read 3, iclass 25, count 0 2006.201.06:08:45.55#ibcon#read 3, iclass 25, count 0 2006.201.06:08:45.55#ibcon#about to read 4, iclass 25, count 0 2006.201.06:08:45.55#ibcon#read 4, iclass 25, count 0 2006.201.06:08:45.55#ibcon#about to read 5, iclass 25, count 0 2006.201.06:08:45.55#ibcon#read 5, iclass 25, count 0 2006.201.06:08:45.55#ibcon#about to read 6, iclass 25, count 0 2006.201.06:08:45.55#ibcon#read 6, iclass 25, count 0 2006.201.06:08:45.55#ibcon#end of sib2, iclass 25, count 0 2006.201.06:08:45.55#ibcon#*after write, iclass 25, count 0 2006.201.06:08:45.55#ibcon#*before return 0, iclass 25, count 0 2006.201.06:08:45.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:45.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:45.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.06:08:45.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.06:08:45.55$vck44/valo=6,814.99 2006.201.06:08:45.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.06:08:45.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.06:08:45.55#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:45.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:45.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:45.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:45.55#ibcon#enter wrdev, iclass 27, count 0 2006.201.06:08:45.55#ibcon#first serial, iclass 27, count 0 2006.201.06:08:45.55#ibcon#enter sib2, iclass 27, count 0 2006.201.06:08:45.55#ibcon#flushed, iclass 27, count 0 2006.201.06:08:45.55#ibcon#about to write, iclass 27, count 0 2006.201.06:08:45.55#ibcon#wrote, iclass 27, count 0 2006.201.06:08:45.55#ibcon#about to read 3, iclass 27, count 0 2006.201.06:08:45.57#ibcon#read 3, iclass 27, count 0 2006.201.06:08:45.57#ibcon#about to read 4, iclass 27, count 0 2006.201.06:08:45.57#ibcon#read 4, iclass 27, count 0 2006.201.06:08:45.57#ibcon#about to read 5, iclass 27, count 0 2006.201.06:08:45.57#ibcon#read 5, iclass 27, count 0 2006.201.06:08:45.57#ibcon#about to read 6, iclass 27, count 0 2006.201.06:08:45.57#ibcon#read 6, iclass 27, count 0 2006.201.06:08:45.57#ibcon#end of sib2, iclass 27, count 0 2006.201.06:08:45.57#ibcon#*mode == 0, iclass 27, count 0 2006.201.06:08:45.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.06:08:45.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.06:08:45.57#ibcon#*before write, iclass 27, count 0 2006.201.06:08:45.57#ibcon#enter sib2, iclass 27, count 0 2006.201.06:08:45.57#ibcon#flushed, iclass 27, count 0 2006.201.06:08:45.57#ibcon#about to write, iclass 27, count 0 2006.201.06:08:45.57#ibcon#wrote, iclass 27, count 0 2006.201.06:08:45.57#ibcon#about to read 3, iclass 27, count 0 2006.201.06:08:45.62#ibcon#read 3, iclass 27, count 0 2006.201.06:08:45.62#ibcon#about to read 4, iclass 27, count 0 2006.201.06:08:45.62#ibcon#read 4, iclass 27, count 0 2006.201.06:08:45.62#ibcon#about to read 5, iclass 27, count 0 2006.201.06:08:45.62#ibcon#read 5, iclass 27, count 0 2006.201.06:08:45.62#ibcon#about to read 6, iclass 27, count 0 2006.201.06:08:45.62#ibcon#read 6, iclass 27, count 0 2006.201.06:08:45.62#ibcon#end of sib2, iclass 27, count 0 2006.201.06:08:45.62#ibcon#*after write, iclass 27, count 0 2006.201.06:08:45.62#ibcon#*before return 0, iclass 27, count 0 2006.201.06:08:45.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:45.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:45.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.06:08:45.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.06:08:45.62$vck44/va=6,5 2006.201.06:08:45.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.06:08:45.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.06:08:45.62#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:45.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:45.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:45.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:45.67#ibcon#enter wrdev, iclass 29, count 2 2006.201.06:08:45.67#ibcon#first serial, iclass 29, count 2 2006.201.06:08:45.67#ibcon#enter sib2, iclass 29, count 2 2006.201.06:08:45.67#ibcon#flushed, iclass 29, count 2 2006.201.06:08:45.67#ibcon#about to write, iclass 29, count 2 2006.201.06:08:45.67#ibcon#wrote, iclass 29, count 2 2006.201.06:08:45.67#ibcon#about to read 3, iclass 29, count 2 2006.201.06:08:45.69#ibcon#read 3, iclass 29, count 2 2006.201.06:08:45.69#ibcon#about to read 4, iclass 29, count 2 2006.201.06:08:45.69#ibcon#read 4, iclass 29, count 2 2006.201.06:08:45.69#ibcon#about to read 5, iclass 29, count 2 2006.201.06:08:45.69#ibcon#read 5, iclass 29, count 2 2006.201.06:08:45.69#ibcon#about to read 6, iclass 29, count 2 2006.201.06:08:45.69#ibcon#read 6, iclass 29, count 2 2006.201.06:08:45.69#ibcon#end of sib2, iclass 29, count 2 2006.201.06:08:45.69#ibcon#*mode == 0, iclass 29, count 2 2006.201.06:08:45.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.06:08:45.69#ibcon#[25=AT06-05\r\n] 2006.201.06:08:45.69#ibcon#*before write, iclass 29, count 2 2006.201.06:08:45.69#ibcon#enter sib2, iclass 29, count 2 2006.201.06:08:45.69#ibcon#flushed, iclass 29, count 2 2006.201.06:08:45.69#ibcon#about to write, iclass 29, count 2 2006.201.06:08:45.69#ibcon#wrote, iclass 29, count 2 2006.201.06:08:45.69#ibcon#about to read 3, iclass 29, count 2 2006.201.06:08:45.72#ibcon#read 3, iclass 29, count 2 2006.201.06:08:45.72#ibcon#about to read 4, iclass 29, count 2 2006.201.06:08:45.72#ibcon#read 4, iclass 29, count 2 2006.201.06:08:45.72#ibcon#about to read 5, iclass 29, count 2 2006.201.06:08:45.72#ibcon#read 5, iclass 29, count 2 2006.201.06:08:45.72#ibcon#about to read 6, iclass 29, count 2 2006.201.06:08:45.72#ibcon#read 6, iclass 29, count 2 2006.201.06:08:45.72#ibcon#end of sib2, iclass 29, count 2 2006.201.06:08:45.72#ibcon#*after write, iclass 29, count 2 2006.201.06:08:45.72#ibcon#*before return 0, iclass 29, count 2 2006.201.06:08:45.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:45.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:45.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.06:08:45.72#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:45.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:45.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:45.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:45.84#ibcon#enter wrdev, iclass 29, count 0 2006.201.06:08:45.84#ibcon#first serial, iclass 29, count 0 2006.201.06:08:45.84#ibcon#enter sib2, iclass 29, count 0 2006.201.06:08:45.84#ibcon#flushed, iclass 29, count 0 2006.201.06:08:45.84#ibcon#about to write, iclass 29, count 0 2006.201.06:08:45.84#ibcon#wrote, iclass 29, count 0 2006.201.06:08:45.84#ibcon#about to read 3, iclass 29, count 0 2006.201.06:08:45.86#ibcon#read 3, iclass 29, count 0 2006.201.06:08:45.86#ibcon#about to read 4, iclass 29, count 0 2006.201.06:08:45.86#ibcon#read 4, iclass 29, count 0 2006.201.06:08:45.86#ibcon#about to read 5, iclass 29, count 0 2006.201.06:08:45.86#ibcon#read 5, iclass 29, count 0 2006.201.06:08:45.86#ibcon#about to read 6, iclass 29, count 0 2006.201.06:08:45.86#ibcon#read 6, iclass 29, count 0 2006.201.06:08:45.86#ibcon#end of sib2, iclass 29, count 0 2006.201.06:08:45.86#ibcon#*mode == 0, iclass 29, count 0 2006.201.06:08:45.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.06:08:45.86#ibcon#[25=USB\r\n] 2006.201.06:08:45.86#ibcon#*before write, iclass 29, count 0 2006.201.06:08:45.86#ibcon#enter sib2, iclass 29, count 0 2006.201.06:08:45.86#ibcon#flushed, iclass 29, count 0 2006.201.06:08:45.86#ibcon#about to write, iclass 29, count 0 2006.201.06:08:45.86#ibcon#wrote, iclass 29, count 0 2006.201.06:08:45.86#ibcon#about to read 3, iclass 29, count 0 2006.201.06:08:45.89#ibcon#read 3, iclass 29, count 0 2006.201.06:08:45.89#ibcon#about to read 4, iclass 29, count 0 2006.201.06:08:45.89#ibcon#read 4, iclass 29, count 0 2006.201.06:08:45.89#ibcon#about to read 5, iclass 29, count 0 2006.201.06:08:45.89#ibcon#read 5, iclass 29, count 0 2006.201.06:08:45.89#ibcon#about to read 6, iclass 29, count 0 2006.201.06:08:45.89#ibcon#read 6, iclass 29, count 0 2006.201.06:08:45.89#ibcon#end of sib2, iclass 29, count 0 2006.201.06:08:45.89#ibcon#*after write, iclass 29, count 0 2006.201.06:08:45.89#ibcon#*before return 0, iclass 29, count 0 2006.201.06:08:45.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:45.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:45.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.06:08:45.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.06:08:45.89$vck44/valo=7,864.99 2006.201.06:08:45.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.06:08:45.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.06:08:45.89#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:45.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:45.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:45.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:45.89#ibcon#enter wrdev, iclass 31, count 0 2006.201.06:08:45.89#ibcon#first serial, iclass 31, count 0 2006.201.06:08:45.89#ibcon#enter sib2, iclass 31, count 0 2006.201.06:08:45.89#ibcon#flushed, iclass 31, count 0 2006.201.06:08:45.89#ibcon#about to write, iclass 31, count 0 2006.201.06:08:45.89#ibcon#wrote, iclass 31, count 0 2006.201.06:08:45.89#ibcon#about to read 3, iclass 31, count 0 2006.201.06:08:45.91#ibcon#read 3, iclass 31, count 0 2006.201.06:08:45.91#ibcon#about to read 4, iclass 31, count 0 2006.201.06:08:45.91#ibcon#read 4, iclass 31, count 0 2006.201.06:08:45.91#ibcon#about to read 5, iclass 31, count 0 2006.201.06:08:45.91#ibcon#read 5, iclass 31, count 0 2006.201.06:08:45.91#ibcon#about to read 6, iclass 31, count 0 2006.201.06:08:45.91#ibcon#read 6, iclass 31, count 0 2006.201.06:08:45.91#ibcon#end of sib2, iclass 31, count 0 2006.201.06:08:45.91#ibcon#*mode == 0, iclass 31, count 0 2006.201.06:08:45.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.06:08:45.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.06:08:45.91#ibcon#*before write, iclass 31, count 0 2006.201.06:08:45.91#ibcon#enter sib2, iclass 31, count 0 2006.201.06:08:45.91#ibcon#flushed, iclass 31, count 0 2006.201.06:08:45.91#ibcon#about to write, iclass 31, count 0 2006.201.06:08:45.91#ibcon#wrote, iclass 31, count 0 2006.201.06:08:45.91#ibcon#about to read 3, iclass 31, count 0 2006.201.06:08:45.96#ibcon#read 3, iclass 31, count 0 2006.201.06:08:45.96#ibcon#about to read 4, iclass 31, count 0 2006.201.06:08:45.96#ibcon#read 4, iclass 31, count 0 2006.201.06:08:45.96#ibcon#about to read 5, iclass 31, count 0 2006.201.06:08:45.96#ibcon#read 5, iclass 31, count 0 2006.201.06:08:45.96#ibcon#about to read 6, iclass 31, count 0 2006.201.06:08:45.96#ibcon#read 6, iclass 31, count 0 2006.201.06:08:45.96#ibcon#end of sib2, iclass 31, count 0 2006.201.06:08:45.96#ibcon#*after write, iclass 31, count 0 2006.201.06:08:45.96#ibcon#*before return 0, iclass 31, count 0 2006.201.06:08:45.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:45.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:45.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.06:08:45.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.06:08:45.96$vck44/va=7,5 2006.201.06:08:45.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.06:08:45.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.06:08:45.96#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:45.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:46.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:46.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:46.01#ibcon#enter wrdev, iclass 33, count 2 2006.201.06:08:46.01#ibcon#first serial, iclass 33, count 2 2006.201.06:08:46.01#ibcon#enter sib2, iclass 33, count 2 2006.201.06:08:46.01#ibcon#flushed, iclass 33, count 2 2006.201.06:08:46.01#ibcon#about to write, iclass 33, count 2 2006.201.06:08:46.01#ibcon#wrote, iclass 33, count 2 2006.201.06:08:46.01#ibcon#about to read 3, iclass 33, count 2 2006.201.06:08:46.03#ibcon#read 3, iclass 33, count 2 2006.201.06:08:46.03#ibcon#about to read 4, iclass 33, count 2 2006.201.06:08:46.03#ibcon#read 4, iclass 33, count 2 2006.201.06:08:46.03#ibcon#about to read 5, iclass 33, count 2 2006.201.06:08:46.03#ibcon#read 5, iclass 33, count 2 2006.201.06:08:46.03#ibcon#about to read 6, iclass 33, count 2 2006.201.06:08:46.03#ibcon#read 6, iclass 33, count 2 2006.201.06:08:46.03#ibcon#end of sib2, iclass 33, count 2 2006.201.06:08:46.03#ibcon#*mode == 0, iclass 33, count 2 2006.201.06:08:46.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.06:08:46.03#ibcon#[25=AT07-05\r\n] 2006.201.06:08:46.03#ibcon#*before write, iclass 33, count 2 2006.201.06:08:46.03#ibcon#enter sib2, iclass 33, count 2 2006.201.06:08:46.03#ibcon#flushed, iclass 33, count 2 2006.201.06:08:46.03#ibcon#about to write, iclass 33, count 2 2006.201.06:08:46.03#ibcon#wrote, iclass 33, count 2 2006.201.06:08:46.03#ibcon#about to read 3, iclass 33, count 2 2006.201.06:08:46.06#ibcon#read 3, iclass 33, count 2 2006.201.06:08:46.06#ibcon#about to read 4, iclass 33, count 2 2006.201.06:08:46.06#ibcon#read 4, iclass 33, count 2 2006.201.06:08:46.06#ibcon#about to read 5, iclass 33, count 2 2006.201.06:08:46.06#ibcon#read 5, iclass 33, count 2 2006.201.06:08:46.06#ibcon#about to read 6, iclass 33, count 2 2006.201.06:08:46.06#ibcon#read 6, iclass 33, count 2 2006.201.06:08:46.06#ibcon#end of sib2, iclass 33, count 2 2006.201.06:08:46.06#ibcon#*after write, iclass 33, count 2 2006.201.06:08:46.06#ibcon#*before return 0, iclass 33, count 2 2006.201.06:08:46.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:46.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:46.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.06:08:46.06#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:46.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:46.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:46.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:46.18#ibcon#enter wrdev, iclass 33, count 0 2006.201.06:08:46.18#ibcon#first serial, iclass 33, count 0 2006.201.06:08:46.18#ibcon#enter sib2, iclass 33, count 0 2006.201.06:08:46.18#ibcon#flushed, iclass 33, count 0 2006.201.06:08:46.18#ibcon#about to write, iclass 33, count 0 2006.201.06:08:46.18#ibcon#wrote, iclass 33, count 0 2006.201.06:08:46.18#ibcon#about to read 3, iclass 33, count 0 2006.201.06:08:46.20#ibcon#read 3, iclass 33, count 0 2006.201.06:08:46.20#ibcon#about to read 4, iclass 33, count 0 2006.201.06:08:46.20#ibcon#read 4, iclass 33, count 0 2006.201.06:08:46.20#ibcon#about to read 5, iclass 33, count 0 2006.201.06:08:46.20#ibcon#read 5, iclass 33, count 0 2006.201.06:08:46.20#ibcon#about to read 6, iclass 33, count 0 2006.201.06:08:46.20#ibcon#read 6, iclass 33, count 0 2006.201.06:08:46.20#ibcon#end of sib2, iclass 33, count 0 2006.201.06:08:46.20#ibcon#*mode == 0, iclass 33, count 0 2006.201.06:08:46.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.06:08:46.20#ibcon#[25=USB\r\n] 2006.201.06:08:46.20#ibcon#*before write, iclass 33, count 0 2006.201.06:08:46.20#ibcon#enter sib2, iclass 33, count 0 2006.201.06:08:46.20#ibcon#flushed, iclass 33, count 0 2006.201.06:08:46.20#ibcon#about to write, iclass 33, count 0 2006.201.06:08:46.20#ibcon#wrote, iclass 33, count 0 2006.201.06:08:46.20#ibcon#about to read 3, iclass 33, count 0 2006.201.06:08:46.23#ibcon#read 3, iclass 33, count 0 2006.201.06:08:46.23#ibcon#about to read 4, iclass 33, count 0 2006.201.06:08:46.23#ibcon#read 4, iclass 33, count 0 2006.201.06:08:46.23#ibcon#about to read 5, iclass 33, count 0 2006.201.06:08:46.23#ibcon#read 5, iclass 33, count 0 2006.201.06:08:46.23#ibcon#about to read 6, iclass 33, count 0 2006.201.06:08:46.23#ibcon#read 6, iclass 33, count 0 2006.201.06:08:46.23#ibcon#end of sib2, iclass 33, count 0 2006.201.06:08:46.23#ibcon#*after write, iclass 33, count 0 2006.201.06:08:46.23#ibcon#*before return 0, iclass 33, count 0 2006.201.06:08:46.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:46.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:46.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.06:08:46.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.06:08:46.23$vck44/valo=8,884.99 2006.201.06:08:46.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.06:08:46.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.06:08:46.23#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:46.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:46.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:46.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:46.23#ibcon#enter wrdev, iclass 35, count 0 2006.201.06:08:46.23#ibcon#first serial, iclass 35, count 0 2006.201.06:08:46.23#ibcon#enter sib2, iclass 35, count 0 2006.201.06:08:46.23#ibcon#flushed, iclass 35, count 0 2006.201.06:08:46.23#ibcon#about to write, iclass 35, count 0 2006.201.06:08:46.23#ibcon#wrote, iclass 35, count 0 2006.201.06:08:46.23#ibcon#about to read 3, iclass 35, count 0 2006.201.06:08:46.25#ibcon#read 3, iclass 35, count 0 2006.201.06:08:46.25#ibcon#about to read 4, iclass 35, count 0 2006.201.06:08:46.25#ibcon#read 4, iclass 35, count 0 2006.201.06:08:46.25#ibcon#about to read 5, iclass 35, count 0 2006.201.06:08:46.25#ibcon#read 5, iclass 35, count 0 2006.201.06:08:46.25#ibcon#about to read 6, iclass 35, count 0 2006.201.06:08:46.25#ibcon#read 6, iclass 35, count 0 2006.201.06:08:46.25#ibcon#end of sib2, iclass 35, count 0 2006.201.06:08:46.25#ibcon#*mode == 0, iclass 35, count 0 2006.201.06:08:46.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.06:08:46.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.06:08:46.25#ibcon#*before write, iclass 35, count 0 2006.201.06:08:46.25#ibcon#enter sib2, iclass 35, count 0 2006.201.06:08:46.25#ibcon#flushed, iclass 35, count 0 2006.201.06:08:46.25#ibcon#about to write, iclass 35, count 0 2006.201.06:08:46.25#ibcon#wrote, iclass 35, count 0 2006.201.06:08:46.25#ibcon#about to read 3, iclass 35, count 0 2006.201.06:08:46.29#ibcon#read 3, iclass 35, count 0 2006.201.06:08:46.29#ibcon#about to read 4, iclass 35, count 0 2006.201.06:08:46.29#ibcon#read 4, iclass 35, count 0 2006.201.06:08:46.29#ibcon#about to read 5, iclass 35, count 0 2006.201.06:08:46.29#ibcon#read 5, iclass 35, count 0 2006.201.06:08:46.29#ibcon#about to read 6, iclass 35, count 0 2006.201.06:08:46.29#ibcon#read 6, iclass 35, count 0 2006.201.06:08:46.29#ibcon#end of sib2, iclass 35, count 0 2006.201.06:08:46.29#ibcon#*after write, iclass 35, count 0 2006.201.06:08:46.29#ibcon#*before return 0, iclass 35, count 0 2006.201.06:08:46.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:46.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:46.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.06:08:46.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.06:08:46.29$vck44/va=8,4 2006.201.06:08:46.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.06:08:46.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.06:08:46.29#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:46.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:08:46.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:08:46.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:08:46.35#ibcon#enter wrdev, iclass 37, count 2 2006.201.06:08:46.35#ibcon#first serial, iclass 37, count 2 2006.201.06:08:46.35#ibcon#enter sib2, iclass 37, count 2 2006.201.06:08:46.35#ibcon#flushed, iclass 37, count 2 2006.201.06:08:46.35#ibcon#about to write, iclass 37, count 2 2006.201.06:08:46.35#ibcon#wrote, iclass 37, count 2 2006.201.06:08:46.35#ibcon#about to read 3, iclass 37, count 2 2006.201.06:08:46.37#ibcon#read 3, iclass 37, count 2 2006.201.06:08:46.37#ibcon#about to read 4, iclass 37, count 2 2006.201.06:08:46.37#ibcon#read 4, iclass 37, count 2 2006.201.06:08:46.37#ibcon#about to read 5, iclass 37, count 2 2006.201.06:08:46.37#ibcon#read 5, iclass 37, count 2 2006.201.06:08:46.37#ibcon#about to read 6, iclass 37, count 2 2006.201.06:08:46.37#ibcon#read 6, iclass 37, count 2 2006.201.06:08:46.37#ibcon#end of sib2, iclass 37, count 2 2006.201.06:08:46.37#ibcon#*mode == 0, iclass 37, count 2 2006.201.06:08:46.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.06:08:46.37#ibcon#[25=AT08-04\r\n] 2006.201.06:08:46.37#ibcon#*before write, iclass 37, count 2 2006.201.06:08:46.37#ibcon#enter sib2, iclass 37, count 2 2006.201.06:08:46.37#ibcon#flushed, iclass 37, count 2 2006.201.06:08:46.37#ibcon#about to write, iclass 37, count 2 2006.201.06:08:46.37#ibcon#wrote, iclass 37, count 2 2006.201.06:08:46.37#ibcon#about to read 3, iclass 37, count 2 2006.201.06:08:46.41#ibcon#read 3, iclass 37, count 2 2006.201.06:08:46.41#ibcon#about to read 4, iclass 37, count 2 2006.201.06:08:46.41#ibcon#read 4, iclass 37, count 2 2006.201.06:08:46.41#ibcon#about to read 5, iclass 37, count 2 2006.201.06:08:46.41#ibcon#read 5, iclass 37, count 2 2006.201.06:08:46.41#ibcon#about to read 6, iclass 37, count 2 2006.201.06:08:46.41#ibcon#read 6, iclass 37, count 2 2006.201.06:08:46.41#ibcon#end of sib2, iclass 37, count 2 2006.201.06:08:46.41#ibcon#*after write, iclass 37, count 2 2006.201.06:08:46.41#ibcon#*before return 0, iclass 37, count 2 2006.201.06:08:46.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:08:46.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:08:46.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.06:08:46.41#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:46.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:08:46.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:08:46.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:08:46.53#ibcon#enter wrdev, iclass 37, count 0 2006.201.06:08:46.53#ibcon#first serial, iclass 37, count 0 2006.201.06:08:46.53#ibcon#enter sib2, iclass 37, count 0 2006.201.06:08:46.53#ibcon#flushed, iclass 37, count 0 2006.201.06:08:46.53#ibcon#about to write, iclass 37, count 0 2006.201.06:08:46.53#ibcon#wrote, iclass 37, count 0 2006.201.06:08:46.53#ibcon#about to read 3, iclass 37, count 0 2006.201.06:08:46.55#ibcon#read 3, iclass 37, count 0 2006.201.06:08:46.55#ibcon#about to read 4, iclass 37, count 0 2006.201.06:08:46.55#ibcon#read 4, iclass 37, count 0 2006.201.06:08:46.55#ibcon#about to read 5, iclass 37, count 0 2006.201.06:08:46.55#ibcon#read 5, iclass 37, count 0 2006.201.06:08:46.55#ibcon#about to read 6, iclass 37, count 0 2006.201.06:08:46.55#ibcon#read 6, iclass 37, count 0 2006.201.06:08:46.55#ibcon#end of sib2, iclass 37, count 0 2006.201.06:08:46.55#ibcon#*mode == 0, iclass 37, count 0 2006.201.06:08:46.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.06:08:46.55#ibcon#[25=USB\r\n] 2006.201.06:08:46.55#ibcon#*before write, iclass 37, count 0 2006.201.06:08:46.55#ibcon#enter sib2, iclass 37, count 0 2006.201.06:08:46.55#ibcon#flushed, iclass 37, count 0 2006.201.06:08:46.55#ibcon#about to write, iclass 37, count 0 2006.201.06:08:46.55#ibcon#wrote, iclass 37, count 0 2006.201.06:08:46.55#ibcon#about to read 3, iclass 37, count 0 2006.201.06:08:46.58#ibcon#read 3, iclass 37, count 0 2006.201.06:08:46.58#ibcon#about to read 4, iclass 37, count 0 2006.201.06:08:46.58#ibcon#read 4, iclass 37, count 0 2006.201.06:08:46.58#ibcon#about to read 5, iclass 37, count 0 2006.201.06:08:46.58#ibcon#read 5, iclass 37, count 0 2006.201.06:08:46.58#ibcon#about to read 6, iclass 37, count 0 2006.201.06:08:46.58#ibcon#read 6, iclass 37, count 0 2006.201.06:08:46.58#ibcon#end of sib2, iclass 37, count 0 2006.201.06:08:46.58#ibcon#*after write, iclass 37, count 0 2006.201.06:08:46.58#ibcon#*before return 0, iclass 37, count 0 2006.201.06:08:46.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:08:46.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:08:46.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.06:08:46.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.06:08:46.58$vck44/vblo=1,629.99 2006.201.06:08:46.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.06:08:46.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.06:08:46.58#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:46.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:08:46.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:08:46.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:08:46.58#ibcon#enter wrdev, iclass 39, count 0 2006.201.06:08:46.58#ibcon#first serial, iclass 39, count 0 2006.201.06:08:46.58#ibcon#enter sib2, iclass 39, count 0 2006.201.06:08:46.58#ibcon#flushed, iclass 39, count 0 2006.201.06:08:46.58#ibcon#about to write, iclass 39, count 0 2006.201.06:08:46.58#ibcon#wrote, iclass 39, count 0 2006.201.06:08:46.58#ibcon#about to read 3, iclass 39, count 0 2006.201.06:08:46.60#ibcon#read 3, iclass 39, count 0 2006.201.06:08:46.60#ibcon#about to read 4, iclass 39, count 0 2006.201.06:08:46.60#ibcon#read 4, iclass 39, count 0 2006.201.06:08:46.60#ibcon#about to read 5, iclass 39, count 0 2006.201.06:08:46.60#ibcon#read 5, iclass 39, count 0 2006.201.06:08:46.60#ibcon#about to read 6, iclass 39, count 0 2006.201.06:08:46.60#ibcon#read 6, iclass 39, count 0 2006.201.06:08:46.60#ibcon#end of sib2, iclass 39, count 0 2006.201.06:08:46.60#ibcon#*mode == 0, iclass 39, count 0 2006.201.06:08:46.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.06:08:46.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.06:08:46.60#ibcon#*before write, iclass 39, count 0 2006.201.06:08:46.60#ibcon#enter sib2, iclass 39, count 0 2006.201.06:08:46.60#ibcon#flushed, iclass 39, count 0 2006.201.06:08:46.60#ibcon#about to write, iclass 39, count 0 2006.201.06:08:46.60#ibcon#wrote, iclass 39, count 0 2006.201.06:08:46.60#ibcon#about to read 3, iclass 39, count 0 2006.201.06:08:46.65#ibcon#read 3, iclass 39, count 0 2006.201.06:08:46.65#ibcon#about to read 4, iclass 39, count 0 2006.201.06:08:46.65#ibcon#read 4, iclass 39, count 0 2006.201.06:08:46.65#ibcon#about to read 5, iclass 39, count 0 2006.201.06:08:46.65#ibcon#read 5, iclass 39, count 0 2006.201.06:08:46.65#ibcon#about to read 6, iclass 39, count 0 2006.201.06:08:46.65#ibcon#read 6, iclass 39, count 0 2006.201.06:08:46.65#ibcon#end of sib2, iclass 39, count 0 2006.201.06:08:46.65#ibcon#*after write, iclass 39, count 0 2006.201.06:08:46.65#ibcon#*before return 0, iclass 39, count 0 2006.201.06:08:46.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:08:46.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:08:46.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.06:08:46.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.06:08:46.65$vck44/vb=1,4 2006.201.06:08:46.65#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.06:08:46.65#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.06:08:46.65#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:46.65#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:08:46.65#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:08:46.65#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:08:46.65#ibcon#enter wrdev, iclass 2, count 2 2006.201.06:08:46.65#ibcon#first serial, iclass 2, count 2 2006.201.06:08:46.65#ibcon#enter sib2, iclass 2, count 2 2006.201.06:08:46.65#ibcon#flushed, iclass 2, count 2 2006.201.06:08:46.65#ibcon#about to write, iclass 2, count 2 2006.201.06:08:46.65#ibcon#wrote, iclass 2, count 2 2006.201.06:08:46.65#ibcon#about to read 3, iclass 2, count 2 2006.201.06:08:46.67#ibcon#read 3, iclass 2, count 2 2006.201.06:08:46.67#ibcon#about to read 4, iclass 2, count 2 2006.201.06:08:46.67#ibcon#read 4, iclass 2, count 2 2006.201.06:08:46.67#ibcon#about to read 5, iclass 2, count 2 2006.201.06:08:46.67#ibcon#read 5, iclass 2, count 2 2006.201.06:08:46.67#ibcon#about to read 6, iclass 2, count 2 2006.201.06:08:46.67#ibcon#read 6, iclass 2, count 2 2006.201.06:08:46.67#ibcon#end of sib2, iclass 2, count 2 2006.201.06:08:46.67#ibcon#*mode == 0, iclass 2, count 2 2006.201.06:08:46.67#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.06:08:46.67#ibcon#[27=AT01-04\r\n] 2006.201.06:08:46.67#ibcon#*before write, iclass 2, count 2 2006.201.06:08:46.67#ibcon#enter sib2, iclass 2, count 2 2006.201.06:08:46.67#ibcon#flushed, iclass 2, count 2 2006.201.06:08:46.67#ibcon#about to write, iclass 2, count 2 2006.201.06:08:46.67#ibcon#wrote, iclass 2, count 2 2006.201.06:08:46.67#ibcon#about to read 3, iclass 2, count 2 2006.201.06:08:46.70#ibcon#read 3, iclass 2, count 2 2006.201.06:08:46.70#ibcon#about to read 4, iclass 2, count 2 2006.201.06:08:46.70#ibcon#read 4, iclass 2, count 2 2006.201.06:08:46.70#ibcon#about to read 5, iclass 2, count 2 2006.201.06:08:46.70#ibcon#read 5, iclass 2, count 2 2006.201.06:08:46.70#ibcon#about to read 6, iclass 2, count 2 2006.201.06:08:46.70#ibcon#read 6, iclass 2, count 2 2006.201.06:08:46.70#ibcon#end of sib2, iclass 2, count 2 2006.201.06:08:46.70#ibcon#*after write, iclass 2, count 2 2006.201.06:08:46.70#ibcon#*before return 0, iclass 2, count 2 2006.201.06:08:46.70#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:08:46.70#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:08:46.70#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.06:08:46.70#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:46.70#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:08:46.82#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:08:46.82#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:08:46.82#ibcon#enter wrdev, iclass 2, count 0 2006.201.06:08:46.82#ibcon#first serial, iclass 2, count 0 2006.201.06:08:46.82#ibcon#enter sib2, iclass 2, count 0 2006.201.06:08:46.82#ibcon#flushed, iclass 2, count 0 2006.201.06:08:46.82#ibcon#about to write, iclass 2, count 0 2006.201.06:08:46.82#ibcon#wrote, iclass 2, count 0 2006.201.06:08:46.82#ibcon#about to read 3, iclass 2, count 0 2006.201.06:08:46.84#ibcon#read 3, iclass 2, count 0 2006.201.06:08:46.84#ibcon#about to read 4, iclass 2, count 0 2006.201.06:08:46.84#ibcon#read 4, iclass 2, count 0 2006.201.06:08:46.84#ibcon#about to read 5, iclass 2, count 0 2006.201.06:08:46.84#ibcon#read 5, iclass 2, count 0 2006.201.06:08:46.84#ibcon#about to read 6, iclass 2, count 0 2006.201.06:08:46.84#ibcon#read 6, iclass 2, count 0 2006.201.06:08:46.84#ibcon#end of sib2, iclass 2, count 0 2006.201.06:08:46.84#ibcon#*mode == 0, iclass 2, count 0 2006.201.06:08:46.84#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.06:08:46.84#ibcon#[27=USB\r\n] 2006.201.06:08:46.84#ibcon#*before write, iclass 2, count 0 2006.201.06:08:46.84#ibcon#enter sib2, iclass 2, count 0 2006.201.06:08:46.84#ibcon#flushed, iclass 2, count 0 2006.201.06:08:46.84#ibcon#about to write, iclass 2, count 0 2006.201.06:08:46.84#ibcon#wrote, iclass 2, count 0 2006.201.06:08:46.84#ibcon#about to read 3, iclass 2, count 0 2006.201.06:08:46.87#ibcon#read 3, iclass 2, count 0 2006.201.06:08:46.87#ibcon#about to read 4, iclass 2, count 0 2006.201.06:08:46.87#ibcon#read 4, iclass 2, count 0 2006.201.06:08:46.87#ibcon#about to read 5, iclass 2, count 0 2006.201.06:08:46.87#ibcon#read 5, iclass 2, count 0 2006.201.06:08:46.87#ibcon#about to read 6, iclass 2, count 0 2006.201.06:08:46.87#ibcon#read 6, iclass 2, count 0 2006.201.06:08:46.87#ibcon#end of sib2, iclass 2, count 0 2006.201.06:08:46.87#ibcon#*after write, iclass 2, count 0 2006.201.06:08:46.87#ibcon#*before return 0, iclass 2, count 0 2006.201.06:08:46.87#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:08:46.87#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:08:46.87#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.06:08:46.87#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.06:08:46.87$vck44/vblo=2,634.99 2006.201.06:08:46.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.06:08:46.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.06:08:46.87#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:46.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:46.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:46.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:46.87#ibcon#enter wrdev, iclass 5, count 0 2006.201.06:08:46.87#ibcon#first serial, iclass 5, count 0 2006.201.06:08:46.87#ibcon#enter sib2, iclass 5, count 0 2006.201.06:08:46.87#ibcon#flushed, iclass 5, count 0 2006.201.06:08:46.87#ibcon#about to write, iclass 5, count 0 2006.201.06:08:46.87#ibcon#wrote, iclass 5, count 0 2006.201.06:08:46.87#ibcon#about to read 3, iclass 5, count 0 2006.201.06:08:46.89#ibcon#read 3, iclass 5, count 0 2006.201.06:08:46.89#ibcon#about to read 4, iclass 5, count 0 2006.201.06:08:46.89#ibcon#read 4, iclass 5, count 0 2006.201.06:08:46.89#ibcon#about to read 5, iclass 5, count 0 2006.201.06:08:46.89#ibcon#read 5, iclass 5, count 0 2006.201.06:08:46.89#ibcon#about to read 6, iclass 5, count 0 2006.201.06:08:46.89#ibcon#read 6, iclass 5, count 0 2006.201.06:08:46.89#ibcon#end of sib2, iclass 5, count 0 2006.201.06:08:46.89#ibcon#*mode == 0, iclass 5, count 0 2006.201.06:08:46.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.06:08:46.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.06:08:46.89#ibcon#*before write, iclass 5, count 0 2006.201.06:08:46.89#ibcon#enter sib2, iclass 5, count 0 2006.201.06:08:46.89#ibcon#flushed, iclass 5, count 0 2006.201.06:08:46.89#ibcon#about to write, iclass 5, count 0 2006.201.06:08:46.89#ibcon#wrote, iclass 5, count 0 2006.201.06:08:46.89#ibcon#about to read 3, iclass 5, count 0 2006.201.06:08:46.93#ibcon#read 3, iclass 5, count 0 2006.201.06:08:46.93#ibcon#about to read 4, iclass 5, count 0 2006.201.06:08:46.93#ibcon#read 4, iclass 5, count 0 2006.201.06:08:46.93#ibcon#about to read 5, iclass 5, count 0 2006.201.06:08:46.93#ibcon#read 5, iclass 5, count 0 2006.201.06:08:46.93#ibcon#about to read 6, iclass 5, count 0 2006.201.06:08:46.93#ibcon#read 6, iclass 5, count 0 2006.201.06:08:46.93#ibcon#end of sib2, iclass 5, count 0 2006.201.06:08:46.93#ibcon#*after write, iclass 5, count 0 2006.201.06:08:46.93#ibcon#*before return 0, iclass 5, count 0 2006.201.06:08:46.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:46.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:08:46.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.06:08:46.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.06:08:46.93$vck44/vb=2,5 2006.201.06:08:46.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.06:08:46.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.06:08:46.93#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:46.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:46.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:46.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:46.99#ibcon#enter wrdev, iclass 7, count 2 2006.201.06:08:46.99#ibcon#first serial, iclass 7, count 2 2006.201.06:08:46.99#ibcon#enter sib2, iclass 7, count 2 2006.201.06:08:46.99#ibcon#flushed, iclass 7, count 2 2006.201.06:08:46.99#ibcon#about to write, iclass 7, count 2 2006.201.06:08:46.99#ibcon#wrote, iclass 7, count 2 2006.201.06:08:46.99#ibcon#about to read 3, iclass 7, count 2 2006.201.06:08:47.01#ibcon#read 3, iclass 7, count 2 2006.201.06:08:47.01#ibcon#about to read 4, iclass 7, count 2 2006.201.06:08:47.01#ibcon#read 4, iclass 7, count 2 2006.201.06:08:47.01#ibcon#about to read 5, iclass 7, count 2 2006.201.06:08:47.01#ibcon#read 5, iclass 7, count 2 2006.201.06:08:47.01#ibcon#about to read 6, iclass 7, count 2 2006.201.06:08:47.01#ibcon#read 6, iclass 7, count 2 2006.201.06:08:47.01#ibcon#end of sib2, iclass 7, count 2 2006.201.06:08:47.01#ibcon#*mode == 0, iclass 7, count 2 2006.201.06:08:47.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.06:08:47.01#ibcon#[27=AT02-05\r\n] 2006.201.06:08:47.01#ibcon#*before write, iclass 7, count 2 2006.201.06:08:47.01#ibcon#enter sib2, iclass 7, count 2 2006.201.06:08:47.01#ibcon#flushed, iclass 7, count 2 2006.201.06:08:47.01#ibcon#about to write, iclass 7, count 2 2006.201.06:08:47.01#ibcon#wrote, iclass 7, count 2 2006.201.06:08:47.01#ibcon#about to read 3, iclass 7, count 2 2006.201.06:08:47.04#ibcon#read 3, iclass 7, count 2 2006.201.06:08:47.04#ibcon#about to read 4, iclass 7, count 2 2006.201.06:08:47.04#ibcon#read 4, iclass 7, count 2 2006.201.06:08:47.04#ibcon#about to read 5, iclass 7, count 2 2006.201.06:08:47.04#ibcon#read 5, iclass 7, count 2 2006.201.06:08:47.04#ibcon#about to read 6, iclass 7, count 2 2006.201.06:08:47.04#ibcon#read 6, iclass 7, count 2 2006.201.06:08:47.04#ibcon#end of sib2, iclass 7, count 2 2006.201.06:08:47.04#ibcon#*after write, iclass 7, count 2 2006.201.06:08:47.04#ibcon#*before return 0, iclass 7, count 2 2006.201.06:08:47.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:47.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:08:47.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.06:08:47.04#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:47.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:47.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:47.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:47.16#ibcon#enter wrdev, iclass 7, count 0 2006.201.06:08:47.16#ibcon#first serial, iclass 7, count 0 2006.201.06:08:47.16#ibcon#enter sib2, iclass 7, count 0 2006.201.06:08:47.16#ibcon#flushed, iclass 7, count 0 2006.201.06:08:47.16#ibcon#about to write, iclass 7, count 0 2006.201.06:08:47.16#ibcon#wrote, iclass 7, count 0 2006.201.06:08:47.16#ibcon#about to read 3, iclass 7, count 0 2006.201.06:08:47.18#ibcon#read 3, iclass 7, count 0 2006.201.06:08:47.18#ibcon#about to read 4, iclass 7, count 0 2006.201.06:08:47.18#ibcon#read 4, iclass 7, count 0 2006.201.06:08:47.18#ibcon#about to read 5, iclass 7, count 0 2006.201.06:08:47.18#ibcon#read 5, iclass 7, count 0 2006.201.06:08:47.18#ibcon#about to read 6, iclass 7, count 0 2006.201.06:08:47.18#ibcon#read 6, iclass 7, count 0 2006.201.06:08:47.18#ibcon#end of sib2, iclass 7, count 0 2006.201.06:08:47.18#ibcon#*mode == 0, iclass 7, count 0 2006.201.06:08:47.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.06:08:47.18#ibcon#[27=USB\r\n] 2006.201.06:08:47.18#ibcon#*before write, iclass 7, count 0 2006.201.06:08:47.18#ibcon#enter sib2, iclass 7, count 0 2006.201.06:08:47.18#ibcon#flushed, iclass 7, count 0 2006.201.06:08:47.18#ibcon#about to write, iclass 7, count 0 2006.201.06:08:47.18#ibcon#wrote, iclass 7, count 0 2006.201.06:08:47.18#ibcon#about to read 3, iclass 7, count 0 2006.201.06:08:47.21#ibcon#read 3, iclass 7, count 0 2006.201.06:08:47.21#ibcon#about to read 4, iclass 7, count 0 2006.201.06:08:47.21#ibcon#read 4, iclass 7, count 0 2006.201.06:08:47.21#ibcon#about to read 5, iclass 7, count 0 2006.201.06:08:47.21#ibcon#read 5, iclass 7, count 0 2006.201.06:08:47.21#ibcon#about to read 6, iclass 7, count 0 2006.201.06:08:47.21#ibcon#read 6, iclass 7, count 0 2006.201.06:08:47.21#ibcon#end of sib2, iclass 7, count 0 2006.201.06:08:47.21#ibcon#*after write, iclass 7, count 0 2006.201.06:08:47.21#ibcon#*before return 0, iclass 7, count 0 2006.201.06:08:47.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:47.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:08:47.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.06:08:47.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.06:08:47.21$vck44/vblo=3,649.99 2006.201.06:08:47.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.06:08:47.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.06:08:47.21#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:47.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:47.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:47.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:47.21#ibcon#enter wrdev, iclass 11, count 0 2006.201.06:08:47.21#ibcon#first serial, iclass 11, count 0 2006.201.06:08:47.21#ibcon#enter sib2, iclass 11, count 0 2006.201.06:08:47.21#ibcon#flushed, iclass 11, count 0 2006.201.06:08:47.21#ibcon#about to write, iclass 11, count 0 2006.201.06:08:47.21#ibcon#wrote, iclass 11, count 0 2006.201.06:08:47.21#ibcon#about to read 3, iclass 11, count 0 2006.201.06:08:47.23#ibcon#read 3, iclass 11, count 0 2006.201.06:08:47.23#ibcon#about to read 4, iclass 11, count 0 2006.201.06:08:47.23#ibcon#read 4, iclass 11, count 0 2006.201.06:08:47.23#ibcon#about to read 5, iclass 11, count 0 2006.201.06:08:47.23#ibcon#read 5, iclass 11, count 0 2006.201.06:08:47.23#ibcon#about to read 6, iclass 11, count 0 2006.201.06:08:47.23#ibcon#read 6, iclass 11, count 0 2006.201.06:08:47.23#ibcon#end of sib2, iclass 11, count 0 2006.201.06:08:47.23#ibcon#*mode == 0, iclass 11, count 0 2006.201.06:08:47.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.06:08:47.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.06:08:47.23#ibcon#*before write, iclass 11, count 0 2006.201.06:08:47.23#ibcon#enter sib2, iclass 11, count 0 2006.201.06:08:47.23#ibcon#flushed, iclass 11, count 0 2006.201.06:08:47.23#ibcon#about to write, iclass 11, count 0 2006.201.06:08:47.23#ibcon#wrote, iclass 11, count 0 2006.201.06:08:47.23#ibcon#about to read 3, iclass 11, count 0 2006.201.06:08:47.27#ibcon#read 3, iclass 11, count 0 2006.201.06:08:47.27#ibcon#about to read 4, iclass 11, count 0 2006.201.06:08:47.27#ibcon#read 4, iclass 11, count 0 2006.201.06:08:47.27#ibcon#about to read 5, iclass 11, count 0 2006.201.06:08:47.27#ibcon#read 5, iclass 11, count 0 2006.201.06:08:47.27#ibcon#about to read 6, iclass 11, count 0 2006.201.06:08:47.27#ibcon#read 6, iclass 11, count 0 2006.201.06:08:47.27#ibcon#end of sib2, iclass 11, count 0 2006.201.06:08:47.27#ibcon#*after write, iclass 11, count 0 2006.201.06:08:47.27#ibcon#*before return 0, iclass 11, count 0 2006.201.06:08:47.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:47.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:08:47.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.06:08:47.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.06:08:47.27$vck44/vb=3,4 2006.201.06:08:47.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.06:08:47.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.06:08:47.27#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:47.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:47.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:47.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:47.33#ibcon#enter wrdev, iclass 13, count 2 2006.201.06:08:47.33#ibcon#first serial, iclass 13, count 2 2006.201.06:08:47.33#ibcon#enter sib2, iclass 13, count 2 2006.201.06:08:47.33#ibcon#flushed, iclass 13, count 2 2006.201.06:08:47.33#ibcon#about to write, iclass 13, count 2 2006.201.06:08:47.33#ibcon#wrote, iclass 13, count 2 2006.201.06:08:47.33#ibcon#about to read 3, iclass 13, count 2 2006.201.06:08:47.35#ibcon#read 3, iclass 13, count 2 2006.201.06:08:47.35#ibcon#about to read 4, iclass 13, count 2 2006.201.06:08:47.35#ibcon#read 4, iclass 13, count 2 2006.201.06:08:47.35#ibcon#about to read 5, iclass 13, count 2 2006.201.06:08:47.35#ibcon#read 5, iclass 13, count 2 2006.201.06:08:47.35#ibcon#about to read 6, iclass 13, count 2 2006.201.06:08:47.35#ibcon#read 6, iclass 13, count 2 2006.201.06:08:47.35#ibcon#end of sib2, iclass 13, count 2 2006.201.06:08:47.35#ibcon#*mode == 0, iclass 13, count 2 2006.201.06:08:47.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.06:08:47.35#ibcon#[27=AT03-04\r\n] 2006.201.06:08:47.35#ibcon#*before write, iclass 13, count 2 2006.201.06:08:47.35#ibcon#enter sib2, iclass 13, count 2 2006.201.06:08:47.35#ibcon#flushed, iclass 13, count 2 2006.201.06:08:47.35#ibcon#about to write, iclass 13, count 2 2006.201.06:08:47.35#ibcon#wrote, iclass 13, count 2 2006.201.06:08:47.35#ibcon#about to read 3, iclass 13, count 2 2006.201.06:08:47.38#ibcon#read 3, iclass 13, count 2 2006.201.06:08:47.38#ibcon#about to read 4, iclass 13, count 2 2006.201.06:08:47.38#ibcon#read 4, iclass 13, count 2 2006.201.06:08:47.38#ibcon#about to read 5, iclass 13, count 2 2006.201.06:08:47.38#ibcon#read 5, iclass 13, count 2 2006.201.06:08:47.38#ibcon#about to read 6, iclass 13, count 2 2006.201.06:08:47.38#ibcon#read 6, iclass 13, count 2 2006.201.06:08:47.38#ibcon#end of sib2, iclass 13, count 2 2006.201.06:08:47.38#ibcon#*after write, iclass 13, count 2 2006.201.06:08:47.38#ibcon#*before return 0, iclass 13, count 2 2006.201.06:08:47.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:47.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:08:47.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.06:08:47.38#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:47.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:47.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:47.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:47.50#ibcon#enter wrdev, iclass 13, count 0 2006.201.06:08:47.50#ibcon#first serial, iclass 13, count 0 2006.201.06:08:47.50#ibcon#enter sib2, iclass 13, count 0 2006.201.06:08:47.50#ibcon#flushed, iclass 13, count 0 2006.201.06:08:47.50#ibcon#about to write, iclass 13, count 0 2006.201.06:08:47.50#ibcon#wrote, iclass 13, count 0 2006.201.06:08:47.50#ibcon#about to read 3, iclass 13, count 0 2006.201.06:08:47.52#ibcon#read 3, iclass 13, count 0 2006.201.06:08:47.52#ibcon#about to read 4, iclass 13, count 0 2006.201.06:08:47.52#ibcon#read 4, iclass 13, count 0 2006.201.06:08:47.52#ibcon#about to read 5, iclass 13, count 0 2006.201.06:08:47.52#ibcon#read 5, iclass 13, count 0 2006.201.06:08:47.52#ibcon#about to read 6, iclass 13, count 0 2006.201.06:08:47.52#ibcon#read 6, iclass 13, count 0 2006.201.06:08:47.52#ibcon#end of sib2, iclass 13, count 0 2006.201.06:08:47.52#ibcon#*mode == 0, iclass 13, count 0 2006.201.06:08:47.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.06:08:47.52#ibcon#[27=USB\r\n] 2006.201.06:08:47.52#ibcon#*before write, iclass 13, count 0 2006.201.06:08:47.52#ibcon#enter sib2, iclass 13, count 0 2006.201.06:08:47.52#ibcon#flushed, iclass 13, count 0 2006.201.06:08:47.52#ibcon#about to write, iclass 13, count 0 2006.201.06:08:47.52#ibcon#wrote, iclass 13, count 0 2006.201.06:08:47.52#ibcon#about to read 3, iclass 13, count 0 2006.201.06:08:47.55#ibcon#read 3, iclass 13, count 0 2006.201.06:08:47.55#ibcon#about to read 4, iclass 13, count 0 2006.201.06:08:47.55#ibcon#read 4, iclass 13, count 0 2006.201.06:08:47.55#ibcon#about to read 5, iclass 13, count 0 2006.201.06:08:47.55#ibcon#read 5, iclass 13, count 0 2006.201.06:08:47.55#ibcon#about to read 6, iclass 13, count 0 2006.201.06:08:47.55#ibcon#read 6, iclass 13, count 0 2006.201.06:08:47.55#ibcon#end of sib2, iclass 13, count 0 2006.201.06:08:47.55#ibcon#*after write, iclass 13, count 0 2006.201.06:08:47.55#ibcon#*before return 0, iclass 13, count 0 2006.201.06:08:47.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:47.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:08:47.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.06:08:47.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.06:08:47.55$vck44/vblo=4,679.99 2006.201.06:08:47.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.06:08:47.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.06:08:47.55#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:47.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:47.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:47.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:47.55#ibcon#enter wrdev, iclass 15, count 0 2006.201.06:08:47.55#ibcon#first serial, iclass 15, count 0 2006.201.06:08:47.55#ibcon#enter sib2, iclass 15, count 0 2006.201.06:08:47.55#ibcon#flushed, iclass 15, count 0 2006.201.06:08:47.55#ibcon#about to write, iclass 15, count 0 2006.201.06:08:47.55#ibcon#wrote, iclass 15, count 0 2006.201.06:08:47.55#ibcon#about to read 3, iclass 15, count 0 2006.201.06:08:47.57#ibcon#read 3, iclass 15, count 0 2006.201.06:08:47.57#ibcon#about to read 4, iclass 15, count 0 2006.201.06:08:47.57#ibcon#read 4, iclass 15, count 0 2006.201.06:08:47.57#ibcon#about to read 5, iclass 15, count 0 2006.201.06:08:47.57#ibcon#read 5, iclass 15, count 0 2006.201.06:08:47.57#ibcon#about to read 6, iclass 15, count 0 2006.201.06:08:47.57#ibcon#read 6, iclass 15, count 0 2006.201.06:08:47.57#ibcon#end of sib2, iclass 15, count 0 2006.201.06:08:47.57#ibcon#*mode == 0, iclass 15, count 0 2006.201.06:08:47.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.06:08:47.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.06:08:47.57#ibcon#*before write, iclass 15, count 0 2006.201.06:08:47.57#ibcon#enter sib2, iclass 15, count 0 2006.201.06:08:47.57#ibcon#flushed, iclass 15, count 0 2006.201.06:08:47.57#ibcon#about to write, iclass 15, count 0 2006.201.06:08:47.57#ibcon#wrote, iclass 15, count 0 2006.201.06:08:47.57#ibcon#about to read 3, iclass 15, count 0 2006.201.06:08:47.61#ibcon#read 3, iclass 15, count 0 2006.201.06:08:47.61#ibcon#about to read 4, iclass 15, count 0 2006.201.06:08:47.61#ibcon#read 4, iclass 15, count 0 2006.201.06:08:47.61#ibcon#about to read 5, iclass 15, count 0 2006.201.06:08:47.61#ibcon#read 5, iclass 15, count 0 2006.201.06:08:47.61#ibcon#about to read 6, iclass 15, count 0 2006.201.06:08:47.61#ibcon#read 6, iclass 15, count 0 2006.201.06:08:47.61#ibcon#end of sib2, iclass 15, count 0 2006.201.06:08:47.61#ibcon#*after write, iclass 15, count 0 2006.201.06:08:47.61#ibcon#*before return 0, iclass 15, count 0 2006.201.06:08:47.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:47.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:08:47.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.06:08:47.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.06:08:47.61$vck44/vb=4,5 2006.201.06:08:47.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.06:08:47.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.06:08:47.61#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:47.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:47.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:47.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:47.67#ibcon#enter wrdev, iclass 17, count 2 2006.201.06:08:47.67#ibcon#first serial, iclass 17, count 2 2006.201.06:08:47.67#ibcon#enter sib2, iclass 17, count 2 2006.201.06:08:47.67#ibcon#flushed, iclass 17, count 2 2006.201.06:08:47.67#ibcon#about to write, iclass 17, count 2 2006.201.06:08:47.67#ibcon#wrote, iclass 17, count 2 2006.201.06:08:47.67#ibcon#about to read 3, iclass 17, count 2 2006.201.06:08:47.69#ibcon#read 3, iclass 17, count 2 2006.201.06:08:47.69#ibcon#about to read 4, iclass 17, count 2 2006.201.06:08:47.69#ibcon#read 4, iclass 17, count 2 2006.201.06:08:47.69#ibcon#about to read 5, iclass 17, count 2 2006.201.06:08:47.69#ibcon#read 5, iclass 17, count 2 2006.201.06:08:47.69#ibcon#about to read 6, iclass 17, count 2 2006.201.06:08:47.69#ibcon#read 6, iclass 17, count 2 2006.201.06:08:47.69#ibcon#end of sib2, iclass 17, count 2 2006.201.06:08:47.69#ibcon#*mode == 0, iclass 17, count 2 2006.201.06:08:47.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.06:08:47.69#ibcon#[27=AT04-05\r\n] 2006.201.06:08:47.69#ibcon#*before write, iclass 17, count 2 2006.201.06:08:47.69#ibcon#enter sib2, iclass 17, count 2 2006.201.06:08:47.69#ibcon#flushed, iclass 17, count 2 2006.201.06:08:47.69#ibcon#about to write, iclass 17, count 2 2006.201.06:08:47.69#ibcon#wrote, iclass 17, count 2 2006.201.06:08:47.69#ibcon#about to read 3, iclass 17, count 2 2006.201.06:08:47.72#ibcon#read 3, iclass 17, count 2 2006.201.06:08:47.72#ibcon#about to read 4, iclass 17, count 2 2006.201.06:08:47.72#ibcon#read 4, iclass 17, count 2 2006.201.06:08:47.72#ibcon#about to read 5, iclass 17, count 2 2006.201.06:08:47.72#ibcon#read 5, iclass 17, count 2 2006.201.06:08:47.72#ibcon#about to read 6, iclass 17, count 2 2006.201.06:08:47.72#ibcon#read 6, iclass 17, count 2 2006.201.06:08:47.72#ibcon#end of sib2, iclass 17, count 2 2006.201.06:08:47.72#ibcon#*after write, iclass 17, count 2 2006.201.06:08:47.72#ibcon#*before return 0, iclass 17, count 2 2006.201.06:08:47.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:47.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:08:47.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.06:08:47.72#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:47.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:47.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:47.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:47.84#ibcon#enter wrdev, iclass 17, count 0 2006.201.06:08:47.84#ibcon#first serial, iclass 17, count 0 2006.201.06:08:47.84#ibcon#enter sib2, iclass 17, count 0 2006.201.06:08:47.84#ibcon#flushed, iclass 17, count 0 2006.201.06:08:47.84#ibcon#about to write, iclass 17, count 0 2006.201.06:08:47.84#ibcon#wrote, iclass 17, count 0 2006.201.06:08:47.84#ibcon#about to read 3, iclass 17, count 0 2006.201.06:08:47.86#ibcon#read 3, iclass 17, count 0 2006.201.06:08:47.86#ibcon#about to read 4, iclass 17, count 0 2006.201.06:08:47.86#ibcon#read 4, iclass 17, count 0 2006.201.06:08:47.86#ibcon#about to read 5, iclass 17, count 0 2006.201.06:08:47.86#ibcon#read 5, iclass 17, count 0 2006.201.06:08:47.86#ibcon#about to read 6, iclass 17, count 0 2006.201.06:08:47.86#ibcon#read 6, iclass 17, count 0 2006.201.06:08:47.86#ibcon#end of sib2, iclass 17, count 0 2006.201.06:08:47.86#ibcon#*mode == 0, iclass 17, count 0 2006.201.06:08:47.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.06:08:47.86#ibcon#[27=USB\r\n] 2006.201.06:08:47.86#ibcon#*before write, iclass 17, count 0 2006.201.06:08:47.86#ibcon#enter sib2, iclass 17, count 0 2006.201.06:08:47.86#ibcon#flushed, iclass 17, count 0 2006.201.06:08:47.86#ibcon#about to write, iclass 17, count 0 2006.201.06:08:47.86#ibcon#wrote, iclass 17, count 0 2006.201.06:08:47.86#ibcon#about to read 3, iclass 17, count 0 2006.201.06:08:47.89#ibcon#read 3, iclass 17, count 0 2006.201.06:08:47.89#ibcon#about to read 4, iclass 17, count 0 2006.201.06:08:47.89#ibcon#read 4, iclass 17, count 0 2006.201.06:08:47.89#ibcon#about to read 5, iclass 17, count 0 2006.201.06:08:47.89#ibcon#read 5, iclass 17, count 0 2006.201.06:08:47.89#ibcon#about to read 6, iclass 17, count 0 2006.201.06:08:47.89#ibcon#read 6, iclass 17, count 0 2006.201.06:08:47.89#ibcon#end of sib2, iclass 17, count 0 2006.201.06:08:47.89#ibcon#*after write, iclass 17, count 0 2006.201.06:08:47.89#ibcon#*before return 0, iclass 17, count 0 2006.201.06:08:47.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:47.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:08:47.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.06:08:47.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.06:08:47.89$vck44/vblo=5,709.99 2006.201.06:08:47.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.06:08:47.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.06:08:47.89#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:47.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:47.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:47.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:47.89#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:08:47.89#ibcon#first serial, iclass 19, count 0 2006.201.06:08:47.89#ibcon#enter sib2, iclass 19, count 0 2006.201.06:08:47.89#ibcon#flushed, iclass 19, count 0 2006.201.06:08:47.89#ibcon#about to write, iclass 19, count 0 2006.201.06:08:47.89#ibcon#wrote, iclass 19, count 0 2006.201.06:08:47.89#ibcon#about to read 3, iclass 19, count 0 2006.201.06:08:47.91#ibcon#read 3, iclass 19, count 0 2006.201.06:08:47.91#ibcon#about to read 4, iclass 19, count 0 2006.201.06:08:47.91#ibcon#read 4, iclass 19, count 0 2006.201.06:08:47.91#ibcon#about to read 5, iclass 19, count 0 2006.201.06:08:47.91#ibcon#read 5, iclass 19, count 0 2006.201.06:08:47.91#ibcon#about to read 6, iclass 19, count 0 2006.201.06:08:47.91#ibcon#read 6, iclass 19, count 0 2006.201.06:08:47.91#ibcon#end of sib2, iclass 19, count 0 2006.201.06:08:47.91#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:08:47.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:08:47.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.06:08:47.91#ibcon#*before write, iclass 19, count 0 2006.201.06:08:47.91#ibcon#enter sib2, iclass 19, count 0 2006.201.06:08:47.91#ibcon#flushed, iclass 19, count 0 2006.201.06:08:47.91#ibcon#about to write, iclass 19, count 0 2006.201.06:08:47.91#ibcon#wrote, iclass 19, count 0 2006.201.06:08:47.91#ibcon#about to read 3, iclass 19, count 0 2006.201.06:08:47.96#ibcon#read 3, iclass 19, count 0 2006.201.06:08:47.96#ibcon#about to read 4, iclass 19, count 0 2006.201.06:08:47.96#ibcon#read 4, iclass 19, count 0 2006.201.06:08:47.96#ibcon#about to read 5, iclass 19, count 0 2006.201.06:08:47.96#ibcon#read 5, iclass 19, count 0 2006.201.06:08:47.96#ibcon#about to read 6, iclass 19, count 0 2006.201.06:08:47.96#ibcon#read 6, iclass 19, count 0 2006.201.06:08:47.96#ibcon#end of sib2, iclass 19, count 0 2006.201.06:08:47.96#ibcon#*after write, iclass 19, count 0 2006.201.06:08:47.96#ibcon#*before return 0, iclass 19, count 0 2006.201.06:08:47.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:47.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:08:47.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:08:47.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:08:47.96$vck44/vb=5,4 2006.201.06:08:47.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.06:08:47.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.06:08:47.96#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:47.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:48.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:48.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:48.01#ibcon#enter wrdev, iclass 21, count 2 2006.201.06:08:48.01#ibcon#first serial, iclass 21, count 2 2006.201.06:08:48.01#ibcon#enter sib2, iclass 21, count 2 2006.201.06:08:48.01#ibcon#flushed, iclass 21, count 2 2006.201.06:08:48.01#ibcon#about to write, iclass 21, count 2 2006.201.06:08:48.01#ibcon#wrote, iclass 21, count 2 2006.201.06:08:48.01#ibcon#about to read 3, iclass 21, count 2 2006.201.06:08:48.03#ibcon#read 3, iclass 21, count 2 2006.201.06:08:48.03#ibcon#about to read 4, iclass 21, count 2 2006.201.06:08:48.03#ibcon#read 4, iclass 21, count 2 2006.201.06:08:48.03#ibcon#about to read 5, iclass 21, count 2 2006.201.06:08:48.03#ibcon#read 5, iclass 21, count 2 2006.201.06:08:48.03#ibcon#about to read 6, iclass 21, count 2 2006.201.06:08:48.03#ibcon#read 6, iclass 21, count 2 2006.201.06:08:48.03#ibcon#end of sib2, iclass 21, count 2 2006.201.06:08:48.03#ibcon#*mode == 0, iclass 21, count 2 2006.201.06:08:48.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.06:08:48.03#ibcon#[27=AT05-04\r\n] 2006.201.06:08:48.03#ibcon#*before write, iclass 21, count 2 2006.201.06:08:48.03#ibcon#enter sib2, iclass 21, count 2 2006.201.06:08:48.03#ibcon#flushed, iclass 21, count 2 2006.201.06:08:48.03#ibcon#about to write, iclass 21, count 2 2006.201.06:08:48.03#ibcon#wrote, iclass 21, count 2 2006.201.06:08:48.03#ibcon#about to read 3, iclass 21, count 2 2006.201.06:08:48.06#ibcon#read 3, iclass 21, count 2 2006.201.06:08:48.06#ibcon#about to read 4, iclass 21, count 2 2006.201.06:08:48.06#ibcon#read 4, iclass 21, count 2 2006.201.06:08:48.06#ibcon#about to read 5, iclass 21, count 2 2006.201.06:08:48.06#ibcon#read 5, iclass 21, count 2 2006.201.06:08:48.06#ibcon#about to read 6, iclass 21, count 2 2006.201.06:08:48.06#ibcon#read 6, iclass 21, count 2 2006.201.06:08:48.06#ibcon#end of sib2, iclass 21, count 2 2006.201.06:08:48.06#ibcon#*after write, iclass 21, count 2 2006.201.06:08:48.06#ibcon#*before return 0, iclass 21, count 2 2006.201.06:08:48.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:48.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:08:48.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.06:08:48.06#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:48.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:48.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:48.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:48.18#ibcon#enter wrdev, iclass 21, count 0 2006.201.06:08:48.18#ibcon#first serial, iclass 21, count 0 2006.201.06:08:48.18#ibcon#enter sib2, iclass 21, count 0 2006.201.06:08:48.18#ibcon#flushed, iclass 21, count 0 2006.201.06:08:48.18#ibcon#about to write, iclass 21, count 0 2006.201.06:08:48.18#ibcon#wrote, iclass 21, count 0 2006.201.06:08:48.18#ibcon#about to read 3, iclass 21, count 0 2006.201.06:08:48.21#ibcon#read 3, iclass 21, count 0 2006.201.06:08:48.21#ibcon#about to read 4, iclass 21, count 0 2006.201.06:08:48.21#ibcon#read 4, iclass 21, count 0 2006.201.06:08:48.21#ibcon#about to read 5, iclass 21, count 0 2006.201.06:08:48.21#ibcon#read 5, iclass 21, count 0 2006.201.06:08:48.21#ibcon#about to read 6, iclass 21, count 0 2006.201.06:08:48.21#ibcon#read 6, iclass 21, count 0 2006.201.06:08:48.21#ibcon#end of sib2, iclass 21, count 0 2006.201.06:08:48.21#ibcon#*mode == 0, iclass 21, count 0 2006.201.06:08:48.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.06:08:48.21#ibcon#[27=USB\r\n] 2006.201.06:08:48.21#ibcon#*before write, iclass 21, count 0 2006.201.06:08:48.21#ibcon#enter sib2, iclass 21, count 0 2006.201.06:08:48.21#ibcon#flushed, iclass 21, count 0 2006.201.06:08:48.21#ibcon#about to write, iclass 21, count 0 2006.201.06:08:48.21#ibcon#wrote, iclass 21, count 0 2006.201.06:08:48.21#ibcon#about to read 3, iclass 21, count 0 2006.201.06:08:48.24#ibcon#read 3, iclass 21, count 0 2006.201.06:08:48.24#ibcon#about to read 4, iclass 21, count 0 2006.201.06:08:48.24#ibcon#read 4, iclass 21, count 0 2006.201.06:08:48.24#ibcon#about to read 5, iclass 21, count 0 2006.201.06:08:48.24#ibcon#read 5, iclass 21, count 0 2006.201.06:08:48.24#ibcon#about to read 6, iclass 21, count 0 2006.201.06:08:48.24#ibcon#read 6, iclass 21, count 0 2006.201.06:08:48.24#ibcon#end of sib2, iclass 21, count 0 2006.201.06:08:48.24#ibcon#*after write, iclass 21, count 0 2006.201.06:08:48.24#ibcon#*before return 0, iclass 21, count 0 2006.201.06:08:48.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:48.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:08:48.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.06:08:48.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.06:08:48.24$vck44/vblo=6,719.99 2006.201.06:08:48.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.06:08:48.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.06:08:48.24#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:48.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:48.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:48.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:48.24#ibcon#enter wrdev, iclass 23, count 0 2006.201.06:08:48.24#ibcon#first serial, iclass 23, count 0 2006.201.06:08:48.24#ibcon#enter sib2, iclass 23, count 0 2006.201.06:08:48.24#ibcon#flushed, iclass 23, count 0 2006.201.06:08:48.24#ibcon#about to write, iclass 23, count 0 2006.201.06:08:48.24#ibcon#wrote, iclass 23, count 0 2006.201.06:08:48.24#ibcon#about to read 3, iclass 23, count 0 2006.201.06:08:48.26#ibcon#read 3, iclass 23, count 0 2006.201.06:08:48.26#ibcon#about to read 4, iclass 23, count 0 2006.201.06:08:48.26#ibcon#read 4, iclass 23, count 0 2006.201.06:08:48.26#ibcon#about to read 5, iclass 23, count 0 2006.201.06:08:48.26#ibcon#read 5, iclass 23, count 0 2006.201.06:08:48.26#ibcon#about to read 6, iclass 23, count 0 2006.201.06:08:48.26#ibcon#read 6, iclass 23, count 0 2006.201.06:08:48.26#ibcon#end of sib2, iclass 23, count 0 2006.201.06:08:48.26#ibcon#*mode == 0, iclass 23, count 0 2006.201.06:08:48.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.06:08:48.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.06:08:48.26#ibcon#*before write, iclass 23, count 0 2006.201.06:08:48.26#ibcon#enter sib2, iclass 23, count 0 2006.201.06:08:48.26#ibcon#flushed, iclass 23, count 0 2006.201.06:08:48.26#ibcon#about to write, iclass 23, count 0 2006.201.06:08:48.26#ibcon#wrote, iclass 23, count 0 2006.201.06:08:48.26#ibcon#about to read 3, iclass 23, count 0 2006.201.06:08:48.30#ibcon#read 3, iclass 23, count 0 2006.201.06:08:48.30#ibcon#about to read 4, iclass 23, count 0 2006.201.06:08:48.30#ibcon#read 4, iclass 23, count 0 2006.201.06:08:48.30#ibcon#about to read 5, iclass 23, count 0 2006.201.06:08:48.30#ibcon#read 5, iclass 23, count 0 2006.201.06:08:48.30#ibcon#about to read 6, iclass 23, count 0 2006.201.06:08:48.30#ibcon#read 6, iclass 23, count 0 2006.201.06:08:48.30#ibcon#end of sib2, iclass 23, count 0 2006.201.06:08:48.30#ibcon#*after write, iclass 23, count 0 2006.201.06:08:48.30#ibcon#*before return 0, iclass 23, count 0 2006.201.06:08:48.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:48.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:08:48.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.06:08:48.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.06:08:48.30$vck44/vb=6,4 2006.201.06:08:48.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.06:08:48.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.06:08:48.30#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:48.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:48.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:48.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:48.36#ibcon#enter wrdev, iclass 25, count 2 2006.201.06:08:48.36#ibcon#first serial, iclass 25, count 2 2006.201.06:08:48.36#ibcon#enter sib2, iclass 25, count 2 2006.201.06:08:48.36#ibcon#flushed, iclass 25, count 2 2006.201.06:08:48.36#ibcon#about to write, iclass 25, count 2 2006.201.06:08:48.36#ibcon#wrote, iclass 25, count 2 2006.201.06:08:48.36#ibcon#about to read 3, iclass 25, count 2 2006.201.06:08:48.38#ibcon#read 3, iclass 25, count 2 2006.201.06:08:48.38#ibcon#about to read 4, iclass 25, count 2 2006.201.06:08:48.38#ibcon#read 4, iclass 25, count 2 2006.201.06:08:48.38#ibcon#about to read 5, iclass 25, count 2 2006.201.06:08:48.38#ibcon#read 5, iclass 25, count 2 2006.201.06:08:48.38#ibcon#about to read 6, iclass 25, count 2 2006.201.06:08:48.38#ibcon#read 6, iclass 25, count 2 2006.201.06:08:48.38#ibcon#end of sib2, iclass 25, count 2 2006.201.06:08:48.38#ibcon#*mode == 0, iclass 25, count 2 2006.201.06:08:48.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.06:08:48.38#ibcon#[27=AT06-04\r\n] 2006.201.06:08:48.38#ibcon#*before write, iclass 25, count 2 2006.201.06:08:48.38#ibcon#enter sib2, iclass 25, count 2 2006.201.06:08:48.38#ibcon#flushed, iclass 25, count 2 2006.201.06:08:48.38#ibcon#about to write, iclass 25, count 2 2006.201.06:08:48.38#ibcon#wrote, iclass 25, count 2 2006.201.06:08:48.38#ibcon#about to read 3, iclass 25, count 2 2006.201.06:08:48.41#ibcon#read 3, iclass 25, count 2 2006.201.06:08:48.41#ibcon#about to read 4, iclass 25, count 2 2006.201.06:08:48.41#ibcon#read 4, iclass 25, count 2 2006.201.06:08:48.41#ibcon#about to read 5, iclass 25, count 2 2006.201.06:08:48.41#ibcon#read 5, iclass 25, count 2 2006.201.06:08:48.41#ibcon#about to read 6, iclass 25, count 2 2006.201.06:08:48.41#ibcon#read 6, iclass 25, count 2 2006.201.06:08:48.41#ibcon#end of sib2, iclass 25, count 2 2006.201.06:08:48.41#ibcon#*after write, iclass 25, count 2 2006.201.06:08:48.41#ibcon#*before return 0, iclass 25, count 2 2006.201.06:08:48.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:48.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:08:48.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.06:08:48.41#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:48.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:48.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:48.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:48.53#ibcon#enter wrdev, iclass 25, count 0 2006.201.06:08:48.53#ibcon#first serial, iclass 25, count 0 2006.201.06:08:48.53#ibcon#enter sib2, iclass 25, count 0 2006.201.06:08:48.53#ibcon#flushed, iclass 25, count 0 2006.201.06:08:48.53#ibcon#about to write, iclass 25, count 0 2006.201.06:08:48.53#ibcon#wrote, iclass 25, count 0 2006.201.06:08:48.53#ibcon#about to read 3, iclass 25, count 0 2006.201.06:08:48.55#ibcon#read 3, iclass 25, count 0 2006.201.06:08:48.55#ibcon#about to read 4, iclass 25, count 0 2006.201.06:08:48.55#ibcon#read 4, iclass 25, count 0 2006.201.06:08:48.55#ibcon#about to read 5, iclass 25, count 0 2006.201.06:08:48.55#ibcon#read 5, iclass 25, count 0 2006.201.06:08:48.55#ibcon#about to read 6, iclass 25, count 0 2006.201.06:08:48.55#ibcon#read 6, iclass 25, count 0 2006.201.06:08:48.55#ibcon#end of sib2, iclass 25, count 0 2006.201.06:08:48.55#ibcon#*mode == 0, iclass 25, count 0 2006.201.06:08:48.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.06:08:48.55#ibcon#[27=USB\r\n] 2006.201.06:08:48.55#ibcon#*before write, iclass 25, count 0 2006.201.06:08:48.55#ibcon#enter sib2, iclass 25, count 0 2006.201.06:08:48.55#ibcon#flushed, iclass 25, count 0 2006.201.06:08:48.55#ibcon#about to write, iclass 25, count 0 2006.201.06:08:48.55#ibcon#wrote, iclass 25, count 0 2006.201.06:08:48.55#ibcon#about to read 3, iclass 25, count 0 2006.201.06:08:48.58#ibcon#read 3, iclass 25, count 0 2006.201.06:08:48.58#ibcon#about to read 4, iclass 25, count 0 2006.201.06:08:48.58#ibcon#read 4, iclass 25, count 0 2006.201.06:08:48.58#ibcon#about to read 5, iclass 25, count 0 2006.201.06:08:48.58#ibcon#read 5, iclass 25, count 0 2006.201.06:08:48.58#ibcon#about to read 6, iclass 25, count 0 2006.201.06:08:48.58#ibcon#read 6, iclass 25, count 0 2006.201.06:08:48.58#ibcon#end of sib2, iclass 25, count 0 2006.201.06:08:48.58#ibcon#*after write, iclass 25, count 0 2006.201.06:08:48.58#ibcon#*before return 0, iclass 25, count 0 2006.201.06:08:48.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:48.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:08:48.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.06:08:48.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.06:08:48.58$vck44/vblo=7,734.99 2006.201.06:08:48.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.06:08:48.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.06:08:48.58#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:48.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:48.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:48.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:48.58#ibcon#enter wrdev, iclass 27, count 0 2006.201.06:08:48.58#ibcon#first serial, iclass 27, count 0 2006.201.06:08:48.58#ibcon#enter sib2, iclass 27, count 0 2006.201.06:08:48.58#ibcon#flushed, iclass 27, count 0 2006.201.06:08:48.58#ibcon#about to write, iclass 27, count 0 2006.201.06:08:48.58#ibcon#wrote, iclass 27, count 0 2006.201.06:08:48.58#ibcon#about to read 3, iclass 27, count 0 2006.201.06:08:48.60#ibcon#read 3, iclass 27, count 0 2006.201.06:08:48.60#ibcon#about to read 4, iclass 27, count 0 2006.201.06:08:48.60#ibcon#read 4, iclass 27, count 0 2006.201.06:08:48.60#ibcon#about to read 5, iclass 27, count 0 2006.201.06:08:48.60#ibcon#read 5, iclass 27, count 0 2006.201.06:08:48.60#ibcon#about to read 6, iclass 27, count 0 2006.201.06:08:48.60#ibcon#read 6, iclass 27, count 0 2006.201.06:08:48.60#ibcon#end of sib2, iclass 27, count 0 2006.201.06:08:48.60#ibcon#*mode == 0, iclass 27, count 0 2006.201.06:08:48.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.06:08:48.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.06:08:48.60#ibcon#*before write, iclass 27, count 0 2006.201.06:08:48.60#ibcon#enter sib2, iclass 27, count 0 2006.201.06:08:48.60#ibcon#flushed, iclass 27, count 0 2006.201.06:08:48.60#ibcon#about to write, iclass 27, count 0 2006.201.06:08:48.60#ibcon#wrote, iclass 27, count 0 2006.201.06:08:48.60#ibcon#about to read 3, iclass 27, count 0 2006.201.06:08:48.64#ibcon#read 3, iclass 27, count 0 2006.201.06:08:48.64#ibcon#about to read 4, iclass 27, count 0 2006.201.06:08:48.64#ibcon#read 4, iclass 27, count 0 2006.201.06:08:48.64#ibcon#about to read 5, iclass 27, count 0 2006.201.06:08:48.64#ibcon#read 5, iclass 27, count 0 2006.201.06:08:48.64#ibcon#about to read 6, iclass 27, count 0 2006.201.06:08:48.64#ibcon#read 6, iclass 27, count 0 2006.201.06:08:48.64#ibcon#end of sib2, iclass 27, count 0 2006.201.06:08:48.64#ibcon#*after write, iclass 27, count 0 2006.201.06:08:48.64#ibcon#*before return 0, iclass 27, count 0 2006.201.06:08:48.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:48.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:08:48.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.06:08:48.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.06:08:48.64$vck44/vb=7,4 2006.201.06:08:48.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.06:08:48.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.06:08:48.64#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:48.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:48.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:48.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:48.70#ibcon#enter wrdev, iclass 29, count 2 2006.201.06:08:48.70#ibcon#first serial, iclass 29, count 2 2006.201.06:08:48.70#ibcon#enter sib2, iclass 29, count 2 2006.201.06:08:48.70#ibcon#flushed, iclass 29, count 2 2006.201.06:08:48.70#ibcon#about to write, iclass 29, count 2 2006.201.06:08:48.70#ibcon#wrote, iclass 29, count 2 2006.201.06:08:48.70#ibcon#about to read 3, iclass 29, count 2 2006.201.06:08:48.72#ibcon#read 3, iclass 29, count 2 2006.201.06:08:48.72#ibcon#about to read 4, iclass 29, count 2 2006.201.06:08:48.72#ibcon#read 4, iclass 29, count 2 2006.201.06:08:48.72#ibcon#about to read 5, iclass 29, count 2 2006.201.06:08:48.72#ibcon#read 5, iclass 29, count 2 2006.201.06:08:48.72#ibcon#about to read 6, iclass 29, count 2 2006.201.06:08:48.72#ibcon#read 6, iclass 29, count 2 2006.201.06:08:48.72#ibcon#end of sib2, iclass 29, count 2 2006.201.06:08:48.72#ibcon#*mode == 0, iclass 29, count 2 2006.201.06:08:48.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.06:08:48.72#ibcon#[27=AT07-04\r\n] 2006.201.06:08:48.72#ibcon#*before write, iclass 29, count 2 2006.201.06:08:48.72#ibcon#enter sib2, iclass 29, count 2 2006.201.06:08:48.72#ibcon#flushed, iclass 29, count 2 2006.201.06:08:48.72#ibcon#about to write, iclass 29, count 2 2006.201.06:08:48.72#ibcon#wrote, iclass 29, count 2 2006.201.06:08:48.72#ibcon#about to read 3, iclass 29, count 2 2006.201.06:08:48.75#ibcon#read 3, iclass 29, count 2 2006.201.06:08:48.75#ibcon#about to read 4, iclass 29, count 2 2006.201.06:08:48.75#ibcon#read 4, iclass 29, count 2 2006.201.06:08:48.75#ibcon#about to read 5, iclass 29, count 2 2006.201.06:08:48.75#ibcon#read 5, iclass 29, count 2 2006.201.06:08:48.75#ibcon#about to read 6, iclass 29, count 2 2006.201.06:08:48.75#ibcon#read 6, iclass 29, count 2 2006.201.06:08:48.75#ibcon#end of sib2, iclass 29, count 2 2006.201.06:08:48.75#ibcon#*after write, iclass 29, count 2 2006.201.06:08:48.75#ibcon#*before return 0, iclass 29, count 2 2006.201.06:08:48.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:48.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:08:48.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.06:08:48.75#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:48.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:48.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:48.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:48.87#ibcon#enter wrdev, iclass 29, count 0 2006.201.06:08:48.87#ibcon#first serial, iclass 29, count 0 2006.201.06:08:48.87#ibcon#enter sib2, iclass 29, count 0 2006.201.06:08:48.87#ibcon#flushed, iclass 29, count 0 2006.201.06:08:48.87#ibcon#about to write, iclass 29, count 0 2006.201.06:08:48.87#ibcon#wrote, iclass 29, count 0 2006.201.06:08:48.87#ibcon#about to read 3, iclass 29, count 0 2006.201.06:08:48.89#ibcon#read 3, iclass 29, count 0 2006.201.06:08:48.89#ibcon#about to read 4, iclass 29, count 0 2006.201.06:08:48.89#ibcon#read 4, iclass 29, count 0 2006.201.06:08:48.89#ibcon#about to read 5, iclass 29, count 0 2006.201.06:08:48.89#ibcon#read 5, iclass 29, count 0 2006.201.06:08:48.89#ibcon#about to read 6, iclass 29, count 0 2006.201.06:08:48.89#ibcon#read 6, iclass 29, count 0 2006.201.06:08:48.89#ibcon#end of sib2, iclass 29, count 0 2006.201.06:08:48.89#ibcon#*mode == 0, iclass 29, count 0 2006.201.06:08:48.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.06:08:48.89#ibcon#[27=USB\r\n] 2006.201.06:08:48.89#ibcon#*before write, iclass 29, count 0 2006.201.06:08:48.89#ibcon#enter sib2, iclass 29, count 0 2006.201.06:08:48.89#ibcon#flushed, iclass 29, count 0 2006.201.06:08:48.89#ibcon#about to write, iclass 29, count 0 2006.201.06:08:48.89#ibcon#wrote, iclass 29, count 0 2006.201.06:08:48.89#ibcon#about to read 3, iclass 29, count 0 2006.201.06:08:48.92#ibcon#read 3, iclass 29, count 0 2006.201.06:08:48.92#ibcon#about to read 4, iclass 29, count 0 2006.201.06:08:48.92#ibcon#read 4, iclass 29, count 0 2006.201.06:08:48.92#ibcon#about to read 5, iclass 29, count 0 2006.201.06:08:48.92#ibcon#read 5, iclass 29, count 0 2006.201.06:08:48.92#ibcon#about to read 6, iclass 29, count 0 2006.201.06:08:48.92#ibcon#read 6, iclass 29, count 0 2006.201.06:08:48.92#ibcon#end of sib2, iclass 29, count 0 2006.201.06:08:48.92#ibcon#*after write, iclass 29, count 0 2006.201.06:08:48.92#ibcon#*before return 0, iclass 29, count 0 2006.201.06:08:48.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:48.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:08:48.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.06:08:48.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.06:08:48.92$vck44/vblo=8,744.99 2006.201.06:08:48.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.06:08:48.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.06:08:48.92#ibcon#ireg 17 cls_cnt 0 2006.201.06:08:48.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:48.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:48.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:48.92#ibcon#enter wrdev, iclass 31, count 0 2006.201.06:08:48.92#ibcon#first serial, iclass 31, count 0 2006.201.06:08:48.92#ibcon#enter sib2, iclass 31, count 0 2006.201.06:08:48.92#ibcon#flushed, iclass 31, count 0 2006.201.06:08:48.92#ibcon#about to write, iclass 31, count 0 2006.201.06:08:48.92#ibcon#wrote, iclass 31, count 0 2006.201.06:08:48.92#ibcon#about to read 3, iclass 31, count 0 2006.201.06:08:48.94#ibcon#read 3, iclass 31, count 0 2006.201.06:08:48.94#ibcon#about to read 4, iclass 31, count 0 2006.201.06:08:48.94#ibcon#read 4, iclass 31, count 0 2006.201.06:08:48.94#ibcon#about to read 5, iclass 31, count 0 2006.201.06:08:48.94#ibcon#read 5, iclass 31, count 0 2006.201.06:08:48.94#ibcon#about to read 6, iclass 31, count 0 2006.201.06:08:48.94#ibcon#read 6, iclass 31, count 0 2006.201.06:08:48.94#ibcon#end of sib2, iclass 31, count 0 2006.201.06:08:48.94#ibcon#*mode == 0, iclass 31, count 0 2006.201.06:08:48.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.06:08:48.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.06:08:48.94#ibcon#*before write, iclass 31, count 0 2006.201.06:08:48.94#ibcon#enter sib2, iclass 31, count 0 2006.201.06:08:48.94#ibcon#flushed, iclass 31, count 0 2006.201.06:08:48.94#ibcon#about to write, iclass 31, count 0 2006.201.06:08:48.94#ibcon#wrote, iclass 31, count 0 2006.201.06:08:48.94#ibcon#about to read 3, iclass 31, count 0 2006.201.06:08:48.99#ibcon#read 3, iclass 31, count 0 2006.201.06:08:48.99#ibcon#about to read 4, iclass 31, count 0 2006.201.06:08:48.99#ibcon#read 4, iclass 31, count 0 2006.201.06:08:48.99#ibcon#about to read 5, iclass 31, count 0 2006.201.06:08:48.99#ibcon#read 5, iclass 31, count 0 2006.201.06:08:48.99#ibcon#about to read 6, iclass 31, count 0 2006.201.06:08:48.99#ibcon#read 6, iclass 31, count 0 2006.201.06:08:48.99#ibcon#end of sib2, iclass 31, count 0 2006.201.06:08:48.99#ibcon#*after write, iclass 31, count 0 2006.201.06:08:48.99#ibcon#*before return 0, iclass 31, count 0 2006.201.06:08:48.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:48.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:08:48.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.06:08:48.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.06:08:48.99$vck44/vb=8,4 2006.201.06:08:48.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.06:08:48.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.06:08:48.99#ibcon#ireg 11 cls_cnt 2 2006.201.06:08:48.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:49.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:49.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:49.04#ibcon#enter wrdev, iclass 33, count 2 2006.201.06:08:49.04#ibcon#first serial, iclass 33, count 2 2006.201.06:08:49.04#ibcon#enter sib2, iclass 33, count 2 2006.201.06:08:49.04#ibcon#flushed, iclass 33, count 2 2006.201.06:08:49.04#ibcon#about to write, iclass 33, count 2 2006.201.06:08:49.04#ibcon#wrote, iclass 33, count 2 2006.201.06:08:49.04#ibcon#about to read 3, iclass 33, count 2 2006.201.06:08:49.06#ibcon#read 3, iclass 33, count 2 2006.201.06:08:49.06#ibcon#about to read 4, iclass 33, count 2 2006.201.06:08:49.06#ibcon#read 4, iclass 33, count 2 2006.201.06:08:49.06#ibcon#about to read 5, iclass 33, count 2 2006.201.06:08:49.06#ibcon#read 5, iclass 33, count 2 2006.201.06:08:49.06#ibcon#about to read 6, iclass 33, count 2 2006.201.06:08:49.06#ibcon#read 6, iclass 33, count 2 2006.201.06:08:49.06#ibcon#end of sib2, iclass 33, count 2 2006.201.06:08:49.06#ibcon#*mode == 0, iclass 33, count 2 2006.201.06:08:49.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.06:08:49.06#ibcon#[27=AT08-04\r\n] 2006.201.06:08:49.06#ibcon#*before write, iclass 33, count 2 2006.201.06:08:49.06#ibcon#enter sib2, iclass 33, count 2 2006.201.06:08:49.06#ibcon#flushed, iclass 33, count 2 2006.201.06:08:49.06#ibcon#about to write, iclass 33, count 2 2006.201.06:08:49.06#ibcon#wrote, iclass 33, count 2 2006.201.06:08:49.06#ibcon#about to read 3, iclass 33, count 2 2006.201.06:08:49.09#ibcon#read 3, iclass 33, count 2 2006.201.06:08:49.09#ibcon#about to read 4, iclass 33, count 2 2006.201.06:08:49.09#ibcon#read 4, iclass 33, count 2 2006.201.06:08:49.09#ibcon#about to read 5, iclass 33, count 2 2006.201.06:08:49.09#ibcon#read 5, iclass 33, count 2 2006.201.06:08:49.09#ibcon#about to read 6, iclass 33, count 2 2006.201.06:08:49.09#ibcon#read 6, iclass 33, count 2 2006.201.06:08:49.09#ibcon#end of sib2, iclass 33, count 2 2006.201.06:08:49.09#ibcon#*after write, iclass 33, count 2 2006.201.06:08:49.09#ibcon#*before return 0, iclass 33, count 2 2006.201.06:08:49.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:49.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:08:49.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.06:08:49.09#ibcon#ireg 7 cls_cnt 0 2006.201.06:08:49.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:49.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:49.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:49.21#ibcon#enter wrdev, iclass 33, count 0 2006.201.06:08:49.21#ibcon#first serial, iclass 33, count 0 2006.201.06:08:49.21#ibcon#enter sib2, iclass 33, count 0 2006.201.06:08:49.21#ibcon#flushed, iclass 33, count 0 2006.201.06:08:49.21#ibcon#about to write, iclass 33, count 0 2006.201.06:08:49.21#ibcon#wrote, iclass 33, count 0 2006.201.06:08:49.21#ibcon#about to read 3, iclass 33, count 0 2006.201.06:08:49.23#ibcon#read 3, iclass 33, count 0 2006.201.06:08:49.23#ibcon#about to read 4, iclass 33, count 0 2006.201.06:08:49.23#ibcon#read 4, iclass 33, count 0 2006.201.06:08:49.23#ibcon#about to read 5, iclass 33, count 0 2006.201.06:08:49.23#ibcon#read 5, iclass 33, count 0 2006.201.06:08:49.23#ibcon#about to read 6, iclass 33, count 0 2006.201.06:08:49.23#ibcon#read 6, iclass 33, count 0 2006.201.06:08:49.23#ibcon#end of sib2, iclass 33, count 0 2006.201.06:08:49.23#ibcon#*mode == 0, iclass 33, count 0 2006.201.06:08:49.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.06:08:49.23#ibcon#[27=USB\r\n] 2006.201.06:08:49.23#ibcon#*before write, iclass 33, count 0 2006.201.06:08:49.23#ibcon#enter sib2, iclass 33, count 0 2006.201.06:08:49.23#ibcon#flushed, iclass 33, count 0 2006.201.06:08:49.23#ibcon#about to write, iclass 33, count 0 2006.201.06:08:49.23#ibcon#wrote, iclass 33, count 0 2006.201.06:08:49.23#ibcon#about to read 3, iclass 33, count 0 2006.201.06:08:49.26#ibcon#read 3, iclass 33, count 0 2006.201.06:08:49.26#ibcon#about to read 4, iclass 33, count 0 2006.201.06:08:49.26#ibcon#read 4, iclass 33, count 0 2006.201.06:08:49.26#ibcon#about to read 5, iclass 33, count 0 2006.201.06:08:49.26#ibcon#read 5, iclass 33, count 0 2006.201.06:08:49.26#ibcon#about to read 6, iclass 33, count 0 2006.201.06:08:49.26#ibcon#read 6, iclass 33, count 0 2006.201.06:08:49.26#ibcon#end of sib2, iclass 33, count 0 2006.201.06:08:49.26#ibcon#*after write, iclass 33, count 0 2006.201.06:08:49.26#ibcon#*before return 0, iclass 33, count 0 2006.201.06:08:49.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:49.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:08:49.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.06:08:49.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.06:08:49.26$vck44/vabw=wide 2006.201.06:08:49.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.06:08:49.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.06:08:49.26#ibcon#ireg 8 cls_cnt 0 2006.201.06:08:49.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:49.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:49.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:49.26#ibcon#enter wrdev, iclass 35, count 0 2006.201.06:08:49.26#ibcon#first serial, iclass 35, count 0 2006.201.06:08:49.26#ibcon#enter sib2, iclass 35, count 0 2006.201.06:08:49.26#ibcon#flushed, iclass 35, count 0 2006.201.06:08:49.26#ibcon#about to write, iclass 35, count 0 2006.201.06:08:49.26#ibcon#wrote, iclass 35, count 0 2006.201.06:08:49.26#ibcon#about to read 3, iclass 35, count 0 2006.201.06:08:49.28#ibcon#read 3, iclass 35, count 0 2006.201.06:08:49.28#ibcon#about to read 4, iclass 35, count 0 2006.201.06:08:49.28#ibcon#read 4, iclass 35, count 0 2006.201.06:08:49.28#ibcon#about to read 5, iclass 35, count 0 2006.201.06:08:49.28#ibcon#read 5, iclass 35, count 0 2006.201.06:08:49.28#ibcon#about to read 6, iclass 35, count 0 2006.201.06:08:49.28#ibcon#read 6, iclass 35, count 0 2006.201.06:08:49.28#ibcon#end of sib2, iclass 35, count 0 2006.201.06:08:49.28#ibcon#*mode == 0, iclass 35, count 0 2006.201.06:08:49.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.06:08:49.28#ibcon#[25=BW32\r\n] 2006.201.06:08:49.28#ibcon#*before write, iclass 35, count 0 2006.201.06:08:49.28#ibcon#enter sib2, iclass 35, count 0 2006.201.06:08:49.28#ibcon#flushed, iclass 35, count 0 2006.201.06:08:49.28#ibcon#about to write, iclass 35, count 0 2006.201.06:08:49.28#ibcon#wrote, iclass 35, count 0 2006.201.06:08:49.28#ibcon#about to read 3, iclass 35, count 0 2006.201.06:08:49.31#ibcon#read 3, iclass 35, count 0 2006.201.06:08:49.31#ibcon#about to read 4, iclass 35, count 0 2006.201.06:08:49.31#ibcon#read 4, iclass 35, count 0 2006.201.06:08:49.31#ibcon#about to read 5, iclass 35, count 0 2006.201.06:08:49.31#ibcon#read 5, iclass 35, count 0 2006.201.06:08:49.31#ibcon#about to read 6, iclass 35, count 0 2006.201.06:08:49.31#ibcon#read 6, iclass 35, count 0 2006.201.06:08:49.31#ibcon#end of sib2, iclass 35, count 0 2006.201.06:08:49.31#ibcon#*after write, iclass 35, count 0 2006.201.06:08:49.31#ibcon#*before return 0, iclass 35, count 0 2006.201.06:08:49.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:49.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:08:49.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.06:08:49.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.06:08:49.31$vck44/vbbw=wide 2006.201.06:08:49.31#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.06:08:49.31#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.06:08:49.31#ibcon#ireg 8 cls_cnt 0 2006.201.06:08:49.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:08:49.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:08:49.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:08:49.38#ibcon#enter wrdev, iclass 37, count 0 2006.201.06:08:49.38#ibcon#first serial, iclass 37, count 0 2006.201.06:08:49.38#ibcon#enter sib2, iclass 37, count 0 2006.201.06:08:49.38#ibcon#flushed, iclass 37, count 0 2006.201.06:08:49.38#ibcon#about to write, iclass 37, count 0 2006.201.06:08:49.38#ibcon#wrote, iclass 37, count 0 2006.201.06:08:49.38#ibcon#about to read 3, iclass 37, count 0 2006.201.06:08:49.40#ibcon#read 3, iclass 37, count 0 2006.201.06:08:49.40#ibcon#about to read 4, iclass 37, count 0 2006.201.06:08:49.40#ibcon#read 4, iclass 37, count 0 2006.201.06:08:49.40#ibcon#about to read 5, iclass 37, count 0 2006.201.06:08:49.40#ibcon#read 5, iclass 37, count 0 2006.201.06:08:49.40#ibcon#about to read 6, iclass 37, count 0 2006.201.06:08:49.40#ibcon#read 6, iclass 37, count 0 2006.201.06:08:49.40#ibcon#end of sib2, iclass 37, count 0 2006.201.06:08:49.40#ibcon#*mode == 0, iclass 37, count 0 2006.201.06:08:49.40#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.06:08:49.40#ibcon#[27=BW32\r\n] 2006.201.06:08:49.40#ibcon#*before write, iclass 37, count 0 2006.201.06:08:49.40#ibcon#enter sib2, iclass 37, count 0 2006.201.06:08:49.40#ibcon#flushed, iclass 37, count 0 2006.201.06:08:49.40#ibcon#about to write, iclass 37, count 0 2006.201.06:08:49.40#ibcon#wrote, iclass 37, count 0 2006.201.06:08:49.40#ibcon#about to read 3, iclass 37, count 0 2006.201.06:08:49.43#ibcon#read 3, iclass 37, count 0 2006.201.06:08:49.43#ibcon#about to read 4, iclass 37, count 0 2006.201.06:08:49.43#ibcon#read 4, iclass 37, count 0 2006.201.06:08:49.43#ibcon#about to read 5, iclass 37, count 0 2006.201.06:08:49.43#ibcon#read 5, iclass 37, count 0 2006.201.06:08:49.43#ibcon#about to read 6, iclass 37, count 0 2006.201.06:08:49.43#ibcon#read 6, iclass 37, count 0 2006.201.06:08:49.43#ibcon#end of sib2, iclass 37, count 0 2006.201.06:08:49.43#ibcon#*after write, iclass 37, count 0 2006.201.06:08:49.43#ibcon#*before return 0, iclass 37, count 0 2006.201.06:08:49.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:08:49.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:08:49.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.06:08:49.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.06:08:49.43$setupk4/ifdk4 2006.201.06:08:49.43$ifdk4/lo= 2006.201.06:08:49.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.06:08:49.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.06:08:49.43$ifdk4/patch= 2006.201.06:08:49.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.06:08:49.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.06:08:49.43$setupk4/!*+20s 2006.201.06:08:52.69#abcon#<5=/04 2.6 5.0 22.94 881003.3\r\n> 2006.201.06:08:52.71#abcon#{5=INTERFACE CLEAR} 2006.201.06:08:52.77#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:09:02.86#abcon#<5=/04 2.6 5.0 22.94 881003.3\r\n> 2006.201.06:09:02.88#abcon#{5=INTERFACE CLEAR} 2006.201.06:09:02.94#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:09:03.91$setupk4/"tpicd 2006.201.06:09:03.91$setupk4/echo=off 2006.201.06:09:03.91$setupk4/xlog=off 2006.201.06:09:03.91:!2006.201.06:15:52 2006.201.06:09:13.14#trakl#Source acquired 2006.201.06:09:13.14#flagr#flagr/antenna,acquired 2006.201.06:15:52.00:preob 2006.201.06:15:53.14/onsource/TRACKING 2006.201.06:15:53.14:!2006.201.06:16:02 2006.201.06:16:02.00:"tape 2006.201.06:16:02.00:"st=record 2006.201.06:16:02.00:data_valid=on 2006.201.06:16:02.00:midob 2006.201.06:16:02.14/onsource/TRACKING 2006.201.06:16:02.14/wx/22.99,1003.3,88 2006.201.06:16:02.31/cable/+6.4647E-03 2006.201.06:16:03.40/va/01,08,usb,yes,28,30 2006.201.06:16:03.40/va/02,07,usb,yes,30,30 2006.201.06:16:03.40/va/03,08,usb,yes,27,28 2006.201.06:16:03.40/va/04,07,usb,yes,31,32 2006.201.06:16:03.40/va/05,04,usb,yes,27,27 2006.201.06:16:03.40/va/06,05,usb,yes,27,27 2006.201.06:16:03.40/va/07,05,usb,yes,26,27 2006.201.06:16:03.40/va/08,04,usb,yes,26,32 2006.201.06:16:03.63/valo/01,524.99,yes,locked 2006.201.06:16:03.63/valo/02,534.99,yes,locked 2006.201.06:16:03.63/valo/03,564.99,yes,locked 2006.201.06:16:03.63/valo/04,624.99,yes,locked 2006.201.06:16:03.63/valo/05,734.99,yes,locked 2006.201.06:16:03.63/valo/06,814.99,yes,locked 2006.201.06:16:03.63/valo/07,864.99,yes,locked 2006.201.06:16:03.63/valo/08,884.99,yes,locked 2006.201.06:16:04.72/vb/01,04,usb,yes,28,26 2006.201.06:16:04.72/vb/02,05,usb,yes,27,27 2006.201.06:16:04.72/vb/03,04,usb,yes,28,31 2006.201.06:16:04.72/vb/04,05,usb,yes,28,27 2006.201.06:16:04.72/vb/05,04,usb,yes,25,27 2006.201.06:16:04.72/vb/06,04,usb,yes,29,25 2006.201.06:16:04.72/vb/07,04,usb,yes,29,29 2006.201.06:16:04.72/vb/08,04,usb,yes,27,30 2006.201.06:16:04.96/vblo/01,629.99,yes,locked 2006.201.06:16:04.96/vblo/02,634.99,yes,locked 2006.201.06:16:04.96/vblo/03,649.99,yes,locked 2006.201.06:16:04.96/vblo/04,679.99,yes,locked 2006.201.06:16:04.96/vblo/05,709.99,yes,locked 2006.201.06:16:04.96/vblo/06,719.99,yes,locked 2006.201.06:16:04.96/vblo/07,734.99,yes,locked 2006.201.06:16:04.96/vblo/08,744.99,yes,locked 2006.201.06:16:05.11/vabw/8 2006.201.06:16:05.26/vbbw/8 2006.201.06:16:05.35/xfe/off,on,15.0 2006.201.06:16:05.72/ifatt/23,28,28,28 2006.201.06:16:06.05/fmout-gps/S +4.48E-07 2006.201.06:16:06.12:!2006.201.06:23:02 2006.201.06:23:02.00:data_valid=off 2006.201.06:23:02.00:"et 2006.201.06:23:02.00:!+3s 2006.201.06:23:05.02:"tape 2006.201.06:23:05.02:postob 2006.201.06:23:05.24/cable/+6.4653E-03 2006.201.06:23:05.24/wx/23.00,1003.3,87 2006.201.06:23:05.32/fmout-gps/S +4.50E-07 2006.201.06:23:05.32:scan_name=201-0629,jd0607,350 2006.201.06:23:05.32:source=oq208,140700.39,282714.7,2000.0,cw 2006.201.06:23:06.14#flagr#flagr/antenna,new-source 2006.201.06:23:06.14:checkk5 2006.201.06:23:06.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.06:23:06.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.06:23:07.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.06:23:07.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.06:23:08.05/chk_obsdata//k5ts1/T2010616??a.dat file size is correct (nominal:1680MB, actual:1676MB). 2006.201.06:23:08.42/chk_obsdata//k5ts2/T2010616??b.dat file size is correct (nominal:1680MB, actual:1676MB). 2006.201.06:23:08.79/chk_obsdata//k5ts3/T2010616??c.dat file size is correct (nominal:1680MB, actual:1676MB). 2006.201.06:23:09.16/chk_obsdata//k5ts4/T2010616??d.dat file size is correct (nominal:1680MB, actual:1676MB). 2006.201.06:23:09.85/k5log//k5ts1_log_newline 2006.201.06:23:10.53/k5log//k5ts2_log_newline 2006.201.06:23:11.21/k5log//k5ts3_log_newline 2006.201.06:23:11.91/k5log//k5ts4_log_newline 2006.201.06:23:11.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.06:23:11.93:setupk4=1 2006.201.06:23:11.93$setupk4/echo=on 2006.201.06:23:11.93$setupk4/pcalon 2006.201.06:23:11.93$pcalon/"no phase cal control is implemented here 2006.201.06:23:11.93$setupk4/"tpicd=stop 2006.201.06:23:11.93$setupk4/"rec=synch_on 2006.201.06:23:11.93$setupk4/"rec_mode=128 2006.201.06:23:11.93$setupk4/!* 2006.201.06:23:11.93$setupk4/recpk4 2006.201.06:23:11.93$recpk4/recpatch= 2006.201.06:23:11.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.06:23:11.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.06:23:11.94$setupk4/vck44 2006.201.06:23:11.94$vck44/valo=1,524.99 2006.201.06:23:11.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.06:23:11.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.06:23:11.94#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:11.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:11.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:11.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:11.94#ibcon#enter wrdev, iclass 17, count 0 2006.201.06:23:11.94#ibcon#first serial, iclass 17, count 0 2006.201.06:23:11.94#ibcon#enter sib2, iclass 17, count 0 2006.201.06:23:11.94#ibcon#flushed, iclass 17, count 0 2006.201.06:23:11.94#ibcon#about to write, iclass 17, count 0 2006.201.06:23:11.94#ibcon#wrote, iclass 17, count 0 2006.201.06:23:11.94#ibcon#about to read 3, iclass 17, count 0 2006.201.06:23:11.98#ibcon#read 3, iclass 17, count 0 2006.201.06:23:11.98#ibcon#about to read 4, iclass 17, count 0 2006.201.06:23:11.98#ibcon#read 4, iclass 17, count 0 2006.201.06:23:11.98#ibcon#about to read 5, iclass 17, count 0 2006.201.06:23:11.98#ibcon#read 5, iclass 17, count 0 2006.201.06:23:11.98#ibcon#about to read 6, iclass 17, count 0 2006.201.06:23:11.98#ibcon#read 6, iclass 17, count 0 2006.201.06:23:11.98#ibcon#end of sib2, iclass 17, count 0 2006.201.06:23:11.98#ibcon#*mode == 0, iclass 17, count 0 2006.201.06:23:11.98#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.06:23:11.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.06:23:11.98#ibcon#*before write, iclass 17, count 0 2006.201.06:23:11.98#ibcon#enter sib2, iclass 17, count 0 2006.201.06:23:11.98#ibcon#flushed, iclass 17, count 0 2006.201.06:23:11.98#ibcon#about to write, iclass 17, count 0 2006.201.06:23:11.98#ibcon#wrote, iclass 17, count 0 2006.201.06:23:11.98#ibcon#about to read 3, iclass 17, count 0 2006.201.06:23:12.03#ibcon#read 3, iclass 17, count 0 2006.201.06:23:12.03#ibcon#about to read 4, iclass 17, count 0 2006.201.06:23:12.03#ibcon#read 4, iclass 17, count 0 2006.201.06:23:12.03#ibcon#about to read 5, iclass 17, count 0 2006.201.06:23:12.03#ibcon#read 5, iclass 17, count 0 2006.201.06:23:12.03#ibcon#about to read 6, iclass 17, count 0 2006.201.06:23:12.03#ibcon#read 6, iclass 17, count 0 2006.201.06:23:12.03#ibcon#end of sib2, iclass 17, count 0 2006.201.06:23:12.03#ibcon#*after write, iclass 17, count 0 2006.201.06:23:12.03#ibcon#*before return 0, iclass 17, count 0 2006.201.06:23:12.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:12.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:12.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.06:23:12.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.06:23:12.03$vck44/va=1,8 2006.201.06:23:12.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.06:23:12.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.06:23:12.03#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:12.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:12.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:12.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:12.03#ibcon#enter wrdev, iclass 19, count 2 2006.201.06:23:12.03#ibcon#first serial, iclass 19, count 2 2006.201.06:23:12.03#ibcon#enter sib2, iclass 19, count 2 2006.201.06:23:12.03#ibcon#flushed, iclass 19, count 2 2006.201.06:23:12.03#ibcon#about to write, iclass 19, count 2 2006.201.06:23:12.03#ibcon#wrote, iclass 19, count 2 2006.201.06:23:12.03#ibcon#about to read 3, iclass 19, count 2 2006.201.06:23:12.05#ibcon#read 3, iclass 19, count 2 2006.201.06:23:12.05#ibcon#about to read 4, iclass 19, count 2 2006.201.06:23:12.05#ibcon#read 4, iclass 19, count 2 2006.201.06:23:12.05#ibcon#about to read 5, iclass 19, count 2 2006.201.06:23:12.05#ibcon#read 5, iclass 19, count 2 2006.201.06:23:12.05#ibcon#about to read 6, iclass 19, count 2 2006.201.06:23:12.05#ibcon#read 6, iclass 19, count 2 2006.201.06:23:12.05#ibcon#end of sib2, iclass 19, count 2 2006.201.06:23:12.05#ibcon#*mode == 0, iclass 19, count 2 2006.201.06:23:12.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.06:23:12.05#ibcon#[25=AT01-08\r\n] 2006.201.06:23:12.05#ibcon#*before write, iclass 19, count 2 2006.201.06:23:12.05#ibcon#enter sib2, iclass 19, count 2 2006.201.06:23:12.05#ibcon#flushed, iclass 19, count 2 2006.201.06:23:12.05#ibcon#about to write, iclass 19, count 2 2006.201.06:23:12.05#ibcon#wrote, iclass 19, count 2 2006.201.06:23:12.05#ibcon#about to read 3, iclass 19, count 2 2006.201.06:23:12.09#ibcon#read 3, iclass 19, count 2 2006.201.06:23:12.09#ibcon#about to read 4, iclass 19, count 2 2006.201.06:23:12.09#ibcon#read 4, iclass 19, count 2 2006.201.06:23:12.09#ibcon#about to read 5, iclass 19, count 2 2006.201.06:23:12.09#ibcon#read 5, iclass 19, count 2 2006.201.06:23:12.09#ibcon#about to read 6, iclass 19, count 2 2006.201.06:23:12.09#ibcon#read 6, iclass 19, count 2 2006.201.06:23:12.09#ibcon#end of sib2, iclass 19, count 2 2006.201.06:23:12.09#ibcon#*after write, iclass 19, count 2 2006.201.06:23:12.09#ibcon#*before return 0, iclass 19, count 2 2006.201.06:23:12.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:12.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:12.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.06:23:12.09#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:12.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:12.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:12.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:12.21#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:23:12.21#ibcon#first serial, iclass 19, count 0 2006.201.06:23:12.21#ibcon#enter sib2, iclass 19, count 0 2006.201.06:23:12.21#ibcon#flushed, iclass 19, count 0 2006.201.06:23:12.21#ibcon#about to write, iclass 19, count 0 2006.201.06:23:12.21#ibcon#wrote, iclass 19, count 0 2006.201.06:23:12.21#ibcon#about to read 3, iclass 19, count 0 2006.201.06:23:12.23#ibcon#read 3, iclass 19, count 0 2006.201.06:23:12.23#ibcon#about to read 4, iclass 19, count 0 2006.201.06:23:12.23#ibcon#read 4, iclass 19, count 0 2006.201.06:23:12.23#ibcon#about to read 5, iclass 19, count 0 2006.201.06:23:12.23#ibcon#read 5, iclass 19, count 0 2006.201.06:23:12.23#ibcon#about to read 6, iclass 19, count 0 2006.201.06:23:12.23#ibcon#read 6, iclass 19, count 0 2006.201.06:23:12.23#ibcon#end of sib2, iclass 19, count 0 2006.201.06:23:12.23#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:23:12.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:23:12.23#ibcon#[25=USB\r\n] 2006.201.06:23:12.23#ibcon#*before write, iclass 19, count 0 2006.201.06:23:12.23#ibcon#enter sib2, iclass 19, count 0 2006.201.06:23:12.23#ibcon#flushed, iclass 19, count 0 2006.201.06:23:12.23#ibcon#about to write, iclass 19, count 0 2006.201.06:23:12.23#ibcon#wrote, iclass 19, count 0 2006.201.06:23:12.23#ibcon#about to read 3, iclass 19, count 0 2006.201.06:23:12.26#ibcon#read 3, iclass 19, count 0 2006.201.06:23:12.26#ibcon#about to read 4, iclass 19, count 0 2006.201.06:23:12.26#ibcon#read 4, iclass 19, count 0 2006.201.06:23:12.26#ibcon#about to read 5, iclass 19, count 0 2006.201.06:23:12.26#ibcon#read 5, iclass 19, count 0 2006.201.06:23:12.26#ibcon#about to read 6, iclass 19, count 0 2006.201.06:23:12.26#ibcon#read 6, iclass 19, count 0 2006.201.06:23:12.26#ibcon#end of sib2, iclass 19, count 0 2006.201.06:23:12.26#ibcon#*after write, iclass 19, count 0 2006.201.06:23:12.26#ibcon#*before return 0, iclass 19, count 0 2006.201.06:23:12.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:12.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:12.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:23:12.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:23:12.26$vck44/valo=2,534.99 2006.201.06:23:12.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.06:23:12.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.06:23:12.26#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:12.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:12.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:12.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:12.26#ibcon#enter wrdev, iclass 21, count 0 2006.201.06:23:12.26#ibcon#first serial, iclass 21, count 0 2006.201.06:23:12.26#ibcon#enter sib2, iclass 21, count 0 2006.201.06:23:12.26#ibcon#flushed, iclass 21, count 0 2006.201.06:23:12.26#ibcon#about to write, iclass 21, count 0 2006.201.06:23:12.26#ibcon#wrote, iclass 21, count 0 2006.201.06:23:12.26#ibcon#about to read 3, iclass 21, count 0 2006.201.06:23:12.28#ibcon#read 3, iclass 21, count 0 2006.201.06:23:12.28#ibcon#about to read 4, iclass 21, count 0 2006.201.06:23:12.28#ibcon#read 4, iclass 21, count 0 2006.201.06:23:12.28#ibcon#about to read 5, iclass 21, count 0 2006.201.06:23:12.28#ibcon#read 5, iclass 21, count 0 2006.201.06:23:12.28#ibcon#about to read 6, iclass 21, count 0 2006.201.06:23:12.28#ibcon#read 6, iclass 21, count 0 2006.201.06:23:12.28#ibcon#end of sib2, iclass 21, count 0 2006.201.06:23:12.28#ibcon#*mode == 0, iclass 21, count 0 2006.201.06:23:12.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.06:23:12.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.06:23:12.28#ibcon#*before write, iclass 21, count 0 2006.201.06:23:12.28#ibcon#enter sib2, iclass 21, count 0 2006.201.06:23:12.28#ibcon#flushed, iclass 21, count 0 2006.201.06:23:12.28#ibcon#about to write, iclass 21, count 0 2006.201.06:23:12.28#ibcon#wrote, iclass 21, count 0 2006.201.06:23:12.28#ibcon#about to read 3, iclass 21, count 0 2006.201.06:23:12.33#ibcon#read 3, iclass 21, count 0 2006.201.06:23:12.33#ibcon#about to read 4, iclass 21, count 0 2006.201.06:23:12.33#ibcon#read 4, iclass 21, count 0 2006.201.06:23:12.33#ibcon#about to read 5, iclass 21, count 0 2006.201.06:23:12.33#ibcon#read 5, iclass 21, count 0 2006.201.06:23:12.33#ibcon#about to read 6, iclass 21, count 0 2006.201.06:23:12.33#ibcon#read 6, iclass 21, count 0 2006.201.06:23:12.33#ibcon#end of sib2, iclass 21, count 0 2006.201.06:23:12.33#ibcon#*after write, iclass 21, count 0 2006.201.06:23:12.33#ibcon#*before return 0, iclass 21, count 0 2006.201.06:23:12.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:12.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:12.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.06:23:12.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.06:23:12.33$vck44/va=2,7 2006.201.06:23:12.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.06:23:12.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.06:23:12.33#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:12.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:12.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:12.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:12.38#ibcon#enter wrdev, iclass 23, count 2 2006.201.06:23:12.38#ibcon#first serial, iclass 23, count 2 2006.201.06:23:12.38#ibcon#enter sib2, iclass 23, count 2 2006.201.06:23:12.38#ibcon#flushed, iclass 23, count 2 2006.201.06:23:12.38#ibcon#about to write, iclass 23, count 2 2006.201.06:23:12.38#ibcon#wrote, iclass 23, count 2 2006.201.06:23:12.38#ibcon#about to read 3, iclass 23, count 2 2006.201.06:23:12.40#ibcon#read 3, iclass 23, count 2 2006.201.06:23:12.40#ibcon#about to read 4, iclass 23, count 2 2006.201.06:23:12.40#ibcon#read 4, iclass 23, count 2 2006.201.06:23:12.40#ibcon#about to read 5, iclass 23, count 2 2006.201.06:23:12.40#ibcon#read 5, iclass 23, count 2 2006.201.06:23:12.40#ibcon#about to read 6, iclass 23, count 2 2006.201.06:23:12.40#ibcon#read 6, iclass 23, count 2 2006.201.06:23:12.40#ibcon#end of sib2, iclass 23, count 2 2006.201.06:23:12.40#ibcon#*mode == 0, iclass 23, count 2 2006.201.06:23:12.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.06:23:12.40#ibcon#[25=AT02-07\r\n] 2006.201.06:23:12.40#ibcon#*before write, iclass 23, count 2 2006.201.06:23:12.40#ibcon#enter sib2, iclass 23, count 2 2006.201.06:23:12.40#ibcon#flushed, iclass 23, count 2 2006.201.06:23:12.40#ibcon#about to write, iclass 23, count 2 2006.201.06:23:12.40#ibcon#wrote, iclass 23, count 2 2006.201.06:23:12.40#ibcon#about to read 3, iclass 23, count 2 2006.201.06:23:12.43#ibcon#read 3, iclass 23, count 2 2006.201.06:23:12.43#ibcon#about to read 4, iclass 23, count 2 2006.201.06:23:12.43#ibcon#read 4, iclass 23, count 2 2006.201.06:23:12.43#ibcon#about to read 5, iclass 23, count 2 2006.201.06:23:12.43#ibcon#read 5, iclass 23, count 2 2006.201.06:23:12.43#ibcon#about to read 6, iclass 23, count 2 2006.201.06:23:12.43#ibcon#read 6, iclass 23, count 2 2006.201.06:23:12.43#ibcon#end of sib2, iclass 23, count 2 2006.201.06:23:12.43#ibcon#*after write, iclass 23, count 2 2006.201.06:23:12.43#ibcon#*before return 0, iclass 23, count 2 2006.201.06:23:12.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:12.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:12.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.06:23:12.43#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:12.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:12.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:12.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:12.55#ibcon#enter wrdev, iclass 23, count 0 2006.201.06:23:12.55#ibcon#first serial, iclass 23, count 0 2006.201.06:23:12.55#ibcon#enter sib2, iclass 23, count 0 2006.201.06:23:12.55#ibcon#flushed, iclass 23, count 0 2006.201.06:23:12.55#ibcon#about to write, iclass 23, count 0 2006.201.06:23:12.55#ibcon#wrote, iclass 23, count 0 2006.201.06:23:12.55#ibcon#about to read 3, iclass 23, count 0 2006.201.06:23:12.57#ibcon#read 3, iclass 23, count 0 2006.201.06:23:12.57#ibcon#about to read 4, iclass 23, count 0 2006.201.06:23:12.57#ibcon#read 4, iclass 23, count 0 2006.201.06:23:12.57#ibcon#about to read 5, iclass 23, count 0 2006.201.06:23:12.57#ibcon#read 5, iclass 23, count 0 2006.201.06:23:12.57#ibcon#about to read 6, iclass 23, count 0 2006.201.06:23:12.57#ibcon#read 6, iclass 23, count 0 2006.201.06:23:12.57#ibcon#end of sib2, iclass 23, count 0 2006.201.06:23:12.57#ibcon#*mode == 0, iclass 23, count 0 2006.201.06:23:12.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.06:23:12.57#ibcon#[25=USB\r\n] 2006.201.06:23:12.57#ibcon#*before write, iclass 23, count 0 2006.201.06:23:12.57#ibcon#enter sib2, iclass 23, count 0 2006.201.06:23:12.57#ibcon#flushed, iclass 23, count 0 2006.201.06:23:12.57#ibcon#about to write, iclass 23, count 0 2006.201.06:23:12.57#ibcon#wrote, iclass 23, count 0 2006.201.06:23:12.57#ibcon#about to read 3, iclass 23, count 0 2006.201.06:23:12.60#ibcon#read 3, iclass 23, count 0 2006.201.06:23:12.60#ibcon#about to read 4, iclass 23, count 0 2006.201.06:23:12.60#ibcon#read 4, iclass 23, count 0 2006.201.06:23:12.60#ibcon#about to read 5, iclass 23, count 0 2006.201.06:23:12.60#ibcon#read 5, iclass 23, count 0 2006.201.06:23:12.60#ibcon#about to read 6, iclass 23, count 0 2006.201.06:23:12.60#ibcon#read 6, iclass 23, count 0 2006.201.06:23:12.60#ibcon#end of sib2, iclass 23, count 0 2006.201.06:23:12.60#ibcon#*after write, iclass 23, count 0 2006.201.06:23:12.60#ibcon#*before return 0, iclass 23, count 0 2006.201.06:23:12.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:12.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:12.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.06:23:12.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.06:23:12.60$vck44/valo=3,564.99 2006.201.06:23:12.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.06:23:12.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.06:23:12.60#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:12.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:12.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:12.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:12.60#ibcon#enter wrdev, iclass 25, count 0 2006.201.06:23:12.60#ibcon#first serial, iclass 25, count 0 2006.201.06:23:12.60#ibcon#enter sib2, iclass 25, count 0 2006.201.06:23:12.60#ibcon#flushed, iclass 25, count 0 2006.201.06:23:12.60#ibcon#about to write, iclass 25, count 0 2006.201.06:23:12.60#ibcon#wrote, iclass 25, count 0 2006.201.06:23:12.60#ibcon#about to read 3, iclass 25, count 0 2006.201.06:23:12.62#ibcon#read 3, iclass 25, count 0 2006.201.06:23:12.62#ibcon#about to read 4, iclass 25, count 0 2006.201.06:23:12.62#ibcon#read 4, iclass 25, count 0 2006.201.06:23:12.62#ibcon#about to read 5, iclass 25, count 0 2006.201.06:23:12.62#ibcon#read 5, iclass 25, count 0 2006.201.06:23:12.62#ibcon#about to read 6, iclass 25, count 0 2006.201.06:23:12.62#ibcon#read 6, iclass 25, count 0 2006.201.06:23:12.62#ibcon#end of sib2, iclass 25, count 0 2006.201.06:23:12.62#ibcon#*mode == 0, iclass 25, count 0 2006.201.06:23:12.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.06:23:12.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.06:23:12.62#ibcon#*before write, iclass 25, count 0 2006.201.06:23:12.62#ibcon#enter sib2, iclass 25, count 0 2006.201.06:23:12.62#ibcon#flushed, iclass 25, count 0 2006.201.06:23:12.62#ibcon#about to write, iclass 25, count 0 2006.201.06:23:12.62#ibcon#wrote, iclass 25, count 0 2006.201.06:23:12.62#ibcon#about to read 3, iclass 25, count 0 2006.201.06:23:12.67#ibcon#read 3, iclass 25, count 0 2006.201.06:23:12.67#ibcon#about to read 4, iclass 25, count 0 2006.201.06:23:12.67#ibcon#read 4, iclass 25, count 0 2006.201.06:23:12.67#ibcon#about to read 5, iclass 25, count 0 2006.201.06:23:12.67#ibcon#read 5, iclass 25, count 0 2006.201.06:23:12.67#ibcon#about to read 6, iclass 25, count 0 2006.201.06:23:12.67#ibcon#read 6, iclass 25, count 0 2006.201.06:23:12.67#ibcon#end of sib2, iclass 25, count 0 2006.201.06:23:12.67#ibcon#*after write, iclass 25, count 0 2006.201.06:23:12.67#ibcon#*before return 0, iclass 25, count 0 2006.201.06:23:12.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:12.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:12.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.06:23:12.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.06:23:12.67$vck44/va=3,8 2006.201.06:23:12.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.06:23:12.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.06:23:12.67#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:12.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:12.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:12.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:12.72#ibcon#enter wrdev, iclass 27, count 2 2006.201.06:23:12.72#ibcon#first serial, iclass 27, count 2 2006.201.06:23:12.72#ibcon#enter sib2, iclass 27, count 2 2006.201.06:23:12.72#ibcon#flushed, iclass 27, count 2 2006.201.06:23:12.72#ibcon#about to write, iclass 27, count 2 2006.201.06:23:12.72#ibcon#wrote, iclass 27, count 2 2006.201.06:23:12.72#ibcon#about to read 3, iclass 27, count 2 2006.201.06:23:12.74#ibcon#read 3, iclass 27, count 2 2006.201.06:23:12.74#ibcon#about to read 4, iclass 27, count 2 2006.201.06:23:12.74#ibcon#read 4, iclass 27, count 2 2006.201.06:23:12.74#ibcon#about to read 5, iclass 27, count 2 2006.201.06:23:12.74#ibcon#read 5, iclass 27, count 2 2006.201.06:23:12.74#ibcon#about to read 6, iclass 27, count 2 2006.201.06:23:12.74#ibcon#read 6, iclass 27, count 2 2006.201.06:23:12.74#ibcon#end of sib2, iclass 27, count 2 2006.201.06:23:12.74#ibcon#*mode == 0, iclass 27, count 2 2006.201.06:23:12.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.06:23:12.74#ibcon#[25=AT03-08\r\n] 2006.201.06:23:12.74#ibcon#*before write, iclass 27, count 2 2006.201.06:23:12.74#ibcon#enter sib2, iclass 27, count 2 2006.201.06:23:12.74#ibcon#flushed, iclass 27, count 2 2006.201.06:23:12.74#ibcon#about to write, iclass 27, count 2 2006.201.06:23:12.74#ibcon#wrote, iclass 27, count 2 2006.201.06:23:12.74#ibcon#about to read 3, iclass 27, count 2 2006.201.06:23:12.77#ibcon#read 3, iclass 27, count 2 2006.201.06:23:12.77#ibcon#about to read 4, iclass 27, count 2 2006.201.06:23:12.77#ibcon#read 4, iclass 27, count 2 2006.201.06:23:12.77#ibcon#about to read 5, iclass 27, count 2 2006.201.06:23:12.77#ibcon#read 5, iclass 27, count 2 2006.201.06:23:12.77#ibcon#about to read 6, iclass 27, count 2 2006.201.06:23:12.77#ibcon#read 6, iclass 27, count 2 2006.201.06:23:12.77#ibcon#end of sib2, iclass 27, count 2 2006.201.06:23:12.77#ibcon#*after write, iclass 27, count 2 2006.201.06:23:12.77#ibcon#*before return 0, iclass 27, count 2 2006.201.06:23:12.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:12.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:12.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.06:23:12.77#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:12.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:12.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:12.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:12.89#ibcon#enter wrdev, iclass 27, count 0 2006.201.06:23:12.89#ibcon#first serial, iclass 27, count 0 2006.201.06:23:12.89#ibcon#enter sib2, iclass 27, count 0 2006.201.06:23:12.89#ibcon#flushed, iclass 27, count 0 2006.201.06:23:12.89#ibcon#about to write, iclass 27, count 0 2006.201.06:23:12.89#ibcon#wrote, iclass 27, count 0 2006.201.06:23:12.89#ibcon#about to read 3, iclass 27, count 0 2006.201.06:23:12.91#ibcon#read 3, iclass 27, count 0 2006.201.06:23:12.91#ibcon#about to read 4, iclass 27, count 0 2006.201.06:23:12.91#ibcon#read 4, iclass 27, count 0 2006.201.06:23:12.91#ibcon#about to read 5, iclass 27, count 0 2006.201.06:23:12.91#ibcon#read 5, iclass 27, count 0 2006.201.06:23:12.91#ibcon#about to read 6, iclass 27, count 0 2006.201.06:23:12.91#ibcon#read 6, iclass 27, count 0 2006.201.06:23:12.91#ibcon#end of sib2, iclass 27, count 0 2006.201.06:23:12.91#ibcon#*mode == 0, iclass 27, count 0 2006.201.06:23:12.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.06:23:12.91#ibcon#[25=USB\r\n] 2006.201.06:23:12.91#ibcon#*before write, iclass 27, count 0 2006.201.06:23:12.91#ibcon#enter sib2, iclass 27, count 0 2006.201.06:23:12.91#ibcon#flushed, iclass 27, count 0 2006.201.06:23:12.91#ibcon#about to write, iclass 27, count 0 2006.201.06:23:12.91#ibcon#wrote, iclass 27, count 0 2006.201.06:23:12.91#ibcon#about to read 3, iclass 27, count 0 2006.201.06:23:12.94#ibcon#read 3, iclass 27, count 0 2006.201.06:23:12.94#ibcon#about to read 4, iclass 27, count 0 2006.201.06:23:12.94#ibcon#read 4, iclass 27, count 0 2006.201.06:23:12.94#ibcon#about to read 5, iclass 27, count 0 2006.201.06:23:12.94#ibcon#read 5, iclass 27, count 0 2006.201.06:23:12.94#ibcon#about to read 6, iclass 27, count 0 2006.201.06:23:12.94#ibcon#read 6, iclass 27, count 0 2006.201.06:23:12.94#ibcon#end of sib2, iclass 27, count 0 2006.201.06:23:12.94#ibcon#*after write, iclass 27, count 0 2006.201.06:23:12.94#ibcon#*before return 0, iclass 27, count 0 2006.201.06:23:12.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:12.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:12.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.06:23:12.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.06:23:12.94$vck44/valo=4,624.99 2006.201.06:23:12.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.06:23:12.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.06:23:12.94#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:12.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:12.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:12.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:12.94#ibcon#enter wrdev, iclass 29, count 0 2006.201.06:23:12.94#ibcon#first serial, iclass 29, count 0 2006.201.06:23:12.94#ibcon#enter sib2, iclass 29, count 0 2006.201.06:23:12.94#ibcon#flushed, iclass 29, count 0 2006.201.06:23:12.94#ibcon#about to write, iclass 29, count 0 2006.201.06:23:12.94#ibcon#wrote, iclass 29, count 0 2006.201.06:23:12.94#ibcon#about to read 3, iclass 29, count 0 2006.201.06:23:12.96#ibcon#read 3, iclass 29, count 0 2006.201.06:23:12.96#ibcon#about to read 4, iclass 29, count 0 2006.201.06:23:12.96#ibcon#read 4, iclass 29, count 0 2006.201.06:23:12.96#ibcon#about to read 5, iclass 29, count 0 2006.201.06:23:12.96#ibcon#read 5, iclass 29, count 0 2006.201.06:23:12.96#ibcon#about to read 6, iclass 29, count 0 2006.201.06:23:12.96#ibcon#read 6, iclass 29, count 0 2006.201.06:23:12.96#ibcon#end of sib2, iclass 29, count 0 2006.201.06:23:12.96#ibcon#*mode == 0, iclass 29, count 0 2006.201.06:23:12.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.06:23:12.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.06:23:12.96#ibcon#*before write, iclass 29, count 0 2006.201.06:23:12.96#ibcon#enter sib2, iclass 29, count 0 2006.201.06:23:12.96#ibcon#flushed, iclass 29, count 0 2006.201.06:23:12.96#ibcon#about to write, iclass 29, count 0 2006.201.06:23:12.96#ibcon#wrote, iclass 29, count 0 2006.201.06:23:12.96#ibcon#about to read 3, iclass 29, count 0 2006.201.06:23:13.01#ibcon#read 3, iclass 29, count 0 2006.201.06:23:13.01#ibcon#about to read 4, iclass 29, count 0 2006.201.06:23:13.01#ibcon#read 4, iclass 29, count 0 2006.201.06:23:13.01#ibcon#about to read 5, iclass 29, count 0 2006.201.06:23:13.01#ibcon#read 5, iclass 29, count 0 2006.201.06:23:13.01#ibcon#about to read 6, iclass 29, count 0 2006.201.06:23:13.01#ibcon#read 6, iclass 29, count 0 2006.201.06:23:13.01#ibcon#end of sib2, iclass 29, count 0 2006.201.06:23:13.01#ibcon#*after write, iclass 29, count 0 2006.201.06:23:13.01#ibcon#*before return 0, iclass 29, count 0 2006.201.06:23:13.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:13.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:13.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.06:23:13.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.06:23:13.01$vck44/va=4,7 2006.201.06:23:13.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.06:23:13.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.06:23:13.01#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:13.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:13.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:13.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:13.06#ibcon#enter wrdev, iclass 31, count 2 2006.201.06:23:13.06#ibcon#first serial, iclass 31, count 2 2006.201.06:23:13.06#ibcon#enter sib2, iclass 31, count 2 2006.201.06:23:13.06#ibcon#flushed, iclass 31, count 2 2006.201.06:23:13.06#ibcon#about to write, iclass 31, count 2 2006.201.06:23:13.06#ibcon#wrote, iclass 31, count 2 2006.201.06:23:13.06#ibcon#about to read 3, iclass 31, count 2 2006.201.06:23:13.08#ibcon#read 3, iclass 31, count 2 2006.201.06:23:13.08#ibcon#about to read 4, iclass 31, count 2 2006.201.06:23:13.08#ibcon#read 4, iclass 31, count 2 2006.201.06:23:13.08#ibcon#about to read 5, iclass 31, count 2 2006.201.06:23:13.08#ibcon#read 5, iclass 31, count 2 2006.201.06:23:13.08#ibcon#about to read 6, iclass 31, count 2 2006.201.06:23:13.08#ibcon#read 6, iclass 31, count 2 2006.201.06:23:13.08#ibcon#end of sib2, iclass 31, count 2 2006.201.06:23:13.08#ibcon#*mode == 0, iclass 31, count 2 2006.201.06:23:13.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.06:23:13.08#ibcon#[25=AT04-07\r\n] 2006.201.06:23:13.08#ibcon#*before write, iclass 31, count 2 2006.201.06:23:13.08#ibcon#enter sib2, iclass 31, count 2 2006.201.06:23:13.08#ibcon#flushed, iclass 31, count 2 2006.201.06:23:13.08#ibcon#about to write, iclass 31, count 2 2006.201.06:23:13.08#ibcon#wrote, iclass 31, count 2 2006.201.06:23:13.08#ibcon#about to read 3, iclass 31, count 2 2006.201.06:23:13.11#ibcon#read 3, iclass 31, count 2 2006.201.06:23:13.11#ibcon#about to read 4, iclass 31, count 2 2006.201.06:23:13.11#ibcon#read 4, iclass 31, count 2 2006.201.06:23:13.11#ibcon#about to read 5, iclass 31, count 2 2006.201.06:23:13.11#ibcon#read 5, iclass 31, count 2 2006.201.06:23:13.11#ibcon#about to read 6, iclass 31, count 2 2006.201.06:23:13.11#ibcon#read 6, iclass 31, count 2 2006.201.06:23:13.11#ibcon#end of sib2, iclass 31, count 2 2006.201.06:23:13.11#ibcon#*after write, iclass 31, count 2 2006.201.06:23:13.11#ibcon#*before return 0, iclass 31, count 2 2006.201.06:23:13.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:13.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:13.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.06:23:13.11#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:13.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:13.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:13.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:13.23#ibcon#enter wrdev, iclass 31, count 0 2006.201.06:23:13.23#ibcon#first serial, iclass 31, count 0 2006.201.06:23:13.23#ibcon#enter sib2, iclass 31, count 0 2006.201.06:23:13.23#ibcon#flushed, iclass 31, count 0 2006.201.06:23:13.23#ibcon#about to write, iclass 31, count 0 2006.201.06:23:13.23#ibcon#wrote, iclass 31, count 0 2006.201.06:23:13.23#ibcon#about to read 3, iclass 31, count 0 2006.201.06:23:13.25#ibcon#read 3, iclass 31, count 0 2006.201.06:23:13.25#ibcon#about to read 4, iclass 31, count 0 2006.201.06:23:13.25#ibcon#read 4, iclass 31, count 0 2006.201.06:23:13.25#ibcon#about to read 5, iclass 31, count 0 2006.201.06:23:13.25#ibcon#read 5, iclass 31, count 0 2006.201.06:23:13.25#ibcon#about to read 6, iclass 31, count 0 2006.201.06:23:13.25#ibcon#read 6, iclass 31, count 0 2006.201.06:23:13.25#ibcon#end of sib2, iclass 31, count 0 2006.201.06:23:13.25#ibcon#*mode == 0, iclass 31, count 0 2006.201.06:23:13.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.06:23:13.25#ibcon#[25=USB\r\n] 2006.201.06:23:13.25#ibcon#*before write, iclass 31, count 0 2006.201.06:23:13.25#ibcon#enter sib2, iclass 31, count 0 2006.201.06:23:13.25#ibcon#flushed, iclass 31, count 0 2006.201.06:23:13.25#ibcon#about to write, iclass 31, count 0 2006.201.06:23:13.25#ibcon#wrote, iclass 31, count 0 2006.201.06:23:13.25#ibcon#about to read 3, iclass 31, count 0 2006.201.06:23:13.28#ibcon#read 3, iclass 31, count 0 2006.201.06:23:13.28#ibcon#about to read 4, iclass 31, count 0 2006.201.06:23:13.28#ibcon#read 4, iclass 31, count 0 2006.201.06:23:13.28#ibcon#about to read 5, iclass 31, count 0 2006.201.06:23:13.28#ibcon#read 5, iclass 31, count 0 2006.201.06:23:13.28#ibcon#about to read 6, iclass 31, count 0 2006.201.06:23:13.28#ibcon#read 6, iclass 31, count 0 2006.201.06:23:13.28#ibcon#end of sib2, iclass 31, count 0 2006.201.06:23:13.28#ibcon#*after write, iclass 31, count 0 2006.201.06:23:13.28#ibcon#*before return 0, iclass 31, count 0 2006.201.06:23:13.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:13.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:13.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.06:23:13.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.06:23:13.28$vck44/valo=5,734.99 2006.201.06:23:13.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.06:23:13.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.06:23:13.28#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:13.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:13.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:13.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:13.28#ibcon#enter wrdev, iclass 33, count 0 2006.201.06:23:13.28#ibcon#first serial, iclass 33, count 0 2006.201.06:23:13.28#ibcon#enter sib2, iclass 33, count 0 2006.201.06:23:13.28#ibcon#flushed, iclass 33, count 0 2006.201.06:23:13.28#ibcon#about to write, iclass 33, count 0 2006.201.06:23:13.28#ibcon#wrote, iclass 33, count 0 2006.201.06:23:13.28#ibcon#about to read 3, iclass 33, count 0 2006.201.06:23:13.30#ibcon#read 3, iclass 33, count 0 2006.201.06:23:13.30#ibcon#about to read 4, iclass 33, count 0 2006.201.06:23:13.30#ibcon#read 4, iclass 33, count 0 2006.201.06:23:13.30#ibcon#about to read 5, iclass 33, count 0 2006.201.06:23:13.30#ibcon#read 5, iclass 33, count 0 2006.201.06:23:13.30#ibcon#about to read 6, iclass 33, count 0 2006.201.06:23:13.30#ibcon#read 6, iclass 33, count 0 2006.201.06:23:13.30#ibcon#end of sib2, iclass 33, count 0 2006.201.06:23:13.30#ibcon#*mode == 0, iclass 33, count 0 2006.201.06:23:13.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.06:23:13.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.06:23:13.30#ibcon#*before write, iclass 33, count 0 2006.201.06:23:13.30#ibcon#enter sib2, iclass 33, count 0 2006.201.06:23:13.30#ibcon#flushed, iclass 33, count 0 2006.201.06:23:13.30#ibcon#about to write, iclass 33, count 0 2006.201.06:23:13.30#ibcon#wrote, iclass 33, count 0 2006.201.06:23:13.30#ibcon#about to read 3, iclass 33, count 0 2006.201.06:23:13.34#ibcon#read 3, iclass 33, count 0 2006.201.06:23:13.34#ibcon#about to read 4, iclass 33, count 0 2006.201.06:23:13.34#ibcon#read 4, iclass 33, count 0 2006.201.06:23:13.34#ibcon#about to read 5, iclass 33, count 0 2006.201.06:23:13.34#ibcon#read 5, iclass 33, count 0 2006.201.06:23:13.34#ibcon#about to read 6, iclass 33, count 0 2006.201.06:23:13.34#ibcon#read 6, iclass 33, count 0 2006.201.06:23:13.34#ibcon#end of sib2, iclass 33, count 0 2006.201.06:23:13.34#ibcon#*after write, iclass 33, count 0 2006.201.06:23:13.34#ibcon#*before return 0, iclass 33, count 0 2006.201.06:23:13.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:13.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:13.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.06:23:13.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.06:23:13.34$vck44/va=5,4 2006.201.06:23:13.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.06:23:13.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.06:23:13.34#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:13.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:13.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:13.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:13.40#ibcon#enter wrdev, iclass 35, count 2 2006.201.06:23:13.40#ibcon#first serial, iclass 35, count 2 2006.201.06:23:13.40#ibcon#enter sib2, iclass 35, count 2 2006.201.06:23:13.40#ibcon#flushed, iclass 35, count 2 2006.201.06:23:13.40#ibcon#about to write, iclass 35, count 2 2006.201.06:23:13.40#ibcon#wrote, iclass 35, count 2 2006.201.06:23:13.40#ibcon#about to read 3, iclass 35, count 2 2006.201.06:23:13.42#ibcon#read 3, iclass 35, count 2 2006.201.06:23:13.42#ibcon#about to read 4, iclass 35, count 2 2006.201.06:23:13.42#ibcon#read 4, iclass 35, count 2 2006.201.06:23:13.42#ibcon#about to read 5, iclass 35, count 2 2006.201.06:23:13.42#ibcon#read 5, iclass 35, count 2 2006.201.06:23:13.42#ibcon#about to read 6, iclass 35, count 2 2006.201.06:23:13.42#ibcon#read 6, iclass 35, count 2 2006.201.06:23:13.42#ibcon#end of sib2, iclass 35, count 2 2006.201.06:23:13.42#ibcon#*mode == 0, iclass 35, count 2 2006.201.06:23:13.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.06:23:13.42#ibcon#[25=AT05-04\r\n] 2006.201.06:23:13.42#ibcon#*before write, iclass 35, count 2 2006.201.06:23:13.42#ibcon#enter sib2, iclass 35, count 2 2006.201.06:23:13.42#ibcon#flushed, iclass 35, count 2 2006.201.06:23:13.42#ibcon#about to write, iclass 35, count 2 2006.201.06:23:13.42#ibcon#wrote, iclass 35, count 2 2006.201.06:23:13.42#ibcon#about to read 3, iclass 35, count 2 2006.201.06:23:13.45#ibcon#read 3, iclass 35, count 2 2006.201.06:23:13.45#ibcon#about to read 4, iclass 35, count 2 2006.201.06:23:13.45#ibcon#read 4, iclass 35, count 2 2006.201.06:23:13.45#ibcon#about to read 5, iclass 35, count 2 2006.201.06:23:13.45#ibcon#read 5, iclass 35, count 2 2006.201.06:23:13.45#ibcon#about to read 6, iclass 35, count 2 2006.201.06:23:13.45#ibcon#read 6, iclass 35, count 2 2006.201.06:23:13.45#ibcon#end of sib2, iclass 35, count 2 2006.201.06:23:13.45#ibcon#*after write, iclass 35, count 2 2006.201.06:23:13.45#ibcon#*before return 0, iclass 35, count 2 2006.201.06:23:13.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:13.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:13.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.06:23:13.45#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:13.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:13.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:13.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:13.57#ibcon#enter wrdev, iclass 35, count 0 2006.201.06:23:13.57#ibcon#first serial, iclass 35, count 0 2006.201.06:23:13.57#ibcon#enter sib2, iclass 35, count 0 2006.201.06:23:13.57#ibcon#flushed, iclass 35, count 0 2006.201.06:23:13.57#ibcon#about to write, iclass 35, count 0 2006.201.06:23:13.57#ibcon#wrote, iclass 35, count 0 2006.201.06:23:13.57#ibcon#about to read 3, iclass 35, count 0 2006.201.06:23:13.59#ibcon#read 3, iclass 35, count 0 2006.201.06:23:13.59#ibcon#about to read 4, iclass 35, count 0 2006.201.06:23:13.59#ibcon#read 4, iclass 35, count 0 2006.201.06:23:13.59#ibcon#about to read 5, iclass 35, count 0 2006.201.06:23:13.59#ibcon#read 5, iclass 35, count 0 2006.201.06:23:13.59#ibcon#about to read 6, iclass 35, count 0 2006.201.06:23:13.59#ibcon#read 6, iclass 35, count 0 2006.201.06:23:13.59#ibcon#end of sib2, iclass 35, count 0 2006.201.06:23:13.59#ibcon#*mode == 0, iclass 35, count 0 2006.201.06:23:13.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.06:23:13.59#ibcon#[25=USB\r\n] 2006.201.06:23:13.59#ibcon#*before write, iclass 35, count 0 2006.201.06:23:13.59#ibcon#enter sib2, iclass 35, count 0 2006.201.06:23:13.59#ibcon#flushed, iclass 35, count 0 2006.201.06:23:13.59#ibcon#about to write, iclass 35, count 0 2006.201.06:23:13.59#ibcon#wrote, iclass 35, count 0 2006.201.06:23:13.59#ibcon#about to read 3, iclass 35, count 0 2006.201.06:23:13.62#ibcon#read 3, iclass 35, count 0 2006.201.06:23:13.62#ibcon#about to read 4, iclass 35, count 0 2006.201.06:23:13.62#ibcon#read 4, iclass 35, count 0 2006.201.06:23:13.62#ibcon#about to read 5, iclass 35, count 0 2006.201.06:23:13.62#ibcon#read 5, iclass 35, count 0 2006.201.06:23:13.62#ibcon#about to read 6, iclass 35, count 0 2006.201.06:23:13.62#ibcon#read 6, iclass 35, count 0 2006.201.06:23:13.62#ibcon#end of sib2, iclass 35, count 0 2006.201.06:23:13.62#ibcon#*after write, iclass 35, count 0 2006.201.06:23:13.62#ibcon#*before return 0, iclass 35, count 0 2006.201.06:23:13.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:13.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:13.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.06:23:13.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.06:23:13.62$vck44/valo=6,814.99 2006.201.06:23:13.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.06:23:13.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.06:23:13.62#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:13.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:13.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:13.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:13.62#ibcon#enter wrdev, iclass 37, count 0 2006.201.06:23:13.62#ibcon#first serial, iclass 37, count 0 2006.201.06:23:13.62#ibcon#enter sib2, iclass 37, count 0 2006.201.06:23:13.62#ibcon#flushed, iclass 37, count 0 2006.201.06:23:13.62#ibcon#about to write, iclass 37, count 0 2006.201.06:23:13.62#ibcon#wrote, iclass 37, count 0 2006.201.06:23:13.62#ibcon#about to read 3, iclass 37, count 0 2006.201.06:23:13.64#ibcon#read 3, iclass 37, count 0 2006.201.06:23:13.64#ibcon#about to read 4, iclass 37, count 0 2006.201.06:23:13.64#ibcon#read 4, iclass 37, count 0 2006.201.06:23:13.64#ibcon#about to read 5, iclass 37, count 0 2006.201.06:23:13.64#ibcon#read 5, iclass 37, count 0 2006.201.06:23:13.64#ibcon#about to read 6, iclass 37, count 0 2006.201.06:23:13.64#ibcon#read 6, iclass 37, count 0 2006.201.06:23:13.64#ibcon#end of sib2, iclass 37, count 0 2006.201.06:23:13.64#ibcon#*mode == 0, iclass 37, count 0 2006.201.06:23:13.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.06:23:13.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.06:23:13.64#ibcon#*before write, iclass 37, count 0 2006.201.06:23:13.64#ibcon#enter sib2, iclass 37, count 0 2006.201.06:23:13.64#ibcon#flushed, iclass 37, count 0 2006.201.06:23:13.64#ibcon#about to write, iclass 37, count 0 2006.201.06:23:13.64#ibcon#wrote, iclass 37, count 0 2006.201.06:23:13.64#ibcon#about to read 3, iclass 37, count 0 2006.201.06:23:13.68#ibcon#read 3, iclass 37, count 0 2006.201.06:23:13.68#ibcon#about to read 4, iclass 37, count 0 2006.201.06:23:13.68#ibcon#read 4, iclass 37, count 0 2006.201.06:23:13.68#ibcon#about to read 5, iclass 37, count 0 2006.201.06:23:13.68#ibcon#read 5, iclass 37, count 0 2006.201.06:23:13.68#ibcon#about to read 6, iclass 37, count 0 2006.201.06:23:13.68#ibcon#read 6, iclass 37, count 0 2006.201.06:23:13.68#ibcon#end of sib2, iclass 37, count 0 2006.201.06:23:13.68#ibcon#*after write, iclass 37, count 0 2006.201.06:23:13.68#ibcon#*before return 0, iclass 37, count 0 2006.201.06:23:13.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:13.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:13.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.06:23:13.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.06:23:13.68$vck44/va=6,5 2006.201.06:23:13.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.06:23:13.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.06:23:13.68#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:13.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:13.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:13.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:13.74#ibcon#enter wrdev, iclass 39, count 2 2006.201.06:23:13.74#ibcon#first serial, iclass 39, count 2 2006.201.06:23:13.74#ibcon#enter sib2, iclass 39, count 2 2006.201.06:23:13.74#ibcon#flushed, iclass 39, count 2 2006.201.06:23:13.74#ibcon#about to write, iclass 39, count 2 2006.201.06:23:13.74#ibcon#wrote, iclass 39, count 2 2006.201.06:23:13.74#ibcon#about to read 3, iclass 39, count 2 2006.201.06:23:13.76#ibcon#read 3, iclass 39, count 2 2006.201.06:23:13.76#ibcon#about to read 4, iclass 39, count 2 2006.201.06:23:13.76#ibcon#read 4, iclass 39, count 2 2006.201.06:23:13.76#ibcon#about to read 5, iclass 39, count 2 2006.201.06:23:13.76#ibcon#read 5, iclass 39, count 2 2006.201.06:23:13.76#ibcon#about to read 6, iclass 39, count 2 2006.201.06:23:13.76#ibcon#read 6, iclass 39, count 2 2006.201.06:23:13.76#ibcon#end of sib2, iclass 39, count 2 2006.201.06:23:13.76#ibcon#*mode == 0, iclass 39, count 2 2006.201.06:23:13.76#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.06:23:13.76#ibcon#[25=AT06-05\r\n] 2006.201.06:23:13.76#ibcon#*before write, iclass 39, count 2 2006.201.06:23:13.76#ibcon#enter sib2, iclass 39, count 2 2006.201.06:23:13.76#ibcon#flushed, iclass 39, count 2 2006.201.06:23:13.76#ibcon#about to write, iclass 39, count 2 2006.201.06:23:13.76#ibcon#wrote, iclass 39, count 2 2006.201.06:23:13.76#ibcon#about to read 3, iclass 39, count 2 2006.201.06:23:13.79#ibcon#read 3, iclass 39, count 2 2006.201.06:23:13.79#ibcon#about to read 4, iclass 39, count 2 2006.201.06:23:13.79#ibcon#read 4, iclass 39, count 2 2006.201.06:23:13.79#ibcon#about to read 5, iclass 39, count 2 2006.201.06:23:13.79#ibcon#read 5, iclass 39, count 2 2006.201.06:23:13.79#ibcon#about to read 6, iclass 39, count 2 2006.201.06:23:13.79#ibcon#read 6, iclass 39, count 2 2006.201.06:23:13.79#ibcon#end of sib2, iclass 39, count 2 2006.201.06:23:13.79#ibcon#*after write, iclass 39, count 2 2006.201.06:23:13.79#ibcon#*before return 0, iclass 39, count 2 2006.201.06:23:13.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:13.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:13.79#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.06:23:13.79#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:13.79#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:13.91#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:13.91#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:13.91#ibcon#enter wrdev, iclass 39, count 0 2006.201.06:23:13.91#ibcon#first serial, iclass 39, count 0 2006.201.06:23:13.91#ibcon#enter sib2, iclass 39, count 0 2006.201.06:23:13.91#ibcon#flushed, iclass 39, count 0 2006.201.06:23:13.91#ibcon#about to write, iclass 39, count 0 2006.201.06:23:13.91#ibcon#wrote, iclass 39, count 0 2006.201.06:23:13.91#ibcon#about to read 3, iclass 39, count 0 2006.201.06:23:13.93#ibcon#read 3, iclass 39, count 0 2006.201.06:23:13.93#ibcon#about to read 4, iclass 39, count 0 2006.201.06:23:13.93#ibcon#read 4, iclass 39, count 0 2006.201.06:23:13.93#ibcon#about to read 5, iclass 39, count 0 2006.201.06:23:13.93#ibcon#read 5, iclass 39, count 0 2006.201.06:23:13.93#ibcon#about to read 6, iclass 39, count 0 2006.201.06:23:13.93#ibcon#read 6, iclass 39, count 0 2006.201.06:23:13.93#ibcon#end of sib2, iclass 39, count 0 2006.201.06:23:13.93#ibcon#*mode == 0, iclass 39, count 0 2006.201.06:23:13.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.06:23:13.93#ibcon#[25=USB\r\n] 2006.201.06:23:13.93#ibcon#*before write, iclass 39, count 0 2006.201.06:23:13.93#ibcon#enter sib2, iclass 39, count 0 2006.201.06:23:13.93#ibcon#flushed, iclass 39, count 0 2006.201.06:23:13.93#ibcon#about to write, iclass 39, count 0 2006.201.06:23:13.93#ibcon#wrote, iclass 39, count 0 2006.201.06:23:13.93#ibcon#about to read 3, iclass 39, count 0 2006.201.06:23:13.96#ibcon#read 3, iclass 39, count 0 2006.201.06:23:13.96#ibcon#about to read 4, iclass 39, count 0 2006.201.06:23:13.96#ibcon#read 4, iclass 39, count 0 2006.201.06:23:13.96#ibcon#about to read 5, iclass 39, count 0 2006.201.06:23:13.96#ibcon#read 5, iclass 39, count 0 2006.201.06:23:13.96#ibcon#about to read 6, iclass 39, count 0 2006.201.06:23:13.96#ibcon#read 6, iclass 39, count 0 2006.201.06:23:13.96#ibcon#end of sib2, iclass 39, count 0 2006.201.06:23:13.96#ibcon#*after write, iclass 39, count 0 2006.201.06:23:13.96#ibcon#*before return 0, iclass 39, count 0 2006.201.06:23:13.96#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:13.96#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:13.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.06:23:13.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.06:23:13.96$vck44/valo=7,864.99 2006.201.06:23:13.96#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.06:23:13.96#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.06:23:13.96#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:13.96#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:13.96#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:13.96#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:13.96#ibcon#enter wrdev, iclass 2, count 0 2006.201.06:23:13.96#ibcon#first serial, iclass 2, count 0 2006.201.06:23:13.96#ibcon#enter sib2, iclass 2, count 0 2006.201.06:23:13.96#ibcon#flushed, iclass 2, count 0 2006.201.06:23:13.96#ibcon#about to write, iclass 2, count 0 2006.201.06:23:13.96#ibcon#wrote, iclass 2, count 0 2006.201.06:23:13.96#ibcon#about to read 3, iclass 2, count 0 2006.201.06:23:13.98#ibcon#read 3, iclass 2, count 0 2006.201.06:23:13.98#ibcon#about to read 4, iclass 2, count 0 2006.201.06:23:13.98#ibcon#read 4, iclass 2, count 0 2006.201.06:23:13.98#ibcon#about to read 5, iclass 2, count 0 2006.201.06:23:13.98#ibcon#read 5, iclass 2, count 0 2006.201.06:23:13.98#ibcon#about to read 6, iclass 2, count 0 2006.201.06:23:13.98#ibcon#read 6, iclass 2, count 0 2006.201.06:23:13.98#ibcon#end of sib2, iclass 2, count 0 2006.201.06:23:13.98#ibcon#*mode == 0, iclass 2, count 0 2006.201.06:23:13.98#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.06:23:13.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.06:23:13.98#ibcon#*before write, iclass 2, count 0 2006.201.06:23:13.98#ibcon#enter sib2, iclass 2, count 0 2006.201.06:23:13.98#ibcon#flushed, iclass 2, count 0 2006.201.06:23:13.98#ibcon#about to write, iclass 2, count 0 2006.201.06:23:13.98#ibcon#wrote, iclass 2, count 0 2006.201.06:23:13.98#ibcon#about to read 3, iclass 2, count 0 2006.201.06:23:14.02#ibcon#read 3, iclass 2, count 0 2006.201.06:23:14.02#ibcon#about to read 4, iclass 2, count 0 2006.201.06:23:14.02#ibcon#read 4, iclass 2, count 0 2006.201.06:23:14.02#ibcon#about to read 5, iclass 2, count 0 2006.201.06:23:14.02#ibcon#read 5, iclass 2, count 0 2006.201.06:23:14.02#ibcon#about to read 6, iclass 2, count 0 2006.201.06:23:14.02#ibcon#read 6, iclass 2, count 0 2006.201.06:23:14.02#ibcon#end of sib2, iclass 2, count 0 2006.201.06:23:14.02#ibcon#*after write, iclass 2, count 0 2006.201.06:23:14.02#ibcon#*before return 0, iclass 2, count 0 2006.201.06:23:14.02#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:14.02#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:14.02#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.06:23:14.02#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.06:23:14.02$vck44/va=7,5 2006.201.06:23:14.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.06:23:14.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.06:23:14.02#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:14.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:14.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:14.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:14.08#ibcon#enter wrdev, iclass 5, count 2 2006.201.06:23:14.08#ibcon#first serial, iclass 5, count 2 2006.201.06:23:14.08#ibcon#enter sib2, iclass 5, count 2 2006.201.06:23:14.08#ibcon#flushed, iclass 5, count 2 2006.201.06:23:14.08#ibcon#about to write, iclass 5, count 2 2006.201.06:23:14.08#ibcon#wrote, iclass 5, count 2 2006.201.06:23:14.08#ibcon#about to read 3, iclass 5, count 2 2006.201.06:23:14.10#ibcon#read 3, iclass 5, count 2 2006.201.06:23:14.10#ibcon#about to read 4, iclass 5, count 2 2006.201.06:23:14.10#ibcon#read 4, iclass 5, count 2 2006.201.06:23:14.10#ibcon#about to read 5, iclass 5, count 2 2006.201.06:23:14.10#ibcon#read 5, iclass 5, count 2 2006.201.06:23:14.10#ibcon#about to read 6, iclass 5, count 2 2006.201.06:23:14.10#ibcon#read 6, iclass 5, count 2 2006.201.06:23:14.10#ibcon#end of sib2, iclass 5, count 2 2006.201.06:23:14.10#ibcon#*mode == 0, iclass 5, count 2 2006.201.06:23:14.10#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.06:23:14.10#ibcon#[25=AT07-05\r\n] 2006.201.06:23:14.10#ibcon#*before write, iclass 5, count 2 2006.201.06:23:14.10#ibcon#enter sib2, iclass 5, count 2 2006.201.06:23:14.10#ibcon#flushed, iclass 5, count 2 2006.201.06:23:14.10#ibcon#about to write, iclass 5, count 2 2006.201.06:23:14.10#ibcon#wrote, iclass 5, count 2 2006.201.06:23:14.10#ibcon#about to read 3, iclass 5, count 2 2006.201.06:23:14.13#ibcon#read 3, iclass 5, count 2 2006.201.06:23:14.13#ibcon#about to read 4, iclass 5, count 2 2006.201.06:23:14.13#ibcon#read 4, iclass 5, count 2 2006.201.06:23:14.13#ibcon#about to read 5, iclass 5, count 2 2006.201.06:23:14.13#ibcon#read 5, iclass 5, count 2 2006.201.06:23:14.13#ibcon#about to read 6, iclass 5, count 2 2006.201.06:23:14.13#ibcon#read 6, iclass 5, count 2 2006.201.06:23:14.13#ibcon#end of sib2, iclass 5, count 2 2006.201.06:23:14.13#ibcon#*after write, iclass 5, count 2 2006.201.06:23:14.13#ibcon#*before return 0, iclass 5, count 2 2006.201.06:23:14.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:14.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:14.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.06:23:14.13#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:14.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:14.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:14.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:14.25#ibcon#enter wrdev, iclass 5, count 0 2006.201.06:23:14.25#ibcon#first serial, iclass 5, count 0 2006.201.06:23:14.25#ibcon#enter sib2, iclass 5, count 0 2006.201.06:23:14.25#ibcon#flushed, iclass 5, count 0 2006.201.06:23:14.25#ibcon#about to write, iclass 5, count 0 2006.201.06:23:14.25#ibcon#wrote, iclass 5, count 0 2006.201.06:23:14.25#ibcon#about to read 3, iclass 5, count 0 2006.201.06:23:14.27#ibcon#read 3, iclass 5, count 0 2006.201.06:23:14.27#ibcon#about to read 4, iclass 5, count 0 2006.201.06:23:14.27#ibcon#read 4, iclass 5, count 0 2006.201.06:23:14.27#ibcon#about to read 5, iclass 5, count 0 2006.201.06:23:14.27#ibcon#read 5, iclass 5, count 0 2006.201.06:23:14.27#ibcon#about to read 6, iclass 5, count 0 2006.201.06:23:14.27#ibcon#read 6, iclass 5, count 0 2006.201.06:23:14.27#ibcon#end of sib2, iclass 5, count 0 2006.201.06:23:14.27#ibcon#*mode == 0, iclass 5, count 0 2006.201.06:23:14.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.06:23:14.27#ibcon#[25=USB\r\n] 2006.201.06:23:14.27#ibcon#*before write, iclass 5, count 0 2006.201.06:23:14.27#ibcon#enter sib2, iclass 5, count 0 2006.201.06:23:14.27#ibcon#flushed, iclass 5, count 0 2006.201.06:23:14.27#ibcon#about to write, iclass 5, count 0 2006.201.06:23:14.27#ibcon#wrote, iclass 5, count 0 2006.201.06:23:14.27#ibcon#about to read 3, iclass 5, count 0 2006.201.06:23:14.30#ibcon#read 3, iclass 5, count 0 2006.201.06:23:14.30#ibcon#about to read 4, iclass 5, count 0 2006.201.06:23:14.30#ibcon#read 4, iclass 5, count 0 2006.201.06:23:14.30#ibcon#about to read 5, iclass 5, count 0 2006.201.06:23:14.30#ibcon#read 5, iclass 5, count 0 2006.201.06:23:14.30#ibcon#about to read 6, iclass 5, count 0 2006.201.06:23:14.30#ibcon#read 6, iclass 5, count 0 2006.201.06:23:14.30#ibcon#end of sib2, iclass 5, count 0 2006.201.06:23:14.30#ibcon#*after write, iclass 5, count 0 2006.201.06:23:14.30#ibcon#*before return 0, iclass 5, count 0 2006.201.06:23:14.30#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:14.30#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:14.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.06:23:14.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.06:23:14.30$vck44/valo=8,884.99 2006.201.06:23:14.30#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.06:23:14.30#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.06:23:14.30#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:14.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:14.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:14.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:14.30#ibcon#enter wrdev, iclass 7, count 0 2006.201.06:23:14.30#ibcon#first serial, iclass 7, count 0 2006.201.06:23:14.30#ibcon#enter sib2, iclass 7, count 0 2006.201.06:23:14.30#ibcon#flushed, iclass 7, count 0 2006.201.06:23:14.30#ibcon#about to write, iclass 7, count 0 2006.201.06:23:14.30#ibcon#wrote, iclass 7, count 0 2006.201.06:23:14.30#ibcon#about to read 3, iclass 7, count 0 2006.201.06:23:14.32#ibcon#read 3, iclass 7, count 0 2006.201.06:23:14.32#ibcon#about to read 4, iclass 7, count 0 2006.201.06:23:14.32#ibcon#read 4, iclass 7, count 0 2006.201.06:23:14.32#ibcon#about to read 5, iclass 7, count 0 2006.201.06:23:14.32#ibcon#read 5, iclass 7, count 0 2006.201.06:23:14.32#ibcon#about to read 6, iclass 7, count 0 2006.201.06:23:14.32#ibcon#read 6, iclass 7, count 0 2006.201.06:23:14.32#ibcon#end of sib2, iclass 7, count 0 2006.201.06:23:14.32#ibcon#*mode == 0, iclass 7, count 0 2006.201.06:23:14.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.06:23:14.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.06:23:14.32#ibcon#*before write, iclass 7, count 0 2006.201.06:23:14.32#ibcon#enter sib2, iclass 7, count 0 2006.201.06:23:14.32#ibcon#flushed, iclass 7, count 0 2006.201.06:23:14.32#ibcon#about to write, iclass 7, count 0 2006.201.06:23:14.32#ibcon#wrote, iclass 7, count 0 2006.201.06:23:14.32#ibcon#about to read 3, iclass 7, count 0 2006.201.06:23:14.36#ibcon#read 3, iclass 7, count 0 2006.201.06:23:14.36#ibcon#about to read 4, iclass 7, count 0 2006.201.06:23:14.36#ibcon#read 4, iclass 7, count 0 2006.201.06:23:14.36#ibcon#about to read 5, iclass 7, count 0 2006.201.06:23:14.36#ibcon#read 5, iclass 7, count 0 2006.201.06:23:14.36#ibcon#about to read 6, iclass 7, count 0 2006.201.06:23:14.36#ibcon#read 6, iclass 7, count 0 2006.201.06:23:14.36#ibcon#end of sib2, iclass 7, count 0 2006.201.06:23:14.36#ibcon#*after write, iclass 7, count 0 2006.201.06:23:14.36#ibcon#*before return 0, iclass 7, count 0 2006.201.06:23:14.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:14.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:14.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.06:23:14.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.06:23:14.36$vck44/va=8,4 2006.201.06:23:14.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.06:23:14.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.06:23:14.36#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:14.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:23:14.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:23:14.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:23:14.42#ibcon#enter wrdev, iclass 11, count 2 2006.201.06:23:14.42#ibcon#first serial, iclass 11, count 2 2006.201.06:23:14.42#ibcon#enter sib2, iclass 11, count 2 2006.201.06:23:14.42#ibcon#flushed, iclass 11, count 2 2006.201.06:23:14.42#ibcon#about to write, iclass 11, count 2 2006.201.06:23:14.42#ibcon#wrote, iclass 11, count 2 2006.201.06:23:14.42#ibcon#about to read 3, iclass 11, count 2 2006.201.06:23:14.44#ibcon#read 3, iclass 11, count 2 2006.201.06:23:14.44#ibcon#about to read 4, iclass 11, count 2 2006.201.06:23:14.44#ibcon#read 4, iclass 11, count 2 2006.201.06:23:14.44#ibcon#about to read 5, iclass 11, count 2 2006.201.06:23:14.44#ibcon#read 5, iclass 11, count 2 2006.201.06:23:14.44#ibcon#about to read 6, iclass 11, count 2 2006.201.06:23:14.44#ibcon#read 6, iclass 11, count 2 2006.201.06:23:14.44#ibcon#end of sib2, iclass 11, count 2 2006.201.06:23:14.44#ibcon#*mode == 0, iclass 11, count 2 2006.201.06:23:14.44#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.06:23:14.44#ibcon#[25=AT08-04\r\n] 2006.201.06:23:14.44#ibcon#*before write, iclass 11, count 2 2006.201.06:23:14.44#ibcon#enter sib2, iclass 11, count 2 2006.201.06:23:14.44#ibcon#flushed, iclass 11, count 2 2006.201.06:23:14.44#ibcon#about to write, iclass 11, count 2 2006.201.06:23:14.44#ibcon#wrote, iclass 11, count 2 2006.201.06:23:14.44#ibcon#about to read 3, iclass 11, count 2 2006.201.06:23:14.47#ibcon#read 3, iclass 11, count 2 2006.201.06:23:14.47#ibcon#about to read 4, iclass 11, count 2 2006.201.06:23:14.47#ibcon#read 4, iclass 11, count 2 2006.201.06:23:14.47#ibcon#about to read 5, iclass 11, count 2 2006.201.06:23:14.47#ibcon#read 5, iclass 11, count 2 2006.201.06:23:14.47#ibcon#about to read 6, iclass 11, count 2 2006.201.06:23:14.47#ibcon#read 6, iclass 11, count 2 2006.201.06:23:14.47#ibcon#end of sib2, iclass 11, count 2 2006.201.06:23:14.47#ibcon#*after write, iclass 11, count 2 2006.201.06:23:14.47#ibcon#*before return 0, iclass 11, count 2 2006.201.06:23:14.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:23:14.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:23:14.47#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.06:23:14.47#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:14.47#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:23:14.59#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:23:14.59#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:23:14.59#ibcon#enter wrdev, iclass 11, count 0 2006.201.06:23:14.59#ibcon#first serial, iclass 11, count 0 2006.201.06:23:14.59#ibcon#enter sib2, iclass 11, count 0 2006.201.06:23:14.59#ibcon#flushed, iclass 11, count 0 2006.201.06:23:14.59#ibcon#about to write, iclass 11, count 0 2006.201.06:23:14.59#ibcon#wrote, iclass 11, count 0 2006.201.06:23:14.59#ibcon#about to read 3, iclass 11, count 0 2006.201.06:23:14.61#ibcon#read 3, iclass 11, count 0 2006.201.06:23:14.61#ibcon#about to read 4, iclass 11, count 0 2006.201.06:23:14.61#ibcon#read 4, iclass 11, count 0 2006.201.06:23:14.61#ibcon#about to read 5, iclass 11, count 0 2006.201.06:23:14.61#ibcon#read 5, iclass 11, count 0 2006.201.06:23:14.61#ibcon#about to read 6, iclass 11, count 0 2006.201.06:23:14.61#ibcon#read 6, iclass 11, count 0 2006.201.06:23:14.61#ibcon#end of sib2, iclass 11, count 0 2006.201.06:23:14.61#ibcon#*mode == 0, iclass 11, count 0 2006.201.06:23:14.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.06:23:14.61#ibcon#[25=USB\r\n] 2006.201.06:23:14.61#ibcon#*before write, iclass 11, count 0 2006.201.06:23:14.61#ibcon#enter sib2, iclass 11, count 0 2006.201.06:23:14.61#ibcon#flushed, iclass 11, count 0 2006.201.06:23:14.61#ibcon#about to write, iclass 11, count 0 2006.201.06:23:14.61#ibcon#wrote, iclass 11, count 0 2006.201.06:23:14.61#ibcon#about to read 3, iclass 11, count 0 2006.201.06:23:14.64#ibcon#read 3, iclass 11, count 0 2006.201.06:23:14.64#ibcon#about to read 4, iclass 11, count 0 2006.201.06:23:14.64#ibcon#read 4, iclass 11, count 0 2006.201.06:23:14.64#ibcon#about to read 5, iclass 11, count 0 2006.201.06:23:14.64#ibcon#read 5, iclass 11, count 0 2006.201.06:23:14.64#ibcon#about to read 6, iclass 11, count 0 2006.201.06:23:14.64#ibcon#read 6, iclass 11, count 0 2006.201.06:23:14.64#ibcon#end of sib2, iclass 11, count 0 2006.201.06:23:14.64#ibcon#*after write, iclass 11, count 0 2006.201.06:23:14.64#ibcon#*before return 0, iclass 11, count 0 2006.201.06:23:14.64#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:23:14.64#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:23:14.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.06:23:14.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.06:23:14.64$vck44/vblo=1,629.99 2006.201.06:23:14.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.06:23:14.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.06:23:14.64#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:14.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:23:14.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:23:14.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:23:14.64#ibcon#enter wrdev, iclass 13, count 0 2006.201.06:23:14.64#ibcon#first serial, iclass 13, count 0 2006.201.06:23:14.64#ibcon#enter sib2, iclass 13, count 0 2006.201.06:23:14.64#ibcon#flushed, iclass 13, count 0 2006.201.06:23:14.64#ibcon#about to write, iclass 13, count 0 2006.201.06:23:14.64#ibcon#wrote, iclass 13, count 0 2006.201.06:23:14.64#ibcon#about to read 3, iclass 13, count 0 2006.201.06:23:14.66#ibcon#read 3, iclass 13, count 0 2006.201.06:23:14.66#ibcon#about to read 4, iclass 13, count 0 2006.201.06:23:14.66#ibcon#read 4, iclass 13, count 0 2006.201.06:23:14.66#ibcon#about to read 5, iclass 13, count 0 2006.201.06:23:14.66#ibcon#read 5, iclass 13, count 0 2006.201.06:23:14.66#ibcon#about to read 6, iclass 13, count 0 2006.201.06:23:14.66#ibcon#read 6, iclass 13, count 0 2006.201.06:23:14.66#ibcon#end of sib2, iclass 13, count 0 2006.201.06:23:14.66#ibcon#*mode == 0, iclass 13, count 0 2006.201.06:23:14.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.06:23:14.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.06:23:14.66#ibcon#*before write, iclass 13, count 0 2006.201.06:23:14.66#ibcon#enter sib2, iclass 13, count 0 2006.201.06:23:14.66#ibcon#flushed, iclass 13, count 0 2006.201.06:23:14.66#ibcon#about to write, iclass 13, count 0 2006.201.06:23:14.66#ibcon#wrote, iclass 13, count 0 2006.201.06:23:14.66#ibcon#about to read 3, iclass 13, count 0 2006.201.06:23:14.71#ibcon#read 3, iclass 13, count 0 2006.201.06:23:14.71#ibcon#about to read 4, iclass 13, count 0 2006.201.06:23:14.71#ibcon#read 4, iclass 13, count 0 2006.201.06:23:14.71#ibcon#about to read 5, iclass 13, count 0 2006.201.06:23:14.71#ibcon#read 5, iclass 13, count 0 2006.201.06:23:14.71#ibcon#about to read 6, iclass 13, count 0 2006.201.06:23:14.71#ibcon#read 6, iclass 13, count 0 2006.201.06:23:14.71#ibcon#end of sib2, iclass 13, count 0 2006.201.06:23:14.71#ibcon#*after write, iclass 13, count 0 2006.201.06:23:14.71#ibcon#*before return 0, iclass 13, count 0 2006.201.06:23:14.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:23:14.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:23:14.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.06:23:14.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.06:23:14.71$vck44/vb=1,4 2006.201.06:23:14.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.06:23:14.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.06:23:14.71#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:14.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:23:14.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:23:14.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:23:14.71#ibcon#enter wrdev, iclass 15, count 2 2006.201.06:23:14.71#ibcon#first serial, iclass 15, count 2 2006.201.06:23:14.71#ibcon#enter sib2, iclass 15, count 2 2006.201.06:23:14.71#ibcon#flushed, iclass 15, count 2 2006.201.06:23:14.71#ibcon#about to write, iclass 15, count 2 2006.201.06:23:14.71#ibcon#wrote, iclass 15, count 2 2006.201.06:23:14.71#ibcon#about to read 3, iclass 15, count 2 2006.201.06:23:14.73#ibcon#read 3, iclass 15, count 2 2006.201.06:23:14.73#ibcon#about to read 4, iclass 15, count 2 2006.201.06:23:14.73#ibcon#read 4, iclass 15, count 2 2006.201.06:23:14.73#ibcon#about to read 5, iclass 15, count 2 2006.201.06:23:14.73#ibcon#read 5, iclass 15, count 2 2006.201.06:23:14.73#ibcon#about to read 6, iclass 15, count 2 2006.201.06:23:14.73#ibcon#read 6, iclass 15, count 2 2006.201.06:23:14.73#ibcon#end of sib2, iclass 15, count 2 2006.201.06:23:14.73#ibcon#*mode == 0, iclass 15, count 2 2006.201.06:23:14.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.06:23:14.73#ibcon#[27=AT01-04\r\n] 2006.201.06:23:14.73#ibcon#*before write, iclass 15, count 2 2006.201.06:23:14.73#ibcon#enter sib2, iclass 15, count 2 2006.201.06:23:14.73#ibcon#flushed, iclass 15, count 2 2006.201.06:23:14.73#ibcon#about to write, iclass 15, count 2 2006.201.06:23:14.73#ibcon#wrote, iclass 15, count 2 2006.201.06:23:14.73#ibcon#about to read 3, iclass 15, count 2 2006.201.06:23:14.76#ibcon#read 3, iclass 15, count 2 2006.201.06:23:14.76#ibcon#about to read 4, iclass 15, count 2 2006.201.06:23:14.76#ibcon#read 4, iclass 15, count 2 2006.201.06:23:14.76#ibcon#about to read 5, iclass 15, count 2 2006.201.06:23:14.76#ibcon#read 5, iclass 15, count 2 2006.201.06:23:14.76#ibcon#about to read 6, iclass 15, count 2 2006.201.06:23:14.76#ibcon#read 6, iclass 15, count 2 2006.201.06:23:14.76#ibcon#end of sib2, iclass 15, count 2 2006.201.06:23:14.76#ibcon#*after write, iclass 15, count 2 2006.201.06:23:14.76#ibcon#*before return 0, iclass 15, count 2 2006.201.06:23:14.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:23:14.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:23:14.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.06:23:14.76#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:14.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:23:14.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:23:14.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:23:14.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.06:23:14.88#ibcon#first serial, iclass 15, count 0 2006.201.06:23:14.88#ibcon#enter sib2, iclass 15, count 0 2006.201.06:23:14.88#ibcon#flushed, iclass 15, count 0 2006.201.06:23:14.88#ibcon#about to write, iclass 15, count 0 2006.201.06:23:14.88#ibcon#wrote, iclass 15, count 0 2006.201.06:23:14.88#ibcon#about to read 3, iclass 15, count 0 2006.201.06:23:14.90#ibcon#read 3, iclass 15, count 0 2006.201.06:23:14.90#ibcon#about to read 4, iclass 15, count 0 2006.201.06:23:14.90#ibcon#read 4, iclass 15, count 0 2006.201.06:23:14.90#ibcon#about to read 5, iclass 15, count 0 2006.201.06:23:14.90#ibcon#read 5, iclass 15, count 0 2006.201.06:23:14.90#ibcon#about to read 6, iclass 15, count 0 2006.201.06:23:14.90#ibcon#read 6, iclass 15, count 0 2006.201.06:23:14.90#ibcon#end of sib2, iclass 15, count 0 2006.201.06:23:14.90#ibcon#*mode == 0, iclass 15, count 0 2006.201.06:23:14.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.06:23:14.90#ibcon#[27=USB\r\n] 2006.201.06:23:14.90#ibcon#*before write, iclass 15, count 0 2006.201.06:23:14.90#ibcon#enter sib2, iclass 15, count 0 2006.201.06:23:14.90#ibcon#flushed, iclass 15, count 0 2006.201.06:23:14.90#ibcon#about to write, iclass 15, count 0 2006.201.06:23:14.90#ibcon#wrote, iclass 15, count 0 2006.201.06:23:14.90#ibcon#about to read 3, iclass 15, count 0 2006.201.06:23:14.93#ibcon#read 3, iclass 15, count 0 2006.201.06:23:14.93#ibcon#about to read 4, iclass 15, count 0 2006.201.06:23:14.93#ibcon#read 4, iclass 15, count 0 2006.201.06:23:14.93#ibcon#about to read 5, iclass 15, count 0 2006.201.06:23:14.93#ibcon#read 5, iclass 15, count 0 2006.201.06:23:14.93#ibcon#about to read 6, iclass 15, count 0 2006.201.06:23:14.93#ibcon#read 6, iclass 15, count 0 2006.201.06:23:14.93#ibcon#end of sib2, iclass 15, count 0 2006.201.06:23:14.93#ibcon#*after write, iclass 15, count 0 2006.201.06:23:14.93#ibcon#*before return 0, iclass 15, count 0 2006.201.06:23:14.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:23:14.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:23:14.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.06:23:14.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.06:23:14.93$vck44/vblo=2,634.99 2006.201.06:23:14.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.06:23:14.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.06:23:14.93#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:14.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:14.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:14.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:14.93#ibcon#enter wrdev, iclass 17, count 0 2006.201.06:23:14.93#ibcon#first serial, iclass 17, count 0 2006.201.06:23:14.93#ibcon#enter sib2, iclass 17, count 0 2006.201.06:23:14.93#ibcon#flushed, iclass 17, count 0 2006.201.06:23:14.93#ibcon#about to write, iclass 17, count 0 2006.201.06:23:14.93#ibcon#wrote, iclass 17, count 0 2006.201.06:23:14.93#ibcon#about to read 3, iclass 17, count 0 2006.201.06:23:14.95#ibcon#read 3, iclass 17, count 0 2006.201.06:23:14.95#ibcon#about to read 4, iclass 17, count 0 2006.201.06:23:14.95#ibcon#read 4, iclass 17, count 0 2006.201.06:23:14.95#ibcon#about to read 5, iclass 17, count 0 2006.201.06:23:14.95#ibcon#read 5, iclass 17, count 0 2006.201.06:23:14.95#ibcon#about to read 6, iclass 17, count 0 2006.201.06:23:14.95#ibcon#read 6, iclass 17, count 0 2006.201.06:23:14.95#ibcon#end of sib2, iclass 17, count 0 2006.201.06:23:14.95#ibcon#*mode == 0, iclass 17, count 0 2006.201.06:23:14.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.06:23:14.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.06:23:14.95#ibcon#*before write, iclass 17, count 0 2006.201.06:23:14.95#ibcon#enter sib2, iclass 17, count 0 2006.201.06:23:14.95#ibcon#flushed, iclass 17, count 0 2006.201.06:23:14.95#ibcon#about to write, iclass 17, count 0 2006.201.06:23:14.95#ibcon#wrote, iclass 17, count 0 2006.201.06:23:14.95#ibcon#about to read 3, iclass 17, count 0 2006.201.06:23:14.99#ibcon#read 3, iclass 17, count 0 2006.201.06:23:14.99#ibcon#about to read 4, iclass 17, count 0 2006.201.06:23:14.99#ibcon#read 4, iclass 17, count 0 2006.201.06:23:14.99#ibcon#about to read 5, iclass 17, count 0 2006.201.06:23:14.99#ibcon#read 5, iclass 17, count 0 2006.201.06:23:14.99#ibcon#about to read 6, iclass 17, count 0 2006.201.06:23:14.99#ibcon#read 6, iclass 17, count 0 2006.201.06:23:14.99#ibcon#end of sib2, iclass 17, count 0 2006.201.06:23:14.99#ibcon#*after write, iclass 17, count 0 2006.201.06:23:14.99#ibcon#*before return 0, iclass 17, count 0 2006.201.06:23:14.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:14.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:23:14.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.06:23:14.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.06:23:14.99$vck44/vb=2,5 2006.201.06:23:14.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.06:23:14.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.06:23:14.99#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:14.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:15.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:15.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:15.05#ibcon#enter wrdev, iclass 19, count 2 2006.201.06:23:15.05#ibcon#first serial, iclass 19, count 2 2006.201.06:23:15.05#ibcon#enter sib2, iclass 19, count 2 2006.201.06:23:15.05#ibcon#flushed, iclass 19, count 2 2006.201.06:23:15.05#ibcon#about to write, iclass 19, count 2 2006.201.06:23:15.05#ibcon#wrote, iclass 19, count 2 2006.201.06:23:15.05#ibcon#about to read 3, iclass 19, count 2 2006.201.06:23:15.07#ibcon#read 3, iclass 19, count 2 2006.201.06:23:15.07#ibcon#about to read 4, iclass 19, count 2 2006.201.06:23:15.07#ibcon#read 4, iclass 19, count 2 2006.201.06:23:15.07#ibcon#about to read 5, iclass 19, count 2 2006.201.06:23:15.07#ibcon#read 5, iclass 19, count 2 2006.201.06:23:15.07#ibcon#about to read 6, iclass 19, count 2 2006.201.06:23:15.07#ibcon#read 6, iclass 19, count 2 2006.201.06:23:15.07#ibcon#end of sib2, iclass 19, count 2 2006.201.06:23:15.07#ibcon#*mode == 0, iclass 19, count 2 2006.201.06:23:15.07#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.06:23:15.07#ibcon#[27=AT02-05\r\n] 2006.201.06:23:15.07#ibcon#*before write, iclass 19, count 2 2006.201.06:23:15.07#ibcon#enter sib2, iclass 19, count 2 2006.201.06:23:15.07#ibcon#flushed, iclass 19, count 2 2006.201.06:23:15.07#ibcon#about to write, iclass 19, count 2 2006.201.06:23:15.07#ibcon#wrote, iclass 19, count 2 2006.201.06:23:15.07#ibcon#about to read 3, iclass 19, count 2 2006.201.06:23:15.10#ibcon#read 3, iclass 19, count 2 2006.201.06:23:15.10#ibcon#about to read 4, iclass 19, count 2 2006.201.06:23:15.10#ibcon#read 4, iclass 19, count 2 2006.201.06:23:15.10#ibcon#about to read 5, iclass 19, count 2 2006.201.06:23:15.10#ibcon#read 5, iclass 19, count 2 2006.201.06:23:15.10#ibcon#about to read 6, iclass 19, count 2 2006.201.06:23:15.10#ibcon#read 6, iclass 19, count 2 2006.201.06:23:15.10#ibcon#end of sib2, iclass 19, count 2 2006.201.06:23:15.10#ibcon#*after write, iclass 19, count 2 2006.201.06:23:15.10#ibcon#*before return 0, iclass 19, count 2 2006.201.06:23:15.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:15.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:23:15.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.06:23:15.10#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:15.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:15.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:15.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:15.22#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:23:15.22#ibcon#first serial, iclass 19, count 0 2006.201.06:23:15.22#ibcon#enter sib2, iclass 19, count 0 2006.201.06:23:15.22#ibcon#flushed, iclass 19, count 0 2006.201.06:23:15.22#ibcon#about to write, iclass 19, count 0 2006.201.06:23:15.22#ibcon#wrote, iclass 19, count 0 2006.201.06:23:15.22#ibcon#about to read 3, iclass 19, count 0 2006.201.06:23:15.24#ibcon#read 3, iclass 19, count 0 2006.201.06:23:15.24#ibcon#about to read 4, iclass 19, count 0 2006.201.06:23:15.24#ibcon#read 4, iclass 19, count 0 2006.201.06:23:15.24#ibcon#about to read 5, iclass 19, count 0 2006.201.06:23:15.24#ibcon#read 5, iclass 19, count 0 2006.201.06:23:15.24#ibcon#about to read 6, iclass 19, count 0 2006.201.06:23:15.24#ibcon#read 6, iclass 19, count 0 2006.201.06:23:15.24#ibcon#end of sib2, iclass 19, count 0 2006.201.06:23:15.24#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:23:15.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:23:15.24#ibcon#[27=USB\r\n] 2006.201.06:23:15.24#ibcon#*before write, iclass 19, count 0 2006.201.06:23:15.24#ibcon#enter sib2, iclass 19, count 0 2006.201.06:23:15.24#ibcon#flushed, iclass 19, count 0 2006.201.06:23:15.24#ibcon#about to write, iclass 19, count 0 2006.201.06:23:15.24#ibcon#wrote, iclass 19, count 0 2006.201.06:23:15.24#ibcon#about to read 3, iclass 19, count 0 2006.201.06:23:15.27#ibcon#read 3, iclass 19, count 0 2006.201.06:23:15.27#ibcon#about to read 4, iclass 19, count 0 2006.201.06:23:15.27#ibcon#read 4, iclass 19, count 0 2006.201.06:23:15.27#ibcon#about to read 5, iclass 19, count 0 2006.201.06:23:15.27#ibcon#read 5, iclass 19, count 0 2006.201.06:23:15.27#ibcon#about to read 6, iclass 19, count 0 2006.201.06:23:15.27#ibcon#read 6, iclass 19, count 0 2006.201.06:23:15.27#ibcon#end of sib2, iclass 19, count 0 2006.201.06:23:15.27#ibcon#*after write, iclass 19, count 0 2006.201.06:23:15.27#ibcon#*before return 0, iclass 19, count 0 2006.201.06:23:15.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:15.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:23:15.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:23:15.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:23:15.27$vck44/vblo=3,649.99 2006.201.06:23:15.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.06:23:15.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.06:23:15.27#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:15.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:15.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:15.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:15.27#ibcon#enter wrdev, iclass 21, count 0 2006.201.06:23:15.27#ibcon#first serial, iclass 21, count 0 2006.201.06:23:15.27#ibcon#enter sib2, iclass 21, count 0 2006.201.06:23:15.27#ibcon#flushed, iclass 21, count 0 2006.201.06:23:15.27#ibcon#about to write, iclass 21, count 0 2006.201.06:23:15.27#ibcon#wrote, iclass 21, count 0 2006.201.06:23:15.27#ibcon#about to read 3, iclass 21, count 0 2006.201.06:23:15.29#ibcon#read 3, iclass 21, count 0 2006.201.06:23:15.29#ibcon#about to read 4, iclass 21, count 0 2006.201.06:23:15.29#ibcon#read 4, iclass 21, count 0 2006.201.06:23:15.29#ibcon#about to read 5, iclass 21, count 0 2006.201.06:23:15.29#ibcon#read 5, iclass 21, count 0 2006.201.06:23:15.29#ibcon#about to read 6, iclass 21, count 0 2006.201.06:23:15.29#ibcon#read 6, iclass 21, count 0 2006.201.06:23:15.29#ibcon#end of sib2, iclass 21, count 0 2006.201.06:23:15.29#ibcon#*mode == 0, iclass 21, count 0 2006.201.06:23:15.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.06:23:15.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.06:23:15.29#ibcon#*before write, iclass 21, count 0 2006.201.06:23:15.29#ibcon#enter sib2, iclass 21, count 0 2006.201.06:23:15.29#ibcon#flushed, iclass 21, count 0 2006.201.06:23:15.29#ibcon#about to write, iclass 21, count 0 2006.201.06:23:15.29#ibcon#wrote, iclass 21, count 0 2006.201.06:23:15.29#ibcon#about to read 3, iclass 21, count 0 2006.201.06:23:15.34#ibcon#read 3, iclass 21, count 0 2006.201.06:23:15.34#ibcon#about to read 4, iclass 21, count 0 2006.201.06:23:15.34#ibcon#read 4, iclass 21, count 0 2006.201.06:23:15.34#ibcon#about to read 5, iclass 21, count 0 2006.201.06:23:15.34#ibcon#read 5, iclass 21, count 0 2006.201.06:23:15.34#ibcon#about to read 6, iclass 21, count 0 2006.201.06:23:15.34#ibcon#read 6, iclass 21, count 0 2006.201.06:23:15.34#ibcon#end of sib2, iclass 21, count 0 2006.201.06:23:15.34#ibcon#*after write, iclass 21, count 0 2006.201.06:23:15.34#ibcon#*before return 0, iclass 21, count 0 2006.201.06:23:15.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:15.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:23:15.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.06:23:15.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.06:23:15.34$vck44/vb=3,4 2006.201.06:23:15.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.06:23:15.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.06:23:15.34#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:15.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:15.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:15.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:15.39#ibcon#enter wrdev, iclass 23, count 2 2006.201.06:23:15.39#ibcon#first serial, iclass 23, count 2 2006.201.06:23:15.39#ibcon#enter sib2, iclass 23, count 2 2006.201.06:23:15.39#ibcon#flushed, iclass 23, count 2 2006.201.06:23:15.39#ibcon#about to write, iclass 23, count 2 2006.201.06:23:15.39#ibcon#wrote, iclass 23, count 2 2006.201.06:23:15.39#ibcon#about to read 3, iclass 23, count 2 2006.201.06:23:15.41#ibcon#read 3, iclass 23, count 2 2006.201.06:23:15.41#ibcon#about to read 4, iclass 23, count 2 2006.201.06:23:15.41#ibcon#read 4, iclass 23, count 2 2006.201.06:23:15.41#ibcon#about to read 5, iclass 23, count 2 2006.201.06:23:15.41#ibcon#read 5, iclass 23, count 2 2006.201.06:23:15.41#ibcon#about to read 6, iclass 23, count 2 2006.201.06:23:15.41#ibcon#read 6, iclass 23, count 2 2006.201.06:23:15.41#ibcon#end of sib2, iclass 23, count 2 2006.201.06:23:15.41#ibcon#*mode == 0, iclass 23, count 2 2006.201.06:23:15.41#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.06:23:15.41#ibcon#[27=AT03-04\r\n] 2006.201.06:23:15.41#ibcon#*before write, iclass 23, count 2 2006.201.06:23:15.41#ibcon#enter sib2, iclass 23, count 2 2006.201.06:23:15.41#ibcon#flushed, iclass 23, count 2 2006.201.06:23:15.41#ibcon#about to write, iclass 23, count 2 2006.201.06:23:15.41#ibcon#wrote, iclass 23, count 2 2006.201.06:23:15.41#ibcon#about to read 3, iclass 23, count 2 2006.201.06:23:15.44#ibcon#read 3, iclass 23, count 2 2006.201.06:23:15.44#ibcon#about to read 4, iclass 23, count 2 2006.201.06:23:15.44#ibcon#read 4, iclass 23, count 2 2006.201.06:23:15.44#ibcon#about to read 5, iclass 23, count 2 2006.201.06:23:15.44#ibcon#read 5, iclass 23, count 2 2006.201.06:23:15.44#ibcon#about to read 6, iclass 23, count 2 2006.201.06:23:15.44#ibcon#read 6, iclass 23, count 2 2006.201.06:23:15.44#ibcon#end of sib2, iclass 23, count 2 2006.201.06:23:15.44#ibcon#*after write, iclass 23, count 2 2006.201.06:23:15.44#ibcon#*before return 0, iclass 23, count 2 2006.201.06:23:15.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:15.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:23:15.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.06:23:15.44#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:15.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:15.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:15.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:15.56#ibcon#enter wrdev, iclass 23, count 0 2006.201.06:23:15.56#ibcon#first serial, iclass 23, count 0 2006.201.06:23:15.56#ibcon#enter sib2, iclass 23, count 0 2006.201.06:23:15.56#ibcon#flushed, iclass 23, count 0 2006.201.06:23:15.56#ibcon#about to write, iclass 23, count 0 2006.201.06:23:15.56#ibcon#wrote, iclass 23, count 0 2006.201.06:23:15.56#ibcon#about to read 3, iclass 23, count 0 2006.201.06:23:15.58#ibcon#read 3, iclass 23, count 0 2006.201.06:23:15.58#ibcon#about to read 4, iclass 23, count 0 2006.201.06:23:15.58#ibcon#read 4, iclass 23, count 0 2006.201.06:23:15.58#ibcon#about to read 5, iclass 23, count 0 2006.201.06:23:15.58#ibcon#read 5, iclass 23, count 0 2006.201.06:23:15.58#ibcon#about to read 6, iclass 23, count 0 2006.201.06:23:15.58#ibcon#read 6, iclass 23, count 0 2006.201.06:23:15.58#ibcon#end of sib2, iclass 23, count 0 2006.201.06:23:15.58#ibcon#*mode == 0, iclass 23, count 0 2006.201.06:23:15.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.06:23:15.58#ibcon#[27=USB\r\n] 2006.201.06:23:15.58#ibcon#*before write, iclass 23, count 0 2006.201.06:23:15.58#ibcon#enter sib2, iclass 23, count 0 2006.201.06:23:15.58#ibcon#flushed, iclass 23, count 0 2006.201.06:23:15.58#ibcon#about to write, iclass 23, count 0 2006.201.06:23:15.58#ibcon#wrote, iclass 23, count 0 2006.201.06:23:15.58#ibcon#about to read 3, iclass 23, count 0 2006.201.06:23:15.61#ibcon#read 3, iclass 23, count 0 2006.201.06:23:15.61#ibcon#about to read 4, iclass 23, count 0 2006.201.06:23:15.61#ibcon#read 4, iclass 23, count 0 2006.201.06:23:15.61#ibcon#about to read 5, iclass 23, count 0 2006.201.06:23:15.61#ibcon#read 5, iclass 23, count 0 2006.201.06:23:15.61#ibcon#about to read 6, iclass 23, count 0 2006.201.06:23:15.61#ibcon#read 6, iclass 23, count 0 2006.201.06:23:15.61#ibcon#end of sib2, iclass 23, count 0 2006.201.06:23:15.61#ibcon#*after write, iclass 23, count 0 2006.201.06:23:15.61#ibcon#*before return 0, iclass 23, count 0 2006.201.06:23:15.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:15.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:23:15.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.06:23:15.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.06:23:15.61$vck44/vblo=4,679.99 2006.201.06:23:15.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.06:23:15.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.06:23:15.61#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:15.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:15.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:15.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:15.61#ibcon#enter wrdev, iclass 25, count 0 2006.201.06:23:15.61#ibcon#first serial, iclass 25, count 0 2006.201.06:23:15.61#ibcon#enter sib2, iclass 25, count 0 2006.201.06:23:15.61#ibcon#flushed, iclass 25, count 0 2006.201.06:23:15.61#ibcon#about to write, iclass 25, count 0 2006.201.06:23:15.61#ibcon#wrote, iclass 25, count 0 2006.201.06:23:15.61#ibcon#about to read 3, iclass 25, count 0 2006.201.06:23:15.63#ibcon#read 3, iclass 25, count 0 2006.201.06:23:15.63#ibcon#about to read 4, iclass 25, count 0 2006.201.06:23:15.63#ibcon#read 4, iclass 25, count 0 2006.201.06:23:15.63#ibcon#about to read 5, iclass 25, count 0 2006.201.06:23:15.63#ibcon#read 5, iclass 25, count 0 2006.201.06:23:15.63#ibcon#about to read 6, iclass 25, count 0 2006.201.06:23:15.63#ibcon#read 6, iclass 25, count 0 2006.201.06:23:15.63#ibcon#end of sib2, iclass 25, count 0 2006.201.06:23:15.63#ibcon#*mode == 0, iclass 25, count 0 2006.201.06:23:15.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.06:23:15.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.06:23:15.63#ibcon#*before write, iclass 25, count 0 2006.201.06:23:15.63#ibcon#enter sib2, iclass 25, count 0 2006.201.06:23:15.63#ibcon#flushed, iclass 25, count 0 2006.201.06:23:15.63#ibcon#about to write, iclass 25, count 0 2006.201.06:23:15.63#ibcon#wrote, iclass 25, count 0 2006.201.06:23:15.63#ibcon#about to read 3, iclass 25, count 0 2006.201.06:23:15.68#ibcon#read 3, iclass 25, count 0 2006.201.06:23:15.68#ibcon#about to read 4, iclass 25, count 0 2006.201.06:23:15.68#ibcon#read 4, iclass 25, count 0 2006.201.06:23:15.68#ibcon#about to read 5, iclass 25, count 0 2006.201.06:23:15.68#ibcon#read 5, iclass 25, count 0 2006.201.06:23:15.68#ibcon#about to read 6, iclass 25, count 0 2006.201.06:23:15.68#ibcon#read 6, iclass 25, count 0 2006.201.06:23:15.68#ibcon#end of sib2, iclass 25, count 0 2006.201.06:23:15.68#ibcon#*after write, iclass 25, count 0 2006.201.06:23:15.68#ibcon#*before return 0, iclass 25, count 0 2006.201.06:23:15.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:15.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:23:15.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.06:23:15.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.06:23:15.68$vck44/vb=4,5 2006.201.06:23:15.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.06:23:15.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.06:23:15.68#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:15.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:15.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:15.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:15.73#ibcon#enter wrdev, iclass 27, count 2 2006.201.06:23:15.73#ibcon#first serial, iclass 27, count 2 2006.201.06:23:15.73#ibcon#enter sib2, iclass 27, count 2 2006.201.06:23:15.73#ibcon#flushed, iclass 27, count 2 2006.201.06:23:15.73#ibcon#about to write, iclass 27, count 2 2006.201.06:23:15.73#ibcon#wrote, iclass 27, count 2 2006.201.06:23:15.73#ibcon#about to read 3, iclass 27, count 2 2006.201.06:23:15.75#ibcon#read 3, iclass 27, count 2 2006.201.06:23:15.75#ibcon#about to read 4, iclass 27, count 2 2006.201.06:23:15.75#ibcon#read 4, iclass 27, count 2 2006.201.06:23:15.75#ibcon#about to read 5, iclass 27, count 2 2006.201.06:23:15.75#ibcon#read 5, iclass 27, count 2 2006.201.06:23:15.75#ibcon#about to read 6, iclass 27, count 2 2006.201.06:23:15.75#ibcon#read 6, iclass 27, count 2 2006.201.06:23:15.75#ibcon#end of sib2, iclass 27, count 2 2006.201.06:23:15.75#ibcon#*mode == 0, iclass 27, count 2 2006.201.06:23:15.75#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.06:23:15.75#ibcon#[27=AT04-05\r\n] 2006.201.06:23:15.75#ibcon#*before write, iclass 27, count 2 2006.201.06:23:15.75#ibcon#enter sib2, iclass 27, count 2 2006.201.06:23:15.75#ibcon#flushed, iclass 27, count 2 2006.201.06:23:15.75#ibcon#about to write, iclass 27, count 2 2006.201.06:23:15.75#ibcon#wrote, iclass 27, count 2 2006.201.06:23:15.75#ibcon#about to read 3, iclass 27, count 2 2006.201.06:23:15.78#ibcon#read 3, iclass 27, count 2 2006.201.06:23:15.78#ibcon#about to read 4, iclass 27, count 2 2006.201.06:23:15.78#ibcon#read 4, iclass 27, count 2 2006.201.06:23:15.78#ibcon#about to read 5, iclass 27, count 2 2006.201.06:23:15.78#ibcon#read 5, iclass 27, count 2 2006.201.06:23:15.78#ibcon#about to read 6, iclass 27, count 2 2006.201.06:23:15.78#ibcon#read 6, iclass 27, count 2 2006.201.06:23:15.78#ibcon#end of sib2, iclass 27, count 2 2006.201.06:23:15.78#ibcon#*after write, iclass 27, count 2 2006.201.06:23:15.78#ibcon#*before return 0, iclass 27, count 2 2006.201.06:23:15.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:15.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:23:15.78#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.06:23:15.78#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:15.78#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:15.90#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:15.90#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:15.90#ibcon#enter wrdev, iclass 27, count 0 2006.201.06:23:15.90#ibcon#first serial, iclass 27, count 0 2006.201.06:23:15.90#ibcon#enter sib2, iclass 27, count 0 2006.201.06:23:15.90#ibcon#flushed, iclass 27, count 0 2006.201.06:23:15.90#ibcon#about to write, iclass 27, count 0 2006.201.06:23:15.90#ibcon#wrote, iclass 27, count 0 2006.201.06:23:15.90#ibcon#about to read 3, iclass 27, count 0 2006.201.06:23:15.92#ibcon#read 3, iclass 27, count 0 2006.201.06:23:15.92#ibcon#about to read 4, iclass 27, count 0 2006.201.06:23:15.92#ibcon#read 4, iclass 27, count 0 2006.201.06:23:15.92#ibcon#about to read 5, iclass 27, count 0 2006.201.06:23:15.92#ibcon#read 5, iclass 27, count 0 2006.201.06:23:15.92#ibcon#about to read 6, iclass 27, count 0 2006.201.06:23:15.92#ibcon#read 6, iclass 27, count 0 2006.201.06:23:15.92#ibcon#end of sib2, iclass 27, count 0 2006.201.06:23:15.92#ibcon#*mode == 0, iclass 27, count 0 2006.201.06:23:15.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.06:23:15.92#ibcon#[27=USB\r\n] 2006.201.06:23:15.92#ibcon#*before write, iclass 27, count 0 2006.201.06:23:15.92#ibcon#enter sib2, iclass 27, count 0 2006.201.06:23:15.92#ibcon#flushed, iclass 27, count 0 2006.201.06:23:15.92#ibcon#about to write, iclass 27, count 0 2006.201.06:23:15.92#ibcon#wrote, iclass 27, count 0 2006.201.06:23:15.92#ibcon#about to read 3, iclass 27, count 0 2006.201.06:23:15.95#ibcon#read 3, iclass 27, count 0 2006.201.06:23:15.95#ibcon#about to read 4, iclass 27, count 0 2006.201.06:23:15.95#ibcon#read 4, iclass 27, count 0 2006.201.06:23:15.95#ibcon#about to read 5, iclass 27, count 0 2006.201.06:23:15.95#ibcon#read 5, iclass 27, count 0 2006.201.06:23:15.95#ibcon#about to read 6, iclass 27, count 0 2006.201.06:23:15.95#ibcon#read 6, iclass 27, count 0 2006.201.06:23:15.95#ibcon#end of sib2, iclass 27, count 0 2006.201.06:23:15.95#ibcon#*after write, iclass 27, count 0 2006.201.06:23:15.95#ibcon#*before return 0, iclass 27, count 0 2006.201.06:23:15.95#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:15.95#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:23:15.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.06:23:15.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.06:23:15.95$vck44/vblo=5,709.99 2006.201.06:23:15.95#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.06:23:15.95#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.06:23:15.95#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:15.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:15.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:15.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:15.95#ibcon#enter wrdev, iclass 29, count 0 2006.201.06:23:15.95#ibcon#first serial, iclass 29, count 0 2006.201.06:23:15.95#ibcon#enter sib2, iclass 29, count 0 2006.201.06:23:15.95#ibcon#flushed, iclass 29, count 0 2006.201.06:23:15.95#ibcon#about to write, iclass 29, count 0 2006.201.06:23:15.95#ibcon#wrote, iclass 29, count 0 2006.201.06:23:15.95#ibcon#about to read 3, iclass 29, count 0 2006.201.06:23:15.97#ibcon#read 3, iclass 29, count 0 2006.201.06:23:15.97#ibcon#about to read 4, iclass 29, count 0 2006.201.06:23:15.97#ibcon#read 4, iclass 29, count 0 2006.201.06:23:15.97#ibcon#about to read 5, iclass 29, count 0 2006.201.06:23:15.97#ibcon#read 5, iclass 29, count 0 2006.201.06:23:15.97#ibcon#about to read 6, iclass 29, count 0 2006.201.06:23:15.97#ibcon#read 6, iclass 29, count 0 2006.201.06:23:15.97#ibcon#end of sib2, iclass 29, count 0 2006.201.06:23:15.97#ibcon#*mode == 0, iclass 29, count 0 2006.201.06:23:15.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.06:23:15.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.06:23:15.97#ibcon#*before write, iclass 29, count 0 2006.201.06:23:15.97#ibcon#enter sib2, iclass 29, count 0 2006.201.06:23:15.97#ibcon#flushed, iclass 29, count 0 2006.201.06:23:15.97#ibcon#about to write, iclass 29, count 0 2006.201.06:23:15.97#ibcon#wrote, iclass 29, count 0 2006.201.06:23:15.97#ibcon#about to read 3, iclass 29, count 0 2006.201.06:23:16.01#ibcon#read 3, iclass 29, count 0 2006.201.06:23:16.01#ibcon#about to read 4, iclass 29, count 0 2006.201.06:23:16.01#ibcon#read 4, iclass 29, count 0 2006.201.06:23:16.01#ibcon#about to read 5, iclass 29, count 0 2006.201.06:23:16.01#ibcon#read 5, iclass 29, count 0 2006.201.06:23:16.01#ibcon#about to read 6, iclass 29, count 0 2006.201.06:23:16.01#ibcon#read 6, iclass 29, count 0 2006.201.06:23:16.01#ibcon#end of sib2, iclass 29, count 0 2006.201.06:23:16.01#ibcon#*after write, iclass 29, count 0 2006.201.06:23:16.01#ibcon#*before return 0, iclass 29, count 0 2006.201.06:23:16.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:16.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:23:16.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.06:23:16.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.06:23:16.01$vck44/vb=5,4 2006.201.06:23:16.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.06:23:16.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.06:23:16.01#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:16.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:16.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:16.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:16.07#ibcon#enter wrdev, iclass 31, count 2 2006.201.06:23:16.07#ibcon#first serial, iclass 31, count 2 2006.201.06:23:16.07#ibcon#enter sib2, iclass 31, count 2 2006.201.06:23:16.07#ibcon#flushed, iclass 31, count 2 2006.201.06:23:16.07#ibcon#about to write, iclass 31, count 2 2006.201.06:23:16.07#ibcon#wrote, iclass 31, count 2 2006.201.06:23:16.07#ibcon#about to read 3, iclass 31, count 2 2006.201.06:23:16.09#ibcon#read 3, iclass 31, count 2 2006.201.06:23:16.09#ibcon#about to read 4, iclass 31, count 2 2006.201.06:23:16.09#ibcon#read 4, iclass 31, count 2 2006.201.06:23:16.09#ibcon#about to read 5, iclass 31, count 2 2006.201.06:23:16.09#ibcon#read 5, iclass 31, count 2 2006.201.06:23:16.09#ibcon#about to read 6, iclass 31, count 2 2006.201.06:23:16.09#ibcon#read 6, iclass 31, count 2 2006.201.06:23:16.09#ibcon#end of sib2, iclass 31, count 2 2006.201.06:23:16.09#ibcon#*mode == 0, iclass 31, count 2 2006.201.06:23:16.09#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.06:23:16.09#ibcon#[27=AT05-04\r\n] 2006.201.06:23:16.09#ibcon#*before write, iclass 31, count 2 2006.201.06:23:16.09#ibcon#enter sib2, iclass 31, count 2 2006.201.06:23:16.09#ibcon#flushed, iclass 31, count 2 2006.201.06:23:16.09#ibcon#about to write, iclass 31, count 2 2006.201.06:23:16.09#ibcon#wrote, iclass 31, count 2 2006.201.06:23:16.09#ibcon#about to read 3, iclass 31, count 2 2006.201.06:23:16.12#ibcon#read 3, iclass 31, count 2 2006.201.06:23:16.12#ibcon#about to read 4, iclass 31, count 2 2006.201.06:23:16.12#ibcon#read 4, iclass 31, count 2 2006.201.06:23:16.12#ibcon#about to read 5, iclass 31, count 2 2006.201.06:23:16.12#ibcon#read 5, iclass 31, count 2 2006.201.06:23:16.12#ibcon#about to read 6, iclass 31, count 2 2006.201.06:23:16.12#ibcon#read 6, iclass 31, count 2 2006.201.06:23:16.12#ibcon#end of sib2, iclass 31, count 2 2006.201.06:23:16.12#ibcon#*after write, iclass 31, count 2 2006.201.06:23:16.12#ibcon#*before return 0, iclass 31, count 2 2006.201.06:23:16.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:16.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:23:16.12#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.06:23:16.12#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:16.12#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:16.24#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:16.24#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:16.24#ibcon#enter wrdev, iclass 31, count 0 2006.201.06:23:16.24#ibcon#first serial, iclass 31, count 0 2006.201.06:23:16.24#ibcon#enter sib2, iclass 31, count 0 2006.201.06:23:16.24#ibcon#flushed, iclass 31, count 0 2006.201.06:23:16.24#ibcon#about to write, iclass 31, count 0 2006.201.06:23:16.24#ibcon#wrote, iclass 31, count 0 2006.201.06:23:16.24#ibcon#about to read 3, iclass 31, count 0 2006.201.06:23:16.26#ibcon#read 3, iclass 31, count 0 2006.201.06:23:16.26#ibcon#about to read 4, iclass 31, count 0 2006.201.06:23:16.26#ibcon#read 4, iclass 31, count 0 2006.201.06:23:16.26#ibcon#about to read 5, iclass 31, count 0 2006.201.06:23:16.26#ibcon#read 5, iclass 31, count 0 2006.201.06:23:16.26#ibcon#about to read 6, iclass 31, count 0 2006.201.06:23:16.26#ibcon#read 6, iclass 31, count 0 2006.201.06:23:16.26#ibcon#end of sib2, iclass 31, count 0 2006.201.06:23:16.26#ibcon#*mode == 0, iclass 31, count 0 2006.201.06:23:16.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.06:23:16.26#ibcon#[27=USB\r\n] 2006.201.06:23:16.26#ibcon#*before write, iclass 31, count 0 2006.201.06:23:16.26#ibcon#enter sib2, iclass 31, count 0 2006.201.06:23:16.26#ibcon#flushed, iclass 31, count 0 2006.201.06:23:16.26#ibcon#about to write, iclass 31, count 0 2006.201.06:23:16.26#ibcon#wrote, iclass 31, count 0 2006.201.06:23:16.26#ibcon#about to read 3, iclass 31, count 0 2006.201.06:23:16.29#ibcon#read 3, iclass 31, count 0 2006.201.06:23:16.29#ibcon#about to read 4, iclass 31, count 0 2006.201.06:23:16.29#ibcon#read 4, iclass 31, count 0 2006.201.06:23:16.29#ibcon#about to read 5, iclass 31, count 0 2006.201.06:23:16.29#ibcon#read 5, iclass 31, count 0 2006.201.06:23:16.29#ibcon#about to read 6, iclass 31, count 0 2006.201.06:23:16.29#ibcon#read 6, iclass 31, count 0 2006.201.06:23:16.29#ibcon#end of sib2, iclass 31, count 0 2006.201.06:23:16.29#ibcon#*after write, iclass 31, count 0 2006.201.06:23:16.29#ibcon#*before return 0, iclass 31, count 0 2006.201.06:23:16.29#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:16.29#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:23:16.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.06:23:16.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.06:23:16.29$vck44/vblo=6,719.99 2006.201.06:23:16.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.06:23:16.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.06:23:16.29#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:16.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:16.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:16.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:16.29#ibcon#enter wrdev, iclass 33, count 0 2006.201.06:23:16.29#ibcon#first serial, iclass 33, count 0 2006.201.06:23:16.29#ibcon#enter sib2, iclass 33, count 0 2006.201.06:23:16.29#ibcon#flushed, iclass 33, count 0 2006.201.06:23:16.29#ibcon#about to write, iclass 33, count 0 2006.201.06:23:16.29#ibcon#wrote, iclass 33, count 0 2006.201.06:23:16.29#ibcon#about to read 3, iclass 33, count 0 2006.201.06:23:16.31#ibcon#read 3, iclass 33, count 0 2006.201.06:23:16.31#ibcon#about to read 4, iclass 33, count 0 2006.201.06:23:16.31#ibcon#read 4, iclass 33, count 0 2006.201.06:23:16.31#ibcon#about to read 5, iclass 33, count 0 2006.201.06:23:16.31#ibcon#read 5, iclass 33, count 0 2006.201.06:23:16.31#ibcon#about to read 6, iclass 33, count 0 2006.201.06:23:16.31#ibcon#read 6, iclass 33, count 0 2006.201.06:23:16.31#ibcon#end of sib2, iclass 33, count 0 2006.201.06:23:16.31#ibcon#*mode == 0, iclass 33, count 0 2006.201.06:23:16.31#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.06:23:16.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.06:23:16.31#ibcon#*before write, iclass 33, count 0 2006.201.06:23:16.31#ibcon#enter sib2, iclass 33, count 0 2006.201.06:23:16.31#ibcon#flushed, iclass 33, count 0 2006.201.06:23:16.31#ibcon#about to write, iclass 33, count 0 2006.201.06:23:16.31#ibcon#wrote, iclass 33, count 0 2006.201.06:23:16.31#ibcon#about to read 3, iclass 33, count 0 2006.201.06:23:16.36#ibcon#read 3, iclass 33, count 0 2006.201.06:23:16.36#ibcon#about to read 4, iclass 33, count 0 2006.201.06:23:16.36#ibcon#read 4, iclass 33, count 0 2006.201.06:23:16.36#ibcon#about to read 5, iclass 33, count 0 2006.201.06:23:16.36#ibcon#read 5, iclass 33, count 0 2006.201.06:23:16.36#ibcon#about to read 6, iclass 33, count 0 2006.201.06:23:16.36#ibcon#read 6, iclass 33, count 0 2006.201.06:23:16.36#ibcon#end of sib2, iclass 33, count 0 2006.201.06:23:16.36#ibcon#*after write, iclass 33, count 0 2006.201.06:23:16.36#ibcon#*before return 0, iclass 33, count 0 2006.201.06:23:16.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:16.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:23:16.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.06:23:16.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.06:23:16.36$vck44/vb=6,4 2006.201.06:23:16.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.06:23:16.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.06:23:16.36#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:16.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:16.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:16.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:16.41#ibcon#enter wrdev, iclass 35, count 2 2006.201.06:23:16.41#ibcon#first serial, iclass 35, count 2 2006.201.06:23:16.41#ibcon#enter sib2, iclass 35, count 2 2006.201.06:23:16.41#ibcon#flushed, iclass 35, count 2 2006.201.06:23:16.41#ibcon#about to write, iclass 35, count 2 2006.201.06:23:16.41#ibcon#wrote, iclass 35, count 2 2006.201.06:23:16.41#ibcon#about to read 3, iclass 35, count 2 2006.201.06:23:16.43#ibcon#read 3, iclass 35, count 2 2006.201.06:23:16.43#ibcon#about to read 4, iclass 35, count 2 2006.201.06:23:16.43#ibcon#read 4, iclass 35, count 2 2006.201.06:23:16.43#ibcon#about to read 5, iclass 35, count 2 2006.201.06:23:16.43#ibcon#read 5, iclass 35, count 2 2006.201.06:23:16.43#ibcon#about to read 6, iclass 35, count 2 2006.201.06:23:16.43#ibcon#read 6, iclass 35, count 2 2006.201.06:23:16.43#ibcon#end of sib2, iclass 35, count 2 2006.201.06:23:16.43#ibcon#*mode == 0, iclass 35, count 2 2006.201.06:23:16.43#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.06:23:16.43#ibcon#[27=AT06-04\r\n] 2006.201.06:23:16.43#ibcon#*before write, iclass 35, count 2 2006.201.06:23:16.43#ibcon#enter sib2, iclass 35, count 2 2006.201.06:23:16.43#ibcon#flushed, iclass 35, count 2 2006.201.06:23:16.43#ibcon#about to write, iclass 35, count 2 2006.201.06:23:16.43#ibcon#wrote, iclass 35, count 2 2006.201.06:23:16.43#ibcon#about to read 3, iclass 35, count 2 2006.201.06:23:16.46#ibcon#read 3, iclass 35, count 2 2006.201.06:23:16.46#ibcon#about to read 4, iclass 35, count 2 2006.201.06:23:16.46#ibcon#read 4, iclass 35, count 2 2006.201.06:23:16.46#ibcon#about to read 5, iclass 35, count 2 2006.201.06:23:16.46#ibcon#read 5, iclass 35, count 2 2006.201.06:23:16.46#ibcon#about to read 6, iclass 35, count 2 2006.201.06:23:16.46#ibcon#read 6, iclass 35, count 2 2006.201.06:23:16.46#ibcon#end of sib2, iclass 35, count 2 2006.201.06:23:16.46#ibcon#*after write, iclass 35, count 2 2006.201.06:23:16.46#ibcon#*before return 0, iclass 35, count 2 2006.201.06:23:16.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:16.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:23:16.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.06:23:16.46#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:16.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:16.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:16.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:16.58#ibcon#enter wrdev, iclass 35, count 0 2006.201.06:23:16.58#ibcon#first serial, iclass 35, count 0 2006.201.06:23:16.58#ibcon#enter sib2, iclass 35, count 0 2006.201.06:23:16.58#ibcon#flushed, iclass 35, count 0 2006.201.06:23:16.58#ibcon#about to write, iclass 35, count 0 2006.201.06:23:16.58#ibcon#wrote, iclass 35, count 0 2006.201.06:23:16.58#ibcon#about to read 3, iclass 35, count 0 2006.201.06:23:16.60#ibcon#read 3, iclass 35, count 0 2006.201.06:23:16.60#ibcon#about to read 4, iclass 35, count 0 2006.201.06:23:16.60#ibcon#read 4, iclass 35, count 0 2006.201.06:23:16.60#ibcon#about to read 5, iclass 35, count 0 2006.201.06:23:16.60#ibcon#read 5, iclass 35, count 0 2006.201.06:23:16.60#ibcon#about to read 6, iclass 35, count 0 2006.201.06:23:16.60#ibcon#read 6, iclass 35, count 0 2006.201.06:23:16.60#ibcon#end of sib2, iclass 35, count 0 2006.201.06:23:16.60#ibcon#*mode == 0, iclass 35, count 0 2006.201.06:23:16.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.06:23:16.60#ibcon#[27=USB\r\n] 2006.201.06:23:16.60#ibcon#*before write, iclass 35, count 0 2006.201.06:23:16.60#ibcon#enter sib2, iclass 35, count 0 2006.201.06:23:16.60#ibcon#flushed, iclass 35, count 0 2006.201.06:23:16.60#ibcon#about to write, iclass 35, count 0 2006.201.06:23:16.60#ibcon#wrote, iclass 35, count 0 2006.201.06:23:16.60#ibcon#about to read 3, iclass 35, count 0 2006.201.06:23:16.63#ibcon#read 3, iclass 35, count 0 2006.201.06:23:16.63#ibcon#about to read 4, iclass 35, count 0 2006.201.06:23:16.63#ibcon#read 4, iclass 35, count 0 2006.201.06:23:16.63#ibcon#about to read 5, iclass 35, count 0 2006.201.06:23:16.63#ibcon#read 5, iclass 35, count 0 2006.201.06:23:16.63#ibcon#about to read 6, iclass 35, count 0 2006.201.06:23:16.63#ibcon#read 6, iclass 35, count 0 2006.201.06:23:16.63#ibcon#end of sib2, iclass 35, count 0 2006.201.06:23:16.63#ibcon#*after write, iclass 35, count 0 2006.201.06:23:16.63#ibcon#*before return 0, iclass 35, count 0 2006.201.06:23:16.63#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:16.63#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:23:16.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.06:23:16.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.06:23:16.63$vck44/vblo=7,734.99 2006.201.06:23:16.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.06:23:16.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.06:23:16.63#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:16.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:16.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:16.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:16.63#ibcon#enter wrdev, iclass 37, count 0 2006.201.06:23:16.63#ibcon#first serial, iclass 37, count 0 2006.201.06:23:16.63#ibcon#enter sib2, iclass 37, count 0 2006.201.06:23:16.63#ibcon#flushed, iclass 37, count 0 2006.201.06:23:16.63#ibcon#about to write, iclass 37, count 0 2006.201.06:23:16.63#ibcon#wrote, iclass 37, count 0 2006.201.06:23:16.63#ibcon#about to read 3, iclass 37, count 0 2006.201.06:23:16.65#ibcon#read 3, iclass 37, count 0 2006.201.06:23:16.65#ibcon#about to read 4, iclass 37, count 0 2006.201.06:23:16.65#ibcon#read 4, iclass 37, count 0 2006.201.06:23:16.65#ibcon#about to read 5, iclass 37, count 0 2006.201.06:23:16.65#ibcon#read 5, iclass 37, count 0 2006.201.06:23:16.65#ibcon#about to read 6, iclass 37, count 0 2006.201.06:23:16.65#ibcon#read 6, iclass 37, count 0 2006.201.06:23:16.65#ibcon#end of sib2, iclass 37, count 0 2006.201.06:23:16.65#ibcon#*mode == 0, iclass 37, count 0 2006.201.06:23:16.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.06:23:16.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.06:23:16.65#ibcon#*before write, iclass 37, count 0 2006.201.06:23:16.65#ibcon#enter sib2, iclass 37, count 0 2006.201.06:23:16.65#ibcon#flushed, iclass 37, count 0 2006.201.06:23:16.65#ibcon#about to write, iclass 37, count 0 2006.201.06:23:16.65#ibcon#wrote, iclass 37, count 0 2006.201.06:23:16.65#ibcon#about to read 3, iclass 37, count 0 2006.201.06:23:16.69#ibcon#read 3, iclass 37, count 0 2006.201.06:23:16.69#ibcon#about to read 4, iclass 37, count 0 2006.201.06:23:16.69#ibcon#read 4, iclass 37, count 0 2006.201.06:23:16.69#ibcon#about to read 5, iclass 37, count 0 2006.201.06:23:16.69#ibcon#read 5, iclass 37, count 0 2006.201.06:23:16.69#ibcon#about to read 6, iclass 37, count 0 2006.201.06:23:16.69#ibcon#read 6, iclass 37, count 0 2006.201.06:23:16.69#ibcon#end of sib2, iclass 37, count 0 2006.201.06:23:16.69#ibcon#*after write, iclass 37, count 0 2006.201.06:23:16.69#ibcon#*before return 0, iclass 37, count 0 2006.201.06:23:16.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:16.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:23:16.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.06:23:16.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.06:23:16.69$vck44/vb=7,4 2006.201.06:23:16.69#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.06:23:16.69#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.06:23:16.69#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:16.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:16.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:16.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:16.75#ibcon#enter wrdev, iclass 39, count 2 2006.201.06:23:16.75#ibcon#first serial, iclass 39, count 2 2006.201.06:23:16.75#ibcon#enter sib2, iclass 39, count 2 2006.201.06:23:16.75#ibcon#flushed, iclass 39, count 2 2006.201.06:23:16.75#ibcon#about to write, iclass 39, count 2 2006.201.06:23:16.75#ibcon#wrote, iclass 39, count 2 2006.201.06:23:16.75#ibcon#about to read 3, iclass 39, count 2 2006.201.06:23:16.77#ibcon#read 3, iclass 39, count 2 2006.201.06:23:16.77#ibcon#about to read 4, iclass 39, count 2 2006.201.06:23:16.77#ibcon#read 4, iclass 39, count 2 2006.201.06:23:16.77#ibcon#about to read 5, iclass 39, count 2 2006.201.06:23:16.77#ibcon#read 5, iclass 39, count 2 2006.201.06:23:16.77#ibcon#about to read 6, iclass 39, count 2 2006.201.06:23:16.77#ibcon#read 6, iclass 39, count 2 2006.201.06:23:16.77#ibcon#end of sib2, iclass 39, count 2 2006.201.06:23:16.77#ibcon#*mode == 0, iclass 39, count 2 2006.201.06:23:16.77#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.06:23:16.77#ibcon#[27=AT07-04\r\n] 2006.201.06:23:16.77#ibcon#*before write, iclass 39, count 2 2006.201.06:23:16.77#ibcon#enter sib2, iclass 39, count 2 2006.201.06:23:16.77#ibcon#flushed, iclass 39, count 2 2006.201.06:23:16.77#ibcon#about to write, iclass 39, count 2 2006.201.06:23:16.77#ibcon#wrote, iclass 39, count 2 2006.201.06:23:16.77#ibcon#about to read 3, iclass 39, count 2 2006.201.06:23:16.80#ibcon#read 3, iclass 39, count 2 2006.201.06:23:16.80#ibcon#about to read 4, iclass 39, count 2 2006.201.06:23:16.80#ibcon#read 4, iclass 39, count 2 2006.201.06:23:16.80#ibcon#about to read 5, iclass 39, count 2 2006.201.06:23:16.80#ibcon#read 5, iclass 39, count 2 2006.201.06:23:16.80#ibcon#about to read 6, iclass 39, count 2 2006.201.06:23:16.80#ibcon#read 6, iclass 39, count 2 2006.201.06:23:16.80#ibcon#end of sib2, iclass 39, count 2 2006.201.06:23:16.80#ibcon#*after write, iclass 39, count 2 2006.201.06:23:16.80#ibcon#*before return 0, iclass 39, count 2 2006.201.06:23:16.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:16.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:23:16.80#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.06:23:16.80#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:16.80#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:16.92#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:16.92#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:16.92#ibcon#enter wrdev, iclass 39, count 0 2006.201.06:23:16.92#ibcon#first serial, iclass 39, count 0 2006.201.06:23:16.92#ibcon#enter sib2, iclass 39, count 0 2006.201.06:23:16.92#ibcon#flushed, iclass 39, count 0 2006.201.06:23:16.92#ibcon#about to write, iclass 39, count 0 2006.201.06:23:16.92#ibcon#wrote, iclass 39, count 0 2006.201.06:23:16.92#ibcon#about to read 3, iclass 39, count 0 2006.201.06:23:16.94#ibcon#read 3, iclass 39, count 0 2006.201.06:23:16.94#ibcon#about to read 4, iclass 39, count 0 2006.201.06:23:16.94#ibcon#read 4, iclass 39, count 0 2006.201.06:23:16.94#ibcon#about to read 5, iclass 39, count 0 2006.201.06:23:16.94#ibcon#read 5, iclass 39, count 0 2006.201.06:23:16.94#ibcon#about to read 6, iclass 39, count 0 2006.201.06:23:16.94#ibcon#read 6, iclass 39, count 0 2006.201.06:23:16.94#ibcon#end of sib2, iclass 39, count 0 2006.201.06:23:16.94#ibcon#*mode == 0, iclass 39, count 0 2006.201.06:23:16.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.06:23:16.94#ibcon#[27=USB\r\n] 2006.201.06:23:16.94#ibcon#*before write, iclass 39, count 0 2006.201.06:23:16.94#ibcon#enter sib2, iclass 39, count 0 2006.201.06:23:16.94#ibcon#flushed, iclass 39, count 0 2006.201.06:23:16.94#ibcon#about to write, iclass 39, count 0 2006.201.06:23:16.94#ibcon#wrote, iclass 39, count 0 2006.201.06:23:16.94#ibcon#about to read 3, iclass 39, count 0 2006.201.06:23:16.97#ibcon#read 3, iclass 39, count 0 2006.201.06:23:16.97#ibcon#about to read 4, iclass 39, count 0 2006.201.06:23:16.97#ibcon#read 4, iclass 39, count 0 2006.201.06:23:16.97#ibcon#about to read 5, iclass 39, count 0 2006.201.06:23:16.97#ibcon#read 5, iclass 39, count 0 2006.201.06:23:16.97#ibcon#about to read 6, iclass 39, count 0 2006.201.06:23:16.97#ibcon#read 6, iclass 39, count 0 2006.201.06:23:16.97#ibcon#end of sib2, iclass 39, count 0 2006.201.06:23:16.97#ibcon#*after write, iclass 39, count 0 2006.201.06:23:16.97#ibcon#*before return 0, iclass 39, count 0 2006.201.06:23:16.97#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:16.97#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:23:16.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.06:23:16.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.06:23:16.97$vck44/vblo=8,744.99 2006.201.06:23:16.97#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.06:23:16.97#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.06:23:16.97#ibcon#ireg 17 cls_cnt 0 2006.201.06:23:16.97#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:16.97#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:16.97#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:16.97#ibcon#enter wrdev, iclass 2, count 0 2006.201.06:23:16.97#ibcon#first serial, iclass 2, count 0 2006.201.06:23:16.97#ibcon#enter sib2, iclass 2, count 0 2006.201.06:23:16.97#ibcon#flushed, iclass 2, count 0 2006.201.06:23:16.97#ibcon#about to write, iclass 2, count 0 2006.201.06:23:16.97#ibcon#wrote, iclass 2, count 0 2006.201.06:23:16.97#ibcon#about to read 3, iclass 2, count 0 2006.201.06:23:16.99#ibcon#read 3, iclass 2, count 0 2006.201.06:23:16.99#ibcon#about to read 4, iclass 2, count 0 2006.201.06:23:16.99#ibcon#read 4, iclass 2, count 0 2006.201.06:23:16.99#ibcon#about to read 5, iclass 2, count 0 2006.201.06:23:16.99#ibcon#read 5, iclass 2, count 0 2006.201.06:23:16.99#ibcon#about to read 6, iclass 2, count 0 2006.201.06:23:16.99#ibcon#read 6, iclass 2, count 0 2006.201.06:23:16.99#ibcon#end of sib2, iclass 2, count 0 2006.201.06:23:16.99#ibcon#*mode == 0, iclass 2, count 0 2006.201.06:23:16.99#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.06:23:16.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.06:23:16.99#ibcon#*before write, iclass 2, count 0 2006.201.06:23:16.99#ibcon#enter sib2, iclass 2, count 0 2006.201.06:23:16.99#ibcon#flushed, iclass 2, count 0 2006.201.06:23:16.99#ibcon#about to write, iclass 2, count 0 2006.201.06:23:16.99#ibcon#wrote, iclass 2, count 0 2006.201.06:23:16.99#ibcon#about to read 3, iclass 2, count 0 2006.201.06:23:17.04#ibcon#read 3, iclass 2, count 0 2006.201.06:23:17.04#ibcon#about to read 4, iclass 2, count 0 2006.201.06:23:17.04#ibcon#read 4, iclass 2, count 0 2006.201.06:23:17.04#ibcon#about to read 5, iclass 2, count 0 2006.201.06:23:17.04#ibcon#read 5, iclass 2, count 0 2006.201.06:23:17.04#ibcon#about to read 6, iclass 2, count 0 2006.201.06:23:17.04#ibcon#read 6, iclass 2, count 0 2006.201.06:23:17.04#ibcon#end of sib2, iclass 2, count 0 2006.201.06:23:17.04#ibcon#*after write, iclass 2, count 0 2006.201.06:23:17.04#ibcon#*before return 0, iclass 2, count 0 2006.201.06:23:17.04#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:17.04#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:23:17.04#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.06:23:17.04#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.06:23:17.04$vck44/vb=8,4 2006.201.06:23:17.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.06:23:17.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.06:23:17.04#ibcon#ireg 11 cls_cnt 2 2006.201.06:23:17.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:17.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:17.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:17.09#ibcon#enter wrdev, iclass 5, count 2 2006.201.06:23:17.09#ibcon#first serial, iclass 5, count 2 2006.201.06:23:17.09#ibcon#enter sib2, iclass 5, count 2 2006.201.06:23:17.09#ibcon#flushed, iclass 5, count 2 2006.201.06:23:17.09#ibcon#about to write, iclass 5, count 2 2006.201.06:23:17.09#ibcon#wrote, iclass 5, count 2 2006.201.06:23:17.09#ibcon#about to read 3, iclass 5, count 2 2006.201.06:23:17.11#ibcon#read 3, iclass 5, count 2 2006.201.06:23:17.11#ibcon#about to read 4, iclass 5, count 2 2006.201.06:23:17.11#ibcon#read 4, iclass 5, count 2 2006.201.06:23:17.11#ibcon#about to read 5, iclass 5, count 2 2006.201.06:23:17.11#ibcon#read 5, iclass 5, count 2 2006.201.06:23:17.11#ibcon#about to read 6, iclass 5, count 2 2006.201.06:23:17.11#ibcon#read 6, iclass 5, count 2 2006.201.06:23:17.11#ibcon#end of sib2, iclass 5, count 2 2006.201.06:23:17.11#ibcon#*mode == 0, iclass 5, count 2 2006.201.06:23:17.11#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.06:23:17.11#ibcon#[27=AT08-04\r\n] 2006.201.06:23:17.11#ibcon#*before write, iclass 5, count 2 2006.201.06:23:17.11#ibcon#enter sib2, iclass 5, count 2 2006.201.06:23:17.11#ibcon#flushed, iclass 5, count 2 2006.201.06:23:17.11#ibcon#about to write, iclass 5, count 2 2006.201.06:23:17.11#ibcon#wrote, iclass 5, count 2 2006.201.06:23:17.11#ibcon#about to read 3, iclass 5, count 2 2006.201.06:23:17.14#ibcon#read 3, iclass 5, count 2 2006.201.06:23:17.14#ibcon#about to read 4, iclass 5, count 2 2006.201.06:23:17.14#ibcon#read 4, iclass 5, count 2 2006.201.06:23:17.14#ibcon#about to read 5, iclass 5, count 2 2006.201.06:23:17.14#ibcon#read 5, iclass 5, count 2 2006.201.06:23:17.14#ibcon#about to read 6, iclass 5, count 2 2006.201.06:23:17.14#ibcon#read 6, iclass 5, count 2 2006.201.06:23:17.14#ibcon#end of sib2, iclass 5, count 2 2006.201.06:23:17.14#ibcon#*after write, iclass 5, count 2 2006.201.06:23:17.14#ibcon#*before return 0, iclass 5, count 2 2006.201.06:23:17.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:17.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:23:17.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.06:23:17.14#ibcon#ireg 7 cls_cnt 0 2006.201.06:23:17.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:17.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:17.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:17.26#ibcon#enter wrdev, iclass 5, count 0 2006.201.06:23:17.26#ibcon#first serial, iclass 5, count 0 2006.201.06:23:17.26#ibcon#enter sib2, iclass 5, count 0 2006.201.06:23:17.26#ibcon#flushed, iclass 5, count 0 2006.201.06:23:17.26#ibcon#about to write, iclass 5, count 0 2006.201.06:23:17.26#ibcon#wrote, iclass 5, count 0 2006.201.06:23:17.26#ibcon#about to read 3, iclass 5, count 0 2006.201.06:23:17.28#ibcon#read 3, iclass 5, count 0 2006.201.06:23:17.28#ibcon#about to read 4, iclass 5, count 0 2006.201.06:23:17.28#ibcon#read 4, iclass 5, count 0 2006.201.06:23:17.28#ibcon#about to read 5, iclass 5, count 0 2006.201.06:23:17.28#ibcon#read 5, iclass 5, count 0 2006.201.06:23:17.28#ibcon#about to read 6, iclass 5, count 0 2006.201.06:23:17.28#ibcon#read 6, iclass 5, count 0 2006.201.06:23:17.28#ibcon#end of sib2, iclass 5, count 0 2006.201.06:23:17.28#ibcon#*mode == 0, iclass 5, count 0 2006.201.06:23:17.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.06:23:17.28#ibcon#[27=USB\r\n] 2006.201.06:23:17.28#ibcon#*before write, iclass 5, count 0 2006.201.06:23:17.28#ibcon#enter sib2, iclass 5, count 0 2006.201.06:23:17.28#ibcon#flushed, iclass 5, count 0 2006.201.06:23:17.28#ibcon#about to write, iclass 5, count 0 2006.201.06:23:17.28#ibcon#wrote, iclass 5, count 0 2006.201.06:23:17.28#ibcon#about to read 3, iclass 5, count 0 2006.201.06:23:17.31#ibcon#read 3, iclass 5, count 0 2006.201.06:23:17.31#ibcon#about to read 4, iclass 5, count 0 2006.201.06:23:17.31#ibcon#read 4, iclass 5, count 0 2006.201.06:23:17.31#ibcon#about to read 5, iclass 5, count 0 2006.201.06:23:17.31#ibcon#read 5, iclass 5, count 0 2006.201.06:23:17.31#ibcon#about to read 6, iclass 5, count 0 2006.201.06:23:17.31#ibcon#read 6, iclass 5, count 0 2006.201.06:23:17.31#ibcon#end of sib2, iclass 5, count 0 2006.201.06:23:17.31#ibcon#*after write, iclass 5, count 0 2006.201.06:23:17.31#ibcon#*before return 0, iclass 5, count 0 2006.201.06:23:17.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:17.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:23:17.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.06:23:17.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.06:23:17.31$vck44/vabw=wide 2006.201.06:23:17.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.06:23:17.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.06:23:17.31#ibcon#ireg 8 cls_cnt 0 2006.201.06:23:17.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:17.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:17.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:17.31#ibcon#enter wrdev, iclass 7, count 0 2006.201.06:23:17.31#ibcon#first serial, iclass 7, count 0 2006.201.06:23:17.31#ibcon#enter sib2, iclass 7, count 0 2006.201.06:23:17.31#ibcon#flushed, iclass 7, count 0 2006.201.06:23:17.31#ibcon#about to write, iclass 7, count 0 2006.201.06:23:17.31#ibcon#wrote, iclass 7, count 0 2006.201.06:23:17.31#ibcon#about to read 3, iclass 7, count 0 2006.201.06:23:17.33#ibcon#read 3, iclass 7, count 0 2006.201.06:23:17.33#ibcon#about to read 4, iclass 7, count 0 2006.201.06:23:17.33#ibcon#read 4, iclass 7, count 0 2006.201.06:23:17.33#ibcon#about to read 5, iclass 7, count 0 2006.201.06:23:17.33#ibcon#read 5, iclass 7, count 0 2006.201.06:23:17.33#ibcon#about to read 6, iclass 7, count 0 2006.201.06:23:17.33#ibcon#read 6, iclass 7, count 0 2006.201.06:23:17.33#ibcon#end of sib2, iclass 7, count 0 2006.201.06:23:17.33#ibcon#*mode == 0, iclass 7, count 0 2006.201.06:23:17.33#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.06:23:17.33#ibcon#[25=BW32\r\n] 2006.201.06:23:17.33#ibcon#*before write, iclass 7, count 0 2006.201.06:23:17.33#ibcon#enter sib2, iclass 7, count 0 2006.201.06:23:17.33#ibcon#flushed, iclass 7, count 0 2006.201.06:23:17.33#ibcon#about to write, iclass 7, count 0 2006.201.06:23:17.33#ibcon#wrote, iclass 7, count 0 2006.201.06:23:17.33#ibcon#about to read 3, iclass 7, count 0 2006.201.06:23:17.37#ibcon#read 3, iclass 7, count 0 2006.201.06:23:17.37#ibcon#about to read 4, iclass 7, count 0 2006.201.06:23:17.37#ibcon#read 4, iclass 7, count 0 2006.201.06:23:17.37#ibcon#about to read 5, iclass 7, count 0 2006.201.06:23:17.37#ibcon#read 5, iclass 7, count 0 2006.201.06:23:17.37#ibcon#about to read 6, iclass 7, count 0 2006.201.06:23:17.37#ibcon#read 6, iclass 7, count 0 2006.201.06:23:17.37#ibcon#end of sib2, iclass 7, count 0 2006.201.06:23:17.37#ibcon#*after write, iclass 7, count 0 2006.201.06:23:17.37#ibcon#*before return 0, iclass 7, count 0 2006.201.06:23:17.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:17.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:23:17.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.06:23:17.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.06:23:17.37$vck44/vbbw=wide 2006.201.06:23:17.37#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.06:23:17.37#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.06:23:17.37#ibcon#ireg 8 cls_cnt 0 2006.201.06:23:17.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:23:17.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:23:17.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:23:17.43#ibcon#enter wrdev, iclass 11, count 0 2006.201.06:23:17.43#ibcon#first serial, iclass 11, count 0 2006.201.06:23:17.43#ibcon#enter sib2, iclass 11, count 0 2006.201.06:23:17.43#ibcon#flushed, iclass 11, count 0 2006.201.06:23:17.43#ibcon#about to write, iclass 11, count 0 2006.201.06:23:17.43#ibcon#wrote, iclass 11, count 0 2006.201.06:23:17.43#ibcon#about to read 3, iclass 11, count 0 2006.201.06:23:17.45#ibcon#read 3, iclass 11, count 0 2006.201.06:23:17.45#ibcon#about to read 4, iclass 11, count 0 2006.201.06:23:17.45#ibcon#read 4, iclass 11, count 0 2006.201.06:23:17.45#ibcon#about to read 5, iclass 11, count 0 2006.201.06:23:17.45#ibcon#read 5, iclass 11, count 0 2006.201.06:23:17.45#ibcon#about to read 6, iclass 11, count 0 2006.201.06:23:17.45#ibcon#read 6, iclass 11, count 0 2006.201.06:23:17.45#ibcon#end of sib2, iclass 11, count 0 2006.201.06:23:17.45#ibcon#*mode == 0, iclass 11, count 0 2006.201.06:23:17.45#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.06:23:17.45#ibcon#[27=BW32\r\n] 2006.201.06:23:17.45#ibcon#*before write, iclass 11, count 0 2006.201.06:23:17.45#ibcon#enter sib2, iclass 11, count 0 2006.201.06:23:17.45#ibcon#flushed, iclass 11, count 0 2006.201.06:23:17.45#ibcon#about to write, iclass 11, count 0 2006.201.06:23:17.45#ibcon#wrote, iclass 11, count 0 2006.201.06:23:17.45#ibcon#about to read 3, iclass 11, count 0 2006.201.06:23:17.48#ibcon#read 3, iclass 11, count 0 2006.201.06:23:17.48#ibcon#about to read 4, iclass 11, count 0 2006.201.06:23:17.48#ibcon#read 4, iclass 11, count 0 2006.201.06:23:17.48#ibcon#about to read 5, iclass 11, count 0 2006.201.06:23:17.48#ibcon#read 5, iclass 11, count 0 2006.201.06:23:17.48#ibcon#about to read 6, iclass 11, count 0 2006.201.06:23:17.48#ibcon#read 6, iclass 11, count 0 2006.201.06:23:17.48#ibcon#end of sib2, iclass 11, count 0 2006.201.06:23:17.48#ibcon#*after write, iclass 11, count 0 2006.201.06:23:17.48#ibcon#*before return 0, iclass 11, count 0 2006.201.06:23:17.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:23:17.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:23:17.48#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.06:23:17.48#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.06:23:17.48$setupk4/ifdk4 2006.201.06:23:17.48$ifdk4/lo= 2006.201.06:23:17.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.06:23:17.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.06:23:17.48$ifdk4/patch= 2006.201.06:23:17.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.06:23:17.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.06:23:17.48$setupk4/!*+20s 2006.201.06:23:20.29#abcon#<5=/04 2.7 4.7 23.00 881003.3\r\n> 2006.201.06:23:20.31#abcon#{5=INTERFACE CLEAR} 2006.201.06:23:20.37#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:23:30.46#abcon#<5=/04 2.7 4.7 23.00 881003.3\r\n> 2006.201.06:23:30.48#abcon#{5=INTERFACE CLEAR} 2006.201.06:23:30.54#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:23:31.14#trakl#Source acquired 2006.201.06:23:31.94$setupk4/"tpicd 2006.201.06:23:31.94$setupk4/echo=off 2006.201.06:23:31.94$setupk4/xlog=off 2006.201.06:23:31.94:!2006.201.06:29:43 2006.201.06:23:32.14#flagr#flagr/antenna,acquired 2006.201.06:29:43.00:preob 2006.201.06:29:43.14/onsource/TRACKING 2006.201.06:29:43.14:!2006.201.06:29:53 2006.201.06:29:53.00:"tape 2006.201.06:29:53.00:"st=record 2006.201.06:29:53.00:data_valid=on 2006.201.06:29:53.00:midob 2006.201.06:29:54.14/onsource/TRACKING 2006.201.06:29:54.14/wx/23.07,1003.3,87 2006.201.06:29:54.32/cable/+6.4664E-03 2006.201.06:29:55.41/va/01,08,usb,yes,28,30 2006.201.06:29:55.41/va/02,07,usb,yes,30,31 2006.201.06:29:55.41/va/03,08,usb,yes,27,28 2006.201.06:29:55.41/va/04,07,usb,yes,31,32 2006.201.06:29:55.41/va/05,04,usb,yes,27,28 2006.201.06:29:55.41/va/06,05,usb,yes,27,27 2006.201.06:29:55.41/va/07,05,usb,yes,26,28 2006.201.06:29:55.41/va/08,04,usb,yes,26,32 2006.201.06:29:55.64/valo/01,524.99,yes,locked 2006.201.06:29:55.64/valo/02,534.99,yes,locked 2006.201.06:29:55.64/valo/03,564.99,yes,locked 2006.201.06:29:55.64/valo/04,624.99,yes,locked 2006.201.06:29:55.64/valo/05,734.99,yes,locked 2006.201.06:29:55.64/valo/06,814.99,yes,locked 2006.201.06:29:55.64/valo/07,864.99,yes,locked 2006.201.06:29:55.64/valo/08,884.99,yes,locked 2006.201.06:29:56.73/vb/01,04,usb,yes,28,26 2006.201.06:29:56.73/vb/02,05,usb,yes,26,26 2006.201.06:29:56.73/vb/03,04,usb,yes,27,30 2006.201.06:29:56.73/vb/04,05,usb,yes,27,26 2006.201.06:29:56.73/vb/05,04,usb,yes,24,26 2006.201.06:29:56.73/vb/06,04,usb,yes,28,25 2006.201.06:29:56.73/vb/07,04,usb,yes,28,28 2006.201.06:29:56.73/vb/08,04,usb,yes,26,29 2006.201.06:29:56.97/vblo/01,629.99,yes,locked 2006.201.06:29:56.97/vblo/02,634.99,yes,locked 2006.201.06:29:56.97/vblo/03,649.99,yes,locked 2006.201.06:29:56.97/vblo/04,679.99,yes,locked 2006.201.06:29:56.97/vblo/05,709.99,yes,locked 2006.201.06:29:56.97/vblo/06,719.99,yes,locked 2006.201.06:29:56.97/vblo/07,734.99,yes,locked 2006.201.06:29:56.97/vblo/08,744.99,yes,locked 2006.201.06:29:57.12/vabw/8 2006.201.06:29:57.27/vbbw/8 2006.201.06:29:57.38/xfe/off,on,15.5 2006.201.06:29:57.75/ifatt/23,28,28,28 2006.201.06:29:58.05/fmout-gps/S +4.50E-07 2006.201.06:29:58.13:!2006.201.06:35:43 2006.201.06:35:43.00:data_valid=off 2006.201.06:35:43.00:"et 2006.201.06:35:43.00:!+3s 2006.201.06:35:46.02:"tape 2006.201.06:35:46.02:postob 2006.201.06:35:46.12/cable/+6.4642E-03 2006.201.06:35:46.12/wx/23.18,1003.3,87 2006.201.06:35:46.18/fmout-gps/S +4.52E-07 2006.201.06:35:46.18:scan_name=201-0643,jd0607,100 2006.201.06:35:46.18:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.201.06:35:48.13#flagr#flagr/antenna,new-source 2006.201.06:35:48.13:checkk5 2006.201.06:35:48.58/chk_autoobs//k5ts1/ autoobs is running! 2006.201.06:35:48.96/chk_autoobs//k5ts2/ autoobs is running! 2006.201.06:35:49.35/chk_autoobs//k5ts3/ autoobs is running! 2006.201.06:35:49.75/chk_autoobs//k5ts4/ autoobs is running! 2006.201.06:35:50.12/chk_obsdata//k5ts1/T2010629??a.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.201.06:35:50.49/chk_obsdata//k5ts2/T2010629??b.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.201.06:35:50.86/chk_obsdata//k5ts3/T2010629??c.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.201.06:35:51.24/chk_obsdata//k5ts4/T2010629??d.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.201.06:35:51.92/k5log//k5ts1_log_newline 2006.201.06:35:52.62/k5log//k5ts2_log_newline 2006.201.06:35:53.31/k5log//k5ts3_log_newline 2006.201.06:35:54.01/k5log//k5ts4_log_newline 2006.201.06:35:54.04/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.06:35:54.04:setupk4=1 2006.201.06:35:54.04$setupk4/echo=on 2006.201.06:35:54.04$setupk4/pcalon 2006.201.06:35:54.04$pcalon/"no phase cal control is implemented here 2006.201.06:35:54.04$setupk4/"tpicd=stop 2006.201.06:35:54.04$setupk4/"rec=synch_on 2006.201.06:35:54.04$setupk4/"rec_mode=128 2006.201.06:35:54.04$setupk4/!* 2006.201.06:35:54.04$setupk4/recpk4 2006.201.06:35:54.04$recpk4/recpatch= 2006.201.06:35:54.04$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.06:35:54.04$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.06:35:54.04$setupk4/vck44 2006.201.06:35:54.04$vck44/valo=1,524.99 2006.201.06:35:54.04#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.06:35:54.04#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.06:35:54.04#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:54.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:54.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:54.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:54.04#ibcon#enter wrdev, iclass 28, count 0 2006.201.06:35:54.04#ibcon#first serial, iclass 28, count 0 2006.201.06:35:54.04#ibcon#enter sib2, iclass 28, count 0 2006.201.06:35:54.04#ibcon#flushed, iclass 28, count 0 2006.201.06:35:54.04#ibcon#about to write, iclass 28, count 0 2006.201.06:35:54.05#ibcon#wrote, iclass 28, count 0 2006.201.06:35:54.05#ibcon#about to read 3, iclass 28, count 0 2006.201.06:35:54.08#ibcon#read 3, iclass 28, count 0 2006.201.06:35:54.08#ibcon#about to read 4, iclass 28, count 0 2006.201.06:35:54.08#ibcon#read 4, iclass 28, count 0 2006.201.06:35:54.08#ibcon#about to read 5, iclass 28, count 0 2006.201.06:35:54.08#ibcon#read 5, iclass 28, count 0 2006.201.06:35:54.08#ibcon#about to read 6, iclass 28, count 0 2006.201.06:35:54.08#ibcon#read 6, iclass 28, count 0 2006.201.06:35:54.08#ibcon#end of sib2, iclass 28, count 0 2006.201.06:35:54.08#ibcon#*mode == 0, iclass 28, count 0 2006.201.06:35:54.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.06:35:54.08#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.06:35:54.08#ibcon#*before write, iclass 28, count 0 2006.201.06:35:54.08#ibcon#enter sib2, iclass 28, count 0 2006.201.06:35:54.08#ibcon#flushed, iclass 28, count 0 2006.201.06:35:54.08#ibcon#about to write, iclass 28, count 0 2006.201.06:35:54.08#ibcon#wrote, iclass 28, count 0 2006.201.06:35:54.08#ibcon#about to read 3, iclass 28, count 0 2006.201.06:35:54.13#ibcon#read 3, iclass 28, count 0 2006.201.06:35:54.13#ibcon#about to read 4, iclass 28, count 0 2006.201.06:35:54.13#ibcon#read 4, iclass 28, count 0 2006.201.06:35:54.13#ibcon#about to read 5, iclass 28, count 0 2006.201.06:35:54.13#ibcon#read 5, iclass 28, count 0 2006.201.06:35:54.13#ibcon#about to read 6, iclass 28, count 0 2006.201.06:35:54.13#ibcon#read 6, iclass 28, count 0 2006.201.06:35:54.13#ibcon#end of sib2, iclass 28, count 0 2006.201.06:35:54.13#ibcon#*after write, iclass 28, count 0 2006.201.06:35:54.13#ibcon#*before return 0, iclass 28, count 0 2006.201.06:35:54.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:54.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:54.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.06:35:54.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.06:35:54.13$vck44/va=1,8 2006.201.06:35:54.13#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.06:35:54.13#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.06:35:54.13#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:54.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:54.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:54.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:54.13#ibcon#enter wrdev, iclass 30, count 2 2006.201.06:35:54.13#ibcon#first serial, iclass 30, count 2 2006.201.06:35:54.13#ibcon#enter sib2, iclass 30, count 2 2006.201.06:35:54.13#ibcon#flushed, iclass 30, count 2 2006.201.06:35:54.13#ibcon#about to write, iclass 30, count 2 2006.201.06:35:54.13#ibcon#wrote, iclass 30, count 2 2006.201.06:35:54.13#ibcon#about to read 3, iclass 30, count 2 2006.201.06:35:54.15#ibcon#read 3, iclass 30, count 2 2006.201.06:35:54.15#ibcon#about to read 4, iclass 30, count 2 2006.201.06:35:54.15#ibcon#read 4, iclass 30, count 2 2006.201.06:35:54.15#ibcon#about to read 5, iclass 30, count 2 2006.201.06:35:54.15#ibcon#read 5, iclass 30, count 2 2006.201.06:35:54.15#ibcon#about to read 6, iclass 30, count 2 2006.201.06:35:54.15#ibcon#read 6, iclass 30, count 2 2006.201.06:35:54.15#ibcon#end of sib2, iclass 30, count 2 2006.201.06:35:54.15#ibcon#*mode == 0, iclass 30, count 2 2006.201.06:35:54.15#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.06:35:54.15#ibcon#[25=AT01-08\r\n] 2006.201.06:35:54.15#ibcon#*before write, iclass 30, count 2 2006.201.06:35:54.15#ibcon#enter sib2, iclass 30, count 2 2006.201.06:35:54.15#ibcon#flushed, iclass 30, count 2 2006.201.06:35:54.15#ibcon#about to write, iclass 30, count 2 2006.201.06:35:54.15#ibcon#wrote, iclass 30, count 2 2006.201.06:35:54.15#ibcon#about to read 3, iclass 30, count 2 2006.201.06:35:54.19#ibcon#read 3, iclass 30, count 2 2006.201.06:35:54.19#ibcon#about to read 4, iclass 30, count 2 2006.201.06:35:54.19#ibcon#read 4, iclass 30, count 2 2006.201.06:35:54.19#ibcon#about to read 5, iclass 30, count 2 2006.201.06:35:54.19#ibcon#read 5, iclass 30, count 2 2006.201.06:35:54.19#ibcon#about to read 6, iclass 30, count 2 2006.201.06:35:54.19#ibcon#read 6, iclass 30, count 2 2006.201.06:35:54.19#ibcon#end of sib2, iclass 30, count 2 2006.201.06:35:54.19#ibcon#*after write, iclass 30, count 2 2006.201.06:35:54.19#ibcon#*before return 0, iclass 30, count 2 2006.201.06:35:54.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:54.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:54.19#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.06:35:54.19#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:54.19#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:54.31#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:54.31#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:54.31#ibcon#enter wrdev, iclass 30, count 0 2006.201.06:35:54.31#ibcon#first serial, iclass 30, count 0 2006.201.06:35:54.31#ibcon#enter sib2, iclass 30, count 0 2006.201.06:35:54.31#ibcon#flushed, iclass 30, count 0 2006.201.06:35:54.31#ibcon#about to write, iclass 30, count 0 2006.201.06:35:54.31#ibcon#wrote, iclass 30, count 0 2006.201.06:35:54.31#ibcon#about to read 3, iclass 30, count 0 2006.201.06:35:54.33#ibcon#read 3, iclass 30, count 0 2006.201.06:35:54.33#ibcon#about to read 4, iclass 30, count 0 2006.201.06:35:54.33#ibcon#read 4, iclass 30, count 0 2006.201.06:35:54.33#ibcon#about to read 5, iclass 30, count 0 2006.201.06:35:54.33#ibcon#read 5, iclass 30, count 0 2006.201.06:35:54.33#ibcon#about to read 6, iclass 30, count 0 2006.201.06:35:54.33#ibcon#read 6, iclass 30, count 0 2006.201.06:35:54.33#ibcon#end of sib2, iclass 30, count 0 2006.201.06:35:54.33#ibcon#*mode == 0, iclass 30, count 0 2006.201.06:35:54.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.06:35:54.33#ibcon#[25=USB\r\n] 2006.201.06:35:54.33#ibcon#*before write, iclass 30, count 0 2006.201.06:35:54.33#ibcon#enter sib2, iclass 30, count 0 2006.201.06:35:54.33#ibcon#flushed, iclass 30, count 0 2006.201.06:35:54.33#ibcon#about to write, iclass 30, count 0 2006.201.06:35:54.33#ibcon#wrote, iclass 30, count 0 2006.201.06:35:54.33#ibcon#about to read 3, iclass 30, count 0 2006.201.06:35:54.36#ibcon#read 3, iclass 30, count 0 2006.201.06:35:54.36#ibcon#about to read 4, iclass 30, count 0 2006.201.06:35:54.36#ibcon#read 4, iclass 30, count 0 2006.201.06:35:54.36#ibcon#about to read 5, iclass 30, count 0 2006.201.06:35:54.36#ibcon#read 5, iclass 30, count 0 2006.201.06:35:54.36#ibcon#about to read 6, iclass 30, count 0 2006.201.06:35:54.36#ibcon#read 6, iclass 30, count 0 2006.201.06:35:54.36#ibcon#end of sib2, iclass 30, count 0 2006.201.06:35:54.36#ibcon#*after write, iclass 30, count 0 2006.201.06:35:54.36#ibcon#*before return 0, iclass 30, count 0 2006.201.06:35:54.36#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:54.36#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:54.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.06:35:54.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.06:35:54.36$vck44/valo=2,534.99 2006.201.06:35:54.36#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.06:35:54.36#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.06:35:54.36#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:54.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:54.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:54.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:54.36#ibcon#enter wrdev, iclass 32, count 0 2006.201.06:35:54.36#ibcon#first serial, iclass 32, count 0 2006.201.06:35:54.36#ibcon#enter sib2, iclass 32, count 0 2006.201.06:35:54.36#ibcon#flushed, iclass 32, count 0 2006.201.06:35:54.36#ibcon#about to write, iclass 32, count 0 2006.201.06:35:54.36#ibcon#wrote, iclass 32, count 0 2006.201.06:35:54.36#ibcon#about to read 3, iclass 32, count 0 2006.201.06:35:54.38#ibcon#read 3, iclass 32, count 0 2006.201.06:35:54.38#ibcon#about to read 4, iclass 32, count 0 2006.201.06:35:54.38#ibcon#read 4, iclass 32, count 0 2006.201.06:35:54.38#ibcon#about to read 5, iclass 32, count 0 2006.201.06:35:54.38#ibcon#read 5, iclass 32, count 0 2006.201.06:35:54.38#ibcon#about to read 6, iclass 32, count 0 2006.201.06:35:54.38#ibcon#read 6, iclass 32, count 0 2006.201.06:35:54.38#ibcon#end of sib2, iclass 32, count 0 2006.201.06:35:54.38#ibcon#*mode == 0, iclass 32, count 0 2006.201.06:35:54.38#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.06:35:54.38#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.06:35:54.38#ibcon#*before write, iclass 32, count 0 2006.201.06:35:54.38#ibcon#enter sib2, iclass 32, count 0 2006.201.06:35:54.38#ibcon#flushed, iclass 32, count 0 2006.201.06:35:54.38#ibcon#about to write, iclass 32, count 0 2006.201.06:35:54.38#ibcon#wrote, iclass 32, count 0 2006.201.06:35:54.38#ibcon#about to read 3, iclass 32, count 0 2006.201.06:35:54.43#ibcon#read 3, iclass 32, count 0 2006.201.06:35:54.43#ibcon#about to read 4, iclass 32, count 0 2006.201.06:35:54.43#ibcon#read 4, iclass 32, count 0 2006.201.06:35:54.43#ibcon#about to read 5, iclass 32, count 0 2006.201.06:35:54.43#ibcon#read 5, iclass 32, count 0 2006.201.06:35:54.43#ibcon#about to read 6, iclass 32, count 0 2006.201.06:35:54.43#ibcon#read 6, iclass 32, count 0 2006.201.06:35:54.43#ibcon#end of sib2, iclass 32, count 0 2006.201.06:35:54.43#ibcon#*after write, iclass 32, count 0 2006.201.06:35:54.43#ibcon#*before return 0, iclass 32, count 0 2006.201.06:35:54.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:54.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:54.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.06:35:54.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.06:35:54.43$vck44/va=2,7 2006.201.06:35:54.43#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.06:35:54.43#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.06:35:54.43#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:54.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:54.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:54.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:54.48#ibcon#enter wrdev, iclass 34, count 2 2006.201.06:35:54.48#ibcon#first serial, iclass 34, count 2 2006.201.06:35:54.48#ibcon#enter sib2, iclass 34, count 2 2006.201.06:35:54.48#ibcon#flushed, iclass 34, count 2 2006.201.06:35:54.48#ibcon#about to write, iclass 34, count 2 2006.201.06:35:54.48#ibcon#wrote, iclass 34, count 2 2006.201.06:35:54.48#ibcon#about to read 3, iclass 34, count 2 2006.201.06:35:54.50#ibcon#read 3, iclass 34, count 2 2006.201.06:35:54.50#ibcon#about to read 4, iclass 34, count 2 2006.201.06:35:54.50#ibcon#read 4, iclass 34, count 2 2006.201.06:35:54.50#ibcon#about to read 5, iclass 34, count 2 2006.201.06:35:54.50#ibcon#read 5, iclass 34, count 2 2006.201.06:35:54.50#ibcon#about to read 6, iclass 34, count 2 2006.201.06:35:54.50#ibcon#read 6, iclass 34, count 2 2006.201.06:35:54.50#ibcon#end of sib2, iclass 34, count 2 2006.201.06:35:54.50#ibcon#*mode == 0, iclass 34, count 2 2006.201.06:35:54.50#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.06:35:54.50#ibcon#[25=AT02-07\r\n] 2006.201.06:35:54.50#ibcon#*before write, iclass 34, count 2 2006.201.06:35:54.50#ibcon#enter sib2, iclass 34, count 2 2006.201.06:35:54.50#ibcon#flushed, iclass 34, count 2 2006.201.06:35:54.50#ibcon#about to write, iclass 34, count 2 2006.201.06:35:54.50#ibcon#wrote, iclass 34, count 2 2006.201.06:35:54.50#ibcon#about to read 3, iclass 34, count 2 2006.201.06:35:54.53#ibcon#read 3, iclass 34, count 2 2006.201.06:35:54.53#ibcon#about to read 4, iclass 34, count 2 2006.201.06:35:54.53#ibcon#read 4, iclass 34, count 2 2006.201.06:35:54.53#ibcon#about to read 5, iclass 34, count 2 2006.201.06:35:54.53#ibcon#read 5, iclass 34, count 2 2006.201.06:35:54.53#ibcon#about to read 6, iclass 34, count 2 2006.201.06:35:54.53#ibcon#read 6, iclass 34, count 2 2006.201.06:35:54.53#ibcon#end of sib2, iclass 34, count 2 2006.201.06:35:54.53#ibcon#*after write, iclass 34, count 2 2006.201.06:35:54.53#ibcon#*before return 0, iclass 34, count 2 2006.201.06:35:54.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:54.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:54.53#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.06:35:54.53#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:54.53#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:54.65#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:54.65#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:54.65#ibcon#enter wrdev, iclass 34, count 0 2006.201.06:35:54.65#ibcon#first serial, iclass 34, count 0 2006.201.06:35:54.65#ibcon#enter sib2, iclass 34, count 0 2006.201.06:35:54.65#ibcon#flushed, iclass 34, count 0 2006.201.06:35:54.65#ibcon#about to write, iclass 34, count 0 2006.201.06:35:54.65#ibcon#wrote, iclass 34, count 0 2006.201.06:35:54.65#ibcon#about to read 3, iclass 34, count 0 2006.201.06:35:54.67#ibcon#read 3, iclass 34, count 0 2006.201.06:35:54.67#ibcon#about to read 4, iclass 34, count 0 2006.201.06:35:54.67#ibcon#read 4, iclass 34, count 0 2006.201.06:35:54.67#ibcon#about to read 5, iclass 34, count 0 2006.201.06:35:54.67#ibcon#read 5, iclass 34, count 0 2006.201.06:35:54.67#ibcon#about to read 6, iclass 34, count 0 2006.201.06:35:54.67#ibcon#read 6, iclass 34, count 0 2006.201.06:35:54.67#ibcon#end of sib2, iclass 34, count 0 2006.201.06:35:54.67#ibcon#*mode == 0, iclass 34, count 0 2006.201.06:35:54.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.06:35:54.67#ibcon#[25=USB\r\n] 2006.201.06:35:54.67#ibcon#*before write, iclass 34, count 0 2006.201.06:35:54.67#ibcon#enter sib2, iclass 34, count 0 2006.201.06:35:54.67#ibcon#flushed, iclass 34, count 0 2006.201.06:35:54.67#ibcon#about to write, iclass 34, count 0 2006.201.06:35:54.67#ibcon#wrote, iclass 34, count 0 2006.201.06:35:54.67#ibcon#about to read 3, iclass 34, count 0 2006.201.06:35:54.70#ibcon#read 3, iclass 34, count 0 2006.201.06:35:54.70#ibcon#about to read 4, iclass 34, count 0 2006.201.06:35:54.70#ibcon#read 4, iclass 34, count 0 2006.201.06:35:54.70#ibcon#about to read 5, iclass 34, count 0 2006.201.06:35:54.70#ibcon#read 5, iclass 34, count 0 2006.201.06:35:54.70#ibcon#about to read 6, iclass 34, count 0 2006.201.06:35:54.70#ibcon#read 6, iclass 34, count 0 2006.201.06:35:54.70#ibcon#end of sib2, iclass 34, count 0 2006.201.06:35:54.70#ibcon#*after write, iclass 34, count 0 2006.201.06:35:54.70#ibcon#*before return 0, iclass 34, count 0 2006.201.06:35:54.70#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:54.70#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:54.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.06:35:54.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.06:35:54.70$vck44/valo=3,564.99 2006.201.06:35:54.70#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.06:35:54.70#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.06:35:54.70#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:54.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:54.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:54.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:54.70#ibcon#enter wrdev, iclass 36, count 0 2006.201.06:35:54.70#ibcon#first serial, iclass 36, count 0 2006.201.06:35:54.70#ibcon#enter sib2, iclass 36, count 0 2006.201.06:35:54.70#ibcon#flushed, iclass 36, count 0 2006.201.06:35:54.70#ibcon#about to write, iclass 36, count 0 2006.201.06:35:54.70#ibcon#wrote, iclass 36, count 0 2006.201.06:35:54.70#ibcon#about to read 3, iclass 36, count 0 2006.201.06:35:54.72#ibcon#read 3, iclass 36, count 0 2006.201.06:35:54.72#ibcon#about to read 4, iclass 36, count 0 2006.201.06:35:54.72#ibcon#read 4, iclass 36, count 0 2006.201.06:35:54.72#ibcon#about to read 5, iclass 36, count 0 2006.201.06:35:54.72#ibcon#read 5, iclass 36, count 0 2006.201.06:35:54.72#ibcon#about to read 6, iclass 36, count 0 2006.201.06:35:54.72#ibcon#read 6, iclass 36, count 0 2006.201.06:35:54.72#ibcon#end of sib2, iclass 36, count 0 2006.201.06:35:54.72#ibcon#*mode == 0, iclass 36, count 0 2006.201.06:35:54.72#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.06:35:54.72#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.06:35:54.72#ibcon#*before write, iclass 36, count 0 2006.201.06:35:54.72#ibcon#enter sib2, iclass 36, count 0 2006.201.06:35:54.72#ibcon#flushed, iclass 36, count 0 2006.201.06:35:54.72#ibcon#about to write, iclass 36, count 0 2006.201.06:35:54.72#ibcon#wrote, iclass 36, count 0 2006.201.06:35:54.72#ibcon#about to read 3, iclass 36, count 0 2006.201.06:35:54.77#ibcon#read 3, iclass 36, count 0 2006.201.06:35:54.77#ibcon#about to read 4, iclass 36, count 0 2006.201.06:35:54.77#ibcon#read 4, iclass 36, count 0 2006.201.06:35:54.77#ibcon#about to read 5, iclass 36, count 0 2006.201.06:35:54.77#ibcon#read 5, iclass 36, count 0 2006.201.06:35:54.77#ibcon#about to read 6, iclass 36, count 0 2006.201.06:35:54.77#ibcon#read 6, iclass 36, count 0 2006.201.06:35:54.77#ibcon#end of sib2, iclass 36, count 0 2006.201.06:35:54.77#ibcon#*after write, iclass 36, count 0 2006.201.06:35:54.77#ibcon#*before return 0, iclass 36, count 0 2006.201.06:35:54.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:54.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:54.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.06:35:54.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.06:35:54.77$vck44/va=3,8 2006.201.06:35:54.77#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.06:35:54.77#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.06:35:54.77#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:54.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:54.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:54.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:54.82#ibcon#enter wrdev, iclass 38, count 2 2006.201.06:35:54.82#ibcon#first serial, iclass 38, count 2 2006.201.06:35:54.82#ibcon#enter sib2, iclass 38, count 2 2006.201.06:35:54.82#ibcon#flushed, iclass 38, count 2 2006.201.06:35:54.82#ibcon#about to write, iclass 38, count 2 2006.201.06:35:54.82#ibcon#wrote, iclass 38, count 2 2006.201.06:35:54.82#ibcon#about to read 3, iclass 38, count 2 2006.201.06:35:54.84#ibcon#read 3, iclass 38, count 2 2006.201.06:35:54.84#ibcon#about to read 4, iclass 38, count 2 2006.201.06:35:54.84#ibcon#read 4, iclass 38, count 2 2006.201.06:35:54.84#ibcon#about to read 5, iclass 38, count 2 2006.201.06:35:54.84#ibcon#read 5, iclass 38, count 2 2006.201.06:35:54.84#ibcon#about to read 6, iclass 38, count 2 2006.201.06:35:54.84#ibcon#read 6, iclass 38, count 2 2006.201.06:35:54.84#ibcon#end of sib2, iclass 38, count 2 2006.201.06:35:54.84#ibcon#*mode == 0, iclass 38, count 2 2006.201.06:35:54.84#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.06:35:54.84#ibcon#[25=AT03-08\r\n] 2006.201.06:35:54.84#ibcon#*before write, iclass 38, count 2 2006.201.06:35:54.84#ibcon#enter sib2, iclass 38, count 2 2006.201.06:35:54.84#ibcon#flushed, iclass 38, count 2 2006.201.06:35:54.84#ibcon#about to write, iclass 38, count 2 2006.201.06:35:54.84#ibcon#wrote, iclass 38, count 2 2006.201.06:35:54.84#ibcon#about to read 3, iclass 38, count 2 2006.201.06:35:54.87#ibcon#read 3, iclass 38, count 2 2006.201.06:35:54.87#ibcon#about to read 4, iclass 38, count 2 2006.201.06:35:54.87#ibcon#read 4, iclass 38, count 2 2006.201.06:35:54.87#ibcon#about to read 5, iclass 38, count 2 2006.201.06:35:54.87#ibcon#read 5, iclass 38, count 2 2006.201.06:35:54.87#ibcon#about to read 6, iclass 38, count 2 2006.201.06:35:54.87#ibcon#read 6, iclass 38, count 2 2006.201.06:35:54.87#ibcon#end of sib2, iclass 38, count 2 2006.201.06:35:54.87#ibcon#*after write, iclass 38, count 2 2006.201.06:35:54.87#ibcon#*before return 0, iclass 38, count 2 2006.201.06:35:54.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:54.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:54.87#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.06:35:54.87#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:54.87#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:54.99#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:54.99#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:54.99#ibcon#enter wrdev, iclass 38, count 0 2006.201.06:35:54.99#ibcon#first serial, iclass 38, count 0 2006.201.06:35:54.99#ibcon#enter sib2, iclass 38, count 0 2006.201.06:35:54.99#ibcon#flushed, iclass 38, count 0 2006.201.06:35:54.99#ibcon#about to write, iclass 38, count 0 2006.201.06:35:54.99#ibcon#wrote, iclass 38, count 0 2006.201.06:35:54.99#ibcon#about to read 3, iclass 38, count 0 2006.201.06:35:55.01#ibcon#read 3, iclass 38, count 0 2006.201.06:35:55.01#ibcon#about to read 4, iclass 38, count 0 2006.201.06:35:55.01#ibcon#read 4, iclass 38, count 0 2006.201.06:35:55.01#ibcon#about to read 5, iclass 38, count 0 2006.201.06:35:55.01#ibcon#read 5, iclass 38, count 0 2006.201.06:35:55.01#ibcon#about to read 6, iclass 38, count 0 2006.201.06:35:55.01#ibcon#read 6, iclass 38, count 0 2006.201.06:35:55.01#ibcon#end of sib2, iclass 38, count 0 2006.201.06:35:55.01#ibcon#*mode == 0, iclass 38, count 0 2006.201.06:35:55.01#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.06:35:55.01#ibcon#[25=USB\r\n] 2006.201.06:35:55.01#ibcon#*before write, iclass 38, count 0 2006.201.06:35:55.01#ibcon#enter sib2, iclass 38, count 0 2006.201.06:35:55.01#ibcon#flushed, iclass 38, count 0 2006.201.06:35:55.01#ibcon#about to write, iclass 38, count 0 2006.201.06:35:55.01#ibcon#wrote, iclass 38, count 0 2006.201.06:35:55.01#ibcon#about to read 3, iclass 38, count 0 2006.201.06:35:55.04#ibcon#read 3, iclass 38, count 0 2006.201.06:35:55.04#ibcon#about to read 4, iclass 38, count 0 2006.201.06:35:55.04#ibcon#read 4, iclass 38, count 0 2006.201.06:35:55.04#ibcon#about to read 5, iclass 38, count 0 2006.201.06:35:55.04#ibcon#read 5, iclass 38, count 0 2006.201.06:35:55.04#ibcon#about to read 6, iclass 38, count 0 2006.201.06:35:55.04#ibcon#read 6, iclass 38, count 0 2006.201.06:35:55.04#ibcon#end of sib2, iclass 38, count 0 2006.201.06:35:55.04#ibcon#*after write, iclass 38, count 0 2006.201.06:35:55.04#ibcon#*before return 0, iclass 38, count 0 2006.201.06:35:55.04#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:55.04#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:55.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.06:35:55.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.06:35:55.04$vck44/valo=4,624.99 2006.201.06:35:55.04#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.06:35:55.04#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.06:35:55.04#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:55.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:55.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:55.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:55.04#ibcon#enter wrdev, iclass 40, count 0 2006.201.06:35:55.04#ibcon#first serial, iclass 40, count 0 2006.201.06:35:55.04#ibcon#enter sib2, iclass 40, count 0 2006.201.06:35:55.04#ibcon#flushed, iclass 40, count 0 2006.201.06:35:55.04#ibcon#about to write, iclass 40, count 0 2006.201.06:35:55.04#ibcon#wrote, iclass 40, count 0 2006.201.06:35:55.04#ibcon#about to read 3, iclass 40, count 0 2006.201.06:35:55.06#ibcon#read 3, iclass 40, count 0 2006.201.06:35:55.06#ibcon#about to read 4, iclass 40, count 0 2006.201.06:35:55.06#ibcon#read 4, iclass 40, count 0 2006.201.06:35:55.06#ibcon#about to read 5, iclass 40, count 0 2006.201.06:35:55.06#ibcon#read 5, iclass 40, count 0 2006.201.06:35:55.06#ibcon#about to read 6, iclass 40, count 0 2006.201.06:35:55.06#ibcon#read 6, iclass 40, count 0 2006.201.06:35:55.06#ibcon#end of sib2, iclass 40, count 0 2006.201.06:35:55.06#ibcon#*mode == 0, iclass 40, count 0 2006.201.06:35:55.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.06:35:55.06#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.06:35:55.06#ibcon#*before write, iclass 40, count 0 2006.201.06:35:55.06#ibcon#enter sib2, iclass 40, count 0 2006.201.06:35:55.06#ibcon#flushed, iclass 40, count 0 2006.201.06:35:55.06#ibcon#about to write, iclass 40, count 0 2006.201.06:35:55.06#ibcon#wrote, iclass 40, count 0 2006.201.06:35:55.06#ibcon#about to read 3, iclass 40, count 0 2006.201.06:35:55.11#ibcon#read 3, iclass 40, count 0 2006.201.06:35:55.11#ibcon#about to read 4, iclass 40, count 0 2006.201.06:35:55.11#ibcon#read 4, iclass 40, count 0 2006.201.06:35:55.11#ibcon#about to read 5, iclass 40, count 0 2006.201.06:35:55.11#ibcon#read 5, iclass 40, count 0 2006.201.06:35:55.11#ibcon#about to read 6, iclass 40, count 0 2006.201.06:35:55.11#ibcon#read 6, iclass 40, count 0 2006.201.06:35:55.11#ibcon#end of sib2, iclass 40, count 0 2006.201.06:35:55.11#ibcon#*after write, iclass 40, count 0 2006.201.06:35:55.11#ibcon#*before return 0, iclass 40, count 0 2006.201.06:35:55.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:55.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:55.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.06:35:55.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.06:35:55.11$vck44/va=4,7 2006.201.06:35:55.11#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.06:35:55.11#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.06:35:55.11#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:55.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:55.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:55.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:55.16#ibcon#enter wrdev, iclass 4, count 2 2006.201.06:35:55.16#ibcon#first serial, iclass 4, count 2 2006.201.06:35:55.16#ibcon#enter sib2, iclass 4, count 2 2006.201.06:35:55.16#ibcon#flushed, iclass 4, count 2 2006.201.06:35:55.16#ibcon#about to write, iclass 4, count 2 2006.201.06:35:55.16#ibcon#wrote, iclass 4, count 2 2006.201.06:35:55.16#ibcon#about to read 3, iclass 4, count 2 2006.201.06:35:55.18#ibcon#read 3, iclass 4, count 2 2006.201.06:35:55.18#ibcon#about to read 4, iclass 4, count 2 2006.201.06:35:55.18#ibcon#read 4, iclass 4, count 2 2006.201.06:35:55.18#ibcon#about to read 5, iclass 4, count 2 2006.201.06:35:55.18#ibcon#read 5, iclass 4, count 2 2006.201.06:35:55.18#ibcon#about to read 6, iclass 4, count 2 2006.201.06:35:55.18#ibcon#read 6, iclass 4, count 2 2006.201.06:35:55.18#ibcon#end of sib2, iclass 4, count 2 2006.201.06:35:55.18#ibcon#*mode == 0, iclass 4, count 2 2006.201.06:35:55.18#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.06:35:55.18#ibcon#[25=AT04-07\r\n] 2006.201.06:35:55.18#ibcon#*before write, iclass 4, count 2 2006.201.06:35:55.18#ibcon#enter sib2, iclass 4, count 2 2006.201.06:35:55.18#ibcon#flushed, iclass 4, count 2 2006.201.06:35:55.18#ibcon#about to write, iclass 4, count 2 2006.201.06:35:55.18#ibcon#wrote, iclass 4, count 2 2006.201.06:35:55.18#ibcon#about to read 3, iclass 4, count 2 2006.201.06:35:55.21#ibcon#read 3, iclass 4, count 2 2006.201.06:35:55.21#ibcon#about to read 4, iclass 4, count 2 2006.201.06:35:55.21#ibcon#read 4, iclass 4, count 2 2006.201.06:35:55.21#ibcon#about to read 5, iclass 4, count 2 2006.201.06:35:55.21#ibcon#read 5, iclass 4, count 2 2006.201.06:35:55.21#ibcon#about to read 6, iclass 4, count 2 2006.201.06:35:55.21#ibcon#read 6, iclass 4, count 2 2006.201.06:35:55.21#ibcon#end of sib2, iclass 4, count 2 2006.201.06:35:55.21#ibcon#*after write, iclass 4, count 2 2006.201.06:35:55.21#ibcon#*before return 0, iclass 4, count 2 2006.201.06:35:55.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:55.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:55.21#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.06:35:55.21#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:55.21#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:55.33#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:55.33#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:55.33#ibcon#enter wrdev, iclass 4, count 0 2006.201.06:35:55.33#ibcon#first serial, iclass 4, count 0 2006.201.06:35:55.33#ibcon#enter sib2, iclass 4, count 0 2006.201.06:35:55.33#ibcon#flushed, iclass 4, count 0 2006.201.06:35:55.33#ibcon#about to write, iclass 4, count 0 2006.201.06:35:55.33#ibcon#wrote, iclass 4, count 0 2006.201.06:35:55.33#ibcon#about to read 3, iclass 4, count 0 2006.201.06:35:55.35#ibcon#read 3, iclass 4, count 0 2006.201.06:35:55.35#ibcon#about to read 4, iclass 4, count 0 2006.201.06:35:55.35#ibcon#read 4, iclass 4, count 0 2006.201.06:35:55.35#ibcon#about to read 5, iclass 4, count 0 2006.201.06:35:55.35#ibcon#read 5, iclass 4, count 0 2006.201.06:35:55.35#ibcon#about to read 6, iclass 4, count 0 2006.201.06:35:55.35#ibcon#read 6, iclass 4, count 0 2006.201.06:35:55.35#ibcon#end of sib2, iclass 4, count 0 2006.201.06:35:55.35#ibcon#*mode == 0, iclass 4, count 0 2006.201.06:35:55.35#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.06:35:55.35#ibcon#[25=USB\r\n] 2006.201.06:35:55.35#ibcon#*before write, iclass 4, count 0 2006.201.06:35:55.35#ibcon#enter sib2, iclass 4, count 0 2006.201.06:35:55.35#ibcon#flushed, iclass 4, count 0 2006.201.06:35:55.35#ibcon#about to write, iclass 4, count 0 2006.201.06:35:55.35#ibcon#wrote, iclass 4, count 0 2006.201.06:35:55.35#ibcon#about to read 3, iclass 4, count 0 2006.201.06:35:55.38#ibcon#read 3, iclass 4, count 0 2006.201.06:35:55.38#ibcon#about to read 4, iclass 4, count 0 2006.201.06:35:55.38#ibcon#read 4, iclass 4, count 0 2006.201.06:35:55.38#ibcon#about to read 5, iclass 4, count 0 2006.201.06:35:55.38#ibcon#read 5, iclass 4, count 0 2006.201.06:35:55.38#ibcon#about to read 6, iclass 4, count 0 2006.201.06:35:55.38#ibcon#read 6, iclass 4, count 0 2006.201.06:35:55.38#ibcon#end of sib2, iclass 4, count 0 2006.201.06:35:55.38#ibcon#*after write, iclass 4, count 0 2006.201.06:35:55.38#ibcon#*before return 0, iclass 4, count 0 2006.201.06:35:55.38#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:55.38#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:55.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.06:35:55.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.06:35:55.38$vck44/valo=5,734.99 2006.201.06:35:55.38#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.06:35:55.38#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.06:35:55.38#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:55.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:55.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:55.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:55.38#ibcon#enter wrdev, iclass 6, count 0 2006.201.06:35:55.38#ibcon#first serial, iclass 6, count 0 2006.201.06:35:55.38#ibcon#enter sib2, iclass 6, count 0 2006.201.06:35:55.38#ibcon#flushed, iclass 6, count 0 2006.201.06:35:55.38#ibcon#about to write, iclass 6, count 0 2006.201.06:35:55.38#ibcon#wrote, iclass 6, count 0 2006.201.06:35:55.38#ibcon#about to read 3, iclass 6, count 0 2006.201.06:35:55.40#ibcon#read 3, iclass 6, count 0 2006.201.06:35:55.40#ibcon#about to read 4, iclass 6, count 0 2006.201.06:35:55.40#ibcon#read 4, iclass 6, count 0 2006.201.06:35:55.40#ibcon#about to read 5, iclass 6, count 0 2006.201.06:35:55.40#ibcon#read 5, iclass 6, count 0 2006.201.06:35:55.40#ibcon#about to read 6, iclass 6, count 0 2006.201.06:35:55.40#ibcon#read 6, iclass 6, count 0 2006.201.06:35:55.40#ibcon#end of sib2, iclass 6, count 0 2006.201.06:35:55.40#ibcon#*mode == 0, iclass 6, count 0 2006.201.06:35:55.40#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.06:35:55.40#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.06:35:55.40#ibcon#*before write, iclass 6, count 0 2006.201.06:35:55.40#ibcon#enter sib2, iclass 6, count 0 2006.201.06:35:55.40#ibcon#flushed, iclass 6, count 0 2006.201.06:35:55.40#ibcon#about to write, iclass 6, count 0 2006.201.06:35:55.40#ibcon#wrote, iclass 6, count 0 2006.201.06:35:55.40#ibcon#about to read 3, iclass 6, count 0 2006.201.06:35:55.44#ibcon#read 3, iclass 6, count 0 2006.201.06:35:55.44#ibcon#about to read 4, iclass 6, count 0 2006.201.06:35:55.44#ibcon#read 4, iclass 6, count 0 2006.201.06:35:55.44#ibcon#about to read 5, iclass 6, count 0 2006.201.06:35:55.44#ibcon#read 5, iclass 6, count 0 2006.201.06:35:55.44#ibcon#about to read 6, iclass 6, count 0 2006.201.06:35:55.44#ibcon#read 6, iclass 6, count 0 2006.201.06:35:55.44#ibcon#end of sib2, iclass 6, count 0 2006.201.06:35:55.44#ibcon#*after write, iclass 6, count 0 2006.201.06:35:55.44#ibcon#*before return 0, iclass 6, count 0 2006.201.06:35:55.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:55.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:55.44#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.06:35:55.44#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.06:35:55.44$vck44/va=5,4 2006.201.06:35:55.44#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.06:35:55.44#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.06:35:55.44#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:55.44#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:55.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:55.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:55.50#ibcon#enter wrdev, iclass 10, count 2 2006.201.06:35:55.50#ibcon#first serial, iclass 10, count 2 2006.201.06:35:55.50#ibcon#enter sib2, iclass 10, count 2 2006.201.06:35:55.50#ibcon#flushed, iclass 10, count 2 2006.201.06:35:55.50#ibcon#about to write, iclass 10, count 2 2006.201.06:35:55.50#ibcon#wrote, iclass 10, count 2 2006.201.06:35:55.50#ibcon#about to read 3, iclass 10, count 2 2006.201.06:35:55.52#ibcon#read 3, iclass 10, count 2 2006.201.06:35:55.52#ibcon#about to read 4, iclass 10, count 2 2006.201.06:35:55.52#ibcon#read 4, iclass 10, count 2 2006.201.06:35:55.52#ibcon#about to read 5, iclass 10, count 2 2006.201.06:35:55.52#ibcon#read 5, iclass 10, count 2 2006.201.06:35:55.52#ibcon#about to read 6, iclass 10, count 2 2006.201.06:35:55.52#ibcon#read 6, iclass 10, count 2 2006.201.06:35:55.52#ibcon#end of sib2, iclass 10, count 2 2006.201.06:35:55.52#ibcon#*mode == 0, iclass 10, count 2 2006.201.06:35:55.52#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.06:35:55.52#ibcon#[25=AT05-04\r\n] 2006.201.06:35:55.52#ibcon#*before write, iclass 10, count 2 2006.201.06:35:55.52#ibcon#enter sib2, iclass 10, count 2 2006.201.06:35:55.52#ibcon#flushed, iclass 10, count 2 2006.201.06:35:55.52#ibcon#about to write, iclass 10, count 2 2006.201.06:35:55.52#ibcon#wrote, iclass 10, count 2 2006.201.06:35:55.52#ibcon#about to read 3, iclass 10, count 2 2006.201.06:35:55.55#ibcon#read 3, iclass 10, count 2 2006.201.06:35:55.55#ibcon#about to read 4, iclass 10, count 2 2006.201.06:35:55.55#ibcon#read 4, iclass 10, count 2 2006.201.06:35:55.55#ibcon#about to read 5, iclass 10, count 2 2006.201.06:35:55.55#ibcon#read 5, iclass 10, count 2 2006.201.06:35:55.55#ibcon#about to read 6, iclass 10, count 2 2006.201.06:35:55.55#ibcon#read 6, iclass 10, count 2 2006.201.06:35:55.55#ibcon#end of sib2, iclass 10, count 2 2006.201.06:35:55.55#ibcon#*after write, iclass 10, count 2 2006.201.06:35:55.55#ibcon#*before return 0, iclass 10, count 2 2006.201.06:35:55.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:55.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:55.55#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.06:35:55.55#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:55.55#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:55.67#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:55.67#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:55.67#ibcon#enter wrdev, iclass 10, count 0 2006.201.06:35:55.67#ibcon#first serial, iclass 10, count 0 2006.201.06:35:55.67#ibcon#enter sib2, iclass 10, count 0 2006.201.06:35:55.67#ibcon#flushed, iclass 10, count 0 2006.201.06:35:55.67#ibcon#about to write, iclass 10, count 0 2006.201.06:35:55.67#ibcon#wrote, iclass 10, count 0 2006.201.06:35:55.67#ibcon#about to read 3, iclass 10, count 0 2006.201.06:35:55.69#ibcon#read 3, iclass 10, count 0 2006.201.06:35:55.69#ibcon#about to read 4, iclass 10, count 0 2006.201.06:35:55.69#ibcon#read 4, iclass 10, count 0 2006.201.06:35:55.69#ibcon#about to read 5, iclass 10, count 0 2006.201.06:35:55.69#ibcon#read 5, iclass 10, count 0 2006.201.06:35:55.69#ibcon#about to read 6, iclass 10, count 0 2006.201.06:35:55.69#ibcon#read 6, iclass 10, count 0 2006.201.06:35:55.69#ibcon#end of sib2, iclass 10, count 0 2006.201.06:35:55.69#ibcon#*mode == 0, iclass 10, count 0 2006.201.06:35:55.69#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.06:35:55.69#ibcon#[25=USB\r\n] 2006.201.06:35:55.69#ibcon#*before write, iclass 10, count 0 2006.201.06:35:55.69#ibcon#enter sib2, iclass 10, count 0 2006.201.06:35:55.69#ibcon#flushed, iclass 10, count 0 2006.201.06:35:55.69#ibcon#about to write, iclass 10, count 0 2006.201.06:35:55.69#ibcon#wrote, iclass 10, count 0 2006.201.06:35:55.69#ibcon#about to read 3, iclass 10, count 0 2006.201.06:35:55.72#ibcon#read 3, iclass 10, count 0 2006.201.06:35:55.72#ibcon#about to read 4, iclass 10, count 0 2006.201.06:35:55.72#ibcon#read 4, iclass 10, count 0 2006.201.06:35:55.72#ibcon#about to read 5, iclass 10, count 0 2006.201.06:35:55.72#ibcon#read 5, iclass 10, count 0 2006.201.06:35:55.72#ibcon#about to read 6, iclass 10, count 0 2006.201.06:35:55.72#ibcon#read 6, iclass 10, count 0 2006.201.06:35:55.72#ibcon#end of sib2, iclass 10, count 0 2006.201.06:35:55.72#ibcon#*after write, iclass 10, count 0 2006.201.06:35:55.72#ibcon#*before return 0, iclass 10, count 0 2006.201.06:35:55.72#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:55.72#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:55.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.06:35:55.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.06:35:55.72$vck44/valo=6,814.99 2006.201.06:35:55.72#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.06:35:55.72#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.06:35:55.72#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:55.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:55.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:55.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:55.72#ibcon#enter wrdev, iclass 12, count 0 2006.201.06:35:55.72#ibcon#first serial, iclass 12, count 0 2006.201.06:35:55.72#ibcon#enter sib2, iclass 12, count 0 2006.201.06:35:55.72#ibcon#flushed, iclass 12, count 0 2006.201.06:35:55.72#ibcon#about to write, iclass 12, count 0 2006.201.06:35:55.72#ibcon#wrote, iclass 12, count 0 2006.201.06:35:55.72#ibcon#about to read 3, iclass 12, count 0 2006.201.06:35:55.74#ibcon#read 3, iclass 12, count 0 2006.201.06:35:55.74#ibcon#about to read 4, iclass 12, count 0 2006.201.06:35:55.74#ibcon#read 4, iclass 12, count 0 2006.201.06:35:55.74#ibcon#about to read 5, iclass 12, count 0 2006.201.06:35:55.74#ibcon#read 5, iclass 12, count 0 2006.201.06:35:55.74#ibcon#about to read 6, iclass 12, count 0 2006.201.06:35:55.74#ibcon#read 6, iclass 12, count 0 2006.201.06:35:55.74#ibcon#end of sib2, iclass 12, count 0 2006.201.06:35:55.74#ibcon#*mode == 0, iclass 12, count 0 2006.201.06:35:55.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.06:35:55.74#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.06:35:55.74#ibcon#*before write, iclass 12, count 0 2006.201.06:35:55.74#ibcon#enter sib2, iclass 12, count 0 2006.201.06:35:55.74#ibcon#flushed, iclass 12, count 0 2006.201.06:35:55.74#ibcon#about to write, iclass 12, count 0 2006.201.06:35:55.74#ibcon#wrote, iclass 12, count 0 2006.201.06:35:55.74#ibcon#about to read 3, iclass 12, count 0 2006.201.06:35:55.79#ibcon#read 3, iclass 12, count 0 2006.201.06:35:55.79#ibcon#about to read 4, iclass 12, count 0 2006.201.06:35:55.79#ibcon#read 4, iclass 12, count 0 2006.201.06:35:55.79#ibcon#about to read 5, iclass 12, count 0 2006.201.06:35:55.79#ibcon#read 5, iclass 12, count 0 2006.201.06:35:55.79#ibcon#about to read 6, iclass 12, count 0 2006.201.06:35:55.79#ibcon#read 6, iclass 12, count 0 2006.201.06:35:55.79#ibcon#end of sib2, iclass 12, count 0 2006.201.06:35:55.79#ibcon#*after write, iclass 12, count 0 2006.201.06:35:55.79#ibcon#*before return 0, iclass 12, count 0 2006.201.06:35:55.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:55.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:55.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.06:35:55.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.06:35:55.79$vck44/va=6,5 2006.201.06:35:55.79#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.06:35:55.79#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.06:35:55.79#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:55.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:55.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:55.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:55.84#ibcon#enter wrdev, iclass 14, count 2 2006.201.06:35:55.84#ibcon#first serial, iclass 14, count 2 2006.201.06:35:55.84#ibcon#enter sib2, iclass 14, count 2 2006.201.06:35:55.84#ibcon#flushed, iclass 14, count 2 2006.201.06:35:55.84#ibcon#about to write, iclass 14, count 2 2006.201.06:35:55.84#ibcon#wrote, iclass 14, count 2 2006.201.06:35:55.84#ibcon#about to read 3, iclass 14, count 2 2006.201.06:35:55.86#ibcon#read 3, iclass 14, count 2 2006.201.06:35:55.86#ibcon#about to read 4, iclass 14, count 2 2006.201.06:35:55.86#ibcon#read 4, iclass 14, count 2 2006.201.06:35:55.86#ibcon#about to read 5, iclass 14, count 2 2006.201.06:35:55.86#ibcon#read 5, iclass 14, count 2 2006.201.06:35:55.86#ibcon#about to read 6, iclass 14, count 2 2006.201.06:35:55.86#ibcon#read 6, iclass 14, count 2 2006.201.06:35:55.86#ibcon#end of sib2, iclass 14, count 2 2006.201.06:35:55.86#ibcon#*mode == 0, iclass 14, count 2 2006.201.06:35:55.86#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.06:35:55.86#ibcon#[25=AT06-05\r\n] 2006.201.06:35:55.86#ibcon#*before write, iclass 14, count 2 2006.201.06:35:55.86#ibcon#enter sib2, iclass 14, count 2 2006.201.06:35:55.86#ibcon#flushed, iclass 14, count 2 2006.201.06:35:55.86#ibcon#about to write, iclass 14, count 2 2006.201.06:35:55.86#ibcon#wrote, iclass 14, count 2 2006.201.06:35:55.86#ibcon#about to read 3, iclass 14, count 2 2006.201.06:35:55.89#ibcon#read 3, iclass 14, count 2 2006.201.06:35:55.89#ibcon#about to read 4, iclass 14, count 2 2006.201.06:35:55.89#ibcon#read 4, iclass 14, count 2 2006.201.06:35:55.89#ibcon#about to read 5, iclass 14, count 2 2006.201.06:35:55.89#ibcon#read 5, iclass 14, count 2 2006.201.06:35:55.89#ibcon#about to read 6, iclass 14, count 2 2006.201.06:35:55.89#ibcon#read 6, iclass 14, count 2 2006.201.06:35:55.89#ibcon#end of sib2, iclass 14, count 2 2006.201.06:35:55.89#ibcon#*after write, iclass 14, count 2 2006.201.06:35:55.89#ibcon#*before return 0, iclass 14, count 2 2006.201.06:35:55.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:55.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:55.89#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.06:35:55.89#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:55.89#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:56.01#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:56.01#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:56.01#ibcon#enter wrdev, iclass 14, count 0 2006.201.06:35:56.01#ibcon#first serial, iclass 14, count 0 2006.201.06:35:56.01#ibcon#enter sib2, iclass 14, count 0 2006.201.06:35:56.01#ibcon#flushed, iclass 14, count 0 2006.201.06:35:56.01#ibcon#about to write, iclass 14, count 0 2006.201.06:35:56.01#ibcon#wrote, iclass 14, count 0 2006.201.06:35:56.01#ibcon#about to read 3, iclass 14, count 0 2006.201.06:35:56.03#ibcon#read 3, iclass 14, count 0 2006.201.06:35:56.03#ibcon#about to read 4, iclass 14, count 0 2006.201.06:35:56.03#ibcon#read 4, iclass 14, count 0 2006.201.06:35:56.03#ibcon#about to read 5, iclass 14, count 0 2006.201.06:35:56.03#ibcon#read 5, iclass 14, count 0 2006.201.06:35:56.03#ibcon#about to read 6, iclass 14, count 0 2006.201.06:35:56.03#ibcon#read 6, iclass 14, count 0 2006.201.06:35:56.03#ibcon#end of sib2, iclass 14, count 0 2006.201.06:35:56.03#ibcon#*mode == 0, iclass 14, count 0 2006.201.06:35:56.03#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.06:35:56.03#ibcon#[25=USB\r\n] 2006.201.06:35:56.03#ibcon#*before write, iclass 14, count 0 2006.201.06:35:56.03#ibcon#enter sib2, iclass 14, count 0 2006.201.06:35:56.03#ibcon#flushed, iclass 14, count 0 2006.201.06:35:56.03#ibcon#about to write, iclass 14, count 0 2006.201.06:35:56.03#ibcon#wrote, iclass 14, count 0 2006.201.06:35:56.03#ibcon#about to read 3, iclass 14, count 0 2006.201.06:35:56.06#ibcon#read 3, iclass 14, count 0 2006.201.06:35:56.06#ibcon#about to read 4, iclass 14, count 0 2006.201.06:35:56.06#ibcon#read 4, iclass 14, count 0 2006.201.06:35:56.06#ibcon#about to read 5, iclass 14, count 0 2006.201.06:35:56.06#ibcon#read 5, iclass 14, count 0 2006.201.06:35:56.06#ibcon#about to read 6, iclass 14, count 0 2006.201.06:35:56.06#ibcon#read 6, iclass 14, count 0 2006.201.06:35:56.06#ibcon#end of sib2, iclass 14, count 0 2006.201.06:35:56.06#ibcon#*after write, iclass 14, count 0 2006.201.06:35:56.06#ibcon#*before return 0, iclass 14, count 0 2006.201.06:35:56.06#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:56.06#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:56.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.06:35:56.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.06:35:56.06$vck44/valo=7,864.99 2006.201.06:35:56.06#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.06:35:56.06#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.06:35:56.06#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:56.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:56.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:56.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:56.06#ibcon#enter wrdev, iclass 16, count 0 2006.201.06:35:56.06#ibcon#first serial, iclass 16, count 0 2006.201.06:35:56.06#ibcon#enter sib2, iclass 16, count 0 2006.201.06:35:56.06#ibcon#flushed, iclass 16, count 0 2006.201.06:35:56.06#ibcon#about to write, iclass 16, count 0 2006.201.06:35:56.06#ibcon#wrote, iclass 16, count 0 2006.201.06:35:56.06#ibcon#about to read 3, iclass 16, count 0 2006.201.06:35:56.08#ibcon#read 3, iclass 16, count 0 2006.201.06:35:56.08#ibcon#about to read 4, iclass 16, count 0 2006.201.06:35:56.08#ibcon#read 4, iclass 16, count 0 2006.201.06:35:56.08#ibcon#about to read 5, iclass 16, count 0 2006.201.06:35:56.08#ibcon#read 5, iclass 16, count 0 2006.201.06:35:56.08#ibcon#about to read 6, iclass 16, count 0 2006.201.06:35:56.08#ibcon#read 6, iclass 16, count 0 2006.201.06:35:56.08#ibcon#end of sib2, iclass 16, count 0 2006.201.06:35:56.08#ibcon#*mode == 0, iclass 16, count 0 2006.201.06:35:56.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.06:35:56.08#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.06:35:56.08#ibcon#*before write, iclass 16, count 0 2006.201.06:35:56.08#ibcon#enter sib2, iclass 16, count 0 2006.201.06:35:56.08#ibcon#flushed, iclass 16, count 0 2006.201.06:35:56.08#ibcon#about to write, iclass 16, count 0 2006.201.06:35:56.08#ibcon#wrote, iclass 16, count 0 2006.201.06:35:56.08#ibcon#about to read 3, iclass 16, count 0 2006.201.06:35:56.13#ibcon#read 3, iclass 16, count 0 2006.201.06:35:56.13#ibcon#about to read 4, iclass 16, count 0 2006.201.06:35:56.13#ibcon#read 4, iclass 16, count 0 2006.201.06:35:56.13#ibcon#about to read 5, iclass 16, count 0 2006.201.06:35:56.13#ibcon#read 5, iclass 16, count 0 2006.201.06:35:56.13#ibcon#about to read 6, iclass 16, count 0 2006.201.06:35:56.13#ibcon#read 6, iclass 16, count 0 2006.201.06:35:56.13#ibcon#end of sib2, iclass 16, count 0 2006.201.06:35:56.13#ibcon#*after write, iclass 16, count 0 2006.201.06:35:56.13#ibcon#*before return 0, iclass 16, count 0 2006.201.06:35:56.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:56.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:56.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.06:35:56.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.06:35:56.13$vck44/va=7,5 2006.201.06:35:56.13#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.06:35:56.13#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.06:35:56.13#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:56.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:56.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:56.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:56.18#ibcon#enter wrdev, iclass 18, count 2 2006.201.06:35:56.18#ibcon#first serial, iclass 18, count 2 2006.201.06:35:56.18#ibcon#enter sib2, iclass 18, count 2 2006.201.06:35:56.18#ibcon#flushed, iclass 18, count 2 2006.201.06:35:56.18#ibcon#about to write, iclass 18, count 2 2006.201.06:35:56.18#ibcon#wrote, iclass 18, count 2 2006.201.06:35:56.18#ibcon#about to read 3, iclass 18, count 2 2006.201.06:35:56.20#ibcon#read 3, iclass 18, count 2 2006.201.06:35:56.20#ibcon#about to read 4, iclass 18, count 2 2006.201.06:35:56.20#ibcon#read 4, iclass 18, count 2 2006.201.06:35:56.20#ibcon#about to read 5, iclass 18, count 2 2006.201.06:35:56.20#ibcon#read 5, iclass 18, count 2 2006.201.06:35:56.20#ibcon#about to read 6, iclass 18, count 2 2006.201.06:35:56.20#ibcon#read 6, iclass 18, count 2 2006.201.06:35:56.20#ibcon#end of sib2, iclass 18, count 2 2006.201.06:35:56.20#ibcon#*mode == 0, iclass 18, count 2 2006.201.06:35:56.20#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.06:35:56.20#ibcon#[25=AT07-05\r\n] 2006.201.06:35:56.20#ibcon#*before write, iclass 18, count 2 2006.201.06:35:56.20#ibcon#enter sib2, iclass 18, count 2 2006.201.06:35:56.20#ibcon#flushed, iclass 18, count 2 2006.201.06:35:56.20#ibcon#about to write, iclass 18, count 2 2006.201.06:35:56.20#ibcon#wrote, iclass 18, count 2 2006.201.06:35:56.20#ibcon#about to read 3, iclass 18, count 2 2006.201.06:35:56.23#ibcon#read 3, iclass 18, count 2 2006.201.06:35:56.23#ibcon#about to read 4, iclass 18, count 2 2006.201.06:35:56.23#ibcon#read 4, iclass 18, count 2 2006.201.06:35:56.23#ibcon#about to read 5, iclass 18, count 2 2006.201.06:35:56.23#ibcon#read 5, iclass 18, count 2 2006.201.06:35:56.23#ibcon#about to read 6, iclass 18, count 2 2006.201.06:35:56.23#ibcon#read 6, iclass 18, count 2 2006.201.06:35:56.23#ibcon#end of sib2, iclass 18, count 2 2006.201.06:35:56.23#ibcon#*after write, iclass 18, count 2 2006.201.06:35:56.23#ibcon#*before return 0, iclass 18, count 2 2006.201.06:35:56.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:56.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:56.23#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.06:35:56.23#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:56.23#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:56.35#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:56.35#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:56.35#ibcon#enter wrdev, iclass 18, count 0 2006.201.06:35:56.35#ibcon#first serial, iclass 18, count 0 2006.201.06:35:56.35#ibcon#enter sib2, iclass 18, count 0 2006.201.06:35:56.35#ibcon#flushed, iclass 18, count 0 2006.201.06:35:56.35#ibcon#about to write, iclass 18, count 0 2006.201.06:35:56.35#ibcon#wrote, iclass 18, count 0 2006.201.06:35:56.35#ibcon#about to read 3, iclass 18, count 0 2006.201.06:35:56.37#ibcon#read 3, iclass 18, count 0 2006.201.06:35:56.37#ibcon#about to read 4, iclass 18, count 0 2006.201.06:35:56.37#ibcon#read 4, iclass 18, count 0 2006.201.06:35:56.37#ibcon#about to read 5, iclass 18, count 0 2006.201.06:35:56.37#ibcon#read 5, iclass 18, count 0 2006.201.06:35:56.37#ibcon#about to read 6, iclass 18, count 0 2006.201.06:35:56.37#ibcon#read 6, iclass 18, count 0 2006.201.06:35:56.37#ibcon#end of sib2, iclass 18, count 0 2006.201.06:35:56.37#ibcon#*mode == 0, iclass 18, count 0 2006.201.06:35:56.37#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.06:35:56.37#ibcon#[25=USB\r\n] 2006.201.06:35:56.37#ibcon#*before write, iclass 18, count 0 2006.201.06:35:56.37#ibcon#enter sib2, iclass 18, count 0 2006.201.06:35:56.37#ibcon#flushed, iclass 18, count 0 2006.201.06:35:56.37#ibcon#about to write, iclass 18, count 0 2006.201.06:35:56.37#ibcon#wrote, iclass 18, count 0 2006.201.06:35:56.37#ibcon#about to read 3, iclass 18, count 0 2006.201.06:35:56.40#ibcon#read 3, iclass 18, count 0 2006.201.06:35:56.40#ibcon#about to read 4, iclass 18, count 0 2006.201.06:35:56.40#ibcon#read 4, iclass 18, count 0 2006.201.06:35:56.40#ibcon#about to read 5, iclass 18, count 0 2006.201.06:35:56.40#ibcon#read 5, iclass 18, count 0 2006.201.06:35:56.40#ibcon#about to read 6, iclass 18, count 0 2006.201.06:35:56.40#ibcon#read 6, iclass 18, count 0 2006.201.06:35:56.40#ibcon#end of sib2, iclass 18, count 0 2006.201.06:35:56.40#ibcon#*after write, iclass 18, count 0 2006.201.06:35:56.40#ibcon#*before return 0, iclass 18, count 0 2006.201.06:35:56.40#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:56.40#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:56.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.06:35:56.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.06:35:56.40$vck44/valo=8,884.99 2006.201.06:35:56.40#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.06:35:56.40#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.06:35:56.40#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:56.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:56.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:56.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:56.40#ibcon#enter wrdev, iclass 20, count 0 2006.201.06:35:56.40#ibcon#first serial, iclass 20, count 0 2006.201.06:35:56.40#ibcon#enter sib2, iclass 20, count 0 2006.201.06:35:56.40#ibcon#flushed, iclass 20, count 0 2006.201.06:35:56.40#ibcon#about to write, iclass 20, count 0 2006.201.06:35:56.40#ibcon#wrote, iclass 20, count 0 2006.201.06:35:56.40#ibcon#about to read 3, iclass 20, count 0 2006.201.06:35:56.42#ibcon#read 3, iclass 20, count 0 2006.201.06:35:56.42#ibcon#about to read 4, iclass 20, count 0 2006.201.06:35:56.42#ibcon#read 4, iclass 20, count 0 2006.201.06:35:56.42#ibcon#about to read 5, iclass 20, count 0 2006.201.06:35:56.42#ibcon#read 5, iclass 20, count 0 2006.201.06:35:56.42#ibcon#about to read 6, iclass 20, count 0 2006.201.06:35:56.42#ibcon#read 6, iclass 20, count 0 2006.201.06:35:56.42#ibcon#end of sib2, iclass 20, count 0 2006.201.06:35:56.42#ibcon#*mode == 0, iclass 20, count 0 2006.201.06:35:56.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.06:35:56.42#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.06:35:56.42#ibcon#*before write, iclass 20, count 0 2006.201.06:35:56.42#ibcon#enter sib2, iclass 20, count 0 2006.201.06:35:56.42#ibcon#flushed, iclass 20, count 0 2006.201.06:35:56.42#ibcon#about to write, iclass 20, count 0 2006.201.06:35:56.42#ibcon#wrote, iclass 20, count 0 2006.201.06:35:56.42#ibcon#about to read 3, iclass 20, count 0 2006.201.06:35:56.46#ibcon#read 3, iclass 20, count 0 2006.201.06:35:56.46#ibcon#about to read 4, iclass 20, count 0 2006.201.06:35:56.46#ibcon#read 4, iclass 20, count 0 2006.201.06:35:56.46#ibcon#about to read 5, iclass 20, count 0 2006.201.06:35:56.46#ibcon#read 5, iclass 20, count 0 2006.201.06:35:56.46#ibcon#about to read 6, iclass 20, count 0 2006.201.06:35:56.46#ibcon#read 6, iclass 20, count 0 2006.201.06:35:56.46#ibcon#end of sib2, iclass 20, count 0 2006.201.06:35:56.46#ibcon#*after write, iclass 20, count 0 2006.201.06:35:56.46#ibcon#*before return 0, iclass 20, count 0 2006.201.06:35:56.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:56.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:56.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.06:35:56.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.06:35:56.46$vck44/va=8,4 2006.201.06:35:56.46#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.06:35:56.46#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.06:35:56.46#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:56.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:35:56.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:35:56.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:35:56.52#ibcon#enter wrdev, iclass 22, count 2 2006.201.06:35:56.52#ibcon#first serial, iclass 22, count 2 2006.201.06:35:56.52#ibcon#enter sib2, iclass 22, count 2 2006.201.06:35:56.52#ibcon#flushed, iclass 22, count 2 2006.201.06:35:56.52#ibcon#about to write, iclass 22, count 2 2006.201.06:35:56.52#ibcon#wrote, iclass 22, count 2 2006.201.06:35:56.52#ibcon#about to read 3, iclass 22, count 2 2006.201.06:35:56.54#ibcon#read 3, iclass 22, count 2 2006.201.06:35:56.54#ibcon#about to read 4, iclass 22, count 2 2006.201.06:35:56.54#ibcon#read 4, iclass 22, count 2 2006.201.06:35:56.54#ibcon#about to read 5, iclass 22, count 2 2006.201.06:35:56.54#ibcon#read 5, iclass 22, count 2 2006.201.06:35:56.54#ibcon#about to read 6, iclass 22, count 2 2006.201.06:35:56.54#ibcon#read 6, iclass 22, count 2 2006.201.06:35:56.54#ibcon#end of sib2, iclass 22, count 2 2006.201.06:35:56.54#ibcon#*mode == 0, iclass 22, count 2 2006.201.06:35:56.54#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.06:35:56.54#ibcon#[25=AT08-04\r\n] 2006.201.06:35:56.54#ibcon#*before write, iclass 22, count 2 2006.201.06:35:56.54#ibcon#enter sib2, iclass 22, count 2 2006.201.06:35:56.54#ibcon#flushed, iclass 22, count 2 2006.201.06:35:56.54#ibcon#about to write, iclass 22, count 2 2006.201.06:35:56.54#ibcon#wrote, iclass 22, count 2 2006.201.06:35:56.54#ibcon#about to read 3, iclass 22, count 2 2006.201.06:35:56.57#ibcon#read 3, iclass 22, count 2 2006.201.06:35:56.57#ibcon#about to read 4, iclass 22, count 2 2006.201.06:35:56.57#ibcon#read 4, iclass 22, count 2 2006.201.06:35:56.57#ibcon#about to read 5, iclass 22, count 2 2006.201.06:35:56.57#ibcon#read 5, iclass 22, count 2 2006.201.06:35:56.57#ibcon#about to read 6, iclass 22, count 2 2006.201.06:35:56.57#ibcon#read 6, iclass 22, count 2 2006.201.06:35:56.57#ibcon#end of sib2, iclass 22, count 2 2006.201.06:35:56.57#ibcon#*after write, iclass 22, count 2 2006.201.06:35:56.57#ibcon#*before return 0, iclass 22, count 2 2006.201.06:35:56.57#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:35:56.57#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.06:35:56.57#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.06:35:56.57#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:56.57#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:35:56.69#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:35:56.69#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:35:56.69#ibcon#enter wrdev, iclass 22, count 0 2006.201.06:35:56.69#ibcon#first serial, iclass 22, count 0 2006.201.06:35:56.69#ibcon#enter sib2, iclass 22, count 0 2006.201.06:35:56.69#ibcon#flushed, iclass 22, count 0 2006.201.06:35:56.69#ibcon#about to write, iclass 22, count 0 2006.201.06:35:56.69#ibcon#wrote, iclass 22, count 0 2006.201.06:35:56.69#ibcon#about to read 3, iclass 22, count 0 2006.201.06:35:56.71#ibcon#read 3, iclass 22, count 0 2006.201.06:35:56.71#ibcon#about to read 4, iclass 22, count 0 2006.201.06:35:56.71#ibcon#read 4, iclass 22, count 0 2006.201.06:35:56.71#ibcon#about to read 5, iclass 22, count 0 2006.201.06:35:56.71#ibcon#read 5, iclass 22, count 0 2006.201.06:35:56.71#ibcon#about to read 6, iclass 22, count 0 2006.201.06:35:56.71#ibcon#read 6, iclass 22, count 0 2006.201.06:35:56.71#ibcon#end of sib2, iclass 22, count 0 2006.201.06:35:56.71#ibcon#*mode == 0, iclass 22, count 0 2006.201.06:35:56.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.06:35:56.71#ibcon#[25=USB\r\n] 2006.201.06:35:56.71#ibcon#*before write, iclass 22, count 0 2006.201.06:35:56.71#ibcon#enter sib2, iclass 22, count 0 2006.201.06:35:56.71#ibcon#flushed, iclass 22, count 0 2006.201.06:35:56.71#ibcon#about to write, iclass 22, count 0 2006.201.06:35:56.71#ibcon#wrote, iclass 22, count 0 2006.201.06:35:56.71#ibcon#about to read 3, iclass 22, count 0 2006.201.06:35:56.74#ibcon#read 3, iclass 22, count 0 2006.201.06:35:56.74#ibcon#about to read 4, iclass 22, count 0 2006.201.06:35:56.74#ibcon#read 4, iclass 22, count 0 2006.201.06:35:56.74#ibcon#about to read 5, iclass 22, count 0 2006.201.06:35:56.74#ibcon#read 5, iclass 22, count 0 2006.201.06:35:56.74#ibcon#about to read 6, iclass 22, count 0 2006.201.06:35:56.74#ibcon#read 6, iclass 22, count 0 2006.201.06:35:56.74#ibcon#end of sib2, iclass 22, count 0 2006.201.06:35:56.74#ibcon#*after write, iclass 22, count 0 2006.201.06:35:56.74#ibcon#*before return 0, iclass 22, count 0 2006.201.06:35:56.74#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:35:56.74#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.06:35:56.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.06:35:56.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.06:35:56.74$vck44/vblo=1,629.99 2006.201.06:35:56.74#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.06:35:56.74#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.06:35:56.74#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:56.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:35:56.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:35:56.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:35:56.74#ibcon#enter wrdev, iclass 24, count 0 2006.201.06:35:56.74#ibcon#first serial, iclass 24, count 0 2006.201.06:35:56.74#ibcon#enter sib2, iclass 24, count 0 2006.201.06:35:56.74#ibcon#flushed, iclass 24, count 0 2006.201.06:35:56.74#ibcon#about to write, iclass 24, count 0 2006.201.06:35:56.74#ibcon#wrote, iclass 24, count 0 2006.201.06:35:56.74#ibcon#about to read 3, iclass 24, count 0 2006.201.06:35:56.76#ibcon#read 3, iclass 24, count 0 2006.201.06:35:56.76#ibcon#about to read 4, iclass 24, count 0 2006.201.06:35:56.76#ibcon#read 4, iclass 24, count 0 2006.201.06:35:56.76#ibcon#about to read 5, iclass 24, count 0 2006.201.06:35:56.76#ibcon#read 5, iclass 24, count 0 2006.201.06:35:56.76#ibcon#about to read 6, iclass 24, count 0 2006.201.06:35:56.76#ibcon#read 6, iclass 24, count 0 2006.201.06:35:56.76#ibcon#end of sib2, iclass 24, count 0 2006.201.06:35:56.76#ibcon#*mode == 0, iclass 24, count 0 2006.201.06:35:56.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.06:35:56.76#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.06:35:56.76#ibcon#*before write, iclass 24, count 0 2006.201.06:35:56.76#ibcon#enter sib2, iclass 24, count 0 2006.201.06:35:56.76#ibcon#flushed, iclass 24, count 0 2006.201.06:35:56.76#ibcon#about to write, iclass 24, count 0 2006.201.06:35:56.76#ibcon#wrote, iclass 24, count 0 2006.201.06:35:56.76#ibcon#about to read 3, iclass 24, count 0 2006.201.06:35:56.81#ibcon#read 3, iclass 24, count 0 2006.201.06:35:56.81#ibcon#about to read 4, iclass 24, count 0 2006.201.06:35:56.81#ibcon#read 4, iclass 24, count 0 2006.201.06:35:56.81#ibcon#about to read 5, iclass 24, count 0 2006.201.06:35:56.81#ibcon#read 5, iclass 24, count 0 2006.201.06:35:56.81#ibcon#about to read 6, iclass 24, count 0 2006.201.06:35:56.81#ibcon#read 6, iclass 24, count 0 2006.201.06:35:56.81#ibcon#end of sib2, iclass 24, count 0 2006.201.06:35:56.81#ibcon#*after write, iclass 24, count 0 2006.201.06:35:56.81#ibcon#*before return 0, iclass 24, count 0 2006.201.06:35:56.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:35:56.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.06:35:56.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.06:35:56.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.06:35:56.81$vck44/vb=1,4 2006.201.06:35:56.81#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.06:35:56.81#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.06:35:56.81#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:56.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:35:56.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:35:56.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:35:56.81#ibcon#enter wrdev, iclass 26, count 2 2006.201.06:35:56.81#ibcon#first serial, iclass 26, count 2 2006.201.06:35:56.81#ibcon#enter sib2, iclass 26, count 2 2006.201.06:35:56.81#ibcon#flushed, iclass 26, count 2 2006.201.06:35:56.81#ibcon#about to write, iclass 26, count 2 2006.201.06:35:56.81#ibcon#wrote, iclass 26, count 2 2006.201.06:35:56.81#ibcon#about to read 3, iclass 26, count 2 2006.201.06:35:56.83#ibcon#read 3, iclass 26, count 2 2006.201.06:35:56.83#ibcon#about to read 4, iclass 26, count 2 2006.201.06:35:56.83#ibcon#read 4, iclass 26, count 2 2006.201.06:35:56.83#ibcon#about to read 5, iclass 26, count 2 2006.201.06:35:56.83#ibcon#read 5, iclass 26, count 2 2006.201.06:35:56.83#ibcon#about to read 6, iclass 26, count 2 2006.201.06:35:56.83#ibcon#read 6, iclass 26, count 2 2006.201.06:35:56.83#ibcon#end of sib2, iclass 26, count 2 2006.201.06:35:56.83#ibcon#*mode == 0, iclass 26, count 2 2006.201.06:35:56.83#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.06:35:56.83#ibcon#[27=AT01-04\r\n] 2006.201.06:35:56.83#ibcon#*before write, iclass 26, count 2 2006.201.06:35:56.83#ibcon#enter sib2, iclass 26, count 2 2006.201.06:35:56.83#ibcon#flushed, iclass 26, count 2 2006.201.06:35:56.83#ibcon#about to write, iclass 26, count 2 2006.201.06:35:56.83#ibcon#wrote, iclass 26, count 2 2006.201.06:35:56.83#ibcon#about to read 3, iclass 26, count 2 2006.201.06:35:56.86#ibcon#read 3, iclass 26, count 2 2006.201.06:35:56.86#ibcon#about to read 4, iclass 26, count 2 2006.201.06:35:56.86#ibcon#read 4, iclass 26, count 2 2006.201.06:35:56.86#ibcon#about to read 5, iclass 26, count 2 2006.201.06:35:56.86#ibcon#read 5, iclass 26, count 2 2006.201.06:35:56.86#ibcon#about to read 6, iclass 26, count 2 2006.201.06:35:56.86#ibcon#read 6, iclass 26, count 2 2006.201.06:35:56.86#ibcon#end of sib2, iclass 26, count 2 2006.201.06:35:56.86#ibcon#*after write, iclass 26, count 2 2006.201.06:35:56.86#ibcon#*before return 0, iclass 26, count 2 2006.201.06:35:56.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:35:56.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.06:35:56.86#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.06:35:56.86#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:56.86#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:35:56.98#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:35:56.98#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:35:56.98#ibcon#enter wrdev, iclass 26, count 0 2006.201.06:35:56.98#ibcon#first serial, iclass 26, count 0 2006.201.06:35:56.98#ibcon#enter sib2, iclass 26, count 0 2006.201.06:35:56.98#ibcon#flushed, iclass 26, count 0 2006.201.06:35:56.98#ibcon#about to write, iclass 26, count 0 2006.201.06:35:56.98#ibcon#wrote, iclass 26, count 0 2006.201.06:35:56.98#ibcon#about to read 3, iclass 26, count 0 2006.201.06:35:57.00#ibcon#read 3, iclass 26, count 0 2006.201.06:35:57.00#ibcon#about to read 4, iclass 26, count 0 2006.201.06:35:57.00#ibcon#read 4, iclass 26, count 0 2006.201.06:35:57.00#ibcon#about to read 5, iclass 26, count 0 2006.201.06:35:57.00#ibcon#read 5, iclass 26, count 0 2006.201.06:35:57.00#ibcon#about to read 6, iclass 26, count 0 2006.201.06:35:57.00#ibcon#read 6, iclass 26, count 0 2006.201.06:35:57.00#ibcon#end of sib2, iclass 26, count 0 2006.201.06:35:57.00#ibcon#*mode == 0, iclass 26, count 0 2006.201.06:35:57.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.06:35:57.00#ibcon#[27=USB\r\n] 2006.201.06:35:57.00#ibcon#*before write, iclass 26, count 0 2006.201.06:35:57.00#ibcon#enter sib2, iclass 26, count 0 2006.201.06:35:57.00#ibcon#flushed, iclass 26, count 0 2006.201.06:35:57.00#ibcon#about to write, iclass 26, count 0 2006.201.06:35:57.00#ibcon#wrote, iclass 26, count 0 2006.201.06:35:57.00#ibcon#about to read 3, iclass 26, count 0 2006.201.06:35:57.03#ibcon#read 3, iclass 26, count 0 2006.201.06:35:57.03#ibcon#about to read 4, iclass 26, count 0 2006.201.06:35:57.03#ibcon#read 4, iclass 26, count 0 2006.201.06:35:57.03#ibcon#about to read 5, iclass 26, count 0 2006.201.06:35:57.03#ibcon#read 5, iclass 26, count 0 2006.201.06:35:57.03#ibcon#about to read 6, iclass 26, count 0 2006.201.06:35:57.03#ibcon#read 6, iclass 26, count 0 2006.201.06:35:57.03#ibcon#end of sib2, iclass 26, count 0 2006.201.06:35:57.03#ibcon#*after write, iclass 26, count 0 2006.201.06:35:57.03#ibcon#*before return 0, iclass 26, count 0 2006.201.06:35:57.03#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:35:57.03#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.06:35:57.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.06:35:57.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.06:35:57.03$vck44/vblo=2,634.99 2006.201.06:35:57.03#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.06:35:57.03#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.06:35:57.03#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:57.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:57.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:57.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:57.03#ibcon#enter wrdev, iclass 28, count 0 2006.201.06:35:57.03#ibcon#first serial, iclass 28, count 0 2006.201.06:35:57.03#ibcon#enter sib2, iclass 28, count 0 2006.201.06:35:57.03#ibcon#flushed, iclass 28, count 0 2006.201.06:35:57.03#ibcon#about to write, iclass 28, count 0 2006.201.06:35:57.03#ibcon#wrote, iclass 28, count 0 2006.201.06:35:57.03#ibcon#about to read 3, iclass 28, count 0 2006.201.06:35:57.05#ibcon#read 3, iclass 28, count 0 2006.201.06:35:57.05#ibcon#about to read 4, iclass 28, count 0 2006.201.06:35:57.05#ibcon#read 4, iclass 28, count 0 2006.201.06:35:57.05#ibcon#about to read 5, iclass 28, count 0 2006.201.06:35:57.05#ibcon#read 5, iclass 28, count 0 2006.201.06:35:57.05#ibcon#about to read 6, iclass 28, count 0 2006.201.06:35:57.05#ibcon#read 6, iclass 28, count 0 2006.201.06:35:57.05#ibcon#end of sib2, iclass 28, count 0 2006.201.06:35:57.05#ibcon#*mode == 0, iclass 28, count 0 2006.201.06:35:57.05#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.06:35:57.05#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.06:35:57.05#ibcon#*before write, iclass 28, count 0 2006.201.06:35:57.05#ibcon#enter sib2, iclass 28, count 0 2006.201.06:35:57.05#ibcon#flushed, iclass 28, count 0 2006.201.06:35:57.05#ibcon#about to write, iclass 28, count 0 2006.201.06:35:57.05#ibcon#wrote, iclass 28, count 0 2006.201.06:35:57.05#ibcon#about to read 3, iclass 28, count 0 2006.201.06:35:57.09#ibcon#read 3, iclass 28, count 0 2006.201.06:35:57.09#ibcon#about to read 4, iclass 28, count 0 2006.201.06:35:57.09#ibcon#read 4, iclass 28, count 0 2006.201.06:35:57.09#ibcon#about to read 5, iclass 28, count 0 2006.201.06:35:57.09#ibcon#read 5, iclass 28, count 0 2006.201.06:35:57.09#ibcon#about to read 6, iclass 28, count 0 2006.201.06:35:57.09#ibcon#read 6, iclass 28, count 0 2006.201.06:35:57.09#ibcon#end of sib2, iclass 28, count 0 2006.201.06:35:57.09#ibcon#*after write, iclass 28, count 0 2006.201.06:35:57.09#ibcon#*before return 0, iclass 28, count 0 2006.201.06:35:57.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:57.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.06:35:57.09#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.06:35:57.09#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.06:35:57.09$vck44/vb=2,5 2006.201.06:35:57.09#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.06:35:57.09#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.06:35:57.09#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:57.09#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:57.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:57.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:57.15#ibcon#enter wrdev, iclass 30, count 2 2006.201.06:35:57.15#ibcon#first serial, iclass 30, count 2 2006.201.06:35:57.15#ibcon#enter sib2, iclass 30, count 2 2006.201.06:35:57.15#ibcon#flushed, iclass 30, count 2 2006.201.06:35:57.15#ibcon#about to write, iclass 30, count 2 2006.201.06:35:57.15#ibcon#wrote, iclass 30, count 2 2006.201.06:35:57.15#ibcon#about to read 3, iclass 30, count 2 2006.201.06:35:57.17#ibcon#read 3, iclass 30, count 2 2006.201.06:35:57.17#ibcon#about to read 4, iclass 30, count 2 2006.201.06:35:57.17#ibcon#read 4, iclass 30, count 2 2006.201.06:35:57.17#ibcon#about to read 5, iclass 30, count 2 2006.201.06:35:57.17#ibcon#read 5, iclass 30, count 2 2006.201.06:35:57.17#ibcon#about to read 6, iclass 30, count 2 2006.201.06:35:57.17#ibcon#read 6, iclass 30, count 2 2006.201.06:35:57.17#ibcon#end of sib2, iclass 30, count 2 2006.201.06:35:57.17#ibcon#*mode == 0, iclass 30, count 2 2006.201.06:35:57.17#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.06:35:57.17#ibcon#[27=AT02-05\r\n] 2006.201.06:35:57.17#ibcon#*before write, iclass 30, count 2 2006.201.06:35:57.17#ibcon#enter sib2, iclass 30, count 2 2006.201.06:35:57.17#ibcon#flushed, iclass 30, count 2 2006.201.06:35:57.17#ibcon#about to write, iclass 30, count 2 2006.201.06:35:57.17#ibcon#wrote, iclass 30, count 2 2006.201.06:35:57.17#ibcon#about to read 3, iclass 30, count 2 2006.201.06:35:57.20#ibcon#read 3, iclass 30, count 2 2006.201.06:35:57.20#ibcon#about to read 4, iclass 30, count 2 2006.201.06:35:57.20#ibcon#read 4, iclass 30, count 2 2006.201.06:35:57.20#ibcon#about to read 5, iclass 30, count 2 2006.201.06:35:57.20#ibcon#read 5, iclass 30, count 2 2006.201.06:35:57.20#ibcon#about to read 6, iclass 30, count 2 2006.201.06:35:57.20#ibcon#read 6, iclass 30, count 2 2006.201.06:35:57.20#ibcon#end of sib2, iclass 30, count 2 2006.201.06:35:57.20#ibcon#*after write, iclass 30, count 2 2006.201.06:35:57.20#ibcon#*before return 0, iclass 30, count 2 2006.201.06:35:57.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:57.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.06:35:57.20#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.06:35:57.20#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:57.20#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:57.32#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:57.32#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:57.32#ibcon#enter wrdev, iclass 30, count 0 2006.201.06:35:57.32#ibcon#first serial, iclass 30, count 0 2006.201.06:35:57.32#ibcon#enter sib2, iclass 30, count 0 2006.201.06:35:57.32#ibcon#flushed, iclass 30, count 0 2006.201.06:35:57.32#ibcon#about to write, iclass 30, count 0 2006.201.06:35:57.32#ibcon#wrote, iclass 30, count 0 2006.201.06:35:57.32#ibcon#about to read 3, iclass 30, count 0 2006.201.06:35:57.34#ibcon#read 3, iclass 30, count 0 2006.201.06:35:57.34#ibcon#about to read 4, iclass 30, count 0 2006.201.06:35:57.34#ibcon#read 4, iclass 30, count 0 2006.201.06:35:57.34#ibcon#about to read 5, iclass 30, count 0 2006.201.06:35:57.34#ibcon#read 5, iclass 30, count 0 2006.201.06:35:57.34#ibcon#about to read 6, iclass 30, count 0 2006.201.06:35:57.34#ibcon#read 6, iclass 30, count 0 2006.201.06:35:57.34#ibcon#end of sib2, iclass 30, count 0 2006.201.06:35:57.34#ibcon#*mode == 0, iclass 30, count 0 2006.201.06:35:57.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.06:35:57.34#ibcon#[27=USB\r\n] 2006.201.06:35:57.34#ibcon#*before write, iclass 30, count 0 2006.201.06:35:57.34#ibcon#enter sib2, iclass 30, count 0 2006.201.06:35:57.34#ibcon#flushed, iclass 30, count 0 2006.201.06:35:57.34#ibcon#about to write, iclass 30, count 0 2006.201.06:35:57.34#ibcon#wrote, iclass 30, count 0 2006.201.06:35:57.34#ibcon#about to read 3, iclass 30, count 0 2006.201.06:35:57.37#ibcon#read 3, iclass 30, count 0 2006.201.06:35:57.37#ibcon#about to read 4, iclass 30, count 0 2006.201.06:35:57.37#ibcon#read 4, iclass 30, count 0 2006.201.06:35:57.37#ibcon#about to read 5, iclass 30, count 0 2006.201.06:35:57.37#ibcon#read 5, iclass 30, count 0 2006.201.06:35:57.37#ibcon#about to read 6, iclass 30, count 0 2006.201.06:35:57.37#ibcon#read 6, iclass 30, count 0 2006.201.06:35:57.37#ibcon#end of sib2, iclass 30, count 0 2006.201.06:35:57.37#ibcon#*after write, iclass 30, count 0 2006.201.06:35:57.37#ibcon#*before return 0, iclass 30, count 0 2006.201.06:35:57.37#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:57.37#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.06:35:57.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.06:35:57.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.06:35:57.37$vck44/vblo=3,649.99 2006.201.06:35:57.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.06:35:57.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.06:35:57.37#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:57.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:57.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:57.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:57.37#ibcon#enter wrdev, iclass 32, count 0 2006.201.06:35:57.37#ibcon#first serial, iclass 32, count 0 2006.201.06:35:57.37#ibcon#enter sib2, iclass 32, count 0 2006.201.06:35:57.37#ibcon#flushed, iclass 32, count 0 2006.201.06:35:57.37#ibcon#about to write, iclass 32, count 0 2006.201.06:35:57.37#ibcon#wrote, iclass 32, count 0 2006.201.06:35:57.37#ibcon#about to read 3, iclass 32, count 0 2006.201.06:35:57.39#ibcon#read 3, iclass 32, count 0 2006.201.06:35:57.39#ibcon#about to read 4, iclass 32, count 0 2006.201.06:35:57.39#ibcon#read 4, iclass 32, count 0 2006.201.06:35:57.39#ibcon#about to read 5, iclass 32, count 0 2006.201.06:35:57.39#ibcon#read 5, iclass 32, count 0 2006.201.06:35:57.39#ibcon#about to read 6, iclass 32, count 0 2006.201.06:35:57.39#ibcon#read 6, iclass 32, count 0 2006.201.06:35:57.39#ibcon#end of sib2, iclass 32, count 0 2006.201.06:35:57.39#ibcon#*mode == 0, iclass 32, count 0 2006.201.06:35:57.39#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.06:35:57.39#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.06:35:57.39#ibcon#*before write, iclass 32, count 0 2006.201.06:35:57.39#ibcon#enter sib2, iclass 32, count 0 2006.201.06:35:57.39#ibcon#flushed, iclass 32, count 0 2006.201.06:35:57.39#ibcon#about to write, iclass 32, count 0 2006.201.06:35:57.39#ibcon#wrote, iclass 32, count 0 2006.201.06:35:57.39#ibcon#about to read 3, iclass 32, count 0 2006.201.06:35:57.43#ibcon#read 3, iclass 32, count 0 2006.201.06:35:57.43#ibcon#about to read 4, iclass 32, count 0 2006.201.06:35:57.43#ibcon#read 4, iclass 32, count 0 2006.201.06:35:57.43#ibcon#about to read 5, iclass 32, count 0 2006.201.06:35:57.43#ibcon#read 5, iclass 32, count 0 2006.201.06:35:57.43#ibcon#about to read 6, iclass 32, count 0 2006.201.06:35:57.43#ibcon#read 6, iclass 32, count 0 2006.201.06:35:57.43#ibcon#end of sib2, iclass 32, count 0 2006.201.06:35:57.43#ibcon#*after write, iclass 32, count 0 2006.201.06:35:57.43#ibcon#*before return 0, iclass 32, count 0 2006.201.06:35:57.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:57.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.06:35:57.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.06:35:57.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.06:35:57.43$vck44/vb=3,4 2006.201.06:35:57.43#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.06:35:57.43#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.06:35:57.43#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:57.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:57.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:57.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:57.49#ibcon#enter wrdev, iclass 34, count 2 2006.201.06:35:57.49#ibcon#first serial, iclass 34, count 2 2006.201.06:35:57.49#ibcon#enter sib2, iclass 34, count 2 2006.201.06:35:57.49#ibcon#flushed, iclass 34, count 2 2006.201.06:35:57.49#ibcon#about to write, iclass 34, count 2 2006.201.06:35:57.49#ibcon#wrote, iclass 34, count 2 2006.201.06:35:57.49#ibcon#about to read 3, iclass 34, count 2 2006.201.06:35:57.51#ibcon#read 3, iclass 34, count 2 2006.201.06:35:57.51#ibcon#about to read 4, iclass 34, count 2 2006.201.06:35:57.51#ibcon#read 4, iclass 34, count 2 2006.201.06:35:57.51#ibcon#about to read 5, iclass 34, count 2 2006.201.06:35:57.51#ibcon#read 5, iclass 34, count 2 2006.201.06:35:57.51#ibcon#about to read 6, iclass 34, count 2 2006.201.06:35:57.51#ibcon#read 6, iclass 34, count 2 2006.201.06:35:57.51#ibcon#end of sib2, iclass 34, count 2 2006.201.06:35:57.51#ibcon#*mode == 0, iclass 34, count 2 2006.201.06:35:57.51#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.06:35:57.51#ibcon#[27=AT03-04\r\n] 2006.201.06:35:57.51#ibcon#*before write, iclass 34, count 2 2006.201.06:35:57.51#ibcon#enter sib2, iclass 34, count 2 2006.201.06:35:57.51#ibcon#flushed, iclass 34, count 2 2006.201.06:35:57.51#ibcon#about to write, iclass 34, count 2 2006.201.06:35:57.51#ibcon#wrote, iclass 34, count 2 2006.201.06:35:57.51#ibcon#about to read 3, iclass 34, count 2 2006.201.06:35:57.54#ibcon#read 3, iclass 34, count 2 2006.201.06:35:57.54#ibcon#about to read 4, iclass 34, count 2 2006.201.06:35:57.54#ibcon#read 4, iclass 34, count 2 2006.201.06:35:57.54#ibcon#about to read 5, iclass 34, count 2 2006.201.06:35:57.54#ibcon#read 5, iclass 34, count 2 2006.201.06:35:57.54#ibcon#about to read 6, iclass 34, count 2 2006.201.06:35:57.54#ibcon#read 6, iclass 34, count 2 2006.201.06:35:57.54#ibcon#end of sib2, iclass 34, count 2 2006.201.06:35:57.54#ibcon#*after write, iclass 34, count 2 2006.201.06:35:57.54#ibcon#*before return 0, iclass 34, count 2 2006.201.06:35:57.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:57.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.06:35:57.54#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.06:35:57.54#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:57.54#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:57.66#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:57.66#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:57.66#ibcon#enter wrdev, iclass 34, count 0 2006.201.06:35:57.66#ibcon#first serial, iclass 34, count 0 2006.201.06:35:57.66#ibcon#enter sib2, iclass 34, count 0 2006.201.06:35:57.66#ibcon#flushed, iclass 34, count 0 2006.201.06:35:57.66#ibcon#about to write, iclass 34, count 0 2006.201.06:35:57.66#ibcon#wrote, iclass 34, count 0 2006.201.06:35:57.66#ibcon#about to read 3, iclass 34, count 0 2006.201.06:35:57.68#ibcon#read 3, iclass 34, count 0 2006.201.06:35:57.68#ibcon#about to read 4, iclass 34, count 0 2006.201.06:35:57.68#ibcon#read 4, iclass 34, count 0 2006.201.06:35:57.68#ibcon#about to read 5, iclass 34, count 0 2006.201.06:35:57.68#ibcon#read 5, iclass 34, count 0 2006.201.06:35:57.68#ibcon#about to read 6, iclass 34, count 0 2006.201.06:35:57.68#ibcon#read 6, iclass 34, count 0 2006.201.06:35:57.68#ibcon#end of sib2, iclass 34, count 0 2006.201.06:35:57.68#ibcon#*mode == 0, iclass 34, count 0 2006.201.06:35:57.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.06:35:57.68#ibcon#[27=USB\r\n] 2006.201.06:35:57.68#ibcon#*before write, iclass 34, count 0 2006.201.06:35:57.68#ibcon#enter sib2, iclass 34, count 0 2006.201.06:35:57.68#ibcon#flushed, iclass 34, count 0 2006.201.06:35:57.68#ibcon#about to write, iclass 34, count 0 2006.201.06:35:57.68#ibcon#wrote, iclass 34, count 0 2006.201.06:35:57.68#ibcon#about to read 3, iclass 34, count 0 2006.201.06:35:57.71#ibcon#read 3, iclass 34, count 0 2006.201.06:35:57.71#ibcon#about to read 4, iclass 34, count 0 2006.201.06:35:57.71#ibcon#read 4, iclass 34, count 0 2006.201.06:35:57.71#ibcon#about to read 5, iclass 34, count 0 2006.201.06:35:57.71#ibcon#read 5, iclass 34, count 0 2006.201.06:35:57.71#ibcon#about to read 6, iclass 34, count 0 2006.201.06:35:57.71#ibcon#read 6, iclass 34, count 0 2006.201.06:35:57.71#ibcon#end of sib2, iclass 34, count 0 2006.201.06:35:57.71#ibcon#*after write, iclass 34, count 0 2006.201.06:35:57.71#ibcon#*before return 0, iclass 34, count 0 2006.201.06:35:57.71#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:57.71#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.06:35:57.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.06:35:57.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.06:35:57.71$vck44/vblo=4,679.99 2006.201.06:35:57.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.06:35:57.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.06:35:57.71#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:57.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:57.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:57.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:57.71#ibcon#enter wrdev, iclass 36, count 0 2006.201.06:35:57.71#ibcon#first serial, iclass 36, count 0 2006.201.06:35:57.71#ibcon#enter sib2, iclass 36, count 0 2006.201.06:35:57.71#ibcon#flushed, iclass 36, count 0 2006.201.06:35:57.71#ibcon#about to write, iclass 36, count 0 2006.201.06:35:57.71#ibcon#wrote, iclass 36, count 0 2006.201.06:35:57.71#ibcon#about to read 3, iclass 36, count 0 2006.201.06:35:57.73#ibcon#read 3, iclass 36, count 0 2006.201.06:35:57.73#ibcon#about to read 4, iclass 36, count 0 2006.201.06:35:57.73#ibcon#read 4, iclass 36, count 0 2006.201.06:35:57.73#ibcon#about to read 5, iclass 36, count 0 2006.201.06:35:57.73#ibcon#read 5, iclass 36, count 0 2006.201.06:35:57.73#ibcon#about to read 6, iclass 36, count 0 2006.201.06:35:57.73#ibcon#read 6, iclass 36, count 0 2006.201.06:35:57.73#ibcon#end of sib2, iclass 36, count 0 2006.201.06:35:57.73#ibcon#*mode == 0, iclass 36, count 0 2006.201.06:35:57.73#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.06:35:57.73#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.06:35:57.73#ibcon#*before write, iclass 36, count 0 2006.201.06:35:57.73#ibcon#enter sib2, iclass 36, count 0 2006.201.06:35:57.73#ibcon#flushed, iclass 36, count 0 2006.201.06:35:57.73#ibcon#about to write, iclass 36, count 0 2006.201.06:35:57.73#ibcon#wrote, iclass 36, count 0 2006.201.06:35:57.73#ibcon#about to read 3, iclass 36, count 0 2006.201.06:35:57.78#ibcon#read 3, iclass 36, count 0 2006.201.06:35:57.78#ibcon#about to read 4, iclass 36, count 0 2006.201.06:35:57.78#ibcon#read 4, iclass 36, count 0 2006.201.06:35:57.78#ibcon#about to read 5, iclass 36, count 0 2006.201.06:35:57.78#ibcon#read 5, iclass 36, count 0 2006.201.06:35:57.78#ibcon#about to read 6, iclass 36, count 0 2006.201.06:35:57.78#ibcon#read 6, iclass 36, count 0 2006.201.06:35:57.78#ibcon#end of sib2, iclass 36, count 0 2006.201.06:35:57.78#ibcon#*after write, iclass 36, count 0 2006.201.06:35:57.78#ibcon#*before return 0, iclass 36, count 0 2006.201.06:35:57.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:57.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.06:35:57.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.06:35:57.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.06:35:57.78$vck44/vb=4,5 2006.201.06:35:57.78#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.06:35:57.78#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.06:35:57.78#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:57.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:57.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:57.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:57.83#ibcon#enter wrdev, iclass 38, count 2 2006.201.06:35:57.83#ibcon#first serial, iclass 38, count 2 2006.201.06:35:57.83#ibcon#enter sib2, iclass 38, count 2 2006.201.06:35:57.83#ibcon#flushed, iclass 38, count 2 2006.201.06:35:57.83#ibcon#about to write, iclass 38, count 2 2006.201.06:35:57.83#ibcon#wrote, iclass 38, count 2 2006.201.06:35:57.83#ibcon#about to read 3, iclass 38, count 2 2006.201.06:35:57.85#ibcon#read 3, iclass 38, count 2 2006.201.06:35:57.85#ibcon#about to read 4, iclass 38, count 2 2006.201.06:35:57.85#ibcon#read 4, iclass 38, count 2 2006.201.06:35:57.85#ibcon#about to read 5, iclass 38, count 2 2006.201.06:35:57.85#ibcon#read 5, iclass 38, count 2 2006.201.06:35:57.85#ibcon#about to read 6, iclass 38, count 2 2006.201.06:35:57.85#ibcon#read 6, iclass 38, count 2 2006.201.06:35:57.85#ibcon#end of sib2, iclass 38, count 2 2006.201.06:35:57.85#ibcon#*mode == 0, iclass 38, count 2 2006.201.06:35:57.85#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.06:35:57.85#ibcon#[27=AT04-05\r\n] 2006.201.06:35:57.85#ibcon#*before write, iclass 38, count 2 2006.201.06:35:57.85#ibcon#enter sib2, iclass 38, count 2 2006.201.06:35:57.85#ibcon#flushed, iclass 38, count 2 2006.201.06:35:57.85#ibcon#about to write, iclass 38, count 2 2006.201.06:35:57.85#ibcon#wrote, iclass 38, count 2 2006.201.06:35:57.85#ibcon#about to read 3, iclass 38, count 2 2006.201.06:35:57.88#ibcon#read 3, iclass 38, count 2 2006.201.06:35:57.88#ibcon#about to read 4, iclass 38, count 2 2006.201.06:35:57.88#ibcon#read 4, iclass 38, count 2 2006.201.06:35:57.88#ibcon#about to read 5, iclass 38, count 2 2006.201.06:35:57.88#ibcon#read 5, iclass 38, count 2 2006.201.06:35:57.88#ibcon#about to read 6, iclass 38, count 2 2006.201.06:35:57.88#ibcon#read 6, iclass 38, count 2 2006.201.06:35:57.88#ibcon#end of sib2, iclass 38, count 2 2006.201.06:35:57.88#ibcon#*after write, iclass 38, count 2 2006.201.06:35:57.88#ibcon#*before return 0, iclass 38, count 2 2006.201.06:35:57.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:57.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.06:35:57.88#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.06:35:57.88#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:57.88#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:58.00#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:58.00#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:58.00#ibcon#enter wrdev, iclass 38, count 0 2006.201.06:35:58.00#ibcon#first serial, iclass 38, count 0 2006.201.06:35:58.00#ibcon#enter sib2, iclass 38, count 0 2006.201.06:35:58.00#ibcon#flushed, iclass 38, count 0 2006.201.06:35:58.00#ibcon#about to write, iclass 38, count 0 2006.201.06:35:58.00#ibcon#wrote, iclass 38, count 0 2006.201.06:35:58.00#ibcon#about to read 3, iclass 38, count 0 2006.201.06:35:58.02#ibcon#read 3, iclass 38, count 0 2006.201.06:35:58.02#ibcon#about to read 4, iclass 38, count 0 2006.201.06:35:58.02#ibcon#read 4, iclass 38, count 0 2006.201.06:35:58.02#ibcon#about to read 5, iclass 38, count 0 2006.201.06:35:58.02#ibcon#read 5, iclass 38, count 0 2006.201.06:35:58.02#ibcon#about to read 6, iclass 38, count 0 2006.201.06:35:58.02#ibcon#read 6, iclass 38, count 0 2006.201.06:35:58.02#ibcon#end of sib2, iclass 38, count 0 2006.201.06:35:58.02#ibcon#*mode == 0, iclass 38, count 0 2006.201.06:35:58.02#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.06:35:58.02#ibcon#[27=USB\r\n] 2006.201.06:35:58.02#ibcon#*before write, iclass 38, count 0 2006.201.06:35:58.02#ibcon#enter sib2, iclass 38, count 0 2006.201.06:35:58.02#ibcon#flushed, iclass 38, count 0 2006.201.06:35:58.02#ibcon#about to write, iclass 38, count 0 2006.201.06:35:58.02#ibcon#wrote, iclass 38, count 0 2006.201.06:35:58.02#ibcon#about to read 3, iclass 38, count 0 2006.201.06:35:58.05#ibcon#read 3, iclass 38, count 0 2006.201.06:35:58.05#ibcon#about to read 4, iclass 38, count 0 2006.201.06:35:58.05#ibcon#read 4, iclass 38, count 0 2006.201.06:35:58.05#ibcon#about to read 5, iclass 38, count 0 2006.201.06:35:58.05#ibcon#read 5, iclass 38, count 0 2006.201.06:35:58.05#ibcon#about to read 6, iclass 38, count 0 2006.201.06:35:58.05#ibcon#read 6, iclass 38, count 0 2006.201.06:35:58.05#ibcon#end of sib2, iclass 38, count 0 2006.201.06:35:58.05#ibcon#*after write, iclass 38, count 0 2006.201.06:35:58.05#ibcon#*before return 0, iclass 38, count 0 2006.201.06:35:58.05#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:58.05#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.06:35:58.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.06:35:58.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.06:35:58.05$vck44/vblo=5,709.99 2006.201.06:35:58.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.06:35:58.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.06:35:58.05#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:58.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:58.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:58.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:58.05#ibcon#enter wrdev, iclass 40, count 0 2006.201.06:35:58.05#ibcon#first serial, iclass 40, count 0 2006.201.06:35:58.05#ibcon#enter sib2, iclass 40, count 0 2006.201.06:35:58.05#ibcon#flushed, iclass 40, count 0 2006.201.06:35:58.05#ibcon#about to write, iclass 40, count 0 2006.201.06:35:58.05#ibcon#wrote, iclass 40, count 0 2006.201.06:35:58.05#ibcon#about to read 3, iclass 40, count 0 2006.201.06:35:58.07#ibcon#read 3, iclass 40, count 0 2006.201.06:35:58.07#ibcon#about to read 4, iclass 40, count 0 2006.201.06:35:58.07#ibcon#read 4, iclass 40, count 0 2006.201.06:35:58.07#ibcon#about to read 5, iclass 40, count 0 2006.201.06:35:58.07#ibcon#read 5, iclass 40, count 0 2006.201.06:35:58.07#ibcon#about to read 6, iclass 40, count 0 2006.201.06:35:58.07#ibcon#read 6, iclass 40, count 0 2006.201.06:35:58.07#ibcon#end of sib2, iclass 40, count 0 2006.201.06:35:58.07#ibcon#*mode == 0, iclass 40, count 0 2006.201.06:35:58.07#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.06:35:58.07#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.06:35:58.07#ibcon#*before write, iclass 40, count 0 2006.201.06:35:58.07#ibcon#enter sib2, iclass 40, count 0 2006.201.06:35:58.07#ibcon#flushed, iclass 40, count 0 2006.201.06:35:58.07#ibcon#about to write, iclass 40, count 0 2006.201.06:35:58.07#ibcon#wrote, iclass 40, count 0 2006.201.06:35:58.07#ibcon#about to read 3, iclass 40, count 0 2006.201.06:35:58.11#ibcon#read 3, iclass 40, count 0 2006.201.06:35:58.11#ibcon#about to read 4, iclass 40, count 0 2006.201.06:35:58.11#ibcon#read 4, iclass 40, count 0 2006.201.06:35:58.11#ibcon#about to read 5, iclass 40, count 0 2006.201.06:35:58.11#ibcon#read 5, iclass 40, count 0 2006.201.06:35:58.11#ibcon#about to read 6, iclass 40, count 0 2006.201.06:35:58.11#ibcon#read 6, iclass 40, count 0 2006.201.06:35:58.11#ibcon#end of sib2, iclass 40, count 0 2006.201.06:35:58.11#ibcon#*after write, iclass 40, count 0 2006.201.06:35:58.11#ibcon#*before return 0, iclass 40, count 0 2006.201.06:35:58.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:58.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:35:58.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.06:35:58.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.06:35:58.11$vck44/vb=5,4 2006.201.06:35:58.11#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.06:35:58.11#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.06:35:58.11#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:58.11#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:58.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:58.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:58.17#ibcon#enter wrdev, iclass 4, count 2 2006.201.06:35:58.17#ibcon#first serial, iclass 4, count 2 2006.201.06:35:58.17#ibcon#enter sib2, iclass 4, count 2 2006.201.06:35:58.17#ibcon#flushed, iclass 4, count 2 2006.201.06:35:58.17#ibcon#about to write, iclass 4, count 2 2006.201.06:35:58.17#ibcon#wrote, iclass 4, count 2 2006.201.06:35:58.17#ibcon#about to read 3, iclass 4, count 2 2006.201.06:35:58.19#ibcon#read 3, iclass 4, count 2 2006.201.06:35:58.19#ibcon#about to read 4, iclass 4, count 2 2006.201.06:35:58.19#ibcon#read 4, iclass 4, count 2 2006.201.06:35:58.19#ibcon#about to read 5, iclass 4, count 2 2006.201.06:35:58.19#ibcon#read 5, iclass 4, count 2 2006.201.06:35:58.19#ibcon#about to read 6, iclass 4, count 2 2006.201.06:35:58.19#ibcon#read 6, iclass 4, count 2 2006.201.06:35:58.19#ibcon#end of sib2, iclass 4, count 2 2006.201.06:35:58.19#ibcon#*mode == 0, iclass 4, count 2 2006.201.06:35:58.19#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.06:35:58.19#ibcon#[27=AT05-04\r\n] 2006.201.06:35:58.19#ibcon#*before write, iclass 4, count 2 2006.201.06:35:58.19#ibcon#enter sib2, iclass 4, count 2 2006.201.06:35:58.19#ibcon#flushed, iclass 4, count 2 2006.201.06:35:58.19#ibcon#about to write, iclass 4, count 2 2006.201.06:35:58.19#ibcon#wrote, iclass 4, count 2 2006.201.06:35:58.19#ibcon#about to read 3, iclass 4, count 2 2006.201.06:35:58.22#ibcon#read 3, iclass 4, count 2 2006.201.06:35:58.22#ibcon#about to read 4, iclass 4, count 2 2006.201.06:35:58.22#ibcon#read 4, iclass 4, count 2 2006.201.06:35:58.22#ibcon#about to read 5, iclass 4, count 2 2006.201.06:35:58.22#ibcon#read 5, iclass 4, count 2 2006.201.06:35:58.22#ibcon#about to read 6, iclass 4, count 2 2006.201.06:35:58.22#ibcon#read 6, iclass 4, count 2 2006.201.06:35:58.22#ibcon#end of sib2, iclass 4, count 2 2006.201.06:35:58.22#ibcon#*after write, iclass 4, count 2 2006.201.06:35:58.22#ibcon#*before return 0, iclass 4, count 2 2006.201.06:35:58.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:58.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.06:35:58.22#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.06:35:58.22#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:58.22#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:58.34#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:58.34#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:58.34#ibcon#enter wrdev, iclass 4, count 0 2006.201.06:35:58.34#ibcon#first serial, iclass 4, count 0 2006.201.06:35:58.34#ibcon#enter sib2, iclass 4, count 0 2006.201.06:35:58.34#ibcon#flushed, iclass 4, count 0 2006.201.06:35:58.34#ibcon#about to write, iclass 4, count 0 2006.201.06:35:58.34#ibcon#wrote, iclass 4, count 0 2006.201.06:35:58.34#ibcon#about to read 3, iclass 4, count 0 2006.201.06:35:58.36#ibcon#read 3, iclass 4, count 0 2006.201.06:35:58.36#ibcon#about to read 4, iclass 4, count 0 2006.201.06:35:58.36#ibcon#read 4, iclass 4, count 0 2006.201.06:35:58.36#ibcon#about to read 5, iclass 4, count 0 2006.201.06:35:58.36#ibcon#read 5, iclass 4, count 0 2006.201.06:35:58.36#ibcon#about to read 6, iclass 4, count 0 2006.201.06:35:58.36#ibcon#read 6, iclass 4, count 0 2006.201.06:35:58.36#ibcon#end of sib2, iclass 4, count 0 2006.201.06:35:58.36#ibcon#*mode == 0, iclass 4, count 0 2006.201.06:35:58.36#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.06:35:58.36#ibcon#[27=USB\r\n] 2006.201.06:35:58.36#ibcon#*before write, iclass 4, count 0 2006.201.06:35:58.36#ibcon#enter sib2, iclass 4, count 0 2006.201.06:35:58.36#ibcon#flushed, iclass 4, count 0 2006.201.06:35:58.36#ibcon#about to write, iclass 4, count 0 2006.201.06:35:58.36#ibcon#wrote, iclass 4, count 0 2006.201.06:35:58.36#ibcon#about to read 3, iclass 4, count 0 2006.201.06:35:58.39#ibcon#read 3, iclass 4, count 0 2006.201.06:35:58.39#ibcon#about to read 4, iclass 4, count 0 2006.201.06:35:58.39#ibcon#read 4, iclass 4, count 0 2006.201.06:35:58.39#ibcon#about to read 5, iclass 4, count 0 2006.201.06:35:58.39#ibcon#read 5, iclass 4, count 0 2006.201.06:35:58.39#ibcon#about to read 6, iclass 4, count 0 2006.201.06:35:58.39#ibcon#read 6, iclass 4, count 0 2006.201.06:35:58.39#ibcon#end of sib2, iclass 4, count 0 2006.201.06:35:58.39#ibcon#*after write, iclass 4, count 0 2006.201.06:35:58.39#ibcon#*before return 0, iclass 4, count 0 2006.201.06:35:58.39#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:58.39#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.06:35:58.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.06:35:58.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.06:35:58.39$vck44/vblo=6,719.99 2006.201.06:35:58.39#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.06:35:58.39#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.06:35:58.39#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:58.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:58.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:58.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:58.39#ibcon#enter wrdev, iclass 6, count 0 2006.201.06:35:58.39#ibcon#first serial, iclass 6, count 0 2006.201.06:35:58.39#ibcon#enter sib2, iclass 6, count 0 2006.201.06:35:58.39#ibcon#flushed, iclass 6, count 0 2006.201.06:35:58.39#ibcon#about to write, iclass 6, count 0 2006.201.06:35:58.39#ibcon#wrote, iclass 6, count 0 2006.201.06:35:58.39#ibcon#about to read 3, iclass 6, count 0 2006.201.06:35:58.41#ibcon#read 3, iclass 6, count 0 2006.201.06:35:58.41#ibcon#about to read 4, iclass 6, count 0 2006.201.06:35:58.41#ibcon#read 4, iclass 6, count 0 2006.201.06:35:58.41#ibcon#about to read 5, iclass 6, count 0 2006.201.06:35:58.41#ibcon#read 5, iclass 6, count 0 2006.201.06:35:58.41#ibcon#about to read 6, iclass 6, count 0 2006.201.06:35:58.41#ibcon#read 6, iclass 6, count 0 2006.201.06:35:58.41#ibcon#end of sib2, iclass 6, count 0 2006.201.06:35:58.41#ibcon#*mode == 0, iclass 6, count 0 2006.201.06:35:58.41#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.06:35:58.41#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.06:35:58.41#ibcon#*before write, iclass 6, count 0 2006.201.06:35:58.41#ibcon#enter sib2, iclass 6, count 0 2006.201.06:35:58.41#ibcon#flushed, iclass 6, count 0 2006.201.06:35:58.41#ibcon#about to write, iclass 6, count 0 2006.201.06:35:58.41#ibcon#wrote, iclass 6, count 0 2006.201.06:35:58.41#ibcon#about to read 3, iclass 6, count 0 2006.201.06:35:58.46#ibcon#read 3, iclass 6, count 0 2006.201.06:35:58.46#ibcon#about to read 4, iclass 6, count 0 2006.201.06:35:58.46#ibcon#read 4, iclass 6, count 0 2006.201.06:35:58.46#ibcon#about to read 5, iclass 6, count 0 2006.201.06:35:58.46#ibcon#read 5, iclass 6, count 0 2006.201.06:35:58.46#ibcon#about to read 6, iclass 6, count 0 2006.201.06:35:58.46#ibcon#read 6, iclass 6, count 0 2006.201.06:35:58.46#ibcon#end of sib2, iclass 6, count 0 2006.201.06:35:58.46#ibcon#*after write, iclass 6, count 0 2006.201.06:35:58.46#ibcon#*before return 0, iclass 6, count 0 2006.201.06:35:58.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:58.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.06:35:58.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.06:35:58.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.06:35:58.46$vck44/vb=6,4 2006.201.06:35:58.46#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.06:35:58.46#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.06:35:58.46#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:58.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:58.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:58.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:58.51#ibcon#enter wrdev, iclass 10, count 2 2006.201.06:35:58.51#ibcon#first serial, iclass 10, count 2 2006.201.06:35:58.51#ibcon#enter sib2, iclass 10, count 2 2006.201.06:35:58.51#ibcon#flushed, iclass 10, count 2 2006.201.06:35:58.51#ibcon#about to write, iclass 10, count 2 2006.201.06:35:58.51#ibcon#wrote, iclass 10, count 2 2006.201.06:35:58.51#ibcon#about to read 3, iclass 10, count 2 2006.201.06:35:58.53#ibcon#read 3, iclass 10, count 2 2006.201.06:35:58.53#ibcon#about to read 4, iclass 10, count 2 2006.201.06:35:58.53#ibcon#read 4, iclass 10, count 2 2006.201.06:35:58.53#ibcon#about to read 5, iclass 10, count 2 2006.201.06:35:58.53#ibcon#read 5, iclass 10, count 2 2006.201.06:35:58.53#ibcon#about to read 6, iclass 10, count 2 2006.201.06:35:58.53#ibcon#read 6, iclass 10, count 2 2006.201.06:35:58.53#ibcon#end of sib2, iclass 10, count 2 2006.201.06:35:58.53#ibcon#*mode == 0, iclass 10, count 2 2006.201.06:35:58.53#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.06:35:58.53#ibcon#[27=AT06-04\r\n] 2006.201.06:35:58.53#ibcon#*before write, iclass 10, count 2 2006.201.06:35:58.53#ibcon#enter sib2, iclass 10, count 2 2006.201.06:35:58.53#ibcon#flushed, iclass 10, count 2 2006.201.06:35:58.53#ibcon#about to write, iclass 10, count 2 2006.201.06:35:58.53#ibcon#wrote, iclass 10, count 2 2006.201.06:35:58.53#ibcon#about to read 3, iclass 10, count 2 2006.201.06:35:58.56#ibcon#read 3, iclass 10, count 2 2006.201.06:35:58.56#ibcon#about to read 4, iclass 10, count 2 2006.201.06:35:58.56#ibcon#read 4, iclass 10, count 2 2006.201.06:35:58.56#ibcon#about to read 5, iclass 10, count 2 2006.201.06:35:58.56#ibcon#read 5, iclass 10, count 2 2006.201.06:35:58.56#ibcon#about to read 6, iclass 10, count 2 2006.201.06:35:58.56#ibcon#read 6, iclass 10, count 2 2006.201.06:35:58.56#ibcon#end of sib2, iclass 10, count 2 2006.201.06:35:58.56#ibcon#*after write, iclass 10, count 2 2006.201.06:35:58.56#ibcon#*before return 0, iclass 10, count 2 2006.201.06:35:58.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:58.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.06:35:58.56#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.06:35:58.56#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:58.56#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:58.68#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:58.68#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:58.68#ibcon#enter wrdev, iclass 10, count 0 2006.201.06:35:58.68#ibcon#first serial, iclass 10, count 0 2006.201.06:35:58.68#ibcon#enter sib2, iclass 10, count 0 2006.201.06:35:58.68#ibcon#flushed, iclass 10, count 0 2006.201.06:35:58.68#ibcon#about to write, iclass 10, count 0 2006.201.06:35:58.68#ibcon#wrote, iclass 10, count 0 2006.201.06:35:58.68#ibcon#about to read 3, iclass 10, count 0 2006.201.06:35:58.70#ibcon#read 3, iclass 10, count 0 2006.201.06:35:58.70#ibcon#about to read 4, iclass 10, count 0 2006.201.06:35:58.70#ibcon#read 4, iclass 10, count 0 2006.201.06:35:58.70#ibcon#about to read 5, iclass 10, count 0 2006.201.06:35:58.70#ibcon#read 5, iclass 10, count 0 2006.201.06:35:58.70#ibcon#about to read 6, iclass 10, count 0 2006.201.06:35:58.70#ibcon#read 6, iclass 10, count 0 2006.201.06:35:58.70#ibcon#end of sib2, iclass 10, count 0 2006.201.06:35:58.70#ibcon#*mode == 0, iclass 10, count 0 2006.201.06:35:58.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.06:35:58.70#ibcon#[27=USB\r\n] 2006.201.06:35:58.70#ibcon#*before write, iclass 10, count 0 2006.201.06:35:58.70#ibcon#enter sib2, iclass 10, count 0 2006.201.06:35:58.70#ibcon#flushed, iclass 10, count 0 2006.201.06:35:58.70#ibcon#about to write, iclass 10, count 0 2006.201.06:35:58.70#ibcon#wrote, iclass 10, count 0 2006.201.06:35:58.70#ibcon#about to read 3, iclass 10, count 0 2006.201.06:35:58.73#ibcon#read 3, iclass 10, count 0 2006.201.06:35:58.73#ibcon#about to read 4, iclass 10, count 0 2006.201.06:35:58.73#ibcon#read 4, iclass 10, count 0 2006.201.06:35:58.73#ibcon#about to read 5, iclass 10, count 0 2006.201.06:35:58.73#ibcon#read 5, iclass 10, count 0 2006.201.06:35:58.73#ibcon#about to read 6, iclass 10, count 0 2006.201.06:35:58.73#ibcon#read 6, iclass 10, count 0 2006.201.06:35:58.73#ibcon#end of sib2, iclass 10, count 0 2006.201.06:35:58.73#ibcon#*after write, iclass 10, count 0 2006.201.06:35:58.73#ibcon#*before return 0, iclass 10, count 0 2006.201.06:35:58.73#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:58.73#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.06:35:58.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.06:35:58.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.06:35:58.73$vck44/vblo=7,734.99 2006.201.06:35:58.73#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.06:35:58.73#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.06:35:58.73#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:58.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:58.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:58.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:58.73#ibcon#enter wrdev, iclass 12, count 0 2006.201.06:35:58.73#ibcon#first serial, iclass 12, count 0 2006.201.06:35:58.73#ibcon#enter sib2, iclass 12, count 0 2006.201.06:35:58.73#ibcon#flushed, iclass 12, count 0 2006.201.06:35:58.73#ibcon#about to write, iclass 12, count 0 2006.201.06:35:58.73#ibcon#wrote, iclass 12, count 0 2006.201.06:35:58.73#ibcon#about to read 3, iclass 12, count 0 2006.201.06:35:58.75#ibcon#read 3, iclass 12, count 0 2006.201.06:35:58.75#ibcon#about to read 4, iclass 12, count 0 2006.201.06:35:58.75#ibcon#read 4, iclass 12, count 0 2006.201.06:35:58.75#ibcon#about to read 5, iclass 12, count 0 2006.201.06:35:58.75#ibcon#read 5, iclass 12, count 0 2006.201.06:35:58.75#ibcon#about to read 6, iclass 12, count 0 2006.201.06:35:58.75#ibcon#read 6, iclass 12, count 0 2006.201.06:35:58.75#ibcon#end of sib2, iclass 12, count 0 2006.201.06:35:58.75#ibcon#*mode == 0, iclass 12, count 0 2006.201.06:35:58.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.06:35:58.75#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.06:35:58.75#ibcon#*before write, iclass 12, count 0 2006.201.06:35:58.75#ibcon#enter sib2, iclass 12, count 0 2006.201.06:35:58.75#ibcon#flushed, iclass 12, count 0 2006.201.06:35:58.75#ibcon#about to write, iclass 12, count 0 2006.201.06:35:58.75#ibcon#wrote, iclass 12, count 0 2006.201.06:35:58.75#ibcon#about to read 3, iclass 12, count 0 2006.201.06:35:58.80#ibcon#read 3, iclass 12, count 0 2006.201.06:35:58.80#ibcon#about to read 4, iclass 12, count 0 2006.201.06:35:58.80#ibcon#read 4, iclass 12, count 0 2006.201.06:35:58.80#ibcon#about to read 5, iclass 12, count 0 2006.201.06:35:58.80#ibcon#read 5, iclass 12, count 0 2006.201.06:35:58.80#ibcon#about to read 6, iclass 12, count 0 2006.201.06:35:58.80#ibcon#read 6, iclass 12, count 0 2006.201.06:35:58.80#ibcon#end of sib2, iclass 12, count 0 2006.201.06:35:58.80#ibcon#*after write, iclass 12, count 0 2006.201.06:35:58.80#ibcon#*before return 0, iclass 12, count 0 2006.201.06:35:58.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:58.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.06:35:58.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.06:35:58.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.06:35:58.80$vck44/vb=7,4 2006.201.06:35:58.80#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.06:35:58.80#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.06:35:58.80#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:58.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:58.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:58.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:58.85#ibcon#enter wrdev, iclass 14, count 2 2006.201.06:35:58.85#ibcon#first serial, iclass 14, count 2 2006.201.06:35:58.85#ibcon#enter sib2, iclass 14, count 2 2006.201.06:35:58.85#ibcon#flushed, iclass 14, count 2 2006.201.06:35:58.85#ibcon#about to write, iclass 14, count 2 2006.201.06:35:58.85#ibcon#wrote, iclass 14, count 2 2006.201.06:35:58.85#ibcon#about to read 3, iclass 14, count 2 2006.201.06:35:58.87#ibcon#read 3, iclass 14, count 2 2006.201.06:35:58.87#ibcon#about to read 4, iclass 14, count 2 2006.201.06:35:58.87#ibcon#read 4, iclass 14, count 2 2006.201.06:35:58.87#ibcon#about to read 5, iclass 14, count 2 2006.201.06:35:58.87#ibcon#read 5, iclass 14, count 2 2006.201.06:35:58.87#ibcon#about to read 6, iclass 14, count 2 2006.201.06:35:58.87#ibcon#read 6, iclass 14, count 2 2006.201.06:35:58.87#ibcon#end of sib2, iclass 14, count 2 2006.201.06:35:58.87#ibcon#*mode == 0, iclass 14, count 2 2006.201.06:35:58.87#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.06:35:58.87#ibcon#[27=AT07-04\r\n] 2006.201.06:35:58.87#ibcon#*before write, iclass 14, count 2 2006.201.06:35:58.87#ibcon#enter sib2, iclass 14, count 2 2006.201.06:35:58.87#ibcon#flushed, iclass 14, count 2 2006.201.06:35:58.87#ibcon#about to write, iclass 14, count 2 2006.201.06:35:58.87#ibcon#wrote, iclass 14, count 2 2006.201.06:35:58.87#ibcon#about to read 3, iclass 14, count 2 2006.201.06:35:58.90#ibcon#read 3, iclass 14, count 2 2006.201.06:35:58.90#ibcon#about to read 4, iclass 14, count 2 2006.201.06:35:58.90#ibcon#read 4, iclass 14, count 2 2006.201.06:35:58.90#ibcon#about to read 5, iclass 14, count 2 2006.201.06:35:58.90#ibcon#read 5, iclass 14, count 2 2006.201.06:35:58.90#ibcon#about to read 6, iclass 14, count 2 2006.201.06:35:58.90#ibcon#read 6, iclass 14, count 2 2006.201.06:35:58.90#ibcon#end of sib2, iclass 14, count 2 2006.201.06:35:58.90#ibcon#*after write, iclass 14, count 2 2006.201.06:35:58.90#ibcon#*before return 0, iclass 14, count 2 2006.201.06:35:58.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:58.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.06:35:58.90#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.06:35:58.90#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:58.90#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:59.02#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:59.02#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:59.02#ibcon#enter wrdev, iclass 14, count 0 2006.201.06:35:59.02#ibcon#first serial, iclass 14, count 0 2006.201.06:35:59.02#ibcon#enter sib2, iclass 14, count 0 2006.201.06:35:59.02#ibcon#flushed, iclass 14, count 0 2006.201.06:35:59.02#ibcon#about to write, iclass 14, count 0 2006.201.06:35:59.02#ibcon#wrote, iclass 14, count 0 2006.201.06:35:59.02#ibcon#about to read 3, iclass 14, count 0 2006.201.06:35:59.04#ibcon#read 3, iclass 14, count 0 2006.201.06:35:59.04#ibcon#about to read 4, iclass 14, count 0 2006.201.06:35:59.04#ibcon#read 4, iclass 14, count 0 2006.201.06:35:59.04#ibcon#about to read 5, iclass 14, count 0 2006.201.06:35:59.04#ibcon#read 5, iclass 14, count 0 2006.201.06:35:59.04#ibcon#about to read 6, iclass 14, count 0 2006.201.06:35:59.04#ibcon#read 6, iclass 14, count 0 2006.201.06:35:59.04#ibcon#end of sib2, iclass 14, count 0 2006.201.06:35:59.04#ibcon#*mode == 0, iclass 14, count 0 2006.201.06:35:59.04#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.06:35:59.04#ibcon#[27=USB\r\n] 2006.201.06:35:59.04#ibcon#*before write, iclass 14, count 0 2006.201.06:35:59.04#ibcon#enter sib2, iclass 14, count 0 2006.201.06:35:59.04#ibcon#flushed, iclass 14, count 0 2006.201.06:35:59.04#ibcon#about to write, iclass 14, count 0 2006.201.06:35:59.04#ibcon#wrote, iclass 14, count 0 2006.201.06:35:59.04#ibcon#about to read 3, iclass 14, count 0 2006.201.06:35:59.07#ibcon#read 3, iclass 14, count 0 2006.201.06:35:59.07#ibcon#about to read 4, iclass 14, count 0 2006.201.06:35:59.07#ibcon#read 4, iclass 14, count 0 2006.201.06:35:59.07#ibcon#about to read 5, iclass 14, count 0 2006.201.06:35:59.07#ibcon#read 5, iclass 14, count 0 2006.201.06:35:59.07#ibcon#about to read 6, iclass 14, count 0 2006.201.06:35:59.07#ibcon#read 6, iclass 14, count 0 2006.201.06:35:59.07#ibcon#end of sib2, iclass 14, count 0 2006.201.06:35:59.07#ibcon#*after write, iclass 14, count 0 2006.201.06:35:59.07#ibcon#*before return 0, iclass 14, count 0 2006.201.06:35:59.07#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:59.07#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.06:35:59.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.06:35:59.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.06:35:59.07$vck44/vblo=8,744.99 2006.201.06:35:59.07#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.06:35:59.07#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.06:35:59.07#ibcon#ireg 17 cls_cnt 0 2006.201.06:35:59.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:59.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:59.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:59.07#ibcon#enter wrdev, iclass 16, count 0 2006.201.06:35:59.07#ibcon#first serial, iclass 16, count 0 2006.201.06:35:59.07#ibcon#enter sib2, iclass 16, count 0 2006.201.06:35:59.07#ibcon#flushed, iclass 16, count 0 2006.201.06:35:59.07#ibcon#about to write, iclass 16, count 0 2006.201.06:35:59.07#ibcon#wrote, iclass 16, count 0 2006.201.06:35:59.07#ibcon#about to read 3, iclass 16, count 0 2006.201.06:35:59.09#ibcon#read 3, iclass 16, count 0 2006.201.06:35:59.09#ibcon#about to read 4, iclass 16, count 0 2006.201.06:35:59.09#ibcon#read 4, iclass 16, count 0 2006.201.06:35:59.09#ibcon#about to read 5, iclass 16, count 0 2006.201.06:35:59.09#ibcon#read 5, iclass 16, count 0 2006.201.06:35:59.09#ibcon#about to read 6, iclass 16, count 0 2006.201.06:35:59.09#ibcon#read 6, iclass 16, count 0 2006.201.06:35:59.09#ibcon#end of sib2, iclass 16, count 0 2006.201.06:35:59.09#ibcon#*mode == 0, iclass 16, count 0 2006.201.06:35:59.09#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.06:35:59.09#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.06:35:59.09#ibcon#*before write, iclass 16, count 0 2006.201.06:35:59.09#ibcon#enter sib2, iclass 16, count 0 2006.201.06:35:59.09#ibcon#flushed, iclass 16, count 0 2006.201.06:35:59.09#ibcon#about to write, iclass 16, count 0 2006.201.06:35:59.09#ibcon#wrote, iclass 16, count 0 2006.201.06:35:59.09#ibcon#about to read 3, iclass 16, count 0 2006.201.06:35:59.13#ibcon#read 3, iclass 16, count 0 2006.201.06:35:59.13#ibcon#about to read 4, iclass 16, count 0 2006.201.06:35:59.13#ibcon#read 4, iclass 16, count 0 2006.201.06:35:59.13#ibcon#about to read 5, iclass 16, count 0 2006.201.06:35:59.13#ibcon#read 5, iclass 16, count 0 2006.201.06:35:59.13#ibcon#about to read 6, iclass 16, count 0 2006.201.06:35:59.13#ibcon#read 6, iclass 16, count 0 2006.201.06:35:59.13#ibcon#end of sib2, iclass 16, count 0 2006.201.06:35:59.13#ibcon#*after write, iclass 16, count 0 2006.201.06:35:59.13#ibcon#*before return 0, iclass 16, count 0 2006.201.06:35:59.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:59.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.06:35:59.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.06:35:59.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.06:35:59.13$vck44/vb=8,4 2006.201.06:35:59.13#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.06:35:59.13#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.06:35:59.13#ibcon#ireg 11 cls_cnt 2 2006.201.06:35:59.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:59.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:59.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:59.19#ibcon#enter wrdev, iclass 18, count 2 2006.201.06:35:59.19#ibcon#first serial, iclass 18, count 2 2006.201.06:35:59.19#ibcon#enter sib2, iclass 18, count 2 2006.201.06:35:59.19#ibcon#flushed, iclass 18, count 2 2006.201.06:35:59.19#ibcon#about to write, iclass 18, count 2 2006.201.06:35:59.19#ibcon#wrote, iclass 18, count 2 2006.201.06:35:59.19#ibcon#about to read 3, iclass 18, count 2 2006.201.06:35:59.21#ibcon#read 3, iclass 18, count 2 2006.201.06:35:59.21#ibcon#about to read 4, iclass 18, count 2 2006.201.06:35:59.21#ibcon#read 4, iclass 18, count 2 2006.201.06:35:59.21#ibcon#about to read 5, iclass 18, count 2 2006.201.06:35:59.21#ibcon#read 5, iclass 18, count 2 2006.201.06:35:59.21#ibcon#about to read 6, iclass 18, count 2 2006.201.06:35:59.21#ibcon#read 6, iclass 18, count 2 2006.201.06:35:59.21#ibcon#end of sib2, iclass 18, count 2 2006.201.06:35:59.21#ibcon#*mode == 0, iclass 18, count 2 2006.201.06:35:59.21#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.06:35:59.21#ibcon#[27=AT08-04\r\n] 2006.201.06:35:59.21#ibcon#*before write, iclass 18, count 2 2006.201.06:35:59.21#ibcon#enter sib2, iclass 18, count 2 2006.201.06:35:59.21#ibcon#flushed, iclass 18, count 2 2006.201.06:35:59.21#ibcon#about to write, iclass 18, count 2 2006.201.06:35:59.21#ibcon#wrote, iclass 18, count 2 2006.201.06:35:59.21#ibcon#about to read 3, iclass 18, count 2 2006.201.06:35:59.24#ibcon#read 3, iclass 18, count 2 2006.201.06:35:59.24#ibcon#about to read 4, iclass 18, count 2 2006.201.06:35:59.24#ibcon#read 4, iclass 18, count 2 2006.201.06:35:59.24#ibcon#about to read 5, iclass 18, count 2 2006.201.06:35:59.24#ibcon#read 5, iclass 18, count 2 2006.201.06:35:59.24#ibcon#about to read 6, iclass 18, count 2 2006.201.06:35:59.24#ibcon#read 6, iclass 18, count 2 2006.201.06:35:59.24#ibcon#end of sib2, iclass 18, count 2 2006.201.06:35:59.24#ibcon#*after write, iclass 18, count 2 2006.201.06:35:59.24#ibcon#*before return 0, iclass 18, count 2 2006.201.06:35:59.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:59.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.06:35:59.24#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.06:35:59.24#ibcon#ireg 7 cls_cnt 0 2006.201.06:35:59.24#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:59.36#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:59.36#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:59.36#ibcon#enter wrdev, iclass 18, count 0 2006.201.06:35:59.36#ibcon#first serial, iclass 18, count 0 2006.201.06:35:59.36#ibcon#enter sib2, iclass 18, count 0 2006.201.06:35:59.36#ibcon#flushed, iclass 18, count 0 2006.201.06:35:59.36#ibcon#about to write, iclass 18, count 0 2006.201.06:35:59.36#ibcon#wrote, iclass 18, count 0 2006.201.06:35:59.36#ibcon#about to read 3, iclass 18, count 0 2006.201.06:35:59.38#ibcon#read 3, iclass 18, count 0 2006.201.06:35:59.38#ibcon#about to read 4, iclass 18, count 0 2006.201.06:35:59.38#ibcon#read 4, iclass 18, count 0 2006.201.06:35:59.38#ibcon#about to read 5, iclass 18, count 0 2006.201.06:35:59.38#ibcon#read 5, iclass 18, count 0 2006.201.06:35:59.38#ibcon#about to read 6, iclass 18, count 0 2006.201.06:35:59.38#ibcon#read 6, iclass 18, count 0 2006.201.06:35:59.38#ibcon#end of sib2, iclass 18, count 0 2006.201.06:35:59.38#ibcon#*mode == 0, iclass 18, count 0 2006.201.06:35:59.38#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.06:35:59.38#ibcon#[27=USB\r\n] 2006.201.06:35:59.38#ibcon#*before write, iclass 18, count 0 2006.201.06:35:59.38#ibcon#enter sib2, iclass 18, count 0 2006.201.06:35:59.38#ibcon#flushed, iclass 18, count 0 2006.201.06:35:59.38#ibcon#about to write, iclass 18, count 0 2006.201.06:35:59.38#ibcon#wrote, iclass 18, count 0 2006.201.06:35:59.38#ibcon#about to read 3, iclass 18, count 0 2006.201.06:35:59.41#ibcon#read 3, iclass 18, count 0 2006.201.06:35:59.41#ibcon#about to read 4, iclass 18, count 0 2006.201.06:35:59.41#ibcon#read 4, iclass 18, count 0 2006.201.06:35:59.41#ibcon#about to read 5, iclass 18, count 0 2006.201.06:35:59.41#ibcon#read 5, iclass 18, count 0 2006.201.06:35:59.41#ibcon#about to read 6, iclass 18, count 0 2006.201.06:35:59.41#ibcon#read 6, iclass 18, count 0 2006.201.06:35:59.41#ibcon#end of sib2, iclass 18, count 0 2006.201.06:35:59.41#ibcon#*after write, iclass 18, count 0 2006.201.06:35:59.41#ibcon#*before return 0, iclass 18, count 0 2006.201.06:35:59.41#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:59.41#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.06:35:59.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.06:35:59.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.06:35:59.41$vck44/vabw=wide 2006.201.06:35:59.41#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.06:35:59.41#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.06:35:59.41#ibcon#ireg 8 cls_cnt 0 2006.201.06:35:59.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:59.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:59.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:59.41#ibcon#enter wrdev, iclass 20, count 0 2006.201.06:35:59.41#ibcon#first serial, iclass 20, count 0 2006.201.06:35:59.41#ibcon#enter sib2, iclass 20, count 0 2006.201.06:35:59.41#ibcon#flushed, iclass 20, count 0 2006.201.06:35:59.41#ibcon#about to write, iclass 20, count 0 2006.201.06:35:59.41#ibcon#wrote, iclass 20, count 0 2006.201.06:35:59.41#ibcon#about to read 3, iclass 20, count 0 2006.201.06:35:59.43#ibcon#read 3, iclass 20, count 0 2006.201.06:35:59.43#ibcon#about to read 4, iclass 20, count 0 2006.201.06:35:59.43#ibcon#read 4, iclass 20, count 0 2006.201.06:35:59.43#ibcon#about to read 5, iclass 20, count 0 2006.201.06:35:59.43#ibcon#read 5, iclass 20, count 0 2006.201.06:35:59.43#ibcon#about to read 6, iclass 20, count 0 2006.201.06:35:59.43#ibcon#read 6, iclass 20, count 0 2006.201.06:35:59.43#ibcon#end of sib2, iclass 20, count 0 2006.201.06:35:59.43#ibcon#*mode == 0, iclass 20, count 0 2006.201.06:35:59.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.06:35:59.43#ibcon#[25=BW32\r\n] 2006.201.06:35:59.43#ibcon#*before write, iclass 20, count 0 2006.201.06:35:59.43#ibcon#enter sib2, iclass 20, count 0 2006.201.06:35:59.43#ibcon#flushed, iclass 20, count 0 2006.201.06:35:59.43#ibcon#about to write, iclass 20, count 0 2006.201.06:35:59.43#ibcon#wrote, iclass 20, count 0 2006.201.06:35:59.43#ibcon#about to read 3, iclass 20, count 0 2006.201.06:35:59.47#ibcon#read 3, iclass 20, count 0 2006.201.06:35:59.47#ibcon#about to read 4, iclass 20, count 0 2006.201.06:35:59.47#ibcon#read 4, iclass 20, count 0 2006.201.06:35:59.47#ibcon#about to read 5, iclass 20, count 0 2006.201.06:35:59.47#ibcon#read 5, iclass 20, count 0 2006.201.06:35:59.47#ibcon#about to read 6, iclass 20, count 0 2006.201.06:35:59.47#ibcon#read 6, iclass 20, count 0 2006.201.06:35:59.47#ibcon#end of sib2, iclass 20, count 0 2006.201.06:35:59.47#ibcon#*after write, iclass 20, count 0 2006.201.06:35:59.47#ibcon#*before return 0, iclass 20, count 0 2006.201.06:35:59.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:59.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.06:35:59.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.06:35:59.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.06:35:59.47$vck44/vbbw=wide 2006.201.06:35:59.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.06:35:59.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.06:35:59.47#ibcon#ireg 8 cls_cnt 0 2006.201.06:35:59.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:35:59.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:35:59.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:35:59.53#ibcon#enter wrdev, iclass 22, count 0 2006.201.06:35:59.53#ibcon#first serial, iclass 22, count 0 2006.201.06:35:59.53#ibcon#enter sib2, iclass 22, count 0 2006.201.06:35:59.53#ibcon#flushed, iclass 22, count 0 2006.201.06:35:59.53#ibcon#about to write, iclass 22, count 0 2006.201.06:35:59.53#ibcon#wrote, iclass 22, count 0 2006.201.06:35:59.53#ibcon#about to read 3, iclass 22, count 0 2006.201.06:35:59.55#ibcon#read 3, iclass 22, count 0 2006.201.06:35:59.55#ibcon#about to read 4, iclass 22, count 0 2006.201.06:35:59.55#ibcon#read 4, iclass 22, count 0 2006.201.06:35:59.55#ibcon#about to read 5, iclass 22, count 0 2006.201.06:35:59.55#ibcon#read 5, iclass 22, count 0 2006.201.06:35:59.55#ibcon#about to read 6, iclass 22, count 0 2006.201.06:35:59.55#ibcon#read 6, iclass 22, count 0 2006.201.06:35:59.55#ibcon#end of sib2, iclass 22, count 0 2006.201.06:35:59.55#ibcon#*mode == 0, iclass 22, count 0 2006.201.06:35:59.55#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.06:35:59.55#ibcon#[27=BW32\r\n] 2006.201.06:35:59.55#ibcon#*before write, iclass 22, count 0 2006.201.06:35:59.55#ibcon#enter sib2, iclass 22, count 0 2006.201.06:35:59.55#ibcon#flushed, iclass 22, count 0 2006.201.06:35:59.55#ibcon#about to write, iclass 22, count 0 2006.201.06:35:59.55#ibcon#wrote, iclass 22, count 0 2006.201.06:35:59.55#ibcon#about to read 3, iclass 22, count 0 2006.201.06:35:59.58#ibcon#read 3, iclass 22, count 0 2006.201.06:35:59.58#ibcon#about to read 4, iclass 22, count 0 2006.201.06:35:59.58#ibcon#read 4, iclass 22, count 0 2006.201.06:35:59.58#ibcon#about to read 5, iclass 22, count 0 2006.201.06:35:59.58#ibcon#read 5, iclass 22, count 0 2006.201.06:35:59.58#ibcon#about to read 6, iclass 22, count 0 2006.201.06:35:59.58#ibcon#read 6, iclass 22, count 0 2006.201.06:35:59.58#ibcon#end of sib2, iclass 22, count 0 2006.201.06:35:59.58#ibcon#*after write, iclass 22, count 0 2006.201.06:35:59.58#ibcon#*before return 0, iclass 22, count 0 2006.201.06:35:59.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:35:59.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:35:59.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.06:35:59.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.06:35:59.58$setupk4/ifdk4 2006.201.06:35:59.58$ifdk4/lo= 2006.201.06:35:59.58$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.06:35:59.58$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.06:35:59.58$ifdk4/patch= 2006.201.06:35:59.58$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.06:35:59.58$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.06:35:59.58$setupk4/!*+20s 2006.201.06:36:03.29#abcon#<5=/04 2.1 5.2 23.18 871003.3\r\n> 2006.201.06:36:03.31#abcon#{5=INTERFACE CLEAR} 2006.201.06:36:03.37#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:36:13.46#abcon#<5=/04 2.1 5.1 23.18 871003.3\r\n> 2006.201.06:36:13.48#abcon#{5=INTERFACE CLEAR} 2006.201.06:36:13.54#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:36:14.05$setupk4/"tpicd 2006.201.06:36:14.05$setupk4/echo=off 2006.201.06:36:14.05$setupk4/xlog=off 2006.201.06:36:14.05:!2006.201.06:43:36 2006.201.06:36:14.13#trakl#Source acquired 2006.201.06:36:16.13#flagr#flagr/antenna,acquired 2006.201.06:43:36.00:preob 2006.201.06:43:36.14/onsource/TRACKING 2006.201.06:43:36.14:!2006.201.06:43:46 2006.201.06:43:46.00:"tape 2006.201.06:43:46.00:"st=record 2006.201.06:43:46.00:data_valid=on 2006.201.06:43:46.00:midob 2006.201.06:43:46.14/onsource/TRACKING 2006.201.06:43:46.14/wx/23.17,1003.2,88 2006.201.06:43:46.20/cable/+6.4674E-03 2006.201.06:43:47.29/va/01,08,usb,yes,29,31 2006.201.06:43:47.29/va/02,07,usb,yes,31,32 2006.201.06:43:47.29/va/03,08,usb,yes,28,29 2006.201.06:43:47.29/va/04,07,usb,yes,32,33 2006.201.06:43:47.29/va/05,04,usb,yes,28,28 2006.201.06:43:47.29/va/06,05,usb,yes,28,28 2006.201.06:43:47.29/va/07,05,usb,yes,27,28 2006.201.06:43:47.29/va/08,04,usb,yes,27,33 2006.201.06:43:47.52/valo/01,524.99,yes,locked 2006.201.06:43:47.52/valo/02,534.99,yes,locked 2006.201.06:43:47.52/valo/03,564.99,yes,locked 2006.201.06:43:47.52/valo/04,624.99,yes,locked 2006.201.06:43:47.52/valo/05,734.99,yes,locked 2006.201.06:43:47.52/valo/06,814.99,yes,locked 2006.201.06:43:47.52/valo/07,864.99,yes,locked 2006.201.06:43:47.52/valo/08,884.99,yes,locked 2006.201.06:43:48.61/vb/01,04,usb,yes,28,27 2006.201.06:43:48.61/vb/02,05,usb,yes,27,27 2006.201.06:43:48.61/vb/03,04,usb,yes,28,31 2006.201.06:43:48.61/vb/04,05,usb,yes,28,27 2006.201.06:43:48.61/vb/05,04,usb,yes,25,27 2006.201.06:43:48.61/vb/06,04,usb,yes,29,25 2006.201.06:43:48.61/vb/07,04,usb,yes,29,29 2006.201.06:43:48.61/vb/08,04,usb,yes,27,30 2006.201.06:43:48.85/vblo/01,629.99,yes,locked 2006.201.06:43:48.85/vblo/02,634.99,yes,locked 2006.201.06:43:48.85/vblo/03,649.99,yes,locked 2006.201.06:43:48.85/vblo/04,679.99,yes,locked 2006.201.06:43:48.85/vblo/05,709.99,yes,locked 2006.201.06:43:48.85/vblo/06,719.99,yes,locked 2006.201.06:43:48.85/vblo/07,734.99,yes,locked 2006.201.06:43:48.85/vblo/08,744.99,yes,locked 2006.201.06:43:49.00/vabw/8 2006.201.06:43:49.15/vbbw/8 2006.201.06:43:49.24/xfe/off,on,15.0 2006.201.06:43:49.62/ifatt/23,28,28,28 2006.201.06:43:50.05/fmout-gps/S +4.53E-07 2006.201.06:43:50.12:!2006.201.06:45:26 2006.201.06:45:26.00:data_valid=off 2006.201.06:45:26.00:"et 2006.201.06:45:26.00:!+3s 2006.201.06:45:29.02:"tape 2006.201.06:45:29.02:postob 2006.201.06:45:29.10/cable/+6.4665E-03 2006.201.06:45:29.10/wx/23.17,1003.2,89 2006.201.06:45:29.17/fmout-gps/S +4.56E-07 2006.201.06:45:29.17:scan_name=201-0647,jd0607,90 2006.201.06:45:29.17:source=3c274,123049.42,122328.0,2000.0,cw 2006.201.06:45:31.13#flagr#flagr/antenna,new-source 2006.201.06:45:31.13:checkk5 2006.201.06:45:31.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.06:45:31.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.06:45:32.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.06:45:32.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.06:45:33.00/chk_obsdata//k5ts1/T2010643??a.dat file size is correct (nominal:400MB, actual:400MB). 2006.201.06:45:33.36/chk_obsdata//k5ts2/T2010643??b.dat file size is correct (nominal:400MB, actual:400MB). 2006.201.06:45:33.75/chk_obsdata//k5ts3/T2010643??c.dat file size is correct (nominal:400MB, actual:400MB). 2006.201.06:45:34.11/chk_obsdata//k5ts4/T2010643??d.dat file size is correct (nominal:400MB, actual:400MB). 2006.201.06:45:34.80/k5log//k5ts1_log_newline 2006.201.06:45:35.49/k5log//k5ts2_log_newline 2006.201.06:45:36.19/k5log//k5ts3_log_newline 2006.201.06:45:36.88/k5log//k5ts4_log_newline 2006.201.06:45:36.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.06:45:36.90:setupk4=1 2006.201.06:45:36.90$setupk4/echo=on 2006.201.06:45:36.90$setupk4/pcalon 2006.201.06:45:36.90$pcalon/"no phase cal control is implemented here 2006.201.06:45:36.90$setupk4/"tpicd=stop 2006.201.06:45:36.90$setupk4/"rec=synch_on 2006.201.06:45:36.90$setupk4/"rec_mode=128 2006.201.06:45:36.90$setupk4/!* 2006.201.06:45:36.90$setupk4/recpk4 2006.201.06:45:36.90$recpk4/recpatch= 2006.201.06:45:36.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.06:45:36.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.06:45:36.91$setupk4/vck44 2006.201.06:45:36.91$vck44/valo=1,524.99 2006.201.06:45:36.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.06:45:36.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.06:45:36.91#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:36.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:36.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:36.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:36.91#ibcon#enter wrdev, iclass 39, count 0 2006.201.06:45:36.91#ibcon#first serial, iclass 39, count 0 2006.201.06:45:36.91#ibcon#enter sib2, iclass 39, count 0 2006.201.06:45:36.91#ibcon#flushed, iclass 39, count 0 2006.201.06:45:36.91#ibcon#about to write, iclass 39, count 0 2006.201.06:45:36.91#ibcon#wrote, iclass 39, count 0 2006.201.06:45:36.91#ibcon#about to read 3, iclass 39, count 0 2006.201.06:45:36.94#ibcon#read 3, iclass 39, count 0 2006.201.06:45:36.94#ibcon#about to read 4, iclass 39, count 0 2006.201.06:45:36.94#ibcon#read 4, iclass 39, count 0 2006.201.06:45:36.94#ibcon#about to read 5, iclass 39, count 0 2006.201.06:45:36.94#ibcon#read 5, iclass 39, count 0 2006.201.06:45:36.94#ibcon#about to read 6, iclass 39, count 0 2006.201.06:45:36.94#ibcon#read 6, iclass 39, count 0 2006.201.06:45:36.94#ibcon#end of sib2, iclass 39, count 0 2006.201.06:45:36.94#ibcon#*mode == 0, iclass 39, count 0 2006.201.06:45:36.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.06:45:36.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.06:45:36.94#ibcon#*before write, iclass 39, count 0 2006.201.06:45:36.94#ibcon#enter sib2, iclass 39, count 0 2006.201.06:45:36.94#ibcon#flushed, iclass 39, count 0 2006.201.06:45:36.94#ibcon#about to write, iclass 39, count 0 2006.201.06:45:36.94#ibcon#wrote, iclass 39, count 0 2006.201.06:45:36.94#ibcon#about to read 3, iclass 39, count 0 2006.201.06:45:37.00#ibcon#read 3, iclass 39, count 0 2006.201.06:45:37.00#ibcon#about to read 4, iclass 39, count 0 2006.201.06:45:37.00#ibcon#read 4, iclass 39, count 0 2006.201.06:45:37.00#ibcon#about to read 5, iclass 39, count 0 2006.201.06:45:37.00#ibcon#read 5, iclass 39, count 0 2006.201.06:45:37.00#ibcon#about to read 6, iclass 39, count 0 2006.201.06:45:37.00#ibcon#read 6, iclass 39, count 0 2006.201.06:45:37.00#ibcon#end of sib2, iclass 39, count 0 2006.201.06:45:37.00#ibcon#*after write, iclass 39, count 0 2006.201.06:45:37.00#ibcon#*before return 0, iclass 39, count 0 2006.201.06:45:37.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:37.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:37.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.06:45:37.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.06:45:37.00$vck44/va=1,8 2006.201.06:45:37.00#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.06:45:37.00#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.06:45:37.00#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:37.00#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:37.00#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:37.00#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:37.00#ibcon#enter wrdev, iclass 2, count 2 2006.201.06:45:37.00#ibcon#first serial, iclass 2, count 2 2006.201.06:45:37.00#ibcon#enter sib2, iclass 2, count 2 2006.201.06:45:37.00#ibcon#flushed, iclass 2, count 2 2006.201.06:45:37.00#ibcon#about to write, iclass 2, count 2 2006.201.06:45:37.00#ibcon#wrote, iclass 2, count 2 2006.201.06:45:37.00#ibcon#about to read 3, iclass 2, count 2 2006.201.06:45:37.02#ibcon#read 3, iclass 2, count 2 2006.201.06:45:37.02#ibcon#about to read 4, iclass 2, count 2 2006.201.06:45:37.02#ibcon#read 4, iclass 2, count 2 2006.201.06:45:37.02#ibcon#about to read 5, iclass 2, count 2 2006.201.06:45:37.02#ibcon#read 5, iclass 2, count 2 2006.201.06:45:37.02#ibcon#about to read 6, iclass 2, count 2 2006.201.06:45:37.02#ibcon#read 6, iclass 2, count 2 2006.201.06:45:37.02#ibcon#end of sib2, iclass 2, count 2 2006.201.06:45:37.02#ibcon#*mode == 0, iclass 2, count 2 2006.201.06:45:37.02#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.06:45:37.02#ibcon#[25=AT01-08\r\n] 2006.201.06:45:37.02#ibcon#*before write, iclass 2, count 2 2006.201.06:45:37.02#ibcon#enter sib2, iclass 2, count 2 2006.201.06:45:37.02#ibcon#flushed, iclass 2, count 2 2006.201.06:45:37.02#ibcon#about to write, iclass 2, count 2 2006.201.06:45:37.02#ibcon#wrote, iclass 2, count 2 2006.201.06:45:37.02#ibcon#about to read 3, iclass 2, count 2 2006.201.06:45:37.06#ibcon#read 3, iclass 2, count 2 2006.201.06:45:37.06#ibcon#about to read 4, iclass 2, count 2 2006.201.06:45:37.06#ibcon#read 4, iclass 2, count 2 2006.201.06:45:37.06#ibcon#about to read 5, iclass 2, count 2 2006.201.06:45:37.06#ibcon#read 5, iclass 2, count 2 2006.201.06:45:37.06#ibcon#about to read 6, iclass 2, count 2 2006.201.06:45:37.06#ibcon#read 6, iclass 2, count 2 2006.201.06:45:37.06#ibcon#end of sib2, iclass 2, count 2 2006.201.06:45:37.06#ibcon#*after write, iclass 2, count 2 2006.201.06:45:37.06#ibcon#*before return 0, iclass 2, count 2 2006.201.06:45:37.06#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:37.06#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:37.06#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.06:45:37.06#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:37.06#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:37.18#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:37.18#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:37.18#ibcon#enter wrdev, iclass 2, count 0 2006.201.06:45:37.18#ibcon#first serial, iclass 2, count 0 2006.201.06:45:37.18#ibcon#enter sib2, iclass 2, count 0 2006.201.06:45:37.18#ibcon#flushed, iclass 2, count 0 2006.201.06:45:37.18#ibcon#about to write, iclass 2, count 0 2006.201.06:45:37.18#ibcon#wrote, iclass 2, count 0 2006.201.06:45:37.18#ibcon#about to read 3, iclass 2, count 0 2006.201.06:45:37.20#ibcon#read 3, iclass 2, count 0 2006.201.06:45:37.20#ibcon#about to read 4, iclass 2, count 0 2006.201.06:45:37.21#ibcon#read 4, iclass 2, count 0 2006.201.06:45:37.21#ibcon#about to read 5, iclass 2, count 0 2006.201.06:45:37.21#ibcon#read 5, iclass 2, count 0 2006.201.06:45:37.21#ibcon#about to read 6, iclass 2, count 0 2006.201.06:45:37.21#ibcon#read 6, iclass 2, count 0 2006.201.06:45:37.21#ibcon#end of sib2, iclass 2, count 0 2006.201.06:45:37.21#ibcon#*mode == 0, iclass 2, count 0 2006.201.06:45:37.21#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.06:45:37.21#ibcon#[25=USB\r\n] 2006.201.06:45:37.21#ibcon#*before write, iclass 2, count 0 2006.201.06:45:37.21#ibcon#enter sib2, iclass 2, count 0 2006.201.06:45:37.21#ibcon#flushed, iclass 2, count 0 2006.201.06:45:37.21#ibcon#about to write, iclass 2, count 0 2006.201.06:45:37.21#ibcon#wrote, iclass 2, count 0 2006.201.06:45:37.21#ibcon#about to read 3, iclass 2, count 0 2006.201.06:45:37.24#ibcon#read 3, iclass 2, count 0 2006.201.06:45:37.24#ibcon#about to read 4, iclass 2, count 0 2006.201.06:45:37.24#ibcon#read 4, iclass 2, count 0 2006.201.06:45:37.24#ibcon#about to read 5, iclass 2, count 0 2006.201.06:45:37.24#ibcon#read 5, iclass 2, count 0 2006.201.06:45:37.24#ibcon#about to read 6, iclass 2, count 0 2006.201.06:45:37.24#ibcon#read 6, iclass 2, count 0 2006.201.06:45:37.24#ibcon#end of sib2, iclass 2, count 0 2006.201.06:45:37.24#ibcon#*after write, iclass 2, count 0 2006.201.06:45:37.24#ibcon#*before return 0, iclass 2, count 0 2006.201.06:45:37.24#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:37.24#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:37.24#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.06:45:37.24#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.06:45:37.24$vck44/valo=2,534.99 2006.201.06:45:37.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.06:45:37.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.06:45:37.24#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:37.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:37.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:37.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:37.24#ibcon#enter wrdev, iclass 5, count 0 2006.201.06:45:37.24#ibcon#first serial, iclass 5, count 0 2006.201.06:45:37.24#ibcon#enter sib2, iclass 5, count 0 2006.201.06:45:37.24#ibcon#flushed, iclass 5, count 0 2006.201.06:45:37.24#ibcon#about to write, iclass 5, count 0 2006.201.06:45:37.24#ibcon#wrote, iclass 5, count 0 2006.201.06:45:37.24#ibcon#about to read 3, iclass 5, count 0 2006.201.06:45:37.26#ibcon#read 3, iclass 5, count 0 2006.201.06:45:37.26#ibcon#about to read 4, iclass 5, count 0 2006.201.06:45:37.26#ibcon#read 4, iclass 5, count 0 2006.201.06:45:37.26#ibcon#about to read 5, iclass 5, count 0 2006.201.06:45:37.26#ibcon#read 5, iclass 5, count 0 2006.201.06:45:37.26#ibcon#about to read 6, iclass 5, count 0 2006.201.06:45:37.26#ibcon#read 6, iclass 5, count 0 2006.201.06:45:37.26#ibcon#end of sib2, iclass 5, count 0 2006.201.06:45:37.26#ibcon#*mode == 0, iclass 5, count 0 2006.201.06:45:37.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.06:45:37.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.06:45:37.26#ibcon#*before write, iclass 5, count 0 2006.201.06:45:37.26#ibcon#enter sib2, iclass 5, count 0 2006.201.06:45:37.26#ibcon#flushed, iclass 5, count 0 2006.201.06:45:37.26#ibcon#about to write, iclass 5, count 0 2006.201.06:45:37.26#ibcon#wrote, iclass 5, count 0 2006.201.06:45:37.26#ibcon#about to read 3, iclass 5, count 0 2006.201.06:45:37.30#ibcon#read 3, iclass 5, count 0 2006.201.06:45:37.30#ibcon#about to read 4, iclass 5, count 0 2006.201.06:45:37.30#ibcon#read 4, iclass 5, count 0 2006.201.06:45:37.30#ibcon#about to read 5, iclass 5, count 0 2006.201.06:45:37.30#ibcon#read 5, iclass 5, count 0 2006.201.06:45:37.30#ibcon#about to read 6, iclass 5, count 0 2006.201.06:45:37.30#ibcon#read 6, iclass 5, count 0 2006.201.06:45:37.30#ibcon#end of sib2, iclass 5, count 0 2006.201.06:45:37.30#ibcon#*after write, iclass 5, count 0 2006.201.06:45:37.30#ibcon#*before return 0, iclass 5, count 0 2006.201.06:45:37.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:37.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:37.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.06:45:37.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.06:45:37.30$vck44/va=2,7 2006.201.06:45:37.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.06:45:37.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.06:45:37.30#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:37.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:37.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:37.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:37.36#ibcon#enter wrdev, iclass 7, count 2 2006.201.06:45:37.36#ibcon#first serial, iclass 7, count 2 2006.201.06:45:37.36#ibcon#enter sib2, iclass 7, count 2 2006.201.06:45:37.36#ibcon#flushed, iclass 7, count 2 2006.201.06:45:37.36#ibcon#about to write, iclass 7, count 2 2006.201.06:45:37.36#ibcon#wrote, iclass 7, count 2 2006.201.06:45:37.36#ibcon#about to read 3, iclass 7, count 2 2006.201.06:45:37.38#ibcon#read 3, iclass 7, count 2 2006.201.06:45:37.38#ibcon#about to read 4, iclass 7, count 2 2006.201.06:45:37.38#ibcon#read 4, iclass 7, count 2 2006.201.06:45:37.38#ibcon#about to read 5, iclass 7, count 2 2006.201.06:45:37.38#ibcon#read 5, iclass 7, count 2 2006.201.06:45:37.38#ibcon#about to read 6, iclass 7, count 2 2006.201.06:45:37.38#ibcon#read 6, iclass 7, count 2 2006.201.06:45:37.38#ibcon#end of sib2, iclass 7, count 2 2006.201.06:45:37.38#ibcon#*mode == 0, iclass 7, count 2 2006.201.06:45:37.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.06:45:37.38#ibcon#[25=AT02-07\r\n] 2006.201.06:45:37.38#ibcon#*before write, iclass 7, count 2 2006.201.06:45:37.38#ibcon#enter sib2, iclass 7, count 2 2006.201.06:45:37.38#ibcon#flushed, iclass 7, count 2 2006.201.06:45:37.38#ibcon#about to write, iclass 7, count 2 2006.201.06:45:37.38#ibcon#wrote, iclass 7, count 2 2006.201.06:45:37.38#ibcon#about to read 3, iclass 7, count 2 2006.201.06:45:37.41#ibcon#read 3, iclass 7, count 2 2006.201.06:45:37.41#ibcon#about to read 4, iclass 7, count 2 2006.201.06:45:37.41#ibcon#read 4, iclass 7, count 2 2006.201.06:45:37.41#ibcon#about to read 5, iclass 7, count 2 2006.201.06:45:37.41#ibcon#read 5, iclass 7, count 2 2006.201.06:45:37.41#ibcon#about to read 6, iclass 7, count 2 2006.201.06:45:37.41#ibcon#read 6, iclass 7, count 2 2006.201.06:45:37.41#ibcon#end of sib2, iclass 7, count 2 2006.201.06:45:37.41#ibcon#*after write, iclass 7, count 2 2006.201.06:45:37.41#ibcon#*before return 0, iclass 7, count 2 2006.201.06:45:37.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:37.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:37.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.06:45:37.41#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:37.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:37.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:37.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:37.53#ibcon#enter wrdev, iclass 7, count 0 2006.201.06:45:37.53#ibcon#first serial, iclass 7, count 0 2006.201.06:45:37.53#ibcon#enter sib2, iclass 7, count 0 2006.201.06:45:37.53#ibcon#flushed, iclass 7, count 0 2006.201.06:45:37.53#ibcon#about to write, iclass 7, count 0 2006.201.06:45:37.53#ibcon#wrote, iclass 7, count 0 2006.201.06:45:37.53#ibcon#about to read 3, iclass 7, count 0 2006.201.06:45:37.55#ibcon#read 3, iclass 7, count 0 2006.201.06:45:37.55#ibcon#about to read 4, iclass 7, count 0 2006.201.06:45:37.55#ibcon#read 4, iclass 7, count 0 2006.201.06:45:37.55#ibcon#about to read 5, iclass 7, count 0 2006.201.06:45:37.55#ibcon#read 5, iclass 7, count 0 2006.201.06:45:37.55#ibcon#about to read 6, iclass 7, count 0 2006.201.06:45:37.55#ibcon#read 6, iclass 7, count 0 2006.201.06:45:37.55#ibcon#end of sib2, iclass 7, count 0 2006.201.06:45:37.55#ibcon#*mode == 0, iclass 7, count 0 2006.201.06:45:37.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.06:45:37.55#ibcon#[25=USB\r\n] 2006.201.06:45:37.55#ibcon#*before write, iclass 7, count 0 2006.201.06:45:37.55#ibcon#enter sib2, iclass 7, count 0 2006.201.06:45:37.55#ibcon#flushed, iclass 7, count 0 2006.201.06:45:37.55#ibcon#about to write, iclass 7, count 0 2006.201.06:45:37.55#ibcon#wrote, iclass 7, count 0 2006.201.06:45:37.55#ibcon#about to read 3, iclass 7, count 0 2006.201.06:45:37.58#ibcon#read 3, iclass 7, count 0 2006.201.06:45:37.58#ibcon#about to read 4, iclass 7, count 0 2006.201.06:45:37.58#ibcon#read 4, iclass 7, count 0 2006.201.06:45:37.58#ibcon#about to read 5, iclass 7, count 0 2006.201.06:45:37.58#ibcon#read 5, iclass 7, count 0 2006.201.06:45:37.58#ibcon#about to read 6, iclass 7, count 0 2006.201.06:45:37.58#ibcon#read 6, iclass 7, count 0 2006.201.06:45:37.58#ibcon#end of sib2, iclass 7, count 0 2006.201.06:45:37.58#ibcon#*after write, iclass 7, count 0 2006.201.06:45:37.58#ibcon#*before return 0, iclass 7, count 0 2006.201.06:45:37.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:37.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:37.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.06:45:37.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.06:45:37.58$vck44/valo=3,564.99 2006.201.06:45:37.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.06:45:37.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.06:45:37.58#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:37.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:37.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:37.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:37.58#ibcon#enter wrdev, iclass 11, count 0 2006.201.06:45:37.58#ibcon#first serial, iclass 11, count 0 2006.201.06:45:37.58#ibcon#enter sib2, iclass 11, count 0 2006.201.06:45:37.58#ibcon#flushed, iclass 11, count 0 2006.201.06:45:37.58#ibcon#about to write, iclass 11, count 0 2006.201.06:45:37.58#ibcon#wrote, iclass 11, count 0 2006.201.06:45:37.58#ibcon#about to read 3, iclass 11, count 0 2006.201.06:45:37.60#ibcon#read 3, iclass 11, count 0 2006.201.06:45:37.60#ibcon#about to read 4, iclass 11, count 0 2006.201.06:45:37.60#ibcon#read 4, iclass 11, count 0 2006.201.06:45:37.60#ibcon#about to read 5, iclass 11, count 0 2006.201.06:45:37.60#ibcon#read 5, iclass 11, count 0 2006.201.06:45:37.60#ibcon#about to read 6, iclass 11, count 0 2006.201.06:45:37.60#ibcon#read 6, iclass 11, count 0 2006.201.06:45:37.60#ibcon#end of sib2, iclass 11, count 0 2006.201.06:45:37.60#ibcon#*mode == 0, iclass 11, count 0 2006.201.06:45:37.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.06:45:37.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.06:45:37.60#ibcon#*before write, iclass 11, count 0 2006.201.06:45:37.60#ibcon#enter sib2, iclass 11, count 0 2006.201.06:45:37.60#ibcon#flushed, iclass 11, count 0 2006.201.06:45:37.60#ibcon#about to write, iclass 11, count 0 2006.201.06:45:37.60#ibcon#wrote, iclass 11, count 0 2006.201.06:45:37.60#ibcon#about to read 3, iclass 11, count 0 2006.201.06:45:37.65#ibcon#read 3, iclass 11, count 0 2006.201.06:45:37.65#ibcon#about to read 4, iclass 11, count 0 2006.201.06:45:37.65#ibcon#read 4, iclass 11, count 0 2006.201.06:45:37.65#ibcon#about to read 5, iclass 11, count 0 2006.201.06:45:37.65#ibcon#read 5, iclass 11, count 0 2006.201.06:45:37.65#ibcon#about to read 6, iclass 11, count 0 2006.201.06:45:37.65#ibcon#read 6, iclass 11, count 0 2006.201.06:45:37.65#ibcon#end of sib2, iclass 11, count 0 2006.201.06:45:37.65#ibcon#*after write, iclass 11, count 0 2006.201.06:45:37.65#ibcon#*before return 0, iclass 11, count 0 2006.201.06:45:37.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:37.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:37.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.06:45:37.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.06:45:37.65$vck44/va=3,8 2006.201.06:45:37.65#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.06:45:37.65#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.06:45:37.65#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:37.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:37.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:37.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:37.70#ibcon#enter wrdev, iclass 13, count 2 2006.201.06:45:37.70#ibcon#first serial, iclass 13, count 2 2006.201.06:45:37.70#ibcon#enter sib2, iclass 13, count 2 2006.201.06:45:37.70#ibcon#flushed, iclass 13, count 2 2006.201.06:45:37.70#ibcon#about to write, iclass 13, count 2 2006.201.06:45:37.70#ibcon#wrote, iclass 13, count 2 2006.201.06:45:37.70#ibcon#about to read 3, iclass 13, count 2 2006.201.06:45:37.72#ibcon#read 3, iclass 13, count 2 2006.201.06:45:37.72#ibcon#about to read 4, iclass 13, count 2 2006.201.06:45:37.72#ibcon#read 4, iclass 13, count 2 2006.201.06:45:37.72#ibcon#about to read 5, iclass 13, count 2 2006.201.06:45:37.72#ibcon#read 5, iclass 13, count 2 2006.201.06:45:37.72#ibcon#about to read 6, iclass 13, count 2 2006.201.06:45:37.72#ibcon#read 6, iclass 13, count 2 2006.201.06:45:37.72#ibcon#end of sib2, iclass 13, count 2 2006.201.06:45:37.72#ibcon#*mode == 0, iclass 13, count 2 2006.201.06:45:37.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.06:45:37.72#ibcon#[25=AT03-08\r\n] 2006.201.06:45:37.72#ibcon#*before write, iclass 13, count 2 2006.201.06:45:37.72#ibcon#enter sib2, iclass 13, count 2 2006.201.06:45:37.72#ibcon#flushed, iclass 13, count 2 2006.201.06:45:37.72#ibcon#about to write, iclass 13, count 2 2006.201.06:45:37.72#ibcon#wrote, iclass 13, count 2 2006.201.06:45:37.72#ibcon#about to read 3, iclass 13, count 2 2006.201.06:45:37.75#ibcon#read 3, iclass 13, count 2 2006.201.06:45:37.75#ibcon#about to read 4, iclass 13, count 2 2006.201.06:45:37.75#ibcon#read 4, iclass 13, count 2 2006.201.06:45:37.75#ibcon#about to read 5, iclass 13, count 2 2006.201.06:45:37.75#ibcon#read 5, iclass 13, count 2 2006.201.06:45:37.75#ibcon#about to read 6, iclass 13, count 2 2006.201.06:45:37.75#ibcon#read 6, iclass 13, count 2 2006.201.06:45:37.75#ibcon#end of sib2, iclass 13, count 2 2006.201.06:45:37.75#ibcon#*after write, iclass 13, count 2 2006.201.06:45:37.75#ibcon#*before return 0, iclass 13, count 2 2006.201.06:45:37.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:37.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:37.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.06:45:37.75#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:37.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:37.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:37.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:37.87#ibcon#enter wrdev, iclass 13, count 0 2006.201.06:45:37.87#ibcon#first serial, iclass 13, count 0 2006.201.06:45:37.87#ibcon#enter sib2, iclass 13, count 0 2006.201.06:45:37.87#ibcon#flushed, iclass 13, count 0 2006.201.06:45:37.87#ibcon#about to write, iclass 13, count 0 2006.201.06:45:37.87#ibcon#wrote, iclass 13, count 0 2006.201.06:45:37.87#ibcon#about to read 3, iclass 13, count 0 2006.201.06:45:37.89#ibcon#read 3, iclass 13, count 0 2006.201.06:45:37.89#ibcon#about to read 4, iclass 13, count 0 2006.201.06:45:37.89#ibcon#read 4, iclass 13, count 0 2006.201.06:45:37.89#ibcon#about to read 5, iclass 13, count 0 2006.201.06:45:37.89#ibcon#read 5, iclass 13, count 0 2006.201.06:45:37.89#ibcon#about to read 6, iclass 13, count 0 2006.201.06:45:37.89#ibcon#read 6, iclass 13, count 0 2006.201.06:45:37.89#ibcon#end of sib2, iclass 13, count 0 2006.201.06:45:37.89#ibcon#*mode == 0, iclass 13, count 0 2006.201.06:45:37.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.06:45:37.89#ibcon#[25=USB\r\n] 2006.201.06:45:37.89#ibcon#*before write, iclass 13, count 0 2006.201.06:45:37.89#ibcon#enter sib2, iclass 13, count 0 2006.201.06:45:37.89#ibcon#flushed, iclass 13, count 0 2006.201.06:45:37.89#ibcon#about to write, iclass 13, count 0 2006.201.06:45:37.89#ibcon#wrote, iclass 13, count 0 2006.201.06:45:37.89#ibcon#about to read 3, iclass 13, count 0 2006.201.06:45:37.92#ibcon#read 3, iclass 13, count 0 2006.201.06:45:37.92#ibcon#about to read 4, iclass 13, count 0 2006.201.06:45:37.92#ibcon#read 4, iclass 13, count 0 2006.201.06:45:37.92#ibcon#about to read 5, iclass 13, count 0 2006.201.06:45:37.92#ibcon#read 5, iclass 13, count 0 2006.201.06:45:37.92#ibcon#about to read 6, iclass 13, count 0 2006.201.06:45:37.92#ibcon#read 6, iclass 13, count 0 2006.201.06:45:37.92#ibcon#end of sib2, iclass 13, count 0 2006.201.06:45:37.92#ibcon#*after write, iclass 13, count 0 2006.201.06:45:37.92#ibcon#*before return 0, iclass 13, count 0 2006.201.06:45:37.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:37.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:37.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.06:45:37.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.06:45:37.92$vck44/valo=4,624.99 2006.201.06:45:37.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.06:45:37.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.06:45:37.92#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:37.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:37.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:37.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:37.92#ibcon#enter wrdev, iclass 15, count 0 2006.201.06:45:37.92#ibcon#first serial, iclass 15, count 0 2006.201.06:45:37.92#ibcon#enter sib2, iclass 15, count 0 2006.201.06:45:37.92#ibcon#flushed, iclass 15, count 0 2006.201.06:45:37.92#ibcon#about to write, iclass 15, count 0 2006.201.06:45:37.92#ibcon#wrote, iclass 15, count 0 2006.201.06:45:37.92#ibcon#about to read 3, iclass 15, count 0 2006.201.06:45:37.94#ibcon#read 3, iclass 15, count 0 2006.201.06:45:37.94#ibcon#about to read 4, iclass 15, count 0 2006.201.06:45:37.94#ibcon#read 4, iclass 15, count 0 2006.201.06:45:37.94#ibcon#about to read 5, iclass 15, count 0 2006.201.06:45:37.94#ibcon#read 5, iclass 15, count 0 2006.201.06:45:37.94#ibcon#about to read 6, iclass 15, count 0 2006.201.06:45:37.94#ibcon#read 6, iclass 15, count 0 2006.201.06:45:37.94#ibcon#end of sib2, iclass 15, count 0 2006.201.06:45:37.94#ibcon#*mode == 0, iclass 15, count 0 2006.201.06:45:37.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.06:45:37.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.06:45:37.94#ibcon#*before write, iclass 15, count 0 2006.201.06:45:37.94#ibcon#enter sib2, iclass 15, count 0 2006.201.06:45:37.94#ibcon#flushed, iclass 15, count 0 2006.201.06:45:37.94#ibcon#about to write, iclass 15, count 0 2006.201.06:45:37.94#ibcon#wrote, iclass 15, count 0 2006.201.06:45:37.94#ibcon#about to read 3, iclass 15, count 0 2006.201.06:45:37.99#ibcon#read 3, iclass 15, count 0 2006.201.06:45:37.99#ibcon#about to read 4, iclass 15, count 0 2006.201.06:45:37.99#ibcon#read 4, iclass 15, count 0 2006.201.06:45:37.99#ibcon#about to read 5, iclass 15, count 0 2006.201.06:45:37.99#ibcon#read 5, iclass 15, count 0 2006.201.06:45:37.99#ibcon#about to read 6, iclass 15, count 0 2006.201.06:45:37.99#ibcon#read 6, iclass 15, count 0 2006.201.06:45:37.99#ibcon#end of sib2, iclass 15, count 0 2006.201.06:45:37.99#ibcon#*after write, iclass 15, count 0 2006.201.06:45:37.99#ibcon#*before return 0, iclass 15, count 0 2006.201.06:45:37.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:37.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:37.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.06:45:37.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.06:45:37.99$vck44/va=4,7 2006.201.06:45:37.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.06:45:37.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.06:45:37.99#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:37.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:38.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:38.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:38.04#ibcon#enter wrdev, iclass 17, count 2 2006.201.06:45:38.04#ibcon#first serial, iclass 17, count 2 2006.201.06:45:38.04#ibcon#enter sib2, iclass 17, count 2 2006.201.06:45:38.04#ibcon#flushed, iclass 17, count 2 2006.201.06:45:38.04#ibcon#about to write, iclass 17, count 2 2006.201.06:45:38.04#ibcon#wrote, iclass 17, count 2 2006.201.06:45:38.04#ibcon#about to read 3, iclass 17, count 2 2006.201.06:45:38.06#ibcon#read 3, iclass 17, count 2 2006.201.06:45:38.06#ibcon#about to read 4, iclass 17, count 2 2006.201.06:45:38.06#ibcon#read 4, iclass 17, count 2 2006.201.06:45:38.06#ibcon#about to read 5, iclass 17, count 2 2006.201.06:45:38.06#ibcon#read 5, iclass 17, count 2 2006.201.06:45:38.06#ibcon#about to read 6, iclass 17, count 2 2006.201.06:45:38.06#ibcon#read 6, iclass 17, count 2 2006.201.06:45:38.06#ibcon#end of sib2, iclass 17, count 2 2006.201.06:45:38.06#ibcon#*mode == 0, iclass 17, count 2 2006.201.06:45:38.06#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.06:45:38.06#ibcon#[25=AT04-07\r\n] 2006.201.06:45:38.06#ibcon#*before write, iclass 17, count 2 2006.201.06:45:38.06#ibcon#enter sib2, iclass 17, count 2 2006.201.06:45:38.06#ibcon#flushed, iclass 17, count 2 2006.201.06:45:38.06#ibcon#about to write, iclass 17, count 2 2006.201.06:45:38.06#ibcon#wrote, iclass 17, count 2 2006.201.06:45:38.06#ibcon#about to read 3, iclass 17, count 2 2006.201.06:45:38.09#ibcon#read 3, iclass 17, count 2 2006.201.06:45:38.09#ibcon#about to read 4, iclass 17, count 2 2006.201.06:45:38.09#ibcon#read 4, iclass 17, count 2 2006.201.06:45:38.09#ibcon#about to read 5, iclass 17, count 2 2006.201.06:45:38.09#ibcon#read 5, iclass 17, count 2 2006.201.06:45:38.09#ibcon#about to read 6, iclass 17, count 2 2006.201.06:45:38.09#ibcon#read 6, iclass 17, count 2 2006.201.06:45:38.09#ibcon#end of sib2, iclass 17, count 2 2006.201.06:45:38.09#ibcon#*after write, iclass 17, count 2 2006.201.06:45:38.09#ibcon#*before return 0, iclass 17, count 2 2006.201.06:45:38.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:38.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:38.09#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.06:45:38.09#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:38.09#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:38.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:38.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:38.21#ibcon#enter wrdev, iclass 17, count 0 2006.201.06:45:38.21#ibcon#first serial, iclass 17, count 0 2006.201.06:45:38.21#ibcon#enter sib2, iclass 17, count 0 2006.201.06:45:38.21#ibcon#flushed, iclass 17, count 0 2006.201.06:45:38.21#ibcon#about to write, iclass 17, count 0 2006.201.06:45:38.21#ibcon#wrote, iclass 17, count 0 2006.201.06:45:38.21#ibcon#about to read 3, iclass 17, count 0 2006.201.06:45:38.23#ibcon#read 3, iclass 17, count 0 2006.201.06:45:38.23#ibcon#about to read 4, iclass 17, count 0 2006.201.06:45:38.23#ibcon#read 4, iclass 17, count 0 2006.201.06:45:38.23#ibcon#about to read 5, iclass 17, count 0 2006.201.06:45:38.23#ibcon#read 5, iclass 17, count 0 2006.201.06:45:38.23#ibcon#about to read 6, iclass 17, count 0 2006.201.06:45:38.23#ibcon#read 6, iclass 17, count 0 2006.201.06:45:38.23#ibcon#end of sib2, iclass 17, count 0 2006.201.06:45:38.23#ibcon#*mode == 0, iclass 17, count 0 2006.201.06:45:38.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.06:45:38.23#ibcon#[25=USB\r\n] 2006.201.06:45:38.23#ibcon#*before write, iclass 17, count 0 2006.201.06:45:38.23#ibcon#enter sib2, iclass 17, count 0 2006.201.06:45:38.23#ibcon#flushed, iclass 17, count 0 2006.201.06:45:38.23#ibcon#about to write, iclass 17, count 0 2006.201.06:45:38.23#ibcon#wrote, iclass 17, count 0 2006.201.06:45:38.23#ibcon#about to read 3, iclass 17, count 0 2006.201.06:45:38.26#ibcon#read 3, iclass 17, count 0 2006.201.06:45:38.26#ibcon#about to read 4, iclass 17, count 0 2006.201.06:45:38.26#ibcon#read 4, iclass 17, count 0 2006.201.06:45:38.26#ibcon#about to read 5, iclass 17, count 0 2006.201.06:45:38.26#ibcon#read 5, iclass 17, count 0 2006.201.06:45:38.26#ibcon#about to read 6, iclass 17, count 0 2006.201.06:45:38.26#ibcon#read 6, iclass 17, count 0 2006.201.06:45:38.26#ibcon#end of sib2, iclass 17, count 0 2006.201.06:45:38.26#ibcon#*after write, iclass 17, count 0 2006.201.06:45:38.26#ibcon#*before return 0, iclass 17, count 0 2006.201.06:45:38.26#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:38.26#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:38.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.06:45:38.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.06:45:38.26$vck44/valo=5,734.99 2006.201.06:45:38.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.06:45:38.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.06:45:38.26#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:38.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:38.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:38.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:38.26#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:45:38.26#ibcon#first serial, iclass 19, count 0 2006.201.06:45:38.26#ibcon#enter sib2, iclass 19, count 0 2006.201.06:45:38.26#ibcon#flushed, iclass 19, count 0 2006.201.06:45:38.26#ibcon#about to write, iclass 19, count 0 2006.201.06:45:38.26#ibcon#wrote, iclass 19, count 0 2006.201.06:45:38.26#ibcon#about to read 3, iclass 19, count 0 2006.201.06:45:38.28#ibcon#read 3, iclass 19, count 0 2006.201.06:45:38.28#ibcon#about to read 4, iclass 19, count 0 2006.201.06:45:38.28#ibcon#read 4, iclass 19, count 0 2006.201.06:45:38.28#ibcon#about to read 5, iclass 19, count 0 2006.201.06:45:38.28#ibcon#read 5, iclass 19, count 0 2006.201.06:45:38.28#ibcon#about to read 6, iclass 19, count 0 2006.201.06:45:38.28#ibcon#read 6, iclass 19, count 0 2006.201.06:45:38.28#ibcon#end of sib2, iclass 19, count 0 2006.201.06:45:38.28#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:45:38.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:45:38.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.06:45:38.28#ibcon#*before write, iclass 19, count 0 2006.201.06:45:38.28#ibcon#enter sib2, iclass 19, count 0 2006.201.06:45:38.28#ibcon#flushed, iclass 19, count 0 2006.201.06:45:38.28#ibcon#about to write, iclass 19, count 0 2006.201.06:45:38.28#ibcon#wrote, iclass 19, count 0 2006.201.06:45:38.28#ibcon#about to read 3, iclass 19, count 0 2006.201.06:45:38.32#ibcon#read 3, iclass 19, count 0 2006.201.06:45:38.32#ibcon#about to read 4, iclass 19, count 0 2006.201.06:45:38.32#ibcon#read 4, iclass 19, count 0 2006.201.06:45:38.32#ibcon#about to read 5, iclass 19, count 0 2006.201.06:45:38.32#ibcon#read 5, iclass 19, count 0 2006.201.06:45:38.32#ibcon#about to read 6, iclass 19, count 0 2006.201.06:45:38.32#ibcon#read 6, iclass 19, count 0 2006.201.06:45:38.32#ibcon#end of sib2, iclass 19, count 0 2006.201.06:45:38.32#ibcon#*after write, iclass 19, count 0 2006.201.06:45:38.32#ibcon#*before return 0, iclass 19, count 0 2006.201.06:45:38.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:38.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:38.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:45:38.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:45:38.32$vck44/va=5,4 2006.201.06:45:38.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.06:45:38.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.06:45:38.32#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:38.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:38.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:38.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:38.38#ibcon#enter wrdev, iclass 21, count 2 2006.201.06:45:38.38#ibcon#first serial, iclass 21, count 2 2006.201.06:45:38.38#ibcon#enter sib2, iclass 21, count 2 2006.201.06:45:38.38#ibcon#flushed, iclass 21, count 2 2006.201.06:45:38.38#ibcon#about to write, iclass 21, count 2 2006.201.06:45:38.38#ibcon#wrote, iclass 21, count 2 2006.201.06:45:38.38#ibcon#about to read 3, iclass 21, count 2 2006.201.06:45:38.40#ibcon#read 3, iclass 21, count 2 2006.201.06:45:38.40#ibcon#about to read 4, iclass 21, count 2 2006.201.06:45:38.40#ibcon#read 4, iclass 21, count 2 2006.201.06:45:38.40#ibcon#about to read 5, iclass 21, count 2 2006.201.06:45:38.40#ibcon#read 5, iclass 21, count 2 2006.201.06:45:38.40#ibcon#about to read 6, iclass 21, count 2 2006.201.06:45:38.40#ibcon#read 6, iclass 21, count 2 2006.201.06:45:38.40#ibcon#end of sib2, iclass 21, count 2 2006.201.06:45:38.40#ibcon#*mode == 0, iclass 21, count 2 2006.201.06:45:38.40#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.06:45:38.40#ibcon#[25=AT05-04\r\n] 2006.201.06:45:38.40#ibcon#*before write, iclass 21, count 2 2006.201.06:45:38.40#ibcon#enter sib2, iclass 21, count 2 2006.201.06:45:38.40#ibcon#flushed, iclass 21, count 2 2006.201.06:45:38.40#ibcon#about to write, iclass 21, count 2 2006.201.06:45:38.40#ibcon#wrote, iclass 21, count 2 2006.201.06:45:38.40#ibcon#about to read 3, iclass 21, count 2 2006.201.06:45:38.43#ibcon#read 3, iclass 21, count 2 2006.201.06:45:38.43#ibcon#about to read 4, iclass 21, count 2 2006.201.06:45:38.43#ibcon#read 4, iclass 21, count 2 2006.201.06:45:38.43#ibcon#about to read 5, iclass 21, count 2 2006.201.06:45:38.43#ibcon#read 5, iclass 21, count 2 2006.201.06:45:38.43#ibcon#about to read 6, iclass 21, count 2 2006.201.06:45:38.43#ibcon#read 6, iclass 21, count 2 2006.201.06:45:38.43#ibcon#end of sib2, iclass 21, count 2 2006.201.06:45:38.43#ibcon#*after write, iclass 21, count 2 2006.201.06:45:38.43#ibcon#*before return 0, iclass 21, count 2 2006.201.06:45:38.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:38.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:38.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.06:45:38.43#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:38.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:38.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:38.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:38.55#ibcon#enter wrdev, iclass 21, count 0 2006.201.06:45:38.55#ibcon#first serial, iclass 21, count 0 2006.201.06:45:38.55#ibcon#enter sib2, iclass 21, count 0 2006.201.06:45:38.55#ibcon#flushed, iclass 21, count 0 2006.201.06:45:38.55#ibcon#about to write, iclass 21, count 0 2006.201.06:45:38.55#ibcon#wrote, iclass 21, count 0 2006.201.06:45:38.55#ibcon#about to read 3, iclass 21, count 0 2006.201.06:45:38.57#ibcon#read 3, iclass 21, count 0 2006.201.06:45:38.57#ibcon#about to read 4, iclass 21, count 0 2006.201.06:45:38.57#ibcon#read 4, iclass 21, count 0 2006.201.06:45:38.57#ibcon#about to read 5, iclass 21, count 0 2006.201.06:45:38.57#ibcon#read 5, iclass 21, count 0 2006.201.06:45:38.57#ibcon#about to read 6, iclass 21, count 0 2006.201.06:45:38.57#ibcon#read 6, iclass 21, count 0 2006.201.06:45:38.57#ibcon#end of sib2, iclass 21, count 0 2006.201.06:45:38.57#ibcon#*mode == 0, iclass 21, count 0 2006.201.06:45:38.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.06:45:38.57#ibcon#[25=USB\r\n] 2006.201.06:45:38.57#ibcon#*before write, iclass 21, count 0 2006.201.06:45:38.57#ibcon#enter sib2, iclass 21, count 0 2006.201.06:45:38.57#ibcon#flushed, iclass 21, count 0 2006.201.06:45:38.57#ibcon#about to write, iclass 21, count 0 2006.201.06:45:38.57#ibcon#wrote, iclass 21, count 0 2006.201.06:45:38.57#ibcon#about to read 3, iclass 21, count 0 2006.201.06:45:38.60#ibcon#read 3, iclass 21, count 0 2006.201.06:45:38.60#ibcon#about to read 4, iclass 21, count 0 2006.201.06:45:38.60#ibcon#read 4, iclass 21, count 0 2006.201.06:45:38.60#ibcon#about to read 5, iclass 21, count 0 2006.201.06:45:38.60#ibcon#read 5, iclass 21, count 0 2006.201.06:45:38.60#ibcon#about to read 6, iclass 21, count 0 2006.201.06:45:38.60#ibcon#read 6, iclass 21, count 0 2006.201.06:45:38.60#ibcon#end of sib2, iclass 21, count 0 2006.201.06:45:38.60#ibcon#*after write, iclass 21, count 0 2006.201.06:45:38.60#ibcon#*before return 0, iclass 21, count 0 2006.201.06:45:38.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:38.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:38.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.06:45:38.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.06:45:38.60$vck44/valo=6,814.99 2006.201.06:45:38.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.06:45:38.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.06:45:38.60#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:38.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:38.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:38.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:38.60#ibcon#enter wrdev, iclass 23, count 0 2006.201.06:45:38.60#ibcon#first serial, iclass 23, count 0 2006.201.06:45:38.60#ibcon#enter sib2, iclass 23, count 0 2006.201.06:45:38.60#ibcon#flushed, iclass 23, count 0 2006.201.06:45:38.60#ibcon#about to write, iclass 23, count 0 2006.201.06:45:38.60#ibcon#wrote, iclass 23, count 0 2006.201.06:45:38.60#ibcon#about to read 3, iclass 23, count 0 2006.201.06:45:38.62#ibcon#read 3, iclass 23, count 0 2006.201.06:45:38.62#ibcon#about to read 4, iclass 23, count 0 2006.201.06:45:38.62#ibcon#read 4, iclass 23, count 0 2006.201.06:45:38.62#ibcon#about to read 5, iclass 23, count 0 2006.201.06:45:38.62#ibcon#read 5, iclass 23, count 0 2006.201.06:45:38.62#ibcon#about to read 6, iclass 23, count 0 2006.201.06:45:38.62#ibcon#read 6, iclass 23, count 0 2006.201.06:45:38.62#ibcon#end of sib2, iclass 23, count 0 2006.201.06:45:38.62#ibcon#*mode == 0, iclass 23, count 0 2006.201.06:45:38.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.06:45:38.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.06:45:38.62#ibcon#*before write, iclass 23, count 0 2006.201.06:45:38.62#ibcon#enter sib2, iclass 23, count 0 2006.201.06:45:38.62#ibcon#flushed, iclass 23, count 0 2006.201.06:45:38.62#ibcon#about to write, iclass 23, count 0 2006.201.06:45:38.62#ibcon#wrote, iclass 23, count 0 2006.201.06:45:38.62#ibcon#about to read 3, iclass 23, count 0 2006.201.06:45:38.67#ibcon#read 3, iclass 23, count 0 2006.201.06:45:38.67#ibcon#about to read 4, iclass 23, count 0 2006.201.06:45:38.67#ibcon#read 4, iclass 23, count 0 2006.201.06:45:38.67#ibcon#about to read 5, iclass 23, count 0 2006.201.06:45:38.67#ibcon#read 5, iclass 23, count 0 2006.201.06:45:38.67#ibcon#about to read 6, iclass 23, count 0 2006.201.06:45:38.67#ibcon#read 6, iclass 23, count 0 2006.201.06:45:38.67#ibcon#end of sib2, iclass 23, count 0 2006.201.06:45:38.67#ibcon#*after write, iclass 23, count 0 2006.201.06:45:38.67#ibcon#*before return 0, iclass 23, count 0 2006.201.06:45:38.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:38.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:38.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.06:45:38.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.06:45:38.67$vck44/va=6,5 2006.201.06:45:38.67#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.06:45:38.67#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.06:45:38.67#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:38.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:38.72#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:38.72#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:38.72#ibcon#enter wrdev, iclass 25, count 2 2006.201.06:45:38.72#ibcon#first serial, iclass 25, count 2 2006.201.06:45:38.72#ibcon#enter sib2, iclass 25, count 2 2006.201.06:45:38.72#ibcon#flushed, iclass 25, count 2 2006.201.06:45:38.72#ibcon#about to write, iclass 25, count 2 2006.201.06:45:38.72#ibcon#wrote, iclass 25, count 2 2006.201.06:45:38.72#ibcon#about to read 3, iclass 25, count 2 2006.201.06:45:38.74#ibcon#read 3, iclass 25, count 2 2006.201.06:45:38.74#ibcon#about to read 4, iclass 25, count 2 2006.201.06:45:38.74#ibcon#read 4, iclass 25, count 2 2006.201.06:45:38.74#ibcon#about to read 5, iclass 25, count 2 2006.201.06:45:38.74#ibcon#read 5, iclass 25, count 2 2006.201.06:45:38.74#ibcon#about to read 6, iclass 25, count 2 2006.201.06:45:38.74#ibcon#read 6, iclass 25, count 2 2006.201.06:45:38.74#ibcon#end of sib2, iclass 25, count 2 2006.201.06:45:38.74#ibcon#*mode == 0, iclass 25, count 2 2006.201.06:45:38.74#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.06:45:38.74#ibcon#[25=AT06-05\r\n] 2006.201.06:45:38.74#ibcon#*before write, iclass 25, count 2 2006.201.06:45:38.74#ibcon#enter sib2, iclass 25, count 2 2006.201.06:45:38.74#ibcon#flushed, iclass 25, count 2 2006.201.06:45:38.74#ibcon#about to write, iclass 25, count 2 2006.201.06:45:38.74#ibcon#wrote, iclass 25, count 2 2006.201.06:45:38.74#ibcon#about to read 3, iclass 25, count 2 2006.201.06:45:38.77#ibcon#read 3, iclass 25, count 2 2006.201.06:45:38.77#ibcon#about to read 4, iclass 25, count 2 2006.201.06:45:38.77#ibcon#read 4, iclass 25, count 2 2006.201.06:45:38.77#ibcon#about to read 5, iclass 25, count 2 2006.201.06:45:38.77#ibcon#read 5, iclass 25, count 2 2006.201.06:45:38.77#ibcon#about to read 6, iclass 25, count 2 2006.201.06:45:38.77#ibcon#read 6, iclass 25, count 2 2006.201.06:45:38.77#ibcon#end of sib2, iclass 25, count 2 2006.201.06:45:38.77#ibcon#*after write, iclass 25, count 2 2006.201.06:45:38.77#ibcon#*before return 0, iclass 25, count 2 2006.201.06:45:38.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:38.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:38.77#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.06:45:38.77#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:38.77#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:38.89#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:38.89#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:38.89#ibcon#enter wrdev, iclass 25, count 0 2006.201.06:45:38.89#ibcon#first serial, iclass 25, count 0 2006.201.06:45:38.89#ibcon#enter sib2, iclass 25, count 0 2006.201.06:45:38.89#ibcon#flushed, iclass 25, count 0 2006.201.06:45:38.89#ibcon#about to write, iclass 25, count 0 2006.201.06:45:38.89#ibcon#wrote, iclass 25, count 0 2006.201.06:45:38.89#ibcon#about to read 3, iclass 25, count 0 2006.201.06:45:38.91#ibcon#read 3, iclass 25, count 0 2006.201.06:45:38.91#ibcon#about to read 4, iclass 25, count 0 2006.201.06:45:38.91#ibcon#read 4, iclass 25, count 0 2006.201.06:45:38.91#ibcon#about to read 5, iclass 25, count 0 2006.201.06:45:38.91#ibcon#read 5, iclass 25, count 0 2006.201.06:45:38.91#ibcon#about to read 6, iclass 25, count 0 2006.201.06:45:38.91#ibcon#read 6, iclass 25, count 0 2006.201.06:45:38.91#ibcon#end of sib2, iclass 25, count 0 2006.201.06:45:38.91#ibcon#*mode == 0, iclass 25, count 0 2006.201.06:45:38.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.06:45:38.91#ibcon#[25=USB\r\n] 2006.201.06:45:38.91#ibcon#*before write, iclass 25, count 0 2006.201.06:45:38.91#ibcon#enter sib2, iclass 25, count 0 2006.201.06:45:38.91#ibcon#flushed, iclass 25, count 0 2006.201.06:45:38.91#ibcon#about to write, iclass 25, count 0 2006.201.06:45:38.91#ibcon#wrote, iclass 25, count 0 2006.201.06:45:38.91#ibcon#about to read 3, iclass 25, count 0 2006.201.06:45:38.94#ibcon#read 3, iclass 25, count 0 2006.201.06:45:38.94#ibcon#about to read 4, iclass 25, count 0 2006.201.06:45:38.94#ibcon#read 4, iclass 25, count 0 2006.201.06:45:38.94#ibcon#about to read 5, iclass 25, count 0 2006.201.06:45:38.94#ibcon#read 5, iclass 25, count 0 2006.201.06:45:38.94#ibcon#about to read 6, iclass 25, count 0 2006.201.06:45:38.94#ibcon#read 6, iclass 25, count 0 2006.201.06:45:38.94#ibcon#end of sib2, iclass 25, count 0 2006.201.06:45:38.94#ibcon#*after write, iclass 25, count 0 2006.201.06:45:38.94#ibcon#*before return 0, iclass 25, count 0 2006.201.06:45:38.94#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:38.94#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:38.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.06:45:38.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.06:45:38.94$vck44/valo=7,864.99 2006.201.06:45:38.94#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.06:45:38.94#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.06:45:38.94#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:38.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:38.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:38.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:38.94#ibcon#enter wrdev, iclass 27, count 0 2006.201.06:45:38.94#ibcon#first serial, iclass 27, count 0 2006.201.06:45:38.94#ibcon#enter sib2, iclass 27, count 0 2006.201.06:45:38.94#ibcon#flushed, iclass 27, count 0 2006.201.06:45:38.94#ibcon#about to write, iclass 27, count 0 2006.201.06:45:38.94#ibcon#wrote, iclass 27, count 0 2006.201.06:45:38.94#ibcon#about to read 3, iclass 27, count 0 2006.201.06:45:38.96#ibcon#read 3, iclass 27, count 0 2006.201.06:45:38.96#ibcon#about to read 4, iclass 27, count 0 2006.201.06:45:38.96#ibcon#read 4, iclass 27, count 0 2006.201.06:45:38.96#ibcon#about to read 5, iclass 27, count 0 2006.201.06:45:38.96#ibcon#read 5, iclass 27, count 0 2006.201.06:45:38.96#ibcon#about to read 6, iclass 27, count 0 2006.201.06:45:38.96#ibcon#read 6, iclass 27, count 0 2006.201.06:45:38.96#ibcon#end of sib2, iclass 27, count 0 2006.201.06:45:38.96#ibcon#*mode == 0, iclass 27, count 0 2006.201.06:45:38.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.06:45:38.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.06:45:38.96#ibcon#*before write, iclass 27, count 0 2006.201.06:45:38.96#ibcon#enter sib2, iclass 27, count 0 2006.201.06:45:38.96#ibcon#flushed, iclass 27, count 0 2006.201.06:45:38.96#ibcon#about to write, iclass 27, count 0 2006.201.06:45:38.96#ibcon#wrote, iclass 27, count 0 2006.201.06:45:38.96#ibcon#about to read 3, iclass 27, count 0 2006.201.06:45:39.00#ibcon#read 3, iclass 27, count 0 2006.201.06:45:39.00#ibcon#about to read 4, iclass 27, count 0 2006.201.06:45:39.00#ibcon#read 4, iclass 27, count 0 2006.201.06:45:39.00#ibcon#about to read 5, iclass 27, count 0 2006.201.06:45:39.00#ibcon#read 5, iclass 27, count 0 2006.201.06:45:39.00#ibcon#about to read 6, iclass 27, count 0 2006.201.06:45:39.00#ibcon#read 6, iclass 27, count 0 2006.201.06:45:39.00#ibcon#end of sib2, iclass 27, count 0 2006.201.06:45:39.00#ibcon#*after write, iclass 27, count 0 2006.201.06:45:39.00#ibcon#*before return 0, iclass 27, count 0 2006.201.06:45:39.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:39.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:39.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.06:45:39.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.06:45:39.00$vck44/va=7,5 2006.201.06:45:39.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.06:45:39.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.06:45:39.00#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:39.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:39.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:39.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:39.06#ibcon#enter wrdev, iclass 29, count 2 2006.201.06:45:39.06#ibcon#first serial, iclass 29, count 2 2006.201.06:45:39.06#ibcon#enter sib2, iclass 29, count 2 2006.201.06:45:39.06#ibcon#flushed, iclass 29, count 2 2006.201.06:45:39.06#ibcon#about to write, iclass 29, count 2 2006.201.06:45:39.06#ibcon#wrote, iclass 29, count 2 2006.201.06:45:39.06#ibcon#about to read 3, iclass 29, count 2 2006.201.06:45:39.08#ibcon#read 3, iclass 29, count 2 2006.201.06:45:39.08#ibcon#about to read 4, iclass 29, count 2 2006.201.06:45:39.08#ibcon#read 4, iclass 29, count 2 2006.201.06:45:39.08#ibcon#about to read 5, iclass 29, count 2 2006.201.06:45:39.08#ibcon#read 5, iclass 29, count 2 2006.201.06:45:39.08#ibcon#about to read 6, iclass 29, count 2 2006.201.06:45:39.08#ibcon#read 6, iclass 29, count 2 2006.201.06:45:39.08#ibcon#end of sib2, iclass 29, count 2 2006.201.06:45:39.08#ibcon#*mode == 0, iclass 29, count 2 2006.201.06:45:39.08#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.06:45:39.08#ibcon#[25=AT07-05\r\n] 2006.201.06:45:39.08#ibcon#*before write, iclass 29, count 2 2006.201.06:45:39.08#ibcon#enter sib2, iclass 29, count 2 2006.201.06:45:39.08#ibcon#flushed, iclass 29, count 2 2006.201.06:45:39.08#ibcon#about to write, iclass 29, count 2 2006.201.06:45:39.08#ibcon#wrote, iclass 29, count 2 2006.201.06:45:39.08#ibcon#about to read 3, iclass 29, count 2 2006.201.06:45:39.11#ibcon#read 3, iclass 29, count 2 2006.201.06:45:39.11#ibcon#about to read 4, iclass 29, count 2 2006.201.06:45:39.11#ibcon#read 4, iclass 29, count 2 2006.201.06:45:39.11#ibcon#about to read 5, iclass 29, count 2 2006.201.06:45:39.11#ibcon#read 5, iclass 29, count 2 2006.201.06:45:39.11#ibcon#about to read 6, iclass 29, count 2 2006.201.06:45:39.11#ibcon#read 6, iclass 29, count 2 2006.201.06:45:39.11#ibcon#end of sib2, iclass 29, count 2 2006.201.06:45:39.11#ibcon#*after write, iclass 29, count 2 2006.201.06:45:39.11#ibcon#*before return 0, iclass 29, count 2 2006.201.06:45:39.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:39.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:39.11#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.06:45:39.11#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:39.11#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:39.23#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:39.23#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:39.23#ibcon#enter wrdev, iclass 29, count 0 2006.201.06:45:39.23#ibcon#first serial, iclass 29, count 0 2006.201.06:45:39.23#ibcon#enter sib2, iclass 29, count 0 2006.201.06:45:39.23#ibcon#flushed, iclass 29, count 0 2006.201.06:45:39.23#ibcon#about to write, iclass 29, count 0 2006.201.06:45:39.23#ibcon#wrote, iclass 29, count 0 2006.201.06:45:39.23#ibcon#about to read 3, iclass 29, count 0 2006.201.06:45:39.25#ibcon#read 3, iclass 29, count 0 2006.201.06:45:39.25#ibcon#about to read 4, iclass 29, count 0 2006.201.06:45:39.25#ibcon#read 4, iclass 29, count 0 2006.201.06:45:39.25#ibcon#about to read 5, iclass 29, count 0 2006.201.06:45:39.25#ibcon#read 5, iclass 29, count 0 2006.201.06:45:39.25#ibcon#about to read 6, iclass 29, count 0 2006.201.06:45:39.25#ibcon#read 6, iclass 29, count 0 2006.201.06:45:39.25#ibcon#end of sib2, iclass 29, count 0 2006.201.06:45:39.25#ibcon#*mode == 0, iclass 29, count 0 2006.201.06:45:39.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.06:45:39.25#ibcon#[25=USB\r\n] 2006.201.06:45:39.25#ibcon#*before write, iclass 29, count 0 2006.201.06:45:39.25#ibcon#enter sib2, iclass 29, count 0 2006.201.06:45:39.25#ibcon#flushed, iclass 29, count 0 2006.201.06:45:39.25#ibcon#about to write, iclass 29, count 0 2006.201.06:45:39.25#ibcon#wrote, iclass 29, count 0 2006.201.06:45:39.25#ibcon#about to read 3, iclass 29, count 0 2006.201.06:45:39.28#ibcon#read 3, iclass 29, count 0 2006.201.06:45:39.28#ibcon#about to read 4, iclass 29, count 0 2006.201.06:45:39.28#ibcon#read 4, iclass 29, count 0 2006.201.06:45:39.28#ibcon#about to read 5, iclass 29, count 0 2006.201.06:45:39.28#ibcon#read 5, iclass 29, count 0 2006.201.06:45:39.28#ibcon#about to read 6, iclass 29, count 0 2006.201.06:45:39.28#ibcon#read 6, iclass 29, count 0 2006.201.06:45:39.28#ibcon#end of sib2, iclass 29, count 0 2006.201.06:45:39.28#ibcon#*after write, iclass 29, count 0 2006.201.06:45:39.28#ibcon#*before return 0, iclass 29, count 0 2006.201.06:45:39.28#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:39.28#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:39.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.06:45:39.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.06:45:39.28$vck44/valo=8,884.99 2006.201.06:45:39.28#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.06:45:39.28#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.06:45:39.28#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:39.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:39.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:39.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:39.28#ibcon#enter wrdev, iclass 31, count 0 2006.201.06:45:39.28#ibcon#first serial, iclass 31, count 0 2006.201.06:45:39.28#ibcon#enter sib2, iclass 31, count 0 2006.201.06:45:39.28#ibcon#flushed, iclass 31, count 0 2006.201.06:45:39.28#ibcon#about to write, iclass 31, count 0 2006.201.06:45:39.28#ibcon#wrote, iclass 31, count 0 2006.201.06:45:39.28#ibcon#about to read 3, iclass 31, count 0 2006.201.06:45:39.30#ibcon#read 3, iclass 31, count 0 2006.201.06:45:39.30#ibcon#about to read 4, iclass 31, count 0 2006.201.06:45:39.30#ibcon#read 4, iclass 31, count 0 2006.201.06:45:39.30#ibcon#about to read 5, iclass 31, count 0 2006.201.06:45:39.30#ibcon#read 5, iclass 31, count 0 2006.201.06:45:39.30#ibcon#about to read 6, iclass 31, count 0 2006.201.06:45:39.30#ibcon#read 6, iclass 31, count 0 2006.201.06:45:39.30#ibcon#end of sib2, iclass 31, count 0 2006.201.06:45:39.30#ibcon#*mode == 0, iclass 31, count 0 2006.201.06:45:39.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.06:45:39.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.06:45:39.30#ibcon#*before write, iclass 31, count 0 2006.201.06:45:39.30#ibcon#enter sib2, iclass 31, count 0 2006.201.06:45:39.30#ibcon#flushed, iclass 31, count 0 2006.201.06:45:39.30#ibcon#about to write, iclass 31, count 0 2006.201.06:45:39.30#ibcon#wrote, iclass 31, count 0 2006.201.06:45:39.30#ibcon#about to read 3, iclass 31, count 0 2006.201.06:45:39.34#ibcon#read 3, iclass 31, count 0 2006.201.06:45:39.34#ibcon#about to read 4, iclass 31, count 0 2006.201.06:45:39.34#ibcon#read 4, iclass 31, count 0 2006.201.06:45:39.34#ibcon#about to read 5, iclass 31, count 0 2006.201.06:45:39.34#ibcon#read 5, iclass 31, count 0 2006.201.06:45:39.34#ibcon#about to read 6, iclass 31, count 0 2006.201.06:45:39.34#ibcon#read 6, iclass 31, count 0 2006.201.06:45:39.34#ibcon#end of sib2, iclass 31, count 0 2006.201.06:45:39.34#ibcon#*after write, iclass 31, count 0 2006.201.06:45:39.34#ibcon#*before return 0, iclass 31, count 0 2006.201.06:45:39.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:39.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:39.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.06:45:39.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.06:45:39.34$vck44/va=8,4 2006.201.06:45:39.34#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.06:45:39.34#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.06:45:39.34#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:39.34#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:45:39.40#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:45:39.40#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:45:39.40#ibcon#enter wrdev, iclass 33, count 2 2006.201.06:45:39.40#ibcon#first serial, iclass 33, count 2 2006.201.06:45:39.40#ibcon#enter sib2, iclass 33, count 2 2006.201.06:45:39.40#ibcon#flushed, iclass 33, count 2 2006.201.06:45:39.40#ibcon#about to write, iclass 33, count 2 2006.201.06:45:39.40#ibcon#wrote, iclass 33, count 2 2006.201.06:45:39.40#ibcon#about to read 3, iclass 33, count 2 2006.201.06:45:39.42#ibcon#read 3, iclass 33, count 2 2006.201.06:45:39.42#ibcon#about to read 4, iclass 33, count 2 2006.201.06:45:39.42#ibcon#read 4, iclass 33, count 2 2006.201.06:45:39.42#ibcon#about to read 5, iclass 33, count 2 2006.201.06:45:39.42#ibcon#read 5, iclass 33, count 2 2006.201.06:45:39.42#ibcon#about to read 6, iclass 33, count 2 2006.201.06:45:39.42#ibcon#read 6, iclass 33, count 2 2006.201.06:45:39.42#ibcon#end of sib2, iclass 33, count 2 2006.201.06:45:39.42#ibcon#*mode == 0, iclass 33, count 2 2006.201.06:45:39.42#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.06:45:39.42#ibcon#[25=AT08-04\r\n] 2006.201.06:45:39.42#ibcon#*before write, iclass 33, count 2 2006.201.06:45:39.42#ibcon#enter sib2, iclass 33, count 2 2006.201.06:45:39.42#ibcon#flushed, iclass 33, count 2 2006.201.06:45:39.42#ibcon#about to write, iclass 33, count 2 2006.201.06:45:39.42#ibcon#wrote, iclass 33, count 2 2006.201.06:45:39.42#ibcon#about to read 3, iclass 33, count 2 2006.201.06:45:39.45#ibcon#read 3, iclass 33, count 2 2006.201.06:45:39.45#ibcon#about to read 4, iclass 33, count 2 2006.201.06:45:39.45#ibcon#read 4, iclass 33, count 2 2006.201.06:45:39.45#ibcon#about to read 5, iclass 33, count 2 2006.201.06:45:39.45#ibcon#read 5, iclass 33, count 2 2006.201.06:45:39.45#ibcon#about to read 6, iclass 33, count 2 2006.201.06:45:39.45#ibcon#read 6, iclass 33, count 2 2006.201.06:45:39.45#ibcon#end of sib2, iclass 33, count 2 2006.201.06:45:39.45#ibcon#*after write, iclass 33, count 2 2006.201.06:45:39.45#ibcon#*before return 0, iclass 33, count 2 2006.201.06:45:39.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:45:39.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.06:45:39.45#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.06:45:39.45#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:39.45#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:45:39.57#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:45:39.57#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:45:39.57#ibcon#enter wrdev, iclass 33, count 0 2006.201.06:45:39.57#ibcon#first serial, iclass 33, count 0 2006.201.06:45:39.57#ibcon#enter sib2, iclass 33, count 0 2006.201.06:45:39.57#ibcon#flushed, iclass 33, count 0 2006.201.06:45:39.57#ibcon#about to write, iclass 33, count 0 2006.201.06:45:39.57#ibcon#wrote, iclass 33, count 0 2006.201.06:45:39.57#ibcon#about to read 3, iclass 33, count 0 2006.201.06:45:39.59#ibcon#read 3, iclass 33, count 0 2006.201.06:45:39.59#ibcon#about to read 4, iclass 33, count 0 2006.201.06:45:39.59#ibcon#read 4, iclass 33, count 0 2006.201.06:45:39.59#ibcon#about to read 5, iclass 33, count 0 2006.201.06:45:39.59#ibcon#read 5, iclass 33, count 0 2006.201.06:45:39.59#ibcon#about to read 6, iclass 33, count 0 2006.201.06:45:39.59#ibcon#read 6, iclass 33, count 0 2006.201.06:45:39.59#ibcon#end of sib2, iclass 33, count 0 2006.201.06:45:39.59#ibcon#*mode == 0, iclass 33, count 0 2006.201.06:45:39.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.06:45:39.59#ibcon#[25=USB\r\n] 2006.201.06:45:39.59#ibcon#*before write, iclass 33, count 0 2006.201.06:45:39.59#ibcon#enter sib2, iclass 33, count 0 2006.201.06:45:39.59#ibcon#flushed, iclass 33, count 0 2006.201.06:45:39.59#ibcon#about to write, iclass 33, count 0 2006.201.06:45:39.59#ibcon#wrote, iclass 33, count 0 2006.201.06:45:39.59#ibcon#about to read 3, iclass 33, count 0 2006.201.06:45:39.62#ibcon#read 3, iclass 33, count 0 2006.201.06:45:39.62#ibcon#about to read 4, iclass 33, count 0 2006.201.06:45:39.62#ibcon#read 4, iclass 33, count 0 2006.201.06:45:39.62#ibcon#about to read 5, iclass 33, count 0 2006.201.06:45:39.62#ibcon#read 5, iclass 33, count 0 2006.201.06:45:39.62#ibcon#about to read 6, iclass 33, count 0 2006.201.06:45:39.62#ibcon#read 6, iclass 33, count 0 2006.201.06:45:39.62#ibcon#end of sib2, iclass 33, count 0 2006.201.06:45:39.62#ibcon#*after write, iclass 33, count 0 2006.201.06:45:39.62#ibcon#*before return 0, iclass 33, count 0 2006.201.06:45:39.62#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:45:39.62#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.06:45:39.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.06:45:39.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.06:45:39.62$vck44/vblo=1,629.99 2006.201.06:45:39.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.06:45:39.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.06:45:39.62#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:39.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:45:39.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:45:39.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:45:39.62#ibcon#enter wrdev, iclass 35, count 0 2006.201.06:45:39.62#ibcon#first serial, iclass 35, count 0 2006.201.06:45:39.62#ibcon#enter sib2, iclass 35, count 0 2006.201.06:45:39.62#ibcon#flushed, iclass 35, count 0 2006.201.06:45:39.62#ibcon#about to write, iclass 35, count 0 2006.201.06:45:39.62#ibcon#wrote, iclass 35, count 0 2006.201.06:45:39.62#ibcon#about to read 3, iclass 35, count 0 2006.201.06:45:39.64#ibcon#read 3, iclass 35, count 0 2006.201.06:45:39.64#ibcon#about to read 4, iclass 35, count 0 2006.201.06:45:39.64#ibcon#read 4, iclass 35, count 0 2006.201.06:45:39.64#ibcon#about to read 5, iclass 35, count 0 2006.201.06:45:39.64#ibcon#read 5, iclass 35, count 0 2006.201.06:45:39.64#ibcon#about to read 6, iclass 35, count 0 2006.201.06:45:39.64#ibcon#read 6, iclass 35, count 0 2006.201.06:45:39.64#ibcon#end of sib2, iclass 35, count 0 2006.201.06:45:39.64#ibcon#*mode == 0, iclass 35, count 0 2006.201.06:45:39.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.06:45:39.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.06:45:39.64#ibcon#*before write, iclass 35, count 0 2006.201.06:45:39.64#ibcon#enter sib2, iclass 35, count 0 2006.201.06:45:39.64#ibcon#flushed, iclass 35, count 0 2006.201.06:45:39.64#ibcon#about to write, iclass 35, count 0 2006.201.06:45:39.64#ibcon#wrote, iclass 35, count 0 2006.201.06:45:39.64#ibcon#about to read 3, iclass 35, count 0 2006.201.06:45:39.69#ibcon#read 3, iclass 35, count 0 2006.201.06:45:39.69#ibcon#about to read 4, iclass 35, count 0 2006.201.06:45:39.69#ibcon#read 4, iclass 35, count 0 2006.201.06:45:39.69#ibcon#about to read 5, iclass 35, count 0 2006.201.06:45:39.69#ibcon#read 5, iclass 35, count 0 2006.201.06:45:39.69#ibcon#about to read 6, iclass 35, count 0 2006.201.06:45:39.69#ibcon#read 6, iclass 35, count 0 2006.201.06:45:39.69#ibcon#end of sib2, iclass 35, count 0 2006.201.06:45:39.69#ibcon#*after write, iclass 35, count 0 2006.201.06:45:39.69#ibcon#*before return 0, iclass 35, count 0 2006.201.06:45:39.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:45:39.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.06:45:39.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.06:45:39.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.06:45:39.69$vck44/vb=1,4 2006.201.06:45:39.69#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.06:45:39.69#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.06:45:39.69#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:39.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:45:39.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:45:39.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:45:39.69#ibcon#enter wrdev, iclass 37, count 2 2006.201.06:45:39.69#ibcon#first serial, iclass 37, count 2 2006.201.06:45:39.69#ibcon#enter sib2, iclass 37, count 2 2006.201.06:45:39.69#ibcon#flushed, iclass 37, count 2 2006.201.06:45:39.69#ibcon#about to write, iclass 37, count 2 2006.201.06:45:39.69#ibcon#wrote, iclass 37, count 2 2006.201.06:45:39.69#ibcon#about to read 3, iclass 37, count 2 2006.201.06:45:39.71#ibcon#read 3, iclass 37, count 2 2006.201.06:45:39.71#ibcon#about to read 4, iclass 37, count 2 2006.201.06:45:39.71#ibcon#read 4, iclass 37, count 2 2006.201.06:45:39.71#ibcon#about to read 5, iclass 37, count 2 2006.201.06:45:39.71#ibcon#read 5, iclass 37, count 2 2006.201.06:45:39.71#ibcon#about to read 6, iclass 37, count 2 2006.201.06:45:39.71#ibcon#read 6, iclass 37, count 2 2006.201.06:45:39.71#ibcon#end of sib2, iclass 37, count 2 2006.201.06:45:39.71#ibcon#*mode == 0, iclass 37, count 2 2006.201.06:45:39.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.06:45:39.71#ibcon#[27=AT01-04\r\n] 2006.201.06:45:39.71#ibcon#*before write, iclass 37, count 2 2006.201.06:45:39.71#ibcon#enter sib2, iclass 37, count 2 2006.201.06:45:39.71#ibcon#flushed, iclass 37, count 2 2006.201.06:45:39.71#ibcon#about to write, iclass 37, count 2 2006.201.06:45:39.71#ibcon#wrote, iclass 37, count 2 2006.201.06:45:39.71#ibcon#about to read 3, iclass 37, count 2 2006.201.06:45:39.74#ibcon#read 3, iclass 37, count 2 2006.201.06:45:39.74#ibcon#about to read 4, iclass 37, count 2 2006.201.06:45:39.74#ibcon#read 4, iclass 37, count 2 2006.201.06:45:39.74#ibcon#about to read 5, iclass 37, count 2 2006.201.06:45:39.74#ibcon#read 5, iclass 37, count 2 2006.201.06:45:39.74#ibcon#about to read 6, iclass 37, count 2 2006.201.06:45:39.74#ibcon#read 6, iclass 37, count 2 2006.201.06:45:39.74#ibcon#end of sib2, iclass 37, count 2 2006.201.06:45:39.74#ibcon#*after write, iclass 37, count 2 2006.201.06:45:39.74#ibcon#*before return 0, iclass 37, count 2 2006.201.06:45:39.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:45:39.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.06:45:39.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.06:45:39.74#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:39.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:45:39.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:45:39.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:45:39.86#ibcon#enter wrdev, iclass 37, count 0 2006.201.06:45:39.86#ibcon#first serial, iclass 37, count 0 2006.201.06:45:39.86#ibcon#enter sib2, iclass 37, count 0 2006.201.06:45:39.86#ibcon#flushed, iclass 37, count 0 2006.201.06:45:39.86#ibcon#about to write, iclass 37, count 0 2006.201.06:45:39.86#ibcon#wrote, iclass 37, count 0 2006.201.06:45:39.86#ibcon#about to read 3, iclass 37, count 0 2006.201.06:45:39.88#ibcon#read 3, iclass 37, count 0 2006.201.06:45:39.88#ibcon#about to read 4, iclass 37, count 0 2006.201.06:45:39.88#ibcon#read 4, iclass 37, count 0 2006.201.06:45:39.88#ibcon#about to read 5, iclass 37, count 0 2006.201.06:45:39.88#ibcon#read 5, iclass 37, count 0 2006.201.06:45:39.88#ibcon#about to read 6, iclass 37, count 0 2006.201.06:45:39.88#ibcon#read 6, iclass 37, count 0 2006.201.06:45:39.88#ibcon#end of sib2, iclass 37, count 0 2006.201.06:45:39.88#ibcon#*mode == 0, iclass 37, count 0 2006.201.06:45:39.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.06:45:39.88#ibcon#[27=USB\r\n] 2006.201.06:45:39.88#ibcon#*before write, iclass 37, count 0 2006.201.06:45:39.88#ibcon#enter sib2, iclass 37, count 0 2006.201.06:45:39.88#ibcon#flushed, iclass 37, count 0 2006.201.06:45:39.88#ibcon#about to write, iclass 37, count 0 2006.201.06:45:39.88#ibcon#wrote, iclass 37, count 0 2006.201.06:45:39.88#ibcon#about to read 3, iclass 37, count 0 2006.201.06:45:39.91#ibcon#read 3, iclass 37, count 0 2006.201.06:45:39.91#ibcon#about to read 4, iclass 37, count 0 2006.201.06:45:39.91#ibcon#read 4, iclass 37, count 0 2006.201.06:45:39.91#ibcon#about to read 5, iclass 37, count 0 2006.201.06:45:39.91#ibcon#read 5, iclass 37, count 0 2006.201.06:45:39.91#ibcon#about to read 6, iclass 37, count 0 2006.201.06:45:39.91#ibcon#read 6, iclass 37, count 0 2006.201.06:45:39.91#ibcon#end of sib2, iclass 37, count 0 2006.201.06:45:39.91#ibcon#*after write, iclass 37, count 0 2006.201.06:45:39.91#ibcon#*before return 0, iclass 37, count 0 2006.201.06:45:39.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:45:39.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.06:45:39.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.06:45:39.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.06:45:39.91$vck44/vblo=2,634.99 2006.201.06:45:39.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.06:45:39.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.06:45:39.91#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:39.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:39.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:39.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:39.91#ibcon#enter wrdev, iclass 39, count 0 2006.201.06:45:39.91#ibcon#first serial, iclass 39, count 0 2006.201.06:45:39.91#ibcon#enter sib2, iclass 39, count 0 2006.201.06:45:39.91#ibcon#flushed, iclass 39, count 0 2006.201.06:45:39.91#ibcon#about to write, iclass 39, count 0 2006.201.06:45:39.91#ibcon#wrote, iclass 39, count 0 2006.201.06:45:39.91#ibcon#about to read 3, iclass 39, count 0 2006.201.06:45:39.93#ibcon#read 3, iclass 39, count 0 2006.201.06:45:39.93#ibcon#about to read 4, iclass 39, count 0 2006.201.06:45:39.93#ibcon#read 4, iclass 39, count 0 2006.201.06:45:39.93#ibcon#about to read 5, iclass 39, count 0 2006.201.06:45:39.93#ibcon#read 5, iclass 39, count 0 2006.201.06:45:39.93#ibcon#about to read 6, iclass 39, count 0 2006.201.06:45:39.93#ibcon#read 6, iclass 39, count 0 2006.201.06:45:39.93#ibcon#end of sib2, iclass 39, count 0 2006.201.06:45:39.93#ibcon#*mode == 0, iclass 39, count 0 2006.201.06:45:39.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.06:45:39.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.06:45:39.93#ibcon#*before write, iclass 39, count 0 2006.201.06:45:39.93#ibcon#enter sib2, iclass 39, count 0 2006.201.06:45:39.93#ibcon#flushed, iclass 39, count 0 2006.201.06:45:39.93#ibcon#about to write, iclass 39, count 0 2006.201.06:45:39.93#ibcon#wrote, iclass 39, count 0 2006.201.06:45:39.93#ibcon#about to read 3, iclass 39, count 0 2006.201.06:45:39.97#ibcon#read 3, iclass 39, count 0 2006.201.06:45:39.97#ibcon#about to read 4, iclass 39, count 0 2006.201.06:45:39.97#ibcon#read 4, iclass 39, count 0 2006.201.06:45:39.97#ibcon#about to read 5, iclass 39, count 0 2006.201.06:45:39.97#ibcon#read 5, iclass 39, count 0 2006.201.06:45:39.97#ibcon#about to read 6, iclass 39, count 0 2006.201.06:45:39.97#ibcon#read 6, iclass 39, count 0 2006.201.06:45:39.97#ibcon#end of sib2, iclass 39, count 0 2006.201.06:45:39.97#ibcon#*after write, iclass 39, count 0 2006.201.06:45:39.97#ibcon#*before return 0, iclass 39, count 0 2006.201.06:45:39.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:39.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.06:45:39.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.06:45:39.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.06:45:39.97$vck44/vb=2,5 2006.201.06:45:39.97#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.06:45:39.97#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.06:45:39.97#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:39.97#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:40.03#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:40.03#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:40.03#ibcon#enter wrdev, iclass 2, count 2 2006.201.06:45:40.03#ibcon#first serial, iclass 2, count 2 2006.201.06:45:40.03#ibcon#enter sib2, iclass 2, count 2 2006.201.06:45:40.03#ibcon#flushed, iclass 2, count 2 2006.201.06:45:40.03#ibcon#about to write, iclass 2, count 2 2006.201.06:45:40.03#ibcon#wrote, iclass 2, count 2 2006.201.06:45:40.03#ibcon#about to read 3, iclass 2, count 2 2006.201.06:45:40.05#ibcon#read 3, iclass 2, count 2 2006.201.06:45:40.05#ibcon#about to read 4, iclass 2, count 2 2006.201.06:45:40.05#ibcon#read 4, iclass 2, count 2 2006.201.06:45:40.05#ibcon#about to read 5, iclass 2, count 2 2006.201.06:45:40.05#ibcon#read 5, iclass 2, count 2 2006.201.06:45:40.05#ibcon#about to read 6, iclass 2, count 2 2006.201.06:45:40.05#ibcon#read 6, iclass 2, count 2 2006.201.06:45:40.05#ibcon#end of sib2, iclass 2, count 2 2006.201.06:45:40.05#ibcon#*mode == 0, iclass 2, count 2 2006.201.06:45:40.05#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.06:45:40.05#ibcon#[27=AT02-05\r\n] 2006.201.06:45:40.05#ibcon#*before write, iclass 2, count 2 2006.201.06:45:40.05#ibcon#enter sib2, iclass 2, count 2 2006.201.06:45:40.05#ibcon#flushed, iclass 2, count 2 2006.201.06:45:40.05#ibcon#about to write, iclass 2, count 2 2006.201.06:45:40.05#ibcon#wrote, iclass 2, count 2 2006.201.06:45:40.05#ibcon#about to read 3, iclass 2, count 2 2006.201.06:45:40.08#ibcon#read 3, iclass 2, count 2 2006.201.06:45:40.08#ibcon#about to read 4, iclass 2, count 2 2006.201.06:45:40.08#ibcon#read 4, iclass 2, count 2 2006.201.06:45:40.08#ibcon#about to read 5, iclass 2, count 2 2006.201.06:45:40.08#ibcon#read 5, iclass 2, count 2 2006.201.06:45:40.08#ibcon#about to read 6, iclass 2, count 2 2006.201.06:45:40.08#ibcon#read 6, iclass 2, count 2 2006.201.06:45:40.08#ibcon#end of sib2, iclass 2, count 2 2006.201.06:45:40.08#ibcon#*after write, iclass 2, count 2 2006.201.06:45:40.08#ibcon#*before return 0, iclass 2, count 2 2006.201.06:45:40.08#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:40.08#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.06:45:40.08#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.06:45:40.08#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:40.08#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:40.20#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:40.20#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:40.20#ibcon#enter wrdev, iclass 2, count 0 2006.201.06:45:40.20#ibcon#first serial, iclass 2, count 0 2006.201.06:45:40.20#ibcon#enter sib2, iclass 2, count 0 2006.201.06:45:40.20#ibcon#flushed, iclass 2, count 0 2006.201.06:45:40.20#ibcon#about to write, iclass 2, count 0 2006.201.06:45:40.20#ibcon#wrote, iclass 2, count 0 2006.201.06:45:40.20#ibcon#about to read 3, iclass 2, count 0 2006.201.06:45:40.22#ibcon#read 3, iclass 2, count 0 2006.201.06:45:40.22#ibcon#about to read 4, iclass 2, count 0 2006.201.06:45:40.22#ibcon#read 4, iclass 2, count 0 2006.201.06:45:40.22#ibcon#about to read 5, iclass 2, count 0 2006.201.06:45:40.22#ibcon#read 5, iclass 2, count 0 2006.201.06:45:40.22#ibcon#about to read 6, iclass 2, count 0 2006.201.06:45:40.22#ibcon#read 6, iclass 2, count 0 2006.201.06:45:40.22#ibcon#end of sib2, iclass 2, count 0 2006.201.06:45:40.22#ibcon#*mode == 0, iclass 2, count 0 2006.201.06:45:40.22#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.06:45:40.22#ibcon#[27=USB\r\n] 2006.201.06:45:40.22#ibcon#*before write, iclass 2, count 0 2006.201.06:45:40.22#ibcon#enter sib2, iclass 2, count 0 2006.201.06:45:40.22#ibcon#flushed, iclass 2, count 0 2006.201.06:45:40.22#ibcon#about to write, iclass 2, count 0 2006.201.06:45:40.22#ibcon#wrote, iclass 2, count 0 2006.201.06:45:40.22#ibcon#about to read 3, iclass 2, count 0 2006.201.06:45:40.25#ibcon#read 3, iclass 2, count 0 2006.201.06:45:40.25#ibcon#about to read 4, iclass 2, count 0 2006.201.06:45:40.25#ibcon#read 4, iclass 2, count 0 2006.201.06:45:40.25#ibcon#about to read 5, iclass 2, count 0 2006.201.06:45:40.25#ibcon#read 5, iclass 2, count 0 2006.201.06:45:40.25#ibcon#about to read 6, iclass 2, count 0 2006.201.06:45:40.25#ibcon#read 6, iclass 2, count 0 2006.201.06:45:40.25#ibcon#end of sib2, iclass 2, count 0 2006.201.06:45:40.25#ibcon#*after write, iclass 2, count 0 2006.201.06:45:40.25#ibcon#*before return 0, iclass 2, count 0 2006.201.06:45:40.25#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:40.25#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.06:45:40.25#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.06:45:40.25#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.06:45:40.25$vck44/vblo=3,649.99 2006.201.06:45:40.25#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.06:45:40.25#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.06:45:40.25#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:40.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:40.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:40.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:40.25#ibcon#enter wrdev, iclass 5, count 0 2006.201.06:45:40.25#ibcon#first serial, iclass 5, count 0 2006.201.06:45:40.25#ibcon#enter sib2, iclass 5, count 0 2006.201.06:45:40.25#ibcon#flushed, iclass 5, count 0 2006.201.06:45:40.25#ibcon#about to write, iclass 5, count 0 2006.201.06:45:40.25#ibcon#wrote, iclass 5, count 0 2006.201.06:45:40.25#ibcon#about to read 3, iclass 5, count 0 2006.201.06:45:40.27#ibcon#read 3, iclass 5, count 0 2006.201.06:45:40.27#ibcon#about to read 4, iclass 5, count 0 2006.201.06:45:40.27#ibcon#read 4, iclass 5, count 0 2006.201.06:45:40.27#ibcon#about to read 5, iclass 5, count 0 2006.201.06:45:40.27#ibcon#read 5, iclass 5, count 0 2006.201.06:45:40.27#ibcon#about to read 6, iclass 5, count 0 2006.201.06:45:40.27#ibcon#read 6, iclass 5, count 0 2006.201.06:45:40.27#ibcon#end of sib2, iclass 5, count 0 2006.201.06:45:40.27#ibcon#*mode == 0, iclass 5, count 0 2006.201.06:45:40.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.06:45:40.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.06:45:40.27#ibcon#*before write, iclass 5, count 0 2006.201.06:45:40.27#ibcon#enter sib2, iclass 5, count 0 2006.201.06:45:40.27#ibcon#flushed, iclass 5, count 0 2006.201.06:45:40.27#ibcon#about to write, iclass 5, count 0 2006.201.06:45:40.27#ibcon#wrote, iclass 5, count 0 2006.201.06:45:40.27#ibcon#about to read 3, iclass 5, count 0 2006.201.06:45:40.31#ibcon#read 3, iclass 5, count 0 2006.201.06:45:40.31#ibcon#about to read 4, iclass 5, count 0 2006.201.06:45:40.31#ibcon#read 4, iclass 5, count 0 2006.201.06:45:40.31#ibcon#about to read 5, iclass 5, count 0 2006.201.06:45:40.31#ibcon#read 5, iclass 5, count 0 2006.201.06:45:40.31#ibcon#about to read 6, iclass 5, count 0 2006.201.06:45:40.31#ibcon#read 6, iclass 5, count 0 2006.201.06:45:40.31#ibcon#end of sib2, iclass 5, count 0 2006.201.06:45:40.31#ibcon#*after write, iclass 5, count 0 2006.201.06:45:40.31#ibcon#*before return 0, iclass 5, count 0 2006.201.06:45:40.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:40.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:45:40.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.06:45:40.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.06:45:40.31$vck44/vb=3,4 2006.201.06:45:40.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.06:45:40.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.06:45:40.31#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:40.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:40.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:40.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:40.37#ibcon#enter wrdev, iclass 7, count 2 2006.201.06:45:40.37#ibcon#first serial, iclass 7, count 2 2006.201.06:45:40.37#ibcon#enter sib2, iclass 7, count 2 2006.201.06:45:40.37#ibcon#flushed, iclass 7, count 2 2006.201.06:45:40.37#ibcon#about to write, iclass 7, count 2 2006.201.06:45:40.37#ibcon#wrote, iclass 7, count 2 2006.201.06:45:40.37#ibcon#about to read 3, iclass 7, count 2 2006.201.06:45:40.39#ibcon#read 3, iclass 7, count 2 2006.201.06:45:40.39#ibcon#about to read 4, iclass 7, count 2 2006.201.06:45:40.39#ibcon#read 4, iclass 7, count 2 2006.201.06:45:40.39#ibcon#about to read 5, iclass 7, count 2 2006.201.06:45:40.39#ibcon#read 5, iclass 7, count 2 2006.201.06:45:40.39#ibcon#about to read 6, iclass 7, count 2 2006.201.06:45:40.39#ibcon#read 6, iclass 7, count 2 2006.201.06:45:40.39#ibcon#end of sib2, iclass 7, count 2 2006.201.06:45:40.39#ibcon#*mode == 0, iclass 7, count 2 2006.201.06:45:40.39#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.06:45:40.39#ibcon#[27=AT03-04\r\n] 2006.201.06:45:40.39#ibcon#*before write, iclass 7, count 2 2006.201.06:45:40.39#ibcon#enter sib2, iclass 7, count 2 2006.201.06:45:40.39#ibcon#flushed, iclass 7, count 2 2006.201.06:45:40.39#ibcon#about to write, iclass 7, count 2 2006.201.06:45:40.39#ibcon#wrote, iclass 7, count 2 2006.201.06:45:40.39#ibcon#about to read 3, iclass 7, count 2 2006.201.06:45:40.42#ibcon#read 3, iclass 7, count 2 2006.201.06:45:40.42#ibcon#about to read 4, iclass 7, count 2 2006.201.06:45:40.42#ibcon#read 4, iclass 7, count 2 2006.201.06:45:40.42#ibcon#about to read 5, iclass 7, count 2 2006.201.06:45:40.42#ibcon#read 5, iclass 7, count 2 2006.201.06:45:40.42#ibcon#about to read 6, iclass 7, count 2 2006.201.06:45:40.42#ibcon#read 6, iclass 7, count 2 2006.201.06:45:40.42#ibcon#end of sib2, iclass 7, count 2 2006.201.06:45:40.42#ibcon#*after write, iclass 7, count 2 2006.201.06:45:40.42#ibcon#*before return 0, iclass 7, count 2 2006.201.06:45:40.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:40.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.06:45:40.42#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.06:45:40.42#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:40.42#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:40.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:40.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:40.54#ibcon#enter wrdev, iclass 7, count 0 2006.201.06:45:40.54#ibcon#first serial, iclass 7, count 0 2006.201.06:45:40.54#ibcon#enter sib2, iclass 7, count 0 2006.201.06:45:40.54#ibcon#flushed, iclass 7, count 0 2006.201.06:45:40.54#ibcon#about to write, iclass 7, count 0 2006.201.06:45:40.54#ibcon#wrote, iclass 7, count 0 2006.201.06:45:40.54#ibcon#about to read 3, iclass 7, count 0 2006.201.06:45:40.56#ibcon#read 3, iclass 7, count 0 2006.201.06:45:40.56#ibcon#about to read 4, iclass 7, count 0 2006.201.06:45:40.56#ibcon#read 4, iclass 7, count 0 2006.201.06:45:40.56#ibcon#about to read 5, iclass 7, count 0 2006.201.06:45:40.56#ibcon#read 5, iclass 7, count 0 2006.201.06:45:40.56#ibcon#about to read 6, iclass 7, count 0 2006.201.06:45:40.56#ibcon#read 6, iclass 7, count 0 2006.201.06:45:40.56#ibcon#end of sib2, iclass 7, count 0 2006.201.06:45:40.56#ibcon#*mode == 0, iclass 7, count 0 2006.201.06:45:40.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.06:45:40.56#ibcon#[27=USB\r\n] 2006.201.06:45:40.56#ibcon#*before write, iclass 7, count 0 2006.201.06:45:40.56#ibcon#enter sib2, iclass 7, count 0 2006.201.06:45:40.56#ibcon#flushed, iclass 7, count 0 2006.201.06:45:40.56#ibcon#about to write, iclass 7, count 0 2006.201.06:45:40.56#ibcon#wrote, iclass 7, count 0 2006.201.06:45:40.56#ibcon#about to read 3, iclass 7, count 0 2006.201.06:45:40.59#ibcon#read 3, iclass 7, count 0 2006.201.06:45:40.59#ibcon#about to read 4, iclass 7, count 0 2006.201.06:45:40.59#ibcon#read 4, iclass 7, count 0 2006.201.06:45:40.59#ibcon#about to read 5, iclass 7, count 0 2006.201.06:45:40.59#ibcon#read 5, iclass 7, count 0 2006.201.06:45:40.59#ibcon#about to read 6, iclass 7, count 0 2006.201.06:45:40.59#ibcon#read 6, iclass 7, count 0 2006.201.06:45:40.59#ibcon#end of sib2, iclass 7, count 0 2006.201.06:45:40.59#ibcon#*after write, iclass 7, count 0 2006.201.06:45:40.59#ibcon#*before return 0, iclass 7, count 0 2006.201.06:45:40.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:40.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.06:45:40.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.06:45:40.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.06:45:40.59$vck44/vblo=4,679.99 2006.201.06:45:40.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.06:45:40.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.06:45:40.59#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:40.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:40.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:40.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:40.59#ibcon#enter wrdev, iclass 11, count 0 2006.201.06:45:40.59#ibcon#first serial, iclass 11, count 0 2006.201.06:45:40.59#ibcon#enter sib2, iclass 11, count 0 2006.201.06:45:40.59#ibcon#flushed, iclass 11, count 0 2006.201.06:45:40.59#ibcon#about to write, iclass 11, count 0 2006.201.06:45:40.59#ibcon#wrote, iclass 11, count 0 2006.201.06:45:40.59#ibcon#about to read 3, iclass 11, count 0 2006.201.06:45:40.61#ibcon#read 3, iclass 11, count 0 2006.201.06:45:40.61#ibcon#about to read 4, iclass 11, count 0 2006.201.06:45:40.61#ibcon#read 4, iclass 11, count 0 2006.201.06:45:40.61#ibcon#about to read 5, iclass 11, count 0 2006.201.06:45:40.61#ibcon#read 5, iclass 11, count 0 2006.201.06:45:40.61#ibcon#about to read 6, iclass 11, count 0 2006.201.06:45:40.61#ibcon#read 6, iclass 11, count 0 2006.201.06:45:40.61#ibcon#end of sib2, iclass 11, count 0 2006.201.06:45:40.61#ibcon#*mode == 0, iclass 11, count 0 2006.201.06:45:40.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.06:45:40.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.06:45:40.61#ibcon#*before write, iclass 11, count 0 2006.201.06:45:40.61#ibcon#enter sib2, iclass 11, count 0 2006.201.06:45:40.61#ibcon#flushed, iclass 11, count 0 2006.201.06:45:40.61#ibcon#about to write, iclass 11, count 0 2006.201.06:45:40.61#ibcon#wrote, iclass 11, count 0 2006.201.06:45:40.61#ibcon#about to read 3, iclass 11, count 0 2006.201.06:45:40.66#ibcon#read 3, iclass 11, count 0 2006.201.06:45:40.66#ibcon#about to read 4, iclass 11, count 0 2006.201.06:45:40.66#ibcon#read 4, iclass 11, count 0 2006.201.06:45:40.66#ibcon#about to read 5, iclass 11, count 0 2006.201.06:45:40.66#ibcon#read 5, iclass 11, count 0 2006.201.06:45:40.66#ibcon#about to read 6, iclass 11, count 0 2006.201.06:45:40.66#ibcon#read 6, iclass 11, count 0 2006.201.06:45:40.66#ibcon#end of sib2, iclass 11, count 0 2006.201.06:45:40.66#ibcon#*after write, iclass 11, count 0 2006.201.06:45:40.66#ibcon#*before return 0, iclass 11, count 0 2006.201.06:45:40.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:40.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.06:45:40.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.06:45:40.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.06:45:40.66$vck44/vb=4,5 2006.201.06:45:40.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.06:45:40.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.06:45:40.66#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:40.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:40.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:40.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:40.71#ibcon#enter wrdev, iclass 13, count 2 2006.201.06:45:40.71#ibcon#first serial, iclass 13, count 2 2006.201.06:45:40.71#ibcon#enter sib2, iclass 13, count 2 2006.201.06:45:40.71#ibcon#flushed, iclass 13, count 2 2006.201.06:45:40.71#ibcon#about to write, iclass 13, count 2 2006.201.06:45:40.71#ibcon#wrote, iclass 13, count 2 2006.201.06:45:40.71#ibcon#about to read 3, iclass 13, count 2 2006.201.06:45:40.73#ibcon#read 3, iclass 13, count 2 2006.201.06:45:40.73#ibcon#about to read 4, iclass 13, count 2 2006.201.06:45:40.73#ibcon#read 4, iclass 13, count 2 2006.201.06:45:40.73#ibcon#about to read 5, iclass 13, count 2 2006.201.06:45:40.73#ibcon#read 5, iclass 13, count 2 2006.201.06:45:40.73#ibcon#about to read 6, iclass 13, count 2 2006.201.06:45:40.73#ibcon#read 6, iclass 13, count 2 2006.201.06:45:40.73#ibcon#end of sib2, iclass 13, count 2 2006.201.06:45:40.73#ibcon#*mode == 0, iclass 13, count 2 2006.201.06:45:40.73#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.06:45:40.73#ibcon#[27=AT04-05\r\n] 2006.201.06:45:40.73#ibcon#*before write, iclass 13, count 2 2006.201.06:45:40.73#ibcon#enter sib2, iclass 13, count 2 2006.201.06:45:40.73#ibcon#flushed, iclass 13, count 2 2006.201.06:45:40.73#ibcon#about to write, iclass 13, count 2 2006.201.06:45:40.73#ibcon#wrote, iclass 13, count 2 2006.201.06:45:40.73#ibcon#about to read 3, iclass 13, count 2 2006.201.06:45:40.76#ibcon#read 3, iclass 13, count 2 2006.201.06:45:40.76#ibcon#about to read 4, iclass 13, count 2 2006.201.06:45:40.76#ibcon#read 4, iclass 13, count 2 2006.201.06:45:40.76#ibcon#about to read 5, iclass 13, count 2 2006.201.06:45:40.76#ibcon#read 5, iclass 13, count 2 2006.201.06:45:40.76#ibcon#about to read 6, iclass 13, count 2 2006.201.06:45:40.76#ibcon#read 6, iclass 13, count 2 2006.201.06:45:40.76#ibcon#end of sib2, iclass 13, count 2 2006.201.06:45:40.76#ibcon#*after write, iclass 13, count 2 2006.201.06:45:40.76#ibcon#*before return 0, iclass 13, count 2 2006.201.06:45:40.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:40.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.06:45:40.76#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.06:45:40.76#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:40.76#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:40.88#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:40.88#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:40.88#ibcon#enter wrdev, iclass 13, count 0 2006.201.06:45:40.88#ibcon#first serial, iclass 13, count 0 2006.201.06:45:40.88#ibcon#enter sib2, iclass 13, count 0 2006.201.06:45:40.88#ibcon#flushed, iclass 13, count 0 2006.201.06:45:40.88#ibcon#about to write, iclass 13, count 0 2006.201.06:45:40.88#ibcon#wrote, iclass 13, count 0 2006.201.06:45:40.88#ibcon#about to read 3, iclass 13, count 0 2006.201.06:45:40.90#ibcon#read 3, iclass 13, count 0 2006.201.06:45:40.90#ibcon#about to read 4, iclass 13, count 0 2006.201.06:45:40.90#ibcon#read 4, iclass 13, count 0 2006.201.06:45:40.90#ibcon#about to read 5, iclass 13, count 0 2006.201.06:45:40.90#ibcon#read 5, iclass 13, count 0 2006.201.06:45:40.90#ibcon#about to read 6, iclass 13, count 0 2006.201.06:45:40.90#ibcon#read 6, iclass 13, count 0 2006.201.06:45:40.90#ibcon#end of sib2, iclass 13, count 0 2006.201.06:45:40.90#ibcon#*mode == 0, iclass 13, count 0 2006.201.06:45:40.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.06:45:40.90#ibcon#[27=USB\r\n] 2006.201.06:45:40.90#ibcon#*before write, iclass 13, count 0 2006.201.06:45:40.90#ibcon#enter sib2, iclass 13, count 0 2006.201.06:45:40.90#ibcon#flushed, iclass 13, count 0 2006.201.06:45:40.90#ibcon#about to write, iclass 13, count 0 2006.201.06:45:40.90#ibcon#wrote, iclass 13, count 0 2006.201.06:45:40.90#ibcon#about to read 3, iclass 13, count 0 2006.201.06:45:40.93#ibcon#read 3, iclass 13, count 0 2006.201.06:45:40.93#ibcon#about to read 4, iclass 13, count 0 2006.201.06:45:40.93#ibcon#read 4, iclass 13, count 0 2006.201.06:45:40.93#ibcon#about to read 5, iclass 13, count 0 2006.201.06:45:40.93#ibcon#read 5, iclass 13, count 0 2006.201.06:45:40.93#ibcon#about to read 6, iclass 13, count 0 2006.201.06:45:40.93#ibcon#read 6, iclass 13, count 0 2006.201.06:45:40.93#ibcon#end of sib2, iclass 13, count 0 2006.201.06:45:40.93#ibcon#*after write, iclass 13, count 0 2006.201.06:45:40.93#ibcon#*before return 0, iclass 13, count 0 2006.201.06:45:40.93#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:40.93#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.06:45:40.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.06:45:40.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.06:45:40.93$vck44/vblo=5,709.99 2006.201.06:45:40.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.06:45:40.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.06:45:40.93#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:40.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:40.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:40.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:40.93#ibcon#enter wrdev, iclass 15, count 0 2006.201.06:45:40.93#ibcon#first serial, iclass 15, count 0 2006.201.06:45:40.93#ibcon#enter sib2, iclass 15, count 0 2006.201.06:45:40.93#ibcon#flushed, iclass 15, count 0 2006.201.06:45:40.93#ibcon#about to write, iclass 15, count 0 2006.201.06:45:40.93#ibcon#wrote, iclass 15, count 0 2006.201.06:45:40.93#ibcon#about to read 3, iclass 15, count 0 2006.201.06:45:40.95#ibcon#read 3, iclass 15, count 0 2006.201.06:45:40.95#ibcon#about to read 4, iclass 15, count 0 2006.201.06:45:40.95#ibcon#read 4, iclass 15, count 0 2006.201.06:45:40.95#ibcon#about to read 5, iclass 15, count 0 2006.201.06:45:40.95#ibcon#read 5, iclass 15, count 0 2006.201.06:45:40.95#ibcon#about to read 6, iclass 15, count 0 2006.201.06:45:40.95#ibcon#read 6, iclass 15, count 0 2006.201.06:45:40.95#ibcon#end of sib2, iclass 15, count 0 2006.201.06:45:40.95#ibcon#*mode == 0, iclass 15, count 0 2006.201.06:45:40.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.06:45:40.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.06:45:40.95#ibcon#*before write, iclass 15, count 0 2006.201.06:45:40.95#ibcon#enter sib2, iclass 15, count 0 2006.201.06:45:40.95#ibcon#flushed, iclass 15, count 0 2006.201.06:45:40.95#ibcon#about to write, iclass 15, count 0 2006.201.06:45:40.95#ibcon#wrote, iclass 15, count 0 2006.201.06:45:40.95#ibcon#about to read 3, iclass 15, count 0 2006.201.06:45:40.99#ibcon#read 3, iclass 15, count 0 2006.201.06:45:40.99#ibcon#about to read 4, iclass 15, count 0 2006.201.06:45:40.99#ibcon#read 4, iclass 15, count 0 2006.201.06:45:40.99#ibcon#about to read 5, iclass 15, count 0 2006.201.06:45:40.99#ibcon#read 5, iclass 15, count 0 2006.201.06:45:40.99#ibcon#about to read 6, iclass 15, count 0 2006.201.06:45:40.99#ibcon#read 6, iclass 15, count 0 2006.201.06:45:40.99#ibcon#end of sib2, iclass 15, count 0 2006.201.06:45:40.99#ibcon#*after write, iclass 15, count 0 2006.201.06:45:40.99#ibcon#*before return 0, iclass 15, count 0 2006.201.06:45:40.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:40.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:45:40.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.06:45:40.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.06:45:40.99$vck44/vb=5,4 2006.201.06:45:40.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.06:45:40.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.06:45:40.99#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:40.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:41.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:41.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:41.05#ibcon#enter wrdev, iclass 17, count 2 2006.201.06:45:41.05#ibcon#first serial, iclass 17, count 2 2006.201.06:45:41.05#ibcon#enter sib2, iclass 17, count 2 2006.201.06:45:41.05#ibcon#flushed, iclass 17, count 2 2006.201.06:45:41.05#ibcon#about to write, iclass 17, count 2 2006.201.06:45:41.05#ibcon#wrote, iclass 17, count 2 2006.201.06:45:41.05#ibcon#about to read 3, iclass 17, count 2 2006.201.06:45:41.07#ibcon#read 3, iclass 17, count 2 2006.201.06:45:41.07#ibcon#about to read 4, iclass 17, count 2 2006.201.06:45:41.07#ibcon#read 4, iclass 17, count 2 2006.201.06:45:41.07#ibcon#about to read 5, iclass 17, count 2 2006.201.06:45:41.07#ibcon#read 5, iclass 17, count 2 2006.201.06:45:41.07#ibcon#about to read 6, iclass 17, count 2 2006.201.06:45:41.07#ibcon#read 6, iclass 17, count 2 2006.201.06:45:41.07#ibcon#end of sib2, iclass 17, count 2 2006.201.06:45:41.07#ibcon#*mode == 0, iclass 17, count 2 2006.201.06:45:41.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.06:45:41.07#ibcon#[27=AT05-04\r\n] 2006.201.06:45:41.07#ibcon#*before write, iclass 17, count 2 2006.201.06:45:41.07#ibcon#enter sib2, iclass 17, count 2 2006.201.06:45:41.07#ibcon#flushed, iclass 17, count 2 2006.201.06:45:41.07#ibcon#about to write, iclass 17, count 2 2006.201.06:45:41.07#ibcon#wrote, iclass 17, count 2 2006.201.06:45:41.07#ibcon#about to read 3, iclass 17, count 2 2006.201.06:45:41.10#ibcon#read 3, iclass 17, count 2 2006.201.06:45:41.10#ibcon#about to read 4, iclass 17, count 2 2006.201.06:45:41.10#ibcon#read 4, iclass 17, count 2 2006.201.06:45:41.10#ibcon#about to read 5, iclass 17, count 2 2006.201.06:45:41.10#ibcon#read 5, iclass 17, count 2 2006.201.06:45:41.10#ibcon#about to read 6, iclass 17, count 2 2006.201.06:45:41.10#ibcon#read 6, iclass 17, count 2 2006.201.06:45:41.10#ibcon#end of sib2, iclass 17, count 2 2006.201.06:45:41.10#ibcon#*after write, iclass 17, count 2 2006.201.06:45:41.10#ibcon#*before return 0, iclass 17, count 2 2006.201.06:45:41.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:41.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.06:45:41.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.06:45:41.10#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:41.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:41.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:41.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:41.22#ibcon#enter wrdev, iclass 17, count 0 2006.201.06:45:41.22#ibcon#first serial, iclass 17, count 0 2006.201.06:45:41.22#ibcon#enter sib2, iclass 17, count 0 2006.201.06:45:41.22#ibcon#flushed, iclass 17, count 0 2006.201.06:45:41.22#ibcon#about to write, iclass 17, count 0 2006.201.06:45:41.22#ibcon#wrote, iclass 17, count 0 2006.201.06:45:41.22#ibcon#about to read 3, iclass 17, count 0 2006.201.06:45:41.24#ibcon#read 3, iclass 17, count 0 2006.201.06:45:41.24#ibcon#about to read 4, iclass 17, count 0 2006.201.06:45:41.24#ibcon#read 4, iclass 17, count 0 2006.201.06:45:41.24#ibcon#about to read 5, iclass 17, count 0 2006.201.06:45:41.24#ibcon#read 5, iclass 17, count 0 2006.201.06:45:41.24#ibcon#about to read 6, iclass 17, count 0 2006.201.06:45:41.24#ibcon#read 6, iclass 17, count 0 2006.201.06:45:41.24#ibcon#end of sib2, iclass 17, count 0 2006.201.06:45:41.24#ibcon#*mode == 0, iclass 17, count 0 2006.201.06:45:41.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.06:45:41.24#ibcon#[27=USB\r\n] 2006.201.06:45:41.24#ibcon#*before write, iclass 17, count 0 2006.201.06:45:41.24#ibcon#enter sib2, iclass 17, count 0 2006.201.06:45:41.24#ibcon#flushed, iclass 17, count 0 2006.201.06:45:41.24#ibcon#about to write, iclass 17, count 0 2006.201.06:45:41.24#ibcon#wrote, iclass 17, count 0 2006.201.06:45:41.24#ibcon#about to read 3, iclass 17, count 0 2006.201.06:45:41.27#ibcon#read 3, iclass 17, count 0 2006.201.06:45:41.27#ibcon#about to read 4, iclass 17, count 0 2006.201.06:45:41.27#ibcon#read 4, iclass 17, count 0 2006.201.06:45:41.27#ibcon#about to read 5, iclass 17, count 0 2006.201.06:45:41.27#ibcon#read 5, iclass 17, count 0 2006.201.06:45:41.27#ibcon#about to read 6, iclass 17, count 0 2006.201.06:45:41.27#ibcon#read 6, iclass 17, count 0 2006.201.06:45:41.27#ibcon#end of sib2, iclass 17, count 0 2006.201.06:45:41.27#ibcon#*after write, iclass 17, count 0 2006.201.06:45:41.27#ibcon#*before return 0, iclass 17, count 0 2006.201.06:45:41.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:41.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.06:45:41.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.06:45:41.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.06:45:41.27$vck44/vblo=6,719.99 2006.201.06:45:41.27#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.06:45:41.27#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.06:45:41.27#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:41.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:41.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:41.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:41.27#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:45:41.27#ibcon#first serial, iclass 19, count 0 2006.201.06:45:41.27#ibcon#enter sib2, iclass 19, count 0 2006.201.06:45:41.27#ibcon#flushed, iclass 19, count 0 2006.201.06:45:41.27#ibcon#about to write, iclass 19, count 0 2006.201.06:45:41.27#ibcon#wrote, iclass 19, count 0 2006.201.06:45:41.27#ibcon#about to read 3, iclass 19, count 0 2006.201.06:45:41.29#ibcon#read 3, iclass 19, count 0 2006.201.06:45:41.29#ibcon#about to read 4, iclass 19, count 0 2006.201.06:45:41.29#ibcon#read 4, iclass 19, count 0 2006.201.06:45:41.29#ibcon#about to read 5, iclass 19, count 0 2006.201.06:45:41.29#ibcon#read 5, iclass 19, count 0 2006.201.06:45:41.29#ibcon#about to read 6, iclass 19, count 0 2006.201.06:45:41.29#ibcon#read 6, iclass 19, count 0 2006.201.06:45:41.29#ibcon#end of sib2, iclass 19, count 0 2006.201.06:45:41.29#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:45:41.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:45:41.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.06:45:41.29#ibcon#*before write, iclass 19, count 0 2006.201.06:45:41.29#ibcon#enter sib2, iclass 19, count 0 2006.201.06:45:41.29#ibcon#flushed, iclass 19, count 0 2006.201.06:45:41.29#ibcon#about to write, iclass 19, count 0 2006.201.06:45:41.29#ibcon#wrote, iclass 19, count 0 2006.201.06:45:41.29#ibcon#about to read 3, iclass 19, count 0 2006.201.06:45:41.33#ibcon#read 3, iclass 19, count 0 2006.201.06:45:41.33#ibcon#about to read 4, iclass 19, count 0 2006.201.06:45:41.33#ibcon#read 4, iclass 19, count 0 2006.201.06:45:41.33#ibcon#about to read 5, iclass 19, count 0 2006.201.06:45:41.33#ibcon#read 5, iclass 19, count 0 2006.201.06:45:41.33#ibcon#about to read 6, iclass 19, count 0 2006.201.06:45:41.33#ibcon#read 6, iclass 19, count 0 2006.201.06:45:41.33#ibcon#end of sib2, iclass 19, count 0 2006.201.06:45:41.33#ibcon#*after write, iclass 19, count 0 2006.201.06:45:41.33#ibcon#*before return 0, iclass 19, count 0 2006.201.06:45:41.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:41.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.06:45:41.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:45:41.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:45:41.33$vck44/vb=6,4 2006.201.06:45:41.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.06:45:41.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.06:45:41.33#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:41.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:41.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:41.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:41.39#ibcon#enter wrdev, iclass 21, count 2 2006.201.06:45:41.39#ibcon#first serial, iclass 21, count 2 2006.201.06:45:41.39#ibcon#enter sib2, iclass 21, count 2 2006.201.06:45:41.39#ibcon#flushed, iclass 21, count 2 2006.201.06:45:41.39#ibcon#about to write, iclass 21, count 2 2006.201.06:45:41.39#ibcon#wrote, iclass 21, count 2 2006.201.06:45:41.39#ibcon#about to read 3, iclass 21, count 2 2006.201.06:45:41.41#ibcon#read 3, iclass 21, count 2 2006.201.06:45:41.41#ibcon#about to read 4, iclass 21, count 2 2006.201.06:45:41.41#ibcon#read 4, iclass 21, count 2 2006.201.06:45:41.41#ibcon#about to read 5, iclass 21, count 2 2006.201.06:45:41.41#ibcon#read 5, iclass 21, count 2 2006.201.06:45:41.41#ibcon#about to read 6, iclass 21, count 2 2006.201.06:45:41.41#ibcon#read 6, iclass 21, count 2 2006.201.06:45:41.41#ibcon#end of sib2, iclass 21, count 2 2006.201.06:45:41.41#ibcon#*mode == 0, iclass 21, count 2 2006.201.06:45:41.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.06:45:41.41#ibcon#[27=AT06-04\r\n] 2006.201.06:45:41.41#ibcon#*before write, iclass 21, count 2 2006.201.06:45:41.41#ibcon#enter sib2, iclass 21, count 2 2006.201.06:45:41.41#ibcon#flushed, iclass 21, count 2 2006.201.06:45:41.41#ibcon#about to write, iclass 21, count 2 2006.201.06:45:41.41#ibcon#wrote, iclass 21, count 2 2006.201.06:45:41.41#ibcon#about to read 3, iclass 21, count 2 2006.201.06:45:41.44#ibcon#read 3, iclass 21, count 2 2006.201.06:45:41.44#ibcon#about to read 4, iclass 21, count 2 2006.201.06:45:41.44#ibcon#read 4, iclass 21, count 2 2006.201.06:45:41.44#ibcon#about to read 5, iclass 21, count 2 2006.201.06:45:41.44#ibcon#read 5, iclass 21, count 2 2006.201.06:45:41.44#ibcon#about to read 6, iclass 21, count 2 2006.201.06:45:41.44#ibcon#read 6, iclass 21, count 2 2006.201.06:45:41.44#ibcon#end of sib2, iclass 21, count 2 2006.201.06:45:41.44#ibcon#*after write, iclass 21, count 2 2006.201.06:45:41.44#ibcon#*before return 0, iclass 21, count 2 2006.201.06:45:41.44#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:41.44#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.06:45:41.44#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.06:45:41.44#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:41.44#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:41.56#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:41.56#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:41.56#ibcon#enter wrdev, iclass 21, count 0 2006.201.06:45:41.56#ibcon#first serial, iclass 21, count 0 2006.201.06:45:41.56#ibcon#enter sib2, iclass 21, count 0 2006.201.06:45:41.56#ibcon#flushed, iclass 21, count 0 2006.201.06:45:41.56#ibcon#about to write, iclass 21, count 0 2006.201.06:45:41.56#ibcon#wrote, iclass 21, count 0 2006.201.06:45:41.56#ibcon#about to read 3, iclass 21, count 0 2006.201.06:45:41.58#ibcon#read 3, iclass 21, count 0 2006.201.06:45:41.58#ibcon#about to read 4, iclass 21, count 0 2006.201.06:45:41.58#ibcon#read 4, iclass 21, count 0 2006.201.06:45:41.58#ibcon#about to read 5, iclass 21, count 0 2006.201.06:45:41.58#ibcon#read 5, iclass 21, count 0 2006.201.06:45:41.58#ibcon#about to read 6, iclass 21, count 0 2006.201.06:45:41.58#ibcon#read 6, iclass 21, count 0 2006.201.06:45:41.58#ibcon#end of sib2, iclass 21, count 0 2006.201.06:45:41.58#ibcon#*mode == 0, iclass 21, count 0 2006.201.06:45:41.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.06:45:41.58#ibcon#[27=USB\r\n] 2006.201.06:45:41.58#ibcon#*before write, iclass 21, count 0 2006.201.06:45:41.58#ibcon#enter sib2, iclass 21, count 0 2006.201.06:45:41.58#ibcon#flushed, iclass 21, count 0 2006.201.06:45:41.58#ibcon#about to write, iclass 21, count 0 2006.201.06:45:41.58#ibcon#wrote, iclass 21, count 0 2006.201.06:45:41.58#ibcon#about to read 3, iclass 21, count 0 2006.201.06:45:41.61#ibcon#read 3, iclass 21, count 0 2006.201.06:45:41.61#ibcon#about to read 4, iclass 21, count 0 2006.201.06:45:41.61#ibcon#read 4, iclass 21, count 0 2006.201.06:45:41.61#ibcon#about to read 5, iclass 21, count 0 2006.201.06:45:41.61#ibcon#read 5, iclass 21, count 0 2006.201.06:45:41.61#ibcon#about to read 6, iclass 21, count 0 2006.201.06:45:41.61#ibcon#read 6, iclass 21, count 0 2006.201.06:45:41.61#ibcon#end of sib2, iclass 21, count 0 2006.201.06:45:41.61#ibcon#*after write, iclass 21, count 0 2006.201.06:45:41.61#ibcon#*before return 0, iclass 21, count 0 2006.201.06:45:41.61#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:41.61#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.06:45:41.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.06:45:41.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.06:45:41.61$vck44/vblo=7,734.99 2006.201.06:45:41.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.06:45:41.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.06:45:41.61#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:41.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:41.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:41.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:41.61#ibcon#enter wrdev, iclass 23, count 0 2006.201.06:45:41.61#ibcon#first serial, iclass 23, count 0 2006.201.06:45:41.61#ibcon#enter sib2, iclass 23, count 0 2006.201.06:45:41.61#ibcon#flushed, iclass 23, count 0 2006.201.06:45:41.61#ibcon#about to write, iclass 23, count 0 2006.201.06:45:41.61#ibcon#wrote, iclass 23, count 0 2006.201.06:45:41.61#ibcon#about to read 3, iclass 23, count 0 2006.201.06:45:41.63#ibcon#read 3, iclass 23, count 0 2006.201.06:45:41.63#ibcon#about to read 4, iclass 23, count 0 2006.201.06:45:41.63#ibcon#read 4, iclass 23, count 0 2006.201.06:45:41.63#ibcon#about to read 5, iclass 23, count 0 2006.201.06:45:41.63#ibcon#read 5, iclass 23, count 0 2006.201.06:45:41.63#ibcon#about to read 6, iclass 23, count 0 2006.201.06:45:41.63#ibcon#read 6, iclass 23, count 0 2006.201.06:45:41.63#ibcon#end of sib2, iclass 23, count 0 2006.201.06:45:41.63#ibcon#*mode == 0, iclass 23, count 0 2006.201.06:45:41.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.06:45:41.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.06:45:41.63#ibcon#*before write, iclass 23, count 0 2006.201.06:45:41.63#ibcon#enter sib2, iclass 23, count 0 2006.201.06:45:41.63#ibcon#flushed, iclass 23, count 0 2006.201.06:45:41.63#ibcon#about to write, iclass 23, count 0 2006.201.06:45:41.63#ibcon#wrote, iclass 23, count 0 2006.201.06:45:41.63#ibcon#about to read 3, iclass 23, count 0 2006.201.06:45:41.68#ibcon#read 3, iclass 23, count 0 2006.201.06:45:41.68#ibcon#about to read 4, iclass 23, count 0 2006.201.06:45:41.68#ibcon#read 4, iclass 23, count 0 2006.201.06:45:41.68#ibcon#about to read 5, iclass 23, count 0 2006.201.06:45:41.68#ibcon#read 5, iclass 23, count 0 2006.201.06:45:41.68#ibcon#about to read 6, iclass 23, count 0 2006.201.06:45:41.68#ibcon#read 6, iclass 23, count 0 2006.201.06:45:41.68#ibcon#end of sib2, iclass 23, count 0 2006.201.06:45:41.68#ibcon#*after write, iclass 23, count 0 2006.201.06:45:41.68#ibcon#*before return 0, iclass 23, count 0 2006.201.06:45:41.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:41.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.06:45:41.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.06:45:41.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.06:45:41.68$vck44/vb=7,4 2006.201.06:45:41.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.06:45:41.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.06:45:41.68#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:41.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:41.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:41.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:41.73#ibcon#enter wrdev, iclass 25, count 2 2006.201.06:45:41.73#ibcon#first serial, iclass 25, count 2 2006.201.06:45:41.73#ibcon#enter sib2, iclass 25, count 2 2006.201.06:45:41.73#ibcon#flushed, iclass 25, count 2 2006.201.06:45:41.73#ibcon#about to write, iclass 25, count 2 2006.201.06:45:41.73#ibcon#wrote, iclass 25, count 2 2006.201.06:45:41.73#ibcon#about to read 3, iclass 25, count 2 2006.201.06:45:41.75#ibcon#read 3, iclass 25, count 2 2006.201.06:45:41.75#ibcon#about to read 4, iclass 25, count 2 2006.201.06:45:41.75#ibcon#read 4, iclass 25, count 2 2006.201.06:45:41.75#ibcon#about to read 5, iclass 25, count 2 2006.201.06:45:41.75#ibcon#read 5, iclass 25, count 2 2006.201.06:45:41.75#ibcon#about to read 6, iclass 25, count 2 2006.201.06:45:41.75#ibcon#read 6, iclass 25, count 2 2006.201.06:45:41.75#ibcon#end of sib2, iclass 25, count 2 2006.201.06:45:41.75#ibcon#*mode == 0, iclass 25, count 2 2006.201.06:45:41.75#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.06:45:41.75#ibcon#[27=AT07-04\r\n] 2006.201.06:45:41.75#ibcon#*before write, iclass 25, count 2 2006.201.06:45:41.75#ibcon#enter sib2, iclass 25, count 2 2006.201.06:45:41.75#ibcon#flushed, iclass 25, count 2 2006.201.06:45:41.75#ibcon#about to write, iclass 25, count 2 2006.201.06:45:41.75#ibcon#wrote, iclass 25, count 2 2006.201.06:45:41.75#ibcon#about to read 3, iclass 25, count 2 2006.201.06:45:41.78#ibcon#read 3, iclass 25, count 2 2006.201.06:45:41.78#ibcon#about to read 4, iclass 25, count 2 2006.201.06:45:41.78#ibcon#read 4, iclass 25, count 2 2006.201.06:45:41.78#ibcon#about to read 5, iclass 25, count 2 2006.201.06:45:41.78#ibcon#read 5, iclass 25, count 2 2006.201.06:45:41.78#ibcon#about to read 6, iclass 25, count 2 2006.201.06:45:41.78#ibcon#read 6, iclass 25, count 2 2006.201.06:45:41.78#ibcon#end of sib2, iclass 25, count 2 2006.201.06:45:41.78#ibcon#*after write, iclass 25, count 2 2006.201.06:45:41.78#ibcon#*before return 0, iclass 25, count 2 2006.201.06:45:41.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:41.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.06:45:41.78#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.06:45:41.78#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:41.78#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:41.90#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:41.90#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:41.90#ibcon#enter wrdev, iclass 25, count 0 2006.201.06:45:41.90#ibcon#first serial, iclass 25, count 0 2006.201.06:45:41.90#ibcon#enter sib2, iclass 25, count 0 2006.201.06:45:41.90#ibcon#flushed, iclass 25, count 0 2006.201.06:45:41.90#ibcon#about to write, iclass 25, count 0 2006.201.06:45:41.90#ibcon#wrote, iclass 25, count 0 2006.201.06:45:41.90#ibcon#about to read 3, iclass 25, count 0 2006.201.06:45:41.92#ibcon#read 3, iclass 25, count 0 2006.201.06:45:41.92#ibcon#about to read 4, iclass 25, count 0 2006.201.06:45:41.92#ibcon#read 4, iclass 25, count 0 2006.201.06:45:41.92#ibcon#about to read 5, iclass 25, count 0 2006.201.06:45:41.92#ibcon#read 5, iclass 25, count 0 2006.201.06:45:41.92#ibcon#about to read 6, iclass 25, count 0 2006.201.06:45:41.92#ibcon#read 6, iclass 25, count 0 2006.201.06:45:41.92#ibcon#end of sib2, iclass 25, count 0 2006.201.06:45:41.92#ibcon#*mode == 0, iclass 25, count 0 2006.201.06:45:41.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.06:45:41.92#ibcon#[27=USB\r\n] 2006.201.06:45:41.92#ibcon#*before write, iclass 25, count 0 2006.201.06:45:41.92#ibcon#enter sib2, iclass 25, count 0 2006.201.06:45:41.92#ibcon#flushed, iclass 25, count 0 2006.201.06:45:41.92#ibcon#about to write, iclass 25, count 0 2006.201.06:45:41.92#ibcon#wrote, iclass 25, count 0 2006.201.06:45:41.92#ibcon#about to read 3, iclass 25, count 0 2006.201.06:45:41.95#ibcon#read 3, iclass 25, count 0 2006.201.06:45:41.95#ibcon#about to read 4, iclass 25, count 0 2006.201.06:45:41.95#ibcon#read 4, iclass 25, count 0 2006.201.06:45:41.95#ibcon#about to read 5, iclass 25, count 0 2006.201.06:45:41.95#ibcon#read 5, iclass 25, count 0 2006.201.06:45:41.95#ibcon#about to read 6, iclass 25, count 0 2006.201.06:45:41.95#ibcon#read 6, iclass 25, count 0 2006.201.06:45:41.95#ibcon#end of sib2, iclass 25, count 0 2006.201.06:45:41.95#ibcon#*after write, iclass 25, count 0 2006.201.06:45:41.95#ibcon#*before return 0, iclass 25, count 0 2006.201.06:45:41.95#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:41.95#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.06:45:41.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.06:45:41.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.06:45:41.95$vck44/vblo=8,744.99 2006.201.06:45:41.95#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.06:45:41.95#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.06:45:41.95#ibcon#ireg 17 cls_cnt 0 2006.201.06:45:41.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:41.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:41.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:41.95#ibcon#enter wrdev, iclass 27, count 0 2006.201.06:45:41.95#ibcon#first serial, iclass 27, count 0 2006.201.06:45:41.95#ibcon#enter sib2, iclass 27, count 0 2006.201.06:45:41.95#ibcon#flushed, iclass 27, count 0 2006.201.06:45:41.95#ibcon#about to write, iclass 27, count 0 2006.201.06:45:41.95#ibcon#wrote, iclass 27, count 0 2006.201.06:45:41.95#ibcon#about to read 3, iclass 27, count 0 2006.201.06:45:41.97#ibcon#read 3, iclass 27, count 0 2006.201.06:45:41.97#ibcon#about to read 4, iclass 27, count 0 2006.201.06:45:41.97#ibcon#read 4, iclass 27, count 0 2006.201.06:45:41.97#ibcon#about to read 5, iclass 27, count 0 2006.201.06:45:41.97#ibcon#read 5, iclass 27, count 0 2006.201.06:45:41.97#ibcon#about to read 6, iclass 27, count 0 2006.201.06:45:41.97#ibcon#read 6, iclass 27, count 0 2006.201.06:45:41.97#ibcon#end of sib2, iclass 27, count 0 2006.201.06:45:41.97#ibcon#*mode == 0, iclass 27, count 0 2006.201.06:45:41.97#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.06:45:41.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.06:45:41.97#ibcon#*before write, iclass 27, count 0 2006.201.06:45:41.97#ibcon#enter sib2, iclass 27, count 0 2006.201.06:45:41.97#ibcon#flushed, iclass 27, count 0 2006.201.06:45:41.97#ibcon#about to write, iclass 27, count 0 2006.201.06:45:41.97#ibcon#wrote, iclass 27, count 0 2006.201.06:45:41.97#ibcon#about to read 3, iclass 27, count 0 2006.201.06:45:42.01#ibcon#read 3, iclass 27, count 0 2006.201.06:45:42.01#ibcon#about to read 4, iclass 27, count 0 2006.201.06:45:42.01#ibcon#read 4, iclass 27, count 0 2006.201.06:45:42.01#ibcon#about to read 5, iclass 27, count 0 2006.201.06:45:42.01#ibcon#read 5, iclass 27, count 0 2006.201.06:45:42.01#ibcon#about to read 6, iclass 27, count 0 2006.201.06:45:42.01#ibcon#read 6, iclass 27, count 0 2006.201.06:45:42.01#ibcon#end of sib2, iclass 27, count 0 2006.201.06:45:42.01#ibcon#*after write, iclass 27, count 0 2006.201.06:45:42.01#ibcon#*before return 0, iclass 27, count 0 2006.201.06:45:42.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:42.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.06:45:42.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.06:45:42.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.06:45:42.01$vck44/vb=8,4 2006.201.06:45:42.01#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.06:45:42.01#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.06:45:42.01#ibcon#ireg 11 cls_cnt 2 2006.201.06:45:42.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:42.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:42.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:42.07#ibcon#enter wrdev, iclass 29, count 2 2006.201.06:45:42.07#ibcon#first serial, iclass 29, count 2 2006.201.06:45:42.07#ibcon#enter sib2, iclass 29, count 2 2006.201.06:45:42.07#ibcon#flushed, iclass 29, count 2 2006.201.06:45:42.07#ibcon#about to write, iclass 29, count 2 2006.201.06:45:42.07#ibcon#wrote, iclass 29, count 2 2006.201.06:45:42.07#ibcon#about to read 3, iclass 29, count 2 2006.201.06:45:42.09#ibcon#read 3, iclass 29, count 2 2006.201.06:45:42.09#ibcon#about to read 4, iclass 29, count 2 2006.201.06:45:42.09#ibcon#read 4, iclass 29, count 2 2006.201.06:45:42.09#ibcon#about to read 5, iclass 29, count 2 2006.201.06:45:42.09#ibcon#read 5, iclass 29, count 2 2006.201.06:45:42.09#ibcon#about to read 6, iclass 29, count 2 2006.201.06:45:42.09#ibcon#read 6, iclass 29, count 2 2006.201.06:45:42.09#ibcon#end of sib2, iclass 29, count 2 2006.201.06:45:42.09#ibcon#*mode == 0, iclass 29, count 2 2006.201.06:45:42.09#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.06:45:42.09#ibcon#[27=AT08-04\r\n] 2006.201.06:45:42.09#ibcon#*before write, iclass 29, count 2 2006.201.06:45:42.09#ibcon#enter sib2, iclass 29, count 2 2006.201.06:45:42.09#ibcon#flushed, iclass 29, count 2 2006.201.06:45:42.09#ibcon#about to write, iclass 29, count 2 2006.201.06:45:42.09#ibcon#wrote, iclass 29, count 2 2006.201.06:45:42.09#ibcon#about to read 3, iclass 29, count 2 2006.201.06:45:42.12#ibcon#read 3, iclass 29, count 2 2006.201.06:45:42.12#ibcon#about to read 4, iclass 29, count 2 2006.201.06:45:42.12#ibcon#read 4, iclass 29, count 2 2006.201.06:45:42.12#ibcon#about to read 5, iclass 29, count 2 2006.201.06:45:42.12#ibcon#read 5, iclass 29, count 2 2006.201.06:45:42.12#ibcon#about to read 6, iclass 29, count 2 2006.201.06:45:42.12#ibcon#read 6, iclass 29, count 2 2006.201.06:45:42.12#ibcon#end of sib2, iclass 29, count 2 2006.201.06:45:42.12#ibcon#*after write, iclass 29, count 2 2006.201.06:45:42.12#ibcon#*before return 0, iclass 29, count 2 2006.201.06:45:42.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:42.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.06:45:42.12#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.06:45:42.12#ibcon#ireg 7 cls_cnt 0 2006.201.06:45:42.12#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:42.24#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:42.24#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:42.24#ibcon#enter wrdev, iclass 29, count 0 2006.201.06:45:42.24#ibcon#first serial, iclass 29, count 0 2006.201.06:45:42.24#ibcon#enter sib2, iclass 29, count 0 2006.201.06:45:42.24#ibcon#flushed, iclass 29, count 0 2006.201.06:45:42.24#ibcon#about to write, iclass 29, count 0 2006.201.06:45:42.24#ibcon#wrote, iclass 29, count 0 2006.201.06:45:42.24#ibcon#about to read 3, iclass 29, count 0 2006.201.06:45:42.26#ibcon#read 3, iclass 29, count 0 2006.201.06:45:42.26#ibcon#about to read 4, iclass 29, count 0 2006.201.06:45:42.26#ibcon#read 4, iclass 29, count 0 2006.201.06:45:42.26#ibcon#about to read 5, iclass 29, count 0 2006.201.06:45:42.26#ibcon#read 5, iclass 29, count 0 2006.201.06:45:42.26#ibcon#about to read 6, iclass 29, count 0 2006.201.06:45:42.26#ibcon#read 6, iclass 29, count 0 2006.201.06:45:42.26#ibcon#end of sib2, iclass 29, count 0 2006.201.06:45:42.26#ibcon#*mode == 0, iclass 29, count 0 2006.201.06:45:42.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.06:45:42.26#ibcon#[27=USB\r\n] 2006.201.06:45:42.26#ibcon#*before write, iclass 29, count 0 2006.201.06:45:42.26#ibcon#enter sib2, iclass 29, count 0 2006.201.06:45:42.26#ibcon#flushed, iclass 29, count 0 2006.201.06:45:42.26#ibcon#about to write, iclass 29, count 0 2006.201.06:45:42.26#ibcon#wrote, iclass 29, count 0 2006.201.06:45:42.26#ibcon#about to read 3, iclass 29, count 0 2006.201.06:45:42.29#ibcon#read 3, iclass 29, count 0 2006.201.06:45:42.29#ibcon#about to read 4, iclass 29, count 0 2006.201.06:45:42.29#ibcon#read 4, iclass 29, count 0 2006.201.06:45:42.29#ibcon#about to read 5, iclass 29, count 0 2006.201.06:45:42.29#ibcon#read 5, iclass 29, count 0 2006.201.06:45:42.29#ibcon#about to read 6, iclass 29, count 0 2006.201.06:45:42.29#ibcon#read 6, iclass 29, count 0 2006.201.06:45:42.29#ibcon#end of sib2, iclass 29, count 0 2006.201.06:45:42.29#ibcon#*after write, iclass 29, count 0 2006.201.06:45:42.29#ibcon#*before return 0, iclass 29, count 0 2006.201.06:45:42.29#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:42.29#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.06:45:42.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.06:45:42.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.06:45:42.29$vck44/vabw=wide 2006.201.06:45:42.29#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.06:45:42.29#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.06:45:42.29#ibcon#ireg 8 cls_cnt 0 2006.201.06:45:42.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:42.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:42.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:42.29#ibcon#enter wrdev, iclass 31, count 0 2006.201.06:45:42.29#ibcon#first serial, iclass 31, count 0 2006.201.06:45:42.29#ibcon#enter sib2, iclass 31, count 0 2006.201.06:45:42.29#ibcon#flushed, iclass 31, count 0 2006.201.06:45:42.29#ibcon#about to write, iclass 31, count 0 2006.201.06:45:42.29#ibcon#wrote, iclass 31, count 0 2006.201.06:45:42.29#ibcon#about to read 3, iclass 31, count 0 2006.201.06:45:42.31#ibcon#read 3, iclass 31, count 0 2006.201.06:45:42.31#ibcon#about to read 4, iclass 31, count 0 2006.201.06:45:42.31#ibcon#read 4, iclass 31, count 0 2006.201.06:45:42.31#ibcon#about to read 5, iclass 31, count 0 2006.201.06:45:42.31#ibcon#read 5, iclass 31, count 0 2006.201.06:45:42.31#ibcon#about to read 6, iclass 31, count 0 2006.201.06:45:42.31#ibcon#read 6, iclass 31, count 0 2006.201.06:45:42.31#ibcon#end of sib2, iclass 31, count 0 2006.201.06:45:42.31#ibcon#*mode == 0, iclass 31, count 0 2006.201.06:45:42.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.06:45:42.31#ibcon#[25=BW32\r\n] 2006.201.06:45:42.31#ibcon#*before write, iclass 31, count 0 2006.201.06:45:42.31#ibcon#enter sib2, iclass 31, count 0 2006.201.06:45:42.31#ibcon#flushed, iclass 31, count 0 2006.201.06:45:42.31#ibcon#about to write, iclass 31, count 0 2006.201.06:45:42.31#ibcon#wrote, iclass 31, count 0 2006.201.06:45:42.31#ibcon#about to read 3, iclass 31, count 0 2006.201.06:45:42.35#ibcon#read 3, iclass 31, count 0 2006.201.06:45:42.35#ibcon#about to read 4, iclass 31, count 0 2006.201.06:45:42.35#ibcon#read 4, iclass 31, count 0 2006.201.06:45:42.35#ibcon#about to read 5, iclass 31, count 0 2006.201.06:45:42.35#ibcon#read 5, iclass 31, count 0 2006.201.06:45:42.35#ibcon#about to read 6, iclass 31, count 0 2006.201.06:45:42.35#ibcon#read 6, iclass 31, count 0 2006.201.06:45:42.35#ibcon#end of sib2, iclass 31, count 0 2006.201.06:45:42.35#ibcon#*after write, iclass 31, count 0 2006.201.06:45:42.35#ibcon#*before return 0, iclass 31, count 0 2006.201.06:45:42.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:42.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.06:45:42.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.06:45:42.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.06:45:42.35$vck44/vbbw=wide 2006.201.06:45:42.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.06:45:42.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.06:45:42.35#ibcon#ireg 8 cls_cnt 0 2006.201.06:45:42.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:45:42.41#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:45:42.41#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:45:42.41#ibcon#enter wrdev, iclass 33, count 0 2006.201.06:45:42.41#ibcon#first serial, iclass 33, count 0 2006.201.06:45:42.41#ibcon#enter sib2, iclass 33, count 0 2006.201.06:45:42.41#ibcon#flushed, iclass 33, count 0 2006.201.06:45:42.41#ibcon#about to write, iclass 33, count 0 2006.201.06:45:42.41#ibcon#wrote, iclass 33, count 0 2006.201.06:45:42.41#ibcon#about to read 3, iclass 33, count 0 2006.201.06:45:42.43#ibcon#read 3, iclass 33, count 0 2006.201.06:45:42.43#ibcon#about to read 4, iclass 33, count 0 2006.201.06:45:42.43#ibcon#read 4, iclass 33, count 0 2006.201.06:45:42.43#ibcon#about to read 5, iclass 33, count 0 2006.201.06:45:42.43#ibcon#read 5, iclass 33, count 0 2006.201.06:45:42.43#ibcon#about to read 6, iclass 33, count 0 2006.201.06:45:42.43#ibcon#read 6, iclass 33, count 0 2006.201.06:45:42.43#ibcon#end of sib2, iclass 33, count 0 2006.201.06:45:42.43#ibcon#*mode == 0, iclass 33, count 0 2006.201.06:45:42.43#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.06:45:42.43#ibcon#[27=BW32\r\n] 2006.201.06:45:42.43#ibcon#*before write, iclass 33, count 0 2006.201.06:45:42.43#ibcon#enter sib2, iclass 33, count 0 2006.201.06:45:42.43#ibcon#flushed, iclass 33, count 0 2006.201.06:45:42.43#ibcon#about to write, iclass 33, count 0 2006.201.06:45:42.43#ibcon#wrote, iclass 33, count 0 2006.201.06:45:42.43#ibcon#about to read 3, iclass 33, count 0 2006.201.06:45:42.46#ibcon#read 3, iclass 33, count 0 2006.201.06:45:42.46#ibcon#about to read 4, iclass 33, count 0 2006.201.06:45:42.46#ibcon#read 4, iclass 33, count 0 2006.201.06:45:42.46#ibcon#about to read 5, iclass 33, count 0 2006.201.06:45:42.46#ibcon#read 5, iclass 33, count 0 2006.201.06:45:42.46#ibcon#about to read 6, iclass 33, count 0 2006.201.06:45:42.46#ibcon#read 6, iclass 33, count 0 2006.201.06:45:42.46#ibcon#end of sib2, iclass 33, count 0 2006.201.06:45:42.46#ibcon#*after write, iclass 33, count 0 2006.201.06:45:42.46#ibcon#*before return 0, iclass 33, count 0 2006.201.06:45:42.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:45:42.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:45:42.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.06:45:42.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.06:45:42.46$setupk4/ifdk4 2006.201.06:45:42.46$ifdk4/lo= 2006.201.06:45:42.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.06:45:42.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.06:45:42.46$ifdk4/patch= 2006.201.06:45:42.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.06:45:42.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.06:45:42.46$setupk4/!*+20s 2006.201.06:45:43.14#abcon#<5=/05 2.8 4.5 23.17 891003.2\r\n> 2006.201.06:45:43.16#abcon#{5=INTERFACE CLEAR} 2006.201.06:45:43.22#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:45:51.13#trakl#Source acquired 2006.201.06:45:53.13#flagr#flagr/antenna,acquired 2006.201.06:45:53.31#abcon#<5=/05 2.8 4.5 23.17 891003.2\r\n> 2006.201.06:45:53.33#abcon#{5=INTERFACE CLEAR} 2006.201.06:45:53.39#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:45:56.91$setupk4/"tpicd 2006.201.06:45:56.91$setupk4/echo=off 2006.201.06:45:56.91$setupk4/xlog=off 2006.201.06:45:56.91:!2006.201.06:47:03 2006.201.06:47:03.00:preob 2006.201.06:47:03.14/onsource/TRACKING 2006.201.06:47:03.14:!2006.201.06:47:13 2006.201.06:47:13.00:"tape 2006.201.06:47:13.00:"st=record 2006.201.06:47:13.00:data_valid=on 2006.201.06:47:13.00:midob 2006.201.06:47:14.14/onsource/TRACKING 2006.201.06:47:14.14/wx/23.18,1003.2,88 2006.201.06:47:14.35/cable/+6.4684E-03 2006.201.06:47:15.44/va/01,08,usb,yes,30,33 2006.201.06:47:15.44/va/02,07,usb,yes,33,34 2006.201.06:47:15.44/va/03,08,usb,yes,30,31 2006.201.06:47:15.44/va/04,07,usb,yes,34,36 2006.201.06:47:15.44/va/05,04,usb,yes,30,30 2006.201.06:47:15.44/va/06,05,usb,yes,30,30 2006.201.06:47:15.44/va/07,05,usb,yes,29,30 2006.201.06:47:15.44/va/08,04,usb,yes,28,34 2006.201.06:47:15.67/valo/01,524.99,yes,locked 2006.201.06:47:15.67/valo/02,534.99,yes,locked 2006.201.06:47:15.67/valo/03,564.99,yes,locked 2006.201.06:47:15.67/valo/04,624.99,yes,locked 2006.201.06:47:15.67/valo/05,734.99,yes,locked 2006.201.06:47:15.67/valo/06,814.99,yes,locked 2006.201.06:47:15.67/valo/07,864.99,yes,locked 2006.201.06:47:15.67/valo/08,884.99,yes,locked 2006.201.06:47:16.76/vb/01,04,usb,yes,36,33 2006.201.06:47:16.76/vb/02,05,usb,yes,34,34 2006.201.06:47:16.76/vb/03,04,usb,yes,35,38 2006.201.06:47:16.76/vb/04,05,usb,yes,35,34 2006.201.06:47:16.76/vb/05,04,usb,yes,31,34 2006.201.06:47:16.76/vb/06,04,usb,yes,36,32 2006.201.06:47:16.76/vb/07,04,usb,yes,35,36 2006.201.06:47:16.76/vb/08,04,usb,yes,32,36 2006.201.06:47:17.00/vblo/01,629.99,yes,locked 2006.201.06:47:17.00/vblo/02,634.99,yes,locked 2006.201.06:47:17.00/vblo/03,649.99,yes,locked 2006.201.06:47:17.00/vblo/04,679.99,yes,locked 2006.201.06:47:17.00/vblo/05,709.99,yes,locked 2006.201.06:47:17.00/vblo/06,719.99,yes,locked 2006.201.06:47:17.00/vblo/07,734.99,yes,locked 2006.201.06:47:17.00/vblo/08,744.99,yes,locked 2006.201.06:47:17.15/vabw/8 2006.201.06:47:17.30/vbbw/8 2006.201.06:47:17.39/xfe/off,on,15.2 2006.201.06:47:17.78/ifatt/23,28,28,28 2006.201.06:47:18.05/fmout-gps/S +4.53E-07 2006.201.06:47:18.12:!2006.201.06:48:43 2006.201.06:48:43.00:data_valid=off 2006.201.06:48:43.00:"et 2006.201.06:48:43.00:!+3s 2006.201.06:48:46.02:"tape 2006.201.06:48:46.02:postob 2006.201.06:48:46.15/cable/+6.4686E-03 2006.201.06:48:46.15/wx/23.19,1003.2,90 2006.201.06:48:46.21/fmout-gps/S +4.53E-07 2006.201.06:48:46.21:scan_name=201-0655,jd0607,130 2006.201.06:48:46.21:source=1749+096,175132.82,093900.7,2000.0,cw 2006.201.06:48:47.14#flagr#flagr/antenna,new-source 2006.201.06:48:47.14:checkk5 2006.201.06:48:47.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.06:48:47.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.06:48:48.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.06:48:48.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.06:48:48.99/chk_obsdata//k5ts1/T2010647??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.06:48:49.37/chk_obsdata//k5ts2/T2010647??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.06:48:49.74/chk_obsdata//k5ts3/T2010647??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.06:48:50.10/chk_obsdata//k5ts4/T2010647??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.06:48:50.79/k5log//k5ts1_log_newline 2006.201.06:48:51.47/k5log//k5ts2_log_newline 2006.201.06:48:52.17/k5log//k5ts3_log_newline 2006.201.06:48:52.85/k5log//k5ts4_log_newline 2006.201.06:48:52.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.06:48:52.87:setupk4=1 2006.201.06:48:52.87$setupk4/echo=on 2006.201.06:48:52.87$setupk4/pcalon 2006.201.06:48:52.87$pcalon/"no phase cal control is implemented here 2006.201.06:48:52.87$setupk4/"tpicd=stop 2006.201.06:48:52.87$setupk4/"rec=synch_on 2006.201.06:48:52.87$setupk4/"rec_mode=128 2006.201.06:48:52.87$setupk4/!* 2006.201.06:48:52.87$setupk4/recpk4 2006.201.06:48:52.87$recpk4/recpatch= 2006.201.06:48:52.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.06:48:52.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.06:48:52.88$setupk4/vck44 2006.201.06:48:52.88$vck44/valo=1,524.99 2006.201.06:48:52.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.06:48:52.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.06:48:52.88#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:52.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:52.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:52.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:52.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.06:48:52.88#ibcon#first serial, iclass 4, count 0 2006.201.06:48:52.88#ibcon#enter sib2, iclass 4, count 0 2006.201.06:48:52.88#ibcon#flushed, iclass 4, count 0 2006.201.06:48:52.88#ibcon#about to write, iclass 4, count 0 2006.201.06:48:52.88#ibcon#wrote, iclass 4, count 0 2006.201.06:48:52.88#ibcon#about to read 3, iclass 4, count 0 2006.201.06:48:52.92#ibcon#read 3, iclass 4, count 0 2006.201.06:48:52.92#ibcon#about to read 4, iclass 4, count 0 2006.201.06:48:52.92#ibcon#read 4, iclass 4, count 0 2006.201.06:48:52.92#ibcon#about to read 5, iclass 4, count 0 2006.201.06:48:52.92#ibcon#read 5, iclass 4, count 0 2006.201.06:48:52.92#ibcon#about to read 6, iclass 4, count 0 2006.201.06:48:52.92#ibcon#read 6, iclass 4, count 0 2006.201.06:48:52.92#ibcon#end of sib2, iclass 4, count 0 2006.201.06:48:52.92#ibcon#*mode == 0, iclass 4, count 0 2006.201.06:48:52.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.06:48:52.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.06:48:52.92#ibcon#*before write, iclass 4, count 0 2006.201.06:48:52.92#ibcon#enter sib2, iclass 4, count 0 2006.201.06:48:52.92#ibcon#flushed, iclass 4, count 0 2006.201.06:48:52.92#ibcon#about to write, iclass 4, count 0 2006.201.06:48:52.92#ibcon#wrote, iclass 4, count 0 2006.201.06:48:52.92#ibcon#about to read 3, iclass 4, count 0 2006.201.06:48:52.97#ibcon#read 3, iclass 4, count 0 2006.201.06:48:52.97#ibcon#about to read 4, iclass 4, count 0 2006.201.06:48:52.97#ibcon#read 4, iclass 4, count 0 2006.201.06:48:52.97#ibcon#about to read 5, iclass 4, count 0 2006.201.06:48:52.97#ibcon#read 5, iclass 4, count 0 2006.201.06:48:52.97#ibcon#about to read 6, iclass 4, count 0 2006.201.06:48:52.97#ibcon#read 6, iclass 4, count 0 2006.201.06:48:52.97#ibcon#end of sib2, iclass 4, count 0 2006.201.06:48:52.97#ibcon#*after write, iclass 4, count 0 2006.201.06:48:52.97#ibcon#*before return 0, iclass 4, count 0 2006.201.06:48:52.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:52.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:52.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.06:48:52.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.06:48:52.97$vck44/va=1,8 2006.201.06:48:52.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.06:48:52.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.06:48:52.97#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:52.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:52.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:52.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:52.97#ibcon#enter wrdev, iclass 6, count 2 2006.201.06:48:52.97#ibcon#first serial, iclass 6, count 2 2006.201.06:48:52.97#ibcon#enter sib2, iclass 6, count 2 2006.201.06:48:52.97#ibcon#flushed, iclass 6, count 2 2006.201.06:48:52.97#ibcon#about to write, iclass 6, count 2 2006.201.06:48:52.97#ibcon#wrote, iclass 6, count 2 2006.201.06:48:52.97#ibcon#about to read 3, iclass 6, count 2 2006.201.06:48:52.99#ibcon#read 3, iclass 6, count 2 2006.201.06:48:52.99#ibcon#about to read 4, iclass 6, count 2 2006.201.06:48:52.99#ibcon#read 4, iclass 6, count 2 2006.201.06:48:52.99#ibcon#about to read 5, iclass 6, count 2 2006.201.06:48:52.99#ibcon#read 5, iclass 6, count 2 2006.201.06:48:52.99#ibcon#about to read 6, iclass 6, count 2 2006.201.06:48:52.99#ibcon#read 6, iclass 6, count 2 2006.201.06:48:52.99#ibcon#end of sib2, iclass 6, count 2 2006.201.06:48:52.99#ibcon#*mode == 0, iclass 6, count 2 2006.201.06:48:52.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.06:48:52.99#ibcon#[25=AT01-08\r\n] 2006.201.06:48:52.99#ibcon#*before write, iclass 6, count 2 2006.201.06:48:52.99#ibcon#enter sib2, iclass 6, count 2 2006.201.06:48:52.99#ibcon#flushed, iclass 6, count 2 2006.201.06:48:52.99#ibcon#about to write, iclass 6, count 2 2006.201.06:48:52.99#ibcon#wrote, iclass 6, count 2 2006.201.06:48:52.99#ibcon#about to read 3, iclass 6, count 2 2006.201.06:48:53.03#ibcon#read 3, iclass 6, count 2 2006.201.06:48:53.03#ibcon#about to read 4, iclass 6, count 2 2006.201.06:48:53.03#ibcon#read 4, iclass 6, count 2 2006.201.06:48:53.03#ibcon#about to read 5, iclass 6, count 2 2006.201.06:48:53.03#ibcon#read 5, iclass 6, count 2 2006.201.06:48:53.03#ibcon#about to read 6, iclass 6, count 2 2006.201.06:48:53.03#ibcon#read 6, iclass 6, count 2 2006.201.06:48:53.03#ibcon#end of sib2, iclass 6, count 2 2006.201.06:48:53.03#ibcon#*after write, iclass 6, count 2 2006.201.06:48:53.03#ibcon#*before return 0, iclass 6, count 2 2006.201.06:48:53.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:53.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:53.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.06:48:53.03#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:53.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:53.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:53.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:53.15#ibcon#enter wrdev, iclass 6, count 0 2006.201.06:48:53.15#ibcon#first serial, iclass 6, count 0 2006.201.06:48:53.15#ibcon#enter sib2, iclass 6, count 0 2006.201.06:48:53.15#ibcon#flushed, iclass 6, count 0 2006.201.06:48:53.15#ibcon#about to write, iclass 6, count 0 2006.201.06:48:53.15#ibcon#wrote, iclass 6, count 0 2006.201.06:48:53.15#ibcon#about to read 3, iclass 6, count 0 2006.201.06:48:53.17#ibcon#read 3, iclass 6, count 0 2006.201.06:48:53.17#ibcon#about to read 4, iclass 6, count 0 2006.201.06:48:53.17#ibcon#read 4, iclass 6, count 0 2006.201.06:48:53.17#ibcon#about to read 5, iclass 6, count 0 2006.201.06:48:53.17#ibcon#read 5, iclass 6, count 0 2006.201.06:48:53.17#ibcon#about to read 6, iclass 6, count 0 2006.201.06:48:53.17#ibcon#read 6, iclass 6, count 0 2006.201.06:48:53.17#ibcon#end of sib2, iclass 6, count 0 2006.201.06:48:53.17#ibcon#*mode == 0, iclass 6, count 0 2006.201.06:48:53.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.06:48:53.17#ibcon#[25=USB\r\n] 2006.201.06:48:53.17#ibcon#*before write, iclass 6, count 0 2006.201.06:48:53.17#ibcon#enter sib2, iclass 6, count 0 2006.201.06:48:53.17#ibcon#flushed, iclass 6, count 0 2006.201.06:48:53.17#ibcon#about to write, iclass 6, count 0 2006.201.06:48:53.17#ibcon#wrote, iclass 6, count 0 2006.201.06:48:53.17#ibcon#about to read 3, iclass 6, count 0 2006.201.06:48:53.20#ibcon#read 3, iclass 6, count 0 2006.201.06:48:53.20#ibcon#about to read 4, iclass 6, count 0 2006.201.06:48:53.20#ibcon#read 4, iclass 6, count 0 2006.201.06:48:53.20#ibcon#about to read 5, iclass 6, count 0 2006.201.06:48:53.20#ibcon#read 5, iclass 6, count 0 2006.201.06:48:53.20#ibcon#about to read 6, iclass 6, count 0 2006.201.06:48:53.20#ibcon#read 6, iclass 6, count 0 2006.201.06:48:53.20#ibcon#end of sib2, iclass 6, count 0 2006.201.06:48:53.20#ibcon#*after write, iclass 6, count 0 2006.201.06:48:53.20#ibcon#*before return 0, iclass 6, count 0 2006.201.06:48:53.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:53.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:53.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.06:48:53.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.06:48:53.20$vck44/valo=2,534.99 2006.201.06:48:53.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.06:48:53.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.06:48:53.20#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:53.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:53.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:53.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:53.20#ibcon#enter wrdev, iclass 10, count 0 2006.201.06:48:53.20#ibcon#first serial, iclass 10, count 0 2006.201.06:48:53.20#ibcon#enter sib2, iclass 10, count 0 2006.201.06:48:53.20#ibcon#flushed, iclass 10, count 0 2006.201.06:48:53.20#ibcon#about to write, iclass 10, count 0 2006.201.06:48:53.20#ibcon#wrote, iclass 10, count 0 2006.201.06:48:53.20#ibcon#about to read 3, iclass 10, count 0 2006.201.06:48:53.22#ibcon#read 3, iclass 10, count 0 2006.201.06:48:53.22#ibcon#about to read 4, iclass 10, count 0 2006.201.06:48:53.22#ibcon#read 4, iclass 10, count 0 2006.201.06:48:53.22#ibcon#about to read 5, iclass 10, count 0 2006.201.06:48:53.22#ibcon#read 5, iclass 10, count 0 2006.201.06:48:53.22#ibcon#about to read 6, iclass 10, count 0 2006.201.06:48:53.22#ibcon#read 6, iclass 10, count 0 2006.201.06:48:53.22#ibcon#end of sib2, iclass 10, count 0 2006.201.06:48:53.22#ibcon#*mode == 0, iclass 10, count 0 2006.201.06:48:53.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.06:48:53.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.06:48:53.22#ibcon#*before write, iclass 10, count 0 2006.201.06:48:53.22#ibcon#enter sib2, iclass 10, count 0 2006.201.06:48:53.22#ibcon#flushed, iclass 10, count 0 2006.201.06:48:53.22#ibcon#about to write, iclass 10, count 0 2006.201.06:48:53.22#ibcon#wrote, iclass 10, count 0 2006.201.06:48:53.22#ibcon#about to read 3, iclass 10, count 0 2006.201.06:48:53.26#ibcon#read 3, iclass 10, count 0 2006.201.06:48:53.26#ibcon#about to read 4, iclass 10, count 0 2006.201.06:48:53.26#ibcon#read 4, iclass 10, count 0 2006.201.06:48:53.26#ibcon#about to read 5, iclass 10, count 0 2006.201.06:48:53.26#ibcon#read 5, iclass 10, count 0 2006.201.06:48:53.26#ibcon#about to read 6, iclass 10, count 0 2006.201.06:48:53.26#ibcon#read 6, iclass 10, count 0 2006.201.06:48:53.26#ibcon#end of sib2, iclass 10, count 0 2006.201.06:48:53.26#ibcon#*after write, iclass 10, count 0 2006.201.06:48:53.26#ibcon#*before return 0, iclass 10, count 0 2006.201.06:48:53.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:53.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:53.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.06:48:53.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.06:48:53.26$vck44/va=2,7 2006.201.06:48:53.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.06:48:53.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.06:48:53.26#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:53.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:53.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:53.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:53.32#ibcon#enter wrdev, iclass 12, count 2 2006.201.06:48:53.32#ibcon#first serial, iclass 12, count 2 2006.201.06:48:53.32#ibcon#enter sib2, iclass 12, count 2 2006.201.06:48:53.32#ibcon#flushed, iclass 12, count 2 2006.201.06:48:53.32#ibcon#about to write, iclass 12, count 2 2006.201.06:48:53.32#ibcon#wrote, iclass 12, count 2 2006.201.06:48:53.32#ibcon#about to read 3, iclass 12, count 2 2006.201.06:48:53.34#ibcon#read 3, iclass 12, count 2 2006.201.06:48:53.34#ibcon#about to read 4, iclass 12, count 2 2006.201.06:48:53.34#ibcon#read 4, iclass 12, count 2 2006.201.06:48:53.34#ibcon#about to read 5, iclass 12, count 2 2006.201.06:48:53.34#ibcon#read 5, iclass 12, count 2 2006.201.06:48:53.34#ibcon#about to read 6, iclass 12, count 2 2006.201.06:48:53.34#ibcon#read 6, iclass 12, count 2 2006.201.06:48:53.34#ibcon#end of sib2, iclass 12, count 2 2006.201.06:48:53.34#ibcon#*mode == 0, iclass 12, count 2 2006.201.06:48:53.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.06:48:53.34#ibcon#[25=AT02-07\r\n] 2006.201.06:48:53.34#ibcon#*before write, iclass 12, count 2 2006.201.06:48:53.34#ibcon#enter sib2, iclass 12, count 2 2006.201.06:48:53.34#ibcon#flushed, iclass 12, count 2 2006.201.06:48:53.34#ibcon#about to write, iclass 12, count 2 2006.201.06:48:53.34#ibcon#wrote, iclass 12, count 2 2006.201.06:48:53.34#ibcon#about to read 3, iclass 12, count 2 2006.201.06:48:53.37#ibcon#read 3, iclass 12, count 2 2006.201.06:48:53.37#ibcon#about to read 4, iclass 12, count 2 2006.201.06:48:53.37#ibcon#read 4, iclass 12, count 2 2006.201.06:48:53.37#ibcon#about to read 5, iclass 12, count 2 2006.201.06:48:53.37#ibcon#read 5, iclass 12, count 2 2006.201.06:48:53.37#ibcon#about to read 6, iclass 12, count 2 2006.201.06:48:53.37#ibcon#read 6, iclass 12, count 2 2006.201.06:48:53.37#ibcon#end of sib2, iclass 12, count 2 2006.201.06:48:53.37#ibcon#*after write, iclass 12, count 2 2006.201.06:48:53.37#ibcon#*before return 0, iclass 12, count 2 2006.201.06:48:53.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:53.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:53.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.06:48:53.37#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:53.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:53.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:53.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:53.49#ibcon#enter wrdev, iclass 12, count 0 2006.201.06:48:53.49#ibcon#first serial, iclass 12, count 0 2006.201.06:48:53.49#ibcon#enter sib2, iclass 12, count 0 2006.201.06:48:53.49#ibcon#flushed, iclass 12, count 0 2006.201.06:48:53.49#ibcon#about to write, iclass 12, count 0 2006.201.06:48:53.49#ibcon#wrote, iclass 12, count 0 2006.201.06:48:53.49#ibcon#about to read 3, iclass 12, count 0 2006.201.06:48:53.51#ibcon#read 3, iclass 12, count 0 2006.201.06:48:53.51#ibcon#about to read 4, iclass 12, count 0 2006.201.06:48:53.51#ibcon#read 4, iclass 12, count 0 2006.201.06:48:53.51#ibcon#about to read 5, iclass 12, count 0 2006.201.06:48:53.51#ibcon#read 5, iclass 12, count 0 2006.201.06:48:53.51#ibcon#about to read 6, iclass 12, count 0 2006.201.06:48:53.51#ibcon#read 6, iclass 12, count 0 2006.201.06:48:53.51#ibcon#end of sib2, iclass 12, count 0 2006.201.06:48:53.51#ibcon#*mode == 0, iclass 12, count 0 2006.201.06:48:53.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.06:48:53.51#ibcon#[25=USB\r\n] 2006.201.06:48:53.51#ibcon#*before write, iclass 12, count 0 2006.201.06:48:53.51#ibcon#enter sib2, iclass 12, count 0 2006.201.06:48:53.51#ibcon#flushed, iclass 12, count 0 2006.201.06:48:53.51#ibcon#about to write, iclass 12, count 0 2006.201.06:48:53.51#ibcon#wrote, iclass 12, count 0 2006.201.06:48:53.51#ibcon#about to read 3, iclass 12, count 0 2006.201.06:48:53.54#ibcon#read 3, iclass 12, count 0 2006.201.06:48:53.54#ibcon#about to read 4, iclass 12, count 0 2006.201.06:48:53.54#ibcon#read 4, iclass 12, count 0 2006.201.06:48:53.54#ibcon#about to read 5, iclass 12, count 0 2006.201.06:48:53.54#ibcon#read 5, iclass 12, count 0 2006.201.06:48:53.54#ibcon#about to read 6, iclass 12, count 0 2006.201.06:48:53.54#ibcon#read 6, iclass 12, count 0 2006.201.06:48:53.54#ibcon#end of sib2, iclass 12, count 0 2006.201.06:48:53.54#ibcon#*after write, iclass 12, count 0 2006.201.06:48:53.54#ibcon#*before return 0, iclass 12, count 0 2006.201.06:48:53.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:53.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:53.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.06:48:53.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.06:48:53.54$vck44/valo=3,564.99 2006.201.06:48:53.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.06:48:53.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.06:48:53.54#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:53.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.06:48:53.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.06:48:53.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.06:48:53.54#ibcon#enter wrdev, iclass 14, count 0 2006.201.06:48:53.54#ibcon#first serial, iclass 14, count 0 2006.201.06:48:53.54#ibcon#enter sib2, iclass 14, count 0 2006.201.06:48:53.54#ibcon#flushed, iclass 14, count 0 2006.201.06:48:53.54#ibcon#about to write, iclass 14, count 0 2006.201.06:48:53.54#ibcon#wrote, iclass 14, count 0 2006.201.06:48:53.54#ibcon#about to read 3, iclass 14, count 0 2006.201.06:48:53.56#ibcon#read 3, iclass 14, count 0 2006.201.06:48:53.56#ibcon#about to read 4, iclass 14, count 0 2006.201.06:48:53.56#ibcon#read 4, iclass 14, count 0 2006.201.06:48:53.56#ibcon#about to read 5, iclass 14, count 0 2006.201.06:48:53.56#ibcon#read 5, iclass 14, count 0 2006.201.06:48:53.56#ibcon#about to read 6, iclass 14, count 0 2006.201.06:48:53.56#ibcon#read 6, iclass 14, count 0 2006.201.06:48:53.56#ibcon#end of sib2, iclass 14, count 0 2006.201.06:48:53.56#ibcon#*mode == 0, iclass 14, count 0 2006.201.06:48:53.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.06:48:53.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.06:48:53.56#ibcon#*before write, iclass 14, count 0 2006.201.06:48:53.56#ibcon#enter sib2, iclass 14, count 0 2006.201.06:48:53.56#ibcon#flushed, iclass 14, count 0 2006.201.06:48:53.56#ibcon#about to write, iclass 14, count 0 2006.201.06:48:53.56#ibcon#wrote, iclass 14, count 0 2006.201.06:48:53.56#ibcon#about to read 3, iclass 14, count 0 2006.201.06:48:53.61#ibcon#read 3, iclass 14, count 0 2006.201.06:48:53.61#ibcon#about to read 4, iclass 14, count 0 2006.201.06:48:53.61#ibcon#read 4, iclass 14, count 0 2006.201.06:48:53.61#ibcon#about to read 5, iclass 14, count 0 2006.201.06:48:53.61#ibcon#read 5, iclass 14, count 0 2006.201.06:48:53.61#ibcon#about to read 6, iclass 14, count 0 2006.201.06:48:53.61#ibcon#read 6, iclass 14, count 0 2006.201.06:48:53.61#ibcon#end of sib2, iclass 14, count 0 2006.201.06:48:53.61#ibcon#*after write, iclass 14, count 0 2006.201.06:48:53.61#ibcon#*before return 0, iclass 14, count 0 2006.201.06:48:53.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.06:48:53.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.06:48:53.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.06:48:53.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.06:48:53.61$vck44/va=3,8 2006.201.06:48:53.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.06:48:53.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.06:48:53.61#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:53.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.06:48:53.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.06:48:53.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.06:48:53.66#ibcon#enter wrdev, iclass 16, count 2 2006.201.06:48:53.66#ibcon#first serial, iclass 16, count 2 2006.201.06:48:53.66#ibcon#enter sib2, iclass 16, count 2 2006.201.06:48:53.66#ibcon#flushed, iclass 16, count 2 2006.201.06:48:53.66#ibcon#about to write, iclass 16, count 2 2006.201.06:48:53.66#ibcon#wrote, iclass 16, count 2 2006.201.06:48:53.66#ibcon#about to read 3, iclass 16, count 2 2006.201.06:48:53.68#ibcon#read 3, iclass 16, count 2 2006.201.06:48:53.68#ibcon#about to read 4, iclass 16, count 2 2006.201.06:48:53.68#ibcon#read 4, iclass 16, count 2 2006.201.06:48:53.68#ibcon#about to read 5, iclass 16, count 2 2006.201.06:48:53.68#ibcon#read 5, iclass 16, count 2 2006.201.06:48:53.68#ibcon#about to read 6, iclass 16, count 2 2006.201.06:48:53.68#ibcon#read 6, iclass 16, count 2 2006.201.06:48:53.68#ibcon#end of sib2, iclass 16, count 2 2006.201.06:48:53.68#ibcon#*mode == 0, iclass 16, count 2 2006.201.06:48:53.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.06:48:53.68#ibcon#[25=AT03-08\r\n] 2006.201.06:48:53.68#ibcon#*before write, iclass 16, count 2 2006.201.06:48:53.68#ibcon#enter sib2, iclass 16, count 2 2006.201.06:48:53.68#ibcon#flushed, iclass 16, count 2 2006.201.06:48:53.68#ibcon#about to write, iclass 16, count 2 2006.201.06:48:53.68#ibcon#wrote, iclass 16, count 2 2006.201.06:48:53.68#ibcon#about to read 3, iclass 16, count 2 2006.201.06:48:53.71#ibcon#read 3, iclass 16, count 2 2006.201.06:48:53.71#ibcon#about to read 4, iclass 16, count 2 2006.201.06:48:53.71#ibcon#read 4, iclass 16, count 2 2006.201.06:48:53.71#ibcon#about to read 5, iclass 16, count 2 2006.201.06:48:53.71#ibcon#read 5, iclass 16, count 2 2006.201.06:48:53.71#ibcon#about to read 6, iclass 16, count 2 2006.201.06:48:53.71#ibcon#read 6, iclass 16, count 2 2006.201.06:48:53.71#ibcon#end of sib2, iclass 16, count 2 2006.201.06:48:53.71#ibcon#*after write, iclass 16, count 2 2006.201.06:48:53.71#ibcon#*before return 0, iclass 16, count 2 2006.201.06:48:53.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.06:48:53.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.06:48:53.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.06:48:53.71#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:53.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.06:48:53.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.06:48:53.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.06:48:53.83#ibcon#enter wrdev, iclass 16, count 0 2006.201.06:48:53.83#ibcon#first serial, iclass 16, count 0 2006.201.06:48:53.83#ibcon#enter sib2, iclass 16, count 0 2006.201.06:48:53.83#ibcon#flushed, iclass 16, count 0 2006.201.06:48:53.83#ibcon#about to write, iclass 16, count 0 2006.201.06:48:53.83#ibcon#wrote, iclass 16, count 0 2006.201.06:48:53.83#ibcon#about to read 3, iclass 16, count 0 2006.201.06:48:53.85#ibcon#read 3, iclass 16, count 0 2006.201.06:48:53.85#ibcon#about to read 4, iclass 16, count 0 2006.201.06:48:53.85#ibcon#read 4, iclass 16, count 0 2006.201.06:48:53.85#ibcon#about to read 5, iclass 16, count 0 2006.201.06:48:53.85#ibcon#read 5, iclass 16, count 0 2006.201.06:48:53.85#ibcon#about to read 6, iclass 16, count 0 2006.201.06:48:53.85#ibcon#read 6, iclass 16, count 0 2006.201.06:48:53.85#ibcon#end of sib2, iclass 16, count 0 2006.201.06:48:53.85#ibcon#*mode == 0, iclass 16, count 0 2006.201.06:48:53.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.06:48:53.85#ibcon#[25=USB\r\n] 2006.201.06:48:53.85#ibcon#*before write, iclass 16, count 0 2006.201.06:48:53.85#ibcon#enter sib2, iclass 16, count 0 2006.201.06:48:53.85#ibcon#flushed, iclass 16, count 0 2006.201.06:48:53.85#ibcon#about to write, iclass 16, count 0 2006.201.06:48:53.85#ibcon#wrote, iclass 16, count 0 2006.201.06:48:53.85#ibcon#about to read 3, iclass 16, count 0 2006.201.06:48:53.88#ibcon#read 3, iclass 16, count 0 2006.201.06:48:53.88#ibcon#about to read 4, iclass 16, count 0 2006.201.06:48:53.88#ibcon#read 4, iclass 16, count 0 2006.201.06:48:53.88#ibcon#about to read 5, iclass 16, count 0 2006.201.06:48:53.88#ibcon#read 5, iclass 16, count 0 2006.201.06:48:53.88#ibcon#about to read 6, iclass 16, count 0 2006.201.06:48:53.88#ibcon#read 6, iclass 16, count 0 2006.201.06:48:53.88#ibcon#end of sib2, iclass 16, count 0 2006.201.06:48:53.88#ibcon#*after write, iclass 16, count 0 2006.201.06:48:53.88#ibcon#*before return 0, iclass 16, count 0 2006.201.06:48:53.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.06:48:53.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.06:48:53.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.06:48:53.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.06:48:53.88$vck44/valo=4,624.99 2006.201.06:48:53.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.06:48:53.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.06:48:53.88#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:53.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.06:48:53.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.06:48:53.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.06:48:53.88#ibcon#enter wrdev, iclass 18, count 0 2006.201.06:48:53.88#ibcon#first serial, iclass 18, count 0 2006.201.06:48:53.88#ibcon#enter sib2, iclass 18, count 0 2006.201.06:48:53.88#ibcon#flushed, iclass 18, count 0 2006.201.06:48:53.88#ibcon#about to write, iclass 18, count 0 2006.201.06:48:53.88#ibcon#wrote, iclass 18, count 0 2006.201.06:48:53.88#ibcon#about to read 3, iclass 18, count 0 2006.201.06:48:53.90#ibcon#read 3, iclass 18, count 0 2006.201.06:48:53.90#ibcon#about to read 4, iclass 18, count 0 2006.201.06:48:53.90#ibcon#read 4, iclass 18, count 0 2006.201.06:48:53.90#ibcon#about to read 5, iclass 18, count 0 2006.201.06:48:53.90#ibcon#read 5, iclass 18, count 0 2006.201.06:48:53.90#ibcon#about to read 6, iclass 18, count 0 2006.201.06:48:53.90#ibcon#read 6, iclass 18, count 0 2006.201.06:48:53.90#ibcon#end of sib2, iclass 18, count 0 2006.201.06:48:53.90#ibcon#*mode == 0, iclass 18, count 0 2006.201.06:48:53.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.06:48:53.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.06:48:53.90#ibcon#*before write, iclass 18, count 0 2006.201.06:48:53.90#ibcon#enter sib2, iclass 18, count 0 2006.201.06:48:53.90#ibcon#flushed, iclass 18, count 0 2006.201.06:48:53.90#ibcon#about to write, iclass 18, count 0 2006.201.06:48:53.90#ibcon#wrote, iclass 18, count 0 2006.201.06:48:53.90#ibcon#about to read 3, iclass 18, count 0 2006.201.06:48:53.94#ibcon#read 3, iclass 18, count 0 2006.201.06:48:53.94#ibcon#about to read 4, iclass 18, count 0 2006.201.06:48:53.94#ibcon#read 4, iclass 18, count 0 2006.201.06:48:53.94#ibcon#about to read 5, iclass 18, count 0 2006.201.06:48:53.94#ibcon#read 5, iclass 18, count 0 2006.201.06:48:53.94#ibcon#about to read 6, iclass 18, count 0 2006.201.06:48:53.94#ibcon#read 6, iclass 18, count 0 2006.201.06:48:53.94#ibcon#end of sib2, iclass 18, count 0 2006.201.06:48:53.94#ibcon#*after write, iclass 18, count 0 2006.201.06:48:53.94#ibcon#*before return 0, iclass 18, count 0 2006.201.06:48:53.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.06:48:53.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.06:48:53.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.06:48:53.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.06:48:53.94$vck44/va=4,7 2006.201.06:48:53.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.06:48:53.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.06:48:53.94#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:53.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.06:48:54.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.06:48:54.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.06:48:54.00#ibcon#enter wrdev, iclass 20, count 2 2006.201.06:48:54.00#ibcon#first serial, iclass 20, count 2 2006.201.06:48:54.00#ibcon#enter sib2, iclass 20, count 2 2006.201.06:48:54.00#ibcon#flushed, iclass 20, count 2 2006.201.06:48:54.00#ibcon#about to write, iclass 20, count 2 2006.201.06:48:54.00#ibcon#wrote, iclass 20, count 2 2006.201.06:48:54.00#ibcon#about to read 3, iclass 20, count 2 2006.201.06:48:54.02#ibcon#read 3, iclass 20, count 2 2006.201.06:48:54.02#ibcon#about to read 4, iclass 20, count 2 2006.201.06:48:54.02#ibcon#read 4, iclass 20, count 2 2006.201.06:48:54.02#ibcon#about to read 5, iclass 20, count 2 2006.201.06:48:54.02#ibcon#read 5, iclass 20, count 2 2006.201.06:48:54.02#ibcon#about to read 6, iclass 20, count 2 2006.201.06:48:54.02#ibcon#read 6, iclass 20, count 2 2006.201.06:48:54.02#ibcon#end of sib2, iclass 20, count 2 2006.201.06:48:54.02#ibcon#*mode == 0, iclass 20, count 2 2006.201.06:48:54.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.06:48:54.02#ibcon#[25=AT04-07\r\n] 2006.201.06:48:54.02#ibcon#*before write, iclass 20, count 2 2006.201.06:48:54.02#ibcon#enter sib2, iclass 20, count 2 2006.201.06:48:54.02#ibcon#flushed, iclass 20, count 2 2006.201.06:48:54.02#ibcon#about to write, iclass 20, count 2 2006.201.06:48:54.02#ibcon#wrote, iclass 20, count 2 2006.201.06:48:54.02#ibcon#about to read 3, iclass 20, count 2 2006.201.06:48:54.05#ibcon#read 3, iclass 20, count 2 2006.201.06:48:54.05#ibcon#about to read 4, iclass 20, count 2 2006.201.06:48:54.05#ibcon#read 4, iclass 20, count 2 2006.201.06:48:54.05#ibcon#about to read 5, iclass 20, count 2 2006.201.06:48:54.05#ibcon#read 5, iclass 20, count 2 2006.201.06:48:54.05#ibcon#about to read 6, iclass 20, count 2 2006.201.06:48:54.05#ibcon#read 6, iclass 20, count 2 2006.201.06:48:54.05#ibcon#end of sib2, iclass 20, count 2 2006.201.06:48:54.05#ibcon#*after write, iclass 20, count 2 2006.201.06:48:54.05#ibcon#*before return 0, iclass 20, count 2 2006.201.06:48:54.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.06:48:54.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.06:48:54.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.06:48:54.05#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:54.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.06:48:54.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.06:48:54.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.06:48:54.17#ibcon#enter wrdev, iclass 20, count 0 2006.201.06:48:54.17#ibcon#first serial, iclass 20, count 0 2006.201.06:48:54.17#ibcon#enter sib2, iclass 20, count 0 2006.201.06:48:54.17#ibcon#flushed, iclass 20, count 0 2006.201.06:48:54.17#ibcon#about to write, iclass 20, count 0 2006.201.06:48:54.17#ibcon#wrote, iclass 20, count 0 2006.201.06:48:54.17#ibcon#about to read 3, iclass 20, count 0 2006.201.06:48:54.19#ibcon#read 3, iclass 20, count 0 2006.201.06:48:54.19#ibcon#about to read 4, iclass 20, count 0 2006.201.06:48:54.19#ibcon#read 4, iclass 20, count 0 2006.201.06:48:54.19#ibcon#about to read 5, iclass 20, count 0 2006.201.06:48:54.19#ibcon#read 5, iclass 20, count 0 2006.201.06:48:54.19#ibcon#about to read 6, iclass 20, count 0 2006.201.06:48:54.19#ibcon#read 6, iclass 20, count 0 2006.201.06:48:54.19#ibcon#end of sib2, iclass 20, count 0 2006.201.06:48:54.19#ibcon#*mode == 0, iclass 20, count 0 2006.201.06:48:54.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.06:48:54.19#ibcon#[25=USB\r\n] 2006.201.06:48:54.19#ibcon#*before write, iclass 20, count 0 2006.201.06:48:54.19#ibcon#enter sib2, iclass 20, count 0 2006.201.06:48:54.19#ibcon#flushed, iclass 20, count 0 2006.201.06:48:54.19#ibcon#about to write, iclass 20, count 0 2006.201.06:48:54.19#ibcon#wrote, iclass 20, count 0 2006.201.06:48:54.19#ibcon#about to read 3, iclass 20, count 0 2006.201.06:48:54.22#ibcon#read 3, iclass 20, count 0 2006.201.06:48:54.22#ibcon#about to read 4, iclass 20, count 0 2006.201.06:48:54.22#ibcon#read 4, iclass 20, count 0 2006.201.06:48:54.22#ibcon#about to read 5, iclass 20, count 0 2006.201.06:48:54.22#ibcon#read 5, iclass 20, count 0 2006.201.06:48:54.22#ibcon#about to read 6, iclass 20, count 0 2006.201.06:48:54.22#ibcon#read 6, iclass 20, count 0 2006.201.06:48:54.22#ibcon#end of sib2, iclass 20, count 0 2006.201.06:48:54.22#ibcon#*after write, iclass 20, count 0 2006.201.06:48:54.22#ibcon#*before return 0, iclass 20, count 0 2006.201.06:48:54.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.06:48:54.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.06:48:54.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.06:48:54.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.06:48:54.22$vck44/valo=5,734.99 2006.201.06:48:54.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.06:48:54.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.06:48:54.22#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:54.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:54.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:54.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:54.22#ibcon#enter wrdev, iclass 22, count 0 2006.201.06:48:54.22#ibcon#first serial, iclass 22, count 0 2006.201.06:48:54.22#ibcon#enter sib2, iclass 22, count 0 2006.201.06:48:54.22#ibcon#flushed, iclass 22, count 0 2006.201.06:48:54.22#ibcon#about to write, iclass 22, count 0 2006.201.06:48:54.22#ibcon#wrote, iclass 22, count 0 2006.201.06:48:54.22#ibcon#about to read 3, iclass 22, count 0 2006.201.06:48:54.24#ibcon#read 3, iclass 22, count 0 2006.201.06:48:54.24#ibcon#about to read 4, iclass 22, count 0 2006.201.06:48:54.24#ibcon#read 4, iclass 22, count 0 2006.201.06:48:54.24#ibcon#about to read 5, iclass 22, count 0 2006.201.06:48:54.24#ibcon#read 5, iclass 22, count 0 2006.201.06:48:54.24#ibcon#about to read 6, iclass 22, count 0 2006.201.06:48:54.24#ibcon#read 6, iclass 22, count 0 2006.201.06:48:54.24#ibcon#end of sib2, iclass 22, count 0 2006.201.06:48:54.24#ibcon#*mode == 0, iclass 22, count 0 2006.201.06:48:54.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.06:48:54.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.06:48:54.24#ibcon#*before write, iclass 22, count 0 2006.201.06:48:54.24#ibcon#enter sib2, iclass 22, count 0 2006.201.06:48:54.24#ibcon#flushed, iclass 22, count 0 2006.201.06:48:54.24#ibcon#about to write, iclass 22, count 0 2006.201.06:48:54.24#ibcon#wrote, iclass 22, count 0 2006.201.06:48:54.24#ibcon#about to read 3, iclass 22, count 0 2006.201.06:48:54.28#ibcon#read 3, iclass 22, count 0 2006.201.06:48:54.28#ibcon#about to read 4, iclass 22, count 0 2006.201.06:48:54.28#ibcon#read 4, iclass 22, count 0 2006.201.06:48:54.28#ibcon#about to read 5, iclass 22, count 0 2006.201.06:48:54.28#ibcon#read 5, iclass 22, count 0 2006.201.06:48:54.28#ibcon#about to read 6, iclass 22, count 0 2006.201.06:48:54.28#ibcon#read 6, iclass 22, count 0 2006.201.06:48:54.28#ibcon#end of sib2, iclass 22, count 0 2006.201.06:48:54.28#ibcon#*after write, iclass 22, count 0 2006.201.06:48:54.28#ibcon#*before return 0, iclass 22, count 0 2006.201.06:48:54.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:54.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:54.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.06:48:54.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.06:48:54.28$vck44/va=5,4 2006.201.06:48:54.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.06:48:54.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.06:48:54.28#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:54.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:54.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:54.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:54.34#ibcon#enter wrdev, iclass 24, count 2 2006.201.06:48:54.34#ibcon#first serial, iclass 24, count 2 2006.201.06:48:54.34#ibcon#enter sib2, iclass 24, count 2 2006.201.06:48:54.34#ibcon#flushed, iclass 24, count 2 2006.201.06:48:54.34#ibcon#about to write, iclass 24, count 2 2006.201.06:48:54.34#ibcon#wrote, iclass 24, count 2 2006.201.06:48:54.34#ibcon#about to read 3, iclass 24, count 2 2006.201.06:48:54.36#ibcon#read 3, iclass 24, count 2 2006.201.06:48:54.36#ibcon#about to read 4, iclass 24, count 2 2006.201.06:48:54.36#ibcon#read 4, iclass 24, count 2 2006.201.06:48:54.36#ibcon#about to read 5, iclass 24, count 2 2006.201.06:48:54.36#ibcon#read 5, iclass 24, count 2 2006.201.06:48:54.36#ibcon#about to read 6, iclass 24, count 2 2006.201.06:48:54.36#ibcon#read 6, iclass 24, count 2 2006.201.06:48:54.36#ibcon#end of sib2, iclass 24, count 2 2006.201.06:48:54.36#ibcon#*mode == 0, iclass 24, count 2 2006.201.06:48:54.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.06:48:54.36#ibcon#[25=AT05-04\r\n] 2006.201.06:48:54.36#ibcon#*before write, iclass 24, count 2 2006.201.06:48:54.36#ibcon#enter sib2, iclass 24, count 2 2006.201.06:48:54.36#ibcon#flushed, iclass 24, count 2 2006.201.06:48:54.36#ibcon#about to write, iclass 24, count 2 2006.201.06:48:54.36#ibcon#wrote, iclass 24, count 2 2006.201.06:48:54.36#ibcon#about to read 3, iclass 24, count 2 2006.201.06:48:54.39#ibcon#read 3, iclass 24, count 2 2006.201.06:48:54.39#ibcon#about to read 4, iclass 24, count 2 2006.201.06:48:54.39#ibcon#read 4, iclass 24, count 2 2006.201.06:48:54.39#ibcon#about to read 5, iclass 24, count 2 2006.201.06:48:54.39#ibcon#read 5, iclass 24, count 2 2006.201.06:48:54.39#ibcon#about to read 6, iclass 24, count 2 2006.201.06:48:54.39#ibcon#read 6, iclass 24, count 2 2006.201.06:48:54.39#ibcon#end of sib2, iclass 24, count 2 2006.201.06:48:54.39#ibcon#*after write, iclass 24, count 2 2006.201.06:48:54.39#ibcon#*before return 0, iclass 24, count 2 2006.201.06:48:54.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:54.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:54.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.06:48:54.39#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:54.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:54.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:54.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:54.51#ibcon#enter wrdev, iclass 24, count 0 2006.201.06:48:54.51#ibcon#first serial, iclass 24, count 0 2006.201.06:48:54.51#ibcon#enter sib2, iclass 24, count 0 2006.201.06:48:54.51#ibcon#flushed, iclass 24, count 0 2006.201.06:48:54.51#ibcon#about to write, iclass 24, count 0 2006.201.06:48:54.51#ibcon#wrote, iclass 24, count 0 2006.201.06:48:54.51#ibcon#about to read 3, iclass 24, count 0 2006.201.06:48:54.53#ibcon#read 3, iclass 24, count 0 2006.201.06:48:54.53#ibcon#about to read 4, iclass 24, count 0 2006.201.06:48:54.53#ibcon#read 4, iclass 24, count 0 2006.201.06:48:54.53#ibcon#about to read 5, iclass 24, count 0 2006.201.06:48:54.53#ibcon#read 5, iclass 24, count 0 2006.201.06:48:54.53#ibcon#about to read 6, iclass 24, count 0 2006.201.06:48:54.53#ibcon#read 6, iclass 24, count 0 2006.201.06:48:54.53#ibcon#end of sib2, iclass 24, count 0 2006.201.06:48:54.53#ibcon#*mode == 0, iclass 24, count 0 2006.201.06:48:54.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.06:48:54.53#ibcon#[25=USB\r\n] 2006.201.06:48:54.53#ibcon#*before write, iclass 24, count 0 2006.201.06:48:54.53#ibcon#enter sib2, iclass 24, count 0 2006.201.06:48:54.53#ibcon#flushed, iclass 24, count 0 2006.201.06:48:54.53#ibcon#about to write, iclass 24, count 0 2006.201.06:48:54.53#ibcon#wrote, iclass 24, count 0 2006.201.06:48:54.53#ibcon#about to read 3, iclass 24, count 0 2006.201.06:48:54.56#ibcon#read 3, iclass 24, count 0 2006.201.06:48:54.56#ibcon#about to read 4, iclass 24, count 0 2006.201.06:48:54.56#ibcon#read 4, iclass 24, count 0 2006.201.06:48:54.56#ibcon#about to read 5, iclass 24, count 0 2006.201.06:48:54.56#ibcon#read 5, iclass 24, count 0 2006.201.06:48:54.56#ibcon#about to read 6, iclass 24, count 0 2006.201.06:48:54.56#ibcon#read 6, iclass 24, count 0 2006.201.06:48:54.56#ibcon#end of sib2, iclass 24, count 0 2006.201.06:48:54.56#ibcon#*after write, iclass 24, count 0 2006.201.06:48:54.56#ibcon#*before return 0, iclass 24, count 0 2006.201.06:48:54.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:54.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:54.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.06:48:54.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.06:48:54.56$vck44/valo=6,814.99 2006.201.06:48:54.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.06:48:54.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.06:48:54.56#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:54.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:54.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:54.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:54.56#ibcon#enter wrdev, iclass 26, count 0 2006.201.06:48:54.56#ibcon#first serial, iclass 26, count 0 2006.201.06:48:54.56#ibcon#enter sib2, iclass 26, count 0 2006.201.06:48:54.56#ibcon#flushed, iclass 26, count 0 2006.201.06:48:54.56#ibcon#about to write, iclass 26, count 0 2006.201.06:48:54.56#ibcon#wrote, iclass 26, count 0 2006.201.06:48:54.56#ibcon#about to read 3, iclass 26, count 0 2006.201.06:48:54.58#ibcon#read 3, iclass 26, count 0 2006.201.06:48:54.58#ibcon#about to read 4, iclass 26, count 0 2006.201.06:48:54.58#ibcon#read 4, iclass 26, count 0 2006.201.06:48:54.58#ibcon#about to read 5, iclass 26, count 0 2006.201.06:48:54.58#ibcon#read 5, iclass 26, count 0 2006.201.06:48:54.58#ibcon#about to read 6, iclass 26, count 0 2006.201.06:48:54.58#ibcon#read 6, iclass 26, count 0 2006.201.06:48:54.58#ibcon#end of sib2, iclass 26, count 0 2006.201.06:48:54.58#ibcon#*mode == 0, iclass 26, count 0 2006.201.06:48:54.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.06:48:54.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.06:48:54.58#ibcon#*before write, iclass 26, count 0 2006.201.06:48:54.58#ibcon#enter sib2, iclass 26, count 0 2006.201.06:48:54.58#ibcon#flushed, iclass 26, count 0 2006.201.06:48:54.58#ibcon#about to write, iclass 26, count 0 2006.201.06:48:54.58#ibcon#wrote, iclass 26, count 0 2006.201.06:48:54.58#ibcon#about to read 3, iclass 26, count 0 2006.201.06:48:54.62#ibcon#read 3, iclass 26, count 0 2006.201.06:48:54.62#ibcon#about to read 4, iclass 26, count 0 2006.201.06:48:54.62#ibcon#read 4, iclass 26, count 0 2006.201.06:48:54.62#ibcon#about to read 5, iclass 26, count 0 2006.201.06:48:54.62#ibcon#read 5, iclass 26, count 0 2006.201.06:48:54.62#ibcon#about to read 6, iclass 26, count 0 2006.201.06:48:54.62#ibcon#read 6, iclass 26, count 0 2006.201.06:48:54.62#ibcon#end of sib2, iclass 26, count 0 2006.201.06:48:54.62#ibcon#*after write, iclass 26, count 0 2006.201.06:48:54.62#ibcon#*before return 0, iclass 26, count 0 2006.201.06:48:54.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:54.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:54.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.06:48:54.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.06:48:54.62$vck44/va=6,5 2006.201.06:48:54.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.06:48:54.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.06:48:54.62#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:54.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:54.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:54.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:54.68#ibcon#enter wrdev, iclass 28, count 2 2006.201.06:48:54.68#ibcon#first serial, iclass 28, count 2 2006.201.06:48:54.68#ibcon#enter sib2, iclass 28, count 2 2006.201.06:48:54.68#ibcon#flushed, iclass 28, count 2 2006.201.06:48:54.68#ibcon#about to write, iclass 28, count 2 2006.201.06:48:54.68#ibcon#wrote, iclass 28, count 2 2006.201.06:48:54.68#ibcon#about to read 3, iclass 28, count 2 2006.201.06:48:54.70#ibcon#read 3, iclass 28, count 2 2006.201.06:48:54.70#ibcon#about to read 4, iclass 28, count 2 2006.201.06:48:54.70#ibcon#read 4, iclass 28, count 2 2006.201.06:48:54.70#ibcon#about to read 5, iclass 28, count 2 2006.201.06:48:54.70#ibcon#read 5, iclass 28, count 2 2006.201.06:48:54.70#ibcon#about to read 6, iclass 28, count 2 2006.201.06:48:54.70#ibcon#read 6, iclass 28, count 2 2006.201.06:48:54.70#ibcon#end of sib2, iclass 28, count 2 2006.201.06:48:54.70#ibcon#*mode == 0, iclass 28, count 2 2006.201.06:48:54.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.06:48:54.70#ibcon#[25=AT06-05\r\n] 2006.201.06:48:54.70#ibcon#*before write, iclass 28, count 2 2006.201.06:48:54.70#ibcon#enter sib2, iclass 28, count 2 2006.201.06:48:54.70#ibcon#flushed, iclass 28, count 2 2006.201.06:48:54.70#ibcon#about to write, iclass 28, count 2 2006.201.06:48:54.70#ibcon#wrote, iclass 28, count 2 2006.201.06:48:54.70#ibcon#about to read 3, iclass 28, count 2 2006.201.06:48:54.73#ibcon#read 3, iclass 28, count 2 2006.201.06:48:54.73#ibcon#about to read 4, iclass 28, count 2 2006.201.06:48:54.73#ibcon#read 4, iclass 28, count 2 2006.201.06:48:54.73#ibcon#about to read 5, iclass 28, count 2 2006.201.06:48:54.73#ibcon#read 5, iclass 28, count 2 2006.201.06:48:54.73#ibcon#about to read 6, iclass 28, count 2 2006.201.06:48:54.73#ibcon#read 6, iclass 28, count 2 2006.201.06:48:54.73#ibcon#end of sib2, iclass 28, count 2 2006.201.06:48:54.73#ibcon#*after write, iclass 28, count 2 2006.201.06:48:54.73#ibcon#*before return 0, iclass 28, count 2 2006.201.06:48:54.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:54.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:54.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.06:48:54.73#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:54.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:54.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:54.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:54.85#ibcon#enter wrdev, iclass 28, count 0 2006.201.06:48:54.85#ibcon#first serial, iclass 28, count 0 2006.201.06:48:54.85#ibcon#enter sib2, iclass 28, count 0 2006.201.06:48:54.85#ibcon#flushed, iclass 28, count 0 2006.201.06:48:54.85#ibcon#about to write, iclass 28, count 0 2006.201.06:48:54.85#ibcon#wrote, iclass 28, count 0 2006.201.06:48:54.85#ibcon#about to read 3, iclass 28, count 0 2006.201.06:48:54.87#ibcon#read 3, iclass 28, count 0 2006.201.06:48:54.87#ibcon#about to read 4, iclass 28, count 0 2006.201.06:48:54.87#ibcon#read 4, iclass 28, count 0 2006.201.06:48:54.87#ibcon#about to read 5, iclass 28, count 0 2006.201.06:48:54.87#ibcon#read 5, iclass 28, count 0 2006.201.06:48:54.87#ibcon#about to read 6, iclass 28, count 0 2006.201.06:48:54.87#ibcon#read 6, iclass 28, count 0 2006.201.06:48:54.87#ibcon#end of sib2, iclass 28, count 0 2006.201.06:48:54.87#ibcon#*mode == 0, iclass 28, count 0 2006.201.06:48:54.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.06:48:54.87#ibcon#[25=USB\r\n] 2006.201.06:48:54.87#ibcon#*before write, iclass 28, count 0 2006.201.06:48:54.87#ibcon#enter sib2, iclass 28, count 0 2006.201.06:48:54.87#ibcon#flushed, iclass 28, count 0 2006.201.06:48:54.87#ibcon#about to write, iclass 28, count 0 2006.201.06:48:54.87#ibcon#wrote, iclass 28, count 0 2006.201.06:48:54.87#ibcon#about to read 3, iclass 28, count 0 2006.201.06:48:54.90#ibcon#read 3, iclass 28, count 0 2006.201.06:48:54.90#ibcon#about to read 4, iclass 28, count 0 2006.201.06:48:54.90#ibcon#read 4, iclass 28, count 0 2006.201.06:48:54.90#ibcon#about to read 5, iclass 28, count 0 2006.201.06:48:54.90#ibcon#read 5, iclass 28, count 0 2006.201.06:48:54.90#ibcon#about to read 6, iclass 28, count 0 2006.201.06:48:54.90#ibcon#read 6, iclass 28, count 0 2006.201.06:48:54.90#ibcon#end of sib2, iclass 28, count 0 2006.201.06:48:54.90#ibcon#*after write, iclass 28, count 0 2006.201.06:48:54.90#ibcon#*before return 0, iclass 28, count 0 2006.201.06:48:54.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:54.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:54.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.06:48:54.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.06:48:54.90$vck44/valo=7,864.99 2006.201.06:48:54.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.06:48:54.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.06:48:54.90#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:54.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:54.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:54.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:54.90#ibcon#enter wrdev, iclass 30, count 0 2006.201.06:48:54.90#ibcon#first serial, iclass 30, count 0 2006.201.06:48:54.90#ibcon#enter sib2, iclass 30, count 0 2006.201.06:48:54.90#ibcon#flushed, iclass 30, count 0 2006.201.06:48:54.90#ibcon#about to write, iclass 30, count 0 2006.201.06:48:54.90#ibcon#wrote, iclass 30, count 0 2006.201.06:48:54.90#ibcon#about to read 3, iclass 30, count 0 2006.201.06:48:54.92#ibcon#read 3, iclass 30, count 0 2006.201.06:48:54.92#ibcon#about to read 4, iclass 30, count 0 2006.201.06:48:54.92#ibcon#read 4, iclass 30, count 0 2006.201.06:48:54.92#ibcon#about to read 5, iclass 30, count 0 2006.201.06:48:54.92#ibcon#read 5, iclass 30, count 0 2006.201.06:48:54.92#ibcon#about to read 6, iclass 30, count 0 2006.201.06:48:54.92#ibcon#read 6, iclass 30, count 0 2006.201.06:48:54.92#ibcon#end of sib2, iclass 30, count 0 2006.201.06:48:54.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.06:48:54.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.06:48:54.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.06:48:54.92#ibcon#*before write, iclass 30, count 0 2006.201.06:48:54.92#ibcon#enter sib2, iclass 30, count 0 2006.201.06:48:54.92#ibcon#flushed, iclass 30, count 0 2006.201.06:48:54.92#ibcon#about to write, iclass 30, count 0 2006.201.06:48:54.92#ibcon#wrote, iclass 30, count 0 2006.201.06:48:54.92#ibcon#about to read 3, iclass 30, count 0 2006.201.06:48:54.96#ibcon#read 3, iclass 30, count 0 2006.201.06:48:54.96#ibcon#about to read 4, iclass 30, count 0 2006.201.06:48:54.96#ibcon#read 4, iclass 30, count 0 2006.201.06:48:54.96#ibcon#about to read 5, iclass 30, count 0 2006.201.06:48:54.96#ibcon#read 5, iclass 30, count 0 2006.201.06:48:54.96#ibcon#about to read 6, iclass 30, count 0 2006.201.06:48:54.96#ibcon#read 6, iclass 30, count 0 2006.201.06:48:54.96#ibcon#end of sib2, iclass 30, count 0 2006.201.06:48:54.96#ibcon#*after write, iclass 30, count 0 2006.201.06:48:54.96#ibcon#*before return 0, iclass 30, count 0 2006.201.06:48:54.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:54.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:54.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.06:48:54.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.06:48:54.96$vck44/va=7,5 2006.201.06:48:54.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.06:48:54.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.06:48:54.96#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:54.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:55.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:55.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:55.02#ibcon#enter wrdev, iclass 32, count 2 2006.201.06:48:55.02#ibcon#first serial, iclass 32, count 2 2006.201.06:48:55.02#ibcon#enter sib2, iclass 32, count 2 2006.201.06:48:55.02#ibcon#flushed, iclass 32, count 2 2006.201.06:48:55.02#ibcon#about to write, iclass 32, count 2 2006.201.06:48:55.02#ibcon#wrote, iclass 32, count 2 2006.201.06:48:55.02#ibcon#about to read 3, iclass 32, count 2 2006.201.06:48:55.04#ibcon#read 3, iclass 32, count 2 2006.201.06:48:55.04#ibcon#about to read 4, iclass 32, count 2 2006.201.06:48:55.04#ibcon#read 4, iclass 32, count 2 2006.201.06:48:55.04#ibcon#about to read 5, iclass 32, count 2 2006.201.06:48:55.04#ibcon#read 5, iclass 32, count 2 2006.201.06:48:55.04#ibcon#about to read 6, iclass 32, count 2 2006.201.06:48:55.04#ibcon#read 6, iclass 32, count 2 2006.201.06:48:55.04#ibcon#end of sib2, iclass 32, count 2 2006.201.06:48:55.04#ibcon#*mode == 0, iclass 32, count 2 2006.201.06:48:55.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.06:48:55.04#ibcon#[25=AT07-05\r\n] 2006.201.06:48:55.04#ibcon#*before write, iclass 32, count 2 2006.201.06:48:55.04#ibcon#enter sib2, iclass 32, count 2 2006.201.06:48:55.04#ibcon#flushed, iclass 32, count 2 2006.201.06:48:55.04#ibcon#about to write, iclass 32, count 2 2006.201.06:48:55.04#ibcon#wrote, iclass 32, count 2 2006.201.06:48:55.04#ibcon#about to read 3, iclass 32, count 2 2006.201.06:48:55.07#ibcon#read 3, iclass 32, count 2 2006.201.06:48:55.07#ibcon#about to read 4, iclass 32, count 2 2006.201.06:48:55.07#ibcon#read 4, iclass 32, count 2 2006.201.06:48:55.07#ibcon#about to read 5, iclass 32, count 2 2006.201.06:48:55.07#ibcon#read 5, iclass 32, count 2 2006.201.06:48:55.07#ibcon#about to read 6, iclass 32, count 2 2006.201.06:48:55.07#ibcon#read 6, iclass 32, count 2 2006.201.06:48:55.07#ibcon#end of sib2, iclass 32, count 2 2006.201.06:48:55.07#ibcon#*after write, iclass 32, count 2 2006.201.06:48:55.07#ibcon#*before return 0, iclass 32, count 2 2006.201.06:48:55.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:55.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:55.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.06:48:55.07#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:55.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:55.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:55.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:55.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.06:48:55.19#ibcon#first serial, iclass 32, count 0 2006.201.06:48:55.19#ibcon#enter sib2, iclass 32, count 0 2006.201.06:48:55.19#ibcon#flushed, iclass 32, count 0 2006.201.06:48:55.19#ibcon#about to write, iclass 32, count 0 2006.201.06:48:55.19#ibcon#wrote, iclass 32, count 0 2006.201.06:48:55.19#ibcon#about to read 3, iclass 32, count 0 2006.201.06:48:55.21#ibcon#read 3, iclass 32, count 0 2006.201.06:48:55.21#ibcon#about to read 4, iclass 32, count 0 2006.201.06:48:55.21#ibcon#read 4, iclass 32, count 0 2006.201.06:48:55.21#ibcon#about to read 5, iclass 32, count 0 2006.201.06:48:55.21#ibcon#read 5, iclass 32, count 0 2006.201.06:48:55.21#ibcon#about to read 6, iclass 32, count 0 2006.201.06:48:55.21#ibcon#read 6, iclass 32, count 0 2006.201.06:48:55.21#ibcon#end of sib2, iclass 32, count 0 2006.201.06:48:55.21#ibcon#*mode == 0, iclass 32, count 0 2006.201.06:48:55.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.06:48:55.21#ibcon#[25=USB\r\n] 2006.201.06:48:55.21#ibcon#*before write, iclass 32, count 0 2006.201.06:48:55.21#ibcon#enter sib2, iclass 32, count 0 2006.201.06:48:55.21#ibcon#flushed, iclass 32, count 0 2006.201.06:48:55.21#ibcon#about to write, iclass 32, count 0 2006.201.06:48:55.21#ibcon#wrote, iclass 32, count 0 2006.201.06:48:55.21#ibcon#about to read 3, iclass 32, count 0 2006.201.06:48:55.24#ibcon#read 3, iclass 32, count 0 2006.201.06:48:55.24#ibcon#about to read 4, iclass 32, count 0 2006.201.06:48:55.24#ibcon#read 4, iclass 32, count 0 2006.201.06:48:55.24#ibcon#about to read 5, iclass 32, count 0 2006.201.06:48:55.24#ibcon#read 5, iclass 32, count 0 2006.201.06:48:55.24#ibcon#about to read 6, iclass 32, count 0 2006.201.06:48:55.24#ibcon#read 6, iclass 32, count 0 2006.201.06:48:55.24#ibcon#end of sib2, iclass 32, count 0 2006.201.06:48:55.24#ibcon#*after write, iclass 32, count 0 2006.201.06:48:55.24#ibcon#*before return 0, iclass 32, count 0 2006.201.06:48:55.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:55.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:55.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.06:48:55.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.06:48:55.24$vck44/valo=8,884.99 2006.201.06:48:55.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.06:48:55.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.06:48:55.24#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:55.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:55.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:55.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:55.24#ibcon#enter wrdev, iclass 34, count 0 2006.201.06:48:55.24#ibcon#first serial, iclass 34, count 0 2006.201.06:48:55.24#ibcon#enter sib2, iclass 34, count 0 2006.201.06:48:55.24#ibcon#flushed, iclass 34, count 0 2006.201.06:48:55.24#ibcon#about to write, iclass 34, count 0 2006.201.06:48:55.24#ibcon#wrote, iclass 34, count 0 2006.201.06:48:55.24#ibcon#about to read 3, iclass 34, count 0 2006.201.06:48:55.26#ibcon#read 3, iclass 34, count 0 2006.201.06:48:55.26#ibcon#about to read 4, iclass 34, count 0 2006.201.06:48:55.26#ibcon#read 4, iclass 34, count 0 2006.201.06:48:55.26#ibcon#about to read 5, iclass 34, count 0 2006.201.06:48:55.26#ibcon#read 5, iclass 34, count 0 2006.201.06:48:55.26#ibcon#about to read 6, iclass 34, count 0 2006.201.06:48:55.26#ibcon#read 6, iclass 34, count 0 2006.201.06:48:55.26#ibcon#end of sib2, iclass 34, count 0 2006.201.06:48:55.26#ibcon#*mode == 0, iclass 34, count 0 2006.201.06:48:55.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.06:48:55.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.06:48:55.26#ibcon#*before write, iclass 34, count 0 2006.201.06:48:55.26#ibcon#enter sib2, iclass 34, count 0 2006.201.06:48:55.26#ibcon#flushed, iclass 34, count 0 2006.201.06:48:55.26#ibcon#about to write, iclass 34, count 0 2006.201.06:48:55.26#ibcon#wrote, iclass 34, count 0 2006.201.06:48:55.26#ibcon#about to read 3, iclass 34, count 0 2006.201.06:48:55.30#ibcon#read 3, iclass 34, count 0 2006.201.06:48:55.30#ibcon#about to read 4, iclass 34, count 0 2006.201.06:48:55.30#ibcon#read 4, iclass 34, count 0 2006.201.06:48:55.30#ibcon#about to read 5, iclass 34, count 0 2006.201.06:48:55.30#ibcon#read 5, iclass 34, count 0 2006.201.06:48:55.30#ibcon#about to read 6, iclass 34, count 0 2006.201.06:48:55.30#ibcon#read 6, iclass 34, count 0 2006.201.06:48:55.30#ibcon#end of sib2, iclass 34, count 0 2006.201.06:48:55.30#ibcon#*after write, iclass 34, count 0 2006.201.06:48:55.30#ibcon#*before return 0, iclass 34, count 0 2006.201.06:48:55.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:55.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:55.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.06:48:55.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.06:48:55.30$vck44/va=8,4 2006.201.06:48:55.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.06:48:55.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.06:48:55.30#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:55.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:55.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:55.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:55.36#ibcon#enter wrdev, iclass 36, count 2 2006.201.06:48:55.36#ibcon#first serial, iclass 36, count 2 2006.201.06:48:55.36#ibcon#enter sib2, iclass 36, count 2 2006.201.06:48:55.36#ibcon#flushed, iclass 36, count 2 2006.201.06:48:55.36#ibcon#about to write, iclass 36, count 2 2006.201.06:48:55.36#ibcon#wrote, iclass 36, count 2 2006.201.06:48:55.36#ibcon#about to read 3, iclass 36, count 2 2006.201.06:48:55.38#ibcon#read 3, iclass 36, count 2 2006.201.06:48:55.38#ibcon#about to read 4, iclass 36, count 2 2006.201.06:48:55.38#ibcon#read 4, iclass 36, count 2 2006.201.06:48:55.38#ibcon#about to read 5, iclass 36, count 2 2006.201.06:48:55.38#ibcon#read 5, iclass 36, count 2 2006.201.06:48:55.38#ibcon#about to read 6, iclass 36, count 2 2006.201.06:48:55.38#ibcon#read 6, iclass 36, count 2 2006.201.06:48:55.38#ibcon#end of sib2, iclass 36, count 2 2006.201.06:48:55.38#ibcon#*mode == 0, iclass 36, count 2 2006.201.06:48:55.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.06:48:55.38#ibcon#[25=AT08-04\r\n] 2006.201.06:48:55.38#ibcon#*before write, iclass 36, count 2 2006.201.06:48:55.38#ibcon#enter sib2, iclass 36, count 2 2006.201.06:48:55.38#ibcon#flushed, iclass 36, count 2 2006.201.06:48:55.38#ibcon#about to write, iclass 36, count 2 2006.201.06:48:55.38#ibcon#wrote, iclass 36, count 2 2006.201.06:48:55.38#ibcon#about to read 3, iclass 36, count 2 2006.201.06:48:55.41#ibcon#read 3, iclass 36, count 2 2006.201.06:48:55.41#ibcon#about to read 4, iclass 36, count 2 2006.201.06:48:55.41#ibcon#read 4, iclass 36, count 2 2006.201.06:48:55.41#ibcon#about to read 5, iclass 36, count 2 2006.201.06:48:55.41#ibcon#read 5, iclass 36, count 2 2006.201.06:48:55.41#ibcon#about to read 6, iclass 36, count 2 2006.201.06:48:55.41#ibcon#read 6, iclass 36, count 2 2006.201.06:48:55.41#ibcon#end of sib2, iclass 36, count 2 2006.201.06:48:55.41#ibcon#*after write, iclass 36, count 2 2006.201.06:48:55.41#ibcon#*before return 0, iclass 36, count 2 2006.201.06:48:55.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:55.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:55.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.06:48:55.41#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:55.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:55.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:55.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:55.53#ibcon#enter wrdev, iclass 36, count 0 2006.201.06:48:55.53#ibcon#first serial, iclass 36, count 0 2006.201.06:48:55.53#ibcon#enter sib2, iclass 36, count 0 2006.201.06:48:55.53#ibcon#flushed, iclass 36, count 0 2006.201.06:48:55.53#ibcon#about to write, iclass 36, count 0 2006.201.06:48:55.53#ibcon#wrote, iclass 36, count 0 2006.201.06:48:55.53#ibcon#about to read 3, iclass 36, count 0 2006.201.06:48:55.55#ibcon#read 3, iclass 36, count 0 2006.201.06:48:55.55#ibcon#about to read 4, iclass 36, count 0 2006.201.06:48:55.55#ibcon#read 4, iclass 36, count 0 2006.201.06:48:55.55#ibcon#about to read 5, iclass 36, count 0 2006.201.06:48:55.55#ibcon#read 5, iclass 36, count 0 2006.201.06:48:55.55#ibcon#about to read 6, iclass 36, count 0 2006.201.06:48:55.55#ibcon#read 6, iclass 36, count 0 2006.201.06:48:55.55#ibcon#end of sib2, iclass 36, count 0 2006.201.06:48:55.55#ibcon#*mode == 0, iclass 36, count 0 2006.201.06:48:55.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.06:48:55.55#ibcon#[25=USB\r\n] 2006.201.06:48:55.55#ibcon#*before write, iclass 36, count 0 2006.201.06:48:55.55#ibcon#enter sib2, iclass 36, count 0 2006.201.06:48:55.55#ibcon#flushed, iclass 36, count 0 2006.201.06:48:55.55#ibcon#about to write, iclass 36, count 0 2006.201.06:48:55.55#ibcon#wrote, iclass 36, count 0 2006.201.06:48:55.55#ibcon#about to read 3, iclass 36, count 0 2006.201.06:48:55.58#ibcon#read 3, iclass 36, count 0 2006.201.06:48:55.58#ibcon#about to read 4, iclass 36, count 0 2006.201.06:48:55.58#ibcon#read 4, iclass 36, count 0 2006.201.06:48:55.58#ibcon#about to read 5, iclass 36, count 0 2006.201.06:48:55.58#ibcon#read 5, iclass 36, count 0 2006.201.06:48:55.58#ibcon#about to read 6, iclass 36, count 0 2006.201.06:48:55.58#ibcon#read 6, iclass 36, count 0 2006.201.06:48:55.58#ibcon#end of sib2, iclass 36, count 0 2006.201.06:48:55.58#ibcon#*after write, iclass 36, count 0 2006.201.06:48:55.58#ibcon#*before return 0, iclass 36, count 0 2006.201.06:48:55.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:55.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:55.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.06:48:55.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.06:48:55.58$vck44/vblo=1,629.99 2006.201.06:48:55.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.06:48:55.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.06:48:55.58#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:55.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:55.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:55.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:55.58#ibcon#enter wrdev, iclass 38, count 0 2006.201.06:48:55.58#ibcon#first serial, iclass 38, count 0 2006.201.06:48:55.58#ibcon#enter sib2, iclass 38, count 0 2006.201.06:48:55.58#ibcon#flushed, iclass 38, count 0 2006.201.06:48:55.58#ibcon#about to write, iclass 38, count 0 2006.201.06:48:55.58#ibcon#wrote, iclass 38, count 0 2006.201.06:48:55.58#ibcon#about to read 3, iclass 38, count 0 2006.201.06:48:55.60#ibcon#read 3, iclass 38, count 0 2006.201.06:48:55.60#ibcon#about to read 4, iclass 38, count 0 2006.201.06:48:55.60#ibcon#read 4, iclass 38, count 0 2006.201.06:48:55.60#ibcon#about to read 5, iclass 38, count 0 2006.201.06:48:55.60#ibcon#read 5, iclass 38, count 0 2006.201.06:48:55.60#ibcon#about to read 6, iclass 38, count 0 2006.201.06:48:55.60#ibcon#read 6, iclass 38, count 0 2006.201.06:48:55.60#ibcon#end of sib2, iclass 38, count 0 2006.201.06:48:55.60#ibcon#*mode == 0, iclass 38, count 0 2006.201.06:48:55.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.06:48:55.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.06:48:55.60#ibcon#*before write, iclass 38, count 0 2006.201.06:48:55.60#ibcon#enter sib2, iclass 38, count 0 2006.201.06:48:55.60#ibcon#flushed, iclass 38, count 0 2006.201.06:48:55.60#ibcon#about to write, iclass 38, count 0 2006.201.06:48:55.60#ibcon#wrote, iclass 38, count 0 2006.201.06:48:55.60#ibcon#about to read 3, iclass 38, count 0 2006.201.06:48:55.65#ibcon#read 3, iclass 38, count 0 2006.201.06:48:55.65#ibcon#about to read 4, iclass 38, count 0 2006.201.06:48:55.65#ibcon#read 4, iclass 38, count 0 2006.201.06:48:55.65#ibcon#about to read 5, iclass 38, count 0 2006.201.06:48:55.65#ibcon#read 5, iclass 38, count 0 2006.201.06:48:55.65#ibcon#about to read 6, iclass 38, count 0 2006.201.06:48:55.65#ibcon#read 6, iclass 38, count 0 2006.201.06:48:55.65#ibcon#end of sib2, iclass 38, count 0 2006.201.06:48:55.65#ibcon#*after write, iclass 38, count 0 2006.201.06:48:55.65#ibcon#*before return 0, iclass 38, count 0 2006.201.06:48:55.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:55.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:55.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.06:48:55.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.06:48:55.65$vck44/vb=1,4 2006.201.06:48:55.65#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.06:48:55.65#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.06:48:55.65#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:55.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.06:48:55.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.06:48:55.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.06:48:55.65#ibcon#enter wrdev, iclass 40, count 2 2006.201.06:48:55.65#ibcon#first serial, iclass 40, count 2 2006.201.06:48:55.65#ibcon#enter sib2, iclass 40, count 2 2006.201.06:48:55.65#ibcon#flushed, iclass 40, count 2 2006.201.06:48:55.65#ibcon#about to write, iclass 40, count 2 2006.201.06:48:55.65#ibcon#wrote, iclass 40, count 2 2006.201.06:48:55.65#ibcon#about to read 3, iclass 40, count 2 2006.201.06:48:55.67#ibcon#read 3, iclass 40, count 2 2006.201.06:48:55.67#ibcon#about to read 4, iclass 40, count 2 2006.201.06:48:55.67#ibcon#read 4, iclass 40, count 2 2006.201.06:48:55.67#ibcon#about to read 5, iclass 40, count 2 2006.201.06:48:55.67#ibcon#read 5, iclass 40, count 2 2006.201.06:48:55.67#ibcon#about to read 6, iclass 40, count 2 2006.201.06:48:55.67#ibcon#read 6, iclass 40, count 2 2006.201.06:48:55.67#ibcon#end of sib2, iclass 40, count 2 2006.201.06:48:55.67#ibcon#*mode == 0, iclass 40, count 2 2006.201.06:48:55.67#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.06:48:55.67#ibcon#[27=AT01-04\r\n] 2006.201.06:48:55.67#ibcon#*before write, iclass 40, count 2 2006.201.06:48:55.67#ibcon#enter sib2, iclass 40, count 2 2006.201.06:48:55.67#ibcon#flushed, iclass 40, count 2 2006.201.06:48:55.67#ibcon#about to write, iclass 40, count 2 2006.201.06:48:55.67#ibcon#wrote, iclass 40, count 2 2006.201.06:48:55.67#ibcon#about to read 3, iclass 40, count 2 2006.201.06:48:55.70#ibcon#read 3, iclass 40, count 2 2006.201.06:48:55.70#ibcon#about to read 4, iclass 40, count 2 2006.201.06:48:55.70#ibcon#read 4, iclass 40, count 2 2006.201.06:48:55.70#ibcon#about to read 5, iclass 40, count 2 2006.201.06:48:55.70#ibcon#read 5, iclass 40, count 2 2006.201.06:48:55.70#ibcon#about to read 6, iclass 40, count 2 2006.201.06:48:55.70#ibcon#read 6, iclass 40, count 2 2006.201.06:48:55.70#ibcon#end of sib2, iclass 40, count 2 2006.201.06:48:55.70#ibcon#*after write, iclass 40, count 2 2006.201.06:48:55.70#ibcon#*before return 0, iclass 40, count 2 2006.201.06:48:55.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.06:48:55.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.06:48:55.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.06:48:55.70#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:55.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.06:48:55.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.06:48:55.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.06:48:55.82#ibcon#enter wrdev, iclass 40, count 0 2006.201.06:48:55.82#ibcon#first serial, iclass 40, count 0 2006.201.06:48:55.82#ibcon#enter sib2, iclass 40, count 0 2006.201.06:48:55.82#ibcon#flushed, iclass 40, count 0 2006.201.06:48:55.82#ibcon#about to write, iclass 40, count 0 2006.201.06:48:55.82#ibcon#wrote, iclass 40, count 0 2006.201.06:48:55.82#ibcon#about to read 3, iclass 40, count 0 2006.201.06:48:55.84#ibcon#read 3, iclass 40, count 0 2006.201.06:48:55.84#ibcon#about to read 4, iclass 40, count 0 2006.201.06:48:55.84#ibcon#read 4, iclass 40, count 0 2006.201.06:48:55.84#ibcon#about to read 5, iclass 40, count 0 2006.201.06:48:55.84#ibcon#read 5, iclass 40, count 0 2006.201.06:48:55.84#ibcon#about to read 6, iclass 40, count 0 2006.201.06:48:55.84#ibcon#read 6, iclass 40, count 0 2006.201.06:48:55.84#ibcon#end of sib2, iclass 40, count 0 2006.201.06:48:55.84#ibcon#*mode == 0, iclass 40, count 0 2006.201.06:48:55.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.06:48:55.84#ibcon#[27=USB\r\n] 2006.201.06:48:55.84#ibcon#*before write, iclass 40, count 0 2006.201.06:48:55.84#ibcon#enter sib2, iclass 40, count 0 2006.201.06:48:55.84#ibcon#flushed, iclass 40, count 0 2006.201.06:48:55.84#ibcon#about to write, iclass 40, count 0 2006.201.06:48:55.84#ibcon#wrote, iclass 40, count 0 2006.201.06:48:55.84#ibcon#about to read 3, iclass 40, count 0 2006.201.06:48:55.87#ibcon#read 3, iclass 40, count 0 2006.201.06:48:55.87#ibcon#about to read 4, iclass 40, count 0 2006.201.06:48:55.87#ibcon#read 4, iclass 40, count 0 2006.201.06:48:55.87#ibcon#about to read 5, iclass 40, count 0 2006.201.06:48:55.87#ibcon#read 5, iclass 40, count 0 2006.201.06:48:55.87#ibcon#about to read 6, iclass 40, count 0 2006.201.06:48:55.87#ibcon#read 6, iclass 40, count 0 2006.201.06:48:55.87#ibcon#end of sib2, iclass 40, count 0 2006.201.06:48:55.87#ibcon#*after write, iclass 40, count 0 2006.201.06:48:55.87#ibcon#*before return 0, iclass 40, count 0 2006.201.06:48:55.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.06:48:55.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.06:48:55.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.06:48:55.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.06:48:55.87$vck44/vblo=2,634.99 2006.201.06:48:55.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.06:48:55.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.06:48:55.87#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:55.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:55.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:55.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:55.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.06:48:55.87#ibcon#first serial, iclass 4, count 0 2006.201.06:48:55.87#ibcon#enter sib2, iclass 4, count 0 2006.201.06:48:55.87#ibcon#flushed, iclass 4, count 0 2006.201.06:48:55.87#ibcon#about to write, iclass 4, count 0 2006.201.06:48:55.87#ibcon#wrote, iclass 4, count 0 2006.201.06:48:55.87#ibcon#about to read 3, iclass 4, count 0 2006.201.06:48:55.89#ibcon#read 3, iclass 4, count 0 2006.201.06:48:55.89#ibcon#about to read 4, iclass 4, count 0 2006.201.06:48:55.89#ibcon#read 4, iclass 4, count 0 2006.201.06:48:55.89#ibcon#about to read 5, iclass 4, count 0 2006.201.06:48:55.89#ibcon#read 5, iclass 4, count 0 2006.201.06:48:55.89#ibcon#about to read 6, iclass 4, count 0 2006.201.06:48:55.89#ibcon#read 6, iclass 4, count 0 2006.201.06:48:55.89#ibcon#end of sib2, iclass 4, count 0 2006.201.06:48:55.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.06:48:55.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.06:48:55.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.06:48:55.89#ibcon#*before write, iclass 4, count 0 2006.201.06:48:55.89#ibcon#enter sib2, iclass 4, count 0 2006.201.06:48:55.89#ibcon#flushed, iclass 4, count 0 2006.201.06:48:55.89#ibcon#about to write, iclass 4, count 0 2006.201.06:48:55.89#ibcon#wrote, iclass 4, count 0 2006.201.06:48:55.89#ibcon#about to read 3, iclass 4, count 0 2006.201.06:48:55.93#ibcon#read 3, iclass 4, count 0 2006.201.06:48:55.93#ibcon#about to read 4, iclass 4, count 0 2006.201.06:48:55.93#ibcon#read 4, iclass 4, count 0 2006.201.06:48:55.93#ibcon#about to read 5, iclass 4, count 0 2006.201.06:48:55.93#ibcon#read 5, iclass 4, count 0 2006.201.06:48:55.93#ibcon#about to read 6, iclass 4, count 0 2006.201.06:48:55.93#ibcon#read 6, iclass 4, count 0 2006.201.06:48:55.93#ibcon#end of sib2, iclass 4, count 0 2006.201.06:48:55.93#ibcon#*after write, iclass 4, count 0 2006.201.06:48:55.93#ibcon#*before return 0, iclass 4, count 0 2006.201.06:48:55.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:55.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.06:48:55.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.06:48:55.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.06:48:55.93$vck44/vb=2,5 2006.201.06:48:55.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.06:48:55.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.06:48:55.93#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:55.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:55.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:55.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:55.99#ibcon#enter wrdev, iclass 6, count 2 2006.201.06:48:55.99#ibcon#first serial, iclass 6, count 2 2006.201.06:48:55.99#ibcon#enter sib2, iclass 6, count 2 2006.201.06:48:55.99#ibcon#flushed, iclass 6, count 2 2006.201.06:48:55.99#ibcon#about to write, iclass 6, count 2 2006.201.06:48:55.99#ibcon#wrote, iclass 6, count 2 2006.201.06:48:55.99#ibcon#about to read 3, iclass 6, count 2 2006.201.06:48:56.01#ibcon#read 3, iclass 6, count 2 2006.201.06:48:56.01#ibcon#about to read 4, iclass 6, count 2 2006.201.06:48:56.01#ibcon#read 4, iclass 6, count 2 2006.201.06:48:56.01#ibcon#about to read 5, iclass 6, count 2 2006.201.06:48:56.01#ibcon#read 5, iclass 6, count 2 2006.201.06:48:56.01#ibcon#about to read 6, iclass 6, count 2 2006.201.06:48:56.01#ibcon#read 6, iclass 6, count 2 2006.201.06:48:56.01#ibcon#end of sib2, iclass 6, count 2 2006.201.06:48:56.01#ibcon#*mode == 0, iclass 6, count 2 2006.201.06:48:56.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.06:48:56.01#ibcon#[27=AT02-05\r\n] 2006.201.06:48:56.01#ibcon#*before write, iclass 6, count 2 2006.201.06:48:56.01#ibcon#enter sib2, iclass 6, count 2 2006.201.06:48:56.01#ibcon#flushed, iclass 6, count 2 2006.201.06:48:56.01#ibcon#about to write, iclass 6, count 2 2006.201.06:48:56.01#ibcon#wrote, iclass 6, count 2 2006.201.06:48:56.01#ibcon#about to read 3, iclass 6, count 2 2006.201.06:48:56.04#ibcon#read 3, iclass 6, count 2 2006.201.06:48:56.04#ibcon#about to read 4, iclass 6, count 2 2006.201.06:48:56.04#ibcon#read 4, iclass 6, count 2 2006.201.06:48:56.04#ibcon#about to read 5, iclass 6, count 2 2006.201.06:48:56.04#ibcon#read 5, iclass 6, count 2 2006.201.06:48:56.04#ibcon#about to read 6, iclass 6, count 2 2006.201.06:48:56.04#ibcon#read 6, iclass 6, count 2 2006.201.06:48:56.04#ibcon#end of sib2, iclass 6, count 2 2006.201.06:48:56.04#ibcon#*after write, iclass 6, count 2 2006.201.06:48:56.04#ibcon#*before return 0, iclass 6, count 2 2006.201.06:48:56.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:56.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.06:48:56.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.06:48:56.04#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:56.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:56.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:56.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:56.16#ibcon#enter wrdev, iclass 6, count 0 2006.201.06:48:56.16#ibcon#first serial, iclass 6, count 0 2006.201.06:48:56.16#ibcon#enter sib2, iclass 6, count 0 2006.201.06:48:56.16#ibcon#flushed, iclass 6, count 0 2006.201.06:48:56.16#ibcon#about to write, iclass 6, count 0 2006.201.06:48:56.16#ibcon#wrote, iclass 6, count 0 2006.201.06:48:56.16#ibcon#about to read 3, iclass 6, count 0 2006.201.06:48:56.18#ibcon#read 3, iclass 6, count 0 2006.201.06:48:56.18#ibcon#about to read 4, iclass 6, count 0 2006.201.06:48:56.18#ibcon#read 4, iclass 6, count 0 2006.201.06:48:56.18#ibcon#about to read 5, iclass 6, count 0 2006.201.06:48:56.18#ibcon#read 5, iclass 6, count 0 2006.201.06:48:56.18#ibcon#about to read 6, iclass 6, count 0 2006.201.06:48:56.18#ibcon#read 6, iclass 6, count 0 2006.201.06:48:56.18#ibcon#end of sib2, iclass 6, count 0 2006.201.06:48:56.18#ibcon#*mode == 0, iclass 6, count 0 2006.201.06:48:56.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.06:48:56.18#ibcon#[27=USB\r\n] 2006.201.06:48:56.18#ibcon#*before write, iclass 6, count 0 2006.201.06:48:56.18#ibcon#enter sib2, iclass 6, count 0 2006.201.06:48:56.18#ibcon#flushed, iclass 6, count 0 2006.201.06:48:56.18#ibcon#about to write, iclass 6, count 0 2006.201.06:48:56.18#ibcon#wrote, iclass 6, count 0 2006.201.06:48:56.18#ibcon#about to read 3, iclass 6, count 0 2006.201.06:48:56.21#ibcon#read 3, iclass 6, count 0 2006.201.06:48:56.21#ibcon#about to read 4, iclass 6, count 0 2006.201.06:48:56.21#ibcon#read 4, iclass 6, count 0 2006.201.06:48:56.21#ibcon#about to read 5, iclass 6, count 0 2006.201.06:48:56.21#ibcon#read 5, iclass 6, count 0 2006.201.06:48:56.21#ibcon#about to read 6, iclass 6, count 0 2006.201.06:48:56.21#ibcon#read 6, iclass 6, count 0 2006.201.06:48:56.21#ibcon#end of sib2, iclass 6, count 0 2006.201.06:48:56.21#ibcon#*after write, iclass 6, count 0 2006.201.06:48:56.21#ibcon#*before return 0, iclass 6, count 0 2006.201.06:48:56.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:56.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.06:48:56.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.06:48:56.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.06:48:56.21$vck44/vblo=3,649.99 2006.201.06:48:56.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.06:48:56.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.06:48:56.21#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:56.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:56.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:56.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:56.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.06:48:56.21#ibcon#first serial, iclass 10, count 0 2006.201.06:48:56.21#ibcon#enter sib2, iclass 10, count 0 2006.201.06:48:56.21#ibcon#flushed, iclass 10, count 0 2006.201.06:48:56.21#ibcon#about to write, iclass 10, count 0 2006.201.06:48:56.21#ibcon#wrote, iclass 10, count 0 2006.201.06:48:56.21#ibcon#about to read 3, iclass 10, count 0 2006.201.06:48:56.23#ibcon#read 3, iclass 10, count 0 2006.201.06:48:56.23#ibcon#about to read 4, iclass 10, count 0 2006.201.06:48:56.23#ibcon#read 4, iclass 10, count 0 2006.201.06:48:56.23#ibcon#about to read 5, iclass 10, count 0 2006.201.06:48:56.23#ibcon#read 5, iclass 10, count 0 2006.201.06:48:56.23#ibcon#about to read 6, iclass 10, count 0 2006.201.06:48:56.23#ibcon#read 6, iclass 10, count 0 2006.201.06:48:56.23#ibcon#end of sib2, iclass 10, count 0 2006.201.06:48:56.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.06:48:56.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.06:48:56.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.06:48:56.23#ibcon#*before write, iclass 10, count 0 2006.201.06:48:56.23#ibcon#enter sib2, iclass 10, count 0 2006.201.06:48:56.23#ibcon#flushed, iclass 10, count 0 2006.201.06:48:56.23#ibcon#about to write, iclass 10, count 0 2006.201.06:48:56.23#ibcon#wrote, iclass 10, count 0 2006.201.06:48:56.23#ibcon#about to read 3, iclass 10, count 0 2006.201.06:48:56.28#ibcon#read 3, iclass 10, count 0 2006.201.06:48:56.28#ibcon#about to read 4, iclass 10, count 0 2006.201.06:48:56.28#ibcon#read 4, iclass 10, count 0 2006.201.06:48:56.28#ibcon#about to read 5, iclass 10, count 0 2006.201.06:48:56.28#ibcon#read 5, iclass 10, count 0 2006.201.06:48:56.28#ibcon#about to read 6, iclass 10, count 0 2006.201.06:48:56.28#ibcon#read 6, iclass 10, count 0 2006.201.06:48:56.28#ibcon#end of sib2, iclass 10, count 0 2006.201.06:48:56.28#ibcon#*after write, iclass 10, count 0 2006.201.06:48:56.28#ibcon#*before return 0, iclass 10, count 0 2006.201.06:48:56.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:56.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.06:48:56.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.06:48:56.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.06:48:56.28$vck44/vb=3,4 2006.201.06:48:56.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.06:48:56.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.06:48:56.28#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:56.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:56.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:56.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:56.33#ibcon#enter wrdev, iclass 12, count 2 2006.201.06:48:56.33#ibcon#first serial, iclass 12, count 2 2006.201.06:48:56.33#ibcon#enter sib2, iclass 12, count 2 2006.201.06:48:56.33#ibcon#flushed, iclass 12, count 2 2006.201.06:48:56.33#ibcon#about to write, iclass 12, count 2 2006.201.06:48:56.33#ibcon#wrote, iclass 12, count 2 2006.201.06:48:56.33#ibcon#about to read 3, iclass 12, count 2 2006.201.06:48:56.35#ibcon#read 3, iclass 12, count 2 2006.201.06:48:56.35#ibcon#about to read 4, iclass 12, count 2 2006.201.06:48:56.35#ibcon#read 4, iclass 12, count 2 2006.201.06:48:56.35#ibcon#about to read 5, iclass 12, count 2 2006.201.06:48:56.35#ibcon#read 5, iclass 12, count 2 2006.201.06:48:56.35#ibcon#about to read 6, iclass 12, count 2 2006.201.06:48:56.35#ibcon#read 6, iclass 12, count 2 2006.201.06:48:56.35#ibcon#end of sib2, iclass 12, count 2 2006.201.06:48:56.35#ibcon#*mode == 0, iclass 12, count 2 2006.201.06:48:56.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.06:48:56.35#ibcon#[27=AT03-04\r\n] 2006.201.06:48:56.35#ibcon#*before write, iclass 12, count 2 2006.201.06:48:56.35#ibcon#enter sib2, iclass 12, count 2 2006.201.06:48:56.35#ibcon#flushed, iclass 12, count 2 2006.201.06:48:56.35#ibcon#about to write, iclass 12, count 2 2006.201.06:48:56.35#ibcon#wrote, iclass 12, count 2 2006.201.06:48:56.35#ibcon#about to read 3, iclass 12, count 2 2006.201.06:48:56.38#ibcon#read 3, iclass 12, count 2 2006.201.06:48:56.38#ibcon#about to read 4, iclass 12, count 2 2006.201.06:48:56.38#ibcon#read 4, iclass 12, count 2 2006.201.06:48:56.38#ibcon#about to read 5, iclass 12, count 2 2006.201.06:48:56.38#ibcon#read 5, iclass 12, count 2 2006.201.06:48:56.38#ibcon#about to read 6, iclass 12, count 2 2006.201.06:48:56.38#ibcon#read 6, iclass 12, count 2 2006.201.06:48:56.38#ibcon#end of sib2, iclass 12, count 2 2006.201.06:48:56.38#ibcon#*after write, iclass 12, count 2 2006.201.06:48:56.38#ibcon#*before return 0, iclass 12, count 2 2006.201.06:48:56.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:56.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.06:48:56.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.06:48:56.38#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:56.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:56.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:56.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:56.50#ibcon#enter wrdev, iclass 12, count 0 2006.201.06:48:56.50#ibcon#first serial, iclass 12, count 0 2006.201.06:48:56.50#ibcon#enter sib2, iclass 12, count 0 2006.201.06:48:56.50#ibcon#flushed, iclass 12, count 0 2006.201.06:48:56.50#ibcon#about to write, iclass 12, count 0 2006.201.06:48:56.50#ibcon#wrote, iclass 12, count 0 2006.201.06:48:56.50#ibcon#about to read 3, iclass 12, count 0 2006.201.06:48:56.52#ibcon#read 3, iclass 12, count 0 2006.201.06:48:56.52#ibcon#about to read 4, iclass 12, count 0 2006.201.06:48:56.52#ibcon#read 4, iclass 12, count 0 2006.201.06:48:56.52#ibcon#about to read 5, iclass 12, count 0 2006.201.06:48:56.52#ibcon#read 5, iclass 12, count 0 2006.201.06:48:56.52#ibcon#about to read 6, iclass 12, count 0 2006.201.06:48:56.52#ibcon#read 6, iclass 12, count 0 2006.201.06:48:56.52#ibcon#end of sib2, iclass 12, count 0 2006.201.06:48:56.52#ibcon#*mode == 0, iclass 12, count 0 2006.201.06:48:56.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.06:48:56.52#ibcon#[27=USB\r\n] 2006.201.06:48:56.52#ibcon#*before write, iclass 12, count 0 2006.201.06:48:56.52#ibcon#enter sib2, iclass 12, count 0 2006.201.06:48:56.52#ibcon#flushed, iclass 12, count 0 2006.201.06:48:56.52#ibcon#about to write, iclass 12, count 0 2006.201.06:48:56.52#ibcon#wrote, iclass 12, count 0 2006.201.06:48:56.52#ibcon#about to read 3, iclass 12, count 0 2006.201.06:48:56.55#ibcon#read 3, iclass 12, count 0 2006.201.06:48:56.55#ibcon#about to read 4, iclass 12, count 0 2006.201.06:48:56.55#ibcon#read 4, iclass 12, count 0 2006.201.06:48:56.55#ibcon#about to read 5, iclass 12, count 0 2006.201.06:48:56.55#ibcon#read 5, iclass 12, count 0 2006.201.06:48:56.55#ibcon#about to read 6, iclass 12, count 0 2006.201.06:48:56.55#ibcon#read 6, iclass 12, count 0 2006.201.06:48:56.55#ibcon#end of sib2, iclass 12, count 0 2006.201.06:48:56.55#ibcon#*after write, iclass 12, count 0 2006.201.06:48:56.55#ibcon#*before return 0, iclass 12, count 0 2006.201.06:48:56.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:56.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.06:48:56.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.06:48:56.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.06:48:56.55$vck44/vblo=4,679.99 2006.201.06:48:56.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.06:48:56.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.06:48:56.55#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:56.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:48:56.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:48:56.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:48:56.55#ibcon#enter wrdev, iclass 15, count 0 2006.201.06:48:56.55#ibcon#first serial, iclass 15, count 0 2006.201.06:48:56.55#ibcon#enter sib2, iclass 15, count 0 2006.201.06:48:56.55#ibcon#flushed, iclass 15, count 0 2006.201.06:48:56.55#ibcon#about to write, iclass 15, count 0 2006.201.06:48:56.55#ibcon#wrote, iclass 15, count 0 2006.201.06:48:56.55#ibcon#about to read 3, iclass 15, count 0 2006.201.06:48:56.57#ibcon#read 3, iclass 15, count 0 2006.201.06:48:56.57#ibcon#about to read 4, iclass 15, count 0 2006.201.06:48:56.57#ibcon#read 4, iclass 15, count 0 2006.201.06:48:56.57#ibcon#about to read 5, iclass 15, count 0 2006.201.06:48:56.57#ibcon#read 5, iclass 15, count 0 2006.201.06:48:56.57#ibcon#about to read 6, iclass 15, count 0 2006.201.06:48:56.57#ibcon#read 6, iclass 15, count 0 2006.201.06:48:56.57#ibcon#end of sib2, iclass 15, count 0 2006.201.06:48:56.57#ibcon#*mode == 0, iclass 15, count 0 2006.201.06:48:56.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.06:48:56.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.06:48:56.57#ibcon#*before write, iclass 15, count 0 2006.201.06:48:56.57#ibcon#enter sib2, iclass 15, count 0 2006.201.06:48:56.57#ibcon#flushed, iclass 15, count 0 2006.201.06:48:56.57#ibcon#about to write, iclass 15, count 0 2006.201.06:48:56.57#ibcon#wrote, iclass 15, count 0 2006.201.06:48:56.57#ibcon#about to read 3, iclass 15, count 0 2006.201.06:48:56.57#abcon#<5=/05 2.6 4.5 23.19 901003.2\r\n> 2006.201.06:48:56.59#abcon#{5=INTERFACE CLEAR} 2006.201.06:48:56.61#ibcon#read 3, iclass 15, count 0 2006.201.06:48:56.61#ibcon#about to read 4, iclass 15, count 0 2006.201.06:48:56.61#ibcon#read 4, iclass 15, count 0 2006.201.06:48:56.61#ibcon#about to read 5, iclass 15, count 0 2006.201.06:48:56.61#ibcon#read 5, iclass 15, count 0 2006.201.06:48:56.61#ibcon#about to read 6, iclass 15, count 0 2006.201.06:48:56.61#ibcon#read 6, iclass 15, count 0 2006.201.06:48:56.61#ibcon#end of sib2, iclass 15, count 0 2006.201.06:48:56.61#ibcon#*after write, iclass 15, count 0 2006.201.06:48:56.61#ibcon#*before return 0, iclass 15, count 0 2006.201.06:48:56.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:48:56.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.06:48:56.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.06:48:56.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.06:48:56.61$vck44/vb=4,5 2006.201.06:48:56.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.06:48:56.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.06:48:56.61#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:56.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:48:56.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:48:56.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:48:56.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:48:56.67#ibcon#enter wrdev, iclass 19, count 2 2006.201.06:48:56.67#ibcon#first serial, iclass 19, count 2 2006.201.06:48:56.67#ibcon#enter sib2, iclass 19, count 2 2006.201.06:48:56.67#ibcon#flushed, iclass 19, count 2 2006.201.06:48:56.67#ibcon#about to write, iclass 19, count 2 2006.201.06:48:56.67#ibcon#wrote, iclass 19, count 2 2006.201.06:48:56.67#ibcon#about to read 3, iclass 19, count 2 2006.201.06:48:56.69#ibcon#read 3, iclass 19, count 2 2006.201.06:48:56.69#ibcon#about to read 4, iclass 19, count 2 2006.201.06:48:56.69#ibcon#read 4, iclass 19, count 2 2006.201.06:48:56.69#ibcon#about to read 5, iclass 19, count 2 2006.201.06:48:56.69#ibcon#read 5, iclass 19, count 2 2006.201.06:48:56.69#ibcon#about to read 6, iclass 19, count 2 2006.201.06:48:56.69#ibcon#read 6, iclass 19, count 2 2006.201.06:48:56.69#ibcon#end of sib2, iclass 19, count 2 2006.201.06:48:56.69#ibcon#*mode == 0, iclass 19, count 2 2006.201.06:48:56.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.06:48:56.69#ibcon#[27=AT04-05\r\n] 2006.201.06:48:56.69#ibcon#*before write, iclass 19, count 2 2006.201.06:48:56.69#ibcon#enter sib2, iclass 19, count 2 2006.201.06:48:56.69#ibcon#flushed, iclass 19, count 2 2006.201.06:48:56.69#ibcon#about to write, iclass 19, count 2 2006.201.06:48:56.69#ibcon#wrote, iclass 19, count 2 2006.201.06:48:56.69#ibcon#about to read 3, iclass 19, count 2 2006.201.06:48:56.72#ibcon#read 3, iclass 19, count 2 2006.201.06:48:56.72#ibcon#about to read 4, iclass 19, count 2 2006.201.06:48:56.72#ibcon#read 4, iclass 19, count 2 2006.201.06:48:56.72#ibcon#about to read 5, iclass 19, count 2 2006.201.06:48:56.72#ibcon#read 5, iclass 19, count 2 2006.201.06:48:56.72#ibcon#about to read 6, iclass 19, count 2 2006.201.06:48:56.72#ibcon#read 6, iclass 19, count 2 2006.201.06:48:56.72#ibcon#end of sib2, iclass 19, count 2 2006.201.06:48:56.72#ibcon#*after write, iclass 19, count 2 2006.201.06:48:56.72#ibcon#*before return 0, iclass 19, count 2 2006.201.06:48:56.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:48:56.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:48:56.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.06:48:56.72#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:56.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:48:56.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:48:56.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:48:56.84#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:48:56.84#ibcon#first serial, iclass 19, count 0 2006.201.06:48:56.84#ibcon#enter sib2, iclass 19, count 0 2006.201.06:48:56.84#ibcon#flushed, iclass 19, count 0 2006.201.06:48:56.84#ibcon#about to write, iclass 19, count 0 2006.201.06:48:56.84#ibcon#wrote, iclass 19, count 0 2006.201.06:48:56.84#ibcon#about to read 3, iclass 19, count 0 2006.201.06:48:56.86#ibcon#read 3, iclass 19, count 0 2006.201.06:48:56.86#ibcon#about to read 4, iclass 19, count 0 2006.201.06:48:56.86#ibcon#read 4, iclass 19, count 0 2006.201.06:48:56.86#ibcon#about to read 5, iclass 19, count 0 2006.201.06:48:56.86#ibcon#read 5, iclass 19, count 0 2006.201.06:48:56.86#ibcon#about to read 6, iclass 19, count 0 2006.201.06:48:56.86#ibcon#read 6, iclass 19, count 0 2006.201.06:48:56.86#ibcon#end of sib2, iclass 19, count 0 2006.201.06:48:56.86#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:48:56.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:48:56.86#ibcon#[27=USB\r\n] 2006.201.06:48:56.86#ibcon#*before write, iclass 19, count 0 2006.201.06:48:56.86#ibcon#enter sib2, iclass 19, count 0 2006.201.06:48:56.86#ibcon#flushed, iclass 19, count 0 2006.201.06:48:56.86#ibcon#about to write, iclass 19, count 0 2006.201.06:48:56.86#ibcon#wrote, iclass 19, count 0 2006.201.06:48:56.86#ibcon#about to read 3, iclass 19, count 0 2006.201.06:48:56.89#ibcon#read 3, iclass 19, count 0 2006.201.06:48:56.89#ibcon#about to read 4, iclass 19, count 0 2006.201.06:48:56.89#ibcon#read 4, iclass 19, count 0 2006.201.06:48:56.89#ibcon#about to read 5, iclass 19, count 0 2006.201.06:48:56.89#ibcon#read 5, iclass 19, count 0 2006.201.06:48:56.89#ibcon#about to read 6, iclass 19, count 0 2006.201.06:48:56.89#ibcon#read 6, iclass 19, count 0 2006.201.06:48:56.89#ibcon#end of sib2, iclass 19, count 0 2006.201.06:48:56.89#ibcon#*after write, iclass 19, count 0 2006.201.06:48:56.89#ibcon#*before return 0, iclass 19, count 0 2006.201.06:48:56.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:48:56.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:48:56.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:48:56.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:48:56.89$vck44/vblo=5,709.99 2006.201.06:48:56.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.06:48:56.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.06:48:56.89#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:56.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:56.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:56.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:56.89#ibcon#enter wrdev, iclass 22, count 0 2006.201.06:48:56.89#ibcon#first serial, iclass 22, count 0 2006.201.06:48:56.89#ibcon#enter sib2, iclass 22, count 0 2006.201.06:48:56.89#ibcon#flushed, iclass 22, count 0 2006.201.06:48:56.89#ibcon#about to write, iclass 22, count 0 2006.201.06:48:56.89#ibcon#wrote, iclass 22, count 0 2006.201.06:48:56.89#ibcon#about to read 3, iclass 22, count 0 2006.201.06:48:56.91#ibcon#read 3, iclass 22, count 0 2006.201.06:48:56.91#ibcon#about to read 4, iclass 22, count 0 2006.201.06:48:56.91#ibcon#read 4, iclass 22, count 0 2006.201.06:48:56.91#ibcon#about to read 5, iclass 22, count 0 2006.201.06:48:56.91#ibcon#read 5, iclass 22, count 0 2006.201.06:48:56.91#ibcon#about to read 6, iclass 22, count 0 2006.201.06:48:56.91#ibcon#read 6, iclass 22, count 0 2006.201.06:48:56.91#ibcon#end of sib2, iclass 22, count 0 2006.201.06:48:56.91#ibcon#*mode == 0, iclass 22, count 0 2006.201.06:48:56.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.06:48:56.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.06:48:56.91#ibcon#*before write, iclass 22, count 0 2006.201.06:48:56.91#ibcon#enter sib2, iclass 22, count 0 2006.201.06:48:56.91#ibcon#flushed, iclass 22, count 0 2006.201.06:48:56.91#ibcon#about to write, iclass 22, count 0 2006.201.06:48:56.91#ibcon#wrote, iclass 22, count 0 2006.201.06:48:56.91#ibcon#about to read 3, iclass 22, count 0 2006.201.06:48:56.95#ibcon#read 3, iclass 22, count 0 2006.201.06:48:56.95#ibcon#about to read 4, iclass 22, count 0 2006.201.06:48:56.95#ibcon#read 4, iclass 22, count 0 2006.201.06:48:56.95#ibcon#about to read 5, iclass 22, count 0 2006.201.06:48:56.95#ibcon#read 5, iclass 22, count 0 2006.201.06:48:56.95#ibcon#about to read 6, iclass 22, count 0 2006.201.06:48:56.95#ibcon#read 6, iclass 22, count 0 2006.201.06:48:56.95#ibcon#end of sib2, iclass 22, count 0 2006.201.06:48:56.95#ibcon#*after write, iclass 22, count 0 2006.201.06:48:56.95#ibcon#*before return 0, iclass 22, count 0 2006.201.06:48:56.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:56.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.06:48:56.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.06:48:56.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.06:48:56.95$vck44/vb=5,4 2006.201.06:48:56.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.06:48:56.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.06:48:56.95#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:56.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:57.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:57.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:57.01#ibcon#enter wrdev, iclass 24, count 2 2006.201.06:48:57.01#ibcon#first serial, iclass 24, count 2 2006.201.06:48:57.01#ibcon#enter sib2, iclass 24, count 2 2006.201.06:48:57.01#ibcon#flushed, iclass 24, count 2 2006.201.06:48:57.01#ibcon#about to write, iclass 24, count 2 2006.201.06:48:57.01#ibcon#wrote, iclass 24, count 2 2006.201.06:48:57.01#ibcon#about to read 3, iclass 24, count 2 2006.201.06:48:57.03#ibcon#read 3, iclass 24, count 2 2006.201.06:48:57.03#ibcon#about to read 4, iclass 24, count 2 2006.201.06:48:57.03#ibcon#read 4, iclass 24, count 2 2006.201.06:48:57.03#ibcon#about to read 5, iclass 24, count 2 2006.201.06:48:57.03#ibcon#read 5, iclass 24, count 2 2006.201.06:48:57.03#ibcon#about to read 6, iclass 24, count 2 2006.201.06:48:57.03#ibcon#read 6, iclass 24, count 2 2006.201.06:48:57.03#ibcon#end of sib2, iclass 24, count 2 2006.201.06:48:57.03#ibcon#*mode == 0, iclass 24, count 2 2006.201.06:48:57.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.06:48:57.03#ibcon#[27=AT05-04\r\n] 2006.201.06:48:57.03#ibcon#*before write, iclass 24, count 2 2006.201.06:48:57.03#ibcon#enter sib2, iclass 24, count 2 2006.201.06:48:57.03#ibcon#flushed, iclass 24, count 2 2006.201.06:48:57.03#ibcon#about to write, iclass 24, count 2 2006.201.06:48:57.03#ibcon#wrote, iclass 24, count 2 2006.201.06:48:57.03#ibcon#about to read 3, iclass 24, count 2 2006.201.06:48:57.06#ibcon#read 3, iclass 24, count 2 2006.201.06:48:57.06#ibcon#about to read 4, iclass 24, count 2 2006.201.06:48:57.06#ibcon#read 4, iclass 24, count 2 2006.201.06:48:57.06#ibcon#about to read 5, iclass 24, count 2 2006.201.06:48:57.06#ibcon#read 5, iclass 24, count 2 2006.201.06:48:57.06#ibcon#about to read 6, iclass 24, count 2 2006.201.06:48:57.06#ibcon#read 6, iclass 24, count 2 2006.201.06:48:57.06#ibcon#end of sib2, iclass 24, count 2 2006.201.06:48:57.06#ibcon#*after write, iclass 24, count 2 2006.201.06:48:57.06#ibcon#*before return 0, iclass 24, count 2 2006.201.06:48:57.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:57.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.06:48:57.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.06:48:57.06#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:57.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:57.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:57.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:57.18#ibcon#enter wrdev, iclass 24, count 0 2006.201.06:48:57.18#ibcon#first serial, iclass 24, count 0 2006.201.06:48:57.18#ibcon#enter sib2, iclass 24, count 0 2006.201.06:48:57.18#ibcon#flushed, iclass 24, count 0 2006.201.06:48:57.18#ibcon#about to write, iclass 24, count 0 2006.201.06:48:57.18#ibcon#wrote, iclass 24, count 0 2006.201.06:48:57.18#ibcon#about to read 3, iclass 24, count 0 2006.201.06:48:57.21#ibcon#read 3, iclass 24, count 0 2006.201.06:48:57.21#ibcon#about to read 4, iclass 24, count 0 2006.201.06:48:57.21#ibcon#read 4, iclass 24, count 0 2006.201.06:48:57.21#ibcon#about to read 5, iclass 24, count 0 2006.201.06:48:57.21#ibcon#read 5, iclass 24, count 0 2006.201.06:48:57.21#ibcon#about to read 6, iclass 24, count 0 2006.201.06:48:57.21#ibcon#read 6, iclass 24, count 0 2006.201.06:48:57.21#ibcon#end of sib2, iclass 24, count 0 2006.201.06:48:57.21#ibcon#*mode == 0, iclass 24, count 0 2006.201.06:48:57.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.06:48:57.21#ibcon#[27=USB\r\n] 2006.201.06:48:57.21#ibcon#*before write, iclass 24, count 0 2006.201.06:48:57.21#ibcon#enter sib2, iclass 24, count 0 2006.201.06:48:57.21#ibcon#flushed, iclass 24, count 0 2006.201.06:48:57.21#ibcon#about to write, iclass 24, count 0 2006.201.06:48:57.21#ibcon#wrote, iclass 24, count 0 2006.201.06:48:57.21#ibcon#about to read 3, iclass 24, count 0 2006.201.06:48:57.24#ibcon#read 3, iclass 24, count 0 2006.201.06:48:57.24#ibcon#about to read 4, iclass 24, count 0 2006.201.06:48:57.24#ibcon#read 4, iclass 24, count 0 2006.201.06:48:57.24#ibcon#about to read 5, iclass 24, count 0 2006.201.06:48:57.24#ibcon#read 5, iclass 24, count 0 2006.201.06:48:57.24#ibcon#about to read 6, iclass 24, count 0 2006.201.06:48:57.24#ibcon#read 6, iclass 24, count 0 2006.201.06:48:57.24#ibcon#end of sib2, iclass 24, count 0 2006.201.06:48:57.24#ibcon#*after write, iclass 24, count 0 2006.201.06:48:57.24#ibcon#*before return 0, iclass 24, count 0 2006.201.06:48:57.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:57.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.06:48:57.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.06:48:57.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.06:48:57.24$vck44/vblo=6,719.99 2006.201.06:48:57.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.06:48:57.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.06:48:57.24#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:57.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:57.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:57.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:57.24#ibcon#enter wrdev, iclass 26, count 0 2006.201.06:48:57.24#ibcon#first serial, iclass 26, count 0 2006.201.06:48:57.24#ibcon#enter sib2, iclass 26, count 0 2006.201.06:48:57.24#ibcon#flushed, iclass 26, count 0 2006.201.06:48:57.24#ibcon#about to write, iclass 26, count 0 2006.201.06:48:57.24#ibcon#wrote, iclass 26, count 0 2006.201.06:48:57.24#ibcon#about to read 3, iclass 26, count 0 2006.201.06:48:57.26#ibcon#read 3, iclass 26, count 0 2006.201.06:48:57.26#ibcon#about to read 4, iclass 26, count 0 2006.201.06:48:57.26#ibcon#read 4, iclass 26, count 0 2006.201.06:48:57.26#ibcon#about to read 5, iclass 26, count 0 2006.201.06:48:57.26#ibcon#read 5, iclass 26, count 0 2006.201.06:48:57.26#ibcon#about to read 6, iclass 26, count 0 2006.201.06:48:57.26#ibcon#read 6, iclass 26, count 0 2006.201.06:48:57.26#ibcon#end of sib2, iclass 26, count 0 2006.201.06:48:57.26#ibcon#*mode == 0, iclass 26, count 0 2006.201.06:48:57.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.06:48:57.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.06:48:57.26#ibcon#*before write, iclass 26, count 0 2006.201.06:48:57.26#ibcon#enter sib2, iclass 26, count 0 2006.201.06:48:57.26#ibcon#flushed, iclass 26, count 0 2006.201.06:48:57.26#ibcon#about to write, iclass 26, count 0 2006.201.06:48:57.26#ibcon#wrote, iclass 26, count 0 2006.201.06:48:57.26#ibcon#about to read 3, iclass 26, count 0 2006.201.06:48:57.30#ibcon#read 3, iclass 26, count 0 2006.201.06:48:57.30#ibcon#about to read 4, iclass 26, count 0 2006.201.06:48:57.30#ibcon#read 4, iclass 26, count 0 2006.201.06:48:57.30#ibcon#about to read 5, iclass 26, count 0 2006.201.06:48:57.30#ibcon#read 5, iclass 26, count 0 2006.201.06:48:57.30#ibcon#about to read 6, iclass 26, count 0 2006.201.06:48:57.30#ibcon#read 6, iclass 26, count 0 2006.201.06:48:57.30#ibcon#end of sib2, iclass 26, count 0 2006.201.06:48:57.30#ibcon#*after write, iclass 26, count 0 2006.201.06:48:57.30#ibcon#*before return 0, iclass 26, count 0 2006.201.06:48:57.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:57.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.06:48:57.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.06:48:57.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.06:48:57.30$vck44/vb=6,4 2006.201.06:48:57.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.06:48:57.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.06:48:57.30#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:57.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:57.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:57.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:57.36#ibcon#enter wrdev, iclass 28, count 2 2006.201.06:48:57.36#ibcon#first serial, iclass 28, count 2 2006.201.06:48:57.36#ibcon#enter sib2, iclass 28, count 2 2006.201.06:48:57.36#ibcon#flushed, iclass 28, count 2 2006.201.06:48:57.36#ibcon#about to write, iclass 28, count 2 2006.201.06:48:57.36#ibcon#wrote, iclass 28, count 2 2006.201.06:48:57.36#ibcon#about to read 3, iclass 28, count 2 2006.201.06:48:57.38#ibcon#read 3, iclass 28, count 2 2006.201.06:48:57.38#ibcon#about to read 4, iclass 28, count 2 2006.201.06:48:57.38#ibcon#read 4, iclass 28, count 2 2006.201.06:48:57.38#ibcon#about to read 5, iclass 28, count 2 2006.201.06:48:57.38#ibcon#read 5, iclass 28, count 2 2006.201.06:48:57.38#ibcon#about to read 6, iclass 28, count 2 2006.201.06:48:57.38#ibcon#read 6, iclass 28, count 2 2006.201.06:48:57.38#ibcon#end of sib2, iclass 28, count 2 2006.201.06:48:57.38#ibcon#*mode == 0, iclass 28, count 2 2006.201.06:48:57.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.06:48:57.38#ibcon#[27=AT06-04\r\n] 2006.201.06:48:57.38#ibcon#*before write, iclass 28, count 2 2006.201.06:48:57.38#ibcon#enter sib2, iclass 28, count 2 2006.201.06:48:57.38#ibcon#flushed, iclass 28, count 2 2006.201.06:48:57.38#ibcon#about to write, iclass 28, count 2 2006.201.06:48:57.38#ibcon#wrote, iclass 28, count 2 2006.201.06:48:57.38#ibcon#about to read 3, iclass 28, count 2 2006.201.06:48:57.41#ibcon#read 3, iclass 28, count 2 2006.201.06:48:57.41#ibcon#about to read 4, iclass 28, count 2 2006.201.06:48:57.41#ibcon#read 4, iclass 28, count 2 2006.201.06:48:57.41#ibcon#about to read 5, iclass 28, count 2 2006.201.06:48:57.41#ibcon#read 5, iclass 28, count 2 2006.201.06:48:57.41#ibcon#about to read 6, iclass 28, count 2 2006.201.06:48:57.41#ibcon#read 6, iclass 28, count 2 2006.201.06:48:57.41#ibcon#end of sib2, iclass 28, count 2 2006.201.06:48:57.41#ibcon#*after write, iclass 28, count 2 2006.201.06:48:57.41#ibcon#*before return 0, iclass 28, count 2 2006.201.06:48:57.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:57.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.06:48:57.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.06:48:57.41#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:57.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:57.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:57.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:57.53#ibcon#enter wrdev, iclass 28, count 0 2006.201.06:48:57.53#ibcon#first serial, iclass 28, count 0 2006.201.06:48:57.53#ibcon#enter sib2, iclass 28, count 0 2006.201.06:48:57.53#ibcon#flushed, iclass 28, count 0 2006.201.06:48:57.53#ibcon#about to write, iclass 28, count 0 2006.201.06:48:57.53#ibcon#wrote, iclass 28, count 0 2006.201.06:48:57.53#ibcon#about to read 3, iclass 28, count 0 2006.201.06:48:57.55#ibcon#read 3, iclass 28, count 0 2006.201.06:48:57.55#ibcon#about to read 4, iclass 28, count 0 2006.201.06:48:57.55#ibcon#read 4, iclass 28, count 0 2006.201.06:48:57.55#ibcon#about to read 5, iclass 28, count 0 2006.201.06:48:57.55#ibcon#read 5, iclass 28, count 0 2006.201.06:48:57.55#ibcon#about to read 6, iclass 28, count 0 2006.201.06:48:57.55#ibcon#read 6, iclass 28, count 0 2006.201.06:48:57.55#ibcon#end of sib2, iclass 28, count 0 2006.201.06:48:57.55#ibcon#*mode == 0, iclass 28, count 0 2006.201.06:48:57.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.06:48:57.55#ibcon#[27=USB\r\n] 2006.201.06:48:57.55#ibcon#*before write, iclass 28, count 0 2006.201.06:48:57.55#ibcon#enter sib2, iclass 28, count 0 2006.201.06:48:57.55#ibcon#flushed, iclass 28, count 0 2006.201.06:48:57.55#ibcon#about to write, iclass 28, count 0 2006.201.06:48:57.55#ibcon#wrote, iclass 28, count 0 2006.201.06:48:57.55#ibcon#about to read 3, iclass 28, count 0 2006.201.06:48:57.58#ibcon#read 3, iclass 28, count 0 2006.201.06:48:57.58#ibcon#about to read 4, iclass 28, count 0 2006.201.06:48:57.58#ibcon#read 4, iclass 28, count 0 2006.201.06:48:57.58#ibcon#about to read 5, iclass 28, count 0 2006.201.06:48:57.58#ibcon#read 5, iclass 28, count 0 2006.201.06:48:57.58#ibcon#about to read 6, iclass 28, count 0 2006.201.06:48:57.58#ibcon#read 6, iclass 28, count 0 2006.201.06:48:57.58#ibcon#end of sib2, iclass 28, count 0 2006.201.06:48:57.58#ibcon#*after write, iclass 28, count 0 2006.201.06:48:57.58#ibcon#*before return 0, iclass 28, count 0 2006.201.06:48:57.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:57.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.06:48:57.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.06:48:57.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.06:48:57.58$vck44/vblo=7,734.99 2006.201.06:48:57.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.06:48:57.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.06:48:57.58#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:57.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:57.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:57.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:57.58#ibcon#enter wrdev, iclass 30, count 0 2006.201.06:48:57.58#ibcon#first serial, iclass 30, count 0 2006.201.06:48:57.58#ibcon#enter sib2, iclass 30, count 0 2006.201.06:48:57.58#ibcon#flushed, iclass 30, count 0 2006.201.06:48:57.58#ibcon#about to write, iclass 30, count 0 2006.201.06:48:57.58#ibcon#wrote, iclass 30, count 0 2006.201.06:48:57.58#ibcon#about to read 3, iclass 30, count 0 2006.201.06:48:57.60#ibcon#read 3, iclass 30, count 0 2006.201.06:48:57.60#ibcon#about to read 4, iclass 30, count 0 2006.201.06:48:57.60#ibcon#read 4, iclass 30, count 0 2006.201.06:48:57.60#ibcon#about to read 5, iclass 30, count 0 2006.201.06:48:57.60#ibcon#read 5, iclass 30, count 0 2006.201.06:48:57.60#ibcon#about to read 6, iclass 30, count 0 2006.201.06:48:57.60#ibcon#read 6, iclass 30, count 0 2006.201.06:48:57.60#ibcon#end of sib2, iclass 30, count 0 2006.201.06:48:57.60#ibcon#*mode == 0, iclass 30, count 0 2006.201.06:48:57.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.06:48:57.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.06:48:57.60#ibcon#*before write, iclass 30, count 0 2006.201.06:48:57.60#ibcon#enter sib2, iclass 30, count 0 2006.201.06:48:57.60#ibcon#flushed, iclass 30, count 0 2006.201.06:48:57.60#ibcon#about to write, iclass 30, count 0 2006.201.06:48:57.60#ibcon#wrote, iclass 30, count 0 2006.201.06:48:57.60#ibcon#about to read 3, iclass 30, count 0 2006.201.06:48:57.64#ibcon#read 3, iclass 30, count 0 2006.201.06:48:57.64#ibcon#about to read 4, iclass 30, count 0 2006.201.06:48:57.64#ibcon#read 4, iclass 30, count 0 2006.201.06:48:57.64#ibcon#about to read 5, iclass 30, count 0 2006.201.06:48:57.64#ibcon#read 5, iclass 30, count 0 2006.201.06:48:57.64#ibcon#about to read 6, iclass 30, count 0 2006.201.06:48:57.64#ibcon#read 6, iclass 30, count 0 2006.201.06:48:57.64#ibcon#end of sib2, iclass 30, count 0 2006.201.06:48:57.64#ibcon#*after write, iclass 30, count 0 2006.201.06:48:57.64#ibcon#*before return 0, iclass 30, count 0 2006.201.06:48:57.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:57.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.06:48:57.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.06:48:57.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.06:48:57.64$vck44/vb=7,4 2006.201.06:48:57.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.06:48:57.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.06:48:57.64#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:57.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:57.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:57.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:57.70#ibcon#enter wrdev, iclass 32, count 2 2006.201.06:48:57.70#ibcon#first serial, iclass 32, count 2 2006.201.06:48:57.70#ibcon#enter sib2, iclass 32, count 2 2006.201.06:48:57.70#ibcon#flushed, iclass 32, count 2 2006.201.06:48:57.70#ibcon#about to write, iclass 32, count 2 2006.201.06:48:57.70#ibcon#wrote, iclass 32, count 2 2006.201.06:48:57.70#ibcon#about to read 3, iclass 32, count 2 2006.201.06:48:57.72#ibcon#read 3, iclass 32, count 2 2006.201.06:48:57.72#ibcon#about to read 4, iclass 32, count 2 2006.201.06:48:57.72#ibcon#read 4, iclass 32, count 2 2006.201.06:48:57.72#ibcon#about to read 5, iclass 32, count 2 2006.201.06:48:57.72#ibcon#read 5, iclass 32, count 2 2006.201.06:48:57.72#ibcon#about to read 6, iclass 32, count 2 2006.201.06:48:57.72#ibcon#read 6, iclass 32, count 2 2006.201.06:48:57.72#ibcon#end of sib2, iclass 32, count 2 2006.201.06:48:57.72#ibcon#*mode == 0, iclass 32, count 2 2006.201.06:48:57.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.06:48:57.72#ibcon#[27=AT07-04\r\n] 2006.201.06:48:57.72#ibcon#*before write, iclass 32, count 2 2006.201.06:48:57.72#ibcon#enter sib2, iclass 32, count 2 2006.201.06:48:57.72#ibcon#flushed, iclass 32, count 2 2006.201.06:48:57.72#ibcon#about to write, iclass 32, count 2 2006.201.06:48:57.72#ibcon#wrote, iclass 32, count 2 2006.201.06:48:57.72#ibcon#about to read 3, iclass 32, count 2 2006.201.06:48:57.75#ibcon#read 3, iclass 32, count 2 2006.201.06:48:57.75#ibcon#about to read 4, iclass 32, count 2 2006.201.06:48:57.75#ibcon#read 4, iclass 32, count 2 2006.201.06:48:57.75#ibcon#about to read 5, iclass 32, count 2 2006.201.06:48:57.75#ibcon#read 5, iclass 32, count 2 2006.201.06:48:57.75#ibcon#about to read 6, iclass 32, count 2 2006.201.06:48:57.75#ibcon#read 6, iclass 32, count 2 2006.201.06:48:57.75#ibcon#end of sib2, iclass 32, count 2 2006.201.06:48:57.75#ibcon#*after write, iclass 32, count 2 2006.201.06:48:57.75#ibcon#*before return 0, iclass 32, count 2 2006.201.06:48:57.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:57.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.06:48:57.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.06:48:57.75#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:57.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:57.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:57.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:57.87#ibcon#enter wrdev, iclass 32, count 0 2006.201.06:48:57.87#ibcon#first serial, iclass 32, count 0 2006.201.06:48:57.87#ibcon#enter sib2, iclass 32, count 0 2006.201.06:48:57.87#ibcon#flushed, iclass 32, count 0 2006.201.06:48:57.87#ibcon#about to write, iclass 32, count 0 2006.201.06:48:57.87#ibcon#wrote, iclass 32, count 0 2006.201.06:48:57.87#ibcon#about to read 3, iclass 32, count 0 2006.201.06:48:57.89#ibcon#read 3, iclass 32, count 0 2006.201.06:48:57.89#ibcon#about to read 4, iclass 32, count 0 2006.201.06:48:57.89#ibcon#read 4, iclass 32, count 0 2006.201.06:48:57.89#ibcon#about to read 5, iclass 32, count 0 2006.201.06:48:57.89#ibcon#read 5, iclass 32, count 0 2006.201.06:48:57.89#ibcon#about to read 6, iclass 32, count 0 2006.201.06:48:57.89#ibcon#read 6, iclass 32, count 0 2006.201.06:48:57.89#ibcon#end of sib2, iclass 32, count 0 2006.201.06:48:57.89#ibcon#*mode == 0, iclass 32, count 0 2006.201.06:48:57.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.06:48:57.89#ibcon#[27=USB\r\n] 2006.201.06:48:57.89#ibcon#*before write, iclass 32, count 0 2006.201.06:48:57.89#ibcon#enter sib2, iclass 32, count 0 2006.201.06:48:57.89#ibcon#flushed, iclass 32, count 0 2006.201.06:48:57.89#ibcon#about to write, iclass 32, count 0 2006.201.06:48:57.89#ibcon#wrote, iclass 32, count 0 2006.201.06:48:57.89#ibcon#about to read 3, iclass 32, count 0 2006.201.06:48:57.92#ibcon#read 3, iclass 32, count 0 2006.201.06:48:57.92#ibcon#about to read 4, iclass 32, count 0 2006.201.06:48:57.92#ibcon#read 4, iclass 32, count 0 2006.201.06:48:57.92#ibcon#about to read 5, iclass 32, count 0 2006.201.06:48:57.92#ibcon#read 5, iclass 32, count 0 2006.201.06:48:57.92#ibcon#about to read 6, iclass 32, count 0 2006.201.06:48:57.92#ibcon#read 6, iclass 32, count 0 2006.201.06:48:57.92#ibcon#end of sib2, iclass 32, count 0 2006.201.06:48:57.92#ibcon#*after write, iclass 32, count 0 2006.201.06:48:57.92#ibcon#*before return 0, iclass 32, count 0 2006.201.06:48:57.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:57.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.06:48:57.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.06:48:57.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.06:48:57.92$vck44/vblo=8,744.99 2006.201.06:48:57.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.06:48:57.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.06:48:57.92#ibcon#ireg 17 cls_cnt 0 2006.201.06:48:57.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:57.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:57.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:57.92#ibcon#enter wrdev, iclass 34, count 0 2006.201.06:48:57.92#ibcon#first serial, iclass 34, count 0 2006.201.06:48:57.92#ibcon#enter sib2, iclass 34, count 0 2006.201.06:48:57.92#ibcon#flushed, iclass 34, count 0 2006.201.06:48:57.92#ibcon#about to write, iclass 34, count 0 2006.201.06:48:57.92#ibcon#wrote, iclass 34, count 0 2006.201.06:48:57.92#ibcon#about to read 3, iclass 34, count 0 2006.201.06:48:57.94#ibcon#read 3, iclass 34, count 0 2006.201.06:48:57.94#ibcon#about to read 4, iclass 34, count 0 2006.201.06:48:57.94#ibcon#read 4, iclass 34, count 0 2006.201.06:48:57.94#ibcon#about to read 5, iclass 34, count 0 2006.201.06:48:57.94#ibcon#read 5, iclass 34, count 0 2006.201.06:48:57.94#ibcon#about to read 6, iclass 34, count 0 2006.201.06:48:57.94#ibcon#read 6, iclass 34, count 0 2006.201.06:48:57.94#ibcon#end of sib2, iclass 34, count 0 2006.201.06:48:57.94#ibcon#*mode == 0, iclass 34, count 0 2006.201.06:48:57.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.06:48:57.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.06:48:57.94#ibcon#*before write, iclass 34, count 0 2006.201.06:48:57.94#ibcon#enter sib2, iclass 34, count 0 2006.201.06:48:57.94#ibcon#flushed, iclass 34, count 0 2006.201.06:48:57.94#ibcon#about to write, iclass 34, count 0 2006.201.06:48:57.94#ibcon#wrote, iclass 34, count 0 2006.201.06:48:57.94#ibcon#about to read 3, iclass 34, count 0 2006.201.06:48:57.99#ibcon#read 3, iclass 34, count 0 2006.201.06:48:57.99#ibcon#about to read 4, iclass 34, count 0 2006.201.06:48:57.99#ibcon#read 4, iclass 34, count 0 2006.201.06:48:57.99#ibcon#about to read 5, iclass 34, count 0 2006.201.06:48:57.99#ibcon#read 5, iclass 34, count 0 2006.201.06:48:57.99#ibcon#about to read 6, iclass 34, count 0 2006.201.06:48:57.99#ibcon#read 6, iclass 34, count 0 2006.201.06:48:57.99#ibcon#end of sib2, iclass 34, count 0 2006.201.06:48:57.99#ibcon#*after write, iclass 34, count 0 2006.201.06:48:57.99#ibcon#*before return 0, iclass 34, count 0 2006.201.06:48:57.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:57.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.06:48:57.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.06:48:57.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.06:48:57.99$vck44/vb=8,4 2006.201.06:48:57.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.06:48:57.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.06:48:57.99#ibcon#ireg 11 cls_cnt 2 2006.201.06:48:57.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:58.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:58.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:58.04#ibcon#enter wrdev, iclass 36, count 2 2006.201.06:48:58.04#ibcon#first serial, iclass 36, count 2 2006.201.06:48:58.04#ibcon#enter sib2, iclass 36, count 2 2006.201.06:48:58.04#ibcon#flushed, iclass 36, count 2 2006.201.06:48:58.04#ibcon#about to write, iclass 36, count 2 2006.201.06:48:58.04#ibcon#wrote, iclass 36, count 2 2006.201.06:48:58.04#ibcon#about to read 3, iclass 36, count 2 2006.201.06:48:58.06#ibcon#read 3, iclass 36, count 2 2006.201.06:48:58.06#ibcon#about to read 4, iclass 36, count 2 2006.201.06:48:58.06#ibcon#read 4, iclass 36, count 2 2006.201.06:48:58.06#ibcon#about to read 5, iclass 36, count 2 2006.201.06:48:58.06#ibcon#read 5, iclass 36, count 2 2006.201.06:48:58.06#ibcon#about to read 6, iclass 36, count 2 2006.201.06:48:58.06#ibcon#read 6, iclass 36, count 2 2006.201.06:48:58.06#ibcon#end of sib2, iclass 36, count 2 2006.201.06:48:58.06#ibcon#*mode == 0, iclass 36, count 2 2006.201.06:48:58.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.06:48:58.06#ibcon#[27=AT08-04\r\n] 2006.201.06:48:58.06#ibcon#*before write, iclass 36, count 2 2006.201.06:48:58.06#ibcon#enter sib2, iclass 36, count 2 2006.201.06:48:58.06#ibcon#flushed, iclass 36, count 2 2006.201.06:48:58.06#ibcon#about to write, iclass 36, count 2 2006.201.06:48:58.06#ibcon#wrote, iclass 36, count 2 2006.201.06:48:58.06#ibcon#about to read 3, iclass 36, count 2 2006.201.06:48:58.09#ibcon#read 3, iclass 36, count 2 2006.201.06:48:58.09#ibcon#about to read 4, iclass 36, count 2 2006.201.06:48:58.09#ibcon#read 4, iclass 36, count 2 2006.201.06:48:58.09#ibcon#about to read 5, iclass 36, count 2 2006.201.06:48:58.09#ibcon#read 5, iclass 36, count 2 2006.201.06:48:58.09#ibcon#about to read 6, iclass 36, count 2 2006.201.06:48:58.09#ibcon#read 6, iclass 36, count 2 2006.201.06:48:58.09#ibcon#end of sib2, iclass 36, count 2 2006.201.06:48:58.09#ibcon#*after write, iclass 36, count 2 2006.201.06:48:58.09#ibcon#*before return 0, iclass 36, count 2 2006.201.06:48:58.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:58.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.06:48:58.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.06:48:58.09#ibcon#ireg 7 cls_cnt 0 2006.201.06:48:58.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:58.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:58.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:58.21#ibcon#enter wrdev, iclass 36, count 0 2006.201.06:48:58.21#ibcon#first serial, iclass 36, count 0 2006.201.06:48:58.21#ibcon#enter sib2, iclass 36, count 0 2006.201.06:48:58.21#ibcon#flushed, iclass 36, count 0 2006.201.06:48:58.21#ibcon#about to write, iclass 36, count 0 2006.201.06:48:58.21#ibcon#wrote, iclass 36, count 0 2006.201.06:48:58.21#ibcon#about to read 3, iclass 36, count 0 2006.201.06:48:58.23#ibcon#read 3, iclass 36, count 0 2006.201.06:48:58.23#ibcon#about to read 4, iclass 36, count 0 2006.201.06:48:58.23#ibcon#read 4, iclass 36, count 0 2006.201.06:48:58.23#ibcon#about to read 5, iclass 36, count 0 2006.201.06:48:58.23#ibcon#read 5, iclass 36, count 0 2006.201.06:48:58.23#ibcon#about to read 6, iclass 36, count 0 2006.201.06:48:58.23#ibcon#read 6, iclass 36, count 0 2006.201.06:48:58.23#ibcon#end of sib2, iclass 36, count 0 2006.201.06:48:58.23#ibcon#*mode == 0, iclass 36, count 0 2006.201.06:48:58.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.06:48:58.23#ibcon#[27=USB\r\n] 2006.201.06:48:58.23#ibcon#*before write, iclass 36, count 0 2006.201.06:48:58.23#ibcon#enter sib2, iclass 36, count 0 2006.201.06:48:58.23#ibcon#flushed, iclass 36, count 0 2006.201.06:48:58.23#ibcon#about to write, iclass 36, count 0 2006.201.06:48:58.23#ibcon#wrote, iclass 36, count 0 2006.201.06:48:58.23#ibcon#about to read 3, iclass 36, count 0 2006.201.06:48:58.26#ibcon#read 3, iclass 36, count 0 2006.201.06:48:58.26#ibcon#about to read 4, iclass 36, count 0 2006.201.06:48:58.26#ibcon#read 4, iclass 36, count 0 2006.201.06:48:58.26#ibcon#about to read 5, iclass 36, count 0 2006.201.06:48:58.26#ibcon#read 5, iclass 36, count 0 2006.201.06:48:58.26#ibcon#about to read 6, iclass 36, count 0 2006.201.06:48:58.26#ibcon#read 6, iclass 36, count 0 2006.201.06:48:58.26#ibcon#end of sib2, iclass 36, count 0 2006.201.06:48:58.26#ibcon#*after write, iclass 36, count 0 2006.201.06:48:58.26#ibcon#*before return 0, iclass 36, count 0 2006.201.06:48:58.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:58.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.06:48:58.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.06:48:58.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.06:48:58.26$vck44/vabw=wide 2006.201.06:48:58.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.06:48:58.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.06:48:58.26#ibcon#ireg 8 cls_cnt 0 2006.201.06:48:58.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:58.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:58.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:58.26#ibcon#enter wrdev, iclass 38, count 0 2006.201.06:48:58.26#ibcon#first serial, iclass 38, count 0 2006.201.06:48:58.26#ibcon#enter sib2, iclass 38, count 0 2006.201.06:48:58.26#ibcon#flushed, iclass 38, count 0 2006.201.06:48:58.26#ibcon#about to write, iclass 38, count 0 2006.201.06:48:58.26#ibcon#wrote, iclass 38, count 0 2006.201.06:48:58.26#ibcon#about to read 3, iclass 38, count 0 2006.201.06:48:58.28#ibcon#read 3, iclass 38, count 0 2006.201.06:48:58.28#ibcon#about to read 4, iclass 38, count 0 2006.201.06:48:58.28#ibcon#read 4, iclass 38, count 0 2006.201.06:48:58.28#ibcon#about to read 5, iclass 38, count 0 2006.201.06:48:58.28#ibcon#read 5, iclass 38, count 0 2006.201.06:48:58.28#ibcon#about to read 6, iclass 38, count 0 2006.201.06:48:58.28#ibcon#read 6, iclass 38, count 0 2006.201.06:48:58.28#ibcon#end of sib2, iclass 38, count 0 2006.201.06:48:58.28#ibcon#*mode == 0, iclass 38, count 0 2006.201.06:48:58.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.06:48:58.28#ibcon#[25=BW32\r\n] 2006.201.06:48:58.28#ibcon#*before write, iclass 38, count 0 2006.201.06:48:58.28#ibcon#enter sib2, iclass 38, count 0 2006.201.06:48:58.28#ibcon#flushed, iclass 38, count 0 2006.201.06:48:58.28#ibcon#about to write, iclass 38, count 0 2006.201.06:48:58.28#ibcon#wrote, iclass 38, count 0 2006.201.06:48:58.28#ibcon#about to read 3, iclass 38, count 0 2006.201.06:48:58.31#ibcon#read 3, iclass 38, count 0 2006.201.06:48:58.31#ibcon#about to read 4, iclass 38, count 0 2006.201.06:48:58.31#ibcon#read 4, iclass 38, count 0 2006.201.06:48:58.31#ibcon#about to read 5, iclass 38, count 0 2006.201.06:48:58.31#ibcon#read 5, iclass 38, count 0 2006.201.06:48:58.31#ibcon#about to read 6, iclass 38, count 0 2006.201.06:48:58.31#ibcon#read 6, iclass 38, count 0 2006.201.06:48:58.31#ibcon#end of sib2, iclass 38, count 0 2006.201.06:48:58.31#ibcon#*after write, iclass 38, count 0 2006.201.06:48:58.31#ibcon#*before return 0, iclass 38, count 0 2006.201.06:48:58.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:58.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.06:48:58.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.06:48:58.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.06:48:58.31$vck44/vbbw=wide 2006.201.06:48:58.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.06:48:58.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.06:48:58.31#ibcon#ireg 8 cls_cnt 0 2006.201.06:48:58.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:48:58.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:48:58.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:48:58.38#ibcon#enter wrdev, iclass 40, count 0 2006.201.06:48:58.38#ibcon#first serial, iclass 40, count 0 2006.201.06:48:58.38#ibcon#enter sib2, iclass 40, count 0 2006.201.06:48:58.38#ibcon#flushed, iclass 40, count 0 2006.201.06:48:58.38#ibcon#about to write, iclass 40, count 0 2006.201.06:48:58.38#ibcon#wrote, iclass 40, count 0 2006.201.06:48:58.38#ibcon#about to read 3, iclass 40, count 0 2006.201.06:48:58.40#ibcon#read 3, iclass 40, count 0 2006.201.06:48:58.40#ibcon#about to read 4, iclass 40, count 0 2006.201.06:48:58.40#ibcon#read 4, iclass 40, count 0 2006.201.06:48:58.40#ibcon#about to read 5, iclass 40, count 0 2006.201.06:48:58.40#ibcon#read 5, iclass 40, count 0 2006.201.06:48:58.40#ibcon#about to read 6, iclass 40, count 0 2006.201.06:48:58.40#ibcon#read 6, iclass 40, count 0 2006.201.06:48:58.40#ibcon#end of sib2, iclass 40, count 0 2006.201.06:48:58.40#ibcon#*mode == 0, iclass 40, count 0 2006.201.06:48:58.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.06:48:58.40#ibcon#[27=BW32\r\n] 2006.201.06:48:58.40#ibcon#*before write, iclass 40, count 0 2006.201.06:48:58.40#ibcon#enter sib2, iclass 40, count 0 2006.201.06:48:58.40#ibcon#flushed, iclass 40, count 0 2006.201.06:48:58.40#ibcon#about to write, iclass 40, count 0 2006.201.06:48:58.40#ibcon#wrote, iclass 40, count 0 2006.201.06:48:58.40#ibcon#about to read 3, iclass 40, count 0 2006.201.06:48:58.43#ibcon#read 3, iclass 40, count 0 2006.201.06:48:58.43#ibcon#about to read 4, iclass 40, count 0 2006.201.06:48:58.43#ibcon#read 4, iclass 40, count 0 2006.201.06:48:58.43#ibcon#about to read 5, iclass 40, count 0 2006.201.06:48:58.43#ibcon#read 5, iclass 40, count 0 2006.201.06:48:58.43#ibcon#about to read 6, iclass 40, count 0 2006.201.06:48:58.43#ibcon#read 6, iclass 40, count 0 2006.201.06:48:58.43#ibcon#end of sib2, iclass 40, count 0 2006.201.06:48:58.43#ibcon#*after write, iclass 40, count 0 2006.201.06:48:58.43#ibcon#*before return 0, iclass 40, count 0 2006.201.06:48:58.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:48:58.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.06:48:58.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.06:48:58.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.06:48:58.43$setupk4/ifdk4 2006.201.06:48:58.43$ifdk4/lo= 2006.201.06:48:58.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.06:48:58.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.06:48:58.43$ifdk4/patch= 2006.201.06:48:58.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.06:48:58.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.06:48:58.43$setupk4/!*+20s 2006.201.06:49:06.74#abcon#<5=/05 2.6 4.5 23.19 901003.2\r\n> 2006.201.06:49:06.76#abcon#{5=INTERFACE CLEAR} 2006.201.06:49:06.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:49:12.88$setupk4/"tpicd 2006.201.06:49:12.88$setupk4/echo=off 2006.201.06:49:12.88$setupk4/xlog=off 2006.201.06:49:12.88:!2006.201.06:55:47 2006.201.06:49:21.14#trakl#Source acquired 2006.201.06:49:22.14#flagr#flagr/antenna,acquired 2006.201.06:55:47.00:preob 2006.201.06:55:47.14/onsource/TRACKING 2006.201.06:55:47.14:!2006.201.06:55:57 2006.201.06:55:57.00:"tape 2006.201.06:55:57.00:"st=record 2006.201.06:55:57.00:data_valid=on 2006.201.06:55:57.00:midob 2006.201.06:55:58.14/onsource/TRACKING 2006.201.06:55:58.14/wx/23.20,1003.2,89 2006.201.06:55:58.31/cable/+6.4654E-03 2006.201.06:55:59.40/va/01,08,usb,yes,34,37 2006.201.06:55:59.40/va/02,07,usb,yes,37,38 2006.201.06:55:59.40/va/03,08,usb,yes,33,35 2006.201.06:55:59.40/va/04,07,usb,yes,38,40 2006.201.06:55:59.40/va/05,04,usb,yes,34,34 2006.201.06:55:59.40/va/06,05,usb,yes,34,34 2006.201.06:55:59.40/va/07,05,usb,yes,33,34 2006.201.06:55:59.40/va/08,04,usb,yes,33,39 2006.201.06:55:59.63/valo/01,524.99,yes,locked 2006.201.06:55:59.63/valo/02,534.99,yes,locked 2006.201.06:55:59.63/valo/03,564.99,yes,locked 2006.201.06:55:59.63/valo/04,624.99,yes,locked 2006.201.06:55:59.63/valo/05,734.99,yes,locked 2006.201.06:55:59.63/valo/06,814.99,yes,locked 2006.201.06:55:59.63/valo/07,864.99,yes,locked 2006.201.06:55:59.63/valo/08,884.99,yes,locked 2006.201.06:56:00.72/vb/01,04,usb,yes,32,30 2006.201.06:56:00.72/vb/02,05,usb,yes,30,30 2006.201.06:56:00.72/vb/03,04,usb,yes,31,35 2006.201.06:56:00.72/vb/04,05,usb,yes,32,31 2006.201.06:56:00.72/vb/05,04,usb,yes,28,31 2006.201.06:56:00.72/vb/06,04,usb,yes,33,29 2006.201.06:56:00.72/vb/07,04,usb,yes,33,33 2006.201.06:56:00.72/vb/08,04,usb,yes,30,34 2006.201.06:56:00.96/vblo/01,629.99,yes,locked 2006.201.06:56:00.96/vblo/02,634.99,yes,locked 2006.201.06:56:00.96/vblo/03,649.99,yes,locked 2006.201.06:56:00.96/vblo/04,679.99,yes,locked 2006.201.06:56:00.96/vblo/05,709.99,yes,locked 2006.201.06:56:00.96/vblo/06,719.99,yes,locked 2006.201.06:56:00.96/vblo/07,734.99,yes,locked 2006.201.06:56:00.96/vblo/08,744.99,yes,locked 2006.201.06:56:01.11/vabw/8 2006.201.06:56:01.26/vbbw/8 2006.201.06:56:01.35/xfe/off,on,15.2 2006.201.06:56:01.73/ifatt/23,28,28,28 2006.201.06:56:02.05/fmout-gps/S +4.54E-07 2006.201.06:56:02.12:!2006.201.06:58:07 2006.201.06:58:07.00:data_valid=off 2006.201.06:58:07.00:"et 2006.201.06:58:07.00:!+3s 2006.201.06:58:10.02:"tape 2006.201.06:58:10.02:postob 2006.201.06:58:10.17/cable/+6.4647E-03 2006.201.06:58:10.17/wx/23.19,1003.2,89 2006.201.06:58:10.23/fmout-gps/S +4.55E-07 2006.201.06:58:10.23:scan_name=201-0659,jd0607,60 2006.201.06:58:10.23:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.201.06:58:12.14#flagr#flagr/antenna,new-source 2006.201.06:58:12.14:checkk5 2006.201.06:58:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.06:58:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.06:58:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.06:58:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.06:58:14.01/chk_obsdata//k5ts1/T2010655??a.dat file size is correct (nominal:520MB, actual:520MB). 2006.201.06:58:14.37/chk_obsdata//k5ts2/T2010655??b.dat file size is correct (nominal:520MB, actual:520MB). 2006.201.06:58:14.73/chk_obsdata//k5ts3/T2010655??c.dat file size is correct (nominal:520MB, actual:520MB). 2006.201.06:58:15.10/chk_obsdata//k5ts4/T2010655??d.dat file size is correct (nominal:520MB, actual:520MB). 2006.201.06:58:15.79/k5log//k5ts1_log_newline 2006.201.06:58:16.47/k5log//k5ts2_log_newline 2006.201.06:58:17.15/k5log//k5ts3_log_newline 2006.201.06:58:17.83/k5log//k5ts4_log_newline 2006.201.06:58:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.06:58:17.86:setupk4=1 2006.201.06:58:17.86$setupk4/echo=on 2006.201.06:58:17.86$setupk4/pcalon 2006.201.06:58:17.86$pcalon/"no phase cal control is implemented here 2006.201.06:58:17.86$setupk4/"tpicd=stop 2006.201.06:58:17.86$setupk4/"rec=synch_on 2006.201.06:58:17.86$setupk4/"rec_mode=128 2006.201.06:58:17.86$setupk4/!* 2006.201.06:58:17.86$setupk4/recpk4 2006.201.06:58:17.86$recpk4/recpatch= 2006.201.06:58:17.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.06:58:17.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.06:58:17.86$setupk4/vck44 2006.201.06:58:17.86$vck44/valo=1,524.99 2006.201.06:58:17.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.06:58:17.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.06:58:17.86#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:17.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:17.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:17.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:17.86#ibcon#enter wrdev, iclass 13, count 0 2006.201.06:58:17.86#ibcon#first serial, iclass 13, count 0 2006.201.06:58:17.86#ibcon#enter sib2, iclass 13, count 0 2006.201.06:58:17.86#ibcon#flushed, iclass 13, count 0 2006.201.06:58:17.86#ibcon#about to write, iclass 13, count 0 2006.201.06:58:17.86#ibcon#wrote, iclass 13, count 0 2006.201.06:58:17.86#ibcon#about to read 3, iclass 13, count 0 2006.201.06:58:17.90#ibcon#read 3, iclass 13, count 0 2006.201.06:58:17.90#ibcon#about to read 4, iclass 13, count 0 2006.201.06:58:17.90#ibcon#read 4, iclass 13, count 0 2006.201.06:58:17.90#ibcon#about to read 5, iclass 13, count 0 2006.201.06:58:17.90#ibcon#read 5, iclass 13, count 0 2006.201.06:58:17.90#ibcon#about to read 6, iclass 13, count 0 2006.201.06:58:17.90#ibcon#read 6, iclass 13, count 0 2006.201.06:58:17.90#ibcon#end of sib2, iclass 13, count 0 2006.201.06:58:17.90#ibcon#*mode == 0, iclass 13, count 0 2006.201.06:58:17.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.06:58:17.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.06:58:17.90#ibcon#*before write, iclass 13, count 0 2006.201.06:58:17.90#ibcon#enter sib2, iclass 13, count 0 2006.201.06:58:17.90#ibcon#flushed, iclass 13, count 0 2006.201.06:58:17.90#ibcon#about to write, iclass 13, count 0 2006.201.06:58:17.90#ibcon#wrote, iclass 13, count 0 2006.201.06:58:17.90#ibcon#about to read 3, iclass 13, count 0 2006.201.06:58:17.95#ibcon#read 3, iclass 13, count 0 2006.201.06:58:17.95#ibcon#about to read 4, iclass 13, count 0 2006.201.06:58:17.95#ibcon#read 4, iclass 13, count 0 2006.201.06:58:17.95#ibcon#about to read 5, iclass 13, count 0 2006.201.06:58:17.95#ibcon#read 5, iclass 13, count 0 2006.201.06:58:17.95#ibcon#about to read 6, iclass 13, count 0 2006.201.06:58:17.95#ibcon#read 6, iclass 13, count 0 2006.201.06:58:17.95#ibcon#end of sib2, iclass 13, count 0 2006.201.06:58:17.95#ibcon#*after write, iclass 13, count 0 2006.201.06:58:17.95#ibcon#*before return 0, iclass 13, count 0 2006.201.06:58:17.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:17.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:17.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.06:58:17.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.06:58:17.95$vck44/va=1,8 2006.201.06:58:17.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.06:58:17.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.06:58:17.95#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:17.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:17.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:17.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:17.95#ibcon#enter wrdev, iclass 15, count 2 2006.201.06:58:17.95#ibcon#first serial, iclass 15, count 2 2006.201.06:58:17.95#ibcon#enter sib2, iclass 15, count 2 2006.201.06:58:17.95#ibcon#flushed, iclass 15, count 2 2006.201.06:58:17.95#ibcon#about to write, iclass 15, count 2 2006.201.06:58:17.95#ibcon#wrote, iclass 15, count 2 2006.201.06:58:17.95#ibcon#about to read 3, iclass 15, count 2 2006.201.06:58:17.97#ibcon#read 3, iclass 15, count 2 2006.201.06:58:17.97#ibcon#about to read 4, iclass 15, count 2 2006.201.06:58:17.97#ibcon#read 4, iclass 15, count 2 2006.201.06:58:17.97#ibcon#about to read 5, iclass 15, count 2 2006.201.06:58:17.97#ibcon#read 5, iclass 15, count 2 2006.201.06:58:17.97#ibcon#about to read 6, iclass 15, count 2 2006.201.06:58:17.97#ibcon#read 6, iclass 15, count 2 2006.201.06:58:17.97#ibcon#end of sib2, iclass 15, count 2 2006.201.06:58:17.97#ibcon#*mode == 0, iclass 15, count 2 2006.201.06:58:17.97#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.06:58:17.97#ibcon#[25=AT01-08\r\n] 2006.201.06:58:17.97#ibcon#*before write, iclass 15, count 2 2006.201.06:58:17.97#ibcon#enter sib2, iclass 15, count 2 2006.201.06:58:17.97#ibcon#flushed, iclass 15, count 2 2006.201.06:58:17.97#ibcon#about to write, iclass 15, count 2 2006.201.06:58:17.97#ibcon#wrote, iclass 15, count 2 2006.201.06:58:17.97#ibcon#about to read 3, iclass 15, count 2 2006.201.06:58:18.01#ibcon#read 3, iclass 15, count 2 2006.201.06:58:18.01#ibcon#about to read 4, iclass 15, count 2 2006.201.06:58:18.01#ibcon#read 4, iclass 15, count 2 2006.201.06:58:18.01#ibcon#about to read 5, iclass 15, count 2 2006.201.06:58:18.01#ibcon#read 5, iclass 15, count 2 2006.201.06:58:18.01#ibcon#about to read 6, iclass 15, count 2 2006.201.06:58:18.01#ibcon#read 6, iclass 15, count 2 2006.201.06:58:18.01#ibcon#end of sib2, iclass 15, count 2 2006.201.06:58:18.01#ibcon#*after write, iclass 15, count 2 2006.201.06:58:18.01#ibcon#*before return 0, iclass 15, count 2 2006.201.06:58:18.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:18.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:18.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.06:58:18.01#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:18.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:18.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:18.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:18.13#ibcon#enter wrdev, iclass 15, count 0 2006.201.06:58:18.13#ibcon#first serial, iclass 15, count 0 2006.201.06:58:18.13#ibcon#enter sib2, iclass 15, count 0 2006.201.06:58:18.13#ibcon#flushed, iclass 15, count 0 2006.201.06:58:18.13#ibcon#about to write, iclass 15, count 0 2006.201.06:58:18.13#ibcon#wrote, iclass 15, count 0 2006.201.06:58:18.13#ibcon#about to read 3, iclass 15, count 0 2006.201.06:58:18.15#ibcon#read 3, iclass 15, count 0 2006.201.06:58:18.15#ibcon#about to read 4, iclass 15, count 0 2006.201.06:58:18.15#ibcon#read 4, iclass 15, count 0 2006.201.06:58:18.15#ibcon#about to read 5, iclass 15, count 0 2006.201.06:58:18.15#ibcon#read 5, iclass 15, count 0 2006.201.06:58:18.15#ibcon#about to read 6, iclass 15, count 0 2006.201.06:58:18.15#ibcon#read 6, iclass 15, count 0 2006.201.06:58:18.15#ibcon#end of sib2, iclass 15, count 0 2006.201.06:58:18.15#ibcon#*mode == 0, iclass 15, count 0 2006.201.06:58:18.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.06:58:18.15#ibcon#[25=USB\r\n] 2006.201.06:58:18.15#ibcon#*before write, iclass 15, count 0 2006.201.06:58:18.15#ibcon#enter sib2, iclass 15, count 0 2006.201.06:58:18.15#ibcon#flushed, iclass 15, count 0 2006.201.06:58:18.15#ibcon#about to write, iclass 15, count 0 2006.201.06:58:18.15#ibcon#wrote, iclass 15, count 0 2006.201.06:58:18.15#ibcon#about to read 3, iclass 15, count 0 2006.201.06:58:18.18#ibcon#read 3, iclass 15, count 0 2006.201.06:58:18.18#ibcon#about to read 4, iclass 15, count 0 2006.201.06:58:18.18#ibcon#read 4, iclass 15, count 0 2006.201.06:58:18.18#ibcon#about to read 5, iclass 15, count 0 2006.201.06:58:18.18#ibcon#read 5, iclass 15, count 0 2006.201.06:58:18.18#ibcon#about to read 6, iclass 15, count 0 2006.201.06:58:18.18#ibcon#read 6, iclass 15, count 0 2006.201.06:58:18.18#ibcon#end of sib2, iclass 15, count 0 2006.201.06:58:18.18#ibcon#*after write, iclass 15, count 0 2006.201.06:58:18.18#ibcon#*before return 0, iclass 15, count 0 2006.201.06:58:18.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:18.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:18.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.06:58:18.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.06:58:18.18$vck44/valo=2,534.99 2006.201.06:58:18.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.06:58:18.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.06:58:18.18#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:18.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:18.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:18.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:18.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.06:58:18.18#ibcon#first serial, iclass 17, count 0 2006.201.06:58:18.18#ibcon#enter sib2, iclass 17, count 0 2006.201.06:58:18.18#ibcon#flushed, iclass 17, count 0 2006.201.06:58:18.18#ibcon#about to write, iclass 17, count 0 2006.201.06:58:18.18#ibcon#wrote, iclass 17, count 0 2006.201.06:58:18.18#ibcon#about to read 3, iclass 17, count 0 2006.201.06:58:18.20#ibcon#read 3, iclass 17, count 0 2006.201.06:58:18.20#ibcon#about to read 4, iclass 17, count 0 2006.201.06:58:18.20#ibcon#read 4, iclass 17, count 0 2006.201.06:58:18.20#ibcon#about to read 5, iclass 17, count 0 2006.201.06:58:18.20#ibcon#read 5, iclass 17, count 0 2006.201.06:58:18.20#ibcon#about to read 6, iclass 17, count 0 2006.201.06:58:18.20#ibcon#read 6, iclass 17, count 0 2006.201.06:58:18.20#ibcon#end of sib2, iclass 17, count 0 2006.201.06:58:18.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.06:58:18.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.06:58:18.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.06:58:18.20#ibcon#*before write, iclass 17, count 0 2006.201.06:58:18.20#ibcon#enter sib2, iclass 17, count 0 2006.201.06:58:18.20#ibcon#flushed, iclass 17, count 0 2006.201.06:58:18.20#ibcon#about to write, iclass 17, count 0 2006.201.06:58:18.20#ibcon#wrote, iclass 17, count 0 2006.201.06:58:18.20#ibcon#about to read 3, iclass 17, count 0 2006.201.06:58:18.25#ibcon#read 3, iclass 17, count 0 2006.201.06:58:18.25#ibcon#about to read 4, iclass 17, count 0 2006.201.06:58:18.25#ibcon#read 4, iclass 17, count 0 2006.201.06:58:18.25#ibcon#about to read 5, iclass 17, count 0 2006.201.06:58:18.25#ibcon#read 5, iclass 17, count 0 2006.201.06:58:18.25#ibcon#about to read 6, iclass 17, count 0 2006.201.06:58:18.25#ibcon#read 6, iclass 17, count 0 2006.201.06:58:18.25#ibcon#end of sib2, iclass 17, count 0 2006.201.06:58:18.25#ibcon#*after write, iclass 17, count 0 2006.201.06:58:18.25#ibcon#*before return 0, iclass 17, count 0 2006.201.06:58:18.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:18.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:18.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.06:58:18.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.06:58:18.25$vck44/va=2,7 2006.201.06:58:18.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.06:58:18.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.06:58:18.25#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:18.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:18.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:18.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:18.30#ibcon#enter wrdev, iclass 19, count 2 2006.201.06:58:18.30#ibcon#first serial, iclass 19, count 2 2006.201.06:58:18.30#ibcon#enter sib2, iclass 19, count 2 2006.201.06:58:18.30#ibcon#flushed, iclass 19, count 2 2006.201.06:58:18.30#ibcon#about to write, iclass 19, count 2 2006.201.06:58:18.30#ibcon#wrote, iclass 19, count 2 2006.201.06:58:18.30#ibcon#about to read 3, iclass 19, count 2 2006.201.06:58:18.32#ibcon#read 3, iclass 19, count 2 2006.201.06:58:18.32#ibcon#about to read 4, iclass 19, count 2 2006.201.06:58:18.32#ibcon#read 4, iclass 19, count 2 2006.201.06:58:18.32#ibcon#about to read 5, iclass 19, count 2 2006.201.06:58:18.32#ibcon#read 5, iclass 19, count 2 2006.201.06:58:18.32#ibcon#about to read 6, iclass 19, count 2 2006.201.06:58:18.32#ibcon#read 6, iclass 19, count 2 2006.201.06:58:18.32#ibcon#end of sib2, iclass 19, count 2 2006.201.06:58:18.32#ibcon#*mode == 0, iclass 19, count 2 2006.201.06:58:18.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.06:58:18.32#ibcon#[25=AT02-07\r\n] 2006.201.06:58:18.32#ibcon#*before write, iclass 19, count 2 2006.201.06:58:18.32#ibcon#enter sib2, iclass 19, count 2 2006.201.06:58:18.32#ibcon#flushed, iclass 19, count 2 2006.201.06:58:18.32#ibcon#about to write, iclass 19, count 2 2006.201.06:58:18.32#ibcon#wrote, iclass 19, count 2 2006.201.06:58:18.32#ibcon#about to read 3, iclass 19, count 2 2006.201.06:58:18.35#ibcon#read 3, iclass 19, count 2 2006.201.06:58:18.35#ibcon#about to read 4, iclass 19, count 2 2006.201.06:58:18.35#ibcon#read 4, iclass 19, count 2 2006.201.06:58:18.35#ibcon#about to read 5, iclass 19, count 2 2006.201.06:58:18.35#ibcon#read 5, iclass 19, count 2 2006.201.06:58:18.35#ibcon#about to read 6, iclass 19, count 2 2006.201.06:58:18.35#ibcon#read 6, iclass 19, count 2 2006.201.06:58:18.35#ibcon#end of sib2, iclass 19, count 2 2006.201.06:58:18.35#ibcon#*after write, iclass 19, count 2 2006.201.06:58:18.35#ibcon#*before return 0, iclass 19, count 2 2006.201.06:58:18.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:18.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:18.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.06:58:18.35#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:18.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:18.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:18.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:18.47#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:58:18.47#ibcon#first serial, iclass 19, count 0 2006.201.06:58:18.47#ibcon#enter sib2, iclass 19, count 0 2006.201.06:58:18.47#ibcon#flushed, iclass 19, count 0 2006.201.06:58:18.47#ibcon#about to write, iclass 19, count 0 2006.201.06:58:18.47#ibcon#wrote, iclass 19, count 0 2006.201.06:58:18.47#ibcon#about to read 3, iclass 19, count 0 2006.201.06:58:18.49#ibcon#read 3, iclass 19, count 0 2006.201.06:58:18.49#ibcon#about to read 4, iclass 19, count 0 2006.201.06:58:18.49#ibcon#read 4, iclass 19, count 0 2006.201.06:58:18.49#ibcon#about to read 5, iclass 19, count 0 2006.201.06:58:18.49#ibcon#read 5, iclass 19, count 0 2006.201.06:58:18.49#ibcon#about to read 6, iclass 19, count 0 2006.201.06:58:18.49#ibcon#read 6, iclass 19, count 0 2006.201.06:58:18.49#ibcon#end of sib2, iclass 19, count 0 2006.201.06:58:18.49#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:58:18.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:58:18.49#ibcon#[25=USB\r\n] 2006.201.06:58:18.49#ibcon#*before write, iclass 19, count 0 2006.201.06:58:18.49#ibcon#enter sib2, iclass 19, count 0 2006.201.06:58:18.49#ibcon#flushed, iclass 19, count 0 2006.201.06:58:18.49#ibcon#about to write, iclass 19, count 0 2006.201.06:58:18.49#ibcon#wrote, iclass 19, count 0 2006.201.06:58:18.49#ibcon#about to read 3, iclass 19, count 0 2006.201.06:58:18.52#ibcon#read 3, iclass 19, count 0 2006.201.06:58:18.52#ibcon#about to read 4, iclass 19, count 0 2006.201.06:58:18.52#ibcon#read 4, iclass 19, count 0 2006.201.06:58:18.52#ibcon#about to read 5, iclass 19, count 0 2006.201.06:58:18.52#ibcon#read 5, iclass 19, count 0 2006.201.06:58:18.52#ibcon#about to read 6, iclass 19, count 0 2006.201.06:58:18.52#ibcon#read 6, iclass 19, count 0 2006.201.06:58:18.52#ibcon#end of sib2, iclass 19, count 0 2006.201.06:58:18.52#ibcon#*after write, iclass 19, count 0 2006.201.06:58:18.52#ibcon#*before return 0, iclass 19, count 0 2006.201.06:58:18.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:18.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:18.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:58:18.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:58:18.52$vck44/valo=3,564.99 2006.201.06:58:18.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.06:58:18.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.06:58:18.52#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:18.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:18.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:18.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:18.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.06:58:18.52#ibcon#first serial, iclass 21, count 0 2006.201.06:58:18.52#ibcon#enter sib2, iclass 21, count 0 2006.201.06:58:18.52#ibcon#flushed, iclass 21, count 0 2006.201.06:58:18.52#ibcon#about to write, iclass 21, count 0 2006.201.06:58:18.52#ibcon#wrote, iclass 21, count 0 2006.201.06:58:18.52#ibcon#about to read 3, iclass 21, count 0 2006.201.06:58:18.54#ibcon#read 3, iclass 21, count 0 2006.201.06:58:18.54#ibcon#about to read 4, iclass 21, count 0 2006.201.06:58:18.54#ibcon#read 4, iclass 21, count 0 2006.201.06:58:18.54#ibcon#about to read 5, iclass 21, count 0 2006.201.06:58:18.54#ibcon#read 5, iclass 21, count 0 2006.201.06:58:18.54#ibcon#about to read 6, iclass 21, count 0 2006.201.06:58:18.54#ibcon#read 6, iclass 21, count 0 2006.201.06:58:18.54#ibcon#end of sib2, iclass 21, count 0 2006.201.06:58:18.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.06:58:18.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.06:58:18.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.06:58:18.54#ibcon#*before write, iclass 21, count 0 2006.201.06:58:18.54#ibcon#enter sib2, iclass 21, count 0 2006.201.06:58:18.54#ibcon#flushed, iclass 21, count 0 2006.201.06:58:18.54#ibcon#about to write, iclass 21, count 0 2006.201.06:58:18.54#ibcon#wrote, iclass 21, count 0 2006.201.06:58:18.54#ibcon#about to read 3, iclass 21, count 0 2006.201.06:58:18.59#ibcon#read 3, iclass 21, count 0 2006.201.06:58:18.59#ibcon#about to read 4, iclass 21, count 0 2006.201.06:58:18.59#ibcon#read 4, iclass 21, count 0 2006.201.06:58:18.59#ibcon#about to read 5, iclass 21, count 0 2006.201.06:58:18.59#ibcon#read 5, iclass 21, count 0 2006.201.06:58:18.59#ibcon#about to read 6, iclass 21, count 0 2006.201.06:58:18.59#ibcon#read 6, iclass 21, count 0 2006.201.06:58:18.59#ibcon#end of sib2, iclass 21, count 0 2006.201.06:58:18.59#ibcon#*after write, iclass 21, count 0 2006.201.06:58:18.59#ibcon#*before return 0, iclass 21, count 0 2006.201.06:58:18.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:18.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:18.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.06:58:18.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.06:58:18.59$vck44/va=3,8 2006.201.06:58:18.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.06:58:18.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.06:58:18.59#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:18.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:18.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:18.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:18.64#ibcon#enter wrdev, iclass 23, count 2 2006.201.06:58:18.64#ibcon#first serial, iclass 23, count 2 2006.201.06:58:18.64#ibcon#enter sib2, iclass 23, count 2 2006.201.06:58:18.64#ibcon#flushed, iclass 23, count 2 2006.201.06:58:18.64#ibcon#about to write, iclass 23, count 2 2006.201.06:58:18.64#ibcon#wrote, iclass 23, count 2 2006.201.06:58:18.64#ibcon#about to read 3, iclass 23, count 2 2006.201.06:58:18.66#ibcon#read 3, iclass 23, count 2 2006.201.06:58:18.66#ibcon#about to read 4, iclass 23, count 2 2006.201.06:58:18.66#ibcon#read 4, iclass 23, count 2 2006.201.06:58:18.66#ibcon#about to read 5, iclass 23, count 2 2006.201.06:58:18.66#ibcon#read 5, iclass 23, count 2 2006.201.06:58:18.66#ibcon#about to read 6, iclass 23, count 2 2006.201.06:58:18.66#ibcon#read 6, iclass 23, count 2 2006.201.06:58:18.66#ibcon#end of sib2, iclass 23, count 2 2006.201.06:58:18.66#ibcon#*mode == 0, iclass 23, count 2 2006.201.06:58:18.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.06:58:18.66#ibcon#[25=AT03-08\r\n] 2006.201.06:58:18.66#ibcon#*before write, iclass 23, count 2 2006.201.06:58:18.66#ibcon#enter sib2, iclass 23, count 2 2006.201.06:58:18.66#ibcon#flushed, iclass 23, count 2 2006.201.06:58:18.66#ibcon#about to write, iclass 23, count 2 2006.201.06:58:18.66#ibcon#wrote, iclass 23, count 2 2006.201.06:58:18.66#ibcon#about to read 3, iclass 23, count 2 2006.201.06:58:18.69#ibcon#read 3, iclass 23, count 2 2006.201.06:58:18.69#ibcon#about to read 4, iclass 23, count 2 2006.201.06:58:18.69#ibcon#read 4, iclass 23, count 2 2006.201.06:58:18.69#ibcon#about to read 5, iclass 23, count 2 2006.201.06:58:18.69#ibcon#read 5, iclass 23, count 2 2006.201.06:58:18.69#ibcon#about to read 6, iclass 23, count 2 2006.201.06:58:18.69#ibcon#read 6, iclass 23, count 2 2006.201.06:58:18.69#ibcon#end of sib2, iclass 23, count 2 2006.201.06:58:18.69#ibcon#*after write, iclass 23, count 2 2006.201.06:58:18.69#ibcon#*before return 0, iclass 23, count 2 2006.201.06:58:18.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:18.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:18.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.06:58:18.69#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:18.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:18.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:18.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:18.81#ibcon#enter wrdev, iclass 23, count 0 2006.201.06:58:18.81#ibcon#first serial, iclass 23, count 0 2006.201.06:58:18.81#ibcon#enter sib2, iclass 23, count 0 2006.201.06:58:18.81#ibcon#flushed, iclass 23, count 0 2006.201.06:58:18.81#ibcon#about to write, iclass 23, count 0 2006.201.06:58:18.81#ibcon#wrote, iclass 23, count 0 2006.201.06:58:18.81#ibcon#about to read 3, iclass 23, count 0 2006.201.06:58:18.83#ibcon#read 3, iclass 23, count 0 2006.201.06:58:18.83#ibcon#about to read 4, iclass 23, count 0 2006.201.06:58:18.83#ibcon#read 4, iclass 23, count 0 2006.201.06:58:18.83#ibcon#about to read 5, iclass 23, count 0 2006.201.06:58:18.83#ibcon#read 5, iclass 23, count 0 2006.201.06:58:18.83#ibcon#about to read 6, iclass 23, count 0 2006.201.06:58:18.83#ibcon#read 6, iclass 23, count 0 2006.201.06:58:18.83#ibcon#end of sib2, iclass 23, count 0 2006.201.06:58:18.83#ibcon#*mode == 0, iclass 23, count 0 2006.201.06:58:18.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.06:58:18.83#ibcon#[25=USB\r\n] 2006.201.06:58:18.83#ibcon#*before write, iclass 23, count 0 2006.201.06:58:18.83#ibcon#enter sib2, iclass 23, count 0 2006.201.06:58:18.83#ibcon#flushed, iclass 23, count 0 2006.201.06:58:18.83#ibcon#about to write, iclass 23, count 0 2006.201.06:58:18.83#ibcon#wrote, iclass 23, count 0 2006.201.06:58:18.83#ibcon#about to read 3, iclass 23, count 0 2006.201.06:58:18.86#ibcon#read 3, iclass 23, count 0 2006.201.06:58:18.86#ibcon#about to read 4, iclass 23, count 0 2006.201.06:58:18.86#ibcon#read 4, iclass 23, count 0 2006.201.06:58:18.86#ibcon#about to read 5, iclass 23, count 0 2006.201.06:58:18.86#ibcon#read 5, iclass 23, count 0 2006.201.06:58:18.86#ibcon#about to read 6, iclass 23, count 0 2006.201.06:58:18.86#ibcon#read 6, iclass 23, count 0 2006.201.06:58:18.86#ibcon#end of sib2, iclass 23, count 0 2006.201.06:58:18.86#ibcon#*after write, iclass 23, count 0 2006.201.06:58:18.86#ibcon#*before return 0, iclass 23, count 0 2006.201.06:58:18.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:18.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:18.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.06:58:18.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.06:58:18.86$vck44/valo=4,624.99 2006.201.06:58:18.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.06:58:18.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.06:58:18.86#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:18.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:18.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:18.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:18.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.06:58:18.86#ibcon#first serial, iclass 25, count 0 2006.201.06:58:18.86#ibcon#enter sib2, iclass 25, count 0 2006.201.06:58:18.86#ibcon#flushed, iclass 25, count 0 2006.201.06:58:18.86#ibcon#about to write, iclass 25, count 0 2006.201.06:58:18.86#ibcon#wrote, iclass 25, count 0 2006.201.06:58:18.86#ibcon#about to read 3, iclass 25, count 0 2006.201.06:58:18.88#ibcon#read 3, iclass 25, count 0 2006.201.06:58:18.88#ibcon#about to read 4, iclass 25, count 0 2006.201.06:58:18.88#ibcon#read 4, iclass 25, count 0 2006.201.06:58:18.88#ibcon#about to read 5, iclass 25, count 0 2006.201.06:58:18.88#ibcon#read 5, iclass 25, count 0 2006.201.06:58:18.88#ibcon#about to read 6, iclass 25, count 0 2006.201.06:58:18.88#ibcon#read 6, iclass 25, count 0 2006.201.06:58:18.88#ibcon#end of sib2, iclass 25, count 0 2006.201.06:58:18.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.06:58:18.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.06:58:18.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.06:58:18.88#ibcon#*before write, iclass 25, count 0 2006.201.06:58:18.88#ibcon#enter sib2, iclass 25, count 0 2006.201.06:58:18.88#ibcon#flushed, iclass 25, count 0 2006.201.06:58:18.88#ibcon#about to write, iclass 25, count 0 2006.201.06:58:18.88#ibcon#wrote, iclass 25, count 0 2006.201.06:58:18.88#ibcon#about to read 3, iclass 25, count 0 2006.201.06:58:18.93#ibcon#read 3, iclass 25, count 0 2006.201.06:58:18.93#ibcon#about to read 4, iclass 25, count 0 2006.201.06:58:18.93#ibcon#read 4, iclass 25, count 0 2006.201.06:58:18.93#ibcon#about to read 5, iclass 25, count 0 2006.201.06:58:18.93#ibcon#read 5, iclass 25, count 0 2006.201.06:58:18.93#ibcon#about to read 6, iclass 25, count 0 2006.201.06:58:18.93#ibcon#read 6, iclass 25, count 0 2006.201.06:58:18.93#ibcon#end of sib2, iclass 25, count 0 2006.201.06:58:18.93#ibcon#*after write, iclass 25, count 0 2006.201.06:58:18.93#ibcon#*before return 0, iclass 25, count 0 2006.201.06:58:18.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:18.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:18.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.06:58:18.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.06:58:18.93$vck44/va=4,7 2006.201.06:58:18.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.06:58:18.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.06:58:18.93#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:18.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:18.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:18.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:18.98#ibcon#enter wrdev, iclass 27, count 2 2006.201.06:58:18.98#ibcon#first serial, iclass 27, count 2 2006.201.06:58:18.98#ibcon#enter sib2, iclass 27, count 2 2006.201.06:58:18.98#ibcon#flushed, iclass 27, count 2 2006.201.06:58:18.98#ibcon#about to write, iclass 27, count 2 2006.201.06:58:18.98#ibcon#wrote, iclass 27, count 2 2006.201.06:58:18.98#ibcon#about to read 3, iclass 27, count 2 2006.201.06:58:19.00#ibcon#read 3, iclass 27, count 2 2006.201.06:58:19.00#ibcon#about to read 4, iclass 27, count 2 2006.201.06:58:19.00#ibcon#read 4, iclass 27, count 2 2006.201.06:58:19.00#ibcon#about to read 5, iclass 27, count 2 2006.201.06:58:19.00#ibcon#read 5, iclass 27, count 2 2006.201.06:58:19.00#ibcon#about to read 6, iclass 27, count 2 2006.201.06:58:19.00#ibcon#read 6, iclass 27, count 2 2006.201.06:58:19.00#ibcon#end of sib2, iclass 27, count 2 2006.201.06:58:19.00#ibcon#*mode == 0, iclass 27, count 2 2006.201.06:58:19.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.06:58:19.00#ibcon#[25=AT04-07\r\n] 2006.201.06:58:19.00#ibcon#*before write, iclass 27, count 2 2006.201.06:58:19.00#ibcon#enter sib2, iclass 27, count 2 2006.201.06:58:19.00#ibcon#flushed, iclass 27, count 2 2006.201.06:58:19.00#ibcon#about to write, iclass 27, count 2 2006.201.06:58:19.00#ibcon#wrote, iclass 27, count 2 2006.201.06:58:19.00#ibcon#about to read 3, iclass 27, count 2 2006.201.06:58:19.03#ibcon#read 3, iclass 27, count 2 2006.201.06:58:19.03#ibcon#about to read 4, iclass 27, count 2 2006.201.06:58:19.03#ibcon#read 4, iclass 27, count 2 2006.201.06:58:19.03#ibcon#about to read 5, iclass 27, count 2 2006.201.06:58:19.03#ibcon#read 5, iclass 27, count 2 2006.201.06:58:19.03#ibcon#about to read 6, iclass 27, count 2 2006.201.06:58:19.03#ibcon#read 6, iclass 27, count 2 2006.201.06:58:19.03#ibcon#end of sib2, iclass 27, count 2 2006.201.06:58:19.03#ibcon#*after write, iclass 27, count 2 2006.201.06:58:19.03#ibcon#*before return 0, iclass 27, count 2 2006.201.06:58:19.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:19.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:19.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.06:58:19.03#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:19.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:19.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:19.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:19.15#ibcon#enter wrdev, iclass 27, count 0 2006.201.06:58:19.15#ibcon#first serial, iclass 27, count 0 2006.201.06:58:19.15#ibcon#enter sib2, iclass 27, count 0 2006.201.06:58:19.15#ibcon#flushed, iclass 27, count 0 2006.201.06:58:19.15#ibcon#about to write, iclass 27, count 0 2006.201.06:58:19.15#ibcon#wrote, iclass 27, count 0 2006.201.06:58:19.15#ibcon#about to read 3, iclass 27, count 0 2006.201.06:58:19.17#ibcon#read 3, iclass 27, count 0 2006.201.06:58:19.17#ibcon#about to read 4, iclass 27, count 0 2006.201.06:58:19.17#ibcon#read 4, iclass 27, count 0 2006.201.06:58:19.17#ibcon#about to read 5, iclass 27, count 0 2006.201.06:58:19.17#ibcon#read 5, iclass 27, count 0 2006.201.06:58:19.17#ibcon#about to read 6, iclass 27, count 0 2006.201.06:58:19.17#ibcon#read 6, iclass 27, count 0 2006.201.06:58:19.17#ibcon#end of sib2, iclass 27, count 0 2006.201.06:58:19.17#ibcon#*mode == 0, iclass 27, count 0 2006.201.06:58:19.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.06:58:19.17#ibcon#[25=USB\r\n] 2006.201.06:58:19.17#ibcon#*before write, iclass 27, count 0 2006.201.06:58:19.17#ibcon#enter sib2, iclass 27, count 0 2006.201.06:58:19.17#ibcon#flushed, iclass 27, count 0 2006.201.06:58:19.17#ibcon#about to write, iclass 27, count 0 2006.201.06:58:19.17#ibcon#wrote, iclass 27, count 0 2006.201.06:58:19.17#ibcon#about to read 3, iclass 27, count 0 2006.201.06:58:19.20#ibcon#read 3, iclass 27, count 0 2006.201.06:58:19.20#ibcon#about to read 4, iclass 27, count 0 2006.201.06:58:19.20#ibcon#read 4, iclass 27, count 0 2006.201.06:58:19.20#ibcon#about to read 5, iclass 27, count 0 2006.201.06:58:19.20#ibcon#read 5, iclass 27, count 0 2006.201.06:58:19.20#ibcon#about to read 6, iclass 27, count 0 2006.201.06:58:19.20#ibcon#read 6, iclass 27, count 0 2006.201.06:58:19.20#ibcon#end of sib2, iclass 27, count 0 2006.201.06:58:19.20#ibcon#*after write, iclass 27, count 0 2006.201.06:58:19.20#ibcon#*before return 0, iclass 27, count 0 2006.201.06:58:19.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:19.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:19.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.06:58:19.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.06:58:19.20$vck44/valo=5,734.99 2006.201.06:58:19.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.06:58:19.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.06:58:19.20#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:19.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:19.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:19.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:19.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.06:58:19.20#ibcon#first serial, iclass 29, count 0 2006.201.06:58:19.20#ibcon#enter sib2, iclass 29, count 0 2006.201.06:58:19.20#ibcon#flushed, iclass 29, count 0 2006.201.06:58:19.20#ibcon#about to write, iclass 29, count 0 2006.201.06:58:19.20#ibcon#wrote, iclass 29, count 0 2006.201.06:58:19.20#ibcon#about to read 3, iclass 29, count 0 2006.201.06:58:19.22#ibcon#read 3, iclass 29, count 0 2006.201.06:58:19.22#ibcon#about to read 4, iclass 29, count 0 2006.201.06:58:19.22#ibcon#read 4, iclass 29, count 0 2006.201.06:58:19.22#ibcon#about to read 5, iclass 29, count 0 2006.201.06:58:19.22#ibcon#read 5, iclass 29, count 0 2006.201.06:58:19.22#ibcon#about to read 6, iclass 29, count 0 2006.201.06:58:19.22#ibcon#read 6, iclass 29, count 0 2006.201.06:58:19.22#ibcon#end of sib2, iclass 29, count 0 2006.201.06:58:19.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.06:58:19.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.06:58:19.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.06:58:19.22#ibcon#*before write, iclass 29, count 0 2006.201.06:58:19.22#ibcon#enter sib2, iclass 29, count 0 2006.201.06:58:19.22#ibcon#flushed, iclass 29, count 0 2006.201.06:58:19.22#ibcon#about to write, iclass 29, count 0 2006.201.06:58:19.22#ibcon#wrote, iclass 29, count 0 2006.201.06:58:19.22#ibcon#about to read 3, iclass 29, count 0 2006.201.06:58:19.26#ibcon#read 3, iclass 29, count 0 2006.201.06:58:19.26#ibcon#about to read 4, iclass 29, count 0 2006.201.06:58:19.26#ibcon#read 4, iclass 29, count 0 2006.201.06:58:19.26#ibcon#about to read 5, iclass 29, count 0 2006.201.06:58:19.26#ibcon#read 5, iclass 29, count 0 2006.201.06:58:19.26#ibcon#about to read 6, iclass 29, count 0 2006.201.06:58:19.26#ibcon#read 6, iclass 29, count 0 2006.201.06:58:19.26#ibcon#end of sib2, iclass 29, count 0 2006.201.06:58:19.26#ibcon#*after write, iclass 29, count 0 2006.201.06:58:19.26#ibcon#*before return 0, iclass 29, count 0 2006.201.06:58:19.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:19.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:19.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.06:58:19.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.06:58:19.26$vck44/va=5,4 2006.201.06:58:19.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.06:58:19.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.06:58:19.26#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:19.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:19.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:19.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:19.32#ibcon#enter wrdev, iclass 31, count 2 2006.201.06:58:19.32#ibcon#first serial, iclass 31, count 2 2006.201.06:58:19.32#ibcon#enter sib2, iclass 31, count 2 2006.201.06:58:19.32#ibcon#flushed, iclass 31, count 2 2006.201.06:58:19.32#ibcon#about to write, iclass 31, count 2 2006.201.06:58:19.32#ibcon#wrote, iclass 31, count 2 2006.201.06:58:19.32#ibcon#about to read 3, iclass 31, count 2 2006.201.06:58:19.34#ibcon#read 3, iclass 31, count 2 2006.201.06:58:19.34#ibcon#about to read 4, iclass 31, count 2 2006.201.06:58:19.34#ibcon#read 4, iclass 31, count 2 2006.201.06:58:19.34#ibcon#about to read 5, iclass 31, count 2 2006.201.06:58:19.34#ibcon#read 5, iclass 31, count 2 2006.201.06:58:19.34#ibcon#about to read 6, iclass 31, count 2 2006.201.06:58:19.34#ibcon#read 6, iclass 31, count 2 2006.201.06:58:19.34#ibcon#end of sib2, iclass 31, count 2 2006.201.06:58:19.34#ibcon#*mode == 0, iclass 31, count 2 2006.201.06:58:19.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.06:58:19.34#ibcon#[25=AT05-04\r\n] 2006.201.06:58:19.34#ibcon#*before write, iclass 31, count 2 2006.201.06:58:19.34#ibcon#enter sib2, iclass 31, count 2 2006.201.06:58:19.34#ibcon#flushed, iclass 31, count 2 2006.201.06:58:19.34#ibcon#about to write, iclass 31, count 2 2006.201.06:58:19.34#ibcon#wrote, iclass 31, count 2 2006.201.06:58:19.34#ibcon#about to read 3, iclass 31, count 2 2006.201.06:58:19.37#ibcon#read 3, iclass 31, count 2 2006.201.06:58:19.37#ibcon#about to read 4, iclass 31, count 2 2006.201.06:58:19.37#ibcon#read 4, iclass 31, count 2 2006.201.06:58:19.37#ibcon#about to read 5, iclass 31, count 2 2006.201.06:58:19.37#ibcon#read 5, iclass 31, count 2 2006.201.06:58:19.37#ibcon#about to read 6, iclass 31, count 2 2006.201.06:58:19.37#ibcon#read 6, iclass 31, count 2 2006.201.06:58:19.37#ibcon#end of sib2, iclass 31, count 2 2006.201.06:58:19.37#ibcon#*after write, iclass 31, count 2 2006.201.06:58:19.37#ibcon#*before return 0, iclass 31, count 2 2006.201.06:58:19.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:19.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:19.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.06:58:19.37#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:19.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:19.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:19.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:19.49#ibcon#enter wrdev, iclass 31, count 0 2006.201.06:58:19.49#ibcon#first serial, iclass 31, count 0 2006.201.06:58:19.49#ibcon#enter sib2, iclass 31, count 0 2006.201.06:58:19.49#ibcon#flushed, iclass 31, count 0 2006.201.06:58:19.49#ibcon#about to write, iclass 31, count 0 2006.201.06:58:19.49#ibcon#wrote, iclass 31, count 0 2006.201.06:58:19.49#ibcon#about to read 3, iclass 31, count 0 2006.201.06:58:19.51#ibcon#read 3, iclass 31, count 0 2006.201.06:58:19.51#ibcon#about to read 4, iclass 31, count 0 2006.201.06:58:19.51#ibcon#read 4, iclass 31, count 0 2006.201.06:58:19.51#ibcon#about to read 5, iclass 31, count 0 2006.201.06:58:19.51#ibcon#read 5, iclass 31, count 0 2006.201.06:58:19.51#ibcon#about to read 6, iclass 31, count 0 2006.201.06:58:19.51#ibcon#read 6, iclass 31, count 0 2006.201.06:58:19.51#ibcon#end of sib2, iclass 31, count 0 2006.201.06:58:19.51#ibcon#*mode == 0, iclass 31, count 0 2006.201.06:58:19.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.06:58:19.51#ibcon#[25=USB\r\n] 2006.201.06:58:19.51#ibcon#*before write, iclass 31, count 0 2006.201.06:58:19.51#ibcon#enter sib2, iclass 31, count 0 2006.201.06:58:19.51#ibcon#flushed, iclass 31, count 0 2006.201.06:58:19.51#ibcon#about to write, iclass 31, count 0 2006.201.06:58:19.51#ibcon#wrote, iclass 31, count 0 2006.201.06:58:19.51#ibcon#about to read 3, iclass 31, count 0 2006.201.06:58:19.54#ibcon#read 3, iclass 31, count 0 2006.201.06:58:19.54#ibcon#about to read 4, iclass 31, count 0 2006.201.06:58:19.54#ibcon#read 4, iclass 31, count 0 2006.201.06:58:19.54#ibcon#about to read 5, iclass 31, count 0 2006.201.06:58:19.54#ibcon#read 5, iclass 31, count 0 2006.201.06:58:19.54#ibcon#about to read 6, iclass 31, count 0 2006.201.06:58:19.54#ibcon#read 6, iclass 31, count 0 2006.201.06:58:19.54#ibcon#end of sib2, iclass 31, count 0 2006.201.06:58:19.54#ibcon#*after write, iclass 31, count 0 2006.201.06:58:19.54#ibcon#*before return 0, iclass 31, count 0 2006.201.06:58:19.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:19.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:19.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.06:58:19.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.06:58:19.54$vck44/valo=6,814.99 2006.201.06:58:19.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.06:58:19.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.06:58:19.54#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:19.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:19.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:19.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:19.54#ibcon#enter wrdev, iclass 33, count 0 2006.201.06:58:19.54#ibcon#first serial, iclass 33, count 0 2006.201.06:58:19.54#ibcon#enter sib2, iclass 33, count 0 2006.201.06:58:19.54#ibcon#flushed, iclass 33, count 0 2006.201.06:58:19.54#ibcon#about to write, iclass 33, count 0 2006.201.06:58:19.54#ibcon#wrote, iclass 33, count 0 2006.201.06:58:19.54#ibcon#about to read 3, iclass 33, count 0 2006.201.06:58:19.56#ibcon#read 3, iclass 33, count 0 2006.201.06:58:19.56#ibcon#about to read 4, iclass 33, count 0 2006.201.06:58:19.56#ibcon#read 4, iclass 33, count 0 2006.201.06:58:19.56#ibcon#about to read 5, iclass 33, count 0 2006.201.06:58:19.56#ibcon#read 5, iclass 33, count 0 2006.201.06:58:19.56#ibcon#about to read 6, iclass 33, count 0 2006.201.06:58:19.56#ibcon#read 6, iclass 33, count 0 2006.201.06:58:19.56#ibcon#end of sib2, iclass 33, count 0 2006.201.06:58:19.56#ibcon#*mode == 0, iclass 33, count 0 2006.201.06:58:19.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.06:58:19.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.06:58:19.56#ibcon#*before write, iclass 33, count 0 2006.201.06:58:19.56#ibcon#enter sib2, iclass 33, count 0 2006.201.06:58:19.56#ibcon#flushed, iclass 33, count 0 2006.201.06:58:19.56#ibcon#about to write, iclass 33, count 0 2006.201.06:58:19.56#ibcon#wrote, iclass 33, count 0 2006.201.06:58:19.56#ibcon#about to read 3, iclass 33, count 0 2006.201.06:58:19.61#ibcon#read 3, iclass 33, count 0 2006.201.06:58:19.61#ibcon#about to read 4, iclass 33, count 0 2006.201.06:58:19.61#ibcon#read 4, iclass 33, count 0 2006.201.06:58:19.61#ibcon#about to read 5, iclass 33, count 0 2006.201.06:58:19.61#ibcon#read 5, iclass 33, count 0 2006.201.06:58:19.61#ibcon#about to read 6, iclass 33, count 0 2006.201.06:58:19.61#ibcon#read 6, iclass 33, count 0 2006.201.06:58:19.61#ibcon#end of sib2, iclass 33, count 0 2006.201.06:58:19.61#ibcon#*after write, iclass 33, count 0 2006.201.06:58:19.61#ibcon#*before return 0, iclass 33, count 0 2006.201.06:58:19.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:19.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:19.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.06:58:19.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.06:58:19.61$vck44/va=6,5 2006.201.06:58:19.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.06:58:19.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.06:58:19.61#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:19.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:19.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:19.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:19.66#ibcon#enter wrdev, iclass 35, count 2 2006.201.06:58:19.66#ibcon#first serial, iclass 35, count 2 2006.201.06:58:19.66#ibcon#enter sib2, iclass 35, count 2 2006.201.06:58:19.66#ibcon#flushed, iclass 35, count 2 2006.201.06:58:19.66#ibcon#about to write, iclass 35, count 2 2006.201.06:58:19.66#ibcon#wrote, iclass 35, count 2 2006.201.06:58:19.66#ibcon#about to read 3, iclass 35, count 2 2006.201.06:58:19.68#ibcon#read 3, iclass 35, count 2 2006.201.06:58:19.68#ibcon#about to read 4, iclass 35, count 2 2006.201.06:58:19.68#ibcon#read 4, iclass 35, count 2 2006.201.06:58:19.68#ibcon#about to read 5, iclass 35, count 2 2006.201.06:58:19.68#ibcon#read 5, iclass 35, count 2 2006.201.06:58:19.68#ibcon#about to read 6, iclass 35, count 2 2006.201.06:58:19.68#ibcon#read 6, iclass 35, count 2 2006.201.06:58:19.68#ibcon#end of sib2, iclass 35, count 2 2006.201.06:58:19.68#ibcon#*mode == 0, iclass 35, count 2 2006.201.06:58:19.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.06:58:19.68#ibcon#[25=AT06-05\r\n] 2006.201.06:58:19.68#ibcon#*before write, iclass 35, count 2 2006.201.06:58:19.68#ibcon#enter sib2, iclass 35, count 2 2006.201.06:58:19.68#ibcon#flushed, iclass 35, count 2 2006.201.06:58:19.68#ibcon#about to write, iclass 35, count 2 2006.201.06:58:19.68#ibcon#wrote, iclass 35, count 2 2006.201.06:58:19.68#ibcon#about to read 3, iclass 35, count 2 2006.201.06:58:19.71#ibcon#read 3, iclass 35, count 2 2006.201.06:58:19.71#ibcon#about to read 4, iclass 35, count 2 2006.201.06:58:19.71#ibcon#read 4, iclass 35, count 2 2006.201.06:58:19.71#ibcon#about to read 5, iclass 35, count 2 2006.201.06:58:19.71#ibcon#read 5, iclass 35, count 2 2006.201.06:58:19.71#ibcon#about to read 6, iclass 35, count 2 2006.201.06:58:19.71#ibcon#read 6, iclass 35, count 2 2006.201.06:58:19.71#ibcon#end of sib2, iclass 35, count 2 2006.201.06:58:19.71#ibcon#*after write, iclass 35, count 2 2006.201.06:58:19.71#ibcon#*before return 0, iclass 35, count 2 2006.201.06:58:19.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:19.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:19.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.06:58:19.71#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:19.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:19.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:19.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:19.83#ibcon#enter wrdev, iclass 35, count 0 2006.201.06:58:19.83#ibcon#first serial, iclass 35, count 0 2006.201.06:58:19.83#ibcon#enter sib2, iclass 35, count 0 2006.201.06:58:19.83#ibcon#flushed, iclass 35, count 0 2006.201.06:58:19.83#ibcon#about to write, iclass 35, count 0 2006.201.06:58:19.83#ibcon#wrote, iclass 35, count 0 2006.201.06:58:19.83#ibcon#about to read 3, iclass 35, count 0 2006.201.06:58:19.85#ibcon#read 3, iclass 35, count 0 2006.201.06:58:19.85#ibcon#about to read 4, iclass 35, count 0 2006.201.06:58:19.85#ibcon#read 4, iclass 35, count 0 2006.201.06:58:19.85#ibcon#about to read 5, iclass 35, count 0 2006.201.06:58:19.85#ibcon#read 5, iclass 35, count 0 2006.201.06:58:19.85#ibcon#about to read 6, iclass 35, count 0 2006.201.06:58:19.85#ibcon#read 6, iclass 35, count 0 2006.201.06:58:19.85#ibcon#end of sib2, iclass 35, count 0 2006.201.06:58:19.85#ibcon#*mode == 0, iclass 35, count 0 2006.201.06:58:19.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.06:58:19.85#ibcon#[25=USB\r\n] 2006.201.06:58:19.85#ibcon#*before write, iclass 35, count 0 2006.201.06:58:19.85#ibcon#enter sib2, iclass 35, count 0 2006.201.06:58:19.85#ibcon#flushed, iclass 35, count 0 2006.201.06:58:19.85#ibcon#about to write, iclass 35, count 0 2006.201.06:58:19.85#ibcon#wrote, iclass 35, count 0 2006.201.06:58:19.85#ibcon#about to read 3, iclass 35, count 0 2006.201.06:58:19.88#ibcon#read 3, iclass 35, count 0 2006.201.06:58:19.88#ibcon#about to read 4, iclass 35, count 0 2006.201.06:58:19.88#ibcon#read 4, iclass 35, count 0 2006.201.06:58:19.88#ibcon#about to read 5, iclass 35, count 0 2006.201.06:58:19.88#ibcon#read 5, iclass 35, count 0 2006.201.06:58:19.88#ibcon#about to read 6, iclass 35, count 0 2006.201.06:58:19.88#ibcon#read 6, iclass 35, count 0 2006.201.06:58:19.88#ibcon#end of sib2, iclass 35, count 0 2006.201.06:58:19.88#ibcon#*after write, iclass 35, count 0 2006.201.06:58:19.88#ibcon#*before return 0, iclass 35, count 0 2006.201.06:58:19.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:19.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:19.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.06:58:19.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.06:58:19.88$vck44/valo=7,864.99 2006.201.06:58:19.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.06:58:19.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.06:58:19.88#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:19.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:19.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:19.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:19.88#ibcon#enter wrdev, iclass 37, count 0 2006.201.06:58:19.88#ibcon#first serial, iclass 37, count 0 2006.201.06:58:19.88#ibcon#enter sib2, iclass 37, count 0 2006.201.06:58:19.88#ibcon#flushed, iclass 37, count 0 2006.201.06:58:19.88#ibcon#about to write, iclass 37, count 0 2006.201.06:58:19.88#ibcon#wrote, iclass 37, count 0 2006.201.06:58:19.88#ibcon#about to read 3, iclass 37, count 0 2006.201.06:58:19.90#ibcon#read 3, iclass 37, count 0 2006.201.06:58:19.90#ibcon#about to read 4, iclass 37, count 0 2006.201.06:58:19.90#ibcon#read 4, iclass 37, count 0 2006.201.06:58:19.90#ibcon#about to read 5, iclass 37, count 0 2006.201.06:58:19.90#ibcon#read 5, iclass 37, count 0 2006.201.06:58:19.90#ibcon#about to read 6, iclass 37, count 0 2006.201.06:58:19.90#ibcon#read 6, iclass 37, count 0 2006.201.06:58:19.90#ibcon#end of sib2, iclass 37, count 0 2006.201.06:58:19.90#ibcon#*mode == 0, iclass 37, count 0 2006.201.06:58:19.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.06:58:19.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.06:58:19.90#ibcon#*before write, iclass 37, count 0 2006.201.06:58:19.90#ibcon#enter sib2, iclass 37, count 0 2006.201.06:58:19.90#ibcon#flushed, iclass 37, count 0 2006.201.06:58:19.90#ibcon#about to write, iclass 37, count 0 2006.201.06:58:19.90#ibcon#wrote, iclass 37, count 0 2006.201.06:58:19.90#ibcon#about to read 3, iclass 37, count 0 2006.201.06:58:19.94#ibcon#read 3, iclass 37, count 0 2006.201.06:58:19.94#ibcon#about to read 4, iclass 37, count 0 2006.201.06:58:19.94#ibcon#read 4, iclass 37, count 0 2006.201.06:58:19.94#ibcon#about to read 5, iclass 37, count 0 2006.201.06:58:19.94#ibcon#read 5, iclass 37, count 0 2006.201.06:58:19.94#ibcon#about to read 6, iclass 37, count 0 2006.201.06:58:19.94#ibcon#read 6, iclass 37, count 0 2006.201.06:58:19.94#ibcon#end of sib2, iclass 37, count 0 2006.201.06:58:19.94#ibcon#*after write, iclass 37, count 0 2006.201.06:58:19.94#ibcon#*before return 0, iclass 37, count 0 2006.201.06:58:19.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:19.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:19.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.06:58:19.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.06:58:19.94$vck44/va=7,5 2006.201.06:58:19.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.06:58:19.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.06:58:19.94#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:19.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:20.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:20.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:20.00#ibcon#enter wrdev, iclass 39, count 2 2006.201.06:58:20.00#ibcon#first serial, iclass 39, count 2 2006.201.06:58:20.00#ibcon#enter sib2, iclass 39, count 2 2006.201.06:58:20.00#ibcon#flushed, iclass 39, count 2 2006.201.06:58:20.00#ibcon#about to write, iclass 39, count 2 2006.201.06:58:20.00#ibcon#wrote, iclass 39, count 2 2006.201.06:58:20.00#ibcon#about to read 3, iclass 39, count 2 2006.201.06:58:20.02#ibcon#read 3, iclass 39, count 2 2006.201.06:58:20.02#ibcon#about to read 4, iclass 39, count 2 2006.201.06:58:20.02#ibcon#read 4, iclass 39, count 2 2006.201.06:58:20.02#ibcon#about to read 5, iclass 39, count 2 2006.201.06:58:20.02#ibcon#read 5, iclass 39, count 2 2006.201.06:58:20.02#ibcon#about to read 6, iclass 39, count 2 2006.201.06:58:20.02#ibcon#read 6, iclass 39, count 2 2006.201.06:58:20.02#ibcon#end of sib2, iclass 39, count 2 2006.201.06:58:20.02#ibcon#*mode == 0, iclass 39, count 2 2006.201.06:58:20.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.06:58:20.02#ibcon#[25=AT07-05\r\n] 2006.201.06:58:20.02#ibcon#*before write, iclass 39, count 2 2006.201.06:58:20.02#ibcon#enter sib2, iclass 39, count 2 2006.201.06:58:20.02#ibcon#flushed, iclass 39, count 2 2006.201.06:58:20.02#ibcon#about to write, iclass 39, count 2 2006.201.06:58:20.02#ibcon#wrote, iclass 39, count 2 2006.201.06:58:20.02#ibcon#about to read 3, iclass 39, count 2 2006.201.06:58:20.05#ibcon#read 3, iclass 39, count 2 2006.201.06:58:20.05#ibcon#about to read 4, iclass 39, count 2 2006.201.06:58:20.05#ibcon#read 4, iclass 39, count 2 2006.201.06:58:20.05#ibcon#about to read 5, iclass 39, count 2 2006.201.06:58:20.05#ibcon#read 5, iclass 39, count 2 2006.201.06:58:20.05#ibcon#about to read 6, iclass 39, count 2 2006.201.06:58:20.05#ibcon#read 6, iclass 39, count 2 2006.201.06:58:20.05#ibcon#end of sib2, iclass 39, count 2 2006.201.06:58:20.05#ibcon#*after write, iclass 39, count 2 2006.201.06:58:20.05#ibcon#*before return 0, iclass 39, count 2 2006.201.06:58:20.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:20.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:20.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.06:58:20.05#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:20.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:20.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:20.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:20.17#ibcon#enter wrdev, iclass 39, count 0 2006.201.06:58:20.17#ibcon#first serial, iclass 39, count 0 2006.201.06:58:20.17#ibcon#enter sib2, iclass 39, count 0 2006.201.06:58:20.17#ibcon#flushed, iclass 39, count 0 2006.201.06:58:20.17#ibcon#about to write, iclass 39, count 0 2006.201.06:58:20.17#ibcon#wrote, iclass 39, count 0 2006.201.06:58:20.17#ibcon#about to read 3, iclass 39, count 0 2006.201.06:58:20.19#ibcon#read 3, iclass 39, count 0 2006.201.06:58:20.19#ibcon#about to read 4, iclass 39, count 0 2006.201.06:58:20.19#ibcon#read 4, iclass 39, count 0 2006.201.06:58:20.19#ibcon#about to read 5, iclass 39, count 0 2006.201.06:58:20.19#ibcon#read 5, iclass 39, count 0 2006.201.06:58:20.19#ibcon#about to read 6, iclass 39, count 0 2006.201.06:58:20.19#ibcon#read 6, iclass 39, count 0 2006.201.06:58:20.19#ibcon#end of sib2, iclass 39, count 0 2006.201.06:58:20.19#ibcon#*mode == 0, iclass 39, count 0 2006.201.06:58:20.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.06:58:20.19#ibcon#[25=USB\r\n] 2006.201.06:58:20.19#ibcon#*before write, iclass 39, count 0 2006.201.06:58:20.19#ibcon#enter sib2, iclass 39, count 0 2006.201.06:58:20.19#ibcon#flushed, iclass 39, count 0 2006.201.06:58:20.19#ibcon#about to write, iclass 39, count 0 2006.201.06:58:20.19#ibcon#wrote, iclass 39, count 0 2006.201.06:58:20.19#ibcon#about to read 3, iclass 39, count 0 2006.201.06:58:20.22#ibcon#read 3, iclass 39, count 0 2006.201.06:58:20.22#ibcon#about to read 4, iclass 39, count 0 2006.201.06:58:20.22#ibcon#read 4, iclass 39, count 0 2006.201.06:58:20.22#ibcon#about to read 5, iclass 39, count 0 2006.201.06:58:20.22#ibcon#read 5, iclass 39, count 0 2006.201.06:58:20.22#ibcon#about to read 6, iclass 39, count 0 2006.201.06:58:20.22#ibcon#read 6, iclass 39, count 0 2006.201.06:58:20.22#ibcon#end of sib2, iclass 39, count 0 2006.201.06:58:20.22#ibcon#*after write, iclass 39, count 0 2006.201.06:58:20.22#ibcon#*before return 0, iclass 39, count 0 2006.201.06:58:20.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:20.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:20.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.06:58:20.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.06:58:20.22$vck44/valo=8,884.99 2006.201.06:58:20.22#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.06:58:20.22#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.06:58:20.22#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:20.22#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:20.22#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:20.22#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:20.22#ibcon#enter wrdev, iclass 2, count 0 2006.201.06:58:20.22#ibcon#first serial, iclass 2, count 0 2006.201.06:58:20.22#ibcon#enter sib2, iclass 2, count 0 2006.201.06:58:20.22#ibcon#flushed, iclass 2, count 0 2006.201.06:58:20.22#ibcon#about to write, iclass 2, count 0 2006.201.06:58:20.22#ibcon#wrote, iclass 2, count 0 2006.201.06:58:20.22#ibcon#about to read 3, iclass 2, count 0 2006.201.06:58:20.24#ibcon#read 3, iclass 2, count 0 2006.201.06:58:20.24#ibcon#about to read 4, iclass 2, count 0 2006.201.06:58:20.24#ibcon#read 4, iclass 2, count 0 2006.201.06:58:20.24#ibcon#about to read 5, iclass 2, count 0 2006.201.06:58:20.24#ibcon#read 5, iclass 2, count 0 2006.201.06:58:20.24#ibcon#about to read 6, iclass 2, count 0 2006.201.06:58:20.24#ibcon#read 6, iclass 2, count 0 2006.201.06:58:20.24#ibcon#end of sib2, iclass 2, count 0 2006.201.06:58:20.24#ibcon#*mode == 0, iclass 2, count 0 2006.201.06:58:20.24#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.06:58:20.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.06:58:20.24#ibcon#*before write, iclass 2, count 0 2006.201.06:58:20.24#ibcon#enter sib2, iclass 2, count 0 2006.201.06:58:20.24#ibcon#flushed, iclass 2, count 0 2006.201.06:58:20.24#ibcon#about to write, iclass 2, count 0 2006.201.06:58:20.24#ibcon#wrote, iclass 2, count 0 2006.201.06:58:20.24#ibcon#about to read 3, iclass 2, count 0 2006.201.06:58:20.28#ibcon#read 3, iclass 2, count 0 2006.201.06:58:20.28#ibcon#about to read 4, iclass 2, count 0 2006.201.06:58:20.28#ibcon#read 4, iclass 2, count 0 2006.201.06:58:20.28#ibcon#about to read 5, iclass 2, count 0 2006.201.06:58:20.28#ibcon#read 5, iclass 2, count 0 2006.201.06:58:20.28#ibcon#about to read 6, iclass 2, count 0 2006.201.06:58:20.28#ibcon#read 6, iclass 2, count 0 2006.201.06:58:20.28#ibcon#end of sib2, iclass 2, count 0 2006.201.06:58:20.28#ibcon#*after write, iclass 2, count 0 2006.201.06:58:20.28#ibcon#*before return 0, iclass 2, count 0 2006.201.06:58:20.28#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:20.28#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:20.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.06:58:20.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.06:58:20.28$vck44/va=8,4 2006.201.06:58:20.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.06:58:20.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.06:58:20.28#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:20.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:58:20.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:58:20.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:58:20.34#ibcon#enter wrdev, iclass 5, count 2 2006.201.06:58:20.34#ibcon#first serial, iclass 5, count 2 2006.201.06:58:20.34#ibcon#enter sib2, iclass 5, count 2 2006.201.06:58:20.34#ibcon#flushed, iclass 5, count 2 2006.201.06:58:20.34#ibcon#about to write, iclass 5, count 2 2006.201.06:58:20.34#ibcon#wrote, iclass 5, count 2 2006.201.06:58:20.34#ibcon#about to read 3, iclass 5, count 2 2006.201.06:58:20.36#ibcon#read 3, iclass 5, count 2 2006.201.06:58:20.36#ibcon#about to read 4, iclass 5, count 2 2006.201.06:58:20.36#ibcon#read 4, iclass 5, count 2 2006.201.06:58:20.36#ibcon#about to read 5, iclass 5, count 2 2006.201.06:58:20.36#ibcon#read 5, iclass 5, count 2 2006.201.06:58:20.36#ibcon#about to read 6, iclass 5, count 2 2006.201.06:58:20.36#ibcon#read 6, iclass 5, count 2 2006.201.06:58:20.36#ibcon#end of sib2, iclass 5, count 2 2006.201.06:58:20.36#ibcon#*mode == 0, iclass 5, count 2 2006.201.06:58:20.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.06:58:20.36#ibcon#[25=AT08-04\r\n] 2006.201.06:58:20.36#ibcon#*before write, iclass 5, count 2 2006.201.06:58:20.36#ibcon#enter sib2, iclass 5, count 2 2006.201.06:58:20.36#ibcon#flushed, iclass 5, count 2 2006.201.06:58:20.36#ibcon#about to write, iclass 5, count 2 2006.201.06:58:20.36#ibcon#wrote, iclass 5, count 2 2006.201.06:58:20.36#ibcon#about to read 3, iclass 5, count 2 2006.201.06:58:20.39#ibcon#read 3, iclass 5, count 2 2006.201.06:58:20.39#ibcon#about to read 4, iclass 5, count 2 2006.201.06:58:20.39#ibcon#read 4, iclass 5, count 2 2006.201.06:58:20.39#ibcon#about to read 5, iclass 5, count 2 2006.201.06:58:20.39#ibcon#read 5, iclass 5, count 2 2006.201.06:58:20.39#ibcon#about to read 6, iclass 5, count 2 2006.201.06:58:20.39#ibcon#read 6, iclass 5, count 2 2006.201.06:58:20.39#ibcon#end of sib2, iclass 5, count 2 2006.201.06:58:20.39#ibcon#*after write, iclass 5, count 2 2006.201.06:58:20.39#ibcon#*before return 0, iclass 5, count 2 2006.201.06:58:20.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:58:20.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.06:58:20.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.06:58:20.39#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:20.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:58:20.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:58:20.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:58:20.51#ibcon#enter wrdev, iclass 5, count 0 2006.201.06:58:20.51#ibcon#first serial, iclass 5, count 0 2006.201.06:58:20.51#ibcon#enter sib2, iclass 5, count 0 2006.201.06:58:20.51#ibcon#flushed, iclass 5, count 0 2006.201.06:58:20.51#ibcon#about to write, iclass 5, count 0 2006.201.06:58:20.51#ibcon#wrote, iclass 5, count 0 2006.201.06:58:20.51#ibcon#about to read 3, iclass 5, count 0 2006.201.06:58:20.53#ibcon#read 3, iclass 5, count 0 2006.201.06:58:20.53#ibcon#about to read 4, iclass 5, count 0 2006.201.06:58:20.53#ibcon#read 4, iclass 5, count 0 2006.201.06:58:20.53#ibcon#about to read 5, iclass 5, count 0 2006.201.06:58:20.53#ibcon#read 5, iclass 5, count 0 2006.201.06:58:20.53#ibcon#about to read 6, iclass 5, count 0 2006.201.06:58:20.53#ibcon#read 6, iclass 5, count 0 2006.201.06:58:20.53#ibcon#end of sib2, iclass 5, count 0 2006.201.06:58:20.53#ibcon#*mode == 0, iclass 5, count 0 2006.201.06:58:20.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.06:58:20.53#ibcon#[25=USB\r\n] 2006.201.06:58:20.53#ibcon#*before write, iclass 5, count 0 2006.201.06:58:20.53#ibcon#enter sib2, iclass 5, count 0 2006.201.06:58:20.53#ibcon#flushed, iclass 5, count 0 2006.201.06:58:20.53#ibcon#about to write, iclass 5, count 0 2006.201.06:58:20.53#ibcon#wrote, iclass 5, count 0 2006.201.06:58:20.53#ibcon#about to read 3, iclass 5, count 0 2006.201.06:58:20.56#ibcon#read 3, iclass 5, count 0 2006.201.06:58:20.56#ibcon#about to read 4, iclass 5, count 0 2006.201.06:58:20.56#ibcon#read 4, iclass 5, count 0 2006.201.06:58:20.56#ibcon#about to read 5, iclass 5, count 0 2006.201.06:58:20.56#ibcon#read 5, iclass 5, count 0 2006.201.06:58:20.56#ibcon#about to read 6, iclass 5, count 0 2006.201.06:58:20.56#ibcon#read 6, iclass 5, count 0 2006.201.06:58:20.56#ibcon#end of sib2, iclass 5, count 0 2006.201.06:58:20.56#ibcon#*after write, iclass 5, count 0 2006.201.06:58:20.56#ibcon#*before return 0, iclass 5, count 0 2006.201.06:58:20.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:58:20.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.06:58:20.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.06:58:20.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.06:58:20.56$vck44/vblo=1,629.99 2006.201.06:58:20.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.06:58:20.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.06:58:20.56#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:20.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:58:20.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:58:20.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:58:20.56#ibcon#enter wrdev, iclass 7, count 0 2006.201.06:58:20.56#ibcon#first serial, iclass 7, count 0 2006.201.06:58:20.56#ibcon#enter sib2, iclass 7, count 0 2006.201.06:58:20.56#ibcon#flushed, iclass 7, count 0 2006.201.06:58:20.56#ibcon#about to write, iclass 7, count 0 2006.201.06:58:20.56#ibcon#wrote, iclass 7, count 0 2006.201.06:58:20.56#ibcon#about to read 3, iclass 7, count 0 2006.201.06:58:20.58#ibcon#read 3, iclass 7, count 0 2006.201.06:58:20.58#ibcon#about to read 4, iclass 7, count 0 2006.201.06:58:20.58#ibcon#read 4, iclass 7, count 0 2006.201.06:58:20.58#ibcon#about to read 5, iclass 7, count 0 2006.201.06:58:20.58#ibcon#read 5, iclass 7, count 0 2006.201.06:58:20.58#ibcon#about to read 6, iclass 7, count 0 2006.201.06:58:20.58#ibcon#read 6, iclass 7, count 0 2006.201.06:58:20.58#ibcon#end of sib2, iclass 7, count 0 2006.201.06:58:20.58#ibcon#*mode == 0, iclass 7, count 0 2006.201.06:58:20.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.06:58:20.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.06:58:20.58#ibcon#*before write, iclass 7, count 0 2006.201.06:58:20.58#ibcon#enter sib2, iclass 7, count 0 2006.201.06:58:20.58#ibcon#flushed, iclass 7, count 0 2006.201.06:58:20.58#ibcon#about to write, iclass 7, count 0 2006.201.06:58:20.58#ibcon#wrote, iclass 7, count 0 2006.201.06:58:20.58#ibcon#about to read 3, iclass 7, count 0 2006.201.06:58:20.63#ibcon#read 3, iclass 7, count 0 2006.201.06:58:20.63#ibcon#about to read 4, iclass 7, count 0 2006.201.06:58:20.63#ibcon#read 4, iclass 7, count 0 2006.201.06:58:20.63#ibcon#about to read 5, iclass 7, count 0 2006.201.06:58:20.63#ibcon#read 5, iclass 7, count 0 2006.201.06:58:20.63#ibcon#about to read 6, iclass 7, count 0 2006.201.06:58:20.63#ibcon#read 6, iclass 7, count 0 2006.201.06:58:20.63#ibcon#end of sib2, iclass 7, count 0 2006.201.06:58:20.63#ibcon#*after write, iclass 7, count 0 2006.201.06:58:20.63#ibcon#*before return 0, iclass 7, count 0 2006.201.06:58:20.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:58:20.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.06:58:20.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.06:58:20.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.06:58:20.63$vck44/vb=1,4 2006.201.06:58:20.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.06:58:20.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.06:58:20.63#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:20.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:58:20.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:58:20.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:58:20.63#ibcon#enter wrdev, iclass 11, count 2 2006.201.06:58:20.63#ibcon#first serial, iclass 11, count 2 2006.201.06:58:20.63#ibcon#enter sib2, iclass 11, count 2 2006.201.06:58:20.63#ibcon#flushed, iclass 11, count 2 2006.201.06:58:20.63#ibcon#about to write, iclass 11, count 2 2006.201.06:58:20.63#ibcon#wrote, iclass 11, count 2 2006.201.06:58:20.63#ibcon#about to read 3, iclass 11, count 2 2006.201.06:58:20.65#ibcon#read 3, iclass 11, count 2 2006.201.06:58:20.65#ibcon#about to read 4, iclass 11, count 2 2006.201.06:58:20.65#ibcon#read 4, iclass 11, count 2 2006.201.06:58:20.65#ibcon#about to read 5, iclass 11, count 2 2006.201.06:58:20.65#ibcon#read 5, iclass 11, count 2 2006.201.06:58:20.65#ibcon#about to read 6, iclass 11, count 2 2006.201.06:58:20.65#ibcon#read 6, iclass 11, count 2 2006.201.06:58:20.65#ibcon#end of sib2, iclass 11, count 2 2006.201.06:58:20.65#ibcon#*mode == 0, iclass 11, count 2 2006.201.06:58:20.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.06:58:20.65#ibcon#[27=AT01-04\r\n] 2006.201.06:58:20.65#ibcon#*before write, iclass 11, count 2 2006.201.06:58:20.65#ibcon#enter sib2, iclass 11, count 2 2006.201.06:58:20.65#ibcon#flushed, iclass 11, count 2 2006.201.06:58:20.65#ibcon#about to write, iclass 11, count 2 2006.201.06:58:20.65#ibcon#wrote, iclass 11, count 2 2006.201.06:58:20.65#ibcon#about to read 3, iclass 11, count 2 2006.201.06:58:20.68#ibcon#read 3, iclass 11, count 2 2006.201.06:58:20.68#ibcon#about to read 4, iclass 11, count 2 2006.201.06:58:20.68#ibcon#read 4, iclass 11, count 2 2006.201.06:58:20.68#ibcon#about to read 5, iclass 11, count 2 2006.201.06:58:20.68#ibcon#read 5, iclass 11, count 2 2006.201.06:58:20.68#ibcon#about to read 6, iclass 11, count 2 2006.201.06:58:20.68#ibcon#read 6, iclass 11, count 2 2006.201.06:58:20.68#ibcon#end of sib2, iclass 11, count 2 2006.201.06:58:20.68#ibcon#*after write, iclass 11, count 2 2006.201.06:58:20.68#ibcon#*before return 0, iclass 11, count 2 2006.201.06:58:20.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:58:20.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.06:58:20.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.06:58:20.68#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:20.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:58:20.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:58:20.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:58:20.80#ibcon#enter wrdev, iclass 11, count 0 2006.201.06:58:20.80#ibcon#first serial, iclass 11, count 0 2006.201.06:58:20.80#ibcon#enter sib2, iclass 11, count 0 2006.201.06:58:20.80#ibcon#flushed, iclass 11, count 0 2006.201.06:58:20.80#ibcon#about to write, iclass 11, count 0 2006.201.06:58:20.80#ibcon#wrote, iclass 11, count 0 2006.201.06:58:20.80#ibcon#about to read 3, iclass 11, count 0 2006.201.06:58:20.82#ibcon#read 3, iclass 11, count 0 2006.201.06:58:20.82#ibcon#about to read 4, iclass 11, count 0 2006.201.06:58:20.82#ibcon#read 4, iclass 11, count 0 2006.201.06:58:20.82#ibcon#about to read 5, iclass 11, count 0 2006.201.06:58:20.82#ibcon#read 5, iclass 11, count 0 2006.201.06:58:20.82#ibcon#about to read 6, iclass 11, count 0 2006.201.06:58:20.82#ibcon#read 6, iclass 11, count 0 2006.201.06:58:20.82#ibcon#end of sib2, iclass 11, count 0 2006.201.06:58:20.82#ibcon#*mode == 0, iclass 11, count 0 2006.201.06:58:20.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.06:58:20.82#ibcon#[27=USB\r\n] 2006.201.06:58:20.82#ibcon#*before write, iclass 11, count 0 2006.201.06:58:20.82#ibcon#enter sib2, iclass 11, count 0 2006.201.06:58:20.82#ibcon#flushed, iclass 11, count 0 2006.201.06:58:20.82#ibcon#about to write, iclass 11, count 0 2006.201.06:58:20.82#ibcon#wrote, iclass 11, count 0 2006.201.06:58:20.82#ibcon#about to read 3, iclass 11, count 0 2006.201.06:58:20.85#ibcon#read 3, iclass 11, count 0 2006.201.06:58:20.85#ibcon#about to read 4, iclass 11, count 0 2006.201.06:58:20.85#ibcon#read 4, iclass 11, count 0 2006.201.06:58:20.85#ibcon#about to read 5, iclass 11, count 0 2006.201.06:58:20.85#ibcon#read 5, iclass 11, count 0 2006.201.06:58:20.85#ibcon#about to read 6, iclass 11, count 0 2006.201.06:58:20.85#ibcon#read 6, iclass 11, count 0 2006.201.06:58:20.85#ibcon#end of sib2, iclass 11, count 0 2006.201.06:58:20.85#ibcon#*after write, iclass 11, count 0 2006.201.06:58:20.85#ibcon#*before return 0, iclass 11, count 0 2006.201.06:58:20.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:58:20.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.06:58:20.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.06:58:20.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.06:58:20.85$vck44/vblo=2,634.99 2006.201.06:58:20.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.06:58:20.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.06:58:20.85#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:20.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:20.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:20.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:20.85#ibcon#enter wrdev, iclass 13, count 0 2006.201.06:58:20.85#ibcon#first serial, iclass 13, count 0 2006.201.06:58:20.85#ibcon#enter sib2, iclass 13, count 0 2006.201.06:58:20.85#ibcon#flushed, iclass 13, count 0 2006.201.06:58:20.85#ibcon#about to write, iclass 13, count 0 2006.201.06:58:20.85#ibcon#wrote, iclass 13, count 0 2006.201.06:58:20.85#ibcon#about to read 3, iclass 13, count 0 2006.201.06:58:20.87#ibcon#read 3, iclass 13, count 0 2006.201.06:58:20.87#ibcon#about to read 4, iclass 13, count 0 2006.201.06:58:20.87#ibcon#read 4, iclass 13, count 0 2006.201.06:58:20.87#ibcon#about to read 5, iclass 13, count 0 2006.201.06:58:20.87#ibcon#read 5, iclass 13, count 0 2006.201.06:58:20.87#ibcon#about to read 6, iclass 13, count 0 2006.201.06:58:20.87#ibcon#read 6, iclass 13, count 0 2006.201.06:58:20.87#ibcon#end of sib2, iclass 13, count 0 2006.201.06:58:20.87#ibcon#*mode == 0, iclass 13, count 0 2006.201.06:58:20.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.06:58:20.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.06:58:20.87#ibcon#*before write, iclass 13, count 0 2006.201.06:58:20.87#ibcon#enter sib2, iclass 13, count 0 2006.201.06:58:20.87#ibcon#flushed, iclass 13, count 0 2006.201.06:58:20.87#ibcon#about to write, iclass 13, count 0 2006.201.06:58:20.87#ibcon#wrote, iclass 13, count 0 2006.201.06:58:20.87#ibcon#about to read 3, iclass 13, count 0 2006.201.06:58:20.91#ibcon#read 3, iclass 13, count 0 2006.201.06:58:20.91#ibcon#about to read 4, iclass 13, count 0 2006.201.06:58:20.91#ibcon#read 4, iclass 13, count 0 2006.201.06:58:20.91#ibcon#about to read 5, iclass 13, count 0 2006.201.06:58:20.91#ibcon#read 5, iclass 13, count 0 2006.201.06:58:20.91#ibcon#about to read 6, iclass 13, count 0 2006.201.06:58:20.91#ibcon#read 6, iclass 13, count 0 2006.201.06:58:20.91#ibcon#end of sib2, iclass 13, count 0 2006.201.06:58:20.91#ibcon#*after write, iclass 13, count 0 2006.201.06:58:20.91#ibcon#*before return 0, iclass 13, count 0 2006.201.06:58:20.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:20.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.06:58:20.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.06:58:20.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.06:58:20.91$vck44/vb=2,5 2006.201.06:58:20.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.06:58:20.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.06:58:20.91#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:20.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:20.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:20.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:20.97#ibcon#enter wrdev, iclass 15, count 2 2006.201.06:58:20.97#ibcon#first serial, iclass 15, count 2 2006.201.06:58:20.97#ibcon#enter sib2, iclass 15, count 2 2006.201.06:58:20.97#ibcon#flushed, iclass 15, count 2 2006.201.06:58:20.97#ibcon#about to write, iclass 15, count 2 2006.201.06:58:20.97#ibcon#wrote, iclass 15, count 2 2006.201.06:58:20.97#ibcon#about to read 3, iclass 15, count 2 2006.201.06:58:20.99#ibcon#read 3, iclass 15, count 2 2006.201.06:58:20.99#ibcon#about to read 4, iclass 15, count 2 2006.201.06:58:20.99#ibcon#read 4, iclass 15, count 2 2006.201.06:58:20.99#ibcon#about to read 5, iclass 15, count 2 2006.201.06:58:20.99#ibcon#read 5, iclass 15, count 2 2006.201.06:58:20.99#ibcon#about to read 6, iclass 15, count 2 2006.201.06:58:20.99#ibcon#read 6, iclass 15, count 2 2006.201.06:58:20.99#ibcon#end of sib2, iclass 15, count 2 2006.201.06:58:20.99#ibcon#*mode == 0, iclass 15, count 2 2006.201.06:58:20.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.06:58:20.99#ibcon#[27=AT02-05\r\n] 2006.201.06:58:20.99#ibcon#*before write, iclass 15, count 2 2006.201.06:58:20.99#ibcon#enter sib2, iclass 15, count 2 2006.201.06:58:20.99#ibcon#flushed, iclass 15, count 2 2006.201.06:58:20.99#ibcon#about to write, iclass 15, count 2 2006.201.06:58:20.99#ibcon#wrote, iclass 15, count 2 2006.201.06:58:20.99#ibcon#about to read 3, iclass 15, count 2 2006.201.06:58:21.02#ibcon#read 3, iclass 15, count 2 2006.201.06:58:21.02#ibcon#about to read 4, iclass 15, count 2 2006.201.06:58:21.02#ibcon#read 4, iclass 15, count 2 2006.201.06:58:21.02#ibcon#about to read 5, iclass 15, count 2 2006.201.06:58:21.02#ibcon#read 5, iclass 15, count 2 2006.201.06:58:21.02#ibcon#about to read 6, iclass 15, count 2 2006.201.06:58:21.02#ibcon#read 6, iclass 15, count 2 2006.201.06:58:21.02#ibcon#end of sib2, iclass 15, count 2 2006.201.06:58:21.02#ibcon#*after write, iclass 15, count 2 2006.201.06:58:21.02#ibcon#*before return 0, iclass 15, count 2 2006.201.06:58:21.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:21.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.06:58:21.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.06:58:21.02#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:21.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:21.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:21.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:21.14#ibcon#enter wrdev, iclass 15, count 0 2006.201.06:58:21.14#ibcon#first serial, iclass 15, count 0 2006.201.06:58:21.14#ibcon#enter sib2, iclass 15, count 0 2006.201.06:58:21.14#ibcon#flushed, iclass 15, count 0 2006.201.06:58:21.14#ibcon#about to write, iclass 15, count 0 2006.201.06:58:21.14#ibcon#wrote, iclass 15, count 0 2006.201.06:58:21.14#ibcon#about to read 3, iclass 15, count 0 2006.201.06:58:21.16#ibcon#read 3, iclass 15, count 0 2006.201.06:58:21.16#ibcon#about to read 4, iclass 15, count 0 2006.201.06:58:21.16#ibcon#read 4, iclass 15, count 0 2006.201.06:58:21.16#ibcon#about to read 5, iclass 15, count 0 2006.201.06:58:21.16#ibcon#read 5, iclass 15, count 0 2006.201.06:58:21.16#ibcon#about to read 6, iclass 15, count 0 2006.201.06:58:21.16#ibcon#read 6, iclass 15, count 0 2006.201.06:58:21.16#ibcon#end of sib2, iclass 15, count 0 2006.201.06:58:21.16#ibcon#*mode == 0, iclass 15, count 0 2006.201.06:58:21.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.06:58:21.16#ibcon#[27=USB\r\n] 2006.201.06:58:21.16#ibcon#*before write, iclass 15, count 0 2006.201.06:58:21.16#ibcon#enter sib2, iclass 15, count 0 2006.201.06:58:21.16#ibcon#flushed, iclass 15, count 0 2006.201.06:58:21.16#ibcon#about to write, iclass 15, count 0 2006.201.06:58:21.16#ibcon#wrote, iclass 15, count 0 2006.201.06:58:21.16#ibcon#about to read 3, iclass 15, count 0 2006.201.06:58:21.19#ibcon#read 3, iclass 15, count 0 2006.201.06:58:21.19#ibcon#about to read 4, iclass 15, count 0 2006.201.06:58:21.19#ibcon#read 4, iclass 15, count 0 2006.201.06:58:21.19#ibcon#about to read 5, iclass 15, count 0 2006.201.06:58:21.19#ibcon#read 5, iclass 15, count 0 2006.201.06:58:21.19#ibcon#about to read 6, iclass 15, count 0 2006.201.06:58:21.19#ibcon#read 6, iclass 15, count 0 2006.201.06:58:21.19#ibcon#end of sib2, iclass 15, count 0 2006.201.06:58:21.19#ibcon#*after write, iclass 15, count 0 2006.201.06:58:21.19#ibcon#*before return 0, iclass 15, count 0 2006.201.06:58:21.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:21.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.06:58:21.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.06:58:21.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.06:58:21.19$vck44/vblo=3,649.99 2006.201.06:58:21.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.06:58:21.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.06:58:21.19#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:21.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:21.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:21.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:21.19#ibcon#enter wrdev, iclass 17, count 0 2006.201.06:58:21.19#ibcon#first serial, iclass 17, count 0 2006.201.06:58:21.19#ibcon#enter sib2, iclass 17, count 0 2006.201.06:58:21.19#ibcon#flushed, iclass 17, count 0 2006.201.06:58:21.19#ibcon#about to write, iclass 17, count 0 2006.201.06:58:21.19#ibcon#wrote, iclass 17, count 0 2006.201.06:58:21.19#ibcon#about to read 3, iclass 17, count 0 2006.201.06:58:21.21#ibcon#read 3, iclass 17, count 0 2006.201.06:58:21.21#ibcon#about to read 4, iclass 17, count 0 2006.201.06:58:21.21#ibcon#read 4, iclass 17, count 0 2006.201.06:58:21.21#ibcon#about to read 5, iclass 17, count 0 2006.201.06:58:21.21#ibcon#read 5, iclass 17, count 0 2006.201.06:58:21.21#ibcon#about to read 6, iclass 17, count 0 2006.201.06:58:21.21#ibcon#read 6, iclass 17, count 0 2006.201.06:58:21.21#ibcon#end of sib2, iclass 17, count 0 2006.201.06:58:21.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.06:58:21.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.06:58:21.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.06:58:21.21#ibcon#*before write, iclass 17, count 0 2006.201.06:58:21.21#ibcon#enter sib2, iclass 17, count 0 2006.201.06:58:21.21#ibcon#flushed, iclass 17, count 0 2006.201.06:58:21.21#ibcon#about to write, iclass 17, count 0 2006.201.06:58:21.21#ibcon#wrote, iclass 17, count 0 2006.201.06:58:21.21#ibcon#about to read 3, iclass 17, count 0 2006.201.06:58:21.26#ibcon#read 3, iclass 17, count 0 2006.201.06:58:21.26#ibcon#about to read 4, iclass 17, count 0 2006.201.06:58:21.26#ibcon#read 4, iclass 17, count 0 2006.201.06:58:21.26#ibcon#about to read 5, iclass 17, count 0 2006.201.06:58:21.26#ibcon#read 5, iclass 17, count 0 2006.201.06:58:21.26#ibcon#about to read 6, iclass 17, count 0 2006.201.06:58:21.26#ibcon#read 6, iclass 17, count 0 2006.201.06:58:21.26#ibcon#end of sib2, iclass 17, count 0 2006.201.06:58:21.26#ibcon#*after write, iclass 17, count 0 2006.201.06:58:21.26#ibcon#*before return 0, iclass 17, count 0 2006.201.06:58:21.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:21.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.06:58:21.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.06:58:21.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.06:58:21.26$vck44/vb=3,4 2006.201.06:58:21.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.06:58:21.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.06:58:21.26#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:21.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:21.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:21.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:21.31#ibcon#enter wrdev, iclass 19, count 2 2006.201.06:58:21.31#ibcon#first serial, iclass 19, count 2 2006.201.06:58:21.31#ibcon#enter sib2, iclass 19, count 2 2006.201.06:58:21.31#ibcon#flushed, iclass 19, count 2 2006.201.06:58:21.31#ibcon#about to write, iclass 19, count 2 2006.201.06:58:21.31#ibcon#wrote, iclass 19, count 2 2006.201.06:58:21.31#ibcon#about to read 3, iclass 19, count 2 2006.201.06:58:21.33#ibcon#read 3, iclass 19, count 2 2006.201.06:58:21.33#ibcon#about to read 4, iclass 19, count 2 2006.201.06:58:21.33#ibcon#read 4, iclass 19, count 2 2006.201.06:58:21.33#ibcon#about to read 5, iclass 19, count 2 2006.201.06:58:21.33#ibcon#read 5, iclass 19, count 2 2006.201.06:58:21.33#ibcon#about to read 6, iclass 19, count 2 2006.201.06:58:21.33#ibcon#read 6, iclass 19, count 2 2006.201.06:58:21.33#ibcon#end of sib2, iclass 19, count 2 2006.201.06:58:21.33#ibcon#*mode == 0, iclass 19, count 2 2006.201.06:58:21.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.06:58:21.33#ibcon#[27=AT03-04\r\n] 2006.201.06:58:21.33#ibcon#*before write, iclass 19, count 2 2006.201.06:58:21.33#ibcon#enter sib2, iclass 19, count 2 2006.201.06:58:21.33#ibcon#flushed, iclass 19, count 2 2006.201.06:58:21.33#ibcon#about to write, iclass 19, count 2 2006.201.06:58:21.33#ibcon#wrote, iclass 19, count 2 2006.201.06:58:21.33#ibcon#about to read 3, iclass 19, count 2 2006.201.06:58:21.36#ibcon#read 3, iclass 19, count 2 2006.201.06:58:21.36#ibcon#about to read 4, iclass 19, count 2 2006.201.06:58:21.36#ibcon#read 4, iclass 19, count 2 2006.201.06:58:21.36#ibcon#about to read 5, iclass 19, count 2 2006.201.06:58:21.36#ibcon#read 5, iclass 19, count 2 2006.201.06:58:21.36#ibcon#about to read 6, iclass 19, count 2 2006.201.06:58:21.36#ibcon#read 6, iclass 19, count 2 2006.201.06:58:21.36#ibcon#end of sib2, iclass 19, count 2 2006.201.06:58:21.36#ibcon#*after write, iclass 19, count 2 2006.201.06:58:21.36#ibcon#*before return 0, iclass 19, count 2 2006.201.06:58:21.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:21.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.06:58:21.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.06:58:21.36#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:21.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:21.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:21.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:21.48#ibcon#enter wrdev, iclass 19, count 0 2006.201.06:58:21.48#ibcon#first serial, iclass 19, count 0 2006.201.06:58:21.48#ibcon#enter sib2, iclass 19, count 0 2006.201.06:58:21.48#ibcon#flushed, iclass 19, count 0 2006.201.06:58:21.48#ibcon#about to write, iclass 19, count 0 2006.201.06:58:21.48#ibcon#wrote, iclass 19, count 0 2006.201.06:58:21.48#ibcon#about to read 3, iclass 19, count 0 2006.201.06:58:21.50#ibcon#read 3, iclass 19, count 0 2006.201.06:58:21.50#ibcon#about to read 4, iclass 19, count 0 2006.201.06:58:21.50#ibcon#read 4, iclass 19, count 0 2006.201.06:58:21.50#ibcon#about to read 5, iclass 19, count 0 2006.201.06:58:21.50#ibcon#read 5, iclass 19, count 0 2006.201.06:58:21.50#ibcon#about to read 6, iclass 19, count 0 2006.201.06:58:21.50#ibcon#read 6, iclass 19, count 0 2006.201.06:58:21.50#ibcon#end of sib2, iclass 19, count 0 2006.201.06:58:21.50#ibcon#*mode == 0, iclass 19, count 0 2006.201.06:58:21.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.06:58:21.50#ibcon#[27=USB\r\n] 2006.201.06:58:21.50#ibcon#*before write, iclass 19, count 0 2006.201.06:58:21.50#ibcon#enter sib2, iclass 19, count 0 2006.201.06:58:21.50#ibcon#flushed, iclass 19, count 0 2006.201.06:58:21.50#ibcon#about to write, iclass 19, count 0 2006.201.06:58:21.50#ibcon#wrote, iclass 19, count 0 2006.201.06:58:21.50#ibcon#about to read 3, iclass 19, count 0 2006.201.06:58:21.53#ibcon#read 3, iclass 19, count 0 2006.201.06:58:21.53#ibcon#about to read 4, iclass 19, count 0 2006.201.06:58:21.53#ibcon#read 4, iclass 19, count 0 2006.201.06:58:21.53#ibcon#about to read 5, iclass 19, count 0 2006.201.06:58:21.53#ibcon#read 5, iclass 19, count 0 2006.201.06:58:21.53#ibcon#about to read 6, iclass 19, count 0 2006.201.06:58:21.53#ibcon#read 6, iclass 19, count 0 2006.201.06:58:21.53#ibcon#end of sib2, iclass 19, count 0 2006.201.06:58:21.53#ibcon#*after write, iclass 19, count 0 2006.201.06:58:21.53#ibcon#*before return 0, iclass 19, count 0 2006.201.06:58:21.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:21.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.06:58:21.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.06:58:21.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.06:58:21.53$vck44/vblo=4,679.99 2006.201.06:58:21.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.06:58:21.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.06:58:21.53#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:21.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:21.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:21.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:21.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.06:58:21.53#ibcon#first serial, iclass 21, count 0 2006.201.06:58:21.53#ibcon#enter sib2, iclass 21, count 0 2006.201.06:58:21.53#ibcon#flushed, iclass 21, count 0 2006.201.06:58:21.53#ibcon#about to write, iclass 21, count 0 2006.201.06:58:21.53#ibcon#wrote, iclass 21, count 0 2006.201.06:58:21.53#ibcon#about to read 3, iclass 21, count 0 2006.201.06:58:21.55#ibcon#read 3, iclass 21, count 0 2006.201.06:58:21.55#ibcon#about to read 4, iclass 21, count 0 2006.201.06:58:21.55#ibcon#read 4, iclass 21, count 0 2006.201.06:58:21.55#ibcon#about to read 5, iclass 21, count 0 2006.201.06:58:21.55#ibcon#read 5, iclass 21, count 0 2006.201.06:58:21.55#ibcon#about to read 6, iclass 21, count 0 2006.201.06:58:21.55#ibcon#read 6, iclass 21, count 0 2006.201.06:58:21.55#ibcon#end of sib2, iclass 21, count 0 2006.201.06:58:21.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.06:58:21.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.06:58:21.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.06:58:21.55#ibcon#*before write, iclass 21, count 0 2006.201.06:58:21.55#ibcon#enter sib2, iclass 21, count 0 2006.201.06:58:21.55#ibcon#flushed, iclass 21, count 0 2006.201.06:58:21.55#ibcon#about to write, iclass 21, count 0 2006.201.06:58:21.55#ibcon#wrote, iclass 21, count 0 2006.201.06:58:21.55#ibcon#about to read 3, iclass 21, count 0 2006.201.06:58:21.60#ibcon#read 3, iclass 21, count 0 2006.201.06:58:21.60#ibcon#about to read 4, iclass 21, count 0 2006.201.06:58:21.60#ibcon#read 4, iclass 21, count 0 2006.201.06:58:21.60#ibcon#about to read 5, iclass 21, count 0 2006.201.06:58:21.60#ibcon#read 5, iclass 21, count 0 2006.201.06:58:21.60#ibcon#about to read 6, iclass 21, count 0 2006.201.06:58:21.60#ibcon#read 6, iclass 21, count 0 2006.201.06:58:21.60#ibcon#end of sib2, iclass 21, count 0 2006.201.06:58:21.60#ibcon#*after write, iclass 21, count 0 2006.201.06:58:21.60#ibcon#*before return 0, iclass 21, count 0 2006.201.06:58:21.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:21.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.06:58:21.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.06:58:21.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.06:58:21.60$vck44/vb=4,5 2006.201.06:58:21.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.06:58:21.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.06:58:21.60#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:21.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:21.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:21.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:21.65#ibcon#enter wrdev, iclass 23, count 2 2006.201.06:58:21.65#ibcon#first serial, iclass 23, count 2 2006.201.06:58:21.65#ibcon#enter sib2, iclass 23, count 2 2006.201.06:58:21.65#ibcon#flushed, iclass 23, count 2 2006.201.06:58:21.65#ibcon#about to write, iclass 23, count 2 2006.201.06:58:21.65#ibcon#wrote, iclass 23, count 2 2006.201.06:58:21.65#ibcon#about to read 3, iclass 23, count 2 2006.201.06:58:21.67#ibcon#read 3, iclass 23, count 2 2006.201.06:58:21.67#ibcon#about to read 4, iclass 23, count 2 2006.201.06:58:21.67#ibcon#read 4, iclass 23, count 2 2006.201.06:58:21.67#ibcon#about to read 5, iclass 23, count 2 2006.201.06:58:21.67#ibcon#read 5, iclass 23, count 2 2006.201.06:58:21.67#ibcon#about to read 6, iclass 23, count 2 2006.201.06:58:21.67#ibcon#read 6, iclass 23, count 2 2006.201.06:58:21.67#ibcon#end of sib2, iclass 23, count 2 2006.201.06:58:21.67#ibcon#*mode == 0, iclass 23, count 2 2006.201.06:58:21.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.06:58:21.67#ibcon#[27=AT04-05\r\n] 2006.201.06:58:21.67#ibcon#*before write, iclass 23, count 2 2006.201.06:58:21.67#ibcon#enter sib2, iclass 23, count 2 2006.201.06:58:21.67#ibcon#flushed, iclass 23, count 2 2006.201.06:58:21.67#ibcon#about to write, iclass 23, count 2 2006.201.06:58:21.67#ibcon#wrote, iclass 23, count 2 2006.201.06:58:21.67#ibcon#about to read 3, iclass 23, count 2 2006.201.06:58:21.70#ibcon#read 3, iclass 23, count 2 2006.201.06:58:21.70#ibcon#about to read 4, iclass 23, count 2 2006.201.06:58:21.70#ibcon#read 4, iclass 23, count 2 2006.201.06:58:21.70#ibcon#about to read 5, iclass 23, count 2 2006.201.06:58:21.70#ibcon#read 5, iclass 23, count 2 2006.201.06:58:21.70#ibcon#about to read 6, iclass 23, count 2 2006.201.06:58:21.70#ibcon#read 6, iclass 23, count 2 2006.201.06:58:21.70#ibcon#end of sib2, iclass 23, count 2 2006.201.06:58:21.70#ibcon#*after write, iclass 23, count 2 2006.201.06:58:21.70#ibcon#*before return 0, iclass 23, count 2 2006.201.06:58:21.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:21.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.06:58:21.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.06:58:21.70#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:21.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:21.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:21.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:21.82#ibcon#enter wrdev, iclass 23, count 0 2006.201.06:58:21.82#ibcon#first serial, iclass 23, count 0 2006.201.06:58:21.82#ibcon#enter sib2, iclass 23, count 0 2006.201.06:58:21.82#ibcon#flushed, iclass 23, count 0 2006.201.06:58:21.82#ibcon#about to write, iclass 23, count 0 2006.201.06:58:21.82#ibcon#wrote, iclass 23, count 0 2006.201.06:58:21.82#ibcon#about to read 3, iclass 23, count 0 2006.201.06:58:21.84#ibcon#read 3, iclass 23, count 0 2006.201.06:58:21.84#ibcon#about to read 4, iclass 23, count 0 2006.201.06:58:21.84#ibcon#read 4, iclass 23, count 0 2006.201.06:58:21.84#ibcon#about to read 5, iclass 23, count 0 2006.201.06:58:21.84#ibcon#read 5, iclass 23, count 0 2006.201.06:58:21.84#ibcon#about to read 6, iclass 23, count 0 2006.201.06:58:21.84#ibcon#read 6, iclass 23, count 0 2006.201.06:58:21.84#ibcon#end of sib2, iclass 23, count 0 2006.201.06:58:21.84#ibcon#*mode == 0, iclass 23, count 0 2006.201.06:58:21.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.06:58:21.84#ibcon#[27=USB\r\n] 2006.201.06:58:21.84#ibcon#*before write, iclass 23, count 0 2006.201.06:58:21.84#ibcon#enter sib2, iclass 23, count 0 2006.201.06:58:21.84#ibcon#flushed, iclass 23, count 0 2006.201.06:58:21.84#ibcon#about to write, iclass 23, count 0 2006.201.06:58:21.84#ibcon#wrote, iclass 23, count 0 2006.201.06:58:21.84#ibcon#about to read 3, iclass 23, count 0 2006.201.06:58:21.87#ibcon#read 3, iclass 23, count 0 2006.201.06:58:21.87#ibcon#about to read 4, iclass 23, count 0 2006.201.06:58:21.87#ibcon#read 4, iclass 23, count 0 2006.201.06:58:21.87#ibcon#about to read 5, iclass 23, count 0 2006.201.06:58:21.87#ibcon#read 5, iclass 23, count 0 2006.201.06:58:21.87#ibcon#about to read 6, iclass 23, count 0 2006.201.06:58:21.87#ibcon#read 6, iclass 23, count 0 2006.201.06:58:21.87#ibcon#end of sib2, iclass 23, count 0 2006.201.06:58:21.87#ibcon#*after write, iclass 23, count 0 2006.201.06:58:21.87#ibcon#*before return 0, iclass 23, count 0 2006.201.06:58:21.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:21.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.06:58:21.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.06:58:21.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.06:58:21.87$vck44/vblo=5,709.99 2006.201.06:58:21.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.06:58:21.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.06:58:21.87#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:21.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:21.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:21.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:21.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.06:58:21.87#ibcon#first serial, iclass 25, count 0 2006.201.06:58:21.87#ibcon#enter sib2, iclass 25, count 0 2006.201.06:58:21.87#ibcon#flushed, iclass 25, count 0 2006.201.06:58:21.87#ibcon#about to write, iclass 25, count 0 2006.201.06:58:21.87#ibcon#wrote, iclass 25, count 0 2006.201.06:58:21.87#ibcon#about to read 3, iclass 25, count 0 2006.201.06:58:21.89#ibcon#read 3, iclass 25, count 0 2006.201.06:58:21.89#ibcon#about to read 4, iclass 25, count 0 2006.201.06:58:21.89#ibcon#read 4, iclass 25, count 0 2006.201.06:58:21.89#ibcon#about to read 5, iclass 25, count 0 2006.201.06:58:21.89#ibcon#read 5, iclass 25, count 0 2006.201.06:58:21.89#ibcon#about to read 6, iclass 25, count 0 2006.201.06:58:21.89#ibcon#read 6, iclass 25, count 0 2006.201.06:58:21.89#ibcon#end of sib2, iclass 25, count 0 2006.201.06:58:21.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.06:58:21.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.06:58:21.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.06:58:21.89#ibcon#*before write, iclass 25, count 0 2006.201.06:58:21.89#ibcon#enter sib2, iclass 25, count 0 2006.201.06:58:21.89#ibcon#flushed, iclass 25, count 0 2006.201.06:58:21.89#ibcon#about to write, iclass 25, count 0 2006.201.06:58:21.89#ibcon#wrote, iclass 25, count 0 2006.201.06:58:21.89#ibcon#about to read 3, iclass 25, count 0 2006.201.06:58:21.94#ibcon#read 3, iclass 25, count 0 2006.201.06:58:21.94#ibcon#about to read 4, iclass 25, count 0 2006.201.06:58:21.94#ibcon#read 4, iclass 25, count 0 2006.201.06:58:21.94#ibcon#about to read 5, iclass 25, count 0 2006.201.06:58:21.94#ibcon#read 5, iclass 25, count 0 2006.201.06:58:21.94#ibcon#about to read 6, iclass 25, count 0 2006.201.06:58:21.94#ibcon#read 6, iclass 25, count 0 2006.201.06:58:21.94#ibcon#end of sib2, iclass 25, count 0 2006.201.06:58:21.94#ibcon#*after write, iclass 25, count 0 2006.201.06:58:21.94#ibcon#*before return 0, iclass 25, count 0 2006.201.06:58:21.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:21.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.06:58:21.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.06:58:21.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.06:58:21.94$vck44/vb=5,4 2006.201.06:58:21.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.06:58:21.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.06:58:21.94#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:21.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:21.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:21.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:21.99#ibcon#enter wrdev, iclass 27, count 2 2006.201.06:58:21.99#ibcon#first serial, iclass 27, count 2 2006.201.06:58:21.99#ibcon#enter sib2, iclass 27, count 2 2006.201.06:58:21.99#ibcon#flushed, iclass 27, count 2 2006.201.06:58:21.99#ibcon#about to write, iclass 27, count 2 2006.201.06:58:21.99#ibcon#wrote, iclass 27, count 2 2006.201.06:58:21.99#ibcon#about to read 3, iclass 27, count 2 2006.201.06:58:22.01#ibcon#read 3, iclass 27, count 2 2006.201.06:58:22.01#ibcon#about to read 4, iclass 27, count 2 2006.201.06:58:22.01#ibcon#read 4, iclass 27, count 2 2006.201.06:58:22.01#ibcon#about to read 5, iclass 27, count 2 2006.201.06:58:22.01#ibcon#read 5, iclass 27, count 2 2006.201.06:58:22.01#ibcon#about to read 6, iclass 27, count 2 2006.201.06:58:22.01#ibcon#read 6, iclass 27, count 2 2006.201.06:58:22.01#ibcon#end of sib2, iclass 27, count 2 2006.201.06:58:22.01#ibcon#*mode == 0, iclass 27, count 2 2006.201.06:58:22.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.06:58:22.01#ibcon#[27=AT05-04\r\n] 2006.201.06:58:22.01#ibcon#*before write, iclass 27, count 2 2006.201.06:58:22.01#ibcon#enter sib2, iclass 27, count 2 2006.201.06:58:22.01#ibcon#flushed, iclass 27, count 2 2006.201.06:58:22.01#ibcon#about to write, iclass 27, count 2 2006.201.06:58:22.01#ibcon#wrote, iclass 27, count 2 2006.201.06:58:22.01#ibcon#about to read 3, iclass 27, count 2 2006.201.06:58:22.04#ibcon#read 3, iclass 27, count 2 2006.201.06:58:22.04#ibcon#about to read 4, iclass 27, count 2 2006.201.06:58:22.04#ibcon#read 4, iclass 27, count 2 2006.201.06:58:22.04#ibcon#about to read 5, iclass 27, count 2 2006.201.06:58:22.04#ibcon#read 5, iclass 27, count 2 2006.201.06:58:22.04#ibcon#about to read 6, iclass 27, count 2 2006.201.06:58:22.04#ibcon#read 6, iclass 27, count 2 2006.201.06:58:22.04#ibcon#end of sib2, iclass 27, count 2 2006.201.06:58:22.04#ibcon#*after write, iclass 27, count 2 2006.201.06:58:22.04#ibcon#*before return 0, iclass 27, count 2 2006.201.06:58:22.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:22.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.06:58:22.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.06:58:22.04#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:22.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:22.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:22.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:22.16#ibcon#enter wrdev, iclass 27, count 0 2006.201.06:58:22.16#ibcon#first serial, iclass 27, count 0 2006.201.06:58:22.16#ibcon#enter sib2, iclass 27, count 0 2006.201.06:58:22.16#ibcon#flushed, iclass 27, count 0 2006.201.06:58:22.16#ibcon#about to write, iclass 27, count 0 2006.201.06:58:22.16#ibcon#wrote, iclass 27, count 0 2006.201.06:58:22.16#ibcon#about to read 3, iclass 27, count 0 2006.201.06:58:22.18#ibcon#read 3, iclass 27, count 0 2006.201.06:58:22.18#ibcon#about to read 4, iclass 27, count 0 2006.201.06:58:22.18#ibcon#read 4, iclass 27, count 0 2006.201.06:58:22.18#ibcon#about to read 5, iclass 27, count 0 2006.201.06:58:22.18#ibcon#read 5, iclass 27, count 0 2006.201.06:58:22.18#ibcon#about to read 6, iclass 27, count 0 2006.201.06:58:22.18#ibcon#read 6, iclass 27, count 0 2006.201.06:58:22.18#ibcon#end of sib2, iclass 27, count 0 2006.201.06:58:22.18#ibcon#*mode == 0, iclass 27, count 0 2006.201.06:58:22.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.06:58:22.18#ibcon#[27=USB\r\n] 2006.201.06:58:22.18#ibcon#*before write, iclass 27, count 0 2006.201.06:58:22.18#ibcon#enter sib2, iclass 27, count 0 2006.201.06:58:22.18#ibcon#flushed, iclass 27, count 0 2006.201.06:58:22.18#ibcon#about to write, iclass 27, count 0 2006.201.06:58:22.18#ibcon#wrote, iclass 27, count 0 2006.201.06:58:22.18#ibcon#about to read 3, iclass 27, count 0 2006.201.06:58:22.21#ibcon#read 3, iclass 27, count 0 2006.201.06:58:22.21#ibcon#about to read 4, iclass 27, count 0 2006.201.06:58:22.21#ibcon#read 4, iclass 27, count 0 2006.201.06:58:22.21#ibcon#about to read 5, iclass 27, count 0 2006.201.06:58:22.21#ibcon#read 5, iclass 27, count 0 2006.201.06:58:22.21#ibcon#about to read 6, iclass 27, count 0 2006.201.06:58:22.21#ibcon#read 6, iclass 27, count 0 2006.201.06:58:22.21#ibcon#end of sib2, iclass 27, count 0 2006.201.06:58:22.21#ibcon#*after write, iclass 27, count 0 2006.201.06:58:22.21#ibcon#*before return 0, iclass 27, count 0 2006.201.06:58:22.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:22.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.06:58:22.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.06:58:22.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.06:58:22.21$vck44/vblo=6,719.99 2006.201.06:58:22.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.06:58:22.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.06:58:22.21#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:22.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:22.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:22.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:22.21#ibcon#enter wrdev, iclass 29, count 0 2006.201.06:58:22.21#ibcon#first serial, iclass 29, count 0 2006.201.06:58:22.21#ibcon#enter sib2, iclass 29, count 0 2006.201.06:58:22.21#ibcon#flushed, iclass 29, count 0 2006.201.06:58:22.21#ibcon#about to write, iclass 29, count 0 2006.201.06:58:22.21#ibcon#wrote, iclass 29, count 0 2006.201.06:58:22.21#ibcon#about to read 3, iclass 29, count 0 2006.201.06:58:22.23#ibcon#read 3, iclass 29, count 0 2006.201.06:58:22.23#ibcon#about to read 4, iclass 29, count 0 2006.201.06:58:22.23#ibcon#read 4, iclass 29, count 0 2006.201.06:58:22.23#ibcon#about to read 5, iclass 29, count 0 2006.201.06:58:22.23#ibcon#read 5, iclass 29, count 0 2006.201.06:58:22.23#ibcon#about to read 6, iclass 29, count 0 2006.201.06:58:22.23#ibcon#read 6, iclass 29, count 0 2006.201.06:58:22.23#ibcon#end of sib2, iclass 29, count 0 2006.201.06:58:22.23#ibcon#*mode == 0, iclass 29, count 0 2006.201.06:58:22.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.06:58:22.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.06:58:22.23#ibcon#*before write, iclass 29, count 0 2006.201.06:58:22.23#ibcon#enter sib2, iclass 29, count 0 2006.201.06:58:22.23#ibcon#flushed, iclass 29, count 0 2006.201.06:58:22.23#ibcon#about to write, iclass 29, count 0 2006.201.06:58:22.23#ibcon#wrote, iclass 29, count 0 2006.201.06:58:22.23#ibcon#about to read 3, iclass 29, count 0 2006.201.06:58:22.27#ibcon#read 3, iclass 29, count 0 2006.201.06:58:22.27#ibcon#about to read 4, iclass 29, count 0 2006.201.06:58:22.27#ibcon#read 4, iclass 29, count 0 2006.201.06:58:22.27#ibcon#about to read 5, iclass 29, count 0 2006.201.06:58:22.27#ibcon#read 5, iclass 29, count 0 2006.201.06:58:22.27#ibcon#about to read 6, iclass 29, count 0 2006.201.06:58:22.27#ibcon#read 6, iclass 29, count 0 2006.201.06:58:22.27#ibcon#end of sib2, iclass 29, count 0 2006.201.06:58:22.27#ibcon#*after write, iclass 29, count 0 2006.201.06:58:22.27#ibcon#*before return 0, iclass 29, count 0 2006.201.06:58:22.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:22.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.06:58:22.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.06:58:22.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.06:58:22.27$vck44/vb=6,4 2006.201.06:58:22.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.06:58:22.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.06:58:22.27#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:22.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:22.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:22.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:22.33#ibcon#enter wrdev, iclass 31, count 2 2006.201.06:58:22.33#ibcon#first serial, iclass 31, count 2 2006.201.06:58:22.33#ibcon#enter sib2, iclass 31, count 2 2006.201.06:58:22.33#ibcon#flushed, iclass 31, count 2 2006.201.06:58:22.33#ibcon#about to write, iclass 31, count 2 2006.201.06:58:22.33#ibcon#wrote, iclass 31, count 2 2006.201.06:58:22.33#ibcon#about to read 3, iclass 31, count 2 2006.201.06:58:22.35#ibcon#read 3, iclass 31, count 2 2006.201.06:58:22.35#ibcon#about to read 4, iclass 31, count 2 2006.201.06:58:22.35#ibcon#read 4, iclass 31, count 2 2006.201.06:58:22.35#ibcon#about to read 5, iclass 31, count 2 2006.201.06:58:22.35#ibcon#read 5, iclass 31, count 2 2006.201.06:58:22.35#ibcon#about to read 6, iclass 31, count 2 2006.201.06:58:22.35#ibcon#read 6, iclass 31, count 2 2006.201.06:58:22.35#ibcon#end of sib2, iclass 31, count 2 2006.201.06:58:22.35#ibcon#*mode == 0, iclass 31, count 2 2006.201.06:58:22.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.06:58:22.35#ibcon#[27=AT06-04\r\n] 2006.201.06:58:22.35#ibcon#*before write, iclass 31, count 2 2006.201.06:58:22.35#ibcon#enter sib2, iclass 31, count 2 2006.201.06:58:22.35#ibcon#flushed, iclass 31, count 2 2006.201.06:58:22.35#ibcon#about to write, iclass 31, count 2 2006.201.06:58:22.35#ibcon#wrote, iclass 31, count 2 2006.201.06:58:22.35#ibcon#about to read 3, iclass 31, count 2 2006.201.06:58:22.38#ibcon#read 3, iclass 31, count 2 2006.201.06:58:22.38#ibcon#about to read 4, iclass 31, count 2 2006.201.06:58:22.38#ibcon#read 4, iclass 31, count 2 2006.201.06:58:22.38#ibcon#about to read 5, iclass 31, count 2 2006.201.06:58:22.38#ibcon#read 5, iclass 31, count 2 2006.201.06:58:22.38#ibcon#about to read 6, iclass 31, count 2 2006.201.06:58:22.38#ibcon#read 6, iclass 31, count 2 2006.201.06:58:22.38#ibcon#end of sib2, iclass 31, count 2 2006.201.06:58:22.38#ibcon#*after write, iclass 31, count 2 2006.201.06:58:22.38#ibcon#*before return 0, iclass 31, count 2 2006.201.06:58:22.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:22.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.06:58:22.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.06:58:22.38#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:22.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:22.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:22.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:22.50#ibcon#enter wrdev, iclass 31, count 0 2006.201.06:58:22.50#ibcon#first serial, iclass 31, count 0 2006.201.06:58:22.50#ibcon#enter sib2, iclass 31, count 0 2006.201.06:58:22.50#ibcon#flushed, iclass 31, count 0 2006.201.06:58:22.50#ibcon#about to write, iclass 31, count 0 2006.201.06:58:22.50#ibcon#wrote, iclass 31, count 0 2006.201.06:58:22.50#ibcon#about to read 3, iclass 31, count 0 2006.201.06:58:22.52#ibcon#read 3, iclass 31, count 0 2006.201.06:58:22.52#ibcon#about to read 4, iclass 31, count 0 2006.201.06:58:22.52#ibcon#read 4, iclass 31, count 0 2006.201.06:58:22.52#ibcon#about to read 5, iclass 31, count 0 2006.201.06:58:22.52#ibcon#read 5, iclass 31, count 0 2006.201.06:58:22.52#ibcon#about to read 6, iclass 31, count 0 2006.201.06:58:22.52#ibcon#read 6, iclass 31, count 0 2006.201.06:58:22.52#ibcon#end of sib2, iclass 31, count 0 2006.201.06:58:22.52#ibcon#*mode == 0, iclass 31, count 0 2006.201.06:58:22.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.06:58:22.52#ibcon#[27=USB\r\n] 2006.201.06:58:22.52#ibcon#*before write, iclass 31, count 0 2006.201.06:58:22.52#ibcon#enter sib2, iclass 31, count 0 2006.201.06:58:22.52#ibcon#flushed, iclass 31, count 0 2006.201.06:58:22.52#ibcon#about to write, iclass 31, count 0 2006.201.06:58:22.52#ibcon#wrote, iclass 31, count 0 2006.201.06:58:22.52#ibcon#about to read 3, iclass 31, count 0 2006.201.06:58:22.55#ibcon#read 3, iclass 31, count 0 2006.201.06:58:22.55#ibcon#about to read 4, iclass 31, count 0 2006.201.06:58:22.55#ibcon#read 4, iclass 31, count 0 2006.201.06:58:22.55#ibcon#about to read 5, iclass 31, count 0 2006.201.06:58:22.55#ibcon#read 5, iclass 31, count 0 2006.201.06:58:22.55#ibcon#about to read 6, iclass 31, count 0 2006.201.06:58:22.55#ibcon#read 6, iclass 31, count 0 2006.201.06:58:22.55#ibcon#end of sib2, iclass 31, count 0 2006.201.06:58:22.55#ibcon#*after write, iclass 31, count 0 2006.201.06:58:22.55#ibcon#*before return 0, iclass 31, count 0 2006.201.06:58:22.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:22.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.06:58:22.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.06:58:22.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.06:58:22.55$vck44/vblo=7,734.99 2006.201.06:58:22.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.06:58:22.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.06:58:22.55#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:22.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:22.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:22.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:22.55#ibcon#enter wrdev, iclass 33, count 0 2006.201.06:58:22.55#ibcon#first serial, iclass 33, count 0 2006.201.06:58:22.55#ibcon#enter sib2, iclass 33, count 0 2006.201.06:58:22.55#ibcon#flushed, iclass 33, count 0 2006.201.06:58:22.55#ibcon#about to write, iclass 33, count 0 2006.201.06:58:22.55#ibcon#wrote, iclass 33, count 0 2006.201.06:58:22.55#ibcon#about to read 3, iclass 33, count 0 2006.201.06:58:22.57#ibcon#read 3, iclass 33, count 0 2006.201.06:58:22.57#ibcon#about to read 4, iclass 33, count 0 2006.201.06:58:22.57#ibcon#read 4, iclass 33, count 0 2006.201.06:58:22.57#ibcon#about to read 5, iclass 33, count 0 2006.201.06:58:22.57#ibcon#read 5, iclass 33, count 0 2006.201.06:58:22.57#ibcon#about to read 6, iclass 33, count 0 2006.201.06:58:22.57#ibcon#read 6, iclass 33, count 0 2006.201.06:58:22.57#ibcon#end of sib2, iclass 33, count 0 2006.201.06:58:22.57#ibcon#*mode == 0, iclass 33, count 0 2006.201.06:58:22.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.06:58:22.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.06:58:22.57#ibcon#*before write, iclass 33, count 0 2006.201.06:58:22.57#ibcon#enter sib2, iclass 33, count 0 2006.201.06:58:22.57#ibcon#flushed, iclass 33, count 0 2006.201.06:58:22.57#ibcon#about to write, iclass 33, count 0 2006.201.06:58:22.57#ibcon#wrote, iclass 33, count 0 2006.201.06:58:22.57#ibcon#about to read 3, iclass 33, count 0 2006.201.06:58:22.61#ibcon#read 3, iclass 33, count 0 2006.201.06:58:22.61#ibcon#about to read 4, iclass 33, count 0 2006.201.06:58:22.61#ibcon#read 4, iclass 33, count 0 2006.201.06:58:22.61#ibcon#about to read 5, iclass 33, count 0 2006.201.06:58:22.61#ibcon#read 5, iclass 33, count 0 2006.201.06:58:22.61#ibcon#about to read 6, iclass 33, count 0 2006.201.06:58:22.61#ibcon#read 6, iclass 33, count 0 2006.201.06:58:22.61#ibcon#end of sib2, iclass 33, count 0 2006.201.06:58:22.61#ibcon#*after write, iclass 33, count 0 2006.201.06:58:22.61#ibcon#*before return 0, iclass 33, count 0 2006.201.06:58:22.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:22.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.06:58:22.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.06:58:22.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.06:58:22.61$vck44/vb=7,4 2006.201.06:58:22.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.06:58:22.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.06:58:22.61#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:22.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:22.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:22.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:22.67#ibcon#enter wrdev, iclass 35, count 2 2006.201.06:58:22.67#ibcon#first serial, iclass 35, count 2 2006.201.06:58:22.67#ibcon#enter sib2, iclass 35, count 2 2006.201.06:58:22.67#ibcon#flushed, iclass 35, count 2 2006.201.06:58:22.67#ibcon#about to write, iclass 35, count 2 2006.201.06:58:22.67#ibcon#wrote, iclass 35, count 2 2006.201.06:58:22.67#ibcon#about to read 3, iclass 35, count 2 2006.201.06:58:22.69#ibcon#read 3, iclass 35, count 2 2006.201.06:58:22.69#ibcon#about to read 4, iclass 35, count 2 2006.201.06:58:22.69#ibcon#read 4, iclass 35, count 2 2006.201.06:58:22.69#ibcon#about to read 5, iclass 35, count 2 2006.201.06:58:22.69#ibcon#read 5, iclass 35, count 2 2006.201.06:58:22.69#ibcon#about to read 6, iclass 35, count 2 2006.201.06:58:22.69#ibcon#read 6, iclass 35, count 2 2006.201.06:58:22.69#ibcon#end of sib2, iclass 35, count 2 2006.201.06:58:22.69#ibcon#*mode == 0, iclass 35, count 2 2006.201.06:58:22.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.06:58:22.69#ibcon#[27=AT07-04\r\n] 2006.201.06:58:22.69#ibcon#*before write, iclass 35, count 2 2006.201.06:58:22.69#ibcon#enter sib2, iclass 35, count 2 2006.201.06:58:22.69#ibcon#flushed, iclass 35, count 2 2006.201.06:58:22.69#ibcon#about to write, iclass 35, count 2 2006.201.06:58:22.69#ibcon#wrote, iclass 35, count 2 2006.201.06:58:22.69#ibcon#about to read 3, iclass 35, count 2 2006.201.06:58:22.72#ibcon#read 3, iclass 35, count 2 2006.201.06:58:22.72#ibcon#about to read 4, iclass 35, count 2 2006.201.06:58:22.72#ibcon#read 4, iclass 35, count 2 2006.201.06:58:22.72#ibcon#about to read 5, iclass 35, count 2 2006.201.06:58:22.72#ibcon#read 5, iclass 35, count 2 2006.201.06:58:22.72#ibcon#about to read 6, iclass 35, count 2 2006.201.06:58:22.72#ibcon#read 6, iclass 35, count 2 2006.201.06:58:22.72#ibcon#end of sib2, iclass 35, count 2 2006.201.06:58:22.72#ibcon#*after write, iclass 35, count 2 2006.201.06:58:22.72#ibcon#*before return 0, iclass 35, count 2 2006.201.06:58:22.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:22.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.06:58:22.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.06:58:22.72#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:22.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:22.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:22.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:22.84#ibcon#enter wrdev, iclass 35, count 0 2006.201.06:58:22.84#ibcon#first serial, iclass 35, count 0 2006.201.06:58:22.84#ibcon#enter sib2, iclass 35, count 0 2006.201.06:58:22.84#ibcon#flushed, iclass 35, count 0 2006.201.06:58:22.84#ibcon#about to write, iclass 35, count 0 2006.201.06:58:22.84#ibcon#wrote, iclass 35, count 0 2006.201.06:58:22.84#ibcon#about to read 3, iclass 35, count 0 2006.201.06:58:22.86#ibcon#read 3, iclass 35, count 0 2006.201.06:58:22.86#ibcon#about to read 4, iclass 35, count 0 2006.201.06:58:22.86#ibcon#read 4, iclass 35, count 0 2006.201.06:58:22.86#ibcon#about to read 5, iclass 35, count 0 2006.201.06:58:22.86#ibcon#read 5, iclass 35, count 0 2006.201.06:58:22.86#ibcon#about to read 6, iclass 35, count 0 2006.201.06:58:22.86#ibcon#read 6, iclass 35, count 0 2006.201.06:58:22.86#ibcon#end of sib2, iclass 35, count 0 2006.201.06:58:22.86#ibcon#*mode == 0, iclass 35, count 0 2006.201.06:58:22.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.06:58:22.86#ibcon#[27=USB\r\n] 2006.201.06:58:22.86#ibcon#*before write, iclass 35, count 0 2006.201.06:58:22.86#ibcon#enter sib2, iclass 35, count 0 2006.201.06:58:22.86#ibcon#flushed, iclass 35, count 0 2006.201.06:58:22.86#ibcon#about to write, iclass 35, count 0 2006.201.06:58:22.86#ibcon#wrote, iclass 35, count 0 2006.201.06:58:22.86#ibcon#about to read 3, iclass 35, count 0 2006.201.06:58:22.89#ibcon#read 3, iclass 35, count 0 2006.201.06:58:22.89#ibcon#about to read 4, iclass 35, count 0 2006.201.06:58:22.89#ibcon#read 4, iclass 35, count 0 2006.201.06:58:22.89#ibcon#about to read 5, iclass 35, count 0 2006.201.06:58:22.89#ibcon#read 5, iclass 35, count 0 2006.201.06:58:22.89#ibcon#about to read 6, iclass 35, count 0 2006.201.06:58:22.89#ibcon#read 6, iclass 35, count 0 2006.201.06:58:22.89#ibcon#end of sib2, iclass 35, count 0 2006.201.06:58:22.89#ibcon#*after write, iclass 35, count 0 2006.201.06:58:22.89#ibcon#*before return 0, iclass 35, count 0 2006.201.06:58:22.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:22.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.06:58:22.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.06:58:22.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.06:58:22.89$vck44/vblo=8,744.99 2006.201.06:58:22.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.06:58:22.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.06:58:22.89#ibcon#ireg 17 cls_cnt 0 2006.201.06:58:22.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:22.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:22.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:22.89#ibcon#enter wrdev, iclass 37, count 0 2006.201.06:58:22.89#ibcon#first serial, iclass 37, count 0 2006.201.06:58:22.89#ibcon#enter sib2, iclass 37, count 0 2006.201.06:58:22.89#ibcon#flushed, iclass 37, count 0 2006.201.06:58:22.89#ibcon#about to write, iclass 37, count 0 2006.201.06:58:22.89#ibcon#wrote, iclass 37, count 0 2006.201.06:58:22.89#ibcon#about to read 3, iclass 37, count 0 2006.201.06:58:22.91#ibcon#read 3, iclass 37, count 0 2006.201.06:58:22.91#ibcon#about to read 4, iclass 37, count 0 2006.201.06:58:22.91#ibcon#read 4, iclass 37, count 0 2006.201.06:58:22.91#ibcon#about to read 5, iclass 37, count 0 2006.201.06:58:22.91#ibcon#read 5, iclass 37, count 0 2006.201.06:58:22.91#ibcon#about to read 6, iclass 37, count 0 2006.201.06:58:22.91#ibcon#read 6, iclass 37, count 0 2006.201.06:58:22.91#ibcon#end of sib2, iclass 37, count 0 2006.201.06:58:22.91#ibcon#*mode == 0, iclass 37, count 0 2006.201.06:58:22.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.06:58:22.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.06:58:22.91#ibcon#*before write, iclass 37, count 0 2006.201.06:58:22.91#ibcon#enter sib2, iclass 37, count 0 2006.201.06:58:22.91#ibcon#flushed, iclass 37, count 0 2006.201.06:58:22.91#ibcon#about to write, iclass 37, count 0 2006.201.06:58:22.91#ibcon#wrote, iclass 37, count 0 2006.201.06:58:22.91#ibcon#about to read 3, iclass 37, count 0 2006.201.06:58:22.96#ibcon#read 3, iclass 37, count 0 2006.201.06:58:22.96#ibcon#about to read 4, iclass 37, count 0 2006.201.06:58:22.96#ibcon#read 4, iclass 37, count 0 2006.201.06:58:22.96#ibcon#about to read 5, iclass 37, count 0 2006.201.06:58:22.96#ibcon#read 5, iclass 37, count 0 2006.201.06:58:22.96#ibcon#about to read 6, iclass 37, count 0 2006.201.06:58:22.96#ibcon#read 6, iclass 37, count 0 2006.201.06:58:22.96#ibcon#end of sib2, iclass 37, count 0 2006.201.06:58:22.96#ibcon#*after write, iclass 37, count 0 2006.201.06:58:22.96#ibcon#*before return 0, iclass 37, count 0 2006.201.06:58:22.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:22.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.06:58:22.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.06:58:22.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.06:58:22.96$vck44/vb=8,4 2006.201.06:58:22.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.06:58:22.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.06:58:22.96#ibcon#ireg 11 cls_cnt 2 2006.201.06:58:22.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:23.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:23.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:23.01#ibcon#enter wrdev, iclass 39, count 2 2006.201.06:58:23.01#ibcon#first serial, iclass 39, count 2 2006.201.06:58:23.01#ibcon#enter sib2, iclass 39, count 2 2006.201.06:58:23.01#ibcon#flushed, iclass 39, count 2 2006.201.06:58:23.01#ibcon#about to write, iclass 39, count 2 2006.201.06:58:23.01#ibcon#wrote, iclass 39, count 2 2006.201.06:58:23.01#ibcon#about to read 3, iclass 39, count 2 2006.201.06:58:23.03#ibcon#read 3, iclass 39, count 2 2006.201.06:58:23.03#ibcon#about to read 4, iclass 39, count 2 2006.201.06:58:23.03#ibcon#read 4, iclass 39, count 2 2006.201.06:58:23.03#ibcon#about to read 5, iclass 39, count 2 2006.201.06:58:23.03#ibcon#read 5, iclass 39, count 2 2006.201.06:58:23.03#ibcon#about to read 6, iclass 39, count 2 2006.201.06:58:23.03#ibcon#read 6, iclass 39, count 2 2006.201.06:58:23.03#ibcon#end of sib2, iclass 39, count 2 2006.201.06:58:23.03#ibcon#*mode == 0, iclass 39, count 2 2006.201.06:58:23.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.06:58:23.03#ibcon#[27=AT08-04\r\n] 2006.201.06:58:23.03#ibcon#*before write, iclass 39, count 2 2006.201.06:58:23.03#ibcon#enter sib2, iclass 39, count 2 2006.201.06:58:23.03#ibcon#flushed, iclass 39, count 2 2006.201.06:58:23.03#ibcon#about to write, iclass 39, count 2 2006.201.06:58:23.03#ibcon#wrote, iclass 39, count 2 2006.201.06:58:23.03#ibcon#about to read 3, iclass 39, count 2 2006.201.06:58:23.06#ibcon#read 3, iclass 39, count 2 2006.201.06:58:23.06#ibcon#about to read 4, iclass 39, count 2 2006.201.06:58:23.06#ibcon#read 4, iclass 39, count 2 2006.201.06:58:23.06#ibcon#about to read 5, iclass 39, count 2 2006.201.06:58:23.06#ibcon#read 5, iclass 39, count 2 2006.201.06:58:23.06#ibcon#about to read 6, iclass 39, count 2 2006.201.06:58:23.06#ibcon#read 6, iclass 39, count 2 2006.201.06:58:23.06#ibcon#end of sib2, iclass 39, count 2 2006.201.06:58:23.06#ibcon#*after write, iclass 39, count 2 2006.201.06:58:23.06#ibcon#*before return 0, iclass 39, count 2 2006.201.06:58:23.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:23.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.06:58:23.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.06:58:23.06#ibcon#ireg 7 cls_cnt 0 2006.201.06:58:23.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:23.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:23.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:23.18#ibcon#enter wrdev, iclass 39, count 0 2006.201.06:58:23.18#ibcon#first serial, iclass 39, count 0 2006.201.06:58:23.18#ibcon#enter sib2, iclass 39, count 0 2006.201.06:58:23.18#ibcon#flushed, iclass 39, count 0 2006.201.06:58:23.18#ibcon#about to write, iclass 39, count 0 2006.201.06:58:23.18#ibcon#wrote, iclass 39, count 0 2006.201.06:58:23.18#ibcon#about to read 3, iclass 39, count 0 2006.201.06:58:23.20#ibcon#read 3, iclass 39, count 0 2006.201.06:58:23.20#ibcon#about to read 4, iclass 39, count 0 2006.201.06:58:23.20#ibcon#read 4, iclass 39, count 0 2006.201.06:58:23.20#ibcon#about to read 5, iclass 39, count 0 2006.201.06:58:23.20#ibcon#read 5, iclass 39, count 0 2006.201.06:58:23.20#ibcon#about to read 6, iclass 39, count 0 2006.201.06:58:23.20#ibcon#read 6, iclass 39, count 0 2006.201.06:58:23.20#ibcon#end of sib2, iclass 39, count 0 2006.201.06:58:23.20#ibcon#*mode == 0, iclass 39, count 0 2006.201.06:58:23.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.06:58:23.20#ibcon#[27=USB\r\n] 2006.201.06:58:23.20#ibcon#*before write, iclass 39, count 0 2006.201.06:58:23.20#ibcon#enter sib2, iclass 39, count 0 2006.201.06:58:23.20#ibcon#flushed, iclass 39, count 0 2006.201.06:58:23.20#ibcon#about to write, iclass 39, count 0 2006.201.06:58:23.20#ibcon#wrote, iclass 39, count 0 2006.201.06:58:23.20#ibcon#about to read 3, iclass 39, count 0 2006.201.06:58:23.23#ibcon#read 3, iclass 39, count 0 2006.201.06:58:23.23#ibcon#about to read 4, iclass 39, count 0 2006.201.06:58:23.23#ibcon#read 4, iclass 39, count 0 2006.201.06:58:23.23#ibcon#about to read 5, iclass 39, count 0 2006.201.06:58:23.23#ibcon#read 5, iclass 39, count 0 2006.201.06:58:23.23#ibcon#about to read 6, iclass 39, count 0 2006.201.06:58:23.23#ibcon#read 6, iclass 39, count 0 2006.201.06:58:23.23#ibcon#end of sib2, iclass 39, count 0 2006.201.06:58:23.23#ibcon#*after write, iclass 39, count 0 2006.201.06:58:23.23#ibcon#*before return 0, iclass 39, count 0 2006.201.06:58:23.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:23.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.06:58:23.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.06:58:23.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.06:58:23.23$vck44/vabw=wide 2006.201.06:58:23.23#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.06:58:23.23#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.06:58:23.23#ibcon#ireg 8 cls_cnt 0 2006.201.06:58:23.23#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:23.23#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:23.23#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:23.23#ibcon#enter wrdev, iclass 2, count 0 2006.201.06:58:23.23#ibcon#first serial, iclass 2, count 0 2006.201.06:58:23.23#ibcon#enter sib2, iclass 2, count 0 2006.201.06:58:23.23#ibcon#flushed, iclass 2, count 0 2006.201.06:58:23.23#ibcon#about to write, iclass 2, count 0 2006.201.06:58:23.23#ibcon#wrote, iclass 2, count 0 2006.201.06:58:23.23#ibcon#about to read 3, iclass 2, count 0 2006.201.06:58:23.25#ibcon#read 3, iclass 2, count 0 2006.201.06:58:23.25#ibcon#about to read 4, iclass 2, count 0 2006.201.06:58:23.25#ibcon#read 4, iclass 2, count 0 2006.201.06:58:23.25#ibcon#about to read 5, iclass 2, count 0 2006.201.06:58:23.25#ibcon#read 5, iclass 2, count 0 2006.201.06:58:23.25#ibcon#about to read 6, iclass 2, count 0 2006.201.06:58:23.25#ibcon#read 6, iclass 2, count 0 2006.201.06:58:23.25#ibcon#end of sib2, iclass 2, count 0 2006.201.06:58:23.25#ibcon#*mode == 0, iclass 2, count 0 2006.201.06:58:23.25#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.06:58:23.25#ibcon#[25=BW32\r\n] 2006.201.06:58:23.25#ibcon#*before write, iclass 2, count 0 2006.201.06:58:23.25#ibcon#enter sib2, iclass 2, count 0 2006.201.06:58:23.25#ibcon#flushed, iclass 2, count 0 2006.201.06:58:23.25#ibcon#about to write, iclass 2, count 0 2006.201.06:58:23.25#ibcon#wrote, iclass 2, count 0 2006.201.06:58:23.25#ibcon#about to read 3, iclass 2, count 0 2006.201.06:58:23.28#ibcon#read 3, iclass 2, count 0 2006.201.06:58:23.28#ibcon#about to read 4, iclass 2, count 0 2006.201.06:58:23.28#ibcon#read 4, iclass 2, count 0 2006.201.06:58:23.28#ibcon#about to read 5, iclass 2, count 0 2006.201.06:58:23.28#ibcon#read 5, iclass 2, count 0 2006.201.06:58:23.28#ibcon#about to read 6, iclass 2, count 0 2006.201.06:58:23.28#ibcon#read 6, iclass 2, count 0 2006.201.06:58:23.28#ibcon#end of sib2, iclass 2, count 0 2006.201.06:58:23.28#ibcon#*after write, iclass 2, count 0 2006.201.06:58:23.28#ibcon#*before return 0, iclass 2, count 0 2006.201.06:58:23.28#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:23.28#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.06:58:23.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.06:58:23.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.06:58:23.28$vck44/vbbw=wide 2006.201.06:58:23.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.06:58:23.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.06:58:23.28#ibcon#ireg 8 cls_cnt 0 2006.201.06:58:23.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:58:23.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:58:23.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:58:23.35#ibcon#enter wrdev, iclass 5, count 0 2006.201.06:58:23.35#ibcon#first serial, iclass 5, count 0 2006.201.06:58:23.35#ibcon#enter sib2, iclass 5, count 0 2006.201.06:58:23.35#ibcon#flushed, iclass 5, count 0 2006.201.06:58:23.35#ibcon#about to write, iclass 5, count 0 2006.201.06:58:23.35#ibcon#wrote, iclass 5, count 0 2006.201.06:58:23.35#ibcon#about to read 3, iclass 5, count 0 2006.201.06:58:23.37#ibcon#read 3, iclass 5, count 0 2006.201.06:58:23.37#ibcon#about to read 4, iclass 5, count 0 2006.201.06:58:23.37#ibcon#read 4, iclass 5, count 0 2006.201.06:58:23.37#ibcon#about to read 5, iclass 5, count 0 2006.201.06:58:23.37#ibcon#read 5, iclass 5, count 0 2006.201.06:58:23.37#ibcon#about to read 6, iclass 5, count 0 2006.201.06:58:23.37#ibcon#read 6, iclass 5, count 0 2006.201.06:58:23.37#ibcon#end of sib2, iclass 5, count 0 2006.201.06:58:23.37#ibcon#*mode == 0, iclass 5, count 0 2006.201.06:58:23.37#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.06:58:23.37#ibcon#[27=BW32\r\n] 2006.201.06:58:23.37#ibcon#*before write, iclass 5, count 0 2006.201.06:58:23.37#ibcon#enter sib2, iclass 5, count 0 2006.201.06:58:23.37#ibcon#flushed, iclass 5, count 0 2006.201.06:58:23.37#ibcon#about to write, iclass 5, count 0 2006.201.06:58:23.37#ibcon#wrote, iclass 5, count 0 2006.201.06:58:23.37#ibcon#about to read 3, iclass 5, count 0 2006.201.06:58:23.40#ibcon#read 3, iclass 5, count 0 2006.201.06:58:23.40#ibcon#about to read 4, iclass 5, count 0 2006.201.06:58:23.40#ibcon#read 4, iclass 5, count 0 2006.201.06:58:23.40#ibcon#about to read 5, iclass 5, count 0 2006.201.06:58:23.40#ibcon#read 5, iclass 5, count 0 2006.201.06:58:23.40#ibcon#about to read 6, iclass 5, count 0 2006.201.06:58:23.40#ibcon#read 6, iclass 5, count 0 2006.201.06:58:23.40#ibcon#end of sib2, iclass 5, count 0 2006.201.06:58:23.40#ibcon#*after write, iclass 5, count 0 2006.201.06:58:23.40#ibcon#*before return 0, iclass 5, count 0 2006.201.06:58:23.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:58:23.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.06:58:23.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.06:58:23.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.06:58:23.40$setupk4/ifdk4 2006.201.06:58:23.40$ifdk4/lo= 2006.201.06:58:23.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.06:58:23.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.06:58:23.40$ifdk4/patch= 2006.201.06:58:23.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.06:58:23.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.06:58:23.40$setupk4/!*+20s 2006.201.06:58:26.40#abcon#<5=/05 2.4 4.5 23.19 891003.2\r\n> 2006.201.06:58:26.42#abcon#{5=INTERFACE CLEAR} 2006.201.06:58:26.48#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:58:36.57#abcon#<5=/05 2.4 4.5 23.20 891003.2\r\n> 2006.201.06:58:36.59#abcon#{5=INTERFACE CLEAR} 2006.201.06:58:36.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.06:58:37.87$setupk4/"tpicd 2006.201.06:58:37.87$setupk4/echo=off 2006.201.06:58:37.87$setupk4/xlog=off 2006.201.06:58:37.87:!2006.201.06:59:24 2006.201.06:59:05.14#trakl#Source acquired 2006.201.06:59:07.14#flagr#flagr/antenna,acquired 2006.201.06:59:24.00:preob 2006.201.06:59:24.14/onsource/TRACKING 2006.201.06:59:24.14:!2006.201.06:59:34 2006.201.06:59:34.00:"tape 2006.201.06:59:34.00:"st=record 2006.201.06:59:34.00:data_valid=on 2006.201.06:59:34.00:midob 2006.201.06:59:34.14/onsource/TRACKING 2006.201.06:59:34.14/wx/23.20,1003.2,89 2006.201.06:59:34.27/cable/+6.4659E-03 2006.201.06:59:35.36/va/01,08,usb,yes,30,32 2006.201.06:59:35.36/va/02,07,usb,yes,33,33 2006.201.06:59:35.36/va/03,08,usb,yes,29,31 2006.201.06:59:35.36/va/04,07,usb,yes,33,35 2006.201.06:59:35.36/va/05,04,usb,yes,30,30 2006.201.06:59:35.36/va/06,05,usb,yes,30,30 2006.201.06:59:35.36/va/07,05,usb,yes,29,30 2006.201.06:59:35.36/va/08,04,usb,yes,28,34 2006.201.06:59:35.59/valo/01,524.99,yes,locked 2006.201.06:59:35.59/valo/02,534.99,yes,locked 2006.201.06:59:35.59/valo/03,564.99,yes,locked 2006.201.06:59:35.59/valo/04,624.99,yes,locked 2006.201.06:59:35.59/valo/05,734.99,yes,locked 2006.201.06:59:35.59/valo/06,814.99,yes,locked 2006.201.06:59:35.59/valo/07,864.99,yes,locked 2006.201.06:59:35.59/valo/08,884.99,yes,locked 2006.201.06:59:36.68/vb/01,04,usb,yes,30,28 2006.201.06:59:36.68/vb/02,05,usb,yes,29,28 2006.201.06:59:36.68/vb/03,04,usb,yes,29,32 2006.201.06:59:36.68/vb/04,05,usb,yes,30,29 2006.201.06:59:36.68/vb/05,04,usb,yes,26,29 2006.201.06:59:36.68/vb/06,04,usb,yes,31,27 2006.201.06:59:36.68/vb/07,04,usb,yes,31,30 2006.201.06:59:36.68/vb/08,04,usb,yes,28,31 2006.201.06:59:36.92/vblo/01,629.99,yes,locked 2006.201.06:59:36.92/vblo/02,634.99,yes,locked 2006.201.06:59:36.92/vblo/03,649.99,yes,locked 2006.201.06:59:36.92/vblo/04,679.99,yes,locked 2006.201.06:59:36.92/vblo/05,709.99,yes,locked 2006.201.06:59:36.92/vblo/06,719.99,yes,locked 2006.201.06:59:36.92/vblo/07,734.99,yes,locked 2006.201.06:59:36.92/vblo/08,744.99,yes,locked 2006.201.06:59:37.07/vabw/8 2006.201.06:59:37.22/vbbw/8 2006.201.06:59:37.31/xfe/off,on,15.0 2006.201.06:59:37.68/ifatt/23,28,28,28 2006.201.06:59:38.05/fmout-gps/S +4.54E-07 2006.201.06:59:38.12:!2006.201.07:00:34 2006.201.07:00:34.00:data_valid=off 2006.201.07:00:34.00:"et 2006.201.07:00:34.00:!+3s 2006.201.07:00:37.02:"tape 2006.201.07:00:37.02:postob 2006.201.07:00:37.20/cable/+6.4667E-03 2006.201.07:00:37.20/wx/23.19,1003.2,89 2006.201.07:00:37.28/fmout-gps/S +4.55E-07 2006.201.07:00:37.28:scan_name=201-0704,jd0607,40 2006.201.07:00:37.28:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.201.07:00:38.14#flagr#flagr/antenna,new-source 2006.201.07:00:38.14:checkk5 2006.201.07:00:38.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:00:38.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:00:39.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:00:39.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:00:40.00/chk_obsdata//k5ts1/T2010659??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.07:00:40.36/chk_obsdata//k5ts2/T2010659??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.07:00:40.72/chk_obsdata//k5ts3/T2010659??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.07:00:41.09/chk_obsdata//k5ts4/T2010659??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.07:00:41.77/k5log//k5ts1_log_newline 2006.201.07:00:42.46/k5log//k5ts2_log_newline 2006.201.07:00:43.16/k5log//k5ts3_log_newline 2006.201.07:00:43.85/k5log//k5ts4_log_newline 2006.201.07:00:43.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:00:43.87:setupk4=1 2006.201.07:00:43.87$setupk4/echo=on 2006.201.07:00:43.87$setupk4/pcalon 2006.201.07:00:43.87$pcalon/"no phase cal control is implemented here 2006.201.07:00:43.87$setupk4/"tpicd=stop 2006.201.07:00:43.87$setupk4/"rec=synch_on 2006.201.07:00:43.87$setupk4/"rec_mode=128 2006.201.07:00:43.87$setupk4/!* 2006.201.07:00:43.87$setupk4/recpk4 2006.201.07:00:43.87$recpk4/recpatch= 2006.201.07:00:43.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:00:43.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:00:43.88$setupk4/vck44 2006.201.07:00:43.88$vck44/valo=1,524.99 2006.201.07:00:43.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.07:00:43.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.07:00:43.88#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:43.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:43.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:43.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:43.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:00:43.88#ibcon#first serial, iclass 32, count 0 2006.201.07:00:43.88#ibcon#enter sib2, iclass 32, count 0 2006.201.07:00:43.88#ibcon#flushed, iclass 32, count 0 2006.201.07:00:43.88#ibcon#about to write, iclass 32, count 0 2006.201.07:00:43.88#ibcon#wrote, iclass 32, count 0 2006.201.07:00:43.88#ibcon#about to read 3, iclass 32, count 0 2006.201.07:00:43.91#ibcon#read 3, iclass 32, count 0 2006.201.07:00:43.91#ibcon#about to read 4, iclass 32, count 0 2006.201.07:00:43.91#ibcon#read 4, iclass 32, count 0 2006.201.07:00:43.91#ibcon#about to read 5, iclass 32, count 0 2006.201.07:00:43.91#ibcon#read 5, iclass 32, count 0 2006.201.07:00:43.91#ibcon#about to read 6, iclass 32, count 0 2006.201.07:00:43.91#ibcon#read 6, iclass 32, count 0 2006.201.07:00:43.91#ibcon#end of sib2, iclass 32, count 0 2006.201.07:00:43.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:00:43.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:00:43.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:00:43.91#ibcon#*before write, iclass 32, count 0 2006.201.07:00:43.91#ibcon#enter sib2, iclass 32, count 0 2006.201.07:00:43.91#ibcon#flushed, iclass 32, count 0 2006.201.07:00:43.91#ibcon#about to write, iclass 32, count 0 2006.201.07:00:43.91#ibcon#wrote, iclass 32, count 0 2006.201.07:00:43.91#ibcon#about to read 3, iclass 32, count 0 2006.201.07:00:43.96#ibcon#read 3, iclass 32, count 0 2006.201.07:00:43.96#ibcon#about to read 4, iclass 32, count 0 2006.201.07:00:43.96#ibcon#read 4, iclass 32, count 0 2006.201.07:00:43.96#ibcon#about to read 5, iclass 32, count 0 2006.201.07:00:43.96#ibcon#read 5, iclass 32, count 0 2006.201.07:00:43.96#ibcon#about to read 6, iclass 32, count 0 2006.201.07:00:43.96#ibcon#read 6, iclass 32, count 0 2006.201.07:00:43.96#ibcon#end of sib2, iclass 32, count 0 2006.201.07:00:43.96#ibcon#*after write, iclass 32, count 0 2006.201.07:00:43.96#ibcon#*before return 0, iclass 32, count 0 2006.201.07:00:43.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:43.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:43.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:00:43.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:00:43.96$vck44/va=1,8 2006.201.07:00:43.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.07:00:43.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.07:00:43.96#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:43.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:43.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:43.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:43.96#ibcon#enter wrdev, iclass 34, count 2 2006.201.07:00:43.96#ibcon#first serial, iclass 34, count 2 2006.201.07:00:43.96#ibcon#enter sib2, iclass 34, count 2 2006.201.07:00:43.96#ibcon#flushed, iclass 34, count 2 2006.201.07:00:43.96#ibcon#about to write, iclass 34, count 2 2006.201.07:00:43.96#ibcon#wrote, iclass 34, count 2 2006.201.07:00:43.96#ibcon#about to read 3, iclass 34, count 2 2006.201.07:00:43.98#ibcon#read 3, iclass 34, count 2 2006.201.07:00:43.98#ibcon#about to read 4, iclass 34, count 2 2006.201.07:00:43.98#ibcon#read 4, iclass 34, count 2 2006.201.07:00:43.98#ibcon#about to read 5, iclass 34, count 2 2006.201.07:00:43.98#ibcon#read 5, iclass 34, count 2 2006.201.07:00:43.98#ibcon#about to read 6, iclass 34, count 2 2006.201.07:00:43.98#ibcon#read 6, iclass 34, count 2 2006.201.07:00:43.98#ibcon#end of sib2, iclass 34, count 2 2006.201.07:00:43.98#ibcon#*mode == 0, iclass 34, count 2 2006.201.07:00:43.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.07:00:43.98#ibcon#[25=AT01-08\r\n] 2006.201.07:00:43.98#ibcon#*before write, iclass 34, count 2 2006.201.07:00:43.98#ibcon#enter sib2, iclass 34, count 2 2006.201.07:00:43.98#ibcon#flushed, iclass 34, count 2 2006.201.07:00:43.98#ibcon#about to write, iclass 34, count 2 2006.201.07:00:43.98#ibcon#wrote, iclass 34, count 2 2006.201.07:00:43.98#ibcon#about to read 3, iclass 34, count 2 2006.201.07:00:44.01#ibcon#read 3, iclass 34, count 2 2006.201.07:00:44.01#ibcon#about to read 4, iclass 34, count 2 2006.201.07:00:44.01#ibcon#read 4, iclass 34, count 2 2006.201.07:00:44.01#ibcon#about to read 5, iclass 34, count 2 2006.201.07:00:44.01#ibcon#read 5, iclass 34, count 2 2006.201.07:00:44.01#ibcon#about to read 6, iclass 34, count 2 2006.201.07:00:44.01#ibcon#read 6, iclass 34, count 2 2006.201.07:00:44.01#ibcon#end of sib2, iclass 34, count 2 2006.201.07:00:44.01#ibcon#*after write, iclass 34, count 2 2006.201.07:00:44.01#ibcon#*before return 0, iclass 34, count 2 2006.201.07:00:44.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:44.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:44.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.07:00:44.01#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:44.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:44.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:44.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:44.13#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:00:44.13#ibcon#first serial, iclass 34, count 0 2006.201.07:00:44.13#ibcon#enter sib2, iclass 34, count 0 2006.201.07:00:44.13#ibcon#flushed, iclass 34, count 0 2006.201.07:00:44.13#ibcon#about to write, iclass 34, count 0 2006.201.07:00:44.13#ibcon#wrote, iclass 34, count 0 2006.201.07:00:44.13#ibcon#about to read 3, iclass 34, count 0 2006.201.07:00:44.15#ibcon#read 3, iclass 34, count 0 2006.201.07:00:44.15#ibcon#about to read 4, iclass 34, count 0 2006.201.07:00:44.15#ibcon#read 4, iclass 34, count 0 2006.201.07:00:44.15#ibcon#about to read 5, iclass 34, count 0 2006.201.07:00:44.15#ibcon#read 5, iclass 34, count 0 2006.201.07:00:44.15#ibcon#about to read 6, iclass 34, count 0 2006.201.07:00:44.15#ibcon#read 6, iclass 34, count 0 2006.201.07:00:44.15#ibcon#end of sib2, iclass 34, count 0 2006.201.07:00:44.15#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:00:44.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:00:44.15#ibcon#[25=USB\r\n] 2006.201.07:00:44.15#ibcon#*before write, iclass 34, count 0 2006.201.07:00:44.15#ibcon#enter sib2, iclass 34, count 0 2006.201.07:00:44.15#ibcon#flushed, iclass 34, count 0 2006.201.07:00:44.15#ibcon#about to write, iclass 34, count 0 2006.201.07:00:44.15#ibcon#wrote, iclass 34, count 0 2006.201.07:00:44.15#ibcon#about to read 3, iclass 34, count 0 2006.201.07:00:44.18#ibcon#read 3, iclass 34, count 0 2006.201.07:00:44.18#ibcon#about to read 4, iclass 34, count 0 2006.201.07:00:44.18#ibcon#read 4, iclass 34, count 0 2006.201.07:00:44.18#ibcon#about to read 5, iclass 34, count 0 2006.201.07:00:44.18#ibcon#read 5, iclass 34, count 0 2006.201.07:00:44.18#ibcon#about to read 6, iclass 34, count 0 2006.201.07:00:44.18#ibcon#read 6, iclass 34, count 0 2006.201.07:00:44.18#ibcon#end of sib2, iclass 34, count 0 2006.201.07:00:44.18#ibcon#*after write, iclass 34, count 0 2006.201.07:00:44.18#ibcon#*before return 0, iclass 34, count 0 2006.201.07:00:44.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:44.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:44.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:00:44.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:00:44.18$vck44/valo=2,534.99 2006.201.07:00:44.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.07:00:44.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.07:00:44.18#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:44.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:44.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:44.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:44.18#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:00:44.18#ibcon#first serial, iclass 36, count 0 2006.201.07:00:44.18#ibcon#enter sib2, iclass 36, count 0 2006.201.07:00:44.18#ibcon#flushed, iclass 36, count 0 2006.201.07:00:44.18#ibcon#about to write, iclass 36, count 0 2006.201.07:00:44.18#ibcon#wrote, iclass 36, count 0 2006.201.07:00:44.18#ibcon#about to read 3, iclass 36, count 0 2006.201.07:00:44.20#ibcon#read 3, iclass 36, count 0 2006.201.07:00:44.20#ibcon#about to read 4, iclass 36, count 0 2006.201.07:00:44.20#ibcon#read 4, iclass 36, count 0 2006.201.07:00:44.20#ibcon#about to read 5, iclass 36, count 0 2006.201.07:00:44.20#ibcon#read 5, iclass 36, count 0 2006.201.07:00:44.20#ibcon#about to read 6, iclass 36, count 0 2006.201.07:00:44.20#ibcon#read 6, iclass 36, count 0 2006.201.07:00:44.20#ibcon#end of sib2, iclass 36, count 0 2006.201.07:00:44.20#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:00:44.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:00:44.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:00:44.20#ibcon#*before write, iclass 36, count 0 2006.201.07:00:44.20#ibcon#enter sib2, iclass 36, count 0 2006.201.07:00:44.20#ibcon#flushed, iclass 36, count 0 2006.201.07:00:44.20#ibcon#about to write, iclass 36, count 0 2006.201.07:00:44.20#ibcon#wrote, iclass 36, count 0 2006.201.07:00:44.20#ibcon#about to read 3, iclass 36, count 0 2006.201.07:00:44.25#ibcon#read 3, iclass 36, count 0 2006.201.07:00:44.25#ibcon#about to read 4, iclass 36, count 0 2006.201.07:00:44.25#ibcon#read 4, iclass 36, count 0 2006.201.07:00:44.25#ibcon#about to read 5, iclass 36, count 0 2006.201.07:00:44.25#ibcon#read 5, iclass 36, count 0 2006.201.07:00:44.25#ibcon#about to read 6, iclass 36, count 0 2006.201.07:00:44.25#ibcon#read 6, iclass 36, count 0 2006.201.07:00:44.25#ibcon#end of sib2, iclass 36, count 0 2006.201.07:00:44.25#ibcon#*after write, iclass 36, count 0 2006.201.07:00:44.25#ibcon#*before return 0, iclass 36, count 0 2006.201.07:00:44.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:44.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:44.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:00:44.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:00:44.25$vck44/va=2,7 2006.201.07:00:44.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.07:00:44.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.07:00:44.25#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:44.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:44.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:44.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:44.30#ibcon#enter wrdev, iclass 38, count 2 2006.201.07:00:44.30#ibcon#first serial, iclass 38, count 2 2006.201.07:00:44.30#ibcon#enter sib2, iclass 38, count 2 2006.201.07:00:44.30#ibcon#flushed, iclass 38, count 2 2006.201.07:00:44.30#ibcon#about to write, iclass 38, count 2 2006.201.07:00:44.30#ibcon#wrote, iclass 38, count 2 2006.201.07:00:44.30#ibcon#about to read 3, iclass 38, count 2 2006.201.07:00:44.32#ibcon#read 3, iclass 38, count 2 2006.201.07:00:44.32#ibcon#about to read 4, iclass 38, count 2 2006.201.07:00:44.32#ibcon#read 4, iclass 38, count 2 2006.201.07:00:44.32#ibcon#about to read 5, iclass 38, count 2 2006.201.07:00:44.32#ibcon#read 5, iclass 38, count 2 2006.201.07:00:44.32#ibcon#about to read 6, iclass 38, count 2 2006.201.07:00:44.32#ibcon#read 6, iclass 38, count 2 2006.201.07:00:44.32#ibcon#end of sib2, iclass 38, count 2 2006.201.07:00:44.32#ibcon#*mode == 0, iclass 38, count 2 2006.201.07:00:44.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.07:00:44.32#ibcon#[25=AT02-07\r\n] 2006.201.07:00:44.32#ibcon#*before write, iclass 38, count 2 2006.201.07:00:44.32#ibcon#enter sib2, iclass 38, count 2 2006.201.07:00:44.32#ibcon#flushed, iclass 38, count 2 2006.201.07:00:44.32#ibcon#about to write, iclass 38, count 2 2006.201.07:00:44.32#ibcon#wrote, iclass 38, count 2 2006.201.07:00:44.32#ibcon#about to read 3, iclass 38, count 2 2006.201.07:00:44.35#ibcon#read 3, iclass 38, count 2 2006.201.07:00:44.35#ibcon#about to read 4, iclass 38, count 2 2006.201.07:00:44.35#ibcon#read 4, iclass 38, count 2 2006.201.07:00:44.35#ibcon#about to read 5, iclass 38, count 2 2006.201.07:00:44.35#ibcon#read 5, iclass 38, count 2 2006.201.07:00:44.35#ibcon#about to read 6, iclass 38, count 2 2006.201.07:00:44.35#ibcon#read 6, iclass 38, count 2 2006.201.07:00:44.35#ibcon#end of sib2, iclass 38, count 2 2006.201.07:00:44.35#ibcon#*after write, iclass 38, count 2 2006.201.07:00:44.35#ibcon#*before return 0, iclass 38, count 2 2006.201.07:00:44.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:44.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:44.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.07:00:44.35#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:44.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:44.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:44.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:44.47#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:00:44.47#ibcon#first serial, iclass 38, count 0 2006.201.07:00:44.47#ibcon#enter sib2, iclass 38, count 0 2006.201.07:00:44.47#ibcon#flushed, iclass 38, count 0 2006.201.07:00:44.47#ibcon#about to write, iclass 38, count 0 2006.201.07:00:44.47#ibcon#wrote, iclass 38, count 0 2006.201.07:00:44.47#ibcon#about to read 3, iclass 38, count 0 2006.201.07:00:44.49#ibcon#read 3, iclass 38, count 0 2006.201.07:00:44.49#ibcon#about to read 4, iclass 38, count 0 2006.201.07:00:44.49#ibcon#read 4, iclass 38, count 0 2006.201.07:00:44.49#ibcon#about to read 5, iclass 38, count 0 2006.201.07:00:44.49#ibcon#read 5, iclass 38, count 0 2006.201.07:00:44.49#ibcon#about to read 6, iclass 38, count 0 2006.201.07:00:44.49#ibcon#read 6, iclass 38, count 0 2006.201.07:00:44.49#ibcon#end of sib2, iclass 38, count 0 2006.201.07:00:44.49#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:00:44.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:00:44.49#ibcon#[25=USB\r\n] 2006.201.07:00:44.49#ibcon#*before write, iclass 38, count 0 2006.201.07:00:44.49#ibcon#enter sib2, iclass 38, count 0 2006.201.07:00:44.49#ibcon#flushed, iclass 38, count 0 2006.201.07:00:44.49#ibcon#about to write, iclass 38, count 0 2006.201.07:00:44.49#ibcon#wrote, iclass 38, count 0 2006.201.07:00:44.49#ibcon#about to read 3, iclass 38, count 0 2006.201.07:00:44.52#ibcon#read 3, iclass 38, count 0 2006.201.07:00:44.52#ibcon#about to read 4, iclass 38, count 0 2006.201.07:00:44.52#ibcon#read 4, iclass 38, count 0 2006.201.07:00:44.52#ibcon#about to read 5, iclass 38, count 0 2006.201.07:00:44.52#ibcon#read 5, iclass 38, count 0 2006.201.07:00:44.52#ibcon#about to read 6, iclass 38, count 0 2006.201.07:00:44.52#ibcon#read 6, iclass 38, count 0 2006.201.07:00:44.52#ibcon#end of sib2, iclass 38, count 0 2006.201.07:00:44.52#ibcon#*after write, iclass 38, count 0 2006.201.07:00:44.52#ibcon#*before return 0, iclass 38, count 0 2006.201.07:00:44.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:44.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:44.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:00:44.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:00:44.52$vck44/valo=3,564.99 2006.201.07:00:44.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.07:00:44.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.07:00:44.52#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:44.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:44.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:44.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:44.52#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:00:44.52#ibcon#first serial, iclass 40, count 0 2006.201.07:00:44.52#ibcon#enter sib2, iclass 40, count 0 2006.201.07:00:44.52#ibcon#flushed, iclass 40, count 0 2006.201.07:00:44.52#ibcon#about to write, iclass 40, count 0 2006.201.07:00:44.52#ibcon#wrote, iclass 40, count 0 2006.201.07:00:44.52#ibcon#about to read 3, iclass 40, count 0 2006.201.07:00:44.54#ibcon#read 3, iclass 40, count 0 2006.201.07:00:44.54#ibcon#about to read 4, iclass 40, count 0 2006.201.07:00:44.54#ibcon#read 4, iclass 40, count 0 2006.201.07:00:44.54#ibcon#about to read 5, iclass 40, count 0 2006.201.07:00:44.54#ibcon#read 5, iclass 40, count 0 2006.201.07:00:44.54#ibcon#about to read 6, iclass 40, count 0 2006.201.07:00:44.54#ibcon#read 6, iclass 40, count 0 2006.201.07:00:44.54#ibcon#end of sib2, iclass 40, count 0 2006.201.07:00:44.54#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:00:44.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:00:44.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:00:44.54#ibcon#*before write, iclass 40, count 0 2006.201.07:00:44.54#ibcon#enter sib2, iclass 40, count 0 2006.201.07:00:44.54#ibcon#flushed, iclass 40, count 0 2006.201.07:00:44.54#ibcon#about to write, iclass 40, count 0 2006.201.07:00:44.54#ibcon#wrote, iclass 40, count 0 2006.201.07:00:44.54#ibcon#about to read 3, iclass 40, count 0 2006.201.07:00:44.59#ibcon#read 3, iclass 40, count 0 2006.201.07:00:44.59#ibcon#about to read 4, iclass 40, count 0 2006.201.07:00:44.59#ibcon#read 4, iclass 40, count 0 2006.201.07:00:44.59#ibcon#about to read 5, iclass 40, count 0 2006.201.07:00:44.59#ibcon#read 5, iclass 40, count 0 2006.201.07:00:44.59#ibcon#about to read 6, iclass 40, count 0 2006.201.07:00:44.59#ibcon#read 6, iclass 40, count 0 2006.201.07:00:44.59#ibcon#end of sib2, iclass 40, count 0 2006.201.07:00:44.59#ibcon#*after write, iclass 40, count 0 2006.201.07:00:44.59#ibcon#*before return 0, iclass 40, count 0 2006.201.07:00:44.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:44.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:44.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:00:44.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:00:44.59$vck44/va=3,8 2006.201.07:00:44.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.07:00:44.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.07:00:44.59#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:44.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:44.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:44.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:44.64#ibcon#enter wrdev, iclass 4, count 2 2006.201.07:00:44.64#ibcon#first serial, iclass 4, count 2 2006.201.07:00:44.64#ibcon#enter sib2, iclass 4, count 2 2006.201.07:00:44.64#ibcon#flushed, iclass 4, count 2 2006.201.07:00:44.64#ibcon#about to write, iclass 4, count 2 2006.201.07:00:44.64#ibcon#wrote, iclass 4, count 2 2006.201.07:00:44.64#ibcon#about to read 3, iclass 4, count 2 2006.201.07:00:44.66#ibcon#read 3, iclass 4, count 2 2006.201.07:00:44.66#ibcon#about to read 4, iclass 4, count 2 2006.201.07:00:44.66#ibcon#read 4, iclass 4, count 2 2006.201.07:00:44.66#ibcon#about to read 5, iclass 4, count 2 2006.201.07:00:44.66#ibcon#read 5, iclass 4, count 2 2006.201.07:00:44.66#ibcon#about to read 6, iclass 4, count 2 2006.201.07:00:44.66#ibcon#read 6, iclass 4, count 2 2006.201.07:00:44.66#ibcon#end of sib2, iclass 4, count 2 2006.201.07:00:44.66#ibcon#*mode == 0, iclass 4, count 2 2006.201.07:00:44.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.07:00:44.66#ibcon#[25=AT03-08\r\n] 2006.201.07:00:44.66#ibcon#*before write, iclass 4, count 2 2006.201.07:00:44.66#ibcon#enter sib2, iclass 4, count 2 2006.201.07:00:44.66#ibcon#flushed, iclass 4, count 2 2006.201.07:00:44.66#ibcon#about to write, iclass 4, count 2 2006.201.07:00:44.66#ibcon#wrote, iclass 4, count 2 2006.201.07:00:44.66#ibcon#about to read 3, iclass 4, count 2 2006.201.07:00:44.69#ibcon#read 3, iclass 4, count 2 2006.201.07:00:44.69#ibcon#about to read 4, iclass 4, count 2 2006.201.07:00:44.69#ibcon#read 4, iclass 4, count 2 2006.201.07:00:44.69#ibcon#about to read 5, iclass 4, count 2 2006.201.07:00:44.69#ibcon#read 5, iclass 4, count 2 2006.201.07:00:44.69#ibcon#about to read 6, iclass 4, count 2 2006.201.07:00:44.69#ibcon#read 6, iclass 4, count 2 2006.201.07:00:44.69#ibcon#end of sib2, iclass 4, count 2 2006.201.07:00:44.69#ibcon#*after write, iclass 4, count 2 2006.201.07:00:44.69#ibcon#*before return 0, iclass 4, count 2 2006.201.07:00:44.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:44.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:44.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.07:00:44.69#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:44.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:44.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:44.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:44.81#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:00:44.81#ibcon#first serial, iclass 4, count 0 2006.201.07:00:44.81#ibcon#enter sib2, iclass 4, count 0 2006.201.07:00:44.81#ibcon#flushed, iclass 4, count 0 2006.201.07:00:44.81#ibcon#about to write, iclass 4, count 0 2006.201.07:00:44.81#ibcon#wrote, iclass 4, count 0 2006.201.07:00:44.81#ibcon#about to read 3, iclass 4, count 0 2006.201.07:00:44.83#ibcon#read 3, iclass 4, count 0 2006.201.07:00:44.83#ibcon#about to read 4, iclass 4, count 0 2006.201.07:00:44.83#ibcon#read 4, iclass 4, count 0 2006.201.07:00:44.83#ibcon#about to read 5, iclass 4, count 0 2006.201.07:00:44.83#ibcon#read 5, iclass 4, count 0 2006.201.07:00:44.83#ibcon#about to read 6, iclass 4, count 0 2006.201.07:00:44.83#ibcon#read 6, iclass 4, count 0 2006.201.07:00:44.83#ibcon#end of sib2, iclass 4, count 0 2006.201.07:00:44.83#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:00:44.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:00:44.83#ibcon#[25=USB\r\n] 2006.201.07:00:44.83#ibcon#*before write, iclass 4, count 0 2006.201.07:00:44.83#ibcon#enter sib2, iclass 4, count 0 2006.201.07:00:44.83#ibcon#flushed, iclass 4, count 0 2006.201.07:00:44.83#ibcon#about to write, iclass 4, count 0 2006.201.07:00:44.83#ibcon#wrote, iclass 4, count 0 2006.201.07:00:44.83#ibcon#about to read 3, iclass 4, count 0 2006.201.07:00:44.86#ibcon#read 3, iclass 4, count 0 2006.201.07:00:44.86#ibcon#about to read 4, iclass 4, count 0 2006.201.07:00:44.86#ibcon#read 4, iclass 4, count 0 2006.201.07:00:44.86#ibcon#about to read 5, iclass 4, count 0 2006.201.07:00:44.86#ibcon#read 5, iclass 4, count 0 2006.201.07:00:44.86#ibcon#about to read 6, iclass 4, count 0 2006.201.07:00:44.86#ibcon#read 6, iclass 4, count 0 2006.201.07:00:44.86#ibcon#end of sib2, iclass 4, count 0 2006.201.07:00:44.86#ibcon#*after write, iclass 4, count 0 2006.201.07:00:44.86#ibcon#*before return 0, iclass 4, count 0 2006.201.07:00:44.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:44.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:44.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:00:44.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:00:44.86$vck44/valo=4,624.99 2006.201.07:00:44.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.07:00:44.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.07:00:44.86#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:44.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:44.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:44.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:44.86#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:00:44.86#ibcon#first serial, iclass 6, count 0 2006.201.07:00:44.86#ibcon#enter sib2, iclass 6, count 0 2006.201.07:00:44.86#ibcon#flushed, iclass 6, count 0 2006.201.07:00:44.86#ibcon#about to write, iclass 6, count 0 2006.201.07:00:44.86#ibcon#wrote, iclass 6, count 0 2006.201.07:00:44.86#ibcon#about to read 3, iclass 6, count 0 2006.201.07:00:44.88#ibcon#read 3, iclass 6, count 0 2006.201.07:00:44.88#ibcon#about to read 4, iclass 6, count 0 2006.201.07:00:44.88#ibcon#read 4, iclass 6, count 0 2006.201.07:00:44.88#ibcon#about to read 5, iclass 6, count 0 2006.201.07:00:44.88#ibcon#read 5, iclass 6, count 0 2006.201.07:00:44.88#ibcon#about to read 6, iclass 6, count 0 2006.201.07:00:44.88#ibcon#read 6, iclass 6, count 0 2006.201.07:00:44.88#ibcon#end of sib2, iclass 6, count 0 2006.201.07:00:44.88#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:00:44.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:00:44.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:00:44.88#ibcon#*before write, iclass 6, count 0 2006.201.07:00:44.88#ibcon#enter sib2, iclass 6, count 0 2006.201.07:00:44.88#ibcon#flushed, iclass 6, count 0 2006.201.07:00:44.88#ibcon#about to write, iclass 6, count 0 2006.201.07:00:44.88#ibcon#wrote, iclass 6, count 0 2006.201.07:00:44.88#ibcon#about to read 3, iclass 6, count 0 2006.201.07:00:44.93#ibcon#read 3, iclass 6, count 0 2006.201.07:00:44.93#ibcon#about to read 4, iclass 6, count 0 2006.201.07:00:44.93#ibcon#read 4, iclass 6, count 0 2006.201.07:00:44.93#ibcon#about to read 5, iclass 6, count 0 2006.201.07:00:44.93#ibcon#read 5, iclass 6, count 0 2006.201.07:00:44.93#ibcon#about to read 6, iclass 6, count 0 2006.201.07:00:44.93#ibcon#read 6, iclass 6, count 0 2006.201.07:00:44.93#ibcon#end of sib2, iclass 6, count 0 2006.201.07:00:44.93#ibcon#*after write, iclass 6, count 0 2006.201.07:00:44.93#ibcon#*before return 0, iclass 6, count 0 2006.201.07:00:44.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:44.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:44.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:00:44.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:00:44.93$vck44/va=4,7 2006.201.07:00:44.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.07:00:44.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.07:00:44.93#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:44.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:44.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:44.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:44.98#ibcon#enter wrdev, iclass 10, count 2 2006.201.07:00:44.98#ibcon#first serial, iclass 10, count 2 2006.201.07:00:44.98#ibcon#enter sib2, iclass 10, count 2 2006.201.07:00:44.98#ibcon#flushed, iclass 10, count 2 2006.201.07:00:44.98#ibcon#about to write, iclass 10, count 2 2006.201.07:00:44.98#ibcon#wrote, iclass 10, count 2 2006.201.07:00:44.98#ibcon#about to read 3, iclass 10, count 2 2006.201.07:00:45.00#ibcon#read 3, iclass 10, count 2 2006.201.07:00:45.00#ibcon#about to read 4, iclass 10, count 2 2006.201.07:00:45.00#ibcon#read 4, iclass 10, count 2 2006.201.07:00:45.00#ibcon#about to read 5, iclass 10, count 2 2006.201.07:00:45.00#ibcon#read 5, iclass 10, count 2 2006.201.07:00:45.00#ibcon#about to read 6, iclass 10, count 2 2006.201.07:00:45.00#ibcon#read 6, iclass 10, count 2 2006.201.07:00:45.00#ibcon#end of sib2, iclass 10, count 2 2006.201.07:00:45.00#ibcon#*mode == 0, iclass 10, count 2 2006.201.07:00:45.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.07:00:45.00#ibcon#[25=AT04-07\r\n] 2006.201.07:00:45.00#ibcon#*before write, iclass 10, count 2 2006.201.07:00:45.00#ibcon#enter sib2, iclass 10, count 2 2006.201.07:00:45.00#ibcon#flushed, iclass 10, count 2 2006.201.07:00:45.00#ibcon#about to write, iclass 10, count 2 2006.201.07:00:45.00#ibcon#wrote, iclass 10, count 2 2006.201.07:00:45.00#ibcon#about to read 3, iclass 10, count 2 2006.201.07:00:45.03#ibcon#read 3, iclass 10, count 2 2006.201.07:00:45.03#ibcon#about to read 4, iclass 10, count 2 2006.201.07:00:45.03#ibcon#read 4, iclass 10, count 2 2006.201.07:00:45.03#ibcon#about to read 5, iclass 10, count 2 2006.201.07:00:45.03#ibcon#read 5, iclass 10, count 2 2006.201.07:00:45.03#ibcon#about to read 6, iclass 10, count 2 2006.201.07:00:45.03#ibcon#read 6, iclass 10, count 2 2006.201.07:00:45.03#ibcon#end of sib2, iclass 10, count 2 2006.201.07:00:45.03#ibcon#*after write, iclass 10, count 2 2006.201.07:00:45.03#ibcon#*before return 0, iclass 10, count 2 2006.201.07:00:45.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:45.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:45.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.07:00:45.03#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:45.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:45.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:45.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:45.15#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:00:45.15#ibcon#first serial, iclass 10, count 0 2006.201.07:00:45.15#ibcon#enter sib2, iclass 10, count 0 2006.201.07:00:45.15#ibcon#flushed, iclass 10, count 0 2006.201.07:00:45.15#ibcon#about to write, iclass 10, count 0 2006.201.07:00:45.15#ibcon#wrote, iclass 10, count 0 2006.201.07:00:45.15#ibcon#about to read 3, iclass 10, count 0 2006.201.07:00:45.17#ibcon#read 3, iclass 10, count 0 2006.201.07:00:45.17#ibcon#about to read 4, iclass 10, count 0 2006.201.07:00:45.17#ibcon#read 4, iclass 10, count 0 2006.201.07:00:45.17#ibcon#about to read 5, iclass 10, count 0 2006.201.07:00:45.17#ibcon#read 5, iclass 10, count 0 2006.201.07:00:45.17#ibcon#about to read 6, iclass 10, count 0 2006.201.07:00:45.17#ibcon#read 6, iclass 10, count 0 2006.201.07:00:45.17#ibcon#end of sib2, iclass 10, count 0 2006.201.07:00:45.17#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:00:45.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:00:45.17#ibcon#[25=USB\r\n] 2006.201.07:00:45.17#ibcon#*before write, iclass 10, count 0 2006.201.07:00:45.17#ibcon#enter sib2, iclass 10, count 0 2006.201.07:00:45.17#ibcon#flushed, iclass 10, count 0 2006.201.07:00:45.17#ibcon#about to write, iclass 10, count 0 2006.201.07:00:45.17#ibcon#wrote, iclass 10, count 0 2006.201.07:00:45.17#ibcon#about to read 3, iclass 10, count 0 2006.201.07:00:45.20#ibcon#read 3, iclass 10, count 0 2006.201.07:00:45.20#ibcon#about to read 4, iclass 10, count 0 2006.201.07:00:45.20#ibcon#read 4, iclass 10, count 0 2006.201.07:00:45.20#ibcon#about to read 5, iclass 10, count 0 2006.201.07:00:45.20#ibcon#read 5, iclass 10, count 0 2006.201.07:00:45.20#ibcon#about to read 6, iclass 10, count 0 2006.201.07:00:45.20#ibcon#read 6, iclass 10, count 0 2006.201.07:00:45.20#ibcon#end of sib2, iclass 10, count 0 2006.201.07:00:45.20#ibcon#*after write, iclass 10, count 0 2006.201.07:00:45.20#ibcon#*before return 0, iclass 10, count 0 2006.201.07:00:45.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:45.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:45.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:00:45.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:00:45.20$vck44/valo=5,734.99 2006.201.07:00:45.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.07:00:45.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.07:00:45.20#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:45.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:45.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:45.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:45.20#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:00:45.20#ibcon#first serial, iclass 12, count 0 2006.201.07:00:45.20#ibcon#enter sib2, iclass 12, count 0 2006.201.07:00:45.20#ibcon#flushed, iclass 12, count 0 2006.201.07:00:45.20#ibcon#about to write, iclass 12, count 0 2006.201.07:00:45.20#ibcon#wrote, iclass 12, count 0 2006.201.07:00:45.20#ibcon#about to read 3, iclass 12, count 0 2006.201.07:00:45.22#ibcon#read 3, iclass 12, count 0 2006.201.07:00:45.22#ibcon#about to read 4, iclass 12, count 0 2006.201.07:00:45.22#ibcon#read 4, iclass 12, count 0 2006.201.07:00:45.22#ibcon#about to read 5, iclass 12, count 0 2006.201.07:00:45.22#ibcon#read 5, iclass 12, count 0 2006.201.07:00:45.22#ibcon#about to read 6, iclass 12, count 0 2006.201.07:00:45.22#ibcon#read 6, iclass 12, count 0 2006.201.07:00:45.22#ibcon#end of sib2, iclass 12, count 0 2006.201.07:00:45.22#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:00:45.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:00:45.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:00:45.22#ibcon#*before write, iclass 12, count 0 2006.201.07:00:45.22#ibcon#enter sib2, iclass 12, count 0 2006.201.07:00:45.22#ibcon#flushed, iclass 12, count 0 2006.201.07:00:45.22#ibcon#about to write, iclass 12, count 0 2006.201.07:00:45.22#ibcon#wrote, iclass 12, count 0 2006.201.07:00:45.22#ibcon#about to read 3, iclass 12, count 0 2006.201.07:00:45.26#ibcon#read 3, iclass 12, count 0 2006.201.07:00:45.26#ibcon#about to read 4, iclass 12, count 0 2006.201.07:00:45.26#ibcon#read 4, iclass 12, count 0 2006.201.07:00:45.26#ibcon#about to read 5, iclass 12, count 0 2006.201.07:00:45.26#ibcon#read 5, iclass 12, count 0 2006.201.07:00:45.26#ibcon#about to read 6, iclass 12, count 0 2006.201.07:00:45.26#ibcon#read 6, iclass 12, count 0 2006.201.07:00:45.26#ibcon#end of sib2, iclass 12, count 0 2006.201.07:00:45.26#ibcon#*after write, iclass 12, count 0 2006.201.07:00:45.26#ibcon#*before return 0, iclass 12, count 0 2006.201.07:00:45.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:45.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:45.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:00:45.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:00:45.26$vck44/va=5,4 2006.201.07:00:45.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.07:00:45.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.07:00:45.26#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:45.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:45.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:45.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:45.32#ibcon#enter wrdev, iclass 14, count 2 2006.201.07:00:45.32#ibcon#first serial, iclass 14, count 2 2006.201.07:00:45.32#ibcon#enter sib2, iclass 14, count 2 2006.201.07:00:45.32#ibcon#flushed, iclass 14, count 2 2006.201.07:00:45.32#ibcon#about to write, iclass 14, count 2 2006.201.07:00:45.32#ibcon#wrote, iclass 14, count 2 2006.201.07:00:45.32#ibcon#about to read 3, iclass 14, count 2 2006.201.07:00:45.34#ibcon#read 3, iclass 14, count 2 2006.201.07:00:45.34#ibcon#about to read 4, iclass 14, count 2 2006.201.07:00:45.34#ibcon#read 4, iclass 14, count 2 2006.201.07:00:45.34#ibcon#about to read 5, iclass 14, count 2 2006.201.07:00:45.34#ibcon#read 5, iclass 14, count 2 2006.201.07:00:45.34#ibcon#about to read 6, iclass 14, count 2 2006.201.07:00:45.34#ibcon#read 6, iclass 14, count 2 2006.201.07:00:45.34#ibcon#end of sib2, iclass 14, count 2 2006.201.07:00:45.34#ibcon#*mode == 0, iclass 14, count 2 2006.201.07:00:45.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.07:00:45.34#ibcon#[25=AT05-04\r\n] 2006.201.07:00:45.34#ibcon#*before write, iclass 14, count 2 2006.201.07:00:45.34#ibcon#enter sib2, iclass 14, count 2 2006.201.07:00:45.34#ibcon#flushed, iclass 14, count 2 2006.201.07:00:45.34#ibcon#about to write, iclass 14, count 2 2006.201.07:00:45.34#ibcon#wrote, iclass 14, count 2 2006.201.07:00:45.34#ibcon#about to read 3, iclass 14, count 2 2006.201.07:00:45.37#ibcon#read 3, iclass 14, count 2 2006.201.07:00:45.37#ibcon#about to read 4, iclass 14, count 2 2006.201.07:00:45.37#ibcon#read 4, iclass 14, count 2 2006.201.07:00:45.37#ibcon#about to read 5, iclass 14, count 2 2006.201.07:00:45.37#ibcon#read 5, iclass 14, count 2 2006.201.07:00:45.37#ibcon#about to read 6, iclass 14, count 2 2006.201.07:00:45.37#ibcon#read 6, iclass 14, count 2 2006.201.07:00:45.37#ibcon#end of sib2, iclass 14, count 2 2006.201.07:00:45.37#ibcon#*after write, iclass 14, count 2 2006.201.07:00:45.37#ibcon#*before return 0, iclass 14, count 2 2006.201.07:00:45.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:45.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:45.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.07:00:45.37#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:45.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:45.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:45.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:45.49#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:00:45.49#ibcon#first serial, iclass 14, count 0 2006.201.07:00:45.49#ibcon#enter sib2, iclass 14, count 0 2006.201.07:00:45.49#ibcon#flushed, iclass 14, count 0 2006.201.07:00:45.49#ibcon#about to write, iclass 14, count 0 2006.201.07:00:45.49#ibcon#wrote, iclass 14, count 0 2006.201.07:00:45.49#ibcon#about to read 3, iclass 14, count 0 2006.201.07:00:45.51#ibcon#read 3, iclass 14, count 0 2006.201.07:00:45.51#ibcon#about to read 4, iclass 14, count 0 2006.201.07:00:45.51#ibcon#read 4, iclass 14, count 0 2006.201.07:00:45.51#ibcon#about to read 5, iclass 14, count 0 2006.201.07:00:45.51#ibcon#read 5, iclass 14, count 0 2006.201.07:00:45.51#ibcon#about to read 6, iclass 14, count 0 2006.201.07:00:45.51#ibcon#read 6, iclass 14, count 0 2006.201.07:00:45.51#ibcon#end of sib2, iclass 14, count 0 2006.201.07:00:45.51#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:00:45.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:00:45.51#ibcon#[25=USB\r\n] 2006.201.07:00:45.51#ibcon#*before write, iclass 14, count 0 2006.201.07:00:45.51#ibcon#enter sib2, iclass 14, count 0 2006.201.07:00:45.51#ibcon#flushed, iclass 14, count 0 2006.201.07:00:45.51#ibcon#about to write, iclass 14, count 0 2006.201.07:00:45.51#ibcon#wrote, iclass 14, count 0 2006.201.07:00:45.51#ibcon#about to read 3, iclass 14, count 0 2006.201.07:00:45.54#ibcon#read 3, iclass 14, count 0 2006.201.07:00:45.54#ibcon#about to read 4, iclass 14, count 0 2006.201.07:00:45.54#ibcon#read 4, iclass 14, count 0 2006.201.07:00:45.54#ibcon#about to read 5, iclass 14, count 0 2006.201.07:00:45.54#ibcon#read 5, iclass 14, count 0 2006.201.07:00:45.54#ibcon#about to read 6, iclass 14, count 0 2006.201.07:00:45.54#ibcon#read 6, iclass 14, count 0 2006.201.07:00:45.54#ibcon#end of sib2, iclass 14, count 0 2006.201.07:00:45.54#ibcon#*after write, iclass 14, count 0 2006.201.07:00:45.54#ibcon#*before return 0, iclass 14, count 0 2006.201.07:00:45.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:45.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:45.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:00:45.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:00:45.54$vck44/valo=6,814.99 2006.201.07:00:45.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.07:00:45.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.07:00:45.54#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:45.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:45.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:45.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:45.54#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:00:45.54#ibcon#first serial, iclass 16, count 0 2006.201.07:00:45.54#ibcon#enter sib2, iclass 16, count 0 2006.201.07:00:45.54#ibcon#flushed, iclass 16, count 0 2006.201.07:00:45.54#ibcon#about to write, iclass 16, count 0 2006.201.07:00:45.54#ibcon#wrote, iclass 16, count 0 2006.201.07:00:45.54#ibcon#about to read 3, iclass 16, count 0 2006.201.07:00:45.56#ibcon#read 3, iclass 16, count 0 2006.201.07:00:45.56#ibcon#about to read 4, iclass 16, count 0 2006.201.07:00:45.56#ibcon#read 4, iclass 16, count 0 2006.201.07:00:45.56#ibcon#about to read 5, iclass 16, count 0 2006.201.07:00:45.56#ibcon#read 5, iclass 16, count 0 2006.201.07:00:45.56#ibcon#about to read 6, iclass 16, count 0 2006.201.07:00:45.56#ibcon#read 6, iclass 16, count 0 2006.201.07:00:45.56#ibcon#end of sib2, iclass 16, count 0 2006.201.07:00:45.56#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:00:45.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:00:45.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:00:45.56#ibcon#*before write, iclass 16, count 0 2006.201.07:00:45.56#ibcon#enter sib2, iclass 16, count 0 2006.201.07:00:45.56#ibcon#flushed, iclass 16, count 0 2006.201.07:00:45.56#ibcon#about to write, iclass 16, count 0 2006.201.07:00:45.56#ibcon#wrote, iclass 16, count 0 2006.201.07:00:45.56#ibcon#about to read 3, iclass 16, count 0 2006.201.07:00:45.61#ibcon#read 3, iclass 16, count 0 2006.201.07:00:45.61#ibcon#about to read 4, iclass 16, count 0 2006.201.07:00:45.61#ibcon#read 4, iclass 16, count 0 2006.201.07:00:45.61#ibcon#about to read 5, iclass 16, count 0 2006.201.07:00:45.61#ibcon#read 5, iclass 16, count 0 2006.201.07:00:45.61#ibcon#about to read 6, iclass 16, count 0 2006.201.07:00:45.61#ibcon#read 6, iclass 16, count 0 2006.201.07:00:45.61#ibcon#end of sib2, iclass 16, count 0 2006.201.07:00:45.61#ibcon#*after write, iclass 16, count 0 2006.201.07:00:45.61#ibcon#*before return 0, iclass 16, count 0 2006.201.07:00:45.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:45.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:45.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:00:45.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:00:45.61$vck44/va=6,5 2006.201.07:00:45.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.07:00:45.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.07:00:45.61#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:45.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:45.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:45.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:45.66#ibcon#enter wrdev, iclass 18, count 2 2006.201.07:00:45.66#ibcon#first serial, iclass 18, count 2 2006.201.07:00:45.66#ibcon#enter sib2, iclass 18, count 2 2006.201.07:00:45.66#ibcon#flushed, iclass 18, count 2 2006.201.07:00:45.66#ibcon#about to write, iclass 18, count 2 2006.201.07:00:45.66#ibcon#wrote, iclass 18, count 2 2006.201.07:00:45.66#ibcon#about to read 3, iclass 18, count 2 2006.201.07:00:45.68#ibcon#read 3, iclass 18, count 2 2006.201.07:00:45.68#ibcon#about to read 4, iclass 18, count 2 2006.201.07:00:45.68#ibcon#read 4, iclass 18, count 2 2006.201.07:00:45.68#ibcon#about to read 5, iclass 18, count 2 2006.201.07:00:45.68#ibcon#read 5, iclass 18, count 2 2006.201.07:00:45.68#ibcon#about to read 6, iclass 18, count 2 2006.201.07:00:45.68#ibcon#read 6, iclass 18, count 2 2006.201.07:00:45.68#ibcon#end of sib2, iclass 18, count 2 2006.201.07:00:45.68#ibcon#*mode == 0, iclass 18, count 2 2006.201.07:00:45.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.07:00:45.68#ibcon#[25=AT06-05\r\n] 2006.201.07:00:45.68#ibcon#*before write, iclass 18, count 2 2006.201.07:00:45.68#ibcon#enter sib2, iclass 18, count 2 2006.201.07:00:45.68#ibcon#flushed, iclass 18, count 2 2006.201.07:00:45.68#ibcon#about to write, iclass 18, count 2 2006.201.07:00:45.68#ibcon#wrote, iclass 18, count 2 2006.201.07:00:45.68#ibcon#about to read 3, iclass 18, count 2 2006.201.07:00:45.71#ibcon#read 3, iclass 18, count 2 2006.201.07:00:45.71#ibcon#about to read 4, iclass 18, count 2 2006.201.07:00:45.71#ibcon#read 4, iclass 18, count 2 2006.201.07:00:45.71#ibcon#about to read 5, iclass 18, count 2 2006.201.07:00:45.71#ibcon#read 5, iclass 18, count 2 2006.201.07:00:45.71#ibcon#about to read 6, iclass 18, count 2 2006.201.07:00:45.71#ibcon#read 6, iclass 18, count 2 2006.201.07:00:45.71#ibcon#end of sib2, iclass 18, count 2 2006.201.07:00:45.71#ibcon#*after write, iclass 18, count 2 2006.201.07:00:45.71#ibcon#*before return 0, iclass 18, count 2 2006.201.07:00:45.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:45.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:45.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.07:00:45.71#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:45.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:45.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:45.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:45.83#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:00:45.83#ibcon#first serial, iclass 18, count 0 2006.201.07:00:45.83#ibcon#enter sib2, iclass 18, count 0 2006.201.07:00:45.83#ibcon#flushed, iclass 18, count 0 2006.201.07:00:45.83#ibcon#about to write, iclass 18, count 0 2006.201.07:00:45.83#ibcon#wrote, iclass 18, count 0 2006.201.07:00:45.83#ibcon#about to read 3, iclass 18, count 0 2006.201.07:00:45.85#ibcon#read 3, iclass 18, count 0 2006.201.07:00:45.85#ibcon#about to read 4, iclass 18, count 0 2006.201.07:00:45.85#ibcon#read 4, iclass 18, count 0 2006.201.07:00:45.85#ibcon#about to read 5, iclass 18, count 0 2006.201.07:00:45.85#ibcon#read 5, iclass 18, count 0 2006.201.07:00:45.85#ibcon#about to read 6, iclass 18, count 0 2006.201.07:00:45.85#ibcon#read 6, iclass 18, count 0 2006.201.07:00:45.85#ibcon#end of sib2, iclass 18, count 0 2006.201.07:00:45.85#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:00:45.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:00:45.85#ibcon#[25=USB\r\n] 2006.201.07:00:45.85#ibcon#*before write, iclass 18, count 0 2006.201.07:00:45.85#ibcon#enter sib2, iclass 18, count 0 2006.201.07:00:45.85#ibcon#flushed, iclass 18, count 0 2006.201.07:00:45.85#ibcon#about to write, iclass 18, count 0 2006.201.07:00:45.85#ibcon#wrote, iclass 18, count 0 2006.201.07:00:45.85#ibcon#about to read 3, iclass 18, count 0 2006.201.07:00:45.88#ibcon#read 3, iclass 18, count 0 2006.201.07:00:45.88#ibcon#about to read 4, iclass 18, count 0 2006.201.07:00:45.88#ibcon#read 4, iclass 18, count 0 2006.201.07:00:45.88#ibcon#about to read 5, iclass 18, count 0 2006.201.07:00:45.88#ibcon#read 5, iclass 18, count 0 2006.201.07:00:45.88#ibcon#about to read 6, iclass 18, count 0 2006.201.07:00:45.88#ibcon#read 6, iclass 18, count 0 2006.201.07:00:45.88#ibcon#end of sib2, iclass 18, count 0 2006.201.07:00:45.88#ibcon#*after write, iclass 18, count 0 2006.201.07:00:45.88#ibcon#*before return 0, iclass 18, count 0 2006.201.07:00:45.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:45.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:45.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:00:45.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:00:45.88$vck44/valo=7,864.99 2006.201.07:00:45.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.07:00:45.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.07:00:45.88#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:45.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:00:45.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:00:45.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:00:45.88#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:00:45.88#ibcon#first serial, iclass 20, count 0 2006.201.07:00:45.88#ibcon#enter sib2, iclass 20, count 0 2006.201.07:00:45.88#ibcon#flushed, iclass 20, count 0 2006.201.07:00:45.88#ibcon#about to write, iclass 20, count 0 2006.201.07:00:45.88#ibcon#wrote, iclass 20, count 0 2006.201.07:00:45.88#ibcon#about to read 3, iclass 20, count 0 2006.201.07:00:45.90#ibcon#read 3, iclass 20, count 0 2006.201.07:00:45.90#ibcon#about to read 4, iclass 20, count 0 2006.201.07:00:45.90#ibcon#read 4, iclass 20, count 0 2006.201.07:00:45.90#ibcon#about to read 5, iclass 20, count 0 2006.201.07:00:45.90#ibcon#read 5, iclass 20, count 0 2006.201.07:00:45.90#ibcon#about to read 6, iclass 20, count 0 2006.201.07:00:45.90#ibcon#read 6, iclass 20, count 0 2006.201.07:00:45.90#ibcon#end of sib2, iclass 20, count 0 2006.201.07:00:45.90#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:00:45.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:00:45.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:00:45.90#ibcon#*before write, iclass 20, count 0 2006.201.07:00:45.90#ibcon#enter sib2, iclass 20, count 0 2006.201.07:00:45.90#ibcon#flushed, iclass 20, count 0 2006.201.07:00:45.90#ibcon#about to write, iclass 20, count 0 2006.201.07:00:45.90#ibcon#wrote, iclass 20, count 0 2006.201.07:00:45.90#ibcon#about to read 3, iclass 20, count 0 2006.201.07:00:45.94#ibcon#read 3, iclass 20, count 0 2006.201.07:00:45.94#ibcon#about to read 4, iclass 20, count 0 2006.201.07:00:45.94#ibcon#read 4, iclass 20, count 0 2006.201.07:00:45.94#ibcon#about to read 5, iclass 20, count 0 2006.201.07:00:45.94#ibcon#read 5, iclass 20, count 0 2006.201.07:00:45.94#ibcon#about to read 6, iclass 20, count 0 2006.201.07:00:45.94#ibcon#read 6, iclass 20, count 0 2006.201.07:00:45.94#ibcon#end of sib2, iclass 20, count 0 2006.201.07:00:45.94#ibcon#*after write, iclass 20, count 0 2006.201.07:00:45.94#ibcon#*before return 0, iclass 20, count 0 2006.201.07:00:45.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:00:45.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:00:45.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:00:45.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:00:45.94$vck44/va=7,5 2006.201.07:00:45.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.07:00:45.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.07:00:45.94#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:45.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:00:46.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:00:46.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:00:46.00#ibcon#enter wrdev, iclass 22, count 2 2006.201.07:00:46.00#ibcon#first serial, iclass 22, count 2 2006.201.07:00:46.00#ibcon#enter sib2, iclass 22, count 2 2006.201.07:00:46.00#ibcon#flushed, iclass 22, count 2 2006.201.07:00:46.00#ibcon#about to write, iclass 22, count 2 2006.201.07:00:46.00#ibcon#wrote, iclass 22, count 2 2006.201.07:00:46.00#ibcon#about to read 3, iclass 22, count 2 2006.201.07:00:46.02#ibcon#read 3, iclass 22, count 2 2006.201.07:00:46.02#ibcon#about to read 4, iclass 22, count 2 2006.201.07:00:46.02#ibcon#read 4, iclass 22, count 2 2006.201.07:00:46.02#ibcon#about to read 5, iclass 22, count 2 2006.201.07:00:46.02#ibcon#read 5, iclass 22, count 2 2006.201.07:00:46.02#ibcon#about to read 6, iclass 22, count 2 2006.201.07:00:46.02#ibcon#read 6, iclass 22, count 2 2006.201.07:00:46.02#ibcon#end of sib2, iclass 22, count 2 2006.201.07:00:46.02#ibcon#*mode == 0, iclass 22, count 2 2006.201.07:00:46.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.07:00:46.02#ibcon#[25=AT07-05\r\n] 2006.201.07:00:46.02#ibcon#*before write, iclass 22, count 2 2006.201.07:00:46.02#ibcon#enter sib2, iclass 22, count 2 2006.201.07:00:46.02#ibcon#flushed, iclass 22, count 2 2006.201.07:00:46.02#ibcon#about to write, iclass 22, count 2 2006.201.07:00:46.02#ibcon#wrote, iclass 22, count 2 2006.201.07:00:46.02#ibcon#about to read 3, iclass 22, count 2 2006.201.07:00:46.05#ibcon#read 3, iclass 22, count 2 2006.201.07:00:46.05#ibcon#about to read 4, iclass 22, count 2 2006.201.07:00:46.05#ibcon#read 4, iclass 22, count 2 2006.201.07:00:46.05#ibcon#about to read 5, iclass 22, count 2 2006.201.07:00:46.05#ibcon#read 5, iclass 22, count 2 2006.201.07:00:46.05#ibcon#about to read 6, iclass 22, count 2 2006.201.07:00:46.05#ibcon#read 6, iclass 22, count 2 2006.201.07:00:46.05#ibcon#end of sib2, iclass 22, count 2 2006.201.07:00:46.05#ibcon#*after write, iclass 22, count 2 2006.201.07:00:46.05#ibcon#*before return 0, iclass 22, count 2 2006.201.07:00:46.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:00:46.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:00:46.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.07:00:46.05#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:46.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:00:46.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:00:46.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:00:46.17#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:00:46.17#ibcon#first serial, iclass 22, count 0 2006.201.07:00:46.17#ibcon#enter sib2, iclass 22, count 0 2006.201.07:00:46.17#ibcon#flushed, iclass 22, count 0 2006.201.07:00:46.17#ibcon#about to write, iclass 22, count 0 2006.201.07:00:46.17#ibcon#wrote, iclass 22, count 0 2006.201.07:00:46.17#ibcon#about to read 3, iclass 22, count 0 2006.201.07:00:46.19#ibcon#read 3, iclass 22, count 0 2006.201.07:00:46.19#ibcon#about to read 4, iclass 22, count 0 2006.201.07:00:46.19#ibcon#read 4, iclass 22, count 0 2006.201.07:00:46.19#ibcon#about to read 5, iclass 22, count 0 2006.201.07:00:46.19#ibcon#read 5, iclass 22, count 0 2006.201.07:00:46.19#ibcon#about to read 6, iclass 22, count 0 2006.201.07:00:46.19#ibcon#read 6, iclass 22, count 0 2006.201.07:00:46.19#ibcon#end of sib2, iclass 22, count 0 2006.201.07:00:46.19#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:00:46.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:00:46.19#ibcon#[25=USB\r\n] 2006.201.07:00:46.19#ibcon#*before write, iclass 22, count 0 2006.201.07:00:46.19#ibcon#enter sib2, iclass 22, count 0 2006.201.07:00:46.19#ibcon#flushed, iclass 22, count 0 2006.201.07:00:46.19#ibcon#about to write, iclass 22, count 0 2006.201.07:00:46.19#ibcon#wrote, iclass 22, count 0 2006.201.07:00:46.19#ibcon#about to read 3, iclass 22, count 0 2006.201.07:00:46.22#ibcon#read 3, iclass 22, count 0 2006.201.07:00:46.22#ibcon#about to read 4, iclass 22, count 0 2006.201.07:00:46.22#ibcon#read 4, iclass 22, count 0 2006.201.07:00:46.22#ibcon#about to read 5, iclass 22, count 0 2006.201.07:00:46.22#ibcon#read 5, iclass 22, count 0 2006.201.07:00:46.22#ibcon#about to read 6, iclass 22, count 0 2006.201.07:00:46.22#ibcon#read 6, iclass 22, count 0 2006.201.07:00:46.22#ibcon#end of sib2, iclass 22, count 0 2006.201.07:00:46.22#ibcon#*after write, iclass 22, count 0 2006.201.07:00:46.22#ibcon#*before return 0, iclass 22, count 0 2006.201.07:00:46.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:00:46.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:00:46.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:00:46.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:00:46.22$vck44/valo=8,884.99 2006.201.07:00:46.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.07:00:46.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.07:00:46.22#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:46.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:00:46.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:00:46.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:00:46.22#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:00:46.22#ibcon#first serial, iclass 24, count 0 2006.201.07:00:46.22#ibcon#enter sib2, iclass 24, count 0 2006.201.07:00:46.22#ibcon#flushed, iclass 24, count 0 2006.201.07:00:46.22#ibcon#about to write, iclass 24, count 0 2006.201.07:00:46.22#ibcon#wrote, iclass 24, count 0 2006.201.07:00:46.22#ibcon#about to read 3, iclass 24, count 0 2006.201.07:00:46.24#ibcon#read 3, iclass 24, count 0 2006.201.07:00:46.24#ibcon#about to read 4, iclass 24, count 0 2006.201.07:00:46.24#ibcon#read 4, iclass 24, count 0 2006.201.07:00:46.24#ibcon#about to read 5, iclass 24, count 0 2006.201.07:00:46.24#ibcon#read 5, iclass 24, count 0 2006.201.07:00:46.24#ibcon#about to read 6, iclass 24, count 0 2006.201.07:00:46.24#ibcon#read 6, iclass 24, count 0 2006.201.07:00:46.24#ibcon#end of sib2, iclass 24, count 0 2006.201.07:00:46.24#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:00:46.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:00:46.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:00:46.24#ibcon#*before write, iclass 24, count 0 2006.201.07:00:46.24#ibcon#enter sib2, iclass 24, count 0 2006.201.07:00:46.24#ibcon#flushed, iclass 24, count 0 2006.201.07:00:46.24#ibcon#about to write, iclass 24, count 0 2006.201.07:00:46.24#ibcon#wrote, iclass 24, count 0 2006.201.07:00:46.24#ibcon#about to read 3, iclass 24, count 0 2006.201.07:00:46.28#ibcon#read 3, iclass 24, count 0 2006.201.07:00:46.28#ibcon#about to read 4, iclass 24, count 0 2006.201.07:00:46.28#ibcon#read 4, iclass 24, count 0 2006.201.07:00:46.28#ibcon#about to read 5, iclass 24, count 0 2006.201.07:00:46.28#ibcon#read 5, iclass 24, count 0 2006.201.07:00:46.28#ibcon#about to read 6, iclass 24, count 0 2006.201.07:00:46.28#ibcon#read 6, iclass 24, count 0 2006.201.07:00:46.28#ibcon#end of sib2, iclass 24, count 0 2006.201.07:00:46.28#ibcon#*after write, iclass 24, count 0 2006.201.07:00:46.28#ibcon#*before return 0, iclass 24, count 0 2006.201.07:00:46.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:00:46.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:00:46.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:00:46.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:00:46.28$vck44/va=8,4 2006.201.07:00:46.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.07:00:46.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.07:00:46.28#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:46.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:00:46.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:00:46.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:00:46.34#ibcon#enter wrdev, iclass 26, count 2 2006.201.07:00:46.34#ibcon#first serial, iclass 26, count 2 2006.201.07:00:46.34#ibcon#enter sib2, iclass 26, count 2 2006.201.07:00:46.34#ibcon#flushed, iclass 26, count 2 2006.201.07:00:46.34#ibcon#about to write, iclass 26, count 2 2006.201.07:00:46.34#ibcon#wrote, iclass 26, count 2 2006.201.07:00:46.34#ibcon#about to read 3, iclass 26, count 2 2006.201.07:00:46.36#ibcon#read 3, iclass 26, count 2 2006.201.07:00:46.36#ibcon#about to read 4, iclass 26, count 2 2006.201.07:00:46.36#ibcon#read 4, iclass 26, count 2 2006.201.07:00:46.36#ibcon#about to read 5, iclass 26, count 2 2006.201.07:00:46.36#ibcon#read 5, iclass 26, count 2 2006.201.07:00:46.36#ibcon#about to read 6, iclass 26, count 2 2006.201.07:00:46.36#ibcon#read 6, iclass 26, count 2 2006.201.07:00:46.36#ibcon#end of sib2, iclass 26, count 2 2006.201.07:00:46.36#ibcon#*mode == 0, iclass 26, count 2 2006.201.07:00:46.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.07:00:46.36#ibcon#[25=AT08-04\r\n] 2006.201.07:00:46.36#ibcon#*before write, iclass 26, count 2 2006.201.07:00:46.36#ibcon#enter sib2, iclass 26, count 2 2006.201.07:00:46.36#ibcon#flushed, iclass 26, count 2 2006.201.07:00:46.36#ibcon#about to write, iclass 26, count 2 2006.201.07:00:46.36#ibcon#wrote, iclass 26, count 2 2006.201.07:00:46.36#ibcon#about to read 3, iclass 26, count 2 2006.201.07:00:46.39#ibcon#read 3, iclass 26, count 2 2006.201.07:00:46.39#ibcon#about to read 4, iclass 26, count 2 2006.201.07:00:46.39#ibcon#read 4, iclass 26, count 2 2006.201.07:00:46.39#ibcon#about to read 5, iclass 26, count 2 2006.201.07:00:46.39#ibcon#read 5, iclass 26, count 2 2006.201.07:00:46.39#ibcon#about to read 6, iclass 26, count 2 2006.201.07:00:46.39#ibcon#read 6, iclass 26, count 2 2006.201.07:00:46.39#ibcon#end of sib2, iclass 26, count 2 2006.201.07:00:46.39#ibcon#*after write, iclass 26, count 2 2006.201.07:00:46.39#ibcon#*before return 0, iclass 26, count 2 2006.201.07:00:46.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:00:46.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:00:46.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.07:00:46.39#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:46.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:00:46.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:00:46.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:00:46.51#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:00:46.51#ibcon#first serial, iclass 26, count 0 2006.201.07:00:46.51#ibcon#enter sib2, iclass 26, count 0 2006.201.07:00:46.51#ibcon#flushed, iclass 26, count 0 2006.201.07:00:46.51#ibcon#about to write, iclass 26, count 0 2006.201.07:00:46.51#ibcon#wrote, iclass 26, count 0 2006.201.07:00:46.51#ibcon#about to read 3, iclass 26, count 0 2006.201.07:00:46.53#ibcon#read 3, iclass 26, count 0 2006.201.07:00:46.53#ibcon#about to read 4, iclass 26, count 0 2006.201.07:00:46.53#ibcon#read 4, iclass 26, count 0 2006.201.07:00:46.53#ibcon#about to read 5, iclass 26, count 0 2006.201.07:00:46.53#ibcon#read 5, iclass 26, count 0 2006.201.07:00:46.53#ibcon#about to read 6, iclass 26, count 0 2006.201.07:00:46.53#ibcon#read 6, iclass 26, count 0 2006.201.07:00:46.53#ibcon#end of sib2, iclass 26, count 0 2006.201.07:00:46.53#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:00:46.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:00:46.53#ibcon#[25=USB\r\n] 2006.201.07:00:46.53#ibcon#*before write, iclass 26, count 0 2006.201.07:00:46.53#ibcon#enter sib2, iclass 26, count 0 2006.201.07:00:46.53#ibcon#flushed, iclass 26, count 0 2006.201.07:00:46.53#ibcon#about to write, iclass 26, count 0 2006.201.07:00:46.53#ibcon#wrote, iclass 26, count 0 2006.201.07:00:46.53#ibcon#about to read 3, iclass 26, count 0 2006.201.07:00:46.56#ibcon#read 3, iclass 26, count 0 2006.201.07:00:46.56#ibcon#about to read 4, iclass 26, count 0 2006.201.07:00:46.56#ibcon#read 4, iclass 26, count 0 2006.201.07:00:46.56#ibcon#about to read 5, iclass 26, count 0 2006.201.07:00:46.56#ibcon#read 5, iclass 26, count 0 2006.201.07:00:46.56#ibcon#about to read 6, iclass 26, count 0 2006.201.07:00:46.56#ibcon#read 6, iclass 26, count 0 2006.201.07:00:46.56#ibcon#end of sib2, iclass 26, count 0 2006.201.07:00:46.56#ibcon#*after write, iclass 26, count 0 2006.201.07:00:46.56#ibcon#*before return 0, iclass 26, count 0 2006.201.07:00:46.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:00:46.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:00:46.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:00:46.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:00:46.56$vck44/vblo=1,629.99 2006.201.07:00:46.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.07:00:46.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.07:00:46.56#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:46.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:46.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:46.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:46.56#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:00:46.56#ibcon#first serial, iclass 28, count 0 2006.201.07:00:46.56#ibcon#enter sib2, iclass 28, count 0 2006.201.07:00:46.56#ibcon#flushed, iclass 28, count 0 2006.201.07:00:46.56#ibcon#about to write, iclass 28, count 0 2006.201.07:00:46.56#ibcon#wrote, iclass 28, count 0 2006.201.07:00:46.56#ibcon#about to read 3, iclass 28, count 0 2006.201.07:00:46.58#ibcon#read 3, iclass 28, count 0 2006.201.07:00:46.58#ibcon#about to read 4, iclass 28, count 0 2006.201.07:00:46.58#ibcon#read 4, iclass 28, count 0 2006.201.07:00:46.58#ibcon#about to read 5, iclass 28, count 0 2006.201.07:00:46.58#ibcon#read 5, iclass 28, count 0 2006.201.07:00:46.58#ibcon#about to read 6, iclass 28, count 0 2006.201.07:00:46.58#ibcon#read 6, iclass 28, count 0 2006.201.07:00:46.58#ibcon#end of sib2, iclass 28, count 0 2006.201.07:00:46.58#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:00:46.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:00:46.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:00:46.58#ibcon#*before write, iclass 28, count 0 2006.201.07:00:46.58#ibcon#enter sib2, iclass 28, count 0 2006.201.07:00:46.58#ibcon#flushed, iclass 28, count 0 2006.201.07:00:46.58#ibcon#about to write, iclass 28, count 0 2006.201.07:00:46.58#ibcon#wrote, iclass 28, count 0 2006.201.07:00:46.58#ibcon#about to read 3, iclass 28, count 0 2006.201.07:00:46.63#ibcon#read 3, iclass 28, count 0 2006.201.07:00:46.63#ibcon#about to read 4, iclass 28, count 0 2006.201.07:00:46.63#ibcon#read 4, iclass 28, count 0 2006.201.07:00:46.63#ibcon#about to read 5, iclass 28, count 0 2006.201.07:00:46.63#ibcon#read 5, iclass 28, count 0 2006.201.07:00:46.63#ibcon#about to read 6, iclass 28, count 0 2006.201.07:00:46.63#ibcon#read 6, iclass 28, count 0 2006.201.07:00:46.63#ibcon#end of sib2, iclass 28, count 0 2006.201.07:00:46.63#ibcon#*after write, iclass 28, count 0 2006.201.07:00:46.63#ibcon#*before return 0, iclass 28, count 0 2006.201.07:00:46.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:46.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:46.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:00:46.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:00:46.63$vck44/vb=1,4 2006.201.07:00:46.63#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.07:00:46.63#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.07:00:46.63#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:46.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:00:46.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:00:46.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:00:46.63#ibcon#enter wrdev, iclass 30, count 2 2006.201.07:00:46.63#ibcon#first serial, iclass 30, count 2 2006.201.07:00:46.63#ibcon#enter sib2, iclass 30, count 2 2006.201.07:00:46.63#ibcon#flushed, iclass 30, count 2 2006.201.07:00:46.63#ibcon#about to write, iclass 30, count 2 2006.201.07:00:46.63#ibcon#wrote, iclass 30, count 2 2006.201.07:00:46.63#ibcon#about to read 3, iclass 30, count 2 2006.201.07:00:46.65#ibcon#read 3, iclass 30, count 2 2006.201.07:00:46.65#ibcon#about to read 4, iclass 30, count 2 2006.201.07:00:46.65#ibcon#read 4, iclass 30, count 2 2006.201.07:00:46.65#ibcon#about to read 5, iclass 30, count 2 2006.201.07:00:46.65#ibcon#read 5, iclass 30, count 2 2006.201.07:00:46.65#ibcon#about to read 6, iclass 30, count 2 2006.201.07:00:46.65#ibcon#read 6, iclass 30, count 2 2006.201.07:00:46.65#ibcon#end of sib2, iclass 30, count 2 2006.201.07:00:46.65#ibcon#*mode == 0, iclass 30, count 2 2006.201.07:00:46.65#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.07:00:46.65#ibcon#[27=AT01-04\r\n] 2006.201.07:00:46.65#ibcon#*before write, iclass 30, count 2 2006.201.07:00:46.65#ibcon#enter sib2, iclass 30, count 2 2006.201.07:00:46.65#ibcon#flushed, iclass 30, count 2 2006.201.07:00:46.65#ibcon#about to write, iclass 30, count 2 2006.201.07:00:46.65#ibcon#wrote, iclass 30, count 2 2006.201.07:00:46.65#ibcon#about to read 3, iclass 30, count 2 2006.201.07:00:46.68#ibcon#read 3, iclass 30, count 2 2006.201.07:00:46.68#ibcon#about to read 4, iclass 30, count 2 2006.201.07:00:46.68#ibcon#read 4, iclass 30, count 2 2006.201.07:00:46.68#ibcon#about to read 5, iclass 30, count 2 2006.201.07:00:46.68#ibcon#read 5, iclass 30, count 2 2006.201.07:00:46.68#ibcon#about to read 6, iclass 30, count 2 2006.201.07:00:46.68#ibcon#read 6, iclass 30, count 2 2006.201.07:00:46.68#ibcon#end of sib2, iclass 30, count 2 2006.201.07:00:46.68#ibcon#*after write, iclass 30, count 2 2006.201.07:00:46.68#ibcon#*before return 0, iclass 30, count 2 2006.201.07:00:46.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:00:46.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:00:46.68#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.07:00:46.68#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:46.68#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:00:46.80#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:00:46.80#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:00:46.80#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:00:46.80#ibcon#first serial, iclass 30, count 0 2006.201.07:00:46.80#ibcon#enter sib2, iclass 30, count 0 2006.201.07:00:46.80#ibcon#flushed, iclass 30, count 0 2006.201.07:00:46.80#ibcon#about to write, iclass 30, count 0 2006.201.07:00:46.80#ibcon#wrote, iclass 30, count 0 2006.201.07:00:46.80#ibcon#about to read 3, iclass 30, count 0 2006.201.07:00:46.82#ibcon#read 3, iclass 30, count 0 2006.201.07:00:46.82#ibcon#about to read 4, iclass 30, count 0 2006.201.07:00:46.82#ibcon#read 4, iclass 30, count 0 2006.201.07:00:46.82#ibcon#about to read 5, iclass 30, count 0 2006.201.07:00:46.82#ibcon#read 5, iclass 30, count 0 2006.201.07:00:46.82#ibcon#about to read 6, iclass 30, count 0 2006.201.07:00:46.82#ibcon#read 6, iclass 30, count 0 2006.201.07:00:46.82#ibcon#end of sib2, iclass 30, count 0 2006.201.07:00:46.82#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:00:46.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:00:46.82#ibcon#[27=USB\r\n] 2006.201.07:00:46.82#ibcon#*before write, iclass 30, count 0 2006.201.07:00:46.82#ibcon#enter sib2, iclass 30, count 0 2006.201.07:00:46.82#ibcon#flushed, iclass 30, count 0 2006.201.07:00:46.82#ibcon#about to write, iclass 30, count 0 2006.201.07:00:46.82#ibcon#wrote, iclass 30, count 0 2006.201.07:00:46.82#ibcon#about to read 3, iclass 30, count 0 2006.201.07:00:46.85#ibcon#read 3, iclass 30, count 0 2006.201.07:00:46.85#ibcon#about to read 4, iclass 30, count 0 2006.201.07:00:46.85#ibcon#read 4, iclass 30, count 0 2006.201.07:00:46.85#ibcon#about to read 5, iclass 30, count 0 2006.201.07:00:46.85#ibcon#read 5, iclass 30, count 0 2006.201.07:00:46.85#ibcon#about to read 6, iclass 30, count 0 2006.201.07:00:46.85#ibcon#read 6, iclass 30, count 0 2006.201.07:00:46.85#ibcon#end of sib2, iclass 30, count 0 2006.201.07:00:46.85#ibcon#*after write, iclass 30, count 0 2006.201.07:00:46.85#ibcon#*before return 0, iclass 30, count 0 2006.201.07:00:46.85#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:00:46.85#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:00:46.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:00:46.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:00:46.85$vck44/vblo=2,634.99 2006.201.07:00:46.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.07:00:46.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.07:00:46.85#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:46.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:46.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:46.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:46.85#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:00:46.85#ibcon#first serial, iclass 32, count 0 2006.201.07:00:46.85#ibcon#enter sib2, iclass 32, count 0 2006.201.07:00:46.85#ibcon#flushed, iclass 32, count 0 2006.201.07:00:46.85#ibcon#about to write, iclass 32, count 0 2006.201.07:00:46.85#ibcon#wrote, iclass 32, count 0 2006.201.07:00:46.85#ibcon#about to read 3, iclass 32, count 0 2006.201.07:00:46.87#ibcon#read 3, iclass 32, count 0 2006.201.07:00:46.87#ibcon#about to read 4, iclass 32, count 0 2006.201.07:00:46.87#ibcon#read 4, iclass 32, count 0 2006.201.07:00:46.87#ibcon#about to read 5, iclass 32, count 0 2006.201.07:00:46.87#ibcon#read 5, iclass 32, count 0 2006.201.07:00:46.87#ibcon#about to read 6, iclass 32, count 0 2006.201.07:00:46.87#ibcon#read 6, iclass 32, count 0 2006.201.07:00:46.87#ibcon#end of sib2, iclass 32, count 0 2006.201.07:00:46.87#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:00:46.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:00:46.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:00:46.87#ibcon#*before write, iclass 32, count 0 2006.201.07:00:46.87#ibcon#enter sib2, iclass 32, count 0 2006.201.07:00:46.87#ibcon#flushed, iclass 32, count 0 2006.201.07:00:46.87#ibcon#about to write, iclass 32, count 0 2006.201.07:00:46.87#ibcon#wrote, iclass 32, count 0 2006.201.07:00:46.87#ibcon#about to read 3, iclass 32, count 0 2006.201.07:00:46.91#ibcon#read 3, iclass 32, count 0 2006.201.07:00:46.91#ibcon#about to read 4, iclass 32, count 0 2006.201.07:00:46.91#ibcon#read 4, iclass 32, count 0 2006.201.07:00:46.91#ibcon#about to read 5, iclass 32, count 0 2006.201.07:00:46.91#ibcon#read 5, iclass 32, count 0 2006.201.07:00:46.91#ibcon#about to read 6, iclass 32, count 0 2006.201.07:00:46.91#ibcon#read 6, iclass 32, count 0 2006.201.07:00:46.91#ibcon#end of sib2, iclass 32, count 0 2006.201.07:00:46.91#ibcon#*after write, iclass 32, count 0 2006.201.07:00:46.91#ibcon#*before return 0, iclass 32, count 0 2006.201.07:00:46.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:46.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:00:46.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:00:46.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:00:46.91$vck44/vb=2,5 2006.201.07:00:46.91#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.07:00:46.91#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.07:00:46.91#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:46.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:46.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:46.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:46.97#ibcon#enter wrdev, iclass 34, count 2 2006.201.07:00:46.97#ibcon#first serial, iclass 34, count 2 2006.201.07:00:46.97#ibcon#enter sib2, iclass 34, count 2 2006.201.07:00:46.97#ibcon#flushed, iclass 34, count 2 2006.201.07:00:46.97#ibcon#about to write, iclass 34, count 2 2006.201.07:00:46.97#ibcon#wrote, iclass 34, count 2 2006.201.07:00:46.97#ibcon#about to read 3, iclass 34, count 2 2006.201.07:00:46.99#ibcon#read 3, iclass 34, count 2 2006.201.07:00:46.99#ibcon#about to read 4, iclass 34, count 2 2006.201.07:00:46.99#ibcon#read 4, iclass 34, count 2 2006.201.07:00:46.99#ibcon#about to read 5, iclass 34, count 2 2006.201.07:00:46.99#ibcon#read 5, iclass 34, count 2 2006.201.07:00:46.99#ibcon#about to read 6, iclass 34, count 2 2006.201.07:00:46.99#ibcon#read 6, iclass 34, count 2 2006.201.07:00:46.99#ibcon#end of sib2, iclass 34, count 2 2006.201.07:00:46.99#ibcon#*mode == 0, iclass 34, count 2 2006.201.07:00:46.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.07:00:46.99#ibcon#[27=AT02-05\r\n] 2006.201.07:00:46.99#ibcon#*before write, iclass 34, count 2 2006.201.07:00:46.99#ibcon#enter sib2, iclass 34, count 2 2006.201.07:00:46.99#ibcon#flushed, iclass 34, count 2 2006.201.07:00:46.99#ibcon#about to write, iclass 34, count 2 2006.201.07:00:46.99#ibcon#wrote, iclass 34, count 2 2006.201.07:00:46.99#ibcon#about to read 3, iclass 34, count 2 2006.201.07:00:47.02#ibcon#read 3, iclass 34, count 2 2006.201.07:00:47.02#ibcon#about to read 4, iclass 34, count 2 2006.201.07:00:47.02#ibcon#read 4, iclass 34, count 2 2006.201.07:00:47.02#ibcon#about to read 5, iclass 34, count 2 2006.201.07:00:47.02#ibcon#read 5, iclass 34, count 2 2006.201.07:00:47.02#ibcon#about to read 6, iclass 34, count 2 2006.201.07:00:47.02#ibcon#read 6, iclass 34, count 2 2006.201.07:00:47.02#ibcon#end of sib2, iclass 34, count 2 2006.201.07:00:47.02#ibcon#*after write, iclass 34, count 2 2006.201.07:00:47.02#ibcon#*before return 0, iclass 34, count 2 2006.201.07:00:47.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:47.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:00:47.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.07:00:47.02#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:47.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:47.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:47.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:47.14#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:00:47.14#ibcon#first serial, iclass 34, count 0 2006.201.07:00:47.14#ibcon#enter sib2, iclass 34, count 0 2006.201.07:00:47.14#ibcon#flushed, iclass 34, count 0 2006.201.07:00:47.14#ibcon#about to write, iclass 34, count 0 2006.201.07:00:47.14#ibcon#wrote, iclass 34, count 0 2006.201.07:00:47.14#ibcon#about to read 3, iclass 34, count 0 2006.201.07:00:47.16#ibcon#read 3, iclass 34, count 0 2006.201.07:00:47.16#ibcon#about to read 4, iclass 34, count 0 2006.201.07:00:47.16#ibcon#read 4, iclass 34, count 0 2006.201.07:00:47.16#ibcon#about to read 5, iclass 34, count 0 2006.201.07:00:47.16#ibcon#read 5, iclass 34, count 0 2006.201.07:00:47.16#ibcon#about to read 6, iclass 34, count 0 2006.201.07:00:47.16#ibcon#read 6, iclass 34, count 0 2006.201.07:00:47.16#ibcon#end of sib2, iclass 34, count 0 2006.201.07:00:47.16#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:00:47.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:00:47.16#ibcon#[27=USB\r\n] 2006.201.07:00:47.16#ibcon#*before write, iclass 34, count 0 2006.201.07:00:47.16#ibcon#enter sib2, iclass 34, count 0 2006.201.07:00:47.16#ibcon#flushed, iclass 34, count 0 2006.201.07:00:47.16#ibcon#about to write, iclass 34, count 0 2006.201.07:00:47.16#ibcon#wrote, iclass 34, count 0 2006.201.07:00:47.16#ibcon#about to read 3, iclass 34, count 0 2006.201.07:00:47.19#ibcon#read 3, iclass 34, count 0 2006.201.07:00:47.19#ibcon#about to read 4, iclass 34, count 0 2006.201.07:00:47.19#ibcon#read 4, iclass 34, count 0 2006.201.07:00:47.19#ibcon#about to read 5, iclass 34, count 0 2006.201.07:00:47.19#ibcon#read 5, iclass 34, count 0 2006.201.07:00:47.19#ibcon#about to read 6, iclass 34, count 0 2006.201.07:00:47.19#ibcon#read 6, iclass 34, count 0 2006.201.07:00:47.19#ibcon#end of sib2, iclass 34, count 0 2006.201.07:00:47.19#ibcon#*after write, iclass 34, count 0 2006.201.07:00:47.19#ibcon#*before return 0, iclass 34, count 0 2006.201.07:00:47.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:47.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:00:47.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:00:47.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:00:47.19$vck44/vblo=3,649.99 2006.201.07:00:47.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.07:00:47.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.07:00:47.19#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:47.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:47.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:47.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:47.19#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:00:47.19#ibcon#first serial, iclass 36, count 0 2006.201.07:00:47.19#ibcon#enter sib2, iclass 36, count 0 2006.201.07:00:47.19#ibcon#flushed, iclass 36, count 0 2006.201.07:00:47.19#ibcon#about to write, iclass 36, count 0 2006.201.07:00:47.19#ibcon#wrote, iclass 36, count 0 2006.201.07:00:47.19#ibcon#about to read 3, iclass 36, count 0 2006.201.07:00:47.21#ibcon#read 3, iclass 36, count 0 2006.201.07:00:47.21#ibcon#about to read 4, iclass 36, count 0 2006.201.07:00:47.21#ibcon#read 4, iclass 36, count 0 2006.201.07:00:47.21#ibcon#about to read 5, iclass 36, count 0 2006.201.07:00:47.21#ibcon#read 5, iclass 36, count 0 2006.201.07:00:47.21#ibcon#about to read 6, iclass 36, count 0 2006.201.07:00:47.21#ibcon#read 6, iclass 36, count 0 2006.201.07:00:47.21#ibcon#end of sib2, iclass 36, count 0 2006.201.07:00:47.21#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:00:47.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:00:47.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:00:47.21#ibcon#*before write, iclass 36, count 0 2006.201.07:00:47.21#ibcon#enter sib2, iclass 36, count 0 2006.201.07:00:47.21#ibcon#flushed, iclass 36, count 0 2006.201.07:00:47.21#ibcon#about to write, iclass 36, count 0 2006.201.07:00:47.21#ibcon#wrote, iclass 36, count 0 2006.201.07:00:47.21#ibcon#about to read 3, iclass 36, count 0 2006.201.07:00:47.26#ibcon#read 3, iclass 36, count 0 2006.201.07:00:47.26#ibcon#about to read 4, iclass 36, count 0 2006.201.07:00:47.26#ibcon#read 4, iclass 36, count 0 2006.201.07:00:47.26#ibcon#about to read 5, iclass 36, count 0 2006.201.07:00:47.26#ibcon#read 5, iclass 36, count 0 2006.201.07:00:47.26#ibcon#about to read 6, iclass 36, count 0 2006.201.07:00:47.26#ibcon#read 6, iclass 36, count 0 2006.201.07:00:47.26#ibcon#end of sib2, iclass 36, count 0 2006.201.07:00:47.26#ibcon#*after write, iclass 36, count 0 2006.201.07:00:47.26#ibcon#*before return 0, iclass 36, count 0 2006.201.07:00:47.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:47.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:00:47.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:00:47.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:00:47.26$vck44/vb=3,4 2006.201.07:00:47.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.07:00:47.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.07:00:47.26#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:47.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:47.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:47.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:47.31#ibcon#enter wrdev, iclass 38, count 2 2006.201.07:00:47.31#ibcon#first serial, iclass 38, count 2 2006.201.07:00:47.31#ibcon#enter sib2, iclass 38, count 2 2006.201.07:00:47.31#ibcon#flushed, iclass 38, count 2 2006.201.07:00:47.31#ibcon#about to write, iclass 38, count 2 2006.201.07:00:47.31#ibcon#wrote, iclass 38, count 2 2006.201.07:00:47.31#ibcon#about to read 3, iclass 38, count 2 2006.201.07:00:47.33#ibcon#read 3, iclass 38, count 2 2006.201.07:00:47.33#ibcon#about to read 4, iclass 38, count 2 2006.201.07:00:47.33#ibcon#read 4, iclass 38, count 2 2006.201.07:00:47.33#ibcon#about to read 5, iclass 38, count 2 2006.201.07:00:47.33#ibcon#read 5, iclass 38, count 2 2006.201.07:00:47.33#ibcon#about to read 6, iclass 38, count 2 2006.201.07:00:47.33#ibcon#read 6, iclass 38, count 2 2006.201.07:00:47.33#ibcon#end of sib2, iclass 38, count 2 2006.201.07:00:47.33#ibcon#*mode == 0, iclass 38, count 2 2006.201.07:00:47.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.07:00:47.33#ibcon#[27=AT03-04\r\n] 2006.201.07:00:47.33#ibcon#*before write, iclass 38, count 2 2006.201.07:00:47.33#ibcon#enter sib2, iclass 38, count 2 2006.201.07:00:47.33#ibcon#flushed, iclass 38, count 2 2006.201.07:00:47.33#ibcon#about to write, iclass 38, count 2 2006.201.07:00:47.33#ibcon#wrote, iclass 38, count 2 2006.201.07:00:47.33#ibcon#about to read 3, iclass 38, count 2 2006.201.07:00:47.36#ibcon#read 3, iclass 38, count 2 2006.201.07:00:47.36#ibcon#about to read 4, iclass 38, count 2 2006.201.07:00:47.36#ibcon#read 4, iclass 38, count 2 2006.201.07:00:47.36#ibcon#about to read 5, iclass 38, count 2 2006.201.07:00:47.36#ibcon#read 5, iclass 38, count 2 2006.201.07:00:47.36#ibcon#about to read 6, iclass 38, count 2 2006.201.07:00:47.36#ibcon#read 6, iclass 38, count 2 2006.201.07:00:47.36#ibcon#end of sib2, iclass 38, count 2 2006.201.07:00:47.36#ibcon#*after write, iclass 38, count 2 2006.201.07:00:47.36#ibcon#*before return 0, iclass 38, count 2 2006.201.07:00:47.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:47.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:00:47.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.07:00:47.36#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:47.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:47.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:47.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:47.48#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:00:47.48#ibcon#first serial, iclass 38, count 0 2006.201.07:00:47.48#ibcon#enter sib2, iclass 38, count 0 2006.201.07:00:47.48#ibcon#flushed, iclass 38, count 0 2006.201.07:00:47.48#ibcon#about to write, iclass 38, count 0 2006.201.07:00:47.48#ibcon#wrote, iclass 38, count 0 2006.201.07:00:47.48#ibcon#about to read 3, iclass 38, count 0 2006.201.07:00:47.50#ibcon#read 3, iclass 38, count 0 2006.201.07:00:47.50#ibcon#about to read 4, iclass 38, count 0 2006.201.07:00:47.50#ibcon#read 4, iclass 38, count 0 2006.201.07:00:47.50#ibcon#about to read 5, iclass 38, count 0 2006.201.07:00:47.50#ibcon#read 5, iclass 38, count 0 2006.201.07:00:47.50#ibcon#about to read 6, iclass 38, count 0 2006.201.07:00:47.50#ibcon#read 6, iclass 38, count 0 2006.201.07:00:47.50#ibcon#end of sib2, iclass 38, count 0 2006.201.07:00:47.50#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:00:47.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:00:47.50#ibcon#[27=USB\r\n] 2006.201.07:00:47.50#ibcon#*before write, iclass 38, count 0 2006.201.07:00:47.50#ibcon#enter sib2, iclass 38, count 0 2006.201.07:00:47.50#ibcon#flushed, iclass 38, count 0 2006.201.07:00:47.50#ibcon#about to write, iclass 38, count 0 2006.201.07:00:47.50#ibcon#wrote, iclass 38, count 0 2006.201.07:00:47.50#ibcon#about to read 3, iclass 38, count 0 2006.201.07:00:47.53#ibcon#read 3, iclass 38, count 0 2006.201.07:00:47.53#ibcon#about to read 4, iclass 38, count 0 2006.201.07:00:47.53#ibcon#read 4, iclass 38, count 0 2006.201.07:00:47.53#ibcon#about to read 5, iclass 38, count 0 2006.201.07:00:47.53#ibcon#read 5, iclass 38, count 0 2006.201.07:00:47.53#ibcon#about to read 6, iclass 38, count 0 2006.201.07:00:47.53#ibcon#read 6, iclass 38, count 0 2006.201.07:00:47.53#ibcon#end of sib2, iclass 38, count 0 2006.201.07:00:47.53#ibcon#*after write, iclass 38, count 0 2006.201.07:00:47.53#ibcon#*before return 0, iclass 38, count 0 2006.201.07:00:47.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:47.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:00:47.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:00:47.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:00:47.53$vck44/vblo=4,679.99 2006.201.07:00:47.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.07:00:47.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.07:00:47.53#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:47.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:47.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:47.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:47.53#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:00:47.53#ibcon#first serial, iclass 40, count 0 2006.201.07:00:47.53#ibcon#enter sib2, iclass 40, count 0 2006.201.07:00:47.53#ibcon#flushed, iclass 40, count 0 2006.201.07:00:47.53#ibcon#about to write, iclass 40, count 0 2006.201.07:00:47.53#ibcon#wrote, iclass 40, count 0 2006.201.07:00:47.53#ibcon#about to read 3, iclass 40, count 0 2006.201.07:00:47.55#ibcon#read 3, iclass 40, count 0 2006.201.07:00:47.55#ibcon#about to read 4, iclass 40, count 0 2006.201.07:00:47.55#ibcon#read 4, iclass 40, count 0 2006.201.07:00:47.55#ibcon#about to read 5, iclass 40, count 0 2006.201.07:00:47.55#ibcon#read 5, iclass 40, count 0 2006.201.07:00:47.55#ibcon#about to read 6, iclass 40, count 0 2006.201.07:00:47.55#ibcon#read 6, iclass 40, count 0 2006.201.07:00:47.55#ibcon#end of sib2, iclass 40, count 0 2006.201.07:00:47.55#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:00:47.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:00:47.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:00:47.55#ibcon#*before write, iclass 40, count 0 2006.201.07:00:47.55#ibcon#enter sib2, iclass 40, count 0 2006.201.07:00:47.55#ibcon#flushed, iclass 40, count 0 2006.201.07:00:47.55#ibcon#about to write, iclass 40, count 0 2006.201.07:00:47.55#ibcon#wrote, iclass 40, count 0 2006.201.07:00:47.55#ibcon#about to read 3, iclass 40, count 0 2006.201.07:00:47.59#ibcon#read 3, iclass 40, count 0 2006.201.07:00:47.59#ibcon#about to read 4, iclass 40, count 0 2006.201.07:00:47.59#ibcon#read 4, iclass 40, count 0 2006.201.07:00:47.59#ibcon#about to read 5, iclass 40, count 0 2006.201.07:00:47.59#ibcon#read 5, iclass 40, count 0 2006.201.07:00:47.59#ibcon#about to read 6, iclass 40, count 0 2006.201.07:00:47.59#ibcon#read 6, iclass 40, count 0 2006.201.07:00:47.59#ibcon#end of sib2, iclass 40, count 0 2006.201.07:00:47.59#ibcon#*after write, iclass 40, count 0 2006.201.07:00:47.59#ibcon#*before return 0, iclass 40, count 0 2006.201.07:00:47.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:47.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:00:47.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:00:47.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:00:47.59$vck44/vb=4,5 2006.201.07:00:47.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.07:00:47.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.07:00:47.59#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:47.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:47.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:47.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:47.65#ibcon#enter wrdev, iclass 4, count 2 2006.201.07:00:47.65#ibcon#first serial, iclass 4, count 2 2006.201.07:00:47.65#ibcon#enter sib2, iclass 4, count 2 2006.201.07:00:47.65#ibcon#flushed, iclass 4, count 2 2006.201.07:00:47.65#ibcon#about to write, iclass 4, count 2 2006.201.07:00:47.65#ibcon#wrote, iclass 4, count 2 2006.201.07:00:47.65#ibcon#about to read 3, iclass 4, count 2 2006.201.07:00:47.67#ibcon#read 3, iclass 4, count 2 2006.201.07:00:47.67#ibcon#about to read 4, iclass 4, count 2 2006.201.07:00:47.67#ibcon#read 4, iclass 4, count 2 2006.201.07:00:47.67#ibcon#about to read 5, iclass 4, count 2 2006.201.07:00:47.67#ibcon#read 5, iclass 4, count 2 2006.201.07:00:47.67#ibcon#about to read 6, iclass 4, count 2 2006.201.07:00:47.67#ibcon#read 6, iclass 4, count 2 2006.201.07:00:47.67#ibcon#end of sib2, iclass 4, count 2 2006.201.07:00:47.67#ibcon#*mode == 0, iclass 4, count 2 2006.201.07:00:47.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.07:00:47.67#ibcon#[27=AT04-05\r\n] 2006.201.07:00:47.67#ibcon#*before write, iclass 4, count 2 2006.201.07:00:47.67#ibcon#enter sib2, iclass 4, count 2 2006.201.07:00:47.67#ibcon#flushed, iclass 4, count 2 2006.201.07:00:47.67#ibcon#about to write, iclass 4, count 2 2006.201.07:00:47.67#ibcon#wrote, iclass 4, count 2 2006.201.07:00:47.67#ibcon#about to read 3, iclass 4, count 2 2006.201.07:00:47.70#ibcon#read 3, iclass 4, count 2 2006.201.07:00:47.70#ibcon#about to read 4, iclass 4, count 2 2006.201.07:00:47.70#ibcon#read 4, iclass 4, count 2 2006.201.07:00:47.70#ibcon#about to read 5, iclass 4, count 2 2006.201.07:00:47.70#ibcon#read 5, iclass 4, count 2 2006.201.07:00:47.70#ibcon#about to read 6, iclass 4, count 2 2006.201.07:00:47.70#ibcon#read 6, iclass 4, count 2 2006.201.07:00:47.70#ibcon#end of sib2, iclass 4, count 2 2006.201.07:00:47.70#ibcon#*after write, iclass 4, count 2 2006.201.07:00:47.70#ibcon#*before return 0, iclass 4, count 2 2006.201.07:00:47.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:47.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:00:47.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.07:00:47.70#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:47.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:47.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:47.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:47.82#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:00:47.82#ibcon#first serial, iclass 4, count 0 2006.201.07:00:47.82#ibcon#enter sib2, iclass 4, count 0 2006.201.07:00:47.82#ibcon#flushed, iclass 4, count 0 2006.201.07:00:47.82#ibcon#about to write, iclass 4, count 0 2006.201.07:00:47.82#ibcon#wrote, iclass 4, count 0 2006.201.07:00:47.82#ibcon#about to read 3, iclass 4, count 0 2006.201.07:00:47.84#ibcon#read 3, iclass 4, count 0 2006.201.07:00:47.84#ibcon#about to read 4, iclass 4, count 0 2006.201.07:00:47.84#ibcon#read 4, iclass 4, count 0 2006.201.07:00:47.84#ibcon#about to read 5, iclass 4, count 0 2006.201.07:00:47.84#ibcon#read 5, iclass 4, count 0 2006.201.07:00:47.84#ibcon#about to read 6, iclass 4, count 0 2006.201.07:00:47.84#ibcon#read 6, iclass 4, count 0 2006.201.07:00:47.84#ibcon#end of sib2, iclass 4, count 0 2006.201.07:00:47.84#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:00:47.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:00:47.84#ibcon#[27=USB\r\n] 2006.201.07:00:47.84#ibcon#*before write, iclass 4, count 0 2006.201.07:00:47.84#ibcon#enter sib2, iclass 4, count 0 2006.201.07:00:47.84#ibcon#flushed, iclass 4, count 0 2006.201.07:00:47.84#ibcon#about to write, iclass 4, count 0 2006.201.07:00:47.84#ibcon#wrote, iclass 4, count 0 2006.201.07:00:47.84#ibcon#about to read 3, iclass 4, count 0 2006.201.07:00:47.87#ibcon#read 3, iclass 4, count 0 2006.201.07:00:47.87#ibcon#about to read 4, iclass 4, count 0 2006.201.07:00:47.87#ibcon#read 4, iclass 4, count 0 2006.201.07:00:47.87#ibcon#about to read 5, iclass 4, count 0 2006.201.07:00:47.87#ibcon#read 5, iclass 4, count 0 2006.201.07:00:47.87#ibcon#about to read 6, iclass 4, count 0 2006.201.07:00:47.87#ibcon#read 6, iclass 4, count 0 2006.201.07:00:47.87#ibcon#end of sib2, iclass 4, count 0 2006.201.07:00:47.87#ibcon#*after write, iclass 4, count 0 2006.201.07:00:47.87#ibcon#*before return 0, iclass 4, count 0 2006.201.07:00:47.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:47.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:00:47.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:00:47.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:00:47.87$vck44/vblo=5,709.99 2006.201.07:00:47.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.07:00:47.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.07:00:47.87#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:47.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:47.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:47.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:47.87#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:00:47.87#ibcon#first serial, iclass 6, count 0 2006.201.07:00:47.87#ibcon#enter sib2, iclass 6, count 0 2006.201.07:00:47.87#ibcon#flushed, iclass 6, count 0 2006.201.07:00:47.87#ibcon#about to write, iclass 6, count 0 2006.201.07:00:47.87#ibcon#wrote, iclass 6, count 0 2006.201.07:00:47.87#ibcon#about to read 3, iclass 6, count 0 2006.201.07:00:47.89#ibcon#read 3, iclass 6, count 0 2006.201.07:00:47.89#ibcon#about to read 4, iclass 6, count 0 2006.201.07:00:47.89#ibcon#read 4, iclass 6, count 0 2006.201.07:00:47.89#ibcon#about to read 5, iclass 6, count 0 2006.201.07:00:47.89#ibcon#read 5, iclass 6, count 0 2006.201.07:00:47.89#ibcon#about to read 6, iclass 6, count 0 2006.201.07:00:47.89#ibcon#read 6, iclass 6, count 0 2006.201.07:00:47.89#ibcon#end of sib2, iclass 6, count 0 2006.201.07:00:47.89#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:00:47.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:00:47.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:00:47.89#ibcon#*before write, iclass 6, count 0 2006.201.07:00:47.89#ibcon#enter sib2, iclass 6, count 0 2006.201.07:00:47.89#ibcon#flushed, iclass 6, count 0 2006.201.07:00:47.89#ibcon#about to write, iclass 6, count 0 2006.201.07:00:47.89#ibcon#wrote, iclass 6, count 0 2006.201.07:00:47.89#ibcon#about to read 3, iclass 6, count 0 2006.201.07:00:47.94#ibcon#read 3, iclass 6, count 0 2006.201.07:00:47.94#ibcon#about to read 4, iclass 6, count 0 2006.201.07:00:47.94#ibcon#read 4, iclass 6, count 0 2006.201.07:00:47.94#ibcon#about to read 5, iclass 6, count 0 2006.201.07:00:47.94#ibcon#read 5, iclass 6, count 0 2006.201.07:00:47.94#ibcon#about to read 6, iclass 6, count 0 2006.201.07:00:47.94#ibcon#read 6, iclass 6, count 0 2006.201.07:00:47.94#ibcon#end of sib2, iclass 6, count 0 2006.201.07:00:47.94#ibcon#*after write, iclass 6, count 0 2006.201.07:00:47.94#ibcon#*before return 0, iclass 6, count 0 2006.201.07:00:47.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:47.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:00:47.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:00:47.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:00:47.94$vck44/vb=5,4 2006.201.07:00:47.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.07:00:47.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.07:00:47.94#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:47.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:47.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:47.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:47.99#ibcon#enter wrdev, iclass 10, count 2 2006.201.07:00:47.99#ibcon#first serial, iclass 10, count 2 2006.201.07:00:47.99#ibcon#enter sib2, iclass 10, count 2 2006.201.07:00:47.99#ibcon#flushed, iclass 10, count 2 2006.201.07:00:47.99#ibcon#about to write, iclass 10, count 2 2006.201.07:00:47.99#ibcon#wrote, iclass 10, count 2 2006.201.07:00:47.99#ibcon#about to read 3, iclass 10, count 2 2006.201.07:00:48.01#ibcon#read 3, iclass 10, count 2 2006.201.07:00:48.01#ibcon#about to read 4, iclass 10, count 2 2006.201.07:00:48.01#ibcon#read 4, iclass 10, count 2 2006.201.07:00:48.01#ibcon#about to read 5, iclass 10, count 2 2006.201.07:00:48.01#ibcon#read 5, iclass 10, count 2 2006.201.07:00:48.01#ibcon#about to read 6, iclass 10, count 2 2006.201.07:00:48.01#ibcon#read 6, iclass 10, count 2 2006.201.07:00:48.01#ibcon#end of sib2, iclass 10, count 2 2006.201.07:00:48.01#ibcon#*mode == 0, iclass 10, count 2 2006.201.07:00:48.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.07:00:48.01#ibcon#[27=AT05-04\r\n] 2006.201.07:00:48.01#ibcon#*before write, iclass 10, count 2 2006.201.07:00:48.01#ibcon#enter sib2, iclass 10, count 2 2006.201.07:00:48.01#ibcon#flushed, iclass 10, count 2 2006.201.07:00:48.01#ibcon#about to write, iclass 10, count 2 2006.201.07:00:48.01#ibcon#wrote, iclass 10, count 2 2006.201.07:00:48.01#ibcon#about to read 3, iclass 10, count 2 2006.201.07:00:48.04#ibcon#read 3, iclass 10, count 2 2006.201.07:00:48.04#ibcon#about to read 4, iclass 10, count 2 2006.201.07:00:48.04#ibcon#read 4, iclass 10, count 2 2006.201.07:00:48.04#ibcon#about to read 5, iclass 10, count 2 2006.201.07:00:48.04#ibcon#read 5, iclass 10, count 2 2006.201.07:00:48.04#ibcon#about to read 6, iclass 10, count 2 2006.201.07:00:48.04#ibcon#read 6, iclass 10, count 2 2006.201.07:00:48.04#ibcon#end of sib2, iclass 10, count 2 2006.201.07:00:48.04#ibcon#*after write, iclass 10, count 2 2006.201.07:00:48.04#ibcon#*before return 0, iclass 10, count 2 2006.201.07:00:48.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:48.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:00:48.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.07:00:48.04#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:48.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:48.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:48.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:48.16#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:00:48.16#ibcon#first serial, iclass 10, count 0 2006.201.07:00:48.16#ibcon#enter sib2, iclass 10, count 0 2006.201.07:00:48.16#ibcon#flushed, iclass 10, count 0 2006.201.07:00:48.16#ibcon#about to write, iclass 10, count 0 2006.201.07:00:48.16#ibcon#wrote, iclass 10, count 0 2006.201.07:00:48.16#ibcon#about to read 3, iclass 10, count 0 2006.201.07:00:48.18#ibcon#read 3, iclass 10, count 0 2006.201.07:00:48.18#ibcon#about to read 4, iclass 10, count 0 2006.201.07:00:48.18#ibcon#read 4, iclass 10, count 0 2006.201.07:00:48.18#ibcon#about to read 5, iclass 10, count 0 2006.201.07:00:48.18#ibcon#read 5, iclass 10, count 0 2006.201.07:00:48.18#ibcon#about to read 6, iclass 10, count 0 2006.201.07:00:48.18#ibcon#read 6, iclass 10, count 0 2006.201.07:00:48.18#ibcon#end of sib2, iclass 10, count 0 2006.201.07:00:48.18#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:00:48.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:00:48.18#ibcon#[27=USB\r\n] 2006.201.07:00:48.18#ibcon#*before write, iclass 10, count 0 2006.201.07:00:48.18#ibcon#enter sib2, iclass 10, count 0 2006.201.07:00:48.18#ibcon#flushed, iclass 10, count 0 2006.201.07:00:48.18#ibcon#about to write, iclass 10, count 0 2006.201.07:00:48.18#ibcon#wrote, iclass 10, count 0 2006.201.07:00:48.18#ibcon#about to read 3, iclass 10, count 0 2006.201.07:00:48.21#ibcon#read 3, iclass 10, count 0 2006.201.07:00:48.21#ibcon#about to read 4, iclass 10, count 0 2006.201.07:00:48.21#ibcon#read 4, iclass 10, count 0 2006.201.07:00:48.21#ibcon#about to read 5, iclass 10, count 0 2006.201.07:00:48.21#ibcon#read 5, iclass 10, count 0 2006.201.07:00:48.21#ibcon#about to read 6, iclass 10, count 0 2006.201.07:00:48.21#ibcon#read 6, iclass 10, count 0 2006.201.07:00:48.21#ibcon#end of sib2, iclass 10, count 0 2006.201.07:00:48.21#ibcon#*after write, iclass 10, count 0 2006.201.07:00:48.21#ibcon#*before return 0, iclass 10, count 0 2006.201.07:00:48.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:48.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:00:48.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:00:48.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:00:48.21$vck44/vblo=6,719.99 2006.201.07:00:48.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.07:00:48.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.07:00:48.21#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:48.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:48.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:48.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:48.21#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:00:48.21#ibcon#first serial, iclass 12, count 0 2006.201.07:00:48.21#ibcon#enter sib2, iclass 12, count 0 2006.201.07:00:48.21#ibcon#flushed, iclass 12, count 0 2006.201.07:00:48.21#ibcon#about to write, iclass 12, count 0 2006.201.07:00:48.21#ibcon#wrote, iclass 12, count 0 2006.201.07:00:48.21#ibcon#about to read 3, iclass 12, count 0 2006.201.07:00:48.23#ibcon#read 3, iclass 12, count 0 2006.201.07:00:48.23#ibcon#about to read 4, iclass 12, count 0 2006.201.07:00:48.23#ibcon#read 4, iclass 12, count 0 2006.201.07:00:48.23#ibcon#about to read 5, iclass 12, count 0 2006.201.07:00:48.23#ibcon#read 5, iclass 12, count 0 2006.201.07:00:48.23#ibcon#about to read 6, iclass 12, count 0 2006.201.07:00:48.23#ibcon#read 6, iclass 12, count 0 2006.201.07:00:48.23#ibcon#end of sib2, iclass 12, count 0 2006.201.07:00:48.23#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:00:48.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:00:48.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:00:48.23#ibcon#*before write, iclass 12, count 0 2006.201.07:00:48.23#ibcon#enter sib2, iclass 12, count 0 2006.201.07:00:48.23#ibcon#flushed, iclass 12, count 0 2006.201.07:00:48.23#ibcon#about to write, iclass 12, count 0 2006.201.07:00:48.23#ibcon#wrote, iclass 12, count 0 2006.201.07:00:48.23#ibcon#about to read 3, iclass 12, count 0 2006.201.07:00:48.27#ibcon#read 3, iclass 12, count 0 2006.201.07:00:48.27#ibcon#about to read 4, iclass 12, count 0 2006.201.07:00:48.27#ibcon#read 4, iclass 12, count 0 2006.201.07:00:48.27#ibcon#about to read 5, iclass 12, count 0 2006.201.07:00:48.27#ibcon#read 5, iclass 12, count 0 2006.201.07:00:48.27#ibcon#about to read 6, iclass 12, count 0 2006.201.07:00:48.27#ibcon#read 6, iclass 12, count 0 2006.201.07:00:48.27#ibcon#end of sib2, iclass 12, count 0 2006.201.07:00:48.27#ibcon#*after write, iclass 12, count 0 2006.201.07:00:48.27#ibcon#*before return 0, iclass 12, count 0 2006.201.07:00:48.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:48.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:00:48.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:00:48.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:00:48.27$vck44/vb=6,4 2006.201.07:00:48.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.07:00:48.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.07:00:48.27#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:48.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:48.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:48.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:48.33#ibcon#enter wrdev, iclass 14, count 2 2006.201.07:00:48.33#ibcon#first serial, iclass 14, count 2 2006.201.07:00:48.33#ibcon#enter sib2, iclass 14, count 2 2006.201.07:00:48.33#ibcon#flushed, iclass 14, count 2 2006.201.07:00:48.33#ibcon#about to write, iclass 14, count 2 2006.201.07:00:48.33#ibcon#wrote, iclass 14, count 2 2006.201.07:00:48.33#ibcon#about to read 3, iclass 14, count 2 2006.201.07:00:48.35#ibcon#read 3, iclass 14, count 2 2006.201.07:00:48.35#ibcon#about to read 4, iclass 14, count 2 2006.201.07:00:48.35#ibcon#read 4, iclass 14, count 2 2006.201.07:00:48.35#ibcon#about to read 5, iclass 14, count 2 2006.201.07:00:48.35#ibcon#read 5, iclass 14, count 2 2006.201.07:00:48.35#ibcon#about to read 6, iclass 14, count 2 2006.201.07:00:48.35#ibcon#read 6, iclass 14, count 2 2006.201.07:00:48.35#ibcon#end of sib2, iclass 14, count 2 2006.201.07:00:48.35#ibcon#*mode == 0, iclass 14, count 2 2006.201.07:00:48.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.07:00:48.35#ibcon#[27=AT06-04\r\n] 2006.201.07:00:48.35#ibcon#*before write, iclass 14, count 2 2006.201.07:00:48.35#ibcon#enter sib2, iclass 14, count 2 2006.201.07:00:48.35#ibcon#flushed, iclass 14, count 2 2006.201.07:00:48.35#ibcon#about to write, iclass 14, count 2 2006.201.07:00:48.35#ibcon#wrote, iclass 14, count 2 2006.201.07:00:48.35#ibcon#about to read 3, iclass 14, count 2 2006.201.07:00:48.38#ibcon#read 3, iclass 14, count 2 2006.201.07:00:48.38#ibcon#about to read 4, iclass 14, count 2 2006.201.07:00:48.38#ibcon#read 4, iclass 14, count 2 2006.201.07:00:48.38#ibcon#about to read 5, iclass 14, count 2 2006.201.07:00:48.38#ibcon#read 5, iclass 14, count 2 2006.201.07:00:48.38#ibcon#about to read 6, iclass 14, count 2 2006.201.07:00:48.38#ibcon#read 6, iclass 14, count 2 2006.201.07:00:48.38#ibcon#end of sib2, iclass 14, count 2 2006.201.07:00:48.38#ibcon#*after write, iclass 14, count 2 2006.201.07:00:48.38#ibcon#*before return 0, iclass 14, count 2 2006.201.07:00:48.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:48.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:00:48.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.07:00:48.38#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:48.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:48.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:48.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:48.50#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:00:48.50#ibcon#first serial, iclass 14, count 0 2006.201.07:00:48.50#ibcon#enter sib2, iclass 14, count 0 2006.201.07:00:48.50#ibcon#flushed, iclass 14, count 0 2006.201.07:00:48.50#ibcon#about to write, iclass 14, count 0 2006.201.07:00:48.50#ibcon#wrote, iclass 14, count 0 2006.201.07:00:48.50#ibcon#about to read 3, iclass 14, count 0 2006.201.07:00:48.52#ibcon#read 3, iclass 14, count 0 2006.201.07:00:48.52#ibcon#about to read 4, iclass 14, count 0 2006.201.07:00:48.52#ibcon#read 4, iclass 14, count 0 2006.201.07:00:48.52#ibcon#about to read 5, iclass 14, count 0 2006.201.07:00:48.52#ibcon#read 5, iclass 14, count 0 2006.201.07:00:48.52#ibcon#about to read 6, iclass 14, count 0 2006.201.07:00:48.52#ibcon#read 6, iclass 14, count 0 2006.201.07:00:48.52#ibcon#end of sib2, iclass 14, count 0 2006.201.07:00:48.52#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:00:48.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:00:48.52#ibcon#[27=USB\r\n] 2006.201.07:00:48.52#ibcon#*before write, iclass 14, count 0 2006.201.07:00:48.52#ibcon#enter sib2, iclass 14, count 0 2006.201.07:00:48.52#ibcon#flushed, iclass 14, count 0 2006.201.07:00:48.52#ibcon#about to write, iclass 14, count 0 2006.201.07:00:48.52#ibcon#wrote, iclass 14, count 0 2006.201.07:00:48.52#ibcon#about to read 3, iclass 14, count 0 2006.201.07:00:48.55#ibcon#read 3, iclass 14, count 0 2006.201.07:00:48.55#ibcon#about to read 4, iclass 14, count 0 2006.201.07:00:48.55#ibcon#read 4, iclass 14, count 0 2006.201.07:00:48.55#ibcon#about to read 5, iclass 14, count 0 2006.201.07:00:48.55#ibcon#read 5, iclass 14, count 0 2006.201.07:00:48.55#ibcon#about to read 6, iclass 14, count 0 2006.201.07:00:48.55#ibcon#read 6, iclass 14, count 0 2006.201.07:00:48.55#ibcon#end of sib2, iclass 14, count 0 2006.201.07:00:48.55#ibcon#*after write, iclass 14, count 0 2006.201.07:00:48.55#ibcon#*before return 0, iclass 14, count 0 2006.201.07:00:48.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:48.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:00:48.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:00:48.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:00:48.55$vck44/vblo=7,734.99 2006.201.07:00:48.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.07:00:48.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.07:00:48.55#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:48.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:48.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:48.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:48.55#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:00:48.55#ibcon#first serial, iclass 16, count 0 2006.201.07:00:48.55#ibcon#enter sib2, iclass 16, count 0 2006.201.07:00:48.55#ibcon#flushed, iclass 16, count 0 2006.201.07:00:48.55#ibcon#about to write, iclass 16, count 0 2006.201.07:00:48.55#ibcon#wrote, iclass 16, count 0 2006.201.07:00:48.55#ibcon#about to read 3, iclass 16, count 0 2006.201.07:00:48.57#ibcon#read 3, iclass 16, count 0 2006.201.07:00:48.57#ibcon#about to read 4, iclass 16, count 0 2006.201.07:00:48.57#ibcon#read 4, iclass 16, count 0 2006.201.07:00:48.57#ibcon#about to read 5, iclass 16, count 0 2006.201.07:00:48.57#ibcon#read 5, iclass 16, count 0 2006.201.07:00:48.57#ibcon#about to read 6, iclass 16, count 0 2006.201.07:00:48.57#ibcon#read 6, iclass 16, count 0 2006.201.07:00:48.57#ibcon#end of sib2, iclass 16, count 0 2006.201.07:00:48.57#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:00:48.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:00:48.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:00:48.57#ibcon#*before write, iclass 16, count 0 2006.201.07:00:48.57#ibcon#enter sib2, iclass 16, count 0 2006.201.07:00:48.57#ibcon#flushed, iclass 16, count 0 2006.201.07:00:48.57#ibcon#about to write, iclass 16, count 0 2006.201.07:00:48.57#ibcon#wrote, iclass 16, count 0 2006.201.07:00:48.57#ibcon#about to read 3, iclass 16, count 0 2006.201.07:00:48.61#ibcon#read 3, iclass 16, count 0 2006.201.07:00:48.61#ibcon#about to read 4, iclass 16, count 0 2006.201.07:00:48.61#ibcon#read 4, iclass 16, count 0 2006.201.07:00:48.61#ibcon#about to read 5, iclass 16, count 0 2006.201.07:00:48.61#ibcon#read 5, iclass 16, count 0 2006.201.07:00:48.61#ibcon#about to read 6, iclass 16, count 0 2006.201.07:00:48.61#ibcon#read 6, iclass 16, count 0 2006.201.07:00:48.61#ibcon#end of sib2, iclass 16, count 0 2006.201.07:00:48.61#ibcon#*after write, iclass 16, count 0 2006.201.07:00:48.61#ibcon#*before return 0, iclass 16, count 0 2006.201.07:00:48.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:48.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:00:48.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:00:48.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:00:48.61$vck44/vb=7,4 2006.201.07:00:48.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.07:00:48.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.07:00:48.61#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:48.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:48.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:48.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:48.67#ibcon#enter wrdev, iclass 18, count 2 2006.201.07:00:48.67#ibcon#first serial, iclass 18, count 2 2006.201.07:00:48.67#ibcon#enter sib2, iclass 18, count 2 2006.201.07:00:48.67#ibcon#flushed, iclass 18, count 2 2006.201.07:00:48.67#ibcon#about to write, iclass 18, count 2 2006.201.07:00:48.67#ibcon#wrote, iclass 18, count 2 2006.201.07:00:48.67#ibcon#about to read 3, iclass 18, count 2 2006.201.07:00:48.69#ibcon#read 3, iclass 18, count 2 2006.201.07:00:48.69#ibcon#about to read 4, iclass 18, count 2 2006.201.07:00:48.69#ibcon#read 4, iclass 18, count 2 2006.201.07:00:48.69#ibcon#about to read 5, iclass 18, count 2 2006.201.07:00:48.69#ibcon#read 5, iclass 18, count 2 2006.201.07:00:48.69#ibcon#about to read 6, iclass 18, count 2 2006.201.07:00:48.69#ibcon#read 6, iclass 18, count 2 2006.201.07:00:48.69#ibcon#end of sib2, iclass 18, count 2 2006.201.07:00:48.69#ibcon#*mode == 0, iclass 18, count 2 2006.201.07:00:48.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.07:00:48.69#ibcon#[27=AT07-04\r\n] 2006.201.07:00:48.69#ibcon#*before write, iclass 18, count 2 2006.201.07:00:48.69#ibcon#enter sib2, iclass 18, count 2 2006.201.07:00:48.69#ibcon#flushed, iclass 18, count 2 2006.201.07:00:48.69#ibcon#about to write, iclass 18, count 2 2006.201.07:00:48.69#ibcon#wrote, iclass 18, count 2 2006.201.07:00:48.69#ibcon#about to read 3, iclass 18, count 2 2006.201.07:00:48.72#ibcon#read 3, iclass 18, count 2 2006.201.07:00:48.72#ibcon#about to read 4, iclass 18, count 2 2006.201.07:00:48.72#ibcon#read 4, iclass 18, count 2 2006.201.07:00:48.72#ibcon#about to read 5, iclass 18, count 2 2006.201.07:00:48.72#ibcon#read 5, iclass 18, count 2 2006.201.07:00:48.72#ibcon#about to read 6, iclass 18, count 2 2006.201.07:00:48.72#ibcon#read 6, iclass 18, count 2 2006.201.07:00:48.72#ibcon#end of sib2, iclass 18, count 2 2006.201.07:00:48.72#ibcon#*after write, iclass 18, count 2 2006.201.07:00:48.72#ibcon#*before return 0, iclass 18, count 2 2006.201.07:00:48.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:48.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:00:48.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.07:00:48.72#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:48.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:48.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:48.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:48.84#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:00:48.84#ibcon#first serial, iclass 18, count 0 2006.201.07:00:48.84#ibcon#enter sib2, iclass 18, count 0 2006.201.07:00:48.84#ibcon#flushed, iclass 18, count 0 2006.201.07:00:48.84#ibcon#about to write, iclass 18, count 0 2006.201.07:00:48.84#ibcon#wrote, iclass 18, count 0 2006.201.07:00:48.84#ibcon#about to read 3, iclass 18, count 0 2006.201.07:00:48.86#ibcon#read 3, iclass 18, count 0 2006.201.07:00:48.86#ibcon#about to read 4, iclass 18, count 0 2006.201.07:00:48.86#ibcon#read 4, iclass 18, count 0 2006.201.07:00:48.86#ibcon#about to read 5, iclass 18, count 0 2006.201.07:00:48.86#ibcon#read 5, iclass 18, count 0 2006.201.07:00:48.86#ibcon#about to read 6, iclass 18, count 0 2006.201.07:00:48.86#ibcon#read 6, iclass 18, count 0 2006.201.07:00:48.86#ibcon#end of sib2, iclass 18, count 0 2006.201.07:00:48.86#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:00:48.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:00:48.86#ibcon#[27=USB\r\n] 2006.201.07:00:48.86#ibcon#*before write, iclass 18, count 0 2006.201.07:00:48.86#ibcon#enter sib2, iclass 18, count 0 2006.201.07:00:48.86#ibcon#flushed, iclass 18, count 0 2006.201.07:00:48.86#ibcon#about to write, iclass 18, count 0 2006.201.07:00:48.86#ibcon#wrote, iclass 18, count 0 2006.201.07:00:48.86#ibcon#about to read 3, iclass 18, count 0 2006.201.07:00:48.89#ibcon#read 3, iclass 18, count 0 2006.201.07:00:48.89#ibcon#about to read 4, iclass 18, count 0 2006.201.07:00:48.89#ibcon#read 4, iclass 18, count 0 2006.201.07:00:48.89#ibcon#about to read 5, iclass 18, count 0 2006.201.07:00:48.89#ibcon#read 5, iclass 18, count 0 2006.201.07:00:48.89#ibcon#about to read 6, iclass 18, count 0 2006.201.07:00:48.89#ibcon#read 6, iclass 18, count 0 2006.201.07:00:48.89#ibcon#end of sib2, iclass 18, count 0 2006.201.07:00:48.89#ibcon#*after write, iclass 18, count 0 2006.201.07:00:48.89#ibcon#*before return 0, iclass 18, count 0 2006.201.07:00:48.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:48.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:00:48.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:00:48.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:00:48.89$vck44/vblo=8,744.99 2006.201.07:00:48.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.07:00:48.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.07:00:48.89#ibcon#ireg 17 cls_cnt 0 2006.201.07:00:48.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:00:48.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:00:48.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:00:48.89#ibcon#enter wrdev, iclass 21, count 0 2006.201.07:00:48.89#ibcon#first serial, iclass 21, count 0 2006.201.07:00:48.89#ibcon#enter sib2, iclass 21, count 0 2006.201.07:00:48.89#ibcon#flushed, iclass 21, count 0 2006.201.07:00:48.89#ibcon#about to write, iclass 21, count 0 2006.201.07:00:48.89#ibcon#wrote, iclass 21, count 0 2006.201.07:00:48.89#ibcon#about to read 3, iclass 21, count 0 2006.201.07:00:48.91#ibcon#read 3, iclass 21, count 0 2006.201.07:00:48.91#ibcon#about to read 4, iclass 21, count 0 2006.201.07:00:48.91#ibcon#read 4, iclass 21, count 0 2006.201.07:00:48.91#ibcon#about to read 5, iclass 21, count 0 2006.201.07:00:48.91#ibcon#read 5, iclass 21, count 0 2006.201.07:00:48.91#ibcon#about to read 6, iclass 21, count 0 2006.201.07:00:48.91#ibcon#read 6, iclass 21, count 0 2006.201.07:00:48.91#ibcon#end of sib2, iclass 21, count 0 2006.201.07:00:48.91#ibcon#*mode == 0, iclass 21, count 0 2006.201.07:00:48.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.07:00:48.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:00:48.91#ibcon#*before write, iclass 21, count 0 2006.201.07:00:48.91#ibcon#enter sib2, iclass 21, count 0 2006.201.07:00:48.91#ibcon#flushed, iclass 21, count 0 2006.201.07:00:48.91#ibcon#about to write, iclass 21, count 0 2006.201.07:00:48.91#ibcon#wrote, iclass 21, count 0 2006.201.07:00:48.91#ibcon#about to read 3, iclass 21, count 0 2006.201.07:00:48.92#abcon#<5=/05 2.5 4.5 23.19 891003.2\r\n> 2006.201.07:00:48.94#abcon#{5=INTERFACE CLEAR} 2006.201.07:00:48.96#ibcon#read 3, iclass 21, count 0 2006.201.07:00:48.96#ibcon#about to read 4, iclass 21, count 0 2006.201.07:00:48.96#ibcon#read 4, iclass 21, count 0 2006.201.07:00:48.96#ibcon#about to read 5, iclass 21, count 0 2006.201.07:00:48.96#ibcon#read 5, iclass 21, count 0 2006.201.07:00:48.96#ibcon#about to read 6, iclass 21, count 0 2006.201.07:00:48.96#ibcon#read 6, iclass 21, count 0 2006.201.07:00:48.96#ibcon#end of sib2, iclass 21, count 0 2006.201.07:00:48.96#ibcon#*after write, iclass 21, count 0 2006.201.07:00:48.96#ibcon#*before return 0, iclass 21, count 0 2006.201.07:00:48.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:00:48.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:00:48.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.07:00:48.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.07:00:48.96$vck44/vb=8,4 2006.201.07:00:48.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.07:00:48.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.07:00:48.96#ibcon#ireg 11 cls_cnt 2 2006.201.07:00:48.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:00:49.00#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:00:49.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:00:49.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:00:49.01#ibcon#enter wrdev, iclass 25, count 2 2006.201.07:00:49.01#ibcon#first serial, iclass 25, count 2 2006.201.07:00:49.01#ibcon#enter sib2, iclass 25, count 2 2006.201.07:00:49.01#ibcon#flushed, iclass 25, count 2 2006.201.07:00:49.01#ibcon#about to write, iclass 25, count 2 2006.201.07:00:49.01#ibcon#wrote, iclass 25, count 2 2006.201.07:00:49.01#ibcon#about to read 3, iclass 25, count 2 2006.201.07:00:49.03#ibcon#read 3, iclass 25, count 2 2006.201.07:00:49.03#ibcon#about to read 4, iclass 25, count 2 2006.201.07:00:49.03#ibcon#read 4, iclass 25, count 2 2006.201.07:00:49.03#ibcon#about to read 5, iclass 25, count 2 2006.201.07:00:49.03#ibcon#read 5, iclass 25, count 2 2006.201.07:00:49.03#ibcon#about to read 6, iclass 25, count 2 2006.201.07:00:49.03#ibcon#read 6, iclass 25, count 2 2006.201.07:00:49.03#ibcon#end of sib2, iclass 25, count 2 2006.201.07:00:49.03#ibcon#*mode == 0, iclass 25, count 2 2006.201.07:00:49.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.07:00:49.03#ibcon#[27=AT08-04\r\n] 2006.201.07:00:49.03#ibcon#*before write, iclass 25, count 2 2006.201.07:00:49.03#ibcon#enter sib2, iclass 25, count 2 2006.201.07:00:49.03#ibcon#flushed, iclass 25, count 2 2006.201.07:00:49.03#ibcon#about to write, iclass 25, count 2 2006.201.07:00:49.03#ibcon#wrote, iclass 25, count 2 2006.201.07:00:49.03#ibcon#about to read 3, iclass 25, count 2 2006.201.07:00:49.06#ibcon#read 3, iclass 25, count 2 2006.201.07:00:49.06#ibcon#about to read 4, iclass 25, count 2 2006.201.07:00:49.06#ibcon#read 4, iclass 25, count 2 2006.201.07:00:49.06#ibcon#about to read 5, iclass 25, count 2 2006.201.07:00:49.06#ibcon#read 5, iclass 25, count 2 2006.201.07:00:49.06#ibcon#about to read 6, iclass 25, count 2 2006.201.07:00:49.06#ibcon#read 6, iclass 25, count 2 2006.201.07:00:49.06#ibcon#end of sib2, iclass 25, count 2 2006.201.07:00:49.06#ibcon#*after write, iclass 25, count 2 2006.201.07:00:49.06#ibcon#*before return 0, iclass 25, count 2 2006.201.07:00:49.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:00:49.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:00:49.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.07:00:49.06#ibcon#ireg 7 cls_cnt 0 2006.201.07:00:49.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:00:49.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:00:49.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:00:49.18#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:00:49.18#ibcon#first serial, iclass 25, count 0 2006.201.07:00:49.18#ibcon#enter sib2, iclass 25, count 0 2006.201.07:00:49.18#ibcon#flushed, iclass 25, count 0 2006.201.07:00:49.18#ibcon#about to write, iclass 25, count 0 2006.201.07:00:49.18#ibcon#wrote, iclass 25, count 0 2006.201.07:00:49.18#ibcon#about to read 3, iclass 25, count 0 2006.201.07:00:49.20#ibcon#read 3, iclass 25, count 0 2006.201.07:00:49.20#ibcon#about to read 4, iclass 25, count 0 2006.201.07:00:49.20#ibcon#read 4, iclass 25, count 0 2006.201.07:00:49.20#ibcon#about to read 5, iclass 25, count 0 2006.201.07:00:49.20#ibcon#read 5, iclass 25, count 0 2006.201.07:00:49.20#ibcon#about to read 6, iclass 25, count 0 2006.201.07:00:49.20#ibcon#read 6, iclass 25, count 0 2006.201.07:00:49.20#ibcon#end of sib2, iclass 25, count 0 2006.201.07:00:49.20#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:00:49.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:00:49.20#ibcon#[27=USB\r\n] 2006.201.07:00:49.20#ibcon#*before write, iclass 25, count 0 2006.201.07:00:49.20#ibcon#enter sib2, iclass 25, count 0 2006.201.07:00:49.20#ibcon#flushed, iclass 25, count 0 2006.201.07:00:49.20#ibcon#about to write, iclass 25, count 0 2006.201.07:00:49.20#ibcon#wrote, iclass 25, count 0 2006.201.07:00:49.20#ibcon#about to read 3, iclass 25, count 0 2006.201.07:00:49.23#ibcon#read 3, iclass 25, count 0 2006.201.07:00:49.23#ibcon#about to read 4, iclass 25, count 0 2006.201.07:00:49.23#ibcon#read 4, iclass 25, count 0 2006.201.07:00:49.23#ibcon#about to read 5, iclass 25, count 0 2006.201.07:00:49.23#ibcon#read 5, iclass 25, count 0 2006.201.07:00:49.23#ibcon#about to read 6, iclass 25, count 0 2006.201.07:00:49.23#ibcon#read 6, iclass 25, count 0 2006.201.07:00:49.23#ibcon#end of sib2, iclass 25, count 0 2006.201.07:00:49.23#ibcon#*after write, iclass 25, count 0 2006.201.07:00:49.23#ibcon#*before return 0, iclass 25, count 0 2006.201.07:00:49.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:00:49.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:00:49.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:00:49.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:00:49.23$vck44/vabw=wide 2006.201.07:00:49.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.07:00:49.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.07:00:49.23#ibcon#ireg 8 cls_cnt 0 2006.201.07:00:49.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:49.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:49.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:49.23#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:00:49.23#ibcon#first serial, iclass 28, count 0 2006.201.07:00:49.23#ibcon#enter sib2, iclass 28, count 0 2006.201.07:00:49.23#ibcon#flushed, iclass 28, count 0 2006.201.07:00:49.23#ibcon#about to write, iclass 28, count 0 2006.201.07:00:49.23#ibcon#wrote, iclass 28, count 0 2006.201.07:00:49.23#ibcon#about to read 3, iclass 28, count 0 2006.201.07:00:49.25#ibcon#read 3, iclass 28, count 0 2006.201.07:00:49.25#ibcon#about to read 4, iclass 28, count 0 2006.201.07:00:49.25#ibcon#read 4, iclass 28, count 0 2006.201.07:00:49.25#ibcon#about to read 5, iclass 28, count 0 2006.201.07:00:49.25#ibcon#read 5, iclass 28, count 0 2006.201.07:00:49.25#ibcon#about to read 6, iclass 28, count 0 2006.201.07:00:49.25#ibcon#read 6, iclass 28, count 0 2006.201.07:00:49.25#ibcon#end of sib2, iclass 28, count 0 2006.201.07:00:49.25#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:00:49.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:00:49.25#ibcon#[25=BW32\r\n] 2006.201.07:00:49.25#ibcon#*before write, iclass 28, count 0 2006.201.07:00:49.25#ibcon#enter sib2, iclass 28, count 0 2006.201.07:00:49.25#ibcon#flushed, iclass 28, count 0 2006.201.07:00:49.25#ibcon#about to write, iclass 28, count 0 2006.201.07:00:49.25#ibcon#wrote, iclass 28, count 0 2006.201.07:00:49.25#ibcon#about to read 3, iclass 28, count 0 2006.201.07:00:49.28#ibcon#read 3, iclass 28, count 0 2006.201.07:00:49.28#ibcon#about to read 4, iclass 28, count 0 2006.201.07:00:49.28#ibcon#read 4, iclass 28, count 0 2006.201.07:00:49.28#ibcon#about to read 5, iclass 28, count 0 2006.201.07:00:49.28#ibcon#read 5, iclass 28, count 0 2006.201.07:00:49.28#ibcon#about to read 6, iclass 28, count 0 2006.201.07:00:49.28#ibcon#read 6, iclass 28, count 0 2006.201.07:00:49.28#ibcon#end of sib2, iclass 28, count 0 2006.201.07:00:49.28#ibcon#*after write, iclass 28, count 0 2006.201.07:00:49.28#ibcon#*before return 0, iclass 28, count 0 2006.201.07:00:49.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:49.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:00:49.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:00:49.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:00:49.28$vck44/vbbw=wide 2006.201.07:00:49.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.07:00:49.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.07:00:49.28#ibcon#ireg 8 cls_cnt 0 2006.201.07:00:49.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:00:49.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:00:49.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:00:49.35#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:00:49.35#ibcon#first serial, iclass 30, count 0 2006.201.07:00:49.35#ibcon#enter sib2, iclass 30, count 0 2006.201.07:00:49.35#ibcon#flushed, iclass 30, count 0 2006.201.07:00:49.35#ibcon#about to write, iclass 30, count 0 2006.201.07:00:49.35#ibcon#wrote, iclass 30, count 0 2006.201.07:00:49.35#ibcon#about to read 3, iclass 30, count 0 2006.201.07:00:49.37#ibcon#read 3, iclass 30, count 0 2006.201.07:00:49.37#ibcon#about to read 4, iclass 30, count 0 2006.201.07:00:49.37#ibcon#read 4, iclass 30, count 0 2006.201.07:00:49.37#ibcon#about to read 5, iclass 30, count 0 2006.201.07:00:49.37#ibcon#read 5, iclass 30, count 0 2006.201.07:00:49.37#ibcon#about to read 6, iclass 30, count 0 2006.201.07:00:49.37#ibcon#read 6, iclass 30, count 0 2006.201.07:00:49.37#ibcon#end of sib2, iclass 30, count 0 2006.201.07:00:49.37#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:00:49.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:00:49.37#ibcon#[27=BW32\r\n] 2006.201.07:00:49.37#ibcon#*before write, iclass 30, count 0 2006.201.07:00:49.37#ibcon#enter sib2, iclass 30, count 0 2006.201.07:00:49.37#ibcon#flushed, iclass 30, count 0 2006.201.07:00:49.37#ibcon#about to write, iclass 30, count 0 2006.201.07:00:49.37#ibcon#wrote, iclass 30, count 0 2006.201.07:00:49.37#ibcon#about to read 3, iclass 30, count 0 2006.201.07:00:49.40#ibcon#read 3, iclass 30, count 0 2006.201.07:00:49.40#ibcon#about to read 4, iclass 30, count 0 2006.201.07:00:49.40#ibcon#read 4, iclass 30, count 0 2006.201.07:00:49.40#ibcon#about to read 5, iclass 30, count 0 2006.201.07:00:49.40#ibcon#read 5, iclass 30, count 0 2006.201.07:00:49.40#ibcon#about to read 6, iclass 30, count 0 2006.201.07:00:49.40#ibcon#read 6, iclass 30, count 0 2006.201.07:00:49.40#ibcon#end of sib2, iclass 30, count 0 2006.201.07:00:49.40#ibcon#*after write, iclass 30, count 0 2006.201.07:00:49.40#ibcon#*before return 0, iclass 30, count 0 2006.201.07:00:49.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:00:49.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:00:49.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:00:49.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:00:49.40$setupk4/ifdk4 2006.201.07:00:49.40$ifdk4/lo= 2006.201.07:00:49.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:00:49.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:00:49.40$ifdk4/patch= 2006.201.07:00:49.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:00:49.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:00:49.40$setupk4/!*+20s 2006.201.07:00:59.09#abcon#<5=/05 2.5 4.5 23.19 891003.2\r\n> 2006.201.07:00:59.11#abcon#{5=INTERFACE CLEAR} 2006.201.07:00:59.17#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:01:03.88$setupk4/"tpicd 2006.201.07:01:03.88$setupk4/echo=off 2006.201.07:01:03.88$setupk4/xlog=off 2006.201.07:01:03.88:!2006.201.07:03:51 2006.201.07:01:05.13#trakl#Source acquired 2006.201.07:01:07.13#flagr#flagr/antenna,acquired 2006.201.07:03:51.00:preob 2006.201.07:03:51.14/onsource/TRACKING 2006.201.07:03:51.14:!2006.201.07:04:01 2006.201.07:04:01.00:"tape 2006.201.07:04:01.00:"st=record 2006.201.07:04:01.00:data_valid=on 2006.201.07:04:01.00:midob 2006.201.07:04:01.14/onsource/TRACKING 2006.201.07:04:01.14/wx/23.19,1003.2,89 2006.201.07:04:01.28/cable/+6.4697E-03 2006.201.07:04:02.37/va/01,08,usb,yes,36,39 2006.201.07:04:02.37/va/02,07,usb,yes,39,40 2006.201.07:04:02.37/va/03,08,usb,yes,35,37 2006.201.07:04:02.37/va/04,07,usb,yes,40,42 2006.201.07:04:02.37/va/05,04,usb,yes,35,36 2006.201.07:04:02.37/va/06,05,usb,yes,35,35 2006.201.07:04:02.37/va/07,05,usb,yes,35,36 2006.201.07:04:02.37/va/08,04,usb,yes,34,41 2006.201.07:04:02.60/valo/01,524.99,yes,locked 2006.201.07:04:02.60/valo/02,534.99,yes,locked 2006.201.07:04:02.60/valo/03,564.99,yes,locked 2006.201.07:04:02.60/valo/04,624.99,yes,locked 2006.201.07:04:02.60/valo/05,734.99,yes,locked 2006.201.07:04:02.60/valo/06,814.99,yes,locked 2006.201.07:04:02.60/valo/07,864.99,yes,locked 2006.201.07:04:02.60/valo/08,884.99,yes,locked 2006.201.07:04:03.69/vb/01,04,usb,yes,31,29 2006.201.07:04:03.69/vb/02,05,usb,yes,30,30 2006.201.07:04:03.69/vb/03,04,usb,yes,31,34 2006.201.07:04:03.69/vb/04,05,usb,yes,31,30 2006.201.07:04:03.69/vb/05,04,usb,yes,27,30 2006.201.07:04:03.69/vb/06,04,usb,yes,32,28 2006.201.07:04:03.69/vb/07,04,usb,yes,32,32 2006.201.07:04:03.69/vb/08,04,usb,yes,29,33 2006.201.07:04:03.93/vblo/01,629.99,yes,locked 2006.201.07:04:03.93/vblo/02,634.99,yes,locked 2006.201.07:04:03.93/vblo/03,649.99,yes,locked 2006.201.07:04:03.93/vblo/04,679.99,yes,locked 2006.201.07:04:03.93/vblo/05,709.99,yes,locked 2006.201.07:04:03.93/vblo/06,719.99,yes,locked 2006.201.07:04:03.93/vblo/07,734.99,yes,locked 2006.201.07:04:03.93/vblo/08,744.99,yes,locked 2006.201.07:04:04.08/vabw/8 2006.201.07:04:04.23/vbbw/8 2006.201.07:04:04.34/xfe/off,on,15.2 2006.201.07:04:04.72/ifatt/23,28,28,28 2006.201.07:04:05.06/fmout-gps/S +4.56E-07 2006.201.07:04:05.13:!2006.201.07:04:41 2006.201.07:04:41.00:data_valid=off 2006.201.07:04:41.00:"et 2006.201.07:04:41.00:!+3s 2006.201.07:04:44.02:"tape 2006.201.07:04:44.02:postob 2006.201.07:04:44.20/cable/+6.4684E-03 2006.201.07:04:44.20/wx/23.19,1003.2,89 2006.201.07:04:44.26/fmout-gps/S +4.55E-07 2006.201.07:04:44.26:scan_name=201-0709,jd0607,40 2006.201.07:04:44.26:source=1424-418,142756.30,-420619.4,2000.0,ccw 2006.201.07:04:46.14#flagr#flagr/antenna,new-source 2006.201.07:04:46.14:checkk5 2006.201.07:04:46.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:04:46.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:04:47.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:04:47.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:04:48.01/chk_obsdata//k5ts1/T2010704??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:04:48.37/chk_obsdata//k5ts2/T2010704??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:04:48.74/chk_obsdata//k5ts3/T2010704??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:04:49.11/chk_obsdata//k5ts4/T2010704??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:04:49.81/k5log//k5ts1_log_newline 2006.201.07:04:50.49/k5log//k5ts2_log_newline 2006.201.07:04:51.20/k5log//k5ts3_log_newline 2006.201.07:04:51.85/k5log//k5ts4_log_newline 2006.201.07:04:51.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:04:51.87:setupk4=1 2006.201.07:04:51.87$setupk4/echo=on 2006.201.07:04:51.87$setupk4/pcalon 2006.201.07:04:51.87$pcalon/"no phase cal control is implemented here 2006.201.07:04:51.87$setupk4/"tpicd=stop 2006.201.07:04:51.87$setupk4/"rec=synch_on 2006.201.07:04:51.87$setupk4/"rec_mode=128 2006.201.07:04:51.87$setupk4/!* 2006.201.07:04:51.87$setupk4/recpk4 2006.201.07:04:51.87$recpk4/recpatch= 2006.201.07:04:51.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:04:51.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:04:51.88$setupk4/vck44 2006.201.07:04:51.88$vck44/valo=1,524.99 2006.201.07:04:51.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.07:04:51.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.07:04:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:51.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:51.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:51.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:51.88#ibcon#enter wrdev, iclass 19, count 0 2006.201.07:04:51.88#ibcon#first serial, iclass 19, count 0 2006.201.07:04:51.88#ibcon#enter sib2, iclass 19, count 0 2006.201.07:04:51.88#ibcon#flushed, iclass 19, count 0 2006.201.07:04:51.88#ibcon#about to write, iclass 19, count 0 2006.201.07:04:51.88#ibcon#wrote, iclass 19, count 0 2006.201.07:04:51.88#ibcon#about to read 3, iclass 19, count 0 2006.201.07:04:51.91#ibcon#read 3, iclass 19, count 0 2006.201.07:04:51.91#ibcon#about to read 4, iclass 19, count 0 2006.201.07:04:51.91#ibcon#read 4, iclass 19, count 0 2006.201.07:04:51.91#ibcon#about to read 5, iclass 19, count 0 2006.201.07:04:51.91#ibcon#read 5, iclass 19, count 0 2006.201.07:04:51.91#ibcon#about to read 6, iclass 19, count 0 2006.201.07:04:51.91#ibcon#read 6, iclass 19, count 0 2006.201.07:04:51.91#ibcon#end of sib2, iclass 19, count 0 2006.201.07:04:51.91#ibcon#*mode == 0, iclass 19, count 0 2006.201.07:04:51.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.07:04:51.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:04:51.91#ibcon#*before write, iclass 19, count 0 2006.201.07:04:51.91#ibcon#enter sib2, iclass 19, count 0 2006.201.07:04:51.91#ibcon#flushed, iclass 19, count 0 2006.201.07:04:51.91#ibcon#about to write, iclass 19, count 0 2006.201.07:04:51.91#ibcon#wrote, iclass 19, count 0 2006.201.07:04:51.91#ibcon#about to read 3, iclass 19, count 0 2006.201.07:04:51.96#ibcon#read 3, iclass 19, count 0 2006.201.07:04:51.96#ibcon#about to read 4, iclass 19, count 0 2006.201.07:04:51.96#ibcon#read 4, iclass 19, count 0 2006.201.07:04:51.96#ibcon#about to read 5, iclass 19, count 0 2006.201.07:04:51.96#ibcon#read 5, iclass 19, count 0 2006.201.07:04:51.96#ibcon#about to read 6, iclass 19, count 0 2006.201.07:04:51.96#ibcon#read 6, iclass 19, count 0 2006.201.07:04:51.96#ibcon#end of sib2, iclass 19, count 0 2006.201.07:04:51.96#ibcon#*after write, iclass 19, count 0 2006.201.07:04:51.96#ibcon#*before return 0, iclass 19, count 0 2006.201.07:04:51.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:51.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:51.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.07:04:51.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.07:04:51.96$vck44/va=1,8 2006.201.07:04:51.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.07:04:51.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.07:04:51.96#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:51.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:51.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:51.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:51.96#ibcon#enter wrdev, iclass 21, count 2 2006.201.07:04:51.96#ibcon#first serial, iclass 21, count 2 2006.201.07:04:51.96#ibcon#enter sib2, iclass 21, count 2 2006.201.07:04:51.96#ibcon#flushed, iclass 21, count 2 2006.201.07:04:51.96#ibcon#about to write, iclass 21, count 2 2006.201.07:04:51.96#ibcon#wrote, iclass 21, count 2 2006.201.07:04:51.96#ibcon#about to read 3, iclass 21, count 2 2006.201.07:04:51.98#ibcon#read 3, iclass 21, count 2 2006.201.07:04:51.98#ibcon#about to read 4, iclass 21, count 2 2006.201.07:04:51.98#ibcon#read 4, iclass 21, count 2 2006.201.07:04:51.98#ibcon#about to read 5, iclass 21, count 2 2006.201.07:04:51.98#ibcon#read 5, iclass 21, count 2 2006.201.07:04:51.98#ibcon#about to read 6, iclass 21, count 2 2006.201.07:04:51.98#ibcon#read 6, iclass 21, count 2 2006.201.07:04:51.98#ibcon#end of sib2, iclass 21, count 2 2006.201.07:04:51.98#ibcon#*mode == 0, iclass 21, count 2 2006.201.07:04:51.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.07:04:51.98#ibcon#[25=AT01-08\r\n] 2006.201.07:04:51.98#ibcon#*before write, iclass 21, count 2 2006.201.07:04:51.98#ibcon#enter sib2, iclass 21, count 2 2006.201.07:04:51.98#ibcon#flushed, iclass 21, count 2 2006.201.07:04:51.98#ibcon#about to write, iclass 21, count 2 2006.201.07:04:51.98#ibcon#wrote, iclass 21, count 2 2006.201.07:04:51.98#ibcon#about to read 3, iclass 21, count 2 2006.201.07:04:52.01#ibcon#read 3, iclass 21, count 2 2006.201.07:04:52.01#ibcon#about to read 4, iclass 21, count 2 2006.201.07:04:52.01#ibcon#read 4, iclass 21, count 2 2006.201.07:04:52.01#ibcon#about to read 5, iclass 21, count 2 2006.201.07:04:52.01#ibcon#read 5, iclass 21, count 2 2006.201.07:04:52.01#ibcon#about to read 6, iclass 21, count 2 2006.201.07:04:52.01#ibcon#read 6, iclass 21, count 2 2006.201.07:04:52.01#ibcon#end of sib2, iclass 21, count 2 2006.201.07:04:52.01#ibcon#*after write, iclass 21, count 2 2006.201.07:04:52.01#ibcon#*before return 0, iclass 21, count 2 2006.201.07:04:52.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:52.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:52.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.07:04:52.01#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:52.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:52.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:52.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:52.13#ibcon#enter wrdev, iclass 21, count 0 2006.201.07:04:52.13#ibcon#first serial, iclass 21, count 0 2006.201.07:04:52.13#ibcon#enter sib2, iclass 21, count 0 2006.201.07:04:52.13#ibcon#flushed, iclass 21, count 0 2006.201.07:04:52.13#ibcon#about to write, iclass 21, count 0 2006.201.07:04:52.13#ibcon#wrote, iclass 21, count 0 2006.201.07:04:52.13#ibcon#about to read 3, iclass 21, count 0 2006.201.07:04:52.15#ibcon#read 3, iclass 21, count 0 2006.201.07:04:52.15#ibcon#about to read 4, iclass 21, count 0 2006.201.07:04:52.15#ibcon#read 4, iclass 21, count 0 2006.201.07:04:52.15#ibcon#about to read 5, iclass 21, count 0 2006.201.07:04:52.15#ibcon#read 5, iclass 21, count 0 2006.201.07:04:52.15#ibcon#about to read 6, iclass 21, count 0 2006.201.07:04:52.15#ibcon#read 6, iclass 21, count 0 2006.201.07:04:52.15#ibcon#end of sib2, iclass 21, count 0 2006.201.07:04:52.15#ibcon#*mode == 0, iclass 21, count 0 2006.201.07:04:52.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.07:04:52.15#ibcon#[25=USB\r\n] 2006.201.07:04:52.15#ibcon#*before write, iclass 21, count 0 2006.201.07:04:52.15#ibcon#enter sib2, iclass 21, count 0 2006.201.07:04:52.15#ibcon#flushed, iclass 21, count 0 2006.201.07:04:52.15#ibcon#about to write, iclass 21, count 0 2006.201.07:04:52.15#ibcon#wrote, iclass 21, count 0 2006.201.07:04:52.15#ibcon#about to read 3, iclass 21, count 0 2006.201.07:04:52.18#ibcon#read 3, iclass 21, count 0 2006.201.07:04:52.18#ibcon#about to read 4, iclass 21, count 0 2006.201.07:04:52.18#ibcon#read 4, iclass 21, count 0 2006.201.07:04:52.18#ibcon#about to read 5, iclass 21, count 0 2006.201.07:04:52.18#ibcon#read 5, iclass 21, count 0 2006.201.07:04:52.18#ibcon#about to read 6, iclass 21, count 0 2006.201.07:04:52.18#ibcon#read 6, iclass 21, count 0 2006.201.07:04:52.18#ibcon#end of sib2, iclass 21, count 0 2006.201.07:04:52.18#ibcon#*after write, iclass 21, count 0 2006.201.07:04:52.18#ibcon#*before return 0, iclass 21, count 0 2006.201.07:04:52.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:52.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:52.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.07:04:52.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.07:04:52.18$vck44/valo=2,534.99 2006.201.07:04:52.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.07:04:52.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.07:04:52.18#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:52.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:52.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:52.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:52.18#ibcon#enter wrdev, iclass 23, count 0 2006.201.07:04:52.18#ibcon#first serial, iclass 23, count 0 2006.201.07:04:52.18#ibcon#enter sib2, iclass 23, count 0 2006.201.07:04:52.18#ibcon#flushed, iclass 23, count 0 2006.201.07:04:52.18#ibcon#about to write, iclass 23, count 0 2006.201.07:04:52.18#ibcon#wrote, iclass 23, count 0 2006.201.07:04:52.18#ibcon#about to read 3, iclass 23, count 0 2006.201.07:04:52.20#ibcon#read 3, iclass 23, count 0 2006.201.07:04:52.20#ibcon#about to read 4, iclass 23, count 0 2006.201.07:04:52.20#ibcon#read 4, iclass 23, count 0 2006.201.07:04:52.20#ibcon#about to read 5, iclass 23, count 0 2006.201.07:04:52.20#ibcon#read 5, iclass 23, count 0 2006.201.07:04:52.20#ibcon#about to read 6, iclass 23, count 0 2006.201.07:04:52.20#ibcon#read 6, iclass 23, count 0 2006.201.07:04:52.20#ibcon#end of sib2, iclass 23, count 0 2006.201.07:04:52.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.07:04:52.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.07:04:52.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:04:52.20#ibcon#*before write, iclass 23, count 0 2006.201.07:04:52.20#ibcon#enter sib2, iclass 23, count 0 2006.201.07:04:52.20#ibcon#flushed, iclass 23, count 0 2006.201.07:04:52.20#ibcon#about to write, iclass 23, count 0 2006.201.07:04:52.20#ibcon#wrote, iclass 23, count 0 2006.201.07:04:52.20#ibcon#about to read 3, iclass 23, count 0 2006.201.07:04:52.25#ibcon#read 3, iclass 23, count 0 2006.201.07:04:52.25#ibcon#about to read 4, iclass 23, count 0 2006.201.07:04:52.25#ibcon#read 4, iclass 23, count 0 2006.201.07:04:52.25#ibcon#about to read 5, iclass 23, count 0 2006.201.07:04:52.25#ibcon#read 5, iclass 23, count 0 2006.201.07:04:52.25#ibcon#about to read 6, iclass 23, count 0 2006.201.07:04:52.25#ibcon#read 6, iclass 23, count 0 2006.201.07:04:52.25#ibcon#end of sib2, iclass 23, count 0 2006.201.07:04:52.25#ibcon#*after write, iclass 23, count 0 2006.201.07:04:52.25#ibcon#*before return 0, iclass 23, count 0 2006.201.07:04:52.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:52.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:52.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.07:04:52.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.07:04:52.25$vck44/va=2,7 2006.201.07:04:52.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.07:04:52.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.07:04:52.25#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:52.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:52.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:52.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:52.30#ibcon#enter wrdev, iclass 25, count 2 2006.201.07:04:52.30#ibcon#first serial, iclass 25, count 2 2006.201.07:04:52.30#ibcon#enter sib2, iclass 25, count 2 2006.201.07:04:52.30#ibcon#flushed, iclass 25, count 2 2006.201.07:04:52.30#ibcon#about to write, iclass 25, count 2 2006.201.07:04:52.30#ibcon#wrote, iclass 25, count 2 2006.201.07:04:52.30#ibcon#about to read 3, iclass 25, count 2 2006.201.07:04:52.32#ibcon#read 3, iclass 25, count 2 2006.201.07:04:52.32#ibcon#about to read 4, iclass 25, count 2 2006.201.07:04:52.32#ibcon#read 4, iclass 25, count 2 2006.201.07:04:52.32#ibcon#about to read 5, iclass 25, count 2 2006.201.07:04:52.32#ibcon#read 5, iclass 25, count 2 2006.201.07:04:52.32#ibcon#about to read 6, iclass 25, count 2 2006.201.07:04:52.32#ibcon#read 6, iclass 25, count 2 2006.201.07:04:52.32#ibcon#end of sib2, iclass 25, count 2 2006.201.07:04:52.32#ibcon#*mode == 0, iclass 25, count 2 2006.201.07:04:52.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.07:04:52.32#ibcon#[25=AT02-07\r\n] 2006.201.07:04:52.32#ibcon#*before write, iclass 25, count 2 2006.201.07:04:52.32#ibcon#enter sib2, iclass 25, count 2 2006.201.07:04:52.32#ibcon#flushed, iclass 25, count 2 2006.201.07:04:52.32#ibcon#about to write, iclass 25, count 2 2006.201.07:04:52.32#ibcon#wrote, iclass 25, count 2 2006.201.07:04:52.32#ibcon#about to read 3, iclass 25, count 2 2006.201.07:04:52.35#ibcon#read 3, iclass 25, count 2 2006.201.07:04:52.35#ibcon#about to read 4, iclass 25, count 2 2006.201.07:04:52.35#ibcon#read 4, iclass 25, count 2 2006.201.07:04:52.35#ibcon#about to read 5, iclass 25, count 2 2006.201.07:04:52.35#ibcon#read 5, iclass 25, count 2 2006.201.07:04:52.35#ibcon#about to read 6, iclass 25, count 2 2006.201.07:04:52.35#ibcon#read 6, iclass 25, count 2 2006.201.07:04:52.35#ibcon#end of sib2, iclass 25, count 2 2006.201.07:04:52.35#ibcon#*after write, iclass 25, count 2 2006.201.07:04:52.35#ibcon#*before return 0, iclass 25, count 2 2006.201.07:04:52.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:52.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:52.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.07:04:52.35#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:52.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:52.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:52.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:52.47#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:04:52.47#ibcon#first serial, iclass 25, count 0 2006.201.07:04:52.47#ibcon#enter sib2, iclass 25, count 0 2006.201.07:04:52.47#ibcon#flushed, iclass 25, count 0 2006.201.07:04:52.47#ibcon#about to write, iclass 25, count 0 2006.201.07:04:52.47#ibcon#wrote, iclass 25, count 0 2006.201.07:04:52.47#ibcon#about to read 3, iclass 25, count 0 2006.201.07:04:52.49#ibcon#read 3, iclass 25, count 0 2006.201.07:04:52.49#ibcon#about to read 4, iclass 25, count 0 2006.201.07:04:52.49#ibcon#read 4, iclass 25, count 0 2006.201.07:04:52.49#ibcon#about to read 5, iclass 25, count 0 2006.201.07:04:52.49#ibcon#read 5, iclass 25, count 0 2006.201.07:04:52.49#ibcon#about to read 6, iclass 25, count 0 2006.201.07:04:52.49#ibcon#read 6, iclass 25, count 0 2006.201.07:04:52.49#ibcon#end of sib2, iclass 25, count 0 2006.201.07:04:52.49#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:04:52.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:04:52.49#ibcon#[25=USB\r\n] 2006.201.07:04:52.49#ibcon#*before write, iclass 25, count 0 2006.201.07:04:52.49#ibcon#enter sib2, iclass 25, count 0 2006.201.07:04:52.49#ibcon#flushed, iclass 25, count 0 2006.201.07:04:52.49#ibcon#about to write, iclass 25, count 0 2006.201.07:04:52.49#ibcon#wrote, iclass 25, count 0 2006.201.07:04:52.49#ibcon#about to read 3, iclass 25, count 0 2006.201.07:04:52.52#ibcon#read 3, iclass 25, count 0 2006.201.07:04:52.52#ibcon#about to read 4, iclass 25, count 0 2006.201.07:04:52.52#ibcon#read 4, iclass 25, count 0 2006.201.07:04:52.52#ibcon#about to read 5, iclass 25, count 0 2006.201.07:04:52.52#ibcon#read 5, iclass 25, count 0 2006.201.07:04:52.52#ibcon#about to read 6, iclass 25, count 0 2006.201.07:04:52.52#ibcon#read 6, iclass 25, count 0 2006.201.07:04:52.52#ibcon#end of sib2, iclass 25, count 0 2006.201.07:04:52.52#ibcon#*after write, iclass 25, count 0 2006.201.07:04:52.52#ibcon#*before return 0, iclass 25, count 0 2006.201.07:04:52.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:52.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:52.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:04:52.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:04:52.52$vck44/valo=3,564.99 2006.201.07:04:52.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.07:04:52.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.07:04:52.52#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:52.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:52.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:52.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:52.52#ibcon#enter wrdev, iclass 27, count 0 2006.201.07:04:52.52#ibcon#first serial, iclass 27, count 0 2006.201.07:04:52.52#ibcon#enter sib2, iclass 27, count 0 2006.201.07:04:52.52#ibcon#flushed, iclass 27, count 0 2006.201.07:04:52.52#ibcon#about to write, iclass 27, count 0 2006.201.07:04:52.52#ibcon#wrote, iclass 27, count 0 2006.201.07:04:52.52#ibcon#about to read 3, iclass 27, count 0 2006.201.07:04:52.54#ibcon#read 3, iclass 27, count 0 2006.201.07:04:52.54#ibcon#about to read 4, iclass 27, count 0 2006.201.07:04:52.54#ibcon#read 4, iclass 27, count 0 2006.201.07:04:52.54#ibcon#about to read 5, iclass 27, count 0 2006.201.07:04:52.54#ibcon#read 5, iclass 27, count 0 2006.201.07:04:52.54#ibcon#about to read 6, iclass 27, count 0 2006.201.07:04:52.54#ibcon#read 6, iclass 27, count 0 2006.201.07:04:52.54#ibcon#end of sib2, iclass 27, count 0 2006.201.07:04:52.54#ibcon#*mode == 0, iclass 27, count 0 2006.201.07:04:52.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.07:04:52.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:04:52.54#ibcon#*before write, iclass 27, count 0 2006.201.07:04:52.54#ibcon#enter sib2, iclass 27, count 0 2006.201.07:04:52.54#ibcon#flushed, iclass 27, count 0 2006.201.07:04:52.54#ibcon#about to write, iclass 27, count 0 2006.201.07:04:52.54#ibcon#wrote, iclass 27, count 0 2006.201.07:04:52.54#ibcon#about to read 3, iclass 27, count 0 2006.201.07:04:52.59#ibcon#read 3, iclass 27, count 0 2006.201.07:04:52.59#ibcon#about to read 4, iclass 27, count 0 2006.201.07:04:52.59#ibcon#read 4, iclass 27, count 0 2006.201.07:04:52.59#ibcon#about to read 5, iclass 27, count 0 2006.201.07:04:52.59#ibcon#read 5, iclass 27, count 0 2006.201.07:04:52.59#ibcon#about to read 6, iclass 27, count 0 2006.201.07:04:52.59#ibcon#read 6, iclass 27, count 0 2006.201.07:04:52.59#ibcon#end of sib2, iclass 27, count 0 2006.201.07:04:52.59#ibcon#*after write, iclass 27, count 0 2006.201.07:04:52.59#ibcon#*before return 0, iclass 27, count 0 2006.201.07:04:52.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:52.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:52.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.07:04:52.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.07:04:52.59$vck44/va=3,8 2006.201.07:04:52.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.07:04:52.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.07:04:52.59#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:52.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:52.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:52.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:52.64#ibcon#enter wrdev, iclass 29, count 2 2006.201.07:04:52.64#ibcon#first serial, iclass 29, count 2 2006.201.07:04:52.64#ibcon#enter sib2, iclass 29, count 2 2006.201.07:04:52.64#ibcon#flushed, iclass 29, count 2 2006.201.07:04:52.64#ibcon#about to write, iclass 29, count 2 2006.201.07:04:52.64#ibcon#wrote, iclass 29, count 2 2006.201.07:04:52.64#ibcon#about to read 3, iclass 29, count 2 2006.201.07:04:52.66#ibcon#read 3, iclass 29, count 2 2006.201.07:04:52.66#ibcon#about to read 4, iclass 29, count 2 2006.201.07:04:52.66#ibcon#read 4, iclass 29, count 2 2006.201.07:04:52.66#ibcon#about to read 5, iclass 29, count 2 2006.201.07:04:52.66#ibcon#read 5, iclass 29, count 2 2006.201.07:04:52.66#ibcon#about to read 6, iclass 29, count 2 2006.201.07:04:52.66#ibcon#read 6, iclass 29, count 2 2006.201.07:04:52.66#ibcon#end of sib2, iclass 29, count 2 2006.201.07:04:52.66#ibcon#*mode == 0, iclass 29, count 2 2006.201.07:04:52.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.07:04:52.66#ibcon#[25=AT03-08\r\n] 2006.201.07:04:52.66#ibcon#*before write, iclass 29, count 2 2006.201.07:04:52.66#ibcon#enter sib2, iclass 29, count 2 2006.201.07:04:52.66#ibcon#flushed, iclass 29, count 2 2006.201.07:04:52.66#ibcon#about to write, iclass 29, count 2 2006.201.07:04:52.66#ibcon#wrote, iclass 29, count 2 2006.201.07:04:52.66#ibcon#about to read 3, iclass 29, count 2 2006.201.07:04:52.69#ibcon#read 3, iclass 29, count 2 2006.201.07:04:52.69#ibcon#about to read 4, iclass 29, count 2 2006.201.07:04:52.69#ibcon#read 4, iclass 29, count 2 2006.201.07:04:52.69#ibcon#about to read 5, iclass 29, count 2 2006.201.07:04:52.69#ibcon#read 5, iclass 29, count 2 2006.201.07:04:52.69#ibcon#about to read 6, iclass 29, count 2 2006.201.07:04:52.69#ibcon#read 6, iclass 29, count 2 2006.201.07:04:52.69#ibcon#end of sib2, iclass 29, count 2 2006.201.07:04:52.69#ibcon#*after write, iclass 29, count 2 2006.201.07:04:52.69#ibcon#*before return 0, iclass 29, count 2 2006.201.07:04:52.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:52.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:52.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.07:04:52.69#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:52.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:52.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:52.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:52.81#ibcon#enter wrdev, iclass 29, count 0 2006.201.07:04:52.81#ibcon#first serial, iclass 29, count 0 2006.201.07:04:52.81#ibcon#enter sib2, iclass 29, count 0 2006.201.07:04:52.81#ibcon#flushed, iclass 29, count 0 2006.201.07:04:52.81#ibcon#about to write, iclass 29, count 0 2006.201.07:04:52.81#ibcon#wrote, iclass 29, count 0 2006.201.07:04:52.81#ibcon#about to read 3, iclass 29, count 0 2006.201.07:04:52.83#ibcon#read 3, iclass 29, count 0 2006.201.07:04:52.83#ibcon#about to read 4, iclass 29, count 0 2006.201.07:04:52.83#ibcon#read 4, iclass 29, count 0 2006.201.07:04:52.83#ibcon#about to read 5, iclass 29, count 0 2006.201.07:04:52.83#ibcon#read 5, iclass 29, count 0 2006.201.07:04:52.83#ibcon#about to read 6, iclass 29, count 0 2006.201.07:04:52.83#ibcon#read 6, iclass 29, count 0 2006.201.07:04:52.83#ibcon#end of sib2, iclass 29, count 0 2006.201.07:04:52.83#ibcon#*mode == 0, iclass 29, count 0 2006.201.07:04:52.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.07:04:52.83#ibcon#[25=USB\r\n] 2006.201.07:04:52.83#ibcon#*before write, iclass 29, count 0 2006.201.07:04:52.83#ibcon#enter sib2, iclass 29, count 0 2006.201.07:04:52.83#ibcon#flushed, iclass 29, count 0 2006.201.07:04:52.83#ibcon#about to write, iclass 29, count 0 2006.201.07:04:52.83#ibcon#wrote, iclass 29, count 0 2006.201.07:04:52.83#ibcon#about to read 3, iclass 29, count 0 2006.201.07:04:52.86#ibcon#read 3, iclass 29, count 0 2006.201.07:04:52.86#ibcon#about to read 4, iclass 29, count 0 2006.201.07:04:52.86#ibcon#read 4, iclass 29, count 0 2006.201.07:04:52.86#ibcon#about to read 5, iclass 29, count 0 2006.201.07:04:52.86#ibcon#read 5, iclass 29, count 0 2006.201.07:04:52.86#ibcon#about to read 6, iclass 29, count 0 2006.201.07:04:52.86#ibcon#read 6, iclass 29, count 0 2006.201.07:04:52.86#ibcon#end of sib2, iclass 29, count 0 2006.201.07:04:52.86#ibcon#*after write, iclass 29, count 0 2006.201.07:04:52.86#ibcon#*before return 0, iclass 29, count 0 2006.201.07:04:52.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:52.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:52.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.07:04:52.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.07:04:52.86$vck44/valo=4,624.99 2006.201.07:04:52.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.07:04:52.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.07:04:52.86#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:52.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:52.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:52.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:52.86#ibcon#enter wrdev, iclass 31, count 0 2006.201.07:04:52.86#ibcon#first serial, iclass 31, count 0 2006.201.07:04:52.86#ibcon#enter sib2, iclass 31, count 0 2006.201.07:04:52.86#ibcon#flushed, iclass 31, count 0 2006.201.07:04:52.86#ibcon#about to write, iclass 31, count 0 2006.201.07:04:52.86#ibcon#wrote, iclass 31, count 0 2006.201.07:04:52.86#ibcon#about to read 3, iclass 31, count 0 2006.201.07:04:52.88#ibcon#read 3, iclass 31, count 0 2006.201.07:04:52.88#ibcon#about to read 4, iclass 31, count 0 2006.201.07:04:52.88#ibcon#read 4, iclass 31, count 0 2006.201.07:04:52.88#ibcon#about to read 5, iclass 31, count 0 2006.201.07:04:52.88#ibcon#read 5, iclass 31, count 0 2006.201.07:04:52.88#ibcon#about to read 6, iclass 31, count 0 2006.201.07:04:52.88#ibcon#read 6, iclass 31, count 0 2006.201.07:04:52.88#ibcon#end of sib2, iclass 31, count 0 2006.201.07:04:52.88#ibcon#*mode == 0, iclass 31, count 0 2006.201.07:04:52.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.07:04:52.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:04:52.88#ibcon#*before write, iclass 31, count 0 2006.201.07:04:52.88#ibcon#enter sib2, iclass 31, count 0 2006.201.07:04:52.88#ibcon#flushed, iclass 31, count 0 2006.201.07:04:52.88#ibcon#about to write, iclass 31, count 0 2006.201.07:04:52.88#ibcon#wrote, iclass 31, count 0 2006.201.07:04:52.88#ibcon#about to read 3, iclass 31, count 0 2006.201.07:04:52.93#ibcon#read 3, iclass 31, count 0 2006.201.07:04:52.93#ibcon#about to read 4, iclass 31, count 0 2006.201.07:04:52.93#ibcon#read 4, iclass 31, count 0 2006.201.07:04:52.93#ibcon#about to read 5, iclass 31, count 0 2006.201.07:04:52.93#ibcon#read 5, iclass 31, count 0 2006.201.07:04:52.93#ibcon#about to read 6, iclass 31, count 0 2006.201.07:04:52.93#ibcon#read 6, iclass 31, count 0 2006.201.07:04:52.93#ibcon#end of sib2, iclass 31, count 0 2006.201.07:04:52.93#ibcon#*after write, iclass 31, count 0 2006.201.07:04:52.93#ibcon#*before return 0, iclass 31, count 0 2006.201.07:04:52.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:52.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:52.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.07:04:52.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.07:04:52.93$vck44/va=4,7 2006.201.07:04:52.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.07:04:52.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.07:04:52.93#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:52.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:52.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:52.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:52.98#ibcon#enter wrdev, iclass 33, count 2 2006.201.07:04:52.98#ibcon#first serial, iclass 33, count 2 2006.201.07:04:52.98#ibcon#enter sib2, iclass 33, count 2 2006.201.07:04:52.98#ibcon#flushed, iclass 33, count 2 2006.201.07:04:52.98#ibcon#about to write, iclass 33, count 2 2006.201.07:04:52.98#ibcon#wrote, iclass 33, count 2 2006.201.07:04:52.98#ibcon#about to read 3, iclass 33, count 2 2006.201.07:04:53.00#abcon#<5=/05 2.3 4.0 23.19 891003.2\r\n> 2006.201.07:04:53.00#ibcon#read 3, iclass 33, count 2 2006.201.07:04:53.00#ibcon#about to read 4, iclass 33, count 2 2006.201.07:04:53.00#ibcon#read 4, iclass 33, count 2 2006.201.07:04:53.00#ibcon#about to read 5, iclass 33, count 2 2006.201.07:04:53.00#ibcon#read 5, iclass 33, count 2 2006.201.07:04:53.00#ibcon#about to read 6, iclass 33, count 2 2006.201.07:04:53.00#ibcon#read 6, iclass 33, count 2 2006.201.07:04:53.00#ibcon#end of sib2, iclass 33, count 2 2006.201.07:04:53.00#ibcon#*mode == 0, iclass 33, count 2 2006.201.07:04:53.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.07:04:53.00#ibcon#[25=AT04-07\r\n] 2006.201.07:04:53.00#ibcon#*before write, iclass 33, count 2 2006.201.07:04:53.00#ibcon#enter sib2, iclass 33, count 2 2006.201.07:04:53.00#ibcon#flushed, iclass 33, count 2 2006.201.07:04:53.00#ibcon#about to write, iclass 33, count 2 2006.201.07:04:53.00#ibcon#wrote, iclass 33, count 2 2006.201.07:04:53.00#ibcon#about to read 3, iclass 33, count 2 2006.201.07:04:53.02#abcon#{5=INTERFACE CLEAR} 2006.201.07:04:53.03#ibcon#read 3, iclass 33, count 2 2006.201.07:04:53.03#ibcon#about to read 4, iclass 33, count 2 2006.201.07:04:53.03#ibcon#read 4, iclass 33, count 2 2006.201.07:04:53.03#ibcon#about to read 5, iclass 33, count 2 2006.201.07:04:53.03#ibcon#read 5, iclass 33, count 2 2006.201.07:04:53.03#ibcon#about to read 6, iclass 33, count 2 2006.201.07:04:53.03#ibcon#read 6, iclass 33, count 2 2006.201.07:04:53.03#ibcon#end of sib2, iclass 33, count 2 2006.201.07:04:53.03#ibcon#*after write, iclass 33, count 2 2006.201.07:04:53.03#ibcon#*before return 0, iclass 33, count 2 2006.201.07:04:53.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:53.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:53.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.07:04:53.03#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:53.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:53.08#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:04:53.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:53.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:53.15#ibcon#enter wrdev, iclass 33, count 0 2006.201.07:04:53.15#ibcon#first serial, iclass 33, count 0 2006.201.07:04:53.15#ibcon#enter sib2, iclass 33, count 0 2006.201.07:04:53.15#ibcon#flushed, iclass 33, count 0 2006.201.07:04:53.15#ibcon#about to write, iclass 33, count 0 2006.201.07:04:53.15#ibcon#wrote, iclass 33, count 0 2006.201.07:04:53.15#ibcon#about to read 3, iclass 33, count 0 2006.201.07:04:53.17#ibcon#read 3, iclass 33, count 0 2006.201.07:04:53.17#ibcon#about to read 4, iclass 33, count 0 2006.201.07:04:53.17#ibcon#read 4, iclass 33, count 0 2006.201.07:04:53.17#ibcon#about to read 5, iclass 33, count 0 2006.201.07:04:53.17#ibcon#read 5, iclass 33, count 0 2006.201.07:04:53.17#ibcon#about to read 6, iclass 33, count 0 2006.201.07:04:53.17#ibcon#read 6, iclass 33, count 0 2006.201.07:04:53.17#ibcon#end of sib2, iclass 33, count 0 2006.201.07:04:53.17#ibcon#*mode == 0, iclass 33, count 0 2006.201.07:04:53.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.07:04:53.17#ibcon#[25=USB\r\n] 2006.201.07:04:53.17#ibcon#*before write, iclass 33, count 0 2006.201.07:04:53.17#ibcon#enter sib2, iclass 33, count 0 2006.201.07:04:53.17#ibcon#flushed, iclass 33, count 0 2006.201.07:04:53.17#ibcon#about to write, iclass 33, count 0 2006.201.07:04:53.17#ibcon#wrote, iclass 33, count 0 2006.201.07:04:53.17#ibcon#about to read 3, iclass 33, count 0 2006.201.07:04:53.20#ibcon#read 3, iclass 33, count 0 2006.201.07:04:53.20#ibcon#about to read 4, iclass 33, count 0 2006.201.07:04:53.20#ibcon#read 4, iclass 33, count 0 2006.201.07:04:53.20#ibcon#about to read 5, iclass 33, count 0 2006.201.07:04:53.20#ibcon#read 5, iclass 33, count 0 2006.201.07:04:53.20#ibcon#about to read 6, iclass 33, count 0 2006.201.07:04:53.20#ibcon#read 6, iclass 33, count 0 2006.201.07:04:53.20#ibcon#end of sib2, iclass 33, count 0 2006.201.07:04:53.20#ibcon#*after write, iclass 33, count 0 2006.201.07:04:53.20#ibcon#*before return 0, iclass 33, count 0 2006.201.07:04:53.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:53.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:53.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.07:04:53.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.07:04:53.20$vck44/valo=5,734.99 2006.201.07:04:53.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.07:04:53.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.07:04:53.20#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:53.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:53.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:53.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:53.20#ibcon#enter wrdev, iclass 39, count 0 2006.201.07:04:53.20#ibcon#first serial, iclass 39, count 0 2006.201.07:04:53.20#ibcon#enter sib2, iclass 39, count 0 2006.201.07:04:53.20#ibcon#flushed, iclass 39, count 0 2006.201.07:04:53.20#ibcon#about to write, iclass 39, count 0 2006.201.07:04:53.20#ibcon#wrote, iclass 39, count 0 2006.201.07:04:53.20#ibcon#about to read 3, iclass 39, count 0 2006.201.07:04:53.22#ibcon#read 3, iclass 39, count 0 2006.201.07:04:53.22#ibcon#about to read 4, iclass 39, count 0 2006.201.07:04:53.22#ibcon#read 4, iclass 39, count 0 2006.201.07:04:53.22#ibcon#about to read 5, iclass 39, count 0 2006.201.07:04:53.22#ibcon#read 5, iclass 39, count 0 2006.201.07:04:53.22#ibcon#about to read 6, iclass 39, count 0 2006.201.07:04:53.22#ibcon#read 6, iclass 39, count 0 2006.201.07:04:53.22#ibcon#end of sib2, iclass 39, count 0 2006.201.07:04:53.22#ibcon#*mode == 0, iclass 39, count 0 2006.201.07:04:53.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.07:04:53.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:04:53.22#ibcon#*before write, iclass 39, count 0 2006.201.07:04:53.22#ibcon#enter sib2, iclass 39, count 0 2006.201.07:04:53.22#ibcon#flushed, iclass 39, count 0 2006.201.07:04:53.22#ibcon#about to write, iclass 39, count 0 2006.201.07:04:53.22#ibcon#wrote, iclass 39, count 0 2006.201.07:04:53.22#ibcon#about to read 3, iclass 39, count 0 2006.201.07:04:53.26#ibcon#read 3, iclass 39, count 0 2006.201.07:04:53.26#ibcon#about to read 4, iclass 39, count 0 2006.201.07:04:53.26#ibcon#read 4, iclass 39, count 0 2006.201.07:04:53.26#ibcon#about to read 5, iclass 39, count 0 2006.201.07:04:53.26#ibcon#read 5, iclass 39, count 0 2006.201.07:04:53.26#ibcon#about to read 6, iclass 39, count 0 2006.201.07:04:53.26#ibcon#read 6, iclass 39, count 0 2006.201.07:04:53.26#ibcon#end of sib2, iclass 39, count 0 2006.201.07:04:53.26#ibcon#*after write, iclass 39, count 0 2006.201.07:04:53.26#ibcon#*before return 0, iclass 39, count 0 2006.201.07:04:53.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:53.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:53.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.07:04:53.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.07:04:53.26$vck44/va=5,4 2006.201.07:04:53.26#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.07:04:53.26#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.07:04:53.26#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:53.26#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:53.32#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:53.32#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:53.32#ibcon#enter wrdev, iclass 2, count 2 2006.201.07:04:53.32#ibcon#first serial, iclass 2, count 2 2006.201.07:04:53.32#ibcon#enter sib2, iclass 2, count 2 2006.201.07:04:53.32#ibcon#flushed, iclass 2, count 2 2006.201.07:04:53.32#ibcon#about to write, iclass 2, count 2 2006.201.07:04:53.32#ibcon#wrote, iclass 2, count 2 2006.201.07:04:53.32#ibcon#about to read 3, iclass 2, count 2 2006.201.07:04:53.34#ibcon#read 3, iclass 2, count 2 2006.201.07:04:53.34#ibcon#about to read 4, iclass 2, count 2 2006.201.07:04:53.34#ibcon#read 4, iclass 2, count 2 2006.201.07:04:53.34#ibcon#about to read 5, iclass 2, count 2 2006.201.07:04:53.34#ibcon#read 5, iclass 2, count 2 2006.201.07:04:53.34#ibcon#about to read 6, iclass 2, count 2 2006.201.07:04:53.34#ibcon#read 6, iclass 2, count 2 2006.201.07:04:53.34#ibcon#end of sib2, iclass 2, count 2 2006.201.07:04:53.34#ibcon#*mode == 0, iclass 2, count 2 2006.201.07:04:53.34#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.07:04:53.34#ibcon#[25=AT05-04\r\n] 2006.201.07:04:53.34#ibcon#*before write, iclass 2, count 2 2006.201.07:04:53.34#ibcon#enter sib2, iclass 2, count 2 2006.201.07:04:53.34#ibcon#flushed, iclass 2, count 2 2006.201.07:04:53.34#ibcon#about to write, iclass 2, count 2 2006.201.07:04:53.34#ibcon#wrote, iclass 2, count 2 2006.201.07:04:53.34#ibcon#about to read 3, iclass 2, count 2 2006.201.07:04:53.37#ibcon#read 3, iclass 2, count 2 2006.201.07:04:53.37#ibcon#about to read 4, iclass 2, count 2 2006.201.07:04:53.37#ibcon#read 4, iclass 2, count 2 2006.201.07:04:53.37#ibcon#about to read 5, iclass 2, count 2 2006.201.07:04:53.37#ibcon#read 5, iclass 2, count 2 2006.201.07:04:53.37#ibcon#about to read 6, iclass 2, count 2 2006.201.07:04:53.37#ibcon#read 6, iclass 2, count 2 2006.201.07:04:53.37#ibcon#end of sib2, iclass 2, count 2 2006.201.07:04:53.37#ibcon#*after write, iclass 2, count 2 2006.201.07:04:53.37#ibcon#*before return 0, iclass 2, count 2 2006.201.07:04:53.37#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:53.37#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:53.37#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.07:04:53.37#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:53.37#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:53.49#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:53.49#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:53.49#ibcon#enter wrdev, iclass 2, count 0 2006.201.07:04:53.49#ibcon#first serial, iclass 2, count 0 2006.201.07:04:53.49#ibcon#enter sib2, iclass 2, count 0 2006.201.07:04:53.49#ibcon#flushed, iclass 2, count 0 2006.201.07:04:53.49#ibcon#about to write, iclass 2, count 0 2006.201.07:04:53.49#ibcon#wrote, iclass 2, count 0 2006.201.07:04:53.49#ibcon#about to read 3, iclass 2, count 0 2006.201.07:04:53.51#ibcon#read 3, iclass 2, count 0 2006.201.07:04:53.51#ibcon#about to read 4, iclass 2, count 0 2006.201.07:04:53.51#ibcon#read 4, iclass 2, count 0 2006.201.07:04:53.51#ibcon#about to read 5, iclass 2, count 0 2006.201.07:04:53.51#ibcon#read 5, iclass 2, count 0 2006.201.07:04:53.51#ibcon#about to read 6, iclass 2, count 0 2006.201.07:04:53.51#ibcon#read 6, iclass 2, count 0 2006.201.07:04:53.51#ibcon#end of sib2, iclass 2, count 0 2006.201.07:04:53.51#ibcon#*mode == 0, iclass 2, count 0 2006.201.07:04:53.51#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.07:04:53.51#ibcon#[25=USB\r\n] 2006.201.07:04:53.51#ibcon#*before write, iclass 2, count 0 2006.201.07:04:53.51#ibcon#enter sib2, iclass 2, count 0 2006.201.07:04:53.51#ibcon#flushed, iclass 2, count 0 2006.201.07:04:53.51#ibcon#about to write, iclass 2, count 0 2006.201.07:04:53.51#ibcon#wrote, iclass 2, count 0 2006.201.07:04:53.51#ibcon#about to read 3, iclass 2, count 0 2006.201.07:04:53.54#ibcon#read 3, iclass 2, count 0 2006.201.07:04:53.54#ibcon#about to read 4, iclass 2, count 0 2006.201.07:04:53.54#ibcon#read 4, iclass 2, count 0 2006.201.07:04:53.54#ibcon#about to read 5, iclass 2, count 0 2006.201.07:04:53.54#ibcon#read 5, iclass 2, count 0 2006.201.07:04:53.54#ibcon#about to read 6, iclass 2, count 0 2006.201.07:04:53.54#ibcon#read 6, iclass 2, count 0 2006.201.07:04:53.54#ibcon#end of sib2, iclass 2, count 0 2006.201.07:04:53.54#ibcon#*after write, iclass 2, count 0 2006.201.07:04:53.54#ibcon#*before return 0, iclass 2, count 0 2006.201.07:04:53.54#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:53.54#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:53.54#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.07:04:53.54#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.07:04:53.54$vck44/valo=6,814.99 2006.201.07:04:53.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.07:04:53.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.07:04:53.54#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:53.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:53.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:53.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:53.54#ibcon#enter wrdev, iclass 5, count 0 2006.201.07:04:53.54#ibcon#first serial, iclass 5, count 0 2006.201.07:04:53.54#ibcon#enter sib2, iclass 5, count 0 2006.201.07:04:53.54#ibcon#flushed, iclass 5, count 0 2006.201.07:04:53.54#ibcon#about to write, iclass 5, count 0 2006.201.07:04:53.54#ibcon#wrote, iclass 5, count 0 2006.201.07:04:53.54#ibcon#about to read 3, iclass 5, count 0 2006.201.07:04:53.56#ibcon#read 3, iclass 5, count 0 2006.201.07:04:53.56#ibcon#about to read 4, iclass 5, count 0 2006.201.07:04:53.56#ibcon#read 4, iclass 5, count 0 2006.201.07:04:53.56#ibcon#about to read 5, iclass 5, count 0 2006.201.07:04:53.56#ibcon#read 5, iclass 5, count 0 2006.201.07:04:53.56#ibcon#about to read 6, iclass 5, count 0 2006.201.07:04:53.56#ibcon#read 6, iclass 5, count 0 2006.201.07:04:53.56#ibcon#end of sib2, iclass 5, count 0 2006.201.07:04:53.56#ibcon#*mode == 0, iclass 5, count 0 2006.201.07:04:53.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.07:04:53.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:04:53.56#ibcon#*before write, iclass 5, count 0 2006.201.07:04:53.56#ibcon#enter sib2, iclass 5, count 0 2006.201.07:04:53.56#ibcon#flushed, iclass 5, count 0 2006.201.07:04:53.56#ibcon#about to write, iclass 5, count 0 2006.201.07:04:53.56#ibcon#wrote, iclass 5, count 0 2006.201.07:04:53.56#ibcon#about to read 3, iclass 5, count 0 2006.201.07:04:53.61#ibcon#read 3, iclass 5, count 0 2006.201.07:04:53.61#ibcon#about to read 4, iclass 5, count 0 2006.201.07:04:53.61#ibcon#read 4, iclass 5, count 0 2006.201.07:04:53.61#ibcon#about to read 5, iclass 5, count 0 2006.201.07:04:53.61#ibcon#read 5, iclass 5, count 0 2006.201.07:04:53.61#ibcon#about to read 6, iclass 5, count 0 2006.201.07:04:53.61#ibcon#read 6, iclass 5, count 0 2006.201.07:04:53.61#ibcon#end of sib2, iclass 5, count 0 2006.201.07:04:53.61#ibcon#*after write, iclass 5, count 0 2006.201.07:04:53.61#ibcon#*before return 0, iclass 5, count 0 2006.201.07:04:53.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:53.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:53.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.07:04:53.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.07:04:53.61$vck44/va=6,5 2006.201.07:04:53.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.07:04:53.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.07:04:53.61#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:53.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:53.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:53.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:53.66#ibcon#enter wrdev, iclass 7, count 2 2006.201.07:04:53.66#ibcon#first serial, iclass 7, count 2 2006.201.07:04:53.66#ibcon#enter sib2, iclass 7, count 2 2006.201.07:04:53.66#ibcon#flushed, iclass 7, count 2 2006.201.07:04:53.66#ibcon#about to write, iclass 7, count 2 2006.201.07:04:53.66#ibcon#wrote, iclass 7, count 2 2006.201.07:04:53.66#ibcon#about to read 3, iclass 7, count 2 2006.201.07:04:53.68#ibcon#read 3, iclass 7, count 2 2006.201.07:04:53.68#ibcon#about to read 4, iclass 7, count 2 2006.201.07:04:53.68#ibcon#read 4, iclass 7, count 2 2006.201.07:04:53.68#ibcon#about to read 5, iclass 7, count 2 2006.201.07:04:53.68#ibcon#read 5, iclass 7, count 2 2006.201.07:04:53.68#ibcon#about to read 6, iclass 7, count 2 2006.201.07:04:53.68#ibcon#read 6, iclass 7, count 2 2006.201.07:04:53.68#ibcon#end of sib2, iclass 7, count 2 2006.201.07:04:53.68#ibcon#*mode == 0, iclass 7, count 2 2006.201.07:04:53.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.07:04:53.68#ibcon#[25=AT06-05\r\n] 2006.201.07:04:53.68#ibcon#*before write, iclass 7, count 2 2006.201.07:04:53.68#ibcon#enter sib2, iclass 7, count 2 2006.201.07:04:53.68#ibcon#flushed, iclass 7, count 2 2006.201.07:04:53.68#ibcon#about to write, iclass 7, count 2 2006.201.07:04:53.68#ibcon#wrote, iclass 7, count 2 2006.201.07:04:53.68#ibcon#about to read 3, iclass 7, count 2 2006.201.07:04:53.71#ibcon#read 3, iclass 7, count 2 2006.201.07:04:53.71#ibcon#about to read 4, iclass 7, count 2 2006.201.07:04:53.71#ibcon#read 4, iclass 7, count 2 2006.201.07:04:53.71#ibcon#about to read 5, iclass 7, count 2 2006.201.07:04:53.71#ibcon#read 5, iclass 7, count 2 2006.201.07:04:53.71#ibcon#about to read 6, iclass 7, count 2 2006.201.07:04:53.71#ibcon#read 6, iclass 7, count 2 2006.201.07:04:53.71#ibcon#end of sib2, iclass 7, count 2 2006.201.07:04:53.71#ibcon#*after write, iclass 7, count 2 2006.201.07:04:53.71#ibcon#*before return 0, iclass 7, count 2 2006.201.07:04:53.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:53.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:53.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.07:04:53.71#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:53.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:53.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:53.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:53.83#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:04:53.83#ibcon#first serial, iclass 7, count 0 2006.201.07:04:53.83#ibcon#enter sib2, iclass 7, count 0 2006.201.07:04:53.83#ibcon#flushed, iclass 7, count 0 2006.201.07:04:53.83#ibcon#about to write, iclass 7, count 0 2006.201.07:04:53.83#ibcon#wrote, iclass 7, count 0 2006.201.07:04:53.83#ibcon#about to read 3, iclass 7, count 0 2006.201.07:04:53.85#ibcon#read 3, iclass 7, count 0 2006.201.07:04:53.85#ibcon#about to read 4, iclass 7, count 0 2006.201.07:04:53.85#ibcon#read 4, iclass 7, count 0 2006.201.07:04:53.85#ibcon#about to read 5, iclass 7, count 0 2006.201.07:04:53.85#ibcon#read 5, iclass 7, count 0 2006.201.07:04:53.85#ibcon#about to read 6, iclass 7, count 0 2006.201.07:04:53.85#ibcon#read 6, iclass 7, count 0 2006.201.07:04:53.85#ibcon#end of sib2, iclass 7, count 0 2006.201.07:04:53.85#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:04:53.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:04:53.85#ibcon#[25=USB\r\n] 2006.201.07:04:53.85#ibcon#*before write, iclass 7, count 0 2006.201.07:04:53.85#ibcon#enter sib2, iclass 7, count 0 2006.201.07:04:53.85#ibcon#flushed, iclass 7, count 0 2006.201.07:04:53.85#ibcon#about to write, iclass 7, count 0 2006.201.07:04:53.85#ibcon#wrote, iclass 7, count 0 2006.201.07:04:53.85#ibcon#about to read 3, iclass 7, count 0 2006.201.07:04:53.88#ibcon#read 3, iclass 7, count 0 2006.201.07:04:53.88#ibcon#about to read 4, iclass 7, count 0 2006.201.07:04:53.88#ibcon#read 4, iclass 7, count 0 2006.201.07:04:53.88#ibcon#about to read 5, iclass 7, count 0 2006.201.07:04:53.88#ibcon#read 5, iclass 7, count 0 2006.201.07:04:53.88#ibcon#about to read 6, iclass 7, count 0 2006.201.07:04:53.88#ibcon#read 6, iclass 7, count 0 2006.201.07:04:53.88#ibcon#end of sib2, iclass 7, count 0 2006.201.07:04:53.88#ibcon#*after write, iclass 7, count 0 2006.201.07:04:53.88#ibcon#*before return 0, iclass 7, count 0 2006.201.07:04:53.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:53.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:53.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:04:53.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:04:53.88$vck44/valo=7,864.99 2006.201.07:04:53.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.07:04:53.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.07:04:53.88#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:53.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:53.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:53.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:53.88#ibcon#enter wrdev, iclass 11, count 0 2006.201.07:04:53.88#ibcon#first serial, iclass 11, count 0 2006.201.07:04:53.88#ibcon#enter sib2, iclass 11, count 0 2006.201.07:04:53.88#ibcon#flushed, iclass 11, count 0 2006.201.07:04:53.88#ibcon#about to write, iclass 11, count 0 2006.201.07:04:53.88#ibcon#wrote, iclass 11, count 0 2006.201.07:04:53.88#ibcon#about to read 3, iclass 11, count 0 2006.201.07:04:53.90#ibcon#read 3, iclass 11, count 0 2006.201.07:04:53.90#ibcon#about to read 4, iclass 11, count 0 2006.201.07:04:53.90#ibcon#read 4, iclass 11, count 0 2006.201.07:04:53.90#ibcon#about to read 5, iclass 11, count 0 2006.201.07:04:53.90#ibcon#read 5, iclass 11, count 0 2006.201.07:04:53.90#ibcon#about to read 6, iclass 11, count 0 2006.201.07:04:53.90#ibcon#read 6, iclass 11, count 0 2006.201.07:04:53.90#ibcon#end of sib2, iclass 11, count 0 2006.201.07:04:53.90#ibcon#*mode == 0, iclass 11, count 0 2006.201.07:04:53.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.07:04:53.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:04:53.90#ibcon#*before write, iclass 11, count 0 2006.201.07:04:53.90#ibcon#enter sib2, iclass 11, count 0 2006.201.07:04:53.90#ibcon#flushed, iclass 11, count 0 2006.201.07:04:53.90#ibcon#about to write, iclass 11, count 0 2006.201.07:04:53.90#ibcon#wrote, iclass 11, count 0 2006.201.07:04:53.90#ibcon#about to read 3, iclass 11, count 0 2006.201.07:04:53.94#ibcon#read 3, iclass 11, count 0 2006.201.07:04:53.94#ibcon#about to read 4, iclass 11, count 0 2006.201.07:04:53.94#ibcon#read 4, iclass 11, count 0 2006.201.07:04:53.94#ibcon#about to read 5, iclass 11, count 0 2006.201.07:04:53.94#ibcon#read 5, iclass 11, count 0 2006.201.07:04:53.94#ibcon#about to read 6, iclass 11, count 0 2006.201.07:04:53.94#ibcon#read 6, iclass 11, count 0 2006.201.07:04:53.94#ibcon#end of sib2, iclass 11, count 0 2006.201.07:04:53.94#ibcon#*after write, iclass 11, count 0 2006.201.07:04:53.94#ibcon#*before return 0, iclass 11, count 0 2006.201.07:04:53.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:53.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:53.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.07:04:53.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.07:04:53.94$vck44/va=7,5 2006.201.07:04:53.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.07:04:53.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.07:04:53.94#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:53.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:54.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:54.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:54.00#ibcon#enter wrdev, iclass 13, count 2 2006.201.07:04:54.00#ibcon#first serial, iclass 13, count 2 2006.201.07:04:54.00#ibcon#enter sib2, iclass 13, count 2 2006.201.07:04:54.00#ibcon#flushed, iclass 13, count 2 2006.201.07:04:54.00#ibcon#about to write, iclass 13, count 2 2006.201.07:04:54.00#ibcon#wrote, iclass 13, count 2 2006.201.07:04:54.00#ibcon#about to read 3, iclass 13, count 2 2006.201.07:04:54.02#ibcon#read 3, iclass 13, count 2 2006.201.07:04:54.02#ibcon#about to read 4, iclass 13, count 2 2006.201.07:04:54.02#ibcon#read 4, iclass 13, count 2 2006.201.07:04:54.02#ibcon#about to read 5, iclass 13, count 2 2006.201.07:04:54.02#ibcon#read 5, iclass 13, count 2 2006.201.07:04:54.02#ibcon#about to read 6, iclass 13, count 2 2006.201.07:04:54.02#ibcon#read 6, iclass 13, count 2 2006.201.07:04:54.02#ibcon#end of sib2, iclass 13, count 2 2006.201.07:04:54.02#ibcon#*mode == 0, iclass 13, count 2 2006.201.07:04:54.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.07:04:54.02#ibcon#[25=AT07-05\r\n] 2006.201.07:04:54.02#ibcon#*before write, iclass 13, count 2 2006.201.07:04:54.02#ibcon#enter sib2, iclass 13, count 2 2006.201.07:04:54.02#ibcon#flushed, iclass 13, count 2 2006.201.07:04:54.02#ibcon#about to write, iclass 13, count 2 2006.201.07:04:54.02#ibcon#wrote, iclass 13, count 2 2006.201.07:04:54.02#ibcon#about to read 3, iclass 13, count 2 2006.201.07:04:54.05#ibcon#read 3, iclass 13, count 2 2006.201.07:04:54.05#ibcon#about to read 4, iclass 13, count 2 2006.201.07:04:54.05#ibcon#read 4, iclass 13, count 2 2006.201.07:04:54.05#ibcon#about to read 5, iclass 13, count 2 2006.201.07:04:54.05#ibcon#read 5, iclass 13, count 2 2006.201.07:04:54.05#ibcon#about to read 6, iclass 13, count 2 2006.201.07:04:54.05#ibcon#read 6, iclass 13, count 2 2006.201.07:04:54.05#ibcon#end of sib2, iclass 13, count 2 2006.201.07:04:54.05#ibcon#*after write, iclass 13, count 2 2006.201.07:04:54.05#ibcon#*before return 0, iclass 13, count 2 2006.201.07:04:54.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:54.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:54.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.07:04:54.05#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:54.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:54.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:54.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:54.17#ibcon#enter wrdev, iclass 13, count 0 2006.201.07:04:54.17#ibcon#first serial, iclass 13, count 0 2006.201.07:04:54.17#ibcon#enter sib2, iclass 13, count 0 2006.201.07:04:54.17#ibcon#flushed, iclass 13, count 0 2006.201.07:04:54.17#ibcon#about to write, iclass 13, count 0 2006.201.07:04:54.17#ibcon#wrote, iclass 13, count 0 2006.201.07:04:54.17#ibcon#about to read 3, iclass 13, count 0 2006.201.07:04:54.19#ibcon#read 3, iclass 13, count 0 2006.201.07:04:54.19#ibcon#about to read 4, iclass 13, count 0 2006.201.07:04:54.19#ibcon#read 4, iclass 13, count 0 2006.201.07:04:54.19#ibcon#about to read 5, iclass 13, count 0 2006.201.07:04:54.19#ibcon#read 5, iclass 13, count 0 2006.201.07:04:54.19#ibcon#about to read 6, iclass 13, count 0 2006.201.07:04:54.19#ibcon#read 6, iclass 13, count 0 2006.201.07:04:54.19#ibcon#end of sib2, iclass 13, count 0 2006.201.07:04:54.19#ibcon#*mode == 0, iclass 13, count 0 2006.201.07:04:54.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.07:04:54.19#ibcon#[25=USB\r\n] 2006.201.07:04:54.19#ibcon#*before write, iclass 13, count 0 2006.201.07:04:54.19#ibcon#enter sib2, iclass 13, count 0 2006.201.07:04:54.19#ibcon#flushed, iclass 13, count 0 2006.201.07:04:54.19#ibcon#about to write, iclass 13, count 0 2006.201.07:04:54.19#ibcon#wrote, iclass 13, count 0 2006.201.07:04:54.19#ibcon#about to read 3, iclass 13, count 0 2006.201.07:04:54.22#ibcon#read 3, iclass 13, count 0 2006.201.07:04:54.22#ibcon#about to read 4, iclass 13, count 0 2006.201.07:04:54.22#ibcon#read 4, iclass 13, count 0 2006.201.07:04:54.22#ibcon#about to read 5, iclass 13, count 0 2006.201.07:04:54.22#ibcon#read 5, iclass 13, count 0 2006.201.07:04:54.22#ibcon#about to read 6, iclass 13, count 0 2006.201.07:04:54.22#ibcon#read 6, iclass 13, count 0 2006.201.07:04:54.22#ibcon#end of sib2, iclass 13, count 0 2006.201.07:04:54.22#ibcon#*after write, iclass 13, count 0 2006.201.07:04:54.22#ibcon#*before return 0, iclass 13, count 0 2006.201.07:04:54.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:54.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:54.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.07:04:54.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.07:04:54.22$vck44/valo=8,884.99 2006.201.07:04:54.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.07:04:54.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.07:04:54.22#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:54.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:54.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:54.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:54.22#ibcon#enter wrdev, iclass 15, count 0 2006.201.07:04:54.22#ibcon#first serial, iclass 15, count 0 2006.201.07:04:54.22#ibcon#enter sib2, iclass 15, count 0 2006.201.07:04:54.22#ibcon#flushed, iclass 15, count 0 2006.201.07:04:54.22#ibcon#about to write, iclass 15, count 0 2006.201.07:04:54.22#ibcon#wrote, iclass 15, count 0 2006.201.07:04:54.22#ibcon#about to read 3, iclass 15, count 0 2006.201.07:04:54.24#ibcon#read 3, iclass 15, count 0 2006.201.07:04:54.24#ibcon#about to read 4, iclass 15, count 0 2006.201.07:04:54.24#ibcon#read 4, iclass 15, count 0 2006.201.07:04:54.24#ibcon#about to read 5, iclass 15, count 0 2006.201.07:04:54.24#ibcon#read 5, iclass 15, count 0 2006.201.07:04:54.24#ibcon#about to read 6, iclass 15, count 0 2006.201.07:04:54.24#ibcon#read 6, iclass 15, count 0 2006.201.07:04:54.24#ibcon#end of sib2, iclass 15, count 0 2006.201.07:04:54.24#ibcon#*mode == 0, iclass 15, count 0 2006.201.07:04:54.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.07:04:54.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:04:54.24#ibcon#*before write, iclass 15, count 0 2006.201.07:04:54.24#ibcon#enter sib2, iclass 15, count 0 2006.201.07:04:54.24#ibcon#flushed, iclass 15, count 0 2006.201.07:04:54.24#ibcon#about to write, iclass 15, count 0 2006.201.07:04:54.24#ibcon#wrote, iclass 15, count 0 2006.201.07:04:54.24#ibcon#about to read 3, iclass 15, count 0 2006.201.07:04:54.28#ibcon#read 3, iclass 15, count 0 2006.201.07:04:54.28#ibcon#about to read 4, iclass 15, count 0 2006.201.07:04:54.28#ibcon#read 4, iclass 15, count 0 2006.201.07:04:54.28#ibcon#about to read 5, iclass 15, count 0 2006.201.07:04:54.28#ibcon#read 5, iclass 15, count 0 2006.201.07:04:54.28#ibcon#about to read 6, iclass 15, count 0 2006.201.07:04:54.28#ibcon#read 6, iclass 15, count 0 2006.201.07:04:54.28#ibcon#end of sib2, iclass 15, count 0 2006.201.07:04:54.28#ibcon#*after write, iclass 15, count 0 2006.201.07:04:54.28#ibcon#*before return 0, iclass 15, count 0 2006.201.07:04:54.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:54.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:54.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.07:04:54.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.07:04:54.28$vck44/va=8,4 2006.201.07:04:54.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.07:04:54.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.07:04:54.28#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:54.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:04:54.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:04:54.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:04:54.34#ibcon#enter wrdev, iclass 17, count 2 2006.201.07:04:54.34#ibcon#first serial, iclass 17, count 2 2006.201.07:04:54.34#ibcon#enter sib2, iclass 17, count 2 2006.201.07:04:54.34#ibcon#flushed, iclass 17, count 2 2006.201.07:04:54.34#ibcon#about to write, iclass 17, count 2 2006.201.07:04:54.34#ibcon#wrote, iclass 17, count 2 2006.201.07:04:54.34#ibcon#about to read 3, iclass 17, count 2 2006.201.07:04:54.36#ibcon#read 3, iclass 17, count 2 2006.201.07:04:54.36#ibcon#about to read 4, iclass 17, count 2 2006.201.07:04:54.36#ibcon#read 4, iclass 17, count 2 2006.201.07:04:54.36#ibcon#about to read 5, iclass 17, count 2 2006.201.07:04:54.36#ibcon#read 5, iclass 17, count 2 2006.201.07:04:54.36#ibcon#about to read 6, iclass 17, count 2 2006.201.07:04:54.36#ibcon#read 6, iclass 17, count 2 2006.201.07:04:54.36#ibcon#end of sib2, iclass 17, count 2 2006.201.07:04:54.36#ibcon#*mode == 0, iclass 17, count 2 2006.201.07:04:54.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.07:04:54.36#ibcon#[25=AT08-04\r\n] 2006.201.07:04:54.36#ibcon#*before write, iclass 17, count 2 2006.201.07:04:54.36#ibcon#enter sib2, iclass 17, count 2 2006.201.07:04:54.36#ibcon#flushed, iclass 17, count 2 2006.201.07:04:54.36#ibcon#about to write, iclass 17, count 2 2006.201.07:04:54.36#ibcon#wrote, iclass 17, count 2 2006.201.07:04:54.36#ibcon#about to read 3, iclass 17, count 2 2006.201.07:04:54.39#ibcon#read 3, iclass 17, count 2 2006.201.07:04:54.39#ibcon#about to read 4, iclass 17, count 2 2006.201.07:04:54.39#ibcon#read 4, iclass 17, count 2 2006.201.07:04:54.39#ibcon#about to read 5, iclass 17, count 2 2006.201.07:04:54.39#ibcon#read 5, iclass 17, count 2 2006.201.07:04:54.39#ibcon#about to read 6, iclass 17, count 2 2006.201.07:04:54.39#ibcon#read 6, iclass 17, count 2 2006.201.07:04:54.39#ibcon#end of sib2, iclass 17, count 2 2006.201.07:04:54.39#ibcon#*after write, iclass 17, count 2 2006.201.07:04:54.39#ibcon#*before return 0, iclass 17, count 2 2006.201.07:04:54.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:04:54.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:04:54.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.07:04:54.39#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:54.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:04:54.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:04:54.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:04:54.51#ibcon#enter wrdev, iclass 17, count 0 2006.201.07:04:54.51#ibcon#first serial, iclass 17, count 0 2006.201.07:04:54.51#ibcon#enter sib2, iclass 17, count 0 2006.201.07:04:54.51#ibcon#flushed, iclass 17, count 0 2006.201.07:04:54.51#ibcon#about to write, iclass 17, count 0 2006.201.07:04:54.51#ibcon#wrote, iclass 17, count 0 2006.201.07:04:54.51#ibcon#about to read 3, iclass 17, count 0 2006.201.07:04:54.53#ibcon#read 3, iclass 17, count 0 2006.201.07:04:54.53#ibcon#about to read 4, iclass 17, count 0 2006.201.07:04:54.53#ibcon#read 4, iclass 17, count 0 2006.201.07:04:54.53#ibcon#about to read 5, iclass 17, count 0 2006.201.07:04:54.53#ibcon#read 5, iclass 17, count 0 2006.201.07:04:54.53#ibcon#about to read 6, iclass 17, count 0 2006.201.07:04:54.53#ibcon#read 6, iclass 17, count 0 2006.201.07:04:54.53#ibcon#end of sib2, iclass 17, count 0 2006.201.07:04:54.53#ibcon#*mode == 0, iclass 17, count 0 2006.201.07:04:54.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.07:04:54.53#ibcon#[25=USB\r\n] 2006.201.07:04:54.53#ibcon#*before write, iclass 17, count 0 2006.201.07:04:54.53#ibcon#enter sib2, iclass 17, count 0 2006.201.07:04:54.53#ibcon#flushed, iclass 17, count 0 2006.201.07:04:54.53#ibcon#about to write, iclass 17, count 0 2006.201.07:04:54.53#ibcon#wrote, iclass 17, count 0 2006.201.07:04:54.53#ibcon#about to read 3, iclass 17, count 0 2006.201.07:04:54.56#ibcon#read 3, iclass 17, count 0 2006.201.07:04:54.56#ibcon#about to read 4, iclass 17, count 0 2006.201.07:04:54.56#ibcon#read 4, iclass 17, count 0 2006.201.07:04:54.56#ibcon#about to read 5, iclass 17, count 0 2006.201.07:04:54.56#ibcon#read 5, iclass 17, count 0 2006.201.07:04:54.56#ibcon#about to read 6, iclass 17, count 0 2006.201.07:04:54.56#ibcon#read 6, iclass 17, count 0 2006.201.07:04:54.56#ibcon#end of sib2, iclass 17, count 0 2006.201.07:04:54.56#ibcon#*after write, iclass 17, count 0 2006.201.07:04:54.56#ibcon#*before return 0, iclass 17, count 0 2006.201.07:04:54.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:04:54.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:04:54.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.07:04:54.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.07:04:54.56$vck44/vblo=1,629.99 2006.201.07:04:54.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.07:04:54.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.07:04:54.56#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:54.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:54.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:54.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:54.56#ibcon#enter wrdev, iclass 19, count 0 2006.201.07:04:54.56#ibcon#first serial, iclass 19, count 0 2006.201.07:04:54.56#ibcon#enter sib2, iclass 19, count 0 2006.201.07:04:54.56#ibcon#flushed, iclass 19, count 0 2006.201.07:04:54.56#ibcon#about to write, iclass 19, count 0 2006.201.07:04:54.56#ibcon#wrote, iclass 19, count 0 2006.201.07:04:54.56#ibcon#about to read 3, iclass 19, count 0 2006.201.07:04:54.58#ibcon#read 3, iclass 19, count 0 2006.201.07:04:54.58#ibcon#about to read 4, iclass 19, count 0 2006.201.07:04:54.58#ibcon#read 4, iclass 19, count 0 2006.201.07:04:54.58#ibcon#about to read 5, iclass 19, count 0 2006.201.07:04:54.58#ibcon#read 5, iclass 19, count 0 2006.201.07:04:54.58#ibcon#about to read 6, iclass 19, count 0 2006.201.07:04:54.58#ibcon#read 6, iclass 19, count 0 2006.201.07:04:54.58#ibcon#end of sib2, iclass 19, count 0 2006.201.07:04:54.58#ibcon#*mode == 0, iclass 19, count 0 2006.201.07:04:54.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.07:04:54.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:04:54.58#ibcon#*before write, iclass 19, count 0 2006.201.07:04:54.58#ibcon#enter sib2, iclass 19, count 0 2006.201.07:04:54.58#ibcon#flushed, iclass 19, count 0 2006.201.07:04:54.58#ibcon#about to write, iclass 19, count 0 2006.201.07:04:54.58#ibcon#wrote, iclass 19, count 0 2006.201.07:04:54.58#ibcon#about to read 3, iclass 19, count 0 2006.201.07:04:54.63#ibcon#read 3, iclass 19, count 0 2006.201.07:04:54.63#ibcon#about to read 4, iclass 19, count 0 2006.201.07:04:54.63#ibcon#read 4, iclass 19, count 0 2006.201.07:04:54.63#ibcon#about to read 5, iclass 19, count 0 2006.201.07:04:54.63#ibcon#read 5, iclass 19, count 0 2006.201.07:04:54.63#ibcon#about to read 6, iclass 19, count 0 2006.201.07:04:54.63#ibcon#read 6, iclass 19, count 0 2006.201.07:04:54.63#ibcon#end of sib2, iclass 19, count 0 2006.201.07:04:54.63#ibcon#*after write, iclass 19, count 0 2006.201.07:04:54.63#ibcon#*before return 0, iclass 19, count 0 2006.201.07:04:54.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:54.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:04:54.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.07:04:54.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.07:04:54.63$vck44/vb=1,4 2006.201.07:04:54.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.07:04:54.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.07:04:54.63#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:54.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:54.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:54.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:54.63#ibcon#enter wrdev, iclass 21, count 2 2006.201.07:04:54.63#ibcon#first serial, iclass 21, count 2 2006.201.07:04:54.63#ibcon#enter sib2, iclass 21, count 2 2006.201.07:04:54.63#ibcon#flushed, iclass 21, count 2 2006.201.07:04:54.63#ibcon#about to write, iclass 21, count 2 2006.201.07:04:54.63#ibcon#wrote, iclass 21, count 2 2006.201.07:04:54.63#ibcon#about to read 3, iclass 21, count 2 2006.201.07:04:54.65#ibcon#read 3, iclass 21, count 2 2006.201.07:04:54.65#ibcon#about to read 4, iclass 21, count 2 2006.201.07:04:54.65#ibcon#read 4, iclass 21, count 2 2006.201.07:04:54.65#ibcon#about to read 5, iclass 21, count 2 2006.201.07:04:54.65#ibcon#read 5, iclass 21, count 2 2006.201.07:04:54.65#ibcon#about to read 6, iclass 21, count 2 2006.201.07:04:54.65#ibcon#read 6, iclass 21, count 2 2006.201.07:04:54.65#ibcon#end of sib2, iclass 21, count 2 2006.201.07:04:54.65#ibcon#*mode == 0, iclass 21, count 2 2006.201.07:04:54.65#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.07:04:54.65#ibcon#[27=AT01-04\r\n] 2006.201.07:04:54.65#ibcon#*before write, iclass 21, count 2 2006.201.07:04:54.65#ibcon#enter sib2, iclass 21, count 2 2006.201.07:04:54.65#ibcon#flushed, iclass 21, count 2 2006.201.07:04:54.65#ibcon#about to write, iclass 21, count 2 2006.201.07:04:54.65#ibcon#wrote, iclass 21, count 2 2006.201.07:04:54.65#ibcon#about to read 3, iclass 21, count 2 2006.201.07:04:54.68#ibcon#read 3, iclass 21, count 2 2006.201.07:04:54.68#ibcon#about to read 4, iclass 21, count 2 2006.201.07:04:54.68#ibcon#read 4, iclass 21, count 2 2006.201.07:04:54.68#ibcon#about to read 5, iclass 21, count 2 2006.201.07:04:54.68#ibcon#read 5, iclass 21, count 2 2006.201.07:04:54.68#ibcon#about to read 6, iclass 21, count 2 2006.201.07:04:54.68#ibcon#read 6, iclass 21, count 2 2006.201.07:04:54.68#ibcon#end of sib2, iclass 21, count 2 2006.201.07:04:54.68#ibcon#*after write, iclass 21, count 2 2006.201.07:04:54.68#ibcon#*before return 0, iclass 21, count 2 2006.201.07:04:54.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:54.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:04:54.68#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.07:04:54.68#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:54.68#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:54.80#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:54.80#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:54.80#ibcon#enter wrdev, iclass 21, count 0 2006.201.07:04:54.80#ibcon#first serial, iclass 21, count 0 2006.201.07:04:54.80#ibcon#enter sib2, iclass 21, count 0 2006.201.07:04:54.80#ibcon#flushed, iclass 21, count 0 2006.201.07:04:54.80#ibcon#about to write, iclass 21, count 0 2006.201.07:04:54.80#ibcon#wrote, iclass 21, count 0 2006.201.07:04:54.80#ibcon#about to read 3, iclass 21, count 0 2006.201.07:04:54.82#ibcon#read 3, iclass 21, count 0 2006.201.07:04:54.82#ibcon#about to read 4, iclass 21, count 0 2006.201.07:04:54.82#ibcon#read 4, iclass 21, count 0 2006.201.07:04:54.82#ibcon#about to read 5, iclass 21, count 0 2006.201.07:04:54.82#ibcon#read 5, iclass 21, count 0 2006.201.07:04:54.82#ibcon#about to read 6, iclass 21, count 0 2006.201.07:04:54.82#ibcon#read 6, iclass 21, count 0 2006.201.07:04:54.82#ibcon#end of sib2, iclass 21, count 0 2006.201.07:04:54.82#ibcon#*mode == 0, iclass 21, count 0 2006.201.07:04:54.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.07:04:54.82#ibcon#[27=USB\r\n] 2006.201.07:04:54.82#ibcon#*before write, iclass 21, count 0 2006.201.07:04:54.82#ibcon#enter sib2, iclass 21, count 0 2006.201.07:04:54.82#ibcon#flushed, iclass 21, count 0 2006.201.07:04:54.82#ibcon#about to write, iclass 21, count 0 2006.201.07:04:54.82#ibcon#wrote, iclass 21, count 0 2006.201.07:04:54.82#ibcon#about to read 3, iclass 21, count 0 2006.201.07:04:54.85#ibcon#read 3, iclass 21, count 0 2006.201.07:04:54.85#ibcon#about to read 4, iclass 21, count 0 2006.201.07:04:54.85#ibcon#read 4, iclass 21, count 0 2006.201.07:04:54.85#ibcon#about to read 5, iclass 21, count 0 2006.201.07:04:54.85#ibcon#read 5, iclass 21, count 0 2006.201.07:04:54.85#ibcon#about to read 6, iclass 21, count 0 2006.201.07:04:54.85#ibcon#read 6, iclass 21, count 0 2006.201.07:04:54.85#ibcon#end of sib2, iclass 21, count 0 2006.201.07:04:54.85#ibcon#*after write, iclass 21, count 0 2006.201.07:04:54.85#ibcon#*before return 0, iclass 21, count 0 2006.201.07:04:54.85#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:54.85#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:04:54.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.07:04:54.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.07:04:54.85$vck44/vblo=2,634.99 2006.201.07:04:54.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.07:04:54.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.07:04:54.85#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:54.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:54.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:54.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:54.85#ibcon#enter wrdev, iclass 23, count 0 2006.201.07:04:54.85#ibcon#first serial, iclass 23, count 0 2006.201.07:04:54.85#ibcon#enter sib2, iclass 23, count 0 2006.201.07:04:54.85#ibcon#flushed, iclass 23, count 0 2006.201.07:04:54.85#ibcon#about to write, iclass 23, count 0 2006.201.07:04:54.85#ibcon#wrote, iclass 23, count 0 2006.201.07:04:54.85#ibcon#about to read 3, iclass 23, count 0 2006.201.07:04:54.87#ibcon#read 3, iclass 23, count 0 2006.201.07:04:54.87#ibcon#about to read 4, iclass 23, count 0 2006.201.07:04:54.87#ibcon#read 4, iclass 23, count 0 2006.201.07:04:54.87#ibcon#about to read 5, iclass 23, count 0 2006.201.07:04:54.87#ibcon#read 5, iclass 23, count 0 2006.201.07:04:54.87#ibcon#about to read 6, iclass 23, count 0 2006.201.07:04:54.87#ibcon#read 6, iclass 23, count 0 2006.201.07:04:54.87#ibcon#end of sib2, iclass 23, count 0 2006.201.07:04:54.87#ibcon#*mode == 0, iclass 23, count 0 2006.201.07:04:54.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.07:04:54.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:04:54.87#ibcon#*before write, iclass 23, count 0 2006.201.07:04:54.87#ibcon#enter sib2, iclass 23, count 0 2006.201.07:04:54.87#ibcon#flushed, iclass 23, count 0 2006.201.07:04:54.87#ibcon#about to write, iclass 23, count 0 2006.201.07:04:54.87#ibcon#wrote, iclass 23, count 0 2006.201.07:04:54.87#ibcon#about to read 3, iclass 23, count 0 2006.201.07:04:54.91#ibcon#read 3, iclass 23, count 0 2006.201.07:04:54.91#ibcon#about to read 4, iclass 23, count 0 2006.201.07:04:54.91#ibcon#read 4, iclass 23, count 0 2006.201.07:04:54.91#ibcon#about to read 5, iclass 23, count 0 2006.201.07:04:54.91#ibcon#read 5, iclass 23, count 0 2006.201.07:04:54.91#ibcon#about to read 6, iclass 23, count 0 2006.201.07:04:54.91#ibcon#read 6, iclass 23, count 0 2006.201.07:04:54.91#ibcon#end of sib2, iclass 23, count 0 2006.201.07:04:54.91#ibcon#*after write, iclass 23, count 0 2006.201.07:04:54.91#ibcon#*before return 0, iclass 23, count 0 2006.201.07:04:54.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:54.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:04:54.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.07:04:54.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.07:04:54.91$vck44/vb=2,5 2006.201.07:04:54.91#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.07:04:54.91#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.07:04:54.91#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:54.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:54.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:54.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:54.97#ibcon#enter wrdev, iclass 25, count 2 2006.201.07:04:54.97#ibcon#first serial, iclass 25, count 2 2006.201.07:04:54.97#ibcon#enter sib2, iclass 25, count 2 2006.201.07:04:54.97#ibcon#flushed, iclass 25, count 2 2006.201.07:04:54.97#ibcon#about to write, iclass 25, count 2 2006.201.07:04:54.97#ibcon#wrote, iclass 25, count 2 2006.201.07:04:54.97#ibcon#about to read 3, iclass 25, count 2 2006.201.07:04:54.99#ibcon#read 3, iclass 25, count 2 2006.201.07:04:54.99#ibcon#about to read 4, iclass 25, count 2 2006.201.07:04:54.99#ibcon#read 4, iclass 25, count 2 2006.201.07:04:54.99#ibcon#about to read 5, iclass 25, count 2 2006.201.07:04:54.99#ibcon#read 5, iclass 25, count 2 2006.201.07:04:54.99#ibcon#about to read 6, iclass 25, count 2 2006.201.07:04:54.99#ibcon#read 6, iclass 25, count 2 2006.201.07:04:54.99#ibcon#end of sib2, iclass 25, count 2 2006.201.07:04:54.99#ibcon#*mode == 0, iclass 25, count 2 2006.201.07:04:54.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.07:04:54.99#ibcon#[27=AT02-05\r\n] 2006.201.07:04:54.99#ibcon#*before write, iclass 25, count 2 2006.201.07:04:54.99#ibcon#enter sib2, iclass 25, count 2 2006.201.07:04:54.99#ibcon#flushed, iclass 25, count 2 2006.201.07:04:54.99#ibcon#about to write, iclass 25, count 2 2006.201.07:04:54.99#ibcon#wrote, iclass 25, count 2 2006.201.07:04:54.99#ibcon#about to read 3, iclass 25, count 2 2006.201.07:04:55.02#ibcon#read 3, iclass 25, count 2 2006.201.07:04:55.02#ibcon#about to read 4, iclass 25, count 2 2006.201.07:04:55.02#ibcon#read 4, iclass 25, count 2 2006.201.07:04:55.02#ibcon#about to read 5, iclass 25, count 2 2006.201.07:04:55.02#ibcon#read 5, iclass 25, count 2 2006.201.07:04:55.02#ibcon#about to read 6, iclass 25, count 2 2006.201.07:04:55.02#ibcon#read 6, iclass 25, count 2 2006.201.07:04:55.02#ibcon#end of sib2, iclass 25, count 2 2006.201.07:04:55.02#ibcon#*after write, iclass 25, count 2 2006.201.07:04:55.02#ibcon#*before return 0, iclass 25, count 2 2006.201.07:04:55.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:55.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:04:55.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.07:04:55.02#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:55.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:55.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:55.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:55.14#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:04:55.14#ibcon#first serial, iclass 25, count 0 2006.201.07:04:55.14#ibcon#enter sib2, iclass 25, count 0 2006.201.07:04:55.14#ibcon#flushed, iclass 25, count 0 2006.201.07:04:55.14#ibcon#about to write, iclass 25, count 0 2006.201.07:04:55.14#ibcon#wrote, iclass 25, count 0 2006.201.07:04:55.14#ibcon#about to read 3, iclass 25, count 0 2006.201.07:04:55.16#ibcon#read 3, iclass 25, count 0 2006.201.07:04:55.16#ibcon#about to read 4, iclass 25, count 0 2006.201.07:04:55.16#ibcon#read 4, iclass 25, count 0 2006.201.07:04:55.16#ibcon#about to read 5, iclass 25, count 0 2006.201.07:04:55.16#ibcon#read 5, iclass 25, count 0 2006.201.07:04:55.16#ibcon#about to read 6, iclass 25, count 0 2006.201.07:04:55.16#ibcon#read 6, iclass 25, count 0 2006.201.07:04:55.16#ibcon#end of sib2, iclass 25, count 0 2006.201.07:04:55.16#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:04:55.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:04:55.16#ibcon#[27=USB\r\n] 2006.201.07:04:55.16#ibcon#*before write, iclass 25, count 0 2006.201.07:04:55.16#ibcon#enter sib2, iclass 25, count 0 2006.201.07:04:55.16#ibcon#flushed, iclass 25, count 0 2006.201.07:04:55.16#ibcon#about to write, iclass 25, count 0 2006.201.07:04:55.16#ibcon#wrote, iclass 25, count 0 2006.201.07:04:55.16#ibcon#about to read 3, iclass 25, count 0 2006.201.07:04:55.19#ibcon#read 3, iclass 25, count 0 2006.201.07:04:55.19#ibcon#about to read 4, iclass 25, count 0 2006.201.07:04:55.19#ibcon#read 4, iclass 25, count 0 2006.201.07:04:55.19#ibcon#about to read 5, iclass 25, count 0 2006.201.07:04:55.19#ibcon#read 5, iclass 25, count 0 2006.201.07:04:55.19#ibcon#about to read 6, iclass 25, count 0 2006.201.07:04:55.19#ibcon#read 6, iclass 25, count 0 2006.201.07:04:55.19#ibcon#end of sib2, iclass 25, count 0 2006.201.07:04:55.19#ibcon#*after write, iclass 25, count 0 2006.201.07:04:55.19#ibcon#*before return 0, iclass 25, count 0 2006.201.07:04:55.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:55.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:04:55.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:04:55.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:04:55.19$vck44/vblo=3,649.99 2006.201.07:04:55.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.07:04:55.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.07:04:55.19#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:55.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:55.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:55.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:55.19#ibcon#enter wrdev, iclass 27, count 0 2006.201.07:04:55.19#ibcon#first serial, iclass 27, count 0 2006.201.07:04:55.19#ibcon#enter sib2, iclass 27, count 0 2006.201.07:04:55.19#ibcon#flushed, iclass 27, count 0 2006.201.07:04:55.19#ibcon#about to write, iclass 27, count 0 2006.201.07:04:55.19#ibcon#wrote, iclass 27, count 0 2006.201.07:04:55.19#ibcon#about to read 3, iclass 27, count 0 2006.201.07:04:55.21#ibcon#read 3, iclass 27, count 0 2006.201.07:04:55.21#ibcon#about to read 4, iclass 27, count 0 2006.201.07:04:55.21#ibcon#read 4, iclass 27, count 0 2006.201.07:04:55.21#ibcon#about to read 5, iclass 27, count 0 2006.201.07:04:55.21#ibcon#read 5, iclass 27, count 0 2006.201.07:04:55.21#ibcon#about to read 6, iclass 27, count 0 2006.201.07:04:55.21#ibcon#read 6, iclass 27, count 0 2006.201.07:04:55.21#ibcon#end of sib2, iclass 27, count 0 2006.201.07:04:55.21#ibcon#*mode == 0, iclass 27, count 0 2006.201.07:04:55.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.07:04:55.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:04:55.21#ibcon#*before write, iclass 27, count 0 2006.201.07:04:55.21#ibcon#enter sib2, iclass 27, count 0 2006.201.07:04:55.21#ibcon#flushed, iclass 27, count 0 2006.201.07:04:55.21#ibcon#about to write, iclass 27, count 0 2006.201.07:04:55.21#ibcon#wrote, iclass 27, count 0 2006.201.07:04:55.21#ibcon#about to read 3, iclass 27, count 0 2006.201.07:04:55.25#ibcon#read 3, iclass 27, count 0 2006.201.07:04:55.25#ibcon#about to read 4, iclass 27, count 0 2006.201.07:04:55.25#ibcon#read 4, iclass 27, count 0 2006.201.07:04:55.25#ibcon#about to read 5, iclass 27, count 0 2006.201.07:04:55.25#ibcon#read 5, iclass 27, count 0 2006.201.07:04:55.25#ibcon#about to read 6, iclass 27, count 0 2006.201.07:04:55.25#ibcon#read 6, iclass 27, count 0 2006.201.07:04:55.25#ibcon#end of sib2, iclass 27, count 0 2006.201.07:04:55.25#ibcon#*after write, iclass 27, count 0 2006.201.07:04:55.25#ibcon#*before return 0, iclass 27, count 0 2006.201.07:04:55.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:55.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:04:55.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.07:04:55.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.07:04:55.25$vck44/vb=3,4 2006.201.07:04:55.25#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.07:04:55.25#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.07:04:55.25#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:55.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:55.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:55.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:55.31#ibcon#enter wrdev, iclass 29, count 2 2006.201.07:04:55.31#ibcon#first serial, iclass 29, count 2 2006.201.07:04:55.31#ibcon#enter sib2, iclass 29, count 2 2006.201.07:04:55.31#ibcon#flushed, iclass 29, count 2 2006.201.07:04:55.31#ibcon#about to write, iclass 29, count 2 2006.201.07:04:55.31#ibcon#wrote, iclass 29, count 2 2006.201.07:04:55.31#ibcon#about to read 3, iclass 29, count 2 2006.201.07:04:55.33#ibcon#read 3, iclass 29, count 2 2006.201.07:04:55.33#ibcon#about to read 4, iclass 29, count 2 2006.201.07:04:55.33#ibcon#read 4, iclass 29, count 2 2006.201.07:04:55.33#ibcon#about to read 5, iclass 29, count 2 2006.201.07:04:55.33#ibcon#read 5, iclass 29, count 2 2006.201.07:04:55.33#ibcon#about to read 6, iclass 29, count 2 2006.201.07:04:55.33#ibcon#read 6, iclass 29, count 2 2006.201.07:04:55.33#ibcon#end of sib2, iclass 29, count 2 2006.201.07:04:55.33#ibcon#*mode == 0, iclass 29, count 2 2006.201.07:04:55.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.07:04:55.33#ibcon#[27=AT03-04\r\n] 2006.201.07:04:55.33#ibcon#*before write, iclass 29, count 2 2006.201.07:04:55.33#ibcon#enter sib2, iclass 29, count 2 2006.201.07:04:55.33#ibcon#flushed, iclass 29, count 2 2006.201.07:04:55.33#ibcon#about to write, iclass 29, count 2 2006.201.07:04:55.33#ibcon#wrote, iclass 29, count 2 2006.201.07:04:55.33#ibcon#about to read 3, iclass 29, count 2 2006.201.07:04:55.36#ibcon#read 3, iclass 29, count 2 2006.201.07:04:55.36#ibcon#about to read 4, iclass 29, count 2 2006.201.07:04:55.36#ibcon#read 4, iclass 29, count 2 2006.201.07:04:55.36#ibcon#about to read 5, iclass 29, count 2 2006.201.07:04:55.36#ibcon#read 5, iclass 29, count 2 2006.201.07:04:55.36#ibcon#about to read 6, iclass 29, count 2 2006.201.07:04:55.36#ibcon#read 6, iclass 29, count 2 2006.201.07:04:55.36#ibcon#end of sib2, iclass 29, count 2 2006.201.07:04:55.36#ibcon#*after write, iclass 29, count 2 2006.201.07:04:55.36#ibcon#*before return 0, iclass 29, count 2 2006.201.07:04:55.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:55.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:04:55.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.07:04:55.36#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:55.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:55.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:55.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:55.48#ibcon#enter wrdev, iclass 29, count 0 2006.201.07:04:55.48#ibcon#first serial, iclass 29, count 0 2006.201.07:04:55.48#ibcon#enter sib2, iclass 29, count 0 2006.201.07:04:55.48#ibcon#flushed, iclass 29, count 0 2006.201.07:04:55.48#ibcon#about to write, iclass 29, count 0 2006.201.07:04:55.48#ibcon#wrote, iclass 29, count 0 2006.201.07:04:55.48#ibcon#about to read 3, iclass 29, count 0 2006.201.07:04:55.50#ibcon#read 3, iclass 29, count 0 2006.201.07:04:55.50#ibcon#about to read 4, iclass 29, count 0 2006.201.07:04:55.50#ibcon#read 4, iclass 29, count 0 2006.201.07:04:55.50#ibcon#about to read 5, iclass 29, count 0 2006.201.07:04:55.50#ibcon#read 5, iclass 29, count 0 2006.201.07:04:55.50#ibcon#about to read 6, iclass 29, count 0 2006.201.07:04:55.50#ibcon#read 6, iclass 29, count 0 2006.201.07:04:55.50#ibcon#end of sib2, iclass 29, count 0 2006.201.07:04:55.50#ibcon#*mode == 0, iclass 29, count 0 2006.201.07:04:55.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.07:04:55.50#ibcon#[27=USB\r\n] 2006.201.07:04:55.50#ibcon#*before write, iclass 29, count 0 2006.201.07:04:55.50#ibcon#enter sib2, iclass 29, count 0 2006.201.07:04:55.50#ibcon#flushed, iclass 29, count 0 2006.201.07:04:55.50#ibcon#about to write, iclass 29, count 0 2006.201.07:04:55.50#ibcon#wrote, iclass 29, count 0 2006.201.07:04:55.50#ibcon#about to read 3, iclass 29, count 0 2006.201.07:04:55.53#ibcon#read 3, iclass 29, count 0 2006.201.07:04:55.53#ibcon#about to read 4, iclass 29, count 0 2006.201.07:04:55.53#ibcon#read 4, iclass 29, count 0 2006.201.07:04:55.53#ibcon#about to read 5, iclass 29, count 0 2006.201.07:04:55.53#ibcon#read 5, iclass 29, count 0 2006.201.07:04:55.53#ibcon#about to read 6, iclass 29, count 0 2006.201.07:04:55.53#ibcon#read 6, iclass 29, count 0 2006.201.07:04:55.53#ibcon#end of sib2, iclass 29, count 0 2006.201.07:04:55.53#ibcon#*after write, iclass 29, count 0 2006.201.07:04:55.53#ibcon#*before return 0, iclass 29, count 0 2006.201.07:04:55.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:55.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:04:55.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.07:04:55.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.07:04:55.53$vck44/vblo=4,679.99 2006.201.07:04:55.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.07:04:55.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.07:04:55.53#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:55.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:55.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:55.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:55.53#ibcon#enter wrdev, iclass 31, count 0 2006.201.07:04:55.53#ibcon#first serial, iclass 31, count 0 2006.201.07:04:55.53#ibcon#enter sib2, iclass 31, count 0 2006.201.07:04:55.53#ibcon#flushed, iclass 31, count 0 2006.201.07:04:55.53#ibcon#about to write, iclass 31, count 0 2006.201.07:04:55.53#ibcon#wrote, iclass 31, count 0 2006.201.07:04:55.53#ibcon#about to read 3, iclass 31, count 0 2006.201.07:04:55.55#ibcon#read 3, iclass 31, count 0 2006.201.07:04:55.55#ibcon#about to read 4, iclass 31, count 0 2006.201.07:04:55.55#ibcon#read 4, iclass 31, count 0 2006.201.07:04:55.55#ibcon#about to read 5, iclass 31, count 0 2006.201.07:04:55.55#ibcon#read 5, iclass 31, count 0 2006.201.07:04:55.55#ibcon#about to read 6, iclass 31, count 0 2006.201.07:04:55.55#ibcon#read 6, iclass 31, count 0 2006.201.07:04:55.55#ibcon#end of sib2, iclass 31, count 0 2006.201.07:04:55.55#ibcon#*mode == 0, iclass 31, count 0 2006.201.07:04:55.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.07:04:55.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:04:55.55#ibcon#*before write, iclass 31, count 0 2006.201.07:04:55.55#ibcon#enter sib2, iclass 31, count 0 2006.201.07:04:55.55#ibcon#flushed, iclass 31, count 0 2006.201.07:04:55.55#ibcon#about to write, iclass 31, count 0 2006.201.07:04:55.55#ibcon#wrote, iclass 31, count 0 2006.201.07:04:55.55#ibcon#about to read 3, iclass 31, count 0 2006.201.07:04:55.60#ibcon#read 3, iclass 31, count 0 2006.201.07:04:55.60#ibcon#about to read 4, iclass 31, count 0 2006.201.07:04:55.60#ibcon#read 4, iclass 31, count 0 2006.201.07:04:55.60#ibcon#about to read 5, iclass 31, count 0 2006.201.07:04:55.60#ibcon#read 5, iclass 31, count 0 2006.201.07:04:55.60#ibcon#about to read 6, iclass 31, count 0 2006.201.07:04:55.60#ibcon#read 6, iclass 31, count 0 2006.201.07:04:55.60#ibcon#end of sib2, iclass 31, count 0 2006.201.07:04:55.60#ibcon#*after write, iclass 31, count 0 2006.201.07:04:55.60#ibcon#*before return 0, iclass 31, count 0 2006.201.07:04:55.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:55.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:04:55.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.07:04:55.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.07:04:55.60$vck44/vb=4,5 2006.201.07:04:55.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.07:04:55.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.07:04:55.60#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:55.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:55.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:55.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:55.65#ibcon#enter wrdev, iclass 33, count 2 2006.201.07:04:55.65#ibcon#first serial, iclass 33, count 2 2006.201.07:04:55.65#ibcon#enter sib2, iclass 33, count 2 2006.201.07:04:55.65#ibcon#flushed, iclass 33, count 2 2006.201.07:04:55.65#ibcon#about to write, iclass 33, count 2 2006.201.07:04:55.65#ibcon#wrote, iclass 33, count 2 2006.201.07:04:55.65#ibcon#about to read 3, iclass 33, count 2 2006.201.07:04:55.67#ibcon#read 3, iclass 33, count 2 2006.201.07:04:55.67#ibcon#about to read 4, iclass 33, count 2 2006.201.07:04:55.67#ibcon#read 4, iclass 33, count 2 2006.201.07:04:55.67#ibcon#about to read 5, iclass 33, count 2 2006.201.07:04:55.67#ibcon#read 5, iclass 33, count 2 2006.201.07:04:55.67#ibcon#about to read 6, iclass 33, count 2 2006.201.07:04:55.67#ibcon#read 6, iclass 33, count 2 2006.201.07:04:55.67#ibcon#end of sib2, iclass 33, count 2 2006.201.07:04:55.67#ibcon#*mode == 0, iclass 33, count 2 2006.201.07:04:55.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.07:04:55.67#ibcon#[27=AT04-05\r\n] 2006.201.07:04:55.67#ibcon#*before write, iclass 33, count 2 2006.201.07:04:55.67#ibcon#enter sib2, iclass 33, count 2 2006.201.07:04:55.67#ibcon#flushed, iclass 33, count 2 2006.201.07:04:55.67#ibcon#about to write, iclass 33, count 2 2006.201.07:04:55.67#ibcon#wrote, iclass 33, count 2 2006.201.07:04:55.67#ibcon#about to read 3, iclass 33, count 2 2006.201.07:04:55.70#ibcon#read 3, iclass 33, count 2 2006.201.07:04:55.70#ibcon#about to read 4, iclass 33, count 2 2006.201.07:04:55.70#ibcon#read 4, iclass 33, count 2 2006.201.07:04:55.70#ibcon#about to read 5, iclass 33, count 2 2006.201.07:04:55.70#ibcon#read 5, iclass 33, count 2 2006.201.07:04:55.70#ibcon#about to read 6, iclass 33, count 2 2006.201.07:04:55.70#ibcon#read 6, iclass 33, count 2 2006.201.07:04:55.70#ibcon#end of sib2, iclass 33, count 2 2006.201.07:04:55.70#ibcon#*after write, iclass 33, count 2 2006.201.07:04:55.70#ibcon#*before return 0, iclass 33, count 2 2006.201.07:04:55.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:55.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:04:55.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.07:04:55.70#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:55.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:55.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:55.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:55.82#ibcon#enter wrdev, iclass 33, count 0 2006.201.07:04:55.82#ibcon#first serial, iclass 33, count 0 2006.201.07:04:55.82#ibcon#enter sib2, iclass 33, count 0 2006.201.07:04:55.82#ibcon#flushed, iclass 33, count 0 2006.201.07:04:55.82#ibcon#about to write, iclass 33, count 0 2006.201.07:04:55.82#ibcon#wrote, iclass 33, count 0 2006.201.07:04:55.82#ibcon#about to read 3, iclass 33, count 0 2006.201.07:04:55.84#ibcon#read 3, iclass 33, count 0 2006.201.07:04:55.84#ibcon#about to read 4, iclass 33, count 0 2006.201.07:04:55.84#ibcon#read 4, iclass 33, count 0 2006.201.07:04:55.84#ibcon#about to read 5, iclass 33, count 0 2006.201.07:04:55.84#ibcon#read 5, iclass 33, count 0 2006.201.07:04:55.84#ibcon#about to read 6, iclass 33, count 0 2006.201.07:04:55.84#ibcon#read 6, iclass 33, count 0 2006.201.07:04:55.84#ibcon#end of sib2, iclass 33, count 0 2006.201.07:04:55.84#ibcon#*mode == 0, iclass 33, count 0 2006.201.07:04:55.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.07:04:55.84#ibcon#[27=USB\r\n] 2006.201.07:04:55.84#ibcon#*before write, iclass 33, count 0 2006.201.07:04:55.84#ibcon#enter sib2, iclass 33, count 0 2006.201.07:04:55.84#ibcon#flushed, iclass 33, count 0 2006.201.07:04:55.84#ibcon#about to write, iclass 33, count 0 2006.201.07:04:55.84#ibcon#wrote, iclass 33, count 0 2006.201.07:04:55.84#ibcon#about to read 3, iclass 33, count 0 2006.201.07:04:55.87#ibcon#read 3, iclass 33, count 0 2006.201.07:04:55.87#ibcon#about to read 4, iclass 33, count 0 2006.201.07:04:55.87#ibcon#read 4, iclass 33, count 0 2006.201.07:04:55.87#ibcon#about to read 5, iclass 33, count 0 2006.201.07:04:55.87#ibcon#read 5, iclass 33, count 0 2006.201.07:04:55.87#ibcon#about to read 6, iclass 33, count 0 2006.201.07:04:55.87#ibcon#read 6, iclass 33, count 0 2006.201.07:04:55.87#ibcon#end of sib2, iclass 33, count 0 2006.201.07:04:55.87#ibcon#*after write, iclass 33, count 0 2006.201.07:04:55.87#ibcon#*before return 0, iclass 33, count 0 2006.201.07:04:55.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:55.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:04:55.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.07:04:55.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.07:04:55.87$vck44/vblo=5,709.99 2006.201.07:04:55.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.07:04:55.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.07:04:55.87#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:55.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:04:55.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:04:55.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:04:55.87#ibcon#enter wrdev, iclass 35, count 0 2006.201.07:04:55.87#ibcon#first serial, iclass 35, count 0 2006.201.07:04:55.87#ibcon#enter sib2, iclass 35, count 0 2006.201.07:04:55.87#ibcon#flushed, iclass 35, count 0 2006.201.07:04:55.87#ibcon#about to write, iclass 35, count 0 2006.201.07:04:55.87#ibcon#wrote, iclass 35, count 0 2006.201.07:04:55.87#ibcon#about to read 3, iclass 35, count 0 2006.201.07:04:55.89#ibcon#read 3, iclass 35, count 0 2006.201.07:04:55.89#ibcon#about to read 4, iclass 35, count 0 2006.201.07:04:55.89#ibcon#read 4, iclass 35, count 0 2006.201.07:04:55.89#ibcon#about to read 5, iclass 35, count 0 2006.201.07:04:55.89#ibcon#read 5, iclass 35, count 0 2006.201.07:04:55.89#ibcon#about to read 6, iclass 35, count 0 2006.201.07:04:55.89#ibcon#read 6, iclass 35, count 0 2006.201.07:04:55.89#ibcon#end of sib2, iclass 35, count 0 2006.201.07:04:55.89#ibcon#*mode == 0, iclass 35, count 0 2006.201.07:04:55.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.07:04:55.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:04:55.89#ibcon#*before write, iclass 35, count 0 2006.201.07:04:55.89#ibcon#enter sib2, iclass 35, count 0 2006.201.07:04:55.89#ibcon#flushed, iclass 35, count 0 2006.201.07:04:55.89#ibcon#about to write, iclass 35, count 0 2006.201.07:04:55.89#ibcon#wrote, iclass 35, count 0 2006.201.07:04:55.89#ibcon#about to read 3, iclass 35, count 0 2006.201.07:04:55.93#ibcon#read 3, iclass 35, count 0 2006.201.07:04:55.93#ibcon#about to read 4, iclass 35, count 0 2006.201.07:04:55.93#ibcon#read 4, iclass 35, count 0 2006.201.07:04:55.93#ibcon#about to read 5, iclass 35, count 0 2006.201.07:04:55.93#ibcon#read 5, iclass 35, count 0 2006.201.07:04:55.93#ibcon#about to read 6, iclass 35, count 0 2006.201.07:04:55.93#ibcon#read 6, iclass 35, count 0 2006.201.07:04:55.93#ibcon#end of sib2, iclass 35, count 0 2006.201.07:04:55.93#ibcon#*after write, iclass 35, count 0 2006.201.07:04:55.93#ibcon#*before return 0, iclass 35, count 0 2006.201.07:04:55.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:04:55.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:04:55.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.07:04:55.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.07:04:55.93$vck44/vb=5,4 2006.201.07:04:55.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.07:04:55.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.07:04:55.93#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:55.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:04:55.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:04:55.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:04:55.99#ibcon#enter wrdev, iclass 37, count 2 2006.201.07:04:55.99#ibcon#first serial, iclass 37, count 2 2006.201.07:04:55.99#ibcon#enter sib2, iclass 37, count 2 2006.201.07:04:55.99#ibcon#flushed, iclass 37, count 2 2006.201.07:04:55.99#ibcon#about to write, iclass 37, count 2 2006.201.07:04:55.99#ibcon#wrote, iclass 37, count 2 2006.201.07:04:55.99#ibcon#about to read 3, iclass 37, count 2 2006.201.07:04:56.01#ibcon#read 3, iclass 37, count 2 2006.201.07:04:56.01#ibcon#about to read 4, iclass 37, count 2 2006.201.07:04:56.01#ibcon#read 4, iclass 37, count 2 2006.201.07:04:56.01#ibcon#about to read 5, iclass 37, count 2 2006.201.07:04:56.01#ibcon#read 5, iclass 37, count 2 2006.201.07:04:56.01#ibcon#about to read 6, iclass 37, count 2 2006.201.07:04:56.01#ibcon#read 6, iclass 37, count 2 2006.201.07:04:56.01#ibcon#end of sib2, iclass 37, count 2 2006.201.07:04:56.01#ibcon#*mode == 0, iclass 37, count 2 2006.201.07:04:56.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.07:04:56.01#ibcon#[27=AT05-04\r\n] 2006.201.07:04:56.01#ibcon#*before write, iclass 37, count 2 2006.201.07:04:56.01#ibcon#enter sib2, iclass 37, count 2 2006.201.07:04:56.01#ibcon#flushed, iclass 37, count 2 2006.201.07:04:56.01#ibcon#about to write, iclass 37, count 2 2006.201.07:04:56.01#ibcon#wrote, iclass 37, count 2 2006.201.07:04:56.01#ibcon#about to read 3, iclass 37, count 2 2006.201.07:04:56.04#ibcon#read 3, iclass 37, count 2 2006.201.07:04:56.04#ibcon#about to read 4, iclass 37, count 2 2006.201.07:04:56.04#ibcon#read 4, iclass 37, count 2 2006.201.07:04:56.04#ibcon#about to read 5, iclass 37, count 2 2006.201.07:04:56.04#ibcon#read 5, iclass 37, count 2 2006.201.07:04:56.04#ibcon#about to read 6, iclass 37, count 2 2006.201.07:04:56.04#ibcon#read 6, iclass 37, count 2 2006.201.07:04:56.04#ibcon#end of sib2, iclass 37, count 2 2006.201.07:04:56.04#ibcon#*after write, iclass 37, count 2 2006.201.07:04:56.04#ibcon#*before return 0, iclass 37, count 2 2006.201.07:04:56.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:04:56.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:04:56.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.07:04:56.04#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:56.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:04:56.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:04:56.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:04:56.16#ibcon#enter wrdev, iclass 37, count 0 2006.201.07:04:56.16#ibcon#first serial, iclass 37, count 0 2006.201.07:04:56.16#ibcon#enter sib2, iclass 37, count 0 2006.201.07:04:56.16#ibcon#flushed, iclass 37, count 0 2006.201.07:04:56.16#ibcon#about to write, iclass 37, count 0 2006.201.07:04:56.16#ibcon#wrote, iclass 37, count 0 2006.201.07:04:56.16#ibcon#about to read 3, iclass 37, count 0 2006.201.07:04:56.18#ibcon#read 3, iclass 37, count 0 2006.201.07:04:56.18#ibcon#about to read 4, iclass 37, count 0 2006.201.07:04:56.18#ibcon#read 4, iclass 37, count 0 2006.201.07:04:56.18#ibcon#about to read 5, iclass 37, count 0 2006.201.07:04:56.18#ibcon#read 5, iclass 37, count 0 2006.201.07:04:56.18#ibcon#about to read 6, iclass 37, count 0 2006.201.07:04:56.18#ibcon#read 6, iclass 37, count 0 2006.201.07:04:56.18#ibcon#end of sib2, iclass 37, count 0 2006.201.07:04:56.18#ibcon#*mode == 0, iclass 37, count 0 2006.201.07:04:56.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.07:04:56.18#ibcon#[27=USB\r\n] 2006.201.07:04:56.18#ibcon#*before write, iclass 37, count 0 2006.201.07:04:56.18#ibcon#enter sib2, iclass 37, count 0 2006.201.07:04:56.18#ibcon#flushed, iclass 37, count 0 2006.201.07:04:56.18#ibcon#about to write, iclass 37, count 0 2006.201.07:04:56.18#ibcon#wrote, iclass 37, count 0 2006.201.07:04:56.18#ibcon#about to read 3, iclass 37, count 0 2006.201.07:04:56.21#ibcon#read 3, iclass 37, count 0 2006.201.07:04:56.21#ibcon#about to read 4, iclass 37, count 0 2006.201.07:04:56.21#ibcon#read 4, iclass 37, count 0 2006.201.07:04:56.21#ibcon#about to read 5, iclass 37, count 0 2006.201.07:04:56.21#ibcon#read 5, iclass 37, count 0 2006.201.07:04:56.21#ibcon#about to read 6, iclass 37, count 0 2006.201.07:04:56.21#ibcon#read 6, iclass 37, count 0 2006.201.07:04:56.21#ibcon#end of sib2, iclass 37, count 0 2006.201.07:04:56.21#ibcon#*after write, iclass 37, count 0 2006.201.07:04:56.21#ibcon#*before return 0, iclass 37, count 0 2006.201.07:04:56.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:04:56.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:04:56.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.07:04:56.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.07:04:56.21$vck44/vblo=6,719.99 2006.201.07:04:56.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.07:04:56.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.07:04:56.21#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:56.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:56.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:56.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:56.21#ibcon#enter wrdev, iclass 39, count 0 2006.201.07:04:56.21#ibcon#first serial, iclass 39, count 0 2006.201.07:04:56.21#ibcon#enter sib2, iclass 39, count 0 2006.201.07:04:56.21#ibcon#flushed, iclass 39, count 0 2006.201.07:04:56.21#ibcon#about to write, iclass 39, count 0 2006.201.07:04:56.21#ibcon#wrote, iclass 39, count 0 2006.201.07:04:56.21#ibcon#about to read 3, iclass 39, count 0 2006.201.07:04:56.23#ibcon#read 3, iclass 39, count 0 2006.201.07:04:56.23#ibcon#about to read 4, iclass 39, count 0 2006.201.07:04:56.23#ibcon#read 4, iclass 39, count 0 2006.201.07:04:56.23#ibcon#about to read 5, iclass 39, count 0 2006.201.07:04:56.23#ibcon#read 5, iclass 39, count 0 2006.201.07:04:56.23#ibcon#about to read 6, iclass 39, count 0 2006.201.07:04:56.23#ibcon#read 6, iclass 39, count 0 2006.201.07:04:56.23#ibcon#end of sib2, iclass 39, count 0 2006.201.07:04:56.23#ibcon#*mode == 0, iclass 39, count 0 2006.201.07:04:56.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.07:04:56.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:04:56.23#ibcon#*before write, iclass 39, count 0 2006.201.07:04:56.23#ibcon#enter sib2, iclass 39, count 0 2006.201.07:04:56.23#ibcon#flushed, iclass 39, count 0 2006.201.07:04:56.23#ibcon#about to write, iclass 39, count 0 2006.201.07:04:56.23#ibcon#wrote, iclass 39, count 0 2006.201.07:04:56.23#ibcon#about to read 3, iclass 39, count 0 2006.201.07:04:56.27#ibcon#read 3, iclass 39, count 0 2006.201.07:04:56.27#ibcon#about to read 4, iclass 39, count 0 2006.201.07:04:56.27#ibcon#read 4, iclass 39, count 0 2006.201.07:04:56.27#ibcon#about to read 5, iclass 39, count 0 2006.201.07:04:56.27#ibcon#read 5, iclass 39, count 0 2006.201.07:04:56.27#ibcon#about to read 6, iclass 39, count 0 2006.201.07:04:56.27#ibcon#read 6, iclass 39, count 0 2006.201.07:04:56.27#ibcon#end of sib2, iclass 39, count 0 2006.201.07:04:56.27#ibcon#*after write, iclass 39, count 0 2006.201.07:04:56.27#ibcon#*before return 0, iclass 39, count 0 2006.201.07:04:56.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:56.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:04:56.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.07:04:56.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.07:04:56.27$vck44/vb=6,4 2006.201.07:04:56.27#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.07:04:56.27#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.07:04:56.27#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:56.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:56.33#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:56.33#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:56.33#ibcon#enter wrdev, iclass 2, count 2 2006.201.07:04:56.33#ibcon#first serial, iclass 2, count 2 2006.201.07:04:56.33#ibcon#enter sib2, iclass 2, count 2 2006.201.07:04:56.33#ibcon#flushed, iclass 2, count 2 2006.201.07:04:56.33#ibcon#about to write, iclass 2, count 2 2006.201.07:04:56.33#ibcon#wrote, iclass 2, count 2 2006.201.07:04:56.33#ibcon#about to read 3, iclass 2, count 2 2006.201.07:04:56.35#ibcon#read 3, iclass 2, count 2 2006.201.07:04:56.35#ibcon#about to read 4, iclass 2, count 2 2006.201.07:04:56.35#ibcon#read 4, iclass 2, count 2 2006.201.07:04:56.35#ibcon#about to read 5, iclass 2, count 2 2006.201.07:04:56.35#ibcon#read 5, iclass 2, count 2 2006.201.07:04:56.35#ibcon#about to read 6, iclass 2, count 2 2006.201.07:04:56.35#ibcon#read 6, iclass 2, count 2 2006.201.07:04:56.35#ibcon#end of sib2, iclass 2, count 2 2006.201.07:04:56.35#ibcon#*mode == 0, iclass 2, count 2 2006.201.07:04:56.35#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.07:04:56.35#ibcon#[27=AT06-04\r\n] 2006.201.07:04:56.35#ibcon#*before write, iclass 2, count 2 2006.201.07:04:56.35#ibcon#enter sib2, iclass 2, count 2 2006.201.07:04:56.35#ibcon#flushed, iclass 2, count 2 2006.201.07:04:56.35#ibcon#about to write, iclass 2, count 2 2006.201.07:04:56.35#ibcon#wrote, iclass 2, count 2 2006.201.07:04:56.35#ibcon#about to read 3, iclass 2, count 2 2006.201.07:04:56.38#ibcon#read 3, iclass 2, count 2 2006.201.07:04:56.38#ibcon#about to read 4, iclass 2, count 2 2006.201.07:04:56.38#ibcon#read 4, iclass 2, count 2 2006.201.07:04:56.38#ibcon#about to read 5, iclass 2, count 2 2006.201.07:04:56.38#ibcon#read 5, iclass 2, count 2 2006.201.07:04:56.38#ibcon#about to read 6, iclass 2, count 2 2006.201.07:04:56.38#ibcon#read 6, iclass 2, count 2 2006.201.07:04:56.38#ibcon#end of sib2, iclass 2, count 2 2006.201.07:04:56.38#ibcon#*after write, iclass 2, count 2 2006.201.07:04:56.38#ibcon#*before return 0, iclass 2, count 2 2006.201.07:04:56.38#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:56.38#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:04:56.38#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.07:04:56.38#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:56.38#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:56.50#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:56.50#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:56.50#ibcon#enter wrdev, iclass 2, count 0 2006.201.07:04:56.50#ibcon#first serial, iclass 2, count 0 2006.201.07:04:56.50#ibcon#enter sib2, iclass 2, count 0 2006.201.07:04:56.50#ibcon#flushed, iclass 2, count 0 2006.201.07:04:56.50#ibcon#about to write, iclass 2, count 0 2006.201.07:04:56.50#ibcon#wrote, iclass 2, count 0 2006.201.07:04:56.50#ibcon#about to read 3, iclass 2, count 0 2006.201.07:04:56.52#ibcon#read 3, iclass 2, count 0 2006.201.07:04:56.52#ibcon#about to read 4, iclass 2, count 0 2006.201.07:04:56.52#ibcon#read 4, iclass 2, count 0 2006.201.07:04:56.52#ibcon#about to read 5, iclass 2, count 0 2006.201.07:04:56.52#ibcon#read 5, iclass 2, count 0 2006.201.07:04:56.52#ibcon#about to read 6, iclass 2, count 0 2006.201.07:04:56.52#ibcon#read 6, iclass 2, count 0 2006.201.07:04:56.52#ibcon#end of sib2, iclass 2, count 0 2006.201.07:04:56.52#ibcon#*mode == 0, iclass 2, count 0 2006.201.07:04:56.52#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.07:04:56.52#ibcon#[27=USB\r\n] 2006.201.07:04:56.52#ibcon#*before write, iclass 2, count 0 2006.201.07:04:56.52#ibcon#enter sib2, iclass 2, count 0 2006.201.07:04:56.52#ibcon#flushed, iclass 2, count 0 2006.201.07:04:56.52#ibcon#about to write, iclass 2, count 0 2006.201.07:04:56.52#ibcon#wrote, iclass 2, count 0 2006.201.07:04:56.52#ibcon#about to read 3, iclass 2, count 0 2006.201.07:04:56.55#ibcon#read 3, iclass 2, count 0 2006.201.07:04:56.55#ibcon#about to read 4, iclass 2, count 0 2006.201.07:04:56.55#ibcon#read 4, iclass 2, count 0 2006.201.07:04:56.55#ibcon#about to read 5, iclass 2, count 0 2006.201.07:04:56.55#ibcon#read 5, iclass 2, count 0 2006.201.07:04:56.55#ibcon#about to read 6, iclass 2, count 0 2006.201.07:04:56.55#ibcon#read 6, iclass 2, count 0 2006.201.07:04:56.55#ibcon#end of sib2, iclass 2, count 0 2006.201.07:04:56.55#ibcon#*after write, iclass 2, count 0 2006.201.07:04:56.55#ibcon#*before return 0, iclass 2, count 0 2006.201.07:04:56.55#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:56.55#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:04:56.55#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.07:04:56.55#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.07:04:56.55$vck44/vblo=7,734.99 2006.201.07:04:56.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.07:04:56.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.07:04:56.55#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:56.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:56.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:56.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:56.55#ibcon#enter wrdev, iclass 5, count 0 2006.201.07:04:56.55#ibcon#first serial, iclass 5, count 0 2006.201.07:04:56.55#ibcon#enter sib2, iclass 5, count 0 2006.201.07:04:56.55#ibcon#flushed, iclass 5, count 0 2006.201.07:04:56.55#ibcon#about to write, iclass 5, count 0 2006.201.07:04:56.55#ibcon#wrote, iclass 5, count 0 2006.201.07:04:56.55#ibcon#about to read 3, iclass 5, count 0 2006.201.07:04:56.57#ibcon#read 3, iclass 5, count 0 2006.201.07:04:56.57#ibcon#about to read 4, iclass 5, count 0 2006.201.07:04:56.57#ibcon#read 4, iclass 5, count 0 2006.201.07:04:56.57#ibcon#about to read 5, iclass 5, count 0 2006.201.07:04:56.57#ibcon#read 5, iclass 5, count 0 2006.201.07:04:56.57#ibcon#about to read 6, iclass 5, count 0 2006.201.07:04:56.57#ibcon#read 6, iclass 5, count 0 2006.201.07:04:56.57#ibcon#end of sib2, iclass 5, count 0 2006.201.07:04:56.57#ibcon#*mode == 0, iclass 5, count 0 2006.201.07:04:56.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.07:04:56.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:04:56.57#ibcon#*before write, iclass 5, count 0 2006.201.07:04:56.57#ibcon#enter sib2, iclass 5, count 0 2006.201.07:04:56.57#ibcon#flushed, iclass 5, count 0 2006.201.07:04:56.57#ibcon#about to write, iclass 5, count 0 2006.201.07:04:56.57#ibcon#wrote, iclass 5, count 0 2006.201.07:04:56.57#ibcon#about to read 3, iclass 5, count 0 2006.201.07:04:56.62#ibcon#read 3, iclass 5, count 0 2006.201.07:04:56.62#ibcon#about to read 4, iclass 5, count 0 2006.201.07:04:56.62#ibcon#read 4, iclass 5, count 0 2006.201.07:04:56.62#ibcon#about to read 5, iclass 5, count 0 2006.201.07:04:56.62#ibcon#read 5, iclass 5, count 0 2006.201.07:04:56.62#ibcon#about to read 6, iclass 5, count 0 2006.201.07:04:56.62#ibcon#read 6, iclass 5, count 0 2006.201.07:04:56.62#ibcon#end of sib2, iclass 5, count 0 2006.201.07:04:56.62#ibcon#*after write, iclass 5, count 0 2006.201.07:04:56.62#ibcon#*before return 0, iclass 5, count 0 2006.201.07:04:56.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:56.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:04:56.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.07:04:56.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.07:04:56.62$vck44/vb=7,4 2006.201.07:04:56.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.07:04:56.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.07:04:56.62#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:56.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:56.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:56.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:56.67#ibcon#enter wrdev, iclass 7, count 2 2006.201.07:04:56.67#ibcon#first serial, iclass 7, count 2 2006.201.07:04:56.67#ibcon#enter sib2, iclass 7, count 2 2006.201.07:04:56.67#ibcon#flushed, iclass 7, count 2 2006.201.07:04:56.67#ibcon#about to write, iclass 7, count 2 2006.201.07:04:56.67#ibcon#wrote, iclass 7, count 2 2006.201.07:04:56.67#ibcon#about to read 3, iclass 7, count 2 2006.201.07:04:56.69#ibcon#read 3, iclass 7, count 2 2006.201.07:04:56.69#ibcon#about to read 4, iclass 7, count 2 2006.201.07:04:56.69#ibcon#read 4, iclass 7, count 2 2006.201.07:04:56.69#ibcon#about to read 5, iclass 7, count 2 2006.201.07:04:56.69#ibcon#read 5, iclass 7, count 2 2006.201.07:04:56.69#ibcon#about to read 6, iclass 7, count 2 2006.201.07:04:56.69#ibcon#read 6, iclass 7, count 2 2006.201.07:04:56.69#ibcon#end of sib2, iclass 7, count 2 2006.201.07:04:56.69#ibcon#*mode == 0, iclass 7, count 2 2006.201.07:04:56.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.07:04:56.69#ibcon#[27=AT07-04\r\n] 2006.201.07:04:56.69#ibcon#*before write, iclass 7, count 2 2006.201.07:04:56.69#ibcon#enter sib2, iclass 7, count 2 2006.201.07:04:56.69#ibcon#flushed, iclass 7, count 2 2006.201.07:04:56.69#ibcon#about to write, iclass 7, count 2 2006.201.07:04:56.69#ibcon#wrote, iclass 7, count 2 2006.201.07:04:56.69#ibcon#about to read 3, iclass 7, count 2 2006.201.07:04:56.72#ibcon#read 3, iclass 7, count 2 2006.201.07:04:56.72#ibcon#about to read 4, iclass 7, count 2 2006.201.07:04:56.72#ibcon#read 4, iclass 7, count 2 2006.201.07:04:56.72#ibcon#about to read 5, iclass 7, count 2 2006.201.07:04:56.72#ibcon#read 5, iclass 7, count 2 2006.201.07:04:56.72#ibcon#about to read 6, iclass 7, count 2 2006.201.07:04:56.72#ibcon#read 6, iclass 7, count 2 2006.201.07:04:56.72#ibcon#end of sib2, iclass 7, count 2 2006.201.07:04:56.72#ibcon#*after write, iclass 7, count 2 2006.201.07:04:56.72#ibcon#*before return 0, iclass 7, count 2 2006.201.07:04:56.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:56.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:04:56.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.07:04:56.72#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:56.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:56.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:56.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:56.84#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:04:56.84#ibcon#first serial, iclass 7, count 0 2006.201.07:04:56.84#ibcon#enter sib2, iclass 7, count 0 2006.201.07:04:56.84#ibcon#flushed, iclass 7, count 0 2006.201.07:04:56.84#ibcon#about to write, iclass 7, count 0 2006.201.07:04:56.84#ibcon#wrote, iclass 7, count 0 2006.201.07:04:56.84#ibcon#about to read 3, iclass 7, count 0 2006.201.07:04:56.86#ibcon#read 3, iclass 7, count 0 2006.201.07:04:56.86#ibcon#about to read 4, iclass 7, count 0 2006.201.07:04:56.86#ibcon#read 4, iclass 7, count 0 2006.201.07:04:56.86#ibcon#about to read 5, iclass 7, count 0 2006.201.07:04:56.86#ibcon#read 5, iclass 7, count 0 2006.201.07:04:56.86#ibcon#about to read 6, iclass 7, count 0 2006.201.07:04:56.86#ibcon#read 6, iclass 7, count 0 2006.201.07:04:56.86#ibcon#end of sib2, iclass 7, count 0 2006.201.07:04:56.86#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:04:56.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:04:56.86#ibcon#[27=USB\r\n] 2006.201.07:04:56.86#ibcon#*before write, iclass 7, count 0 2006.201.07:04:56.86#ibcon#enter sib2, iclass 7, count 0 2006.201.07:04:56.86#ibcon#flushed, iclass 7, count 0 2006.201.07:04:56.86#ibcon#about to write, iclass 7, count 0 2006.201.07:04:56.86#ibcon#wrote, iclass 7, count 0 2006.201.07:04:56.86#ibcon#about to read 3, iclass 7, count 0 2006.201.07:04:56.89#ibcon#read 3, iclass 7, count 0 2006.201.07:04:56.89#ibcon#about to read 4, iclass 7, count 0 2006.201.07:04:56.89#ibcon#read 4, iclass 7, count 0 2006.201.07:04:56.89#ibcon#about to read 5, iclass 7, count 0 2006.201.07:04:56.89#ibcon#read 5, iclass 7, count 0 2006.201.07:04:56.89#ibcon#about to read 6, iclass 7, count 0 2006.201.07:04:56.89#ibcon#read 6, iclass 7, count 0 2006.201.07:04:56.89#ibcon#end of sib2, iclass 7, count 0 2006.201.07:04:56.89#ibcon#*after write, iclass 7, count 0 2006.201.07:04:56.89#ibcon#*before return 0, iclass 7, count 0 2006.201.07:04:56.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:56.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:04:56.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:04:56.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:04:56.89$vck44/vblo=8,744.99 2006.201.07:04:56.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.07:04:56.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.07:04:56.89#ibcon#ireg 17 cls_cnt 0 2006.201.07:04:56.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:56.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:56.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:56.89#ibcon#enter wrdev, iclass 11, count 0 2006.201.07:04:56.89#ibcon#first serial, iclass 11, count 0 2006.201.07:04:56.89#ibcon#enter sib2, iclass 11, count 0 2006.201.07:04:56.89#ibcon#flushed, iclass 11, count 0 2006.201.07:04:56.89#ibcon#about to write, iclass 11, count 0 2006.201.07:04:56.89#ibcon#wrote, iclass 11, count 0 2006.201.07:04:56.89#ibcon#about to read 3, iclass 11, count 0 2006.201.07:04:56.91#ibcon#read 3, iclass 11, count 0 2006.201.07:04:56.91#ibcon#about to read 4, iclass 11, count 0 2006.201.07:04:56.91#ibcon#read 4, iclass 11, count 0 2006.201.07:04:56.91#ibcon#about to read 5, iclass 11, count 0 2006.201.07:04:56.91#ibcon#read 5, iclass 11, count 0 2006.201.07:04:56.91#ibcon#about to read 6, iclass 11, count 0 2006.201.07:04:56.91#ibcon#read 6, iclass 11, count 0 2006.201.07:04:56.91#ibcon#end of sib2, iclass 11, count 0 2006.201.07:04:56.91#ibcon#*mode == 0, iclass 11, count 0 2006.201.07:04:56.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.07:04:56.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:04:56.91#ibcon#*before write, iclass 11, count 0 2006.201.07:04:56.91#ibcon#enter sib2, iclass 11, count 0 2006.201.07:04:56.91#ibcon#flushed, iclass 11, count 0 2006.201.07:04:56.91#ibcon#about to write, iclass 11, count 0 2006.201.07:04:56.91#ibcon#wrote, iclass 11, count 0 2006.201.07:04:56.91#ibcon#about to read 3, iclass 11, count 0 2006.201.07:04:56.95#ibcon#read 3, iclass 11, count 0 2006.201.07:04:56.95#ibcon#about to read 4, iclass 11, count 0 2006.201.07:04:56.95#ibcon#read 4, iclass 11, count 0 2006.201.07:04:56.95#ibcon#about to read 5, iclass 11, count 0 2006.201.07:04:56.95#ibcon#read 5, iclass 11, count 0 2006.201.07:04:56.95#ibcon#about to read 6, iclass 11, count 0 2006.201.07:04:56.95#ibcon#read 6, iclass 11, count 0 2006.201.07:04:56.95#ibcon#end of sib2, iclass 11, count 0 2006.201.07:04:56.95#ibcon#*after write, iclass 11, count 0 2006.201.07:04:56.95#ibcon#*before return 0, iclass 11, count 0 2006.201.07:04:56.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:56.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:04:56.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.07:04:56.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.07:04:56.95$vck44/vb=8,4 2006.201.07:04:56.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.07:04:56.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.07:04:56.95#ibcon#ireg 11 cls_cnt 2 2006.201.07:04:56.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:57.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:57.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:57.01#ibcon#enter wrdev, iclass 13, count 2 2006.201.07:04:57.01#ibcon#first serial, iclass 13, count 2 2006.201.07:04:57.01#ibcon#enter sib2, iclass 13, count 2 2006.201.07:04:57.01#ibcon#flushed, iclass 13, count 2 2006.201.07:04:57.01#ibcon#about to write, iclass 13, count 2 2006.201.07:04:57.01#ibcon#wrote, iclass 13, count 2 2006.201.07:04:57.01#ibcon#about to read 3, iclass 13, count 2 2006.201.07:04:57.03#ibcon#read 3, iclass 13, count 2 2006.201.07:04:57.03#ibcon#about to read 4, iclass 13, count 2 2006.201.07:04:57.03#ibcon#read 4, iclass 13, count 2 2006.201.07:04:57.03#ibcon#about to read 5, iclass 13, count 2 2006.201.07:04:57.03#ibcon#read 5, iclass 13, count 2 2006.201.07:04:57.03#ibcon#about to read 6, iclass 13, count 2 2006.201.07:04:57.03#ibcon#read 6, iclass 13, count 2 2006.201.07:04:57.03#ibcon#end of sib2, iclass 13, count 2 2006.201.07:04:57.03#ibcon#*mode == 0, iclass 13, count 2 2006.201.07:04:57.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.07:04:57.03#ibcon#[27=AT08-04\r\n] 2006.201.07:04:57.03#ibcon#*before write, iclass 13, count 2 2006.201.07:04:57.03#ibcon#enter sib2, iclass 13, count 2 2006.201.07:04:57.03#ibcon#flushed, iclass 13, count 2 2006.201.07:04:57.03#ibcon#about to write, iclass 13, count 2 2006.201.07:04:57.03#ibcon#wrote, iclass 13, count 2 2006.201.07:04:57.03#ibcon#about to read 3, iclass 13, count 2 2006.201.07:04:57.06#ibcon#read 3, iclass 13, count 2 2006.201.07:04:57.06#ibcon#about to read 4, iclass 13, count 2 2006.201.07:04:57.06#ibcon#read 4, iclass 13, count 2 2006.201.07:04:57.06#ibcon#about to read 5, iclass 13, count 2 2006.201.07:04:57.06#ibcon#read 5, iclass 13, count 2 2006.201.07:04:57.06#ibcon#about to read 6, iclass 13, count 2 2006.201.07:04:57.06#ibcon#read 6, iclass 13, count 2 2006.201.07:04:57.06#ibcon#end of sib2, iclass 13, count 2 2006.201.07:04:57.06#ibcon#*after write, iclass 13, count 2 2006.201.07:04:57.06#ibcon#*before return 0, iclass 13, count 2 2006.201.07:04:57.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:57.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:04:57.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.07:04:57.06#ibcon#ireg 7 cls_cnt 0 2006.201.07:04:57.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:57.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:57.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:57.18#ibcon#enter wrdev, iclass 13, count 0 2006.201.07:04:57.18#ibcon#first serial, iclass 13, count 0 2006.201.07:04:57.18#ibcon#enter sib2, iclass 13, count 0 2006.201.07:04:57.18#ibcon#flushed, iclass 13, count 0 2006.201.07:04:57.18#ibcon#about to write, iclass 13, count 0 2006.201.07:04:57.18#ibcon#wrote, iclass 13, count 0 2006.201.07:04:57.18#ibcon#about to read 3, iclass 13, count 0 2006.201.07:04:57.21#ibcon#read 3, iclass 13, count 0 2006.201.07:04:57.21#ibcon#about to read 4, iclass 13, count 0 2006.201.07:04:57.21#ibcon#read 4, iclass 13, count 0 2006.201.07:04:57.21#ibcon#about to read 5, iclass 13, count 0 2006.201.07:04:57.21#ibcon#read 5, iclass 13, count 0 2006.201.07:04:57.21#ibcon#about to read 6, iclass 13, count 0 2006.201.07:04:57.21#ibcon#read 6, iclass 13, count 0 2006.201.07:04:57.21#ibcon#end of sib2, iclass 13, count 0 2006.201.07:04:57.21#ibcon#*mode == 0, iclass 13, count 0 2006.201.07:04:57.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.07:04:57.21#ibcon#[27=USB\r\n] 2006.201.07:04:57.21#ibcon#*before write, iclass 13, count 0 2006.201.07:04:57.21#ibcon#enter sib2, iclass 13, count 0 2006.201.07:04:57.21#ibcon#flushed, iclass 13, count 0 2006.201.07:04:57.21#ibcon#about to write, iclass 13, count 0 2006.201.07:04:57.21#ibcon#wrote, iclass 13, count 0 2006.201.07:04:57.21#ibcon#about to read 3, iclass 13, count 0 2006.201.07:04:57.24#ibcon#read 3, iclass 13, count 0 2006.201.07:04:57.24#ibcon#about to read 4, iclass 13, count 0 2006.201.07:04:57.24#ibcon#read 4, iclass 13, count 0 2006.201.07:04:57.24#ibcon#about to read 5, iclass 13, count 0 2006.201.07:04:57.24#ibcon#read 5, iclass 13, count 0 2006.201.07:04:57.24#ibcon#about to read 6, iclass 13, count 0 2006.201.07:04:57.24#ibcon#read 6, iclass 13, count 0 2006.201.07:04:57.24#ibcon#end of sib2, iclass 13, count 0 2006.201.07:04:57.24#ibcon#*after write, iclass 13, count 0 2006.201.07:04:57.24#ibcon#*before return 0, iclass 13, count 0 2006.201.07:04:57.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:57.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:04:57.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.07:04:57.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.07:04:57.24$vck44/vabw=wide 2006.201.07:04:57.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.07:04:57.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.07:04:57.24#ibcon#ireg 8 cls_cnt 0 2006.201.07:04:57.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:57.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:57.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:57.24#ibcon#enter wrdev, iclass 15, count 0 2006.201.07:04:57.24#ibcon#first serial, iclass 15, count 0 2006.201.07:04:57.24#ibcon#enter sib2, iclass 15, count 0 2006.201.07:04:57.24#ibcon#flushed, iclass 15, count 0 2006.201.07:04:57.24#ibcon#about to write, iclass 15, count 0 2006.201.07:04:57.24#ibcon#wrote, iclass 15, count 0 2006.201.07:04:57.24#ibcon#about to read 3, iclass 15, count 0 2006.201.07:04:57.26#ibcon#read 3, iclass 15, count 0 2006.201.07:04:57.26#ibcon#about to read 4, iclass 15, count 0 2006.201.07:04:57.26#ibcon#read 4, iclass 15, count 0 2006.201.07:04:57.26#ibcon#about to read 5, iclass 15, count 0 2006.201.07:04:57.26#ibcon#read 5, iclass 15, count 0 2006.201.07:04:57.26#ibcon#about to read 6, iclass 15, count 0 2006.201.07:04:57.26#ibcon#read 6, iclass 15, count 0 2006.201.07:04:57.26#ibcon#end of sib2, iclass 15, count 0 2006.201.07:04:57.26#ibcon#*mode == 0, iclass 15, count 0 2006.201.07:04:57.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.07:04:57.26#ibcon#[25=BW32\r\n] 2006.201.07:04:57.26#ibcon#*before write, iclass 15, count 0 2006.201.07:04:57.26#ibcon#enter sib2, iclass 15, count 0 2006.201.07:04:57.26#ibcon#flushed, iclass 15, count 0 2006.201.07:04:57.26#ibcon#about to write, iclass 15, count 0 2006.201.07:04:57.26#ibcon#wrote, iclass 15, count 0 2006.201.07:04:57.26#ibcon#about to read 3, iclass 15, count 0 2006.201.07:04:57.29#ibcon#read 3, iclass 15, count 0 2006.201.07:04:57.29#ibcon#about to read 4, iclass 15, count 0 2006.201.07:04:57.29#ibcon#read 4, iclass 15, count 0 2006.201.07:04:57.29#ibcon#about to read 5, iclass 15, count 0 2006.201.07:04:57.29#ibcon#read 5, iclass 15, count 0 2006.201.07:04:57.29#ibcon#about to read 6, iclass 15, count 0 2006.201.07:04:57.29#ibcon#read 6, iclass 15, count 0 2006.201.07:04:57.29#ibcon#end of sib2, iclass 15, count 0 2006.201.07:04:57.29#ibcon#*after write, iclass 15, count 0 2006.201.07:04:57.29#ibcon#*before return 0, iclass 15, count 0 2006.201.07:04:57.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:57.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:04:57.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.07:04:57.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.07:04:57.29$vck44/vbbw=wide 2006.201.07:04:57.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.07:04:57.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.07:04:57.29#ibcon#ireg 8 cls_cnt 0 2006.201.07:04:57.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:04:57.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:04:57.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:04:57.36#ibcon#enter wrdev, iclass 17, count 0 2006.201.07:04:57.36#ibcon#first serial, iclass 17, count 0 2006.201.07:04:57.36#ibcon#enter sib2, iclass 17, count 0 2006.201.07:04:57.36#ibcon#flushed, iclass 17, count 0 2006.201.07:04:57.36#ibcon#about to write, iclass 17, count 0 2006.201.07:04:57.36#ibcon#wrote, iclass 17, count 0 2006.201.07:04:57.36#ibcon#about to read 3, iclass 17, count 0 2006.201.07:04:57.38#ibcon#read 3, iclass 17, count 0 2006.201.07:04:57.38#ibcon#about to read 4, iclass 17, count 0 2006.201.07:04:57.38#ibcon#read 4, iclass 17, count 0 2006.201.07:04:57.38#ibcon#about to read 5, iclass 17, count 0 2006.201.07:04:57.38#ibcon#read 5, iclass 17, count 0 2006.201.07:04:57.38#ibcon#about to read 6, iclass 17, count 0 2006.201.07:04:57.38#ibcon#read 6, iclass 17, count 0 2006.201.07:04:57.38#ibcon#end of sib2, iclass 17, count 0 2006.201.07:04:57.38#ibcon#*mode == 0, iclass 17, count 0 2006.201.07:04:57.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.07:04:57.38#ibcon#[27=BW32\r\n] 2006.201.07:04:57.38#ibcon#*before write, iclass 17, count 0 2006.201.07:04:57.38#ibcon#enter sib2, iclass 17, count 0 2006.201.07:04:57.38#ibcon#flushed, iclass 17, count 0 2006.201.07:04:57.38#ibcon#about to write, iclass 17, count 0 2006.201.07:04:57.38#ibcon#wrote, iclass 17, count 0 2006.201.07:04:57.38#ibcon#about to read 3, iclass 17, count 0 2006.201.07:04:57.41#ibcon#read 3, iclass 17, count 0 2006.201.07:04:57.41#ibcon#about to read 4, iclass 17, count 0 2006.201.07:04:57.41#ibcon#read 4, iclass 17, count 0 2006.201.07:04:57.41#ibcon#about to read 5, iclass 17, count 0 2006.201.07:04:57.41#ibcon#read 5, iclass 17, count 0 2006.201.07:04:57.41#ibcon#about to read 6, iclass 17, count 0 2006.201.07:04:57.41#ibcon#read 6, iclass 17, count 0 2006.201.07:04:57.41#ibcon#end of sib2, iclass 17, count 0 2006.201.07:04:57.41#ibcon#*after write, iclass 17, count 0 2006.201.07:04:57.41#ibcon#*before return 0, iclass 17, count 0 2006.201.07:04:57.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:04:57.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:04:57.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.07:04:57.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.07:04:57.41$setupk4/ifdk4 2006.201.07:04:57.41$ifdk4/lo= 2006.201.07:04:57.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:04:57.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:04:57.41$ifdk4/patch= 2006.201.07:04:57.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:04:57.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:04:57.41$setupk4/!*+20s 2006.201.07:05:03.17#abcon#<5=/05 2.3 4.0 23.19 891003.2\r\n> 2006.201.07:05:03.19#abcon#{5=INTERFACE CLEAR} 2006.201.07:05:03.25#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:05:11.88$setupk4/"tpicd 2006.201.07:05:11.88$setupk4/echo=off 2006.201.07:05:11.88$setupk4/xlog=off 2006.201.07:05:11.88:!2006.201.07:09:19 2006.201.07:05:26.14#trakl#Source acquired 2006.201.07:05:26.14#flagr#flagr/antenna,acquired 2006.201.07:09:19.00:preob 2006.201.07:09:19.14/onsource/TRACKING 2006.201.07:09:19.14:!2006.201.07:09:29 2006.201.07:09:29.00:"tape 2006.201.07:09:29.00:"st=record 2006.201.07:09:29.00:data_valid=on 2006.201.07:09:29.00:midob 2006.201.07:09:29.14/onsource/TRACKING 2006.201.07:09:29.14/wx/23.18,1003.2,88 2006.201.07:09:29.32/cable/+6.4672E-03 2006.201.07:09:30.41/va/01,08,usb,yes,38,40 2006.201.07:09:30.41/va/02,07,usb,yes,41,42 2006.201.07:09:30.41/va/03,08,usb,yes,37,38 2006.201.07:09:30.41/va/04,07,usb,yes,42,44 2006.201.07:09:30.41/va/05,04,usb,yes,37,38 2006.201.07:09:30.41/va/06,05,usb,yes,37,37 2006.201.07:09:30.41/va/07,05,usb,yes,36,38 2006.201.07:09:30.41/va/08,04,usb,yes,36,43 2006.201.07:09:30.64/valo/01,524.99,yes,locked 2006.201.07:09:30.64/valo/02,534.99,yes,locked 2006.201.07:09:30.64/valo/03,564.99,yes,locked 2006.201.07:09:30.64/valo/04,624.99,yes,locked 2006.201.07:09:30.64/valo/05,734.99,yes,locked 2006.201.07:09:30.64/valo/06,814.99,yes,locked 2006.201.07:09:30.64/valo/07,864.99,yes,locked 2006.201.07:09:30.64/valo/08,884.99,yes,locked 2006.201.07:09:31.73/vb/01,04,usb,yes,32,31 2006.201.07:09:31.73/vb/02,05,usb,yes,30,32 2006.201.07:09:31.73/vb/03,04,usb,yes,31,35 2006.201.07:09:31.73/vb/04,05,usb,yes,31,30 2006.201.07:09:31.73/vb/05,04,usb,yes,28,31 2006.201.07:09:31.73/vb/06,04,usb,yes,33,29 2006.201.07:09:31.73/vb/07,04,usb,yes,33,32 2006.201.07:09:31.73/vb/08,04,usb,yes,30,33 2006.201.07:09:31.96/vblo/01,629.99,yes,locked 2006.201.07:09:31.96/vblo/02,634.99,yes,locked 2006.201.07:09:31.96/vblo/03,649.99,yes,locked 2006.201.07:09:31.96/vblo/04,679.99,yes,locked 2006.201.07:09:31.96/vblo/05,709.99,yes,locked 2006.201.07:09:31.96/vblo/06,719.99,yes,locked 2006.201.07:09:31.96/vblo/07,734.99,yes,locked 2006.201.07:09:31.96/vblo/08,744.99,yes,locked 2006.201.07:09:32.11/vabw/8 2006.201.07:09:32.26/vbbw/8 2006.201.07:09:32.35/xfe/off,on,15.2 2006.201.07:09:32.73/ifatt/23,28,28,28 2006.201.07:09:33.05/fmout-gps/S +4.53E-07 2006.201.07:09:33.12:!2006.201.07:10:09 2006.201.07:10:09.00:data_valid=off 2006.201.07:10:09.00:"et 2006.201.07:10:09.00:!+3s 2006.201.07:10:12.02:"tape 2006.201.07:10:12.02:postob 2006.201.07:10:12.19/cable/+6.4677E-03 2006.201.07:10:12.19/wx/23.18,1003.2,88 2006.201.07:10:12.26/fmout-gps/S +4.54E-07 2006.201.07:10:12.26:scan_name=201-0717,jd0607,40 2006.201.07:10:12.26:source=3c345,164258.81,394837.0,2000.0,ccw 2006.201.07:10:14.13#flagr#flagr/antenna,new-source 2006.201.07:10:14.13:checkk5 2006.201.07:10:14.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:10:14.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:10:15.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:10:15.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:10:16.00/chk_obsdata//k5ts1/T2010709??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:10:16.37/chk_obsdata//k5ts2/T2010709??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:10:16.73/chk_obsdata//k5ts3/T2010709??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:10:17.10/chk_obsdata//k5ts4/T2010709??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:10:17.79/k5log//k5ts1_log_newline 2006.201.07:10:18.48/k5log//k5ts2_log_newline 2006.201.07:10:19.17/k5log//k5ts3_log_newline 2006.201.07:10:19.87/k5log//k5ts4_log_newline 2006.201.07:10:19.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:10:19.89:setupk4=1 2006.201.07:10:19.89$setupk4/echo=on 2006.201.07:10:19.89$setupk4/pcalon 2006.201.07:10:19.89$pcalon/"no phase cal control is implemented here 2006.201.07:10:19.89$setupk4/"tpicd=stop 2006.201.07:10:19.89$setupk4/"rec=synch_on 2006.201.07:10:19.89$setupk4/"rec_mode=128 2006.201.07:10:19.89$setupk4/!* 2006.201.07:10:19.90$setupk4/recpk4 2006.201.07:10:19.90$recpk4/recpatch= 2006.201.07:10:19.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:10:19.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:10:19.90$setupk4/vck44 2006.201.07:10:19.90$vck44/valo=1,524.99 2006.201.07:10:19.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.07:10:19.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.07:10:19.90#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:19.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:19.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:19.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:19.90#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:10:19.90#ibcon#first serial, iclass 4, count 0 2006.201.07:10:19.90#ibcon#enter sib2, iclass 4, count 0 2006.201.07:10:19.90#ibcon#flushed, iclass 4, count 0 2006.201.07:10:19.90#ibcon#about to write, iclass 4, count 0 2006.201.07:10:19.90#ibcon#wrote, iclass 4, count 0 2006.201.07:10:19.90#ibcon#about to read 3, iclass 4, count 0 2006.201.07:10:19.94#ibcon#read 3, iclass 4, count 0 2006.201.07:10:19.94#ibcon#about to read 4, iclass 4, count 0 2006.201.07:10:19.94#ibcon#read 4, iclass 4, count 0 2006.201.07:10:19.94#ibcon#about to read 5, iclass 4, count 0 2006.201.07:10:19.94#ibcon#read 5, iclass 4, count 0 2006.201.07:10:19.94#ibcon#about to read 6, iclass 4, count 0 2006.201.07:10:19.94#ibcon#read 6, iclass 4, count 0 2006.201.07:10:19.94#ibcon#end of sib2, iclass 4, count 0 2006.201.07:10:19.94#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:10:19.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:10:19.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:10:19.94#ibcon#*before write, iclass 4, count 0 2006.201.07:10:19.94#ibcon#enter sib2, iclass 4, count 0 2006.201.07:10:19.94#ibcon#flushed, iclass 4, count 0 2006.201.07:10:19.94#ibcon#about to write, iclass 4, count 0 2006.201.07:10:19.94#ibcon#wrote, iclass 4, count 0 2006.201.07:10:19.94#ibcon#about to read 3, iclass 4, count 0 2006.201.07:10:19.99#ibcon#read 3, iclass 4, count 0 2006.201.07:10:19.99#ibcon#about to read 4, iclass 4, count 0 2006.201.07:10:19.99#ibcon#read 4, iclass 4, count 0 2006.201.07:10:19.99#ibcon#about to read 5, iclass 4, count 0 2006.201.07:10:19.99#ibcon#read 5, iclass 4, count 0 2006.201.07:10:19.99#ibcon#about to read 6, iclass 4, count 0 2006.201.07:10:19.99#ibcon#read 6, iclass 4, count 0 2006.201.07:10:19.99#ibcon#end of sib2, iclass 4, count 0 2006.201.07:10:19.99#ibcon#*after write, iclass 4, count 0 2006.201.07:10:19.99#ibcon#*before return 0, iclass 4, count 0 2006.201.07:10:19.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:19.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:19.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:10:19.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:10:19.99$vck44/va=1,8 2006.201.07:10:19.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.07:10:19.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.07:10:19.99#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:19.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:19.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:19.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:19.99#ibcon#enter wrdev, iclass 6, count 2 2006.201.07:10:19.99#ibcon#first serial, iclass 6, count 2 2006.201.07:10:19.99#ibcon#enter sib2, iclass 6, count 2 2006.201.07:10:19.99#ibcon#flushed, iclass 6, count 2 2006.201.07:10:19.99#ibcon#about to write, iclass 6, count 2 2006.201.07:10:19.99#ibcon#wrote, iclass 6, count 2 2006.201.07:10:19.99#ibcon#about to read 3, iclass 6, count 2 2006.201.07:10:20.01#ibcon#read 3, iclass 6, count 2 2006.201.07:10:20.01#ibcon#about to read 4, iclass 6, count 2 2006.201.07:10:20.01#ibcon#read 4, iclass 6, count 2 2006.201.07:10:20.01#ibcon#about to read 5, iclass 6, count 2 2006.201.07:10:20.01#ibcon#read 5, iclass 6, count 2 2006.201.07:10:20.01#ibcon#about to read 6, iclass 6, count 2 2006.201.07:10:20.01#ibcon#read 6, iclass 6, count 2 2006.201.07:10:20.01#ibcon#end of sib2, iclass 6, count 2 2006.201.07:10:20.01#ibcon#*mode == 0, iclass 6, count 2 2006.201.07:10:20.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.07:10:20.01#ibcon#[25=AT01-08\r\n] 2006.201.07:10:20.01#ibcon#*before write, iclass 6, count 2 2006.201.07:10:20.01#ibcon#enter sib2, iclass 6, count 2 2006.201.07:10:20.01#ibcon#flushed, iclass 6, count 2 2006.201.07:10:20.01#ibcon#about to write, iclass 6, count 2 2006.201.07:10:20.01#ibcon#wrote, iclass 6, count 2 2006.201.07:10:20.01#ibcon#about to read 3, iclass 6, count 2 2006.201.07:10:20.05#ibcon#read 3, iclass 6, count 2 2006.201.07:10:20.05#ibcon#about to read 4, iclass 6, count 2 2006.201.07:10:20.05#ibcon#read 4, iclass 6, count 2 2006.201.07:10:20.05#ibcon#about to read 5, iclass 6, count 2 2006.201.07:10:20.05#ibcon#read 5, iclass 6, count 2 2006.201.07:10:20.05#ibcon#about to read 6, iclass 6, count 2 2006.201.07:10:20.05#ibcon#read 6, iclass 6, count 2 2006.201.07:10:20.05#ibcon#end of sib2, iclass 6, count 2 2006.201.07:10:20.05#ibcon#*after write, iclass 6, count 2 2006.201.07:10:20.05#ibcon#*before return 0, iclass 6, count 2 2006.201.07:10:20.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:20.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:20.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.07:10:20.05#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:20.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:20.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:20.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:20.17#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:10:20.17#ibcon#first serial, iclass 6, count 0 2006.201.07:10:20.17#ibcon#enter sib2, iclass 6, count 0 2006.201.07:10:20.17#ibcon#flushed, iclass 6, count 0 2006.201.07:10:20.17#ibcon#about to write, iclass 6, count 0 2006.201.07:10:20.17#ibcon#wrote, iclass 6, count 0 2006.201.07:10:20.17#ibcon#about to read 3, iclass 6, count 0 2006.201.07:10:20.19#ibcon#read 3, iclass 6, count 0 2006.201.07:10:20.19#ibcon#about to read 4, iclass 6, count 0 2006.201.07:10:20.19#ibcon#read 4, iclass 6, count 0 2006.201.07:10:20.19#ibcon#about to read 5, iclass 6, count 0 2006.201.07:10:20.19#ibcon#read 5, iclass 6, count 0 2006.201.07:10:20.19#ibcon#about to read 6, iclass 6, count 0 2006.201.07:10:20.20#ibcon#read 6, iclass 6, count 0 2006.201.07:10:20.20#ibcon#end of sib2, iclass 6, count 0 2006.201.07:10:20.20#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:10:20.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:10:20.20#ibcon#[25=USB\r\n] 2006.201.07:10:20.20#ibcon#*before write, iclass 6, count 0 2006.201.07:10:20.20#ibcon#enter sib2, iclass 6, count 0 2006.201.07:10:20.20#ibcon#flushed, iclass 6, count 0 2006.201.07:10:20.20#ibcon#about to write, iclass 6, count 0 2006.201.07:10:20.20#ibcon#wrote, iclass 6, count 0 2006.201.07:10:20.20#ibcon#about to read 3, iclass 6, count 0 2006.201.07:10:20.23#ibcon#read 3, iclass 6, count 0 2006.201.07:10:20.23#ibcon#about to read 4, iclass 6, count 0 2006.201.07:10:20.23#ibcon#read 4, iclass 6, count 0 2006.201.07:10:20.23#ibcon#about to read 5, iclass 6, count 0 2006.201.07:10:20.23#ibcon#read 5, iclass 6, count 0 2006.201.07:10:20.23#ibcon#about to read 6, iclass 6, count 0 2006.201.07:10:20.23#ibcon#read 6, iclass 6, count 0 2006.201.07:10:20.23#ibcon#end of sib2, iclass 6, count 0 2006.201.07:10:20.23#ibcon#*after write, iclass 6, count 0 2006.201.07:10:20.23#ibcon#*before return 0, iclass 6, count 0 2006.201.07:10:20.23#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:20.23#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:20.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:10:20.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:10:20.23$vck44/valo=2,534.99 2006.201.07:10:20.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.07:10:20.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.07:10:20.23#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:20.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:20.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:20.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:20.23#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:10:20.23#ibcon#first serial, iclass 10, count 0 2006.201.07:10:20.23#ibcon#enter sib2, iclass 10, count 0 2006.201.07:10:20.23#ibcon#flushed, iclass 10, count 0 2006.201.07:10:20.23#ibcon#about to write, iclass 10, count 0 2006.201.07:10:20.23#ibcon#wrote, iclass 10, count 0 2006.201.07:10:20.23#ibcon#about to read 3, iclass 10, count 0 2006.201.07:10:20.25#ibcon#read 3, iclass 10, count 0 2006.201.07:10:20.25#ibcon#about to read 4, iclass 10, count 0 2006.201.07:10:20.25#ibcon#read 4, iclass 10, count 0 2006.201.07:10:20.25#ibcon#about to read 5, iclass 10, count 0 2006.201.07:10:20.25#ibcon#read 5, iclass 10, count 0 2006.201.07:10:20.25#ibcon#about to read 6, iclass 10, count 0 2006.201.07:10:20.25#ibcon#read 6, iclass 10, count 0 2006.201.07:10:20.25#ibcon#end of sib2, iclass 10, count 0 2006.201.07:10:20.25#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:10:20.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:10:20.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:10:20.25#ibcon#*before write, iclass 10, count 0 2006.201.07:10:20.25#ibcon#enter sib2, iclass 10, count 0 2006.201.07:10:20.25#ibcon#flushed, iclass 10, count 0 2006.201.07:10:20.25#ibcon#about to write, iclass 10, count 0 2006.201.07:10:20.25#ibcon#wrote, iclass 10, count 0 2006.201.07:10:20.25#ibcon#about to read 3, iclass 10, count 0 2006.201.07:10:20.29#ibcon#read 3, iclass 10, count 0 2006.201.07:10:20.29#ibcon#about to read 4, iclass 10, count 0 2006.201.07:10:20.29#ibcon#read 4, iclass 10, count 0 2006.201.07:10:20.29#ibcon#about to read 5, iclass 10, count 0 2006.201.07:10:20.29#ibcon#read 5, iclass 10, count 0 2006.201.07:10:20.29#ibcon#about to read 6, iclass 10, count 0 2006.201.07:10:20.29#ibcon#read 6, iclass 10, count 0 2006.201.07:10:20.29#ibcon#end of sib2, iclass 10, count 0 2006.201.07:10:20.29#ibcon#*after write, iclass 10, count 0 2006.201.07:10:20.29#ibcon#*before return 0, iclass 10, count 0 2006.201.07:10:20.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:20.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:20.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:10:20.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:10:20.29$vck44/va=2,7 2006.201.07:10:20.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.07:10:20.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.07:10:20.29#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:20.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:20.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:20.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:20.35#ibcon#enter wrdev, iclass 12, count 2 2006.201.07:10:20.35#ibcon#first serial, iclass 12, count 2 2006.201.07:10:20.35#ibcon#enter sib2, iclass 12, count 2 2006.201.07:10:20.35#ibcon#flushed, iclass 12, count 2 2006.201.07:10:20.35#ibcon#about to write, iclass 12, count 2 2006.201.07:10:20.35#ibcon#wrote, iclass 12, count 2 2006.201.07:10:20.35#ibcon#about to read 3, iclass 12, count 2 2006.201.07:10:20.37#ibcon#read 3, iclass 12, count 2 2006.201.07:10:20.37#ibcon#about to read 4, iclass 12, count 2 2006.201.07:10:20.37#ibcon#read 4, iclass 12, count 2 2006.201.07:10:20.37#ibcon#about to read 5, iclass 12, count 2 2006.201.07:10:20.37#ibcon#read 5, iclass 12, count 2 2006.201.07:10:20.37#ibcon#about to read 6, iclass 12, count 2 2006.201.07:10:20.37#ibcon#read 6, iclass 12, count 2 2006.201.07:10:20.37#ibcon#end of sib2, iclass 12, count 2 2006.201.07:10:20.37#ibcon#*mode == 0, iclass 12, count 2 2006.201.07:10:20.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.07:10:20.37#ibcon#[25=AT02-07\r\n] 2006.201.07:10:20.37#ibcon#*before write, iclass 12, count 2 2006.201.07:10:20.37#ibcon#enter sib2, iclass 12, count 2 2006.201.07:10:20.37#ibcon#flushed, iclass 12, count 2 2006.201.07:10:20.37#ibcon#about to write, iclass 12, count 2 2006.201.07:10:20.37#ibcon#wrote, iclass 12, count 2 2006.201.07:10:20.37#ibcon#about to read 3, iclass 12, count 2 2006.201.07:10:20.40#ibcon#read 3, iclass 12, count 2 2006.201.07:10:20.40#ibcon#about to read 4, iclass 12, count 2 2006.201.07:10:20.40#ibcon#read 4, iclass 12, count 2 2006.201.07:10:20.40#ibcon#about to read 5, iclass 12, count 2 2006.201.07:10:20.40#ibcon#read 5, iclass 12, count 2 2006.201.07:10:20.40#ibcon#about to read 6, iclass 12, count 2 2006.201.07:10:20.40#ibcon#read 6, iclass 12, count 2 2006.201.07:10:20.40#ibcon#end of sib2, iclass 12, count 2 2006.201.07:10:20.40#ibcon#*after write, iclass 12, count 2 2006.201.07:10:20.40#ibcon#*before return 0, iclass 12, count 2 2006.201.07:10:20.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:20.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:20.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.07:10:20.40#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:20.40#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:20.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:20.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:20.52#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:10:20.52#ibcon#first serial, iclass 12, count 0 2006.201.07:10:20.52#ibcon#enter sib2, iclass 12, count 0 2006.201.07:10:20.52#ibcon#flushed, iclass 12, count 0 2006.201.07:10:20.52#ibcon#about to write, iclass 12, count 0 2006.201.07:10:20.52#ibcon#wrote, iclass 12, count 0 2006.201.07:10:20.52#ibcon#about to read 3, iclass 12, count 0 2006.201.07:10:20.54#ibcon#read 3, iclass 12, count 0 2006.201.07:10:20.54#ibcon#about to read 4, iclass 12, count 0 2006.201.07:10:20.54#ibcon#read 4, iclass 12, count 0 2006.201.07:10:20.54#ibcon#about to read 5, iclass 12, count 0 2006.201.07:10:20.54#ibcon#read 5, iclass 12, count 0 2006.201.07:10:20.54#ibcon#about to read 6, iclass 12, count 0 2006.201.07:10:20.54#ibcon#read 6, iclass 12, count 0 2006.201.07:10:20.54#ibcon#end of sib2, iclass 12, count 0 2006.201.07:10:20.54#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:10:20.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:10:20.54#ibcon#[25=USB\r\n] 2006.201.07:10:20.54#ibcon#*before write, iclass 12, count 0 2006.201.07:10:20.54#ibcon#enter sib2, iclass 12, count 0 2006.201.07:10:20.54#ibcon#flushed, iclass 12, count 0 2006.201.07:10:20.54#ibcon#about to write, iclass 12, count 0 2006.201.07:10:20.54#ibcon#wrote, iclass 12, count 0 2006.201.07:10:20.54#ibcon#about to read 3, iclass 12, count 0 2006.201.07:10:20.57#ibcon#read 3, iclass 12, count 0 2006.201.07:10:20.57#ibcon#about to read 4, iclass 12, count 0 2006.201.07:10:20.57#ibcon#read 4, iclass 12, count 0 2006.201.07:10:20.57#ibcon#about to read 5, iclass 12, count 0 2006.201.07:10:20.57#ibcon#read 5, iclass 12, count 0 2006.201.07:10:20.57#ibcon#about to read 6, iclass 12, count 0 2006.201.07:10:20.57#ibcon#read 6, iclass 12, count 0 2006.201.07:10:20.57#ibcon#end of sib2, iclass 12, count 0 2006.201.07:10:20.57#ibcon#*after write, iclass 12, count 0 2006.201.07:10:20.57#ibcon#*before return 0, iclass 12, count 0 2006.201.07:10:20.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:20.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:20.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:10:20.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:10:20.57$vck44/valo=3,564.99 2006.201.07:10:20.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.07:10:20.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.07:10:20.57#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:20.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:20.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:20.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:20.57#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:10:20.57#ibcon#first serial, iclass 14, count 0 2006.201.07:10:20.57#ibcon#enter sib2, iclass 14, count 0 2006.201.07:10:20.57#ibcon#flushed, iclass 14, count 0 2006.201.07:10:20.57#ibcon#about to write, iclass 14, count 0 2006.201.07:10:20.57#ibcon#wrote, iclass 14, count 0 2006.201.07:10:20.57#ibcon#about to read 3, iclass 14, count 0 2006.201.07:10:20.59#ibcon#read 3, iclass 14, count 0 2006.201.07:10:20.59#ibcon#about to read 4, iclass 14, count 0 2006.201.07:10:20.59#ibcon#read 4, iclass 14, count 0 2006.201.07:10:20.59#ibcon#about to read 5, iclass 14, count 0 2006.201.07:10:20.59#ibcon#read 5, iclass 14, count 0 2006.201.07:10:20.59#ibcon#about to read 6, iclass 14, count 0 2006.201.07:10:20.59#ibcon#read 6, iclass 14, count 0 2006.201.07:10:20.59#ibcon#end of sib2, iclass 14, count 0 2006.201.07:10:20.59#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:10:20.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:10:20.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:10:20.59#ibcon#*before write, iclass 14, count 0 2006.201.07:10:20.59#ibcon#enter sib2, iclass 14, count 0 2006.201.07:10:20.59#ibcon#flushed, iclass 14, count 0 2006.201.07:10:20.59#ibcon#about to write, iclass 14, count 0 2006.201.07:10:20.59#ibcon#wrote, iclass 14, count 0 2006.201.07:10:20.59#ibcon#about to read 3, iclass 14, count 0 2006.201.07:10:20.64#ibcon#read 3, iclass 14, count 0 2006.201.07:10:20.64#ibcon#about to read 4, iclass 14, count 0 2006.201.07:10:20.64#ibcon#read 4, iclass 14, count 0 2006.201.07:10:20.64#ibcon#about to read 5, iclass 14, count 0 2006.201.07:10:20.64#ibcon#read 5, iclass 14, count 0 2006.201.07:10:20.64#ibcon#about to read 6, iclass 14, count 0 2006.201.07:10:20.64#ibcon#read 6, iclass 14, count 0 2006.201.07:10:20.64#ibcon#end of sib2, iclass 14, count 0 2006.201.07:10:20.64#ibcon#*after write, iclass 14, count 0 2006.201.07:10:20.64#ibcon#*before return 0, iclass 14, count 0 2006.201.07:10:20.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:20.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:20.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:10:20.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:10:20.64$vck44/va=3,8 2006.201.07:10:20.64#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.07:10:20.64#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.07:10:20.64#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:20.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:20.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:20.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:20.69#ibcon#enter wrdev, iclass 16, count 2 2006.201.07:10:20.69#ibcon#first serial, iclass 16, count 2 2006.201.07:10:20.69#ibcon#enter sib2, iclass 16, count 2 2006.201.07:10:20.69#ibcon#flushed, iclass 16, count 2 2006.201.07:10:20.69#ibcon#about to write, iclass 16, count 2 2006.201.07:10:20.69#ibcon#wrote, iclass 16, count 2 2006.201.07:10:20.69#ibcon#about to read 3, iclass 16, count 2 2006.201.07:10:20.71#ibcon#read 3, iclass 16, count 2 2006.201.07:10:20.71#ibcon#about to read 4, iclass 16, count 2 2006.201.07:10:20.71#ibcon#read 4, iclass 16, count 2 2006.201.07:10:20.71#ibcon#about to read 5, iclass 16, count 2 2006.201.07:10:20.71#ibcon#read 5, iclass 16, count 2 2006.201.07:10:20.71#ibcon#about to read 6, iclass 16, count 2 2006.201.07:10:20.71#ibcon#read 6, iclass 16, count 2 2006.201.07:10:20.71#ibcon#end of sib2, iclass 16, count 2 2006.201.07:10:20.71#ibcon#*mode == 0, iclass 16, count 2 2006.201.07:10:20.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.07:10:20.71#ibcon#[25=AT03-08\r\n] 2006.201.07:10:20.71#ibcon#*before write, iclass 16, count 2 2006.201.07:10:20.71#ibcon#enter sib2, iclass 16, count 2 2006.201.07:10:20.71#ibcon#flushed, iclass 16, count 2 2006.201.07:10:20.71#ibcon#about to write, iclass 16, count 2 2006.201.07:10:20.71#ibcon#wrote, iclass 16, count 2 2006.201.07:10:20.71#ibcon#about to read 3, iclass 16, count 2 2006.201.07:10:20.74#ibcon#read 3, iclass 16, count 2 2006.201.07:10:20.74#ibcon#about to read 4, iclass 16, count 2 2006.201.07:10:20.74#ibcon#read 4, iclass 16, count 2 2006.201.07:10:20.74#ibcon#about to read 5, iclass 16, count 2 2006.201.07:10:20.74#ibcon#read 5, iclass 16, count 2 2006.201.07:10:20.74#ibcon#about to read 6, iclass 16, count 2 2006.201.07:10:20.74#ibcon#read 6, iclass 16, count 2 2006.201.07:10:20.74#ibcon#end of sib2, iclass 16, count 2 2006.201.07:10:20.74#ibcon#*after write, iclass 16, count 2 2006.201.07:10:20.74#ibcon#*before return 0, iclass 16, count 2 2006.201.07:10:20.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:20.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:20.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.07:10:20.74#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:20.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:20.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:20.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:20.86#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:10:20.86#ibcon#first serial, iclass 16, count 0 2006.201.07:10:20.86#ibcon#enter sib2, iclass 16, count 0 2006.201.07:10:20.86#ibcon#flushed, iclass 16, count 0 2006.201.07:10:20.86#ibcon#about to write, iclass 16, count 0 2006.201.07:10:20.86#ibcon#wrote, iclass 16, count 0 2006.201.07:10:20.86#ibcon#about to read 3, iclass 16, count 0 2006.201.07:10:20.88#ibcon#read 3, iclass 16, count 0 2006.201.07:10:20.88#ibcon#about to read 4, iclass 16, count 0 2006.201.07:10:20.88#ibcon#read 4, iclass 16, count 0 2006.201.07:10:20.88#ibcon#about to read 5, iclass 16, count 0 2006.201.07:10:20.88#ibcon#read 5, iclass 16, count 0 2006.201.07:10:20.88#ibcon#about to read 6, iclass 16, count 0 2006.201.07:10:20.88#ibcon#read 6, iclass 16, count 0 2006.201.07:10:20.88#ibcon#end of sib2, iclass 16, count 0 2006.201.07:10:20.88#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:10:20.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:10:20.88#ibcon#[25=USB\r\n] 2006.201.07:10:20.88#ibcon#*before write, iclass 16, count 0 2006.201.07:10:20.88#ibcon#enter sib2, iclass 16, count 0 2006.201.07:10:20.88#ibcon#flushed, iclass 16, count 0 2006.201.07:10:20.88#ibcon#about to write, iclass 16, count 0 2006.201.07:10:20.88#ibcon#wrote, iclass 16, count 0 2006.201.07:10:20.88#ibcon#about to read 3, iclass 16, count 0 2006.201.07:10:20.91#ibcon#read 3, iclass 16, count 0 2006.201.07:10:20.91#ibcon#about to read 4, iclass 16, count 0 2006.201.07:10:20.91#ibcon#read 4, iclass 16, count 0 2006.201.07:10:20.91#ibcon#about to read 5, iclass 16, count 0 2006.201.07:10:20.91#ibcon#read 5, iclass 16, count 0 2006.201.07:10:20.91#ibcon#about to read 6, iclass 16, count 0 2006.201.07:10:20.91#ibcon#read 6, iclass 16, count 0 2006.201.07:10:20.91#ibcon#end of sib2, iclass 16, count 0 2006.201.07:10:20.91#ibcon#*after write, iclass 16, count 0 2006.201.07:10:20.91#ibcon#*before return 0, iclass 16, count 0 2006.201.07:10:20.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:20.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:20.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:10:20.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:10:20.91$vck44/valo=4,624.99 2006.201.07:10:20.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.07:10:20.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.07:10:20.91#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:20.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:20.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:20.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:20.91#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:10:20.91#ibcon#first serial, iclass 18, count 0 2006.201.07:10:20.91#ibcon#enter sib2, iclass 18, count 0 2006.201.07:10:20.91#ibcon#flushed, iclass 18, count 0 2006.201.07:10:20.91#ibcon#about to write, iclass 18, count 0 2006.201.07:10:20.91#ibcon#wrote, iclass 18, count 0 2006.201.07:10:20.91#ibcon#about to read 3, iclass 18, count 0 2006.201.07:10:20.93#ibcon#read 3, iclass 18, count 0 2006.201.07:10:20.93#ibcon#about to read 4, iclass 18, count 0 2006.201.07:10:20.93#ibcon#read 4, iclass 18, count 0 2006.201.07:10:20.93#ibcon#about to read 5, iclass 18, count 0 2006.201.07:10:20.93#ibcon#read 5, iclass 18, count 0 2006.201.07:10:20.93#ibcon#about to read 6, iclass 18, count 0 2006.201.07:10:20.93#ibcon#read 6, iclass 18, count 0 2006.201.07:10:20.93#ibcon#end of sib2, iclass 18, count 0 2006.201.07:10:20.93#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:10:20.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:10:20.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:10:20.93#ibcon#*before write, iclass 18, count 0 2006.201.07:10:20.93#ibcon#enter sib2, iclass 18, count 0 2006.201.07:10:20.93#ibcon#flushed, iclass 18, count 0 2006.201.07:10:20.93#ibcon#about to write, iclass 18, count 0 2006.201.07:10:20.93#ibcon#wrote, iclass 18, count 0 2006.201.07:10:20.93#ibcon#about to read 3, iclass 18, count 0 2006.201.07:10:20.97#ibcon#read 3, iclass 18, count 0 2006.201.07:10:20.97#ibcon#about to read 4, iclass 18, count 0 2006.201.07:10:20.97#ibcon#read 4, iclass 18, count 0 2006.201.07:10:20.97#ibcon#about to read 5, iclass 18, count 0 2006.201.07:10:20.97#ibcon#read 5, iclass 18, count 0 2006.201.07:10:20.97#ibcon#about to read 6, iclass 18, count 0 2006.201.07:10:20.97#ibcon#read 6, iclass 18, count 0 2006.201.07:10:20.97#ibcon#end of sib2, iclass 18, count 0 2006.201.07:10:20.97#ibcon#*after write, iclass 18, count 0 2006.201.07:10:20.97#ibcon#*before return 0, iclass 18, count 0 2006.201.07:10:20.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:20.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:20.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:10:20.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:10:20.97$vck44/va=4,7 2006.201.07:10:20.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.07:10:20.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.07:10:20.97#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:20.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:21.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:21.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:21.03#ibcon#enter wrdev, iclass 20, count 2 2006.201.07:10:21.03#ibcon#first serial, iclass 20, count 2 2006.201.07:10:21.03#ibcon#enter sib2, iclass 20, count 2 2006.201.07:10:21.03#ibcon#flushed, iclass 20, count 2 2006.201.07:10:21.03#ibcon#about to write, iclass 20, count 2 2006.201.07:10:21.03#ibcon#wrote, iclass 20, count 2 2006.201.07:10:21.03#ibcon#about to read 3, iclass 20, count 2 2006.201.07:10:21.05#ibcon#read 3, iclass 20, count 2 2006.201.07:10:21.05#ibcon#about to read 4, iclass 20, count 2 2006.201.07:10:21.05#ibcon#read 4, iclass 20, count 2 2006.201.07:10:21.05#ibcon#about to read 5, iclass 20, count 2 2006.201.07:10:21.05#ibcon#read 5, iclass 20, count 2 2006.201.07:10:21.05#ibcon#about to read 6, iclass 20, count 2 2006.201.07:10:21.05#ibcon#read 6, iclass 20, count 2 2006.201.07:10:21.05#ibcon#end of sib2, iclass 20, count 2 2006.201.07:10:21.05#ibcon#*mode == 0, iclass 20, count 2 2006.201.07:10:21.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.07:10:21.05#ibcon#[25=AT04-07\r\n] 2006.201.07:10:21.05#ibcon#*before write, iclass 20, count 2 2006.201.07:10:21.05#ibcon#enter sib2, iclass 20, count 2 2006.201.07:10:21.05#ibcon#flushed, iclass 20, count 2 2006.201.07:10:21.05#ibcon#about to write, iclass 20, count 2 2006.201.07:10:21.05#ibcon#wrote, iclass 20, count 2 2006.201.07:10:21.05#ibcon#about to read 3, iclass 20, count 2 2006.201.07:10:21.08#ibcon#read 3, iclass 20, count 2 2006.201.07:10:21.08#ibcon#about to read 4, iclass 20, count 2 2006.201.07:10:21.08#ibcon#read 4, iclass 20, count 2 2006.201.07:10:21.08#ibcon#about to read 5, iclass 20, count 2 2006.201.07:10:21.08#ibcon#read 5, iclass 20, count 2 2006.201.07:10:21.08#ibcon#about to read 6, iclass 20, count 2 2006.201.07:10:21.08#ibcon#read 6, iclass 20, count 2 2006.201.07:10:21.08#ibcon#end of sib2, iclass 20, count 2 2006.201.07:10:21.08#ibcon#*after write, iclass 20, count 2 2006.201.07:10:21.08#ibcon#*before return 0, iclass 20, count 2 2006.201.07:10:21.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:21.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:21.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.07:10:21.08#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:21.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:21.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:21.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:21.20#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:10:21.20#ibcon#first serial, iclass 20, count 0 2006.201.07:10:21.20#ibcon#enter sib2, iclass 20, count 0 2006.201.07:10:21.20#ibcon#flushed, iclass 20, count 0 2006.201.07:10:21.20#ibcon#about to write, iclass 20, count 0 2006.201.07:10:21.20#ibcon#wrote, iclass 20, count 0 2006.201.07:10:21.20#ibcon#about to read 3, iclass 20, count 0 2006.201.07:10:21.22#ibcon#read 3, iclass 20, count 0 2006.201.07:10:21.22#ibcon#about to read 4, iclass 20, count 0 2006.201.07:10:21.22#ibcon#read 4, iclass 20, count 0 2006.201.07:10:21.22#ibcon#about to read 5, iclass 20, count 0 2006.201.07:10:21.22#ibcon#read 5, iclass 20, count 0 2006.201.07:10:21.22#ibcon#about to read 6, iclass 20, count 0 2006.201.07:10:21.22#ibcon#read 6, iclass 20, count 0 2006.201.07:10:21.22#ibcon#end of sib2, iclass 20, count 0 2006.201.07:10:21.22#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:10:21.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:10:21.22#ibcon#[25=USB\r\n] 2006.201.07:10:21.22#ibcon#*before write, iclass 20, count 0 2006.201.07:10:21.22#ibcon#enter sib2, iclass 20, count 0 2006.201.07:10:21.22#ibcon#flushed, iclass 20, count 0 2006.201.07:10:21.22#ibcon#about to write, iclass 20, count 0 2006.201.07:10:21.22#ibcon#wrote, iclass 20, count 0 2006.201.07:10:21.22#ibcon#about to read 3, iclass 20, count 0 2006.201.07:10:21.25#ibcon#read 3, iclass 20, count 0 2006.201.07:10:21.25#ibcon#about to read 4, iclass 20, count 0 2006.201.07:10:21.25#ibcon#read 4, iclass 20, count 0 2006.201.07:10:21.25#ibcon#about to read 5, iclass 20, count 0 2006.201.07:10:21.25#ibcon#read 5, iclass 20, count 0 2006.201.07:10:21.25#ibcon#about to read 6, iclass 20, count 0 2006.201.07:10:21.25#ibcon#read 6, iclass 20, count 0 2006.201.07:10:21.25#ibcon#end of sib2, iclass 20, count 0 2006.201.07:10:21.25#ibcon#*after write, iclass 20, count 0 2006.201.07:10:21.25#ibcon#*before return 0, iclass 20, count 0 2006.201.07:10:21.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:21.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:21.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:10:21.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:10:21.25$vck44/valo=5,734.99 2006.201.07:10:21.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.07:10:21.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.07:10:21.25#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:21.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:21.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:21.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:21.25#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:10:21.25#ibcon#first serial, iclass 22, count 0 2006.201.07:10:21.25#ibcon#enter sib2, iclass 22, count 0 2006.201.07:10:21.25#ibcon#flushed, iclass 22, count 0 2006.201.07:10:21.25#ibcon#about to write, iclass 22, count 0 2006.201.07:10:21.25#ibcon#wrote, iclass 22, count 0 2006.201.07:10:21.25#ibcon#about to read 3, iclass 22, count 0 2006.201.07:10:21.27#ibcon#read 3, iclass 22, count 0 2006.201.07:10:21.27#ibcon#about to read 4, iclass 22, count 0 2006.201.07:10:21.27#ibcon#read 4, iclass 22, count 0 2006.201.07:10:21.27#ibcon#about to read 5, iclass 22, count 0 2006.201.07:10:21.27#ibcon#read 5, iclass 22, count 0 2006.201.07:10:21.27#ibcon#about to read 6, iclass 22, count 0 2006.201.07:10:21.27#ibcon#read 6, iclass 22, count 0 2006.201.07:10:21.27#ibcon#end of sib2, iclass 22, count 0 2006.201.07:10:21.27#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:10:21.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:10:21.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:10:21.27#ibcon#*before write, iclass 22, count 0 2006.201.07:10:21.27#ibcon#enter sib2, iclass 22, count 0 2006.201.07:10:21.27#ibcon#flushed, iclass 22, count 0 2006.201.07:10:21.27#ibcon#about to write, iclass 22, count 0 2006.201.07:10:21.27#ibcon#wrote, iclass 22, count 0 2006.201.07:10:21.27#ibcon#about to read 3, iclass 22, count 0 2006.201.07:10:21.31#ibcon#read 3, iclass 22, count 0 2006.201.07:10:21.31#ibcon#about to read 4, iclass 22, count 0 2006.201.07:10:21.31#ibcon#read 4, iclass 22, count 0 2006.201.07:10:21.31#ibcon#about to read 5, iclass 22, count 0 2006.201.07:10:21.31#ibcon#read 5, iclass 22, count 0 2006.201.07:10:21.31#ibcon#about to read 6, iclass 22, count 0 2006.201.07:10:21.31#ibcon#read 6, iclass 22, count 0 2006.201.07:10:21.31#ibcon#end of sib2, iclass 22, count 0 2006.201.07:10:21.31#ibcon#*after write, iclass 22, count 0 2006.201.07:10:21.31#ibcon#*before return 0, iclass 22, count 0 2006.201.07:10:21.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:21.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:21.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:10:21.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:10:21.31$vck44/va=5,4 2006.201.07:10:21.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.07:10:21.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.07:10:21.31#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:21.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:21.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:21.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:21.37#ibcon#enter wrdev, iclass 24, count 2 2006.201.07:10:21.37#ibcon#first serial, iclass 24, count 2 2006.201.07:10:21.37#ibcon#enter sib2, iclass 24, count 2 2006.201.07:10:21.37#ibcon#flushed, iclass 24, count 2 2006.201.07:10:21.37#ibcon#about to write, iclass 24, count 2 2006.201.07:10:21.37#ibcon#wrote, iclass 24, count 2 2006.201.07:10:21.37#ibcon#about to read 3, iclass 24, count 2 2006.201.07:10:21.39#ibcon#read 3, iclass 24, count 2 2006.201.07:10:21.39#ibcon#about to read 4, iclass 24, count 2 2006.201.07:10:21.39#ibcon#read 4, iclass 24, count 2 2006.201.07:10:21.39#ibcon#about to read 5, iclass 24, count 2 2006.201.07:10:21.39#ibcon#read 5, iclass 24, count 2 2006.201.07:10:21.39#ibcon#about to read 6, iclass 24, count 2 2006.201.07:10:21.39#ibcon#read 6, iclass 24, count 2 2006.201.07:10:21.39#ibcon#end of sib2, iclass 24, count 2 2006.201.07:10:21.39#ibcon#*mode == 0, iclass 24, count 2 2006.201.07:10:21.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.07:10:21.39#ibcon#[25=AT05-04\r\n] 2006.201.07:10:21.39#ibcon#*before write, iclass 24, count 2 2006.201.07:10:21.39#ibcon#enter sib2, iclass 24, count 2 2006.201.07:10:21.39#ibcon#flushed, iclass 24, count 2 2006.201.07:10:21.39#ibcon#about to write, iclass 24, count 2 2006.201.07:10:21.39#ibcon#wrote, iclass 24, count 2 2006.201.07:10:21.39#ibcon#about to read 3, iclass 24, count 2 2006.201.07:10:21.42#ibcon#read 3, iclass 24, count 2 2006.201.07:10:21.42#ibcon#about to read 4, iclass 24, count 2 2006.201.07:10:21.42#ibcon#read 4, iclass 24, count 2 2006.201.07:10:21.42#ibcon#about to read 5, iclass 24, count 2 2006.201.07:10:21.42#ibcon#read 5, iclass 24, count 2 2006.201.07:10:21.42#ibcon#about to read 6, iclass 24, count 2 2006.201.07:10:21.42#ibcon#read 6, iclass 24, count 2 2006.201.07:10:21.42#ibcon#end of sib2, iclass 24, count 2 2006.201.07:10:21.42#ibcon#*after write, iclass 24, count 2 2006.201.07:10:21.42#ibcon#*before return 0, iclass 24, count 2 2006.201.07:10:21.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:21.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:21.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.07:10:21.42#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:21.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:21.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:21.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:21.54#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:10:21.54#ibcon#first serial, iclass 24, count 0 2006.201.07:10:21.54#ibcon#enter sib2, iclass 24, count 0 2006.201.07:10:21.54#ibcon#flushed, iclass 24, count 0 2006.201.07:10:21.54#ibcon#about to write, iclass 24, count 0 2006.201.07:10:21.54#ibcon#wrote, iclass 24, count 0 2006.201.07:10:21.54#ibcon#about to read 3, iclass 24, count 0 2006.201.07:10:21.56#ibcon#read 3, iclass 24, count 0 2006.201.07:10:21.56#ibcon#about to read 4, iclass 24, count 0 2006.201.07:10:21.56#ibcon#read 4, iclass 24, count 0 2006.201.07:10:21.56#ibcon#about to read 5, iclass 24, count 0 2006.201.07:10:21.56#ibcon#read 5, iclass 24, count 0 2006.201.07:10:21.56#ibcon#about to read 6, iclass 24, count 0 2006.201.07:10:21.56#ibcon#read 6, iclass 24, count 0 2006.201.07:10:21.56#ibcon#end of sib2, iclass 24, count 0 2006.201.07:10:21.56#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:10:21.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:10:21.56#ibcon#[25=USB\r\n] 2006.201.07:10:21.56#ibcon#*before write, iclass 24, count 0 2006.201.07:10:21.56#ibcon#enter sib2, iclass 24, count 0 2006.201.07:10:21.56#ibcon#flushed, iclass 24, count 0 2006.201.07:10:21.56#ibcon#about to write, iclass 24, count 0 2006.201.07:10:21.56#ibcon#wrote, iclass 24, count 0 2006.201.07:10:21.56#ibcon#about to read 3, iclass 24, count 0 2006.201.07:10:21.59#ibcon#read 3, iclass 24, count 0 2006.201.07:10:21.59#ibcon#about to read 4, iclass 24, count 0 2006.201.07:10:21.59#ibcon#read 4, iclass 24, count 0 2006.201.07:10:21.59#ibcon#about to read 5, iclass 24, count 0 2006.201.07:10:21.59#ibcon#read 5, iclass 24, count 0 2006.201.07:10:21.59#ibcon#about to read 6, iclass 24, count 0 2006.201.07:10:21.59#ibcon#read 6, iclass 24, count 0 2006.201.07:10:21.59#ibcon#end of sib2, iclass 24, count 0 2006.201.07:10:21.59#ibcon#*after write, iclass 24, count 0 2006.201.07:10:21.59#ibcon#*before return 0, iclass 24, count 0 2006.201.07:10:21.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:21.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:21.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:10:21.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:10:21.59$vck44/valo=6,814.99 2006.201.07:10:21.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.07:10:21.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.07:10:21.59#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:21.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:21.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:21.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:21.59#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:10:21.59#ibcon#first serial, iclass 26, count 0 2006.201.07:10:21.59#ibcon#enter sib2, iclass 26, count 0 2006.201.07:10:21.59#ibcon#flushed, iclass 26, count 0 2006.201.07:10:21.59#ibcon#about to write, iclass 26, count 0 2006.201.07:10:21.59#ibcon#wrote, iclass 26, count 0 2006.201.07:10:21.59#ibcon#about to read 3, iclass 26, count 0 2006.201.07:10:21.61#ibcon#read 3, iclass 26, count 0 2006.201.07:10:21.61#ibcon#about to read 4, iclass 26, count 0 2006.201.07:10:21.61#ibcon#read 4, iclass 26, count 0 2006.201.07:10:21.61#ibcon#about to read 5, iclass 26, count 0 2006.201.07:10:21.61#ibcon#read 5, iclass 26, count 0 2006.201.07:10:21.61#ibcon#about to read 6, iclass 26, count 0 2006.201.07:10:21.61#ibcon#read 6, iclass 26, count 0 2006.201.07:10:21.61#ibcon#end of sib2, iclass 26, count 0 2006.201.07:10:21.61#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:10:21.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:10:21.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:10:21.61#ibcon#*before write, iclass 26, count 0 2006.201.07:10:21.61#ibcon#enter sib2, iclass 26, count 0 2006.201.07:10:21.61#ibcon#flushed, iclass 26, count 0 2006.201.07:10:21.61#ibcon#about to write, iclass 26, count 0 2006.201.07:10:21.61#ibcon#wrote, iclass 26, count 0 2006.201.07:10:21.61#ibcon#about to read 3, iclass 26, count 0 2006.201.07:10:21.66#ibcon#read 3, iclass 26, count 0 2006.201.07:10:21.66#ibcon#about to read 4, iclass 26, count 0 2006.201.07:10:21.66#ibcon#read 4, iclass 26, count 0 2006.201.07:10:21.66#ibcon#about to read 5, iclass 26, count 0 2006.201.07:10:21.66#ibcon#read 5, iclass 26, count 0 2006.201.07:10:21.66#ibcon#about to read 6, iclass 26, count 0 2006.201.07:10:21.66#ibcon#read 6, iclass 26, count 0 2006.201.07:10:21.66#ibcon#end of sib2, iclass 26, count 0 2006.201.07:10:21.66#ibcon#*after write, iclass 26, count 0 2006.201.07:10:21.66#ibcon#*before return 0, iclass 26, count 0 2006.201.07:10:21.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:21.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:21.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:10:21.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:10:21.66$vck44/va=6,5 2006.201.07:10:21.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.07:10:21.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.07:10:21.66#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:21.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:21.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:21.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:21.71#ibcon#enter wrdev, iclass 28, count 2 2006.201.07:10:21.71#ibcon#first serial, iclass 28, count 2 2006.201.07:10:21.71#ibcon#enter sib2, iclass 28, count 2 2006.201.07:10:21.71#ibcon#flushed, iclass 28, count 2 2006.201.07:10:21.71#ibcon#about to write, iclass 28, count 2 2006.201.07:10:21.71#ibcon#wrote, iclass 28, count 2 2006.201.07:10:21.71#ibcon#about to read 3, iclass 28, count 2 2006.201.07:10:21.73#ibcon#read 3, iclass 28, count 2 2006.201.07:10:21.73#ibcon#about to read 4, iclass 28, count 2 2006.201.07:10:21.73#ibcon#read 4, iclass 28, count 2 2006.201.07:10:21.73#ibcon#about to read 5, iclass 28, count 2 2006.201.07:10:21.73#ibcon#read 5, iclass 28, count 2 2006.201.07:10:21.73#ibcon#about to read 6, iclass 28, count 2 2006.201.07:10:21.73#ibcon#read 6, iclass 28, count 2 2006.201.07:10:21.73#ibcon#end of sib2, iclass 28, count 2 2006.201.07:10:21.73#ibcon#*mode == 0, iclass 28, count 2 2006.201.07:10:21.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.07:10:21.73#ibcon#[25=AT06-05\r\n] 2006.201.07:10:21.73#ibcon#*before write, iclass 28, count 2 2006.201.07:10:21.73#ibcon#enter sib2, iclass 28, count 2 2006.201.07:10:21.73#ibcon#flushed, iclass 28, count 2 2006.201.07:10:21.73#ibcon#about to write, iclass 28, count 2 2006.201.07:10:21.73#ibcon#wrote, iclass 28, count 2 2006.201.07:10:21.73#ibcon#about to read 3, iclass 28, count 2 2006.201.07:10:21.76#ibcon#read 3, iclass 28, count 2 2006.201.07:10:21.76#ibcon#about to read 4, iclass 28, count 2 2006.201.07:10:21.76#ibcon#read 4, iclass 28, count 2 2006.201.07:10:21.76#ibcon#about to read 5, iclass 28, count 2 2006.201.07:10:21.76#ibcon#read 5, iclass 28, count 2 2006.201.07:10:21.76#ibcon#about to read 6, iclass 28, count 2 2006.201.07:10:21.76#ibcon#read 6, iclass 28, count 2 2006.201.07:10:21.76#ibcon#end of sib2, iclass 28, count 2 2006.201.07:10:21.76#ibcon#*after write, iclass 28, count 2 2006.201.07:10:21.76#ibcon#*before return 0, iclass 28, count 2 2006.201.07:10:21.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:21.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:21.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.07:10:21.76#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:21.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:21.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:21.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:21.88#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:10:21.88#ibcon#first serial, iclass 28, count 0 2006.201.07:10:21.88#ibcon#enter sib2, iclass 28, count 0 2006.201.07:10:21.88#ibcon#flushed, iclass 28, count 0 2006.201.07:10:21.88#ibcon#about to write, iclass 28, count 0 2006.201.07:10:21.88#ibcon#wrote, iclass 28, count 0 2006.201.07:10:21.88#ibcon#about to read 3, iclass 28, count 0 2006.201.07:10:21.90#ibcon#read 3, iclass 28, count 0 2006.201.07:10:21.90#ibcon#about to read 4, iclass 28, count 0 2006.201.07:10:21.90#ibcon#read 4, iclass 28, count 0 2006.201.07:10:21.90#ibcon#about to read 5, iclass 28, count 0 2006.201.07:10:21.90#ibcon#read 5, iclass 28, count 0 2006.201.07:10:21.90#ibcon#about to read 6, iclass 28, count 0 2006.201.07:10:21.90#ibcon#read 6, iclass 28, count 0 2006.201.07:10:21.90#ibcon#end of sib2, iclass 28, count 0 2006.201.07:10:21.90#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:10:21.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:10:21.90#ibcon#[25=USB\r\n] 2006.201.07:10:21.90#ibcon#*before write, iclass 28, count 0 2006.201.07:10:21.90#ibcon#enter sib2, iclass 28, count 0 2006.201.07:10:21.90#ibcon#flushed, iclass 28, count 0 2006.201.07:10:21.90#ibcon#about to write, iclass 28, count 0 2006.201.07:10:21.90#ibcon#wrote, iclass 28, count 0 2006.201.07:10:21.90#ibcon#about to read 3, iclass 28, count 0 2006.201.07:10:21.93#ibcon#read 3, iclass 28, count 0 2006.201.07:10:21.93#ibcon#about to read 4, iclass 28, count 0 2006.201.07:10:21.93#ibcon#read 4, iclass 28, count 0 2006.201.07:10:21.93#ibcon#about to read 5, iclass 28, count 0 2006.201.07:10:21.93#ibcon#read 5, iclass 28, count 0 2006.201.07:10:21.93#ibcon#about to read 6, iclass 28, count 0 2006.201.07:10:21.93#ibcon#read 6, iclass 28, count 0 2006.201.07:10:21.93#ibcon#end of sib2, iclass 28, count 0 2006.201.07:10:21.93#ibcon#*after write, iclass 28, count 0 2006.201.07:10:21.93#ibcon#*before return 0, iclass 28, count 0 2006.201.07:10:21.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:21.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:21.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:10:21.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:10:21.93$vck44/valo=7,864.99 2006.201.07:10:21.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.07:10:21.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.07:10:21.93#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:21.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:21.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:21.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:21.93#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:10:21.93#ibcon#first serial, iclass 30, count 0 2006.201.07:10:21.93#ibcon#enter sib2, iclass 30, count 0 2006.201.07:10:21.93#ibcon#flushed, iclass 30, count 0 2006.201.07:10:21.93#ibcon#about to write, iclass 30, count 0 2006.201.07:10:21.93#ibcon#wrote, iclass 30, count 0 2006.201.07:10:21.93#ibcon#about to read 3, iclass 30, count 0 2006.201.07:10:21.95#ibcon#read 3, iclass 30, count 0 2006.201.07:10:21.95#ibcon#about to read 4, iclass 30, count 0 2006.201.07:10:21.95#ibcon#read 4, iclass 30, count 0 2006.201.07:10:21.95#ibcon#about to read 5, iclass 30, count 0 2006.201.07:10:21.95#ibcon#read 5, iclass 30, count 0 2006.201.07:10:21.95#ibcon#about to read 6, iclass 30, count 0 2006.201.07:10:21.95#ibcon#read 6, iclass 30, count 0 2006.201.07:10:21.95#ibcon#end of sib2, iclass 30, count 0 2006.201.07:10:21.95#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:10:21.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:10:21.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:10:21.95#ibcon#*before write, iclass 30, count 0 2006.201.07:10:21.95#ibcon#enter sib2, iclass 30, count 0 2006.201.07:10:21.95#ibcon#flushed, iclass 30, count 0 2006.201.07:10:21.95#ibcon#about to write, iclass 30, count 0 2006.201.07:10:21.95#ibcon#wrote, iclass 30, count 0 2006.201.07:10:21.95#ibcon#about to read 3, iclass 30, count 0 2006.201.07:10:21.99#ibcon#read 3, iclass 30, count 0 2006.201.07:10:21.99#ibcon#about to read 4, iclass 30, count 0 2006.201.07:10:21.99#ibcon#read 4, iclass 30, count 0 2006.201.07:10:21.99#ibcon#about to read 5, iclass 30, count 0 2006.201.07:10:21.99#ibcon#read 5, iclass 30, count 0 2006.201.07:10:21.99#ibcon#about to read 6, iclass 30, count 0 2006.201.07:10:21.99#ibcon#read 6, iclass 30, count 0 2006.201.07:10:21.99#ibcon#end of sib2, iclass 30, count 0 2006.201.07:10:21.99#ibcon#*after write, iclass 30, count 0 2006.201.07:10:21.99#ibcon#*before return 0, iclass 30, count 0 2006.201.07:10:21.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:21.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:21.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:10:21.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:10:21.99$vck44/va=7,5 2006.201.07:10:21.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.07:10:21.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.07:10:21.99#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:21.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:22.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:22.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:22.05#ibcon#enter wrdev, iclass 32, count 2 2006.201.07:10:22.05#ibcon#first serial, iclass 32, count 2 2006.201.07:10:22.05#ibcon#enter sib2, iclass 32, count 2 2006.201.07:10:22.05#ibcon#flushed, iclass 32, count 2 2006.201.07:10:22.05#ibcon#about to write, iclass 32, count 2 2006.201.07:10:22.05#ibcon#wrote, iclass 32, count 2 2006.201.07:10:22.05#ibcon#about to read 3, iclass 32, count 2 2006.201.07:10:22.07#ibcon#read 3, iclass 32, count 2 2006.201.07:10:22.07#ibcon#about to read 4, iclass 32, count 2 2006.201.07:10:22.07#ibcon#read 4, iclass 32, count 2 2006.201.07:10:22.07#ibcon#about to read 5, iclass 32, count 2 2006.201.07:10:22.07#ibcon#read 5, iclass 32, count 2 2006.201.07:10:22.07#ibcon#about to read 6, iclass 32, count 2 2006.201.07:10:22.07#ibcon#read 6, iclass 32, count 2 2006.201.07:10:22.07#ibcon#end of sib2, iclass 32, count 2 2006.201.07:10:22.07#ibcon#*mode == 0, iclass 32, count 2 2006.201.07:10:22.07#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.07:10:22.07#ibcon#[25=AT07-05\r\n] 2006.201.07:10:22.07#ibcon#*before write, iclass 32, count 2 2006.201.07:10:22.07#ibcon#enter sib2, iclass 32, count 2 2006.201.07:10:22.07#ibcon#flushed, iclass 32, count 2 2006.201.07:10:22.07#ibcon#about to write, iclass 32, count 2 2006.201.07:10:22.07#ibcon#wrote, iclass 32, count 2 2006.201.07:10:22.07#ibcon#about to read 3, iclass 32, count 2 2006.201.07:10:22.10#ibcon#read 3, iclass 32, count 2 2006.201.07:10:22.10#ibcon#about to read 4, iclass 32, count 2 2006.201.07:10:22.10#ibcon#read 4, iclass 32, count 2 2006.201.07:10:22.10#ibcon#about to read 5, iclass 32, count 2 2006.201.07:10:22.10#ibcon#read 5, iclass 32, count 2 2006.201.07:10:22.10#ibcon#about to read 6, iclass 32, count 2 2006.201.07:10:22.10#ibcon#read 6, iclass 32, count 2 2006.201.07:10:22.10#ibcon#end of sib2, iclass 32, count 2 2006.201.07:10:22.10#ibcon#*after write, iclass 32, count 2 2006.201.07:10:22.10#ibcon#*before return 0, iclass 32, count 2 2006.201.07:10:22.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:22.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:22.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.07:10:22.10#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:22.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:22.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:22.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:22.22#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:10:22.22#ibcon#first serial, iclass 32, count 0 2006.201.07:10:22.22#ibcon#enter sib2, iclass 32, count 0 2006.201.07:10:22.22#ibcon#flushed, iclass 32, count 0 2006.201.07:10:22.22#ibcon#about to write, iclass 32, count 0 2006.201.07:10:22.22#ibcon#wrote, iclass 32, count 0 2006.201.07:10:22.22#ibcon#about to read 3, iclass 32, count 0 2006.201.07:10:22.24#ibcon#read 3, iclass 32, count 0 2006.201.07:10:22.24#ibcon#about to read 4, iclass 32, count 0 2006.201.07:10:22.24#ibcon#read 4, iclass 32, count 0 2006.201.07:10:22.24#ibcon#about to read 5, iclass 32, count 0 2006.201.07:10:22.24#ibcon#read 5, iclass 32, count 0 2006.201.07:10:22.24#ibcon#about to read 6, iclass 32, count 0 2006.201.07:10:22.24#ibcon#read 6, iclass 32, count 0 2006.201.07:10:22.24#ibcon#end of sib2, iclass 32, count 0 2006.201.07:10:22.24#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:10:22.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:10:22.24#ibcon#[25=USB\r\n] 2006.201.07:10:22.24#ibcon#*before write, iclass 32, count 0 2006.201.07:10:22.24#ibcon#enter sib2, iclass 32, count 0 2006.201.07:10:22.24#ibcon#flushed, iclass 32, count 0 2006.201.07:10:22.24#ibcon#about to write, iclass 32, count 0 2006.201.07:10:22.24#ibcon#wrote, iclass 32, count 0 2006.201.07:10:22.24#ibcon#about to read 3, iclass 32, count 0 2006.201.07:10:22.27#ibcon#read 3, iclass 32, count 0 2006.201.07:10:22.27#ibcon#about to read 4, iclass 32, count 0 2006.201.07:10:22.27#ibcon#read 4, iclass 32, count 0 2006.201.07:10:22.27#ibcon#about to read 5, iclass 32, count 0 2006.201.07:10:22.27#ibcon#read 5, iclass 32, count 0 2006.201.07:10:22.27#ibcon#about to read 6, iclass 32, count 0 2006.201.07:10:22.27#ibcon#read 6, iclass 32, count 0 2006.201.07:10:22.27#ibcon#end of sib2, iclass 32, count 0 2006.201.07:10:22.27#ibcon#*after write, iclass 32, count 0 2006.201.07:10:22.27#ibcon#*before return 0, iclass 32, count 0 2006.201.07:10:22.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:22.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:22.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:10:22.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:10:22.27$vck44/valo=8,884.99 2006.201.07:10:22.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.07:10:22.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.07:10:22.27#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:22.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:22.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:22.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:22.27#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:10:22.27#ibcon#first serial, iclass 34, count 0 2006.201.07:10:22.27#ibcon#enter sib2, iclass 34, count 0 2006.201.07:10:22.27#ibcon#flushed, iclass 34, count 0 2006.201.07:10:22.27#ibcon#about to write, iclass 34, count 0 2006.201.07:10:22.27#ibcon#wrote, iclass 34, count 0 2006.201.07:10:22.27#ibcon#about to read 3, iclass 34, count 0 2006.201.07:10:22.29#ibcon#read 3, iclass 34, count 0 2006.201.07:10:22.29#ibcon#about to read 4, iclass 34, count 0 2006.201.07:10:22.29#ibcon#read 4, iclass 34, count 0 2006.201.07:10:22.29#ibcon#about to read 5, iclass 34, count 0 2006.201.07:10:22.29#ibcon#read 5, iclass 34, count 0 2006.201.07:10:22.29#ibcon#about to read 6, iclass 34, count 0 2006.201.07:10:22.29#ibcon#read 6, iclass 34, count 0 2006.201.07:10:22.29#ibcon#end of sib2, iclass 34, count 0 2006.201.07:10:22.29#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:10:22.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:10:22.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:10:22.29#ibcon#*before write, iclass 34, count 0 2006.201.07:10:22.29#ibcon#enter sib2, iclass 34, count 0 2006.201.07:10:22.29#ibcon#flushed, iclass 34, count 0 2006.201.07:10:22.29#ibcon#about to write, iclass 34, count 0 2006.201.07:10:22.29#ibcon#wrote, iclass 34, count 0 2006.201.07:10:22.29#ibcon#about to read 3, iclass 34, count 0 2006.201.07:10:22.34#ibcon#read 3, iclass 34, count 0 2006.201.07:10:22.34#ibcon#about to read 4, iclass 34, count 0 2006.201.07:10:22.34#ibcon#read 4, iclass 34, count 0 2006.201.07:10:22.34#ibcon#about to read 5, iclass 34, count 0 2006.201.07:10:22.34#ibcon#read 5, iclass 34, count 0 2006.201.07:10:22.34#ibcon#about to read 6, iclass 34, count 0 2006.201.07:10:22.34#ibcon#read 6, iclass 34, count 0 2006.201.07:10:22.34#ibcon#end of sib2, iclass 34, count 0 2006.201.07:10:22.34#ibcon#*after write, iclass 34, count 0 2006.201.07:10:22.34#ibcon#*before return 0, iclass 34, count 0 2006.201.07:10:22.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:22.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:22.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:10:22.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:10:22.34$vck44/va=8,4 2006.201.07:10:22.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.07:10:22.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.07:10:22.34#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:22.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:10:22.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:10:22.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:10:22.39#ibcon#enter wrdev, iclass 36, count 2 2006.201.07:10:22.39#ibcon#first serial, iclass 36, count 2 2006.201.07:10:22.39#ibcon#enter sib2, iclass 36, count 2 2006.201.07:10:22.39#ibcon#flushed, iclass 36, count 2 2006.201.07:10:22.39#ibcon#about to write, iclass 36, count 2 2006.201.07:10:22.39#ibcon#wrote, iclass 36, count 2 2006.201.07:10:22.39#ibcon#about to read 3, iclass 36, count 2 2006.201.07:10:22.41#ibcon#read 3, iclass 36, count 2 2006.201.07:10:22.41#ibcon#about to read 4, iclass 36, count 2 2006.201.07:10:22.41#ibcon#read 4, iclass 36, count 2 2006.201.07:10:22.41#ibcon#about to read 5, iclass 36, count 2 2006.201.07:10:22.41#ibcon#read 5, iclass 36, count 2 2006.201.07:10:22.41#ibcon#about to read 6, iclass 36, count 2 2006.201.07:10:22.41#ibcon#read 6, iclass 36, count 2 2006.201.07:10:22.41#ibcon#end of sib2, iclass 36, count 2 2006.201.07:10:22.41#ibcon#*mode == 0, iclass 36, count 2 2006.201.07:10:22.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.07:10:22.41#ibcon#[25=AT08-04\r\n] 2006.201.07:10:22.41#ibcon#*before write, iclass 36, count 2 2006.201.07:10:22.41#ibcon#enter sib2, iclass 36, count 2 2006.201.07:10:22.41#ibcon#flushed, iclass 36, count 2 2006.201.07:10:22.41#ibcon#about to write, iclass 36, count 2 2006.201.07:10:22.41#ibcon#wrote, iclass 36, count 2 2006.201.07:10:22.41#ibcon#about to read 3, iclass 36, count 2 2006.201.07:10:22.44#ibcon#read 3, iclass 36, count 2 2006.201.07:10:22.44#ibcon#about to read 4, iclass 36, count 2 2006.201.07:10:22.44#ibcon#read 4, iclass 36, count 2 2006.201.07:10:22.44#ibcon#about to read 5, iclass 36, count 2 2006.201.07:10:22.44#ibcon#read 5, iclass 36, count 2 2006.201.07:10:22.44#ibcon#about to read 6, iclass 36, count 2 2006.201.07:10:22.44#ibcon#read 6, iclass 36, count 2 2006.201.07:10:22.44#ibcon#end of sib2, iclass 36, count 2 2006.201.07:10:22.44#ibcon#*after write, iclass 36, count 2 2006.201.07:10:22.44#ibcon#*before return 0, iclass 36, count 2 2006.201.07:10:22.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:10:22.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:10:22.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.07:10:22.44#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:22.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:10:22.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:10:22.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:10:22.56#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:10:22.56#ibcon#first serial, iclass 36, count 0 2006.201.07:10:22.56#ibcon#enter sib2, iclass 36, count 0 2006.201.07:10:22.56#ibcon#flushed, iclass 36, count 0 2006.201.07:10:22.56#ibcon#about to write, iclass 36, count 0 2006.201.07:10:22.56#ibcon#wrote, iclass 36, count 0 2006.201.07:10:22.56#ibcon#about to read 3, iclass 36, count 0 2006.201.07:10:22.58#ibcon#read 3, iclass 36, count 0 2006.201.07:10:22.58#ibcon#about to read 4, iclass 36, count 0 2006.201.07:10:22.58#ibcon#read 4, iclass 36, count 0 2006.201.07:10:22.58#ibcon#about to read 5, iclass 36, count 0 2006.201.07:10:22.58#ibcon#read 5, iclass 36, count 0 2006.201.07:10:22.58#ibcon#about to read 6, iclass 36, count 0 2006.201.07:10:22.58#ibcon#read 6, iclass 36, count 0 2006.201.07:10:22.58#ibcon#end of sib2, iclass 36, count 0 2006.201.07:10:22.58#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:10:22.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:10:22.58#ibcon#[25=USB\r\n] 2006.201.07:10:22.58#ibcon#*before write, iclass 36, count 0 2006.201.07:10:22.58#ibcon#enter sib2, iclass 36, count 0 2006.201.07:10:22.58#ibcon#flushed, iclass 36, count 0 2006.201.07:10:22.58#ibcon#about to write, iclass 36, count 0 2006.201.07:10:22.58#ibcon#wrote, iclass 36, count 0 2006.201.07:10:22.58#ibcon#about to read 3, iclass 36, count 0 2006.201.07:10:22.61#ibcon#read 3, iclass 36, count 0 2006.201.07:10:22.61#ibcon#about to read 4, iclass 36, count 0 2006.201.07:10:22.61#ibcon#read 4, iclass 36, count 0 2006.201.07:10:22.61#ibcon#about to read 5, iclass 36, count 0 2006.201.07:10:22.61#ibcon#read 5, iclass 36, count 0 2006.201.07:10:22.61#ibcon#about to read 6, iclass 36, count 0 2006.201.07:10:22.61#ibcon#read 6, iclass 36, count 0 2006.201.07:10:22.61#ibcon#end of sib2, iclass 36, count 0 2006.201.07:10:22.61#ibcon#*after write, iclass 36, count 0 2006.201.07:10:22.61#ibcon#*before return 0, iclass 36, count 0 2006.201.07:10:22.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:10:22.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:10:22.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:10:22.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:10:22.61$vck44/vblo=1,629.99 2006.201.07:10:22.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.07:10:22.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.07:10:22.61#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:22.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:10:22.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:10:22.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:10:22.61#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:10:22.61#ibcon#first serial, iclass 38, count 0 2006.201.07:10:22.61#ibcon#enter sib2, iclass 38, count 0 2006.201.07:10:22.61#ibcon#flushed, iclass 38, count 0 2006.201.07:10:22.61#ibcon#about to write, iclass 38, count 0 2006.201.07:10:22.61#ibcon#wrote, iclass 38, count 0 2006.201.07:10:22.61#ibcon#about to read 3, iclass 38, count 0 2006.201.07:10:22.63#ibcon#read 3, iclass 38, count 0 2006.201.07:10:22.63#ibcon#about to read 4, iclass 38, count 0 2006.201.07:10:22.63#ibcon#read 4, iclass 38, count 0 2006.201.07:10:22.63#ibcon#about to read 5, iclass 38, count 0 2006.201.07:10:22.63#ibcon#read 5, iclass 38, count 0 2006.201.07:10:22.63#ibcon#about to read 6, iclass 38, count 0 2006.201.07:10:22.63#ibcon#read 6, iclass 38, count 0 2006.201.07:10:22.63#ibcon#end of sib2, iclass 38, count 0 2006.201.07:10:22.63#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:10:22.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:10:22.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:10:22.63#ibcon#*before write, iclass 38, count 0 2006.201.07:10:22.63#ibcon#enter sib2, iclass 38, count 0 2006.201.07:10:22.63#ibcon#flushed, iclass 38, count 0 2006.201.07:10:22.63#ibcon#about to write, iclass 38, count 0 2006.201.07:10:22.63#ibcon#wrote, iclass 38, count 0 2006.201.07:10:22.63#ibcon#about to read 3, iclass 38, count 0 2006.201.07:10:22.67#ibcon#read 3, iclass 38, count 0 2006.201.07:10:22.67#ibcon#about to read 4, iclass 38, count 0 2006.201.07:10:22.67#ibcon#read 4, iclass 38, count 0 2006.201.07:10:22.67#ibcon#about to read 5, iclass 38, count 0 2006.201.07:10:22.67#ibcon#read 5, iclass 38, count 0 2006.201.07:10:22.67#ibcon#about to read 6, iclass 38, count 0 2006.201.07:10:22.67#ibcon#read 6, iclass 38, count 0 2006.201.07:10:22.67#ibcon#end of sib2, iclass 38, count 0 2006.201.07:10:22.67#ibcon#*after write, iclass 38, count 0 2006.201.07:10:22.67#ibcon#*before return 0, iclass 38, count 0 2006.201.07:10:22.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:10:22.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:10:22.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:10:22.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:10:22.67$vck44/vb=1,4 2006.201.07:10:22.67#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.07:10:22.67#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.07:10:22.67#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:22.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:10:22.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:10:22.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:10:22.67#ibcon#enter wrdev, iclass 40, count 2 2006.201.07:10:22.67#ibcon#first serial, iclass 40, count 2 2006.201.07:10:22.67#ibcon#enter sib2, iclass 40, count 2 2006.201.07:10:22.67#ibcon#flushed, iclass 40, count 2 2006.201.07:10:22.67#ibcon#about to write, iclass 40, count 2 2006.201.07:10:22.67#ibcon#wrote, iclass 40, count 2 2006.201.07:10:22.67#ibcon#about to read 3, iclass 40, count 2 2006.201.07:10:22.69#ibcon#read 3, iclass 40, count 2 2006.201.07:10:22.69#ibcon#about to read 4, iclass 40, count 2 2006.201.07:10:22.69#ibcon#read 4, iclass 40, count 2 2006.201.07:10:22.69#ibcon#about to read 5, iclass 40, count 2 2006.201.07:10:22.69#ibcon#read 5, iclass 40, count 2 2006.201.07:10:22.69#ibcon#about to read 6, iclass 40, count 2 2006.201.07:10:22.69#ibcon#read 6, iclass 40, count 2 2006.201.07:10:22.69#ibcon#end of sib2, iclass 40, count 2 2006.201.07:10:22.69#ibcon#*mode == 0, iclass 40, count 2 2006.201.07:10:22.69#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.07:10:22.69#ibcon#[27=AT01-04\r\n] 2006.201.07:10:22.69#ibcon#*before write, iclass 40, count 2 2006.201.07:10:22.69#ibcon#enter sib2, iclass 40, count 2 2006.201.07:10:22.69#ibcon#flushed, iclass 40, count 2 2006.201.07:10:22.69#ibcon#about to write, iclass 40, count 2 2006.201.07:10:22.69#ibcon#wrote, iclass 40, count 2 2006.201.07:10:22.69#ibcon#about to read 3, iclass 40, count 2 2006.201.07:10:22.72#ibcon#read 3, iclass 40, count 2 2006.201.07:10:22.72#ibcon#about to read 4, iclass 40, count 2 2006.201.07:10:22.72#ibcon#read 4, iclass 40, count 2 2006.201.07:10:22.72#ibcon#about to read 5, iclass 40, count 2 2006.201.07:10:22.72#ibcon#read 5, iclass 40, count 2 2006.201.07:10:22.72#ibcon#about to read 6, iclass 40, count 2 2006.201.07:10:22.72#ibcon#read 6, iclass 40, count 2 2006.201.07:10:22.72#ibcon#end of sib2, iclass 40, count 2 2006.201.07:10:22.72#ibcon#*after write, iclass 40, count 2 2006.201.07:10:22.72#ibcon#*before return 0, iclass 40, count 2 2006.201.07:10:22.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:10:22.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:10:22.72#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.07:10:22.72#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:22.72#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:10:22.84#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:10:22.84#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:10:22.84#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:10:22.84#ibcon#first serial, iclass 40, count 0 2006.201.07:10:22.84#ibcon#enter sib2, iclass 40, count 0 2006.201.07:10:22.84#ibcon#flushed, iclass 40, count 0 2006.201.07:10:22.84#ibcon#about to write, iclass 40, count 0 2006.201.07:10:22.84#ibcon#wrote, iclass 40, count 0 2006.201.07:10:22.84#ibcon#about to read 3, iclass 40, count 0 2006.201.07:10:22.86#ibcon#read 3, iclass 40, count 0 2006.201.07:10:22.86#ibcon#about to read 4, iclass 40, count 0 2006.201.07:10:22.86#ibcon#read 4, iclass 40, count 0 2006.201.07:10:22.86#ibcon#about to read 5, iclass 40, count 0 2006.201.07:10:22.86#ibcon#read 5, iclass 40, count 0 2006.201.07:10:22.86#ibcon#about to read 6, iclass 40, count 0 2006.201.07:10:22.86#ibcon#read 6, iclass 40, count 0 2006.201.07:10:22.86#ibcon#end of sib2, iclass 40, count 0 2006.201.07:10:22.86#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:10:22.86#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:10:22.86#ibcon#[27=USB\r\n] 2006.201.07:10:22.86#ibcon#*before write, iclass 40, count 0 2006.201.07:10:22.86#ibcon#enter sib2, iclass 40, count 0 2006.201.07:10:22.86#ibcon#flushed, iclass 40, count 0 2006.201.07:10:22.86#ibcon#about to write, iclass 40, count 0 2006.201.07:10:22.86#ibcon#wrote, iclass 40, count 0 2006.201.07:10:22.86#ibcon#about to read 3, iclass 40, count 0 2006.201.07:10:22.89#ibcon#read 3, iclass 40, count 0 2006.201.07:10:22.89#ibcon#about to read 4, iclass 40, count 0 2006.201.07:10:22.89#ibcon#read 4, iclass 40, count 0 2006.201.07:10:22.89#ibcon#about to read 5, iclass 40, count 0 2006.201.07:10:22.89#ibcon#read 5, iclass 40, count 0 2006.201.07:10:22.89#ibcon#about to read 6, iclass 40, count 0 2006.201.07:10:22.89#ibcon#read 6, iclass 40, count 0 2006.201.07:10:22.89#ibcon#end of sib2, iclass 40, count 0 2006.201.07:10:22.89#ibcon#*after write, iclass 40, count 0 2006.201.07:10:22.89#ibcon#*before return 0, iclass 40, count 0 2006.201.07:10:22.89#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:10:22.89#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:10:22.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:10:22.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:10:22.89$vck44/vblo=2,634.99 2006.201.07:10:22.89#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.07:10:22.89#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.07:10:22.89#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:22.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:22.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:22.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:22.89#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:10:22.89#ibcon#first serial, iclass 4, count 0 2006.201.07:10:22.89#ibcon#enter sib2, iclass 4, count 0 2006.201.07:10:22.89#ibcon#flushed, iclass 4, count 0 2006.201.07:10:22.89#ibcon#about to write, iclass 4, count 0 2006.201.07:10:22.89#ibcon#wrote, iclass 4, count 0 2006.201.07:10:22.89#ibcon#about to read 3, iclass 4, count 0 2006.201.07:10:22.91#ibcon#read 3, iclass 4, count 0 2006.201.07:10:22.91#ibcon#about to read 4, iclass 4, count 0 2006.201.07:10:22.91#ibcon#read 4, iclass 4, count 0 2006.201.07:10:22.91#ibcon#about to read 5, iclass 4, count 0 2006.201.07:10:22.91#ibcon#read 5, iclass 4, count 0 2006.201.07:10:22.91#ibcon#about to read 6, iclass 4, count 0 2006.201.07:10:22.91#ibcon#read 6, iclass 4, count 0 2006.201.07:10:22.91#ibcon#end of sib2, iclass 4, count 0 2006.201.07:10:22.91#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:10:22.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:10:22.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:10:22.91#ibcon#*before write, iclass 4, count 0 2006.201.07:10:22.91#ibcon#enter sib2, iclass 4, count 0 2006.201.07:10:22.91#ibcon#flushed, iclass 4, count 0 2006.201.07:10:22.91#ibcon#about to write, iclass 4, count 0 2006.201.07:10:22.91#ibcon#wrote, iclass 4, count 0 2006.201.07:10:22.91#ibcon#about to read 3, iclass 4, count 0 2006.201.07:10:22.95#ibcon#read 3, iclass 4, count 0 2006.201.07:10:22.95#ibcon#about to read 4, iclass 4, count 0 2006.201.07:10:22.95#ibcon#read 4, iclass 4, count 0 2006.201.07:10:22.95#ibcon#about to read 5, iclass 4, count 0 2006.201.07:10:22.95#ibcon#read 5, iclass 4, count 0 2006.201.07:10:22.95#ibcon#about to read 6, iclass 4, count 0 2006.201.07:10:22.95#ibcon#read 6, iclass 4, count 0 2006.201.07:10:22.95#ibcon#end of sib2, iclass 4, count 0 2006.201.07:10:22.95#ibcon#*after write, iclass 4, count 0 2006.201.07:10:22.95#ibcon#*before return 0, iclass 4, count 0 2006.201.07:10:22.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:22.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:10:22.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:10:22.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:10:22.95$vck44/vb=2,5 2006.201.07:10:22.95#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.07:10:22.95#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.07:10:22.95#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:22.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:23.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:23.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:23.01#ibcon#enter wrdev, iclass 6, count 2 2006.201.07:10:23.01#ibcon#first serial, iclass 6, count 2 2006.201.07:10:23.01#ibcon#enter sib2, iclass 6, count 2 2006.201.07:10:23.01#ibcon#flushed, iclass 6, count 2 2006.201.07:10:23.01#ibcon#about to write, iclass 6, count 2 2006.201.07:10:23.01#ibcon#wrote, iclass 6, count 2 2006.201.07:10:23.01#ibcon#about to read 3, iclass 6, count 2 2006.201.07:10:23.03#ibcon#read 3, iclass 6, count 2 2006.201.07:10:23.03#ibcon#about to read 4, iclass 6, count 2 2006.201.07:10:23.03#ibcon#read 4, iclass 6, count 2 2006.201.07:10:23.03#ibcon#about to read 5, iclass 6, count 2 2006.201.07:10:23.03#ibcon#read 5, iclass 6, count 2 2006.201.07:10:23.03#ibcon#about to read 6, iclass 6, count 2 2006.201.07:10:23.03#ibcon#read 6, iclass 6, count 2 2006.201.07:10:23.03#ibcon#end of sib2, iclass 6, count 2 2006.201.07:10:23.03#ibcon#*mode == 0, iclass 6, count 2 2006.201.07:10:23.03#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.07:10:23.03#ibcon#[27=AT02-05\r\n] 2006.201.07:10:23.03#ibcon#*before write, iclass 6, count 2 2006.201.07:10:23.03#ibcon#enter sib2, iclass 6, count 2 2006.201.07:10:23.03#ibcon#flushed, iclass 6, count 2 2006.201.07:10:23.03#ibcon#about to write, iclass 6, count 2 2006.201.07:10:23.03#ibcon#wrote, iclass 6, count 2 2006.201.07:10:23.03#ibcon#about to read 3, iclass 6, count 2 2006.201.07:10:23.06#ibcon#read 3, iclass 6, count 2 2006.201.07:10:23.06#ibcon#about to read 4, iclass 6, count 2 2006.201.07:10:23.06#ibcon#read 4, iclass 6, count 2 2006.201.07:10:23.06#ibcon#about to read 5, iclass 6, count 2 2006.201.07:10:23.06#ibcon#read 5, iclass 6, count 2 2006.201.07:10:23.06#ibcon#about to read 6, iclass 6, count 2 2006.201.07:10:23.06#ibcon#read 6, iclass 6, count 2 2006.201.07:10:23.06#ibcon#end of sib2, iclass 6, count 2 2006.201.07:10:23.06#ibcon#*after write, iclass 6, count 2 2006.201.07:10:23.06#ibcon#*before return 0, iclass 6, count 2 2006.201.07:10:23.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:23.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:10:23.06#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.07:10:23.06#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:23.06#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:23.18#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:23.18#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:23.18#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:10:23.18#ibcon#first serial, iclass 6, count 0 2006.201.07:10:23.18#ibcon#enter sib2, iclass 6, count 0 2006.201.07:10:23.18#ibcon#flushed, iclass 6, count 0 2006.201.07:10:23.18#ibcon#about to write, iclass 6, count 0 2006.201.07:10:23.18#ibcon#wrote, iclass 6, count 0 2006.201.07:10:23.18#ibcon#about to read 3, iclass 6, count 0 2006.201.07:10:23.20#ibcon#read 3, iclass 6, count 0 2006.201.07:10:23.20#ibcon#about to read 4, iclass 6, count 0 2006.201.07:10:23.20#ibcon#read 4, iclass 6, count 0 2006.201.07:10:23.20#ibcon#about to read 5, iclass 6, count 0 2006.201.07:10:23.20#ibcon#read 5, iclass 6, count 0 2006.201.07:10:23.20#ibcon#about to read 6, iclass 6, count 0 2006.201.07:10:23.20#ibcon#read 6, iclass 6, count 0 2006.201.07:10:23.20#ibcon#end of sib2, iclass 6, count 0 2006.201.07:10:23.20#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:10:23.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:10:23.20#ibcon#[27=USB\r\n] 2006.201.07:10:23.20#ibcon#*before write, iclass 6, count 0 2006.201.07:10:23.20#ibcon#enter sib2, iclass 6, count 0 2006.201.07:10:23.20#ibcon#flushed, iclass 6, count 0 2006.201.07:10:23.20#ibcon#about to write, iclass 6, count 0 2006.201.07:10:23.20#ibcon#wrote, iclass 6, count 0 2006.201.07:10:23.20#ibcon#about to read 3, iclass 6, count 0 2006.201.07:10:23.23#ibcon#read 3, iclass 6, count 0 2006.201.07:10:23.23#ibcon#about to read 4, iclass 6, count 0 2006.201.07:10:23.23#ibcon#read 4, iclass 6, count 0 2006.201.07:10:23.23#ibcon#about to read 5, iclass 6, count 0 2006.201.07:10:23.23#ibcon#read 5, iclass 6, count 0 2006.201.07:10:23.23#ibcon#about to read 6, iclass 6, count 0 2006.201.07:10:23.23#ibcon#read 6, iclass 6, count 0 2006.201.07:10:23.23#ibcon#end of sib2, iclass 6, count 0 2006.201.07:10:23.23#ibcon#*after write, iclass 6, count 0 2006.201.07:10:23.23#ibcon#*before return 0, iclass 6, count 0 2006.201.07:10:23.23#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:23.23#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:10:23.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:10:23.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:10:23.23$vck44/vblo=3,649.99 2006.201.07:10:23.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.07:10:23.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.07:10:23.23#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:23.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:23.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:23.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:23.23#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:10:23.23#ibcon#first serial, iclass 10, count 0 2006.201.07:10:23.23#ibcon#enter sib2, iclass 10, count 0 2006.201.07:10:23.23#ibcon#flushed, iclass 10, count 0 2006.201.07:10:23.23#ibcon#about to write, iclass 10, count 0 2006.201.07:10:23.23#ibcon#wrote, iclass 10, count 0 2006.201.07:10:23.23#ibcon#about to read 3, iclass 10, count 0 2006.201.07:10:23.25#ibcon#read 3, iclass 10, count 0 2006.201.07:10:23.25#ibcon#about to read 4, iclass 10, count 0 2006.201.07:10:23.25#ibcon#read 4, iclass 10, count 0 2006.201.07:10:23.25#ibcon#about to read 5, iclass 10, count 0 2006.201.07:10:23.25#ibcon#read 5, iclass 10, count 0 2006.201.07:10:23.25#ibcon#about to read 6, iclass 10, count 0 2006.201.07:10:23.25#ibcon#read 6, iclass 10, count 0 2006.201.07:10:23.25#ibcon#end of sib2, iclass 10, count 0 2006.201.07:10:23.25#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:10:23.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:10:23.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:10:23.25#ibcon#*before write, iclass 10, count 0 2006.201.07:10:23.25#ibcon#enter sib2, iclass 10, count 0 2006.201.07:10:23.25#ibcon#flushed, iclass 10, count 0 2006.201.07:10:23.25#ibcon#about to write, iclass 10, count 0 2006.201.07:10:23.25#ibcon#wrote, iclass 10, count 0 2006.201.07:10:23.25#ibcon#about to read 3, iclass 10, count 0 2006.201.07:10:23.30#ibcon#read 3, iclass 10, count 0 2006.201.07:10:23.30#ibcon#about to read 4, iclass 10, count 0 2006.201.07:10:23.30#ibcon#read 4, iclass 10, count 0 2006.201.07:10:23.30#ibcon#about to read 5, iclass 10, count 0 2006.201.07:10:23.30#ibcon#read 5, iclass 10, count 0 2006.201.07:10:23.30#ibcon#about to read 6, iclass 10, count 0 2006.201.07:10:23.30#ibcon#read 6, iclass 10, count 0 2006.201.07:10:23.30#ibcon#end of sib2, iclass 10, count 0 2006.201.07:10:23.30#ibcon#*after write, iclass 10, count 0 2006.201.07:10:23.30#ibcon#*before return 0, iclass 10, count 0 2006.201.07:10:23.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:23.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:10:23.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:10:23.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:10:23.30$vck44/vb=3,4 2006.201.07:10:23.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.07:10:23.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.07:10:23.30#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:23.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:23.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:23.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:23.35#ibcon#enter wrdev, iclass 12, count 2 2006.201.07:10:23.35#ibcon#first serial, iclass 12, count 2 2006.201.07:10:23.35#ibcon#enter sib2, iclass 12, count 2 2006.201.07:10:23.35#ibcon#flushed, iclass 12, count 2 2006.201.07:10:23.35#ibcon#about to write, iclass 12, count 2 2006.201.07:10:23.35#ibcon#wrote, iclass 12, count 2 2006.201.07:10:23.35#ibcon#about to read 3, iclass 12, count 2 2006.201.07:10:23.37#ibcon#read 3, iclass 12, count 2 2006.201.07:10:23.37#ibcon#about to read 4, iclass 12, count 2 2006.201.07:10:23.37#ibcon#read 4, iclass 12, count 2 2006.201.07:10:23.37#ibcon#about to read 5, iclass 12, count 2 2006.201.07:10:23.37#ibcon#read 5, iclass 12, count 2 2006.201.07:10:23.37#ibcon#about to read 6, iclass 12, count 2 2006.201.07:10:23.37#ibcon#read 6, iclass 12, count 2 2006.201.07:10:23.37#ibcon#end of sib2, iclass 12, count 2 2006.201.07:10:23.37#ibcon#*mode == 0, iclass 12, count 2 2006.201.07:10:23.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.07:10:23.37#ibcon#[27=AT03-04\r\n] 2006.201.07:10:23.37#ibcon#*before write, iclass 12, count 2 2006.201.07:10:23.37#ibcon#enter sib2, iclass 12, count 2 2006.201.07:10:23.37#ibcon#flushed, iclass 12, count 2 2006.201.07:10:23.37#ibcon#about to write, iclass 12, count 2 2006.201.07:10:23.37#ibcon#wrote, iclass 12, count 2 2006.201.07:10:23.37#ibcon#about to read 3, iclass 12, count 2 2006.201.07:10:23.40#ibcon#read 3, iclass 12, count 2 2006.201.07:10:23.40#ibcon#about to read 4, iclass 12, count 2 2006.201.07:10:23.40#ibcon#read 4, iclass 12, count 2 2006.201.07:10:23.40#ibcon#about to read 5, iclass 12, count 2 2006.201.07:10:23.40#ibcon#read 5, iclass 12, count 2 2006.201.07:10:23.40#ibcon#about to read 6, iclass 12, count 2 2006.201.07:10:23.40#ibcon#read 6, iclass 12, count 2 2006.201.07:10:23.40#ibcon#end of sib2, iclass 12, count 2 2006.201.07:10:23.40#ibcon#*after write, iclass 12, count 2 2006.201.07:10:23.40#ibcon#*before return 0, iclass 12, count 2 2006.201.07:10:23.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:23.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:10:23.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.07:10:23.40#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:23.40#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:23.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:23.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:23.52#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:10:23.52#ibcon#first serial, iclass 12, count 0 2006.201.07:10:23.52#ibcon#enter sib2, iclass 12, count 0 2006.201.07:10:23.52#ibcon#flushed, iclass 12, count 0 2006.201.07:10:23.52#ibcon#about to write, iclass 12, count 0 2006.201.07:10:23.52#ibcon#wrote, iclass 12, count 0 2006.201.07:10:23.52#ibcon#about to read 3, iclass 12, count 0 2006.201.07:10:23.54#ibcon#read 3, iclass 12, count 0 2006.201.07:10:23.54#ibcon#about to read 4, iclass 12, count 0 2006.201.07:10:23.54#ibcon#read 4, iclass 12, count 0 2006.201.07:10:23.54#ibcon#about to read 5, iclass 12, count 0 2006.201.07:10:23.54#ibcon#read 5, iclass 12, count 0 2006.201.07:10:23.54#ibcon#about to read 6, iclass 12, count 0 2006.201.07:10:23.54#ibcon#read 6, iclass 12, count 0 2006.201.07:10:23.54#ibcon#end of sib2, iclass 12, count 0 2006.201.07:10:23.54#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:10:23.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:10:23.54#ibcon#[27=USB\r\n] 2006.201.07:10:23.54#ibcon#*before write, iclass 12, count 0 2006.201.07:10:23.54#ibcon#enter sib2, iclass 12, count 0 2006.201.07:10:23.54#ibcon#flushed, iclass 12, count 0 2006.201.07:10:23.54#ibcon#about to write, iclass 12, count 0 2006.201.07:10:23.54#ibcon#wrote, iclass 12, count 0 2006.201.07:10:23.54#ibcon#about to read 3, iclass 12, count 0 2006.201.07:10:23.57#ibcon#read 3, iclass 12, count 0 2006.201.07:10:23.57#ibcon#about to read 4, iclass 12, count 0 2006.201.07:10:23.57#ibcon#read 4, iclass 12, count 0 2006.201.07:10:23.57#ibcon#about to read 5, iclass 12, count 0 2006.201.07:10:23.57#ibcon#read 5, iclass 12, count 0 2006.201.07:10:23.57#ibcon#about to read 6, iclass 12, count 0 2006.201.07:10:23.57#ibcon#read 6, iclass 12, count 0 2006.201.07:10:23.57#ibcon#end of sib2, iclass 12, count 0 2006.201.07:10:23.57#ibcon#*after write, iclass 12, count 0 2006.201.07:10:23.57#ibcon#*before return 0, iclass 12, count 0 2006.201.07:10:23.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:23.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:10:23.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:10:23.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:10:23.57$vck44/vblo=4,679.99 2006.201.07:10:23.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.07:10:23.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.07:10:23.57#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:23.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:23.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:23.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:23.57#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:10:23.57#ibcon#first serial, iclass 14, count 0 2006.201.07:10:23.57#ibcon#enter sib2, iclass 14, count 0 2006.201.07:10:23.57#ibcon#flushed, iclass 14, count 0 2006.201.07:10:23.57#ibcon#about to write, iclass 14, count 0 2006.201.07:10:23.57#ibcon#wrote, iclass 14, count 0 2006.201.07:10:23.57#ibcon#about to read 3, iclass 14, count 0 2006.201.07:10:23.59#ibcon#read 3, iclass 14, count 0 2006.201.07:10:23.59#ibcon#about to read 4, iclass 14, count 0 2006.201.07:10:23.59#ibcon#read 4, iclass 14, count 0 2006.201.07:10:23.59#ibcon#about to read 5, iclass 14, count 0 2006.201.07:10:23.59#ibcon#read 5, iclass 14, count 0 2006.201.07:10:23.59#ibcon#about to read 6, iclass 14, count 0 2006.201.07:10:23.59#ibcon#read 6, iclass 14, count 0 2006.201.07:10:23.59#ibcon#end of sib2, iclass 14, count 0 2006.201.07:10:23.59#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:10:23.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:10:23.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:10:23.59#ibcon#*before write, iclass 14, count 0 2006.201.07:10:23.59#ibcon#enter sib2, iclass 14, count 0 2006.201.07:10:23.59#ibcon#flushed, iclass 14, count 0 2006.201.07:10:23.59#ibcon#about to write, iclass 14, count 0 2006.201.07:10:23.59#ibcon#wrote, iclass 14, count 0 2006.201.07:10:23.59#ibcon#about to read 3, iclass 14, count 0 2006.201.07:10:23.63#ibcon#read 3, iclass 14, count 0 2006.201.07:10:23.63#ibcon#about to read 4, iclass 14, count 0 2006.201.07:10:23.63#ibcon#read 4, iclass 14, count 0 2006.201.07:10:23.63#ibcon#about to read 5, iclass 14, count 0 2006.201.07:10:23.63#ibcon#read 5, iclass 14, count 0 2006.201.07:10:23.63#ibcon#about to read 6, iclass 14, count 0 2006.201.07:10:23.63#ibcon#read 6, iclass 14, count 0 2006.201.07:10:23.63#ibcon#end of sib2, iclass 14, count 0 2006.201.07:10:23.63#ibcon#*after write, iclass 14, count 0 2006.201.07:10:23.63#ibcon#*before return 0, iclass 14, count 0 2006.201.07:10:23.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:23.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:10:23.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:10:23.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:10:23.63$vck44/vb=4,5 2006.201.07:10:23.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.07:10:23.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.07:10:23.63#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:23.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:23.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:23.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:23.69#ibcon#enter wrdev, iclass 16, count 2 2006.201.07:10:23.69#ibcon#first serial, iclass 16, count 2 2006.201.07:10:23.69#ibcon#enter sib2, iclass 16, count 2 2006.201.07:10:23.69#ibcon#flushed, iclass 16, count 2 2006.201.07:10:23.69#ibcon#about to write, iclass 16, count 2 2006.201.07:10:23.69#ibcon#wrote, iclass 16, count 2 2006.201.07:10:23.69#ibcon#about to read 3, iclass 16, count 2 2006.201.07:10:23.71#ibcon#read 3, iclass 16, count 2 2006.201.07:10:23.71#ibcon#about to read 4, iclass 16, count 2 2006.201.07:10:23.71#ibcon#read 4, iclass 16, count 2 2006.201.07:10:23.71#ibcon#about to read 5, iclass 16, count 2 2006.201.07:10:23.71#ibcon#read 5, iclass 16, count 2 2006.201.07:10:23.71#ibcon#about to read 6, iclass 16, count 2 2006.201.07:10:23.71#ibcon#read 6, iclass 16, count 2 2006.201.07:10:23.71#ibcon#end of sib2, iclass 16, count 2 2006.201.07:10:23.71#ibcon#*mode == 0, iclass 16, count 2 2006.201.07:10:23.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.07:10:23.71#ibcon#[27=AT04-05\r\n] 2006.201.07:10:23.71#ibcon#*before write, iclass 16, count 2 2006.201.07:10:23.71#ibcon#enter sib2, iclass 16, count 2 2006.201.07:10:23.71#ibcon#flushed, iclass 16, count 2 2006.201.07:10:23.71#ibcon#about to write, iclass 16, count 2 2006.201.07:10:23.71#ibcon#wrote, iclass 16, count 2 2006.201.07:10:23.71#ibcon#about to read 3, iclass 16, count 2 2006.201.07:10:23.74#ibcon#read 3, iclass 16, count 2 2006.201.07:10:23.74#ibcon#about to read 4, iclass 16, count 2 2006.201.07:10:23.74#ibcon#read 4, iclass 16, count 2 2006.201.07:10:23.74#ibcon#about to read 5, iclass 16, count 2 2006.201.07:10:23.74#ibcon#read 5, iclass 16, count 2 2006.201.07:10:23.74#ibcon#about to read 6, iclass 16, count 2 2006.201.07:10:23.74#ibcon#read 6, iclass 16, count 2 2006.201.07:10:23.74#ibcon#end of sib2, iclass 16, count 2 2006.201.07:10:23.74#ibcon#*after write, iclass 16, count 2 2006.201.07:10:23.74#ibcon#*before return 0, iclass 16, count 2 2006.201.07:10:23.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:23.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:10:23.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.07:10:23.74#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:23.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:23.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:23.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:23.86#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:10:23.86#ibcon#first serial, iclass 16, count 0 2006.201.07:10:23.86#ibcon#enter sib2, iclass 16, count 0 2006.201.07:10:23.86#ibcon#flushed, iclass 16, count 0 2006.201.07:10:23.86#ibcon#about to write, iclass 16, count 0 2006.201.07:10:23.86#ibcon#wrote, iclass 16, count 0 2006.201.07:10:23.86#ibcon#about to read 3, iclass 16, count 0 2006.201.07:10:23.88#ibcon#read 3, iclass 16, count 0 2006.201.07:10:23.88#ibcon#about to read 4, iclass 16, count 0 2006.201.07:10:23.88#ibcon#read 4, iclass 16, count 0 2006.201.07:10:23.88#ibcon#about to read 5, iclass 16, count 0 2006.201.07:10:23.88#ibcon#read 5, iclass 16, count 0 2006.201.07:10:23.88#ibcon#about to read 6, iclass 16, count 0 2006.201.07:10:23.88#ibcon#read 6, iclass 16, count 0 2006.201.07:10:23.88#ibcon#end of sib2, iclass 16, count 0 2006.201.07:10:23.88#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:10:23.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:10:23.88#ibcon#[27=USB\r\n] 2006.201.07:10:23.88#ibcon#*before write, iclass 16, count 0 2006.201.07:10:23.88#ibcon#enter sib2, iclass 16, count 0 2006.201.07:10:23.88#ibcon#flushed, iclass 16, count 0 2006.201.07:10:23.88#ibcon#about to write, iclass 16, count 0 2006.201.07:10:23.88#ibcon#wrote, iclass 16, count 0 2006.201.07:10:23.88#ibcon#about to read 3, iclass 16, count 0 2006.201.07:10:23.91#ibcon#read 3, iclass 16, count 0 2006.201.07:10:23.91#ibcon#about to read 4, iclass 16, count 0 2006.201.07:10:23.91#ibcon#read 4, iclass 16, count 0 2006.201.07:10:23.91#ibcon#about to read 5, iclass 16, count 0 2006.201.07:10:23.91#ibcon#read 5, iclass 16, count 0 2006.201.07:10:23.91#ibcon#about to read 6, iclass 16, count 0 2006.201.07:10:23.91#ibcon#read 6, iclass 16, count 0 2006.201.07:10:23.91#ibcon#end of sib2, iclass 16, count 0 2006.201.07:10:23.91#ibcon#*after write, iclass 16, count 0 2006.201.07:10:23.91#ibcon#*before return 0, iclass 16, count 0 2006.201.07:10:23.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:23.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:10:23.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:10:23.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:10:23.91$vck44/vblo=5,709.99 2006.201.07:10:23.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.07:10:23.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.07:10:23.91#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:23.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:23.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:23.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:23.91#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:10:23.91#ibcon#first serial, iclass 18, count 0 2006.201.07:10:23.91#ibcon#enter sib2, iclass 18, count 0 2006.201.07:10:23.91#ibcon#flushed, iclass 18, count 0 2006.201.07:10:23.91#ibcon#about to write, iclass 18, count 0 2006.201.07:10:23.91#ibcon#wrote, iclass 18, count 0 2006.201.07:10:23.91#ibcon#about to read 3, iclass 18, count 0 2006.201.07:10:23.93#ibcon#read 3, iclass 18, count 0 2006.201.07:10:23.93#ibcon#about to read 4, iclass 18, count 0 2006.201.07:10:23.93#ibcon#read 4, iclass 18, count 0 2006.201.07:10:23.93#ibcon#about to read 5, iclass 18, count 0 2006.201.07:10:23.93#ibcon#read 5, iclass 18, count 0 2006.201.07:10:23.93#ibcon#about to read 6, iclass 18, count 0 2006.201.07:10:23.93#ibcon#read 6, iclass 18, count 0 2006.201.07:10:23.93#ibcon#end of sib2, iclass 18, count 0 2006.201.07:10:23.93#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:10:23.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:10:23.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:10:23.93#ibcon#*before write, iclass 18, count 0 2006.201.07:10:23.93#ibcon#enter sib2, iclass 18, count 0 2006.201.07:10:23.93#ibcon#flushed, iclass 18, count 0 2006.201.07:10:23.93#ibcon#about to write, iclass 18, count 0 2006.201.07:10:23.93#ibcon#wrote, iclass 18, count 0 2006.201.07:10:23.93#ibcon#about to read 3, iclass 18, count 0 2006.201.07:10:23.98#ibcon#read 3, iclass 18, count 0 2006.201.07:10:23.98#ibcon#about to read 4, iclass 18, count 0 2006.201.07:10:23.98#ibcon#read 4, iclass 18, count 0 2006.201.07:10:23.98#ibcon#about to read 5, iclass 18, count 0 2006.201.07:10:23.98#ibcon#read 5, iclass 18, count 0 2006.201.07:10:23.98#ibcon#about to read 6, iclass 18, count 0 2006.201.07:10:23.98#ibcon#read 6, iclass 18, count 0 2006.201.07:10:23.98#ibcon#end of sib2, iclass 18, count 0 2006.201.07:10:23.98#ibcon#*after write, iclass 18, count 0 2006.201.07:10:23.98#ibcon#*before return 0, iclass 18, count 0 2006.201.07:10:23.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:23.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:10:23.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:10:23.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:10:23.98$vck44/vb=5,4 2006.201.07:10:23.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.07:10:23.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.07:10:23.98#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:23.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:24.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:24.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:24.03#ibcon#enter wrdev, iclass 20, count 2 2006.201.07:10:24.03#ibcon#first serial, iclass 20, count 2 2006.201.07:10:24.03#ibcon#enter sib2, iclass 20, count 2 2006.201.07:10:24.03#ibcon#flushed, iclass 20, count 2 2006.201.07:10:24.03#ibcon#about to write, iclass 20, count 2 2006.201.07:10:24.03#ibcon#wrote, iclass 20, count 2 2006.201.07:10:24.03#ibcon#about to read 3, iclass 20, count 2 2006.201.07:10:24.05#ibcon#read 3, iclass 20, count 2 2006.201.07:10:24.05#ibcon#about to read 4, iclass 20, count 2 2006.201.07:10:24.05#ibcon#read 4, iclass 20, count 2 2006.201.07:10:24.05#ibcon#about to read 5, iclass 20, count 2 2006.201.07:10:24.05#ibcon#read 5, iclass 20, count 2 2006.201.07:10:24.05#ibcon#about to read 6, iclass 20, count 2 2006.201.07:10:24.05#ibcon#read 6, iclass 20, count 2 2006.201.07:10:24.05#ibcon#end of sib2, iclass 20, count 2 2006.201.07:10:24.05#ibcon#*mode == 0, iclass 20, count 2 2006.201.07:10:24.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.07:10:24.05#ibcon#[27=AT05-04\r\n] 2006.201.07:10:24.05#ibcon#*before write, iclass 20, count 2 2006.201.07:10:24.05#ibcon#enter sib2, iclass 20, count 2 2006.201.07:10:24.05#ibcon#flushed, iclass 20, count 2 2006.201.07:10:24.05#ibcon#about to write, iclass 20, count 2 2006.201.07:10:24.05#ibcon#wrote, iclass 20, count 2 2006.201.07:10:24.05#ibcon#about to read 3, iclass 20, count 2 2006.201.07:10:24.08#ibcon#read 3, iclass 20, count 2 2006.201.07:10:24.08#ibcon#about to read 4, iclass 20, count 2 2006.201.07:10:24.08#ibcon#read 4, iclass 20, count 2 2006.201.07:10:24.08#ibcon#about to read 5, iclass 20, count 2 2006.201.07:10:24.08#ibcon#read 5, iclass 20, count 2 2006.201.07:10:24.08#ibcon#about to read 6, iclass 20, count 2 2006.201.07:10:24.08#ibcon#read 6, iclass 20, count 2 2006.201.07:10:24.08#ibcon#end of sib2, iclass 20, count 2 2006.201.07:10:24.08#ibcon#*after write, iclass 20, count 2 2006.201.07:10:24.08#ibcon#*before return 0, iclass 20, count 2 2006.201.07:10:24.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:24.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:10:24.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.07:10:24.08#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:24.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:24.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:24.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:24.20#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:10:24.20#ibcon#first serial, iclass 20, count 0 2006.201.07:10:24.20#ibcon#enter sib2, iclass 20, count 0 2006.201.07:10:24.20#ibcon#flushed, iclass 20, count 0 2006.201.07:10:24.20#ibcon#about to write, iclass 20, count 0 2006.201.07:10:24.20#ibcon#wrote, iclass 20, count 0 2006.201.07:10:24.20#ibcon#about to read 3, iclass 20, count 0 2006.201.07:10:24.23#ibcon#read 3, iclass 20, count 0 2006.201.07:10:24.23#ibcon#about to read 4, iclass 20, count 0 2006.201.07:10:24.23#ibcon#read 4, iclass 20, count 0 2006.201.07:10:24.23#ibcon#about to read 5, iclass 20, count 0 2006.201.07:10:24.23#ibcon#read 5, iclass 20, count 0 2006.201.07:10:24.23#ibcon#about to read 6, iclass 20, count 0 2006.201.07:10:24.23#ibcon#read 6, iclass 20, count 0 2006.201.07:10:24.23#ibcon#end of sib2, iclass 20, count 0 2006.201.07:10:24.23#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:10:24.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:10:24.23#ibcon#[27=USB\r\n] 2006.201.07:10:24.23#ibcon#*before write, iclass 20, count 0 2006.201.07:10:24.23#ibcon#enter sib2, iclass 20, count 0 2006.201.07:10:24.23#ibcon#flushed, iclass 20, count 0 2006.201.07:10:24.23#ibcon#about to write, iclass 20, count 0 2006.201.07:10:24.23#ibcon#wrote, iclass 20, count 0 2006.201.07:10:24.23#ibcon#about to read 3, iclass 20, count 0 2006.201.07:10:24.26#ibcon#read 3, iclass 20, count 0 2006.201.07:10:24.26#ibcon#about to read 4, iclass 20, count 0 2006.201.07:10:24.26#ibcon#read 4, iclass 20, count 0 2006.201.07:10:24.26#ibcon#about to read 5, iclass 20, count 0 2006.201.07:10:24.26#ibcon#read 5, iclass 20, count 0 2006.201.07:10:24.26#ibcon#about to read 6, iclass 20, count 0 2006.201.07:10:24.26#ibcon#read 6, iclass 20, count 0 2006.201.07:10:24.26#ibcon#end of sib2, iclass 20, count 0 2006.201.07:10:24.26#ibcon#*after write, iclass 20, count 0 2006.201.07:10:24.26#ibcon#*before return 0, iclass 20, count 0 2006.201.07:10:24.26#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:24.26#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:10:24.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:10:24.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:10:24.26$vck44/vblo=6,719.99 2006.201.07:10:24.26#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.07:10:24.26#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.07:10:24.26#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:24.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:24.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:24.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:24.26#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:10:24.26#ibcon#first serial, iclass 22, count 0 2006.201.07:10:24.26#ibcon#enter sib2, iclass 22, count 0 2006.201.07:10:24.26#ibcon#flushed, iclass 22, count 0 2006.201.07:10:24.26#ibcon#about to write, iclass 22, count 0 2006.201.07:10:24.26#ibcon#wrote, iclass 22, count 0 2006.201.07:10:24.26#ibcon#about to read 3, iclass 22, count 0 2006.201.07:10:24.28#ibcon#read 3, iclass 22, count 0 2006.201.07:10:24.28#ibcon#about to read 4, iclass 22, count 0 2006.201.07:10:24.28#ibcon#read 4, iclass 22, count 0 2006.201.07:10:24.28#ibcon#about to read 5, iclass 22, count 0 2006.201.07:10:24.28#ibcon#read 5, iclass 22, count 0 2006.201.07:10:24.28#ibcon#about to read 6, iclass 22, count 0 2006.201.07:10:24.28#ibcon#read 6, iclass 22, count 0 2006.201.07:10:24.28#ibcon#end of sib2, iclass 22, count 0 2006.201.07:10:24.28#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:10:24.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:10:24.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:10:24.28#ibcon#*before write, iclass 22, count 0 2006.201.07:10:24.28#ibcon#enter sib2, iclass 22, count 0 2006.201.07:10:24.28#ibcon#flushed, iclass 22, count 0 2006.201.07:10:24.28#ibcon#about to write, iclass 22, count 0 2006.201.07:10:24.28#ibcon#wrote, iclass 22, count 0 2006.201.07:10:24.28#ibcon#about to read 3, iclass 22, count 0 2006.201.07:10:24.32#ibcon#read 3, iclass 22, count 0 2006.201.07:10:24.32#ibcon#about to read 4, iclass 22, count 0 2006.201.07:10:24.32#ibcon#read 4, iclass 22, count 0 2006.201.07:10:24.32#ibcon#about to read 5, iclass 22, count 0 2006.201.07:10:24.32#ibcon#read 5, iclass 22, count 0 2006.201.07:10:24.32#ibcon#about to read 6, iclass 22, count 0 2006.201.07:10:24.32#ibcon#read 6, iclass 22, count 0 2006.201.07:10:24.32#ibcon#end of sib2, iclass 22, count 0 2006.201.07:10:24.32#ibcon#*after write, iclass 22, count 0 2006.201.07:10:24.32#ibcon#*before return 0, iclass 22, count 0 2006.201.07:10:24.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:24.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:10:24.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:10:24.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:10:24.32$vck44/vb=6,4 2006.201.07:10:24.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.07:10:24.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.07:10:24.32#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:24.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:24.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:24.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:24.38#ibcon#enter wrdev, iclass 24, count 2 2006.201.07:10:24.38#ibcon#first serial, iclass 24, count 2 2006.201.07:10:24.38#ibcon#enter sib2, iclass 24, count 2 2006.201.07:10:24.38#ibcon#flushed, iclass 24, count 2 2006.201.07:10:24.38#ibcon#about to write, iclass 24, count 2 2006.201.07:10:24.38#ibcon#wrote, iclass 24, count 2 2006.201.07:10:24.38#ibcon#about to read 3, iclass 24, count 2 2006.201.07:10:24.40#ibcon#read 3, iclass 24, count 2 2006.201.07:10:24.40#ibcon#about to read 4, iclass 24, count 2 2006.201.07:10:24.40#ibcon#read 4, iclass 24, count 2 2006.201.07:10:24.40#ibcon#about to read 5, iclass 24, count 2 2006.201.07:10:24.40#ibcon#read 5, iclass 24, count 2 2006.201.07:10:24.40#ibcon#about to read 6, iclass 24, count 2 2006.201.07:10:24.40#ibcon#read 6, iclass 24, count 2 2006.201.07:10:24.40#ibcon#end of sib2, iclass 24, count 2 2006.201.07:10:24.40#ibcon#*mode == 0, iclass 24, count 2 2006.201.07:10:24.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.07:10:24.40#ibcon#[27=AT06-04\r\n] 2006.201.07:10:24.40#ibcon#*before write, iclass 24, count 2 2006.201.07:10:24.40#ibcon#enter sib2, iclass 24, count 2 2006.201.07:10:24.40#ibcon#flushed, iclass 24, count 2 2006.201.07:10:24.40#ibcon#about to write, iclass 24, count 2 2006.201.07:10:24.40#ibcon#wrote, iclass 24, count 2 2006.201.07:10:24.40#ibcon#about to read 3, iclass 24, count 2 2006.201.07:10:24.43#ibcon#read 3, iclass 24, count 2 2006.201.07:10:24.43#ibcon#about to read 4, iclass 24, count 2 2006.201.07:10:24.43#ibcon#read 4, iclass 24, count 2 2006.201.07:10:24.43#ibcon#about to read 5, iclass 24, count 2 2006.201.07:10:24.43#ibcon#read 5, iclass 24, count 2 2006.201.07:10:24.43#ibcon#about to read 6, iclass 24, count 2 2006.201.07:10:24.43#ibcon#read 6, iclass 24, count 2 2006.201.07:10:24.43#ibcon#end of sib2, iclass 24, count 2 2006.201.07:10:24.43#ibcon#*after write, iclass 24, count 2 2006.201.07:10:24.43#ibcon#*before return 0, iclass 24, count 2 2006.201.07:10:24.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:24.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:10:24.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.07:10:24.43#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:24.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:24.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:24.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:24.55#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:10:24.55#ibcon#first serial, iclass 24, count 0 2006.201.07:10:24.55#ibcon#enter sib2, iclass 24, count 0 2006.201.07:10:24.55#ibcon#flushed, iclass 24, count 0 2006.201.07:10:24.55#ibcon#about to write, iclass 24, count 0 2006.201.07:10:24.55#ibcon#wrote, iclass 24, count 0 2006.201.07:10:24.55#ibcon#about to read 3, iclass 24, count 0 2006.201.07:10:24.57#ibcon#read 3, iclass 24, count 0 2006.201.07:10:24.57#ibcon#about to read 4, iclass 24, count 0 2006.201.07:10:24.57#ibcon#read 4, iclass 24, count 0 2006.201.07:10:24.57#ibcon#about to read 5, iclass 24, count 0 2006.201.07:10:24.57#ibcon#read 5, iclass 24, count 0 2006.201.07:10:24.57#ibcon#about to read 6, iclass 24, count 0 2006.201.07:10:24.57#ibcon#read 6, iclass 24, count 0 2006.201.07:10:24.57#ibcon#end of sib2, iclass 24, count 0 2006.201.07:10:24.57#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:10:24.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:10:24.57#ibcon#[27=USB\r\n] 2006.201.07:10:24.57#ibcon#*before write, iclass 24, count 0 2006.201.07:10:24.57#ibcon#enter sib2, iclass 24, count 0 2006.201.07:10:24.57#ibcon#flushed, iclass 24, count 0 2006.201.07:10:24.57#ibcon#about to write, iclass 24, count 0 2006.201.07:10:24.57#ibcon#wrote, iclass 24, count 0 2006.201.07:10:24.57#ibcon#about to read 3, iclass 24, count 0 2006.201.07:10:24.60#ibcon#read 3, iclass 24, count 0 2006.201.07:10:24.60#ibcon#about to read 4, iclass 24, count 0 2006.201.07:10:24.60#ibcon#read 4, iclass 24, count 0 2006.201.07:10:24.60#ibcon#about to read 5, iclass 24, count 0 2006.201.07:10:24.60#ibcon#read 5, iclass 24, count 0 2006.201.07:10:24.60#ibcon#about to read 6, iclass 24, count 0 2006.201.07:10:24.60#ibcon#read 6, iclass 24, count 0 2006.201.07:10:24.60#ibcon#end of sib2, iclass 24, count 0 2006.201.07:10:24.60#ibcon#*after write, iclass 24, count 0 2006.201.07:10:24.60#ibcon#*before return 0, iclass 24, count 0 2006.201.07:10:24.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:24.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:10:24.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:10:24.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:10:24.60$vck44/vblo=7,734.99 2006.201.07:10:24.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.07:10:24.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.07:10:24.60#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:24.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:24.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:24.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:24.60#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:10:24.60#ibcon#first serial, iclass 26, count 0 2006.201.07:10:24.60#ibcon#enter sib2, iclass 26, count 0 2006.201.07:10:24.60#ibcon#flushed, iclass 26, count 0 2006.201.07:10:24.60#ibcon#about to write, iclass 26, count 0 2006.201.07:10:24.60#ibcon#wrote, iclass 26, count 0 2006.201.07:10:24.60#ibcon#about to read 3, iclass 26, count 0 2006.201.07:10:24.62#ibcon#read 3, iclass 26, count 0 2006.201.07:10:24.62#ibcon#about to read 4, iclass 26, count 0 2006.201.07:10:24.62#ibcon#read 4, iclass 26, count 0 2006.201.07:10:24.62#ibcon#about to read 5, iclass 26, count 0 2006.201.07:10:24.62#ibcon#read 5, iclass 26, count 0 2006.201.07:10:24.62#ibcon#about to read 6, iclass 26, count 0 2006.201.07:10:24.62#ibcon#read 6, iclass 26, count 0 2006.201.07:10:24.62#ibcon#end of sib2, iclass 26, count 0 2006.201.07:10:24.62#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:10:24.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:10:24.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:10:24.62#ibcon#*before write, iclass 26, count 0 2006.201.07:10:24.62#ibcon#enter sib2, iclass 26, count 0 2006.201.07:10:24.62#ibcon#flushed, iclass 26, count 0 2006.201.07:10:24.62#ibcon#about to write, iclass 26, count 0 2006.201.07:10:24.62#ibcon#wrote, iclass 26, count 0 2006.201.07:10:24.62#ibcon#about to read 3, iclass 26, count 0 2006.201.07:10:24.66#ibcon#read 3, iclass 26, count 0 2006.201.07:10:24.66#ibcon#about to read 4, iclass 26, count 0 2006.201.07:10:24.66#ibcon#read 4, iclass 26, count 0 2006.201.07:10:24.66#ibcon#about to read 5, iclass 26, count 0 2006.201.07:10:24.66#ibcon#read 5, iclass 26, count 0 2006.201.07:10:24.66#ibcon#about to read 6, iclass 26, count 0 2006.201.07:10:24.66#ibcon#read 6, iclass 26, count 0 2006.201.07:10:24.66#ibcon#end of sib2, iclass 26, count 0 2006.201.07:10:24.66#ibcon#*after write, iclass 26, count 0 2006.201.07:10:24.66#ibcon#*before return 0, iclass 26, count 0 2006.201.07:10:24.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:24.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:10:24.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:10:24.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:10:24.66$vck44/vb=7,4 2006.201.07:10:24.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.07:10:24.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.07:10:24.66#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:24.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:24.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:24.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:24.72#ibcon#enter wrdev, iclass 28, count 2 2006.201.07:10:24.72#ibcon#first serial, iclass 28, count 2 2006.201.07:10:24.72#ibcon#enter sib2, iclass 28, count 2 2006.201.07:10:24.72#ibcon#flushed, iclass 28, count 2 2006.201.07:10:24.72#ibcon#about to write, iclass 28, count 2 2006.201.07:10:24.72#ibcon#wrote, iclass 28, count 2 2006.201.07:10:24.72#ibcon#about to read 3, iclass 28, count 2 2006.201.07:10:24.74#ibcon#read 3, iclass 28, count 2 2006.201.07:10:24.74#ibcon#about to read 4, iclass 28, count 2 2006.201.07:10:24.74#ibcon#read 4, iclass 28, count 2 2006.201.07:10:24.74#ibcon#about to read 5, iclass 28, count 2 2006.201.07:10:24.74#ibcon#read 5, iclass 28, count 2 2006.201.07:10:24.74#ibcon#about to read 6, iclass 28, count 2 2006.201.07:10:24.74#ibcon#read 6, iclass 28, count 2 2006.201.07:10:24.74#ibcon#end of sib2, iclass 28, count 2 2006.201.07:10:24.74#ibcon#*mode == 0, iclass 28, count 2 2006.201.07:10:24.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.07:10:24.74#ibcon#[27=AT07-04\r\n] 2006.201.07:10:24.74#ibcon#*before write, iclass 28, count 2 2006.201.07:10:24.74#ibcon#enter sib2, iclass 28, count 2 2006.201.07:10:24.74#ibcon#flushed, iclass 28, count 2 2006.201.07:10:24.74#ibcon#about to write, iclass 28, count 2 2006.201.07:10:24.74#ibcon#wrote, iclass 28, count 2 2006.201.07:10:24.74#ibcon#about to read 3, iclass 28, count 2 2006.201.07:10:24.78#ibcon#read 3, iclass 28, count 2 2006.201.07:10:24.78#ibcon#about to read 4, iclass 28, count 2 2006.201.07:10:24.78#ibcon#read 4, iclass 28, count 2 2006.201.07:10:24.78#ibcon#about to read 5, iclass 28, count 2 2006.201.07:10:24.78#ibcon#read 5, iclass 28, count 2 2006.201.07:10:24.78#ibcon#about to read 6, iclass 28, count 2 2006.201.07:10:24.78#ibcon#read 6, iclass 28, count 2 2006.201.07:10:24.78#ibcon#end of sib2, iclass 28, count 2 2006.201.07:10:24.78#ibcon#*after write, iclass 28, count 2 2006.201.07:10:24.78#ibcon#*before return 0, iclass 28, count 2 2006.201.07:10:24.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:24.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:10:24.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.07:10:24.78#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:24.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:24.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:24.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:24.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:10:24.90#ibcon#first serial, iclass 28, count 0 2006.201.07:10:24.90#ibcon#enter sib2, iclass 28, count 0 2006.201.07:10:24.90#ibcon#flushed, iclass 28, count 0 2006.201.07:10:24.90#ibcon#about to write, iclass 28, count 0 2006.201.07:10:24.90#ibcon#wrote, iclass 28, count 0 2006.201.07:10:24.90#ibcon#about to read 3, iclass 28, count 0 2006.201.07:10:24.92#ibcon#read 3, iclass 28, count 0 2006.201.07:10:24.92#ibcon#about to read 4, iclass 28, count 0 2006.201.07:10:24.92#ibcon#read 4, iclass 28, count 0 2006.201.07:10:24.92#ibcon#about to read 5, iclass 28, count 0 2006.201.07:10:24.92#ibcon#read 5, iclass 28, count 0 2006.201.07:10:24.92#ibcon#about to read 6, iclass 28, count 0 2006.201.07:10:24.92#ibcon#read 6, iclass 28, count 0 2006.201.07:10:24.92#ibcon#end of sib2, iclass 28, count 0 2006.201.07:10:24.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:10:24.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:10:24.92#ibcon#[27=USB\r\n] 2006.201.07:10:24.92#ibcon#*before write, iclass 28, count 0 2006.201.07:10:24.92#ibcon#enter sib2, iclass 28, count 0 2006.201.07:10:24.92#ibcon#flushed, iclass 28, count 0 2006.201.07:10:24.92#ibcon#about to write, iclass 28, count 0 2006.201.07:10:24.92#ibcon#wrote, iclass 28, count 0 2006.201.07:10:24.92#ibcon#about to read 3, iclass 28, count 0 2006.201.07:10:24.95#ibcon#read 3, iclass 28, count 0 2006.201.07:10:24.95#ibcon#about to read 4, iclass 28, count 0 2006.201.07:10:24.95#ibcon#read 4, iclass 28, count 0 2006.201.07:10:24.95#ibcon#about to read 5, iclass 28, count 0 2006.201.07:10:24.95#ibcon#read 5, iclass 28, count 0 2006.201.07:10:24.95#ibcon#about to read 6, iclass 28, count 0 2006.201.07:10:24.95#ibcon#read 6, iclass 28, count 0 2006.201.07:10:24.95#ibcon#end of sib2, iclass 28, count 0 2006.201.07:10:24.95#ibcon#*after write, iclass 28, count 0 2006.201.07:10:24.95#ibcon#*before return 0, iclass 28, count 0 2006.201.07:10:24.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:24.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:10:24.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:10:24.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:10:24.95$vck44/vblo=8,744.99 2006.201.07:10:24.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.07:10:24.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.07:10:24.95#ibcon#ireg 17 cls_cnt 0 2006.201.07:10:24.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:24.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:24.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:24.95#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:10:24.95#ibcon#first serial, iclass 30, count 0 2006.201.07:10:24.95#ibcon#enter sib2, iclass 30, count 0 2006.201.07:10:24.95#ibcon#flushed, iclass 30, count 0 2006.201.07:10:24.95#ibcon#about to write, iclass 30, count 0 2006.201.07:10:24.95#ibcon#wrote, iclass 30, count 0 2006.201.07:10:24.95#ibcon#about to read 3, iclass 30, count 0 2006.201.07:10:24.97#ibcon#read 3, iclass 30, count 0 2006.201.07:10:24.97#ibcon#about to read 4, iclass 30, count 0 2006.201.07:10:24.97#ibcon#read 4, iclass 30, count 0 2006.201.07:10:24.97#ibcon#about to read 5, iclass 30, count 0 2006.201.07:10:24.97#ibcon#read 5, iclass 30, count 0 2006.201.07:10:24.97#ibcon#about to read 6, iclass 30, count 0 2006.201.07:10:24.97#ibcon#read 6, iclass 30, count 0 2006.201.07:10:24.97#ibcon#end of sib2, iclass 30, count 0 2006.201.07:10:24.97#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:10:24.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:10:24.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:10:24.97#ibcon#*before write, iclass 30, count 0 2006.201.07:10:24.97#ibcon#enter sib2, iclass 30, count 0 2006.201.07:10:24.97#ibcon#flushed, iclass 30, count 0 2006.201.07:10:24.97#ibcon#about to write, iclass 30, count 0 2006.201.07:10:24.97#ibcon#wrote, iclass 30, count 0 2006.201.07:10:24.97#ibcon#about to read 3, iclass 30, count 0 2006.201.07:10:25.01#ibcon#read 3, iclass 30, count 0 2006.201.07:10:25.01#ibcon#about to read 4, iclass 30, count 0 2006.201.07:10:25.01#ibcon#read 4, iclass 30, count 0 2006.201.07:10:25.01#ibcon#about to read 5, iclass 30, count 0 2006.201.07:10:25.01#ibcon#read 5, iclass 30, count 0 2006.201.07:10:25.01#ibcon#about to read 6, iclass 30, count 0 2006.201.07:10:25.01#ibcon#read 6, iclass 30, count 0 2006.201.07:10:25.01#ibcon#end of sib2, iclass 30, count 0 2006.201.07:10:25.01#ibcon#*after write, iclass 30, count 0 2006.201.07:10:25.01#ibcon#*before return 0, iclass 30, count 0 2006.201.07:10:25.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:25.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:10:25.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:10:25.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:10:25.01$vck44/vb=8,4 2006.201.07:10:25.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.07:10:25.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.07:10:25.01#ibcon#ireg 11 cls_cnt 2 2006.201.07:10:25.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:25.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:25.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:25.07#ibcon#enter wrdev, iclass 32, count 2 2006.201.07:10:25.07#ibcon#first serial, iclass 32, count 2 2006.201.07:10:25.07#ibcon#enter sib2, iclass 32, count 2 2006.201.07:10:25.07#ibcon#flushed, iclass 32, count 2 2006.201.07:10:25.07#ibcon#about to write, iclass 32, count 2 2006.201.07:10:25.07#ibcon#wrote, iclass 32, count 2 2006.201.07:10:25.07#ibcon#about to read 3, iclass 32, count 2 2006.201.07:10:25.09#ibcon#read 3, iclass 32, count 2 2006.201.07:10:25.09#ibcon#about to read 4, iclass 32, count 2 2006.201.07:10:25.09#ibcon#read 4, iclass 32, count 2 2006.201.07:10:25.09#ibcon#about to read 5, iclass 32, count 2 2006.201.07:10:25.09#ibcon#read 5, iclass 32, count 2 2006.201.07:10:25.09#ibcon#about to read 6, iclass 32, count 2 2006.201.07:10:25.09#ibcon#read 6, iclass 32, count 2 2006.201.07:10:25.09#ibcon#end of sib2, iclass 32, count 2 2006.201.07:10:25.09#ibcon#*mode == 0, iclass 32, count 2 2006.201.07:10:25.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.07:10:25.09#ibcon#[27=AT08-04\r\n] 2006.201.07:10:25.09#ibcon#*before write, iclass 32, count 2 2006.201.07:10:25.09#ibcon#enter sib2, iclass 32, count 2 2006.201.07:10:25.09#ibcon#flushed, iclass 32, count 2 2006.201.07:10:25.09#ibcon#about to write, iclass 32, count 2 2006.201.07:10:25.09#ibcon#wrote, iclass 32, count 2 2006.201.07:10:25.09#ibcon#about to read 3, iclass 32, count 2 2006.201.07:10:25.12#ibcon#read 3, iclass 32, count 2 2006.201.07:10:25.12#ibcon#about to read 4, iclass 32, count 2 2006.201.07:10:25.12#ibcon#read 4, iclass 32, count 2 2006.201.07:10:25.12#ibcon#about to read 5, iclass 32, count 2 2006.201.07:10:25.12#ibcon#read 5, iclass 32, count 2 2006.201.07:10:25.12#ibcon#about to read 6, iclass 32, count 2 2006.201.07:10:25.12#ibcon#read 6, iclass 32, count 2 2006.201.07:10:25.12#ibcon#end of sib2, iclass 32, count 2 2006.201.07:10:25.12#ibcon#*after write, iclass 32, count 2 2006.201.07:10:25.12#ibcon#*before return 0, iclass 32, count 2 2006.201.07:10:25.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:25.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:10:25.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.07:10:25.12#ibcon#ireg 7 cls_cnt 0 2006.201.07:10:25.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:25.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:25.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:25.24#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:10:25.24#ibcon#first serial, iclass 32, count 0 2006.201.07:10:25.24#ibcon#enter sib2, iclass 32, count 0 2006.201.07:10:25.24#ibcon#flushed, iclass 32, count 0 2006.201.07:10:25.24#ibcon#about to write, iclass 32, count 0 2006.201.07:10:25.24#ibcon#wrote, iclass 32, count 0 2006.201.07:10:25.24#ibcon#about to read 3, iclass 32, count 0 2006.201.07:10:25.26#ibcon#read 3, iclass 32, count 0 2006.201.07:10:25.26#ibcon#about to read 4, iclass 32, count 0 2006.201.07:10:25.26#ibcon#read 4, iclass 32, count 0 2006.201.07:10:25.26#ibcon#about to read 5, iclass 32, count 0 2006.201.07:10:25.26#ibcon#read 5, iclass 32, count 0 2006.201.07:10:25.26#ibcon#about to read 6, iclass 32, count 0 2006.201.07:10:25.26#ibcon#read 6, iclass 32, count 0 2006.201.07:10:25.26#ibcon#end of sib2, iclass 32, count 0 2006.201.07:10:25.26#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:10:25.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:10:25.26#ibcon#[27=USB\r\n] 2006.201.07:10:25.26#ibcon#*before write, iclass 32, count 0 2006.201.07:10:25.26#ibcon#enter sib2, iclass 32, count 0 2006.201.07:10:25.26#ibcon#flushed, iclass 32, count 0 2006.201.07:10:25.26#ibcon#about to write, iclass 32, count 0 2006.201.07:10:25.26#ibcon#wrote, iclass 32, count 0 2006.201.07:10:25.26#ibcon#about to read 3, iclass 32, count 0 2006.201.07:10:25.29#ibcon#read 3, iclass 32, count 0 2006.201.07:10:25.29#ibcon#about to read 4, iclass 32, count 0 2006.201.07:10:25.29#ibcon#read 4, iclass 32, count 0 2006.201.07:10:25.29#ibcon#about to read 5, iclass 32, count 0 2006.201.07:10:25.29#ibcon#read 5, iclass 32, count 0 2006.201.07:10:25.29#ibcon#about to read 6, iclass 32, count 0 2006.201.07:10:25.29#ibcon#read 6, iclass 32, count 0 2006.201.07:10:25.29#ibcon#end of sib2, iclass 32, count 0 2006.201.07:10:25.29#ibcon#*after write, iclass 32, count 0 2006.201.07:10:25.29#ibcon#*before return 0, iclass 32, count 0 2006.201.07:10:25.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:25.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:10:25.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:10:25.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:10:25.29$vck44/vabw=wide 2006.201.07:10:25.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.07:10:25.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.07:10:25.29#ibcon#ireg 8 cls_cnt 0 2006.201.07:10:25.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:25.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:25.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:25.29#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:10:25.29#ibcon#first serial, iclass 34, count 0 2006.201.07:10:25.29#ibcon#enter sib2, iclass 34, count 0 2006.201.07:10:25.29#ibcon#flushed, iclass 34, count 0 2006.201.07:10:25.29#ibcon#about to write, iclass 34, count 0 2006.201.07:10:25.29#ibcon#wrote, iclass 34, count 0 2006.201.07:10:25.29#ibcon#about to read 3, iclass 34, count 0 2006.201.07:10:25.31#ibcon#read 3, iclass 34, count 0 2006.201.07:10:25.31#ibcon#about to read 4, iclass 34, count 0 2006.201.07:10:25.31#ibcon#read 4, iclass 34, count 0 2006.201.07:10:25.31#ibcon#about to read 5, iclass 34, count 0 2006.201.07:10:25.31#ibcon#read 5, iclass 34, count 0 2006.201.07:10:25.31#ibcon#about to read 6, iclass 34, count 0 2006.201.07:10:25.31#ibcon#read 6, iclass 34, count 0 2006.201.07:10:25.31#ibcon#end of sib2, iclass 34, count 0 2006.201.07:10:25.31#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:10:25.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:10:25.31#ibcon#[25=BW32\r\n] 2006.201.07:10:25.31#ibcon#*before write, iclass 34, count 0 2006.201.07:10:25.31#ibcon#enter sib2, iclass 34, count 0 2006.201.07:10:25.31#ibcon#flushed, iclass 34, count 0 2006.201.07:10:25.31#ibcon#about to write, iclass 34, count 0 2006.201.07:10:25.31#ibcon#wrote, iclass 34, count 0 2006.201.07:10:25.31#ibcon#about to read 3, iclass 34, count 0 2006.201.07:10:25.34#ibcon#read 3, iclass 34, count 0 2006.201.07:10:25.34#ibcon#about to read 4, iclass 34, count 0 2006.201.07:10:25.34#ibcon#read 4, iclass 34, count 0 2006.201.07:10:25.34#ibcon#about to read 5, iclass 34, count 0 2006.201.07:10:25.34#ibcon#read 5, iclass 34, count 0 2006.201.07:10:25.34#ibcon#about to read 6, iclass 34, count 0 2006.201.07:10:25.34#ibcon#read 6, iclass 34, count 0 2006.201.07:10:25.34#ibcon#end of sib2, iclass 34, count 0 2006.201.07:10:25.34#ibcon#*after write, iclass 34, count 0 2006.201.07:10:25.34#ibcon#*before return 0, iclass 34, count 0 2006.201.07:10:25.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:25.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:10:25.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:10:25.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:10:25.34$vck44/vbbw=wide 2006.201.07:10:25.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.07:10:25.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.07:10:25.34#ibcon#ireg 8 cls_cnt 0 2006.201.07:10:25.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:10:25.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:10:25.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:10:25.41#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:10:25.41#ibcon#first serial, iclass 36, count 0 2006.201.07:10:25.41#ibcon#enter sib2, iclass 36, count 0 2006.201.07:10:25.41#ibcon#flushed, iclass 36, count 0 2006.201.07:10:25.41#ibcon#about to write, iclass 36, count 0 2006.201.07:10:25.41#ibcon#wrote, iclass 36, count 0 2006.201.07:10:25.41#ibcon#about to read 3, iclass 36, count 0 2006.201.07:10:25.43#ibcon#read 3, iclass 36, count 0 2006.201.07:10:25.43#ibcon#about to read 4, iclass 36, count 0 2006.201.07:10:25.43#ibcon#read 4, iclass 36, count 0 2006.201.07:10:25.43#ibcon#about to read 5, iclass 36, count 0 2006.201.07:10:25.43#ibcon#read 5, iclass 36, count 0 2006.201.07:10:25.43#ibcon#about to read 6, iclass 36, count 0 2006.201.07:10:25.43#ibcon#read 6, iclass 36, count 0 2006.201.07:10:25.43#ibcon#end of sib2, iclass 36, count 0 2006.201.07:10:25.43#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:10:25.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:10:25.43#ibcon#[27=BW32\r\n] 2006.201.07:10:25.43#ibcon#*before write, iclass 36, count 0 2006.201.07:10:25.43#ibcon#enter sib2, iclass 36, count 0 2006.201.07:10:25.43#ibcon#flushed, iclass 36, count 0 2006.201.07:10:25.43#ibcon#about to write, iclass 36, count 0 2006.201.07:10:25.43#ibcon#wrote, iclass 36, count 0 2006.201.07:10:25.43#ibcon#about to read 3, iclass 36, count 0 2006.201.07:10:25.46#ibcon#read 3, iclass 36, count 0 2006.201.07:10:25.46#ibcon#about to read 4, iclass 36, count 0 2006.201.07:10:25.46#ibcon#read 4, iclass 36, count 0 2006.201.07:10:25.46#ibcon#about to read 5, iclass 36, count 0 2006.201.07:10:25.46#ibcon#read 5, iclass 36, count 0 2006.201.07:10:25.46#ibcon#about to read 6, iclass 36, count 0 2006.201.07:10:25.46#ibcon#read 6, iclass 36, count 0 2006.201.07:10:25.46#ibcon#end of sib2, iclass 36, count 0 2006.201.07:10:25.46#ibcon#*after write, iclass 36, count 0 2006.201.07:10:25.46#ibcon#*before return 0, iclass 36, count 0 2006.201.07:10:25.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:10:25.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:10:25.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:10:25.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:10:25.46$setupk4/ifdk4 2006.201.07:10:25.46$ifdk4/lo= 2006.201.07:10:25.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:10:25.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:10:25.46$ifdk4/patch= 2006.201.07:10:25.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:10:25.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:10:25.46$setupk4/!*+20s 2006.201.07:10:28.77#abcon#<5=/04 2.3 4.7 23.18 881003.2\r\n> 2006.201.07:10:28.79#abcon#{5=INTERFACE CLEAR} 2006.201.07:10:28.85#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:10:38.94#abcon#<5=/04 2.3 4.7 23.18 881003.2\r\n> 2006.201.07:10:38.96#abcon#{5=INTERFACE CLEAR} 2006.201.07:10:39.02#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:10:39.90$setupk4/"tpicd 2006.201.07:10:39.90$setupk4/echo=off 2006.201.07:10:39.90$setupk4/xlog=off 2006.201.07:10:39.90:!2006.201.07:17:49 2006.201.07:10:52.13#trakl#Source acquired 2006.201.07:10:54.13#flagr#flagr/antenna,acquired 2006.201.07:17:49.00:preob 2006.201.07:17:49.14/onsource/TRACKING 2006.201.07:17:49.14:!2006.201.07:17:59 2006.201.07:17:59.00:"tape 2006.201.07:17:59.00:"st=record 2006.201.07:17:59.00:data_valid=on 2006.201.07:17:59.00:midob 2006.201.07:18:00.13/onsource/TRACKING 2006.201.07:18:00.13/wx/23.20,1003.1,88 2006.201.07:18:00.19/cable/+6.4654E-03 2006.201.07:18:01.29/va/01,08,usb,yes,28,31 2006.201.07:18:01.29/va/02,07,usb,yes,31,31 2006.201.07:18:01.29/va/03,08,usb,yes,28,29 2006.201.07:18:01.29/va/04,07,usb,yes,31,33 2006.201.07:18:01.29/va/05,04,usb,yes,28,28 2006.201.07:18:01.29/va/06,05,usb,yes,28,28 2006.201.07:18:01.29/va/07,05,usb,yes,27,28 2006.201.07:18:01.29/va/08,04,usb,yes,27,32 2006.201.07:18:01.52/valo/01,524.99,yes,locked 2006.201.07:18:01.52/valo/02,534.99,yes,locked 2006.201.07:18:01.52/valo/03,564.99,yes,locked 2006.201.07:18:01.52/valo/04,624.99,yes,locked 2006.201.07:18:01.52/valo/05,734.99,yes,locked 2006.201.07:18:01.52/valo/06,814.99,yes,locked 2006.201.07:18:01.52/valo/07,864.99,yes,locked 2006.201.07:18:01.52/valo/08,884.99,yes,locked 2006.201.07:18:02.61/vb/01,04,usb,yes,29,27 2006.201.07:18:02.61/vb/02,05,usb,yes,28,27 2006.201.07:18:02.61/vb/03,04,usb,yes,28,31 2006.201.07:18:02.61/vb/04,05,usb,yes,29,28 2006.201.07:18:02.61/vb/05,04,usb,yes,25,28 2006.201.07:18:02.61/vb/06,04,usb,yes,30,26 2006.201.07:18:02.61/vb/07,04,usb,yes,29,29 2006.201.07:18:02.61/vb/08,04,usb,yes,27,30 2006.201.07:18:02.85/vblo/01,629.99,yes,locked 2006.201.07:18:02.85/vblo/02,634.99,yes,locked 2006.201.07:18:02.85/vblo/03,649.99,yes,locked 2006.201.07:18:02.85/vblo/04,679.99,yes,locked 2006.201.07:18:02.85/vblo/05,709.99,yes,locked 2006.201.07:18:02.85/vblo/06,719.99,yes,locked 2006.201.07:18:02.85/vblo/07,734.99,yes,locked 2006.201.07:18:02.85/vblo/08,744.99,yes,locked 2006.201.07:18:03.00/vabw/8 2006.201.07:18:03.15/vbbw/8 2006.201.07:18:03.24/xfe/off,on,15.2 2006.201.07:18:03.62/ifatt/23,28,28,28 2006.201.07:18:04.04/fmout-gps/S +4.51E-07 2006.201.07:18:04.09:!2006.201.07:18:39 2006.201.07:18:39.00:data_valid=off 2006.201.07:18:39.00:"et 2006.201.07:18:39.00:!+3s 2006.201.07:18:42.02:"tape 2006.201.07:18:42.02:postob 2006.201.07:18:42.09/cable/+6.4656E-03 2006.201.07:18:42.09/wx/23.21,1003.1,89 2006.201.07:18:42.16/fmout-gps/S +4.52E-07 2006.201.07:18:42.16:scan_name=201-0720,jd0607,40 2006.201.07:18:42.16:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.201.07:18:44.13#flagr#flagr/antenna,new-source 2006.201.07:18:44.13:checkk5 2006.201.07:18:44.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:18:44.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:18:45.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:18:45.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:18:46.00/chk_obsdata//k5ts1/T2010717??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:18:46.36/chk_obsdata//k5ts2/T2010717??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:18:46.73/chk_obsdata//k5ts3/T2010717??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:18:47.10/chk_obsdata//k5ts4/T2010717??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:18:47.80/k5log//k5ts1_log_newline 2006.201.07:18:48.50/k5log//k5ts2_log_newline 2006.201.07:18:49.20/k5log//k5ts3_log_newline 2006.201.07:18:49.89/k5log//k5ts4_log_newline 2006.201.07:18:49.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:18:49.91:setupk4=1 2006.201.07:18:49.91$setupk4/echo=on 2006.201.07:18:49.92$setupk4/pcalon 2006.201.07:18:49.92$pcalon/"no phase cal control is implemented here 2006.201.07:18:49.92$setupk4/"tpicd=stop 2006.201.07:18:49.92$setupk4/"rec=synch_on 2006.201.07:18:49.92$setupk4/"rec_mode=128 2006.201.07:18:49.92$setupk4/!* 2006.201.07:18:49.92$setupk4/recpk4 2006.201.07:18:49.92$recpk4/recpatch= 2006.201.07:18:49.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:18:49.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:18:49.92$setupk4/vck44 2006.201.07:18:49.92$vck44/valo=1,524.99 2006.201.07:18:49.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.07:18:49.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.07:18:49.92#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:49.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:49.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:49.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:49.92#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:18:49.92#ibcon#first serial, iclass 25, count 0 2006.201.07:18:49.92#ibcon#enter sib2, iclass 25, count 0 2006.201.07:18:49.92#ibcon#flushed, iclass 25, count 0 2006.201.07:18:49.92#ibcon#about to write, iclass 25, count 0 2006.201.07:18:49.92#ibcon#wrote, iclass 25, count 0 2006.201.07:18:49.92#ibcon#about to read 3, iclass 25, count 0 2006.201.07:18:49.96#ibcon#read 3, iclass 25, count 0 2006.201.07:18:49.96#ibcon#about to read 4, iclass 25, count 0 2006.201.07:18:49.96#ibcon#read 4, iclass 25, count 0 2006.201.07:18:49.96#ibcon#about to read 5, iclass 25, count 0 2006.201.07:18:49.96#ibcon#read 5, iclass 25, count 0 2006.201.07:18:49.96#ibcon#about to read 6, iclass 25, count 0 2006.201.07:18:49.96#ibcon#read 6, iclass 25, count 0 2006.201.07:18:49.96#ibcon#end of sib2, iclass 25, count 0 2006.201.07:18:49.96#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:18:49.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:18:49.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:18:49.96#ibcon#*before write, iclass 25, count 0 2006.201.07:18:49.96#ibcon#enter sib2, iclass 25, count 0 2006.201.07:18:49.96#ibcon#flushed, iclass 25, count 0 2006.201.07:18:49.96#ibcon#about to write, iclass 25, count 0 2006.201.07:18:49.96#ibcon#wrote, iclass 25, count 0 2006.201.07:18:49.96#ibcon#about to read 3, iclass 25, count 0 2006.201.07:18:50.01#ibcon#read 3, iclass 25, count 0 2006.201.07:18:50.01#ibcon#about to read 4, iclass 25, count 0 2006.201.07:18:50.01#ibcon#read 4, iclass 25, count 0 2006.201.07:18:50.01#ibcon#about to read 5, iclass 25, count 0 2006.201.07:18:50.01#ibcon#read 5, iclass 25, count 0 2006.201.07:18:50.01#ibcon#about to read 6, iclass 25, count 0 2006.201.07:18:50.01#ibcon#read 6, iclass 25, count 0 2006.201.07:18:50.01#ibcon#end of sib2, iclass 25, count 0 2006.201.07:18:50.01#ibcon#*after write, iclass 25, count 0 2006.201.07:18:50.01#ibcon#*before return 0, iclass 25, count 0 2006.201.07:18:50.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:50.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:50.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:18:50.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:18:50.01$vck44/va=1,8 2006.201.07:18:50.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.07:18:50.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.07:18:50.01#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:50.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:50.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:50.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:50.01#ibcon#enter wrdev, iclass 27, count 2 2006.201.07:18:50.01#ibcon#first serial, iclass 27, count 2 2006.201.07:18:50.01#ibcon#enter sib2, iclass 27, count 2 2006.201.07:18:50.01#ibcon#flushed, iclass 27, count 2 2006.201.07:18:50.01#ibcon#about to write, iclass 27, count 2 2006.201.07:18:50.01#ibcon#wrote, iclass 27, count 2 2006.201.07:18:50.01#ibcon#about to read 3, iclass 27, count 2 2006.201.07:18:50.03#ibcon#read 3, iclass 27, count 2 2006.201.07:18:50.03#ibcon#about to read 4, iclass 27, count 2 2006.201.07:18:50.03#ibcon#read 4, iclass 27, count 2 2006.201.07:18:50.03#ibcon#about to read 5, iclass 27, count 2 2006.201.07:18:50.03#ibcon#read 5, iclass 27, count 2 2006.201.07:18:50.03#ibcon#about to read 6, iclass 27, count 2 2006.201.07:18:50.03#ibcon#read 6, iclass 27, count 2 2006.201.07:18:50.03#ibcon#end of sib2, iclass 27, count 2 2006.201.07:18:50.03#ibcon#*mode == 0, iclass 27, count 2 2006.201.07:18:50.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.07:18:50.03#ibcon#[25=AT01-08\r\n] 2006.201.07:18:50.03#ibcon#*before write, iclass 27, count 2 2006.201.07:18:50.03#ibcon#enter sib2, iclass 27, count 2 2006.201.07:18:50.03#ibcon#flushed, iclass 27, count 2 2006.201.07:18:50.03#ibcon#about to write, iclass 27, count 2 2006.201.07:18:50.03#ibcon#wrote, iclass 27, count 2 2006.201.07:18:50.03#ibcon#about to read 3, iclass 27, count 2 2006.201.07:18:50.06#ibcon#read 3, iclass 27, count 2 2006.201.07:18:50.06#ibcon#about to read 4, iclass 27, count 2 2006.201.07:18:50.06#ibcon#read 4, iclass 27, count 2 2006.201.07:18:50.06#ibcon#about to read 5, iclass 27, count 2 2006.201.07:18:50.06#ibcon#read 5, iclass 27, count 2 2006.201.07:18:50.06#ibcon#about to read 6, iclass 27, count 2 2006.201.07:18:50.06#ibcon#read 6, iclass 27, count 2 2006.201.07:18:50.06#ibcon#end of sib2, iclass 27, count 2 2006.201.07:18:50.06#ibcon#*after write, iclass 27, count 2 2006.201.07:18:50.06#ibcon#*before return 0, iclass 27, count 2 2006.201.07:18:50.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:50.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:50.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.07:18:50.06#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:50.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:50.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:50.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:50.18#ibcon#enter wrdev, iclass 27, count 0 2006.201.07:18:50.18#ibcon#first serial, iclass 27, count 0 2006.201.07:18:50.18#ibcon#enter sib2, iclass 27, count 0 2006.201.07:18:50.18#ibcon#flushed, iclass 27, count 0 2006.201.07:18:50.18#ibcon#about to write, iclass 27, count 0 2006.201.07:18:50.18#ibcon#wrote, iclass 27, count 0 2006.201.07:18:50.18#ibcon#about to read 3, iclass 27, count 0 2006.201.07:18:50.20#ibcon#read 3, iclass 27, count 0 2006.201.07:18:50.20#ibcon#about to read 4, iclass 27, count 0 2006.201.07:18:50.20#ibcon#read 4, iclass 27, count 0 2006.201.07:18:50.20#ibcon#about to read 5, iclass 27, count 0 2006.201.07:18:50.20#ibcon#read 5, iclass 27, count 0 2006.201.07:18:50.20#ibcon#about to read 6, iclass 27, count 0 2006.201.07:18:50.20#ibcon#read 6, iclass 27, count 0 2006.201.07:18:50.20#ibcon#end of sib2, iclass 27, count 0 2006.201.07:18:50.20#ibcon#*mode == 0, iclass 27, count 0 2006.201.07:18:50.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.07:18:50.20#ibcon#[25=USB\r\n] 2006.201.07:18:50.20#ibcon#*before write, iclass 27, count 0 2006.201.07:18:50.20#ibcon#enter sib2, iclass 27, count 0 2006.201.07:18:50.20#ibcon#flushed, iclass 27, count 0 2006.201.07:18:50.20#ibcon#about to write, iclass 27, count 0 2006.201.07:18:50.20#ibcon#wrote, iclass 27, count 0 2006.201.07:18:50.20#ibcon#about to read 3, iclass 27, count 0 2006.201.07:18:50.23#ibcon#read 3, iclass 27, count 0 2006.201.07:18:50.23#ibcon#about to read 4, iclass 27, count 0 2006.201.07:18:50.23#ibcon#read 4, iclass 27, count 0 2006.201.07:18:50.23#ibcon#about to read 5, iclass 27, count 0 2006.201.07:18:50.23#ibcon#read 5, iclass 27, count 0 2006.201.07:18:50.23#ibcon#about to read 6, iclass 27, count 0 2006.201.07:18:50.23#ibcon#read 6, iclass 27, count 0 2006.201.07:18:50.23#ibcon#end of sib2, iclass 27, count 0 2006.201.07:18:50.23#ibcon#*after write, iclass 27, count 0 2006.201.07:18:50.23#ibcon#*before return 0, iclass 27, count 0 2006.201.07:18:50.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:50.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:50.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.07:18:50.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.07:18:50.23$vck44/valo=2,534.99 2006.201.07:18:50.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.07:18:50.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.07:18:50.23#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:50.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:50.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:50.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:50.23#ibcon#enter wrdev, iclass 29, count 0 2006.201.07:18:50.23#ibcon#first serial, iclass 29, count 0 2006.201.07:18:50.23#ibcon#enter sib2, iclass 29, count 0 2006.201.07:18:50.23#ibcon#flushed, iclass 29, count 0 2006.201.07:18:50.23#ibcon#about to write, iclass 29, count 0 2006.201.07:18:50.23#ibcon#wrote, iclass 29, count 0 2006.201.07:18:50.23#ibcon#about to read 3, iclass 29, count 0 2006.201.07:18:50.25#ibcon#read 3, iclass 29, count 0 2006.201.07:18:50.25#ibcon#about to read 4, iclass 29, count 0 2006.201.07:18:50.25#ibcon#read 4, iclass 29, count 0 2006.201.07:18:50.25#ibcon#about to read 5, iclass 29, count 0 2006.201.07:18:50.25#ibcon#read 5, iclass 29, count 0 2006.201.07:18:50.25#ibcon#about to read 6, iclass 29, count 0 2006.201.07:18:50.25#ibcon#read 6, iclass 29, count 0 2006.201.07:18:50.25#ibcon#end of sib2, iclass 29, count 0 2006.201.07:18:50.25#ibcon#*mode == 0, iclass 29, count 0 2006.201.07:18:50.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.07:18:50.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:18:50.25#ibcon#*before write, iclass 29, count 0 2006.201.07:18:50.25#ibcon#enter sib2, iclass 29, count 0 2006.201.07:18:50.25#ibcon#flushed, iclass 29, count 0 2006.201.07:18:50.25#ibcon#about to write, iclass 29, count 0 2006.201.07:18:50.25#ibcon#wrote, iclass 29, count 0 2006.201.07:18:50.25#ibcon#about to read 3, iclass 29, count 0 2006.201.07:18:50.29#ibcon#read 3, iclass 29, count 0 2006.201.07:18:50.29#ibcon#about to read 4, iclass 29, count 0 2006.201.07:18:50.29#ibcon#read 4, iclass 29, count 0 2006.201.07:18:50.29#ibcon#about to read 5, iclass 29, count 0 2006.201.07:18:50.29#ibcon#read 5, iclass 29, count 0 2006.201.07:18:50.29#ibcon#about to read 6, iclass 29, count 0 2006.201.07:18:50.29#ibcon#read 6, iclass 29, count 0 2006.201.07:18:50.29#ibcon#end of sib2, iclass 29, count 0 2006.201.07:18:50.29#ibcon#*after write, iclass 29, count 0 2006.201.07:18:50.29#ibcon#*before return 0, iclass 29, count 0 2006.201.07:18:50.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:50.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:50.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.07:18:50.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.07:18:50.29$vck44/va=2,7 2006.201.07:18:50.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.07:18:50.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.07:18:50.29#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:50.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:50.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:50.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:50.35#ibcon#enter wrdev, iclass 31, count 2 2006.201.07:18:50.35#ibcon#first serial, iclass 31, count 2 2006.201.07:18:50.35#ibcon#enter sib2, iclass 31, count 2 2006.201.07:18:50.35#ibcon#flushed, iclass 31, count 2 2006.201.07:18:50.35#ibcon#about to write, iclass 31, count 2 2006.201.07:18:50.35#ibcon#wrote, iclass 31, count 2 2006.201.07:18:50.35#ibcon#about to read 3, iclass 31, count 2 2006.201.07:18:50.37#ibcon#read 3, iclass 31, count 2 2006.201.07:18:50.37#ibcon#about to read 4, iclass 31, count 2 2006.201.07:18:50.37#ibcon#read 4, iclass 31, count 2 2006.201.07:18:50.37#ibcon#about to read 5, iclass 31, count 2 2006.201.07:18:50.37#ibcon#read 5, iclass 31, count 2 2006.201.07:18:50.37#ibcon#about to read 6, iclass 31, count 2 2006.201.07:18:50.37#ibcon#read 6, iclass 31, count 2 2006.201.07:18:50.37#ibcon#end of sib2, iclass 31, count 2 2006.201.07:18:50.37#ibcon#*mode == 0, iclass 31, count 2 2006.201.07:18:50.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.07:18:50.37#ibcon#[25=AT02-07\r\n] 2006.201.07:18:50.37#ibcon#*before write, iclass 31, count 2 2006.201.07:18:50.37#ibcon#enter sib2, iclass 31, count 2 2006.201.07:18:50.37#ibcon#flushed, iclass 31, count 2 2006.201.07:18:50.37#ibcon#about to write, iclass 31, count 2 2006.201.07:18:50.37#ibcon#wrote, iclass 31, count 2 2006.201.07:18:50.37#ibcon#about to read 3, iclass 31, count 2 2006.201.07:18:50.40#ibcon#read 3, iclass 31, count 2 2006.201.07:18:50.40#ibcon#about to read 4, iclass 31, count 2 2006.201.07:18:50.40#ibcon#read 4, iclass 31, count 2 2006.201.07:18:50.40#ibcon#about to read 5, iclass 31, count 2 2006.201.07:18:50.40#ibcon#read 5, iclass 31, count 2 2006.201.07:18:50.40#ibcon#about to read 6, iclass 31, count 2 2006.201.07:18:50.40#ibcon#read 6, iclass 31, count 2 2006.201.07:18:50.40#ibcon#end of sib2, iclass 31, count 2 2006.201.07:18:50.40#ibcon#*after write, iclass 31, count 2 2006.201.07:18:50.40#ibcon#*before return 0, iclass 31, count 2 2006.201.07:18:50.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:50.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:50.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.07:18:50.40#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:50.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:50.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:50.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:50.52#ibcon#enter wrdev, iclass 31, count 0 2006.201.07:18:50.52#ibcon#first serial, iclass 31, count 0 2006.201.07:18:50.52#ibcon#enter sib2, iclass 31, count 0 2006.201.07:18:50.52#ibcon#flushed, iclass 31, count 0 2006.201.07:18:50.52#ibcon#about to write, iclass 31, count 0 2006.201.07:18:50.52#ibcon#wrote, iclass 31, count 0 2006.201.07:18:50.52#ibcon#about to read 3, iclass 31, count 0 2006.201.07:18:50.54#ibcon#read 3, iclass 31, count 0 2006.201.07:18:50.54#ibcon#about to read 4, iclass 31, count 0 2006.201.07:18:50.54#ibcon#read 4, iclass 31, count 0 2006.201.07:18:50.54#ibcon#about to read 5, iclass 31, count 0 2006.201.07:18:50.54#ibcon#read 5, iclass 31, count 0 2006.201.07:18:50.54#ibcon#about to read 6, iclass 31, count 0 2006.201.07:18:50.54#ibcon#read 6, iclass 31, count 0 2006.201.07:18:50.54#ibcon#end of sib2, iclass 31, count 0 2006.201.07:18:50.54#ibcon#*mode == 0, iclass 31, count 0 2006.201.07:18:50.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.07:18:50.54#ibcon#[25=USB\r\n] 2006.201.07:18:50.54#ibcon#*before write, iclass 31, count 0 2006.201.07:18:50.54#ibcon#enter sib2, iclass 31, count 0 2006.201.07:18:50.54#ibcon#flushed, iclass 31, count 0 2006.201.07:18:50.54#ibcon#about to write, iclass 31, count 0 2006.201.07:18:50.54#ibcon#wrote, iclass 31, count 0 2006.201.07:18:50.54#ibcon#about to read 3, iclass 31, count 0 2006.201.07:18:50.57#ibcon#read 3, iclass 31, count 0 2006.201.07:18:50.57#ibcon#about to read 4, iclass 31, count 0 2006.201.07:18:50.57#ibcon#read 4, iclass 31, count 0 2006.201.07:18:50.57#ibcon#about to read 5, iclass 31, count 0 2006.201.07:18:50.57#ibcon#read 5, iclass 31, count 0 2006.201.07:18:50.57#ibcon#about to read 6, iclass 31, count 0 2006.201.07:18:50.57#ibcon#read 6, iclass 31, count 0 2006.201.07:18:50.57#ibcon#end of sib2, iclass 31, count 0 2006.201.07:18:50.57#ibcon#*after write, iclass 31, count 0 2006.201.07:18:50.57#ibcon#*before return 0, iclass 31, count 0 2006.201.07:18:50.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:50.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:50.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.07:18:50.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.07:18:50.57$vck44/valo=3,564.99 2006.201.07:18:50.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.07:18:50.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.07:18:50.57#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:50.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:50.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:50.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:50.57#ibcon#enter wrdev, iclass 33, count 0 2006.201.07:18:50.57#ibcon#first serial, iclass 33, count 0 2006.201.07:18:50.57#ibcon#enter sib2, iclass 33, count 0 2006.201.07:18:50.57#ibcon#flushed, iclass 33, count 0 2006.201.07:18:50.57#ibcon#about to write, iclass 33, count 0 2006.201.07:18:50.57#ibcon#wrote, iclass 33, count 0 2006.201.07:18:50.57#ibcon#about to read 3, iclass 33, count 0 2006.201.07:18:50.59#ibcon#read 3, iclass 33, count 0 2006.201.07:18:50.59#ibcon#about to read 4, iclass 33, count 0 2006.201.07:18:50.59#ibcon#read 4, iclass 33, count 0 2006.201.07:18:50.59#ibcon#about to read 5, iclass 33, count 0 2006.201.07:18:50.59#ibcon#read 5, iclass 33, count 0 2006.201.07:18:50.59#ibcon#about to read 6, iclass 33, count 0 2006.201.07:18:50.59#ibcon#read 6, iclass 33, count 0 2006.201.07:18:50.59#ibcon#end of sib2, iclass 33, count 0 2006.201.07:18:50.59#ibcon#*mode == 0, iclass 33, count 0 2006.201.07:18:50.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.07:18:50.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:18:50.59#ibcon#*before write, iclass 33, count 0 2006.201.07:18:50.59#ibcon#enter sib2, iclass 33, count 0 2006.201.07:18:50.59#ibcon#flushed, iclass 33, count 0 2006.201.07:18:50.59#ibcon#about to write, iclass 33, count 0 2006.201.07:18:50.59#ibcon#wrote, iclass 33, count 0 2006.201.07:18:50.59#ibcon#about to read 3, iclass 33, count 0 2006.201.07:18:50.64#ibcon#read 3, iclass 33, count 0 2006.201.07:18:50.64#ibcon#about to read 4, iclass 33, count 0 2006.201.07:18:50.64#ibcon#read 4, iclass 33, count 0 2006.201.07:18:50.64#ibcon#about to read 5, iclass 33, count 0 2006.201.07:18:50.64#ibcon#read 5, iclass 33, count 0 2006.201.07:18:50.64#ibcon#about to read 6, iclass 33, count 0 2006.201.07:18:50.64#ibcon#read 6, iclass 33, count 0 2006.201.07:18:50.64#ibcon#end of sib2, iclass 33, count 0 2006.201.07:18:50.64#ibcon#*after write, iclass 33, count 0 2006.201.07:18:50.64#ibcon#*before return 0, iclass 33, count 0 2006.201.07:18:50.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:50.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:50.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.07:18:50.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.07:18:50.64$vck44/va=3,8 2006.201.07:18:50.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.07:18:50.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.07:18:50.64#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:50.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:50.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:50.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:50.69#ibcon#enter wrdev, iclass 35, count 2 2006.201.07:18:50.69#ibcon#first serial, iclass 35, count 2 2006.201.07:18:50.69#ibcon#enter sib2, iclass 35, count 2 2006.201.07:18:50.69#ibcon#flushed, iclass 35, count 2 2006.201.07:18:50.69#ibcon#about to write, iclass 35, count 2 2006.201.07:18:50.69#ibcon#wrote, iclass 35, count 2 2006.201.07:18:50.69#ibcon#about to read 3, iclass 35, count 2 2006.201.07:18:50.71#ibcon#read 3, iclass 35, count 2 2006.201.07:18:50.71#ibcon#about to read 4, iclass 35, count 2 2006.201.07:18:50.71#ibcon#read 4, iclass 35, count 2 2006.201.07:18:50.71#ibcon#about to read 5, iclass 35, count 2 2006.201.07:18:50.71#ibcon#read 5, iclass 35, count 2 2006.201.07:18:50.71#ibcon#about to read 6, iclass 35, count 2 2006.201.07:18:50.71#ibcon#read 6, iclass 35, count 2 2006.201.07:18:50.71#ibcon#end of sib2, iclass 35, count 2 2006.201.07:18:50.71#ibcon#*mode == 0, iclass 35, count 2 2006.201.07:18:50.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.07:18:50.71#ibcon#[25=AT03-08\r\n] 2006.201.07:18:50.71#ibcon#*before write, iclass 35, count 2 2006.201.07:18:50.71#ibcon#enter sib2, iclass 35, count 2 2006.201.07:18:50.71#ibcon#flushed, iclass 35, count 2 2006.201.07:18:50.71#ibcon#about to write, iclass 35, count 2 2006.201.07:18:50.71#ibcon#wrote, iclass 35, count 2 2006.201.07:18:50.71#ibcon#about to read 3, iclass 35, count 2 2006.201.07:18:50.74#ibcon#read 3, iclass 35, count 2 2006.201.07:18:50.74#ibcon#about to read 4, iclass 35, count 2 2006.201.07:18:50.74#ibcon#read 4, iclass 35, count 2 2006.201.07:18:50.74#ibcon#about to read 5, iclass 35, count 2 2006.201.07:18:50.74#ibcon#read 5, iclass 35, count 2 2006.201.07:18:50.74#ibcon#about to read 6, iclass 35, count 2 2006.201.07:18:50.74#ibcon#read 6, iclass 35, count 2 2006.201.07:18:50.74#ibcon#end of sib2, iclass 35, count 2 2006.201.07:18:50.74#ibcon#*after write, iclass 35, count 2 2006.201.07:18:50.74#ibcon#*before return 0, iclass 35, count 2 2006.201.07:18:50.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:50.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:50.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.07:18:50.74#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:50.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:50.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:50.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:50.86#ibcon#enter wrdev, iclass 35, count 0 2006.201.07:18:50.86#ibcon#first serial, iclass 35, count 0 2006.201.07:18:50.86#ibcon#enter sib2, iclass 35, count 0 2006.201.07:18:50.86#ibcon#flushed, iclass 35, count 0 2006.201.07:18:50.86#ibcon#about to write, iclass 35, count 0 2006.201.07:18:50.86#ibcon#wrote, iclass 35, count 0 2006.201.07:18:50.86#ibcon#about to read 3, iclass 35, count 0 2006.201.07:18:50.88#ibcon#read 3, iclass 35, count 0 2006.201.07:18:50.88#ibcon#about to read 4, iclass 35, count 0 2006.201.07:18:50.88#ibcon#read 4, iclass 35, count 0 2006.201.07:18:50.88#ibcon#about to read 5, iclass 35, count 0 2006.201.07:18:50.88#ibcon#read 5, iclass 35, count 0 2006.201.07:18:50.88#ibcon#about to read 6, iclass 35, count 0 2006.201.07:18:50.88#ibcon#read 6, iclass 35, count 0 2006.201.07:18:50.88#ibcon#end of sib2, iclass 35, count 0 2006.201.07:18:50.88#ibcon#*mode == 0, iclass 35, count 0 2006.201.07:18:50.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.07:18:50.88#ibcon#[25=USB\r\n] 2006.201.07:18:50.88#ibcon#*before write, iclass 35, count 0 2006.201.07:18:50.88#ibcon#enter sib2, iclass 35, count 0 2006.201.07:18:50.88#ibcon#flushed, iclass 35, count 0 2006.201.07:18:50.88#ibcon#about to write, iclass 35, count 0 2006.201.07:18:50.88#ibcon#wrote, iclass 35, count 0 2006.201.07:18:50.88#ibcon#about to read 3, iclass 35, count 0 2006.201.07:18:50.91#ibcon#read 3, iclass 35, count 0 2006.201.07:18:50.91#ibcon#about to read 4, iclass 35, count 0 2006.201.07:18:50.91#ibcon#read 4, iclass 35, count 0 2006.201.07:18:50.91#ibcon#about to read 5, iclass 35, count 0 2006.201.07:18:50.91#ibcon#read 5, iclass 35, count 0 2006.201.07:18:50.91#ibcon#about to read 6, iclass 35, count 0 2006.201.07:18:50.91#ibcon#read 6, iclass 35, count 0 2006.201.07:18:50.91#ibcon#end of sib2, iclass 35, count 0 2006.201.07:18:50.91#ibcon#*after write, iclass 35, count 0 2006.201.07:18:50.91#ibcon#*before return 0, iclass 35, count 0 2006.201.07:18:50.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:50.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:50.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.07:18:50.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.07:18:50.91$vck44/valo=4,624.99 2006.201.07:18:50.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.07:18:50.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.07:18:50.91#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:50.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:50.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:50.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:50.91#ibcon#enter wrdev, iclass 37, count 0 2006.201.07:18:50.91#ibcon#first serial, iclass 37, count 0 2006.201.07:18:50.91#ibcon#enter sib2, iclass 37, count 0 2006.201.07:18:50.91#ibcon#flushed, iclass 37, count 0 2006.201.07:18:50.91#ibcon#about to write, iclass 37, count 0 2006.201.07:18:50.91#ibcon#wrote, iclass 37, count 0 2006.201.07:18:50.91#ibcon#about to read 3, iclass 37, count 0 2006.201.07:18:50.93#ibcon#read 3, iclass 37, count 0 2006.201.07:18:50.93#ibcon#about to read 4, iclass 37, count 0 2006.201.07:18:50.93#ibcon#read 4, iclass 37, count 0 2006.201.07:18:50.93#ibcon#about to read 5, iclass 37, count 0 2006.201.07:18:50.93#ibcon#read 5, iclass 37, count 0 2006.201.07:18:50.93#ibcon#about to read 6, iclass 37, count 0 2006.201.07:18:50.93#ibcon#read 6, iclass 37, count 0 2006.201.07:18:50.93#ibcon#end of sib2, iclass 37, count 0 2006.201.07:18:50.93#ibcon#*mode == 0, iclass 37, count 0 2006.201.07:18:50.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.07:18:50.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:18:50.93#ibcon#*before write, iclass 37, count 0 2006.201.07:18:50.93#ibcon#enter sib2, iclass 37, count 0 2006.201.07:18:50.93#ibcon#flushed, iclass 37, count 0 2006.201.07:18:50.93#ibcon#about to write, iclass 37, count 0 2006.201.07:18:50.93#ibcon#wrote, iclass 37, count 0 2006.201.07:18:50.93#ibcon#about to read 3, iclass 37, count 0 2006.201.07:18:50.97#ibcon#read 3, iclass 37, count 0 2006.201.07:18:50.97#ibcon#about to read 4, iclass 37, count 0 2006.201.07:18:50.97#ibcon#read 4, iclass 37, count 0 2006.201.07:18:50.97#ibcon#about to read 5, iclass 37, count 0 2006.201.07:18:50.97#ibcon#read 5, iclass 37, count 0 2006.201.07:18:50.97#ibcon#about to read 6, iclass 37, count 0 2006.201.07:18:50.97#ibcon#read 6, iclass 37, count 0 2006.201.07:18:50.97#ibcon#end of sib2, iclass 37, count 0 2006.201.07:18:50.97#ibcon#*after write, iclass 37, count 0 2006.201.07:18:50.97#ibcon#*before return 0, iclass 37, count 0 2006.201.07:18:50.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:50.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:50.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.07:18:50.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.07:18:50.97$vck44/va=4,7 2006.201.07:18:50.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.07:18:50.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.07:18:50.97#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:50.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:51.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:51.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:51.03#ibcon#enter wrdev, iclass 39, count 2 2006.201.07:18:51.03#ibcon#first serial, iclass 39, count 2 2006.201.07:18:51.03#ibcon#enter sib2, iclass 39, count 2 2006.201.07:18:51.03#ibcon#flushed, iclass 39, count 2 2006.201.07:18:51.03#ibcon#about to write, iclass 39, count 2 2006.201.07:18:51.03#ibcon#wrote, iclass 39, count 2 2006.201.07:18:51.03#ibcon#about to read 3, iclass 39, count 2 2006.201.07:18:51.05#ibcon#read 3, iclass 39, count 2 2006.201.07:18:51.05#ibcon#about to read 4, iclass 39, count 2 2006.201.07:18:51.05#ibcon#read 4, iclass 39, count 2 2006.201.07:18:51.05#ibcon#about to read 5, iclass 39, count 2 2006.201.07:18:51.05#ibcon#read 5, iclass 39, count 2 2006.201.07:18:51.05#ibcon#about to read 6, iclass 39, count 2 2006.201.07:18:51.05#ibcon#read 6, iclass 39, count 2 2006.201.07:18:51.05#ibcon#end of sib2, iclass 39, count 2 2006.201.07:18:51.05#ibcon#*mode == 0, iclass 39, count 2 2006.201.07:18:51.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.07:18:51.05#ibcon#[25=AT04-07\r\n] 2006.201.07:18:51.05#ibcon#*before write, iclass 39, count 2 2006.201.07:18:51.05#ibcon#enter sib2, iclass 39, count 2 2006.201.07:18:51.05#ibcon#flushed, iclass 39, count 2 2006.201.07:18:51.05#ibcon#about to write, iclass 39, count 2 2006.201.07:18:51.05#ibcon#wrote, iclass 39, count 2 2006.201.07:18:51.05#ibcon#about to read 3, iclass 39, count 2 2006.201.07:18:51.08#ibcon#read 3, iclass 39, count 2 2006.201.07:18:51.08#ibcon#about to read 4, iclass 39, count 2 2006.201.07:18:51.08#ibcon#read 4, iclass 39, count 2 2006.201.07:18:51.08#ibcon#about to read 5, iclass 39, count 2 2006.201.07:18:51.08#ibcon#read 5, iclass 39, count 2 2006.201.07:18:51.08#ibcon#about to read 6, iclass 39, count 2 2006.201.07:18:51.08#ibcon#read 6, iclass 39, count 2 2006.201.07:18:51.08#ibcon#end of sib2, iclass 39, count 2 2006.201.07:18:51.08#ibcon#*after write, iclass 39, count 2 2006.201.07:18:51.08#ibcon#*before return 0, iclass 39, count 2 2006.201.07:18:51.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:51.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:51.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.07:18:51.08#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:51.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:51.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:51.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:51.20#ibcon#enter wrdev, iclass 39, count 0 2006.201.07:18:51.20#ibcon#first serial, iclass 39, count 0 2006.201.07:18:51.20#ibcon#enter sib2, iclass 39, count 0 2006.201.07:18:51.20#ibcon#flushed, iclass 39, count 0 2006.201.07:18:51.20#ibcon#about to write, iclass 39, count 0 2006.201.07:18:51.20#ibcon#wrote, iclass 39, count 0 2006.201.07:18:51.20#ibcon#about to read 3, iclass 39, count 0 2006.201.07:18:51.22#ibcon#read 3, iclass 39, count 0 2006.201.07:18:51.22#ibcon#about to read 4, iclass 39, count 0 2006.201.07:18:51.22#ibcon#read 4, iclass 39, count 0 2006.201.07:18:51.22#ibcon#about to read 5, iclass 39, count 0 2006.201.07:18:51.22#ibcon#read 5, iclass 39, count 0 2006.201.07:18:51.22#ibcon#about to read 6, iclass 39, count 0 2006.201.07:18:51.22#ibcon#read 6, iclass 39, count 0 2006.201.07:18:51.22#ibcon#end of sib2, iclass 39, count 0 2006.201.07:18:51.22#ibcon#*mode == 0, iclass 39, count 0 2006.201.07:18:51.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.07:18:51.22#ibcon#[25=USB\r\n] 2006.201.07:18:51.22#ibcon#*before write, iclass 39, count 0 2006.201.07:18:51.22#ibcon#enter sib2, iclass 39, count 0 2006.201.07:18:51.22#ibcon#flushed, iclass 39, count 0 2006.201.07:18:51.22#ibcon#about to write, iclass 39, count 0 2006.201.07:18:51.22#ibcon#wrote, iclass 39, count 0 2006.201.07:18:51.22#ibcon#about to read 3, iclass 39, count 0 2006.201.07:18:51.25#ibcon#read 3, iclass 39, count 0 2006.201.07:18:51.25#ibcon#about to read 4, iclass 39, count 0 2006.201.07:18:51.25#ibcon#read 4, iclass 39, count 0 2006.201.07:18:51.25#ibcon#about to read 5, iclass 39, count 0 2006.201.07:18:51.25#ibcon#read 5, iclass 39, count 0 2006.201.07:18:51.25#ibcon#about to read 6, iclass 39, count 0 2006.201.07:18:51.25#ibcon#read 6, iclass 39, count 0 2006.201.07:18:51.25#ibcon#end of sib2, iclass 39, count 0 2006.201.07:18:51.25#ibcon#*after write, iclass 39, count 0 2006.201.07:18:51.25#ibcon#*before return 0, iclass 39, count 0 2006.201.07:18:51.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:51.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:51.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.07:18:51.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.07:18:51.25$vck44/valo=5,734.99 2006.201.07:18:51.25#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.07:18:51.25#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.07:18:51.25#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:51.25#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:51.25#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:51.25#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:51.25#ibcon#enter wrdev, iclass 2, count 0 2006.201.07:18:51.25#ibcon#first serial, iclass 2, count 0 2006.201.07:18:51.25#ibcon#enter sib2, iclass 2, count 0 2006.201.07:18:51.25#ibcon#flushed, iclass 2, count 0 2006.201.07:18:51.25#ibcon#about to write, iclass 2, count 0 2006.201.07:18:51.25#ibcon#wrote, iclass 2, count 0 2006.201.07:18:51.25#ibcon#about to read 3, iclass 2, count 0 2006.201.07:18:51.27#ibcon#read 3, iclass 2, count 0 2006.201.07:18:51.27#ibcon#about to read 4, iclass 2, count 0 2006.201.07:18:51.27#ibcon#read 4, iclass 2, count 0 2006.201.07:18:51.27#ibcon#about to read 5, iclass 2, count 0 2006.201.07:18:51.27#ibcon#read 5, iclass 2, count 0 2006.201.07:18:51.27#ibcon#about to read 6, iclass 2, count 0 2006.201.07:18:51.27#ibcon#read 6, iclass 2, count 0 2006.201.07:18:51.27#ibcon#end of sib2, iclass 2, count 0 2006.201.07:18:51.27#ibcon#*mode == 0, iclass 2, count 0 2006.201.07:18:51.27#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.07:18:51.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:18:51.27#ibcon#*before write, iclass 2, count 0 2006.201.07:18:51.27#ibcon#enter sib2, iclass 2, count 0 2006.201.07:18:51.27#ibcon#flushed, iclass 2, count 0 2006.201.07:18:51.27#ibcon#about to write, iclass 2, count 0 2006.201.07:18:51.27#ibcon#wrote, iclass 2, count 0 2006.201.07:18:51.27#ibcon#about to read 3, iclass 2, count 0 2006.201.07:18:51.31#ibcon#read 3, iclass 2, count 0 2006.201.07:18:51.31#ibcon#about to read 4, iclass 2, count 0 2006.201.07:18:51.31#ibcon#read 4, iclass 2, count 0 2006.201.07:18:51.31#ibcon#about to read 5, iclass 2, count 0 2006.201.07:18:51.31#ibcon#read 5, iclass 2, count 0 2006.201.07:18:51.31#ibcon#about to read 6, iclass 2, count 0 2006.201.07:18:51.31#ibcon#read 6, iclass 2, count 0 2006.201.07:18:51.31#ibcon#end of sib2, iclass 2, count 0 2006.201.07:18:51.31#ibcon#*after write, iclass 2, count 0 2006.201.07:18:51.31#ibcon#*before return 0, iclass 2, count 0 2006.201.07:18:51.31#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:51.31#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:51.31#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.07:18:51.31#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.07:18:51.31$vck44/va=5,4 2006.201.07:18:51.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.07:18:51.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.07:18:51.31#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:51.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:51.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:51.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:51.37#ibcon#enter wrdev, iclass 5, count 2 2006.201.07:18:51.37#ibcon#first serial, iclass 5, count 2 2006.201.07:18:51.37#ibcon#enter sib2, iclass 5, count 2 2006.201.07:18:51.37#ibcon#flushed, iclass 5, count 2 2006.201.07:18:51.37#ibcon#about to write, iclass 5, count 2 2006.201.07:18:51.37#ibcon#wrote, iclass 5, count 2 2006.201.07:18:51.37#ibcon#about to read 3, iclass 5, count 2 2006.201.07:18:51.39#ibcon#read 3, iclass 5, count 2 2006.201.07:18:51.39#ibcon#about to read 4, iclass 5, count 2 2006.201.07:18:51.39#ibcon#read 4, iclass 5, count 2 2006.201.07:18:51.39#ibcon#about to read 5, iclass 5, count 2 2006.201.07:18:51.39#ibcon#read 5, iclass 5, count 2 2006.201.07:18:51.39#ibcon#about to read 6, iclass 5, count 2 2006.201.07:18:51.39#ibcon#read 6, iclass 5, count 2 2006.201.07:18:51.39#ibcon#end of sib2, iclass 5, count 2 2006.201.07:18:51.39#ibcon#*mode == 0, iclass 5, count 2 2006.201.07:18:51.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.07:18:51.39#ibcon#[25=AT05-04\r\n] 2006.201.07:18:51.39#ibcon#*before write, iclass 5, count 2 2006.201.07:18:51.39#ibcon#enter sib2, iclass 5, count 2 2006.201.07:18:51.39#ibcon#flushed, iclass 5, count 2 2006.201.07:18:51.39#ibcon#about to write, iclass 5, count 2 2006.201.07:18:51.39#ibcon#wrote, iclass 5, count 2 2006.201.07:18:51.39#ibcon#about to read 3, iclass 5, count 2 2006.201.07:18:51.42#ibcon#read 3, iclass 5, count 2 2006.201.07:18:51.42#ibcon#about to read 4, iclass 5, count 2 2006.201.07:18:51.42#ibcon#read 4, iclass 5, count 2 2006.201.07:18:51.42#ibcon#about to read 5, iclass 5, count 2 2006.201.07:18:51.42#ibcon#read 5, iclass 5, count 2 2006.201.07:18:51.42#ibcon#about to read 6, iclass 5, count 2 2006.201.07:18:51.42#ibcon#read 6, iclass 5, count 2 2006.201.07:18:51.42#ibcon#end of sib2, iclass 5, count 2 2006.201.07:18:51.42#ibcon#*after write, iclass 5, count 2 2006.201.07:18:51.42#ibcon#*before return 0, iclass 5, count 2 2006.201.07:18:51.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:51.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:51.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.07:18:51.42#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:51.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:51.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:51.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:51.54#ibcon#enter wrdev, iclass 5, count 0 2006.201.07:18:51.54#ibcon#first serial, iclass 5, count 0 2006.201.07:18:51.54#ibcon#enter sib2, iclass 5, count 0 2006.201.07:18:51.54#ibcon#flushed, iclass 5, count 0 2006.201.07:18:51.54#ibcon#about to write, iclass 5, count 0 2006.201.07:18:51.54#ibcon#wrote, iclass 5, count 0 2006.201.07:18:51.54#ibcon#about to read 3, iclass 5, count 0 2006.201.07:18:51.56#ibcon#read 3, iclass 5, count 0 2006.201.07:18:51.56#ibcon#about to read 4, iclass 5, count 0 2006.201.07:18:51.56#ibcon#read 4, iclass 5, count 0 2006.201.07:18:51.56#ibcon#about to read 5, iclass 5, count 0 2006.201.07:18:51.56#ibcon#read 5, iclass 5, count 0 2006.201.07:18:51.56#ibcon#about to read 6, iclass 5, count 0 2006.201.07:18:51.56#ibcon#read 6, iclass 5, count 0 2006.201.07:18:51.56#ibcon#end of sib2, iclass 5, count 0 2006.201.07:18:51.56#ibcon#*mode == 0, iclass 5, count 0 2006.201.07:18:51.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.07:18:51.56#ibcon#[25=USB\r\n] 2006.201.07:18:51.56#ibcon#*before write, iclass 5, count 0 2006.201.07:18:51.56#ibcon#enter sib2, iclass 5, count 0 2006.201.07:18:51.56#ibcon#flushed, iclass 5, count 0 2006.201.07:18:51.56#ibcon#about to write, iclass 5, count 0 2006.201.07:18:51.56#ibcon#wrote, iclass 5, count 0 2006.201.07:18:51.56#ibcon#about to read 3, iclass 5, count 0 2006.201.07:18:51.59#ibcon#read 3, iclass 5, count 0 2006.201.07:18:51.59#ibcon#about to read 4, iclass 5, count 0 2006.201.07:18:51.59#ibcon#read 4, iclass 5, count 0 2006.201.07:18:51.59#ibcon#about to read 5, iclass 5, count 0 2006.201.07:18:51.59#ibcon#read 5, iclass 5, count 0 2006.201.07:18:51.59#ibcon#about to read 6, iclass 5, count 0 2006.201.07:18:51.59#ibcon#read 6, iclass 5, count 0 2006.201.07:18:51.59#ibcon#end of sib2, iclass 5, count 0 2006.201.07:18:51.59#ibcon#*after write, iclass 5, count 0 2006.201.07:18:51.59#ibcon#*before return 0, iclass 5, count 0 2006.201.07:18:51.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:51.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:51.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.07:18:51.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.07:18:51.59$vck44/valo=6,814.99 2006.201.07:18:51.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.07:18:51.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.07:18:51.59#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:51.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:51.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:51.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:51.59#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:18:51.59#ibcon#first serial, iclass 7, count 0 2006.201.07:18:51.59#ibcon#enter sib2, iclass 7, count 0 2006.201.07:18:51.59#ibcon#flushed, iclass 7, count 0 2006.201.07:18:51.59#ibcon#about to write, iclass 7, count 0 2006.201.07:18:51.59#ibcon#wrote, iclass 7, count 0 2006.201.07:18:51.59#ibcon#about to read 3, iclass 7, count 0 2006.201.07:18:51.61#ibcon#read 3, iclass 7, count 0 2006.201.07:18:51.61#ibcon#about to read 4, iclass 7, count 0 2006.201.07:18:51.61#ibcon#read 4, iclass 7, count 0 2006.201.07:18:51.61#ibcon#about to read 5, iclass 7, count 0 2006.201.07:18:51.61#ibcon#read 5, iclass 7, count 0 2006.201.07:18:51.61#ibcon#about to read 6, iclass 7, count 0 2006.201.07:18:51.61#ibcon#read 6, iclass 7, count 0 2006.201.07:18:51.61#ibcon#end of sib2, iclass 7, count 0 2006.201.07:18:51.61#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:18:51.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:18:51.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:18:51.61#ibcon#*before write, iclass 7, count 0 2006.201.07:18:51.61#ibcon#enter sib2, iclass 7, count 0 2006.201.07:18:51.61#ibcon#flushed, iclass 7, count 0 2006.201.07:18:51.61#ibcon#about to write, iclass 7, count 0 2006.201.07:18:51.61#ibcon#wrote, iclass 7, count 0 2006.201.07:18:51.61#ibcon#about to read 3, iclass 7, count 0 2006.201.07:18:51.66#ibcon#read 3, iclass 7, count 0 2006.201.07:18:51.66#ibcon#about to read 4, iclass 7, count 0 2006.201.07:18:51.66#ibcon#read 4, iclass 7, count 0 2006.201.07:18:51.66#ibcon#about to read 5, iclass 7, count 0 2006.201.07:18:51.66#ibcon#read 5, iclass 7, count 0 2006.201.07:18:51.66#ibcon#about to read 6, iclass 7, count 0 2006.201.07:18:51.66#ibcon#read 6, iclass 7, count 0 2006.201.07:18:51.66#ibcon#end of sib2, iclass 7, count 0 2006.201.07:18:51.66#ibcon#*after write, iclass 7, count 0 2006.201.07:18:51.66#ibcon#*before return 0, iclass 7, count 0 2006.201.07:18:51.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:51.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:51.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:18:51.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:18:51.66$vck44/va=6,5 2006.201.07:18:51.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.07:18:51.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.07:18:51.66#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:51.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:51.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:51.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:51.71#ibcon#enter wrdev, iclass 11, count 2 2006.201.07:18:51.71#ibcon#first serial, iclass 11, count 2 2006.201.07:18:51.71#ibcon#enter sib2, iclass 11, count 2 2006.201.07:18:51.71#ibcon#flushed, iclass 11, count 2 2006.201.07:18:51.71#ibcon#about to write, iclass 11, count 2 2006.201.07:18:51.71#ibcon#wrote, iclass 11, count 2 2006.201.07:18:51.71#ibcon#about to read 3, iclass 11, count 2 2006.201.07:18:51.73#ibcon#read 3, iclass 11, count 2 2006.201.07:18:51.73#ibcon#about to read 4, iclass 11, count 2 2006.201.07:18:51.73#ibcon#read 4, iclass 11, count 2 2006.201.07:18:51.73#ibcon#about to read 5, iclass 11, count 2 2006.201.07:18:51.73#ibcon#read 5, iclass 11, count 2 2006.201.07:18:51.73#ibcon#about to read 6, iclass 11, count 2 2006.201.07:18:51.73#ibcon#read 6, iclass 11, count 2 2006.201.07:18:51.73#ibcon#end of sib2, iclass 11, count 2 2006.201.07:18:51.73#ibcon#*mode == 0, iclass 11, count 2 2006.201.07:18:51.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.07:18:51.73#ibcon#[25=AT06-05\r\n] 2006.201.07:18:51.73#ibcon#*before write, iclass 11, count 2 2006.201.07:18:51.73#ibcon#enter sib2, iclass 11, count 2 2006.201.07:18:51.73#ibcon#flushed, iclass 11, count 2 2006.201.07:18:51.73#ibcon#about to write, iclass 11, count 2 2006.201.07:18:51.73#ibcon#wrote, iclass 11, count 2 2006.201.07:18:51.73#ibcon#about to read 3, iclass 11, count 2 2006.201.07:18:51.76#ibcon#read 3, iclass 11, count 2 2006.201.07:18:51.76#ibcon#about to read 4, iclass 11, count 2 2006.201.07:18:51.76#ibcon#read 4, iclass 11, count 2 2006.201.07:18:51.76#ibcon#about to read 5, iclass 11, count 2 2006.201.07:18:51.76#ibcon#read 5, iclass 11, count 2 2006.201.07:18:51.76#ibcon#about to read 6, iclass 11, count 2 2006.201.07:18:51.76#ibcon#read 6, iclass 11, count 2 2006.201.07:18:51.76#ibcon#end of sib2, iclass 11, count 2 2006.201.07:18:51.76#ibcon#*after write, iclass 11, count 2 2006.201.07:18:51.76#ibcon#*before return 0, iclass 11, count 2 2006.201.07:18:51.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:51.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:51.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.07:18:51.76#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:51.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:51.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:51.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:51.88#ibcon#enter wrdev, iclass 11, count 0 2006.201.07:18:51.88#ibcon#first serial, iclass 11, count 0 2006.201.07:18:51.88#ibcon#enter sib2, iclass 11, count 0 2006.201.07:18:51.88#ibcon#flushed, iclass 11, count 0 2006.201.07:18:51.88#ibcon#about to write, iclass 11, count 0 2006.201.07:18:51.88#ibcon#wrote, iclass 11, count 0 2006.201.07:18:51.88#ibcon#about to read 3, iclass 11, count 0 2006.201.07:18:51.90#ibcon#read 3, iclass 11, count 0 2006.201.07:18:51.90#ibcon#about to read 4, iclass 11, count 0 2006.201.07:18:51.90#ibcon#read 4, iclass 11, count 0 2006.201.07:18:51.90#ibcon#about to read 5, iclass 11, count 0 2006.201.07:18:51.90#ibcon#read 5, iclass 11, count 0 2006.201.07:18:51.90#ibcon#about to read 6, iclass 11, count 0 2006.201.07:18:51.90#ibcon#read 6, iclass 11, count 0 2006.201.07:18:51.90#ibcon#end of sib2, iclass 11, count 0 2006.201.07:18:51.90#ibcon#*mode == 0, iclass 11, count 0 2006.201.07:18:51.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.07:18:51.90#ibcon#[25=USB\r\n] 2006.201.07:18:51.90#ibcon#*before write, iclass 11, count 0 2006.201.07:18:51.90#ibcon#enter sib2, iclass 11, count 0 2006.201.07:18:51.90#ibcon#flushed, iclass 11, count 0 2006.201.07:18:51.90#ibcon#about to write, iclass 11, count 0 2006.201.07:18:51.90#ibcon#wrote, iclass 11, count 0 2006.201.07:18:51.90#ibcon#about to read 3, iclass 11, count 0 2006.201.07:18:51.93#ibcon#read 3, iclass 11, count 0 2006.201.07:18:51.93#ibcon#about to read 4, iclass 11, count 0 2006.201.07:18:51.93#ibcon#read 4, iclass 11, count 0 2006.201.07:18:51.93#ibcon#about to read 5, iclass 11, count 0 2006.201.07:18:51.93#ibcon#read 5, iclass 11, count 0 2006.201.07:18:51.93#ibcon#about to read 6, iclass 11, count 0 2006.201.07:18:51.93#ibcon#read 6, iclass 11, count 0 2006.201.07:18:51.93#ibcon#end of sib2, iclass 11, count 0 2006.201.07:18:51.93#ibcon#*after write, iclass 11, count 0 2006.201.07:18:51.93#ibcon#*before return 0, iclass 11, count 0 2006.201.07:18:51.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:51.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:51.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.07:18:51.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.07:18:51.93$vck44/valo=7,864.99 2006.201.07:18:51.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.07:18:51.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.07:18:51.93#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:51.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:51.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:51.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:51.93#ibcon#enter wrdev, iclass 13, count 0 2006.201.07:18:51.93#ibcon#first serial, iclass 13, count 0 2006.201.07:18:51.93#ibcon#enter sib2, iclass 13, count 0 2006.201.07:18:51.93#ibcon#flushed, iclass 13, count 0 2006.201.07:18:51.93#ibcon#about to write, iclass 13, count 0 2006.201.07:18:51.93#ibcon#wrote, iclass 13, count 0 2006.201.07:18:51.93#ibcon#about to read 3, iclass 13, count 0 2006.201.07:18:51.95#ibcon#read 3, iclass 13, count 0 2006.201.07:18:51.95#ibcon#about to read 4, iclass 13, count 0 2006.201.07:18:51.95#ibcon#read 4, iclass 13, count 0 2006.201.07:18:51.95#ibcon#about to read 5, iclass 13, count 0 2006.201.07:18:51.95#ibcon#read 5, iclass 13, count 0 2006.201.07:18:51.95#ibcon#about to read 6, iclass 13, count 0 2006.201.07:18:51.95#ibcon#read 6, iclass 13, count 0 2006.201.07:18:51.95#ibcon#end of sib2, iclass 13, count 0 2006.201.07:18:51.95#ibcon#*mode == 0, iclass 13, count 0 2006.201.07:18:51.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.07:18:51.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:18:51.95#ibcon#*before write, iclass 13, count 0 2006.201.07:18:51.95#ibcon#enter sib2, iclass 13, count 0 2006.201.07:18:51.95#ibcon#flushed, iclass 13, count 0 2006.201.07:18:51.95#ibcon#about to write, iclass 13, count 0 2006.201.07:18:51.95#ibcon#wrote, iclass 13, count 0 2006.201.07:18:51.95#ibcon#about to read 3, iclass 13, count 0 2006.201.07:18:51.99#ibcon#read 3, iclass 13, count 0 2006.201.07:18:51.99#ibcon#about to read 4, iclass 13, count 0 2006.201.07:18:51.99#ibcon#read 4, iclass 13, count 0 2006.201.07:18:51.99#ibcon#about to read 5, iclass 13, count 0 2006.201.07:18:51.99#ibcon#read 5, iclass 13, count 0 2006.201.07:18:51.99#ibcon#about to read 6, iclass 13, count 0 2006.201.07:18:51.99#ibcon#read 6, iclass 13, count 0 2006.201.07:18:51.99#ibcon#end of sib2, iclass 13, count 0 2006.201.07:18:51.99#ibcon#*after write, iclass 13, count 0 2006.201.07:18:51.99#ibcon#*before return 0, iclass 13, count 0 2006.201.07:18:51.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:51.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:51.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.07:18:51.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.07:18:51.99$vck44/va=7,5 2006.201.07:18:51.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.07:18:51.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.07:18:51.99#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:51.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:52.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:52.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:52.05#ibcon#enter wrdev, iclass 15, count 2 2006.201.07:18:52.05#ibcon#first serial, iclass 15, count 2 2006.201.07:18:52.05#ibcon#enter sib2, iclass 15, count 2 2006.201.07:18:52.05#ibcon#flushed, iclass 15, count 2 2006.201.07:18:52.05#ibcon#about to write, iclass 15, count 2 2006.201.07:18:52.05#ibcon#wrote, iclass 15, count 2 2006.201.07:18:52.05#ibcon#about to read 3, iclass 15, count 2 2006.201.07:18:52.07#ibcon#read 3, iclass 15, count 2 2006.201.07:18:52.07#ibcon#about to read 4, iclass 15, count 2 2006.201.07:18:52.07#ibcon#read 4, iclass 15, count 2 2006.201.07:18:52.07#ibcon#about to read 5, iclass 15, count 2 2006.201.07:18:52.07#ibcon#read 5, iclass 15, count 2 2006.201.07:18:52.07#ibcon#about to read 6, iclass 15, count 2 2006.201.07:18:52.07#ibcon#read 6, iclass 15, count 2 2006.201.07:18:52.07#ibcon#end of sib2, iclass 15, count 2 2006.201.07:18:52.07#ibcon#*mode == 0, iclass 15, count 2 2006.201.07:18:52.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.07:18:52.07#ibcon#[25=AT07-05\r\n] 2006.201.07:18:52.07#ibcon#*before write, iclass 15, count 2 2006.201.07:18:52.07#ibcon#enter sib2, iclass 15, count 2 2006.201.07:18:52.07#ibcon#flushed, iclass 15, count 2 2006.201.07:18:52.07#ibcon#about to write, iclass 15, count 2 2006.201.07:18:52.07#ibcon#wrote, iclass 15, count 2 2006.201.07:18:52.07#ibcon#about to read 3, iclass 15, count 2 2006.201.07:18:52.10#ibcon#read 3, iclass 15, count 2 2006.201.07:18:52.10#ibcon#about to read 4, iclass 15, count 2 2006.201.07:18:52.10#ibcon#read 4, iclass 15, count 2 2006.201.07:18:52.10#ibcon#about to read 5, iclass 15, count 2 2006.201.07:18:52.10#ibcon#read 5, iclass 15, count 2 2006.201.07:18:52.10#ibcon#about to read 6, iclass 15, count 2 2006.201.07:18:52.10#ibcon#read 6, iclass 15, count 2 2006.201.07:18:52.10#ibcon#end of sib2, iclass 15, count 2 2006.201.07:18:52.10#ibcon#*after write, iclass 15, count 2 2006.201.07:18:52.10#ibcon#*before return 0, iclass 15, count 2 2006.201.07:18:52.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:52.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:52.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.07:18:52.10#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:52.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:52.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:52.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:52.22#ibcon#enter wrdev, iclass 15, count 0 2006.201.07:18:52.22#ibcon#first serial, iclass 15, count 0 2006.201.07:18:52.22#ibcon#enter sib2, iclass 15, count 0 2006.201.07:18:52.22#ibcon#flushed, iclass 15, count 0 2006.201.07:18:52.22#ibcon#about to write, iclass 15, count 0 2006.201.07:18:52.22#ibcon#wrote, iclass 15, count 0 2006.201.07:18:52.22#ibcon#about to read 3, iclass 15, count 0 2006.201.07:18:52.24#ibcon#read 3, iclass 15, count 0 2006.201.07:18:52.24#ibcon#about to read 4, iclass 15, count 0 2006.201.07:18:52.24#ibcon#read 4, iclass 15, count 0 2006.201.07:18:52.24#ibcon#about to read 5, iclass 15, count 0 2006.201.07:18:52.24#ibcon#read 5, iclass 15, count 0 2006.201.07:18:52.24#ibcon#about to read 6, iclass 15, count 0 2006.201.07:18:52.24#ibcon#read 6, iclass 15, count 0 2006.201.07:18:52.24#ibcon#end of sib2, iclass 15, count 0 2006.201.07:18:52.24#ibcon#*mode == 0, iclass 15, count 0 2006.201.07:18:52.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.07:18:52.24#ibcon#[25=USB\r\n] 2006.201.07:18:52.24#ibcon#*before write, iclass 15, count 0 2006.201.07:18:52.24#ibcon#enter sib2, iclass 15, count 0 2006.201.07:18:52.24#ibcon#flushed, iclass 15, count 0 2006.201.07:18:52.24#ibcon#about to write, iclass 15, count 0 2006.201.07:18:52.24#ibcon#wrote, iclass 15, count 0 2006.201.07:18:52.24#ibcon#about to read 3, iclass 15, count 0 2006.201.07:18:52.27#ibcon#read 3, iclass 15, count 0 2006.201.07:18:52.27#ibcon#about to read 4, iclass 15, count 0 2006.201.07:18:52.27#ibcon#read 4, iclass 15, count 0 2006.201.07:18:52.27#ibcon#about to read 5, iclass 15, count 0 2006.201.07:18:52.27#ibcon#read 5, iclass 15, count 0 2006.201.07:18:52.27#ibcon#about to read 6, iclass 15, count 0 2006.201.07:18:52.27#ibcon#read 6, iclass 15, count 0 2006.201.07:18:52.27#ibcon#end of sib2, iclass 15, count 0 2006.201.07:18:52.27#ibcon#*after write, iclass 15, count 0 2006.201.07:18:52.27#ibcon#*before return 0, iclass 15, count 0 2006.201.07:18:52.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:52.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:52.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.07:18:52.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.07:18:52.27$vck44/valo=8,884.99 2006.201.07:18:52.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.07:18:52.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.07:18:52.27#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:52.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:52.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:52.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:52.27#ibcon#enter wrdev, iclass 17, count 0 2006.201.07:18:52.27#ibcon#first serial, iclass 17, count 0 2006.201.07:18:52.27#ibcon#enter sib2, iclass 17, count 0 2006.201.07:18:52.27#ibcon#flushed, iclass 17, count 0 2006.201.07:18:52.27#ibcon#about to write, iclass 17, count 0 2006.201.07:18:52.27#ibcon#wrote, iclass 17, count 0 2006.201.07:18:52.27#ibcon#about to read 3, iclass 17, count 0 2006.201.07:18:52.29#ibcon#read 3, iclass 17, count 0 2006.201.07:18:52.29#ibcon#about to read 4, iclass 17, count 0 2006.201.07:18:52.29#ibcon#read 4, iclass 17, count 0 2006.201.07:18:52.29#ibcon#about to read 5, iclass 17, count 0 2006.201.07:18:52.29#ibcon#read 5, iclass 17, count 0 2006.201.07:18:52.29#ibcon#about to read 6, iclass 17, count 0 2006.201.07:18:52.29#ibcon#read 6, iclass 17, count 0 2006.201.07:18:52.29#ibcon#end of sib2, iclass 17, count 0 2006.201.07:18:52.29#ibcon#*mode == 0, iclass 17, count 0 2006.201.07:18:52.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.07:18:52.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:18:52.29#ibcon#*before write, iclass 17, count 0 2006.201.07:18:52.29#ibcon#enter sib2, iclass 17, count 0 2006.201.07:18:52.29#ibcon#flushed, iclass 17, count 0 2006.201.07:18:52.29#ibcon#about to write, iclass 17, count 0 2006.201.07:18:52.29#ibcon#wrote, iclass 17, count 0 2006.201.07:18:52.29#ibcon#about to read 3, iclass 17, count 0 2006.201.07:18:52.33#ibcon#read 3, iclass 17, count 0 2006.201.07:18:52.33#ibcon#about to read 4, iclass 17, count 0 2006.201.07:18:52.33#ibcon#read 4, iclass 17, count 0 2006.201.07:18:52.33#ibcon#about to read 5, iclass 17, count 0 2006.201.07:18:52.33#ibcon#read 5, iclass 17, count 0 2006.201.07:18:52.33#ibcon#about to read 6, iclass 17, count 0 2006.201.07:18:52.33#ibcon#read 6, iclass 17, count 0 2006.201.07:18:52.33#ibcon#end of sib2, iclass 17, count 0 2006.201.07:18:52.33#ibcon#*after write, iclass 17, count 0 2006.201.07:18:52.33#ibcon#*before return 0, iclass 17, count 0 2006.201.07:18:52.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:52.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:52.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.07:18:52.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.07:18:52.33$vck44/va=8,4 2006.201.07:18:52.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.07:18:52.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.07:18:52.33#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:52.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:18:52.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:18:52.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:18:52.39#ibcon#enter wrdev, iclass 19, count 2 2006.201.07:18:52.39#ibcon#first serial, iclass 19, count 2 2006.201.07:18:52.39#ibcon#enter sib2, iclass 19, count 2 2006.201.07:18:52.39#ibcon#flushed, iclass 19, count 2 2006.201.07:18:52.39#ibcon#about to write, iclass 19, count 2 2006.201.07:18:52.39#ibcon#wrote, iclass 19, count 2 2006.201.07:18:52.39#ibcon#about to read 3, iclass 19, count 2 2006.201.07:18:52.41#ibcon#read 3, iclass 19, count 2 2006.201.07:18:52.41#ibcon#about to read 4, iclass 19, count 2 2006.201.07:18:52.41#ibcon#read 4, iclass 19, count 2 2006.201.07:18:52.41#ibcon#about to read 5, iclass 19, count 2 2006.201.07:18:52.41#ibcon#read 5, iclass 19, count 2 2006.201.07:18:52.41#ibcon#about to read 6, iclass 19, count 2 2006.201.07:18:52.41#ibcon#read 6, iclass 19, count 2 2006.201.07:18:52.41#ibcon#end of sib2, iclass 19, count 2 2006.201.07:18:52.41#ibcon#*mode == 0, iclass 19, count 2 2006.201.07:18:52.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.07:18:52.41#ibcon#[25=AT08-04\r\n] 2006.201.07:18:52.41#ibcon#*before write, iclass 19, count 2 2006.201.07:18:52.41#ibcon#enter sib2, iclass 19, count 2 2006.201.07:18:52.41#ibcon#flushed, iclass 19, count 2 2006.201.07:18:52.41#ibcon#about to write, iclass 19, count 2 2006.201.07:18:52.41#ibcon#wrote, iclass 19, count 2 2006.201.07:18:52.41#ibcon#about to read 3, iclass 19, count 2 2006.201.07:18:52.44#ibcon#read 3, iclass 19, count 2 2006.201.07:18:52.44#ibcon#about to read 4, iclass 19, count 2 2006.201.07:18:52.44#ibcon#read 4, iclass 19, count 2 2006.201.07:18:52.44#ibcon#about to read 5, iclass 19, count 2 2006.201.07:18:52.44#ibcon#read 5, iclass 19, count 2 2006.201.07:18:52.44#ibcon#about to read 6, iclass 19, count 2 2006.201.07:18:52.44#ibcon#read 6, iclass 19, count 2 2006.201.07:18:52.44#ibcon#end of sib2, iclass 19, count 2 2006.201.07:18:52.44#ibcon#*after write, iclass 19, count 2 2006.201.07:18:52.44#ibcon#*before return 0, iclass 19, count 2 2006.201.07:18:52.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:18:52.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:18:52.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.07:18:52.44#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:52.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:18:52.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:18:52.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:18:52.56#ibcon#enter wrdev, iclass 19, count 0 2006.201.07:18:52.56#ibcon#first serial, iclass 19, count 0 2006.201.07:18:52.56#ibcon#enter sib2, iclass 19, count 0 2006.201.07:18:52.56#ibcon#flushed, iclass 19, count 0 2006.201.07:18:52.56#ibcon#about to write, iclass 19, count 0 2006.201.07:18:52.56#ibcon#wrote, iclass 19, count 0 2006.201.07:18:52.56#ibcon#about to read 3, iclass 19, count 0 2006.201.07:18:52.58#ibcon#read 3, iclass 19, count 0 2006.201.07:18:52.58#ibcon#about to read 4, iclass 19, count 0 2006.201.07:18:52.58#ibcon#read 4, iclass 19, count 0 2006.201.07:18:52.58#ibcon#about to read 5, iclass 19, count 0 2006.201.07:18:52.58#ibcon#read 5, iclass 19, count 0 2006.201.07:18:52.58#ibcon#about to read 6, iclass 19, count 0 2006.201.07:18:52.58#ibcon#read 6, iclass 19, count 0 2006.201.07:18:52.58#ibcon#end of sib2, iclass 19, count 0 2006.201.07:18:52.58#ibcon#*mode == 0, iclass 19, count 0 2006.201.07:18:52.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.07:18:52.58#ibcon#[25=USB\r\n] 2006.201.07:18:52.58#ibcon#*before write, iclass 19, count 0 2006.201.07:18:52.58#ibcon#enter sib2, iclass 19, count 0 2006.201.07:18:52.58#ibcon#flushed, iclass 19, count 0 2006.201.07:18:52.58#ibcon#about to write, iclass 19, count 0 2006.201.07:18:52.58#ibcon#wrote, iclass 19, count 0 2006.201.07:18:52.58#ibcon#about to read 3, iclass 19, count 0 2006.201.07:18:52.61#ibcon#read 3, iclass 19, count 0 2006.201.07:18:52.61#ibcon#about to read 4, iclass 19, count 0 2006.201.07:18:52.61#ibcon#read 4, iclass 19, count 0 2006.201.07:18:52.61#ibcon#about to read 5, iclass 19, count 0 2006.201.07:18:52.61#ibcon#read 5, iclass 19, count 0 2006.201.07:18:52.61#ibcon#about to read 6, iclass 19, count 0 2006.201.07:18:52.61#ibcon#read 6, iclass 19, count 0 2006.201.07:18:52.61#ibcon#end of sib2, iclass 19, count 0 2006.201.07:18:52.61#ibcon#*after write, iclass 19, count 0 2006.201.07:18:52.61#ibcon#*before return 0, iclass 19, count 0 2006.201.07:18:52.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:18:52.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:18:52.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.07:18:52.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.07:18:52.61$vck44/vblo=1,629.99 2006.201.07:18:52.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.07:18:52.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.07:18:52.61#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:52.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:18:52.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:18:52.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:18:52.61#ibcon#enter wrdev, iclass 21, count 0 2006.201.07:18:52.61#ibcon#first serial, iclass 21, count 0 2006.201.07:18:52.61#ibcon#enter sib2, iclass 21, count 0 2006.201.07:18:52.61#ibcon#flushed, iclass 21, count 0 2006.201.07:18:52.61#ibcon#about to write, iclass 21, count 0 2006.201.07:18:52.61#ibcon#wrote, iclass 21, count 0 2006.201.07:18:52.61#ibcon#about to read 3, iclass 21, count 0 2006.201.07:18:52.63#ibcon#read 3, iclass 21, count 0 2006.201.07:18:52.63#ibcon#about to read 4, iclass 21, count 0 2006.201.07:18:52.63#ibcon#read 4, iclass 21, count 0 2006.201.07:18:52.63#ibcon#about to read 5, iclass 21, count 0 2006.201.07:18:52.63#ibcon#read 5, iclass 21, count 0 2006.201.07:18:52.63#ibcon#about to read 6, iclass 21, count 0 2006.201.07:18:52.63#ibcon#read 6, iclass 21, count 0 2006.201.07:18:52.63#ibcon#end of sib2, iclass 21, count 0 2006.201.07:18:52.63#ibcon#*mode == 0, iclass 21, count 0 2006.201.07:18:52.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.07:18:52.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:18:52.63#ibcon#*before write, iclass 21, count 0 2006.201.07:18:52.63#ibcon#enter sib2, iclass 21, count 0 2006.201.07:18:52.63#ibcon#flushed, iclass 21, count 0 2006.201.07:18:52.63#ibcon#about to write, iclass 21, count 0 2006.201.07:18:52.63#ibcon#wrote, iclass 21, count 0 2006.201.07:18:52.63#ibcon#about to read 3, iclass 21, count 0 2006.201.07:18:52.68#ibcon#read 3, iclass 21, count 0 2006.201.07:18:52.68#ibcon#about to read 4, iclass 21, count 0 2006.201.07:18:52.68#ibcon#read 4, iclass 21, count 0 2006.201.07:18:52.68#ibcon#about to read 5, iclass 21, count 0 2006.201.07:18:52.68#ibcon#read 5, iclass 21, count 0 2006.201.07:18:52.68#ibcon#about to read 6, iclass 21, count 0 2006.201.07:18:52.68#ibcon#read 6, iclass 21, count 0 2006.201.07:18:52.68#ibcon#end of sib2, iclass 21, count 0 2006.201.07:18:52.68#ibcon#*after write, iclass 21, count 0 2006.201.07:18:52.68#ibcon#*before return 0, iclass 21, count 0 2006.201.07:18:52.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:18:52.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:18:52.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.07:18:52.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.07:18:52.68$vck44/vb=1,4 2006.201.07:18:52.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.07:18:52.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.07:18:52.68#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:52.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:18:52.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:18:52.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:18:52.68#ibcon#enter wrdev, iclass 23, count 2 2006.201.07:18:52.68#ibcon#first serial, iclass 23, count 2 2006.201.07:18:52.68#ibcon#enter sib2, iclass 23, count 2 2006.201.07:18:52.68#ibcon#flushed, iclass 23, count 2 2006.201.07:18:52.68#ibcon#about to write, iclass 23, count 2 2006.201.07:18:52.68#ibcon#wrote, iclass 23, count 2 2006.201.07:18:52.68#ibcon#about to read 3, iclass 23, count 2 2006.201.07:18:52.70#ibcon#read 3, iclass 23, count 2 2006.201.07:18:52.70#ibcon#about to read 4, iclass 23, count 2 2006.201.07:18:52.70#ibcon#read 4, iclass 23, count 2 2006.201.07:18:52.70#ibcon#about to read 5, iclass 23, count 2 2006.201.07:18:52.70#ibcon#read 5, iclass 23, count 2 2006.201.07:18:52.70#ibcon#about to read 6, iclass 23, count 2 2006.201.07:18:52.70#ibcon#read 6, iclass 23, count 2 2006.201.07:18:52.70#ibcon#end of sib2, iclass 23, count 2 2006.201.07:18:52.70#ibcon#*mode == 0, iclass 23, count 2 2006.201.07:18:52.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.07:18:52.70#ibcon#[27=AT01-04\r\n] 2006.201.07:18:52.70#ibcon#*before write, iclass 23, count 2 2006.201.07:18:52.70#ibcon#enter sib2, iclass 23, count 2 2006.201.07:18:52.70#ibcon#flushed, iclass 23, count 2 2006.201.07:18:52.70#ibcon#about to write, iclass 23, count 2 2006.201.07:18:52.70#ibcon#wrote, iclass 23, count 2 2006.201.07:18:52.70#ibcon#about to read 3, iclass 23, count 2 2006.201.07:18:52.73#ibcon#read 3, iclass 23, count 2 2006.201.07:18:52.73#ibcon#about to read 4, iclass 23, count 2 2006.201.07:18:52.73#ibcon#read 4, iclass 23, count 2 2006.201.07:18:52.73#ibcon#about to read 5, iclass 23, count 2 2006.201.07:18:52.73#ibcon#read 5, iclass 23, count 2 2006.201.07:18:52.73#ibcon#about to read 6, iclass 23, count 2 2006.201.07:18:52.73#ibcon#read 6, iclass 23, count 2 2006.201.07:18:52.73#ibcon#end of sib2, iclass 23, count 2 2006.201.07:18:52.73#ibcon#*after write, iclass 23, count 2 2006.201.07:18:52.73#ibcon#*before return 0, iclass 23, count 2 2006.201.07:18:52.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:18:52.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:18:52.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.07:18:52.73#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:52.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:18:52.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:18:52.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:18:52.85#ibcon#enter wrdev, iclass 23, count 0 2006.201.07:18:52.85#ibcon#first serial, iclass 23, count 0 2006.201.07:18:52.85#ibcon#enter sib2, iclass 23, count 0 2006.201.07:18:52.85#ibcon#flushed, iclass 23, count 0 2006.201.07:18:52.85#ibcon#about to write, iclass 23, count 0 2006.201.07:18:52.85#ibcon#wrote, iclass 23, count 0 2006.201.07:18:52.85#ibcon#about to read 3, iclass 23, count 0 2006.201.07:18:52.87#ibcon#read 3, iclass 23, count 0 2006.201.07:18:52.87#ibcon#about to read 4, iclass 23, count 0 2006.201.07:18:52.87#ibcon#read 4, iclass 23, count 0 2006.201.07:18:52.87#ibcon#about to read 5, iclass 23, count 0 2006.201.07:18:52.87#ibcon#read 5, iclass 23, count 0 2006.201.07:18:52.87#ibcon#about to read 6, iclass 23, count 0 2006.201.07:18:52.87#ibcon#read 6, iclass 23, count 0 2006.201.07:18:52.87#ibcon#end of sib2, iclass 23, count 0 2006.201.07:18:52.87#ibcon#*mode == 0, iclass 23, count 0 2006.201.07:18:52.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.07:18:52.87#ibcon#[27=USB\r\n] 2006.201.07:18:52.87#ibcon#*before write, iclass 23, count 0 2006.201.07:18:52.87#ibcon#enter sib2, iclass 23, count 0 2006.201.07:18:52.87#ibcon#flushed, iclass 23, count 0 2006.201.07:18:52.87#ibcon#about to write, iclass 23, count 0 2006.201.07:18:52.87#ibcon#wrote, iclass 23, count 0 2006.201.07:18:52.87#ibcon#about to read 3, iclass 23, count 0 2006.201.07:18:52.90#ibcon#read 3, iclass 23, count 0 2006.201.07:18:52.90#ibcon#about to read 4, iclass 23, count 0 2006.201.07:18:52.90#ibcon#read 4, iclass 23, count 0 2006.201.07:18:52.90#ibcon#about to read 5, iclass 23, count 0 2006.201.07:18:52.90#ibcon#read 5, iclass 23, count 0 2006.201.07:18:52.90#ibcon#about to read 6, iclass 23, count 0 2006.201.07:18:52.90#ibcon#read 6, iclass 23, count 0 2006.201.07:18:52.90#ibcon#end of sib2, iclass 23, count 0 2006.201.07:18:52.90#ibcon#*after write, iclass 23, count 0 2006.201.07:18:52.90#ibcon#*before return 0, iclass 23, count 0 2006.201.07:18:52.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:18:52.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:18:52.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.07:18:52.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.07:18:52.90$vck44/vblo=2,634.99 2006.201.07:18:52.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.07:18:52.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.07:18:52.90#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:52.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:52.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:52.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:52.90#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:18:52.90#ibcon#first serial, iclass 25, count 0 2006.201.07:18:52.90#ibcon#enter sib2, iclass 25, count 0 2006.201.07:18:52.90#ibcon#flushed, iclass 25, count 0 2006.201.07:18:52.90#ibcon#about to write, iclass 25, count 0 2006.201.07:18:52.90#ibcon#wrote, iclass 25, count 0 2006.201.07:18:52.90#ibcon#about to read 3, iclass 25, count 0 2006.201.07:18:52.92#ibcon#read 3, iclass 25, count 0 2006.201.07:18:52.92#ibcon#about to read 4, iclass 25, count 0 2006.201.07:18:52.92#ibcon#read 4, iclass 25, count 0 2006.201.07:18:52.92#ibcon#about to read 5, iclass 25, count 0 2006.201.07:18:52.92#ibcon#read 5, iclass 25, count 0 2006.201.07:18:52.92#ibcon#about to read 6, iclass 25, count 0 2006.201.07:18:52.92#ibcon#read 6, iclass 25, count 0 2006.201.07:18:52.92#ibcon#end of sib2, iclass 25, count 0 2006.201.07:18:52.92#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:18:52.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:18:52.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:18:52.92#ibcon#*before write, iclass 25, count 0 2006.201.07:18:52.92#ibcon#enter sib2, iclass 25, count 0 2006.201.07:18:52.92#ibcon#flushed, iclass 25, count 0 2006.201.07:18:52.92#ibcon#about to write, iclass 25, count 0 2006.201.07:18:52.92#ibcon#wrote, iclass 25, count 0 2006.201.07:18:52.92#ibcon#about to read 3, iclass 25, count 0 2006.201.07:18:52.96#ibcon#read 3, iclass 25, count 0 2006.201.07:18:52.96#ibcon#about to read 4, iclass 25, count 0 2006.201.07:18:52.96#ibcon#read 4, iclass 25, count 0 2006.201.07:18:52.96#ibcon#about to read 5, iclass 25, count 0 2006.201.07:18:52.96#ibcon#read 5, iclass 25, count 0 2006.201.07:18:52.96#ibcon#about to read 6, iclass 25, count 0 2006.201.07:18:52.96#ibcon#read 6, iclass 25, count 0 2006.201.07:18:52.96#ibcon#end of sib2, iclass 25, count 0 2006.201.07:18:52.96#ibcon#*after write, iclass 25, count 0 2006.201.07:18:52.96#ibcon#*before return 0, iclass 25, count 0 2006.201.07:18:52.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:52.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:18:52.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:18:52.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:18:52.96$vck44/vb=2,5 2006.201.07:18:52.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.07:18:52.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.07:18:52.96#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:52.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:53.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:53.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:53.02#ibcon#enter wrdev, iclass 27, count 2 2006.201.07:18:53.02#ibcon#first serial, iclass 27, count 2 2006.201.07:18:53.02#ibcon#enter sib2, iclass 27, count 2 2006.201.07:18:53.02#ibcon#flushed, iclass 27, count 2 2006.201.07:18:53.02#ibcon#about to write, iclass 27, count 2 2006.201.07:18:53.02#ibcon#wrote, iclass 27, count 2 2006.201.07:18:53.02#ibcon#about to read 3, iclass 27, count 2 2006.201.07:18:53.04#ibcon#read 3, iclass 27, count 2 2006.201.07:18:53.04#ibcon#about to read 4, iclass 27, count 2 2006.201.07:18:53.04#ibcon#read 4, iclass 27, count 2 2006.201.07:18:53.04#ibcon#about to read 5, iclass 27, count 2 2006.201.07:18:53.04#ibcon#read 5, iclass 27, count 2 2006.201.07:18:53.04#ibcon#about to read 6, iclass 27, count 2 2006.201.07:18:53.04#ibcon#read 6, iclass 27, count 2 2006.201.07:18:53.04#ibcon#end of sib2, iclass 27, count 2 2006.201.07:18:53.04#ibcon#*mode == 0, iclass 27, count 2 2006.201.07:18:53.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.07:18:53.04#ibcon#[27=AT02-05\r\n] 2006.201.07:18:53.04#ibcon#*before write, iclass 27, count 2 2006.201.07:18:53.04#ibcon#enter sib2, iclass 27, count 2 2006.201.07:18:53.04#ibcon#flushed, iclass 27, count 2 2006.201.07:18:53.04#ibcon#about to write, iclass 27, count 2 2006.201.07:18:53.04#ibcon#wrote, iclass 27, count 2 2006.201.07:18:53.04#ibcon#about to read 3, iclass 27, count 2 2006.201.07:18:53.07#ibcon#read 3, iclass 27, count 2 2006.201.07:18:53.07#ibcon#about to read 4, iclass 27, count 2 2006.201.07:18:53.07#ibcon#read 4, iclass 27, count 2 2006.201.07:18:53.07#ibcon#about to read 5, iclass 27, count 2 2006.201.07:18:53.07#ibcon#read 5, iclass 27, count 2 2006.201.07:18:53.07#ibcon#about to read 6, iclass 27, count 2 2006.201.07:18:53.07#ibcon#read 6, iclass 27, count 2 2006.201.07:18:53.07#ibcon#end of sib2, iclass 27, count 2 2006.201.07:18:53.07#ibcon#*after write, iclass 27, count 2 2006.201.07:18:53.07#ibcon#*before return 0, iclass 27, count 2 2006.201.07:18:53.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:53.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:18:53.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.07:18:53.07#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:53.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:53.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:53.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:53.19#ibcon#enter wrdev, iclass 27, count 0 2006.201.07:18:53.19#ibcon#first serial, iclass 27, count 0 2006.201.07:18:53.19#ibcon#enter sib2, iclass 27, count 0 2006.201.07:18:53.19#ibcon#flushed, iclass 27, count 0 2006.201.07:18:53.19#ibcon#about to write, iclass 27, count 0 2006.201.07:18:53.19#ibcon#wrote, iclass 27, count 0 2006.201.07:18:53.19#ibcon#about to read 3, iclass 27, count 0 2006.201.07:18:53.21#ibcon#read 3, iclass 27, count 0 2006.201.07:18:53.21#ibcon#about to read 4, iclass 27, count 0 2006.201.07:18:53.21#ibcon#read 4, iclass 27, count 0 2006.201.07:18:53.21#ibcon#about to read 5, iclass 27, count 0 2006.201.07:18:53.21#ibcon#read 5, iclass 27, count 0 2006.201.07:18:53.21#ibcon#about to read 6, iclass 27, count 0 2006.201.07:18:53.21#ibcon#read 6, iclass 27, count 0 2006.201.07:18:53.21#ibcon#end of sib2, iclass 27, count 0 2006.201.07:18:53.21#ibcon#*mode == 0, iclass 27, count 0 2006.201.07:18:53.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.07:18:53.21#ibcon#[27=USB\r\n] 2006.201.07:18:53.21#ibcon#*before write, iclass 27, count 0 2006.201.07:18:53.21#ibcon#enter sib2, iclass 27, count 0 2006.201.07:18:53.21#ibcon#flushed, iclass 27, count 0 2006.201.07:18:53.21#ibcon#about to write, iclass 27, count 0 2006.201.07:18:53.21#ibcon#wrote, iclass 27, count 0 2006.201.07:18:53.21#ibcon#about to read 3, iclass 27, count 0 2006.201.07:18:53.24#ibcon#read 3, iclass 27, count 0 2006.201.07:18:53.24#ibcon#about to read 4, iclass 27, count 0 2006.201.07:18:53.24#ibcon#read 4, iclass 27, count 0 2006.201.07:18:53.24#ibcon#about to read 5, iclass 27, count 0 2006.201.07:18:53.24#ibcon#read 5, iclass 27, count 0 2006.201.07:18:53.24#ibcon#about to read 6, iclass 27, count 0 2006.201.07:18:53.24#ibcon#read 6, iclass 27, count 0 2006.201.07:18:53.24#ibcon#end of sib2, iclass 27, count 0 2006.201.07:18:53.24#ibcon#*after write, iclass 27, count 0 2006.201.07:18:53.24#ibcon#*before return 0, iclass 27, count 0 2006.201.07:18:53.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:53.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:18:53.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.07:18:53.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.07:18:53.24$vck44/vblo=3,649.99 2006.201.07:18:53.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.07:18:53.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.07:18:53.24#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:53.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:53.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:53.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:53.24#ibcon#enter wrdev, iclass 29, count 0 2006.201.07:18:53.24#ibcon#first serial, iclass 29, count 0 2006.201.07:18:53.24#ibcon#enter sib2, iclass 29, count 0 2006.201.07:18:53.24#ibcon#flushed, iclass 29, count 0 2006.201.07:18:53.24#ibcon#about to write, iclass 29, count 0 2006.201.07:18:53.24#ibcon#wrote, iclass 29, count 0 2006.201.07:18:53.24#ibcon#about to read 3, iclass 29, count 0 2006.201.07:18:53.26#ibcon#read 3, iclass 29, count 0 2006.201.07:18:53.26#ibcon#about to read 4, iclass 29, count 0 2006.201.07:18:53.26#ibcon#read 4, iclass 29, count 0 2006.201.07:18:53.26#ibcon#about to read 5, iclass 29, count 0 2006.201.07:18:53.26#ibcon#read 5, iclass 29, count 0 2006.201.07:18:53.26#ibcon#about to read 6, iclass 29, count 0 2006.201.07:18:53.26#ibcon#read 6, iclass 29, count 0 2006.201.07:18:53.26#ibcon#end of sib2, iclass 29, count 0 2006.201.07:18:53.26#ibcon#*mode == 0, iclass 29, count 0 2006.201.07:18:53.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.07:18:53.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:18:53.26#ibcon#*before write, iclass 29, count 0 2006.201.07:18:53.26#ibcon#enter sib2, iclass 29, count 0 2006.201.07:18:53.26#ibcon#flushed, iclass 29, count 0 2006.201.07:18:53.26#ibcon#about to write, iclass 29, count 0 2006.201.07:18:53.26#ibcon#wrote, iclass 29, count 0 2006.201.07:18:53.26#ibcon#about to read 3, iclass 29, count 0 2006.201.07:18:53.30#ibcon#read 3, iclass 29, count 0 2006.201.07:18:53.30#ibcon#about to read 4, iclass 29, count 0 2006.201.07:18:53.30#ibcon#read 4, iclass 29, count 0 2006.201.07:18:53.30#ibcon#about to read 5, iclass 29, count 0 2006.201.07:18:53.30#ibcon#read 5, iclass 29, count 0 2006.201.07:18:53.30#ibcon#about to read 6, iclass 29, count 0 2006.201.07:18:53.30#ibcon#read 6, iclass 29, count 0 2006.201.07:18:53.30#ibcon#end of sib2, iclass 29, count 0 2006.201.07:18:53.30#ibcon#*after write, iclass 29, count 0 2006.201.07:18:53.30#ibcon#*before return 0, iclass 29, count 0 2006.201.07:18:53.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:53.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:18:53.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.07:18:53.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.07:18:53.30$vck44/vb=3,4 2006.201.07:18:53.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.07:18:53.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.07:18:53.30#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:53.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:53.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:53.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:53.36#ibcon#enter wrdev, iclass 31, count 2 2006.201.07:18:53.36#ibcon#first serial, iclass 31, count 2 2006.201.07:18:53.36#ibcon#enter sib2, iclass 31, count 2 2006.201.07:18:53.36#ibcon#flushed, iclass 31, count 2 2006.201.07:18:53.36#ibcon#about to write, iclass 31, count 2 2006.201.07:18:53.36#ibcon#wrote, iclass 31, count 2 2006.201.07:18:53.36#ibcon#about to read 3, iclass 31, count 2 2006.201.07:18:53.38#ibcon#read 3, iclass 31, count 2 2006.201.07:18:53.38#ibcon#about to read 4, iclass 31, count 2 2006.201.07:18:53.38#ibcon#read 4, iclass 31, count 2 2006.201.07:18:53.38#ibcon#about to read 5, iclass 31, count 2 2006.201.07:18:53.38#ibcon#read 5, iclass 31, count 2 2006.201.07:18:53.38#ibcon#about to read 6, iclass 31, count 2 2006.201.07:18:53.38#ibcon#read 6, iclass 31, count 2 2006.201.07:18:53.38#ibcon#end of sib2, iclass 31, count 2 2006.201.07:18:53.38#ibcon#*mode == 0, iclass 31, count 2 2006.201.07:18:53.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.07:18:53.38#ibcon#[27=AT03-04\r\n] 2006.201.07:18:53.38#ibcon#*before write, iclass 31, count 2 2006.201.07:18:53.38#ibcon#enter sib2, iclass 31, count 2 2006.201.07:18:53.38#ibcon#flushed, iclass 31, count 2 2006.201.07:18:53.38#ibcon#about to write, iclass 31, count 2 2006.201.07:18:53.38#ibcon#wrote, iclass 31, count 2 2006.201.07:18:53.38#ibcon#about to read 3, iclass 31, count 2 2006.201.07:18:53.42#ibcon#read 3, iclass 31, count 2 2006.201.07:18:53.42#ibcon#about to read 4, iclass 31, count 2 2006.201.07:18:53.42#ibcon#read 4, iclass 31, count 2 2006.201.07:18:53.42#ibcon#about to read 5, iclass 31, count 2 2006.201.07:18:53.42#ibcon#read 5, iclass 31, count 2 2006.201.07:18:53.42#ibcon#about to read 6, iclass 31, count 2 2006.201.07:18:53.42#ibcon#read 6, iclass 31, count 2 2006.201.07:18:53.42#ibcon#end of sib2, iclass 31, count 2 2006.201.07:18:53.42#ibcon#*after write, iclass 31, count 2 2006.201.07:18:53.42#ibcon#*before return 0, iclass 31, count 2 2006.201.07:18:53.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:53.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:18:53.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.07:18:53.42#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:53.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:53.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:53.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:53.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.07:18:53.54#ibcon#first serial, iclass 31, count 0 2006.201.07:18:53.54#ibcon#enter sib2, iclass 31, count 0 2006.201.07:18:53.54#ibcon#flushed, iclass 31, count 0 2006.201.07:18:53.54#ibcon#about to write, iclass 31, count 0 2006.201.07:18:53.54#ibcon#wrote, iclass 31, count 0 2006.201.07:18:53.54#ibcon#about to read 3, iclass 31, count 0 2006.201.07:18:53.56#ibcon#read 3, iclass 31, count 0 2006.201.07:18:53.56#ibcon#about to read 4, iclass 31, count 0 2006.201.07:18:53.56#ibcon#read 4, iclass 31, count 0 2006.201.07:18:53.56#ibcon#about to read 5, iclass 31, count 0 2006.201.07:18:53.56#ibcon#read 5, iclass 31, count 0 2006.201.07:18:53.56#ibcon#about to read 6, iclass 31, count 0 2006.201.07:18:53.56#ibcon#read 6, iclass 31, count 0 2006.201.07:18:53.56#ibcon#end of sib2, iclass 31, count 0 2006.201.07:18:53.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.07:18:53.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.07:18:53.56#ibcon#[27=USB\r\n] 2006.201.07:18:53.56#ibcon#*before write, iclass 31, count 0 2006.201.07:18:53.56#ibcon#enter sib2, iclass 31, count 0 2006.201.07:18:53.56#ibcon#flushed, iclass 31, count 0 2006.201.07:18:53.56#ibcon#about to write, iclass 31, count 0 2006.201.07:18:53.56#ibcon#wrote, iclass 31, count 0 2006.201.07:18:53.56#ibcon#about to read 3, iclass 31, count 0 2006.201.07:18:53.59#ibcon#read 3, iclass 31, count 0 2006.201.07:18:53.59#ibcon#about to read 4, iclass 31, count 0 2006.201.07:18:53.59#ibcon#read 4, iclass 31, count 0 2006.201.07:18:53.59#ibcon#about to read 5, iclass 31, count 0 2006.201.07:18:53.59#ibcon#read 5, iclass 31, count 0 2006.201.07:18:53.59#ibcon#about to read 6, iclass 31, count 0 2006.201.07:18:53.59#ibcon#read 6, iclass 31, count 0 2006.201.07:18:53.59#ibcon#end of sib2, iclass 31, count 0 2006.201.07:18:53.59#ibcon#*after write, iclass 31, count 0 2006.201.07:18:53.59#ibcon#*before return 0, iclass 31, count 0 2006.201.07:18:53.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:53.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:18:53.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.07:18:53.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.07:18:53.59$vck44/vblo=4,679.99 2006.201.07:18:53.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.07:18:53.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.07:18:53.59#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:53.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:53.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:53.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:53.59#ibcon#enter wrdev, iclass 33, count 0 2006.201.07:18:53.59#ibcon#first serial, iclass 33, count 0 2006.201.07:18:53.59#ibcon#enter sib2, iclass 33, count 0 2006.201.07:18:53.59#ibcon#flushed, iclass 33, count 0 2006.201.07:18:53.59#ibcon#about to write, iclass 33, count 0 2006.201.07:18:53.59#ibcon#wrote, iclass 33, count 0 2006.201.07:18:53.59#ibcon#about to read 3, iclass 33, count 0 2006.201.07:18:53.61#ibcon#read 3, iclass 33, count 0 2006.201.07:18:53.61#ibcon#about to read 4, iclass 33, count 0 2006.201.07:18:53.61#ibcon#read 4, iclass 33, count 0 2006.201.07:18:53.61#ibcon#about to read 5, iclass 33, count 0 2006.201.07:18:53.61#ibcon#read 5, iclass 33, count 0 2006.201.07:18:53.61#ibcon#about to read 6, iclass 33, count 0 2006.201.07:18:53.61#ibcon#read 6, iclass 33, count 0 2006.201.07:18:53.61#ibcon#end of sib2, iclass 33, count 0 2006.201.07:18:53.61#ibcon#*mode == 0, iclass 33, count 0 2006.201.07:18:53.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.07:18:53.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:18:53.61#ibcon#*before write, iclass 33, count 0 2006.201.07:18:53.61#ibcon#enter sib2, iclass 33, count 0 2006.201.07:18:53.61#ibcon#flushed, iclass 33, count 0 2006.201.07:18:53.61#ibcon#about to write, iclass 33, count 0 2006.201.07:18:53.61#ibcon#wrote, iclass 33, count 0 2006.201.07:18:53.61#ibcon#about to read 3, iclass 33, count 0 2006.201.07:18:53.66#ibcon#read 3, iclass 33, count 0 2006.201.07:18:53.66#ibcon#about to read 4, iclass 33, count 0 2006.201.07:18:53.66#ibcon#read 4, iclass 33, count 0 2006.201.07:18:53.66#ibcon#about to read 5, iclass 33, count 0 2006.201.07:18:53.66#ibcon#read 5, iclass 33, count 0 2006.201.07:18:53.66#ibcon#about to read 6, iclass 33, count 0 2006.201.07:18:53.66#ibcon#read 6, iclass 33, count 0 2006.201.07:18:53.66#ibcon#end of sib2, iclass 33, count 0 2006.201.07:18:53.66#ibcon#*after write, iclass 33, count 0 2006.201.07:18:53.66#ibcon#*before return 0, iclass 33, count 0 2006.201.07:18:53.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:53.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:18:53.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.07:18:53.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.07:18:53.66$vck44/vb=4,5 2006.201.07:18:53.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.07:18:53.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.07:18:53.66#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:53.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:53.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:53.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:53.71#ibcon#enter wrdev, iclass 35, count 2 2006.201.07:18:53.71#ibcon#first serial, iclass 35, count 2 2006.201.07:18:53.71#ibcon#enter sib2, iclass 35, count 2 2006.201.07:18:53.71#ibcon#flushed, iclass 35, count 2 2006.201.07:18:53.71#ibcon#about to write, iclass 35, count 2 2006.201.07:18:53.71#ibcon#wrote, iclass 35, count 2 2006.201.07:18:53.71#ibcon#about to read 3, iclass 35, count 2 2006.201.07:18:53.73#ibcon#read 3, iclass 35, count 2 2006.201.07:18:53.73#ibcon#about to read 4, iclass 35, count 2 2006.201.07:18:53.73#ibcon#read 4, iclass 35, count 2 2006.201.07:18:53.73#ibcon#about to read 5, iclass 35, count 2 2006.201.07:18:53.73#ibcon#read 5, iclass 35, count 2 2006.201.07:18:53.73#ibcon#about to read 6, iclass 35, count 2 2006.201.07:18:53.73#ibcon#read 6, iclass 35, count 2 2006.201.07:18:53.73#ibcon#end of sib2, iclass 35, count 2 2006.201.07:18:53.73#ibcon#*mode == 0, iclass 35, count 2 2006.201.07:18:53.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.07:18:53.73#ibcon#[27=AT04-05\r\n] 2006.201.07:18:53.73#ibcon#*before write, iclass 35, count 2 2006.201.07:18:53.73#ibcon#enter sib2, iclass 35, count 2 2006.201.07:18:53.73#ibcon#flushed, iclass 35, count 2 2006.201.07:18:53.73#ibcon#about to write, iclass 35, count 2 2006.201.07:18:53.73#ibcon#wrote, iclass 35, count 2 2006.201.07:18:53.73#ibcon#about to read 3, iclass 35, count 2 2006.201.07:18:53.76#ibcon#read 3, iclass 35, count 2 2006.201.07:18:53.76#ibcon#about to read 4, iclass 35, count 2 2006.201.07:18:53.76#ibcon#read 4, iclass 35, count 2 2006.201.07:18:53.76#ibcon#about to read 5, iclass 35, count 2 2006.201.07:18:53.76#ibcon#read 5, iclass 35, count 2 2006.201.07:18:53.76#ibcon#about to read 6, iclass 35, count 2 2006.201.07:18:53.76#ibcon#read 6, iclass 35, count 2 2006.201.07:18:53.76#ibcon#end of sib2, iclass 35, count 2 2006.201.07:18:53.76#ibcon#*after write, iclass 35, count 2 2006.201.07:18:53.76#ibcon#*before return 0, iclass 35, count 2 2006.201.07:18:53.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:53.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:18:53.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.07:18:53.76#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:53.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:53.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:53.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:53.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.07:18:53.88#ibcon#first serial, iclass 35, count 0 2006.201.07:18:53.88#ibcon#enter sib2, iclass 35, count 0 2006.201.07:18:53.88#ibcon#flushed, iclass 35, count 0 2006.201.07:18:53.88#ibcon#about to write, iclass 35, count 0 2006.201.07:18:53.88#ibcon#wrote, iclass 35, count 0 2006.201.07:18:53.88#ibcon#about to read 3, iclass 35, count 0 2006.201.07:18:53.90#ibcon#read 3, iclass 35, count 0 2006.201.07:18:53.90#ibcon#about to read 4, iclass 35, count 0 2006.201.07:18:53.90#ibcon#read 4, iclass 35, count 0 2006.201.07:18:53.90#ibcon#about to read 5, iclass 35, count 0 2006.201.07:18:53.90#ibcon#read 5, iclass 35, count 0 2006.201.07:18:53.90#ibcon#about to read 6, iclass 35, count 0 2006.201.07:18:53.90#ibcon#read 6, iclass 35, count 0 2006.201.07:18:53.90#ibcon#end of sib2, iclass 35, count 0 2006.201.07:18:53.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.07:18:53.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.07:18:53.90#ibcon#[27=USB\r\n] 2006.201.07:18:53.90#ibcon#*before write, iclass 35, count 0 2006.201.07:18:53.90#ibcon#enter sib2, iclass 35, count 0 2006.201.07:18:53.90#ibcon#flushed, iclass 35, count 0 2006.201.07:18:53.90#ibcon#about to write, iclass 35, count 0 2006.201.07:18:53.90#ibcon#wrote, iclass 35, count 0 2006.201.07:18:53.90#ibcon#about to read 3, iclass 35, count 0 2006.201.07:18:53.93#ibcon#read 3, iclass 35, count 0 2006.201.07:18:53.93#ibcon#about to read 4, iclass 35, count 0 2006.201.07:18:53.93#ibcon#read 4, iclass 35, count 0 2006.201.07:18:53.93#ibcon#about to read 5, iclass 35, count 0 2006.201.07:18:53.93#ibcon#read 5, iclass 35, count 0 2006.201.07:18:53.93#ibcon#about to read 6, iclass 35, count 0 2006.201.07:18:53.93#ibcon#read 6, iclass 35, count 0 2006.201.07:18:53.93#ibcon#end of sib2, iclass 35, count 0 2006.201.07:18:53.93#ibcon#*after write, iclass 35, count 0 2006.201.07:18:53.93#ibcon#*before return 0, iclass 35, count 0 2006.201.07:18:53.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:53.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:18:53.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.07:18:53.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.07:18:53.93$vck44/vblo=5,709.99 2006.201.07:18:53.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.07:18:53.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.07:18:53.93#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:53.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:53.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:53.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:53.93#ibcon#enter wrdev, iclass 37, count 0 2006.201.07:18:53.93#ibcon#first serial, iclass 37, count 0 2006.201.07:18:53.93#ibcon#enter sib2, iclass 37, count 0 2006.201.07:18:53.93#ibcon#flushed, iclass 37, count 0 2006.201.07:18:53.93#ibcon#about to write, iclass 37, count 0 2006.201.07:18:53.93#ibcon#wrote, iclass 37, count 0 2006.201.07:18:53.93#ibcon#about to read 3, iclass 37, count 0 2006.201.07:18:53.95#ibcon#read 3, iclass 37, count 0 2006.201.07:18:53.95#ibcon#about to read 4, iclass 37, count 0 2006.201.07:18:53.95#ibcon#read 4, iclass 37, count 0 2006.201.07:18:53.95#ibcon#about to read 5, iclass 37, count 0 2006.201.07:18:53.95#ibcon#read 5, iclass 37, count 0 2006.201.07:18:53.95#ibcon#about to read 6, iclass 37, count 0 2006.201.07:18:53.95#ibcon#read 6, iclass 37, count 0 2006.201.07:18:53.95#ibcon#end of sib2, iclass 37, count 0 2006.201.07:18:53.95#ibcon#*mode == 0, iclass 37, count 0 2006.201.07:18:53.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.07:18:53.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:18:53.95#ibcon#*before write, iclass 37, count 0 2006.201.07:18:53.95#ibcon#enter sib2, iclass 37, count 0 2006.201.07:18:53.95#ibcon#flushed, iclass 37, count 0 2006.201.07:18:53.95#ibcon#about to write, iclass 37, count 0 2006.201.07:18:53.95#ibcon#wrote, iclass 37, count 0 2006.201.07:18:53.95#ibcon#about to read 3, iclass 37, count 0 2006.201.07:18:53.99#ibcon#read 3, iclass 37, count 0 2006.201.07:18:53.99#ibcon#about to read 4, iclass 37, count 0 2006.201.07:18:53.99#ibcon#read 4, iclass 37, count 0 2006.201.07:18:53.99#ibcon#about to read 5, iclass 37, count 0 2006.201.07:18:53.99#ibcon#read 5, iclass 37, count 0 2006.201.07:18:53.99#ibcon#about to read 6, iclass 37, count 0 2006.201.07:18:53.99#ibcon#read 6, iclass 37, count 0 2006.201.07:18:53.99#ibcon#end of sib2, iclass 37, count 0 2006.201.07:18:53.99#ibcon#*after write, iclass 37, count 0 2006.201.07:18:53.99#ibcon#*before return 0, iclass 37, count 0 2006.201.07:18:53.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:53.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:18:53.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.07:18:53.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.07:18:53.99$vck44/vb=5,4 2006.201.07:18:53.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.07:18:53.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.07:18:53.99#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:53.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:54.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:54.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:54.05#ibcon#enter wrdev, iclass 39, count 2 2006.201.07:18:54.05#ibcon#first serial, iclass 39, count 2 2006.201.07:18:54.05#ibcon#enter sib2, iclass 39, count 2 2006.201.07:18:54.05#ibcon#flushed, iclass 39, count 2 2006.201.07:18:54.05#ibcon#about to write, iclass 39, count 2 2006.201.07:18:54.05#ibcon#wrote, iclass 39, count 2 2006.201.07:18:54.05#ibcon#about to read 3, iclass 39, count 2 2006.201.07:18:54.07#ibcon#read 3, iclass 39, count 2 2006.201.07:18:54.07#ibcon#about to read 4, iclass 39, count 2 2006.201.07:18:54.07#ibcon#read 4, iclass 39, count 2 2006.201.07:18:54.07#ibcon#about to read 5, iclass 39, count 2 2006.201.07:18:54.07#ibcon#read 5, iclass 39, count 2 2006.201.07:18:54.07#ibcon#about to read 6, iclass 39, count 2 2006.201.07:18:54.07#ibcon#read 6, iclass 39, count 2 2006.201.07:18:54.07#ibcon#end of sib2, iclass 39, count 2 2006.201.07:18:54.07#ibcon#*mode == 0, iclass 39, count 2 2006.201.07:18:54.07#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.07:18:54.07#ibcon#[27=AT05-04\r\n] 2006.201.07:18:54.07#ibcon#*before write, iclass 39, count 2 2006.201.07:18:54.07#ibcon#enter sib2, iclass 39, count 2 2006.201.07:18:54.07#ibcon#flushed, iclass 39, count 2 2006.201.07:18:54.07#ibcon#about to write, iclass 39, count 2 2006.201.07:18:54.07#ibcon#wrote, iclass 39, count 2 2006.201.07:18:54.07#ibcon#about to read 3, iclass 39, count 2 2006.201.07:18:54.10#ibcon#read 3, iclass 39, count 2 2006.201.07:18:54.10#ibcon#about to read 4, iclass 39, count 2 2006.201.07:18:54.10#ibcon#read 4, iclass 39, count 2 2006.201.07:18:54.10#ibcon#about to read 5, iclass 39, count 2 2006.201.07:18:54.10#ibcon#read 5, iclass 39, count 2 2006.201.07:18:54.10#ibcon#about to read 6, iclass 39, count 2 2006.201.07:18:54.10#ibcon#read 6, iclass 39, count 2 2006.201.07:18:54.10#ibcon#end of sib2, iclass 39, count 2 2006.201.07:18:54.10#ibcon#*after write, iclass 39, count 2 2006.201.07:18:54.10#ibcon#*before return 0, iclass 39, count 2 2006.201.07:18:54.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:54.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:18:54.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.07:18:54.10#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:54.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:54.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:54.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:54.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.07:18:54.22#ibcon#first serial, iclass 39, count 0 2006.201.07:18:54.22#ibcon#enter sib2, iclass 39, count 0 2006.201.07:18:54.22#ibcon#flushed, iclass 39, count 0 2006.201.07:18:54.22#ibcon#about to write, iclass 39, count 0 2006.201.07:18:54.22#ibcon#wrote, iclass 39, count 0 2006.201.07:18:54.22#ibcon#about to read 3, iclass 39, count 0 2006.201.07:18:54.24#ibcon#read 3, iclass 39, count 0 2006.201.07:18:54.24#ibcon#about to read 4, iclass 39, count 0 2006.201.07:18:54.24#ibcon#read 4, iclass 39, count 0 2006.201.07:18:54.24#ibcon#about to read 5, iclass 39, count 0 2006.201.07:18:54.24#ibcon#read 5, iclass 39, count 0 2006.201.07:18:54.24#ibcon#about to read 6, iclass 39, count 0 2006.201.07:18:54.24#ibcon#read 6, iclass 39, count 0 2006.201.07:18:54.24#ibcon#end of sib2, iclass 39, count 0 2006.201.07:18:54.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.07:18:54.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.07:18:54.24#ibcon#[27=USB\r\n] 2006.201.07:18:54.24#ibcon#*before write, iclass 39, count 0 2006.201.07:18:54.24#ibcon#enter sib2, iclass 39, count 0 2006.201.07:18:54.24#ibcon#flushed, iclass 39, count 0 2006.201.07:18:54.24#ibcon#about to write, iclass 39, count 0 2006.201.07:18:54.24#ibcon#wrote, iclass 39, count 0 2006.201.07:18:54.24#ibcon#about to read 3, iclass 39, count 0 2006.201.07:18:54.27#ibcon#read 3, iclass 39, count 0 2006.201.07:18:54.27#ibcon#about to read 4, iclass 39, count 0 2006.201.07:18:54.27#ibcon#read 4, iclass 39, count 0 2006.201.07:18:54.27#ibcon#about to read 5, iclass 39, count 0 2006.201.07:18:54.27#ibcon#read 5, iclass 39, count 0 2006.201.07:18:54.27#ibcon#about to read 6, iclass 39, count 0 2006.201.07:18:54.27#ibcon#read 6, iclass 39, count 0 2006.201.07:18:54.27#ibcon#end of sib2, iclass 39, count 0 2006.201.07:18:54.27#ibcon#*after write, iclass 39, count 0 2006.201.07:18:54.27#ibcon#*before return 0, iclass 39, count 0 2006.201.07:18:54.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:54.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:18:54.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.07:18:54.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.07:18:54.27$vck44/vblo=6,719.99 2006.201.07:18:54.27#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.07:18:54.27#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.07:18:54.27#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:54.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:54.27#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:54.27#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:54.27#ibcon#enter wrdev, iclass 2, count 0 2006.201.07:18:54.27#ibcon#first serial, iclass 2, count 0 2006.201.07:18:54.27#ibcon#enter sib2, iclass 2, count 0 2006.201.07:18:54.27#ibcon#flushed, iclass 2, count 0 2006.201.07:18:54.27#ibcon#about to write, iclass 2, count 0 2006.201.07:18:54.27#ibcon#wrote, iclass 2, count 0 2006.201.07:18:54.27#ibcon#about to read 3, iclass 2, count 0 2006.201.07:18:54.29#ibcon#read 3, iclass 2, count 0 2006.201.07:18:54.29#ibcon#about to read 4, iclass 2, count 0 2006.201.07:18:54.29#ibcon#read 4, iclass 2, count 0 2006.201.07:18:54.29#ibcon#about to read 5, iclass 2, count 0 2006.201.07:18:54.29#ibcon#read 5, iclass 2, count 0 2006.201.07:18:54.29#ibcon#about to read 6, iclass 2, count 0 2006.201.07:18:54.29#ibcon#read 6, iclass 2, count 0 2006.201.07:18:54.29#ibcon#end of sib2, iclass 2, count 0 2006.201.07:18:54.29#ibcon#*mode == 0, iclass 2, count 0 2006.201.07:18:54.29#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.07:18:54.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:18:54.29#ibcon#*before write, iclass 2, count 0 2006.201.07:18:54.29#ibcon#enter sib2, iclass 2, count 0 2006.201.07:18:54.29#ibcon#flushed, iclass 2, count 0 2006.201.07:18:54.29#ibcon#about to write, iclass 2, count 0 2006.201.07:18:54.29#ibcon#wrote, iclass 2, count 0 2006.201.07:18:54.29#ibcon#about to read 3, iclass 2, count 0 2006.201.07:18:54.33#ibcon#read 3, iclass 2, count 0 2006.201.07:18:54.33#ibcon#about to read 4, iclass 2, count 0 2006.201.07:18:54.33#ibcon#read 4, iclass 2, count 0 2006.201.07:18:54.33#ibcon#about to read 5, iclass 2, count 0 2006.201.07:18:54.33#ibcon#read 5, iclass 2, count 0 2006.201.07:18:54.33#ibcon#about to read 6, iclass 2, count 0 2006.201.07:18:54.33#ibcon#read 6, iclass 2, count 0 2006.201.07:18:54.33#ibcon#end of sib2, iclass 2, count 0 2006.201.07:18:54.33#ibcon#*after write, iclass 2, count 0 2006.201.07:18:54.33#ibcon#*before return 0, iclass 2, count 0 2006.201.07:18:54.33#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:54.33#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:18:54.33#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.07:18:54.33#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.07:18:54.33$vck44/vb=6,4 2006.201.07:18:54.33#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.07:18:54.33#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.07:18:54.33#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:54.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:54.39#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:54.39#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:54.39#ibcon#enter wrdev, iclass 5, count 2 2006.201.07:18:54.39#ibcon#first serial, iclass 5, count 2 2006.201.07:18:54.39#ibcon#enter sib2, iclass 5, count 2 2006.201.07:18:54.39#ibcon#flushed, iclass 5, count 2 2006.201.07:18:54.39#ibcon#about to write, iclass 5, count 2 2006.201.07:18:54.39#ibcon#wrote, iclass 5, count 2 2006.201.07:18:54.39#ibcon#about to read 3, iclass 5, count 2 2006.201.07:18:54.41#ibcon#read 3, iclass 5, count 2 2006.201.07:18:54.41#ibcon#about to read 4, iclass 5, count 2 2006.201.07:18:54.41#ibcon#read 4, iclass 5, count 2 2006.201.07:18:54.41#ibcon#about to read 5, iclass 5, count 2 2006.201.07:18:54.41#ibcon#read 5, iclass 5, count 2 2006.201.07:18:54.41#ibcon#about to read 6, iclass 5, count 2 2006.201.07:18:54.41#ibcon#read 6, iclass 5, count 2 2006.201.07:18:54.41#ibcon#end of sib2, iclass 5, count 2 2006.201.07:18:54.41#ibcon#*mode == 0, iclass 5, count 2 2006.201.07:18:54.41#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.07:18:54.41#ibcon#[27=AT06-04\r\n] 2006.201.07:18:54.41#ibcon#*before write, iclass 5, count 2 2006.201.07:18:54.41#ibcon#enter sib2, iclass 5, count 2 2006.201.07:18:54.41#ibcon#flushed, iclass 5, count 2 2006.201.07:18:54.41#ibcon#about to write, iclass 5, count 2 2006.201.07:18:54.41#ibcon#wrote, iclass 5, count 2 2006.201.07:18:54.41#ibcon#about to read 3, iclass 5, count 2 2006.201.07:18:54.44#ibcon#read 3, iclass 5, count 2 2006.201.07:18:54.44#ibcon#about to read 4, iclass 5, count 2 2006.201.07:18:54.44#ibcon#read 4, iclass 5, count 2 2006.201.07:18:54.44#ibcon#about to read 5, iclass 5, count 2 2006.201.07:18:54.44#ibcon#read 5, iclass 5, count 2 2006.201.07:18:54.44#ibcon#about to read 6, iclass 5, count 2 2006.201.07:18:54.44#ibcon#read 6, iclass 5, count 2 2006.201.07:18:54.44#ibcon#end of sib2, iclass 5, count 2 2006.201.07:18:54.44#ibcon#*after write, iclass 5, count 2 2006.201.07:18:54.44#ibcon#*before return 0, iclass 5, count 2 2006.201.07:18:54.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:54.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:18:54.44#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.07:18:54.44#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:54.44#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:54.56#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:54.56#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:54.56#ibcon#enter wrdev, iclass 5, count 0 2006.201.07:18:54.56#ibcon#first serial, iclass 5, count 0 2006.201.07:18:54.56#ibcon#enter sib2, iclass 5, count 0 2006.201.07:18:54.56#ibcon#flushed, iclass 5, count 0 2006.201.07:18:54.56#ibcon#about to write, iclass 5, count 0 2006.201.07:18:54.56#ibcon#wrote, iclass 5, count 0 2006.201.07:18:54.56#ibcon#about to read 3, iclass 5, count 0 2006.201.07:18:54.58#ibcon#read 3, iclass 5, count 0 2006.201.07:18:54.58#ibcon#about to read 4, iclass 5, count 0 2006.201.07:18:54.58#ibcon#read 4, iclass 5, count 0 2006.201.07:18:54.58#ibcon#about to read 5, iclass 5, count 0 2006.201.07:18:54.58#ibcon#read 5, iclass 5, count 0 2006.201.07:18:54.58#ibcon#about to read 6, iclass 5, count 0 2006.201.07:18:54.58#ibcon#read 6, iclass 5, count 0 2006.201.07:18:54.58#ibcon#end of sib2, iclass 5, count 0 2006.201.07:18:54.58#ibcon#*mode == 0, iclass 5, count 0 2006.201.07:18:54.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.07:18:54.58#ibcon#[27=USB\r\n] 2006.201.07:18:54.58#ibcon#*before write, iclass 5, count 0 2006.201.07:18:54.58#ibcon#enter sib2, iclass 5, count 0 2006.201.07:18:54.58#ibcon#flushed, iclass 5, count 0 2006.201.07:18:54.58#ibcon#about to write, iclass 5, count 0 2006.201.07:18:54.58#ibcon#wrote, iclass 5, count 0 2006.201.07:18:54.58#ibcon#about to read 3, iclass 5, count 0 2006.201.07:18:54.61#ibcon#read 3, iclass 5, count 0 2006.201.07:18:54.61#ibcon#about to read 4, iclass 5, count 0 2006.201.07:18:54.61#ibcon#read 4, iclass 5, count 0 2006.201.07:18:54.61#ibcon#about to read 5, iclass 5, count 0 2006.201.07:18:54.61#ibcon#read 5, iclass 5, count 0 2006.201.07:18:54.61#ibcon#about to read 6, iclass 5, count 0 2006.201.07:18:54.61#ibcon#read 6, iclass 5, count 0 2006.201.07:18:54.61#ibcon#end of sib2, iclass 5, count 0 2006.201.07:18:54.61#ibcon#*after write, iclass 5, count 0 2006.201.07:18:54.61#ibcon#*before return 0, iclass 5, count 0 2006.201.07:18:54.61#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:54.61#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:18:54.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.07:18:54.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.07:18:54.61$vck44/vblo=7,734.99 2006.201.07:18:54.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.07:18:54.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.07:18:54.61#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:54.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:54.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:54.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:54.61#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:18:54.61#ibcon#first serial, iclass 7, count 0 2006.201.07:18:54.61#ibcon#enter sib2, iclass 7, count 0 2006.201.07:18:54.61#ibcon#flushed, iclass 7, count 0 2006.201.07:18:54.61#ibcon#about to write, iclass 7, count 0 2006.201.07:18:54.61#ibcon#wrote, iclass 7, count 0 2006.201.07:18:54.61#ibcon#about to read 3, iclass 7, count 0 2006.201.07:18:54.63#ibcon#read 3, iclass 7, count 0 2006.201.07:18:54.63#ibcon#about to read 4, iclass 7, count 0 2006.201.07:18:54.63#ibcon#read 4, iclass 7, count 0 2006.201.07:18:54.63#ibcon#about to read 5, iclass 7, count 0 2006.201.07:18:54.63#ibcon#read 5, iclass 7, count 0 2006.201.07:18:54.63#ibcon#about to read 6, iclass 7, count 0 2006.201.07:18:54.63#ibcon#read 6, iclass 7, count 0 2006.201.07:18:54.63#ibcon#end of sib2, iclass 7, count 0 2006.201.07:18:54.63#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:18:54.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:18:54.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:18:54.63#ibcon#*before write, iclass 7, count 0 2006.201.07:18:54.63#ibcon#enter sib2, iclass 7, count 0 2006.201.07:18:54.63#ibcon#flushed, iclass 7, count 0 2006.201.07:18:54.63#ibcon#about to write, iclass 7, count 0 2006.201.07:18:54.63#ibcon#wrote, iclass 7, count 0 2006.201.07:18:54.63#ibcon#about to read 3, iclass 7, count 0 2006.201.07:18:54.67#ibcon#read 3, iclass 7, count 0 2006.201.07:18:54.67#ibcon#about to read 4, iclass 7, count 0 2006.201.07:18:54.67#ibcon#read 4, iclass 7, count 0 2006.201.07:18:54.67#ibcon#about to read 5, iclass 7, count 0 2006.201.07:18:54.67#ibcon#read 5, iclass 7, count 0 2006.201.07:18:54.67#ibcon#about to read 6, iclass 7, count 0 2006.201.07:18:54.67#ibcon#read 6, iclass 7, count 0 2006.201.07:18:54.67#ibcon#end of sib2, iclass 7, count 0 2006.201.07:18:54.67#ibcon#*after write, iclass 7, count 0 2006.201.07:18:54.67#ibcon#*before return 0, iclass 7, count 0 2006.201.07:18:54.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:54.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:18:54.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:18:54.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:18:54.67$vck44/vb=7,4 2006.201.07:18:54.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.07:18:54.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.07:18:54.67#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:54.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:54.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:54.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:54.73#ibcon#enter wrdev, iclass 11, count 2 2006.201.07:18:54.73#ibcon#first serial, iclass 11, count 2 2006.201.07:18:54.73#ibcon#enter sib2, iclass 11, count 2 2006.201.07:18:54.73#ibcon#flushed, iclass 11, count 2 2006.201.07:18:54.73#ibcon#about to write, iclass 11, count 2 2006.201.07:18:54.73#ibcon#wrote, iclass 11, count 2 2006.201.07:18:54.73#ibcon#about to read 3, iclass 11, count 2 2006.201.07:18:54.75#ibcon#read 3, iclass 11, count 2 2006.201.07:18:54.75#ibcon#about to read 4, iclass 11, count 2 2006.201.07:18:54.75#ibcon#read 4, iclass 11, count 2 2006.201.07:18:54.75#ibcon#about to read 5, iclass 11, count 2 2006.201.07:18:54.75#ibcon#read 5, iclass 11, count 2 2006.201.07:18:54.75#ibcon#about to read 6, iclass 11, count 2 2006.201.07:18:54.75#ibcon#read 6, iclass 11, count 2 2006.201.07:18:54.75#ibcon#end of sib2, iclass 11, count 2 2006.201.07:18:54.75#ibcon#*mode == 0, iclass 11, count 2 2006.201.07:18:54.75#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.07:18:54.75#ibcon#[27=AT07-04\r\n] 2006.201.07:18:54.75#ibcon#*before write, iclass 11, count 2 2006.201.07:18:54.75#ibcon#enter sib2, iclass 11, count 2 2006.201.07:18:54.75#ibcon#flushed, iclass 11, count 2 2006.201.07:18:54.75#ibcon#about to write, iclass 11, count 2 2006.201.07:18:54.75#ibcon#wrote, iclass 11, count 2 2006.201.07:18:54.75#ibcon#about to read 3, iclass 11, count 2 2006.201.07:18:54.78#ibcon#read 3, iclass 11, count 2 2006.201.07:18:54.78#ibcon#about to read 4, iclass 11, count 2 2006.201.07:18:54.78#ibcon#read 4, iclass 11, count 2 2006.201.07:18:54.78#ibcon#about to read 5, iclass 11, count 2 2006.201.07:18:54.78#ibcon#read 5, iclass 11, count 2 2006.201.07:18:54.78#ibcon#about to read 6, iclass 11, count 2 2006.201.07:18:54.78#ibcon#read 6, iclass 11, count 2 2006.201.07:18:54.78#ibcon#end of sib2, iclass 11, count 2 2006.201.07:18:54.78#ibcon#*after write, iclass 11, count 2 2006.201.07:18:54.78#ibcon#*before return 0, iclass 11, count 2 2006.201.07:18:54.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:54.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:18:54.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.07:18:54.78#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:54.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:54.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:54.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:54.90#ibcon#enter wrdev, iclass 11, count 0 2006.201.07:18:54.90#ibcon#first serial, iclass 11, count 0 2006.201.07:18:54.90#ibcon#enter sib2, iclass 11, count 0 2006.201.07:18:54.90#ibcon#flushed, iclass 11, count 0 2006.201.07:18:54.90#ibcon#about to write, iclass 11, count 0 2006.201.07:18:54.90#ibcon#wrote, iclass 11, count 0 2006.201.07:18:54.90#ibcon#about to read 3, iclass 11, count 0 2006.201.07:18:54.92#ibcon#read 3, iclass 11, count 0 2006.201.07:18:54.92#ibcon#about to read 4, iclass 11, count 0 2006.201.07:18:54.92#ibcon#read 4, iclass 11, count 0 2006.201.07:18:54.92#ibcon#about to read 5, iclass 11, count 0 2006.201.07:18:54.92#ibcon#read 5, iclass 11, count 0 2006.201.07:18:54.92#ibcon#about to read 6, iclass 11, count 0 2006.201.07:18:54.92#ibcon#read 6, iclass 11, count 0 2006.201.07:18:54.92#ibcon#end of sib2, iclass 11, count 0 2006.201.07:18:54.92#ibcon#*mode == 0, iclass 11, count 0 2006.201.07:18:54.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.07:18:54.92#ibcon#[27=USB\r\n] 2006.201.07:18:54.92#ibcon#*before write, iclass 11, count 0 2006.201.07:18:54.92#ibcon#enter sib2, iclass 11, count 0 2006.201.07:18:54.92#ibcon#flushed, iclass 11, count 0 2006.201.07:18:54.92#ibcon#about to write, iclass 11, count 0 2006.201.07:18:54.92#ibcon#wrote, iclass 11, count 0 2006.201.07:18:54.92#ibcon#about to read 3, iclass 11, count 0 2006.201.07:18:54.95#ibcon#read 3, iclass 11, count 0 2006.201.07:18:54.95#ibcon#about to read 4, iclass 11, count 0 2006.201.07:18:54.95#ibcon#read 4, iclass 11, count 0 2006.201.07:18:54.95#ibcon#about to read 5, iclass 11, count 0 2006.201.07:18:54.95#ibcon#read 5, iclass 11, count 0 2006.201.07:18:54.95#ibcon#about to read 6, iclass 11, count 0 2006.201.07:18:54.95#ibcon#read 6, iclass 11, count 0 2006.201.07:18:54.95#ibcon#end of sib2, iclass 11, count 0 2006.201.07:18:54.95#ibcon#*after write, iclass 11, count 0 2006.201.07:18:54.95#ibcon#*before return 0, iclass 11, count 0 2006.201.07:18:54.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:54.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:18:54.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.07:18:54.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.07:18:54.95$vck44/vblo=8,744.99 2006.201.07:18:54.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.07:18:54.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.07:18:54.95#ibcon#ireg 17 cls_cnt 0 2006.201.07:18:54.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:54.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:54.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:54.95#ibcon#enter wrdev, iclass 13, count 0 2006.201.07:18:54.95#ibcon#first serial, iclass 13, count 0 2006.201.07:18:54.95#ibcon#enter sib2, iclass 13, count 0 2006.201.07:18:54.95#ibcon#flushed, iclass 13, count 0 2006.201.07:18:54.95#ibcon#about to write, iclass 13, count 0 2006.201.07:18:54.95#ibcon#wrote, iclass 13, count 0 2006.201.07:18:54.95#ibcon#about to read 3, iclass 13, count 0 2006.201.07:18:54.97#ibcon#read 3, iclass 13, count 0 2006.201.07:18:54.97#ibcon#about to read 4, iclass 13, count 0 2006.201.07:18:54.97#ibcon#read 4, iclass 13, count 0 2006.201.07:18:54.97#ibcon#about to read 5, iclass 13, count 0 2006.201.07:18:54.97#ibcon#read 5, iclass 13, count 0 2006.201.07:18:54.97#ibcon#about to read 6, iclass 13, count 0 2006.201.07:18:54.97#ibcon#read 6, iclass 13, count 0 2006.201.07:18:54.97#ibcon#end of sib2, iclass 13, count 0 2006.201.07:18:54.97#ibcon#*mode == 0, iclass 13, count 0 2006.201.07:18:54.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.07:18:54.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:18:54.97#ibcon#*before write, iclass 13, count 0 2006.201.07:18:54.97#ibcon#enter sib2, iclass 13, count 0 2006.201.07:18:54.97#ibcon#flushed, iclass 13, count 0 2006.201.07:18:54.97#ibcon#about to write, iclass 13, count 0 2006.201.07:18:54.97#ibcon#wrote, iclass 13, count 0 2006.201.07:18:54.97#ibcon#about to read 3, iclass 13, count 0 2006.201.07:18:55.01#ibcon#read 3, iclass 13, count 0 2006.201.07:18:55.01#ibcon#about to read 4, iclass 13, count 0 2006.201.07:18:55.01#ibcon#read 4, iclass 13, count 0 2006.201.07:18:55.01#ibcon#about to read 5, iclass 13, count 0 2006.201.07:18:55.01#ibcon#read 5, iclass 13, count 0 2006.201.07:18:55.01#ibcon#about to read 6, iclass 13, count 0 2006.201.07:18:55.01#ibcon#read 6, iclass 13, count 0 2006.201.07:18:55.01#ibcon#end of sib2, iclass 13, count 0 2006.201.07:18:55.01#ibcon#*after write, iclass 13, count 0 2006.201.07:18:55.01#ibcon#*before return 0, iclass 13, count 0 2006.201.07:18:55.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:55.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:18:55.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.07:18:55.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.07:18:55.01$vck44/vb=8,4 2006.201.07:18:55.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.07:18:55.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.07:18:55.01#ibcon#ireg 11 cls_cnt 2 2006.201.07:18:55.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:55.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:55.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:55.07#ibcon#enter wrdev, iclass 15, count 2 2006.201.07:18:55.07#ibcon#first serial, iclass 15, count 2 2006.201.07:18:55.07#ibcon#enter sib2, iclass 15, count 2 2006.201.07:18:55.07#ibcon#flushed, iclass 15, count 2 2006.201.07:18:55.07#ibcon#about to write, iclass 15, count 2 2006.201.07:18:55.07#ibcon#wrote, iclass 15, count 2 2006.201.07:18:55.07#ibcon#about to read 3, iclass 15, count 2 2006.201.07:18:55.09#ibcon#read 3, iclass 15, count 2 2006.201.07:18:55.09#ibcon#about to read 4, iclass 15, count 2 2006.201.07:18:55.09#ibcon#read 4, iclass 15, count 2 2006.201.07:18:55.09#ibcon#about to read 5, iclass 15, count 2 2006.201.07:18:55.09#ibcon#read 5, iclass 15, count 2 2006.201.07:18:55.09#ibcon#about to read 6, iclass 15, count 2 2006.201.07:18:55.09#ibcon#read 6, iclass 15, count 2 2006.201.07:18:55.09#ibcon#end of sib2, iclass 15, count 2 2006.201.07:18:55.09#ibcon#*mode == 0, iclass 15, count 2 2006.201.07:18:55.09#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.07:18:55.09#ibcon#[27=AT08-04\r\n] 2006.201.07:18:55.09#ibcon#*before write, iclass 15, count 2 2006.201.07:18:55.09#ibcon#enter sib2, iclass 15, count 2 2006.201.07:18:55.09#ibcon#flushed, iclass 15, count 2 2006.201.07:18:55.09#ibcon#about to write, iclass 15, count 2 2006.201.07:18:55.09#ibcon#wrote, iclass 15, count 2 2006.201.07:18:55.09#ibcon#about to read 3, iclass 15, count 2 2006.201.07:18:55.12#ibcon#read 3, iclass 15, count 2 2006.201.07:18:55.12#ibcon#about to read 4, iclass 15, count 2 2006.201.07:18:55.12#ibcon#read 4, iclass 15, count 2 2006.201.07:18:55.12#ibcon#about to read 5, iclass 15, count 2 2006.201.07:18:55.12#ibcon#read 5, iclass 15, count 2 2006.201.07:18:55.12#ibcon#about to read 6, iclass 15, count 2 2006.201.07:18:55.12#ibcon#read 6, iclass 15, count 2 2006.201.07:18:55.12#ibcon#end of sib2, iclass 15, count 2 2006.201.07:18:55.12#ibcon#*after write, iclass 15, count 2 2006.201.07:18:55.12#ibcon#*before return 0, iclass 15, count 2 2006.201.07:18:55.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:55.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:18:55.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.07:18:55.12#ibcon#ireg 7 cls_cnt 0 2006.201.07:18:55.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:55.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:55.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:55.24#ibcon#enter wrdev, iclass 15, count 0 2006.201.07:18:55.24#ibcon#first serial, iclass 15, count 0 2006.201.07:18:55.24#ibcon#enter sib2, iclass 15, count 0 2006.201.07:18:55.24#ibcon#flushed, iclass 15, count 0 2006.201.07:18:55.24#ibcon#about to write, iclass 15, count 0 2006.201.07:18:55.24#ibcon#wrote, iclass 15, count 0 2006.201.07:18:55.24#ibcon#about to read 3, iclass 15, count 0 2006.201.07:18:55.26#ibcon#read 3, iclass 15, count 0 2006.201.07:18:55.26#ibcon#about to read 4, iclass 15, count 0 2006.201.07:18:55.26#ibcon#read 4, iclass 15, count 0 2006.201.07:18:55.26#ibcon#about to read 5, iclass 15, count 0 2006.201.07:18:55.26#ibcon#read 5, iclass 15, count 0 2006.201.07:18:55.26#ibcon#about to read 6, iclass 15, count 0 2006.201.07:18:55.26#ibcon#read 6, iclass 15, count 0 2006.201.07:18:55.26#ibcon#end of sib2, iclass 15, count 0 2006.201.07:18:55.26#ibcon#*mode == 0, iclass 15, count 0 2006.201.07:18:55.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.07:18:55.26#ibcon#[27=USB\r\n] 2006.201.07:18:55.26#ibcon#*before write, iclass 15, count 0 2006.201.07:18:55.26#ibcon#enter sib2, iclass 15, count 0 2006.201.07:18:55.26#ibcon#flushed, iclass 15, count 0 2006.201.07:18:55.26#ibcon#about to write, iclass 15, count 0 2006.201.07:18:55.26#ibcon#wrote, iclass 15, count 0 2006.201.07:18:55.26#ibcon#about to read 3, iclass 15, count 0 2006.201.07:18:55.29#ibcon#read 3, iclass 15, count 0 2006.201.07:18:55.29#ibcon#about to read 4, iclass 15, count 0 2006.201.07:18:55.29#ibcon#read 4, iclass 15, count 0 2006.201.07:18:55.29#ibcon#about to read 5, iclass 15, count 0 2006.201.07:18:55.29#ibcon#read 5, iclass 15, count 0 2006.201.07:18:55.29#ibcon#about to read 6, iclass 15, count 0 2006.201.07:18:55.29#ibcon#read 6, iclass 15, count 0 2006.201.07:18:55.29#ibcon#end of sib2, iclass 15, count 0 2006.201.07:18:55.29#ibcon#*after write, iclass 15, count 0 2006.201.07:18:55.29#ibcon#*before return 0, iclass 15, count 0 2006.201.07:18:55.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:55.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:18:55.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.07:18:55.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.07:18:55.29$vck44/vabw=wide 2006.201.07:18:55.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.07:18:55.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.07:18:55.29#ibcon#ireg 8 cls_cnt 0 2006.201.07:18:55.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:55.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:55.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:55.29#ibcon#enter wrdev, iclass 17, count 0 2006.201.07:18:55.29#ibcon#first serial, iclass 17, count 0 2006.201.07:18:55.29#ibcon#enter sib2, iclass 17, count 0 2006.201.07:18:55.29#ibcon#flushed, iclass 17, count 0 2006.201.07:18:55.29#ibcon#about to write, iclass 17, count 0 2006.201.07:18:55.29#ibcon#wrote, iclass 17, count 0 2006.201.07:18:55.29#ibcon#about to read 3, iclass 17, count 0 2006.201.07:18:55.31#ibcon#read 3, iclass 17, count 0 2006.201.07:18:55.31#ibcon#about to read 4, iclass 17, count 0 2006.201.07:18:55.31#ibcon#read 4, iclass 17, count 0 2006.201.07:18:55.31#ibcon#about to read 5, iclass 17, count 0 2006.201.07:18:55.31#ibcon#read 5, iclass 17, count 0 2006.201.07:18:55.31#ibcon#about to read 6, iclass 17, count 0 2006.201.07:18:55.31#ibcon#read 6, iclass 17, count 0 2006.201.07:18:55.31#ibcon#end of sib2, iclass 17, count 0 2006.201.07:18:55.31#ibcon#*mode == 0, iclass 17, count 0 2006.201.07:18:55.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.07:18:55.31#ibcon#[25=BW32\r\n] 2006.201.07:18:55.31#ibcon#*before write, iclass 17, count 0 2006.201.07:18:55.31#ibcon#enter sib2, iclass 17, count 0 2006.201.07:18:55.31#ibcon#flushed, iclass 17, count 0 2006.201.07:18:55.31#ibcon#about to write, iclass 17, count 0 2006.201.07:18:55.31#ibcon#wrote, iclass 17, count 0 2006.201.07:18:55.31#ibcon#about to read 3, iclass 17, count 0 2006.201.07:18:55.35#ibcon#read 3, iclass 17, count 0 2006.201.07:18:55.35#ibcon#about to read 4, iclass 17, count 0 2006.201.07:18:55.35#ibcon#read 4, iclass 17, count 0 2006.201.07:18:55.35#ibcon#about to read 5, iclass 17, count 0 2006.201.07:18:55.35#ibcon#read 5, iclass 17, count 0 2006.201.07:18:55.35#ibcon#about to read 6, iclass 17, count 0 2006.201.07:18:55.35#ibcon#read 6, iclass 17, count 0 2006.201.07:18:55.35#ibcon#end of sib2, iclass 17, count 0 2006.201.07:18:55.35#ibcon#*after write, iclass 17, count 0 2006.201.07:18:55.35#ibcon#*before return 0, iclass 17, count 0 2006.201.07:18:55.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:55.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:18:55.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.07:18:55.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.07:18:55.35$vck44/vbbw=wide 2006.201.07:18:55.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.07:18:55.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.07:18:55.35#ibcon#ireg 8 cls_cnt 0 2006.201.07:18:55.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:18:55.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:18:55.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:18:55.41#ibcon#enter wrdev, iclass 19, count 0 2006.201.07:18:55.41#ibcon#first serial, iclass 19, count 0 2006.201.07:18:55.41#ibcon#enter sib2, iclass 19, count 0 2006.201.07:18:55.41#ibcon#flushed, iclass 19, count 0 2006.201.07:18:55.41#ibcon#about to write, iclass 19, count 0 2006.201.07:18:55.41#ibcon#wrote, iclass 19, count 0 2006.201.07:18:55.41#ibcon#about to read 3, iclass 19, count 0 2006.201.07:18:55.43#ibcon#read 3, iclass 19, count 0 2006.201.07:18:55.43#ibcon#about to read 4, iclass 19, count 0 2006.201.07:18:55.43#ibcon#read 4, iclass 19, count 0 2006.201.07:18:55.43#ibcon#about to read 5, iclass 19, count 0 2006.201.07:18:55.43#ibcon#read 5, iclass 19, count 0 2006.201.07:18:55.43#ibcon#about to read 6, iclass 19, count 0 2006.201.07:18:55.43#ibcon#read 6, iclass 19, count 0 2006.201.07:18:55.43#ibcon#end of sib2, iclass 19, count 0 2006.201.07:18:55.43#ibcon#*mode == 0, iclass 19, count 0 2006.201.07:18:55.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.07:18:55.43#ibcon#[27=BW32\r\n] 2006.201.07:18:55.43#ibcon#*before write, iclass 19, count 0 2006.201.07:18:55.43#ibcon#enter sib2, iclass 19, count 0 2006.201.07:18:55.43#ibcon#flushed, iclass 19, count 0 2006.201.07:18:55.43#ibcon#about to write, iclass 19, count 0 2006.201.07:18:55.43#ibcon#wrote, iclass 19, count 0 2006.201.07:18:55.43#ibcon#about to read 3, iclass 19, count 0 2006.201.07:18:55.46#ibcon#read 3, iclass 19, count 0 2006.201.07:18:55.46#ibcon#about to read 4, iclass 19, count 0 2006.201.07:18:55.46#ibcon#read 4, iclass 19, count 0 2006.201.07:18:55.46#ibcon#about to read 5, iclass 19, count 0 2006.201.07:18:55.46#ibcon#read 5, iclass 19, count 0 2006.201.07:18:55.46#ibcon#about to read 6, iclass 19, count 0 2006.201.07:18:55.46#ibcon#read 6, iclass 19, count 0 2006.201.07:18:55.46#ibcon#end of sib2, iclass 19, count 0 2006.201.07:18:55.46#ibcon#*after write, iclass 19, count 0 2006.201.07:18:55.46#ibcon#*before return 0, iclass 19, count 0 2006.201.07:18:55.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:18:55.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:18:55.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.07:18:55.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.07:18:55.46$setupk4/ifdk4 2006.201.07:18:55.46$ifdk4/lo= 2006.201.07:18:55.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:18:55.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:18:55.46$ifdk4/patch= 2006.201.07:18:55.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:18:55.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:18:55.46$setupk4/!*+20s 2006.201.07:18:57.41#abcon#<5=/04 2.5 4.2 23.21 881003.1\r\n> 2006.201.07:18:57.43#abcon#{5=INTERFACE CLEAR} 2006.201.07:18:57.49#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:19:07.58#abcon#<5=/04 2.5 4.2 23.21 881003.1\r\n> 2006.201.07:19:07.60#abcon#{5=INTERFACE CLEAR} 2006.201.07:19:07.66#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:19:08.13#trakl#Source acquired 2006.201.07:19:09.13#flagr#flagr/antenna,acquired 2006.201.07:19:09.93$setupk4/"tpicd 2006.201.07:19:09.93$setupk4/echo=off 2006.201.07:19:09.93$setupk4/xlog=off 2006.201.07:19:09.93:!2006.201.07:19:56 2006.201.07:19:56.00:preob 2006.201.07:19:56.13/onsource/TRACKING 2006.201.07:19:56.13:!2006.201.07:20:06 2006.201.07:20:06.00:"tape 2006.201.07:20:06.00:"st=record 2006.201.07:20:06.00:data_valid=on 2006.201.07:20:06.00:midob 2006.201.07:20:06.14/onsource/TRACKING 2006.201.07:20:06.14/wx/23.21,1003.1,88 2006.201.07:20:06.23/cable/+6.4662E-03 2006.201.07:20:07.32/va/01,08,usb,yes,36,39 2006.201.07:20:07.32/va/02,07,usb,yes,39,40 2006.201.07:20:07.32/va/03,08,usb,yes,35,37 2006.201.07:20:07.32/va/04,07,usb,yes,40,43 2006.201.07:20:07.32/va/05,04,usb,yes,36,36 2006.201.07:20:07.32/va/06,05,usb,yes,36,36 2006.201.07:20:07.32/va/07,05,usb,yes,35,36 2006.201.07:20:07.32/va/08,04,usb,yes,35,41 2006.201.07:20:07.55/valo/01,524.99,yes,locked 2006.201.07:20:07.55/valo/02,534.99,yes,locked 2006.201.07:20:07.55/valo/03,564.99,yes,locked 2006.201.07:20:07.55/valo/04,624.99,yes,locked 2006.201.07:20:07.55/valo/05,734.99,yes,locked 2006.201.07:20:07.55/valo/06,814.99,yes,locked 2006.201.07:20:07.55/valo/07,864.99,yes,locked 2006.201.07:20:07.55/valo/08,884.99,yes,locked 2006.201.07:20:08.64/vb/01,04,usb,yes,33,30 2006.201.07:20:08.64/vb/02,05,usb,yes,31,30 2006.201.07:20:08.64/vb/03,04,usb,yes,32,35 2006.201.07:20:08.64/vb/04,05,usb,yes,32,31 2006.201.07:20:08.64/vb/05,04,usb,yes,29,31 2006.201.07:20:08.64/vb/06,04,usb,yes,34,29 2006.201.07:20:08.64/vb/07,04,usb,yes,33,33 2006.201.07:20:08.64/vb/08,04,usb,yes,30,34 2006.201.07:20:08.87/vblo/01,629.99,yes,locked 2006.201.07:20:08.87/vblo/02,634.99,yes,locked 2006.201.07:20:08.87/vblo/03,649.99,yes,locked 2006.201.07:20:08.87/vblo/04,679.99,yes,locked 2006.201.07:20:08.87/vblo/05,709.99,yes,locked 2006.201.07:20:08.87/vblo/06,719.99,yes,locked 2006.201.07:20:08.87/vblo/07,734.99,yes,locked 2006.201.07:20:08.87/vblo/08,744.99,yes,locked 2006.201.07:20:09.02/vabw/8 2006.201.07:20:09.17/vbbw/8 2006.201.07:20:09.29/xfe/off,on,16.2 2006.201.07:20:09.66/ifatt/23,28,28,28 2006.201.07:20:10.05/fmout-gps/S +4.52E-07 2006.201.07:20:10.09:!2006.201.07:20:46 2006.201.07:20:46.00:data_valid=off 2006.201.07:20:46.00:"et 2006.201.07:20:46.00:!+3s 2006.201.07:20:49.02:"tape 2006.201.07:20:49.02:postob 2006.201.07:20:49.23/cable/+6.4673E-03 2006.201.07:20:49.23/wx/23.22,1003.2,88 2006.201.07:20:49.29/fmout-gps/S +4.52E-07 2006.201.07:20:49.29:scan_name=201-0721,jd0607,100 2006.201.07:20:49.29:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.201.07:20:51.14#flagr#flagr/antenna,new-source 2006.201.07:20:51.14:checkk5 2006.201.07:20:51.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:20:51.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:20:52.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:20:52.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:20:52.98/chk_obsdata//k5ts1/T2010720??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:20:53.35/chk_obsdata//k5ts2/T2010720??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:20:53.71/chk_obsdata//k5ts3/T2010720??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:20:54.08/chk_obsdata//k5ts4/T2010720??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.07:20:54.77/k5log//k5ts1_log_newline 2006.201.07:20:55.47/k5log//k5ts2_log_newline 2006.201.07:20:56.17/k5log//k5ts3_log_newline 2006.201.07:20:56.87/k5log//k5ts4_log_newline 2006.201.07:20:56.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:20:56.89:setupk4=1 2006.201.07:20:56.89$setupk4/echo=on 2006.201.07:20:56.89$setupk4/pcalon 2006.201.07:20:56.89$pcalon/"no phase cal control is implemented here 2006.201.07:20:56.89$setupk4/"tpicd=stop 2006.201.07:20:56.89$setupk4/"rec=synch_on 2006.201.07:20:56.89$setupk4/"rec_mode=128 2006.201.07:20:56.89$setupk4/!* 2006.201.07:20:56.89$setupk4/recpk4 2006.201.07:20:56.89$recpk4/recpatch= 2006.201.07:20:56.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:20:56.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:20:56.90$setupk4/vck44 2006.201.07:20:56.90$vck44/valo=1,524.99 2006.201.07:20:56.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.07:20:56.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.07:20:56.90#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:56.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:56.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:56.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:56.90#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:20:56.90#ibcon#first serial, iclass 36, count 0 2006.201.07:20:56.90#ibcon#enter sib2, iclass 36, count 0 2006.201.07:20:56.90#ibcon#flushed, iclass 36, count 0 2006.201.07:20:56.90#ibcon#about to write, iclass 36, count 0 2006.201.07:20:56.90#ibcon#wrote, iclass 36, count 0 2006.201.07:20:56.90#ibcon#about to read 3, iclass 36, count 0 2006.201.07:20:56.93#ibcon#read 3, iclass 36, count 0 2006.201.07:20:56.93#ibcon#about to read 4, iclass 36, count 0 2006.201.07:20:56.93#ibcon#read 4, iclass 36, count 0 2006.201.07:20:56.93#ibcon#about to read 5, iclass 36, count 0 2006.201.07:20:56.93#ibcon#read 5, iclass 36, count 0 2006.201.07:20:56.93#ibcon#about to read 6, iclass 36, count 0 2006.201.07:20:56.93#ibcon#read 6, iclass 36, count 0 2006.201.07:20:56.93#ibcon#end of sib2, iclass 36, count 0 2006.201.07:20:56.93#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:20:56.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:20:56.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:20:56.93#ibcon#*before write, iclass 36, count 0 2006.201.07:20:56.93#ibcon#enter sib2, iclass 36, count 0 2006.201.07:20:56.93#ibcon#flushed, iclass 36, count 0 2006.201.07:20:56.93#ibcon#about to write, iclass 36, count 0 2006.201.07:20:56.93#ibcon#wrote, iclass 36, count 0 2006.201.07:20:56.93#ibcon#about to read 3, iclass 36, count 0 2006.201.07:20:56.98#ibcon#read 3, iclass 36, count 0 2006.201.07:20:56.98#ibcon#about to read 4, iclass 36, count 0 2006.201.07:20:56.98#ibcon#read 4, iclass 36, count 0 2006.201.07:20:56.98#ibcon#about to read 5, iclass 36, count 0 2006.201.07:20:56.98#ibcon#read 5, iclass 36, count 0 2006.201.07:20:56.98#ibcon#about to read 6, iclass 36, count 0 2006.201.07:20:56.98#ibcon#read 6, iclass 36, count 0 2006.201.07:20:56.98#ibcon#end of sib2, iclass 36, count 0 2006.201.07:20:56.98#ibcon#*after write, iclass 36, count 0 2006.201.07:20:56.98#ibcon#*before return 0, iclass 36, count 0 2006.201.07:20:56.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:56.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:56.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:20:56.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:20:56.98$vck44/va=1,8 2006.201.07:20:56.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.07:20:56.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.07:20:56.98#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:56.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:56.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:56.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:56.98#ibcon#enter wrdev, iclass 38, count 2 2006.201.07:20:56.98#ibcon#first serial, iclass 38, count 2 2006.201.07:20:56.98#ibcon#enter sib2, iclass 38, count 2 2006.201.07:20:56.98#ibcon#flushed, iclass 38, count 2 2006.201.07:20:56.98#ibcon#about to write, iclass 38, count 2 2006.201.07:20:56.98#ibcon#wrote, iclass 38, count 2 2006.201.07:20:56.98#ibcon#about to read 3, iclass 38, count 2 2006.201.07:20:57.00#ibcon#read 3, iclass 38, count 2 2006.201.07:20:57.00#ibcon#about to read 4, iclass 38, count 2 2006.201.07:20:57.00#ibcon#read 4, iclass 38, count 2 2006.201.07:20:57.00#ibcon#about to read 5, iclass 38, count 2 2006.201.07:20:57.00#ibcon#read 5, iclass 38, count 2 2006.201.07:20:57.00#ibcon#about to read 6, iclass 38, count 2 2006.201.07:20:57.00#ibcon#read 6, iclass 38, count 2 2006.201.07:20:57.00#ibcon#end of sib2, iclass 38, count 2 2006.201.07:20:57.00#ibcon#*mode == 0, iclass 38, count 2 2006.201.07:20:57.00#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.07:20:57.00#ibcon#[25=AT01-08\r\n] 2006.201.07:20:57.00#ibcon#*before write, iclass 38, count 2 2006.201.07:20:57.00#ibcon#enter sib2, iclass 38, count 2 2006.201.07:20:57.00#ibcon#flushed, iclass 38, count 2 2006.201.07:20:57.00#ibcon#about to write, iclass 38, count 2 2006.201.07:20:57.00#ibcon#wrote, iclass 38, count 2 2006.201.07:20:57.00#ibcon#about to read 3, iclass 38, count 2 2006.201.07:20:57.03#ibcon#read 3, iclass 38, count 2 2006.201.07:20:57.03#ibcon#about to read 4, iclass 38, count 2 2006.201.07:20:57.03#ibcon#read 4, iclass 38, count 2 2006.201.07:20:57.03#ibcon#about to read 5, iclass 38, count 2 2006.201.07:20:57.03#ibcon#read 5, iclass 38, count 2 2006.201.07:20:57.03#ibcon#about to read 6, iclass 38, count 2 2006.201.07:20:57.03#ibcon#read 6, iclass 38, count 2 2006.201.07:20:57.03#ibcon#end of sib2, iclass 38, count 2 2006.201.07:20:57.03#ibcon#*after write, iclass 38, count 2 2006.201.07:20:57.03#ibcon#*before return 0, iclass 38, count 2 2006.201.07:20:57.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:57.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:57.03#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.07:20:57.03#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:57.03#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:57.15#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:57.15#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:57.15#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:20:57.15#ibcon#first serial, iclass 38, count 0 2006.201.07:20:57.15#ibcon#enter sib2, iclass 38, count 0 2006.201.07:20:57.15#ibcon#flushed, iclass 38, count 0 2006.201.07:20:57.15#ibcon#about to write, iclass 38, count 0 2006.201.07:20:57.15#ibcon#wrote, iclass 38, count 0 2006.201.07:20:57.15#ibcon#about to read 3, iclass 38, count 0 2006.201.07:20:57.17#ibcon#read 3, iclass 38, count 0 2006.201.07:20:57.17#ibcon#about to read 4, iclass 38, count 0 2006.201.07:20:57.17#ibcon#read 4, iclass 38, count 0 2006.201.07:20:57.17#ibcon#about to read 5, iclass 38, count 0 2006.201.07:20:57.17#ibcon#read 5, iclass 38, count 0 2006.201.07:20:57.17#ibcon#about to read 6, iclass 38, count 0 2006.201.07:20:57.17#ibcon#read 6, iclass 38, count 0 2006.201.07:20:57.17#ibcon#end of sib2, iclass 38, count 0 2006.201.07:20:57.17#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:20:57.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:20:57.17#ibcon#[25=USB\r\n] 2006.201.07:20:57.17#ibcon#*before write, iclass 38, count 0 2006.201.07:20:57.17#ibcon#enter sib2, iclass 38, count 0 2006.201.07:20:57.17#ibcon#flushed, iclass 38, count 0 2006.201.07:20:57.17#ibcon#about to write, iclass 38, count 0 2006.201.07:20:57.17#ibcon#wrote, iclass 38, count 0 2006.201.07:20:57.17#ibcon#about to read 3, iclass 38, count 0 2006.201.07:20:57.20#ibcon#read 3, iclass 38, count 0 2006.201.07:20:57.20#ibcon#about to read 4, iclass 38, count 0 2006.201.07:20:57.20#ibcon#read 4, iclass 38, count 0 2006.201.07:20:57.20#ibcon#about to read 5, iclass 38, count 0 2006.201.07:20:57.20#ibcon#read 5, iclass 38, count 0 2006.201.07:20:57.20#ibcon#about to read 6, iclass 38, count 0 2006.201.07:20:57.20#ibcon#read 6, iclass 38, count 0 2006.201.07:20:57.20#ibcon#end of sib2, iclass 38, count 0 2006.201.07:20:57.20#ibcon#*after write, iclass 38, count 0 2006.201.07:20:57.20#ibcon#*before return 0, iclass 38, count 0 2006.201.07:20:57.20#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:57.20#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:57.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:20:57.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:20:57.20$vck44/valo=2,534.99 2006.201.07:20:57.20#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.07:20:57.20#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.07:20:57.20#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:57.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:57.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:57.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:57.20#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:20:57.20#ibcon#first serial, iclass 40, count 0 2006.201.07:20:57.20#ibcon#enter sib2, iclass 40, count 0 2006.201.07:20:57.20#ibcon#flushed, iclass 40, count 0 2006.201.07:20:57.20#ibcon#about to write, iclass 40, count 0 2006.201.07:20:57.20#ibcon#wrote, iclass 40, count 0 2006.201.07:20:57.20#ibcon#about to read 3, iclass 40, count 0 2006.201.07:20:57.22#ibcon#read 3, iclass 40, count 0 2006.201.07:20:57.22#ibcon#about to read 4, iclass 40, count 0 2006.201.07:20:57.22#ibcon#read 4, iclass 40, count 0 2006.201.07:20:57.22#ibcon#about to read 5, iclass 40, count 0 2006.201.07:20:57.22#ibcon#read 5, iclass 40, count 0 2006.201.07:20:57.22#ibcon#about to read 6, iclass 40, count 0 2006.201.07:20:57.22#ibcon#read 6, iclass 40, count 0 2006.201.07:20:57.22#ibcon#end of sib2, iclass 40, count 0 2006.201.07:20:57.22#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:20:57.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:20:57.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:20:57.22#ibcon#*before write, iclass 40, count 0 2006.201.07:20:57.22#ibcon#enter sib2, iclass 40, count 0 2006.201.07:20:57.22#ibcon#flushed, iclass 40, count 0 2006.201.07:20:57.22#ibcon#about to write, iclass 40, count 0 2006.201.07:20:57.22#ibcon#wrote, iclass 40, count 0 2006.201.07:20:57.22#ibcon#about to read 3, iclass 40, count 0 2006.201.07:20:57.27#ibcon#read 3, iclass 40, count 0 2006.201.07:20:57.27#ibcon#about to read 4, iclass 40, count 0 2006.201.07:20:57.27#ibcon#read 4, iclass 40, count 0 2006.201.07:20:57.27#ibcon#about to read 5, iclass 40, count 0 2006.201.07:20:57.27#ibcon#read 5, iclass 40, count 0 2006.201.07:20:57.27#ibcon#about to read 6, iclass 40, count 0 2006.201.07:20:57.27#ibcon#read 6, iclass 40, count 0 2006.201.07:20:57.27#ibcon#end of sib2, iclass 40, count 0 2006.201.07:20:57.27#ibcon#*after write, iclass 40, count 0 2006.201.07:20:57.27#ibcon#*before return 0, iclass 40, count 0 2006.201.07:20:57.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:57.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:57.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:20:57.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:20:57.27$vck44/va=2,7 2006.201.07:20:57.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.07:20:57.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.07:20:57.27#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:57.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:20:57.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:20:57.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:20:57.32#ibcon#enter wrdev, iclass 4, count 2 2006.201.07:20:57.32#ibcon#first serial, iclass 4, count 2 2006.201.07:20:57.32#ibcon#enter sib2, iclass 4, count 2 2006.201.07:20:57.32#ibcon#flushed, iclass 4, count 2 2006.201.07:20:57.32#ibcon#about to write, iclass 4, count 2 2006.201.07:20:57.32#ibcon#wrote, iclass 4, count 2 2006.201.07:20:57.32#ibcon#about to read 3, iclass 4, count 2 2006.201.07:20:57.34#ibcon#read 3, iclass 4, count 2 2006.201.07:20:57.34#ibcon#about to read 4, iclass 4, count 2 2006.201.07:20:57.34#ibcon#read 4, iclass 4, count 2 2006.201.07:20:57.34#ibcon#about to read 5, iclass 4, count 2 2006.201.07:20:57.34#ibcon#read 5, iclass 4, count 2 2006.201.07:20:57.34#ibcon#about to read 6, iclass 4, count 2 2006.201.07:20:57.34#ibcon#read 6, iclass 4, count 2 2006.201.07:20:57.34#ibcon#end of sib2, iclass 4, count 2 2006.201.07:20:57.34#ibcon#*mode == 0, iclass 4, count 2 2006.201.07:20:57.34#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.07:20:57.34#ibcon#[25=AT02-07\r\n] 2006.201.07:20:57.34#ibcon#*before write, iclass 4, count 2 2006.201.07:20:57.34#ibcon#enter sib2, iclass 4, count 2 2006.201.07:20:57.34#ibcon#flushed, iclass 4, count 2 2006.201.07:20:57.34#ibcon#about to write, iclass 4, count 2 2006.201.07:20:57.34#ibcon#wrote, iclass 4, count 2 2006.201.07:20:57.34#ibcon#about to read 3, iclass 4, count 2 2006.201.07:20:57.37#ibcon#read 3, iclass 4, count 2 2006.201.07:20:57.37#ibcon#about to read 4, iclass 4, count 2 2006.201.07:20:57.37#ibcon#read 4, iclass 4, count 2 2006.201.07:20:57.37#ibcon#about to read 5, iclass 4, count 2 2006.201.07:20:57.37#ibcon#read 5, iclass 4, count 2 2006.201.07:20:57.37#ibcon#about to read 6, iclass 4, count 2 2006.201.07:20:57.37#ibcon#read 6, iclass 4, count 2 2006.201.07:20:57.37#ibcon#end of sib2, iclass 4, count 2 2006.201.07:20:57.37#ibcon#*after write, iclass 4, count 2 2006.201.07:20:57.37#ibcon#*before return 0, iclass 4, count 2 2006.201.07:20:57.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:20:57.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:20:57.37#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.07:20:57.37#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:57.37#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:20:57.49#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:20:57.49#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:20:57.49#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:20:57.49#ibcon#first serial, iclass 4, count 0 2006.201.07:20:57.49#ibcon#enter sib2, iclass 4, count 0 2006.201.07:20:57.49#ibcon#flushed, iclass 4, count 0 2006.201.07:20:57.49#ibcon#about to write, iclass 4, count 0 2006.201.07:20:57.49#ibcon#wrote, iclass 4, count 0 2006.201.07:20:57.49#ibcon#about to read 3, iclass 4, count 0 2006.201.07:20:57.51#ibcon#read 3, iclass 4, count 0 2006.201.07:20:57.51#ibcon#about to read 4, iclass 4, count 0 2006.201.07:20:57.51#ibcon#read 4, iclass 4, count 0 2006.201.07:20:57.51#ibcon#about to read 5, iclass 4, count 0 2006.201.07:20:57.51#ibcon#read 5, iclass 4, count 0 2006.201.07:20:57.51#ibcon#about to read 6, iclass 4, count 0 2006.201.07:20:57.51#ibcon#read 6, iclass 4, count 0 2006.201.07:20:57.51#ibcon#end of sib2, iclass 4, count 0 2006.201.07:20:57.51#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:20:57.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:20:57.51#ibcon#[25=USB\r\n] 2006.201.07:20:57.51#ibcon#*before write, iclass 4, count 0 2006.201.07:20:57.51#ibcon#enter sib2, iclass 4, count 0 2006.201.07:20:57.51#ibcon#flushed, iclass 4, count 0 2006.201.07:20:57.51#ibcon#about to write, iclass 4, count 0 2006.201.07:20:57.51#ibcon#wrote, iclass 4, count 0 2006.201.07:20:57.51#ibcon#about to read 3, iclass 4, count 0 2006.201.07:20:57.54#ibcon#read 3, iclass 4, count 0 2006.201.07:20:57.54#ibcon#about to read 4, iclass 4, count 0 2006.201.07:20:57.54#ibcon#read 4, iclass 4, count 0 2006.201.07:20:57.54#ibcon#about to read 5, iclass 4, count 0 2006.201.07:20:57.54#ibcon#read 5, iclass 4, count 0 2006.201.07:20:57.54#ibcon#about to read 6, iclass 4, count 0 2006.201.07:20:57.54#ibcon#read 6, iclass 4, count 0 2006.201.07:20:57.54#ibcon#end of sib2, iclass 4, count 0 2006.201.07:20:57.54#ibcon#*after write, iclass 4, count 0 2006.201.07:20:57.54#ibcon#*before return 0, iclass 4, count 0 2006.201.07:20:57.54#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:20:57.54#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:20:57.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:20:57.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:20:57.54$vck44/valo=3,564.99 2006.201.07:20:57.54#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.07:20:57.54#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.07:20:57.54#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:57.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:20:57.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:20:57.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:20:57.54#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:20:57.54#ibcon#first serial, iclass 6, count 0 2006.201.07:20:57.54#ibcon#enter sib2, iclass 6, count 0 2006.201.07:20:57.54#ibcon#flushed, iclass 6, count 0 2006.201.07:20:57.54#ibcon#about to write, iclass 6, count 0 2006.201.07:20:57.54#ibcon#wrote, iclass 6, count 0 2006.201.07:20:57.54#ibcon#about to read 3, iclass 6, count 0 2006.201.07:20:57.56#ibcon#read 3, iclass 6, count 0 2006.201.07:20:57.56#ibcon#about to read 4, iclass 6, count 0 2006.201.07:20:57.56#ibcon#read 4, iclass 6, count 0 2006.201.07:20:57.56#ibcon#about to read 5, iclass 6, count 0 2006.201.07:20:57.56#ibcon#read 5, iclass 6, count 0 2006.201.07:20:57.56#ibcon#about to read 6, iclass 6, count 0 2006.201.07:20:57.56#ibcon#read 6, iclass 6, count 0 2006.201.07:20:57.56#ibcon#end of sib2, iclass 6, count 0 2006.201.07:20:57.56#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:20:57.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:20:57.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:20:57.56#ibcon#*before write, iclass 6, count 0 2006.201.07:20:57.56#ibcon#enter sib2, iclass 6, count 0 2006.201.07:20:57.56#ibcon#flushed, iclass 6, count 0 2006.201.07:20:57.56#ibcon#about to write, iclass 6, count 0 2006.201.07:20:57.56#ibcon#wrote, iclass 6, count 0 2006.201.07:20:57.56#ibcon#about to read 3, iclass 6, count 0 2006.201.07:20:57.60#ibcon#read 3, iclass 6, count 0 2006.201.07:20:57.60#ibcon#about to read 4, iclass 6, count 0 2006.201.07:20:57.60#ibcon#read 4, iclass 6, count 0 2006.201.07:20:57.60#ibcon#about to read 5, iclass 6, count 0 2006.201.07:20:57.60#ibcon#read 5, iclass 6, count 0 2006.201.07:20:57.60#ibcon#about to read 6, iclass 6, count 0 2006.201.07:20:57.60#ibcon#read 6, iclass 6, count 0 2006.201.07:20:57.60#ibcon#end of sib2, iclass 6, count 0 2006.201.07:20:57.60#ibcon#*after write, iclass 6, count 0 2006.201.07:20:57.60#ibcon#*before return 0, iclass 6, count 0 2006.201.07:20:57.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:20:57.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:20:57.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:20:57.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:20:57.60$vck44/va=3,8 2006.201.07:20:57.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.07:20:57.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.07:20:57.60#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:57.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:20:57.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:20:57.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:20:57.66#ibcon#enter wrdev, iclass 10, count 2 2006.201.07:20:57.66#ibcon#first serial, iclass 10, count 2 2006.201.07:20:57.66#ibcon#enter sib2, iclass 10, count 2 2006.201.07:20:57.66#ibcon#flushed, iclass 10, count 2 2006.201.07:20:57.66#ibcon#about to write, iclass 10, count 2 2006.201.07:20:57.66#ibcon#wrote, iclass 10, count 2 2006.201.07:20:57.66#ibcon#about to read 3, iclass 10, count 2 2006.201.07:20:57.68#ibcon#read 3, iclass 10, count 2 2006.201.07:20:57.68#ibcon#about to read 4, iclass 10, count 2 2006.201.07:20:57.68#ibcon#read 4, iclass 10, count 2 2006.201.07:20:57.68#ibcon#about to read 5, iclass 10, count 2 2006.201.07:20:57.68#ibcon#read 5, iclass 10, count 2 2006.201.07:20:57.68#ibcon#about to read 6, iclass 10, count 2 2006.201.07:20:57.68#ibcon#read 6, iclass 10, count 2 2006.201.07:20:57.68#ibcon#end of sib2, iclass 10, count 2 2006.201.07:20:57.68#ibcon#*mode == 0, iclass 10, count 2 2006.201.07:20:57.68#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.07:20:57.68#ibcon#[25=AT03-08\r\n] 2006.201.07:20:57.68#ibcon#*before write, iclass 10, count 2 2006.201.07:20:57.68#ibcon#enter sib2, iclass 10, count 2 2006.201.07:20:57.68#ibcon#flushed, iclass 10, count 2 2006.201.07:20:57.68#ibcon#about to write, iclass 10, count 2 2006.201.07:20:57.68#ibcon#wrote, iclass 10, count 2 2006.201.07:20:57.68#ibcon#about to read 3, iclass 10, count 2 2006.201.07:20:57.71#ibcon#read 3, iclass 10, count 2 2006.201.07:20:57.71#ibcon#about to read 4, iclass 10, count 2 2006.201.07:20:57.71#ibcon#read 4, iclass 10, count 2 2006.201.07:20:57.71#ibcon#about to read 5, iclass 10, count 2 2006.201.07:20:57.71#ibcon#read 5, iclass 10, count 2 2006.201.07:20:57.71#ibcon#about to read 6, iclass 10, count 2 2006.201.07:20:57.71#ibcon#read 6, iclass 10, count 2 2006.201.07:20:57.71#ibcon#end of sib2, iclass 10, count 2 2006.201.07:20:57.71#ibcon#*after write, iclass 10, count 2 2006.201.07:20:57.71#ibcon#*before return 0, iclass 10, count 2 2006.201.07:20:57.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:20:57.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:20:57.71#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.07:20:57.71#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:57.71#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:20:57.83#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:20:57.83#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:20:57.83#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:20:57.83#ibcon#first serial, iclass 10, count 0 2006.201.07:20:57.83#ibcon#enter sib2, iclass 10, count 0 2006.201.07:20:57.83#ibcon#flushed, iclass 10, count 0 2006.201.07:20:57.83#ibcon#about to write, iclass 10, count 0 2006.201.07:20:57.83#ibcon#wrote, iclass 10, count 0 2006.201.07:20:57.83#ibcon#about to read 3, iclass 10, count 0 2006.201.07:20:57.85#ibcon#read 3, iclass 10, count 0 2006.201.07:20:57.85#ibcon#about to read 4, iclass 10, count 0 2006.201.07:20:57.85#ibcon#read 4, iclass 10, count 0 2006.201.07:20:57.85#ibcon#about to read 5, iclass 10, count 0 2006.201.07:20:57.85#ibcon#read 5, iclass 10, count 0 2006.201.07:20:57.85#ibcon#about to read 6, iclass 10, count 0 2006.201.07:20:57.85#ibcon#read 6, iclass 10, count 0 2006.201.07:20:57.85#ibcon#end of sib2, iclass 10, count 0 2006.201.07:20:57.85#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:20:57.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:20:57.85#ibcon#[25=USB\r\n] 2006.201.07:20:57.85#ibcon#*before write, iclass 10, count 0 2006.201.07:20:57.85#ibcon#enter sib2, iclass 10, count 0 2006.201.07:20:57.85#ibcon#flushed, iclass 10, count 0 2006.201.07:20:57.85#ibcon#about to write, iclass 10, count 0 2006.201.07:20:57.85#ibcon#wrote, iclass 10, count 0 2006.201.07:20:57.85#ibcon#about to read 3, iclass 10, count 0 2006.201.07:20:57.88#ibcon#read 3, iclass 10, count 0 2006.201.07:20:57.88#ibcon#about to read 4, iclass 10, count 0 2006.201.07:20:57.88#ibcon#read 4, iclass 10, count 0 2006.201.07:20:57.88#ibcon#about to read 5, iclass 10, count 0 2006.201.07:20:57.88#ibcon#read 5, iclass 10, count 0 2006.201.07:20:57.88#ibcon#about to read 6, iclass 10, count 0 2006.201.07:20:57.88#ibcon#read 6, iclass 10, count 0 2006.201.07:20:57.88#ibcon#end of sib2, iclass 10, count 0 2006.201.07:20:57.88#ibcon#*after write, iclass 10, count 0 2006.201.07:20:57.88#ibcon#*before return 0, iclass 10, count 0 2006.201.07:20:57.88#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:20:57.88#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:20:57.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:20:57.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:20:57.88$vck44/valo=4,624.99 2006.201.07:20:57.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.07:20:57.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.07:20:57.88#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:57.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:20:57.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:20:57.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:20:57.88#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:20:57.88#ibcon#first serial, iclass 12, count 0 2006.201.07:20:57.88#ibcon#enter sib2, iclass 12, count 0 2006.201.07:20:57.88#ibcon#flushed, iclass 12, count 0 2006.201.07:20:57.88#ibcon#about to write, iclass 12, count 0 2006.201.07:20:57.88#ibcon#wrote, iclass 12, count 0 2006.201.07:20:57.88#ibcon#about to read 3, iclass 12, count 0 2006.201.07:20:57.90#ibcon#read 3, iclass 12, count 0 2006.201.07:20:57.90#ibcon#about to read 4, iclass 12, count 0 2006.201.07:20:57.90#ibcon#read 4, iclass 12, count 0 2006.201.07:20:57.90#ibcon#about to read 5, iclass 12, count 0 2006.201.07:20:57.90#ibcon#read 5, iclass 12, count 0 2006.201.07:20:57.90#ibcon#about to read 6, iclass 12, count 0 2006.201.07:20:57.90#ibcon#read 6, iclass 12, count 0 2006.201.07:20:57.90#ibcon#end of sib2, iclass 12, count 0 2006.201.07:20:57.90#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:20:57.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:20:57.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:20:57.90#ibcon#*before write, iclass 12, count 0 2006.201.07:20:57.90#ibcon#enter sib2, iclass 12, count 0 2006.201.07:20:57.90#ibcon#flushed, iclass 12, count 0 2006.201.07:20:57.90#ibcon#about to write, iclass 12, count 0 2006.201.07:20:57.90#ibcon#wrote, iclass 12, count 0 2006.201.07:20:57.90#ibcon#about to read 3, iclass 12, count 0 2006.201.07:20:57.94#ibcon#read 3, iclass 12, count 0 2006.201.07:20:57.94#ibcon#about to read 4, iclass 12, count 0 2006.201.07:20:57.94#ibcon#read 4, iclass 12, count 0 2006.201.07:20:57.94#ibcon#about to read 5, iclass 12, count 0 2006.201.07:20:57.94#ibcon#read 5, iclass 12, count 0 2006.201.07:20:57.94#ibcon#about to read 6, iclass 12, count 0 2006.201.07:20:57.94#ibcon#read 6, iclass 12, count 0 2006.201.07:20:57.94#ibcon#end of sib2, iclass 12, count 0 2006.201.07:20:57.94#ibcon#*after write, iclass 12, count 0 2006.201.07:20:57.94#ibcon#*before return 0, iclass 12, count 0 2006.201.07:20:57.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:20:57.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:20:57.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:20:57.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:20:57.94$vck44/va=4,7 2006.201.07:20:57.94#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.07:20:57.94#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.07:20:57.94#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:57.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:20:58.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:20:58.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:20:58.00#ibcon#enter wrdev, iclass 14, count 2 2006.201.07:20:58.00#ibcon#first serial, iclass 14, count 2 2006.201.07:20:58.00#ibcon#enter sib2, iclass 14, count 2 2006.201.07:20:58.00#ibcon#flushed, iclass 14, count 2 2006.201.07:20:58.00#ibcon#about to write, iclass 14, count 2 2006.201.07:20:58.00#ibcon#wrote, iclass 14, count 2 2006.201.07:20:58.00#ibcon#about to read 3, iclass 14, count 2 2006.201.07:20:58.02#ibcon#read 3, iclass 14, count 2 2006.201.07:20:58.02#ibcon#about to read 4, iclass 14, count 2 2006.201.07:20:58.02#ibcon#read 4, iclass 14, count 2 2006.201.07:20:58.02#ibcon#about to read 5, iclass 14, count 2 2006.201.07:20:58.02#ibcon#read 5, iclass 14, count 2 2006.201.07:20:58.02#ibcon#about to read 6, iclass 14, count 2 2006.201.07:20:58.02#ibcon#read 6, iclass 14, count 2 2006.201.07:20:58.02#ibcon#end of sib2, iclass 14, count 2 2006.201.07:20:58.02#ibcon#*mode == 0, iclass 14, count 2 2006.201.07:20:58.02#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.07:20:58.02#ibcon#[25=AT04-07\r\n] 2006.201.07:20:58.02#ibcon#*before write, iclass 14, count 2 2006.201.07:20:58.02#ibcon#enter sib2, iclass 14, count 2 2006.201.07:20:58.02#ibcon#flushed, iclass 14, count 2 2006.201.07:20:58.02#ibcon#about to write, iclass 14, count 2 2006.201.07:20:58.02#ibcon#wrote, iclass 14, count 2 2006.201.07:20:58.02#ibcon#about to read 3, iclass 14, count 2 2006.201.07:20:58.05#ibcon#read 3, iclass 14, count 2 2006.201.07:20:58.05#ibcon#about to read 4, iclass 14, count 2 2006.201.07:20:58.05#ibcon#read 4, iclass 14, count 2 2006.201.07:20:58.05#ibcon#about to read 5, iclass 14, count 2 2006.201.07:20:58.05#ibcon#read 5, iclass 14, count 2 2006.201.07:20:58.05#ibcon#about to read 6, iclass 14, count 2 2006.201.07:20:58.05#ibcon#read 6, iclass 14, count 2 2006.201.07:20:58.05#ibcon#end of sib2, iclass 14, count 2 2006.201.07:20:58.05#ibcon#*after write, iclass 14, count 2 2006.201.07:20:58.05#ibcon#*before return 0, iclass 14, count 2 2006.201.07:20:58.05#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:20:58.05#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:20:58.05#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.07:20:58.05#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:58.05#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:20:58.17#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:20:58.17#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:20:58.17#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:20:58.17#ibcon#first serial, iclass 14, count 0 2006.201.07:20:58.17#ibcon#enter sib2, iclass 14, count 0 2006.201.07:20:58.17#ibcon#flushed, iclass 14, count 0 2006.201.07:20:58.17#ibcon#about to write, iclass 14, count 0 2006.201.07:20:58.17#ibcon#wrote, iclass 14, count 0 2006.201.07:20:58.17#ibcon#about to read 3, iclass 14, count 0 2006.201.07:20:58.19#ibcon#read 3, iclass 14, count 0 2006.201.07:20:58.19#ibcon#about to read 4, iclass 14, count 0 2006.201.07:20:58.19#ibcon#read 4, iclass 14, count 0 2006.201.07:20:58.19#ibcon#about to read 5, iclass 14, count 0 2006.201.07:20:58.19#ibcon#read 5, iclass 14, count 0 2006.201.07:20:58.19#ibcon#about to read 6, iclass 14, count 0 2006.201.07:20:58.19#ibcon#read 6, iclass 14, count 0 2006.201.07:20:58.19#ibcon#end of sib2, iclass 14, count 0 2006.201.07:20:58.19#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:20:58.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:20:58.19#ibcon#[25=USB\r\n] 2006.201.07:20:58.19#ibcon#*before write, iclass 14, count 0 2006.201.07:20:58.19#ibcon#enter sib2, iclass 14, count 0 2006.201.07:20:58.19#ibcon#flushed, iclass 14, count 0 2006.201.07:20:58.19#ibcon#about to write, iclass 14, count 0 2006.201.07:20:58.19#ibcon#wrote, iclass 14, count 0 2006.201.07:20:58.19#ibcon#about to read 3, iclass 14, count 0 2006.201.07:20:58.22#ibcon#read 3, iclass 14, count 0 2006.201.07:20:58.22#ibcon#about to read 4, iclass 14, count 0 2006.201.07:20:58.22#ibcon#read 4, iclass 14, count 0 2006.201.07:20:58.22#ibcon#about to read 5, iclass 14, count 0 2006.201.07:20:58.22#ibcon#read 5, iclass 14, count 0 2006.201.07:20:58.22#ibcon#about to read 6, iclass 14, count 0 2006.201.07:20:58.22#ibcon#read 6, iclass 14, count 0 2006.201.07:20:58.22#ibcon#end of sib2, iclass 14, count 0 2006.201.07:20:58.22#ibcon#*after write, iclass 14, count 0 2006.201.07:20:58.22#ibcon#*before return 0, iclass 14, count 0 2006.201.07:20:58.22#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:20:58.22#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:20:58.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:20:58.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:20:58.22$vck44/valo=5,734.99 2006.201.07:20:58.22#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.07:20:58.22#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.07:20:58.22#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:58.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:20:58.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:20:58.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:20:58.22#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:20:58.22#ibcon#first serial, iclass 16, count 0 2006.201.07:20:58.22#ibcon#enter sib2, iclass 16, count 0 2006.201.07:20:58.22#ibcon#flushed, iclass 16, count 0 2006.201.07:20:58.22#ibcon#about to write, iclass 16, count 0 2006.201.07:20:58.22#ibcon#wrote, iclass 16, count 0 2006.201.07:20:58.22#ibcon#about to read 3, iclass 16, count 0 2006.201.07:20:58.24#ibcon#read 3, iclass 16, count 0 2006.201.07:20:58.24#ibcon#about to read 4, iclass 16, count 0 2006.201.07:20:58.24#ibcon#read 4, iclass 16, count 0 2006.201.07:20:58.24#ibcon#about to read 5, iclass 16, count 0 2006.201.07:20:58.24#ibcon#read 5, iclass 16, count 0 2006.201.07:20:58.24#ibcon#about to read 6, iclass 16, count 0 2006.201.07:20:58.24#ibcon#read 6, iclass 16, count 0 2006.201.07:20:58.24#ibcon#end of sib2, iclass 16, count 0 2006.201.07:20:58.24#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:20:58.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:20:58.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:20:58.24#ibcon#*before write, iclass 16, count 0 2006.201.07:20:58.24#ibcon#enter sib2, iclass 16, count 0 2006.201.07:20:58.24#ibcon#flushed, iclass 16, count 0 2006.201.07:20:58.24#ibcon#about to write, iclass 16, count 0 2006.201.07:20:58.24#ibcon#wrote, iclass 16, count 0 2006.201.07:20:58.24#ibcon#about to read 3, iclass 16, count 0 2006.201.07:20:58.28#ibcon#read 3, iclass 16, count 0 2006.201.07:20:58.28#ibcon#about to read 4, iclass 16, count 0 2006.201.07:20:58.28#ibcon#read 4, iclass 16, count 0 2006.201.07:20:58.28#ibcon#about to read 5, iclass 16, count 0 2006.201.07:20:58.28#ibcon#read 5, iclass 16, count 0 2006.201.07:20:58.28#ibcon#about to read 6, iclass 16, count 0 2006.201.07:20:58.28#ibcon#read 6, iclass 16, count 0 2006.201.07:20:58.28#ibcon#end of sib2, iclass 16, count 0 2006.201.07:20:58.28#ibcon#*after write, iclass 16, count 0 2006.201.07:20:58.28#ibcon#*before return 0, iclass 16, count 0 2006.201.07:20:58.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:20:58.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:20:58.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:20:58.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:20:58.28$vck44/va=5,4 2006.201.07:20:58.28#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.07:20:58.28#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.07:20:58.28#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:58.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:20:58.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:20:58.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:20:58.34#ibcon#enter wrdev, iclass 18, count 2 2006.201.07:20:58.34#ibcon#first serial, iclass 18, count 2 2006.201.07:20:58.34#ibcon#enter sib2, iclass 18, count 2 2006.201.07:20:58.34#ibcon#flushed, iclass 18, count 2 2006.201.07:20:58.34#ibcon#about to write, iclass 18, count 2 2006.201.07:20:58.34#ibcon#wrote, iclass 18, count 2 2006.201.07:20:58.34#ibcon#about to read 3, iclass 18, count 2 2006.201.07:20:58.36#ibcon#read 3, iclass 18, count 2 2006.201.07:20:58.36#ibcon#about to read 4, iclass 18, count 2 2006.201.07:20:58.36#ibcon#read 4, iclass 18, count 2 2006.201.07:20:58.36#ibcon#about to read 5, iclass 18, count 2 2006.201.07:20:58.36#ibcon#read 5, iclass 18, count 2 2006.201.07:20:58.36#ibcon#about to read 6, iclass 18, count 2 2006.201.07:20:58.36#ibcon#read 6, iclass 18, count 2 2006.201.07:20:58.36#ibcon#end of sib2, iclass 18, count 2 2006.201.07:20:58.36#ibcon#*mode == 0, iclass 18, count 2 2006.201.07:20:58.36#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.07:20:58.36#ibcon#[25=AT05-04\r\n] 2006.201.07:20:58.36#ibcon#*before write, iclass 18, count 2 2006.201.07:20:58.36#ibcon#enter sib2, iclass 18, count 2 2006.201.07:20:58.36#ibcon#flushed, iclass 18, count 2 2006.201.07:20:58.36#ibcon#about to write, iclass 18, count 2 2006.201.07:20:58.36#ibcon#wrote, iclass 18, count 2 2006.201.07:20:58.36#ibcon#about to read 3, iclass 18, count 2 2006.201.07:20:58.39#ibcon#read 3, iclass 18, count 2 2006.201.07:20:58.39#ibcon#about to read 4, iclass 18, count 2 2006.201.07:20:58.39#ibcon#read 4, iclass 18, count 2 2006.201.07:20:58.39#ibcon#about to read 5, iclass 18, count 2 2006.201.07:20:58.39#ibcon#read 5, iclass 18, count 2 2006.201.07:20:58.39#ibcon#about to read 6, iclass 18, count 2 2006.201.07:20:58.39#ibcon#read 6, iclass 18, count 2 2006.201.07:20:58.39#ibcon#end of sib2, iclass 18, count 2 2006.201.07:20:58.39#ibcon#*after write, iclass 18, count 2 2006.201.07:20:58.39#ibcon#*before return 0, iclass 18, count 2 2006.201.07:20:58.39#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:20:58.39#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:20:58.39#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.07:20:58.39#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:58.39#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:20:58.51#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:20:58.51#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:20:58.51#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:20:58.51#ibcon#first serial, iclass 18, count 0 2006.201.07:20:58.51#ibcon#enter sib2, iclass 18, count 0 2006.201.07:20:58.51#ibcon#flushed, iclass 18, count 0 2006.201.07:20:58.51#ibcon#about to write, iclass 18, count 0 2006.201.07:20:58.51#ibcon#wrote, iclass 18, count 0 2006.201.07:20:58.51#ibcon#about to read 3, iclass 18, count 0 2006.201.07:20:58.53#ibcon#read 3, iclass 18, count 0 2006.201.07:20:58.53#ibcon#about to read 4, iclass 18, count 0 2006.201.07:20:58.53#ibcon#read 4, iclass 18, count 0 2006.201.07:20:58.53#ibcon#about to read 5, iclass 18, count 0 2006.201.07:20:58.53#ibcon#read 5, iclass 18, count 0 2006.201.07:20:58.53#ibcon#about to read 6, iclass 18, count 0 2006.201.07:20:58.53#ibcon#read 6, iclass 18, count 0 2006.201.07:20:58.53#ibcon#end of sib2, iclass 18, count 0 2006.201.07:20:58.53#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:20:58.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:20:58.53#ibcon#[25=USB\r\n] 2006.201.07:20:58.53#ibcon#*before write, iclass 18, count 0 2006.201.07:20:58.53#ibcon#enter sib2, iclass 18, count 0 2006.201.07:20:58.53#ibcon#flushed, iclass 18, count 0 2006.201.07:20:58.53#ibcon#about to write, iclass 18, count 0 2006.201.07:20:58.53#ibcon#wrote, iclass 18, count 0 2006.201.07:20:58.53#ibcon#about to read 3, iclass 18, count 0 2006.201.07:20:58.56#ibcon#read 3, iclass 18, count 0 2006.201.07:20:58.56#ibcon#about to read 4, iclass 18, count 0 2006.201.07:20:58.56#ibcon#read 4, iclass 18, count 0 2006.201.07:20:58.56#ibcon#about to read 5, iclass 18, count 0 2006.201.07:20:58.56#ibcon#read 5, iclass 18, count 0 2006.201.07:20:58.56#ibcon#about to read 6, iclass 18, count 0 2006.201.07:20:58.56#ibcon#read 6, iclass 18, count 0 2006.201.07:20:58.56#ibcon#end of sib2, iclass 18, count 0 2006.201.07:20:58.56#ibcon#*after write, iclass 18, count 0 2006.201.07:20:58.56#ibcon#*before return 0, iclass 18, count 0 2006.201.07:20:58.56#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:20:58.56#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:20:58.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:20:58.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:20:58.56$vck44/valo=6,814.99 2006.201.07:20:58.56#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.07:20:58.56#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.07:20:58.56#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:58.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:20:58.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:20:58.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:20:58.56#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:20:58.56#ibcon#first serial, iclass 20, count 0 2006.201.07:20:58.56#ibcon#enter sib2, iclass 20, count 0 2006.201.07:20:58.56#ibcon#flushed, iclass 20, count 0 2006.201.07:20:58.56#ibcon#about to write, iclass 20, count 0 2006.201.07:20:58.56#ibcon#wrote, iclass 20, count 0 2006.201.07:20:58.56#ibcon#about to read 3, iclass 20, count 0 2006.201.07:20:58.58#ibcon#read 3, iclass 20, count 0 2006.201.07:20:58.58#ibcon#about to read 4, iclass 20, count 0 2006.201.07:20:58.58#ibcon#read 4, iclass 20, count 0 2006.201.07:20:58.58#ibcon#about to read 5, iclass 20, count 0 2006.201.07:20:58.58#ibcon#read 5, iclass 20, count 0 2006.201.07:20:58.58#ibcon#about to read 6, iclass 20, count 0 2006.201.07:20:58.58#ibcon#read 6, iclass 20, count 0 2006.201.07:20:58.58#ibcon#end of sib2, iclass 20, count 0 2006.201.07:20:58.58#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:20:58.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:20:58.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:20:58.58#ibcon#*before write, iclass 20, count 0 2006.201.07:20:58.58#ibcon#enter sib2, iclass 20, count 0 2006.201.07:20:58.58#ibcon#flushed, iclass 20, count 0 2006.201.07:20:58.58#ibcon#about to write, iclass 20, count 0 2006.201.07:20:58.58#ibcon#wrote, iclass 20, count 0 2006.201.07:20:58.58#ibcon#about to read 3, iclass 20, count 0 2006.201.07:20:58.62#ibcon#read 3, iclass 20, count 0 2006.201.07:20:58.62#ibcon#about to read 4, iclass 20, count 0 2006.201.07:20:58.62#ibcon#read 4, iclass 20, count 0 2006.201.07:20:58.62#ibcon#about to read 5, iclass 20, count 0 2006.201.07:20:58.62#ibcon#read 5, iclass 20, count 0 2006.201.07:20:58.62#ibcon#about to read 6, iclass 20, count 0 2006.201.07:20:58.62#ibcon#read 6, iclass 20, count 0 2006.201.07:20:58.62#ibcon#end of sib2, iclass 20, count 0 2006.201.07:20:58.62#ibcon#*after write, iclass 20, count 0 2006.201.07:20:58.62#ibcon#*before return 0, iclass 20, count 0 2006.201.07:20:58.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:20:58.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:20:58.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:20:58.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:20:58.62$vck44/va=6,5 2006.201.07:20:58.62#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.07:20:58.62#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.07:20:58.62#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:58.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:20:58.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:20:58.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:20:58.68#ibcon#enter wrdev, iclass 22, count 2 2006.201.07:20:58.68#ibcon#first serial, iclass 22, count 2 2006.201.07:20:58.68#ibcon#enter sib2, iclass 22, count 2 2006.201.07:20:58.68#ibcon#flushed, iclass 22, count 2 2006.201.07:20:58.68#ibcon#about to write, iclass 22, count 2 2006.201.07:20:58.68#ibcon#wrote, iclass 22, count 2 2006.201.07:20:58.68#ibcon#about to read 3, iclass 22, count 2 2006.201.07:20:58.70#ibcon#read 3, iclass 22, count 2 2006.201.07:20:58.70#ibcon#about to read 4, iclass 22, count 2 2006.201.07:20:58.70#ibcon#read 4, iclass 22, count 2 2006.201.07:20:58.70#ibcon#about to read 5, iclass 22, count 2 2006.201.07:20:58.70#ibcon#read 5, iclass 22, count 2 2006.201.07:20:58.70#ibcon#about to read 6, iclass 22, count 2 2006.201.07:20:58.70#ibcon#read 6, iclass 22, count 2 2006.201.07:20:58.70#ibcon#end of sib2, iclass 22, count 2 2006.201.07:20:58.70#ibcon#*mode == 0, iclass 22, count 2 2006.201.07:20:58.70#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.07:20:58.70#ibcon#[25=AT06-05\r\n] 2006.201.07:20:58.70#ibcon#*before write, iclass 22, count 2 2006.201.07:20:58.70#ibcon#enter sib2, iclass 22, count 2 2006.201.07:20:58.70#ibcon#flushed, iclass 22, count 2 2006.201.07:20:58.70#ibcon#about to write, iclass 22, count 2 2006.201.07:20:58.70#ibcon#wrote, iclass 22, count 2 2006.201.07:20:58.70#ibcon#about to read 3, iclass 22, count 2 2006.201.07:20:58.73#ibcon#read 3, iclass 22, count 2 2006.201.07:20:58.73#ibcon#about to read 4, iclass 22, count 2 2006.201.07:20:58.73#ibcon#read 4, iclass 22, count 2 2006.201.07:20:58.73#ibcon#about to read 5, iclass 22, count 2 2006.201.07:20:58.73#ibcon#read 5, iclass 22, count 2 2006.201.07:20:58.73#ibcon#about to read 6, iclass 22, count 2 2006.201.07:20:58.73#ibcon#read 6, iclass 22, count 2 2006.201.07:20:58.73#ibcon#end of sib2, iclass 22, count 2 2006.201.07:20:58.73#ibcon#*after write, iclass 22, count 2 2006.201.07:20:58.73#ibcon#*before return 0, iclass 22, count 2 2006.201.07:20:58.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:20:58.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:20:58.73#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.07:20:58.73#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:58.73#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:20:58.85#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:20:58.85#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:20:58.85#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:20:58.85#ibcon#first serial, iclass 22, count 0 2006.201.07:20:58.85#ibcon#enter sib2, iclass 22, count 0 2006.201.07:20:58.85#ibcon#flushed, iclass 22, count 0 2006.201.07:20:58.85#ibcon#about to write, iclass 22, count 0 2006.201.07:20:58.85#ibcon#wrote, iclass 22, count 0 2006.201.07:20:58.85#ibcon#about to read 3, iclass 22, count 0 2006.201.07:20:58.87#ibcon#read 3, iclass 22, count 0 2006.201.07:20:58.87#ibcon#about to read 4, iclass 22, count 0 2006.201.07:20:58.87#ibcon#read 4, iclass 22, count 0 2006.201.07:20:58.87#ibcon#about to read 5, iclass 22, count 0 2006.201.07:20:58.87#ibcon#read 5, iclass 22, count 0 2006.201.07:20:58.87#ibcon#about to read 6, iclass 22, count 0 2006.201.07:20:58.87#ibcon#read 6, iclass 22, count 0 2006.201.07:20:58.87#ibcon#end of sib2, iclass 22, count 0 2006.201.07:20:58.87#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:20:58.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:20:58.87#ibcon#[25=USB\r\n] 2006.201.07:20:58.87#ibcon#*before write, iclass 22, count 0 2006.201.07:20:58.87#ibcon#enter sib2, iclass 22, count 0 2006.201.07:20:58.87#ibcon#flushed, iclass 22, count 0 2006.201.07:20:58.87#ibcon#about to write, iclass 22, count 0 2006.201.07:20:58.87#ibcon#wrote, iclass 22, count 0 2006.201.07:20:58.87#ibcon#about to read 3, iclass 22, count 0 2006.201.07:20:58.90#ibcon#read 3, iclass 22, count 0 2006.201.07:20:58.90#ibcon#about to read 4, iclass 22, count 0 2006.201.07:20:58.90#ibcon#read 4, iclass 22, count 0 2006.201.07:20:58.90#ibcon#about to read 5, iclass 22, count 0 2006.201.07:20:58.90#ibcon#read 5, iclass 22, count 0 2006.201.07:20:58.90#ibcon#about to read 6, iclass 22, count 0 2006.201.07:20:58.90#ibcon#read 6, iclass 22, count 0 2006.201.07:20:58.90#ibcon#end of sib2, iclass 22, count 0 2006.201.07:20:58.90#ibcon#*after write, iclass 22, count 0 2006.201.07:20:58.90#ibcon#*before return 0, iclass 22, count 0 2006.201.07:20:58.90#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:20:58.90#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:20:58.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:20:58.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:20:58.90$vck44/valo=7,864.99 2006.201.07:20:58.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.07:20:58.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.07:20:58.90#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:58.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:20:58.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:20:58.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:20:58.90#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:20:58.90#ibcon#first serial, iclass 24, count 0 2006.201.07:20:58.90#ibcon#enter sib2, iclass 24, count 0 2006.201.07:20:58.90#ibcon#flushed, iclass 24, count 0 2006.201.07:20:58.90#ibcon#about to write, iclass 24, count 0 2006.201.07:20:58.90#ibcon#wrote, iclass 24, count 0 2006.201.07:20:58.90#ibcon#about to read 3, iclass 24, count 0 2006.201.07:20:58.92#ibcon#read 3, iclass 24, count 0 2006.201.07:20:58.92#ibcon#about to read 4, iclass 24, count 0 2006.201.07:20:58.92#ibcon#read 4, iclass 24, count 0 2006.201.07:20:58.92#ibcon#about to read 5, iclass 24, count 0 2006.201.07:20:58.92#ibcon#read 5, iclass 24, count 0 2006.201.07:20:58.92#ibcon#about to read 6, iclass 24, count 0 2006.201.07:20:58.92#ibcon#read 6, iclass 24, count 0 2006.201.07:20:58.92#ibcon#end of sib2, iclass 24, count 0 2006.201.07:20:58.92#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:20:58.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:20:58.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:20:58.92#ibcon#*before write, iclass 24, count 0 2006.201.07:20:58.92#ibcon#enter sib2, iclass 24, count 0 2006.201.07:20:58.92#ibcon#flushed, iclass 24, count 0 2006.201.07:20:58.92#ibcon#about to write, iclass 24, count 0 2006.201.07:20:58.92#ibcon#wrote, iclass 24, count 0 2006.201.07:20:58.92#ibcon#about to read 3, iclass 24, count 0 2006.201.07:20:58.96#ibcon#read 3, iclass 24, count 0 2006.201.07:20:58.96#ibcon#about to read 4, iclass 24, count 0 2006.201.07:20:58.96#ibcon#read 4, iclass 24, count 0 2006.201.07:20:58.96#ibcon#about to read 5, iclass 24, count 0 2006.201.07:20:58.96#ibcon#read 5, iclass 24, count 0 2006.201.07:20:58.96#ibcon#about to read 6, iclass 24, count 0 2006.201.07:20:58.96#ibcon#read 6, iclass 24, count 0 2006.201.07:20:58.96#ibcon#end of sib2, iclass 24, count 0 2006.201.07:20:58.96#ibcon#*after write, iclass 24, count 0 2006.201.07:20:58.96#ibcon#*before return 0, iclass 24, count 0 2006.201.07:20:58.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:20:58.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:20:58.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:20:58.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:20:58.96$vck44/va=7,5 2006.201.07:20:58.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.07:20:58.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.07:20:58.96#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:58.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:20:59.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:20:59.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:20:59.02#ibcon#enter wrdev, iclass 26, count 2 2006.201.07:20:59.02#ibcon#first serial, iclass 26, count 2 2006.201.07:20:59.02#ibcon#enter sib2, iclass 26, count 2 2006.201.07:20:59.02#ibcon#flushed, iclass 26, count 2 2006.201.07:20:59.02#ibcon#about to write, iclass 26, count 2 2006.201.07:20:59.02#ibcon#wrote, iclass 26, count 2 2006.201.07:20:59.02#ibcon#about to read 3, iclass 26, count 2 2006.201.07:20:59.04#ibcon#read 3, iclass 26, count 2 2006.201.07:20:59.04#ibcon#about to read 4, iclass 26, count 2 2006.201.07:20:59.04#ibcon#read 4, iclass 26, count 2 2006.201.07:20:59.04#ibcon#about to read 5, iclass 26, count 2 2006.201.07:20:59.04#ibcon#read 5, iclass 26, count 2 2006.201.07:20:59.04#ibcon#about to read 6, iclass 26, count 2 2006.201.07:20:59.04#ibcon#read 6, iclass 26, count 2 2006.201.07:20:59.04#ibcon#end of sib2, iclass 26, count 2 2006.201.07:20:59.04#ibcon#*mode == 0, iclass 26, count 2 2006.201.07:20:59.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.07:20:59.04#ibcon#[25=AT07-05\r\n] 2006.201.07:20:59.04#ibcon#*before write, iclass 26, count 2 2006.201.07:20:59.04#ibcon#enter sib2, iclass 26, count 2 2006.201.07:20:59.04#ibcon#flushed, iclass 26, count 2 2006.201.07:20:59.04#ibcon#about to write, iclass 26, count 2 2006.201.07:20:59.04#ibcon#wrote, iclass 26, count 2 2006.201.07:20:59.04#ibcon#about to read 3, iclass 26, count 2 2006.201.07:20:59.07#ibcon#read 3, iclass 26, count 2 2006.201.07:20:59.07#ibcon#about to read 4, iclass 26, count 2 2006.201.07:20:59.07#ibcon#read 4, iclass 26, count 2 2006.201.07:20:59.07#ibcon#about to read 5, iclass 26, count 2 2006.201.07:20:59.07#ibcon#read 5, iclass 26, count 2 2006.201.07:20:59.07#ibcon#about to read 6, iclass 26, count 2 2006.201.07:20:59.07#ibcon#read 6, iclass 26, count 2 2006.201.07:20:59.07#ibcon#end of sib2, iclass 26, count 2 2006.201.07:20:59.07#ibcon#*after write, iclass 26, count 2 2006.201.07:20:59.07#ibcon#*before return 0, iclass 26, count 2 2006.201.07:20:59.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:20:59.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:20:59.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.07:20:59.07#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:59.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:20:59.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:20:59.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:20:59.19#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:20:59.19#ibcon#first serial, iclass 26, count 0 2006.201.07:20:59.19#ibcon#enter sib2, iclass 26, count 0 2006.201.07:20:59.19#ibcon#flushed, iclass 26, count 0 2006.201.07:20:59.19#ibcon#about to write, iclass 26, count 0 2006.201.07:20:59.19#ibcon#wrote, iclass 26, count 0 2006.201.07:20:59.19#ibcon#about to read 3, iclass 26, count 0 2006.201.07:20:59.21#ibcon#read 3, iclass 26, count 0 2006.201.07:20:59.21#ibcon#about to read 4, iclass 26, count 0 2006.201.07:20:59.21#ibcon#read 4, iclass 26, count 0 2006.201.07:20:59.21#ibcon#about to read 5, iclass 26, count 0 2006.201.07:20:59.21#ibcon#read 5, iclass 26, count 0 2006.201.07:20:59.21#ibcon#about to read 6, iclass 26, count 0 2006.201.07:20:59.21#ibcon#read 6, iclass 26, count 0 2006.201.07:20:59.21#ibcon#end of sib2, iclass 26, count 0 2006.201.07:20:59.21#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:20:59.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:20:59.21#ibcon#[25=USB\r\n] 2006.201.07:20:59.21#ibcon#*before write, iclass 26, count 0 2006.201.07:20:59.21#ibcon#enter sib2, iclass 26, count 0 2006.201.07:20:59.21#ibcon#flushed, iclass 26, count 0 2006.201.07:20:59.21#ibcon#about to write, iclass 26, count 0 2006.201.07:20:59.21#ibcon#wrote, iclass 26, count 0 2006.201.07:20:59.21#ibcon#about to read 3, iclass 26, count 0 2006.201.07:20:59.24#ibcon#read 3, iclass 26, count 0 2006.201.07:20:59.24#ibcon#about to read 4, iclass 26, count 0 2006.201.07:20:59.24#ibcon#read 4, iclass 26, count 0 2006.201.07:20:59.24#ibcon#about to read 5, iclass 26, count 0 2006.201.07:20:59.24#ibcon#read 5, iclass 26, count 0 2006.201.07:20:59.24#ibcon#about to read 6, iclass 26, count 0 2006.201.07:20:59.24#ibcon#read 6, iclass 26, count 0 2006.201.07:20:59.24#ibcon#end of sib2, iclass 26, count 0 2006.201.07:20:59.24#ibcon#*after write, iclass 26, count 0 2006.201.07:20:59.24#ibcon#*before return 0, iclass 26, count 0 2006.201.07:20:59.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:20:59.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:20:59.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:20:59.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:20:59.24$vck44/valo=8,884.99 2006.201.07:20:59.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.07:20:59.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.07:20:59.24#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:59.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:20:59.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:20:59.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:20:59.24#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:20:59.24#ibcon#first serial, iclass 28, count 0 2006.201.07:20:59.24#ibcon#enter sib2, iclass 28, count 0 2006.201.07:20:59.24#ibcon#flushed, iclass 28, count 0 2006.201.07:20:59.24#ibcon#about to write, iclass 28, count 0 2006.201.07:20:59.24#ibcon#wrote, iclass 28, count 0 2006.201.07:20:59.24#ibcon#about to read 3, iclass 28, count 0 2006.201.07:20:59.26#ibcon#read 3, iclass 28, count 0 2006.201.07:20:59.26#ibcon#about to read 4, iclass 28, count 0 2006.201.07:20:59.26#ibcon#read 4, iclass 28, count 0 2006.201.07:20:59.26#ibcon#about to read 5, iclass 28, count 0 2006.201.07:20:59.26#ibcon#read 5, iclass 28, count 0 2006.201.07:20:59.26#ibcon#about to read 6, iclass 28, count 0 2006.201.07:20:59.26#ibcon#read 6, iclass 28, count 0 2006.201.07:20:59.26#ibcon#end of sib2, iclass 28, count 0 2006.201.07:20:59.26#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:20:59.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:20:59.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:20:59.26#ibcon#*before write, iclass 28, count 0 2006.201.07:20:59.26#ibcon#enter sib2, iclass 28, count 0 2006.201.07:20:59.26#ibcon#flushed, iclass 28, count 0 2006.201.07:20:59.26#ibcon#about to write, iclass 28, count 0 2006.201.07:20:59.26#ibcon#wrote, iclass 28, count 0 2006.201.07:20:59.26#ibcon#about to read 3, iclass 28, count 0 2006.201.07:20:59.30#ibcon#read 3, iclass 28, count 0 2006.201.07:20:59.30#ibcon#about to read 4, iclass 28, count 0 2006.201.07:20:59.30#ibcon#read 4, iclass 28, count 0 2006.201.07:20:59.30#ibcon#about to read 5, iclass 28, count 0 2006.201.07:20:59.30#ibcon#read 5, iclass 28, count 0 2006.201.07:20:59.30#ibcon#about to read 6, iclass 28, count 0 2006.201.07:20:59.30#ibcon#read 6, iclass 28, count 0 2006.201.07:20:59.30#ibcon#end of sib2, iclass 28, count 0 2006.201.07:20:59.30#ibcon#*after write, iclass 28, count 0 2006.201.07:20:59.30#ibcon#*before return 0, iclass 28, count 0 2006.201.07:20:59.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:20:59.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:20:59.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:20:59.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:20:59.30$vck44/va=8,4 2006.201.07:20:59.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.07:20:59.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.07:20:59.30#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:59.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:20:59.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:20:59.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:20:59.36#ibcon#enter wrdev, iclass 30, count 2 2006.201.07:20:59.36#ibcon#first serial, iclass 30, count 2 2006.201.07:20:59.36#ibcon#enter sib2, iclass 30, count 2 2006.201.07:20:59.36#ibcon#flushed, iclass 30, count 2 2006.201.07:20:59.36#ibcon#about to write, iclass 30, count 2 2006.201.07:20:59.36#ibcon#wrote, iclass 30, count 2 2006.201.07:20:59.36#ibcon#about to read 3, iclass 30, count 2 2006.201.07:20:59.38#ibcon#read 3, iclass 30, count 2 2006.201.07:20:59.38#ibcon#about to read 4, iclass 30, count 2 2006.201.07:20:59.38#ibcon#read 4, iclass 30, count 2 2006.201.07:20:59.38#ibcon#about to read 5, iclass 30, count 2 2006.201.07:20:59.38#ibcon#read 5, iclass 30, count 2 2006.201.07:20:59.38#ibcon#about to read 6, iclass 30, count 2 2006.201.07:20:59.38#ibcon#read 6, iclass 30, count 2 2006.201.07:20:59.38#ibcon#end of sib2, iclass 30, count 2 2006.201.07:20:59.38#ibcon#*mode == 0, iclass 30, count 2 2006.201.07:20:59.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.07:20:59.38#ibcon#[25=AT08-04\r\n] 2006.201.07:20:59.38#ibcon#*before write, iclass 30, count 2 2006.201.07:20:59.38#ibcon#enter sib2, iclass 30, count 2 2006.201.07:20:59.38#ibcon#flushed, iclass 30, count 2 2006.201.07:20:59.38#ibcon#about to write, iclass 30, count 2 2006.201.07:20:59.38#ibcon#wrote, iclass 30, count 2 2006.201.07:20:59.38#ibcon#about to read 3, iclass 30, count 2 2006.201.07:20:59.41#ibcon#read 3, iclass 30, count 2 2006.201.07:20:59.41#ibcon#about to read 4, iclass 30, count 2 2006.201.07:20:59.41#ibcon#read 4, iclass 30, count 2 2006.201.07:20:59.41#ibcon#about to read 5, iclass 30, count 2 2006.201.07:20:59.41#ibcon#read 5, iclass 30, count 2 2006.201.07:20:59.41#ibcon#about to read 6, iclass 30, count 2 2006.201.07:20:59.41#ibcon#read 6, iclass 30, count 2 2006.201.07:20:59.41#ibcon#end of sib2, iclass 30, count 2 2006.201.07:20:59.41#ibcon#*after write, iclass 30, count 2 2006.201.07:20:59.41#ibcon#*before return 0, iclass 30, count 2 2006.201.07:20:59.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:20:59.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:20:59.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.07:20:59.41#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:59.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:20:59.45#abcon#<5=/05 2.4 4.2 23.22 881003.1\r\n> 2006.201.07:20:59.47#abcon#{5=INTERFACE CLEAR} 2006.201.07:20:59.53#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:20:59.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:20:59.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:20:59.53#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:20:59.53#ibcon#first serial, iclass 30, count 0 2006.201.07:20:59.53#ibcon#enter sib2, iclass 30, count 0 2006.201.07:20:59.53#ibcon#flushed, iclass 30, count 0 2006.201.07:20:59.53#ibcon#about to write, iclass 30, count 0 2006.201.07:20:59.53#ibcon#wrote, iclass 30, count 0 2006.201.07:20:59.53#ibcon#about to read 3, iclass 30, count 0 2006.201.07:20:59.55#ibcon#read 3, iclass 30, count 0 2006.201.07:20:59.55#ibcon#about to read 4, iclass 30, count 0 2006.201.07:20:59.55#ibcon#read 4, iclass 30, count 0 2006.201.07:20:59.55#ibcon#about to read 5, iclass 30, count 0 2006.201.07:20:59.55#ibcon#read 5, iclass 30, count 0 2006.201.07:20:59.55#ibcon#about to read 6, iclass 30, count 0 2006.201.07:20:59.55#ibcon#read 6, iclass 30, count 0 2006.201.07:20:59.55#ibcon#end of sib2, iclass 30, count 0 2006.201.07:20:59.55#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:20:59.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:20:59.55#ibcon#[25=USB\r\n] 2006.201.07:20:59.55#ibcon#*before write, iclass 30, count 0 2006.201.07:20:59.55#ibcon#enter sib2, iclass 30, count 0 2006.201.07:20:59.55#ibcon#flushed, iclass 30, count 0 2006.201.07:20:59.55#ibcon#about to write, iclass 30, count 0 2006.201.07:20:59.55#ibcon#wrote, iclass 30, count 0 2006.201.07:20:59.55#ibcon#about to read 3, iclass 30, count 0 2006.201.07:20:59.58#ibcon#read 3, iclass 30, count 0 2006.201.07:20:59.58#ibcon#about to read 4, iclass 30, count 0 2006.201.07:20:59.58#ibcon#read 4, iclass 30, count 0 2006.201.07:20:59.58#ibcon#about to read 5, iclass 30, count 0 2006.201.07:20:59.58#ibcon#read 5, iclass 30, count 0 2006.201.07:20:59.58#ibcon#about to read 6, iclass 30, count 0 2006.201.07:20:59.58#ibcon#read 6, iclass 30, count 0 2006.201.07:20:59.58#ibcon#end of sib2, iclass 30, count 0 2006.201.07:20:59.58#ibcon#*after write, iclass 30, count 0 2006.201.07:20:59.58#ibcon#*before return 0, iclass 30, count 0 2006.201.07:20:59.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:20:59.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:20:59.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:20:59.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:20:59.58$vck44/vblo=1,629.99 2006.201.07:20:59.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.07:20:59.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.07:20:59.58#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:59.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:59.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:59.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:59.58#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:20:59.58#ibcon#first serial, iclass 36, count 0 2006.201.07:20:59.58#ibcon#enter sib2, iclass 36, count 0 2006.201.07:20:59.58#ibcon#flushed, iclass 36, count 0 2006.201.07:20:59.58#ibcon#about to write, iclass 36, count 0 2006.201.07:20:59.58#ibcon#wrote, iclass 36, count 0 2006.201.07:20:59.58#ibcon#about to read 3, iclass 36, count 0 2006.201.07:20:59.60#ibcon#read 3, iclass 36, count 0 2006.201.07:20:59.60#ibcon#about to read 4, iclass 36, count 0 2006.201.07:20:59.60#ibcon#read 4, iclass 36, count 0 2006.201.07:20:59.60#ibcon#about to read 5, iclass 36, count 0 2006.201.07:20:59.60#ibcon#read 5, iclass 36, count 0 2006.201.07:20:59.60#ibcon#about to read 6, iclass 36, count 0 2006.201.07:20:59.60#ibcon#read 6, iclass 36, count 0 2006.201.07:20:59.60#ibcon#end of sib2, iclass 36, count 0 2006.201.07:20:59.60#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:20:59.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:20:59.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:20:59.60#ibcon#*before write, iclass 36, count 0 2006.201.07:20:59.60#ibcon#enter sib2, iclass 36, count 0 2006.201.07:20:59.60#ibcon#flushed, iclass 36, count 0 2006.201.07:20:59.60#ibcon#about to write, iclass 36, count 0 2006.201.07:20:59.60#ibcon#wrote, iclass 36, count 0 2006.201.07:20:59.60#ibcon#about to read 3, iclass 36, count 0 2006.201.07:20:59.64#ibcon#read 3, iclass 36, count 0 2006.201.07:20:59.64#ibcon#about to read 4, iclass 36, count 0 2006.201.07:20:59.64#ibcon#read 4, iclass 36, count 0 2006.201.07:20:59.64#ibcon#about to read 5, iclass 36, count 0 2006.201.07:20:59.64#ibcon#read 5, iclass 36, count 0 2006.201.07:20:59.64#ibcon#about to read 6, iclass 36, count 0 2006.201.07:20:59.64#ibcon#read 6, iclass 36, count 0 2006.201.07:20:59.64#ibcon#end of sib2, iclass 36, count 0 2006.201.07:20:59.64#ibcon#*after write, iclass 36, count 0 2006.201.07:20:59.64#ibcon#*before return 0, iclass 36, count 0 2006.201.07:20:59.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:59.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:20:59.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:20:59.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:20:59.64$vck44/vb=1,4 2006.201.07:20:59.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.07:20:59.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.07:20:59.64#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:59.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:59.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:59.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:59.64#ibcon#enter wrdev, iclass 38, count 2 2006.201.07:20:59.64#ibcon#first serial, iclass 38, count 2 2006.201.07:20:59.64#ibcon#enter sib2, iclass 38, count 2 2006.201.07:20:59.64#ibcon#flushed, iclass 38, count 2 2006.201.07:20:59.64#ibcon#about to write, iclass 38, count 2 2006.201.07:20:59.64#ibcon#wrote, iclass 38, count 2 2006.201.07:20:59.64#ibcon#about to read 3, iclass 38, count 2 2006.201.07:20:59.66#ibcon#read 3, iclass 38, count 2 2006.201.07:20:59.66#ibcon#about to read 4, iclass 38, count 2 2006.201.07:20:59.66#ibcon#read 4, iclass 38, count 2 2006.201.07:20:59.66#ibcon#about to read 5, iclass 38, count 2 2006.201.07:20:59.66#ibcon#read 5, iclass 38, count 2 2006.201.07:20:59.66#ibcon#about to read 6, iclass 38, count 2 2006.201.07:20:59.66#ibcon#read 6, iclass 38, count 2 2006.201.07:20:59.66#ibcon#end of sib2, iclass 38, count 2 2006.201.07:20:59.66#ibcon#*mode == 0, iclass 38, count 2 2006.201.07:20:59.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.07:20:59.66#ibcon#[27=AT01-04\r\n] 2006.201.07:20:59.66#ibcon#*before write, iclass 38, count 2 2006.201.07:20:59.66#ibcon#enter sib2, iclass 38, count 2 2006.201.07:20:59.66#ibcon#flushed, iclass 38, count 2 2006.201.07:20:59.66#ibcon#about to write, iclass 38, count 2 2006.201.07:20:59.66#ibcon#wrote, iclass 38, count 2 2006.201.07:20:59.66#ibcon#about to read 3, iclass 38, count 2 2006.201.07:20:59.69#ibcon#read 3, iclass 38, count 2 2006.201.07:20:59.69#ibcon#about to read 4, iclass 38, count 2 2006.201.07:20:59.69#ibcon#read 4, iclass 38, count 2 2006.201.07:20:59.69#ibcon#about to read 5, iclass 38, count 2 2006.201.07:20:59.69#ibcon#read 5, iclass 38, count 2 2006.201.07:20:59.69#ibcon#about to read 6, iclass 38, count 2 2006.201.07:20:59.69#ibcon#read 6, iclass 38, count 2 2006.201.07:20:59.69#ibcon#end of sib2, iclass 38, count 2 2006.201.07:20:59.69#ibcon#*after write, iclass 38, count 2 2006.201.07:20:59.69#ibcon#*before return 0, iclass 38, count 2 2006.201.07:20:59.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:59.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:20:59.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.07:20:59.69#ibcon#ireg 7 cls_cnt 0 2006.201.07:20:59.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:59.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:59.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:59.81#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:20:59.81#ibcon#first serial, iclass 38, count 0 2006.201.07:20:59.81#ibcon#enter sib2, iclass 38, count 0 2006.201.07:20:59.81#ibcon#flushed, iclass 38, count 0 2006.201.07:20:59.81#ibcon#about to write, iclass 38, count 0 2006.201.07:20:59.81#ibcon#wrote, iclass 38, count 0 2006.201.07:20:59.81#ibcon#about to read 3, iclass 38, count 0 2006.201.07:20:59.83#ibcon#read 3, iclass 38, count 0 2006.201.07:20:59.83#ibcon#about to read 4, iclass 38, count 0 2006.201.07:20:59.83#ibcon#read 4, iclass 38, count 0 2006.201.07:20:59.83#ibcon#about to read 5, iclass 38, count 0 2006.201.07:20:59.83#ibcon#read 5, iclass 38, count 0 2006.201.07:20:59.83#ibcon#about to read 6, iclass 38, count 0 2006.201.07:20:59.83#ibcon#read 6, iclass 38, count 0 2006.201.07:20:59.83#ibcon#end of sib2, iclass 38, count 0 2006.201.07:20:59.83#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:20:59.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:20:59.83#ibcon#[27=USB\r\n] 2006.201.07:20:59.83#ibcon#*before write, iclass 38, count 0 2006.201.07:20:59.83#ibcon#enter sib2, iclass 38, count 0 2006.201.07:20:59.83#ibcon#flushed, iclass 38, count 0 2006.201.07:20:59.83#ibcon#about to write, iclass 38, count 0 2006.201.07:20:59.83#ibcon#wrote, iclass 38, count 0 2006.201.07:20:59.83#ibcon#about to read 3, iclass 38, count 0 2006.201.07:20:59.86#ibcon#read 3, iclass 38, count 0 2006.201.07:20:59.86#ibcon#about to read 4, iclass 38, count 0 2006.201.07:20:59.86#ibcon#read 4, iclass 38, count 0 2006.201.07:20:59.86#ibcon#about to read 5, iclass 38, count 0 2006.201.07:20:59.86#ibcon#read 5, iclass 38, count 0 2006.201.07:20:59.86#ibcon#about to read 6, iclass 38, count 0 2006.201.07:20:59.86#ibcon#read 6, iclass 38, count 0 2006.201.07:20:59.86#ibcon#end of sib2, iclass 38, count 0 2006.201.07:20:59.86#ibcon#*after write, iclass 38, count 0 2006.201.07:20:59.86#ibcon#*before return 0, iclass 38, count 0 2006.201.07:20:59.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:59.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:20:59.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:20:59.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:20:59.86$vck44/vblo=2,634.99 2006.201.07:20:59.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.07:20:59.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.07:20:59.86#ibcon#ireg 17 cls_cnt 0 2006.201.07:20:59.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:59.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:59.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:59.86#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:20:59.86#ibcon#first serial, iclass 40, count 0 2006.201.07:20:59.86#ibcon#enter sib2, iclass 40, count 0 2006.201.07:20:59.86#ibcon#flushed, iclass 40, count 0 2006.201.07:20:59.86#ibcon#about to write, iclass 40, count 0 2006.201.07:20:59.86#ibcon#wrote, iclass 40, count 0 2006.201.07:20:59.86#ibcon#about to read 3, iclass 40, count 0 2006.201.07:20:59.88#ibcon#read 3, iclass 40, count 0 2006.201.07:20:59.88#ibcon#about to read 4, iclass 40, count 0 2006.201.07:20:59.88#ibcon#read 4, iclass 40, count 0 2006.201.07:20:59.88#ibcon#about to read 5, iclass 40, count 0 2006.201.07:20:59.88#ibcon#read 5, iclass 40, count 0 2006.201.07:20:59.88#ibcon#about to read 6, iclass 40, count 0 2006.201.07:20:59.88#ibcon#read 6, iclass 40, count 0 2006.201.07:20:59.88#ibcon#end of sib2, iclass 40, count 0 2006.201.07:20:59.88#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:20:59.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:20:59.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:20:59.88#ibcon#*before write, iclass 40, count 0 2006.201.07:20:59.88#ibcon#enter sib2, iclass 40, count 0 2006.201.07:20:59.88#ibcon#flushed, iclass 40, count 0 2006.201.07:20:59.88#ibcon#about to write, iclass 40, count 0 2006.201.07:20:59.88#ibcon#wrote, iclass 40, count 0 2006.201.07:20:59.88#ibcon#about to read 3, iclass 40, count 0 2006.201.07:20:59.92#ibcon#read 3, iclass 40, count 0 2006.201.07:20:59.92#ibcon#about to read 4, iclass 40, count 0 2006.201.07:20:59.92#ibcon#read 4, iclass 40, count 0 2006.201.07:20:59.92#ibcon#about to read 5, iclass 40, count 0 2006.201.07:20:59.92#ibcon#read 5, iclass 40, count 0 2006.201.07:20:59.92#ibcon#about to read 6, iclass 40, count 0 2006.201.07:20:59.92#ibcon#read 6, iclass 40, count 0 2006.201.07:20:59.92#ibcon#end of sib2, iclass 40, count 0 2006.201.07:20:59.92#ibcon#*after write, iclass 40, count 0 2006.201.07:20:59.92#ibcon#*before return 0, iclass 40, count 0 2006.201.07:20:59.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:59.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:20:59.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:20:59.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:20:59.92$vck44/vb=2,5 2006.201.07:20:59.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.07:20:59.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.07:20:59.92#ibcon#ireg 11 cls_cnt 2 2006.201.07:20:59.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:20:59.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:20:59.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:20:59.98#ibcon#enter wrdev, iclass 4, count 2 2006.201.07:20:59.98#ibcon#first serial, iclass 4, count 2 2006.201.07:20:59.98#ibcon#enter sib2, iclass 4, count 2 2006.201.07:20:59.98#ibcon#flushed, iclass 4, count 2 2006.201.07:20:59.98#ibcon#about to write, iclass 4, count 2 2006.201.07:20:59.98#ibcon#wrote, iclass 4, count 2 2006.201.07:20:59.98#ibcon#about to read 3, iclass 4, count 2 2006.201.07:21:00.00#ibcon#read 3, iclass 4, count 2 2006.201.07:21:00.00#ibcon#about to read 4, iclass 4, count 2 2006.201.07:21:00.00#ibcon#read 4, iclass 4, count 2 2006.201.07:21:00.00#ibcon#about to read 5, iclass 4, count 2 2006.201.07:21:00.00#ibcon#read 5, iclass 4, count 2 2006.201.07:21:00.00#ibcon#about to read 6, iclass 4, count 2 2006.201.07:21:00.00#ibcon#read 6, iclass 4, count 2 2006.201.07:21:00.00#ibcon#end of sib2, iclass 4, count 2 2006.201.07:21:00.00#ibcon#*mode == 0, iclass 4, count 2 2006.201.07:21:00.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.07:21:00.00#ibcon#[27=AT02-05\r\n] 2006.201.07:21:00.00#ibcon#*before write, iclass 4, count 2 2006.201.07:21:00.00#ibcon#enter sib2, iclass 4, count 2 2006.201.07:21:00.00#ibcon#flushed, iclass 4, count 2 2006.201.07:21:00.00#ibcon#about to write, iclass 4, count 2 2006.201.07:21:00.00#ibcon#wrote, iclass 4, count 2 2006.201.07:21:00.00#ibcon#about to read 3, iclass 4, count 2 2006.201.07:21:00.03#ibcon#read 3, iclass 4, count 2 2006.201.07:21:00.03#ibcon#about to read 4, iclass 4, count 2 2006.201.07:21:00.03#ibcon#read 4, iclass 4, count 2 2006.201.07:21:00.03#ibcon#about to read 5, iclass 4, count 2 2006.201.07:21:00.03#ibcon#read 5, iclass 4, count 2 2006.201.07:21:00.03#ibcon#about to read 6, iclass 4, count 2 2006.201.07:21:00.03#ibcon#read 6, iclass 4, count 2 2006.201.07:21:00.03#ibcon#end of sib2, iclass 4, count 2 2006.201.07:21:00.03#ibcon#*after write, iclass 4, count 2 2006.201.07:21:00.03#ibcon#*before return 0, iclass 4, count 2 2006.201.07:21:00.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:21:00.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:21:00.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.07:21:00.03#ibcon#ireg 7 cls_cnt 0 2006.201.07:21:00.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:21:00.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:21:00.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:21:00.15#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:21:00.15#ibcon#first serial, iclass 4, count 0 2006.201.07:21:00.15#ibcon#enter sib2, iclass 4, count 0 2006.201.07:21:00.15#ibcon#flushed, iclass 4, count 0 2006.201.07:21:00.15#ibcon#about to write, iclass 4, count 0 2006.201.07:21:00.15#ibcon#wrote, iclass 4, count 0 2006.201.07:21:00.15#ibcon#about to read 3, iclass 4, count 0 2006.201.07:21:00.17#ibcon#read 3, iclass 4, count 0 2006.201.07:21:00.17#ibcon#about to read 4, iclass 4, count 0 2006.201.07:21:00.17#ibcon#read 4, iclass 4, count 0 2006.201.07:21:00.17#ibcon#about to read 5, iclass 4, count 0 2006.201.07:21:00.17#ibcon#read 5, iclass 4, count 0 2006.201.07:21:00.17#ibcon#about to read 6, iclass 4, count 0 2006.201.07:21:00.17#ibcon#read 6, iclass 4, count 0 2006.201.07:21:00.17#ibcon#end of sib2, iclass 4, count 0 2006.201.07:21:00.17#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:21:00.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:21:00.17#ibcon#[27=USB\r\n] 2006.201.07:21:00.17#ibcon#*before write, iclass 4, count 0 2006.201.07:21:00.17#ibcon#enter sib2, iclass 4, count 0 2006.201.07:21:00.17#ibcon#flushed, iclass 4, count 0 2006.201.07:21:00.17#ibcon#about to write, iclass 4, count 0 2006.201.07:21:00.17#ibcon#wrote, iclass 4, count 0 2006.201.07:21:00.17#ibcon#about to read 3, iclass 4, count 0 2006.201.07:21:00.20#ibcon#read 3, iclass 4, count 0 2006.201.07:21:00.20#ibcon#about to read 4, iclass 4, count 0 2006.201.07:21:00.20#ibcon#read 4, iclass 4, count 0 2006.201.07:21:00.20#ibcon#about to read 5, iclass 4, count 0 2006.201.07:21:00.20#ibcon#read 5, iclass 4, count 0 2006.201.07:21:00.20#ibcon#about to read 6, iclass 4, count 0 2006.201.07:21:00.20#ibcon#read 6, iclass 4, count 0 2006.201.07:21:00.20#ibcon#end of sib2, iclass 4, count 0 2006.201.07:21:00.20#ibcon#*after write, iclass 4, count 0 2006.201.07:21:00.20#ibcon#*before return 0, iclass 4, count 0 2006.201.07:21:00.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:21:00.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:21:00.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:21:00.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:21:00.20$vck44/vblo=3,649.99 2006.201.07:21:00.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.07:21:00.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.07:21:00.20#ibcon#ireg 17 cls_cnt 0 2006.201.07:21:00.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:21:00.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:21:00.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:21:00.20#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:21:00.20#ibcon#first serial, iclass 6, count 0 2006.201.07:21:00.20#ibcon#enter sib2, iclass 6, count 0 2006.201.07:21:00.20#ibcon#flushed, iclass 6, count 0 2006.201.07:21:00.20#ibcon#about to write, iclass 6, count 0 2006.201.07:21:00.20#ibcon#wrote, iclass 6, count 0 2006.201.07:21:00.20#ibcon#about to read 3, iclass 6, count 0 2006.201.07:21:00.22#ibcon#read 3, iclass 6, count 0 2006.201.07:21:00.22#ibcon#about to read 4, iclass 6, count 0 2006.201.07:21:00.22#ibcon#read 4, iclass 6, count 0 2006.201.07:21:00.22#ibcon#about to read 5, iclass 6, count 0 2006.201.07:21:00.22#ibcon#read 5, iclass 6, count 0 2006.201.07:21:00.22#ibcon#about to read 6, iclass 6, count 0 2006.201.07:21:00.22#ibcon#read 6, iclass 6, count 0 2006.201.07:21:00.22#ibcon#end of sib2, iclass 6, count 0 2006.201.07:21:00.22#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:21:00.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:21:00.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:21:00.22#ibcon#*before write, iclass 6, count 0 2006.201.07:21:00.22#ibcon#enter sib2, iclass 6, count 0 2006.201.07:21:00.22#ibcon#flushed, iclass 6, count 0 2006.201.07:21:00.22#ibcon#about to write, iclass 6, count 0 2006.201.07:21:00.22#ibcon#wrote, iclass 6, count 0 2006.201.07:21:00.22#ibcon#about to read 3, iclass 6, count 0 2006.201.07:21:00.26#ibcon#read 3, iclass 6, count 0 2006.201.07:21:00.26#ibcon#about to read 4, iclass 6, count 0 2006.201.07:21:00.26#ibcon#read 4, iclass 6, count 0 2006.201.07:21:00.26#ibcon#about to read 5, iclass 6, count 0 2006.201.07:21:00.26#ibcon#read 5, iclass 6, count 0 2006.201.07:21:00.26#ibcon#about to read 6, iclass 6, count 0 2006.201.07:21:00.26#ibcon#read 6, iclass 6, count 0 2006.201.07:21:00.26#ibcon#end of sib2, iclass 6, count 0 2006.201.07:21:00.26#ibcon#*after write, iclass 6, count 0 2006.201.07:21:00.26#ibcon#*before return 0, iclass 6, count 0 2006.201.07:21:00.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:21:00.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:21:00.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:21:00.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:21:00.26$vck44/vb=3,4 2006.201.07:21:00.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.07:21:00.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.07:21:00.26#ibcon#ireg 11 cls_cnt 2 2006.201.07:21:00.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:21:00.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:21:00.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:21:00.32#ibcon#enter wrdev, iclass 10, count 2 2006.201.07:21:00.32#ibcon#first serial, iclass 10, count 2 2006.201.07:21:00.32#ibcon#enter sib2, iclass 10, count 2 2006.201.07:21:00.32#ibcon#flushed, iclass 10, count 2 2006.201.07:21:00.32#ibcon#about to write, iclass 10, count 2 2006.201.07:21:00.32#ibcon#wrote, iclass 10, count 2 2006.201.07:21:00.32#ibcon#about to read 3, iclass 10, count 2 2006.201.07:21:00.34#ibcon#read 3, iclass 10, count 2 2006.201.07:21:00.34#ibcon#about to read 4, iclass 10, count 2 2006.201.07:21:00.34#ibcon#read 4, iclass 10, count 2 2006.201.07:21:00.34#ibcon#about to read 5, iclass 10, count 2 2006.201.07:21:00.34#ibcon#read 5, iclass 10, count 2 2006.201.07:21:00.34#ibcon#about to read 6, iclass 10, count 2 2006.201.07:21:00.34#ibcon#read 6, iclass 10, count 2 2006.201.07:21:00.34#ibcon#end of sib2, iclass 10, count 2 2006.201.07:21:00.34#ibcon#*mode == 0, iclass 10, count 2 2006.201.07:21:00.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.07:21:00.34#ibcon#[27=AT03-04\r\n] 2006.201.07:21:00.34#ibcon#*before write, iclass 10, count 2 2006.201.07:21:00.34#ibcon#enter sib2, iclass 10, count 2 2006.201.07:21:00.34#ibcon#flushed, iclass 10, count 2 2006.201.07:21:00.34#ibcon#about to write, iclass 10, count 2 2006.201.07:21:00.34#ibcon#wrote, iclass 10, count 2 2006.201.07:21:00.34#ibcon#about to read 3, iclass 10, count 2 2006.201.07:21:00.37#ibcon#read 3, iclass 10, count 2 2006.201.07:21:00.37#ibcon#about to read 4, iclass 10, count 2 2006.201.07:21:00.37#ibcon#read 4, iclass 10, count 2 2006.201.07:21:00.37#ibcon#about to read 5, iclass 10, count 2 2006.201.07:21:00.37#ibcon#read 5, iclass 10, count 2 2006.201.07:21:00.37#ibcon#about to read 6, iclass 10, count 2 2006.201.07:21:00.37#ibcon#read 6, iclass 10, count 2 2006.201.07:21:00.37#ibcon#end of sib2, iclass 10, count 2 2006.201.07:21:00.37#ibcon#*after write, iclass 10, count 2 2006.201.07:21:00.37#ibcon#*before return 0, iclass 10, count 2 2006.201.07:21:00.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:21:00.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:21:00.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.07:21:00.37#ibcon#ireg 7 cls_cnt 0 2006.201.07:21:00.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:21:00.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:21:00.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:21:00.49#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:21:00.49#ibcon#first serial, iclass 10, count 0 2006.201.07:21:00.49#ibcon#enter sib2, iclass 10, count 0 2006.201.07:21:00.49#ibcon#flushed, iclass 10, count 0 2006.201.07:21:00.49#ibcon#about to write, iclass 10, count 0 2006.201.07:21:00.49#ibcon#wrote, iclass 10, count 0 2006.201.07:21:00.49#ibcon#about to read 3, iclass 10, count 0 2006.201.07:21:00.51#ibcon#read 3, iclass 10, count 0 2006.201.07:21:00.51#ibcon#about to read 4, iclass 10, count 0 2006.201.07:21:00.51#ibcon#read 4, iclass 10, count 0 2006.201.07:21:00.51#ibcon#about to read 5, iclass 10, count 0 2006.201.07:21:00.51#ibcon#read 5, iclass 10, count 0 2006.201.07:21:00.51#ibcon#about to read 6, iclass 10, count 0 2006.201.07:21:00.51#ibcon#read 6, iclass 10, count 0 2006.201.07:21:00.51#ibcon#end of sib2, iclass 10, count 0 2006.201.07:21:00.51#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:21:00.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:21:00.51#ibcon#[27=USB\r\n] 2006.201.07:21:00.51#ibcon#*before write, iclass 10, count 0 2006.201.07:21:00.51#ibcon#enter sib2, iclass 10, count 0 2006.201.07:21:00.51#ibcon#flushed, iclass 10, count 0 2006.201.07:21:00.51#ibcon#about to write, iclass 10, count 0 2006.201.07:21:00.51#ibcon#wrote, iclass 10, count 0 2006.201.07:21:00.51#ibcon#about to read 3, iclass 10, count 0 2006.201.07:21:00.54#ibcon#read 3, iclass 10, count 0 2006.201.07:21:00.54#ibcon#about to read 4, iclass 10, count 0 2006.201.07:21:00.54#ibcon#read 4, iclass 10, count 0 2006.201.07:21:00.54#ibcon#about to read 5, iclass 10, count 0 2006.201.07:21:00.54#ibcon#read 5, iclass 10, count 0 2006.201.07:21:00.54#ibcon#about to read 6, iclass 10, count 0 2006.201.07:21:00.54#ibcon#read 6, iclass 10, count 0 2006.201.07:21:00.54#ibcon#end of sib2, iclass 10, count 0 2006.201.07:21:00.54#ibcon#*after write, iclass 10, count 0 2006.201.07:21:00.54#ibcon#*before return 0, iclass 10, count 0 2006.201.07:21:00.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:21:00.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:21:00.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:21:00.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:21:00.54$vck44/vblo=4,679.99 2006.201.07:21:00.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.07:21:00.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.07:21:00.54#ibcon#ireg 17 cls_cnt 0 2006.201.07:21:00.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:21:00.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:21:00.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:21:00.54#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:21:00.54#ibcon#first serial, iclass 12, count 0 2006.201.07:21:00.54#ibcon#enter sib2, iclass 12, count 0 2006.201.07:21:00.54#ibcon#flushed, iclass 12, count 0 2006.201.07:21:00.54#ibcon#about to write, iclass 12, count 0 2006.201.07:21:00.54#ibcon#wrote, iclass 12, count 0 2006.201.07:21:00.54#ibcon#about to read 3, iclass 12, count 0 2006.201.07:21:00.56#ibcon#read 3, iclass 12, count 0 2006.201.07:21:00.56#ibcon#about to read 4, iclass 12, count 0 2006.201.07:21:00.56#ibcon#read 4, iclass 12, count 0 2006.201.07:21:00.56#ibcon#about to read 5, iclass 12, count 0 2006.201.07:21:00.56#ibcon#read 5, iclass 12, count 0 2006.201.07:21:00.56#ibcon#about to read 6, iclass 12, count 0 2006.201.07:21:00.56#ibcon#read 6, iclass 12, count 0 2006.201.07:21:00.56#ibcon#end of sib2, iclass 12, count 0 2006.201.07:21:00.56#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:21:00.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:21:00.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:21:00.56#ibcon#*before write, iclass 12, count 0 2006.201.07:21:00.56#ibcon#enter sib2, iclass 12, count 0 2006.201.07:21:00.56#ibcon#flushed, iclass 12, count 0 2006.201.07:21:00.56#ibcon#about to write, iclass 12, count 0 2006.201.07:21:00.56#ibcon#wrote, iclass 12, count 0 2006.201.07:21:00.56#ibcon#about to read 3, iclass 12, count 0 2006.201.07:21:00.60#ibcon#read 3, iclass 12, count 0 2006.201.07:21:00.60#ibcon#about to read 4, iclass 12, count 0 2006.201.07:21:00.60#ibcon#read 4, iclass 12, count 0 2006.201.07:21:00.60#ibcon#about to read 5, iclass 12, count 0 2006.201.07:21:00.60#ibcon#read 5, iclass 12, count 0 2006.201.07:21:00.60#ibcon#about to read 6, iclass 12, count 0 2006.201.07:21:00.60#ibcon#read 6, iclass 12, count 0 2006.201.07:21:00.60#ibcon#end of sib2, iclass 12, count 0 2006.201.07:21:00.60#ibcon#*after write, iclass 12, count 0 2006.201.07:21:00.60#ibcon#*before return 0, iclass 12, count 0 2006.201.07:21:00.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:21:00.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:21:00.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:21:00.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:21:00.60$vck44/vb=4,5 2006.201.07:21:00.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.07:21:00.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.07:21:00.60#ibcon#ireg 11 cls_cnt 2 2006.201.07:21:00.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:21:00.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:21:00.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:21:00.66#ibcon#enter wrdev, iclass 14, count 2 2006.201.07:21:00.66#ibcon#first serial, iclass 14, count 2 2006.201.07:21:00.66#ibcon#enter sib2, iclass 14, count 2 2006.201.07:21:00.66#ibcon#flushed, iclass 14, count 2 2006.201.07:21:00.66#ibcon#about to write, iclass 14, count 2 2006.201.07:21:00.66#ibcon#wrote, iclass 14, count 2 2006.201.07:21:00.66#ibcon#about to read 3, iclass 14, count 2 2006.201.07:21:00.68#ibcon#read 3, iclass 14, count 2 2006.201.07:21:00.68#ibcon#about to read 4, iclass 14, count 2 2006.201.07:21:00.68#ibcon#read 4, iclass 14, count 2 2006.201.07:21:00.68#ibcon#about to read 5, iclass 14, count 2 2006.201.07:21:00.68#ibcon#read 5, iclass 14, count 2 2006.201.07:21:00.68#ibcon#about to read 6, iclass 14, count 2 2006.201.07:21:00.68#ibcon#read 6, iclass 14, count 2 2006.201.07:21:00.68#ibcon#end of sib2, iclass 14, count 2 2006.201.07:21:00.68#ibcon#*mode == 0, iclass 14, count 2 2006.201.07:21:00.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.07:21:00.68#ibcon#[27=AT04-05\r\n] 2006.201.07:21:00.68#ibcon#*before write, iclass 14, count 2 2006.201.07:21:00.68#ibcon#enter sib2, iclass 14, count 2 2006.201.07:21:00.68#ibcon#flushed, iclass 14, count 2 2006.201.07:21:00.68#ibcon#about to write, iclass 14, count 2 2006.201.07:21:00.68#ibcon#wrote, iclass 14, count 2 2006.201.07:21:00.68#ibcon#about to read 3, iclass 14, count 2 2006.201.07:21:00.71#ibcon#read 3, iclass 14, count 2 2006.201.07:21:00.71#ibcon#about to read 4, iclass 14, count 2 2006.201.07:21:00.71#ibcon#read 4, iclass 14, count 2 2006.201.07:21:00.71#ibcon#about to read 5, iclass 14, count 2 2006.201.07:21:00.71#ibcon#read 5, iclass 14, count 2 2006.201.07:21:00.71#ibcon#about to read 6, iclass 14, count 2 2006.201.07:21:00.71#ibcon#read 6, iclass 14, count 2 2006.201.07:21:00.71#ibcon#end of sib2, iclass 14, count 2 2006.201.07:21:00.71#ibcon#*after write, iclass 14, count 2 2006.201.07:21:00.71#ibcon#*before return 0, iclass 14, count 2 2006.201.07:21:00.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:21:00.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:21:00.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.07:21:00.71#ibcon#ireg 7 cls_cnt 0 2006.201.07:21:00.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:21:00.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:21:00.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:21:00.83#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:21:00.83#ibcon#first serial, iclass 14, count 0 2006.201.07:21:00.83#ibcon#enter sib2, iclass 14, count 0 2006.201.07:21:00.83#ibcon#flushed, iclass 14, count 0 2006.201.07:21:00.83#ibcon#about to write, iclass 14, count 0 2006.201.07:21:00.83#ibcon#wrote, iclass 14, count 0 2006.201.07:21:00.83#ibcon#about to read 3, iclass 14, count 0 2006.201.07:21:00.85#ibcon#read 3, iclass 14, count 0 2006.201.07:21:00.85#ibcon#about to read 4, iclass 14, count 0 2006.201.07:21:00.85#ibcon#read 4, iclass 14, count 0 2006.201.07:21:00.85#ibcon#about to read 5, iclass 14, count 0 2006.201.07:21:00.85#ibcon#read 5, iclass 14, count 0 2006.201.07:21:00.85#ibcon#about to read 6, iclass 14, count 0 2006.201.07:21:00.85#ibcon#read 6, iclass 14, count 0 2006.201.07:21:00.85#ibcon#end of sib2, iclass 14, count 0 2006.201.07:21:00.85#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:21:00.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:21:00.85#ibcon#[27=USB\r\n] 2006.201.07:21:00.85#ibcon#*before write, iclass 14, count 0 2006.201.07:21:00.85#ibcon#enter sib2, iclass 14, count 0 2006.201.07:21:00.85#ibcon#flushed, iclass 14, count 0 2006.201.07:21:00.85#ibcon#about to write, iclass 14, count 0 2006.201.07:21:00.85#ibcon#wrote, iclass 14, count 0 2006.201.07:21:00.85#ibcon#about to read 3, iclass 14, count 0 2006.201.07:21:00.88#ibcon#read 3, iclass 14, count 0 2006.201.07:21:00.88#ibcon#about to read 4, iclass 14, count 0 2006.201.07:21:00.88#ibcon#read 4, iclass 14, count 0 2006.201.07:21:00.88#ibcon#about to read 5, iclass 14, count 0 2006.201.07:21:00.88#ibcon#read 5, iclass 14, count 0 2006.201.07:21:00.88#ibcon#about to read 6, iclass 14, count 0 2006.201.07:21:00.88#ibcon#read 6, iclass 14, count 0 2006.201.07:21:00.88#ibcon#end of sib2, iclass 14, count 0 2006.201.07:21:00.88#ibcon#*after write, iclass 14, count 0 2006.201.07:21:00.88#ibcon#*before return 0, iclass 14, count 0 2006.201.07:21:00.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:21:00.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:21:00.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:21:00.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:21:00.88$vck44/vblo=5,709.99 2006.201.07:21:00.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.07:21:00.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.07:21:00.88#ibcon#ireg 17 cls_cnt 0 2006.201.07:21:00.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:21:00.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:21:00.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:21:00.88#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:21:00.88#ibcon#first serial, iclass 16, count 0 2006.201.07:21:00.88#ibcon#enter sib2, iclass 16, count 0 2006.201.07:21:00.88#ibcon#flushed, iclass 16, count 0 2006.201.07:21:00.88#ibcon#about to write, iclass 16, count 0 2006.201.07:21:00.88#ibcon#wrote, iclass 16, count 0 2006.201.07:21:00.88#ibcon#about to read 3, iclass 16, count 0 2006.201.07:21:00.90#ibcon#read 3, iclass 16, count 0 2006.201.07:21:00.90#ibcon#about to read 4, iclass 16, count 0 2006.201.07:21:00.90#ibcon#read 4, iclass 16, count 0 2006.201.07:21:00.90#ibcon#about to read 5, iclass 16, count 0 2006.201.07:21:00.90#ibcon#read 5, iclass 16, count 0 2006.201.07:21:00.90#ibcon#about to read 6, iclass 16, count 0 2006.201.07:21:00.90#ibcon#read 6, iclass 16, count 0 2006.201.07:21:00.90#ibcon#end of sib2, iclass 16, count 0 2006.201.07:21:00.90#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:21:00.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:21:00.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:21:00.90#ibcon#*before write, iclass 16, count 0 2006.201.07:21:00.90#ibcon#enter sib2, iclass 16, count 0 2006.201.07:21:00.90#ibcon#flushed, iclass 16, count 0 2006.201.07:21:00.90#ibcon#about to write, iclass 16, count 0 2006.201.07:21:00.90#ibcon#wrote, iclass 16, count 0 2006.201.07:21:00.90#ibcon#about to read 3, iclass 16, count 0 2006.201.07:21:00.95#ibcon#read 3, iclass 16, count 0 2006.201.07:21:00.95#ibcon#about to read 4, iclass 16, count 0 2006.201.07:21:00.95#ibcon#read 4, iclass 16, count 0 2006.201.07:21:00.95#ibcon#about to read 5, iclass 16, count 0 2006.201.07:21:00.95#ibcon#read 5, iclass 16, count 0 2006.201.07:21:00.95#ibcon#about to read 6, iclass 16, count 0 2006.201.07:21:00.95#ibcon#read 6, iclass 16, count 0 2006.201.07:21:00.95#ibcon#end of sib2, iclass 16, count 0 2006.201.07:21:00.95#ibcon#*after write, iclass 16, count 0 2006.201.07:21:00.95#ibcon#*before return 0, iclass 16, count 0 2006.201.07:21:00.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:21:00.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:21:00.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:21:00.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:21:00.95$vck44/vb=5,4 2006.201.07:21:00.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.07:21:00.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.07:21:00.95#ibcon#ireg 11 cls_cnt 2 2006.201.07:21:00.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:21:01.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:21:01.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:21:01.00#ibcon#enter wrdev, iclass 18, count 2 2006.201.07:21:01.00#ibcon#first serial, iclass 18, count 2 2006.201.07:21:01.00#ibcon#enter sib2, iclass 18, count 2 2006.201.07:21:01.00#ibcon#flushed, iclass 18, count 2 2006.201.07:21:01.00#ibcon#about to write, iclass 18, count 2 2006.201.07:21:01.00#ibcon#wrote, iclass 18, count 2 2006.201.07:21:01.00#ibcon#about to read 3, iclass 18, count 2 2006.201.07:21:01.02#ibcon#read 3, iclass 18, count 2 2006.201.07:21:01.02#ibcon#about to read 4, iclass 18, count 2 2006.201.07:21:01.02#ibcon#read 4, iclass 18, count 2 2006.201.07:21:01.02#ibcon#about to read 5, iclass 18, count 2 2006.201.07:21:01.02#ibcon#read 5, iclass 18, count 2 2006.201.07:21:01.02#ibcon#about to read 6, iclass 18, count 2 2006.201.07:21:01.02#ibcon#read 6, iclass 18, count 2 2006.201.07:21:01.02#ibcon#end of sib2, iclass 18, count 2 2006.201.07:21:01.02#ibcon#*mode == 0, iclass 18, count 2 2006.201.07:21:01.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.07:21:01.02#ibcon#[27=AT05-04\r\n] 2006.201.07:21:01.02#ibcon#*before write, iclass 18, count 2 2006.201.07:21:01.02#ibcon#enter sib2, iclass 18, count 2 2006.201.07:21:01.02#ibcon#flushed, iclass 18, count 2 2006.201.07:21:01.02#ibcon#about to write, iclass 18, count 2 2006.201.07:21:01.02#ibcon#wrote, iclass 18, count 2 2006.201.07:21:01.02#ibcon#about to read 3, iclass 18, count 2 2006.201.07:21:01.05#ibcon#read 3, iclass 18, count 2 2006.201.07:21:01.05#ibcon#about to read 4, iclass 18, count 2 2006.201.07:21:01.05#ibcon#read 4, iclass 18, count 2 2006.201.07:21:01.05#ibcon#about to read 5, iclass 18, count 2 2006.201.07:21:01.05#ibcon#read 5, iclass 18, count 2 2006.201.07:21:01.05#ibcon#about to read 6, iclass 18, count 2 2006.201.07:21:01.05#ibcon#read 6, iclass 18, count 2 2006.201.07:21:01.05#ibcon#end of sib2, iclass 18, count 2 2006.201.07:21:01.05#ibcon#*after write, iclass 18, count 2 2006.201.07:21:01.05#ibcon#*before return 0, iclass 18, count 2 2006.201.07:21:01.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:21:01.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:21:01.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.07:21:01.05#ibcon#ireg 7 cls_cnt 0 2006.201.07:21:01.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:21:01.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:21:01.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:21:01.17#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:21:01.17#ibcon#first serial, iclass 18, count 0 2006.201.07:21:01.17#ibcon#enter sib2, iclass 18, count 0 2006.201.07:21:01.17#ibcon#flushed, iclass 18, count 0 2006.201.07:21:01.17#ibcon#about to write, iclass 18, count 0 2006.201.07:21:01.17#ibcon#wrote, iclass 18, count 0 2006.201.07:21:01.17#ibcon#about to read 3, iclass 18, count 0 2006.201.07:21:01.19#ibcon#read 3, iclass 18, count 0 2006.201.07:21:01.19#ibcon#about to read 4, iclass 18, count 0 2006.201.07:21:01.19#ibcon#read 4, iclass 18, count 0 2006.201.07:21:01.19#ibcon#about to read 5, iclass 18, count 0 2006.201.07:21:01.19#ibcon#read 5, iclass 18, count 0 2006.201.07:21:01.19#ibcon#about to read 6, iclass 18, count 0 2006.201.07:21:01.19#ibcon#read 6, iclass 18, count 0 2006.201.07:21:01.19#ibcon#end of sib2, iclass 18, count 0 2006.201.07:21:01.19#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:21:01.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:21:01.19#ibcon#[27=USB\r\n] 2006.201.07:21:01.19#ibcon#*before write, iclass 18, count 0 2006.201.07:21:01.19#ibcon#enter sib2, iclass 18, count 0 2006.201.07:21:01.19#ibcon#flushed, iclass 18, count 0 2006.201.07:21:01.19#ibcon#about to write, iclass 18, count 0 2006.201.07:21:01.19#ibcon#wrote, iclass 18, count 0 2006.201.07:21:01.19#ibcon#about to read 3, iclass 18, count 0 2006.201.07:21:01.22#ibcon#read 3, iclass 18, count 0 2006.201.07:21:01.22#ibcon#about to read 4, iclass 18, count 0 2006.201.07:21:01.22#ibcon#read 4, iclass 18, count 0 2006.201.07:21:01.22#ibcon#about to read 5, iclass 18, count 0 2006.201.07:21:01.22#ibcon#read 5, iclass 18, count 0 2006.201.07:21:01.22#ibcon#about to read 6, iclass 18, count 0 2006.201.07:21:01.22#ibcon#read 6, iclass 18, count 0 2006.201.07:21:01.22#ibcon#end of sib2, iclass 18, count 0 2006.201.07:21:01.22#ibcon#*after write, iclass 18, count 0 2006.201.07:21:01.22#ibcon#*before return 0, iclass 18, count 0 2006.201.07:21:01.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:21:01.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:21:01.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:21:01.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:21:01.22$vck44/vblo=6,719.99 2006.201.07:21:01.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.07:21:01.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.07:21:01.22#ibcon#ireg 17 cls_cnt 0 2006.201.07:21:01.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:21:01.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:21:01.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:21:01.22#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:21:01.22#ibcon#first serial, iclass 20, count 0 2006.201.07:21:01.22#ibcon#enter sib2, iclass 20, count 0 2006.201.07:21:01.22#ibcon#flushed, iclass 20, count 0 2006.201.07:21:01.22#ibcon#about to write, iclass 20, count 0 2006.201.07:21:01.22#ibcon#wrote, iclass 20, count 0 2006.201.07:21:01.22#ibcon#about to read 3, iclass 20, count 0 2006.201.07:21:01.24#ibcon#read 3, iclass 20, count 0 2006.201.07:21:01.24#ibcon#about to read 4, iclass 20, count 0 2006.201.07:21:01.24#ibcon#read 4, iclass 20, count 0 2006.201.07:21:01.24#ibcon#about to read 5, iclass 20, count 0 2006.201.07:21:01.24#ibcon#read 5, iclass 20, count 0 2006.201.07:21:01.24#ibcon#about to read 6, iclass 20, count 0 2006.201.07:21:01.24#ibcon#read 6, iclass 20, count 0 2006.201.07:21:01.24#ibcon#end of sib2, iclass 20, count 0 2006.201.07:21:01.24#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:21:01.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:21:01.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:21:01.24#ibcon#*before write, iclass 20, count 0 2006.201.07:21:01.24#ibcon#enter sib2, iclass 20, count 0 2006.201.07:21:01.24#ibcon#flushed, iclass 20, count 0 2006.201.07:21:01.24#ibcon#about to write, iclass 20, count 0 2006.201.07:21:01.24#ibcon#wrote, iclass 20, count 0 2006.201.07:21:01.24#ibcon#about to read 3, iclass 20, count 0 2006.201.07:21:01.28#ibcon#read 3, iclass 20, count 0 2006.201.07:21:01.28#ibcon#about to read 4, iclass 20, count 0 2006.201.07:21:01.28#ibcon#read 4, iclass 20, count 0 2006.201.07:21:01.28#ibcon#about to read 5, iclass 20, count 0 2006.201.07:21:01.28#ibcon#read 5, iclass 20, count 0 2006.201.07:21:01.28#ibcon#about to read 6, iclass 20, count 0 2006.201.07:21:01.28#ibcon#read 6, iclass 20, count 0 2006.201.07:21:01.28#ibcon#end of sib2, iclass 20, count 0 2006.201.07:21:01.28#ibcon#*after write, iclass 20, count 0 2006.201.07:21:01.28#ibcon#*before return 0, iclass 20, count 0 2006.201.07:21:01.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:21:01.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:21:01.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:21:01.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:21:01.28$vck44/vb=6,4 2006.201.07:21:01.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.07:21:01.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.07:21:01.28#ibcon#ireg 11 cls_cnt 2 2006.201.07:21:01.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:21:01.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:21:01.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:21:01.34#ibcon#enter wrdev, iclass 22, count 2 2006.201.07:21:01.34#ibcon#first serial, iclass 22, count 2 2006.201.07:21:01.34#ibcon#enter sib2, iclass 22, count 2 2006.201.07:21:01.34#ibcon#flushed, iclass 22, count 2 2006.201.07:21:01.34#ibcon#about to write, iclass 22, count 2 2006.201.07:21:01.34#ibcon#wrote, iclass 22, count 2 2006.201.07:21:01.34#ibcon#about to read 3, iclass 22, count 2 2006.201.07:21:01.36#ibcon#read 3, iclass 22, count 2 2006.201.07:21:01.36#ibcon#about to read 4, iclass 22, count 2 2006.201.07:21:01.36#ibcon#read 4, iclass 22, count 2 2006.201.07:21:01.36#ibcon#about to read 5, iclass 22, count 2 2006.201.07:21:01.36#ibcon#read 5, iclass 22, count 2 2006.201.07:21:01.36#ibcon#about to read 6, iclass 22, count 2 2006.201.07:21:01.36#ibcon#read 6, iclass 22, count 2 2006.201.07:21:01.36#ibcon#end of sib2, iclass 22, count 2 2006.201.07:21:01.36#ibcon#*mode == 0, iclass 22, count 2 2006.201.07:21:01.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.07:21:01.36#ibcon#[27=AT06-04\r\n] 2006.201.07:21:01.36#ibcon#*before write, iclass 22, count 2 2006.201.07:21:01.36#ibcon#enter sib2, iclass 22, count 2 2006.201.07:21:01.36#ibcon#flushed, iclass 22, count 2 2006.201.07:21:01.36#ibcon#about to write, iclass 22, count 2 2006.201.07:21:01.36#ibcon#wrote, iclass 22, count 2 2006.201.07:21:01.36#ibcon#about to read 3, iclass 22, count 2 2006.201.07:21:01.39#ibcon#read 3, iclass 22, count 2 2006.201.07:21:01.39#ibcon#about to read 4, iclass 22, count 2 2006.201.07:21:01.39#ibcon#read 4, iclass 22, count 2 2006.201.07:21:01.39#ibcon#about to read 5, iclass 22, count 2 2006.201.07:21:01.39#ibcon#read 5, iclass 22, count 2 2006.201.07:21:01.39#ibcon#about to read 6, iclass 22, count 2 2006.201.07:21:01.39#ibcon#read 6, iclass 22, count 2 2006.201.07:21:01.39#ibcon#end of sib2, iclass 22, count 2 2006.201.07:21:01.39#ibcon#*after write, iclass 22, count 2 2006.201.07:21:01.39#ibcon#*before return 0, iclass 22, count 2 2006.201.07:21:01.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:21:01.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:21:01.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.07:21:01.39#ibcon#ireg 7 cls_cnt 0 2006.201.07:21:01.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:21:01.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:21:01.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:21:01.51#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:21:01.51#ibcon#first serial, iclass 22, count 0 2006.201.07:21:01.51#ibcon#enter sib2, iclass 22, count 0 2006.201.07:21:01.51#ibcon#flushed, iclass 22, count 0 2006.201.07:21:01.51#ibcon#about to write, iclass 22, count 0 2006.201.07:21:01.51#ibcon#wrote, iclass 22, count 0 2006.201.07:21:01.51#ibcon#about to read 3, iclass 22, count 0 2006.201.07:21:01.53#ibcon#read 3, iclass 22, count 0 2006.201.07:21:01.53#ibcon#about to read 4, iclass 22, count 0 2006.201.07:21:01.53#ibcon#read 4, iclass 22, count 0 2006.201.07:21:01.53#ibcon#about to read 5, iclass 22, count 0 2006.201.07:21:01.53#ibcon#read 5, iclass 22, count 0 2006.201.07:21:01.53#ibcon#about to read 6, iclass 22, count 0 2006.201.07:21:01.53#ibcon#read 6, iclass 22, count 0 2006.201.07:21:01.53#ibcon#end of sib2, iclass 22, count 0 2006.201.07:21:01.53#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:21:01.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:21:01.53#ibcon#[27=USB\r\n] 2006.201.07:21:01.53#ibcon#*before write, iclass 22, count 0 2006.201.07:21:01.53#ibcon#enter sib2, iclass 22, count 0 2006.201.07:21:01.53#ibcon#flushed, iclass 22, count 0 2006.201.07:21:01.53#ibcon#about to write, iclass 22, count 0 2006.201.07:21:01.53#ibcon#wrote, iclass 22, count 0 2006.201.07:21:01.53#ibcon#about to read 3, iclass 22, count 0 2006.201.07:21:01.56#ibcon#read 3, iclass 22, count 0 2006.201.07:21:01.56#ibcon#about to read 4, iclass 22, count 0 2006.201.07:21:01.56#ibcon#read 4, iclass 22, count 0 2006.201.07:21:01.56#ibcon#about to read 5, iclass 22, count 0 2006.201.07:21:01.56#ibcon#read 5, iclass 22, count 0 2006.201.07:21:01.56#ibcon#about to read 6, iclass 22, count 0 2006.201.07:21:01.56#ibcon#read 6, iclass 22, count 0 2006.201.07:21:01.56#ibcon#end of sib2, iclass 22, count 0 2006.201.07:21:01.56#ibcon#*after write, iclass 22, count 0 2006.201.07:21:01.56#ibcon#*before return 0, iclass 22, count 0 2006.201.07:21:01.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:21:01.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:21:01.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:21:01.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:21:01.56$vck44/vblo=7,734.99 2006.201.07:21:01.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.07:21:01.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.07:21:01.56#ibcon#ireg 17 cls_cnt 0 2006.201.07:21:01.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:21:01.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:21:01.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:21:01.56#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:21:01.56#ibcon#first serial, iclass 24, count 0 2006.201.07:21:01.56#ibcon#enter sib2, iclass 24, count 0 2006.201.07:21:01.56#ibcon#flushed, iclass 24, count 0 2006.201.07:21:01.56#ibcon#about to write, iclass 24, count 0 2006.201.07:21:01.56#ibcon#wrote, iclass 24, count 0 2006.201.07:21:01.56#ibcon#about to read 3, iclass 24, count 0 2006.201.07:21:01.58#ibcon#read 3, iclass 24, count 0 2006.201.07:21:01.58#ibcon#about to read 4, iclass 24, count 0 2006.201.07:21:01.58#ibcon#read 4, iclass 24, count 0 2006.201.07:21:01.58#ibcon#about to read 5, iclass 24, count 0 2006.201.07:21:01.58#ibcon#read 5, iclass 24, count 0 2006.201.07:21:01.58#ibcon#about to read 6, iclass 24, count 0 2006.201.07:21:01.58#ibcon#read 6, iclass 24, count 0 2006.201.07:21:01.58#ibcon#end of sib2, iclass 24, count 0 2006.201.07:21:01.58#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:21:01.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:21:01.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:21:01.58#ibcon#*before write, iclass 24, count 0 2006.201.07:21:01.58#ibcon#enter sib2, iclass 24, count 0 2006.201.07:21:01.58#ibcon#flushed, iclass 24, count 0 2006.201.07:21:01.58#ibcon#about to write, iclass 24, count 0 2006.201.07:21:01.58#ibcon#wrote, iclass 24, count 0 2006.201.07:21:01.58#ibcon#about to read 3, iclass 24, count 0 2006.201.07:21:01.62#ibcon#read 3, iclass 24, count 0 2006.201.07:21:01.62#ibcon#about to read 4, iclass 24, count 0 2006.201.07:21:01.62#ibcon#read 4, iclass 24, count 0 2006.201.07:21:01.62#ibcon#about to read 5, iclass 24, count 0 2006.201.07:21:01.62#ibcon#read 5, iclass 24, count 0 2006.201.07:21:01.62#ibcon#about to read 6, iclass 24, count 0 2006.201.07:21:01.62#ibcon#read 6, iclass 24, count 0 2006.201.07:21:01.62#ibcon#end of sib2, iclass 24, count 0 2006.201.07:21:01.62#ibcon#*after write, iclass 24, count 0 2006.201.07:21:01.62#ibcon#*before return 0, iclass 24, count 0 2006.201.07:21:01.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:21:01.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:21:01.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:21:01.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:21:01.62$vck44/vb=7,4 2006.201.07:21:01.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.07:21:01.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.07:21:01.62#ibcon#ireg 11 cls_cnt 2 2006.201.07:21:01.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:21:01.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:21:01.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:21:01.68#ibcon#enter wrdev, iclass 26, count 2 2006.201.07:21:01.68#ibcon#first serial, iclass 26, count 2 2006.201.07:21:01.68#ibcon#enter sib2, iclass 26, count 2 2006.201.07:21:01.68#ibcon#flushed, iclass 26, count 2 2006.201.07:21:01.68#ibcon#about to write, iclass 26, count 2 2006.201.07:21:01.68#ibcon#wrote, iclass 26, count 2 2006.201.07:21:01.68#ibcon#about to read 3, iclass 26, count 2 2006.201.07:21:01.70#ibcon#read 3, iclass 26, count 2 2006.201.07:21:01.70#ibcon#about to read 4, iclass 26, count 2 2006.201.07:21:01.70#ibcon#read 4, iclass 26, count 2 2006.201.07:21:01.70#ibcon#about to read 5, iclass 26, count 2 2006.201.07:21:01.70#ibcon#read 5, iclass 26, count 2 2006.201.07:21:01.70#ibcon#about to read 6, iclass 26, count 2 2006.201.07:21:01.70#ibcon#read 6, iclass 26, count 2 2006.201.07:21:01.70#ibcon#end of sib2, iclass 26, count 2 2006.201.07:21:01.70#ibcon#*mode == 0, iclass 26, count 2 2006.201.07:21:01.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.07:21:01.70#ibcon#[27=AT07-04\r\n] 2006.201.07:21:01.70#ibcon#*before write, iclass 26, count 2 2006.201.07:21:01.70#ibcon#enter sib2, iclass 26, count 2 2006.201.07:21:01.70#ibcon#flushed, iclass 26, count 2 2006.201.07:21:01.70#ibcon#about to write, iclass 26, count 2 2006.201.07:21:01.70#ibcon#wrote, iclass 26, count 2 2006.201.07:21:01.70#ibcon#about to read 3, iclass 26, count 2 2006.201.07:21:01.73#ibcon#read 3, iclass 26, count 2 2006.201.07:21:01.73#ibcon#about to read 4, iclass 26, count 2 2006.201.07:21:01.73#ibcon#read 4, iclass 26, count 2 2006.201.07:21:01.73#ibcon#about to read 5, iclass 26, count 2 2006.201.07:21:01.73#ibcon#read 5, iclass 26, count 2 2006.201.07:21:01.73#ibcon#about to read 6, iclass 26, count 2 2006.201.07:21:01.73#ibcon#read 6, iclass 26, count 2 2006.201.07:21:01.73#ibcon#end of sib2, iclass 26, count 2 2006.201.07:21:01.73#ibcon#*after write, iclass 26, count 2 2006.201.07:21:01.73#ibcon#*before return 0, iclass 26, count 2 2006.201.07:21:01.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:21:01.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:21:01.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.07:21:01.73#ibcon#ireg 7 cls_cnt 0 2006.201.07:21:01.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:21:01.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:21:01.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:21:01.85#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:21:01.85#ibcon#first serial, iclass 26, count 0 2006.201.07:21:01.85#ibcon#enter sib2, iclass 26, count 0 2006.201.07:21:01.85#ibcon#flushed, iclass 26, count 0 2006.201.07:21:01.85#ibcon#about to write, iclass 26, count 0 2006.201.07:21:01.85#ibcon#wrote, iclass 26, count 0 2006.201.07:21:01.85#ibcon#about to read 3, iclass 26, count 0 2006.201.07:21:01.87#ibcon#read 3, iclass 26, count 0 2006.201.07:21:01.87#ibcon#about to read 4, iclass 26, count 0 2006.201.07:21:01.87#ibcon#read 4, iclass 26, count 0 2006.201.07:21:01.87#ibcon#about to read 5, iclass 26, count 0 2006.201.07:21:01.87#ibcon#read 5, iclass 26, count 0 2006.201.07:21:01.87#ibcon#about to read 6, iclass 26, count 0 2006.201.07:21:01.87#ibcon#read 6, iclass 26, count 0 2006.201.07:21:01.87#ibcon#end of sib2, iclass 26, count 0 2006.201.07:21:01.87#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:21:01.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:21:01.87#ibcon#[27=USB\r\n] 2006.201.07:21:01.87#ibcon#*before write, iclass 26, count 0 2006.201.07:21:01.87#ibcon#enter sib2, iclass 26, count 0 2006.201.07:21:01.87#ibcon#flushed, iclass 26, count 0 2006.201.07:21:01.87#ibcon#about to write, iclass 26, count 0 2006.201.07:21:01.87#ibcon#wrote, iclass 26, count 0 2006.201.07:21:01.87#ibcon#about to read 3, iclass 26, count 0 2006.201.07:21:01.90#ibcon#read 3, iclass 26, count 0 2006.201.07:21:01.90#ibcon#about to read 4, iclass 26, count 0 2006.201.07:21:01.90#ibcon#read 4, iclass 26, count 0 2006.201.07:21:01.90#ibcon#about to read 5, iclass 26, count 0 2006.201.07:21:01.90#ibcon#read 5, iclass 26, count 0 2006.201.07:21:01.90#ibcon#about to read 6, iclass 26, count 0 2006.201.07:21:01.90#ibcon#read 6, iclass 26, count 0 2006.201.07:21:01.90#ibcon#end of sib2, iclass 26, count 0 2006.201.07:21:01.90#ibcon#*after write, iclass 26, count 0 2006.201.07:21:01.90#ibcon#*before return 0, iclass 26, count 0 2006.201.07:21:01.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:21:01.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:21:01.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:21:01.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:21:01.90$vck44/vblo=8,744.99 2006.201.07:21:01.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.07:21:01.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.07:21:01.90#ibcon#ireg 17 cls_cnt 0 2006.201.07:21:01.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:21:01.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:21:01.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:21:01.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:21:01.90#ibcon#first serial, iclass 28, count 0 2006.201.07:21:01.90#ibcon#enter sib2, iclass 28, count 0 2006.201.07:21:01.90#ibcon#flushed, iclass 28, count 0 2006.201.07:21:01.90#ibcon#about to write, iclass 28, count 0 2006.201.07:21:01.90#ibcon#wrote, iclass 28, count 0 2006.201.07:21:01.90#ibcon#about to read 3, iclass 28, count 0 2006.201.07:21:01.92#ibcon#read 3, iclass 28, count 0 2006.201.07:21:01.92#ibcon#about to read 4, iclass 28, count 0 2006.201.07:21:01.92#ibcon#read 4, iclass 28, count 0 2006.201.07:21:01.92#ibcon#about to read 5, iclass 28, count 0 2006.201.07:21:01.92#ibcon#read 5, iclass 28, count 0 2006.201.07:21:01.92#ibcon#about to read 6, iclass 28, count 0 2006.201.07:21:01.92#ibcon#read 6, iclass 28, count 0 2006.201.07:21:01.92#ibcon#end of sib2, iclass 28, count 0 2006.201.07:21:01.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:21:01.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:21:01.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:21:01.92#ibcon#*before write, iclass 28, count 0 2006.201.07:21:01.92#ibcon#enter sib2, iclass 28, count 0 2006.201.07:21:01.92#ibcon#flushed, iclass 28, count 0 2006.201.07:21:01.92#ibcon#about to write, iclass 28, count 0 2006.201.07:21:01.92#ibcon#wrote, iclass 28, count 0 2006.201.07:21:01.92#ibcon#about to read 3, iclass 28, count 0 2006.201.07:21:01.96#ibcon#read 3, iclass 28, count 0 2006.201.07:21:01.96#ibcon#about to read 4, iclass 28, count 0 2006.201.07:21:01.96#ibcon#read 4, iclass 28, count 0 2006.201.07:21:01.96#ibcon#about to read 5, iclass 28, count 0 2006.201.07:21:01.96#ibcon#read 5, iclass 28, count 0 2006.201.07:21:01.96#ibcon#about to read 6, iclass 28, count 0 2006.201.07:21:01.96#ibcon#read 6, iclass 28, count 0 2006.201.07:21:01.96#ibcon#end of sib2, iclass 28, count 0 2006.201.07:21:01.96#ibcon#*after write, iclass 28, count 0 2006.201.07:21:01.96#ibcon#*before return 0, iclass 28, count 0 2006.201.07:21:01.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:21:01.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:21:01.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:21:01.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:21:01.96$vck44/vb=8,4 2006.201.07:21:01.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.07:21:01.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.07:21:01.96#ibcon#ireg 11 cls_cnt 2 2006.201.07:21:01.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:21:02.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:21:02.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:21:02.02#ibcon#enter wrdev, iclass 30, count 2 2006.201.07:21:02.02#ibcon#first serial, iclass 30, count 2 2006.201.07:21:02.02#ibcon#enter sib2, iclass 30, count 2 2006.201.07:21:02.02#ibcon#flushed, iclass 30, count 2 2006.201.07:21:02.02#ibcon#about to write, iclass 30, count 2 2006.201.07:21:02.02#ibcon#wrote, iclass 30, count 2 2006.201.07:21:02.02#ibcon#about to read 3, iclass 30, count 2 2006.201.07:21:02.04#ibcon#read 3, iclass 30, count 2 2006.201.07:21:02.04#ibcon#about to read 4, iclass 30, count 2 2006.201.07:21:02.04#ibcon#read 4, iclass 30, count 2 2006.201.07:21:02.04#ibcon#about to read 5, iclass 30, count 2 2006.201.07:21:02.04#ibcon#read 5, iclass 30, count 2 2006.201.07:21:02.04#ibcon#about to read 6, iclass 30, count 2 2006.201.07:21:02.04#ibcon#read 6, iclass 30, count 2 2006.201.07:21:02.04#ibcon#end of sib2, iclass 30, count 2 2006.201.07:21:02.04#ibcon#*mode == 0, iclass 30, count 2 2006.201.07:21:02.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.07:21:02.04#ibcon#[27=AT08-04\r\n] 2006.201.07:21:02.04#ibcon#*before write, iclass 30, count 2 2006.201.07:21:02.04#ibcon#enter sib2, iclass 30, count 2 2006.201.07:21:02.04#ibcon#flushed, iclass 30, count 2 2006.201.07:21:02.04#ibcon#about to write, iclass 30, count 2 2006.201.07:21:02.04#ibcon#wrote, iclass 30, count 2 2006.201.07:21:02.04#ibcon#about to read 3, iclass 30, count 2 2006.201.07:21:02.07#ibcon#read 3, iclass 30, count 2 2006.201.07:21:02.07#ibcon#about to read 4, iclass 30, count 2 2006.201.07:21:02.07#ibcon#read 4, iclass 30, count 2 2006.201.07:21:02.07#ibcon#about to read 5, iclass 30, count 2 2006.201.07:21:02.07#ibcon#read 5, iclass 30, count 2 2006.201.07:21:02.07#ibcon#about to read 6, iclass 30, count 2 2006.201.07:21:02.07#ibcon#read 6, iclass 30, count 2 2006.201.07:21:02.07#ibcon#end of sib2, iclass 30, count 2 2006.201.07:21:02.07#ibcon#*after write, iclass 30, count 2 2006.201.07:21:02.07#ibcon#*before return 0, iclass 30, count 2 2006.201.07:21:02.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:21:02.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:21:02.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.07:21:02.07#ibcon#ireg 7 cls_cnt 0 2006.201.07:21:02.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:21:02.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:21:02.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:21:02.19#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:21:02.19#ibcon#first serial, iclass 30, count 0 2006.201.07:21:02.19#ibcon#enter sib2, iclass 30, count 0 2006.201.07:21:02.19#ibcon#flushed, iclass 30, count 0 2006.201.07:21:02.19#ibcon#about to write, iclass 30, count 0 2006.201.07:21:02.19#ibcon#wrote, iclass 30, count 0 2006.201.07:21:02.19#ibcon#about to read 3, iclass 30, count 0 2006.201.07:21:02.21#ibcon#read 3, iclass 30, count 0 2006.201.07:21:02.21#ibcon#about to read 4, iclass 30, count 0 2006.201.07:21:02.21#ibcon#read 4, iclass 30, count 0 2006.201.07:21:02.21#ibcon#about to read 5, iclass 30, count 0 2006.201.07:21:02.21#ibcon#read 5, iclass 30, count 0 2006.201.07:21:02.21#ibcon#about to read 6, iclass 30, count 0 2006.201.07:21:02.21#ibcon#read 6, iclass 30, count 0 2006.201.07:21:02.21#ibcon#end of sib2, iclass 30, count 0 2006.201.07:21:02.21#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:21:02.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:21:02.21#ibcon#[27=USB\r\n] 2006.201.07:21:02.21#ibcon#*before write, iclass 30, count 0 2006.201.07:21:02.21#ibcon#enter sib2, iclass 30, count 0 2006.201.07:21:02.21#ibcon#flushed, iclass 30, count 0 2006.201.07:21:02.21#ibcon#about to write, iclass 30, count 0 2006.201.07:21:02.21#ibcon#wrote, iclass 30, count 0 2006.201.07:21:02.21#ibcon#about to read 3, iclass 30, count 0 2006.201.07:21:02.24#ibcon#read 3, iclass 30, count 0 2006.201.07:21:02.24#ibcon#about to read 4, iclass 30, count 0 2006.201.07:21:02.24#ibcon#read 4, iclass 30, count 0 2006.201.07:21:02.24#ibcon#about to read 5, iclass 30, count 0 2006.201.07:21:02.24#ibcon#read 5, iclass 30, count 0 2006.201.07:21:02.24#ibcon#about to read 6, iclass 30, count 0 2006.201.07:21:02.24#ibcon#read 6, iclass 30, count 0 2006.201.07:21:02.24#ibcon#end of sib2, iclass 30, count 0 2006.201.07:21:02.24#ibcon#*after write, iclass 30, count 0 2006.201.07:21:02.24#ibcon#*before return 0, iclass 30, count 0 2006.201.07:21:02.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:21:02.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:21:02.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:21:02.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:21:02.24$vck44/vabw=wide 2006.201.07:21:02.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.07:21:02.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.07:21:02.24#ibcon#ireg 8 cls_cnt 0 2006.201.07:21:02.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:21:02.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:21:02.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:21:02.24#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:21:02.24#ibcon#first serial, iclass 32, count 0 2006.201.07:21:02.24#ibcon#enter sib2, iclass 32, count 0 2006.201.07:21:02.24#ibcon#flushed, iclass 32, count 0 2006.201.07:21:02.24#ibcon#about to write, iclass 32, count 0 2006.201.07:21:02.24#ibcon#wrote, iclass 32, count 0 2006.201.07:21:02.24#ibcon#about to read 3, iclass 32, count 0 2006.201.07:21:02.26#ibcon#read 3, iclass 32, count 0 2006.201.07:21:02.26#ibcon#about to read 4, iclass 32, count 0 2006.201.07:21:02.26#ibcon#read 4, iclass 32, count 0 2006.201.07:21:02.26#ibcon#about to read 5, iclass 32, count 0 2006.201.07:21:02.26#ibcon#read 5, iclass 32, count 0 2006.201.07:21:02.26#ibcon#about to read 6, iclass 32, count 0 2006.201.07:21:02.26#ibcon#read 6, iclass 32, count 0 2006.201.07:21:02.26#ibcon#end of sib2, iclass 32, count 0 2006.201.07:21:02.26#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:21:02.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:21:02.26#ibcon#[25=BW32\r\n] 2006.201.07:21:02.26#ibcon#*before write, iclass 32, count 0 2006.201.07:21:02.26#ibcon#enter sib2, iclass 32, count 0 2006.201.07:21:02.26#ibcon#flushed, iclass 32, count 0 2006.201.07:21:02.26#ibcon#about to write, iclass 32, count 0 2006.201.07:21:02.26#ibcon#wrote, iclass 32, count 0 2006.201.07:21:02.26#ibcon#about to read 3, iclass 32, count 0 2006.201.07:21:02.29#ibcon#read 3, iclass 32, count 0 2006.201.07:21:02.29#ibcon#about to read 4, iclass 32, count 0 2006.201.07:21:02.29#ibcon#read 4, iclass 32, count 0 2006.201.07:21:02.29#ibcon#about to read 5, iclass 32, count 0 2006.201.07:21:02.29#ibcon#read 5, iclass 32, count 0 2006.201.07:21:02.29#ibcon#about to read 6, iclass 32, count 0 2006.201.07:21:02.29#ibcon#read 6, iclass 32, count 0 2006.201.07:21:02.29#ibcon#end of sib2, iclass 32, count 0 2006.201.07:21:02.29#ibcon#*after write, iclass 32, count 0 2006.201.07:21:02.29#ibcon#*before return 0, iclass 32, count 0 2006.201.07:21:02.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:21:02.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:21:02.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:21:02.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:21:02.29$vck44/vbbw=wide 2006.201.07:21:02.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.07:21:02.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.07:21:02.29#ibcon#ireg 8 cls_cnt 0 2006.201.07:21:02.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:21:02.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:21:02.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:21:02.36#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:21:02.36#ibcon#first serial, iclass 34, count 0 2006.201.07:21:02.36#ibcon#enter sib2, iclass 34, count 0 2006.201.07:21:02.36#ibcon#flushed, iclass 34, count 0 2006.201.07:21:02.36#ibcon#about to write, iclass 34, count 0 2006.201.07:21:02.36#ibcon#wrote, iclass 34, count 0 2006.201.07:21:02.36#ibcon#about to read 3, iclass 34, count 0 2006.201.07:21:02.38#ibcon#read 3, iclass 34, count 0 2006.201.07:21:02.38#ibcon#about to read 4, iclass 34, count 0 2006.201.07:21:02.38#ibcon#read 4, iclass 34, count 0 2006.201.07:21:02.38#ibcon#about to read 5, iclass 34, count 0 2006.201.07:21:02.38#ibcon#read 5, iclass 34, count 0 2006.201.07:21:02.38#ibcon#about to read 6, iclass 34, count 0 2006.201.07:21:02.38#ibcon#read 6, iclass 34, count 0 2006.201.07:21:02.38#ibcon#end of sib2, iclass 34, count 0 2006.201.07:21:02.38#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:21:02.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:21:02.38#ibcon#[27=BW32\r\n] 2006.201.07:21:02.38#ibcon#*before write, iclass 34, count 0 2006.201.07:21:02.38#ibcon#enter sib2, iclass 34, count 0 2006.201.07:21:02.38#ibcon#flushed, iclass 34, count 0 2006.201.07:21:02.38#ibcon#about to write, iclass 34, count 0 2006.201.07:21:02.38#ibcon#wrote, iclass 34, count 0 2006.201.07:21:02.38#ibcon#about to read 3, iclass 34, count 0 2006.201.07:21:02.41#ibcon#read 3, iclass 34, count 0 2006.201.07:21:02.41#ibcon#about to read 4, iclass 34, count 0 2006.201.07:21:02.41#ibcon#read 4, iclass 34, count 0 2006.201.07:21:02.41#ibcon#about to read 5, iclass 34, count 0 2006.201.07:21:02.41#ibcon#read 5, iclass 34, count 0 2006.201.07:21:02.41#ibcon#about to read 6, iclass 34, count 0 2006.201.07:21:02.41#ibcon#read 6, iclass 34, count 0 2006.201.07:21:02.41#ibcon#end of sib2, iclass 34, count 0 2006.201.07:21:02.41#ibcon#*after write, iclass 34, count 0 2006.201.07:21:02.41#ibcon#*before return 0, iclass 34, count 0 2006.201.07:21:02.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:21:02.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:21:02.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:21:02.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:21:02.41$setupk4/ifdk4 2006.201.07:21:02.41$ifdk4/lo= 2006.201.07:21:02.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:21:02.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:21:02.41$ifdk4/patch= 2006.201.07:21:02.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:21:02.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:21:02.41$setupk4/!*+20s 2006.201.07:21:09.62#abcon#<5=/05 2.4 4.2 23.22 881003.1\r\n> 2006.201.07:21:09.64#abcon#{5=INTERFACE CLEAR} 2006.201.07:21:09.70#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:21:16.90$setupk4/"tpicd 2006.201.07:21:16.90$setupk4/echo=off 2006.201.07:21:16.90$setupk4/xlog=off 2006.201.07:21:16.90:!2006.201.07:21:36 2006.201.07:21:19.14#trakl#Source acquired 2006.201.07:21:19.14#flagr#flagr/antenna,acquired 2006.201.07:21:36.00:preob 2006.201.07:21:36.14/onsource/TRACKING 2006.201.07:21:36.14:!2006.201.07:21:46 2006.201.07:21:46.00:"tape 2006.201.07:21:46.00:"st=record 2006.201.07:21:46.00:data_valid=on 2006.201.07:21:46.00:midob 2006.201.07:21:46.14/onsource/TRACKING 2006.201.07:21:46.14/wx/23.22,1003.1,88 2006.201.07:21:46.23/cable/+6.4652E-03 2006.201.07:21:47.32/va/01,08,usb,yes,28,30 2006.201.07:21:47.32/va/02,07,usb,yes,30,31 2006.201.07:21:47.32/va/03,08,usb,yes,27,29 2006.201.07:21:47.32/va/04,07,usb,yes,31,33 2006.201.07:21:47.32/va/05,04,usb,yes,28,28 2006.201.07:21:47.32/va/06,05,usb,yes,28,28 2006.201.07:21:47.32/va/07,05,usb,yes,27,28 2006.201.07:21:47.32/va/08,04,usb,yes,27,32 2006.201.07:21:47.55/valo/01,524.99,yes,locked 2006.201.07:21:47.55/valo/02,534.99,yes,locked 2006.201.07:21:47.55/valo/03,564.99,yes,locked 2006.201.07:21:47.55/valo/04,624.99,yes,locked 2006.201.07:21:47.55/valo/05,734.99,yes,locked 2006.201.07:21:47.55/valo/06,814.99,yes,locked 2006.201.07:21:47.55/valo/07,864.99,yes,locked 2006.201.07:21:47.55/valo/08,884.99,yes,locked 2006.201.07:21:48.64/vb/01,04,usb,yes,28,26 2006.201.07:21:48.64/vb/02,05,usb,yes,27,27 2006.201.07:21:48.64/vb/03,04,usb,yes,28,31 2006.201.07:21:48.64/vb/04,05,usb,yes,28,27 2006.201.07:21:48.64/vb/05,04,usb,yes,25,27 2006.201.07:21:48.64/vb/06,04,usb,yes,29,25 2006.201.07:21:48.64/vb/07,04,usb,yes,29,28 2006.201.07:21:48.64/vb/08,04,usb,yes,26,29 2006.201.07:21:48.87/vblo/01,629.99,yes,locked 2006.201.07:21:48.87/vblo/02,634.99,yes,locked 2006.201.07:21:48.87/vblo/03,649.99,yes,locked 2006.201.07:21:48.87/vblo/04,679.99,yes,locked 2006.201.07:21:48.87/vblo/05,709.99,yes,locked 2006.201.07:21:48.87/vblo/06,719.99,yes,locked 2006.201.07:21:48.87/vblo/07,734.99,yes,locked 2006.201.07:21:48.87/vblo/08,744.99,yes,locked 2006.201.07:21:49.02/vabw/8 2006.201.07:21:49.17/vbbw/8 2006.201.07:21:49.26/xfe/off,on,15.2 2006.201.07:21:49.63/ifatt/23,28,28,28 2006.201.07:21:50.05/fmout-gps/S +4.52E-07 2006.201.07:21:50.12:!2006.201.07:23:26 2006.201.07:23:26.00:data_valid=off 2006.201.07:23:26.00:"et 2006.201.07:23:26.00:!+3s 2006.201.07:23:29.02:"tape 2006.201.07:23:29.02:postob 2006.201.07:23:29.10/cable/+6.4683E-03 2006.201.07:23:29.10/wx/23.22,1003.1,87 2006.201.07:23:29.17/fmout-gps/S +4.53E-07 2006.201.07:23:29.17:scan_name=201-0725,jd0607,350 2006.201.07:23:29.18:source=oq208,140700.39,282714.7,2000.0,ccw 2006.201.07:23:31.14#flagr#flagr/antenna,new-source 2006.201.07:23:31.14:checkk5 2006.201.07:23:31.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:23:31.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:23:32.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:23:32.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:23:32.98/chk_obsdata//k5ts1/T2010721??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.07:23:33.35/chk_obsdata//k5ts2/T2010721??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.07:23:33.72/chk_obsdata//k5ts3/T2010721??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.07:23:34.08/chk_obsdata//k5ts4/T2010721??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.07:23:34.76/k5log//k5ts1_log_newline 2006.201.07:23:35.46/k5log//k5ts2_log_newline 2006.201.07:23:36.15/k5log//k5ts3_log_newline 2006.201.07:23:36.84/k5log//k5ts4_log_newline 2006.201.07:23:36.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:23:36.86:setupk4=1 2006.201.07:23:36.86$setupk4/echo=on 2006.201.07:23:36.86$setupk4/pcalon 2006.201.07:23:36.86$pcalon/"no phase cal control is implemented here 2006.201.07:23:36.86$setupk4/"tpicd=stop 2006.201.07:23:36.86$setupk4/"rec=synch_on 2006.201.07:23:36.86$setupk4/"rec_mode=128 2006.201.07:23:36.86$setupk4/!* 2006.201.07:23:36.86$setupk4/recpk4 2006.201.07:23:36.86$recpk4/recpatch= 2006.201.07:23:36.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:23:36.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:23:36.87$setupk4/vck44 2006.201.07:23:36.87$vck44/valo=1,524.99 2006.201.07:23:36.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.07:23:36.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.07:23:36.87#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:36.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:36.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:36.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:36.87#ibcon#enter wrdev, iclass 27, count 0 2006.201.07:23:36.87#ibcon#first serial, iclass 27, count 0 2006.201.07:23:36.87#ibcon#enter sib2, iclass 27, count 0 2006.201.07:23:36.87#ibcon#flushed, iclass 27, count 0 2006.201.07:23:36.87#ibcon#about to write, iclass 27, count 0 2006.201.07:23:36.87#ibcon#wrote, iclass 27, count 0 2006.201.07:23:36.87#ibcon#about to read 3, iclass 27, count 0 2006.201.07:23:36.90#ibcon#read 3, iclass 27, count 0 2006.201.07:23:36.90#ibcon#about to read 4, iclass 27, count 0 2006.201.07:23:36.90#ibcon#read 4, iclass 27, count 0 2006.201.07:23:36.90#ibcon#about to read 5, iclass 27, count 0 2006.201.07:23:36.90#ibcon#read 5, iclass 27, count 0 2006.201.07:23:36.90#ibcon#about to read 6, iclass 27, count 0 2006.201.07:23:36.90#ibcon#read 6, iclass 27, count 0 2006.201.07:23:36.90#ibcon#end of sib2, iclass 27, count 0 2006.201.07:23:36.90#ibcon#*mode == 0, iclass 27, count 0 2006.201.07:23:36.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.07:23:36.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:23:36.90#ibcon#*before write, iclass 27, count 0 2006.201.07:23:36.90#ibcon#enter sib2, iclass 27, count 0 2006.201.07:23:36.90#ibcon#flushed, iclass 27, count 0 2006.201.07:23:36.90#ibcon#about to write, iclass 27, count 0 2006.201.07:23:36.90#ibcon#wrote, iclass 27, count 0 2006.201.07:23:36.90#ibcon#about to read 3, iclass 27, count 0 2006.201.07:23:36.95#ibcon#read 3, iclass 27, count 0 2006.201.07:23:36.95#ibcon#about to read 4, iclass 27, count 0 2006.201.07:23:36.95#ibcon#read 4, iclass 27, count 0 2006.201.07:23:36.95#ibcon#about to read 5, iclass 27, count 0 2006.201.07:23:36.95#ibcon#read 5, iclass 27, count 0 2006.201.07:23:36.95#ibcon#about to read 6, iclass 27, count 0 2006.201.07:23:36.95#ibcon#read 6, iclass 27, count 0 2006.201.07:23:36.95#ibcon#end of sib2, iclass 27, count 0 2006.201.07:23:36.95#ibcon#*after write, iclass 27, count 0 2006.201.07:23:36.95#ibcon#*before return 0, iclass 27, count 0 2006.201.07:23:36.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:36.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:36.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.07:23:36.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.07:23:36.95$vck44/va=1,8 2006.201.07:23:36.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.07:23:36.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.07:23:36.95#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:36.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:36.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:36.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:36.95#ibcon#enter wrdev, iclass 29, count 2 2006.201.07:23:36.95#ibcon#first serial, iclass 29, count 2 2006.201.07:23:36.95#ibcon#enter sib2, iclass 29, count 2 2006.201.07:23:36.95#ibcon#flushed, iclass 29, count 2 2006.201.07:23:36.95#ibcon#about to write, iclass 29, count 2 2006.201.07:23:36.95#ibcon#wrote, iclass 29, count 2 2006.201.07:23:36.95#ibcon#about to read 3, iclass 29, count 2 2006.201.07:23:36.97#ibcon#read 3, iclass 29, count 2 2006.201.07:23:36.97#ibcon#about to read 4, iclass 29, count 2 2006.201.07:23:36.97#ibcon#read 4, iclass 29, count 2 2006.201.07:23:36.97#ibcon#about to read 5, iclass 29, count 2 2006.201.07:23:36.97#ibcon#read 5, iclass 29, count 2 2006.201.07:23:36.97#ibcon#about to read 6, iclass 29, count 2 2006.201.07:23:36.97#ibcon#read 6, iclass 29, count 2 2006.201.07:23:36.97#ibcon#end of sib2, iclass 29, count 2 2006.201.07:23:36.97#ibcon#*mode == 0, iclass 29, count 2 2006.201.07:23:36.97#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.07:23:36.97#ibcon#[25=AT01-08\r\n] 2006.201.07:23:36.97#ibcon#*before write, iclass 29, count 2 2006.201.07:23:36.97#ibcon#enter sib2, iclass 29, count 2 2006.201.07:23:36.97#ibcon#flushed, iclass 29, count 2 2006.201.07:23:36.97#ibcon#about to write, iclass 29, count 2 2006.201.07:23:36.97#ibcon#wrote, iclass 29, count 2 2006.201.07:23:36.97#ibcon#about to read 3, iclass 29, count 2 2006.201.07:23:37.00#ibcon#read 3, iclass 29, count 2 2006.201.07:23:37.00#ibcon#about to read 4, iclass 29, count 2 2006.201.07:23:37.00#ibcon#read 4, iclass 29, count 2 2006.201.07:23:37.00#ibcon#about to read 5, iclass 29, count 2 2006.201.07:23:37.00#ibcon#read 5, iclass 29, count 2 2006.201.07:23:37.00#ibcon#about to read 6, iclass 29, count 2 2006.201.07:23:37.00#ibcon#read 6, iclass 29, count 2 2006.201.07:23:37.00#ibcon#end of sib2, iclass 29, count 2 2006.201.07:23:37.00#ibcon#*after write, iclass 29, count 2 2006.201.07:23:37.00#ibcon#*before return 0, iclass 29, count 2 2006.201.07:23:37.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:37.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:37.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.07:23:37.00#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:37.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:37.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:37.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:37.12#ibcon#enter wrdev, iclass 29, count 0 2006.201.07:23:37.12#ibcon#first serial, iclass 29, count 0 2006.201.07:23:37.12#ibcon#enter sib2, iclass 29, count 0 2006.201.07:23:37.12#ibcon#flushed, iclass 29, count 0 2006.201.07:23:37.12#ibcon#about to write, iclass 29, count 0 2006.201.07:23:37.12#ibcon#wrote, iclass 29, count 0 2006.201.07:23:37.12#ibcon#about to read 3, iclass 29, count 0 2006.201.07:23:37.14#ibcon#read 3, iclass 29, count 0 2006.201.07:23:37.14#ibcon#about to read 4, iclass 29, count 0 2006.201.07:23:37.14#ibcon#read 4, iclass 29, count 0 2006.201.07:23:37.14#ibcon#about to read 5, iclass 29, count 0 2006.201.07:23:37.14#ibcon#read 5, iclass 29, count 0 2006.201.07:23:37.14#ibcon#about to read 6, iclass 29, count 0 2006.201.07:23:37.14#ibcon#read 6, iclass 29, count 0 2006.201.07:23:37.14#ibcon#end of sib2, iclass 29, count 0 2006.201.07:23:37.14#ibcon#*mode == 0, iclass 29, count 0 2006.201.07:23:37.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.07:23:37.14#ibcon#[25=USB\r\n] 2006.201.07:23:37.14#ibcon#*before write, iclass 29, count 0 2006.201.07:23:37.14#ibcon#enter sib2, iclass 29, count 0 2006.201.07:23:37.14#ibcon#flushed, iclass 29, count 0 2006.201.07:23:37.14#ibcon#about to write, iclass 29, count 0 2006.201.07:23:37.14#ibcon#wrote, iclass 29, count 0 2006.201.07:23:37.14#ibcon#about to read 3, iclass 29, count 0 2006.201.07:23:37.17#ibcon#read 3, iclass 29, count 0 2006.201.07:23:37.17#ibcon#about to read 4, iclass 29, count 0 2006.201.07:23:37.17#ibcon#read 4, iclass 29, count 0 2006.201.07:23:37.17#ibcon#about to read 5, iclass 29, count 0 2006.201.07:23:37.17#ibcon#read 5, iclass 29, count 0 2006.201.07:23:37.17#ibcon#about to read 6, iclass 29, count 0 2006.201.07:23:37.17#ibcon#read 6, iclass 29, count 0 2006.201.07:23:37.17#ibcon#end of sib2, iclass 29, count 0 2006.201.07:23:37.17#ibcon#*after write, iclass 29, count 0 2006.201.07:23:37.17#ibcon#*before return 0, iclass 29, count 0 2006.201.07:23:37.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:37.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:37.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.07:23:37.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.07:23:37.17$vck44/valo=2,534.99 2006.201.07:23:37.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.07:23:37.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.07:23:37.17#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:37.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:37.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:37.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:37.17#ibcon#enter wrdev, iclass 31, count 0 2006.201.07:23:37.17#ibcon#first serial, iclass 31, count 0 2006.201.07:23:37.17#ibcon#enter sib2, iclass 31, count 0 2006.201.07:23:37.17#ibcon#flushed, iclass 31, count 0 2006.201.07:23:37.17#ibcon#about to write, iclass 31, count 0 2006.201.07:23:37.17#ibcon#wrote, iclass 31, count 0 2006.201.07:23:37.17#ibcon#about to read 3, iclass 31, count 0 2006.201.07:23:37.19#ibcon#read 3, iclass 31, count 0 2006.201.07:23:37.19#ibcon#about to read 4, iclass 31, count 0 2006.201.07:23:37.19#ibcon#read 4, iclass 31, count 0 2006.201.07:23:37.19#ibcon#about to read 5, iclass 31, count 0 2006.201.07:23:37.19#ibcon#read 5, iclass 31, count 0 2006.201.07:23:37.19#ibcon#about to read 6, iclass 31, count 0 2006.201.07:23:37.19#ibcon#read 6, iclass 31, count 0 2006.201.07:23:37.19#ibcon#end of sib2, iclass 31, count 0 2006.201.07:23:37.19#ibcon#*mode == 0, iclass 31, count 0 2006.201.07:23:37.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.07:23:37.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:23:37.19#ibcon#*before write, iclass 31, count 0 2006.201.07:23:37.19#ibcon#enter sib2, iclass 31, count 0 2006.201.07:23:37.19#ibcon#flushed, iclass 31, count 0 2006.201.07:23:37.19#ibcon#about to write, iclass 31, count 0 2006.201.07:23:37.19#ibcon#wrote, iclass 31, count 0 2006.201.07:23:37.19#ibcon#about to read 3, iclass 31, count 0 2006.201.07:23:37.24#ibcon#read 3, iclass 31, count 0 2006.201.07:23:37.24#ibcon#about to read 4, iclass 31, count 0 2006.201.07:23:37.24#ibcon#read 4, iclass 31, count 0 2006.201.07:23:37.24#ibcon#about to read 5, iclass 31, count 0 2006.201.07:23:37.24#ibcon#read 5, iclass 31, count 0 2006.201.07:23:37.24#ibcon#about to read 6, iclass 31, count 0 2006.201.07:23:37.24#ibcon#read 6, iclass 31, count 0 2006.201.07:23:37.24#ibcon#end of sib2, iclass 31, count 0 2006.201.07:23:37.24#ibcon#*after write, iclass 31, count 0 2006.201.07:23:37.24#ibcon#*before return 0, iclass 31, count 0 2006.201.07:23:37.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:37.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:37.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.07:23:37.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.07:23:37.24$vck44/va=2,7 2006.201.07:23:37.24#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.07:23:37.24#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.07:23:37.24#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:37.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:37.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:37.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:37.29#ibcon#enter wrdev, iclass 33, count 2 2006.201.07:23:37.29#ibcon#first serial, iclass 33, count 2 2006.201.07:23:37.29#ibcon#enter sib2, iclass 33, count 2 2006.201.07:23:37.29#ibcon#flushed, iclass 33, count 2 2006.201.07:23:37.29#ibcon#about to write, iclass 33, count 2 2006.201.07:23:37.29#ibcon#wrote, iclass 33, count 2 2006.201.07:23:37.29#ibcon#about to read 3, iclass 33, count 2 2006.201.07:23:37.31#ibcon#read 3, iclass 33, count 2 2006.201.07:23:37.31#ibcon#about to read 4, iclass 33, count 2 2006.201.07:23:37.31#ibcon#read 4, iclass 33, count 2 2006.201.07:23:37.31#ibcon#about to read 5, iclass 33, count 2 2006.201.07:23:37.31#ibcon#read 5, iclass 33, count 2 2006.201.07:23:37.31#ibcon#about to read 6, iclass 33, count 2 2006.201.07:23:37.31#ibcon#read 6, iclass 33, count 2 2006.201.07:23:37.31#ibcon#end of sib2, iclass 33, count 2 2006.201.07:23:37.31#ibcon#*mode == 0, iclass 33, count 2 2006.201.07:23:37.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.07:23:37.31#ibcon#[25=AT02-07\r\n] 2006.201.07:23:37.31#ibcon#*before write, iclass 33, count 2 2006.201.07:23:37.31#ibcon#enter sib2, iclass 33, count 2 2006.201.07:23:37.31#ibcon#flushed, iclass 33, count 2 2006.201.07:23:37.31#ibcon#about to write, iclass 33, count 2 2006.201.07:23:37.31#ibcon#wrote, iclass 33, count 2 2006.201.07:23:37.31#ibcon#about to read 3, iclass 33, count 2 2006.201.07:23:37.34#ibcon#read 3, iclass 33, count 2 2006.201.07:23:37.34#ibcon#about to read 4, iclass 33, count 2 2006.201.07:23:37.34#ibcon#read 4, iclass 33, count 2 2006.201.07:23:37.34#ibcon#about to read 5, iclass 33, count 2 2006.201.07:23:37.34#ibcon#read 5, iclass 33, count 2 2006.201.07:23:37.34#ibcon#about to read 6, iclass 33, count 2 2006.201.07:23:37.34#ibcon#read 6, iclass 33, count 2 2006.201.07:23:37.34#ibcon#end of sib2, iclass 33, count 2 2006.201.07:23:37.34#ibcon#*after write, iclass 33, count 2 2006.201.07:23:37.34#ibcon#*before return 0, iclass 33, count 2 2006.201.07:23:37.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:37.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:37.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.07:23:37.34#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:37.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:37.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:37.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:37.46#ibcon#enter wrdev, iclass 33, count 0 2006.201.07:23:37.46#ibcon#first serial, iclass 33, count 0 2006.201.07:23:37.46#ibcon#enter sib2, iclass 33, count 0 2006.201.07:23:37.46#ibcon#flushed, iclass 33, count 0 2006.201.07:23:37.46#ibcon#about to write, iclass 33, count 0 2006.201.07:23:37.46#ibcon#wrote, iclass 33, count 0 2006.201.07:23:37.46#ibcon#about to read 3, iclass 33, count 0 2006.201.07:23:37.48#ibcon#read 3, iclass 33, count 0 2006.201.07:23:37.48#ibcon#about to read 4, iclass 33, count 0 2006.201.07:23:37.48#ibcon#read 4, iclass 33, count 0 2006.201.07:23:37.48#ibcon#about to read 5, iclass 33, count 0 2006.201.07:23:37.48#ibcon#read 5, iclass 33, count 0 2006.201.07:23:37.48#ibcon#about to read 6, iclass 33, count 0 2006.201.07:23:37.48#ibcon#read 6, iclass 33, count 0 2006.201.07:23:37.48#ibcon#end of sib2, iclass 33, count 0 2006.201.07:23:37.48#ibcon#*mode == 0, iclass 33, count 0 2006.201.07:23:37.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.07:23:37.48#ibcon#[25=USB\r\n] 2006.201.07:23:37.48#ibcon#*before write, iclass 33, count 0 2006.201.07:23:37.48#ibcon#enter sib2, iclass 33, count 0 2006.201.07:23:37.48#ibcon#flushed, iclass 33, count 0 2006.201.07:23:37.48#ibcon#about to write, iclass 33, count 0 2006.201.07:23:37.48#ibcon#wrote, iclass 33, count 0 2006.201.07:23:37.48#ibcon#about to read 3, iclass 33, count 0 2006.201.07:23:37.51#ibcon#read 3, iclass 33, count 0 2006.201.07:23:37.51#ibcon#about to read 4, iclass 33, count 0 2006.201.07:23:37.51#ibcon#read 4, iclass 33, count 0 2006.201.07:23:37.51#ibcon#about to read 5, iclass 33, count 0 2006.201.07:23:37.51#ibcon#read 5, iclass 33, count 0 2006.201.07:23:37.51#ibcon#about to read 6, iclass 33, count 0 2006.201.07:23:37.51#ibcon#read 6, iclass 33, count 0 2006.201.07:23:37.51#ibcon#end of sib2, iclass 33, count 0 2006.201.07:23:37.51#ibcon#*after write, iclass 33, count 0 2006.201.07:23:37.51#ibcon#*before return 0, iclass 33, count 0 2006.201.07:23:37.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:37.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:37.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.07:23:37.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.07:23:37.51$vck44/valo=3,564.99 2006.201.07:23:37.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.07:23:37.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.07:23:37.51#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:37.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:37.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:37.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:37.51#ibcon#enter wrdev, iclass 35, count 0 2006.201.07:23:37.51#ibcon#first serial, iclass 35, count 0 2006.201.07:23:37.51#ibcon#enter sib2, iclass 35, count 0 2006.201.07:23:37.51#ibcon#flushed, iclass 35, count 0 2006.201.07:23:37.51#ibcon#about to write, iclass 35, count 0 2006.201.07:23:37.51#ibcon#wrote, iclass 35, count 0 2006.201.07:23:37.51#ibcon#about to read 3, iclass 35, count 0 2006.201.07:23:37.53#ibcon#read 3, iclass 35, count 0 2006.201.07:23:37.53#ibcon#about to read 4, iclass 35, count 0 2006.201.07:23:37.53#ibcon#read 4, iclass 35, count 0 2006.201.07:23:37.53#ibcon#about to read 5, iclass 35, count 0 2006.201.07:23:37.53#ibcon#read 5, iclass 35, count 0 2006.201.07:23:37.53#ibcon#about to read 6, iclass 35, count 0 2006.201.07:23:37.53#ibcon#read 6, iclass 35, count 0 2006.201.07:23:37.53#ibcon#end of sib2, iclass 35, count 0 2006.201.07:23:37.53#ibcon#*mode == 0, iclass 35, count 0 2006.201.07:23:37.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.07:23:37.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:23:37.53#ibcon#*before write, iclass 35, count 0 2006.201.07:23:37.53#ibcon#enter sib2, iclass 35, count 0 2006.201.07:23:37.53#ibcon#flushed, iclass 35, count 0 2006.201.07:23:37.53#ibcon#about to write, iclass 35, count 0 2006.201.07:23:37.53#ibcon#wrote, iclass 35, count 0 2006.201.07:23:37.53#ibcon#about to read 3, iclass 35, count 0 2006.201.07:23:37.58#ibcon#read 3, iclass 35, count 0 2006.201.07:23:37.58#ibcon#about to read 4, iclass 35, count 0 2006.201.07:23:37.58#ibcon#read 4, iclass 35, count 0 2006.201.07:23:37.58#ibcon#about to read 5, iclass 35, count 0 2006.201.07:23:37.58#ibcon#read 5, iclass 35, count 0 2006.201.07:23:37.58#ibcon#about to read 6, iclass 35, count 0 2006.201.07:23:37.58#ibcon#read 6, iclass 35, count 0 2006.201.07:23:37.58#ibcon#end of sib2, iclass 35, count 0 2006.201.07:23:37.58#ibcon#*after write, iclass 35, count 0 2006.201.07:23:37.58#ibcon#*before return 0, iclass 35, count 0 2006.201.07:23:37.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:37.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:37.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.07:23:37.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.07:23:37.58$vck44/va=3,8 2006.201.07:23:37.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.07:23:37.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.07:23:37.58#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:37.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:37.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:37.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:37.63#ibcon#enter wrdev, iclass 37, count 2 2006.201.07:23:37.63#ibcon#first serial, iclass 37, count 2 2006.201.07:23:37.63#ibcon#enter sib2, iclass 37, count 2 2006.201.07:23:37.63#ibcon#flushed, iclass 37, count 2 2006.201.07:23:37.63#ibcon#about to write, iclass 37, count 2 2006.201.07:23:37.63#ibcon#wrote, iclass 37, count 2 2006.201.07:23:37.63#ibcon#about to read 3, iclass 37, count 2 2006.201.07:23:37.65#ibcon#read 3, iclass 37, count 2 2006.201.07:23:37.65#ibcon#about to read 4, iclass 37, count 2 2006.201.07:23:37.65#ibcon#read 4, iclass 37, count 2 2006.201.07:23:37.65#ibcon#about to read 5, iclass 37, count 2 2006.201.07:23:37.65#ibcon#read 5, iclass 37, count 2 2006.201.07:23:37.65#ibcon#about to read 6, iclass 37, count 2 2006.201.07:23:37.65#ibcon#read 6, iclass 37, count 2 2006.201.07:23:37.65#ibcon#end of sib2, iclass 37, count 2 2006.201.07:23:37.65#ibcon#*mode == 0, iclass 37, count 2 2006.201.07:23:37.65#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.07:23:37.65#ibcon#[25=AT03-08\r\n] 2006.201.07:23:37.65#ibcon#*before write, iclass 37, count 2 2006.201.07:23:37.65#ibcon#enter sib2, iclass 37, count 2 2006.201.07:23:37.65#ibcon#flushed, iclass 37, count 2 2006.201.07:23:37.65#ibcon#about to write, iclass 37, count 2 2006.201.07:23:37.65#ibcon#wrote, iclass 37, count 2 2006.201.07:23:37.65#ibcon#about to read 3, iclass 37, count 2 2006.201.07:23:37.68#ibcon#read 3, iclass 37, count 2 2006.201.07:23:37.68#ibcon#about to read 4, iclass 37, count 2 2006.201.07:23:37.68#ibcon#read 4, iclass 37, count 2 2006.201.07:23:37.68#ibcon#about to read 5, iclass 37, count 2 2006.201.07:23:37.68#ibcon#read 5, iclass 37, count 2 2006.201.07:23:37.68#ibcon#about to read 6, iclass 37, count 2 2006.201.07:23:37.68#ibcon#read 6, iclass 37, count 2 2006.201.07:23:37.68#ibcon#end of sib2, iclass 37, count 2 2006.201.07:23:37.68#ibcon#*after write, iclass 37, count 2 2006.201.07:23:37.68#ibcon#*before return 0, iclass 37, count 2 2006.201.07:23:37.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:37.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:37.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.07:23:37.68#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:37.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:37.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:37.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:37.80#ibcon#enter wrdev, iclass 37, count 0 2006.201.07:23:37.80#ibcon#first serial, iclass 37, count 0 2006.201.07:23:37.80#ibcon#enter sib2, iclass 37, count 0 2006.201.07:23:37.80#ibcon#flushed, iclass 37, count 0 2006.201.07:23:37.80#ibcon#about to write, iclass 37, count 0 2006.201.07:23:37.80#ibcon#wrote, iclass 37, count 0 2006.201.07:23:37.80#ibcon#about to read 3, iclass 37, count 0 2006.201.07:23:37.82#ibcon#read 3, iclass 37, count 0 2006.201.07:23:37.82#ibcon#about to read 4, iclass 37, count 0 2006.201.07:23:37.82#ibcon#read 4, iclass 37, count 0 2006.201.07:23:37.82#ibcon#about to read 5, iclass 37, count 0 2006.201.07:23:37.82#ibcon#read 5, iclass 37, count 0 2006.201.07:23:37.82#ibcon#about to read 6, iclass 37, count 0 2006.201.07:23:37.82#ibcon#read 6, iclass 37, count 0 2006.201.07:23:37.82#ibcon#end of sib2, iclass 37, count 0 2006.201.07:23:37.82#ibcon#*mode == 0, iclass 37, count 0 2006.201.07:23:37.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.07:23:37.82#ibcon#[25=USB\r\n] 2006.201.07:23:37.82#ibcon#*before write, iclass 37, count 0 2006.201.07:23:37.82#ibcon#enter sib2, iclass 37, count 0 2006.201.07:23:37.82#ibcon#flushed, iclass 37, count 0 2006.201.07:23:37.82#ibcon#about to write, iclass 37, count 0 2006.201.07:23:37.82#ibcon#wrote, iclass 37, count 0 2006.201.07:23:37.82#ibcon#about to read 3, iclass 37, count 0 2006.201.07:23:37.85#ibcon#read 3, iclass 37, count 0 2006.201.07:23:37.85#ibcon#about to read 4, iclass 37, count 0 2006.201.07:23:37.85#ibcon#read 4, iclass 37, count 0 2006.201.07:23:37.85#ibcon#about to read 5, iclass 37, count 0 2006.201.07:23:37.85#ibcon#read 5, iclass 37, count 0 2006.201.07:23:37.85#ibcon#about to read 6, iclass 37, count 0 2006.201.07:23:37.85#ibcon#read 6, iclass 37, count 0 2006.201.07:23:37.85#ibcon#end of sib2, iclass 37, count 0 2006.201.07:23:37.85#ibcon#*after write, iclass 37, count 0 2006.201.07:23:37.85#ibcon#*before return 0, iclass 37, count 0 2006.201.07:23:37.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:37.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:37.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.07:23:37.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.07:23:37.85$vck44/valo=4,624.99 2006.201.07:23:37.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.07:23:37.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.07:23:37.85#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:37.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:37.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:37.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:37.85#ibcon#enter wrdev, iclass 39, count 0 2006.201.07:23:37.85#ibcon#first serial, iclass 39, count 0 2006.201.07:23:37.85#ibcon#enter sib2, iclass 39, count 0 2006.201.07:23:37.85#ibcon#flushed, iclass 39, count 0 2006.201.07:23:37.85#ibcon#about to write, iclass 39, count 0 2006.201.07:23:37.85#ibcon#wrote, iclass 39, count 0 2006.201.07:23:37.85#ibcon#about to read 3, iclass 39, count 0 2006.201.07:23:37.87#ibcon#read 3, iclass 39, count 0 2006.201.07:23:37.87#ibcon#about to read 4, iclass 39, count 0 2006.201.07:23:37.87#ibcon#read 4, iclass 39, count 0 2006.201.07:23:37.87#ibcon#about to read 5, iclass 39, count 0 2006.201.07:23:37.87#ibcon#read 5, iclass 39, count 0 2006.201.07:23:37.87#ibcon#about to read 6, iclass 39, count 0 2006.201.07:23:37.87#ibcon#read 6, iclass 39, count 0 2006.201.07:23:37.87#ibcon#end of sib2, iclass 39, count 0 2006.201.07:23:37.87#ibcon#*mode == 0, iclass 39, count 0 2006.201.07:23:37.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.07:23:37.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:23:37.87#ibcon#*before write, iclass 39, count 0 2006.201.07:23:37.87#ibcon#enter sib2, iclass 39, count 0 2006.201.07:23:37.87#ibcon#flushed, iclass 39, count 0 2006.201.07:23:37.87#ibcon#about to write, iclass 39, count 0 2006.201.07:23:37.87#ibcon#wrote, iclass 39, count 0 2006.201.07:23:37.87#ibcon#about to read 3, iclass 39, count 0 2006.201.07:23:37.91#ibcon#read 3, iclass 39, count 0 2006.201.07:23:37.91#ibcon#about to read 4, iclass 39, count 0 2006.201.07:23:37.91#ibcon#read 4, iclass 39, count 0 2006.201.07:23:37.91#ibcon#about to read 5, iclass 39, count 0 2006.201.07:23:37.91#ibcon#read 5, iclass 39, count 0 2006.201.07:23:37.91#ibcon#about to read 6, iclass 39, count 0 2006.201.07:23:37.91#ibcon#read 6, iclass 39, count 0 2006.201.07:23:37.91#ibcon#end of sib2, iclass 39, count 0 2006.201.07:23:37.91#ibcon#*after write, iclass 39, count 0 2006.201.07:23:37.91#ibcon#*before return 0, iclass 39, count 0 2006.201.07:23:37.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:37.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:37.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.07:23:37.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.07:23:37.91$vck44/va=4,7 2006.201.07:23:37.91#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.07:23:37.91#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.07:23:37.91#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:37.91#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:37.97#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:37.97#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:37.97#ibcon#enter wrdev, iclass 2, count 2 2006.201.07:23:37.97#ibcon#first serial, iclass 2, count 2 2006.201.07:23:37.97#ibcon#enter sib2, iclass 2, count 2 2006.201.07:23:37.97#ibcon#flushed, iclass 2, count 2 2006.201.07:23:37.97#ibcon#about to write, iclass 2, count 2 2006.201.07:23:37.97#ibcon#wrote, iclass 2, count 2 2006.201.07:23:37.97#ibcon#about to read 3, iclass 2, count 2 2006.201.07:23:37.99#ibcon#read 3, iclass 2, count 2 2006.201.07:23:37.99#ibcon#about to read 4, iclass 2, count 2 2006.201.07:23:37.99#ibcon#read 4, iclass 2, count 2 2006.201.07:23:37.99#ibcon#about to read 5, iclass 2, count 2 2006.201.07:23:37.99#ibcon#read 5, iclass 2, count 2 2006.201.07:23:37.99#ibcon#about to read 6, iclass 2, count 2 2006.201.07:23:37.99#ibcon#read 6, iclass 2, count 2 2006.201.07:23:37.99#ibcon#end of sib2, iclass 2, count 2 2006.201.07:23:37.99#ibcon#*mode == 0, iclass 2, count 2 2006.201.07:23:37.99#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.07:23:37.99#ibcon#[25=AT04-07\r\n] 2006.201.07:23:37.99#ibcon#*before write, iclass 2, count 2 2006.201.07:23:37.99#ibcon#enter sib2, iclass 2, count 2 2006.201.07:23:37.99#ibcon#flushed, iclass 2, count 2 2006.201.07:23:37.99#ibcon#about to write, iclass 2, count 2 2006.201.07:23:37.99#ibcon#wrote, iclass 2, count 2 2006.201.07:23:37.99#ibcon#about to read 3, iclass 2, count 2 2006.201.07:23:38.02#ibcon#read 3, iclass 2, count 2 2006.201.07:23:38.02#ibcon#about to read 4, iclass 2, count 2 2006.201.07:23:38.02#ibcon#read 4, iclass 2, count 2 2006.201.07:23:38.02#ibcon#about to read 5, iclass 2, count 2 2006.201.07:23:38.02#ibcon#read 5, iclass 2, count 2 2006.201.07:23:38.02#ibcon#about to read 6, iclass 2, count 2 2006.201.07:23:38.02#ibcon#read 6, iclass 2, count 2 2006.201.07:23:38.02#ibcon#end of sib2, iclass 2, count 2 2006.201.07:23:38.02#ibcon#*after write, iclass 2, count 2 2006.201.07:23:38.02#ibcon#*before return 0, iclass 2, count 2 2006.201.07:23:38.02#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:38.02#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:38.02#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.07:23:38.02#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:38.02#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:38.14#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:38.14#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:38.14#ibcon#enter wrdev, iclass 2, count 0 2006.201.07:23:38.14#ibcon#first serial, iclass 2, count 0 2006.201.07:23:38.14#ibcon#enter sib2, iclass 2, count 0 2006.201.07:23:38.14#ibcon#flushed, iclass 2, count 0 2006.201.07:23:38.14#ibcon#about to write, iclass 2, count 0 2006.201.07:23:38.14#ibcon#wrote, iclass 2, count 0 2006.201.07:23:38.14#ibcon#about to read 3, iclass 2, count 0 2006.201.07:23:38.16#ibcon#read 3, iclass 2, count 0 2006.201.07:23:38.16#ibcon#about to read 4, iclass 2, count 0 2006.201.07:23:38.16#ibcon#read 4, iclass 2, count 0 2006.201.07:23:38.16#ibcon#about to read 5, iclass 2, count 0 2006.201.07:23:38.16#ibcon#read 5, iclass 2, count 0 2006.201.07:23:38.16#ibcon#about to read 6, iclass 2, count 0 2006.201.07:23:38.16#ibcon#read 6, iclass 2, count 0 2006.201.07:23:38.16#ibcon#end of sib2, iclass 2, count 0 2006.201.07:23:38.16#ibcon#*mode == 0, iclass 2, count 0 2006.201.07:23:38.16#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.07:23:38.16#ibcon#[25=USB\r\n] 2006.201.07:23:38.16#ibcon#*before write, iclass 2, count 0 2006.201.07:23:38.16#ibcon#enter sib2, iclass 2, count 0 2006.201.07:23:38.16#ibcon#flushed, iclass 2, count 0 2006.201.07:23:38.16#ibcon#about to write, iclass 2, count 0 2006.201.07:23:38.16#ibcon#wrote, iclass 2, count 0 2006.201.07:23:38.16#ibcon#about to read 3, iclass 2, count 0 2006.201.07:23:38.19#ibcon#read 3, iclass 2, count 0 2006.201.07:23:38.19#ibcon#about to read 4, iclass 2, count 0 2006.201.07:23:38.19#ibcon#read 4, iclass 2, count 0 2006.201.07:23:38.19#ibcon#about to read 5, iclass 2, count 0 2006.201.07:23:38.19#ibcon#read 5, iclass 2, count 0 2006.201.07:23:38.19#ibcon#about to read 6, iclass 2, count 0 2006.201.07:23:38.19#ibcon#read 6, iclass 2, count 0 2006.201.07:23:38.19#ibcon#end of sib2, iclass 2, count 0 2006.201.07:23:38.19#ibcon#*after write, iclass 2, count 0 2006.201.07:23:38.19#ibcon#*before return 0, iclass 2, count 0 2006.201.07:23:38.19#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:38.19#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:38.19#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.07:23:38.19#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.07:23:38.19$vck44/valo=5,734.99 2006.201.07:23:38.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.07:23:38.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.07:23:38.19#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:38.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:38.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:38.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:38.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.07:23:38.19#ibcon#first serial, iclass 5, count 0 2006.201.07:23:38.19#ibcon#enter sib2, iclass 5, count 0 2006.201.07:23:38.19#ibcon#flushed, iclass 5, count 0 2006.201.07:23:38.19#ibcon#about to write, iclass 5, count 0 2006.201.07:23:38.19#ibcon#wrote, iclass 5, count 0 2006.201.07:23:38.19#ibcon#about to read 3, iclass 5, count 0 2006.201.07:23:38.21#ibcon#read 3, iclass 5, count 0 2006.201.07:23:38.21#ibcon#about to read 4, iclass 5, count 0 2006.201.07:23:38.21#ibcon#read 4, iclass 5, count 0 2006.201.07:23:38.21#ibcon#about to read 5, iclass 5, count 0 2006.201.07:23:38.21#ibcon#read 5, iclass 5, count 0 2006.201.07:23:38.21#ibcon#about to read 6, iclass 5, count 0 2006.201.07:23:38.21#ibcon#read 6, iclass 5, count 0 2006.201.07:23:38.21#ibcon#end of sib2, iclass 5, count 0 2006.201.07:23:38.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.07:23:38.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.07:23:38.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:23:38.21#ibcon#*before write, iclass 5, count 0 2006.201.07:23:38.21#ibcon#enter sib2, iclass 5, count 0 2006.201.07:23:38.21#ibcon#flushed, iclass 5, count 0 2006.201.07:23:38.21#ibcon#about to write, iclass 5, count 0 2006.201.07:23:38.21#ibcon#wrote, iclass 5, count 0 2006.201.07:23:38.21#ibcon#about to read 3, iclass 5, count 0 2006.201.07:23:38.25#ibcon#read 3, iclass 5, count 0 2006.201.07:23:38.25#ibcon#about to read 4, iclass 5, count 0 2006.201.07:23:38.25#ibcon#read 4, iclass 5, count 0 2006.201.07:23:38.25#ibcon#about to read 5, iclass 5, count 0 2006.201.07:23:38.25#ibcon#read 5, iclass 5, count 0 2006.201.07:23:38.25#ibcon#about to read 6, iclass 5, count 0 2006.201.07:23:38.25#ibcon#read 6, iclass 5, count 0 2006.201.07:23:38.25#ibcon#end of sib2, iclass 5, count 0 2006.201.07:23:38.25#ibcon#*after write, iclass 5, count 0 2006.201.07:23:38.25#ibcon#*before return 0, iclass 5, count 0 2006.201.07:23:38.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:38.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:38.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.07:23:38.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.07:23:38.25$vck44/va=5,4 2006.201.07:23:38.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.07:23:38.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.07:23:38.25#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:38.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:38.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:38.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:38.31#ibcon#enter wrdev, iclass 7, count 2 2006.201.07:23:38.31#ibcon#first serial, iclass 7, count 2 2006.201.07:23:38.31#ibcon#enter sib2, iclass 7, count 2 2006.201.07:23:38.31#ibcon#flushed, iclass 7, count 2 2006.201.07:23:38.31#ibcon#about to write, iclass 7, count 2 2006.201.07:23:38.31#ibcon#wrote, iclass 7, count 2 2006.201.07:23:38.31#ibcon#about to read 3, iclass 7, count 2 2006.201.07:23:38.33#ibcon#read 3, iclass 7, count 2 2006.201.07:23:38.33#ibcon#about to read 4, iclass 7, count 2 2006.201.07:23:38.33#ibcon#read 4, iclass 7, count 2 2006.201.07:23:38.33#ibcon#about to read 5, iclass 7, count 2 2006.201.07:23:38.33#ibcon#read 5, iclass 7, count 2 2006.201.07:23:38.33#ibcon#about to read 6, iclass 7, count 2 2006.201.07:23:38.33#ibcon#read 6, iclass 7, count 2 2006.201.07:23:38.33#ibcon#end of sib2, iclass 7, count 2 2006.201.07:23:38.33#ibcon#*mode == 0, iclass 7, count 2 2006.201.07:23:38.33#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.07:23:38.33#ibcon#[25=AT05-04\r\n] 2006.201.07:23:38.33#ibcon#*before write, iclass 7, count 2 2006.201.07:23:38.33#ibcon#enter sib2, iclass 7, count 2 2006.201.07:23:38.33#ibcon#flushed, iclass 7, count 2 2006.201.07:23:38.33#ibcon#about to write, iclass 7, count 2 2006.201.07:23:38.33#ibcon#wrote, iclass 7, count 2 2006.201.07:23:38.33#ibcon#about to read 3, iclass 7, count 2 2006.201.07:23:38.36#ibcon#read 3, iclass 7, count 2 2006.201.07:23:38.36#ibcon#about to read 4, iclass 7, count 2 2006.201.07:23:38.36#ibcon#read 4, iclass 7, count 2 2006.201.07:23:38.36#ibcon#about to read 5, iclass 7, count 2 2006.201.07:23:38.36#ibcon#read 5, iclass 7, count 2 2006.201.07:23:38.36#ibcon#about to read 6, iclass 7, count 2 2006.201.07:23:38.36#ibcon#read 6, iclass 7, count 2 2006.201.07:23:38.36#ibcon#end of sib2, iclass 7, count 2 2006.201.07:23:38.36#ibcon#*after write, iclass 7, count 2 2006.201.07:23:38.36#ibcon#*before return 0, iclass 7, count 2 2006.201.07:23:38.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:38.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:38.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.07:23:38.36#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:38.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:38.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:38.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:38.48#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:23:38.48#ibcon#first serial, iclass 7, count 0 2006.201.07:23:38.48#ibcon#enter sib2, iclass 7, count 0 2006.201.07:23:38.48#ibcon#flushed, iclass 7, count 0 2006.201.07:23:38.48#ibcon#about to write, iclass 7, count 0 2006.201.07:23:38.48#ibcon#wrote, iclass 7, count 0 2006.201.07:23:38.48#ibcon#about to read 3, iclass 7, count 0 2006.201.07:23:38.50#ibcon#read 3, iclass 7, count 0 2006.201.07:23:38.50#ibcon#about to read 4, iclass 7, count 0 2006.201.07:23:38.50#ibcon#read 4, iclass 7, count 0 2006.201.07:23:38.50#ibcon#about to read 5, iclass 7, count 0 2006.201.07:23:38.50#ibcon#read 5, iclass 7, count 0 2006.201.07:23:38.50#ibcon#about to read 6, iclass 7, count 0 2006.201.07:23:38.50#ibcon#read 6, iclass 7, count 0 2006.201.07:23:38.50#ibcon#end of sib2, iclass 7, count 0 2006.201.07:23:38.50#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:23:38.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:23:38.50#ibcon#[25=USB\r\n] 2006.201.07:23:38.50#ibcon#*before write, iclass 7, count 0 2006.201.07:23:38.50#ibcon#enter sib2, iclass 7, count 0 2006.201.07:23:38.50#ibcon#flushed, iclass 7, count 0 2006.201.07:23:38.50#ibcon#about to write, iclass 7, count 0 2006.201.07:23:38.50#ibcon#wrote, iclass 7, count 0 2006.201.07:23:38.50#ibcon#about to read 3, iclass 7, count 0 2006.201.07:23:38.53#ibcon#read 3, iclass 7, count 0 2006.201.07:23:38.53#ibcon#about to read 4, iclass 7, count 0 2006.201.07:23:38.53#ibcon#read 4, iclass 7, count 0 2006.201.07:23:38.53#ibcon#about to read 5, iclass 7, count 0 2006.201.07:23:38.53#ibcon#read 5, iclass 7, count 0 2006.201.07:23:38.53#ibcon#about to read 6, iclass 7, count 0 2006.201.07:23:38.53#ibcon#read 6, iclass 7, count 0 2006.201.07:23:38.53#ibcon#end of sib2, iclass 7, count 0 2006.201.07:23:38.53#ibcon#*after write, iclass 7, count 0 2006.201.07:23:38.53#ibcon#*before return 0, iclass 7, count 0 2006.201.07:23:38.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:38.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:38.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:23:38.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:23:38.53$vck44/valo=6,814.99 2006.201.07:23:38.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.07:23:38.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.07:23:38.53#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:38.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:38.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:38.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:38.53#ibcon#enter wrdev, iclass 11, count 0 2006.201.07:23:38.53#ibcon#first serial, iclass 11, count 0 2006.201.07:23:38.53#ibcon#enter sib2, iclass 11, count 0 2006.201.07:23:38.53#ibcon#flushed, iclass 11, count 0 2006.201.07:23:38.53#ibcon#about to write, iclass 11, count 0 2006.201.07:23:38.53#ibcon#wrote, iclass 11, count 0 2006.201.07:23:38.53#ibcon#about to read 3, iclass 11, count 0 2006.201.07:23:38.55#ibcon#read 3, iclass 11, count 0 2006.201.07:23:38.55#ibcon#about to read 4, iclass 11, count 0 2006.201.07:23:38.55#ibcon#read 4, iclass 11, count 0 2006.201.07:23:38.55#ibcon#about to read 5, iclass 11, count 0 2006.201.07:23:38.55#ibcon#read 5, iclass 11, count 0 2006.201.07:23:38.55#ibcon#about to read 6, iclass 11, count 0 2006.201.07:23:38.55#ibcon#read 6, iclass 11, count 0 2006.201.07:23:38.55#ibcon#end of sib2, iclass 11, count 0 2006.201.07:23:38.55#ibcon#*mode == 0, iclass 11, count 0 2006.201.07:23:38.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.07:23:38.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:23:38.55#ibcon#*before write, iclass 11, count 0 2006.201.07:23:38.55#ibcon#enter sib2, iclass 11, count 0 2006.201.07:23:38.55#ibcon#flushed, iclass 11, count 0 2006.201.07:23:38.55#ibcon#about to write, iclass 11, count 0 2006.201.07:23:38.55#ibcon#wrote, iclass 11, count 0 2006.201.07:23:38.55#ibcon#about to read 3, iclass 11, count 0 2006.201.07:23:38.59#ibcon#read 3, iclass 11, count 0 2006.201.07:23:38.59#ibcon#about to read 4, iclass 11, count 0 2006.201.07:23:38.59#ibcon#read 4, iclass 11, count 0 2006.201.07:23:38.59#ibcon#about to read 5, iclass 11, count 0 2006.201.07:23:38.59#ibcon#read 5, iclass 11, count 0 2006.201.07:23:38.59#ibcon#about to read 6, iclass 11, count 0 2006.201.07:23:38.59#ibcon#read 6, iclass 11, count 0 2006.201.07:23:38.59#ibcon#end of sib2, iclass 11, count 0 2006.201.07:23:38.59#ibcon#*after write, iclass 11, count 0 2006.201.07:23:38.59#ibcon#*before return 0, iclass 11, count 0 2006.201.07:23:38.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:38.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:38.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.07:23:38.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.07:23:38.59$vck44/va=6,5 2006.201.07:23:38.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.07:23:38.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.07:23:38.59#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:38.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:38.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:38.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:38.65#ibcon#enter wrdev, iclass 13, count 2 2006.201.07:23:38.65#ibcon#first serial, iclass 13, count 2 2006.201.07:23:38.65#ibcon#enter sib2, iclass 13, count 2 2006.201.07:23:38.65#ibcon#flushed, iclass 13, count 2 2006.201.07:23:38.65#ibcon#about to write, iclass 13, count 2 2006.201.07:23:38.65#ibcon#wrote, iclass 13, count 2 2006.201.07:23:38.65#ibcon#about to read 3, iclass 13, count 2 2006.201.07:23:38.67#ibcon#read 3, iclass 13, count 2 2006.201.07:23:38.67#ibcon#about to read 4, iclass 13, count 2 2006.201.07:23:38.67#ibcon#read 4, iclass 13, count 2 2006.201.07:23:38.67#ibcon#about to read 5, iclass 13, count 2 2006.201.07:23:38.67#ibcon#read 5, iclass 13, count 2 2006.201.07:23:38.67#ibcon#about to read 6, iclass 13, count 2 2006.201.07:23:38.67#ibcon#read 6, iclass 13, count 2 2006.201.07:23:38.67#ibcon#end of sib2, iclass 13, count 2 2006.201.07:23:38.67#ibcon#*mode == 0, iclass 13, count 2 2006.201.07:23:38.67#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.07:23:38.67#ibcon#[25=AT06-05\r\n] 2006.201.07:23:38.67#ibcon#*before write, iclass 13, count 2 2006.201.07:23:38.67#ibcon#enter sib2, iclass 13, count 2 2006.201.07:23:38.67#ibcon#flushed, iclass 13, count 2 2006.201.07:23:38.67#ibcon#about to write, iclass 13, count 2 2006.201.07:23:38.67#ibcon#wrote, iclass 13, count 2 2006.201.07:23:38.67#ibcon#about to read 3, iclass 13, count 2 2006.201.07:23:38.70#ibcon#read 3, iclass 13, count 2 2006.201.07:23:38.70#ibcon#about to read 4, iclass 13, count 2 2006.201.07:23:38.70#ibcon#read 4, iclass 13, count 2 2006.201.07:23:38.70#ibcon#about to read 5, iclass 13, count 2 2006.201.07:23:38.70#ibcon#read 5, iclass 13, count 2 2006.201.07:23:38.70#ibcon#about to read 6, iclass 13, count 2 2006.201.07:23:38.70#ibcon#read 6, iclass 13, count 2 2006.201.07:23:38.70#ibcon#end of sib2, iclass 13, count 2 2006.201.07:23:38.70#ibcon#*after write, iclass 13, count 2 2006.201.07:23:38.70#ibcon#*before return 0, iclass 13, count 2 2006.201.07:23:38.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:38.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:38.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.07:23:38.70#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:38.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:38.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:38.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:38.82#ibcon#enter wrdev, iclass 13, count 0 2006.201.07:23:38.82#ibcon#first serial, iclass 13, count 0 2006.201.07:23:38.82#ibcon#enter sib2, iclass 13, count 0 2006.201.07:23:38.82#ibcon#flushed, iclass 13, count 0 2006.201.07:23:38.82#ibcon#about to write, iclass 13, count 0 2006.201.07:23:38.82#ibcon#wrote, iclass 13, count 0 2006.201.07:23:38.82#ibcon#about to read 3, iclass 13, count 0 2006.201.07:23:38.84#ibcon#read 3, iclass 13, count 0 2006.201.07:23:38.84#ibcon#about to read 4, iclass 13, count 0 2006.201.07:23:38.84#ibcon#read 4, iclass 13, count 0 2006.201.07:23:38.84#ibcon#about to read 5, iclass 13, count 0 2006.201.07:23:38.84#ibcon#read 5, iclass 13, count 0 2006.201.07:23:38.84#ibcon#about to read 6, iclass 13, count 0 2006.201.07:23:38.84#ibcon#read 6, iclass 13, count 0 2006.201.07:23:38.84#ibcon#end of sib2, iclass 13, count 0 2006.201.07:23:38.84#ibcon#*mode == 0, iclass 13, count 0 2006.201.07:23:38.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.07:23:38.84#ibcon#[25=USB\r\n] 2006.201.07:23:38.84#ibcon#*before write, iclass 13, count 0 2006.201.07:23:38.84#ibcon#enter sib2, iclass 13, count 0 2006.201.07:23:38.84#ibcon#flushed, iclass 13, count 0 2006.201.07:23:38.84#ibcon#about to write, iclass 13, count 0 2006.201.07:23:38.84#ibcon#wrote, iclass 13, count 0 2006.201.07:23:38.84#ibcon#about to read 3, iclass 13, count 0 2006.201.07:23:38.87#ibcon#read 3, iclass 13, count 0 2006.201.07:23:38.87#ibcon#about to read 4, iclass 13, count 0 2006.201.07:23:38.87#ibcon#read 4, iclass 13, count 0 2006.201.07:23:38.87#ibcon#about to read 5, iclass 13, count 0 2006.201.07:23:38.87#ibcon#read 5, iclass 13, count 0 2006.201.07:23:38.87#ibcon#about to read 6, iclass 13, count 0 2006.201.07:23:38.87#ibcon#read 6, iclass 13, count 0 2006.201.07:23:38.87#ibcon#end of sib2, iclass 13, count 0 2006.201.07:23:38.87#ibcon#*after write, iclass 13, count 0 2006.201.07:23:38.87#ibcon#*before return 0, iclass 13, count 0 2006.201.07:23:38.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:38.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:38.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.07:23:38.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.07:23:38.87$vck44/valo=7,864.99 2006.201.07:23:38.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.07:23:38.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.07:23:38.87#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:38.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:38.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:38.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:38.87#ibcon#enter wrdev, iclass 15, count 0 2006.201.07:23:38.87#ibcon#first serial, iclass 15, count 0 2006.201.07:23:38.87#ibcon#enter sib2, iclass 15, count 0 2006.201.07:23:38.87#ibcon#flushed, iclass 15, count 0 2006.201.07:23:38.87#ibcon#about to write, iclass 15, count 0 2006.201.07:23:38.87#ibcon#wrote, iclass 15, count 0 2006.201.07:23:38.87#ibcon#about to read 3, iclass 15, count 0 2006.201.07:23:38.89#ibcon#read 3, iclass 15, count 0 2006.201.07:23:38.89#ibcon#about to read 4, iclass 15, count 0 2006.201.07:23:38.89#ibcon#read 4, iclass 15, count 0 2006.201.07:23:38.89#ibcon#about to read 5, iclass 15, count 0 2006.201.07:23:38.89#ibcon#read 5, iclass 15, count 0 2006.201.07:23:38.89#ibcon#about to read 6, iclass 15, count 0 2006.201.07:23:38.89#ibcon#read 6, iclass 15, count 0 2006.201.07:23:38.89#ibcon#end of sib2, iclass 15, count 0 2006.201.07:23:38.89#ibcon#*mode == 0, iclass 15, count 0 2006.201.07:23:38.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.07:23:38.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:23:38.89#ibcon#*before write, iclass 15, count 0 2006.201.07:23:38.89#ibcon#enter sib2, iclass 15, count 0 2006.201.07:23:38.89#ibcon#flushed, iclass 15, count 0 2006.201.07:23:38.89#ibcon#about to write, iclass 15, count 0 2006.201.07:23:38.89#ibcon#wrote, iclass 15, count 0 2006.201.07:23:38.89#ibcon#about to read 3, iclass 15, count 0 2006.201.07:23:38.93#ibcon#read 3, iclass 15, count 0 2006.201.07:23:38.93#ibcon#about to read 4, iclass 15, count 0 2006.201.07:23:38.93#ibcon#read 4, iclass 15, count 0 2006.201.07:23:38.93#ibcon#about to read 5, iclass 15, count 0 2006.201.07:23:38.93#ibcon#read 5, iclass 15, count 0 2006.201.07:23:38.93#ibcon#about to read 6, iclass 15, count 0 2006.201.07:23:38.93#ibcon#read 6, iclass 15, count 0 2006.201.07:23:38.93#ibcon#end of sib2, iclass 15, count 0 2006.201.07:23:38.93#ibcon#*after write, iclass 15, count 0 2006.201.07:23:38.93#ibcon#*before return 0, iclass 15, count 0 2006.201.07:23:38.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:38.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:38.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.07:23:38.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.07:23:38.93$vck44/va=7,5 2006.201.07:23:38.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.07:23:38.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.07:23:38.93#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:38.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:38.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:38.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:38.99#ibcon#enter wrdev, iclass 17, count 2 2006.201.07:23:38.99#ibcon#first serial, iclass 17, count 2 2006.201.07:23:38.99#ibcon#enter sib2, iclass 17, count 2 2006.201.07:23:38.99#ibcon#flushed, iclass 17, count 2 2006.201.07:23:38.99#ibcon#about to write, iclass 17, count 2 2006.201.07:23:38.99#ibcon#wrote, iclass 17, count 2 2006.201.07:23:38.99#ibcon#about to read 3, iclass 17, count 2 2006.201.07:23:39.01#ibcon#read 3, iclass 17, count 2 2006.201.07:23:39.01#ibcon#about to read 4, iclass 17, count 2 2006.201.07:23:39.01#ibcon#read 4, iclass 17, count 2 2006.201.07:23:39.01#ibcon#about to read 5, iclass 17, count 2 2006.201.07:23:39.01#ibcon#read 5, iclass 17, count 2 2006.201.07:23:39.01#ibcon#about to read 6, iclass 17, count 2 2006.201.07:23:39.01#ibcon#read 6, iclass 17, count 2 2006.201.07:23:39.01#ibcon#end of sib2, iclass 17, count 2 2006.201.07:23:39.01#ibcon#*mode == 0, iclass 17, count 2 2006.201.07:23:39.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.07:23:39.01#ibcon#[25=AT07-05\r\n] 2006.201.07:23:39.01#ibcon#*before write, iclass 17, count 2 2006.201.07:23:39.01#ibcon#enter sib2, iclass 17, count 2 2006.201.07:23:39.01#ibcon#flushed, iclass 17, count 2 2006.201.07:23:39.01#ibcon#about to write, iclass 17, count 2 2006.201.07:23:39.01#ibcon#wrote, iclass 17, count 2 2006.201.07:23:39.01#ibcon#about to read 3, iclass 17, count 2 2006.201.07:23:39.04#ibcon#read 3, iclass 17, count 2 2006.201.07:23:39.04#ibcon#about to read 4, iclass 17, count 2 2006.201.07:23:39.04#ibcon#read 4, iclass 17, count 2 2006.201.07:23:39.04#ibcon#about to read 5, iclass 17, count 2 2006.201.07:23:39.04#ibcon#read 5, iclass 17, count 2 2006.201.07:23:39.04#ibcon#about to read 6, iclass 17, count 2 2006.201.07:23:39.04#ibcon#read 6, iclass 17, count 2 2006.201.07:23:39.04#ibcon#end of sib2, iclass 17, count 2 2006.201.07:23:39.04#ibcon#*after write, iclass 17, count 2 2006.201.07:23:39.04#ibcon#*before return 0, iclass 17, count 2 2006.201.07:23:39.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:39.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:39.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.07:23:39.04#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:39.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:39.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:39.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:39.16#ibcon#enter wrdev, iclass 17, count 0 2006.201.07:23:39.16#ibcon#first serial, iclass 17, count 0 2006.201.07:23:39.16#ibcon#enter sib2, iclass 17, count 0 2006.201.07:23:39.16#ibcon#flushed, iclass 17, count 0 2006.201.07:23:39.16#ibcon#about to write, iclass 17, count 0 2006.201.07:23:39.16#ibcon#wrote, iclass 17, count 0 2006.201.07:23:39.16#ibcon#about to read 3, iclass 17, count 0 2006.201.07:23:39.18#ibcon#read 3, iclass 17, count 0 2006.201.07:23:39.18#ibcon#about to read 4, iclass 17, count 0 2006.201.07:23:39.18#ibcon#read 4, iclass 17, count 0 2006.201.07:23:39.18#ibcon#about to read 5, iclass 17, count 0 2006.201.07:23:39.18#ibcon#read 5, iclass 17, count 0 2006.201.07:23:39.18#ibcon#about to read 6, iclass 17, count 0 2006.201.07:23:39.18#ibcon#read 6, iclass 17, count 0 2006.201.07:23:39.18#ibcon#end of sib2, iclass 17, count 0 2006.201.07:23:39.18#ibcon#*mode == 0, iclass 17, count 0 2006.201.07:23:39.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.07:23:39.18#ibcon#[25=USB\r\n] 2006.201.07:23:39.18#ibcon#*before write, iclass 17, count 0 2006.201.07:23:39.18#ibcon#enter sib2, iclass 17, count 0 2006.201.07:23:39.18#ibcon#flushed, iclass 17, count 0 2006.201.07:23:39.18#ibcon#about to write, iclass 17, count 0 2006.201.07:23:39.18#ibcon#wrote, iclass 17, count 0 2006.201.07:23:39.18#ibcon#about to read 3, iclass 17, count 0 2006.201.07:23:39.21#ibcon#read 3, iclass 17, count 0 2006.201.07:23:39.21#ibcon#about to read 4, iclass 17, count 0 2006.201.07:23:39.21#ibcon#read 4, iclass 17, count 0 2006.201.07:23:39.21#ibcon#about to read 5, iclass 17, count 0 2006.201.07:23:39.21#ibcon#read 5, iclass 17, count 0 2006.201.07:23:39.21#ibcon#about to read 6, iclass 17, count 0 2006.201.07:23:39.21#ibcon#read 6, iclass 17, count 0 2006.201.07:23:39.21#ibcon#end of sib2, iclass 17, count 0 2006.201.07:23:39.21#ibcon#*after write, iclass 17, count 0 2006.201.07:23:39.21#ibcon#*before return 0, iclass 17, count 0 2006.201.07:23:39.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:39.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:39.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.07:23:39.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.07:23:39.21$vck44/valo=8,884.99 2006.201.07:23:39.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.07:23:39.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.07:23:39.21#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:39.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:23:39.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:23:39.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:23:39.21#ibcon#enter wrdev, iclass 19, count 0 2006.201.07:23:39.21#ibcon#first serial, iclass 19, count 0 2006.201.07:23:39.21#ibcon#enter sib2, iclass 19, count 0 2006.201.07:23:39.21#ibcon#flushed, iclass 19, count 0 2006.201.07:23:39.21#ibcon#about to write, iclass 19, count 0 2006.201.07:23:39.21#ibcon#wrote, iclass 19, count 0 2006.201.07:23:39.21#ibcon#about to read 3, iclass 19, count 0 2006.201.07:23:39.23#ibcon#read 3, iclass 19, count 0 2006.201.07:23:39.23#ibcon#about to read 4, iclass 19, count 0 2006.201.07:23:39.23#ibcon#read 4, iclass 19, count 0 2006.201.07:23:39.23#ibcon#about to read 5, iclass 19, count 0 2006.201.07:23:39.23#ibcon#read 5, iclass 19, count 0 2006.201.07:23:39.23#ibcon#about to read 6, iclass 19, count 0 2006.201.07:23:39.23#ibcon#read 6, iclass 19, count 0 2006.201.07:23:39.23#ibcon#end of sib2, iclass 19, count 0 2006.201.07:23:39.23#ibcon#*mode == 0, iclass 19, count 0 2006.201.07:23:39.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.07:23:39.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:23:39.23#ibcon#*before write, iclass 19, count 0 2006.201.07:23:39.23#ibcon#enter sib2, iclass 19, count 0 2006.201.07:23:39.23#ibcon#flushed, iclass 19, count 0 2006.201.07:23:39.23#ibcon#about to write, iclass 19, count 0 2006.201.07:23:39.23#ibcon#wrote, iclass 19, count 0 2006.201.07:23:39.23#ibcon#about to read 3, iclass 19, count 0 2006.201.07:23:39.27#ibcon#read 3, iclass 19, count 0 2006.201.07:23:39.27#ibcon#about to read 4, iclass 19, count 0 2006.201.07:23:39.27#ibcon#read 4, iclass 19, count 0 2006.201.07:23:39.27#ibcon#about to read 5, iclass 19, count 0 2006.201.07:23:39.27#ibcon#read 5, iclass 19, count 0 2006.201.07:23:39.27#ibcon#about to read 6, iclass 19, count 0 2006.201.07:23:39.27#ibcon#read 6, iclass 19, count 0 2006.201.07:23:39.27#ibcon#end of sib2, iclass 19, count 0 2006.201.07:23:39.27#ibcon#*after write, iclass 19, count 0 2006.201.07:23:39.27#ibcon#*before return 0, iclass 19, count 0 2006.201.07:23:39.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:23:39.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.07:23:39.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.07:23:39.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.07:23:39.27$vck44/va=8,4 2006.201.07:23:39.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.07:23:39.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.07:23:39.27#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:39.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:23:39.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:23:39.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:23:39.33#ibcon#enter wrdev, iclass 21, count 2 2006.201.07:23:39.33#ibcon#first serial, iclass 21, count 2 2006.201.07:23:39.33#ibcon#enter sib2, iclass 21, count 2 2006.201.07:23:39.33#ibcon#flushed, iclass 21, count 2 2006.201.07:23:39.33#ibcon#about to write, iclass 21, count 2 2006.201.07:23:39.33#ibcon#wrote, iclass 21, count 2 2006.201.07:23:39.33#ibcon#about to read 3, iclass 21, count 2 2006.201.07:23:39.35#ibcon#read 3, iclass 21, count 2 2006.201.07:23:39.35#ibcon#about to read 4, iclass 21, count 2 2006.201.07:23:39.35#ibcon#read 4, iclass 21, count 2 2006.201.07:23:39.35#ibcon#about to read 5, iclass 21, count 2 2006.201.07:23:39.35#ibcon#read 5, iclass 21, count 2 2006.201.07:23:39.35#ibcon#about to read 6, iclass 21, count 2 2006.201.07:23:39.35#ibcon#read 6, iclass 21, count 2 2006.201.07:23:39.35#ibcon#end of sib2, iclass 21, count 2 2006.201.07:23:39.35#ibcon#*mode == 0, iclass 21, count 2 2006.201.07:23:39.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.07:23:39.35#ibcon#[25=AT08-04\r\n] 2006.201.07:23:39.35#ibcon#*before write, iclass 21, count 2 2006.201.07:23:39.35#ibcon#enter sib2, iclass 21, count 2 2006.201.07:23:39.35#ibcon#flushed, iclass 21, count 2 2006.201.07:23:39.35#ibcon#about to write, iclass 21, count 2 2006.201.07:23:39.35#ibcon#wrote, iclass 21, count 2 2006.201.07:23:39.35#ibcon#about to read 3, iclass 21, count 2 2006.201.07:23:39.38#ibcon#read 3, iclass 21, count 2 2006.201.07:23:39.38#ibcon#about to read 4, iclass 21, count 2 2006.201.07:23:39.38#ibcon#read 4, iclass 21, count 2 2006.201.07:23:39.38#ibcon#about to read 5, iclass 21, count 2 2006.201.07:23:39.38#ibcon#read 5, iclass 21, count 2 2006.201.07:23:39.38#ibcon#about to read 6, iclass 21, count 2 2006.201.07:23:39.38#ibcon#read 6, iclass 21, count 2 2006.201.07:23:39.38#ibcon#end of sib2, iclass 21, count 2 2006.201.07:23:39.38#ibcon#*after write, iclass 21, count 2 2006.201.07:23:39.38#ibcon#*before return 0, iclass 21, count 2 2006.201.07:23:39.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:23:39.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.07:23:39.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.07:23:39.38#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:39.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:23:39.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:23:39.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:23:39.50#ibcon#enter wrdev, iclass 21, count 0 2006.201.07:23:39.50#ibcon#first serial, iclass 21, count 0 2006.201.07:23:39.50#ibcon#enter sib2, iclass 21, count 0 2006.201.07:23:39.50#ibcon#flushed, iclass 21, count 0 2006.201.07:23:39.50#ibcon#about to write, iclass 21, count 0 2006.201.07:23:39.50#ibcon#wrote, iclass 21, count 0 2006.201.07:23:39.50#ibcon#about to read 3, iclass 21, count 0 2006.201.07:23:39.52#ibcon#read 3, iclass 21, count 0 2006.201.07:23:39.52#ibcon#about to read 4, iclass 21, count 0 2006.201.07:23:39.52#ibcon#read 4, iclass 21, count 0 2006.201.07:23:39.52#ibcon#about to read 5, iclass 21, count 0 2006.201.07:23:39.52#ibcon#read 5, iclass 21, count 0 2006.201.07:23:39.52#ibcon#about to read 6, iclass 21, count 0 2006.201.07:23:39.52#ibcon#read 6, iclass 21, count 0 2006.201.07:23:39.52#ibcon#end of sib2, iclass 21, count 0 2006.201.07:23:39.52#ibcon#*mode == 0, iclass 21, count 0 2006.201.07:23:39.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.07:23:39.52#ibcon#[25=USB\r\n] 2006.201.07:23:39.52#ibcon#*before write, iclass 21, count 0 2006.201.07:23:39.52#ibcon#enter sib2, iclass 21, count 0 2006.201.07:23:39.52#ibcon#flushed, iclass 21, count 0 2006.201.07:23:39.52#ibcon#about to write, iclass 21, count 0 2006.201.07:23:39.52#ibcon#wrote, iclass 21, count 0 2006.201.07:23:39.52#ibcon#about to read 3, iclass 21, count 0 2006.201.07:23:39.55#ibcon#read 3, iclass 21, count 0 2006.201.07:23:39.55#ibcon#about to read 4, iclass 21, count 0 2006.201.07:23:39.55#ibcon#read 4, iclass 21, count 0 2006.201.07:23:39.55#ibcon#about to read 5, iclass 21, count 0 2006.201.07:23:39.55#ibcon#read 5, iclass 21, count 0 2006.201.07:23:39.55#ibcon#about to read 6, iclass 21, count 0 2006.201.07:23:39.55#ibcon#read 6, iclass 21, count 0 2006.201.07:23:39.55#ibcon#end of sib2, iclass 21, count 0 2006.201.07:23:39.55#ibcon#*after write, iclass 21, count 0 2006.201.07:23:39.55#ibcon#*before return 0, iclass 21, count 0 2006.201.07:23:39.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:23:39.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.07:23:39.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.07:23:39.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.07:23:39.55$vck44/vblo=1,629.99 2006.201.07:23:39.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.07:23:39.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.07:23:39.55#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:39.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:23:39.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:23:39.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:23:39.55#ibcon#enter wrdev, iclass 23, count 0 2006.201.07:23:39.55#ibcon#first serial, iclass 23, count 0 2006.201.07:23:39.55#ibcon#enter sib2, iclass 23, count 0 2006.201.07:23:39.55#ibcon#flushed, iclass 23, count 0 2006.201.07:23:39.55#ibcon#about to write, iclass 23, count 0 2006.201.07:23:39.55#ibcon#wrote, iclass 23, count 0 2006.201.07:23:39.55#ibcon#about to read 3, iclass 23, count 0 2006.201.07:23:39.57#ibcon#read 3, iclass 23, count 0 2006.201.07:23:39.57#ibcon#about to read 4, iclass 23, count 0 2006.201.07:23:39.57#ibcon#read 4, iclass 23, count 0 2006.201.07:23:39.57#ibcon#about to read 5, iclass 23, count 0 2006.201.07:23:39.57#ibcon#read 5, iclass 23, count 0 2006.201.07:23:39.57#ibcon#about to read 6, iclass 23, count 0 2006.201.07:23:39.57#ibcon#read 6, iclass 23, count 0 2006.201.07:23:39.57#ibcon#end of sib2, iclass 23, count 0 2006.201.07:23:39.57#ibcon#*mode == 0, iclass 23, count 0 2006.201.07:23:39.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.07:23:39.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:23:39.57#ibcon#*before write, iclass 23, count 0 2006.201.07:23:39.57#ibcon#enter sib2, iclass 23, count 0 2006.201.07:23:39.57#ibcon#flushed, iclass 23, count 0 2006.201.07:23:39.57#ibcon#about to write, iclass 23, count 0 2006.201.07:23:39.57#ibcon#wrote, iclass 23, count 0 2006.201.07:23:39.57#ibcon#about to read 3, iclass 23, count 0 2006.201.07:23:39.62#ibcon#read 3, iclass 23, count 0 2006.201.07:23:39.62#ibcon#about to read 4, iclass 23, count 0 2006.201.07:23:39.62#ibcon#read 4, iclass 23, count 0 2006.201.07:23:39.62#ibcon#about to read 5, iclass 23, count 0 2006.201.07:23:39.62#ibcon#read 5, iclass 23, count 0 2006.201.07:23:39.62#ibcon#about to read 6, iclass 23, count 0 2006.201.07:23:39.62#ibcon#read 6, iclass 23, count 0 2006.201.07:23:39.62#ibcon#end of sib2, iclass 23, count 0 2006.201.07:23:39.62#ibcon#*after write, iclass 23, count 0 2006.201.07:23:39.62#ibcon#*before return 0, iclass 23, count 0 2006.201.07:23:39.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:23:39.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.07:23:39.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.07:23:39.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.07:23:39.62$vck44/vb=1,4 2006.201.07:23:39.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.07:23:39.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.07:23:39.62#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:39.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:23:39.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:23:39.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:23:39.62#ibcon#enter wrdev, iclass 25, count 2 2006.201.07:23:39.62#ibcon#first serial, iclass 25, count 2 2006.201.07:23:39.62#ibcon#enter sib2, iclass 25, count 2 2006.201.07:23:39.62#ibcon#flushed, iclass 25, count 2 2006.201.07:23:39.62#ibcon#about to write, iclass 25, count 2 2006.201.07:23:39.62#ibcon#wrote, iclass 25, count 2 2006.201.07:23:39.62#ibcon#about to read 3, iclass 25, count 2 2006.201.07:23:39.64#ibcon#read 3, iclass 25, count 2 2006.201.07:23:39.64#ibcon#about to read 4, iclass 25, count 2 2006.201.07:23:39.64#ibcon#read 4, iclass 25, count 2 2006.201.07:23:39.64#ibcon#about to read 5, iclass 25, count 2 2006.201.07:23:39.64#ibcon#read 5, iclass 25, count 2 2006.201.07:23:39.64#ibcon#about to read 6, iclass 25, count 2 2006.201.07:23:39.64#ibcon#read 6, iclass 25, count 2 2006.201.07:23:39.64#ibcon#end of sib2, iclass 25, count 2 2006.201.07:23:39.64#ibcon#*mode == 0, iclass 25, count 2 2006.201.07:23:39.64#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.07:23:39.64#ibcon#[27=AT01-04\r\n] 2006.201.07:23:39.64#ibcon#*before write, iclass 25, count 2 2006.201.07:23:39.64#ibcon#enter sib2, iclass 25, count 2 2006.201.07:23:39.64#ibcon#flushed, iclass 25, count 2 2006.201.07:23:39.64#ibcon#about to write, iclass 25, count 2 2006.201.07:23:39.64#ibcon#wrote, iclass 25, count 2 2006.201.07:23:39.64#ibcon#about to read 3, iclass 25, count 2 2006.201.07:23:39.67#ibcon#read 3, iclass 25, count 2 2006.201.07:23:39.67#ibcon#about to read 4, iclass 25, count 2 2006.201.07:23:39.67#ibcon#read 4, iclass 25, count 2 2006.201.07:23:39.67#ibcon#about to read 5, iclass 25, count 2 2006.201.07:23:39.67#ibcon#read 5, iclass 25, count 2 2006.201.07:23:39.67#ibcon#about to read 6, iclass 25, count 2 2006.201.07:23:39.67#ibcon#read 6, iclass 25, count 2 2006.201.07:23:39.67#ibcon#end of sib2, iclass 25, count 2 2006.201.07:23:39.67#ibcon#*after write, iclass 25, count 2 2006.201.07:23:39.67#ibcon#*before return 0, iclass 25, count 2 2006.201.07:23:39.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:23:39.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.07:23:39.67#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.07:23:39.67#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:39.67#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:23:39.79#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:23:39.79#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:23:39.79#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:23:39.79#ibcon#first serial, iclass 25, count 0 2006.201.07:23:39.79#ibcon#enter sib2, iclass 25, count 0 2006.201.07:23:39.79#ibcon#flushed, iclass 25, count 0 2006.201.07:23:39.79#ibcon#about to write, iclass 25, count 0 2006.201.07:23:39.79#ibcon#wrote, iclass 25, count 0 2006.201.07:23:39.79#ibcon#about to read 3, iclass 25, count 0 2006.201.07:23:39.81#ibcon#read 3, iclass 25, count 0 2006.201.07:23:39.81#ibcon#about to read 4, iclass 25, count 0 2006.201.07:23:39.81#ibcon#read 4, iclass 25, count 0 2006.201.07:23:39.81#ibcon#about to read 5, iclass 25, count 0 2006.201.07:23:39.81#ibcon#read 5, iclass 25, count 0 2006.201.07:23:39.81#ibcon#about to read 6, iclass 25, count 0 2006.201.07:23:39.81#ibcon#read 6, iclass 25, count 0 2006.201.07:23:39.81#ibcon#end of sib2, iclass 25, count 0 2006.201.07:23:39.81#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:23:39.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:23:39.81#ibcon#[27=USB\r\n] 2006.201.07:23:39.81#ibcon#*before write, iclass 25, count 0 2006.201.07:23:39.81#ibcon#enter sib2, iclass 25, count 0 2006.201.07:23:39.81#ibcon#flushed, iclass 25, count 0 2006.201.07:23:39.81#ibcon#about to write, iclass 25, count 0 2006.201.07:23:39.81#ibcon#wrote, iclass 25, count 0 2006.201.07:23:39.81#ibcon#about to read 3, iclass 25, count 0 2006.201.07:23:39.84#ibcon#read 3, iclass 25, count 0 2006.201.07:23:39.84#ibcon#about to read 4, iclass 25, count 0 2006.201.07:23:39.84#ibcon#read 4, iclass 25, count 0 2006.201.07:23:39.84#ibcon#about to read 5, iclass 25, count 0 2006.201.07:23:39.84#ibcon#read 5, iclass 25, count 0 2006.201.07:23:39.84#ibcon#about to read 6, iclass 25, count 0 2006.201.07:23:39.84#ibcon#read 6, iclass 25, count 0 2006.201.07:23:39.84#ibcon#end of sib2, iclass 25, count 0 2006.201.07:23:39.84#ibcon#*after write, iclass 25, count 0 2006.201.07:23:39.84#ibcon#*before return 0, iclass 25, count 0 2006.201.07:23:39.84#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:23:39.84#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.07:23:39.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:23:39.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:23:39.84$vck44/vblo=2,634.99 2006.201.07:23:39.84#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.07:23:39.84#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.07:23:39.84#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:39.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:39.84#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:39.84#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:39.84#ibcon#enter wrdev, iclass 27, count 0 2006.201.07:23:39.84#ibcon#first serial, iclass 27, count 0 2006.201.07:23:39.84#ibcon#enter sib2, iclass 27, count 0 2006.201.07:23:39.84#ibcon#flushed, iclass 27, count 0 2006.201.07:23:39.84#ibcon#about to write, iclass 27, count 0 2006.201.07:23:39.84#ibcon#wrote, iclass 27, count 0 2006.201.07:23:39.84#ibcon#about to read 3, iclass 27, count 0 2006.201.07:23:39.86#ibcon#read 3, iclass 27, count 0 2006.201.07:23:39.86#ibcon#about to read 4, iclass 27, count 0 2006.201.07:23:39.86#ibcon#read 4, iclass 27, count 0 2006.201.07:23:39.86#ibcon#about to read 5, iclass 27, count 0 2006.201.07:23:39.86#ibcon#read 5, iclass 27, count 0 2006.201.07:23:39.86#ibcon#about to read 6, iclass 27, count 0 2006.201.07:23:39.86#ibcon#read 6, iclass 27, count 0 2006.201.07:23:39.86#ibcon#end of sib2, iclass 27, count 0 2006.201.07:23:39.86#ibcon#*mode == 0, iclass 27, count 0 2006.201.07:23:39.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.07:23:39.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:23:39.86#ibcon#*before write, iclass 27, count 0 2006.201.07:23:39.86#ibcon#enter sib2, iclass 27, count 0 2006.201.07:23:39.86#ibcon#flushed, iclass 27, count 0 2006.201.07:23:39.86#ibcon#about to write, iclass 27, count 0 2006.201.07:23:39.86#ibcon#wrote, iclass 27, count 0 2006.201.07:23:39.86#ibcon#about to read 3, iclass 27, count 0 2006.201.07:23:39.90#ibcon#read 3, iclass 27, count 0 2006.201.07:23:39.90#ibcon#about to read 4, iclass 27, count 0 2006.201.07:23:39.90#ibcon#read 4, iclass 27, count 0 2006.201.07:23:39.90#ibcon#about to read 5, iclass 27, count 0 2006.201.07:23:39.90#ibcon#read 5, iclass 27, count 0 2006.201.07:23:39.90#ibcon#about to read 6, iclass 27, count 0 2006.201.07:23:39.90#ibcon#read 6, iclass 27, count 0 2006.201.07:23:39.90#ibcon#end of sib2, iclass 27, count 0 2006.201.07:23:39.90#ibcon#*after write, iclass 27, count 0 2006.201.07:23:39.90#ibcon#*before return 0, iclass 27, count 0 2006.201.07:23:39.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:39.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.07:23:39.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.07:23:39.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.07:23:39.90$vck44/vb=2,5 2006.201.07:23:39.90#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.07:23:39.90#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.07:23:39.90#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:39.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:39.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:39.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:39.96#ibcon#enter wrdev, iclass 29, count 2 2006.201.07:23:39.96#ibcon#first serial, iclass 29, count 2 2006.201.07:23:39.96#ibcon#enter sib2, iclass 29, count 2 2006.201.07:23:39.96#ibcon#flushed, iclass 29, count 2 2006.201.07:23:39.96#ibcon#about to write, iclass 29, count 2 2006.201.07:23:39.96#ibcon#wrote, iclass 29, count 2 2006.201.07:23:39.96#ibcon#about to read 3, iclass 29, count 2 2006.201.07:23:39.98#ibcon#read 3, iclass 29, count 2 2006.201.07:23:39.98#ibcon#about to read 4, iclass 29, count 2 2006.201.07:23:39.98#ibcon#read 4, iclass 29, count 2 2006.201.07:23:39.98#ibcon#about to read 5, iclass 29, count 2 2006.201.07:23:39.98#ibcon#read 5, iclass 29, count 2 2006.201.07:23:39.98#ibcon#about to read 6, iclass 29, count 2 2006.201.07:23:39.98#ibcon#read 6, iclass 29, count 2 2006.201.07:23:39.98#ibcon#end of sib2, iclass 29, count 2 2006.201.07:23:39.98#ibcon#*mode == 0, iclass 29, count 2 2006.201.07:23:39.98#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.07:23:39.98#ibcon#[27=AT02-05\r\n] 2006.201.07:23:39.98#ibcon#*before write, iclass 29, count 2 2006.201.07:23:39.98#ibcon#enter sib2, iclass 29, count 2 2006.201.07:23:39.98#ibcon#flushed, iclass 29, count 2 2006.201.07:23:39.98#ibcon#about to write, iclass 29, count 2 2006.201.07:23:39.98#ibcon#wrote, iclass 29, count 2 2006.201.07:23:39.98#ibcon#about to read 3, iclass 29, count 2 2006.201.07:23:40.01#ibcon#read 3, iclass 29, count 2 2006.201.07:23:40.01#ibcon#about to read 4, iclass 29, count 2 2006.201.07:23:40.01#ibcon#read 4, iclass 29, count 2 2006.201.07:23:40.01#ibcon#about to read 5, iclass 29, count 2 2006.201.07:23:40.01#ibcon#read 5, iclass 29, count 2 2006.201.07:23:40.01#ibcon#about to read 6, iclass 29, count 2 2006.201.07:23:40.01#ibcon#read 6, iclass 29, count 2 2006.201.07:23:40.01#ibcon#end of sib2, iclass 29, count 2 2006.201.07:23:40.01#ibcon#*after write, iclass 29, count 2 2006.201.07:23:40.01#ibcon#*before return 0, iclass 29, count 2 2006.201.07:23:40.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:40.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.07:23:40.01#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.07:23:40.01#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:40.01#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:40.13#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:40.13#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:40.13#ibcon#enter wrdev, iclass 29, count 0 2006.201.07:23:40.13#ibcon#first serial, iclass 29, count 0 2006.201.07:23:40.13#ibcon#enter sib2, iclass 29, count 0 2006.201.07:23:40.13#ibcon#flushed, iclass 29, count 0 2006.201.07:23:40.13#ibcon#about to write, iclass 29, count 0 2006.201.07:23:40.13#ibcon#wrote, iclass 29, count 0 2006.201.07:23:40.13#ibcon#about to read 3, iclass 29, count 0 2006.201.07:23:40.15#ibcon#read 3, iclass 29, count 0 2006.201.07:23:40.15#ibcon#about to read 4, iclass 29, count 0 2006.201.07:23:40.15#ibcon#read 4, iclass 29, count 0 2006.201.07:23:40.15#ibcon#about to read 5, iclass 29, count 0 2006.201.07:23:40.15#ibcon#read 5, iclass 29, count 0 2006.201.07:23:40.15#ibcon#about to read 6, iclass 29, count 0 2006.201.07:23:40.15#ibcon#read 6, iclass 29, count 0 2006.201.07:23:40.15#ibcon#end of sib2, iclass 29, count 0 2006.201.07:23:40.15#ibcon#*mode == 0, iclass 29, count 0 2006.201.07:23:40.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.07:23:40.15#ibcon#[27=USB\r\n] 2006.201.07:23:40.15#ibcon#*before write, iclass 29, count 0 2006.201.07:23:40.15#ibcon#enter sib2, iclass 29, count 0 2006.201.07:23:40.15#ibcon#flushed, iclass 29, count 0 2006.201.07:23:40.15#ibcon#about to write, iclass 29, count 0 2006.201.07:23:40.15#ibcon#wrote, iclass 29, count 0 2006.201.07:23:40.15#ibcon#about to read 3, iclass 29, count 0 2006.201.07:23:40.18#ibcon#read 3, iclass 29, count 0 2006.201.07:23:40.18#ibcon#about to read 4, iclass 29, count 0 2006.201.07:23:40.18#ibcon#read 4, iclass 29, count 0 2006.201.07:23:40.18#ibcon#about to read 5, iclass 29, count 0 2006.201.07:23:40.18#ibcon#read 5, iclass 29, count 0 2006.201.07:23:40.18#ibcon#about to read 6, iclass 29, count 0 2006.201.07:23:40.18#ibcon#read 6, iclass 29, count 0 2006.201.07:23:40.18#ibcon#end of sib2, iclass 29, count 0 2006.201.07:23:40.18#ibcon#*after write, iclass 29, count 0 2006.201.07:23:40.18#ibcon#*before return 0, iclass 29, count 0 2006.201.07:23:40.18#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:40.18#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.07:23:40.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.07:23:40.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.07:23:40.18$vck44/vblo=3,649.99 2006.201.07:23:40.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.07:23:40.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.07:23:40.18#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:40.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:40.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:40.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:40.18#ibcon#enter wrdev, iclass 31, count 0 2006.201.07:23:40.18#ibcon#first serial, iclass 31, count 0 2006.201.07:23:40.18#ibcon#enter sib2, iclass 31, count 0 2006.201.07:23:40.18#ibcon#flushed, iclass 31, count 0 2006.201.07:23:40.18#ibcon#about to write, iclass 31, count 0 2006.201.07:23:40.18#ibcon#wrote, iclass 31, count 0 2006.201.07:23:40.18#ibcon#about to read 3, iclass 31, count 0 2006.201.07:23:40.20#ibcon#read 3, iclass 31, count 0 2006.201.07:23:40.20#ibcon#about to read 4, iclass 31, count 0 2006.201.07:23:40.20#ibcon#read 4, iclass 31, count 0 2006.201.07:23:40.20#ibcon#about to read 5, iclass 31, count 0 2006.201.07:23:40.20#ibcon#read 5, iclass 31, count 0 2006.201.07:23:40.20#ibcon#about to read 6, iclass 31, count 0 2006.201.07:23:40.20#ibcon#read 6, iclass 31, count 0 2006.201.07:23:40.20#ibcon#end of sib2, iclass 31, count 0 2006.201.07:23:40.20#ibcon#*mode == 0, iclass 31, count 0 2006.201.07:23:40.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.07:23:40.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:23:40.20#ibcon#*before write, iclass 31, count 0 2006.201.07:23:40.20#ibcon#enter sib2, iclass 31, count 0 2006.201.07:23:40.20#ibcon#flushed, iclass 31, count 0 2006.201.07:23:40.20#ibcon#about to write, iclass 31, count 0 2006.201.07:23:40.20#ibcon#wrote, iclass 31, count 0 2006.201.07:23:40.20#ibcon#about to read 3, iclass 31, count 0 2006.201.07:23:40.25#ibcon#read 3, iclass 31, count 0 2006.201.07:23:40.25#ibcon#about to read 4, iclass 31, count 0 2006.201.07:23:40.25#ibcon#read 4, iclass 31, count 0 2006.201.07:23:40.25#ibcon#about to read 5, iclass 31, count 0 2006.201.07:23:40.25#ibcon#read 5, iclass 31, count 0 2006.201.07:23:40.25#ibcon#about to read 6, iclass 31, count 0 2006.201.07:23:40.25#ibcon#read 6, iclass 31, count 0 2006.201.07:23:40.25#ibcon#end of sib2, iclass 31, count 0 2006.201.07:23:40.25#ibcon#*after write, iclass 31, count 0 2006.201.07:23:40.25#ibcon#*before return 0, iclass 31, count 0 2006.201.07:23:40.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:40.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:23:40.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.07:23:40.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.07:23:40.25$vck44/vb=3,4 2006.201.07:23:40.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.07:23:40.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.07:23:40.25#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:40.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:40.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:40.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:40.30#ibcon#enter wrdev, iclass 33, count 2 2006.201.07:23:40.30#ibcon#first serial, iclass 33, count 2 2006.201.07:23:40.30#ibcon#enter sib2, iclass 33, count 2 2006.201.07:23:40.30#ibcon#flushed, iclass 33, count 2 2006.201.07:23:40.30#ibcon#about to write, iclass 33, count 2 2006.201.07:23:40.30#ibcon#wrote, iclass 33, count 2 2006.201.07:23:40.30#ibcon#about to read 3, iclass 33, count 2 2006.201.07:23:40.32#ibcon#read 3, iclass 33, count 2 2006.201.07:23:40.32#ibcon#about to read 4, iclass 33, count 2 2006.201.07:23:40.32#ibcon#read 4, iclass 33, count 2 2006.201.07:23:40.32#ibcon#about to read 5, iclass 33, count 2 2006.201.07:23:40.32#ibcon#read 5, iclass 33, count 2 2006.201.07:23:40.32#ibcon#about to read 6, iclass 33, count 2 2006.201.07:23:40.32#ibcon#read 6, iclass 33, count 2 2006.201.07:23:40.32#ibcon#end of sib2, iclass 33, count 2 2006.201.07:23:40.32#ibcon#*mode == 0, iclass 33, count 2 2006.201.07:23:40.32#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.07:23:40.32#ibcon#[27=AT03-04\r\n] 2006.201.07:23:40.32#ibcon#*before write, iclass 33, count 2 2006.201.07:23:40.32#ibcon#enter sib2, iclass 33, count 2 2006.201.07:23:40.32#ibcon#flushed, iclass 33, count 2 2006.201.07:23:40.32#ibcon#about to write, iclass 33, count 2 2006.201.07:23:40.32#ibcon#wrote, iclass 33, count 2 2006.201.07:23:40.32#ibcon#about to read 3, iclass 33, count 2 2006.201.07:23:40.35#ibcon#read 3, iclass 33, count 2 2006.201.07:23:40.35#ibcon#about to read 4, iclass 33, count 2 2006.201.07:23:40.35#ibcon#read 4, iclass 33, count 2 2006.201.07:23:40.35#ibcon#about to read 5, iclass 33, count 2 2006.201.07:23:40.35#ibcon#read 5, iclass 33, count 2 2006.201.07:23:40.35#ibcon#about to read 6, iclass 33, count 2 2006.201.07:23:40.35#ibcon#read 6, iclass 33, count 2 2006.201.07:23:40.35#ibcon#end of sib2, iclass 33, count 2 2006.201.07:23:40.35#ibcon#*after write, iclass 33, count 2 2006.201.07:23:40.35#ibcon#*before return 0, iclass 33, count 2 2006.201.07:23:40.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:40.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.07:23:40.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.07:23:40.35#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:40.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:40.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:40.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:40.47#ibcon#enter wrdev, iclass 33, count 0 2006.201.07:23:40.47#ibcon#first serial, iclass 33, count 0 2006.201.07:23:40.47#ibcon#enter sib2, iclass 33, count 0 2006.201.07:23:40.47#ibcon#flushed, iclass 33, count 0 2006.201.07:23:40.47#ibcon#about to write, iclass 33, count 0 2006.201.07:23:40.47#ibcon#wrote, iclass 33, count 0 2006.201.07:23:40.47#ibcon#about to read 3, iclass 33, count 0 2006.201.07:23:40.49#ibcon#read 3, iclass 33, count 0 2006.201.07:23:40.49#ibcon#about to read 4, iclass 33, count 0 2006.201.07:23:40.49#ibcon#read 4, iclass 33, count 0 2006.201.07:23:40.49#ibcon#about to read 5, iclass 33, count 0 2006.201.07:23:40.49#ibcon#read 5, iclass 33, count 0 2006.201.07:23:40.49#ibcon#about to read 6, iclass 33, count 0 2006.201.07:23:40.49#ibcon#read 6, iclass 33, count 0 2006.201.07:23:40.49#ibcon#end of sib2, iclass 33, count 0 2006.201.07:23:40.49#ibcon#*mode == 0, iclass 33, count 0 2006.201.07:23:40.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.07:23:40.49#ibcon#[27=USB\r\n] 2006.201.07:23:40.49#ibcon#*before write, iclass 33, count 0 2006.201.07:23:40.49#ibcon#enter sib2, iclass 33, count 0 2006.201.07:23:40.49#ibcon#flushed, iclass 33, count 0 2006.201.07:23:40.49#ibcon#about to write, iclass 33, count 0 2006.201.07:23:40.49#ibcon#wrote, iclass 33, count 0 2006.201.07:23:40.49#ibcon#about to read 3, iclass 33, count 0 2006.201.07:23:40.52#ibcon#read 3, iclass 33, count 0 2006.201.07:23:40.52#ibcon#about to read 4, iclass 33, count 0 2006.201.07:23:40.52#ibcon#read 4, iclass 33, count 0 2006.201.07:23:40.52#ibcon#about to read 5, iclass 33, count 0 2006.201.07:23:40.52#ibcon#read 5, iclass 33, count 0 2006.201.07:23:40.52#ibcon#about to read 6, iclass 33, count 0 2006.201.07:23:40.52#ibcon#read 6, iclass 33, count 0 2006.201.07:23:40.52#ibcon#end of sib2, iclass 33, count 0 2006.201.07:23:40.52#ibcon#*after write, iclass 33, count 0 2006.201.07:23:40.52#ibcon#*before return 0, iclass 33, count 0 2006.201.07:23:40.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:40.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.07:23:40.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.07:23:40.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.07:23:40.52$vck44/vblo=4,679.99 2006.201.07:23:40.52#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.07:23:40.52#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.07:23:40.52#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:40.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:40.52#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:40.52#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:40.52#ibcon#enter wrdev, iclass 35, count 0 2006.201.07:23:40.52#ibcon#first serial, iclass 35, count 0 2006.201.07:23:40.52#ibcon#enter sib2, iclass 35, count 0 2006.201.07:23:40.52#ibcon#flushed, iclass 35, count 0 2006.201.07:23:40.52#ibcon#about to write, iclass 35, count 0 2006.201.07:23:40.52#ibcon#wrote, iclass 35, count 0 2006.201.07:23:40.52#ibcon#about to read 3, iclass 35, count 0 2006.201.07:23:40.54#ibcon#read 3, iclass 35, count 0 2006.201.07:23:40.54#ibcon#about to read 4, iclass 35, count 0 2006.201.07:23:40.54#ibcon#read 4, iclass 35, count 0 2006.201.07:23:40.54#ibcon#about to read 5, iclass 35, count 0 2006.201.07:23:40.54#ibcon#read 5, iclass 35, count 0 2006.201.07:23:40.54#ibcon#about to read 6, iclass 35, count 0 2006.201.07:23:40.54#ibcon#read 6, iclass 35, count 0 2006.201.07:23:40.54#ibcon#end of sib2, iclass 35, count 0 2006.201.07:23:40.54#ibcon#*mode == 0, iclass 35, count 0 2006.201.07:23:40.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.07:23:40.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:23:40.54#ibcon#*before write, iclass 35, count 0 2006.201.07:23:40.54#ibcon#enter sib2, iclass 35, count 0 2006.201.07:23:40.54#ibcon#flushed, iclass 35, count 0 2006.201.07:23:40.54#ibcon#about to write, iclass 35, count 0 2006.201.07:23:40.54#ibcon#wrote, iclass 35, count 0 2006.201.07:23:40.54#ibcon#about to read 3, iclass 35, count 0 2006.201.07:23:40.58#ibcon#read 3, iclass 35, count 0 2006.201.07:23:40.58#ibcon#about to read 4, iclass 35, count 0 2006.201.07:23:40.58#ibcon#read 4, iclass 35, count 0 2006.201.07:23:40.58#ibcon#about to read 5, iclass 35, count 0 2006.201.07:23:40.58#ibcon#read 5, iclass 35, count 0 2006.201.07:23:40.58#ibcon#about to read 6, iclass 35, count 0 2006.201.07:23:40.58#ibcon#read 6, iclass 35, count 0 2006.201.07:23:40.58#ibcon#end of sib2, iclass 35, count 0 2006.201.07:23:40.58#ibcon#*after write, iclass 35, count 0 2006.201.07:23:40.58#ibcon#*before return 0, iclass 35, count 0 2006.201.07:23:40.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:40.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.07:23:40.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.07:23:40.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.07:23:40.58$vck44/vb=4,5 2006.201.07:23:40.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.07:23:40.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.07:23:40.58#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:40.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:40.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:40.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:40.64#ibcon#enter wrdev, iclass 37, count 2 2006.201.07:23:40.64#ibcon#first serial, iclass 37, count 2 2006.201.07:23:40.64#ibcon#enter sib2, iclass 37, count 2 2006.201.07:23:40.64#ibcon#flushed, iclass 37, count 2 2006.201.07:23:40.64#ibcon#about to write, iclass 37, count 2 2006.201.07:23:40.64#ibcon#wrote, iclass 37, count 2 2006.201.07:23:40.64#ibcon#about to read 3, iclass 37, count 2 2006.201.07:23:40.66#ibcon#read 3, iclass 37, count 2 2006.201.07:23:40.66#ibcon#about to read 4, iclass 37, count 2 2006.201.07:23:40.66#ibcon#read 4, iclass 37, count 2 2006.201.07:23:40.66#ibcon#about to read 5, iclass 37, count 2 2006.201.07:23:40.66#ibcon#read 5, iclass 37, count 2 2006.201.07:23:40.66#ibcon#about to read 6, iclass 37, count 2 2006.201.07:23:40.66#ibcon#read 6, iclass 37, count 2 2006.201.07:23:40.66#ibcon#end of sib2, iclass 37, count 2 2006.201.07:23:40.66#ibcon#*mode == 0, iclass 37, count 2 2006.201.07:23:40.66#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.07:23:40.66#ibcon#[27=AT04-05\r\n] 2006.201.07:23:40.66#ibcon#*before write, iclass 37, count 2 2006.201.07:23:40.66#ibcon#enter sib2, iclass 37, count 2 2006.201.07:23:40.66#ibcon#flushed, iclass 37, count 2 2006.201.07:23:40.66#ibcon#about to write, iclass 37, count 2 2006.201.07:23:40.66#ibcon#wrote, iclass 37, count 2 2006.201.07:23:40.66#ibcon#about to read 3, iclass 37, count 2 2006.201.07:23:40.69#ibcon#read 3, iclass 37, count 2 2006.201.07:23:40.69#ibcon#about to read 4, iclass 37, count 2 2006.201.07:23:40.69#ibcon#read 4, iclass 37, count 2 2006.201.07:23:40.69#ibcon#about to read 5, iclass 37, count 2 2006.201.07:23:40.69#ibcon#read 5, iclass 37, count 2 2006.201.07:23:40.69#ibcon#about to read 6, iclass 37, count 2 2006.201.07:23:40.69#ibcon#read 6, iclass 37, count 2 2006.201.07:23:40.69#ibcon#end of sib2, iclass 37, count 2 2006.201.07:23:40.69#ibcon#*after write, iclass 37, count 2 2006.201.07:23:40.69#ibcon#*before return 0, iclass 37, count 2 2006.201.07:23:40.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:40.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.07:23:40.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.07:23:40.69#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:40.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:40.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:40.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:40.81#ibcon#enter wrdev, iclass 37, count 0 2006.201.07:23:40.81#ibcon#first serial, iclass 37, count 0 2006.201.07:23:40.81#ibcon#enter sib2, iclass 37, count 0 2006.201.07:23:40.81#ibcon#flushed, iclass 37, count 0 2006.201.07:23:40.81#ibcon#about to write, iclass 37, count 0 2006.201.07:23:40.81#ibcon#wrote, iclass 37, count 0 2006.201.07:23:40.81#ibcon#about to read 3, iclass 37, count 0 2006.201.07:23:40.83#ibcon#read 3, iclass 37, count 0 2006.201.07:23:40.83#ibcon#about to read 4, iclass 37, count 0 2006.201.07:23:40.83#ibcon#read 4, iclass 37, count 0 2006.201.07:23:40.83#ibcon#about to read 5, iclass 37, count 0 2006.201.07:23:40.83#ibcon#read 5, iclass 37, count 0 2006.201.07:23:40.83#ibcon#about to read 6, iclass 37, count 0 2006.201.07:23:40.83#ibcon#read 6, iclass 37, count 0 2006.201.07:23:40.83#ibcon#end of sib2, iclass 37, count 0 2006.201.07:23:40.83#ibcon#*mode == 0, iclass 37, count 0 2006.201.07:23:40.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.07:23:40.83#ibcon#[27=USB\r\n] 2006.201.07:23:40.83#ibcon#*before write, iclass 37, count 0 2006.201.07:23:40.83#ibcon#enter sib2, iclass 37, count 0 2006.201.07:23:40.83#ibcon#flushed, iclass 37, count 0 2006.201.07:23:40.83#ibcon#about to write, iclass 37, count 0 2006.201.07:23:40.83#ibcon#wrote, iclass 37, count 0 2006.201.07:23:40.83#ibcon#about to read 3, iclass 37, count 0 2006.201.07:23:40.86#ibcon#read 3, iclass 37, count 0 2006.201.07:23:40.86#ibcon#about to read 4, iclass 37, count 0 2006.201.07:23:40.86#ibcon#read 4, iclass 37, count 0 2006.201.07:23:40.86#ibcon#about to read 5, iclass 37, count 0 2006.201.07:23:40.86#ibcon#read 5, iclass 37, count 0 2006.201.07:23:40.86#ibcon#about to read 6, iclass 37, count 0 2006.201.07:23:40.86#ibcon#read 6, iclass 37, count 0 2006.201.07:23:40.86#ibcon#end of sib2, iclass 37, count 0 2006.201.07:23:40.86#ibcon#*after write, iclass 37, count 0 2006.201.07:23:40.86#ibcon#*before return 0, iclass 37, count 0 2006.201.07:23:40.86#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:40.86#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.07:23:40.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.07:23:40.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.07:23:40.86$vck44/vblo=5,709.99 2006.201.07:23:40.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.07:23:40.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.07:23:40.86#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:40.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:40.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:40.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:40.86#ibcon#enter wrdev, iclass 39, count 0 2006.201.07:23:40.86#ibcon#first serial, iclass 39, count 0 2006.201.07:23:40.86#ibcon#enter sib2, iclass 39, count 0 2006.201.07:23:40.86#ibcon#flushed, iclass 39, count 0 2006.201.07:23:40.86#ibcon#about to write, iclass 39, count 0 2006.201.07:23:40.86#ibcon#wrote, iclass 39, count 0 2006.201.07:23:40.86#ibcon#about to read 3, iclass 39, count 0 2006.201.07:23:40.88#ibcon#read 3, iclass 39, count 0 2006.201.07:23:40.88#ibcon#about to read 4, iclass 39, count 0 2006.201.07:23:40.88#ibcon#read 4, iclass 39, count 0 2006.201.07:23:40.88#ibcon#about to read 5, iclass 39, count 0 2006.201.07:23:40.88#ibcon#read 5, iclass 39, count 0 2006.201.07:23:40.88#ibcon#about to read 6, iclass 39, count 0 2006.201.07:23:40.88#ibcon#read 6, iclass 39, count 0 2006.201.07:23:40.88#ibcon#end of sib2, iclass 39, count 0 2006.201.07:23:40.88#ibcon#*mode == 0, iclass 39, count 0 2006.201.07:23:40.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.07:23:40.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:23:40.88#ibcon#*before write, iclass 39, count 0 2006.201.07:23:40.88#ibcon#enter sib2, iclass 39, count 0 2006.201.07:23:40.88#ibcon#flushed, iclass 39, count 0 2006.201.07:23:40.88#ibcon#about to write, iclass 39, count 0 2006.201.07:23:40.88#ibcon#wrote, iclass 39, count 0 2006.201.07:23:40.88#ibcon#about to read 3, iclass 39, count 0 2006.201.07:23:40.92#ibcon#read 3, iclass 39, count 0 2006.201.07:23:40.92#ibcon#about to read 4, iclass 39, count 0 2006.201.07:23:40.92#ibcon#read 4, iclass 39, count 0 2006.201.07:23:40.92#ibcon#about to read 5, iclass 39, count 0 2006.201.07:23:40.92#ibcon#read 5, iclass 39, count 0 2006.201.07:23:40.92#ibcon#about to read 6, iclass 39, count 0 2006.201.07:23:40.92#ibcon#read 6, iclass 39, count 0 2006.201.07:23:40.92#ibcon#end of sib2, iclass 39, count 0 2006.201.07:23:40.92#ibcon#*after write, iclass 39, count 0 2006.201.07:23:40.92#ibcon#*before return 0, iclass 39, count 0 2006.201.07:23:40.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:40.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.07:23:40.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.07:23:40.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.07:23:40.92$vck44/vb=5,4 2006.201.07:23:40.92#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.07:23:40.92#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.07:23:40.92#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:40.92#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:40.98#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:40.98#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:40.98#ibcon#enter wrdev, iclass 2, count 2 2006.201.07:23:40.98#ibcon#first serial, iclass 2, count 2 2006.201.07:23:40.98#ibcon#enter sib2, iclass 2, count 2 2006.201.07:23:40.98#ibcon#flushed, iclass 2, count 2 2006.201.07:23:40.98#ibcon#about to write, iclass 2, count 2 2006.201.07:23:40.98#ibcon#wrote, iclass 2, count 2 2006.201.07:23:40.98#ibcon#about to read 3, iclass 2, count 2 2006.201.07:23:41.00#ibcon#read 3, iclass 2, count 2 2006.201.07:23:41.00#ibcon#about to read 4, iclass 2, count 2 2006.201.07:23:41.00#ibcon#read 4, iclass 2, count 2 2006.201.07:23:41.00#ibcon#about to read 5, iclass 2, count 2 2006.201.07:23:41.00#ibcon#read 5, iclass 2, count 2 2006.201.07:23:41.00#ibcon#about to read 6, iclass 2, count 2 2006.201.07:23:41.00#ibcon#read 6, iclass 2, count 2 2006.201.07:23:41.00#ibcon#end of sib2, iclass 2, count 2 2006.201.07:23:41.00#ibcon#*mode == 0, iclass 2, count 2 2006.201.07:23:41.00#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.07:23:41.00#ibcon#[27=AT05-04\r\n] 2006.201.07:23:41.00#ibcon#*before write, iclass 2, count 2 2006.201.07:23:41.00#ibcon#enter sib2, iclass 2, count 2 2006.201.07:23:41.00#ibcon#flushed, iclass 2, count 2 2006.201.07:23:41.00#ibcon#about to write, iclass 2, count 2 2006.201.07:23:41.00#ibcon#wrote, iclass 2, count 2 2006.201.07:23:41.00#ibcon#about to read 3, iclass 2, count 2 2006.201.07:23:41.03#ibcon#read 3, iclass 2, count 2 2006.201.07:23:41.03#ibcon#about to read 4, iclass 2, count 2 2006.201.07:23:41.03#ibcon#read 4, iclass 2, count 2 2006.201.07:23:41.03#ibcon#about to read 5, iclass 2, count 2 2006.201.07:23:41.03#ibcon#read 5, iclass 2, count 2 2006.201.07:23:41.03#ibcon#about to read 6, iclass 2, count 2 2006.201.07:23:41.03#ibcon#read 6, iclass 2, count 2 2006.201.07:23:41.03#ibcon#end of sib2, iclass 2, count 2 2006.201.07:23:41.03#ibcon#*after write, iclass 2, count 2 2006.201.07:23:41.03#ibcon#*before return 0, iclass 2, count 2 2006.201.07:23:41.03#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:41.03#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.07:23:41.03#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.07:23:41.03#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:41.03#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:41.15#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:41.15#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:41.15#ibcon#enter wrdev, iclass 2, count 0 2006.201.07:23:41.15#ibcon#first serial, iclass 2, count 0 2006.201.07:23:41.15#ibcon#enter sib2, iclass 2, count 0 2006.201.07:23:41.15#ibcon#flushed, iclass 2, count 0 2006.201.07:23:41.15#ibcon#about to write, iclass 2, count 0 2006.201.07:23:41.15#ibcon#wrote, iclass 2, count 0 2006.201.07:23:41.15#ibcon#about to read 3, iclass 2, count 0 2006.201.07:23:41.17#ibcon#read 3, iclass 2, count 0 2006.201.07:23:41.17#ibcon#about to read 4, iclass 2, count 0 2006.201.07:23:41.17#ibcon#read 4, iclass 2, count 0 2006.201.07:23:41.17#ibcon#about to read 5, iclass 2, count 0 2006.201.07:23:41.17#ibcon#read 5, iclass 2, count 0 2006.201.07:23:41.17#ibcon#about to read 6, iclass 2, count 0 2006.201.07:23:41.17#ibcon#read 6, iclass 2, count 0 2006.201.07:23:41.17#ibcon#end of sib2, iclass 2, count 0 2006.201.07:23:41.17#ibcon#*mode == 0, iclass 2, count 0 2006.201.07:23:41.17#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.07:23:41.17#ibcon#[27=USB\r\n] 2006.201.07:23:41.17#ibcon#*before write, iclass 2, count 0 2006.201.07:23:41.17#ibcon#enter sib2, iclass 2, count 0 2006.201.07:23:41.17#ibcon#flushed, iclass 2, count 0 2006.201.07:23:41.17#ibcon#about to write, iclass 2, count 0 2006.201.07:23:41.17#ibcon#wrote, iclass 2, count 0 2006.201.07:23:41.17#ibcon#about to read 3, iclass 2, count 0 2006.201.07:23:41.20#ibcon#read 3, iclass 2, count 0 2006.201.07:23:41.20#ibcon#about to read 4, iclass 2, count 0 2006.201.07:23:41.20#ibcon#read 4, iclass 2, count 0 2006.201.07:23:41.20#ibcon#about to read 5, iclass 2, count 0 2006.201.07:23:41.20#ibcon#read 5, iclass 2, count 0 2006.201.07:23:41.20#ibcon#about to read 6, iclass 2, count 0 2006.201.07:23:41.20#ibcon#read 6, iclass 2, count 0 2006.201.07:23:41.20#ibcon#end of sib2, iclass 2, count 0 2006.201.07:23:41.20#ibcon#*after write, iclass 2, count 0 2006.201.07:23:41.20#ibcon#*before return 0, iclass 2, count 0 2006.201.07:23:41.20#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:41.20#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.07:23:41.20#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.07:23:41.20#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.07:23:41.20$vck44/vblo=6,719.99 2006.201.07:23:41.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.07:23:41.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.07:23:41.20#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:41.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:41.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:41.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:41.20#ibcon#enter wrdev, iclass 5, count 0 2006.201.07:23:41.20#ibcon#first serial, iclass 5, count 0 2006.201.07:23:41.20#ibcon#enter sib2, iclass 5, count 0 2006.201.07:23:41.20#ibcon#flushed, iclass 5, count 0 2006.201.07:23:41.20#ibcon#about to write, iclass 5, count 0 2006.201.07:23:41.20#ibcon#wrote, iclass 5, count 0 2006.201.07:23:41.20#ibcon#about to read 3, iclass 5, count 0 2006.201.07:23:41.22#ibcon#read 3, iclass 5, count 0 2006.201.07:23:41.22#ibcon#about to read 4, iclass 5, count 0 2006.201.07:23:41.22#ibcon#read 4, iclass 5, count 0 2006.201.07:23:41.22#ibcon#about to read 5, iclass 5, count 0 2006.201.07:23:41.22#ibcon#read 5, iclass 5, count 0 2006.201.07:23:41.22#ibcon#about to read 6, iclass 5, count 0 2006.201.07:23:41.22#ibcon#read 6, iclass 5, count 0 2006.201.07:23:41.22#ibcon#end of sib2, iclass 5, count 0 2006.201.07:23:41.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.07:23:41.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.07:23:41.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:23:41.22#ibcon#*before write, iclass 5, count 0 2006.201.07:23:41.22#ibcon#enter sib2, iclass 5, count 0 2006.201.07:23:41.22#ibcon#flushed, iclass 5, count 0 2006.201.07:23:41.22#ibcon#about to write, iclass 5, count 0 2006.201.07:23:41.22#ibcon#wrote, iclass 5, count 0 2006.201.07:23:41.22#ibcon#about to read 3, iclass 5, count 0 2006.201.07:23:41.26#ibcon#read 3, iclass 5, count 0 2006.201.07:23:41.26#ibcon#about to read 4, iclass 5, count 0 2006.201.07:23:41.26#ibcon#read 4, iclass 5, count 0 2006.201.07:23:41.26#ibcon#about to read 5, iclass 5, count 0 2006.201.07:23:41.26#ibcon#read 5, iclass 5, count 0 2006.201.07:23:41.26#ibcon#about to read 6, iclass 5, count 0 2006.201.07:23:41.26#ibcon#read 6, iclass 5, count 0 2006.201.07:23:41.26#ibcon#end of sib2, iclass 5, count 0 2006.201.07:23:41.26#ibcon#*after write, iclass 5, count 0 2006.201.07:23:41.26#ibcon#*before return 0, iclass 5, count 0 2006.201.07:23:41.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:41.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.07:23:41.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.07:23:41.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.07:23:41.26$vck44/vb=6,4 2006.201.07:23:41.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.07:23:41.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.07:23:41.26#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:41.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:41.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:41.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:41.32#ibcon#enter wrdev, iclass 7, count 2 2006.201.07:23:41.32#ibcon#first serial, iclass 7, count 2 2006.201.07:23:41.32#ibcon#enter sib2, iclass 7, count 2 2006.201.07:23:41.32#ibcon#flushed, iclass 7, count 2 2006.201.07:23:41.32#ibcon#about to write, iclass 7, count 2 2006.201.07:23:41.32#ibcon#wrote, iclass 7, count 2 2006.201.07:23:41.32#ibcon#about to read 3, iclass 7, count 2 2006.201.07:23:41.34#ibcon#read 3, iclass 7, count 2 2006.201.07:23:41.34#ibcon#about to read 4, iclass 7, count 2 2006.201.07:23:41.34#ibcon#read 4, iclass 7, count 2 2006.201.07:23:41.34#ibcon#about to read 5, iclass 7, count 2 2006.201.07:23:41.34#ibcon#read 5, iclass 7, count 2 2006.201.07:23:41.34#ibcon#about to read 6, iclass 7, count 2 2006.201.07:23:41.34#ibcon#read 6, iclass 7, count 2 2006.201.07:23:41.34#ibcon#end of sib2, iclass 7, count 2 2006.201.07:23:41.34#ibcon#*mode == 0, iclass 7, count 2 2006.201.07:23:41.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.07:23:41.34#ibcon#[27=AT06-04\r\n] 2006.201.07:23:41.34#ibcon#*before write, iclass 7, count 2 2006.201.07:23:41.34#ibcon#enter sib2, iclass 7, count 2 2006.201.07:23:41.34#ibcon#flushed, iclass 7, count 2 2006.201.07:23:41.34#ibcon#about to write, iclass 7, count 2 2006.201.07:23:41.34#ibcon#wrote, iclass 7, count 2 2006.201.07:23:41.34#ibcon#about to read 3, iclass 7, count 2 2006.201.07:23:41.37#ibcon#read 3, iclass 7, count 2 2006.201.07:23:41.37#ibcon#about to read 4, iclass 7, count 2 2006.201.07:23:41.37#ibcon#read 4, iclass 7, count 2 2006.201.07:23:41.37#ibcon#about to read 5, iclass 7, count 2 2006.201.07:23:41.37#ibcon#read 5, iclass 7, count 2 2006.201.07:23:41.37#ibcon#about to read 6, iclass 7, count 2 2006.201.07:23:41.37#ibcon#read 6, iclass 7, count 2 2006.201.07:23:41.37#ibcon#end of sib2, iclass 7, count 2 2006.201.07:23:41.37#ibcon#*after write, iclass 7, count 2 2006.201.07:23:41.37#ibcon#*before return 0, iclass 7, count 2 2006.201.07:23:41.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:41.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:23:41.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.07:23:41.37#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:41.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:41.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:41.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:41.49#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:23:41.49#ibcon#first serial, iclass 7, count 0 2006.201.07:23:41.49#ibcon#enter sib2, iclass 7, count 0 2006.201.07:23:41.49#ibcon#flushed, iclass 7, count 0 2006.201.07:23:41.49#ibcon#about to write, iclass 7, count 0 2006.201.07:23:41.49#ibcon#wrote, iclass 7, count 0 2006.201.07:23:41.49#ibcon#about to read 3, iclass 7, count 0 2006.201.07:23:41.51#ibcon#read 3, iclass 7, count 0 2006.201.07:23:41.51#ibcon#about to read 4, iclass 7, count 0 2006.201.07:23:41.51#ibcon#read 4, iclass 7, count 0 2006.201.07:23:41.51#ibcon#about to read 5, iclass 7, count 0 2006.201.07:23:41.51#ibcon#read 5, iclass 7, count 0 2006.201.07:23:41.51#ibcon#about to read 6, iclass 7, count 0 2006.201.07:23:41.51#ibcon#read 6, iclass 7, count 0 2006.201.07:23:41.51#ibcon#end of sib2, iclass 7, count 0 2006.201.07:23:41.51#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:23:41.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:23:41.51#ibcon#[27=USB\r\n] 2006.201.07:23:41.51#ibcon#*before write, iclass 7, count 0 2006.201.07:23:41.51#ibcon#enter sib2, iclass 7, count 0 2006.201.07:23:41.51#ibcon#flushed, iclass 7, count 0 2006.201.07:23:41.51#ibcon#about to write, iclass 7, count 0 2006.201.07:23:41.51#ibcon#wrote, iclass 7, count 0 2006.201.07:23:41.51#ibcon#about to read 3, iclass 7, count 0 2006.201.07:23:41.54#ibcon#read 3, iclass 7, count 0 2006.201.07:23:41.54#ibcon#about to read 4, iclass 7, count 0 2006.201.07:23:41.54#ibcon#read 4, iclass 7, count 0 2006.201.07:23:41.54#ibcon#about to read 5, iclass 7, count 0 2006.201.07:23:41.54#ibcon#read 5, iclass 7, count 0 2006.201.07:23:41.54#ibcon#about to read 6, iclass 7, count 0 2006.201.07:23:41.54#ibcon#read 6, iclass 7, count 0 2006.201.07:23:41.54#ibcon#end of sib2, iclass 7, count 0 2006.201.07:23:41.54#ibcon#*after write, iclass 7, count 0 2006.201.07:23:41.54#ibcon#*before return 0, iclass 7, count 0 2006.201.07:23:41.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:41.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:23:41.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:23:41.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:23:41.54$vck44/vblo=7,734.99 2006.201.07:23:41.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.07:23:41.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.07:23:41.54#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:41.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:41.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:41.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:41.54#ibcon#enter wrdev, iclass 11, count 0 2006.201.07:23:41.54#ibcon#first serial, iclass 11, count 0 2006.201.07:23:41.54#ibcon#enter sib2, iclass 11, count 0 2006.201.07:23:41.54#ibcon#flushed, iclass 11, count 0 2006.201.07:23:41.54#ibcon#about to write, iclass 11, count 0 2006.201.07:23:41.54#ibcon#wrote, iclass 11, count 0 2006.201.07:23:41.54#ibcon#about to read 3, iclass 11, count 0 2006.201.07:23:41.56#ibcon#read 3, iclass 11, count 0 2006.201.07:23:41.56#ibcon#about to read 4, iclass 11, count 0 2006.201.07:23:41.56#ibcon#read 4, iclass 11, count 0 2006.201.07:23:41.56#ibcon#about to read 5, iclass 11, count 0 2006.201.07:23:41.56#ibcon#read 5, iclass 11, count 0 2006.201.07:23:41.56#ibcon#about to read 6, iclass 11, count 0 2006.201.07:23:41.56#ibcon#read 6, iclass 11, count 0 2006.201.07:23:41.56#ibcon#end of sib2, iclass 11, count 0 2006.201.07:23:41.56#ibcon#*mode == 0, iclass 11, count 0 2006.201.07:23:41.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.07:23:41.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:23:41.56#ibcon#*before write, iclass 11, count 0 2006.201.07:23:41.56#ibcon#enter sib2, iclass 11, count 0 2006.201.07:23:41.56#ibcon#flushed, iclass 11, count 0 2006.201.07:23:41.56#ibcon#about to write, iclass 11, count 0 2006.201.07:23:41.56#ibcon#wrote, iclass 11, count 0 2006.201.07:23:41.56#ibcon#about to read 3, iclass 11, count 0 2006.201.07:23:41.60#ibcon#read 3, iclass 11, count 0 2006.201.07:23:41.60#ibcon#about to read 4, iclass 11, count 0 2006.201.07:23:41.60#ibcon#read 4, iclass 11, count 0 2006.201.07:23:41.60#ibcon#about to read 5, iclass 11, count 0 2006.201.07:23:41.60#ibcon#read 5, iclass 11, count 0 2006.201.07:23:41.60#ibcon#about to read 6, iclass 11, count 0 2006.201.07:23:41.60#ibcon#read 6, iclass 11, count 0 2006.201.07:23:41.60#ibcon#end of sib2, iclass 11, count 0 2006.201.07:23:41.60#ibcon#*after write, iclass 11, count 0 2006.201.07:23:41.60#ibcon#*before return 0, iclass 11, count 0 2006.201.07:23:41.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:41.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.07:23:41.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.07:23:41.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.07:23:41.60$vck44/vb=7,4 2006.201.07:23:41.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.07:23:41.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.07:23:41.60#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:41.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:41.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:41.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:41.66#ibcon#enter wrdev, iclass 13, count 2 2006.201.07:23:41.66#ibcon#first serial, iclass 13, count 2 2006.201.07:23:41.66#ibcon#enter sib2, iclass 13, count 2 2006.201.07:23:41.66#ibcon#flushed, iclass 13, count 2 2006.201.07:23:41.66#ibcon#about to write, iclass 13, count 2 2006.201.07:23:41.66#ibcon#wrote, iclass 13, count 2 2006.201.07:23:41.66#ibcon#about to read 3, iclass 13, count 2 2006.201.07:23:41.68#ibcon#read 3, iclass 13, count 2 2006.201.07:23:41.68#ibcon#about to read 4, iclass 13, count 2 2006.201.07:23:41.68#ibcon#read 4, iclass 13, count 2 2006.201.07:23:41.68#ibcon#about to read 5, iclass 13, count 2 2006.201.07:23:41.68#ibcon#read 5, iclass 13, count 2 2006.201.07:23:41.68#ibcon#about to read 6, iclass 13, count 2 2006.201.07:23:41.68#ibcon#read 6, iclass 13, count 2 2006.201.07:23:41.68#ibcon#end of sib2, iclass 13, count 2 2006.201.07:23:41.68#ibcon#*mode == 0, iclass 13, count 2 2006.201.07:23:41.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.07:23:41.68#ibcon#[27=AT07-04\r\n] 2006.201.07:23:41.68#ibcon#*before write, iclass 13, count 2 2006.201.07:23:41.68#ibcon#enter sib2, iclass 13, count 2 2006.201.07:23:41.68#ibcon#flushed, iclass 13, count 2 2006.201.07:23:41.68#ibcon#about to write, iclass 13, count 2 2006.201.07:23:41.68#ibcon#wrote, iclass 13, count 2 2006.201.07:23:41.68#ibcon#about to read 3, iclass 13, count 2 2006.201.07:23:41.71#ibcon#read 3, iclass 13, count 2 2006.201.07:23:41.71#ibcon#about to read 4, iclass 13, count 2 2006.201.07:23:41.71#ibcon#read 4, iclass 13, count 2 2006.201.07:23:41.71#ibcon#about to read 5, iclass 13, count 2 2006.201.07:23:41.71#ibcon#read 5, iclass 13, count 2 2006.201.07:23:41.71#ibcon#about to read 6, iclass 13, count 2 2006.201.07:23:41.71#ibcon#read 6, iclass 13, count 2 2006.201.07:23:41.71#ibcon#end of sib2, iclass 13, count 2 2006.201.07:23:41.71#ibcon#*after write, iclass 13, count 2 2006.201.07:23:41.71#ibcon#*before return 0, iclass 13, count 2 2006.201.07:23:41.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:41.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.07:23:41.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.07:23:41.71#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:41.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:41.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:41.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:41.83#ibcon#enter wrdev, iclass 13, count 0 2006.201.07:23:41.83#ibcon#first serial, iclass 13, count 0 2006.201.07:23:41.83#ibcon#enter sib2, iclass 13, count 0 2006.201.07:23:41.83#ibcon#flushed, iclass 13, count 0 2006.201.07:23:41.83#ibcon#about to write, iclass 13, count 0 2006.201.07:23:41.83#ibcon#wrote, iclass 13, count 0 2006.201.07:23:41.83#ibcon#about to read 3, iclass 13, count 0 2006.201.07:23:41.85#ibcon#read 3, iclass 13, count 0 2006.201.07:23:41.85#ibcon#about to read 4, iclass 13, count 0 2006.201.07:23:41.85#ibcon#read 4, iclass 13, count 0 2006.201.07:23:41.85#ibcon#about to read 5, iclass 13, count 0 2006.201.07:23:41.85#ibcon#read 5, iclass 13, count 0 2006.201.07:23:41.85#ibcon#about to read 6, iclass 13, count 0 2006.201.07:23:41.85#ibcon#read 6, iclass 13, count 0 2006.201.07:23:41.85#ibcon#end of sib2, iclass 13, count 0 2006.201.07:23:41.85#ibcon#*mode == 0, iclass 13, count 0 2006.201.07:23:41.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.07:23:41.85#ibcon#[27=USB\r\n] 2006.201.07:23:41.85#ibcon#*before write, iclass 13, count 0 2006.201.07:23:41.85#ibcon#enter sib2, iclass 13, count 0 2006.201.07:23:41.85#ibcon#flushed, iclass 13, count 0 2006.201.07:23:41.85#ibcon#about to write, iclass 13, count 0 2006.201.07:23:41.85#ibcon#wrote, iclass 13, count 0 2006.201.07:23:41.85#ibcon#about to read 3, iclass 13, count 0 2006.201.07:23:41.88#ibcon#read 3, iclass 13, count 0 2006.201.07:23:41.88#ibcon#about to read 4, iclass 13, count 0 2006.201.07:23:41.88#ibcon#read 4, iclass 13, count 0 2006.201.07:23:41.88#ibcon#about to read 5, iclass 13, count 0 2006.201.07:23:41.88#ibcon#read 5, iclass 13, count 0 2006.201.07:23:41.88#ibcon#about to read 6, iclass 13, count 0 2006.201.07:23:41.88#ibcon#read 6, iclass 13, count 0 2006.201.07:23:41.88#ibcon#end of sib2, iclass 13, count 0 2006.201.07:23:41.88#ibcon#*after write, iclass 13, count 0 2006.201.07:23:41.88#ibcon#*before return 0, iclass 13, count 0 2006.201.07:23:41.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:41.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.07:23:41.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.07:23:41.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.07:23:41.88$vck44/vblo=8,744.99 2006.201.07:23:41.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.07:23:41.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.07:23:41.88#ibcon#ireg 17 cls_cnt 0 2006.201.07:23:41.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:41.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:41.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:41.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.07:23:41.88#ibcon#first serial, iclass 15, count 0 2006.201.07:23:41.88#ibcon#enter sib2, iclass 15, count 0 2006.201.07:23:41.88#ibcon#flushed, iclass 15, count 0 2006.201.07:23:41.88#ibcon#about to write, iclass 15, count 0 2006.201.07:23:41.88#ibcon#wrote, iclass 15, count 0 2006.201.07:23:41.88#ibcon#about to read 3, iclass 15, count 0 2006.201.07:23:41.90#ibcon#read 3, iclass 15, count 0 2006.201.07:23:41.90#ibcon#about to read 4, iclass 15, count 0 2006.201.07:23:41.90#ibcon#read 4, iclass 15, count 0 2006.201.07:23:41.90#ibcon#about to read 5, iclass 15, count 0 2006.201.07:23:41.90#ibcon#read 5, iclass 15, count 0 2006.201.07:23:41.90#ibcon#about to read 6, iclass 15, count 0 2006.201.07:23:41.90#ibcon#read 6, iclass 15, count 0 2006.201.07:23:41.90#ibcon#end of sib2, iclass 15, count 0 2006.201.07:23:41.90#ibcon#*mode == 0, iclass 15, count 0 2006.201.07:23:41.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.07:23:41.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:23:41.90#ibcon#*before write, iclass 15, count 0 2006.201.07:23:41.90#ibcon#enter sib2, iclass 15, count 0 2006.201.07:23:41.90#ibcon#flushed, iclass 15, count 0 2006.201.07:23:41.90#ibcon#about to write, iclass 15, count 0 2006.201.07:23:41.90#ibcon#wrote, iclass 15, count 0 2006.201.07:23:41.90#ibcon#about to read 3, iclass 15, count 0 2006.201.07:23:41.94#ibcon#read 3, iclass 15, count 0 2006.201.07:23:41.94#ibcon#about to read 4, iclass 15, count 0 2006.201.07:23:41.94#ibcon#read 4, iclass 15, count 0 2006.201.07:23:41.94#ibcon#about to read 5, iclass 15, count 0 2006.201.07:23:41.94#ibcon#read 5, iclass 15, count 0 2006.201.07:23:41.94#ibcon#about to read 6, iclass 15, count 0 2006.201.07:23:41.94#ibcon#read 6, iclass 15, count 0 2006.201.07:23:41.94#ibcon#end of sib2, iclass 15, count 0 2006.201.07:23:41.94#ibcon#*after write, iclass 15, count 0 2006.201.07:23:41.94#ibcon#*before return 0, iclass 15, count 0 2006.201.07:23:41.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:41.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.07:23:41.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.07:23:41.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.07:23:41.94$vck44/vb=8,4 2006.201.07:23:41.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.07:23:41.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.07:23:41.94#ibcon#ireg 11 cls_cnt 2 2006.201.07:23:41.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:42.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:42.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:42.00#ibcon#enter wrdev, iclass 17, count 2 2006.201.07:23:42.00#ibcon#first serial, iclass 17, count 2 2006.201.07:23:42.00#ibcon#enter sib2, iclass 17, count 2 2006.201.07:23:42.00#ibcon#flushed, iclass 17, count 2 2006.201.07:23:42.00#ibcon#about to write, iclass 17, count 2 2006.201.07:23:42.00#ibcon#wrote, iclass 17, count 2 2006.201.07:23:42.00#ibcon#about to read 3, iclass 17, count 2 2006.201.07:23:42.02#ibcon#read 3, iclass 17, count 2 2006.201.07:23:42.02#ibcon#about to read 4, iclass 17, count 2 2006.201.07:23:42.02#ibcon#read 4, iclass 17, count 2 2006.201.07:23:42.02#ibcon#about to read 5, iclass 17, count 2 2006.201.07:23:42.02#ibcon#read 5, iclass 17, count 2 2006.201.07:23:42.02#ibcon#about to read 6, iclass 17, count 2 2006.201.07:23:42.02#ibcon#read 6, iclass 17, count 2 2006.201.07:23:42.02#ibcon#end of sib2, iclass 17, count 2 2006.201.07:23:42.02#ibcon#*mode == 0, iclass 17, count 2 2006.201.07:23:42.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.07:23:42.02#ibcon#[27=AT08-04\r\n] 2006.201.07:23:42.02#ibcon#*before write, iclass 17, count 2 2006.201.07:23:42.02#ibcon#enter sib2, iclass 17, count 2 2006.201.07:23:42.02#ibcon#flushed, iclass 17, count 2 2006.201.07:23:42.02#ibcon#about to write, iclass 17, count 2 2006.201.07:23:42.02#ibcon#wrote, iclass 17, count 2 2006.201.07:23:42.02#ibcon#about to read 3, iclass 17, count 2 2006.201.07:23:42.05#ibcon#read 3, iclass 17, count 2 2006.201.07:23:42.05#ibcon#about to read 4, iclass 17, count 2 2006.201.07:23:42.05#ibcon#read 4, iclass 17, count 2 2006.201.07:23:42.05#ibcon#about to read 5, iclass 17, count 2 2006.201.07:23:42.05#ibcon#read 5, iclass 17, count 2 2006.201.07:23:42.05#ibcon#about to read 6, iclass 17, count 2 2006.201.07:23:42.05#ibcon#read 6, iclass 17, count 2 2006.201.07:23:42.05#ibcon#end of sib2, iclass 17, count 2 2006.201.07:23:42.05#ibcon#*after write, iclass 17, count 2 2006.201.07:23:42.05#ibcon#*before return 0, iclass 17, count 2 2006.201.07:23:42.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:42.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.07:23:42.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.07:23:42.05#ibcon#ireg 7 cls_cnt 0 2006.201.07:23:42.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:42.17#abcon#<5=/05 2.7 4.3 23.22 881003.1\r\n> 2006.201.07:23:42.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:42.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:42.17#ibcon#enter wrdev, iclass 17, count 0 2006.201.07:23:42.17#ibcon#first serial, iclass 17, count 0 2006.201.07:23:42.17#ibcon#enter sib2, iclass 17, count 0 2006.201.07:23:42.17#ibcon#flushed, iclass 17, count 0 2006.201.07:23:42.17#ibcon#about to write, iclass 17, count 0 2006.201.07:23:42.17#ibcon#wrote, iclass 17, count 0 2006.201.07:23:42.17#ibcon#about to read 3, iclass 17, count 0 2006.201.07:23:42.20#ibcon#read 3, iclass 17, count 0 2006.201.07:23:42.20#ibcon#about to read 4, iclass 17, count 0 2006.201.07:23:42.20#ibcon#read 4, iclass 17, count 0 2006.201.07:23:42.20#ibcon#about to read 5, iclass 17, count 0 2006.201.07:23:42.20#ibcon#read 5, iclass 17, count 0 2006.201.07:23:42.20#ibcon#about to read 6, iclass 17, count 0 2006.201.07:23:42.20#ibcon#read 6, iclass 17, count 0 2006.201.07:23:42.20#ibcon#end of sib2, iclass 17, count 0 2006.201.07:23:42.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.07:23:42.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.07:23:42.20#ibcon#[27=USB\r\n] 2006.201.07:23:42.20#ibcon#*before write, iclass 17, count 0 2006.201.07:23:42.20#ibcon#enter sib2, iclass 17, count 0 2006.201.07:23:42.20#ibcon#flushed, iclass 17, count 0 2006.201.07:23:42.20#ibcon#about to write, iclass 17, count 0 2006.201.07:23:42.20#ibcon#wrote, iclass 17, count 0 2006.201.07:23:42.20#ibcon#about to read 3, iclass 17, count 0 2006.201.07:23:42.20#abcon#{5=INTERFACE CLEAR} 2006.201.07:23:42.23#ibcon#read 3, iclass 17, count 0 2006.201.07:23:42.23#ibcon#about to read 4, iclass 17, count 0 2006.201.07:23:42.23#ibcon#read 4, iclass 17, count 0 2006.201.07:23:42.23#ibcon#about to read 5, iclass 17, count 0 2006.201.07:23:42.23#ibcon#read 5, iclass 17, count 0 2006.201.07:23:42.23#ibcon#about to read 6, iclass 17, count 0 2006.201.07:23:42.23#ibcon#read 6, iclass 17, count 0 2006.201.07:23:42.23#ibcon#end of sib2, iclass 17, count 0 2006.201.07:23:42.23#ibcon#*after write, iclass 17, count 0 2006.201.07:23:42.23#ibcon#*before return 0, iclass 17, count 0 2006.201.07:23:42.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:42.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.07:23:42.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.07:23:42.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.07:23:42.23$vck44/vabw=wide 2006.201.07:23:42.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.07:23:42.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.07:23:42.23#ibcon#ireg 8 cls_cnt 0 2006.201.07:23:42.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:23:42.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:23:42.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:23:42.23#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:23:42.23#ibcon#first serial, iclass 22, count 0 2006.201.07:23:42.23#ibcon#enter sib2, iclass 22, count 0 2006.201.07:23:42.23#ibcon#flushed, iclass 22, count 0 2006.201.07:23:42.23#ibcon#about to write, iclass 22, count 0 2006.201.07:23:42.23#ibcon#wrote, iclass 22, count 0 2006.201.07:23:42.23#ibcon#about to read 3, iclass 22, count 0 2006.201.07:23:42.25#ibcon#read 3, iclass 22, count 0 2006.201.07:23:42.25#ibcon#about to read 4, iclass 22, count 0 2006.201.07:23:42.25#ibcon#read 4, iclass 22, count 0 2006.201.07:23:42.25#ibcon#about to read 5, iclass 22, count 0 2006.201.07:23:42.25#ibcon#read 5, iclass 22, count 0 2006.201.07:23:42.25#ibcon#about to read 6, iclass 22, count 0 2006.201.07:23:42.25#ibcon#read 6, iclass 22, count 0 2006.201.07:23:42.25#ibcon#end of sib2, iclass 22, count 0 2006.201.07:23:42.25#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:23:42.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:23:42.25#ibcon#[25=BW32\r\n] 2006.201.07:23:42.25#ibcon#*before write, iclass 22, count 0 2006.201.07:23:42.25#ibcon#enter sib2, iclass 22, count 0 2006.201.07:23:42.25#ibcon#flushed, iclass 22, count 0 2006.201.07:23:42.25#ibcon#about to write, iclass 22, count 0 2006.201.07:23:42.25#ibcon#wrote, iclass 22, count 0 2006.201.07:23:42.25#ibcon#about to read 3, iclass 22, count 0 2006.201.07:23:42.26#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:23:42.28#ibcon#read 3, iclass 22, count 0 2006.201.07:23:42.28#ibcon#about to read 4, iclass 22, count 0 2006.201.07:23:42.28#ibcon#read 4, iclass 22, count 0 2006.201.07:23:42.28#ibcon#about to read 5, iclass 22, count 0 2006.201.07:23:42.28#ibcon#read 5, iclass 22, count 0 2006.201.07:23:42.28#ibcon#about to read 6, iclass 22, count 0 2006.201.07:23:42.28#ibcon#read 6, iclass 22, count 0 2006.201.07:23:42.28#ibcon#end of sib2, iclass 22, count 0 2006.201.07:23:42.28#ibcon#*after write, iclass 22, count 0 2006.201.07:23:42.28#ibcon#*before return 0, iclass 22, count 0 2006.201.07:23:42.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:23:42.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:23:42.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:23:42.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:23:42.28$vck44/vbbw=wide 2006.201.07:23:42.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.07:23:42.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.07:23:42.28#ibcon#ireg 8 cls_cnt 0 2006.201.07:23:42.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:23:42.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:23:42.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:23:42.35#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:23:42.35#ibcon#first serial, iclass 25, count 0 2006.201.07:23:42.35#ibcon#enter sib2, iclass 25, count 0 2006.201.07:23:42.35#ibcon#flushed, iclass 25, count 0 2006.201.07:23:42.35#ibcon#about to write, iclass 25, count 0 2006.201.07:23:42.35#ibcon#wrote, iclass 25, count 0 2006.201.07:23:42.35#ibcon#about to read 3, iclass 25, count 0 2006.201.07:23:42.37#ibcon#read 3, iclass 25, count 0 2006.201.07:23:42.37#ibcon#about to read 4, iclass 25, count 0 2006.201.07:23:42.37#ibcon#read 4, iclass 25, count 0 2006.201.07:23:42.37#ibcon#about to read 5, iclass 25, count 0 2006.201.07:23:42.37#ibcon#read 5, iclass 25, count 0 2006.201.07:23:42.37#ibcon#about to read 6, iclass 25, count 0 2006.201.07:23:42.37#ibcon#read 6, iclass 25, count 0 2006.201.07:23:42.37#ibcon#end of sib2, iclass 25, count 0 2006.201.07:23:42.37#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:23:42.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:23:42.37#ibcon#[27=BW32\r\n] 2006.201.07:23:42.37#ibcon#*before write, iclass 25, count 0 2006.201.07:23:42.37#ibcon#enter sib2, iclass 25, count 0 2006.201.07:23:42.37#ibcon#flushed, iclass 25, count 0 2006.201.07:23:42.37#ibcon#about to write, iclass 25, count 0 2006.201.07:23:42.37#ibcon#wrote, iclass 25, count 0 2006.201.07:23:42.37#ibcon#about to read 3, iclass 25, count 0 2006.201.07:23:42.40#ibcon#read 3, iclass 25, count 0 2006.201.07:23:42.40#ibcon#about to read 4, iclass 25, count 0 2006.201.07:23:42.40#ibcon#read 4, iclass 25, count 0 2006.201.07:23:42.40#ibcon#about to read 5, iclass 25, count 0 2006.201.07:23:42.40#ibcon#read 5, iclass 25, count 0 2006.201.07:23:42.40#ibcon#about to read 6, iclass 25, count 0 2006.201.07:23:42.40#ibcon#read 6, iclass 25, count 0 2006.201.07:23:42.40#ibcon#end of sib2, iclass 25, count 0 2006.201.07:23:42.40#ibcon#*after write, iclass 25, count 0 2006.201.07:23:42.40#ibcon#*before return 0, iclass 25, count 0 2006.201.07:23:42.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:23:42.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:23:42.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:23:42.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:23:42.40$setupk4/ifdk4 2006.201.07:23:42.40$ifdk4/lo= 2006.201.07:23:42.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:23:42.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:23:42.40$ifdk4/patch= 2006.201.07:23:42.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:23:42.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:23:42.40$setupk4/!*+20s 2006.201.07:23:52.35#abcon#<5=/05 2.7 4.3 23.22 881003.1\r\n> 2006.201.07:23:52.37#abcon#{5=INTERFACE CLEAR} 2006.201.07:23:52.43#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:23:56.87$setupk4/"tpicd 2006.201.07:23:56.87$setupk4/echo=off 2006.201.07:23:56.87$setupk4/xlog=off 2006.201.07:23:56.87:!2006.201.07:25:09 2006.201.07:23:58.14#trakl#Source acquired 2006.201.07:23:59.14#flagr#flagr/antenna,acquired 2006.201.07:25:09.00:preob 2006.201.07:25:09.14/onsource/TRACKING 2006.201.07:25:09.14:!2006.201.07:25:19 2006.201.07:25:19.00:"tape 2006.201.07:25:19.00:"st=record 2006.201.07:25:19.00:data_valid=on 2006.201.07:25:19.00:midob 2006.201.07:25:20.14/onsource/TRACKING 2006.201.07:25:20.14/wx/23.23,1003.0,88 2006.201.07:25:20.31/cable/+6.4674E-03 2006.201.07:25:21.40/va/01,08,usb,yes,27,30 2006.201.07:25:21.40/va/02,07,usb,yes,30,30 2006.201.07:25:21.40/va/03,08,usb,yes,27,28 2006.201.07:25:21.40/va/04,07,usb,yes,30,32 2006.201.07:25:21.40/va/05,04,usb,yes,27,27 2006.201.07:25:21.40/va/06,05,usb,yes,27,27 2006.201.07:25:21.40/va/07,05,usb,yes,26,27 2006.201.07:25:21.40/va/08,04,usb,yes,26,31 2006.201.07:25:21.63/valo/01,524.99,yes,locked 2006.201.07:25:21.63/valo/02,534.99,yes,locked 2006.201.07:25:21.63/valo/03,564.99,yes,locked 2006.201.07:25:21.63/valo/04,624.99,yes,locked 2006.201.07:25:21.63/valo/05,734.99,yes,locked 2006.201.07:25:21.63/valo/06,814.99,yes,locked 2006.201.07:25:21.63/valo/07,864.99,yes,locked 2006.201.07:25:21.63/valo/08,884.99,yes,locked 2006.201.07:25:22.72/vb/01,04,usb,yes,28,26 2006.201.07:25:22.72/vb/02,05,usb,yes,27,27 2006.201.07:25:22.72/vb/03,04,usb,yes,28,30 2006.201.07:25:22.72/vb/04,05,usb,yes,28,27 2006.201.07:25:22.72/vb/05,04,usb,yes,25,27 2006.201.07:25:22.72/vb/06,04,usb,yes,29,25 2006.201.07:25:22.72/vb/07,04,usb,yes,29,28 2006.201.07:25:22.72/vb/08,04,usb,yes,26,30 2006.201.07:25:22.96/vblo/01,629.99,yes,locked 2006.201.07:25:22.96/vblo/02,634.99,yes,locked 2006.201.07:25:22.96/vblo/03,649.99,yes,locked 2006.201.07:25:22.96/vblo/04,679.99,yes,locked 2006.201.07:25:22.96/vblo/05,709.99,yes,locked 2006.201.07:25:22.96/vblo/06,719.99,yes,locked 2006.201.07:25:22.96/vblo/07,734.99,yes,locked 2006.201.07:25:22.96/vblo/08,744.99,yes,locked 2006.201.07:25:23.11/vabw/8 2006.201.07:25:23.26/vbbw/8 2006.201.07:25:23.35/xfe/off,on,14.7 2006.201.07:25:23.73/ifatt/23,28,28,28 2006.201.07:25:24.05/fmout-gps/S +4.56E-07 2006.201.07:25:24.12:!2006.201.07:31:09 2006.201.07:31:09.00:data_valid=off 2006.201.07:31:09.00:"et 2006.201.07:31:09.00:!+3s 2006.201.07:31:12.02:"tape 2006.201.07:31:12.02:postob 2006.201.07:31:12.24/cable/+6.4674E-03 2006.201.07:31:12.24/wx/23.27,1003.0,88 2006.201.07:31:12.31/fmout-gps/S +4.56E-07 2006.201.07:31:12.31:scan_name=201-0739,jd0607,360 2006.201.07:31:12.31:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.201.07:31:13.14#flagr#flagr/antenna,new-source 2006.201.07:31:13.14:checkk5 2006.201.07:31:13.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:31:13.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:31:14.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:31:14.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:31:15.03/chk_obsdata//k5ts1/T2010725??a.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.201.07:31:15.39/chk_obsdata//k5ts2/T2010725??b.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.201.07:31:15.76/chk_obsdata//k5ts3/T2010725??c.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.201.07:31:16.13/chk_obsdata//k5ts4/T2010725??d.dat file size is correct (nominal:1400MB, actual:1396MB). 2006.201.07:31:16.83/k5log//k5ts1_log_newline 2006.201.07:31:17.52/k5log//k5ts2_log_newline 2006.201.07:31:18.22/k5log//k5ts3_log_newline 2006.201.07:31:18.93/k5log//k5ts4_log_newline 2006.201.07:31:18.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:31:18.95:setupk4=1 2006.201.07:31:18.95$setupk4/echo=on 2006.201.07:31:18.95$setupk4/pcalon 2006.201.07:31:18.95$pcalon/"no phase cal control is implemented here 2006.201.07:31:18.95$setupk4/"tpicd=stop 2006.201.07:31:18.95$setupk4/"rec=synch_on 2006.201.07:31:18.95$setupk4/"rec_mode=128 2006.201.07:31:18.95$setupk4/!* 2006.201.07:31:18.95$setupk4/recpk4 2006.201.07:31:18.96$recpk4/recpatch= 2006.201.07:31:18.96$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:31:18.96$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:31:18.96$setupk4/vck44 2006.201.07:31:18.96$vck44/valo=1,524.99 2006.201.07:31:18.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.07:31:18.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.07:31:18.96#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:18.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:18.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:18.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:18.96#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:31:18.96#ibcon#first serial, iclass 26, count 0 2006.201.07:31:18.96#ibcon#enter sib2, iclass 26, count 0 2006.201.07:31:18.96#ibcon#flushed, iclass 26, count 0 2006.201.07:31:18.96#ibcon#about to write, iclass 26, count 0 2006.201.07:31:18.96#ibcon#wrote, iclass 26, count 0 2006.201.07:31:18.96#ibcon#about to read 3, iclass 26, count 0 2006.201.07:31:19.00#ibcon#read 3, iclass 26, count 0 2006.201.07:31:19.00#ibcon#about to read 4, iclass 26, count 0 2006.201.07:31:19.00#ibcon#read 4, iclass 26, count 0 2006.201.07:31:19.00#ibcon#about to read 5, iclass 26, count 0 2006.201.07:31:19.00#ibcon#read 5, iclass 26, count 0 2006.201.07:31:19.00#ibcon#about to read 6, iclass 26, count 0 2006.201.07:31:19.00#ibcon#read 6, iclass 26, count 0 2006.201.07:31:19.00#ibcon#end of sib2, iclass 26, count 0 2006.201.07:31:19.00#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:31:19.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:31:19.00#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:31:19.00#ibcon#*before write, iclass 26, count 0 2006.201.07:31:19.00#ibcon#enter sib2, iclass 26, count 0 2006.201.07:31:19.00#ibcon#flushed, iclass 26, count 0 2006.201.07:31:19.00#ibcon#about to write, iclass 26, count 0 2006.201.07:31:19.00#ibcon#wrote, iclass 26, count 0 2006.201.07:31:19.00#ibcon#about to read 3, iclass 26, count 0 2006.201.07:31:19.05#ibcon#read 3, iclass 26, count 0 2006.201.07:31:19.05#ibcon#about to read 4, iclass 26, count 0 2006.201.07:31:19.05#ibcon#read 4, iclass 26, count 0 2006.201.07:31:19.05#ibcon#about to read 5, iclass 26, count 0 2006.201.07:31:19.05#ibcon#read 5, iclass 26, count 0 2006.201.07:31:19.05#ibcon#about to read 6, iclass 26, count 0 2006.201.07:31:19.05#ibcon#read 6, iclass 26, count 0 2006.201.07:31:19.05#ibcon#end of sib2, iclass 26, count 0 2006.201.07:31:19.05#ibcon#*after write, iclass 26, count 0 2006.201.07:31:19.05#ibcon#*before return 0, iclass 26, count 0 2006.201.07:31:19.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:19.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:19.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:31:19.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:31:19.05$vck44/va=1,8 2006.201.07:31:19.05#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.07:31:19.05#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.07:31:19.05#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:19.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:19.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:19.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:19.05#ibcon#enter wrdev, iclass 28, count 2 2006.201.07:31:19.05#ibcon#first serial, iclass 28, count 2 2006.201.07:31:19.05#ibcon#enter sib2, iclass 28, count 2 2006.201.07:31:19.05#ibcon#flushed, iclass 28, count 2 2006.201.07:31:19.05#ibcon#about to write, iclass 28, count 2 2006.201.07:31:19.05#ibcon#wrote, iclass 28, count 2 2006.201.07:31:19.05#ibcon#about to read 3, iclass 28, count 2 2006.201.07:31:19.07#ibcon#read 3, iclass 28, count 2 2006.201.07:31:19.07#ibcon#about to read 4, iclass 28, count 2 2006.201.07:31:19.07#ibcon#read 4, iclass 28, count 2 2006.201.07:31:19.07#ibcon#about to read 5, iclass 28, count 2 2006.201.07:31:19.07#ibcon#read 5, iclass 28, count 2 2006.201.07:31:19.07#ibcon#about to read 6, iclass 28, count 2 2006.201.07:31:19.07#ibcon#read 6, iclass 28, count 2 2006.201.07:31:19.07#ibcon#end of sib2, iclass 28, count 2 2006.201.07:31:19.07#ibcon#*mode == 0, iclass 28, count 2 2006.201.07:31:19.07#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.07:31:19.07#ibcon#[25=AT01-08\r\n] 2006.201.07:31:19.07#ibcon#*before write, iclass 28, count 2 2006.201.07:31:19.07#ibcon#enter sib2, iclass 28, count 2 2006.201.07:31:19.07#ibcon#flushed, iclass 28, count 2 2006.201.07:31:19.07#ibcon#about to write, iclass 28, count 2 2006.201.07:31:19.07#ibcon#wrote, iclass 28, count 2 2006.201.07:31:19.07#ibcon#about to read 3, iclass 28, count 2 2006.201.07:31:19.10#ibcon#read 3, iclass 28, count 2 2006.201.07:31:19.10#ibcon#about to read 4, iclass 28, count 2 2006.201.07:31:19.10#ibcon#read 4, iclass 28, count 2 2006.201.07:31:19.10#ibcon#about to read 5, iclass 28, count 2 2006.201.07:31:19.10#ibcon#read 5, iclass 28, count 2 2006.201.07:31:19.10#ibcon#about to read 6, iclass 28, count 2 2006.201.07:31:19.10#ibcon#read 6, iclass 28, count 2 2006.201.07:31:19.10#ibcon#end of sib2, iclass 28, count 2 2006.201.07:31:19.10#ibcon#*after write, iclass 28, count 2 2006.201.07:31:19.10#ibcon#*before return 0, iclass 28, count 2 2006.201.07:31:19.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:19.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:19.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.07:31:19.10#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:19.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:19.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:19.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:19.22#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:31:19.22#ibcon#first serial, iclass 28, count 0 2006.201.07:31:19.22#ibcon#enter sib2, iclass 28, count 0 2006.201.07:31:19.22#ibcon#flushed, iclass 28, count 0 2006.201.07:31:19.22#ibcon#about to write, iclass 28, count 0 2006.201.07:31:19.22#ibcon#wrote, iclass 28, count 0 2006.201.07:31:19.22#ibcon#about to read 3, iclass 28, count 0 2006.201.07:31:19.24#ibcon#read 3, iclass 28, count 0 2006.201.07:31:19.24#ibcon#about to read 4, iclass 28, count 0 2006.201.07:31:19.24#ibcon#read 4, iclass 28, count 0 2006.201.07:31:19.24#ibcon#about to read 5, iclass 28, count 0 2006.201.07:31:19.24#ibcon#read 5, iclass 28, count 0 2006.201.07:31:19.24#ibcon#about to read 6, iclass 28, count 0 2006.201.07:31:19.24#ibcon#read 6, iclass 28, count 0 2006.201.07:31:19.24#ibcon#end of sib2, iclass 28, count 0 2006.201.07:31:19.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:31:19.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:31:19.24#ibcon#[25=USB\r\n] 2006.201.07:31:19.24#ibcon#*before write, iclass 28, count 0 2006.201.07:31:19.24#ibcon#enter sib2, iclass 28, count 0 2006.201.07:31:19.24#ibcon#flushed, iclass 28, count 0 2006.201.07:31:19.24#ibcon#about to write, iclass 28, count 0 2006.201.07:31:19.24#ibcon#wrote, iclass 28, count 0 2006.201.07:31:19.24#ibcon#about to read 3, iclass 28, count 0 2006.201.07:31:19.27#ibcon#read 3, iclass 28, count 0 2006.201.07:31:19.27#ibcon#about to read 4, iclass 28, count 0 2006.201.07:31:19.27#ibcon#read 4, iclass 28, count 0 2006.201.07:31:19.27#ibcon#about to read 5, iclass 28, count 0 2006.201.07:31:19.27#ibcon#read 5, iclass 28, count 0 2006.201.07:31:19.27#ibcon#about to read 6, iclass 28, count 0 2006.201.07:31:19.27#ibcon#read 6, iclass 28, count 0 2006.201.07:31:19.27#ibcon#end of sib2, iclass 28, count 0 2006.201.07:31:19.27#ibcon#*after write, iclass 28, count 0 2006.201.07:31:19.27#ibcon#*before return 0, iclass 28, count 0 2006.201.07:31:19.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:19.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:19.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:31:19.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:31:19.27$vck44/valo=2,534.99 2006.201.07:31:19.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.07:31:19.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.07:31:19.27#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:19.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:19.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:19.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:19.27#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:31:19.27#ibcon#first serial, iclass 30, count 0 2006.201.07:31:19.27#ibcon#enter sib2, iclass 30, count 0 2006.201.07:31:19.27#ibcon#flushed, iclass 30, count 0 2006.201.07:31:19.27#ibcon#about to write, iclass 30, count 0 2006.201.07:31:19.27#ibcon#wrote, iclass 30, count 0 2006.201.07:31:19.27#ibcon#about to read 3, iclass 30, count 0 2006.201.07:31:19.29#ibcon#read 3, iclass 30, count 0 2006.201.07:31:19.29#ibcon#about to read 4, iclass 30, count 0 2006.201.07:31:19.29#ibcon#read 4, iclass 30, count 0 2006.201.07:31:19.29#ibcon#about to read 5, iclass 30, count 0 2006.201.07:31:19.29#ibcon#read 5, iclass 30, count 0 2006.201.07:31:19.29#ibcon#about to read 6, iclass 30, count 0 2006.201.07:31:19.29#ibcon#read 6, iclass 30, count 0 2006.201.07:31:19.29#ibcon#end of sib2, iclass 30, count 0 2006.201.07:31:19.29#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:31:19.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:31:19.29#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:31:19.29#ibcon#*before write, iclass 30, count 0 2006.201.07:31:19.29#ibcon#enter sib2, iclass 30, count 0 2006.201.07:31:19.29#ibcon#flushed, iclass 30, count 0 2006.201.07:31:19.29#ibcon#about to write, iclass 30, count 0 2006.201.07:31:19.29#ibcon#wrote, iclass 30, count 0 2006.201.07:31:19.29#ibcon#about to read 3, iclass 30, count 0 2006.201.07:31:19.33#ibcon#read 3, iclass 30, count 0 2006.201.07:31:19.33#ibcon#about to read 4, iclass 30, count 0 2006.201.07:31:19.33#ibcon#read 4, iclass 30, count 0 2006.201.07:31:19.33#ibcon#about to read 5, iclass 30, count 0 2006.201.07:31:19.33#ibcon#read 5, iclass 30, count 0 2006.201.07:31:19.33#ibcon#about to read 6, iclass 30, count 0 2006.201.07:31:19.33#ibcon#read 6, iclass 30, count 0 2006.201.07:31:19.33#ibcon#end of sib2, iclass 30, count 0 2006.201.07:31:19.33#ibcon#*after write, iclass 30, count 0 2006.201.07:31:19.33#ibcon#*before return 0, iclass 30, count 0 2006.201.07:31:19.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:19.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:19.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:31:19.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:31:19.33$vck44/va=2,7 2006.201.07:31:19.33#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.07:31:19.33#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.07:31:19.33#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:19.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:19.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:19.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:19.39#ibcon#enter wrdev, iclass 32, count 2 2006.201.07:31:19.39#ibcon#first serial, iclass 32, count 2 2006.201.07:31:19.39#ibcon#enter sib2, iclass 32, count 2 2006.201.07:31:19.39#ibcon#flushed, iclass 32, count 2 2006.201.07:31:19.39#ibcon#about to write, iclass 32, count 2 2006.201.07:31:19.39#ibcon#wrote, iclass 32, count 2 2006.201.07:31:19.39#ibcon#about to read 3, iclass 32, count 2 2006.201.07:31:19.41#ibcon#read 3, iclass 32, count 2 2006.201.07:31:19.41#ibcon#about to read 4, iclass 32, count 2 2006.201.07:31:19.41#ibcon#read 4, iclass 32, count 2 2006.201.07:31:19.41#ibcon#about to read 5, iclass 32, count 2 2006.201.07:31:19.41#ibcon#read 5, iclass 32, count 2 2006.201.07:31:19.41#ibcon#about to read 6, iclass 32, count 2 2006.201.07:31:19.41#ibcon#read 6, iclass 32, count 2 2006.201.07:31:19.41#ibcon#end of sib2, iclass 32, count 2 2006.201.07:31:19.41#ibcon#*mode == 0, iclass 32, count 2 2006.201.07:31:19.41#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.07:31:19.41#ibcon#[25=AT02-07\r\n] 2006.201.07:31:19.41#ibcon#*before write, iclass 32, count 2 2006.201.07:31:19.41#ibcon#enter sib2, iclass 32, count 2 2006.201.07:31:19.41#ibcon#flushed, iclass 32, count 2 2006.201.07:31:19.41#ibcon#about to write, iclass 32, count 2 2006.201.07:31:19.41#ibcon#wrote, iclass 32, count 2 2006.201.07:31:19.41#ibcon#about to read 3, iclass 32, count 2 2006.201.07:31:19.44#ibcon#read 3, iclass 32, count 2 2006.201.07:31:19.44#ibcon#about to read 4, iclass 32, count 2 2006.201.07:31:19.44#ibcon#read 4, iclass 32, count 2 2006.201.07:31:19.44#ibcon#about to read 5, iclass 32, count 2 2006.201.07:31:19.44#ibcon#read 5, iclass 32, count 2 2006.201.07:31:19.44#ibcon#about to read 6, iclass 32, count 2 2006.201.07:31:19.44#ibcon#read 6, iclass 32, count 2 2006.201.07:31:19.44#ibcon#end of sib2, iclass 32, count 2 2006.201.07:31:19.44#ibcon#*after write, iclass 32, count 2 2006.201.07:31:19.44#ibcon#*before return 0, iclass 32, count 2 2006.201.07:31:19.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:19.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:19.44#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.07:31:19.44#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:19.44#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:19.56#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:19.56#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:19.56#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:31:19.56#ibcon#first serial, iclass 32, count 0 2006.201.07:31:19.56#ibcon#enter sib2, iclass 32, count 0 2006.201.07:31:19.56#ibcon#flushed, iclass 32, count 0 2006.201.07:31:19.56#ibcon#about to write, iclass 32, count 0 2006.201.07:31:19.56#ibcon#wrote, iclass 32, count 0 2006.201.07:31:19.56#ibcon#about to read 3, iclass 32, count 0 2006.201.07:31:19.58#ibcon#read 3, iclass 32, count 0 2006.201.07:31:19.58#ibcon#about to read 4, iclass 32, count 0 2006.201.07:31:19.58#ibcon#read 4, iclass 32, count 0 2006.201.07:31:19.58#ibcon#about to read 5, iclass 32, count 0 2006.201.07:31:19.58#ibcon#read 5, iclass 32, count 0 2006.201.07:31:19.58#ibcon#about to read 6, iclass 32, count 0 2006.201.07:31:19.58#ibcon#read 6, iclass 32, count 0 2006.201.07:31:19.58#ibcon#end of sib2, iclass 32, count 0 2006.201.07:31:19.58#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:31:19.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:31:19.58#ibcon#[25=USB\r\n] 2006.201.07:31:19.58#ibcon#*before write, iclass 32, count 0 2006.201.07:31:19.58#ibcon#enter sib2, iclass 32, count 0 2006.201.07:31:19.58#ibcon#flushed, iclass 32, count 0 2006.201.07:31:19.58#ibcon#about to write, iclass 32, count 0 2006.201.07:31:19.58#ibcon#wrote, iclass 32, count 0 2006.201.07:31:19.58#ibcon#about to read 3, iclass 32, count 0 2006.201.07:31:19.61#ibcon#read 3, iclass 32, count 0 2006.201.07:31:19.61#ibcon#about to read 4, iclass 32, count 0 2006.201.07:31:19.61#ibcon#read 4, iclass 32, count 0 2006.201.07:31:19.61#ibcon#about to read 5, iclass 32, count 0 2006.201.07:31:19.61#ibcon#read 5, iclass 32, count 0 2006.201.07:31:19.61#ibcon#about to read 6, iclass 32, count 0 2006.201.07:31:19.61#ibcon#read 6, iclass 32, count 0 2006.201.07:31:19.61#ibcon#end of sib2, iclass 32, count 0 2006.201.07:31:19.61#ibcon#*after write, iclass 32, count 0 2006.201.07:31:19.61#ibcon#*before return 0, iclass 32, count 0 2006.201.07:31:19.61#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:19.61#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:19.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:31:19.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:31:19.61$vck44/valo=3,564.99 2006.201.07:31:19.61#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.07:31:19.61#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.07:31:19.61#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:19.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:19.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:19.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:19.61#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:31:19.61#ibcon#first serial, iclass 34, count 0 2006.201.07:31:19.61#ibcon#enter sib2, iclass 34, count 0 2006.201.07:31:19.61#ibcon#flushed, iclass 34, count 0 2006.201.07:31:19.61#ibcon#about to write, iclass 34, count 0 2006.201.07:31:19.61#ibcon#wrote, iclass 34, count 0 2006.201.07:31:19.61#ibcon#about to read 3, iclass 34, count 0 2006.201.07:31:19.63#ibcon#read 3, iclass 34, count 0 2006.201.07:31:19.63#ibcon#about to read 4, iclass 34, count 0 2006.201.07:31:19.63#ibcon#read 4, iclass 34, count 0 2006.201.07:31:19.63#ibcon#about to read 5, iclass 34, count 0 2006.201.07:31:19.63#ibcon#read 5, iclass 34, count 0 2006.201.07:31:19.63#ibcon#about to read 6, iclass 34, count 0 2006.201.07:31:19.63#ibcon#read 6, iclass 34, count 0 2006.201.07:31:19.63#ibcon#end of sib2, iclass 34, count 0 2006.201.07:31:19.63#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:31:19.63#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:31:19.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:31:19.63#ibcon#*before write, iclass 34, count 0 2006.201.07:31:19.63#ibcon#enter sib2, iclass 34, count 0 2006.201.07:31:19.63#ibcon#flushed, iclass 34, count 0 2006.201.07:31:19.63#ibcon#about to write, iclass 34, count 0 2006.201.07:31:19.63#ibcon#wrote, iclass 34, count 0 2006.201.07:31:19.63#ibcon#about to read 3, iclass 34, count 0 2006.201.07:31:19.68#ibcon#read 3, iclass 34, count 0 2006.201.07:31:19.68#ibcon#about to read 4, iclass 34, count 0 2006.201.07:31:19.68#ibcon#read 4, iclass 34, count 0 2006.201.07:31:19.68#ibcon#about to read 5, iclass 34, count 0 2006.201.07:31:19.68#ibcon#read 5, iclass 34, count 0 2006.201.07:31:19.68#ibcon#about to read 6, iclass 34, count 0 2006.201.07:31:19.68#ibcon#read 6, iclass 34, count 0 2006.201.07:31:19.68#ibcon#end of sib2, iclass 34, count 0 2006.201.07:31:19.68#ibcon#*after write, iclass 34, count 0 2006.201.07:31:19.68#ibcon#*before return 0, iclass 34, count 0 2006.201.07:31:19.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:19.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:19.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:31:19.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:31:19.68$vck44/va=3,8 2006.201.07:31:19.68#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.07:31:19.68#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.07:31:19.68#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:19.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:19.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:19.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:19.73#ibcon#enter wrdev, iclass 36, count 2 2006.201.07:31:19.73#ibcon#first serial, iclass 36, count 2 2006.201.07:31:19.73#ibcon#enter sib2, iclass 36, count 2 2006.201.07:31:19.73#ibcon#flushed, iclass 36, count 2 2006.201.07:31:19.73#ibcon#about to write, iclass 36, count 2 2006.201.07:31:19.73#ibcon#wrote, iclass 36, count 2 2006.201.07:31:19.73#ibcon#about to read 3, iclass 36, count 2 2006.201.07:31:19.75#ibcon#read 3, iclass 36, count 2 2006.201.07:31:19.75#ibcon#about to read 4, iclass 36, count 2 2006.201.07:31:19.75#ibcon#read 4, iclass 36, count 2 2006.201.07:31:19.75#ibcon#about to read 5, iclass 36, count 2 2006.201.07:31:19.75#ibcon#read 5, iclass 36, count 2 2006.201.07:31:19.75#ibcon#about to read 6, iclass 36, count 2 2006.201.07:31:19.75#ibcon#read 6, iclass 36, count 2 2006.201.07:31:19.75#ibcon#end of sib2, iclass 36, count 2 2006.201.07:31:19.75#ibcon#*mode == 0, iclass 36, count 2 2006.201.07:31:19.75#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.07:31:19.75#ibcon#[25=AT03-08\r\n] 2006.201.07:31:19.75#ibcon#*before write, iclass 36, count 2 2006.201.07:31:19.75#ibcon#enter sib2, iclass 36, count 2 2006.201.07:31:19.75#ibcon#flushed, iclass 36, count 2 2006.201.07:31:19.75#ibcon#about to write, iclass 36, count 2 2006.201.07:31:19.75#ibcon#wrote, iclass 36, count 2 2006.201.07:31:19.75#ibcon#about to read 3, iclass 36, count 2 2006.201.07:31:19.78#ibcon#read 3, iclass 36, count 2 2006.201.07:31:19.78#ibcon#about to read 4, iclass 36, count 2 2006.201.07:31:19.78#ibcon#read 4, iclass 36, count 2 2006.201.07:31:19.78#ibcon#about to read 5, iclass 36, count 2 2006.201.07:31:19.78#ibcon#read 5, iclass 36, count 2 2006.201.07:31:19.78#ibcon#about to read 6, iclass 36, count 2 2006.201.07:31:19.78#ibcon#read 6, iclass 36, count 2 2006.201.07:31:19.78#ibcon#end of sib2, iclass 36, count 2 2006.201.07:31:19.78#ibcon#*after write, iclass 36, count 2 2006.201.07:31:19.78#ibcon#*before return 0, iclass 36, count 2 2006.201.07:31:19.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:19.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:19.78#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.07:31:19.78#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:19.78#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:19.90#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:19.90#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:19.90#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:31:19.90#ibcon#first serial, iclass 36, count 0 2006.201.07:31:19.90#ibcon#enter sib2, iclass 36, count 0 2006.201.07:31:19.90#ibcon#flushed, iclass 36, count 0 2006.201.07:31:19.90#ibcon#about to write, iclass 36, count 0 2006.201.07:31:19.90#ibcon#wrote, iclass 36, count 0 2006.201.07:31:19.90#ibcon#about to read 3, iclass 36, count 0 2006.201.07:31:19.92#ibcon#read 3, iclass 36, count 0 2006.201.07:31:19.92#ibcon#about to read 4, iclass 36, count 0 2006.201.07:31:19.92#ibcon#read 4, iclass 36, count 0 2006.201.07:31:19.92#ibcon#about to read 5, iclass 36, count 0 2006.201.07:31:19.92#ibcon#read 5, iclass 36, count 0 2006.201.07:31:19.92#ibcon#about to read 6, iclass 36, count 0 2006.201.07:31:19.92#ibcon#read 6, iclass 36, count 0 2006.201.07:31:19.92#ibcon#end of sib2, iclass 36, count 0 2006.201.07:31:19.92#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:31:19.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:31:19.92#ibcon#[25=USB\r\n] 2006.201.07:31:19.92#ibcon#*before write, iclass 36, count 0 2006.201.07:31:19.92#ibcon#enter sib2, iclass 36, count 0 2006.201.07:31:19.92#ibcon#flushed, iclass 36, count 0 2006.201.07:31:19.92#ibcon#about to write, iclass 36, count 0 2006.201.07:31:19.92#ibcon#wrote, iclass 36, count 0 2006.201.07:31:19.92#ibcon#about to read 3, iclass 36, count 0 2006.201.07:31:19.95#ibcon#read 3, iclass 36, count 0 2006.201.07:31:19.95#ibcon#about to read 4, iclass 36, count 0 2006.201.07:31:19.95#ibcon#read 4, iclass 36, count 0 2006.201.07:31:19.95#ibcon#about to read 5, iclass 36, count 0 2006.201.07:31:19.95#ibcon#read 5, iclass 36, count 0 2006.201.07:31:19.95#ibcon#about to read 6, iclass 36, count 0 2006.201.07:31:19.95#ibcon#read 6, iclass 36, count 0 2006.201.07:31:19.95#ibcon#end of sib2, iclass 36, count 0 2006.201.07:31:19.95#ibcon#*after write, iclass 36, count 0 2006.201.07:31:19.95#ibcon#*before return 0, iclass 36, count 0 2006.201.07:31:19.95#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:19.95#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:19.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:31:19.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:31:19.95$vck44/valo=4,624.99 2006.201.07:31:19.95#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.07:31:19.95#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.07:31:19.95#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:19.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:19.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:19.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:19.95#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:31:19.95#ibcon#first serial, iclass 38, count 0 2006.201.07:31:19.95#ibcon#enter sib2, iclass 38, count 0 2006.201.07:31:19.95#ibcon#flushed, iclass 38, count 0 2006.201.07:31:19.95#ibcon#about to write, iclass 38, count 0 2006.201.07:31:19.95#ibcon#wrote, iclass 38, count 0 2006.201.07:31:19.95#ibcon#about to read 3, iclass 38, count 0 2006.201.07:31:19.97#ibcon#read 3, iclass 38, count 0 2006.201.07:31:19.97#ibcon#about to read 4, iclass 38, count 0 2006.201.07:31:19.97#ibcon#read 4, iclass 38, count 0 2006.201.07:31:19.97#ibcon#about to read 5, iclass 38, count 0 2006.201.07:31:19.97#ibcon#read 5, iclass 38, count 0 2006.201.07:31:19.97#ibcon#about to read 6, iclass 38, count 0 2006.201.07:31:19.97#ibcon#read 6, iclass 38, count 0 2006.201.07:31:19.97#ibcon#end of sib2, iclass 38, count 0 2006.201.07:31:19.97#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:31:19.97#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:31:19.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:31:19.97#ibcon#*before write, iclass 38, count 0 2006.201.07:31:19.97#ibcon#enter sib2, iclass 38, count 0 2006.201.07:31:19.97#ibcon#flushed, iclass 38, count 0 2006.201.07:31:19.97#ibcon#about to write, iclass 38, count 0 2006.201.07:31:19.97#ibcon#wrote, iclass 38, count 0 2006.201.07:31:19.97#ibcon#about to read 3, iclass 38, count 0 2006.201.07:31:20.01#ibcon#read 3, iclass 38, count 0 2006.201.07:31:20.01#ibcon#about to read 4, iclass 38, count 0 2006.201.07:31:20.01#ibcon#read 4, iclass 38, count 0 2006.201.07:31:20.01#ibcon#about to read 5, iclass 38, count 0 2006.201.07:31:20.01#ibcon#read 5, iclass 38, count 0 2006.201.07:31:20.01#ibcon#about to read 6, iclass 38, count 0 2006.201.07:31:20.01#ibcon#read 6, iclass 38, count 0 2006.201.07:31:20.01#ibcon#end of sib2, iclass 38, count 0 2006.201.07:31:20.01#ibcon#*after write, iclass 38, count 0 2006.201.07:31:20.01#ibcon#*before return 0, iclass 38, count 0 2006.201.07:31:20.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:20.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:20.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:31:20.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:31:20.01$vck44/va=4,7 2006.201.07:31:20.01#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.07:31:20.01#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.07:31:20.01#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:20.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:20.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:20.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:20.07#ibcon#enter wrdev, iclass 40, count 2 2006.201.07:31:20.07#ibcon#first serial, iclass 40, count 2 2006.201.07:31:20.07#ibcon#enter sib2, iclass 40, count 2 2006.201.07:31:20.07#ibcon#flushed, iclass 40, count 2 2006.201.07:31:20.07#ibcon#about to write, iclass 40, count 2 2006.201.07:31:20.07#ibcon#wrote, iclass 40, count 2 2006.201.07:31:20.07#ibcon#about to read 3, iclass 40, count 2 2006.201.07:31:20.09#ibcon#read 3, iclass 40, count 2 2006.201.07:31:20.09#ibcon#about to read 4, iclass 40, count 2 2006.201.07:31:20.09#ibcon#read 4, iclass 40, count 2 2006.201.07:31:20.09#ibcon#about to read 5, iclass 40, count 2 2006.201.07:31:20.09#ibcon#read 5, iclass 40, count 2 2006.201.07:31:20.09#ibcon#about to read 6, iclass 40, count 2 2006.201.07:31:20.09#ibcon#read 6, iclass 40, count 2 2006.201.07:31:20.09#ibcon#end of sib2, iclass 40, count 2 2006.201.07:31:20.09#ibcon#*mode == 0, iclass 40, count 2 2006.201.07:31:20.09#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.07:31:20.09#ibcon#[25=AT04-07\r\n] 2006.201.07:31:20.09#ibcon#*before write, iclass 40, count 2 2006.201.07:31:20.09#ibcon#enter sib2, iclass 40, count 2 2006.201.07:31:20.09#ibcon#flushed, iclass 40, count 2 2006.201.07:31:20.09#ibcon#about to write, iclass 40, count 2 2006.201.07:31:20.09#ibcon#wrote, iclass 40, count 2 2006.201.07:31:20.09#ibcon#about to read 3, iclass 40, count 2 2006.201.07:31:20.12#ibcon#read 3, iclass 40, count 2 2006.201.07:31:20.12#ibcon#about to read 4, iclass 40, count 2 2006.201.07:31:20.12#ibcon#read 4, iclass 40, count 2 2006.201.07:31:20.12#ibcon#about to read 5, iclass 40, count 2 2006.201.07:31:20.12#ibcon#read 5, iclass 40, count 2 2006.201.07:31:20.12#ibcon#about to read 6, iclass 40, count 2 2006.201.07:31:20.12#ibcon#read 6, iclass 40, count 2 2006.201.07:31:20.12#ibcon#end of sib2, iclass 40, count 2 2006.201.07:31:20.12#ibcon#*after write, iclass 40, count 2 2006.201.07:31:20.12#ibcon#*before return 0, iclass 40, count 2 2006.201.07:31:20.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:20.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:20.12#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.07:31:20.12#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:20.12#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:20.24#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:20.24#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:20.24#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:31:20.24#ibcon#first serial, iclass 40, count 0 2006.201.07:31:20.24#ibcon#enter sib2, iclass 40, count 0 2006.201.07:31:20.24#ibcon#flushed, iclass 40, count 0 2006.201.07:31:20.24#ibcon#about to write, iclass 40, count 0 2006.201.07:31:20.24#ibcon#wrote, iclass 40, count 0 2006.201.07:31:20.24#ibcon#about to read 3, iclass 40, count 0 2006.201.07:31:20.26#ibcon#read 3, iclass 40, count 0 2006.201.07:31:20.26#ibcon#about to read 4, iclass 40, count 0 2006.201.07:31:20.26#ibcon#read 4, iclass 40, count 0 2006.201.07:31:20.26#ibcon#about to read 5, iclass 40, count 0 2006.201.07:31:20.26#ibcon#read 5, iclass 40, count 0 2006.201.07:31:20.26#ibcon#about to read 6, iclass 40, count 0 2006.201.07:31:20.26#ibcon#read 6, iclass 40, count 0 2006.201.07:31:20.26#ibcon#end of sib2, iclass 40, count 0 2006.201.07:31:20.26#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:31:20.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:31:20.26#ibcon#[25=USB\r\n] 2006.201.07:31:20.26#ibcon#*before write, iclass 40, count 0 2006.201.07:31:20.26#ibcon#enter sib2, iclass 40, count 0 2006.201.07:31:20.26#ibcon#flushed, iclass 40, count 0 2006.201.07:31:20.26#ibcon#about to write, iclass 40, count 0 2006.201.07:31:20.26#ibcon#wrote, iclass 40, count 0 2006.201.07:31:20.26#ibcon#about to read 3, iclass 40, count 0 2006.201.07:31:20.29#ibcon#read 3, iclass 40, count 0 2006.201.07:31:20.29#ibcon#about to read 4, iclass 40, count 0 2006.201.07:31:20.29#ibcon#read 4, iclass 40, count 0 2006.201.07:31:20.29#ibcon#about to read 5, iclass 40, count 0 2006.201.07:31:20.29#ibcon#read 5, iclass 40, count 0 2006.201.07:31:20.29#ibcon#about to read 6, iclass 40, count 0 2006.201.07:31:20.29#ibcon#read 6, iclass 40, count 0 2006.201.07:31:20.29#ibcon#end of sib2, iclass 40, count 0 2006.201.07:31:20.29#ibcon#*after write, iclass 40, count 0 2006.201.07:31:20.29#ibcon#*before return 0, iclass 40, count 0 2006.201.07:31:20.29#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:20.29#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:20.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:31:20.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:31:20.29$vck44/valo=5,734.99 2006.201.07:31:20.29#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.07:31:20.29#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.07:31:20.29#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:20.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:20.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:20.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:20.29#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:31:20.29#ibcon#first serial, iclass 4, count 0 2006.201.07:31:20.29#ibcon#enter sib2, iclass 4, count 0 2006.201.07:31:20.29#ibcon#flushed, iclass 4, count 0 2006.201.07:31:20.29#ibcon#about to write, iclass 4, count 0 2006.201.07:31:20.29#ibcon#wrote, iclass 4, count 0 2006.201.07:31:20.29#ibcon#about to read 3, iclass 4, count 0 2006.201.07:31:20.31#ibcon#read 3, iclass 4, count 0 2006.201.07:31:20.31#ibcon#about to read 4, iclass 4, count 0 2006.201.07:31:20.31#ibcon#read 4, iclass 4, count 0 2006.201.07:31:20.31#ibcon#about to read 5, iclass 4, count 0 2006.201.07:31:20.31#ibcon#read 5, iclass 4, count 0 2006.201.07:31:20.31#ibcon#about to read 6, iclass 4, count 0 2006.201.07:31:20.31#ibcon#read 6, iclass 4, count 0 2006.201.07:31:20.31#ibcon#end of sib2, iclass 4, count 0 2006.201.07:31:20.31#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:31:20.31#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:31:20.31#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:31:20.31#ibcon#*before write, iclass 4, count 0 2006.201.07:31:20.31#ibcon#enter sib2, iclass 4, count 0 2006.201.07:31:20.31#ibcon#flushed, iclass 4, count 0 2006.201.07:31:20.31#ibcon#about to write, iclass 4, count 0 2006.201.07:31:20.31#ibcon#wrote, iclass 4, count 0 2006.201.07:31:20.31#ibcon#about to read 3, iclass 4, count 0 2006.201.07:31:20.35#ibcon#read 3, iclass 4, count 0 2006.201.07:31:20.35#ibcon#about to read 4, iclass 4, count 0 2006.201.07:31:20.35#ibcon#read 4, iclass 4, count 0 2006.201.07:31:20.35#ibcon#about to read 5, iclass 4, count 0 2006.201.07:31:20.35#ibcon#read 5, iclass 4, count 0 2006.201.07:31:20.35#ibcon#about to read 6, iclass 4, count 0 2006.201.07:31:20.35#ibcon#read 6, iclass 4, count 0 2006.201.07:31:20.35#ibcon#end of sib2, iclass 4, count 0 2006.201.07:31:20.35#ibcon#*after write, iclass 4, count 0 2006.201.07:31:20.35#ibcon#*before return 0, iclass 4, count 0 2006.201.07:31:20.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:20.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:20.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:31:20.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:31:20.35$vck44/va=5,4 2006.201.07:31:20.35#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.07:31:20.35#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.07:31:20.35#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:20.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:31:20.39#abcon#<5=/05 2.9 4.6 23.27 881003.0\r\n> 2006.201.07:31:20.41#abcon#{5=INTERFACE CLEAR} 2006.201.07:31:20.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:31:20.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:31:20.41#ibcon#enter wrdev, iclass 7, count 2 2006.201.07:31:20.41#ibcon#first serial, iclass 7, count 2 2006.201.07:31:20.41#ibcon#enter sib2, iclass 7, count 2 2006.201.07:31:20.41#ibcon#flushed, iclass 7, count 2 2006.201.07:31:20.41#ibcon#about to write, iclass 7, count 2 2006.201.07:31:20.41#ibcon#wrote, iclass 7, count 2 2006.201.07:31:20.41#ibcon#about to read 3, iclass 7, count 2 2006.201.07:31:20.43#ibcon#read 3, iclass 7, count 2 2006.201.07:31:20.43#ibcon#about to read 4, iclass 7, count 2 2006.201.07:31:20.43#ibcon#read 4, iclass 7, count 2 2006.201.07:31:20.43#ibcon#about to read 5, iclass 7, count 2 2006.201.07:31:20.43#ibcon#read 5, iclass 7, count 2 2006.201.07:31:20.43#ibcon#about to read 6, iclass 7, count 2 2006.201.07:31:20.43#ibcon#read 6, iclass 7, count 2 2006.201.07:31:20.43#ibcon#end of sib2, iclass 7, count 2 2006.201.07:31:20.43#ibcon#*mode == 0, iclass 7, count 2 2006.201.07:31:20.43#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.07:31:20.43#ibcon#[25=AT05-04\r\n] 2006.201.07:31:20.43#ibcon#*before write, iclass 7, count 2 2006.201.07:31:20.43#ibcon#enter sib2, iclass 7, count 2 2006.201.07:31:20.43#ibcon#flushed, iclass 7, count 2 2006.201.07:31:20.43#ibcon#about to write, iclass 7, count 2 2006.201.07:31:20.43#ibcon#wrote, iclass 7, count 2 2006.201.07:31:20.43#ibcon#about to read 3, iclass 7, count 2 2006.201.07:31:20.46#ibcon#read 3, iclass 7, count 2 2006.201.07:31:20.46#ibcon#about to read 4, iclass 7, count 2 2006.201.07:31:20.46#ibcon#read 4, iclass 7, count 2 2006.201.07:31:20.46#ibcon#about to read 5, iclass 7, count 2 2006.201.07:31:20.46#ibcon#read 5, iclass 7, count 2 2006.201.07:31:20.46#ibcon#about to read 6, iclass 7, count 2 2006.201.07:31:20.46#ibcon#read 6, iclass 7, count 2 2006.201.07:31:20.46#ibcon#end of sib2, iclass 7, count 2 2006.201.07:31:20.46#ibcon#*after write, iclass 7, count 2 2006.201.07:31:20.46#ibcon#*before return 0, iclass 7, count 2 2006.201.07:31:20.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:31:20.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.07:31:20.46#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.07:31:20.46#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:20.46#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:31:20.47#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:31:20.58#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:31:20.58#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:31:20.58#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:31:20.58#ibcon#first serial, iclass 7, count 0 2006.201.07:31:20.58#ibcon#enter sib2, iclass 7, count 0 2006.201.07:31:20.58#ibcon#flushed, iclass 7, count 0 2006.201.07:31:20.58#ibcon#about to write, iclass 7, count 0 2006.201.07:31:20.58#ibcon#wrote, iclass 7, count 0 2006.201.07:31:20.58#ibcon#about to read 3, iclass 7, count 0 2006.201.07:31:20.60#ibcon#read 3, iclass 7, count 0 2006.201.07:31:20.60#ibcon#about to read 4, iclass 7, count 0 2006.201.07:31:20.60#ibcon#read 4, iclass 7, count 0 2006.201.07:31:20.60#ibcon#about to read 5, iclass 7, count 0 2006.201.07:31:20.60#ibcon#read 5, iclass 7, count 0 2006.201.07:31:20.60#ibcon#about to read 6, iclass 7, count 0 2006.201.07:31:20.60#ibcon#read 6, iclass 7, count 0 2006.201.07:31:20.60#ibcon#end of sib2, iclass 7, count 0 2006.201.07:31:20.60#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:31:20.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:31:20.60#ibcon#[25=USB\r\n] 2006.201.07:31:20.60#ibcon#*before write, iclass 7, count 0 2006.201.07:31:20.60#ibcon#enter sib2, iclass 7, count 0 2006.201.07:31:20.60#ibcon#flushed, iclass 7, count 0 2006.201.07:31:20.60#ibcon#about to write, iclass 7, count 0 2006.201.07:31:20.60#ibcon#wrote, iclass 7, count 0 2006.201.07:31:20.60#ibcon#about to read 3, iclass 7, count 0 2006.201.07:31:20.63#ibcon#read 3, iclass 7, count 0 2006.201.07:31:20.63#ibcon#about to read 4, iclass 7, count 0 2006.201.07:31:20.63#ibcon#read 4, iclass 7, count 0 2006.201.07:31:20.63#ibcon#about to read 5, iclass 7, count 0 2006.201.07:31:20.63#ibcon#read 5, iclass 7, count 0 2006.201.07:31:20.63#ibcon#about to read 6, iclass 7, count 0 2006.201.07:31:20.63#ibcon#read 6, iclass 7, count 0 2006.201.07:31:20.63#ibcon#end of sib2, iclass 7, count 0 2006.201.07:31:20.63#ibcon#*after write, iclass 7, count 0 2006.201.07:31:20.63#ibcon#*before return 0, iclass 7, count 0 2006.201.07:31:20.63#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:31:20.63#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.07:31:20.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:31:20.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:31:20.63$vck44/valo=6,814.99 2006.201.07:31:20.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.07:31:20.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.07:31:20.63#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:20.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:20.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:20.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:20.63#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:31:20.63#ibcon#first serial, iclass 14, count 0 2006.201.07:31:20.63#ibcon#enter sib2, iclass 14, count 0 2006.201.07:31:20.63#ibcon#flushed, iclass 14, count 0 2006.201.07:31:20.63#ibcon#about to write, iclass 14, count 0 2006.201.07:31:20.63#ibcon#wrote, iclass 14, count 0 2006.201.07:31:20.63#ibcon#about to read 3, iclass 14, count 0 2006.201.07:31:20.65#ibcon#read 3, iclass 14, count 0 2006.201.07:31:20.65#ibcon#about to read 4, iclass 14, count 0 2006.201.07:31:20.65#ibcon#read 4, iclass 14, count 0 2006.201.07:31:20.65#ibcon#about to read 5, iclass 14, count 0 2006.201.07:31:20.65#ibcon#read 5, iclass 14, count 0 2006.201.07:31:20.65#ibcon#about to read 6, iclass 14, count 0 2006.201.07:31:20.65#ibcon#read 6, iclass 14, count 0 2006.201.07:31:20.65#ibcon#end of sib2, iclass 14, count 0 2006.201.07:31:20.65#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:31:20.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:31:20.65#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:31:20.65#ibcon#*before write, iclass 14, count 0 2006.201.07:31:20.65#ibcon#enter sib2, iclass 14, count 0 2006.201.07:31:20.65#ibcon#flushed, iclass 14, count 0 2006.201.07:31:20.65#ibcon#about to write, iclass 14, count 0 2006.201.07:31:20.65#ibcon#wrote, iclass 14, count 0 2006.201.07:31:20.65#ibcon#about to read 3, iclass 14, count 0 2006.201.07:31:20.69#ibcon#read 3, iclass 14, count 0 2006.201.07:31:20.69#ibcon#about to read 4, iclass 14, count 0 2006.201.07:31:20.69#ibcon#read 4, iclass 14, count 0 2006.201.07:31:20.69#ibcon#about to read 5, iclass 14, count 0 2006.201.07:31:20.69#ibcon#read 5, iclass 14, count 0 2006.201.07:31:20.69#ibcon#about to read 6, iclass 14, count 0 2006.201.07:31:20.69#ibcon#read 6, iclass 14, count 0 2006.201.07:31:20.69#ibcon#end of sib2, iclass 14, count 0 2006.201.07:31:20.69#ibcon#*after write, iclass 14, count 0 2006.201.07:31:20.69#ibcon#*before return 0, iclass 14, count 0 2006.201.07:31:20.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:20.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:20.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:31:20.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:31:20.69$vck44/va=6,5 2006.201.07:31:20.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.07:31:20.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.07:31:20.69#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:20.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:20.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:20.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:20.75#ibcon#enter wrdev, iclass 16, count 2 2006.201.07:31:20.75#ibcon#first serial, iclass 16, count 2 2006.201.07:31:20.75#ibcon#enter sib2, iclass 16, count 2 2006.201.07:31:20.75#ibcon#flushed, iclass 16, count 2 2006.201.07:31:20.75#ibcon#about to write, iclass 16, count 2 2006.201.07:31:20.75#ibcon#wrote, iclass 16, count 2 2006.201.07:31:20.75#ibcon#about to read 3, iclass 16, count 2 2006.201.07:31:20.77#ibcon#read 3, iclass 16, count 2 2006.201.07:31:20.77#ibcon#about to read 4, iclass 16, count 2 2006.201.07:31:20.77#ibcon#read 4, iclass 16, count 2 2006.201.07:31:20.77#ibcon#about to read 5, iclass 16, count 2 2006.201.07:31:20.77#ibcon#read 5, iclass 16, count 2 2006.201.07:31:20.77#ibcon#about to read 6, iclass 16, count 2 2006.201.07:31:20.77#ibcon#read 6, iclass 16, count 2 2006.201.07:31:20.77#ibcon#end of sib2, iclass 16, count 2 2006.201.07:31:20.77#ibcon#*mode == 0, iclass 16, count 2 2006.201.07:31:20.77#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.07:31:20.77#ibcon#[25=AT06-05\r\n] 2006.201.07:31:20.77#ibcon#*before write, iclass 16, count 2 2006.201.07:31:20.77#ibcon#enter sib2, iclass 16, count 2 2006.201.07:31:20.77#ibcon#flushed, iclass 16, count 2 2006.201.07:31:20.77#ibcon#about to write, iclass 16, count 2 2006.201.07:31:20.77#ibcon#wrote, iclass 16, count 2 2006.201.07:31:20.77#ibcon#about to read 3, iclass 16, count 2 2006.201.07:31:20.80#ibcon#read 3, iclass 16, count 2 2006.201.07:31:20.80#ibcon#about to read 4, iclass 16, count 2 2006.201.07:31:20.80#ibcon#read 4, iclass 16, count 2 2006.201.07:31:20.80#ibcon#about to read 5, iclass 16, count 2 2006.201.07:31:20.80#ibcon#read 5, iclass 16, count 2 2006.201.07:31:20.80#ibcon#about to read 6, iclass 16, count 2 2006.201.07:31:20.80#ibcon#read 6, iclass 16, count 2 2006.201.07:31:20.80#ibcon#end of sib2, iclass 16, count 2 2006.201.07:31:20.80#ibcon#*after write, iclass 16, count 2 2006.201.07:31:20.80#ibcon#*before return 0, iclass 16, count 2 2006.201.07:31:20.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:20.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:20.80#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.07:31:20.80#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:20.80#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:20.92#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:20.92#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:20.92#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:31:20.92#ibcon#first serial, iclass 16, count 0 2006.201.07:31:20.92#ibcon#enter sib2, iclass 16, count 0 2006.201.07:31:20.92#ibcon#flushed, iclass 16, count 0 2006.201.07:31:20.92#ibcon#about to write, iclass 16, count 0 2006.201.07:31:20.92#ibcon#wrote, iclass 16, count 0 2006.201.07:31:20.92#ibcon#about to read 3, iclass 16, count 0 2006.201.07:31:20.94#ibcon#read 3, iclass 16, count 0 2006.201.07:31:20.94#ibcon#about to read 4, iclass 16, count 0 2006.201.07:31:20.94#ibcon#read 4, iclass 16, count 0 2006.201.07:31:20.94#ibcon#about to read 5, iclass 16, count 0 2006.201.07:31:20.94#ibcon#read 5, iclass 16, count 0 2006.201.07:31:20.94#ibcon#about to read 6, iclass 16, count 0 2006.201.07:31:20.94#ibcon#read 6, iclass 16, count 0 2006.201.07:31:20.94#ibcon#end of sib2, iclass 16, count 0 2006.201.07:31:20.94#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:31:20.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:31:20.94#ibcon#[25=USB\r\n] 2006.201.07:31:20.94#ibcon#*before write, iclass 16, count 0 2006.201.07:31:20.94#ibcon#enter sib2, iclass 16, count 0 2006.201.07:31:20.94#ibcon#flushed, iclass 16, count 0 2006.201.07:31:20.94#ibcon#about to write, iclass 16, count 0 2006.201.07:31:20.94#ibcon#wrote, iclass 16, count 0 2006.201.07:31:20.94#ibcon#about to read 3, iclass 16, count 0 2006.201.07:31:20.97#ibcon#read 3, iclass 16, count 0 2006.201.07:31:20.97#ibcon#about to read 4, iclass 16, count 0 2006.201.07:31:20.97#ibcon#read 4, iclass 16, count 0 2006.201.07:31:20.97#ibcon#about to read 5, iclass 16, count 0 2006.201.07:31:20.97#ibcon#read 5, iclass 16, count 0 2006.201.07:31:20.97#ibcon#about to read 6, iclass 16, count 0 2006.201.07:31:20.97#ibcon#read 6, iclass 16, count 0 2006.201.07:31:20.97#ibcon#end of sib2, iclass 16, count 0 2006.201.07:31:20.97#ibcon#*after write, iclass 16, count 0 2006.201.07:31:20.97#ibcon#*before return 0, iclass 16, count 0 2006.201.07:31:20.97#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:20.97#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:20.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:31:20.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:31:20.97$vck44/valo=7,864.99 2006.201.07:31:20.97#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.07:31:20.97#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.07:31:20.97#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:20.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:20.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:20.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:20.97#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:31:20.97#ibcon#first serial, iclass 18, count 0 2006.201.07:31:20.97#ibcon#enter sib2, iclass 18, count 0 2006.201.07:31:20.97#ibcon#flushed, iclass 18, count 0 2006.201.07:31:20.97#ibcon#about to write, iclass 18, count 0 2006.201.07:31:20.97#ibcon#wrote, iclass 18, count 0 2006.201.07:31:20.97#ibcon#about to read 3, iclass 18, count 0 2006.201.07:31:20.99#ibcon#read 3, iclass 18, count 0 2006.201.07:31:20.99#ibcon#about to read 4, iclass 18, count 0 2006.201.07:31:20.99#ibcon#read 4, iclass 18, count 0 2006.201.07:31:20.99#ibcon#about to read 5, iclass 18, count 0 2006.201.07:31:20.99#ibcon#read 5, iclass 18, count 0 2006.201.07:31:20.99#ibcon#about to read 6, iclass 18, count 0 2006.201.07:31:20.99#ibcon#read 6, iclass 18, count 0 2006.201.07:31:20.99#ibcon#end of sib2, iclass 18, count 0 2006.201.07:31:20.99#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:31:20.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:31:20.99#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:31:20.99#ibcon#*before write, iclass 18, count 0 2006.201.07:31:20.99#ibcon#enter sib2, iclass 18, count 0 2006.201.07:31:20.99#ibcon#flushed, iclass 18, count 0 2006.201.07:31:20.99#ibcon#about to write, iclass 18, count 0 2006.201.07:31:20.99#ibcon#wrote, iclass 18, count 0 2006.201.07:31:20.99#ibcon#about to read 3, iclass 18, count 0 2006.201.07:31:21.03#ibcon#read 3, iclass 18, count 0 2006.201.07:31:21.03#ibcon#about to read 4, iclass 18, count 0 2006.201.07:31:21.03#ibcon#read 4, iclass 18, count 0 2006.201.07:31:21.03#ibcon#about to read 5, iclass 18, count 0 2006.201.07:31:21.03#ibcon#read 5, iclass 18, count 0 2006.201.07:31:21.03#ibcon#about to read 6, iclass 18, count 0 2006.201.07:31:21.03#ibcon#read 6, iclass 18, count 0 2006.201.07:31:21.03#ibcon#end of sib2, iclass 18, count 0 2006.201.07:31:21.03#ibcon#*after write, iclass 18, count 0 2006.201.07:31:21.03#ibcon#*before return 0, iclass 18, count 0 2006.201.07:31:21.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:21.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:21.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:31:21.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:31:21.03$vck44/va=7,5 2006.201.07:31:21.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.07:31:21.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.07:31:21.03#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:21.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:21.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:21.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:21.09#ibcon#enter wrdev, iclass 20, count 2 2006.201.07:31:21.09#ibcon#first serial, iclass 20, count 2 2006.201.07:31:21.09#ibcon#enter sib2, iclass 20, count 2 2006.201.07:31:21.09#ibcon#flushed, iclass 20, count 2 2006.201.07:31:21.09#ibcon#about to write, iclass 20, count 2 2006.201.07:31:21.09#ibcon#wrote, iclass 20, count 2 2006.201.07:31:21.09#ibcon#about to read 3, iclass 20, count 2 2006.201.07:31:21.11#ibcon#read 3, iclass 20, count 2 2006.201.07:31:21.11#ibcon#about to read 4, iclass 20, count 2 2006.201.07:31:21.11#ibcon#read 4, iclass 20, count 2 2006.201.07:31:21.11#ibcon#about to read 5, iclass 20, count 2 2006.201.07:31:21.11#ibcon#read 5, iclass 20, count 2 2006.201.07:31:21.11#ibcon#about to read 6, iclass 20, count 2 2006.201.07:31:21.11#ibcon#read 6, iclass 20, count 2 2006.201.07:31:21.11#ibcon#end of sib2, iclass 20, count 2 2006.201.07:31:21.11#ibcon#*mode == 0, iclass 20, count 2 2006.201.07:31:21.11#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.07:31:21.11#ibcon#[25=AT07-05\r\n] 2006.201.07:31:21.11#ibcon#*before write, iclass 20, count 2 2006.201.07:31:21.11#ibcon#enter sib2, iclass 20, count 2 2006.201.07:31:21.11#ibcon#flushed, iclass 20, count 2 2006.201.07:31:21.11#ibcon#about to write, iclass 20, count 2 2006.201.07:31:21.11#ibcon#wrote, iclass 20, count 2 2006.201.07:31:21.11#ibcon#about to read 3, iclass 20, count 2 2006.201.07:31:21.14#ibcon#read 3, iclass 20, count 2 2006.201.07:31:21.14#ibcon#about to read 4, iclass 20, count 2 2006.201.07:31:21.14#ibcon#read 4, iclass 20, count 2 2006.201.07:31:21.14#ibcon#about to read 5, iclass 20, count 2 2006.201.07:31:21.14#ibcon#read 5, iclass 20, count 2 2006.201.07:31:21.14#ibcon#about to read 6, iclass 20, count 2 2006.201.07:31:21.14#ibcon#read 6, iclass 20, count 2 2006.201.07:31:21.14#ibcon#end of sib2, iclass 20, count 2 2006.201.07:31:21.14#ibcon#*after write, iclass 20, count 2 2006.201.07:31:21.14#ibcon#*before return 0, iclass 20, count 2 2006.201.07:31:21.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:21.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:21.14#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.07:31:21.14#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:21.14#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:21.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:21.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:21.26#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:31:21.26#ibcon#first serial, iclass 20, count 0 2006.201.07:31:21.26#ibcon#enter sib2, iclass 20, count 0 2006.201.07:31:21.26#ibcon#flushed, iclass 20, count 0 2006.201.07:31:21.26#ibcon#about to write, iclass 20, count 0 2006.201.07:31:21.26#ibcon#wrote, iclass 20, count 0 2006.201.07:31:21.26#ibcon#about to read 3, iclass 20, count 0 2006.201.07:31:21.28#ibcon#read 3, iclass 20, count 0 2006.201.07:31:21.28#ibcon#about to read 4, iclass 20, count 0 2006.201.07:31:21.28#ibcon#read 4, iclass 20, count 0 2006.201.07:31:21.28#ibcon#about to read 5, iclass 20, count 0 2006.201.07:31:21.28#ibcon#read 5, iclass 20, count 0 2006.201.07:31:21.28#ibcon#about to read 6, iclass 20, count 0 2006.201.07:31:21.28#ibcon#read 6, iclass 20, count 0 2006.201.07:31:21.28#ibcon#end of sib2, iclass 20, count 0 2006.201.07:31:21.28#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:31:21.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:31:21.28#ibcon#[25=USB\r\n] 2006.201.07:31:21.28#ibcon#*before write, iclass 20, count 0 2006.201.07:31:21.28#ibcon#enter sib2, iclass 20, count 0 2006.201.07:31:21.28#ibcon#flushed, iclass 20, count 0 2006.201.07:31:21.28#ibcon#about to write, iclass 20, count 0 2006.201.07:31:21.28#ibcon#wrote, iclass 20, count 0 2006.201.07:31:21.28#ibcon#about to read 3, iclass 20, count 0 2006.201.07:31:21.31#ibcon#read 3, iclass 20, count 0 2006.201.07:31:21.31#ibcon#about to read 4, iclass 20, count 0 2006.201.07:31:21.31#ibcon#read 4, iclass 20, count 0 2006.201.07:31:21.31#ibcon#about to read 5, iclass 20, count 0 2006.201.07:31:21.31#ibcon#read 5, iclass 20, count 0 2006.201.07:31:21.31#ibcon#about to read 6, iclass 20, count 0 2006.201.07:31:21.31#ibcon#read 6, iclass 20, count 0 2006.201.07:31:21.31#ibcon#end of sib2, iclass 20, count 0 2006.201.07:31:21.31#ibcon#*after write, iclass 20, count 0 2006.201.07:31:21.31#ibcon#*before return 0, iclass 20, count 0 2006.201.07:31:21.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:21.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:21.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:31:21.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:31:21.31$vck44/valo=8,884.99 2006.201.07:31:21.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.07:31:21.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.07:31:21.31#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:21.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:21.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:21.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:21.31#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:31:21.31#ibcon#first serial, iclass 22, count 0 2006.201.07:31:21.31#ibcon#enter sib2, iclass 22, count 0 2006.201.07:31:21.31#ibcon#flushed, iclass 22, count 0 2006.201.07:31:21.31#ibcon#about to write, iclass 22, count 0 2006.201.07:31:21.31#ibcon#wrote, iclass 22, count 0 2006.201.07:31:21.31#ibcon#about to read 3, iclass 22, count 0 2006.201.07:31:21.33#ibcon#read 3, iclass 22, count 0 2006.201.07:31:21.33#ibcon#about to read 4, iclass 22, count 0 2006.201.07:31:21.33#ibcon#read 4, iclass 22, count 0 2006.201.07:31:21.33#ibcon#about to read 5, iclass 22, count 0 2006.201.07:31:21.33#ibcon#read 5, iclass 22, count 0 2006.201.07:31:21.33#ibcon#about to read 6, iclass 22, count 0 2006.201.07:31:21.33#ibcon#read 6, iclass 22, count 0 2006.201.07:31:21.33#ibcon#end of sib2, iclass 22, count 0 2006.201.07:31:21.33#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:31:21.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:31:21.33#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:31:21.33#ibcon#*before write, iclass 22, count 0 2006.201.07:31:21.33#ibcon#enter sib2, iclass 22, count 0 2006.201.07:31:21.33#ibcon#flushed, iclass 22, count 0 2006.201.07:31:21.33#ibcon#about to write, iclass 22, count 0 2006.201.07:31:21.33#ibcon#wrote, iclass 22, count 0 2006.201.07:31:21.33#ibcon#about to read 3, iclass 22, count 0 2006.201.07:31:21.37#ibcon#read 3, iclass 22, count 0 2006.201.07:31:21.37#ibcon#about to read 4, iclass 22, count 0 2006.201.07:31:21.37#ibcon#read 4, iclass 22, count 0 2006.201.07:31:21.37#ibcon#about to read 5, iclass 22, count 0 2006.201.07:31:21.37#ibcon#read 5, iclass 22, count 0 2006.201.07:31:21.37#ibcon#about to read 6, iclass 22, count 0 2006.201.07:31:21.37#ibcon#read 6, iclass 22, count 0 2006.201.07:31:21.37#ibcon#end of sib2, iclass 22, count 0 2006.201.07:31:21.37#ibcon#*after write, iclass 22, count 0 2006.201.07:31:21.37#ibcon#*before return 0, iclass 22, count 0 2006.201.07:31:21.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:21.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:21.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:31:21.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:31:21.37$vck44/va=8,4 2006.201.07:31:21.37#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.07:31:21.37#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.07:31:21.37#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:21.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:31:21.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:31:21.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:31:21.43#ibcon#enter wrdev, iclass 24, count 2 2006.201.07:31:21.43#ibcon#first serial, iclass 24, count 2 2006.201.07:31:21.43#ibcon#enter sib2, iclass 24, count 2 2006.201.07:31:21.43#ibcon#flushed, iclass 24, count 2 2006.201.07:31:21.43#ibcon#about to write, iclass 24, count 2 2006.201.07:31:21.43#ibcon#wrote, iclass 24, count 2 2006.201.07:31:21.43#ibcon#about to read 3, iclass 24, count 2 2006.201.07:31:21.45#ibcon#read 3, iclass 24, count 2 2006.201.07:31:21.45#ibcon#about to read 4, iclass 24, count 2 2006.201.07:31:21.45#ibcon#read 4, iclass 24, count 2 2006.201.07:31:21.45#ibcon#about to read 5, iclass 24, count 2 2006.201.07:31:21.45#ibcon#read 5, iclass 24, count 2 2006.201.07:31:21.45#ibcon#about to read 6, iclass 24, count 2 2006.201.07:31:21.45#ibcon#read 6, iclass 24, count 2 2006.201.07:31:21.45#ibcon#end of sib2, iclass 24, count 2 2006.201.07:31:21.45#ibcon#*mode == 0, iclass 24, count 2 2006.201.07:31:21.45#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.07:31:21.45#ibcon#[25=AT08-04\r\n] 2006.201.07:31:21.45#ibcon#*before write, iclass 24, count 2 2006.201.07:31:21.45#ibcon#enter sib2, iclass 24, count 2 2006.201.07:31:21.45#ibcon#flushed, iclass 24, count 2 2006.201.07:31:21.45#ibcon#about to write, iclass 24, count 2 2006.201.07:31:21.45#ibcon#wrote, iclass 24, count 2 2006.201.07:31:21.45#ibcon#about to read 3, iclass 24, count 2 2006.201.07:31:21.48#ibcon#read 3, iclass 24, count 2 2006.201.07:31:21.48#ibcon#about to read 4, iclass 24, count 2 2006.201.07:31:21.48#ibcon#read 4, iclass 24, count 2 2006.201.07:31:21.48#ibcon#about to read 5, iclass 24, count 2 2006.201.07:31:21.48#ibcon#read 5, iclass 24, count 2 2006.201.07:31:21.48#ibcon#about to read 6, iclass 24, count 2 2006.201.07:31:21.48#ibcon#read 6, iclass 24, count 2 2006.201.07:31:21.48#ibcon#end of sib2, iclass 24, count 2 2006.201.07:31:21.48#ibcon#*after write, iclass 24, count 2 2006.201.07:31:21.48#ibcon#*before return 0, iclass 24, count 2 2006.201.07:31:21.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:31:21.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.07:31:21.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.07:31:21.48#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:21.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:31:21.60#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:31:21.60#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:31:21.60#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:31:21.60#ibcon#first serial, iclass 24, count 0 2006.201.07:31:21.60#ibcon#enter sib2, iclass 24, count 0 2006.201.07:31:21.60#ibcon#flushed, iclass 24, count 0 2006.201.07:31:21.60#ibcon#about to write, iclass 24, count 0 2006.201.07:31:21.60#ibcon#wrote, iclass 24, count 0 2006.201.07:31:21.60#ibcon#about to read 3, iclass 24, count 0 2006.201.07:31:21.62#ibcon#read 3, iclass 24, count 0 2006.201.07:31:21.62#ibcon#about to read 4, iclass 24, count 0 2006.201.07:31:21.62#ibcon#read 4, iclass 24, count 0 2006.201.07:31:21.62#ibcon#about to read 5, iclass 24, count 0 2006.201.07:31:21.62#ibcon#read 5, iclass 24, count 0 2006.201.07:31:21.62#ibcon#about to read 6, iclass 24, count 0 2006.201.07:31:21.62#ibcon#read 6, iclass 24, count 0 2006.201.07:31:21.62#ibcon#end of sib2, iclass 24, count 0 2006.201.07:31:21.62#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:31:21.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:31:21.62#ibcon#[25=USB\r\n] 2006.201.07:31:21.62#ibcon#*before write, iclass 24, count 0 2006.201.07:31:21.62#ibcon#enter sib2, iclass 24, count 0 2006.201.07:31:21.62#ibcon#flushed, iclass 24, count 0 2006.201.07:31:21.62#ibcon#about to write, iclass 24, count 0 2006.201.07:31:21.62#ibcon#wrote, iclass 24, count 0 2006.201.07:31:21.62#ibcon#about to read 3, iclass 24, count 0 2006.201.07:31:21.65#ibcon#read 3, iclass 24, count 0 2006.201.07:31:21.65#ibcon#about to read 4, iclass 24, count 0 2006.201.07:31:21.65#ibcon#read 4, iclass 24, count 0 2006.201.07:31:21.65#ibcon#about to read 5, iclass 24, count 0 2006.201.07:31:21.65#ibcon#read 5, iclass 24, count 0 2006.201.07:31:21.65#ibcon#about to read 6, iclass 24, count 0 2006.201.07:31:21.65#ibcon#read 6, iclass 24, count 0 2006.201.07:31:21.65#ibcon#end of sib2, iclass 24, count 0 2006.201.07:31:21.65#ibcon#*after write, iclass 24, count 0 2006.201.07:31:21.65#ibcon#*before return 0, iclass 24, count 0 2006.201.07:31:21.65#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:31:21.65#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.07:31:21.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:31:21.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:31:21.65$vck44/vblo=1,629.99 2006.201.07:31:21.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.07:31:21.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.07:31:21.65#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:21.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:21.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:21.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:21.65#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:31:21.65#ibcon#first serial, iclass 26, count 0 2006.201.07:31:21.65#ibcon#enter sib2, iclass 26, count 0 2006.201.07:31:21.65#ibcon#flushed, iclass 26, count 0 2006.201.07:31:21.65#ibcon#about to write, iclass 26, count 0 2006.201.07:31:21.65#ibcon#wrote, iclass 26, count 0 2006.201.07:31:21.65#ibcon#about to read 3, iclass 26, count 0 2006.201.07:31:21.67#ibcon#read 3, iclass 26, count 0 2006.201.07:31:21.67#ibcon#about to read 4, iclass 26, count 0 2006.201.07:31:21.67#ibcon#read 4, iclass 26, count 0 2006.201.07:31:21.67#ibcon#about to read 5, iclass 26, count 0 2006.201.07:31:21.67#ibcon#read 5, iclass 26, count 0 2006.201.07:31:21.67#ibcon#about to read 6, iclass 26, count 0 2006.201.07:31:21.67#ibcon#read 6, iclass 26, count 0 2006.201.07:31:21.67#ibcon#end of sib2, iclass 26, count 0 2006.201.07:31:21.67#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:31:21.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:31:21.67#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:31:21.67#ibcon#*before write, iclass 26, count 0 2006.201.07:31:21.67#ibcon#enter sib2, iclass 26, count 0 2006.201.07:31:21.67#ibcon#flushed, iclass 26, count 0 2006.201.07:31:21.67#ibcon#about to write, iclass 26, count 0 2006.201.07:31:21.67#ibcon#wrote, iclass 26, count 0 2006.201.07:31:21.67#ibcon#about to read 3, iclass 26, count 0 2006.201.07:31:21.71#ibcon#read 3, iclass 26, count 0 2006.201.07:31:21.71#ibcon#about to read 4, iclass 26, count 0 2006.201.07:31:21.71#ibcon#read 4, iclass 26, count 0 2006.201.07:31:21.71#ibcon#about to read 5, iclass 26, count 0 2006.201.07:31:21.71#ibcon#read 5, iclass 26, count 0 2006.201.07:31:21.71#ibcon#about to read 6, iclass 26, count 0 2006.201.07:31:21.71#ibcon#read 6, iclass 26, count 0 2006.201.07:31:21.71#ibcon#end of sib2, iclass 26, count 0 2006.201.07:31:21.71#ibcon#*after write, iclass 26, count 0 2006.201.07:31:21.71#ibcon#*before return 0, iclass 26, count 0 2006.201.07:31:21.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:21.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.07:31:21.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:31:21.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:31:21.71$vck44/vb=1,4 2006.201.07:31:21.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.07:31:21.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.07:31:21.71#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:21.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:21.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:21.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:21.71#ibcon#enter wrdev, iclass 28, count 2 2006.201.07:31:21.71#ibcon#first serial, iclass 28, count 2 2006.201.07:31:21.71#ibcon#enter sib2, iclass 28, count 2 2006.201.07:31:21.71#ibcon#flushed, iclass 28, count 2 2006.201.07:31:21.71#ibcon#about to write, iclass 28, count 2 2006.201.07:31:21.71#ibcon#wrote, iclass 28, count 2 2006.201.07:31:21.71#ibcon#about to read 3, iclass 28, count 2 2006.201.07:31:21.73#ibcon#read 3, iclass 28, count 2 2006.201.07:31:21.73#ibcon#about to read 4, iclass 28, count 2 2006.201.07:31:21.73#ibcon#read 4, iclass 28, count 2 2006.201.07:31:21.73#ibcon#about to read 5, iclass 28, count 2 2006.201.07:31:21.73#ibcon#read 5, iclass 28, count 2 2006.201.07:31:21.73#ibcon#about to read 6, iclass 28, count 2 2006.201.07:31:21.73#ibcon#read 6, iclass 28, count 2 2006.201.07:31:21.73#ibcon#end of sib2, iclass 28, count 2 2006.201.07:31:21.73#ibcon#*mode == 0, iclass 28, count 2 2006.201.07:31:21.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.07:31:21.73#ibcon#[27=AT01-04\r\n] 2006.201.07:31:21.73#ibcon#*before write, iclass 28, count 2 2006.201.07:31:21.73#ibcon#enter sib2, iclass 28, count 2 2006.201.07:31:21.73#ibcon#flushed, iclass 28, count 2 2006.201.07:31:21.73#ibcon#about to write, iclass 28, count 2 2006.201.07:31:21.73#ibcon#wrote, iclass 28, count 2 2006.201.07:31:21.73#ibcon#about to read 3, iclass 28, count 2 2006.201.07:31:21.76#ibcon#read 3, iclass 28, count 2 2006.201.07:31:21.76#ibcon#about to read 4, iclass 28, count 2 2006.201.07:31:21.76#ibcon#read 4, iclass 28, count 2 2006.201.07:31:21.76#ibcon#about to read 5, iclass 28, count 2 2006.201.07:31:21.76#ibcon#read 5, iclass 28, count 2 2006.201.07:31:21.76#ibcon#about to read 6, iclass 28, count 2 2006.201.07:31:21.76#ibcon#read 6, iclass 28, count 2 2006.201.07:31:21.76#ibcon#end of sib2, iclass 28, count 2 2006.201.07:31:21.76#ibcon#*after write, iclass 28, count 2 2006.201.07:31:21.76#ibcon#*before return 0, iclass 28, count 2 2006.201.07:31:21.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:21.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.07:31:21.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.07:31:21.76#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:21.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:21.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:21.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:21.88#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:31:21.88#ibcon#first serial, iclass 28, count 0 2006.201.07:31:21.88#ibcon#enter sib2, iclass 28, count 0 2006.201.07:31:21.88#ibcon#flushed, iclass 28, count 0 2006.201.07:31:21.88#ibcon#about to write, iclass 28, count 0 2006.201.07:31:21.88#ibcon#wrote, iclass 28, count 0 2006.201.07:31:21.88#ibcon#about to read 3, iclass 28, count 0 2006.201.07:31:21.90#ibcon#read 3, iclass 28, count 0 2006.201.07:31:21.90#ibcon#about to read 4, iclass 28, count 0 2006.201.07:31:21.90#ibcon#read 4, iclass 28, count 0 2006.201.07:31:21.90#ibcon#about to read 5, iclass 28, count 0 2006.201.07:31:21.90#ibcon#read 5, iclass 28, count 0 2006.201.07:31:21.90#ibcon#about to read 6, iclass 28, count 0 2006.201.07:31:21.90#ibcon#read 6, iclass 28, count 0 2006.201.07:31:21.90#ibcon#end of sib2, iclass 28, count 0 2006.201.07:31:21.90#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:31:21.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:31:21.90#ibcon#[27=USB\r\n] 2006.201.07:31:21.90#ibcon#*before write, iclass 28, count 0 2006.201.07:31:21.90#ibcon#enter sib2, iclass 28, count 0 2006.201.07:31:21.90#ibcon#flushed, iclass 28, count 0 2006.201.07:31:21.90#ibcon#about to write, iclass 28, count 0 2006.201.07:31:21.90#ibcon#wrote, iclass 28, count 0 2006.201.07:31:21.90#ibcon#about to read 3, iclass 28, count 0 2006.201.07:31:21.93#ibcon#read 3, iclass 28, count 0 2006.201.07:31:21.93#ibcon#about to read 4, iclass 28, count 0 2006.201.07:31:21.93#ibcon#read 4, iclass 28, count 0 2006.201.07:31:21.93#ibcon#about to read 5, iclass 28, count 0 2006.201.07:31:21.93#ibcon#read 5, iclass 28, count 0 2006.201.07:31:21.93#ibcon#about to read 6, iclass 28, count 0 2006.201.07:31:21.93#ibcon#read 6, iclass 28, count 0 2006.201.07:31:21.93#ibcon#end of sib2, iclass 28, count 0 2006.201.07:31:21.93#ibcon#*after write, iclass 28, count 0 2006.201.07:31:21.93#ibcon#*before return 0, iclass 28, count 0 2006.201.07:31:21.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:21.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.07:31:21.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:31:21.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:31:21.93$vck44/vblo=2,634.99 2006.201.07:31:21.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.07:31:21.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.07:31:21.93#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:21.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:21.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:21.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:21.93#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:31:21.93#ibcon#first serial, iclass 30, count 0 2006.201.07:31:21.93#ibcon#enter sib2, iclass 30, count 0 2006.201.07:31:21.93#ibcon#flushed, iclass 30, count 0 2006.201.07:31:21.93#ibcon#about to write, iclass 30, count 0 2006.201.07:31:21.93#ibcon#wrote, iclass 30, count 0 2006.201.07:31:21.93#ibcon#about to read 3, iclass 30, count 0 2006.201.07:31:21.95#ibcon#read 3, iclass 30, count 0 2006.201.07:31:21.95#ibcon#about to read 4, iclass 30, count 0 2006.201.07:31:21.95#ibcon#read 4, iclass 30, count 0 2006.201.07:31:21.95#ibcon#about to read 5, iclass 30, count 0 2006.201.07:31:21.95#ibcon#read 5, iclass 30, count 0 2006.201.07:31:21.95#ibcon#about to read 6, iclass 30, count 0 2006.201.07:31:21.95#ibcon#read 6, iclass 30, count 0 2006.201.07:31:21.95#ibcon#end of sib2, iclass 30, count 0 2006.201.07:31:21.95#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:31:21.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:31:21.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:31:21.95#ibcon#*before write, iclass 30, count 0 2006.201.07:31:21.95#ibcon#enter sib2, iclass 30, count 0 2006.201.07:31:21.95#ibcon#flushed, iclass 30, count 0 2006.201.07:31:21.95#ibcon#about to write, iclass 30, count 0 2006.201.07:31:21.95#ibcon#wrote, iclass 30, count 0 2006.201.07:31:21.95#ibcon#about to read 3, iclass 30, count 0 2006.201.07:31:21.99#ibcon#read 3, iclass 30, count 0 2006.201.07:31:21.99#ibcon#about to read 4, iclass 30, count 0 2006.201.07:31:21.99#ibcon#read 4, iclass 30, count 0 2006.201.07:31:21.99#ibcon#about to read 5, iclass 30, count 0 2006.201.07:31:21.99#ibcon#read 5, iclass 30, count 0 2006.201.07:31:21.99#ibcon#about to read 6, iclass 30, count 0 2006.201.07:31:21.99#ibcon#read 6, iclass 30, count 0 2006.201.07:31:21.99#ibcon#end of sib2, iclass 30, count 0 2006.201.07:31:21.99#ibcon#*after write, iclass 30, count 0 2006.201.07:31:21.99#ibcon#*before return 0, iclass 30, count 0 2006.201.07:31:21.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:21.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.07:31:21.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:31:21.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:31:21.99$vck44/vb=2,5 2006.201.07:31:21.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.07:31:21.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.07:31:21.99#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:21.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:22.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:22.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:22.05#ibcon#enter wrdev, iclass 32, count 2 2006.201.07:31:22.05#ibcon#first serial, iclass 32, count 2 2006.201.07:31:22.05#ibcon#enter sib2, iclass 32, count 2 2006.201.07:31:22.05#ibcon#flushed, iclass 32, count 2 2006.201.07:31:22.05#ibcon#about to write, iclass 32, count 2 2006.201.07:31:22.05#ibcon#wrote, iclass 32, count 2 2006.201.07:31:22.05#ibcon#about to read 3, iclass 32, count 2 2006.201.07:31:22.07#ibcon#read 3, iclass 32, count 2 2006.201.07:31:22.07#ibcon#about to read 4, iclass 32, count 2 2006.201.07:31:22.07#ibcon#read 4, iclass 32, count 2 2006.201.07:31:22.07#ibcon#about to read 5, iclass 32, count 2 2006.201.07:31:22.07#ibcon#read 5, iclass 32, count 2 2006.201.07:31:22.07#ibcon#about to read 6, iclass 32, count 2 2006.201.07:31:22.07#ibcon#read 6, iclass 32, count 2 2006.201.07:31:22.07#ibcon#end of sib2, iclass 32, count 2 2006.201.07:31:22.07#ibcon#*mode == 0, iclass 32, count 2 2006.201.07:31:22.07#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.07:31:22.07#ibcon#[27=AT02-05\r\n] 2006.201.07:31:22.07#ibcon#*before write, iclass 32, count 2 2006.201.07:31:22.07#ibcon#enter sib2, iclass 32, count 2 2006.201.07:31:22.07#ibcon#flushed, iclass 32, count 2 2006.201.07:31:22.07#ibcon#about to write, iclass 32, count 2 2006.201.07:31:22.07#ibcon#wrote, iclass 32, count 2 2006.201.07:31:22.07#ibcon#about to read 3, iclass 32, count 2 2006.201.07:31:22.10#ibcon#read 3, iclass 32, count 2 2006.201.07:31:22.10#ibcon#about to read 4, iclass 32, count 2 2006.201.07:31:22.10#ibcon#read 4, iclass 32, count 2 2006.201.07:31:22.10#ibcon#about to read 5, iclass 32, count 2 2006.201.07:31:22.10#ibcon#read 5, iclass 32, count 2 2006.201.07:31:22.10#ibcon#about to read 6, iclass 32, count 2 2006.201.07:31:22.10#ibcon#read 6, iclass 32, count 2 2006.201.07:31:22.10#ibcon#end of sib2, iclass 32, count 2 2006.201.07:31:22.10#ibcon#*after write, iclass 32, count 2 2006.201.07:31:22.10#ibcon#*before return 0, iclass 32, count 2 2006.201.07:31:22.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:22.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.07:31:22.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.07:31:22.10#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:22.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:22.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:22.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:22.22#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:31:22.22#ibcon#first serial, iclass 32, count 0 2006.201.07:31:22.22#ibcon#enter sib2, iclass 32, count 0 2006.201.07:31:22.22#ibcon#flushed, iclass 32, count 0 2006.201.07:31:22.22#ibcon#about to write, iclass 32, count 0 2006.201.07:31:22.22#ibcon#wrote, iclass 32, count 0 2006.201.07:31:22.22#ibcon#about to read 3, iclass 32, count 0 2006.201.07:31:22.24#ibcon#read 3, iclass 32, count 0 2006.201.07:31:22.24#ibcon#about to read 4, iclass 32, count 0 2006.201.07:31:22.24#ibcon#read 4, iclass 32, count 0 2006.201.07:31:22.24#ibcon#about to read 5, iclass 32, count 0 2006.201.07:31:22.24#ibcon#read 5, iclass 32, count 0 2006.201.07:31:22.24#ibcon#about to read 6, iclass 32, count 0 2006.201.07:31:22.24#ibcon#read 6, iclass 32, count 0 2006.201.07:31:22.24#ibcon#end of sib2, iclass 32, count 0 2006.201.07:31:22.24#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:31:22.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:31:22.24#ibcon#[27=USB\r\n] 2006.201.07:31:22.24#ibcon#*before write, iclass 32, count 0 2006.201.07:31:22.24#ibcon#enter sib2, iclass 32, count 0 2006.201.07:31:22.24#ibcon#flushed, iclass 32, count 0 2006.201.07:31:22.24#ibcon#about to write, iclass 32, count 0 2006.201.07:31:22.24#ibcon#wrote, iclass 32, count 0 2006.201.07:31:22.24#ibcon#about to read 3, iclass 32, count 0 2006.201.07:31:22.27#ibcon#read 3, iclass 32, count 0 2006.201.07:31:22.27#ibcon#about to read 4, iclass 32, count 0 2006.201.07:31:22.27#ibcon#read 4, iclass 32, count 0 2006.201.07:31:22.27#ibcon#about to read 5, iclass 32, count 0 2006.201.07:31:22.27#ibcon#read 5, iclass 32, count 0 2006.201.07:31:22.27#ibcon#about to read 6, iclass 32, count 0 2006.201.07:31:22.27#ibcon#read 6, iclass 32, count 0 2006.201.07:31:22.27#ibcon#end of sib2, iclass 32, count 0 2006.201.07:31:22.27#ibcon#*after write, iclass 32, count 0 2006.201.07:31:22.27#ibcon#*before return 0, iclass 32, count 0 2006.201.07:31:22.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:22.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.07:31:22.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:31:22.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:31:22.27$vck44/vblo=3,649.99 2006.201.07:31:22.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.07:31:22.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.07:31:22.27#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:22.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:22.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:22.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:22.27#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:31:22.27#ibcon#first serial, iclass 34, count 0 2006.201.07:31:22.27#ibcon#enter sib2, iclass 34, count 0 2006.201.07:31:22.27#ibcon#flushed, iclass 34, count 0 2006.201.07:31:22.27#ibcon#about to write, iclass 34, count 0 2006.201.07:31:22.27#ibcon#wrote, iclass 34, count 0 2006.201.07:31:22.27#ibcon#about to read 3, iclass 34, count 0 2006.201.07:31:22.29#ibcon#read 3, iclass 34, count 0 2006.201.07:31:22.29#ibcon#about to read 4, iclass 34, count 0 2006.201.07:31:22.29#ibcon#read 4, iclass 34, count 0 2006.201.07:31:22.29#ibcon#about to read 5, iclass 34, count 0 2006.201.07:31:22.29#ibcon#read 5, iclass 34, count 0 2006.201.07:31:22.29#ibcon#about to read 6, iclass 34, count 0 2006.201.07:31:22.29#ibcon#read 6, iclass 34, count 0 2006.201.07:31:22.29#ibcon#end of sib2, iclass 34, count 0 2006.201.07:31:22.29#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:31:22.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:31:22.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:31:22.29#ibcon#*before write, iclass 34, count 0 2006.201.07:31:22.29#ibcon#enter sib2, iclass 34, count 0 2006.201.07:31:22.29#ibcon#flushed, iclass 34, count 0 2006.201.07:31:22.29#ibcon#about to write, iclass 34, count 0 2006.201.07:31:22.29#ibcon#wrote, iclass 34, count 0 2006.201.07:31:22.29#ibcon#about to read 3, iclass 34, count 0 2006.201.07:31:22.33#ibcon#read 3, iclass 34, count 0 2006.201.07:31:22.33#ibcon#about to read 4, iclass 34, count 0 2006.201.07:31:22.33#ibcon#read 4, iclass 34, count 0 2006.201.07:31:22.33#ibcon#about to read 5, iclass 34, count 0 2006.201.07:31:22.33#ibcon#read 5, iclass 34, count 0 2006.201.07:31:22.33#ibcon#about to read 6, iclass 34, count 0 2006.201.07:31:22.33#ibcon#read 6, iclass 34, count 0 2006.201.07:31:22.33#ibcon#end of sib2, iclass 34, count 0 2006.201.07:31:22.33#ibcon#*after write, iclass 34, count 0 2006.201.07:31:22.33#ibcon#*before return 0, iclass 34, count 0 2006.201.07:31:22.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:22.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.07:31:22.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:31:22.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:31:22.33$vck44/vb=3,4 2006.201.07:31:22.33#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.07:31:22.33#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.07:31:22.33#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:22.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:22.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:22.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:22.39#ibcon#enter wrdev, iclass 36, count 2 2006.201.07:31:22.39#ibcon#first serial, iclass 36, count 2 2006.201.07:31:22.39#ibcon#enter sib2, iclass 36, count 2 2006.201.07:31:22.39#ibcon#flushed, iclass 36, count 2 2006.201.07:31:22.39#ibcon#about to write, iclass 36, count 2 2006.201.07:31:22.39#ibcon#wrote, iclass 36, count 2 2006.201.07:31:22.39#ibcon#about to read 3, iclass 36, count 2 2006.201.07:31:22.41#ibcon#read 3, iclass 36, count 2 2006.201.07:31:22.41#ibcon#about to read 4, iclass 36, count 2 2006.201.07:31:22.41#ibcon#read 4, iclass 36, count 2 2006.201.07:31:22.41#ibcon#about to read 5, iclass 36, count 2 2006.201.07:31:22.41#ibcon#read 5, iclass 36, count 2 2006.201.07:31:22.41#ibcon#about to read 6, iclass 36, count 2 2006.201.07:31:22.41#ibcon#read 6, iclass 36, count 2 2006.201.07:31:22.41#ibcon#end of sib2, iclass 36, count 2 2006.201.07:31:22.41#ibcon#*mode == 0, iclass 36, count 2 2006.201.07:31:22.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.07:31:22.41#ibcon#[27=AT03-04\r\n] 2006.201.07:31:22.41#ibcon#*before write, iclass 36, count 2 2006.201.07:31:22.41#ibcon#enter sib2, iclass 36, count 2 2006.201.07:31:22.41#ibcon#flushed, iclass 36, count 2 2006.201.07:31:22.41#ibcon#about to write, iclass 36, count 2 2006.201.07:31:22.41#ibcon#wrote, iclass 36, count 2 2006.201.07:31:22.41#ibcon#about to read 3, iclass 36, count 2 2006.201.07:31:22.44#ibcon#read 3, iclass 36, count 2 2006.201.07:31:22.44#ibcon#about to read 4, iclass 36, count 2 2006.201.07:31:22.44#ibcon#read 4, iclass 36, count 2 2006.201.07:31:22.44#ibcon#about to read 5, iclass 36, count 2 2006.201.07:31:22.44#ibcon#read 5, iclass 36, count 2 2006.201.07:31:22.44#ibcon#about to read 6, iclass 36, count 2 2006.201.07:31:22.44#ibcon#read 6, iclass 36, count 2 2006.201.07:31:22.44#ibcon#end of sib2, iclass 36, count 2 2006.201.07:31:22.44#ibcon#*after write, iclass 36, count 2 2006.201.07:31:22.44#ibcon#*before return 0, iclass 36, count 2 2006.201.07:31:22.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:22.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.07:31:22.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.07:31:22.44#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:22.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:22.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:22.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:22.56#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:31:22.56#ibcon#first serial, iclass 36, count 0 2006.201.07:31:22.56#ibcon#enter sib2, iclass 36, count 0 2006.201.07:31:22.56#ibcon#flushed, iclass 36, count 0 2006.201.07:31:22.56#ibcon#about to write, iclass 36, count 0 2006.201.07:31:22.56#ibcon#wrote, iclass 36, count 0 2006.201.07:31:22.56#ibcon#about to read 3, iclass 36, count 0 2006.201.07:31:22.58#ibcon#read 3, iclass 36, count 0 2006.201.07:31:22.58#ibcon#about to read 4, iclass 36, count 0 2006.201.07:31:22.58#ibcon#read 4, iclass 36, count 0 2006.201.07:31:22.58#ibcon#about to read 5, iclass 36, count 0 2006.201.07:31:22.58#ibcon#read 5, iclass 36, count 0 2006.201.07:31:22.58#ibcon#about to read 6, iclass 36, count 0 2006.201.07:31:22.58#ibcon#read 6, iclass 36, count 0 2006.201.07:31:22.58#ibcon#end of sib2, iclass 36, count 0 2006.201.07:31:22.58#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:31:22.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:31:22.58#ibcon#[27=USB\r\n] 2006.201.07:31:22.58#ibcon#*before write, iclass 36, count 0 2006.201.07:31:22.58#ibcon#enter sib2, iclass 36, count 0 2006.201.07:31:22.58#ibcon#flushed, iclass 36, count 0 2006.201.07:31:22.58#ibcon#about to write, iclass 36, count 0 2006.201.07:31:22.58#ibcon#wrote, iclass 36, count 0 2006.201.07:31:22.58#ibcon#about to read 3, iclass 36, count 0 2006.201.07:31:22.61#ibcon#read 3, iclass 36, count 0 2006.201.07:31:22.61#ibcon#about to read 4, iclass 36, count 0 2006.201.07:31:22.61#ibcon#read 4, iclass 36, count 0 2006.201.07:31:22.61#ibcon#about to read 5, iclass 36, count 0 2006.201.07:31:22.61#ibcon#read 5, iclass 36, count 0 2006.201.07:31:22.61#ibcon#about to read 6, iclass 36, count 0 2006.201.07:31:22.61#ibcon#read 6, iclass 36, count 0 2006.201.07:31:22.61#ibcon#end of sib2, iclass 36, count 0 2006.201.07:31:22.61#ibcon#*after write, iclass 36, count 0 2006.201.07:31:22.61#ibcon#*before return 0, iclass 36, count 0 2006.201.07:31:22.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:22.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.07:31:22.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:31:22.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:31:22.61$vck44/vblo=4,679.99 2006.201.07:31:22.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.07:31:22.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.07:31:22.61#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:22.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:22.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:22.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:22.61#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:31:22.61#ibcon#first serial, iclass 38, count 0 2006.201.07:31:22.61#ibcon#enter sib2, iclass 38, count 0 2006.201.07:31:22.61#ibcon#flushed, iclass 38, count 0 2006.201.07:31:22.61#ibcon#about to write, iclass 38, count 0 2006.201.07:31:22.61#ibcon#wrote, iclass 38, count 0 2006.201.07:31:22.61#ibcon#about to read 3, iclass 38, count 0 2006.201.07:31:22.63#ibcon#read 3, iclass 38, count 0 2006.201.07:31:22.63#ibcon#about to read 4, iclass 38, count 0 2006.201.07:31:22.63#ibcon#read 4, iclass 38, count 0 2006.201.07:31:22.63#ibcon#about to read 5, iclass 38, count 0 2006.201.07:31:22.63#ibcon#read 5, iclass 38, count 0 2006.201.07:31:22.63#ibcon#about to read 6, iclass 38, count 0 2006.201.07:31:22.63#ibcon#read 6, iclass 38, count 0 2006.201.07:31:22.63#ibcon#end of sib2, iclass 38, count 0 2006.201.07:31:22.63#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:31:22.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:31:22.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:31:22.63#ibcon#*before write, iclass 38, count 0 2006.201.07:31:22.63#ibcon#enter sib2, iclass 38, count 0 2006.201.07:31:22.63#ibcon#flushed, iclass 38, count 0 2006.201.07:31:22.63#ibcon#about to write, iclass 38, count 0 2006.201.07:31:22.63#ibcon#wrote, iclass 38, count 0 2006.201.07:31:22.63#ibcon#about to read 3, iclass 38, count 0 2006.201.07:31:22.67#ibcon#read 3, iclass 38, count 0 2006.201.07:31:22.67#ibcon#about to read 4, iclass 38, count 0 2006.201.07:31:22.67#ibcon#read 4, iclass 38, count 0 2006.201.07:31:22.67#ibcon#about to read 5, iclass 38, count 0 2006.201.07:31:22.67#ibcon#read 5, iclass 38, count 0 2006.201.07:31:22.67#ibcon#about to read 6, iclass 38, count 0 2006.201.07:31:22.67#ibcon#read 6, iclass 38, count 0 2006.201.07:31:22.67#ibcon#end of sib2, iclass 38, count 0 2006.201.07:31:22.67#ibcon#*after write, iclass 38, count 0 2006.201.07:31:22.67#ibcon#*before return 0, iclass 38, count 0 2006.201.07:31:22.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:22.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.07:31:22.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:31:22.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:31:22.67$vck44/vb=4,5 2006.201.07:31:22.67#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.07:31:22.67#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.07:31:22.67#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:22.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:22.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:22.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:22.73#ibcon#enter wrdev, iclass 40, count 2 2006.201.07:31:22.73#ibcon#first serial, iclass 40, count 2 2006.201.07:31:22.73#ibcon#enter sib2, iclass 40, count 2 2006.201.07:31:22.73#ibcon#flushed, iclass 40, count 2 2006.201.07:31:22.73#ibcon#about to write, iclass 40, count 2 2006.201.07:31:22.73#ibcon#wrote, iclass 40, count 2 2006.201.07:31:22.73#ibcon#about to read 3, iclass 40, count 2 2006.201.07:31:22.75#ibcon#read 3, iclass 40, count 2 2006.201.07:31:22.75#ibcon#about to read 4, iclass 40, count 2 2006.201.07:31:22.75#ibcon#read 4, iclass 40, count 2 2006.201.07:31:22.75#ibcon#about to read 5, iclass 40, count 2 2006.201.07:31:22.75#ibcon#read 5, iclass 40, count 2 2006.201.07:31:22.75#ibcon#about to read 6, iclass 40, count 2 2006.201.07:31:22.75#ibcon#read 6, iclass 40, count 2 2006.201.07:31:22.75#ibcon#end of sib2, iclass 40, count 2 2006.201.07:31:22.75#ibcon#*mode == 0, iclass 40, count 2 2006.201.07:31:22.75#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.07:31:22.75#ibcon#[27=AT04-05\r\n] 2006.201.07:31:22.75#ibcon#*before write, iclass 40, count 2 2006.201.07:31:22.75#ibcon#enter sib2, iclass 40, count 2 2006.201.07:31:22.75#ibcon#flushed, iclass 40, count 2 2006.201.07:31:22.75#ibcon#about to write, iclass 40, count 2 2006.201.07:31:22.75#ibcon#wrote, iclass 40, count 2 2006.201.07:31:22.75#ibcon#about to read 3, iclass 40, count 2 2006.201.07:31:22.78#ibcon#read 3, iclass 40, count 2 2006.201.07:31:22.78#ibcon#about to read 4, iclass 40, count 2 2006.201.07:31:22.78#ibcon#read 4, iclass 40, count 2 2006.201.07:31:22.78#ibcon#about to read 5, iclass 40, count 2 2006.201.07:31:22.78#ibcon#read 5, iclass 40, count 2 2006.201.07:31:22.78#ibcon#about to read 6, iclass 40, count 2 2006.201.07:31:22.78#ibcon#read 6, iclass 40, count 2 2006.201.07:31:22.78#ibcon#end of sib2, iclass 40, count 2 2006.201.07:31:22.78#ibcon#*after write, iclass 40, count 2 2006.201.07:31:22.78#ibcon#*before return 0, iclass 40, count 2 2006.201.07:31:22.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:22.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.07:31:22.78#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.07:31:22.78#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:22.78#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:22.90#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:22.90#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:22.90#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:31:22.90#ibcon#first serial, iclass 40, count 0 2006.201.07:31:22.90#ibcon#enter sib2, iclass 40, count 0 2006.201.07:31:22.90#ibcon#flushed, iclass 40, count 0 2006.201.07:31:22.90#ibcon#about to write, iclass 40, count 0 2006.201.07:31:22.90#ibcon#wrote, iclass 40, count 0 2006.201.07:31:22.90#ibcon#about to read 3, iclass 40, count 0 2006.201.07:31:22.92#ibcon#read 3, iclass 40, count 0 2006.201.07:31:22.92#ibcon#about to read 4, iclass 40, count 0 2006.201.07:31:22.92#ibcon#read 4, iclass 40, count 0 2006.201.07:31:22.92#ibcon#about to read 5, iclass 40, count 0 2006.201.07:31:22.92#ibcon#read 5, iclass 40, count 0 2006.201.07:31:22.92#ibcon#about to read 6, iclass 40, count 0 2006.201.07:31:22.92#ibcon#read 6, iclass 40, count 0 2006.201.07:31:22.92#ibcon#end of sib2, iclass 40, count 0 2006.201.07:31:22.92#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:31:22.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:31:22.92#ibcon#[27=USB\r\n] 2006.201.07:31:22.92#ibcon#*before write, iclass 40, count 0 2006.201.07:31:22.92#ibcon#enter sib2, iclass 40, count 0 2006.201.07:31:22.92#ibcon#flushed, iclass 40, count 0 2006.201.07:31:22.92#ibcon#about to write, iclass 40, count 0 2006.201.07:31:22.92#ibcon#wrote, iclass 40, count 0 2006.201.07:31:22.92#ibcon#about to read 3, iclass 40, count 0 2006.201.07:31:22.95#ibcon#read 3, iclass 40, count 0 2006.201.07:31:22.95#ibcon#about to read 4, iclass 40, count 0 2006.201.07:31:22.95#ibcon#read 4, iclass 40, count 0 2006.201.07:31:22.95#ibcon#about to read 5, iclass 40, count 0 2006.201.07:31:22.95#ibcon#read 5, iclass 40, count 0 2006.201.07:31:22.95#ibcon#about to read 6, iclass 40, count 0 2006.201.07:31:22.95#ibcon#read 6, iclass 40, count 0 2006.201.07:31:22.95#ibcon#end of sib2, iclass 40, count 0 2006.201.07:31:22.95#ibcon#*after write, iclass 40, count 0 2006.201.07:31:22.95#ibcon#*before return 0, iclass 40, count 0 2006.201.07:31:22.95#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:22.95#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.07:31:22.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:31:22.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:31:22.95$vck44/vblo=5,709.99 2006.201.07:31:22.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.07:31:22.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.07:31:22.95#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:22.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:22.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:22.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:22.95#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:31:22.95#ibcon#first serial, iclass 4, count 0 2006.201.07:31:22.95#ibcon#enter sib2, iclass 4, count 0 2006.201.07:31:22.95#ibcon#flushed, iclass 4, count 0 2006.201.07:31:22.95#ibcon#about to write, iclass 4, count 0 2006.201.07:31:22.95#ibcon#wrote, iclass 4, count 0 2006.201.07:31:22.95#ibcon#about to read 3, iclass 4, count 0 2006.201.07:31:22.97#ibcon#read 3, iclass 4, count 0 2006.201.07:31:22.97#ibcon#about to read 4, iclass 4, count 0 2006.201.07:31:22.97#ibcon#read 4, iclass 4, count 0 2006.201.07:31:22.97#ibcon#about to read 5, iclass 4, count 0 2006.201.07:31:22.97#ibcon#read 5, iclass 4, count 0 2006.201.07:31:22.97#ibcon#about to read 6, iclass 4, count 0 2006.201.07:31:22.97#ibcon#read 6, iclass 4, count 0 2006.201.07:31:22.97#ibcon#end of sib2, iclass 4, count 0 2006.201.07:31:22.97#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:31:22.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:31:22.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:31:22.97#ibcon#*before write, iclass 4, count 0 2006.201.07:31:22.97#ibcon#enter sib2, iclass 4, count 0 2006.201.07:31:22.97#ibcon#flushed, iclass 4, count 0 2006.201.07:31:22.97#ibcon#about to write, iclass 4, count 0 2006.201.07:31:22.97#ibcon#wrote, iclass 4, count 0 2006.201.07:31:22.97#ibcon#about to read 3, iclass 4, count 0 2006.201.07:31:23.01#ibcon#read 3, iclass 4, count 0 2006.201.07:31:23.01#ibcon#about to read 4, iclass 4, count 0 2006.201.07:31:23.01#ibcon#read 4, iclass 4, count 0 2006.201.07:31:23.01#ibcon#about to read 5, iclass 4, count 0 2006.201.07:31:23.01#ibcon#read 5, iclass 4, count 0 2006.201.07:31:23.01#ibcon#about to read 6, iclass 4, count 0 2006.201.07:31:23.01#ibcon#read 6, iclass 4, count 0 2006.201.07:31:23.01#ibcon#end of sib2, iclass 4, count 0 2006.201.07:31:23.01#ibcon#*after write, iclass 4, count 0 2006.201.07:31:23.01#ibcon#*before return 0, iclass 4, count 0 2006.201.07:31:23.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:23.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.07:31:23.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:31:23.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:31:23.01$vck44/vb=5,4 2006.201.07:31:23.01#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.07:31:23.01#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.07:31:23.01#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:23.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:31:23.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:31:23.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:31:23.07#ibcon#enter wrdev, iclass 6, count 2 2006.201.07:31:23.07#ibcon#first serial, iclass 6, count 2 2006.201.07:31:23.07#ibcon#enter sib2, iclass 6, count 2 2006.201.07:31:23.07#ibcon#flushed, iclass 6, count 2 2006.201.07:31:23.07#ibcon#about to write, iclass 6, count 2 2006.201.07:31:23.07#ibcon#wrote, iclass 6, count 2 2006.201.07:31:23.07#ibcon#about to read 3, iclass 6, count 2 2006.201.07:31:23.09#ibcon#read 3, iclass 6, count 2 2006.201.07:31:23.09#ibcon#about to read 4, iclass 6, count 2 2006.201.07:31:23.09#ibcon#read 4, iclass 6, count 2 2006.201.07:31:23.09#ibcon#about to read 5, iclass 6, count 2 2006.201.07:31:23.09#ibcon#read 5, iclass 6, count 2 2006.201.07:31:23.09#ibcon#about to read 6, iclass 6, count 2 2006.201.07:31:23.09#ibcon#read 6, iclass 6, count 2 2006.201.07:31:23.09#ibcon#end of sib2, iclass 6, count 2 2006.201.07:31:23.09#ibcon#*mode == 0, iclass 6, count 2 2006.201.07:31:23.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.07:31:23.09#ibcon#[27=AT05-04\r\n] 2006.201.07:31:23.09#ibcon#*before write, iclass 6, count 2 2006.201.07:31:23.09#ibcon#enter sib2, iclass 6, count 2 2006.201.07:31:23.09#ibcon#flushed, iclass 6, count 2 2006.201.07:31:23.09#ibcon#about to write, iclass 6, count 2 2006.201.07:31:23.09#ibcon#wrote, iclass 6, count 2 2006.201.07:31:23.09#ibcon#about to read 3, iclass 6, count 2 2006.201.07:31:23.12#ibcon#read 3, iclass 6, count 2 2006.201.07:31:23.12#ibcon#about to read 4, iclass 6, count 2 2006.201.07:31:23.12#ibcon#read 4, iclass 6, count 2 2006.201.07:31:23.12#ibcon#about to read 5, iclass 6, count 2 2006.201.07:31:23.12#ibcon#read 5, iclass 6, count 2 2006.201.07:31:23.12#ibcon#about to read 6, iclass 6, count 2 2006.201.07:31:23.12#ibcon#read 6, iclass 6, count 2 2006.201.07:31:23.12#ibcon#end of sib2, iclass 6, count 2 2006.201.07:31:23.12#ibcon#*after write, iclass 6, count 2 2006.201.07:31:23.12#ibcon#*before return 0, iclass 6, count 2 2006.201.07:31:23.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:31:23.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.07:31:23.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.07:31:23.12#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:23.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:31:23.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:31:23.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:31:23.24#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:31:23.24#ibcon#first serial, iclass 6, count 0 2006.201.07:31:23.24#ibcon#enter sib2, iclass 6, count 0 2006.201.07:31:23.24#ibcon#flushed, iclass 6, count 0 2006.201.07:31:23.24#ibcon#about to write, iclass 6, count 0 2006.201.07:31:23.24#ibcon#wrote, iclass 6, count 0 2006.201.07:31:23.24#ibcon#about to read 3, iclass 6, count 0 2006.201.07:31:23.26#ibcon#read 3, iclass 6, count 0 2006.201.07:31:23.26#ibcon#about to read 4, iclass 6, count 0 2006.201.07:31:23.26#ibcon#read 4, iclass 6, count 0 2006.201.07:31:23.26#ibcon#about to read 5, iclass 6, count 0 2006.201.07:31:23.26#ibcon#read 5, iclass 6, count 0 2006.201.07:31:23.26#ibcon#about to read 6, iclass 6, count 0 2006.201.07:31:23.26#ibcon#read 6, iclass 6, count 0 2006.201.07:31:23.26#ibcon#end of sib2, iclass 6, count 0 2006.201.07:31:23.26#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:31:23.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:31:23.26#ibcon#[27=USB\r\n] 2006.201.07:31:23.26#ibcon#*before write, iclass 6, count 0 2006.201.07:31:23.26#ibcon#enter sib2, iclass 6, count 0 2006.201.07:31:23.26#ibcon#flushed, iclass 6, count 0 2006.201.07:31:23.26#ibcon#about to write, iclass 6, count 0 2006.201.07:31:23.26#ibcon#wrote, iclass 6, count 0 2006.201.07:31:23.26#ibcon#about to read 3, iclass 6, count 0 2006.201.07:31:23.29#ibcon#read 3, iclass 6, count 0 2006.201.07:31:23.29#ibcon#about to read 4, iclass 6, count 0 2006.201.07:31:23.29#ibcon#read 4, iclass 6, count 0 2006.201.07:31:23.29#ibcon#about to read 5, iclass 6, count 0 2006.201.07:31:23.29#ibcon#read 5, iclass 6, count 0 2006.201.07:31:23.29#ibcon#about to read 6, iclass 6, count 0 2006.201.07:31:23.29#ibcon#read 6, iclass 6, count 0 2006.201.07:31:23.29#ibcon#end of sib2, iclass 6, count 0 2006.201.07:31:23.29#ibcon#*after write, iclass 6, count 0 2006.201.07:31:23.29#ibcon#*before return 0, iclass 6, count 0 2006.201.07:31:23.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:31:23.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.07:31:23.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:31:23.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:31:23.29$vck44/vblo=6,719.99 2006.201.07:31:23.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.07:31:23.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.07:31:23.29#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:23.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:31:23.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:31:23.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:31:23.29#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:31:23.29#ibcon#first serial, iclass 10, count 0 2006.201.07:31:23.29#ibcon#enter sib2, iclass 10, count 0 2006.201.07:31:23.29#ibcon#flushed, iclass 10, count 0 2006.201.07:31:23.29#ibcon#about to write, iclass 10, count 0 2006.201.07:31:23.29#ibcon#wrote, iclass 10, count 0 2006.201.07:31:23.29#ibcon#about to read 3, iclass 10, count 0 2006.201.07:31:23.31#ibcon#read 3, iclass 10, count 0 2006.201.07:31:23.31#ibcon#about to read 4, iclass 10, count 0 2006.201.07:31:23.31#ibcon#read 4, iclass 10, count 0 2006.201.07:31:23.31#ibcon#about to read 5, iclass 10, count 0 2006.201.07:31:23.31#ibcon#read 5, iclass 10, count 0 2006.201.07:31:23.31#ibcon#about to read 6, iclass 10, count 0 2006.201.07:31:23.31#ibcon#read 6, iclass 10, count 0 2006.201.07:31:23.31#ibcon#end of sib2, iclass 10, count 0 2006.201.07:31:23.31#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:31:23.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:31:23.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:31:23.31#ibcon#*before write, iclass 10, count 0 2006.201.07:31:23.31#ibcon#enter sib2, iclass 10, count 0 2006.201.07:31:23.31#ibcon#flushed, iclass 10, count 0 2006.201.07:31:23.31#ibcon#about to write, iclass 10, count 0 2006.201.07:31:23.31#ibcon#wrote, iclass 10, count 0 2006.201.07:31:23.31#ibcon#about to read 3, iclass 10, count 0 2006.201.07:31:23.35#ibcon#read 3, iclass 10, count 0 2006.201.07:31:23.35#ibcon#about to read 4, iclass 10, count 0 2006.201.07:31:23.35#ibcon#read 4, iclass 10, count 0 2006.201.07:31:23.35#ibcon#about to read 5, iclass 10, count 0 2006.201.07:31:23.35#ibcon#read 5, iclass 10, count 0 2006.201.07:31:23.35#ibcon#about to read 6, iclass 10, count 0 2006.201.07:31:23.35#ibcon#read 6, iclass 10, count 0 2006.201.07:31:23.35#ibcon#end of sib2, iclass 10, count 0 2006.201.07:31:23.35#ibcon#*after write, iclass 10, count 0 2006.201.07:31:23.35#ibcon#*before return 0, iclass 10, count 0 2006.201.07:31:23.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:31:23.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.07:31:23.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:31:23.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:31:23.35$vck44/vb=6,4 2006.201.07:31:23.35#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.07:31:23.35#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.07:31:23.35#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:23.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:31:23.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:31:23.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:31:23.41#ibcon#enter wrdev, iclass 12, count 2 2006.201.07:31:23.41#ibcon#first serial, iclass 12, count 2 2006.201.07:31:23.41#ibcon#enter sib2, iclass 12, count 2 2006.201.07:31:23.41#ibcon#flushed, iclass 12, count 2 2006.201.07:31:23.41#ibcon#about to write, iclass 12, count 2 2006.201.07:31:23.41#ibcon#wrote, iclass 12, count 2 2006.201.07:31:23.41#ibcon#about to read 3, iclass 12, count 2 2006.201.07:31:23.43#ibcon#read 3, iclass 12, count 2 2006.201.07:31:23.43#ibcon#about to read 4, iclass 12, count 2 2006.201.07:31:23.43#ibcon#read 4, iclass 12, count 2 2006.201.07:31:23.43#ibcon#about to read 5, iclass 12, count 2 2006.201.07:31:23.43#ibcon#read 5, iclass 12, count 2 2006.201.07:31:23.43#ibcon#about to read 6, iclass 12, count 2 2006.201.07:31:23.43#ibcon#read 6, iclass 12, count 2 2006.201.07:31:23.43#ibcon#end of sib2, iclass 12, count 2 2006.201.07:31:23.43#ibcon#*mode == 0, iclass 12, count 2 2006.201.07:31:23.43#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.07:31:23.43#ibcon#[27=AT06-04\r\n] 2006.201.07:31:23.43#ibcon#*before write, iclass 12, count 2 2006.201.07:31:23.43#ibcon#enter sib2, iclass 12, count 2 2006.201.07:31:23.43#ibcon#flushed, iclass 12, count 2 2006.201.07:31:23.43#ibcon#about to write, iclass 12, count 2 2006.201.07:31:23.43#ibcon#wrote, iclass 12, count 2 2006.201.07:31:23.43#ibcon#about to read 3, iclass 12, count 2 2006.201.07:31:23.46#ibcon#read 3, iclass 12, count 2 2006.201.07:31:23.46#ibcon#about to read 4, iclass 12, count 2 2006.201.07:31:23.46#ibcon#read 4, iclass 12, count 2 2006.201.07:31:23.46#ibcon#about to read 5, iclass 12, count 2 2006.201.07:31:23.46#ibcon#read 5, iclass 12, count 2 2006.201.07:31:23.46#ibcon#about to read 6, iclass 12, count 2 2006.201.07:31:23.46#ibcon#read 6, iclass 12, count 2 2006.201.07:31:23.46#ibcon#end of sib2, iclass 12, count 2 2006.201.07:31:23.46#ibcon#*after write, iclass 12, count 2 2006.201.07:31:23.46#ibcon#*before return 0, iclass 12, count 2 2006.201.07:31:23.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:31:23.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.07:31:23.46#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.07:31:23.46#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:23.46#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:31:23.58#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:31:23.58#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:31:23.58#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:31:23.58#ibcon#first serial, iclass 12, count 0 2006.201.07:31:23.58#ibcon#enter sib2, iclass 12, count 0 2006.201.07:31:23.58#ibcon#flushed, iclass 12, count 0 2006.201.07:31:23.58#ibcon#about to write, iclass 12, count 0 2006.201.07:31:23.58#ibcon#wrote, iclass 12, count 0 2006.201.07:31:23.58#ibcon#about to read 3, iclass 12, count 0 2006.201.07:31:23.60#ibcon#read 3, iclass 12, count 0 2006.201.07:31:23.60#ibcon#about to read 4, iclass 12, count 0 2006.201.07:31:23.60#ibcon#read 4, iclass 12, count 0 2006.201.07:31:23.60#ibcon#about to read 5, iclass 12, count 0 2006.201.07:31:23.60#ibcon#read 5, iclass 12, count 0 2006.201.07:31:23.60#ibcon#about to read 6, iclass 12, count 0 2006.201.07:31:23.60#ibcon#read 6, iclass 12, count 0 2006.201.07:31:23.60#ibcon#end of sib2, iclass 12, count 0 2006.201.07:31:23.60#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:31:23.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:31:23.60#ibcon#[27=USB\r\n] 2006.201.07:31:23.60#ibcon#*before write, iclass 12, count 0 2006.201.07:31:23.60#ibcon#enter sib2, iclass 12, count 0 2006.201.07:31:23.60#ibcon#flushed, iclass 12, count 0 2006.201.07:31:23.60#ibcon#about to write, iclass 12, count 0 2006.201.07:31:23.60#ibcon#wrote, iclass 12, count 0 2006.201.07:31:23.60#ibcon#about to read 3, iclass 12, count 0 2006.201.07:31:23.63#ibcon#read 3, iclass 12, count 0 2006.201.07:31:23.63#ibcon#about to read 4, iclass 12, count 0 2006.201.07:31:23.63#ibcon#read 4, iclass 12, count 0 2006.201.07:31:23.63#ibcon#about to read 5, iclass 12, count 0 2006.201.07:31:23.63#ibcon#read 5, iclass 12, count 0 2006.201.07:31:23.63#ibcon#about to read 6, iclass 12, count 0 2006.201.07:31:23.63#ibcon#read 6, iclass 12, count 0 2006.201.07:31:23.63#ibcon#end of sib2, iclass 12, count 0 2006.201.07:31:23.63#ibcon#*after write, iclass 12, count 0 2006.201.07:31:23.63#ibcon#*before return 0, iclass 12, count 0 2006.201.07:31:23.63#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:31:23.63#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.07:31:23.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:31:23.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:31:23.63$vck44/vblo=7,734.99 2006.201.07:31:23.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.07:31:23.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.07:31:23.63#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:23.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:23.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:23.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:23.63#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:31:23.63#ibcon#first serial, iclass 14, count 0 2006.201.07:31:23.63#ibcon#enter sib2, iclass 14, count 0 2006.201.07:31:23.63#ibcon#flushed, iclass 14, count 0 2006.201.07:31:23.63#ibcon#about to write, iclass 14, count 0 2006.201.07:31:23.63#ibcon#wrote, iclass 14, count 0 2006.201.07:31:23.63#ibcon#about to read 3, iclass 14, count 0 2006.201.07:31:23.65#ibcon#read 3, iclass 14, count 0 2006.201.07:31:23.65#ibcon#about to read 4, iclass 14, count 0 2006.201.07:31:23.65#ibcon#read 4, iclass 14, count 0 2006.201.07:31:23.65#ibcon#about to read 5, iclass 14, count 0 2006.201.07:31:23.65#ibcon#read 5, iclass 14, count 0 2006.201.07:31:23.65#ibcon#about to read 6, iclass 14, count 0 2006.201.07:31:23.65#ibcon#read 6, iclass 14, count 0 2006.201.07:31:23.65#ibcon#end of sib2, iclass 14, count 0 2006.201.07:31:23.65#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:31:23.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:31:23.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:31:23.65#ibcon#*before write, iclass 14, count 0 2006.201.07:31:23.65#ibcon#enter sib2, iclass 14, count 0 2006.201.07:31:23.65#ibcon#flushed, iclass 14, count 0 2006.201.07:31:23.65#ibcon#about to write, iclass 14, count 0 2006.201.07:31:23.65#ibcon#wrote, iclass 14, count 0 2006.201.07:31:23.65#ibcon#about to read 3, iclass 14, count 0 2006.201.07:31:23.69#ibcon#read 3, iclass 14, count 0 2006.201.07:31:23.69#ibcon#about to read 4, iclass 14, count 0 2006.201.07:31:23.69#ibcon#read 4, iclass 14, count 0 2006.201.07:31:23.69#ibcon#about to read 5, iclass 14, count 0 2006.201.07:31:23.69#ibcon#read 5, iclass 14, count 0 2006.201.07:31:23.69#ibcon#about to read 6, iclass 14, count 0 2006.201.07:31:23.69#ibcon#read 6, iclass 14, count 0 2006.201.07:31:23.69#ibcon#end of sib2, iclass 14, count 0 2006.201.07:31:23.69#ibcon#*after write, iclass 14, count 0 2006.201.07:31:23.69#ibcon#*before return 0, iclass 14, count 0 2006.201.07:31:23.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:23.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:31:23.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:31:23.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:31:23.69$vck44/vb=7,4 2006.201.07:31:23.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.07:31:23.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.07:31:23.69#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:23.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:23.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:23.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:23.75#ibcon#enter wrdev, iclass 16, count 2 2006.201.07:31:23.75#ibcon#first serial, iclass 16, count 2 2006.201.07:31:23.75#ibcon#enter sib2, iclass 16, count 2 2006.201.07:31:23.75#ibcon#flushed, iclass 16, count 2 2006.201.07:31:23.75#ibcon#about to write, iclass 16, count 2 2006.201.07:31:23.75#ibcon#wrote, iclass 16, count 2 2006.201.07:31:23.75#ibcon#about to read 3, iclass 16, count 2 2006.201.07:31:23.77#ibcon#read 3, iclass 16, count 2 2006.201.07:31:23.77#ibcon#about to read 4, iclass 16, count 2 2006.201.07:31:23.77#ibcon#read 4, iclass 16, count 2 2006.201.07:31:23.77#ibcon#about to read 5, iclass 16, count 2 2006.201.07:31:23.77#ibcon#read 5, iclass 16, count 2 2006.201.07:31:23.77#ibcon#about to read 6, iclass 16, count 2 2006.201.07:31:23.77#ibcon#read 6, iclass 16, count 2 2006.201.07:31:23.77#ibcon#end of sib2, iclass 16, count 2 2006.201.07:31:23.77#ibcon#*mode == 0, iclass 16, count 2 2006.201.07:31:23.77#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.07:31:23.77#ibcon#[27=AT07-04\r\n] 2006.201.07:31:23.77#ibcon#*before write, iclass 16, count 2 2006.201.07:31:23.77#ibcon#enter sib2, iclass 16, count 2 2006.201.07:31:23.77#ibcon#flushed, iclass 16, count 2 2006.201.07:31:23.77#ibcon#about to write, iclass 16, count 2 2006.201.07:31:23.77#ibcon#wrote, iclass 16, count 2 2006.201.07:31:23.77#ibcon#about to read 3, iclass 16, count 2 2006.201.07:31:23.80#ibcon#read 3, iclass 16, count 2 2006.201.07:31:23.80#ibcon#about to read 4, iclass 16, count 2 2006.201.07:31:23.80#ibcon#read 4, iclass 16, count 2 2006.201.07:31:23.80#ibcon#about to read 5, iclass 16, count 2 2006.201.07:31:23.80#ibcon#read 5, iclass 16, count 2 2006.201.07:31:23.80#ibcon#about to read 6, iclass 16, count 2 2006.201.07:31:23.80#ibcon#read 6, iclass 16, count 2 2006.201.07:31:23.80#ibcon#end of sib2, iclass 16, count 2 2006.201.07:31:23.80#ibcon#*after write, iclass 16, count 2 2006.201.07:31:23.80#ibcon#*before return 0, iclass 16, count 2 2006.201.07:31:23.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:23.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.07:31:23.80#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.07:31:23.80#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:23.80#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:23.92#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:23.92#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:23.92#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:31:23.92#ibcon#first serial, iclass 16, count 0 2006.201.07:31:23.92#ibcon#enter sib2, iclass 16, count 0 2006.201.07:31:23.92#ibcon#flushed, iclass 16, count 0 2006.201.07:31:23.92#ibcon#about to write, iclass 16, count 0 2006.201.07:31:23.92#ibcon#wrote, iclass 16, count 0 2006.201.07:31:23.92#ibcon#about to read 3, iclass 16, count 0 2006.201.07:31:23.94#ibcon#read 3, iclass 16, count 0 2006.201.07:31:23.94#ibcon#about to read 4, iclass 16, count 0 2006.201.07:31:23.94#ibcon#read 4, iclass 16, count 0 2006.201.07:31:23.94#ibcon#about to read 5, iclass 16, count 0 2006.201.07:31:23.94#ibcon#read 5, iclass 16, count 0 2006.201.07:31:23.94#ibcon#about to read 6, iclass 16, count 0 2006.201.07:31:23.94#ibcon#read 6, iclass 16, count 0 2006.201.07:31:23.94#ibcon#end of sib2, iclass 16, count 0 2006.201.07:31:23.94#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:31:23.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:31:23.94#ibcon#[27=USB\r\n] 2006.201.07:31:23.94#ibcon#*before write, iclass 16, count 0 2006.201.07:31:23.94#ibcon#enter sib2, iclass 16, count 0 2006.201.07:31:23.94#ibcon#flushed, iclass 16, count 0 2006.201.07:31:23.94#ibcon#about to write, iclass 16, count 0 2006.201.07:31:23.94#ibcon#wrote, iclass 16, count 0 2006.201.07:31:23.94#ibcon#about to read 3, iclass 16, count 0 2006.201.07:31:23.97#ibcon#read 3, iclass 16, count 0 2006.201.07:31:23.97#ibcon#about to read 4, iclass 16, count 0 2006.201.07:31:23.97#ibcon#read 4, iclass 16, count 0 2006.201.07:31:23.97#ibcon#about to read 5, iclass 16, count 0 2006.201.07:31:23.97#ibcon#read 5, iclass 16, count 0 2006.201.07:31:23.97#ibcon#about to read 6, iclass 16, count 0 2006.201.07:31:23.97#ibcon#read 6, iclass 16, count 0 2006.201.07:31:23.97#ibcon#end of sib2, iclass 16, count 0 2006.201.07:31:23.97#ibcon#*after write, iclass 16, count 0 2006.201.07:31:23.97#ibcon#*before return 0, iclass 16, count 0 2006.201.07:31:23.97#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:23.97#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.07:31:23.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:31:23.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:31:23.97$vck44/vblo=8,744.99 2006.201.07:31:23.97#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.07:31:23.97#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.07:31:23.97#ibcon#ireg 17 cls_cnt 0 2006.201.07:31:23.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:23.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:23.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:23.97#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:31:23.97#ibcon#first serial, iclass 18, count 0 2006.201.07:31:23.97#ibcon#enter sib2, iclass 18, count 0 2006.201.07:31:23.97#ibcon#flushed, iclass 18, count 0 2006.201.07:31:23.97#ibcon#about to write, iclass 18, count 0 2006.201.07:31:23.97#ibcon#wrote, iclass 18, count 0 2006.201.07:31:23.97#ibcon#about to read 3, iclass 18, count 0 2006.201.07:31:23.99#ibcon#read 3, iclass 18, count 0 2006.201.07:31:23.99#ibcon#about to read 4, iclass 18, count 0 2006.201.07:31:23.99#ibcon#read 4, iclass 18, count 0 2006.201.07:31:23.99#ibcon#about to read 5, iclass 18, count 0 2006.201.07:31:23.99#ibcon#read 5, iclass 18, count 0 2006.201.07:31:23.99#ibcon#about to read 6, iclass 18, count 0 2006.201.07:31:23.99#ibcon#read 6, iclass 18, count 0 2006.201.07:31:23.99#ibcon#end of sib2, iclass 18, count 0 2006.201.07:31:23.99#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:31:23.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:31:23.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:31:23.99#ibcon#*before write, iclass 18, count 0 2006.201.07:31:23.99#ibcon#enter sib2, iclass 18, count 0 2006.201.07:31:23.99#ibcon#flushed, iclass 18, count 0 2006.201.07:31:23.99#ibcon#about to write, iclass 18, count 0 2006.201.07:31:23.99#ibcon#wrote, iclass 18, count 0 2006.201.07:31:23.99#ibcon#about to read 3, iclass 18, count 0 2006.201.07:31:24.04#ibcon#read 3, iclass 18, count 0 2006.201.07:31:24.04#ibcon#about to read 4, iclass 18, count 0 2006.201.07:31:24.04#ibcon#read 4, iclass 18, count 0 2006.201.07:31:24.04#ibcon#about to read 5, iclass 18, count 0 2006.201.07:31:24.04#ibcon#read 5, iclass 18, count 0 2006.201.07:31:24.04#ibcon#about to read 6, iclass 18, count 0 2006.201.07:31:24.04#ibcon#read 6, iclass 18, count 0 2006.201.07:31:24.04#ibcon#end of sib2, iclass 18, count 0 2006.201.07:31:24.04#ibcon#*after write, iclass 18, count 0 2006.201.07:31:24.04#ibcon#*before return 0, iclass 18, count 0 2006.201.07:31:24.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:24.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.07:31:24.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:31:24.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:31:24.04$vck44/vb=8,4 2006.201.07:31:24.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.07:31:24.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.07:31:24.04#ibcon#ireg 11 cls_cnt 2 2006.201.07:31:24.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:24.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:24.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:24.09#ibcon#enter wrdev, iclass 20, count 2 2006.201.07:31:24.09#ibcon#first serial, iclass 20, count 2 2006.201.07:31:24.09#ibcon#enter sib2, iclass 20, count 2 2006.201.07:31:24.09#ibcon#flushed, iclass 20, count 2 2006.201.07:31:24.09#ibcon#about to write, iclass 20, count 2 2006.201.07:31:24.09#ibcon#wrote, iclass 20, count 2 2006.201.07:31:24.09#ibcon#about to read 3, iclass 20, count 2 2006.201.07:31:24.11#ibcon#read 3, iclass 20, count 2 2006.201.07:31:24.11#ibcon#about to read 4, iclass 20, count 2 2006.201.07:31:24.11#ibcon#read 4, iclass 20, count 2 2006.201.07:31:24.11#ibcon#about to read 5, iclass 20, count 2 2006.201.07:31:24.11#ibcon#read 5, iclass 20, count 2 2006.201.07:31:24.11#ibcon#about to read 6, iclass 20, count 2 2006.201.07:31:24.11#ibcon#read 6, iclass 20, count 2 2006.201.07:31:24.11#ibcon#end of sib2, iclass 20, count 2 2006.201.07:31:24.11#ibcon#*mode == 0, iclass 20, count 2 2006.201.07:31:24.11#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.07:31:24.11#ibcon#[27=AT08-04\r\n] 2006.201.07:31:24.11#ibcon#*before write, iclass 20, count 2 2006.201.07:31:24.11#ibcon#enter sib2, iclass 20, count 2 2006.201.07:31:24.11#ibcon#flushed, iclass 20, count 2 2006.201.07:31:24.11#ibcon#about to write, iclass 20, count 2 2006.201.07:31:24.11#ibcon#wrote, iclass 20, count 2 2006.201.07:31:24.11#ibcon#about to read 3, iclass 20, count 2 2006.201.07:31:24.14#ibcon#read 3, iclass 20, count 2 2006.201.07:31:24.14#ibcon#about to read 4, iclass 20, count 2 2006.201.07:31:24.14#ibcon#read 4, iclass 20, count 2 2006.201.07:31:24.14#ibcon#about to read 5, iclass 20, count 2 2006.201.07:31:24.14#ibcon#read 5, iclass 20, count 2 2006.201.07:31:24.14#ibcon#about to read 6, iclass 20, count 2 2006.201.07:31:24.14#ibcon#read 6, iclass 20, count 2 2006.201.07:31:24.14#ibcon#end of sib2, iclass 20, count 2 2006.201.07:31:24.14#ibcon#*after write, iclass 20, count 2 2006.201.07:31:24.14#ibcon#*before return 0, iclass 20, count 2 2006.201.07:31:24.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:24.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.07:31:24.14#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.07:31:24.14#ibcon#ireg 7 cls_cnt 0 2006.201.07:31:24.14#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:24.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:24.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:24.26#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:31:24.26#ibcon#first serial, iclass 20, count 0 2006.201.07:31:24.26#ibcon#enter sib2, iclass 20, count 0 2006.201.07:31:24.26#ibcon#flushed, iclass 20, count 0 2006.201.07:31:24.26#ibcon#about to write, iclass 20, count 0 2006.201.07:31:24.26#ibcon#wrote, iclass 20, count 0 2006.201.07:31:24.26#ibcon#about to read 3, iclass 20, count 0 2006.201.07:31:24.28#ibcon#read 3, iclass 20, count 0 2006.201.07:31:24.28#ibcon#about to read 4, iclass 20, count 0 2006.201.07:31:24.28#ibcon#read 4, iclass 20, count 0 2006.201.07:31:24.28#ibcon#about to read 5, iclass 20, count 0 2006.201.07:31:24.28#ibcon#read 5, iclass 20, count 0 2006.201.07:31:24.28#ibcon#about to read 6, iclass 20, count 0 2006.201.07:31:24.28#ibcon#read 6, iclass 20, count 0 2006.201.07:31:24.28#ibcon#end of sib2, iclass 20, count 0 2006.201.07:31:24.28#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:31:24.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:31:24.28#ibcon#[27=USB\r\n] 2006.201.07:31:24.28#ibcon#*before write, iclass 20, count 0 2006.201.07:31:24.28#ibcon#enter sib2, iclass 20, count 0 2006.201.07:31:24.28#ibcon#flushed, iclass 20, count 0 2006.201.07:31:24.28#ibcon#about to write, iclass 20, count 0 2006.201.07:31:24.28#ibcon#wrote, iclass 20, count 0 2006.201.07:31:24.28#ibcon#about to read 3, iclass 20, count 0 2006.201.07:31:24.31#ibcon#read 3, iclass 20, count 0 2006.201.07:31:24.31#ibcon#about to read 4, iclass 20, count 0 2006.201.07:31:24.31#ibcon#read 4, iclass 20, count 0 2006.201.07:31:24.31#ibcon#about to read 5, iclass 20, count 0 2006.201.07:31:24.31#ibcon#read 5, iclass 20, count 0 2006.201.07:31:24.31#ibcon#about to read 6, iclass 20, count 0 2006.201.07:31:24.31#ibcon#read 6, iclass 20, count 0 2006.201.07:31:24.31#ibcon#end of sib2, iclass 20, count 0 2006.201.07:31:24.31#ibcon#*after write, iclass 20, count 0 2006.201.07:31:24.31#ibcon#*before return 0, iclass 20, count 0 2006.201.07:31:24.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:24.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.07:31:24.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:31:24.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:31:24.31$vck44/vabw=wide 2006.201.07:31:24.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.07:31:24.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.07:31:24.31#ibcon#ireg 8 cls_cnt 0 2006.201.07:31:24.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:24.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:24.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:24.31#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:31:24.31#ibcon#first serial, iclass 22, count 0 2006.201.07:31:24.31#ibcon#enter sib2, iclass 22, count 0 2006.201.07:31:24.31#ibcon#flushed, iclass 22, count 0 2006.201.07:31:24.31#ibcon#about to write, iclass 22, count 0 2006.201.07:31:24.31#ibcon#wrote, iclass 22, count 0 2006.201.07:31:24.31#ibcon#about to read 3, iclass 22, count 0 2006.201.07:31:24.33#ibcon#read 3, iclass 22, count 0 2006.201.07:31:24.33#ibcon#about to read 4, iclass 22, count 0 2006.201.07:31:24.33#ibcon#read 4, iclass 22, count 0 2006.201.07:31:24.33#ibcon#about to read 5, iclass 22, count 0 2006.201.07:31:24.33#ibcon#read 5, iclass 22, count 0 2006.201.07:31:24.33#ibcon#about to read 6, iclass 22, count 0 2006.201.07:31:24.33#ibcon#read 6, iclass 22, count 0 2006.201.07:31:24.33#ibcon#end of sib2, iclass 22, count 0 2006.201.07:31:24.33#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:31:24.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:31:24.33#ibcon#[25=BW32\r\n] 2006.201.07:31:24.33#ibcon#*before write, iclass 22, count 0 2006.201.07:31:24.33#ibcon#enter sib2, iclass 22, count 0 2006.201.07:31:24.33#ibcon#flushed, iclass 22, count 0 2006.201.07:31:24.33#ibcon#about to write, iclass 22, count 0 2006.201.07:31:24.33#ibcon#wrote, iclass 22, count 0 2006.201.07:31:24.33#ibcon#about to read 3, iclass 22, count 0 2006.201.07:31:24.36#ibcon#read 3, iclass 22, count 0 2006.201.07:31:24.36#ibcon#about to read 4, iclass 22, count 0 2006.201.07:31:24.36#ibcon#read 4, iclass 22, count 0 2006.201.07:31:24.36#ibcon#about to read 5, iclass 22, count 0 2006.201.07:31:24.36#ibcon#read 5, iclass 22, count 0 2006.201.07:31:24.36#ibcon#about to read 6, iclass 22, count 0 2006.201.07:31:24.36#ibcon#read 6, iclass 22, count 0 2006.201.07:31:24.36#ibcon#end of sib2, iclass 22, count 0 2006.201.07:31:24.36#ibcon#*after write, iclass 22, count 0 2006.201.07:31:24.36#ibcon#*before return 0, iclass 22, count 0 2006.201.07:31:24.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:24.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.07:31:24.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:31:24.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:31:24.36$vck44/vbbw=wide 2006.201.07:31:24.36#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.07:31:24.36#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.07:31:24.36#ibcon#ireg 8 cls_cnt 0 2006.201.07:31:24.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:31:24.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:31:24.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:31:24.43#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:31:24.43#ibcon#first serial, iclass 24, count 0 2006.201.07:31:24.43#ibcon#enter sib2, iclass 24, count 0 2006.201.07:31:24.43#ibcon#flushed, iclass 24, count 0 2006.201.07:31:24.43#ibcon#about to write, iclass 24, count 0 2006.201.07:31:24.43#ibcon#wrote, iclass 24, count 0 2006.201.07:31:24.43#ibcon#about to read 3, iclass 24, count 0 2006.201.07:31:24.45#ibcon#read 3, iclass 24, count 0 2006.201.07:31:24.45#ibcon#about to read 4, iclass 24, count 0 2006.201.07:31:24.45#ibcon#read 4, iclass 24, count 0 2006.201.07:31:24.45#ibcon#about to read 5, iclass 24, count 0 2006.201.07:31:24.45#ibcon#read 5, iclass 24, count 0 2006.201.07:31:24.45#ibcon#about to read 6, iclass 24, count 0 2006.201.07:31:24.45#ibcon#read 6, iclass 24, count 0 2006.201.07:31:24.45#ibcon#end of sib2, iclass 24, count 0 2006.201.07:31:24.45#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:31:24.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:31:24.45#ibcon#[27=BW32\r\n] 2006.201.07:31:24.45#ibcon#*before write, iclass 24, count 0 2006.201.07:31:24.45#ibcon#enter sib2, iclass 24, count 0 2006.201.07:31:24.45#ibcon#flushed, iclass 24, count 0 2006.201.07:31:24.45#ibcon#about to write, iclass 24, count 0 2006.201.07:31:24.45#ibcon#wrote, iclass 24, count 0 2006.201.07:31:24.45#ibcon#about to read 3, iclass 24, count 0 2006.201.07:31:24.48#ibcon#read 3, iclass 24, count 0 2006.201.07:31:24.48#ibcon#about to read 4, iclass 24, count 0 2006.201.07:31:24.48#ibcon#read 4, iclass 24, count 0 2006.201.07:31:24.48#ibcon#about to read 5, iclass 24, count 0 2006.201.07:31:24.48#ibcon#read 5, iclass 24, count 0 2006.201.07:31:24.48#ibcon#about to read 6, iclass 24, count 0 2006.201.07:31:24.48#ibcon#read 6, iclass 24, count 0 2006.201.07:31:24.48#ibcon#end of sib2, iclass 24, count 0 2006.201.07:31:24.48#ibcon#*after write, iclass 24, count 0 2006.201.07:31:24.48#ibcon#*before return 0, iclass 24, count 0 2006.201.07:31:24.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:31:24.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:31:24.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:31:24.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:31:24.48$setupk4/ifdk4 2006.201.07:31:24.48$ifdk4/lo= 2006.201.07:31:24.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:31:24.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:31:24.48$ifdk4/patch= 2006.201.07:31:24.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:31:24.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:31:24.48$setupk4/!*+20s 2006.201.07:31:27.14#trakl#Source acquired 2006.201.07:31:29.14#flagr#flagr/antenna,acquired 2006.201.07:31:30.56#abcon#<5=/05 2.8 4.6 23.27 881003.0\r\n> 2006.201.07:31:30.58#abcon#{5=INTERFACE CLEAR} 2006.201.07:31:30.64#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:31:38.96$setupk4/"tpicd 2006.201.07:31:38.96$setupk4/echo=off 2006.201.07:31:38.96$setupk4/xlog=off 2006.201.07:31:38.96:!2006.201.07:39:00 2006.201.07:39:00.00:preob 2006.201.07:39:00.14/onsource/TRACKING 2006.201.07:39:00.14:!2006.201.07:39:10 2006.201.07:39:10.00:"tape 2006.201.07:39:10.00:"st=record 2006.201.07:39:10.00:data_valid=on 2006.201.07:39:10.00:midob 2006.201.07:39:11.14/onsource/TRACKING 2006.201.07:39:11.14/wx/23.29,1003.0,88 2006.201.07:39:11.21/cable/+6.4673E-03 2006.201.07:39:12.30/va/01,08,usb,yes,27,29 2006.201.07:39:12.30/va/02,07,usb,yes,30,30 2006.201.07:39:12.30/va/03,08,usb,yes,27,28 2006.201.07:39:12.30/va/04,07,usb,yes,30,32 2006.201.07:39:12.30/va/05,04,usb,yes,27,27 2006.201.07:39:12.30/va/06,05,usb,yes,27,27 2006.201.07:39:12.30/va/07,05,usb,yes,26,27 2006.201.07:39:12.30/va/08,04,usb,yes,26,31 2006.201.07:39:12.53/valo/01,524.99,yes,locked 2006.201.07:39:12.53/valo/02,534.99,yes,locked 2006.201.07:39:12.53/valo/03,564.99,yes,locked 2006.201.07:39:12.53/valo/04,624.99,yes,locked 2006.201.07:39:12.53/valo/05,734.99,yes,locked 2006.201.07:39:12.53/valo/06,814.99,yes,locked 2006.201.07:39:12.53/valo/07,864.99,yes,locked 2006.201.07:39:12.53/valo/08,884.99,yes,locked 2006.201.07:39:13.62/vb/01,04,usb,yes,28,26 2006.201.07:39:13.62/vb/02,05,usb,yes,27,27 2006.201.07:39:13.62/vb/03,04,usb,yes,28,31 2006.201.07:39:13.62/vb/04,05,usb,yes,28,27 2006.201.07:39:13.62/vb/05,04,usb,yes,25,27 2006.201.07:39:13.62/vb/06,04,usb,yes,29,25 2006.201.07:39:13.62/vb/07,04,usb,yes,29,29 2006.201.07:39:13.62/vb/08,04,usb,yes,26,30 2006.201.07:39:13.86/vblo/01,629.99,yes,locked 2006.201.07:39:13.86/vblo/02,634.99,yes,locked 2006.201.07:39:13.86/vblo/03,649.99,yes,locked 2006.201.07:39:13.86/vblo/04,679.99,yes,locked 2006.201.07:39:13.86/vblo/05,709.99,yes,locked 2006.201.07:39:13.86/vblo/06,719.99,yes,locked 2006.201.07:39:13.86/vblo/07,734.99,yes,locked 2006.201.07:39:13.86/vblo/08,744.99,yes,locked 2006.201.07:39:14.01/vabw/8 2006.201.07:39:14.16/vbbw/8 2006.201.07:39:14.33/xfe/off,on,15.0 2006.201.07:39:14.72/ifatt/23,28,28,28 2006.201.07:39:15.05/fmout-gps/S +4.52E-07 2006.201.07:39:15.12:!2006.201.07:45:10 2006.201.07:45:10.00:data_valid=off 2006.201.07:45:10.00:"et 2006.201.07:45:10.00:!+3s 2006.201.07:45:13.02:"tape 2006.201.07:45:13.02:postob 2006.201.07:45:13.24/cable/+6.4667E-03 2006.201.07:45:13.24/wx/23.31,1003.0,89 2006.201.07:45:13.32/fmout-gps/S +4.51E-07 2006.201.07:45:13.32:scan_name=201-0746,jd0607,90 2006.201.07:45:13.32:source=3c274,123049.42,122328.0,2000.0,ccw 2006.201.07:45:14.13#flagr#flagr/antenna,new-source 2006.201.07:45:14.13:checkk5 2006.201.07:45:14.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:45:14.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:45:15.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:45:15.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:45:16.04/chk_obsdata//k5ts1/T2010739??a.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.201.07:45:16.40/chk_obsdata//k5ts2/T2010739??b.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.201.07:45:16.76/chk_obsdata//k5ts3/T2010739??c.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.201.07:45:17.13/chk_obsdata//k5ts4/T2010739??d.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.201.07:45:17.82/k5log//k5ts1_log_newline 2006.201.07:45:18.51/k5log//k5ts2_log_newline 2006.201.07:45:19.22/k5log//k5ts3_log_newline 2006.201.07:45:19.91/k5log//k5ts4_log_newline 2006.201.07:45:19.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:45:19.93:setupk4=1 2006.201.07:45:19.93$setupk4/echo=on 2006.201.07:45:19.93$setupk4/pcalon 2006.201.07:45:19.93$pcalon/"no phase cal control is implemented here 2006.201.07:45:19.93$setupk4/"tpicd=stop 2006.201.07:45:19.93$setupk4/"rec=synch_on 2006.201.07:45:19.93$setupk4/"rec_mode=128 2006.201.07:45:19.93$setupk4/!* 2006.201.07:45:19.93$setupk4/recpk4 2006.201.07:45:19.93$recpk4/recpatch= 2006.201.07:45:19.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:45:19.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:45:19.94$setupk4/vck44 2006.201.07:45:19.94$vck44/valo=1,524.99 2006.201.07:45:19.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.07:45:19.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.07:45:19.94#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:19.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:19.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:19.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:19.94#ibcon#enter wrdev, iclass 33, count 0 2006.201.07:45:19.94#ibcon#first serial, iclass 33, count 0 2006.201.07:45:19.94#ibcon#enter sib2, iclass 33, count 0 2006.201.07:45:19.94#ibcon#flushed, iclass 33, count 0 2006.201.07:45:19.94#ibcon#about to write, iclass 33, count 0 2006.201.07:45:19.94#ibcon#wrote, iclass 33, count 0 2006.201.07:45:19.94#ibcon#about to read 3, iclass 33, count 0 2006.201.07:45:19.97#ibcon#read 3, iclass 33, count 0 2006.201.07:45:19.97#ibcon#about to read 4, iclass 33, count 0 2006.201.07:45:19.97#ibcon#read 4, iclass 33, count 0 2006.201.07:45:19.97#ibcon#about to read 5, iclass 33, count 0 2006.201.07:45:19.97#ibcon#read 5, iclass 33, count 0 2006.201.07:45:19.97#ibcon#about to read 6, iclass 33, count 0 2006.201.07:45:19.97#ibcon#read 6, iclass 33, count 0 2006.201.07:45:19.97#ibcon#end of sib2, iclass 33, count 0 2006.201.07:45:19.97#ibcon#*mode == 0, iclass 33, count 0 2006.201.07:45:19.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.07:45:19.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:45:19.97#ibcon#*before write, iclass 33, count 0 2006.201.07:45:19.97#ibcon#enter sib2, iclass 33, count 0 2006.201.07:45:19.97#ibcon#flushed, iclass 33, count 0 2006.201.07:45:19.97#ibcon#about to write, iclass 33, count 0 2006.201.07:45:19.97#ibcon#wrote, iclass 33, count 0 2006.201.07:45:19.97#ibcon#about to read 3, iclass 33, count 0 2006.201.07:45:20.02#ibcon#read 3, iclass 33, count 0 2006.201.07:45:20.02#ibcon#about to read 4, iclass 33, count 0 2006.201.07:45:20.02#ibcon#read 4, iclass 33, count 0 2006.201.07:45:20.02#ibcon#about to read 5, iclass 33, count 0 2006.201.07:45:20.02#ibcon#read 5, iclass 33, count 0 2006.201.07:45:20.02#ibcon#about to read 6, iclass 33, count 0 2006.201.07:45:20.02#ibcon#read 6, iclass 33, count 0 2006.201.07:45:20.02#ibcon#end of sib2, iclass 33, count 0 2006.201.07:45:20.02#ibcon#*after write, iclass 33, count 0 2006.201.07:45:20.02#ibcon#*before return 0, iclass 33, count 0 2006.201.07:45:20.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:20.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:20.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.07:45:20.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.07:45:20.02$vck44/va=1,8 2006.201.07:45:20.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.07:45:20.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.07:45:20.02#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:20.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:20.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:20.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:20.02#ibcon#enter wrdev, iclass 35, count 2 2006.201.07:45:20.02#ibcon#first serial, iclass 35, count 2 2006.201.07:45:20.02#ibcon#enter sib2, iclass 35, count 2 2006.201.07:45:20.02#ibcon#flushed, iclass 35, count 2 2006.201.07:45:20.02#ibcon#about to write, iclass 35, count 2 2006.201.07:45:20.02#ibcon#wrote, iclass 35, count 2 2006.201.07:45:20.02#ibcon#about to read 3, iclass 35, count 2 2006.201.07:45:20.04#ibcon#read 3, iclass 35, count 2 2006.201.07:45:20.04#ibcon#about to read 4, iclass 35, count 2 2006.201.07:45:20.04#ibcon#read 4, iclass 35, count 2 2006.201.07:45:20.04#ibcon#about to read 5, iclass 35, count 2 2006.201.07:45:20.04#ibcon#read 5, iclass 35, count 2 2006.201.07:45:20.04#ibcon#about to read 6, iclass 35, count 2 2006.201.07:45:20.04#ibcon#read 6, iclass 35, count 2 2006.201.07:45:20.04#ibcon#end of sib2, iclass 35, count 2 2006.201.07:45:20.04#ibcon#*mode == 0, iclass 35, count 2 2006.201.07:45:20.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.07:45:20.04#ibcon#[25=AT01-08\r\n] 2006.201.07:45:20.04#ibcon#*before write, iclass 35, count 2 2006.201.07:45:20.04#ibcon#enter sib2, iclass 35, count 2 2006.201.07:45:20.04#ibcon#flushed, iclass 35, count 2 2006.201.07:45:20.04#ibcon#about to write, iclass 35, count 2 2006.201.07:45:20.04#ibcon#wrote, iclass 35, count 2 2006.201.07:45:20.04#ibcon#about to read 3, iclass 35, count 2 2006.201.07:45:20.07#ibcon#read 3, iclass 35, count 2 2006.201.07:45:20.07#ibcon#about to read 4, iclass 35, count 2 2006.201.07:45:20.07#ibcon#read 4, iclass 35, count 2 2006.201.07:45:20.07#ibcon#about to read 5, iclass 35, count 2 2006.201.07:45:20.07#ibcon#read 5, iclass 35, count 2 2006.201.07:45:20.07#ibcon#about to read 6, iclass 35, count 2 2006.201.07:45:20.07#ibcon#read 6, iclass 35, count 2 2006.201.07:45:20.07#ibcon#end of sib2, iclass 35, count 2 2006.201.07:45:20.07#ibcon#*after write, iclass 35, count 2 2006.201.07:45:20.07#ibcon#*before return 0, iclass 35, count 2 2006.201.07:45:20.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:20.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:20.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.07:45:20.07#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:20.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:20.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:20.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:20.19#ibcon#enter wrdev, iclass 35, count 0 2006.201.07:45:20.19#ibcon#first serial, iclass 35, count 0 2006.201.07:45:20.19#ibcon#enter sib2, iclass 35, count 0 2006.201.07:45:20.19#ibcon#flushed, iclass 35, count 0 2006.201.07:45:20.19#ibcon#about to write, iclass 35, count 0 2006.201.07:45:20.19#ibcon#wrote, iclass 35, count 0 2006.201.07:45:20.19#ibcon#about to read 3, iclass 35, count 0 2006.201.07:45:20.21#ibcon#read 3, iclass 35, count 0 2006.201.07:45:20.21#ibcon#about to read 4, iclass 35, count 0 2006.201.07:45:20.21#ibcon#read 4, iclass 35, count 0 2006.201.07:45:20.21#ibcon#about to read 5, iclass 35, count 0 2006.201.07:45:20.21#ibcon#read 5, iclass 35, count 0 2006.201.07:45:20.21#ibcon#about to read 6, iclass 35, count 0 2006.201.07:45:20.21#ibcon#read 6, iclass 35, count 0 2006.201.07:45:20.21#ibcon#end of sib2, iclass 35, count 0 2006.201.07:45:20.21#ibcon#*mode == 0, iclass 35, count 0 2006.201.07:45:20.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.07:45:20.21#ibcon#[25=USB\r\n] 2006.201.07:45:20.21#ibcon#*before write, iclass 35, count 0 2006.201.07:45:20.21#ibcon#enter sib2, iclass 35, count 0 2006.201.07:45:20.21#ibcon#flushed, iclass 35, count 0 2006.201.07:45:20.21#ibcon#about to write, iclass 35, count 0 2006.201.07:45:20.21#ibcon#wrote, iclass 35, count 0 2006.201.07:45:20.21#ibcon#about to read 3, iclass 35, count 0 2006.201.07:45:20.24#ibcon#read 3, iclass 35, count 0 2006.201.07:45:20.24#ibcon#about to read 4, iclass 35, count 0 2006.201.07:45:20.24#ibcon#read 4, iclass 35, count 0 2006.201.07:45:20.24#ibcon#about to read 5, iclass 35, count 0 2006.201.07:45:20.24#ibcon#read 5, iclass 35, count 0 2006.201.07:45:20.24#ibcon#about to read 6, iclass 35, count 0 2006.201.07:45:20.24#ibcon#read 6, iclass 35, count 0 2006.201.07:45:20.24#ibcon#end of sib2, iclass 35, count 0 2006.201.07:45:20.24#ibcon#*after write, iclass 35, count 0 2006.201.07:45:20.24#ibcon#*before return 0, iclass 35, count 0 2006.201.07:45:20.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:20.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:20.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.07:45:20.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.07:45:20.24$vck44/valo=2,534.99 2006.201.07:45:20.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.07:45:20.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.07:45:20.24#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:20.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:20.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:20.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:20.24#ibcon#enter wrdev, iclass 37, count 0 2006.201.07:45:20.24#ibcon#first serial, iclass 37, count 0 2006.201.07:45:20.24#ibcon#enter sib2, iclass 37, count 0 2006.201.07:45:20.24#ibcon#flushed, iclass 37, count 0 2006.201.07:45:20.24#ibcon#about to write, iclass 37, count 0 2006.201.07:45:20.24#ibcon#wrote, iclass 37, count 0 2006.201.07:45:20.24#ibcon#about to read 3, iclass 37, count 0 2006.201.07:45:20.26#ibcon#read 3, iclass 37, count 0 2006.201.07:45:20.26#ibcon#about to read 4, iclass 37, count 0 2006.201.07:45:20.26#ibcon#read 4, iclass 37, count 0 2006.201.07:45:20.26#ibcon#about to read 5, iclass 37, count 0 2006.201.07:45:20.26#ibcon#read 5, iclass 37, count 0 2006.201.07:45:20.26#ibcon#about to read 6, iclass 37, count 0 2006.201.07:45:20.26#ibcon#read 6, iclass 37, count 0 2006.201.07:45:20.26#ibcon#end of sib2, iclass 37, count 0 2006.201.07:45:20.26#ibcon#*mode == 0, iclass 37, count 0 2006.201.07:45:20.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.07:45:20.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:45:20.26#ibcon#*before write, iclass 37, count 0 2006.201.07:45:20.26#ibcon#enter sib2, iclass 37, count 0 2006.201.07:45:20.26#ibcon#flushed, iclass 37, count 0 2006.201.07:45:20.26#ibcon#about to write, iclass 37, count 0 2006.201.07:45:20.26#ibcon#wrote, iclass 37, count 0 2006.201.07:45:20.26#ibcon#about to read 3, iclass 37, count 0 2006.201.07:45:20.31#ibcon#read 3, iclass 37, count 0 2006.201.07:45:20.31#ibcon#about to read 4, iclass 37, count 0 2006.201.07:45:20.31#ibcon#read 4, iclass 37, count 0 2006.201.07:45:20.31#ibcon#about to read 5, iclass 37, count 0 2006.201.07:45:20.31#ibcon#read 5, iclass 37, count 0 2006.201.07:45:20.31#ibcon#about to read 6, iclass 37, count 0 2006.201.07:45:20.31#ibcon#read 6, iclass 37, count 0 2006.201.07:45:20.31#ibcon#end of sib2, iclass 37, count 0 2006.201.07:45:20.31#ibcon#*after write, iclass 37, count 0 2006.201.07:45:20.31#ibcon#*before return 0, iclass 37, count 0 2006.201.07:45:20.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:20.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:20.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.07:45:20.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.07:45:20.31$vck44/va=2,7 2006.201.07:45:20.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.07:45:20.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.07:45:20.31#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:20.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:20.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:20.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:20.36#ibcon#enter wrdev, iclass 39, count 2 2006.201.07:45:20.36#ibcon#first serial, iclass 39, count 2 2006.201.07:45:20.36#ibcon#enter sib2, iclass 39, count 2 2006.201.07:45:20.36#ibcon#flushed, iclass 39, count 2 2006.201.07:45:20.36#ibcon#about to write, iclass 39, count 2 2006.201.07:45:20.36#ibcon#wrote, iclass 39, count 2 2006.201.07:45:20.36#ibcon#about to read 3, iclass 39, count 2 2006.201.07:45:20.38#ibcon#read 3, iclass 39, count 2 2006.201.07:45:20.38#ibcon#about to read 4, iclass 39, count 2 2006.201.07:45:20.38#ibcon#read 4, iclass 39, count 2 2006.201.07:45:20.38#ibcon#about to read 5, iclass 39, count 2 2006.201.07:45:20.38#ibcon#read 5, iclass 39, count 2 2006.201.07:45:20.38#ibcon#about to read 6, iclass 39, count 2 2006.201.07:45:20.38#ibcon#read 6, iclass 39, count 2 2006.201.07:45:20.38#ibcon#end of sib2, iclass 39, count 2 2006.201.07:45:20.38#ibcon#*mode == 0, iclass 39, count 2 2006.201.07:45:20.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.07:45:20.38#ibcon#[25=AT02-07\r\n] 2006.201.07:45:20.38#ibcon#*before write, iclass 39, count 2 2006.201.07:45:20.38#ibcon#enter sib2, iclass 39, count 2 2006.201.07:45:20.38#ibcon#flushed, iclass 39, count 2 2006.201.07:45:20.38#ibcon#about to write, iclass 39, count 2 2006.201.07:45:20.38#ibcon#wrote, iclass 39, count 2 2006.201.07:45:20.38#ibcon#about to read 3, iclass 39, count 2 2006.201.07:45:20.41#ibcon#read 3, iclass 39, count 2 2006.201.07:45:20.41#ibcon#about to read 4, iclass 39, count 2 2006.201.07:45:20.41#ibcon#read 4, iclass 39, count 2 2006.201.07:45:20.41#ibcon#about to read 5, iclass 39, count 2 2006.201.07:45:20.41#ibcon#read 5, iclass 39, count 2 2006.201.07:45:20.41#ibcon#about to read 6, iclass 39, count 2 2006.201.07:45:20.41#ibcon#read 6, iclass 39, count 2 2006.201.07:45:20.41#ibcon#end of sib2, iclass 39, count 2 2006.201.07:45:20.41#ibcon#*after write, iclass 39, count 2 2006.201.07:45:20.41#ibcon#*before return 0, iclass 39, count 2 2006.201.07:45:20.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:20.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:20.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.07:45:20.41#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:20.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:20.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:20.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:20.53#ibcon#enter wrdev, iclass 39, count 0 2006.201.07:45:20.53#ibcon#first serial, iclass 39, count 0 2006.201.07:45:20.53#ibcon#enter sib2, iclass 39, count 0 2006.201.07:45:20.53#ibcon#flushed, iclass 39, count 0 2006.201.07:45:20.53#ibcon#about to write, iclass 39, count 0 2006.201.07:45:20.53#ibcon#wrote, iclass 39, count 0 2006.201.07:45:20.53#ibcon#about to read 3, iclass 39, count 0 2006.201.07:45:20.55#ibcon#read 3, iclass 39, count 0 2006.201.07:45:20.55#ibcon#about to read 4, iclass 39, count 0 2006.201.07:45:20.55#ibcon#read 4, iclass 39, count 0 2006.201.07:45:20.55#ibcon#about to read 5, iclass 39, count 0 2006.201.07:45:20.55#ibcon#read 5, iclass 39, count 0 2006.201.07:45:20.55#ibcon#about to read 6, iclass 39, count 0 2006.201.07:45:20.55#ibcon#read 6, iclass 39, count 0 2006.201.07:45:20.55#ibcon#end of sib2, iclass 39, count 0 2006.201.07:45:20.55#ibcon#*mode == 0, iclass 39, count 0 2006.201.07:45:20.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.07:45:20.55#ibcon#[25=USB\r\n] 2006.201.07:45:20.55#ibcon#*before write, iclass 39, count 0 2006.201.07:45:20.55#ibcon#enter sib2, iclass 39, count 0 2006.201.07:45:20.55#ibcon#flushed, iclass 39, count 0 2006.201.07:45:20.55#ibcon#about to write, iclass 39, count 0 2006.201.07:45:20.55#ibcon#wrote, iclass 39, count 0 2006.201.07:45:20.55#ibcon#about to read 3, iclass 39, count 0 2006.201.07:45:20.58#ibcon#read 3, iclass 39, count 0 2006.201.07:45:20.58#ibcon#about to read 4, iclass 39, count 0 2006.201.07:45:20.58#ibcon#read 4, iclass 39, count 0 2006.201.07:45:20.58#ibcon#about to read 5, iclass 39, count 0 2006.201.07:45:20.58#ibcon#read 5, iclass 39, count 0 2006.201.07:45:20.58#ibcon#about to read 6, iclass 39, count 0 2006.201.07:45:20.58#ibcon#read 6, iclass 39, count 0 2006.201.07:45:20.58#ibcon#end of sib2, iclass 39, count 0 2006.201.07:45:20.58#ibcon#*after write, iclass 39, count 0 2006.201.07:45:20.58#ibcon#*before return 0, iclass 39, count 0 2006.201.07:45:20.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:20.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:20.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.07:45:20.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.07:45:20.58$vck44/valo=3,564.99 2006.201.07:45:20.58#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.07:45:20.58#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.07:45:20.58#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:20.58#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:20.58#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:20.58#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:20.58#ibcon#enter wrdev, iclass 2, count 0 2006.201.07:45:20.58#ibcon#first serial, iclass 2, count 0 2006.201.07:45:20.58#ibcon#enter sib2, iclass 2, count 0 2006.201.07:45:20.58#ibcon#flushed, iclass 2, count 0 2006.201.07:45:20.58#ibcon#about to write, iclass 2, count 0 2006.201.07:45:20.58#ibcon#wrote, iclass 2, count 0 2006.201.07:45:20.58#ibcon#about to read 3, iclass 2, count 0 2006.201.07:45:20.60#ibcon#read 3, iclass 2, count 0 2006.201.07:45:20.60#ibcon#about to read 4, iclass 2, count 0 2006.201.07:45:20.60#ibcon#read 4, iclass 2, count 0 2006.201.07:45:20.60#ibcon#about to read 5, iclass 2, count 0 2006.201.07:45:20.60#ibcon#read 5, iclass 2, count 0 2006.201.07:45:20.60#ibcon#about to read 6, iclass 2, count 0 2006.201.07:45:20.60#ibcon#read 6, iclass 2, count 0 2006.201.07:45:20.60#ibcon#end of sib2, iclass 2, count 0 2006.201.07:45:20.60#ibcon#*mode == 0, iclass 2, count 0 2006.201.07:45:20.60#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.07:45:20.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:45:20.60#ibcon#*before write, iclass 2, count 0 2006.201.07:45:20.60#ibcon#enter sib2, iclass 2, count 0 2006.201.07:45:20.60#ibcon#flushed, iclass 2, count 0 2006.201.07:45:20.60#ibcon#about to write, iclass 2, count 0 2006.201.07:45:20.60#ibcon#wrote, iclass 2, count 0 2006.201.07:45:20.60#ibcon#about to read 3, iclass 2, count 0 2006.201.07:45:20.64#ibcon#read 3, iclass 2, count 0 2006.201.07:45:20.64#ibcon#about to read 4, iclass 2, count 0 2006.201.07:45:20.64#ibcon#read 4, iclass 2, count 0 2006.201.07:45:20.64#ibcon#about to read 5, iclass 2, count 0 2006.201.07:45:20.64#ibcon#read 5, iclass 2, count 0 2006.201.07:45:20.64#ibcon#about to read 6, iclass 2, count 0 2006.201.07:45:20.64#ibcon#read 6, iclass 2, count 0 2006.201.07:45:20.64#ibcon#end of sib2, iclass 2, count 0 2006.201.07:45:20.64#ibcon#*after write, iclass 2, count 0 2006.201.07:45:20.64#ibcon#*before return 0, iclass 2, count 0 2006.201.07:45:20.64#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:20.64#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:20.64#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.07:45:20.64#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.07:45:20.64$vck44/va=3,8 2006.201.07:45:20.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.07:45:20.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.07:45:20.64#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:20.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:20.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:20.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:20.70#ibcon#enter wrdev, iclass 5, count 2 2006.201.07:45:20.70#ibcon#first serial, iclass 5, count 2 2006.201.07:45:20.70#ibcon#enter sib2, iclass 5, count 2 2006.201.07:45:20.70#ibcon#flushed, iclass 5, count 2 2006.201.07:45:20.70#ibcon#about to write, iclass 5, count 2 2006.201.07:45:20.70#ibcon#wrote, iclass 5, count 2 2006.201.07:45:20.70#ibcon#about to read 3, iclass 5, count 2 2006.201.07:45:20.72#ibcon#read 3, iclass 5, count 2 2006.201.07:45:20.72#ibcon#about to read 4, iclass 5, count 2 2006.201.07:45:20.72#ibcon#read 4, iclass 5, count 2 2006.201.07:45:20.72#ibcon#about to read 5, iclass 5, count 2 2006.201.07:45:20.72#ibcon#read 5, iclass 5, count 2 2006.201.07:45:20.72#ibcon#about to read 6, iclass 5, count 2 2006.201.07:45:20.72#ibcon#read 6, iclass 5, count 2 2006.201.07:45:20.72#ibcon#end of sib2, iclass 5, count 2 2006.201.07:45:20.72#ibcon#*mode == 0, iclass 5, count 2 2006.201.07:45:20.72#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.07:45:20.72#ibcon#[25=AT03-08\r\n] 2006.201.07:45:20.72#ibcon#*before write, iclass 5, count 2 2006.201.07:45:20.72#ibcon#enter sib2, iclass 5, count 2 2006.201.07:45:20.72#ibcon#flushed, iclass 5, count 2 2006.201.07:45:20.72#ibcon#about to write, iclass 5, count 2 2006.201.07:45:20.72#ibcon#wrote, iclass 5, count 2 2006.201.07:45:20.72#ibcon#about to read 3, iclass 5, count 2 2006.201.07:45:20.75#ibcon#read 3, iclass 5, count 2 2006.201.07:45:20.75#ibcon#about to read 4, iclass 5, count 2 2006.201.07:45:20.75#ibcon#read 4, iclass 5, count 2 2006.201.07:45:20.75#ibcon#about to read 5, iclass 5, count 2 2006.201.07:45:20.75#ibcon#read 5, iclass 5, count 2 2006.201.07:45:20.75#ibcon#about to read 6, iclass 5, count 2 2006.201.07:45:20.75#ibcon#read 6, iclass 5, count 2 2006.201.07:45:20.75#ibcon#end of sib2, iclass 5, count 2 2006.201.07:45:20.75#ibcon#*after write, iclass 5, count 2 2006.201.07:45:20.75#ibcon#*before return 0, iclass 5, count 2 2006.201.07:45:20.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:20.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:20.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.07:45:20.75#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:20.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:20.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:20.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:20.87#ibcon#enter wrdev, iclass 5, count 0 2006.201.07:45:20.87#ibcon#first serial, iclass 5, count 0 2006.201.07:45:20.87#ibcon#enter sib2, iclass 5, count 0 2006.201.07:45:20.87#ibcon#flushed, iclass 5, count 0 2006.201.07:45:20.87#ibcon#about to write, iclass 5, count 0 2006.201.07:45:20.87#ibcon#wrote, iclass 5, count 0 2006.201.07:45:20.87#ibcon#about to read 3, iclass 5, count 0 2006.201.07:45:20.89#ibcon#read 3, iclass 5, count 0 2006.201.07:45:20.89#ibcon#about to read 4, iclass 5, count 0 2006.201.07:45:20.89#ibcon#read 4, iclass 5, count 0 2006.201.07:45:20.89#ibcon#about to read 5, iclass 5, count 0 2006.201.07:45:20.89#ibcon#read 5, iclass 5, count 0 2006.201.07:45:20.89#ibcon#about to read 6, iclass 5, count 0 2006.201.07:45:20.89#ibcon#read 6, iclass 5, count 0 2006.201.07:45:20.89#ibcon#end of sib2, iclass 5, count 0 2006.201.07:45:20.89#ibcon#*mode == 0, iclass 5, count 0 2006.201.07:45:20.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.07:45:20.89#ibcon#[25=USB\r\n] 2006.201.07:45:20.89#ibcon#*before write, iclass 5, count 0 2006.201.07:45:20.89#ibcon#enter sib2, iclass 5, count 0 2006.201.07:45:20.89#ibcon#flushed, iclass 5, count 0 2006.201.07:45:20.89#ibcon#about to write, iclass 5, count 0 2006.201.07:45:20.89#ibcon#wrote, iclass 5, count 0 2006.201.07:45:20.89#ibcon#about to read 3, iclass 5, count 0 2006.201.07:45:20.92#ibcon#read 3, iclass 5, count 0 2006.201.07:45:20.92#ibcon#about to read 4, iclass 5, count 0 2006.201.07:45:20.92#ibcon#read 4, iclass 5, count 0 2006.201.07:45:20.92#ibcon#about to read 5, iclass 5, count 0 2006.201.07:45:20.92#ibcon#read 5, iclass 5, count 0 2006.201.07:45:20.92#ibcon#about to read 6, iclass 5, count 0 2006.201.07:45:20.92#ibcon#read 6, iclass 5, count 0 2006.201.07:45:20.92#ibcon#end of sib2, iclass 5, count 0 2006.201.07:45:20.92#ibcon#*after write, iclass 5, count 0 2006.201.07:45:20.92#ibcon#*before return 0, iclass 5, count 0 2006.201.07:45:20.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:20.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:20.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.07:45:20.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.07:45:20.92$vck44/valo=4,624.99 2006.201.07:45:20.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.07:45:20.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.07:45:20.92#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:20.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:20.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:20.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:20.92#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:45:20.92#ibcon#first serial, iclass 7, count 0 2006.201.07:45:20.92#ibcon#enter sib2, iclass 7, count 0 2006.201.07:45:20.92#ibcon#flushed, iclass 7, count 0 2006.201.07:45:20.92#ibcon#about to write, iclass 7, count 0 2006.201.07:45:20.92#ibcon#wrote, iclass 7, count 0 2006.201.07:45:20.92#ibcon#about to read 3, iclass 7, count 0 2006.201.07:45:20.94#ibcon#read 3, iclass 7, count 0 2006.201.07:45:20.94#ibcon#about to read 4, iclass 7, count 0 2006.201.07:45:20.94#ibcon#read 4, iclass 7, count 0 2006.201.07:45:20.94#ibcon#about to read 5, iclass 7, count 0 2006.201.07:45:20.94#ibcon#read 5, iclass 7, count 0 2006.201.07:45:20.94#ibcon#about to read 6, iclass 7, count 0 2006.201.07:45:20.94#ibcon#read 6, iclass 7, count 0 2006.201.07:45:20.94#ibcon#end of sib2, iclass 7, count 0 2006.201.07:45:20.94#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:45:20.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:45:20.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:45:20.94#ibcon#*before write, iclass 7, count 0 2006.201.07:45:20.94#ibcon#enter sib2, iclass 7, count 0 2006.201.07:45:20.94#ibcon#flushed, iclass 7, count 0 2006.201.07:45:20.94#ibcon#about to write, iclass 7, count 0 2006.201.07:45:20.94#ibcon#wrote, iclass 7, count 0 2006.201.07:45:20.94#ibcon#about to read 3, iclass 7, count 0 2006.201.07:45:20.99#ibcon#read 3, iclass 7, count 0 2006.201.07:45:20.99#ibcon#about to read 4, iclass 7, count 0 2006.201.07:45:20.99#ibcon#read 4, iclass 7, count 0 2006.201.07:45:20.99#ibcon#about to read 5, iclass 7, count 0 2006.201.07:45:20.99#ibcon#read 5, iclass 7, count 0 2006.201.07:45:20.99#ibcon#about to read 6, iclass 7, count 0 2006.201.07:45:20.99#ibcon#read 6, iclass 7, count 0 2006.201.07:45:20.99#ibcon#end of sib2, iclass 7, count 0 2006.201.07:45:20.99#ibcon#*after write, iclass 7, count 0 2006.201.07:45:20.99#ibcon#*before return 0, iclass 7, count 0 2006.201.07:45:20.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:20.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:20.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:45:20.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:45:20.99$vck44/va=4,7 2006.201.07:45:20.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.07:45:20.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.07:45:20.99#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:20.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:21.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:21.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:21.04#ibcon#enter wrdev, iclass 11, count 2 2006.201.07:45:21.04#ibcon#first serial, iclass 11, count 2 2006.201.07:45:21.04#ibcon#enter sib2, iclass 11, count 2 2006.201.07:45:21.04#ibcon#flushed, iclass 11, count 2 2006.201.07:45:21.04#ibcon#about to write, iclass 11, count 2 2006.201.07:45:21.04#ibcon#wrote, iclass 11, count 2 2006.201.07:45:21.04#ibcon#about to read 3, iclass 11, count 2 2006.201.07:45:21.06#ibcon#read 3, iclass 11, count 2 2006.201.07:45:21.06#ibcon#about to read 4, iclass 11, count 2 2006.201.07:45:21.06#ibcon#read 4, iclass 11, count 2 2006.201.07:45:21.06#ibcon#about to read 5, iclass 11, count 2 2006.201.07:45:21.06#ibcon#read 5, iclass 11, count 2 2006.201.07:45:21.06#ibcon#about to read 6, iclass 11, count 2 2006.201.07:45:21.06#ibcon#read 6, iclass 11, count 2 2006.201.07:45:21.06#ibcon#end of sib2, iclass 11, count 2 2006.201.07:45:21.06#ibcon#*mode == 0, iclass 11, count 2 2006.201.07:45:21.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.07:45:21.06#ibcon#[25=AT04-07\r\n] 2006.201.07:45:21.06#ibcon#*before write, iclass 11, count 2 2006.201.07:45:21.06#ibcon#enter sib2, iclass 11, count 2 2006.201.07:45:21.06#ibcon#flushed, iclass 11, count 2 2006.201.07:45:21.06#ibcon#about to write, iclass 11, count 2 2006.201.07:45:21.06#ibcon#wrote, iclass 11, count 2 2006.201.07:45:21.06#ibcon#about to read 3, iclass 11, count 2 2006.201.07:45:21.09#ibcon#read 3, iclass 11, count 2 2006.201.07:45:21.09#ibcon#about to read 4, iclass 11, count 2 2006.201.07:45:21.09#ibcon#read 4, iclass 11, count 2 2006.201.07:45:21.09#ibcon#about to read 5, iclass 11, count 2 2006.201.07:45:21.09#ibcon#read 5, iclass 11, count 2 2006.201.07:45:21.09#ibcon#about to read 6, iclass 11, count 2 2006.201.07:45:21.09#ibcon#read 6, iclass 11, count 2 2006.201.07:45:21.09#ibcon#end of sib2, iclass 11, count 2 2006.201.07:45:21.09#ibcon#*after write, iclass 11, count 2 2006.201.07:45:21.09#ibcon#*before return 0, iclass 11, count 2 2006.201.07:45:21.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:21.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:21.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.07:45:21.09#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:21.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:21.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:21.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:21.21#ibcon#enter wrdev, iclass 11, count 0 2006.201.07:45:21.21#ibcon#first serial, iclass 11, count 0 2006.201.07:45:21.21#ibcon#enter sib2, iclass 11, count 0 2006.201.07:45:21.21#ibcon#flushed, iclass 11, count 0 2006.201.07:45:21.21#ibcon#about to write, iclass 11, count 0 2006.201.07:45:21.21#ibcon#wrote, iclass 11, count 0 2006.201.07:45:21.21#ibcon#about to read 3, iclass 11, count 0 2006.201.07:45:21.23#ibcon#read 3, iclass 11, count 0 2006.201.07:45:21.23#ibcon#about to read 4, iclass 11, count 0 2006.201.07:45:21.23#ibcon#read 4, iclass 11, count 0 2006.201.07:45:21.23#ibcon#about to read 5, iclass 11, count 0 2006.201.07:45:21.23#ibcon#read 5, iclass 11, count 0 2006.201.07:45:21.23#ibcon#about to read 6, iclass 11, count 0 2006.201.07:45:21.23#ibcon#read 6, iclass 11, count 0 2006.201.07:45:21.23#ibcon#end of sib2, iclass 11, count 0 2006.201.07:45:21.23#ibcon#*mode == 0, iclass 11, count 0 2006.201.07:45:21.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.07:45:21.23#ibcon#[25=USB\r\n] 2006.201.07:45:21.23#ibcon#*before write, iclass 11, count 0 2006.201.07:45:21.23#ibcon#enter sib2, iclass 11, count 0 2006.201.07:45:21.23#ibcon#flushed, iclass 11, count 0 2006.201.07:45:21.23#ibcon#about to write, iclass 11, count 0 2006.201.07:45:21.23#ibcon#wrote, iclass 11, count 0 2006.201.07:45:21.23#ibcon#about to read 3, iclass 11, count 0 2006.201.07:45:21.26#ibcon#read 3, iclass 11, count 0 2006.201.07:45:21.26#ibcon#about to read 4, iclass 11, count 0 2006.201.07:45:21.26#ibcon#read 4, iclass 11, count 0 2006.201.07:45:21.26#ibcon#about to read 5, iclass 11, count 0 2006.201.07:45:21.26#ibcon#read 5, iclass 11, count 0 2006.201.07:45:21.26#ibcon#about to read 6, iclass 11, count 0 2006.201.07:45:21.26#ibcon#read 6, iclass 11, count 0 2006.201.07:45:21.26#ibcon#end of sib2, iclass 11, count 0 2006.201.07:45:21.26#ibcon#*after write, iclass 11, count 0 2006.201.07:45:21.26#ibcon#*before return 0, iclass 11, count 0 2006.201.07:45:21.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:21.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:21.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.07:45:21.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.07:45:21.26$vck44/valo=5,734.99 2006.201.07:45:21.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.07:45:21.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.07:45:21.26#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:21.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:21.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:21.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:21.26#ibcon#enter wrdev, iclass 13, count 0 2006.201.07:45:21.26#ibcon#first serial, iclass 13, count 0 2006.201.07:45:21.26#ibcon#enter sib2, iclass 13, count 0 2006.201.07:45:21.26#ibcon#flushed, iclass 13, count 0 2006.201.07:45:21.26#ibcon#about to write, iclass 13, count 0 2006.201.07:45:21.26#ibcon#wrote, iclass 13, count 0 2006.201.07:45:21.26#ibcon#about to read 3, iclass 13, count 0 2006.201.07:45:21.28#ibcon#read 3, iclass 13, count 0 2006.201.07:45:21.28#ibcon#about to read 4, iclass 13, count 0 2006.201.07:45:21.28#ibcon#read 4, iclass 13, count 0 2006.201.07:45:21.28#ibcon#about to read 5, iclass 13, count 0 2006.201.07:45:21.28#ibcon#read 5, iclass 13, count 0 2006.201.07:45:21.28#ibcon#about to read 6, iclass 13, count 0 2006.201.07:45:21.28#ibcon#read 6, iclass 13, count 0 2006.201.07:45:21.28#ibcon#end of sib2, iclass 13, count 0 2006.201.07:45:21.28#ibcon#*mode == 0, iclass 13, count 0 2006.201.07:45:21.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.07:45:21.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:45:21.28#ibcon#*before write, iclass 13, count 0 2006.201.07:45:21.28#ibcon#enter sib2, iclass 13, count 0 2006.201.07:45:21.28#ibcon#flushed, iclass 13, count 0 2006.201.07:45:21.28#ibcon#about to write, iclass 13, count 0 2006.201.07:45:21.28#ibcon#wrote, iclass 13, count 0 2006.201.07:45:21.28#ibcon#about to read 3, iclass 13, count 0 2006.201.07:45:21.32#ibcon#read 3, iclass 13, count 0 2006.201.07:45:21.32#ibcon#about to read 4, iclass 13, count 0 2006.201.07:45:21.32#ibcon#read 4, iclass 13, count 0 2006.201.07:45:21.32#ibcon#about to read 5, iclass 13, count 0 2006.201.07:45:21.32#ibcon#read 5, iclass 13, count 0 2006.201.07:45:21.32#ibcon#about to read 6, iclass 13, count 0 2006.201.07:45:21.32#ibcon#read 6, iclass 13, count 0 2006.201.07:45:21.32#ibcon#end of sib2, iclass 13, count 0 2006.201.07:45:21.32#ibcon#*after write, iclass 13, count 0 2006.201.07:45:21.32#ibcon#*before return 0, iclass 13, count 0 2006.201.07:45:21.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:21.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:21.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.07:45:21.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.07:45:21.32$vck44/va=5,4 2006.201.07:45:21.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.07:45:21.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.07:45:21.32#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:21.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:21.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:21.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:21.38#ibcon#enter wrdev, iclass 15, count 2 2006.201.07:45:21.38#ibcon#first serial, iclass 15, count 2 2006.201.07:45:21.38#ibcon#enter sib2, iclass 15, count 2 2006.201.07:45:21.38#ibcon#flushed, iclass 15, count 2 2006.201.07:45:21.38#ibcon#about to write, iclass 15, count 2 2006.201.07:45:21.38#ibcon#wrote, iclass 15, count 2 2006.201.07:45:21.38#ibcon#about to read 3, iclass 15, count 2 2006.201.07:45:21.40#ibcon#read 3, iclass 15, count 2 2006.201.07:45:21.40#ibcon#about to read 4, iclass 15, count 2 2006.201.07:45:21.40#ibcon#read 4, iclass 15, count 2 2006.201.07:45:21.40#ibcon#about to read 5, iclass 15, count 2 2006.201.07:45:21.40#ibcon#read 5, iclass 15, count 2 2006.201.07:45:21.40#ibcon#about to read 6, iclass 15, count 2 2006.201.07:45:21.40#ibcon#read 6, iclass 15, count 2 2006.201.07:45:21.40#ibcon#end of sib2, iclass 15, count 2 2006.201.07:45:21.40#ibcon#*mode == 0, iclass 15, count 2 2006.201.07:45:21.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.07:45:21.40#ibcon#[25=AT05-04\r\n] 2006.201.07:45:21.40#ibcon#*before write, iclass 15, count 2 2006.201.07:45:21.40#ibcon#enter sib2, iclass 15, count 2 2006.201.07:45:21.40#ibcon#flushed, iclass 15, count 2 2006.201.07:45:21.40#ibcon#about to write, iclass 15, count 2 2006.201.07:45:21.40#ibcon#wrote, iclass 15, count 2 2006.201.07:45:21.40#ibcon#about to read 3, iclass 15, count 2 2006.201.07:45:21.43#ibcon#read 3, iclass 15, count 2 2006.201.07:45:21.43#ibcon#about to read 4, iclass 15, count 2 2006.201.07:45:21.43#ibcon#read 4, iclass 15, count 2 2006.201.07:45:21.43#ibcon#about to read 5, iclass 15, count 2 2006.201.07:45:21.43#ibcon#read 5, iclass 15, count 2 2006.201.07:45:21.43#ibcon#about to read 6, iclass 15, count 2 2006.201.07:45:21.43#ibcon#read 6, iclass 15, count 2 2006.201.07:45:21.43#ibcon#end of sib2, iclass 15, count 2 2006.201.07:45:21.43#ibcon#*after write, iclass 15, count 2 2006.201.07:45:21.43#ibcon#*before return 0, iclass 15, count 2 2006.201.07:45:21.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:21.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:21.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.07:45:21.43#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:21.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:21.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:21.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:21.55#ibcon#enter wrdev, iclass 15, count 0 2006.201.07:45:21.55#ibcon#first serial, iclass 15, count 0 2006.201.07:45:21.55#ibcon#enter sib2, iclass 15, count 0 2006.201.07:45:21.55#ibcon#flushed, iclass 15, count 0 2006.201.07:45:21.55#ibcon#about to write, iclass 15, count 0 2006.201.07:45:21.55#ibcon#wrote, iclass 15, count 0 2006.201.07:45:21.55#ibcon#about to read 3, iclass 15, count 0 2006.201.07:45:21.57#ibcon#read 3, iclass 15, count 0 2006.201.07:45:21.57#ibcon#about to read 4, iclass 15, count 0 2006.201.07:45:21.57#ibcon#read 4, iclass 15, count 0 2006.201.07:45:21.57#ibcon#about to read 5, iclass 15, count 0 2006.201.07:45:21.57#ibcon#read 5, iclass 15, count 0 2006.201.07:45:21.57#ibcon#about to read 6, iclass 15, count 0 2006.201.07:45:21.57#ibcon#read 6, iclass 15, count 0 2006.201.07:45:21.57#ibcon#end of sib2, iclass 15, count 0 2006.201.07:45:21.57#ibcon#*mode == 0, iclass 15, count 0 2006.201.07:45:21.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.07:45:21.57#ibcon#[25=USB\r\n] 2006.201.07:45:21.57#ibcon#*before write, iclass 15, count 0 2006.201.07:45:21.57#ibcon#enter sib2, iclass 15, count 0 2006.201.07:45:21.57#ibcon#flushed, iclass 15, count 0 2006.201.07:45:21.57#ibcon#about to write, iclass 15, count 0 2006.201.07:45:21.57#ibcon#wrote, iclass 15, count 0 2006.201.07:45:21.57#ibcon#about to read 3, iclass 15, count 0 2006.201.07:45:21.60#ibcon#read 3, iclass 15, count 0 2006.201.07:45:21.60#ibcon#about to read 4, iclass 15, count 0 2006.201.07:45:21.60#ibcon#read 4, iclass 15, count 0 2006.201.07:45:21.60#ibcon#about to read 5, iclass 15, count 0 2006.201.07:45:21.60#ibcon#read 5, iclass 15, count 0 2006.201.07:45:21.60#ibcon#about to read 6, iclass 15, count 0 2006.201.07:45:21.60#ibcon#read 6, iclass 15, count 0 2006.201.07:45:21.60#ibcon#end of sib2, iclass 15, count 0 2006.201.07:45:21.60#ibcon#*after write, iclass 15, count 0 2006.201.07:45:21.60#ibcon#*before return 0, iclass 15, count 0 2006.201.07:45:21.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:21.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:21.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.07:45:21.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.07:45:21.60$vck44/valo=6,814.99 2006.201.07:45:21.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.07:45:21.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.07:45:21.60#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:21.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:21.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:21.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:21.60#ibcon#enter wrdev, iclass 17, count 0 2006.201.07:45:21.60#ibcon#first serial, iclass 17, count 0 2006.201.07:45:21.60#ibcon#enter sib2, iclass 17, count 0 2006.201.07:45:21.60#ibcon#flushed, iclass 17, count 0 2006.201.07:45:21.60#ibcon#about to write, iclass 17, count 0 2006.201.07:45:21.60#ibcon#wrote, iclass 17, count 0 2006.201.07:45:21.60#ibcon#about to read 3, iclass 17, count 0 2006.201.07:45:21.62#ibcon#read 3, iclass 17, count 0 2006.201.07:45:21.62#ibcon#about to read 4, iclass 17, count 0 2006.201.07:45:21.62#ibcon#read 4, iclass 17, count 0 2006.201.07:45:21.62#ibcon#about to read 5, iclass 17, count 0 2006.201.07:45:21.62#ibcon#read 5, iclass 17, count 0 2006.201.07:45:21.62#ibcon#about to read 6, iclass 17, count 0 2006.201.07:45:21.62#ibcon#read 6, iclass 17, count 0 2006.201.07:45:21.62#ibcon#end of sib2, iclass 17, count 0 2006.201.07:45:21.62#ibcon#*mode == 0, iclass 17, count 0 2006.201.07:45:21.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.07:45:21.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:45:21.62#ibcon#*before write, iclass 17, count 0 2006.201.07:45:21.62#ibcon#enter sib2, iclass 17, count 0 2006.201.07:45:21.62#ibcon#flushed, iclass 17, count 0 2006.201.07:45:21.62#ibcon#about to write, iclass 17, count 0 2006.201.07:45:21.62#ibcon#wrote, iclass 17, count 0 2006.201.07:45:21.62#ibcon#about to read 3, iclass 17, count 0 2006.201.07:45:21.67#ibcon#read 3, iclass 17, count 0 2006.201.07:45:21.67#ibcon#about to read 4, iclass 17, count 0 2006.201.07:45:21.67#ibcon#read 4, iclass 17, count 0 2006.201.07:45:21.67#ibcon#about to read 5, iclass 17, count 0 2006.201.07:45:21.67#ibcon#read 5, iclass 17, count 0 2006.201.07:45:21.67#ibcon#about to read 6, iclass 17, count 0 2006.201.07:45:21.67#ibcon#read 6, iclass 17, count 0 2006.201.07:45:21.67#ibcon#end of sib2, iclass 17, count 0 2006.201.07:45:21.67#ibcon#*after write, iclass 17, count 0 2006.201.07:45:21.67#ibcon#*before return 0, iclass 17, count 0 2006.201.07:45:21.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:21.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:21.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.07:45:21.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.07:45:21.67$vck44/va=6,5 2006.201.07:45:21.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.07:45:21.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.07:45:21.67#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:21.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:21.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:21.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:21.72#ibcon#enter wrdev, iclass 19, count 2 2006.201.07:45:21.72#ibcon#first serial, iclass 19, count 2 2006.201.07:45:21.72#ibcon#enter sib2, iclass 19, count 2 2006.201.07:45:21.72#ibcon#flushed, iclass 19, count 2 2006.201.07:45:21.72#ibcon#about to write, iclass 19, count 2 2006.201.07:45:21.72#ibcon#wrote, iclass 19, count 2 2006.201.07:45:21.72#ibcon#about to read 3, iclass 19, count 2 2006.201.07:45:21.74#ibcon#read 3, iclass 19, count 2 2006.201.07:45:21.74#ibcon#about to read 4, iclass 19, count 2 2006.201.07:45:21.74#ibcon#read 4, iclass 19, count 2 2006.201.07:45:21.74#ibcon#about to read 5, iclass 19, count 2 2006.201.07:45:21.74#ibcon#read 5, iclass 19, count 2 2006.201.07:45:21.74#ibcon#about to read 6, iclass 19, count 2 2006.201.07:45:21.74#ibcon#read 6, iclass 19, count 2 2006.201.07:45:21.74#ibcon#end of sib2, iclass 19, count 2 2006.201.07:45:21.74#ibcon#*mode == 0, iclass 19, count 2 2006.201.07:45:21.74#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.07:45:21.74#ibcon#[25=AT06-05\r\n] 2006.201.07:45:21.74#ibcon#*before write, iclass 19, count 2 2006.201.07:45:21.74#ibcon#enter sib2, iclass 19, count 2 2006.201.07:45:21.74#ibcon#flushed, iclass 19, count 2 2006.201.07:45:21.74#ibcon#about to write, iclass 19, count 2 2006.201.07:45:21.74#ibcon#wrote, iclass 19, count 2 2006.201.07:45:21.74#ibcon#about to read 3, iclass 19, count 2 2006.201.07:45:21.77#ibcon#read 3, iclass 19, count 2 2006.201.07:45:21.77#ibcon#about to read 4, iclass 19, count 2 2006.201.07:45:21.77#ibcon#read 4, iclass 19, count 2 2006.201.07:45:21.77#ibcon#about to read 5, iclass 19, count 2 2006.201.07:45:21.77#ibcon#read 5, iclass 19, count 2 2006.201.07:45:21.77#ibcon#about to read 6, iclass 19, count 2 2006.201.07:45:21.77#ibcon#read 6, iclass 19, count 2 2006.201.07:45:21.77#ibcon#end of sib2, iclass 19, count 2 2006.201.07:45:21.77#ibcon#*after write, iclass 19, count 2 2006.201.07:45:21.77#ibcon#*before return 0, iclass 19, count 2 2006.201.07:45:21.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:21.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:21.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.07:45:21.77#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:21.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:21.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:21.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:21.89#ibcon#enter wrdev, iclass 19, count 0 2006.201.07:45:21.89#ibcon#first serial, iclass 19, count 0 2006.201.07:45:21.89#ibcon#enter sib2, iclass 19, count 0 2006.201.07:45:21.89#ibcon#flushed, iclass 19, count 0 2006.201.07:45:21.89#ibcon#about to write, iclass 19, count 0 2006.201.07:45:21.89#ibcon#wrote, iclass 19, count 0 2006.201.07:45:21.89#ibcon#about to read 3, iclass 19, count 0 2006.201.07:45:21.91#ibcon#read 3, iclass 19, count 0 2006.201.07:45:21.91#ibcon#about to read 4, iclass 19, count 0 2006.201.07:45:21.91#ibcon#read 4, iclass 19, count 0 2006.201.07:45:21.91#ibcon#about to read 5, iclass 19, count 0 2006.201.07:45:21.91#ibcon#read 5, iclass 19, count 0 2006.201.07:45:21.91#ibcon#about to read 6, iclass 19, count 0 2006.201.07:45:21.91#ibcon#read 6, iclass 19, count 0 2006.201.07:45:21.91#ibcon#end of sib2, iclass 19, count 0 2006.201.07:45:21.91#ibcon#*mode == 0, iclass 19, count 0 2006.201.07:45:21.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.07:45:21.91#ibcon#[25=USB\r\n] 2006.201.07:45:21.91#ibcon#*before write, iclass 19, count 0 2006.201.07:45:21.91#ibcon#enter sib2, iclass 19, count 0 2006.201.07:45:21.91#ibcon#flushed, iclass 19, count 0 2006.201.07:45:21.91#ibcon#about to write, iclass 19, count 0 2006.201.07:45:21.91#ibcon#wrote, iclass 19, count 0 2006.201.07:45:21.91#ibcon#about to read 3, iclass 19, count 0 2006.201.07:45:21.94#ibcon#read 3, iclass 19, count 0 2006.201.07:45:21.94#ibcon#about to read 4, iclass 19, count 0 2006.201.07:45:21.94#ibcon#read 4, iclass 19, count 0 2006.201.07:45:21.94#ibcon#about to read 5, iclass 19, count 0 2006.201.07:45:21.94#ibcon#read 5, iclass 19, count 0 2006.201.07:45:21.94#ibcon#about to read 6, iclass 19, count 0 2006.201.07:45:21.94#ibcon#read 6, iclass 19, count 0 2006.201.07:45:21.94#ibcon#end of sib2, iclass 19, count 0 2006.201.07:45:21.94#ibcon#*after write, iclass 19, count 0 2006.201.07:45:21.94#ibcon#*before return 0, iclass 19, count 0 2006.201.07:45:21.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:21.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:21.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.07:45:21.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.07:45:21.94$vck44/valo=7,864.99 2006.201.07:45:21.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.07:45:21.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.07:45:21.94#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:21.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:45:21.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:45:21.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:45:21.94#ibcon#enter wrdev, iclass 21, count 0 2006.201.07:45:21.94#ibcon#first serial, iclass 21, count 0 2006.201.07:45:21.94#ibcon#enter sib2, iclass 21, count 0 2006.201.07:45:21.94#ibcon#flushed, iclass 21, count 0 2006.201.07:45:21.94#ibcon#about to write, iclass 21, count 0 2006.201.07:45:21.94#ibcon#wrote, iclass 21, count 0 2006.201.07:45:21.94#ibcon#about to read 3, iclass 21, count 0 2006.201.07:45:21.96#ibcon#read 3, iclass 21, count 0 2006.201.07:45:21.96#ibcon#about to read 4, iclass 21, count 0 2006.201.07:45:21.96#ibcon#read 4, iclass 21, count 0 2006.201.07:45:21.96#ibcon#about to read 5, iclass 21, count 0 2006.201.07:45:21.96#ibcon#read 5, iclass 21, count 0 2006.201.07:45:21.96#ibcon#about to read 6, iclass 21, count 0 2006.201.07:45:21.96#ibcon#read 6, iclass 21, count 0 2006.201.07:45:21.96#ibcon#end of sib2, iclass 21, count 0 2006.201.07:45:21.96#ibcon#*mode == 0, iclass 21, count 0 2006.201.07:45:21.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.07:45:21.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:45:21.96#ibcon#*before write, iclass 21, count 0 2006.201.07:45:21.96#ibcon#enter sib2, iclass 21, count 0 2006.201.07:45:21.96#ibcon#flushed, iclass 21, count 0 2006.201.07:45:21.96#ibcon#about to write, iclass 21, count 0 2006.201.07:45:21.96#ibcon#wrote, iclass 21, count 0 2006.201.07:45:21.96#ibcon#about to read 3, iclass 21, count 0 2006.201.07:45:22.00#ibcon#read 3, iclass 21, count 0 2006.201.07:45:22.00#ibcon#about to read 4, iclass 21, count 0 2006.201.07:45:22.00#ibcon#read 4, iclass 21, count 0 2006.201.07:45:22.00#ibcon#about to read 5, iclass 21, count 0 2006.201.07:45:22.00#ibcon#read 5, iclass 21, count 0 2006.201.07:45:22.00#ibcon#about to read 6, iclass 21, count 0 2006.201.07:45:22.00#ibcon#read 6, iclass 21, count 0 2006.201.07:45:22.00#ibcon#end of sib2, iclass 21, count 0 2006.201.07:45:22.00#ibcon#*after write, iclass 21, count 0 2006.201.07:45:22.00#ibcon#*before return 0, iclass 21, count 0 2006.201.07:45:22.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:45:22.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.07:45:22.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.07:45:22.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.07:45:22.00$vck44/va=7,5 2006.201.07:45:22.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.07:45:22.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.07:45:22.00#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:22.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:45:22.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:45:22.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:45:22.06#ibcon#enter wrdev, iclass 23, count 2 2006.201.07:45:22.06#ibcon#first serial, iclass 23, count 2 2006.201.07:45:22.06#ibcon#enter sib2, iclass 23, count 2 2006.201.07:45:22.06#ibcon#flushed, iclass 23, count 2 2006.201.07:45:22.06#ibcon#about to write, iclass 23, count 2 2006.201.07:45:22.06#ibcon#wrote, iclass 23, count 2 2006.201.07:45:22.06#ibcon#about to read 3, iclass 23, count 2 2006.201.07:45:22.08#ibcon#read 3, iclass 23, count 2 2006.201.07:45:22.08#ibcon#about to read 4, iclass 23, count 2 2006.201.07:45:22.08#ibcon#read 4, iclass 23, count 2 2006.201.07:45:22.08#ibcon#about to read 5, iclass 23, count 2 2006.201.07:45:22.08#ibcon#read 5, iclass 23, count 2 2006.201.07:45:22.08#ibcon#about to read 6, iclass 23, count 2 2006.201.07:45:22.08#ibcon#read 6, iclass 23, count 2 2006.201.07:45:22.08#ibcon#end of sib2, iclass 23, count 2 2006.201.07:45:22.08#ibcon#*mode == 0, iclass 23, count 2 2006.201.07:45:22.08#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.07:45:22.08#ibcon#[25=AT07-05\r\n] 2006.201.07:45:22.08#ibcon#*before write, iclass 23, count 2 2006.201.07:45:22.08#ibcon#enter sib2, iclass 23, count 2 2006.201.07:45:22.08#ibcon#flushed, iclass 23, count 2 2006.201.07:45:22.08#ibcon#about to write, iclass 23, count 2 2006.201.07:45:22.08#ibcon#wrote, iclass 23, count 2 2006.201.07:45:22.08#ibcon#about to read 3, iclass 23, count 2 2006.201.07:45:22.11#ibcon#read 3, iclass 23, count 2 2006.201.07:45:22.11#ibcon#about to read 4, iclass 23, count 2 2006.201.07:45:22.11#ibcon#read 4, iclass 23, count 2 2006.201.07:45:22.11#ibcon#about to read 5, iclass 23, count 2 2006.201.07:45:22.11#ibcon#read 5, iclass 23, count 2 2006.201.07:45:22.11#ibcon#about to read 6, iclass 23, count 2 2006.201.07:45:22.11#ibcon#read 6, iclass 23, count 2 2006.201.07:45:22.11#ibcon#end of sib2, iclass 23, count 2 2006.201.07:45:22.11#ibcon#*after write, iclass 23, count 2 2006.201.07:45:22.11#ibcon#*before return 0, iclass 23, count 2 2006.201.07:45:22.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:45:22.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.07:45:22.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.07:45:22.11#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:22.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:45:22.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:45:22.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:45:22.23#ibcon#enter wrdev, iclass 23, count 0 2006.201.07:45:22.23#ibcon#first serial, iclass 23, count 0 2006.201.07:45:22.23#ibcon#enter sib2, iclass 23, count 0 2006.201.07:45:22.23#ibcon#flushed, iclass 23, count 0 2006.201.07:45:22.23#ibcon#about to write, iclass 23, count 0 2006.201.07:45:22.23#ibcon#wrote, iclass 23, count 0 2006.201.07:45:22.23#ibcon#about to read 3, iclass 23, count 0 2006.201.07:45:22.25#ibcon#read 3, iclass 23, count 0 2006.201.07:45:22.25#ibcon#about to read 4, iclass 23, count 0 2006.201.07:45:22.25#ibcon#read 4, iclass 23, count 0 2006.201.07:45:22.25#ibcon#about to read 5, iclass 23, count 0 2006.201.07:45:22.25#ibcon#read 5, iclass 23, count 0 2006.201.07:45:22.25#ibcon#about to read 6, iclass 23, count 0 2006.201.07:45:22.25#ibcon#read 6, iclass 23, count 0 2006.201.07:45:22.25#ibcon#end of sib2, iclass 23, count 0 2006.201.07:45:22.25#ibcon#*mode == 0, iclass 23, count 0 2006.201.07:45:22.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.07:45:22.25#ibcon#[25=USB\r\n] 2006.201.07:45:22.25#ibcon#*before write, iclass 23, count 0 2006.201.07:45:22.25#ibcon#enter sib2, iclass 23, count 0 2006.201.07:45:22.25#ibcon#flushed, iclass 23, count 0 2006.201.07:45:22.25#ibcon#about to write, iclass 23, count 0 2006.201.07:45:22.25#ibcon#wrote, iclass 23, count 0 2006.201.07:45:22.25#ibcon#about to read 3, iclass 23, count 0 2006.201.07:45:22.28#ibcon#read 3, iclass 23, count 0 2006.201.07:45:22.28#ibcon#about to read 4, iclass 23, count 0 2006.201.07:45:22.28#ibcon#read 4, iclass 23, count 0 2006.201.07:45:22.28#ibcon#about to read 5, iclass 23, count 0 2006.201.07:45:22.28#ibcon#read 5, iclass 23, count 0 2006.201.07:45:22.28#ibcon#about to read 6, iclass 23, count 0 2006.201.07:45:22.28#ibcon#read 6, iclass 23, count 0 2006.201.07:45:22.28#ibcon#end of sib2, iclass 23, count 0 2006.201.07:45:22.28#ibcon#*after write, iclass 23, count 0 2006.201.07:45:22.28#ibcon#*before return 0, iclass 23, count 0 2006.201.07:45:22.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:45:22.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.07:45:22.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.07:45:22.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.07:45:22.28$vck44/valo=8,884.99 2006.201.07:45:22.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.07:45:22.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.07:45:22.28#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:22.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:22.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:22.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:22.28#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:45:22.28#ibcon#first serial, iclass 25, count 0 2006.201.07:45:22.28#ibcon#enter sib2, iclass 25, count 0 2006.201.07:45:22.28#ibcon#flushed, iclass 25, count 0 2006.201.07:45:22.28#ibcon#about to write, iclass 25, count 0 2006.201.07:45:22.28#ibcon#wrote, iclass 25, count 0 2006.201.07:45:22.28#ibcon#about to read 3, iclass 25, count 0 2006.201.07:45:22.30#ibcon#read 3, iclass 25, count 0 2006.201.07:45:22.30#ibcon#about to read 4, iclass 25, count 0 2006.201.07:45:22.30#ibcon#read 4, iclass 25, count 0 2006.201.07:45:22.30#ibcon#about to read 5, iclass 25, count 0 2006.201.07:45:22.30#ibcon#read 5, iclass 25, count 0 2006.201.07:45:22.30#ibcon#about to read 6, iclass 25, count 0 2006.201.07:45:22.30#ibcon#read 6, iclass 25, count 0 2006.201.07:45:22.30#ibcon#end of sib2, iclass 25, count 0 2006.201.07:45:22.30#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:45:22.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:45:22.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:45:22.30#ibcon#*before write, iclass 25, count 0 2006.201.07:45:22.30#ibcon#enter sib2, iclass 25, count 0 2006.201.07:45:22.30#ibcon#flushed, iclass 25, count 0 2006.201.07:45:22.30#ibcon#about to write, iclass 25, count 0 2006.201.07:45:22.30#ibcon#wrote, iclass 25, count 0 2006.201.07:45:22.30#ibcon#about to read 3, iclass 25, count 0 2006.201.07:45:22.34#ibcon#read 3, iclass 25, count 0 2006.201.07:45:22.34#ibcon#about to read 4, iclass 25, count 0 2006.201.07:45:22.34#ibcon#read 4, iclass 25, count 0 2006.201.07:45:22.34#ibcon#about to read 5, iclass 25, count 0 2006.201.07:45:22.34#ibcon#read 5, iclass 25, count 0 2006.201.07:45:22.34#ibcon#about to read 6, iclass 25, count 0 2006.201.07:45:22.34#ibcon#read 6, iclass 25, count 0 2006.201.07:45:22.34#ibcon#end of sib2, iclass 25, count 0 2006.201.07:45:22.34#ibcon#*after write, iclass 25, count 0 2006.201.07:45:22.34#ibcon#*before return 0, iclass 25, count 0 2006.201.07:45:22.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:22.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:22.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:45:22.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:45:22.34$vck44/va=8,4 2006.201.07:45:22.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.07:45:22.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.07:45:22.34#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:22.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:22.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:22.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:22.40#ibcon#enter wrdev, iclass 27, count 2 2006.201.07:45:22.40#ibcon#first serial, iclass 27, count 2 2006.201.07:45:22.40#ibcon#enter sib2, iclass 27, count 2 2006.201.07:45:22.40#ibcon#flushed, iclass 27, count 2 2006.201.07:45:22.40#ibcon#about to write, iclass 27, count 2 2006.201.07:45:22.40#ibcon#wrote, iclass 27, count 2 2006.201.07:45:22.40#ibcon#about to read 3, iclass 27, count 2 2006.201.07:45:22.42#ibcon#read 3, iclass 27, count 2 2006.201.07:45:22.42#ibcon#about to read 4, iclass 27, count 2 2006.201.07:45:22.42#ibcon#read 4, iclass 27, count 2 2006.201.07:45:22.42#ibcon#about to read 5, iclass 27, count 2 2006.201.07:45:22.42#ibcon#read 5, iclass 27, count 2 2006.201.07:45:22.42#ibcon#about to read 6, iclass 27, count 2 2006.201.07:45:22.42#ibcon#read 6, iclass 27, count 2 2006.201.07:45:22.42#ibcon#end of sib2, iclass 27, count 2 2006.201.07:45:22.42#ibcon#*mode == 0, iclass 27, count 2 2006.201.07:45:22.42#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.07:45:22.42#ibcon#[25=AT08-04\r\n] 2006.201.07:45:22.42#ibcon#*before write, iclass 27, count 2 2006.201.07:45:22.42#ibcon#enter sib2, iclass 27, count 2 2006.201.07:45:22.42#ibcon#flushed, iclass 27, count 2 2006.201.07:45:22.42#ibcon#about to write, iclass 27, count 2 2006.201.07:45:22.42#ibcon#wrote, iclass 27, count 2 2006.201.07:45:22.42#ibcon#about to read 3, iclass 27, count 2 2006.201.07:45:22.45#ibcon#read 3, iclass 27, count 2 2006.201.07:45:22.45#ibcon#about to read 4, iclass 27, count 2 2006.201.07:45:22.45#ibcon#read 4, iclass 27, count 2 2006.201.07:45:22.45#ibcon#about to read 5, iclass 27, count 2 2006.201.07:45:22.45#ibcon#read 5, iclass 27, count 2 2006.201.07:45:22.45#ibcon#about to read 6, iclass 27, count 2 2006.201.07:45:22.45#ibcon#read 6, iclass 27, count 2 2006.201.07:45:22.45#ibcon#end of sib2, iclass 27, count 2 2006.201.07:45:22.45#ibcon#*after write, iclass 27, count 2 2006.201.07:45:22.45#ibcon#*before return 0, iclass 27, count 2 2006.201.07:45:22.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:22.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:22.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.07:45:22.45#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:22.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:22.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:22.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:22.57#ibcon#enter wrdev, iclass 27, count 0 2006.201.07:45:22.57#ibcon#first serial, iclass 27, count 0 2006.201.07:45:22.57#ibcon#enter sib2, iclass 27, count 0 2006.201.07:45:22.57#ibcon#flushed, iclass 27, count 0 2006.201.07:45:22.57#ibcon#about to write, iclass 27, count 0 2006.201.07:45:22.57#ibcon#wrote, iclass 27, count 0 2006.201.07:45:22.57#ibcon#about to read 3, iclass 27, count 0 2006.201.07:45:22.59#ibcon#read 3, iclass 27, count 0 2006.201.07:45:22.59#ibcon#about to read 4, iclass 27, count 0 2006.201.07:45:22.59#ibcon#read 4, iclass 27, count 0 2006.201.07:45:22.59#ibcon#about to read 5, iclass 27, count 0 2006.201.07:45:22.59#ibcon#read 5, iclass 27, count 0 2006.201.07:45:22.59#ibcon#about to read 6, iclass 27, count 0 2006.201.07:45:22.59#ibcon#read 6, iclass 27, count 0 2006.201.07:45:22.59#ibcon#end of sib2, iclass 27, count 0 2006.201.07:45:22.59#ibcon#*mode == 0, iclass 27, count 0 2006.201.07:45:22.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.07:45:22.59#ibcon#[25=USB\r\n] 2006.201.07:45:22.59#ibcon#*before write, iclass 27, count 0 2006.201.07:45:22.59#ibcon#enter sib2, iclass 27, count 0 2006.201.07:45:22.59#ibcon#flushed, iclass 27, count 0 2006.201.07:45:22.59#ibcon#about to write, iclass 27, count 0 2006.201.07:45:22.59#ibcon#wrote, iclass 27, count 0 2006.201.07:45:22.59#ibcon#about to read 3, iclass 27, count 0 2006.201.07:45:22.62#ibcon#read 3, iclass 27, count 0 2006.201.07:45:22.62#ibcon#about to read 4, iclass 27, count 0 2006.201.07:45:22.62#ibcon#read 4, iclass 27, count 0 2006.201.07:45:22.62#ibcon#about to read 5, iclass 27, count 0 2006.201.07:45:22.62#ibcon#read 5, iclass 27, count 0 2006.201.07:45:22.62#ibcon#about to read 6, iclass 27, count 0 2006.201.07:45:22.62#ibcon#read 6, iclass 27, count 0 2006.201.07:45:22.62#ibcon#end of sib2, iclass 27, count 0 2006.201.07:45:22.62#ibcon#*after write, iclass 27, count 0 2006.201.07:45:22.62#ibcon#*before return 0, iclass 27, count 0 2006.201.07:45:22.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:22.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:22.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.07:45:22.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.07:45:22.62$vck44/vblo=1,629.99 2006.201.07:45:22.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.07:45:22.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.07:45:22.62#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:22.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:22.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:22.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:22.62#ibcon#enter wrdev, iclass 29, count 0 2006.201.07:45:22.62#ibcon#first serial, iclass 29, count 0 2006.201.07:45:22.62#ibcon#enter sib2, iclass 29, count 0 2006.201.07:45:22.62#ibcon#flushed, iclass 29, count 0 2006.201.07:45:22.62#ibcon#about to write, iclass 29, count 0 2006.201.07:45:22.62#ibcon#wrote, iclass 29, count 0 2006.201.07:45:22.62#ibcon#about to read 3, iclass 29, count 0 2006.201.07:45:22.64#ibcon#read 3, iclass 29, count 0 2006.201.07:45:22.64#ibcon#about to read 4, iclass 29, count 0 2006.201.07:45:22.64#ibcon#read 4, iclass 29, count 0 2006.201.07:45:22.64#ibcon#about to read 5, iclass 29, count 0 2006.201.07:45:22.64#ibcon#read 5, iclass 29, count 0 2006.201.07:45:22.64#ibcon#about to read 6, iclass 29, count 0 2006.201.07:45:22.64#ibcon#read 6, iclass 29, count 0 2006.201.07:45:22.64#ibcon#end of sib2, iclass 29, count 0 2006.201.07:45:22.64#ibcon#*mode == 0, iclass 29, count 0 2006.201.07:45:22.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.07:45:22.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:45:22.64#ibcon#*before write, iclass 29, count 0 2006.201.07:45:22.64#ibcon#enter sib2, iclass 29, count 0 2006.201.07:45:22.64#ibcon#flushed, iclass 29, count 0 2006.201.07:45:22.64#ibcon#about to write, iclass 29, count 0 2006.201.07:45:22.64#ibcon#wrote, iclass 29, count 0 2006.201.07:45:22.64#ibcon#about to read 3, iclass 29, count 0 2006.201.07:45:22.68#ibcon#read 3, iclass 29, count 0 2006.201.07:45:22.68#ibcon#about to read 4, iclass 29, count 0 2006.201.07:45:22.68#ibcon#read 4, iclass 29, count 0 2006.201.07:45:22.68#ibcon#about to read 5, iclass 29, count 0 2006.201.07:45:22.68#ibcon#read 5, iclass 29, count 0 2006.201.07:45:22.68#ibcon#about to read 6, iclass 29, count 0 2006.201.07:45:22.68#ibcon#read 6, iclass 29, count 0 2006.201.07:45:22.68#ibcon#end of sib2, iclass 29, count 0 2006.201.07:45:22.68#ibcon#*after write, iclass 29, count 0 2006.201.07:45:22.68#ibcon#*before return 0, iclass 29, count 0 2006.201.07:45:22.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:22.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:22.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.07:45:22.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.07:45:22.68$vck44/vb=1,4 2006.201.07:45:22.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.07:45:22.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.07:45:22.68#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:22.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:45:22.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:45:22.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:45:22.68#ibcon#enter wrdev, iclass 31, count 2 2006.201.07:45:22.68#ibcon#first serial, iclass 31, count 2 2006.201.07:45:22.68#ibcon#enter sib2, iclass 31, count 2 2006.201.07:45:22.68#ibcon#flushed, iclass 31, count 2 2006.201.07:45:22.68#ibcon#about to write, iclass 31, count 2 2006.201.07:45:22.68#ibcon#wrote, iclass 31, count 2 2006.201.07:45:22.68#ibcon#about to read 3, iclass 31, count 2 2006.201.07:45:22.70#ibcon#read 3, iclass 31, count 2 2006.201.07:45:22.70#ibcon#about to read 4, iclass 31, count 2 2006.201.07:45:22.70#ibcon#read 4, iclass 31, count 2 2006.201.07:45:22.70#ibcon#about to read 5, iclass 31, count 2 2006.201.07:45:22.70#ibcon#read 5, iclass 31, count 2 2006.201.07:45:22.70#ibcon#about to read 6, iclass 31, count 2 2006.201.07:45:22.70#ibcon#read 6, iclass 31, count 2 2006.201.07:45:22.70#ibcon#end of sib2, iclass 31, count 2 2006.201.07:45:22.70#ibcon#*mode == 0, iclass 31, count 2 2006.201.07:45:22.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.07:45:22.70#ibcon#[27=AT01-04\r\n] 2006.201.07:45:22.70#ibcon#*before write, iclass 31, count 2 2006.201.07:45:22.70#ibcon#enter sib2, iclass 31, count 2 2006.201.07:45:22.70#ibcon#flushed, iclass 31, count 2 2006.201.07:45:22.70#ibcon#about to write, iclass 31, count 2 2006.201.07:45:22.70#ibcon#wrote, iclass 31, count 2 2006.201.07:45:22.70#ibcon#about to read 3, iclass 31, count 2 2006.201.07:45:22.73#ibcon#read 3, iclass 31, count 2 2006.201.07:45:22.73#ibcon#about to read 4, iclass 31, count 2 2006.201.07:45:22.73#ibcon#read 4, iclass 31, count 2 2006.201.07:45:22.73#ibcon#about to read 5, iclass 31, count 2 2006.201.07:45:22.73#ibcon#read 5, iclass 31, count 2 2006.201.07:45:22.73#ibcon#about to read 6, iclass 31, count 2 2006.201.07:45:22.73#ibcon#read 6, iclass 31, count 2 2006.201.07:45:22.73#ibcon#end of sib2, iclass 31, count 2 2006.201.07:45:22.73#ibcon#*after write, iclass 31, count 2 2006.201.07:45:22.73#ibcon#*before return 0, iclass 31, count 2 2006.201.07:45:22.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:45:22.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.07:45:22.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.07:45:22.73#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:22.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:45:22.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:45:22.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:45:22.85#ibcon#enter wrdev, iclass 31, count 0 2006.201.07:45:22.85#ibcon#first serial, iclass 31, count 0 2006.201.07:45:22.85#ibcon#enter sib2, iclass 31, count 0 2006.201.07:45:22.85#ibcon#flushed, iclass 31, count 0 2006.201.07:45:22.85#ibcon#about to write, iclass 31, count 0 2006.201.07:45:22.85#ibcon#wrote, iclass 31, count 0 2006.201.07:45:22.85#ibcon#about to read 3, iclass 31, count 0 2006.201.07:45:22.87#ibcon#read 3, iclass 31, count 0 2006.201.07:45:22.87#ibcon#about to read 4, iclass 31, count 0 2006.201.07:45:22.87#ibcon#read 4, iclass 31, count 0 2006.201.07:45:22.87#ibcon#about to read 5, iclass 31, count 0 2006.201.07:45:22.87#ibcon#read 5, iclass 31, count 0 2006.201.07:45:22.87#ibcon#about to read 6, iclass 31, count 0 2006.201.07:45:22.87#ibcon#read 6, iclass 31, count 0 2006.201.07:45:22.87#ibcon#end of sib2, iclass 31, count 0 2006.201.07:45:22.87#ibcon#*mode == 0, iclass 31, count 0 2006.201.07:45:22.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.07:45:22.87#ibcon#[27=USB\r\n] 2006.201.07:45:22.87#ibcon#*before write, iclass 31, count 0 2006.201.07:45:22.87#ibcon#enter sib2, iclass 31, count 0 2006.201.07:45:22.87#ibcon#flushed, iclass 31, count 0 2006.201.07:45:22.87#ibcon#about to write, iclass 31, count 0 2006.201.07:45:22.87#ibcon#wrote, iclass 31, count 0 2006.201.07:45:22.87#ibcon#about to read 3, iclass 31, count 0 2006.201.07:45:22.90#ibcon#read 3, iclass 31, count 0 2006.201.07:45:22.90#ibcon#about to read 4, iclass 31, count 0 2006.201.07:45:22.90#ibcon#read 4, iclass 31, count 0 2006.201.07:45:22.90#ibcon#about to read 5, iclass 31, count 0 2006.201.07:45:22.90#ibcon#read 5, iclass 31, count 0 2006.201.07:45:22.90#ibcon#about to read 6, iclass 31, count 0 2006.201.07:45:22.90#ibcon#read 6, iclass 31, count 0 2006.201.07:45:22.90#ibcon#end of sib2, iclass 31, count 0 2006.201.07:45:22.90#ibcon#*after write, iclass 31, count 0 2006.201.07:45:22.90#ibcon#*before return 0, iclass 31, count 0 2006.201.07:45:22.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:45:22.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.07:45:22.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.07:45:22.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.07:45:22.90$vck44/vblo=2,634.99 2006.201.07:45:22.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.07:45:22.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.07:45:22.90#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:22.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:22.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:22.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:22.90#ibcon#enter wrdev, iclass 33, count 0 2006.201.07:45:22.90#ibcon#first serial, iclass 33, count 0 2006.201.07:45:22.90#ibcon#enter sib2, iclass 33, count 0 2006.201.07:45:22.90#ibcon#flushed, iclass 33, count 0 2006.201.07:45:22.90#ibcon#about to write, iclass 33, count 0 2006.201.07:45:22.90#ibcon#wrote, iclass 33, count 0 2006.201.07:45:22.90#ibcon#about to read 3, iclass 33, count 0 2006.201.07:45:22.92#ibcon#read 3, iclass 33, count 0 2006.201.07:45:22.92#ibcon#about to read 4, iclass 33, count 0 2006.201.07:45:22.92#ibcon#read 4, iclass 33, count 0 2006.201.07:45:22.92#ibcon#about to read 5, iclass 33, count 0 2006.201.07:45:22.92#ibcon#read 5, iclass 33, count 0 2006.201.07:45:22.92#ibcon#about to read 6, iclass 33, count 0 2006.201.07:45:22.92#ibcon#read 6, iclass 33, count 0 2006.201.07:45:22.92#ibcon#end of sib2, iclass 33, count 0 2006.201.07:45:22.92#ibcon#*mode == 0, iclass 33, count 0 2006.201.07:45:22.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.07:45:22.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:45:22.92#ibcon#*before write, iclass 33, count 0 2006.201.07:45:22.92#ibcon#enter sib2, iclass 33, count 0 2006.201.07:45:22.92#ibcon#flushed, iclass 33, count 0 2006.201.07:45:22.92#ibcon#about to write, iclass 33, count 0 2006.201.07:45:22.92#ibcon#wrote, iclass 33, count 0 2006.201.07:45:22.92#ibcon#about to read 3, iclass 33, count 0 2006.201.07:45:22.96#ibcon#read 3, iclass 33, count 0 2006.201.07:45:22.96#ibcon#about to read 4, iclass 33, count 0 2006.201.07:45:22.96#ibcon#read 4, iclass 33, count 0 2006.201.07:45:22.96#ibcon#about to read 5, iclass 33, count 0 2006.201.07:45:22.96#ibcon#read 5, iclass 33, count 0 2006.201.07:45:22.96#ibcon#about to read 6, iclass 33, count 0 2006.201.07:45:22.96#ibcon#read 6, iclass 33, count 0 2006.201.07:45:22.96#ibcon#end of sib2, iclass 33, count 0 2006.201.07:45:22.96#ibcon#*after write, iclass 33, count 0 2006.201.07:45:22.96#ibcon#*before return 0, iclass 33, count 0 2006.201.07:45:22.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:22.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.07:45:22.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.07:45:22.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.07:45:22.96$vck44/vb=2,5 2006.201.07:45:22.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.07:45:22.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.07:45:22.96#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:22.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:23.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:23.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:23.02#ibcon#enter wrdev, iclass 35, count 2 2006.201.07:45:23.02#ibcon#first serial, iclass 35, count 2 2006.201.07:45:23.02#ibcon#enter sib2, iclass 35, count 2 2006.201.07:45:23.02#ibcon#flushed, iclass 35, count 2 2006.201.07:45:23.02#ibcon#about to write, iclass 35, count 2 2006.201.07:45:23.02#ibcon#wrote, iclass 35, count 2 2006.201.07:45:23.02#ibcon#about to read 3, iclass 35, count 2 2006.201.07:45:23.04#ibcon#read 3, iclass 35, count 2 2006.201.07:45:23.04#ibcon#about to read 4, iclass 35, count 2 2006.201.07:45:23.04#ibcon#read 4, iclass 35, count 2 2006.201.07:45:23.04#ibcon#about to read 5, iclass 35, count 2 2006.201.07:45:23.04#ibcon#read 5, iclass 35, count 2 2006.201.07:45:23.04#ibcon#about to read 6, iclass 35, count 2 2006.201.07:45:23.04#ibcon#read 6, iclass 35, count 2 2006.201.07:45:23.04#ibcon#end of sib2, iclass 35, count 2 2006.201.07:45:23.04#ibcon#*mode == 0, iclass 35, count 2 2006.201.07:45:23.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.07:45:23.04#ibcon#[27=AT02-05\r\n] 2006.201.07:45:23.04#ibcon#*before write, iclass 35, count 2 2006.201.07:45:23.04#ibcon#enter sib2, iclass 35, count 2 2006.201.07:45:23.04#ibcon#flushed, iclass 35, count 2 2006.201.07:45:23.04#ibcon#about to write, iclass 35, count 2 2006.201.07:45:23.04#ibcon#wrote, iclass 35, count 2 2006.201.07:45:23.04#ibcon#about to read 3, iclass 35, count 2 2006.201.07:45:23.07#ibcon#read 3, iclass 35, count 2 2006.201.07:45:23.07#ibcon#about to read 4, iclass 35, count 2 2006.201.07:45:23.07#ibcon#read 4, iclass 35, count 2 2006.201.07:45:23.07#ibcon#about to read 5, iclass 35, count 2 2006.201.07:45:23.07#ibcon#read 5, iclass 35, count 2 2006.201.07:45:23.07#ibcon#about to read 6, iclass 35, count 2 2006.201.07:45:23.07#ibcon#read 6, iclass 35, count 2 2006.201.07:45:23.07#ibcon#end of sib2, iclass 35, count 2 2006.201.07:45:23.07#ibcon#*after write, iclass 35, count 2 2006.201.07:45:23.07#ibcon#*before return 0, iclass 35, count 2 2006.201.07:45:23.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:23.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.07:45:23.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.07:45:23.07#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:23.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:23.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:23.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:23.19#ibcon#enter wrdev, iclass 35, count 0 2006.201.07:45:23.19#ibcon#first serial, iclass 35, count 0 2006.201.07:45:23.19#ibcon#enter sib2, iclass 35, count 0 2006.201.07:45:23.19#ibcon#flushed, iclass 35, count 0 2006.201.07:45:23.19#ibcon#about to write, iclass 35, count 0 2006.201.07:45:23.19#ibcon#wrote, iclass 35, count 0 2006.201.07:45:23.19#ibcon#about to read 3, iclass 35, count 0 2006.201.07:45:23.21#ibcon#read 3, iclass 35, count 0 2006.201.07:45:23.21#ibcon#about to read 4, iclass 35, count 0 2006.201.07:45:23.21#ibcon#read 4, iclass 35, count 0 2006.201.07:45:23.21#ibcon#about to read 5, iclass 35, count 0 2006.201.07:45:23.21#ibcon#read 5, iclass 35, count 0 2006.201.07:45:23.21#ibcon#about to read 6, iclass 35, count 0 2006.201.07:45:23.21#ibcon#read 6, iclass 35, count 0 2006.201.07:45:23.21#ibcon#end of sib2, iclass 35, count 0 2006.201.07:45:23.21#ibcon#*mode == 0, iclass 35, count 0 2006.201.07:45:23.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.07:45:23.21#ibcon#[27=USB\r\n] 2006.201.07:45:23.21#ibcon#*before write, iclass 35, count 0 2006.201.07:45:23.21#ibcon#enter sib2, iclass 35, count 0 2006.201.07:45:23.21#ibcon#flushed, iclass 35, count 0 2006.201.07:45:23.21#ibcon#about to write, iclass 35, count 0 2006.201.07:45:23.21#ibcon#wrote, iclass 35, count 0 2006.201.07:45:23.21#ibcon#about to read 3, iclass 35, count 0 2006.201.07:45:23.24#ibcon#read 3, iclass 35, count 0 2006.201.07:45:23.24#ibcon#about to read 4, iclass 35, count 0 2006.201.07:45:23.24#ibcon#read 4, iclass 35, count 0 2006.201.07:45:23.24#ibcon#about to read 5, iclass 35, count 0 2006.201.07:45:23.24#ibcon#read 5, iclass 35, count 0 2006.201.07:45:23.24#ibcon#about to read 6, iclass 35, count 0 2006.201.07:45:23.24#ibcon#read 6, iclass 35, count 0 2006.201.07:45:23.24#ibcon#end of sib2, iclass 35, count 0 2006.201.07:45:23.24#ibcon#*after write, iclass 35, count 0 2006.201.07:45:23.24#ibcon#*before return 0, iclass 35, count 0 2006.201.07:45:23.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:23.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.07:45:23.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.07:45:23.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.07:45:23.24$vck44/vblo=3,649.99 2006.201.07:45:23.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.07:45:23.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.07:45:23.24#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:23.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:23.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:23.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:23.24#ibcon#enter wrdev, iclass 37, count 0 2006.201.07:45:23.24#ibcon#first serial, iclass 37, count 0 2006.201.07:45:23.24#ibcon#enter sib2, iclass 37, count 0 2006.201.07:45:23.24#ibcon#flushed, iclass 37, count 0 2006.201.07:45:23.24#ibcon#about to write, iclass 37, count 0 2006.201.07:45:23.24#ibcon#wrote, iclass 37, count 0 2006.201.07:45:23.24#ibcon#about to read 3, iclass 37, count 0 2006.201.07:45:23.26#ibcon#read 3, iclass 37, count 0 2006.201.07:45:23.26#ibcon#about to read 4, iclass 37, count 0 2006.201.07:45:23.26#ibcon#read 4, iclass 37, count 0 2006.201.07:45:23.26#ibcon#about to read 5, iclass 37, count 0 2006.201.07:45:23.26#ibcon#read 5, iclass 37, count 0 2006.201.07:45:23.26#ibcon#about to read 6, iclass 37, count 0 2006.201.07:45:23.26#ibcon#read 6, iclass 37, count 0 2006.201.07:45:23.26#ibcon#end of sib2, iclass 37, count 0 2006.201.07:45:23.26#ibcon#*mode == 0, iclass 37, count 0 2006.201.07:45:23.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.07:45:23.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:45:23.26#ibcon#*before write, iclass 37, count 0 2006.201.07:45:23.26#ibcon#enter sib2, iclass 37, count 0 2006.201.07:45:23.26#ibcon#flushed, iclass 37, count 0 2006.201.07:45:23.26#ibcon#about to write, iclass 37, count 0 2006.201.07:45:23.26#ibcon#wrote, iclass 37, count 0 2006.201.07:45:23.26#ibcon#about to read 3, iclass 37, count 0 2006.201.07:45:23.31#ibcon#read 3, iclass 37, count 0 2006.201.07:45:23.31#ibcon#about to read 4, iclass 37, count 0 2006.201.07:45:23.31#ibcon#read 4, iclass 37, count 0 2006.201.07:45:23.31#ibcon#about to read 5, iclass 37, count 0 2006.201.07:45:23.31#ibcon#read 5, iclass 37, count 0 2006.201.07:45:23.31#ibcon#about to read 6, iclass 37, count 0 2006.201.07:45:23.31#ibcon#read 6, iclass 37, count 0 2006.201.07:45:23.31#ibcon#end of sib2, iclass 37, count 0 2006.201.07:45:23.31#ibcon#*after write, iclass 37, count 0 2006.201.07:45:23.31#ibcon#*before return 0, iclass 37, count 0 2006.201.07:45:23.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:23.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.07:45:23.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.07:45:23.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.07:45:23.31$vck44/vb=3,4 2006.201.07:45:23.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.07:45:23.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.07:45:23.31#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:23.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:23.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:23.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:23.36#ibcon#enter wrdev, iclass 39, count 2 2006.201.07:45:23.36#ibcon#first serial, iclass 39, count 2 2006.201.07:45:23.36#ibcon#enter sib2, iclass 39, count 2 2006.201.07:45:23.36#ibcon#flushed, iclass 39, count 2 2006.201.07:45:23.36#ibcon#about to write, iclass 39, count 2 2006.201.07:45:23.36#ibcon#wrote, iclass 39, count 2 2006.201.07:45:23.36#ibcon#about to read 3, iclass 39, count 2 2006.201.07:45:23.38#ibcon#read 3, iclass 39, count 2 2006.201.07:45:23.38#ibcon#about to read 4, iclass 39, count 2 2006.201.07:45:23.38#ibcon#read 4, iclass 39, count 2 2006.201.07:45:23.38#ibcon#about to read 5, iclass 39, count 2 2006.201.07:45:23.38#ibcon#read 5, iclass 39, count 2 2006.201.07:45:23.38#ibcon#about to read 6, iclass 39, count 2 2006.201.07:45:23.38#ibcon#read 6, iclass 39, count 2 2006.201.07:45:23.38#ibcon#end of sib2, iclass 39, count 2 2006.201.07:45:23.38#ibcon#*mode == 0, iclass 39, count 2 2006.201.07:45:23.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.07:45:23.38#ibcon#[27=AT03-04\r\n] 2006.201.07:45:23.38#ibcon#*before write, iclass 39, count 2 2006.201.07:45:23.38#ibcon#enter sib2, iclass 39, count 2 2006.201.07:45:23.38#ibcon#flushed, iclass 39, count 2 2006.201.07:45:23.38#ibcon#about to write, iclass 39, count 2 2006.201.07:45:23.38#ibcon#wrote, iclass 39, count 2 2006.201.07:45:23.38#ibcon#about to read 3, iclass 39, count 2 2006.201.07:45:23.41#ibcon#read 3, iclass 39, count 2 2006.201.07:45:23.41#ibcon#about to read 4, iclass 39, count 2 2006.201.07:45:23.41#ibcon#read 4, iclass 39, count 2 2006.201.07:45:23.41#ibcon#about to read 5, iclass 39, count 2 2006.201.07:45:23.41#ibcon#read 5, iclass 39, count 2 2006.201.07:45:23.41#ibcon#about to read 6, iclass 39, count 2 2006.201.07:45:23.41#ibcon#read 6, iclass 39, count 2 2006.201.07:45:23.41#ibcon#end of sib2, iclass 39, count 2 2006.201.07:45:23.41#ibcon#*after write, iclass 39, count 2 2006.201.07:45:23.41#ibcon#*before return 0, iclass 39, count 2 2006.201.07:45:23.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:23.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.07:45:23.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.07:45:23.41#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:23.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:23.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:23.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:23.53#ibcon#enter wrdev, iclass 39, count 0 2006.201.07:45:23.53#ibcon#first serial, iclass 39, count 0 2006.201.07:45:23.53#ibcon#enter sib2, iclass 39, count 0 2006.201.07:45:23.53#ibcon#flushed, iclass 39, count 0 2006.201.07:45:23.53#ibcon#about to write, iclass 39, count 0 2006.201.07:45:23.53#ibcon#wrote, iclass 39, count 0 2006.201.07:45:23.53#ibcon#about to read 3, iclass 39, count 0 2006.201.07:45:23.55#ibcon#read 3, iclass 39, count 0 2006.201.07:45:23.55#ibcon#about to read 4, iclass 39, count 0 2006.201.07:45:23.55#ibcon#read 4, iclass 39, count 0 2006.201.07:45:23.55#ibcon#about to read 5, iclass 39, count 0 2006.201.07:45:23.55#ibcon#read 5, iclass 39, count 0 2006.201.07:45:23.55#ibcon#about to read 6, iclass 39, count 0 2006.201.07:45:23.55#ibcon#read 6, iclass 39, count 0 2006.201.07:45:23.55#ibcon#end of sib2, iclass 39, count 0 2006.201.07:45:23.55#ibcon#*mode == 0, iclass 39, count 0 2006.201.07:45:23.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.07:45:23.55#ibcon#[27=USB\r\n] 2006.201.07:45:23.55#ibcon#*before write, iclass 39, count 0 2006.201.07:45:23.55#ibcon#enter sib2, iclass 39, count 0 2006.201.07:45:23.55#ibcon#flushed, iclass 39, count 0 2006.201.07:45:23.55#ibcon#about to write, iclass 39, count 0 2006.201.07:45:23.55#ibcon#wrote, iclass 39, count 0 2006.201.07:45:23.55#ibcon#about to read 3, iclass 39, count 0 2006.201.07:45:23.58#ibcon#read 3, iclass 39, count 0 2006.201.07:45:23.58#ibcon#about to read 4, iclass 39, count 0 2006.201.07:45:23.58#ibcon#read 4, iclass 39, count 0 2006.201.07:45:23.58#ibcon#about to read 5, iclass 39, count 0 2006.201.07:45:23.58#ibcon#read 5, iclass 39, count 0 2006.201.07:45:23.58#ibcon#about to read 6, iclass 39, count 0 2006.201.07:45:23.58#ibcon#read 6, iclass 39, count 0 2006.201.07:45:23.58#ibcon#end of sib2, iclass 39, count 0 2006.201.07:45:23.58#ibcon#*after write, iclass 39, count 0 2006.201.07:45:23.58#ibcon#*before return 0, iclass 39, count 0 2006.201.07:45:23.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:23.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.07:45:23.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.07:45:23.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.07:45:23.58$vck44/vblo=4,679.99 2006.201.07:45:23.58#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.07:45:23.58#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.07:45:23.58#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:23.58#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:23.58#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:23.58#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:23.58#ibcon#enter wrdev, iclass 2, count 0 2006.201.07:45:23.58#ibcon#first serial, iclass 2, count 0 2006.201.07:45:23.58#ibcon#enter sib2, iclass 2, count 0 2006.201.07:45:23.58#ibcon#flushed, iclass 2, count 0 2006.201.07:45:23.58#ibcon#about to write, iclass 2, count 0 2006.201.07:45:23.58#ibcon#wrote, iclass 2, count 0 2006.201.07:45:23.58#ibcon#about to read 3, iclass 2, count 0 2006.201.07:45:23.60#ibcon#read 3, iclass 2, count 0 2006.201.07:45:23.60#ibcon#about to read 4, iclass 2, count 0 2006.201.07:45:23.60#ibcon#read 4, iclass 2, count 0 2006.201.07:45:23.60#ibcon#about to read 5, iclass 2, count 0 2006.201.07:45:23.60#ibcon#read 5, iclass 2, count 0 2006.201.07:45:23.60#ibcon#about to read 6, iclass 2, count 0 2006.201.07:45:23.60#ibcon#read 6, iclass 2, count 0 2006.201.07:45:23.60#ibcon#end of sib2, iclass 2, count 0 2006.201.07:45:23.60#ibcon#*mode == 0, iclass 2, count 0 2006.201.07:45:23.60#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.07:45:23.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:45:23.60#ibcon#*before write, iclass 2, count 0 2006.201.07:45:23.60#ibcon#enter sib2, iclass 2, count 0 2006.201.07:45:23.60#ibcon#flushed, iclass 2, count 0 2006.201.07:45:23.60#ibcon#about to write, iclass 2, count 0 2006.201.07:45:23.60#ibcon#wrote, iclass 2, count 0 2006.201.07:45:23.60#ibcon#about to read 3, iclass 2, count 0 2006.201.07:45:23.64#ibcon#read 3, iclass 2, count 0 2006.201.07:45:23.64#ibcon#about to read 4, iclass 2, count 0 2006.201.07:45:23.64#ibcon#read 4, iclass 2, count 0 2006.201.07:45:23.64#ibcon#about to read 5, iclass 2, count 0 2006.201.07:45:23.64#ibcon#read 5, iclass 2, count 0 2006.201.07:45:23.64#ibcon#about to read 6, iclass 2, count 0 2006.201.07:45:23.64#ibcon#read 6, iclass 2, count 0 2006.201.07:45:23.64#ibcon#end of sib2, iclass 2, count 0 2006.201.07:45:23.64#ibcon#*after write, iclass 2, count 0 2006.201.07:45:23.64#ibcon#*before return 0, iclass 2, count 0 2006.201.07:45:23.64#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:23.64#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.07:45:23.64#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.07:45:23.64#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.07:45:23.64$vck44/vb=4,5 2006.201.07:45:23.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.07:45:23.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.07:45:23.64#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:23.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:23.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:23.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:23.70#ibcon#enter wrdev, iclass 5, count 2 2006.201.07:45:23.70#ibcon#first serial, iclass 5, count 2 2006.201.07:45:23.70#ibcon#enter sib2, iclass 5, count 2 2006.201.07:45:23.70#ibcon#flushed, iclass 5, count 2 2006.201.07:45:23.70#ibcon#about to write, iclass 5, count 2 2006.201.07:45:23.70#ibcon#wrote, iclass 5, count 2 2006.201.07:45:23.70#ibcon#about to read 3, iclass 5, count 2 2006.201.07:45:23.72#ibcon#read 3, iclass 5, count 2 2006.201.07:45:23.72#ibcon#about to read 4, iclass 5, count 2 2006.201.07:45:23.72#ibcon#read 4, iclass 5, count 2 2006.201.07:45:23.72#ibcon#about to read 5, iclass 5, count 2 2006.201.07:45:23.72#ibcon#read 5, iclass 5, count 2 2006.201.07:45:23.72#ibcon#about to read 6, iclass 5, count 2 2006.201.07:45:23.72#ibcon#read 6, iclass 5, count 2 2006.201.07:45:23.72#ibcon#end of sib2, iclass 5, count 2 2006.201.07:45:23.72#ibcon#*mode == 0, iclass 5, count 2 2006.201.07:45:23.72#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.07:45:23.72#ibcon#[27=AT04-05\r\n] 2006.201.07:45:23.72#ibcon#*before write, iclass 5, count 2 2006.201.07:45:23.72#ibcon#enter sib2, iclass 5, count 2 2006.201.07:45:23.72#ibcon#flushed, iclass 5, count 2 2006.201.07:45:23.72#ibcon#about to write, iclass 5, count 2 2006.201.07:45:23.72#ibcon#wrote, iclass 5, count 2 2006.201.07:45:23.72#ibcon#about to read 3, iclass 5, count 2 2006.201.07:45:23.75#ibcon#read 3, iclass 5, count 2 2006.201.07:45:23.75#ibcon#about to read 4, iclass 5, count 2 2006.201.07:45:23.75#ibcon#read 4, iclass 5, count 2 2006.201.07:45:23.75#ibcon#about to read 5, iclass 5, count 2 2006.201.07:45:23.75#ibcon#read 5, iclass 5, count 2 2006.201.07:45:23.75#ibcon#about to read 6, iclass 5, count 2 2006.201.07:45:23.75#ibcon#read 6, iclass 5, count 2 2006.201.07:45:23.75#ibcon#end of sib2, iclass 5, count 2 2006.201.07:45:23.75#ibcon#*after write, iclass 5, count 2 2006.201.07:45:23.75#ibcon#*before return 0, iclass 5, count 2 2006.201.07:45:23.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:23.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.07:45:23.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.07:45:23.75#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:23.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:23.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:23.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:23.87#ibcon#enter wrdev, iclass 5, count 0 2006.201.07:45:23.87#ibcon#first serial, iclass 5, count 0 2006.201.07:45:23.87#ibcon#enter sib2, iclass 5, count 0 2006.201.07:45:23.87#ibcon#flushed, iclass 5, count 0 2006.201.07:45:23.87#ibcon#about to write, iclass 5, count 0 2006.201.07:45:23.87#ibcon#wrote, iclass 5, count 0 2006.201.07:45:23.87#ibcon#about to read 3, iclass 5, count 0 2006.201.07:45:23.89#ibcon#read 3, iclass 5, count 0 2006.201.07:45:23.89#ibcon#about to read 4, iclass 5, count 0 2006.201.07:45:23.89#ibcon#read 4, iclass 5, count 0 2006.201.07:45:23.89#ibcon#about to read 5, iclass 5, count 0 2006.201.07:45:23.89#ibcon#read 5, iclass 5, count 0 2006.201.07:45:23.89#ibcon#about to read 6, iclass 5, count 0 2006.201.07:45:23.89#ibcon#read 6, iclass 5, count 0 2006.201.07:45:23.89#ibcon#end of sib2, iclass 5, count 0 2006.201.07:45:23.89#ibcon#*mode == 0, iclass 5, count 0 2006.201.07:45:23.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.07:45:23.89#ibcon#[27=USB\r\n] 2006.201.07:45:23.89#ibcon#*before write, iclass 5, count 0 2006.201.07:45:23.89#ibcon#enter sib2, iclass 5, count 0 2006.201.07:45:23.89#ibcon#flushed, iclass 5, count 0 2006.201.07:45:23.89#ibcon#about to write, iclass 5, count 0 2006.201.07:45:23.89#ibcon#wrote, iclass 5, count 0 2006.201.07:45:23.89#ibcon#about to read 3, iclass 5, count 0 2006.201.07:45:23.92#ibcon#read 3, iclass 5, count 0 2006.201.07:45:23.92#ibcon#about to read 4, iclass 5, count 0 2006.201.07:45:23.92#ibcon#read 4, iclass 5, count 0 2006.201.07:45:23.92#ibcon#about to read 5, iclass 5, count 0 2006.201.07:45:23.92#ibcon#read 5, iclass 5, count 0 2006.201.07:45:23.92#ibcon#about to read 6, iclass 5, count 0 2006.201.07:45:23.92#ibcon#read 6, iclass 5, count 0 2006.201.07:45:23.92#ibcon#end of sib2, iclass 5, count 0 2006.201.07:45:23.92#ibcon#*after write, iclass 5, count 0 2006.201.07:45:23.92#ibcon#*before return 0, iclass 5, count 0 2006.201.07:45:23.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:23.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.07:45:23.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.07:45:23.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.07:45:23.92$vck44/vblo=5,709.99 2006.201.07:45:23.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.07:45:23.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.07:45:23.92#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:23.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:23.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:23.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:23.92#ibcon#enter wrdev, iclass 7, count 0 2006.201.07:45:23.92#ibcon#first serial, iclass 7, count 0 2006.201.07:45:23.92#ibcon#enter sib2, iclass 7, count 0 2006.201.07:45:23.92#ibcon#flushed, iclass 7, count 0 2006.201.07:45:23.92#ibcon#about to write, iclass 7, count 0 2006.201.07:45:23.92#ibcon#wrote, iclass 7, count 0 2006.201.07:45:23.92#ibcon#about to read 3, iclass 7, count 0 2006.201.07:45:23.94#ibcon#read 3, iclass 7, count 0 2006.201.07:45:23.94#ibcon#about to read 4, iclass 7, count 0 2006.201.07:45:23.94#ibcon#read 4, iclass 7, count 0 2006.201.07:45:23.94#ibcon#about to read 5, iclass 7, count 0 2006.201.07:45:23.94#ibcon#read 5, iclass 7, count 0 2006.201.07:45:23.94#ibcon#about to read 6, iclass 7, count 0 2006.201.07:45:23.94#ibcon#read 6, iclass 7, count 0 2006.201.07:45:23.94#ibcon#end of sib2, iclass 7, count 0 2006.201.07:45:23.94#ibcon#*mode == 0, iclass 7, count 0 2006.201.07:45:23.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.07:45:23.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:45:23.94#ibcon#*before write, iclass 7, count 0 2006.201.07:45:23.94#ibcon#enter sib2, iclass 7, count 0 2006.201.07:45:23.94#ibcon#flushed, iclass 7, count 0 2006.201.07:45:23.94#ibcon#about to write, iclass 7, count 0 2006.201.07:45:23.94#ibcon#wrote, iclass 7, count 0 2006.201.07:45:23.94#ibcon#about to read 3, iclass 7, count 0 2006.201.07:45:23.98#ibcon#read 3, iclass 7, count 0 2006.201.07:45:23.98#ibcon#about to read 4, iclass 7, count 0 2006.201.07:45:23.98#ibcon#read 4, iclass 7, count 0 2006.201.07:45:23.98#ibcon#about to read 5, iclass 7, count 0 2006.201.07:45:23.98#ibcon#read 5, iclass 7, count 0 2006.201.07:45:23.98#ibcon#about to read 6, iclass 7, count 0 2006.201.07:45:23.98#ibcon#read 6, iclass 7, count 0 2006.201.07:45:23.98#ibcon#end of sib2, iclass 7, count 0 2006.201.07:45:23.98#ibcon#*after write, iclass 7, count 0 2006.201.07:45:23.98#ibcon#*before return 0, iclass 7, count 0 2006.201.07:45:23.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:23.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.07:45:23.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.07:45:23.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.07:45:23.98$vck44/vb=5,4 2006.201.07:45:23.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.07:45:23.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.07:45:23.98#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:23.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:24.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:24.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:24.04#ibcon#enter wrdev, iclass 11, count 2 2006.201.07:45:24.04#ibcon#first serial, iclass 11, count 2 2006.201.07:45:24.04#ibcon#enter sib2, iclass 11, count 2 2006.201.07:45:24.04#ibcon#flushed, iclass 11, count 2 2006.201.07:45:24.04#ibcon#about to write, iclass 11, count 2 2006.201.07:45:24.04#ibcon#wrote, iclass 11, count 2 2006.201.07:45:24.04#ibcon#about to read 3, iclass 11, count 2 2006.201.07:45:24.06#ibcon#read 3, iclass 11, count 2 2006.201.07:45:24.06#ibcon#about to read 4, iclass 11, count 2 2006.201.07:45:24.06#ibcon#read 4, iclass 11, count 2 2006.201.07:45:24.06#ibcon#about to read 5, iclass 11, count 2 2006.201.07:45:24.06#ibcon#read 5, iclass 11, count 2 2006.201.07:45:24.06#ibcon#about to read 6, iclass 11, count 2 2006.201.07:45:24.06#ibcon#read 6, iclass 11, count 2 2006.201.07:45:24.06#ibcon#end of sib2, iclass 11, count 2 2006.201.07:45:24.06#ibcon#*mode == 0, iclass 11, count 2 2006.201.07:45:24.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.07:45:24.06#ibcon#[27=AT05-04\r\n] 2006.201.07:45:24.06#ibcon#*before write, iclass 11, count 2 2006.201.07:45:24.06#ibcon#enter sib2, iclass 11, count 2 2006.201.07:45:24.06#ibcon#flushed, iclass 11, count 2 2006.201.07:45:24.06#ibcon#about to write, iclass 11, count 2 2006.201.07:45:24.06#ibcon#wrote, iclass 11, count 2 2006.201.07:45:24.06#ibcon#about to read 3, iclass 11, count 2 2006.201.07:45:24.09#ibcon#read 3, iclass 11, count 2 2006.201.07:45:24.09#ibcon#about to read 4, iclass 11, count 2 2006.201.07:45:24.09#ibcon#read 4, iclass 11, count 2 2006.201.07:45:24.09#ibcon#about to read 5, iclass 11, count 2 2006.201.07:45:24.09#ibcon#read 5, iclass 11, count 2 2006.201.07:45:24.09#ibcon#about to read 6, iclass 11, count 2 2006.201.07:45:24.09#ibcon#read 6, iclass 11, count 2 2006.201.07:45:24.09#ibcon#end of sib2, iclass 11, count 2 2006.201.07:45:24.09#ibcon#*after write, iclass 11, count 2 2006.201.07:45:24.09#ibcon#*before return 0, iclass 11, count 2 2006.201.07:45:24.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:24.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.07:45:24.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.07:45:24.09#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:24.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:24.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:24.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:24.21#ibcon#enter wrdev, iclass 11, count 0 2006.201.07:45:24.21#ibcon#first serial, iclass 11, count 0 2006.201.07:45:24.21#ibcon#enter sib2, iclass 11, count 0 2006.201.07:45:24.21#ibcon#flushed, iclass 11, count 0 2006.201.07:45:24.21#ibcon#about to write, iclass 11, count 0 2006.201.07:45:24.21#ibcon#wrote, iclass 11, count 0 2006.201.07:45:24.21#ibcon#about to read 3, iclass 11, count 0 2006.201.07:45:24.23#ibcon#read 3, iclass 11, count 0 2006.201.07:45:24.23#ibcon#about to read 4, iclass 11, count 0 2006.201.07:45:24.23#ibcon#read 4, iclass 11, count 0 2006.201.07:45:24.23#ibcon#about to read 5, iclass 11, count 0 2006.201.07:45:24.23#ibcon#read 5, iclass 11, count 0 2006.201.07:45:24.23#ibcon#about to read 6, iclass 11, count 0 2006.201.07:45:24.23#ibcon#read 6, iclass 11, count 0 2006.201.07:45:24.23#ibcon#end of sib2, iclass 11, count 0 2006.201.07:45:24.23#ibcon#*mode == 0, iclass 11, count 0 2006.201.07:45:24.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.07:45:24.23#ibcon#[27=USB\r\n] 2006.201.07:45:24.23#ibcon#*before write, iclass 11, count 0 2006.201.07:45:24.23#ibcon#enter sib2, iclass 11, count 0 2006.201.07:45:24.23#ibcon#flushed, iclass 11, count 0 2006.201.07:45:24.23#ibcon#about to write, iclass 11, count 0 2006.201.07:45:24.23#ibcon#wrote, iclass 11, count 0 2006.201.07:45:24.23#ibcon#about to read 3, iclass 11, count 0 2006.201.07:45:24.26#ibcon#read 3, iclass 11, count 0 2006.201.07:45:24.26#ibcon#about to read 4, iclass 11, count 0 2006.201.07:45:24.26#ibcon#read 4, iclass 11, count 0 2006.201.07:45:24.26#ibcon#about to read 5, iclass 11, count 0 2006.201.07:45:24.26#ibcon#read 5, iclass 11, count 0 2006.201.07:45:24.26#ibcon#about to read 6, iclass 11, count 0 2006.201.07:45:24.26#ibcon#read 6, iclass 11, count 0 2006.201.07:45:24.26#ibcon#end of sib2, iclass 11, count 0 2006.201.07:45:24.26#ibcon#*after write, iclass 11, count 0 2006.201.07:45:24.26#ibcon#*before return 0, iclass 11, count 0 2006.201.07:45:24.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:24.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.07:45:24.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.07:45:24.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.07:45:24.26$vck44/vblo=6,719.99 2006.201.07:45:24.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.07:45:24.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.07:45:24.26#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:24.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:24.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:24.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:24.26#ibcon#enter wrdev, iclass 13, count 0 2006.201.07:45:24.26#ibcon#first serial, iclass 13, count 0 2006.201.07:45:24.26#ibcon#enter sib2, iclass 13, count 0 2006.201.07:45:24.26#ibcon#flushed, iclass 13, count 0 2006.201.07:45:24.26#ibcon#about to write, iclass 13, count 0 2006.201.07:45:24.26#ibcon#wrote, iclass 13, count 0 2006.201.07:45:24.26#ibcon#about to read 3, iclass 13, count 0 2006.201.07:45:24.28#ibcon#read 3, iclass 13, count 0 2006.201.07:45:24.28#ibcon#about to read 4, iclass 13, count 0 2006.201.07:45:24.28#ibcon#read 4, iclass 13, count 0 2006.201.07:45:24.28#ibcon#about to read 5, iclass 13, count 0 2006.201.07:45:24.28#ibcon#read 5, iclass 13, count 0 2006.201.07:45:24.28#ibcon#about to read 6, iclass 13, count 0 2006.201.07:45:24.28#ibcon#read 6, iclass 13, count 0 2006.201.07:45:24.28#ibcon#end of sib2, iclass 13, count 0 2006.201.07:45:24.28#ibcon#*mode == 0, iclass 13, count 0 2006.201.07:45:24.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.07:45:24.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:45:24.28#ibcon#*before write, iclass 13, count 0 2006.201.07:45:24.28#ibcon#enter sib2, iclass 13, count 0 2006.201.07:45:24.28#ibcon#flushed, iclass 13, count 0 2006.201.07:45:24.28#ibcon#about to write, iclass 13, count 0 2006.201.07:45:24.28#ibcon#wrote, iclass 13, count 0 2006.201.07:45:24.28#ibcon#about to read 3, iclass 13, count 0 2006.201.07:45:24.32#ibcon#read 3, iclass 13, count 0 2006.201.07:45:24.32#ibcon#about to read 4, iclass 13, count 0 2006.201.07:45:24.32#ibcon#read 4, iclass 13, count 0 2006.201.07:45:24.32#ibcon#about to read 5, iclass 13, count 0 2006.201.07:45:24.32#ibcon#read 5, iclass 13, count 0 2006.201.07:45:24.32#ibcon#about to read 6, iclass 13, count 0 2006.201.07:45:24.32#ibcon#read 6, iclass 13, count 0 2006.201.07:45:24.32#ibcon#end of sib2, iclass 13, count 0 2006.201.07:45:24.32#ibcon#*after write, iclass 13, count 0 2006.201.07:45:24.32#ibcon#*before return 0, iclass 13, count 0 2006.201.07:45:24.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:24.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.07:45:24.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.07:45:24.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.07:45:24.32$vck44/vb=6,4 2006.201.07:45:24.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.07:45:24.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.07:45:24.32#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:24.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:24.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:24.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:24.38#ibcon#enter wrdev, iclass 15, count 2 2006.201.07:45:24.38#ibcon#first serial, iclass 15, count 2 2006.201.07:45:24.38#ibcon#enter sib2, iclass 15, count 2 2006.201.07:45:24.38#ibcon#flushed, iclass 15, count 2 2006.201.07:45:24.38#ibcon#about to write, iclass 15, count 2 2006.201.07:45:24.38#ibcon#wrote, iclass 15, count 2 2006.201.07:45:24.38#ibcon#about to read 3, iclass 15, count 2 2006.201.07:45:24.40#ibcon#read 3, iclass 15, count 2 2006.201.07:45:24.40#ibcon#about to read 4, iclass 15, count 2 2006.201.07:45:24.40#ibcon#read 4, iclass 15, count 2 2006.201.07:45:24.40#ibcon#about to read 5, iclass 15, count 2 2006.201.07:45:24.40#ibcon#read 5, iclass 15, count 2 2006.201.07:45:24.40#ibcon#about to read 6, iclass 15, count 2 2006.201.07:45:24.40#ibcon#read 6, iclass 15, count 2 2006.201.07:45:24.40#ibcon#end of sib2, iclass 15, count 2 2006.201.07:45:24.40#ibcon#*mode == 0, iclass 15, count 2 2006.201.07:45:24.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.07:45:24.40#ibcon#[27=AT06-04\r\n] 2006.201.07:45:24.40#ibcon#*before write, iclass 15, count 2 2006.201.07:45:24.40#ibcon#enter sib2, iclass 15, count 2 2006.201.07:45:24.40#ibcon#flushed, iclass 15, count 2 2006.201.07:45:24.40#ibcon#about to write, iclass 15, count 2 2006.201.07:45:24.40#ibcon#wrote, iclass 15, count 2 2006.201.07:45:24.40#ibcon#about to read 3, iclass 15, count 2 2006.201.07:45:24.43#ibcon#read 3, iclass 15, count 2 2006.201.07:45:24.43#ibcon#about to read 4, iclass 15, count 2 2006.201.07:45:24.43#ibcon#read 4, iclass 15, count 2 2006.201.07:45:24.43#ibcon#about to read 5, iclass 15, count 2 2006.201.07:45:24.43#ibcon#read 5, iclass 15, count 2 2006.201.07:45:24.43#ibcon#about to read 6, iclass 15, count 2 2006.201.07:45:24.43#ibcon#read 6, iclass 15, count 2 2006.201.07:45:24.43#ibcon#end of sib2, iclass 15, count 2 2006.201.07:45:24.43#ibcon#*after write, iclass 15, count 2 2006.201.07:45:24.43#ibcon#*before return 0, iclass 15, count 2 2006.201.07:45:24.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:24.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.07:45:24.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.07:45:24.43#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:24.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:24.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:24.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:24.55#ibcon#enter wrdev, iclass 15, count 0 2006.201.07:45:24.55#ibcon#first serial, iclass 15, count 0 2006.201.07:45:24.55#ibcon#enter sib2, iclass 15, count 0 2006.201.07:45:24.55#ibcon#flushed, iclass 15, count 0 2006.201.07:45:24.55#ibcon#about to write, iclass 15, count 0 2006.201.07:45:24.55#ibcon#wrote, iclass 15, count 0 2006.201.07:45:24.55#ibcon#about to read 3, iclass 15, count 0 2006.201.07:45:24.57#ibcon#read 3, iclass 15, count 0 2006.201.07:45:24.57#ibcon#about to read 4, iclass 15, count 0 2006.201.07:45:24.57#ibcon#read 4, iclass 15, count 0 2006.201.07:45:24.57#ibcon#about to read 5, iclass 15, count 0 2006.201.07:45:24.57#ibcon#read 5, iclass 15, count 0 2006.201.07:45:24.57#ibcon#about to read 6, iclass 15, count 0 2006.201.07:45:24.57#ibcon#read 6, iclass 15, count 0 2006.201.07:45:24.57#ibcon#end of sib2, iclass 15, count 0 2006.201.07:45:24.57#ibcon#*mode == 0, iclass 15, count 0 2006.201.07:45:24.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.07:45:24.57#ibcon#[27=USB\r\n] 2006.201.07:45:24.57#ibcon#*before write, iclass 15, count 0 2006.201.07:45:24.57#ibcon#enter sib2, iclass 15, count 0 2006.201.07:45:24.57#ibcon#flushed, iclass 15, count 0 2006.201.07:45:24.57#ibcon#about to write, iclass 15, count 0 2006.201.07:45:24.57#ibcon#wrote, iclass 15, count 0 2006.201.07:45:24.57#ibcon#about to read 3, iclass 15, count 0 2006.201.07:45:24.60#ibcon#read 3, iclass 15, count 0 2006.201.07:45:24.60#ibcon#about to read 4, iclass 15, count 0 2006.201.07:45:24.60#ibcon#read 4, iclass 15, count 0 2006.201.07:45:24.60#ibcon#about to read 5, iclass 15, count 0 2006.201.07:45:24.60#ibcon#read 5, iclass 15, count 0 2006.201.07:45:24.60#ibcon#about to read 6, iclass 15, count 0 2006.201.07:45:24.60#ibcon#read 6, iclass 15, count 0 2006.201.07:45:24.60#ibcon#end of sib2, iclass 15, count 0 2006.201.07:45:24.60#ibcon#*after write, iclass 15, count 0 2006.201.07:45:24.60#ibcon#*before return 0, iclass 15, count 0 2006.201.07:45:24.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:24.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.07:45:24.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.07:45:24.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.07:45:24.60$vck44/vblo=7,734.99 2006.201.07:45:24.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.07:45:24.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.07:45:24.60#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:24.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:24.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:24.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:24.60#ibcon#enter wrdev, iclass 17, count 0 2006.201.07:45:24.60#ibcon#first serial, iclass 17, count 0 2006.201.07:45:24.60#ibcon#enter sib2, iclass 17, count 0 2006.201.07:45:24.60#ibcon#flushed, iclass 17, count 0 2006.201.07:45:24.60#ibcon#about to write, iclass 17, count 0 2006.201.07:45:24.60#ibcon#wrote, iclass 17, count 0 2006.201.07:45:24.60#ibcon#about to read 3, iclass 17, count 0 2006.201.07:45:24.62#ibcon#read 3, iclass 17, count 0 2006.201.07:45:24.62#ibcon#about to read 4, iclass 17, count 0 2006.201.07:45:24.62#ibcon#read 4, iclass 17, count 0 2006.201.07:45:24.62#ibcon#about to read 5, iclass 17, count 0 2006.201.07:45:24.62#ibcon#read 5, iclass 17, count 0 2006.201.07:45:24.62#ibcon#about to read 6, iclass 17, count 0 2006.201.07:45:24.62#ibcon#read 6, iclass 17, count 0 2006.201.07:45:24.62#ibcon#end of sib2, iclass 17, count 0 2006.201.07:45:24.62#ibcon#*mode == 0, iclass 17, count 0 2006.201.07:45:24.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.07:45:24.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:45:24.62#ibcon#*before write, iclass 17, count 0 2006.201.07:45:24.62#ibcon#enter sib2, iclass 17, count 0 2006.201.07:45:24.62#ibcon#flushed, iclass 17, count 0 2006.201.07:45:24.62#ibcon#about to write, iclass 17, count 0 2006.201.07:45:24.62#ibcon#wrote, iclass 17, count 0 2006.201.07:45:24.62#ibcon#about to read 3, iclass 17, count 0 2006.201.07:45:24.66#ibcon#read 3, iclass 17, count 0 2006.201.07:45:24.66#ibcon#about to read 4, iclass 17, count 0 2006.201.07:45:24.66#ibcon#read 4, iclass 17, count 0 2006.201.07:45:24.66#ibcon#about to read 5, iclass 17, count 0 2006.201.07:45:24.66#ibcon#read 5, iclass 17, count 0 2006.201.07:45:24.66#ibcon#about to read 6, iclass 17, count 0 2006.201.07:45:24.66#ibcon#read 6, iclass 17, count 0 2006.201.07:45:24.66#ibcon#end of sib2, iclass 17, count 0 2006.201.07:45:24.66#ibcon#*after write, iclass 17, count 0 2006.201.07:45:24.66#ibcon#*before return 0, iclass 17, count 0 2006.201.07:45:24.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:24.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.07:45:24.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.07:45:24.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.07:45:24.66$vck44/vb=7,4 2006.201.07:45:24.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.07:45:24.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.07:45:24.66#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:24.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:24.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:24.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:24.72#ibcon#enter wrdev, iclass 19, count 2 2006.201.07:45:24.72#ibcon#first serial, iclass 19, count 2 2006.201.07:45:24.72#ibcon#enter sib2, iclass 19, count 2 2006.201.07:45:24.72#ibcon#flushed, iclass 19, count 2 2006.201.07:45:24.72#ibcon#about to write, iclass 19, count 2 2006.201.07:45:24.72#ibcon#wrote, iclass 19, count 2 2006.201.07:45:24.72#ibcon#about to read 3, iclass 19, count 2 2006.201.07:45:24.74#ibcon#read 3, iclass 19, count 2 2006.201.07:45:24.74#ibcon#about to read 4, iclass 19, count 2 2006.201.07:45:24.74#ibcon#read 4, iclass 19, count 2 2006.201.07:45:24.74#ibcon#about to read 5, iclass 19, count 2 2006.201.07:45:24.74#ibcon#read 5, iclass 19, count 2 2006.201.07:45:24.74#ibcon#about to read 6, iclass 19, count 2 2006.201.07:45:24.74#ibcon#read 6, iclass 19, count 2 2006.201.07:45:24.74#ibcon#end of sib2, iclass 19, count 2 2006.201.07:45:24.74#ibcon#*mode == 0, iclass 19, count 2 2006.201.07:45:24.74#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.07:45:24.74#ibcon#[27=AT07-04\r\n] 2006.201.07:45:24.74#ibcon#*before write, iclass 19, count 2 2006.201.07:45:24.74#ibcon#enter sib2, iclass 19, count 2 2006.201.07:45:24.74#ibcon#flushed, iclass 19, count 2 2006.201.07:45:24.74#ibcon#about to write, iclass 19, count 2 2006.201.07:45:24.74#ibcon#wrote, iclass 19, count 2 2006.201.07:45:24.74#ibcon#about to read 3, iclass 19, count 2 2006.201.07:45:24.75#abcon#<5=/04 2.4 5.1 23.31 891003.0\r\n> 2006.201.07:45:24.77#abcon#{5=INTERFACE CLEAR} 2006.201.07:45:24.77#ibcon#read 3, iclass 19, count 2 2006.201.07:45:24.77#ibcon#about to read 4, iclass 19, count 2 2006.201.07:45:24.77#ibcon#read 4, iclass 19, count 2 2006.201.07:45:24.77#ibcon#about to read 5, iclass 19, count 2 2006.201.07:45:24.77#ibcon#read 5, iclass 19, count 2 2006.201.07:45:24.77#ibcon#about to read 6, iclass 19, count 2 2006.201.07:45:24.77#ibcon#read 6, iclass 19, count 2 2006.201.07:45:24.77#ibcon#end of sib2, iclass 19, count 2 2006.201.07:45:24.77#ibcon#*after write, iclass 19, count 2 2006.201.07:45:24.77#ibcon#*before return 0, iclass 19, count 2 2006.201.07:45:24.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:24.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.07:45:24.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.07:45:24.77#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:24.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:24.83#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:45:24.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:24.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:24.89#ibcon#enter wrdev, iclass 19, count 0 2006.201.07:45:24.89#ibcon#first serial, iclass 19, count 0 2006.201.07:45:24.89#ibcon#enter sib2, iclass 19, count 0 2006.201.07:45:24.89#ibcon#flushed, iclass 19, count 0 2006.201.07:45:24.89#ibcon#about to write, iclass 19, count 0 2006.201.07:45:24.89#ibcon#wrote, iclass 19, count 0 2006.201.07:45:24.89#ibcon#about to read 3, iclass 19, count 0 2006.201.07:45:24.91#ibcon#read 3, iclass 19, count 0 2006.201.07:45:24.91#ibcon#about to read 4, iclass 19, count 0 2006.201.07:45:24.91#ibcon#read 4, iclass 19, count 0 2006.201.07:45:24.91#ibcon#about to read 5, iclass 19, count 0 2006.201.07:45:24.91#ibcon#read 5, iclass 19, count 0 2006.201.07:45:24.91#ibcon#about to read 6, iclass 19, count 0 2006.201.07:45:24.91#ibcon#read 6, iclass 19, count 0 2006.201.07:45:24.91#ibcon#end of sib2, iclass 19, count 0 2006.201.07:45:24.91#ibcon#*mode == 0, iclass 19, count 0 2006.201.07:45:24.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.07:45:24.91#ibcon#[27=USB\r\n] 2006.201.07:45:24.91#ibcon#*before write, iclass 19, count 0 2006.201.07:45:24.91#ibcon#enter sib2, iclass 19, count 0 2006.201.07:45:24.91#ibcon#flushed, iclass 19, count 0 2006.201.07:45:24.91#ibcon#about to write, iclass 19, count 0 2006.201.07:45:24.91#ibcon#wrote, iclass 19, count 0 2006.201.07:45:24.91#ibcon#about to read 3, iclass 19, count 0 2006.201.07:45:24.94#ibcon#read 3, iclass 19, count 0 2006.201.07:45:24.94#ibcon#about to read 4, iclass 19, count 0 2006.201.07:45:24.94#ibcon#read 4, iclass 19, count 0 2006.201.07:45:24.94#ibcon#about to read 5, iclass 19, count 0 2006.201.07:45:24.94#ibcon#read 5, iclass 19, count 0 2006.201.07:45:24.94#ibcon#about to read 6, iclass 19, count 0 2006.201.07:45:24.94#ibcon#read 6, iclass 19, count 0 2006.201.07:45:24.94#ibcon#end of sib2, iclass 19, count 0 2006.201.07:45:24.94#ibcon#*after write, iclass 19, count 0 2006.201.07:45:24.94#ibcon#*before return 0, iclass 19, count 0 2006.201.07:45:24.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:24.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.07:45:24.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.07:45:24.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.07:45:24.94$vck44/vblo=8,744.99 2006.201.07:45:24.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.07:45:24.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.07:45:24.94#ibcon#ireg 17 cls_cnt 0 2006.201.07:45:24.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:24.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:24.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:24.94#ibcon#enter wrdev, iclass 25, count 0 2006.201.07:45:24.94#ibcon#first serial, iclass 25, count 0 2006.201.07:45:24.94#ibcon#enter sib2, iclass 25, count 0 2006.201.07:45:24.94#ibcon#flushed, iclass 25, count 0 2006.201.07:45:24.94#ibcon#about to write, iclass 25, count 0 2006.201.07:45:24.94#ibcon#wrote, iclass 25, count 0 2006.201.07:45:24.94#ibcon#about to read 3, iclass 25, count 0 2006.201.07:45:24.96#ibcon#read 3, iclass 25, count 0 2006.201.07:45:24.96#ibcon#about to read 4, iclass 25, count 0 2006.201.07:45:24.96#ibcon#read 4, iclass 25, count 0 2006.201.07:45:24.96#ibcon#about to read 5, iclass 25, count 0 2006.201.07:45:24.96#ibcon#read 5, iclass 25, count 0 2006.201.07:45:24.96#ibcon#about to read 6, iclass 25, count 0 2006.201.07:45:24.96#ibcon#read 6, iclass 25, count 0 2006.201.07:45:24.96#ibcon#end of sib2, iclass 25, count 0 2006.201.07:45:24.96#ibcon#*mode == 0, iclass 25, count 0 2006.201.07:45:24.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.07:45:24.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:45:24.96#ibcon#*before write, iclass 25, count 0 2006.201.07:45:24.96#ibcon#enter sib2, iclass 25, count 0 2006.201.07:45:24.96#ibcon#flushed, iclass 25, count 0 2006.201.07:45:24.96#ibcon#about to write, iclass 25, count 0 2006.201.07:45:24.96#ibcon#wrote, iclass 25, count 0 2006.201.07:45:24.96#ibcon#about to read 3, iclass 25, count 0 2006.201.07:45:25.00#ibcon#read 3, iclass 25, count 0 2006.201.07:45:25.00#ibcon#about to read 4, iclass 25, count 0 2006.201.07:45:25.00#ibcon#read 4, iclass 25, count 0 2006.201.07:45:25.00#ibcon#about to read 5, iclass 25, count 0 2006.201.07:45:25.00#ibcon#read 5, iclass 25, count 0 2006.201.07:45:25.00#ibcon#about to read 6, iclass 25, count 0 2006.201.07:45:25.00#ibcon#read 6, iclass 25, count 0 2006.201.07:45:25.00#ibcon#end of sib2, iclass 25, count 0 2006.201.07:45:25.00#ibcon#*after write, iclass 25, count 0 2006.201.07:45:25.00#ibcon#*before return 0, iclass 25, count 0 2006.201.07:45:25.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:25.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.07:45:25.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.07:45:25.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.07:45:25.00$vck44/vb=8,4 2006.201.07:45:25.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.07:45:25.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.07:45:25.00#ibcon#ireg 11 cls_cnt 2 2006.201.07:45:25.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:25.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:25.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:25.06#ibcon#enter wrdev, iclass 27, count 2 2006.201.07:45:25.06#ibcon#first serial, iclass 27, count 2 2006.201.07:45:25.06#ibcon#enter sib2, iclass 27, count 2 2006.201.07:45:25.06#ibcon#flushed, iclass 27, count 2 2006.201.07:45:25.06#ibcon#about to write, iclass 27, count 2 2006.201.07:45:25.06#ibcon#wrote, iclass 27, count 2 2006.201.07:45:25.06#ibcon#about to read 3, iclass 27, count 2 2006.201.07:45:25.08#ibcon#read 3, iclass 27, count 2 2006.201.07:45:25.08#ibcon#about to read 4, iclass 27, count 2 2006.201.07:45:25.08#ibcon#read 4, iclass 27, count 2 2006.201.07:45:25.08#ibcon#about to read 5, iclass 27, count 2 2006.201.07:45:25.08#ibcon#read 5, iclass 27, count 2 2006.201.07:45:25.08#ibcon#about to read 6, iclass 27, count 2 2006.201.07:45:25.08#ibcon#read 6, iclass 27, count 2 2006.201.07:45:25.08#ibcon#end of sib2, iclass 27, count 2 2006.201.07:45:25.08#ibcon#*mode == 0, iclass 27, count 2 2006.201.07:45:25.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.07:45:25.08#ibcon#[27=AT08-04\r\n] 2006.201.07:45:25.08#ibcon#*before write, iclass 27, count 2 2006.201.07:45:25.08#ibcon#enter sib2, iclass 27, count 2 2006.201.07:45:25.08#ibcon#flushed, iclass 27, count 2 2006.201.07:45:25.08#ibcon#about to write, iclass 27, count 2 2006.201.07:45:25.08#ibcon#wrote, iclass 27, count 2 2006.201.07:45:25.08#ibcon#about to read 3, iclass 27, count 2 2006.201.07:45:25.12#ibcon#read 3, iclass 27, count 2 2006.201.07:45:25.12#ibcon#about to read 4, iclass 27, count 2 2006.201.07:45:25.12#ibcon#read 4, iclass 27, count 2 2006.201.07:45:25.12#ibcon#about to read 5, iclass 27, count 2 2006.201.07:45:25.12#ibcon#read 5, iclass 27, count 2 2006.201.07:45:25.12#ibcon#about to read 6, iclass 27, count 2 2006.201.07:45:25.12#ibcon#read 6, iclass 27, count 2 2006.201.07:45:25.12#ibcon#end of sib2, iclass 27, count 2 2006.201.07:45:25.12#ibcon#*after write, iclass 27, count 2 2006.201.07:45:25.12#ibcon#*before return 0, iclass 27, count 2 2006.201.07:45:25.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:25.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.07:45:25.12#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.07:45:25.12#ibcon#ireg 7 cls_cnt 0 2006.201.07:45:25.12#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:25.24#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:25.24#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:25.24#ibcon#enter wrdev, iclass 27, count 0 2006.201.07:45:25.24#ibcon#first serial, iclass 27, count 0 2006.201.07:45:25.24#ibcon#enter sib2, iclass 27, count 0 2006.201.07:45:25.24#ibcon#flushed, iclass 27, count 0 2006.201.07:45:25.24#ibcon#about to write, iclass 27, count 0 2006.201.07:45:25.24#ibcon#wrote, iclass 27, count 0 2006.201.07:45:25.24#ibcon#about to read 3, iclass 27, count 0 2006.201.07:45:25.26#ibcon#read 3, iclass 27, count 0 2006.201.07:45:25.26#ibcon#about to read 4, iclass 27, count 0 2006.201.07:45:25.26#ibcon#read 4, iclass 27, count 0 2006.201.07:45:25.26#ibcon#about to read 5, iclass 27, count 0 2006.201.07:45:25.26#ibcon#read 5, iclass 27, count 0 2006.201.07:45:25.26#ibcon#about to read 6, iclass 27, count 0 2006.201.07:45:25.26#ibcon#read 6, iclass 27, count 0 2006.201.07:45:25.26#ibcon#end of sib2, iclass 27, count 0 2006.201.07:45:25.26#ibcon#*mode == 0, iclass 27, count 0 2006.201.07:45:25.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.07:45:25.26#ibcon#[27=USB\r\n] 2006.201.07:45:25.26#ibcon#*before write, iclass 27, count 0 2006.201.07:45:25.26#ibcon#enter sib2, iclass 27, count 0 2006.201.07:45:25.26#ibcon#flushed, iclass 27, count 0 2006.201.07:45:25.26#ibcon#about to write, iclass 27, count 0 2006.201.07:45:25.26#ibcon#wrote, iclass 27, count 0 2006.201.07:45:25.26#ibcon#about to read 3, iclass 27, count 0 2006.201.07:45:25.29#ibcon#read 3, iclass 27, count 0 2006.201.07:45:25.29#ibcon#about to read 4, iclass 27, count 0 2006.201.07:45:25.29#ibcon#read 4, iclass 27, count 0 2006.201.07:45:25.29#ibcon#about to read 5, iclass 27, count 0 2006.201.07:45:25.29#ibcon#read 5, iclass 27, count 0 2006.201.07:45:25.29#ibcon#about to read 6, iclass 27, count 0 2006.201.07:45:25.29#ibcon#read 6, iclass 27, count 0 2006.201.07:45:25.29#ibcon#end of sib2, iclass 27, count 0 2006.201.07:45:25.29#ibcon#*after write, iclass 27, count 0 2006.201.07:45:25.29#ibcon#*before return 0, iclass 27, count 0 2006.201.07:45:25.29#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:25.29#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.07:45:25.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.07:45:25.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.07:45:25.29$vck44/vabw=wide 2006.201.07:45:25.29#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.07:45:25.29#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.07:45:25.29#ibcon#ireg 8 cls_cnt 0 2006.201.07:45:25.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:25.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:25.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:25.29#ibcon#enter wrdev, iclass 29, count 0 2006.201.07:45:25.29#ibcon#first serial, iclass 29, count 0 2006.201.07:45:25.29#ibcon#enter sib2, iclass 29, count 0 2006.201.07:45:25.29#ibcon#flushed, iclass 29, count 0 2006.201.07:45:25.29#ibcon#about to write, iclass 29, count 0 2006.201.07:45:25.29#ibcon#wrote, iclass 29, count 0 2006.201.07:45:25.29#ibcon#about to read 3, iclass 29, count 0 2006.201.07:45:25.31#ibcon#read 3, iclass 29, count 0 2006.201.07:45:25.31#ibcon#about to read 4, iclass 29, count 0 2006.201.07:45:25.31#ibcon#read 4, iclass 29, count 0 2006.201.07:45:25.31#ibcon#about to read 5, iclass 29, count 0 2006.201.07:45:25.31#ibcon#read 5, iclass 29, count 0 2006.201.07:45:25.31#ibcon#about to read 6, iclass 29, count 0 2006.201.07:45:25.31#ibcon#read 6, iclass 29, count 0 2006.201.07:45:25.31#ibcon#end of sib2, iclass 29, count 0 2006.201.07:45:25.31#ibcon#*mode == 0, iclass 29, count 0 2006.201.07:45:25.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.07:45:25.31#ibcon#[25=BW32\r\n] 2006.201.07:45:25.31#ibcon#*before write, iclass 29, count 0 2006.201.07:45:25.31#ibcon#enter sib2, iclass 29, count 0 2006.201.07:45:25.31#ibcon#flushed, iclass 29, count 0 2006.201.07:45:25.31#ibcon#about to write, iclass 29, count 0 2006.201.07:45:25.31#ibcon#wrote, iclass 29, count 0 2006.201.07:45:25.31#ibcon#about to read 3, iclass 29, count 0 2006.201.07:45:25.34#ibcon#read 3, iclass 29, count 0 2006.201.07:45:25.34#ibcon#about to read 4, iclass 29, count 0 2006.201.07:45:25.34#ibcon#read 4, iclass 29, count 0 2006.201.07:45:25.34#ibcon#about to read 5, iclass 29, count 0 2006.201.07:45:25.34#ibcon#read 5, iclass 29, count 0 2006.201.07:45:25.34#ibcon#about to read 6, iclass 29, count 0 2006.201.07:45:25.34#ibcon#read 6, iclass 29, count 0 2006.201.07:45:25.34#ibcon#end of sib2, iclass 29, count 0 2006.201.07:45:25.34#ibcon#*after write, iclass 29, count 0 2006.201.07:45:25.34#ibcon#*before return 0, iclass 29, count 0 2006.201.07:45:25.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:25.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.07:45:25.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.07:45:25.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.07:45:25.34$vck44/vbbw=wide 2006.201.07:45:25.34#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.07:45:25.34#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.07:45:25.34#ibcon#ireg 8 cls_cnt 0 2006.201.07:45:25.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:45:25.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:45:25.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:45:25.41#ibcon#enter wrdev, iclass 31, count 0 2006.201.07:45:25.41#ibcon#first serial, iclass 31, count 0 2006.201.07:45:25.41#ibcon#enter sib2, iclass 31, count 0 2006.201.07:45:25.41#ibcon#flushed, iclass 31, count 0 2006.201.07:45:25.41#ibcon#about to write, iclass 31, count 0 2006.201.07:45:25.41#ibcon#wrote, iclass 31, count 0 2006.201.07:45:25.41#ibcon#about to read 3, iclass 31, count 0 2006.201.07:45:25.43#ibcon#read 3, iclass 31, count 0 2006.201.07:45:25.43#ibcon#about to read 4, iclass 31, count 0 2006.201.07:45:25.43#ibcon#read 4, iclass 31, count 0 2006.201.07:45:25.43#ibcon#about to read 5, iclass 31, count 0 2006.201.07:45:25.43#ibcon#read 5, iclass 31, count 0 2006.201.07:45:25.43#ibcon#about to read 6, iclass 31, count 0 2006.201.07:45:25.43#ibcon#read 6, iclass 31, count 0 2006.201.07:45:25.43#ibcon#end of sib2, iclass 31, count 0 2006.201.07:45:25.43#ibcon#*mode == 0, iclass 31, count 0 2006.201.07:45:25.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.07:45:25.43#ibcon#[27=BW32\r\n] 2006.201.07:45:25.43#ibcon#*before write, iclass 31, count 0 2006.201.07:45:25.43#ibcon#enter sib2, iclass 31, count 0 2006.201.07:45:25.43#ibcon#flushed, iclass 31, count 0 2006.201.07:45:25.43#ibcon#about to write, iclass 31, count 0 2006.201.07:45:25.43#ibcon#wrote, iclass 31, count 0 2006.201.07:45:25.43#ibcon#about to read 3, iclass 31, count 0 2006.201.07:45:25.46#ibcon#read 3, iclass 31, count 0 2006.201.07:45:25.46#ibcon#about to read 4, iclass 31, count 0 2006.201.07:45:25.46#ibcon#read 4, iclass 31, count 0 2006.201.07:45:25.46#ibcon#about to read 5, iclass 31, count 0 2006.201.07:45:25.46#ibcon#read 5, iclass 31, count 0 2006.201.07:45:25.46#ibcon#about to read 6, iclass 31, count 0 2006.201.07:45:25.46#ibcon#read 6, iclass 31, count 0 2006.201.07:45:25.46#ibcon#end of sib2, iclass 31, count 0 2006.201.07:45:25.46#ibcon#*after write, iclass 31, count 0 2006.201.07:45:25.46#ibcon#*before return 0, iclass 31, count 0 2006.201.07:45:25.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:45:25.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.07:45:25.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.07:45:25.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.07:45:25.46$setupk4/ifdk4 2006.201.07:45:25.46$ifdk4/lo= 2006.201.07:45:25.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:45:25.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:45:25.46$ifdk4/patch= 2006.201.07:45:25.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:45:25.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:45:25.46$setupk4/!*+20s 2006.201.07:45:35.04#abcon#<5=/04 2.5 5.1 23.32 871003.0\r\n> 2006.201.07:45:35.06#abcon#{5=INTERFACE CLEAR} 2006.201.07:45:35.12#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:45:39.94$setupk4/"tpicd 2006.201.07:45:39.94$setupk4/echo=off 2006.201.07:45:39.94$setupk4/xlog=off 2006.201.07:45:39.94:!2006.201.07:45:58 2006.201.07:45:40.14#trakl#Source acquired 2006.201.07:45:40.14#flagr#flagr/antenna,acquired 2006.201.07:45:58.00:preob 2006.201.07:45:59.14/onsource/TRACKING 2006.201.07:45:59.14:!2006.201.07:46:08 2006.201.07:46:08.00:"tape 2006.201.07:46:08.00:"st=record 2006.201.07:46:08.00:data_valid=on 2006.201.07:46:08.00:midob 2006.201.07:46:08.14/onsource/TRACKING 2006.201.07:46:08.14/wx/23.32,1003.0,88 2006.201.07:46:08.36/cable/+6.4683E-03 2006.201.07:46:09.45/va/01,08,usb,yes,30,33 2006.201.07:46:09.45/va/02,07,usb,yes,33,33 2006.201.07:46:09.45/va/03,08,usb,yes,29,31 2006.201.07:46:09.45/va/04,07,usb,yes,34,35 2006.201.07:46:09.45/va/05,04,usb,yes,30,30 2006.201.07:46:09.45/va/06,05,usb,yes,30,30 2006.201.07:46:09.45/va/07,05,usb,yes,29,30 2006.201.07:46:09.45/va/08,04,usb,yes,28,34 2006.201.07:46:09.68/valo/01,524.99,yes,locked 2006.201.07:46:09.68/valo/02,534.99,yes,locked 2006.201.07:46:09.68/valo/03,564.99,yes,locked 2006.201.07:46:09.68/valo/04,624.99,yes,locked 2006.201.07:46:09.68/valo/05,734.99,yes,locked 2006.201.07:46:09.68/valo/06,814.99,yes,locked 2006.201.07:46:09.68/valo/07,864.99,yes,locked 2006.201.07:46:09.68/valo/08,884.99,yes,locked 2006.201.07:46:10.77/vb/01,04,usb,yes,36,33 2006.201.07:46:10.77/vb/02,05,usb,yes,34,33 2006.201.07:46:10.77/vb/03,04,usb,yes,35,38 2006.201.07:46:10.77/vb/04,05,usb,yes,35,34 2006.201.07:46:10.77/vb/05,04,usb,yes,31,34 2006.201.07:46:10.77/vb/06,04,usb,yes,36,32 2006.201.07:46:10.77/vb/07,04,usb,yes,35,35 2006.201.07:46:10.77/vb/08,04,usb,yes,32,36 2006.201.07:46:11.00/vblo/01,629.99,yes,locked 2006.201.07:46:11.00/vblo/02,634.99,yes,locked 2006.201.07:46:11.00/vblo/03,649.99,yes,locked 2006.201.07:46:11.00/vblo/04,679.99,yes,locked 2006.201.07:46:11.00/vblo/05,709.99,yes,locked 2006.201.07:46:11.00/vblo/06,719.99,yes,locked 2006.201.07:46:11.00/vblo/07,734.99,yes,locked 2006.201.07:46:11.00/vblo/08,744.99,yes,locked 2006.201.07:46:11.15/vabw/8 2006.201.07:46:11.30/vbbw/8 2006.201.07:46:11.39/xfe/off,on,16.0 2006.201.07:46:11.77/ifatt/23,28,28,28 2006.201.07:46:12.05/fmout-gps/S +4.51E-07 2006.201.07:46:12.12:!2006.201.07:47:38 2006.201.07:47:38.00:data_valid=off 2006.201.07:47:38.00:"et 2006.201.07:47:38.00:!+3s 2006.201.07:47:41.02:"tape 2006.201.07:47:41.02:postob 2006.201.07:47:41.09/cable/+6.4694E-03 2006.201.07:47:41.09/wx/23.34,1003.0,89 2006.201.07:47:41.17/fmout-gps/S +4.52E-07 2006.201.07:47:41.17:scan_name=201-0755,jd0607,784 2006.201.07:47:41.18:source=1749+096,175132.82,093900.7,2000.0,ccw 2006.201.07:47:42.14#flagr#flagr/antenna,new-source 2006.201.07:47:42.14:checkk5 2006.201.07:47:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.07:47:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.07:47:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.07:47:43.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.07:47:43.99/chk_obsdata//k5ts1/T2010746??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.07:47:44.35/chk_obsdata//k5ts2/T2010746??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.07:47:44.72/chk_obsdata//k5ts3/T2010746??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.07:47:45.09/chk_obsdata//k5ts4/T2010746??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.07:47:45.78/k5log//k5ts1_log_newline 2006.201.07:47:46.46/k5log//k5ts2_log_newline 2006.201.07:47:47.15/k5log//k5ts3_log_newline 2006.201.07:47:47.84/k5log//k5ts4_log_newline 2006.201.07:47:47.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.07:47:47.86:setupk4=1 2006.201.07:47:47.86$setupk4/echo=on 2006.201.07:47:47.86$setupk4/pcalon 2006.201.07:47:47.86$pcalon/"no phase cal control is implemented here 2006.201.07:47:47.86$setupk4/"tpicd=stop 2006.201.07:47:47.86$setupk4/"rec=synch_on 2006.201.07:47:47.86$setupk4/"rec_mode=128 2006.201.07:47:47.86$setupk4/!* 2006.201.07:47:47.86$setupk4/recpk4 2006.201.07:47:47.86$recpk4/recpatch= 2006.201.07:47:47.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.07:47:47.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.07:47:47.87$setupk4/vck44 2006.201.07:47:47.87$vck44/valo=1,524.99 2006.201.07:47:47.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.07:47:47.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.07:47:47.87#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:47.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:47.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:47.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:47.87#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:47:47.87#ibcon#first serial, iclass 20, count 0 2006.201.07:47:47.87#ibcon#enter sib2, iclass 20, count 0 2006.201.07:47:47.87#ibcon#flushed, iclass 20, count 0 2006.201.07:47:47.87#ibcon#about to write, iclass 20, count 0 2006.201.07:47:47.87#ibcon#wrote, iclass 20, count 0 2006.201.07:47:47.87#ibcon#about to read 3, iclass 20, count 0 2006.201.07:47:47.90#ibcon#read 3, iclass 20, count 0 2006.201.07:47:47.90#ibcon#about to read 4, iclass 20, count 0 2006.201.07:47:47.90#ibcon#read 4, iclass 20, count 0 2006.201.07:47:47.90#ibcon#about to read 5, iclass 20, count 0 2006.201.07:47:47.90#ibcon#read 5, iclass 20, count 0 2006.201.07:47:47.90#ibcon#about to read 6, iclass 20, count 0 2006.201.07:47:47.90#ibcon#read 6, iclass 20, count 0 2006.201.07:47:47.90#ibcon#end of sib2, iclass 20, count 0 2006.201.07:47:47.90#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:47:47.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:47:47.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.07:47:47.90#ibcon#*before write, iclass 20, count 0 2006.201.07:47:47.90#ibcon#enter sib2, iclass 20, count 0 2006.201.07:47:47.90#ibcon#flushed, iclass 20, count 0 2006.201.07:47:47.90#ibcon#about to write, iclass 20, count 0 2006.201.07:47:47.90#ibcon#wrote, iclass 20, count 0 2006.201.07:47:47.90#ibcon#about to read 3, iclass 20, count 0 2006.201.07:47:47.95#ibcon#read 3, iclass 20, count 0 2006.201.07:47:47.95#ibcon#about to read 4, iclass 20, count 0 2006.201.07:47:47.95#ibcon#read 4, iclass 20, count 0 2006.201.07:47:47.95#ibcon#about to read 5, iclass 20, count 0 2006.201.07:47:47.95#ibcon#read 5, iclass 20, count 0 2006.201.07:47:47.95#ibcon#about to read 6, iclass 20, count 0 2006.201.07:47:47.95#ibcon#read 6, iclass 20, count 0 2006.201.07:47:47.95#ibcon#end of sib2, iclass 20, count 0 2006.201.07:47:47.95#ibcon#*after write, iclass 20, count 0 2006.201.07:47:47.95#ibcon#*before return 0, iclass 20, count 0 2006.201.07:47:47.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:47.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:47.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:47:47.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:47:47.95$vck44/va=1,8 2006.201.07:47:47.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.07:47:47.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.07:47:47.95#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:47.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:47.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:47.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:47.95#ibcon#enter wrdev, iclass 22, count 2 2006.201.07:47:47.95#ibcon#first serial, iclass 22, count 2 2006.201.07:47:47.95#ibcon#enter sib2, iclass 22, count 2 2006.201.07:47:47.95#ibcon#flushed, iclass 22, count 2 2006.201.07:47:47.95#ibcon#about to write, iclass 22, count 2 2006.201.07:47:47.95#ibcon#wrote, iclass 22, count 2 2006.201.07:47:47.95#ibcon#about to read 3, iclass 22, count 2 2006.201.07:47:47.97#ibcon#read 3, iclass 22, count 2 2006.201.07:47:47.97#ibcon#about to read 4, iclass 22, count 2 2006.201.07:47:47.97#ibcon#read 4, iclass 22, count 2 2006.201.07:47:47.97#ibcon#about to read 5, iclass 22, count 2 2006.201.07:47:47.97#ibcon#read 5, iclass 22, count 2 2006.201.07:47:47.97#ibcon#about to read 6, iclass 22, count 2 2006.201.07:47:47.97#ibcon#read 6, iclass 22, count 2 2006.201.07:47:47.97#ibcon#end of sib2, iclass 22, count 2 2006.201.07:47:47.97#ibcon#*mode == 0, iclass 22, count 2 2006.201.07:47:47.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.07:47:47.97#ibcon#[25=AT01-08\r\n] 2006.201.07:47:47.97#ibcon#*before write, iclass 22, count 2 2006.201.07:47:47.97#ibcon#enter sib2, iclass 22, count 2 2006.201.07:47:47.97#ibcon#flushed, iclass 22, count 2 2006.201.07:47:47.97#ibcon#about to write, iclass 22, count 2 2006.201.07:47:47.97#ibcon#wrote, iclass 22, count 2 2006.201.07:47:47.97#ibcon#about to read 3, iclass 22, count 2 2006.201.07:47:48.00#ibcon#read 3, iclass 22, count 2 2006.201.07:47:48.00#ibcon#about to read 4, iclass 22, count 2 2006.201.07:47:48.00#ibcon#read 4, iclass 22, count 2 2006.201.07:47:48.00#ibcon#about to read 5, iclass 22, count 2 2006.201.07:47:48.00#ibcon#read 5, iclass 22, count 2 2006.201.07:47:48.00#ibcon#about to read 6, iclass 22, count 2 2006.201.07:47:48.00#ibcon#read 6, iclass 22, count 2 2006.201.07:47:48.00#ibcon#end of sib2, iclass 22, count 2 2006.201.07:47:48.00#ibcon#*after write, iclass 22, count 2 2006.201.07:47:48.00#ibcon#*before return 0, iclass 22, count 2 2006.201.07:47:48.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:48.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:48.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.07:47:48.00#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:48.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:48.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:48.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:48.12#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:47:48.12#ibcon#first serial, iclass 22, count 0 2006.201.07:47:48.12#ibcon#enter sib2, iclass 22, count 0 2006.201.07:47:48.12#ibcon#flushed, iclass 22, count 0 2006.201.07:47:48.12#ibcon#about to write, iclass 22, count 0 2006.201.07:47:48.12#ibcon#wrote, iclass 22, count 0 2006.201.07:47:48.12#ibcon#about to read 3, iclass 22, count 0 2006.201.07:47:48.14#ibcon#read 3, iclass 22, count 0 2006.201.07:47:48.14#ibcon#about to read 4, iclass 22, count 0 2006.201.07:47:48.14#ibcon#read 4, iclass 22, count 0 2006.201.07:47:48.14#ibcon#about to read 5, iclass 22, count 0 2006.201.07:47:48.14#ibcon#read 5, iclass 22, count 0 2006.201.07:47:48.14#ibcon#about to read 6, iclass 22, count 0 2006.201.07:47:48.14#ibcon#read 6, iclass 22, count 0 2006.201.07:47:48.14#ibcon#end of sib2, iclass 22, count 0 2006.201.07:47:48.14#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:47:48.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:47:48.14#ibcon#[25=USB\r\n] 2006.201.07:47:48.14#ibcon#*before write, iclass 22, count 0 2006.201.07:47:48.14#ibcon#enter sib2, iclass 22, count 0 2006.201.07:47:48.14#ibcon#flushed, iclass 22, count 0 2006.201.07:47:48.14#ibcon#about to write, iclass 22, count 0 2006.201.07:47:48.14#ibcon#wrote, iclass 22, count 0 2006.201.07:47:48.14#ibcon#about to read 3, iclass 22, count 0 2006.201.07:47:48.17#ibcon#read 3, iclass 22, count 0 2006.201.07:47:48.17#ibcon#about to read 4, iclass 22, count 0 2006.201.07:47:48.17#ibcon#read 4, iclass 22, count 0 2006.201.07:47:48.17#ibcon#about to read 5, iclass 22, count 0 2006.201.07:47:48.17#ibcon#read 5, iclass 22, count 0 2006.201.07:47:48.17#ibcon#about to read 6, iclass 22, count 0 2006.201.07:47:48.17#ibcon#read 6, iclass 22, count 0 2006.201.07:47:48.17#ibcon#end of sib2, iclass 22, count 0 2006.201.07:47:48.17#ibcon#*after write, iclass 22, count 0 2006.201.07:47:48.17#ibcon#*before return 0, iclass 22, count 0 2006.201.07:47:48.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:48.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:48.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:47:48.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:47:48.17$vck44/valo=2,534.99 2006.201.07:47:48.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.07:47:48.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.07:47:48.17#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:48.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:48.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:48.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:48.17#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:47:48.17#ibcon#first serial, iclass 24, count 0 2006.201.07:47:48.17#ibcon#enter sib2, iclass 24, count 0 2006.201.07:47:48.17#ibcon#flushed, iclass 24, count 0 2006.201.07:47:48.17#ibcon#about to write, iclass 24, count 0 2006.201.07:47:48.17#ibcon#wrote, iclass 24, count 0 2006.201.07:47:48.17#ibcon#about to read 3, iclass 24, count 0 2006.201.07:47:48.19#ibcon#read 3, iclass 24, count 0 2006.201.07:47:48.19#ibcon#about to read 4, iclass 24, count 0 2006.201.07:47:48.19#ibcon#read 4, iclass 24, count 0 2006.201.07:47:48.19#ibcon#about to read 5, iclass 24, count 0 2006.201.07:47:48.19#ibcon#read 5, iclass 24, count 0 2006.201.07:47:48.19#ibcon#about to read 6, iclass 24, count 0 2006.201.07:47:48.19#ibcon#read 6, iclass 24, count 0 2006.201.07:47:48.19#ibcon#end of sib2, iclass 24, count 0 2006.201.07:47:48.19#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:47:48.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:47:48.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.07:47:48.19#ibcon#*before write, iclass 24, count 0 2006.201.07:47:48.19#ibcon#enter sib2, iclass 24, count 0 2006.201.07:47:48.19#ibcon#flushed, iclass 24, count 0 2006.201.07:47:48.19#ibcon#about to write, iclass 24, count 0 2006.201.07:47:48.19#ibcon#wrote, iclass 24, count 0 2006.201.07:47:48.19#ibcon#about to read 3, iclass 24, count 0 2006.201.07:47:48.24#ibcon#read 3, iclass 24, count 0 2006.201.07:47:48.24#ibcon#about to read 4, iclass 24, count 0 2006.201.07:47:48.24#ibcon#read 4, iclass 24, count 0 2006.201.07:47:48.24#ibcon#about to read 5, iclass 24, count 0 2006.201.07:47:48.24#ibcon#read 5, iclass 24, count 0 2006.201.07:47:48.24#ibcon#about to read 6, iclass 24, count 0 2006.201.07:47:48.24#ibcon#read 6, iclass 24, count 0 2006.201.07:47:48.24#ibcon#end of sib2, iclass 24, count 0 2006.201.07:47:48.24#ibcon#*after write, iclass 24, count 0 2006.201.07:47:48.24#ibcon#*before return 0, iclass 24, count 0 2006.201.07:47:48.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:48.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:48.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:47:48.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:47:48.24$vck44/va=2,7 2006.201.07:47:48.24#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.07:47:48.24#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.07:47:48.24#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:48.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:48.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:48.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:48.29#ibcon#enter wrdev, iclass 26, count 2 2006.201.07:47:48.29#ibcon#first serial, iclass 26, count 2 2006.201.07:47:48.29#ibcon#enter sib2, iclass 26, count 2 2006.201.07:47:48.29#ibcon#flushed, iclass 26, count 2 2006.201.07:47:48.29#ibcon#about to write, iclass 26, count 2 2006.201.07:47:48.29#ibcon#wrote, iclass 26, count 2 2006.201.07:47:48.29#ibcon#about to read 3, iclass 26, count 2 2006.201.07:47:48.31#ibcon#read 3, iclass 26, count 2 2006.201.07:47:48.31#ibcon#about to read 4, iclass 26, count 2 2006.201.07:47:48.31#ibcon#read 4, iclass 26, count 2 2006.201.07:47:48.31#ibcon#about to read 5, iclass 26, count 2 2006.201.07:47:48.31#ibcon#read 5, iclass 26, count 2 2006.201.07:47:48.31#ibcon#about to read 6, iclass 26, count 2 2006.201.07:47:48.31#ibcon#read 6, iclass 26, count 2 2006.201.07:47:48.31#ibcon#end of sib2, iclass 26, count 2 2006.201.07:47:48.31#ibcon#*mode == 0, iclass 26, count 2 2006.201.07:47:48.31#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.07:47:48.31#ibcon#[25=AT02-07\r\n] 2006.201.07:47:48.31#ibcon#*before write, iclass 26, count 2 2006.201.07:47:48.31#ibcon#enter sib2, iclass 26, count 2 2006.201.07:47:48.31#ibcon#flushed, iclass 26, count 2 2006.201.07:47:48.31#ibcon#about to write, iclass 26, count 2 2006.201.07:47:48.31#ibcon#wrote, iclass 26, count 2 2006.201.07:47:48.31#ibcon#about to read 3, iclass 26, count 2 2006.201.07:47:48.34#ibcon#read 3, iclass 26, count 2 2006.201.07:47:48.34#ibcon#about to read 4, iclass 26, count 2 2006.201.07:47:48.34#ibcon#read 4, iclass 26, count 2 2006.201.07:47:48.34#ibcon#about to read 5, iclass 26, count 2 2006.201.07:47:48.34#ibcon#read 5, iclass 26, count 2 2006.201.07:47:48.34#ibcon#about to read 6, iclass 26, count 2 2006.201.07:47:48.34#ibcon#read 6, iclass 26, count 2 2006.201.07:47:48.34#ibcon#end of sib2, iclass 26, count 2 2006.201.07:47:48.34#ibcon#*after write, iclass 26, count 2 2006.201.07:47:48.34#ibcon#*before return 0, iclass 26, count 2 2006.201.07:47:48.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:48.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:48.34#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.07:47:48.34#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:48.34#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:48.46#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:48.46#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:48.46#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:47:48.46#ibcon#first serial, iclass 26, count 0 2006.201.07:47:48.46#ibcon#enter sib2, iclass 26, count 0 2006.201.07:47:48.46#ibcon#flushed, iclass 26, count 0 2006.201.07:47:48.46#ibcon#about to write, iclass 26, count 0 2006.201.07:47:48.46#ibcon#wrote, iclass 26, count 0 2006.201.07:47:48.46#ibcon#about to read 3, iclass 26, count 0 2006.201.07:47:48.48#ibcon#read 3, iclass 26, count 0 2006.201.07:47:48.48#ibcon#about to read 4, iclass 26, count 0 2006.201.07:47:48.48#ibcon#read 4, iclass 26, count 0 2006.201.07:47:48.48#ibcon#about to read 5, iclass 26, count 0 2006.201.07:47:48.48#ibcon#read 5, iclass 26, count 0 2006.201.07:47:48.48#ibcon#about to read 6, iclass 26, count 0 2006.201.07:47:48.48#ibcon#read 6, iclass 26, count 0 2006.201.07:47:48.48#ibcon#end of sib2, iclass 26, count 0 2006.201.07:47:48.48#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:47:48.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:47:48.48#ibcon#[25=USB\r\n] 2006.201.07:47:48.48#ibcon#*before write, iclass 26, count 0 2006.201.07:47:48.48#ibcon#enter sib2, iclass 26, count 0 2006.201.07:47:48.48#ibcon#flushed, iclass 26, count 0 2006.201.07:47:48.48#ibcon#about to write, iclass 26, count 0 2006.201.07:47:48.48#ibcon#wrote, iclass 26, count 0 2006.201.07:47:48.48#ibcon#about to read 3, iclass 26, count 0 2006.201.07:47:48.51#ibcon#read 3, iclass 26, count 0 2006.201.07:47:48.51#ibcon#about to read 4, iclass 26, count 0 2006.201.07:47:48.51#ibcon#read 4, iclass 26, count 0 2006.201.07:47:48.51#ibcon#about to read 5, iclass 26, count 0 2006.201.07:47:48.51#ibcon#read 5, iclass 26, count 0 2006.201.07:47:48.51#ibcon#about to read 6, iclass 26, count 0 2006.201.07:47:48.51#ibcon#read 6, iclass 26, count 0 2006.201.07:47:48.51#ibcon#end of sib2, iclass 26, count 0 2006.201.07:47:48.51#ibcon#*after write, iclass 26, count 0 2006.201.07:47:48.51#ibcon#*before return 0, iclass 26, count 0 2006.201.07:47:48.51#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:48.51#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:48.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:47:48.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:47:48.51$vck44/valo=3,564.99 2006.201.07:47:48.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.07:47:48.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.07:47:48.51#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:48.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:48.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:48.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:48.51#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:47:48.51#ibcon#first serial, iclass 28, count 0 2006.201.07:47:48.51#ibcon#enter sib2, iclass 28, count 0 2006.201.07:47:48.51#ibcon#flushed, iclass 28, count 0 2006.201.07:47:48.51#ibcon#about to write, iclass 28, count 0 2006.201.07:47:48.51#ibcon#wrote, iclass 28, count 0 2006.201.07:47:48.51#ibcon#about to read 3, iclass 28, count 0 2006.201.07:47:48.53#ibcon#read 3, iclass 28, count 0 2006.201.07:47:48.53#ibcon#about to read 4, iclass 28, count 0 2006.201.07:47:48.53#ibcon#read 4, iclass 28, count 0 2006.201.07:47:48.53#ibcon#about to read 5, iclass 28, count 0 2006.201.07:47:48.53#ibcon#read 5, iclass 28, count 0 2006.201.07:47:48.53#ibcon#about to read 6, iclass 28, count 0 2006.201.07:47:48.53#ibcon#read 6, iclass 28, count 0 2006.201.07:47:48.53#ibcon#end of sib2, iclass 28, count 0 2006.201.07:47:48.53#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:47:48.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:47:48.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.07:47:48.53#ibcon#*before write, iclass 28, count 0 2006.201.07:47:48.53#ibcon#enter sib2, iclass 28, count 0 2006.201.07:47:48.53#ibcon#flushed, iclass 28, count 0 2006.201.07:47:48.53#ibcon#about to write, iclass 28, count 0 2006.201.07:47:48.53#ibcon#wrote, iclass 28, count 0 2006.201.07:47:48.53#ibcon#about to read 3, iclass 28, count 0 2006.201.07:47:48.58#ibcon#read 3, iclass 28, count 0 2006.201.07:47:48.58#ibcon#about to read 4, iclass 28, count 0 2006.201.07:47:48.58#ibcon#read 4, iclass 28, count 0 2006.201.07:47:48.58#ibcon#about to read 5, iclass 28, count 0 2006.201.07:47:48.58#ibcon#read 5, iclass 28, count 0 2006.201.07:47:48.58#ibcon#about to read 6, iclass 28, count 0 2006.201.07:47:48.58#ibcon#read 6, iclass 28, count 0 2006.201.07:47:48.58#ibcon#end of sib2, iclass 28, count 0 2006.201.07:47:48.58#ibcon#*after write, iclass 28, count 0 2006.201.07:47:48.58#ibcon#*before return 0, iclass 28, count 0 2006.201.07:47:48.58#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:48.58#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:48.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:47:48.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:47:48.58$vck44/va=3,8 2006.201.07:47:48.58#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.07:47:48.58#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.07:47:48.58#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:48.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:48.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:48.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:48.63#ibcon#enter wrdev, iclass 30, count 2 2006.201.07:47:48.63#ibcon#first serial, iclass 30, count 2 2006.201.07:47:48.63#ibcon#enter sib2, iclass 30, count 2 2006.201.07:47:48.63#ibcon#flushed, iclass 30, count 2 2006.201.07:47:48.63#ibcon#about to write, iclass 30, count 2 2006.201.07:47:48.63#ibcon#wrote, iclass 30, count 2 2006.201.07:47:48.63#ibcon#about to read 3, iclass 30, count 2 2006.201.07:47:48.65#ibcon#read 3, iclass 30, count 2 2006.201.07:47:48.65#ibcon#about to read 4, iclass 30, count 2 2006.201.07:47:48.65#ibcon#read 4, iclass 30, count 2 2006.201.07:47:48.65#ibcon#about to read 5, iclass 30, count 2 2006.201.07:47:48.65#ibcon#read 5, iclass 30, count 2 2006.201.07:47:48.65#ibcon#about to read 6, iclass 30, count 2 2006.201.07:47:48.65#ibcon#read 6, iclass 30, count 2 2006.201.07:47:48.65#ibcon#end of sib2, iclass 30, count 2 2006.201.07:47:48.65#ibcon#*mode == 0, iclass 30, count 2 2006.201.07:47:48.65#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.07:47:48.65#ibcon#[25=AT03-08\r\n] 2006.201.07:47:48.65#ibcon#*before write, iclass 30, count 2 2006.201.07:47:48.65#ibcon#enter sib2, iclass 30, count 2 2006.201.07:47:48.65#ibcon#flushed, iclass 30, count 2 2006.201.07:47:48.65#ibcon#about to write, iclass 30, count 2 2006.201.07:47:48.65#ibcon#wrote, iclass 30, count 2 2006.201.07:47:48.65#ibcon#about to read 3, iclass 30, count 2 2006.201.07:47:48.68#ibcon#read 3, iclass 30, count 2 2006.201.07:47:48.68#ibcon#about to read 4, iclass 30, count 2 2006.201.07:47:48.68#ibcon#read 4, iclass 30, count 2 2006.201.07:47:48.68#ibcon#about to read 5, iclass 30, count 2 2006.201.07:47:48.68#ibcon#read 5, iclass 30, count 2 2006.201.07:47:48.68#ibcon#about to read 6, iclass 30, count 2 2006.201.07:47:48.68#ibcon#read 6, iclass 30, count 2 2006.201.07:47:48.68#ibcon#end of sib2, iclass 30, count 2 2006.201.07:47:48.68#ibcon#*after write, iclass 30, count 2 2006.201.07:47:48.68#ibcon#*before return 0, iclass 30, count 2 2006.201.07:47:48.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:48.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:48.68#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.07:47:48.68#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:48.68#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:48.80#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:48.80#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:48.80#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:47:48.80#ibcon#first serial, iclass 30, count 0 2006.201.07:47:48.80#ibcon#enter sib2, iclass 30, count 0 2006.201.07:47:48.80#ibcon#flushed, iclass 30, count 0 2006.201.07:47:48.80#ibcon#about to write, iclass 30, count 0 2006.201.07:47:48.80#ibcon#wrote, iclass 30, count 0 2006.201.07:47:48.80#ibcon#about to read 3, iclass 30, count 0 2006.201.07:47:48.82#ibcon#read 3, iclass 30, count 0 2006.201.07:47:48.82#ibcon#about to read 4, iclass 30, count 0 2006.201.07:47:48.82#ibcon#read 4, iclass 30, count 0 2006.201.07:47:48.82#ibcon#about to read 5, iclass 30, count 0 2006.201.07:47:48.82#ibcon#read 5, iclass 30, count 0 2006.201.07:47:48.82#ibcon#about to read 6, iclass 30, count 0 2006.201.07:47:48.82#ibcon#read 6, iclass 30, count 0 2006.201.07:47:48.82#ibcon#end of sib2, iclass 30, count 0 2006.201.07:47:48.82#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:47:48.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:47:48.82#ibcon#[25=USB\r\n] 2006.201.07:47:48.82#ibcon#*before write, iclass 30, count 0 2006.201.07:47:48.82#ibcon#enter sib2, iclass 30, count 0 2006.201.07:47:48.82#ibcon#flushed, iclass 30, count 0 2006.201.07:47:48.82#ibcon#about to write, iclass 30, count 0 2006.201.07:47:48.82#ibcon#wrote, iclass 30, count 0 2006.201.07:47:48.82#ibcon#about to read 3, iclass 30, count 0 2006.201.07:47:48.85#ibcon#read 3, iclass 30, count 0 2006.201.07:47:48.85#ibcon#about to read 4, iclass 30, count 0 2006.201.07:47:48.85#ibcon#read 4, iclass 30, count 0 2006.201.07:47:48.85#ibcon#about to read 5, iclass 30, count 0 2006.201.07:47:48.85#ibcon#read 5, iclass 30, count 0 2006.201.07:47:48.85#ibcon#about to read 6, iclass 30, count 0 2006.201.07:47:48.85#ibcon#read 6, iclass 30, count 0 2006.201.07:47:48.85#ibcon#end of sib2, iclass 30, count 0 2006.201.07:47:48.85#ibcon#*after write, iclass 30, count 0 2006.201.07:47:48.85#ibcon#*before return 0, iclass 30, count 0 2006.201.07:47:48.85#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:48.85#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:48.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:47:48.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:47:48.85$vck44/valo=4,624.99 2006.201.07:47:48.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.07:47:48.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.07:47:48.85#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:48.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:48.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:48.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:48.85#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:47:48.85#ibcon#first serial, iclass 32, count 0 2006.201.07:47:48.85#ibcon#enter sib2, iclass 32, count 0 2006.201.07:47:48.85#ibcon#flushed, iclass 32, count 0 2006.201.07:47:48.85#ibcon#about to write, iclass 32, count 0 2006.201.07:47:48.85#ibcon#wrote, iclass 32, count 0 2006.201.07:47:48.85#ibcon#about to read 3, iclass 32, count 0 2006.201.07:47:48.87#ibcon#read 3, iclass 32, count 0 2006.201.07:47:48.87#ibcon#about to read 4, iclass 32, count 0 2006.201.07:47:48.87#ibcon#read 4, iclass 32, count 0 2006.201.07:47:48.87#ibcon#about to read 5, iclass 32, count 0 2006.201.07:47:48.87#ibcon#read 5, iclass 32, count 0 2006.201.07:47:48.87#ibcon#about to read 6, iclass 32, count 0 2006.201.07:47:48.87#ibcon#read 6, iclass 32, count 0 2006.201.07:47:48.87#ibcon#end of sib2, iclass 32, count 0 2006.201.07:47:48.87#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:47:48.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:47:48.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.07:47:48.87#ibcon#*before write, iclass 32, count 0 2006.201.07:47:48.87#ibcon#enter sib2, iclass 32, count 0 2006.201.07:47:48.87#ibcon#flushed, iclass 32, count 0 2006.201.07:47:48.87#ibcon#about to write, iclass 32, count 0 2006.201.07:47:48.87#ibcon#wrote, iclass 32, count 0 2006.201.07:47:48.87#ibcon#about to read 3, iclass 32, count 0 2006.201.07:47:48.92#ibcon#read 3, iclass 32, count 0 2006.201.07:47:48.92#ibcon#about to read 4, iclass 32, count 0 2006.201.07:47:48.92#ibcon#read 4, iclass 32, count 0 2006.201.07:47:48.92#ibcon#about to read 5, iclass 32, count 0 2006.201.07:47:48.92#ibcon#read 5, iclass 32, count 0 2006.201.07:47:48.92#ibcon#about to read 6, iclass 32, count 0 2006.201.07:47:48.92#ibcon#read 6, iclass 32, count 0 2006.201.07:47:48.92#ibcon#end of sib2, iclass 32, count 0 2006.201.07:47:48.92#ibcon#*after write, iclass 32, count 0 2006.201.07:47:48.92#ibcon#*before return 0, iclass 32, count 0 2006.201.07:47:48.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:48.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:48.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:47:48.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:47:48.92$vck44/va=4,7 2006.201.07:47:48.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.07:47:48.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.07:47:48.92#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:48.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:48.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:48.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:48.97#ibcon#enter wrdev, iclass 34, count 2 2006.201.07:47:48.97#ibcon#first serial, iclass 34, count 2 2006.201.07:47:48.97#ibcon#enter sib2, iclass 34, count 2 2006.201.07:47:48.97#ibcon#flushed, iclass 34, count 2 2006.201.07:47:48.97#ibcon#about to write, iclass 34, count 2 2006.201.07:47:48.97#ibcon#wrote, iclass 34, count 2 2006.201.07:47:48.97#ibcon#about to read 3, iclass 34, count 2 2006.201.07:47:48.99#ibcon#read 3, iclass 34, count 2 2006.201.07:47:48.99#ibcon#about to read 4, iclass 34, count 2 2006.201.07:47:48.99#ibcon#read 4, iclass 34, count 2 2006.201.07:47:48.99#ibcon#about to read 5, iclass 34, count 2 2006.201.07:47:48.99#ibcon#read 5, iclass 34, count 2 2006.201.07:47:48.99#ibcon#about to read 6, iclass 34, count 2 2006.201.07:47:48.99#ibcon#read 6, iclass 34, count 2 2006.201.07:47:48.99#ibcon#end of sib2, iclass 34, count 2 2006.201.07:47:48.99#ibcon#*mode == 0, iclass 34, count 2 2006.201.07:47:48.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.07:47:48.99#ibcon#[25=AT04-07\r\n] 2006.201.07:47:48.99#ibcon#*before write, iclass 34, count 2 2006.201.07:47:48.99#ibcon#enter sib2, iclass 34, count 2 2006.201.07:47:48.99#ibcon#flushed, iclass 34, count 2 2006.201.07:47:48.99#ibcon#about to write, iclass 34, count 2 2006.201.07:47:48.99#ibcon#wrote, iclass 34, count 2 2006.201.07:47:48.99#ibcon#about to read 3, iclass 34, count 2 2006.201.07:47:49.02#ibcon#read 3, iclass 34, count 2 2006.201.07:47:49.02#ibcon#about to read 4, iclass 34, count 2 2006.201.07:47:49.02#ibcon#read 4, iclass 34, count 2 2006.201.07:47:49.02#ibcon#about to read 5, iclass 34, count 2 2006.201.07:47:49.02#ibcon#read 5, iclass 34, count 2 2006.201.07:47:49.02#ibcon#about to read 6, iclass 34, count 2 2006.201.07:47:49.02#ibcon#read 6, iclass 34, count 2 2006.201.07:47:49.02#ibcon#end of sib2, iclass 34, count 2 2006.201.07:47:49.02#ibcon#*after write, iclass 34, count 2 2006.201.07:47:49.02#ibcon#*before return 0, iclass 34, count 2 2006.201.07:47:49.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:49.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:49.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.07:47:49.02#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:49.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:49.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:49.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:49.14#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:47:49.14#ibcon#first serial, iclass 34, count 0 2006.201.07:47:49.14#ibcon#enter sib2, iclass 34, count 0 2006.201.07:47:49.14#ibcon#flushed, iclass 34, count 0 2006.201.07:47:49.14#ibcon#about to write, iclass 34, count 0 2006.201.07:47:49.14#ibcon#wrote, iclass 34, count 0 2006.201.07:47:49.14#ibcon#about to read 3, iclass 34, count 0 2006.201.07:47:49.16#ibcon#read 3, iclass 34, count 0 2006.201.07:47:49.16#ibcon#about to read 4, iclass 34, count 0 2006.201.07:47:49.16#ibcon#read 4, iclass 34, count 0 2006.201.07:47:49.16#ibcon#about to read 5, iclass 34, count 0 2006.201.07:47:49.16#ibcon#read 5, iclass 34, count 0 2006.201.07:47:49.16#ibcon#about to read 6, iclass 34, count 0 2006.201.07:47:49.16#ibcon#read 6, iclass 34, count 0 2006.201.07:47:49.16#ibcon#end of sib2, iclass 34, count 0 2006.201.07:47:49.16#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:47:49.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:47:49.16#ibcon#[25=USB\r\n] 2006.201.07:47:49.16#ibcon#*before write, iclass 34, count 0 2006.201.07:47:49.16#ibcon#enter sib2, iclass 34, count 0 2006.201.07:47:49.16#ibcon#flushed, iclass 34, count 0 2006.201.07:47:49.16#ibcon#about to write, iclass 34, count 0 2006.201.07:47:49.16#ibcon#wrote, iclass 34, count 0 2006.201.07:47:49.16#ibcon#about to read 3, iclass 34, count 0 2006.201.07:47:49.19#ibcon#read 3, iclass 34, count 0 2006.201.07:47:49.19#ibcon#about to read 4, iclass 34, count 0 2006.201.07:47:49.19#ibcon#read 4, iclass 34, count 0 2006.201.07:47:49.19#ibcon#about to read 5, iclass 34, count 0 2006.201.07:47:49.19#ibcon#read 5, iclass 34, count 0 2006.201.07:47:49.19#ibcon#about to read 6, iclass 34, count 0 2006.201.07:47:49.19#ibcon#read 6, iclass 34, count 0 2006.201.07:47:49.19#ibcon#end of sib2, iclass 34, count 0 2006.201.07:47:49.19#ibcon#*after write, iclass 34, count 0 2006.201.07:47:49.19#ibcon#*before return 0, iclass 34, count 0 2006.201.07:47:49.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:49.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:49.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:47:49.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:47:49.19$vck44/valo=5,734.99 2006.201.07:47:49.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.07:47:49.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.07:47:49.19#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:49.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:49.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:49.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:49.19#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:47:49.19#ibcon#first serial, iclass 36, count 0 2006.201.07:47:49.19#ibcon#enter sib2, iclass 36, count 0 2006.201.07:47:49.19#ibcon#flushed, iclass 36, count 0 2006.201.07:47:49.19#ibcon#about to write, iclass 36, count 0 2006.201.07:47:49.19#ibcon#wrote, iclass 36, count 0 2006.201.07:47:49.19#ibcon#about to read 3, iclass 36, count 0 2006.201.07:47:49.21#ibcon#read 3, iclass 36, count 0 2006.201.07:47:49.21#ibcon#about to read 4, iclass 36, count 0 2006.201.07:47:49.21#ibcon#read 4, iclass 36, count 0 2006.201.07:47:49.21#ibcon#about to read 5, iclass 36, count 0 2006.201.07:47:49.21#ibcon#read 5, iclass 36, count 0 2006.201.07:47:49.21#ibcon#about to read 6, iclass 36, count 0 2006.201.07:47:49.21#ibcon#read 6, iclass 36, count 0 2006.201.07:47:49.21#ibcon#end of sib2, iclass 36, count 0 2006.201.07:47:49.21#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:47:49.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:47:49.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.07:47:49.21#ibcon#*before write, iclass 36, count 0 2006.201.07:47:49.21#ibcon#enter sib2, iclass 36, count 0 2006.201.07:47:49.21#ibcon#flushed, iclass 36, count 0 2006.201.07:47:49.21#ibcon#about to write, iclass 36, count 0 2006.201.07:47:49.21#ibcon#wrote, iclass 36, count 0 2006.201.07:47:49.21#ibcon#about to read 3, iclass 36, count 0 2006.201.07:47:49.25#ibcon#read 3, iclass 36, count 0 2006.201.07:47:49.25#ibcon#about to read 4, iclass 36, count 0 2006.201.07:47:49.25#ibcon#read 4, iclass 36, count 0 2006.201.07:47:49.25#ibcon#about to read 5, iclass 36, count 0 2006.201.07:47:49.25#ibcon#read 5, iclass 36, count 0 2006.201.07:47:49.25#ibcon#about to read 6, iclass 36, count 0 2006.201.07:47:49.25#ibcon#read 6, iclass 36, count 0 2006.201.07:47:49.25#ibcon#end of sib2, iclass 36, count 0 2006.201.07:47:49.25#ibcon#*after write, iclass 36, count 0 2006.201.07:47:49.25#ibcon#*before return 0, iclass 36, count 0 2006.201.07:47:49.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:49.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:49.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:47:49.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:47:49.25$vck44/va=5,4 2006.201.07:47:49.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.07:47:49.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.07:47:49.25#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:49.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:49.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:49.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:49.31#ibcon#enter wrdev, iclass 38, count 2 2006.201.07:47:49.31#ibcon#first serial, iclass 38, count 2 2006.201.07:47:49.31#ibcon#enter sib2, iclass 38, count 2 2006.201.07:47:49.31#ibcon#flushed, iclass 38, count 2 2006.201.07:47:49.31#ibcon#about to write, iclass 38, count 2 2006.201.07:47:49.31#ibcon#wrote, iclass 38, count 2 2006.201.07:47:49.31#ibcon#about to read 3, iclass 38, count 2 2006.201.07:47:49.33#ibcon#read 3, iclass 38, count 2 2006.201.07:47:49.33#ibcon#about to read 4, iclass 38, count 2 2006.201.07:47:49.33#ibcon#read 4, iclass 38, count 2 2006.201.07:47:49.33#ibcon#about to read 5, iclass 38, count 2 2006.201.07:47:49.33#ibcon#read 5, iclass 38, count 2 2006.201.07:47:49.33#ibcon#about to read 6, iclass 38, count 2 2006.201.07:47:49.33#ibcon#read 6, iclass 38, count 2 2006.201.07:47:49.33#ibcon#end of sib2, iclass 38, count 2 2006.201.07:47:49.33#ibcon#*mode == 0, iclass 38, count 2 2006.201.07:47:49.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.07:47:49.33#ibcon#[25=AT05-04\r\n] 2006.201.07:47:49.33#ibcon#*before write, iclass 38, count 2 2006.201.07:47:49.33#ibcon#enter sib2, iclass 38, count 2 2006.201.07:47:49.33#ibcon#flushed, iclass 38, count 2 2006.201.07:47:49.33#ibcon#about to write, iclass 38, count 2 2006.201.07:47:49.33#ibcon#wrote, iclass 38, count 2 2006.201.07:47:49.33#ibcon#about to read 3, iclass 38, count 2 2006.201.07:47:49.36#ibcon#read 3, iclass 38, count 2 2006.201.07:47:49.36#ibcon#about to read 4, iclass 38, count 2 2006.201.07:47:49.36#ibcon#read 4, iclass 38, count 2 2006.201.07:47:49.36#ibcon#about to read 5, iclass 38, count 2 2006.201.07:47:49.36#ibcon#read 5, iclass 38, count 2 2006.201.07:47:49.36#ibcon#about to read 6, iclass 38, count 2 2006.201.07:47:49.36#ibcon#read 6, iclass 38, count 2 2006.201.07:47:49.36#ibcon#end of sib2, iclass 38, count 2 2006.201.07:47:49.36#ibcon#*after write, iclass 38, count 2 2006.201.07:47:49.36#ibcon#*before return 0, iclass 38, count 2 2006.201.07:47:49.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:49.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:49.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.07:47:49.36#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:49.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:49.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:49.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:49.48#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:47:49.48#ibcon#first serial, iclass 38, count 0 2006.201.07:47:49.48#ibcon#enter sib2, iclass 38, count 0 2006.201.07:47:49.48#ibcon#flushed, iclass 38, count 0 2006.201.07:47:49.48#ibcon#about to write, iclass 38, count 0 2006.201.07:47:49.48#ibcon#wrote, iclass 38, count 0 2006.201.07:47:49.48#ibcon#about to read 3, iclass 38, count 0 2006.201.07:47:49.50#ibcon#read 3, iclass 38, count 0 2006.201.07:47:49.50#ibcon#about to read 4, iclass 38, count 0 2006.201.07:47:49.50#ibcon#read 4, iclass 38, count 0 2006.201.07:47:49.50#ibcon#about to read 5, iclass 38, count 0 2006.201.07:47:49.50#ibcon#read 5, iclass 38, count 0 2006.201.07:47:49.50#ibcon#about to read 6, iclass 38, count 0 2006.201.07:47:49.50#ibcon#read 6, iclass 38, count 0 2006.201.07:47:49.50#ibcon#end of sib2, iclass 38, count 0 2006.201.07:47:49.50#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:47:49.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:47:49.50#ibcon#[25=USB\r\n] 2006.201.07:47:49.50#ibcon#*before write, iclass 38, count 0 2006.201.07:47:49.50#ibcon#enter sib2, iclass 38, count 0 2006.201.07:47:49.50#ibcon#flushed, iclass 38, count 0 2006.201.07:47:49.50#ibcon#about to write, iclass 38, count 0 2006.201.07:47:49.50#ibcon#wrote, iclass 38, count 0 2006.201.07:47:49.50#ibcon#about to read 3, iclass 38, count 0 2006.201.07:47:49.53#ibcon#read 3, iclass 38, count 0 2006.201.07:47:49.53#ibcon#about to read 4, iclass 38, count 0 2006.201.07:47:49.53#ibcon#read 4, iclass 38, count 0 2006.201.07:47:49.53#ibcon#about to read 5, iclass 38, count 0 2006.201.07:47:49.53#ibcon#read 5, iclass 38, count 0 2006.201.07:47:49.53#ibcon#about to read 6, iclass 38, count 0 2006.201.07:47:49.53#ibcon#read 6, iclass 38, count 0 2006.201.07:47:49.53#ibcon#end of sib2, iclass 38, count 0 2006.201.07:47:49.53#ibcon#*after write, iclass 38, count 0 2006.201.07:47:49.53#ibcon#*before return 0, iclass 38, count 0 2006.201.07:47:49.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:49.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:49.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:47:49.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:47:49.53$vck44/valo=6,814.99 2006.201.07:47:49.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.07:47:49.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.07:47:49.53#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:49.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:49.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:49.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:49.53#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:47:49.53#ibcon#first serial, iclass 40, count 0 2006.201.07:47:49.53#ibcon#enter sib2, iclass 40, count 0 2006.201.07:47:49.53#ibcon#flushed, iclass 40, count 0 2006.201.07:47:49.53#ibcon#about to write, iclass 40, count 0 2006.201.07:47:49.53#ibcon#wrote, iclass 40, count 0 2006.201.07:47:49.53#ibcon#about to read 3, iclass 40, count 0 2006.201.07:47:49.55#ibcon#read 3, iclass 40, count 0 2006.201.07:47:49.55#ibcon#about to read 4, iclass 40, count 0 2006.201.07:47:49.55#ibcon#read 4, iclass 40, count 0 2006.201.07:47:49.55#ibcon#about to read 5, iclass 40, count 0 2006.201.07:47:49.55#ibcon#read 5, iclass 40, count 0 2006.201.07:47:49.55#ibcon#about to read 6, iclass 40, count 0 2006.201.07:47:49.55#ibcon#read 6, iclass 40, count 0 2006.201.07:47:49.55#ibcon#end of sib2, iclass 40, count 0 2006.201.07:47:49.55#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:47:49.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:47:49.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.07:47:49.55#ibcon#*before write, iclass 40, count 0 2006.201.07:47:49.55#ibcon#enter sib2, iclass 40, count 0 2006.201.07:47:49.55#ibcon#flushed, iclass 40, count 0 2006.201.07:47:49.55#ibcon#about to write, iclass 40, count 0 2006.201.07:47:49.55#ibcon#wrote, iclass 40, count 0 2006.201.07:47:49.55#ibcon#about to read 3, iclass 40, count 0 2006.201.07:47:49.60#ibcon#read 3, iclass 40, count 0 2006.201.07:47:49.60#ibcon#about to read 4, iclass 40, count 0 2006.201.07:47:49.60#ibcon#read 4, iclass 40, count 0 2006.201.07:47:49.60#ibcon#about to read 5, iclass 40, count 0 2006.201.07:47:49.60#ibcon#read 5, iclass 40, count 0 2006.201.07:47:49.60#ibcon#about to read 6, iclass 40, count 0 2006.201.07:47:49.60#ibcon#read 6, iclass 40, count 0 2006.201.07:47:49.60#ibcon#end of sib2, iclass 40, count 0 2006.201.07:47:49.60#ibcon#*after write, iclass 40, count 0 2006.201.07:47:49.60#ibcon#*before return 0, iclass 40, count 0 2006.201.07:47:49.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:49.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:49.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:47:49.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:47:49.60$vck44/va=6,5 2006.201.07:47:49.60#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.07:47:49.60#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.07:47:49.60#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:49.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:49.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:49.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:49.65#ibcon#enter wrdev, iclass 4, count 2 2006.201.07:47:49.65#ibcon#first serial, iclass 4, count 2 2006.201.07:47:49.65#ibcon#enter sib2, iclass 4, count 2 2006.201.07:47:49.65#ibcon#flushed, iclass 4, count 2 2006.201.07:47:49.65#ibcon#about to write, iclass 4, count 2 2006.201.07:47:49.65#ibcon#wrote, iclass 4, count 2 2006.201.07:47:49.65#ibcon#about to read 3, iclass 4, count 2 2006.201.07:47:49.67#ibcon#read 3, iclass 4, count 2 2006.201.07:47:49.67#ibcon#about to read 4, iclass 4, count 2 2006.201.07:47:49.67#ibcon#read 4, iclass 4, count 2 2006.201.07:47:49.67#ibcon#about to read 5, iclass 4, count 2 2006.201.07:47:49.67#ibcon#read 5, iclass 4, count 2 2006.201.07:47:49.67#ibcon#about to read 6, iclass 4, count 2 2006.201.07:47:49.67#ibcon#read 6, iclass 4, count 2 2006.201.07:47:49.67#ibcon#end of sib2, iclass 4, count 2 2006.201.07:47:49.67#ibcon#*mode == 0, iclass 4, count 2 2006.201.07:47:49.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.07:47:49.67#ibcon#[25=AT06-05\r\n] 2006.201.07:47:49.67#ibcon#*before write, iclass 4, count 2 2006.201.07:47:49.67#ibcon#enter sib2, iclass 4, count 2 2006.201.07:47:49.67#ibcon#flushed, iclass 4, count 2 2006.201.07:47:49.67#ibcon#about to write, iclass 4, count 2 2006.201.07:47:49.67#ibcon#wrote, iclass 4, count 2 2006.201.07:47:49.67#ibcon#about to read 3, iclass 4, count 2 2006.201.07:47:49.70#ibcon#read 3, iclass 4, count 2 2006.201.07:47:49.70#ibcon#about to read 4, iclass 4, count 2 2006.201.07:47:49.70#ibcon#read 4, iclass 4, count 2 2006.201.07:47:49.70#ibcon#about to read 5, iclass 4, count 2 2006.201.07:47:49.70#ibcon#read 5, iclass 4, count 2 2006.201.07:47:49.70#ibcon#about to read 6, iclass 4, count 2 2006.201.07:47:49.70#ibcon#read 6, iclass 4, count 2 2006.201.07:47:49.70#ibcon#end of sib2, iclass 4, count 2 2006.201.07:47:49.70#ibcon#*after write, iclass 4, count 2 2006.201.07:47:49.70#ibcon#*before return 0, iclass 4, count 2 2006.201.07:47:49.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:49.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:49.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.07:47:49.70#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:49.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:49.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:49.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:49.82#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:47:49.82#ibcon#first serial, iclass 4, count 0 2006.201.07:47:49.82#ibcon#enter sib2, iclass 4, count 0 2006.201.07:47:49.82#ibcon#flushed, iclass 4, count 0 2006.201.07:47:49.82#ibcon#about to write, iclass 4, count 0 2006.201.07:47:49.82#ibcon#wrote, iclass 4, count 0 2006.201.07:47:49.82#ibcon#about to read 3, iclass 4, count 0 2006.201.07:47:49.84#ibcon#read 3, iclass 4, count 0 2006.201.07:47:49.84#ibcon#about to read 4, iclass 4, count 0 2006.201.07:47:49.84#ibcon#read 4, iclass 4, count 0 2006.201.07:47:49.84#ibcon#about to read 5, iclass 4, count 0 2006.201.07:47:49.84#ibcon#read 5, iclass 4, count 0 2006.201.07:47:49.84#ibcon#about to read 6, iclass 4, count 0 2006.201.07:47:49.84#ibcon#read 6, iclass 4, count 0 2006.201.07:47:49.84#ibcon#end of sib2, iclass 4, count 0 2006.201.07:47:49.84#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:47:49.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:47:49.84#ibcon#[25=USB\r\n] 2006.201.07:47:49.84#ibcon#*before write, iclass 4, count 0 2006.201.07:47:49.84#ibcon#enter sib2, iclass 4, count 0 2006.201.07:47:49.84#ibcon#flushed, iclass 4, count 0 2006.201.07:47:49.84#ibcon#about to write, iclass 4, count 0 2006.201.07:47:49.84#ibcon#wrote, iclass 4, count 0 2006.201.07:47:49.84#ibcon#about to read 3, iclass 4, count 0 2006.201.07:47:49.87#ibcon#read 3, iclass 4, count 0 2006.201.07:47:49.87#ibcon#about to read 4, iclass 4, count 0 2006.201.07:47:49.87#ibcon#read 4, iclass 4, count 0 2006.201.07:47:49.87#ibcon#about to read 5, iclass 4, count 0 2006.201.07:47:49.87#ibcon#read 5, iclass 4, count 0 2006.201.07:47:49.87#ibcon#about to read 6, iclass 4, count 0 2006.201.07:47:49.87#ibcon#read 6, iclass 4, count 0 2006.201.07:47:49.87#ibcon#end of sib2, iclass 4, count 0 2006.201.07:47:49.87#ibcon#*after write, iclass 4, count 0 2006.201.07:47:49.87#ibcon#*before return 0, iclass 4, count 0 2006.201.07:47:49.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:49.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:49.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:47:49.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:47:49.87$vck44/valo=7,864.99 2006.201.07:47:49.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.07:47:49.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.07:47:49.87#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:49.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:49.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:49.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:49.87#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:47:49.87#ibcon#first serial, iclass 6, count 0 2006.201.07:47:49.87#ibcon#enter sib2, iclass 6, count 0 2006.201.07:47:49.87#ibcon#flushed, iclass 6, count 0 2006.201.07:47:49.87#ibcon#about to write, iclass 6, count 0 2006.201.07:47:49.87#ibcon#wrote, iclass 6, count 0 2006.201.07:47:49.87#ibcon#about to read 3, iclass 6, count 0 2006.201.07:47:49.89#ibcon#read 3, iclass 6, count 0 2006.201.07:47:49.89#ibcon#about to read 4, iclass 6, count 0 2006.201.07:47:49.89#ibcon#read 4, iclass 6, count 0 2006.201.07:47:49.89#ibcon#about to read 5, iclass 6, count 0 2006.201.07:47:49.89#ibcon#read 5, iclass 6, count 0 2006.201.07:47:49.89#ibcon#about to read 6, iclass 6, count 0 2006.201.07:47:49.89#ibcon#read 6, iclass 6, count 0 2006.201.07:47:49.89#ibcon#end of sib2, iclass 6, count 0 2006.201.07:47:49.89#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:47:49.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:47:49.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.07:47:49.89#ibcon#*before write, iclass 6, count 0 2006.201.07:47:49.89#ibcon#enter sib2, iclass 6, count 0 2006.201.07:47:49.89#ibcon#flushed, iclass 6, count 0 2006.201.07:47:49.89#ibcon#about to write, iclass 6, count 0 2006.201.07:47:49.89#ibcon#wrote, iclass 6, count 0 2006.201.07:47:49.89#ibcon#about to read 3, iclass 6, count 0 2006.201.07:47:49.94#ibcon#read 3, iclass 6, count 0 2006.201.07:47:49.94#ibcon#about to read 4, iclass 6, count 0 2006.201.07:47:49.94#ibcon#read 4, iclass 6, count 0 2006.201.07:47:49.94#ibcon#about to read 5, iclass 6, count 0 2006.201.07:47:49.94#ibcon#read 5, iclass 6, count 0 2006.201.07:47:49.94#ibcon#about to read 6, iclass 6, count 0 2006.201.07:47:49.94#ibcon#read 6, iclass 6, count 0 2006.201.07:47:49.94#ibcon#end of sib2, iclass 6, count 0 2006.201.07:47:49.94#ibcon#*after write, iclass 6, count 0 2006.201.07:47:49.94#ibcon#*before return 0, iclass 6, count 0 2006.201.07:47:49.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:49.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:49.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:47:49.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:47:49.94$vck44/va=7,5 2006.201.07:47:49.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.07:47:49.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.07:47:49.94#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:49.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:49.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:49.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:49.99#ibcon#enter wrdev, iclass 10, count 2 2006.201.07:47:49.99#ibcon#first serial, iclass 10, count 2 2006.201.07:47:49.99#ibcon#enter sib2, iclass 10, count 2 2006.201.07:47:49.99#ibcon#flushed, iclass 10, count 2 2006.201.07:47:49.99#ibcon#about to write, iclass 10, count 2 2006.201.07:47:49.99#ibcon#wrote, iclass 10, count 2 2006.201.07:47:49.99#ibcon#about to read 3, iclass 10, count 2 2006.201.07:47:50.01#ibcon#read 3, iclass 10, count 2 2006.201.07:47:50.01#ibcon#about to read 4, iclass 10, count 2 2006.201.07:47:50.01#ibcon#read 4, iclass 10, count 2 2006.201.07:47:50.01#ibcon#about to read 5, iclass 10, count 2 2006.201.07:47:50.01#ibcon#read 5, iclass 10, count 2 2006.201.07:47:50.01#ibcon#about to read 6, iclass 10, count 2 2006.201.07:47:50.01#ibcon#read 6, iclass 10, count 2 2006.201.07:47:50.01#ibcon#end of sib2, iclass 10, count 2 2006.201.07:47:50.01#ibcon#*mode == 0, iclass 10, count 2 2006.201.07:47:50.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.07:47:50.01#ibcon#[25=AT07-05\r\n] 2006.201.07:47:50.01#ibcon#*before write, iclass 10, count 2 2006.201.07:47:50.01#ibcon#enter sib2, iclass 10, count 2 2006.201.07:47:50.01#ibcon#flushed, iclass 10, count 2 2006.201.07:47:50.01#ibcon#about to write, iclass 10, count 2 2006.201.07:47:50.01#ibcon#wrote, iclass 10, count 2 2006.201.07:47:50.01#ibcon#about to read 3, iclass 10, count 2 2006.201.07:47:50.04#ibcon#read 3, iclass 10, count 2 2006.201.07:47:50.04#ibcon#about to read 4, iclass 10, count 2 2006.201.07:47:50.04#ibcon#read 4, iclass 10, count 2 2006.201.07:47:50.04#ibcon#about to read 5, iclass 10, count 2 2006.201.07:47:50.04#ibcon#read 5, iclass 10, count 2 2006.201.07:47:50.04#ibcon#about to read 6, iclass 10, count 2 2006.201.07:47:50.04#ibcon#read 6, iclass 10, count 2 2006.201.07:47:50.04#ibcon#end of sib2, iclass 10, count 2 2006.201.07:47:50.04#ibcon#*after write, iclass 10, count 2 2006.201.07:47:50.04#ibcon#*before return 0, iclass 10, count 2 2006.201.07:47:50.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:50.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:50.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.07:47:50.04#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:50.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:50.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:50.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:50.16#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:47:50.16#ibcon#first serial, iclass 10, count 0 2006.201.07:47:50.16#ibcon#enter sib2, iclass 10, count 0 2006.201.07:47:50.16#ibcon#flushed, iclass 10, count 0 2006.201.07:47:50.16#ibcon#about to write, iclass 10, count 0 2006.201.07:47:50.16#ibcon#wrote, iclass 10, count 0 2006.201.07:47:50.16#ibcon#about to read 3, iclass 10, count 0 2006.201.07:47:50.18#ibcon#read 3, iclass 10, count 0 2006.201.07:47:50.18#ibcon#about to read 4, iclass 10, count 0 2006.201.07:47:50.18#ibcon#read 4, iclass 10, count 0 2006.201.07:47:50.18#ibcon#about to read 5, iclass 10, count 0 2006.201.07:47:50.18#ibcon#read 5, iclass 10, count 0 2006.201.07:47:50.18#ibcon#about to read 6, iclass 10, count 0 2006.201.07:47:50.18#ibcon#read 6, iclass 10, count 0 2006.201.07:47:50.18#ibcon#end of sib2, iclass 10, count 0 2006.201.07:47:50.18#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:47:50.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:47:50.18#ibcon#[25=USB\r\n] 2006.201.07:47:50.18#ibcon#*before write, iclass 10, count 0 2006.201.07:47:50.18#ibcon#enter sib2, iclass 10, count 0 2006.201.07:47:50.18#ibcon#flushed, iclass 10, count 0 2006.201.07:47:50.18#ibcon#about to write, iclass 10, count 0 2006.201.07:47:50.18#ibcon#wrote, iclass 10, count 0 2006.201.07:47:50.18#ibcon#about to read 3, iclass 10, count 0 2006.201.07:47:50.21#ibcon#read 3, iclass 10, count 0 2006.201.07:47:50.21#ibcon#about to read 4, iclass 10, count 0 2006.201.07:47:50.21#ibcon#read 4, iclass 10, count 0 2006.201.07:47:50.21#ibcon#about to read 5, iclass 10, count 0 2006.201.07:47:50.21#ibcon#read 5, iclass 10, count 0 2006.201.07:47:50.21#ibcon#about to read 6, iclass 10, count 0 2006.201.07:47:50.21#ibcon#read 6, iclass 10, count 0 2006.201.07:47:50.21#ibcon#end of sib2, iclass 10, count 0 2006.201.07:47:50.21#ibcon#*after write, iclass 10, count 0 2006.201.07:47:50.21#ibcon#*before return 0, iclass 10, count 0 2006.201.07:47:50.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:50.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:50.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:47:50.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:47:50.21$vck44/valo=8,884.99 2006.201.07:47:50.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.07:47:50.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.07:47:50.21#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:50.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:50.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:50.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:50.21#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:47:50.21#ibcon#first serial, iclass 12, count 0 2006.201.07:47:50.21#ibcon#enter sib2, iclass 12, count 0 2006.201.07:47:50.21#ibcon#flushed, iclass 12, count 0 2006.201.07:47:50.21#ibcon#about to write, iclass 12, count 0 2006.201.07:47:50.21#ibcon#wrote, iclass 12, count 0 2006.201.07:47:50.21#ibcon#about to read 3, iclass 12, count 0 2006.201.07:47:50.23#ibcon#read 3, iclass 12, count 0 2006.201.07:47:50.23#ibcon#about to read 4, iclass 12, count 0 2006.201.07:47:50.23#ibcon#read 4, iclass 12, count 0 2006.201.07:47:50.23#ibcon#about to read 5, iclass 12, count 0 2006.201.07:47:50.23#ibcon#read 5, iclass 12, count 0 2006.201.07:47:50.23#ibcon#about to read 6, iclass 12, count 0 2006.201.07:47:50.23#ibcon#read 6, iclass 12, count 0 2006.201.07:47:50.23#ibcon#end of sib2, iclass 12, count 0 2006.201.07:47:50.23#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:47:50.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:47:50.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.07:47:50.23#ibcon#*before write, iclass 12, count 0 2006.201.07:47:50.23#ibcon#enter sib2, iclass 12, count 0 2006.201.07:47:50.23#ibcon#flushed, iclass 12, count 0 2006.201.07:47:50.23#ibcon#about to write, iclass 12, count 0 2006.201.07:47:50.23#ibcon#wrote, iclass 12, count 0 2006.201.07:47:50.23#ibcon#about to read 3, iclass 12, count 0 2006.201.07:47:50.27#ibcon#read 3, iclass 12, count 0 2006.201.07:47:50.27#ibcon#about to read 4, iclass 12, count 0 2006.201.07:47:50.27#ibcon#read 4, iclass 12, count 0 2006.201.07:47:50.27#ibcon#about to read 5, iclass 12, count 0 2006.201.07:47:50.27#ibcon#read 5, iclass 12, count 0 2006.201.07:47:50.27#ibcon#about to read 6, iclass 12, count 0 2006.201.07:47:50.27#ibcon#read 6, iclass 12, count 0 2006.201.07:47:50.27#ibcon#end of sib2, iclass 12, count 0 2006.201.07:47:50.27#ibcon#*after write, iclass 12, count 0 2006.201.07:47:50.27#ibcon#*before return 0, iclass 12, count 0 2006.201.07:47:50.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:50.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:50.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:47:50.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:47:50.27$vck44/va=8,4 2006.201.07:47:50.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.07:47:50.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.07:47:50.27#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:50.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:47:50.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:47:50.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:47:50.33#ibcon#enter wrdev, iclass 14, count 2 2006.201.07:47:50.33#ibcon#first serial, iclass 14, count 2 2006.201.07:47:50.33#ibcon#enter sib2, iclass 14, count 2 2006.201.07:47:50.33#ibcon#flushed, iclass 14, count 2 2006.201.07:47:50.33#ibcon#about to write, iclass 14, count 2 2006.201.07:47:50.33#ibcon#wrote, iclass 14, count 2 2006.201.07:47:50.33#ibcon#about to read 3, iclass 14, count 2 2006.201.07:47:50.35#ibcon#read 3, iclass 14, count 2 2006.201.07:47:50.35#ibcon#about to read 4, iclass 14, count 2 2006.201.07:47:50.35#ibcon#read 4, iclass 14, count 2 2006.201.07:47:50.35#ibcon#about to read 5, iclass 14, count 2 2006.201.07:47:50.35#ibcon#read 5, iclass 14, count 2 2006.201.07:47:50.35#ibcon#about to read 6, iclass 14, count 2 2006.201.07:47:50.35#ibcon#read 6, iclass 14, count 2 2006.201.07:47:50.35#ibcon#end of sib2, iclass 14, count 2 2006.201.07:47:50.35#ibcon#*mode == 0, iclass 14, count 2 2006.201.07:47:50.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.07:47:50.35#ibcon#[25=AT08-04\r\n] 2006.201.07:47:50.35#ibcon#*before write, iclass 14, count 2 2006.201.07:47:50.35#ibcon#enter sib2, iclass 14, count 2 2006.201.07:47:50.35#ibcon#flushed, iclass 14, count 2 2006.201.07:47:50.35#ibcon#about to write, iclass 14, count 2 2006.201.07:47:50.35#ibcon#wrote, iclass 14, count 2 2006.201.07:47:50.35#ibcon#about to read 3, iclass 14, count 2 2006.201.07:47:50.38#ibcon#read 3, iclass 14, count 2 2006.201.07:47:50.38#ibcon#about to read 4, iclass 14, count 2 2006.201.07:47:50.38#ibcon#read 4, iclass 14, count 2 2006.201.07:47:50.38#ibcon#about to read 5, iclass 14, count 2 2006.201.07:47:50.38#ibcon#read 5, iclass 14, count 2 2006.201.07:47:50.38#ibcon#about to read 6, iclass 14, count 2 2006.201.07:47:50.38#ibcon#read 6, iclass 14, count 2 2006.201.07:47:50.38#ibcon#end of sib2, iclass 14, count 2 2006.201.07:47:50.38#ibcon#*after write, iclass 14, count 2 2006.201.07:47:50.38#ibcon#*before return 0, iclass 14, count 2 2006.201.07:47:50.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:47:50.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.07:47:50.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.07:47:50.38#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:50.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:47:50.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:47:50.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:47:50.50#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:47:50.50#ibcon#first serial, iclass 14, count 0 2006.201.07:47:50.50#ibcon#enter sib2, iclass 14, count 0 2006.201.07:47:50.50#ibcon#flushed, iclass 14, count 0 2006.201.07:47:50.50#ibcon#about to write, iclass 14, count 0 2006.201.07:47:50.50#ibcon#wrote, iclass 14, count 0 2006.201.07:47:50.50#ibcon#about to read 3, iclass 14, count 0 2006.201.07:47:50.52#ibcon#read 3, iclass 14, count 0 2006.201.07:47:50.52#ibcon#about to read 4, iclass 14, count 0 2006.201.07:47:50.52#ibcon#read 4, iclass 14, count 0 2006.201.07:47:50.52#ibcon#about to read 5, iclass 14, count 0 2006.201.07:47:50.52#ibcon#read 5, iclass 14, count 0 2006.201.07:47:50.52#ibcon#about to read 6, iclass 14, count 0 2006.201.07:47:50.52#ibcon#read 6, iclass 14, count 0 2006.201.07:47:50.52#ibcon#end of sib2, iclass 14, count 0 2006.201.07:47:50.52#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:47:50.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:47:50.52#ibcon#[25=USB\r\n] 2006.201.07:47:50.52#ibcon#*before write, iclass 14, count 0 2006.201.07:47:50.52#ibcon#enter sib2, iclass 14, count 0 2006.201.07:47:50.52#ibcon#flushed, iclass 14, count 0 2006.201.07:47:50.52#ibcon#about to write, iclass 14, count 0 2006.201.07:47:50.52#ibcon#wrote, iclass 14, count 0 2006.201.07:47:50.52#ibcon#about to read 3, iclass 14, count 0 2006.201.07:47:50.55#ibcon#read 3, iclass 14, count 0 2006.201.07:47:50.55#ibcon#about to read 4, iclass 14, count 0 2006.201.07:47:50.55#ibcon#read 4, iclass 14, count 0 2006.201.07:47:50.55#ibcon#about to read 5, iclass 14, count 0 2006.201.07:47:50.55#ibcon#read 5, iclass 14, count 0 2006.201.07:47:50.55#ibcon#about to read 6, iclass 14, count 0 2006.201.07:47:50.55#ibcon#read 6, iclass 14, count 0 2006.201.07:47:50.55#ibcon#end of sib2, iclass 14, count 0 2006.201.07:47:50.55#ibcon#*after write, iclass 14, count 0 2006.201.07:47:50.55#ibcon#*before return 0, iclass 14, count 0 2006.201.07:47:50.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:47:50.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.07:47:50.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:47:50.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:47:50.55$vck44/vblo=1,629.99 2006.201.07:47:50.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.07:47:50.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.07:47:50.55#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:50.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:47:50.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:47:50.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:47:50.55#ibcon#enter wrdev, iclass 16, count 0 2006.201.07:47:50.55#ibcon#first serial, iclass 16, count 0 2006.201.07:47:50.55#ibcon#enter sib2, iclass 16, count 0 2006.201.07:47:50.55#ibcon#flushed, iclass 16, count 0 2006.201.07:47:50.55#ibcon#about to write, iclass 16, count 0 2006.201.07:47:50.55#ibcon#wrote, iclass 16, count 0 2006.201.07:47:50.55#ibcon#about to read 3, iclass 16, count 0 2006.201.07:47:50.57#ibcon#read 3, iclass 16, count 0 2006.201.07:47:50.57#ibcon#about to read 4, iclass 16, count 0 2006.201.07:47:50.57#ibcon#read 4, iclass 16, count 0 2006.201.07:47:50.57#ibcon#about to read 5, iclass 16, count 0 2006.201.07:47:50.57#ibcon#read 5, iclass 16, count 0 2006.201.07:47:50.57#ibcon#about to read 6, iclass 16, count 0 2006.201.07:47:50.57#ibcon#read 6, iclass 16, count 0 2006.201.07:47:50.57#ibcon#end of sib2, iclass 16, count 0 2006.201.07:47:50.57#ibcon#*mode == 0, iclass 16, count 0 2006.201.07:47:50.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.07:47:50.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.07:47:50.57#ibcon#*before write, iclass 16, count 0 2006.201.07:47:50.57#ibcon#enter sib2, iclass 16, count 0 2006.201.07:47:50.57#ibcon#flushed, iclass 16, count 0 2006.201.07:47:50.57#ibcon#about to write, iclass 16, count 0 2006.201.07:47:50.57#ibcon#wrote, iclass 16, count 0 2006.201.07:47:50.57#ibcon#about to read 3, iclass 16, count 0 2006.201.07:47:50.61#ibcon#read 3, iclass 16, count 0 2006.201.07:47:50.61#ibcon#about to read 4, iclass 16, count 0 2006.201.07:47:50.61#ibcon#read 4, iclass 16, count 0 2006.201.07:47:50.61#ibcon#about to read 5, iclass 16, count 0 2006.201.07:47:50.61#ibcon#read 5, iclass 16, count 0 2006.201.07:47:50.61#ibcon#about to read 6, iclass 16, count 0 2006.201.07:47:50.61#ibcon#read 6, iclass 16, count 0 2006.201.07:47:50.61#ibcon#end of sib2, iclass 16, count 0 2006.201.07:47:50.61#ibcon#*after write, iclass 16, count 0 2006.201.07:47:50.61#ibcon#*before return 0, iclass 16, count 0 2006.201.07:47:50.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:47:50.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.07:47:50.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.07:47:50.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.07:47:50.61$vck44/vb=1,4 2006.201.07:47:50.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.07:47:50.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.07:47:50.61#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:50.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:47:50.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:47:50.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:47:50.61#ibcon#enter wrdev, iclass 18, count 2 2006.201.07:47:50.61#ibcon#first serial, iclass 18, count 2 2006.201.07:47:50.61#ibcon#enter sib2, iclass 18, count 2 2006.201.07:47:50.61#ibcon#flushed, iclass 18, count 2 2006.201.07:47:50.61#ibcon#about to write, iclass 18, count 2 2006.201.07:47:50.61#ibcon#wrote, iclass 18, count 2 2006.201.07:47:50.61#ibcon#about to read 3, iclass 18, count 2 2006.201.07:47:50.63#ibcon#read 3, iclass 18, count 2 2006.201.07:47:50.63#ibcon#about to read 4, iclass 18, count 2 2006.201.07:47:50.63#ibcon#read 4, iclass 18, count 2 2006.201.07:47:50.63#ibcon#about to read 5, iclass 18, count 2 2006.201.07:47:50.63#ibcon#read 5, iclass 18, count 2 2006.201.07:47:50.63#ibcon#about to read 6, iclass 18, count 2 2006.201.07:47:50.63#ibcon#read 6, iclass 18, count 2 2006.201.07:47:50.63#ibcon#end of sib2, iclass 18, count 2 2006.201.07:47:50.63#ibcon#*mode == 0, iclass 18, count 2 2006.201.07:47:50.63#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.07:47:50.63#ibcon#[27=AT01-04\r\n] 2006.201.07:47:50.63#ibcon#*before write, iclass 18, count 2 2006.201.07:47:50.63#ibcon#enter sib2, iclass 18, count 2 2006.201.07:47:50.63#ibcon#flushed, iclass 18, count 2 2006.201.07:47:50.63#ibcon#about to write, iclass 18, count 2 2006.201.07:47:50.63#ibcon#wrote, iclass 18, count 2 2006.201.07:47:50.63#ibcon#about to read 3, iclass 18, count 2 2006.201.07:47:50.66#ibcon#read 3, iclass 18, count 2 2006.201.07:47:50.66#ibcon#about to read 4, iclass 18, count 2 2006.201.07:47:50.66#ibcon#read 4, iclass 18, count 2 2006.201.07:47:50.66#ibcon#about to read 5, iclass 18, count 2 2006.201.07:47:50.66#ibcon#read 5, iclass 18, count 2 2006.201.07:47:50.66#ibcon#about to read 6, iclass 18, count 2 2006.201.07:47:50.66#ibcon#read 6, iclass 18, count 2 2006.201.07:47:50.66#ibcon#end of sib2, iclass 18, count 2 2006.201.07:47:50.66#ibcon#*after write, iclass 18, count 2 2006.201.07:47:50.66#ibcon#*before return 0, iclass 18, count 2 2006.201.07:47:50.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:47:50.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.07:47:50.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.07:47:50.66#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:50.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:47:50.78#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:47:50.78#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:47:50.78#ibcon#enter wrdev, iclass 18, count 0 2006.201.07:47:50.78#ibcon#first serial, iclass 18, count 0 2006.201.07:47:50.78#ibcon#enter sib2, iclass 18, count 0 2006.201.07:47:50.78#ibcon#flushed, iclass 18, count 0 2006.201.07:47:50.78#ibcon#about to write, iclass 18, count 0 2006.201.07:47:50.78#ibcon#wrote, iclass 18, count 0 2006.201.07:47:50.78#ibcon#about to read 3, iclass 18, count 0 2006.201.07:47:50.80#ibcon#read 3, iclass 18, count 0 2006.201.07:47:50.80#ibcon#about to read 4, iclass 18, count 0 2006.201.07:47:50.80#ibcon#read 4, iclass 18, count 0 2006.201.07:47:50.80#ibcon#about to read 5, iclass 18, count 0 2006.201.07:47:50.80#ibcon#read 5, iclass 18, count 0 2006.201.07:47:50.80#ibcon#about to read 6, iclass 18, count 0 2006.201.07:47:50.80#ibcon#read 6, iclass 18, count 0 2006.201.07:47:50.80#ibcon#end of sib2, iclass 18, count 0 2006.201.07:47:50.80#ibcon#*mode == 0, iclass 18, count 0 2006.201.07:47:50.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.07:47:50.80#ibcon#[27=USB\r\n] 2006.201.07:47:50.80#ibcon#*before write, iclass 18, count 0 2006.201.07:47:50.80#ibcon#enter sib2, iclass 18, count 0 2006.201.07:47:50.80#ibcon#flushed, iclass 18, count 0 2006.201.07:47:50.80#ibcon#about to write, iclass 18, count 0 2006.201.07:47:50.80#ibcon#wrote, iclass 18, count 0 2006.201.07:47:50.80#ibcon#about to read 3, iclass 18, count 0 2006.201.07:47:50.83#ibcon#read 3, iclass 18, count 0 2006.201.07:47:50.83#ibcon#about to read 4, iclass 18, count 0 2006.201.07:47:50.83#ibcon#read 4, iclass 18, count 0 2006.201.07:47:50.83#ibcon#about to read 5, iclass 18, count 0 2006.201.07:47:50.83#ibcon#read 5, iclass 18, count 0 2006.201.07:47:50.83#ibcon#about to read 6, iclass 18, count 0 2006.201.07:47:50.83#ibcon#read 6, iclass 18, count 0 2006.201.07:47:50.83#ibcon#end of sib2, iclass 18, count 0 2006.201.07:47:50.83#ibcon#*after write, iclass 18, count 0 2006.201.07:47:50.83#ibcon#*before return 0, iclass 18, count 0 2006.201.07:47:50.83#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:47:50.83#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.07:47:50.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.07:47:50.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.07:47:50.83$vck44/vblo=2,634.99 2006.201.07:47:50.83#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.07:47:50.83#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.07:47:50.83#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:50.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:50.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:50.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:50.83#ibcon#enter wrdev, iclass 20, count 0 2006.201.07:47:50.83#ibcon#first serial, iclass 20, count 0 2006.201.07:47:50.83#ibcon#enter sib2, iclass 20, count 0 2006.201.07:47:50.83#ibcon#flushed, iclass 20, count 0 2006.201.07:47:50.83#ibcon#about to write, iclass 20, count 0 2006.201.07:47:50.83#ibcon#wrote, iclass 20, count 0 2006.201.07:47:50.83#ibcon#about to read 3, iclass 20, count 0 2006.201.07:47:50.85#ibcon#read 3, iclass 20, count 0 2006.201.07:47:50.85#ibcon#about to read 4, iclass 20, count 0 2006.201.07:47:50.85#ibcon#read 4, iclass 20, count 0 2006.201.07:47:50.85#ibcon#about to read 5, iclass 20, count 0 2006.201.07:47:50.85#ibcon#read 5, iclass 20, count 0 2006.201.07:47:50.85#ibcon#about to read 6, iclass 20, count 0 2006.201.07:47:50.85#ibcon#read 6, iclass 20, count 0 2006.201.07:47:50.85#ibcon#end of sib2, iclass 20, count 0 2006.201.07:47:50.85#ibcon#*mode == 0, iclass 20, count 0 2006.201.07:47:50.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.07:47:50.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.07:47:50.85#ibcon#*before write, iclass 20, count 0 2006.201.07:47:50.85#ibcon#enter sib2, iclass 20, count 0 2006.201.07:47:50.85#ibcon#flushed, iclass 20, count 0 2006.201.07:47:50.85#ibcon#about to write, iclass 20, count 0 2006.201.07:47:50.85#ibcon#wrote, iclass 20, count 0 2006.201.07:47:50.85#ibcon#about to read 3, iclass 20, count 0 2006.201.07:47:50.90#ibcon#read 3, iclass 20, count 0 2006.201.07:47:50.90#ibcon#about to read 4, iclass 20, count 0 2006.201.07:47:50.90#ibcon#read 4, iclass 20, count 0 2006.201.07:47:50.90#ibcon#about to read 5, iclass 20, count 0 2006.201.07:47:50.90#ibcon#read 5, iclass 20, count 0 2006.201.07:47:50.90#ibcon#about to read 6, iclass 20, count 0 2006.201.07:47:50.90#ibcon#read 6, iclass 20, count 0 2006.201.07:47:50.90#ibcon#end of sib2, iclass 20, count 0 2006.201.07:47:50.90#ibcon#*after write, iclass 20, count 0 2006.201.07:47:50.90#ibcon#*before return 0, iclass 20, count 0 2006.201.07:47:50.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:50.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.07:47:50.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.07:47:50.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.07:47:50.90$vck44/vb=2,5 2006.201.07:47:50.90#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.07:47:50.90#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.07:47:50.90#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:50.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:50.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:50.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:50.95#ibcon#enter wrdev, iclass 22, count 2 2006.201.07:47:50.95#ibcon#first serial, iclass 22, count 2 2006.201.07:47:50.95#ibcon#enter sib2, iclass 22, count 2 2006.201.07:47:50.95#ibcon#flushed, iclass 22, count 2 2006.201.07:47:50.95#ibcon#about to write, iclass 22, count 2 2006.201.07:47:50.95#ibcon#wrote, iclass 22, count 2 2006.201.07:47:50.95#ibcon#about to read 3, iclass 22, count 2 2006.201.07:47:50.97#ibcon#read 3, iclass 22, count 2 2006.201.07:47:50.97#ibcon#about to read 4, iclass 22, count 2 2006.201.07:47:50.97#ibcon#read 4, iclass 22, count 2 2006.201.07:47:50.97#ibcon#about to read 5, iclass 22, count 2 2006.201.07:47:50.97#ibcon#read 5, iclass 22, count 2 2006.201.07:47:50.97#ibcon#about to read 6, iclass 22, count 2 2006.201.07:47:50.97#ibcon#read 6, iclass 22, count 2 2006.201.07:47:50.97#ibcon#end of sib2, iclass 22, count 2 2006.201.07:47:50.97#ibcon#*mode == 0, iclass 22, count 2 2006.201.07:47:50.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.07:47:50.97#ibcon#[27=AT02-05\r\n] 2006.201.07:47:50.97#ibcon#*before write, iclass 22, count 2 2006.201.07:47:50.97#ibcon#enter sib2, iclass 22, count 2 2006.201.07:47:50.97#ibcon#flushed, iclass 22, count 2 2006.201.07:47:50.97#ibcon#about to write, iclass 22, count 2 2006.201.07:47:50.97#ibcon#wrote, iclass 22, count 2 2006.201.07:47:50.97#ibcon#about to read 3, iclass 22, count 2 2006.201.07:47:51.00#ibcon#read 3, iclass 22, count 2 2006.201.07:47:51.00#ibcon#about to read 4, iclass 22, count 2 2006.201.07:47:51.00#ibcon#read 4, iclass 22, count 2 2006.201.07:47:51.00#ibcon#about to read 5, iclass 22, count 2 2006.201.07:47:51.00#ibcon#read 5, iclass 22, count 2 2006.201.07:47:51.00#ibcon#about to read 6, iclass 22, count 2 2006.201.07:47:51.00#ibcon#read 6, iclass 22, count 2 2006.201.07:47:51.00#ibcon#end of sib2, iclass 22, count 2 2006.201.07:47:51.00#ibcon#*after write, iclass 22, count 2 2006.201.07:47:51.00#ibcon#*before return 0, iclass 22, count 2 2006.201.07:47:51.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:51.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.07:47:51.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.07:47:51.00#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:51.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:51.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:51.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:51.12#ibcon#enter wrdev, iclass 22, count 0 2006.201.07:47:51.12#ibcon#first serial, iclass 22, count 0 2006.201.07:47:51.12#ibcon#enter sib2, iclass 22, count 0 2006.201.07:47:51.12#ibcon#flushed, iclass 22, count 0 2006.201.07:47:51.12#ibcon#about to write, iclass 22, count 0 2006.201.07:47:51.12#ibcon#wrote, iclass 22, count 0 2006.201.07:47:51.12#ibcon#about to read 3, iclass 22, count 0 2006.201.07:47:51.14#ibcon#read 3, iclass 22, count 0 2006.201.07:47:51.14#ibcon#about to read 4, iclass 22, count 0 2006.201.07:47:51.14#ibcon#read 4, iclass 22, count 0 2006.201.07:47:51.14#ibcon#about to read 5, iclass 22, count 0 2006.201.07:47:51.14#ibcon#read 5, iclass 22, count 0 2006.201.07:47:51.14#ibcon#about to read 6, iclass 22, count 0 2006.201.07:47:51.14#ibcon#read 6, iclass 22, count 0 2006.201.07:47:51.14#ibcon#end of sib2, iclass 22, count 0 2006.201.07:47:51.14#ibcon#*mode == 0, iclass 22, count 0 2006.201.07:47:51.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.07:47:51.14#ibcon#[27=USB\r\n] 2006.201.07:47:51.14#ibcon#*before write, iclass 22, count 0 2006.201.07:47:51.14#ibcon#enter sib2, iclass 22, count 0 2006.201.07:47:51.14#ibcon#flushed, iclass 22, count 0 2006.201.07:47:51.14#ibcon#about to write, iclass 22, count 0 2006.201.07:47:51.14#ibcon#wrote, iclass 22, count 0 2006.201.07:47:51.14#ibcon#about to read 3, iclass 22, count 0 2006.201.07:47:51.17#ibcon#read 3, iclass 22, count 0 2006.201.07:47:51.17#ibcon#about to read 4, iclass 22, count 0 2006.201.07:47:51.17#ibcon#read 4, iclass 22, count 0 2006.201.07:47:51.17#ibcon#about to read 5, iclass 22, count 0 2006.201.07:47:51.17#ibcon#read 5, iclass 22, count 0 2006.201.07:47:51.17#ibcon#about to read 6, iclass 22, count 0 2006.201.07:47:51.17#ibcon#read 6, iclass 22, count 0 2006.201.07:47:51.17#ibcon#end of sib2, iclass 22, count 0 2006.201.07:47:51.17#ibcon#*after write, iclass 22, count 0 2006.201.07:47:51.17#ibcon#*before return 0, iclass 22, count 0 2006.201.07:47:51.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:51.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.07:47:51.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.07:47:51.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.07:47:51.17$vck44/vblo=3,649.99 2006.201.07:47:51.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.07:47:51.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.07:47:51.17#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:51.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:51.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:51.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:51.17#ibcon#enter wrdev, iclass 24, count 0 2006.201.07:47:51.17#ibcon#first serial, iclass 24, count 0 2006.201.07:47:51.17#ibcon#enter sib2, iclass 24, count 0 2006.201.07:47:51.17#ibcon#flushed, iclass 24, count 0 2006.201.07:47:51.17#ibcon#about to write, iclass 24, count 0 2006.201.07:47:51.17#ibcon#wrote, iclass 24, count 0 2006.201.07:47:51.17#ibcon#about to read 3, iclass 24, count 0 2006.201.07:47:51.19#ibcon#read 3, iclass 24, count 0 2006.201.07:47:51.19#ibcon#about to read 4, iclass 24, count 0 2006.201.07:47:51.19#ibcon#read 4, iclass 24, count 0 2006.201.07:47:51.19#ibcon#about to read 5, iclass 24, count 0 2006.201.07:47:51.19#ibcon#read 5, iclass 24, count 0 2006.201.07:47:51.19#ibcon#about to read 6, iclass 24, count 0 2006.201.07:47:51.19#ibcon#read 6, iclass 24, count 0 2006.201.07:47:51.19#ibcon#end of sib2, iclass 24, count 0 2006.201.07:47:51.19#ibcon#*mode == 0, iclass 24, count 0 2006.201.07:47:51.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.07:47:51.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.07:47:51.19#ibcon#*before write, iclass 24, count 0 2006.201.07:47:51.19#ibcon#enter sib2, iclass 24, count 0 2006.201.07:47:51.19#ibcon#flushed, iclass 24, count 0 2006.201.07:47:51.19#ibcon#about to write, iclass 24, count 0 2006.201.07:47:51.19#ibcon#wrote, iclass 24, count 0 2006.201.07:47:51.19#ibcon#about to read 3, iclass 24, count 0 2006.201.07:47:51.24#ibcon#read 3, iclass 24, count 0 2006.201.07:47:51.24#ibcon#about to read 4, iclass 24, count 0 2006.201.07:47:51.24#ibcon#read 4, iclass 24, count 0 2006.201.07:47:51.24#ibcon#about to read 5, iclass 24, count 0 2006.201.07:47:51.24#ibcon#read 5, iclass 24, count 0 2006.201.07:47:51.24#ibcon#about to read 6, iclass 24, count 0 2006.201.07:47:51.24#ibcon#read 6, iclass 24, count 0 2006.201.07:47:51.24#ibcon#end of sib2, iclass 24, count 0 2006.201.07:47:51.24#ibcon#*after write, iclass 24, count 0 2006.201.07:47:51.24#ibcon#*before return 0, iclass 24, count 0 2006.201.07:47:51.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:51.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.07:47:51.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.07:47:51.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.07:47:51.24$vck44/vb=3,4 2006.201.07:47:51.24#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.07:47:51.24#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.07:47:51.24#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:51.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:51.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:51.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:51.29#ibcon#enter wrdev, iclass 26, count 2 2006.201.07:47:51.29#ibcon#first serial, iclass 26, count 2 2006.201.07:47:51.29#ibcon#enter sib2, iclass 26, count 2 2006.201.07:47:51.29#ibcon#flushed, iclass 26, count 2 2006.201.07:47:51.29#ibcon#about to write, iclass 26, count 2 2006.201.07:47:51.29#ibcon#wrote, iclass 26, count 2 2006.201.07:47:51.29#ibcon#about to read 3, iclass 26, count 2 2006.201.07:47:51.31#ibcon#read 3, iclass 26, count 2 2006.201.07:47:51.31#ibcon#about to read 4, iclass 26, count 2 2006.201.07:47:51.31#ibcon#read 4, iclass 26, count 2 2006.201.07:47:51.31#ibcon#about to read 5, iclass 26, count 2 2006.201.07:47:51.31#ibcon#read 5, iclass 26, count 2 2006.201.07:47:51.31#ibcon#about to read 6, iclass 26, count 2 2006.201.07:47:51.31#ibcon#read 6, iclass 26, count 2 2006.201.07:47:51.31#ibcon#end of sib2, iclass 26, count 2 2006.201.07:47:51.31#ibcon#*mode == 0, iclass 26, count 2 2006.201.07:47:51.31#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.07:47:51.31#ibcon#[27=AT03-04\r\n] 2006.201.07:47:51.31#ibcon#*before write, iclass 26, count 2 2006.201.07:47:51.31#ibcon#enter sib2, iclass 26, count 2 2006.201.07:47:51.31#ibcon#flushed, iclass 26, count 2 2006.201.07:47:51.31#ibcon#about to write, iclass 26, count 2 2006.201.07:47:51.31#ibcon#wrote, iclass 26, count 2 2006.201.07:47:51.31#ibcon#about to read 3, iclass 26, count 2 2006.201.07:47:51.34#ibcon#read 3, iclass 26, count 2 2006.201.07:47:51.34#ibcon#about to read 4, iclass 26, count 2 2006.201.07:47:51.34#ibcon#read 4, iclass 26, count 2 2006.201.07:47:51.34#ibcon#about to read 5, iclass 26, count 2 2006.201.07:47:51.34#ibcon#read 5, iclass 26, count 2 2006.201.07:47:51.34#ibcon#about to read 6, iclass 26, count 2 2006.201.07:47:51.34#ibcon#read 6, iclass 26, count 2 2006.201.07:47:51.34#ibcon#end of sib2, iclass 26, count 2 2006.201.07:47:51.34#ibcon#*after write, iclass 26, count 2 2006.201.07:47:51.34#ibcon#*before return 0, iclass 26, count 2 2006.201.07:47:51.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:51.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.07:47:51.34#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.07:47:51.34#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:51.34#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:51.46#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:51.46#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:51.46#ibcon#enter wrdev, iclass 26, count 0 2006.201.07:47:51.46#ibcon#first serial, iclass 26, count 0 2006.201.07:47:51.46#ibcon#enter sib2, iclass 26, count 0 2006.201.07:47:51.46#ibcon#flushed, iclass 26, count 0 2006.201.07:47:51.46#ibcon#about to write, iclass 26, count 0 2006.201.07:47:51.46#ibcon#wrote, iclass 26, count 0 2006.201.07:47:51.46#ibcon#about to read 3, iclass 26, count 0 2006.201.07:47:51.48#ibcon#read 3, iclass 26, count 0 2006.201.07:47:51.48#ibcon#about to read 4, iclass 26, count 0 2006.201.07:47:51.48#ibcon#read 4, iclass 26, count 0 2006.201.07:47:51.48#ibcon#about to read 5, iclass 26, count 0 2006.201.07:47:51.48#ibcon#read 5, iclass 26, count 0 2006.201.07:47:51.48#ibcon#about to read 6, iclass 26, count 0 2006.201.07:47:51.48#ibcon#read 6, iclass 26, count 0 2006.201.07:47:51.48#ibcon#end of sib2, iclass 26, count 0 2006.201.07:47:51.48#ibcon#*mode == 0, iclass 26, count 0 2006.201.07:47:51.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.07:47:51.48#ibcon#[27=USB\r\n] 2006.201.07:47:51.48#ibcon#*before write, iclass 26, count 0 2006.201.07:47:51.48#ibcon#enter sib2, iclass 26, count 0 2006.201.07:47:51.48#ibcon#flushed, iclass 26, count 0 2006.201.07:47:51.48#ibcon#about to write, iclass 26, count 0 2006.201.07:47:51.48#ibcon#wrote, iclass 26, count 0 2006.201.07:47:51.48#ibcon#about to read 3, iclass 26, count 0 2006.201.07:47:51.51#ibcon#read 3, iclass 26, count 0 2006.201.07:47:51.51#ibcon#about to read 4, iclass 26, count 0 2006.201.07:47:51.51#ibcon#read 4, iclass 26, count 0 2006.201.07:47:51.51#ibcon#about to read 5, iclass 26, count 0 2006.201.07:47:51.51#ibcon#read 5, iclass 26, count 0 2006.201.07:47:51.51#ibcon#about to read 6, iclass 26, count 0 2006.201.07:47:51.51#ibcon#read 6, iclass 26, count 0 2006.201.07:47:51.51#ibcon#end of sib2, iclass 26, count 0 2006.201.07:47:51.51#ibcon#*after write, iclass 26, count 0 2006.201.07:47:51.51#ibcon#*before return 0, iclass 26, count 0 2006.201.07:47:51.51#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:51.51#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.07:47:51.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.07:47:51.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.07:47:51.51$vck44/vblo=4,679.99 2006.201.07:47:51.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.07:47:51.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.07:47:51.51#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:51.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:51.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:51.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:51.51#ibcon#enter wrdev, iclass 28, count 0 2006.201.07:47:51.51#ibcon#first serial, iclass 28, count 0 2006.201.07:47:51.51#ibcon#enter sib2, iclass 28, count 0 2006.201.07:47:51.51#ibcon#flushed, iclass 28, count 0 2006.201.07:47:51.51#ibcon#about to write, iclass 28, count 0 2006.201.07:47:51.51#ibcon#wrote, iclass 28, count 0 2006.201.07:47:51.51#ibcon#about to read 3, iclass 28, count 0 2006.201.07:47:51.53#ibcon#read 3, iclass 28, count 0 2006.201.07:47:51.53#ibcon#about to read 4, iclass 28, count 0 2006.201.07:47:51.53#ibcon#read 4, iclass 28, count 0 2006.201.07:47:51.53#ibcon#about to read 5, iclass 28, count 0 2006.201.07:47:51.53#ibcon#read 5, iclass 28, count 0 2006.201.07:47:51.53#ibcon#about to read 6, iclass 28, count 0 2006.201.07:47:51.53#ibcon#read 6, iclass 28, count 0 2006.201.07:47:51.53#ibcon#end of sib2, iclass 28, count 0 2006.201.07:47:51.53#ibcon#*mode == 0, iclass 28, count 0 2006.201.07:47:51.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.07:47:51.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.07:47:51.53#ibcon#*before write, iclass 28, count 0 2006.201.07:47:51.53#ibcon#enter sib2, iclass 28, count 0 2006.201.07:47:51.53#ibcon#flushed, iclass 28, count 0 2006.201.07:47:51.53#ibcon#about to write, iclass 28, count 0 2006.201.07:47:51.53#ibcon#wrote, iclass 28, count 0 2006.201.07:47:51.53#ibcon#about to read 3, iclass 28, count 0 2006.201.07:47:51.57#ibcon#read 3, iclass 28, count 0 2006.201.07:47:51.57#ibcon#about to read 4, iclass 28, count 0 2006.201.07:47:51.57#ibcon#read 4, iclass 28, count 0 2006.201.07:47:51.57#ibcon#about to read 5, iclass 28, count 0 2006.201.07:47:51.57#ibcon#read 5, iclass 28, count 0 2006.201.07:47:51.57#ibcon#about to read 6, iclass 28, count 0 2006.201.07:47:51.57#ibcon#read 6, iclass 28, count 0 2006.201.07:47:51.57#ibcon#end of sib2, iclass 28, count 0 2006.201.07:47:51.57#ibcon#*after write, iclass 28, count 0 2006.201.07:47:51.57#ibcon#*before return 0, iclass 28, count 0 2006.201.07:47:51.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:51.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.07:47:51.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.07:47:51.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.07:47:51.57$vck44/vb=4,5 2006.201.07:47:51.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.07:47:51.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.07:47:51.57#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:51.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:51.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:51.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:51.63#ibcon#enter wrdev, iclass 30, count 2 2006.201.07:47:51.63#ibcon#first serial, iclass 30, count 2 2006.201.07:47:51.63#ibcon#enter sib2, iclass 30, count 2 2006.201.07:47:51.63#ibcon#flushed, iclass 30, count 2 2006.201.07:47:51.63#ibcon#about to write, iclass 30, count 2 2006.201.07:47:51.63#ibcon#wrote, iclass 30, count 2 2006.201.07:47:51.63#ibcon#about to read 3, iclass 30, count 2 2006.201.07:47:51.65#ibcon#read 3, iclass 30, count 2 2006.201.07:47:51.65#ibcon#about to read 4, iclass 30, count 2 2006.201.07:47:51.65#ibcon#read 4, iclass 30, count 2 2006.201.07:47:51.65#ibcon#about to read 5, iclass 30, count 2 2006.201.07:47:51.65#ibcon#read 5, iclass 30, count 2 2006.201.07:47:51.65#ibcon#about to read 6, iclass 30, count 2 2006.201.07:47:51.65#ibcon#read 6, iclass 30, count 2 2006.201.07:47:51.65#ibcon#end of sib2, iclass 30, count 2 2006.201.07:47:51.65#ibcon#*mode == 0, iclass 30, count 2 2006.201.07:47:51.65#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.07:47:51.65#ibcon#[27=AT04-05\r\n] 2006.201.07:47:51.65#ibcon#*before write, iclass 30, count 2 2006.201.07:47:51.65#ibcon#enter sib2, iclass 30, count 2 2006.201.07:47:51.65#ibcon#flushed, iclass 30, count 2 2006.201.07:47:51.65#ibcon#about to write, iclass 30, count 2 2006.201.07:47:51.65#ibcon#wrote, iclass 30, count 2 2006.201.07:47:51.65#ibcon#about to read 3, iclass 30, count 2 2006.201.07:47:51.68#ibcon#read 3, iclass 30, count 2 2006.201.07:47:51.68#ibcon#about to read 4, iclass 30, count 2 2006.201.07:47:51.68#ibcon#read 4, iclass 30, count 2 2006.201.07:47:51.68#ibcon#about to read 5, iclass 30, count 2 2006.201.07:47:51.68#ibcon#read 5, iclass 30, count 2 2006.201.07:47:51.68#ibcon#about to read 6, iclass 30, count 2 2006.201.07:47:51.68#ibcon#read 6, iclass 30, count 2 2006.201.07:47:51.68#ibcon#end of sib2, iclass 30, count 2 2006.201.07:47:51.68#ibcon#*after write, iclass 30, count 2 2006.201.07:47:51.68#ibcon#*before return 0, iclass 30, count 2 2006.201.07:47:51.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:51.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.07:47:51.68#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.07:47:51.68#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:51.68#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:51.80#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:51.80#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:51.80#ibcon#enter wrdev, iclass 30, count 0 2006.201.07:47:51.80#ibcon#first serial, iclass 30, count 0 2006.201.07:47:51.80#ibcon#enter sib2, iclass 30, count 0 2006.201.07:47:51.80#ibcon#flushed, iclass 30, count 0 2006.201.07:47:51.80#ibcon#about to write, iclass 30, count 0 2006.201.07:47:51.80#ibcon#wrote, iclass 30, count 0 2006.201.07:47:51.80#ibcon#about to read 3, iclass 30, count 0 2006.201.07:47:51.82#ibcon#read 3, iclass 30, count 0 2006.201.07:47:51.82#ibcon#about to read 4, iclass 30, count 0 2006.201.07:47:51.82#ibcon#read 4, iclass 30, count 0 2006.201.07:47:51.82#ibcon#about to read 5, iclass 30, count 0 2006.201.07:47:51.82#ibcon#read 5, iclass 30, count 0 2006.201.07:47:51.82#ibcon#about to read 6, iclass 30, count 0 2006.201.07:47:51.82#ibcon#read 6, iclass 30, count 0 2006.201.07:47:51.82#ibcon#end of sib2, iclass 30, count 0 2006.201.07:47:51.82#ibcon#*mode == 0, iclass 30, count 0 2006.201.07:47:51.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.07:47:51.82#ibcon#[27=USB\r\n] 2006.201.07:47:51.82#ibcon#*before write, iclass 30, count 0 2006.201.07:47:51.82#ibcon#enter sib2, iclass 30, count 0 2006.201.07:47:51.82#ibcon#flushed, iclass 30, count 0 2006.201.07:47:51.82#ibcon#about to write, iclass 30, count 0 2006.201.07:47:51.82#ibcon#wrote, iclass 30, count 0 2006.201.07:47:51.82#ibcon#about to read 3, iclass 30, count 0 2006.201.07:47:51.85#ibcon#read 3, iclass 30, count 0 2006.201.07:47:51.85#ibcon#about to read 4, iclass 30, count 0 2006.201.07:47:51.85#ibcon#read 4, iclass 30, count 0 2006.201.07:47:51.85#ibcon#about to read 5, iclass 30, count 0 2006.201.07:47:51.85#ibcon#read 5, iclass 30, count 0 2006.201.07:47:51.85#ibcon#about to read 6, iclass 30, count 0 2006.201.07:47:51.85#ibcon#read 6, iclass 30, count 0 2006.201.07:47:51.85#ibcon#end of sib2, iclass 30, count 0 2006.201.07:47:51.85#ibcon#*after write, iclass 30, count 0 2006.201.07:47:51.85#ibcon#*before return 0, iclass 30, count 0 2006.201.07:47:51.85#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:51.85#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.07:47:51.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.07:47:51.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.07:47:51.85$vck44/vblo=5,709.99 2006.201.07:47:51.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.07:47:51.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.07:47:51.85#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:51.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:51.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:51.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:51.85#ibcon#enter wrdev, iclass 32, count 0 2006.201.07:47:51.85#ibcon#first serial, iclass 32, count 0 2006.201.07:47:51.85#ibcon#enter sib2, iclass 32, count 0 2006.201.07:47:51.85#ibcon#flushed, iclass 32, count 0 2006.201.07:47:51.85#ibcon#about to write, iclass 32, count 0 2006.201.07:47:51.85#ibcon#wrote, iclass 32, count 0 2006.201.07:47:51.85#ibcon#about to read 3, iclass 32, count 0 2006.201.07:47:51.87#ibcon#read 3, iclass 32, count 0 2006.201.07:47:51.87#ibcon#about to read 4, iclass 32, count 0 2006.201.07:47:51.87#ibcon#read 4, iclass 32, count 0 2006.201.07:47:51.87#ibcon#about to read 5, iclass 32, count 0 2006.201.07:47:51.87#ibcon#read 5, iclass 32, count 0 2006.201.07:47:51.87#ibcon#about to read 6, iclass 32, count 0 2006.201.07:47:51.87#ibcon#read 6, iclass 32, count 0 2006.201.07:47:51.87#ibcon#end of sib2, iclass 32, count 0 2006.201.07:47:51.87#ibcon#*mode == 0, iclass 32, count 0 2006.201.07:47:51.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.07:47:51.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.07:47:51.87#ibcon#*before write, iclass 32, count 0 2006.201.07:47:51.87#ibcon#enter sib2, iclass 32, count 0 2006.201.07:47:51.87#ibcon#flushed, iclass 32, count 0 2006.201.07:47:51.87#ibcon#about to write, iclass 32, count 0 2006.201.07:47:51.87#ibcon#wrote, iclass 32, count 0 2006.201.07:47:51.87#ibcon#about to read 3, iclass 32, count 0 2006.201.07:47:51.92#ibcon#read 3, iclass 32, count 0 2006.201.07:47:51.92#ibcon#about to read 4, iclass 32, count 0 2006.201.07:47:51.92#ibcon#read 4, iclass 32, count 0 2006.201.07:47:51.92#ibcon#about to read 5, iclass 32, count 0 2006.201.07:47:51.92#ibcon#read 5, iclass 32, count 0 2006.201.07:47:51.92#ibcon#about to read 6, iclass 32, count 0 2006.201.07:47:51.92#ibcon#read 6, iclass 32, count 0 2006.201.07:47:51.92#ibcon#end of sib2, iclass 32, count 0 2006.201.07:47:51.92#ibcon#*after write, iclass 32, count 0 2006.201.07:47:51.92#ibcon#*before return 0, iclass 32, count 0 2006.201.07:47:51.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:51.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.07:47:51.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.07:47:51.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.07:47:51.92$vck44/vb=5,4 2006.201.07:47:51.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.07:47:51.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.07:47:51.92#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:51.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:51.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:51.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:51.97#ibcon#enter wrdev, iclass 34, count 2 2006.201.07:47:51.97#ibcon#first serial, iclass 34, count 2 2006.201.07:47:51.97#ibcon#enter sib2, iclass 34, count 2 2006.201.07:47:51.97#ibcon#flushed, iclass 34, count 2 2006.201.07:47:51.97#ibcon#about to write, iclass 34, count 2 2006.201.07:47:51.97#ibcon#wrote, iclass 34, count 2 2006.201.07:47:51.97#ibcon#about to read 3, iclass 34, count 2 2006.201.07:47:51.99#ibcon#read 3, iclass 34, count 2 2006.201.07:47:51.99#ibcon#about to read 4, iclass 34, count 2 2006.201.07:47:51.99#ibcon#read 4, iclass 34, count 2 2006.201.07:47:51.99#ibcon#about to read 5, iclass 34, count 2 2006.201.07:47:51.99#ibcon#read 5, iclass 34, count 2 2006.201.07:47:51.99#ibcon#about to read 6, iclass 34, count 2 2006.201.07:47:51.99#ibcon#read 6, iclass 34, count 2 2006.201.07:47:51.99#ibcon#end of sib2, iclass 34, count 2 2006.201.07:47:51.99#ibcon#*mode == 0, iclass 34, count 2 2006.201.07:47:51.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.07:47:51.99#ibcon#[27=AT05-04\r\n] 2006.201.07:47:51.99#ibcon#*before write, iclass 34, count 2 2006.201.07:47:51.99#ibcon#enter sib2, iclass 34, count 2 2006.201.07:47:51.99#ibcon#flushed, iclass 34, count 2 2006.201.07:47:51.99#ibcon#about to write, iclass 34, count 2 2006.201.07:47:51.99#ibcon#wrote, iclass 34, count 2 2006.201.07:47:51.99#ibcon#about to read 3, iclass 34, count 2 2006.201.07:47:52.02#ibcon#read 3, iclass 34, count 2 2006.201.07:47:52.02#ibcon#about to read 4, iclass 34, count 2 2006.201.07:47:52.02#ibcon#read 4, iclass 34, count 2 2006.201.07:47:52.02#ibcon#about to read 5, iclass 34, count 2 2006.201.07:47:52.02#ibcon#read 5, iclass 34, count 2 2006.201.07:47:52.02#ibcon#about to read 6, iclass 34, count 2 2006.201.07:47:52.02#ibcon#read 6, iclass 34, count 2 2006.201.07:47:52.02#ibcon#end of sib2, iclass 34, count 2 2006.201.07:47:52.02#ibcon#*after write, iclass 34, count 2 2006.201.07:47:52.02#ibcon#*before return 0, iclass 34, count 2 2006.201.07:47:52.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:52.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.07:47:52.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.07:47:52.02#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:52.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:52.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:52.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:52.14#ibcon#enter wrdev, iclass 34, count 0 2006.201.07:47:52.14#ibcon#first serial, iclass 34, count 0 2006.201.07:47:52.14#ibcon#enter sib2, iclass 34, count 0 2006.201.07:47:52.14#ibcon#flushed, iclass 34, count 0 2006.201.07:47:52.14#ibcon#about to write, iclass 34, count 0 2006.201.07:47:52.14#ibcon#wrote, iclass 34, count 0 2006.201.07:47:52.14#ibcon#about to read 3, iclass 34, count 0 2006.201.07:47:52.16#ibcon#read 3, iclass 34, count 0 2006.201.07:47:52.16#ibcon#about to read 4, iclass 34, count 0 2006.201.07:47:52.16#ibcon#read 4, iclass 34, count 0 2006.201.07:47:52.16#ibcon#about to read 5, iclass 34, count 0 2006.201.07:47:52.16#ibcon#read 5, iclass 34, count 0 2006.201.07:47:52.16#ibcon#about to read 6, iclass 34, count 0 2006.201.07:47:52.16#ibcon#read 6, iclass 34, count 0 2006.201.07:47:52.16#ibcon#end of sib2, iclass 34, count 0 2006.201.07:47:52.16#ibcon#*mode == 0, iclass 34, count 0 2006.201.07:47:52.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.07:47:52.16#ibcon#[27=USB\r\n] 2006.201.07:47:52.16#ibcon#*before write, iclass 34, count 0 2006.201.07:47:52.16#ibcon#enter sib2, iclass 34, count 0 2006.201.07:47:52.16#ibcon#flushed, iclass 34, count 0 2006.201.07:47:52.16#ibcon#about to write, iclass 34, count 0 2006.201.07:47:52.16#ibcon#wrote, iclass 34, count 0 2006.201.07:47:52.16#ibcon#about to read 3, iclass 34, count 0 2006.201.07:47:52.19#ibcon#read 3, iclass 34, count 0 2006.201.07:47:52.19#ibcon#about to read 4, iclass 34, count 0 2006.201.07:47:52.19#ibcon#read 4, iclass 34, count 0 2006.201.07:47:52.19#ibcon#about to read 5, iclass 34, count 0 2006.201.07:47:52.19#ibcon#read 5, iclass 34, count 0 2006.201.07:47:52.19#ibcon#about to read 6, iclass 34, count 0 2006.201.07:47:52.19#ibcon#read 6, iclass 34, count 0 2006.201.07:47:52.19#ibcon#end of sib2, iclass 34, count 0 2006.201.07:47:52.19#ibcon#*after write, iclass 34, count 0 2006.201.07:47:52.19#ibcon#*before return 0, iclass 34, count 0 2006.201.07:47:52.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:52.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.07:47:52.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.07:47:52.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.07:47:52.19$vck44/vblo=6,719.99 2006.201.07:47:52.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.07:47:52.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.07:47:52.19#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:52.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:52.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:52.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:52.19#ibcon#enter wrdev, iclass 36, count 0 2006.201.07:47:52.19#ibcon#first serial, iclass 36, count 0 2006.201.07:47:52.19#ibcon#enter sib2, iclass 36, count 0 2006.201.07:47:52.19#ibcon#flushed, iclass 36, count 0 2006.201.07:47:52.19#ibcon#about to write, iclass 36, count 0 2006.201.07:47:52.19#ibcon#wrote, iclass 36, count 0 2006.201.07:47:52.19#ibcon#about to read 3, iclass 36, count 0 2006.201.07:47:52.21#ibcon#read 3, iclass 36, count 0 2006.201.07:47:52.21#ibcon#about to read 4, iclass 36, count 0 2006.201.07:47:52.21#ibcon#read 4, iclass 36, count 0 2006.201.07:47:52.21#ibcon#about to read 5, iclass 36, count 0 2006.201.07:47:52.21#ibcon#read 5, iclass 36, count 0 2006.201.07:47:52.21#ibcon#about to read 6, iclass 36, count 0 2006.201.07:47:52.21#ibcon#read 6, iclass 36, count 0 2006.201.07:47:52.21#ibcon#end of sib2, iclass 36, count 0 2006.201.07:47:52.21#ibcon#*mode == 0, iclass 36, count 0 2006.201.07:47:52.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.07:47:52.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.07:47:52.21#ibcon#*before write, iclass 36, count 0 2006.201.07:47:52.21#ibcon#enter sib2, iclass 36, count 0 2006.201.07:47:52.21#ibcon#flushed, iclass 36, count 0 2006.201.07:47:52.21#ibcon#about to write, iclass 36, count 0 2006.201.07:47:52.21#ibcon#wrote, iclass 36, count 0 2006.201.07:47:52.21#ibcon#about to read 3, iclass 36, count 0 2006.201.07:47:52.25#ibcon#read 3, iclass 36, count 0 2006.201.07:47:52.25#ibcon#about to read 4, iclass 36, count 0 2006.201.07:47:52.25#ibcon#read 4, iclass 36, count 0 2006.201.07:47:52.25#ibcon#about to read 5, iclass 36, count 0 2006.201.07:47:52.25#ibcon#read 5, iclass 36, count 0 2006.201.07:47:52.25#ibcon#about to read 6, iclass 36, count 0 2006.201.07:47:52.25#ibcon#read 6, iclass 36, count 0 2006.201.07:47:52.25#ibcon#end of sib2, iclass 36, count 0 2006.201.07:47:52.25#ibcon#*after write, iclass 36, count 0 2006.201.07:47:52.25#ibcon#*before return 0, iclass 36, count 0 2006.201.07:47:52.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:52.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.07:47:52.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.07:47:52.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.07:47:52.25$vck44/vb=6,4 2006.201.07:47:52.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.07:47:52.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.07:47:52.25#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:52.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:52.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:52.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:52.31#ibcon#enter wrdev, iclass 38, count 2 2006.201.07:47:52.31#ibcon#first serial, iclass 38, count 2 2006.201.07:47:52.31#ibcon#enter sib2, iclass 38, count 2 2006.201.07:47:52.31#ibcon#flushed, iclass 38, count 2 2006.201.07:47:52.31#ibcon#about to write, iclass 38, count 2 2006.201.07:47:52.31#ibcon#wrote, iclass 38, count 2 2006.201.07:47:52.31#ibcon#about to read 3, iclass 38, count 2 2006.201.07:47:52.33#ibcon#read 3, iclass 38, count 2 2006.201.07:47:52.33#ibcon#about to read 4, iclass 38, count 2 2006.201.07:47:52.33#ibcon#read 4, iclass 38, count 2 2006.201.07:47:52.33#ibcon#about to read 5, iclass 38, count 2 2006.201.07:47:52.33#ibcon#read 5, iclass 38, count 2 2006.201.07:47:52.33#ibcon#about to read 6, iclass 38, count 2 2006.201.07:47:52.33#ibcon#read 6, iclass 38, count 2 2006.201.07:47:52.33#ibcon#end of sib2, iclass 38, count 2 2006.201.07:47:52.33#ibcon#*mode == 0, iclass 38, count 2 2006.201.07:47:52.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.07:47:52.33#ibcon#[27=AT06-04\r\n] 2006.201.07:47:52.33#ibcon#*before write, iclass 38, count 2 2006.201.07:47:52.33#ibcon#enter sib2, iclass 38, count 2 2006.201.07:47:52.33#ibcon#flushed, iclass 38, count 2 2006.201.07:47:52.33#ibcon#about to write, iclass 38, count 2 2006.201.07:47:52.33#ibcon#wrote, iclass 38, count 2 2006.201.07:47:52.33#ibcon#about to read 3, iclass 38, count 2 2006.201.07:47:52.36#ibcon#read 3, iclass 38, count 2 2006.201.07:47:52.36#ibcon#about to read 4, iclass 38, count 2 2006.201.07:47:52.36#ibcon#read 4, iclass 38, count 2 2006.201.07:47:52.36#ibcon#about to read 5, iclass 38, count 2 2006.201.07:47:52.36#ibcon#read 5, iclass 38, count 2 2006.201.07:47:52.36#ibcon#about to read 6, iclass 38, count 2 2006.201.07:47:52.36#ibcon#read 6, iclass 38, count 2 2006.201.07:47:52.36#ibcon#end of sib2, iclass 38, count 2 2006.201.07:47:52.36#ibcon#*after write, iclass 38, count 2 2006.201.07:47:52.36#ibcon#*before return 0, iclass 38, count 2 2006.201.07:47:52.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:52.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.07:47:52.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.07:47:52.36#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:52.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:52.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:52.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:52.48#ibcon#enter wrdev, iclass 38, count 0 2006.201.07:47:52.48#ibcon#first serial, iclass 38, count 0 2006.201.07:47:52.48#ibcon#enter sib2, iclass 38, count 0 2006.201.07:47:52.48#ibcon#flushed, iclass 38, count 0 2006.201.07:47:52.48#ibcon#about to write, iclass 38, count 0 2006.201.07:47:52.48#ibcon#wrote, iclass 38, count 0 2006.201.07:47:52.48#ibcon#about to read 3, iclass 38, count 0 2006.201.07:47:52.50#ibcon#read 3, iclass 38, count 0 2006.201.07:47:52.50#ibcon#about to read 4, iclass 38, count 0 2006.201.07:47:52.50#ibcon#read 4, iclass 38, count 0 2006.201.07:47:52.50#ibcon#about to read 5, iclass 38, count 0 2006.201.07:47:52.50#ibcon#read 5, iclass 38, count 0 2006.201.07:47:52.50#ibcon#about to read 6, iclass 38, count 0 2006.201.07:47:52.50#ibcon#read 6, iclass 38, count 0 2006.201.07:47:52.50#ibcon#end of sib2, iclass 38, count 0 2006.201.07:47:52.50#ibcon#*mode == 0, iclass 38, count 0 2006.201.07:47:52.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.07:47:52.50#ibcon#[27=USB\r\n] 2006.201.07:47:52.50#ibcon#*before write, iclass 38, count 0 2006.201.07:47:52.50#ibcon#enter sib2, iclass 38, count 0 2006.201.07:47:52.50#ibcon#flushed, iclass 38, count 0 2006.201.07:47:52.50#ibcon#about to write, iclass 38, count 0 2006.201.07:47:52.50#ibcon#wrote, iclass 38, count 0 2006.201.07:47:52.50#ibcon#about to read 3, iclass 38, count 0 2006.201.07:47:52.53#ibcon#read 3, iclass 38, count 0 2006.201.07:47:52.53#ibcon#about to read 4, iclass 38, count 0 2006.201.07:47:52.53#ibcon#read 4, iclass 38, count 0 2006.201.07:47:52.53#ibcon#about to read 5, iclass 38, count 0 2006.201.07:47:52.53#ibcon#read 5, iclass 38, count 0 2006.201.07:47:52.53#ibcon#about to read 6, iclass 38, count 0 2006.201.07:47:52.53#ibcon#read 6, iclass 38, count 0 2006.201.07:47:52.53#ibcon#end of sib2, iclass 38, count 0 2006.201.07:47:52.53#ibcon#*after write, iclass 38, count 0 2006.201.07:47:52.53#ibcon#*before return 0, iclass 38, count 0 2006.201.07:47:52.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:52.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.07:47:52.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.07:47:52.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.07:47:52.53$vck44/vblo=7,734.99 2006.201.07:47:52.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.07:47:52.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.07:47:52.53#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:52.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:52.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:52.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:52.53#ibcon#enter wrdev, iclass 40, count 0 2006.201.07:47:52.53#ibcon#first serial, iclass 40, count 0 2006.201.07:47:52.53#ibcon#enter sib2, iclass 40, count 0 2006.201.07:47:52.53#ibcon#flushed, iclass 40, count 0 2006.201.07:47:52.53#ibcon#about to write, iclass 40, count 0 2006.201.07:47:52.53#ibcon#wrote, iclass 40, count 0 2006.201.07:47:52.53#ibcon#about to read 3, iclass 40, count 0 2006.201.07:47:52.55#ibcon#read 3, iclass 40, count 0 2006.201.07:47:52.55#ibcon#about to read 4, iclass 40, count 0 2006.201.07:47:52.55#ibcon#read 4, iclass 40, count 0 2006.201.07:47:52.55#ibcon#about to read 5, iclass 40, count 0 2006.201.07:47:52.55#ibcon#read 5, iclass 40, count 0 2006.201.07:47:52.55#ibcon#about to read 6, iclass 40, count 0 2006.201.07:47:52.55#ibcon#read 6, iclass 40, count 0 2006.201.07:47:52.55#ibcon#end of sib2, iclass 40, count 0 2006.201.07:47:52.55#ibcon#*mode == 0, iclass 40, count 0 2006.201.07:47:52.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.07:47:52.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.07:47:52.55#ibcon#*before write, iclass 40, count 0 2006.201.07:47:52.55#ibcon#enter sib2, iclass 40, count 0 2006.201.07:47:52.55#ibcon#flushed, iclass 40, count 0 2006.201.07:47:52.55#ibcon#about to write, iclass 40, count 0 2006.201.07:47:52.55#ibcon#wrote, iclass 40, count 0 2006.201.07:47:52.55#ibcon#about to read 3, iclass 40, count 0 2006.201.07:47:52.60#ibcon#read 3, iclass 40, count 0 2006.201.07:47:52.60#ibcon#about to read 4, iclass 40, count 0 2006.201.07:47:52.60#ibcon#read 4, iclass 40, count 0 2006.201.07:47:52.60#ibcon#about to read 5, iclass 40, count 0 2006.201.07:47:52.60#ibcon#read 5, iclass 40, count 0 2006.201.07:47:52.60#ibcon#about to read 6, iclass 40, count 0 2006.201.07:47:52.60#ibcon#read 6, iclass 40, count 0 2006.201.07:47:52.60#ibcon#end of sib2, iclass 40, count 0 2006.201.07:47:52.60#ibcon#*after write, iclass 40, count 0 2006.201.07:47:52.60#ibcon#*before return 0, iclass 40, count 0 2006.201.07:47:52.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:52.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.07:47:52.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.07:47:52.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.07:47:52.60$vck44/vb=7,4 2006.201.07:47:52.60#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.07:47:52.60#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.07:47:52.60#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:52.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:52.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:52.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:52.65#ibcon#enter wrdev, iclass 4, count 2 2006.201.07:47:52.65#ibcon#first serial, iclass 4, count 2 2006.201.07:47:52.65#ibcon#enter sib2, iclass 4, count 2 2006.201.07:47:52.65#ibcon#flushed, iclass 4, count 2 2006.201.07:47:52.65#ibcon#about to write, iclass 4, count 2 2006.201.07:47:52.65#ibcon#wrote, iclass 4, count 2 2006.201.07:47:52.65#ibcon#about to read 3, iclass 4, count 2 2006.201.07:47:52.67#ibcon#read 3, iclass 4, count 2 2006.201.07:47:52.67#ibcon#about to read 4, iclass 4, count 2 2006.201.07:47:52.67#ibcon#read 4, iclass 4, count 2 2006.201.07:47:52.67#ibcon#about to read 5, iclass 4, count 2 2006.201.07:47:52.67#ibcon#read 5, iclass 4, count 2 2006.201.07:47:52.67#ibcon#about to read 6, iclass 4, count 2 2006.201.07:47:52.67#ibcon#read 6, iclass 4, count 2 2006.201.07:47:52.67#ibcon#end of sib2, iclass 4, count 2 2006.201.07:47:52.67#ibcon#*mode == 0, iclass 4, count 2 2006.201.07:47:52.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.07:47:52.67#ibcon#[27=AT07-04\r\n] 2006.201.07:47:52.67#ibcon#*before write, iclass 4, count 2 2006.201.07:47:52.67#ibcon#enter sib2, iclass 4, count 2 2006.201.07:47:52.67#ibcon#flushed, iclass 4, count 2 2006.201.07:47:52.67#ibcon#about to write, iclass 4, count 2 2006.201.07:47:52.67#ibcon#wrote, iclass 4, count 2 2006.201.07:47:52.67#ibcon#about to read 3, iclass 4, count 2 2006.201.07:47:52.70#ibcon#read 3, iclass 4, count 2 2006.201.07:47:52.70#ibcon#about to read 4, iclass 4, count 2 2006.201.07:47:52.70#ibcon#read 4, iclass 4, count 2 2006.201.07:47:52.70#ibcon#about to read 5, iclass 4, count 2 2006.201.07:47:52.70#ibcon#read 5, iclass 4, count 2 2006.201.07:47:52.70#ibcon#about to read 6, iclass 4, count 2 2006.201.07:47:52.70#ibcon#read 6, iclass 4, count 2 2006.201.07:47:52.70#ibcon#end of sib2, iclass 4, count 2 2006.201.07:47:52.70#ibcon#*after write, iclass 4, count 2 2006.201.07:47:52.70#ibcon#*before return 0, iclass 4, count 2 2006.201.07:47:52.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:52.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.07:47:52.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.07:47:52.70#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:52.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:52.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:52.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:52.82#ibcon#enter wrdev, iclass 4, count 0 2006.201.07:47:52.82#ibcon#first serial, iclass 4, count 0 2006.201.07:47:52.82#ibcon#enter sib2, iclass 4, count 0 2006.201.07:47:52.82#ibcon#flushed, iclass 4, count 0 2006.201.07:47:52.82#ibcon#about to write, iclass 4, count 0 2006.201.07:47:52.82#ibcon#wrote, iclass 4, count 0 2006.201.07:47:52.82#ibcon#about to read 3, iclass 4, count 0 2006.201.07:47:52.84#ibcon#read 3, iclass 4, count 0 2006.201.07:47:52.84#ibcon#about to read 4, iclass 4, count 0 2006.201.07:47:52.84#ibcon#read 4, iclass 4, count 0 2006.201.07:47:52.84#ibcon#about to read 5, iclass 4, count 0 2006.201.07:47:52.84#ibcon#read 5, iclass 4, count 0 2006.201.07:47:52.84#ibcon#about to read 6, iclass 4, count 0 2006.201.07:47:52.84#ibcon#read 6, iclass 4, count 0 2006.201.07:47:52.84#ibcon#end of sib2, iclass 4, count 0 2006.201.07:47:52.84#ibcon#*mode == 0, iclass 4, count 0 2006.201.07:47:52.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.07:47:52.84#ibcon#[27=USB\r\n] 2006.201.07:47:52.84#ibcon#*before write, iclass 4, count 0 2006.201.07:47:52.84#ibcon#enter sib2, iclass 4, count 0 2006.201.07:47:52.84#ibcon#flushed, iclass 4, count 0 2006.201.07:47:52.84#ibcon#about to write, iclass 4, count 0 2006.201.07:47:52.84#ibcon#wrote, iclass 4, count 0 2006.201.07:47:52.84#ibcon#about to read 3, iclass 4, count 0 2006.201.07:47:52.87#ibcon#read 3, iclass 4, count 0 2006.201.07:47:52.87#ibcon#about to read 4, iclass 4, count 0 2006.201.07:47:52.87#ibcon#read 4, iclass 4, count 0 2006.201.07:47:52.87#ibcon#about to read 5, iclass 4, count 0 2006.201.07:47:52.87#ibcon#read 5, iclass 4, count 0 2006.201.07:47:52.87#ibcon#about to read 6, iclass 4, count 0 2006.201.07:47:52.87#ibcon#read 6, iclass 4, count 0 2006.201.07:47:52.87#ibcon#end of sib2, iclass 4, count 0 2006.201.07:47:52.87#ibcon#*after write, iclass 4, count 0 2006.201.07:47:52.87#ibcon#*before return 0, iclass 4, count 0 2006.201.07:47:52.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:52.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.07:47:52.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.07:47:52.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.07:47:52.87$vck44/vblo=8,744.99 2006.201.07:47:52.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.07:47:52.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.07:47:52.87#ibcon#ireg 17 cls_cnt 0 2006.201.07:47:52.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:52.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:52.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:52.87#ibcon#enter wrdev, iclass 6, count 0 2006.201.07:47:52.87#ibcon#first serial, iclass 6, count 0 2006.201.07:47:52.87#ibcon#enter sib2, iclass 6, count 0 2006.201.07:47:52.87#ibcon#flushed, iclass 6, count 0 2006.201.07:47:52.87#ibcon#about to write, iclass 6, count 0 2006.201.07:47:52.87#ibcon#wrote, iclass 6, count 0 2006.201.07:47:52.87#ibcon#about to read 3, iclass 6, count 0 2006.201.07:47:52.89#ibcon#read 3, iclass 6, count 0 2006.201.07:47:52.89#ibcon#about to read 4, iclass 6, count 0 2006.201.07:47:52.89#ibcon#read 4, iclass 6, count 0 2006.201.07:47:52.89#ibcon#about to read 5, iclass 6, count 0 2006.201.07:47:52.89#ibcon#read 5, iclass 6, count 0 2006.201.07:47:52.89#ibcon#about to read 6, iclass 6, count 0 2006.201.07:47:52.89#ibcon#read 6, iclass 6, count 0 2006.201.07:47:52.89#ibcon#end of sib2, iclass 6, count 0 2006.201.07:47:52.89#ibcon#*mode == 0, iclass 6, count 0 2006.201.07:47:52.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.07:47:52.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.07:47:52.89#ibcon#*before write, iclass 6, count 0 2006.201.07:47:52.89#ibcon#enter sib2, iclass 6, count 0 2006.201.07:47:52.89#ibcon#flushed, iclass 6, count 0 2006.201.07:47:52.89#ibcon#about to write, iclass 6, count 0 2006.201.07:47:52.89#ibcon#wrote, iclass 6, count 0 2006.201.07:47:52.89#ibcon#about to read 3, iclass 6, count 0 2006.201.07:47:52.94#ibcon#read 3, iclass 6, count 0 2006.201.07:47:52.94#ibcon#about to read 4, iclass 6, count 0 2006.201.07:47:52.94#ibcon#read 4, iclass 6, count 0 2006.201.07:47:52.94#ibcon#about to read 5, iclass 6, count 0 2006.201.07:47:52.94#ibcon#read 5, iclass 6, count 0 2006.201.07:47:52.94#ibcon#about to read 6, iclass 6, count 0 2006.201.07:47:52.94#ibcon#read 6, iclass 6, count 0 2006.201.07:47:52.94#ibcon#end of sib2, iclass 6, count 0 2006.201.07:47:52.94#ibcon#*after write, iclass 6, count 0 2006.201.07:47:52.94#ibcon#*before return 0, iclass 6, count 0 2006.201.07:47:52.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:52.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.07:47:52.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.07:47:52.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.07:47:52.94$vck44/vb=8,4 2006.201.07:47:52.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.07:47:52.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.07:47:52.94#ibcon#ireg 11 cls_cnt 2 2006.201.07:47:52.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:52.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:52.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:52.99#ibcon#enter wrdev, iclass 10, count 2 2006.201.07:47:52.99#ibcon#first serial, iclass 10, count 2 2006.201.07:47:52.99#ibcon#enter sib2, iclass 10, count 2 2006.201.07:47:52.99#ibcon#flushed, iclass 10, count 2 2006.201.07:47:52.99#ibcon#about to write, iclass 10, count 2 2006.201.07:47:52.99#ibcon#wrote, iclass 10, count 2 2006.201.07:47:52.99#ibcon#about to read 3, iclass 10, count 2 2006.201.07:47:53.01#ibcon#read 3, iclass 10, count 2 2006.201.07:47:53.01#ibcon#about to read 4, iclass 10, count 2 2006.201.07:47:53.01#ibcon#read 4, iclass 10, count 2 2006.201.07:47:53.01#ibcon#about to read 5, iclass 10, count 2 2006.201.07:47:53.01#ibcon#read 5, iclass 10, count 2 2006.201.07:47:53.01#ibcon#about to read 6, iclass 10, count 2 2006.201.07:47:53.01#ibcon#read 6, iclass 10, count 2 2006.201.07:47:53.01#ibcon#end of sib2, iclass 10, count 2 2006.201.07:47:53.01#ibcon#*mode == 0, iclass 10, count 2 2006.201.07:47:53.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.07:47:53.01#ibcon#[27=AT08-04\r\n] 2006.201.07:47:53.01#ibcon#*before write, iclass 10, count 2 2006.201.07:47:53.01#ibcon#enter sib2, iclass 10, count 2 2006.201.07:47:53.01#ibcon#flushed, iclass 10, count 2 2006.201.07:47:53.01#ibcon#about to write, iclass 10, count 2 2006.201.07:47:53.01#ibcon#wrote, iclass 10, count 2 2006.201.07:47:53.01#ibcon#about to read 3, iclass 10, count 2 2006.201.07:47:53.04#ibcon#read 3, iclass 10, count 2 2006.201.07:47:53.04#ibcon#about to read 4, iclass 10, count 2 2006.201.07:47:53.04#ibcon#read 4, iclass 10, count 2 2006.201.07:47:53.04#ibcon#about to read 5, iclass 10, count 2 2006.201.07:47:53.04#ibcon#read 5, iclass 10, count 2 2006.201.07:47:53.04#ibcon#about to read 6, iclass 10, count 2 2006.201.07:47:53.04#ibcon#read 6, iclass 10, count 2 2006.201.07:47:53.04#ibcon#end of sib2, iclass 10, count 2 2006.201.07:47:53.04#ibcon#*after write, iclass 10, count 2 2006.201.07:47:53.04#ibcon#*before return 0, iclass 10, count 2 2006.201.07:47:53.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:53.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.07:47:53.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.07:47:53.04#ibcon#ireg 7 cls_cnt 0 2006.201.07:47:53.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:53.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:53.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:53.16#ibcon#enter wrdev, iclass 10, count 0 2006.201.07:47:53.16#ibcon#first serial, iclass 10, count 0 2006.201.07:47:53.16#ibcon#enter sib2, iclass 10, count 0 2006.201.07:47:53.16#ibcon#flushed, iclass 10, count 0 2006.201.07:47:53.16#ibcon#about to write, iclass 10, count 0 2006.201.07:47:53.16#ibcon#wrote, iclass 10, count 0 2006.201.07:47:53.16#ibcon#about to read 3, iclass 10, count 0 2006.201.07:47:53.18#ibcon#read 3, iclass 10, count 0 2006.201.07:47:53.18#ibcon#about to read 4, iclass 10, count 0 2006.201.07:47:53.18#ibcon#read 4, iclass 10, count 0 2006.201.07:47:53.18#ibcon#about to read 5, iclass 10, count 0 2006.201.07:47:53.18#ibcon#read 5, iclass 10, count 0 2006.201.07:47:53.18#ibcon#about to read 6, iclass 10, count 0 2006.201.07:47:53.18#ibcon#read 6, iclass 10, count 0 2006.201.07:47:53.18#ibcon#end of sib2, iclass 10, count 0 2006.201.07:47:53.18#ibcon#*mode == 0, iclass 10, count 0 2006.201.07:47:53.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.07:47:53.18#ibcon#[27=USB\r\n] 2006.201.07:47:53.18#ibcon#*before write, iclass 10, count 0 2006.201.07:47:53.18#ibcon#enter sib2, iclass 10, count 0 2006.201.07:47:53.18#ibcon#flushed, iclass 10, count 0 2006.201.07:47:53.18#ibcon#about to write, iclass 10, count 0 2006.201.07:47:53.18#ibcon#wrote, iclass 10, count 0 2006.201.07:47:53.18#ibcon#about to read 3, iclass 10, count 0 2006.201.07:47:53.21#ibcon#read 3, iclass 10, count 0 2006.201.07:47:53.21#ibcon#about to read 4, iclass 10, count 0 2006.201.07:47:53.21#ibcon#read 4, iclass 10, count 0 2006.201.07:47:53.21#ibcon#about to read 5, iclass 10, count 0 2006.201.07:47:53.21#ibcon#read 5, iclass 10, count 0 2006.201.07:47:53.21#ibcon#about to read 6, iclass 10, count 0 2006.201.07:47:53.21#ibcon#read 6, iclass 10, count 0 2006.201.07:47:53.21#ibcon#end of sib2, iclass 10, count 0 2006.201.07:47:53.21#ibcon#*after write, iclass 10, count 0 2006.201.07:47:53.21#ibcon#*before return 0, iclass 10, count 0 2006.201.07:47:53.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:53.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.07:47:53.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.07:47:53.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.07:47:53.21$vck44/vabw=wide 2006.201.07:47:53.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.07:47:53.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.07:47:53.21#ibcon#ireg 8 cls_cnt 0 2006.201.07:47:53.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:53.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:53.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:53.21#ibcon#enter wrdev, iclass 12, count 0 2006.201.07:47:53.21#ibcon#first serial, iclass 12, count 0 2006.201.07:47:53.21#ibcon#enter sib2, iclass 12, count 0 2006.201.07:47:53.21#ibcon#flushed, iclass 12, count 0 2006.201.07:47:53.21#ibcon#about to write, iclass 12, count 0 2006.201.07:47:53.21#ibcon#wrote, iclass 12, count 0 2006.201.07:47:53.21#ibcon#about to read 3, iclass 12, count 0 2006.201.07:47:53.23#ibcon#read 3, iclass 12, count 0 2006.201.07:47:53.23#ibcon#about to read 4, iclass 12, count 0 2006.201.07:47:53.23#ibcon#read 4, iclass 12, count 0 2006.201.07:47:53.23#ibcon#about to read 5, iclass 12, count 0 2006.201.07:47:53.23#ibcon#read 5, iclass 12, count 0 2006.201.07:47:53.23#ibcon#about to read 6, iclass 12, count 0 2006.201.07:47:53.23#ibcon#read 6, iclass 12, count 0 2006.201.07:47:53.23#ibcon#end of sib2, iclass 12, count 0 2006.201.07:47:53.23#ibcon#*mode == 0, iclass 12, count 0 2006.201.07:47:53.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.07:47:53.23#ibcon#[25=BW32\r\n] 2006.201.07:47:53.23#ibcon#*before write, iclass 12, count 0 2006.201.07:47:53.23#ibcon#enter sib2, iclass 12, count 0 2006.201.07:47:53.23#ibcon#flushed, iclass 12, count 0 2006.201.07:47:53.23#ibcon#about to write, iclass 12, count 0 2006.201.07:47:53.23#ibcon#wrote, iclass 12, count 0 2006.201.07:47:53.23#ibcon#about to read 3, iclass 12, count 0 2006.201.07:47:53.26#ibcon#read 3, iclass 12, count 0 2006.201.07:47:53.26#ibcon#about to read 4, iclass 12, count 0 2006.201.07:47:53.26#ibcon#read 4, iclass 12, count 0 2006.201.07:47:53.26#ibcon#about to read 5, iclass 12, count 0 2006.201.07:47:53.26#ibcon#read 5, iclass 12, count 0 2006.201.07:47:53.26#ibcon#about to read 6, iclass 12, count 0 2006.201.07:47:53.26#ibcon#read 6, iclass 12, count 0 2006.201.07:47:53.26#ibcon#end of sib2, iclass 12, count 0 2006.201.07:47:53.26#ibcon#*after write, iclass 12, count 0 2006.201.07:47:53.26#ibcon#*before return 0, iclass 12, count 0 2006.201.07:47:53.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:53.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.07:47:53.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.07:47:53.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.07:47:53.26$vck44/vbbw=wide 2006.201.07:47:53.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.07:47:53.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.07:47:53.26#ibcon#ireg 8 cls_cnt 0 2006.201.07:47:53.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:47:53.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:47:53.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:47:53.33#ibcon#enter wrdev, iclass 14, count 0 2006.201.07:47:53.33#ibcon#first serial, iclass 14, count 0 2006.201.07:47:53.33#ibcon#enter sib2, iclass 14, count 0 2006.201.07:47:53.33#ibcon#flushed, iclass 14, count 0 2006.201.07:47:53.33#ibcon#about to write, iclass 14, count 0 2006.201.07:47:53.33#ibcon#wrote, iclass 14, count 0 2006.201.07:47:53.33#ibcon#about to read 3, iclass 14, count 0 2006.201.07:47:53.35#ibcon#read 3, iclass 14, count 0 2006.201.07:47:53.35#ibcon#about to read 4, iclass 14, count 0 2006.201.07:47:53.35#ibcon#read 4, iclass 14, count 0 2006.201.07:47:53.35#ibcon#about to read 5, iclass 14, count 0 2006.201.07:47:53.35#ibcon#read 5, iclass 14, count 0 2006.201.07:47:53.35#ibcon#about to read 6, iclass 14, count 0 2006.201.07:47:53.35#ibcon#read 6, iclass 14, count 0 2006.201.07:47:53.35#ibcon#end of sib2, iclass 14, count 0 2006.201.07:47:53.35#ibcon#*mode == 0, iclass 14, count 0 2006.201.07:47:53.35#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.07:47:53.35#ibcon#[27=BW32\r\n] 2006.201.07:47:53.35#ibcon#*before write, iclass 14, count 0 2006.201.07:47:53.35#ibcon#enter sib2, iclass 14, count 0 2006.201.07:47:53.35#ibcon#flushed, iclass 14, count 0 2006.201.07:47:53.35#ibcon#about to write, iclass 14, count 0 2006.201.07:47:53.35#ibcon#wrote, iclass 14, count 0 2006.201.07:47:53.35#ibcon#about to read 3, iclass 14, count 0 2006.201.07:47:53.38#ibcon#read 3, iclass 14, count 0 2006.201.07:47:53.38#ibcon#about to read 4, iclass 14, count 0 2006.201.07:47:53.38#ibcon#read 4, iclass 14, count 0 2006.201.07:47:53.38#ibcon#about to read 5, iclass 14, count 0 2006.201.07:47:53.38#ibcon#read 5, iclass 14, count 0 2006.201.07:47:53.38#ibcon#about to read 6, iclass 14, count 0 2006.201.07:47:53.38#ibcon#read 6, iclass 14, count 0 2006.201.07:47:53.38#ibcon#end of sib2, iclass 14, count 0 2006.201.07:47:53.38#ibcon#*after write, iclass 14, count 0 2006.201.07:47:53.38#ibcon#*before return 0, iclass 14, count 0 2006.201.07:47:53.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:47:53.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.07:47:53.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.07:47:53.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.07:47:53.38$setupk4/ifdk4 2006.201.07:47:53.38$ifdk4/lo= 2006.201.07:47:53.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.07:47:53.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.07:47:53.38$ifdk4/patch= 2006.201.07:47:53.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.07:47:53.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.07:47:53.38$setupk4/!*+20s 2006.201.07:47:57.51#abcon#<5=/04 2.4 5.1 23.35 891003.0\r\n> 2006.201.07:47:57.53#abcon#{5=INTERFACE CLEAR} 2006.201.07:47:57.60#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:48:07.69#abcon#<5=/04 2.4 5.1 23.35 891003.0\r\n> 2006.201.07:48:07.71#abcon#{5=INTERFACE CLEAR} 2006.201.07:48:07.77#abcon#[5=S1D000X0/0*\r\n] 2006.201.07:48:07.87$setupk4/"tpicd 2006.201.07:48:07.87$setupk4/echo=off 2006.201.07:48:07.87$setupk4/xlog=off 2006.201.07:48:07.87:!2006.201.07:54:57 2006.201.07:48:26.14#trakl#Source acquired 2006.201.07:48:26.14#flagr#flagr/antenna,acquired 2006.201.07:54:57.00:preob 2006.201.07:54:57.14/onsource/TRACKING 2006.201.07:54:57.14:!2006.201.07:55:07 2006.201.07:55:07.00:"tape 2006.201.07:55:07.00:"st=record 2006.201.07:55:07.00:data_valid=on 2006.201.07:55:07.00:midob 2006.201.07:55:08.14/onsource/TRACKING 2006.201.07:55:08.14/wx/23.43,1003.1,88 2006.201.07:55:08.35/cable/+6.4658E-03 2006.201.07:55:09.44/va/01,08,usb,yes,30,33 2006.201.07:55:09.44/va/02,07,usb,yes,33,33 2006.201.07:55:09.44/va/03,08,usb,yes,29,31 2006.201.07:55:09.44/va/04,07,usb,yes,33,35 2006.201.07:55:09.44/va/05,04,usb,yes,30,30 2006.201.07:55:09.44/va/06,05,usb,yes,30,30 2006.201.07:55:09.44/va/07,05,usb,yes,29,30 2006.201.07:55:09.44/va/08,04,usb,yes,28,34 2006.201.07:55:09.67/valo/01,524.99,yes,locked 2006.201.07:55:09.67/valo/02,534.99,yes,locked 2006.201.07:55:09.67/valo/03,564.99,yes,locked 2006.201.07:55:09.67/valo/04,624.99,yes,locked 2006.201.07:55:09.67/valo/05,734.99,yes,locked 2006.201.07:55:09.67/valo/06,814.99,yes,locked 2006.201.07:55:09.67/valo/07,864.99,yes,locked 2006.201.07:55:09.67/valo/08,884.99,yes,locked 2006.201.07:55:10.76/vb/01,04,usb,yes,30,27 2006.201.07:55:10.76/vb/02,05,usb,yes,28,28 2006.201.07:55:10.76/vb/03,04,usb,yes,29,32 2006.201.07:55:10.76/vb/04,05,usb,yes,29,28 2006.201.07:55:10.76/vb/05,04,usb,yes,26,28 2006.201.07:55:10.76/vb/06,04,usb,yes,30,27 2006.201.07:55:10.76/vb/07,04,usb,yes,30,30 2006.201.07:55:10.76/vb/08,04,usb,yes,28,31 2006.201.07:55:11.00/vblo/01,629.99,yes,locked 2006.201.07:55:11.00/vblo/02,634.99,yes,locked 2006.201.07:55:11.00/vblo/03,649.99,yes,locked 2006.201.07:55:11.00/vblo/04,679.99,yes,locked 2006.201.07:55:11.00/vblo/05,709.99,yes,locked 2006.201.07:55:11.00/vblo/06,719.99,yes,locked 2006.201.07:55:11.00/vblo/07,734.99,yes,locked 2006.201.07:55:11.00/vblo/08,744.99,yes,locked 2006.201.07:55:11.15/vabw/8 2006.201.07:55:11.30/vbbw/8 2006.201.07:55:11.39/xfe/off,on,15.0 2006.201.07:55:11.78/ifatt/23,28,28,28 2006.201.07:55:12.05/fmout-gps/S +4.56E-07 2006.201.07:55:12.12:!2006.201.08:08:11 2006.201.08:08:11.00:data_valid=off 2006.201.08:08:11.00:"et 2006.201.08:08:11.00:!+3s 2006.201.08:08:14.02:"tape 2006.201.08:08:14.02:postob 2006.201.08:08:14.12/cable/+6.4651E-03 2006.201.08:08:14.12/wx/23.25,1003.1,86 2006.201.08:08:14.19/fmout-gps/S +4.55E-07 2006.201.08:08:14.19:scan_name=201-0809,jd0607,100 2006.201.08:08:14.19:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.201.08:08:16.14#flagr#flagr/antenna,new-source 2006.201.08:08:16.14:checkk5 2006.201.08:08:16.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:08:16.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:08:17.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:08:17.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:08:18.36/chk_obsdata//k5ts1/T2010755??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.201.08:08:19.04/chk_obsdata//k5ts2/T2010755??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.201.08:08:19.71/chk_obsdata//k5ts3/T2010755??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.201.08:08:20.38/chk_obsdata//k5ts4/T2010755??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.201.08:08:21.07/k5log//k5ts1_log_newline 2006.201.08:08:21.76/k5log//k5ts2_log_newline 2006.201.08:08:22.45/k5log//k5ts3_log_newline 2006.201.08:08:23.14/k5log//k5ts4_log_newline 2006.201.08:08:23.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:08:23.16:setupk4=1 2006.201.08:08:23.16$setupk4/echo=on 2006.201.08:08:23.16$setupk4/pcalon 2006.201.08:08:23.16$pcalon/"no phase cal control is implemented here 2006.201.08:08:23.16$setupk4/"tpicd=stop 2006.201.08:08:23.16$setupk4/"rec=synch_on 2006.201.08:08:23.16$setupk4/"rec_mode=128 2006.201.08:08:23.16$setupk4/!* 2006.201.08:08:23.16$setupk4/recpk4 2006.201.08:08:23.16$recpk4/recpatch= 2006.201.08:08:23.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:08:23.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:08:23.17$setupk4/vck44 2006.201.08:08:23.17$vck44/valo=1,524.99 2006.201.08:08:23.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.08:08:23.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.08:08:23.17#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:23.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:23.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:23.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:23.17#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:08:23.17#ibcon#first serial, iclass 35, count 0 2006.201.08:08:23.17#ibcon#enter sib2, iclass 35, count 0 2006.201.08:08:23.17#ibcon#flushed, iclass 35, count 0 2006.201.08:08:23.17#ibcon#about to write, iclass 35, count 0 2006.201.08:08:23.17#ibcon#wrote, iclass 35, count 0 2006.201.08:08:23.17#ibcon#about to read 3, iclass 35, count 0 2006.201.08:08:23.20#ibcon#read 3, iclass 35, count 0 2006.201.08:08:23.20#ibcon#about to read 4, iclass 35, count 0 2006.201.08:08:23.20#ibcon#read 4, iclass 35, count 0 2006.201.08:08:23.20#ibcon#about to read 5, iclass 35, count 0 2006.201.08:08:23.20#ibcon#read 5, iclass 35, count 0 2006.201.08:08:23.20#ibcon#about to read 6, iclass 35, count 0 2006.201.08:08:23.20#ibcon#read 6, iclass 35, count 0 2006.201.08:08:23.20#ibcon#end of sib2, iclass 35, count 0 2006.201.08:08:23.20#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:08:23.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:08:23.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:08:23.20#ibcon#*before write, iclass 35, count 0 2006.201.08:08:23.20#ibcon#enter sib2, iclass 35, count 0 2006.201.08:08:23.20#ibcon#flushed, iclass 35, count 0 2006.201.08:08:23.20#ibcon#about to write, iclass 35, count 0 2006.201.08:08:23.20#ibcon#wrote, iclass 35, count 0 2006.201.08:08:23.20#ibcon#about to read 3, iclass 35, count 0 2006.201.08:08:23.26#ibcon#read 3, iclass 35, count 0 2006.201.08:08:23.26#ibcon#about to read 4, iclass 35, count 0 2006.201.08:08:23.26#ibcon#read 4, iclass 35, count 0 2006.201.08:08:23.26#ibcon#about to read 5, iclass 35, count 0 2006.201.08:08:23.26#ibcon#read 5, iclass 35, count 0 2006.201.08:08:23.26#ibcon#about to read 6, iclass 35, count 0 2006.201.08:08:23.26#ibcon#read 6, iclass 35, count 0 2006.201.08:08:23.26#ibcon#end of sib2, iclass 35, count 0 2006.201.08:08:23.26#ibcon#*after write, iclass 35, count 0 2006.201.08:08:23.26#ibcon#*before return 0, iclass 35, count 0 2006.201.08:08:23.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:23.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:23.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:08:23.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:08:23.26$vck44/va=1,8 2006.201.08:08:23.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.08:08:23.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.08:08:23.26#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:23.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:23.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:23.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:23.26#ibcon#enter wrdev, iclass 37, count 2 2006.201.08:08:23.26#ibcon#first serial, iclass 37, count 2 2006.201.08:08:23.26#ibcon#enter sib2, iclass 37, count 2 2006.201.08:08:23.26#ibcon#flushed, iclass 37, count 2 2006.201.08:08:23.26#ibcon#about to write, iclass 37, count 2 2006.201.08:08:23.26#ibcon#wrote, iclass 37, count 2 2006.201.08:08:23.26#ibcon#about to read 3, iclass 37, count 2 2006.201.08:08:23.28#ibcon#read 3, iclass 37, count 2 2006.201.08:08:23.28#ibcon#about to read 4, iclass 37, count 2 2006.201.08:08:23.28#ibcon#read 4, iclass 37, count 2 2006.201.08:08:23.28#ibcon#about to read 5, iclass 37, count 2 2006.201.08:08:23.28#ibcon#read 5, iclass 37, count 2 2006.201.08:08:23.28#ibcon#about to read 6, iclass 37, count 2 2006.201.08:08:23.28#ibcon#read 6, iclass 37, count 2 2006.201.08:08:23.28#ibcon#end of sib2, iclass 37, count 2 2006.201.08:08:23.28#ibcon#*mode == 0, iclass 37, count 2 2006.201.08:08:23.28#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.08:08:23.28#ibcon#[25=AT01-08\r\n] 2006.201.08:08:23.28#ibcon#*before write, iclass 37, count 2 2006.201.08:08:23.28#ibcon#enter sib2, iclass 37, count 2 2006.201.08:08:23.28#ibcon#flushed, iclass 37, count 2 2006.201.08:08:23.28#ibcon#about to write, iclass 37, count 2 2006.201.08:08:23.28#ibcon#wrote, iclass 37, count 2 2006.201.08:08:23.28#ibcon#about to read 3, iclass 37, count 2 2006.201.08:08:23.32#ibcon#read 3, iclass 37, count 2 2006.201.08:08:23.32#ibcon#about to read 4, iclass 37, count 2 2006.201.08:08:23.32#ibcon#read 4, iclass 37, count 2 2006.201.08:08:23.32#ibcon#about to read 5, iclass 37, count 2 2006.201.08:08:23.32#ibcon#read 5, iclass 37, count 2 2006.201.08:08:23.32#ibcon#about to read 6, iclass 37, count 2 2006.201.08:08:23.32#ibcon#read 6, iclass 37, count 2 2006.201.08:08:23.32#ibcon#end of sib2, iclass 37, count 2 2006.201.08:08:23.32#ibcon#*after write, iclass 37, count 2 2006.201.08:08:23.32#ibcon#*before return 0, iclass 37, count 2 2006.201.08:08:23.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:23.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:23.32#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.08:08:23.32#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:23.32#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:23.44#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:23.44#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:23.44#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:08:23.44#ibcon#first serial, iclass 37, count 0 2006.201.08:08:23.44#ibcon#enter sib2, iclass 37, count 0 2006.201.08:08:23.44#ibcon#flushed, iclass 37, count 0 2006.201.08:08:23.44#ibcon#about to write, iclass 37, count 0 2006.201.08:08:23.44#ibcon#wrote, iclass 37, count 0 2006.201.08:08:23.44#ibcon#about to read 3, iclass 37, count 0 2006.201.08:08:23.46#ibcon#read 3, iclass 37, count 0 2006.201.08:08:23.46#ibcon#about to read 4, iclass 37, count 0 2006.201.08:08:23.46#ibcon#read 4, iclass 37, count 0 2006.201.08:08:23.46#ibcon#about to read 5, iclass 37, count 0 2006.201.08:08:23.46#ibcon#read 5, iclass 37, count 0 2006.201.08:08:23.46#ibcon#about to read 6, iclass 37, count 0 2006.201.08:08:23.46#ibcon#read 6, iclass 37, count 0 2006.201.08:08:23.46#ibcon#end of sib2, iclass 37, count 0 2006.201.08:08:23.46#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:08:23.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:08:23.46#ibcon#[25=USB\r\n] 2006.201.08:08:23.46#ibcon#*before write, iclass 37, count 0 2006.201.08:08:23.46#ibcon#enter sib2, iclass 37, count 0 2006.201.08:08:23.46#ibcon#flushed, iclass 37, count 0 2006.201.08:08:23.46#ibcon#about to write, iclass 37, count 0 2006.201.08:08:23.46#ibcon#wrote, iclass 37, count 0 2006.201.08:08:23.46#ibcon#about to read 3, iclass 37, count 0 2006.201.08:08:23.49#ibcon#read 3, iclass 37, count 0 2006.201.08:08:23.49#ibcon#about to read 4, iclass 37, count 0 2006.201.08:08:23.49#ibcon#read 4, iclass 37, count 0 2006.201.08:08:23.49#ibcon#about to read 5, iclass 37, count 0 2006.201.08:08:23.49#ibcon#read 5, iclass 37, count 0 2006.201.08:08:23.49#ibcon#about to read 6, iclass 37, count 0 2006.201.08:08:23.49#ibcon#read 6, iclass 37, count 0 2006.201.08:08:23.49#ibcon#end of sib2, iclass 37, count 0 2006.201.08:08:23.49#ibcon#*after write, iclass 37, count 0 2006.201.08:08:23.49#ibcon#*before return 0, iclass 37, count 0 2006.201.08:08:23.49#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:23.49#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:23.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:08:23.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:08:23.49$vck44/valo=2,534.99 2006.201.08:08:23.49#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.08:08:23.49#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.08:08:23.49#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:23.49#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:23.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:23.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:23.49#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:08:23.49#ibcon#first serial, iclass 39, count 0 2006.201.08:08:23.49#ibcon#enter sib2, iclass 39, count 0 2006.201.08:08:23.49#ibcon#flushed, iclass 39, count 0 2006.201.08:08:23.49#ibcon#about to write, iclass 39, count 0 2006.201.08:08:23.49#ibcon#wrote, iclass 39, count 0 2006.201.08:08:23.49#ibcon#about to read 3, iclass 39, count 0 2006.201.08:08:23.51#ibcon#read 3, iclass 39, count 0 2006.201.08:08:23.51#ibcon#about to read 4, iclass 39, count 0 2006.201.08:08:23.51#ibcon#read 4, iclass 39, count 0 2006.201.08:08:23.51#ibcon#about to read 5, iclass 39, count 0 2006.201.08:08:23.51#ibcon#read 5, iclass 39, count 0 2006.201.08:08:23.51#ibcon#about to read 6, iclass 39, count 0 2006.201.08:08:23.51#ibcon#read 6, iclass 39, count 0 2006.201.08:08:23.51#ibcon#end of sib2, iclass 39, count 0 2006.201.08:08:23.51#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:08:23.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:08:23.51#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:08:23.51#ibcon#*before write, iclass 39, count 0 2006.201.08:08:23.51#ibcon#enter sib2, iclass 39, count 0 2006.201.08:08:23.51#ibcon#flushed, iclass 39, count 0 2006.201.08:08:23.51#ibcon#about to write, iclass 39, count 0 2006.201.08:08:23.51#ibcon#wrote, iclass 39, count 0 2006.201.08:08:23.51#ibcon#about to read 3, iclass 39, count 0 2006.201.08:08:23.55#ibcon#read 3, iclass 39, count 0 2006.201.08:08:23.55#ibcon#about to read 4, iclass 39, count 0 2006.201.08:08:23.55#ibcon#read 4, iclass 39, count 0 2006.201.08:08:23.55#ibcon#about to read 5, iclass 39, count 0 2006.201.08:08:23.55#ibcon#read 5, iclass 39, count 0 2006.201.08:08:23.55#ibcon#about to read 6, iclass 39, count 0 2006.201.08:08:23.55#ibcon#read 6, iclass 39, count 0 2006.201.08:08:23.55#ibcon#end of sib2, iclass 39, count 0 2006.201.08:08:23.55#ibcon#*after write, iclass 39, count 0 2006.201.08:08:23.55#ibcon#*before return 0, iclass 39, count 0 2006.201.08:08:23.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:23.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:23.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:08:23.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:08:23.55$vck44/va=2,7 2006.201.08:08:23.55#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.08:08:23.55#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.08:08:23.55#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:23.55#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:23.61#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:23.61#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:23.61#ibcon#enter wrdev, iclass 2, count 2 2006.201.08:08:23.61#ibcon#first serial, iclass 2, count 2 2006.201.08:08:23.61#ibcon#enter sib2, iclass 2, count 2 2006.201.08:08:23.61#ibcon#flushed, iclass 2, count 2 2006.201.08:08:23.61#ibcon#about to write, iclass 2, count 2 2006.201.08:08:23.61#ibcon#wrote, iclass 2, count 2 2006.201.08:08:23.61#ibcon#about to read 3, iclass 2, count 2 2006.201.08:08:23.63#ibcon#read 3, iclass 2, count 2 2006.201.08:08:23.63#ibcon#about to read 4, iclass 2, count 2 2006.201.08:08:23.63#ibcon#read 4, iclass 2, count 2 2006.201.08:08:23.63#ibcon#about to read 5, iclass 2, count 2 2006.201.08:08:23.63#ibcon#read 5, iclass 2, count 2 2006.201.08:08:23.63#ibcon#about to read 6, iclass 2, count 2 2006.201.08:08:23.63#ibcon#read 6, iclass 2, count 2 2006.201.08:08:23.63#ibcon#end of sib2, iclass 2, count 2 2006.201.08:08:23.63#ibcon#*mode == 0, iclass 2, count 2 2006.201.08:08:23.63#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.08:08:23.63#ibcon#[25=AT02-07\r\n] 2006.201.08:08:23.63#ibcon#*before write, iclass 2, count 2 2006.201.08:08:23.63#ibcon#enter sib2, iclass 2, count 2 2006.201.08:08:23.63#ibcon#flushed, iclass 2, count 2 2006.201.08:08:23.63#ibcon#about to write, iclass 2, count 2 2006.201.08:08:23.63#ibcon#wrote, iclass 2, count 2 2006.201.08:08:23.63#ibcon#about to read 3, iclass 2, count 2 2006.201.08:08:23.66#ibcon#read 3, iclass 2, count 2 2006.201.08:08:23.66#ibcon#about to read 4, iclass 2, count 2 2006.201.08:08:23.66#ibcon#read 4, iclass 2, count 2 2006.201.08:08:23.66#ibcon#about to read 5, iclass 2, count 2 2006.201.08:08:23.66#ibcon#read 5, iclass 2, count 2 2006.201.08:08:23.66#ibcon#about to read 6, iclass 2, count 2 2006.201.08:08:23.66#ibcon#read 6, iclass 2, count 2 2006.201.08:08:23.66#ibcon#end of sib2, iclass 2, count 2 2006.201.08:08:23.66#ibcon#*after write, iclass 2, count 2 2006.201.08:08:23.66#ibcon#*before return 0, iclass 2, count 2 2006.201.08:08:23.66#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:23.66#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:23.66#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.08:08:23.66#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:23.66#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:23.78#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:23.78#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:23.78#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:08:23.78#ibcon#first serial, iclass 2, count 0 2006.201.08:08:23.78#ibcon#enter sib2, iclass 2, count 0 2006.201.08:08:23.78#ibcon#flushed, iclass 2, count 0 2006.201.08:08:23.78#ibcon#about to write, iclass 2, count 0 2006.201.08:08:23.78#ibcon#wrote, iclass 2, count 0 2006.201.08:08:23.78#ibcon#about to read 3, iclass 2, count 0 2006.201.08:08:23.80#ibcon#read 3, iclass 2, count 0 2006.201.08:08:23.80#ibcon#about to read 4, iclass 2, count 0 2006.201.08:08:23.80#ibcon#read 4, iclass 2, count 0 2006.201.08:08:23.80#ibcon#about to read 5, iclass 2, count 0 2006.201.08:08:23.80#ibcon#read 5, iclass 2, count 0 2006.201.08:08:23.80#ibcon#about to read 6, iclass 2, count 0 2006.201.08:08:23.80#ibcon#read 6, iclass 2, count 0 2006.201.08:08:23.80#ibcon#end of sib2, iclass 2, count 0 2006.201.08:08:23.80#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:08:23.80#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:08:23.80#ibcon#[25=USB\r\n] 2006.201.08:08:23.80#ibcon#*before write, iclass 2, count 0 2006.201.08:08:23.80#ibcon#enter sib2, iclass 2, count 0 2006.201.08:08:23.80#ibcon#flushed, iclass 2, count 0 2006.201.08:08:23.80#ibcon#about to write, iclass 2, count 0 2006.201.08:08:23.80#ibcon#wrote, iclass 2, count 0 2006.201.08:08:23.80#ibcon#about to read 3, iclass 2, count 0 2006.201.08:08:23.83#ibcon#read 3, iclass 2, count 0 2006.201.08:08:23.83#ibcon#about to read 4, iclass 2, count 0 2006.201.08:08:23.83#ibcon#read 4, iclass 2, count 0 2006.201.08:08:23.83#ibcon#about to read 5, iclass 2, count 0 2006.201.08:08:23.83#ibcon#read 5, iclass 2, count 0 2006.201.08:08:23.83#ibcon#about to read 6, iclass 2, count 0 2006.201.08:08:23.83#ibcon#read 6, iclass 2, count 0 2006.201.08:08:23.83#ibcon#end of sib2, iclass 2, count 0 2006.201.08:08:23.83#ibcon#*after write, iclass 2, count 0 2006.201.08:08:23.83#ibcon#*before return 0, iclass 2, count 0 2006.201.08:08:23.83#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:23.83#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:23.83#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:08:23.83#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:08:23.83$vck44/valo=3,564.99 2006.201.08:08:23.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.08:08:23.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.08:08:23.83#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:23.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:23.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:23.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:23.83#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:08:23.83#ibcon#first serial, iclass 5, count 0 2006.201.08:08:23.83#ibcon#enter sib2, iclass 5, count 0 2006.201.08:08:23.83#ibcon#flushed, iclass 5, count 0 2006.201.08:08:23.83#ibcon#about to write, iclass 5, count 0 2006.201.08:08:23.83#ibcon#wrote, iclass 5, count 0 2006.201.08:08:23.83#ibcon#about to read 3, iclass 5, count 0 2006.201.08:08:23.85#ibcon#read 3, iclass 5, count 0 2006.201.08:08:23.85#ibcon#about to read 4, iclass 5, count 0 2006.201.08:08:23.85#ibcon#read 4, iclass 5, count 0 2006.201.08:08:23.85#ibcon#about to read 5, iclass 5, count 0 2006.201.08:08:23.85#ibcon#read 5, iclass 5, count 0 2006.201.08:08:23.85#ibcon#about to read 6, iclass 5, count 0 2006.201.08:08:23.85#ibcon#read 6, iclass 5, count 0 2006.201.08:08:23.85#ibcon#end of sib2, iclass 5, count 0 2006.201.08:08:23.85#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:08:23.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:08:23.85#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:08:23.85#ibcon#*before write, iclass 5, count 0 2006.201.08:08:23.85#ibcon#enter sib2, iclass 5, count 0 2006.201.08:08:23.85#ibcon#flushed, iclass 5, count 0 2006.201.08:08:23.85#ibcon#about to write, iclass 5, count 0 2006.201.08:08:23.85#ibcon#wrote, iclass 5, count 0 2006.201.08:08:23.85#ibcon#about to read 3, iclass 5, count 0 2006.201.08:08:23.90#ibcon#read 3, iclass 5, count 0 2006.201.08:08:23.90#ibcon#about to read 4, iclass 5, count 0 2006.201.08:08:23.90#ibcon#read 4, iclass 5, count 0 2006.201.08:08:23.90#ibcon#about to read 5, iclass 5, count 0 2006.201.08:08:23.90#ibcon#read 5, iclass 5, count 0 2006.201.08:08:23.90#ibcon#about to read 6, iclass 5, count 0 2006.201.08:08:23.90#ibcon#read 6, iclass 5, count 0 2006.201.08:08:23.90#ibcon#end of sib2, iclass 5, count 0 2006.201.08:08:23.90#ibcon#*after write, iclass 5, count 0 2006.201.08:08:23.90#ibcon#*before return 0, iclass 5, count 0 2006.201.08:08:23.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:23.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:23.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:08:23.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:08:23.90$vck44/va=3,8 2006.201.08:08:23.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.08:08:23.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.08:08:23.90#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:23.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:23.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:23.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:23.95#ibcon#enter wrdev, iclass 7, count 2 2006.201.08:08:23.95#ibcon#first serial, iclass 7, count 2 2006.201.08:08:23.95#ibcon#enter sib2, iclass 7, count 2 2006.201.08:08:23.95#ibcon#flushed, iclass 7, count 2 2006.201.08:08:23.95#ibcon#about to write, iclass 7, count 2 2006.201.08:08:23.95#ibcon#wrote, iclass 7, count 2 2006.201.08:08:23.95#ibcon#about to read 3, iclass 7, count 2 2006.201.08:08:23.97#ibcon#read 3, iclass 7, count 2 2006.201.08:08:23.97#ibcon#about to read 4, iclass 7, count 2 2006.201.08:08:23.97#ibcon#read 4, iclass 7, count 2 2006.201.08:08:23.97#ibcon#about to read 5, iclass 7, count 2 2006.201.08:08:23.97#ibcon#read 5, iclass 7, count 2 2006.201.08:08:23.97#ibcon#about to read 6, iclass 7, count 2 2006.201.08:08:23.97#ibcon#read 6, iclass 7, count 2 2006.201.08:08:23.97#ibcon#end of sib2, iclass 7, count 2 2006.201.08:08:23.97#ibcon#*mode == 0, iclass 7, count 2 2006.201.08:08:23.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.08:08:23.97#ibcon#[25=AT03-08\r\n] 2006.201.08:08:23.97#ibcon#*before write, iclass 7, count 2 2006.201.08:08:23.97#ibcon#enter sib2, iclass 7, count 2 2006.201.08:08:23.97#ibcon#flushed, iclass 7, count 2 2006.201.08:08:23.97#ibcon#about to write, iclass 7, count 2 2006.201.08:08:23.97#ibcon#wrote, iclass 7, count 2 2006.201.08:08:23.97#ibcon#about to read 3, iclass 7, count 2 2006.201.08:08:24.00#ibcon#read 3, iclass 7, count 2 2006.201.08:08:24.00#ibcon#about to read 4, iclass 7, count 2 2006.201.08:08:24.00#ibcon#read 4, iclass 7, count 2 2006.201.08:08:24.00#ibcon#about to read 5, iclass 7, count 2 2006.201.08:08:24.00#ibcon#read 5, iclass 7, count 2 2006.201.08:08:24.00#ibcon#about to read 6, iclass 7, count 2 2006.201.08:08:24.00#ibcon#read 6, iclass 7, count 2 2006.201.08:08:24.00#ibcon#end of sib2, iclass 7, count 2 2006.201.08:08:24.00#ibcon#*after write, iclass 7, count 2 2006.201.08:08:24.00#ibcon#*before return 0, iclass 7, count 2 2006.201.08:08:24.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:24.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:24.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.08:08:24.00#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:24.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:24.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:24.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:24.12#ibcon#enter wrdev, iclass 7, count 0 2006.201.08:08:24.12#ibcon#first serial, iclass 7, count 0 2006.201.08:08:24.12#ibcon#enter sib2, iclass 7, count 0 2006.201.08:08:24.12#ibcon#flushed, iclass 7, count 0 2006.201.08:08:24.12#ibcon#about to write, iclass 7, count 0 2006.201.08:08:24.12#ibcon#wrote, iclass 7, count 0 2006.201.08:08:24.12#ibcon#about to read 3, iclass 7, count 0 2006.201.08:08:24.14#ibcon#read 3, iclass 7, count 0 2006.201.08:08:24.14#ibcon#about to read 4, iclass 7, count 0 2006.201.08:08:24.14#ibcon#read 4, iclass 7, count 0 2006.201.08:08:24.14#ibcon#about to read 5, iclass 7, count 0 2006.201.08:08:24.14#ibcon#read 5, iclass 7, count 0 2006.201.08:08:24.14#ibcon#about to read 6, iclass 7, count 0 2006.201.08:08:24.14#ibcon#read 6, iclass 7, count 0 2006.201.08:08:24.14#ibcon#end of sib2, iclass 7, count 0 2006.201.08:08:24.14#ibcon#*mode == 0, iclass 7, count 0 2006.201.08:08:24.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.08:08:24.14#ibcon#[25=USB\r\n] 2006.201.08:08:24.14#ibcon#*before write, iclass 7, count 0 2006.201.08:08:24.14#ibcon#enter sib2, iclass 7, count 0 2006.201.08:08:24.14#ibcon#flushed, iclass 7, count 0 2006.201.08:08:24.14#ibcon#about to write, iclass 7, count 0 2006.201.08:08:24.14#ibcon#wrote, iclass 7, count 0 2006.201.08:08:24.14#ibcon#about to read 3, iclass 7, count 0 2006.201.08:08:24.17#ibcon#read 3, iclass 7, count 0 2006.201.08:08:24.17#ibcon#about to read 4, iclass 7, count 0 2006.201.08:08:24.17#ibcon#read 4, iclass 7, count 0 2006.201.08:08:24.17#ibcon#about to read 5, iclass 7, count 0 2006.201.08:08:24.17#ibcon#read 5, iclass 7, count 0 2006.201.08:08:24.17#ibcon#about to read 6, iclass 7, count 0 2006.201.08:08:24.17#ibcon#read 6, iclass 7, count 0 2006.201.08:08:24.17#ibcon#end of sib2, iclass 7, count 0 2006.201.08:08:24.17#ibcon#*after write, iclass 7, count 0 2006.201.08:08:24.17#ibcon#*before return 0, iclass 7, count 0 2006.201.08:08:24.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:24.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:24.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.08:08:24.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.08:08:24.17$vck44/valo=4,624.99 2006.201.08:08:24.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.08:08:24.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.08:08:24.17#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:24.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:24.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:24.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:24.17#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:08:24.17#ibcon#first serial, iclass 11, count 0 2006.201.08:08:24.17#ibcon#enter sib2, iclass 11, count 0 2006.201.08:08:24.17#ibcon#flushed, iclass 11, count 0 2006.201.08:08:24.17#ibcon#about to write, iclass 11, count 0 2006.201.08:08:24.17#ibcon#wrote, iclass 11, count 0 2006.201.08:08:24.17#ibcon#about to read 3, iclass 11, count 0 2006.201.08:08:24.19#ibcon#read 3, iclass 11, count 0 2006.201.08:08:24.19#ibcon#about to read 4, iclass 11, count 0 2006.201.08:08:24.19#ibcon#read 4, iclass 11, count 0 2006.201.08:08:24.19#ibcon#about to read 5, iclass 11, count 0 2006.201.08:08:24.19#ibcon#read 5, iclass 11, count 0 2006.201.08:08:24.19#ibcon#about to read 6, iclass 11, count 0 2006.201.08:08:24.19#ibcon#read 6, iclass 11, count 0 2006.201.08:08:24.19#ibcon#end of sib2, iclass 11, count 0 2006.201.08:08:24.19#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:08:24.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:08:24.19#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:08:24.19#ibcon#*before write, iclass 11, count 0 2006.201.08:08:24.19#ibcon#enter sib2, iclass 11, count 0 2006.201.08:08:24.19#ibcon#flushed, iclass 11, count 0 2006.201.08:08:24.19#ibcon#about to write, iclass 11, count 0 2006.201.08:08:24.19#ibcon#wrote, iclass 11, count 0 2006.201.08:08:24.19#ibcon#about to read 3, iclass 11, count 0 2006.201.08:08:24.23#ibcon#read 3, iclass 11, count 0 2006.201.08:08:24.23#ibcon#about to read 4, iclass 11, count 0 2006.201.08:08:24.23#ibcon#read 4, iclass 11, count 0 2006.201.08:08:24.23#ibcon#about to read 5, iclass 11, count 0 2006.201.08:08:24.23#ibcon#read 5, iclass 11, count 0 2006.201.08:08:24.23#ibcon#about to read 6, iclass 11, count 0 2006.201.08:08:24.23#ibcon#read 6, iclass 11, count 0 2006.201.08:08:24.23#ibcon#end of sib2, iclass 11, count 0 2006.201.08:08:24.23#ibcon#*after write, iclass 11, count 0 2006.201.08:08:24.23#ibcon#*before return 0, iclass 11, count 0 2006.201.08:08:24.23#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:24.23#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:24.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:08:24.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:08:24.23$vck44/va=4,7 2006.201.08:08:24.23#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.08:08:24.23#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.08:08:24.23#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:24.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:24.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:24.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:24.29#ibcon#enter wrdev, iclass 13, count 2 2006.201.08:08:24.29#ibcon#first serial, iclass 13, count 2 2006.201.08:08:24.29#ibcon#enter sib2, iclass 13, count 2 2006.201.08:08:24.29#ibcon#flushed, iclass 13, count 2 2006.201.08:08:24.29#ibcon#about to write, iclass 13, count 2 2006.201.08:08:24.29#ibcon#wrote, iclass 13, count 2 2006.201.08:08:24.29#ibcon#about to read 3, iclass 13, count 2 2006.201.08:08:24.31#ibcon#read 3, iclass 13, count 2 2006.201.08:08:24.31#ibcon#about to read 4, iclass 13, count 2 2006.201.08:08:24.31#ibcon#read 4, iclass 13, count 2 2006.201.08:08:24.31#ibcon#about to read 5, iclass 13, count 2 2006.201.08:08:24.31#ibcon#read 5, iclass 13, count 2 2006.201.08:08:24.31#ibcon#about to read 6, iclass 13, count 2 2006.201.08:08:24.31#ibcon#read 6, iclass 13, count 2 2006.201.08:08:24.31#ibcon#end of sib2, iclass 13, count 2 2006.201.08:08:24.31#ibcon#*mode == 0, iclass 13, count 2 2006.201.08:08:24.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.08:08:24.31#ibcon#[25=AT04-07\r\n] 2006.201.08:08:24.31#ibcon#*before write, iclass 13, count 2 2006.201.08:08:24.31#ibcon#enter sib2, iclass 13, count 2 2006.201.08:08:24.31#ibcon#flushed, iclass 13, count 2 2006.201.08:08:24.31#ibcon#about to write, iclass 13, count 2 2006.201.08:08:24.31#ibcon#wrote, iclass 13, count 2 2006.201.08:08:24.31#ibcon#about to read 3, iclass 13, count 2 2006.201.08:08:24.34#ibcon#read 3, iclass 13, count 2 2006.201.08:08:24.34#ibcon#about to read 4, iclass 13, count 2 2006.201.08:08:24.34#ibcon#read 4, iclass 13, count 2 2006.201.08:08:24.34#ibcon#about to read 5, iclass 13, count 2 2006.201.08:08:24.34#ibcon#read 5, iclass 13, count 2 2006.201.08:08:24.34#ibcon#about to read 6, iclass 13, count 2 2006.201.08:08:24.34#ibcon#read 6, iclass 13, count 2 2006.201.08:08:24.34#ibcon#end of sib2, iclass 13, count 2 2006.201.08:08:24.34#ibcon#*after write, iclass 13, count 2 2006.201.08:08:24.34#ibcon#*before return 0, iclass 13, count 2 2006.201.08:08:24.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:24.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:24.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.08:08:24.34#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:24.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:24.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:24.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:24.46#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:08:24.46#ibcon#first serial, iclass 13, count 0 2006.201.08:08:24.46#ibcon#enter sib2, iclass 13, count 0 2006.201.08:08:24.46#ibcon#flushed, iclass 13, count 0 2006.201.08:08:24.46#ibcon#about to write, iclass 13, count 0 2006.201.08:08:24.46#ibcon#wrote, iclass 13, count 0 2006.201.08:08:24.46#ibcon#about to read 3, iclass 13, count 0 2006.201.08:08:24.48#ibcon#read 3, iclass 13, count 0 2006.201.08:08:24.48#ibcon#about to read 4, iclass 13, count 0 2006.201.08:08:24.48#ibcon#read 4, iclass 13, count 0 2006.201.08:08:24.48#ibcon#about to read 5, iclass 13, count 0 2006.201.08:08:24.48#ibcon#read 5, iclass 13, count 0 2006.201.08:08:24.48#ibcon#about to read 6, iclass 13, count 0 2006.201.08:08:24.48#ibcon#read 6, iclass 13, count 0 2006.201.08:08:24.48#ibcon#end of sib2, iclass 13, count 0 2006.201.08:08:24.48#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:08:24.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:08:24.48#ibcon#[25=USB\r\n] 2006.201.08:08:24.48#ibcon#*before write, iclass 13, count 0 2006.201.08:08:24.48#ibcon#enter sib2, iclass 13, count 0 2006.201.08:08:24.48#ibcon#flushed, iclass 13, count 0 2006.201.08:08:24.48#ibcon#about to write, iclass 13, count 0 2006.201.08:08:24.48#ibcon#wrote, iclass 13, count 0 2006.201.08:08:24.48#ibcon#about to read 3, iclass 13, count 0 2006.201.08:08:24.51#ibcon#read 3, iclass 13, count 0 2006.201.08:08:24.51#ibcon#about to read 4, iclass 13, count 0 2006.201.08:08:24.51#ibcon#read 4, iclass 13, count 0 2006.201.08:08:24.51#ibcon#about to read 5, iclass 13, count 0 2006.201.08:08:24.51#ibcon#read 5, iclass 13, count 0 2006.201.08:08:24.51#ibcon#about to read 6, iclass 13, count 0 2006.201.08:08:24.51#ibcon#read 6, iclass 13, count 0 2006.201.08:08:24.51#ibcon#end of sib2, iclass 13, count 0 2006.201.08:08:24.51#ibcon#*after write, iclass 13, count 0 2006.201.08:08:24.51#ibcon#*before return 0, iclass 13, count 0 2006.201.08:08:24.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:24.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:24.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:08:24.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:08:24.51$vck44/valo=5,734.99 2006.201.08:08:24.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.08:08:24.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.08:08:24.51#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:24.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:24.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:24.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:24.51#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:08:24.51#ibcon#first serial, iclass 15, count 0 2006.201.08:08:24.51#ibcon#enter sib2, iclass 15, count 0 2006.201.08:08:24.51#ibcon#flushed, iclass 15, count 0 2006.201.08:08:24.51#ibcon#about to write, iclass 15, count 0 2006.201.08:08:24.51#ibcon#wrote, iclass 15, count 0 2006.201.08:08:24.51#ibcon#about to read 3, iclass 15, count 0 2006.201.08:08:24.53#ibcon#read 3, iclass 15, count 0 2006.201.08:08:24.53#ibcon#about to read 4, iclass 15, count 0 2006.201.08:08:24.53#ibcon#read 4, iclass 15, count 0 2006.201.08:08:24.53#ibcon#about to read 5, iclass 15, count 0 2006.201.08:08:24.53#ibcon#read 5, iclass 15, count 0 2006.201.08:08:24.53#ibcon#about to read 6, iclass 15, count 0 2006.201.08:08:24.53#ibcon#read 6, iclass 15, count 0 2006.201.08:08:24.53#ibcon#end of sib2, iclass 15, count 0 2006.201.08:08:24.53#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:08:24.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:08:24.53#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:08:24.53#ibcon#*before write, iclass 15, count 0 2006.201.08:08:24.53#ibcon#enter sib2, iclass 15, count 0 2006.201.08:08:24.53#ibcon#flushed, iclass 15, count 0 2006.201.08:08:24.53#ibcon#about to write, iclass 15, count 0 2006.201.08:08:24.53#ibcon#wrote, iclass 15, count 0 2006.201.08:08:24.53#ibcon#about to read 3, iclass 15, count 0 2006.201.08:08:24.57#ibcon#read 3, iclass 15, count 0 2006.201.08:08:24.57#ibcon#about to read 4, iclass 15, count 0 2006.201.08:08:24.57#ibcon#read 4, iclass 15, count 0 2006.201.08:08:24.57#ibcon#about to read 5, iclass 15, count 0 2006.201.08:08:24.57#ibcon#read 5, iclass 15, count 0 2006.201.08:08:24.57#ibcon#about to read 6, iclass 15, count 0 2006.201.08:08:24.57#ibcon#read 6, iclass 15, count 0 2006.201.08:08:24.57#ibcon#end of sib2, iclass 15, count 0 2006.201.08:08:24.57#ibcon#*after write, iclass 15, count 0 2006.201.08:08:24.57#ibcon#*before return 0, iclass 15, count 0 2006.201.08:08:24.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:24.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:24.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:08:24.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:08:24.57$vck44/va=5,4 2006.201.08:08:24.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.08:08:24.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.08:08:24.57#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:24.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:24.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:24.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:24.63#ibcon#enter wrdev, iclass 17, count 2 2006.201.08:08:24.63#ibcon#first serial, iclass 17, count 2 2006.201.08:08:24.63#ibcon#enter sib2, iclass 17, count 2 2006.201.08:08:24.63#ibcon#flushed, iclass 17, count 2 2006.201.08:08:24.63#ibcon#about to write, iclass 17, count 2 2006.201.08:08:24.63#ibcon#wrote, iclass 17, count 2 2006.201.08:08:24.63#ibcon#about to read 3, iclass 17, count 2 2006.201.08:08:24.65#ibcon#read 3, iclass 17, count 2 2006.201.08:08:24.65#ibcon#about to read 4, iclass 17, count 2 2006.201.08:08:24.65#ibcon#read 4, iclass 17, count 2 2006.201.08:08:24.65#ibcon#about to read 5, iclass 17, count 2 2006.201.08:08:24.65#ibcon#read 5, iclass 17, count 2 2006.201.08:08:24.65#ibcon#about to read 6, iclass 17, count 2 2006.201.08:08:24.65#ibcon#read 6, iclass 17, count 2 2006.201.08:08:24.65#ibcon#end of sib2, iclass 17, count 2 2006.201.08:08:24.65#ibcon#*mode == 0, iclass 17, count 2 2006.201.08:08:24.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.08:08:24.65#ibcon#[25=AT05-04\r\n] 2006.201.08:08:24.65#ibcon#*before write, iclass 17, count 2 2006.201.08:08:24.65#ibcon#enter sib2, iclass 17, count 2 2006.201.08:08:24.65#ibcon#flushed, iclass 17, count 2 2006.201.08:08:24.65#ibcon#about to write, iclass 17, count 2 2006.201.08:08:24.65#ibcon#wrote, iclass 17, count 2 2006.201.08:08:24.65#ibcon#about to read 3, iclass 17, count 2 2006.201.08:08:24.68#ibcon#read 3, iclass 17, count 2 2006.201.08:08:24.68#ibcon#about to read 4, iclass 17, count 2 2006.201.08:08:24.68#ibcon#read 4, iclass 17, count 2 2006.201.08:08:24.68#ibcon#about to read 5, iclass 17, count 2 2006.201.08:08:24.68#ibcon#read 5, iclass 17, count 2 2006.201.08:08:24.68#ibcon#about to read 6, iclass 17, count 2 2006.201.08:08:24.68#ibcon#read 6, iclass 17, count 2 2006.201.08:08:24.68#ibcon#end of sib2, iclass 17, count 2 2006.201.08:08:24.68#ibcon#*after write, iclass 17, count 2 2006.201.08:08:24.68#ibcon#*before return 0, iclass 17, count 2 2006.201.08:08:24.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:24.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:24.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.08:08:24.68#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:24.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:24.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:24.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:24.80#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:08:24.80#ibcon#first serial, iclass 17, count 0 2006.201.08:08:24.80#ibcon#enter sib2, iclass 17, count 0 2006.201.08:08:24.80#ibcon#flushed, iclass 17, count 0 2006.201.08:08:24.80#ibcon#about to write, iclass 17, count 0 2006.201.08:08:24.80#ibcon#wrote, iclass 17, count 0 2006.201.08:08:24.80#ibcon#about to read 3, iclass 17, count 0 2006.201.08:08:24.82#ibcon#read 3, iclass 17, count 0 2006.201.08:08:24.82#ibcon#about to read 4, iclass 17, count 0 2006.201.08:08:24.82#ibcon#read 4, iclass 17, count 0 2006.201.08:08:24.82#ibcon#about to read 5, iclass 17, count 0 2006.201.08:08:24.82#ibcon#read 5, iclass 17, count 0 2006.201.08:08:24.82#ibcon#about to read 6, iclass 17, count 0 2006.201.08:08:24.82#ibcon#read 6, iclass 17, count 0 2006.201.08:08:24.82#ibcon#end of sib2, iclass 17, count 0 2006.201.08:08:24.82#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:08:24.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:08:24.82#ibcon#[25=USB\r\n] 2006.201.08:08:24.82#ibcon#*before write, iclass 17, count 0 2006.201.08:08:24.82#ibcon#enter sib2, iclass 17, count 0 2006.201.08:08:24.82#ibcon#flushed, iclass 17, count 0 2006.201.08:08:24.82#ibcon#about to write, iclass 17, count 0 2006.201.08:08:24.82#ibcon#wrote, iclass 17, count 0 2006.201.08:08:24.82#ibcon#about to read 3, iclass 17, count 0 2006.201.08:08:24.85#ibcon#read 3, iclass 17, count 0 2006.201.08:08:24.85#ibcon#about to read 4, iclass 17, count 0 2006.201.08:08:24.85#ibcon#read 4, iclass 17, count 0 2006.201.08:08:24.85#ibcon#about to read 5, iclass 17, count 0 2006.201.08:08:24.85#ibcon#read 5, iclass 17, count 0 2006.201.08:08:24.85#ibcon#about to read 6, iclass 17, count 0 2006.201.08:08:24.85#ibcon#read 6, iclass 17, count 0 2006.201.08:08:24.85#ibcon#end of sib2, iclass 17, count 0 2006.201.08:08:24.85#ibcon#*after write, iclass 17, count 0 2006.201.08:08:24.85#ibcon#*before return 0, iclass 17, count 0 2006.201.08:08:24.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:24.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:24.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:08:24.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:08:24.85$vck44/valo=6,814.99 2006.201.08:08:24.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.08:08:24.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.08:08:24.85#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:24.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:24.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:24.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:24.85#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:08:24.85#ibcon#first serial, iclass 19, count 0 2006.201.08:08:24.85#ibcon#enter sib2, iclass 19, count 0 2006.201.08:08:24.85#ibcon#flushed, iclass 19, count 0 2006.201.08:08:24.85#ibcon#about to write, iclass 19, count 0 2006.201.08:08:24.85#ibcon#wrote, iclass 19, count 0 2006.201.08:08:24.85#ibcon#about to read 3, iclass 19, count 0 2006.201.08:08:24.87#ibcon#read 3, iclass 19, count 0 2006.201.08:08:24.87#ibcon#about to read 4, iclass 19, count 0 2006.201.08:08:24.87#ibcon#read 4, iclass 19, count 0 2006.201.08:08:24.87#ibcon#about to read 5, iclass 19, count 0 2006.201.08:08:24.87#ibcon#read 5, iclass 19, count 0 2006.201.08:08:24.87#ibcon#about to read 6, iclass 19, count 0 2006.201.08:08:24.87#ibcon#read 6, iclass 19, count 0 2006.201.08:08:24.87#ibcon#end of sib2, iclass 19, count 0 2006.201.08:08:24.87#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:08:24.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:08:24.87#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:08:24.87#ibcon#*before write, iclass 19, count 0 2006.201.08:08:24.87#ibcon#enter sib2, iclass 19, count 0 2006.201.08:08:24.87#ibcon#flushed, iclass 19, count 0 2006.201.08:08:24.87#ibcon#about to write, iclass 19, count 0 2006.201.08:08:24.87#ibcon#wrote, iclass 19, count 0 2006.201.08:08:24.87#ibcon#about to read 3, iclass 19, count 0 2006.201.08:08:24.91#ibcon#read 3, iclass 19, count 0 2006.201.08:08:24.91#ibcon#about to read 4, iclass 19, count 0 2006.201.08:08:24.91#ibcon#read 4, iclass 19, count 0 2006.201.08:08:24.91#ibcon#about to read 5, iclass 19, count 0 2006.201.08:08:24.91#ibcon#read 5, iclass 19, count 0 2006.201.08:08:24.91#ibcon#about to read 6, iclass 19, count 0 2006.201.08:08:24.91#ibcon#read 6, iclass 19, count 0 2006.201.08:08:24.91#ibcon#end of sib2, iclass 19, count 0 2006.201.08:08:24.91#ibcon#*after write, iclass 19, count 0 2006.201.08:08:24.91#ibcon#*before return 0, iclass 19, count 0 2006.201.08:08:24.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:24.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:24.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:08:24.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:08:24.91$vck44/va=6,5 2006.201.08:08:24.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.08:08:24.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.08:08:24.91#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:24.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:24.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:24.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:24.97#ibcon#enter wrdev, iclass 21, count 2 2006.201.08:08:24.97#ibcon#first serial, iclass 21, count 2 2006.201.08:08:24.97#ibcon#enter sib2, iclass 21, count 2 2006.201.08:08:24.97#ibcon#flushed, iclass 21, count 2 2006.201.08:08:24.97#ibcon#about to write, iclass 21, count 2 2006.201.08:08:24.97#ibcon#wrote, iclass 21, count 2 2006.201.08:08:24.97#ibcon#about to read 3, iclass 21, count 2 2006.201.08:08:24.99#ibcon#read 3, iclass 21, count 2 2006.201.08:08:24.99#ibcon#about to read 4, iclass 21, count 2 2006.201.08:08:24.99#ibcon#read 4, iclass 21, count 2 2006.201.08:08:24.99#ibcon#about to read 5, iclass 21, count 2 2006.201.08:08:24.99#ibcon#read 5, iclass 21, count 2 2006.201.08:08:24.99#ibcon#about to read 6, iclass 21, count 2 2006.201.08:08:24.99#ibcon#read 6, iclass 21, count 2 2006.201.08:08:24.99#ibcon#end of sib2, iclass 21, count 2 2006.201.08:08:24.99#ibcon#*mode == 0, iclass 21, count 2 2006.201.08:08:24.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.08:08:24.99#ibcon#[25=AT06-05\r\n] 2006.201.08:08:24.99#ibcon#*before write, iclass 21, count 2 2006.201.08:08:24.99#ibcon#enter sib2, iclass 21, count 2 2006.201.08:08:24.99#ibcon#flushed, iclass 21, count 2 2006.201.08:08:24.99#ibcon#about to write, iclass 21, count 2 2006.201.08:08:24.99#ibcon#wrote, iclass 21, count 2 2006.201.08:08:24.99#ibcon#about to read 3, iclass 21, count 2 2006.201.08:08:25.02#ibcon#read 3, iclass 21, count 2 2006.201.08:08:25.02#ibcon#about to read 4, iclass 21, count 2 2006.201.08:08:25.02#ibcon#read 4, iclass 21, count 2 2006.201.08:08:25.02#ibcon#about to read 5, iclass 21, count 2 2006.201.08:08:25.02#ibcon#read 5, iclass 21, count 2 2006.201.08:08:25.02#ibcon#about to read 6, iclass 21, count 2 2006.201.08:08:25.02#ibcon#read 6, iclass 21, count 2 2006.201.08:08:25.02#ibcon#end of sib2, iclass 21, count 2 2006.201.08:08:25.02#ibcon#*after write, iclass 21, count 2 2006.201.08:08:25.02#ibcon#*before return 0, iclass 21, count 2 2006.201.08:08:25.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:25.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:25.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.08:08:25.02#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:25.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:25.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:25.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:25.14#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:08:25.14#ibcon#first serial, iclass 21, count 0 2006.201.08:08:25.14#ibcon#enter sib2, iclass 21, count 0 2006.201.08:08:25.14#ibcon#flushed, iclass 21, count 0 2006.201.08:08:25.14#ibcon#about to write, iclass 21, count 0 2006.201.08:08:25.14#ibcon#wrote, iclass 21, count 0 2006.201.08:08:25.14#ibcon#about to read 3, iclass 21, count 0 2006.201.08:08:25.16#ibcon#read 3, iclass 21, count 0 2006.201.08:08:25.16#ibcon#about to read 4, iclass 21, count 0 2006.201.08:08:25.16#ibcon#read 4, iclass 21, count 0 2006.201.08:08:25.16#ibcon#about to read 5, iclass 21, count 0 2006.201.08:08:25.16#ibcon#read 5, iclass 21, count 0 2006.201.08:08:25.16#ibcon#about to read 6, iclass 21, count 0 2006.201.08:08:25.16#ibcon#read 6, iclass 21, count 0 2006.201.08:08:25.16#ibcon#end of sib2, iclass 21, count 0 2006.201.08:08:25.16#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:08:25.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:08:25.16#ibcon#[25=USB\r\n] 2006.201.08:08:25.16#ibcon#*before write, iclass 21, count 0 2006.201.08:08:25.16#ibcon#enter sib2, iclass 21, count 0 2006.201.08:08:25.16#ibcon#flushed, iclass 21, count 0 2006.201.08:08:25.16#ibcon#about to write, iclass 21, count 0 2006.201.08:08:25.16#ibcon#wrote, iclass 21, count 0 2006.201.08:08:25.16#ibcon#about to read 3, iclass 21, count 0 2006.201.08:08:25.19#ibcon#read 3, iclass 21, count 0 2006.201.08:08:25.19#ibcon#about to read 4, iclass 21, count 0 2006.201.08:08:25.19#ibcon#read 4, iclass 21, count 0 2006.201.08:08:25.19#ibcon#about to read 5, iclass 21, count 0 2006.201.08:08:25.19#ibcon#read 5, iclass 21, count 0 2006.201.08:08:25.19#ibcon#about to read 6, iclass 21, count 0 2006.201.08:08:25.19#ibcon#read 6, iclass 21, count 0 2006.201.08:08:25.19#ibcon#end of sib2, iclass 21, count 0 2006.201.08:08:25.19#ibcon#*after write, iclass 21, count 0 2006.201.08:08:25.19#ibcon#*before return 0, iclass 21, count 0 2006.201.08:08:25.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:25.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:25.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:08:25.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:08:25.19$vck44/valo=7,864.99 2006.201.08:08:25.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.08:08:25.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.08:08:25.19#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:25.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:25.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:25.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:25.19#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:08:25.19#ibcon#first serial, iclass 23, count 0 2006.201.08:08:25.19#ibcon#enter sib2, iclass 23, count 0 2006.201.08:08:25.19#ibcon#flushed, iclass 23, count 0 2006.201.08:08:25.19#ibcon#about to write, iclass 23, count 0 2006.201.08:08:25.19#ibcon#wrote, iclass 23, count 0 2006.201.08:08:25.19#ibcon#about to read 3, iclass 23, count 0 2006.201.08:08:25.21#ibcon#read 3, iclass 23, count 0 2006.201.08:08:25.21#ibcon#about to read 4, iclass 23, count 0 2006.201.08:08:25.21#ibcon#read 4, iclass 23, count 0 2006.201.08:08:25.21#ibcon#about to read 5, iclass 23, count 0 2006.201.08:08:25.21#ibcon#read 5, iclass 23, count 0 2006.201.08:08:25.21#ibcon#about to read 6, iclass 23, count 0 2006.201.08:08:25.21#ibcon#read 6, iclass 23, count 0 2006.201.08:08:25.21#ibcon#end of sib2, iclass 23, count 0 2006.201.08:08:25.21#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:08:25.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:08:25.21#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:08:25.21#ibcon#*before write, iclass 23, count 0 2006.201.08:08:25.21#ibcon#enter sib2, iclass 23, count 0 2006.201.08:08:25.21#ibcon#flushed, iclass 23, count 0 2006.201.08:08:25.21#ibcon#about to write, iclass 23, count 0 2006.201.08:08:25.21#ibcon#wrote, iclass 23, count 0 2006.201.08:08:25.21#ibcon#about to read 3, iclass 23, count 0 2006.201.08:08:25.25#ibcon#read 3, iclass 23, count 0 2006.201.08:08:25.25#ibcon#about to read 4, iclass 23, count 0 2006.201.08:08:25.25#ibcon#read 4, iclass 23, count 0 2006.201.08:08:25.25#ibcon#about to read 5, iclass 23, count 0 2006.201.08:08:25.25#ibcon#read 5, iclass 23, count 0 2006.201.08:08:25.25#ibcon#about to read 6, iclass 23, count 0 2006.201.08:08:25.25#ibcon#read 6, iclass 23, count 0 2006.201.08:08:25.25#ibcon#end of sib2, iclass 23, count 0 2006.201.08:08:25.25#ibcon#*after write, iclass 23, count 0 2006.201.08:08:25.25#ibcon#*before return 0, iclass 23, count 0 2006.201.08:08:25.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:25.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:25.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:08:25.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:08:25.25$vck44/va=7,5 2006.201.08:08:25.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.08:08:25.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.08:08:25.25#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:25.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:25.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:25.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:25.31#ibcon#enter wrdev, iclass 25, count 2 2006.201.08:08:25.31#ibcon#first serial, iclass 25, count 2 2006.201.08:08:25.31#ibcon#enter sib2, iclass 25, count 2 2006.201.08:08:25.31#ibcon#flushed, iclass 25, count 2 2006.201.08:08:25.31#ibcon#about to write, iclass 25, count 2 2006.201.08:08:25.31#ibcon#wrote, iclass 25, count 2 2006.201.08:08:25.31#ibcon#about to read 3, iclass 25, count 2 2006.201.08:08:25.33#ibcon#read 3, iclass 25, count 2 2006.201.08:08:25.33#ibcon#about to read 4, iclass 25, count 2 2006.201.08:08:25.33#ibcon#read 4, iclass 25, count 2 2006.201.08:08:25.33#ibcon#about to read 5, iclass 25, count 2 2006.201.08:08:25.33#ibcon#read 5, iclass 25, count 2 2006.201.08:08:25.33#ibcon#about to read 6, iclass 25, count 2 2006.201.08:08:25.33#ibcon#read 6, iclass 25, count 2 2006.201.08:08:25.33#ibcon#end of sib2, iclass 25, count 2 2006.201.08:08:25.33#ibcon#*mode == 0, iclass 25, count 2 2006.201.08:08:25.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.08:08:25.33#ibcon#[25=AT07-05\r\n] 2006.201.08:08:25.33#ibcon#*before write, iclass 25, count 2 2006.201.08:08:25.33#ibcon#enter sib2, iclass 25, count 2 2006.201.08:08:25.33#ibcon#flushed, iclass 25, count 2 2006.201.08:08:25.33#ibcon#about to write, iclass 25, count 2 2006.201.08:08:25.33#ibcon#wrote, iclass 25, count 2 2006.201.08:08:25.33#ibcon#about to read 3, iclass 25, count 2 2006.201.08:08:25.36#ibcon#read 3, iclass 25, count 2 2006.201.08:08:25.36#ibcon#about to read 4, iclass 25, count 2 2006.201.08:08:25.36#ibcon#read 4, iclass 25, count 2 2006.201.08:08:25.36#ibcon#about to read 5, iclass 25, count 2 2006.201.08:08:25.36#ibcon#read 5, iclass 25, count 2 2006.201.08:08:25.36#ibcon#about to read 6, iclass 25, count 2 2006.201.08:08:25.36#ibcon#read 6, iclass 25, count 2 2006.201.08:08:25.36#ibcon#end of sib2, iclass 25, count 2 2006.201.08:08:25.36#ibcon#*after write, iclass 25, count 2 2006.201.08:08:25.36#ibcon#*before return 0, iclass 25, count 2 2006.201.08:08:25.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:25.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:25.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.08:08:25.36#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:25.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:25.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:25.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:25.48#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:08:25.48#ibcon#first serial, iclass 25, count 0 2006.201.08:08:25.48#ibcon#enter sib2, iclass 25, count 0 2006.201.08:08:25.48#ibcon#flushed, iclass 25, count 0 2006.201.08:08:25.48#ibcon#about to write, iclass 25, count 0 2006.201.08:08:25.48#ibcon#wrote, iclass 25, count 0 2006.201.08:08:25.48#ibcon#about to read 3, iclass 25, count 0 2006.201.08:08:25.50#ibcon#read 3, iclass 25, count 0 2006.201.08:08:25.50#ibcon#about to read 4, iclass 25, count 0 2006.201.08:08:25.50#ibcon#read 4, iclass 25, count 0 2006.201.08:08:25.50#ibcon#about to read 5, iclass 25, count 0 2006.201.08:08:25.50#ibcon#read 5, iclass 25, count 0 2006.201.08:08:25.50#ibcon#about to read 6, iclass 25, count 0 2006.201.08:08:25.50#ibcon#read 6, iclass 25, count 0 2006.201.08:08:25.50#ibcon#end of sib2, iclass 25, count 0 2006.201.08:08:25.50#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:08:25.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:08:25.50#ibcon#[25=USB\r\n] 2006.201.08:08:25.50#ibcon#*before write, iclass 25, count 0 2006.201.08:08:25.50#ibcon#enter sib2, iclass 25, count 0 2006.201.08:08:25.50#ibcon#flushed, iclass 25, count 0 2006.201.08:08:25.50#ibcon#about to write, iclass 25, count 0 2006.201.08:08:25.50#ibcon#wrote, iclass 25, count 0 2006.201.08:08:25.50#ibcon#about to read 3, iclass 25, count 0 2006.201.08:08:25.53#ibcon#read 3, iclass 25, count 0 2006.201.08:08:25.53#ibcon#about to read 4, iclass 25, count 0 2006.201.08:08:25.53#ibcon#read 4, iclass 25, count 0 2006.201.08:08:25.53#ibcon#about to read 5, iclass 25, count 0 2006.201.08:08:25.53#ibcon#read 5, iclass 25, count 0 2006.201.08:08:25.53#ibcon#about to read 6, iclass 25, count 0 2006.201.08:08:25.53#ibcon#read 6, iclass 25, count 0 2006.201.08:08:25.53#ibcon#end of sib2, iclass 25, count 0 2006.201.08:08:25.53#ibcon#*after write, iclass 25, count 0 2006.201.08:08:25.53#ibcon#*before return 0, iclass 25, count 0 2006.201.08:08:25.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:25.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:25.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:08:25.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:08:25.53$vck44/valo=8,884.99 2006.201.08:08:25.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.08:08:25.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.08:08:25.53#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:25.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:08:25.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:08:25.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:08:25.53#ibcon#enter wrdev, iclass 27, count 0 2006.201.08:08:25.53#ibcon#first serial, iclass 27, count 0 2006.201.08:08:25.53#ibcon#enter sib2, iclass 27, count 0 2006.201.08:08:25.53#ibcon#flushed, iclass 27, count 0 2006.201.08:08:25.53#ibcon#about to write, iclass 27, count 0 2006.201.08:08:25.53#ibcon#wrote, iclass 27, count 0 2006.201.08:08:25.53#ibcon#about to read 3, iclass 27, count 0 2006.201.08:08:25.55#ibcon#read 3, iclass 27, count 0 2006.201.08:08:25.55#ibcon#about to read 4, iclass 27, count 0 2006.201.08:08:25.55#ibcon#read 4, iclass 27, count 0 2006.201.08:08:25.55#ibcon#about to read 5, iclass 27, count 0 2006.201.08:08:25.55#ibcon#read 5, iclass 27, count 0 2006.201.08:08:25.55#ibcon#about to read 6, iclass 27, count 0 2006.201.08:08:25.55#ibcon#read 6, iclass 27, count 0 2006.201.08:08:25.55#ibcon#end of sib2, iclass 27, count 0 2006.201.08:08:25.55#ibcon#*mode == 0, iclass 27, count 0 2006.201.08:08:25.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.08:08:25.55#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:08:25.55#ibcon#*before write, iclass 27, count 0 2006.201.08:08:25.55#ibcon#enter sib2, iclass 27, count 0 2006.201.08:08:25.55#ibcon#flushed, iclass 27, count 0 2006.201.08:08:25.55#ibcon#about to write, iclass 27, count 0 2006.201.08:08:25.55#ibcon#wrote, iclass 27, count 0 2006.201.08:08:25.55#ibcon#about to read 3, iclass 27, count 0 2006.201.08:08:25.59#ibcon#read 3, iclass 27, count 0 2006.201.08:08:25.59#ibcon#about to read 4, iclass 27, count 0 2006.201.08:08:25.59#ibcon#read 4, iclass 27, count 0 2006.201.08:08:25.59#ibcon#about to read 5, iclass 27, count 0 2006.201.08:08:25.59#ibcon#read 5, iclass 27, count 0 2006.201.08:08:25.59#ibcon#about to read 6, iclass 27, count 0 2006.201.08:08:25.59#ibcon#read 6, iclass 27, count 0 2006.201.08:08:25.59#ibcon#end of sib2, iclass 27, count 0 2006.201.08:08:25.59#ibcon#*after write, iclass 27, count 0 2006.201.08:08:25.59#ibcon#*before return 0, iclass 27, count 0 2006.201.08:08:25.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:08:25.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:08:25.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.08:08:25.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.08:08:25.59$vck44/va=8,4 2006.201.08:08:25.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.08:08:25.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.08:08:25.59#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:25.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:08:25.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:08:25.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:08:25.65#ibcon#enter wrdev, iclass 29, count 2 2006.201.08:08:25.65#ibcon#first serial, iclass 29, count 2 2006.201.08:08:25.65#ibcon#enter sib2, iclass 29, count 2 2006.201.08:08:25.65#ibcon#flushed, iclass 29, count 2 2006.201.08:08:25.65#ibcon#about to write, iclass 29, count 2 2006.201.08:08:25.65#ibcon#wrote, iclass 29, count 2 2006.201.08:08:25.65#ibcon#about to read 3, iclass 29, count 2 2006.201.08:08:25.67#ibcon#read 3, iclass 29, count 2 2006.201.08:08:25.67#ibcon#about to read 4, iclass 29, count 2 2006.201.08:08:25.67#ibcon#read 4, iclass 29, count 2 2006.201.08:08:25.67#ibcon#about to read 5, iclass 29, count 2 2006.201.08:08:25.67#ibcon#read 5, iclass 29, count 2 2006.201.08:08:25.67#ibcon#about to read 6, iclass 29, count 2 2006.201.08:08:25.67#ibcon#read 6, iclass 29, count 2 2006.201.08:08:25.67#ibcon#end of sib2, iclass 29, count 2 2006.201.08:08:25.67#ibcon#*mode == 0, iclass 29, count 2 2006.201.08:08:25.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.08:08:25.67#ibcon#[25=AT08-04\r\n] 2006.201.08:08:25.67#ibcon#*before write, iclass 29, count 2 2006.201.08:08:25.67#ibcon#enter sib2, iclass 29, count 2 2006.201.08:08:25.67#ibcon#flushed, iclass 29, count 2 2006.201.08:08:25.67#ibcon#about to write, iclass 29, count 2 2006.201.08:08:25.67#ibcon#wrote, iclass 29, count 2 2006.201.08:08:25.67#ibcon#about to read 3, iclass 29, count 2 2006.201.08:08:25.70#ibcon#read 3, iclass 29, count 2 2006.201.08:08:25.70#ibcon#about to read 4, iclass 29, count 2 2006.201.08:08:25.70#ibcon#read 4, iclass 29, count 2 2006.201.08:08:25.70#ibcon#about to read 5, iclass 29, count 2 2006.201.08:08:25.70#ibcon#read 5, iclass 29, count 2 2006.201.08:08:25.70#ibcon#about to read 6, iclass 29, count 2 2006.201.08:08:25.70#ibcon#read 6, iclass 29, count 2 2006.201.08:08:25.70#ibcon#end of sib2, iclass 29, count 2 2006.201.08:08:25.70#ibcon#*after write, iclass 29, count 2 2006.201.08:08:25.70#ibcon#*before return 0, iclass 29, count 2 2006.201.08:08:25.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:08:25.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:08:25.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.08:08:25.70#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:25.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:08:25.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:08:25.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:08:25.82#ibcon#enter wrdev, iclass 29, count 0 2006.201.08:08:25.82#ibcon#first serial, iclass 29, count 0 2006.201.08:08:25.82#ibcon#enter sib2, iclass 29, count 0 2006.201.08:08:25.82#ibcon#flushed, iclass 29, count 0 2006.201.08:08:25.82#ibcon#about to write, iclass 29, count 0 2006.201.08:08:25.82#ibcon#wrote, iclass 29, count 0 2006.201.08:08:25.82#ibcon#about to read 3, iclass 29, count 0 2006.201.08:08:25.84#ibcon#read 3, iclass 29, count 0 2006.201.08:08:25.84#ibcon#about to read 4, iclass 29, count 0 2006.201.08:08:25.84#ibcon#read 4, iclass 29, count 0 2006.201.08:08:25.84#ibcon#about to read 5, iclass 29, count 0 2006.201.08:08:25.84#ibcon#read 5, iclass 29, count 0 2006.201.08:08:25.84#ibcon#about to read 6, iclass 29, count 0 2006.201.08:08:25.84#ibcon#read 6, iclass 29, count 0 2006.201.08:08:25.84#ibcon#end of sib2, iclass 29, count 0 2006.201.08:08:25.84#ibcon#*mode == 0, iclass 29, count 0 2006.201.08:08:25.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.08:08:25.84#ibcon#[25=USB\r\n] 2006.201.08:08:25.84#ibcon#*before write, iclass 29, count 0 2006.201.08:08:25.84#ibcon#enter sib2, iclass 29, count 0 2006.201.08:08:25.84#ibcon#flushed, iclass 29, count 0 2006.201.08:08:25.84#ibcon#about to write, iclass 29, count 0 2006.201.08:08:25.84#ibcon#wrote, iclass 29, count 0 2006.201.08:08:25.84#ibcon#about to read 3, iclass 29, count 0 2006.201.08:08:25.87#ibcon#read 3, iclass 29, count 0 2006.201.08:08:25.87#ibcon#about to read 4, iclass 29, count 0 2006.201.08:08:25.87#ibcon#read 4, iclass 29, count 0 2006.201.08:08:25.87#ibcon#about to read 5, iclass 29, count 0 2006.201.08:08:25.87#ibcon#read 5, iclass 29, count 0 2006.201.08:08:25.87#ibcon#about to read 6, iclass 29, count 0 2006.201.08:08:25.87#ibcon#read 6, iclass 29, count 0 2006.201.08:08:25.87#ibcon#end of sib2, iclass 29, count 0 2006.201.08:08:25.87#ibcon#*after write, iclass 29, count 0 2006.201.08:08:25.87#ibcon#*before return 0, iclass 29, count 0 2006.201.08:08:25.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:08:25.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:08:25.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.08:08:25.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.08:08:25.87$vck44/vblo=1,629.99 2006.201.08:08:25.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.08:08:25.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.08:08:25.87#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:25.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:25.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:25.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:25.87#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:08:25.87#ibcon#first serial, iclass 31, count 0 2006.201.08:08:25.87#ibcon#enter sib2, iclass 31, count 0 2006.201.08:08:25.87#ibcon#flushed, iclass 31, count 0 2006.201.08:08:25.87#ibcon#about to write, iclass 31, count 0 2006.201.08:08:25.87#ibcon#wrote, iclass 31, count 0 2006.201.08:08:25.87#ibcon#about to read 3, iclass 31, count 0 2006.201.08:08:25.89#ibcon#read 3, iclass 31, count 0 2006.201.08:08:25.89#ibcon#about to read 4, iclass 31, count 0 2006.201.08:08:25.89#ibcon#read 4, iclass 31, count 0 2006.201.08:08:25.89#ibcon#about to read 5, iclass 31, count 0 2006.201.08:08:25.89#ibcon#read 5, iclass 31, count 0 2006.201.08:08:25.89#ibcon#about to read 6, iclass 31, count 0 2006.201.08:08:25.89#ibcon#read 6, iclass 31, count 0 2006.201.08:08:25.89#ibcon#end of sib2, iclass 31, count 0 2006.201.08:08:25.89#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:08:25.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:08:25.89#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:08:25.89#ibcon#*before write, iclass 31, count 0 2006.201.08:08:25.89#ibcon#enter sib2, iclass 31, count 0 2006.201.08:08:25.89#ibcon#flushed, iclass 31, count 0 2006.201.08:08:25.89#ibcon#about to write, iclass 31, count 0 2006.201.08:08:25.89#ibcon#wrote, iclass 31, count 0 2006.201.08:08:25.89#ibcon#about to read 3, iclass 31, count 0 2006.201.08:08:25.94#ibcon#read 3, iclass 31, count 0 2006.201.08:08:25.94#ibcon#about to read 4, iclass 31, count 0 2006.201.08:08:25.94#ibcon#read 4, iclass 31, count 0 2006.201.08:08:25.94#ibcon#about to read 5, iclass 31, count 0 2006.201.08:08:25.94#ibcon#read 5, iclass 31, count 0 2006.201.08:08:25.94#ibcon#about to read 6, iclass 31, count 0 2006.201.08:08:25.94#ibcon#read 6, iclass 31, count 0 2006.201.08:08:25.94#ibcon#end of sib2, iclass 31, count 0 2006.201.08:08:25.94#ibcon#*after write, iclass 31, count 0 2006.201.08:08:25.94#ibcon#*before return 0, iclass 31, count 0 2006.201.08:08:25.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:25.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:25.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:08:25.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:08:25.94$vck44/vb=1,4 2006.201.08:08:25.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.08:08:25.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.08:08:25.94#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:25.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:08:25.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:08:25.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:08:25.94#ibcon#enter wrdev, iclass 33, count 2 2006.201.08:08:25.94#ibcon#first serial, iclass 33, count 2 2006.201.08:08:25.94#ibcon#enter sib2, iclass 33, count 2 2006.201.08:08:25.94#ibcon#flushed, iclass 33, count 2 2006.201.08:08:25.94#ibcon#about to write, iclass 33, count 2 2006.201.08:08:25.94#ibcon#wrote, iclass 33, count 2 2006.201.08:08:25.94#ibcon#about to read 3, iclass 33, count 2 2006.201.08:08:25.96#ibcon#read 3, iclass 33, count 2 2006.201.08:08:25.96#ibcon#about to read 4, iclass 33, count 2 2006.201.08:08:25.96#ibcon#read 4, iclass 33, count 2 2006.201.08:08:25.96#ibcon#about to read 5, iclass 33, count 2 2006.201.08:08:25.96#ibcon#read 5, iclass 33, count 2 2006.201.08:08:25.96#ibcon#about to read 6, iclass 33, count 2 2006.201.08:08:25.96#ibcon#read 6, iclass 33, count 2 2006.201.08:08:25.96#ibcon#end of sib2, iclass 33, count 2 2006.201.08:08:25.96#ibcon#*mode == 0, iclass 33, count 2 2006.201.08:08:25.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.08:08:25.96#ibcon#[27=AT01-04\r\n] 2006.201.08:08:25.96#ibcon#*before write, iclass 33, count 2 2006.201.08:08:25.96#ibcon#enter sib2, iclass 33, count 2 2006.201.08:08:25.96#ibcon#flushed, iclass 33, count 2 2006.201.08:08:25.96#ibcon#about to write, iclass 33, count 2 2006.201.08:08:25.96#ibcon#wrote, iclass 33, count 2 2006.201.08:08:25.96#ibcon#about to read 3, iclass 33, count 2 2006.201.08:08:25.99#ibcon#read 3, iclass 33, count 2 2006.201.08:08:25.99#ibcon#about to read 4, iclass 33, count 2 2006.201.08:08:25.99#ibcon#read 4, iclass 33, count 2 2006.201.08:08:25.99#ibcon#about to read 5, iclass 33, count 2 2006.201.08:08:25.99#ibcon#read 5, iclass 33, count 2 2006.201.08:08:25.99#ibcon#about to read 6, iclass 33, count 2 2006.201.08:08:25.99#ibcon#read 6, iclass 33, count 2 2006.201.08:08:25.99#ibcon#end of sib2, iclass 33, count 2 2006.201.08:08:25.99#ibcon#*after write, iclass 33, count 2 2006.201.08:08:25.99#ibcon#*before return 0, iclass 33, count 2 2006.201.08:08:25.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:08:25.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:08:25.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.08:08:25.99#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:25.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:08:26.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:08:26.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:08:26.11#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:08:26.11#ibcon#first serial, iclass 33, count 0 2006.201.08:08:26.11#ibcon#enter sib2, iclass 33, count 0 2006.201.08:08:26.11#ibcon#flushed, iclass 33, count 0 2006.201.08:08:26.11#ibcon#about to write, iclass 33, count 0 2006.201.08:08:26.11#ibcon#wrote, iclass 33, count 0 2006.201.08:08:26.11#ibcon#about to read 3, iclass 33, count 0 2006.201.08:08:26.13#ibcon#read 3, iclass 33, count 0 2006.201.08:08:26.13#ibcon#about to read 4, iclass 33, count 0 2006.201.08:08:26.13#ibcon#read 4, iclass 33, count 0 2006.201.08:08:26.13#ibcon#about to read 5, iclass 33, count 0 2006.201.08:08:26.13#ibcon#read 5, iclass 33, count 0 2006.201.08:08:26.13#ibcon#about to read 6, iclass 33, count 0 2006.201.08:08:26.13#ibcon#read 6, iclass 33, count 0 2006.201.08:08:26.13#ibcon#end of sib2, iclass 33, count 0 2006.201.08:08:26.13#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:08:26.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:08:26.13#ibcon#[27=USB\r\n] 2006.201.08:08:26.13#ibcon#*before write, iclass 33, count 0 2006.201.08:08:26.13#ibcon#enter sib2, iclass 33, count 0 2006.201.08:08:26.13#ibcon#flushed, iclass 33, count 0 2006.201.08:08:26.13#ibcon#about to write, iclass 33, count 0 2006.201.08:08:26.13#ibcon#wrote, iclass 33, count 0 2006.201.08:08:26.13#ibcon#about to read 3, iclass 33, count 0 2006.201.08:08:26.16#ibcon#read 3, iclass 33, count 0 2006.201.08:08:26.16#ibcon#about to read 4, iclass 33, count 0 2006.201.08:08:26.16#ibcon#read 4, iclass 33, count 0 2006.201.08:08:26.16#ibcon#about to read 5, iclass 33, count 0 2006.201.08:08:26.16#ibcon#read 5, iclass 33, count 0 2006.201.08:08:26.16#ibcon#about to read 6, iclass 33, count 0 2006.201.08:08:26.16#ibcon#read 6, iclass 33, count 0 2006.201.08:08:26.16#ibcon#end of sib2, iclass 33, count 0 2006.201.08:08:26.16#ibcon#*after write, iclass 33, count 0 2006.201.08:08:26.16#ibcon#*before return 0, iclass 33, count 0 2006.201.08:08:26.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:08:26.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:08:26.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:08:26.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:08:26.16$vck44/vblo=2,634.99 2006.201.08:08:26.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.08:08:26.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.08:08:26.16#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:26.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:26.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:26.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:26.16#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:08:26.16#ibcon#first serial, iclass 35, count 0 2006.201.08:08:26.16#ibcon#enter sib2, iclass 35, count 0 2006.201.08:08:26.16#ibcon#flushed, iclass 35, count 0 2006.201.08:08:26.16#ibcon#about to write, iclass 35, count 0 2006.201.08:08:26.16#ibcon#wrote, iclass 35, count 0 2006.201.08:08:26.16#ibcon#about to read 3, iclass 35, count 0 2006.201.08:08:26.18#ibcon#read 3, iclass 35, count 0 2006.201.08:08:26.18#ibcon#about to read 4, iclass 35, count 0 2006.201.08:08:26.18#ibcon#read 4, iclass 35, count 0 2006.201.08:08:26.18#ibcon#about to read 5, iclass 35, count 0 2006.201.08:08:26.18#ibcon#read 5, iclass 35, count 0 2006.201.08:08:26.18#ibcon#about to read 6, iclass 35, count 0 2006.201.08:08:26.18#ibcon#read 6, iclass 35, count 0 2006.201.08:08:26.18#ibcon#end of sib2, iclass 35, count 0 2006.201.08:08:26.18#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:08:26.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:08:26.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:08:26.18#ibcon#*before write, iclass 35, count 0 2006.201.08:08:26.18#ibcon#enter sib2, iclass 35, count 0 2006.201.08:08:26.18#ibcon#flushed, iclass 35, count 0 2006.201.08:08:26.18#ibcon#about to write, iclass 35, count 0 2006.201.08:08:26.18#ibcon#wrote, iclass 35, count 0 2006.201.08:08:26.18#ibcon#about to read 3, iclass 35, count 0 2006.201.08:08:26.22#ibcon#read 3, iclass 35, count 0 2006.201.08:08:26.22#ibcon#about to read 4, iclass 35, count 0 2006.201.08:08:26.22#ibcon#read 4, iclass 35, count 0 2006.201.08:08:26.22#ibcon#about to read 5, iclass 35, count 0 2006.201.08:08:26.22#ibcon#read 5, iclass 35, count 0 2006.201.08:08:26.22#ibcon#about to read 6, iclass 35, count 0 2006.201.08:08:26.22#ibcon#read 6, iclass 35, count 0 2006.201.08:08:26.22#ibcon#end of sib2, iclass 35, count 0 2006.201.08:08:26.22#ibcon#*after write, iclass 35, count 0 2006.201.08:08:26.22#ibcon#*before return 0, iclass 35, count 0 2006.201.08:08:26.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:26.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:08:26.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:08:26.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:08:26.22$vck44/vb=2,5 2006.201.08:08:26.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.08:08:26.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.08:08:26.22#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:26.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:26.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:26.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:26.28#ibcon#enter wrdev, iclass 37, count 2 2006.201.08:08:26.28#ibcon#first serial, iclass 37, count 2 2006.201.08:08:26.28#ibcon#enter sib2, iclass 37, count 2 2006.201.08:08:26.28#ibcon#flushed, iclass 37, count 2 2006.201.08:08:26.28#ibcon#about to write, iclass 37, count 2 2006.201.08:08:26.28#ibcon#wrote, iclass 37, count 2 2006.201.08:08:26.28#ibcon#about to read 3, iclass 37, count 2 2006.201.08:08:26.30#ibcon#read 3, iclass 37, count 2 2006.201.08:08:26.30#ibcon#about to read 4, iclass 37, count 2 2006.201.08:08:26.30#ibcon#read 4, iclass 37, count 2 2006.201.08:08:26.30#ibcon#about to read 5, iclass 37, count 2 2006.201.08:08:26.30#ibcon#read 5, iclass 37, count 2 2006.201.08:08:26.30#ibcon#about to read 6, iclass 37, count 2 2006.201.08:08:26.30#ibcon#read 6, iclass 37, count 2 2006.201.08:08:26.30#ibcon#end of sib2, iclass 37, count 2 2006.201.08:08:26.30#ibcon#*mode == 0, iclass 37, count 2 2006.201.08:08:26.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.08:08:26.30#ibcon#[27=AT02-05\r\n] 2006.201.08:08:26.30#ibcon#*before write, iclass 37, count 2 2006.201.08:08:26.30#ibcon#enter sib2, iclass 37, count 2 2006.201.08:08:26.30#ibcon#flushed, iclass 37, count 2 2006.201.08:08:26.30#ibcon#about to write, iclass 37, count 2 2006.201.08:08:26.30#ibcon#wrote, iclass 37, count 2 2006.201.08:08:26.30#ibcon#about to read 3, iclass 37, count 2 2006.201.08:08:26.33#ibcon#read 3, iclass 37, count 2 2006.201.08:08:26.33#ibcon#about to read 4, iclass 37, count 2 2006.201.08:08:26.33#ibcon#read 4, iclass 37, count 2 2006.201.08:08:26.33#ibcon#about to read 5, iclass 37, count 2 2006.201.08:08:26.33#ibcon#read 5, iclass 37, count 2 2006.201.08:08:26.33#ibcon#about to read 6, iclass 37, count 2 2006.201.08:08:26.33#ibcon#read 6, iclass 37, count 2 2006.201.08:08:26.33#ibcon#end of sib2, iclass 37, count 2 2006.201.08:08:26.33#ibcon#*after write, iclass 37, count 2 2006.201.08:08:26.33#ibcon#*before return 0, iclass 37, count 2 2006.201.08:08:26.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:26.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:08:26.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.08:08:26.33#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:26.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:26.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:26.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:26.45#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:08:26.45#ibcon#first serial, iclass 37, count 0 2006.201.08:08:26.45#ibcon#enter sib2, iclass 37, count 0 2006.201.08:08:26.45#ibcon#flushed, iclass 37, count 0 2006.201.08:08:26.45#ibcon#about to write, iclass 37, count 0 2006.201.08:08:26.45#ibcon#wrote, iclass 37, count 0 2006.201.08:08:26.45#ibcon#about to read 3, iclass 37, count 0 2006.201.08:08:26.47#ibcon#read 3, iclass 37, count 0 2006.201.08:08:26.47#ibcon#about to read 4, iclass 37, count 0 2006.201.08:08:26.47#ibcon#read 4, iclass 37, count 0 2006.201.08:08:26.47#ibcon#about to read 5, iclass 37, count 0 2006.201.08:08:26.47#ibcon#read 5, iclass 37, count 0 2006.201.08:08:26.47#ibcon#about to read 6, iclass 37, count 0 2006.201.08:08:26.47#ibcon#read 6, iclass 37, count 0 2006.201.08:08:26.47#ibcon#end of sib2, iclass 37, count 0 2006.201.08:08:26.47#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:08:26.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:08:26.47#ibcon#[27=USB\r\n] 2006.201.08:08:26.47#ibcon#*before write, iclass 37, count 0 2006.201.08:08:26.47#ibcon#enter sib2, iclass 37, count 0 2006.201.08:08:26.47#ibcon#flushed, iclass 37, count 0 2006.201.08:08:26.47#ibcon#about to write, iclass 37, count 0 2006.201.08:08:26.47#ibcon#wrote, iclass 37, count 0 2006.201.08:08:26.47#ibcon#about to read 3, iclass 37, count 0 2006.201.08:08:26.50#ibcon#read 3, iclass 37, count 0 2006.201.08:08:26.50#ibcon#about to read 4, iclass 37, count 0 2006.201.08:08:26.50#ibcon#read 4, iclass 37, count 0 2006.201.08:08:26.50#ibcon#about to read 5, iclass 37, count 0 2006.201.08:08:26.50#ibcon#read 5, iclass 37, count 0 2006.201.08:08:26.50#ibcon#about to read 6, iclass 37, count 0 2006.201.08:08:26.50#ibcon#read 6, iclass 37, count 0 2006.201.08:08:26.50#ibcon#end of sib2, iclass 37, count 0 2006.201.08:08:26.50#ibcon#*after write, iclass 37, count 0 2006.201.08:08:26.50#ibcon#*before return 0, iclass 37, count 0 2006.201.08:08:26.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:26.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:08:26.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:08:26.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:08:26.50$vck44/vblo=3,649.99 2006.201.08:08:26.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.08:08:26.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.08:08:26.50#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:26.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:26.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:26.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:26.50#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:08:26.50#ibcon#first serial, iclass 39, count 0 2006.201.08:08:26.50#ibcon#enter sib2, iclass 39, count 0 2006.201.08:08:26.50#ibcon#flushed, iclass 39, count 0 2006.201.08:08:26.50#ibcon#about to write, iclass 39, count 0 2006.201.08:08:26.50#ibcon#wrote, iclass 39, count 0 2006.201.08:08:26.50#ibcon#about to read 3, iclass 39, count 0 2006.201.08:08:26.52#ibcon#read 3, iclass 39, count 0 2006.201.08:08:26.52#ibcon#about to read 4, iclass 39, count 0 2006.201.08:08:26.52#ibcon#read 4, iclass 39, count 0 2006.201.08:08:26.52#ibcon#about to read 5, iclass 39, count 0 2006.201.08:08:26.52#ibcon#read 5, iclass 39, count 0 2006.201.08:08:26.52#ibcon#about to read 6, iclass 39, count 0 2006.201.08:08:26.52#ibcon#read 6, iclass 39, count 0 2006.201.08:08:26.52#ibcon#end of sib2, iclass 39, count 0 2006.201.08:08:26.52#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:08:26.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:08:26.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:08:26.52#ibcon#*before write, iclass 39, count 0 2006.201.08:08:26.52#ibcon#enter sib2, iclass 39, count 0 2006.201.08:08:26.52#ibcon#flushed, iclass 39, count 0 2006.201.08:08:26.52#ibcon#about to write, iclass 39, count 0 2006.201.08:08:26.52#ibcon#wrote, iclass 39, count 0 2006.201.08:08:26.52#ibcon#about to read 3, iclass 39, count 0 2006.201.08:08:26.56#ibcon#read 3, iclass 39, count 0 2006.201.08:08:26.56#ibcon#about to read 4, iclass 39, count 0 2006.201.08:08:26.56#ibcon#read 4, iclass 39, count 0 2006.201.08:08:26.56#ibcon#about to read 5, iclass 39, count 0 2006.201.08:08:26.56#ibcon#read 5, iclass 39, count 0 2006.201.08:08:26.56#ibcon#about to read 6, iclass 39, count 0 2006.201.08:08:26.56#ibcon#read 6, iclass 39, count 0 2006.201.08:08:26.56#ibcon#end of sib2, iclass 39, count 0 2006.201.08:08:26.56#ibcon#*after write, iclass 39, count 0 2006.201.08:08:26.56#ibcon#*before return 0, iclass 39, count 0 2006.201.08:08:26.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:26.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:08:26.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:08:26.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:08:26.56$vck44/vb=3,4 2006.201.08:08:26.56#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.08:08:26.56#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.08:08:26.56#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:26.56#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:26.62#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:26.62#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:26.62#ibcon#enter wrdev, iclass 2, count 2 2006.201.08:08:26.62#ibcon#first serial, iclass 2, count 2 2006.201.08:08:26.62#ibcon#enter sib2, iclass 2, count 2 2006.201.08:08:26.62#ibcon#flushed, iclass 2, count 2 2006.201.08:08:26.62#ibcon#about to write, iclass 2, count 2 2006.201.08:08:26.62#ibcon#wrote, iclass 2, count 2 2006.201.08:08:26.62#ibcon#about to read 3, iclass 2, count 2 2006.201.08:08:26.64#ibcon#read 3, iclass 2, count 2 2006.201.08:08:26.64#ibcon#about to read 4, iclass 2, count 2 2006.201.08:08:26.64#ibcon#read 4, iclass 2, count 2 2006.201.08:08:26.64#ibcon#about to read 5, iclass 2, count 2 2006.201.08:08:26.64#ibcon#read 5, iclass 2, count 2 2006.201.08:08:26.64#ibcon#about to read 6, iclass 2, count 2 2006.201.08:08:26.64#ibcon#read 6, iclass 2, count 2 2006.201.08:08:26.64#ibcon#end of sib2, iclass 2, count 2 2006.201.08:08:26.64#ibcon#*mode == 0, iclass 2, count 2 2006.201.08:08:26.64#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.08:08:26.64#ibcon#[27=AT03-04\r\n] 2006.201.08:08:26.64#ibcon#*before write, iclass 2, count 2 2006.201.08:08:26.64#ibcon#enter sib2, iclass 2, count 2 2006.201.08:08:26.64#ibcon#flushed, iclass 2, count 2 2006.201.08:08:26.64#ibcon#about to write, iclass 2, count 2 2006.201.08:08:26.64#ibcon#wrote, iclass 2, count 2 2006.201.08:08:26.64#ibcon#about to read 3, iclass 2, count 2 2006.201.08:08:26.67#ibcon#read 3, iclass 2, count 2 2006.201.08:08:26.67#ibcon#about to read 4, iclass 2, count 2 2006.201.08:08:26.67#ibcon#read 4, iclass 2, count 2 2006.201.08:08:26.67#ibcon#about to read 5, iclass 2, count 2 2006.201.08:08:26.67#ibcon#read 5, iclass 2, count 2 2006.201.08:08:26.67#ibcon#about to read 6, iclass 2, count 2 2006.201.08:08:26.67#ibcon#read 6, iclass 2, count 2 2006.201.08:08:26.67#ibcon#end of sib2, iclass 2, count 2 2006.201.08:08:26.67#ibcon#*after write, iclass 2, count 2 2006.201.08:08:26.67#ibcon#*before return 0, iclass 2, count 2 2006.201.08:08:26.67#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:26.67#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:08:26.67#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.08:08:26.67#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:26.67#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:26.79#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:26.79#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:26.79#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:08:26.79#ibcon#first serial, iclass 2, count 0 2006.201.08:08:26.79#ibcon#enter sib2, iclass 2, count 0 2006.201.08:08:26.79#ibcon#flushed, iclass 2, count 0 2006.201.08:08:26.79#ibcon#about to write, iclass 2, count 0 2006.201.08:08:26.79#ibcon#wrote, iclass 2, count 0 2006.201.08:08:26.79#ibcon#about to read 3, iclass 2, count 0 2006.201.08:08:26.81#ibcon#read 3, iclass 2, count 0 2006.201.08:08:26.81#ibcon#about to read 4, iclass 2, count 0 2006.201.08:08:26.81#ibcon#read 4, iclass 2, count 0 2006.201.08:08:26.81#ibcon#about to read 5, iclass 2, count 0 2006.201.08:08:26.81#ibcon#read 5, iclass 2, count 0 2006.201.08:08:26.81#ibcon#about to read 6, iclass 2, count 0 2006.201.08:08:26.81#ibcon#read 6, iclass 2, count 0 2006.201.08:08:26.81#ibcon#end of sib2, iclass 2, count 0 2006.201.08:08:26.81#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:08:26.81#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:08:26.81#ibcon#[27=USB\r\n] 2006.201.08:08:26.81#ibcon#*before write, iclass 2, count 0 2006.201.08:08:26.81#ibcon#enter sib2, iclass 2, count 0 2006.201.08:08:26.81#ibcon#flushed, iclass 2, count 0 2006.201.08:08:26.81#ibcon#about to write, iclass 2, count 0 2006.201.08:08:26.81#ibcon#wrote, iclass 2, count 0 2006.201.08:08:26.81#ibcon#about to read 3, iclass 2, count 0 2006.201.08:08:26.84#ibcon#read 3, iclass 2, count 0 2006.201.08:08:26.84#ibcon#about to read 4, iclass 2, count 0 2006.201.08:08:26.84#ibcon#read 4, iclass 2, count 0 2006.201.08:08:26.84#ibcon#about to read 5, iclass 2, count 0 2006.201.08:08:26.84#ibcon#read 5, iclass 2, count 0 2006.201.08:08:26.84#ibcon#about to read 6, iclass 2, count 0 2006.201.08:08:26.84#ibcon#read 6, iclass 2, count 0 2006.201.08:08:26.84#ibcon#end of sib2, iclass 2, count 0 2006.201.08:08:26.84#ibcon#*after write, iclass 2, count 0 2006.201.08:08:26.84#ibcon#*before return 0, iclass 2, count 0 2006.201.08:08:26.84#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:26.84#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:08:26.84#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:08:26.84#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:08:26.84$vck44/vblo=4,679.99 2006.201.08:08:26.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.08:08:26.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.08:08:26.84#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:26.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:26.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:26.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:26.84#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:08:26.84#ibcon#first serial, iclass 5, count 0 2006.201.08:08:26.84#ibcon#enter sib2, iclass 5, count 0 2006.201.08:08:26.84#ibcon#flushed, iclass 5, count 0 2006.201.08:08:26.84#ibcon#about to write, iclass 5, count 0 2006.201.08:08:26.84#ibcon#wrote, iclass 5, count 0 2006.201.08:08:26.84#ibcon#about to read 3, iclass 5, count 0 2006.201.08:08:26.86#ibcon#read 3, iclass 5, count 0 2006.201.08:08:26.86#ibcon#about to read 4, iclass 5, count 0 2006.201.08:08:26.86#ibcon#read 4, iclass 5, count 0 2006.201.08:08:26.86#ibcon#about to read 5, iclass 5, count 0 2006.201.08:08:26.86#ibcon#read 5, iclass 5, count 0 2006.201.08:08:26.86#ibcon#about to read 6, iclass 5, count 0 2006.201.08:08:26.86#ibcon#read 6, iclass 5, count 0 2006.201.08:08:26.86#ibcon#end of sib2, iclass 5, count 0 2006.201.08:08:26.86#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:08:26.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:08:26.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:08:26.86#ibcon#*before write, iclass 5, count 0 2006.201.08:08:26.86#ibcon#enter sib2, iclass 5, count 0 2006.201.08:08:26.86#ibcon#flushed, iclass 5, count 0 2006.201.08:08:26.86#ibcon#about to write, iclass 5, count 0 2006.201.08:08:26.86#ibcon#wrote, iclass 5, count 0 2006.201.08:08:26.86#ibcon#about to read 3, iclass 5, count 0 2006.201.08:08:26.90#ibcon#read 3, iclass 5, count 0 2006.201.08:08:26.90#ibcon#about to read 4, iclass 5, count 0 2006.201.08:08:26.90#ibcon#read 4, iclass 5, count 0 2006.201.08:08:26.90#ibcon#about to read 5, iclass 5, count 0 2006.201.08:08:26.90#ibcon#read 5, iclass 5, count 0 2006.201.08:08:26.90#ibcon#about to read 6, iclass 5, count 0 2006.201.08:08:26.90#ibcon#read 6, iclass 5, count 0 2006.201.08:08:26.90#ibcon#end of sib2, iclass 5, count 0 2006.201.08:08:26.90#ibcon#*after write, iclass 5, count 0 2006.201.08:08:26.90#ibcon#*before return 0, iclass 5, count 0 2006.201.08:08:26.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:26.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:08:26.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:08:26.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:08:26.90$vck44/vb=4,5 2006.201.08:08:26.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.08:08:26.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.08:08:26.90#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:26.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:26.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:26.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:26.96#ibcon#enter wrdev, iclass 7, count 2 2006.201.08:08:26.96#ibcon#first serial, iclass 7, count 2 2006.201.08:08:26.96#ibcon#enter sib2, iclass 7, count 2 2006.201.08:08:26.96#ibcon#flushed, iclass 7, count 2 2006.201.08:08:26.96#ibcon#about to write, iclass 7, count 2 2006.201.08:08:26.96#ibcon#wrote, iclass 7, count 2 2006.201.08:08:26.96#ibcon#about to read 3, iclass 7, count 2 2006.201.08:08:26.98#ibcon#read 3, iclass 7, count 2 2006.201.08:08:26.98#ibcon#about to read 4, iclass 7, count 2 2006.201.08:08:26.98#ibcon#read 4, iclass 7, count 2 2006.201.08:08:26.98#ibcon#about to read 5, iclass 7, count 2 2006.201.08:08:26.98#ibcon#read 5, iclass 7, count 2 2006.201.08:08:26.98#ibcon#about to read 6, iclass 7, count 2 2006.201.08:08:26.98#ibcon#read 6, iclass 7, count 2 2006.201.08:08:26.98#ibcon#end of sib2, iclass 7, count 2 2006.201.08:08:26.98#ibcon#*mode == 0, iclass 7, count 2 2006.201.08:08:26.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.08:08:26.98#ibcon#[27=AT04-05\r\n] 2006.201.08:08:26.98#ibcon#*before write, iclass 7, count 2 2006.201.08:08:26.98#ibcon#enter sib2, iclass 7, count 2 2006.201.08:08:26.98#ibcon#flushed, iclass 7, count 2 2006.201.08:08:26.98#ibcon#about to write, iclass 7, count 2 2006.201.08:08:26.98#ibcon#wrote, iclass 7, count 2 2006.201.08:08:26.98#ibcon#about to read 3, iclass 7, count 2 2006.201.08:08:27.01#ibcon#read 3, iclass 7, count 2 2006.201.08:08:27.01#ibcon#about to read 4, iclass 7, count 2 2006.201.08:08:27.01#ibcon#read 4, iclass 7, count 2 2006.201.08:08:27.01#ibcon#about to read 5, iclass 7, count 2 2006.201.08:08:27.01#ibcon#read 5, iclass 7, count 2 2006.201.08:08:27.01#ibcon#about to read 6, iclass 7, count 2 2006.201.08:08:27.01#ibcon#read 6, iclass 7, count 2 2006.201.08:08:27.01#ibcon#end of sib2, iclass 7, count 2 2006.201.08:08:27.01#ibcon#*after write, iclass 7, count 2 2006.201.08:08:27.01#ibcon#*before return 0, iclass 7, count 2 2006.201.08:08:27.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:27.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:08:27.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.08:08:27.01#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:27.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:27.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:27.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:27.13#ibcon#enter wrdev, iclass 7, count 0 2006.201.08:08:27.13#ibcon#first serial, iclass 7, count 0 2006.201.08:08:27.13#ibcon#enter sib2, iclass 7, count 0 2006.201.08:08:27.13#ibcon#flushed, iclass 7, count 0 2006.201.08:08:27.13#ibcon#about to write, iclass 7, count 0 2006.201.08:08:27.13#ibcon#wrote, iclass 7, count 0 2006.201.08:08:27.13#ibcon#about to read 3, iclass 7, count 0 2006.201.08:08:27.15#ibcon#read 3, iclass 7, count 0 2006.201.08:08:27.15#ibcon#about to read 4, iclass 7, count 0 2006.201.08:08:27.15#ibcon#read 4, iclass 7, count 0 2006.201.08:08:27.15#ibcon#about to read 5, iclass 7, count 0 2006.201.08:08:27.15#ibcon#read 5, iclass 7, count 0 2006.201.08:08:27.15#ibcon#about to read 6, iclass 7, count 0 2006.201.08:08:27.15#ibcon#read 6, iclass 7, count 0 2006.201.08:08:27.15#ibcon#end of sib2, iclass 7, count 0 2006.201.08:08:27.15#ibcon#*mode == 0, iclass 7, count 0 2006.201.08:08:27.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.08:08:27.15#ibcon#[27=USB\r\n] 2006.201.08:08:27.15#ibcon#*before write, iclass 7, count 0 2006.201.08:08:27.15#ibcon#enter sib2, iclass 7, count 0 2006.201.08:08:27.15#ibcon#flushed, iclass 7, count 0 2006.201.08:08:27.15#ibcon#about to write, iclass 7, count 0 2006.201.08:08:27.15#ibcon#wrote, iclass 7, count 0 2006.201.08:08:27.15#ibcon#about to read 3, iclass 7, count 0 2006.201.08:08:27.18#ibcon#read 3, iclass 7, count 0 2006.201.08:08:27.18#ibcon#about to read 4, iclass 7, count 0 2006.201.08:08:27.18#ibcon#read 4, iclass 7, count 0 2006.201.08:08:27.18#ibcon#about to read 5, iclass 7, count 0 2006.201.08:08:27.18#ibcon#read 5, iclass 7, count 0 2006.201.08:08:27.18#ibcon#about to read 6, iclass 7, count 0 2006.201.08:08:27.18#ibcon#read 6, iclass 7, count 0 2006.201.08:08:27.18#ibcon#end of sib2, iclass 7, count 0 2006.201.08:08:27.18#ibcon#*after write, iclass 7, count 0 2006.201.08:08:27.18#ibcon#*before return 0, iclass 7, count 0 2006.201.08:08:27.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:27.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:08:27.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.08:08:27.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.08:08:27.18$vck44/vblo=5,709.99 2006.201.08:08:27.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.08:08:27.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.08:08:27.18#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:27.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:27.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:27.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:27.18#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:08:27.18#ibcon#first serial, iclass 11, count 0 2006.201.08:08:27.18#ibcon#enter sib2, iclass 11, count 0 2006.201.08:08:27.18#ibcon#flushed, iclass 11, count 0 2006.201.08:08:27.18#ibcon#about to write, iclass 11, count 0 2006.201.08:08:27.18#ibcon#wrote, iclass 11, count 0 2006.201.08:08:27.18#ibcon#about to read 3, iclass 11, count 0 2006.201.08:08:27.20#ibcon#read 3, iclass 11, count 0 2006.201.08:08:27.20#ibcon#about to read 4, iclass 11, count 0 2006.201.08:08:27.20#ibcon#read 4, iclass 11, count 0 2006.201.08:08:27.20#ibcon#about to read 5, iclass 11, count 0 2006.201.08:08:27.20#ibcon#read 5, iclass 11, count 0 2006.201.08:08:27.20#ibcon#about to read 6, iclass 11, count 0 2006.201.08:08:27.20#ibcon#read 6, iclass 11, count 0 2006.201.08:08:27.20#ibcon#end of sib2, iclass 11, count 0 2006.201.08:08:27.20#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:08:27.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:08:27.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:08:27.20#ibcon#*before write, iclass 11, count 0 2006.201.08:08:27.20#ibcon#enter sib2, iclass 11, count 0 2006.201.08:08:27.20#ibcon#flushed, iclass 11, count 0 2006.201.08:08:27.20#ibcon#about to write, iclass 11, count 0 2006.201.08:08:27.20#ibcon#wrote, iclass 11, count 0 2006.201.08:08:27.20#ibcon#about to read 3, iclass 11, count 0 2006.201.08:08:27.24#ibcon#read 3, iclass 11, count 0 2006.201.08:08:27.24#ibcon#about to read 4, iclass 11, count 0 2006.201.08:08:27.24#ibcon#read 4, iclass 11, count 0 2006.201.08:08:27.24#ibcon#about to read 5, iclass 11, count 0 2006.201.08:08:27.24#ibcon#read 5, iclass 11, count 0 2006.201.08:08:27.24#ibcon#about to read 6, iclass 11, count 0 2006.201.08:08:27.24#ibcon#read 6, iclass 11, count 0 2006.201.08:08:27.24#ibcon#end of sib2, iclass 11, count 0 2006.201.08:08:27.24#ibcon#*after write, iclass 11, count 0 2006.201.08:08:27.24#ibcon#*before return 0, iclass 11, count 0 2006.201.08:08:27.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:27.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:08:27.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:08:27.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:08:27.24$vck44/vb=5,4 2006.201.08:08:27.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.08:08:27.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.08:08:27.24#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:27.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:27.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:27.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:27.30#ibcon#enter wrdev, iclass 13, count 2 2006.201.08:08:27.30#ibcon#first serial, iclass 13, count 2 2006.201.08:08:27.30#ibcon#enter sib2, iclass 13, count 2 2006.201.08:08:27.30#ibcon#flushed, iclass 13, count 2 2006.201.08:08:27.30#ibcon#about to write, iclass 13, count 2 2006.201.08:08:27.30#ibcon#wrote, iclass 13, count 2 2006.201.08:08:27.30#ibcon#about to read 3, iclass 13, count 2 2006.201.08:08:27.32#ibcon#read 3, iclass 13, count 2 2006.201.08:08:27.32#ibcon#about to read 4, iclass 13, count 2 2006.201.08:08:27.32#ibcon#read 4, iclass 13, count 2 2006.201.08:08:27.32#ibcon#about to read 5, iclass 13, count 2 2006.201.08:08:27.32#ibcon#read 5, iclass 13, count 2 2006.201.08:08:27.32#ibcon#about to read 6, iclass 13, count 2 2006.201.08:08:27.32#ibcon#read 6, iclass 13, count 2 2006.201.08:08:27.32#ibcon#end of sib2, iclass 13, count 2 2006.201.08:08:27.32#ibcon#*mode == 0, iclass 13, count 2 2006.201.08:08:27.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.08:08:27.32#ibcon#[27=AT05-04\r\n] 2006.201.08:08:27.32#ibcon#*before write, iclass 13, count 2 2006.201.08:08:27.32#ibcon#enter sib2, iclass 13, count 2 2006.201.08:08:27.32#ibcon#flushed, iclass 13, count 2 2006.201.08:08:27.32#ibcon#about to write, iclass 13, count 2 2006.201.08:08:27.32#ibcon#wrote, iclass 13, count 2 2006.201.08:08:27.32#ibcon#about to read 3, iclass 13, count 2 2006.201.08:08:27.35#ibcon#read 3, iclass 13, count 2 2006.201.08:08:27.35#ibcon#about to read 4, iclass 13, count 2 2006.201.08:08:27.35#ibcon#read 4, iclass 13, count 2 2006.201.08:08:27.35#ibcon#about to read 5, iclass 13, count 2 2006.201.08:08:27.35#ibcon#read 5, iclass 13, count 2 2006.201.08:08:27.35#ibcon#about to read 6, iclass 13, count 2 2006.201.08:08:27.35#ibcon#read 6, iclass 13, count 2 2006.201.08:08:27.35#ibcon#end of sib2, iclass 13, count 2 2006.201.08:08:27.35#ibcon#*after write, iclass 13, count 2 2006.201.08:08:27.35#ibcon#*before return 0, iclass 13, count 2 2006.201.08:08:27.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:27.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:08:27.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.08:08:27.35#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:27.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:27.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:27.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:27.47#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:08:27.47#ibcon#first serial, iclass 13, count 0 2006.201.08:08:27.47#ibcon#enter sib2, iclass 13, count 0 2006.201.08:08:27.47#ibcon#flushed, iclass 13, count 0 2006.201.08:08:27.47#ibcon#about to write, iclass 13, count 0 2006.201.08:08:27.47#ibcon#wrote, iclass 13, count 0 2006.201.08:08:27.47#ibcon#about to read 3, iclass 13, count 0 2006.201.08:08:27.49#ibcon#read 3, iclass 13, count 0 2006.201.08:08:27.49#ibcon#about to read 4, iclass 13, count 0 2006.201.08:08:27.49#ibcon#read 4, iclass 13, count 0 2006.201.08:08:27.49#ibcon#about to read 5, iclass 13, count 0 2006.201.08:08:27.49#ibcon#read 5, iclass 13, count 0 2006.201.08:08:27.49#ibcon#about to read 6, iclass 13, count 0 2006.201.08:08:27.49#ibcon#read 6, iclass 13, count 0 2006.201.08:08:27.49#ibcon#end of sib2, iclass 13, count 0 2006.201.08:08:27.49#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:08:27.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:08:27.49#ibcon#[27=USB\r\n] 2006.201.08:08:27.49#ibcon#*before write, iclass 13, count 0 2006.201.08:08:27.49#ibcon#enter sib2, iclass 13, count 0 2006.201.08:08:27.49#ibcon#flushed, iclass 13, count 0 2006.201.08:08:27.49#ibcon#about to write, iclass 13, count 0 2006.201.08:08:27.49#ibcon#wrote, iclass 13, count 0 2006.201.08:08:27.49#ibcon#about to read 3, iclass 13, count 0 2006.201.08:08:27.52#ibcon#read 3, iclass 13, count 0 2006.201.08:08:27.52#ibcon#about to read 4, iclass 13, count 0 2006.201.08:08:27.52#ibcon#read 4, iclass 13, count 0 2006.201.08:08:27.52#ibcon#about to read 5, iclass 13, count 0 2006.201.08:08:27.52#ibcon#read 5, iclass 13, count 0 2006.201.08:08:27.52#ibcon#about to read 6, iclass 13, count 0 2006.201.08:08:27.52#ibcon#read 6, iclass 13, count 0 2006.201.08:08:27.52#ibcon#end of sib2, iclass 13, count 0 2006.201.08:08:27.52#ibcon#*after write, iclass 13, count 0 2006.201.08:08:27.52#ibcon#*before return 0, iclass 13, count 0 2006.201.08:08:27.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:27.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:08:27.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:08:27.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:08:27.52$vck44/vblo=6,719.99 2006.201.08:08:27.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.08:08:27.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.08:08:27.52#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:27.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:27.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:27.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:27.52#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:08:27.52#ibcon#first serial, iclass 15, count 0 2006.201.08:08:27.52#ibcon#enter sib2, iclass 15, count 0 2006.201.08:08:27.52#ibcon#flushed, iclass 15, count 0 2006.201.08:08:27.52#ibcon#about to write, iclass 15, count 0 2006.201.08:08:27.52#ibcon#wrote, iclass 15, count 0 2006.201.08:08:27.52#ibcon#about to read 3, iclass 15, count 0 2006.201.08:08:27.54#ibcon#read 3, iclass 15, count 0 2006.201.08:08:27.54#ibcon#about to read 4, iclass 15, count 0 2006.201.08:08:27.54#ibcon#read 4, iclass 15, count 0 2006.201.08:08:27.54#ibcon#about to read 5, iclass 15, count 0 2006.201.08:08:27.54#ibcon#read 5, iclass 15, count 0 2006.201.08:08:27.54#ibcon#about to read 6, iclass 15, count 0 2006.201.08:08:27.54#ibcon#read 6, iclass 15, count 0 2006.201.08:08:27.54#ibcon#end of sib2, iclass 15, count 0 2006.201.08:08:27.54#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:08:27.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:08:27.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:08:27.54#ibcon#*before write, iclass 15, count 0 2006.201.08:08:27.54#ibcon#enter sib2, iclass 15, count 0 2006.201.08:08:27.54#ibcon#flushed, iclass 15, count 0 2006.201.08:08:27.54#ibcon#about to write, iclass 15, count 0 2006.201.08:08:27.54#ibcon#wrote, iclass 15, count 0 2006.201.08:08:27.54#ibcon#about to read 3, iclass 15, count 0 2006.201.08:08:27.58#ibcon#read 3, iclass 15, count 0 2006.201.08:08:27.58#ibcon#about to read 4, iclass 15, count 0 2006.201.08:08:27.58#ibcon#read 4, iclass 15, count 0 2006.201.08:08:27.58#ibcon#about to read 5, iclass 15, count 0 2006.201.08:08:27.58#ibcon#read 5, iclass 15, count 0 2006.201.08:08:27.58#ibcon#about to read 6, iclass 15, count 0 2006.201.08:08:27.58#ibcon#read 6, iclass 15, count 0 2006.201.08:08:27.58#ibcon#end of sib2, iclass 15, count 0 2006.201.08:08:27.58#ibcon#*after write, iclass 15, count 0 2006.201.08:08:27.58#ibcon#*before return 0, iclass 15, count 0 2006.201.08:08:27.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:27.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:08:27.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:08:27.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:08:27.58$vck44/vb=6,4 2006.201.08:08:27.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.08:08:27.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.08:08:27.58#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:27.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:27.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:27.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:27.64#ibcon#enter wrdev, iclass 17, count 2 2006.201.08:08:27.64#ibcon#first serial, iclass 17, count 2 2006.201.08:08:27.64#ibcon#enter sib2, iclass 17, count 2 2006.201.08:08:27.64#ibcon#flushed, iclass 17, count 2 2006.201.08:08:27.64#ibcon#about to write, iclass 17, count 2 2006.201.08:08:27.64#ibcon#wrote, iclass 17, count 2 2006.201.08:08:27.64#ibcon#about to read 3, iclass 17, count 2 2006.201.08:08:27.66#ibcon#read 3, iclass 17, count 2 2006.201.08:08:27.66#ibcon#about to read 4, iclass 17, count 2 2006.201.08:08:27.66#ibcon#read 4, iclass 17, count 2 2006.201.08:08:27.66#ibcon#about to read 5, iclass 17, count 2 2006.201.08:08:27.66#ibcon#read 5, iclass 17, count 2 2006.201.08:08:27.66#ibcon#about to read 6, iclass 17, count 2 2006.201.08:08:27.66#ibcon#read 6, iclass 17, count 2 2006.201.08:08:27.66#ibcon#end of sib2, iclass 17, count 2 2006.201.08:08:27.66#ibcon#*mode == 0, iclass 17, count 2 2006.201.08:08:27.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.08:08:27.66#ibcon#[27=AT06-04\r\n] 2006.201.08:08:27.66#ibcon#*before write, iclass 17, count 2 2006.201.08:08:27.66#ibcon#enter sib2, iclass 17, count 2 2006.201.08:08:27.66#ibcon#flushed, iclass 17, count 2 2006.201.08:08:27.66#ibcon#about to write, iclass 17, count 2 2006.201.08:08:27.66#ibcon#wrote, iclass 17, count 2 2006.201.08:08:27.66#ibcon#about to read 3, iclass 17, count 2 2006.201.08:08:27.69#ibcon#read 3, iclass 17, count 2 2006.201.08:08:27.69#ibcon#about to read 4, iclass 17, count 2 2006.201.08:08:27.69#ibcon#read 4, iclass 17, count 2 2006.201.08:08:27.69#ibcon#about to read 5, iclass 17, count 2 2006.201.08:08:27.69#ibcon#read 5, iclass 17, count 2 2006.201.08:08:27.69#ibcon#about to read 6, iclass 17, count 2 2006.201.08:08:27.69#ibcon#read 6, iclass 17, count 2 2006.201.08:08:27.69#ibcon#end of sib2, iclass 17, count 2 2006.201.08:08:27.69#ibcon#*after write, iclass 17, count 2 2006.201.08:08:27.69#ibcon#*before return 0, iclass 17, count 2 2006.201.08:08:27.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:27.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:08:27.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.08:08:27.69#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:27.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:27.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:27.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:27.81#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:08:27.81#ibcon#first serial, iclass 17, count 0 2006.201.08:08:27.81#ibcon#enter sib2, iclass 17, count 0 2006.201.08:08:27.81#ibcon#flushed, iclass 17, count 0 2006.201.08:08:27.81#ibcon#about to write, iclass 17, count 0 2006.201.08:08:27.81#ibcon#wrote, iclass 17, count 0 2006.201.08:08:27.81#ibcon#about to read 3, iclass 17, count 0 2006.201.08:08:27.83#ibcon#read 3, iclass 17, count 0 2006.201.08:08:27.83#ibcon#about to read 4, iclass 17, count 0 2006.201.08:08:27.83#ibcon#read 4, iclass 17, count 0 2006.201.08:08:27.83#ibcon#about to read 5, iclass 17, count 0 2006.201.08:08:27.83#ibcon#read 5, iclass 17, count 0 2006.201.08:08:27.83#ibcon#about to read 6, iclass 17, count 0 2006.201.08:08:27.83#ibcon#read 6, iclass 17, count 0 2006.201.08:08:27.83#ibcon#end of sib2, iclass 17, count 0 2006.201.08:08:27.83#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:08:27.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:08:27.83#ibcon#[27=USB\r\n] 2006.201.08:08:27.83#ibcon#*before write, iclass 17, count 0 2006.201.08:08:27.83#ibcon#enter sib2, iclass 17, count 0 2006.201.08:08:27.83#ibcon#flushed, iclass 17, count 0 2006.201.08:08:27.83#ibcon#about to write, iclass 17, count 0 2006.201.08:08:27.83#ibcon#wrote, iclass 17, count 0 2006.201.08:08:27.83#ibcon#about to read 3, iclass 17, count 0 2006.201.08:08:27.86#ibcon#read 3, iclass 17, count 0 2006.201.08:08:27.86#ibcon#about to read 4, iclass 17, count 0 2006.201.08:08:27.86#ibcon#read 4, iclass 17, count 0 2006.201.08:08:27.86#ibcon#about to read 5, iclass 17, count 0 2006.201.08:08:27.86#ibcon#read 5, iclass 17, count 0 2006.201.08:08:27.86#ibcon#about to read 6, iclass 17, count 0 2006.201.08:08:27.86#ibcon#read 6, iclass 17, count 0 2006.201.08:08:27.86#ibcon#end of sib2, iclass 17, count 0 2006.201.08:08:27.86#ibcon#*after write, iclass 17, count 0 2006.201.08:08:27.86#ibcon#*before return 0, iclass 17, count 0 2006.201.08:08:27.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:27.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:08:27.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:08:27.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:08:27.86$vck44/vblo=7,734.99 2006.201.08:08:27.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.08:08:27.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.08:08:27.86#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:27.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:27.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:27.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:27.86#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:08:27.86#ibcon#first serial, iclass 19, count 0 2006.201.08:08:27.86#ibcon#enter sib2, iclass 19, count 0 2006.201.08:08:27.86#ibcon#flushed, iclass 19, count 0 2006.201.08:08:27.86#ibcon#about to write, iclass 19, count 0 2006.201.08:08:27.86#ibcon#wrote, iclass 19, count 0 2006.201.08:08:27.86#ibcon#about to read 3, iclass 19, count 0 2006.201.08:08:27.88#ibcon#read 3, iclass 19, count 0 2006.201.08:08:27.88#ibcon#about to read 4, iclass 19, count 0 2006.201.08:08:27.88#ibcon#read 4, iclass 19, count 0 2006.201.08:08:27.88#ibcon#about to read 5, iclass 19, count 0 2006.201.08:08:27.88#ibcon#read 5, iclass 19, count 0 2006.201.08:08:27.88#ibcon#about to read 6, iclass 19, count 0 2006.201.08:08:27.88#ibcon#read 6, iclass 19, count 0 2006.201.08:08:27.88#ibcon#end of sib2, iclass 19, count 0 2006.201.08:08:27.88#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:08:27.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:08:27.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:08:27.88#ibcon#*before write, iclass 19, count 0 2006.201.08:08:27.88#ibcon#enter sib2, iclass 19, count 0 2006.201.08:08:27.88#ibcon#flushed, iclass 19, count 0 2006.201.08:08:27.88#ibcon#about to write, iclass 19, count 0 2006.201.08:08:27.88#ibcon#wrote, iclass 19, count 0 2006.201.08:08:27.88#ibcon#about to read 3, iclass 19, count 0 2006.201.08:08:27.92#ibcon#read 3, iclass 19, count 0 2006.201.08:08:27.92#ibcon#about to read 4, iclass 19, count 0 2006.201.08:08:27.92#ibcon#read 4, iclass 19, count 0 2006.201.08:08:27.92#ibcon#about to read 5, iclass 19, count 0 2006.201.08:08:27.92#ibcon#read 5, iclass 19, count 0 2006.201.08:08:27.92#ibcon#about to read 6, iclass 19, count 0 2006.201.08:08:27.92#ibcon#read 6, iclass 19, count 0 2006.201.08:08:27.92#ibcon#end of sib2, iclass 19, count 0 2006.201.08:08:27.92#ibcon#*after write, iclass 19, count 0 2006.201.08:08:27.92#ibcon#*before return 0, iclass 19, count 0 2006.201.08:08:27.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:27.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:08:27.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:08:27.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:08:27.92$vck44/vb=7,4 2006.201.08:08:27.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.08:08:27.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.08:08:27.92#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:27.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:27.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:27.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:27.98#ibcon#enter wrdev, iclass 21, count 2 2006.201.08:08:27.98#ibcon#first serial, iclass 21, count 2 2006.201.08:08:27.98#ibcon#enter sib2, iclass 21, count 2 2006.201.08:08:27.98#ibcon#flushed, iclass 21, count 2 2006.201.08:08:27.98#ibcon#about to write, iclass 21, count 2 2006.201.08:08:27.98#ibcon#wrote, iclass 21, count 2 2006.201.08:08:27.98#ibcon#about to read 3, iclass 21, count 2 2006.201.08:08:28.00#ibcon#read 3, iclass 21, count 2 2006.201.08:08:28.00#ibcon#about to read 4, iclass 21, count 2 2006.201.08:08:28.00#ibcon#read 4, iclass 21, count 2 2006.201.08:08:28.00#ibcon#about to read 5, iclass 21, count 2 2006.201.08:08:28.00#ibcon#read 5, iclass 21, count 2 2006.201.08:08:28.00#ibcon#about to read 6, iclass 21, count 2 2006.201.08:08:28.00#ibcon#read 6, iclass 21, count 2 2006.201.08:08:28.00#ibcon#end of sib2, iclass 21, count 2 2006.201.08:08:28.00#ibcon#*mode == 0, iclass 21, count 2 2006.201.08:08:28.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.08:08:28.00#ibcon#[27=AT07-04\r\n] 2006.201.08:08:28.00#ibcon#*before write, iclass 21, count 2 2006.201.08:08:28.00#ibcon#enter sib2, iclass 21, count 2 2006.201.08:08:28.00#ibcon#flushed, iclass 21, count 2 2006.201.08:08:28.00#ibcon#about to write, iclass 21, count 2 2006.201.08:08:28.00#ibcon#wrote, iclass 21, count 2 2006.201.08:08:28.00#ibcon#about to read 3, iclass 21, count 2 2006.201.08:08:28.03#ibcon#read 3, iclass 21, count 2 2006.201.08:08:28.03#ibcon#about to read 4, iclass 21, count 2 2006.201.08:08:28.03#ibcon#read 4, iclass 21, count 2 2006.201.08:08:28.03#ibcon#about to read 5, iclass 21, count 2 2006.201.08:08:28.03#ibcon#read 5, iclass 21, count 2 2006.201.08:08:28.03#ibcon#about to read 6, iclass 21, count 2 2006.201.08:08:28.03#ibcon#read 6, iclass 21, count 2 2006.201.08:08:28.03#ibcon#end of sib2, iclass 21, count 2 2006.201.08:08:28.03#ibcon#*after write, iclass 21, count 2 2006.201.08:08:28.03#ibcon#*before return 0, iclass 21, count 2 2006.201.08:08:28.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:28.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:08:28.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.08:08:28.03#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:28.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:28.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:28.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:28.15#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:08:28.15#ibcon#first serial, iclass 21, count 0 2006.201.08:08:28.15#ibcon#enter sib2, iclass 21, count 0 2006.201.08:08:28.15#ibcon#flushed, iclass 21, count 0 2006.201.08:08:28.15#ibcon#about to write, iclass 21, count 0 2006.201.08:08:28.15#ibcon#wrote, iclass 21, count 0 2006.201.08:08:28.15#ibcon#about to read 3, iclass 21, count 0 2006.201.08:08:28.17#ibcon#read 3, iclass 21, count 0 2006.201.08:08:28.17#ibcon#about to read 4, iclass 21, count 0 2006.201.08:08:28.17#ibcon#read 4, iclass 21, count 0 2006.201.08:08:28.17#ibcon#about to read 5, iclass 21, count 0 2006.201.08:08:28.17#ibcon#read 5, iclass 21, count 0 2006.201.08:08:28.17#ibcon#about to read 6, iclass 21, count 0 2006.201.08:08:28.17#ibcon#read 6, iclass 21, count 0 2006.201.08:08:28.17#ibcon#end of sib2, iclass 21, count 0 2006.201.08:08:28.17#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:08:28.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:08:28.17#ibcon#[27=USB\r\n] 2006.201.08:08:28.17#ibcon#*before write, iclass 21, count 0 2006.201.08:08:28.17#ibcon#enter sib2, iclass 21, count 0 2006.201.08:08:28.17#ibcon#flushed, iclass 21, count 0 2006.201.08:08:28.17#ibcon#about to write, iclass 21, count 0 2006.201.08:08:28.17#ibcon#wrote, iclass 21, count 0 2006.201.08:08:28.17#ibcon#about to read 3, iclass 21, count 0 2006.201.08:08:28.20#ibcon#read 3, iclass 21, count 0 2006.201.08:08:28.20#ibcon#about to read 4, iclass 21, count 0 2006.201.08:08:28.20#ibcon#read 4, iclass 21, count 0 2006.201.08:08:28.20#ibcon#about to read 5, iclass 21, count 0 2006.201.08:08:28.20#ibcon#read 5, iclass 21, count 0 2006.201.08:08:28.20#ibcon#about to read 6, iclass 21, count 0 2006.201.08:08:28.20#ibcon#read 6, iclass 21, count 0 2006.201.08:08:28.20#ibcon#end of sib2, iclass 21, count 0 2006.201.08:08:28.20#ibcon#*after write, iclass 21, count 0 2006.201.08:08:28.20#ibcon#*before return 0, iclass 21, count 0 2006.201.08:08:28.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:28.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:08:28.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:08:28.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:08:28.20$vck44/vblo=8,744.99 2006.201.08:08:28.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.08:08:28.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.08:08:28.20#ibcon#ireg 17 cls_cnt 0 2006.201.08:08:28.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:28.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:28.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:28.20#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:08:28.20#ibcon#first serial, iclass 23, count 0 2006.201.08:08:28.20#ibcon#enter sib2, iclass 23, count 0 2006.201.08:08:28.20#ibcon#flushed, iclass 23, count 0 2006.201.08:08:28.20#ibcon#about to write, iclass 23, count 0 2006.201.08:08:28.20#ibcon#wrote, iclass 23, count 0 2006.201.08:08:28.20#ibcon#about to read 3, iclass 23, count 0 2006.201.08:08:28.22#ibcon#read 3, iclass 23, count 0 2006.201.08:08:28.22#ibcon#about to read 4, iclass 23, count 0 2006.201.08:08:28.22#ibcon#read 4, iclass 23, count 0 2006.201.08:08:28.22#ibcon#about to read 5, iclass 23, count 0 2006.201.08:08:28.22#ibcon#read 5, iclass 23, count 0 2006.201.08:08:28.22#ibcon#about to read 6, iclass 23, count 0 2006.201.08:08:28.22#ibcon#read 6, iclass 23, count 0 2006.201.08:08:28.22#ibcon#end of sib2, iclass 23, count 0 2006.201.08:08:28.22#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:08:28.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:08:28.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:08:28.22#ibcon#*before write, iclass 23, count 0 2006.201.08:08:28.22#ibcon#enter sib2, iclass 23, count 0 2006.201.08:08:28.22#ibcon#flushed, iclass 23, count 0 2006.201.08:08:28.22#ibcon#about to write, iclass 23, count 0 2006.201.08:08:28.22#ibcon#wrote, iclass 23, count 0 2006.201.08:08:28.22#ibcon#about to read 3, iclass 23, count 0 2006.201.08:08:28.26#ibcon#read 3, iclass 23, count 0 2006.201.08:08:28.26#ibcon#about to read 4, iclass 23, count 0 2006.201.08:08:28.26#ibcon#read 4, iclass 23, count 0 2006.201.08:08:28.26#ibcon#about to read 5, iclass 23, count 0 2006.201.08:08:28.26#ibcon#read 5, iclass 23, count 0 2006.201.08:08:28.26#ibcon#about to read 6, iclass 23, count 0 2006.201.08:08:28.26#ibcon#read 6, iclass 23, count 0 2006.201.08:08:28.26#ibcon#end of sib2, iclass 23, count 0 2006.201.08:08:28.26#ibcon#*after write, iclass 23, count 0 2006.201.08:08:28.26#ibcon#*before return 0, iclass 23, count 0 2006.201.08:08:28.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:28.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:08:28.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:08:28.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:08:28.26$vck44/vb=8,4 2006.201.08:08:28.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.08:08:28.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.08:08:28.26#ibcon#ireg 11 cls_cnt 2 2006.201.08:08:28.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:28.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:28.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:28.32#ibcon#enter wrdev, iclass 25, count 2 2006.201.08:08:28.32#ibcon#first serial, iclass 25, count 2 2006.201.08:08:28.32#ibcon#enter sib2, iclass 25, count 2 2006.201.08:08:28.32#ibcon#flushed, iclass 25, count 2 2006.201.08:08:28.32#ibcon#about to write, iclass 25, count 2 2006.201.08:08:28.32#ibcon#wrote, iclass 25, count 2 2006.201.08:08:28.32#ibcon#about to read 3, iclass 25, count 2 2006.201.08:08:28.34#ibcon#read 3, iclass 25, count 2 2006.201.08:08:28.34#ibcon#about to read 4, iclass 25, count 2 2006.201.08:08:28.34#ibcon#read 4, iclass 25, count 2 2006.201.08:08:28.34#ibcon#about to read 5, iclass 25, count 2 2006.201.08:08:28.34#ibcon#read 5, iclass 25, count 2 2006.201.08:08:28.34#ibcon#about to read 6, iclass 25, count 2 2006.201.08:08:28.34#ibcon#read 6, iclass 25, count 2 2006.201.08:08:28.34#ibcon#end of sib2, iclass 25, count 2 2006.201.08:08:28.34#ibcon#*mode == 0, iclass 25, count 2 2006.201.08:08:28.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.08:08:28.34#ibcon#[27=AT08-04\r\n] 2006.201.08:08:28.34#ibcon#*before write, iclass 25, count 2 2006.201.08:08:28.34#ibcon#enter sib2, iclass 25, count 2 2006.201.08:08:28.34#ibcon#flushed, iclass 25, count 2 2006.201.08:08:28.34#ibcon#about to write, iclass 25, count 2 2006.201.08:08:28.34#ibcon#wrote, iclass 25, count 2 2006.201.08:08:28.34#ibcon#about to read 3, iclass 25, count 2 2006.201.08:08:28.37#ibcon#read 3, iclass 25, count 2 2006.201.08:08:28.37#ibcon#about to read 4, iclass 25, count 2 2006.201.08:08:28.37#ibcon#read 4, iclass 25, count 2 2006.201.08:08:28.37#ibcon#about to read 5, iclass 25, count 2 2006.201.08:08:28.37#ibcon#read 5, iclass 25, count 2 2006.201.08:08:28.37#ibcon#about to read 6, iclass 25, count 2 2006.201.08:08:28.37#ibcon#read 6, iclass 25, count 2 2006.201.08:08:28.37#ibcon#end of sib2, iclass 25, count 2 2006.201.08:08:28.37#ibcon#*after write, iclass 25, count 2 2006.201.08:08:28.37#ibcon#*before return 0, iclass 25, count 2 2006.201.08:08:28.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:28.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:08:28.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.08:08:28.37#ibcon#ireg 7 cls_cnt 0 2006.201.08:08:28.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:28.45#abcon#<5=/04 2.3 4.0 23.25 861003.1\r\n> 2006.201.08:08:28.47#abcon#{5=INTERFACE CLEAR} 2006.201.08:08:28.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:28.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:28.49#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:08:28.49#ibcon#first serial, iclass 25, count 0 2006.201.08:08:28.49#ibcon#enter sib2, iclass 25, count 0 2006.201.08:08:28.49#ibcon#flushed, iclass 25, count 0 2006.201.08:08:28.49#ibcon#about to write, iclass 25, count 0 2006.201.08:08:28.49#ibcon#wrote, iclass 25, count 0 2006.201.08:08:28.49#ibcon#about to read 3, iclass 25, count 0 2006.201.08:08:28.51#ibcon#read 3, iclass 25, count 0 2006.201.08:08:28.51#ibcon#about to read 4, iclass 25, count 0 2006.201.08:08:28.51#ibcon#read 4, iclass 25, count 0 2006.201.08:08:28.51#ibcon#about to read 5, iclass 25, count 0 2006.201.08:08:28.51#ibcon#read 5, iclass 25, count 0 2006.201.08:08:28.51#ibcon#about to read 6, iclass 25, count 0 2006.201.08:08:28.51#ibcon#read 6, iclass 25, count 0 2006.201.08:08:28.51#ibcon#end of sib2, iclass 25, count 0 2006.201.08:08:28.51#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:08:28.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:08:28.51#ibcon#[27=USB\r\n] 2006.201.08:08:28.51#ibcon#*before write, iclass 25, count 0 2006.201.08:08:28.51#ibcon#enter sib2, iclass 25, count 0 2006.201.08:08:28.51#ibcon#flushed, iclass 25, count 0 2006.201.08:08:28.51#ibcon#about to write, iclass 25, count 0 2006.201.08:08:28.51#ibcon#wrote, iclass 25, count 0 2006.201.08:08:28.51#ibcon#about to read 3, iclass 25, count 0 2006.201.08:08:28.53#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:08:28.54#ibcon#read 3, iclass 25, count 0 2006.201.08:08:28.54#ibcon#about to read 4, iclass 25, count 0 2006.201.08:08:28.54#ibcon#read 4, iclass 25, count 0 2006.201.08:08:28.54#ibcon#about to read 5, iclass 25, count 0 2006.201.08:08:28.54#ibcon#read 5, iclass 25, count 0 2006.201.08:08:28.54#ibcon#about to read 6, iclass 25, count 0 2006.201.08:08:28.54#ibcon#read 6, iclass 25, count 0 2006.201.08:08:28.54#ibcon#end of sib2, iclass 25, count 0 2006.201.08:08:28.54#ibcon#*after write, iclass 25, count 0 2006.201.08:08:28.54#ibcon#*before return 0, iclass 25, count 0 2006.201.08:08:28.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:28.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:08:28.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:08:28.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:08:28.54$vck44/vabw=wide 2006.201.08:08:28.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.08:08:28.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.08:08:28.54#ibcon#ireg 8 cls_cnt 0 2006.201.08:08:28.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:28.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:28.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:28.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:08:28.54#ibcon#first serial, iclass 31, count 0 2006.201.08:08:28.54#ibcon#enter sib2, iclass 31, count 0 2006.201.08:08:28.54#ibcon#flushed, iclass 31, count 0 2006.201.08:08:28.54#ibcon#about to write, iclass 31, count 0 2006.201.08:08:28.54#ibcon#wrote, iclass 31, count 0 2006.201.08:08:28.54#ibcon#about to read 3, iclass 31, count 0 2006.201.08:08:28.56#ibcon#read 3, iclass 31, count 0 2006.201.08:08:28.56#ibcon#about to read 4, iclass 31, count 0 2006.201.08:08:28.56#ibcon#read 4, iclass 31, count 0 2006.201.08:08:28.56#ibcon#about to read 5, iclass 31, count 0 2006.201.08:08:28.56#ibcon#read 5, iclass 31, count 0 2006.201.08:08:28.56#ibcon#about to read 6, iclass 31, count 0 2006.201.08:08:28.56#ibcon#read 6, iclass 31, count 0 2006.201.08:08:28.56#ibcon#end of sib2, iclass 31, count 0 2006.201.08:08:28.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:08:28.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:08:28.56#ibcon#[25=BW32\r\n] 2006.201.08:08:28.56#ibcon#*before write, iclass 31, count 0 2006.201.08:08:28.56#ibcon#enter sib2, iclass 31, count 0 2006.201.08:08:28.56#ibcon#flushed, iclass 31, count 0 2006.201.08:08:28.56#ibcon#about to write, iclass 31, count 0 2006.201.08:08:28.56#ibcon#wrote, iclass 31, count 0 2006.201.08:08:28.56#ibcon#about to read 3, iclass 31, count 0 2006.201.08:08:28.59#ibcon#read 3, iclass 31, count 0 2006.201.08:08:28.59#ibcon#about to read 4, iclass 31, count 0 2006.201.08:08:28.59#ibcon#read 4, iclass 31, count 0 2006.201.08:08:28.59#ibcon#about to read 5, iclass 31, count 0 2006.201.08:08:28.59#ibcon#read 5, iclass 31, count 0 2006.201.08:08:28.59#ibcon#about to read 6, iclass 31, count 0 2006.201.08:08:28.59#ibcon#read 6, iclass 31, count 0 2006.201.08:08:28.59#ibcon#end of sib2, iclass 31, count 0 2006.201.08:08:28.59#ibcon#*after write, iclass 31, count 0 2006.201.08:08:28.59#ibcon#*before return 0, iclass 31, count 0 2006.201.08:08:28.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:28.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:08:28.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:08:28.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:08:28.59$vck44/vbbw=wide 2006.201.08:08:28.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.08:08:28.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.08:08:28.59#ibcon#ireg 8 cls_cnt 0 2006.201.08:08:28.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:08:28.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:08:28.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:08:28.66#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:08:28.66#ibcon#first serial, iclass 33, count 0 2006.201.08:08:28.66#ibcon#enter sib2, iclass 33, count 0 2006.201.08:08:28.66#ibcon#flushed, iclass 33, count 0 2006.201.08:08:28.66#ibcon#about to write, iclass 33, count 0 2006.201.08:08:28.66#ibcon#wrote, iclass 33, count 0 2006.201.08:08:28.66#ibcon#about to read 3, iclass 33, count 0 2006.201.08:08:28.68#ibcon#read 3, iclass 33, count 0 2006.201.08:08:28.68#ibcon#about to read 4, iclass 33, count 0 2006.201.08:08:28.68#ibcon#read 4, iclass 33, count 0 2006.201.08:08:28.68#ibcon#about to read 5, iclass 33, count 0 2006.201.08:08:28.68#ibcon#read 5, iclass 33, count 0 2006.201.08:08:28.68#ibcon#about to read 6, iclass 33, count 0 2006.201.08:08:28.68#ibcon#read 6, iclass 33, count 0 2006.201.08:08:28.68#ibcon#end of sib2, iclass 33, count 0 2006.201.08:08:28.68#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:08:28.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:08:28.68#ibcon#[27=BW32\r\n] 2006.201.08:08:28.68#ibcon#*before write, iclass 33, count 0 2006.201.08:08:28.68#ibcon#enter sib2, iclass 33, count 0 2006.201.08:08:28.68#ibcon#flushed, iclass 33, count 0 2006.201.08:08:28.68#ibcon#about to write, iclass 33, count 0 2006.201.08:08:28.68#ibcon#wrote, iclass 33, count 0 2006.201.08:08:28.68#ibcon#about to read 3, iclass 33, count 0 2006.201.08:08:28.71#ibcon#read 3, iclass 33, count 0 2006.201.08:08:28.71#ibcon#about to read 4, iclass 33, count 0 2006.201.08:08:28.71#ibcon#read 4, iclass 33, count 0 2006.201.08:08:28.71#ibcon#about to read 5, iclass 33, count 0 2006.201.08:08:28.71#ibcon#read 5, iclass 33, count 0 2006.201.08:08:28.71#ibcon#about to read 6, iclass 33, count 0 2006.201.08:08:28.71#ibcon#read 6, iclass 33, count 0 2006.201.08:08:28.71#ibcon#end of sib2, iclass 33, count 0 2006.201.08:08:28.71#ibcon#*after write, iclass 33, count 0 2006.201.08:08:28.71#ibcon#*before return 0, iclass 33, count 0 2006.201.08:08:28.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:08:28.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:08:28.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:08:28.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:08:28.71$setupk4/ifdk4 2006.201.08:08:28.71$ifdk4/lo= 2006.201.08:08:28.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:08:28.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:08:28.71$ifdk4/patch= 2006.201.08:08:28.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:08:28.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:08:28.71$setupk4/!*+20s 2006.201.08:08:38.62#abcon#<5=/04 2.3 4.0 23.25 861003.1\r\n> 2006.201.08:08:38.64#abcon#{5=INTERFACE CLEAR} 2006.201.08:08:38.70#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:08:43.17$setupk4/"tpicd 2006.201.08:08:43.17$setupk4/echo=off 2006.201.08:08:43.17$setupk4/xlog=off 2006.201.08:08:43.17:!2006.201.08:09:45 2006.201.08:08:50.13#trakl#Source acquired 2006.201.08:08:50.13#flagr#flagr/antenna,acquired 2006.201.08:09:45.00:preob 2006.201.08:09:45.13/onsource/TRACKING 2006.201.08:09:45.13:!2006.201.08:09:55 2006.201.08:09:55.00:"tape 2006.201.08:09:55.00:"st=record 2006.201.08:09:55.00:data_valid=on 2006.201.08:09:55.00:midob 2006.201.08:09:56.13/onsource/TRACKING 2006.201.08:09:56.13/wx/23.23,1003.1,86 2006.201.08:09:56.19/cable/+6.4671E-03 2006.201.08:09:57.28/va/01,08,usb,yes,28,30 2006.201.08:09:57.28/va/02,07,usb,yes,30,31 2006.201.08:09:57.28/va/03,08,usb,yes,27,28 2006.201.08:09:57.28/va/04,07,usb,yes,31,33 2006.201.08:09:57.28/va/05,04,usb,yes,27,28 2006.201.08:09:57.28/va/06,05,usb,yes,28,27 2006.201.08:09:57.28/va/07,05,usb,yes,27,28 2006.201.08:09:57.28/va/08,04,usb,yes,27,32 2006.201.08:09:57.51/valo/01,524.99,yes,locked 2006.201.08:09:57.51/valo/02,534.99,yes,locked 2006.201.08:09:57.51/valo/03,564.99,yes,locked 2006.201.08:09:57.51/valo/04,624.99,yes,locked 2006.201.08:09:57.51/valo/05,734.99,yes,locked 2006.201.08:09:57.51/valo/06,814.99,yes,locked 2006.201.08:09:57.51/valo/07,864.99,yes,locked 2006.201.08:09:57.51/valo/08,884.99,yes,locked 2006.201.08:09:58.60/vb/01,04,usb,yes,29,26 2006.201.08:09:58.60/vb/02,05,usb,yes,27,27 2006.201.08:09:58.60/vb/03,04,usb,yes,28,31 2006.201.08:09:58.60/vb/04,05,usb,yes,28,27 2006.201.08:09:58.60/vb/05,04,usb,yes,25,27 2006.201.08:09:58.60/vb/06,04,usb,yes,29,25 2006.201.08:09:58.60/vb/07,04,usb,yes,29,28 2006.201.08:09:58.60/vb/08,04,usb,yes,26,30 2006.201.08:09:58.83/vblo/01,629.99,yes,locked 2006.201.08:09:58.83/vblo/02,634.99,yes,locked 2006.201.08:09:58.83/vblo/03,649.99,yes,locked 2006.201.08:09:58.83/vblo/04,679.99,yes,locked 2006.201.08:09:58.83/vblo/05,709.99,yes,locked 2006.201.08:09:58.83/vblo/06,719.99,yes,locked 2006.201.08:09:58.83/vblo/07,734.99,yes,locked 2006.201.08:09:58.83/vblo/08,744.99,yes,locked 2006.201.08:09:58.98/vabw/8 2006.201.08:09:59.13/vbbw/8 2006.201.08:09:59.35/xfe/off,on,15.0 2006.201.08:09:59.73/ifatt/23,28,28,28 2006.201.08:10:00.05/fmout-gps/S +4.53E-07 2006.201.08:10:00.12:!2006.201.08:11:35 2006.201.08:11:35.00:data_valid=off 2006.201.08:11:35.00:"et 2006.201.08:11:35.00:!+3s 2006.201.08:11:38.02:"tape 2006.201.08:11:38.02:postob 2006.201.08:11:38.19/cable/+6.4671E-03 2006.201.08:11:38.19/wx/23.22,1003.2,86 2006.201.08:11:38.27/fmout-gps/S +4.53E-07 2006.201.08:11:38.27:scan_name=201-0813,jd0607,40 2006.201.08:11:38.27:source=1424-418,142756.30,-420619.4,2000.0,ccw 2006.201.08:11:40.14#flagr#flagr/antenna,new-source 2006.201.08:11:40.14:checkk5 2006.201.08:11:40.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:11:40.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:11:41.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:11:41.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:11:42.00/chk_obsdata//k5ts1/T2010809??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.08:11:42.36/chk_obsdata//k5ts2/T2010809??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.08:11:42.73/chk_obsdata//k5ts3/T2010809??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.08:11:43.10/chk_obsdata//k5ts4/T2010809??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.08:11:43.79/k5log//k5ts1_log_newline 2006.201.08:11:44.47/k5log//k5ts2_log_newline 2006.201.08:11:45.16/k5log//k5ts3_log_newline 2006.201.08:11:45.85/k5log//k5ts4_log_newline 2006.201.08:11:45.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:11:45.87:setupk4=1 2006.201.08:11:45.87$setupk4/echo=on 2006.201.08:11:45.87$setupk4/pcalon 2006.201.08:11:45.87$pcalon/"no phase cal control is implemented here 2006.201.08:11:45.87$setupk4/"tpicd=stop 2006.201.08:11:45.87$setupk4/"rec=synch_on 2006.201.08:11:45.87$setupk4/"rec_mode=128 2006.201.08:11:45.87$setupk4/!* 2006.201.08:11:45.87$setupk4/recpk4 2006.201.08:11:45.87$recpk4/recpatch= 2006.201.08:11:45.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:11:45.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:11:45.88$setupk4/vck44 2006.201.08:11:45.88$vck44/valo=1,524.99 2006.201.08:11:45.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.08:11:45.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.08:11:45.88#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:45.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:45.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:45.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:45.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.08:11:45.88#ibcon#first serial, iclass 4, count 0 2006.201.08:11:45.88#ibcon#enter sib2, iclass 4, count 0 2006.201.08:11:45.88#ibcon#flushed, iclass 4, count 0 2006.201.08:11:45.88#ibcon#about to write, iclass 4, count 0 2006.201.08:11:45.88#ibcon#wrote, iclass 4, count 0 2006.201.08:11:45.88#ibcon#about to read 3, iclass 4, count 0 2006.201.08:11:45.91#ibcon#read 3, iclass 4, count 0 2006.201.08:11:45.91#ibcon#about to read 4, iclass 4, count 0 2006.201.08:11:45.91#ibcon#read 4, iclass 4, count 0 2006.201.08:11:45.91#ibcon#about to read 5, iclass 4, count 0 2006.201.08:11:45.91#ibcon#read 5, iclass 4, count 0 2006.201.08:11:45.91#ibcon#about to read 6, iclass 4, count 0 2006.201.08:11:45.91#ibcon#read 6, iclass 4, count 0 2006.201.08:11:45.91#ibcon#end of sib2, iclass 4, count 0 2006.201.08:11:45.91#ibcon#*mode == 0, iclass 4, count 0 2006.201.08:11:45.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.08:11:45.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:11:45.91#ibcon#*before write, iclass 4, count 0 2006.201.08:11:45.91#ibcon#enter sib2, iclass 4, count 0 2006.201.08:11:45.91#ibcon#flushed, iclass 4, count 0 2006.201.08:11:45.91#ibcon#about to write, iclass 4, count 0 2006.201.08:11:45.91#ibcon#wrote, iclass 4, count 0 2006.201.08:11:45.91#ibcon#about to read 3, iclass 4, count 0 2006.201.08:11:45.96#ibcon#read 3, iclass 4, count 0 2006.201.08:11:45.96#ibcon#about to read 4, iclass 4, count 0 2006.201.08:11:45.96#ibcon#read 4, iclass 4, count 0 2006.201.08:11:45.96#ibcon#about to read 5, iclass 4, count 0 2006.201.08:11:45.96#ibcon#read 5, iclass 4, count 0 2006.201.08:11:45.96#ibcon#about to read 6, iclass 4, count 0 2006.201.08:11:45.96#ibcon#read 6, iclass 4, count 0 2006.201.08:11:45.96#ibcon#end of sib2, iclass 4, count 0 2006.201.08:11:45.96#ibcon#*after write, iclass 4, count 0 2006.201.08:11:45.96#ibcon#*before return 0, iclass 4, count 0 2006.201.08:11:45.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:45.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:45.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.08:11:45.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.08:11:45.96$vck44/va=1,8 2006.201.08:11:45.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.08:11:45.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.08:11:45.96#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:45.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:45.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:45.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:45.96#ibcon#enter wrdev, iclass 6, count 2 2006.201.08:11:45.96#ibcon#first serial, iclass 6, count 2 2006.201.08:11:45.96#ibcon#enter sib2, iclass 6, count 2 2006.201.08:11:45.96#ibcon#flushed, iclass 6, count 2 2006.201.08:11:45.96#ibcon#about to write, iclass 6, count 2 2006.201.08:11:45.96#ibcon#wrote, iclass 6, count 2 2006.201.08:11:45.96#ibcon#about to read 3, iclass 6, count 2 2006.201.08:11:45.98#ibcon#read 3, iclass 6, count 2 2006.201.08:11:45.98#ibcon#about to read 4, iclass 6, count 2 2006.201.08:11:45.98#ibcon#read 4, iclass 6, count 2 2006.201.08:11:45.98#ibcon#about to read 5, iclass 6, count 2 2006.201.08:11:45.98#ibcon#read 5, iclass 6, count 2 2006.201.08:11:45.98#ibcon#about to read 6, iclass 6, count 2 2006.201.08:11:45.98#ibcon#read 6, iclass 6, count 2 2006.201.08:11:45.98#ibcon#end of sib2, iclass 6, count 2 2006.201.08:11:45.98#ibcon#*mode == 0, iclass 6, count 2 2006.201.08:11:45.98#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.08:11:45.98#ibcon#[25=AT01-08\r\n] 2006.201.08:11:45.98#ibcon#*before write, iclass 6, count 2 2006.201.08:11:45.98#ibcon#enter sib2, iclass 6, count 2 2006.201.08:11:45.98#ibcon#flushed, iclass 6, count 2 2006.201.08:11:45.98#ibcon#about to write, iclass 6, count 2 2006.201.08:11:45.98#ibcon#wrote, iclass 6, count 2 2006.201.08:11:45.98#ibcon#about to read 3, iclass 6, count 2 2006.201.08:11:46.01#ibcon#read 3, iclass 6, count 2 2006.201.08:11:46.01#ibcon#about to read 4, iclass 6, count 2 2006.201.08:11:46.01#ibcon#read 4, iclass 6, count 2 2006.201.08:11:46.01#ibcon#about to read 5, iclass 6, count 2 2006.201.08:11:46.01#ibcon#read 5, iclass 6, count 2 2006.201.08:11:46.01#ibcon#about to read 6, iclass 6, count 2 2006.201.08:11:46.01#ibcon#read 6, iclass 6, count 2 2006.201.08:11:46.01#ibcon#end of sib2, iclass 6, count 2 2006.201.08:11:46.01#ibcon#*after write, iclass 6, count 2 2006.201.08:11:46.01#ibcon#*before return 0, iclass 6, count 2 2006.201.08:11:46.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:46.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:46.01#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.08:11:46.01#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:46.01#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:46.13#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:46.13#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:46.13#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:11:46.13#ibcon#first serial, iclass 6, count 0 2006.201.08:11:46.13#ibcon#enter sib2, iclass 6, count 0 2006.201.08:11:46.13#ibcon#flushed, iclass 6, count 0 2006.201.08:11:46.13#ibcon#about to write, iclass 6, count 0 2006.201.08:11:46.13#ibcon#wrote, iclass 6, count 0 2006.201.08:11:46.13#ibcon#about to read 3, iclass 6, count 0 2006.201.08:11:46.15#ibcon#read 3, iclass 6, count 0 2006.201.08:11:46.15#ibcon#about to read 4, iclass 6, count 0 2006.201.08:11:46.15#ibcon#read 4, iclass 6, count 0 2006.201.08:11:46.15#ibcon#about to read 5, iclass 6, count 0 2006.201.08:11:46.15#ibcon#read 5, iclass 6, count 0 2006.201.08:11:46.15#ibcon#about to read 6, iclass 6, count 0 2006.201.08:11:46.15#ibcon#read 6, iclass 6, count 0 2006.201.08:11:46.15#ibcon#end of sib2, iclass 6, count 0 2006.201.08:11:46.15#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:11:46.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:11:46.15#ibcon#[25=USB\r\n] 2006.201.08:11:46.15#ibcon#*before write, iclass 6, count 0 2006.201.08:11:46.15#ibcon#enter sib2, iclass 6, count 0 2006.201.08:11:46.15#ibcon#flushed, iclass 6, count 0 2006.201.08:11:46.15#ibcon#about to write, iclass 6, count 0 2006.201.08:11:46.15#ibcon#wrote, iclass 6, count 0 2006.201.08:11:46.15#ibcon#about to read 3, iclass 6, count 0 2006.201.08:11:46.18#ibcon#read 3, iclass 6, count 0 2006.201.08:11:46.18#ibcon#about to read 4, iclass 6, count 0 2006.201.08:11:46.18#ibcon#read 4, iclass 6, count 0 2006.201.08:11:46.18#ibcon#about to read 5, iclass 6, count 0 2006.201.08:11:46.18#ibcon#read 5, iclass 6, count 0 2006.201.08:11:46.18#ibcon#about to read 6, iclass 6, count 0 2006.201.08:11:46.18#ibcon#read 6, iclass 6, count 0 2006.201.08:11:46.18#ibcon#end of sib2, iclass 6, count 0 2006.201.08:11:46.18#ibcon#*after write, iclass 6, count 0 2006.201.08:11:46.18#ibcon#*before return 0, iclass 6, count 0 2006.201.08:11:46.18#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:46.18#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:46.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:11:46.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:11:46.18$vck44/valo=2,534.99 2006.201.08:11:46.18#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.08:11:46.18#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.08:11:46.18#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:46.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:46.18#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:46.18#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:46.18#ibcon#enter wrdev, iclass 10, count 0 2006.201.08:11:46.18#ibcon#first serial, iclass 10, count 0 2006.201.08:11:46.18#ibcon#enter sib2, iclass 10, count 0 2006.201.08:11:46.18#ibcon#flushed, iclass 10, count 0 2006.201.08:11:46.18#ibcon#about to write, iclass 10, count 0 2006.201.08:11:46.18#ibcon#wrote, iclass 10, count 0 2006.201.08:11:46.18#ibcon#about to read 3, iclass 10, count 0 2006.201.08:11:46.20#ibcon#read 3, iclass 10, count 0 2006.201.08:11:46.20#ibcon#about to read 4, iclass 10, count 0 2006.201.08:11:46.20#ibcon#read 4, iclass 10, count 0 2006.201.08:11:46.20#ibcon#about to read 5, iclass 10, count 0 2006.201.08:11:46.20#ibcon#read 5, iclass 10, count 0 2006.201.08:11:46.20#ibcon#about to read 6, iclass 10, count 0 2006.201.08:11:46.20#ibcon#read 6, iclass 10, count 0 2006.201.08:11:46.20#ibcon#end of sib2, iclass 10, count 0 2006.201.08:11:46.20#ibcon#*mode == 0, iclass 10, count 0 2006.201.08:11:46.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.08:11:46.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:11:46.20#ibcon#*before write, iclass 10, count 0 2006.201.08:11:46.20#ibcon#enter sib2, iclass 10, count 0 2006.201.08:11:46.20#ibcon#flushed, iclass 10, count 0 2006.201.08:11:46.20#ibcon#about to write, iclass 10, count 0 2006.201.08:11:46.20#ibcon#wrote, iclass 10, count 0 2006.201.08:11:46.20#ibcon#about to read 3, iclass 10, count 0 2006.201.08:11:46.24#ibcon#read 3, iclass 10, count 0 2006.201.08:11:46.24#ibcon#about to read 4, iclass 10, count 0 2006.201.08:11:46.24#ibcon#read 4, iclass 10, count 0 2006.201.08:11:46.24#ibcon#about to read 5, iclass 10, count 0 2006.201.08:11:46.24#ibcon#read 5, iclass 10, count 0 2006.201.08:11:46.24#ibcon#about to read 6, iclass 10, count 0 2006.201.08:11:46.24#ibcon#read 6, iclass 10, count 0 2006.201.08:11:46.24#ibcon#end of sib2, iclass 10, count 0 2006.201.08:11:46.24#ibcon#*after write, iclass 10, count 0 2006.201.08:11:46.24#ibcon#*before return 0, iclass 10, count 0 2006.201.08:11:46.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:46.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:46.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.08:11:46.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.08:11:46.24$vck44/va=2,7 2006.201.08:11:46.24#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.08:11:46.24#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.08:11:46.24#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:46.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:46.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:46.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:46.30#ibcon#enter wrdev, iclass 12, count 2 2006.201.08:11:46.30#ibcon#first serial, iclass 12, count 2 2006.201.08:11:46.30#ibcon#enter sib2, iclass 12, count 2 2006.201.08:11:46.30#ibcon#flushed, iclass 12, count 2 2006.201.08:11:46.30#ibcon#about to write, iclass 12, count 2 2006.201.08:11:46.30#ibcon#wrote, iclass 12, count 2 2006.201.08:11:46.30#ibcon#about to read 3, iclass 12, count 2 2006.201.08:11:46.32#ibcon#read 3, iclass 12, count 2 2006.201.08:11:46.32#ibcon#about to read 4, iclass 12, count 2 2006.201.08:11:46.32#ibcon#read 4, iclass 12, count 2 2006.201.08:11:46.32#ibcon#about to read 5, iclass 12, count 2 2006.201.08:11:46.32#ibcon#read 5, iclass 12, count 2 2006.201.08:11:46.32#ibcon#about to read 6, iclass 12, count 2 2006.201.08:11:46.32#ibcon#read 6, iclass 12, count 2 2006.201.08:11:46.32#ibcon#end of sib2, iclass 12, count 2 2006.201.08:11:46.32#ibcon#*mode == 0, iclass 12, count 2 2006.201.08:11:46.32#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.08:11:46.32#ibcon#[25=AT02-07\r\n] 2006.201.08:11:46.32#ibcon#*before write, iclass 12, count 2 2006.201.08:11:46.32#ibcon#enter sib2, iclass 12, count 2 2006.201.08:11:46.32#ibcon#flushed, iclass 12, count 2 2006.201.08:11:46.32#ibcon#about to write, iclass 12, count 2 2006.201.08:11:46.32#ibcon#wrote, iclass 12, count 2 2006.201.08:11:46.32#ibcon#about to read 3, iclass 12, count 2 2006.201.08:11:46.35#ibcon#read 3, iclass 12, count 2 2006.201.08:11:46.35#ibcon#about to read 4, iclass 12, count 2 2006.201.08:11:46.35#ibcon#read 4, iclass 12, count 2 2006.201.08:11:46.35#ibcon#about to read 5, iclass 12, count 2 2006.201.08:11:46.35#ibcon#read 5, iclass 12, count 2 2006.201.08:11:46.35#ibcon#about to read 6, iclass 12, count 2 2006.201.08:11:46.35#ibcon#read 6, iclass 12, count 2 2006.201.08:11:46.35#ibcon#end of sib2, iclass 12, count 2 2006.201.08:11:46.35#ibcon#*after write, iclass 12, count 2 2006.201.08:11:46.35#ibcon#*before return 0, iclass 12, count 2 2006.201.08:11:46.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:46.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:46.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.08:11:46.35#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:46.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:46.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:46.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:46.47#ibcon#enter wrdev, iclass 12, count 0 2006.201.08:11:46.47#ibcon#first serial, iclass 12, count 0 2006.201.08:11:46.47#ibcon#enter sib2, iclass 12, count 0 2006.201.08:11:46.47#ibcon#flushed, iclass 12, count 0 2006.201.08:11:46.47#ibcon#about to write, iclass 12, count 0 2006.201.08:11:46.47#ibcon#wrote, iclass 12, count 0 2006.201.08:11:46.47#ibcon#about to read 3, iclass 12, count 0 2006.201.08:11:46.49#ibcon#read 3, iclass 12, count 0 2006.201.08:11:46.49#ibcon#about to read 4, iclass 12, count 0 2006.201.08:11:46.49#ibcon#read 4, iclass 12, count 0 2006.201.08:11:46.49#ibcon#about to read 5, iclass 12, count 0 2006.201.08:11:46.49#ibcon#read 5, iclass 12, count 0 2006.201.08:11:46.49#ibcon#about to read 6, iclass 12, count 0 2006.201.08:11:46.49#ibcon#read 6, iclass 12, count 0 2006.201.08:11:46.49#ibcon#end of sib2, iclass 12, count 0 2006.201.08:11:46.49#ibcon#*mode == 0, iclass 12, count 0 2006.201.08:11:46.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.08:11:46.49#ibcon#[25=USB\r\n] 2006.201.08:11:46.49#ibcon#*before write, iclass 12, count 0 2006.201.08:11:46.49#ibcon#enter sib2, iclass 12, count 0 2006.201.08:11:46.49#ibcon#flushed, iclass 12, count 0 2006.201.08:11:46.49#ibcon#about to write, iclass 12, count 0 2006.201.08:11:46.49#ibcon#wrote, iclass 12, count 0 2006.201.08:11:46.49#ibcon#about to read 3, iclass 12, count 0 2006.201.08:11:46.52#ibcon#read 3, iclass 12, count 0 2006.201.08:11:46.52#ibcon#about to read 4, iclass 12, count 0 2006.201.08:11:46.52#ibcon#read 4, iclass 12, count 0 2006.201.08:11:46.52#ibcon#about to read 5, iclass 12, count 0 2006.201.08:11:46.52#ibcon#read 5, iclass 12, count 0 2006.201.08:11:46.52#ibcon#about to read 6, iclass 12, count 0 2006.201.08:11:46.52#ibcon#read 6, iclass 12, count 0 2006.201.08:11:46.52#ibcon#end of sib2, iclass 12, count 0 2006.201.08:11:46.52#ibcon#*after write, iclass 12, count 0 2006.201.08:11:46.52#ibcon#*before return 0, iclass 12, count 0 2006.201.08:11:46.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:46.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:46.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.08:11:46.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.08:11:46.52$vck44/valo=3,564.99 2006.201.08:11:46.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.08:11:46.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.08:11:46.52#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:46.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:46.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:46.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:46.52#ibcon#enter wrdev, iclass 14, count 0 2006.201.08:11:46.52#ibcon#first serial, iclass 14, count 0 2006.201.08:11:46.52#ibcon#enter sib2, iclass 14, count 0 2006.201.08:11:46.52#ibcon#flushed, iclass 14, count 0 2006.201.08:11:46.52#ibcon#about to write, iclass 14, count 0 2006.201.08:11:46.52#ibcon#wrote, iclass 14, count 0 2006.201.08:11:46.52#ibcon#about to read 3, iclass 14, count 0 2006.201.08:11:46.54#ibcon#read 3, iclass 14, count 0 2006.201.08:11:46.54#ibcon#about to read 4, iclass 14, count 0 2006.201.08:11:46.54#ibcon#read 4, iclass 14, count 0 2006.201.08:11:46.54#ibcon#about to read 5, iclass 14, count 0 2006.201.08:11:46.54#ibcon#read 5, iclass 14, count 0 2006.201.08:11:46.54#ibcon#about to read 6, iclass 14, count 0 2006.201.08:11:46.54#ibcon#read 6, iclass 14, count 0 2006.201.08:11:46.54#ibcon#end of sib2, iclass 14, count 0 2006.201.08:11:46.54#ibcon#*mode == 0, iclass 14, count 0 2006.201.08:11:46.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.08:11:46.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:11:46.54#ibcon#*before write, iclass 14, count 0 2006.201.08:11:46.54#ibcon#enter sib2, iclass 14, count 0 2006.201.08:11:46.54#ibcon#flushed, iclass 14, count 0 2006.201.08:11:46.54#ibcon#about to write, iclass 14, count 0 2006.201.08:11:46.54#ibcon#wrote, iclass 14, count 0 2006.201.08:11:46.54#ibcon#about to read 3, iclass 14, count 0 2006.201.08:11:46.59#ibcon#read 3, iclass 14, count 0 2006.201.08:11:46.59#ibcon#about to read 4, iclass 14, count 0 2006.201.08:11:46.59#ibcon#read 4, iclass 14, count 0 2006.201.08:11:46.59#ibcon#about to read 5, iclass 14, count 0 2006.201.08:11:46.59#ibcon#read 5, iclass 14, count 0 2006.201.08:11:46.59#ibcon#about to read 6, iclass 14, count 0 2006.201.08:11:46.59#ibcon#read 6, iclass 14, count 0 2006.201.08:11:46.59#ibcon#end of sib2, iclass 14, count 0 2006.201.08:11:46.59#ibcon#*after write, iclass 14, count 0 2006.201.08:11:46.59#ibcon#*before return 0, iclass 14, count 0 2006.201.08:11:46.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:46.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:46.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.08:11:46.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.08:11:46.59$vck44/va=3,8 2006.201.08:11:46.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.08:11:46.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.08:11:46.59#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:46.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:46.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:46.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:46.64#ibcon#enter wrdev, iclass 16, count 2 2006.201.08:11:46.64#ibcon#first serial, iclass 16, count 2 2006.201.08:11:46.64#ibcon#enter sib2, iclass 16, count 2 2006.201.08:11:46.64#ibcon#flushed, iclass 16, count 2 2006.201.08:11:46.64#ibcon#about to write, iclass 16, count 2 2006.201.08:11:46.64#ibcon#wrote, iclass 16, count 2 2006.201.08:11:46.64#ibcon#about to read 3, iclass 16, count 2 2006.201.08:11:46.66#ibcon#read 3, iclass 16, count 2 2006.201.08:11:46.66#ibcon#about to read 4, iclass 16, count 2 2006.201.08:11:46.66#ibcon#read 4, iclass 16, count 2 2006.201.08:11:46.66#ibcon#about to read 5, iclass 16, count 2 2006.201.08:11:46.66#ibcon#read 5, iclass 16, count 2 2006.201.08:11:46.66#ibcon#about to read 6, iclass 16, count 2 2006.201.08:11:46.66#ibcon#read 6, iclass 16, count 2 2006.201.08:11:46.66#ibcon#end of sib2, iclass 16, count 2 2006.201.08:11:46.66#ibcon#*mode == 0, iclass 16, count 2 2006.201.08:11:46.66#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.08:11:46.66#ibcon#[25=AT03-08\r\n] 2006.201.08:11:46.66#ibcon#*before write, iclass 16, count 2 2006.201.08:11:46.66#ibcon#enter sib2, iclass 16, count 2 2006.201.08:11:46.66#ibcon#flushed, iclass 16, count 2 2006.201.08:11:46.66#ibcon#about to write, iclass 16, count 2 2006.201.08:11:46.66#ibcon#wrote, iclass 16, count 2 2006.201.08:11:46.66#ibcon#about to read 3, iclass 16, count 2 2006.201.08:11:46.69#ibcon#read 3, iclass 16, count 2 2006.201.08:11:46.69#ibcon#about to read 4, iclass 16, count 2 2006.201.08:11:46.69#ibcon#read 4, iclass 16, count 2 2006.201.08:11:46.69#ibcon#about to read 5, iclass 16, count 2 2006.201.08:11:46.69#ibcon#read 5, iclass 16, count 2 2006.201.08:11:46.69#ibcon#about to read 6, iclass 16, count 2 2006.201.08:11:46.69#ibcon#read 6, iclass 16, count 2 2006.201.08:11:46.69#ibcon#end of sib2, iclass 16, count 2 2006.201.08:11:46.69#ibcon#*after write, iclass 16, count 2 2006.201.08:11:46.69#ibcon#*before return 0, iclass 16, count 2 2006.201.08:11:46.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:46.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:46.69#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.08:11:46.69#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:46.69#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:46.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:46.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:46.81#ibcon#enter wrdev, iclass 16, count 0 2006.201.08:11:46.81#ibcon#first serial, iclass 16, count 0 2006.201.08:11:46.81#ibcon#enter sib2, iclass 16, count 0 2006.201.08:11:46.81#ibcon#flushed, iclass 16, count 0 2006.201.08:11:46.81#ibcon#about to write, iclass 16, count 0 2006.201.08:11:46.81#ibcon#wrote, iclass 16, count 0 2006.201.08:11:46.81#ibcon#about to read 3, iclass 16, count 0 2006.201.08:11:46.83#ibcon#read 3, iclass 16, count 0 2006.201.08:11:46.83#ibcon#about to read 4, iclass 16, count 0 2006.201.08:11:46.83#ibcon#read 4, iclass 16, count 0 2006.201.08:11:46.83#ibcon#about to read 5, iclass 16, count 0 2006.201.08:11:46.83#ibcon#read 5, iclass 16, count 0 2006.201.08:11:46.83#ibcon#about to read 6, iclass 16, count 0 2006.201.08:11:46.83#ibcon#read 6, iclass 16, count 0 2006.201.08:11:46.83#ibcon#end of sib2, iclass 16, count 0 2006.201.08:11:46.83#ibcon#*mode == 0, iclass 16, count 0 2006.201.08:11:46.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.08:11:46.83#ibcon#[25=USB\r\n] 2006.201.08:11:46.83#ibcon#*before write, iclass 16, count 0 2006.201.08:11:46.83#ibcon#enter sib2, iclass 16, count 0 2006.201.08:11:46.83#ibcon#flushed, iclass 16, count 0 2006.201.08:11:46.83#ibcon#about to write, iclass 16, count 0 2006.201.08:11:46.83#ibcon#wrote, iclass 16, count 0 2006.201.08:11:46.83#ibcon#about to read 3, iclass 16, count 0 2006.201.08:11:46.86#ibcon#read 3, iclass 16, count 0 2006.201.08:11:46.86#ibcon#about to read 4, iclass 16, count 0 2006.201.08:11:46.86#ibcon#read 4, iclass 16, count 0 2006.201.08:11:46.86#ibcon#about to read 5, iclass 16, count 0 2006.201.08:11:46.86#ibcon#read 5, iclass 16, count 0 2006.201.08:11:46.86#ibcon#about to read 6, iclass 16, count 0 2006.201.08:11:46.86#ibcon#read 6, iclass 16, count 0 2006.201.08:11:46.86#ibcon#end of sib2, iclass 16, count 0 2006.201.08:11:46.86#ibcon#*after write, iclass 16, count 0 2006.201.08:11:46.86#ibcon#*before return 0, iclass 16, count 0 2006.201.08:11:46.86#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:46.86#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:46.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.08:11:46.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.08:11:46.86$vck44/valo=4,624.99 2006.201.08:11:46.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.08:11:46.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.08:11:46.86#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:46.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:46.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:46.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:46.86#ibcon#enter wrdev, iclass 18, count 0 2006.201.08:11:46.86#ibcon#first serial, iclass 18, count 0 2006.201.08:11:46.86#ibcon#enter sib2, iclass 18, count 0 2006.201.08:11:46.86#ibcon#flushed, iclass 18, count 0 2006.201.08:11:46.86#ibcon#about to write, iclass 18, count 0 2006.201.08:11:46.86#ibcon#wrote, iclass 18, count 0 2006.201.08:11:46.86#ibcon#about to read 3, iclass 18, count 0 2006.201.08:11:46.88#ibcon#read 3, iclass 18, count 0 2006.201.08:11:46.88#ibcon#about to read 4, iclass 18, count 0 2006.201.08:11:46.88#ibcon#read 4, iclass 18, count 0 2006.201.08:11:46.88#ibcon#about to read 5, iclass 18, count 0 2006.201.08:11:46.88#ibcon#read 5, iclass 18, count 0 2006.201.08:11:46.88#ibcon#about to read 6, iclass 18, count 0 2006.201.08:11:46.88#ibcon#read 6, iclass 18, count 0 2006.201.08:11:46.88#ibcon#end of sib2, iclass 18, count 0 2006.201.08:11:46.88#ibcon#*mode == 0, iclass 18, count 0 2006.201.08:11:46.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.08:11:46.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:11:46.88#ibcon#*before write, iclass 18, count 0 2006.201.08:11:46.88#ibcon#enter sib2, iclass 18, count 0 2006.201.08:11:46.88#ibcon#flushed, iclass 18, count 0 2006.201.08:11:46.88#ibcon#about to write, iclass 18, count 0 2006.201.08:11:46.88#ibcon#wrote, iclass 18, count 0 2006.201.08:11:46.88#ibcon#about to read 3, iclass 18, count 0 2006.201.08:11:46.93#ibcon#read 3, iclass 18, count 0 2006.201.08:11:46.93#ibcon#about to read 4, iclass 18, count 0 2006.201.08:11:46.93#ibcon#read 4, iclass 18, count 0 2006.201.08:11:46.93#ibcon#about to read 5, iclass 18, count 0 2006.201.08:11:46.93#ibcon#read 5, iclass 18, count 0 2006.201.08:11:46.93#ibcon#about to read 6, iclass 18, count 0 2006.201.08:11:46.93#ibcon#read 6, iclass 18, count 0 2006.201.08:11:46.93#ibcon#end of sib2, iclass 18, count 0 2006.201.08:11:46.93#ibcon#*after write, iclass 18, count 0 2006.201.08:11:46.93#ibcon#*before return 0, iclass 18, count 0 2006.201.08:11:46.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:46.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:46.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.08:11:46.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.08:11:46.93$vck44/va=4,7 2006.201.08:11:46.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.08:11:46.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.08:11:46.93#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:46.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:46.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:46.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:46.98#ibcon#enter wrdev, iclass 20, count 2 2006.201.08:11:46.98#ibcon#first serial, iclass 20, count 2 2006.201.08:11:46.98#ibcon#enter sib2, iclass 20, count 2 2006.201.08:11:46.98#ibcon#flushed, iclass 20, count 2 2006.201.08:11:46.98#ibcon#about to write, iclass 20, count 2 2006.201.08:11:46.98#ibcon#wrote, iclass 20, count 2 2006.201.08:11:46.98#ibcon#about to read 3, iclass 20, count 2 2006.201.08:11:47.00#ibcon#read 3, iclass 20, count 2 2006.201.08:11:47.00#ibcon#about to read 4, iclass 20, count 2 2006.201.08:11:47.00#ibcon#read 4, iclass 20, count 2 2006.201.08:11:47.00#ibcon#about to read 5, iclass 20, count 2 2006.201.08:11:47.00#ibcon#read 5, iclass 20, count 2 2006.201.08:11:47.00#ibcon#about to read 6, iclass 20, count 2 2006.201.08:11:47.00#ibcon#read 6, iclass 20, count 2 2006.201.08:11:47.00#ibcon#end of sib2, iclass 20, count 2 2006.201.08:11:47.00#ibcon#*mode == 0, iclass 20, count 2 2006.201.08:11:47.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.08:11:47.00#ibcon#[25=AT04-07\r\n] 2006.201.08:11:47.00#ibcon#*before write, iclass 20, count 2 2006.201.08:11:47.00#ibcon#enter sib2, iclass 20, count 2 2006.201.08:11:47.00#ibcon#flushed, iclass 20, count 2 2006.201.08:11:47.00#ibcon#about to write, iclass 20, count 2 2006.201.08:11:47.00#ibcon#wrote, iclass 20, count 2 2006.201.08:11:47.00#ibcon#about to read 3, iclass 20, count 2 2006.201.08:11:47.03#ibcon#read 3, iclass 20, count 2 2006.201.08:11:47.03#ibcon#about to read 4, iclass 20, count 2 2006.201.08:11:47.03#ibcon#read 4, iclass 20, count 2 2006.201.08:11:47.03#ibcon#about to read 5, iclass 20, count 2 2006.201.08:11:47.03#ibcon#read 5, iclass 20, count 2 2006.201.08:11:47.03#ibcon#about to read 6, iclass 20, count 2 2006.201.08:11:47.03#ibcon#read 6, iclass 20, count 2 2006.201.08:11:47.03#ibcon#end of sib2, iclass 20, count 2 2006.201.08:11:47.03#ibcon#*after write, iclass 20, count 2 2006.201.08:11:47.03#ibcon#*before return 0, iclass 20, count 2 2006.201.08:11:47.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:47.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:47.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.08:11:47.03#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:47.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:47.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:47.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:47.15#ibcon#enter wrdev, iclass 20, count 0 2006.201.08:11:47.15#ibcon#first serial, iclass 20, count 0 2006.201.08:11:47.15#ibcon#enter sib2, iclass 20, count 0 2006.201.08:11:47.15#ibcon#flushed, iclass 20, count 0 2006.201.08:11:47.15#ibcon#about to write, iclass 20, count 0 2006.201.08:11:47.15#ibcon#wrote, iclass 20, count 0 2006.201.08:11:47.15#ibcon#about to read 3, iclass 20, count 0 2006.201.08:11:47.17#ibcon#read 3, iclass 20, count 0 2006.201.08:11:47.17#ibcon#about to read 4, iclass 20, count 0 2006.201.08:11:47.17#ibcon#read 4, iclass 20, count 0 2006.201.08:11:47.17#ibcon#about to read 5, iclass 20, count 0 2006.201.08:11:47.17#ibcon#read 5, iclass 20, count 0 2006.201.08:11:47.17#ibcon#about to read 6, iclass 20, count 0 2006.201.08:11:47.17#ibcon#read 6, iclass 20, count 0 2006.201.08:11:47.17#ibcon#end of sib2, iclass 20, count 0 2006.201.08:11:47.17#ibcon#*mode == 0, iclass 20, count 0 2006.201.08:11:47.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.08:11:47.17#ibcon#[25=USB\r\n] 2006.201.08:11:47.17#ibcon#*before write, iclass 20, count 0 2006.201.08:11:47.17#ibcon#enter sib2, iclass 20, count 0 2006.201.08:11:47.17#ibcon#flushed, iclass 20, count 0 2006.201.08:11:47.17#ibcon#about to write, iclass 20, count 0 2006.201.08:11:47.17#ibcon#wrote, iclass 20, count 0 2006.201.08:11:47.17#ibcon#about to read 3, iclass 20, count 0 2006.201.08:11:47.20#ibcon#read 3, iclass 20, count 0 2006.201.08:11:47.20#ibcon#about to read 4, iclass 20, count 0 2006.201.08:11:47.20#ibcon#read 4, iclass 20, count 0 2006.201.08:11:47.20#ibcon#about to read 5, iclass 20, count 0 2006.201.08:11:47.20#ibcon#read 5, iclass 20, count 0 2006.201.08:11:47.20#ibcon#about to read 6, iclass 20, count 0 2006.201.08:11:47.20#ibcon#read 6, iclass 20, count 0 2006.201.08:11:47.20#ibcon#end of sib2, iclass 20, count 0 2006.201.08:11:47.20#ibcon#*after write, iclass 20, count 0 2006.201.08:11:47.20#ibcon#*before return 0, iclass 20, count 0 2006.201.08:11:47.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:47.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:47.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.08:11:47.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.08:11:47.20$vck44/valo=5,734.99 2006.201.08:11:47.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.08:11:47.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.08:11:47.20#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:47.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:47.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:47.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:47.20#ibcon#enter wrdev, iclass 22, count 0 2006.201.08:11:47.20#ibcon#first serial, iclass 22, count 0 2006.201.08:11:47.20#ibcon#enter sib2, iclass 22, count 0 2006.201.08:11:47.20#ibcon#flushed, iclass 22, count 0 2006.201.08:11:47.20#ibcon#about to write, iclass 22, count 0 2006.201.08:11:47.20#ibcon#wrote, iclass 22, count 0 2006.201.08:11:47.20#ibcon#about to read 3, iclass 22, count 0 2006.201.08:11:47.22#ibcon#read 3, iclass 22, count 0 2006.201.08:11:47.22#ibcon#about to read 4, iclass 22, count 0 2006.201.08:11:47.22#ibcon#read 4, iclass 22, count 0 2006.201.08:11:47.22#ibcon#about to read 5, iclass 22, count 0 2006.201.08:11:47.22#ibcon#read 5, iclass 22, count 0 2006.201.08:11:47.22#ibcon#about to read 6, iclass 22, count 0 2006.201.08:11:47.22#ibcon#read 6, iclass 22, count 0 2006.201.08:11:47.22#ibcon#end of sib2, iclass 22, count 0 2006.201.08:11:47.22#ibcon#*mode == 0, iclass 22, count 0 2006.201.08:11:47.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.08:11:47.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:11:47.22#ibcon#*before write, iclass 22, count 0 2006.201.08:11:47.22#ibcon#enter sib2, iclass 22, count 0 2006.201.08:11:47.22#ibcon#flushed, iclass 22, count 0 2006.201.08:11:47.22#ibcon#about to write, iclass 22, count 0 2006.201.08:11:47.22#ibcon#wrote, iclass 22, count 0 2006.201.08:11:47.22#ibcon#about to read 3, iclass 22, count 0 2006.201.08:11:47.26#ibcon#read 3, iclass 22, count 0 2006.201.08:11:47.26#ibcon#about to read 4, iclass 22, count 0 2006.201.08:11:47.26#ibcon#read 4, iclass 22, count 0 2006.201.08:11:47.26#ibcon#about to read 5, iclass 22, count 0 2006.201.08:11:47.26#ibcon#read 5, iclass 22, count 0 2006.201.08:11:47.26#ibcon#about to read 6, iclass 22, count 0 2006.201.08:11:47.26#ibcon#read 6, iclass 22, count 0 2006.201.08:11:47.26#ibcon#end of sib2, iclass 22, count 0 2006.201.08:11:47.26#ibcon#*after write, iclass 22, count 0 2006.201.08:11:47.26#ibcon#*before return 0, iclass 22, count 0 2006.201.08:11:47.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:47.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:47.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.08:11:47.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.08:11:47.26$vck44/va=5,4 2006.201.08:11:47.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.08:11:47.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.08:11:47.26#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:47.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:47.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:47.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:47.32#ibcon#enter wrdev, iclass 24, count 2 2006.201.08:11:47.32#ibcon#first serial, iclass 24, count 2 2006.201.08:11:47.32#ibcon#enter sib2, iclass 24, count 2 2006.201.08:11:47.32#ibcon#flushed, iclass 24, count 2 2006.201.08:11:47.32#ibcon#about to write, iclass 24, count 2 2006.201.08:11:47.32#ibcon#wrote, iclass 24, count 2 2006.201.08:11:47.32#ibcon#about to read 3, iclass 24, count 2 2006.201.08:11:47.34#ibcon#read 3, iclass 24, count 2 2006.201.08:11:47.34#ibcon#about to read 4, iclass 24, count 2 2006.201.08:11:47.34#ibcon#read 4, iclass 24, count 2 2006.201.08:11:47.34#ibcon#about to read 5, iclass 24, count 2 2006.201.08:11:47.34#ibcon#read 5, iclass 24, count 2 2006.201.08:11:47.34#ibcon#about to read 6, iclass 24, count 2 2006.201.08:11:47.34#ibcon#read 6, iclass 24, count 2 2006.201.08:11:47.34#ibcon#end of sib2, iclass 24, count 2 2006.201.08:11:47.34#ibcon#*mode == 0, iclass 24, count 2 2006.201.08:11:47.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.08:11:47.34#ibcon#[25=AT05-04\r\n] 2006.201.08:11:47.34#ibcon#*before write, iclass 24, count 2 2006.201.08:11:47.34#ibcon#enter sib2, iclass 24, count 2 2006.201.08:11:47.34#ibcon#flushed, iclass 24, count 2 2006.201.08:11:47.34#ibcon#about to write, iclass 24, count 2 2006.201.08:11:47.34#ibcon#wrote, iclass 24, count 2 2006.201.08:11:47.34#ibcon#about to read 3, iclass 24, count 2 2006.201.08:11:47.37#ibcon#read 3, iclass 24, count 2 2006.201.08:11:47.37#ibcon#about to read 4, iclass 24, count 2 2006.201.08:11:47.37#ibcon#read 4, iclass 24, count 2 2006.201.08:11:47.37#ibcon#about to read 5, iclass 24, count 2 2006.201.08:11:47.37#ibcon#read 5, iclass 24, count 2 2006.201.08:11:47.37#ibcon#about to read 6, iclass 24, count 2 2006.201.08:11:47.37#ibcon#read 6, iclass 24, count 2 2006.201.08:11:47.37#ibcon#end of sib2, iclass 24, count 2 2006.201.08:11:47.37#ibcon#*after write, iclass 24, count 2 2006.201.08:11:47.37#ibcon#*before return 0, iclass 24, count 2 2006.201.08:11:47.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:47.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:47.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.08:11:47.37#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:47.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:47.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:47.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:47.49#ibcon#enter wrdev, iclass 24, count 0 2006.201.08:11:47.49#ibcon#first serial, iclass 24, count 0 2006.201.08:11:47.49#ibcon#enter sib2, iclass 24, count 0 2006.201.08:11:47.49#ibcon#flushed, iclass 24, count 0 2006.201.08:11:47.49#ibcon#about to write, iclass 24, count 0 2006.201.08:11:47.49#ibcon#wrote, iclass 24, count 0 2006.201.08:11:47.49#ibcon#about to read 3, iclass 24, count 0 2006.201.08:11:47.51#ibcon#read 3, iclass 24, count 0 2006.201.08:11:47.51#ibcon#about to read 4, iclass 24, count 0 2006.201.08:11:47.51#ibcon#read 4, iclass 24, count 0 2006.201.08:11:47.51#ibcon#about to read 5, iclass 24, count 0 2006.201.08:11:47.51#ibcon#read 5, iclass 24, count 0 2006.201.08:11:47.51#ibcon#about to read 6, iclass 24, count 0 2006.201.08:11:47.51#ibcon#read 6, iclass 24, count 0 2006.201.08:11:47.51#ibcon#end of sib2, iclass 24, count 0 2006.201.08:11:47.51#ibcon#*mode == 0, iclass 24, count 0 2006.201.08:11:47.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.08:11:47.51#ibcon#[25=USB\r\n] 2006.201.08:11:47.51#ibcon#*before write, iclass 24, count 0 2006.201.08:11:47.51#ibcon#enter sib2, iclass 24, count 0 2006.201.08:11:47.51#ibcon#flushed, iclass 24, count 0 2006.201.08:11:47.51#ibcon#about to write, iclass 24, count 0 2006.201.08:11:47.51#ibcon#wrote, iclass 24, count 0 2006.201.08:11:47.51#ibcon#about to read 3, iclass 24, count 0 2006.201.08:11:47.54#ibcon#read 3, iclass 24, count 0 2006.201.08:11:47.54#ibcon#about to read 4, iclass 24, count 0 2006.201.08:11:47.54#ibcon#read 4, iclass 24, count 0 2006.201.08:11:47.54#ibcon#about to read 5, iclass 24, count 0 2006.201.08:11:47.54#ibcon#read 5, iclass 24, count 0 2006.201.08:11:47.54#ibcon#about to read 6, iclass 24, count 0 2006.201.08:11:47.54#ibcon#read 6, iclass 24, count 0 2006.201.08:11:47.54#ibcon#end of sib2, iclass 24, count 0 2006.201.08:11:47.54#ibcon#*after write, iclass 24, count 0 2006.201.08:11:47.54#ibcon#*before return 0, iclass 24, count 0 2006.201.08:11:47.54#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:47.54#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:47.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.08:11:47.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.08:11:47.54$vck44/valo=6,814.99 2006.201.08:11:47.54#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.08:11:47.54#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.08:11:47.54#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:47.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:47.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:47.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:47.54#ibcon#enter wrdev, iclass 26, count 0 2006.201.08:11:47.54#ibcon#first serial, iclass 26, count 0 2006.201.08:11:47.54#ibcon#enter sib2, iclass 26, count 0 2006.201.08:11:47.54#ibcon#flushed, iclass 26, count 0 2006.201.08:11:47.54#ibcon#about to write, iclass 26, count 0 2006.201.08:11:47.54#ibcon#wrote, iclass 26, count 0 2006.201.08:11:47.54#ibcon#about to read 3, iclass 26, count 0 2006.201.08:11:47.56#ibcon#read 3, iclass 26, count 0 2006.201.08:11:47.56#ibcon#about to read 4, iclass 26, count 0 2006.201.08:11:47.56#ibcon#read 4, iclass 26, count 0 2006.201.08:11:47.56#ibcon#about to read 5, iclass 26, count 0 2006.201.08:11:47.56#ibcon#read 5, iclass 26, count 0 2006.201.08:11:47.56#ibcon#about to read 6, iclass 26, count 0 2006.201.08:11:47.56#ibcon#read 6, iclass 26, count 0 2006.201.08:11:47.56#ibcon#end of sib2, iclass 26, count 0 2006.201.08:11:47.56#ibcon#*mode == 0, iclass 26, count 0 2006.201.08:11:47.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.08:11:47.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:11:47.56#ibcon#*before write, iclass 26, count 0 2006.201.08:11:47.56#ibcon#enter sib2, iclass 26, count 0 2006.201.08:11:47.56#ibcon#flushed, iclass 26, count 0 2006.201.08:11:47.56#ibcon#about to write, iclass 26, count 0 2006.201.08:11:47.56#ibcon#wrote, iclass 26, count 0 2006.201.08:11:47.56#ibcon#about to read 3, iclass 26, count 0 2006.201.08:11:47.61#ibcon#read 3, iclass 26, count 0 2006.201.08:11:47.61#ibcon#about to read 4, iclass 26, count 0 2006.201.08:11:47.61#ibcon#read 4, iclass 26, count 0 2006.201.08:11:47.61#ibcon#about to read 5, iclass 26, count 0 2006.201.08:11:47.61#ibcon#read 5, iclass 26, count 0 2006.201.08:11:47.61#ibcon#about to read 6, iclass 26, count 0 2006.201.08:11:47.61#ibcon#read 6, iclass 26, count 0 2006.201.08:11:47.61#ibcon#end of sib2, iclass 26, count 0 2006.201.08:11:47.61#ibcon#*after write, iclass 26, count 0 2006.201.08:11:47.61#ibcon#*before return 0, iclass 26, count 0 2006.201.08:11:47.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:47.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:47.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.08:11:47.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.08:11:47.61$vck44/va=6,5 2006.201.08:11:47.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.08:11:47.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.08:11:47.61#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:47.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:47.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:47.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:47.66#ibcon#enter wrdev, iclass 28, count 2 2006.201.08:11:47.66#ibcon#first serial, iclass 28, count 2 2006.201.08:11:47.66#ibcon#enter sib2, iclass 28, count 2 2006.201.08:11:47.66#ibcon#flushed, iclass 28, count 2 2006.201.08:11:47.66#ibcon#about to write, iclass 28, count 2 2006.201.08:11:47.66#ibcon#wrote, iclass 28, count 2 2006.201.08:11:47.66#ibcon#about to read 3, iclass 28, count 2 2006.201.08:11:47.68#ibcon#read 3, iclass 28, count 2 2006.201.08:11:47.68#ibcon#about to read 4, iclass 28, count 2 2006.201.08:11:47.68#ibcon#read 4, iclass 28, count 2 2006.201.08:11:47.68#ibcon#about to read 5, iclass 28, count 2 2006.201.08:11:47.68#ibcon#read 5, iclass 28, count 2 2006.201.08:11:47.68#ibcon#about to read 6, iclass 28, count 2 2006.201.08:11:47.68#ibcon#read 6, iclass 28, count 2 2006.201.08:11:47.68#ibcon#end of sib2, iclass 28, count 2 2006.201.08:11:47.68#ibcon#*mode == 0, iclass 28, count 2 2006.201.08:11:47.68#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.08:11:47.68#ibcon#[25=AT06-05\r\n] 2006.201.08:11:47.68#ibcon#*before write, iclass 28, count 2 2006.201.08:11:47.68#ibcon#enter sib2, iclass 28, count 2 2006.201.08:11:47.68#ibcon#flushed, iclass 28, count 2 2006.201.08:11:47.68#ibcon#about to write, iclass 28, count 2 2006.201.08:11:47.68#ibcon#wrote, iclass 28, count 2 2006.201.08:11:47.68#ibcon#about to read 3, iclass 28, count 2 2006.201.08:11:47.71#ibcon#read 3, iclass 28, count 2 2006.201.08:11:47.71#ibcon#about to read 4, iclass 28, count 2 2006.201.08:11:47.71#ibcon#read 4, iclass 28, count 2 2006.201.08:11:47.71#ibcon#about to read 5, iclass 28, count 2 2006.201.08:11:47.71#ibcon#read 5, iclass 28, count 2 2006.201.08:11:47.71#ibcon#about to read 6, iclass 28, count 2 2006.201.08:11:47.71#ibcon#read 6, iclass 28, count 2 2006.201.08:11:47.71#ibcon#end of sib2, iclass 28, count 2 2006.201.08:11:47.71#ibcon#*after write, iclass 28, count 2 2006.201.08:11:47.71#ibcon#*before return 0, iclass 28, count 2 2006.201.08:11:47.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:47.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:47.71#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.08:11:47.71#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:47.71#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:47.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:47.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:47.83#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:11:47.83#ibcon#first serial, iclass 28, count 0 2006.201.08:11:47.83#ibcon#enter sib2, iclass 28, count 0 2006.201.08:11:47.83#ibcon#flushed, iclass 28, count 0 2006.201.08:11:47.83#ibcon#about to write, iclass 28, count 0 2006.201.08:11:47.83#ibcon#wrote, iclass 28, count 0 2006.201.08:11:47.83#ibcon#about to read 3, iclass 28, count 0 2006.201.08:11:47.85#ibcon#read 3, iclass 28, count 0 2006.201.08:11:47.85#ibcon#about to read 4, iclass 28, count 0 2006.201.08:11:47.85#ibcon#read 4, iclass 28, count 0 2006.201.08:11:47.85#ibcon#about to read 5, iclass 28, count 0 2006.201.08:11:47.85#ibcon#read 5, iclass 28, count 0 2006.201.08:11:47.85#ibcon#about to read 6, iclass 28, count 0 2006.201.08:11:47.85#ibcon#read 6, iclass 28, count 0 2006.201.08:11:47.85#ibcon#end of sib2, iclass 28, count 0 2006.201.08:11:47.85#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:11:47.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:11:47.85#ibcon#[25=USB\r\n] 2006.201.08:11:47.85#ibcon#*before write, iclass 28, count 0 2006.201.08:11:47.85#ibcon#enter sib2, iclass 28, count 0 2006.201.08:11:47.85#ibcon#flushed, iclass 28, count 0 2006.201.08:11:47.85#ibcon#about to write, iclass 28, count 0 2006.201.08:11:47.85#ibcon#wrote, iclass 28, count 0 2006.201.08:11:47.85#ibcon#about to read 3, iclass 28, count 0 2006.201.08:11:47.88#ibcon#read 3, iclass 28, count 0 2006.201.08:11:47.88#ibcon#about to read 4, iclass 28, count 0 2006.201.08:11:47.88#ibcon#read 4, iclass 28, count 0 2006.201.08:11:47.88#ibcon#about to read 5, iclass 28, count 0 2006.201.08:11:47.88#ibcon#read 5, iclass 28, count 0 2006.201.08:11:47.88#ibcon#about to read 6, iclass 28, count 0 2006.201.08:11:47.88#ibcon#read 6, iclass 28, count 0 2006.201.08:11:47.88#ibcon#end of sib2, iclass 28, count 0 2006.201.08:11:47.88#ibcon#*after write, iclass 28, count 0 2006.201.08:11:47.88#ibcon#*before return 0, iclass 28, count 0 2006.201.08:11:47.88#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:47.88#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:47.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:11:47.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:11:47.88$vck44/valo=7,864.99 2006.201.08:11:47.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.08:11:47.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.08:11:47.88#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:47.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:47.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:47.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:47.88#ibcon#enter wrdev, iclass 30, count 0 2006.201.08:11:47.88#ibcon#first serial, iclass 30, count 0 2006.201.08:11:47.88#ibcon#enter sib2, iclass 30, count 0 2006.201.08:11:47.88#ibcon#flushed, iclass 30, count 0 2006.201.08:11:47.88#ibcon#about to write, iclass 30, count 0 2006.201.08:11:47.88#ibcon#wrote, iclass 30, count 0 2006.201.08:11:47.88#ibcon#about to read 3, iclass 30, count 0 2006.201.08:11:47.90#ibcon#read 3, iclass 30, count 0 2006.201.08:11:47.90#ibcon#about to read 4, iclass 30, count 0 2006.201.08:11:47.90#ibcon#read 4, iclass 30, count 0 2006.201.08:11:47.90#ibcon#about to read 5, iclass 30, count 0 2006.201.08:11:47.90#ibcon#read 5, iclass 30, count 0 2006.201.08:11:47.90#ibcon#about to read 6, iclass 30, count 0 2006.201.08:11:47.90#ibcon#read 6, iclass 30, count 0 2006.201.08:11:47.90#ibcon#end of sib2, iclass 30, count 0 2006.201.08:11:47.90#ibcon#*mode == 0, iclass 30, count 0 2006.201.08:11:47.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.08:11:47.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:11:47.90#ibcon#*before write, iclass 30, count 0 2006.201.08:11:47.90#ibcon#enter sib2, iclass 30, count 0 2006.201.08:11:47.90#ibcon#flushed, iclass 30, count 0 2006.201.08:11:47.90#ibcon#about to write, iclass 30, count 0 2006.201.08:11:47.90#ibcon#wrote, iclass 30, count 0 2006.201.08:11:47.90#ibcon#about to read 3, iclass 30, count 0 2006.201.08:11:47.94#ibcon#read 3, iclass 30, count 0 2006.201.08:11:47.94#ibcon#about to read 4, iclass 30, count 0 2006.201.08:11:47.94#ibcon#read 4, iclass 30, count 0 2006.201.08:11:47.94#ibcon#about to read 5, iclass 30, count 0 2006.201.08:11:47.94#ibcon#read 5, iclass 30, count 0 2006.201.08:11:47.94#ibcon#about to read 6, iclass 30, count 0 2006.201.08:11:47.94#ibcon#read 6, iclass 30, count 0 2006.201.08:11:47.94#ibcon#end of sib2, iclass 30, count 0 2006.201.08:11:47.94#ibcon#*after write, iclass 30, count 0 2006.201.08:11:47.94#ibcon#*before return 0, iclass 30, count 0 2006.201.08:11:47.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:47.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:47.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.08:11:47.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.08:11:47.94$vck44/va=7,5 2006.201.08:11:47.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.08:11:47.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.08:11:47.94#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:47.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:48.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:48.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:48.00#ibcon#enter wrdev, iclass 32, count 2 2006.201.08:11:48.00#ibcon#first serial, iclass 32, count 2 2006.201.08:11:48.00#ibcon#enter sib2, iclass 32, count 2 2006.201.08:11:48.00#ibcon#flushed, iclass 32, count 2 2006.201.08:11:48.00#ibcon#about to write, iclass 32, count 2 2006.201.08:11:48.00#ibcon#wrote, iclass 32, count 2 2006.201.08:11:48.00#ibcon#about to read 3, iclass 32, count 2 2006.201.08:11:48.02#ibcon#read 3, iclass 32, count 2 2006.201.08:11:48.02#ibcon#about to read 4, iclass 32, count 2 2006.201.08:11:48.02#ibcon#read 4, iclass 32, count 2 2006.201.08:11:48.02#ibcon#about to read 5, iclass 32, count 2 2006.201.08:11:48.02#ibcon#read 5, iclass 32, count 2 2006.201.08:11:48.02#ibcon#about to read 6, iclass 32, count 2 2006.201.08:11:48.02#ibcon#read 6, iclass 32, count 2 2006.201.08:11:48.02#ibcon#end of sib2, iclass 32, count 2 2006.201.08:11:48.02#ibcon#*mode == 0, iclass 32, count 2 2006.201.08:11:48.02#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.08:11:48.02#ibcon#[25=AT07-05\r\n] 2006.201.08:11:48.02#ibcon#*before write, iclass 32, count 2 2006.201.08:11:48.02#ibcon#enter sib2, iclass 32, count 2 2006.201.08:11:48.02#ibcon#flushed, iclass 32, count 2 2006.201.08:11:48.02#ibcon#about to write, iclass 32, count 2 2006.201.08:11:48.02#ibcon#wrote, iclass 32, count 2 2006.201.08:11:48.02#ibcon#about to read 3, iclass 32, count 2 2006.201.08:11:48.05#ibcon#read 3, iclass 32, count 2 2006.201.08:11:48.05#ibcon#about to read 4, iclass 32, count 2 2006.201.08:11:48.05#ibcon#read 4, iclass 32, count 2 2006.201.08:11:48.05#ibcon#about to read 5, iclass 32, count 2 2006.201.08:11:48.05#ibcon#read 5, iclass 32, count 2 2006.201.08:11:48.05#ibcon#about to read 6, iclass 32, count 2 2006.201.08:11:48.05#ibcon#read 6, iclass 32, count 2 2006.201.08:11:48.05#ibcon#end of sib2, iclass 32, count 2 2006.201.08:11:48.05#ibcon#*after write, iclass 32, count 2 2006.201.08:11:48.05#ibcon#*before return 0, iclass 32, count 2 2006.201.08:11:48.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:48.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:48.05#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.08:11:48.05#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:48.05#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:48.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:48.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:48.17#ibcon#enter wrdev, iclass 32, count 0 2006.201.08:11:48.17#ibcon#first serial, iclass 32, count 0 2006.201.08:11:48.17#ibcon#enter sib2, iclass 32, count 0 2006.201.08:11:48.17#ibcon#flushed, iclass 32, count 0 2006.201.08:11:48.17#ibcon#about to write, iclass 32, count 0 2006.201.08:11:48.17#ibcon#wrote, iclass 32, count 0 2006.201.08:11:48.17#ibcon#about to read 3, iclass 32, count 0 2006.201.08:11:48.19#ibcon#read 3, iclass 32, count 0 2006.201.08:11:48.19#ibcon#about to read 4, iclass 32, count 0 2006.201.08:11:48.19#ibcon#read 4, iclass 32, count 0 2006.201.08:11:48.19#ibcon#about to read 5, iclass 32, count 0 2006.201.08:11:48.19#ibcon#read 5, iclass 32, count 0 2006.201.08:11:48.19#ibcon#about to read 6, iclass 32, count 0 2006.201.08:11:48.19#ibcon#read 6, iclass 32, count 0 2006.201.08:11:48.19#ibcon#end of sib2, iclass 32, count 0 2006.201.08:11:48.19#ibcon#*mode == 0, iclass 32, count 0 2006.201.08:11:48.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.08:11:48.19#ibcon#[25=USB\r\n] 2006.201.08:11:48.19#ibcon#*before write, iclass 32, count 0 2006.201.08:11:48.19#ibcon#enter sib2, iclass 32, count 0 2006.201.08:11:48.19#ibcon#flushed, iclass 32, count 0 2006.201.08:11:48.19#ibcon#about to write, iclass 32, count 0 2006.201.08:11:48.19#ibcon#wrote, iclass 32, count 0 2006.201.08:11:48.19#ibcon#about to read 3, iclass 32, count 0 2006.201.08:11:48.22#ibcon#read 3, iclass 32, count 0 2006.201.08:11:48.22#ibcon#about to read 4, iclass 32, count 0 2006.201.08:11:48.22#ibcon#read 4, iclass 32, count 0 2006.201.08:11:48.22#ibcon#about to read 5, iclass 32, count 0 2006.201.08:11:48.22#ibcon#read 5, iclass 32, count 0 2006.201.08:11:48.22#ibcon#about to read 6, iclass 32, count 0 2006.201.08:11:48.22#ibcon#read 6, iclass 32, count 0 2006.201.08:11:48.22#ibcon#end of sib2, iclass 32, count 0 2006.201.08:11:48.22#ibcon#*after write, iclass 32, count 0 2006.201.08:11:48.22#ibcon#*before return 0, iclass 32, count 0 2006.201.08:11:48.22#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:48.22#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:48.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.08:11:48.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.08:11:48.22$vck44/valo=8,884.99 2006.201.08:11:48.22#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.08:11:48.22#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.08:11:48.22#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:48.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:48.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:48.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:48.22#ibcon#enter wrdev, iclass 34, count 0 2006.201.08:11:48.22#ibcon#first serial, iclass 34, count 0 2006.201.08:11:48.22#ibcon#enter sib2, iclass 34, count 0 2006.201.08:11:48.22#ibcon#flushed, iclass 34, count 0 2006.201.08:11:48.22#ibcon#about to write, iclass 34, count 0 2006.201.08:11:48.22#ibcon#wrote, iclass 34, count 0 2006.201.08:11:48.22#ibcon#about to read 3, iclass 34, count 0 2006.201.08:11:48.24#ibcon#read 3, iclass 34, count 0 2006.201.08:11:48.24#ibcon#about to read 4, iclass 34, count 0 2006.201.08:11:48.24#ibcon#read 4, iclass 34, count 0 2006.201.08:11:48.24#ibcon#about to read 5, iclass 34, count 0 2006.201.08:11:48.24#ibcon#read 5, iclass 34, count 0 2006.201.08:11:48.24#ibcon#about to read 6, iclass 34, count 0 2006.201.08:11:48.24#ibcon#read 6, iclass 34, count 0 2006.201.08:11:48.24#ibcon#end of sib2, iclass 34, count 0 2006.201.08:11:48.24#ibcon#*mode == 0, iclass 34, count 0 2006.201.08:11:48.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.08:11:48.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:11:48.24#ibcon#*before write, iclass 34, count 0 2006.201.08:11:48.24#ibcon#enter sib2, iclass 34, count 0 2006.201.08:11:48.24#ibcon#flushed, iclass 34, count 0 2006.201.08:11:48.24#ibcon#about to write, iclass 34, count 0 2006.201.08:11:48.24#ibcon#wrote, iclass 34, count 0 2006.201.08:11:48.24#ibcon#about to read 3, iclass 34, count 0 2006.201.08:11:48.28#ibcon#read 3, iclass 34, count 0 2006.201.08:11:48.28#ibcon#about to read 4, iclass 34, count 0 2006.201.08:11:48.28#ibcon#read 4, iclass 34, count 0 2006.201.08:11:48.28#ibcon#about to read 5, iclass 34, count 0 2006.201.08:11:48.28#ibcon#read 5, iclass 34, count 0 2006.201.08:11:48.28#ibcon#about to read 6, iclass 34, count 0 2006.201.08:11:48.28#ibcon#read 6, iclass 34, count 0 2006.201.08:11:48.28#ibcon#end of sib2, iclass 34, count 0 2006.201.08:11:48.28#ibcon#*after write, iclass 34, count 0 2006.201.08:11:48.28#ibcon#*before return 0, iclass 34, count 0 2006.201.08:11:48.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:48.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:48.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.08:11:48.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.08:11:48.28$vck44/va=8,4 2006.201.08:11:48.28#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.08:11:48.28#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.08:11:48.28#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:48.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.08:11:48.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.08:11:48.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.08:11:48.34#ibcon#enter wrdev, iclass 36, count 2 2006.201.08:11:48.34#ibcon#first serial, iclass 36, count 2 2006.201.08:11:48.34#ibcon#enter sib2, iclass 36, count 2 2006.201.08:11:48.34#ibcon#flushed, iclass 36, count 2 2006.201.08:11:48.34#ibcon#about to write, iclass 36, count 2 2006.201.08:11:48.34#ibcon#wrote, iclass 36, count 2 2006.201.08:11:48.34#ibcon#about to read 3, iclass 36, count 2 2006.201.08:11:48.36#ibcon#read 3, iclass 36, count 2 2006.201.08:11:48.36#ibcon#about to read 4, iclass 36, count 2 2006.201.08:11:48.36#ibcon#read 4, iclass 36, count 2 2006.201.08:11:48.36#ibcon#about to read 5, iclass 36, count 2 2006.201.08:11:48.36#ibcon#read 5, iclass 36, count 2 2006.201.08:11:48.36#ibcon#about to read 6, iclass 36, count 2 2006.201.08:11:48.36#ibcon#read 6, iclass 36, count 2 2006.201.08:11:48.36#ibcon#end of sib2, iclass 36, count 2 2006.201.08:11:48.36#ibcon#*mode == 0, iclass 36, count 2 2006.201.08:11:48.36#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.08:11:48.36#ibcon#[25=AT08-04\r\n] 2006.201.08:11:48.36#ibcon#*before write, iclass 36, count 2 2006.201.08:11:48.36#ibcon#enter sib2, iclass 36, count 2 2006.201.08:11:48.36#ibcon#flushed, iclass 36, count 2 2006.201.08:11:48.36#ibcon#about to write, iclass 36, count 2 2006.201.08:11:48.36#ibcon#wrote, iclass 36, count 2 2006.201.08:11:48.36#ibcon#about to read 3, iclass 36, count 2 2006.201.08:11:48.39#ibcon#read 3, iclass 36, count 2 2006.201.08:11:48.39#ibcon#about to read 4, iclass 36, count 2 2006.201.08:11:48.39#ibcon#read 4, iclass 36, count 2 2006.201.08:11:48.39#ibcon#about to read 5, iclass 36, count 2 2006.201.08:11:48.39#ibcon#read 5, iclass 36, count 2 2006.201.08:11:48.39#ibcon#about to read 6, iclass 36, count 2 2006.201.08:11:48.39#ibcon#read 6, iclass 36, count 2 2006.201.08:11:48.39#ibcon#end of sib2, iclass 36, count 2 2006.201.08:11:48.39#ibcon#*after write, iclass 36, count 2 2006.201.08:11:48.39#ibcon#*before return 0, iclass 36, count 2 2006.201.08:11:48.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.08:11:48.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.08:11:48.39#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.08:11:48.39#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:48.39#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.08:11:48.51#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.08:11:48.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.08:11:48.51#ibcon#enter wrdev, iclass 36, count 0 2006.201.08:11:48.51#ibcon#first serial, iclass 36, count 0 2006.201.08:11:48.51#ibcon#enter sib2, iclass 36, count 0 2006.201.08:11:48.51#ibcon#flushed, iclass 36, count 0 2006.201.08:11:48.51#ibcon#about to write, iclass 36, count 0 2006.201.08:11:48.51#ibcon#wrote, iclass 36, count 0 2006.201.08:11:48.51#ibcon#about to read 3, iclass 36, count 0 2006.201.08:11:48.53#ibcon#read 3, iclass 36, count 0 2006.201.08:11:48.53#ibcon#about to read 4, iclass 36, count 0 2006.201.08:11:48.53#ibcon#read 4, iclass 36, count 0 2006.201.08:11:48.53#ibcon#about to read 5, iclass 36, count 0 2006.201.08:11:48.53#ibcon#read 5, iclass 36, count 0 2006.201.08:11:48.53#ibcon#about to read 6, iclass 36, count 0 2006.201.08:11:48.53#ibcon#read 6, iclass 36, count 0 2006.201.08:11:48.53#ibcon#end of sib2, iclass 36, count 0 2006.201.08:11:48.53#ibcon#*mode == 0, iclass 36, count 0 2006.201.08:11:48.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.08:11:48.53#ibcon#[25=USB\r\n] 2006.201.08:11:48.53#ibcon#*before write, iclass 36, count 0 2006.201.08:11:48.53#ibcon#enter sib2, iclass 36, count 0 2006.201.08:11:48.53#ibcon#flushed, iclass 36, count 0 2006.201.08:11:48.53#ibcon#about to write, iclass 36, count 0 2006.201.08:11:48.53#ibcon#wrote, iclass 36, count 0 2006.201.08:11:48.53#ibcon#about to read 3, iclass 36, count 0 2006.201.08:11:48.56#ibcon#read 3, iclass 36, count 0 2006.201.08:11:48.56#ibcon#about to read 4, iclass 36, count 0 2006.201.08:11:48.56#ibcon#read 4, iclass 36, count 0 2006.201.08:11:48.56#ibcon#about to read 5, iclass 36, count 0 2006.201.08:11:48.56#ibcon#read 5, iclass 36, count 0 2006.201.08:11:48.56#ibcon#about to read 6, iclass 36, count 0 2006.201.08:11:48.56#ibcon#read 6, iclass 36, count 0 2006.201.08:11:48.56#ibcon#end of sib2, iclass 36, count 0 2006.201.08:11:48.56#ibcon#*after write, iclass 36, count 0 2006.201.08:11:48.56#ibcon#*before return 0, iclass 36, count 0 2006.201.08:11:48.56#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.08:11:48.56#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.08:11:48.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.08:11:48.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.08:11:48.56$vck44/vblo=1,629.99 2006.201.08:11:48.56#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.08:11:48.56#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.08:11:48.56#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:48.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.08:11:48.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.08:11:48.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.08:11:48.56#ibcon#enter wrdev, iclass 38, count 0 2006.201.08:11:48.56#ibcon#first serial, iclass 38, count 0 2006.201.08:11:48.56#ibcon#enter sib2, iclass 38, count 0 2006.201.08:11:48.56#ibcon#flushed, iclass 38, count 0 2006.201.08:11:48.56#ibcon#about to write, iclass 38, count 0 2006.201.08:11:48.56#ibcon#wrote, iclass 38, count 0 2006.201.08:11:48.56#ibcon#about to read 3, iclass 38, count 0 2006.201.08:11:48.58#ibcon#read 3, iclass 38, count 0 2006.201.08:11:48.58#ibcon#about to read 4, iclass 38, count 0 2006.201.08:11:48.58#ibcon#read 4, iclass 38, count 0 2006.201.08:11:48.58#ibcon#about to read 5, iclass 38, count 0 2006.201.08:11:48.58#ibcon#read 5, iclass 38, count 0 2006.201.08:11:48.58#ibcon#about to read 6, iclass 38, count 0 2006.201.08:11:48.58#ibcon#read 6, iclass 38, count 0 2006.201.08:11:48.58#ibcon#end of sib2, iclass 38, count 0 2006.201.08:11:48.58#ibcon#*mode == 0, iclass 38, count 0 2006.201.08:11:48.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.08:11:48.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:11:48.58#ibcon#*before write, iclass 38, count 0 2006.201.08:11:48.58#ibcon#enter sib2, iclass 38, count 0 2006.201.08:11:48.58#ibcon#flushed, iclass 38, count 0 2006.201.08:11:48.58#ibcon#about to write, iclass 38, count 0 2006.201.08:11:48.58#ibcon#wrote, iclass 38, count 0 2006.201.08:11:48.58#ibcon#about to read 3, iclass 38, count 0 2006.201.08:11:48.63#ibcon#read 3, iclass 38, count 0 2006.201.08:11:48.63#ibcon#about to read 4, iclass 38, count 0 2006.201.08:11:48.63#ibcon#read 4, iclass 38, count 0 2006.201.08:11:48.63#ibcon#about to read 5, iclass 38, count 0 2006.201.08:11:48.63#ibcon#read 5, iclass 38, count 0 2006.201.08:11:48.63#ibcon#about to read 6, iclass 38, count 0 2006.201.08:11:48.63#ibcon#read 6, iclass 38, count 0 2006.201.08:11:48.63#ibcon#end of sib2, iclass 38, count 0 2006.201.08:11:48.63#ibcon#*after write, iclass 38, count 0 2006.201.08:11:48.63#ibcon#*before return 0, iclass 38, count 0 2006.201.08:11:48.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.08:11:48.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.08:11:48.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.08:11:48.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.08:11:48.63$vck44/vb=1,4 2006.201.08:11:48.63#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.08:11:48.63#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.08:11:48.63#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:48.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.08:11:48.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.08:11:48.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.08:11:48.63#ibcon#enter wrdev, iclass 40, count 2 2006.201.08:11:48.63#ibcon#first serial, iclass 40, count 2 2006.201.08:11:48.63#ibcon#enter sib2, iclass 40, count 2 2006.201.08:11:48.63#ibcon#flushed, iclass 40, count 2 2006.201.08:11:48.63#ibcon#about to write, iclass 40, count 2 2006.201.08:11:48.63#ibcon#wrote, iclass 40, count 2 2006.201.08:11:48.63#ibcon#about to read 3, iclass 40, count 2 2006.201.08:11:48.65#ibcon#read 3, iclass 40, count 2 2006.201.08:11:48.65#ibcon#about to read 4, iclass 40, count 2 2006.201.08:11:48.65#ibcon#read 4, iclass 40, count 2 2006.201.08:11:48.65#ibcon#about to read 5, iclass 40, count 2 2006.201.08:11:48.65#ibcon#read 5, iclass 40, count 2 2006.201.08:11:48.65#ibcon#about to read 6, iclass 40, count 2 2006.201.08:11:48.65#ibcon#read 6, iclass 40, count 2 2006.201.08:11:48.65#ibcon#end of sib2, iclass 40, count 2 2006.201.08:11:48.65#ibcon#*mode == 0, iclass 40, count 2 2006.201.08:11:48.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.08:11:48.65#ibcon#[27=AT01-04\r\n] 2006.201.08:11:48.65#ibcon#*before write, iclass 40, count 2 2006.201.08:11:48.65#ibcon#enter sib2, iclass 40, count 2 2006.201.08:11:48.65#ibcon#flushed, iclass 40, count 2 2006.201.08:11:48.65#ibcon#about to write, iclass 40, count 2 2006.201.08:11:48.65#ibcon#wrote, iclass 40, count 2 2006.201.08:11:48.65#ibcon#about to read 3, iclass 40, count 2 2006.201.08:11:48.68#ibcon#read 3, iclass 40, count 2 2006.201.08:11:48.68#ibcon#about to read 4, iclass 40, count 2 2006.201.08:11:48.68#ibcon#read 4, iclass 40, count 2 2006.201.08:11:48.68#ibcon#about to read 5, iclass 40, count 2 2006.201.08:11:48.68#ibcon#read 5, iclass 40, count 2 2006.201.08:11:48.68#ibcon#about to read 6, iclass 40, count 2 2006.201.08:11:48.68#ibcon#read 6, iclass 40, count 2 2006.201.08:11:48.68#ibcon#end of sib2, iclass 40, count 2 2006.201.08:11:48.68#ibcon#*after write, iclass 40, count 2 2006.201.08:11:48.68#ibcon#*before return 0, iclass 40, count 2 2006.201.08:11:48.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.08:11:48.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.08:11:48.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.08:11:48.68#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:48.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.08:11:48.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.08:11:48.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.08:11:48.80#ibcon#enter wrdev, iclass 40, count 0 2006.201.08:11:48.80#ibcon#first serial, iclass 40, count 0 2006.201.08:11:48.80#ibcon#enter sib2, iclass 40, count 0 2006.201.08:11:48.80#ibcon#flushed, iclass 40, count 0 2006.201.08:11:48.80#ibcon#about to write, iclass 40, count 0 2006.201.08:11:48.80#ibcon#wrote, iclass 40, count 0 2006.201.08:11:48.80#ibcon#about to read 3, iclass 40, count 0 2006.201.08:11:48.82#ibcon#read 3, iclass 40, count 0 2006.201.08:11:48.82#ibcon#about to read 4, iclass 40, count 0 2006.201.08:11:48.82#ibcon#read 4, iclass 40, count 0 2006.201.08:11:48.82#ibcon#about to read 5, iclass 40, count 0 2006.201.08:11:48.82#ibcon#read 5, iclass 40, count 0 2006.201.08:11:48.82#ibcon#about to read 6, iclass 40, count 0 2006.201.08:11:48.82#ibcon#read 6, iclass 40, count 0 2006.201.08:11:48.82#ibcon#end of sib2, iclass 40, count 0 2006.201.08:11:48.82#ibcon#*mode == 0, iclass 40, count 0 2006.201.08:11:48.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.08:11:48.82#ibcon#[27=USB\r\n] 2006.201.08:11:48.82#ibcon#*before write, iclass 40, count 0 2006.201.08:11:48.82#ibcon#enter sib2, iclass 40, count 0 2006.201.08:11:48.82#ibcon#flushed, iclass 40, count 0 2006.201.08:11:48.82#ibcon#about to write, iclass 40, count 0 2006.201.08:11:48.82#ibcon#wrote, iclass 40, count 0 2006.201.08:11:48.82#ibcon#about to read 3, iclass 40, count 0 2006.201.08:11:48.85#ibcon#read 3, iclass 40, count 0 2006.201.08:11:48.85#ibcon#about to read 4, iclass 40, count 0 2006.201.08:11:48.85#ibcon#read 4, iclass 40, count 0 2006.201.08:11:48.85#ibcon#about to read 5, iclass 40, count 0 2006.201.08:11:48.85#ibcon#read 5, iclass 40, count 0 2006.201.08:11:48.85#ibcon#about to read 6, iclass 40, count 0 2006.201.08:11:48.85#ibcon#read 6, iclass 40, count 0 2006.201.08:11:48.85#ibcon#end of sib2, iclass 40, count 0 2006.201.08:11:48.85#ibcon#*after write, iclass 40, count 0 2006.201.08:11:48.85#ibcon#*before return 0, iclass 40, count 0 2006.201.08:11:48.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.08:11:48.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.08:11:48.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.08:11:48.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.08:11:48.85$vck44/vblo=2,634.99 2006.201.08:11:48.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.08:11:48.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.08:11:48.85#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:48.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:48.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:48.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:48.85#ibcon#enter wrdev, iclass 4, count 0 2006.201.08:11:48.85#ibcon#first serial, iclass 4, count 0 2006.201.08:11:48.85#ibcon#enter sib2, iclass 4, count 0 2006.201.08:11:48.85#ibcon#flushed, iclass 4, count 0 2006.201.08:11:48.85#ibcon#about to write, iclass 4, count 0 2006.201.08:11:48.85#ibcon#wrote, iclass 4, count 0 2006.201.08:11:48.85#ibcon#about to read 3, iclass 4, count 0 2006.201.08:11:48.87#ibcon#read 3, iclass 4, count 0 2006.201.08:11:48.87#ibcon#about to read 4, iclass 4, count 0 2006.201.08:11:48.87#ibcon#read 4, iclass 4, count 0 2006.201.08:11:48.87#ibcon#about to read 5, iclass 4, count 0 2006.201.08:11:48.87#ibcon#read 5, iclass 4, count 0 2006.201.08:11:48.87#ibcon#about to read 6, iclass 4, count 0 2006.201.08:11:48.87#ibcon#read 6, iclass 4, count 0 2006.201.08:11:48.87#ibcon#end of sib2, iclass 4, count 0 2006.201.08:11:48.87#ibcon#*mode == 0, iclass 4, count 0 2006.201.08:11:48.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.08:11:48.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:11:48.87#ibcon#*before write, iclass 4, count 0 2006.201.08:11:48.87#ibcon#enter sib2, iclass 4, count 0 2006.201.08:11:48.87#ibcon#flushed, iclass 4, count 0 2006.201.08:11:48.87#ibcon#about to write, iclass 4, count 0 2006.201.08:11:48.87#ibcon#wrote, iclass 4, count 0 2006.201.08:11:48.87#ibcon#about to read 3, iclass 4, count 0 2006.201.08:11:48.91#ibcon#read 3, iclass 4, count 0 2006.201.08:11:48.91#ibcon#about to read 4, iclass 4, count 0 2006.201.08:11:48.91#ibcon#read 4, iclass 4, count 0 2006.201.08:11:48.91#ibcon#about to read 5, iclass 4, count 0 2006.201.08:11:48.91#ibcon#read 5, iclass 4, count 0 2006.201.08:11:48.91#ibcon#about to read 6, iclass 4, count 0 2006.201.08:11:48.91#ibcon#read 6, iclass 4, count 0 2006.201.08:11:48.91#ibcon#end of sib2, iclass 4, count 0 2006.201.08:11:48.91#ibcon#*after write, iclass 4, count 0 2006.201.08:11:48.91#ibcon#*before return 0, iclass 4, count 0 2006.201.08:11:48.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:48.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.08:11:48.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.08:11:48.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.08:11:48.91$vck44/vb=2,5 2006.201.08:11:48.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.08:11:48.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.08:11:48.91#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:48.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:48.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:48.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:48.97#ibcon#enter wrdev, iclass 6, count 2 2006.201.08:11:48.97#ibcon#first serial, iclass 6, count 2 2006.201.08:11:48.97#ibcon#enter sib2, iclass 6, count 2 2006.201.08:11:48.97#ibcon#flushed, iclass 6, count 2 2006.201.08:11:48.97#ibcon#about to write, iclass 6, count 2 2006.201.08:11:48.97#ibcon#wrote, iclass 6, count 2 2006.201.08:11:48.97#ibcon#about to read 3, iclass 6, count 2 2006.201.08:11:48.99#ibcon#read 3, iclass 6, count 2 2006.201.08:11:48.99#ibcon#about to read 4, iclass 6, count 2 2006.201.08:11:48.99#ibcon#read 4, iclass 6, count 2 2006.201.08:11:48.99#ibcon#about to read 5, iclass 6, count 2 2006.201.08:11:48.99#ibcon#read 5, iclass 6, count 2 2006.201.08:11:48.99#ibcon#about to read 6, iclass 6, count 2 2006.201.08:11:48.99#ibcon#read 6, iclass 6, count 2 2006.201.08:11:48.99#ibcon#end of sib2, iclass 6, count 2 2006.201.08:11:48.99#ibcon#*mode == 0, iclass 6, count 2 2006.201.08:11:48.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.08:11:48.99#ibcon#[27=AT02-05\r\n] 2006.201.08:11:48.99#ibcon#*before write, iclass 6, count 2 2006.201.08:11:48.99#ibcon#enter sib2, iclass 6, count 2 2006.201.08:11:48.99#ibcon#flushed, iclass 6, count 2 2006.201.08:11:48.99#ibcon#about to write, iclass 6, count 2 2006.201.08:11:48.99#ibcon#wrote, iclass 6, count 2 2006.201.08:11:48.99#ibcon#about to read 3, iclass 6, count 2 2006.201.08:11:49.02#ibcon#read 3, iclass 6, count 2 2006.201.08:11:49.02#ibcon#about to read 4, iclass 6, count 2 2006.201.08:11:49.02#ibcon#read 4, iclass 6, count 2 2006.201.08:11:49.02#ibcon#about to read 5, iclass 6, count 2 2006.201.08:11:49.02#ibcon#read 5, iclass 6, count 2 2006.201.08:11:49.02#ibcon#about to read 6, iclass 6, count 2 2006.201.08:11:49.02#ibcon#read 6, iclass 6, count 2 2006.201.08:11:49.02#ibcon#end of sib2, iclass 6, count 2 2006.201.08:11:49.02#ibcon#*after write, iclass 6, count 2 2006.201.08:11:49.02#ibcon#*before return 0, iclass 6, count 2 2006.201.08:11:49.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:49.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.08:11:49.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.08:11:49.02#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:49.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:49.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:49.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:49.14#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:11:49.14#ibcon#first serial, iclass 6, count 0 2006.201.08:11:49.14#ibcon#enter sib2, iclass 6, count 0 2006.201.08:11:49.14#ibcon#flushed, iclass 6, count 0 2006.201.08:11:49.14#ibcon#about to write, iclass 6, count 0 2006.201.08:11:49.14#ibcon#wrote, iclass 6, count 0 2006.201.08:11:49.14#ibcon#about to read 3, iclass 6, count 0 2006.201.08:11:49.16#ibcon#read 3, iclass 6, count 0 2006.201.08:11:49.16#ibcon#about to read 4, iclass 6, count 0 2006.201.08:11:49.16#ibcon#read 4, iclass 6, count 0 2006.201.08:11:49.16#ibcon#about to read 5, iclass 6, count 0 2006.201.08:11:49.16#ibcon#read 5, iclass 6, count 0 2006.201.08:11:49.16#ibcon#about to read 6, iclass 6, count 0 2006.201.08:11:49.16#ibcon#read 6, iclass 6, count 0 2006.201.08:11:49.16#ibcon#end of sib2, iclass 6, count 0 2006.201.08:11:49.16#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:11:49.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:11:49.16#ibcon#[27=USB\r\n] 2006.201.08:11:49.16#ibcon#*before write, iclass 6, count 0 2006.201.08:11:49.16#ibcon#enter sib2, iclass 6, count 0 2006.201.08:11:49.16#ibcon#flushed, iclass 6, count 0 2006.201.08:11:49.16#ibcon#about to write, iclass 6, count 0 2006.201.08:11:49.16#ibcon#wrote, iclass 6, count 0 2006.201.08:11:49.16#ibcon#about to read 3, iclass 6, count 0 2006.201.08:11:49.19#ibcon#read 3, iclass 6, count 0 2006.201.08:11:49.19#ibcon#about to read 4, iclass 6, count 0 2006.201.08:11:49.19#ibcon#read 4, iclass 6, count 0 2006.201.08:11:49.19#ibcon#about to read 5, iclass 6, count 0 2006.201.08:11:49.19#ibcon#read 5, iclass 6, count 0 2006.201.08:11:49.19#ibcon#about to read 6, iclass 6, count 0 2006.201.08:11:49.19#ibcon#read 6, iclass 6, count 0 2006.201.08:11:49.19#ibcon#end of sib2, iclass 6, count 0 2006.201.08:11:49.19#ibcon#*after write, iclass 6, count 0 2006.201.08:11:49.19#ibcon#*before return 0, iclass 6, count 0 2006.201.08:11:49.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:49.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.08:11:49.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:11:49.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:11:49.19$vck44/vblo=3,649.99 2006.201.08:11:49.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.08:11:49.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.08:11:49.19#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:49.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:49.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:49.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:49.19#ibcon#enter wrdev, iclass 10, count 0 2006.201.08:11:49.19#ibcon#first serial, iclass 10, count 0 2006.201.08:11:49.19#ibcon#enter sib2, iclass 10, count 0 2006.201.08:11:49.19#ibcon#flushed, iclass 10, count 0 2006.201.08:11:49.19#ibcon#about to write, iclass 10, count 0 2006.201.08:11:49.19#ibcon#wrote, iclass 10, count 0 2006.201.08:11:49.19#ibcon#about to read 3, iclass 10, count 0 2006.201.08:11:49.21#ibcon#read 3, iclass 10, count 0 2006.201.08:11:49.21#ibcon#about to read 4, iclass 10, count 0 2006.201.08:11:49.21#ibcon#read 4, iclass 10, count 0 2006.201.08:11:49.21#ibcon#about to read 5, iclass 10, count 0 2006.201.08:11:49.21#ibcon#read 5, iclass 10, count 0 2006.201.08:11:49.21#ibcon#about to read 6, iclass 10, count 0 2006.201.08:11:49.21#ibcon#read 6, iclass 10, count 0 2006.201.08:11:49.21#ibcon#end of sib2, iclass 10, count 0 2006.201.08:11:49.21#ibcon#*mode == 0, iclass 10, count 0 2006.201.08:11:49.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.08:11:49.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:11:49.21#ibcon#*before write, iclass 10, count 0 2006.201.08:11:49.21#ibcon#enter sib2, iclass 10, count 0 2006.201.08:11:49.21#ibcon#flushed, iclass 10, count 0 2006.201.08:11:49.21#ibcon#about to write, iclass 10, count 0 2006.201.08:11:49.21#ibcon#wrote, iclass 10, count 0 2006.201.08:11:49.21#ibcon#about to read 3, iclass 10, count 0 2006.201.08:11:49.26#ibcon#read 3, iclass 10, count 0 2006.201.08:11:49.26#ibcon#about to read 4, iclass 10, count 0 2006.201.08:11:49.26#ibcon#read 4, iclass 10, count 0 2006.201.08:11:49.26#ibcon#about to read 5, iclass 10, count 0 2006.201.08:11:49.26#ibcon#read 5, iclass 10, count 0 2006.201.08:11:49.26#ibcon#about to read 6, iclass 10, count 0 2006.201.08:11:49.26#ibcon#read 6, iclass 10, count 0 2006.201.08:11:49.26#ibcon#end of sib2, iclass 10, count 0 2006.201.08:11:49.26#ibcon#*after write, iclass 10, count 0 2006.201.08:11:49.26#ibcon#*before return 0, iclass 10, count 0 2006.201.08:11:49.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:49.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:11:49.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.08:11:49.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.08:11:49.26$vck44/vb=3,4 2006.201.08:11:49.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.08:11:49.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.08:11:49.26#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:49.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:49.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:49.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:49.31#ibcon#enter wrdev, iclass 12, count 2 2006.201.08:11:49.31#ibcon#first serial, iclass 12, count 2 2006.201.08:11:49.31#ibcon#enter sib2, iclass 12, count 2 2006.201.08:11:49.31#ibcon#flushed, iclass 12, count 2 2006.201.08:11:49.31#ibcon#about to write, iclass 12, count 2 2006.201.08:11:49.31#ibcon#wrote, iclass 12, count 2 2006.201.08:11:49.31#ibcon#about to read 3, iclass 12, count 2 2006.201.08:11:49.33#ibcon#read 3, iclass 12, count 2 2006.201.08:11:49.33#ibcon#about to read 4, iclass 12, count 2 2006.201.08:11:49.33#ibcon#read 4, iclass 12, count 2 2006.201.08:11:49.33#ibcon#about to read 5, iclass 12, count 2 2006.201.08:11:49.33#ibcon#read 5, iclass 12, count 2 2006.201.08:11:49.33#ibcon#about to read 6, iclass 12, count 2 2006.201.08:11:49.33#ibcon#read 6, iclass 12, count 2 2006.201.08:11:49.33#ibcon#end of sib2, iclass 12, count 2 2006.201.08:11:49.33#ibcon#*mode == 0, iclass 12, count 2 2006.201.08:11:49.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.08:11:49.33#ibcon#[27=AT03-04\r\n] 2006.201.08:11:49.33#ibcon#*before write, iclass 12, count 2 2006.201.08:11:49.33#ibcon#enter sib2, iclass 12, count 2 2006.201.08:11:49.33#ibcon#flushed, iclass 12, count 2 2006.201.08:11:49.33#ibcon#about to write, iclass 12, count 2 2006.201.08:11:49.33#ibcon#wrote, iclass 12, count 2 2006.201.08:11:49.33#ibcon#about to read 3, iclass 12, count 2 2006.201.08:11:49.36#ibcon#read 3, iclass 12, count 2 2006.201.08:11:49.36#ibcon#about to read 4, iclass 12, count 2 2006.201.08:11:49.36#ibcon#read 4, iclass 12, count 2 2006.201.08:11:49.36#ibcon#about to read 5, iclass 12, count 2 2006.201.08:11:49.36#ibcon#read 5, iclass 12, count 2 2006.201.08:11:49.36#ibcon#about to read 6, iclass 12, count 2 2006.201.08:11:49.36#ibcon#read 6, iclass 12, count 2 2006.201.08:11:49.36#ibcon#end of sib2, iclass 12, count 2 2006.201.08:11:49.36#ibcon#*after write, iclass 12, count 2 2006.201.08:11:49.36#ibcon#*before return 0, iclass 12, count 2 2006.201.08:11:49.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:49.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.08:11:49.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.08:11:49.36#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:49.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:49.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:49.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:49.48#ibcon#enter wrdev, iclass 12, count 0 2006.201.08:11:49.48#ibcon#first serial, iclass 12, count 0 2006.201.08:11:49.48#ibcon#enter sib2, iclass 12, count 0 2006.201.08:11:49.48#ibcon#flushed, iclass 12, count 0 2006.201.08:11:49.48#ibcon#about to write, iclass 12, count 0 2006.201.08:11:49.48#ibcon#wrote, iclass 12, count 0 2006.201.08:11:49.48#ibcon#about to read 3, iclass 12, count 0 2006.201.08:11:49.50#ibcon#read 3, iclass 12, count 0 2006.201.08:11:49.50#ibcon#about to read 4, iclass 12, count 0 2006.201.08:11:49.50#ibcon#read 4, iclass 12, count 0 2006.201.08:11:49.50#ibcon#about to read 5, iclass 12, count 0 2006.201.08:11:49.50#ibcon#read 5, iclass 12, count 0 2006.201.08:11:49.50#ibcon#about to read 6, iclass 12, count 0 2006.201.08:11:49.50#ibcon#read 6, iclass 12, count 0 2006.201.08:11:49.50#ibcon#end of sib2, iclass 12, count 0 2006.201.08:11:49.50#ibcon#*mode == 0, iclass 12, count 0 2006.201.08:11:49.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.08:11:49.50#ibcon#[27=USB\r\n] 2006.201.08:11:49.50#ibcon#*before write, iclass 12, count 0 2006.201.08:11:49.50#ibcon#enter sib2, iclass 12, count 0 2006.201.08:11:49.50#ibcon#flushed, iclass 12, count 0 2006.201.08:11:49.50#ibcon#about to write, iclass 12, count 0 2006.201.08:11:49.50#ibcon#wrote, iclass 12, count 0 2006.201.08:11:49.50#ibcon#about to read 3, iclass 12, count 0 2006.201.08:11:49.53#ibcon#read 3, iclass 12, count 0 2006.201.08:11:49.53#ibcon#about to read 4, iclass 12, count 0 2006.201.08:11:49.53#ibcon#read 4, iclass 12, count 0 2006.201.08:11:49.53#ibcon#about to read 5, iclass 12, count 0 2006.201.08:11:49.53#ibcon#read 5, iclass 12, count 0 2006.201.08:11:49.53#ibcon#about to read 6, iclass 12, count 0 2006.201.08:11:49.53#ibcon#read 6, iclass 12, count 0 2006.201.08:11:49.53#ibcon#end of sib2, iclass 12, count 0 2006.201.08:11:49.53#ibcon#*after write, iclass 12, count 0 2006.201.08:11:49.53#ibcon#*before return 0, iclass 12, count 0 2006.201.08:11:49.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:49.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.08:11:49.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.08:11:49.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.08:11:49.53$vck44/vblo=4,679.99 2006.201.08:11:49.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.08:11:49.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.08:11:49.53#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:49.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:49.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:49.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:49.53#ibcon#enter wrdev, iclass 14, count 0 2006.201.08:11:49.53#ibcon#first serial, iclass 14, count 0 2006.201.08:11:49.53#ibcon#enter sib2, iclass 14, count 0 2006.201.08:11:49.53#ibcon#flushed, iclass 14, count 0 2006.201.08:11:49.53#ibcon#about to write, iclass 14, count 0 2006.201.08:11:49.53#ibcon#wrote, iclass 14, count 0 2006.201.08:11:49.53#ibcon#about to read 3, iclass 14, count 0 2006.201.08:11:49.55#ibcon#read 3, iclass 14, count 0 2006.201.08:11:49.55#ibcon#about to read 4, iclass 14, count 0 2006.201.08:11:49.55#ibcon#read 4, iclass 14, count 0 2006.201.08:11:49.55#ibcon#about to read 5, iclass 14, count 0 2006.201.08:11:49.55#ibcon#read 5, iclass 14, count 0 2006.201.08:11:49.55#ibcon#about to read 6, iclass 14, count 0 2006.201.08:11:49.55#ibcon#read 6, iclass 14, count 0 2006.201.08:11:49.55#ibcon#end of sib2, iclass 14, count 0 2006.201.08:11:49.55#ibcon#*mode == 0, iclass 14, count 0 2006.201.08:11:49.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.08:11:49.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:11:49.55#ibcon#*before write, iclass 14, count 0 2006.201.08:11:49.55#ibcon#enter sib2, iclass 14, count 0 2006.201.08:11:49.55#ibcon#flushed, iclass 14, count 0 2006.201.08:11:49.55#ibcon#about to write, iclass 14, count 0 2006.201.08:11:49.55#ibcon#wrote, iclass 14, count 0 2006.201.08:11:49.55#ibcon#about to read 3, iclass 14, count 0 2006.201.08:11:49.59#ibcon#read 3, iclass 14, count 0 2006.201.08:11:49.59#ibcon#about to read 4, iclass 14, count 0 2006.201.08:11:49.59#ibcon#read 4, iclass 14, count 0 2006.201.08:11:49.59#ibcon#about to read 5, iclass 14, count 0 2006.201.08:11:49.59#ibcon#read 5, iclass 14, count 0 2006.201.08:11:49.59#ibcon#about to read 6, iclass 14, count 0 2006.201.08:11:49.59#ibcon#read 6, iclass 14, count 0 2006.201.08:11:49.59#ibcon#end of sib2, iclass 14, count 0 2006.201.08:11:49.59#ibcon#*after write, iclass 14, count 0 2006.201.08:11:49.59#ibcon#*before return 0, iclass 14, count 0 2006.201.08:11:49.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:49.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.08:11:49.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.08:11:49.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.08:11:49.59$vck44/vb=4,5 2006.201.08:11:49.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.08:11:49.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.08:11:49.59#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:49.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:49.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:49.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:49.65#ibcon#enter wrdev, iclass 16, count 2 2006.201.08:11:49.65#ibcon#first serial, iclass 16, count 2 2006.201.08:11:49.65#ibcon#enter sib2, iclass 16, count 2 2006.201.08:11:49.65#ibcon#flushed, iclass 16, count 2 2006.201.08:11:49.65#ibcon#about to write, iclass 16, count 2 2006.201.08:11:49.65#ibcon#wrote, iclass 16, count 2 2006.201.08:11:49.65#ibcon#about to read 3, iclass 16, count 2 2006.201.08:11:49.67#ibcon#read 3, iclass 16, count 2 2006.201.08:11:49.67#ibcon#about to read 4, iclass 16, count 2 2006.201.08:11:49.67#ibcon#read 4, iclass 16, count 2 2006.201.08:11:49.67#ibcon#about to read 5, iclass 16, count 2 2006.201.08:11:49.67#ibcon#read 5, iclass 16, count 2 2006.201.08:11:49.67#ibcon#about to read 6, iclass 16, count 2 2006.201.08:11:49.67#ibcon#read 6, iclass 16, count 2 2006.201.08:11:49.67#ibcon#end of sib2, iclass 16, count 2 2006.201.08:11:49.67#ibcon#*mode == 0, iclass 16, count 2 2006.201.08:11:49.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.08:11:49.67#ibcon#[27=AT04-05\r\n] 2006.201.08:11:49.67#ibcon#*before write, iclass 16, count 2 2006.201.08:11:49.67#ibcon#enter sib2, iclass 16, count 2 2006.201.08:11:49.67#ibcon#flushed, iclass 16, count 2 2006.201.08:11:49.67#ibcon#about to write, iclass 16, count 2 2006.201.08:11:49.67#ibcon#wrote, iclass 16, count 2 2006.201.08:11:49.67#ibcon#about to read 3, iclass 16, count 2 2006.201.08:11:49.70#ibcon#read 3, iclass 16, count 2 2006.201.08:11:49.70#ibcon#about to read 4, iclass 16, count 2 2006.201.08:11:49.70#ibcon#read 4, iclass 16, count 2 2006.201.08:11:49.70#ibcon#about to read 5, iclass 16, count 2 2006.201.08:11:49.70#ibcon#read 5, iclass 16, count 2 2006.201.08:11:49.70#ibcon#about to read 6, iclass 16, count 2 2006.201.08:11:49.70#ibcon#read 6, iclass 16, count 2 2006.201.08:11:49.70#ibcon#end of sib2, iclass 16, count 2 2006.201.08:11:49.70#ibcon#*after write, iclass 16, count 2 2006.201.08:11:49.70#ibcon#*before return 0, iclass 16, count 2 2006.201.08:11:49.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:49.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.08:11:49.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.08:11:49.70#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:49.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:49.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:49.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:49.82#ibcon#enter wrdev, iclass 16, count 0 2006.201.08:11:49.82#ibcon#first serial, iclass 16, count 0 2006.201.08:11:49.82#ibcon#enter sib2, iclass 16, count 0 2006.201.08:11:49.82#ibcon#flushed, iclass 16, count 0 2006.201.08:11:49.82#ibcon#about to write, iclass 16, count 0 2006.201.08:11:49.82#ibcon#wrote, iclass 16, count 0 2006.201.08:11:49.82#ibcon#about to read 3, iclass 16, count 0 2006.201.08:11:49.84#ibcon#read 3, iclass 16, count 0 2006.201.08:11:49.84#ibcon#about to read 4, iclass 16, count 0 2006.201.08:11:49.84#ibcon#read 4, iclass 16, count 0 2006.201.08:11:49.84#ibcon#about to read 5, iclass 16, count 0 2006.201.08:11:49.84#ibcon#read 5, iclass 16, count 0 2006.201.08:11:49.84#ibcon#about to read 6, iclass 16, count 0 2006.201.08:11:49.84#ibcon#read 6, iclass 16, count 0 2006.201.08:11:49.84#ibcon#end of sib2, iclass 16, count 0 2006.201.08:11:49.84#ibcon#*mode == 0, iclass 16, count 0 2006.201.08:11:49.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.08:11:49.84#ibcon#[27=USB\r\n] 2006.201.08:11:49.84#ibcon#*before write, iclass 16, count 0 2006.201.08:11:49.84#ibcon#enter sib2, iclass 16, count 0 2006.201.08:11:49.84#ibcon#flushed, iclass 16, count 0 2006.201.08:11:49.84#ibcon#about to write, iclass 16, count 0 2006.201.08:11:49.84#ibcon#wrote, iclass 16, count 0 2006.201.08:11:49.84#ibcon#about to read 3, iclass 16, count 0 2006.201.08:11:49.87#ibcon#read 3, iclass 16, count 0 2006.201.08:11:49.87#ibcon#about to read 4, iclass 16, count 0 2006.201.08:11:49.87#ibcon#read 4, iclass 16, count 0 2006.201.08:11:49.87#ibcon#about to read 5, iclass 16, count 0 2006.201.08:11:49.87#ibcon#read 5, iclass 16, count 0 2006.201.08:11:49.87#ibcon#about to read 6, iclass 16, count 0 2006.201.08:11:49.87#ibcon#read 6, iclass 16, count 0 2006.201.08:11:49.87#ibcon#end of sib2, iclass 16, count 0 2006.201.08:11:49.87#ibcon#*after write, iclass 16, count 0 2006.201.08:11:49.87#ibcon#*before return 0, iclass 16, count 0 2006.201.08:11:49.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:49.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.08:11:49.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.08:11:49.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.08:11:49.87$vck44/vblo=5,709.99 2006.201.08:11:49.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.08:11:49.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.08:11:49.87#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:49.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:49.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:49.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:49.87#ibcon#enter wrdev, iclass 18, count 0 2006.201.08:11:49.87#ibcon#first serial, iclass 18, count 0 2006.201.08:11:49.87#ibcon#enter sib2, iclass 18, count 0 2006.201.08:11:49.87#ibcon#flushed, iclass 18, count 0 2006.201.08:11:49.87#ibcon#about to write, iclass 18, count 0 2006.201.08:11:49.87#ibcon#wrote, iclass 18, count 0 2006.201.08:11:49.87#ibcon#about to read 3, iclass 18, count 0 2006.201.08:11:49.89#ibcon#read 3, iclass 18, count 0 2006.201.08:11:49.89#ibcon#about to read 4, iclass 18, count 0 2006.201.08:11:49.89#ibcon#read 4, iclass 18, count 0 2006.201.08:11:49.89#ibcon#about to read 5, iclass 18, count 0 2006.201.08:11:49.89#ibcon#read 5, iclass 18, count 0 2006.201.08:11:49.89#ibcon#about to read 6, iclass 18, count 0 2006.201.08:11:49.89#ibcon#read 6, iclass 18, count 0 2006.201.08:11:49.89#ibcon#end of sib2, iclass 18, count 0 2006.201.08:11:49.89#ibcon#*mode == 0, iclass 18, count 0 2006.201.08:11:49.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.08:11:49.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:11:49.89#ibcon#*before write, iclass 18, count 0 2006.201.08:11:49.89#ibcon#enter sib2, iclass 18, count 0 2006.201.08:11:49.89#ibcon#flushed, iclass 18, count 0 2006.201.08:11:49.89#ibcon#about to write, iclass 18, count 0 2006.201.08:11:49.89#ibcon#wrote, iclass 18, count 0 2006.201.08:11:49.89#ibcon#about to read 3, iclass 18, count 0 2006.201.08:11:49.93#ibcon#read 3, iclass 18, count 0 2006.201.08:11:49.93#ibcon#about to read 4, iclass 18, count 0 2006.201.08:11:49.93#ibcon#read 4, iclass 18, count 0 2006.201.08:11:49.93#ibcon#about to read 5, iclass 18, count 0 2006.201.08:11:49.93#ibcon#read 5, iclass 18, count 0 2006.201.08:11:49.93#ibcon#about to read 6, iclass 18, count 0 2006.201.08:11:49.93#ibcon#read 6, iclass 18, count 0 2006.201.08:11:49.93#ibcon#end of sib2, iclass 18, count 0 2006.201.08:11:49.93#ibcon#*after write, iclass 18, count 0 2006.201.08:11:49.93#ibcon#*before return 0, iclass 18, count 0 2006.201.08:11:49.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:49.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:11:49.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.08:11:49.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.08:11:49.93$vck44/vb=5,4 2006.201.08:11:49.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.08:11:49.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.08:11:49.93#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:49.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:49.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:49.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:49.99#ibcon#enter wrdev, iclass 20, count 2 2006.201.08:11:49.99#ibcon#first serial, iclass 20, count 2 2006.201.08:11:49.99#ibcon#enter sib2, iclass 20, count 2 2006.201.08:11:49.99#ibcon#flushed, iclass 20, count 2 2006.201.08:11:49.99#ibcon#about to write, iclass 20, count 2 2006.201.08:11:49.99#ibcon#wrote, iclass 20, count 2 2006.201.08:11:49.99#ibcon#about to read 3, iclass 20, count 2 2006.201.08:11:50.01#ibcon#read 3, iclass 20, count 2 2006.201.08:11:50.01#ibcon#about to read 4, iclass 20, count 2 2006.201.08:11:50.01#ibcon#read 4, iclass 20, count 2 2006.201.08:11:50.01#ibcon#about to read 5, iclass 20, count 2 2006.201.08:11:50.01#ibcon#read 5, iclass 20, count 2 2006.201.08:11:50.01#ibcon#about to read 6, iclass 20, count 2 2006.201.08:11:50.01#ibcon#read 6, iclass 20, count 2 2006.201.08:11:50.01#ibcon#end of sib2, iclass 20, count 2 2006.201.08:11:50.01#ibcon#*mode == 0, iclass 20, count 2 2006.201.08:11:50.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.08:11:50.01#ibcon#[27=AT05-04\r\n] 2006.201.08:11:50.01#ibcon#*before write, iclass 20, count 2 2006.201.08:11:50.01#ibcon#enter sib2, iclass 20, count 2 2006.201.08:11:50.01#ibcon#flushed, iclass 20, count 2 2006.201.08:11:50.01#ibcon#about to write, iclass 20, count 2 2006.201.08:11:50.01#ibcon#wrote, iclass 20, count 2 2006.201.08:11:50.01#ibcon#about to read 3, iclass 20, count 2 2006.201.08:11:50.04#ibcon#read 3, iclass 20, count 2 2006.201.08:11:50.04#ibcon#about to read 4, iclass 20, count 2 2006.201.08:11:50.04#ibcon#read 4, iclass 20, count 2 2006.201.08:11:50.04#ibcon#about to read 5, iclass 20, count 2 2006.201.08:11:50.04#ibcon#read 5, iclass 20, count 2 2006.201.08:11:50.04#ibcon#about to read 6, iclass 20, count 2 2006.201.08:11:50.04#ibcon#read 6, iclass 20, count 2 2006.201.08:11:50.04#ibcon#end of sib2, iclass 20, count 2 2006.201.08:11:50.04#ibcon#*after write, iclass 20, count 2 2006.201.08:11:50.04#ibcon#*before return 0, iclass 20, count 2 2006.201.08:11:50.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:50.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.08:11:50.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.08:11:50.04#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:50.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:50.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:50.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:50.16#ibcon#enter wrdev, iclass 20, count 0 2006.201.08:11:50.16#ibcon#first serial, iclass 20, count 0 2006.201.08:11:50.16#ibcon#enter sib2, iclass 20, count 0 2006.201.08:11:50.16#ibcon#flushed, iclass 20, count 0 2006.201.08:11:50.16#ibcon#about to write, iclass 20, count 0 2006.201.08:11:50.16#ibcon#wrote, iclass 20, count 0 2006.201.08:11:50.16#ibcon#about to read 3, iclass 20, count 0 2006.201.08:11:50.18#ibcon#read 3, iclass 20, count 0 2006.201.08:11:50.18#ibcon#about to read 4, iclass 20, count 0 2006.201.08:11:50.18#ibcon#read 4, iclass 20, count 0 2006.201.08:11:50.18#ibcon#about to read 5, iclass 20, count 0 2006.201.08:11:50.18#ibcon#read 5, iclass 20, count 0 2006.201.08:11:50.18#ibcon#about to read 6, iclass 20, count 0 2006.201.08:11:50.18#ibcon#read 6, iclass 20, count 0 2006.201.08:11:50.18#ibcon#end of sib2, iclass 20, count 0 2006.201.08:11:50.18#ibcon#*mode == 0, iclass 20, count 0 2006.201.08:11:50.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.08:11:50.18#ibcon#[27=USB\r\n] 2006.201.08:11:50.18#ibcon#*before write, iclass 20, count 0 2006.201.08:11:50.18#ibcon#enter sib2, iclass 20, count 0 2006.201.08:11:50.18#ibcon#flushed, iclass 20, count 0 2006.201.08:11:50.18#ibcon#about to write, iclass 20, count 0 2006.201.08:11:50.18#ibcon#wrote, iclass 20, count 0 2006.201.08:11:50.18#ibcon#about to read 3, iclass 20, count 0 2006.201.08:11:50.21#ibcon#read 3, iclass 20, count 0 2006.201.08:11:50.21#ibcon#about to read 4, iclass 20, count 0 2006.201.08:11:50.21#ibcon#read 4, iclass 20, count 0 2006.201.08:11:50.21#ibcon#about to read 5, iclass 20, count 0 2006.201.08:11:50.21#ibcon#read 5, iclass 20, count 0 2006.201.08:11:50.21#ibcon#about to read 6, iclass 20, count 0 2006.201.08:11:50.21#ibcon#read 6, iclass 20, count 0 2006.201.08:11:50.21#ibcon#end of sib2, iclass 20, count 0 2006.201.08:11:50.21#ibcon#*after write, iclass 20, count 0 2006.201.08:11:50.21#ibcon#*before return 0, iclass 20, count 0 2006.201.08:11:50.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:50.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.08:11:50.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.08:11:50.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.08:11:50.21$vck44/vblo=6,719.99 2006.201.08:11:50.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.08:11:50.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.08:11:50.21#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:50.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:50.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:50.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:50.21#ibcon#enter wrdev, iclass 22, count 0 2006.201.08:11:50.21#ibcon#first serial, iclass 22, count 0 2006.201.08:11:50.21#ibcon#enter sib2, iclass 22, count 0 2006.201.08:11:50.21#ibcon#flushed, iclass 22, count 0 2006.201.08:11:50.21#ibcon#about to write, iclass 22, count 0 2006.201.08:11:50.21#ibcon#wrote, iclass 22, count 0 2006.201.08:11:50.21#ibcon#about to read 3, iclass 22, count 0 2006.201.08:11:50.23#ibcon#read 3, iclass 22, count 0 2006.201.08:11:50.23#ibcon#about to read 4, iclass 22, count 0 2006.201.08:11:50.23#ibcon#read 4, iclass 22, count 0 2006.201.08:11:50.23#ibcon#about to read 5, iclass 22, count 0 2006.201.08:11:50.23#ibcon#read 5, iclass 22, count 0 2006.201.08:11:50.23#ibcon#about to read 6, iclass 22, count 0 2006.201.08:11:50.23#ibcon#read 6, iclass 22, count 0 2006.201.08:11:50.23#ibcon#end of sib2, iclass 22, count 0 2006.201.08:11:50.23#ibcon#*mode == 0, iclass 22, count 0 2006.201.08:11:50.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.08:11:50.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:11:50.23#ibcon#*before write, iclass 22, count 0 2006.201.08:11:50.23#ibcon#enter sib2, iclass 22, count 0 2006.201.08:11:50.23#ibcon#flushed, iclass 22, count 0 2006.201.08:11:50.23#ibcon#about to write, iclass 22, count 0 2006.201.08:11:50.23#ibcon#wrote, iclass 22, count 0 2006.201.08:11:50.23#ibcon#about to read 3, iclass 22, count 0 2006.201.08:11:50.27#ibcon#read 3, iclass 22, count 0 2006.201.08:11:50.27#ibcon#about to read 4, iclass 22, count 0 2006.201.08:11:50.27#ibcon#read 4, iclass 22, count 0 2006.201.08:11:50.27#ibcon#about to read 5, iclass 22, count 0 2006.201.08:11:50.27#ibcon#read 5, iclass 22, count 0 2006.201.08:11:50.27#ibcon#about to read 6, iclass 22, count 0 2006.201.08:11:50.27#ibcon#read 6, iclass 22, count 0 2006.201.08:11:50.27#ibcon#end of sib2, iclass 22, count 0 2006.201.08:11:50.27#ibcon#*after write, iclass 22, count 0 2006.201.08:11:50.27#ibcon#*before return 0, iclass 22, count 0 2006.201.08:11:50.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:50.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.08:11:50.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.08:11:50.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.08:11:50.27$vck44/vb=6,4 2006.201.08:11:50.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.08:11:50.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.08:11:50.27#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:50.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:50.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:50.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:50.33#ibcon#enter wrdev, iclass 24, count 2 2006.201.08:11:50.33#ibcon#first serial, iclass 24, count 2 2006.201.08:11:50.33#ibcon#enter sib2, iclass 24, count 2 2006.201.08:11:50.33#ibcon#flushed, iclass 24, count 2 2006.201.08:11:50.33#ibcon#about to write, iclass 24, count 2 2006.201.08:11:50.33#ibcon#wrote, iclass 24, count 2 2006.201.08:11:50.33#ibcon#about to read 3, iclass 24, count 2 2006.201.08:11:50.35#ibcon#read 3, iclass 24, count 2 2006.201.08:11:50.35#ibcon#about to read 4, iclass 24, count 2 2006.201.08:11:50.35#ibcon#read 4, iclass 24, count 2 2006.201.08:11:50.35#ibcon#about to read 5, iclass 24, count 2 2006.201.08:11:50.35#ibcon#read 5, iclass 24, count 2 2006.201.08:11:50.35#ibcon#about to read 6, iclass 24, count 2 2006.201.08:11:50.35#ibcon#read 6, iclass 24, count 2 2006.201.08:11:50.35#ibcon#end of sib2, iclass 24, count 2 2006.201.08:11:50.35#ibcon#*mode == 0, iclass 24, count 2 2006.201.08:11:50.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.08:11:50.35#ibcon#[27=AT06-04\r\n] 2006.201.08:11:50.35#ibcon#*before write, iclass 24, count 2 2006.201.08:11:50.35#ibcon#enter sib2, iclass 24, count 2 2006.201.08:11:50.35#ibcon#flushed, iclass 24, count 2 2006.201.08:11:50.35#ibcon#about to write, iclass 24, count 2 2006.201.08:11:50.35#ibcon#wrote, iclass 24, count 2 2006.201.08:11:50.35#ibcon#about to read 3, iclass 24, count 2 2006.201.08:11:50.38#ibcon#read 3, iclass 24, count 2 2006.201.08:11:50.38#ibcon#about to read 4, iclass 24, count 2 2006.201.08:11:50.38#ibcon#read 4, iclass 24, count 2 2006.201.08:11:50.38#ibcon#about to read 5, iclass 24, count 2 2006.201.08:11:50.38#ibcon#read 5, iclass 24, count 2 2006.201.08:11:50.38#ibcon#about to read 6, iclass 24, count 2 2006.201.08:11:50.38#ibcon#read 6, iclass 24, count 2 2006.201.08:11:50.38#ibcon#end of sib2, iclass 24, count 2 2006.201.08:11:50.38#ibcon#*after write, iclass 24, count 2 2006.201.08:11:50.38#ibcon#*before return 0, iclass 24, count 2 2006.201.08:11:50.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:50.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.08:11:50.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.08:11:50.38#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:50.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:50.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:50.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:50.50#ibcon#enter wrdev, iclass 24, count 0 2006.201.08:11:50.50#ibcon#first serial, iclass 24, count 0 2006.201.08:11:50.50#ibcon#enter sib2, iclass 24, count 0 2006.201.08:11:50.50#ibcon#flushed, iclass 24, count 0 2006.201.08:11:50.50#ibcon#about to write, iclass 24, count 0 2006.201.08:11:50.50#ibcon#wrote, iclass 24, count 0 2006.201.08:11:50.50#ibcon#about to read 3, iclass 24, count 0 2006.201.08:11:50.52#ibcon#read 3, iclass 24, count 0 2006.201.08:11:50.52#ibcon#about to read 4, iclass 24, count 0 2006.201.08:11:50.52#ibcon#read 4, iclass 24, count 0 2006.201.08:11:50.52#ibcon#about to read 5, iclass 24, count 0 2006.201.08:11:50.52#ibcon#read 5, iclass 24, count 0 2006.201.08:11:50.52#ibcon#about to read 6, iclass 24, count 0 2006.201.08:11:50.52#ibcon#read 6, iclass 24, count 0 2006.201.08:11:50.52#ibcon#end of sib2, iclass 24, count 0 2006.201.08:11:50.52#ibcon#*mode == 0, iclass 24, count 0 2006.201.08:11:50.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.08:11:50.52#ibcon#[27=USB\r\n] 2006.201.08:11:50.52#ibcon#*before write, iclass 24, count 0 2006.201.08:11:50.52#ibcon#enter sib2, iclass 24, count 0 2006.201.08:11:50.52#ibcon#flushed, iclass 24, count 0 2006.201.08:11:50.52#ibcon#about to write, iclass 24, count 0 2006.201.08:11:50.52#ibcon#wrote, iclass 24, count 0 2006.201.08:11:50.52#ibcon#about to read 3, iclass 24, count 0 2006.201.08:11:50.55#ibcon#read 3, iclass 24, count 0 2006.201.08:11:50.55#ibcon#about to read 4, iclass 24, count 0 2006.201.08:11:50.55#ibcon#read 4, iclass 24, count 0 2006.201.08:11:50.55#ibcon#about to read 5, iclass 24, count 0 2006.201.08:11:50.55#ibcon#read 5, iclass 24, count 0 2006.201.08:11:50.55#ibcon#about to read 6, iclass 24, count 0 2006.201.08:11:50.55#ibcon#read 6, iclass 24, count 0 2006.201.08:11:50.55#ibcon#end of sib2, iclass 24, count 0 2006.201.08:11:50.55#ibcon#*after write, iclass 24, count 0 2006.201.08:11:50.55#ibcon#*before return 0, iclass 24, count 0 2006.201.08:11:50.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:50.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.08:11:50.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.08:11:50.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.08:11:50.55$vck44/vblo=7,734.99 2006.201.08:11:50.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.08:11:50.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.08:11:50.55#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:50.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:50.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:50.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:50.55#ibcon#enter wrdev, iclass 26, count 0 2006.201.08:11:50.55#ibcon#first serial, iclass 26, count 0 2006.201.08:11:50.55#ibcon#enter sib2, iclass 26, count 0 2006.201.08:11:50.55#ibcon#flushed, iclass 26, count 0 2006.201.08:11:50.55#ibcon#about to write, iclass 26, count 0 2006.201.08:11:50.55#ibcon#wrote, iclass 26, count 0 2006.201.08:11:50.55#ibcon#about to read 3, iclass 26, count 0 2006.201.08:11:50.57#ibcon#read 3, iclass 26, count 0 2006.201.08:11:50.57#ibcon#about to read 4, iclass 26, count 0 2006.201.08:11:50.57#ibcon#read 4, iclass 26, count 0 2006.201.08:11:50.57#ibcon#about to read 5, iclass 26, count 0 2006.201.08:11:50.57#ibcon#read 5, iclass 26, count 0 2006.201.08:11:50.57#ibcon#about to read 6, iclass 26, count 0 2006.201.08:11:50.57#ibcon#read 6, iclass 26, count 0 2006.201.08:11:50.57#ibcon#end of sib2, iclass 26, count 0 2006.201.08:11:50.57#ibcon#*mode == 0, iclass 26, count 0 2006.201.08:11:50.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.08:11:50.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:11:50.57#ibcon#*before write, iclass 26, count 0 2006.201.08:11:50.57#ibcon#enter sib2, iclass 26, count 0 2006.201.08:11:50.57#ibcon#flushed, iclass 26, count 0 2006.201.08:11:50.57#ibcon#about to write, iclass 26, count 0 2006.201.08:11:50.57#ibcon#wrote, iclass 26, count 0 2006.201.08:11:50.57#ibcon#about to read 3, iclass 26, count 0 2006.201.08:11:50.61#ibcon#read 3, iclass 26, count 0 2006.201.08:11:50.61#ibcon#about to read 4, iclass 26, count 0 2006.201.08:11:50.61#ibcon#read 4, iclass 26, count 0 2006.201.08:11:50.61#ibcon#about to read 5, iclass 26, count 0 2006.201.08:11:50.61#ibcon#read 5, iclass 26, count 0 2006.201.08:11:50.61#ibcon#about to read 6, iclass 26, count 0 2006.201.08:11:50.61#ibcon#read 6, iclass 26, count 0 2006.201.08:11:50.61#ibcon#end of sib2, iclass 26, count 0 2006.201.08:11:50.61#ibcon#*after write, iclass 26, count 0 2006.201.08:11:50.61#ibcon#*before return 0, iclass 26, count 0 2006.201.08:11:50.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:50.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.08:11:50.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.08:11:50.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.08:11:50.61$vck44/vb=7,4 2006.201.08:11:50.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.08:11:50.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.08:11:50.61#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:50.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:50.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:50.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:50.67#ibcon#enter wrdev, iclass 28, count 2 2006.201.08:11:50.67#ibcon#first serial, iclass 28, count 2 2006.201.08:11:50.67#ibcon#enter sib2, iclass 28, count 2 2006.201.08:11:50.67#ibcon#flushed, iclass 28, count 2 2006.201.08:11:50.67#ibcon#about to write, iclass 28, count 2 2006.201.08:11:50.67#ibcon#wrote, iclass 28, count 2 2006.201.08:11:50.67#ibcon#about to read 3, iclass 28, count 2 2006.201.08:11:50.69#ibcon#read 3, iclass 28, count 2 2006.201.08:11:50.69#ibcon#about to read 4, iclass 28, count 2 2006.201.08:11:50.69#ibcon#read 4, iclass 28, count 2 2006.201.08:11:50.69#ibcon#about to read 5, iclass 28, count 2 2006.201.08:11:50.69#ibcon#read 5, iclass 28, count 2 2006.201.08:11:50.69#ibcon#about to read 6, iclass 28, count 2 2006.201.08:11:50.69#ibcon#read 6, iclass 28, count 2 2006.201.08:11:50.69#ibcon#end of sib2, iclass 28, count 2 2006.201.08:11:50.69#ibcon#*mode == 0, iclass 28, count 2 2006.201.08:11:50.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.08:11:50.69#ibcon#[27=AT07-04\r\n] 2006.201.08:11:50.69#ibcon#*before write, iclass 28, count 2 2006.201.08:11:50.69#ibcon#enter sib2, iclass 28, count 2 2006.201.08:11:50.69#ibcon#flushed, iclass 28, count 2 2006.201.08:11:50.69#ibcon#about to write, iclass 28, count 2 2006.201.08:11:50.69#ibcon#wrote, iclass 28, count 2 2006.201.08:11:50.69#ibcon#about to read 3, iclass 28, count 2 2006.201.08:11:50.72#ibcon#read 3, iclass 28, count 2 2006.201.08:11:50.72#ibcon#about to read 4, iclass 28, count 2 2006.201.08:11:50.72#ibcon#read 4, iclass 28, count 2 2006.201.08:11:50.72#ibcon#about to read 5, iclass 28, count 2 2006.201.08:11:50.72#ibcon#read 5, iclass 28, count 2 2006.201.08:11:50.72#ibcon#about to read 6, iclass 28, count 2 2006.201.08:11:50.72#ibcon#read 6, iclass 28, count 2 2006.201.08:11:50.72#ibcon#end of sib2, iclass 28, count 2 2006.201.08:11:50.72#ibcon#*after write, iclass 28, count 2 2006.201.08:11:50.72#ibcon#*before return 0, iclass 28, count 2 2006.201.08:11:50.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:50.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.08:11:50.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.08:11:50.72#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:50.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:50.84#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:50.84#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:50.84#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:11:50.84#ibcon#first serial, iclass 28, count 0 2006.201.08:11:50.84#ibcon#enter sib2, iclass 28, count 0 2006.201.08:11:50.84#ibcon#flushed, iclass 28, count 0 2006.201.08:11:50.84#ibcon#about to write, iclass 28, count 0 2006.201.08:11:50.84#ibcon#wrote, iclass 28, count 0 2006.201.08:11:50.84#ibcon#about to read 3, iclass 28, count 0 2006.201.08:11:50.86#ibcon#read 3, iclass 28, count 0 2006.201.08:11:50.86#ibcon#about to read 4, iclass 28, count 0 2006.201.08:11:50.86#ibcon#read 4, iclass 28, count 0 2006.201.08:11:50.86#ibcon#about to read 5, iclass 28, count 0 2006.201.08:11:50.86#ibcon#read 5, iclass 28, count 0 2006.201.08:11:50.86#ibcon#about to read 6, iclass 28, count 0 2006.201.08:11:50.86#ibcon#read 6, iclass 28, count 0 2006.201.08:11:50.86#ibcon#end of sib2, iclass 28, count 0 2006.201.08:11:50.86#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:11:50.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:11:50.86#ibcon#[27=USB\r\n] 2006.201.08:11:50.86#ibcon#*before write, iclass 28, count 0 2006.201.08:11:50.86#ibcon#enter sib2, iclass 28, count 0 2006.201.08:11:50.86#ibcon#flushed, iclass 28, count 0 2006.201.08:11:50.86#ibcon#about to write, iclass 28, count 0 2006.201.08:11:50.86#ibcon#wrote, iclass 28, count 0 2006.201.08:11:50.86#ibcon#about to read 3, iclass 28, count 0 2006.201.08:11:50.89#ibcon#read 3, iclass 28, count 0 2006.201.08:11:50.89#ibcon#about to read 4, iclass 28, count 0 2006.201.08:11:50.89#ibcon#read 4, iclass 28, count 0 2006.201.08:11:50.89#ibcon#about to read 5, iclass 28, count 0 2006.201.08:11:50.89#ibcon#read 5, iclass 28, count 0 2006.201.08:11:50.89#ibcon#about to read 6, iclass 28, count 0 2006.201.08:11:50.89#ibcon#read 6, iclass 28, count 0 2006.201.08:11:50.89#ibcon#end of sib2, iclass 28, count 0 2006.201.08:11:50.89#ibcon#*after write, iclass 28, count 0 2006.201.08:11:50.89#ibcon#*before return 0, iclass 28, count 0 2006.201.08:11:50.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:50.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.08:11:50.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:11:50.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:11:50.89$vck44/vblo=8,744.99 2006.201.08:11:50.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.08:11:50.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.08:11:50.89#ibcon#ireg 17 cls_cnt 0 2006.201.08:11:50.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:50.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:50.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:50.89#ibcon#enter wrdev, iclass 30, count 0 2006.201.08:11:50.89#ibcon#first serial, iclass 30, count 0 2006.201.08:11:50.89#ibcon#enter sib2, iclass 30, count 0 2006.201.08:11:50.89#ibcon#flushed, iclass 30, count 0 2006.201.08:11:50.89#ibcon#about to write, iclass 30, count 0 2006.201.08:11:50.89#ibcon#wrote, iclass 30, count 0 2006.201.08:11:50.89#ibcon#about to read 3, iclass 30, count 0 2006.201.08:11:50.91#ibcon#read 3, iclass 30, count 0 2006.201.08:11:50.91#ibcon#about to read 4, iclass 30, count 0 2006.201.08:11:50.91#ibcon#read 4, iclass 30, count 0 2006.201.08:11:50.91#ibcon#about to read 5, iclass 30, count 0 2006.201.08:11:50.91#ibcon#read 5, iclass 30, count 0 2006.201.08:11:50.91#ibcon#about to read 6, iclass 30, count 0 2006.201.08:11:50.91#ibcon#read 6, iclass 30, count 0 2006.201.08:11:50.91#ibcon#end of sib2, iclass 30, count 0 2006.201.08:11:50.91#ibcon#*mode == 0, iclass 30, count 0 2006.201.08:11:50.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.08:11:50.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:11:50.91#ibcon#*before write, iclass 30, count 0 2006.201.08:11:50.91#ibcon#enter sib2, iclass 30, count 0 2006.201.08:11:50.91#ibcon#flushed, iclass 30, count 0 2006.201.08:11:50.91#ibcon#about to write, iclass 30, count 0 2006.201.08:11:50.91#ibcon#wrote, iclass 30, count 0 2006.201.08:11:50.91#ibcon#about to read 3, iclass 30, count 0 2006.201.08:11:50.95#ibcon#read 3, iclass 30, count 0 2006.201.08:11:50.95#ibcon#about to read 4, iclass 30, count 0 2006.201.08:11:50.95#ibcon#read 4, iclass 30, count 0 2006.201.08:11:50.95#ibcon#about to read 5, iclass 30, count 0 2006.201.08:11:50.95#ibcon#read 5, iclass 30, count 0 2006.201.08:11:50.95#ibcon#about to read 6, iclass 30, count 0 2006.201.08:11:50.95#ibcon#read 6, iclass 30, count 0 2006.201.08:11:50.95#ibcon#end of sib2, iclass 30, count 0 2006.201.08:11:50.95#ibcon#*after write, iclass 30, count 0 2006.201.08:11:50.95#ibcon#*before return 0, iclass 30, count 0 2006.201.08:11:50.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:50.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:11:50.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.08:11:50.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.08:11:50.95$vck44/vb=8,4 2006.201.08:11:50.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.08:11:50.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.08:11:50.95#ibcon#ireg 11 cls_cnt 2 2006.201.08:11:50.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:51.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:51.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:51.01#ibcon#enter wrdev, iclass 32, count 2 2006.201.08:11:51.01#ibcon#first serial, iclass 32, count 2 2006.201.08:11:51.01#ibcon#enter sib2, iclass 32, count 2 2006.201.08:11:51.01#ibcon#flushed, iclass 32, count 2 2006.201.08:11:51.01#ibcon#about to write, iclass 32, count 2 2006.201.08:11:51.01#ibcon#wrote, iclass 32, count 2 2006.201.08:11:51.01#ibcon#about to read 3, iclass 32, count 2 2006.201.08:11:51.03#ibcon#read 3, iclass 32, count 2 2006.201.08:11:51.03#ibcon#about to read 4, iclass 32, count 2 2006.201.08:11:51.03#ibcon#read 4, iclass 32, count 2 2006.201.08:11:51.03#ibcon#about to read 5, iclass 32, count 2 2006.201.08:11:51.03#ibcon#read 5, iclass 32, count 2 2006.201.08:11:51.03#ibcon#about to read 6, iclass 32, count 2 2006.201.08:11:51.03#ibcon#read 6, iclass 32, count 2 2006.201.08:11:51.03#ibcon#end of sib2, iclass 32, count 2 2006.201.08:11:51.03#ibcon#*mode == 0, iclass 32, count 2 2006.201.08:11:51.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.08:11:51.03#ibcon#[27=AT08-04\r\n] 2006.201.08:11:51.03#ibcon#*before write, iclass 32, count 2 2006.201.08:11:51.03#ibcon#enter sib2, iclass 32, count 2 2006.201.08:11:51.03#ibcon#flushed, iclass 32, count 2 2006.201.08:11:51.03#ibcon#about to write, iclass 32, count 2 2006.201.08:11:51.03#ibcon#wrote, iclass 32, count 2 2006.201.08:11:51.03#ibcon#about to read 3, iclass 32, count 2 2006.201.08:11:51.06#ibcon#read 3, iclass 32, count 2 2006.201.08:11:51.06#ibcon#about to read 4, iclass 32, count 2 2006.201.08:11:51.06#ibcon#read 4, iclass 32, count 2 2006.201.08:11:51.06#ibcon#about to read 5, iclass 32, count 2 2006.201.08:11:51.06#ibcon#read 5, iclass 32, count 2 2006.201.08:11:51.06#ibcon#about to read 6, iclass 32, count 2 2006.201.08:11:51.06#ibcon#read 6, iclass 32, count 2 2006.201.08:11:51.06#ibcon#end of sib2, iclass 32, count 2 2006.201.08:11:51.06#ibcon#*after write, iclass 32, count 2 2006.201.08:11:51.06#ibcon#*before return 0, iclass 32, count 2 2006.201.08:11:51.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:51.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.08:11:51.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.08:11:51.06#ibcon#ireg 7 cls_cnt 0 2006.201.08:11:51.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:51.18#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:51.18#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:51.18#ibcon#enter wrdev, iclass 32, count 0 2006.201.08:11:51.18#ibcon#first serial, iclass 32, count 0 2006.201.08:11:51.18#ibcon#enter sib2, iclass 32, count 0 2006.201.08:11:51.18#ibcon#flushed, iclass 32, count 0 2006.201.08:11:51.18#ibcon#about to write, iclass 32, count 0 2006.201.08:11:51.18#ibcon#wrote, iclass 32, count 0 2006.201.08:11:51.18#ibcon#about to read 3, iclass 32, count 0 2006.201.08:11:51.20#ibcon#read 3, iclass 32, count 0 2006.201.08:11:51.20#ibcon#about to read 4, iclass 32, count 0 2006.201.08:11:51.20#ibcon#read 4, iclass 32, count 0 2006.201.08:11:51.20#ibcon#about to read 5, iclass 32, count 0 2006.201.08:11:51.20#ibcon#read 5, iclass 32, count 0 2006.201.08:11:51.20#ibcon#about to read 6, iclass 32, count 0 2006.201.08:11:51.20#ibcon#read 6, iclass 32, count 0 2006.201.08:11:51.20#ibcon#end of sib2, iclass 32, count 0 2006.201.08:11:51.20#ibcon#*mode == 0, iclass 32, count 0 2006.201.08:11:51.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.08:11:51.20#ibcon#[27=USB\r\n] 2006.201.08:11:51.20#ibcon#*before write, iclass 32, count 0 2006.201.08:11:51.20#ibcon#enter sib2, iclass 32, count 0 2006.201.08:11:51.20#ibcon#flushed, iclass 32, count 0 2006.201.08:11:51.20#ibcon#about to write, iclass 32, count 0 2006.201.08:11:51.20#ibcon#wrote, iclass 32, count 0 2006.201.08:11:51.20#ibcon#about to read 3, iclass 32, count 0 2006.201.08:11:51.23#ibcon#read 3, iclass 32, count 0 2006.201.08:11:51.23#ibcon#about to read 4, iclass 32, count 0 2006.201.08:11:51.23#ibcon#read 4, iclass 32, count 0 2006.201.08:11:51.23#ibcon#about to read 5, iclass 32, count 0 2006.201.08:11:51.23#ibcon#read 5, iclass 32, count 0 2006.201.08:11:51.23#ibcon#about to read 6, iclass 32, count 0 2006.201.08:11:51.23#ibcon#read 6, iclass 32, count 0 2006.201.08:11:51.23#ibcon#end of sib2, iclass 32, count 0 2006.201.08:11:51.23#ibcon#*after write, iclass 32, count 0 2006.201.08:11:51.23#ibcon#*before return 0, iclass 32, count 0 2006.201.08:11:51.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:51.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.08:11:51.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.08:11:51.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.08:11:51.23$vck44/vabw=wide 2006.201.08:11:51.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.08:11:51.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.08:11:51.23#ibcon#ireg 8 cls_cnt 0 2006.201.08:11:51.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:51.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:51.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:51.23#ibcon#enter wrdev, iclass 34, count 0 2006.201.08:11:51.23#ibcon#first serial, iclass 34, count 0 2006.201.08:11:51.23#ibcon#enter sib2, iclass 34, count 0 2006.201.08:11:51.23#ibcon#flushed, iclass 34, count 0 2006.201.08:11:51.23#ibcon#about to write, iclass 34, count 0 2006.201.08:11:51.23#ibcon#wrote, iclass 34, count 0 2006.201.08:11:51.23#ibcon#about to read 3, iclass 34, count 0 2006.201.08:11:51.25#ibcon#read 3, iclass 34, count 0 2006.201.08:11:51.25#ibcon#about to read 4, iclass 34, count 0 2006.201.08:11:51.25#ibcon#read 4, iclass 34, count 0 2006.201.08:11:51.25#ibcon#about to read 5, iclass 34, count 0 2006.201.08:11:51.25#ibcon#read 5, iclass 34, count 0 2006.201.08:11:51.25#ibcon#about to read 6, iclass 34, count 0 2006.201.08:11:51.25#ibcon#read 6, iclass 34, count 0 2006.201.08:11:51.25#ibcon#end of sib2, iclass 34, count 0 2006.201.08:11:51.25#ibcon#*mode == 0, iclass 34, count 0 2006.201.08:11:51.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.08:11:51.25#ibcon#[25=BW32\r\n] 2006.201.08:11:51.25#ibcon#*before write, iclass 34, count 0 2006.201.08:11:51.25#ibcon#enter sib2, iclass 34, count 0 2006.201.08:11:51.25#ibcon#flushed, iclass 34, count 0 2006.201.08:11:51.25#ibcon#about to write, iclass 34, count 0 2006.201.08:11:51.25#ibcon#wrote, iclass 34, count 0 2006.201.08:11:51.25#ibcon#about to read 3, iclass 34, count 0 2006.201.08:11:51.28#ibcon#read 3, iclass 34, count 0 2006.201.08:11:51.28#ibcon#about to read 4, iclass 34, count 0 2006.201.08:11:51.28#ibcon#read 4, iclass 34, count 0 2006.201.08:11:51.28#ibcon#about to read 5, iclass 34, count 0 2006.201.08:11:51.28#ibcon#read 5, iclass 34, count 0 2006.201.08:11:51.28#ibcon#about to read 6, iclass 34, count 0 2006.201.08:11:51.28#ibcon#read 6, iclass 34, count 0 2006.201.08:11:51.28#ibcon#end of sib2, iclass 34, count 0 2006.201.08:11:51.28#ibcon#*after write, iclass 34, count 0 2006.201.08:11:51.28#ibcon#*before return 0, iclass 34, count 0 2006.201.08:11:51.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:51.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.08:11:51.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.08:11:51.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.08:11:51.28$vck44/vbbw=wide 2006.201.08:11:51.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.08:11:51.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.08:11:51.28#ibcon#ireg 8 cls_cnt 0 2006.201.08:11:51.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:11:51.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:11:51.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:11:51.35#ibcon#enter wrdev, iclass 36, count 0 2006.201.08:11:51.35#ibcon#first serial, iclass 36, count 0 2006.201.08:11:51.35#ibcon#enter sib2, iclass 36, count 0 2006.201.08:11:51.35#ibcon#flushed, iclass 36, count 0 2006.201.08:11:51.35#ibcon#about to write, iclass 36, count 0 2006.201.08:11:51.35#ibcon#wrote, iclass 36, count 0 2006.201.08:11:51.35#ibcon#about to read 3, iclass 36, count 0 2006.201.08:11:51.37#ibcon#read 3, iclass 36, count 0 2006.201.08:11:51.37#ibcon#about to read 4, iclass 36, count 0 2006.201.08:11:51.37#ibcon#read 4, iclass 36, count 0 2006.201.08:11:51.37#ibcon#about to read 5, iclass 36, count 0 2006.201.08:11:51.37#ibcon#read 5, iclass 36, count 0 2006.201.08:11:51.37#ibcon#about to read 6, iclass 36, count 0 2006.201.08:11:51.37#ibcon#read 6, iclass 36, count 0 2006.201.08:11:51.37#ibcon#end of sib2, iclass 36, count 0 2006.201.08:11:51.37#ibcon#*mode == 0, iclass 36, count 0 2006.201.08:11:51.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.08:11:51.37#ibcon#[27=BW32\r\n] 2006.201.08:11:51.37#ibcon#*before write, iclass 36, count 0 2006.201.08:11:51.37#ibcon#enter sib2, iclass 36, count 0 2006.201.08:11:51.37#ibcon#flushed, iclass 36, count 0 2006.201.08:11:51.37#ibcon#about to write, iclass 36, count 0 2006.201.08:11:51.37#ibcon#wrote, iclass 36, count 0 2006.201.08:11:51.37#ibcon#about to read 3, iclass 36, count 0 2006.201.08:11:51.40#ibcon#read 3, iclass 36, count 0 2006.201.08:11:51.40#ibcon#about to read 4, iclass 36, count 0 2006.201.08:11:51.40#ibcon#read 4, iclass 36, count 0 2006.201.08:11:51.40#ibcon#about to read 5, iclass 36, count 0 2006.201.08:11:51.40#ibcon#read 5, iclass 36, count 0 2006.201.08:11:51.40#ibcon#about to read 6, iclass 36, count 0 2006.201.08:11:51.40#ibcon#read 6, iclass 36, count 0 2006.201.08:11:51.40#ibcon#end of sib2, iclass 36, count 0 2006.201.08:11:51.40#ibcon#*after write, iclass 36, count 0 2006.201.08:11:51.40#ibcon#*before return 0, iclass 36, count 0 2006.201.08:11:51.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:11:51.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:11:51.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.08:11:51.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.08:11:51.40$setupk4/ifdk4 2006.201.08:11:51.40$ifdk4/lo= 2006.201.08:11:51.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:11:51.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:11:51.40$ifdk4/patch= 2006.201.08:11:51.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:11:51.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:11:51.40$setupk4/!*+20s 2006.201.08:11:51.87#abcon#<5=/04 2.4 4.6 23.22 871003.2\r\n> 2006.201.08:11:51.89#abcon#{5=INTERFACE CLEAR} 2006.201.08:11:51.95#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:12:02.04#abcon#<5=/04 2.4 4.6 23.21 871003.2\r\n> 2006.201.08:12:02.06#abcon#{5=INTERFACE CLEAR} 2006.201.08:12:02.12#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:12:02.14#trakl#Source acquired 2006.201.08:12:02.14#flagr#flagr/antenna,acquired 2006.201.08:12:05.88$setupk4/"tpicd 2006.201.08:12:05.88$setupk4/echo=off 2006.201.08:12:05.88$setupk4/xlog=off 2006.201.08:12:05.88:!2006.201.08:13:12 2006.201.08:13:12.00:preob 2006.201.08:13:12.14/onsource/TRACKING 2006.201.08:13:12.14:!2006.201.08:13:22 2006.201.08:13:22.00:"tape 2006.201.08:13:22.00:"st=record 2006.201.08:13:22.00:data_valid=on 2006.201.08:13:22.00:midob 2006.201.08:13:23.14/onsource/TRACKING 2006.201.08:13:23.14/wx/23.21,1003.2,86 2006.201.08:13:23.24/cable/+6.4669E-03 2006.201.08:13:24.33/va/01,08,usb,yes,33,36 2006.201.08:13:24.33/va/02,07,usb,yes,36,37 2006.201.08:13:24.33/va/03,08,usb,yes,32,34 2006.201.08:13:24.33/va/04,07,usb,yes,37,39 2006.201.08:13:24.33/va/05,04,usb,yes,33,33 2006.201.08:13:24.33/va/06,05,usb,yes,33,33 2006.201.08:13:24.33/va/07,05,usb,yes,32,33 2006.201.08:13:24.33/va/08,04,usb,yes,32,38 2006.201.08:13:24.56/valo/01,524.99,yes,locked 2006.201.08:13:24.56/valo/02,534.99,yes,locked 2006.201.08:13:24.56/valo/03,564.99,yes,locked 2006.201.08:13:24.56/valo/04,624.99,yes,locked 2006.201.08:13:24.56/valo/05,734.99,yes,locked 2006.201.08:13:24.56/valo/06,814.99,yes,locked 2006.201.08:13:24.56/valo/07,864.99,yes,locked 2006.201.08:13:24.56/valo/08,884.99,yes,locked 2006.201.08:13:25.65/vb/01,04,usb,yes,30,28 2006.201.08:13:25.65/vb/02,05,usb,yes,29,28 2006.201.08:13:25.65/vb/03,04,usb,yes,29,33 2006.201.08:13:25.65/vb/04,05,usb,yes,30,29 2006.201.08:13:25.65/vb/05,04,usb,yes,26,29 2006.201.08:13:25.65/vb/06,04,usb,yes,31,27 2006.201.08:13:25.65/vb/07,04,usb,yes,31,30 2006.201.08:13:25.65/vb/08,04,usb,yes,28,31 2006.201.08:13:25.88/vblo/01,629.99,yes,locked 2006.201.08:13:25.88/vblo/02,634.99,yes,locked 2006.201.08:13:25.88/vblo/03,649.99,yes,locked 2006.201.08:13:25.88/vblo/04,679.99,yes,locked 2006.201.08:13:25.88/vblo/05,709.99,yes,locked 2006.201.08:13:25.88/vblo/06,719.99,yes,locked 2006.201.08:13:25.88/vblo/07,734.99,yes,locked 2006.201.08:13:25.88/vblo/08,744.99,yes,locked 2006.201.08:13:26.03/vabw/8 2006.201.08:13:26.18/vbbw/8 2006.201.08:13:26.27/xfe/off,on,14.5 2006.201.08:13:26.64/ifatt/23,28,28,28 2006.201.08:13:27.05/fmout-gps/S +4.54E-07 2006.201.08:13:27.09:!2006.201.08:14:02 2006.201.08:14:02.00:data_valid=off 2006.201.08:14:02.00:"et 2006.201.08:14:02.00:!+3s 2006.201.08:14:05.01:"tape 2006.201.08:14:05.01:postob 2006.201.08:14:05.11/cable/+6.4670E-03 2006.201.08:14:05.11/wx/23.21,1003.2,87 2006.201.08:14:05.17/fmout-gps/S +4.53E-07 2006.201.08:14:05.17:scan_name=201-0819,jd0607,220 2006.201.08:14:05.17:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.201.08:14:07.14#flagr#flagr/antenna,new-source 2006.201.08:14:07.14:checkk5 2006.201.08:14:07.49/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:14:07.84/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:14:08.19/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:14:08.54/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:14:08.88/chk_obsdata//k5ts1/T2010813??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.08:14:09.23/chk_obsdata//k5ts2/T2010813??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.08:14:09.58/chk_obsdata//k5ts3/T2010813??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.08:14:09.93/chk_obsdata//k5ts4/T2010813??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.08:14:10.65/k5log//k5ts1_log_newline 2006.201.08:14:11.32/k5log//k5ts2_log_newline 2006.201.08:14:11.99/k5log//k5ts3_log_newline 2006.201.08:14:12.66/k5log//k5ts4_log_newline 2006.201.08:14:12.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:14:12.68:setupk4=1 2006.201.08:14:12.68$setupk4/echo=on 2006.201.08:14:12.68$setupk4/pcalon 2006.201.08:14:12.68$pcalon/"no phase cal control is implemented here 2006.201.08:14:12.68$setupk4/"tpicd=stop 2006.201.08:14:12.68$setupk4/"rec=synch_on 2006.201.08:14:12.68$setupk4/"rec_mode=128 2006.201.08:14:12.68$setupk4/!* 2006.201.08:14:12.68$setupk4/recpk4 2006.201.08:14:12.68$recpk4/recpatch= 2006.201.08:14:12.69$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:14:12.69$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:14:12.69$setupk4/vck44 2006.201.08:14:12.69$vck44/valo=1,524.99 2006.201.08:14:12.69#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.08:14:12.69#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.08:14:12.69#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:12.69#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:12.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:12.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:12.69#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:14:12.69#ibcon#first serial, iclass 25, count 0 2006.201.08:14:12.69#ibcon#enter sib2, iclass 25, count 0 2006.201.08:14:12.69#ibcon#flushed, iclass 25, count 0 2006.201.08:14:12.69#ibcon#about to write, iclass 25, count 0 2006.201.08:14:12.69#ibcon#wrote, iclass 25, count 0 2006.201.08:14:12.69#ibcon#about to read 3, iclass 25, count 0 2006.201.08:14:12.71#ibcon#read 3, iclass 25, count 0 2006.201.08:14:12.71#ibcon#about to read 4, iclass 25, count 0 2006.201.08:14:12.71#ibcon#read 4, iclass 25, count 0 2006.201.08:14:12.71#ibcon#about to read 5, iclass 25, count 0 2006.201.08:14:12.71#ibcon#read 5, iclass 25, count 0 2006.201.08:14:12.71#ibcon#about to read 6, iclass 25, count 0 2006.201.08:14:12.71#ibcon#read 6, iclass 25, count 0 2006.201.08:14:12.71#ibcon#end of sib2, iclass 25, count 0 2006.201.08:14:12.71#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:14:12.71#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:14:12.71#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:14:12.71#ibcon#*before write, iclass 25, count 0 2006.201.08:14:12.71#ibcon#enter sib2, iclass 25, count 0 2006.201.08:14:12.71#ibcon#flushed, iclass 25, count 0 2006.201.08:14:12.71#ibcon#about to write, iclass 25, count 0 2006.201.08:14:12.71#ibcon#wrote, iclass 25, count 0 2006.201.08:14:12.71#ibcon#about to read 3, iclass 25, count 0 2006.201.08:14:12.76#ibcon#read 3, iclass 25, count 0 2006.201.08:14:12.76#ibcon#about to read 4, iclass 25, count 0 2006.201.08:14:12.76#ibcon#read 4, iclass 25, count 0 2006.201.08:14:12.76#ibcon#about to read 5, iclass 25, count 0 2006.201.08:14:12.76#ibcon#read 5, iclass 25, count 0 2006.201.08:14:12.76#ibcon#about to read 6, iclass 25, count 0 2006.201.08:14:12.76#ibcon#read 6, iclass 25, count 0 2006.201.08:14:12.76#ibcon#end of sib2, iclass 25, count 0 2006.201.08:14:12.76#ibcon#*after write, iclass 25, count 0 2006.201.08:14:12.76#ibcon#*before return 0, iclass 25, count 0 2006.201.08:14:12.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:12.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:12.76#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:14:12.76#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:14:12.76$vck44/va=1,8 2006.201.08:14:12.76#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.08:14:12.76#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.08:14:12.76#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:12.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:12.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:12.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:12.76#ibcon#enter wrdev, iclass 27, count 2 2006.201.08:14:12.76#ibcon#first serial, iclass 27, count 2 2006.201.08:14:12.76#ibcon#enter sib2, iclass 27, count 2 2006.201.08:14:12.76#ibcon#flushed, iclass 27, count 2 2006.201.08:14:12.76#ibcon#about to write, iclass 27, count 2 2006.201.08:14:12.76#ibcon#wrote, iclass 27, count 2 2006.201.08:14:12.76#ibcon#about to read 3, iclass 27, count 2 2006.201.08:14:12.78#ibcon#read 3, iclass 27, count 2 2006.201.08:14:12.78#ibcon#about to read 4, iclass 27, count 2 2006.201.08:14:12.78#ibcon#read 4, iclass 27, count 2 2006.201.08:14:12.78#ibcon#about to read 5, iclass 27, count 2 2006.201.08:14:12.78#ibcon#read 5, iclass 27, count 2 2006.201.08:14:12.78#ibcon#about to read 6, iclass 27, count 2 2006.201.08:14:12.78#ibcon#read 6, iclass 27, count 2 2006.201.08:14:12.78#ibcon#end of sib2, iclass 27, count 2 2006.201.08:14:12.78#ibcon#*mode == 0, iclass 27, count 2 2006.201.08:14:12.78#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.08:14:12.78#ibcon#[25=AT01-08\r\n] 2006.201.08:14:12.78#ibcon#*before write, iclass 27, count 2 2006.201.08:14:12.78#ibcon#enter sib2, iclass 27, count 2 2006.201.08:14:12.78#ibcon#flushed, iclass 27, count 2 2006.201.08:14:12.78#ibcon#about to write, iclass 27, count 2 2006.201.08:14:12.78#ibcon#wrote, iclass 27, count 2 2006.201.08:14:12.78#ibcon#about to read 3, iclass 27, count 2 2006.201.08:14:12.81#ibcon#read 3, iclass 27, count 2 2006.201.08:14:12.81#ibcon#about to read 4, iclass 27, count 2 2006.201.08:14:12.81#ibcon#read 4, iclass 27, count 2 2006.201.08:14:12.81#ibcon#about to read 5, iclass 27, count 2 2006.201.08:14:12.81#ibcon#read 5, iclass 27, count 2 2006.201.08:14:12.81#ibcon#about to read 6, iclass 27, count 2 2006.201.08:14:12.81#ibcon#read 6, iclass 27, count 2 2006.201.08:14:12.81#ibcon#end of sib2, iclass 27, count 2 2006.201.08:14:12.81#ibcon#*after write, iclass 27, count 2 2006.201.08:14:12.81#ibcon#*before return 0, iclass 27, count 2 2006.201.08:14:12.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:12.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:12.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.08:14:12.81#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:12.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:12.93#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:12.93#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:12.93#ibcon#enter wrdev, iclass 27, count 0 2006.201.08:14:12.93#ibcon#first serial, iclass 27, count 0 2006.201.08:14:12.93#ibcon#enter sib2, iclass 27, count 0 2006.201.08:14:12.93#ibcon#flushed, iclass 27, count 0 2006.201.08:14:12.93#ibcon#about to write, iclass 27, count 0 2006.201.08:14:12.93#ibcon#wrote, iclass 27, count 0 2006.201.08:14:12.93#ibcon#about to read 3, iclass 27, count 0 2006.201.08:14:12.95#ibcon#read 3, iclass 27, count 0 2006.201.08:14:12.95#ibcon#about to read 4, iclass 27, count 0 2006.201.08:14:12.95#ibcon#read 4, iclass 27, count 0 2006.201.08:14:12.95#ibcon#about to read 5, iclass 27, count 0 2006.201.08:14:12.95#ibcon#read 5, iclass 27, count 0 2006.201.08:14:12.95#ibcon#about to read 6, iclass 27, count 0 2006.201.08:14:12.95#ibcon#read 6, iclass 27, count 0 2006.201.08:14:12.95#ibcon#end of sib2, iclass 27, count 0 2006.201.08:14:12.95#ibcon#*mode == 0, iclass 27, count 0 2006.201.08:14:12.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.08:14:12.95#ibcon#[25=USB\r\n] 2006.201.08:14:12.95#ibcon#*before write, iclass 27, count 0 2006.201.08:14:12.95#ibcon#enter sib2, iclass 27, count 0 2006.201.08:14:12.95#ibcon#flushed, iclass 27, count 0 2006.201.08:14:12.95#ibcon#about to write, iclass 27, count 0 2006.201.08:14:12.95#ibcon#wrote, iclass 27, count 0 2006.201.08:14:12.95#ibcon#about to read 3, iclass 27, count 0 2006.201.08:14:12.98#ibcon#read 3, iclass 27, count 0 2006.201.08:14:12.98#ibcon#about to read 4, iclass 27, count 0 2006.201.08:14:12.98#ibcon#read 4, iclass 27, count 0 2006.201.08:14:12.98#ibcon#about to read 5, iclass 27, count 0 2006.201.08:14:12.98#ibcon#read 5, iclass 27, count 0 2006.201.08:14:12.98#ibcon#about to read 6, iclass 27, count 0 2006.201.08:14:12.98#ibcon#read 6, iclass 27, count 0 2006.201.08:14:12.98#ibcon#end of sib2, iclass 27, count 0 2006.201.08:14:12.98#ibcon#*after write, iclass 27, count 0 2006.201.08:14:12.98#ibcon#*before return 0, iclass 27, count 0 2006.201.08:14:12.98#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:12.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:12.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.08:14:12.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.08:14:12.98$vck44/valo=2,534.99 2006.201.08:14:12.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.08:14:12.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.08:14:12.98#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:12.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:12.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:12.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:12.98#ibcon#enter wrdev, iclass 29, count 0 2006.201.08:14:12.98#ibcon#first serial, iclass 29, count 0 2006.201.08:14:12.98#ibcon#enter sib2, iclass 29, count 0 2006.201.08:14:12.98#ibcon#flushed, iclass 29, count 0 2006.201.08:14:12.98#ibcon#about to write, iclass 29, count 0 2006.201.08:14:12.98#ibcon#wrote, iclass 29, count 0 2006.201.08:14:12.98#ibcon#about to read 3, iclass 29, count 0 2006.201.08:14:13.00#ibcon#read 3, iclass 29, count 0 2006.201.08:14:13.00#ibcon#about to read 4, iclass 29, count 0 2006.201.08:14:13.00#ibcon#read 4, iclass 29, count 0 2006.201.08:14:13.00#ibcon#about to read 5, iclass 29, count 0 2006.201.08:14:13.00#ibcon#read 5, iclass 29, count 0 2006.201.08:14:13.00#ibcon#about to read 6, iclass 29, count 0 2006.201.08:14:13.00#ibcon#read 6, iclass 29, count 0 2006.201.08:14:13.00#ibcon#end of sib2, iclass 29, count 0 2006.201.08:14:13.00#ibcon#*mode == 0, iclass 29, count 0 2006.201.08:14:13.00#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.08:14:13.00#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:14:13.00#ibcon#*before write, iclass 29, count 0 2006.201.08:14:13.00#ibcon#enter sib2, iclass 29, count 0 2006.201.08:14:13.00#ibcon#flushed, iclass 29, count 0 2006.201.08:14:13.00#ibcon#about to write, iclass 29, count 0 2006.201.08:14:13.00#ibcon#wrote, iclass 29, count 0 2006.201.08:14:13.00#ibcon#about to read 3, iclass 29, count 0 2006.201.08:14:13.04#ibcon#read 3, iclass 29, count 0 2006.201.08:14:13.04#ibcon#about to read 4, iclass 29, count 0 2006.201.08:14:13.04#ibcon#read 4, iclass 29, count 0 2006.201.08:14:13.04#ibcon#about to read 5, iclass 29, count 0 2006.201.08:14:13.04#ibcon#read 5, iclass 29, count 0 2006.201.08:14:13.04#ibcon#about to read 6, iclass 29, count 0 2006.201.08:14:13.04#ibcon#read 6, iclass 29, count 0 2006.201.08:14:13.04#ibcon#end of sib2, iclass 29, count 0 2006.201.08:14:13.04#ibcon#*after write, iclass 29, count 0 2006.201.08:14:13.04#ibcon#*before return 0, iclass 29, count 0 2006.201.08:14:13.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:13.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:13.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.08:14:13.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.08:14:13.04$vck44/va=2,7 2006.201.08:14:13.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.08:14:13.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.08:14:13.04#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:13.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:13.10#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:13.10#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:13.10#ibcon#enter wrdev, iclass 31, count 2 2006.201.08:14:13.10#ibcon#first serial, iclass 31, count 2 2006.201.08:14:13.10#ibcon#enter sib2, iclass 31, count 2 2006.201.08:14:13.10#ibcon#flushed, iclass 31, count 2 2006.201.08:14:13.10#ibcon#about to write, iclass 31, count 2 2006.201.08:14:13.10#ibcon#wrote, iclass 31, count 2 2006.201.08:14:13.10#ibcon#about to read 3, iclass 31, count 2 2006.201.08:14:13.12#ibcon#read 3, iclass 31, count 2 2006.201.08:14:13.12#ibcon#about to read 4, iclass 31, count 2 2006.201.08:14:13.12#ibcon#read 4, iclass 31, count 2 2006.201.08:14:13.12#ibcon#about to read 5, iclass 31, count 2 2006.201.08:14:13.12#ibcon#read 5, iclass 31, count 2 2006.201.08:14:13.12#ibcon#about to read 6, iclass 31, count 2 2006.201.08:14:13.12#ibcon#read 6, iclass 31, count 2 2006.201.08:14:13.12#ibcon#end of sib2, iclass 31, count 2 2006.201.08:14:13.12#ibcon#*mode == 0, iclass 31, count 2 2006.201.08:14:13.12#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.08:14:13.12#ibcon#[25=AT02-07\r\n] 2006.201.08:14:13.12#ibcon#*before write, iclass 31, count 2 2006.201.08:14:13.12#ibcon#enter sib2, iclass 31, count 2 2006.201.08:14:13.12#ibcon#flushed, iclass 31, count 2 2006.201.08:14:13.12#ibcon#about to write, iclass 31, count 2 2006.201.08:14:13.12#ibcon#wrote, iclass 31, count 2 2006.201.08:14:13.12#ibcon#about to read 3, iclass 31, count 2 2006.201.08:14:13.15#ibcon#read 3, iclass 31, count 2 2006.201.08:14:13.15#ibcon#about to read 4, iclass 31, count 2 2006.201.08:14:13.15#ibcon#read 4, iclass 31, count 2 2006.201.08:14:13.15#ibcon#about to read 5, iclass 31, count 2 2006.201.08:14:13.15#ibcon#read 5, iclass 31, count 2 2006.201.08:14:13.15#ibcon#about to read 6, iclass 31, count 2 2006.201.08:14:13.15#ibcon#read 6, iclass 31, count 2 2006.201.08:14:13.15#ibcon#end of sib2, iclass 31, count 2 2006.201.08:14:13.15#ibcon#*after write, iclass 31, count 2 2006.201.08:14:13.15#ibcon#*before return 0, iclass 31, count 2 2006.201.08:14:13.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:13.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:13.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.08:14:13.15#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:13.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:13.27#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:13.27#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:13.27#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:14:13.27#ibcon#first serial, iclass 31, count 0 2006.201.08:14:13.27#ibcon#enter sib2, iclass 31, count 0 2006.201.08:14:13.27#ibcon#flushed, iclass 31, count 0 2006.201.08:14:13.27#ibcon#about to write, iclass 31, count 0 2006.201.08:14:13.27#ibcon#wrote, iclass 31, count 0 2006.201.08:14:13.27#ibcon#about to read 3, iclass 31, count 0 2006.201.08:14:13.29#ibcon#read 3, iclass 31, count 0 2006.201.08:14:13.29#ibcon#about to read 4, iclass 31, count 0 2006.201.08:14:13.29#ibcon#read 4, iclass 31, count 0 2006.201.08:14:13.29#ibcon#about to read 5, iclass 31, count 0 2006.201.08:14:13.29#ibcon#read 5, iclass 31, count 0 2006.201.08:14:13.29#ibcon#about to read 6, iclass 31, count 0 2006.201.08:14:13.29#ibcon#read 6, iclass 31, count 0 2006.201.08:14:13.29#ibcon#end of sib2, iclass 31, count 0 2006.201.08:14:13.29#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:14:13.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:14:13.29#ibcon#[25=USB\r\n] 2006.201.08:14:13.29#ibcon#*before write, iclass 31, count 0 2006.201.08:14:13.29#ibcon#enter sib2, iclass 31, count 0 2006.201.08:14:13.29#ibcon#flushed, iclass 31, count 0 2006.201.08:14:13.29#ibcon#about to write, iclass 31, count 0 2006.201.08:14:13.29#ibcon#wrote, iclass 31, count 0 2006.201.08:14:13.29#ibcon#about to read 3, iclass 31, count 0 2006.201.08:14:13.32#ibcon#read 3, iclass 31, count 0 2006.201.08:14:13.32#ibcon#about to read 4, iclass 31, count 0 2006.201.08:14:13.32#ibcon#read 4, iclass 31, count 0 2006.201.08:14:13.32#ibcon#about to read 5, iclass 31, count 0 2006.201.08:14:13.32#ibcon#read 5, iclass 31, count 0 2006.201.08:14:13.32#ibcon#about to read 6, iclass 31, count 0 2006.201.08:14:13.32#ibcon#read 6, iclass 31, count 0 2006.201.08:14:13.32#ibcon#end of sib2, iclass 31, count 0 2006.201.08:14:13.32#ibcon#*after write, iclass 31, count 0 2006.201.08:14:13.32#ibcon#*before return 0, iclass 31, count 0 2006.201.08:14:13.32#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:13.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:13.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:14:13.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:14:13.32$vck44/valo=3,564.99 2006.201.08:14:13.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.08:14:13.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.08:14:13.32#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:13.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:13.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:13.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:13.32#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:14:13.32#ibcon#first serial, iclass 33, count 0 2006.201.08:14:13.32#ibcon#enter sib2, iclass 33, count 0 2006.201.08:14:13.32#ibcon#flushed, iclass 33, count 0 2006.201.08:14:13.32#ibcon#about to write, iclass 33, count 0 2006.201.08:14:13.32#ibcon#wrote, iclass 33, count 0 2006.201.08:14:13.32#ibcon#about to read 3, iclass 33, count 0 2006.201.08:14:13.34#ibcon#read 3, iclass 33, count 0 2006.201.08:14:13.34#ibcon#about to read 4, iclass 33, count 0 2006.201.08:14:13.34#ibcon#read 4, iclass 33, count 0 2006.201.08:14:13.34#ibcon#about to read 5, iclass 33, count 0 2006.201.08:14:13.34#ibcon#read 5, iclass 33, count 0 2006.201.08:14:13.34#ibcon#about to read 6, iclass 33, count 0 2006.201.08:14:13.34#ibcon#read 6, iclass 33, count 0 2006.201.08:14:13.34#ibcon#end of sib2, iclass 33, count 0 2006.201.08:14:13.34#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:14:13.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:14:13.34#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:14:13.34#ibcon#*before write, iclass 33, count 0 2006.201.08:14:13.34#ibcon#enter sib2, iclass 33, count 0 2006.201.08:14:13.34#ibcon#flushed, iclass 33, count 0 2006.201.08:14:13.34#ibcon#about to write, iclass 33, count 0 2006.201.08:14:13.34#ibcon#wrote, iclass 33, count 0 2006.201.08:14:13.34#ibcon#about to read 3, iclass 33, count 0 2006.201.08:14:13.38#ibcon#read 3, iclass 33, count 0 2006.201.08:14:13.38#ibcon#about to read 4, iclass 33, count 0 2006.201.08:14:13.38#ibcon#read 4, iclass 33, count 0 2006.201.08:14:13.38#ibcon#about to read 5, iclass 33, count 0 2006.201.08:14:13.38#ibcon#read 5, iclass 33, count 0 2006.201.08:14:13.38#ibcon#about to read 6, iclass 33, count 0 2006.201.08:14:13.38#ibcon#read 6, iclass 33, count 0 2006.201.08:14:13.38#ibcon#end of sib2, iclass 33, count 0 2006.201.08:14:13.38#ibcon#*after write, iclass 33, count 0 2006.201.08:14:13.38#ibcon#*before return 0, iclass 33, count 0 2006.201.08:14:13.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:13.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:13.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:14:13.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:14:13.38$vck44/va=3,8 2006.201.08:14:13.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.08:14:13.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.08:14:13.38#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:13.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:13.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:13.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:13.44#ibcon#enter wrdev, iclass 35, count 2 2006.201.08:14:13.44#ibcon#first serial, iclass 35, count 2 2006.201.08:14:13.44#ibcon#enter sib2, iclass 35, count 2 2006.201.08:14:13.44#ibcon#flushed, iclass 35, count 2 2006.201.08:14:13.44#ibcon#about to write, iclass 35, count 2 2006.201.08:14:13.44#ibcon#wrote, iclass 35, count 2 2006.201.08:14:13.44#ibcon#about to read 3, iclass 35, count 2 2006.201.08:14:13.46#ibcon#read 3, iclass 35, count 2 2006.201.08:14:13.46#ibcon#about to read 4, iclass 35, count 2 2006.201.08:14:13.46#ibcon#read 4, iclass 35, count 2 2006.201.08:14:13.46#ibcon#about to read 5, iclass 35, count 2 2006.201.08:14:13.46#ibcon#read 5, iclass 35, count 2 2006.201.08:14:13.46#ibcon#about to read 6, iclass 35, count 2 2006.201.08:14:13.46#ibcon#read 6, iclass 35, count 2 2006.201.08:14:13.46#ibcon#end of sib2, iclass 35, count 2 2006.201.08:14:13.46#ibcon#*mode == 0, iclass 35, count 2 2006.201.08:14:13.46#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.08:14:13.46#ibcon#[25=AT03-08\r\n] 2006.201.08:14:13.46#ibcon#*before write, iclass 35, count 2 2006.201.08:14:13.46#ibcon#enter sib2, iclass 35, count 2 2006.201.08:14:13.46#ibcon#flushed, iclass 35, count 2 2006.201.08:14:13.46#ibcon#about to write, iclass 35, count 2 2006.201.08:14:13.46#ibcon#wrote, iclass 35, count 2 2006.201.08:14:13.46#ibcon#about to read 3, iclass 35, count 2 2006.201.08:14:13.49#ibcon#read 3, iclass 35, count 2 2006.201.08:14:13.49#ibcon#about to read 4, iclass 35, count 2 2006.201.08:14:13.49#ibcon#read 4, iclass 35, count 2 2006.201.08:14:13.49#ibcon#about to read 5, iclass 35, count 2 2006.201.08:14:13.49#ibcon#read 5, iclass 35, count 2 2006.201.08:14:13.49#ibcon#about to read 6, iclass 35, count 2 2006.201.08:14:13.49#ibcon#read 6, iclass 35, count 2 2006.201.08:14:13.49#ibcon#end of sib2, iclass 35, count 2 2006.201.08:14:13.49#ibcon#*after write, iclass 35, count 2 2006.201.08:14:13.49#ibcon#*before return 0, iclass 35, count 2 2006.201.08:14:13.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:13.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:13.49#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.08:14:13.49#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:13.49#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:13.61#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:13.61#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:13.61#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:14:13.61#ibcon#first serial, iclass 35, count 0 2006.201.08:14:13.61#ibcon#enter sib2, iclass 35, count 0 2006.201.08:14:13.61#ibcon#flushed, iclass 35, count 0 2006.201.08:14:13.61#ibcon#about to write, iclass 35, count 0 2006.201.08:14:13.61#ibcon#wrote, iclass 35, count 0 2006.201.08:14:13.61#ibcon#about to read 3, iclass 35, count 0 2006.201.08:14:13.63#ibcon#read 3, iclass 35, count 0 2006.201.08:14:13.63#ibcon#about to read 4, iclass 35, count 0 2006.201.08:14:13.63#ibcon#read 4, iclass 35, count 0 2006.201.08:14:13.63#ibcon#about to read 5, iclass 35, count 0 2006.201.08:14:13.63#ibcon#read 5, iclass 35, count 0 2006.201.08:14:13.63#ibcon#about to read 6, iclass 35, count 0 2006.201.08:14:13.63#ibcon#read 6, iclass 35, count 0 2006.201.08:14:13.63#ibcon#end of sib2, iclass 35, count 0 2006.201.08:14:13.63#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:14:13.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:14:13.63#ibcon#[25=USB\r\n] 2006.201.08:14:13.63#ibcon#*before write, iclass 35, count 0 2006.201.08:14:13.63#ibcon#enter sib2, iclass 35, count 0 2006.201.08:14:13.63#ibcon#flushed, iclass 35, count 0 2006.201.08:14:13.63#ibcon#about to write, iclass 35, count 0 2006.201.08:14:13.63#ibcon#wrote, iclass 35, count 0 2006.201.08:14:13.63#ibcon#about to read 3, iclass 35, count 0 2006.201.08:14:13.66#ibcon#read 3, iclass 35, count 0 2006.201.08:14:13.66#ibcon#about to read 4, iclass 35, count 0 2006.201.08:14:13.66#ibcon#read 4, iclass 35, count 0 2006.201.08:14:13.66#ibcon#about to read 5, iclass 35, count 0 2006.201.08:14:13.66#ibcon#read 5, iclass 35, count 0 2006.201.08:14:13.66#ibcon#about to read 6, iclass 35, count 0 2006.201.08:14:13.66#ibcon#read 6, iclass 35, count 0 2006.201.08:14:13.66#ibcon#end of sib2, iclass 35, count 0 2006.201.08:14:13.66#ibcon#*after write, iclass 35, count 0 2006.201.08:14:13.66#ibcon#*before return 0, iclass 35, count 0 2006.201.08:14:13.66#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:13.66#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:13.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:14:13.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:14:13.66$vck44/valo=4,624.99 2006.201.08:14:13.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.08:14:13.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.08:14:13.66#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:13.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:13.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:13.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:13.66#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:14:13.66#ibcon#first serial, iclass 37, count 0 2006.201.08:14:13.66#ibcon#enter sib2, iclass 37, count 0 2006.201.08:14:13.66#ibcon#flushed, iclass 37, count 0 2006.201.08:14:13.66#ibcon#about to write, iclass 37, count 0 2006.201.08:14:13.66#ibcon#wrote, iclass 37, count 0 2006.201.08:14:13.66#ibcon#about to read 3, iclass 37, count 0 2006.201.08:14:13.68#ibcon#read 3, iclass 37, count 0 2006.201.08:14:13.68#ibcon#about to read 4, iclass 37, count 0 2006.201.08:14:13.68#ibcon#read 4, iclass 37, count 0 2006.201.08:14:13.68#ibcon#about to read 5, iclass 37, count 0 2006.201.08:14:13.68#ibcon#read 5, iclass 37, count 0 2006.201.08:14:13.68#ibcon#about to read 6, iclass 37, count 0 2006.201.08:14:13.68#ibcon#read 6, iclass 37, count 0 2006.201.08:14:13.68#ibcon#end of sib2, iclass 37, count 0 2006.201.08:14:13.68#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:14:13.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:14:13.68#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:14:13.68#ibcon#*before write, iclass 37, count 0 2006.201.08:14:13.68#ibcon#enter sib2, iclass 37, count 0 2006.201.08:14:13.68#ibcon#flushed, iclass 37, count 0 2006.201.08:14:13.68#ibcon#about to write, iclass 37, count 0 2006.201.08:14:13.68#ibcon#wrote, iclass 37, count 0 2006.201.08:14:13.68#ibcon#about to read 3, iclass 37, count 0 2006.201.08:14:13.72#ibcon#read 3, iclass 37, count 0 2006.201.08:14:13.72#ibcon#about to read 4, iclass 37, count 0 2006.201.08:14:13.72#ibcon#read 4, iclass 37, count 0 2006.201.08:14:13.72#ibcon#about to read 5, iclass 37, count 0 2006.201.08:14:13.72#ibcon#read 5, iclass 37, count 0 2006.201.08:14:13.72#ibcon#about to read 6, iclass 37, count 0 2006.201.08:14:13.72#ibcon#read 6, iclass 37, count 0 2006.201.08:14:13.72#ibcon#end of sib2, iclass 37, count 0 2006.201.08:14:13.72#ibcon#*after write, iclass 37, count 0 2006.201.08:14:13.72#ibcon#*before return 0, iclass 37, count 0 2006.201.08:14:13.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:13.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:13.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:14:13.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:14:13.72$vck44/va=4,7 2006.201.08:14:13.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.08:14:13.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.08:14:13.72#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:13.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:13.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:13.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:13.78#ibcon#enter wrdev, iclass 39, count 2 2006.201.08:14:13.78#ibcon#first serial, iclass 39, count 2 2006.201.08:14:13.78#ibcon#enter sib2, iclass 39, count 2 2006.201.08:14:13.78#ibcon#flushed, iclass 39, count 2 2006.201.08:14:13.78#ibcon#about to write, iclass 39, count 2 2006.201.08:14:13.78#ibcon#wrote, iclass 39, count 2 2006.201.08:14:13.78#ibcon#about to read 3, iclass 39, count 2 2006.201.08:14:13.80#ibcon#read 3, iclass 39, count 2 2006.201.08:14:13.80#ibcon#about to read 4, iclass 39, count 2 2006.201.08:14:13.80#ibcon#read 4, iclass 39, count 2 2006.201.08:14:13.80#ibcon#about to read 5, iclass 39, count 2 2006.201.08:14:13.80#ibcon#read 5, iclass 39, count 2 2006.201.08:14:13.80#ibcon#about to read 6, iclass 39, count 2 2006.201.08:14:13.80#ibcon#read 6, iclass 39, count 2 2006.201.08:14:13.80#ibcon#end of sib2, iclass 39, count 2 2006.201.08:14:13.80#ibcon#*mode == 0, iclass 39, count 2 2006.201.08:14:13.80#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.08:14:13.80#ibcon#[25=AT04-07\r\n] 2006.201.08:14:13.80#ibcon#*before write, iclass 39, count 2 2006.201.08:14:13.80#ibcon#enter sib2, iclass 39, count 2 2006.201.08:14:13.80#ibcon#flushed, iclass 39, count 2 2006.201.08:14:13.80#ibcon#about to write, iclass 39, count 2 2006.201.08:14:13.80#ibcon#wrote, iclass 39, count 2 2006.201.08:14:13.80#ibcon#about to read 3, iclass 39, count 2 2006.201.08:14:13.83#ibcon#read 3, iclass 39, count 2 2006.201.08:14:13.83#ibcon#about to read 4, iclass 39, count 2 2006.201.08:14:13.83#ibcon#read 4, iclass 39, count 2 2006.201.08:14:13.83#ibcon#about to read 5, iclass 39, count 2 2006.201.08:14:13.83#ibcon#read 5, iclass 39, count 2 2006.201.08:14:13.83#ibcon#about to read 6, iclass 39, count 2 2006.201.08:14:13.83#ibcon#read 6, iclass 39, count 2 2006.201.08:14:13.83#ibcon#end of sib2, iclass 39, count 2 2006.201.08:14:13.83#ibcon#*after write, iclass 39, count 2 2006.201.08:14:13.83#ibcon#*before return 0, iclass 39, count 2 2006.201.08:14:13.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:13.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:13.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.08:14:13.83#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:13.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:13.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:13.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:13.95#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:14:13.95#ibcon#first serial, iclass 39, count 0 2006.201.08:14:13.95#ibcon#enter sib2, iclass 39, count 0 2006.201.08:14:13.95#ibcon#flushed, iclass 39, count 0 2006.201.08:14:13.95#ibcon#about to write, iclass 39, count 0 2006.201.08:14:13.95#ibcon#wrote, iclass 39, count 0 2006.201.08:14:13.95#ibcon#about to read 3, iclass 39, count 0 2006.201.08:14:13.97#ibcon#read 3, iclass 39, count 0 2006.201.08:14:13.97#ibcon#about to read 4, iclass 39, count 0 2006.201.08:14:13.97#ibcon#read 4, iclass 39, count 0 2006.201.08:14:13.97#ibcon#about to read 5, iclass 39, count 0 2006.201.08:14:13.97#ibcon#read 5, iclass 39, count 0 2006.201.08:14:13.97#ibcon#about to read 6, iclass 39, count 0 2006.201.08:14:13.97#ibcon#read 6, iclass 39, count 0 2006.201.08:14:13.97#ibcon#end of sib2, iclass 39, count 0 2006.201.08:14:13.97#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:14:13.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:14:13.97#ibcon#[25=USB\r\n] 2006.201.08:14:13.97#ibcon#*before write, iclass 39, count 0 2006.201.08:14:13.97#ibcon#enter sib2, iclass 39, count 0 2006.201.08:14:13.97#ibcon#flushed, iclass 39, count 0 2006.201.08:14:13.97#ibcon#about to write, iclass 39, count 0 2006.201.08:14:13.97#ibcon#wrote, iclass 39, count 0 2006.201.08:14:13.97#ibcon#about to read 3, iclass 39, count 0 2006.201.08:14:14.00#ibcon#read 3, iclass 39, count 0 2006.201.08:14:14.00#ibcon#about to read 4, iclass 39, count 0 2006.201.08:14:14.00#ibcon#read 4, iclass 39, count 0 2006.201.08:14:14.00#ibcon#about to read 5, iclass 39, count 0 2006.201.08:14:14.00#ibcon#read 5, iclass 39, count 0 2006.201.08:14:14.00#ibcon#about to read 6, iclass 39, count 0 2006.201.08:14:14.00#ibcon#read 6, iclass 39, count 0 2006.201.08:14:14.00#ibcon#end of sib2, iclass 39, count 0 2006.201.08:14:14.00#ibcon#*after write, iclass 39, count 0 2006.201.08:14:14.00#ibcon#*before return 0, iclass 39, count 0 2006.201.08:14:14.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:14.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:14.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:14:14.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:14:14.00$vck44/valo=5,734.99 2006.201.08:14:14.00#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.08:14:14.00#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.08:14:14.00#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:14.00#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:14.00#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:14.00#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:14.00#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:14:14.00#ibcon#first serial, iclass 2, count 0 2006.201.08:14:14.00#ibcon#enter sib2, iclass 2, count 0 2006.201.08:14:14.00#ibcon#flushed, iclass 2, count 0 2006.201.08:14:14.00#ibcon#about to write, iclass 2, count 0 2006.201.08:14:14.00#ibcon#wrote, iclass 2, count 0 2006.201.08:14:14.00#ibcon#about to read 3, iclass 2, count 0 2006.201.08:14:14.02#ibcon#read 3, iclass 2, count 0 2006.201.08:14:14.02#ibcon#about to read 4, iclass 2, count 0 2006.201.08:14:14.02#ibcon#read 4, iclass 2, count 0 2006.201.08:14:14.02#ibcon#about to read 5, iclass 2, count 0 2006.201.08:14:14.02#ibcon#read 5, iclass 2, count 0 2006.201.08:14:14.02#ibcon#about to read 6, iclass 2, count 0 2006.201.08:14:14.02#ibcon#read 6, iclass 2, count 0 2006.201.08:14:14.02#ibcon#end of sib2, iclass 2, count 0 2006.201.08:14:14.02#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:14:14.02#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:14:14.02#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:14:14.02#ibcon#*before write, iclass 2, count 0 2006.201.08:14:14.02#ibcon#enter sib2, iclass 2, count 0 2006.201.08:14:14.02#ibcon#flushed, iclass 2, count 0 2006.201.08:14:14.02#ibcon#about to write, iclass 2, count 0 2006.201.08:14:14.02#ibcon#wrote, iclass 2, count 0 2006.201.08:14:14.02#ibcon#about to read 3, iclass 2, count 0 2006.201.08:14:14.06#ibcon#read 3, iclass 2, count 0 2006.201.08:14:14.06#ibcon#about to read 4, iclass 2, count 0 2006.201.08:14:14.06#ibcon#read 4, iclass 2, count 0 2006.201.08:14:14.06#ibcon#about to read 5, iclass 2, count 0 2006.201.08:14:14.06#ibcon#read 5, iclass 2, count 0 2006.201.08:14:14.06#ibcon#about to read 6, iclass 2, count 0 2006.201.08:14:14.06#ibcon#read 6, iclass 2, count 0 2006.201.08:14:14.06#ibcon#end of sib2, iclass 2, count 0 2006.201.08:14:14.06#ibcon#*after write, iclass 2, count 0 2006.201.08:14:14.06#ibcon#*before return 0, iclass 2, count 0 2006.201.08:14:14.06#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:14.06#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:14.06#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:14:14.06#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:14:14.06$vck44/va=5,4 2006.201.08:14:14.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.08:14:14.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.08:14:14.06#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:14.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:14.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:14.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:14.12#ibcon#enter wrdev, iclass 5, count 2 2006.201.08:14:14.12#ibcon#first serial, iclass 5, count 2 2006.201.08:14:14.12#ibcon#enter sib2, iclass 5, count 2 2006.201.08:14:14.12#ibcon#flushed, iclass 5, count 2 2006.201.08:14:14.12#ibcon#about to write, iclass 5, count 2 2006.201.08:14:14.12#ibcon#wrote, iclass 5, count 2 2006.201.08:14:14.12#ibcon#about to read 3, iclass 5, count 2 2006.201.08:14:14.14#ibcon#read 3, iclass 5, count 2 2006.201.08:14:14.14#ibcon#about to read 4, iclass 5, count 2 2006.201.08:14:14.14#ibcon#read 4, iclass 5, count 2 2006.201.08:14:14.14#ibcon#about to read 5, iclass 5, count 2 2006.201.08:14:14.14#ibcon#read 5, iclass 5, count 2 2006.201.08:14:14.14#ibcon#about to read 6, iclass 5, count 2 2006.201.08:14:14.14#ibcon#read 6, iclass 5, count 2 2006.201.08:14:14.14#ibcon#end of sib2, iclass 5, count 2 2006.201.08:14:14.14#ibcon#*mode == 0, iclass 5, count 2 2006.201.08:14:14.14#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.08:14:14.14#ibcon#[25=AT05-04\r\n] 2006.201.08:14:14.14#ibcon#*before write, iclass 5, count 2 2006.201.08:14:14.14#ibcon#enter sib2, iclass 5, count 2 2006.201.08:14:14.14#ibcon#flushed, iclass 5, count 2 2006.201.08:14:14.14#ibcon#about to write, iclass 5, count 2 2006.201.08:14:14.14#ibcon#wrote, iclass 5, count 2 2006.201.08:14:14.14#ibcon#about to read 3, iclass 5, count 2 2006.201.08:14:14.17#ibcon#read 3, iclass 5, count 2 2006.201.08:14:14.17#ibcon#about to read 4, iclass 5, count 2 2006.201.08:14:14.17#ibcon#read 4, iclass 5, count 2 2006.201.08:14:14.17#ibcon#about to read 5, iclass 5, count 2 2006.201.08:14:14.17#ibcon#read 5, iclass 5, count 2 2006.201.08:14:14.17#ibcon#about to read 6, iclass 5, count 2 2006.201.08:14:14.17#ibcon#read 6, iclass 5, count 2 2006.201.08:14:14.17#ibcon#end of sib2, iclass 5, count 2 2006.201.08:14:14.17#ibcon#*after write, iclass 5, count 2 2006.201.08:14:14.17#ibcon#*before return 0, iclass 5, count 2 2006.201.08:14:14.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:14.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:14.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.08:14:14.17#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:14.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:14.25#abcon#<5=/04 2.5 4.6 23.21 871003.2\r\n> 2006.201.08:14:14.27#abcon#{5=INTERFACE CLEAR} 2006.201.08:14:14.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:14.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:14.29#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:14:14.29#ibcon#first serial, iclass 5, count 0 2006.201.08:14:14.29#ibcon#enter sib2, iclass 5, count 0 2006.201.08:14:14.29#ibcon#flushed, iclass 5, count 0 2006.201.08:14:14.29#ibcon#about to write, iclass 5, count 0 2006.201.08:14:14.29#ibcon#wrote, iclass 5, count 0 2006.201.08:14:14.29#ibcon#about to read 3, iclass 5, count 0 2006.201.08:14:14.31#ibcon#read 3, iclass 5, count 0 2006.201.08:14:14.31#ibcon#about to read 4, iclass 5, count 0 2006.201.08:14:14.31#ibcon#read 4, iclass 5, count 0 2006.201.08:14:14.31#ibcon#about to read 5, iclass 5, count 0 2006.201.08:14:14.31#ibcon#read 5, iclass 5, count 0 2006.201.08:14:14.31#ibcon#about to read 6, iclass 5, count 0 2006.201.08:14:14.31#ibcon#read 6, iclass 5, count 0 2006.201.08:14:14.31#ibcon#end of sib2, iclass 5, count 0 2006.201.08:14:14.31#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:14:14.31#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:14:14.31#ibcon#[25=USB\r\n] 2006.201.08:14:14.31#ibcon#*before write, iclass 5, count 0 2006.201.08:14:14.31#ibcon#enter sib2, iclass 5, count 0 2006.201.08:14:14.31#ibcon#flushed, iclass 5, count 0 2006.201.08:14:14.31#ibcon#about to write, iclass 5, count 0 2006.201.08:14:14.31#ibcon#wrote, iclass 5, count 0 2006.201.08:14:14.31#ibcon#about to read 3, iclass 5, count 0 2006.201.08:14:14.33#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:14:14.34#ibcon#read 3, iclass 5, count 0 2006.201.08:14:14.34#ibcon#about to read 4, iclass 5, count 0 2006.201.08:14:14.34#ibcon#read 4, iclass 5, count 0 2006.201.08:14:14.34#ibcon#about to read 5, iclass 5, count 0 2006.201.08:14:14.34#ibcon#read 5, iclass 5, count 0 2006.201.08:14:14.34#ibcon#about to read 6, iclass 5, count 0 2006.201.08:14:14.34#ibcon#read 6, iclass 5, count 0 2006.201.08:14:14.34#ibcon#end of sib2, iclass 5, count 0 2006.201.08:14:14.34#ibcon#*after write, iclass 5, count 0 2006.201.08:14:14.34#ibcon#*before return 0, iclass 5, count 0 2006.201.08:14:14.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:14.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:14.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:14:14.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:14:14.34$vck44/valo=6,814.99 2006.201.08:14:14.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.08:14:14.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.08:14:14.34#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:14.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:14.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:14.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:14.34#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:14:14.34#ibcon#first serial, iclass 13, count 0 2006.201.08:14:14.34#ibcon#enter sib2, iclass 13, count 0 2006.201.08:14:14.34#ibcon#flushed, iclass 13, count 0 2006.201.08:14:14.34#ibcon#about to write, iclass 13, count 0 2006.201.08:14:14.34#ibcon#wrote, iclass 13, count 0 2006.201.08:14:14.34#ibcon#about to read 3, iclass 13, count 0 2006.201.08:14:14.36#ibcon#read 3, iclass 13, count 0 2006.201.08:14:14.36#ibcon#about to read 4, iclass 13, count 0 2006.201.08:14:14.36#ibcon#read 4, iclass 13, count 0 2006.201.08:14:14.36#ibcon#about to read 5, iclass 13, count 0 2006.201.08:14:14.36#ibcon#read 5, iclass 13, count 0 2006.201.08:14:14.36#ibcon#about to read 6, iclass 13, count 0 2006.201.08:14:14.36#ibcon#read 6, iclass 13, count 0 2006.201.08:14:14.36#ibcon#end of sib2, iclass 13, count 0 2006.201.08:14:14.36#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:14:14.36#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:14:14.36#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:14:14.36#ibcon#*before write, iclass 13, count 0 2006.201.08:14:14.36#ibcon#enter sib2, iclass 13, count 0 2006.201.08:14:14.36#ibcon#flushed, iclass 13, count 0 2006.201.08:14:14.36#ibcon#about to write, iclass 13, count 0 2006.201.08:14:14.36#ibcon#wrote, iclass 13, count 0 2006.201.08:14:14.36#ibcon#about to read 3, iclass 13, count 0 2006.201.08:14:14.40#ibcon#read 3, iclass 13, count 0 2006.201.08:14:14.40#ibcon#about to read 4, iclass 13, count 0 2006.201.08:14:14.40#ibcon#read 4, iclass 13, count 0 2006.201.08:14:14.40#ibcon#about to read 5, iclass 13, count 0 2006.201.08:14:14.40#ibcon#read 5, iclass 13, count 0 2006.201.08:14:14.40#ibcon#about to read 6, iclass 13, count 0 2006.201.08:14:14.40#ibcon#read 6, iclass 13, count 0 2006.201.08:14:14.40#ibcon#end of sib2, iclass 13, count 0 2006.201.08:14:14.40#ibcon#*after write, iclass 13, count 0 2006.201.08:14:14.40#ibcon#*before return 0, iclass 13, count 0 2006.201.08:14:14.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:14.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:14.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:14:14.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:14:14.40$vck44/va=6,5 2006.201.08:14:14.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.08:14:14.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.08:14:14.40#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:14.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:14.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:14.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:14.46#ibcon#enter wrdev, iclass 15, count 2 2006.201.08:14:14.46#ibcon#first serial, iclass 15, count 2 2006.201.08:14:14.46#ibcon#enter sib2, iclass 15, count 2 2006.201.08:14:14.46#ibcon#flushed, iclass 15, count 2 2006.201.08:14:14.46#ibcon#about to write, iclass 15, count 2 2006.201.08:14:14.46#ibcon#wrote, iclass 15, count 2 2006.201.08:14:14.46#ibcon#about to read 3, iclass 15, count 2 2006.201.08:14:14.48#ibcon#read 3, iclass 15, count 2 2006.201.08:14:14.48#ibcon#about to read 4, iclass 15, count 2 2006.201.08:14:14.48#ibcon#read 4, iclass 15, count 2 2006.201.08:14:14.48#ibcon#about to read 5, iclass 15, count 2 2006.201.08:14:14.48#ibcon#read 5, iclass 15, count 2 2006.201.08:14:14.48#ibcon#about to read 6, iclass 15, count 2 2006.201.08:14:14.48#ibcon#read 6, iclass 15, count 2 2006.201.08:14:14.48#ibcon#end of sib2, iclass 15, count 2 2006.201.08:14:14.48#ibcon#*mode == 0, iclass 15, count 2 2006.201.08:14:14.48#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.08:14:14.48#ibcon#[25=AT06-05\r\n] 2006.201.08:14:14.48#ibcon#*before write, iclass 15, count 2 2006.201.08:14:14.48#ibcon#enter sib2, iclass 15, count 2 2006.201.08:14:14.48#ibcon#flushed, iclass 15, count 2 2006.201.08:14:14.48#ibcon#about to write, iclass 15, count 2 2006.201.08:14:14.48#ibcon#wrote, iclass 15, count 2 2006.201.08:14:14.48#ibcon#about to read 3, iclass 15, count 2 2006.201.08:14:14.51#ibcon#read 3, iclass 15, count 2 2006.201.08:14:14.51#ibcon#about to read 4, iclass 15, count 2 2006.201.08:14:14.51#ibcon#read 4, iclass 15, count 2 2006.201.08:14:14.51#ibcon#about to read 5, iclass 15, count 2 2006.201.08:14:14.51#ibcon#read 5, iclass 15, count 2 2006.201.08:14:14.51#ibcon#about to read 6, iclass 15, count 2 2006.201.08:14:14.51#ibcon#read 6, iclass 15, count 2 2006.201.08:14:14.51#ibcon#end of sib2, iclass 15, count 2 2006.201.08:14:14.51#ibcon#*after write, iclass 15, count 2 2006.201.08:14:14.51#ibcon#*before return 0, iclass 15, count 2 2006.201.08:14:14.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:14.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:14.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.08:14:14.51#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:14.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:14.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:14.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:14.63#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:14:14.63#ibcon#first serial, iclass 15, count 0 2006.201.08:14:14.63#ibcon#enter sib2, iclass 15, count 0 2006.201.08:14:14.63#ibcon#flushed, iclass 15, count 0 2006.201.08:14:14.63#ibcon#about to write, iclass 15, count 0 2006.201.08:14:14.63#ibcon#wrote, iclass 15, count 0 2006.201.08:14:14.63#ibcon#about to read 3, iclass 15, count 0 2006.201.08:14:14.65#ibcon#read 3, iclass 15, count 0 2006.201.08:14:14.65#ibcon#about to read 4, iclass 15, count 0 2006.201.08:14:14.65#ibcon#read 4, iclass 15, count 0 2006.201.08:14:14.65#ibcon#about to read 5, iclass 15, count 0 2006.201.08:14:14.65#ibcon#read 5, iclass 15, count 0 2006.201.08:14:14.65#ibcon#about to read 6, iclass 15, count 0 2006.201.08:14:14.65#ibcon#read 6, iclass 15, count 0 2006.201.08:14:14.65#ibcon#end of sib2, iclass 15, count 0 2006.201.08:14:14.65#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:14:14.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:14:14.65#ibcon#[25=USB\r\n] 2006.201.08:14:14.65#ibcon#*before write, iclass 15, count 0 2006.201.08:14:14.65#ibcon#enter sib2, iclass 15, count 0 2006.201.08:14:14.65#ibcon#flushed, iclass 15, count 0 2006.201.08:14:14.65#ibcon#about to write, iclass 15, count 0 2006.201.08:14:14.65#ibcon#wrote, iclass 15, count 0 2006.201.08:14:14.65#ibcon#about to read 3, iclass 15, count 0 2006.201.08:14:14.68#ibcon#read 3, iclass 15, count 0 2006.201.08:14:14.68#ibcon#about to read 4, iclass 15, count 0 2006.201.08:14:14.68#ibcon#read 4, iclass 15, count 0 2006.201.08:14:14.68#ibcon#about to read 5, iclass 15, count 0 2006.201.08:14:14.68#ibcon#read 5, iclass 15, count 0 2006.201.08:14:14.68#ibcon#about to read 6, iclass 15, count 0 2006.201.08:14:14.68#ibcon#read 6, iclass 15, count 0 2006.201.08:14:14.68#ibcon#end of sib2, iclass 15, count 0 2006.201.08:14:14.68#ibcon#*after write, iclass 15, count 0 2006.201.08:14:14.68#ibcon#*before return 0, iclass 15, count 0 2006.201.08:14:14.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:14.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:14.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:14:14.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:14:14.68$vck44/valo=7,864.99 2006.201.08:14:14.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.08:14:14.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.08:14:14.68#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:14.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:14.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:14.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:14.68#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:14:14.68#ibcon#first serial, iclass 17, count 0 2006.201.08:14:14.68#ibcon#enter sib2, iclass 17, count 0 2006.201.08:14:14.68#ibcon#flushed, iclass 17, count 0 2006.201.08:14:14.68#ibcon#about to write, iclass 17, count 0 2006.201.08:14:14.68#ibcon#wrote, iclass 17, count 0 2006.201.08:14:14.68#ibcon#about to read 3, iclass 17, count 0 2006.201.08:14:14.70#ibcon#read 3, iclass 17, count 0 2006.201.08:14:14.70#ibcon#about to read 4, iclass 17, count 0 2006.201.08:14:14.70#ibcon#read 4, iclass 17, count 0 2006.201.08:14:14.70#ibcon#about to read 5, iclass 17, count 0 2006.201.08:14:14.70#ibcon#read 5, iclass 17, count 0 2006.201.08:14:14.70#ibcon#about to read 6, iclass 17, count 0 2006.201.08:14:14.70#ibcon#read 6, iclass 17, count 0 2006.201.08:14:14.70#ibcon#end of sib2, iclass 17, count 0 2006.201.08:14:14.70#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:14:14.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:14:14.70#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:14:14.70#ibcon#*before write, iclass 17, count 0 2006.201.08:14:14.70#ibcon#enter sib2, iclass 17, count 0 2006.201.08:14:14.70#ibcon#flushed, iclass 17, count 0 2006.201.08:14:14.70#ibcon#about to write, iclass 17, count 0 2006.201.08:14:14.70#ibcon#wrote, iclass 17, count 0 2006.201.08:14:14.70#ibcon#about to read 3, iclass 17, count 0 2006.201.08:14:14.74#ibcon#read 3, iclass 17, count 0 2006.201.08:14:14.74#ibcon#about to read 4, iclass 17, count 0 2006.201.08:14:14.74#ibcon#read 4, iclass 17, count 0 2006.201.08:14:14.74#ibcon#about to read 5, iclass 17, count 0 2006.201.08:14:14.74#ibcon#read 5, iclass 17, count 0 2006.201.08:14:14.74#ibcon#about to read 6, iclass 17, count 0 2006.201.08:14:14.74#ibcon#read 6, iclass 17, count 0 2006.201.08:14:14.74#ibcon#end of sib2, iclass 17, count 0 2006.201.08:14:14.74#ibcon#*after write, iclass 17, count 0 2006.201.08:14:14.74#ibcon#*before return 0, iclass 17, count 0 2006.201.08:14:14.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:14.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:14.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:14:14.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:14:14.74$vck44/va=7,5 2006.201.08:14:14.74#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.08:14:14.74#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.08:14:14.74#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:14.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:14.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:14.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:14.80#ibcon#enter wrdev, iclass 19, count 2 2006.201.08:14:14.80#ibcon#first serial, iclass 19, count 2 2006.201.08:14:14.80#ibcon#enter sib2, iclass 19, count 2 2006.201.08:14:14.80#ibcon#flushed, iclass 19, count 2 2006.201.08:14:14.80#ibcon#about to write, iclass 19, count 2 2006.201.08:14:14.80#ibcon#wrote, iclass 19, count 2 2006.201.08:14:14.80#ibcon#about to read 3, iclass 19, count 2 2006.201.08:14:14.82#ibcon#read 3, iclass 19, count 2 2006.201.08:14:14.82#ibcon#about to read 4, iclass 19, count 2 2006.201.08:14:14.82#ibcon#read 4, iclass 19, count 2 2006.201.08:14:14.82#ibcon#about to read 5, iclass 19, count 2 2006.201.08:14:14.82#ibcon#read 5, iclass 19, count 2 2006.201.08:14:14.82#ibcon#about to read 6, iclass 19, count 2 2006.201.08:14:14.82#ibcon#read 6, iclass 19, count 2 2006.201.08:14:14.82#ibcon#end of sib2, iclass 19, count 2 2006.201.08:14:14.82#ibcon#*mode == 0, iclass 19, count 2 2006.201.08:14:14.82#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.08:14:14.82#ibcon#[25=AT07-05\r\n] 2006.201.08:14:14.82#ibcon#*before write, iclass 19, count 2 2006.201.08:14:14.82#ibcon#enter sib2, iclass 19, count 2 2006.201.08:14:14.82#ibcon#flushed, iclass 19, count 2 2006.201.08:14:14.82#ibcon#about to write, iclass 19, count 2 2006.201.08:14:14.82#ibcon#wrote, iclass 19, count 2 2006.201.08:14:14.82#ibcon#about to read 3, iclass 19, count 2 2006.201.08:14:14.85#ibcon#read 3, iclass 19, count 2 2006.201.08:14:14.85#ibcon#about to read 4, iclass 19, count 2 2006.201.08:14:14.85#ibcon#read 4, iclass 19, count 2 2006.201.08:14:14.85#ibcon#about to read 5, iclass 19, count 2 2006.201.08:14:14.85#ibcon#read 5, iclass 19, count 2 2006.201.08:14:14.85#ibcon#about to read 6, iclass 19, count 2 2006.201.08:14:14.85#ibcon#read 6, iclass 19, count 2 2006.201.08:14:14.85#ibcon#end of sib2, iclass 19, count 2 2006.201.08:14:14.85#ibcon#*after write, iclass 19, count 2 2006.201.08:14:14.85#ibcon#*before return 0, iclass 19, count 2 2006.201.08:14:14.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:14.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:14.85#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.08:14:14.85#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:14.85#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:14.97#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:14.97#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:14.97#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:14:14.97#ibcon#first serial, iclass 19, count 0 2006.201.08:14:14.97#ibcon#enter sib2, iclass 19, count 0 2006.201.08:14:14.97#ibcon#flushed, iclass 19, count 0 2006.201.08:14:14.97#ibcon#about to write, iclass 19, count 0 2006.201.08:14:14.97#ibcon#wrote, iclass 19, count 0 2006.201.08:14:14.97#ibcon#about to read 3, iclass 19, count 0 2006.201.08:14:14.99#ibcon#read 3, iclass 19, count 0 2006.201.08:14:14.99#ibcon#about to read 4, iclass 19, count 0 2006.201.08:14:14.99#ibcon#read 4, iclass 19, count 0 2006.201.08:14:14.99#ibcon#about to read 5, iclass 19, count 0 2006.201.08:14:14.99#ibcon#read 5, iclass 19, count 0 2006.201.08:14:14.99#ibcon#about to read 6, iclass 19, count 0 2006.201.08:14:14.99#ibcon#read 6, iclass 19, count 0 2006.201.08:14:14.99#ibcon#end of sib2, iclass 19, count 0 2006.201.08:14:14.99#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:14:14.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:14:14.99#ibcon#[25=USB\r\n] 2006.201.08:14:14.99#ibcon#*before write, iclass 19, count 0 2006.201.08:14:14.99#ibcon#enter sib2, iclass 19, count 0 2006.201.08:14:14.99#ibcon#flushed, iclass 19, count 0 2006.201.08:14:14.99#ibcon#about to write, iclass 19, count 0 2006.201.08:14:14.99#ibcon#wrote, iclass 19, count 0 2006.201.08:14:14.99#ibcon#about to read 3, iclass 19, count 0 2006.201.08:14:15.02#ibcon#read 3, iclass 19, count 0 2006.201.08:14:15.02#ibcon#about to read 4, iclass 19, count 0 2006.201.08:14:15.02#ibcon#read 4, iclass 19, count 0 2006.201.08:14:15.02#ibcon#about to read 5, iclass 19, count 0 2006.201.08:14:15.02#ibcon#read 5, iclass 19, count 0 2006.201.08:14:15.02#ibcon#about to read 6, iclass 19, count 0 2006.201.08:14:15.02#ibcon#read 6, iclass 19, count 0 2006.201.08:14:15.02#ibcon#end of sib2, iclass 19, count 0 2006.201.08:14:15.02#ibcon#*after write, iclass 19, count 0 2006.201.08:14:15.02#ibcon#*before return 0, iclass 19, count 0 2006.201.08:14:15.02#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:15.02#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:15.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:14:15.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:14:15.02$vck44/valo=8,884.99 2006.201.08:14:15.02#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.08:14:15.02#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.08:14:15.02#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:15.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:15.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:15.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:15.02#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:14:15.02#ibcon#first serial, iclass 21, count 0 2006.201.08:14:15.02#ibcon#enter sib2, iclass 21, count 0 2006.201.08:14:15.02#ibcon#flushed, iclass 21, count 0 2006.201.08:14:15.02#ibcon#about to write, iclass 21, count 0 2006.201.08:14:15.02#ibcon#wrote, iclass 21, count 0 2006.201.08:14:15.02#ibcon#about to read 3, iclass 21, count 0 2006.201.08:14:15.04#ibcon#read 3, iclass 21, count 0 2006.201.08:14:15.04#ibcon#about to read 4, iclass 21, count 0 2006.201.08:14:15.04#ibcon#read 4, iclass 21, count 0 2006.201.08:14:15.04#ibcon#about to read 5, iclass 21, count 0 2006.201.08:14:15.04#ibcon#read 5, iclass 21, count 0 2006.201.08:14:15.04#ibcon#about to read 6, iclass 21, count 0 2006.201.08:14:15.04#ibcon#read 6, iclass 21, count 0 2006.201.08:14:15.04#ibcon#end of sib2, iclass 21, count 0 2006.201.08:14:15.04#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:14:15.04#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:14:15.04#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:14:15.04#ibcon#*before write, iclass 21, count 0 2006.201.08:14:15.04#ibcon#enter sib2, iclass 21, count 0 2006.201.08:14:15.04#ibcon#flushed, iclass 21, count 0 2006.201.08:14:15.04#ibcon#about to write, iclass 21, count 0 2006.201.08:14:15.04#ibcon#wrote, iclass 21, count 0 2006.201.08:14:15.04#ibcon#about to read 3, iclass 21, count 0 2006.201.08:14:15.08#ibcon#read 3, iclass 21, count 0 2006.201.08:14:15.08#ibcon#about to read 4, iclass 21, count 0 2006.201.08:14:15.08#ibcon#read 4, iclass 21, count 0 2006.201.08:14:15.08#ibcon#about to read 5, iclass 21, count 0 2006.201.08:14:15.08#ibcon#read 5, iclass 21, count 0 2006.201.08:14:15.08#ibcon#about to read 6, iclass 21, count 0 2006.201.08:14:15.08#ibcon#read 6, iclass 21, count 0 2006.201.08:14:15.08#ibcon#end of sib2, iclass 21, count 0 2006.201.08:14:15.08#ibcon#*after write, iclass 21, count 0 2006.201.08:14:15.08#ibcon#*before return 0, iclass 21, count 0 2006.201.08:14:15.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:15.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:15.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:14:15.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:14:15.08$vck44/va=8,4 2006.201.08:14:15.08#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.08:14:15.08#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.08:14:15.08#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:15.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:14:15.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:14:15.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:14:15.14#ibcon#enter wrdev, iclass 23, count 2 2006.201.08:14:15.14#ibcon#first serial, iclass 23, count 2 2006.201.08:14:15.14#ibcon#enter sib2, iclass 23, count 2 2006.201.08:14:15.14#ibcon#flushed, iclass 23, count 2 2006.201.08:14:15.14#ibcon#about to write, iclass 23, count 2 2006.201.08:14:15.14#ibcon#wrote, iclass 23, count 2 2006.201.08:14:15.14#ibcon#about to read 3, iclass 23, count 2 2006.201.08:14:15.16#ibcon#read 3, iclass 23, count 2 2006.201.08:14:15.16#ibcon#about to read 4, iclass 23, count 2 2006.201.08:14:15.16#ibcon#read 4, iclass 23, count 2 2006.201.08:14:15.16#ibcon#about to read 5, iclass 23, count 2 2006.201.08:14:15.16#ibcon#read 5, iclass 23, count 2 2006.201.08:14:15.16#ibcon#about to read 6, iclass 23, count 2 2006.201.08:14:15.16#ibcon#read 6, iclass 23, count 2 2006.201.08:14:15.16#ibcon#end of sib2, iclass 23, count 2 2006.201.08:14:15.16#ibcon#*mode == 0, iclass 23, count 2 2006.201.08:14:15.16#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.08:14:15.16#ibcon#[25=AT08-04\r\n] 2006.201.08:14:15.16#ibcon#*before write, iclass 23, count 2 2006.201.08:14:15.16#ibcon#enter sib2, iclass 23, count 2 2006.201.08:14:15.16#ibcon#flushed, iclass 23, count 2 2006.201.08:14:15.16#ibcon#about to write, iclass 23, count 2 2006.201.08:14:15.16#ibcon#wrote, iclass 23, count 2 2006.201.08:14:15.16#ibcon#about to read 3, iclass 23, count 2 2006.201.08:14:15.19#ibcon#read 3, iclass 23, count 2 2006.201.08:14:15.19#ibcon#about to read 4, iclass 23, count 2 2006.201.08:14:15.19#ibcon#read 4, iclass 23, count 2 2006.201.08:14:15.19#ibcon#about to read 5, iclass 23, count 2 2006.201.08:14:15.19#ibcon#read 5, iclass 23, count 2 2006.201.08:14:15.19#ibcon#about to read 6, iclass 23, count 2 2006.201.08:14:15.19#ibcon#read 6, iclass 23, count 2 2006.201.08:14:15.19#ibcon#end of sib2, iclass 23, count 2 2006.201.08:14:15.19#ibcon#*after write, iclass 23, count 2 2006.201.08:14:15.19#ibcon#*before return 0, iclass 23, count 2 2006.201.08:14:15.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:14:15.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:14:15.19#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.08:14:15.19#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:15.19#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:14:15.31#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:14:15.31#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:14:15.31#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:14:15.31#ibcon#first serial, iclass 23, count 0 2006.201.08:14:15.31#ibcon#enter sib2, iclass 23, count 0 2006.201.08:14:15.31#ibcon#flushed, iclass 23, count 0 2006.201.08:14:15.31#ibcon#about to write, iclass 23, count 0 2006.201.08:14:15.31#ibcon#wrote, iclass 23, count 0 2006.201.08:14:15.31#ibcon#about to read 3, iclass 23, count 0 2006.201.08:14:15.33#ibcon#read 3, iclass 23, count 0 2006.201.08:14:15.33#ibcon#about to read 4, iclass 23, count 0 2006.201.08:14:15.33#ibcon#read 4, iclass 23, count 0 2006.201.08:14:15.33#ibcon#about to read 5, iclass 23, count 0 2006.201.08:14:15.33#ibcon#read 5, iclass 23, count 0 2006.201.08:14:15.33#ibcon#about to read 6, iclass 23, count 0 2006.201.08:14:15.33#ibcon#read 6, iclass 23, count 0 2006.201.08:14:15.33#ibcon#end of sib2, iclass 23, count 0 2006.201.08:14:15.33#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:14:15.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:14:15.33#ibcon#[25=USB\r\n] 2006.201.08:14:15.33#ibcon#*before write, iclass 23, count 0 2006.201.08:14:15.33#ibcon#enter sib2, iclass 23, count 0 2006.201.08:14:15.33#ibcon#flushed, iclass 23, count 0 2006.201.08:14:15.33#ibcon#about to write, iclass 23, count 0 2006.201.08:14:15.33#ibcon#wrote, iclass 23, count 0 2006.201.08:14:15.33#ibcon#about to read 3, iclass 23, count 0 2006.201.08:14:15.36#ibcon#read 3, iclass 23, count 0 2006.201.08:14:15.36#ibcon#about to read 4, iclass 23, count 0 2006.201.08:14:15.36#ibcon#read 4, iclass 23, count 0 2006.201.08:14:15.36#ibcon#about to read 5, iclass 23, count 0 2006.201.08:14:15.36#ibcon#read 5, iclass 23, count 0 2006.201.08:14:15.36#ibcon#about to read 6, iclass 23, count 0 2006.201.08:14:15.36#ibcon#read 6, iclass 23, count 0 2006.201.08:14:15.36#ibcon#end of sib2, iclass 23, count 0 2006.201.08:14:15.36#ibcon#*after write, iclass 23, count 0 2006.201.08:14:15.36#ibcon#*before return 0, iclass 23, count 0 2006.201.08:14:15.36#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:14:15.36#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:14:15.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:14:15.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:14:15.36$vck44/vblo=1,629.99 2006.201.08:14:15.36#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.08:14:15.36#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.08:14:15.36#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:15.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:15.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:15.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:15.36#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:14:15.36#ibcon#first serial, iclass 25, count 0 2006.201.08:14:15.36#ibcon#enter sib2, iclass 25, count 0 2006.201.08:14:15.36#ibcon#flushed, iclass 25, count 0 2006.201.08:14:15.36#ibcon#about to write, iclass 25, count 0 2006.201.08:14:15.36#ibcon#wrote, iclass 25, count 0 2006.201.08:14:15.36#ibcon#about to read 3, iclass 25, count 0 2006.201.08:14:15.38#ibcon#read 3, iclass 25, count 0 2006.201.08:14:15.38#ibcon#about to read 4, iclass 25, count 0 2006.201.08:14:15.38#ibcon#read 4, iclass 25, count 0 2006.201.08:14:15.38#ibcon#about to read 5, iclass 25, count 0 2006.201.08:14:15.38#ibcon#read 5, iclass 25, count 0 2006.201.08:14:15.38#ibcon#about to read 6, iclass 25, count 0 2006.201.08:14:15.38#ibcon#read 6, iclass 25, count 0 2006.201.08:14:15.38#ibcon#end of sib2, iclass 25, count 0 2006.201.08:14:15.38#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:14:15.38#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:14:15.38#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:14:15.38#ibcon#*before write, iclass 25, count 0 2006.201.08:14:15.38#ibcon#enter sib2, iclass 25, count 0 2006.201.08:14:15.38#ibcon#flushed, iclass 25, count 0 2006.201.08:14:15.38#ibcon#about to write, iclass 25, count 0 2006.201.08:14:15.38#ibcon#wrote, iclass 25, count 0 2006.201.08:14:15.38#ibcon#about to read 3, iclass 25, count 0 2006.201.08:14:15.42#ibcon#read 3, iclass 25, count 0 2006.201.08:14:15.42#ibcon#about to read 4, iclass 25, count 0 2006.201.08:14:15.42#ibcon#read 4, iclass 25, count 0 2006.201.08:14:15.42#ibcon#about to read 5, iclass 25, count 0 2006.201.08:14:15.42#ibcon#read 5, iclass 25, count 0 2006.201.08:14:15.42#ibcon#about to read 6, iclass 25, count 0 2006.201.08:14:15.42#ibcon#read 6, iclass 25, count 0 2006.201.08:14:15.42#ibcon#end of sib2, iclass 25, count 0 2006.201.08:14:15.42#ibcon#*after write, iclass 25, count 0 2006.201.08:14:15.42#ibcon#*before return 0, iclass 25, count 0 2006.201.08:14:15.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:15.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:14:15.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:14:15.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:14:15.42$vck44/vb=1,4 2006.201.08:14:15.42#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.08:14:15.42#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.08:14:15.42#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:15.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:15.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:15.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:15.42#ibcon#enter wrdev, iclass 27, count 2 2006.201.08:14:15.42#ibcon#first serial, iclass 27, count 2 2006.201.08:14:15.42#ibcon#enter sib2, iclass 27, count 2 2006.201.08:14:15.42#ibcon#flushed, iclass 27, count 2 2006.201.08:14:15.42#ibcon#about to write, iclass 27, count 2 2006.201.08:14:15.42#ibcon#wrote, iclass 27, count 2 2006.201.08:14:15.42#ibcon#about to read 3, iclass 27, count 2 2006.201.08:14:15.44#ibcon#read 3, iclass 27, count 2 2006.201.08:14:15.44#ibcon#about to read 4, iclass 27, count 2 2006.201.08:14:15.44#ibcon#read 4, iclass 27, count 2 2006.201.08:14:15.44#ibcon#about to read 5, iclass 27, count 2 2006.201.08:14:15.44#ibcon#read 5, iclass 27, count 2 2006.201.08:14:15.44#ibcon#about to read 6, iclass 27, count 2 2006.201.08:14:15.44#ibcon#read 6, iclass 27, count 2 2006.201.08:14:15.44#ibcon#end of sib2, iclass 27, count 2 2006.201.08:14:15.44#ibcon#*mode == 0, iclass 27, count 2 2006.201.08:14:15.44#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.08:14:15.44#ibcon#[27=AT01-04\r\n] 2006.201.08:14:15.44#ibcon#*before write, iclass 27, count 2 2006.201.08:14:15.44#ibcon#enter sib2, iclass 27, count 2 2006.201.08:14:15.44#ibcon#flushed, iclass 27, count 2 2006.201.08:14:15.44#ibcon#about to write, iclass 27, count 2 2006.201.08:14:15.44#ibcon#wrote, iclass 27, count 2 2006.201.08:14:15.44#ibcon#about to read 3, iclass 27, count 2 2006.201.08:14:15.47#ibcon#read 3, iclass 27, count 2 2006.201.08:14:15.47#ibcon#about to read 4, iclass 27, count 2 2006.201.08:14:15.47#ibcon#read 4, iclass 27, count 2 2006.201.08:14:15.47#ibcon#about to read 5, iclass 27, count 2 2006.201.08:14:15.47#ibcon#read 5, iclass 27, count 2 2006.201.08:14:15.47#ibcon#about to read 6, iclass 27, count 2 2006.201.08:14:15.47#ibcon#read 6, iclass 27, count 2 2006.201.08:14:15.47#ibcon#end of sib2, iclass 27, count 2 2006.201.08:14:15.47#ibcon#*after write, iclass 27, count 2 2006.201.08:14:15.47#ibcon#*before return 0, iclass 27, count 2 2006.201.08:14:15.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:15.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:14:15.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.08:14:15.47#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:15.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:15.59#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:15.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:15.59#ibcon#enter wrdev, iclass 27, count 0 2006.201.08:14:15.59#ibcon#first serial, iclass 27, count 0 2006.201.08:14:15.59#ibcon#enter sib2, iclass 27, count 0 2006.201.08:14:15.59#ibcon#flushed, iclass 27, count 0 2006.201.08:14:15.59#ibcon#about to write, iclass 27, count 0 2006.201.08:14:15.59#ibcon#wrote, iclass 27, count 0 2006.201.08:14:15.59#ibcon#about to read 3, iclass 27, count 0 2006.201.08:14:15.61#ibcon#read 3, iclass 27, count 0 2006.201.08:14:15.61#ibcon#about to read 4, iclass 27, count 0 2006.201.08:14:15.61#ibcon#read 4, iclass 27, count 0 2006.201.08:14:15.61#ibcon#about to read 5, iclass 27, count 0 2006.201.08:14:15.61#ibcon#read 5, iclass 27, count 0 2006.201.08:14:15.61#ibcon#about to read 6, iclass 27, count 0 2006.201.08:14:15.61#ibcon#read 6, iclass 27, count 0 2006.201.08:14:15.61#ibcon#end of sib2, iclass 27, count 0 2006.201.08:14:15.61#ibcon#*mode == 0, iclass 27, count 0 2006.201.08:14:15.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.08:14:15.61#ibcon#[27=USB\r\n] 2006.201.08:14:15.61#ibcon#*before write, iclass 27, count 0 2006.201.08:14:15.61#ibcon#enter sib2, iclass 27, count 0 2006.201.08:14:15.61#ibcon#flushed, iclass 27, count 0 2006.201.08:14:15.61#ibcon#about to write, iclass 27, count 0 2006.201.08:14:15.61#ibcon#wrote, iclass 27, count 0 2006.201.08:14:15.61#ibcon#about to read 3, iclass 27, count 0 2006.201.08:14:15.64#ibcon#read 3, iclass 27, count 0 2006.201.08:14:15.64#ibcon#about to read 4, iclass 27, count 0 2006.201.08:14:15.64#ibcon#read 4, iclass 27, count 0 2006.201.08:14:15.64#ibcon#about to read 5, iclass 27, count 0 2006.201.08:14:15.64#ibcon#read 5, iclass 27, count 0 2006.201.08:14:15.64#ibcon#about to read 6, iclass 27, count 0 2006.201.08:14:15.64#ibcon#read 6, iclass 27, count 0 2006.201.08:14:15.64#ibcon#end of sib2, iclass 27, count 0 2006.201.08:14:15.64#ibcon#*after write, iclass 27, count 0 2006.201.08:14:15.64#ibcon#*before return 0, iclass 27, count 0 2006.201.08:14:15.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:15.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:14:15.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.08:14:15.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.08:14:15.64$vck44/vblo=2,634.99 2006.201.08:14:15.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.08:14:15.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.08:14:15.64#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:15.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:15.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:15.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:15.64#ibcon#enter wrdev, iclass 29, count 0 2006.201.08:14:15.64#ibcon#first serial, iclass 29, count 0 2006.201.08:14:15.64#ibcon#enter sib2, iclass 29, count 0 2006.201.08:14:15.64#ibcon#flushed, iclass 29, count 0 2006.201.08:14:15.64#ibcon#about to write, iclass 29, count 0 2006.201.08:14:15.64#ibcon#wrote, iclass 29, count 0 2006.201.08:14:15.64#ibcon#about to read 3, iclass 29, count 0 2006.201.08:14:15.66#ibcon#read 3, iclass 29, count 0 2006.201.08:14:15.66#ibcon#about to read 4, iclass 29, count 0 2006.201.08:14:15.66#ibcon#read 4, iclass 29, count 0 2006.201.08:14:15.66#ibcon#about to read 5, iclass 29, count 0 2006.201.08:14:15.66#ibcon#read 5, iclass 29, count 0 2006.201.08:14:15.66#ibcon#about to read 6, iclass 29, count 0 2006.201.08:14:15.66#ibcon#read 6, iclass 29, count 0 2006.201.08:14:15.66#ibcon#end of sib2, iclass 29, count 0 2006.201.08:14:15.66#ibcon#*mode == 0, iclass 29, count 0 2006.201.08:14:15.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.08:14:15.66#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:14:15.66#ibcon#*before write, iclass 29, count 0 2006.201.08:14:15.66#ibcon#enter sib2, iclass 29, count 0 2006.201.08:14:15.66#ibcon#flushed, iclass 29, count 0 2006.201.08:14:15.66#ibcon#about to write, iclass 29, count 0 2006.201.08:14:15.66#ibcon#wrote, iclass 29, count 0 2006.201.08:14:15.66#ibcon#about to read 3, iclass 29, count 0 2006.201.08:14:15.70#ibcon#read 3, iclass 29, count 0 2006.201.08:14:15.70#ibcon#about to read 4, iclass 29, count 0 2006.201.08:14:15.70#ibcon#read 4, iclass 29, count 0 2006.201.08:14:15.70#ibcon#about to read 5, iclass 29, count 0 2006.201.08:14:15.70#ibcon#read 5, iclass 29, count 0 2006.201.08:14:15.70#ibcon#about to read 6, iclass 29, count 0 2006.201.08:14:15.70#ibcon#read 6, iclass 29, count 0 2006.201.08:14:15.70#ibcon#end of sib2, iclass 29, count 0 2006.201.08:14:15.70#ibcon#*after write, iclass 29, count 0 2006.201.08:14:15.70#ibcon#*before return 0, iclass 29, count 0 2006.201.08:14:15.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:15.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:14:15.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.08:14:15.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.08:14:15.70$vck44/vb=2,5 2006.201.08:14:15.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.08:14:15.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.08:14:15.70#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:15.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:15.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:15.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:15.76#ibcon#enter wrdev, iclass 31, count 2 2006.201.08:14:15.76#ibcon#first serial, iclass 31, count 2 2006.201.08:14:15.76#ibcon#enter sib2, iclass 31, count 2 2006.201.08:14:15.76#ibcon#flushed, iclass 31, count 2 2006.201.08:14:15.76#ibcon#about to write, iclass 31, count 2 2006.201.08:14:15.76#ibcon#wrote, iclass 31, count 2 2006.201.08:14:15.76#ibcon#about to read 3, iclass 31, count 2 2006.201.08:14:15.78#ibcon#read 3, iclass 31, count 2 2006.201.08:14:15.78#ibcon#about to read 4, iclass 31, count 2 2006.201.08:14:15.78#ibcon#read 4, iclass 31, count 2 2006.201.08:14:15.78#ibcon#about to read 5, iclass 31, count 2 2006.201.08:14:15.78#ibcon#read 5, iclass 31, count 2 2006.201.08:14:15.78#ibcon#about to read 6, iclass 31, count 2 2006.201.08:14:15.78#ibcon#read 6, iclass 31, count 2 2006.201.08:14:15.78#ibcon#end of sib2, iclass 31, count 2 2006.201.08:14:15.78#ibcon#*mode == 0, iclass 31, count 2 2006.201.08:14:15.78#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.08:14:15.78#ibcon#[27=AT02-05\r\n] 2006.201.08:14:15.78#ibcon#*before write, iclass 31, count 2 2006.201.08:14:15.78#ibcon#enter sib2, iclass 31, count 2 2006.201.08:14:15.78#ibcon#flushed, iclass 31, count 2 2006.201.08:14:15.78#ibcon#about to write, iclass 31, count 2 2006.201.08:14:15.78#ibcon#wrote, iclass 31, count 2 2006.201.08:14:15.78#ibcon#about to read 3, iclass 31, count 2 2006.201.08:14:15.81#ibcon#read 3, iclass 31, count 2 2006.201.08:14:15.81#ibcon#about to read 4, iclass 31, count 2 2006.201.08:14:15.81#ibcon#read 4, iclass 31, count 2 2006.201.08:14:15.81#ibcon#about to read 5, iclass 31, count 2 2006.201.08:14:15.81#ibcon#read 5, iclass 31, count 2 2006.201.08:14:15.81#ibcon#about to read 6, iclass 31, count 2 2006.201.08:14:15.81#ibcon#read 6, iclass 31, count 2 2006.201.08:14:15.81#ibcon#end of sib2, iclass 31, count 2 2006.201.08:14:15.81#ibcon#*after write, iclass 31, count 2 2006.201.08:14:15.81#ibcon#*before return 0, iclass 31, count 2 2006.201.08:14:15.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:15.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:14:15.81#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.08:14:15.81#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:15.81#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:15.93#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:15.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:15.93#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:14:15.93#ibcon#first serial, iclass 31, count 0 2006.201.08:14:15.93#ibcon#enter sib2, iclass 31, count 0 2006.201.08:14:15.93#ibcon#flushed, iclass 31, count 0 2006.201.08:14:15.93#ibcon#about to write, iclass 31, count 0 2006.201.08:14:15.93#ibcon#wrote, iclass 31, count 0 2006.201.08:14:15.93#ibcon#about to read 3, iclass 31, count 0 2006.201.08:14:15.95#ibcon#read 3, iclass 31, count 0 2006.201.08:14:15.95#ibcon#about to read 4, iclass 31, count 0 2006.201.08:14:15.95#ibcon#read 4, iclass 31, count 0 2006.201.08:14:15.95#ibcon#about to read 5, iclass 31, count 0 2006.201.08:14:15.95#ibcon#read 5, iclass 31, count 0 2006.201.08:14:15.95#ibcon#about to read 6, iclass 31, count 0 2006.201.08:14:15.95#ibcon#read 6, iclass 31, count 0 2006.201.08:14:15.95#ibcon#end of sib2, iclass 31, count 0 2006.201.08:14:15.95#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:14:15.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:14:15.95#ibcon#[27=USB\r\n] 2006.201.08:14:15.95#ibcon#*before write, iclass 31, count 0 2006.201.08:14:15.95#ibcon#enter sib2, iclass 31, count 0 2006.201.08:14:15.95#ibcon#flushed, iclass 31, count 0 2006.201.08:14:15.95#ibcon#about to write, iclass 31, count 0 2006.201.08:14:15.95#ibcon#wrote, iclass 31, count 0 2006.201.08:14:15.95#ibcon#about to read 3, iclass 31, count 0 2006.201.08:14:15.98#ibcon#read 3, iclass 31, count 0 2006.201.08:14:15.98#ibcon#about to read 4, iclass 31, count 0 2006.201.08:14:15.98#ibcon#read 4, iclass 31, count 0 2006.201.08:14:15.98#ibcon#about to read 5, iclass 31, count 0 2006.201.08:14:15.98#ibcon#read 5, iclass 31, count 0 2006.201.08:14:15.98#ibcon#about to read 6, iclass 31, count 0 2006.201.08:14:15.98#ibcon#read 6, iclass 31, count 0 2006.201.08:14:15.98#ibcon#end of sib2, iclass 31, count 0 2006.201.08:14:15.98#ibcon#*after write, iclass 31, count 0 2006.201.08:14:15.98#ibcon#*before return 0, iclass 31, count 0 2006.201.08:14:15.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:15.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:14:15.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:14:15.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:14:15.98$vck44/vblo=3,649.99 2006.201.08:14:15.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.08:14:15.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.08:14:15.98#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:15.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:15.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:15.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:15.98#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:14:15.98#ibcon#first serial, iclass 33, count 0 2006.201.08:14:15.98#ibcon#enter sib2, iclass 33, count 0 2006.201.08:14:15.98#ibcon#flushed, iclass 33, count 0 2006.201.08:14:15.98#ibcon#about to write, iclass 33, count 0 2006.201.08:14:15.98#ibcon#wrote, iclass 33, count 0 2006.201.08:14:15.98#ibcon#about to read 3, iclass 33, count 0 2006.201.08:14:16.00#ibcon#read 3, iclass 33, count 0 2006.201.08:14:16.00#ibcon#about to read 4, iclass 33, count 0 2006.201.08:14:16.00#ibcon#read 4, iclass 33, count 0 2006.201.08:14:16.00#ibcon#about to read 5, iclass 33, count 0 2006.201.08:14:16.00#ibcon#read 5, iclass 33, count 0 2006.201.08:14:16.00#ibcon#about to read 6, iclass 33, count 0 2006.201.08:14:16.00#ibcon#read 6, iclass 33, count 0 2006.201.08:14:16.00#ibcon#end of sib2, iclass 33, count 0 2006.201.08:14:16.00#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:14:16.00#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:14:16.00#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:14:16.00#ibcon#*before write, iclass 33, count 0 2006.201.08:14:16.00#ibcon#enter sib2, iclass 33, count 0 2006.201.08:14:16.00#ibcon#flushed, iclass 33, count 0 2006.201.08:14:16.00#ibcon#about to write, iclass 33, count 0 2006.201.08:14:16.00#ibcon#wrote, iclass 33, count 0 2006.201.08:14:16.00#ibcon#about to read 3, iclass 33, count 0 2006.201.08:14:16.04#ibcon#read 3, iclass 33, count 0 2006.201.08:14:16.04#ibcon#about to read 4, iclass 33, count 0 2006.201.08:14:16.04#ibcon#read 4, iclass 33, count 0 2006.201.08:14:16.04#ibcon#about to read 5, iclass 33, count 0 2006.201.08:14:16.04#ibcon#read 5, iclass 33, count 0 2006.201.08:14:16.04#ibcon#about to read 6, iclass 33, count 0 2006.201.08:14:16.04#ibcon#read 6, iclass 33, count 0 2006.201.08:14:16.04#ibcon#end of sib2, iclass 33, count 0 2006.201.08:14:16.04#ibcon#*after write, iclass 33, count 0 2006.201.08:14:16.04#ibcon#*before return 0, iclass 33, count 0 2006.201.08:14:16.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:16.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:14:16.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:14:16.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:14:16.04$vck44/vb=3,4 2006.201.08:14:16.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.08:14:16.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.08:14:16.04#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:16.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:16.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:16.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:16.10#ibcon#enter wrdev, iclass 35, count 2 2006.201.08:14:16.10#ibcon#first serial, iclass 35, count 2 2006.201.08:14:16.10#ibcon#enter sib2, iclass 35, count 2 2006.201.08:14:16.10#ibcon#flushed, iclass 35, count 2 2006.201.08:14:16.10#ibcon#about to write, iclass 35, count 2 2006.201.08:14:16.10#ibcon#wrote, iclass 35, count 2 2006.201.08:14:16.10#ibcon#about to read 3, iclass 35, count 2 2006.201.08:14:16.12#ibcon#read 3, iclass 35, count 2 2006.201.08:14:16.12#ibcon#about to read 4, iclass 35, count 2 2006.201.08:14:16.12#ibcon#read 4, iclass 35, count 2 2006.201.08:14:16.12#ibcon#about to read 5, iclass 35, count 2 2006.201.08:14:16.12#ibcon#read 5, iclass 35, count 2 2006.201.08:14:16.12#ibcon#about to read 6, iclass 35, count 2 2006.201.08:14:16.12#ibcon#read 6, iclass 35, count 2 2006.201.08:14:16.12#ibcon#end of sib2, iclass 35, count 2 2006.201.08:14:16.12#ibcon#*mode == 0, iclass 35, count 2 2006.201.08:14:16.12#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.08:14:16.12#ibcon#[27=AT03-04\r\n] 2006.201.08:14:16.12#ibcon#*before write, iclass 35, count 2 2006.201.08:14:16.12#ibcon#enter sib2, iclass 35, count 2 2006.201.08:14:16.12#ibcon#flushed, iclass 35, count 2 2006.201.08:14:16.12#ibcon#about to write, iclass 35, count 2 2006.201.08:14:16.12#ibcon#wrote, iclass 35, count 2 2006.201.08:14:16.12#ibcon#about to read 3, iclass 35, count 2 2006.201.08:14:16.15#ibcon#read 3, iclass 35, count 2 2006.201.08:14:16.15#ibcon#about to read 4, iclass 35, count 2 2006.201.08:14:16.15#ibcon#read 4, iclass 35, count 2 2006.201.08:14:16.15#ibcon#about to read 5, iclass 35, count 2 2006.201.08:14:16.15#ibcon#read 5, iclass 35, count 2 2006.201.08:14:16.15#ibcon#about to read 6, iclass 35, count 2 2006.201.08:14:16.15#ibcon#read 6, iclass 35, count 2 2006.201.08:14:16.15#ibcon#end of sib2, iclass 35, count 2 2006.201.08:14:16.15#ibcon#*after write, iclass 35, count 2 2006.201.08:14:16.15#ibcon#*before return 0, iclass 35, count 2 2006.201.08:14:16.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:16.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:14:16.15#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.08:14:16.15#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:16.15#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:16.27#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:16.27#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:16.27#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:14:16.27#ibcon#first serial, iclass 35, count 0 2006.201.08:14:16.27#ibcon#enter sib2, iclass 35, count 0 2006.201.08:14:16.27#ibcon#flushed, iclass 35, count 0 2006.201.08:14:16.27#ibcon#about to write, iclass 35, count 0 2006.201.08:14:16.27#ibcon#wrote, iclass 35, count 0 2006.201.08:14:16.27#ibcon#about to read 3, iclass 35, count 0 2006.201.08:14:16.29#ibcon#read 3, iclass 35, count 0 2006.201.08:14:16.29#ibcon#about to read 4, iclass 35, count 0 2006.201.08:14:16.29#ibcon#read 4, iclass 35, count 0 2006.201.08:14:16.29#ibcon#about to read 5, iclass 35, count 0 2006.201.08:14:16.29#ibcon#read 5, iclass 35, count 0 2006.201.08:14:16.29#ibcon#about to read 6, iclass 35, count 0 2006.201.08:14:16.29#ibcon#read 6, iclass 35, count 0 2006.201.08:14:16.29#ibcon#end of sib2, iclass 35, count 0 2006.201.08:14:16.29#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:14:16.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:14:16.29#ibcon#[27=USB\r\n] 2006.201.08:14:16.29#ibcon#*before write, iclass 35, count 0 2006.201.08:14:16.29#ibcon#enter sib2, iclass 35, count 0 2006.201.08:14:16.29#ibcon#flushed, iclass 35, count 0 2006.201.08:14:16.29#ibcon#about to write, iclass 35, count 0 2006.201.08:14:16.29#ibcon#wrote, iclass 35, count 0 2006.201.08:14:16.29#ibcon#about to read 3, iclass 35, count 0 2006.201.08:14:16.32#ibcon#read 3, iclass 35, count 0 2006.201.08:14:16.32#ibcon#about to read 4, iclass 35, count 0 2006.201.08:14:16.32#ibcon#read 4, iclass 35, count 0 2006.201.08:14:16.32#ibcon#about to read 5, iclass 35, count 0 2006.201.08:14:16.32#ibcon#read 5, iclass 35, count 0 2006.201.08:14:16.32#ibcon#about to read 6, iclass 35, count 0 2006.201.08:14:16.32#ibcon#read 6, iclass 35, count 0 2006.201.08:14:16.32#ibcon#end of sib2, iclass 35, count 0 2006.201.08:14:16.32#ibcon#*after write, iclass 35, count 0 2006.201.08:14:16.32#ibcon#*before return 0, iclass 35, count 0 2006.201.08:14:16.32#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:16.32#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:14:16.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:14:16.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:14:16.32$vck44/vblo=4,679.99 2006.201.08:14:16.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.08:14:16.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.08:14:16.32#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:16.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:16.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:16.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:16.32#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:14:16.32#ibcon#first serial, iclass 37, count 0 2006.201.08:14:16.32#ibcon#enter sib2, iclass 37, count 0 2006.201.08:14:16.32#ibcon#flushed, iclass 37, count 0 2006.201.08:14:16.32#ibcon#about to write, iclass 37, count 0 2006.201.08:14:16.32#ibcon#wrote, iclass 37, count 0 2006.201.08:14:16.32#ibcon#about to read 3, iclass 37, count 0 2006.201.08:14:16.34#ibcon#read 3, iclass 37, count 0 2006.201.08:14:16.34#ibcon#about to read 4, iclass 37, count 0 2006.201.08:14:16.34#ibcon#read 4, iclass 37, count 0 2006.201.08:14:16.34#ibcon#about to read 5, iclass 37, count 0 2006.201.08:14:16.34#ibcon#read 5, iclass 37, count 0 2006.201.08:14:16.34#ibcon#about to read 6, iclass 37, count 0 2006.201.08:14:16.34#ibcon#read 6, iclass 37, count 0 2006.201.08:14:16.34#ibcon#end of sib2, iclass 37, count 0 2006.201.08:14:16.34#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:14:16.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:14:16.34#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:14:16.34#ibcon#*before write, iclass 37, count 0 2006.201.08:14:16.34#ibcon#enter sib2, iclass 37, count 0 2006.201.08:14:16.34#ibcon#flushed, iclass 37, count 0 2006.201.08:14:16.34#ibcon#about to write, iclass 37, count 0 2006.201.08:14:16.34#ibcon#wrote, iclass 37, count 0 2006.201.08:14:16.34#ibcon#about to read 3, iclass 37, count 0 2006.201.08:14:16.38#ibcon#read 3, iclass 37, count 0 2006.201.08:14:16.38#ibcon#about to read 4, iclass 37, count 0 2006.201.08:14:16.38#ibcon#read 4, iclass 37, count 0 2006.201.08:14:16.38#ibcon#about to read 5, iclass 37, count 0 2006.201.08:14:16.38#ibcon#read 5, iclass 37, count 0 2006.201.08:14:16.38#ibcon#about to read 6, iclass 37, count 0 2006.201.08:14:16.38#ibcon#read 6, iclass 37, count 0 2006.201.08:14:16.38#ibcon#end of sib2, iclass 37, count 0 2006.201.08:14:16.38#ibcon#*after write, iclass 37, count 0 2006.201.08:14:16.38#ibcon#*before return 0, iclass 37, count 0 2006.201.08:14:16.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:16.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:14:16.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:14:16.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:14:16.38$vck44/vb=4,5 2006.201.08:14:16.38#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.08:14:16.38#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.08:14:16.38#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:16.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:16.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:16.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:16.44#ibcon#enter wrdev, iclass 39, count 2 2006.201.08:14:16.44#ibcon#first serial, iclass 39, count 2 2006.201.08:14:16.44#ibcon#enter sib2, iclass 39, count 2 2006.201.08:14:16.44#ibcon#flushed, iclass 39, count 2 2006.201.08:14:16.44#ibcon#about to write, iclass 39, count 2 2006.201.08:14:16.44#ibcon#wrote, iclass 39, count 2 2006.201.08:14:16.44#ibcon#about to read 3, iclass 39, count 2 2006.201.08:14:16.46#ibcon#read 3, iclass 39, count 2 2006.201.08:14:16.46#ibcon#about to read 4, iclass 39, count 2 2006.201.08:14:16.46#ibcon#read 4, iclass 39, count 2 2006.201.08:14:16.46#ibcon#about to read 5, iclass 39, count 2 2006.201.08:14:16.46#ibcon#read 5, iclass 39, count 2 2006.201.08:14:16.46#ibcon#about to read 6, iclass 39, count 2 2006.201.08:14:16.46#ibcon#read 6, iclass 39, count 2 2006.201.08:14:16.46#ibcon#end of sib2, iclass 39, count 2 2006.201.08:14:16.46#ibcon#*mode == 0, iclass 39, count 2 2006.201.08:14:16.46#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.08:14:16.46#ibcon#[27=AT04-05\r\n] 2006.201.08:14:16.46#ibcon#*before write, iclass 39, count 2 2006.201.08:14:16.46#ibcon#enter sib2, iclass 39, count 2 2006.201.08:14:16.46#ibcon#flushed, iclass 39, count 2 2006.201.08:14:16.46#ibcon#about to write, iclass 39, count 2 2006.201.08:14:16.46#ibcon#wrote, iclass 39, count 2 2006.201.08:14:16.46#ibcon#about to read 3, iclass 39, count 2 2006.201.08:14:16.49#ibcon#read 3, iclass 39, count 2 2006.201.08:14:16.49#ibcon#about to read 4, iclass 39, count 2 2006.201.08:14:16.49#ibcon#read 4, iclass 39, count 2 2006.201.08:14:16.49#ibcon#about to read 5, iclass 39, count 2 2006.201.08:14:16.49#ibcon#read 5, iclass 39, count 2 2006.201.08:14:16.49#ibcon#about to read 6, iclass 39, count 2 2006.201.08:14:16.49#ibcon#read 6, iclass 39, count 2 2006.201.08:14:16.49#ibcon#end of sib2, iclass 39, count 2 2006.201.08:14:16.49#ibcon#*after write, iclass 39, count 2 2006.201.08:14:16.49#ibcon#*before return 0, iclass 39, count 2 2006.201.08:14:16.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:16.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:14:16.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.08:14:16.49#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:16.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:16.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:16.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:16.61#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:14:16.61#ibcon#first serial, iclass 39, count 0 2006.201.08:14:16.61#ibcon#enter sib2, iclass 39, count 0 2006.201.08:14:16.61#ibcon#flushed, iclass 39, count 0 2006.201.08:14:16.61#ibcon#about to write, iclass 39, count 0 2006.201.08:14:16.61#ibcon#wrote, iclass 39, count 0 2006.201.08:14:16.61#ibcon#about to read 3, iclass 39, count 0 2006.201.08:14:16.63#ibcon#read 3, iclass 39, count 0 2006.201.08:14:16.63#ibcon#about to read 4, iclass 39, count 0 2006.201.08:14:16.63#ibcon#read 4, iclass 39, count 0 2006.201.08:14:16.63#ibcon#about to read 5, iclass 39, count 0 2006.201.08:14:16.63#ibcon#read 5, iclass 39, count 0 2006.201.08:14:16.63#ibcon#about to read 6, iclass 39, count 0 2006.201.08:14:16.63#ibcon#read 6, iclass 39, count 0 2006.201.08:14:16.63#ibcon#end of sib2, iclass 39, count 0 2006.201.08:14:16.63#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:14:16.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:14:16.63#ibcon#[27=USB\r\n] 2006.201.08:14:16.63#ibcon#*before write, iclass 39, count 0 2006.201.08:14:16.63#ibcon#enter sib2, iclass 39, count 0 2006.201.08:14:16.63#ibcon#flushed, iclass 39, count 0 2006.201.08:14:16.63#ibcon#about to write, iclass 39, count 0 2006.201.08:14:16.63#ibcon#wrote, iclass 39, count 0 2006.201.08:14:16.63#ibcon#about to read 3, iclass 39, count 0 2006.201.08:14:16.66#ibcon#read 3, iclass 39, count 0 2006.201.08:14:16.66#ibcon#about to read 4, iclass 39, count 0 2006.201.08:14:16.66#ibcon#read 4, iclass 39, count 0 2006.201.08:14:16.66#ibcon#about to read 5, iclass 39, count 0 2006.201.08:14:16.66#ibcon#read 5, iclass 39, count 0 2006.201.08:14:16.66#ibcon#about to read 6, iclass 39, count 0 2006.201.08:14:16.66#ibcon#read 6, iclass 39, count 0 2006.201.08:14:16.66#ibcon#end of sib2, iclass 39, count 0 2006.201.08:14:16.66#ibcon#*after write, iclass 39, count 0 2006.201.08:14:16.66#ibcon#*before return 0, iclass 39, count 0 2006.201.08:14:16.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:16.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:14:16.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:14:16.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:14:16.66$vck44/vblo=5,709.99 2006.201.08:14:16.66#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.08:14:16.66#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.08:14:16.66#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:16.66#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:16.66#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:16.66#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:16.66#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:14:16.66#ibcon#first serial, iclass 2, count 0 2006.201.08:14:16.66#ibcon#enter sib2, iclass 2, count 0 2006.201.08:14:16.66#ibcon#flushed, iclass 2, count 0 2006.201.08:14:16.66#ibcon#about to write, iclass 2, count 0 2006.201.08:14:16.66#ibcon#wrote, iclass 2, count 0 2006.201.08:14:16.66#ibcon#about to read 3, iclass 2, count 0 2006.201.08:14:16.68#ibcon#read 3, iclass 2, count 0 2006.201.08:14:16.68#ibcon#about to read 4, iclass 2, count 0 2006.201.08:14:16.68#ibcon#read 4, iclass 2, count 0 2006.201.08:14:16.68#ibcon#about to read 5, iclass 2, count 0 2006.201.08:14:16.68#ibcon#read 5, iclass 2, count 0 2006.201.08:14:16.68#ibcon#about to read 6, iclass 2, count 0 2006.201.08:14:16.68#ibcon#read 6, iclass 2, count 0 2006.201.08:14:16.68#ibcon#end of sib2, iclass 2, count 0 2006.201.08:14:16.68#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:14:16.68#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:14:16.68#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:14:16.68#ibcon#*before write, iclass 2, count 0 2006.201.08:14:16.68#ibcon#enter sib2, iclass 2, count 0 2006.201.08:14:16.68#ibcon#flushed, iclass 2, count 0 2006.201.08:14:16.68#ibcon#about to write, iclass 2, count 0 2006.201.08:14:16.68#ibcon#wrote, iclass 2, count 0 2006.201.08:14:16.68#ibcon#about to read 3, iclass 2, count 0 2006.201.08:14:16.72#ibcon#read 3, iclass 2, count 0 2006.201.08:14:16.72#ibcon#about to read 4, iclass 2, count 0 2006.201.08:14:16.72#ibcon#read 4, iclass 2, count 0 2006.201.08:14:16.72#ibcon#about to read 5, iclass 2, count 0 2006.201.08:14:16.72#ibcon#read 5, iclass 2, count 0 2006.201.08:14:16.72#ibcon#about to read 6, iclass 2, count 0 2006.201.08:14:16.72#ibcon#read 6, iclass 2, count 0 2006.201.08:14:16.72#ibcon#end of sib2, iclass 2, count 0 2006.201.08:14:16.72#ibcon#*after write, iclass 2, count 0 2006.201.08:14:16.72#ibcon#*before return 0, iclass 2, count 0 2006.201.08:14:16.72#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:16.72#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:14:16.72#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:14:16.72#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:14:16.72$vck44/vb=5,4 2006.201.08:14:16.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.08:14:16.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.08:14:16.72#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:16.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:16.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:16.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:16.78#ibcon#enter wrdev, iclass 5, count 2 2006.201.08:14:16.78#ibcon#first serial, iclass 5, count 2 2006.201.08:14:16.78#ibcon#enter sib2, iclass 5, count 2 2006.201.08:14:16.78#ibcon#flushed, iclass 5, count 2 2006.201.08:14:16.78#ibcon#about to write, iclass 5, count 2 2006.201.08:14:16.78#ibcon#wrote, iclass 5, count 2 2006.201.08:14:16.78#ibcon#about to read 3, iclass 5, count 2 2006.201.08:14:16.80#ibcon#read 3, iclass 5, count 2 2006.201.08:14:16.80#ibcon#about to read 4, iclass 5, count 2 2006.201.08:14:16.80#ibcon#read 4, iclass 5, count 2 2006.201.08:14:16.80#ibcon#about to read 5, iclass 5, count 2 2006.201.08:14:16.80#ibcon#read 5, iclass 5, count 2 2006.201.08:14:16.80#ibcon#about to read 6, iclass 5, count 2 2006.201.08:14:16.80#ibcon#read 6, iclass 5, count 2 2006.201.08:14:16.80#ibcon#end of sib2, iclass 5, count 2 2006.201.08:14:16.80#ibcon#*mode == 0, iclass 5, count 2 2006.201.08:14:16.80#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.08:14:16.80#ibcon#[27=AT05-04\r\n] 2006.201.08:14:16.80#ibcon#*before write, iclass 5, count 2 2006.201.08:14:16.80#ibcon#enter sib2, iclass 5, count 2 2006.201.08:14:16.80#ibcon#flushed, iclass 5, count 2 2006.201.08:14:16.80#ibcon#about to write, iclass 5, count 2 2006.201.08:14:16.80#ibcon#wrote, iclass 5, count 2 2006.201.08:14:16.80#ibcon#about to read 3, iclass 5, count 2 2006.201.08:14:16.83#ibcon#read 3, iclass 5, count 2 2006.201.08:14:16.83#ibcon#about to read 4, iclass 5, count 2 2006.201.08:14:16.83#ibcon#read 4, iclass 5, count 2 2006.201.08:14:16.83#ibcon#about to read 5, iclass 5, count 2 2006.201.08:14:16.83#ibcon#read 5, iclass 5, count 2 2006.201.08:14:16.83#ibcon#about to read 6, iclass 5, count 2 2006.201.08:14:16.83#ibcon#read 6, iclass 5, count 2 2006.201.08:14:16.83#ibcon#end of sib2, iclass 5, count 2 2006.201.08:14:16.83#ibcon#*after write, iclass 5, count 2 2006.201.08:14:16.83#ibcon#*before return 0, iclass 5, count 2 2006.201.08:14:16.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:16.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:14:16.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.08:14:16.83#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:16.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:16.95#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:16.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:16.95#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:14:16.95#ibcon#first serial, iclass 5, count 0 2006.201.08:14:16.95#ibcon#enter sib2, iclass 5, count 0 2006.201.08:14:16.95#ibcon#flushed, iclass 5, count 0 2006.201.08:14:16.95#ibcon#about to write, iclass 5, count 0 2006.201.08:14:16.95#ibcon#wrote, iclass 5, count 0 2006.201.08:14:16.95#ibcon#about to read 3, iclass 5, count 0 2006.201.08:14:16.97#ibcon#read 3, iclass 5, count 0 2006.201.08:14:16.97#ibcon#about to read 4, iclass 5, count 0 2006.201.08:14:16.97#ibcon#read 4, iclass 5, count 0 2006.201.08:14:16.97#ibcon#about to read 5, iclass 5, count 0 2006.201.08:14:16.97#ibcon#read 5, iclass 5, count 0 2006.201.08:14:16.97#ibcon#about to read 6, iclass 5, count 0 2006.201.08:14:16.97#ibcon#read 6, iclass 5, count 0 2006.201.08:14:16.97#ibcon#end of sib2, iclass 5, count 0 2006.201.08:14:16.97#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:14:16.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:14:16.97#ibcon#[27=USB\r\n] 2006.201.08:14:16.97#ibcon#*before write, iclass 5, count 0 2006.201.08:14:16.97#ibcon#enter sib2, iclass 5, count 0 2006.201.08:14:16.97#ibcon#flushed, iclass 5, count 0 2006.201.08:14:16.97#ibcon#about to write, iclass 5, count 0 2006.201.08:14:16.97#ibcon#wrote, iclass 5, count 0 2006.201.08:14:16.97#ibcon#about to read 3, iclass 5, count 0 2006.201.08:14:17.00#ibcon#read 3, iclass 5, count 0 2006.201.08:14:17.00#ibcon#about to read 4, iclass 5, count 0 2006.201.08:14:17.00#ibcon#read 4, iclass 5, count 0 2006.201.08:14:17.00#ibcon#about to read 5, iclass 5, count 0 2006.201.08:14:17.00#ibcon#read 5, iclass 5, count 0 2006.201.08:14:17.00#ibcon#about to read 6, iclass 5, count 0 2006.201.08:14:17.00#ibcon#read 6, iclass 5, count 0 2006.201.08:14:17.00#ibcon#end of sib2, iclass 5, count 0 2006.201.08:14:17.00#ibcon#*after write, iclass 5, count 0 2006.201.08:14:17.00#ibcon#*before return 0, iclass 5, count 0 2006.201.08:14:17.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:17.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:14:17.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:14:17.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:14:17.00$vck44/vblo=6,719.99 2006.201.08:14:17.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.08:14:17.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.08:14:17.00#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:17.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:14:17.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:14:17.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:14:17.00#ibcon#enter wrdev, iclass 7, count 0 2006.201.08:14:17.00#ibcon#first serial, iclass 7, count 0 2006.201.08:14:17.00#ibcon#enter sib2, iclass 7, count 0 2006.201.08:14:17.00#ibcon#flushed, iclass 7, count 0 2006.201.08:14:17.00#ibcon#about to write, iclass 7, count 0 2006.201.08:14:17.00#ibcon#wrote, iclass 7, count 0 2006.201.08:14:17.00#ibcon#about to read 3, iclass 7, count 0 2006.201.08:14:17.02#ibcon#read 3, iclass 7, count 0 2006.201.08:14:17.02#ibcon#about to read 4, iclass 7, count 0 2006.201.08:14:17.02#ibcon#read 4, iclass 7, count 0 2006.201.08:14:17.02#ibcon#about to read 5, iclass 7, count 0 2006.201.08:14:17.02#ibcon#read 5, iclass 7, count 0 2006.201.08:14:17.02#ibcon#about to read 6, iclass 7, count 0 2006.201.08:14:17.02#ibcon#read 6, iclass 7, count 0 2006.201.08:14:17.02#ibcon#end of sib2, iclass 7, count 0 2006.201.08:14:17.02#ibcon#*mode == 0, iclass 7, count 0 2006.201.08:14:17.02#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.08:14:17.02#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:14:17.02#ibcon#*before write, iclass 7, count 0 2006.201.08:14:17.02#ibcon#enter sib2, iclass 7, count 0 2006.201.08:14:17.02#ibcon#flushed, iclass 7, count 0 2006.201.08:14:17.02#ibcon#about to write, iclass 7, count 0 2006.201.08:14:17.02#ibcon#wrote, iclass 7, count 0 2006.201.08:14:17.02#ibcon#about to read 3, iclass 7, count 0 2006.201.08:14:17.06#ibcon#read 3, iclass 7, count 0 2006.201.08:14:17.06#ibcon#about to read 4, iclass 7, count 0 2006.201.08:14:17.06#ibcon#read 4, iclass 7, count 0 2006.201.08:14:17.06#ibcon#about to read 5, iclass 7, count 0 2006.201.08:14:17.06#ibcon#read 5, iclass 7, count 0 2006.201.08:14:17.06#ibcon#about to read 6, iclass 7, count 0 2006.201.08:14:17.06#ibcon#read 6, iclass 7, count 0 2006.201.08:14:17.06#ibcon#end of sib2, iclass 7, count 0 2006.201.08:14:17.06#ibcon#*after write, iclass 7, count 0 2006.201.08:14:17.06#ibcon#*before return 0, iclass 7, count 0 2006.201.08:14:17.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:14:17.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:14:17.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.08:14:17.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.08:14:17.06$vck44/vb=6,4 2006.201.08:14:17.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.08:14:17.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.08:14:17.06#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:17.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:14:17.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:14:17.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:14:17.12#ibcon#enter wrdev, iclass 11, count 2 2006.201.08:14:17.12#ibcon#first serial, iclass 11, count 2 2006.201.08:14:17.12#ibcon#enter sib2, iclass 11, count 2 2006.201.08:14:17.12#ibcon#flushed, iclass 11, count 2 2006.201.08:14:17.12#ibcon#about to write, iclass 11, count 2 2006.201.08:14:17.12#ibcon#wrote, iclass 11, count 2 2006.201.08:14:17.12#ibcon#about to read 3, iclass 11, count 2 2006.201.08:14:17.14#ibcon#read 3, iclass 11, count 2 2006.201.08:14:17.14#ibcon#about to read 4, iclass 11, count 2 2006.201.08:14:17.14#ibcon#read 4, iclass 11, count 2 2006.201.08:14:17.14#ibcon#about to read 5, iclass 11, count 2 2006.201.08:14:17.14#ibcon#read 5, iclass 11, count 2 2006.201.08:14:17.14#ibcon#about to read 6, iclass 11, count 2 2006.201.08:14:17.14#ibcon#read 6, iclass 11, count 2 2006.201.08:14:17.14#ibcon#end of sib2, iclass 11, count 2 2006.201.08:14:17.14#ibcon#*mode == 0, iclass 11, count 2 2006.201.08:14:17.14#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.08:14:17.14#ibcon#[27=AT06-04\r\n] 2006.201.08:14:17.14#ibcon#*before write, iclass 11, count 2 2006.201.08:14:17.14#ibcon#enter sib2, iclass 11, count 2 2006.201.08:14:17.14#ibcon#flushed, iclass 11, count 2 2006.201.08:14:17.14#ibcon#about to write, iclass 11, count 2 2006.201.08:14:17.14#ibcon#wrote, iclass 11, count 2 2006.201.08:14:17.14#ibcon#about to read 3, iclass 11, count 2 2006.201.08:14:17.17#ibcon#read 3, iclass 11, count 2 2006.201.08:14:17.17#ibcon#about to read 4, iclass 11, count 2 2006.201.08:14:17.17#ibcon#read 4, iclass 11, count 2 2006.201.08:14:17.17#ibcon#about to read 5, iclass 11, count 2 2006.201.08:14:17.17#ibcon#read 5, iclass 11, count 2 2006.201.08:14:17.17#ibcon#about to read 6, iclass 11, count 2 2006.201.08:14:17.17#ibcon#read 6, iclass 11, count 2 2006.201.08:14:17.17#ibcon#end of sib2, iclass 11, count 2 2006.201.08:14:17.17#ibcon#*after write, iclass 11, count 2 2006.201.08:14:17.17#ibcon#*before return 0, iclass 11, count 2 2006.201.08:14:17.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:14:17.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:14:17.17#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.08:14:17.17#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:17.17#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:14:17.29#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:14:17.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:14:17.29#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:14:17.29#ibcon#first serial, iclass 11, count 0 2006.201.08:14:17.29#ibcon#enter sib2, iclass 11, count 0 2006.201.08:14:17.29#ibcon#flushed, iclass 11, count 0 2006.201.08:14:17.29#ibcon#about to write, iclass 11, count 0 2006.201.08:14:17.29#ibcon#wrote, iclass 11, count 0 2006.201.08:14:17.29#ibcon#about to read 3, iclass 11, count 0 2006.201.08:14:17.31#ibcon#read 3, iclass 11, count 0 2006.201.08:14:17.31#ibcon#about to read 4, iclass 11, count 0 2006.201.08:14:17.31#ibcon#read 4, iclass 11, count 0 2006.201.08:14:17.31#ibcon#about to read 5, iclass 11, count 0 2006.201.08:14:17.31#ibcon#read 5, iclass 11, count 0 2006.201.08:14:17.31#ibcon#about to read 6, iclass 11, count 0 2006.201.08:14:17.31#ibcon#read 6, iclass 11, count 0 2006.201.08:14:17.31#ibcon#end of sib2, iclass 11, count 0 2006.201.08:14:17.31#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:14:17.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:14:17.31#ibcon#[27=USB\r\n] 2006.201.08:14:17.31#ibcon#*before write, iclass 11, count 0 2006.201.08:14:17.31#ibcon#enter sib2, iclass 11, count 0 2006.201.08:14:17.31#ibcon#flushed, iclass 11, count 0 2006.201.08:14:17.31#ibcon#about to write, iclass 11, count 0 2006.201.08:14:17.31#ibcon#wrote, iclass 11, count 0 2006.201.08:14:17.31#ibcon#about to read 3, iclass 11, count 0 2006.201.08:14:17.34#ibcon#read 3, iclass 11, count 0 2006.201.08:14:17.34#ibcon#about to read 4, iclass 11, count 0 2006.201.08:14:17.34#ibcon#read 4, iclass 11, count 0 2006.201.08:14:17.34#ibcon#about to read 5, iclass 11, count 0 2006.201.08:14:17.34#ibcon#read 5, iclass 11, count 0 2006.201.08:14:17.34#ibcon#about to read 6, iclass 11, count 0 2006.201.08:14:17.34#ibcon#read 6, iclass 11, count 0 2006.201.08:14:17.34#ibcon#end of sib2, iclass 11, count 0 2006.201.08:14:17.34#ibcon#*after write, iclass 11, count 0 2006.201.08:14:17.34#ibcon#*before return 0, iclass 11, count 0 2006.201.08:14:17.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:14:17.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:14:17.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:14:17.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:14:17.34$vck44/vblo=7,734.99 2006.201.08:14:17.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.08:14:17.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.08:14:17.34#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:17.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:17.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:17.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:17.34#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:14:17.34#ibcon#first serial, iclass 13, count 0 2006.201.08:14:17.34#ibcon#enter sib2, iclass 13, count 0 2006.201.08:14:17.34#ibcon#flushed, iclass 13, count 0 2006.201.08:14:17.34#ibcon#about to write, iclass 13, count 0 2006.201.08:14:17.34#ibcon#wrote, iclass 13, count 0 2006.201.08:14:17.34#ibcon#about to read 3, iclass 13, count 0 2006.201.08:14:17.36#ibcon#read 3, iclass 13, count 0 2006.201.08:14:17.36#ibcon#about to read 4, iclass 13, count 0 2006.201.08:14:17.36#ibcon#read 4, iclass 13, count 0 2006.201.08:14:17.36#ibcon#about to read 5, iclass 13, count 0 2006.201.08:14:17.36#ibcon#read 5, iclass 13, count 0 2006.201.08:14:17.36#ibcon#about to read 6, iclass 13, count 0 2006.201.08:14:17.36#ibcon#read 6, iclass 13, count 0 2006.201.08:14:17.36#ibcon#end of sib2, iclass 13, count 0 2006.201.08:14:17.36#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:14:17.36#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:14:17.36#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:14:17.36#ibcon#*before write, iclass 13, count 0 2006.201.08:14:17.36#ibcon#enter sib2, iclass 13, count 0 2006.201.08:14:17.36#ibcon#flushed, iclass 13, count 0 2006.201.08:14:17.36#ibcon#about to write, iclass 13, count 0 2006.201.08:14:17.36#ibcon#wrote, iclass 13, count 0 2006.201.08:14:17.36#ibcon#about to read 3, iclass 13, count 0 2006.201.08:14:17.40#ibcon#read 3, iclass 13, count 0 2006.201.08:14:17.40#ibcon#about to read 4, iclass 13, count 0 2006.201.08:14:17.40#ibcon#read 4, iclass 13, count 0 2006.201.08:14:17.40#ibcon#about to read 5, iclass 13, count 0 2006.201.08:14:17.40#ibcon#read 5, iclass 13, count 0 2006.201.08:14:17.40#ibcon#about to read 6, iclass 13, count 0 2006.201.08:14:17.40#ibcon#read 6, iclass 13, count 0 2006.201.08:14:17.40#ibcon#end of sib2, iclass 13, count 0 2006.201.08:14:17.40#ibcon#*after write, iclass 13, count 0 2006.201.08:14:17.40#ibcon#*before return 0, iclass 13, count 0 2006.201.08:14:17.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:17.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:14:17.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:14:17.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:14:17.40$vck44/vb=7,4 2006.201.08:14:17.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.08:14:17.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.08:14:17.40#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:17.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:17.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:17.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:17.46#ibcon#enter wrdev, iclass 15, count 2 2006.201.08:14:17.46#ibcon#first serial, iclass 15, count 2 2006.201.08:14:17.46#ibcon#enter sib2, iclass 15, count 2 2006.201.08:14:17.46#ibcon#flushed, iclass 15, count 2 2006.201.08:14:17.46#ibcon#about to write, iclass 15, count 2 2006.201.08:14:17.46#ibcon#wrote, iclass 15, count 2 2006.201.08:14:17.46#ibcon#about to read 3, iclass 15, count 2 2006.201.08:14:17.48#ibcon#read 3, iclass 15, count 2 2006.201.08:14:17.48#ibcon#about to read 4, iclass 15, count 2 2006.201.08:14:17.48#ibcon#read 4, iclass 15, count 2 2006.201.08:14:17.48#ibcon#about to read 5, iclass 15, count 2 2006.201.08:14:17.48#ibcon#read 5, iclass 15, count 2 2006.201.08:14:17.48#ibcon#about to read 6, iclass 15, count 2 2006.201.08:14:17.48#ibcon#read 6, iclass 15, count 2 2006.201.08:14:17.48#ibcon#end of sib2, iclass 15, count 2 2006.201.08:14:17.48#ibcon#*mode == 0, iclass 15, count 2 2006.201.08:14:17.48#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.08:14:17.48#ibcon#[27=AT07-04\r\n] 2006.201.08:14:17.48#ibcon#*before write, iclass 15, count 2 2006.201.08:14:17.48#ibcon#enter sib2, iclass 15, count 2 2006.201.08:14:17.48#ibcon#flushed, iclass 15, count 2 2006.201.08:14:17.48#ibcon#about to write, iclass 15, count 2 2006.201.08:14:17.48#ibcon#wrote, iclass 15, count 2 2006.201.08:14:17.48#ibcon#about to read 3, iclass 15, count 2 2006.201.08:14:17.51#ibcon#read 3, iclass 15, count 2 2006.201.08:14:17.51#ibcon#about to read 4, iclass 15, count 2 2006.201.08:14:17.51#ibcon#read 4, iclass 15, count 2 2006.201.08:14:17.51#ibcon#about to read 5, iclass 15, count 2 2006.201.08:14:17.51#ibcon#read 5, iclass 15, count 2 2006.201.08:14:17.51#ibcon#about to read 6, iclass 15, count 2 2006.201.08:14:17.51#ibcon#read 6, iclass 15, count 2 2006.201.08:14:17.51#ibcon#end of sib2, iclass 15, count 2 2006.201.08:14:17.51#ibcon#*after write, iclass 15, count 2 2006.201.08:14:17.51#ibcon#*before return 0, iclass 15, count 2 2006.201.08:14:17.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:17.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:14:17.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.08:14:17.51#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:17.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:17.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:17.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:17.63#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:14:17.63#ibcon#first serial, iclass 15, count 0 2006.201.08:14:17.63#ibcon#enter sib2, iclass 15, count 0 2006.201.08:14:17.63#ibcon#flushed, iclass 15, count 0 2006.201.08:14:17.63#ibcon#about to write, iclass 15, count 0 2006.201.08:14:17.63#ibcon#wrote, iclass 15, count 0 2006.201.08:14:17.63#ibcon#about to read 3, iclass 15, count 0 2006.201.08:14:17.65#ibcon#read 3, iclass 15, count 0 2006.201.08:14:17.65#ibcon#about to read 4, iclass 15, count 0 2006.201.08:14:17.65#ibcon#read 4, iclass 15, count 0 2006.201.08:14:17.65#ibcon#about to read 5, iclass 15, count 0 2006.201.08:14:17.65#ibcon#read 5, iclass 15, count 0 2006.201.08:14:17.65#ibcon#about to read 6, iclass 15, count 0 2006.201.08:14:17.65#ibcon#read 6, iclass 15, count 0 2006.201.08:14:17.65#ibcon#end of sib2, iclass 15, count 0 2006.201.08:14:17.65#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:14:17.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:14:17.65#ibcon#[27=USB\r\n] 2006.201.08:14:17.65#ibcon#*before write, iclass 15, count 0 2006.201.08:14:17.65#ibcon#enter sib2, iclass 15, count 0 2006.201.08:14:17.65#ibcon#flushed, iclass 15, count 0 2006.201.08:14:17.65#ibcon#about to write, iclass 15, count 0 2006.201.08:14:17.65#ibcon#wrote, iclass 15, count 0 2006.201.08:14:17.65#ibcon#about to read 3, iclass 15, count 0 2006.201.08:14:17.68#ibcon#read 3, iclass 15, count 0 2006.201.08:14:17.68#ibcon#about to read 4, iclass 15, count 0 2006.201.08:14:17.68#ibcon#read 4, iclass 15, count 0 2006.201.08:14:17.68#ibcon#about to read 5, iclass 15, count 0 2006.201.08:14:17.68#ibcon#read 5, iclass 15, count 0 2006.201.08:14:17.68#ibcon#about to read 6, iclass 15, count 0 2006.201.08:14:17.68#ibcon#read 6, iclass 15, count 0 2006.201.08:14:17.68#ibcon#end of sib2, iclass 15, count 0 2006.201.08:14:17.68#ibcon#*after write, iclass 15, count 0 2006.201.08:14:17.68#ibcon#*before return 0, iclass 15, count 0 2006.201.08:14:17.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:17.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:14:17.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:14:17.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:14:17.68$vck44/vblo=8,744.99 2006.201.08:14:17.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.08:14:17.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.08:14:17.68#ibcon#ireg 17 cls_cnt 0 2006.201.08:14:17.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:17.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:17.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:17.68#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:14:17.68#ibcon#first serial, iclass 17, count 0 2006.201.08:14:17.68#ibcon#enter sib2, iclass 17, count 0 2006.201.08:14:17.68#ibcon#flushed, iclass 17, count 0 2006.201.08:14:17.68#ibcon#about to write, iclass 17, count 0 2006.201.08:14:17.68#ibcon#wrote, iclass 17, count 0 2006.201.08:14:17.68#ibcon#about to read 3, iclass 17, count 0 2006.201.08:14:17.70#ibcon#read 3, iclass 17, count 0 2006.201.08:14:17.70#ibcon#about to read 4, iclass 17, count 0 2006.201.08:14:17.70#ibcon#read 4, iclass 17, count 0 2006.201.08:14:17.70#ibcon#about to read 5, iclass 17, count 0 2006.201.08:14:17.70#ibcon#read 5, iclass 17, count 0 2006.201.08:14:17.70#ibcon#about to read 6, iclass 17, count 0 2006.201.08:14:17.70#ibcon#read 6, iclass 17, count 0 2006.201.08:14:17.70#ibcon#end of sib2, iclass 17, count 0 2006.201.08:14:17.70#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:14:17.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:14:17.70#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:14:17.70#ibcon#*before write, iclass 17, count 0 2006.201.08:14:17.70#ibcon#enter sib2, iclass 17, count 0 2006.201.08:14:17.70#ibcon#flushed, iclass 17, count 0 2006.201.08:14:17.70#ibcon#about to write, iclass 17, count 0 2006.201.08:14:17.70#ibcon#wrote, iclass 17, count 0 2006.201.08:14:17.70#ibcon#about to read 3, iclass 17, count 0 2006.201.08:14:17.74#ibcon#read 3, iclass 17, count 0 2006.201.08:14:17.74#ibcon#about to read 4, iclass 17, count 0 2006.201.08:14:17.74#ibcon#read 4, iclass 17, count 0 2006.201.08:14:17.74#ibcon#about to read 5, iclass 17, count 0 2006.201.08:14:17.74#ibcon#read 5, iclass 17, count 0 2006.201.08:14:17.74#ibcon#about to read 6, iclass 17, count 0 2006.201.08:14:17.74#ibcon#read 6, iclass 17, count 0 2006.201.08:14:17.74#ibcon#end of sib2, iclass 17, count 0 2006.201.08:14:17.74#ibcon#*after write, iclass 17, count 0 2006.201.08:14:17.74#ibcon#*before return 0, iclass 17, count 0 2006.201.08:14:17.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:17.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:14:17.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:14:17.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:14:17.74$vck44/vb=8,4 2006.201.08:14:17.74#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.08:14:17.74#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.08:14:17.74#ibcon#ireg 11 cls_cnt 2 2006.201.08:14:17.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:17.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:17.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:17.80#ibcon#enter wrdev, iclass 19, count 2 2006.201.08:14:17.80#ibcon#first serial, iclass 19, count 2 2006.201.08:14:17.80#ibcon#enter sib2, iclass 19, count 2 2006.201.08:14:17.80#ibcon#flushed, iclass 19, count 2 2006.201.08:14:17.80#ibcon#about to write, iclass 19, count 2 2006.201.08:14:17.80#ibcon#wrote, iclass 19, count 2 2006.201.08:14:17.80#ibcon#about to read 3, iclass 19, count 2 2006.201.08:14:17.82#ibcon#read 3, iclass 19, count 2 2006.201.08:14:17.82#ibcon#about to read 4, iclass 19, count 2 2006.201.08:14:17.82#ibcon#read 4, iclass 19, count 2 2006.201.08:14:17.82#ibcon#about to read 5, iclass 19, count 2 2006.201.08:14:17.82#ibcon#read 5, iclass 19, count 2 2006.201.08:14:17.82#ibcon#about to read 6, iclass 19, count 2 2006.201.08:14:17.82#ibcon#read 6, iclass 19, count 2 2006.201.08:14:17.82#ibcon#end of sib2, iclass 19, count 2 2006.201.08:14:17.82#ibcon#*mode == 0, iclass 19, count 2 2006.201.08:14:17.82#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.08:14:17.82#ibcon#[27=AT08-04\r\n] 2006.201.08:14:17.82#ibcon#*before write, iclass 19, count 2 2006.201.08:14:17.82#ibcon#enter sib2, iclass 19, count 2 2006.201.08:14:17.82#ibcon#flushed, iclass 19, count 2 2006.201.08:14:17.82#ibcon#about to write, iclass 19, count 2 2006.201.08:14:17.82#ibcon#wrote, iclass 19, count 2 2006.201.08:14:17.82#ibcon#about to read 3, iclass 19, count 2 2006.201.08:14:17.85#ibcon#read 3, iclass 19, count 2 2006.201.08:14:17.85#ibcon#about to read 4, iclass 19, count 2 2006.201.08:14:17.85#ibcon#read 4, iclass 19, count 2 2006.201.08:14:17.85#ibcon#about to read 5, iclass 19, count 2 2006.201.08:14:17.85#ibcon#read 5, iclass 19, count 2 2006.201.08:14:17.85#ibcon#about to read 6, iclass 19, count 2 2006.201.08:14:17.85#ibcon#read 6, iclass 19, count 2 2006.201.08:14:17.85#ibcon#end of sib2, iclass 19, count 2 2006.201.08:14:17.85#ibcon#*after write, iclass 19, count 2 2006.201.08:14:17.85#ibcon#*before return 0, iclass 19, count 2 2006.201.08:14:17.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:17.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:14:17.85#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.08:14:17.85#ibcon#ireg 7 cls_cnt 0 2006.201.08:14:17.85#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:17.97#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:17.97#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:17.97#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:14:17.97#ibcon#first serial, iclass 19, count 0 2006.201.08:14:17.97#ibcon#enter sib2, iclass 19, count 0 2006.201.08:14:17.97#ibcon#flushed, iclass 19, count 0 2006.201.08:14:17.97#ibcon#about to write, iclass 19, count 0 2006.201.08:14:17.97#ibcon#wrote, iclass 19, count 0 2006.201.08:14:17.97#ibcon#about to read 3, iclass 19, count 0 2006.201.08:14:17.99#ibcon#read 3, iclass 19, count 0 2006.201.08:14:17.99#ibcon#about to read 4, iclass 19, count 0 2006.201.08:14:17.99#ibcon#read 4, iclass 19, count 0 2006.201.08:14:17.99#ibcon#about to read 5, iclass 19, count 0 2006.201.08:14:17.99#ibcon#read 5, iclass 19, count 0 2006.201.08:14:17.99#ibcon#about to read 6, iclass 19, count 0 2006.201.08:14:17.99#ibcon#read 6, iclass 19, count 0 2006.201.08:14:17.99#ibcon#end of sib2, iclass 19, count 0 2006.201.08:14:17.99#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:14:17.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:14:17.99#ibcon#[27=USB\r\n] 2006.201.08:14:17.99#ibcon#*before write, iclass 19, count 0 2006.201.08:14:17.99#ibcon#enter sib2, iclass 19, count 0 2006.201.08:14:17.99#ibcon#flushed, iclass 19, count 0 2006.201.08:14:17.99#ibcon#about to write, iclass 19, count 0 2006.201.08:14:17.99#ibcon#wrote, iclass 19, count 0 2006.201.08:14:17.99#ibcon#about to read 3, iclass 19, count 0 2006.201.08:14:18.02#ibcon#read 3, iclass 19, count 0 2006.201.08:14:18.02#ibcon#about to read 4, iclass 19, count 0 2006.201.08:14:18.02#ibcon#read 4, iclass 19, count 0 2006.201.08:14:18.02#ibcon#about to read 5, iclass 19, count 0 2006.201.08:14:18.02#ibcon#read 5, iclass 19, count 0 2006.201.08:14:18.02#ibcon#about to read 6, iclass 19, count 0 2006.201.08:14:18.02#ibcon#read 6, iclass 19, count 0 2006.201.08:14:18.02#ibcon#end of sib2, iclass 19, count 0 2006.201.08:14:18.02#ibcon#*after write, iclass 19, count 0 2006.201.08:14:18.02#ibcon#*before return 0, iclass 19, count 0 2006.201.08:14:18.02#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:18.02#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:14:18.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:14:18.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:14:18.02$vck44/vabw=wide 2006.201.08:14:18.02#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.08:14:18.02#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.08:14:18.02#ibcon#ireg 8 cls_cnt 0 2006.201.08:14:18.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:18.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:18.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:18.02#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:14:18.02#ibcon#first serial, iclass 21, count 0 2006.201.08:14:18.02#ibcon#enter sib2, iclass 21, count 0 2006.201.08:14:18.02#ibcon#flushed, iclass 21, count 0 2006.201.08:14:18.02#ibcon#about to write, iclass 21, count 0 2006.201.08:14:18.02#ibcon#wrote, iclass 21, count 0 2006.201.08:14:18.02#ibcon#about to read 3, iclass 21, count 0 2006.201.08:14:18.04#ibcon#read 3, iclass 21, count 0 2006.201.08:14:18.04#ibcon#about to read 4, iclass 21, count 0 2006.201.08:14:18.04#ibcon#read 4, iclass 21, count 0 2006.201.08:14:18.04#ibcon#about to read 5, iclass 21, count 0 2006.201.08:14:18.04#ibcon#read 5, iclass 21, count 0 2006.201.08:14:18.04#ibcon#about to read 6, iclass 21, count 0 2006.201.08:14:18.04#ibcon#read 6, iclass 21, count 0 2006.201.08:14:18.04#ibcon#end of sib2, iclass 21, count 0 2006.201.08:14:18.04#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:14:18.04#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:14:18.04#ibcon#[25=BW32\r\n] 2006.201.08:14:18.04#ibcon#*before write, iclass 21, count 0 2006.201.08:14:18.04#ibcon#enter sib2, iclass 21, count 0 2006.201.08:14:18.04#ibcon#flushed, iclass 21, count 0 2006.201.08:14:18.04#ibcon#about to write, iclass 21, count 0 2006.201.08:14:18.04#ibcon#wrote, iclass 21, count 0 2006.201.08:14:18.04#ibcon#about to read 3, iclass 21, count 0 2006.201.08:14:18.07#ibcon#read 3, iclass 21, count 0 2006.201.08:14:18.07#ibcon#about to read 4, iclass 21, count 0 2006.201.08:14:18.07#ibcon#read 4, iclass 21, count 0 2006.201.08:14:18.07#ibcon#about to read 5, iclass 21, count 0 2006.201.08:14:18.07#ibcon#read 5, iclass 21, count 0 2006.201.08:14:18.07#ibcon#about to read 6, iclass 21, count 0 2006.201.08:14:18.07#ibcon#read 6, iclass 21, count 0 2006.201.08:14:18.07#ibcon#end of sib2, iclass 21, count 0 2006.201.08:14:18.07#ibcon#*after write, iclass 21, count 0 2006.201.08:14:18.07#ibcon#*before return 0, iclass 21, count 0 2006.201.08:14:18.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:18.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:14:18.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:14:18.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:14:18.07$vck44/vbbw=wide 2006.201.08:14:18.07#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.08:14:18.07#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.08:14:18.07#ibcon#ireg 8 cls_cnt 0 2006.201.08:14:18.07#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:14:18.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:14:18.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:14:18.14#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:14:18.14#ibcon#first serial, iclass 23, count 0 2006.201.08:14:18.14#ibcon#enter sib2, iclass 23, count 0 2006.201.08:14:18.14#ibcon#flushed, iclass 23, count 0 2006.201.08:14:18.14#ibcon#about to write, iclass 23, count 0 2006.201.08:14:18.14#ibcon#wrote, iclass 23, count 0 2006.201.08:14:18.14#ibcon#about to read 3, iclass 23, count 0 2006.201.08:14:18.16#ibcon#read 3, iclass 23, count 0 2006.201.08:14:18.16#ibcon#about to read 4, iclass 23, count 0 2006.201.08:14:18.16#ibcon#read 4, iclass 23, count 0 2006.201.08:14:18.16#ibcon#about to read 5, iclass 23, count 0 2006.201.08:14:18.16#ibcon#read 5, iclass 23, count 0 2006.201.08:14:18.16#ibcon#about to read 6, iclass 23, count 0 2006.201.08:14:18.16#ibcon#read 6, iclass 23, count 0 2006.201.08:14:18.16#ibcon#end of sib2, iclass 23, count 0 2006.201.08:14:18.16#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:14:18.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:14:18.16#ibcon#[27=BW32\r\n] 2006.201.08:14:18.16#ibcon#*before write, iclass 23, count 0 2006.201.08:14:18.16#ibcon#enter sib2, iclass 23, count 0 2006.201.08:14:18.16#ibcon#flushed, iclass 23, count 0 2006.201.08:14:18.16#ibcon#about to write, iclass 23, count 0 2006.201.08:14:18.16#ibcon#wrote, iclass 23, count 0 2006.201.08:14:18.16#ibcon#about to read 3, iclass 23, count 0 2006.201.08:14:18.19#ibcon#read 3, iclass 23, count 0 2006.201.08:14:18.19#ibcon#about to read 4, iclass 23, count 0 2006.201.08:14:18.19#ibcon#read 4, iclass 23, count 0 2006.201.08:14:18.19#ibcon#about to read 5, iclass 23, count 0 2006.201.08:14:18.19#ibcon#read 5, iclass 23, count 0 2006.201.08:14:18.19#ibcon#about to read 6, iclass 23, count 0 2006.201.08:14:18.19#ibcon#read 6, iclass 23, count 0 2006.201.08:14:18.19#ibcon#end of sib2, iclass 23, count 0 2006.201.08:14:18.19#ibcon#*after write, iclass 23, count 0 2006.201.08:14:18.19#ibcon#*before return 0, iclass 23, count 0 2006.201.08:14:18.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:14:18.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:14:18.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:14:18.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:14:18.19$setupk4/ifdk4 2006.201.08:14:18.19$ifdk4/lo= 2006.201.08:14:18.19$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:14:18.19$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:14:18.19$ifdk4/patch= 2006.201.08:14:18.19$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:14:18.19$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:14:18.19$setupk4/!*+20s 2006.201.08:14:24.42#abcon#<5=/04 2.5 4.6 23.21 871003.2\r\n> 2006.201.08:14:24.44#abcon#{5=INTERFACE CLEAR} 2006.201.08:14:24.50#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:14:32.69$setupk4/"tpicd 2006.201.08:14:32.69$setupk4/echo=off 2006.201.08:14:32.69$setupk4/xlog=off 2006.201.08:14:32.69:!2006.201.08:19:47 2006.201.08:15:10.14#trakl#Source acquired 2006.201.08:15:11.14#flagr#flagr/antenna,acquired 2006.201.08:19:47.00:preob 2006.201.08:19:48.14/onsource/TRACKING 2006.201.08:19:48.14:!2006.201.08:19:57 2006.201.08:19:57.00:"tape 2006.201.08:19:57.00:"st=record 2006.201.08:19:57.00:data_valid=on 2006.201.08:19:57.00:midob 2006.201.08:19:57.14/onsource/TRACKING 2006.201.08:19:57.14/wx/23.21,1003.3,87 2006.201.08:19:57.32/cable/+6.4685E-03 2006.201.08:19:58.41/va/01,08,usb,yes,28,30 2006.201.08:19:58.41/va/02,07,usb,yes,30,31 2006.201.08:19:58.41/va/03,08,usb,yes,27,28 2006.201.08:19:58.41/va/04,07,usb,yes,31,33 2006.201.08:19:58.41/va/05,04,usb,yes,27,28 2006.201.08:19:58.41/va/06,05,usb,yes,27,27 2006.201.08:19:58.41/va/07,05,usb,yes,26,28 2006.201.08:19:58.41/va/08,04,usb,yes,26,32 2006.201.08:19:58.64/valo/01,524.99,yes,locked 2006.201.08:19:58.64/valo/02,534.99,yes,locked 2006.201.08:19:58.64/valo/03,564.99,yes,locked 2006.201.08:19:58.64/valo/04,624.99,yes,locked 2006.201.08:19:58.64/valo/05,734.99,yes,locked 2006.201.08:19:58.64/valo/06,814.99,yes,locked 2006.201.08:19:58.64/valo/07,864.99,yes,locked 2006.201.08:19:58.64/valo/08,884.99,yes,locked 2006.201.08:19:59.73/vb/01,04,usb,yes,28,27 2006.201.08:19:59.73/vb/02,05,usb,yes,27,27 2006.201.08:19:59.73/vb/03,04,usb,yes,28,31 2006.201.08:19:59.73/vb/04,05,usb,yes,28,27 2006.201.08:19:59.73/vb/05,04,usb,yes,25,27 2006.201.08:19:59.73/vb/06,04,usb,yes,29,25 2006.201.08:19:59.73/vb/07,04,usb,yes,29,29 2006.201.08:19:59.73/vb/08,04,usb,yes,27,30 2006.201.08:19:59.96/vblo/01,629.99,yes,locked 2006.201.08:19:59.96/vblo/02,634.99,yes,locked 2006.201.08:19:59.96/vblo/03,649.99,yes,locked 2006.201.08:19:59.96/vblo/04,679.99,yes,locked 2006.201.08:19:59.96/vblo/05,709.99,yes,locked 2006.201.08:19:59.96/vblo/06,719.99,yes,locked 2006.201.08:19:59.96/vblo/07,734.99,yes,locked 2006.201.08:19:59.96/vblo/08,744.99,yes,locked 2006.201.08:20:00.11/vabw/8 2006.201.08:20:00.26/vbbw/8 2006.201.08:20:00.35/xfe/off,on,15.2 2006.201.08:20:00.76/ifatt/23,28,28,28 2006.201.08:20:01.05/fmout-gps/S +4.54E-07 2006.201.08:20:01.12:!2006.201.08:23:37 2006.201.08:23:37.00:data_valid=off 2006.201.08:23:37.00:"et 2006.201.08:23:37.00:!+3s 2006.201.08:23:40.02:"tape 2006.201.08:23:40.02:postob 2006.201.08:23:40.17/cable/+6.4657E-03 2006.201.08:23:40.17/wx/23.21,1003.3,87 2006.201.08:23:40.23/fmout-gps/S +4.56E-07 2006.201.08:23:40.23:scan_name=201-0827,jd0607,360 2006.201.08:23:40.23:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.201.08:23:42.14#flagr#flagr/antenna,new-source 2006.201.08:23:42.14:checkk5 2006.201.08:23:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:23:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:23:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:23:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:23:44.01/chk_obsdata//k5ts1/T2010819??a.dat file size is correct (nominal:880MB, actual:880MB). 2006.201.08:23:44.38/chk_obsdata//k5ts2/T2010819??b.dat file size is correct (nominal:880MB, actual:880MB). 2006.201.08:23:44.75/chk_obsdata//k5ts3/T2010819??c.dat file size is correct (nominal:880MB, actual:880MB). 2006.201.08:23:45.11/chk_obsdata//k5ts4/T2010819??d.dat file size is correct (nominal:880MB, actual:880MB). 2006.201.08:23:45.83/k5log//k5ts1_log_newline 2006.201.08:23:46.53/k5log//k5ts2_log_newline 2006.201.08:23:47.22/k5log//k5ts3_log_newline 2006.201.08:23:47.90/k5log//k5ts4_log_newline 2006.201.08:23:47.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:23:47.93:setupk4=1 2006.201.08:23:47.93$setupk4/echo=on 2006.201.08:23:47.93$setupk4/pcalon 2006.201.08:23:47.93$pcalon/"no phase cal control is implemented here 2006.201.08:23:47.93$setupk4/"tpicd=stop 2006.201.08:23:47.93$setupk4/"rec=synch_on 2006.201.08:23:47.93$setupk4/"rec_mode=128 2006.201.08:23:47.93$setupk4/!* 2006.201.08:23:47.93$setupk4/recpk4 2006.201.08:23:47.93$recpk4/recpatch= 2006.201.08:23:47.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:23:47.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:23:47.93$setupk4/vck44 2006.201.08:23:47.93$vck44/valo=1,524.99 2006.201.08:23:47.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.08:23:47.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.08:23:47.93#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:47.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:47.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:47.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:47.93#ibcon#enter wrdev, iclass 36, count 0 2006.201.08:23:47.93#ibcon#first serial, iclass 36, count 0 2006.201.08:23:47.93#ibcon#enter sib2, iclass 36, count 0 2006.201.08:23:47.93#ibcon#flushed, iclass 36, count 0 2006.201.08:23:47.93#ibcon#about to write, iclass 36, count 0 2006.201.08:23:47.93#ibcon#wrote, iclass 36, count 0 2006.201.08:23:47.93#ibcon#about to read 3, iclass 36, count 0 2006.201.08:23:47.97#ibcon#read 3, iclass 36, count 0 2006.201.08:23:47.97#ibcon#about to read 4, iclass 36, count 0 2006.201.08:23:47.97#ibcon#read 4, iclass 36, count 0 2006.201.08:23:47.97#ibcon#about to read 5, iclass 36, count 0 2006.201.08:23:47.97#ibcon#read 5, iclass 36, count 0 2006.201.08:23:47.97#ibcon#about to read 6, iclass 36, count 0 2006.201.08:23:47.97#ibcon#read 6, iclass 36, count 0 2006.201.08:23:47.97#ibcon#end of sib2, iclass 36, count 0 2006.201.08:23:47.97#ibcon#*mode == 0, iclass 36, count 0 2006.201.08:23:47.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.08:23:47.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:23:47.97#ibcon#*before write, iclass 36, count 0 2006.201.08:23:47.97#ibcon#enter sib2, iclass 36, count 0 2006.201.08:23:47.97#ibcon#flushed, iclass 36, count 0 2006.201.08:23:47.97#ibcon#about to write, iclass 36, count 0 2006.201.08:23:47.97#ibcon#wrote, iclass 36, count 0 2006.201.08:23:47.97#ibcon#about to read 3, iclass 36, count 0 2006.201.08:23:48.02#ibcon#read 3, iclass 36, count 0 2006.201.08:23:48.02#ibcon#about to read 4, iclass 36, count 0 2006.201.08:23:48.02#ibcon#read 4, iclass 36, count 0 2006.201.08:23:48.02#ibcon#about to read 5, iclass 36, count 0 2006.201.08:23:48.02#ibcon#read 5, iclass 36, count 0 2006.201.08:23:48.02#ibcon#about to read 6, iclass 36, count 0 2006.201.08:23:48.02#ibcon#read 6, iclass 36, count 0 2006.201.08:23:48.02#ibcon#end of sib2, iclass 36, count 0 2006.201.08:23:48.02#ibcon#*after write, iclass 36, count 0 2006.201.08:23:48.02#ibcon#*before return 0, iclass 36, count 0 2006.201.08:23:48.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:48.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:48.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.08:23:48.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.08:23:48.02$vck44/va=1,8 2006.201.08:23:48.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.08:23:48.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.08:23:48.02#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:48.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:48.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:48.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:48.02#ibcon#enter wrdev, iclass 38, count 2 2006.201.08:23:48.02#ibcon#first serial, iclass 38, count 2 2006.201.08:23:48.02#ibcon#enter sib2, iclass 38, count 2 2006.201.08:23:48.02#ibcon#flushed, iclass 38, count 2 2006.201.08:23:48.02#ibcon#about to write, iclass 38, count 2 2006.201.08:23:48.02#ibcon#wrote, iclass 38, count 2 2006.201.08:23:48.02#ibcon#about to read 3, iclass 38, count 2 2006.201.08:23:48.04#ibcon#read 3, iclass 38, count 2 2006.201.08:23:48.04#ibcon#about to read 4, iclass 38, count 2 2006.201.08:23:48.04#ibcon#read 4, iclass 38, count 2 2006.201.08:23:48.04#ibcon#about to read 5, iclass 38, count 2 2006.201.08:23:48.04#ibcon#read 5, iclass 38, count 2 2006.201.08:23:48.04#ibcon#about to read 6, iclass 38, count 2 2006.201.08:23:48.04#ibcon#read 6, iclass 38, count 2 2006.201.08:23:48.04#ibcon#end of sib2, iclass 38, count 2 2006.201.08:23:48.04#ibcon#*mode == 0, iclass 38, count 2 2006.201.08:23:48.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.08:23:48.04#ibcon#[25=AT01-08\r\n] 2006.201.08:23:48.04#ibcon#*before write, iclass 38, count 2 2006.201.08:23:48.04#ibcon#enter sib2, iclass 38, count 2 2006.201.08:23:48.04#ibcon#flushed, iclass 38, count 2 2006.201.08:23:48.04#ibcon#about to write, iclass 38, count 2 2006.201.08:23:48.04#ibcon#wrote, iclass 38, count 2 2006.201.08:23:48.04#ibcon#about to read 3, iclass 38, count 2 2006.201.08:23:48.07#ibcon#read 3, iclass 38, count 2 2006.201.08:23:48.07#ibcon#about to read 4, iclass 38, count 2 2006.201.08:23:48.07#ibcon#read 4, iclass 38, count 2 2006.201.08:23:48.07#ibcon#about to read 5, iclass 38, count 2 2006.201.08:23:48.07#ibcon#read 5, iclass 38, count 2 2006.201.08:23:48.07#ibcon#about to read 6, iclass 38, count 2 2006.201.08:23:48.07#ibcon#read 6, iclass 38, count 2 2006.201.08:23:48.07#ibcon#end of sib2, iclass 38, count 2 2006.201.08:23:48.07#ibcon#*after write, iclass 38, count 2 2006.201.08:23:48.07#ibcon#*before return 0, iclass 38, count 2 2006.201.08:23:48.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:48.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:48.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.08:23:48.07#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:48.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:48.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:48.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:48.19#ibcon#enter wrdev, iclass 38, count 0 2006.201.08:23:48.19#ibcon#first serial, iclass 38, count 0 2006.201.08:23:48.19#ibcon#enter sib2, iclass 38, count 0 2006.201.08:23:48.19#ibcon#flushed, iclass 38, count 0 2006.201.08:23:48.19#ibcon#about to write, iclass 38, count 0 2006.201.08:23:48.19#ibcon#wrote, iclass 38, count 0 2006.201.08:23:48.19#ibcon#about to read 3, iclass 38, count 0 2006.201.08:23:48.22#ibcon#read 3, iclass 38, count 0 2006.201.08:23:48.22#ibcon#about to read 4, iclass 38, count 0 2006.201.08:23:48.22#ibcon#read 4, iclass 38, count 0 2006.201.08:23:48.22#ibcon#about to read 5, iclass 38, count 0 2006.201.08:23:48.22#ibcon#read 5, iclass 38, count 0 2006.201.08:23:48.22#ibcon#about to read 6, iclass 38, count 0 2006.201.08:23:48.22#ibcon#read 6, iclass 38, count 0 2006.201.08:23:48.22#ibcon#end of sib2, iclass 38, count 0 2006.201.08:23:48.22#ibcon#*mode == 0, iclass 38, count 0 2006.201.08:23:48.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.08:23:48.22#ibcon#[25=USB\r\n] 2006.201.08:23:48.22#ibcon#*before write, iclass 38, count 0 2006.201.08:23:48.22#ibcon#enter sib2, iclass 38, count 0 2006.201.08:23:48.22#ibcon#flushed, iclass 38, count 0 2006.201.08:23:48.22#ibcon#about to write, iclass 38, count 0 2006.201.08:23:48.22#ibcon#wrote, iclass 38, count 0 2006.201.08:23:48.22#ibcon#about to read 3, iclass 38, count 0 2006.201.08:23:48.25#ibcon#read 3, iclass 38, count 0 2006.201.08:23:48.25#ibcon#about to read 4, iclass 38, count 0 2006.201.08:23:48.25#ibcon#read 4, iclass 38, count 0 2006.201.08:23:48.25#ibcon#about to read 5, iclass 38, count 0 2006.201.08:23:48.25#ibcon#read 5, iclass 38, count 0 2006.201.08:23:48.25#ibcon#about to read 6, iclass 38, count 0 2006.201.08:23:48.25#ibcon#read 6, iclass 38, count 0 2006.201.08:23:48.25#ibcon#end of sib2, iclass 38, count 0 2006.201.08:23:48.25#ibcon#*after write, iclass 38, count 0 2006.201.08:23:48.25#ibcon#*before return 0, iclass 38, count 0 2006.201.08:23:48.25#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:48.25#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:48.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.08:23:48.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.08:23:48.25$vck44/valo=2,534.99 2006.201.08:23:48.25#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.08:23:48.25#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.08:23:48.25#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:48.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:48.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:48.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:48.25#ibcon#enter wrdev, iclass 40, count 0 2006.201.08:23:48.25#ibcon#first serial, iclass 40, count 0 2006.201.08:23:48.25#ibcon#enter sib2, iclass 40, count 0 2006.201.08:23:48.25#ibcon#flushed, iclass 40, count 0 2006.201.08:23:48.25#ibcon#about to write, iclass 40, count 0 2006.201.08:23:48.25#ibcon#wrote, iclass 40, count 0 2006.201.08:23:48.25#ibcon#about to read 3, iclass 40, count 0 2006.201.08:23:48.27#ibcon#read 3, iclass 40, count 0 2006.201.08:23:48.27#ibcon#about to read 4, iclass 40, count 0 2006.201.08:23:48.27#ibcon#read 4, iclass 40, count 0 2006.201.08:23:48.27#ibcon#about to read 5, iclass 40, count 0 2006.201.08:23:48.27#ibcon#read 5, iclass 40, count 0 2006.201.08:23:48.27#ibcon#about to read 6, iclass 40, count 0 2006.201.08:23:48.27#ibcon#read 6, iclass 40, count 0 2006.201.08:23:48.27#ibcon#end of sib2, iclass 40, count 0 2006.201.08:23:48.27#ibcon#*mode == 0, iclass 40, count 0 2006.201.08:23:48.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.08:23:48.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:23:48.27#ibcon#*before write, iclass 40, count 0 2006.201.08:23:48.27#ibcon#enter sib2, iclass 40, count 0 2006.201.08:23:48.27#ibcon#flushed, iclass 40, count 0 2006.201.08:23:48.27#ibcon#about to write, iclass 40, count 0 2006.201.08:23:48.27#ibcon#wrote, iclass 40, count 0 2006.201.08:23:48.27#ibcon#about to read 3, iclass 40, count 0 2006.201.08:23:48.31#ibcon#read 3, iclass 40, count 0 2006.201.08:23:48.31#ibcon#about to read 4, iclass 40, count 0 2006.201.08:23:48.31#ibcon#read 4, iclass 40, count 0 2006.201.08:23:48.31#ibcon#about to read 5, iclass 40, count 0 2006.201.08:23:48.31#ibcon#read 5, iclass 40, count 0 2006.201.08:23:48.31#ibcon#about to read 6, iclass 40, count 0 2006.201.08:23:48.31#ibcon#read 6, iclass 40, count 0 2006.201.08:23:48.31#ibcon#end of sib2, iclass 40, count 0 2006.201.08:23:48.31#ibcon#*after write, iclass 40, count 0 2006.201.08:23:48.31#ibcon#*before return 0, iclass 40, count 0 2006.201.08:23:48.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:48.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:48.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.08:23:48.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.08:23:48.31$vck44/va=2,7 2006.201.08:23:48.31#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.08:23:48.31#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.08:23:48.31#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:48.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:48.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:48.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:48.37#ibcon#enter wrdev, iclass 4, count 2 2006.201.08:23:48.37#ibcon#first serial, iclass 4, count 2 2006.201.08:23:48.37#ibcon#enter sib2, iclass 4, count 2 2006.201.08:23:48.37#ibcon#flushed, iclass 4, count 2 2006.201.08:23:48.37#ibcon#about to write, iclass 4, count 2 2006.201.08:23:48.37#ibcon#wrote, iclass 4, count 2 2006.201.08:23:48.37#ibcon#about to read 3, iclass 4, count 2 2006.201.08:23:48.39#ibcon#read 3, iclass 4, count 2 2006.201.08:23:48.39#ibcon#about to read 4, iclass 4, count 2 2006.201.08:23:48.39#ibcon#read 4, iclass 4, count 2 2006.201.08:23:48.39#ibcon#about to read 5, iclass 4, count 2 2006.201.08:23:48.39#ibcon#read 5, iclass 4, count 2 2006.201.08:23:48.39#ibcon#about to read 6, iclass 4, count 2 2006.201.08:23:48.39#ibcon#read 6, iclass 4, count 2 2006.201.08:23:48.39#ibcon#end of sib2, iclass 4, count 2 2006.201.08:23:48.39#ibcon#*mode == 0, iclass 4, count 2 2006.201.08:23:48.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.08:23:48.39#ibcon#[25=AT02-07\r\n] 2006.201.08:23:48.39#ibcon#*before write, iclass 4, count 2 2006.201.08:23:48.39#ibcon#enter sib2, iclass 4, count 2 2006.201.08:23:48.39#ibcon#flushed, iclass 4, count 2 2006.201.08:23:48.39#ibcon#about to write, iclass 4, count 2 2006.201.08:23:48.39#ibcon#wrote, iclass 4, count 2 2006.201.08:23:48.39#ibcon#about to read 3, iclass 4, count 2 2006.201.08:23:48.42#ibcon#read 3, iclass 4, count 2 2006.201.08:23:48.42#ibcon#about to read 4, iclass 4, count 2 2006.201.08:23:48.42#ibcon#read 4, iclass 4, count 2 2006.201.08:23:48.42#ibcon#about to read 5, iclass 4, count 2 2006.201.08:23:48.42#ibcon#read 5, iclass 4, count 2 2006.201.08:23:48.42#ibcon#about to read 6, iclass 4, count 2 2006.201.08:23:48.42#ibcon#read 6, iclass 4, count 2 2006.201.08:23:48.42#ibcon#end of sib2, iclass 4, count 2 2006.201.08:23:48.42#ibcon#*after write, iclass 4, count 2 2006.201.08:23:48.42#ibcon#*before return 0, iclass 4, count 2 2006.201.08:23:48.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:48.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:48.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.08:23:48.42#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:48.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:48.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:48.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:48.54#ibcon#enter wrdev, iclass 4, count 0 2006.201.08:23:48.54#ibcon#first serial, iclass 4, count 0 2006.201.08:23:48.54#ibcon#enter sib2, iclass 4, count 0 2006.201.08:23:48.54#ibcon#flushed, iclass 4, count 0 2006.201.08:23:48.54#ibcon#about to write, iclass 4, count 0 2006.201.08:23:48.54#ibcon#wrote, iclass 4, count 0 2006.201.08:23:48.54#ibcon#about to read 3, iclass 4, count 0 2006.201.08:23:48.56#ibcon#read 3, iclass 4, count 0 2006.201.08:23:48.56#ibcon#about to read 4, iclass 4, count 0 2006.201.08:23:48.56#ibcon#read 4, iclass 4, count 0 2006.201.08:23:48.56#ibcon#about to read 5, iclass 4, count 0 2006.201.08:23:48.56#ibcon#read 5, iclass 4, count 0 2006.201.08:23:48.56#ibcon#about to read 6, iclass 4, count 0 2006.201.08:23:48.56#ibcon#read 6, iclass 4, count 0 2006.201.08:23:48.56#ibcon#end of sib2, iclass 4, count 0 2006.201.08:23:48.56#ibcon#*mode == 0, iclass 4, count 0 2006.201.08:23:48.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.08:23:48.56#ibcon#[25=USB\r\n] 2006.201.08:23:48.56#ibcon#*before write, iclass 4, count 0 2006.201.08:23:48.56#ibcon#enter sib2, iclass 4, count 0 2006.201.08:23:48.56#ibcon#flushed, iclass 4, count 0 2006.201.08:23:48.56#ibcon#about to write, iclass 4, count 0 2006.201.08:23:48.56#ibcon#wrote, iclass 4, count 0 2006.201.08:23:48.56#ibcon#about to read 3, iclass 4, count 0 2006.201.08:23:48.59#ibcon#read 3, iclass 4, count 0 2006.201.08:23:48.59#ibcon#about to read 4, iclass 4, count 0 2006.201.08:23:48.59#ibcon#read 4, iclass 4, count 0 2006.201.08:23:48.59#ibcon#about to read 5, iclass 4, count 0 2006.201.08:23:48.59#ibcon#read 5, iclass 4, count 0 2006.201.08:23:48.59#ibcon#about to read 6, iclass 4, count 0 2006.201.08:23:48.59#ibcon#read 6, iclass 4, count 0 2006.201.08:23:48.59#ibcon#end of sib2, iclass 4, count 0 2006.201.08:23:48.59#ibcon#*after write, iclass 4, count 0 2006.201.08:23:48.59#ibcon#*before return 0, iclass 4, count 0 2006.201.08:23:48.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:48.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:48.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.08:23:48.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.08:23:48.59$vck44/valo=3,564.99 2006.201.08:23:48.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.08:23:48.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.08:23:48.59#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:48.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:48.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:48.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:48.59#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:23:48.59#ibcon#first serial, iclass 6, count 0 2006.201.08:23:48.59#ibcon#enter sib2, iclass 6, count 0 2006.201.08:23:48.59#ibcon#flushed, iclass 6, count 0 2006.201.08:23:48.59#ibcon#about to write, iclass 6, count 0 2006.201.08:23:48.59#ibcon#wrote, iclass 6, count 0 2006.201.08:23:48.59#ibcon#about to read 3, iclass 6, count 0 2006.201.08:23:48.61#ibcon#read 3, iclass 6, count 0 2006.201.08:23:48.61#ibcon#about to read 4, iclass 6, count 0 2006.201.08:23:48.61#ibcon#read 4, iclass 6, count 0 2006.201.08:23:48.61#ibcon#about to read 5, iclass 6, count 0 2006.201.08:23:48.61#ibcon#read 5, iclass 6, count 0 2006.201.08:23:48.61#ibcon#about to read 6, iclass 6, count 0 2006.201.08:23:48.61#ibcon#read 6, iclass 6, count 0 2006.201.08:23:48.61#ibcon#end of sib2, iclass 6, count 0 2006.201.08:23:48.61#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:23:48.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:23:48.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:23:48.61#ibcon#*before write, iclass 6, count 0 2006.201.08:23:48.61#ibcon#enter sib2, iclass 6, count 0 2006.201.08:23:48.61#ibcon#flushed, iclass 6, count 0 2006.201.08:23:48.61#ibcon#about to write, iclass 6, count 0 2006.201.08:23:48.61#ibcon#wrote, iclass 6, count 0 2006.201.08:23:48.61#ibcon#about to read 3, iclass 6, count 0 2006.201.08:23:48.65#ibcon#read 3, iclass 6, count 0 2006.201.08:23:48.65#ibcon#about to read 4, iclass 6, count 0 2006.201.08:23:48.65#ibcon#read 4, iclass 6, count 0 2006.201.08:23:48.65#ibcon#about to read 5, iclass 6, count 0 2006.201.08:23:48.65#ibcon#read 5, iclass 6, count 0 2006.201.08:23:48.65#ibcon#about to read 6, iclass 6, count 0 2006.201.08:23:48.65#ibcon#read 6, iclass 6, count 0 2006.201.08:23:48.65#ibcon#end of sib2, iclass 6, count 0 2006.201.08:23:48.65#ibcon#*after write, iclass 6, count 0 2006.201.08:23:48.65#ibcon#*before return 0, iclass 6, count 0 2006.201.08:23:48.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:48.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:48.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:23:48.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:23:48.65$vck44/va=3,8 2006.201.08:23:48.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.08:23:48.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.08:23:48.65#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:48.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:48.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:48.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:48.71#ibcon#enter wrdev, iclass 10, count 2 2006.201.08:23:48.71#ibcon#first serial, iclass 10, count 2 2006.201.08:23:48.71#ibcon#enter sib2, iclass 10, count 2 2006.201.08:23:48.71#ibcon#flushed, iclass 10, count 2 2006.201.08:23:48.71#ibcon#about to write, iclass 10, count 2 2006.201.08:23:48.71#ibcon#wrote, iclass 10, count 2 2006.201.08:23:48.71#ibcon#about to read 3, iclass 10, count 2 2006.201.08:23:48.73#ibcon#read 3, iclass 10, count 2 2006.201.08:23:48.73#ibcon#about to read 4, iclass 10, count 2 2006.201.08:23:48.73#ibcon#read 4, iclass 10, count 2 2006.201.08:23:48.73#ibcon#about to read 5, iclass 10, count 2 2006.201.08:23:48.73#ibcon#read 5, iclass 10, count 2 2006.201.08:23:48.73#ibcon#about to read 6, iclass 10, count 2 2006.201.08:23:48.73#ibcon#read 6, iclass 10, count 2 2006.201.08:23:48.73#ibcon#end of sib2, iclass 10, count 2 2006.201.08:23:48.73#ibcon#*mode == 0, iclass 10, count 2 2006.201.08:23:48.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.08:23:48.73#ibcon#[25=AT03-08\r\n] 2006.201.08:23:48.73#ibcon#*before write, iclass 10, count 2 2006.201.08:23:48.73#ibcon#enter sib2, iclass 10, count 2 2006.201.08:23:48.73#ibcon#flushed, iclass 10, count 2 2006.201.08:23:48.73#ibcon#about to write, iclass 10, count 2 2006.201.08:23:48.73#ibcon#wrote, iclass 10, count 2 2006.201.08:23:48.73#ibcon#about to read 3, iclass 10, count 2 2006.201.08:23:48.76#ibcon#read 3, iclass 10, count 2 2006.201.08:23:48.76#ibcon#about to read 4, iclass 10, count 2 2006.201.08:23:48.76#ibcon#read 4, iclass 10, count 2 2006.201.08:23:48.76#ibcon#about to read 5, iclass 10, count 2 2006.201.08:23:48.76#ibcon#read 5, iclass 10, count 2 2006.201.08:23:48.76#ibcon#about to read 6, iclass 10, count 2 2006.201.08:23:48.76#ibcon#read 6, iclass 10, count 2 2006.201.08:23:48.76#ibcon#end of sib2, iclass 10, count 2 2006.201.08:23:48.76#ibcon#*after write, iclass 10, count 2 2006.201.08:23:48.76#ibcon#*before return 0, iclass 10, count 2 2006.201.08:23:48.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:48.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:48.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.08:23:48.76#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:48.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:48.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:48.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:48.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.08:23:48.88#ibcon#first serial, iclass 10, count 0 2006.201.08:23:48.88#ibcon#enter sib2, iclass 10, count 0 2006.201.08:23:48.88#ibcon#flushed, iclass 10, count 0 2006.201.08:23:48.88#ibcon#about to write, iclass 10, count 0 2006.201.08:23:48.88#ibcon#wrote, iclass 10, count 0 2006.201.08:23:48.88#ibcon#about to read 3, iclass 10, count 0 2006.201.08:23:48.90#ibcon#read 3, iclass 10, count 0 2006.201.08:23:48.90#ibcon#about to read 4, iclass 10, count 0 2006.201.08:23:48.90#ibcon#read 4, iclass 10, count 0 2006.201.08:23:48.90#ibcon#about to read 5, iclass 10, count 0 2006.201.08:23:48.90#ibcon#read 5, iclass 10, count 0 2006.201.08:23:48.90#ibcon#about to read 6, iclass 10, count 0 2006.201.08:23:48.90#ibcon#read 6, iclass 10, count 0 2006.201.08:23:48.90#ibcon#end of sib2, iclass 10, count 0 2006.201.08:23:48.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.08:23:48.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.08:23:48.90#ibcon#[25=USB\r\n] 2006.201.08:23:48.90#ibcon#*before write, iclass 10, count 0 2006.201.08:23:48.90#ibcon#enter sib2, iclass 10, count 0 2006.201.08:23:48.90#ibcon#flushed, iclass 10, count 0 2006.201.08:23:48.90#ibcon#about to write, iclass 10, count 0 2006.201.08:23:48.90#ibcon#wrote, iclass 10, count 0 2006.201.08:23:48.90#ibcon#about to read 3, iclass 10, count 0 2006.201.08:23:48.93#ibcon#read 3, iclass 10, count 0 2006.201.08:23:48.93#ibcon#about to read 4, iclass 10, count 0 2006.201.08:23:48.93#ibcon#read 4, iclass 10, count 0 2006.201.08:23:48.93#ibcon#about to read 5, iclass 10, count 0 2006.201.08:23:48.93#ibcon#read 5, iclass 10, count 0 2006.201.08:23:48.93#ibcon#about to read 6, iclass 10, count 0 2006.201.08:23:48.93#ibcon#read 6, iclass 10, count 0 2006.201.08:23:48.93#ibcon#end of sib2, iclass 10, count 0 2006.201.08:23:48.93#ibcon#*after write, iclass 10, count 0 2006.201.08:23:48.93#ibcon#*before return 0, iclass 10, count 0 2006.201.08:23:48.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:48.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:48.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.08:23:48.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.08:23:48.93$vck44/valo=4,624.99 2006.201.08:23:48.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.08:23:48.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.08:23:48.93#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:48.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:48.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:48.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:48.93#ibcon#enter wrdev, iclass 12, count 0 2006.201.08:23:48.93#ibcon#first serial, iclass 12, count 0 2006.201.08:23:48.93#ibcon#enter sib2, iclass 12, count 0 2006.201.08:23:48.93#ibcon#flushed, iclass 12, count 0 2006.201.08:23:48.93#ibcon#about to write, iclass 12, count 0 2006.201.08:23:48.93#ibcon#wrote, iclass 12, count 0 2006.201.08:23:48.93#ibcon#about to read 3, iclass 12, count 0 2006.201.08:23:48.95#ibcon#read 3, iclass 12, count 0 2006.201.08:23:48.95#ibcon#about to read 4, iclass 12, count 0 2006.201.08:23:48.95#ibcon#read 4, iclass 12, count 0 2006.201.08:23:48.95#ibcon#about to read 5, iclass 12, count 0 2006.201.08:23:48.95#ibcon#read 5, iclass 12, count 0 2006.201.08:23:48.95#ibcon#about to read 6, iclass 12, count 0 2006.201.08:23:48.95#ibcon#read 6, iclass 12, count 0 2006.201.08:23:48.95#ibcon#end of sib2, iclass 12, count 0 2006.201.08:23:48.95#ibcon#*mode == 0, iclass 12, count 0 2006.201.08:23:48.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.08:23:48.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:23:48.95#ibcon#*before write, iclass 12, count 0 2006.201.08:23:48.95#ibcon#enter sib2, iclass 12, count 0 2006.201.08:23:48.95#ibcon#flushed, iclass 12, count 0 2006.201.08:23:48.95#ibcon#about to write, iclass 12, count 0 2006.201.08:23:48.95#ibcon#wrote, iclass 12, count 0 2006.201.08:23:48.95#ibcon#about to read 3, iclass 12, count 0 2006.201.08:23:48.99#ibcon#read 3, iclass 12, count 0 2006.201.08:23:48.99#ibcon#about to read 4, iclass 12, count 0 2006.201.08:23:48.99#ibcon#read 4, iclass 12, count 0 2006.201.08:23:48.99#ibcon#about to read 5, iclass 12, count 0 2006.201.08:23:48.99#ibcon#read 5, iclass 12, count 0 2006.201.08:23:48.99#ibcon#about to read 6, iclass 12, count 0 2006.201.08:23:48.99#ibcon#read 6, iclass 12, count 0 2006.201.08:23:48.99#ibcon#end of sib2, iclass 12, count 0 2006.201.08:23:48.99#ibcon#*after write, iclass 12, count 0 2006.201.08:23:48.99#ibcon#*before return 0, iclass 12, count 0 2006.201.08:23:48.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:48.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:48.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.08:23:48.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.08:23:48.99$vck44/va=4,7 2006.201.08:23:48.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.08:23:48.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.08:23:48.99#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:48.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:49.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:49.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:49.05#ibcon#enter wrdev, iclass 14, count 2 2006.201.08:23:49.05#ibcon#first serial, iclass 14, count 2 2006.201.08:23:49.05#ibcon#enter sib2, iclass 14, count 2 2006.201.08:23:49.05#ibcon#flushed, iclass 14, count 2 2006.201.08:23:49.05#ibcon#about to write, iclass 14, count 2 2006.201.08:23:49.05#ibcon#wrote, iclass 14, count 2 2006.201.08:23:49.05#ibcon#about to read 3, iclass 14, count 2 2006.201.08:23:49.07#ibcon#read 3, iclass 14, count 2 2006.201.08:23:49.07#ibcon#about to read 4, iclass 14, count 2 2006.201.08:23:49.07#ibcon#read 4, iclass 14, count 2 2006.201.08:23:49.07#ibcon#about to read 5, iclass 14, count 2 2006.201.08:23:49.07#ibcon#read 5, iclass 14, count 2 2006.201.08:23:49.07#ibcon#about to read 6, iclass 14, count 2 2006.201.08:23:49.07#ibcon#read 6, iclass 14, count 2 2006.201.08:23:49.07#ibcon#end of sib2, iclass 14, count 2 2006.201.08:23:49.07#ibcon#*mode == 0, iclass 14, count 2 2006.201.08:23:49.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.08:23:49.07#ibcon#[25=AT04-07\r\n] 2006.201.08:23:49.07#ibcon#*before write, iclass 14, count 2 2006.201.08:23:49.07#ibcon#enter sib2, iclass 14, count 2 2006.201.08:23:49.07#ibcon#flushed, iclass 14, count 2 2006.201.08:23:49.07#ibcon#about to write, iclass 14, count 2 2006.201.08:23:49.07#ibcon#wrote, iclass 14, count 2 2006.201.08:23:49.07#ibcon#about to read 3, iclass 14, count 2 2006.201.08:23:49.10#ibcon#read 3, iclass 14, count 2 2006.201.08:23:49.10#ibcon#about to read 4, iclass 14, count 2 2006.201.08:23:49.10#ibcon#read 4, iclass 14, count 2 2006.201.08:23:49.10#ibcon#about to read 5, iclass 14, count 2 2006.201.08:23:49.10#ibcon#read 5, iclass 14, count 2 2006.201.08:23:49.10#ibcon#about to read 6, iclass 14, count 2 2006.201.08:23:49.10#ibcon#read 6, iclass 14, count 2 2006.201.08:23:49.10#ibcon#end of sib2, iclass 14, count 2 2006.201.08:23:49.10#ibcon#*after write, iclass 14, count 2 2006.201.08:23:49.10#ibcon#*before return 0, iclass 14, count 2 2006.201.08:23:49.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:49.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:49.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.08:23:49.10#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:49.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:49.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:49.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:49.22#ibcon#enter wrdev, iclass 14, count 0 2006.201.08:23:49.22#ibcon#first serial, iclass 14, count 0 2006.201.08:23:49.22#ibcon#enter sib2, iclass 14, count 0 2006.201.08:23:49.22#ibcon#flushed, iclass 14, count 0 2006.201.08:23:49.22#ibcon#about to write, iclass 14, count 0 2006.201.08:23:49.22#ibcon#wrote, iclass 14, count 0 2006.201.08:23:49.22#ibcon#about to read 3, iclass 14, count 0 2006.201.08:23:49.24#ibcon#read 3, iclass 14, count 0 2006.201.08:23:49.24#ibcon#about to read 4, iclass 14, count 0 2006.201.08:23:49.24#ibcon#read 4, iclass 14, count 0 2006.201.08:23:49.24#ibcon#about to read 5, iclass 14, count 0 2006.201.08:23:49.24#ibcon#read 5, iclass 14, count 0 2006.201.08:23:49.24#ibcon#about to read 6, iclass 14, count 0 2006.201.08:23:49.24#ibcon#read 6, iclass 14, count 0 2006.201.08:23:49.24#ibcon#end of sib2, iclass 14, count 0 2006.201.08:23:49.24#ibcon#*mode == 0, iclass 14, count 0 2006.201.08:23:49.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.08:23:49.24#ibcon#[25=USB\r\n] 2006.201.08:23:49.24#ibcon#*before write, iclass 14, count 0 2006.201.08:23:49.24#ibcon#enter sib2, iclass 14, count 0 2006.201.08:23:49.24#ibcon#flushed, iclass 14, count 0 2006.201.08:23:49.24#ibcon#about to write, iclass 14, count 0 2006.201.08:23:49.24#ibcon#wrote, iclass 14, count 0 2006.201.08:23:49.24#ibcon#about to read 3, iclass 14, count 0 2006.201.08:23:49.27#ibcon#read 3, iclass 14, count 0 2006.201.08:23:49.27#ibcon#about to read 4, iclass 14, count 0 2006.201.08:23:49.27#ibcon#read 4, iclass 14, count 0 2006.201.08:23:49.27#ibcon#about to read 5, iclass 14, count 0 2006.201.08:23:49.27#ibcon#read 5, iclass 14, count 0 2006.201.08:23:49.27#ibcon#about to read 6, iclass 14, count 0 2006.201.08:23:49.27#ibcon#read 6, iclass 14, count 0 2006.201.08:23:49.27#ibcon#end of sib2, iclass 14, count 0 2006.201.08:23:49.27#ibcon#*after write, iclass 14, count 0 2006.201.08:23:49.27#ibcon#*before return 0, iclass 14, count 0 2006.201.08:23:49.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:49.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:49.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.08:23:49.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.08:23:49.27$vck44/valo=5,734.99 2006.201.08:23:49.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.08:23:49.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.08:23:49.27#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:49.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:49.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:49.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:49.27#ibcon#enter wrdev, iclass 16, count 0 2006.201.08:23:49.27#ibcon#first serial, iclass 16, count 0 2006.201.08:23:49.27#ibcon#enter sib2, iclass 16, count 0 2006.201.08:23:49.27#ibcon#flushed, iclass 16, count 0 2006.201.08:23:49.27#ibcon#about to write, iclass 16, count 0 2006.201.08:23:49.27#ibcon#wrote, iclass 16, count 0 2006.201.08:23:49.27#ibcon#about to read 3, iclass 16, count 0 2006.201.08:23:49.29#ibcon#read 3, iclass 16, count 0 2006.201.08:23:49.29#ibcon#about to read 4, iclass 16, count 0 2006.201.08:23:49.29#ibcon#read 4, iclass 16, count 0 2006.201.08:23:49.29#ibcon#about to read 5, iclass 16, count 0 2006.201.08:23:49.29#ibcon#read 5, iclass 16, count 0 2006.201.08:23:49.29#ibcon#about to read 6, iclass 16, count 0 2006.201.08:23:49.29#ibcon#read 6, iclass 16, count 0 2006.201.08:23:49.29#ibcon#end of sib2, iclass 16, count 0 2006.201.08:23:49.29#ibcon#*mode == 0, iclass 16, count 0 2006.201.08:23:49.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.08:23:49.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:23:49.29#ibcon#*before write, iclass 16, count 0 2006.201.08:23:49.29#ibcon#enter sib2, iclass 16, count 0 2006.201.08:23:49.29#ibcon#flushed, iclass 16, count 0 2006.201.08:23:49.29#ibcon#about to write, iclass 16, count 0 2006.201.08:23:49.29#ibcon#wrote, iclass 16, count 0 2006.201.08:23:49.29#ibcon#about to read 3, iclass 16, count 0 2006.201.08:23:49.33#ibcon#read 3, iclass 16, count 0 2006.201.08:23:49.33#ibcon#about to read 4, iclass 16, count 0 2006.201.08:23:49.33#ibcon#read 4, iclass 16, count 0 2006.201.08:23:49.33#ibcon#about to read 5, iclass 16, count 0 2006.201.08:23:49.33#ibcon#read 5, iclass 16, count 0 2006.201.08:23:49.33#ibcon#about to read 6, iclass 16, count 0 2006.201.08:23:49.33#ibcon#read 6, iclass 16, count 0 2006.201.08:23:49.33#ibcon#end of sib2, iclass 16, count 0 2006.201.08:23:49.33#ibcon#*after write, iclass 16, count 0 2006.201.08:23:49.33#ibcon#*before return 0, iclass 16, count 0 2006.201.08:23:49.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:49.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:49.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.08:23:49.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.08:23:49.33$vck44/va=5,4 2006.201.08:23:49.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.08:23:49.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.08:23:49.33#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:49.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:49.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:49.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:49.39#ibcon#enter wrdev, iclass 18, count 2 2006.201.08:23:49.39#ibcon#first serial, iclass 18, count 2 2006.201.08:23:49.39#ibcon#enter sib2, iclass 18, count 2 2006.201.08:23:49.39#ibcon#flushed, iclass 18, count 2 2006.201.08:23:49.39#ibcon#about to write, iclass 18, count 2 2006.201.08:23:49.39#ibcon#wrote, iclass 18, count 2 2006.201.08:23:49.39#ibcon#about to read 3, iclass 18, count 2 2006.201.08:23:49.41#ibcon#read 3, iclass 18, count 2 2006.201.08:23:49.41#ibcon#about to read 4, iclass 18, count 2 2006.201.08:23:49.41#ibcon#read 4, iclass 18, count 2 2006.201.08:23:49.41#ibcon#about to read 5, iclass 18, count 2 2006.201.08:23:49.41#ibcon#read 5, iclass 18, count 2 2006.201.08:23:49.41#ibcon#about to read 6, iclass 18, count 2 2006.201.08:23:49.41#ibcon#read 6, iclass 18, count 2 2006.201.08:23:49.41#ibcon#end of sib2, iclass 18, count 2 2006.201.08:23:49.41#ibcon#*mode == 0, iclass 18, count 2 2006.201.08:23:49.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.08:23:49.41#ibcon#[25=AT05-04\r\n] 2006.201.08:23:49.41#ibcon#*before write, iclass 18, count 2 2006.201.08:23:49.41#ibcon#enter sib2, iclass 18, count 2 2006.201.08:23:49.41#ibcon#flushed, iclass 18, count 2 2006.201.08:23:49.41#ibcon#about to write, iclass 18, count 2 2006.201.08:23:49.41#ibcon#wrote, iclass 18, count 2 2006.201.08:23:49.41#ibcon#about to read 3, iclass 18, count 2 2006.201.08:23:49.44#ibcon#read 3, iclass 18, count 2 2006.201.08:23:49.44#ibcon#about to read 4, iclass 18, count 2 2006.201.08:23:49.44#ibcon#read 4, iclass 18, count 2 2006.201.08:23:49.44#ibcon#about to read 5, iclass 18, count 2 2006.201.08:23:49.44#ibcon#read 5, iclass 18, count 2 2006.201.08:23:49.44#ibcon#about to read 6, iclass 18, count 2 2006.201.08:23:49.44#ibcon#read 6, iclass 18, count 2 2006.201.08:23:49.44#ibcon#end of sib2, iclass 18, count 2 2006.201.08:23:49.44#ibcon#*after write, iclass 18, count 2 2006.201.08:23:49.44#ibcon#*before return 0, iclass 18, count 2 2006.201.08:23:49.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:49.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:49.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.08:23:49.44#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:49.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:49.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:49.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:49.56#ibcon#enter wrdev, iclass 18, count 0 2006.201.08:23:49.56#ibcon#first serial, iclass 18, count 0 2006.201.08:23:49.56#ibcon#enter sib2, iclass 18, count 0 2006.201.08:23:49.56#ibcon#flushed, iclass 18, count 0 2006.201.08:23:49.56#ibcon#about to write, iclass 18, count 0 2006.201.08:23:49.56#ibcon#wrote, iclass 18, count 0 2006.201.08:23:49.56#ibcon#about to read 3, iclass 18, count 0 2006.201.08:23:49.58#ibcon#read 3, iclass 18, count 0 2006.201.08:23:49.58#ibcon#about to read 4, iclass 18, count 0 2006.201.08:23:49.58#ibcon#read 4, iclass 18, count 0 2006.201.08:23:49.58#ibcon#about to read 5, iclass 18, count 0 2006.201.08:23:49.58#ibcon#read 5, iclass 18, count 0 2006.201.08:23:49.58#ibcon#about to read 6, iclass 18, count 0 2006.201.08:23:49.58#ibcon#read 6, iclass 18, count 0 2006.201.08:23:49.58#ibcon#end of sib2, iclass 18, count 0 2006.201.08:23:49.58#ibcon#*mode == 0, iclass 18, count 0 2006.201.08:23:49.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.08:23:49.58#ibcon#[25=USB\r\n] 2006.201.08:23:49.58#ibcon#*before write, iclass 18, count 0 2006.201.08:23:49.58#ibcon#enter sib2, iclass 18, count 0 2006.201.08:23:49.58#ibcon#flushed, iclass 18, count 0 2006.201.08:23:49.58#ibcon#about to write, iclass 18, count 0 2006.201.08:23:49.58#ibcon#wrote, iclass 18, count 0 2006.201.08:23:49.58#ibcon#about to read 3, iclass 18, count 0 2006.201.08:23:49.61#ibcon#read 3, iclass 18, count 0 2006.201.08:23:49.61#ibcon#about to read 4, iclass 18, count 0 2006.201.08:23:49.61#ibcon#read 4, iclass 18, count 0 2006.201.08:23:49.61#ibcon#about to read 5, iclass 18, count 0 2006.201.08:23:49.61#ibcon#read 5, iclass 18, count 0 2006.201.08:23:49.61#ibcon#about to read 6, iclass 18, count 0 2006.201.08:23:49.61#ibcon#read 6, iclass 18, count 0 2006.201.08:23:49.61#ibcon#end of sib2, iclass 18, count 0 2006.201.08:23:49.61#ibcon#*after write, iclass 18, count 0 2006.201.08:23:49.61#ibcon#*before return 0, iclass 18, count 0 2006.201.08:23:49.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:49.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:49.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.08:23:49.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.08:23:49.61$vck44/valo=6,814.99 2006.201.08:23:49.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.08:23:49.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.08:23:49.61#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:49.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:49.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:49.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:49.61#ibcon#enter wrdev, iclass 20, count 0 2006.201.08:23:49.61#ibcon#first serial, iclass 20, count 0 2006.201.08:23:49.61#ibcon#enter sib2, iclass 20, count 0 2006.201.08:23:49.61#ibcon#flushed, iclass 20, count 0 2006.201.08:23:49.61#ibcon#about to write, iclass 20, count 0 2006.201.08:23:49.61#ibcon#wrote, iclass 20, count 0 2006.201.08:23:49.61#ibcon#about to read 3, iclass 20, count 0 2006.201.08:23:49.63#ibcon#read 3, iclass 20, count 0 2006.201.08:23:49.63#ibcon#about to read 4, iclass 20, count 0 2006.201.08:23:49.63#ibcon#read 4, iclass 20, count 0 2006.201.08:23:49.63#ibcon#about to read 5, iclass 20, count 0 2006.201.08:23:49.63#ibcon#read 5, iclass 20, count 0 2006.201.08:23:49.63#ibcon#about to read 6, iclass 20, count 0 2006.201.08:23:49.63#ibcon#read 6, iclass 20, count 0 2006.201.08:23:49.63#ibcon#end of sib2, iclass 20, count 0 2006.201.08:23:49.63#ibcon#*mode == 0, iclass 20, count 0 2006.201.08:23:49.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.08:23:49.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:23:49.63#ibcon#*before write, iclass 20, count 0 2006.201.08:23:49.63#ibcon#enter sib2, iclass 20, count 0 2006.201.08:23:49.63#ibcon#flushed, iclass 20, count 0 2006.201.08:23:49.63#ibcon#about to write, iclass 20, count 0 2006.201.08:23:49.63#ibcon#wrote, iclass 20, count 0 2006.201.08:23:49.63#ibcon#about to read 3, iclass 20, count 0 2006.201.08:23:49.68#ibcon#read 3, iclass 20, count 0 2006.201.08:23:49.68#ibcon#about to read 4, iclass 20, count 0 2006.201.08:23:49.68#ibcon#read 4, iclass 20, count 0 2006.201.08:23:49.68#ibcon#about to read 5, iclass 20, count 0 2006.201.08:23:49.68#ibcon#read 5, iclass 20, count 0 2006.201.08:23:49.68#ibcon#about to read 6, iclass 20, count 0 2006.201.08:23:49.68#ibcon#read 6, iclass 20, count 0 2006.201.08:23:49.68#ibcon#end of sib2, iclass 20, count 0 2006.201.08:23:49.68#ibcon#*after write, iclass 20, count 0 2006.201.08:23:49.68#ibcon#*before return 0, iclass 20, count 0 2006.201.08:23:49.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:49.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:49.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.08:23:49.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.08:23:49.68$vck44/va=6,5 2006.201.08:23:49.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.08:23:49.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.08:23:49.68#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:49.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:49.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:49.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:49.73#ibcon#enter wrdev, iclass 22, count 2 2006.201.08:23:49.73#ibcon#first serial, iclass 22, count 2 2006.201.08:23:49.73#ibcon#enter sib2, iclass 22, count 2 2006.201.08:23:49.73#ibcon#flushed, iclass 22, count 2 2006.201.08:23:49.73#ibcon#about to write, iclass 22, count 2 2006.201.08:23:49.73#ibcon#wrote, iclass 22, count 2 2006.201.08:23:49.73#ibcon#about to read 3, iclass 22, count 2 2006.201.08:23:49.75#ibcon#read 3, iclass 22, count 2 2006.201.08:23:49.75#ibcon#about to read 4, iclass 22, count 2 2006.201.08:23:49.75#ibcon#read 4, iclass 22, count 2 2006.201.08:23:49.75#ibcon#about to read 5, iclass 22, count 2 2006.201.08:23:49.75#ibcon#read 5, iclass 22, count 2 2006.201.08:23:49.75#ibcon#about to read 6, iclass 22, count 2 2006.201.08:23:49.75#ibcon#read 6, iclass 22, count 2 2006.201.08:23:49.75#ibcon#end of sib2, iclass 22, count 2 2006.201.08:23:49.75#ibcon#*mode == 0, iclass 22, count 2 2006.201.08:23:49.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.08:23:49.75#ibcon#[25=AT06-05\r\n] 2006.201.08:23:49.75#ibcon#*before write, iclass 22, count 2 2006.201.08:23:49.75#ibcon#enter sib2, iclass 22, count 2 2006.201.08:23:49.75#ibcon#flushed, iclass 22, count 2 2006.201.08:23:49.75#ibcon#about to write, iclass 22, count 2 2006.201.08:23:49.75#ibcon#wrote, iclass 22, count 2 2006.201.08:23:49.75#ibcon#about to read 3, iclass 22, count 2 2006.201.08:23:49.78#ibcon#read 3, iclass 22, count 2 2006.201.08:23:49.78#ibcon#about to read 4, iclass 22, count 2 2006.201.08:23:49.78#ibcon#read 4, iclass 22, count 2 2006.201.08:23:49.78#ibcon#about to read 5, iclass 22, count 2 2006.201.08:23:49.78#ibcon#read 5, iclass 22, count 2 2006.201.08:23:49.78#ibcon#about to read 6, iclass 22, count 2 2006.201.08:23:49.78#ibcon#read 6, iclass 22, count 2 2006.201.08:23:49.78#ibcon#end of sib2, iclass 22, count 2 2006.201.08:23:49.78#ibcon#*after write, iclass 22, count 2 2006.201.08:23:49.78#ibcon#*before return 0, iclass 22, count 2 2006.201.08:23:49.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:49.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:49.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.08:23:49.78#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:49.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:49.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:49.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:49.90#ibcon#enter wrdev, iclass 22, count 0 2006.201.08:23:49.90#ibcon#first serial, iclass 22, count 0 2006.201.08:23:49.90#ibcon#enter sib2, iclass 22, count 0 2006.201.08:23:49.90#ibcon#flushed, iclass 22, count 0 2006.201.08:23:49.90#ibcon#about to write, iclass 22, count 0 2006.201.08:23:49.90#ibcon#wrote, iclass 22, count 0 2006.201.08:23:49.90#ibcon#about to read 3, iclass 22, count 0 2006.201.08:23:49.92#ibcon#read 3, iclass 22, count 0 2006.201.08:23:49.92#ibcon#about to read 4, iclass 22, count 0 2006.201.08:23:49.92#ibcon#read 4, iclass 22, count 0 2006.201.08:23:49.92#ibcon#about to read 5, iclass 22, count 0 2006.201.08:23:49.92#ibcon#read 5, iclass 22, count 0 2006.201.08:23:49.92#ibcon#about to read 6, iclass 22, count 0 2006.201.08:23:49.92#ibcon#read 6, iclass 22, count 0 2006.201.08:23:49.92#ibcon#end of sib2, iclass 22, count 0 2006.201.08:23:49.92#ibcon#*mode == 0, iclass 22, count 0 2006.201.08:23:49.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.08:23:49.92#ibcon#[25=USB\r\n] 2006.201.08:23:49.92#ibcon#*before write, iclass 22, count 0 2006.201.08:23:49.92#ibcon#enter sib2, iclass 22, count 0 2006.201.08:23:49.92#ibcon#flushed, iclass 22, count 0 2006.201.08:23:49.92#ibcon#about to write, iclass 22, count 0 2006.201.08:23:49.92#ibcon#wrote, iclass 22, count 0 2006.201.08:23:49.92#ibcon#about to read 3, iclass 22, count 0 2006.201.08:23:49.95#ibcon#read 3, iclass 22, count 0 2006.201.08:23:49.95#ibcon#about to read 4, iclass 22, count 0 2006.201.08:23:49.95#ibcon#read 4, iclass 22, count 0 2006.201.08:23:49.95#ibcon#about to read 5, iclass 22, count 0 2006.201.08:23:49.95#ibcon#read 5, iclass 22, count 0 2006.201.08:23:49.95#ibcon#about to read 6, iclass 22, count 0 2006.201.08:23:49.95#ibcon#read 6, iclass 22, count 0 2006.201.08:23:49.95#ibcon#end of sib2, iclass 22, count 0 2006.201.08:23:49.95#ibcon#*after write, iclass 22, count 0 2006.201.08:23:49.95#ibcon#*before return 0, iclass 22, count 0 2006.201.08:23:49.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:49.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:49.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.08:23:49.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.08:23:49.95$vck44/valo=7,864.99 2006.201.08:23:49.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.08:23:49.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.08:23:49.95#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:49.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:49.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:49.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:49.95#ibcon#enter wrdev, iclass 24, count 0 2006.201.08:23:49.95#ibcon#first serial, iclass 24, count 0 2006.201.08:23:49.95#ibcon#enter sib2, iclass 24, count 0 2006.201.08:23:49.95#ibcon#flushed, iclass 24, count 0 2006.201.08:23:49.95#ibcon#about to write, iclass 24, count 0 2006.201.08:23:49.95#ibcon#wrote, iclass 24, count 0 2006.201.08:23:49.95#ibcon#about to read 3, iclass 24, count 0 2006.201.08:23:49.97#ibcon#read 3, iclass 24, count 0 2006.201.08:23:49.97#ibcon#about to read 4, iclass 24, count 0 2006.201.08:23:49.97#ibcon#read 4, iclass 24, count 0 2006.201.08:23:49.97#ibcon#about to read 5, iclass 24, count 0 2006.201.08:23:49.97#ibcon#read 5, iclass 24, count 0 2006.201.08:23:49.97#ibcon#about to read 6, iclass 24, count 0 2006.201.08:23:49.97#ibcon#read 6, iclass 24, count 0 2006.201.08:23:49.97#ibcon#end of sib2, iclass 24, count 0 2006.201.08:23:49.97#ibcon#*mode == 0, iclass 24, count 0 2006.201.08:23:49.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.08:23:49.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:23:49.97#ibcon#*before write, iclass 24, count 0 2006.201.08:23:49.97#ibcon#enter sib2, iclass 24, count 0 2006.201.08:23:49.97#ibcon#flushed, iclass 24, count 0 2006.201.08:23:49.97#ibcon#about to write, iclass 24, count 0 2006.201.08:23:49.97#ibcon#wrote, iclass 24, count 0 2006.201.08:23:49.97#ibcon#about to read 3, iclass 24, count 0 2006.201.08:23:50.01#ibcon#read 3, iclass 24, count 0 2006.201.08:23:50.01#ibcon#about to read 4, iclass 24, count 0 2006.201.08:23:50.01#ibcon#read 4, iclass 24, count 0 2006.201.08:23:50.01#ibcon#about to read 5, iclass 24, count 0 2006.201.08:23:50.01#ibcon#read 5, iclass 24, count 0 2006.201.08:23:50.01#ibcon#about to read 6, iclass 24, count 0 2006.201.08:23:50.01#ibcon#read 6, iclass 24, count 0 2006.201.08:23:50.01#ibcon#end of sib2, iclass 24, count 0 2006.201.08:23:50.01#ibcon#*after write, iclass 24, count 0 2006.201.08:23:50.01#ibcon#*before return 0, iclass 24, count 0 2006.201.08:23:50.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:50.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:50.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.08:23:50.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.08:23:50.01$vck44/va=7,5 2006.201.08:23:50.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.08:23:50.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.08:23:50.01#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:50.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:50.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:50.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:50.07#ibcon#enter wrdev, iclass 26, count 2 2006.201.08:23:50.07#ibcon#first serial, iclass 26, count 2 2006.201.08:23:50.07#ibcon#enter sib2, iclass 26, count 2 2006.201.08:23:50.07#ibcon#flushed, iclass 26, count 2 2006.201.08:23:50.07#ibcon#about to write, iclass 26, count 2 2006.201.08:23:50.07#ibcon#wrote, iclass 26, count 2 2006.201.08:23:50.07#ibcon#about to read 3, iclass 26, count 2 2006.201.08:23:50.09#ibcon#read 3, iclass 26, count 2 2006.201.08:23:50.09#ibcon#about to read 4, iclass 26, count 2 2006.201.08:23:50.09#ibcon#read 4, iclass 26, count 2 2006.201.08:23:50.09#ibcon#about to read 5, iclass 26, count 2 2006.201.08:23:50.09#ibcon#read 5, iclass 26, count 2 2006.201.08:23:50.09#ibcon#about to read 6, iclass 26, count 2 2006.201.08:23:50.09#ibcon#read 6, iclass 26, count 2 2006.201.08:23:50.09#ibcon#end of sib2, iclass 26, count 2 2006.201.08:23:50.09#ibcon#*mode == 0, iclass 26, count 2 2006.201.08:23:50.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.08:23:50.09#ibcon#[25=AT07-05\r\n] 2006.201.08:23:50.09#ibcon#*before write, iclass 26, count 2 2006.201.08:23:50.09#ibcon#enter sib2, iclass 26, count 2 2006.201.08:23:50.09#ibcon#flushed, iclass 26, count 2 2006.201.08:23:50.09#ibcon#about to write, iclass 26, count 2 2006.201.08:23:50.09#ibcon#wrote, iclass 26, count 2 2006.201.08:23:50.09#ibcon#about to read 3, iclass 26, count 2 2006.201.08:23:50.12#ibcon#read 3, iclass 26, count 2 2006.201.08:23:50.12#ibcon#about to read 4, iclass 26, count 2 2006.201.08:23:50.12#ibcon#read 4, iclass 26, count 2 2006.201.08:23:50.12#ibcon#about to read 5, iclass 26, count 2 2006.201.08:23:50.12#ibcon#read 5, iclass 26, count 2 2006.201.08:23:50.12#ibcon#about to read 6, iclass 26, count 2 2006.201.08:23:50.12#ibcon#read 6, iclass 26, count 2 2006.201.08:23:50.12#ibcon#end of sib2, iclass 26, count 2 2006.201.08:23:50.12#ibcon#*after write, iclass 26, count 2 2006.201.08:23:50.12#ibcon#*before return 0, iclass 26, count 2 2006.201.08:23:50.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:50.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:50.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.08:23:50.12#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:50.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:50.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:50.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:50.24#ibcon#enter wrdev, iclass 26, count 0 2006.201.08:23:50.24#ibcon#first serial, iclass 26, count 0 2006.201.08:23:50.24#ibcon#enter sib2, iclass 26, count 0 2006.201.08:23:50.24#ibcon#flushed, iclass 26, count 0 2006.201.08:23:50.24#ibcon#about to write, iclass 26, count 0 2006.201.08:23:50.24#ibcon#wrote, iclass 26, count 0 2006.201.08:23:50.24#ibcon#about to read 3, iclass 26, count 0 2006.201.08:23:50.26#ibcon#read 3, iclass 26, count 0 2006.201.08:23:50.26#ibcon#about to read 4, iclass 26, count 0 2006.201.08:23:50.26#ibcon#read 4, iclass 26, count 0 2006.201.08:23:50.26#ibcon#about to read 5, iclass 26, count 0 2006.201.08:23:50.26#ibcon#read 5, iclass 26, count 0 2006.201.08:23:50.26#ibcon#about to read 6, iclass 26, count 0 2006.201.08:23:50.26#ibcon#read 6, iclass 26, count 0 2006.201.08:23:50.26#ibcon#end of sib2, iclass 26, count 0 2006.201.08:23:50.26#ibcon#*mode == 0, iclass 26, count 0 2006.201.08:23:50.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.08:23:50.26#ibcon#[25=USB\r\n] 2006.201.08:23:50.26#ibcon#*before write, iclass 26, count 0 2006.201.08:23:50.26#ibcon#enter sib2, iclass 26, count 0 2006.201.08:23:50.26#ibcon#flushed, iclass 26, count 0 2006.201.08:23:50.26#ibcon#about to write, iclass 26, count 0 2006.201.08:23:50.26#ibcon#wrote, iclass 26, count 0 2006.201.08:23:50.26#ibcon#about to read 3, iclass 26, count 0 2006.201.08:23:50.29#ibcon#read 3, iclass 26, count 0 2006.201.08:23:50.29#ibcon#about to read 4, iclass 26, count 0 2006.201.08:23:50.29#ibcon#read 4, iclass 26, count 0 2006.201.08:23:50.29#ibcon#about to read 5, iclass 26, count 0 2006.201.08:23:50.29#ibcon#read 5, iclass 26, count 0 2006.201.08:23:50.29#ibcon#about to read 6, iclass 26, count 0 2006.201.08:23:50.29#ibcon#read 6, iclass 26, count 0 2006.201.08:23:50.29#ibcon#end of sib2, iclass 26, count 0 2006.201.08:23:50.29#ibcon#*after write, iclass 26, count 0 2006.201.08:23:50.29#ibcon#*before return 0, iclass 26, count 0 2006.201.08:23:50.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:50.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:50.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.08:23:50.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.08:23:50.29$vck44/valo=8,884.99 2006.201.08:23:50.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.08:23:50.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.08:23:50.29#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:50.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:50.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:50.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:50.29#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:23:50.29#ibcon#first serial, iclass 28, count 0 2006.201.08:23:50.29#ibcon#enter sib2, iclass 28, count 0 2006.201.08:23:50.29#ibcon#flushed, iclass 28, count 0 2006.201.08:23:50.29#ibcon#about to write, iclass 28, count 0 2006.201.08:23:50.29#ibcon#wrote, iclass 28, count 0 2006.201.08:23:50.29#ibcon#about to read 3, iclass 28, count 0 2006.201.08:23:50.31#ibcon#read 3, iclass 28, count 0 2006.201.08:23:50.31#ibcon#about to read 4, iclass 28, count 0 2006.201.08:23:50.31#ibcon#read 4, iclass 28, count 0 2006.201.08:23:50.31#ibcon#about to read 5, iclass 28, count 0 2006.201.08:23:50.31#ibcon#read 5, iclass 28, count 0 2006.201.08:23:50.31#ibcon#about to read 6, iclass 28, count 0 2006.201.08:23:50.31#ibcon#read 6, iclass 28, count 0 2006.201.08:23:50.31#ibcon#end of sib2, iclass 28, count 0 2006.201.08:23:50.31#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:23:50.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:23:50.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:23:50.31#ibcon#*before write, iclass 28, count 0 2006.201.08:23:50.31#ibcon#enter sib2, iclass 28, count 0 2006.201.08:23:50.31#ibcon#flushed, iclass 28, count 0 2006.201.08:23:50.31#ibcon#about to write, iclass 28, count 0 2006.201.08:23:50.31#ibcon#wrote, iclass 28, count 0 2006.201.08:23:50.31#ibcon#about to read 3, iclass 28, count 0 2006.201.08:23:50.35#ibcon#read 3, iclass 28, count 0 2006.201.08:23:50.35#ibcon#about to read 4, iclass 28, count 0 2006.201.08:23:50.35#ibcon#read 4, iclass 28, count 0 2006.201.08:23:50.35#ibcon#about to read 5, iclass 28, count 0 2006.201.08:23:50.35#ibcon#read 5, iclass 28, count 0 2006.201.08:23:50.35#ibcon#about to read 6, iclass 28, count 0 2006.201.08:23:50.35#ibcon#read 6, iclass 28, count 0 2006.201.08:23:50.35#ibcon#end of sib2, iclass 28, count 0 2006.201.08:23:50.35#ibcon#*after write, iclass 28, count 0 2006.201.08:23:50.35#ibcon#*before return 0, iclass 28, count 0 2006.201.08:23:50.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:50.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:50.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:23:50.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:23:50.35$vck44/va=8,4 2006.201.08:23:50.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.08:23:50.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.08:23:50.35#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:50.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:23:50.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:23:50.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:23:50.41#ibcon#enter wrdev, iclass 30, count 2 2006.201.08:23:50.41#ibcon#first serial, iclass 30, count 2 2006.201.08:23:50.41#ibcon#enter sib2, iclass 30, count 2 2006.201.08:23:50.41#ibcon#flushed, iclass 30, count 2 2006.201.08:23:50.41#ibcon#about to write, iclass 30, count 2 2006.201.08:23:50.41#ibcon#wrote, iclass 30, count 2 2006.201.08:23:50.41#ibcon#about to read 3, iclass 30, count 2 2006.201.08:23:50.43#ibcon#read 3, iclass 30, count 2 2006.201.08:23:50.43#ibcon#about to read 4, iclass 30, count 2 2006.201.08:23:50.43#ibcon#read 4, iclass 30, count 2 2006.201.08:23:50.43#ibcon#about to read 5, iclass 30, count 2 2006.201.08:23:50.43#ibcon#read 5, iclass 30, count 2 2006.201.08:23:50.43#ibcon#about to read 6, iclass 30, count 2 2006.201.08:23:50.43#ibcon#read 6, iclass 30, count 2 2006.201.08:23:50.43#ibcon#end of sib2, iclass 30, count 2 2006.201.08:23:50.43#ibcon#*mode == 0, iclass 30, count 2 2006.201.08:23:50.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.08:23:50.43#ibcon#[25=AT08-04\r\n] 2006.201.08:23:50.43#ibcon#*before write, iclass 30, count 2 2006.201.08:23:50.43#ibcon#enter sib2, iclass 30, count 2 2006.201.08:23:50.43#ibcon#flushed, iclass 30, count 2 2006.201.08:23:50.43#ibcon#about to write, iclass 30, count 2 2006.201.08:23:50.43#ibcon#wrote, iclass 30, count 2 2006.201.08:23:50.43#ibcon#about to read 3, iclass 30, count 2 2006.201.08:23:50.46#ibcon#read 3, iclass 30, count 2 2006.201.08:23:50.46#ibcon#about to read 4, iclass 30, count 2 2006.201.08:23:50.46#ibcon#read 4, iclass 30, count 2 2006.201.08:23:50.46#ibcon#about to read 5, iclass 30, count 2 2006.201.08:23:50.46#ibcon#read 5, iclass 30, count 2 2006.201.08:23:50.46#ibcon#about to read 6, iclass 30, count 2 2006.201.08:23:50.46#ibcon#read 6, iclass 30, count 2 2006.201.08:23:50.46#ibcon#end of sib2, iclass 30, count 2 2006.201.08:23:50.46#ibcon#*after write, iclass 30, count 2 2006.201.08:23:50.46#ibcon#*before return 0, iclass 30, count 2 2006.201.08:23:50.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:23:50.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:23:50.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.08:23:50.46#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:50.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:23:50.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:23:50.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:23:50.58#ibcon#enter wrdev, iclass 30, count 0 2006.201.08:23:50.58#ibcon#first serial, iclass 30, count 0 2006.201.08:23:50.58#ibcon#enter sib2, iclass 30, count 0 2006.201.08:23:50.58#ibcon#flushed, iclass 30, count 0 2006.201.08:23:50.58#ibcon#about to write, iclass 30, count 0 2006.201.08:23:50.58#ibcon#wrote, iclass 30, count 0 2006.201.08:23:50.58#ibcon#about to read 3, iclass 30, count 0 2006.201.08:23:50.60#ibcon#read 3, iclass 30, count 0 2006.201.08:23:50.60#ibcon#about to read 4, iclass 30, count 0 2006.201.08:23:50.60#ibcon#read 4, iclass 30, count 0 2006.201.08:23:50.60#ibcon#about to read 5, iclass 30, count 0 2006.201.08:23:50.60#ibcon#read 5, iclass 30, count 0 2006.201.08:23:50.60#ibcon#about to read 6, iclass 30, count 0 2006.201.08:23:50.60#ibcon#read 6, iclass 30, count 0 2006.201.08:23:50.60#ibcon#end of sib2, iclass 30, count 0 2006.201.08:23:50.60#ibcon#*mode == 0, iclass 30, count 0 2006.201.08:23:50.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.08:23:50.60#ibcon#[25=USB\r\n] 2006.201.08:23:50.60#ibcon#*before write, iclass 30, count 0 2006.201.08:23:50.60#ibcon#enter sib2, iclass 30, count 0 2006.201.08:23:50.60#ibcon#flushed, iclass 30, count 0 2006.201.08:23:50.60#ibcon#about to write, iclass 30, count 0 2006.201.08:23:50.60#ibcon#wrote, iclass 30, count 0 2006.201.08:23:50.60#ibcon#about to read 3, iclass 30, count 0 2006.201.08:23:50.63#ibcon#read 3, iclass 30, count 0 2006.201.08:23:50.63#ibcon#about to read 4, iclass 30, count 0 2006.201.08:23:50.63#ibcon#read 4, iclass 30, count 0 2006.201.08:23:50.63#ibcon#about to read 5, iclass 30, count 0 2006.201.08:23:50.63#ibcon#read 5, iclass 30, count 0 2006.201.08:23:50.63#ibcon#about to read 6, iclass 30, count 0 2006.201.08:23:50.63#ibcon#read 6, iclass 30, count 0 2006.201.08:23:50.63#ibcon#end of sib2, iclass 30, count 0 2006.201.08:23:50.63#ibcon#*after write, iclass 30, count 0 2006.201.08:23:50.63#ibcon#*before return 0, iclass 30, count 0 2006.201.08:23:50.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:23:50.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:23:50.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.08:23:50.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.08:23:50.63$vck44/vblo=1,629.99 2006.201.08:23:50.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.08:23:50.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.08:23:50.63#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:50.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:23:50.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:23:50.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:23:50.63#ibcon#enter wrdev, iclass 32, count 0 2006.201.08:23:50.63#ibcon#first serial, iclass 32, count 0 2006.201.08:23:50.63#ibcon#enter sib2, iclass 32, count 0 2006.201.08:23:50.63#ibcon#flushed, iclass 32, count 0 2006.201.08:23:50.63#ibcon#about to write, iclass 32, count 0 2006.201.08:23:50.63#ibcon#wrote, iclass 32, count 0 2006.201.08:23:50.63#ibcon#about to read 3, iclass 32, count 0 2006.201.08:23:50.65#ibcon#read 3, iclass 32, count 0 2006.201.08:23:50.65#ibcon#about to read 4, iclass 32, count 0 2006.201.08:23:50.65#ibcon#read 4, iclass 32, count 0 2006.201.08:23:50.65#ibcon#about to read 5, iclass 32, count 0 2006.201.08:23:50.65#ibcon#read 5, iclass 32, count 0 2006.201.08:23:50.65#ibcon#about to read 6, iclass 32, count 0 2006.201.08:23:50.65#ibcon#read 6, iclass 32, count 0 2006.201.08:23:50.65#ibcon#end of sib2, iclass 32, count 0 2006.201.08:23:50.65#ibcon#*mode == 0, iclass 32, count 0 2006.201.08:23:50.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.08:23:50.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:23:50.65#ibcon#*before write, iclass 32, count 0 2006.201.08:23:50.65#ibcon#enter sib2, iclass 32, count 0 2006.201.08:23:50.65#ibcon#flushed, iclass 32, count 0 2006.201.08:23:50.65#ibcon#about to write, iclass 32, count 0 2006.201.08:23:50.65#ibcon#wrote, iclass 32, count 0 2006.201.08:23:50.65#ibcon#about to read 3, iclass 32, count 0 2006.201.08:23:50.70#ibcon#read 3, iclass 32, count 0 2006.201.08:23:50.70#ibcon#about to read 4, iclass 32, count 0 2006.201.08:23:50.70#ibcon#read 4, iclass 32, count 0 2006.201.08:23:50.70#ibcon#about to read 5, iclass 32, count 0 2006.201.08:23:50.70#ibcon#read 5, iclass 32, count 0 2006.201.08:23:50.70#ibcon#about to read 6, iclass 32, count 0 2006.201.08:23:50.70#ibcon#read 6, iclass 32, count 0 2006.201.08:23:50.70#ibcon#end of sib2, iclass 32, count 0 2006.201.08:23:50.70#ibcon#*after write, iclass 32, count 0 2006.201.08:23:50.70#ibcon#*before return 0, iclass 32, count 0 2006.201.08:23:50.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:23:50.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:23:50.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.08:23:50.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.08:23:50.70$vck44/vb=1,4 2006.201.08:23:50.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.08:23:50.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.08:23:50.70#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:50.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:23:50.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:23:50.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:23:50.70#ibcon#enter wrdev, iclass 34, count 2 2006.201.08:23:50.70#ibcon#first serial, iclass 34, count 2 2006.201.08:23:50.70#ibcon#enter sib2, iclass 34, count 2 2006.201.08:23:50.70#ibcon#flushed, iclass 34, count 2 2006.201.08:23:50.70#ibcon#about to write, iclass 34, count 2 2006.201.08:23:50.70#ibcon#wrote, iclass 34, count 2 2006.201.08:23:50.70#ibcon#about to read 3, iclass 34, count 2 2006.201.08:23:50.72#ibcon#read 3, iclass 34, count 2 2006.201.08:23:50.72#ibcon#about to read 4, iclass 34, count 2 2006.201.08:23:50.72#ibcon#read 4, iclass 34, count 2 2006.201.08:23:50.72#ibcon#about to read 5, iclass 34, count 2 2006.201.08:23:50.72#ibcon#read 5, iclass 34, count 2 2006.201.08:23:50.72#ibcon#about to read 6, iclass 34, count 2 2006.201.08:23:50.72#ibcon#read 6, iclass 34, count 2 2006.201.08:23:50.72#ibcon#end of sib2, iclass 34, count 2 2006.201.08:23:50.72#ibcon#*mode == 0, iclass 34, count 2 2006.201.08:23:50.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.08:23:50.72#ibcon#[27=AT01-04\r\n] 2006.201.08:23:50.72#ibcon#*before write, iclass 34, count 2 2006.201.08:23:50.72#ibcon#enter sib2, iclass 34, count 2 2006.201.08:23:50.72#ibcon#flushed, iclass 34, count 2 2006.201.08:23:50.72#ibcon#about to write, iclass 34, count 2 2006.201.08:23:50.72#ibcon#wrote, iclass 34, count 2 2006.201.08:23:50.72#ibcon#about to read 3, iclass 34, count 2 2006.201.08:23:50.75#ibcon#read 3, iclass 34, count 2 2006.201.08:23:50.75#ibcon#about to read 4, iclass 34, count 2 2006.201.08:23:50.75#ibcon#read 4, iclass 34, count 2 2006.201.08:23:50.75#ibcon#about to read 5, iclass 34, count 2 2006.201.08:23:50.75#ibcon#read 5, iclass 34, count 2 2006.201.08:23:50.75#ibcon#about to read 6, iclass 34, count 2 2006.201.08:23:50.75#ibcon#read 6, iclass 34, count 2 2006.201.08:23:50.75#ibcon#end of sib2, iclass 34, count 2 2006.201.08:23:50.75#ibcon#*after write, iclass 34, count 2 2006.201.08:23:50.75#ibcon#*before return 0, iclass 34, count 2 2006.201.08:23:50.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:23:50.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:23:50.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.08:23:50.75#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:50.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:23:50.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:23:50.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:23:50.87#ibcon#enter wrdev, iclass 34, count 0 2006.201.08:23:50.87#ibcon#first serial, iclass 34, count 0 2006.201.08:23:50.87#ibcon#enter sib2, iclass 34, count 0 2006.201.08:23:50.87#ibcon#flushed, iclass 34, count 0 2006.201.08:23:50.87#ibcon#about to write, iclass 34, count 0 2006.201.08:23:50.87#ibcon#wrote, iclass 34, count 0 2006.201.08:23:50.87#ibcon#about to read 3, iclass 34, count 0 2006.201.08:23:50.89#ibcon#read 3, iclass 34, count 0 2006.201.08:23:50.89#ibcon#about to read 4, iclass 34, count 0 2006.201.08:23:50.89#ibcon#read 4, iclass 34, count 0 2006.201.08:23:50.89#ibcon#about to read 5, iclass 34, count 0 2006.201.08:23:50.89#ibcon#read 5, iclass 34, count 0 2006.201.08:23:50.89#ibcon#about to read 6, iclass 34, count 0 2006.201.08:23:50.89#ibcon#read 6, iclass 34, count 0 2006.201.08:23:50.89#ibcon#end of sib2, iclass 34, count 0 2006.201.08:23:50.89#ibcon#*mode == 0, iclass 34, count 0 2006.201.08:23:50.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.08:23:50.89#ibcon#[27=USB\r\n] 2006.201.08:23:50.89#ibcon#*before write, iclass 34, count 0 2006.201.08:23:50.89#ibcon#enter sib2, iclass 34, count 0 2006.201.08:23:50.89#ibcon#flushed, iclass 34, count 0 2006.201.08:23:50.89#ibcon#about to write, iclass 34, count 0 2006.201.08:23:50.89#ibcon#wrote, iclass 34, count 0 2006.201.08:23:50.89#ibcon#about to read 3, iclass 34, count 0 2006.201.08:23:50.92#ibcon#read 3, iclass 34, count 0 2006.201.08:23:50.92#ibcon#about to read 4, iclass 34, count 0 2006.201.08:23:50.92#ibcon#read 4, iclass 34, count 0 2006.201.08:23:50.92#ibcon#about to read 5, iclass 34, count 0 2006.201.08:23:50.92#ibcon#read 5, iclass 34, count 0 2006.201.08:23:50.92#ibcon#about to read 6, iclass 34, count 0 2006.201.08:23:50.92#ibcon#read 6, iclass 34, count 0 2006.201.08:23:50.92#ibcon#end of sib2, iclass 34, count 0 2006.201.08:23:50.92#ibcon#*after write, iclass 34, count 0 2006.201.08:23:50.92#ibcon#*before return 0, iclass 34, count 0 2006.201.08:23:50.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:23:50.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:23:50.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.08:23:50.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.08:23:50.92$vck44/vblo=2,634.99 2006.201.08:23:50.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.08:23:50.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.08:23:50.92#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:50.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:50.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:50.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:50.92#ibcon#enter wrdev, iclass 36, count 0 2006.201.08:23:50.92#ibcon#first serial, iclass 36, count 0 2006.201.08:23:50.92#ibcon#enter sib2, iclass 36, count 0 2006.201.08:23:50.92#ibcon#flushed, iclass 36, count 0 2006.201.08:23:50.92#ibcon#about to write, iclass 36, count 0 2006.201.08:23:50.92#ibcon#wrote, iclass 36, count 0 2006.201.08:23:50.92#ibcon#about to read 3, iclass 36, count 0 2006.201.08:23:50.94#ibcon#read 3, iclass 36, count 0 2006.201.08:23:50.94#ibcon#about to read 4, iclass 36, count 0 2006.201.08:23:50.94#ibcon#read 4, iclass 36, count 0 2006.201.08:23:50.94#ibcon#about to read 5, iclass 36, count 0 2006.201.08:23:50.94#ibcon#read 5, iclass 36, count 0 2006.201.08:23:50.94#ibcon#about to read 6, iclass 36, count 0 2006.201.08:23:50.94#ibcon#read 6, iclass 36, count 0 2006.201.08:23:50.94#ibcon#end of sib2, iclass 36, count 0 2006.201.08:23:50.94#ibcon#*mode == 0, iclass 36, count 0 2006.201.08:23:50.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.08:23:50.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:23:50.94#ibcon#*before write, iclass 36, count 0 2006.201.08:23:50.94#ibcon#enter sib2, iclass 36, count 0 2006.201.08:23:50.94#ibcon#flushed, iclass 36, count 0 2006.201.08:23:50.94#ibcon#about to write, iclass 36, count 0 2006.201.08:23:50.94#ibcon#wrote, iclass 36, count 0 2006.201.08:23:50.94#ibcon#about to read 3, iclass 36, count 0 2006.201.08:23:50.98#ibcon#read 3, iclass 36, count 0 2006.201.08:23:50.98#ibcon#about to read 4, iclass 36, count 0 2006.201.08:23:50.98#ibcon#read 4, iclass 36, count 0 2006.201.08:23:50.98#ibcon#about to read 5, iclass 36, count 0 2006.201.08:23:50.98#ibcon#read 5, iclass 36, count 0 2006.201.08:23:50.98#ibcon#about to read 6, iclass 36, count 0 2006.201.08:23:50.98#ibcon#read 6, iclass 36, count 0 2006.201.08:23:50.98#ibcon#end of sib2, iclass 36, count 0 2006.201.08:23:50.98#ibcon#*after write, iclass 36, count 0 2006.201.08:23:50.98#ibcon#*before return 0, iclass 36, count 0 2006.201.08:23:50.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:50.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:23:50.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.08:23:50.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.08:23:50.98$vck44/vb=2,5 2006.201.08:23:50.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.08:23:50.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.08:23:50.98#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:50.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:51.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:51.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:51.04#ibcon#enter wrdev, iclass 38, count 2 2006.201.08:23:51.04#ibcon#first serial, iclass 38, count 2 2006.201.08:23:51.04#ibcon#enter sib2, iclass 38, count 2 2006.201.08:23:51.04#ibcon#flushed, iclass 38, count 2 2006.201.08:23:51.04#ibcon#about to write, iclass 38, count 2 2006.201.08:23:51.04#ibcon#wrote, iclass 38, count 2 2006.201.08:23:51.04#ibcon#about to read 3, iclass 38, count 2 2006.201.08:23:51.06#ibcon#read 3, iclass 38, count 2 2006.201.08:23:51.06#ibcon#about to read 4, iclass 38, count 2 2006.201.08:23:51.06#ibcon#read 4, iclass 38, count 2 2006.201.08:23:51.06#ibcon#about to read 5, iclass 38, count 2 2006.201.08:23:51.06#ibcon#read 5, iclass 38, count 2 2006.201.08:23:51.06#ibcon#about to read 6, iclass 38, count 2 2006.201.08:23:51.06#ibcon#read 6, iclass 38, count 2 2006.201.08:23:51.06#ibcon#end of sib2, iclass 38, count 2 2006.201.08:23:51.06#ibcon#*mode == 0, iclass 38, count 2 2006.201.08:23:51.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.08:23:51.06#ibcon#[27=AT02-05\r\n] 2006.201.08:23:51.06#ibcon#*before write, iclass 38, count 2 2006.201.08:23:51.06#ibcon#enter sib2, iclass 38, count 2 2006.201.08:23:51.06#ibcon#flushed, iclass 38, count 2 2006.201.08:23:51.06#ibcon#about to write, iclass 38, count 2 2006.201.08:23:51.06#ibcon#wrote, iclass 38, count 2 2006.201.08:23:51.06#ibcon#about to read 3, iclass 38, count 2 2006.201.08:23:51.09#ibcon#read 3, iclass 38, count 2 2006.201.08:23:51.09#ibcon#about to read 4, iclass 38, count 2 2006.201.08:23:51.09#ibcon#read 4, iclass 38, count 2 2006.201.08:23:51.09#ibcon#about to read 5, iclass 38, count 2 2006.201.08:23:51.09#ibcon#read 5, iclass 38, count 2 2006.201.08:23:51.09#ibcon#about to read 6, iclass 38, count 2 2006.201.08:23:51.09#ibcon#read 6, iclass 38, count 2 2006.201.08:23:51.09#ibcon#end of sib2, iclass 38, count 2 2006.201.08:23:51.09#ibcon#*after write, iclass 38, count 2 2006.201.08:23:51.09#ibcon#*before return 0, iclass 38, count 2 2006.201.08:23:51.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:51.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:23:51.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.08:23:51.09#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:51.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:51.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:51.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:51.21#ibcon#enter wrdev, iclass 38, count 0 2006.201.08:23:51.21#ibcon#first serial, iclass 38, count 0 2006.201.08:23:51.21#ibcon#enter sib2, iclass 38, count 0 2006.201.08:23:51.21#ibcon#flushed, iclass 38, count 0 2006.201.08:23:51.21#ibcon#about to write, iclass 38, count 0 2006.201.08:23:51.21#ibcon#wrote, iclass 38, count 0 2006.201.08:23:51.21#ibcon#about to read 3, iclass 38, count 0 2006.201.08:23:51.23#ibcon#read 3, iclass 38, count 0 2006.201.08:23:51.23#ibcon#about to read 4, iclass 38, count 0 2006.201.08:23:51.23#ibcon#read 4, iclass 38, count 0 2006.201.08:23:51.23#ibcon#about to read 5, iclass 38, count 0 2006.201.08:23:51.23#ibcon#read 5, iclass 38, count 0 2006.201.08:23:51.23#ibcon#about to read 6, iclass 38, count 0 2006.201.08:23:51.23#ibcon#read 6, iclass 38, count 0 2006.201.08:23:51.23#ibcon#end of sib2, iclass 38, count 0 2006.201.08:23:51.23#ibcon#*mode == 0, iclass 38, count 0 2006.201.08:23:51.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.08:23:51.23#ibcon#[27=USB\r\n] 2006.201.08:23:51.23#ibcon#*before write, iclass 38, count 0 2006.201.08:23:51.23#ibcon#enter sib2, iclass 38, count 0 2006.201.08:23:51.23#ibcon#flushed, iclass 38, count 0 2006.201.08:23:51.23#ibcon#about to write, iclass 38, count 0 2006.201.08:23:51.23#ibcon#wrote, iclass 38, count 0 2006.201.08:23:51.23#ibcon#about to read 3, iclass 38, count 0 2006.201.08:23:51.26#ibcon#read 3, iclass 38, count 0 2006.201.08:23:51.26#ibcon#about to read 4, iclass 38, count 0 2006.201.08:23:51.26#ibcon#read 4, iclass 38, count 0 2006.201.08:23:51.26#ibcon#about to read 5, iclass 38, count 0 2006.201.08:23:51.26#ibcon#read 5, iclass 38, count 0 2006.201.08:23:51.26#ibcon#about to read 6, iclass 38, count 0 2006.201.08:23:51.26#ibcon#read 6, iclass 38, count 0 2006.201.08:23:51.26#ibcon#end of sib2, iclass 38, count 0 2006.201.08:23:51.26#ibcon#*after write, iclass 38, count 0 2006.201.08:23:51.26#ibcon#*before return 0, iclass 38, count 0 2006.201.08:23:51.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:51.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:23:51.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.08:23:51.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.08:23:51.26$vck44/vblo=3,649.99 2006.201.08:23:51.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.08:23:51.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.08:23:51.26#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:51.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:51.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:51.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:51.26#ibcon#enter wrdev, iclass 40, count 0 2006.201.08:23:51.26#ibcon#first serial, iclass 40, count 0 2006.201.08:23:51.26#ibcon#enter sib2, iclass 40, count 0 2006.201.08:23:51.26#ibcon#flushed, iclass 40, count 0 2006.201.08:23:51.26#ibcon#about to write, iclass 40, count 0 2006.201.08:23:51.26#ibcon#wrote, iclass 40, count 0 2006.201.08:23:51.26#ibcon#about to read 3, iclass 40, count 0 2006.201.08:23:51.28#ibcon#read 3, iclass 40, count 0 2006.201.08:23:51.28#ibcon#about to read 4, iclass 40, count 0 2006.201.08:23:51.28#ibcon#read 4, iclass 40, count 0 2006.201.08:23:51.28#ibcon#about to read 5, iclass 40, count 0 2006.201.08:23:51.28#ibcon#read 5, iclass 40, count 0 2006.201.08:23:51.28#ibcon#about to read 6, iclass 40, count 0 2006.201.08:23:51.28#ibcon#read 6, iclass 40, count 0 2006.201.08:23:51.28#ibcon#end of sib2, iclass 40, count 0 2006.201.08:23:51.28#ibcon#*mode == 0, iclass 40, count 0 2006.201.08:23:51.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.08:23:51.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:23:51.28#ibcon#*before write, iclass 40, count 0 2006.201.08:23:51.28#ibcon#enter sib2, iclass 40, count 0 2006.201.08:23:51.28#ibcon#flushed, iclass 40, count 0 2006.201.08:23:51.28#ibcon#about to write, iclass 40, count 0 2006.201.08:23:51.28#ibcon#wrote, iclass 40, count 0 2006.201.08:23:51.28#ibcon#about to read 3, iclass 40, count 0 2006.201.08:23:51.33#ibcon#read 3, iclass 40, count 0 2006.201.08:23:51.33#ibcon#about to read 4, iclass 40, count 0 2006.201.08:23:51.33#ibcon#read 4, iclass 40, count 0 2006.201.08:23:51.33#ibcon#about to read 5, iclass 40, count 0 2006.201.08:23:51.33#ibcon#read 5, iclass 40, count 0 2006.201.08:23:51.33#ibcon#about to read 6, iclass 40, count 0 2006.201.08:23:51.33#ibcon#read 6, iclass 40, count 0 2006.201.08:23:51.33#ibcon#end of sib2, iclass 40, count 0 2006.201.08:23:51.33#ibcon#*after write, iclass 40, count 0 2006.201.08:23:51.33#ibcon#*before return 0, iclass 40, count 0 2006.201.08:23:51.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:51.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:23:51.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.08:23:51.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.08:23:51.33$vck44/vb=3,4 2006.201.08:23:51.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.08:23:51.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.08:23:51.33#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:51.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:51.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:51.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:51.38#ibcon#enter wrdev, iclass 4, count 2 2006.201.08:23:51.38#ibcon#first serial, iclass 4, count 2 2006.201.08:23:51.38#ibcon#enter sib2, iclass 4, count 2 2006.201.08:23:51.38#ibcon#flushed, iclass 4, count 2 2006.201.08:23:51.38#ibcon#about to write, iclass 4, count 2 2006.201.08:23:51.38#ibcon#wrote, iclass 4, count 2 2006.201.08:23:51.38#ibcon#about to read 3, iclass 4, count 2 2006.201.08:23:51.40#ibcon#read 3, iclass 4, count 2 2006.201.08:23:51.40#ibcon#about to read 4, iclass 4, count 2 2006.201.08:23:51.40#ibcon#read 4, iclass 4, count 2 2006.201.08:23:51.40#ibcon#about to read 5, iclass 4, count 2 2006.201.08:23:51.40#ibcon#read 5, iclass 4, count 2 2006.201.08:23:51.40#ibcon#about to read 6, iclass 4, count 2 2006.201.08:23:51.40#ibcon#read 6, iclass 4, count 2 2006.201.08:23:51.40#ibcon#end of sib2, iclass 4, count 2 2006.201.08:23:51.40#ibcon#*mode == 0, iclass 4, count 2 2006.201.08:23:51.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.08:23:51.40#ibcon#[27=AT03-04\r\n] 2006.201.08:23:51.40#ibcon#*before write, iclass 4, count 2 2006.201.08:23:51.40#ibcon#enter sib2, iclass 4, count 2 2006.201.08:23:51.40#ibcon#flushed, iclass 4, count 2 2006.201.08:23:51.40#ibcon#about to write, iclass 4, count 2 2006.201.08:23:51.40#ibcon#wrote, iclass 4, count 2 2006.201.08:23:51.40#ibcon#about to read 3, iclass 4, count 2 2006.201.08:23:51.43#ibcon#read 3, iclass 4, count 2 2006.201.08:23:51.43#ibcon#about to read 4, iclass 4, count 2 2006.201.08:23:51.43#ibcon#read 4, iclass 4, count 2 2006.201.08:23:51.43#ibcon#about to read 5, iclass 4, count 2 2006.201.08:23:51.43#ibcon#read 5, iclass 4, count 2 2006.201.08:23:51.43#ibcon#about to read 6, iclass 4, count 2 2006.201.08:23:51.43#ibcon#read 6, iclass 4, count 2 2006.201.08:23:51.43#ibcon#end of sib2, iclass 4, count 2 2006.201.08:23:51.43#ibcon#*after write, iclass 4, count 2 2006.201.08:23:51.43#ibcon#*before return 0, iclass 4, count 2 2006.201.08:23:51.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:51.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:23:51.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.08:23:51.43#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:51.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:51.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:51.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:51.55#ibcon#enter wrdev, iclass 4, count 0 2006.201.08:23:51.55#ibcon#first serial, iclass 4, count 0 2006.201.08:23:51.55#ibcon#enter sib2, iclass 4, count 0 2006.201.08:23:51.55#ibcon#flushed, iclass 4, count 0 2006.201.08:23:51.55#ibcon#about to write, iclass 4, count 0 2006.201.08:23:51.55#ibcon#wrote, iclass 4, count 0 2006.201.08:23:51.55#ibcon#about to read 3, iclass 4, count 0 2006.201.08:23:51.57#ibcon#read 3, iclass 4, count 0 2006.201.08:23:51.57#ibcon#about to read 4, iclass 4, count 0 2006.201.08:23:51.57#ibcon#read 4, iclass 4, count 0 2006.201.08:23:51.57#ibcon#about to read 5, iclass 4, count 0 2006.201.08:23:51.57#ibcon#read 5, iclass 4, count 0 2006.201.08:23:51.57#ibcon#about to read 6, iclass 4, count 0 2006.201.08:23:51.57#ibcon#read 6, iclass 4, count 0 2006.201.08:23:51.57#ibcon#end of sib2, iclass 4, count 0 2006.201.08:23:51.57#ibcon#*mode == 0, iclass 4, count 0 2006.201.08:23:51.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.08:23:51.57#ibcon#[27=USB\r\n] 2006.201.08:23:51.57#ibcon#*before write, iclass 4, count 0 2006.201.08:23:51.57#ibcon#enter sib2, iclass 4, count 0 2006.201.08:23:51.57#ibcon#flushed, iclass 4, count 0 2006.201.08:23:51.57#ibcon#about to write, iclass 4, count 0 2006.201.08:23:51.57#ibcon#wrote, iclass 4, count 0 2006.201.08:23:51.57#ibcon#about to read 3, iclass 4, count 0 2006.201.08:23:51.60#ibcon#read 3, iclass 4, count 0 2006.201.08:23:51.60#ibcon#about to read 4, iclass 4, count 0 2006.201.08:23:51.60#ibcon#read 4, iclass 4, count 0 2006.201.08:23:51.60#ibcon#about to read 5, iclass 4, count 0 2006.201.08:23:51.60#ibcon#read 5, iclass 4, count 0 2006.201.08:23:51.60#ibcon#about to read 6, iclass 4, count 0 2006.201.08:23:51.60#ibcon#read 6, iclass 4, count 0 2006.201.08:23:51.60#ibcon#end of sib2, iclass 4, count 0 2006.201.08:23:51.60#ibcon#*after write, iclass 4, count 0 2006.201.08:23:51.60#ibcon#*before return 0, iclass 4, count 0 2006.201.08:23:51.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:51.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:23:51.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.08:23:51.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.08:23:51.60$vck44/vblo=4,679.99 2006.201.08:23:51.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.08:23:51.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.08:23:51.60#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:51.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:51.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:51.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:51.60#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:23:51.60#ibcon#first serial, iclass 6, count 0 2006.201.08:23:51.60#ibcon#enter sib2, iclass 6, count 0 2006.201.08:23:51.60#ibcon#flushed, iclass 6, count 0 2006.201.08:23:51.60#ibcon#about to write, iclass 6, count 0 2006.201.08:23:51.60#ibcon#wrote, iclass 6, count 0 2006.201.08:23:51.60#ibcon#about to read 3, iclass 6, count 0 2006.201.08:23:51.62#ibcon#read 3, iclass 6, count 0 2006.201.08:23:51.62#ibcon#about to read 4, iclass 6, count 0 2006.201.08:23:51.62#ibcon#read 4, iclass 6, count 0 2006.201.08:23:51.62#ibcon#about to read 5, iclass 6, count 0 2006.201.08:23:51.62#ibcon#read 5, iclass 6, count 0 2006.201.08:23:51.62#ibcon#about to read 6, iclass 6, count 0 2006.201.08:23:51.62#ibcon#read 6, iclass 6, count 0 2006.201.08:23:51.62#ibcon#end of sib2, iclass 6, count 0 2006.201.08:23:51.62#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:23:51.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:23:51.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:23:51.62#ibcon#*before write, iclass 6, count 0 2006.201.08:23:51.62#ibcon#enter sib2, iclass 6, count 0 2006.201.08:23:51.62#ibcon#flushed, iclass 6, count 0 2006.201.08:23:51.62#ibcon#about to write, iclass 6, count 0 2006.201.08:23:51.62#ibcon#wrote, iclass 6, count 0 2006.201.08:23:51.62#ibcon#about to read 3, iclass 6, count 0 2006.201.08:23:51.67#ibcon#read 3, iclass 6, count 0 2006.201.08:23:51.67#ibcon#about to read 4, iclass 6, count 0 2006.201.08:23:51.67#ibcon#read 4, iclass 6, count 0 2006.201.08:23:51.67#ibcon#about to read 5, iclass 6, count 0 2006.201.08:23:51.67#ibcon#read 5, iclass 6, count 0 2006.201.08:23:51.67#ibcon#about to read 6, iclass 6, count 0 2006.201.08:23:51.67#ibcon#read 6, iclass 6, count 0 2006.201.08:23:51.67#ibcon#end of sib2, iclass 6, count 0 2006.201.08:23:51.67#ibcon#*after write, iclass 6, count 0 2006.201.08:23:51.67#ibcon#*before return 0, iclass 6, count 0 2006.201.08:23:51.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:51.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:23:51.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:23:51.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:23:51.67$vck44/vb=4,5 2006.201.08:23:51.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.08:23:51.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.08:23:51.67#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:51.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:51.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:51.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:51.72#ibcon#enter wrdev, iclass 10, count 2 2006.201.08:23:51.72#ibcon#first serial, iclass 10, count 2 2006.201.08:23:51.72#ibcon#enter sib2, iclass 10, count 2 2006.201.08:23:51.72#ibcon#flushed, iclass 10, count 2 2006.201.08:23:51.72#ibcon#about to write, iclass 10, count 2 2006.201.08:23:51.72#ibcon#wrote, iclass 10, count 2 2006.201.08:23:51.72#ibcon#about to read 3, iclass 10, count 2 2006.201.08:23:51.74#ibcon#read 3, iclass 10, count 2 2006.201.08:23:51.74#ibcon#about to read 4, iclass 10, count 2 2006.201.08:23:51.74#ibcon#read 4, iclass 10, count 2 2006.201.08:23:51.74#ibcon#about to read 5, iclass 10, count 2 2006.201.08:23:51.74#ibcon#read 5, iclass 10, count 2 2006.201.08:23:51.74#ibcon#about to read 6, iclass 10, count 2 2006.201.08:23:51.74#ibcon#read 6, iclass 10, count 2 2006.201.08:23:51.74#ibcon#end of sib2, iclass 10, count 2 2006.201.08:23:51.74#ibcon#*mode == 0, iclass 10, count 2 2006.201.08:23:51.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.08:23:51.74#ibcon#[27=AT04-05\r\n] 2006.201.08:23:51.74#ibcon#*before write, iclass 10, count 2 2006.201.08:23:51.74#ibcon#enter sib2, iclass 10, count 2 2006.201.08:23:51.74#ibcon#flushed, iclass 10, count 2 2006.201.08:23:51.74#ibcon#about to write, iclass 10, count 2 2006.201.08:23:51.74#ibcon#wrote, iclass 10, count 2 2006.201.08:23:51.74#ibcon#about to read 3, iclass 10, count 2 2006.201.08:23:51.77#ibcon#read 3, iclass 10, count 2 2006.201.08:23:51.77#ibcon#about to read 4, iclass 10, count 2 2006.201.08:23:51.77#ibcon#read 4, iclass 10, count 2 2006.201.08:23:51.77#ibcon#about to read 5, iclass 10, count 2 2006.201.08:23:51.77#ibcon#read 5, iclass 10, count 2 2006.201.08:23:51.77#ibcon#about to read 6, iclass 10, count 2 2006.201.08:23:51.77#ibcon#read 6, iclass 10, count 2 2006.201.08:23:51.77#ibcon#end of sib2, iclass 10, count 2 2006.201.08:23:51.77#ibcon#*after write, iclass 10, count 2 2006.201.08:23:51.77#ibcon#*before return 0, iclass 10, count 2 2006.201.08:23:51.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:51.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:23:51.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.08:23:51.77#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:51.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:51.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:51.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:51.89#ibcon#enter wrdev, iclass 10, count 0 2006.201.08:23:51.89#ibcon#first serial, iclass 10, count 0 2006.201.08:23:51.89#ibcon#enter sib2, iclass 10, count 0 2006.201.08:23:51.89#ibcon#flushed, iclass 10, count 0 2006.201.08:23:51.89#ibcon#about to write, iclass 10, count 0 2006.201.08:23:51.89#ibcon#wrote, iclass 10, count 0 2006.201.08:23:51.89#ibcon#about to read 3, iclass 10, count 0 2006.201.08:23:51.91#ibcon#read 3, iclass 10, count 0 2006.201.08:23:51.91#ibcon#about to read 4, iclass 10, count 0 2006.201.08:23:51.91#ibcon#read 4, iclass 10, count 0 2006.201.08:23:51.91#ibcon#about to read 5, iclass 10, count 0 2006.201.08:23:51.91#ibcon#read 5, iclass 10, count 0 2006.201.08:23:51.91#ibcon#about to read 6, iclass 10, count 0 2006.201.08:23:51.91#ibcon#read 6, iclass 10, count 0 2006.201.08:23:51.91#ibcon#end of sib2, iclass 10, count 0 2006.201.08:23:51.91#ibcon#*mode == 0, iclass 10, count 0 2006.201.08:23:51.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.08:23:51.91#ibcon#[27=USB\r\n] 2006.201.08:23:51.91#ibcon#*before write, iclass 10, count 0 2006.201.08:23:51.91#ibcon#enter sib2, iclass 10, count 0 2006.201.08:23:51.91#ibcon#flushed, iclass 10, count 0 2006.201.08:23:51.91#ibcon#about to write, iclass 10, count 0 2006.201.08:23:51.91#ibcon#wrote, iclass 10, count 0 2006.201.08:23:51.91#ibcon#about to read 3, iclass 10, count 0 2006.201.08:23:51.94#ibcon#read 3, iclass 10, count 0 2006.201.08:23:51.94#ibcon#about to read 4, iclass 10, count 0 2006.201.08:23:51.94#ibcon#read 4, iclass 10, count 0 2006.201.08:23:51.94#ibcon#about to read 5, iclass 10, count 0 2006.201.08:23:51.94#ibcon#read 5, iclass 10, count 0 2006.201.08:23:51.94#ibcon#about to read 6, iclass 10, count 0 2006.201.08:23:51.94#ibcon#read 6, iclass 10, count 0 2006.201.08:23:51.94#ibcon#end of sib2, iclass 10, count 0 2006.201.08:23:51.94#ibcon#*after write, iclass 10, count 0 2006.201.08:23:51.94#ibcon#*before return 0, iclass 10, count 0 2006.201.08:23:51.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:51.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:23:51.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.08:23:51.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.08:23:51.94$vck44/vblo=5,709.99 2006.201.08:23:51.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.08:23:51.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.08:23:51.94#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:51.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:51.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:51.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:51.94#ibcon#enter wrdev, iclass 12, count 0 2006.201.08:23:51.94#ibcon#first serial, iclass 12, count 0 2006.201.08:23:51.94#ibcon#enter sib2, iclass 12, count 0 2006.201.08:23:51.94#ibcon#flushed, iclass 12, count 0 2006.201.08:23:51.94#ibcon#about to write, iclass 12, count 0 2006.201.08:23:51.94#ibcon#wrote, iclass 12, count 0 2006.201.08:23:51.94#ibcon#about to read 3, iclass 12, count 0 2006.201.08:23:51.96#ibcon#read 3, iclass 12, count 0 2006.201.08:23:51.96#ibcon#about to read 4, iclass 12, count 0 2006.201.08:23:51.96#ibcon#read 4, iclass 12, count 0 2006.201.08:23:51.96#ibcon#about to read 5, iclass 12, count 0 2006.201.08:23:51.96#ibcon#read 5, iclass 12, count 0 2006.201.08:23:51.96#ibcon#about to read 6, iclass 12, count 0 2006.201.08:23:51.96#ibcon#read 6, iclass 12, count 0 2006.201.08:23:51.96#ibcon#end of sib2, iclass 12, count 0 2006.201.08:23:51.96#ibcon#*mode == 0, iclass 12, count 0 2006.201.08:23:51.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.08:23:51.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:23:51.96#ibcon#*before write, iclass 12, count 0 2006.201.08:23:51.96#ibcon#enter sib2, iclass 12, count 0 2006.201.08:23:51.96#ibcon#flushed, iclass 12, count 0 2006.201.08:23:51.96#ibcon#about to write, iclass 12, count 0 2006.201.08:23:51.96#ibcon#wrote, iclass 12, count 0 2006.201.08:23:51.96#ibcon#about to read 3, iclass 12, count 0 2006.201.08:23:52.00#ibcon#read 3, iclass 12, count 0 2006.201.08:23:52.00#ibcon#about to read 4, iclass 12, count 0 2006.201.08:23:52.00#ibcon#read 4, iclass 12, count 0 2006.201.08:23:52.00#ibcon#about to read 5, iclass 12, count 0 2006.201.08:23:52.00#ibcon#read 5, iclass 12, count 0 2006.201.08:23:52.00#ibcon#about to read 6, iclass 12, count 0 2006.201.08:23:52.00#ibcon#read 6, iclass 12, count 0 2006.201.08:23:52.00#ibcon#end of sib2, iclass 12, count 0 2006.201.08:23:52.00#ibcon#*after write, iclass 12, count 0 2006.201.08:23:52.00#ibcon#*before return 0, iclass 12, count 0 2006.201.08:23:52.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:52.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:23:52.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.08:23:52.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.08:23:52.00$vck44/vb=5,4 2006.201.08:23:52.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.08:23:52.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.08:23:52.00#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:52.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:52.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:52.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:52.06#ibcon#enter wrdev, iclass 14, count 2 2006.201.08:23:52.06#ibcon#first serial, iclass 14, count 2 2006.201.08:23:52.06#ibcon#enter sib2, iclass 14, count 2 2006.201.08:23:52.06#ibcon#flushed, iclass 14, count 2 2006.201.08:23:52.06#ibcon#about to write, iclass 14, count 2 2006.201.08:23:52.06#ibcon#wrote, iclass 14, count 2 2006.201.08:23:52.06#ibcon#about to read 3, iclass 14, count 2 2006.201.08:23:52.08#ibcon#read 3, iclass 14, count 2 2006.201.08:23:52.08#ibcon#about to read 4, iclass 14, count 2 2006.201.08:23:52.08#ibcon#read 4, iclass 14, count 2 2006.201.08:23:52.08#ibcon#about to read 5, iclass 14, count 2 2006.201.08:23:52.08#ibcon#read 5, iclass 14, count 2 2006.201.08:23:52.08#ibcon#about to read 6, iclass 14, count 2 2006.201.08:23:52.08#ibcon#read 6, iclass 14, count 2 2006.201.08:23:52.08#ibcon#end of sib2, iclass 14, count 2 2006.201.08:23:52.08#ibcon#*mode == 0, iclass 14, count 2 2006.201.08:23:52.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.08:23:52.08#ibcon#[27=AT05-04\r\n] 2006.201.08:23:52.08#ibcon#*before write, iclass 14, count 2 2006.201.08:23:52.08#ibcon#enter sib2, iclass 14, count 2 2006.201.08:23:52.08#ibcon#flushed, iclass 14, count 2 2006.201.08:23:52.08#ibcon#about to write, iclass 14, count 2 2006.201.08:23:52.08#ibcon#wrote, iclass 14, count 2 2006.201.08:23:52.08#ibcon#about to read 3, iclass 14, count 2 2006.201.08:23:52.11#ibcon#read 3, iclass 14, count 2 2006.201.08:23:52.11#ibcon#about to read 4, iclass 14, count 2 2006.201.08:23:52.11#ibcon#read 4, iclass 14, count 2 2006.201.08:23:52.11#ibcon#about to read 5, iclass 14, count 2 2006.201.08:23:52.11#ibcon#read 5, iclass 14, count 2 2006.201.08:23:52.11#ibcon#about to read 6, iclass 14, count 2 2006.201.08:23:52.11#ibcon#read 6, iclass 14, count 2 2006.201.08:23:52.11#ibcon#end of sib2, iclass 14, count 2 2006.201.08:23:52.11#ibcon#*after write, iclass 14, count 2 2006.201.08:23:52.11#ibcon#*before return 0, iclass 14, count 2 2006.201.08:23:52.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:52.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:23:52.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.08:23:52.11#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:52.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:52.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:52.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:52.23#ibcon#enter wrdev, iclass 14, count 0 2006.201.08:23:52.23#ibcon#first serial, iclass 14, count 0 2006.201.08:23:52.23#ibcon#enter sib2, iclass 14, count 0 2006.201.08:23:52.23#ibcon#flushed, iclass 14, count 0 2006.201.08:23:52.23#ibcon#about to write, iclass 14, count 0 2006.201.08:23:52.23#ibcon#wrote, iclass 14, count 0 2006.201.08:23:52.23#ibcon#about to read 3, iclass 14, count 0 2006.201.08:23:52.25#ibcon#read 3, iclass 14, count 0 2006.201.08:23:52.25#ibcon#about to read 4, iclass 14, count 0 2006.201.08:23:52.25#ibcon#read 4, iclass 14, count 0 2006.201.08:23:52.25#ibcon#about to read 5, iclass 14, count 0 2006.201.08:23:52.25#ibcon#read 5, iclass 14, count 0 2006.201.08:23:52.25#ibcon#about to read 6, iclass 14, count 0 2006.201.08:23:52.25#ibcon#read 6, iclass 14, count 0 2006.201.08:23:52.25#ibcon#end of sib2, iclass 14, count 0 2006.201.08:23:52.25#ibcon#*mode == 0, iclass 14, count 0 2006.201.08:23:52.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.08:23:52.25#ibcon#[27=USB\r\n] 2006.201.08:23:52.25#ibcon#*before write, iclass 14, count 0 2006.201.08:23:52.25#ibcon#enter sib2, iclass 14, count 0 2006.201.08:23:52.25#ibcon#flushed, iclass 14, count 0 2006.201.08:23:52.25#ibcon#about to write, iclass 14, count 0 2006.201.08:23:52.25#ibcon#wrote, iclass 14, count 0 2006.201.08:23:52.25#ibcon#about to read 3, iclass 14, count 0 2006.201.08:23:52.28#ibcon#read 3, iclass 14, count 0 2006.201.08:23:52.28#ibcon#about to read 4, iclass 14, count 0 2006.201.08:23:52.28#ibcon#read 4, iclass 14, count 0 2006.201.08:23:52.28#ibcon#about to read 5, iclass 14, count 0 2006.201.08:23:52.28#ibcon#read 5, iclass 14, count 0 2006.201.08:23:52.28#ibcon#about to read 6, iclass 14, count 0 2006.201.08:23:52.28#ibcon#read 6, iclass 14, count 0 2006.201.08:23:52.28#ibcon#end of sib2, iclass 14, count 0 2006.201.08:23:52.28#ibcon#*after write, iclass 14, count 0 2006.201.08:23:52.28#ibcon#*before return 0, iclass 14, count 0 2006.201.08:23:52.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:52.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:23:52.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.08:23:52.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.08:23:52.28$vck44/vblo=6,719.99 2006.201.08:23:52.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.08:23:52.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.08:23:52.28#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:52.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:52.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:52.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:52.28#ibcon#enter wrdev, iclass 16, count 0 2006.201.08:23:52.28#ibcon#first serial, iclass 16, count 0 2006.201.08:23:52.28#ibcon#enter sib2, iclass 16, count 0 2006.201.08:23:52.28#ibcon#flushed, iclass 16, count 0 2006.201.08:23:52.28#ibcon#about to write, iclass 16, count 0 2006.201.08:23:52.28#ibcon#wrote, iclass 16, count 0 2006.201.08:23:52.28#ibcon#about to read 3, iclass 16, count 0 2006.201.08:23:52.30#ibcon#read 3, iclass 16, count 0 2006.201.08:23:52.30#ibcon#about to read 4, iclass 16, count 0 2006.201.08:23:52.30#ibcon#read 4, iclass 16, count 0 2006.201.08:23:52.30#ibcon#about to read 5, iclass 16, count 0 2006.201.08:23:52.30#ibcon#read 5, iclass 16, count 0 2006.201.08:23:52.30#ibcon#about to read 6, iclass 16, count 0 2006.201.08:23:52.30#ibcon#read 6, iclass 16, count 0 2006.201.08:23:52.30#ibcon#end of sib2, iclass 16, count 0 2006.201.08:23:52.30#ibcon#*mode == 0, iclass 16, count 0 2006.201.08:23:52.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.08:23:52.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:23:52.30#ibcon#*before write, iclass 16, count 0 2006.201.08:23:52.30#ibcon#enter sib2, iclass 16, count 0 2006.201.08:23:52.30#ibcon#flushed, iclass 16, count 0 2006.201.08:23:52.30#ibcon#about to write, iclass 16, count 0 2006.201.08:23:52.30#ibcon#wrote, iclass 16, count 0 2006.201.08:23:52.30#ibcon#about to read 3, iclass 16, count 0 2006.201.08:23:52.35#ibcon#read 3, iclass 16, count 0 2006.201.08:23:52.35#ibcon#about to read 4, iclass 16, count 0 2006.201.08:23:52.35#ibcon#read 4, iclass 16, count 0 2006.201.08:23:52.35#ibcon#about to read 5, iclass 16, count 0 2006.201.08:23:52.35#ibcon#read 5, iclass 16, count 0 2006.201.08:23:52.35#ibcon#about to read 6, iclass 16, count 0 2006.201.08:23:52.35#ibcon#read 6, iclass 16, count 0 2006.201.08:23:52.35#ibcon#end of sib2, iclass 16, count 0 2006.201.08:23:52.35#ibcon#*after write, iclass 16, count 0 2006.201.08:23:52.35#ibcon#*before return 0, iclass 16, count 0 2006.201.08:23:52.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:52.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:23:52.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.08:23:52.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.08:23:52.35$vck44/vb=6,4 2006.201.08:23:52.35#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.08:23:52.35#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.08:23:52.35#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:52.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:52.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:52.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:52.40#ibcon#enter wrdev, iclass 18, count 2 2006.201.08:23:52.40#ibcon#first serial, iclass 18, count 2 2006.201.08:23:52.40#ibcon#enter sib2, iclass 18, count 2 2006.201.08:23:52.40#ibcon#flushed, iclass 18, count 2 2006.201.08:23:52.40#ibcon#about to write, iclass 18, count 2 2006.201.08:23:52.40#ibcon#wrote, iclass 18, count 2 2006.201.08:23:52.40#ibcon#about to read 3, iclass 18, count 2 2006.201.08:23:52.42#ibcon#read 3, iclass 18, count 2 2006.201.08:23:52.42#ibcon#about to read 4, iclass 18, count 2 2006.201.08:23:52.42#ibcon#read 4, iclass 18, count 2 2006.201.08:23:52.42#ibcon#about to read 5, iclass 18, count 2 2006.201.08:23:52.42#ibcon#read 5, iclass 18, count 2 2006.201.08:23:52.42#ibcon#about to read 6, iclass 18, count 2 2006.201.08:23:52.42#ibcon#read 6, iclass 18, count 2 2006.201.08:23:52.42#ibcon#end of sib2, iclass 18, count 2 2006.201.08:23:52.42#ibcon#*mode == 0, iclass 18, count 2 2006.201.08:23:52.42#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.08:23:52.42#ibcon#[27=AT06-04\r\n] 2006.201.08:23:52.42#ibcon#*before write, iclass 18, count 2 2006.201.08:23:52.42#ibcon#enter sib2, iclass 18, count 2 2006.201.08:23:52.42#ibcon#flushed, iclass 18, count 2 2006.201.08:23:52.42#ibcon#about to write, iclass 18, count 2 2006.201.08:23:52.42#ibcon#wrote, iclass 18, count 2 2006.201.08:23:52.42#ibcon#about to read 3, iclass 18, count 2 2006.201.08:23:52.45#ibcon#read 3, iclass 18, count 2 2006.201.08:23:52.45#ibcon#about to read 4, iclass 18, count 2 2006.201.08:23:52.45#ibcon#read 4, iclass 18, count 2 2006.201.08:23:52.45#ibcon#about to read 5, iclass 18, count 2 2006.201.08:23:52.45#ibcon#read 5, iclass 18, count 2 2006.201.08:23:52.45#ibcon#about to read 6, iclass 18, count 2 2006.201.08:23:52.45#ibcon#read 6, iclass 18, count 2 2006.201.08:23:52.45#ibcon#end of sib2, iclass 18, count 2 2006.201.08:23:52.45#ibcon#*after write, iclass 18, count 2 2006.201.08:23:52.45#ibcon#*before return 0, iclass 18, count 2 2006.201.08:23:52.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:52.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:23:52.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.08:23:52.45#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:52.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:52.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:52.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:52.57#ibcon#enter wrdev, iclass 18, count 0 2006.201.08:23:52.57#ibcon#first serial, iclass 18, count 0 2006.201.08:23:52.57#ibcon#enter sib2, iclass 18, count 0 2006.201.08:23:52.57#ibcon#flushed, iclass 18, count 0 2006.201.08:23:52.57#ibcon#about to write, iclass 18, count 0 2006.201.08:23:52.57#ibcon#wrote, iclass 18, count 0 2006.201.08:23:52.57#ibcon#about to read 3, iclass 18, count 0 2006.201.08:23:52.59#ibcon#read 3, iclass 18, count 0 2006.201.08:23:52.59#ibcon#about to read 4, iclass 18, count 0 2006.201.08:23:52.59#ibcon#read 4, iclass 18, count 0 2006.201.08:23:52.59#ibcon#about to read 5, iclass 18, count 0 2006.201.08:23:52.59#ibcon#read 5, iclass 18, count 0 2006.201.08:23:52.59#ibcon#about to read 6, iclass 18, count 0 2006.201.08:23:52.59#ibcon#read 6, iclass 18, count 0 2006.201.08:23:52.59#ibcon#end of sib2, iclass 18, count 0 2006.201.08:23:52.59#ibcon#*mode == 0, iclass 18, count 0 2006.201.08:23:52.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.08:23:52.59#ibcon#[27=USB\r\n] 2006.201.08:23:52.59#ibcon#*before write, iclass 18, count 0 2006.201.08:23:52.59#ibcon#enter sib2, iclass 18, count 0 2006.201.08:23:52.59#ibcon#flushed, iclass 18, count 0 2006.201.08:23:52.59#ibcon#about to write, iclass 18, count 0 2006.201.08:23:52.59#ibcon#wrote, iclass 18, count 0 2006.201.08:23:52.59#ibcon#about to read 3, iclass 18, count 0 2006.201.08:23:52.62#ibcon#read 3, iclass 18, count 0 2006.201.08:23:52.62#ibcon#about to read 4, iclass 18, count 0 2006.201.08:23:52.62#ibcon#read 4, iclass 18, count 0 2006.201.08:23:52.62#ibcon#about to read 5, iclass 18, count 0 2006.201.08:23:52.62#ibcon#read 5, iclass 18, count 0 2006.201.08:23:52.62#ibcon#about to read 6, iclass 18, count 0 2006.201.08:23:52.62#ibcon#read 6, iclass 18, count 0 2006.201.08:23:52.62#ibcon#end of sib2, iclass 18, count 0 2006.201.08:23:52.62#ibcon#*after write, iclass 18, count 0 2006.201.08:23:52.62#ibcon#*before return 0, iclass 18, count 0 2006.201.08:23:52.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:52.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:23:52.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.08:23:52.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.08:23:52.62$vck44/vblo=7,734.99 2006.201.08:23:52.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.08:23:52.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.08:23:52.62#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:52.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:52.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:52.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:52.62#ibcon#enter wrdev, iclass 20, count 0 2006.201.08:23:52.62#ibcon#first serial, iclass 20, count 0 2006.201.08:23:52.62#ibcon#enter sib2, iclass 20, count 0 2006.201.08:23:52.62#ibcon#flushed, iclass 20, count 0 2006.201.08:23:52.62#ibcon#about to write, iclass 20, count 0 2006.201.08:23:52.62#ibcon#wrote, iclass 20, count 0 2006.201.08:23:52.62#ibcon#about to read 3, iclass 20, count 0 2006.201.08:23:52.64#ibcon#read 3, iclass 20, count 0 2006.201.08:23:52.64#ibcon#about to read 4, iclass 20, count 0 2006.201.08:23:52.64#ibcon#read 4, iclass 20, count 0 2006.201.08:23:52.64#ibcon#about to read 5, iclass 20, count 0 2006.201.08:23:52.64#ibcon#read 5, iclass 20, count 0 2006.201.08:23:52.64#ibcon#about to read 6, iclass 20, count 0 2006.201.08:23:52.64#ibcon#read 6, iclass 20, count 0 2006.201.08:23:52.64#ibcon#end of sib2, iclass 20, count 0 2006.201.08:23:52.64#ibcon#*mode == 0, iclass 20, count 0 2006.201.08:23:52.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.08:23:52.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:23:52.64#ibcon#*before write, iclass 20, count 0 2006.201.08:23:52.64#ibcon#enter sib2, iclass 20, count 0 2006.201.08:23:52.64#ibcon#flushed, iclass 20, count 0 2006.201.08:23:52.64#ibcon#about to write, iclass 20, count 0 2006.201.08:23:52.64#ibcon#wrote, iclass 20, count 0 2006.201.08:23:52.64#ibcon#about to read 3, iclass 20, count 0 2006.201.08:23:52.68#ibcon#read 3, iclass 20, count 0 2006.201.08:23:52.68#ibcon#about to read 4, iclass 20, count 0 2006.201.08:23:52.68#ibcon#read 4, iclass 20, count 0 2006.201.08:23:52.68#ibcon#about to read 5, iclass 20, count 0 2006.201.08:23:52.68#ibcon#read 5, iclass 20, count 0 2006.201.08:23:52.68#ibcon#about to read 6, iclass 20, count 0 2006.201.08:23:52.68#ibcon#read 6, iclass 20, count 0 2006.201.08:23:52.68#ibcon#end of sib2, iclass 20, count 0 2006.201.08:23:52.68#ibcon#*after write, iclass 20, count 0 2006.201.08:23:52.68#ibcon#*before return 0, iclass 20, count 0 2006.201.08:23:52.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:52.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:23:52.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.08:23:52.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.08:23:52.68$vck44/vb=7,4 2006.201.08:23:52.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.08:23:52.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.08:23:52.68#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:52.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:52.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:52.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:52.74#ibcon#enter wrdev, iclass 22, count 2 2006.201.08:23:52.74#ibcon#first serial, iclass 22, count 2 2006.201.08:23:52.74#ibcon#enter sib2, iclass 22, count 2 2006.201.08:23:52.74#ibcon#flushed, iclass 22, count 2 2006.201.08:23:52.74#ibcon#about to write, iclass 22, count 2 2006.201.08:23:52.74#ibcon#wrote, iclass 22, count 2 2006.201.08:23:52.74#ibcon#about to read 3, iclass 22, count 2 2006.201.08:23:52.76#ibcon#read 3, iclass 22, count 2 2006.201.08:23:52.76#ibcon#about to read 4, iclass 22, count 2 2006.201.08:23:52.76#ibcon#read 4, iclass 22, count 2 2006.201.08:23:52.76#ibcon#about to read 5, iclass 22, count 2 2006.201.08:23:52.76#ibcon#read 5, iclass 22, count 2 2006.201.08:23:52.76#ibcon#about to read 6, iclass 22, count 2 2006.201.08:23:52.76#ibcon#read 6, iclass 22, count 2 2006.201.08:23:52.76#ibcon#end of sib2, iclass 22, count 2 2006.201.08:23:52.76#ibcon#*mode == 0, iclass 22, count 2 2006.201.08:23:52.76#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.08:23:52.76#ibcon#[27=AT07-04\r\n] 2006.201.08:23:52.76#ibcon#*before write, iclass 22, count 2 2006.201.08:23:52.76#ibcon#enter sib2, iclass 22, count 2 2006.201.08:23:52.76#ibcon#flushed, iclass 22, count 2 2006.201.08:23:52.76#ibcon#about to write, iclass 22, count 2 2006.201.08:23:52.76#ibcon#wrote, iclass 22, count 2 2006.201.08:23:52.76#ibcon#about to read 3, iclass 22, count 2 2006.201.08:23:52.79#ibcon#read 3, iclass 22, count 2 2006.201.08:23:52.79#ibcon#about to read 4, iclass 22, count 2 2006.201.08:23:52.79#ibcon#read 4, iclass 22, count 2 2006.201.08:23:52.79#ibcon#about to read 5, iclass 22, count 2 2006.201.08:23:52.79#ibcon#read 5, iclass 22, count 2 2006.201.08:23:52.79#ibcon#about to read 6, iclass 22, count 2 2006.201.08:23:52.79#ibcon#read 6, iclass 22, count 2 2006.201.08:23:52.79#ibcon#end of sib2, iclass 22, count 2 2006.201.08:23:52.79#ibcon#*after write, iclass 22, count 2 2006.201.08:23:52.79#ibcon#*before return 0, iclass 22, count 2 2006.201.08:23:52.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:52.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:23:52.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.08:23:52.79#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:52.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:52.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:52.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:52.91#ibcon#enter wrdev, iclass 22, count 0 2006.201.08:23:52.91#ibcon#first serial, iclass 22, count 0 2006.201.08:23:52.91#ibcon#enter sib2, iclass 22, count 0 2006.201.08:23:52.91#ibcon#flushed, iclass 22, count 0 2006.201.08:23:52.91#ibcon#about to write, iclass 22, count 0 2006.201.08:23:52.91#ibcon#wrote, iclass 22, count 0 2006.201.08:23:52.91#ibcon#about to read 3, iclass 22, count 0 2006.201.08:23:52.93#ibcon#read 3, iclass 22, count 0 2006.201.08:23:52.93#ibcon#about to read 4, iclass 22, count 0 2006.201.08:23:52.93#ibcon#read 4, iclass 22, count 0 2006.201.08:23:52.93#ibcon#about to read 5, iclass 22, count 0 2006.201.08:23:52.93#ibcon#read 5, iclass 22, count 0 2006.201.08:23:52.93#ibcon#about to read 6, iclass 22, count 0 2006.201.08:23:52.93#ibcon#read 6, iclass 22, count 0 2006.201.08:23:52.93#ibcon#end of sib2, iclass 22, count 0 2006.201.08:23:52.93#ibcon#*mode == 0, iclass 22, count 0 2006.201.08:23:52.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.08:23:52.93#ibcon#[27=USB\r\n] 2006.201.08:23:52.93#ibcon#*before write, iclass 22, count 0 2006.201.08:23:52.93#ibcon#enter sib2, iclass 22, count 0 2006.201.08:23:52.93#ibcon#flushed, iclass 22, count 0 2006.201.08:23:52.93#ibcon#about to write, iclass 22, count 0 2006.201.08:23:52.93#ibcon#wrote, iclass 22, count 0 2006.201.08:23:52.93#ibcon#about to read 3, iclass 22, count 0 2006.201.08:23:52.96#ibcon#read 3, iclass 22, count 0 2006.201.08:23:52.96#ibcon#about to read 4, iclass 22, count 0 2006.201.08:23:52.96#ibcon#read 4, iclass 22, count 0 2006.201.08:23:52.96#ibcon#about to read 5, iclass 22, count 0 2006.201.08:23:52.96#ibcon#read 5, iclass 22, count 0 2006.201.08:23:52.96#ibcon#about to read 6, iclass 22, count 0 2006.201.08:23:52.96#ibcon#read 6, iclass 22, count 0 2006.201.08:23:52.96#ibcon#end of sib2, iclass 22, count 0 2006.201.08:23:52.96#ibcon#*after write, iclass 22, count 0 2006.201.08:23:52.96#ibcon#*before return 0, iclass 22, count 0 2006.201.08:23:52.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:52.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:23:52.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.08:23:52.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.08:23:52.96$vck44/vblo=8,744.99 2006.201.08:23:52.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.08:23:52.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.08:23:52.96#ibcon#ireg 17 cls_cnt 0 2006.201.08:23:52.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:52.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:52.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:52.96#ibcon#enter wrdev, iclass 24, count 0 2006.201.08:23:52.96#ibcon#first serial, iclass 24, count 0 2006.201.08:23:52.96#ibcon#enter sib2, iclass 24, count 0 2006.201.08:23:52.96#ibcon#flushed, iclass 24, count 0 2006.201.08:23:52.96#ibcon#about to write, iclass 24, count 0 2006.201.08:23:52.96#ibcon#wrote, iclass 24, count 0 2006.201.08:23:52.96#ibcon#about to read 3, iclass 24, count 0 2006.201.08:23:52.98#ibcon#read 3, iclass 24, count 0 2006.201.08:23:52.98#ibcon#about to read 4, iclass 24, count 0 2006.201.08:23:52.98#ibcon#read 4, iclass 24, count 0 2006.201.08:23:52.98#ibcon#about to read 5, iclass 24, count 0 2006.201.08:23:52.98#ibcon#read 5, iclass 24, count 0 2006.201.08:23:52.98#ibcon#about to read 6, iclass 24, count 0 2006.201.08:23:52.98#ibcon#read 6, iclass 24, count 0 2006.201.08:23:52.98#ibcon#end of sib2, iclass 24, count 0 2006.201.08:23:52.98#ibcon#*mode == 0, iclass 24, count 0 2006.201.08:23:52.98#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.08:23:52.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:23:52.98#ibcon#*before write, iclass 24, count 0 2006.201.08:23:52.98#ibcon#enter sib2, iclass 24, count 0 2006.201.08:23:52.98#ibcon#flushed, iclass 24, count 0 2006.201.08:23:52.98#ibcon#about to write, iclass 24, count 0 2006.201.08:23:52.98#ibcon#wrote, iclass 24, count 0 2006.201.08:23:52.98#ibcon#about to read 3, iclass 24, count 0 2006.201.08:23:53.03#ibcon#read 3, iclass 24, count 0 2006.201.08:23:53.03#ibcon#about to read 4, iclass 24, count 0 2006.201.08:23:53.03#ibcon#read 4, iclass 24, count 0 2006.201.08:23:53.03#ibcon#about to read 5, iclass 24, count 0 2006.201.08:23:53.03#ibcon#read 5, iclass 24, count 0 2006.201.08:23:53.03#ibcon#about to read 6, iclass 24, count 0 2006.201.08:23:53.03#ibcon#read 6, iclass 24, count 0 2006.201.08:23:53.03#ibcon#end of sib2, iclass 24, count 0 2006.201.08:23:53.03#ibcon#*after write, iclass 24, count 0 2006.201.08:23:53.03#ibcon#*before return 0, iclass 24, count 0 2006.201.08:23:53.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:53.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:23:53.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.08:23:53.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.08:23:53.03$vck44/vb=8,4 2006.201.08:23:53.03#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.08:23:53.03#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.08:23:53.03#ibcon#ireg 11 cls_cnt 2 2006.201.08:23:53.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:53.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:53.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:53.08#ibcon#enter wrdev, iclass 26, count 2 2006.201.08:23:53.08#ibcon#first serial, iclass 26, count 2 2006.201.08:23:53.08#ibcon#enter sib2, iclass 26, count 2 2006.201.08:23:53.08#ibcon#flushed, iclass 26, count 2 2006.201.08:23:53.08#ibcon#about to write, iclass 26, count 2 2006.201.08:23:53.08#ibcon#wrote, iclass 26, count 2 2006.201.08:23:53.08#ibcon#about to read 3, iclass 26, count 2 2006.201.08:23:53.10#ibcon#read 3, iclass 26, count 2 2006.201.08:23:53.10#ibcon#about to read 4, iclass 26, count 2 2006.201.08:23:53.10#ibcon#read 4, iclass 26, count 2 2006.201.08:23:53.10#ibcon#about to read 5, iclass 26, count 2 2006.201.08:23:53.10#ibcon#read 5, iclass 26, count 2 2006.201.08:23:53.10#ibcon#about to read 6, iclass 26, count 2 2006.201.08:23:53.10#ibcon#read 6, iclass 26, count 2 2006.201.08:23:53.10#ibcon#end of sib2, iclass 26, count 2 2006.201.08:23:53.10#ibcon#*mode == 0, iclass 26, count 2 2006.201.08:23:53.10#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.08:23:53.10#ibcon#[27=AT08-04\r\n] 2006.201.08:23:53.10#ibcon#*before write, iclass 26, count 2 2006.201.08:23:53.10#ibcon#enter sib2, iclass 26, count 2 2006.201.08:23:53.10#ibcon#flushed, iclass 26, count 2 2006.201.08:23:53.10#ibcon#about to write, iclass 26, count 2 2006.201.08:23:53.10#ibcon#wrote, iclass 26, count 2 2006.201.08:23:53.10#ibcon#about to read 3, iclass 26, count 2 2006.201.08:23:53.13#ibcon#read 3, iclass 26, count 2 2006.201.08:23:53.13#ibcon#about to read 4, iclass 26, count 2 2006.201.08:23:53.13#ibcon#read 4, iclass 26, count 2 2006.201.08:23:53.13#ibcon#about to read 5, iclass 26, count 2 2006.201.08:23:53.13#ibcon#read 5, iclass 26, count 2 2006.201.08:23:53.13#ibcon#about to read 6, iclass 26, count 2 2006.201.08:23:53.13#ibcon#read 6, iclass 26, count 2 2006.201.08:23:53.13#ibcon#end of sib2, iclass 26, count 2 2006.201.08:23:53.13#ibcon#*after write, iclass 26, count 2 2006.201.08:23:53.13#ibcon#*before return 0, iclass 26, count 2 2006.201.08:23:53.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:53.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:23:53.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.08:23:53.13#ibcon#ireg 7 cls_cnt 0 2006.201.08:23:53.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:53.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:53.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:53.25#ibcon#enter wrdev, iclass 26, count 0 2006.201.08:23:53.25#ibcon#first serial, iclass 26, count 0 2006.201.08:23:53.25#ibcon#enter sib2, iclass 26, count 0 2006.201.08:23:53.25#ibcon#flushed, iclass 26, count 0 2006.201.08:23:53.25#ibcon#about to write, iclass 26, count 0 2006.201.08:23:53.25#ibcon#wrote, iclass 26, count 0 2006.201.08:23:53.25#ibcon#about to read 3, iclass 26, count 0 2006.201.08:23:53.27#ibcon#read 3, iclass 26, count 0 2006.201.08:23:53.27#ibcon#about to read 4, iclass 26, count 0 2006.201.08:23:53.27#ibcon#read 4, iclass 26, count 0 2006.201.08:23:53.27#ibcon#about to read 5, iclass 26, count 0 2006.201.08:23:53.27#ibcon#read 5, iclass 26, count 0 2006.201.08:23:53.27#ibcon#about to read 6, iclass 26, count 0 2006.201.08:23:53.27#ibcon#read 6, iclass 26, count 0 2006.201.08:23:53.27#ibcon#end of sib2, iclass 26, count 0 2006.201.08:23:53.27#ibcon#*mode == 0, iclass 26, count 0 2006.201.08:23:53.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.08:23:53.27#ibcon#[27=USB\r\n] 2006.201.08:23:53.27#ibcon#*before write, iclass 26, count 0 2006.201.08:23:53.27#ibcon#enter sib2, iclass 26, count 0 2006.201.08:23:53.27#ibcon#flushed, iclass 26, count 0 2006.201.08:23:53.27#ibcon#about to write, iclass 26, count 0 2006.201.08:23:53.27#ibcon#wrote, iclass 26, count 0 2006.201.08:23:53.27#ibcon#about to read 3, iclass 26, count 0 2006.201.08:23:53.30#ibcon#read 3, iclass 26, count 0 2006.201.08:23:53.30#ibcon#about to read 4, iclass 26, count 0 2006.201.08:23:53.30#ibcon#read 4, iclass 26, count 0 2006.201.08:23:53.30#ibcon#about to read 5, iclass 26, count 0 2006.201.08:23:53.30#ibcon#read 5, iclass 26, count 0 2006.201.08:23:53.30#ibcon#about to read 6, iclass 26, count 0 2006.201.08:23:53.30#ibcon#read 6, iclass 26, count 0 2006.201.08:23:53.30#ibcon#end of sib2, iclass 26, count 0 2006.201.08:23:53.30#ibcon#*after write, iclass 26, count 0 2006.201.08:23:53.30#ibcon#*before return 0, iclass 26, count 0 2006.201.08:23:53.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:53.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:23:53.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.08:23:53.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.08:23:53.30$vck44/vabw=wide 2006.201.08:23:53.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.08:23:53.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.08:23:53.30#ibcon#ireg 8 cls_cnt 0 2006.201.08:23:53.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:53.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:53.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:53.30#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:23:53.30#ibcon#first serial, iclass 28, count 0 2006.201.08:23:53.30#ibcon#enter sib2, iclass 28, count 0 2006.201.08:23:53.30#ibcon#flushed, iclass 28, count 0 2006.201.08:23:53.30#ibcon#about to write, iclass 28, count 0 2006.201.08:23:53.30#ibcon#wrote, iclass 28, count 0 2006.201.08:23:53.30#ibcon#about to read 3, iclass 28, count 0 2006.201.08:23:53.32#ibcon#read 3, iclass 28, count 0 2006.201.08:23:53.32#ibcon#about to read 4, iclass 28, count 0 2006.201.08:23:53.32#ibcon#read 4, iclass 28, count 0 2006.201.08:23:53.32#ibcon#about to read 5, iclass 28, count 0 2006.201.08:23:53.32#ibcon#read 5, iclass 28, count 0 2006.201.08:23:53.32#ibcon#about to read 6, iclass 28, count 0 2006.201.08:23:53.32#ibcon#read 6, iclass 28, count 0 2006.201.08:23:53.32#ibcon#end of sib2, iclass 28, count 0 2006.201.08:23:53.32#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:23:53.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:23:53.32#ibcon#[25=BW32\r\n] 2006.201.08:23:53.32#ibcon#*before write, iclass 28, count 0 2006.201.08:23:53.32#ibcon#enter sib2, iclass 28, count 0 2006.201.08:23:53.32#ibcon#flushed, iclass 28, count 0 2006.201.08:23:53.32#ibcon#about to write, iclass 28, count 0 2006.201.08:23:53.32#ibcon#wrote, iclass 28, count 0 2006.201.08:23:53.32#ibcon#about to read 3, iclass 28, count 0 2006.201.08:23:53.35#ibcon#read 3, iclass 28, count 0 2006.201.08:23:53.35#ibcon#about to read 4, iclass 28, count 0 2006.201.08:23:53.35#ibcon#read 4, iclass 28, count 0 2006.201.08:23:53.35#ibcon#about to read 5, iclass 28, count 0 2006.201.08:23:53.35#ibcon#read 5, iclass 28, count 0 2006.201.08:23:53.35#ibcon#about to read 6, iclass 28, count 0 2006.201.08:23:53.35#ibcon#read 6, iclass 28, count 0 2006.201.08:23:53.35#ibcon#end of sib2, iclass 28, count 0 2006.201.08:23:53.35#ibcon#*after write, iclass 28, count 0 2006.201.08:23:53.35#ibcon#*before return 0, iclass 28, count 0 2006.201.08:23:53.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:53.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:23:53.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:23:53.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:23:53.35$vck44/vbbw=wide 2006.201.08:23:53.35#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.08:23:53.35#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.08:23:53.35#ibcon#ireg 8 cls_cnt 0 2006.201.08:23:53.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:23:53.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:23:53.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:23:53.42#ibcon#enter wrdev, iclass 30, count 0 2006.201.08:23:53.42#ibcon#first serial, iclass 30, count 0 2006.201.08:23:53.42#ibcon#enter sib2, iclass 30, count 0 2006.201.08:23:53.42#ibcon#flushed, iclass 30, count 0 2006.201.08:23:53.42#ibcon#about to write, iclass 30, count 0 2006.201.08:23:53.42#ibcon#wrote, iclass 30, count 0 2006.201.08:23:53.42#ibcon#about to read 3, iclass 30, count 0 2006.201.08:23:53.44#ibcon#read 3, iclass 30, count 0 2006.201.08:23:53.44#ibcon#about to read 4, iclass 30, count 0 2006.201.08:23:53.44#ibcon#read 4, iclass 30, count 0 2006.201.08:23:53.44#ibcon#about to read 5, iclass 30, count 0 2006.201.08:23:53.44#ibcon#read 5, iclass 30, count 0 2006.201.08:23:53.44#ibcon#about to read 6, iclass 30, count 0 2006.201.08:23:53.44#ibcon#read 6, iclass 30, count 0 2006.201.08:23:53.44#ibcon#end of sib2, iclass 30, count 0 2006.201.08:23:53.44#ibcon#*mode == 0, iclass 30, count 0 2006.201.08:23:53.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.08:23:53.44#ibcon#[27=BW32\r\n] 2006.201.08:23:53.44#ibcon#*before write, iclass 30, count 0 2006.201.08:23:53.44#ibcon#enter sib2, iclass 30, count 0 2006.201.08:23:53.44#ibcon#flushed, iclass 30, count 0 2006.201.08:23:53.44#ibcon#about to write, iclass 30, count 0 2006.201.08:23:53.44#ibcon#wrote, iclass 30, count 0 2006.201.08:23:53.44#ibcon#about to read 3, iclass 30, count 0 2006.201.08:23:53.47#ibcon#read 3, iclass 30, count 0 2006.201.08:23:53.47#ibcon#about to read 4, iclass 30, count 0 2006.201.08:23:53.47#ibcon#read 4, iclass 30, count 0 2006.201.08:23:53.47#ibcon#about to read 5, iclass 30, count 0 2006.201.08:23:53.47#ibcon#read 5, iclass 30, count 0 2006.201.08:23:53.47#ibcon#about to read 6, iclass 30, count 0 2006.201.08:23:53.47#ibcon#read 6, iclass 30, count 0 2006.201.08:23:53.47#ibcon#end of sib2, iclass 30, count 0 2006.201.08:23:53.47#ibcon#*after write, iclass 30, count 0 2006.201.08:23:53.47#ibcon#*before return 0, iclass 30, count 0 2006.201.08:23:53.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:23:53.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.08:23:53.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.08:23:53.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.08:23:53.47$setupk4/ifdk4 2006.201.08:23:53.47$ifdk4/lo= 2006.201.08:23:53.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:23:53.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:23:53.47$ifdk4/patch= 2006.201.08:23:53.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:23:53.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:23:53.47$setupk4/!*+20s 2006.201.08:23:54.20#abcon#<5=/04 2.2 4.1 23.21 871003.3\r\n> 2006.201.08:23:54.22#abcon#{5=INTERFACE CLEAR} 2006.201.08:23:54.28#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:24:04.37#abcon#<5=/04 2.2 4.1 23.21 871003.3\r\n> 2006.201.08:24:04.39#abcon#{5=INTERFACE CLEAR} 2006.201.08:24:04.45#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:24:07.94$setupk4/"tpicd 2006.201.08:24:07.94$setupk4/echo=off 2006.201.08:24:07.94$setupk4/xlog=off 2006.201.08:24:07.94:!2006.201.08:26:54 2006.201.08:24:24.14#trakl#Source acquired 2006.201.08:24:25.14#flagr#flagr/antenna,acquired 2006.201.08:26:54.00:preob 2006.201.08:26:54.13/onsource/TRACKING 2006.201.08:26:54.13:!2006.201.08:27:04 2006.201.08:27:04.00:"tape 2006.201.08:27:04.00:"st=record 2006.201.08:27:04.00:data_valid=on 2006.201.08:27:04.00:midob 2006.201.08:27:04.13/onsource/TRACKING 2006.201.08:27:04.13/wx/23.20,1003.4,88 2006.201.08:27:04.33/cable/+6.4672E-03 2006.201.08:27:05.42/va/01,08,usb,yes,27,29 2006.201.08:27:05.42/va/02,07,usb,yes,30,30 2006.201.08:27:05.42/va/03,08,usb,yes,26,28 2006.201.08:27:05.42/va/04,07,usb,yes,30,32 2006.201.08:27:05.42/va/05,04,usb,yes,27,27 2006.201.08:27:05.42/va/06,05,usb,yes,27,27 2006.201.08:27:05.42/va/07,05,usb,yes,26,27 2006.201.08:27:05.42/va/08,04,usb,yes,26,31 2006.201.08:27:05.65/valo/01,524.99,yes,locked 2006.201.08:27:05.65/valo/02,534.99,yes,locked 2006.201.08:27:05.65/valo/03,564.99,yes,locked 2006.201.08:27:05.65/valo/04,624.99,yes,locked 2006.201.08:27:05.65/valo/05,734.99,yes,locked 2006.201.08:27:05.65/valo/06,814.99,yes,locked 2006.201.08:27:05.65/valo/07,864.99,yes,locked 2006.201.08:27:05.65/valo/08,884.99,yes,locked 2006.201.08:27:06.74/vb/01,04,usb,yes,28,26 2006.201.08:27:06.74/vb/02,05,usb,yes,27,27 2006.201.08:27:06.74/vb/03,04,usb,yes,28,31 2006.201.08:27:06.74/vb/04,05,usb,yes,28,27 2006.201.08:27:06.74/vb/05,04,usb,yes,25,27 2006.201.08:27:06.74/vb/06,04,usb,yes,29,25 2006.201.08:27:06.74/vb/07,04,usb,yes,29,29 2006.201.08:27:06.74/vb/08,04,usb,yes,26,30 2006.201.08:27:06.97/vblo/01,629.99,yes,locked 2006.201.08:27:06.97/vblo/02,634.99,yes,locked 2006.201.08:27:06.97/vblo/03,649.99,yes,locked 2006.201.08:27:06.97/vblo/04,679.99,yes,locked 2006.201.08:27:06.97/vblo/05,709.99,yes,locked 2006.201.08:27:06.97/vblo/06,719.99,yes,locked 2006.201.08:27:06.97/vblo/07,734.99,yes,locked 2006.201.08:27:06.97/vblo/08,744.99,yes,locked 2006.201.08:27:07.12/vabw/8 2006.201.08:27:07.27/vbbw/8 2006.201.08:27:07.36/xfe/off,on,15.2 2006.201.08:27:07.76/ifatt/23,28,28,28 2006.201.08:27:08.06/fmout-gps/S +4.56E-07 2006.201.08:27:08.10:!2006.201.08:33:04 2006.201.08:28:15.14#trakl#Off source 2006.201.08:28:15.14?ERROR st -7 Antenna off-source! 2006.201.08:28:15.14#trakl#az 240.427 el 82.782 azerr*cos(el) 0.0001 elerr -0.0164 2006.201.08:28:15.14#flagr#flagr/antenna,off-source 2006.201.08:28:21.14#trakl#Source re-acquired 2006.201.08:28:21.14#flagr#flagr/antenna,re-acquired 2006.201.08:33:04.00:data_valid=off 2006.201.08:33:04.00:"et 2006.201.08:33:04.00:!+3s 2006.201.08:33:07.02:"tape 2006.201.08:33:07.02:postob 2006.201.08:33:07.11/cable/+6.4670E-03 2006.201.08:33:07.11/wx/23.17,1003.5,88 2006.201.08:33:07.17/fmout-gps/S +4.55E-07 2006.201.08:33:07.17:scan_name=201-0834,jd0607,40 2006.201.08:33:07.17:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.201.08:33:08.14#flagr#flagr/antenna,new-source 2006.201.08:33:08.14:checkk5 2006.201.08:33:08.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:33:08.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:33:09.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:33:09.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:33:10.04/chk_obsdata//k5ts1/T2010827??a.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.201.08:33:10.41/chk_obsdata//k5ts2/T2010827??b.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.201.08:33:10.78/chk_obsdata//k5ts3/T2010827??c.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.201.08:33:11.15/chk_obsdata//k5ts4/T2010827??d.dat file size is correct (nominal:1440MB, actual:1440MB). 2006.201.08:33:11.83/k5log//k5ts1_log_newline 2006.201.08:33:12.51/k5log//k5ts2_log_newline 2006.201.08:33:13.20/k5log//k5ts3_log_newline 2006.201.08:33:13.89/k5log//k5ts4_log_newline 2006.201.08:33:13.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:33:13.91:setupk4=1 2006.201.08:33:13.91$setupk4/echo=on 2006.201.08:33:13.91$setupk4/pcalon 2006.201.08:33:13.91$pcalon/"no phase cal control is implemented here 2006.201.08:33:13.91$setupk4/"tpicd=stop 2006.201.08:33:13.91$setupk4/"rec=synch_on 2006.201.08:33:13.91$setupk4/"rec_mode=128 2006.201.08:33:13.91$setupk4/!* 2006.201.08:33:13.91$setupk4/recpk4 2006.201.08:33:13.91$recpk4/recpatch= 2006.201.08:33:13.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:33:13.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:33:13.92$setupk4/vck44 2006.201.08:33:13.92$vck44/valo=1,524.99 2006.201.08:33:13.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.08:33:13.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.08:33:13.92#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:13.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:33:13.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:33:13.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:33:13.92#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:33:13.92#ibcon#first serial, iclass 6, count 0 2006.201.08:33:13.92#ibcon#enter sib2, iclass 6, count 0 2006.201.08:33:13.92#ibcon#flushed, iclass 6, count 0 2006.201.08:33:13.92#ibcon#about to write, iclass 6, count 0 2006.201.08:33:13.92#ibcon#wrote, iclass 6, count 0 2006.201.08:33:13.92#ibcon#about to read 3, iclass 6, count 0 2006.201.08:33:13.95#abcon#{5=INTERFACE CLEAR} 2006.201.08:33:13.95#ibcon#read 3, iclass 6, count 0 2006.201.08:33:13.95#ibcon#about to read 4, iclass 6, count 0 2006.201.08:33:13.95#ibcon#read 4, iclass 6, count 0 2006.201.08:33:13.95#ibcon#about to read 5, iclass 6, count 0 2006.201.08:33:13.95#ibcon#read 5, iclass 6, count 0 2006.201.08:33:13.95#ibcon#about to read 6, iclass 6, count 0 2006.201.08:33:13.95#ibcon#read 6, iclass 6, count 0 2006.201.08:33:13.95#ibcon#end of sib2, iclass 6, count 0 2006.201.08:33:13.95#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:33:13.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:33:13.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:33:13.95#ibcon#*before write, iclass 6, count 0 2006.201.08:33:13.95#ibcon#enter sib2, iclass 6, count 0 2006.201.08:33:13.95#ibcon#flushed, iclass 6, count 0 2006.201.08:33:13.95#ibcon#about to write, iclass 6, count 0 2006.201.08:33:13.95#ibcon#wrote, iclass 6, count 0 2006.201.08:33:13.95#ibcon#about to read 3, iclass 6, count 0 2006.201.08:33:14.00#ibcon#read 3, iclass 6, count 0 2006.201.08:33:14.00#ibcon#about to read 4, iclass 6, count 0 2006.201.08:33:14.00#ibcon#read 4, iclass 6, count 0 2006.201.08:33:14.00#ibcon#about to read 5, iclass 6, count 0 2006.201.08:33:14.00#ibcon#read 5, iclass 6, count 0 2006.201.08:33:14.00#ibcon#about to read 6, iclass 6, count 0 2006.201.08:33:14.00#ibcon#read 6, iclass 6, count 0 2006.201.08:33:14.00#ibcon#end of sib2, iclass 6, count 0 2006.201.08:33:14.00#ibcon#*after write, iclass 6, count 0 2006.201.08:33:14.00#ibcon#*before return 0, iclass 6, count 0 2006.201.08:33:14.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:33:14.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:33:14.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:33:14.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:33:14.00$vck44/va=1,8 2006.201.08:33:14.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.08:33:14.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.08:33:14.00#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:14.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:14.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:14.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:14.00#ibcon#enter wrdev, iclass 11, count 2 2006.201.08:33:14.00#ibcon#first serial, iclass 11, count 2 2006.201.08:33:14.00#ibcon#enter sib2, iclass 11, count 2 2006.201.08:33:14.00#ibcon#flushed, iclass 11, count 2 2006.201.08:33:14.00#ibcon#about to write, iclass 11, count 2 2006.201.08:33:14.00#ibcon#wrote, iclass 11, count 2 2006.201.08:33:14.00#ibcon#about to read 3, iclass 11, count 2 2006.201.08:33:14.01#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:33:14.02#ibcon#read 3, iclass 11, count 2 2006.201.08:33:14.02#ibcon#about to read 4, iclass 11, count 2 2006.201.08:33:14.02#ibcon#read 4, iclass 11, count 2 2006.201.08:33:14.02#ibcon#about to read 5, iclass 11, count 2 2006.201.08:33:14.02#ibcon#read 5, iclass 11, count 2 2006.201.08:33:14.02#ibcon#about to read 6, iclass 11, count 2 2006.201.08:33:14.02#ibcon#read 6, iclass 11, count 2 2006.201.08:33:14.02#ibcon#end of sib2, iclass 11, count 2 2006.201.08:33:14.02#ibcon#*mode == 0, iclass 11, count 2 2006.201.08:33:14.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.08:33:14.02#ibcon#[25=AT01-08\r\n] 2006.201.08:33:14.02#ibcon#*before write, iclass 11, count 2 2006.201.08:33:14.02#ibcon#enter sib2, iclass 11, count 2 2006.201.08:33:14.02#ibcon#flushed, iclass 11, count 2 2006.201.08:33:14.02#ibcon#about to write, iclass 11, count 2 2006.201.08:33:14.02#ibcon#wrote, iclass 11, count 2 2006.201.08:33:14.02#ibcon#about to read 3, iclass 11, count 2 2006.201.08:33:14.05#ibcon#read 3, iclass 11, count 2 2006.201.08:33:14.05#ibcon#about to read 4, iclass 11, count 2 2006.201.08:33:14.05#ibcon#read 4, iclass 11, count 2 2006.201.08:33:14.05#ibcon#about to read 5, iclass 11, count 2 2006.201.08:33:14.05#ibcon#read 5, iclass 11, count 2 2006.201.08:33:14.05#ibcon#about to read 6, iclass 11, count 2 2006.201.08:33:14.05#ibcon#read 6, iclass 11, count 2 2006.201.08:33:14.05#ibcon#end of sib2, iclass 11, count 2 2006.201.08:33:14.05#ibcon#*after write, iclass 11, count 2 2006.201.08:33:14.05#ibcon#*before return 0, iclass 11, count 2 2006.201.08:33:14.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:14.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:14.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.08:33:14.05#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:14.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:14.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:14.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:14.17#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:33:14.17#ibcon#first serial, iclass 11, count 0 2006.201.08:33:14.17#ibcon#enter sib2, iclass 11, count 0 2006.201.08:33:14.17#ibcon#flushed, iclass 11, count 0 2006.201.08:33:14.17#ibcon#about to write, iclass 11, count 0 2006.201.08:33:14.17#ibcon#wrote, iclass 11, count 0 2006.201.08:33:14.17#ibcon#about to read 3, iclass 11, count 0 2006.201.08:33:14.19#ibcon#read 3, iclass 11, count 0 2006.201.08:33:14.19#ibcon#about to read 4, iclass 11, count 0 2006.201.08:33:14.19#ibcon#read 4, iclass 11, count 0 2006.201.08:33:14.19#ibcon#about to read 5, iclass 11, count 0 2006.201.08:33:14.19#ibcon#read 5, iclass 11, count 0 2006.201.08:33:14.19#ibcon#about to read 6, iclass 11, count 0 2006.201.08:33:14.19#ibcon#read 6, iclass 11, count 0 2006.201.08:33:14.19#ibcon#end of sib2, iclass 11, count 0 2006.201.08:33:14.19#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:33:14.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:33:14.19#ibcon#[25=USB\r\n] 2006.201.08:33:14.19#ibcon#*before write, iclass 11, count 0 2006.201.08:33:14.19#ibcon#enter sib2, iclass 11, count 0 2006.201.08:33:14.19#ibcon#flushed, iclass 11, count 0 2006.201.08:33:14.19#ibcon#about to write, iclass 11, count 0 2006.201.08:33:14.19#ibcon#wrote, iclass 11, count 0 2006.201.08:33:14.19#ibcon#about to read 3, iclass 11, count 0 2006.201.08:33:14.22#ibcon#read 3, iclass 11, count 0 2006.201.08:33:14.22#ibcon#about to read 4, iclass 11, count 0 2006.201.08:33:14.22#ibcon#read 4, iclass 11, count 0 2006.201.08:33:14.22#ibcon#about to read 5, iclass 11, count 0 2006.201.08:33:14.22#ibcon#read 5, iclass 11, count 0 2006.201.08:33:14.22#ibcon#about to read 6, iclass 11, count 0 2006.201.08:33:14.22#ibcon#read 6, iclass 11, count 0 2006.201.08:33:14.22#ibcon#end of sib2, iclass 11, count 0 2006.201.08:33:14.22#ibcon#*after write, iclass 11, count 0 2006.201.08:33:14.22#ibcon#*before return 0, iclass 11, count 0 2006.201.08:33:14.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:14.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:14.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:33:14.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:33:14.22$vck44/valo=2,534.99 2006.201.08:33:14.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.08:33:14.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.08:33:14.22#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:14.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:14.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:14.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:14.22#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:33:14.22#ibcon#first serial, iclass 13, count 0 2006.201.08:33:14.22#ibcon#enter sib2, iclass 13, count 0 2006.201.08:33:14.22#ibcon#flushed, iclass 13, count 0 2006.201.08:33:14.22#ibcon#about to write, iclass 13, count 0 2006.201.08:33:14.22#ibcon#wrote, iclass 13, count 0 2006.201.08:33:14.22#ibcon#about to read 3, iclass 13, count 0 2006.201.08:33:14.24#ibcon#read 3, iclass 13, count 0 2006.201.08:33:14.24#ibcon#about to read 4, iclass 13, count 0 2006.201.08:33:14.24#ibcon#read 4, iclass 13, count 0 2006.201.08:33:14.24#ibcon#about to read 5, iclass 13, count 0 2006.201.08:33:14.24#ibcon#read 5, iclass 13, count 0 2006.201.08:33:14.24#ibcon#about to read 6, iclass 13, count 0 2006.201.08:33:14.24#ibcon#read 6, iclass 13, count 0 2006.201.08:33:14.24#ibcon#end of sib2, iclass 13, count 0 2006.201.08:33:14.24#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:33:14.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:33:14.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:33:14.24#ibcon#*before write, iclass 13, count 0 2006.201.08:33:14.24#ibcon#enter sib2, iclass 13, count 0 2006.201.08:33:14.24#ibcon#flushed, iclass 13, count 0 2006.201.08:33:14.24#ibcon#about to write, iclass 13, count 0 2006.201.08:33:14.24#ibcon#wrote, iclass 13, count 0 2006.201.08:33:14.24#ibcon#about to read 3, iclass 13, count 0 2006.201.08:33:14.28#ibcon#read 3, iclass 13, count 0 2006.201.08:33:14.28#ibcon#about to read 4, iclass 13, count 0 2006.201.08:33:14.28#ibcon#read 4, iclass 13, count 0 2006.201.08:33:14.28#ibcon#about to read 5, iclass 13, count 0 2006.201.08:33:14.28#ibcon#read 5, iclass 13, count 0 2006.201.08:33:14.28#ibcon#about to read 6, iclass 13, count 0 2006.201.08:33:14.28#ibcon#read 6, iclass 13, count 0 2006.201.08:33:14.28#ibcon#end of sib2, iclass 13, count 0 2006.201.08:33:14.28#ibcon#*after write, iclass 13, count 0 2006.201.08:33:14.28#ibcon#*before return 0, iclass 13, count 0 2006.201.08:33:14.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:14.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:14.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:33:14.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:33:14.28$vck44/va=2,7 2006.201.08:33:14.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.08:33:14.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.08:33:14.28#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:14.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:14.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:14.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:14.34#ibcon#enter wrdev, iclass 15, count 2 2006.201.08:33:14.34#ibcon#first serial, iclass 15, count 2 2006.201.08:33:14.34#ibcon#enter sib2, iclass 15, count 2 2006.201.08:33:14.34#ibcon#flushed, iclass 15, count 2 2006.201.08:33:14.34#ibcon#about to write, iclass 15, count 2 2006.201.08:33:14.34#ibcon#wrote, iclass 15, count 2 2006.201.08:33:14.34#ibcon#about to read 3, iclass 15, count 2 2006.201.08:33:14.36#ibcon#read 3, iclass 15, count 2 2006.201.08:33:14.36#ibcon#about to read 4, iclass 15, count 2 2006.201.08:33:14.36#ibcon#read 4, iclass 15, count 2 2006.201.08:33:14.36#ibcon#about to read 5, iclass 15, count 2 2006.201.08:33:14.36#ibcon#read 5, iclass 15, count 2 2006.201.08:33:14.36#ibcon#about to read 6, iclass 15, count 2 2006.201.08:33:14.36#ibcon#read 6, iclass 15, count 2 2006.201.08:33:14.36#ibcon#end of sib2, iclass 15, count 2 2006.201.08:33:14.36#ibcon#*mode == 0, iclass 15, count 2 2006.201.08:33:14.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.08:33:14.36#ibcon#[25=AT02-07\r\n] 2006.201.08:33:14.36#ibcon#*before write, iclass 15, count 2 2006.201.08:33:14.36#ibcon#enter sib2, iclass 15, count 2 2006.201.08:33:14.36#ibcon#flushed, iclass 15, count 2 2006.201.08:33:14.36#ibcon#about to write, iclass 15, count 2 2006.201.08:33:14.36#ibcon#wrote, iclass 15, count 2 2006.201.08:33:14.36#ibcon#about to read 3, iclass 15, count 2 2006.201.08:33:14.39#ibcon#read 3, iclass 15, count 2 2006.201.08:33:14.39#ibcon#about to read 4, iclass 15, count 2 2006.201.08:33:14.39#ibcon#read 4, iclass 15, count 2 2006.201.08:33:14.39#ibcon#about to read 5, iclass 15, count 2 2006.201.08:33:14.39#ibcon#read 5, iclass 15, count 2 2006.201.08:33:14.39#ibcon#about to read 6, iclass 15, count 2 2006.201.08:33:14.39#ibcon#read 6, iclass 15, count 2 2006.201.08:33:14.39#ibcon#end of sib2, iclass 15, count 2 2006.201.08:33:14.39#ibcon#*after write, iclass 15, count 2 2006.201.08:33:14.39#ibcon#*before return 0, iclass 15, count 2 2006.201.08:33:14.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:14.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:14.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.08:33:14.39#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:14.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:14.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:14.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:14.51#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:33:14.51#ibcon#first serial, iclass 15, count 0 2006.201.08:33:14.51#ibcon#enter sib2, iclass 15, count 0 2006.201.08:33:14.51#ibcon#flushed, iclass 15, count 0 2006.201.08:33:14.51#ibcon#about to write, iclass 15, count 0 2006.201.08:33:14.51#ibcon#wrote, iclass 15, count 0 2006.201.08:33:14.51#ibcon#about to read 3, iclass 15, count 0 2006.201.08:33:14.53#ibcon#read 3, iclass 15, count 0 2006.201.08:33:14.53#ibcon#about to read 4, iclass 15, count 0 2006.201.08:33:14.53#ibcon#read 4, iclass 15, count 0 2006.201.08:33:14.53#ibcon#about to read 5, iclass 15, count 0 2006.201.08:33:14.53#ibcon#read 5, iclass 15, count 0 2006.201.08:33:14.53#ibcon#about to read 6, iclass 15, count 0 2006.201.08:33:14.53#ibcon#read 6, iclass 15, count 0 2006.201.08:33:14.53#ibcon#end of sib2, iclass 15, count 0 2006.201.08:33:14.53#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:33:14.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:33:14.53#ibcon#[25=USB\r\n] 2006.201.08:33:14.53#ibcon#*before write, iclass 15, count 0 2006.201.08:33:14.53#ibcon#enter sib2, iclass 15, count 0 2006.201.08:33:14.53#ibcon#flushed, iclass 15, count 0 2006.201.08:33:14.53#ibcon#about to write, iclass 15, count 0 2006.201.08:33:14.53#ibcon#wrote, iclass 15, count 0 2006.201.08:33:14.53#ibcon#about to read 3, iclass 15, count 0 2006.201.08:33:14.56#ibcon#read 3, iclass 15, count 0 2006.201.08:33:14.56#ibcon#about to read 4, iclass 15, count 0 2006.201.08:33:14.56#ibcon#read 4, iclass 15, count 0 2006.201.08:33:14.56#ibcon#about to read 5, iclass 15, count 0 2006.201.08:33:14.56#ibcon#read 5, iclass 15, count 0 2006.201.08:33:14.56#ibcon#about to read 6, iclass 15, count 0 2006.201.08:33:14.56#ibcon#read 6, iclass 15, count 0 2006.201.08:33:14.56#ibcon#end of sib2, iclass 15, count 0 2006.201.08:33:14.56#ibcon#*after write, iclass 15, count 0 2006.201.08:33:14.56#ibcon#*before return 0, iclass 15, count 0 2006.201.08:33:14.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:14.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:14.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:33:14.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:33:14.56$vck44/valo=3,564.99 2006.201.08:33:14.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.08:33:14.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.08:33:14.56#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:14.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:14.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:14.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:14.56#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:33:14.56#ibcon#first serial, iclass 17, count 0 2006.201.08:33:14.56#ibcon#enter sib2, iclass 17, count 0 2006.201.08:33:14.56#ibcon#flushed, iclass 17, count 0 2006.201.08:33:14.56#ibcon#about to write, iclass 17, count 0 2006.201.08:33:14.56#ibcon#wrote, iclass 17, count 0 2006.201.08:33:14.56#ibcon#about to read 3, iclass 17, count 0 2006.201.08:33:14.58#ibcon#read 3, iclass 17, count 0 2006.201.08:33:14.58#ibcon#about to read 4, iclass 17, count 0 2006.201.08:33:14.58#ibcon#read 4, iclass 17, count 0 2006.201.08:33:14.58#ibcon#about to read 5, iclass 17, count 0 2006.201.08:33:14.58#ibcon#read 5, iclass 17, count 0 2006.201.08:33:14.58#ibcon#about to read 6, iclass 17, count 0 2006.201.08:33:14.58#ibcon#read 6, iclass 17, count 0 2006.201.08:33:14.58#ibcon#end of sib2, iclass 17, count 0 2006.201.08:33:14.58#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:33:14.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:33:14.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:33:14.58#ibcon#*before write, iclass 17, count 0 2006.201.08:33:14.58#ibcon#enter sib2, iclass 17, count 0 2006.201.08:33:14.58#ibcon#flushed, iclass 17, count 0 2006.201.08:33:14.58#ibcon#about to write, iclass 17, count 0 2006.201.08:33:14.58#ibcon#wrote, iclass 17, count 0 2006.201.08:33:14.58#ibcon#about to read 3, iclass 17, count 0 2006.201.08:33:14.63#ibcon#read 3, iclass 17, count 0 2006.201.08:33:14.63#ibcon#about to read 4, iclass 17, count 0 2006.201.08:33:14.63#ibcon#read 4, iclass 17, count 0 2006.201.08:33:14.63#ibcon#about to read 5, iclass 17, count 0 2006.201.08:33:14.63#ibcon#read 5, iclass 17, count 0 2006.201.08:33:14.63#ibcon#about to read 6, iclass 17, count 0 2006.201.08:33:14.63#ibcon#read 6, iclass 17, count 0 2006.201.08:33:14.63#ibcon#end of sib2, iclass 17, count 0 2006.201.08:33:14.63#ibcon#*after write, iclass 17, count 0 2006.201.08:33:14.63#ibcon#*before return 0, iclass 17, count 0 2006.201.08:33:14.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:14.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:14.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:33:14.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:33:14.63$vck44/va=3,8 2006.201.08:33:14.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.08:33:14.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.08:33:14.63#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:14.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:14.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:14.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:14.68#ibcon#enter wrdev, iclass 19, count 2 2006.201.08:33:14.68#ibcon#first serial, iclass 19, count 2 2006.201.08:33:14.68#ibcon#enter sib2, iclass 19, count 2 2006.201.08:33:14.68#ibcon#flushed, iclass 19, count 2 2006.201.08:33:14.68#ibcon#about to write, iclass 19, count 2 2006.201.08:33:14.68#ibcon#wrote, iclass 19, count 2 2006.201.08:33:14.68#ibcon#about to read 3, iclass 19, count 2 2006.201.08:33:14.70#ibcon#read 3, iclass 19, count 2 2006.201.08:33:14.70#ibcon#about to read 4, iclass 19, count 2 2006.201.08:33:14.70#ibcon#read 4, iclass 19, count 2 2006.201.08:33:14.70#ibcon#about to read 5, iclass 19, count 2 2006.201.08:33:14.70#ibcon#read 5, iclass 19, count 2 2006.201.08:33:14.70#ibcon#about to read 6, iclass 19, count 2 2006.201.08:33:14.70#ibcon#read 6, iclass 19, count 2 2006.201.08:33:14.70#ibcon#end of sib2, iclass 19, count 2 2006.201.08:33:14.70#ibcon#*mode == 0, iclass 19, count 2 2006.201.08:33:14.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.08:33:14.70#ibcon#[25=AT03-08\r\n] 2006.201.08:33:14.70#ibcon#*before write, iclass 19, count 2 2006.201.08:33:14.70#ibcon#enter sib2, iclass 19, count 2 2006.201.08:33:14.70#ibcon#flushed, iclass 19, count 2 2006.201.08:33:14.70#ibcon#about to write, iclass 19, count 2 2006.201.08:33:14.70#ibcon#wrote, iclass 19, count 2 2006.201.08:33:14.70#ibcon#about to read 3, iclass 19, count 2 2006.201.08:33:14.73#ibcon#read 3, iclass 19, count 2 2006.201.08:33:14.73#ibcon#about to read 4, iclass 19, count 2 2006.201.08:33:14.73#ibcon#read 4, iclass 19, count 2 2006.201.08:33:14.73#ibcon#about to read 5, iclass 19, count 2 2006.201.08:33:14.73#ibcon#read 5, iclass 19, count 2 2006.201.08:33:14.73#ibcon#about to read 6, iclass 19, count 2 2006.201.08:33:14.73#ibcon#read 6, iclass 19, count 2 2006.201.08:33:14.73#ibcon#end of sib2, iclass 19, count 2 2006.201.08:33:14.73#ibcon#*after write, iclass 19, count 2 2006.201.08:33:14.73#ibcon#*before return 0, iclass 19, count 2 2006.201.08:33:14.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:14.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:14.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.08:33:14.73#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:14.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:14.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:14.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:14.85#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:33:14.85#ibcon#first serial, iclass 19, count 0 2006.201.08:33:14.85#ibcon#enter sib2, iclass 19, count 0 2006.201.08:33:14.85#ibcon#flushed, iclass 19, count 0 2006.201.08:33:14.85#ibcon#about to write, iclass 19, count 0 2006.201.08:33:14.85#ibcon#wrote, iclass 19, count 0 2006.201.08:33:14.85#ibcon#about to read 3, iclass 19, count 0 2006.201.08:33:14.87#ibcon#read 3, iclass 19, count 0 2006.201.08:33:14.87#ibcon#about to read 4, iclass 19, count 0 2006.201.08:33:14.87#ibcon#read 4, iclass 19, count 0 2006.201.08:33:14.87#ibcon#about to read 5, iclass 19, count 0 2006.201.08:33:14.87#ibcon#read 5, iclass 19, count 0 2006.201.08:33:14.87#ibcon#about to read 6, iclass 19, count 0 2006.201.08:33:14.87#ibcon#read 6, iclass 19, count 0 2006.201.08:33:14.87#ibcon#end of sib2, iclass 19, count 0 2006.201.08:33:14.87#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:33:14.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:33:14.87#ibcon#[25=USB\r\n] 2006.201.08:33:14.87#ibcon#*before write, iclass 19, count 0 2006.201.08:33:14.87#ibcon#enter sib2, iclass 19, count 0 2006.201.08:33:14.87#ibcon#flushed, iclass 19, count 0 2006.201.08:33:14.87#ibcon#about to write, iclass 19, count 0 2006.201.08:33:14.87#ibcon#wrote, iclass 19, count 0 2006.201.08:33:14.87#ibcon#about to read 3, iclass 19, count 0 2006.201.08:33:14.90#ibcon#read 3, iclass 19, count 0 2006.201.08:33:14.90#ibcon#about to read 4, iclass 19, count 0 2006.201.08:33:14.90#ibcon#read 4, iclass 19, count 0 2006.201.08:33:14.90#ibcon#about to read 5, iclass 19, count 0 2006.201.08:33:14.90#ibcon#read 5, iclass 19, count 0 2006.201.08:33:14.90#ibcon#about to read 6, iclass 19, count 0 2006.201.08:33:14.90#ibcon#read 6, iclass 19, count 0 2006.201.08:33:14.90#ibcon#end of sib2, iclass 19, count 0 2006.201.08:33:14.90#ibcon#*after write, iclass 19, count 0 2006.201.08:33:14.90#ibcon#*before return 0, iclass 19, count 0 2006.201.08:33:14.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:14.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:14.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:33:14.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:33:14.90$vck44/valo=4,624.99 2006.201.08:33:14.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.08:33:14.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.08:33:14.90#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:14.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:14.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:14.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:14.90#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:33:14.90#ibcon#first serial, iclass 21, count 0 2006.201.08:33:14.90#ibcon#enter sib2, iclass 21, count 0 2006.201.08:33:14.90#ibcon#flushed, iclass 21, count 0 2006.201.08:33:14.90#ibcon#about to write, iclass 21, count 0 2006.201.08:33:14.90#ibcon#wrote, iclass 21, count 0 2006.201.08:33:14.90#ibcon#about to read 3, iclass 21, count 0 2006.201.08:33:14.92#ibcon#read 3, iclass 21, count 0 2006.201.08:33:14.92#ibcon#about to read 4, iclass 21, count 0 2006.201.08:33:14.92#ibcon#read 4, iclass 21, count 0 2006.201.08:33:14.92#ibcon#about to read 5, iclass 21, count 0 2006.201.08:33:14.92#ibcon#read 5, iclass 21, count 0 2006.201.08:33:14.92#ibcon#about to read 6, iclass 21, count 0 2006.201.08:33:14.92#ibcon#read 6, iclass 21, count 0 2006.201.08:33:14.92#ibcon#end of sib2, iclass 21, count 0 2006.201.08:33:14.92#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:33:14.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:33:14.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:33:14.92#ibcon#*before write, iclass 21, count 0 2006.201.08:33:14.92#ibcon#enter sib2, iclass 21, count 0 2006.201.08:33:14.92#ibcon#flushed, iclass 21, count 0 2006.201.08:33:14.92#ibcon#about to write, iclass 21, count 0 2006.201.08:33:14.92#ibcon#wrote, iclass 21, count 0 2006.201.08:33:14.92#ibcon#about to read 3, iclass 21, count 0 2006.201.08:33:14.97#ibcon#read 3, iclass 21, count 0 2006.201.08:33:14.97#ibcon#about to read 4, iclass 21, count 0 2006.201.08:33:14.97#ibcon#read 4, iclass 21, count 0 2006.201.08:33:14.97#ibcon#about to read 5, iclass 21, count 0 2006.201.08:33:14.97#ibcon#read 5, iclass 21, count 0 2006.201.08:33:14.97#ibcon#about to read 6, iclass 21, count 0 2006.201.08:33:14.97#ibcon#read 6, iclass 21, count 0 2006.201.08:33:14.97#ibcon#end of sib2, iclass 21, count 0 2006.201.08:33:14.97#ibcon#*after write, iclass 21, count 0 2006.201.08:33:14.97#ibcon#*before return 0, iclass 21, count 0 2006.201.08:33:14.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:14.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:14.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:33:14.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:33:14.97$vck44/va=4,7 2006.201.08:33:14.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.08:33:14.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.08:33:14.97#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:14.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:15.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:15.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:15.02#ibcon#enter wrdev, iclass 23, count 2 2006.201.08:33:15.02#ibcon#first serial, iclass 23, count 2 2006.201.08:33:15.02#ibcon#enter sib2, iclass 23, count 2 2006.201.08:33:15.02#ibcon#flushed, iclass 23, count 2 2006.201.08:33:15.02#ibcon#about to write, iclass 23, count 2 2006.201.08:33:15.02#ibcon#wrote, iclass 23, count 2 2006.201.08:33:15.02#ibcon#about to read 3, iclass 23, count 2 2006.201.08:33:15.04#ibcon#read 3, iclass 23, count 2 2006.201.08:33:15.04#ibcon#about to read 4, iclass 23, count 2 2006.201.08:33:15.04#ibcon#read 4, iclass 23, count 2 2006.201.08:33:15.04#ibcon#about to read 5, iclass 23, count 2 2006.201.08:33:15.04#ibcon#read 5, iclass 23, count 2 2006.201.08:33:15.04#ibcon#about to read 6, iclass 23, count 2 2006.201.08:33:15.04#ibcon#read 6, iclass 23, count 2 2006.201.08:33:15.04#ibcon#end of sib2, iclass 23, count 2 2006.201.08:33:15.04#ibcon#*mode == 0, iclass 23, count 2 2006.201.08:33:15.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.08:33:15.04#ibcon#[25=AT04-07\r\n] 2006.201.08:33:15.04#ibcon#*before write, iclass 23, count 2 2006.201.08:33:15.04#ibcon#enter sib2, iclass 23, count 2 2006.201.08:33:15.04#ibcon#flushed, iclass 23, count 2 2006.201.08:33:15.04#ibcon#about to write, iclass 23, count 2 2006.201.08:33:15.04#ibcon#wrote, iclass 23, count 2 2006.201.08:33:15.04#ibcon#about to read 3, iclass 23, count 2 2006.201.08:33:15.07#ibcon#read 3, iclass 23, count 2 2006.201.08:33:15.07#ibcon#about to read 4, iclass 23, count 2 2006.201.08:33:15.07#ibcon#read 4, iclass 23, count 2 2006.201.08:33:15.07#ibcon#about to read 5, iclass 23, count 2 2006.201.08:33:15.07#ibcon#read 5, iclass 23, count 2 2006.201.08:33:15.07#ibcon#about to read 6, iclass 23, count 2 2006.201.08:33:15.07#ibcon#read 6, iclass 23, count 2 2006.201.08:33:15.07#ibcon#end of sib2, iclass 23, count 2 2006.201.08:33:15.07#ibcon#*after write, iclass 23, count 2 2006.201.08:33:15.07#ibcon#*before return 0, iclass 23, count 2 2006.201.08:33:15.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:15.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:15.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.08:33:15.07#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:15.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:15.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:15.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:15.19#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:33:15.19#ibcon#first serial, iclass 23, count 0 2006.201.08:33:15.19#ibcon#enter sib2, iclass 23, count 0 2006.201.08:33:15.19#ibcon#flushed, iclass 23, count 0 2006.201.08:33:15.19#ibcon#about to write, iclass 23, count 0 2006.201.08:33:15.19#ibcon#wrote, iclass 23, count 0 2006.201.08:33:15.19#ibcon#about to read 3, iclass 23, count 0 2006.201.08:33:15.21#ibcon#read 3, iclass 23, count 0 2006.201.08:33:15.21#ibcon#about to read 4, iclass 23, count 0 2006.201.08:33:15.21#ibcon#read 4, iclass 23, count 0 2006.201.08:33:15.21#ibcon#about to read 5, iclass 23, count 0 2006.201.08:33:15.21#ibcon#read 5, iclass 23, count 0 2006.201.08:33:15.21#ibcon#about to read 6, iclass 23, count 0 2006.201.08:33:15.21#ibcon#read 6, iclass 23, count 0 2006.201.08:33:15.21#ibcon#end of sib2, iclass 23, count 0 2006.201.08:33:15.21#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:33:15.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:33:15.21#ibcon#[25=USB\r\n] 2006.201.08:33:15.21#ibcon#*before write, iclass 23, count 0 2006.201.08:33:15.21#ibcon#enter sib2, iclass 23, count 0 2006.201.08:33:15.21#ibcon#flushed, iclass 23, count 0 2006.201.08:33:15.21#ibcon#about to write, iclass 23, count 0 2006.201.08:33:15.21#ibcon#wrote, iclass 23, count 0 2006.201.08:33:15.21#ibcon#about to read 3, iclass 23, count 0 2006.201.08:33:15.24#ibcon#read 3, iclass 23, count 0 2006.201.08:33:15.24#ibcon#about to read 4, iclass 23, count 0 2006.201.08:33:15.24#ibcon#read 4, iclass 23, count 0 2006.201.08:33:15.24#ibcon#about to read 5, iclass 23, count 0 2006.201.08:33:15.24#ibcon#read 5, iclass 23, count 0 2006.201.08:33:15.24#ibcon#about to read 6, iclass 23, count 0 2006.201.08:33:15.24#ibcon#read 6, iclass 23, count 0 2006.201.08:33:15.24#ibcon#end of sib2, iclass 23, count 0 2006.201.08:33:15.24#ibcon#*after write, iclass 23, count 0 2006.201.08:33:15.24#ibcon#*before return 0, iclass 23, count 0 2006.201.08:33:15.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:15.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:15.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:33:15.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:33:15.24$vck44/valo=5,734.99 2006.201.08:33:15.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.08:33:15.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.08:33:15.24#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:15.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:15.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:15.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:15.24#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:33:15.24#ibcon#first serial, iclass 25, count 0 2006.201.08:33:15.24#ibcon#enter sib2, iclass 25, count 0 2006.201.08:33:15.24#ibcon#flushed, iclass 25, count 0 2006.201.08:33:15.24#ibcon#about to write, iclass 25, count 0 2006.201.08:33:15.24#ibcon#wrote, iclass 25, count 0 2006.201.08:33:15.24#ibcon#about to read 3, iclass 25, count 0 2006.201.08:33:15.26#ibcon#read 3, iclass 25, count 0 2006.201.08:33:15.26#ibcon#about to read 4, iclass 25, count 0 2006.201.08:33:15.26#ibcon#read 4, iclass 25, count 0 2006.201.08:33:15.26#ibcon#about to read 5, iclass 25, count 0 2006.201.08:33:15.26#ibcon#read 5, iclass 25, count 0 2006.201.08:33:15.26#ibcon#about to read 6, iclass 25, count 0 2006.201.08:33:15.26#ibcon#read 6, iclass 25, count 0 2006.201.08:33:15.26#ibcon#end of sib2, iclass 25, count 0 2006.201.08:33:15.26#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:33:15.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:33:15.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:33:15.26#ibcon#*before write, iclass 25, count 0 2006.201.08:33:15.26#ibcon#enter sib2, iclass 25, count 0 2006.201.08:33:15.26#ibcon#flushed, iclass 25, count 0 2006.201.08:33:15.26#ibcon#about to write, iclass 25, count 0 2006.201.08:33:15.26#ibcon#wrote, iclass 25, count 0 2006.201.08:33:15.26#ibcon#about to read 3, iclass 25, count 0 2006.201.08:33:15.30#ibcon#read 3, iclass 25, count 0 2006.201.08:33:15.30#ibcon#about to read 4, iclass 25, count 0 2006.201.08:33:15.30#ibcon#read 4, iclass 25, count 0 2006.201.08:33:15.30#ibcon#about to read 5, iclass 25, count 0 2006.201.08:33:15.30#ibcon#read 5, iclass 25, count 0 2006.201.08:33:15.30#ibcon#about to read 6, iclass 25, count 0 2006.201.08:33:15.30#ibcon#read 6, iclass 25, count 0 2006.201.08:33:15.30#ibcon#end of sib2, iclass 25, count 0 2006.201.08:33:15.30#ibcon#*after write, iclass 25, count 0 2006.201.08:33:15.30#ibcon#*before return 0, iclass 25, count 0 2006.201.08:33:15.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:15.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:15.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:33:15.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:33:15.30$vck44/va=5,4 2006.201.08:33:15.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.08:33:15.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.08:33:15.30#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:15.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:15.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:15.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:15.36#ibcon#enter wrdev, iclass 27, count 2 2006.201.08:33:15.36#ibcon#first serial, iclass 27, count 2 2006.201.08:33:15.36#ibcon#enter sib2, iclass 27, count 2 2006.201.08:33:15.36#ibcon#flushed, iclass 27, count 2 2006.201.08:33:15.36#ibcon#about to write, iclass 27, count 2 2006.201.08:33:15.36#ibcon#wrote, iclass 27, count 2 2006.201.08:33:15.36#ibcon#about to read 3, iclass 27, count 2 2006.201.08:33:15.38#ibcon#read 3, iclass 27, count 2 2006.201.08:33:15.38#ibcon#about to read 4, iclass 27, count 2 2006.201.08:33:15.38#ibcon#read 4, iclass 27, count 2 2006.201.08:33:15.38#ibcon#about to read 5, iclass 27, count 2 2006.201.08:33:15.38#ibcon#read 5, iclass 27, count 2 2006.201.08:33:15.38#ibcon#about to read 6, iclass 27, count 2 2006.201.08:33:15.38#ibcon#read 6, iclass 27, count 2 2006.201.08:33:15.38#ibcon#end of sib2, iclass 27, count 2 2006.201.08:33:15.38#ibcon#*mode == 0, iclass 27, count 2 2006.201.08:33:15.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.08:33:15.38#ibcon#[25=AT05-04\r\n] 2006.201.08:33:15.38#ibcon#*before write, iclass 27, count 2 2006.201.08:33:15.38#ibcon#enter sib2, iclass 27, count 2 2006.201.08:33:15.38#ibcon#flushed, iclass 27, count 2 2006.201.08:33:15.38#ibcon#about to write, iclass 27, count 2 2006.201.08:33:15.38#ibcon#wrote, iclass 27, count 2 2006.201.08:33:15.38#ibcon#about to read 3, iclass 27, count 2 2006.201.08:33:15.41#ibcon#read 3, iclass 27, count 2 2006.201.08:33:15.41#ibcon#about to read 4, iclass 27, count 2 2006.201.08:33:15.41#ibcon#read 4, iclass 27, count 2 2006.201.08:33:15.41#ibcon#about to read 5, iclass 27, count 2 2006.201.08:33:15.41#ibcon#read 5, iclass 27, count 2 2006.201.08:33:15.41#ibcon#about to read 6, iclass 27, count 2 2006.201.08:33:15.41#ibcon#read 6, iclass 27, count 2 2006.201.08:33:15.41#ibcon#end of sib2, iclass 27, count 2 2006.201.08:33:15.41#ibcon#*after write, iclass 27, count 2 2006.201.08:33:15.41#ibcon#*before return 0, iclass 27, count 2 2006.201.08:33:15.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:15.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:15.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.08:33:15.41#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:15.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:15.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:15.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:15.53#ibcon#enter wrdev, iclass 27, count 0 2006.201.08:33:15.53#ibcon#first serial, iclass 27, count 0 2006.201.08:33:15.53#ibcon#enter sib2, iclass 27, count 0 2006.201.08:33:15.53#ibcon#flushed, iclass 27, count 0 2006.201.08:33:15.53#ibcon#about to write, iclass 27, count 0 2006.201.08:33:15.53#ibcon#wrote, iclass 27, count 0 2006.201.08:33:15.53#ibcon#about to read 3, iclass 27, count 0 2006.201.08:33:15.55#ibcon#read 3, iclass 27, count 0 2006.201.08:33:15.55#ibcon#about to read 4, iclass 27, count 0 2006.201.08:33:15.55#ibcon#read 4, iclass 27, count 0 2006.201.08:33:15.55#ibcon#about to read 5, iclass 27, count 0 2006.201.08:33:15.55#ibcon#read 5, iclass 27, count 0 2006.201.08:33:15.55#ibcon#about to read 6, iclass 27, count 0 2006.201.08:33:15.55#ibcon#read 6, iclass 27, count 0 2006.201.08:33:15.55#ibcon#end of sib2, iclass 27, count 0 2006.201.08:33:15.55#ibcon#*mode == 0, iclass 27, count 0 2006.201.08:33:15.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.08:33:15.55#ibcon#[25=USB\r\n] 2006.201.08:33:15.55#ibcon#*before write, iclass 27, count 0 2006.201.08:33:15.55#ibcon#enter sib2, iclass 27, count 0 2006.201.08:33:15.55#ibcon#flushed, iclass 27, count 0 2006.201.08:33:15.55#ibcon#about to write, iclass 27, count 0 2006.201.08:33:15.55#ibcon#wrote, iclass 27, count 0 2006.201.08:33:15.55#ibcon#about to read 3, iclass 27, count 0 2006.201.08:33:15.58#ibcon#read 3, iclass 27, count 0 2006.201.08:33:15.58#ibcon#about to read 4, iclass 27, count 0 2006.201.08:33:15.58#ibcon#read 4, iclass 27, count 0 2006.201.08:33:15.58#ibcon#about to read 5, iclass 27, count 0 2006.201.08:33:15.58#ibcon#read 5, iclass 27, count 0 2006.201.08:33:15.58#ibcon#about to read 6, iclass 27, count 0 2006.201.08:33:15.58#ibcon#read 6, iclass 27, count 0 2006.201.08:33:15.58#ibcon#end of sib2, iclass 27, count 0 2006.201.08:33:15.58#ibcon#*after write, iclass 27, count 0 2006.201.08:33:15.58#ibcon#*before return 0, iclass 27, count 0 2006.201.08:33:15.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:15.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:15.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.08:33:15.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.08:33:15.58$vck44/valo=6,814.99 2006.201.08:33:15.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.08:33:15.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.08:33:15.58#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:15.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:15.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:15.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:15.58#ibcon#enter wrdev, iclass 29, count 0 2006.201.08:33:15.58#ibcon#first serial, iclass 29, count 0 2006.201.08:33:15.58#ibcon#enter sib2, iclass 29, count 0 2006.201.08:33:15.58#ibcon#flushed, iclass 29, count 0 2006.201.08:33:15.58#ibcon#about to write, iclass 29, count 0 2006.201.08:33:15.58#ibcon#wrote, iclass 29, count 0 2006.201.08:33:15.58#ibcon#about to read 3, iclass 29, count 0 2006.201.08:33:15.60#ibcon#read 3, iclass 29, count 0 2006.201.08:33:15.60#ibcon#about to read 4, iclass 29, count 0 2006.201.08:33:15.60#ibcon#read 4, iclass 29, count 0 2006.201.08:33:15.60#ibcon#about to read 5, iclass 29, count 0 2006.201.08:33:15.60#ibcon#read 5, iclass 29, count 0 2006.201.08:33:15.60#ibcon#about to read 6, iclass 29, count 0 2006.201.08:33:15.60#ibcon#read 6, iclass 29, count 0 2006.201.08:33:15.60#ibcon#end of sib2, iclass 29, count 0 2006.201.08:33:15.60#ibcon#*mode == 0, iclass 29, count 0 2006.201.08:33:15.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.08:33:15.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:33:15.60#ibcon#*before write, iclass 29, count 0 2006.201.08:33:15.60#ibcon#enter sib2, iclass 29, count 0 2006.201.08:33:15.60#ibcon#flushed, iclass 29, count 0 2006.201.08:33:15.60#ibcon#about to write, iclass 29, count 0 2006.201.08:33:15.60#ibcon#wrote, iclass 29, count 0 2006.201.08:33:15.60#ibcon#about to read 3, iclass 29, count 0 2006.201.08:33:15.65#ibcon#read 3, iclass 29, count 0 2006.201.08:33:15.65#ibcon#about to read 4, iclass 29, count 0 2006.201.08:33:15.65#ibcon#read 4, iclass 29, count 0 2006.201.08:33:15.65#ibcon#about to read 5, iclass 29, count 0 2006.201.08:33:15.65#ibcon#read 5, iclass 29, count 0 2006.201.08:33:15.65#ibcon#about to read 6, iclass 29, count 0 2006.201.08:33:15.65#ibcon#read 6, iclass 29, count 0 2006.201.08:33:15.65#ibcon#end of sib2, iclass 29, count 0 2006.201.08:33:15.65#ibcon#*after write, iclass 29, count 0 2006.201.08:33:15.65#ibcon#*before return 0, iclass 29, count 0 2006.201.08:33:15.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:15.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:15.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.08:33:15.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.08:33:15.65$vck44/va=6,5 2006.201.08:33:15.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.08:33:15.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.08:33:15.65#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:15.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:15.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:15.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:15.70#ibcon#enter wrdev, iclass 31, count 2 2006.201.08:33:15.70#ibcon#first serial, iclass 31, count 2 2006.201.08:33:15.70#ibcon#enter sib2, iclass 31, count 2 2006.201.08:33:15.70#ibcon#flushed, iclass 31, count 2 2006.201.08:33:15.70#ibcon#about to write, iclass 31, count 2 2006.201.08:33:15.70#ibcon#wrote, iclass 31, count 2 2006.201.08:33:15.70#ibcon#about to read 3, iclass 31, count 2 2006.201.08:33:15.72#ibcon#read 3, iclass 31, count 2 2006.201.08:33:15.72#ibcon#about to read 4, iclass 31, count 2 2006.201.08:33:15.72#ibcon#read 4, iclass 31, count 2 2006.201.08:33:15.72#ibcon#about to read 5, iclass 31, count 2 2006.201.08:33:15.72#ibcon#read 5, iclass 31, count 2 2006.201.08:33:15.72#ibcon#about to read 6, iclass 31, count 2 2006.201.08:33:15.72#ibcon#read 6, iclass 31, count 2 2006.201.08:33:15.72#ibcon#end of sib2, iclass 31, count 2 2006.201.08:33:15.72#ibcon#*mode == 0, iclass 31, count 2 2006.201.08:33:15.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.08:33:15.72#ibcon#[25=AT06-05\r\n] 2006.201.08:33:15.72#ibcon#*before write, iclass 31, count 2 2006.201.08:33:15.72#ibcon#enter sib2, iclass 31, count 2 2006.201.08:33:15.72#ibcon#flushed, iclass 31, count 2 2006.201.08:33:15.72#ibcon#about to write, iclass 31, count 2 2006.201.08:33:15.72#ibcon#wrote, iclass 31, count 2 2006.201.08:33:15.72#ibcon#about to read 3, iclass 31, count 2 2006.201.08:33:15.75#ibcon#read 3, iclass 31, count 2 2006.201.08:33:15.75#ibcon#about to read 4, iclass 31, count 2 2006.201.08:33:15.75#ibcon#read 4, iclass 31, count 2 2006.201.08:33:15.75#ibcon#about to read 5, iclass 31, count 2 2006.201.08:33:15.75#ibcon#read 5, iclass 31, count 2 2006.201.08:33:15.75#ibcon#about to read 6, iclass 31, count 2 2006.201.08:33:15.75#ibcon#read 6, iclass 31, count 2 2006.201.08:33:15.75#ibcon#end of sib2, iclass 31, count 2 2006.201.08:33:15.75#ibcon#*after write, iclass 31, count 2 2006.201.08:33:15.75#ibcon#*before return 0, iclass 31, count 2 2006.201.08:33:15.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:15.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:15.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.08:33:15.75#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:15.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:15.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:15.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:15.87#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:33:15.87#ibcon#first serial, iclass 31, count 0 2006.201.08:33:15.87#ibcon#enter sib2, iclass 31, count 0 2006.201.08:33:15.87#ibcon#flushed, iclass 31, count 0 2006.201.08:33:15.87#ibcon#about to write, iclass 31, count 0 2006.201.08:33:15.87#ibcon#wrote, iclass 31, count 0 2006.201.08:33:15.87#ibcon#about to read 3, iclass 31, count 0 2006.201.08:33:15.89#ibcon#read 3, iclass 31, count 0 2006.201.08:33:15.89#ibcon#about to read 4, iclass 31, count 0 2006.201.08:33:15.89#ibcon#read 4, iclass 31, count 0 2006.201.08:33:15.89#ibcon#about to read 5, iclass 31, count 0 2006.201.08:33:15.89#ibcon#read 5, iclass 31, count 0 2006.201.08:33:15.89#ibcon#about to read 6, iclass 31, count 0 2006.201.08:33:15.89#ibcon#read 6, iclass 31, count 0 2006.201.08:33:15.89#ibcon#end of sib2, iclass 31, count 0 2006.201.08:33:15.89#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:33:15.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:33:15.89#ibcon#[25=USB\r\n] 2006.201.08:33:15.89#ibcon#*before write, iclass 31, count 0 2006.201.08:33:15.89#ibcon#enter sib2, iclass 31, count 0 2006.201.08:33:15.89#ibcon#flushed, iclass 31, count 0 2006.201.08:33:15.89#ibcon#about to write, iclass 31, count 0 2006.201.08:33:15.89#ibcon#wrote, iclass 31, count 0 2006.201.08:33:15.89#ibcon#about to read 3, iclass 31, count 0 2006.201.08:33:15.92#ibcon#read 3, iclass 31, count 0 2006.201.08:33:15.92#ibcon#about to read 4, iclass 31, count 0 2006.201.08:33:15.92#ibcon#read 4, iclass 31, count 0 2006.201.08:33:15.92#ibcon#about to read 5, iclass 31, count 0 2006.201.08:33:15.92#ibcon#read 5, iclass 31, count 0 2006.201.08:33:15.92#ibcon#about to read 6, iclass 31, count 0 2006.201.08:33:15.92#ibcon#read 6, iclass 31, count 0 2006.201.08:33:15.92#ibcon#end of sib2, iclass 31, count 0 2006.201.08:33:15.92#ibcon#*after write, iclass 31, count 0 2006.201.08:33:15.92#ibcon#*before return 0, iclass 31, count 0 2006.201.08:33:15.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:15.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:15.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:33:15.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:33:15.92$vck44/valo=7,864.99 2006.201.08:33:15.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.08:33:15.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.08:33:15.92#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:15.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:15.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:15.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:15.92#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:33:15.92#ibcon#first serial, iclass 33, count 0 2006.201.08:33:15.92#ibcon#enter sib2, iclass 33, count 0 2006.201.08:33:15.92#ibcon#flushed, iclass 33, count 0 2006.201.08:33:15.92#ibcon#about to write, iclass 33, count 0 2006.201.08:33:15.92#ibcon#wrote, iclass 33, count 0 2006.201.08:33:15.92#ibcon#about to read 3, iclass 33, count 0 2006.201.08:33:15.94#ibcon#read 3, iclass 33, count 0 2006.201.08:33:15.94#ibcon#about to read 4, iclass 33, count 0 2006.201.08:33:15.94#ibcon#read 4, iclass 33, count 0 2006.201.08:33:15.94#ibcon#about to read 5, iclass 33, count 0 2006.201.08:33:15.94#ibcon#read 5, iclass 33, count 0 2006.201.08:33:15.94#ibcon#about to read 6, iclass 33, count 0 2006.201.08:33:15.94#ibcon#read 6, iclass 33, count 0 2006.201.08:33:15.94#ibcon#end of sib2, iclass 33, count 0 2006.201.08:33:15.94#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:33:15.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:33:15.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:33:15.94#ibcon#*before write, iclass 33, count 0 2006.201.08:33:15.94#ibcon#enter sib2, iclass 33, count 0 2006.201.08:33:15.94#ibcon#flushed, iclass 33, count 0 2006.201.08:33:15.94#ibcon#about to write, iclass 33, count 0 2006.201.08:33:15.94#ibcon#wrote, iclass 33, count 0 2006.201.08:33:15.94#ibcon#about to read 3, iclass 33, count 0 2006.201.08:33:15.98#ibcon#read 3, iclass 33, count 0 2006.201.08:33:15.98#ibcon#about to read 4, iclass 33, count 0 2006.201.08:33:15.98#ibcon#read 4, iclass 33, count 0 2006.201.08:33:15.98#ibcon#about to read 5, iclass 33, count 0 2006.201.08:33:15.98#ibcon#read 5, iclass 33, count 0 2006.201.08:33:15.98#ibcon#about to read 6, iclass 33, count 0 2006.201.08:33:15.98#ibcon#read 6, iclass 33, count 0 2006.201.08:33:15.98#ibcon#end of sib2, iclass 33, count 0 2006.201.08:33:15.98#ibcon#*after write, iclass 33, count 0 2006.201.08:33:15.98#ibcon#*before return 0, iclass 33, count 0 2006.201.08:33:15.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:15.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:15.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:33:15.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:33:15.98$vck44/va=7,5 2006.201.08:33:15.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.08:33:15.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.08:33:15.98#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:15.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:16.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:16.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:16.04#ibcon#enter wrdev, iclass 35, count 2 2006.201.08:33:16.04#ibcon#first serial, iclass 35, count 2 2006.201.08:33:16.04#ibcon#enter sib2, iclass 35, count 2 2006.201.08:33:16.04#ibcon#flushed, iclass 35, count 2 2006.201.08:33:16.04#ibcon#about to write, iclass 35, count 2 2006.201.08:33:16.04#ibcon#wrote, iclass 35, count 2 2006.201.08:33:16.04#ibcon#about to read 3, iclass 35, count 2 2006.201.08:33:16.06#ibcon#read 3, iclass 35, count 2 2006.201.08:33:16.06#ibcon#about to read 4, iclass 35, count 2 2006.201.08:33:16.06#ibcon#read 4, iclass 35, count 2 2006.201.08:33:16.06#ibcon#about to read 5, iclass 35, count 2 2006.201.08:33:16.06#ibcon#read 5, iclass 35, count 2 2006.201.08:33:16.06#ibcon#about to read 6, iclass 35, count 2 2006.201.08:33:16.06#ibcon#read 6, iclass 35, count 2 2006.201.08:33:16.06#ibcon#end of sib2, iclass 35, count 2 2006.201.08:33:16.06#ibcon#*mode == 0, iclass 35, count 2 2006.201.08:33:16.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.08:33:16.06#ibcon#[25=AT07-05\r\n] 2006.201.08:33:16.06#ibcon#*before write, iclass 35, count 2 2006.201.08:33:16.06#ibcon#enter sib2, iclass 35, count 2 2006.201.08:33:16.06#ibcon#flushed, iclass 35, count 2 2006.201.08:33:16.06#ibcon#about to write, iclass 35, count 2 2006.201.08:33:16.06#ibcon#wrote, iclass 35, count 2 2006.201.08:33:16.06#ibcon#about to read 3, iclass 35, count 2 2006.201.08:33:16.09#ibcon#read 3, iclass 35, count 2 2006.201.08:33:16.09#ibcon#about to read 4, iclass 35, count 2 2006.201.08:33:16.09#ibcon#read 4, iclass 35, count 2 2006.201.08:33:16.09#ibcon#about to read 5, iclass 35, count 2 2006.201.08:33:16.09#ibcon#read 5, iclass 35, count 2 2006.201.08:33:16.09#ibcon#about to read 6, iclass 35, count 2 2006.201.08:33:16.09#ibcon#read 6, iclass 35, count 2 2006.201.08:33:16.09#ibcon#end of sib2, iclass 35, count 2 2006.201.08:33:16.09#ibcon#*after write, iclass 35, count 2 2006.201.08:33:16.09#ibcon#*before return 0, iclass 35, count 2 2006.201.08:33:16.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:16.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:16.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.08:33:16.09#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:16.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:16.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:16.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:16.21#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:33:16.21#ibcon#first serial, iclass 35, count 0 2006.201.08:33:16.21#ibcon#enter sib2, iclass 35, count 0 2006.201.08:33:16.21#ibcon#flushed, iclass 35, count 0 2006.201.08:33:16.21#ibcon#about to write, iclass 35, count 0 2006.201.08:33:16.21#ibcon#wrote, iclass 35, count 0 2006.201.08:33:16.21#ibcon#about to read 3, iclass 35, count 0 2006.201.08:33:16.23#ibcon#read 3, iclass 35, count 0 2006.201.08:33:16.23#ibcon#about to read 4, iclass 35, count 0 2006.201.08:33:16.23#ibcon#read 4, iclass 35, count 0 2006.201.08:33:16.23#ibcon#about to read 5, iclass 35, count 0 2006.201.08:33:16.23#ibcon#read 5, iclass 35, count 0 2006.201.08:33:16.23#ibcon#about to read 6, iclass 35, count 0 2006.201.08:33:16.23#ibcon#read 6, iclass 35, count 0 2006.201.08:33:16.23#ibcon#end of sib2, iclass 35, count 0 2006.201.08:33:16.23#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:33:16.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:33:16.23#ibcon#[25=USB\r\n] 2006.201.08:33:16.23#ibcon#*before write, iclass 35, count 0 2006.201.08:33:16.23#ibcon#enter sib2, iclass 35, count 0 2006.201.08:33:16.23#ibcon#flushed, iclass 35, count 0 2006.201.08:33:16.23#ibcon#about to write, iclass 35, count 0 2006.201.08:33:16.23#ibcon#wrote, iclass 35, count 0 2006.201.08:33:16.23#ibcon#about to read 3, iclass 35, count 0 2006.201.08:33:16.26#ibcon#read 3, iclass 35, count 0 2006.201.08:33:16.26#ibcon#about to read 4, iclass 35, count 0 2006.201.08:33:16.26#ibcon#read 4, iclass 35, count 0 2006.201.08:33:16.26#ibcon#about to read 5, iclass 35, count 0 2006.201.08:33:16.26#ibcon#read 5, iclass 35, count 0 2006.201.08:33:16.26#ibcon#about to read 6, iclass 35, count 0 2006.201.08:33:16.26#ibcon#read 6, iclass 35, count 0 2006.201.08:33:16.26#ibcon#end of sib2, iclass 35, count 0 2006.201.08:33:16.26#ibcon#*after write, iclass 35, count 0 2006.201.08:33:16.26#ibcon#*before return 0, iclass 35, count 0 2006.201.08:33:16.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:16.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:16.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:33:16.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:33:16.26$vck44/valo=8,884.99 2006.201.08:33:16.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.08:33:16.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.08:33:16.26#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:16.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:16.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:16.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:16.26#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:33:16.26#ibcon#first serial, iclass 37, count 0 2006.201.08:33:16.26#ibcon#enter sib2, iclass 37, count 0 2006.201.08:33:16.26#ibcon#flushed, iclass 37, count 0 2006.201.08:33:16.26#ibcon#about to write, iclass 37, count 0 2006.201.08:33:16.26#ibcon#wrote, iclass 37, count 0 2006.201.08:33:16.26#ibcon#about to read 3, iclass 37, count 0 2006.201.08:33:16.28#ibcon#read 3, iclass 37, count 0 2006.201.08:33:16.28#ibcon#about to read 4, iclass 37, count 0 2006.201.08:33:16.28#ibcon#read 4, iclass 37, count 0 2006.201.08:33:16.28#ibcon#about to read 5, iclass 37, count 0 2006.201.08:33:16.28#ibcon#read 5, iclass 37, count 0 2006.201.08:33:16.28#ibcon#about to read 6, iclass 37, count 0 2006.201.08:33:16.28#ibcon#read 6, iclass 37, count 0 2006.201.08:33:16.28#ibcon#end of sib2, iclass 37, count 0 2006.201.08:33:16.28#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:33:16.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:33:16.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:33:16.28#ibcon#*before write, iclass 37, count 0 2006.201.08:33:16.28#ibcon#enter sib2, iclass 37, count 0 2006.201.08:33:16.28#ibcon#flushed, iclass 37, count 0 2006.201.08:33:16.28#ibcon#about to write, iclass 37, count 0 2006.201.08:33:16.28#ibcon#wrote, iclass 37, count 0 2006.201.08:33:16.28#ibcon#about to read 3, iclass 37, count 0 2006.201.08:33:16.32#ibcon#read 3, iclass 37, count 0 2006.201.08:33:16.32#ibcon#about to read 4, iclass 37, count 0 2006.201.08:33:16.32#ibcon#read 4, iclass 37, count 0 2006.201.08:33:16.32#ibcon#about to read 5, iclass 37, count 0 2006.201.08:33:16.32#ibcon#read 5, iclass 37, count 0 2006.201.08:33:16.32#ibcon#about to read 6, iclass 37, count 0 2006.201.08:33:16.32#ibcon#read 6, iclass 37, count 0 2006.201.08:33:16.32#ibcon#end of sib2, iclass 37, count 0 2006.201.08:33:16.32#ibcon#*after write, iclass 37, count 0 2006.201.08:33:16.32#ibcon#*before return 0, iclass 37, count 0 2006.201.08:33:16.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:16.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:16.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:33:16.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:33:16.32$vck44/va=8,4 2006.201.08:33:16.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.08:33:16.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.08:33:16.32#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:16.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:33:16.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:33:16.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:33:16.38#ibcon#enter wrdev, iclass 39, count 2 2006.201.08:33:16.38#ibcon#first serial, iclass 39, count 2 2006.201.08:33:16.38#ibcon#enter sib2, iclass 39, count 2 2006.201.08:33:16.38#ibcon#flushed, iclass 39, count 2 2006.201.08:33:16.38#ibcon#about to write, iclass 39, count 2 2006.201.08:33:16.38#ibcon#wrote, iclass 39, count 2 2006.201.08:33:16.38#ibcon#about to read 3, iclass 39, count 2 2006.201.08:33:16.40#ibcon#read 3, iclass 39, count 2 2006.201.08:33:16.40#ibcon#about to read 4, iclass 39, count 2 2006.201.08:33:16.40#ibcon#read 4, iclass 39, count 2 2006.201.08:33:16.40#ibcon#about to read 5, iclass 39, count 2 2006.201.08:33:16.40#ibcon#read 5, iclass 39, count 2 2006.201.08:33:16.40#ibcon#about to read 6, iclass 39, count 2 2006.201.08:33:16.40#ibcon#read 6, iclass 39, count 2 2006.201.08:33:16.40#ibcon#end of sib2, iclass 39, count 2 2006.201.08:33:16.40#ibcon#*mode == 0, iclass 39, count 2 2006.201.08:33:16.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.08:33:16.40#ibcon#[25=AT08-04\r\n] 2006.201.08:33:16.40#ibcon#*before write, iclass 39, count 2 2006.201.08:33:16.40#ibcon#enter sib2, iclass 39, count 2 2006.201.08:33:16.40#ibcon#flushed, iclass 39, count 2 2006.201.08:33:16.40#ibcon#about to write, iclass 39, count 2 2006.201.08:33:16.40#ibcon#wrote, iclass 39, count 2 2006.201.08:33:16.40#ibcon#about to read 3, iclass 39, count 2 2006.201.08:33:16.43#ibcon#read 3, iclass 39, count 2 2006.201.08:33:16.43#ibcon#about to read 4, iclass 39, count 2 2006.201.08:33:16.43#ibcon#read 4, iclass 39, count 2 2006.201.08:33:16.43#ibcon#about to read 5, iclass 39, count 2 2006.201.08:33:16.43#ibcon#read 5, iclass 39, count 2 2006.201.08:33:16.43#ibcon#about to read 6, iclass 39, count 2 2006.201.08:33:16.43#ibcon#read 6, iclass 39, count 2 2006.201.08:33:16.43#ibcon#end of sib2, iclass 39, count 2 2006.201.08:33:16.43#ibcon#*after write, iclass 39, count 2 2006.201.08:33:16.43#ibcon#*before return 0, iclass 39, count 2 2006.201.08:33:16.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:33:16.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:33:16.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.08:33:16.43#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:16.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:33:16.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:33:16.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:33:16.55#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:33:16.55#ibcon#first serial, iclass 39, count 0 2006.201.08:33:16.55#ibcon#enter sib2, iclass 39, count 0 2006.201.08:33:16.55#ibcon#flushed, iclass 39, count 0 2006.201.08:33:16.55#ibcon#about to write, iclass 39, count 0 2006.201.08:33:16.55#ibcon#wrote, iclass 39, count 0 2006.201.08:33:16.55#ibcon#about to read 3, iclass 39, count 0 2006.201.08:33:16.57#ibcon#read 3, iclass 39, count 0 2006.201.08:33:16.57#ibcon#about to read 4, iclass 39, count 0 2006.201.08:33:16.57#ibcon#read 4, iclass 39, count 0 2006.201.08:33:16.57#ibcon#about to read 5, iclass 39, count 0 2006.201.08:33:16.57#ibcon#read 5, iclass 39, count 0 2006.201.08:33:16.57#ibcon#about to read 6, iclass 39, count 0 2006.201.08:33:16.57#ibcon#read 6, iclass 39, count 0 2006.201.08:33:16.57#ibcon#end of sib2, iclass 39, count 0 2006.201.08:33:16.57#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:33:16.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:33:16.57#ibcon#[25=USB\r\n] 2006.201.08:33:16.57#ibcon#*before write, iclass 39, count 0 2006.201.08:33:16.57#ibcon#enter sib2, iclass 39, count 0 2006.201.08:33:16.57#ibcon#flushed, iclass 39, count 0 2006.201.08:33:16.57#ibcon#about to write, iclass 39, count 0 2006.201.08:33:16.57#ibcon#wrote, iclass 39, count 0 2006.201.08:33:16.57#ibcon#about to read 3, iclass 39, count 0 2006.201.08:33:16.60#ibcon#read 3, iclass 39, count 0 2006.201.08:33:16.60#ibcon#about to read 4, iclass 39, count 0 2006.201.08:33:16.60#ibcon#read 4, iclass 39, count 0 2006.201.08:33:16.60#ibcon#about to read 5, iclass 39, count 0 2006.201.08:33:16.60#ibcon#read 5, iclass 39, count 0 2006.201.08:33:16.60#ibcon#about to read 6, iclass 39, count 0 2006.201.08:33:16.60#ibcon#read 6, iclass 39, count 0 2006.201.08:33:16.60#ibcon#end of sib2, iclass 39, count 0 2006.201.08:33:16.60#ibcon#*after write, iclass 39, count 0 2006.201.08:33:16.60#ibcon#*before return 0, iclass 39, count 0 2006.201.08:33:16.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:33:16.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:33:16.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:33:16.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:33:16.60$vck44/vblo=1,629.99 2006.201.08:33:16.60#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.08:33:16.60#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.08:33:16.60#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:16.60#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:33:16.60#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:33:16.60#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:33:16.60#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:33:16.60#ibcon#first serial, iclass 2, count 0 2006.201.08:33:16.60#ibcon#enter sib2, iclass 2, count 0 2006.201.08:33:16.60#ibcon#flushed, iclass 2, count 0 2006.201.08:33:16.60#ibcon#about to write, iclass 2, count 0 2006.201.08:33:16.60#ibcon#wrote, iclass 2, count 0 2006.201.08:33:16.60#ibcon#about to read 3, iclass 2, count 0 2006.201.08:33:16.62#ibcon#read 3, iclass 2, count 0 2006.201.08:33:16.62#ibcon#about to read 4, iclass 2, count 0 2006.201.08:33:16.62#ibcon#read 4, iclass 2, count 0 2006.201.08:33:16.62#ibcon#about to read 5, iclass 2, count 0 2006.201.08:33:16.62#ibcon#read 5, iclass 2, count 0 2006.201.08:33:16.62#ibcon#about to read 6, iclass 2, count 0 2006.201.08:33:16.62#ibcon#read 6, iclass 2, count 0 2006.201.08:33:16.62#ibcon#end of sib2, iclass 2, count 0 2006.201.08:33:16.62#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:33:16.62#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:33:16.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:33:16.62#ibcon#*before write, iclass 2, count 0 2006.201.08:33:16.62#ibcon#enter sib2, iclass 2, count 0 2006.201.08:33:16.62#ibcon#flushed, iclass 2, count 0 2006.201.08:33:16.62#ibcon#about to write, iclass 2, count 0 2006.201.08:33:16.62#ibcon#wrote, iclass 2, count 0 2006.201.08:33:16.62#ibcon#about to read 3, iclass 2, count 0 2006.201.08:33:16.66#ibcon#read 3, iclass 2, count 0 2006.201.08:33:16.66#ibcon#about to read 4, iclass 2, count 0 2006.201.08:33:16.66#ibcon#read 4, iclass 2, count 0 2006.201.08:33:16.66#ibcon#about to read 5, iclass 2, count 0 2006.201.08:33:16.66#ibcon#read 5, iclass 2, count 0 2006.201.08:33:16.66#ibcon#about to read 6, iclass 2, count 0 2006.201.08:33:16.66#ibcon#read 6, iclass 2, count 0 2006.201.08:33:16.66#ibcon#end of sib2, iclass 2, count 0 2006.201.08:33:16.66#ibcon#*after write, iclass 2, count 0 2006.201.08:33:16.66#ibcon#*before return 0, iclass 2, count 0 2006.201.08:33:16.66#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:33:16.66#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:33:16.66#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:33:16.66#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:33:16.66$vck44/vb=1,4 2006.201.08:33:16.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.08:33:16.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.08:33:16.66#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:16.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:33:16.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:33:16.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:33:16.66#ibcon#enter wrdev, iclass 5, count 2 2006.201.08:33:16.66#ibcon#first serial, iclass 5, count 2 2006.201.08:33:16.66#ibcon#enter sib2, iclass 5, count 2 2006.201.08:33:16.66#ibcon#flushed, iclass 5, count 2 2006.201.08:33:16.66#ibcon#about to write, iclass 5, count 2 2006.201.08:33:16.66#ibcon#wrote, iclass 5, count 2 2006.201.08:33:16.66#ibcon#about to read 3, iclass 5, count 2 2006.201.08:33:16.68#ibcon#read 3, iclass 5, count 2 2006.201.08:33:16.68#ibcon#about to read 4, iclass 5, count 2 2006.201.08:33:16.68#ibcon#read 4, iclass 5, count 2 2006.201.08:33:16.68#ibcon#about to read 5, iclass 5, count 2 2006.201.08:33:16.68#ibcon#read 5, iclass 5, count 2 2006.201.08:33:16.68#ibcon#about to read 6, iclass 5, count 2 2006.201.08:33:16.68#ibcon#read 6, iclass 5, count 2 2006.201.08:33:16.68#ibcon#end of sib2, iclass 5, count 2 2006.201.08:33:16.68#ibcon#*mode == 0, iclass 5, count 2 2006.201.08:33:16.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.08:33:16.68#ibcon#[27=AT01-04\r\n] 2006.201.08:33:16.68#ibcon#*before write, iclass 5, count 2 2006.201.08:33:16.68#ibcon#enter sib2, iclass 5, count 2 2006.201.08:33:16.68#ibcon#flushed, iclass 5, count 2 2006.201.08:33:16.68#ibcon#about to write, iclass 5, count 2 2006.201.08:33:16.68#ibcon#wrote, iclass 5, count 2 2006.201.08:33:16.68#ibcon#about to read 3, iclass 5, count 2 2006.201.08:33:16.71#ibcon#read 3, iclass 5, count 2 2006.201.08:33:16.71#ibcon#about to read 4, iclass 5, count 2 2006.201.08:33:16.71#ibcon#read 4, iclass 5, count 2 2006.201.08:33:16.71#ibcon#about to read 5, iclass 5, count 2 2006.201.08:33:16.71#ibcon#read 5, iclass 5, count 2 2006.201.08:33:16.71#ibcon#about to read 6, iclass 5, count 2 2006.201.08:33:16.71#ibcon#read 6, iclass 5, count 2 2006.201.08:33:16.71#ibcon#end of sib2, iclass 5, count 2 2006.201.08:33:16.71#ibcon#*after write, iclass 5, count 2 2006.201.08:33:16.71#ibcon#*before return 0, iclass 5, count 2 2006.201.08:33:16.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:33:16.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:33:16.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.08:33:16.71#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:16.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:33:16.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:33:16.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:33:16.83#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:33:16.83#ibcon#first serial, iclass 5, count 0 2006.201.08:33:16.83#ibcon#enter sib2, iclass 5, count 0 2006.201.08:33:16.83#ibcon#flushed, iclass 5, count 0 2006.201.08:33:16.83#ibcon#about to write, iclass 5, count 0 2006.201.08:33:16.83#ibcon#wrote, iclass 5, count 0 2006.201.08:33:16.83#ibcon#about to read 3, iclass 5, count 0 2006.201.08:33:16.85#ibcon#read 3, iclass 5, count 0 2006.201.08:33:16.85#ibcon#about to read 4, iclass 5, count 0 2006.201.08:33:16.85#ibcon#read 4, iclass 5, count 0 2006.201.08:33:16.85#ibcon#about to read 5, iclass 5, count 0 2006.201.08:33:16.85#ibcon#read 5, iclass 5, count 0 2006.201.08:33:16.85#ibcon#about to read 6, iclass 5, count 0 2006.201.08:33:16.85#ibcon#read 6, iclass 5, count 0 2006.201.08:33:16.85#ibcon#end of sib2, iclass 5, count 0 2006.201.08:33:16.85#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:33:16.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:33:16.85#ibcon#[27=USB\r\n] 2006.201.08:33:16.85#ibcon#*before write, iclass 5, count 0 2006.201.08:33:16.85#ibcon#enter sib2, iclass 5, count 0 2006.201.08:33:16.85#ibcon#flushed, iclass 5, count 0 2006.201.08:33:16.85#ibcon#about to write, iclass 5, count 0 2006.201.08:33:16.85#ibcon#wrote, iclass 5, count 0 2006.201.08:33:16.85#ibcon#about to read 3, iclass 5, count 0 2006.201.08:33:16.88#ibcon#read 3, iclass 5, count 0 2006.201.08:33:16.88#ibcon#about to read 4, iclass 5, count 0 2006.201.08:33:16.88#ibcon#read 4, iclass 5, count 0 2006.201.08:33:16.88#ibcon#about to read 5, iclass 5, count 0 2006.201.08:33:16.88#ibcon#read 5, iclass 5, count 0 2006.201.08:33:16.88#ibcon#about to read 6, iclass 5, count 0 2006.201.08:33:16.88#ibcon#read 6, iclass 5, count 0 2006.201.08:33:16.88#ibcon#end of sib2, iclass 5, count 0 2006.201.08:33:16.88#ibcon#*after write, iclass 5, count 0 2006.201.08:33:16.88#ibcon#*before return 0, iclass 5, count 0 2006.201.08:33:16.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:33:16.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:33:16.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:33:16.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:33:16.88$vck44/vblo=2,634.99 2006.201.08:33:16.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.08:33:16.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.08:33:16.88#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:16.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:33:16.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:33:16.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:33:16.88#ibcon#enter wrdev, iclass 7, count 0 2006.201.08:33:16.88#ibcon#first serial, iclass 7, count 0 2006.201.08:33:16.88#ibcon#enter sib2, iclass 7, count 0 2006.201.08:33:16.88#ibcon#flushed, iclass 7, count 0 2006.201.08:33:16.88#ibcon#about to write, iclass 7, count 0 2006.201.08:33:16.88#ibcon#wrote, iclass 7, count 0 2006.201.08:33:16.88#ibcon#about to read 3, iclass 7, count 0 2006.201.08:33:16.90#ibcon#read 3, iclass 7, count 0 2006.201.08:33:16.90#ibcon#about to read 4, iclass 7, count 0 2006.201.08:33:16.90#ibcon#read 4, iclass 7, count 0 2006.201.08:33:16.90#ibcon#about to read 5, iclass 7, count 0 2006.201.08:33:16.90#ibcon#read 5, iclass 7, count 0 2006.201.08:33:16.90#ibcon#about to read 6, iclass 7, count 0 2006.201.08:33:16.90#ibcon#read 6, iclass 7, count 0 2006.201.08:33:16.90#ibcon#end of sib2, iclass 7, count 0 2006.201.08:33:16.90#ibcon#*mode == 0, iclass 7, count 0 2006.201.08:33:16.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.08:33:16.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:33:16.90#ibcon#*before write, iclass 7, count 0 2006.201.08:33:16.90#ibcon#enter sib2, iclass 7, count 0 2006.201.08:33:16.90#ibcon#flushed, iclass 7, count 0 2006.201.08:33:16.90#ibcon#about to write, iclass 7, count 0 2006.201.08:33:16.90#ibcon#wrote, iclass 7, count 0 2006.201.08:33:16.90#ibcon#about to read 3, iclass 7, count 0 2006.201.08:33:16.94#ibcon#read 3, iclass 7, count 0 2006.201.08:33:16.94#ibcon#about to read 4, iclass 7, count 0 2006.201.08:33:16.94#ibcon#read 4, iclass 7, count 0 2006.201.08:33:16.94#ibcon#about to read 5, iclass 7, count 0 2006.201.08:33:16.94#ibcon#read 5, iclass 7, count 0 2006.201.08:33:16.94#ibcon#about to read 6, iclass 7, count 0 2006.201.08:33:16.94#ibcon#read 6, iclass 7, count 0 2006.201.08:33:16.94#ibcon#end of sib2, iclass 7, count 0 2006.201.08:33:16.94#ibcon#*after write, iclass 7, count 0 2006.201.08:33:16.94#ibcon#*before return 0, iclass 7, count 0 2006.201.08:33:16.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:33:16.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:33:16.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.08:33:16.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.08:33:16.94$vck44/vb=2,5 2006.201.08:33:16.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.08:33:16.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.08:33:16.94#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:16.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:17.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:17.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:17.00#ibcon#enter wrdev, iclass 11, count 2 2006.201.08:33:17.00#ibcon#first serial, iclass 11, count 2 2006.201.08:33:17.00#ibcon#enter sib2, iclass 11, count 2 2006.201.08:33:17.00#ibcon#flushed, iclass 11, count 2 2006.201.08:33:17.00#ibcon#about to write, iclass 11, count 2 2006.201.08:33:17.00#ibcon#wrote, iclass 11, count 2 2006.201.08:33:17.00#ibcon#about to read 3, iclass 11, count 2 2006.201.08:33:17.02#ibcon#read 3, iclass 11, count 2 2006.201.08:33:17.02#ibcon#about to read 4, iclass 11, count 2 2006.201.08:33:17.02#ibcon#read 4, iclass 11, count 2 2006.201.08:33:17.02#ibcon#about to read 5, iclass 11, count 2 2006.201.08:33:17.02#ibcon#read 5, iclass 11, count 2 2006.201.08:33:17.02#ibcon#about to read 6, iclass 11, count 2 2006.201.08:33:17.02#ibcon#read 6, iclass 11, count 2 2006.201.08:33:17.02#ibcon#end of sib2, iclass 11, count 2 2006.201.08:33:17.02#ibcon#*mode == 0, iclass 11, count 2 2006.201.08:33:17.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.08:33:17.02#ibcon#[27=AT02-05\r\n] 2006.201.08:33:17.02#ibcon#*before write, iclass 11, count 2 2006.201.08:33:17.02#ibcon#enter sib2, iclass 11, count 2 2006.201.08:33:17.02#ibcon#flushed, iclass 11, count 2 2006.201.08:33:17.02#ibcon#about to write, iclass 11, count 2 2006.201.08:33:17.02#ibcon#wrote, iclass 11, count 2 2006.201.08:33:17.02#ibcon#about to read 3, iclass 11, count 2 2006.201.08:33:17.05#ibcon#read 3, iclass 11, count 2 2006.201.08:33:17.05#ibcon#about to read 4, iclass 11, count 2 2006.201.08:33:17.05#ibcon#read 4, iclass 11, count 2 2006.201.08:33:17.05#ibcon#about to read 5, iclass 11, count 2 2006.201.08:33:17.05#ibcon#read 5, iclass 11, count 2 2006.201.08:33:17.05#ibcon#about to read 6, iclass 11, count 2 2006.201.08:33:17.05#ibcon#read 6, iclass 11, count 2 2006.201.08:33:17.05#ibcon#end of sib2, iclass 11, count 2 2006.201.08:33:17.05#ibcon#*after write, iclass 11, count 2 2006.201.08:33:17.05#ibcon#*before return 0, iclass 11, count 2 2006.201.08:33:17.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:17.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:33:17.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.08:33:17.05#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:17.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:17.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:17.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:17.17#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:33:17.17#ibcon#first serial, iclass 11, count 0 2006.201.08:33:17.17#ibcon#enter sib2, iclass 11, count 0 2006.201.08:33:17.17#ibcon#flushed, iclass 11, count 0 2006.201.08:33:17.17#ibcon#about to write, iclass 11, count 0 2006.201.08:33:17.17#ibcon#wrote, iclass 11, count 0 2006.201.08:33:17.17#ibcon#about to read 3, iclass 11, count 0 2006.201.08:33:17.19#ibcon#read 3, iclass 11, count 0 2006.201.08:33:17.19#ibcon#about to read 4, iclass 11, count 0 2006.201.08:33:17.19#ibcon#read 4, iclass 11, count 0 2006.201.08:33:17.19#ibcon#about to read 5, iclass 11, count 0 2006.201.08:33:17.19#ibcon#read 5, iclass 11, count 0 2006.201.08:33:17.19#ibcon#about to read 6, iclass 11, count 0 2006.201.08:33:17.19#ibcon#read 6, iclass 11, count 0 2006.201.08:33:17.19#ibcon#end of sib2, iclass 11, count 0 2006.201.08:33:17.19#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:33:17.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:33:17.19#ibcon#[27=USB\r\n] 2006.201.08:33:17.19#ibcon#*before write, iclass 11, count 0 2006.201.08:33:17.19#ibcon#enter sib2, iclass 11, count 0 2006.201.08:33:17.19#ibcon#flushed, iclass 11, count 0 2006.201.08:33:17.19#ibcon#about to write, iclass 11, count 0 2006.201.08:33:17.19#ibcon#wrote, iclass 11, count 0 2006.201.08:33:17.19#ibcon#about to read 3, iclass 11, count 0 2006.201.08:33:17.22#ibcon#read 3, iclass 11, count 0 2006.201.08:33:17.22#ibcon#about to read 4, iclass 11, count 0 2006.201.08:33:17.22#ibcon#read 4, iclass 11, count 0 2006.201.08:33:17.22#ibcon#about to read 5, iclass 11, count 0 2006.201.08:33:17.22#ibcon#read 5, iclass 11, count 0 2006.201.08:33:17.22#ibcon#about to read 6, iclass 11, count 0 2006.201.08:33:17.22#ibcon#read 6, iclass 11, count 0 2006.201.08:33:17.22#ibcon#end of sib2, iclass 11, count 0 2006.201.08:33:17.22#ibcon#*after write, iclass 11, count 0 2006.201.08:33:17.22#ibcon#*before return 0, iclass 11, count 0 2006.201.08:33:17.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:17.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:33:17.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:33:17.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:33:17.22$vck44/vblo=3,649.99 2006.201.08:33:17.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.08:33:17.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.08:33:17.22#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:17.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:17.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:17.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:17.22#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:33:17.22#ibcon#first serial, iclass 13, count 0 2006.201.08:33:17.22#ibcon#enter sib2, iclass 13, count 0 2006.201.08:33:17.22#ibcon#flushed, iclass 13, count 0 2006.201.08:33:17.22#ibcon#about to write, iclass 13, count 0 2006.201.08:33:17.22#ibcon#wrote, iclass 13, count 0 2006.201.08:33:17.22#ibcon#about to read 3, iclass 13, count 0 2006.201.08:33:17.24#ibcon#read 3, iclass 13, count 0 2006.201.08:33:17.24#ibcon#about to read 4, iclass 13, count 0 2006.201.08:33:17.24#ibcon#read 4, iclass 13, count 0 2006.201.08:33:17.24#ibcon#about to read 5, iclass 13, count 0 2006.201.08:33:17.24#ibcon#read 5, iclass 13, count 0 2006.201.08:33:17.24#ibcon#about to read 6, iclass 13, count 0 2006.201.08:33:17.24#ibcon#read 6, iclass 13, count 0 2006.201.08:33:17.24#ibcon#end of sib2, iclass 13, count 0 2006.201.08:33:17.24#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:33:17.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:33:17.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:33:17.24#ibcon#*before write, iclass 13, count 0 2006.201.08:33:17.24#ibcon#enter sib2, iclass 13, count 0 2006.201.08:33:17.24#ibcon#flushed, iclass 13, count 0 2006.201.08:33:17.24#ibcon#about to write, iclass 13, count 0 2006.201.08:33:17.24#ibcon#wrote, iclass 13, count 0 2006.201.08:33:17.24#ibcon#about to read 3, iclass 13, count 0 2006.201.08:33:17.28#ibcon#read 3, iclass 13, count 0 2006.201.08:33:17.28#ibcon#about to read 4, iclass 13, count 0 2006.201.08:33:17.28#ibcon#read 4, iclass 13, count 0 2006.201.08:33:17.28#ibcon#about to read 5, iclass 13, count 0 2006.201.08:33:17.28#ibcon#read 5, iclass 13, count 0 2006.201.08:33:17.28#ibcon#about to read 6, iclass 13, count 0 2006.201.08:33:17.28#ibcon#read 6, iclass 13, count 0 2006.201.08:33:17.28#ibcon#end of sib2, iclass 13, count 0 2006.201.08:33:17.28#ibcon#*after write, iclass 13, count 0 2006.201.08:33:17.28#ibcon#*before return 0, iclass 13, count 0 2006.201.08:33:17.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:17.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:33:17.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:33:17.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:33:17.28$vck44/vb=3,4 2006.201.08:33:17.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.08:33:17.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.08:33:17.28#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:17.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:17.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:17.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:17.34#ibcon#enter wrdev, iclass 15, count 2 2006.201.08:33:17.34#ibcon#first serial, iclass 15, count 2 2006.201.08:33:17.34#ibcon#enter sib2, iclass 15, count 2 2006.201.08:33:17.34#ibcon#flushed, iclass 15, count 2 2006.201.08:33:17.34#ibcon#about to write, iclass 15, count 2 2006.201.08:33:17.34#ibcon#wrote, iclass 15, count 2 2006.201.08:33:17.34#ibcon#about to read 3, iclass 15, count 2 2006.201.08:33:17.36#ibcon#read 3, iclass 15, count 2 2006.201.08:33:17.36#ibcon#about to read 4, iclass 15, count 2 2006.201.08:33:17.36#ibcon#read 4, iclass 15, count 2 2006.201.08:33:17.36#ibcon#about to read 5, iclass 15, count 2 2006.201.08:33:17.36#ibcon#read 5, iclass 15, count 2 2006.201.08:33:17.36#ibcon#about to read 6, iclass 15, count 2 2006.201.08:33:17.36#ibcon#read 6, iclass 15, count 2 2006.201.08:33:17.36#ibcon#end of sib2, iclass 15, count 2 2006.201.08:33:17.36#ibcon#*mode == 0, iclass 15, count 2 2006.201.08:33:17.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.08:33:17.36#ibcon#[27=AT03-04\r\n] 2006.201.08:33:17.36#ibcon#*before write, iclass 15, count 2 2006.201.08:33:17.36#ibcon#enter sib2, iclass 15, count 2 2006.201.08:33:17.36#ibcon#flushed, iclass 15, count 2 2006.201.08:33:17.36#ibcon#about to write, iclass 15, count 2 2006.201.08:33:17.36#ibcon#wrote, iclass 15, count 2 2006.201.08:33:17.36#ibcon#about to read 3, iclass 15, count 2 2006.201.08:33:17.39#ibcon#read 3, iclass 15, count 2 2006.201.08:33:17.39#ibcon#about to read 4, iclass 15, count 2 2006.201.08:33:17.39#ibcon#read 4, iclass 15, count 2 2006.201.08:33:17.39#ibcon#about to read 5, iclass 15, count 2 2006.201.08:33:17.39#ibcon#read 5, iclass 15, count 2 2006.201.08:33:17.39#ibcon#about to read 6, iclass 15, count 2 2006.201.08:33:17.39#ibcon#read 6, iclass 15, count 2 2006.201.08:33:17.39#ibcon#end of sib2, iclass 15, count 2 2006.201.08:33:17.39#ibcon#*after write, iclass 15, count 2 2006.201.08:33:17.39#ibcon#*before return 0, iclass 15, count 2 2006.201.08:33:17.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:17.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:33:17.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.08:33:17.39#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:17.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:17.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:17.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:17.51#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:33:17.51#ibcon#first serial, iclass 15, count 0 2006.201.08:33:17.51#ibcon#enter sib2, iclass 15, count 0 2006.201.08:33:17.51#ibcon#flushed, iclass 15, count 0 2006.201.08:33:17.51#ibcon#about to write, iclass 15, count 0 2006.201.08:33:17.51#ibcon#wrote, iclass 15, count 0 2006.201.08:33:17.51#ibcon#about to read 3, iclass 15, count 0 2006.201.08:33:17.53#ibcon#read 3, iclass 15, count 0 2006.201.08:33:17.53#ibcon#about to read 4, iclass 15, count 0 2006.201.08:33:17.53#ibcon#read 4, iclass 15, count 0 2006.201.08:33:17.53#ibcon#about to read 5, iclass 15, count 0 2006.201.08:33:17.53#ibcon#read 5, iclass 15, count 0 2006.201.08:33:17.53#ibcon#about to read 6, iclass 15, count 0 2006.201.08:33:17.53#ibcon#read 6, iclass 15, count 0 2006.201.08:33:17.53#ibcon#end of sib2, iclass 15, count 0 2006.201.08:33:17.53#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:33:17.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:33:17.53#ibcon#[27=USB\r\n] 2006.201.08:33:17.53#ibcon#*before write, iclass 15, count 0 2006.201.08:33:17.53#ibcon#enter sib2, iclass 15, count 0 2006.201.08:33:17.53#ibcon#flushed, iclass 15, count 0 2006.201.08:33:17.53#ibcon#about to write, iclass 15, count 0 2006.201.08:33:17.53#ibcon#wrote, iclass 15, count 0 2006.201.08:33:17.53#ibcon#about to read 3, iclass 15, count 0 2006.201.08:33:17.56#ibcon#read 3, iclass 15, count 0 2006.201.08:33:17.56#ibcon#about to read 4, iclass 15, count 0 2006.201.08:33:17.56#ibcon#read 4, iclass 15, count 0 2006.201.08:33:17.56#ibcon#about to read 5, iclass 15, count 0 2006.201.08:33:17.56#ibcon#read 5, iclass 15, count 0 2006.201.08:33:17.56#ibcon#about to read 6, iclass 15, count 0 2006.201.08:33:17.56#ibcon#read 6, iclass 15, count 0 2006.201.08:33:17.56#ibcon#end of sib2, iclass 15, count 0 2006.201.08:33:17.56#ibcon#*after write, iclass 15, count 0 2006.201.08:33:17.56#ibcon#*before return 0, iclass 15, count 0 2006.201.08:33:17.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:17.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:33:17.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:33:17.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:33:17.56$vck44/vblo=4,679.99 2006.201.08:33:17.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.08:33:17.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.08:33:17.56#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:17.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:17.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:17.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:17.56#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:33:17.56#ibcon#first serial, iclass 17, count 0 2006.201.08:33:17.56#ibcon#enter sib2, iclass 17, count 0 2006.201.08:33:17.56#ibcon#flushed, iclass 17, count 0 2006.201.08:33:17.56#ibcon#about to write, iclass 17, count 0 2006.201.08:33:17.56#ibcon#wrote, iclass 17, count 0 2006.201.08:33:17.56#ibcon#about to read 3, iclass 17, count 0 2006.201.08:33:17.58#ibcon#read 3, iclass 17, count 0 2006.201.08:33:17.58#ibcon#about to read 4, iclass 17, count 0 2006.201.08:33:17.58#ibcon#read 4, iclass 17, count 0 2006.201.08:33:17.58#ibcon#about to read 5, iclass 17, count 0 2006.201.08:33:17.58#ibcon#read 5, iclass 17, count 0 2006.201.08:33:17.58#ibcon#about to read 6, iclass 17, count 0 2006.201.08:33:17.58#ibcon#read 6, iclass 17, count 0 2006.201.08:33:17.58#ibcon#end of sib2, iclass 17, count 0 2006.201.08:33:17.58#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:33:17.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:33:17.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:33:17.58#ibcon#*before write, iclass 17, count 0 2006.201.08:33:17.58#ibcon#enter sib2, iclass 17, count 0 2006.201.08:33:17.58#ibcon#flushed, iclass 17, count 0 2006.201.08:33:17.58#ibcon#about to write, iclass 17, count 0 2006.201.08:33:17.58#ibcon#wrote, iclass 17, count 0 2006.201.08:33:17.58#ibcon#about to read 3, iclass 17, count 0 2006.201.08:33:17.62#ibcon#read 3, iclass 17, count 0 2006.201.08:33:17.62#ibcon#about to read 4, iclass 17, count 0 2006.201.08:33:17.62#ibcon#read 4, iclass 17, count 0 2006.201.08:33:17.62#ibcon#about to read 5, iclass 17, count 0 2006.201.08:33:17.62#ibcon#read 5, iclass 17, count 0 2006.201.08:33:17.62#ibcon#about to read 6, iclass 17, count 0 2006.201.08:33:17.62#ibcon#read 6, iclass 17, count 0 2006.201.08:33:17.62#ibcon#end of sib2, iclass 17, count 0 2006.201.08:33:17.62#ibcon#*after write, iclass 17, count 0 2006.201.08:33:17.62#ibcon#*before return 0, iclass 17, count 0 2006.201.08:33:17.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:17.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:33:17.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:33:17.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:33:17.62$vck44/vb=4,5 2006.201.08:33:17.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.08:33:17.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.08:33:17.62#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:17.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:17.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:17.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:17.68#ibcon#enter wrdev, iclass 19, count 2 2006.201.08:33:17.68#ibcon#first serial, iclass 19, count 2 2006.201.08:33:17.68#ibcon#enter sib2, iclass 19, count 2 2006.201.08:33:17.68#ibcon#flushed, iclass 19, count 2 2006.201.08:33:17.68#ibcon#about to write, iclass 19, count 2 2006.201.08:33:17.68#ibcon#wrote, iclass 19, count 2 2006.201.08:33:17.68#ibcon#about to read 3, iclass 19, count 2 2006.201.08:33:17.70#ibcon#read 3, iclass 19, count 2 2006.201.08:33:17.70#ibcon#about to read 4, iclass 19, count 2 2006.201.08:33:17.70#ibcon#read 4, iclass 19, count 2 2006.201.08:33:17.70#ibcon#about to read 5, iclass 19, count 2 2006.201.08:33:17.70#ibcon#read 5, iclass 19, count 2 2006.201.08:33:17.70#ibcon#about to read 6, iclass 19, count 2 2006.201.08:33:17.70#ibcon#read 6, iclass 19, count 2 2006.201.08:33:17.70#ibcon#end of sib2, iclass 19, count 2 2006.201.08:33:17.70#ibcon#*mode == 0, iclass 19, count 2 2006.201.08:33:17.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.08:33:17.70#ibcon#[27=AT04-05\r\n] 2006.201.08:33:17.70#ibcon#*before write, iclass 19, count 2 2006.201.08:33:17.70#ibcon#enter sib2, iclass 19, count 2 2006.201.08:33:17.70#ibcon#flushed, iclass 19, count 2 2006.201.08:33:17.70#ibcon#about to write, iclass 19, count 2 2006.201.08:33:17.70#ibcon#wrote, iclass 19, count 2 2006.201.08:33:17.70#ibcon#about to read 3, iclass 19, count 2 2006.201.08:33:17.73#ibcon#read 3, iclass 19, count 2 2006.201.08:33:17.73#ibcon#about to read 4, iclass 19, count 2 2006.201.08:33:17.73#ibcon#read 4, iclass 19, count 2 2006.201.08:33:17.73#ibcon#about to read 5, iclass 19, count 2 2006.201.08:33:17.73#ibcon#read 5, iclass 19, count 2 2006.201.08:33:17.73#ibcon#about to read 6, iclass 19, count 2 2006.201.08:33:17.73#ibcon#read 6, iclass 19, count 2 2006.201.08:33:17.73#ibcon#end of sib2, iclass 19, count 2 2006.201.08:33:17.73#ibcon#*after write, iclass 19, count 2 2006.201.08:33:17.73#ibcon#*before return 0, iclass 19, count 2 2006.201.08:33:17.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:17.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:33:17.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.08:33:17.73#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:17.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:17.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:17.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:17.85#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:33:17.85#ibcon#first serial, iclass 19, count 0 2006.201.08:33:17.85#ibcon#enter sib2, iclass 19, count 0 2006.201.08:33:17.85#ibcon#flushed, iclass 19, count 0 2006.201.08:33:17.85#ibcon#about to write, iclass 19, count 0 2006.201.08:33:17.85#ibcon#wrote, iclass 19, count 0 2006.201.08:33:17.85#ibcon#about to read 3, iclass 19, count 0 2006.201.08:33:17.87#ibcon#read 3, iclass 19, count 0 2006.201.08:33:17.87#ibcon#about to read 4, iclass 19, count 0 2006.201.08:33:17.87#ibcon#read 4, iclass 19, count 0 2006.201.08:33:17.87#ibcon#about to read 5, iclass 19, count 0 2006.201.08:33:17.87#ibcon#read 5, iclass 19, count 0 2006.201.08:33:17.87#ibcon#about to read 6, iclass 19, count 0 2006.201.08:33:17.87#ibcon#read 6, iclass 19, count 0 2006.201.08:33:17.87#ibcon#end of sib2, iclass 19, count 0 2006.201.08:33:17.87#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:33:17.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:33:17.87#ibcon#[27=USB\r\n] 2006.201.08:33:17.87#ibcon#*before write, iclass 19, count 0 2006.201.08:33:17.87#ibcon#enter sib2, iclass 19, count 0 2006.201.08:33:17.87#ibcon#flushed, iclass 19, count 0 2006.201.08:33:17.87#ibcon#about to write, iclass 19, count 0 2006.201.08:33:17.87#ibcon#wrote, iclass 19, count 0 2006.201.08:33:17.87#ibcon#about to read 3, iclass 19, count 0 2006.201.08:33:17.90#ibcon#read 3, iclass 19, count 0 2006.201.08:33:17.90#ibcon#about to read 4, iclass 19, count 0 2006.201.08:33:17.90#ibcon#read 4, iclass 19, count 0 2006.201.08:33:17.90#ibcon#about to read 5, iclass 19, count 0 2006.201.08:33:17.90#ibcon#read 5, iclass 19, count 0 2006.201.08:33:17.90#ibcon#about to read 6, iclass 19, count 0 2006.201.08:33:17.90#ibcon#read 6, iclass 19, count 0 2006.201.08:33:17.90#ibcon#end of sib2, iclass 19, count 0 2006.201.08:33:17.90#ibcon#*after write, iclass 19, count 0 2006.201.08:33:17.90#ibcon#*before return 0, iclass 19, count 0 2006.201.08:33:17.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:17.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:33:17.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:33:17.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:33:17.90$vck44/vblo=5,709.99 2006.201.08:33:17.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.08:33:17.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.08:33:17.90#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:17.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:17.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:17.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:17.90#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:33:17.90#ibcon#first serial, iclass 21, count 0 2006.201.08:33:17.90#ibcon#enter sib2, iclass 21, count 0 2006.201.08:33:17.90#ibcon#flushed, iclass 21, count 0 2006.201.08:33:17.90#ibcon#about to write, iclass 21, count 0 2006.201.08:33:17.90#ibcon#wrote, iclass 21, count 0 2006.201.08:33:17.90#ibcon#about to read 3, iclass 21, count 0 2006.201.08:33:17.92#ibcon#read 3, iclass 21, count 0 2006.201.08:33:17.92#ibcon#about to read 4, iclass 21, count 0 2006.201.08:33:17.92#ibcon#read 4, iclass 21, count 0 2006.201.08:33:17.92#ibcon#about to read 5, iclass 21, count 0 2006.201.08:33:17.92#ibcon#read 5, iclass 21, count 0 2006.201.08:33:17.92#ibcon#about to read 6, iclass 21, count 0 2006.201.08:33:17.92#ibcon#read 6, iclass 21, count 0 2006.201.08:33:17.92#ibcon#end of sib2, iclass 21, count 0 2006.201.08:33:17.92#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:33:17.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:33:17.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:33:17.92#ibcon#*before write, iclass 21, count 0 2006.201.08:33:17.92#ibcon#enter sib2, iclass 21, count 0 2006.201.08:33:17.92#ibcon#flushed, iclass 21, count 0 2006.201.08:33:17.92#ibcon#about to write, iclass 21, count 0 2006.201.08:33:17.92#ibcon#wrote, iclass 21, count 0 2006.201.08:33:17.92#ibcon#about to read 3, iclass 21, count 0 2006.201.08:33:17.97#ibcon#read 3, iclass 21, count 0 2006.201.08:33:17.97#ibcon#about to read 4, iclass 21, count 0 2006.201.08:33:17.97#ibcon#read 4, iclass 21, count 0 2006.201.08:33:17.97#ibcon#about to read 5, iclass 21, count 0 2006.201.08:33:17.97#ibcon#read 5, iclass 21, count 0 2006.201.08:33:17.97#ibcon#about to read 6, iclass 21, count 0 2006.201.08:33:17.97#ibcon#read 6, iclass 21, count 0 2006.201.08:33:17.97#ibcon#end of sib2, iclass 21, count 0 2006.201.08:33:17.97#ibcon#*after write, iclass 21, count 0 2006.201.08:33:17.97#ibcon#*before return 0, iclass 21, count 0 2006.201.08:33:17.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:17.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:33:17.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:33:17.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:33:17.97$vck44/vb=5,4 2006.201.08:33:17.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.08:33:17.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.08:33:17.97#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:17.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:18.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:18.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:18.02#ibcon#enter wrdev, iclass 23, count 2 2006.201.08:33:18.02#ibcon#first serial, iclass 23, count 2 2006.201.08:33:18.02#ibcon#enter sib2, iclass 23, count 2 2006.201.08:33:18.02#ibcon#flushed, iclass 23, count 2 2006.201.08:33:18.02#ibcon#about to write, iclass 23, count 2 2006.201.08:33:18.02#ibcon#wrote, iclass 23, count 2 2006.201.08:33:18.02#ibcon#about to read 3, iclass 23, count 2 2006.201.08:33:18.04#ibcon#read 3, iclass 23, count 2 2006.201.08:33:18.04#ibcon#about to read 4, iclass 23, count 2 2006.201.08:33:18.04#ibcon#read 4, iclass 23, count 2 2006.201.08:33:18.04#ibcon#about to read 5, iclass 23, count 2 2006.201.08:33:18.04#ibcon#read 5, iclass 23, count 2 2006.201.08:33:18.04#ibcon#about to read 6, iclass 23, count 2 2006.201.08:33:18.04#ibcon#read 6, iclass 23, count 2 2006.201.08:33:18.04#ibcon#end of sib2, iclass 23, count 2 2006.201.08:33:18.04#ibcon#*mode == 0, iclass 23, count 2 2006.201.08:33:18.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.08:33:18.04#ibcon#[27=AT05-04\r\n] 2006.201.08:33:18.04#ibcon#*before write, iclass 23, count 2 2006.201.08:33:18.04#ibcon#enter sib2, iclass 23, count 2 2006.201.08:33:18.04#ibcon#flushed, iclass 23, count 2 2006.201.08:33:18.04#ibcon#about to write, iclass 23, count 2 2006.201.08:33:18.04#ibcon#wrote, iclass 23, count 2 2006.201.08:33:18.04#ibcon#about to read 3, iclass 23, count 2 2006.201.08:33:18.07#ibcon#read 3, iclass 23, count 2 2006.201.08:33:18.07#ibcon#about to read 4, iclass 23, count 2 2006.201.08:33:18.07#ibcon#read 4, iclass 23, count 2 2006.201.08:33:18.07#ibcon#about to read 5, iclass 23, count 2 2006.201.08:33:18.07#ibcon#read 5, iclass 23, count 2 2006.201.08:33:18.07#ibcon#about to read 6, iclass 23, count 2 2006.201.08:33:18.07#ibcon#read 6, iclass 23, count 2 2006.201.08:33:18.07#ibcon#end of sib2, iclass 23, count 2 2006.201.08:33:18.07#ibcon#*after write, iclass 23, count 2 2006.201.08:33:18.07#ibcon#*before return 0, iclass 23, count 2 2006.201.08:33:18.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:18.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:33:18.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.08:33:18.07#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:18.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:18.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:18.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:18.19#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:33:18.19#ibcon#first serial, iclass 23, count 0 2006.201.08:33:18.19#ibcon#enter sib2, iclass 23, count 0 2006.201.08:33:18.19#ibcon#flushed, iclass 23, count 0 2006.201.08:33:18.19#ibcon#about to write, iclass 23, count 0 2006.201.08:33:18.19#ibcon#wrote, iclass 23, count 0 2006.201.08:33:18.19#ibcon#about to read 3, iclass 23, count 0 2006.201.08:33:18.22#ibcon#read 3, iclass 23, count 0 2006.201.08:33:18.22#ibcon#about to read 4, iclass 23, count 0 2006.201.08:33:18.22#ibcon#read 4, iclass 23, count 0 2006.201.08:33:18.22#ibcon#about to read 5, iclass 23, count 0 2006.201.08:33:18.22#ibcon#read 5, iclass 23, count 0 2006.201.08:33:18.22#ibcon#about to read 6, iclass 23, count 0 2006.201.08:33:18.22#ibcon#read 6, iclass 23, count 0 2006.201.08:33:18.22#ibcon#end of sib2, iclass 23, count 0 2006.201.08:33:18.22#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:33:18.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:33:18.22#ibcon#[27=USB\r\n] 2006.201.08:33:18.22#ibcon#*before write, iclass 23, count 0 2006.201.08:33:18.22#ibcon#enter sib2, iclass 23, count 0 2006.201.08:33:18.22#ibcon#flushed, iclass 23, count 0 2006.201.08:33:18.22#ibcon#about to write, iclass 23, count 0 2006.201.08:33:18.22#ibcon#wrote, iclass 23, count 0 2006.201.08:33:18.22#ibcon#about to read 3, iclass 23, count 0 2006.201.08:33:18.25#ibcon#read 3, iclass 23, count 0 2006.201.08:33:18.25#ibcon#about to read 4, iclass 23, count 0 2006.201.08:33:18.25#ibcon#read 4, iclass 23, count 0 2006.201.08:33:18.25#ibcon#about to read 5, iclass 23, count 0 2006.201.08:33:18.25#ibcon#read 5, iclass 23, count 0 2006.201.08:33:18.25#ibcon#about to read 6, iclass 23, count 0 2006.201.08:33:18.25#ibcon#read 6, iclass 23, count 0 2006.201.08:33:18.25#ibcon#end of sib2, iclass 23, count 0 2006.201.08:33:18.25#ibcon#*after write, iclass 23, count 0 2006.201.08:33:18.25#ibcon#*before return 0, iclass 23, count 0 2006.201.08:33:18.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:18.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:33:18.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:33:18.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:33:18.25$vck44/vblo=6,719.99 2006.201.08:33:18.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.08:33:18.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.08:33:18.25#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:18.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:18.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:18.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:18.25#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:33:18.25#ibcon#first serial, iclass 25, count 0 2006.201.08:33:18.25#ibcon#enter sib2, iclass 25, count 0 2006.201.08:33:18.25#ibcon#flushed, iclass 25, count 0 2006.201.08:33:18.25#ibcon#about to write, iclass 25, count 0 2006.201.08:33:18.25#ibcon#wrote, iclass 25, count 0 2006.201.08:33:18.25#ibcon#about to read 3, iclass 25, count 0 2006.201.08:33:18.27#ibcon#read 3, iclass 25, count 0 2006.201.08:33:18.27#ibcon#about to read 4, iclass 25, count 0 2006.201.08:33:18.27#ibcon#read 4, iclass 25, count 0 2006.201.08:33:18.27#ibcon#about to read 5, iclass 25, count 0 2006.201.08:33:18.27#ibcon#read 5, iclass 25, count 0 2006.201.08:33:18.27#ibcon#about to read 6, iclass 25, count 0 2006.201.08:33:18.27#ibcon#read 6, iclass 25, count 0 2006.201.08:33:18.27#ibcon#end of sib2, iclass 25, count 0 2006.201.08:33:18.27#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:33:18.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:33:18.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:33:18.27#ibcon#*before write, iclass 25, count 0 2006.201.08:33:18.27#ibcon#enter sib2, iclass 25, count 0 2006.201.08:33:18.27#ibcon#flushed, iclass 25, count 0 2006.201.08:33:18.27#ibcon#about to write, iclass 25, count 0 2006.201.08:33:18.27#ibcon#wrote, iclass 25, count 0 2006.201.08:33:18.27#ibcon#about to read 3, iclass 25, count 0 2006.201.08:33:18.31#ibcon#read 3, iclass 25, count 0 2006.201.08:33:18.31#ibcon#about to read 4, iclass 25, count 0 2006.201.08:33:18.31#ibcon#read 4, iclass 25, count 0 2006.201.08:33:18.31#ibcon#about to read 5, iclass 25, count 0 2006.201.08:33:18.31#ibcon#read 5, iclass 25, count 0 2006.201.08:33:18.31#ibcon#about to read 6, iclass 25, count 0 2006.201.08:33:18.31#ibcon#read 6, iclass 25, count 0 2006.201.08:33:18.31#ibcon#end of sib2, iclass 25, count 0 2006.201.08:33:18.31#ibcon#*after write, iclass 25, count 0 2006.201.08:33:18.31#ibcon#*before return 0, iclass 25, count 0 2006.201.08:33:18.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:18.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:33:18.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:33:18.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:33:18.31$vck44/vb=6,4 2006.201.08:33:18.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.08:33:18.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.08:33:18.31#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:18.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:18.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:18.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:18.37#ibcon#enter wrdev, iclass 27, count 2 2006.201.08:33:18.37#ibcon#first serial, iclass 27, count 2 2006.201.08:33:18.37#ibcon#enter sib2, iclass 27, count 2 2006.201.08:33:18.37#ibcon#flushed, iclass 27, count 2 2006.201.08:33:18.37#ibcon#about to write, iclass 27, count 2 2006.201.08:33:18.37#ibcon#wrote, iclass 27, count 2 2006.201.08:33:18.37#ibcon#about to read 3, iclass 27, count 2 2006.201.08:33:18.39#ibcon#read 3, iclass 27, count 2 2006.201.08:33:18.39#ibcon#about to read 4, iclass 27, count 2 2006.201.08:33:18.39#ibcon#read 4, iclass 27, count 2 2006.201.08:33:18.39#ibcon#about to read 5, iclass 27, count 2 2006.201.08:33:18.39#ibcon#read 5, iclass 27, count 2 2006.201.08:33:18.39#ibcon#about to read 6, iclass 27, count 2 2006.201.08:33:18.39#ibcon#read 6, iclass 27, count 2 2006.201.08:33:18.39#ibcon#end of sib2, iclass 27, count 2 2006.201.08:33:18.39#ibcon#*mode == 0, iclass 27, count 2 2006.201.08:33:18.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.08:33:18.39#ibcon#[27=AT06-04\r\n] 2006.201.08:33:18.39#ibcon#*before write, iclass 27, count 2 2006.201.08:33:18.39#ibcon#enter sib2, iclass 27, count 2 2006.201.08:33:18.39#ibcon#flushed, iclass 27, count 2 2006.201.08:33:18.39#ibcon#about to write, iclass 27, count 2 2006.201.08:33:18.39#ibcon#wrote, iclass 27, count 2 2006.201.08:33:18.39#ibcon#about to read 3, iclass 27, count 2 2006.201.08:33:18.42#ibcon#read 3, iclass 27, count 2 2006.201.08:33:18.42#ibcon#about to read 4, iclass 27, count 2 2006.201.08:33:18.42#ibcon#read 4, iclass 27, count 2 2006.201.08:33:18.42#ibcon#about to read 5, iclass 27, count 2 2006.201.08:33:18.42#ibcon#read 5, iclass 27, count 2 2006.201.08:33:18.42#ibcon#about to read 6, iclass 27, count 2 2006.201.08:33:18.42#ibcon#read 6, iclass 27, count 2 2006.201.08:33:18.42#ibcon#end of sib2, iclass 27, count 2 2006.201.08:33:18.42#ibcon#*after write, iclass 27, count 2 2006.201.08:33:18.42#ibcon#*before return 0, iclass 27, count 2 2006.201.08:33:18.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:18.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:33:18.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.08:33:18.42#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:18.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:18.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:18.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:18.54#ibcon#enter wrdev, iclass 27, count 0 2006.201.08:33:18.54#ibcon#first serial, iclass 27, count 0 2006.201.08:33:18.54#ibcon#enter sib2, iclass 27, count 0 2006.201.08:33:18.54#ibcon#flushed, iclass 27, count 0 2006.201.08:33:18.54#ibcon#about to write, iclass 27, count 0 2006.201.08:33:18.54#ibcon#wrote, iclass 27, count 0 2006.201.08:33:18.54#ibcon#about to read 3, iclass 27, count 0 2006.201.08:33:18.56#ibcon#read 3, iclass 27, count 0 2006.201.08:33:18.56#ibcon#about to read 4, iclass 27, count 0 2006.201.08:33:18.56#ibcon#read 4, iclass 27, count 0 2006.201.08:33:18.56#ibcon#about to read 5, iclass 27, count 0 2006.201.08:33:18.56#ibcon#read 5, iclass 27, count 0 2006.201.08:33:18.56#ibcon#about to read 6, iclass 27, count 0 2006.201.08:33:18.56#ibcon#read 6, iclass 27, count 0 2006.201.08:33:18.56#ibcon#end of sib2, iclass 27, count 0 2006.201.08:33:18.56#ibcon#*mode == 0, iclass 27, count 0 2006.201.08:33:18.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.08:33:18.56#ibcon#[27=USB\r\n] 2006.201.08:33:18.56#ibcon#*before write, iclass 27, count 0 2006.201.08:33:18.56#ibcon#enter sib2, iclass 27, count 0 2006.201.08:33:18.56#ibcon#flushed, iclass 27, count 0 2006.201.08:33:18.56#ibcon#about to write, iclass 27, count 0 2006.201.08:33:18.56#ibcon#wrote, iclass 27, count 0 2006.201.08:33:18.56#ibcon#about to read 3, iclass 27, count 0 2006.201.08:33:18.59#ibcon#read 3, iclass 27, count 0 2006.201.08:33:18.59#ibcon#about to read 4, iclass 27, count 0 2006.201.08:33:18.59#ibcon#read 4, iclass 27, count 0 2006.201.08:33:18.59#ibcon#about to read 5, iclass 27, count 0 2006.201.08:33:18.59#ibcon#read 5, iclass 27, count 0 2006.201.08:33:18.59#ibcon#about to read 6, iclass 27, count 0 2006.201.08:33:18.59#ibcon#read 6, iclass 27, count 0 2006.201.08:33:18.59#ibcon#end of sib2, iclass 27, count 0 2006.201.08:33:18.59#ibcon#*after write, iclass 27, count 0 2006.201.08:33:18.59#ibcon#*before return 0, iclass 27, count 0 2006.201.08:33:18.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:18.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:33:18.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.08:33:18.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.08:33:18.59$vck44/vblo=7,734.99 2006.201.08:33:18.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.08:33:18.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.08:33:18.59#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:18.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:18.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:18.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:18.59#ibcon#enter wrdev, iclass 29, count 0 2006.201.08:33:18.59#ibcon#first serial, iclass 29, count 0 2006.201.08:33:18.59#ibcon#enter sib2, iclass 29, count 0 2006.201.08:33:18.59#ibcon#flushed, iclass 29, count 0 2006.201.08:33:18.59#ibcon#about to write, iclass 29, count 0 2006.201.08:33:18.59#ibcon#wrote, iclass 29, count 0 2006.201.08:33:18.59#ibcon#about to read 3, iclass 29, count 0 2006.201.08:33:18.61#ibcon#read 3, iclass 29, count 0 2006.201.08:33:18.61#ibcon#about to read 4, iclass 29, count 0 2006.201.08:33:18.61#ibcon#read 4, iclass 29, count 0 2006.201.08:33:18.61#ibcon#about to read 5, iclass 29, count 0 2006.201.08:33:18.61#ibcon#read 5, iclass 29, count 0 2006.201.08:33:18.61#ibcon#about to read 6, iclass 29, count 0 2006.201.08:33:18.61#ibcon#read 6, iclass 29, count 0 2006.201.08:33:18.61#ibcon#end of sib2, iclass 29, count 0 2006.201.08:33:18.61#ibcon#*mode == 0, iclass 29, count 0 2006.201.08:33:18.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.08:33:18.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:33:18.61#ibcon#*before write, iclass 29, count 0 2006.201.08:33:18.61#ibcon#enter sib2, iclass 29, count 0 2006.201.08:33:18.61#ibcon#flushed, iclass 29, count 0 2006.201.08:33:18.61#ibcon#about to write, iclass 29, count 0 2006.201.08:33:18.61#ibcon#wrote, iclass 29, count 0 2006.201.08:33:18.61#ibcon#about to read 3, iclass 29, count 0 2006.201.08:33:18.65#ibcon#read 3, iclass 29, count 0 2006.201.08:33:18.65#ibcon#about to read 4, iclass 29, count 0 2006.201.08:33:18.65#ibcon#read 4, iclass 29, count 0 2006.201.08:33:18.65#ibcon#about to read 5, iclass 29, count 0 2006.201.08:33:18.65#ibcon#read 5, iclass 29, count 0 2006.201.08:33:18.65#ibcon#about to read 6, iclass 29, count 0 2006.201.08:33:18.65#ibcon#read 6, iclass 29, count 0 2006.201.08:33:18.65#ibcon#end of sib2, iclass 29, count 0 2006.201.08:33:18.65#ibcon#*after write, iclass 29, count 0 2006.201.08:33:18.65#ibcon#*before return 0, iclass 29, count 0 2006.201.08:33:18.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:18.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:33:18.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.08:33:18.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.08:33:18.65$vck44/vb=7,4 2006.201.08:33:18.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.08:33:18.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.08:33:18.65#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:18.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:18.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:18.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:18.71#ibcon#enter wrdev, iclass 31, count 2 2006.201.08:33:18.71#ibcon#first serial, iclass 31, count 2 2006.201.08:33:18.71#ibcon#enter sib2, iclass 31, count 2 2006.201.08:33:18.71#ibcon#flushed, iclass 31, count 2 2006.201.08:33:18.71#ibcon#about to write, iclass 31, count 2 2006.201.08:33:18.71#ibcon#wrote, iclass 31, count 2 2006.201.08:33:18.71#ibcon#about to read 3, iclass 31, count 2 2006.201.08:33:18.73#ibcon#read 3, iclass 31, count 2 2006.201.08:33:18.73#ibcon#about to read 4, iclass 31, count 2 2006.201.08:33:18.73#ibcon#read 4, iclass 31, count 2 2006.201.08:33:18.73#ibcon#about to read 5, iclass 31, count 2 2006.201.08:33:18.73#ibcon#read 5, iclass 31, count 2 2006.201.08:33:18.73#ibcon#about to read 6, iclass 31, count 2 2006.201.08:33:18.73#ibcon#read 6, iclass 31, count 2 2006.201.08:33:18.73#ibcon#end of sib2, iclass 31, count 2 2006.201.08:33:18.73#ibcon#*mode == 0, iclass 31, count 2 2006.201.08:33:18.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.08:33:18.73#ibcon#[27=AT07-04\r\n] 2006.201.08:33:18.73#ibcon#*before write, iclass 31, count 2 2006.201.08:33:18.73#ibcon#enter sib2, iclass 31, count 2 2006.201.08:33:18.73#ibcon#flushed, iclass 31, count 2 2006.201.08:33:18.73#ibcon#about to write, iclass 31, count 2 2006.201.08:33:18.73#ibcon#wrote, iclass 31, count 2 2006.201.08:33:18.73#ibcon#about to read 3, iclass 31, count 2 2006.201.08:33:18.76#ibcon#read 3, iclass 31, count 2 2006.201.08:33:18.76#ibcon#about to read 4, iclass 31, count 2 2006.201.08:33:18.76#ibcon#read 4, iclass 31, count 2 2006.201.08:33:18.76#ibcon#about to read 5, iclass 31, count 2 2006.201.08:33:18.76#ibcon#read 5, iclass 31, count 2 2006.201.08:33:18.76#ibcon#about to read 6, iclass 31, count 2 2006.201.08:33:18.76#ibcon#read 6, iclass 31, count 2 2006.201.08:33:18.76#ibcon#end of sib2, iclass 31, count 2 2006.201.08:33:18.76#ibcon#*after write, iclass 31, count 2 2006.201.08:33:18.76#ibcon#*before return 0, iclass 31, count 2 2006.201.08:33:18.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:18.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:33:18.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.08:33:18.76#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:18.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:18.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:18.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:18.88#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:33:18.88#ibcon#first serial, iclass 31, count 0 2006.201.08:33:18.88#ibcon#enter sib2, iclass 31, count 0 2006.201.08:33:18.88#ibcon#flushed, iclass 31, count 0 2006.201.08:33:18.88#ibcon#about to write, iclass 31, count 0 2006.201.08:33:18.88#ibcon#wrote, iclass 31, count 0 2006.201.08:33:18.88#ibcon#about to read 3, iclass 31, count 0 2006.201.08:33:18.90#ibcon#read 3, iclass 31, count 0 2006.201.08:33:18.90#ibcon#about to read 4, iclass 31, count 0 2006.201.08:33:18.90#ibcon#read 4, iclass 31, count 0 2006.201.08:33:18.90#ibcon#about to read 5, iclass 31, count 0 2006.201.08:33:18.90#ibcon#read 5, iclass 31, count 0 2006.201.08:33:18.90#ibcon#about to read 6, iclass 31, count 0 2006.201.08:33:18.90#ibcon#read 6, iclass 31, count 0 2006.201.08:33:18.90#ibcon#end of sib2, iclass 31, count 0 2006.201.08:33:18.90#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:33:18.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:33:18.90#ibcon#[27=USB\r\n] 2006.201.08:33:18.90#ibcon#*before write, iclass 31, count 0 2006.201.08:33:18.90#ibcon#enter sib2, iclass 31, count 0 2006.201.08:33:18.90#ibcon#flushed, iclass 31, count 0 2006.201.08:33:18.90#ibcon#about to write, iclass 31, count 0 2006.201.08:33:18.90#ibcon#wrote, iclass 31, count 0 2006.201.08:33:18.90#ibcon#about to read 3, iclass 31, count 0 2006.201.08:33:18.93#ibcon#read 3, iclass 31, count 0 2006.201.08:33:18.93#ibcon#about to read 4, iclass 31, count 0 2006.201.08:33:18.93#ibcon#read 4, iclass 31, count 0 2006.201.08:33:18.93#ibcon#about to read 5, iclass 31, count 0 2006.201.08:33:18.93#ibcon#read 5, iclass 31, count 0 2006.201.08:33:18.93#ibcon#about to read 6, iclass 31, count 0 2006.201.08:33:18.93#ibcon#read 6, iclass 31, count 0 2006.201.08:33:18.93#ibcon#end of sib2, iclass 31, count 0 2006.201.08:33:18.93#ibcon#*after write, iclass 31, count 0 2006.201.08:33:18.93#ibcon#*before return 0, iclass 31, count 0 2006.201.08:33:18.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:18.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:33:18.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:33:18.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:33:18.93$vck44/vblo=8,744.99 2006.201.08:33:18.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.08:33:18.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.08:33:18.93#ibcon#ireg 17 cls_cnt 0 2006.201.08:33:18.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:18.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:18.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:18.93#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:33:18.93#ibcon#first serial, iclass 33, count 0 2006.201.08:33:18.93#ibcon#enter sib2, iclass 33, count 0 2006.201.08:33:18.93#ibcon#flushed, iclass 33, count 0 2006.201.08:33:18.93#ibcon#about to write, iclass 33, count 0 2006.201.08:33:18.93#ibcon#wrote, iclass 33, count 0 2006.201.08:33:18.93#ibcon#about to read 3, iclass 33, count 0 2006.201.08:33:18.95#ibcon#read 3, iclass 33, count 0 2006.201.08:33:18.95#ibcon#about to read 4, iclass 33, count 0 2006.201.08:33:18.95#ibcon#read 4, iclass 33, count 0 2006.201.08:33:18.95#ibcon#about to read 5, iclass 33, count 0 2006.201.08:33:18.95#ibcon#read 5, iclass 33, count 0 2006.201.08:33:18.95#ibcon#about to read 6, iclass 33, count 0 2006.201.08:33:18.95#ibcon#read 6, iclass 33, count 0 2006.201.08:33:18.95#ibcon#end of sib2, iclass 33, count 0 2006.201.08:33:18.95#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:33:18.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:33:18.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:33:18.95#ibcon#*before write, iclass 33, count 0 2006.201.08:33:18.95#ibcon#enter sib2, iclass 33, count 0 2006.201.08:33:18.95#ibcon#flushed, iclass 33, count 0 2006.201.08:33:18.95#ibcon#about to write, iclass 33, count 0 2006.201.08:33:18.95#ibcon#wrote, iclass 33, count 0 2006.201.08:33:18.95#ibcon#about to read 3, iclass 33, count 0 2006.201.08:33:19.00#ibcon#read 3, iclass 33, count 0 2006.201.08:33:19.00#ibcon#about to read 4, iclass 33, count 0 2006.201.08:33:19.00#ibcon#read 4, iclass 33, count 0 2006.201.08:33:19.00#ibcon#about to read 5, iclass 33, count 0 2006.201.08:33:19.00#ibcon#read 5, iclass 33, count 0 2006.201.08:33:19.00#ibcon#about to read 6, iclass 33, count 0 2006.201.08:33:19.00#ibcon#read 6, iclass 33, count 0 2006.201.08:33:19.00#ibcon#end of sib2, iclass 33, count 0 2006.201.08:33:19.00#ibcon#*after write, iclass 33, count 0 2006.201.08:33:19.00#ibcon#*before return 0, iclass 33, count 0 2006.201.08:33:19.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:19.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:33:19.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:33:19.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:33:19.00$vck44/vb=8,4 2006.201.08:33:19.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.08:33:19.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.08:33:19.00#ibcon#ireg 11 cls_cnt 2 2006.201.08:33:19.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:19.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:19.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:19.05#ibcon#enter wrdev, iclass 35, count 2 2006.201.08:33:19.05#ibcon#first serial, iclass 35, count 2 2006.201.08:33:19.05#ibcon#enter sib2, iclass 35, count 2 2006.201.08:33:19.05#ibcon#flushed, iclass 35, count 2 2006.201.08:33:19.05#ibcon#about to write, iclass 35, count 2 2006.201.08:33:19.05#ibcon#wrote, iclass 35, count 2 2006.201.08:33:19.05#ibcon#about to read 3, iclass 35, count 2 2006.201.08:33:19.07#ibcon#read 3, iclass 35, count 2 2006.201.08:33:19.07#ibcon#about to read 4, iclass 35, count 2 2006.201.08:33:19.07#ibcon#read 4, iclass 35, count 2 2006.201.08:33:19.07#ibcon#about to read 5, iclass 35, count 2 2006.201.08:33:19.07#ibcon#read 5, iclass 35, count 2 2006.201.08:33:19.07#ibcon#about to read 6, iclass 35, count 2 2006.201.08:33:19.07#ibcon#read 6, iclass 35, count 2 2006.201.08:33:19.07#ibcon#end of sib2, iclass 35, count 2 2006.201.08:33:19.07#ibcon#*mode == 0, iclass 35, count 2 2006.201.08:33:19.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.08:33:19.07#ibcon#[27=AT08-04\r\n] 2006.201.08:33:19.07#ibcon#*before write, iclass 35, count 2 2006.201.08:33:19.07#ibcon#enter sib2, iclass 35, count 2 2006.201.08:33:19.07#ibcon#flushed, iclass 35, count 2 2006.201.08:33:19.07#ibcon#about to write, iclass 35, count 2 2006.201.08:33:19.07#ibcon#wrote, iclass 35, count 2 2006.201.08:33:19.07#ibcon#about to read 3, iclass 35, count 2 2006.201.08:33:19.10#ibcon#read 3, iclass 35, count 2 2006.201.08:33:19.10#ibcon#about to read 4, iclass 35, count 2 2006.201.08:33:19.10#ibcon#read 4, iclass 35, count 2 2006.201.08:33:19.10#ibcon#about to read 5, iclass 35, count 2 2006.201.08:33:19.10#ibcon#read 5, iclass 35, count 2 2006.201.08:33:19.10#ibcon#about to read 6, iclass 35, count 2 2006.201.08:33:19.10#ibcon#read 6, iclass 35, count 2 2006.201.08:33:19.10#ibcon#end of sib2, iclass 35, count 2 2006.201.08:33:19.10#ibcon#*after write, iclass 35, count 2 2006.201.08:33:19.10#ibcon#*before return 0, iclass 35, count 2 2006.201.08:33:19.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:19.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:33:19.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.08:33:19.10#ibcon#ireg 7 cls_cnt 0 2006.201.08:33:19.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:19.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:19.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:19.22#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:33:19.22#ibcon#first serial, iclass 35, count 0 2006.201.08:33:19.22#ibcon#enter sib2, iclass 35, count 0 2006.201.08:33:19.22#ibcon#flushed, iclass 35, count 0 2006.201.08:33:19.22#ibcon#about to write, iclass 35, count 0 2006.201.08:33:19.22#ibcon#wrote, iclass 35, count 0 2006.201.08:33:19.22#ibcon#about to read 3, iclass 35, count 0 2006.201.08:33:19.24#ibcon#read 3, iclass 35, count 0 2006.201.08:33:19.24#ibcon#about to read 4, iclass 35, count 0 2006.201.08:33:19.24#ibcon#read 4, iclass 35, count 0 2006.201.08:33:19.24#ibcon#about to read 5, iclass 35, count 0 2006.201.08:33:19.24#ibcon#read 5, iclass 35, count 0 2006.201.08:33:19.24#ibcon#about to read 6, iclass 35, count 0 2006.201.08:33:19.24#ibcon#read 6, iclass 35, count 0 2006.201.08:33:19.24#ibcon#end of sib2, iclass 35, count 0 2006.201.08:33:19.24#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:33:19.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:33:19.24#ibcon#[27=USB\r\n] 2006.201.08:33:19.24#ibcon#*before write, iclass 35, count 0 2006.201.08:33:19.24#ibcon#enter sib2, iclass 35, count 0 2006.201.08:33:19.24#ibcon#flushed, iclass 35, count 0 2006.201.08:33:19.24#ibcon#about to write, iclass 35, count 0 2006.201.08:33:19.24#ibcon#wrote, iclass 35, count 0 2006.201.08:33:19.24#ibcon#about to read 3, iclass 35, count 0 2006.201.08:33:19.27#ibcon#read 3, iclass 35, count 0 2006.201.08:33:19.27#ibcon#about to read 4, iclass 35, count 0 2006.201.08:33:19.27#ibcon#read 4, iclass 35, count 0 2006.201.08:33:19.27#ibcon#about to read 5, iclass 35, count 0 2006.201.08:33:19.27#ibcon#read 5, iclass 35, count 0 2006.201.08:33:19.27#ibcon#about to read 6, iclass 35, count 0 2006.201.08:33:19.27#ibcon#read 6, iclass 35, count 0 2006.201.08:33:19.27#ibcon#end of sib2, iclass 35, count 0 2006.201.08:33:19.27#ibcon#*after write, iclass 35, count 0 2006.201.08:33:19.27#ibcon#*before return 0, iclass 35, count 0 2006.201.08:33:19.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:19.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:33:19.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:33:19.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:33:19.27$vck44/vabw=wide 2006.201.08:33:19.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.08:33:19.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.08:33:19.27#ibcon#ireg 8 cls_cnt 0 2006.201.08:33:19.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:19.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:19.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:19.27#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:33:19.27#ibcon#first serial, iclass 37, count 0 2006.201.08:33:19.27#ibcon#enter sib2, iclass 37, count 0 2006.201.08:33:19.27#ibcon#flushed, iclass 37, count 0 2006.201.08:33:19.27#ibcon#about to write, iclass 37, count 0 2006.201.08:33:19.27#ibcon#wrote, iclass 37, count 0 2006.201.08:33:19.27#ibcon#about to read 3, iclass 37, count 0 2006.201.08:33:19.29#ibcon#read 3, iclass 37, count 0 2006.201.08:33:19.29#ibcon#about to read 4, iclass 37, count 0 2006.201.08:33:19.29#ibcon#read 4, iclass 37, count 0 2006.201.08:33:19.29#ibcon#about to read 5, iclass 37, count 0 2006.201.08:33:19.29#ibcon#read 5, iclass 37, count 0 2006.201.08:33:19.29#ibcon#about to read 6, iclass 37, count 0 2006.201.08:33:19.29#ibcon#read 6, iclass 37, count 0 2006.201.08:33:19.29#ibcon#end of sib2, iclass 37, count 0 2006.201.08:33:19.29#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:33:19.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:33:19.29#ibcon#[25=BW32\r\n] 2006.201.08:33:19.29#ibcon#*before write, iclass 37, count 0 2006.201.08:33:19.29#ibcon#enter sib2, iclass 37, count 0 2006.201.08:33:19.29#ibcon#flushed, iclass 37, count 0 2006.201.08:33:19.29#ibcon#about to write, iclass 37, count 0 2006.201.08:33:19.29#ibcon#wrote, iclass 37, count 0 2006.201.08:33:19.29#ibcon#about to read 3, iclass 37, count 0 2006.201.08:33:19.32#ibcon#read 3, iclass 37, count 0 2006.201.08:33:19.32#ibcon#about to read 4, iclass 37, count 0 2006.201.08:33:19.32#ibcon#read 4, iclass 37, count 0 2006.201.08:33:19.32#ibcon#about to read 5, iclass 37, count 0 2006.201.08:33:19.32#ibcon#read 5, iclass 37, count 0 2006.201.08:33:19.32#ibcon#about to read 6, iclass 37, count 0 2006.201.08:33:19.32#ibcon#read 6, iclass 37, count 0 2006.201.08:33:19.32#ibcon#end of sib2, iclass 37, count 0 2006.201.08:33:19.32#ibcon#*after write, iclass 37, count 0 2006.201.08:33:19.32#ibcon#*before return 0, iclass 37, count 0 2006.201.08:33:19.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:19.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:33:19.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:33:19.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:33:19.32$vck44/vbbw=wide 2006.201.08:33:19.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.08:33:19.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.08:33:19.32#ibcon#ireg 8 cls_cnt 0 2006.201.08:33:19.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:33:19.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:33:19.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:33:19.39#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:33:19.39#ibcon#first serial, iclass 39, count 0 2006.201.08:33:19.39#ibcon#enter sib2, iclass 39, count 0 2006.201.08:33:19.39#ibcon#flushed, iclass 39, count 0 2006.201.08:33:19.39#ibcon#about to write, iclass 39, count 0 2006.201.08:33:19.39#ibcon#wrote, iclass 39, count 0 2006.201.08:33:19.39#ibcon#about to read 3, iclass 39, count 0 2006.201.08:33:19.41#ibcon#read 3, iclass 39, count 0 2006.201.08:33:19.41#ibcon#about to read 4, iclass 39, count 0 2006.201.08:33:19.41#ibcon#read 4, iclass 39, count 0 2006.201.08:33:19.41#ibcon#about to read 5, iclass 39, count 0 2006.201.08:33:19.41#ibcon#read 5, iclass 39, count 0 2006.201.08:33:19.41#ibcon#about to read 6, iclass 39, count 0 2006.201.08:33:19.41#ibcon#read 6, iclass 39, count 0 2006.201.08:33:19.41#ibcon#end of sib2, iclass 39, count 0 2006.201.08:33:19.41#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:33:19.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:33:19.41#ibcon#[27=BW32\r\n] 2006.201.08:33:19.41#ibcon#*before write, iclass 39, count 0 2006.201.08:33:19.41#ibcon#enter sib2, iclass 39, count 0 2006.201.08:33:19.41#ibcon#flushed, iclass 39, count 0 2006.201.08:33:19.41#ibcon#about to write, iclass 39, count 0 2006.201.08:33:19.41#ibcon#wrote, iclass 39, count 0 2006.201.08:33:19.41#ibcon#about to read 3, iclass 39, count 0 2006.201.08:33:19.44#ibcon#read 3, iclass 39, count 0 2006.201.08:33:19.44#ibcon#about to read 4, iclass 39, count 0 2006.201.08:33:19.44#ibcon#read 4, iclass 39, count 0 2006.201.08:33:19.44#ibcon#about to read 5, iclass 39, count 0 2006.201.08:33:19.44#ibcon#read 5, iclass 39, count 0 2006.201.08:33:19.44#ibcon#about to read 6, iclass 39, count 0 2006.201.08:33:19.44#ibcon#read 6, iclass 39, count 0 2006.201.08:33:19.44#ibcon#end of sib2, iclass 39, count 0 2006.201.08:33:19.44#ibcon#*after write, iclass 39, count 0 2006.201.08:33:19.44#ibcon#*before return 0, iclass 39, count 0 2006.201.08:33:19.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:33:19.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:33:19.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:33:19.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:33:19.44$setupk4/ifdk4 2006.201.08:33:19.44$ifdk4/lo= 2006.201.08:33:19.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:33:19.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:33:19.44$ifdk4/patch= 2006.201.08:33:19.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:33:19.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:33:19.44$setupk4/!*+20s 2006.201.08:33:24.10#abcon#<5=/04 2.8 4.6 23.16 881003.5\r\n> 2006.201.08:33:24.12#abcon#{5=INTERFACE CLEAR} 2006.201.08:33:24.18#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:33:33.92$setupk4/"tpicd 2006.201.08:33:33.92$setupk4/echo=off 2006.201.08:33:33.92$setupk4/xlog=off 2006.201.08:33:33.92:!2006.201.08:34:00 2006.201.08:33:45.14#trakl#Source acquired 2006.201.08:33:46.14#flagr#flagr/antenna,acquired 2006.201.08:34:00.00:preob 2006.201.08:34:00.13/onsource/TRACKING 2006.201.08:34:00.13:!2006.201.08:34:10 2006.201.08:34:10.00:"tape 2006.201.08:34:10.00:"st=record 2006.201.08:34:10.00:data_valid=on 2006.201.08:34:10.00:midob 2006.201.08:34:10.13/onsource/TRACKING 2006.201.08:34:10.13/wx/23.16,1003.5,88 2006.201.08:34:10.19/cable/+6.4679E-03 2006.201.08:34:11.28/va/01,08,usb,yes,49,53 2006.201.08:34:11.28/va/02,07,usb,yes,53,54 2006.201.08:34:11.28/va/03,08,usb,yes,48,50 2006.201.08:34:11.28/va/04,07,usb,yes,55,58 2006.201.08:34:11.28/va/05,04,usb,yes,49,50 2006.201.08:34:11.28/va/06,05,usb,yes,49,49 2006.201.08:34:11.28/va/07,05,usb,yes,48,49 2006.201.08:34:11.28/va/08,04,usb,yes,47,56 2006.201.08:34:11.51/valo/01,524.99,yes,locked 2006.201.08:34:11.51/valo/02,534.99,yes,locked 2006.201.08:34:11.51/valo/03,564.99,yes,locked 2006.201.08:34:11.51/valo/04,624.99,yes,locked 2006.201.08:34:11.51/valo/05,734.99,yes,locked 2006.201.08:34:11.51/valo/06,814.99,yes,locked 2006.201.08:34:11.51/valo/07,864.99,yes,locked 2006.201.08:34:11.51/valo/08,884.99,yes,locked 2006.201.08:34:12.60/vb/01,04,usb,yes,42,41 2006.201.08:34:12.60/vb/02,05,usb,yes,40,41 2006.201.08:34:12.60/vb/03,04,usb,yes,41,46 2006.201.08:34:12.60/vb/04,05,usb,yes,41,40 2006.201.08:34:12.60/vb/05,04,usb,yes,37,41 2006.201.08:34:12.60/vb/06,04,usb,yes,44,39 2006.201.08:34:12.60/vb/07,04,usb,yes,43,43 2006.201.08:34:12.60/vb/08,04,usb,yes,39,44 2006.201.08:34:12.84/vblo/01,629.99,yes,locked 2006.201.08:34:12.84/vblo/02,634.99,yes,locked 2006.201.08:34:12.84/vblo/03,649.99,yes,locked 2006.201.08:34:12.84/vblo/04,679.99,yes,locked 2006.201.08:34:12.84/vblo/05,709.99,yes,locked 2006.201.08:34:12.84/vblo/06,719.99,yes,locked 2006.201.08:34:12.84/vblo/07,734.99,yes,locked 2006.201.08:34:12.84/vblo/08,744.99,yes,locked 2006.201.08:34:12.99/vabw/8 2006.201.08:34:13.14/vbbw/8 2006.201.08:34:13.23/xfe/off,on,16.0 2006.201.08:34:13.61/ifatt/23,28,28,28 2006.201.08:34:14.05/fmout-gps/S +4.57E-07 2006.201.08:34:14.12:!2006.201.08:34:50 2006.201.08:34:50.00:data_valid=off 2006.201.08:34:50.00:"et 2006.201.08:34:50.00:!+3s 2006.201.08:34:53.02:"tape 2006.201.08:34:53.02:postob 2006.201.08:34:53.24/cable/+6.4671E-03 2006.201.08:34:53.24/wx/23.15,1003.5,89 2006.201.08:34:53.32/fmout-gps/S +4.58E-07 2006.201.08:34:53.32:scan_name=201-0836,jd0607,410 2006.201.08:34:53.32:source=1418+546,141946.60,542314.8,2000.0,cw 2006.201.08:34:55.13#flagr#flagr/antenna,new-source 2006.201.08:34:55.13:checkk5 2006.201.08:34:55.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:34:55.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:34:56.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:34:56.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:34:56.99/chk_obsdata//k5ts1/T2010834??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.08:34:57.36/chk_obsdata//k5ts2/T2010834??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.08:34:57.73/chk_obsdata//k5ts3/T2010834??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.08:34:58.10/chk_obsdata//k5ts4/T2010834??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.08:34:58.78/k5log//k5ts1_log_newline 2006.201.08:34:59.46/k5log//k5ts2_log_newline 2006.201.08:35:00.15/k5log//k5ts3_log_newline 2006.201.08:35:00.84/k5log//k5ts4_log_newline 2006.201.08:35:00.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:35:00.86:setupk4=1 2006.201.08:35:00.86$setupk4/echo=on 2006.201.08:35:00.86$setupk4/pcalon 2006.201.08:35:00.86$pcalon/"no phase cal control is implemented here 2006.201.08:35:00.86$setupk4/"tpicd=stop 2006.201.08:35:00.86$setupk4/"rec=synch_on 2006.201.08:35:00.86$setupk4/"rec_mode=128 2006.201.08:35:00.86$setupk4/!* 2006.201.08:35:00.86$setupk4/recpk4 2006.201.08:35:00.86$recpk4/recpatch= 2006.201.08:35:00.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:35:00.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:35:00.87$setupk4/vck44 2006.201.08:35:00.87$vck44/valo=1,524.99 2006.201.08:35:00.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.08:35:00.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.08:35:00.87#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:00.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:00.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:00.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:00.87#ibcon#enter wrdev, iclass 12, count 0 2006.201.08:35:00.87#ibcon#first serial, iclass 12, count 0 2006.201.08:35:00.87#ibcon#enter sib2, iclass 12, count 0 2006.201.08:35:00.87#ibcon#flushed, iclass 12, count 0 2006.201.08:35:00.87#ibcon#about to write, iclass 12, count 0 2006.201.08:35:00.87#ibcon#wrote, iclass 12, count 0 2006.201.08:35:00.87#ibcon#about to read 3, iclass 12, count 0 2006.201.08:35:00.90#ibcon#read 3, iclass 12, count 0 2006.201.08:35:00.90#ibcon#about to read 4, iclass 12, count 0 2006.201.08:35:00.90#ibcon#read 4, iclass 12, count 0 2006.201.08:35:00.90#ibcon#about to read 5, iclass 12, count 0 2006.201.08:35:00.90#ibcon#read 5, iclass 12, count 0 2006.201.08:35:00.90#ibcon#about to read 6, iclass 12, count 0 2006.201.08:35:00.90#ibcon#read 6, iclass 12, count 0 2006.201.08:35:00.90#ibcon#end of sib2, iclass 12, count 0 2006.201.08:35:00.90#ibcon#*mode == 0, iclass 12, count 0 2006.201.08:35:00.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.08:35:00.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:35:00.90#ibcon#*before write, iclass 12, count 0 2006.201.08:35:00.90#ibcon#enter sib2, iclass 12, count 0 2006.201.08:35:00.90#ibcon#flushed, iclass 12, count 0 2006.201.08:35:00.90#ibcon#about to write, iclass 12, count 0 2006.201.08:35:00.90#ibcon#wrote, iclass 12, count 0 2006.201.08:35:00.90#ibcon#about to read 3, iclass 12, count 0 2006.201.08:35:00.95#ibcon#read 3, iclass 12, count 0 2006.201.08:35:00.95#ibcon#about to read 4, iclass 12, count 0 2006.201.08:35:00.95#ibcon#read 4, iclass 12, count 0 2006.201.08:35:00.95#ibcon#about to read 5, iclass 12, count 0 2006.201.08:35:00.95#ibcon#read 5, iclass 12, count 0 2006.201.08:35:00.95#ibcon#about to read 6, iclass 12, count 0 2006.201.08:35:00.95#ibcon#read 6, iclass 12, count 0 2006.201.08:35:00.95#ibcon#end of sib2, iclass 12, count 0 2006.201.08:35:00.95#ibcon#*after write, iclass 12, count 0 2006.201.08:35:00.95#ibcon#*before return 0, iclass 12, count 0 2006.201.08:35:00.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:00.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:00.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.08:35:00.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.08:35:00.95$vck44/va=1,8 2006.201.08:35:00.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.08:35:00.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.08:35:00.95#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:00.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:00.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:00.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:00.95#ibcon#enter wrdev, iclass 14, count 2 2006.201.08:35:00.95#ibcon#first serial, iclass 14, count 2 2006.201.08:35:00.95#ibcon#enter sib2, iclass 14, count 2 2006.201.08:35:00.95#ibcon#flushed, iclass 14, count 2 2006.201.08:35:00.95#ibcon#about to write, iclass 14, count 2 2006.201.08:35:00.95#ibcon#wrote, iclass 14, count 2 2006.201.08:35:00.95#ibcon#about to read 3, iclass 14, count 2 2006.201.08:35:00.97#ibcon#read 3, iclass 14, count 2 2006.201.08:35:00.97#ibcon#about to read 4, iclass 14, count 2 2006.201.08:35:00.97#ibcon#read 4, iclass 14, count 2 2006.201.08:35:00.97#ibcon#about to read 5, iclass 14, count 2 2006.201.08:35:00.97#ibcon#read 5, iclass 14, count 2 2006.201.08:35:00.97#ibcon#about to read 6, iclass 14, count 2 2006.201.08:35:00.97#ibcon#read 6, iclass 14, count 2 2006.201.08:35:00.97#ibcon#end of sib2, iclass 14, count 2 2006.201.08:35:00.97#ibcon#*mode == 0, iclass 14, count 2 2006.201.08:35:00.97#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.08:35:00.97#ibcon#[25=AT01-08\r\n] 2006.201.08:35:00.97#ibcon#*before write, iclass 14, count 2 2006.201.08:35:00.97#ibcon#enter sib2, iclass 14, count 2 2006.201.08:35:00.97#ibcon#flushed, iclass 14, count 2 2006.201.08:35:00.97#ibcon#about to write, iclass 14, count 2 2006.201.08:35:00.97#ibcon#wrote, iclass 14, count 2 2006.201.08:35:00.97#ibcon#about to read 3, iclass 14, count 2 2006.201.08:35:01.00#ibcon#read 3, iclass 14, count 2 2006.201.08:35:01.00#ibcon#about to read 4, iclass 14, count 2 2006.201.08:35:01.00#ibcon#read 4, iclass 14, count 2 2006.201.08:35:01.00#ibcon#about to read 5, iclass 14, count 2 2006.201.08:35:01.00#ibcon#read 5, iclass 14, count 2 2006.201.08:35:01.00#ibcon#about to read 6, iclass 14, count 2 2006.201.08:35:01.00#ibcon#read 6, iclass 14, count 2 2006.201.08:35:01.00#ibcon#end of sib2, iclass 14, count 2 2006.201.08:35:01.00#ibcon#*after write, iclass 14, count 2 2006.201.08:35:01.00#ibcon#*before return 0, iclass 14, count 2 2006.201.08:35:01.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:01.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:01.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.08:35:01.00#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:01.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:01.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:01.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:01.12#ibcon#enter wrdev, iclass 14, count 0 2006.201.08:35:01.12#ibcon#first serial, iclass 14, count 0 2006.201.08:35:01.12#ibcon#enter sib2, iclass 14, count 0 2006.201.08:35:01.12#ibcon#flushed, iclass 14, count 0 2006.201.08:35:01.12#ibcon#about to write, iclass 14, count 0 2006.201.08:35:01.12#ibcon#wrote, iclass 14, count 0 2006.201.08:35:01.12#ibcon#about to read 3, iclass 14, count 0 2006.201.08:35:01.14#ibcon#read 3, iclass 14, count 0 2006.201.08:35:01.14#ibcon#about to read 4, iclass 14, count 0 2006.201.08:35:01.14#ibcon#read 4, iclass 14, count 0 2006.201.08:35:01.14#ibcon#about to read 5, iclass 14, count 0 2006.201.08:35:01.14#ibcon#read 5, iclass 14, count 0 2006.201.08:35:01.14#ibcon#about to read 6, iclass 14, count 0 2006.201.08:35:01.14#ibcon#read 6, iclass 14, count 0 2006.201.08:35:01.14#ibcon#end of sib2, iclass 14, count 0 2006.201.08:35:01.14#ibcon#*mode == 0, iclass 14, count 0 2006.201.08:35:01.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.08:35:01.14#ibcon#[25=USB\r\n] 2006.201.08:35:01.14#ibcon#*before write, iclass 14, count 0 2006.201.08:35:01.14#ibcon#enter sib2, iclass 14, count 0 2006.201.08:35:01.14#ibcon#flushed, iclass 14, count 0 2006.201.08:35:01.14#ibcon#about to write, iclass 14, count 0 2006.201.08:35:01.14#ibcon#wrote, iclass 14, count 0 2006.201.08:35:01.14#ibcon#about to read 3, iclass 14, count 0 2006.201.08:35:01.17#ibcon#read 3, iclass 14, count 0 2006.201.08:35:01.17#ibcon#about to read 4, iclass 14, count 0 2006.201.08:35:01.17#ibcon#read 4, iclass 14, count 0 2006.201.08:35:01.17#ibcon#about to read 5, iclass 14, count 0 2006.201.08:35:01.17#ibcon#read 5, iclass 14, count 0 2006.201.08:35:01.17#ibcon#about to read 6, iclass 14, count 0 2006.201.08:35:01.17#ibcon#read 6, iclass 14, count 0 2006.201.08:35:01.17#ibcon#end of sib2, iclass 14, count 0 2006.201.08:35:01.17#ibcon#*after write, iclass 14, count 0 2006.201.08:35:01.17#ibcon#*before return 0, iclass 14, count 0 2006.201.08:35:01.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:01.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:01.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.08:35:01.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.08:35:01.17$vck44/valo=2,534.99 2006.201.08:35:01.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.08:35:01.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.08:35:01.17#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:01.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:01.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:01.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:01.17#ibcon#enter wrdev, iclass 16, count 0 2006.201.08:35:01.17#ibcon#first serial, iclass 16, count 0 2006.201.08:35:01.17#ibcon#enter sib2, iclass 16, count 0 2006.201.08:35:01.17#ibcon#flushed, iclass 16, count 0 2006.201.08:35:01.17#ibcon#about to write, iclass 16, count 0 2006.201.08:35:01.17#ibcon#wrote, iclass 16, count 0 2006.201.08:35:01.17#ibcon#about to read 3, iclass 16, count 0 2006.201.08:35:01.19#ibcon#read 3, iclass 16, count 0 2006.201.08:35:01.19#ibcon#about to read 4, iclass 16, count 0 2006.201.08:35:01.19#ibcon#read 4, iclass 16, count 0 2006.201.08:35:01.19#ibcon#about to read 5, iclass 16, count 0 2006.201.08:35:01.19#ibcon#read 5, iclass 16, count 0 2006.201.08:35:01.19#ibcon#about to read 6, iclass 16, count 0 2006.201.08:35:01.19#ibcon#read 6, iclass 16, count 0 2006.201.08:35:01.19#ibcon#end of sib2, iclass 16, count 0 2006.201.08:35:01.19#ibcon#*mode == 0, iclass 16, count 0 2006.201.08:35:01.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.08:35:01.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:35:01.19#ibcon#*before write, iclass 16, count 0 2006.201.08:35:01.19#ibcon#enter sib2, iclass 16, count 0 2006.201.08:35:01.19#ibcon#flushed, iclass 16, count 0 2006.201.08:35:01.19#ibcon#about to write, iclass 16, count 0 2006.201.08:35:01.19#ibcon#wrote, iclass 16, count 0 2006.201.08:35:01.19#ibcon#about to read 3, iclass 16, count 0 2006.201.08:35:01.24#ibcon#read 3, iclass 16, count 0 2006.201.08:35:01.24#ibcon#about to read 4, iclass 16, count 0 2006.201.08:35:01.24#ibcon#read 4, iclass 16, count 0 2006.201.08:35:01.24#ibcon#about to read 5, iclass 16, count 0 2006.201.08:35:01.24#ibcon#read 5, iclass 16, count 0 2006.201.08:35:01.24#ibcon#about to read 6, iclass 16, count 0 2006.201.08:35:01.24#ibcon#read 6, iclass 16, count 0 2006.201.08:35:01.24#ibcon#end of sib2, iclass 16, count 0 2006.201.08:35:01.24#ibcon#*after write, iclass 16, count 0 2006.201.08:35:01.24#ibcon#*before return 0, iclass 16, count 0 2006.201.08:35:01.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:01.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:01.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.08:35:01.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.08:35:01.24$vck44/va=2,7 2006.201.08:35:01.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.08:35:01.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.08:35:01.24#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:01.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:01.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:01.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:01.29#ibcon#enter wrdev, iclass 18, count 2 2006.201.08:35:01.29#ibcon#first serial, iclass 18, count 2 2006.201.08:35:01.29#ibcon#enter sib2, iclass 18, count 2 2006.201.08:35:01.29#ibcon#flushed, iclass 18, count 2 2006.201.08:35:01.29#ibcon#about to write, iclass 18, count 2 2006.201.08:35:01.29#ibcon#wrote, iclass 18, count 2 2006.201.08:35:01.29#ibcon#about to read 3, iclass 18, count 2 2006.201.08:35:01.31#ibcon#read 3, iclass 18, count 2 2006.201.08:35:01.31#ibcon#about to read 4, iclass 18, count 2 2006.201.08:35:01.31#ibcon#read 4, iclass 18, count 2 2006.201.08:35:01.31#ibcon#about to read 5, iclass 18, count 2 2006.201.08:35:01.31#ibcon#read 5, iclass 18, count 2 2006.201.08:35:01.31#ibcon#about to read 6, iclass 18, count 2 2006.201.08:35:01.31#ibcon#read 6, iclass 18, count 2 2006.201.08:35:01.31#ibcon#end of sib2, iclass 18, count 2 2006.201.08:35:01.31#ibcon#*mode == 0, iclass 18, count 2 2006.201.08:35:01.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.08:35:01.31#ibcon#[25=AT02-07\r\n] 2006.201.08:35:01.31#ibcon#*before write, iclass 18, count 2 2006.201.08:35:01.31#ibcon#enter sib2, iclass 18, count 2 2006.201.08:35:01.31#ibcon#flushed, iclass 18, count 2 2006.201.08:35:01.31#ibcon#about to write, iclass 18, count 2 2006.201.08:35:01.31#ibcon#wrote, iclass 18, count 2 2006.201.08:35:01.31#ibcon#about to read 3, iclass 18, count 2 2006.201.08:35:01.34#ibcon#read 3, iclass 18, count 2 2006.201.08:35:01.34#ibcon#about to read 4, iclass 18, count 2 2006.201.08:35:01.34#ibcon#read 4, iclass 18, count 2 2006.201.08:35:01.34#ibcon#about to read 5, iclass 18, count 2 2006.201.08:35:01.34#ibcon#read 5, iclass 18, count 2 2006.201.08:35:01.34#ibcon#about to read 6, iclass 18, count 2 2006.201.08:35:01.34#ibcon#read 6, iclass 18, count 2 2006.201.08:35:01.34#ibcon#end of sib2, iclass 18, count 2 2006.201.08:35:01.34#ibcon#*after write, iclass 18, count 2 2006.201.08:35:01.34#ibcon#*before return 0, iclass 18, count 2 2006.201.08:35:01.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:01.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:01.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.08:35:01.34#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:01.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:01.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:01.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:01.46#ibcon#enter wrdev, iclass 18, count 0 2006.201.08:35:01.46#ibcon#first serial, iclass 18, count 0 2006.201.08:35:01.46#ibcon#enter sib2, iclass 18, count 0 2006.201.08:35:01.46#ibcon#flushed, iclass 18, count 0 2006.201.08:35:01.46#ibcon#about to write, iclass 18, count 0 2006.201.08:35:01.46#ibcon#wrote, iclass 18, count 0 2006.201.08:35:01.46#ibcon#about to read 3, iclass 18, count 0 2006.201.08:35:01.48#ibcon#read 3, iclass 18, count 0 2006.201.08:35:01.48#ibcon#about to read 4, iclass 18, count 0 2006.201.08:35:01.48#ibcon#read 4, iclass 18, count 0 2006.201.08:35:01.48#ibcon#about to read 5, iclass 18, count 0 2006.201.08:35:01.48#ibcon#read 5, iclass 18, count 0 2006.201.08:35:01.48#ibcon#about to read 6, iclass 18, count 0 2006.201.08:35:01.48#ibcon#read 6, iclass 18, count 0 2006.201.08:35:01.48#ibcon#end of sib2, iclass 18, count 0 2006.201.08:35:01.48#ibcon#*mode == 0, iclass 18, count 0 2006.201.08:35:01.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.08:35:01.48#ibcon#[25=USB\r\n] 2006.201.08:35:01.48#ibcon#*before write, iclass 18, count 0 2006.201.08:35:01.48#ibcon#enter sib2, iclass 18, count 0 2006.201.08:35:01.48#ibcon#flushed, iclass 18, count 0 2006.201.08:35:01.48#ibcon#about to write, iclass 18, count 0 2006.201.08:35:01.48#ibcon#wrote, iclass 18, count 0 2006.201.08:35:01.48#ibcon#about to read 3, iclass 18, count 0 2006.201.08:35:01.51#ibcon#read 3, iclass 18, count 0 2006.201.08:35:01.51#ibcon#about to read 4, iclass 18, count 0 2006.201.08:35:01.51#ibcon#read 4, iclass 18, count 0 2006.201.08:35:01.51#ibcon#about to read 5, iclass 18, count 0 2006.201.08:35:01.51#ibcon#read 5, iclass 18, count 0 2006.201.08:35:01.51#ibcon#about to read 6, iclass 18, count 0 2006.201.08:35:01.51#ibcon#read 6, iclass 18, count 0 2006.201.08:35:01.51#ibcon#end of sib2, iclass 18, count 0 2006.201.08:35:01.51#ibcon#*after write, iclass 18, count 0 2006.201.08:35:01.51#ibcon#*before return 0, iclass 18, count 0 2006.201.08:35:01.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:01.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:01.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.08:35:01.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.08:35:01.51$vck44/valo=3,564.99 2006.201.08:35:01.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.08:35:01.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.08:35:01.51#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:01.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:01.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:01.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:01.51#ibcon#enter wrdev, iclass 20, count 0 2006.201.08:35:01.51#ibcon#first serial, iclass 20, count 0 2006.201.08:35:01.51#ibcon#enter sib2, iclass 20, count 0 2006.201.08:35:01.51#ibcon#flushed, iclass 20, count 0 2006.201.08:35:01.51#ibcon#about to write, iclass 20, count 0 2006.201.08:35:01.51#ibcon#wrote, iclass 20, count 0 2006.201.08:35:01.51#ibcon#about to read 3, iclass 20, count 0 2006.201.08:35:01.53#ibcon#read 3, iclass 20, count 0 2006.201.08:35:01.53#ibcon#about to read 4, iclass 20, count 0 2006.201.08:35:01.53#ibcon#read 4, iclass 20, count 0 2006.201.08:35:01.53#ibcon#about to read 5, iclass 20, count 0 2006.201.08:35:01.53#ibcon#read 5, iclass 20, count 0 2006.201.08:35:01.53#ibcon#about to read 6, iclass 20, count 0 2006.201.08:35:01.53#ibcon#read 6, iclass 20, count 0 2006.201.08:35:01.53#ibcon#end of sib2, iclass 20, count 0 2006.201.08:35:01.53#ibcon#*mode == 0, iclass 20, count 0 2006.201.08:35:01.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.08:35:01.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:35:01.53#ibcon#*before write, iclass 20, count 0 2006.201.08:35:01.53#ibcon#enter sib2, iclass 20, count 0 2006.201.08:35:01.53#ibcon#flushed, iclass 20, count 0 2006.201.08:35:01.53#ibcon#about to write, iclass 20, count 0 2006.201.08:35:01.53#ibcon#wrote, iclass 20, count 0 2006.201.08:35:01.53#ibcon#about to read 3, iclass 20, count 0 2006.201.08:35:01.58#ibcon#read 3, iclass 20, count 0 2006.201.08:35:01.58#ibcon#about to read 4, iclass 20, count 0 2006.201.08:35:01.58#ibcon#read 4, iclass 20, count 0 2006.201.08:35:01.58#ibcon#about to read 5, iclass 20, count 0 2006.201.08:35:01.58#ibcon#read 5, iclass 20, count 0 2006.201.08:35:01.58#ibcon#about to read 6, iclass 20, count 0 2006.201.08:35:01.58#ibcon#read 6, iclass 20, count 0 2006.201.08:35:01.58#ibcon#end of sib2, iclass 20, count 0 2006.201.08:35:01.58#ibcon#*after write, iclass 20, count 0 2006.201.08:35:01.58#ibcon#*before return 0, iclass 20, count 0 2006.201.08:35:01.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:01.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:01.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.08:35:01.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.08:35:01.58$vck44/va=3,8 2006.201.08:35:01.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.08:35:01.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.08:35:01.58#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:01.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:01.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:01.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:01.63#ibcon#enter wrdev, iclass 22, count 2 2006.201.08:35:01.63#ibcon#first serial, iclass 22, count 2 2006.201.08:35:01.63#ibcon#enter sib2, iclass 22, count 2 2006.201.08:35:01.63#ibcon#flushed, iclass 22, count 2 2006.201.08:35:01.63#ibcon#about to write, iclass 22, count 2 2006.201.08:35:01.63#ibcon#wrote, iclass 22, count 2 2006.201.08:35:01.63#ibcon#about to read 3, iclass 22, count 2 2006.201.08:35:01.65#ibcon#read 3, iclass 22, count 2 2006.201.08:35:01.65#ibcon#about to read 4, iclass 22, count 2 2006.201.08:35:01.65#ibcon#read 4, iclass 22, count 2 2006.201.08:35:01.65#ibcon#about to read 5, iclass 22, count 2 2006.201.08:35:01.65#ibcon#read 5, iclass 22, count 2 2006.201.08:35:01.65#ibcon#about to read 6, iclass 22, count 2 2006.201.08:35:01.65#ibcon#read 6, iclass 22, count 2 2006.201.08:35:01.65#ibcon#end of sib2, iclass 22, count 2 2006.201.08:35:01.65#ibcon#*mode == 0, iclass 22, count 2 2006.201.08:35:01.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.08:35:01.65#ibcon#[25=AT03-08\r\n] 2006.201.08:35:01.65#ibcon#*before write, iclass 22, count 2 2006.201.08:35:01.65#ibcon#enter sib2, iclass 22, count 2 2006.201.08:35:01.65#ibcon#flushed, iclass 22, count 2 2006.201.08:35:01.65#ibcon#about to write, iclass 22, count 2 2006.201.08:35:01.65#ibcon#wrote, iclass 22, count 2 2006.201.08:35:01.65#ibcon#about to read 3, iclass 22, count 2 2006.201.08:35:01.68#ibcon#read 3, iclass 22, count 2 2006.201.08:35:01.68#ibcon#about to read 4, iclass 22, count 2 2006.201.08:35:01.68#ibcon#read 4, iclass 22, count 2 2006.201.08:35:01.68#ibcon#about to read 5, iclass 22, count 2 2006.201.08:35:01.68#ibcon#read 5, iclass 22, count 2 2006.201.08:35:01.68#ibcon#about to read 6, iclass 22, count 2 2006.201.08:35:01.68#ibcon#read 6, iclass 22, count 2 2006.201.08:35:01.68#ibcon#end of sib2, iclass 22, count 2 2006.201.08:35:01.68#ibcon#*after write, iclass 22, count 2 2006.201.08:35:01.68#ibcon#*before return 0, iclass 22, count 2 2006.201.08:35:01.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:01.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:01.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.08:35:01.68#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:01.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:01.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:01.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:01.80#ibcon#enter wrdev, iclass 22, count 0 2006.201.08:35:01.80#ibcon#first serial, iclass 22, count 0 2006.201.08:35:01.80#ibcon#enter sib2, iclass 22, count 0 2006.201.08:35:01.80#ibcon#flushed, iclass 22, count 0 2006.201.08:35:01.80#ibcon#about to write, iclass 22, count 0 2006.201.08:35:01.80#ibcon#wrote, iclass 22, count 0 2006.201.08:35:01.80#ibcon#about to read 3, iclass 22, count 0 2006.201.08:35:01.82#ibcon#read 3, iclass 22, count 0 2006.201.08:35:01.82#ibcon#about to read 4, iclass 22, count 0 2006.201.08:35:01.82#ibcon#read 4, iclass 22, count 0 2006.201.08:35:01.82#ibcon#about to read 5, iclass 22, count 0 2006.201.08:35:01.82#ibcon#read 5, iclass 22, count 0 2006.201.08:35:01.82#ibcon#about to read 6, iclass 22, count 0 2006.201.08:35:01.82#ibcon#read 6, iclass 22, count 0 2006.201.08:35:01.82#ibcon#end of sib2, iclass 22, count 0 2006.201.08:35:01.82#ibcon#*mode == 0, iclass 22, count 0 2006.201.08:35:01.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.08:35:01.82#ibcon#[25=USB\r\n] 2006.201.08:35:01.82#ibcon#*before write, iclass 22, count 0 2006.201.08:35:01.82#ibcon#enter sib2, iclass 22, count 0 2006.201.08:35:01.82#ibcon#flushed, iclass 22, count 0 2006.201.08:35:01.82#ibcon#about to write, iclass 22, count 0 2006.201.08:35:01.82#ibcon#wrote, iclass 22, count 0 2006.201.08:35:01.82#ibcon#about to read 3, iclass 22, count 0 2006.201.08:35:01.85#ibcon#read 3, iclass 22, count 0 2006.201.08:35:01.85#ibcon#about to read 4, iclass 22, count 0 2006.201.08:35:01.85#ibcon#read 4, iclass 22, count 0 2006.201.08:35:01.85#ibcon#about to read 5, iclass 22, count 0 2006.201.08:35:01.85#ibcon#read 5, iclass 22, count 0 2006.201.08:35:01.85#ibcon#about to read 6, iclass 22, count 0 2006.201.08:35:01.85#ibcon#read 6, iclass 22, count 0 2006.201.08:35:01.85#ibcon#end of sib2, iclass 22, count 0 2006.201.08:35:01.85#ibcon#*after write, iclass 22, count 0 2006.201.08:35:01.85#ibcon#*before return 0, iclass 22, count 0 2006.201.08:35:01.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:01.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:01.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.08:35:01.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.08:35:01.85$vck44/valo=4,624.99 2006.201.08:35:01.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.08:35:01.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.08:35:01.85#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:01.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:01.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:01.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:01.85#ibcon#enter wrdev, iclass 24, count 0 2006.201.08:35:01.85#ibcon#first serial, iclass 24, count 0 2006.201.08:35:01.85#ibcon#enter sib2, iclass 24, count 0 2006.201.08:35:01.85#ibcon#flushed, iclass 24, count 0 2006.201.08:35:01.85#ibcon#about to write, iclass 24, count 0 2006.201.08:35:01.85#ibcon#wrote, iclass 24, count 0 2006.201.08:35:01.85#ibcon#about to read 3, iclass 24, count 0 2006.201.08:35:01.87#ibcon#read 3, iclass 24, count 0 2006.201.08:35:01.87#ibcon#about to read 4, iclass 24, count 0 2006.201.08:35:01.87#ibcon#read 4, iclass 24, count 0 2006.201.08:35:01.87#ibcon#about to read 5, iclass 24, count 0 2006.201.08:35:01.87#ibcon#read 5, iclass 24, count 0 2006.201.08:35:01.87#ibcon#about to read 6, iclass 24, count 0 2006.201.08:35:01.87#ibcon#read 6, iclass 24, count 0 2006.201.08:35:01.87#ibcon#end of sib2, iclass 24, count 0 2006.201.08:35:01.87#ibcon#*mode == 0, iclass 24, count 0 2006.201.08:35:01.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.08:35:01.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:35:01.87#ibcon#*before write, iclass 24, count 0 2006.201.08:35:01.87#ibcon#enter sib2, iclass 24, count 0 2006.201.08:35:01.87#ibcon#flushed, iclass 24, count 0 2006.201.08:35:01.87#ibcon#about to write, iclass 24, count 0 2006.201.08:35:01.87#ibcon#wrote, iclass 24, count 0 2006.201.08:35:01.87#ibcon#about to read 3, iclass 24, count 0 2006.201.08:35:01.92#ibcon#read 3, iclass 24, count 0 2006.201.08:35:01.92#ibcon#about to read 4, iclass 24, count 0 2006.201.08:35:01.92#ibcon#read 4, iclass 24, count 0 2006.201.08:35:01.92#ibcon#about to read 5, iclass 24, count 0 2006.201.08:35:01.92#ibcon#read 5, iclass 24, count 0 2006.201.08:35:01.92#ibcon#about to read 6, iclass 24, count 0 2006.201.08:35:01.92#ibcon#read 6, iclass 24, count 0 2006.201.08:35:01.92#ibcon#end of sib2, iclass 24, count 0 2006.201.08:35:01.92#ibcon#*after write, iclass 24, count 0 2006.201.08:35:01.92#ibcon#*before return 0, iclass 24, count 0 2006.201.08:35:01.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:01.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:01.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.08:35:01.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.08:35:01.92$vck44/va=4,7 2006.201.08:35:01.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.08:35:01.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.08:35:01.92#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:01.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:01.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:01.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:01.97#ibcon#enter wrdev, iclass 26, count 2 2006.201.08:35:01.97#ibcon#first serial, iclass 26, count 2 2006.201.08:35:01.97#ibcon#enter sib2, iclass 26, count 2 2006.201.08:35:01.97#ibcon#flushed, iclass 26, count 2 2006.201.08:35:01.97#ibcon#about to write, iclass 26, count 2 2006.201.08:35:01.97#ibcon#wrote, iclass 26, count 2 2006.201.08:35:01.97#ibcon#about to read 3, iclass 26, count 2 2006.201.08:35:01.99#ibcon#read 3, iclass 26, count 2 2006.201.08:35:01.99#ibcon#about to read 4, iclass 26, count 2 2006.201.08:35:01.99#ibcon#read 4, iclass 26, count 2 2006.201.08:35:01.99#ibcon#about to read 5, iclass 26, count 2 2006.201.08:35:01.99#ibcon#read 5, iclass 26, count 2 2006.201.08:35:01.99#ibcon#about to read 6, iclass 26, count 2 2006.201.08:35:01.99#ibcon#read 6, iclass 26, count 2 2006.201.08:35:01.99#ibcon#end of sib2, iclass 26, count 2 2006.201.08:35:01.99#ibcon#*mode == 0, iclass 26, count 2 2006.201.08:35:01.99#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.08:35:01.99#ibcon#[25=AT04-07\r\n] 2006.201.08:35:01.99#ibcon#*before write, iclass 26, count 2 2006.201.08:35:01.99#ibcon#enter sib2, iclass 26, count 2 2006.201.08:35:01.99#ibcon#flushed, iclass 26, count 2 2006.201.08:35:01.99#ibcon#about to write, iclass 26, count 2 2006.201.08:35:01.99#ibcon#wrote, iclass 26, count 2 2006.201.08:35:01.99#ibcon#about to read 3, iclass 26, count 2 2006.201.08:35:02.02#ibcon#read 3, iclass 26, count 2 2006.201.08:35:02.02#ibcon#about to read 4, iclass 26, count 2 2006.201.08:35:02.02#ibcon#read 4, iclass 26, count 2 2006.201.08:35:02.02#ibcon#about to read 5, iclass 26, count 2 2006.201.08:35:02.02#ibcon#read 5, iclass 26, count 2 2006.201.08:35:02.02#ibcon#about to read 6, iclass 26, count 2 2006.201.08:35:02.02#ibcon#read 6, iclass 26, count 2 2006.201.08:35:02.02#ibcon#end of sib2, iclass 26, count 2 2006.201.08:35:02.02#ibcon#*after write, iclass 26, count 2 2006.201.08:35:02.02#ibcon#*before return 0, iclass 26, count 2 2006.201.08:35:02.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:02.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:02.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.08:35:02.02#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:02.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:02.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:02.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:02.14#ibcon#enter wrdev, iclass 26, count 0 2006.201.08:35:02.14#ibcon#first serial, iclass 26, count 0 2006.201.08:35:02.14#ibcon#enter sib2, iclass 26, count 0 2006.201.08:35:02.14#ibcon#flushed, iclass 26, count 0 2006.201.08:35:02.14#ibcon#about to write, iclass 26, count 0 2006.201.08:35:02.14#ibcon#wrote, iclass 26, count 0 2006.201.08:35:02.14#ibcon#about to read 3, iclass 26, count 0 2006.201.08:35:02.16#ibcon#read 3, iclass 26, count 0 2006.201.08:35:02.16#ibcon#about to read 4, iclass 26, count 0 2006.201.08:35:02.16#ibcon#read 4, iclass 26, count 0 2006.201.08:35:02.16#ibcon#about to read 5, iclass 26, count 0 2006.201.08:35:02.16#ibcon#read 5, iclass 26, count 0 2006.201.08:35:02.16#ibcon#about to read 6, iclass 26, count 0 2006.201.08:35:02.16#ibcon#read 6, iclass 26, count 0 2006.201.08:35:02.16#ibcon#end of sib2, iclass 26, count 0 2006.201.08:35:02.16#ibcon#*mode == 0, iclass 26, count 0 2006.201.08:35:02.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.08:35:02.16#ibcon#[25=USB\r\n] 2006.201.08:35:02.16#ibcon#*before write, iclass 26, count 0 2006.201.08:35:02.16#ibcon#enter sib2, iclass 26, count 0 2006.201.08:35:02.16#ibcon#flushed, iclass 26, count 0 2006.201.08:35:02.16#ibcon#about to write, iclass 26, count 0 2006.201.08:35:02.16#ibcon#wrote, iclass 26, count 0 2006.201.08:35:02.16#ibcon#about to read 3, iclass 26, count 0 2006.201.08:35:02.19#ibcon#read 3, iclass 26, count 0 2006.201.08:35:02.19#ibcon#about to read 4, iclass 26, count 0 2006.201.08:35:02.19#ibcon#read 4, iclass 26, count 0 2006.201.08:35:02.19#ibcon#about to read 5, iclass 26, count 0 2006.201.08:35:02.19#ibcon#read 5, iclass 26, count 0 2006.201.08:35:02.19#ibcon#about to read 6, iclass 26, count 0 2006.201.08:35:02.19#ibcon#read 6, iclass 26, count 0 2006.201.08:35:02.19#ibcon#end of sib2, iclass 26, count 0 2006.201.08:35:02.19#ibcon#*after write, iclass 26, count 0 2006.201.08:35:02.19#ibcon#*before return 0, iclass 26, count 0 2006.201.08:35:02.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:02.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:02.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.08:35:02.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.08:35:02.19$vck44/valo=5,734.99 2006.201.08:35:02.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.08:35:02.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.08:35:02.19#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:02.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:02.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:02.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:02.19#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:35:02.19#ibcon#first serial, iclass 28, count 0 2006.201.08:35:02.19#ibcon#enter sib2, iclass 28, count 0 2006.201.08:35:02.19#ibcon#flushed, iclass 28, count 0 2006.201.08:35:02.19#ibcon#about to write, iclass 28, count 0 2006.201.08:35:02.19#ibcon#wrote, iclass 28, count 0 2006.201.08:35:02.19#ibcon#about to read 3, iclass 28, count 0 2006.201.08:35:02.21#ibcon#read 3, iclass 28, count 0 2006.201.08:35:02.21#ibcon#about to read 4, iclass 28, count 0 2006.201.08:35:02.21#ibcon#read 4, iclass 28, count 0 2006.201.08:35:02.21#ibcon#about to read 5, iclass 28, count 0 2006.201.08:35:02.21#ibcon#read 5, iclass 28, count 0 2006.201.08:35:02.21#ibcon#about to read 6, iclass 28, count 0 2006.201.08:35:02.21#ibcon#read 6, iclass 28, count 0 2006.201.08:35:02.21#ibcon#end of sib2, iclass 28, count 0 2006.201.08:35:02.21#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:35:02.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:35:02.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:35:02.21#ibcon#*before write, iclass 28, count 0 2006.201.08:35:02.21#ibcon#enter sib2, iclass 28, count 0 2006.201.08:35:02.21#ibcon#flushed, iclass 28, count 0 2006.201.08:35:02.21#ibcon#about to write, iclass 28, count 0 2006.201.08:35:02.21#ibcon#wrote, iclass 28, count 0 2006.201.08:35:02.21#ibcon#about to read 3, iclass 28, count 0 2006.201.08:35:02.25#ibcon#read 3, iclass 28, count 0 2006.201.08:35:02.25#ibcon#about to read 4, iclass 28, count 0 2006.201.08:35:02.25#ibcon#read 4, iclass 28, count 0 2006.201.08:35:02.25#ibcon#about to read 5, iclass 28, count 0 2006.201.08:35:02.25#ibcon#read 5, iclass 28, count 0 2006.201.08:35:02.25#ibcon#about to read 6, iclass 28, count 0 2006.201.08:35:02.25#ibcon#read 6, iclass 28, count 0 2006.201.08:35:02.25#ibcon#end of sib2, iclass 28, count 0 2006.201.08:35:02.25#ibcon#*after write, iclass 28, count 0 2006.201.08:35:02.25#ibcon#*before return 0, iclass 28, count 0 2006.201.08:35:02.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:02.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:02.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:35:02.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:35:02.25$vck44/va=5,4 2006.201.08:35:02.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.08:35:02.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.08:35:02.25#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:02.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:02.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:02.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:02.31#ibcon#enter wrdev, iclass 30, count 2 2006.201.08:35:02.31#ibcon#first serial, iclass 30, count 2 2006.201.08:35:02.31#ibcon#enter sib2, iclass 30, count 2 2006.201.08:35:02.31#ibcon#flushed, iclass 30, count 2 2006.201.08:35:02.31#ibcon#about to write, iclass 30, count 2 2006.201.08:35:02.31#ibcon#wrote, iclass 30, count 2 2006.201.08:35:02.31#ibcon#about to read 3, iclass 30, count 2 2006.201.08:35:02.33#ibcon#read 3, iclass 30, count 2 2006.201.08:35:02.33#ibcon#about to read 4, iclass 30, count 2 2006.201.08:35:02.33#ibcon#read 4, iclass 30, count 2 2006.201.08:35:02.33#ibcon#about to read 5, iclass 30, count 2 2006.201.08:35:02.33#ibcon#read 5, iclass 30, count 2 2006.201.08:35:02.33#ibcon#about to read 6, iclass 30, count 2 2006.201.08:35:02.33#ibcon#read 6, iclass 30, count 2 2006.201.08:35:02.33#ibcon#end of sib2, iclass 30, count 2 2006.201.08:35:02.33#ibcon#*mode == 0, iclass 30, count 2 2006.201.08:35:02.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.08:35:02.33#ibcon#[25=AT05-04\r\n] 2006.201.08:35:02.33#ibcon#*before write, iclass 30, count 2 2006.201.08:35:02.33#ibcon#enter sib2, iclass 30, count 2 2006.201.08:35:02.33#ibcon#flushed, iclass 30, count 2 2006.201.08:35:02.33#ibcon#about to write, iclass 30, count 2 2006.201.08:35:02.33#ibcon#wrote, iclass 30, count 2 2006.201.08:35:02.33#ibcon#about to read 3, iclass 30, count 2 2006.201.08:35:02.36#ibcon#read 3, iclass 30, count 2 2006.201.08:35:02.36#ibcon#about to read 4, iclass 30, count 2 2006.201.08:35:02.36#ibcon#read 4, iclass 30, count 2 2006.201.08:35:02.36#ibcon#about to read 5, iclass 30, count 2 2006.201.08:35:02.36#ibcon#read 5, iclass 30, count 2 2006.201.08:35:02.36#ibcon#about to read 6, iclass 30, count 2 2006.201.08:35:02.36#ibcon#read 6, iclass 30, count 2 2006.201.08:35:02.36#ibcon#end of sib2, iclass 30, count 2 2006.201.08:35:02.36#ibcon#*after write, iclass 30, count 2 2006.201.08:35:02.36#ibcon#*before return 0, iclass 30, count 2 2006.201.08:35:02.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:02.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:02.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.08:35:02.36#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:02.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:02.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:02.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:02.48#ibcon#enter wrdev, iclass 30, count 0 2006.201.08:35:02.48#ibcon#first serial, iclass 30, count 0 2006.201.08:35:02.48#ibcon#enter sib2, iclass 30, count 0 2006.201.08:35:02.48#ibcon#flushed, iclass 30, count 0 2006.201.08:35:02.48#ibcon#about to write, iclass 30, count 0 2006.201.08:35:02.48#ibcon#wrote, iclass 30, count 0 2006.201.08:35:02.48#ibcon#about to read 3, iclass 30, count 0 2006.201.08:35:02.50#ibcon#read 3, iclass 30, count 0 2006.201.08:35:02.50#ibcon#about to read 4, iclass 30, count 0 2006.201.08:35:02.50#ibcon#read 4, iclass 30, count 0 2006.201.08:35:02.50#ibcon#about to read 5, iclass 30, count 0 2006.201.08:35:02.50#ibcon#read 5, iclass 30, count 0 2006.201.08:35:02.50#ibcon#about to read 6, iclass 30, count 0 2006.201.08:35:02.50#ibcon#read 6, iclass 30, count 0 2006.201.08:35:02.50#ibcon#end of sib2, iclass 30, count 0 2006.201.08:35:02.50#ibcon#*mode == 0, iclass 30, count 0 2006.201.08:35:02.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.08:35:02.50#ibcon#[25=USB\r\n] 2006.201.08:35:02.50#ibcon#*before write, iclass 30, count 0 2006.201.08:35:02.50#ibcon#enter sib2, iclass 30, count 0 2006.201.08:35:02.50#ibcon#flushed, iclass 30, count 0 2006.201.08:35:02.50#ibcon#about to write, iclass 30, count 0 2006.201.08:35:02.50#ibcon#wrote, iclass 30, count 0 2006.201.08:35:02.50#ibcon#about to read 3, iclass 30, count 0 2006.201.08:35:02.53#ibcon#read 3, iclass 30, count 0 2006.201.08:35:02.53#ibcon#about to read 4, iclass 30, count 0 2006.201.08:35:02.53#ibcon#read 4, iclass 30, count 0 2006.201.08:35:02.53#ibcon#about to read 5, iclass 30, count 0 2006.201.08:35:02.53#ibcon#read 5, iclass 30, count 0 2006.201.08:35:02.53#ibcon#about to read 6, iclass 30, count 0 2006.201.08:35:02.53#ibcon#read 6, iclass 30, count 0 2006.201.08:35:02.53#ibcon#end of sib2, iclass 30, count 0 2006.201.08:35:02.53#ibcon#*after write, iclass 30, count 0 2006.201.08:35:02.53#ibcon#*before return 0, iclass 30, count 0 2006.201.08:35:02.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:02.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:02.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.08:35:02.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.08:35:02.53$vck44/valo=6,814.99 2006.201.08:35:02.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.08:35:02.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.08:35:02.53#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:02.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:02.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:02.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:02.53#ibcon#enter wrdev, iclass 32, count 0 2006.201.08:35:02.53#ibcon#first serial, iclass 32, count 0 2006.201.08:35:02.53#ibcon#enter sib2, iclass 32, count 0 2006.201.08:35:02.53#ibcon#flushed, iclass 32, count 0 2006.201.08:35:02.53#ibcon#about to write, iclass 32, count 0 2006.201.08:35:02.53#ibcon#wrote, iclass 32, count 0 2006.201.08:35:02.53#ibcon#about to read 3, iclass 32, count 0 2006.201.08:35:02.55#ibcon#read 3, iclass 32, count 0 2006.201.08:35:02.55#ibcon#about to read 4, iclass 32, count 0 2006.201.08:35:02.55#ibcon#read 4, iclass 32, count 0 2006.201.08:35:02.55#ibcon#about to read 5, iclass 32, count 0 2006.201.08:35:02.55#ibcon#read 5, iclass 32, count 0 2006.201.08:35:02.55#ibcon#about to read 6, iclass 32, count 0 2006.201.08:35:02.55#ibcon#read 6, iclass 32, count 0 2006.201.08:35:02.55#ibcon#end of sib2, iclass 32, count 0 2006.201.08:35:02.55#ibcon#*mode == 0, iclass 32, count 0 2006.201.08:35:02.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.08:35:02.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:35:02.55#ibcon#*before write, iclass 32, count 0 2006.201.08:35:02.55#ibcon#enter sib2, iclass 32, count 0 2006.201.08:35:02.55#ibcon#flushed, iclass 32, count 0 2006.201.08:35:02.55#ibcon#about to write, iclass 32, count 0 2006.201.08:35:02.55#ibcon#wrote, iclass 32, count 0 2006.201.08:35:02.55#ibcon#about to read 3, iclass 32, count 0 2006.201.08:35:02.60#ibcon#read 3, iclass 32, count 0 2006.201.08:35:02.60#ibcon#about to read 4, iclass 32, count 0 2006.201.08:35:02.60#ibcon#read 4, iclass 32, count 0 2006.201.08:35:02.60#ibcon#about to read 5, iclass 32, count 0 2006.201.08:35:02.60#ibcon#read 5, iclass 32, count 0 2006.201.08:35:02.60#ibcon#about to read 6, iclass 32, count 0 2006.201.08:35:02.60#ibcon#read 6, iclass 32, count 0 2006.201.08:35:02.60#ibcon#end of sib2, iclass 32, count 0 2006.201.08:35:02.60#ibcon#*after write, iclass 32, count 0 2006.201.08:35:02.60#ibcon#*before return 0, iclass 32, count 0 2006.201.08:35:02.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:02.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:02.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.08:35:02.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.08:35:02.60$vck44/va=6,5 2006.201.08:35:02.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.08:35:02.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.08:35:02.60#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:02.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:02.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:02.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:02.65#ibcon#enter wrdev, iclass 34, count 2 2006.201.08:35:02.65#ibcon#first serial, iclass 34, count 2 2006.201.08:35:02.65#ibcon#enter sib2, iclass 34, count 2 2006.201.08:35:02.65#ibcon#flushed, iclass 34, count 2 2006.201.08:35:02.65#ibcon#about to write, iclass 34, count 2 2006.201.08:35:02.65#ibcon#wrote, iclass 34, count 2 2006.201.08:35:02.65#ibcon#about to read 3, iclass 34, count 2 2006.201.08:35:02.67#ibcon#read 3, iclass 34, count 2 2006.201.08:35:02.67#ibcon#about to read 4, iclass 34, count 2 2006.201.08:35:02.67#ibcon#read 4, iclass 34, count 2 2006.201.08:35:02.67#ibcon#about to read 5, iclass 34, count 2 2006.201.08:35:02.67#ibcon#read 5, iclass 34, count 2 2006.201.08:35:02.67#ibcon#about to read 6, iclass 34, count 2 2006.201.08:35:02.67#ibcon#read 6, iclass 34, count 2 2006.201.08:35:02.67#ibcon#end of sib2, iclass 34, count 2 2006.201.08:35:02.67#ibcon#*mode == 0, iclass 34, count 2 2006.201.08:35:02.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.08:35:02.67#ibcon#[25=AT06-05\r\n] 2006.201.08:35:02.67#ibcon#*before write, iclass 34, count 2 2006.201.08:35:02.67#ibcon#enter sib2, iclass 34, count 2 2006.201.08:35:02.67#ibcon#flushed, iclass 34, count 2 2006.201.08:35:02.67#ibcon#about to write, iclass 34, count 2 2006.201.08:35:02.67#ibcon#wrote, iclass 34, count 2 2006.201.08:35:02.67#ibcon#about to read 3, iclass 34, count 2 2006.201.08:35:02.70#ibcon#read 3, iclass 34, count 2 2006.201.08:35:02.70#ibcon#about to read 4, iclass 34, count 2 2006.201.08:35:02.70#ibcon#read 4, iclass 34, count 2 2006.201.08:35:02.70#ibcon#about to read 5, iclass 34, count 2 2006.201.08:35:02.70#ibcon#read 5, iclass 34, count 2 2006.201.08:35:02.70#ibcon#about to read 6, iclass 34, count 2 2006.201.08:35:02.70#ibcon#read 6, iclass 34, count 2 2006.201.08:35:02.70#ibcon#end of sib2, iclass 34, count 2 2006.201.08:35:02.70#ibcon#*after write, iclass 34, count 2 2006.201.08:35:02.70#ibcon#*before return 0, iclass 34, count 2 2006.201.08:35:02.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:02.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:02.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.08:35:02.70#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:02.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:02.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:02.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:02.82#ibcon#enter wrdev, iclass 34, count 0 2006.201.08:35:02.82#ibcon#first serial, iclass 34, count 0 2006.201.08:35:02.82#ibcon#enter sib2, iclass 34, count 0 2006.201.08:35:02.82#ibcon#flushed, iclass 34, count 0 2006.201.08:35:02.82#ibcon#about to write, iclass 34, count 0 2006.201.08:35:02.82#ibcon#wrote, iclass 34, count 0 2006.201.08:35:02.82#ibcon#about to read 3, iclass 34, count 0 2006.201.08:35:02.84#ibcon#read 3, iclass 34, count 0 2006.201.08:35:02.84#ibcon#about to read 4, iclass 34, count 0 2006.201.08:35:02.84#ibcon#read 4, iclass 34, count 0 2006.201.08:35:02.84#ibcon#about to read 5, iclass 34, count 0 2006.201.08:35:02.84#ibcon#read 5, iclass 34, count 0 2006.201.08:35:02.84#ibcon#about to read 6, iclass 34, count 0 2006.201.08:35:02.84#ibcon#read 6, iclass 34, count 0 2006.201.08:35:02.84#ibcon#end of sib2, iclass 34, count 0 2006.201.08:35:02.84#ibcon#*mode == 0, iclass 34, count 0 2006.201.08:35:02.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.08:35:02.84#ibcon#[25=USB\r\n] 2006.201.08:35:02.84#ibcon#*before write, iclass 34, count 0 2006.201.08:35:02.84#ibcon#enter sib2, iclass 34, count 0 2006.201.08:35:02.84#ibcon#flushed, iclass 34, count 0 2006.201.08:35:02.84#ibcon#about to write, iclass 34, count 0 2006.201.08:35:02.84#ibcon#wrote, iclass 34, count 0 2006.201.08:35:02.84#ibcon#about to read 3, iclass 34, count 0 2006.201.08:35:02.87#ibcon#read 3, iclass 34, count 0 2006.201.08:35:02.87#ibcon#about to read 4, iclass 34, count 0 2006.201.08:35:02.87#ibcon#read 4, iclass 34, count 0 2006.201.08:35:02.87#ibcon#about to read 5, iclass 34, count 0 2006.201.08:35:02.87#ibcon#read 5, iclass 34, count 0 2006.201.08:35:02.87#ibcon#about to read 6, iclass 34, count 0 2006.201.08:35:02.87#ibcon#read 6, iclass 34, count 0 2006.201.08:35:02.87#ibcon#end of sib2, iclass 34, count 0 2006.201.08:35:02.87#ibcon#*after write, iclass 34, count 0 2006.201.08:35:02.87#ibcon#*before return 0, iclass 34, count 0 2006.201.08:35:02.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:02.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:02.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.08:35:02.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.08:35:02.87$vck44/valo=7,864.99 2006.201.08:35:02.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.08:35:02.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.08:35:02.87#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:02.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:35:02.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:35:02.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:35:02.87#ibcon#enter wrdev, iclass 36, count 0 2006.201.08:35:02.87#ibcon#first serial, iclass 36, count 0 2006.201.08:35:02.87#ibcon#enter sib2, iclass 36, count 0 2006.201.08:35:02.87#ibcon#flushed, iclass 36, count 0 2006.201.08:35:02.87#ibcon#about to write, iclass 36, count 0 2006.201.08:35:02.87#ibcon#wrote, iclass 36, count 0 2006.201.08:35:02.87#ibcon#about to read 3, iclass 36, count 0 2006.201.08:35:02.89#ibcon#read 3, iclass 36, count 0 2006.201.08:35:02.89#ibcon#about to read 4, iclass 36, count 0 2006.201.08:35:02.89#ibcon#read 4, iclass 36, count 0 2006.201.08:35:02.89#ibcon#about to read 5, iclass 36, count 0 2006.201.08:35:02.89#ibcon#read 5, iclass 36, count 0 2006.201.08:35:02.89#ibcon#about to read 6, iclass 36, count 0 2006.201.08:35:02.89#ibcon#read 6, iclass 36, count 0 2006.201.08:35:02.89#ibcon#end of sib2, iclass 36, count 0 2006.201.08:35:02.89#ibcon#*mode == 0, iclass 36, count 0 2006.201.08:35:02.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.08:35:02.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:35:02.89#ibcon#*before write, iclass 36, count 0 2006.201.08:35:02.89#ibcon#enter sib2, iclass 36, count 0 2006.201.08:35:02.89#ibcon#flushed, iclass 36, count 0 2006.201.08:35:02.89#ibcon#about to write, iclass 36, count 0 2006.201.08:35:02.89#ibcon#wrote, iclass 36, count 0 2006.201.08:35:02.89#ibcon#about to read 3, iclass 36, count 0 2006.201.08:35:02.94#ibcon#read 3, iclass 36, count 0 2006.201.08:35:02.94#ibcon#about to read 4, iclass 36, count 0 2006.201.08:35:02.94#ibcon#read 4, iclass 36, count 0 2006.201.08:35:02.94#ibcon#about to read 5, iclass 36, count 0 2006.201.08:35:02.94#ibcon#read 5, iclass 36, count 0 2006.201.08:35:02.94#ibcon#about to read 6, iclass 36, count 0 2006.201.08:35:02.94#ibcon#read 6, iclass 36, count 0 2006.201.08:35:02.94#ibcon#end of sib2, iclass 36, count 0 2006.201.08:35:02.94#ibcon#*after write, iclass 36, count 0 2006.201.08:35:02.94#ibcon#*before return 0, iclass 36, count 0 2006.201.08:35:02.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:35:02.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:35:02.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.08:35:02.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.08:35:02.94$vck44/va=7,5 2006.201.08:35:02.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.08:35:02.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.08:35:02.94#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:02.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:35:02.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:35:02.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:35:02.99#ibcon#enter wrdev, iclass 38, count 2 2006.201.08:35:02.99#ibcon#first serial, iclass 38, count 2 2006.201.08:35:02.99#ibcon#enter sib2, iclass 38, count 2 2006.201.08:35:02.99#ibcon#flushed, iclass 38, count 2 2006.201.08:35:02.99#ibcon#about to write, iclass 38, count 2 2006.201.08:35:02.99#ibcon#wrote, iclass 38, count 2 2006.201.08:35:02.99#ibcon#about to read 3, iclass 38, count 2 2006.201.08:35:03.01#ibcon#read 3, iclass 38, count 2 2006.201.08:35:03.01#ibcon#about to read 4, iclass 38, count 2 2006.201.08:35:03.01#ibcon#read 4, iclass 38, count 2 2006.201.08:35:03.01#ibcon#about to read 5, iclass 38, count 2 2006.201.08:35:03.01#ibcon#read 5, iclass 38, count 2 2006.201.08:35:03.01#ibcon#about to read 6, iclass 38, count 2 2006.201.08:35:03.01#ibcon#read 6, iclass 38, count 2 2006.201.08:35:03.01#ibcon#end of sib2, iclass 38, count 2 2006.201.08:35:03.01#ibcon#*mode == 0, iclass 38, count 2 2006.201.08:35:03.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.08:35:03.01#ibcon#[25=AT07-05\r\n] 2006.201.08:35:03.01#ibcon#*before write, iclass 38, count 2 2006.201.08:35:03.01#ibcon#enter sib2, iclass 38, count 2 2006.201.08:35:03.01#ibcon#flushed, iclass 38, count 2 2006.201.08:35:03.01#ibcon#about to write, iclass 38, count 2 2006.201.08:35:03.01#ibcon#wrote, iclass 38, count 2 2006.201.08:35:03.01#ibcon#about to read 3, iclass 38, count 2 2006.201.08:35:03.04#ibcon#read 3, iclass 38, count 2 2006.201.08:35:03.04#ibcon#about to read 4, iclass 38, count 2 2006.201.08:35:03.04#ibcon#read 4, iclass 38, count 2 2006.201.08:35:03.04#ibcon#about to read 5, iclass 38, count 2 2006.201.08:35:03.04#ibcon#read 5, iclass 38, count 2 2006.201.08:35:03.04#ibcon#about to read 6, iclass 38, count 2 2006.201.08:35:03.04#ibcon#read 6, iclass 38, count 2 2006.201.08:35:03.04#ibcon#end of sib2, iclass 38, count 2 2006.201.08:35:03.04#ibcon#*after write, iclass 38, count 2 2006.201.08:35:03.04#ibcon#*before return 0, iclass 38, count 2 2006.201.08:35:03.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:35:03.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:35:03.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.08:35:03.04#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:03.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:35:03.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:35:03.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:35:03.16#ibcon#enter wrdev, iclass 38, count 0 2006.201.08:35:03.16#ibcon#first serial, iclass 38, count 0 2006.201.08:35:03.16#ibcon#enter sib2, iclass 38, count 0 2006.201.08:35:03.16#ibcon#flushed, iclass 38, count 0 2006.201.08:35:03.16#ibcon#about to write, iclass 38, count 0 2006.201.08:35:03.16#ibcon#wrote, iclass 38, count 0 2006.201.08:35:03.16#ibcon#about to read 3, iclass 38, count 0 2006.201.08:35:03.18#ibcon#read 3, iclass 38, count 0 2006.201.08:35:03.18#ibcon#about to read 4, iclass 38, count 0 2006.201.08:35:03.18#ibcon#read 4, iclass 38, count 0 2006.201.08:35:03.18#ibcon#about to read 5, iclass 38, count 0 2006.201.08:35:03.18#ibcon#read 5, iclass 38, count 0 2006.201.08:35:03.18#ibcon#about to read 6, iclass 38, count 0 2006.201.08:35:03.18#ibcon#read 6, iclass 38, count 0 2006.201.08:35:03.18#ibcon#end of sib2, iclass 38, count 0 2006.201.08:35:03.18#ibcon#*mode == 0, iclass 38, count 0 2006.201.08:35:03.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.08:35:03.18#ibcon#[25=USB\r\n] 2006.201.08:35:03.18#ibcon#*before write, iclass 38, count 0 2006.201.08:35:03.18#ibcon#enter sib2, iclass 38, count 0 2006.201.08:35:03.18#ibcon#flushed, iclass 38, count 0 2006.201.08:35:03.18#ibcon#about to write, iclass 38, count 0 2006.201.08:35:03.18#ibcon#wrote, iclass 38, count 0 2006.201.08:35:03.18#ibcon#about to read 3, iclass 38, count 0 2006.201.08:35:03.21#ibcon#read 3, iclass 38, count 0 2006.201.08:35:03.21#ibcon#about to read 4, iclass 38, count 0 2006.201.08:35:03.21#ibcon#read 4, iclass 38, count 0 2006.201.08:35:03.21#ibcon#about to read 5, iclass 38, count 0 2006.201.08:35:03.21#ibcon#read 5, iclass 38, count 0 2006.201.08:35:03.21#ibcon#about to read 6, iclass 38, count 0 2006.201.08:35:03.21#ibcon#read 6, iclass 38, count 0 2006.201.08:35:03.21#ibcon#end of sib2, iclass 38, count 0 2006.201.08:35:03.21#ibcon#*after write, iclass 38, count 0 2006.201.08:35:03.21#ibcon#*before return 0, iclass 38, count 0 2006.201.08:35:03.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:35:03.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:35:03.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.08:35:03.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.08:35:03.21$vck44/valo=8,884.99 2006.201.08:35:03.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.08:35:03.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.08:35:03.21#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:03.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:35:03.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:35:03.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:35:03.21#ibcon#enter wrdev, iclass 40, count 0 2006.201.08:35:03.21#ibcon#first serial, iclass 40, count 0 2006.201.08:35:03.21#ibcon#enter sib2, iclass 40, count 0 2006.201.08:35:03.21#ibcon#flushed, iclass 40, count 0 2006.201.08:35:03.21#ibcon#about to write, iclass 40, count 0 2006.201.08:35:03.21#ibcon#wrote, iclass 40, count 0 2006.201.08:35:03.21#ibcon#about to read 3, iclass 40, count 0 2006.201.08:35:03.23#ibcon#read 3, iclass 40, count 0 2006.201.08:35:03.23#ibcon#about to read 4, iclass 40, count 0 2006.201.08:35:03.23#ibcon#read 4, iclass 40, count 0 2006.201.08:35:03.23#ibcon#about to read 5, iclass 40, count 0 2006.201.08:35:03.23#ibcon#read 5, iclass 40, count 0 2006.201.08:35:03.23#ibcon#about to read 6, iclass 40, count 0 2006.201.08:35:03.23#ibcon#read 6, iclass 40, count 0 2006.201.08:35:03.23#ibcon#end of sib2, iclass 40, count 0 2006.201.08:35:03.23#ibcon#*mode == 0, iclass 40, count 0 2006.201.08:35:03.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.08:35:03.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:35:03.23#ibcon#*before write, iclass 40, count 0 2006.201.08:35:03.23#ibcon#enter sib2, iclass 40, count 0 2006.201.08:35:03.23#ibcon#flushed, iclass 40, count 0 2006.201.08:35:03.23#ibcon#about to write, iclass 40, count 0 2006.201.08:35:03.23#ibcon#wrote, iclass 40, count 0 2006.201.08:35:03.23#ibcon#about to read 3, iclass 40, count 0 2006.201.08:35:03.27#ibcon#read 3, iclass 40, count 0 2006.201.08:35:03.27#ibcon#about to read 4, iclass 40, count 0 2006.201.08:35:03.27#ibcon#read 4, iclass 40, count 0 2006.201.08:35:03.27#ibcon#about to read 5, iclass 40, count 0 2006.201.08:35:03.27#ibcon#read 5, iclass 40, count 0 2006.201.08:35:03.27#ibcon#about to read 6, iclass 40, count 0 2006.201.08:35:03.27#ibcon#read 6, iclass 40, count 0 2006.201.08:35:03.27#ibcon#end of sib2, iclass 40, count 0 2006.201.08:35:03.27#ibcon#*after write, iclass 40, count 0 2006.201.08:35:03.27#ibcon#*before return 0, iclass 40, count 0 2006.201.08:35:03.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:35:03.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:35:03.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.08:35:03.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.08:35:03.27$vck44/va=8,4 2006.201.08:35:03.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.08:35:03.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.08:35:03.27#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:03.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:35:03.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:35:03.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:35:03.33#ibcon#enter wrdev, iclass 4, count 2 2006.201.08:35:03.33#ibcon#first serial, iclass 4, count 2 2006.201.08:35:03.33#ibcon#enter sib2, iclass 4, count 2 2006.201.08:35:03.33#ibcon#flushed, iclass 4, count 2 2006.201.08:35:03.33#ibcon#about to write, iclass 4, count 2 2006.201.08:35:03.33#ibcon#wrote, iclass 4, count 2 2006.201.08:35:03.33#ibcon#about to read 3, iclass 4, count 2 2006.201.08:35:03.35#ibcon#read 3, iclass 4, count 2 2006.201.08:35:03.35#ibcon#about to read 4, iclass 4, count 2 2006.201.08:35:03.35#ibcon#read 4, iclass 4, count 2 2006.201.08:35:03.35#ibcon#about to read 5, iclass 4, count 2 2006.201.08:35:03.35#ibcon#read 5, iclass 4, count 2 2006.201.08:35:03.35#ibcon#about to read 6, iclass 4, count 2 2006.201.08:35:03.35#ibcon#read 6, iclass 4, count 2 2006.201.08:35:03.35#ibcon#end of sib2, iclass 4, count 2 2006.201.08:35:03.35#ibcon#*mode == 0, iclass 4, count 2 2006.201.08:35:03.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.08:35:03.35#ibcon#[25=AT08-04\r\n] 2006.201.08:35:03.35#ibcon#*before write, iclass 4, count 2 2006.201.08:35:03.35#ibcon#enter sib2, iclass 4, count 2 2006.201.08:35:03.35#ibcon#flushed, iclass 4, count 2 2006.201.08:35:03.35#ibcon#about to write, iclass 4, count 2 2006.201.08:35:03.35#ibcon#wrote, iclass 4, count 2 2006.201.08:35:03.35#ibcon#about to read 3, iclass 4, count 2 2006.201.08:35:03.38#ibcon#read 3, iclass 4, count 2 2006.201.08:35:03.38#ibcon#about to read 4, iclass 4, count 2 2006.201.08:35:03.38#ibcon#read 4, iclass 4, count 2 2006.201.08:35:03.38#ibcon#about to read 5, iclass 4, count 2 2006.201.08:35:03.38#ibcon#read 5, iclass 4, count 2 2006.201.08:35:03.38#ibcon#about to read 6, iclass 4, count 2 2006.201.08:35:03.38#ibcon#read 6, iclass 4, count 2 2006.201.08:35:03.38#ibcon#end of sib2, iclass 4, count 2 2006.201.08:35:03.38#ibcon#*after write, iclass 4, count 2 2006.201.08:35:03.38#ibcon#*before return 0, iclass 4, count 2 2006.201.08:35:03.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:35:03.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:35:03.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.08:35:03.38#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:03.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:35:03.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:35:03.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:35:03.50#ibcon#enter wrdev, iclass 4, count 0 2006.201.08:35:03.50#ibcon#first serial, iclass 4, count 0 2006.201.08:35:03.50#ibcon#enter sib2, iclass 4, count 0 2006.201.08:35:03.50#ibcon#flushed, iclass 4, count 0 2006.201.08:35:03.50#ibcon#about to write, iclass 4, count 0 2006.201.08:35:03.50#ibcon#wrote, iclass 4, count 0 2006.201.08:35:03.50#ibcon#about to read 3, iclass 4, count 0 2006.201.08:35:03.52#ibcon#read 3, iclass 4, count 0 2006.201.08:35:03.52#ibcon#about to read 4, iclass 4, count 0 2006.201.08:35:03.52#ibcon#read 4, iclass 4, count 0 2006.201.08:35:03.52#ibcon#about to read 5, iclass 4, count 0 2006.201.08:35:03.52#ibcon#read 5, iclass 4, count 0 2006.201.08:35:03.52#ibcon#about to read 6, iclass 4, count 0 2006.201.08:35:03.52#ibcon#read 6, iclass 4, count 0 2006.201.08:35:03.52#ibcon#end of sib2, iclass 4, count 0 2006.201.08:35:03.52#ibcon#*mode == 0, iclass 4, count 0 2006.201.08:35:03.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.08:35:03.52#ibcon#[25=USB\r\n] 2006.201.08:35:03.52#ibcon#*before write, iclass 4, count 0 2006.201.08:35:03.52#ibcon#enter sib2, iclass 4, count 0 2006.201.08:35:03.52#ibcon#flushed, iclass 4, count 0 2006.201.08:35:03.52#ibcon#about to write, iclass 4, count 0 2006.201.08:35:03.52#ibcon#wrote, iclass 4, count 0 2006.201.08:35:03.52#ibcon#about to read 3, iclass 4, count 0 2006.201.08:35:03.55#ibcon#read 3, iclass 4, count 0 2006.201.08:35:03.55#ibcon#about to read 4, iclass 4, count 0 2006.201.08:35:03.55#ibcon#read 4, iclass 4, count 0 2006.201.08:35:03.55#ibcon#about to read 5, iclass 4, count 0 2006.201.08:35:03.55#ibcon#read 5, iclass 4, count 0 2006.201.08:35:03.55#ibcon#about to read 6, iclass 4, count 0 2006.201.08:35:03.55#ibcon#read 6, iclass 4, count 0 2006.201.08:35:03.55#ibcon#end of sib2, iclass 4, count 0 2006.201.08:35:03.55#ibcon#*after write, iclass 4, count 0 2006.201.08:35:03.55#ibcon#*before return 0, iclass 4, count 0 2006.201.08:35:03.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:35:03.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:35:03.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.08:35:03.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.08:35:03.55$vck44/vblo=1,629.99 2006.201.08:35:03.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.08:35:03.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.08:35:03.55#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:03.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:03.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:03.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:03.55#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:35:03.55#ibcon#first serial, iclass 6, count 0 2006.201.08:35:03.55#ibcon#enter sib2, iclass 6, count 0 2006.201.08:35:03.55#ibcon#flushed, iclass 6, count 0 2006.201.08:35:03.55#ibcon#about to write, iclass 6, count 0 2006.201.08:35:03.55#ibcon#wrote, iclass 6, count 0 2006.201.08:35:03.55#ibcon#about to read 3, iclass 6, count 0 2006.201.08:35:03.57#ibcon#read 3, iclass 6, count 0 2006.201.08:35:03.57#ibcon#about to read 4, iclass 6, count 0 2006.201.08:35:03.57#ibcon#read 4, iclass 6, count 0 2006.201.08:35:03.57#ibcon#about to read 5, iclass 6, count 0 2006.201.08:35:03.57#ibcon#read 5, iclass 6, count 0 2006.201.08:35:03.57#ibcon#about to read 6, iclass 6, count 0 2006.201.08:35:03.57#ibcon#read 6, iclass 6, count 0 2006.201.08:35:03.57#ibcon#end of sib2, iclass 6, count 0 2006.201.08:35:03.57#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:35:03.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:35:03.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:35:03.57#ibcon#*before write, iclass 6, count 0 2006.201.08:35:03.57#ibcon#enter sib2, iclass 6, count 0 2006.201.08:35:03.57#ibcon#flushed, iclass 6, count 0 2006.201.08:35:03.57#ibcon#about to write, iclass 6, count 0 2006.201.08:35:03.57#ibcon#wrote, iclass 6, count 0 2006.201.08:35:03.57#ibcon#about to read 3, iclass 6, count 0 2006.201.08:35:03.62#ibcon#read 3, iclass 6, count 0 2006.201.08:35:03.62#ibcon#about to read 4, iclass 6, count 0 2006.201.08:35:03.62#ibcon#read 4, iclass 6, count 0 2006.201.08:35:03.62#ibcon#about to read 5, iclass 6, count 0 2006.201.08:35:03.62#ibcon#read 5, iclass 6, count 0 2006.201.08:35:03.62#ibcon#about to read 6, iclass 6, count 0 2006.201.08:35:03.62#ibcon#read 6, iclass 6, count 0 2006.201.08:35:03.62#ibcon#end of sib2, iclass 6, count 0 2006.201.08:35:03.62#ibcon#*after write, iclass 6, count 0 2006.201.08:35:03.62#ibcon#*before return 0, iclass 6, count 0 2006.201.08:35:03.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:03.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:03.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:35:03.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:35:03.62$vck44/vb=1,4 2006.201.08:35:03.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.08:35:03.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.08:35:03.62#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:03.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:35:03.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:35:03.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:35:03.62#ibcon#enter wrdev, iclass 10, count 2 2006.201.08:35:03.62#ibcon#first serial, iclass 10, count 2 2006.201.08:35:03.62#ibcon#enter sib2, iclass 10, count 2 2006.201.08:35:03.62#ibcon#flushed, iclass 10, count 2 2006.201.08:35:03.62#ibcon#about to write, iclass 10, count 2 2006.201.08:35:03.62#ibcon#wrote, iclass 10, count 2 2006.201.08:35:03.62#ibcon#about to read 3, iclass 10, count 2 2006.201.08:35:03.64#ibcon#read 3, iclass 10, count 2 2006.201.08:35:03.64#ibcon#about to read 4, iclass 10, count 2 2006.201.08:35:03.64#ibcon#read 4, iclass 10, count 2 2006.201.08:35:03.64#ibcon#about to read 5, iclass 10, count 2 2006.201.08:35:03.64#ibcon#read 5, iclass 10, count 2 2006.201.08:35:03.64#ibcon#about to read 6, iclass 10, count 2 2006.201.08:35:03.64#ibcon#read 6, iclass 10, count 2 2006.201.08:35:03.64#ibcon#end of sib2, iclass 10, count 2 2006.201.08:35:03.64#ibcon#*mode == 0, iclass 10, count 2 2006.201.08:35:03.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.08:35:03.64#ibcon#[27=AT01-04\r\n] 2006.201.08:35:03.64#ibcon#*before write, iclass 10, count 2 2006.201.08:35:03.64#ibcon#enter sib2, iclass 10, count 2 2006.201.08:35:03.64#ibcon#flushed, iclass 10, count 2 2006.201.08:35:03.64#ibcon#about to write, iclass 10, count 2 2006.201.08:35:03.64#ibcon#wrote, iclass 10, count 2 2006.201.08:35:03.64#ibcon#about to read 3, iclass 10, count 2 2006.201.08:35:03.67#ibcon#read 3, iclass 10, count 2 2006.201.08:35:03.67#ibcon#about to read 4, iclass 10, count 2 2006.201.08:35:03.67#ibcon#read 4, iclass 10, count 2 2006.201.08:35:03.67#ibcon#about to read 5, iclass 10, count 2 2006.201.08:35:03.67#ibcon#read 5, iclass 10, count 2 2006.201.08:35:03.67#ibcon#about to read 6, iclass 10, count 2 2006.201.08:35:03.67#ibcon#read 6, iclass 10, count 2 2006.201.08:35:03.67#ibcon#end of sib2, iclass 10, count 2 2006.201.08:35:03.67#ibcon#*after write, iclass 10, count 2 2006.201.08:35:03.67#ibcon#*before return 0, iclass 10, count 2 2006.201.08:35:03.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:35:03.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:35:03.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.08:35:03.67#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:03.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:35:03.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:35:03.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:35:03.79#ibcon#enter wrdev, iclass 10, count 0 2006.201.08:35:03.79#ibcon#first serial, iclass 10, count 0 2006.201.08:35:03.79#ibcon#enter sib2, iclass 10, count 0 2006.201.08:35:03.79#ibcon#flushed, iclass 10, count 0 2006.201.08:35:03.79#ibcon#about to write, iclass 10, count 0 2006.201.08:35:03.79#ibcon#wrote, iclass 10, count 0 2006.201.08:35:03.79#ibcon#about to read 3, iclass 10, count 0 2006.201.08:35:03.81#ibcon#read 3, iclass 10, count 0 2006.201.08:35:03.81#ibcon#about to read 4, iclass 10, count 0 2006.201.08:35:03.81#ibcon#read 4, iclass 10, count 0 2006.201.08:35:03.81#ibcon#about to read 5, iclass 10, count 0 2006.201.08:35:03.81#ibcon#read 5, iclass 10, count 0 2006.201.08:35:03.81#ibcon#about to read 6, iclass 10, count 0 2006.201.08:35:03.81#ibcon#read 6, iclass 10, count 0 2006.201.08:35:03.81#ibcon#end of sib2, iclass 10, count 0 2006.201.08:35:03.81#ibcon#*mode == 0, iclass 10, count 0 2006.201.08:35:03.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.08:35:03.81#ibcon#[27=USB\r\n] 2006.201.08:35:03.81#ibcon#*before write, iclass 10, count 0 2006.201.08:35:03.81#ibcon#enter sib2, iclass 10, count 0 2006.201.08:35:03.81#ibcon#flushed, iclass 10, count 0 2006.201.08:35:03.81#ibcon#about to write, iclass 10, count 0 2006.201.08:35:03.81#ibcon#wrote, iclass 10, count 0 2006.201.08:35:03.81#ibcon#about to read 3, iclass 10, count 0 2006.201.08:35:03.84#ibcon#read 3, iclass 10, count 0 2006.201.08:35:03.84#ibcon#about to read 4, iclass 10, count 0 2006.201.08:35:03.84#ibcon#read 4, iclass 10, count 0 2006.201.08:35:03.84#ibcon#about to read 5, iclass 10, count 0 2006.201.08:35:03.84#ibcon#read 5, iclass 10, count 0 2006.201.08:35:03.84#ibcon#about to read 6, iclass 10, count 0 2006.201.08:35:03.84#ibcon#read 6, iclass 10, count 0 2006.201.08:35:03.84#ibcon#end of sib2, iclass 10, count 0 2006.201.08:35:03.84#ibcon#*after write, iclass 10, count 0 2006.201.08:35:03.84#ibcon#*before return 0, iclass 10, count 0 2006.201.08:35:03.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:35:03.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:35:03.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.08:35:03.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.08:35:03.84$vck44/vblo=2,634.99 2006.201.08:35:03.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.08:35:03.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.08:35:03.84#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:03.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:03.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:03.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:03.84#ibcon#enter wrdev, iclass 12, count 0 2006.201.08:35:03.84#ibcon#first serial, iclass 12, count 0 2006.201.08:35:03.84#ibcon#enter sib2, iclass 12, count 0 2006.201.08:35:03.84#ibcon#flushed, iclass 12, count 0 2006.201.08:35:03.84#ibcon#about to write, iclass 12, count 0 2006.201.08:35:03.84#ibcon#wrote, iclass 12, count 0 2006.201.08:35:03.84#ibcon#about to read 3, iclass 12, count 0 2006.201.08:35:03.86#ibcon#read 3, iclass 12, count 0 2006.201.08:35:03.86#ibcon#about to read 4, iclass 12, count 0 2006.201.08:35:03.86#ibcon#read 4, iclass 12, count 0 2006.201.08:35:03.86#ibcon#about to read 5, iclass 12, count 0 2006.201.08:35:03.86#ibcon#read 5, iclass 12, count 0 2006.201.08:35:03.86#ibcon#about to read 6, iclass 12, count 0 2006.201.08:35:03.86#ibcon#read 6, iclass 12, count 0 2006.201.08:35:03.86#ibcon#end of sib2, iclass 12, count 0 2006.201.08:35:03.86#ibcon#*mode == 0, iclass 12, count 0 2006.201.08:35:03.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.08:35:03.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:35:03.86#ibcon#*before write, iclass 12, count 0 2006.201.08:35:03.86#ibcon#enter sib2, iclass 12, count 0 2006.201.08:35:03.86#ibcon#flushed, iclass 12, count 0 2006.201.08:35:03.86#ibcon#about to write, iclass 12, count 0 2006.201.08:35:03.86#ibcon#wrote, iclass 12, count 0 2006.201.08:35:03.86#ibcon#about to read 3, iclass 12, count 0 2006.201.08:35:03.90#ibcon#read 3, iclass 12, count 0 2006.201.08:35:03.90#ibcon#about to read 4, iclass 12, count 0 2006.201.08:35:03.90#ibcon#read 4, iclass 12, count 0 2006.201.08:35:03.90#ibcon#about to read 5, iclass 12, count 0 2006.201.08:35:03.90#ibcon#read 5, iclass 12, count 0 2006.201.08:35:03.90#ibcon#about to read 6, iclass 12, count 0 2006.201.08:35:03.90#ibcon#read 6, iclass 12, count 0 2006.201.08:35:03.90#ibcon#end of sib2, iclass 12, count 0 2006.201.08:35:03.90#ibcon#*after write, iclass 12, count 0 2006.201.08:35:03.90#ibcon#*before return 0, iclass 12, count 0 2006.201.08:35:03.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:03.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:35:03.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.08:35:03.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.08:35:03.90$vck44/vb=2,5 2006.201.08:35:03.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.08:35:03.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.08:35:03.90#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:03.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:03.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:03.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:03.96#ibcon#enter wrdev, iclass 14, count 2 2006.201.08:35:03.96#ibcon#first serial, iclass 14, count 2 2006.201.08:35:03.96#ibcon#enter sib2, iclass 14, count 2 2006.201.08:35:03.96#ibcon#flushed, iclass 14, count 2 2006.201.08:35:03.96#ibcon#about to write, iclass 14, count 2 2006.201.08:35:03.96#ibcon#wrote, iclass 14, count 2 2006.201.08:35:03.96#ibcon#about to read 3, iclass 14, count 2 2006.201.08:35:03.98#ibcon#read 3, iclass 14, count 2 2006.201.08:35:03.98#ibcon#about to read 4, iclass 14, count 2 2006.201.08:35:03.98#ibcon#read 4, iclass 14, count 2 2006.201.08:35:03.98#ibcon#about to read 5, iclass 14, count 2 2006.201.08:35:03.98#ibcon#read 5, iclass 14, count 2 2006.201.08:35:03.98#ibcon#about to read 6, iclass 14, count 2 2006.201.08:35:03.98#ibcon#read 6, iclass 14, count 2 2006.201.08:35:03.98#ibcon#end of sib2, iclass 14, count 2 2006.201.08:35:03.98#ibcon#*mode == 0, iclass 14, count 2 2006.201.08:35:03.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.08:35:03.98#ibcon#[27=AT02-05\r\n] 2006.201.08:35:03.98#ibcon#*before write, iclass 14, count 2 2006.201.08:35:03.98#ibcon#enter sib2, iclass 14, count 2 2006.201.08:35:03.98#ibcon#flushed, iclass 14, count 2 2006.201.08:35:03.98#ibcon#about to write, iclass 14, count 2 2006.201.08:35:03.98#ibcon#wrote, iclass 14, count 2 2006.201.08:35:03.98#ibcon#about to read 3, iclass 14, count 2 2006.201.08:35:04.01#ibcon#read 3, iclass 14, count 2 2006.201.08:35:04.01#ibcon#about to read 4, iclass 14, count 2 2006.201.08:35:04.01#ibcon#read 4, iclass 14, count 2 2006.201.08:35:04.01#ibcon#about to read 5, iclass 14, count 2 2006.201.08:35:04.01#ibcon#read 5, iclass 14, count 2 2006.201.08:35:04.01#ibcon#about to read 6, iclass 14, count 2 2006.201.08:35:04.01#ibcon#read 6, iclass 14, count 2 2006.201.08:35:04.01#ibcon#end of sib2, iclass 14, count 2 2006.201.08:35:04.01#ibcon#*after write, iclass 14, count 2 2006.201.08:35:04.01#ibcon#*before return 0, iclass 14, count 2 2006.201.08:35:04.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:04.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:35:04.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.08:35:04.01#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:04.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:04.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:04.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:04.13#ibcon#enter wrdev, iclass 14, count 0 2006.201.08:35:04.13#ibcon#first serial, iclass 14, count 0 2006.201.08:35:04.13#ibcon#enter sib2, iclass 14, count 0 2006.201.08:35:04.13#ibcon#flushed, iclass 14, count 0 2006.201.08:35:04.13#ibcon#about to write, iclass 14, count 0 2006.201.08:35:04.13#ibcon#wrote, iclass 14, count 0 2006.201.08:35:04.13#ibcon#about to read 3, iclass 14, count 0 2006.201.08:35:04.15#ibcon#read 3, iclass 14, count 0 2006.201.08:35:04.15#ibcon#about to read 4, iclass 14, count 0 2006.201.08:35:04.15#ibcon#read 4, iclass 14, count 0 2006.201.08:35:04.15#ibcon#about to read 5, iclass 14, count 0 2006.201.08:35:04.15#ibcon#read 5, iclass 14, count 0 2006.201.08:35:04.15#ibcon#about to read 6, iclass 14, count 0 2006.201.08:35:04.15#ibcon#read 6, iclass 14, count 0 2006.201.08:35:04.15#ibcon#end of sib2, iclass 14, count 0 2006.201.08:35:04.15#ibcon#*mode == 0, iclass 14, count 0 2006.201.08:35:04.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.08:35:04.15#ibcon#[27=USB\r\n] 2006.201.08:35:04.15#ibcon#*before write, iclass 14, count 0 2006.201.08:35:04.15#ibcon#enter sib2, iclass 14, count 0 2006.201.08:35:04.15#ibcon#flushed, iclass 14, count 0 2006.201.08:35:04.15#ibcon#about to write, iclass 14, count 0 2006.201.08:35:04.15#ibcon#wrote, iclass 14, count 0 2006.201.08:35:04.15#ibcon#about to read 3, iclass 14, count 0 2006.201.08:35:04.18#ibcon#read 3, iclass 14, count 0 2006.201.08:35:04.18#ibcon#about to read 4, iclass 14, count 0 2006.201.08:35:04.18#ibcon#read 4, iclass 14, count 0 2006.201.08:35:04.18#ibcon#about to read 5, iclass 14, count 0 2006.201.08:35:04.18#ibcon#read 5, iclass 14, count 0 2006.201.08:35:04.18#ibcon#about to read 6, iclass 14, count 0 2006.201.08:35:04.18#ibcon#read 6, iclass 14, count 0 2006.201.08:35:04.18#ibcon#end of sib2, iclass 14, count 0 2006.201.08:35:04.18#ibcon#*after write, iclass 14, count 0 2006.201.08:35:04.18#ibcon#*before return 0, iclass 14, count 0 2006.201.08:35:04.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:04.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:35:04.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.08:35:04.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.08:35:04.18$vck44/vblo=3,649.99 2006.201.08:35:04.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.08:35:04.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.08:35:04.18#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:04.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:04.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:04.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:04.18#ibcon#enter wrdev, iclass 16, count 0 2006.201.08:35:04.18#ibcon#first serial, iclass 16, count 0 2006.201.08:35:04.18#ibcon#enter sib2, iclass 16, count 0 2006.201.08:35:04.18#ibcon#flushed, iclass 16, count 0 2006.201.08:35:04.18#ibcon#about to write, iclass 16, count 0 2006.201.08:35:04.18#ibcon#wrote, iclass 16, count 0 2006.201.08:35:04.18#ibcon#about to read 3, iclass 16, count 0 2006.201.08:35:04.20#ibcon#read 3, iclass 16, count 0 2006.201.08:35:04.20#ibcon#about to read 4, iclass 16, count 0 2006.201.08:35:04.20#ibcon#read 4, iclass 16, count 0 2006.201.08:35:04.20#ibcon#about to read 5, iclass 16, count 0 2006.201.08:35:04.20#ibcon#read 5, iclass 16, count 0 2006.201.08:35:04.20#ibcon#about to read 6, iclass 16, count 0 2006.201.08:35:04.20#ibcon#read 6, iclass 16, count 0 2006.201.08:35:04.20#ibcon#end of sib2, iclass 16, count 0 2006.201.08:35:04.20#ibcon#*mode == 0, iclass 16, count 0 2006.201.08:35:04.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.08:35:04.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:35:04.20#ibcon#*before write, iclass 16, count 0 2006.201.08:35:04.20#ibcon#enter sib2, iclass 16, count 0 2006.201.08:35:04.20#ibcon#flushed, iclass 16, count 0 2006.201.08:35:04.20#ibcon#about to write, iclass 16, count 0 2006.201.08:35:04.20#ibcon#wrote, iclass 16, count 0 2006.201.08:35:04.20#ibcon#about to read 3, iclass 16, count 0 2006.201.08:35:04.24#ibcon#read 3, iclass 16, count 0 2006.201.08:35:04.24#ibcon#about to read 4, iclass 16, count 0 2006.201.08:35:04.24#ibcon#read 4, iclass 16, count 0 2006.201.08:35:04.24#ibcon#about to read 5, iclass 16, count 0 2006.201.08:35:04.24#ibcon#read 5, iclass 16, count 0 2006.201.08:35:04.24#ibcon#about to read 6, iclass 16, count 0 2006.201.08:35:04.24#ibcon#read 6, iclass 16, count 0 2006.201.08:35:04.24#ibcon#end of sib2, iclass 16, count 0 2006.201.08:35:04.24#ibcon#*after write, iclass 16, count 0 2006.201.08:35:04.24#ibcon#*before return 0, iclass 16, count 0 2006.201.08:35:04.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:04.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:35:04.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.08:35:04.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.08:35:04.24$vck44/vb=3,4 2006.201.08:35:04.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.08:35:04.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.08:35:04.24#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:04.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:04.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:04.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:04.30#ibcon#enter wrdev, iclass 18, count 2 2006.201.08:35:04.30#ibcon#first serial, iclass 18, count 2 2006.201.08:35:04.30#ibcon#enter sib2, iclass 18, count 2 2006.201.08:35:04.30#ibcon#flushed, iclass 18, count 2 2006.201.08:35:04.30#ibcon#about to write, iclass 18, count 2 2006.201.08:35:04.30#ibcon#wrote, iclass 18, count 2 2006.201.08:35:04.30#ibcon#about to read 3, iclass 18, count 2 2006.201.08:35:04.32#ibcon#read 3, iclass 18, count 2 2006.201.08:35:04.32#ibcon#about to read 4, iclass 18, count 2 2006.201.08:35:04.32#ibcon#read 4, iclass 18, count 2 2006.201.08:35:04.32#ibcon#about to read 5, iclass 18, count 2 2006.201.08:35:04.32#ibcon#read 5, iclass 18, count 2 2006.201.08:35:04.32#ibcon#about to read 6, iclass 18, count 2 2006.201.08:35:04.32#ibcon#read 6, iclass 18, count 2 2006.201.08:35:04.32#ibcon#end of sib2, iclass 18, count 2 2006.201.08:35:04.32#ibcon#*mode == 0, iclass 18, count 2 2006.201.08:35:04.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.08:35:04.32#ibcon#[27=AT03-04\r\n] 2006.201.08:35:04.32#ibcon#*before write, iclass 18, count 2 2006.201.08:35:04.32#ibcon#enter sib2, iclass 18, count 2 2006.201.08:35:04.32#ibcon#flushed, iclass 18, count 2 2006.201.08:35:04.32#ibcon#about to write, iclass 18, count 2 2006.201.08:35:04.32#ibcon#wrote, iclass 18, count 2 2006.201.08:35:04.32#ibcon#about to read 3, iclass 18, count 2 2006.201.08:35:04.35#ibcon#read 3, iclass 18, count 2 2006.201.08:35:04.35#ibcon#about to read 4, iclass 18, count 2 2006.201.08:35:04.35#ibcon#read 4, iclass 18, count 2 2006.201.08:35:04.35#ibcon#about to read 5, iclass 18, count 2 2006.201.08:35:04.35#ibcon#read 5, iclass 18, count 2 2006.201.08:35:04.35#ibcon#about to read 6, iclass 18, count 2 2006.201.08:35:04.35#ibcon#read 6, iclass 18, count 2 2006.201.08:35:04.35#ibcon#end of sib2, iclass 18, count 2 2006.201.08:35:04.35#ibcon#*after write, iclass 18, count 2 2006.201.08:35:04.35#ibcon#*before return 0, iclass 18, count 2 2006.201.08:35:04.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:04.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:35:04.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.08:35:04.35#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:04.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:04.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:04.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:04.47#ibcon#enter wrdev, iclass 18, count 0 2006.201.08:35:04.47#ibcon#first serial, iclass 18, count 0 2006.201.08:35:04.47#ibcon#enter sib2, iclass 18, count 0 2006.201.08:35:04.47#ibcon#flushed, iclass 18, count 0 2006.201.08:35:04.47#ibcon#about to write, iclass 18, count 0 2006.201.08:35:04.47#ibcon#wrote, iclass 18, count 0 2006.201.08:35:04.47#ibcon#about to read 3, iclass 18, count 0 2006.201.08:35:04.49#ibcon#read 3, iclass 18, count 0 2006.201.08:35:04.49#ibcon#about to read 4, iclass 18, count 0 2006.201.08:35:04.49#ibcon#read 4, iclass 18, count 0 2006.201.08:35:04.49#ibcon#about to read 5, iclass 18, count 0 2006.201.08:35:04.49#ibcon#read 5, iclass 18, count 0 2006.201.08:35:04.49#ibcon#about to read 6, iclass 18, count 0 2006.201.08:35:04.49#ibcon#read 6, iclass 18, count 0 2006.201.08:35:04.49#ibcon#end of sib2, iclass 18, count 0 2006.201.08:35:04.49#ibcon#*mode == 0, iclass 18, count 0 2006.201.08:35:04.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.08:35:04.49#ibcon#[27=USB\r\n] 2006.201.08:35:04.49#ibcon#*before write, iclass 18, count 0 2006.201.08:35:04.49#ibcon#enter sib2, iclass 18, count 0 2006.201.08:35:04.49#ibcon#flushed, iclass 18, count 0 2006.201.08:35:04.49#ibcon#about to write, iclass 18, count 0 2006.201.08:35:04.49#ibcon#wrote, iclass 18, count 0 2006.201.08:35:04.49#ibcon#about to read 3, iclass 18, count 0 2006.201.08:35:04.52#ibcon#read 3, iclass 18, count 0 2006.201.08:35:04.52#ibcon#about to read 4, iclass 18, count 0 2006.201.08:35:04.52#ibcon#read 4, iclass 18, count 0 2006.201.08:35:04.52#ibcon#about to read 5, iclass 18, count 0 2006.201.08:35:04.52#ibcon#read 5, iclass 18, count 0 2006.201.08:35:04.52#ibcon#about to read 6, iclass 18, count 0 2006.201.08:35:04.52#ibcon#read 6, iclass 18, count 0 2006.201.08:35:04.52#ibcon#end of sib2, iclass 18, count 0 2006.201.08:35:04.52#ibcon#*after write, iclass 18, count 0 2006.201.08:35:04.52#ibcon#*before return 0, iclass 18, count 0 2006.201.08:35:04.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:04.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:35:04.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.08:35:04.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.08:35:04.52$vck44/vblo=4,679.99 2006.201.08:35:04.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.08:35:04.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.08:35:04.52#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:04.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:04.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:04.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:04.52#ibcon#enter wrdev, iclass 20, count 0 2006.201.08:35:04.52#ibcon#first serial, iclass 20, count 0 2006.201.08:35:04.52#ibcon#enter sib2, iclass 20, count 0 2006.201.08:35:04.52#ibcon#flushed, iclass 20, count 0 2006.201.08:35:04.52#ibcon#about to write, iclass 20, count 0 2006.201.08:35:04.52#ibcon#wrote, iclass 20, count 0 2006.201.08:35:04.52#ibcon#about to read 3, iclass 20, count 0 2006.201.08:35:04.54#ibcon#read 3, iclass 20, count 0 2006.201.08:35:04.54#ibcon#about to read 4, iclass 20, count 0 2006.201.08:35:04.54#ibcon#read 4, iclass 20, count 0 2006.201.08:35:04.54#ibcon#about to read 5, iclass 20, count 0 2006.201.08:35:04.54#ibcon#read 5, iclass 20, count 0 2006.201.08:35:04.54#ibcon#about to read 6, iclass 20, count 0 2006.201.08:35:04.54#ibcon#read 6, iclass 20, count 0 2006.201.08:35:04.54#ibcon#end of sib2, iclass 20, count 0 2006.201.08:35:04.54#ibcon#*mode == 0, iclass 20, count 0 2006.201.08:35:04.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.08:35:04.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:35:04.54#ibcon#*before write, iclass 20, count 0 2006.201.08:35:04.54#ibcon#enter sib2, iclass 20, count 0 2006.201.08:35:04.54#ibcon#flushed, iclass 20, count 0 2006.201.08:35:04.54#ibcon#about to write, iclass 20, count 0 2006.201.08:35:04.54#ibcon#wrote, iclass 20, count 0 2006.201.08:35:04.54#ibcon#about to read 3, iclass 20, count 0 2006.201.08:35:04.59#ibcon#read 3, iclass 20, count 0 2006.201.08:35:04.59#ibcon#about to read 4, iclass 20, count 0 2006.201.08:35:04.59#ibcon#read 4, iclass 20, count 0 2006.201.08:35:04.59#ibcon#about to read 5, iclass 20, count 0 2006.201.08:35:04.59#ibcon#read 5, iclass 20, count 0 2006.201.08:35:04.59#ibcon#about to read 6, iclass 20, count 0 2006.201.08:35:04.59#ibcon#read 6, iclass 20, count 0 2006.201.08:35:04.59#ibcon#end of sib2, iclass 20, count 0 2006.201.08:35:04.59#ibcon#*after write, iclass 20, count 0 2006.201.08:35:04.59#ibcon#*before return 0, iclass 20, count 0 2006.201.08:35:04.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:04.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:35:04.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.08:35:04.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.08:35:04.59$vck44/vb=4,5 2006.201.08:35:04.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.08:35:04.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.08:35:04.59#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:04.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:04.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:04.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:04.64#ibcon#enter wrdev, iclass 22, count 2 2006.201.08:35:04.64#ibcon#first serial, iclass 22, count 2 2006.201.08:35:04.64#ibcon#enter sib2, iclass 22, count 2 2006.201.08:35:04.64#ibcon#flushed, iclass 22, count 2 2006.201.08:35:04.64#ibcon#about to write, iclass 22, count 2 2006.201.08:35:04.64#ibcon#wrote, iclass 22, count 2 2006.201.08:35:04.64#ibcon#about to read 3, iclass 22, count 2 2006.201.08:35:04.66#ibcon#read 3, iclass 22, count 2 2006.201.08:35:04.66#ibcon#about to read 4, iclass 22, count 2 2006.201.08:35:04.66#ibcon#read 4, iclass 22, count 2 2006.201.08:35:04.66#ibcon#about to read 5, iclass 22, count 2 2006.201.08:35:04.66#ibcon#read 5, iclass 22, count 2 2006.201.08:35:04.66#ibcon#about to read 6, iclass 22, count 2 2006.201.08:35:04.66#ibcon#read 6, iclass 22, count 2 2006.201.08:35:04.66#ibcon#end of sib2, iclass 22, count 2 2006.201.08:35:04.66#ibcon#*mode == 0, iclass 22, count 2 2006.201.08:35:04.66#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.08:35:04.66#ibcon#[27=AT04-05\r\n] 2006.201.08:35:04.66#ibcon#*before write, iclass 22, count 2 2006.201.08:35:04.66#ibcon#enter sib2, iclass 22, count 2 2006.201.08:35:04.66#ibcon#flushed, iclass 22, count 2 2006.201.08:35:04.66#ibcon#about to write, iclass 22, count 2 2006.201.08:35:04.66#ibcon#wrote, iclass 22, count 2 2006.201.08:35:04.66#ibcon#about to read 3, iclass 22, count 2 2006.201.08:35:04.69#ibcon#read 3, iclass 22, count 2 2006.201.08:35:04.69#ibcon#about to read 4, iclass 22, count 2 2006.201.08:35:04.69#ibcon#read 4, iclass 22, count 2 2006.201.08:35:04.69#ibcon#about to read 5, iclass 22, count 2 2006.201.08:35:04.69#ibcon#read 5, iclass 22, count 2 2006.201.08:35:04.69#ibcon#about to read 6, iclass 22, count 2 2006.201.08:35:04.69#ibcon#read 6, iclass 22, count 2 2006.201.08:35:04.69#ibcon#end of sib2, iclass 22, count 2 2006.201.08:35:04.69#ibcon#*after write, iclass 22, count 2 2006.201.08:35:04.69#ibcon#*before return 0, iclass 22, count 2 2006.201.08:35:04.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:04.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:35:04.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.08:35:04.69#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:04.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:04.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:04.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:04.81#ibcon#enter wrdev, iclass 22, count 0 2006.201.08:35:04.81#ibcon#first serial, iclass 22, count 0 2006.201.08:35:04.81#ibcon#enter sib2, iclass 22, count 0 2006.201.08:35:04.81#ibcon#flushed, iclass 22, count 0 2006.201.08:35:04.81#ibcon#about to write, iclass 22, count 0 2006.201.08:35:04.81#ibcon#wrote, iclass 22, count 0 2006.201.08:35:04.81#ibcon#about to read 3, iclass 22, count 0 2006.201.08:35:04.83#ibcon#read 3, iclass 22, count 0 2006.201.08:35:04.83#ibcon#about to read 4, iclass 22, count 0 2006.201.08:35:04.83#ibcon#read 4, iclass 22, count 0 2006.201.08:35:04.83#ibcon#about to read 5, iclass 22, count 0 2006.201.08:35:04.83#ibcon#read 5, iclass 22, count 0 2006.201.08:35:04.83#ibcon#about to read 6, iclass 22, count 0 2006.201.08:35:04.83#ibcon#read 6, iclass 22, count 0 2006.201.08:35:04.83#ibcon#end of sib2, iclass 22, count 0 2006.201.08:35:04.83#ibcon#*mode == 0, iclass 22, count 0 2006.201.08:35:04.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.08:35:04.83#ibcon#[27=USB\r\n] 2006.201.08:35:04.83#ibcon#*before write, iclass 22, count 0 2006.201.08:35:04.83#ibcon#enter sib2, iclass 22, count 0 2006.201.08:35:04.83#ibcon#flushed, iclass 22, count 0 2006.201.08:35:04.83#ibcon#about to write, iclass 22, count 0 2006.201.08:35:04.83#ibcon#wrote, iclass 22, count 0 2006.201.08:35:04.83#ibcon#about to read 3, iclass 22, count 0 2006.201.08:35:04.86#ibcon#read 3, iclass 22, count 0 2006.201.08:35:04.86#ibcon#about to read 4, iclass 22, count 0 2006.201.08:35:04.86#ibcon#read 4, iclass 22, count 0 2006.201.08:35:04.86#ibcon#about to read 5, iclass 22, count 0 2006.201.08:35:04.86#ibcon#read 5, iclass 22, count 0 2006.201.08:35:04.86#ibcon#about to read 6, iclass 22, count 0 2006.201.08:35:04.86#ibcon#read 6, iclass 22, count 0 2006.201.08:35:04.86#ibcon#end of sib2, iclass 22, count 0 2006.201.08:35:04.86#ibcon#*after write, iclass 22, count 0 2006.201.08:35:04.86#ibcon#*before return 0, iclass 22, count 0 2006.201.08:35:04.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:04.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:35:04.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.08:35:04.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.08:35:04.86$vck44/vblo=5,709.99 2006.201.08:35:04.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.08:35:04.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.08:35:04.86#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:04.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:04.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:04.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:04.86#ibcon#enter wrdev, iclass 24, count 0 2006.201.08:35:04.86#ibcon#first serial, iclass 24, count 0 2006.201.08:35:04.86#ibcon#enter sib2, iclass 24, count 0 2006.201.08:35:04.86#ibcon#flushed, iclass 24, count 0 2006.201.08:35:04.86#ibcon#about to write, iclass 24, count 0 2006.201.08:35:04.86#ibcon#wrote, iclass 24, count 0 2006.201.08:35:04.86#ibcon#about to read 3, iclass 24, count 0 2006.201.08:35:04.88#ibcon#read 3, iclass 24, count 0 2006.201.08:35:04.88#ibcon#about to read 4, iclass 24, count 0 2006.201.08:35:04.88#ibcon#read 4, iclass 24, count 0 2006.201.08:35:04.88#ibcon#about to read 5, iclass 24, count 0 2006.201.08:35:04.88#ibcon#read 5, iclass 24, count 0 2006.201.08:35:04.88#ibcon#about to read 6, iclass 24, count 0 2006.201.08:35:04.88#ibcon#read 6, iclass 24, count 0 2006.201.08:35:04.88#ibcon#end of sib2, iclass 24, count 0 2006.201.08:35:04.88#ibcon#*mode == 0, iclass 24, count 0 2006.201.08:35:04.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.08:35:04.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:35:04.88#ibcon#*before write, iclass 24, count 0 2006.201.08:35:04.88#ibcon#enter sib2, iclass 24, count 0 2006.201.08:35:04.88#ibcon#flushed, iclass 24, count 0 2006.201.08:35:04.88#ibcon#about to write, iclass 24, count 0 2006.201.08:35:04.88#ibcon#wrote, iclass 24, count 0 2006.201.08:35:04.88#ibcon#about to read 3, iclass 24, count 0 2006.201.08:35:04.92#ibcon#read 3, iclass 24, count 0 2006.201.08:35:04.92#ibcon#about to read 4, iclass 24, count 0 2006.201.08:35:04.92#ibcon#read 4, iclass 24, count 0 2006.201.08:35:04.92#ibcon#about to read 5, iclass 24, count 0 2006.201.08:35:04.92#ibcon#read 5, iclass 24, count 0 2006.201.08:35:04.92#ibcon#about to read 6, iclass 24, count 0 2006.201.08:35:04.92#ibcon#read 6, iclass 24, count 0 2006.201.08:35:04.92#ibcon#end of sib2, iclass 24, count 0 2006.201.08:35:04.92#ibcon#*after write, iclass 24, count 0 2006.201.08:35:04.92#ibcon#*before return 0, iclass 24, count 0 2006.201.08:35:04.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:04.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:35:04.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.08:35:04.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.08:35:04.92$vck44/vb=5,4 2006.201.08:35:04.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.08:35:04.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.08:35:04.92#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:04.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:04.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:04.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:04.98#ibcon#enter wrdev, iclass 26, count 2 2006.201.08:35:04.98#ibcon#first serial, iclass 26, count 2 2006.201.08:35:04.98#ibcon#enter sib2, iclass 26, count 2 2006.201.08:35:04.98#ibcon#flushed, iclass 26, count 2 2006.201.08:35:04.98#ibcon#about to write, iclass 26, count 2 2006.201.08:35:04.98#ibcon#wrote, iclass 26, count 2 2006.201.08:35:04.98#ibcon#about to read 3, iclass 26, count 2 2006.201.08:35:05.00#ibcon#read 3, iclass 26, count 2 2006.201.08:35:05.00#ibcon#about to read 4, iclass 26, count 2 2006.201.08:35:05.00#ibcon#read 4, iclass 26, count 2 2006.201.08:35:05.00#ibcon#about to read 5, iclass 26, count 2 2006.201.08:35:05.00#ibcon#read 5, iclass 26, count 2 2006.201.08:35:05.00#ibcon#about to read 6, iclass 26, count 2 2006.201.08:35:05.00#ibcon#read 6, iclass 26, count 2 2006.201.08:35:05.00#ibcon#end of sib2, iclass 26, count 2 2006.201.08:35:05.00#ibcon#*mode == 0, iclass 26, count 2 2006.201.08:35:05.00#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.08:35:05.00#ibcon#[27=AT05-04\r\n] 2006.201.08:35:05.00#ibcon#*before write, iclass 26, count 2 2006.201.08:35:05.00#ibcon#enter sib2, iclass 26, count 2 2006.201.08:35:05.00#ibcon#flushed, iclass 26, count 2 2006.201.08:35:05.00#ibcon#about to write, iclass 26, count 2 2006.201.08:35:05.00#ibcon#wrote, iclass 26, count 2 2006.201.08:35:05.00#ibcon#about to read 3, iclass 26, count 2 2006.201.08:35:05.03#ibcon#read 3, iclass 26, count 2 2006.201.08:35:05.03#ibcon#about to read 4, iclass 26, count 2 2006.201.08:35:05.03#ibcon#read 4, iclass 26, count 2 2006.201.08:35:05.03#ibcon#about to read 5, iclass 26, count 2 2006.201.08:35:05.03#ibcon#read 5, iclass 26, count 2 2006.201.08:35:05.03#ibcon#about to read 6, iclass 26, count 2 2006.201.08:35:05.03#ibcon#read 6, iclass 26, count 2 2006.201.08:35:05.03#ibcon#end of sib2, iclass 26, count 2 2006.201.08:35:05.03#ibcon#*after write, iclass 26, count 2 2006.201.08:35:05.03#ibcon#*before return 0, iclass 26, count 2 2006.201.08:35:05.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:05.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:35:05.03#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.08:35:05.03#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:05.03#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:05.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:05.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:05.15#ibcon#enter wrdev, iclass 26, count 0 2006.201.08:35:05.15#ibcon#first serial, iclass 26, count 0 2006.201.08:35:05.15#ibcon#enter sib2, iclass 26, count 0 2006.201.08:35:05.15#ibcon#flushed, iclass 26, count 0 2006.201.08:35:05.15#ibcon#about to write, iclass 26, count 0 2006.201.08:35:05.15#ibcon#wrote, iclass 26, count 0 2006.201.08:35:05.15#ibcon#about to read 3, iclass 26, count 0 2006.201.08:35:05.17#ibcon#read 3, iclass 26, count 0 2006.201.08:35:05.17#ibcon#about to read 4, iclass 26, count 0 2006.201.08:35:05.17#ibcon#read 4, iclass 26, count 0 2006.201.08:35:05.17#ibcon#about to read 5, iclass 26, count 0 2006.201.08:35:05.17#ibcon#read 5, iclass 26, count 0 2006.201.08:35:05.17#ibcon#about to read 6, iclass 26, count 0 2006.201.08:35:05.17#ibcon#read 6, iclass 26, count 0 2006.201.08:35:05.17#ibcon#end of sib2, iclass 26, count 0 2006.201.08:35:05.17#ibcon#*mode == 0, iclass 26, count 0 2006.201.08:35:05.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.08:35:05.17#ibcon#[27=USB\r\n] 2006.201.08:35:05.17#ibcon#*before write, iclass 26, count 0 2006.201.08:35:05.17#ibcon#enter sib2, iclass 26, count 0 2006.201.08:35:05.17#ibcon#flushed, iclass 26, count 0 2006.201.08:35:05.17#ibcon#about to write, iclass 26, count 0 2006.201.08:35:05.17#ibcon#wrote, iclass 26, count 0 2006.201.08:35:05.17#ibcon#about to read 3, iclass 26, count 0 2006.201.08:35:05.20#ibcon#read 3, iclass 26, count 0 2006.201.08:35:05.20#ibcon#about to read 4, iclass 26, count 0 2006.201.08:35:05.20#ibcon#read 4, iclass 26, count 0 2006.201.08:35:05.20#ibcon#about to read 5, iclass 26, count 0 2006.201.08:35:05.20#ibcon#read 5, iclass 26, count 0 2006.201.08:35:05.20#ibcon#about to read 6, iclass 26, count 0 2006.201.08:35:05.20#ibcon#read 6, iclass 26, count 0 2006.201.08:35:05.20#ibcon#end of sib2, iclass 26, count 0 2006.201.08:35:05.20#ibcon#*after write, iclass 26, count 0 2006.201.08:35:05.20#ibcon#*before return 0, iclass 26, count 0 2006.201.08:35:05.20#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:05.20#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:35:05.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.08:35:05.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.08:35:05.20$vck44/vblo=6,719.99 2006.201.08:35:05.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.08:35:05.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.08:35:05.20#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:05.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:05.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:05.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:05.20#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:35:05.20#ibcon#first serial, iclass 28, count 0 2006.201.08:35:05.20#ibcon#enter sib2, iclass 28, count 0 2006.201.08:35:05.20#ibcon#flushed, iclass 28, count 0 2006.201.08:35:05.20#ibcon#about to write, iclass 28, count 0 2006.201.08:35:05.20#ibcon#wrote, iclass 28, count 0 2006.201.08:35:05.20#ibcon#about to read 3, iclass 28, count 0 2006.201.08:35:05.22#ibcon#read 3, iclass 28, count 0 2006.201.08:35:05.22#ibcon#about to read 4, iclass 28, count 0 2006.201.08:35:05.22#ibcon#read 4, iclass 28, count 0 2006.201.08:35:05.22#ibcon#about to read 5, iclass 28, count 0 2006.201.08:35:05.22#ibcon#read 5, iclass 28, count 0 2006.201.08:35:05.22#ibcon#about to read 6, iclass 28, count 0 2006.201.08:35:05.22#ibcon#read 6, iclass 28, count 0 2006.201.08:35:05.22#ibcon#end of sib2, iclass 28, count 0 2006.201.08:35:05.22#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:35:05.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:35:05.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:35:05.22#ibcon#*before write, iclass 28, count 0 2006.201.08:35:05.22#ibcon#enter sib2, iclass 28, count 0 2006.201.08:35:05.22#ibcon#flushed, iclass 28, count 0 2006.201.08:35:05.22#ibcon#about to write, iclass 28, count 0 2006.201.08:35:05.22#ibcon#wrote, iclass 28, count 0 2006.201.08:35:05.22#ibcon#about to read 3, iclass 28, count 0 2006.201.08:35:05.26#ibcon#read 3, iclass 28, count 0 2006.201.08:35:05.26#ibcon#about to read 4, iclass 28, count 0 2006.201.08:35:05.26#ibcon#read 4, iclass 28, count 0 2006.201.08:35:05.26#ibcon#about to read 5, iclass 28, count 0 2006.201.08:35:05.26#ibcon#read 5, iclass 28, count 0 2006.201.08:35:05.26#ibcon#about to read 6, iclass 28, count 0 2006.201.08:35:05.26#ibcon#read 6, iclass 28, count 0 2006.201.08:35:05.26#ibcon#end of sib2, iclass 28, count 0 2006.201.08:35:05.26#ibcon#*after write, iclass 28, count 0 2006.201.08:35:05.26#ibcon#*before return 0, iclass 28, count 0 2006.201.08:35:05.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:05.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:35:05.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:35:05.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:35:05.26$vck44/vb=6,4 2006.201.08:35:05.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.08:35:05.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.08:35:05.26#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:05.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:05.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:05.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:05.32#ibcon#enter wrdev, iclass 30, count 2 2006.201.08:35:05.32#ibcon#first serial, iclass 30, count 2 2006.201.08:35:05.32#ibcon#enter sib2, iclass 30, count 2 2006.201.08:35:05.32#ibcon#flushed, iclass 30, count 2 2006.201.08:35:05.32#ibcon#about to write, iclass 30, count 2 2006.201.08:35:05.32#ibcon#wrote, iclass 30, count 2 2006.201.08:35:05.32#ibcon#about to read 3, iclass 30, count 2 2006.201.08:35:05.34#ibcon#read 3, iclass 30, count 2 2006.201.08:35:05.34#ibcon#about to read 4, iclass 30, count 2 2006.201.08:35:05.34#ibcon#read 4, iclass 30, count 2 2006.201.08:35:05.34#ibcon#about to read 5, iclass 30, count 2 2006.201.08:35:05.34#ibcon#read 5, iclass 30, count 2 2006.201.08:35:05.34#ibcon#about to read 6, iclass 30, count 2 2006.201.08:35:05.34#ibcon#read 6, iclass 30, count 2 2006.201.08:35:05.34#ibcon#end of sib2, iclass 30, count 2 2006.201.08:35:05.34#ibcon#*mode == 0, iclass 30, count 2 2006.201.08:35:05.34#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.08:35:05.34#ibcon#[27=AT06-04\r\n] 2006.201.08:35:05.34#ibcon#*before write, iclass 30, count 2 2006.201.08:35:05.34#ibcon#enter sib2, iclass 30, count 2 2006.201.08:35:05.34#ibcon#flushed, iclass 30, count 2 2006.201.08:35:05.34#ibcon#about to write, iclass 30, count 2 2006.201.08:35:05.34#ibcon#wrote, iclass 30, count 2 2006.201.08:35:05.34#ibcon#about to read 3, iclass 30, count 2 2006.201.08:35:05.37#ibcon#read 3, iclass 30, count 2 2006.201.08:35:05.37#ibcon#about to read 4, iclass 30, count 2 2006.201.08:35:05.37#ibcon#read 4, iclass 30, count 2 2006.201.08:35:05.37#ibcon#about to read 5, iclass 30, count 2 2006.201.08:35:05.37#ibcon#read 5, iclass 30, count 2 2006.201.08:35:05.37#ibcon#about to read 6, iclass 30, count 2 2006.201.08:35:05.37#ibcon#read 6, iclass 30, count 2 2006.201.08:35:05.37#ibcon#end of sib2, iclass 30, count 2 2006.201.08:35:05.37#ibcon#*after write, iclass 30, count 2 2006.201.08:35:05.37#ibcon#*before return 0, iclass 30, count 2 2006.201.08:35:05.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:05.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:35:05.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.08:35:05.37#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:05.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:05.49#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:05.49#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:05.49#ibcon#enter wrdev, iclass 30, count 0 2006.201.08:35:05.49#ibcon#first serial, iclass 30, count 0 2006.201.08:35:05.49#ibcon#enter sib2, iclass 30, count 0 2006.201.08:35:05.49#ibcon#flushed, iclass 30, count 0 2006.201.08:35:05.49#ibcon#about to write, iclass 30, count 0 2006.201.08:35:05.49#ibcon#wrote, iclass 30, count 0 2006.201.08:35:05.49#ibcon#about to read 3, iclass 30, count 0 2006.201.08:35:05.51#ibcon#read 3, iclass 30, count 0 2006.201.08:35:05.51#ibcon#about to read 4, iclass 30, count 0 2006.201.08:35:05.51#ibcon#read 4, iclass 30, count 0 2006.201.08:35:05.51#ibcon#about to read 5, iclass 30, count 0 2006.201.08:35:05.51#ibcon#read 5, iclass 30, count 0 2006.201.08:35:05.51#ibcon#about to read 6, iclass 30, count 0 2006.201.08:35:05.51#ibcon#read 6, iclass 30, count 0 2006.201.08:35:05.51#ibcon#end of sib2, iclass 30, count 0 2006.201.08:35:05.51#ibcon#*mode == 0, iclass 30, count 0 2006.201.08:35:05.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.08:35:05.51#ibcon#[27=USB\r\n] 2006.201.08:35:05.51#ibcon#*before write, iclass 30, count 0 2006.201.08:35:05.51#ibcon#enter sib2, iclass 30, count 0 2006.201.08:35:05.51#ibcon#flushed, iclass 30, count 0 2006.201.08:35:05.51#ibcon#about to write, iclass 30, count 0 2006.201.08:35:05.51#ibcon#wrote, iclass 30, count 0 2006.201.08:35:05.51#ibcon#about to read 3, iclass 30, count 0 2006.201.08:35:05.54#ibcon#read 3, iclass 30, count 0 2006.201.08:35:05.54#ibcon#about to read 4, iclass 30, count 0 2006.201.08:35:05.54#ibcon#read 4, iclass 30, count 0 2006.201.08:35:05.54#ibcon#about to read 5, iclass 30, count 0 2006.201.08:35:05.54#ibcon#read 5, iclass 30, count 0 2006.201.08:35:05.54#ibcon#about to read 6, iclass 30, count 0 2006.201.08:35:05.54#ibcon#read 6, iclass 30, count 0 2006.201.08:35:05.54#ibcon#end of sib2, iclass 30, count 0 2006.201.08:35:05.54#ibcon#*after write, iclass 30, count 0 2006.201.08:35:05.54#ibcon#*before return 0, iclass 30, count 0 2006.201.08:35:05.54#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:05.54#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:35:05.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.08:35:05.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.08:35:05.54$vck44/vblo=7,734.99 2006.201.08:35:05.54#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.08:35:05.54#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.08:35:05.54#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:05.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:05.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:05.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:05.54#ibcon#enter wrdev, iclass 32, count 0 2006.201.08:35:05.54#ibcon#first serial, iclass 32, count 0 2006.201.08:35:05.54#ibcon#enter sib2, iclass 32, count 0 2006.201.08:35:05.54#ibcon#flushed, iclass 32, count 0 2006.201.08:35:05.54#ibcon#about to write, iclass 32, count 0 2006.201.08:35:05.54#ibcon#wrote, iclass 32, count 0 2006.201.08:35:05.54#ibcon#about to read 3, iclass 32, count 0 2006.201.08:35:05.56#ibcon#read 3, iclass 32, count 0 2006.201.08:35:05.56#ibcon#about to read 4, iclass 32, count 0 2006.201.08:35:05.56#ibcon#read 4, iclass 32, count 0 2006.201.08:35:05.56#ibcon#about to read 5, iclass 32, count 0 2006.201.08:35:05.56#ibcon#read 5, iclass 32, count 0 2006.201.08:35:05.56#ibcon#about to read 6, iclass 32, count 0 2006.201.08:35:05.56#ibcon#read 6, iclass 32, count 0 2006.201.08:35:05.56#ibcon#end of sib2, iclass 32, count 0 2006.201.08:35:05.56#ibcon#*mode == 0, iclass 32, count 0 2006.201.08:35:05.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.08:35:05.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:35:05.56#ibcon#*before write, iclass 32, count 0 2006.201.08:35:05.56#ibcon#enter sib2, iclass 32, count 0 2006.201.08:35:05.56#ibcon#flushed, iclass 32, count 0 2006.201.08:35:05.56#ibcon#about to write, iclass 32, count 0 2006.201.08:35:05.56#ibcon#wrote, iclass 32, count 0 2006.201.08:35:05.56#ibcon#about to read 3, iclass 32, count 0 2006.201.08:35:05.60#ibcon#read 3, iclass 32, count 0 2006.201.08:35:05.60#ibcon#about to read 4, iclass 32, count 0 2006.201.08:35:05.60#ibcon#read 4, iclass 32, count 0 2006.201.08:35:05.60#ibcon#about to read 5, iclass 32, count 0 2006.201.08:35:05.60#ibcon#read 5, iclass 32, count 0 2006.201.08:35:05.60#ibcon#about to read 6, iclass 32, count 0 2006.201.08:35:05.60#ibcon#read 6, iclass 32, count 0 2006.201.08:35:05.60#ibcon#end of sib2, iclass 32, count 0 2006.201.08:35:05.60#ibcon#*after write, iclass 32, count 0 2006.201.08:35:05.60#ibcon#*before return 0, iclass 32, count 0 2006.201.08:35:05.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:05.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:35:05.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.08:35:05.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.08:35:05.60$vck44/vb=7,4 2006.201.08:35:05.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.08:35:05.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.08:35:05.60#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:05.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:05.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:05.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:05.66#ibcon#enter wrdev, iclass 34, count 2 2006.201.08:35:05.66#ibcon#first serial, iclass 34, count 2 2006.201.08:35:05.66#ibcon#enter sib2, iclass 34, count 2 2006.201.08:35:05.66#ibcon#flushed, iclass 34, count 2 2006.201.08:35:05.66#ibcon#about to write, iclass 34, count 2 2006.201.08:35:05.66#ibcon#wrote, iclass 34, count 2 2006.201.08:35:05.66#ibcon#about to read 3, iclass 34, count 2 2006.201.08:35:05.68#ibcon#read 3, iclass 34, count 2 2006.201.08:35:05.68#ibcon#about to read 4, iclass 34, count 2 2006.201.08:35:05.68#ibcon#read 4, iclass 34, count 2 2006.201.08:35:05.68#ibcon#about to read 5, iclass 34, count 2 2006.201.08:35:05.68#ibcon#read 5, iclass 34, count 2 2006.201.08:35:05.68#ibcon#about to read 6, iclass 34, count 2 2006.201.08:35:05.68#ibcon#read 6, iclass 34, count 2 2006.201.08:35:05.68#ibcon#end of sib2, iclass 34, count 2 2006.201.08:35:05.68#ibcon#*mode == 0, iclass 34, count 2 2006.201.08:35:05.68#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.08:35:05.68#ibcon#[27=AT07-04\r\n] 2006.201.08:35:05.68#ibcon#*before write, iclass 34, count 2 2006.201.08:35:05.68#ibcon#enter sib2, iclass 34, count 2 2006.201.08:35:05.68#ibcon#flushed, iclass 34, count 2 2006.201.08:35:05.68#ibcon#about to write, iclass 34, count 2 2006.201.08:35:05.68#ibcon#wrote, iclass 34, count 2 2006.201.08:35:05.68#ibcon#about to read 3, iclass 34, count 2 2006.201.08:35:05.71#ibcon#read 3, iclass 34, count 2 2006.201.08:35:05.71#ibcon#about to read 4, iclass 34, count 2 2006.201.08:35:05.71#ibcon#read 4, iclass 34, count 2 2006.201.08:35:05.71#ibcon#about to read 5, iclass 34, count 2 2006.201.08:35:05.71#ibcon#read 5, iclass 34, count 2 2006.201.08:35:05.71#ibcon#about to read 6, iclass 34, count 2 2006.201.08:35:05.71#ibcon#read 6, iclass 34, count 2 2006.201.08:35:05.71#ibcon#end of sib2, iclass 34, count 2 2006.201.08:35:05.71#ibcon#*after write, iclass 34, count 2 2006.201.08:35:05.71#ibcon#*before return 0, iclass 34, count 2 2006.201.08:35:05.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:05.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:35:05.71#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.08:35:05.71#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:05.71#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:05.83#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:05.83#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:05.83#ibcon#enter wrdev, iclass 34, count 0 2006.201.08:35:05.83#ibcon#first serial, iclass 34, count 0 2006.201.08:35:05.83#ibcon#enter sib2, iclass 34, count 0 2006.201.08:35:05.83#ibcon#flushed, iclass 34, count 0 2006.201.08:35:05.83#ibcon#about to write, iclass 34, count 0 2006.201.08:35:05.83#ibcon#wrote, iclass 34, count 0 2006.201.08:35:05.83#ibcon#about to read 3, iclass 34, count 0 2006.201.08:35:05.85#ibcon#read 3, iclass 34, count 0 2006.201.08:35:05.85#ibcon#about to read 4, iclass 34, count 0 2006.201.08:35:05.85#ibcon#read 4, iclass 34, count 0 2006.201.08:35:05.85#ibcon#about to read 5, iclass 34, count 0 2006.201.08:35:05.85#ibcon#read 5, iclass 34, count 0 2006.201.08:35:05.85#ibcon#about to read 6, iclass 34, count 0 2006.201.08:35:05.85#ibcon#read 6, iclass 34, count 0 2006.201.08:35:05.85#ibcon#end of sib2, iclass 34, count 0 2006.201.08:35:05.85#ibcon#*mode == 0, iclass 34, count 0 2006.201.08:35:05.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.08:35:05.85#ibcon#[27=USB\r\n] 2006.201.08:35:05.85#ibcon#*before write, iclass 34, count 0 2006.201.08:35:05.85#ibcon#enter sib2, iclass 34, count 0 2006.201.08:35:05.85#ibcon#flushed, iclass 34, count 0 2006.201.08:35:05.85#ibcon#about to write, iclass 34, count 0 2006.201.08:35:05.85#ibcon#wrote, iclass 34, count 0 2006.201.08:35:05.85#ibcon#about to read 3, iclass 34, count 0 2006.201.08:35:05.88#ibcon#read 3, iclass 34, count 0 2006.201.08:35:05.88#ibcon#about to read 4, iclass 34, count 0 2006.201.08:35:05.88#ibcon#read 4, iclass 34, count 0 2006.201.08:35:05.88#ibcon#about to read 5, iclass 34, count 0 2006.201.08:35:05.88#ibcon#read 5, iclass 34, count 0 2006.201.08:35:05.88#ibcon#about to read 6, iclass 34, count 0 2006.201.08:35:05.88#ibcon#read 6, iclass 34, count 0 2006.201.08:35:05.88#ibcon#end of sib2, iclass 34, count 0 2006.201.08:35:05.88#ibcon#*after write, iclass 34, count 0 2006.201.08:35:05.88#ibcon#*before return 0, iclass 34, count 0 2006.201.08:35:05.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:05.88#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:35:05.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.08:35:05.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.08:35:05.88$vck44/vblo=8,744.99 2006.201.08:35:05.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.08:35:05.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.08:35:05.88#ibcon#ireg 17 cls_cnt 0 2006.201.08:35:05.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:35:05.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:35:05.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:35:05.88#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:35:05.88#ibcon#first serial, iclass 37, count 0 2006.201.08:35:05.88#ibcon#enter sib2, iclass 37, count 0 2006.201.08:35:05.88#ibcon#flushed, iclass 37, count 0 2006.201.08:35:05.88#ibcon#about to write, iclass 37, count 0 2006.201.08:35:05.88#ibcon#wrote, iclass 37, count 0 2006.201.08:35:05.88#ibcon#about to read 3, iclass 37, count 0 2006.201.08:35:05.89#abcon#<5=/04 2.7 4.6 23.14 891003.6\r\n> 2006.201.08:35:05.90#ibcon#read 3, iclass 37, count 0 2006.201.08:35:05.90#ibcon#about to read 4, iclass 37, count 0 2006.201.08:35:05.90#ibcon#read 4, iclass 37, count 0 2006.201.08:35:05.90#ibcon#about to read 5, iclass 37, count 0 2006.201.08:35:05.90#ibcon#read 5, iclass 37, count 0 2006.201.08:35:05.90#ibcon#about to read 6, iclass 37, count 0 2006.201.08:35:05.90#ibcon#read 6, iclass 37, count 0 2006.201.08:35:05.90#ibcon#end of sib2, iclass 37, count 0 2006.201.08:35:05.90#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:35:05.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:35:05.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:35:05.90#ibcon#*before write, iclass 37, count 0 2006.201.08:35:05.90#ibcon#enter sib2, iclass 37, count 0 2006.201.08:35:05.90#ibcon#flushed, iclass 37, count 0 2006.201.08:35:05.90#ibcon#about to write, iclass 37, count 0 2006.201.08:35:05.90#ibcon#wrote, iclass 37, count 0 2006.201.08:35:05.90#ibcon#about to read 3, iclass 37, count 0 2006.201.08:35:05.91#abcon#{5=INTERFACE CLEAR} 2006.201.08:35:05.94#ibcon#read 3, iclass 37, count 0 2006.201.08:35:05.94#ibcon#about to read 4, iclass 37, count 0 2006.201.08:35:05.94#ibcon#read 4, iclass 37, count 0 2006.201.08:35:05.94#ibcon#about to read 5, iclass 37, count 0 2006.201.08:35:05.94#ibcon#read 5, iclass 37, count 0 2006.201.08:35:05.94#ibcon#about to read 6, iclass 37, count 0 2006.201.08:35:05.94#ibcon#read 6, iclass 37, count 0 2006.201.08:35:05.94#ibcon#end of sib2, iclass 37, count 0 2006.201.08:35:05.94#ibcon#*after write, iclass 37, count 0 2006.201.08:35:05.94#ibcon#*before return 0, iclass 37, count 0 2006.201.08:35:05.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:35:05.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:35:05.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:35:05.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:35:05.94$vck44/vb=8,4 2006.201.08:35:05.94#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.08:35:05.94#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.08:35:05.94#ibcon#ireg 11 cls_cnt 2 2006.201.08:35:05.94#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:35:05.97#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:35:06.00#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:35:06.00#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:35:06.00#ibcon#enter wrdev, iclass 2, count 2 2006.201.08:35:06.00#ibcon#first serial, iclass 2, count 2 2006.201.08:35:06.00#ibcon#enter sib2, iclass 2, count 2 2006.201.08:35:06.00#ibcon#flushed, iclass 2, count 2 2006.201.08:35:06.00#ibcon#about to write, iclass 2, count 2 2006.201.08:35:06.00#ibcon#wrote, iclass 2, count 2 2006.201.08:35:06.00#ibcon#about to read 3, iclass 2, count 2 2006.201.08:35:06.02#ibcon#read 3, iclass 2, count 2 2006.201.08:35:06.02#ibcon#about to read 4, iclass 2, count 2 2006.201.08:35:06.02#ibcon#read 4, iclass 2, count 2 2006.201.08:35:06.02#ibcon#about to read 5, iclass 2, count 2 2006.201.08:35:06.02#ibcon#read 5, iclass 2, count 2 2006.201.08:35:06.02#ibcon#about to read 6, iclass 2, count 2 2006.201.08:35:06.02#ibcon#read 6, iclass 2, count 2 2006.201.08:35:06.02#ibcon#end of sib2, iclass 2, count 2 2006.201.08:35:06.02#ibcon#*mode == 0, iclass 2, count 2 2006.201.08:35:06.02#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.08:35:06.02#ibcon#[27=AT08-04\r\n] 2006.201.08:35:06.02#ibcon#*before write, iclass 2, count 2 2006.201.08:35:06.02#ibcon#enter sib2, iclass 2, count 2 2006.201.08:35:06.02#ibcon#flushed, iclass 2, count 2 2006.201.08:35:06.02#ibcon#about to write, iclass 2, count 2 2006.201.08:35:06.02#ibcon#wrote, iclass 2, count 2 2006.201.08:35:06.02#ibcon#about to read 3, iclass 2, count 2 2006.201.08:35:06.05#ibcon#read 3, iclass 2, count 2 2006.201.08:35:06.05#ibcon#about to read 4, iclass 2, count 2 2006.201.08:35:06.05#ibcon#read 4, iclass 2, count 2 2006.201.08:35:06.05#ibcon#about to read 5, iclass 2, count 2 2006.201.08:35:06.05#ibcon#read 5, iclass 2, count 2 2006.201.08:35:06.05#ibcon#about to read 6, iclass 2, count 2 2006.201.08:35:06.05#ibcon#read 6, iclass 2, count 2 2006.201.08:35:06.05#ibcon#end of sib2, iclass 2, count 2 2006.201.08:35:06.05#ibcon#*after write, iclass 2, count 2 2006.201.08:35:06.05#ibcon#*before return 0, iclass 2, count 2 2006.201.08:35:06.05#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:35:06.05#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:35:06.05#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.08:35:06.05#ibcon#ireg 7 cls_cnt 0 2006.201.08:35:06.05#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:35:06.17#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:35:06.17#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:35:06.17#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:35:06.17#ibcon#first serial, iclass 2, count 0 2006.201.08:35:06.17#ibcon#enter sib2, iclass 2, count 0 2006.201.08:35:06.17#ibcon#flushed, iclass 2, count 0 2006.201.08:35:06.17#ibcon#about to write, iclass 2, count 0 2006.201.08:35:06.17#ibcon#wrote, iclass 2, count 0 2006.201.08:35:06.17#ibcon#about to read 3, iclass 2, count 0 2006.201.08:35:06.20#ibcon#read 3, iclass 2, count 0 2006.201.08:35:06.20#ibcon#about to read 4, iclass 2, count 0 2006.201.08:35:06.20#ibcon#read 4, iclass 2, count 0 2006.201.08:35:06.20#ibcon#about to read 5, iclass 2, count 0 2006.201.08:35:06.20#ibcon#read 5, iclass 2, count 0 2006.201.08:35:06.20#ibcon#about to read 6, iclass 2, count 0 2006.201.08:35:06.20#ibcon#read 6, iclass 2, count 0 2006.201.08:35:06.20#ibcon#end of sib2, iclass 2, count 0 2006.201.08:35:06.20#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:35:06.20#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:35:06.20#ibcon#[27=USB\r\n] 2006.201.08:35:06.20#ibcon#*before write, iclass 2, count 0 2006.201.08:35:06.20#ibcon#enter sib2, iclass 2, count 0 2006.201.08:35:06.20#ibcon#flushed, iclass 2, count 0 2006.201.08:35:06.20#ibcon#about to write, iclass 2, count 0 2006.201.08:35:06.20#ibcon#wrote, iclass 2, count 0 2006.201.08:35:06.20#ibcon#about to read 3, iclass 2, count 0 2006.201.08:35:06.23#ibcon#read 3, iclass 2, count 0 2006.201.08:35:06.23#ibcon#about to read 4, iclass 2, count 0 2006.201.08:35:06.23#ibcon#read 4, iclass 2, count 0 2006.201.08:35:06.23#ibcon#about to read 5, iclass 2, count 0 2006.201.08:35:06.23#ibcon#read 5, iclass 2, count 0 2006.201.08:35:06.23#ibcon#about to read 6, iclass 2, count 0 2006.201.08:35:06.23#ibcon#read 6, iclass 2, count 0 2006.201.08:35:06.23#ibcon#end of sib2, iclass 2, count 0 2006.201.08:35:06.23#ibcon#*after write, iclass 2, count 0 2006.201.08:35:06.23#ibcon#*before return 0, iclass 2, count 0 2006.201.08:35:06.23#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:35:06.23#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:35:06.23#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:35:06.23#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:35:06.23$vck44/vabw=wide 2006.201.08:35:06.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.08:35:06.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.08:35:06.23#ibcon#ireg 8 cls_cnt 0 2006.201.08:35:06.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:06.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:06.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:06.23#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:35:06.23#ibcon#first serial, iclass 6, count 0 2006.201.08:35:06.23#ibcon#enter sib2, iclass 6, count 0 2006.201.08:35:06.23#ibcon#flushed, iclass 6, count 0 2006.201.08:35:06.23#ibcon#about to write, iclass 6, count 0 2006.201.08:35:06.23#ibcon#wrote, iclass 6, count 0 2006.201.08:35:06.23#ibcon#about to read 3, iclass 6, count 0 2006.201.08:35:06.25#ibcon#read 3, iclass 6, count 0 2006.201.08:35:06.25#ibcon#about to read 4, iclass 6, count 0 2006.201.08:35:06.25#ibcon#read 4, iclass 6, count 0 2006.201.08:35:06.25#ibcon#about to read 5, iclass 6, count 0 2006.201.08:35:06.25#ibcon#read 5, iclass 6, count 0 2006.201.08:35:06.25#ibcon#about to read 6, iclass 6, count 0 2006.201.08:35:06.25#ibcon#read 6, iclass 6, count 0 2006.201.08:35:06.25#ibcon#end of sib2, iclass 6, count 0 2006.201.08:35:06.25#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:35:06.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:35:06.25#ibcon#[25=BW32\r\n] 2006.201.08:35:06.25#ibcon#*before write, iclass 6, count 0 2006.201.08:35:06.25#ibcon#enter sib2, iclass 6, count 0 2006.201.08:35:06.25#ibcon#flushed, iclass 6, count 0 2006.201.08:35:06.25#ibcon#about to write, iclass 6, count 0 2006.201.08:35:06.25#ibcon#wrote, iclass 6, count 0 2006.201.08:35:06.25#ibcon#about to read 3, iclass 6, count 0 2006.201.08:35:06.28#ibcon#read 3, iclass 6, count 0 2006.201.08:35:06.28#ibcon#about to read 4, iclass 6, count 0 2006.201.08:35:06.28#ibcon#read 4, iclass 6, count 0 2006.201.08:35:06.28#ibcon#about to read 5, iclass 6, count 0 2006.201.08:35:06.28#ibcon#read 5, iclass 6, count 0 2006.201.08:35:06.28#ibcon#about to read 6, iclass 6, count 0 2006.201.08:35:06.28#ibcon#read 6, iclass 6, count 0 2006.201.08:35:06.28#ibcon#end of sib2, iclass 6, count 0 2006.201.08:35:06.28#ibcon#*after write, iclass 6, count 0 2006.201.08:35:06.28#ibcon#*before return 0, iclass 6, count 0 2006.201.08:35:06.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:06.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:35:06.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:35:06.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:35:06.28$vck44/vbbw=wide 2006.201.08:35:06.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.08:35:06.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.08:35:06.28#ibcon#ireg 8 cls_cnt 0 2006.201.08:35:06.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:35:06.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:35:06.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:35:06.35#ibcon#enter wrdev, iclass 10, count 0 2006.201.08:35:06.35#ibcon#first serial, iclass 10, count 0 2006.201.08:35:06.35#ibcon#enter sib2, iclass 10, count 0 2006.201.08:35:06.35#ibcon#flushed, iclass 10, count 0 2006.201.08:35:06.35#ibcon#about to write, iclass 10, count 0 2006.201.08:35:06.35#ibcon#wrote, iclass 10, count 0 2006.201.08:35:06.35#ibcon#about to read 3, iclass 10, count 0 2006.201.08:35:06.37#ibcon#read 3, iclass 10, count 0 2006.201.08:35:06.37#ibcon#about to read 4, iclass 10, count 0 2006.201.08:35:06.37#ibcon#read 4, iclass 10, count 0 2006.201.08:35:06.37#ibcon#about to read 5, iclass 10, count 0 2006.201.08:35:06.37#ibcon#read 5, iclass 10, count 0 2006.201.08:35:06.37#ibcon#about to read 6, iclass 10, count 0 2006.201.08:35:06.37#ibcon#read 6, iclass 10, count 0 2006.201.08:35:06.37#ibcon#end of sib2, iclass 10, count 0 2006.201.08:35:06.37#ibcon#*mode == 0, iclass 10, count 0 2006.201.08:35:06.37#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.08:35:06.37#ibcon#[27=BW32\r\n] 2006.201.08:35:06.37#ibcon#*before write, iclass 10, count 0 2006.201.08:35:06.37#ibcon#enter sib2, iclass 10, count 0 2006.201.08:35:06.37#ibcon#flushed, iclass 10, count 0 2006.201.08:35:06.37#ibcon#about to write, iclass 10, count 0 2006.201.08:35:06.37#ibcon#wrote, iclass 10, count 0 2006.201.08:35:06.37#ibcon#about to read 3, iclass 10, count 0 2006.201.08:35:06.40#ibcon#read 3, iclass 10, count 0 2006.201.08:35:06.40#ibcon#about to read 4, iclass 10, count 0 2006.201.08:35:06.40#ibcon#read 4, iclass 10, count 0 2006.201.08:35:06.40#ibcon#about to read 5, iclass 10, count 0 2006.201.08:35:06.40#ibcon#read 5, iclass 10, count 0 2006.201.08:35:06.40#ibcon#about to read 6, iclass 10, count 0 2006.201.08:35:06.40#ibcon#read 6, iclass 10, count 0 2006.201.08:35:06.40#ibcon#end of sib2, iclass 10, count 0 2006.201.08:35:06.40#ibcon#*after write, iclass 10, count 0 2006.201.08:35:06.40#ibcon#*before return 0, iclass 10, count 0 2006.201.08:35:06.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:35:06.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.08:35:06.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.08:35:06.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.08:35:06.40$setupk4/ifdk4 2006.201.08:35:06.40$ifdk4/lo= 2006.201.08:35:06.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:35:06.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:35:06.40$ifdk4/patch= 2006.201.08:35:06.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:35:06.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:35:06.40$setupk4/!*+20s 2006.201.08:35:16.06#abcon#<5=/04 2.7 4.6 23.14 891003.6\r\n> 2006.201.08:35:16.08#abcon#{5=INTERFACE CLEAR} 2006.201.08:35:16.14#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:35:20.87$setupk4/"tpicd 2006.201.08:35:20.87$setupk4/echo=off 2006.201.08:35:20.87$setupk4/xlog=off 2006.201.08:35:20.87:!2006.201.08:36:42 2006.201.08:35:27.13#trakl#Source acquired 2006.201.08:35:29.13#flagr#flagr/antenna,acquired 2006.201.08:36:42.00:preob 2006.201.08:36:42.14/onsource/TRACKING 2006.201.08:36:42.14:!2006.201.08:36:52 2006.201.08:36:52.00:"tape 2006.201.08:36:52.00:"st=record 2006.201.08:36:52.00:data_valid=on 2006.201.08:36:52.00:midob 2006.201.08:36:53.14/onsource/TRACKING 2006.201.08:36:53.14/wx/23.13,1003.6,89 2006.201.08:36:53.27/cable/+6.4657E-03 2006.201.08:36:54.36/va/01,08,usb,yes,27,30 2006.201.08:36:54.36/va/02,07,usb,yes,30,30 2006.201.08:36:54.36/va/03,08,usb,yes,27,28 2006.201.08:36:54.36/va/04,07,usb,yes,30,32 2006.201.08:36:54.36/va/05,04,usb,yes,27,27 2006.201.08:36:54.36/va/06,05,usb,yes,27,27 2006.201.08:36:54.36/va/07,05,usb,yes,26,27 2006.201.08:36:54.36/va/08,04,usb,yes,26,31 2006.201.08:36:54.59/valo/01,524.99,yes,locked 2006.201.08:36:54.59/valo/02,534.99,yes,locked 2006.201.08:36:54.59/valo/03,564.99,yes,locked 2006.201.08:36:54.59/valo/04,624.99,yes,locked 2006.201.08:36:54.59/valo/05,734.99,yes,locked 2006.201.08:36:54.59/valo/06,814.99,yes,locked 2006.201.08:36:54.59/valo/07,864.99,yes,locked 2006.201.08:36:54.59/valo/08,884.99,yes,locked 2006.201.08:36:55.68/vb/01,04,usb,yes,28,26 2006.201.08:36:55.68/vb/02,05,usb,yes,26,26 2006.201.08:36:55.68/vb/03,04,usb,yes,27,30 2006.201.08:36:55.68/vb/04,05,usb,yes,27,27 2006.201.08:36:55.68/vb/05,04,usb,yes,24,26 2006.201.08:36:55.68/vb/06,04,usb,yes,28,25 2006.201.08:36:55.68/vb/07,04,usb,yes,28,28 2006.201.08:36:55.68/vb/08,04,usb,yes,26,29 2006.201.08:36:55.92/vblo/01,629.99,yes,locked 2006.201.08:36:55.92/vblo/02,634.99,yes,locked 2006.201.08:36:55.92/vblo/03,649.99,yes,locked 2006.201.08:36:55.92/vblo/04,679.99,yes,locked 2006.201.08:36:55.92/vblo/05,709.99,yes,locked 2006.201.08:36:55.92/vblo/06,719.99,yes,locked 2006.201.08:36:55.92/vblo/07,734.99,yes,locked 2006.201.08:36:55.92/vblo/08,744.99,yes,locked 2006.201.08:36:56.07/vabw/8 2006.201.08:36:56.22/vbbw/8 2006.201.08:36:56.31/xfe/off,on,15.2 2006.201.08:36:56.69/ifatt/23,28,28,28 2006.201.08:36:57.05/fmout-gps/S +4.57E-07 2006.201.08:36:57.12:!2006.201.08:43:42 2006.201.08:43:42.00:data_valid=off 2006.201.08:43:42.00:"et 2006.201.08:43:42.00:!+3s 2006.201.08:43:45.02:"tape 2006.201.08:43:45.02:postob 2006.201.08:43:45.20/cable/+6.4661E-03 2006.201.08:43:45.20/wx/23.07,1003.6,89 2006.201.08:43:45.28/fmout-gps/S +4.56E-07 2006.201.08:43:45.28:scan_name=201-0844,jd0607,280 2006.201.08:43:45.28:source=1803+784,180045.68,782804.0,2000.0,cw 2006.201.08:43:46.13#flagr#flagr/antenna,new-source 2006.201.08:43:46.13:checkk5 2006.201.08:43:46.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:43:46.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:43:47.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:43:47.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:43:48.01/chk_obsdata//k5ts1/T2010836??a.dat file size is correct (nominal:1640MB, actual:1640MB). 2006.201.08:43:48.37/chk_obsdata//k5ts2/T2010836??b.dat file size is correct (nominal:1640MB, actual:1640MB). 2006.201.08:43:48.73/chk_obsdata//k5ts3/T2010836??c.dat file size is correct (nominal:1640MB, actual:1640MB). 2006.201.08:43:49.10/chk_obsdata//k5ts4/T2010836??d.dat file size is correct (nominal:1640MB, actual:1640MB). 2006.201.08:43:49.79/k5log//k5ts1_log_newline 2006.201.08:43:50.48/k5log//k5ts2_log_newline 2006.201.08:43:51.17/k5log//k5ts3_log_newline 2006.201.08:43:51.85/k5log//k5ts4_log_newline 2006.201.08:43:51.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:43:51.87:setupk4=1 2006.201.08:43:51.87$setupk4/echo=on 2006.201.08:43:51.87$setupk4/pcalon 2006.201.08:43:51.87$pcalon/"no phase cal control is implemented here 2006.201.08:43:51.87$setupk4/"tpicd=stop 2006.201.08:43:51.87$setupk4/"rec=synch_on 2006.201.08:43:51.87$setupk4/"rec_mode=128 2006.201.08:43:51.87$setupk4/!* 2006.201.08:43:51.87$setupk4/recpk4 2006.201.08:43:51.87$recpk4/recpatch= 2006.201.08:43:51.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:43:51.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:43:51.88$setupk4/vck44 2006.201.08:43:51.88$vck44/valo=1,524.99 2006.201.08:43:51.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.08:43:51.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.08:43:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:51.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:43:51.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:43:51.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:43:51.88#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:43:51.88#ibcon#first serial, iclass 39, count 0 2006.201.08:43:51.88#ibcon#enter sib2, iclass 39, count 0 2006.201.08:43:51.88#ibcon#flushed, iclass 39, count 0 2006.201.08:43:51.88#ibcon#about to write, iclass 39, count 0 2006.201.08:43:51.88#ibcon#wrote, iclass 39, count 0 2006.201.08:43:51.88#ibcon#about to read 3, iclass 39, count 0 2006.201.08:43:51.92#ibcon#read 3, iclass 39, count 0 2006.201.08:43:51.92#ibcon#about to read 4, iclass 39, count 0 2006.201.08:43:51.92#ibcon#read 4, iclass 39, count 0 2006.201.08:43:51.92#ibcon#about to read 5, iclass 39, count 0 2006.201.08:43:51.92#ibcon#read 5, iclass 39, count 0 2006.201.08:43:51.92#ibcon#about to read 6, iclass 39, count 0 2006.201.08:43:51.92#ibcon#read 6, iclass 39, count 0 2006.201.08:43:51.92#ibcon#end of sib2, iclass 39, count 0 2006.201.08:43:51.92#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:43:51.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:43:51.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:43:51.92#ibcon#*before write, iclass 39, count 0 2006.201.08:43:51.92#ibcon#enter sib2, iclass 39, count 0 2006.201.08:43:51.92#ibcon#flushed, iclass 39, count 0 2006.201.08:43:51.92#ibcon#about to write, iclass 39, count 0 2006.201.08:43:51.92#ibcon#wrote, iclass 39, count 0 2006.201.08:43:51.92#ibcon#about to read 3, iclass 39, count 0 2006.201.08:43:51.97#ibcon#read 3, iclass 39, count 0 2006.201.08:43:51.97#ibcon#about to read 4, iclass 39, count 0 2006.201.08:43:51.97#ibcon#read 4, iclass 39, count 0 2006.201.08:43:51.97#ibcon#about to read 5, iclass 39, count 0 2006.201.08:43:51.97#ibcon#read 5, iclass 39, count 0 2006.201.08:43:51.97#ibcon#about to read 6, iclass 39, count 0 2006.201.08:43:51.97#ibcon#read 6, iclass 39, count 0 2006.201.08:43:51.97#ibcon#end of sib2, iclass 39, count 0 2006.201.08:43:51.97#ibcon#*after write, iclass 39, count 0 2006.201.08:43:51.97#ibcon#*before return 0, iclass 39, count 0 2006.201.08:43:51.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:43:51.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.08:43:51.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:43:51.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:43:51.97$vck44/va=1,8 2006.201.08:43:51.97#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.08:43:51.97#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.08:43:51.97#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:51.97#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:43:51.97#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:43:51.97#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:43:51.97#ibcon#enter wrdev, iclass 2, count 2 2006.201.08:43:51.97#ibcon#first serial, iclass 2, count 2 2006.201.08:43:51.97#ibcon#enter sib2, iclass 2, count 2 2006.201.08:43:51.97#ibcon#flushed, iclass 2, count 2 2006.201.08:43:51.97#ibcon#about to write, iclass 2, count 2 2006.201.08:43:51.97#ibcon#wrote, iclass 2, count 2 2006.201.08:43:51.97#ibcon#about to read 3, iclass 2, count 2 2006.201.08:43:51.99#ibcon#read 3, iclass 2, count 2 2006.201.08:43:51.99#ibcon#about to read 4, iclass 2, count 2 2006.201.08:43:51.99#ibcon#read 4, iclass 2, count 2 2006.201.08:43:51.99#ibcon#about to read 5, iclass 2, count 2 2006.201.08:43:51.99#ibcon#read 5, iclass 2, count 2 2006.201.08:43:51.99#ibcon#about to read 6, iclass 2, count 2 2006.201.08:43:51.99#ibcon#read 6, iclass 2, count 2 2006.201.08:43:51.99#ibcon#end of sib2, iclass 2, count 2 2006.201.08:43:51.99#ibcon#*mode == 0, iclass 2, count 2 2006.201.08:43:51.99#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.08:43:51.99#ibcon#[25=AT01-08\r\n] 2006.201.08:43:51.99#ibcon#*before write, iclass 2, count 2 2006.201.08:43:51.99#ibcon#enter sib2, iclass 2, count 2 2006.201.08:43:51.99#ibcon#flushed, iclass 2, count 2 2006.201.08:43:51.99#ibcon#about to write, iclass 2, count 2 2006.201.08:43:51.99#ibcon#wrote, iclass 2, count 2 2006.201.08:43:51.99#ibcon#about to read 3, iclass 2, count 2 2006.201.08:43:52.03#ibcon#read 3, iclass 2, count 2 2006.201.08:43:52.03#ibcon#about to read 4, iclass 2, count 2 2006.201.08:43:52.03#ibcon#read 4, iclass 2, count 2 2006.201.08:43:52.03#ibcon#about to read 5, iclass 2, count 2 2006.201.08:43:52.03#ibcon#read 5, iclass 2, count 2 2006.201.08:43:52.03#ibcon#about to read 6, iclass 2, count 2 2006.201.08:43:52.03#ibcon#read 6, iclass 2, count 2 2006.201.08:43:52.03#ibcon#end of sib2, iclass 2, count 2 2006.201.08:43:52.03#ibcon#*after write, iclass 2, count 2 2006.201.08:43:52.03#ibcon#*before return 0, iclass 2, count 2 2006.201.08:43:52.03#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:43:52.03#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.08:43:52.03#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.08:43:52.03#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:52.03#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:43:52.15#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:43:52.15#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:43:52.15#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:43:52.15#ibcon#first serial, iclass 2, count 0 2006.201.08:43:52.15#ibcon#enter sib2, iclass 2, count 0 2006.201.08:43:52.15#ibcon#flushed, iclass 2, count 0 2006.201.08:43:52.15#ibcon#about to write, iclass 2, count 0 2006.201.08:43:52.15#ibcon#wrote, iclass 2, count 0 2006.201.08:43:52.15#ibcon#about to read 3, iclass 2, count 0 2006.201.08:43:52.17#ibcon#read 3, iclass 2, count 0 2006.201.08:43:52.17#ibcon#about to read 4, iclass 2, count 0 2006.201.08:43:52.17#ibcon#read 4, iclass 2, count 0 2006.201.08:43:52.17#ibcon#about to read 5, iclass 2, count 0 2006.201.08:43:52.17#ibcon#read 5, iclass 2, count 0 2006.201.08:43:52.17#ibcon#about to read 6, iclass 2, count 0 2006.201.08:43:52.17#ibcon#read 6, iclass 2, count 0 2006.201.08:43:52.17#ibcon#end of sib2, iclass 2, count 0 2006.201.08:43:52.17#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:43:52.17#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:43:52.17#ibcon#[25=USB\r\n] 2006.201.08:43:52.17#ibcon#*before write, iclass 2, count 0 2006.201.08:43:52.17#ibcon#enter sib2, iclass 2, count 0 2006.201.08:43:52.17#ibcon#flushed, iclass 2, count 0 2006.201.08:43:52.17#ibcon#about to write, iclass 2, count 0 2006.201.08:43:52.17#ibcon#wrote, iclass 2, count 0 2006.201.08:43:52.17#ibcon#about to read 3, iclass 2, count 0 2006.201.08:43:52.20#ibcon#read 3, iclass 2, count 0 2006.201.08:43:52.20#ibcon#about to read 4, iclass 2, count 0 2006.201.08:43:52.20#ibcon#read 4, iclass 2, count 0 2006.201.08:43:52.20#ibcon#about to read 5, iclass 2, count 0 2006.201.08:43:52.20#ibcon#read 5, iclass 2, count 0 2006.201.08:43:52.20#ibcon#about to read 6, iclass 2, count 0 2006.201.08:43:52.20#ibcon#read 6, iclass 2, count 0 2006.201.08:43:52.20#ibcon#end of sib2, iclass 2, count 0 2006.201.08:43:52.20#ibcon#*after write, iclass 2, count 0 2006.201.08:43:52.20#ibcon#*before return 0, iclass 2, count 0 2006.201.08:43:52.20#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:43:52.20#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.08:43:52.20#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:43:52.20#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:43:52.20$vck44/valo=2,534.99 2006.201.08:43:52.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.08:43:52.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.08:43:52.20#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:52.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:52.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:52.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:52.20#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:43:52.20#ibcon#first serial, iclass 5, count 0 2006.201.08:43:52.20#ibcon#enter sib2, iclass 5, count 0 2006.201.08:43:52.20#ibcon#flushed, iclass 5, count 0 2006.201.08:43:52.20#ibcon#about to write, iclass 5, count 0 2006.201.08:43:52.20#ibcon#wrote, iclass 5, count 0 2006.201.08:43:52.20#ibcon#about to read 3, iclass 5, count 0 2006.201.08:43:52.22#ibcon#read 3, iclass 5, count 0 2006.201.08:43:52.22#ibcon#about to read 4, iclass 5, count 0 2006.201.08:43:52.22#ibcon#read 4, iclass 5, count 0 2006.201.08:43:52.22#ibcon#about to read 5, iclass 5, count 0 2006.201.08:43:52.22#ibcon#read 5, iclass 5, count 0 2006.201.08:43:52.22#ibcon#about to read 6, iclass 5, count 0 2006.201.08:43:52.22#ibcon#read 6, iclass 5, count 0 2006.201.08:43:52.22#ibcon#end of sib2, iclass 5, count 0 2006.201.08:43:52.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:43:52.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:43:52.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:43:52.22#ibcon#*before write, iclass 5, count 0 2006.201.08:43:52.22#ibcon#enter sib2, iclass 5, count 0 2006.201.08:43:52.22#ibcon#flushed, iclass 5, count 0 2006.201.08:43:52.22#ibcon#about to write, iclass 5, count 0 2006.201.08:43:52.22#ibcon#wrote, iclass 5, count 0 2006.201.08:43:52.22#ibcon#about to read 3, iclass 5, count 0 2006.201.08:43:52.26#ibcon#read 3, iclass 5, count 0 2006.201.08:43:52.26#ibcon#about to read 4, iclass 5, count 0 2006.201.08:43:52.26#ibcon#read 4, iclass 5, count 0 2006.201.08:43:52.26#ibcon#about to read 5, iclass 5, count 0 2006.201.08:43:52.26#ibcon#read 5, iclass 5, count 0 2006.201.08:43:52.26#ibcon#about to read 6, iclass 5, count 0 2006.201.08:43:52.26#ibcon#read 6, iclass 5, count 0 2006.201.08:43:52.26#ibcon#end of sib2, iclass 5, count 0 2006.201.08:43:52.26#ibcon#*after write, iclass 5, count 0 2006.201.08:43:52.26#ibcon#*before return 0, iclass 5, count 0 2006.201.08:43:52.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:52.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:52.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:43:52.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:43:52.26$vck44/va=2,7 2006.201.08:43:52.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.08:43:52.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.08:43:52.26#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:52.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:52.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:52.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:52.32#ibcon#enter wrdev, iclass 7, count 2 2006.201.08:43:52.32#ibcon#first serial, iclass 7, count 2 2006.201.08:43:52.32#ibcon#enter sib2, iclass 7, count 2 2006.201.08:43:52.32#ibcon#flushed, iclass 7, count 2 2006.201.08:43:52.32#ibcon#about to write, iclass 7, count 2 2006.201.08:43:52.32#ibcon#wrote, iclass 7, count 2 2006.201.08:43:52.32#ibcon#about to read 3, iclass 7, count 2 2006.201.08:43:52.34#ibcon#read 3, iclass 7, count 2 2006.201.08:43:52.34#ibcon#about to read 4, iclass 7, count 2 2006.201.08:43:52.34#ibcon#read 4, iclass 7, count 2 2006.201.08:43:52.34#ibcon#about to read 5, iclass 7, count 2 2006.201.08:43:52.34#ibcon#read 5, iclass 7, count 2 2006.201.08:43:52.34#ibcon#about to read 6, iclass 7, count 2 2006.201.08:43:52.34#ibcon#read 6, iclass 7, count 2 2006.201.08:43:52.34#ibcon#end of sib2, iclass 7, count 2 2006.201.08:43:52.34#ibcon#*mode == 0, iclass 7, count 2 2006.201.08:43:52.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.08:43:52.34#ibcon#[25=AT02-07\r\n] 2006.201.08:43:52.34#ibcon#*before write, iclass 7, count 2 2006.201.08:43:52.34#ibcon#enter sib2, iclass 7, count 2 2006.201.08:43:52.34#ibcon#flushed, iclass 7, count 2 2006.201.08:43:52.34#ibcon#about to write, iclass 7, count 2 2006.201.08:43:52.34#ibcon#wrote, iclass 7, count 2 2006.201.08:43:52.34#ibcon#about to read 3, iclass 7, count 2 2006.201.08:43:52.37#ibcon#read 3, iclass 7, count 2 2006.201.08:43:52.37#ibcon#about to read 4, iclass 7, count 2 2006.201.08:43:52.37#ibcon#read 4, iclass 7, count 2 2006.201.08:43:52.37#ibcon#about to read 5, iclass 7, count 2 2006.201.08:43:52.37#ibcon#read 5, iclass 7, count 2 2006.201.08:43:52.37#ibcon#about to read 6, iclass 7, count 2 2006.201.08:43:52.37#ibcon#read 6, iclass 7, count 2 2006.201.08:43:52.37#ibcon#end of sib2, iclass 7, count 2 2006.201.08:43:52.37#ibcon#*after write, iclass 7, count 2 2006.201.08:43:52.37#ibcon#*before return 0, iclass 7, count 2 2006.201.08:43:52.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:52.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:52.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.08:43:52.37#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:52.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:52.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:52.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:52.49#ibcon#enter wrdev, iclass 7, count 0 2006.201.08:43:52.49#ibcon#first serial, iclass 7, count 0 2006.201.08:43:52.49#ibcon#enter sib2, iclass 7, count 0 2006.201.08:43:52.49#ibcon#flushed, iclass 7, count 0 2006.201.08:43:52.49#ibcon#about to write, iclass 7, count 0 2006.201.08:43:52.49#ibcon#wrote, iclass 7, count 0 2006.201.08:43:52.49#ibcon#about to read 3, iclass 7, count 0 2006.201.08:43:52.51#ibcon#read 3, iclass 7, count 0 2006.201.08:43:52.51#ibcon#about to read 4, iclass 7, count 0 2006.201.08:43:52.51#ibcon#read 4, iclass 7, count 0 2006.201.08:43:52.51#ibcon#about to read 5, iclass 7, count 0 2006.201.08:43:52.51#ibcon#read 5, iclass 7, count 0 2006.201.08:43:52.51#ibcon#about to read 6, iclass 7, count 0 2006.201.08:43:52.51#ibcon#read 6, iclass 7, count 0 2006.201.08:43:52.51#ibcon#end of sib2, iclass 7, count 0 2006.201.08:43:52.51#ibcon#*mode == 0, iclass 7, count 0 2006.201.08:43:52.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.08:43:52.51#ibcon#[25=USB\r\n] 2006.201.08:43:52.51#ibcon#*before write, iclass 7, count 0 2006.201.08:43:52.51#ibcon#enter sib2, iclass 7, count 0 2006.201.08:43:52.51#ibcon#flushed, iclass 7, count 0 2006.201.08:43:52.51#ibcon#about to write, iclass 7, count 0 2006.201.08:43:52.51#ibcon#wrote, iclass 7, count 0 2006.201.08:43:52.51#ibcon#about to read 3, iclass 7, count 0 2006.201.08:43:52.54#ibcon#read 3, iclass 7, count 0 2006.201.08:43:52.54#ibcon#about to read 4, iclass 7, count 0 2006.201.08:43:52.54#ibcon#read 4, iclass 7, count 0 2006.201.08:43:52.54#ibcon#about to read 5, iclass 7, count 0 2006.201.08:43:52.54#ibcon#read 5, iclass 7, count 0 2006.201.08:43:52.54#ibcon#about to read 6, iclass 7, count 0 2006.201.08:43:52.54#ibcon#read 6, iclass 7, count 0 2006.201.08:43:52.54#ibcon#end of sib2, iclass 7, count 0 2006.201.08:43:52.54#ibcon#*after write, iclass 7, count 0 2006.201.08:43:52.54#ibcon#*before return 0, iclass 7, count 0 2006.201.08:43:52.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:52.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:52.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.08:43:52.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.08:43:52.54$vck44/valo=3,564.99 2006.201.08:43:52.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.08:43:52.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.08:43:52.54#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:52.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:52.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:52.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:52.54#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:43:52.54#ibcon#first serial, iclass 11, count 0 2006.201.08:43:52.54#ibcon#enter sib2, iclass 11, count 0 2006.201.08:43:52.54#ibcon#flushed, iclass 11, count 0 2006.201.08:43:52.54#ibcon#about to write, iclass 11, count 0 2006.201.08:43:52.54#ibcon#wrote, iclass 11, count 0 2006.201.08:43:52.54#ibcon#about to read 3, iclass 11, count 0 2006.201.08:43:52.56#ibcon#read 3, iclass 11, count 0 2006.201.08:43:52.56#ibcon#about to read 4, iclass 11, count 0 2006.201.08:43:52.56#ibcon#read 4, iclass 11, count 0 2006.201.08:43:52.56#ibcon#about to read 5, iclass 11, count 0 2006.201.08:43:52.56#ibcon#read 5, iclass 11, count 0 2006.201.08:43:52.56#ibcon#about to read 6, iclass 11, count 0 2006.201.08:43:52.56#ibcon#read 6, iclass 11, count 0 2006.201.08:43:52.56#ibcon#end of sib2, iclass 11, count 0 2006.201.08:43:52.56#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:43:52.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:43:52.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:43:52.56#ibcon#*before write, iclass 11, count 0 2006.201.08:43:52.56#ibcon#enter sib2, iclass 11, count 0 2006.201.08:43:52.56#ibcon#flushed, iclass 11, count 0 2006.201.08:43:52.56#ibcon#about to write, iclass 11, count 0 2006.201.08:43:52.56#ibcon#wrote, iclass 11, count 0 2006.201.08:43:52.56#ibcon#about to read 3, iclass 11, count 0 2006.201.08:43:52.61#ibcon#read 3, iclass 11, count 0 2006.201.08:43:52.61#ibcon#about to read 4, iclass 11, count 0 2006.201.08:43:52.61#ibcon#read 4, iclass 11, count 0 2006.201.08:43:52.61#ibcon#about to read 5, iclass 11, count 0 2006.201.08:43:52.61#ibcon#read 5, iclass 11, count 0 2006.201.08:43:52.61#ibcon#about to read 6, iclass 11, count 0 2006.201.08:43:52.61#ibcon#read 6, iclass 11, count 0 2006.201.08:43:52.61#ibcon#end of sib2, iclass 11, count 0 2006.201.08:43:52.61#ibcon#*after write, iclass 11, count 0 2006.201.08:43:52.61#ibcon#*before return 0, iclass 11, count 0 2006.201.08:43:52.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:52.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:52.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:43:52.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:43:52.61$vck44/va=3,8 2006.201.08:43:52.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.08:43:52.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.08:43:52.61#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:52.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:52.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:52.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:52.66#ibcon#enter wrdev, iclass 13, count 2 2006.201.08:43:52.66#ibcon#first serial, iclass 13, count 2 2006.201.08:43:52.66#ibcon#enter sib2, iclass 13, count 2 2006.201.08:43:52.66#ibcon#flushed, iclass 13, count 2 2006.201.08:43:52.66#ibcon#about to write, iclass 13, count 2 2006.201.08:43:52.66#ibcon#wrote, iclass 13, count 2 2006.201.08:43:52.66#ibcon#about to read 3, iclass 13, count 2 2006.201.08:43:52.68#ibcon#read 3, iclass 13, count 2 2006.201.08:43:52.68#ibcon#about to read 4, iclass 13, count 2 2006.201.08:43:52.68#ibcon#read 4, iclass 13, count 2 2006.201.08:43:52.68#ibcon#about to read 5, iclass 13, count 2 2006.201.08:43:52.68#ibcon#read 5, iclass 13, count 2 2006.201.08:43:52.68#ibcon#about to read 6, iclass 13, count 2 2006.201.08:43:52.68#ibcon#read 6, iclass 13, count 2 2006.201.08:43:52.68#ibcon#end of sib2, iclass 13, count 2 2006.201.08:43:52.68#ibcon#*mode == 0, iclass 13, count 2 2006.201.08:43:52.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.08:43:52.68#ibcon#[25=AT03-08\r\n] 2006.201.08:43:52.68#ibcon#*before write, iclass 13, count 2 2006.201.08:43:52.68#ibcon#enter sib2, iclass 13, count 2 2006.201.08:43:52.68#ibcon#flushed, iclass 13, count 2 2006.201.08:43:52.68#ibcon#about to write, iclass 13, count 2 2006.201.08:43:52.68#ibcon#wrote, iclass 13, count 2 2006.201.08:43:52.68#ibcon#about to read 3, iclass 13, count 2 2006.201.08:43:52.71#ibcon#read 3, iclass 13, count 2 2006.201.08:43:52.71#ibcon#about to read 4, iclass 13, count 2 2006.201.08:43:52.71#ibcon#read 4, iclass 13, count 2 2006.201.08:43:52.71#ibcon#about to read 5, iclass 13, count 2 2006.201.08:43:52.71#ibcon#read 5, iclass 13, count 2 2006.201.08:43:52.71#ibcon#about to read 6, iclass 13, count 2 2006.201.08:43:52.71#ibcon#read 6, iclass 13, count 2 2006.201.08:43:52.71#ibcon#end of sib2, iclass 13, count 2 2006.201.08:43:52.71#ibcon#*after write, iclass 13, count 2 2006.201.08:43:52.71#ibcon#*before return 0, iclass 13, count 2 2006.201.08:43:52.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:52.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:52.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.08:43:52.71#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:52.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:52.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:52.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:52.83#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:43:52.83#ibcon#first serial, iclass 13, count 0 2006.201.08:43:52.83#ibcon#enter sib2, iclass 13, count 0 2006.201.08:43:52.83#ibcon#flushed, iclass 13, count 0 2006.201.08:43:52.83#ibcon#about to write, iclass 13, count 0 2006.201.08:43:52.83#ibcon#wrote, iclass 13, count 0 2006.201.08:43:52.83#ibcon#about to read 3, iclass 13, count 0 2006.201.08:43:52.85#ibcon#read 3, iclass 13, count 0 2006.201.08:43:52.85#ibcon#about to read 4, iclass 13, count 0 2006.201.08:43:52.85#ibcon#read 4, iclass 13, count 0 2006.201.08:43:52.85#ibcon#about to read 5, iclass 13, count 0 2006.201.08:43:52.85#ibcon#read 5, iclass 13, count 0 2006.201.08:43:52.85#ibcon#about to read 6, iclass 13, count 0 2006.201.08:43:52.85#ibcon#read 6, iclass 13, count 0 2006.201.08:43:52.85#ibcon#end of sib2, iclass 13, count 0 2006.201.08:43:52.85#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:43:52.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:43:52.85#ibcon#[25=USB\r\n] 2006.201.08:43:52.85#ibcon#*before write, iclass 13, count 0 2006.201.08:43:52.85#ibcon#enter sib2, iclass 13, count 0 2006.201.08:43:52.85#ibcon#flushed, iclass 13, count 0 2006.201.08:43:52.85#ibcon#about to write, iclass 13, count 0 2006.201.08:43:52.85#ibcon#wrote, iclass 13, count 0 2006.201.08:43:52.85#ibcon#about to read 3, iclass 13, count 0 2006.201.08:43:52.88#ibcon#read 3, iclass 13, count 0 2006.201.08:43:52.88#ibcon#about to read 4, iclass 13, count 0 2006.201.08:43:52.88#ibcon#read 4, iclass 13, count 0 2006.201.08:43:52.88#ibcon#about to read 5, iclass 13, count 0 2006.201.08:43:52.88#ibcon#read 5, iclass 13, count 0 2006.201.08:43:52.88#ibcon#about to read 6, iclass 13, count 0 2006.201.08:43:52.88#ibcon#read 6, iclass 13, count 0 2006.201.08:43:52.88#ibcon#end of sib2, iclass 13, count 0 2006.201.08:43:52.88#ibcon#*after write, iclass 13, count 0 2006.201.08:43:52.88#ibcon#*before return 0, iclass 13, count 0 2006.201.08:43:52.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:52.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:52.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:43:52.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:43:52.88$vck44/valo=4,624.99 2006.201.08:43:52.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.08:43:52.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.08:43:52.88#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:52.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:52.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:52.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:52.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:43:52.88#ibcon#first serial, iclass 15, count 0 2006.201.08:43:52.88#ibcon#enter sib2, iclass 15, count 0 2006.201.08:43:52.88#ibcon#flushed, iclass 15, count 0 2006.201.08:43:52.88#ibcon#about to write, iclass 15, count 0 2006.201.08:43:52.88#ibcon#wrote, iclass 15, count 0 2006.201.08:43:52.88#ibcon#about to read 3, iclass 15, count 0 2006.201.08:43:52.90#ibcon#read 3, iclass 15, count 0 2006.201.08:43:52.90#ibcon#about to read 4, iclass 15, count 0 2006.201.08:43:52.90#ibcon#read 4, iclass 15, count 0 2006.201.08:43:52.90#ibcon#about to read 5, iclass 15, count 0 2006.201.08:43:52.90#ibcon#read 5, iclass 15, count 0 2006.201.08:43:52.90#ibcon#about to read 6, iclass 15, count 0 2006.201.08:43:52.90#ibcon#read 6, iclass 15, count 0 2006.201.08:43:52.90#ibcon#end of sib2, iclass 15, count 0 2006.201.08:43:52.90#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:43:52.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:43:52.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:43:52.90#ibcon#*before write, iclass 15, count 0 2006.201.08:43:52.90#ibcon#enter sib2, iclass 15, count 0 2006.201.08:43:52.90#ibcon#flushed, iclass 15, count 0 2006.201.08:43:52.90#ibcon#about to write, iclass 15, count 0 2006.201.08:43:52.90#ibcon#wrote, iclass 15, count 0 2006.201.08:43:52.90#ibcon#about to read 3, iclass 15, count 0 2006.201.08:43:52.95#ibcon#read 3, iclass 15, count 0 2006.201.08:43:52.95#ibcon#about to read 4, iclass 15, count 0 2006.201.08:43:52.95#ibcon#read 4, iclass 15, count 0 2006.201.08:43:52.95#ibcon#about to read 5, iclass 15, count 0 2006.201.08:43:52.95#ibcon#read 5, iclass 15, count 0 2006.201.08:43:52.95#ibcon#about to read 6, iclass 15, count 0 2006.201.08:43:52.95#ibcon#read 6, iclass 15, count 0 2006.201.08:43:52.95#ibcon#end of sib2, iclass 15, count 0 2006.201.08:43:52.95#ibcon#*after write, iclass 15, count 0 2006.201.08:43:52.95#ibcon#*before return 0, iclass 15, count 0 2006.201.08:43:52.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:52.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:52.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:43:52.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:43:52.95$vck44/va=4,7 2006.201.08:43:52.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.08:43:52.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.08:43:52.95#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:52.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:53.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:53.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:53.00#ibcon#enter wrdev, iclass 17, count 2 2006.201.08:43:53.00#ibcon#first serial, iclass 17, count 2 2006.201.08:43:53.00#ibcon#enter sib2, iclass 17, count 2 2006.201.08:43:53.00#ibcon#flushed, iclass 17, count 2 2006.201.08:43:53.00#ibcon#about to write, iclass 17, count 2 2006.201.08:43:53.00#ibcon#wrote, iclass 17, count 2 2006.201.08:43:53.00#ibcon#about to read 3, iclass 17, count 2 2006.201.08:43:53.02#ibcon#read 3, iclass 17, count 2 2006.201.08:43:53.02#ibcon#about to read 4, iclass 17, count 2 2006.201.08:43:53.02#ibcon#read 4, iclass 17, count 2 2006.201.08:43:53.02#ibcon#about to read 5, iclass 17, count 2 2006.201.08:43:53.02#ibcon#read 5, iclass 17, count 2 2006.201.08:43:53.02#ibcon#about to read 6, iclass 17, count 2 2006.201.08:43:53.02#ibcon#read 6, iclass 17, count 2 2006.201.08:43:53.02#ibcon#end of sib2, iclass 17, count 2 2006.201.08:43:53.02#ibcon#*mode == 0, iclass 17, count 2 2006.201.08:43:53.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.08:43:53.02#ibcon#[25=AT04-07\r\n] 2006.201.08:43:53.02#ibcon#*before write, iclass 17, count 2 2006.201.08:43:53.02#ibcon#enter sib2, iclass 17, count 2 2006.201.08:43:53.02#ibcon#flushed, iclass 17, count 2 2006.201.08:43:53.02#ibcon#about to write, iclass 17, count 2 2006.201.08:43:53.02#ibcon#wrote, iclass 17, count 2 2006.201.08:43:53.02#ibcon#about to read 3, iclass 17, count 2 2006.201.08:43:53.05#ibcon#read 3, iclass 17, count 2 2006.201.08:43:53.05#ibcon#about to read 4, iclass 17, count 2 2006.201.08:43:53.05#ibcon#read 4, iclass 17, count 2 2006.201.08:43:53.05#ibcon#about to read 5, iclass 17, count 2 2006.201.08:43:53.05#ibcon#read 5, iclass 17, count 2 2006.201.08:43:53.05#ibcon#about to read 6, iclass 17, count 2 2006.201.08:43:53.05#ibcon#read 6, iclass 17, count 2 2006.201.08:43:53.05#ibcon#end of sib2, iclass 17, count 2 2006.201.08:43:53.05#ibcon#*after write, iclass 17, count 2 2006.201.08:43:53.05#ibcon#*before return 0, iclass 17, count 2 2006.201.08:43:53.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:53.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:53.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.08:43:53.05#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:53.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:53.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:53.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:53.17#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:43:53.17#ibcon#first serial, iclass 17, count 0 2006.201.08:43:53.17#ibcon#enter sib2, iclass 17, count 0 2006.201.08:43:53.17#ibcon#flushed, iclass 17, count 0 2006.201.08:43:53.17#ibcon#about to write, iclass 17, count 0 2006.201.08:43:53.17#ibcon#wrote, iclass 17, count 0 2006.201.08:43:53.17#ibcon#about to read 3, iclass 17, count 0 2006.201.08:43:53.19#ibcon#read 3, iclass 17, count 0 2006.201.08:43:53.19#ibcon#about to read 4, iclass 17, count 0 2006.201.08:43:53.19#ibcon#read 4, iclass 17, count 0 2006.201.08:43:53.19#ibcon#about to read 5, iclass 17, count 0 2006.201.08:43:53.19#ibcon#read 5, iclass 17, count 0 2006.201.08:43:53.19#ibcon#about to read 6, iclass 17, count 0 2006.201.08:43:53.19#ibcon#read 6, iclass 17, count 0 2006.201.08:43:53.19#ibcon#end of sib2, iclass 17, count 0 2006.201.08:43:53.19#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:43:53.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:43:53.19#ibcon#[25=USB\r\n] 2006.201.08:43:53.19#ibcon#*before write, iclass 17, count 0 2006.201.08:43:53.19#ibcon#enter sib2, iclass 17, count 0 2006.201.08:43:53.19#ibcon#flushed, iclass 17, count 0 2006.201.08:43:53.19#ibcon#about to write, iclass 17, count 0 2006.201.08:43:53.19#ibcon#wrote, iclass 17, count 0 2006.201.08:43:53.19#ibcon#about to read 3, iclass 17, count 0 2006.201.08:43:53.22#ibcon#read 3, iclass 17, count 0 2006.201.08:43:53.22#ibcon#about to read 4, iclass 17, count 0 2006.201.08:43:53.22#ibcon#read 4, iclass 17, count 0 2006.201.08:43:53.22#ibcon#about to read 5, iclass 17, count 0 2006.201.08:43:53.22#ibcon#read 5, iclass 17, count 0 2006.201.08:43:53.22#ibcon#about to read 6, iclass 17, count 0 2006.201.08:43:53.22#ibcon#read 6, iclass 17, count 0 2006.201.08:43:53.22#ibcon#end of sib2, iclass 17, count 0 2006.201.08:43:53.22#ibcon#*after write, iclass 17, count 0 2006.201.08:43:53.22#ibcon#*before return 0, iclass 17, count 0 2006.201.08:43:53.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:53.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:53.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:43:53.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:43:53.22$vck44/valo=5,734.99 2006.201.08:43:53.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.08:43:53.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.08:43:53.22#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:53.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:53.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:53.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:53.22#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:43:53.22#ibcon#first serial, iclass 19, count 0 2006.201.08:43:53.22#ibcon#enter sib2, iclass 19, count 0 2006.201.08:43:53.22#ibcon#flushed, iclass 19, count 0 2006.201.08:43:53.22#ibcon#about to write, iclass 19, count 0 2006.201.08:43:53.22#ibcon#wrote, iclass 19, count 0 2006.201.08:43:53.22#ibcon#about to read 3, iclass 19, count 0 2006.201.08:43:53.24#ibcon#read 3, iclass 19, count 0 2006.201.08:43:53.24#ibcon#about to read 4, iclass 19, count 0 2006.201.08:43:53.24#ibcon#read 4, iclass 19, count 0 2006.201.08:43:53.24#ibcon#about to read 5, iclass 19, count 0 2006.201.08:43:53.24#ibcon#read 5, iclass 19, count 0 2006.201.08:43:53.24#ibcon#about to read 6, iclass 19, count 0 2006.201.08:43:53.24#ibcon#read 6, iclass 19, count 0 2006.201.08:43:53.24#ibcon#end of sib2, iclass 19, count 0 2006.201.08:43:53.24#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:43:53.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:43:53.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:43:53.24#ibcon#*before write, iclass 19, count 0 2006.201.08:43:53.24#ibcon#enter sib2, iclass 19, count 0 2006.201.08:43:53.24#ibcon#flushed, iclass 19, count 0 2006.201.08:43:53.24#ibcon#about to write, iclass 19, count 0 2006.201.08:43:53.24#ibcon#wrote, iclass 19, count 0 2006.201.08:43:53.24#ibcon#about to read 3, iclass 19, count 0 2006.201.08:43:53.28#ibcon#read 3, iclass 19, count 0 2006.201.08:43:53.28#ibcon#about to read 4, iclass 19, count 0 2006.201.08:43:53.28#ibcon#read 4, iclass 19, count 0 2006.201.08:43:53.28#ibcon#about to read 5, iclass 19, count 0 2006.201.08:43:53.28#ibcon#read 5, iclass 19, count 0 2006.201.08:43:53.28#ibcon#about to read 6, iclass 19, count 0 2006.201.08:43:53.28#ibcon#read 6, iclass 19, count 0 2006.201.08:43:53.28#ibcon#end of sib2, iclass 19, count 0 2006.201.08:43:53.28#ibcon#*after write, iclass 19, count 0 2006.201.08:43:53.28#ibcon#*before return 0, iclass 19, count 0 2006.201.08:43:53.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:53.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:53.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:43:53.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:43:53.28$vck44/va=5,4 2006.201.08:43:53.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.08:43:53.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.08:43:53.28#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:53.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:53.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:53.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:53.34#ibcon#enter wrdev, iclass 21, count 2 2006.201.08:43:53.34#ibcon#first serial, iclass 21, count 2 2006.201.08:43:53.34#ibcon#enter sib2, iclass 21, count 2 2006.201.08:43:53.34#ibcon#flushed, iclass 21, count 2 2006.201.08:43:53.34#ibcon#about to write, iclass 21, count 2 2006.201.08:43:53.34#ibcon#wrote, iclass 21, count 2 2006.201.08:43:53.34#ibcon#about to read 3, iclass 21, count 2 2006.201.08:43:53.36#ibcon#read 3, iclass 21, count 2 2006.201.08:43:53.36#ibcon#about to read 4, iclass 21, count 2 2006.201.08:43:53.36#ibcon#read 4, iclass 21, count 2 2006.201.08:43:53.36#ibcon#about to read 5, iclass 21, count 2 2006.201.08:43:53.36#ibcon#read 5, iclass 21, count 2 2006.201.08:43:53.36#ibcon#about to read 6, iclass 21, count 2 2006.201.08:43:53.36#ibcon#read 6, iclass 21, count 2 2006.201.08:43:53.36#ibcon#end of sib2, iclass 21, count 2 2006.201.08:43:53.36#ibcon#*mode == 0, iclass 21, count 2 2006.201.08:43:53.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.08:43:53.36#ibcon#[25=AT05-04\r\n] 2006.201.08:43:53.36#ibcon#*before write, iclass 21, count 2 2006.201.08:43:53.36#ibcon#enter sib2, iclass 21, count 2 2006.201.08:43:53.36#ibcon#flushed, iclass 21, count 2 2006.201.08:43:53.36#ibcon#about to write, iclass 21, count 2 2006.201.08:43:53.36#ibcon#wrote, iclass 21, count 2 2006.201.08:43:53.36#ibcon#about to read 3, iclass 21, count 2 2006.201.08:43:53.39#ibcon#read 3, iclass 21, count 2 2006.201.08:43:53.39#ibcon#about to read 4, iclass 21, count 2 2006.201.08:43:53.39#ibcon#read 4, iclass 21, count 2 2006.201.08:43:53.39#ibcon#about to read 5, iclass 21, count 2 2006.201.08:43:53.39#ibcon#read 5, iclass 21, count 2 2006.201.08:43:53.39#ibcon#about to read 6, iclass 21, count 2 2006.201.08:43:53.39#ibcon#read 6, iclass 21, count 2 2006.201.08:43:53.39#ibcon#end of sib2, iclass 21, count 2 2006.201.08:43:53.39#ibcon#*after write, iclass 21, count 2 2006.201.08:43:53.39#ibcon#*before return 0, iclass 21, count 2 2006.201.08:43:53.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:53.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:53.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.08:43:53.39#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:53.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:53.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:53.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:53.51#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:43:53.51#ibcon#first serial, iclass 21, count 0 2006.201.08:43:53.51#ibcon#enter sib2, iclass 21, count 0 2006.201.08:43:53.51#ibcon#flushed, iclass 21, count 0 2006.201.08:43:53.51#ibcon#about to write, iclass 21, count 0 2006.201.08:43:53.51#ibcon#wrote, iclass 21, count 0 2006.201.08:43:53.51#ibcon#about to read 3, iclass 21, count 0 2006.201.08:43:53.53#ibcon#read 3, iclass 21, count 0 2006.201.08:43:53.53#ibcon#about to read 4, iclass 21, count 0 2006.201.08:43:53.53#ibcon#read 4, iclass 21, count 0 2006.201.08:43:53.53#ibcon#about to read 5, iclass 21, count 0 2006.201.08:43:53.53#ibcon#read 5, iclass 21, count 0 2006.201.08:43:53.53#ibcon#about to read 6, iclass 21, count 0 2006.201.08:43:53.53#ibcon#read 6, iclass 21, count 0 2006.201.08:43:53.53#ibcon#end of sib2, iclass 21, count 0 2006.201.08:43:53.53#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:43:53.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:43:53.53#ibcon#[25=USB\r\n] 2006.201.08:43:53.53#ibcon#*before write, iclass 21, count 0 2006.201.08:43:53.53#ibcon#enter sib2, iclass 21, count 0 2006.201.08:43:53.53#ibcon#flushed, iclass 21, count 0 2006.201.08:43:53.53#ibcon#about to write, iclass 21, count 0 2006.201.08:43:53.53#ibcon#wrote, iclass 21, count 0 2006.201.08:43:53.53#ibcon#about to read 3, iclass 21, count 0 2006.201.08:43:53.56#ibcon#read 3, iclass 21, count 0 2006.201.08:43:53.56#ibcon#about to read 4, iclass 21, count 0 2006.201.08:43:53.56#ibcon#read 4, iclass 21, count 0 2006.201.08:43:53.56#ibcon#about to read 5, iclass 21, count 0 2006.201.08:43:53.56#ibcon#read 5, iclass 21, count 0 2006.201.08:43:53.56#ibcon#about to read 6, iclass 21, count 0 2006.201.08:43:53.56#ibcon#read 6, iclass 21, count 0 2006.201.08:43:53.56#ibcon#end of sib2, iclass 21, count 0 2006.201.08:43:53.56#ibcon#*after write, iclass 21, count 0 2006.201.08:43:53.56#ibcon#*before return 0, iclass 21, count 0 2006.201.08:43:53.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:53.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:53.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:43:53.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:43:53.56$vck44/valo=6,814.99 2006.201.08:43:53.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.08:43:53.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.08:43:53.56#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:53.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:53.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:53.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:53.56#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:43:53.56#ibcon#first serial, iclass 23, count 0 2006.201.08:43:53.56#ibcon#enter sib2, iclass 23, count 0 2006.201.08:43:53.56#ibcon#flushed, iclass 23, count 0 2006.201.08:43:53.56#ibcon#about to write, iclass 23, count 0 2006.201.08:43:53.56#ibcon#wrote, iclass 23, count 0 2006.201.08:43:53.56#ibcon#about to read 3, iclass 23, count 0 2006.201.08:43:53.58#ibcon#read 3, iclass 23, count 0 2006.201.08:43:53.58#ibcon#about to read 4, iclass 23, count 0 2006.201.08:43:53.58#ibcon#read 4, iclass 23, count 0 2006.201.08:43:53.58#ibcon#about to read 5, iclass 23, count 0 2006.201.08:43:53.58#ibcon#read 5, iclass 23, count 0 2006.201.08:43:53.58#ibcon#about to read 6, iclass 23, count 0 2006.201.08:43:53.58#ibcon#read 6, iclass 23, count 0 2006.201.08:43:53.58#ibcon#end of sib2, iclass 23, count 0 2006.201.08:43:53.58#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:43:53.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:43:53.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:43:53.58#ibcon#*before write, iclass 23, count 0 2006.201.08:43:53.58#ibcon#enter sib2, iclass 23, count 0 2006.201.08:43:53.58#ibcon#flushed, iclass 23, count 0 2006.201.08:43:53.58#ibcon#about to write, iclass 23, count 0 2006.201.08:43:53.58#ibcon#wrote, iclass 23, count 0 2006.201.08:43:53.58#ibcon#about to read 3, iclass 23, count 0 2006.201.08:43:53.63#ibcon#read 3, iclass 23, count 0 2006.201.08:43:53.63#ibcon#about to read 4, iclass 23, count 0 2006.201.08:43:53.63#ibcon#read 4, iclass 23, count 0 2006.201.08:43:53.63#ibcon#about to read 5, iclass 23, count 0 2006.201.08:43:53.63#ibcon#read 5, iclass 23, count 0 2006.201.08:43:53.63#ibcon#about to read 6, iclass 23, count 0 2006.201.08:43:53.63#ibcon#read 6, iclass 23, count 0 2006.201.08:43:53.63#ibcon#end of sib2, iclass 23, count 0 2006.201.08:43:53.63#ibcon#*after write, iclass 23, count 0 2006.201.08:43:53.63#ibcon#*before return 0, iclass 23, count 0 2006.201.08:43:53.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:53.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:53.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:43:53.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:43:53.63$vck44/va=6,5 2006.201.08:43:53.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.08:43:53.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.08:43:53.63#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:53.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:53.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:53.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:53.68#ibcon#enter wrdev, iclass 25, count 2 2006.201.08:43:53.68#ibcon#first serial, iclass 25, count 2 2006.201.08:43:53.68#ibcon#enter sib2, iclass 25, count 2 2006.201.08:43:53.68#ibcon#flushed, iclass 25, count 2 2006.201.08:43:53.68#ibcon#about to write, iclass 25, count 2 2006.201.08:43:53.68#ibcon#wrote, iclass 25, count 2 2006.201.08:43:53.68#ibcon#about to read 3, iclass 25, count 2 2006.201.08:43:53.70#ibcon#read 3, iclass 25, count 2 2006.201.08:43:53.70#ibcon#about to read 4, iclass 25, count 2 2006.201.08:43:53.70#ibcon#read 4, iclass 25, count 2 2006.201.08:43:53.70#ibcon#about to read 5, iclass 25, count 2 2006.201.08:43:53.70#ibcon#read 5, iclass 25, count 2 2006.201.08:43:53.70#ibcon#about to read 6, iclass 25, count 2 2006.201.08:43:53.70#ibcon#read 6, iclass 25, count 2 2006.201.08:43:53.70#ibcon#end of sib2, iclass 25, count 2 2006.201.08:43:53.70#ibcon#*mode == 0, iclass 25, count 2 2006.201.08:43:53.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.08:43:53.70#ibcon#[25=AT06-05\r\n] 2006.201.08:43:53.70#ibcon#*before write, iclass 25, count 2 2006.201.08:43:53.70#ibcon#enter sib2, iclass 25, count 2 2006.201.08:43:53.70#ibcon#flushed, iclass 25, count 2 2006.201.08:43:53.70#ibcon#about to write, iclass 25, count 2 2006.201.08:43:53.70#ibcon#wrote, iclass 25, count 2 2006.201.08:43:53.70#ibcon#about to read 3, iclass 25, count 2 2006.201.08:43:53.73#ibcon#read 3, iclass 25, count 2 2006.201.08:43:53.73#ibcon#about to read 4, iclass 25, count 2 2006.201.08:43:53.73#ibcon#read 4, iclass 25, count 2 2006.201.08:43:53.73#ibcon#about to read 5, iclass 25, count 2 2006.201.08:43:53.73#ibcon#read 5, iclass 25, count 2 2006.201.08:43:53.73#ibcon#about to read 6, iclass 25, count 2 2006.201.08:43:53.73#ibcon#read 6, iclass 25, count 2 2006.201.08:43:53.73#ibcon#end of sib2, iclass 25, count 2 2006.201.08:43:53.73#ibcon#*after write, iclass 25, count 2 2006.201.08:43:53.73#ibcon#*before return 0, iclass 25, count 2 2006.201.08:43:53.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:53.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:53.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.08:43:53.73#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:53.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:53.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:53.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:53.85#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:43:53.85#ibcon#first serial, iclass 25, count 0 2006.201.08:43:53.85#ibcon#enter sib2, iclass 25, count 0 2006.201.08:43:53.85#ibcon#flushed, iclass 25, count 0 2006.201.08:43:53.85#ibcon#about to write, iclass 25, count 0 2006.201.08:43:53.85#ibcon#wrote, iclass 25, count 0 2006.201.08:43:53.85#ibcon#about to read 3, iclass 25, count 0 2006.201.08:43:53.87#ibcon#read 3, iclass 25, count 0 2006.201.08:43:53.87#ibcon#about to read 4, iclass 25, count 0 2006.201.08:43:53.87#ibcon#read 4, iclass 25, count 0 2006.201.08:43:53.87#ibcon#about to read 5, iclass 25, count 0 2006.201.08:43:53.87#ibcon#read 5, iclass 25, count 0 2006.201.08:43:53.87#ibcon#about to read 6, iclass 25, count 0 2006.201.08:43:53.87#ibcon#read 6, iclass 25, count 0 2006.201.08:43:53.87#ibcon#end of sib2, iclass 25, count 0 2006.201.08:43:53.87#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:43:53.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:43:53.87#ibcon#[25=USB\r\n] 2006.201.08:43:53.87#ibcon#*before write, iclass 25, count 0 2006.201.08:43:53.87#ibcon#enter sib2, iclass 25, count 0 2006.201.08:43:53.87#ibcon#flushed, iclass 25, count 0 2006.201.08:43:53.87#ibcon#about to write, iclass 25, count 0 2006.201.08:43:53.87#ibcon#wrote, iclass 25, count 0 2006.201.08:43:53.87#ibcon#about to read 3, iclass 25, count 0 2006.201.08:43:53.90#ibcon#read 3, iclass 25, count 0 2006.201.08:43:53.90#ibcon#about to read 4, iclass 25, count 0 2006.201.08:43:53.90#ibcon#read 4, iclass 25, count 0 2006.201.08:43:53.90#ibcon#about to read 5, iclass 25, count 0 2006.201.08:43:53.90#ibcon#read 5, iclass 25, count 0 2006.201.08:43:53.90#ibcon#about to read 6, iclass 25, count 0 2006.201.08:43:53.90#ibcon#read 6, iclass 25, count 0 2006.201.08:43:53.90#ibcon#end of sib2, iclass 25, count 0 2006.201.08:43:53.90#ibcon#*after write, iclass 25, count 0 2006.201.08:43:53.90#ibcon#*before return 0, iclass 25, count 0 2006.201.08:43:53.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:53.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:53.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:43:53.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:43:53.90$vck44/valo=7,864.99 2006.201.08:43:53.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.08:43:53.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.08:43:53.90#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:53.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:53.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:53.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:53.90#ibcon#enter wrdev, iclass 27, count 0 2006.201.08:43:53.90#ibcon#first serial, iclass 27, count 0 2006.201.08:43:53.90#ibcon#enter sib2, iclass 27, count 0 2006.201.08:43:53.90#ibcon#flushed, iclass 27, count 0 2006.201.08:43:53.90#ibcon#about to write, iclass 27, count 0 2006.201.08:43:53.90#ibcon#wrote, iclass 27, count 0 2006.201.08:43:53.90#ibcon#about to read 3, iclass 27, count 0 2006.201.08:43:53.92#ibcon#read 3, iclass 27, count 0 2006.201.08:43:53.92#ibcon#about to read 4, iclass 27, count 0 2006.201.08:43:53.92#ibcon#read 4, iclass 27, count 0 2006.201.08:43:53.92#ibcon#about to read 5, iclass 27, count 0 2006.201.08:43:53.92#ibcon#read 5, iclass 27, count 0 2006.201.08:43:53.92#ibcon#about to read 6, iclass 27, count 0 2006.201.08:43:53.92#ibcon#read 6, iclass 27, count 0 2006.201.08:43:53.92#ibcon#end of sib2, iclass 27, count 0 2006.201.08:43:53.92#ibcon#*mode == 0, iclass 27, count 0 2006.201.08:43:53.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.08:43:53.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:43:53.92#ibcon#*before write, iclass 27, count 0 2006.201.08:43:53.92#ibcon#enter sib2, iclass 27, count 0 2006.201.08:43:53.92#ibcon#flushed, iclass 27, count 0 2006.201.08:43:53.92#ibcon#about to write, iclass 27, count 0 2006.201.08:43:53.92#ibcon#wrote, iclass 27, count 0 2006.201.08:43:53.92#ibcon#about to read 3, iclass 27, count 0 2006.201.08:43:53.97#ibcon#read 3, iclass 27, count 0 2006.201.08:43:53.97#ibcon#about to read 4, iclass 27, count 0 2006.201.08:43:53.97#ibcon#read 4, iclass 27, count 0 2006.201.08:43:53.97#ibcon#about to read 5, iclass 27, count 0 2006.201.08:43:53.97#ibcon#read 5, iclass 27, count 0 2006.201.08:43:53.97#ibcon#about to read 6, iclass 27, count 0 2006.201.08:43:53.97#ibcon#read 6, iclass 27, count 0 2006.201.08:43:53.97#ibcon#end of sib2, iclass 27, count 0 2006.201.08:43:53.97#ibcon#*after write, iclass 27, count 0 2006.201.08:43:53.97#ibcon#*before return 0, iclass 27, count 0 2006.201.08:43:53.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:53.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:53.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.08:43:53.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.08:43:53.97$vck44/va=7,5 2006.201.08:43:53.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.08:43:53.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.08:43:53.97#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:53.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:54.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:54.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:54.02#ibcon#enter wrdev, iclass 29, count 2 2006.201.08:43:54.02#ibcon#first serial, iclass 29, count 2 2006.201.08:43:54.02#ibcon#enter sib2, iclass 29, count 2 2006.201.08:43:54.02#ibcon#flushed, iclass 29, count 2 2006.201.08:43:54.02#ibcon#about to write, iclass 29, count 2 2006.201.08:43:54.02#ibcon#wrote, iclass 29, count 2 2006.201.08:43:54.02#ibcon#about to read 3, iclass 29, count 2 2006.201.08:43:54.04#ibcon#read 3, iclass 29, count 2 2006.201.08:43:54.04#ibcon#about to read 4, iclass 29, count 2 2006.201.08:43:54.04#ibcon#read 4, iclass 29, count 2 2006.201.08:43:54.04#ibcon#about to read 5, iclass 29, count 2 2006.201.08:43:54.04#ibcon#read 5, iclass 29, count 2 2006.201.08:43:54.04#ibcon#about to read 6, iclass 29, count 2 2006.201.08:43:54.04#ibcon#read 6, iclass 29, count 2 2006.201.08:43:54.04#ibcon#end of sib2, iclass 29, count 2 2006.201.08:43:54.04#ibcon#*mode == 0, iclass 29, count 2 2006.201.08:43:54.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.08:43:54.04#ibcon#[25=AT07-05\r\n] 2006.201.08:43:54.04#ibcon#*before write, iclass 29, count 2 2006.201.08:43:54.04#ibcon#enter sib2, iclass 29, count 2 2006.201.08:43:54.04#ibcon#flushed, iclass 29, count 2 2006.201.08:43:54.04#ibcon#about to write, iclass 29, count 2 2006.201.08:43:54.04#ibcon#wrote, iclass 29, count 2 2006.201.08:43:54.04#ibcon#about to read 3, iclass 29, count 2 2006.201.08:43:54.07#ibcon#read 3, iclass 29, count 2 2006.201.08:43:54.07#ibcon#about to read 4, iclass 29, count 2 2006.201.08:43:54.07#ibcon#read 4, iclass 29, count 2 2006.201.08:43:54.07#ibcon#about to read 5, iclass 29, count 2 2006.201.08:43:54.07#ibcon#read 5, iclass 29, count 2 2006.201.08:43:54.07#ibcon#about to read 6, iclass 29, count 2 2006.201.08:43:54.07#ibcon#read 6, iclass 29, count 2 2006.201.08:43:54.07#ibcon#end of sib2, iclass 29, count 2 2006.201.08:43:54.07#ibcon#*after write, iclass 29, count 2 2006.201.08:43:54.07#ibcon#*before return 0, iclass 29, count 2 2006.201.08:43:54.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:54.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:54.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.08:43:54.07#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:54.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:54.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:54.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:54.19#ibcon#enter wrdev, iclass 29, count 0 2006.201.08:43:54.19#ibcon#first serial, iclass 29, count 0 2006.201.08:43:54.19#ibcon#enter sib2, iclass 29, count 0 2006.201.08:43:54.19#ibcon#flushed, iclass 29, count 0 2006.201.08:43:54.19#ibcon#about to write, iclass 29, count 0 2006.201.08:43:54.19#ibcon#wrote, iclass 29, count 0 2006.201.08:43:54.19#ibcon#about to read 3, iclass 29, count 0 2006.201.08:43:54.21#ibcon#read 3, iclass 29, count 0 2006.201.08:43:54.21#ibcon#about to read 4, iclass 29, count 0 2006.201.08:43:54.21#ibcon#read 4, iclass 29, count 0 2006.201.08:43:54.21#ibcon#about to read 5, iclass 29, count 0 2006.201.08:43:54.21#ibcon#read 5, iclass 29, count 0 2006.201.08:43:54.21#ibcon#about to read 6, iclass 29, count 0 2006.201.08:43:54.21#ibcon#read 6, iclass 29, count 0 2006.201.08:43:54.21#ibcon#end of sib2, iclass 29, count 0 2006.201.08:43:54.21#ibcon#*mode == 0, iclass 29, count 0 2006.201.08:43:54.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.08:43:54.21#ibcon#[25=USB\r\n] 2006.201.08:43:54.21#ibcon#*before write, iclass 29, count 0 2006.201.08:43:54.21#ibcon#enter sib2, iclass 29, count 0 2006.201.08:43:54.21#ibcon#flushed, iclass 29, count 0 2006.201.08:43:54.21#ibcon#about to write, iclass 29, count 0 2006.201.08:43:54.21#ibcon#wrote, iclass 29, count 0 2006.201.08:43:54.21#ibcon#about to read 3, iclass 29, count 0 2006.201.08:43:54.24#ibcon#read 3, iclass 29, count 0 2006.201.08:43:54.24#ibcon#about to read 4, iclass 29, count 0 2006.201.08:43:54.24#ibcon#read 4, iclass 29, count 0 2006.201.08:43:54.24#ibcon#about to read 5, iclass 29, count 0 2006.201.08:43:54.24#ibcon#read 5, iclass 29, count 0 2006.201.08:43:54.24#ibcon#about to read 6, iclass 29, count 0 2006.201.08:43:54.24#ibcon#read 6, iclass 29, count 0 2006.201.08:43:54.24#ibcon#end of sib2, iclass 29, count 0 2006.201.08:43:54.24#ibcon#*after write, iclass 29, count 0 2006.201.08:43:54.24#ibcon#*before return 0, iclass 29, count 0 2006.201.08:43:54.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:54.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:54.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.08:43:54.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.08:43:54.24$vck44/valo=8,884.99 2006.201.08:43:54.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.08:43:54.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.08:43:54.24#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:54.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:54.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:54.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:54.24#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:43:54.24#ibcon#first serial, iclass 31, count 0 2006.201.08:43:54.24#ibcon#enter sib2, iclass 31, count 0 2006.201.08:43:54.24#ibcon#flushed, iclass 31, count 0 2006.201.08:43:54.24#ibcon#about to write, iclass 31, count 0 2006.201.08:43:54.24#ibcon#wrote, iclass 31, count 0 2006.201.08:43:54.24#ibcon#about to read 3, iclass 31, count 0 2006.201.08:43:54.26#ibcon#read 3, iclass 31, count 0 2006.201.08:43:54.26#ibcon#about to read 4, iclass 31, count 0 2006.201.08:43:54.26#ibcon#read 4, iclass 31, count 0 2006.201.08:43:54.26#ibcon#about to read 5, iclass 31, count 0 2006.201.08:43:54.26#ibcon#read 5, iclass 31, count 0 2006.201.08:43:54.26#ibcon#about to read 6, iclass 31, count 0 2006.201.08:43:54.26#ibcon#read 6, iclass 31, count 0 2006.201.08:43:54.26#ibcon#end of sib2, iclass 31, count 0 2006.201.08:43:54.26#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:43:54.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:43:54.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:43:54.26#ibcon#*before write, iclass 31, count 0 2006.201.08:43:54.26#ibcon#enter sib2, iclass 31, count 0 2006.201.08:43:54.26#ibcon#flushed, iclass 31, count 0 2006.201.08:43:54.26#ibcon#about to write, iclass 31, count 0 2006.201.08:43:54.26#ibcon#wrote, iclass 31, count 0 2006.201.08:43:54.26#ibcon#about to read 3, iclass 31, count 0 2006.201.08:43:54.30#ibcon#read 3, iclass 31, count 0 2006.201.08:43:54.30#ibcon#about to read 4, iclass 31, count 0 2006.201.08:43:54.30#ibcon#read 4, iclass 31, count 0 2006.201.08:43:54.30#ibcon#about to read 5, iclass 31, count 0 2006.201.08:43:54.30#ibcon#read 5, iclass 31, count 0 2006.201.08:43:54.30#ibcon#about to read 6, iclass 31, count 0 2006.201.08:43:54.30#ibcon#read 6, iclass 31, count 0 2006.201.08:43:54.30#ibcon#end of sib2, iclass 31, count 0 2006.201.08:43:54.30#ibcon#*after write, iclass 31, count 0 2006.201.08:43:54.30#ibcon#*before return 0, iclass 31, count 0 2006.201.08:43:54.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:54.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:54.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:43:54.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:43:54.30$vck44/va=8,4 2006.201.08:43:54.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.08:43:54.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.08:43:54.30#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:54.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:54.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:54.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:54.36#ibcon#enter wrdev, iclass 33, count 2 2006.201.08:43:54.36#ibcon#first serial, iclass 33, count 2 2006.201.08:43:54.36#ibcon#enter sib2, iclass 33, count 2 2006.201.08:43:54.36#ibcon#flushed, iclass 33, count 2 2006.201.08:43:54.36#ibcon#about to write, iclass 33, count 2 2006.201.08:43:54.36#ibcon#wrote, iclass 33, count 2 2006.201.08:43:54.36#ibcon#about to read 3, iclass 33, count 2 2006.201.08:43:54.38#ibcon#read 3, iclass 33, count 2 2006.201.08:43:54.38#ibcon#about to read 4, iclass 33, count 2 2006.201.08:43:54.38#ibcon#read 4, iclass 33, count 2 2006.201.08:43:54.38#ibcon#about to read 5, iclass 33, count 2 2006.201.08:43:54.38#ibcon#read 5, iclass 33, count 2 2006.201.08:43:54.38#ibcon#about to read 6, iclass 33, count 2 2006.201.08:43:54.38#ibcon#read 6, iclass 33, count 2 2006.201.08:43:54.38#ibcon#end of sib2, iclass 33, count 2 2006.201.08:43:54.38#ibcon#*mode == 0, iclass 33, count 2 2006.201.08:43:54.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.08:43:54.38#ibcon#[25=AT08-04\r\n] 2006.201.08:43:54.38#ibcon#*before write, iclass 33, count 2 2006.201.08:43:54.38#ibcon#enter sib2, iclass 33, count 2 2006.201.08:43:54.38#ibcon#flushed, iclass 33, count 2 2006.201.08:43:54.38#ibcon#about to write, iclass 33, count 2 2006.201.08:43:54.38#ibcon#wrote, iclass 33, count 2 2006.201.08:43:54.38#ibcon#about to read 3, iclass 33, count 2 2006.201.08:43:54.41#ibcon#read 3, iclass 33, count 2 2006.201.08:43:54.41#ibcon#about to read 4, iclass 33, count 2 2006.201.08:43:54.41#ibcon#read 4, iclass 33, count 2 2006.201.08:43:54.41#ibcon#about to read 5, iclass 33, count 2 2006.201.08:43:54.41#ibcon#read 5, iclass 33, count 2 2006.201.08:43:54.41#ibcon#about to read 6, iclass 33, count 2 2006.201.08:43:54.41#ibcon#read 6, iclass 33, count 2 2006.201.08:43:54.41#ibcon#end of sib2, iclass 33, count 2 2006.201.08:43:54.41#ibcon#*after write, iclass 33, count 2 2006.201.08:43:54.41#ibcon#*before return 0, iclass 33, count 2 2006.201.08:43:54.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:54.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:54.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.08:43:54.41#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:54.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:54.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:54.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:54.53#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:43:54.53#ibcon#first serial, iclass 33, count 0 2006.201.08:43:54.53#ibcon#enter sib2, iclass 33, count 0 2006.201.08:43:54.53#ibcon#flushed, iclass 33, count 0 2006.201.08:43:54.53#ibcon#about to write, iclass 33, count 0 2006.201.08:43:54.53#ibcon#wrote, iclass 33, count 0 2006.201.08:43:54.53#ibcon#about to read 3, iclass 33, count 0 2006.201.08:43:54.55#ibcon#read 3, iclass 33, count 0 2006.201.08:43:54.55#ibcon#about to read 4, iclass 33, count 0 2006.201.08:43:54.55#ibcon#read 4, iclass 33, count 0 2006.201.08:43:54.55#ibcon#about to read 5, iclass 33, count 0 2006.201.08:43:54.55#ibcon#read 5, iclass 33, count 0 2006.201.08:43:54.55#ibcon#about to read 6, iclass 33, count 0 2006.201.08:43:54.55#ibcon#read 6, iclass 33, count 0 2006.201.08:43:54.55#ibcon#end of sib2, iclass 33, count 0 2006.201.08:43:54.55#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:43:54.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:43:54.55#ibcon#[25=USB\r\n] 2006.201.08:43:54.55#ibcon#*before write, iclass 33, count 0 2006.201.08:43:54.55#ibcon#enter sib2, iclass 33, count 0 2006.201.08:43:54.55#ibcon#flushed, iclass 33, count 0 2006.201.08:43:54.55#ibcon#about to write, iclass 33, count 0 2006.201.08:43:54.55#ibcon#wrote, iclass 33, count 0 2006.201.08:43:54.55#ibcon#about to read 3, iclass 33, count 0 2006.201.08:43:54.58#ibcon#read 3, iclass 33, count 0 2006.201.08:43:54.58#ibcon#about to read 4, iclass 33, count 0 2006.201.08:43:54.58#ibcon#read 4, iclass 33, count 0 2006.201.08:43:54.58#ibcon#about to read 5, iclass 33, count 0 2006.201.08:43:54.58#ibcon#read 5, iclass 33, count 0 2006.201.08:43:54.58#ibcon#about to read 6, iclass 33, count 0 2006.201.08:43:54.58#ibcon#read 6, iclass 33, count 0 2006.201.08:43:54.58#ibcon#end of sib2, iclass 33, count 0 2006.201.08:43:54.58#ibcon#*after write, iclass 33, count 0 2006.201.08:43:54.58#ibcon#*before return 0, iclass 33, count 0 2006.201.08:43:54.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:54.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:54.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:43:54.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:43:54.58$vck44/vblo=1,629.99 2006.201.08:43:54.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.08:43:54.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.08:43:54.58#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:54.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:54.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:54.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:54.58#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:43:54.58#ibcon#first serial, iclass 35, count 0 2006.201.08:43:54.58#ibcon#enter sib2, iclass 35, count 0 2006.201.08:43:54.58#ibcon#flushed, iclass 35, count 0 2006.201.08:43:54.58#ibcon#about to write, iclass 35, count 0 2006.201.08:43:54.58#ibcon#wrote, iclass 35, count 0 2006.201.08:43:54.58#ibcon#about to read 3, iclass 35, count 0 2006.201.08:43:54.60#ibcon#read 3, iclass 35, count 0 2006.201.08:43:54.60#ibcon#about to read 4, iclass 35, count 0 2006.201.08:43:54.60#ibcon#read 4, iclass 35, count 0 2006.201.08:43:54.60#ibcon#about to read 5, iclass 35, count 0 2006.201.08:43:54.60#ibcon#read 5, iclass 35, count 0 2006.201.08:43:54.60#ibcon#about to read 6, iclass 35, count 0 2006.201.08:43:54.60#ibcon#read 6, iclass 35, count 0 2006.201.08:43:54.60#ibcon#end of sib2, iclass 35, count 0 2006.201.08:43:54.60#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:43:54.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:43:54.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:43:54.60#ibcon#*before write, iclass 35, count 0 2006.201.08:43:54.60#ibcon#enter sib2, iclass 35, count 0 2006.201.08:43:54.60#ibcon#flushed, iclass 35, count 0 2006.201.08:43:54.60#ibcon#about to write, iclass 35, count 0 2006.201.08:43:54.60#ibcon#wrote, iclass 35, count 0 2006.201.08:43:54.60#ibcon#about to read 3, iclass 35, count 0 2006.201.08:43:54.65#ibcon#read 3, iclass 35, count 0 2006.201.08:43:54.65#ibcon#about to read 4, iclass 35, count 0 2006.201.08:43:54.65#ibcon#read 4, iclass 35, count 0 2006.201.08:43:54.65#ibcon#about to read 5, iclass 35, count 0 2006.201.08:43:54.65#ibcon#read 5, iclass 35, count 0 2006.201.08:43:54.65#ibcon#about to read 6, iclass 35, count 0 2006.201.08:43:54.65#ibcon#read 6, iclass 35, count 0 2006.201.08:43:54.65#ibcon#end of sib2, iclass 35, count 0 2006.201.08:43:54.65#ibcon#*after write, iclass 35, count 0 2006.201.08:43:54.65#ibcon#*before return 0, iclass 35, count 0 2006.201.08:43:54.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:54.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:54.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:43:54.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:43:54.65$vck44/vb=1,4 2006.201.08:43:54.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.08:43:54.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.08:43:54.65#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:54.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:43:54.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:43:54.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:43:54.65#ibcon#enter wrdev, iclass 37, count 2 2006.201.08:43:54.65#ibcon#first serial, iclass 37, count 2 2006.201.08:43:54.65#ibcon#enter sib2, iclass 37, count 2 2006.201.08:43:54.65#ibcon#flushed, iclass 37, count 2 2006.201.08:43:54.65#ibcon#about to write, iclass 37, count 2 2006.201.08:43:54.65#ibcon#wrote, iclass 37, count 2 2006.201.08:43:54.65#ibcon#about to read 3, iclass 37, count 2 2006.201.08:43:54.67#ibcon#read 3, iclass 37, count 2 2006.201.08:43:54.67#ibcon#about to read 4, iclass 37, count 2 2006.201.08:43:54.67#ibcon#read 4, iclass 37, count 2 2006.201.08:43:54.67#ibcon#about to read 5, iclass 37, count 2 2006.201.08:43:54.67#ibcon#read 5, iclass 37, count 2 2006.201.08:43:54.67#ibcon#about to read 6, iclass 37, count 2 2006.201.08:43:54.67#ibcon#read 6, iclass 37, count 2 2006.201.08:43:54.67#ibcon#end of sib2, iclass 37, count 2 2006.201.08:43:54.67#ibcon#*mode == 0, iclass 37, count 2 2006.201.08:43:54.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.08:43:54.67#ibcon#[27=AT01-04\r\n] 2006.201.08:43:54.67#ibcon#*before write, iclass 37, count 2 2006.201.08:43:54.67#ibcon#enter sib2, iclass 37, count 2 2006.201.08:43:54.67#ibcon#flushed, iclass 37, count 2 2006.201.08:43:54.67#ibcon#about to write, iclass 37, count 2 2006.201.08:43:54.67#ibcon#wrote, iclass 37, count 2 2006.201.08:43:54.67#ibcon#about to read 3, iclass 37, count 2 2006.201.08:43:54.70#ibcon#read 3, iclass 37, count 2 2006.201.08:43:54.70#ibcon#about to read 4, iclass 37, count 2 2006.201.08:43:54.70#ibcon#read 4, iclass 37, count 2 2006.201.08:43:54.70#ibcon#about to read 5, iclass 37, count 2 2006.201.08:43:54.70#ibcon#read 5, iclass 37, count 2 2006.201.08:43:54.70#ibcon#about to read 6, iclass 37, count 2 2006.201.08:43:54.70#ibcon#read 6, iclass 37, count 2 2006.201.08:43:54.70#ibcon#end of sib2, iclass 37, count 2 2006.201.08:43:54.70#ibcon#*after write, iclass 37, count 2 2006.201.08:43:54.70#ibcon#*before return 0, iclass 37, count 2 2006.201.08:43:54.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:43:54.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.08:43:54.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.08:43:54.70#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:54.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:43:54.73#abcon#<5=/05 2.3 3.8 23.07 891003.6\r\n> 2006.201.08:43:54.75#abcon#{5=INTERFACE CLEAR} 2006.201.08:43:54.81#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:43:54.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:43:54.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:43:54.82#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:43:54.82#ibcon#first serial, iclass 37, count 0 2006.201.08:43:54.82#ibcon#enter sib2, iclass 37, count 0 2006.201.08:43:54.82#ibcon#flushed, iclass 37, count 0 2006.201.08:43:54.82#ibcon#about to write, iclass 37, count 0 2006.201.08:43:54.82#ibcon#wrote, iclass 37, count 0 2006.201.08:43:54.82#ibcon#about to read 3, iclass 37, count 0 2006.201.08:43:54.84#ibcon#read 3, iclass 37, count 0 2006.201.08:43:54.84#ibcon#about to read 4, iclass 37, count 0 2006.201.08:43:54.84#ibcon#read 4, iclass 37, count 0 2006.201.08:43:54.84#ibcon#about to read 5, iclass 37, count 0 2006.201.08:43:54.84#ibcon#read 5, iclass 37, count 0 2006.201.08:43:54.84#ibcon#about to read 6, iclass 37, count 0 2006.201.08:43:54.84#ibcon#read 6, iclass 37, count 0 2006.201.08:43:54.84#ibcon#end of sib2, iclass 37, count 0 2006.201.08:43:54.84#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:43:54.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:43:54.84#ibcon#[27=USB\r\n] 2006.201.08:43:54.84#ibcon#*before write, iclass 37, count 0 2006.201.08:43:54.84#ibcon#enter sib2, iclass 37, count 0 2006.201.08:43:54.84#ibcon#flushed, iclass 37, count 0 2006.201.08:43:54.84#ibcon#about to write, iclass 37, count 0 2006.201.08:43:54.84#ibcon#wrote, iclass 37, count 0 2006.201.08:43:54.84#ibcon#about to read 3, iclass 37, count 0 2006.201.08:43:54.87#ibcon#read 3, iclass 37, count 0 2006.201.08:43:54.87#ibcon#about to read 4, iclass 37, count 0 2006.201.08:43:54.87#ibcon#read 4, iclass 37, count 0 2006.201.08:43:54.87#ibcon#about to read 5, iclass 37, count 0 2006.201.08:43:54.87#ibcon#read 5, iclass 37, count 0 2006.201.08:43:54.87#ibcon#about to read 6, iclass 37, count 0 2006.201.08:43:54.87#ibcon#read 6, iclass 37, count 0 2006.201.08:43:54.87#ibcon#end of sib2, iclass 37, count 0 2006.201.08:43:54.87#ibcon#*after write, iclass 37, count 0 2006.201.08:43:54.87#ibcon#*before return 0, iclass 37, count 0 2006.201.08:43:54.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:43:54.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.08:43:54.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:43:54.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:43:54.87$vck44/vblo=2,634.99 2006.201.08:43:54.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.08:43:54.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.08:43:54.87#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:54.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:54.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:54.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:54.87#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:43:54.87#ibcon#first serial, iclass 5, count 0 2006.201.08:43:54.87#ibcon#enter sib2, iclass 5, count 0 2006.201.08:43:54.87#ibcon#flushed, iclass 5, count 0 2006.201.08:43:54.87#ibcon#about to write, iclass 5, count 0 2006.201.08:43:54.87#ibcon#wrote, iclass 5, count 0 2006.201.08:43:54.87#ibcon#about to read 3, iclass 5, count 0 2006.201.08:43:54.89#ibcon#read 3, iclass 5, count 0 2006.201.08:43:54.89#ibcon#about to read 4, iclass 5, count 0 2006.201.08:43:54.89#ibcon#read 4, iclass 5, count 0 2006.201.08:43:54.89#ibcon#about to read 5, iclass 5, count 0 2006.201.08:43:54.89#ibcon#read 5, iclass 5, count 0 2006.201.08:43:54.89#ibcon#about to read 6, iclass 5, count 0 2006.201.08:43:54.89#ibcon#read 6, iclass 5, count 0 2006.201.08:43:54.89#ibcon#end of sib2, iclass 5, count 0 2006.201.08:43:54.89#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:43:54.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:43:54.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:43:54.89#ibcon#*before write, iclass 5, count 0 2006.201.08:43:54.89#ibcon#enter sib2, iclass 5, count 0 2006.201.08:43:54.89#ibcon#flushed, iclass 5, count 0 2006.201.08:43:54.89#ibcon#about to write, iclass 5, count 0 2006.201.08:43:54.89#ibcon#wrote, iclass 5, count 0 2006.201.08:43:54.89#ibcon#about to read 3, iclass 5, count 0 2006.201.08:43:54.93#ibcon#read 3, iclass 5, count 0 2006.201.08:43:54.93#ibcon#about to read 4, iclass 5, count 0 2006.201.08:43:54.93#ibcon#read 4, iclass 5, count 0 2006.201.08:43:54.93#ibcon#about to read 5, iclass 5, count 0 2006.201.08:43:54.93#ibcon#read 5, iclass 5, count 0 2006.201.08:43:54.93#ibcon#about to read 6, iclass 5, count 0 2006.201.08:43:54.93#ibcon#read 6, iclass 5, count 0 2006.201.08:43:54.93#ibcon#end of sib2, iclass 5, count 0 2006.201.08:43:54.93#ibcon#*after write, iclass 5, count 0 2006.201.08:43:54.93#ibcon#*before return 0, iclass 5, count 0 2006.201.08:43:54.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:54.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.08:43:54.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:43:54.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:43:54.93$vck44/vb=2,5 2006.201.08:43:54.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.08:43:54.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.08:43:54.93#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:54.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:54.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:54.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:54.99#ibcon#enter wrdev, iclass 7, count 2 2006.201.08:43:54.99#ibcon#first serial, iclass 7, count 2 2006.201.08:43:54.99#ibcon#enter sib2, iclass 7, count 2 2006.201.08:43:54.99#ibcon#flushed, iclass 7, count 2 2006.201.08:43:54.99#ibcon#about to write, iclass 7, count 2 2006.201.08:43:54.99#ibcon#wrote, iclass 7, count 2 2006.201.08:43:54.99#ibcon#about to read 3, iclass 7, count 2 2006.201.08:43:55.01#ibcon#read 3, iclass 7, count 2 2006.201.08:43:55.01#ibcon#about to read 4, iclass 7, count 2 2006.201.08:43:55.01#ibcon#read 4, iclass 7, count 2 2006.201.08:43:55.01#ibcon#about to read 5, iclass 7, count 2 2006.201.08:43:55.01#ibcon#read 5, iclass 7, count 2 2006.201.08:43:55.01#ibcon#about to read 6, iclass 7, count 2 2006.201.08:43:55.01#ibcon#read 6, iclass 7, count 2 2006.201.08:43:55.01#ibcon#end of sib2, iclass 7, count 2 2006.201.08:43:55.01#ibcon#*mode == 0, iclass 7, count 2 2006.201.08:43:55.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.08:43:55.01#ibcon#[27=AT02-05\r\n] 2006.201.08:43:55.01#ibcon#*before write, iclass 7, count 2 2006.201.08:43:55.01#ibcon#enter sib2, iclass 7, count 2 2006.201.08:43:55.01#ibcon#flushed, iclass 7, count 2 2006.201.08:43:55.01#ibcon#about to write, iclass 7, count 2 2006.201.08:43:55.01#ibcon#wrote, iclass 7, count 2 2006.201.08:43:55.01#ibcon#about to read 3, iclass 7, count 2 2006.201.08:43:55.04#ibcon#read 3, iclass 7, count 2 2006.201.08:43:55.04#ibcon#about to read 4, iclass 7, count 2 2006.201.08:43:55.04#ibcon#read 4, iclass 7, count 2 2006.201.08:43:55.04#ibcon#about to read 5, iclass 7, count 2 2006.201.08:43:55.04#ibcon#read 5, iclass 7, count 2 2006.201.08:43:55.04#ibcon#about to read 6, iclass 7, count 2 2006.201.08:43:55.04#ibcon#read 6, iclass 7, count 2 2006.201.08:43:55.04#ibcon#end of sib2, iclass 7, count 2 2006.201.08:43:55.04#ibcon#*after write, iclass 7, count 2 2006.201.08:43:55.04#ibcon#*before return 0, iclass 7, count 2 2006.201.08:43:55.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:55.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.08:43:55.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.08:43:55.04#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:55.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:55.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:55.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:55.16#ibcon#enter wrdev, iclass 7, count 0 2006.201.08:43:55.16#ibcon#first serial, iclass 7, count 0 2006.201.08:43:55.16#ibcon#enter sib2, iclass 7, count 0 2006.201.08:43:55.16#ibcon#flushed, iclass 7, count 0 2006.201.08:43:55.16#ibcon#about to write, iclass 7, count 0 2006.201.08:43:55.16#ibcon#wrote, iclass 7, count 0 2006.201.08:43:55.16#ibcon#about to read 3, iclass 7, count 0 2006.201.08:43:55.18#ibcon#read 3, iclass 7, count 0 2006.201.08:43:55.18#ibcon#about to read 4, iclass 7, count 0 2006.201.08:43:55.18#ibcon#read 4, iclass 7, count 0 2006.201.08:43:55.18#ibcon#about to read 5, iclass 7, count 0 2006.201.08:43:55.18#ibcon#read 5, iclass 7, count 0 2006.201.08:43:55.18#ibcon#about to read 6, iclass 7, count 0 2006.201.08:43:55.18#ibcon#read 6, iclass 7, count 0 2006.201.08:43:55.18#ibcon#end of sib2, iclass 7, count 0 2006.201.08:43:55.18#ibcon#*mode == 0, iclass 7, count 0 2006.201.08:43:55.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.08:43:55.18#ibcon#[27=USB\r\n] 2006.201.08:43:55.18#ibcon#*before write, iclass 7, count 0 2006.201.08:43:55.18#ibcon#enter sib2, iclass 7, count 0 2006.201.08:43:55.18#ibcon#flushed, iclass 7, count 0 2006.201.08:43:55.18#ibcon#about to write, iclass 7, count 0 2006.201.08:43:55.18#ibcon#wrote, iclass 7, count 0 2006.201.08:43:55.18#ibcon#about to read 3, iclass 7, count 0 2006.201.08:43:55.21#ibcon#read 3, iclass 7, count 0 2006.201.08:43:55.21#ibcon#about to read 4, iclass 7, count 0 2006.201.08:43:55.21#ibcon#read 4, iclass 7, count 0 2006.201.08:43:55.21#ibcon#about to read 5, iclass 7, count 0 2006.201.08:43:55.21#ibcon#read 5, iclass 7, count 0 2006.201.08:43:55.21#ibcon#about to read 6, iclass 7, count 0 2006.201.08:43:55.21#ibcon#read 6, iclass 7, count 0 2006.201.08:43:55.21#ibcon#end of sib2, iclass 7, count 0 2006.201.08:43:55.21#ibcon#*after write, iclass 7, count 0 2006.201.08:43:55.21#ibcon#*before return 0, iclass 7, count 0 2006.201.08:43:55.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:55.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.08:43:55.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.08:43:55.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.08:43:55.21$vck44/vblo=3,649.99 2006.201.08:43:55.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.08:43:55.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.08:43:55.21#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:55.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:55.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:55.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:55.21#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:43:55.21#ibcon#first serial, iclass 11, count 0 2006.201.08:43:55.21#ibcon#enter sib2, iclass 11, count 0 2006.201.08:43:55.21#ibcon#flushed, iclass 11, count 0 2006.201.08:43:55.21#ibcon#about to write, iclass 11, count 0 2006.201.08:43:55.21#ibcon#wrote, iclass 11, count 0 2006.201.08:43:55.21#ibcon#about to read 3, iclass 11, count 0 2006.201.08:43:55.23#ibcon#read 3, iclass 11, count 0 2006.201.08:43:55.23#ibcon#about to read 4, iclass 11, count 0 2006.201.08:43:55.23#ibcon#read 4, iclass 11, count 0 2006.201.08:43:55.23#ibcon#about to read 5, iclass 11, count 0 2006.201.08:43:55.23#ibcon#read 5, iclass 11, count 0 2006.201.08:43:55.23#ibcon#about to read 6, iclass 11, count 0 2006.201.08:43:55.23#ibcon#read 6, iclass 11, count 0 2006.201.08:43:55.23#ibcon#end of sib2, iclass 11, count 0 2006.201.08:43:55.23#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:43:55.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:43:55.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:43:55.23#ibcon#*before write, iclass 11, count 0 2006.201.08:43:55.23#ibcon#enter sib2, iclass 11, count 0 2006.201.08:43:55.23#ibcon#flushed, iclass 11, count 0 2006.201.08:43:55.23#ibcon#about to write, iclass 11, count 0 2006.201.08:43:55.23#ibcon#wrote, iclass 11, count 0 2006.201.08:43:55.23#ibcon#about to read 3, iclass 11, count 0 2006.201.08:43:55.28#ibcon#read 3, iclass 11, count 0 2006.201.08:43:55.28#ibcon#about to read 4, iclass 11, count 0 2006.201.08:43:55.28#ibcon#read 4, iclass 11, count 0 2006.201.08:43:55.28#ibcon#about to read 5, iclass 11, count 0 2006.201.08:43:55.28#ibcon#read 5, iclass 11, count 0 2006.201.08:43:55.28#ibcon#about to read 6, iclass 11, count 0 2006.201.08:43:55.28#ibcon#read 6, iclass 11, count 0 2006.201.08:43:55.28#ibcon#end of sib2, iclass 11, count 0 2006.201.08:43:55.28#ibcon#*after write, iclass 11, count 0 2006.201.08:43:55.28#ibcon#*before return 0, iclass 11, count 0 2006.201.08:43:55.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:55.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.08:43:55.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:43:55.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:43:55.28$vck44/vb=3,4 2006.201.08:43:55.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.08:43:55.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.08:43:55.28#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:55.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:55.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:55.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:55.33#ibcon#enter wrdev, iclass 13, count 2 2006.201.08:43:55.33#ibcon#first serial, iclass 13, count 2 2006.201.08:43:55.33#ibcon#enter sib2, iclass 13, count 2 2006.201.08:43:55.33#ibcon#flushed, iclass 13, count 2 2006.201.08:43:55.33#ibcon#about to write, iclass 13, count 2 2006.201.08:43:55.33#ibcon#wrote, iclass 13, count 2 2006.201.08:43:55.33#ibcon#about to read 3, iclass 13, count 2 2006.201.08:43:55.35#ibcon#read 3, iclass 13, count 2 2006.201.08:43:55.35#ibcon#about to read 4, iclass 13, count 2 2006.201.08:43:55.35#ibcon#read 4, iclass 13, count 2 2006.201.08:43:55.35#ibcon#about to read 5, iclass 13, count 2 2006.201.08:43:55.35#ibcon#read 5, iclass 13, count 2 2006.201.08:43:55.35#ibcon#about to read 6, iclass 13, count 2 2006.201.08:43:55.35#ibcon#read 6, iclass 13, count 2 2006.201.08:43:55.35#ibcon#end of sib2, iclass 13, count 2 2006.201.08:43:55.35#ibcon#*mode == 0, iclass 13, count 2 2006.201.08:43:55.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.08:43:55.35#ibcon#[27=AT03-04\r\n] 2006.201.08:43:55.35#ibcon#*before write, iclass 13, count 2 2006.201.08:43:55.35#ibcon#enter sib2, iclass 13, count 2 2006.201.08:43:55.35#ibcon#flushed, iclass 13, count 2 2006.201.08:43:55.35#ibcon#about to write, iclass 13, count 2 2006.201.08:43:55.35#ibcon#wrote, iclass 13, count 2 2006.201.08:43:55.35#ibcon#about to read 3, iclass 13, count 2 2006.201.08:43:55.38#ibcon#read 3, iclass 13, count 2 2006.201.08:43:55.38#ibcon#about to read 4, iclass 13, count 2 2006.201.08:43:55.38#ibcon#read 4, iclass 13, count 2 2006.201.08:43:55.38#ibcon#about to read 5, iclass 13, count 2 2006.201.08:43:55.38#ibcon#read 5, iclass 13, count 2 2006.201.08:43:55.38#ibcon#about to read 6, iclass 13, count 2 2006.201.08:43:55.38#ibcon#read 6, iclass 13, count 2 2006.201.08:43:55.38#ibcon#end of sib2, iclass 13, count 2 2006.201.08:43:55.38#ibcon#*after write, iclass 13, count 2 2006.201.08:43:55.38#ibcon#*before return 0, iclass 13, count 2 2006.201.08:43:55.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:55.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.08:43:55.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.08:43:55.38#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:55.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:55.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:55.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:55.50#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:43:55.50#ibcon#first serial, iclass 13, count 0 2006.201.08:43:55.50#ibcon#enter sib2, iclass 13, count 0 2006.201.08:43:55.50#ibcon#flushed, iclass 13, count 0 2006.201.08:43:55.50#ibcon#about to write, iclass 13, count 0 2006.201.08:43:55.50#ibcon#wrote, iclass 13, count 0 2006.201.08:43:55.50#ibcon#about to read 3, iclass 13, count 0 2006.201.08:43:55.52#ibcon#read 3, iclass 13, count 0 2006.201.08:43:55.52#ibcon#about to read 4, iclass 13, count 0 2006.201.08:43:55.52#ibcon#read 4, iclass 13, count 0 2006.201.08:43:55.52#ibcon#about to read 5, iclass 13, count 0 2006.201.08:43:55.52#ibcon#read 5, iclass 13, count 0 2006.201.08:43:55.52#ibcon#about to read 6, iclass 13, count 0 2006.201.08:43:55.52#ibcon#read 6, iclass 13, count 0 2006.201.08:43:55.52#ibcon#end of sib2, iclass 13, count 0 2006.201.08:43:55.52#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:43:55.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:43:55.52#ibcon#[27=USB\r\n] 2006.201.08:43:55.52#ibcon#*before write, iclass 13, count 0 2006.201.08:43:55.52#ibcon#enter sib2, iclass 13, count 0 2006.201.08:43:55.52#ibcon#flushed, iclass 13, count 0 2006.201.08:43:55.52#ibcon#about to write, iclass 13, count 0 2006.201.08:43:55.52#ibcon#wrote, iclass 13, count 0 2006.201.08:43:55.52#ibcon#about to read 3, iclass 13, count 0 2006.201.08:43:55.55#ibcon#read 3, iclass 13, count 0 2006.201.08:43:55.55#ibcon#about to read 4, iclass 13, count 0 2006.201.08:43:55.55#ibcon#read 4, iclass 13, count 0 2006.201.08:43:55.55#ibcon#about to read 5, iclass 13, count 0 2006.201.08:43:55.55#ibcon#read 5, iclass 13, count 0 2006.201.08:43:55.55#ibcon#about to read 6, iclass 13, count 0 2006.201.08:43:55.55#ibcon#read 6, iclass 13, count 0 2006.201.08:43:55.55#ibcon#end of sib2, iclass 13, count 0 2006.201.08:43:55.55#ibcon#*after write, iclass 13, count 0 2006.201.08:43:55.55#ibcon#*before return 0, iclass 13, count 0 2006.201.08:43:55.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:55.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.08:43:55.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:43:55.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:43:55.55$vck44/vblo=4,679.99 2006.201.08:43:55.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.08:43:55.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.08:43:55.55#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:55.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:55.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:55.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:55.55#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:43:55.55#ibcon#first serial, iclass 15, count 0 2006.201.08:43:55.55#ibcon#enter sib2, iclass 15, count 0 2006.201.08:43:55.55#ibcon#flushed, iclass 15, count 0 2006.201.08:43:55.55#ibcon#about to write, iclass 15, count 0 2006.201.08:43:55.55#ibcon#wrote, iclass 15, count 0 2006.201.08:43:55.55#ibcon#about to read 3, iclass 15, count 0 2006.201.08:43:55.57#ibcon#read 3, iclass 15, count 0 2006.201.08:43:55.57#ibcon#about to read 4, iclass 15, count 0 2006.201.08:43:55.57#ibcon#read 4, iclass 15, count 0 2006.201.08:43:55.57#ibcon#about to read 5, iclass 15, count 0 2006.201.08:43:55.57#ibcon#read 5, iclass 15, count 0 2006.201.08:43:55.57#ibcon#about to read 6, iclass 15, count 0 2006.201.08:43:55.57#ibcon#read 6, iclass 15, count 0 2006.201.08:43:55.57#ibcon#end of sib2, iclass 15, count 0 2006.201.08:43:55.57#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:43:55.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:43:55.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:43:55.57#ibcon#*before write, iclass 15, count 0 2006.201.08:43:55.57#ibcon#enter sib2, iclass 15, count 0 2006.201.08:43:55.57#ibcon#flushed, iclass 15, count 0 2006.201.08:43:55.57#ibcon#about to write, iclass 15, count 0 2006.201.08:43:55.57#ibcon#wrote, iclass 15, count 0 2006.201.08:43:55.57#ibcon#about to read 3, iclass 15, count 0 2006.201.08:43:55.62#ibcon#read 3, iclass 15, count 0 2006.201.08:43:55.62#ibcon#about to read 4, iclass 15, count 0 2006.201.08:43:55.62#ibcon#read 4, iclass 15, count 0 2006.201.08:43:55.62#ibcon#about to read 5, iclass 15, count 0 2006.201.08:43:55.62#ibcon#read 5, iclass 15, count 0 2006.201.08:43:55.62#ibcon#about to read 6, iclass 15, count 0 2006.201.08:43:55.62#ibcon#read 6, iclass 15, count 0 2006.201.08:43:55.62#ibcon#end of sib2, iclass 15, count 0 2006.201.08:43:55.62#ibcon#*after write, iclass 15, count 0 2006.201.08:43:55.62#ibcon#*before return 0, iclass 15, count 0 2006.201.08:43:55.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:55.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.08:43:55.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:43:55.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:43:55.62$vck44/vb=4,5 2006.201.08:43:55.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.08:43:55.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.08:43:55.62#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:55.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:55.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:55.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:55.67#ibcon#enter wrdev, iclass 17, count 2 2006.201.08:43:55.67#ibcon#first serial, iclass 17, count 2 2006.201.08:43:55.67#ibcon#enter sib2, iclass 17, count 2 2006.201.08:43:55.67#ibcon#flushed, iclass 17, count 2 2006.201.08:43:55.67#ibcon#about to write, iclass 17, count 2 2006.201.08:43:55.67#ibcon#wrote, iclass 17, count 2 2006.201.08:43:55.67#ibcon#about to read 3, iclass 17, count 2 2006.201.08:43:55.69#ibcon#read 3, iclass 17, count 2 2006.201.08:43:55.69#ibcon#about to read 4, iclass 17, count 2 2006.201.08:43:55.69#ibcon#read 4, iclass 17, count 2 2006.201.08:43:55.69#ibcon#about to read 5, iclass 17, count 2 2006.201.08:43:55.69#ibcon#read 5, iclass 17, count 2 2006.201.08:43:55.69#ibcon#about to read 6, iclass 17, count 2 2006.201.08:43:55.69#ibcon#read 6, iclass 17, count 2 2006.201.08:43:55.69#ibcon#end of sib2, iclass 17, count 2 2006.201.08:43:55.69#ibcon#*mode == 0, iclass 17, count 2 2006.201.08:43:55.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.08:43:55.69#ibcon#[27=AT04-05\r\n] 2006.201.08:43:55.69#ibcon#*before write, iclass 17, count 2 2006.201.08:43:55.69#ibcon#enter sib2, iclass 17, count 2 2006.201.08:43:55.69#ibcon#flushed, iclass 17, count 2 2006.201.08:43:55.69#ibcon#about to write, iclass 17, count 2 2006.201.08:43:55.69#ibcon#wrote, iclass 17, count 2 2006.201.08:43:55.69#ibcon#about to read 3, iclass 17, count 2 2006.201.08:43:55.72#ibcon#read 3, iclass 17, count 2 2006.201.08:43:55.72#ibcon#about to read 4, iclass 17, count 2 2006.201.08:43:55.72#ibcon#read 4, iclass 17, count 2 2006.201.08:43:55.72#ibcon#about to read 5, iclass 17, count 2 2006.201.08:43:55.72#ibcon#read 5, iclass 17, count 2 2006.201.08:43:55.72#ibcon#about to read 6, iclass 17, count 2 2006.201.08:43:55.72#ibcon#read 6, iclass 17, count 2 2006.201.08:43:55.72#ibcon#end of sib2, iclass 17, count 2 2006.201.08:43:55.72#ibcon#*after write, iclass 17, count 2 2006.201.08:43:55.72#ibcon#*before return 0, iclass 17, count 2 2006.201.08:43:55.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:55.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.08:43:55.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.08:43:55.72#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:55.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:55.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:55.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:55.84#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:43:55.84#ibcon#first serial, iclass 17, count 0 2006.201.08:43:55.84#ibcon#enter sib2, iclass 17, count 0 2006.201.08:43:55.84#ibcon#flushed, iclass 17, count 0 2006.201.08:43:55.84#ibcon#about to write, iclass 17, count 0 2006.201.08:43:55.84#ibcon#wrote, iclass 17, count 0 2006.201.08:43:55.84#ibcon#about to read 3, iclass 17, count 0 2006.201.08:43:55.86#ibcon#read 3, iclass 17, count 0 2006.201.08:43:55.86#ibcon#about to read 4, iclass 17, count 0 2006.201.08:43:55.86#ibcon#read 4, iclass 17, count 0 2006.201.08:43:55.86#ibcon#about to read 5, iclass 17, count 0 2006.201.08:43:55.86#ibcon#read 5, iclass 17, count 0 2006.201.08:43:55.86#ibcon#about to read 6, iclass 17, count 0 2006.201.08:43:55.86#ibcon#read 6, iclass 17, count 0 2006.201.08:43:55.86#ibcon#end of sib2, iclass 17, count 0 2006.201.08:43:55.86#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:43:55.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:43:55.86#ibcon#[27=USB\r\n] 2006.201.08:43:55.86#ibcon#*before write, iclass 17, count 0 2006.201.08:43:55.86#ibcon#enter sib2, iclass 17, count 0 2006.201.08:43:55.86#ibcon#flushed, iclass 17, count 0 2006.201.08:43:55.86#ibcon#about to write, iclass 17, count 0 2006.201.08:43:55.86#ibcon#wrote, iclass 17, count 0 2006.201.08:43:55.86#ibcon#about to read 3, iclass 17, count 0 2006.201.08:43:55.89#ibcon#read 3, iclass 17, count 0 2006.201.08:43:55.89#ibcon#about to read 4, iclass 17, count 0 2006.201.08:43:55.89#ibcon#read 4, iclass 17, count 0 2006.201.08:43:55.89#ibcon#about to read 5, iclass 17, count 0 2006.201.08:43:55.89#ibcon#read 5, iclass 17, count 0 2006.201.08:43:55.89#ibcon#about to read 6, iclass 17, count 0 2006.201.08:43:55.89#ibcon#read 6, iclass 17, count 0 2006.201.08:43:55.89#ibcon#end of sib2, iclass 17, count 0 2006.201.08:43:55.89#ibcon#*after write, iclass 17, count 0 2006.201.08:43:55.89#ibcon#*before return 0, iclass 17, count 0 2006.201.08:43:55.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:55.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.08:43:55.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:43:55.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:43:55.89$vck44/vblo=5,709.99 2006.201.08:43:55.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.08:43:55.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.08:43:55.89#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:55.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:55.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:55.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:55.89#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:43:55.89#ibcon#first serial, iclass 19, count 0 2006.201.08:43:55.89#ibcon#enter sib2, iclass 19, count 0 2006.201.08:43:55.89#ibcon#flushed, iclass 19, count 0 2006.201.08:43:55.89#ibcon#about to write, iclass 19, count 0 2006.201.08:43:55.89#ibcon#wrote, iclass 19, count 0 2006.201.08:43:55.89#ibcon#about to read 3, iclass 19, count 0 2006.201.08:43:55.91#ibcon#read 3, iclass 19, count 0 2006.201.08:43:55.91#ibcon#about to read 4, iclass 19, count 0 2006.201.08:43:55.91#ibcon#read 4, iclass 19, count 0 2006.201.08:43:55.91#ibcon#about to read 5, iclass 19, count 0 2006.201.08:43:55.91#ibcon#read 5, iclass 19, count 0 2006.201.08:43:55.91#ibcon#about to read 6, iclass 19, count 0 2006.201.08:43:55.91#ibcon#read 6, iclass 19, count 0 2006.201.08:43:55.91#ibcon#end of sib2, iclass 19, count 0 2006.201.08:43:55.91#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:43:55.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:43:55.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:43:55.91#ibcon#*before write, iclass 19, count 0 2006.201.08:43:55.91#ibcon#enter sib2, iclass 19, count 0 2006.201.08:43:55.91#ibcon#flushed, iclass 19, count 0 2006.201.08:43:55.91#ibcon#about to write, iclass 19, count 0 2006.201.08:43:55.91#ibcon#wrote, iclass 19, count 0 2006.201.08:43:55.91#ibcon#about to read 3, iclass 19, count 0 2006.201.08:43:55.95#ibcon#read 3, iclass 19, count 0 2006.201.08:43:55.95#ibcon#about to read 4, iclass 19, count 0 2006.201.08:43:55.95#ibcon#read 4, iclass 19, count 0 2006.201.08:43:55.95#ibcon#about to read 5, iclass 19, count 0 2006.201.08:43:55.95#ibcon#read 5, iclass 19, count 0 2006.201.08:43:55.95#ibcon#about to read 6, iclass 19, count 0 2006.201.08:43:55.95#ibcon#read 6, iclass 19, count 0 2006.201.08:43:55.95#ibcon#end of sib2, iclass 19, count 0 2006.201.08:43:55.95#ibcon#*after write, iclass 19, count 0 2006.201.08:43:55.95#ibcon#*before return 0, iclass 19, count 0 2006.201.08:43:55.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:55.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:43:55.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:43:55.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:43:55.95$vck44/vb=5,4 2006.201.08:43:55.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.08:43:55.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.08:43:55.95#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:55.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:56.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:56.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:56.01#ibcon#enter wrdev, iclass 21, count 2 2006.201.08:43:56.01#ibcon#first serial, iclass 21, count 2 2006.201.08:43:56.01#ibcon#enter sib2, iclass 21, count 2 2006.201.08:43:56.01#ibcon#flushed, iclass 21, count 2 2006.201.08:43:56.01#ibcon#about to write, iclass 21, count 2 2006.201.08:43:56.01#ibcon#wrote, iclass 21, count 2 2006.201.08:43:56.01#ibcon#about to read 3, iclass 21, count 2 2006.201.08:43:56.03#ibcon#read 3, iclass 21, count 2 2006.201.08:43:56.03#ibcon#about to read 4, iclass 21, count 2 2006.201.08:43:56.03#ibcon#read 4, iclass 21, count 2 2006.201.08:43:56.03#ibcon#about to read 5, iclass 21, count 2 2006.201.08:43:56.03#ibcon#read 5, iclass 21, count 2 2006.201.08:43:56.03#ibcon#about to read 6, iclass 21, count 2 2006.201.08:43:56.03#ibcon#read 6, iclass 21, count 2 2006.201.08:43:56.03#ibcon#end of sib2, iclass 21, count 2 2006.201.08:43:56.03#ibcon#*mode == 0, iclass 21, count 2 2006.201.08:43:56.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.08:43:56.03#ibcon#[27=AT05-04\r\n] 2006.201.08:43:56.03#ibcon#*before write, iclass 21, count 2 2006.201.08:43:56.03#ibcon#enter sib2, iclass 21, count 2 2006.201.08:43:56.03#ibcon#flushed, iclass 21, count 2 2006.201.08:43:56.03#ibcon#about to write, iclass 21, count 2 2006.201.08:43:56.03#ibcon#wrote, iclass 21, count 2 2006.201.08:43:56.03#ibcon#about to read 3, iclass 21, count 2 2006.201.08:43:56.06#ibcon#read 3, iclass 21, count 2 2006.201.08:43:56.06#ibcon#about to read 4, iclass 21, count 2 2006.201.08:43:56.06#ibcon#read 4, iclass 21, count 2 2006.201.08:43:56.06#ibcon#about to read 5, iclass 21, count 2 2006.201.08:43:56.06#ibcon#read 5, iclass 21, count 2 2006.201.08:43:56.06#ibcon#about to read 6, iclass 21, count 2 2006.201.08:43:56.06#ibcon#read 6, iclass 21, count 2 2006.201.08:43:56.06#ibcon#end of sib2, iclass 21, count 2 2006.201.08:43:56.06#ibcon#*after write, iclass 21, count 2 2006.201.08:43:56.06#ibcon#*before return 0, iclass 21, count 2 2006.201.08:43:56.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:56.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.08:43:56.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.08:43:56.06#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:56.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:56.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:56.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:56.18#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:43:56.18#ibcon#first serial, iclass 21, count 0 2006.201.08:43:56.18#ibcon#enter sib2, iclass 21, count 0 2006.201.08:43:56.18#ibcon#flushed, iclass 21, count 0 2006.201.08:43:56.18#ibcon#about to write, iclass 21, count 0 2006.201.08:43:56.18#ibcon#wrote, iclass 21, count 0 2006.201.08:43:56.18#ibcon#about to read 3, iclass 21, count 0 2006.201.08:43:56.20#ibcon#read 3, iclass 21, count 0 2006.201.08:43:56.20#ibcon#about to read 4, iclass 21, count 0 2006.201.08:43:56.20#ibcon#read 4, iclass 21, count 0 2006.201.08:43:56.20#ibcon#about to read 5, iclass 21, count 0 2006.201.08:43:56.20#ibcon#read 5, iclass 21, count 0 2006.201.08:43:56.20#ibcon#about to read 6, iclass 21, count 0 2006.201.08:43:56.20#ibcon#read 6, iclass 21, count 0 2006.201.08:43:56.20#ibcon#end of sib2, iclass 21, count 0 2006.201.08:43:56.20#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:43:56.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:43:56.20#ibcon#[27=USB\r\n] 2006.201.08:43:56.20#ibcon#*before write, iclass 21, count 0 2006.201.08:43:56.20#ibcon#enter sib2, iclass 21, count 0 2006.201.08:43:56.20#ibcon#flushed, iclass 21, count 0 2006.201.08:43:56.20#ibcon#about to write, iclass 21, count 0 2006.201.08:43:56.20#ibcon#wrote, iclass 21, count 0 2006.201.08:43:56.20#ibcon#about to read 3, iclass 21, count 0 2006.201.08:43:56.23#ibcon#read 3, iclass 21, count 0 2006.201.08:43:56.23#ibcon#about to read 4, iclass 21, count 0 2006.201.08:43:56.23#ibcon#read 4, iclass 21, count 0 2006.201.08:43:56.23#ibcon#about to read 5, iclass 21, count 0 2006.201.08:43:56.23#ibcon#read 5, iclass 21, count 0 2006.201.08:43:56.23#ibcon#about to read 6, iclass 21, count 0 2006.201.08:43:56.23#ibcon#read 6, iclass 21, count 0 2006.201.08:43:56.23#ibcon#end of sib2, iclass 21, count 0 2006.201.08:43:56.23#ibcon#*after write, iclass 21, count 0 2006.201.08:43:56.23#ibcon#*before return 0, iclass 21, count 0 2006.201.08:43:56.23#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:56.23#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.08:43:56.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:43:56.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:43:56.23$vck44/vblo=6,719.99 2006.201.08:43:56.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.08:43:56.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.08:43:56.23#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:56.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:56.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:56.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:56.23#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:43:56.23#ibcon#first serial, iclass 23, count 0 2006.201.08:43:56.23#ibcon#enter sib2, iclass 23, count 0 2006.201.08:43:56.23#ibcon#flushed, iclass 23, count 0 2006.201.08:43:56.23#ibcon#about to write, iclass 23, count 0 2006.201.08:43:56.23#ibcon#wrote, iclass 23, count 0 2006.201.08:43:56.23#ibcon#about to read 3, iclass 23, count 0 2006.201.08:43:56.25#ibcon#read 3, iclass 23, count 0 2006.201.08:43:56.25#ibcon#about to read 4, iclass 23, count 0 2006.201.08:43:56.25#ibcon#read 4, iclass 23, count 0 2006.201.08:43:56.25#ibcon#about to read 5, iclass 23, count 0 2006.201.08:43:56.25#ibcon#read 5, iclass 23, count 0 2006.201.08:43:56.25#ibcon#about to read 6, iclass 23, count 0 2006.201.08:43:56.25#ibcon#read 6, iclass 23, count 0 2006.201.08:43:56.25#ibcon#end of sib2, iclass 23, count 0 2006.201.08:43:56.25#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:43:56.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:43:56.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:43:56.25#ibcon#*before write, iclass 23, count 0 2006.201.08:43:56.25#ibcon#enter sib2, iclass 23, count 0 2006.201.08:43:56.25#ibcon#flushed, iclass 23, count 0 2006.201.08:43:56.25#ibcon#about to write, iclass 23, count 0 2006.201.08:43:56.25#ibcon#wrote, iclass 23, count 0 2006.201.08:43:56.25#ibcon#about to read 3, iclass 23, count 0 2006.201.08:43:56.30#ibcon#read 3, iclass 23, count 0 2006.201.08:43:56.30#ibcon#about to read 4, iclass 23, count 0 2006.201.08:43:56.30#ibcon#read 4, iclass 23, count 0 2006.201.08:43:56.30#ibcon#about to read 5, iclass 23, count 0 2006.201.08:43:56.30#ibcon#read 5, iclass 23, count 0 2006.201.08:43:56.30#ibcon#about to read 6, iclass 23, count 0 2006.201.08:43:56.30#ibcon#read 6, iclass 23, count 0 2006.201.08:43:56.30#ibcon#end of sib2, iclass 23, count 0 2006.201.08:43:56.30#ibcon#*after write, iclass 23, count 0 2006.201.08:43:56.30#ibcon#*before return 0, iclass 23, count 0 2006.201.08:43:56.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:56.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.08:43:56.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:43:56.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:43:56.30$vck44/vb=6,4 2006.201.08:43:56.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.08:43:56.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.08:43:56.30#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:56.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:56.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:56.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:56.35#ibcon#enter wrdev, iclass 25, count 2 2006.201.08:43:56.35#ibcon#first serial, iclass 25, count 2 2006.201.08:43:56.35#ibcon#enter sib2, iclass 25, count 2 2006.201.08:43:56.35#ibcon#flushed, iclass 25, count 2 2006.201.08:43:56.35#ibcon#about to write, iclass 25, count 2 2006.201.08:43:56.35#ibcon#wrote, iclass 25, count 2 2006.201.08:43:56.35#ibcon#about to read 3, iclass 25, count 2 2006.201.08:43:56.37#ibcon#read 3, iclass 25, count 2 2006.201.08:43:56.37#ibcon#about to read 4, iclass 25, count 2 2006.201.08:43:56.37#ibcon#read 4, iclass 25, count 2 2006.201.08:43:56.37#ibcon#about to read 5, iclass 25, count 2 2006.201.08:43:56.37#ibcon#read 5, iclass 25, count 2 2006.201.08:43:56.37#ibcon#about to read 6, iclass 25, count 2 2006.201.08:43:56.37#ibcon#read 6, iclass 25, count 2 2006.201.08:43:56.37#ibcon#end of sib2, iclass 25, count 2 2006.201.08:43:56.37#ibcon#*mode == 0, iclass 25, count 2 2006.201.08:43:56.37#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.08:43:56.37#ibcon#[27=AT06-04\r\n] 2006.201.08:43:56.37#ibcon#*before write, iclass 25, count 2 2006.201.08:43:56.37#ibcon#enter sib2, iclass 25, count 2 2006.201.08:43:56.37#ibcon#flushed, iclass 25, count 2 2006.201.08:43:56.37#ibcon#about to write, iclass 25, count 2 2006.201.08:43:56.37#ibcon#wrote, iclass 25, count 2 2006.201.08:43:56.37#ibcon#about to read 3, iclass 25, count 2 2006.201.08:43:56.40#ibcon#read 3, iclass 25, count 2 2006.201.08:43:56.40#ibcon#about to read 4, iclass 25, count 2 2006.201.08:43:56.40#ibcon#read 4, iclass 25, count 2 2006.201.08:43:56.40#ibcon#about to read 5, iclass 25, count 2 2006.201.08:43:56.40#ibcon#read 5, iclass 25, count 2 2006.201.08:43:56.40#ibcon#about to read 6, iclass 25, count 2 2006.201.08:43:56.40#ibcon#read 6, iclass 25, count 2 2006.201.08:43:56.40#ibcon#end of sib2, iclass 25, count 2 2006.201.08:43:56.40#ibcon#*after write, iclass 25, count 2 2006.201.08:43:56.40#ibcon#*before return 0, iclass 25, count 2 2006.201.08:43:56.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:56.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.08:43:56.40#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.08:43:56.40#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:56.40#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:56.52#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:56.52#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:56.52#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:43:56.52#ibcon#first serial, iclass 25, count 0 2006.201.08:43:56.52#ibcon#enter sib2, iclass 25, count 0 2006.201.08:43:56.52#ibcon#flushed, iclass 25, count 0 2006.201.08:43:56.52#ibcon#about to write, iclass 25, count 0 2006.201.08:43:56.52#ibcon#wrote, iclass 25, count 0 2006.201.08:43:56.52#ibcon#about to read 3, iclass 25, count 0 2006.201.08:43:56.54#ibcon#read 3, iclass 25, count 0 2006.201.08:43:56.54#ibcon#about to read 4, iclass 25, count 0 2006.201.08:43:56.54#ibcon#read 4, iclass 25, count 0 2006.201.08:43:56.54#ibcon#about to read 5, iclass 25, count 0 2006.201.08:43:56.54#ibcon#read 5, iclass 25, count 0 2006.201.08:43:56.54#ibcon#about to read 6, iclass 25, count 0 2006.201.08:43:56.54#ibcon#read 6, iclass 25, count 0 2006.201.08:43:56.54#ibcon#end of sib2, iclass 25, count 0 2006.201.08:43:56.54#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:43:56.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:43:56.54#ibcon#[27=USB\r\n] 2006.201.08:43:56.54#ibcon#*before write, iclass 25, count 0 2006.201.08:43:56.54#ibcon#enter sib2, iclass 25, count 0 2006.201.08:43:56.54#ibcon#flushed, iclass 25, count 0 2006.201.08:43:56.54#ibcon#about to write, iclass 25, count 0 2006.201.08:43:56.54#ibcon#wrote, iclass 25, count 0 2006.201.08:43:56.54#ibcon#about to read 3, iclass 25, count 0 2006.201.08:43:56.57#ibcon#read 3, iclass 25, count 0 2006.201.08:43:56.57#ibcon#about to read 4, iclass 25, count 0 2006.201.08:43:56.57#ibcon#read 4, iclass 25, count 0 2006.201.08:43:56.57#ibcon#about to read 5, iclass 25, count 0 2006.201.08:43:56.57#ibcon#read 5, iclass 25, count 0 2006.201.08:43:56.57#ibcon#about to read 6, iclass 25, count 0 2006.201.08:43:56.57#ibcon#read 6, iclass 25, count 0 2006.201.08:43:56.57#ibcon#end of sib2, iclass 25, count 0 2006.201.08:43:56.57#ibcon#*after write, iclass 25, count 0 2006.201.08:43:56.57#ibcon#*before return 0, iclass 25, count 0 2006.201.08:43:56.57#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:56.57#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.08:43:56.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:43:56.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:43:56.57$vck44/vblo=7,734.99 2006.201.08:43:56.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.08:43:56.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.08:43:56.57#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:56.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:56.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:56.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:56.57#ibcon#enter wrdev, iclass 27, count 0 2006.201.08:43:56.57#ibcon#first serial, iclass 27, count 0 2006.201.08:43:56.57#ibcon#enter sib2, iclass 27, count 0 2006.201.08:43:56.57#ibcon#flushed, iclass 27, count 0 2006.201.08:43:56.57#ibcon#about to write, iclass 27, count 0 2006.201.08:43:56.57#ibcon#wrote, iclass 27, count 0 2006.201.08:43:56.57#ibcon#about to read 3, iclass 27, count 0 2006.201.08:43:56.59#ibcon#read 3, iclass 27, count 0 2006.201.08:43:56.59#ibcon#about to read 4, iclass 27, count 0 2006.201.08:43:56.59#ibcon#read 4, iclass 27, count 0 2006.201.08:43:56.59#ibcon#about to read 5, iclass 27, count 0 2006.201.08:43:56.59#ibcon#read 5, iclass 27, count 0 2006.201.08:43:56.59#ibcon#about to read 6, iclass 27, count 0 2006.201.08:43:56.59#ibcon#read 6, iclass 27, count 0 2006.201.08:43:56.59#ibcon#end of sib2, iclass 27, count 0 2006.201.08:43:56.59#ibcon#*mode == 0, iclass 27, count 0 2006.201.08:43:56.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.08:43:56.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:43:56.59#ibcon#*before write, iclass 27, count 0 2006.201.08:43:56.59#ibcon#enter sib2, iclass 27, count 0 2006.201.08:43:56.59#ibcon#flushed, iclass 27, count 0 2006.201.08:43:56.59#ibcon#about to write, iclass 27, count 0 2006.201.08:43:56.59#ibcon#wrote, iclass 27, count 0 2006.201.08:43:56.59#ibcon#about to read 3, iclass 27, count 0 2006.201.08:43:56.63#ibcon#read 3, iclass 27, count 0 2006.201.08:43:56.63#ibcon#about to read 4, iclass 27, count 0 2006.201.08:43:56.63#ibcon#read 4, iclass 27, count 0 2006.201.08:43:56.63#ibcon#about to read 5, iclass 27, count 0 2006.201.08:43:56.63#ibcon#read 5, iclass 27, count 0 2006.201.08:43:56.63#ibcon#about to read 6, iclass 27, count 0 2006.201.08:43:56.63#ibcon#read 6, iclass 27, count 0 2006.201.08:43:56.63#ibcon#end of sib2, iclass 27, count 0 2006.201.08:43:56.63#ibcon#*after write, iclass 27, count 0 2006.201.08:43:56.63#ibcon#*before return 0, iclass 27, count 0 2006.201.08:43:56.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:56.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.08:43:56.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.08:43:56.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.08:43:56.63$vck44/vb=7,4 2006.201.08:43:56.63#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.08:43:56.63#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.08:43:56.63#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:56.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:56.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:56.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:56.69#ibcon#enter wrdev, iclass 29, count 2 2006.201.08:43:56.69#ibcon#first serial, iclass 29, count 2 2006.201.08:43:56.69#ibcon#enter sib2, iclass 29, count 2 2006.201.08:43:56.69#ibcon#flushed, iclass 29, count 2 2006.201.08:43:56.69#ibcon#about to write, iclass 29, count 2 2006.201.08:43:56.69#ibcon#wrote, iclass 29, count 2 2006.201.08:43:56.69#ibcon#about to read 3, iclass 29, count 2 2006.201.08:43:56.71#ibcon#read 3, iclass 29, count 2 2006.201.08:43:56.71#ibcon#about to read 4, iclass 29, count 2 2006.201.08:43:56.71#ibcon#read 4, iclass 29, count 2 2006.201.08:43:56.71#ibcon#about to read 5, iclass 29, count 2 2006.201.08:43:56.71#ibcon#read 5, iclass 29, count 2 2006.201.08:43:56.71#ibcon#about to read 6, iclass 29, count 2 2006.201.08:43:56.71#ibcon#read 6, iclass 29, count 2 2006.201.08:43:56.71#ibcon#end of sib2, iclass 29, count 2 2006.201.08:43:56.71#ibcon#*mode == 0, iclass 29, count 2 2006.201.08:43:56.71#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.08:43:56.71#ibcon#[27=AT07-04\r\n] 2006.201.08:43:56.71#ibcon#*before write, iclass 29, count 2 2006.201.08:43:56.71#ibcon#enter sib2, iclass 29, count 2 2006.201.08:43:56.71#ibcon#flushed, iclass 29, count 2 2006.201.08:43:56.71#ibcon#about to write, iclass 29, count 2 2006.201.08:43:56.71#ibcon#wrote, iclass 29, count 2 2006.201.08:43:56.71#ibcon#about to read 3, iclass 29, count 2 2006.201.08:43:56.74#ibcon#read 3, iclass 29, count 2 2006.201.08:43:56.74#ibcon#about to read 4, iclass 29, count 2 2006.201.08:43:56.74#ibcon#read 4, iclass 29, count 2 2006.201.08:43:56.74#ibcon#about to read 5, iclass 29, count 2 2006.201.08:43:56.74#ibcon#read 5, iclass 29, count 2 2006.201.08:43:56.74#ibcon#about to read 6, iclass 29, count 2 2006.201.08:43:56.74#ibcon#read 6, iclass 29, count 2 2006.201.08:43:56.74#ibcon#end of sib2, iclass 29, count 2 2006.201.08:43:56.74#ibcon#*after write, iclass 29, count 2 2006.201.08:43:56.74#ibcon#*before return 0, iclass 29, count 2 2006.201.08:43:56.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:56.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.08:43:56.74#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.08:43:56.74#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:56.74#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:56.86#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:56.86#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:56.86#ibcon#enter wrdev, iclass 29, count 0 2006.201.08:43:56.86#ibcon#first serial, iclass 29, count 0 2006.201.08:43:56.86#ibcon#enter sib2, iclass 29, count 0 2006.201.08:43:56.86#ibcon#flushed, iclass 29, count 0 2006.201.08:43:56.86#ibcon#about to write, iclass 29, count 0 2006.201.08:43:56.86#ibcon#wrote, iclass 29, count 0 2006.201.08:43:56.86#ibcon#about to read 3, iclass 29, count 0 2006.201.08:43:56.88#ibcon#read 3, iclass 29, count 0 2006.201.08:43:56.88#ibcon#about to read 4, iclass 29, count 0 2006.201.08:43:56.88#ibcon#read 4, iclass 29, count 0 2006.201.08:43:56.88#ibcon#about to read 5, iclass 29, count 0 2006.201.08:43:56.88#ibcon#read 5, iclass 29, count 0 2006.201.08:43:56.88#ibcon#about to read 6, iclass 29, count 0 2006.201.08:43:56.88#ibcon#read 6, iclass 29, count 0 2006.201.08:43:56.88#ibcon#end of sib2, iclass 29, count 0 2006.201.08:43:56.88#ibcon#*mode == 0, iclass 29, count 0 2006.201.08:43:56.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.08:43:56.88#ibcon#[27=USB\r\n] 2006.201.08:43:56.88#ibcon#*before write, iclass 29, count 0 2006.201.08:43:56.88#ibcon#enter sib2, iclass 29, count 0 2006.201.08:43:56.88#ibcon#flushed, iclass 29, count 0 2006.201.08:43:56.88#ibcon#about to write, iclass 29, count 0 2006.201.08:43:56.88#ibcon#wrote, iclass 29, count 0 2006.201.08:43:56.88#ibcon#about to read 3, iclass 29, count 0 2006.201.08:43:56.91#ibcon#read 3, iclass 29, count 0 2006.201.08:43:56.91#ibcon#about to read 4, iclass 29, count 0 2006.201.08:43:56.91#ibcon#read 4, iclass 29, count 0 2006.201.08:43:56.91#ibcon#about to read 5, iclass 29, count 0 2006.201.08:43:56.91#ibcon#read 5, iclass 29, count 0 2006.201.08:43:56.91#ibcon#about to read 6, iclass 29, count 0 2006.201.08:43:56.91#ibcon#read 6, iclass 29, count 0 2006.201.08:43:56.91#ibcon#end of sib2, iclass 29, count 0 2006.201.08:43:56.91#ibcon#*after write, iclass 29, count 0 2006.201.08:43:56.91#ibcon#*before return 0, iclass 29, count 0 2006.201.08:43:56.91#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:56.91#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.08:43:56.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.08:43:56.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.08:43:56.91$vck44/vblo=8,744.99 2006.201.08:43:56.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.08:43:56.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.08:43:56.91#ibcon#ireg 17 cls_cnt 0 2006.201.08:43:56.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:56.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:56.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:56.91#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:43:56.91#ibcon#first serial, iclass 31, count 0 2006.201.08:43:56.91#ibcon#enter sib2, iclass 31, count 0 2006.201.08:43:56.91#ibcon#flushed, iclass 31, count 0 2006.201.08:43:56.91#ibcon#about to write, iclass 31, count 0 2006.201.08:43:56.91#ibcon#wrote, iclass 31, count 0 2006.201.08:43:56.91#ibcon#about to read 3, iclass 31, count 0 2006.201.08:43:56.93#ibcon#read 3, iclass 31, count 0 2006.201.08:43:56.93#ibcon#about to read 4, iclass 31, count 0 2006.201.08:43:56.93#ibcon#read 4, iclass 31, count 0 2006.201.08:43:56.93#ibcon#about to read 5, iclass 31, count 0 2006.201.08:43:56.93#ibcon#read 5, iclass 31, count 0 2006.201.08:43:56.93#ibcon#about to read 6, iclass 31, count 0 2006.201.08:43:56.93#ibcon#read 6, iclass 31, count 0 2006.201.08:43:56.93#ibcon#end of sib2, iclass 31, count 0 2006.201.08:43:56.93#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:43:56.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:43:56.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:43:56.93#ibcon#*before write, iclass 31, count 0 2006.201.08:43:56.93#ibcon#enter sib2, iclass 31, count 0 2006.201.08:43:56.93#ibcon#flushed, iclass 31, count 0 2006.201.08:43:56.93#ibcon#about to write, iclass 31, count 0 2006.201.08:43:56.93#ibcon#wrote, iclass 31, count 0 2006.201.08:43:56.93#ibcon#about to read 3, iclass 31, count 0 2006.201.08:43:56.98#ibcon#read 3, iclass 31, count 0 2006.201.08:43:56.98#ibcon#about to read 4, iclass 31, count 0 2006.201.08:43:56.98#ibcon#read 4, iclass 31, count 0 2006.201.08:43:56.98#ibcon#about to read 5, iclass 31, count 0 2006.201.08:43:56.98#ibcon#read 5, iclass 31, count 0 2006.201.08:43:56.98#ibcon#about to read 6, iclass 31, count 0 2006.201.08:43:56.98#ibcon#read 6, iclass 31, count 0 2006.201.08:43:56.98#ibcon#end of sib2, iclass 31, count 0 2006.201.08:43:56.98#ibcon#*after write, iclass 31, count 0 2006.201.08:43:56.98#ibcon#*before return 0, iclass 31, count 0 2006.201.08:43:56.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:56.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.08:43:56.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:43:56.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:43:56.98$vck44/vb=8,4 2006.201.08:43:56.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.08:43:56.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.08:43:56.98#ibcon#ireg 11 cls_cnt 2 2006.201.08:43:56.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:57.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:57.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:57.03#ibcon#enter wrdev, iclass 33, count 2 2006.201.08:43:57.03#ibcon#first serial, iclass 33, count 2 2006.201.08:43:57.03#ibcon#enter sib2, iclass 33, count 2 2006.201.08:43:57.03#ibcon#flushed, iclass 33, count 2 2006.201.08:43:57.03#ibcon#about to write, iclass 33, count 2 2006.201.08:43:57.03#ibcon#wrote, iclass 33, count 2 2006.201.08:43:57.03#ibcon#about to read 3, iclass 33, count 2 2006.201.08:43:57.05#ibcon#read 3, iclass 33, count 2 2006.201.08:43:57.05#ibcon#about to read 4, iclass 33, count 2 2006.201.08:43:57.05#ibcon#read 4, iclass 33, count 2 2006.201.08:43:57.05#ibcon#about to read 5, iclass 33, count 2 2006.201.08:43:57.05#ibcon#read 5, iclass 33, count 2 2006.201.08:43:57.05#ibcon#about to read 6, iclass 33, count 2 2006.201.08:43:57.05#ibcon#read 6, iclass 33, count 2 2006.201.08:43:57.05#ibcon#end of sib2, iclass 33, count 2 2006.201.08:43:57.05#ibcon#*mode == 0, iclass 33, count 2 2006.201.08:43:57.05#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.08:43:57.05#ibcon#[27=AT08-04\r\n] 2006.201.08:43:57.05#ibcon#*before write, iclass 33, count 2 2006.201.08:43:57.05#ibcon#enter sib2, iclass 33, count 2 2006.201.08:43:57.05#ibcon#flushed, iclass 33, count 2 2006.201.08:43:57.05#ibcon#about to write, iclass 33, count 2 2006.201.08:43:57.05#ibcon#wrote, iclass 33, count 2 2006.201.08:43:57.05#ibcon#about to read 3, iclass 33, count 2 2006.201.08:43:57.08#ibcon#read 3, iclass 33, count 2 2006.201.08:43:57.08#ibcon#about to read 4, iclass 33, count 2 2006.201.08:43:57.08#ibcon#read 4, iclass 33, count 2 2006.201.08:43:57.08#ibcon#about to read 5, iclass 33, count 2 2006.201.08:43:57.08#ibcon#read 5, iclass 33, count 2 2006.201.08:43:57.08#ibcon#about to read 6, iclass 33, count 2 2006.201.08:43:57.08#ibcon#read 6, iclass 33, count 2 2006.201.08:43:57.08#ibcon#end of sib2, iclass 33, count 2 2006.201.08:43:57.08#ibcon#*after write, iclass 33, count 2 2006.201.08:43:57.08#ibcon#*before return 0, iclass 33, count 2 2006.201.08:43:57.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:57.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.08:43:57.08#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.08:43:57.08#ibcon#ireg 7 cls_cnt 0 2006.201.08:43:57.08#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:57.20#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:57.20#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:57.20#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:43:57.20#ibcon#first serial, iclass 33, count 0 2006.201.08:43:57.20#ibcon#enter sib2, iclass 33, count 0 2006.201.08:43:57.20#ibcon#flushed, iclass 33, count 0 2006.201.08:43:57.20#ibcon#about to write, iclass 33, count 0 2006.201.08:43:57.20#ibcon#wrote, iclass 33, count 0 2006.201.08:43:57.20#ibcon#about to read 3, iclass 33, count 0 2006.201.08:43:57.23#ibcon#read 3, iclass 33, count 0 2006.201.08:43:57.23#ibcon#about to read 4, iclass 33, count 0 2006.201.08:43:57.23#ibcon#read 4, iclass 33, count 0 2006.201.08:43:57.23#ibcon#about to read 5, iclass 33, count 0 2006.201.08:43:57.23#ibcon#read 5, iclass 33, count 0 2006.201.08:43:57.23#ibcon#about to read 6, iclass 33, count 0 2006.201.08:43:57.23#ibcon#read 6, iclass 33, count 0 2006.201.08:43:57.23#ibcon#end of sib2, iclass 33, count 0 2006.201.08:43:57.23#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:43:57.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:43:57.23#ibcon#[27=USB\r\n] 2006.201.08:43:57.23#ibcon#*before write, iclass 33, count 0 2006.201.08:43:57.23#ibcon#enter sib2, iclass 33, count 0 2006.201.08:43:57.23#ibcon#flushed, iclass 33, count 0 2006.201.08:43:57.23#ibcon#about to write, iclass 33, count 0 2006.201.08:43:57.23#ibcon#wrote, iclass 33, count 0 2006.201.08:43:57.23#ibcon#about to read 3, iclass 33, count 0 2006.201.08:43:57.26#ibcon#read 3, iclass 33, count 0 2006.201.08:43:57.26#ibcon#about to read 4, iclass 33, count 0 2006.201.08:43:57.26#ibcon#read 4, iclass 33, count 0 2006.201.08:43:57.26#ibcon#about to read 5, iclass 33, count 0 2006.201.08:43:57.26#ibcon#read 5, iclass 33, count 0 2006.201.08:43:57.26#ibcon#about to read 6, iclass 33, count 0 2006.201.08:43:57.26#ibcon#read 6, iclass 33, count 0 2006.201.08:43:57.26#ibcon#end of sib2, iclass 33, count 0 2006.201.08:43:57.26#ibcon#*after write, iclass 33, count 0 2006.201.08:43:57.26#ibcon#*before return 0, iclass 33, count 0 2006.201.08:43:57.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:57.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.08:43:57.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:43:57.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:43:57.26$vck44/vabw=wide 2006.201.08:43:57.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.08:43:57.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.08:43:57.26#ibcon#ireg 8 cls_cnt 0 2006.201.08:43:57.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:57.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:57.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:57.26#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:43:57.26#ibcon#first serial, iclass 35, count 0 2006.201.08:43:57.26#ibcon#enter sib2, iclass 35, count 0 2006.201.08:43:57.26#ibcon#flushed, iclass 35, count 0 2006.201.08:43:57.26#ibcon#about to write, iclass 35, count 0 2006.201.08:43:57.26#ibcon#wrote, iclass 35, count 0 2006.201.08:43:57.26#ibcon#about to read 3, iclass 35, count 0 2006.201.08:43:57.28#ibcon#read 3, iclass 35, count 0 2006.201.08:43:57.28#ibcon#about to read 4, iclass 35, count 0 2006.201.08:43:57.28#ibcon#read 4, iclass 35, count 0 2006.201.08:43:57.28#ibcon#about to read 5, iclass 35, count 0 2006.201.08:43:57.28#ibcon#read 5, iclass 35, count 0 2006.201.08:43:57.28#ibcon#about to read 6, iclass 35, count 0 2006.201.08:43:57.28#ibcon#read 6, iclass 35, count 0 2006.201.08:43:57.28#ibcon#end of sib2, iclass 35, count 0 2006.201.08:43:57.28#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:43:57.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:43:57.28#ibcon#[25=BW32\r\n] 2006.201.08:43:57.28#ibcon#*before write, iclass 35, count 0 2006.201.08:43:57.28#ibcon#enter sib2, iclass 35, count 0 2006.201.08:43:57.28#ibcon#flushed, iclass 35, count 0 2006.201.08:43:57.28#ibcon#about to write, iclass 35, count 0 2006.201.08:43:57.28#ibcon#wrote, iclass 35, count 0 2006.201.08:43:57.28#ibcon#about to read 3, iclass 35, count 0 2006.201.08:43:57.31#ibcon#read 3, iclass 35, count 0 2006.201.08:43:57.31#ibcon#about to read 4, iclass 35, count 0 2006.201.08:43:57.31#ibcon#read 4, iclass 35, count 0 2006.201.08:43:57.31#ibcon#about to read 5, iclass 35, count 0 2006.201.08:43:57.31#ibcon#read 5, iclass 35, count 0 2006.201.08:43:57.31#ibcon#about to read 6, iclass 35, count 0 2006.201.08:43:57.31#ibcon#read 6, iclass 35, count 0 2006.201.08:43:57.31#ibcon#end of sib2, iclass 35, count 0 2006.201.08:43:57.31#ibcon#*after write, iclass 35, count 0 2006.201.08:43:57.31#ibcon#*before return 0, iclass 35, count 0 2006.201.08:43:57.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:57.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.08:43:57.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:43:57.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:43:57.31$vck44/vbbw=wide 2006.201.08:43:57.31#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.08:43:57.31#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.08:43:57.31#ibcon#ireg 8 cls_cnt 0 2006.201.08:43:57.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:43:57.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:43:57.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:43:57.38#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:43:57.38#ibcon#first serial, iclass 37, count 0 2006.201.08:43:57.38#ibcon#enter sib2, iclass 37, count 0 2006.201.08:43:57.38#ibcon#flushed, iclass 37, count 0 2006.201.08:43:57.38#ibcon#about to write, iclass 37, count 0 2006.201.08:43:57.38#ibcon#wrote, iclass 37, count 0 2006.201.08:43:57.38#ibcon#about to read 3, iclass 37, count 0 2006.201.08:43:57.40#ibcon#read 3, iclass 37, count 0 2006.201.08:43:57.40#ibcon#about to read 4, iclass 37, count 0 2006.201.08:43:57.40#ibcon#read 4, iclass 37, count 0 2006.201.08:43:57.40#ibcon#about to read 5, iclass 37, count 0 2006.201.08:43:57.40#ibcon#read 5, iclass 37, count 0 2006.201.08:43:57.40#ibcon#about to read 6, iclass 37, count 0 2006.201.08:43:57.40#ibcon#read 6, iclass 37, count 0 2006.201.08:43:57.40#ibcon#end of sib2, iclass 37, count 0 2006.201.08:43:57.40#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:43:57.40#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:43:57.40#ibcon#[27=BW32\r\n] 2006.201.08:43:57.40#ibcon#*before write, iclass 37, count 0 2006.201.08:43:57.40#ibcon#enter sib2, iclass 37, count 0 2006.201.08:43:57.40#ibcon#flushed, iclass 37, count 0 2006.201.08:43:57.40#ibcon#about to write, iclass 37, count 0 2006.201.08:43:57.40#ibcon#wrote, iclass 37, count 0 2006.201.08:43:57.40#ibcon#about to read 3, iclass 37, count 0 2006.201.08:43:57.43#ibcon#read 3, iclass 37, count 0 2006.201.08:43:57.43#ibcon#about to read 4, iclass 37, count 0 2006.201.08:43:57.43#ibcon#read 4, iclass 37, count 0 2006.201.08:43:57.43#ibcon#about to read 5, iclass 37, count 0 2006.201.08:43:57.43#ibcon#read 5, iclass 37, count 0 2006.201.08:43:57.43#ibcon#about to read 6, iclass 37, count 0 2006.201.08:43:57.43#ibcon#read 6, iclass 37, count 0 2006.201.08:43:57.43#ibcon#end of sib2, iclass 37, count 0 2006.201.08:43:57.43#ibcon#*after write, iclass 37, count 0 2006.201.08:43:57.43#ibcon#*before return 0, iclass 37, count 0 2006.201.08:43:57.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:43:57.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:43:57.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:43:57.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:43:57.43$setupk4/ifdk4 2006.201.08:43:57.43$ifdk4/lo= 2006.201.08:43:57.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:43:57.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:43:57.43$ifdk4/patch= 2006.201.08:43:57.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:43:57.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:43:57.43$setupk4/!*+20s 2006.201.08:44:08.13#trakl#Source acquired 2006.201.08:44:08.13#flagr#flagr/antenna,acquired 2006.201.08:44:11.88$setupk4/"tpicd 2006.201.08:44:11.88$setupk4/echo=off 2006.201.08:44:11.88$setupk4/xlog=off 2006.201.08:44:11.88:!2006.201.08:44:29 2006.201.08:44:29.00:preob 2006.201.08:44:30.13/onsource/TRACKING 2006.201.08:44:30.13:!2006.201.08:44:39 2006.201.08:44:39.00:"tape 2006.201.08:44:39.00:"st=record 2006.201.08:44:39.00:data_valid=on 2006.201.08:44:39.00:midob 2006.201.08:44:39.13/onsource/TRACKING 2006.201.08:44:39.13/wx/23.06,1003.6,89 2006.201.08:44:39.27/cable/+6.4663E-03 2006.201.08:44:40.36/va/01,08,usb,yes,28,30 2006.201.08:44:40.36/va/02,07,usb,yes,30,31 2006.201.08:44:40.36/va/03,08,usb,yes,27,28 2006.201.08:44:40.36/va/04,07,usb,yes,31,33 2006.201.08:44:40.36/va/05,04,usb,yes,27,28 2006.201.08:44:40.36/va/06,05,usb,yes,27,27 2006.201.08:44:40.36/va/07,05,usb,yes,27,28 2006.201.08:44:40.36/va/08,04,usb,yes,26,32 2006.201.08:44:40.59/valo/01,524.99,yes,locked 2006.201.08:44:40.59/valo/02,534.99,yes,locked 2006.201.08:44:40.59/valo/03,564.99,yes,locked 2006.201.08:44:40.59/valo/04,624.99,yes,locked 2006.201.08:44:40.59/valo/05,734.99,yes,locked 2006.201.08:44:40.59/valo/06,814.99,yes,locked 2006.201.08:44:40.59/valo/07,864.99,yes,locked 2006.201.08:44:40.59/valo/08,884.99,yes,locked 2006.201.08:44:41.68/vb/01,04,usb,yes,28,26 2006.201.08:44:41.68/vb/02,05,usb,yes,27,26 2006.201.08:44:41.68/vb/03,04,usb,yes,27,30 2006.201.08:44:41.68/vb/04,05,usb,yes,28,27 2006.201.08:44:41.68/vb/05,04,usb,yes,24,27 2006.201.08:44:41.68/vb/06,04,usb,yes,28,25 2006.201.08:44:41.68/vb/07,04,usb,yes,28,28 2006.201.08:44:41.68/vb/08,04,usb,yes,26,29 2006.201.08:44:41.91/vblo/01,629.99,yes,locked 2006.201.08:44:41.91/vblo/02,634.99,yes,locked 2006.201.08:44:41.91/vblo/03,649.99,yes,locked 2006.201.08:44:41.91/vblo/04,679.99,yes,locked 2006.201.08:44:41.91/vblo/05,709.99,yes,locked 2006.201.08:44:41.91/vblo/06,719.99,yes,locked 2006.201.08:44:41.91/vblo/07,734.99,yes,locked 2006.201.08:44:41.91/vblo/08,744.99,yes,locked 2006.201.08:44:42.06/vabw/8 2006.201.08:44:42.21/vbbw/8 2006.201.08:44:42.30/xfe/off,on,15.0 2006.201.08:44:42.68/ifatt/23,28,28,28 2006.201.08:44:43.05/fmout-gps/S +4.56E-07 2006.201.08:44:43.12:!2006.201.08:49:19 2006.201.08:49:19.00:data_valid=off 2006.201.08:49:19.00:"et 2006.201.08:49:19.00:!+3s 2006.201.08:49:22.02:"tape 2006.201.08:49:22.02:postob 2006.201.08:49:22.21/cable/+6.4666E-03 2006.201.08:49:22.21/wx/23.02,1003.7,89 2006.201.08:49:22.28/fmout-gps/S +4.55E-07 2006.201.08:49:22.28:scan_name=201-0850,jd0607,400 2006.201.08:49:22.28:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.201.08:49:24.14#flagr#flagr/antenna,new-source 2006.201.08:49:24.14:checkk5 2006.201.08:49:24.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:49:24.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:49:25.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:49:25.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:49:26.02/chk_obsdata//k5ts1/T2010844??a.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.201.08:49:26.39/chk_obsdata//k5ts2/T2010844??b.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.201.08:49:26.75/chk_obsdata//k5ts3/T2010844??c.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.201.08:49:27.13/chk_obsdata//k5ts4/T2010844??d.dat file size is correct (nominal:1120MB, actual:1116MB). 2006.201.08:49:27.81/k5log//k5ts1_log_newline 2006.201.08:49:28.51/k5log//k5ts2_log_newline 2006.201.08:49:29.20/k5log//k5ts3_log_newline 2006.201.08:49:29.88/k5log//k5ts4_log_newline 2006.201.08:49:29.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:49:29.91:setupk4=1 2006.201.08:49:29.91$setupk4/echo=on 2006.201.08:49:29.91$setupk4/pcalon 2006.201.08:49:29.91$pcalon/"no phase cal control is implemented here 2006.201.08:49:29.91$setupk4/"tpicd=stop 2006.201.08:49:29.91$setupk4/"rec=synch_on 2006.201.08:49:29.91$setupk4/"rec_mode=128 2006.201.08:49:29.91$setupk4/!* 2006.201.08:49:29.91$setupk4/recpk4 2006.201.08:49:29.91$recpk4/recpatch= 2006.201.08:49:29.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:49:29.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:49:29.91$setupk4/vck44 2006.201.08:49:29.91$vck44/valo=1,524.99 2006.201.08:49:29.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.08:49:29.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.08:49:29.91#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:29.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:29.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:29.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:29.91#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:49:29.91#ibcon#first serial, iclass 21, count 0 2006.201.08:49:29.91#ibcon#enter sib2, iclass 21, count 0 2006.201.08:49:29.91#ibcon#flushed, iclass 21, count 0 2006.201.08:49:29.91#ibcon#about to write, iclass 21, count 0 2006.201.08:49:29.91#ibcon#wrote, iclass 21, count 0 2006.201.08:49:29.91#ibcon#about to read 3, iclass 21, count 0 2006.201.08:49:29.95#ibcon#read 3, iclass 21, count 0 2006.201.08:49:29.95#ibcon#about to read 4, iclass 21, count 0 2006.201.08:49:29.95#ibcon#read 4, iclass 21, count 0 2006.201.08:49:29.95#ibcon#about to read 5, iclass 21, count 0 2006.201.08:49:29.95#ibcon#read 5, iclass 21, count 0 2006.201.08:49:29.95#ibcon#about to read 6, iclass 21, count 0 2006.201.08:49:29.95#ibcon#read 6, iclass 21, count 0 2006.201.08:49:29.95#ibcon#end of sib2, iclass 21, count 0 2006.201.08:49:29.95#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:49:29.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:49:29.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:49:29.95#ibcon#*before write, iclass 21, count 0 2006.201.08:49:29.95#ibcon#enter sib2, iclass 21, count 0 2006.201.08:49:29.95#ibcon#flushed, iclass 21, count 0 2006.201.08:49:29.95#ibcon#about to write, iclass 21, count 0 2006.201.08:49:29.95#ibcon#wrote, iclass 21, count 0 2006.201.08:49:29.95#ibcon#about to read 3, iclass 21, count 0 2006.201.08:49:30.00#ibcon#read 3, iclass 21, count 0 2006.201.08:49:30.00#ibcon#about to read 4, iclass 21, count 0 2006.201.08:49:30.00#ibcon#read 4, iclass 21, count 0 2006.201.08:49:30.00#ibcon#about to read 5, iclass 21, count 0 2006.201.08:49:30.00#ibcon#read 5, iclass 21, count 0 2006.201.08:49:30.00#ibcon#about to read 6, iclass 21, count 0 2006.201.08:49:30.00#ibcon#read 6, iclass 21, count 0 2006.201.08:49:30.00#ibcon#end of sib2, iclass 21, count 0 2006.201.08:49:30.00#ibcon#*after write, iclass 21, count 0 2006.201.08:49:30.00#ibcon#*before return 0, iclass 21, count 0 2006.201.08:49:30.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:30.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:30.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:49:30.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:49:30.00$vck44/va=1,8 2006.201.08:49:30.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.08:49:30.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.08:49:30.00#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:30.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:30.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:30.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:30.00#ibcon#enter wrdev, iclass 23, count 2 2006.201.08:49:30.00#ibcon#first serial, iclass 23, count 2 2006.201.08:49:30.00#ibcon#enter sib2, iclass 23, count 2 2006.201.08:49:30.00#ibcon#flushed, iclass 23, count 2 2006.201.08:49:30.00#ibcon#about to write, iclass 23, count 2 2006.201.08:49:30.00#ibcon#wrote, iclass 23, count 2 2006.201.08:49:30.00#ibcon#about to read 3, iclass 23, count 2 2006.201.08:49:30.02#ibcon#read 3, iclass 23, count 2 2006.201.08:49:30.02#ibcon#about to read 4, iclass 23, count 2 2006.201.08:49:30.02#ibcon#read 4, iclass 23, count 2 2006.201.08:49:30.02#ibcon#about to read 5, iclass 23, count 2 2006.201.08:49:30.02#ibcon#read 5, iclass 23, count 2 2006.201.08:49:30.02#ibcon#about to read 6, iclass 23, count 2 2006.201.08:49:30.02#ibcon#read 6, iclass 23, count 2 2006.201.08:49:30.02#ibcon#end of sib2, iclass 23, count 2 2006.201.08:49:30.02#ibcon#*mode == 0, iclass 23, count 2 2006.201.08:49:30.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.08:49:30.02#ibcon#[25=AT01-08\r\n] 2006.201.08:49:30.02#ibcon#*before write, iclass 23, count 2 2006.201.08:49:30.02#ibcon#enter sib2, iclass 23, count 2 2006.201.08:49:30.02#ibcon#flushed, iclass 23, count 2 2006.201.08:49:30.02#ibcon#about to write, iclass 23, count 2 2006.201.08:49:30.02#ibcon#wrote, iclass 23, count 2 2006.201.08:49:30.02#ibcon#about to read 3, iclass 23, count 2 2006.201.08:49:30.05#ibcon#read 3, iclass 23, count 2 2006.201.08:49:30.05#ibcon#about to read 4, iclass 23, count 2 2006.201.08:49:30.05#ibcon#read 4, iclass 23, count 2 2006.201.08:49:30.05#ibcon#about to read 5, iclass 23, count 2 2006.201.08:49:30.05#ibcon#read 5, iclass 23, count 2 2006.201.08:49:30.05#ibcon#about to read 6, iclass 23, count 2 2006.201.08:49:30.05#ibcon#read 6, iclass 23, count 2 2006.201.08:49:30.05#ibcon#end of sib2, iclass 23, count 2 2006.201.08:49:30.05#ibcon#*after write, iclass 23, count 2 2006.201.08:49:30.05#ibcon#*before return 0, iclass 23, count 2 2006.201.08:49:30.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:30.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:30.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.08:49:30.05#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:30.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:30.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:30.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:30.17#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:49:30.17#ibcon#first serial, iclass 23, count 0 2006.201.08:49:30.17#ibcon#enter sib2, iclass 23, count 0 2006.201.08:49:30.17#ibcon#flushed, iclass 23, count 0 2006.201.08:49:30.17#ibcon#about to write, iclass 23, count 0 2006.201.08:49:30.17#ibcon#wrote, iclass 23, count 0 2006.201.08:49:30.17#ibcon#about to read 3, iclass 23, count 0 2006.201.08:49:30.19#ibcon#read 3, iclass 23, count 0 2006.201.08:49:30.19#ibcon#about to read 4, iclass 23, count 0 2006.201.08:49:30.19#ibcon#read 4, iclass 23, count 0 2006.201.08:49:30.19#ibcon#about to read 5, iclass 23, count 0 2006.201.08:49:30.19#ibcon#read 5, iclass 23, count 0 2006.201.08:49:30.19#ibcon#about to read 6, iclass 23, count 0 2006.201.08:49:30.19#ibcon#read 6, iclass 23, count 0 2006.201.08:49:30.19#ibcon#end of sib2, iclass 23, count 0 2006.201.08:49:30.19#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:49:30.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:49:30.19#ibcon#[25=USB\r\n] 2006.201.08:49:30.19#ibcon#*before write, iclass 23, count 0 2006.201.08:49:30.19#ibcon#enter sib2, iclass 23, count 0 2006.201.08:49:30.19#ibcon#flushed, iclass 23, count 0 2006.201.08:49:30.19#ibcon#about to write, iclass 23, count 0 2006.201.08:49:30.19#ibcon#wrote, iclass 23, count 0 2006.201.08:49:30.19#ibcon#about to read 3, iclass 23, count 0 2006.201.08:49:30.22#ibcon#read 3, iclass 23, count 0 2006.201.08:49:30.22#ibcon#about to read 4, iclass 23, count 0 2006.201.08:49:30.22#ibcon#read 4, iclass 23, count 0 2006.201.08:49:30.22#ibcon#about to read 5, iclass 23, count 0 2006.201.08:49:30.22#ibcon#read 5, iclass 23, count 0 2006.201.08:49:30.22#ibcon#about to read 6, iclass 23, count 0 2006.201.08:49:30.22#ibcon#read 6, iclass 23, count 0 2006.201.08:49:30.22#ibcon#end of sib2, iclass 23, count 0 2006.201.08:49:30.22#ibcon#*after write, iclass 23, count 0 2006.201.08:49:30.22#ibcon#*before return 0, iclass 23, count 0 2006.201.08:49:30.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:30.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:30.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:49:30.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:49:30.22$vck44/valo=2,534.99 2006.201.08:49:30.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.08:49:30.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.08:49:30.22#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:30.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:49:30.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:49:30.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:49:30.22#ibcon#enter wrdev, iclass 25, count 0 2006.201.08:49:30.22#ibcon#first serial, iclass 25, count 0 2006.201.08:49:30.22#ibcon#enter sib2, iclass 25, count 0 2006.201.08:49:30.22#ibcon#flushed, iclass 25, count 0 2006.201.08:49:30.22#ibcon#about to write, iclass 25, count 0 2006.201.08:49:30.22#ibcon#wrote, iclass 25, count 0 2006.201.08:49:30.22#ibcon#about to read 3, iclass 25, count 0 2006.201.08:49:30.24#ibcon#read 3, iclass 25, count 0 2006.201.08:49:30.24#ibcon#about to read 4, iclass 25, count 0 2006.201.08:49:30.24#ibcon#read 4, iclass 25, count 0 2006.201.08:49:30.24#ibcon#about to read 5, iclass 25, count 0 2006.201.08:49:30.24#ibcon#read 5, iclass 25, count 0 2006.201.08:49:30.24#ibcon#about to read 6, iclass 25, count 0 2006.201.08:49:30.24#ibcon#read 6, iclass 25, count 0 2006.201.08:49:30.24#ibcon#end of sib2, iclass 25, count 0 2006.201.08:49:30.24#ibcon#*mode == 0, iclass 25, count 0 2006.201.08:49:30.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.08:49:30.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:49:30.24#ibcon#*before write, iclass 25, count 0 2006.201.08:49:30.24#ibcon#enter sib2, iclass 25, count 0 2006.201.08:49:30.24#ibcon#flushed, iclass 25, count 0 2006.201.08:49:30.24#ibcon#about to write, iclass 25, count 0 2006.201.08:49:30.24#ibcon#wrote, iclass 25, count 0 2006.201.08:49:30.24#ibcon#about to read 3, iclass 25, count 0 2006.201.08:49:30.28#ibcon#read 3, iclass 25, count 0 2006.201.08:49:30.28#ibcon#about to read 4, iclass 25, count 0 2006.201.08:49:30.28#ibcon#read 4, iclass 25, count 0 2006.201.08:49:30.28#ibcon#about to read 5, iclass 25, count 0 2006.201.08:49:30.28#ibcon#read 5, iclass 25, count 0 2006.201.08:49:30.28#ibcon#about to read 6, iclass 25, count 0 2006.201.08:49:30.28#ibcon#read 6, iclass 25, count 0 2006.201.08:49:30.28#ibcon#end of sib2, iclass 25, count 0 2006.201.08:49:30.28#ibcon#*after write, iclass 25, count 0 2006.201.08:49:30.28#ibcon#*before return 0, iclass 25, count 0 2006.201.08:49:30.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:49:30.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.08:49:30.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.08:49:30.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.08:49:30.28$vck44/va=2,7 2006.201.08:49:30.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.08:49:30.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.08:49:30.28#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:30.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:49:30.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:49:30.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:49:30.34#ibcon#enter wrdev, iclass 27, count 2 2006.201.08:49:30.34#ibcon#first serial, iclass 27, count 2 2006.201.08:49:30.34#ibcon#enter sib2, iclass 27, count 2 2006.201.08:49:30.34#ibcon#flushed, iclass 27, count 2 2006.201.08:49:30.34#ibcon#about to write, iclass 27, count 2 2006.201.08:49:30.34#ibcon#wrote, iclass 27, count 2 2006.201.08:49:30.34#ibcon#about to read 3, iclass 27, count 2 2006.201.08:49:30.36#ibcon#read 3, iclass 27, count 2 2006.201.08:49:30.36#ibcon#about to read 4, iclass 27, count 2 2006.201.08:49:30.36#ibcon#read 4, iclass 27, count 2 2006.201.08:49:30.36#ibcon#about to read 5, iclass 27, count 2 2006.201.08:49:30.36#ibcon#read 5, iclass 27, count 2 2006.201.08:49:30.36#ibcon#about to read 6, iclass 27, count 2 2006.201.08:49:30.36#ibcon#read 6, iclass 27, count 2 2006.201.08:49:30.36#ibcon#end of sib2, iclass 27, count 2 2006.201.08:49:30.36#ibcon#*mode == 0, iclass 27, count 2 2006.201.08:49:30.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.08:49:30.36#ibcon#[25=AT02-07\r\n] 2006.201.08:49:30.36#ibcon#*before write, iclass 27, count 2 2006.201.08:49:30.36#ibcon#enter sib2, iclass 27, count 2 2006.201.08:49:30.36#ibcon#flushed, iclass 27, count 2 2006.201.08:49:30.36#ibcon#about to write, iclass 27, count 2 2006.201.08:49:30.36#ibcon#wrote, iclass 27, count 2 2006.201.08:49:30.36#ibcon#about to read 3, iclass 27, count 2 2006.201.08:49:30.39#ibcon#read 3, iclass 27, count 2 2006.201.08:49:30.39#ibcon#about to read 4, iclass 27, count 2 2006.201.08:49:30.39#ibcon#read 4, iclass 27, count 2 2006.201.08:49:30.39#ibcon#about to read 5, iclass 27, count 2 2006.201.08:49:30.39#ibcon#read 5, iclass 27, count 2 2006.201.08:49:30.39#ibcon#about to read 6, iclass 27, count 2 2006.201.08:49:30.39#ibcon#read 6, iclass 27, count 2 2006.201.08:49:30.39#ibcon#end of sib2, iclass 27, count 2 2006.201.08:49:30.39#ibcon#*after write, iclass 27, count 2 2006.201.08:49:30.39#ibcon#*before return 0, iclass 27, count 2 2006.201.08:49:30.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:49:30.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.08:49:30.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.08:49:30.39#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:30.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:49:30.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:49:30.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:49:30.51#ibcon#enter wrdev, iclass 27, count 0 2006.201.08:49:30.51#ibcon#first serial, iclass 27, count 0 2006.201.08:49:30.51#ibcon#enter sib2, iclass 27, count 0 2006.201.08:49:30.51#ibcon#flushed, iclass 27, count 0 2006.201.08:49:30.51#ibcon#about to write, iclass 27, count 0 2006.201.08:49:30.51#ibcon#wrote, iclass 27, count 0 2006.201.08:49:30.51#ibcon#about to read 3, iclass 27, count 0 2006.201.08:49:30.53#ibcon#read 3, iclass 27, count 0 2006.201.08:49:30.53#ibcon#about to read 4, iclass 27, count 0 2006.201.08:49:30.53#ibcon#read 4, iclass 27, count 0 2006.201.08:49:30.53#ibcon#about to read 5, iclass 27, count 0 2006.201.08:49:30.53#ibcon#read 5, iclass 27, count 0 2006.201.08:49:30.53#ibcon#about to read 6, iclass 27, count 0 2006.201.08:49:30.53#ibcon#read 6, iclass 27, count 0 2006.201.08:49:30.53#ibcon#end of sib2, iclass 27, count 0 2006.201.08:49:30.53#ibcon#*mode == 0, iclass 27, count 0 2006.201.08:49:30.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.08:49:30.53#ibcon#[25=USB\r\n] 2006.201.08:49:30.53#ibcon#*before write, iclass 27, count 0 2006.201.08:49:30.53#ibcon#enter sib2, iclass 27, count 0 2006.201.08:49:30.53#ibcon#flushed, iclass 27, count 0 2006.201.08:49:30.53#ibcon#about to write, iclass 27, count 0 2006.201.08:49:30.53#ibcon#wrote, iclass 27, count 0 2006.201.08:49:30.53#ibcon#about to read 3, iclass 27, count 0 2006.201.08:49:30.56#ibcon#read 3, iclass 27, count 0 2006.201.08:49:30.56#ibcon#about to read 4, iclass 27, count 0 2006.201.08:49:30.56#ibcon#read 4, iclass 27, count 0 2006.201.08:49:30.56#ibcon#about to read 5, iclass 27, count 0 2006.201.08:49:30.56#ibcon#read 5, iclass 27, count 0 2006.201.08:49:30.56#ibcon#about to read 6, iclass 27, count 0 2006.201.08:49:30.56#ibcon#read 6, iclass 27, count 0 2006.201.08:49:30.56#ibcon#end of sib2, iclass 27, count 0 2006.201.08:49:30.56#ibcon#*after write, iclass 27, count 0 2006.201.08:49:30.56#ibcon#*before return 0, iclass 27, count 0 2006.201.08:49:30.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:49:30.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.08:49:30.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.08:49:30.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.08:49:30.56$vck44/valo=3,564.99 2006.201.08:49:30.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.08:49:30.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.08:49:30.56#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:30.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:49:30.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:49:30.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:49:30.56#ibcon#enter wrdev, iclass 29, count 0 2006.201.08:49:30.56#ibcon#first serial, iclass 29, count 0 2006.201.08:49:30.56#ibcon#enter sib2, iclass 29, count 0 2006.201.08:49:30.56#ibcon#flushed, iclass 29, count 0 2006.201.08:49:30.56#ibcon#about to write, iclass 29, count 0 2006.201.08:49:30.56#ibcon#wrote, iclass 29, count 0 2006.201.08:49:30.56#ibcon#about to read 3, iclass 29, count 0 2006.201.08:49:30.58#ibcon#read 3, iclass 29, count 0 2006.201.08:49:30.58#ibcon#about to read 4, iclass 29, count 0 2006.201.08:49:30.58#ibcon#read 4, iclass 29, count 0 2006.201.08:49:30.58#ibcon#about to read 5, iclass 29, count 0 2006.201.08:49:30.58#ibcon#read 5, iclass 29, count 0 2006.201.08:49:30.58#ibcon#about to read 6, iclass 29, count 0 2006.201.08:49:30.58#ibcon#read 6, iclass 29, count 0 2006.201.08:49:30.58#ibcon#end of sib2, iclass 29, count 0 2006.201.08:49:30.58#ibcon#*mode == 0, iclass 29, count 0 2006.201.08:49:30.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.08:49:30.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:49:30.58#ibcon#*before write, iclass 29, count 0 2006.201.08:49:30.58#ibcon#enter sib2, iclass 29, count 0 2006.201.08:49:30.58#ibcon#flushed, iclass 29, count 0 2006.201.08:49:30.58#ibcon#about to write, iclass 29, count 0 2006.201.08:49:30.58#ibcon#wrote, iclass 29, count 0 2006.201.08:49:30.58#ibcon#about to read 3, iclass 29, count 0 2006.201.08:49:30.63#ibcon#read 3, iclass 29, count 0 2006.201.08:49:30.63#ibcon#about to read 4, iclass 29, count 0 2006.201.08:49:30.63#ibcon#read 4, iclass 29, count 0 2006.201.08:49:30.63#ibcon#about to read 5, iclass 29, count 0 2006.201.08:49:30.63#ibcon#read 5, iclass 29, count 0 2006.201.08:49:30.63#ibcon#about to read 6, iclass 29, count 0 2006.201.08:49:30.63#ibcon#read 6, iclass 29, count 0 2006.201.08:49:30.63#ibcon#end of sib2, iclass 29, count 0 2006.201.08:49:30.63#ibcon#*after write, iclass 29, count 0 2006.201.08:49:30.63#ibcon#*before return 0, iclass 29, count 0 2006.201.08:49:30.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:49:30.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.08:49:30.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.08:49:30.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.08:49:30.63$vck44/va=3,8 2006.201.08:49:30.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.08:49:30.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.08:49:30.63#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:30.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:30.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:30.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:30.68#ibcon#enter wrdev, iclass 31, count 2 2006.201.08:49:30.68#ibcon#first serial, iclass 31, count 2 2006.201.08:49:30.68#ibcon#enter sib2, iclass 31, count 2 2006.201.08:49:30.68#ibcon#flushed, iclass 31, count 2 2006.201.08:49:30.68#ibcon#about to write, iclass 31, count 2 2006.201.08:49:30.68#ibcon#wrote, iclass 31, count 2 2006.201.08:49:30.68#ibcon#about to read 3, iclass 31, count 2 2006.201.08:49:30.70#ibcon#read 3, iclass 31, count 2 2006.201.08:49:30.70#ibcon#about to read 4, iclass 31, count 2 2006.201.08:49:30.70#ibcon#read 4, iclass 31, count 2 2006.201.08:49:30.70#ibcon#about to read 5, iclass 31, count 2 2006.201.08:49:30.70#ibcon#read 5, iclass 31, count 2 2006.201.08:49:30.70#ibcon#about to read 6, iclass 31, count 2 2006.201.08:49:30.70#ibcon#read 6, iclass 31, count 2 2006.201.08:49:30.70#ibcon#end of sib2, iclass 31, count 2 2006.201.08:49:30.70#ibcon#*mode == 0, iclass 31, count 2 2006.201.08:49:30.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.08:49:30.70#ibcon#[25=AT03-08\r\n] 2006.201.08:49:30.70#ibcon#*before write, iclass 31, count 2 2006.201.08:49:30.70#ibcon#enter sib2, iclass 31, count 2 2006.201.08:49:30.70#ibcon#flushed, iclass 31, count 2 2006.201.08:49:30.70#ibcon#about to write, iclass 31, count 2 2006.201.08:49:30.70#ibcon#wrote, iclass 31, count 2 2006.201.08:49:30.70#ibcon#about to read 3, iclass 31, count 2 2006.201.08:49:30.73#ibcon#read 3, iclass 31, count 2 2006.201.08:49:30.73#ibcon#about to read 4, iclass 31, count 2 2006.201.08:49:30.73#ibcon#read 4, iclass 31, count 2 2006.201.08:49:30.73#ibcon#about to read 5, iclass 31, count 2 2006.201.08:49:30.73#ibcon#read 5, iclass 31, count 2 2006.201.08:49:30.73#ibcon#about to read 6, iclass 31, count 2 2006.201.08:49:30.73#ibcon#read 6, iclass 31, count 2 2006.201.08:49:30.73#ibcon#end of sib2, iclass 31, count 2 2006.201.08:49:30.73#ibcon#*after write, iclass 31, count 2 2006.201.08:49:30.73#ibcon#*before return 0, iclass 31, count 2 2006.201.08:49:30.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:30.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:30.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.08:49:30.73#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:30.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:30.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:30.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:30.85#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:49:30.85#ibcon#first serial, iclass 31, count 0 2006.201.08:49:30.85#ibcon#enter sib2, iclass 31, count 0 2006.201.08:49:30.85#ibcon#flushed, iclass 31, count 0 2006.201.08:49:30.85#ibcon#about to write, iclass 31, count 0 2006.201.08:49:30.85#ibcon#wrote, iclass 31, count 0 2006.201.08:49:30.85#ibcon#about to read 3, iclass 31, count 0 2006.201.08:49:30.87#ibcon#read 3, iclass 31, count 0 2006.201.08:49:30.87#ibcon#about to read 4, iclass 31, count 0 2006.201.08:49:30.87#ibcon#read 4, iclass 31, count 0 2006.201.08:49:30.87#ibcon#about to read 5, iclass 31, count 0 2006.201.08:49:30.87#ibcon#read 5, iclass 31, count 0 2006.201.08:49:30.87#ibcon#about to read 6, iclass 31, count 0 2006.201.08:49:30.87#ibcon#read 6, iclass 31, count 0 2006.201.08:49:30.87#ibcon#end of sib2, iclass 31, count 0 2006.201.08:49:30.87#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:49:30.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:49:30.87#ibcon#[25=USB\r\n] 2006.201.08:49:30.87#ibcon#*before write, iclass 31, count 0 2006.201.08:49:30.87#ibcon#enter sib2, iclass 31, count 0 2006.201.08:49:30.87#ibcon#flushed, iclass 31, count 0 2006.201.08:49:30.87#ibcon#about to write, iclass 31, count 0 2006.201.08:49:30.87#ibcon#wrote, iclass 31, count 0 2006.201.08:49:30.87#ibcon#about to read 3, iclass 31, count 0 2006.201.08:49:30.90#ibcon#read 3, iclass 31, count 0 2006.201.08:49:30.90#ibcon#about to read 4, iclass 31, count 0 2006.201.08:49:30.90#ibcon#read 4, iclass 31, count 0 2006.201.08:49:30.90#ibcon#about to read 5, iclass 31, count 0 2006.201.08:49:30.90#ibcon#read 5, iclass 31, count 0 2006.201.08:49:30.90#ibcon#about to read 6, iclass 31, count 0 2006.201.08:49:30.90#ibcon#read 6, iclass 31, count 0 2006.201.08:49:30.90#ibcon#end of sib2, iclass 31, count 0 2006.201.08:49:30.90#ibcon#*after write, iclass 31, count 0 2006.201.08:49:30.90#ibcon#*before return 0, iclass 31, count 0 2006.201.08:49:30.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:30.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:30.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:49:30.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:49:30.90$vck44/valo=4,624.99 2006.201.08:49:30.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.08:49:30.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.08:49:30.90#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:30.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:30.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:30.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:30.90#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:49:30.90#ibcon#first serial, iclass 33, count 0 2006.201.08:49:30.90#ibcon#enter sib2, iclass 33, count 0 2006.201.08:49:30.90#ibcon#flushed, iclass 33, count 0 2006.201.08:49:30.90#ibcon#about to write, iclass 33, count 0 2006.201.08:49:30.90#ibcon#wrote, iclass 33, count 0 2006.201.08:49:30.90#ibcon#about to read 3, iclass 33, count 0 2006.201.08:49:30.92#ibcon#read 3, iclass 33, count 0 2006.201.08:49:30.92#ibcon#about to read 4, iclass 33, count 0 2006.201.08:49:30.92#ibcon#read 4, iclass 33, count 0 2006.201.08:49:30.92#ibcon#about to read 5, iclass 33, count 0 2006.201.08:49:30.92#ibcon#read 5, iclass 33, count 0 2006.201.08:49:30.92#ibcon#about to read 6, iclass 33, count 0 2006.201.08:49:30.92#ibcon#read 6, iclass 33, count 0 2006.201.08:49:30.92#ibcon#end of sib2, iclass 33, count 0 2006.201.08:49:30.92#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:49:30.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:49:30.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:49:30.92#ibcon#*before write, iclass 33, count 0 2006.201.08:49:30.92#ibcon#enter sib2, iclass 33, count 0 2006.201.08:49:30.92#ibcon#flushed, iclass 33, count 0 2006.201.08:49:30.92#ibcon#about to write, iclass 33, count 0 2006.201.08:49:30.92#ibcon#wrote, iclass 33, count 0 2006.201.08:49:30.92#ibcon#about to read 3, iclass 33, count 0 2006.201.08:49:30.97#ibcon#read 3, iclass 33, count 0 2006.201.08:49:30.97#ibcon#about to read 4, iclass 33, count 0 2006.201.08:49:30.97#ibcon#read 4, iclass 33, count 0 2006.201.08:49:30.97#ibcon#about to read 5, iclass 33, count 0 2006.201.08:49:30.97#ibcon#read 5, iclass 33, count 0 2006.201.08:49:30.97#ibcon#about to read 6, iclass 33, count 0 2006.201.08:49:30.97#ibcon#read 6, iclass 33, count 0 2006.201.08:49:30.97#ibcon#end of sib2, iclass 33, count 0 2006.201.08:49:30.97#ibcon#*after write, iclass 33, count 0 2006.201.08:49:30.97#ibcon#*before return 0, iclass 33, count 0 2006.201.08:49:30.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:30.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:30.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:49:30.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:49:30.97$vck44/va=4,7 2006.201.08:49:30.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.08:49:30.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.08:49:30.97#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:30.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:31.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:31.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:31.02#ibcon#enter wrdev, iclass 35, count 2 2006.201.08:49:31.02#ibcon#first serial, iclass 35, count 2 2006.201.08:49:31.02#ibcon#enter sib2, iclass 35, count 2 2006.201.08:49:31.02#ibcon#flushed, iclass 35, count 2 2006.201.08:49:31.02#ibcon#about to write, iclass 35, count 2 2006.201.08:49:31.02#ibcon#wrote, iclass 35, count 2 2006.201.08:49:31.02#ibcon#about to read 3, iclass 35, count 2 2006.201.08:49:31.04#ibcon#read 3, iclass 35, count 2 2006.201.08:49:31.04#ibcon#about to read 4, iclass 35, count 2 2006.201.08:49:31.04#ibcon#read 4, iclass 35, count 2 2006.201.08:49:31.04#ibcon#about to read 5, iclass 35, count 2 2006.201.08:49:31.04#ibcon#read 5, iclass 35, count 2 2006.201.08:49:31.04#ibcon#about to read 6, iclass 35, count 2 2006.201.08:49:31.04#ibcon#read 6, iclass 35, count 2 2006.201.08:49:31.04#ibcon#end of sib2, iclass 35, count 2 2006.201.08:49:31.04#ibcon#*mode == 0, iclass 35, count 2 2006.201.08:49:31.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.08:49:31.04#ibcon#[25=AT04-07\r\n] 2006.201.08:49:31.04#ibcon#*before write, iclass 35, count 2 2006.201.08:49:31.04#ibcon#enter sib2, iclass 35, count 2 2006.201.08:49:31.04#ibcon#flushed, iclass 35, count 2 2006.201.08:49:31.04#ibcon#about to write, iclass 35, count 2 2006.201.08:49:31.04#ibcon#wrote, iclass 35, count 2 2006.201.08:49:31.04#ibcon#about to read 3, iclass 35, count 2 2006.201.08:49:31.07#ibcon#read 3, iclass 35, count 2 2006.201.08:49:31.07#ibcon#about to read 4, iclass 35, count 2 2006.201.08:49:31.07#ibcon#read 4, iclass 35, count 2 2006.201.08:49:31.07#ibcon#about to read 5, iclass 35, count 2 2006.201.08:49:31.07#ibcon#read 5, iclass 35, count 2 2006.201.08:49:31.07#ibcon#about to read 6, iclass 35, count 2 2006.201.08:49:31.07#ibcon#read 6, iclass 35, count 2 2006.201.08:49:31.07#ibcon#end of sib2, iclass 35, count 2 2006.201.08:49:31.07#ibcon#*after write, iclass 35, count 2 2006.201.08:49:31.07#ibcon#*before return 0, iclass 35, count 2 2006.201.08:49:31.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:31.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:31.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.08:49:31.07#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:31.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:31.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:31.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:31.19#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:49:31.19#ibcon#first serial, iclass 35, count 0 2006.201.08:49:31.19#ibcon#enter sib2, iclass 35, count 0 2006.201.08:49:31.19#ibcon#flushed, iclass 35, count 0 2006.201.08:49:31.19#ibcon#about to write, iclass 35, count 0 2006.201.08:49:31.19#ibcon#wrote, iclass 35, count 0 2006.201.08:49:31.19#ibcon#about to read 3, iclass 35, count 0 2006.201.08:49:31.21#ibcon#read 3, iclass 35, count 0 2006.201.08:49:31.21#ibcon#about to read 4, iclass 35, count 0 2006.201.08:49:31.21#ibcon#read 4, iclass 35, count 0 2006.201.08:49:31.21#ibcon#about to read 5, iclass 35, count 0 2006.201.08:49:31.21#ibcon#read 5, iclass 35, count 0 2006.201.08:49:31.21#ibcon#about to read 6, iclass 35, count 0 2006.201.08:49:31.21#ibcon#read 6, iclass 35, count 0 2006.201.08:49:31.21#ibcon#end of sib2, iclass 35, count 0 2006.201.08:49:31.21#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:49:31.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:49:31.21#ibcon#[25=USB\r\n] 2006.201.08:49:31.21#ibcon#*before write, iclass 35, count 0 2006.201.08:49:31.21#ibcon#enter sib2, iclass 35, count 0 2006.201.08:49:31.21#ibcon#flushed, iclass 35, count 0 2006.201.08:49:31.21#ibcon#about to write, iclass 35, count 0 2006.201.08:49:31.21#ibcon#wrote, iclass 35, count 0 2006.201.08:49:31.21#ibcon#about to read 3, iclass 35, count 0 2006.201.08:49:31.24#ibcon#read 3, iclass 35, count 0 2006.201.08:49:31.24#ibcon#about to read 4, iclass 35, count 0 2006.201.08:49:31.24#ibcon#read 4, iclass 35, count 0 2006.201.08:49:31.24#ibcon#about to read 5, iclass 35, count 0 2006.201.08:49:31.24#ibcon#read 5, iclass 35, count 0 2006.201.08:49:31.24#ibcon#about to read 6, iclass 35, count 0 2006.201.08:49:31.24#ibcon#read 6, iclass 35, count 0 2006.201.08:49:31.24#ibcon#end of sib2, iclass 35, count 0 2006.201.08:49:31.24#ibcon#*after write, iclass 35, count 0 2006.201.08:49:31.24#ibcon#*before return 0, iclass 35, count 0 2006.201.08:49:31.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:31.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:31.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:49:31.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:49:31.24$vck44/valo=5,734.99 2006.201.08:49:31.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.08:49:31.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.08:49:31.24#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:31.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:31.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:31.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:31.24#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:49:31.24#ibcon#first serial, iclass 37, count 0 2006.201.08:49:31.24#ibcon#enter sib2, iclass 37, count 0 2006.201.08:49:31.24#ibcon#flushed, iclass 37, count 0 2006.201.08:49:31.24#ibcon#about to write, iclass 37, count 0 2006.201.08:49:31.24#ibcon#wrote, iclass 37, count 0 2006.201.08:49:31.24#ibcon#about to read 3, iclass 37, count 0 2006.201.08:49:31.26#ibcon#read 3, iclass 37, count 0 2006.201.08:49:31.26#ibcon#about to read 4, iclass 37, count 0 2006.201.08:49:31.26#ibcon#read 4, iclass 37, count 0 2006.201.08:49:31.26#ibcon#about to read 5, iclass 37, count 0 2006.201.08:49:31.26#ibcon#read 5, iclass 37, count 0 2006.201.08:49:31.26#ibcon#about to read 6, iclass 37, count 0 2006.201.08:49:31.26#ibcon#read 6, iclass 37, count 0 2006.201.08:49:31.26#ibcon#end of sib2, iclass 37, count 0 2006.201.08:49:31.26#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:49:31.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:49:31.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:49:31.26#ibcon#*before write, iclass 37, count 0 2006.201.08:49:31.26#ibcon#enter sib2, iclass 37, count 0 2006.201.08:49:31.26#ibcon#flushed, iclass 37, count 0 2006.201.08:49:31.26#ibcon#about to write, iclass 37, count 0 2006.201.08:49:31.26#ibcon#wrote, iclass 37, count 0 2006.201.08:49:31.26#ibcon#about to read 3, iclass 37, count 0 2006.201.08:49:31.30#ibcon#read 3, iclass 37, count 0 2006.201.08:49:31.30#ibcon#about to read 4, iclass 37, count 0 2006.201.08:49:31.30#ibcon#read 4, iclass 37, count 0 2006.201.08:49:31.30#ibcon#about to read 5, iclass 37, count 0 2006.201.08:49:31.30#ibcon#read 5, iclass 37, count 0 2006.201.08:49:31.30#ibcon#about to read 6, iclass 37, count 0 2006.201.08:49:31.30#ibcon#read 6, iclass 37, count 0 2006.201.08:49:31.30#ibcon#end of sib2, iclass 37, count 0 2006.201.08:49:31.30#ibcon#*after write, iclass 37, count 0 2006.201.08:49:31.30#ibcon#*before return 0, iclass 37, count 0 2006.201.08:49:31.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:31.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:31.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:49:31.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:49:31.30$vck44/va=5,4 2006.201.08:49:31.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.08:49:31.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.08:49:31.30#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:31.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:31.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:31.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:31.36#ibcon#enter wrdev, iclass 39, count 2 2006.201.08:49:31.36#ibcon#first serial, iclass 39, count 2 2006.201.08:49:31.36#ibcon#enter sib2, iclass 39, count 2 2006.201.08:49:31.36#ibcon#flushed, iclass 39, count 2 2006.201.08:49:31.36#ibcon#about to write, iclass 39, count 2 2006.201.08:49:31.36#ibcon#wrote, iclass 39, count 2 2006.201.08:49:31.36#ibcon#about to read 3, iclass 39, count 2 2006.201.08:49:31.38#ibcon#read 3, iclass 39, count 2 2006.201.08:49:31.38#ibcon#about to read 4, iclass 39, count 2 2006.201.08:49:31.38#ibcon#read 4, iclass 39, count 2 2006.201.08:49:31.38#ibcon#about to read 5, iclass 39, count 2 2006.201.08:49:31.38#ibcon#read 5, iclass 39, count 2 2006.201.08:49:31.38#ibcon#about to read 6, iclass 39, count 2 2006.201.08:49:31.38#ibcon#read 6, iclass 39, count 2 2006.201.08:49:31.38#ibcon#end of sib2, iclass 39, count 2 2006.201.08:49:31.38#ibcon#*mode == 0, iclass 39, count 2 2006.201.08:49:31.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.08:49:31.38#ibcon#[25=AT05-04\r\n] 2006.201.08:49:31.38#ibcon#*before write, iclass 39, count 2 2006.201.08:49:31.38#ibcon#enter sib2, iclass 39, count 2 2006.201.08:49:31.38#ibcon#flushed, iclass 39, count 2 2006.201.08:49:31.38#ibcon#about to write, iclass 39, count 2 2006.201.08:49:31.38#ibcon#wrote, iclass 39, count 2 2006.201.08:49:31.38#ibcon#about to read 3, iclass 39, count 2 2006.201.08:49:31.41#ibcon#read 3, iclass 39, count 2 2006.201.08:49:31.41#ibcon#about to read 4, iclass 39, count 2 2006.201.08:49:31.41#ibcon#read 4, iclass 39, count 2 2006.201.08:49:31.41#ibcon#about to read 5, iclass 39, count 2 2006.201.08:49:31.41#ibcon#read 5, iclass 39, count 2 2006.201.08:49:31.41#ibcon#about to read 6, iclass 39, count 2 2006.201.08:49:31.41#ibcon#read 6, iclass 39, count 2 2006.201.08:49:31.41#ibcon#end of sib2, iclass 39, count 2 2006.201.08:49:31.41#ibcon#*after write, iclass 39, count 2 2006.201.08:49:31.41#ibcon#*before return 0, iclass 39, count 2 2006.201.08:49:31.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:31.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:31.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.08:49:31.41#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:31.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:31.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:31.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:31.53#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:49:31.53#ibcon#first serial, iclass 39, count 0 2006.201.08:49:31.53#ibcon#enter sib2, iclass 39, count 0 2006.201.08:49:31.53#ibcon#flushed, iclass 39, count 0 2006.201.08:49:31.53#ibcon#about to write, iclass 39, count 0 2006.201.08:49:31.53#ibcon#wrote, iclass 39, count 0 2006.201.08:49:31.53#ibcon#about to read 3, iclass 39, count 0 2006.201.08:49:31.55#ibcon#read 3, iclass 39, count 0 2006.201.08:49:31.55#ibcon#about to read 4, iclass 39, count 0 2006.201.08:49:31.55#ibcon#read 4, iclass 39, count 0 2006.201.08:49:31.55#ibcon#about to read 5, iclass 39, count 0 2006.201.08:49:31.55#ibcon#read 5, iclass 39, count 0 2006.201.08:49:31.55#ibcon#about to read 6, iclass 39, count 0 2006.201.08:49:31.55#ibcon#read 6, iclass 39, count 0 2006.201.08:49:31.55#ibcon#end of sib2, iclass 39, count 0 2006.201.08:49:31.55#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:49:31.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:49:31.55#ibcon#[25=USB\r\n] 2006.201.08:49:31.55#ibcon#*before write, iclass 39, count 0 2006.201.08:49:31.55#ibcon#enter sib2, iclass 39, count 0 2006.201.08:49:31.55#ibcon#flushed, iclass 39, count 0 2006.201.08:49:31.55#ibcon#about to write, iclass 39, count 0 2006.201.08:49:31.55#ibcon#wrote, iclass 39, count 0 2006.201.08:49:31.55#ibcon#about to read 3, iclass 39, count 0 2006.201.08:49:31.58#ibcon#read 3, iclass 39, count 0 2006.201.08:49:31.58#ibcon#about to read 4, iclass 39, count 0 2006.201.08:49:31.58#ibcon#read 4, iclass 39, count 0 2006.201.08:49:31.58#ibcon#about to read 5, iclass 39, count 0 2006.201.08:49:31.58#ibcon#read 5, iclass 39, count 0 2006.201.08:49:31.58#ibcon#about to read 6, iclass 39, count 0 2006.201.08:49:31.58#ibcon#read 6, iclass 39, count 0 2006.201.08:49:31.58#ibcon#end of sib2, iclass 39, count 0 2006.201.08:49:31.58#ibcon#*after write, iclass 39, count 0 2006.201.08:49:31.58#ibcon#*before return 0, iclass 39, count 0 2006.201.08:49:31.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:31.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:31.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:49:31.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:49:31.58$vck44/valo=6,814.99 2006.201.08:49:31.58#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.08:49:31.58#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.08:49:31.58#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:31.58#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:31.58#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:31.58#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:31.58#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:49:31.58#ibcon#first serial, iclass 2, count 0 2006.201.08:49:31.58#ibcon#enter sib2, iclass 2, count 0 2006.201.08:49:31.58#ibcon#flushed, iclass 2, count 0 2006.201.08:49:31.58#ibcon#about to write, iclass 2, count 0 2006.201.08:49:31.58#ibcon#wrote, iclass 2, count 0 2006.201.08:49:31.58#ibcon#about to read 3, iclass 2, count 0 2006.201.08:49:31.60#ibcon#read 3, iclass 2, count 0 2006.201.08:49:31.60#ibcon#about to read 4, iclass 2, count 0 2006.201.08:49:31.60#ibcon#read 4, iclass 2, count 0 2006.201.08:49:31.60#ibcon#about to read 5, iclass 2, count 0 2006.201.08:49:31.60#ibcon#read 5, iclass 2, count 0 2006.201.08:49:31.60#ibcon#about to read 6, iclass 2, count 0 2006.201.08:49:31.60#ibcon#read 6, iclass 2, count 0 2006.201.08:49:31.60#ibcon#end of sib2, iclass 2, count 0 2006.201.08:49:31.60#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:49:31.60#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:49:31.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:49:31.60#ibcon#*before write, iclass 2, count 0 2006.201.08:49:31.60#ibcon#enter sib2, iclass 2, count 0 2006.201.08:49:31.60#ibcon#flushed, iclass 2, count 0 2006.201.08:49:31.60#ibcon#about to write, iclass 2, count 0 2006.201.08:49:31.60#ibcon#wrote, iclass 2, count 0 2006.201.08:49:31.60#ibcon#about to read 3, iclass 2, count 0 2006.201.08:49:31.64#ibcon#read 3, iclass 2, count 0 2006.201.08:49:31.64#ibcon#about to read 4, iclass 2, count 0 2006.201.08:49:31.64#ibcon#read 4, iclass 2, count 0 2006.201.08:49:31.64#ibcon#about to read 5, iclass 2, count 0 2006.201.08:49:31.64#ibcon#read 5, iclass 2, count 0 2006.201.08:49:31.64#ibcon#about to read 6, iclass 2, count 0 2006.201.08:49:31.64#ibcon#read 6, iclass 2, count 0 2006.201.08:49:31.64#ibcon#end of sib2, iclass 2, count 0 2006.201.08:49:31.64#ibcon#*after write, iclass 2, count 0 2006.201.08:49:31.64#ibcon#*before return 0, iclass 2, count 0 2006.201.08:49:31.64#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:31.64#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:31.64#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:49:31.64#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:49:31.64$vck44/va=6,5 2006.201.08:49:31.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.08:49:31.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.08:49:31.64#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:31.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:31.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:31.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:31.70#ibcon#enter wrdev, iclass 5, count 2 2006.201.08:49:31.70#ibcon#first serial, iclass 5, count 2 2006.201.08:49:31.70#ibcon#enter sib2, iclass 5, count 2 2006.201.08:49:31.70#ibcon#flushed, iclass 5, count 2 2006.201.08:49:31.70#ibcon#about to write, iclass 5, count 2 2006.201.08:49:31.70#ibcon#wrote, iclass 5, count 2 2006.201.08:49:31.70#ibcon#about to read 3, iclass 5, count 2 2006.201.08:49:31.72#ibcon#read 3, iclass 5, count 2 2006.201.08:49:31.72#ibcon#about to read 4, iclass 5, count 2 2006.201.08:49:31.72#ibcon#read 4, iclass 5, count 2 2006.201.08:49:31.72#ibcon#about to read 5, iclass 5, count 2 2006.201.08:49:31.72#ibcon#read 5, iclass 5, count 2 2006.201.08:49:31.72#ibcon#about to read 6, iclass 5, count 2 2006.201.08:49:31.72#ibcon#read 6, iclass 5, count 2 2006.201.08:49:31.72#ibcon#end of sib2, iclass 5, count 2 2006.201.08:49:31.72#ibcon#*mode == 0, iclass 5, count 2 2006.201.08:49:31.72#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.08:49:31.72#ibcon#[25=AT06-05\r\n] 2006.201.08:49:31.72#ibcon#*before write, iclass 5, count 2 2006.201.08:49:31.72#ibcon#enter sib2, iclass 5, count 2 2006.201.08:49:31.72#ibcon#flushed, iclass 5, count 2 2006.201.08:49:31.72#ibcon#about to write, iclass 5, count 2 2006.201.08:49:31.72#ibcon#wrote, iclass 5, count 2 2006.201.08:49:31.72#ibcon#about to read 3, iclass 5, count 2 2006.201.08:49:31.75#ibcon#read 3, iclass 5, count 2 2006.201.08:49:31.75#ibcon#about to read 4, iclass 5, count 2 2006.201.08:49:31.75#ibcon#read 4, iclass 5, count 2 2006.201.08:49:31.75#ibcon#about to read 5, iclass 5, count 2 2006.201.08:49:31.75#ibcon#read 5, iclass 5, count 2 2006.201.08:49:31.75#ibcon#about to read 6, iclass 5, count 2 2006.201.08:49:31.75#ibcon#read 6, iclass 5, count 2 2006.201.08:49:31.75#ibcon#end of sib2, iclass 5, count 2 2006.201.08:49:31.75#ibcon#*after write, iclass 5, count 2 2006.201.08:49:31.75#ibcon#*before return 0, iclass 5, count 2 2006.201.08:49:31.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:31.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:31.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.08:49:31.75#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:31.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:31.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:31.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:31.87#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:49:31.87#ibcon#first serial, iclass 5, count 0 2006.201.08:49:31.87#ibcon#enter sib2, iclass 5, count 0 2006.201.08:49:31.87#ibcon#flushed, iclass 5, count 0 2006.201.08:49:31.87#ibcon#about to write, iclass 5, count 0 2006.201.08:49:31.87#ibcon#wrote, iclass 5, count 0 2006.201.08:49:31.87#ibcon#about to read 3, iclass 5, count 0 2006.201.08:49:31.89#ibcon#read 3, iclass 5, count 0 2006.201.08:49:31.89#ibcon#about to read 4, iclass 5, count 0 2006.201.08:49:31.89#ibcon#read 4, iclass 5, count 0 2006.201.08:49:31.89#ibcon#about to read 5, iclass 5, count 0 2006.201.08:49:31.89#ibcon#read 5, iclass 5, count 0 2006.201.08:49:31.89#ibcon#about to read 6, iclass 5, count 0 2006.201.08:49:31.89#ibcon#read 6, iclass 5, count 0 2006.201.08:49:31.89#ibcon#end of sib2, iclass 5, count 0 2006.201.08:49:31.89#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:49:31.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:49:31.89#ibcon#[25=USB\r\n] 2006.201.08:49:31.89#ibcon#*before write, iclass 5, count 0 2006.201.08:49:31.89#ibcon#enter sib2, iclass 5, count 0 2006.201.08:49:31.89#ibcon#flushed, iclass 5, count 0 2006.201.08:49:31.89#ibcon#about to write, iclass 5, count 0 2006.201.08:49:31.89#ibcon#wrote, iclass 5, count 0 2006.201.08:49:31.89#ibcon#about to read 3, iclass 5, count 0 2006.201.08:49:31.92#ibcon#read 3, iclass 5, count 0 2006.201.08:49:31.92#ibcon#about to read 4, iclass 5, count 0 2006.201.08:49:31.92#ibcon#read 4, iclass 5, count 0 2006.201.08:49:31.92#ibcon#about to read 5, iclass 5, count 0 2006.201.08:49:31.92#ibcon#read 5, iclass 5, count 0 2006.201.08:49:31.92#ibcon#about to read 6, iclass 5, count 0 2006.201.08:49:31.92#ibcon#read 6, iclass 5, count 0 2006.201.08:49:31.92#ibcon#end of sib2, iclass 5, count 0 2006.201.08:49:31.92#ibcon#*after write, iclass 5, count 0 2006.201.08:49:31.92#ibcon#*before return 0, iclass 5, count 0 2006.201.08:49:31.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:31.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:31.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:49:31.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:49:31.92$vck44/valo=7,864.99 2006.201.08:49:31.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.08:49:31.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.08:49:31.92#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:31.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:31.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:31.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:31.92#ibcon#enter wrdev, iclass 7, count 0 2006.201.08:49:31.92#ibcon#first serial, iclass 7, count 0 2006.201.08:49:31.92#ibcon#enter sib2, iclass 7, count 0 2006.201.08:49:31.92#ibcon#flushed, iclass 7, count 0 2006.201.08:49:31.92#ibcon#about to write, iclass 7, count 0 2006.201.08:49:31.92#ibcon#wrote, iclass 7, count 0 2006.201.08:49:31.92#ibcon#about to read 3, iclass 7, count 0 2006.201.08:49:31.94#ibcon#read 3, iclass 7, count 0 2006.201.08:49:31.94#ibcon#about to read 4, iclass 7, count 0 2006.201.08:49:31.94#ibcon#read 4, iclass 7, count 0 2006.201.08:49:31.94#ibcon#about to read 5, iclass 7, count 0 2006.201.08:49:31.94#ibcon#read 5, iclass 7, count 0 2006.201.08:49:31.94#ibcon#about to read 6, iclass 7, count 0 2006.201.08:49:31.94#ibcon#read 6, iclass 7, count 0 2006.201.08:49:31.94#ibcon#end of sib2, iclass 7, count 0 2006.201.08:49:31.94#ibcon#*mode == 0, iclass 7, count 0 2006.201.08:49:31.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.08:49:31.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:49:31.94#ibcon#*before write, iclass 7, count 0 2006.201.08:49:31.94#ibcon#enter sib2, iclass 7, count 0 2006.201.08:49:31.94#ibcon#flushed, iclass 7, count 0 2006.201.08:49:31.94#ibcon#about to write, iclass 7, count 0 2006.201.08:49:31.94#ibcon#wrote, iclass 7, count 0 2006.201.08:49:31.94#ibcon#about to read 3, iclass 7, count 0 2006.201.08:49:31.99#ibcon#read 3, iclass 7, count 0 2006.201.08:49:31.99#ibcon#about to read 4, iclass 7, count 0 2006.201.08:49:31.99#ibcon#read 4, iclass 7, count 0 2006.201.08:49:31.99#ibcon#about to read 5, iclass 7, count 0 2006.201.08:49:31.99#ibcon#read 5, iclass 7, count 0 2006.201.08:49:31.99#ibcon#about to read 6, iclass 7, count 0 2006.201.08:49:31.99#ibcon#read 6, iclass 7, count 0 2006.201.08:49:31.99#ibcon#end of sib2, iclass 7, count 0 2006.201.08:49:31.99#ibcon#*after write, iclass 7, count 0 2006.201.08:49:31.99#ibcon#*before return 0, iclass 7, count 0 2006.201.08:49:31.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:31.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:31.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.08:49:31.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.08:49:31.99$vck44/va=7,5 2006.201.08:49:31.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.08:49:31.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.08:49:31.99#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:31.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:32.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:32.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:32.04#ibcon#enter wrdev, iclass 11, count 2 2006.201.08:49:32.04#ibcon#first serial, iclass 11, count 2 2006.201.08:49:32.04#ibcon#enter sib2, iclass 11, count 2 2006.201.08:49:32.04#ibcon#flushed, iclass 11, count 2 2006.201.08:49:32.04#ibcon#about to write, iclass 11, count 2 2006.201.08:49:32.04#ibcon#wrote, iclass 11, count 2 2006.201.08:49:32.04#ibcon#about to read 3, iclass 11, count 2 2006.201.08:49:32.06#ibcon#read 3, iclass 11, count 2 2006.201.08:49:32.06#ibcon#about to read 4, iclass 11, count 2 2006.201.08:49:32.06#ibcon#read 4, iclass 11, count 2 2006.201.08:49:32.06#ibcon#about to read 5, iclass 11, count 2 2006.201.08:49:32.06#ibcon#read 5, iclass 11, count 2 2006.201.08:49:32.06#ibcon#about to read 6, iclass 11, count 2 2006.201.08:49:32.06#ibcon#read 6, iclass 11, count 2 2006.201.08:49:32.06#ibcon#end of sib2, iclass 11, count 2 2006.201.08:49:32.06#ibcon#*mode == 0, iclass 11, count 2 2006.201.08:49:32.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.08:49:32.06#ibcon#[25=AT07-05\r\n] 2006.201.08:49:32.06#ibcon#*before write, iclass 11, count 2 2006.201.08:49:32.06#ibcon#enter sib2, iclass 11, count 2 2006.201.08:49:32.06#ibcon#flushed, iclass 11, count 2 2006.201.08:49:32.06#ibcon#about to write, iclass 11, count 2 2006.201.08:49:32.06#ibcon#wrote, iclass 11, count 2 2006.201.08:49:32.06#ibcon#about to read 3, iclass 11, count 2 2006.201.08:49:32.09#ibcon#read 3, iclass 11, count 2 2006.201.08:49:32.09#ibcon#about to read 4, iclass 11, count 2 2006.201.08:49:32.09#ibcon#read 4, iclass 11, count 2 2006.201.08:49:32.09#ibcon#about to read 5, iclass 11, count 2 2006.201.08:49:32.09#ibcon#read 5, iclass 11, count 2 2006.201.08:49:32.09#ibcon#about to read 6, iclass 11, count 2 2006.201.08:49:32.09#ibcon#read 6, iclass 11, count 2 2006.201.08:49:32.09#ibcon#end of sib2, iclass 11, count 2 2006.201.08:49:32.09#ibcon#*after write, iclass 11, count 2 2006.201.08:49:32.09#ibcon#*before return 0, iclass 11, count 2 2006.201.08:49:32.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:32.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:32.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.08:49:32.09#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:32.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:32.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:32.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:32.21#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:49:32.21#ibcon#first serial, iclass 11, count 0 2006.201.08:49:32.21#ibcon#enter sib2, iclass 11, count 0 2006.201.08:49:32.21#ibcon#flushed, iclass 11, count 0 2006.201.08:49:32.21#ibcon#about to write, iclass 11, count 0 2006.201.08:49:32.21#ibcon#wrote, iclass 11, count 0 2006.201.08:49:32.21#ibcon#about to read 3, iclass 11, count 0 2006.201.08:49:32.23#ibcon#read 3, iclass 11, count 0 2006.201.08:49:32.23#ibcon#about to read 4, iclass 11, count 0 2006.201.08:49:32.23#ibcon#read 4, iclass 11, count 0 2006.201.08:49:32.23#ibcon#about to read 5, iclass 11, count 0 2006.201.08:49:32.23#ibcon#read 5, iclass 11, count 0 2006.201.08:49:32.23#ibcon#about to read 6, iclass 11, count 0 2006.201.08:49:32.23#ibcon#read 6, iclass 11, count 0 2006.201.08:49:32.23#ibcon#end of sib2, iclass 11, count 0 2006.201.08:49:32.23#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:49:32.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:49:32.23#ibcon#[25=USB\r\n] 2006.201.08:49:32.23#ibcon#*before write, iclass 11, count 0 2006.201.08:49:32.23#ibcon#enter sib2, iclass 11, count 0 2006.201.08:49:32.23#ibcon#flushed, iclass 11, count 0 2006.201.08:49:32.23#ibcon#about to write, iclass 11, count 0 2006.201.08:49:32.23#ibcon#wrote, iclass 11, count 0 2006.201.08:49:32.23#ibcon#about to read 3, iclass 11, count 0 2006.201.08:49:32.26#ibcon#read 3, iclass 11, count 0 2006.201.08:49:32.26#ibcon#about to read 4, iclass 11, count 0 2006.201.08:49:32.26#ibcon#read 4, iclass 11, count 0 2006.201.08:49:32.26#ibcon#about to read 5, iclass 11, count 0 2006.201.08:49:32.26#ibcon#read 5, iclass 11, count 0 2006.201.08:49:32.26#ibcon#about to read 6, iclass 11, count 0 2006.201.08:49:32.26#ibcon#read 6, iclass 11, count 0 2006.201.08:49:32.26#ibcon#end of sib2, iclass 11, count 0 2006.201.08:49:32.26#ibcon#*after write, iclass 11, count 0 2006.201.08:49:32.26#ibcon#*before return 0, iclass 11, count 0 2006.201.08:49:32.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:32.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:32.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:49:32.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:49:32.26$vck44/valo=8,884.99 2006.201.08:49:32.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.08:49:32.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.08:49:32.26#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:32.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:32.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:32.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:32.26#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:49:32.26#ibcon#first serial, iclass 13, count 0 2006.201.08:49:32.26#ibcon#enter sib2, iclass 13, count 0 2006.201.08:49:32.26#ibcon#flushed, iclass 13, count 0 2006.201.08:49:32.26#ibcon#about to write, iclass 13, count 0 2006.201.08:49:32.26#ibcon#wrote, iclass 13, count 0 2006.201.08:49:32.26#ibcon#about to read 3, iclass 13, count 0 2006.201.08:49:32.28#ibcon#read 3, iclass 13, count 0 2006.201.08:49:32.28#ibcon#about to read 4, iclass 13, count 0 2006.201.08:49:32.28#ibcon#read 4, iclass 13, count 0 2006.201.08:49:32.28#ibcon#about to read 5, iclass 13, count 0 2006.201.08:49:32.28#ibcon#read 5, iclass 13, count 0 2006.201.08:49:32.28#ibcon#about to read 6, iclass 13, count 0 2006.201.08:49:32.28#ibcon#read 6, iclass 13, count 0 2006.201.08:49:32.28#ibcon#end of sib2, iclass 13, count 0 2006.201.08:49:32.28#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:49:32.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:49:32.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:49:32.28#ibcon#*before write, iclass 13, count 0 2006.201.08:49:32.28#ibcon#enter sib2, iclass 13, count 0 2006.201.08:49:32.28#ibcon#flushed, iclass 13, count 0 2006.201.08:49:32.28#ibcon#about to write, iclass 13, count 0 2006.201.08:49:32.28#ibcon#wrote, iclass 13, count 0 2006.201.08:49:32.28#ibcon#about to read 3, iclass 13, count 0 2006.201.08:49:32.32#ibcon#read 3, iclass 13, count 0 2006.201.08:49:32.32#ibcon#about to read 4, iclass 13, count 0 2006.201.08:49:32.32#ibcon#read 4, iclass 13, count 0 2006.201.08:49:32.32#ibcon#about to read 5, iclass 13, count 0 2006.201.08:49:32.32#ibcon#read 5, iclass 13, count 0 2006.201.08:49:32.32#ibcon#about to read 6, iclass 13, count 0 2006.201.08:49:32.32#ibcon#read 6, iclass 13, count 0 2006.201.08:49:32.32#ibcon#end of sib2, iclass 13, count 0 2006.201.08:49:32.32#ibcon#*after write, iclass 13, count 0 2006.201.08:49:32.32#ibcon#*before return 0, iclass 13, count 0 2006.201.08:49:32.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:32.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:32.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:49:32.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:49:32.32$vck44/va=8,4 2006.201.08:49:32.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.08:49:32.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.08:49:32.32#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:32.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:32.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:32.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:32.38#ibcon#enter wrdev, iclass 15, count 2 2006.201.08:49:32.38#ibcon#first serial, iclass 15, count 2 2006.201.08:49:32.38#ibcon#enter sib2, iclass 15, count 2 2006.201.08:49:32.38#ibcon#flushed, iclass 15, count 2 2006.201.08:49:32.38#ibcon#about to write, iclass 15, count 2 2006.201.08:49:32.38#ibcon#wrote, iclass 15, count 2 2006.201.08:49:32.38#ibcon#about to read 3, iclass 15, count 2 2006.201.08:49:32.40#ibcon#read 3, iclass 15, count 2 2006.201.08:49:32.40#ibcon#about to read 4, iclass 15, count 2 2006.201.08:49:32.40#ibcon#read 4, iclass 15, count 2 2006.201.08:49:32.40#ibcon#about to read 5, iclass 15, count 2 2006.201.08:49:32.40#ibcon#read 5, iclass 15, count 2 2006.201.08:49:32.40#ibcon#about to read 6, iclass 15, count 2 2006.201.08:49:32.40#ibcon#read 6, iclass 15, count 2 2006.201.08:49:32.40#ibcon#end of sib2, iclass 15, count 2 2006.201.08:49:32.40#ibcon#*mode == 0, iclass 15, count 2 2006.201.08:49:32.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.08:49:32.40#ibcon#[25=AT08-04\r\n] 2006.201.08:49:32.40#ibcon#*before write, iclass 15, count 2 2006.201.08:49:32.40#ibcon#enter sib2, iclass 15, count 2 2006.201.08:49:32.40#ibcon#flushed, iclass 15, count 2 2006.201.08:49:32.40#ibcon#about to write, iclass 15, count 2 2006.201.08:49:32.40#ibcon#wrote, iclass 15, count 2 2006.201.08:49:32.40#ibcon#about to read 3, iclass 15, count 2 2006.201.08:49:32.43#ibcon#read 3, iclass 15, count 2 2006.201.08:49:32.43#ibcon#about to read 4, iclass 15, count 2 2006.201.08:49:32.43#ibcon#read 4, iclass 15, count 2 2006.201.08:49:32.43#ibcon#about to read 5, iclass 15, count 2 2006.201.08:49:32.43#ibcon#read 5, iclass 15, count 2 2006.201.08:49:32.43#ibcon#about to read 6, iclass 15, count 2 2006.201.08:49:32.43#ibcon#read 6, iclass 15, count 2 2006.201.08:49:32.43#ibcon#end of sib2, iclass 15, count 2 2006.201.08:49:32.43#ibcon#*after write, iclass 15, count 2 2006.201.08:49:32.43#ibcon#*before return 0, iclass 15, count 2 2006.201.08:49:32.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:32.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:32.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.08:49:32.43#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:32.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:32.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:32.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:32.55#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:49:32.55#ibcon#first serial, iclass 15, count 0 2006.201.08:49:32.55#ibcon#enter sib2, iclass 15, count 0 2006.201.08:49:32.55#ibcon#flushed, iclass 15, count 0 2006.201.08:49:32.55#ibcon#about to write, iclass 15, count 0 2006.201.08:49:32.55#ibcon#wrote, iclass 15, count 0 2006.201.08:49:32.55#ibcon#about to read 3, iclass 15, count 0 2006.201.08:49:32.57#ibcon#read 3, iclass 15, count 0 2006.201.08:49:32.57#ibcon#about to read 4, iclass 15, count 0 2006.201.08:49:32.57#ibcon#read 4, iclass 15, count 0 2006.201.08:49:32.57#ibcon#about to read 5, iclass 15, count 0 2006.201.08:49:32.57#ibcon#read 5, iclass 15, count 0 2006.201.08:49:32.57#ibcon#about to read 6, iclass 15, count 0 2006.201.08:49:32.57#ibcon#read 6, iclass 15, count 0 2006.201.08:49:32.57#ibcon#end of sib2, iclass 15, count 0 2006.201.08:49:32.57#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:49:32.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:49:32.57#ibcon#[25=USB\r\n] 2006.201.08:49:32.57#ibcon#*before write, iclass 15, count 0 2006.201.08:49:32.57#ibcon#enter sib2, iclass 15, count 0 2006.201.08:49:32.57#ibcon#flushed, iclass 15, count 0 2006.201.08:49:32.57#ibcon#about to write, iclass 15, count 0 2006.201.08:49:32.57#ibcon#wrote, iclass 15, count 0 2006.201.08:49:32.57#ibcon#about to read 3, iclass 15, count 0 2006.201.08:49:32.60#ibcon#read 3, iclass 15, count 0 2006.201.08:49:32.60#ibcon#about to read 4, iclass 15, count 0 2006.201.08:49:32.60#ibcon#read 4, iclass 15, count 0 2006.201.08:49:32.60#ibcon#about to read 5, iclass 15, count 0 2006.201.08:49:32.60#ibcon#read 5, iclass 15, count 0 2006.201.08:49:32.60#ibcon#about to read 6, iclass 15, count 0 2006.201.08:49:32.60#ibcon#read 6, iclass 15, count 0 2006.201.08:49:32.60#ibcon#end of sib2, iclass 15, count 0 2006.201.08:49:32.60#ibcon#*after write, iclass 15, count 0 2006.201.08:49:32.60#ibcon#*before return 0, iclass 15, count 0 2006.201.08:49:32.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:32.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:32.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:49:32.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:49:32.60$vck44/vblo=1,629.99 2006.201.08:49:32.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.08:49:32.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.08:49:32.60#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:32.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:32.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:32.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:32.60#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:49:32.60#ibcon#first serial, iclass 17, count 0 2006.201.08:49:32.60#ibcon#enter sib2, iclass 17, count 0 2006.201.08:49:32.60#ibcon#flushed, iclass 17, count 0 2006.201.08:49:32.60#ibcon#about to write, iclass 17, count 0 2006.201.08:49:32.60#ibcon#wrote, iclass 17, count 0 2006.201.08:49:32.60#ibcon#about to read 3, iclass 17, count 0 2006.201.08:49:32.62#ibcon#read 3, iclass 17, count 0 2006.201.08:49:32.62#ibcon#about to read 4, iclass 17, count 0 2006.201.08:49:32.62#ibcon#read 4, iclass 17, count 0 2006.201.08:49:32.62#ibcon#about to read 5, iclass 17, count 0 2006.201.08:49:32.62#ibcon#read 5, iclass 17, count 0 2006.201.08:49:32.62#ibcon#about to read 6, iclass 17, count 0 2006.201.08:49:32.62#ibcon#read 6, iclass 17, count 0 2006.201.08:49:32.62#ibcon#end of sib2, iclass 17, count 0 2006.201.08:49:32.62#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:49:32.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:49:32.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:49:32.62#ibcon#*before write, iclass 17, count 0 2006.201.08:49:32.62#ibcon#enter sib2, iclass 17, count 0 2006.201.08:49:32.62#ibcon#flushed, iclass 17, count 0 2006.201.08:49:32.62#ibcon#about to write, iclass 17, count 0 2006.201.08:49:32.62#ibcon#wrote, iclass 17, count 0 2006.201.08:49:32.62#ibcon#about to read 3, iclass 17, count 0 2006.201.08:49:32.66#ibcon#read 3, iclass 17, count 0 2006.201.08:49:32.66#ibcon#about to read 4, iclass 17, count 0 2006.201.08:49:32.66#ibcon#read 4, iclass 17, count 0 2006.201.08:49:32.66#ibcon#about to read 5, iclass 17, count 0 2006.201.08:49:32.66#ibcon#read 5, iclass 17, count 0 2006.201.08:49:32.66#ibcon#about to read 6, iclass 17, count 0 2006.201.08:49:32.66#ibcon#read 6, iclass 17, count 0 2006.201.08:49:32.66#ibcon#end of sib2, iclass 17, count 0 2006.201.08:49:32.66#ibcon#*after write, iclass 17, count 0 2006.201.08:49:32.66#ibcon#*before return 0, iclass 17, count 0 2006.201.08:49:32.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:32.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:32.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:49:32.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:49:32.66$vck44/vb=1,4 2006.201.08:49:32.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.08:49:32.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.08:49:32.66#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:32.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:49:32.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:49:32.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:49:32.66#ibcon#enter wrdev, iclass 19, count 2 2006.201.08:49:32.66#ibcon#first serial, iclass 19, count 2 2006.201.08:49:32.66#ibcon#enter sib2, iclass 19, count 2 2006.201.08:49:32.66#ibcon#flushed, iclass 19, count 2 2006.201.08:49:32.66#ibcon#about to write, iclass 19, count 2 2006.201.08:49:32.66#ibcon#wrote, iclass 19, count 2 2006.201.08:49:32.66#ibcon#about to read 3, iclass 19, count 2 2006.201.08:49:32.68#ibcon#read 3, iclass 19, count 2 2006.201.08:49:32.68#ibcon#about to read 4, iclass 19, count 2 2006.201.08:49:32.68#ibcon#read 4, iclass 19, count 2 2006.201.08:49:32.68#ibcon#about to read 5, iclass 19, count 2 2006.201.08:49:32.68#ibcon#read 5, iclass 19, count 2 2006.201.08:49:32.68#ibcon#about to read 6, iclass 19, count 2 2006.201.08:49:32.68#ibcon#read 6, iclass 19, count 2 2006.201.08:49:32.68#ibcon#end of sib2, iclass 19, count 2 2006.201.08:49:32.68#ibcon#*mode == 0, iclass 19, count 2 2006.201.08:49:32.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.08:49:32.68#ibcon#[27=AT01-04\r\n] 2006.201.08:49:32.68#ibcon#*before write, iclass 19, count 2 2006.201.08:49:32.68#ibcon#enter sib2, iclass 19, count 2 2006.201.08:49:32.68#ibcon#flushed, iclass 19, count 2 2006.201.08:49:32.68#ibcon#about to write, iclass 19, count 2 2006.201.08:49:32.68#ibcon#wrote, iclass 19, count 2 2006.201.08:49:32.68#ibcon#about to read 3, iclass 19, count 2 2006.201.08:49:32.71#ibcon#read 3, iclass 19, count 2 2006.201.08:49:32.71#ibcon#about to read 4, iclass 19, count 2 2006.201.08:49:32.71#ibcon#read 4, iclass 19, count 2 2006.201.08:49:32.71#ibcon#about to read 5, iclass 19, count 2 2006.201.08:49:32.71#ibcon#read 5, iclass 19, count 2 2006.201.08:49:32.71#ibcon#about to read 6, iclass 19, count 2 2006.201.08:49:32.71#ibcon#read 6, iclass 19, count 2 2006.201.08:49:32.71#ibcon#end of sib2, iclass 19, count 2 2006.201.08:49:32.71#ibcon#*after write, iclass 19, count 2 2006.201.08:49:32.71#ibcon#*before return 0, iclass 19, count 2 2006.201.08:49:32.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:49:32.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.08:49:32.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.08:49:32.71#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:32.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:49:32.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:49:32.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:49:32.83#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:49:32.83#ibcon#first serial, iclass 19, count 0 2006.201.08:49:32.83#ibcon#enter sib2, iclass 19, count 0 2006.201.08:49:32.83#ibcon#flushed, iclass 19, count 0 2006.201.08:49:32.83#ibcon#about to write, iclass 19, count 0 2006.201.08:49:32.83#ibcon#wrote, iclass 19, count 0 2006.201.08:49:32.83#ibcon#about to read 3, iclass 19, count 0 2006.201.08:49:32.85#ibcon#read 3, iclass 19, count 0 2006.201.08:49:32.85#ibcon#about to read 4, iclass 19, count 0 2006.201.08:49:32.85#ibcon#read 4, iclass 19, count 0 2006.201.08:49:32.85#ibcon#about to read 5, iclass 19, count 0 2006.201.08:49:32.85#ibcon#read 5, iclass 19, count 0 2006.201.08:49:32.85#ibcon#about to read 6, iclass 19, count 0 2006.201.08:49:32.85#ibcon#read 6, iclass 19, count 0 2006.201.08:49:32.85#ibcon#end of sib2, iclass 19, count 0 2006.201.08:49:32.85#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:49:32.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:49:32.85#ibcon#[27=USB\r\n] 2006.201.08:49:32.85#ibcon#*before write, iclass 19, count 0 2006.201.08:49:32.85#ibcon#enter sib2, iclass 19, count 0 2006.201.08:49:32.85#ibcon#flushed, iclass 19, count 0 2006.201.08:49:32.85#ibcon#about to write, iclass 19, count 0 2006.201.08:49:32.85#ibcon#wrote, iclass 19, count 0 2006.201.08:49:32.85#ibcon#about to read 3, iclass 19, count 0 2006.201.08:49:32.88#ibcon#read 3, iclass 19, count 0 2006.201.08:49:32.88#ibcon#about to read 4, iclass 19, count 0 2006.201.08:49:32.88#ibcon#read 4, iclass 19, count 0 2006.201.08:49:32.88#ibcon#about to read 5, iclass 19, count 0 2006.201.08:49:32.88#ibcon#read 5, iclass 19, count 0 2006.201.08:49:32.88#ibcon#about to read 6, iclass 19, count 0 2006.201.08:49:32.88#ibcon#read 6, iclass 19, count 0 2006.201.08:49:32.88#ibcon#end of sib2, iclass 19, count 0 2006.201.08:49:32.88#ibcon#*after write, iclass 19, count 0 2006.201.08:49:32.88#ibcon#*before return 0, iclass 19, count 0 2006.201.08:49:32.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:49:32.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.08:49:32.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:49:32.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:49:32.88$vck44/vblo=2,634.99 2006.201.08:49:32.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.08:49:32.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.08:49:32.88#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:32.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:32.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:32.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:32.88#ibcon#enter wrdev, iclass 21, count 0 2006.201.08:49:32.88#ibcon#first serial, iclass 21, count 0 2006.201.08:49:32.88#ibcon#enter sib2, iclass 21, count 0 2006.201.08:49:32.88#ibcon#flushed, iclass 21, count 0 2006.201.08:49:32.88#ibcon#about to write, iclass 21, count 0 2006.201.08:49:32.88#ibcon#wrote, iclass 21, count 0 2006.201.08:49:32.88#ibcon#about to read 3, iclass 21, count 0 2006.201.08:49:32.90#ibcon#read 3, iclass 21, count 0 2006.201.08:49:32.90#ibcon#about to read 4, iclass 21, count 0 2006.201.08:49:32.90#ibcon#read 4, iclass 21, count 0 2006.201.08:49:32.90#ibcon#about to read 5, iclass 21, count 0 2006.201.08:49:32.90#ibcon#read 5, iclass 21, count 0 2006.201.08:49:32.90#ibcon#about to read 6, iclass 21, count 0 2006.201.08:49:32.90#ibcon#read 6, iclass 21, count 0 2006.201.08:49:32.90#ibcon#end of sib2, iclass 21, count 0 2006.201.08:49:32.90#ibcon#*mode == 0, iclass 21, count 0 2006.201.08:49:32.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.08:49:32.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:49:32.90#ibcon#*before write, iclass 21, count 0 2006.201.08:49:32.90#ibcon#enter sib2, iclass 21, count 0 2006.201.08:49:32.90#ibcon#flushed, iclass 21, count 0 2006.201.08:49:32.90#ibcon#about to write, iclass 21, count 0 2006.201.08:49:32.90#ibcon#wrote, iclass 21, count 0 2006.201.08:49:32.90#ibcon#about to read 3, iclass 21, count 0 2006.201.08:49:32.95#ibcon#read 3, iclass 21, count 0 2006.201.08:49:32.95#ibcon#about to read 4, iclass 21, count 0 2006.201.08:49:32.95#ibcon#read 4, iclass 21, count 0 2006.201.08:49:32.95#ibcon#about to read 5, iclass 21, count 0 2006.201.08:49:32.95#ibcon#read 5, iclass 21, count 0 2006.201.08:49:32.95#ibcon#about to read 6, iclass 21, count 0 2006.201.08:49:32.95#ibcon#read 6, iclass 21, count 0 2006.201.08:49:32.95#ibcon#end of sib2, iclass 21, count 0 2006.201.08:49:32.95#ibcon#*after write, iclass 21, count 0 2006.201.08:49:32.95#ibcon#*before return 0, iclass 21, count 0 2006.201.08:49:32.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:32.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.08:49:32.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.08:49:32.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.08:49:32.95$vck44/vb=2,5 2006.201.08:49:32.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.08:49:32.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.08:49:32.95#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:32.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:33.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:33.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:33.00#ibcon#enter wrdev, iclass 23, count 2 2006.201.08:49:33.00#ibcon#first serial, iclass 23, count 2 2006.201.08:49:33.00#ibcon#enter sib2, iclass 23, count 2 2006.201.08:49:33.00#ibcon#flushed, iclass 23, count 2 2006.201.08:49:33.00#ibcon#about to write, iclass 23, count 2 2006.201.08:49:33.00#ibcon#wrote, iclass 23, count 2 2006.201.08:49:33.00#ibcon#about to read 3, iclass 23, count 2 2006.201.08:49:33.02#ibcon#read 3, iclass 23, count 2 2006.201.08:49:33.02#ibcon#about to read 4, iclass 23, count 2 2006.201.08:49:33.02#ibcon#read 4, iclass 23, count 2 2006.201.08:49:33.02#ibcon#about to read 5, iclass 23, count 2 2006.201.08:49:33.02#ibcon#read 5, iclass 23, count 2 2006.201.08:49:33.02#ibcon#about to read 6, iclass 23, count 2 2006.201.08:49:33.02#ibcon#read 6, iclass 23, count 2 2006.201.08:49:33.02#ibcon#end of sib2, iclass 23, count 2 2006.201.08:49:33.02#ibcon#*mode == 0, iclass 23, count 2 2006.201.08:49:33.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.08:49:33.02#ibcon#[27=AT02-05\r\n] 2006.201.08:49:33.02#ibcon#*before write, iclass 23, count 2 2006.201.08:49:33.02#ibcon#enter sib2, iclass 23, count 2 2006.201.08:49:33.02#ibcon#flushed, iclass 23, count 2 2006.201.08:49:33.02#ibcon#about to write, iclass 23, count 2 2006.201.08:49:33.02#ibcon#wrote, iclass 23, count 2 2006.201.08:49:33.02#ibcon#about to read 3, iclass 23, count 2 2006.201.08:49:33.05#ibcon#read 3, iclass 23, count 2 2006.201.08:49:33.05#ibcon#about to read 4, iclass 23, count 2 2006.201.08:49:33.05#ibcon#read 4, iclass 23, count 2 2006.201.08:49:33.05#ibcon#about to read 5, iclass 23, count 2 2006.201.08:49:33.05#ibcon#read 5, iclass 23, count 2 2006.201.08:49:33.05#ibcon#about to read 6, iclass 23, count 2 2006.201.08:49:33.05#ibcon#read 6, iclass 23, count 2 2006.201.08:49:33.05#ibcon#end of sib2, iclass 23, count 2 2006.201.08:49:33.05#ibcon#*after write, iclass 23, count 2 2006.201.08:49:33.05#ibcon#*before return 0, iclass 23, count 2 2006.201.08:49:33.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:33.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.08:49:33.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.08:49:33.05#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:33.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:33.17#abcon#<5=/05 2.6 4.5 23.01 891003.7\r\n> 2006.201.08:49:33.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:33.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:33.17#ibcon#enter wrdev, iclass 23, count 0 2006.201.08:49:33.17#ibcon#first serial, iclass 23, count 0 2006.201.08:49:33.17#ibcon#enter sib2, iclass 23, count 0 2006.201.08:49:33.17#ibcon#flushed, iclass 23, count 0 2006.201.08:49:33.17#ibcon#about to write, iclass 23, count 0 2006.201.08:49:33.17#ibcon#wrote, iclass 23, count 0 2006.201.08:49:33.17#ibcon#about to read 3, iclass 23, count 0 2006.201.08:49:33.19#ibcon#read 3, iclass 23, count 0 2006.201.08:49:33.19#ibcon#about to read 4, iclass 23, count 0 2006.201.08:49:33.19#ibcon#read 4, iclass 23, count 0 2006.201.08:49:33.19#ibcon#about to read 5, iclass 23, count 0 2006.201.08:49:33.19#ibcon#read 5, iclass 23, count 0 2006.201.08:49:33.19#ibcon#about to read 6, iclass 23, count 0 2006.201.08:49:33.19#ibcon#read 6, iclass 23, count 0 2006.201.08:49:33.19#ibcon#end of sib2, iclass 23, count 0 2006.201.08:49:33.19#ibcon#*mode == 0, iclass 23, count 0 2006.201.08:49:33.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.08:49:33.19#ibcon#[27=USB\r\n] 2006.201.08:49:33.19#ibcon#*before write, iclass 23, count 0 2006.201.08:49:33.19#ibcon#enter sib2, iclass 23, count 0 2006.201.08:49:33.19#ibcon#flushed, iclass 23, count 0 2006.201.08:49:33.19#ibcon#about to write, iclass 23, count 0 2006.201.08:49:33.19#ibcon#wrote, iclass 23, count 0 2006.201.08:49:33.19#ibcon#about to read 3, iclass 23, count 0 2006.201.08:49:33.19#abcon#{5=INTERFACE CLEAR} 2006.201.08:49:33.22#ibcon#read 3, iclass 23, count 0 2006.201.08:49:33.22#ibcon#about to read 4, iclass 23, count 0 2006.201.08:49:33.22#ibcon#read 4, iclass 23, count 0 2006.201.08:49:33.22#ibcon#about to read 5, iclass 23, count 0 2006.201.08:49:33.22#ibcon#read 5, iclass 23, count 0 2006.201.08:49:33.22#ibcon#about to read 6, iclass 23, count 0 2006.201.08:49:33.22#ibcon#read 6, iclass 23, count 0 2006.201.08:49:33.22#ibcon#end of sib2, iclass 23, count 0 2006.201.08:49:33.22#ibcon#*after write, iclass 23, count 0 2006.201.08:49:33.22#ibcon#*before return 0, iclass 23, count 0 2006.201.08:49:33.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:33.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.08:49:33.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.08:49:33.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.08:49:33.22$vck44/vblo=3,649.99 2006.201.08:49:33.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.08:49:33.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.08:49:33.22#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:33.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:49:33.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:49:33.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:49:33.22#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:49:33.22#ibcon#first serial, iclass 28, count 0 2006.201.08:49:33.22#ibcon#enter sib2, iclass 28, count 0 2006.201.08:49:33.22#ibcon#flushed, iclass 28, count 0 2006.201.08:49:33.22#ibcon#about to write, iclass 28, count 0 2006.201.08:49:33.22#ibcon#wrote, iclass 28, count 0 2006.201.08:49:33.22#ibcon#about to read 3, iclass 28, count 0 2006.201.08:49:33.24#ibcon#read 3, iclass 28, count 0 2006.201.08:49:33.24#ibcon#about to read 4, iclass 28, count 0 2006.201.08:49:33.24#ibcon#read 4, iclass 28, count 0 2006.201.08:49:33.24#ibcon#about to read 5, iclass 28, count 0 2006.201.08:49:33.24#ibcon#read 5, iclass 28, count 0 2006.201.08:49:33.24#ibcon#about to read 6, iclass 28, count 0 2006.201.08:49:33.24#ibcon#read 6, iclass 28, count 0 2006.201.08:49:33.24#ibcon#end of sib2, iclass 28, count 0 2006.201.08:49:33.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:49:33.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:49:33.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:49:33.24#ibcon#*before write, iclass 28, count 0 2006.201.08:49:33.24#ibcon#enter sib2, iclass 28, count 0 2006.201.08:49:33.24#ibcon#flushed, iclass 28, count 0 2006.201.08:49:33.24#ibcon#about to write, iclass 28, count 0 2006.201.08:49:33.24#ibcon#wrote, iclass 28, count 0 2006.201.08:49:33.24#ibcon#about to read 3, iclass 28, count 0 2006.201.08:49:33.25#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:49:33.28#ibcon#read 3, iclass 28, count 0 2006.201.08:49:33.28#ibcon#about to read 4, iclass 28, count 0 2006.201.08:49:33.28#ibcon#read 4, iclass 28, count 0 2006.201.08:49:33.28#ibcon#about to read 5, iclass 28, count 0 2006.201.08:49:33.28#ibcon#read 5, iclass 28, count 0 2006.201.08:49:33.28#ibcon#about to read 6, iclass 28, count 0 2006.201.08:49:33.28#ibcon#read 6, iclass 28, count 0 2006.201.08:49:33.28#ibcon#end of sib2, iclass 28, count 0 2006.201.08:49:33.28#ibcon#*after write, iclass 28, count 0 2006.201.08:49:33.28#ibcon#*before return 0, iclass 28, count 0 2006.201.08:49:33.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:49:33.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:49:33.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:49:33.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:49:33.28$vck44/vb=3,4 2006.201.08:49:33.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.08:49:33.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.08:49:33.28#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:33.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:33.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:33.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:33.34#ibcon#enter wrdev, iclass 31, count 2 2006.201.08:49:33.34#ibcon#first serial, iclass 31, count 2 2006.201.08:49:33.34#ibcon#enter sib2, iclass 31, count 2 2006.201.08:49:33.34#ibcon#flushed, iclass 31, count 2 2006.201.08:49:33.34#ibcon#about to write, iclass 31, count 2 2006.201.08:49:33.34#ibcon#wrote, iclass 31, count 2 2006.201.08:49:33.34#ibcon#about to read 3, iclass 31, count 2 2006.201.08:49:33.36#ibcon#read 3, iclass 31, count 2 2006.201.08:49:33.36#ibcon#about to read 4, iclass 31, count 2 2006.201.08:49:33.36#ibcon#read 4, iclass 31, count 2 2006.201.08:49:33.36#ibcon#about to read 5, iclass 31, count 2 2006.201.08:49:33.36#ibcon#read 5, iclass 31, count 2 2006.201.08:49:33.36#ibcon#about to read 6, iclass 31, count 2 2006.201.08:49:33.36#ibcon#read 6, iclass 31, count 2 2006.201.08:49:33.36#ibcon#end of sib2, iclass 31, count 2 2006.201.08:49:33.36#ibcon#*mode == 0, iclass 31, count 2 2006.201.08:49:33.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.08:49:33.36#ibcon#[27=AT03-04\r\n] 2006.201.08:49:33.36#ibcon#*before write, iclass 31, count 2 2006.201.08:49:33.36#ibcon#enter sib2, iclass 31, count 2 2006.201.08:49:33.36#ibcon#flushed, iclass 31, count 2 2006.201.08:49:33.36#ibcon#about to write, iclass 31, count 2 2006.201.08:49:33.36#ibcon#wrote, iclass 31, count 2 2006.201.08:49:33.36#ibcon#about to read 3, iclass 31, count 2 2006.201.08:49:33.39#ibcon#read 3, iclass 31, count 2 2006.201.08:49:33.39#ibcon#about to read 4, iclass 31, count 2 2006.201.08:49:33.39#ibcon#read 4, iclass 31, count 2 2006.201.08:49:33.39#ibcon#about to read 5, iclass 31, count 2 2006.201.08:49:33.39#ibcon#read 5, iclass 31, count 2 2006.201.08:49:33.39#ibcon#about to read 6, iclass 31, count 2 2006.201.08:49:33.39#ibcon#read 6, iclass 31, count 2 2006.201.08:49:33.39#ibcon#end of sib2, iclass 31, count 2 2006.201.08:49:33.39#ibcon#*after write, iclass 31, count 2 2006.201.08:49:33.39#ibcon#*before return 0, iclass 31, count 2 2006.201.08:49:33.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:33.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.08:49:33.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.08:49:33.39#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:33.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:33.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:33.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:33.51#ibcon#enter wrdev, iclass 31, count 0 2006.201.08:49:33.51#ibcon#first serial, iclass 31, count 0 2006.201.08:49:33.51#ibcon#enter sib2, iclass 31, count 0 2006.201.08:49:33.51#ibcon#flushed, iclass 31, count 0 2006.201.08:49:33.51#ibcon#about to write, iclass 31, count 0 2006.201.08:49:33.51#ibcon#wrote, iclass 31, count 0 2006.201.08:49:33.51#ibcon#about to read 3, iclass 31, count 0 2006.201.08:49:33.53#ibcon#read 3, iclass 31, count 0 2006.201.08:49:33.53#ibcon#about to read 4, iclass 31, count 0 2006.201.08:49:33.53#ibcon#read 4, iclass 31, count 0 2006.201.08:49:33.53#ibcon#about to read 5, iclass 31, count 0 2006.201.08:49:33.53#ibcon#read 5, iclass 31, count 0 2006.201.08:49:33.53#ibcon#about to read 6, iclass 31, count 0 2006.201.08:49:33.53#ibcon#read 6, iclass 31, count 0 2006.201.08:49:33.53#ibcon#end of sib2, iclass 31, count 0 2006.201.08:49:33.53#ibcon#*mode == 0, iclass 31, count 0 2006.201.08:49:33.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.08:49:33.53#ibcon#[27=USB\r\n] 2006.201.08:49:33.53#ibcon#*before write, iclass 31, count 0 2006.201.08:49:33.53#ibcon#enter sib2, iclass 31, count 0 2006.201.08:49:33.53#ibcon#flushed, iclass 31, count 0 2006.201.08:49:33.53#ibcon#about to write, iclass 31, count 0 2006.201.08:49:33.53#ibcon#wrote, iclass 31, count 0 2006.201.08:49:33.53#ibcon#about to read 3, iclass 31, count 0 2006.201.08:49:33.56#ibcon#read 3, iclass 31, count 0 2006.201.08:49:33.56#ibcon#about to read 4, iclass 31, count 0 2006.201.08:49:33.56#ibcon#read 4, iclass 31, count 0 2006.201.08:49:33.56#ibcon#about to read 5, iclass 31, count 0 2006.201.08:49:33.56#ibcon#read 5, iclass 31, count 0 2006.201.08:49:33.56#ibcon#about to read 6, iclass 31, count 0 2006.201.08:49:33.56#ibcon#read 6, iclass 31, count 0 2006.201.08:49:33.56#ibcon#end of sib2, iclass 31, count 0 2006.201.08:49:33.56#ibcon#*after write, iclass 31, count 0 2006.201.08:49:33.56#ibcon#*before return 0, iclass 31, count 0 2006.201.08:49:33.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:33.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.08:49:33.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.08:49:33.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.08:49:33.56$vck44/vblo=4,679.99 2006.201.08:49:33.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.08:49:33.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.08:49:33.56#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:33.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:33.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:33.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:33.56#ibcon#enter wrdev, iclass 33, count 0 2006.201.08:49:33.56#ibcon#first serial, iclass 33, count 0 2006.201.08:49:33.56#ibcon#enter sib2, iclass 33, count 0 2006.201.08:49:33.56#ibcon#flushed, iclass 33, count 0 2006.201.08:49:33.56#ibcon#about to write, iclass 33, count 0 2006.201.08:49:33.56#ibcon#wrote, iclass 33, count 0 2006.201.08:49:33.56#ibcon#about to read 3, iclass 33, count 0 2006.201.08:49:33.58#ibcon#read 3, iclass 33, count 0 2006.201.08:49:33.58#ibcon#about to read 4, iclass 33, count 0 2006.201.08:49:33.58#ibcon#read 4, iclass 33, count 0 2006.201.08:49:33.58#ibcon#about to read 5, iclass 33, count 0 2006.201.08:49:33.58#ibcon#read 5, iclass 33, count 0 2006.201.08:49:33.58#ibcon#about to read 6, iclass 33, count 0 2006.201.08:49:33.58#ibcon#read 6, iclass 33, count 0 2006.201.08:49:33.58#ibcon#end of sib2, iclass 33, count 0 2006.201.08:49:33.58#ibcon#*mode == 0, iclass 33, count 0 2006.201.08:49:33.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.08:49:33.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:49:33.58#ibcon#*before write, iclass 33, count 0 2006.201.08:49:33.58#ibcon#enter sib2, iclass 33, count 0 2006.201.08:49:33.58#ibcon#flushed, iclass 33, count 0 2006.201.08:49:33.58#ibcon#about to write, iclass 33, count 0 2006.201.08:49:33.58#ibcon#wrote, iclass 33, count 0 2006.201.08:49:33.58#ibcon#about to read 3, iclass 33, count 0 2006.201.08:49:33.63#ibcon#read 3, iclass 33, count 0 2006.201.08:49:33.63#ibcon#about to read 4, iclass 33, count 0 2006.201.08:49:33.63#ibcon#read 4, iclass 33, count 0 2006.201.08:49:33.63#ibcon#about to read 5, iclass 33, count 0 2006.201.08:49:33.63#ibcon#read 5, iclass 33, count 0 2006.201.08:49:33.63#ibcon#about to read 6, iclass 33, count 0 2006.201.08:49:33.63#ibcon#read 6, iclass 33, count 0 2006.201.08:49:33.63#ibcon#end of sib2, iclass 33, count 0 2006.201.08:49:33.63#ibcon#*after write, iclass 33, count 0 2006.201.08:49:33.63#ibcon#*before return 0, iclass 33, count 0 2006.201.08:49:33.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:33.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.08:49:33.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.08:49:33.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.08:49:33.63$vck44/vb=4,5 2006.201.08:49:33.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.08:49:33.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.08:49:33.63#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:33.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:33.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:33.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:33.68#ibcon#enter wrdev, iclass 35, count 2 2006.201.08:49:33.68#ibcon#first serial, iclass 35, count 2 2006.201.08:49:33.68#ibcon#enter sib2, iclass 35, count 2 2006.201.08:49:33.68#ibcon#flushed, iclass 35, count 2 2006.201.08:49:33.68#ibcon#about to write, iclass 35, count 2 2006.201.08:49:33.68#ibcon#wrote, iclass 35, count 2 2006.201.08:49:33.68#ibcon#about to read 3, iclass 35, count 2 2006.201.08:49:33.70#ibcon#read 3, iclass 35, count 2 2006.201.08:49:33.70#ibcon#about to read 4, iclass 35, count 2 2006.201.08:49:33.70#ibcon#read 4, iclass 35, count 2 2006.201.08:49:33.70#ibcon#about to read 5, iclass 35, count 2 2006.201.08:49:33.70#ibcon#read 5, iclass 35, count 2 2006.201.08:49:33.70#ibcon#about to read 6, iclass 35, count 2 2006.201.08:49:33.70#ibcon#read 6, iclass 35, count 2 2006.201.08:49:33.70#ibcon#end of sib2, iclass 35, count 2 2006.201.08:49:33.70#ibcon#*mode == 0, iclass 35, count 2 2006.201.08:49:33.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.08:49:33.70#ibcon#[27=AT04-05\r\n] 2006.201.08:49:33.70#ibcon#*before write, iclass 35, count 2 2006.201.08:49:33.70#ibcon#enter sib2, iclass 35, count 2 2006.201.08:49:33.70#ibcon#flushed, iclass 35, count 2 2006.201.08:49:33.70#ibcon#about to write, iclass 35, count 2 2006.201.08:49:33.70#ibcon#wrote, iclass 35, count 2 2006.201.08:49:33.70#ibcon#about to read 3, iclass 35, count 2 2006.201.08:49:33.73#ibcon#read 3, iclass 35, count 2 2006.201.08:49:33.73#ibcon#about to read 4, iclass 35, count 2 2006.201.08:49:33.73#ibcon#read 4, iclass 35, count 2 2006.201.08:49:33.73#ibcon#about to read 5, iclass 35, count 2 2006.201.08:49:33.73#ibcon#read 5, iclass 35, count 2 2006.201.08:49:33.73#ibcon#about to read 6, iclass 35, count 2 2006.201.08:49:33.73#ibcon#read 6, iclass 35, count 2 2006.201.08:49:33.73#ibcon#end of sib2, iclass 35, count 2 2006.201.08:49:33.73#ibcon#*after write, iclass 35, count 2 2006.201.08:49:33.73#ibcon#*before return 0, iclass 35, count 2 2006.201.08:49:33.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:33.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.08:49:33.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.08:49:33.73#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:33.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:33.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:33.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:33.85#ibcon#enter wrdev, iclass 35, count 0 2006.201.08:49:33.85#ibcon#first serial, iclass 35, count 0 2006.201.08:49:33.85#ibcon#enter sib2, iclass 35, count 0 2006.201.08:49:33.85#ibcon#flushed, iclass 35, count 0 2006.201.08:49:33.85#ibcon#about to write, iclass 35, count 0 2006.201.08:49:33.85#ibcon#wrote, iclass 35, count 0 2006.201.08:49:33.85#ibcon#about to read 3, iclass 35, count 0 2006.201.08:49:33.87#ibcon#read 3, iclass 35, count 0 2006.201.08:49:33.87#ibcon#about to read 4, iclass 35, count 0 2006.201.08:49:33.87#ibcon#read 4, iclass 35, count 0 2006.201.08:49:33.87#ibcon#about to read 5, iclass 35, count 0 2006.201.08:49:33.87#ibcon#read 5, iclass 35, count 0 2006.201.08:49:33.87#ibcon#about to read 6, iclass 35, count 0 2006.201.08:49:33.87#ibcon#read 6, iclass 35, count 0 2006.201.08:49:33.87#ibcon#end of sib2, iclass 35, count 0 2006.201.08:49:33.87#ibcon#*mode == 0, iclass 35, count 0 2006.201.08:49:33.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.08:49:33.87#ibcon#[27=USB\r\n] 2006.201.08:49:33.87#ibcon#*before write, iclass 35, count 0 2006.201.08:49:33.87#ibcon#enter sib2, iclass 35, count 0 2006.201.08:49:33.87#ibcon#flushed, iclass 35, count 0 2006.201.08:49:33.87#ibcon#about to write, iclass 35, count 0 2006.201.08:49:33.87#ibcon#wrote, iclass 35, count 0 2006.201.08:49:33.87#ibcon#about to read 3, iclass 35, count 0 2006.201.08:49:33.90#ibcon#read 3, iclass 35, count 0 2006.201.08:49:33.90#ibcon#about to read 4, iclass 35, count 0 2006.201.08:49:33.90#ibcon#read 4, iclass 35, count 0 2006.201.08:49:33.90#ibcon#about to read 5, iclass 35, count 0 2006.201.08:49:33.90#ibcon#read 5, iclass 35, count 0 2006.201.08:49:33.90#ibcon#about to read 6, iclass 35, count 0 2006.201.08:49:33.90#ibcon#read 6, iclass 35, count 0 2006.201.08:49:33.90#ibcon#end of sib2, iclass 35, count 0 2006.201.08:49:33.90#ibcon#*after write, iclass 35, count 0 2006.201.08:49:33.90#ibcon#*before return 0, iclass 35, count 0 2006.201.08:49:33.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:33.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.08:49:33.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.08:49:33.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.08:49:33.90$vck44/vblo=5,709.99 2006.201.08:49:33.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.08:49:33.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.08:49:33.90#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:33.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:33.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:33.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:33.90#ibcon#enter wrdev, iclass 37, count 0 2006.201.08:49:33.90#ibcon#first serial, iclass 37, count 0 2006.201.08:49:33.90#ibcon#enter sib2, iclass 37, count 0 2006.201.08:49:33.90#ibcon#flushed, iclass 37, count 0 2006.201.08:49:33.90#ibcon#about to write, iclass 37, count 0 2006.201.08:49:33.90#ibcon#wrote, iclass 37, count 0 2006.201.08:49:33.90#ibcon#about to read 3, iclass 37, count 0 2006.201.08:49:33.92#ibcon#read 3, iclass 37, count 0 2006.201.08:49:33.92#ibcon#about to read 4, iclass 37, count 0 2006.201.08:49:33.92#ibcon#read 4, iclass 37, count 0 2006.201.08:49:33.92#ibcon#about to read 5, iclass 37, count 0 2006.201.08:49:33.92#ibcon#read 5, iclass 37, count 0 2006.201.08:49:33.92#ibcon#about to read 6, iclass 37, count 0 2006.201.08:49:33.92#ibcon#read 6, iclass 37, count 0 2006.201.08:49:33.92#ibcon#end of sib2, iclass 37, count 0 2006.201.08:49:33.92#ibcon#*mode == 0, iclass 37, count 0 2006.201.08:49:33.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.08:49:33.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:49:33.92#ibcon#*before write, iclass 37, count 0 2006.201.08:49:33.92#ibcon#enter sib2, iclass 37, count 0 2006.201.08:49:33.92#ibcon#flushed, iclass 37, count 0 2006.201.08:49:33.92#ibcon#about to write, iclass 37, count 0 2006.201.08:49:33.92#ibcon#wrote, iclass 37, count 0 2006.201.08:49:33.92#ibcon#about to read 3, iclass 37, count 0 2006.201.08:49:33.96#ibcon#read 3, iclass 37, count 0 2006.201.08:49:33.96#ibcon#about to read 4, iclass 37, count 0 2006.201.08:49:33.96#ibcon#read 4, iclass 37, count 0 2006.201.08:49:33.96#ibcon#about to read 5, iclass 37, count 0 2006.201.08:49:33.96#ibcon#read 5, iclass 37, count 0 2006.201.08:49:33.96#ibcon#about to read 6, iclass 37, count 0 2006.201.08:49:33.96#ibcon#read 6, iclass 37, count 0 2006.201.08:49:33.96#ibcon#end of sib2, iclass 37, count 0 2006.201.08:49:33.96#ibcon#*after write, iclass 37, count 0 2006.201.08:49:33.96#ibcon#*before return 0, iclass 37, count 0 2006.201.08:49:33.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:33.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.08:49:33.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.08:49:33.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.08:49:33.96$vck44/vb=5,4 2006.201.08:49:33.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.08:49:33.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.08:49:33.96#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:33.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:34.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:34.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:34.02#ibcon#enter wrdev, iclass 39, count 2 2006.201.08:49:34.02#ibcon#first serial, iclass 39, count 2 2006.201.08:49:34.02#ibcon#enter sib2, iclass 39, count 2 2006.201.08:49:34.02#ibcon#flushed, iclass 39, count 2 2006.201.08:49:34.02#ibcon#about to write, iclass 39, count 2 2006.201.08:49:34.02#ibcon#wrote, iclass 39, count 2 2006.201.08:49:34.02#ibcon#about to read 3, iclass 39, count 2 2006.201.08:49:34.04#ibcon#read 3, iclass 39, count 2 2006.201.08:49:34.04#ibcon#about to read 4, iclass 39, count 2 2006.201.08:49:34.04#ibcon#read 4, iclass 39, count 2 2006.201.08:49:34.04#ibcon#about to read 5, iclass 39, count 2 2006.201.08:49:34.04#ibcon#read 5, iclass 39, count 2 2006.201.08:49:34.04#ibcon#about to read 6, iclass 39, count 2 2006.201.08:49:34.04#ibcon#read 6, iclass 39, count 2 2006.201.08:49:34.04#ibcon#end of sib2, iclass 39, count 2 2006.201.08:49:34.04#ibcon#*mode == 0, iclass 39, count 2 2006.201.08:49:34.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.08:49:34.04#ibcon#[27=AT05-04\r\n] 2006.201.08:49:34.04#ibcon#*before write, iclass 39, count 2 2006.201.08:49:34.04#ibcon#enter sib2, iclass 39, count 2 2006.201.08:49:34.04#ibcon#flushed, iclass 39, count 2 2006.201.08:49:34.04#ibcon#about to write, iclass 39, count 2 2006.201.08:49:34.04#ibcon#wrote, iclass 39, count 2 2006.201.08:49:34.04#ibcon#about to read 3, iclass 39, count 2 2006.201.08:49:34.07#ibcon#read 3, iclass 39, count 2 2006.201.08:49:34.07#ibcon#about to read 4, iclass 39, count 2 2006.201.08:49:34.07#ibcon#read 4, iclass 39, count 2 2006.201.08:49:34.07#ibcon#about to read 5, iclass 39, count 2 2006.201.08:49:34.07#ibcon#read 5, iclass 39, count 2 2006.201.08:49:34.07#ibcon#about to read 6, iclass 39, count 2 2006.201.08:49:34.07#ibcon#read 6, iclass 39, count 2 2006.201.08:49:34.07#ibcon#end of sib2, iclass 39, count 2 2006.201.08:49:34.07#ibcon#*after write, iclass 39, count 2 2006.201.08:49:34.07#ibcon#*before return 0, iclass 39, count 2 2006.201.08:49:34.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:34.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.08:49:34.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.08:49:34.07#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:34.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:34.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:34.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:34.19#ibcon#enter wrdev, iclass 39, count 0 2006.201.08:49:34.19#ibcon#first serial, iclass 39, count 0 2006.201.08:49:34.19#ibcon#enter sib2, iclass 39, count 0 2006.201.08:49:34.19#ibcon#flushed, iclass 39, count 0 2006.201.08:49:34.19#ibcon#about to write, iclass 39, count 0 2006.201.08:49:34.19#ibcon#wrote, iclass 39, count 0 2006.201.08:49:34.19#ibcon#about to read 3, iclass 39, count 0 2006.201.08:49:34.21#ibcon#read 3, iclass 39, count 0 2006.201.08:49:34.21#ibcon#about to read 4, iclass 39, count 0 2006.201.08:49:34.21#ibcon#read 4, iclass 39, count 0 2006.201.08:49:34.21#ibcon#about to read 5, iclass 39, count 0 2006.201.08:49:34.21#ibcon#read 5, iclass 39, count 0 2006.201.08:49:34.21#ibcon#about to read 6, iclass 39, count 0 2006.201.08:49:34.21#ibcon#read 6, iclass 39, count 0 2006.201.08:49:34.21#ibcon#end of sib2, iclass 39, count 0 2006.201.08:49:34.21#ibcon#*mode == 0, iclass 39, count 0 2006.201.08:49:34.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.08:49:34.21#ibcon#[27=USB\r\n] 2006.201.08:49:34.21#ibcon#*before write, iclass 39, count 0 2006.201.08:49:34.21#ibcon#enter sib2, iclass 39, count 0 2006.201.08:49:34.21#ibcon#flushed, iclass 39, count 0 2006.201.08:49:34.21#ibcon#about to write, iclass 39, count 0 2006.201.08:49:34.21#ibcon#wrote, iclass 39, count 0 2006.201.08:49:34.21#ibcon#about to read 3, iclass 39, count 0 2006.201.08:49:34.24#ibcon#read 3, iclass 39, count 0 2006.201.08:49:34.24#ibcon#about to read 4, iclass 39, count 0 2006.201.08:49:34.24#ibcon#read 4, iclass 39, count 0 2006.201.08:49:34.24#ibcon#about to read 5, iclass 39, count 0 2006.201.08:49:34.24#ibcon#read 5, iclass 39, count 0 2006.201.08:49:34.24#ibcon#about to read 6, iclass 39, count 0 2006.201.08:49:34.24#ibcon#read 6, iclass 39, count 0 2006.201.08:49:34.24#ibcon#end of sib2, iclass 39, count 0 2006.201.08:49:34.24#ibcon#*after write, iclass 39, count 0 2006.201.08:49:34.24#ibcon#*before return 0, iclass 39, count 0 2006.201.08:49:34.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:34.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.08:49:34.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.08:49:34.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.08:49:34.24$vck44/vblo=6,719.99 2006.201.08:49:34.24#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.08:49:34.24#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.08:49:34.24#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:34.24#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:34.24#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:34.24#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:34.24#ibcon#enter wrdev, iclass 2, count 0 2006.201.08:49:34.24#ibcon#first serial, iclass 2, count 0 2006.201.08:49:34.24#ibcon#enter sib2, iclass 2, count 0 2006.201.08:49:34.24#ibcon#flushed, iclass 2, count 0 2006.201.08:49:34.24#ibcon#about to write, iclass 2, count 0 2006.201.08:49:34.24#ibcon#wrote, iclass 2, count 0 2006.201.08:49:34.24#ibcon#about to read 3, iclass 2, count 0 2006.201.08:49:34.26#ibcon#read 3, iclass 2, count 0 2006.201.08:49:34.26#ibcon#about to read 4, iclass 2, count 0 2006.201.08:49:34.26#ibcon#read 4, iclass 2, count 0 2006.201.08:49:34.26#ibcon#about to read 5, iclass 2, count 0 2006.201.08:49:34.26#ibcon#read 5, iclass 2, count 0 2006.201.08:49:34.26#ibcon#about to read 6, iclass 2, count 0 2006.201.08:49:34.26#ibcon#read 6, iclass 2, count 0 2006.201.08:49:34.26#ibcon#end of sib2, iclass 2, count 0 2006.201.08:49:34.26#ibcon#*mode == 0, iclass 2, count 0 2006.201.08:49:34.26#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.08:49:34.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:49:34.26#ibcon#*before write, iclass 2, count 0 2006.201.08:49:34.26#ibcon#enter sib2, iclass 2, count 0 2006.201.08:49:34.26#ibcon#flushed, iclass 2, count 0 2006.201.08:49:34.26#ibcon#about to write, iclass 2, count 0 2006.201.08:49:34.26#ibcon#wrote, iclass 2, count 0 2006.201.08:49:34.26#ibcon#about to read 3, iclass 2, count 0 2006.201.08:49:34.30#ibcon#read 3, iclass 2, count 0 2006.201.08:49:34.30#ibcon#about to read 4, iclass 2, count 0 2006.201.08:49:34.30#ibcon#read 4, iclass 2, count 0 2006.201.08:49:34.30#ibcon#about to read 5, iclass 2, count 0 2006.201.08:49:34.30#ibcon#read 5, iclass 2, count 0 2006.201.08:49:34.30#ibcon#about to read 6, iclass 2, count 0 2006.201.08:49:34.30#ibcon#read 6, iclass 2, count 0 2006.201.08:49:34.30#ibcon#end of sib2, iclass 2, count 0 2006.201.08:49:34.30#ibcon#*after write, iclass 2, count 0 2006.201.08:49:34.30#ibcon#*before return 0, iclass 2, count 0 2006.201.08:49:34.30#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:34.30#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.08:49:34.30#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.08:49:34.30#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.08:49:34.30$vck44/vb=6,4 2006.201.08:49:34.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.08:49:34.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.08:49:34.30#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:34.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:34.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:34.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:34.36#ibcon#enter wrdev, iclass 5, count 2 2006.201.08:49:34.36#ibcon#first serial, iclass 5, count 2 2006.201.08:49:34.36#ibcon#enter sib2, iclass 5, count 2 2006.201.08:49:34.36#ibcon#flushed, iclass 5, count 2 2006.201.08:49:34.36#ibcon#about to write, iclass 5, count 2 2006.201.08:49:34.36#ibcon#wrote, iclass 5, count 2 2006.201.08:49:34.36#ibcon#about to read 3, iclass 5, count 2 2006.201.08:49:34.38#ibcon#read 3, iclass 5, count 2 2006.201.08:49:34.38#ibcon#about to read 4, iclass 5, count 2 2006.201.08:49:34.38#ibcon#read 4, iclass 5, count 2 2006.201.08:49:34.38#ibcon#about to read 5, iclass 5, count 2 2006.201.08:49:34.38#ibcon#read 5, iclass 5, count 2 2006.201.08:49:34.38#ibcon#about to read 6, iclass 5, count 2 2006.201.08:49:34.38#ibcon#read 6, iclass 5, count 2 2006.201.08:49:34.38#ibcon#end of sib2, iclass 5, count 2 2006.201.08:49:34.38#ibcon#*mode == 0, iclass 5, count 2 2006.201.08:49:34.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.08:49:34.38#ibcon#[27=AT06-04\r\n] 2006.201.08:49:34.38#ibcon#*before write, iclass 5, count 2 2006.201.08:49:34.38#ibcon#enter sib2, iclass 5, count 2 2006.201.08:49:34.38#ibcon#flushed, iclass 5, count 2 2006.201.08:49:34.38#ibcon#about to write, iclass 5, count 2 2006.201.08:49:34.38#ibcon#wrote, iclass 5, count 2 2006.201.08:49:34.38#ibcon#about to read 3, iclass 5, count 2 2006.201.08:49:34.41#ibcon#read 3, iclass 5, count 2 2006.201.08:49:34.41#ibcon#about to read 4, iclass 5, count 2 2006.201.08:49:34.41#ibcon#read 4, iclass 5, count 2 2006.201.08:49:34.41#ibcon#about to read 5, iclass 5, count 2 2006.201.08:49:34.41#ibcon#read 5, iclass 5, count 2 2006.201.08:49:34.41#ibcon#about to read 6, iclass 5, count 2 2006.201.08:49:34.41#ibcon#read 6, iclass 5, count 2 2006.201.08:49:34.41#ibcon#end of sib2, iclass 5, count 2 2006.201.08:49:34.41#ibcon#*after write, iclass 5, count 2 2006.201.08:49:34.41#ibcon#*before return 0, iclass 5, count 2 2006.201.08:49:34.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:34.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.08:49:34.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.08:49:34.41#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:34.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:34.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:34.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:34.53#ibcon#enter wrdev, iclass 5, count 0 2006.201.08:49:34.53#ibcon#first serial, iclass 5, count 0 2006.201.08:49:34.53#ibcon#enter sib2, iclass 5, count 0 2006.201.08:49:34.53#ibcon#flushed, iclass 5, count 0 2006.201.08:49:34.53#ibcon#about to write, iclass 5, count 0 2006.201.08:49:34.53#ibcon#wrote, iclass 5, count 0 2006.201.08:49:34.53#ibcon#about to read 3, iclass 5, count 0 2006.201.08:49:34.55#ibcon#read 3, iclass 5, count 0 2006.201.08:49:34.55#ibcon#about to read 4, iclass 5, count 0 2006.201.08:49:34.55#ibcon#read 4, iclass 5, count 0 2006.201.08:49:34.55#ibcon#about to read 5, iclass 5, count 0 2006.201.08:49:34.55#ibcon#read 5, iclass 5, count 0 2006.201.08:49:34.55#ibcon#about to read 6, iclass 5, count 0 2006.201.08:49:34.55#ibcon#read 6, iclass 5, count 0 2006.201.08:49:34.55#ibcon#end of sib2, iclass 5, count 0 2006.201.08:49:34.55#ibcon#*mode == 0, iclass 5, count 0 2006.201.08:49:34.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.08:49:34.55#ibcon#[27=USB\r\n] 2006.201.08:49:34.55#ibcon#*before write, iclass 5, count 0 2006.201.08:49:34.55#ibcon#enter sib2, iclass 5, count 0 2006.201.08:49:34.55#ibcon#flushed, iclass 5, count 0 2006.201.08:49:34.55#ibcon#about to write, iclass 5, count 0 2006.201.08:49:34.55#ibcon#wrote, iclass 5, count 0 2006.201.08:49:34.55#ibcon#about to read 3, iclass 5, count 0 2006.201.08:49:34.58#ibcon#read 3, iclass 5, count 0 2006.201.08:49:34.58#ibcon#about to read 4, iclass 5, count 0 2006.201.08:49:34.58#ibcon#read 4, iclass 5, count 0 2006.201.08:49:34.58#ibcon#about to read 5, iclass 5, count 0 2006.201.08:49:34.58#ibcon#read 5, iclass 5, count 0 2006.201.08:49:34.58#ibcon#about to read 6, iclass 5, count 0 2006.201.08:49:34.58#ibcon#read 6, iclass 5, count 0 2006.201.08:49:34.58#ibcon#end of sib2, iclass 5, count 0 2006.201.08:49:34.58#ibcon#*after write, iclass 5, count 0 2006.201.08:49:34.58#ibcon#*before return 0, iclass 5, count 0 2006.201.08:49:34.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:34.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.08:49:34.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.08:49:34.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.08:49:34.58$vck44/vblo=7,734.99 2006.201.08:49:34.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.08:49:34.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.08:49:34.58#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:34.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:34.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:34.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:34.58#ibcon#enter wrdev, iclass 7, count 0 2006.201.08:49:34.58#ibcon#first serial, iclass 7, count 0 2006.201.08:49:34.58#ibcon#enter sib2, iclass 7, count 0 2006.201.08:49:34.58#ibcon#flushed, iclass 7, count 0 2006.201.08:49:34.58#ibcon#about to write, iclass 7, count 0 2006.201.08:49:34.58#ibcon#wrote, iclass 7, count 0 2006.201.08:49:34.58#ibcon#about to read 3, iclass 7, count 0 2006.201.08:49:34.60#ibcon#read 3, iclass 7, count 0 2006.201.08:49:34.60#ibcon#about to read 4, iclass 7, count 0 2006.201.08:49:34.60#ibcon#read 4, iclass 7, count 0 2006.201.08:49:34.60#ibcon#about to read 5, iclass 7, count 0 2006.201.08:49:34.60#ibcon#read 5, iclass 7, count 0 2006.201.08:49:34.60#ibcon#about to read 6, iclass 7, count 0 2006.201.08:49:34.60#ibcon#read 6, iclass 7, count 0 2006.201.08:49:34.60#ibcon#end of sib2, iclass 7, count 0 2006.201.08:49:34.60#ibcon#*mode == 0, iclass 7, count 0 2006.201.08:49:34.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.08:49:34.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:49:34.60#ibcon#*before write, iclass 7, count 0 2006.201.08:49:34.60#ibcon#enter sib2, iclass 7, count 0 2006.201.08:49:34.60#ibcon#flushed, iclass 7, count 0 2006.201.08:49:34.60#ibcon#about to write, iclass 7, count 0 2006.201.08:49:34.60#ibcon#wrote, iclass 7, count 0 2006.201.08:49:34.60#ibcon#about to read 3, iclass 7, count 0 2006.201.08:49:34.65#ibcon#read 3, iclass 7, count 0 2006.201.08:49:34.65#ibcon#about to read 4, iclass 7, count 0 2006.201.08:49:34.65#ibcon#read 4, iclass 7, count 0 2006.201.08:49:34.65#ibcon#about to read 5, iclass 7, count 0 2006.201.08:49:34.65#ibcon#read 5, iclass 7, count 0 2006.201.08:49:34.65#ibcon#about to read 6, iclass 7, count 0 2006.201.08:49:34.65#ibcon#read 6, iclass 7, count 0 2006.201.08:49:34.65#ibcon#end of sib2, iclass 7, count 0 2006.201.08:49:34.65#ibcon#*after write, iclass 7, count 0 2006.201.08:49:34.65#ibcon#*before return 0, iclass 7, count 0 2006.201.08:49:34.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:34.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.08:49:34.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.08:49:34.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.08:49:34.65$vck44/vb=7,4 2006.201.08:49:34.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.08:49:34.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.08:49:34.65#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:34.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:34.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:34.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:34.70#ibcon#enter wrdev, iclass 11, count 2 2006.201.08:49:34.70#ibcon#first serial, iclass 11, count 2 2006.201.08:49:34.70#ibcon#enter sib2, iclass 11, count 2 2006.201.08:49:34.70#ibcon#flushed, iclass 11, count 2 2006.201.08:49:34.70#ibcon#about to write, iclass 11, count 2 2006.201.08:49:34.70#ibcon#wrote, iclass 11, count 2 2006.201.08:49:34.70#ibcon#about to read 3, iclass 11, count 2 2006.201.08:49:34.72#ibcon#read 3, iclass 11, count 2 2006.201.08:49:34.72#ibcon#about to read 4, iclass 11, count 2 2006.201.08:49:34.72#ibcon#read 4, iclass 11, count 2 2006.201.08:49:34.72#ibcon#about to read 5, iclass 11, count 2 2006.201.08:49:34.72#ibcon#read 5, iclass 11, count 2 2006.201.08:49:34.72#ibcon#about to read 6, iclass 11, count 2 2006.201.08:49:34.72#ibcon#read 6, iclass 11, count 2 2006.201.08:49:34.72#ibcon#end of sib2, iclass 11, count 2 2006.201.08:49:34.72#ibcon#*mode == 0, iclass 11, count 2 2006.201.08:49:34.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.08:49:34.72#ibcon#[27=AT07-04\r\n] 2006.201.08:49:34.72#ibcon#*before write, iclass 11, count 2 2006.201.08:49:34.72#ibcon#enter sib2, iclass 11, count 2 2006.201.08:49:34.72#ibcon#flushed, iclass 11, count 2 2006.201.08:49:34.72#ibcon#about to write, iclass 11, count 2 2006.201.08:49:34.72#ibcon#wrote, iclass 11, count 2 2006.201.08:49:34.72#ibcon#about to read 3, iclass 11, count 2 2006.201.08:49:34.75#ibcon#read 3, iclass 11, count 2 2006.201.08:49:34.75#ibcon#about to read 4, iclass 11, count 2 2006.201.08:49:34.75#ibcon#read 4, iclass 11, count 2 2006.201.08:49:34.75#ibcon#about to read 5, iclass 11, count 2 2006.201.08:49:34.75#ibcon#read 5, iclass 11, count 2 2006.201.08:49:34.75#ibcon#about to read 6, iclass 11, count 2 2006.201.08:49:34.75#ibcon#read 6, iclass 11, count 2 2006.201.08:49:34.75#ibcon#end of sib2, iclass 11, count 2 2006.201.08:49:34.75#ibcon#*after write, iclass 11, count 2 2006.201.08:49:34.75#ibcon#*before return 0, iclass 11, count 2 2006.201.08:49:34.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:34.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.08:49:34.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.08:49:34.75#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:34.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:34.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:34.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:34.87#ibcon#enter wrdev, iclass 11, count 0 2006.201.08:49:34.87#ibcon#first serial, iclass 11, count 0 2006.201.08:49:34.87#ibcon#enter sib2, iclass 11, count 0 2006.201.08:49:34.87#ibcon#flushed, iclass 11, count 0 2006.201.08:49:34.87#ibcon#about to write, iclass 11, count 0 2006.201.08:49:34.87#ibcon#wrote, iclass 11, count 0 2006.201.08:49:34.87#ibcon#about to read 3, iclass 11, count 0 2006.201.08:49:34.89#ibcon#read 3, iclass 11, count 0 2006.201.08:49:34.89#ibcon#about to read 4, iclass 11, count 0 2006.201.08:49:34.89#ibcon#read 4, iclass 11, count 0 2006.201.08:49:34.89#ibcon#about to read 5, iclass 11, count 0 2006.201.08:49:34.89#ibcon#read 5, iclass 11, count 0 2006.201.08:49:34.89#ibcon#about to read 6, iclass 11, count 0 2006.201.08:49:34.89#ibcon#read 6, iclass 11, count 0 2006.201.08:49:34.89#ibcon#end of sib2, iclass 11, count 0 2006.201.08:49:34.89#ibcon#*mode == 0, iclass 11, count 0 2006.201.08:49:34.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.08:49:34.89#ibcon#[27=USB\r\n] 2006.201.08:49:34.89#ibcon#*before write, iclass 11, count 0 2006.201.08:49:34.89#ibcon#enter sib2, iclass 11, count 0 2006.201.08:49:34.89#ibcon#flushed, iclass 11, count 0 2006.201.08:49:34.89#ibcon#about to write, iclass 11, count 0 2006.201.08:49:34.89#ibcon#wrote, iclass 11, count 0 2006.201.08:49:34.89#ibcon#about to read 3, iclass 11, count 0 2006.201.08:49:34.92#ibcon#read 3, iclass 11, count 0 2006.201.08:49:34.92#ibcon#about to read 4, iclass 11, count 0 2006.201.08:49:34.92#ibcon#read 4, iclass 11, count 0 2006.201.08:49:34.92#ibcon#about to read 5, iclass 11, count 0 2006.201.08:49:34.92#ibcon#read 5, iclass 11, count 0 2006.201.08:49:34.92#ibcon#about to read 6, iclass 11, count 0 2006.201.08:49:34.92#ibcon#read 6, iclass 11, count 0 2006.201.08:49:34.92#ibcon#end of sib2, iclass 11, count 0 2006.201.08:49:34.92#ibcon#*after write, iclass 11, count 0 2006.201.08:49:34.92#ibcon#*before return 0, iclass 11, count 0 2006.201.08:49:34.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:34.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.08:49:34.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.08:49:34.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.08:49:34.92$vck44/vblo=8,744.99 2006.201.08:49:34.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.08:49:34.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.08:49:34.92#ibcon#ireg 17 cls_cnt 0 2006.201.08:49:34.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:34.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:34.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:34.92#ibcon#enter wrdev, iclass 13, count 0 2006.201.08:49:34.92#ibcon#first serial, iclass 13, count 0 2006.201.08:49:34.92#ibcon#enter sib2, iclass 13, count 0 2006.201.08:49:34.92#ibcon#flushed, iclass 13, count 0 2006.201.08:49:34.92#ibcon#about to write, iclass 13, count 0 2006.201.08:49:34.92#ibcon#wrote, iclass 13, count 0 2006.201.08:49:34.92#ibcon#about to read 3, iclass 13, count 0 2006.201.08:49:34.94#ibcon#read 3, iclass 13, count 0 2006.201.08:49:34.94#ibcon#about to read 4, iclass 13, count 0 2006.201.08:49:34.94#ibcon#read 4, iclass 13, count 0 2006.201.08:49:34.94#ibcon#about to read 5, iclass 13, count 0 2006.201.08:49:34.94#ibcon#read 5, iclass 13, count 0 2006.201.08:49:34.94#ibcon#about to read 6, iclass 13, count 0 2006.201.08:49:34.94#ibcon#read 6, iclass 13, count 0 2006.201.08:49:34.94#ibcon#end of sib2, iclass 13, count 0 2006.201.08:49:34.94#ibcon#*mode == 0, iclass 13, count 0 2006.201.08:49:34.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.08:49:34.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:49:34.94#ibcon#*before write, iclass 13, count 0 2006.201.08:49:34.94#ibcon#enter sib2, iclass 13, count 0 2006.201.08:49:34.94#ibcon#flushed, iclass 13, count 0 2006.201.08:49:34.94#ibcon#about to write, iclass 13, count 0 2006.201.08:49:34.94#ibcon#wrote, iclass 13, count 0 2006.201.08:49:34.94#ibcon#about to read 3, iclass 13, count 0 2006.201.08:49:34.98#ibcon#read 3, iclass 13, count 0 2006.201.08:49:34.98#ibcon#about to read 4, iclass 13, count 0 2006.201.08:49:34.98#ibcon#read 4, iclass 13, count 0 2006.201.08:49:34.98#ibcon#about to read 5, iclass 13, count 0 2006.201.08:49:34.98#ibcon#read 5, iclass 13, count 0 2006.201.08:49:34.98#ibcon#about to read 6, iclass 13, count 0 2006.201.08:49:34.98#ibcon#read 6, iclass 13, count 0 2006.201.08:49:34.98#ibcon#end of sib2, iclass 13, count 0 2006.201.08:49:34.98#ibcon#*after write, iclass 13, count 0 2006.201.08:49:34.98#ibcon#*before return 0, iclass 13, count 0 2006.201.08:49:34.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:34.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.08:49:34.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.08:49:34.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.08:49:34.98$vck44/vb=8,4 2006.201.08:49:34.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.08:49:34.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.08:49:34.98#ibcon#ireg 11 cls_cnt 2 2006.201.08:49:34.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:35.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:35.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:35.04#ibcon#enter wrdev, iclass 15, count 2 2006.201.08:49:35.04#ibcon#first serial, iclass 15, count 2 2006.201.08:49:35.04#ibcon#enter sib2, iclass 15, count 2 2006.201.08:49:35.04#ibcon#flushed, iclass 15, count 2 2006.201.08:49:35.04#ibcon#about to write, iclass 15, count 2 2006.201.08:49:35.04#ibcon#wrote, iclass 15, count 2 2006.201.08:49:35.04#ibcon#about to read 3, iclass 15, count 2 2006.201.08:49:35.06#ibcon#read 3, iclass 15, count 2 2006.201.08:49:35.06#ibcon#about to read 4, iclass 15, count 2 2006.201.08:49:35.06#ibcon#read 4, iclass 15, count 2 2006.201.08:49:35.06#ibcon#about to read 5, iclass 15, count 2 2006.201.08:49:35.06#ibcon#read 5, iclass 15, count 2 2006.201.08:49:35.06#ibcon#about to read 6, iclass 15, count 2 2006.201.08:49:35.06#ibcon#read 6, iclass 15, count 2 2006.201.08:49:35.06#ibcon#end of sib2, iclass 15, count 2 2006.201.08:49:35.06#ibcon#*mode == 0, iclass 15, count 2 2006.201.08:49:35.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.08:49:35.06#ibcon#[27=AT08-04\r\n] 2006.201.08:49:35.06#ibcon#*before write, iclass 15, count 2 2006.201.08:49:35.06#ibcon#enter sib2, iclass 15, count 2 2006.201.08:49:35.06#ibcon#flushed, iclass 15, count 2 2006.201.08:49:35.06#ibcon#about to write, iclass 15, count 2 2006.201.08:49:35.06#ibcon#wrote, iclass 15, count 2 2006.201.08:49:35.06#ibcon#about to read 3, iclass 15, count 2 2006.201.08:49:35.09#ibcon#read 3, iclass 15, count 2 2006.201.08:49:35.09#ibcon#about to read 4, iclass 15, count 2 2006.201.08:49:35.09#ibcon#read 4, iclass 15, count 2 2006.201.08:49:35.09#ibcon#about to read 5, iclass 15, count 2 2006.201.08:49:35.09#ibcon#read 5, iclass 15, count 2 2006.201.08:49:35.09#ibcon#about to read 6, iclass 15, count 2 2006.201.08:49:35.09#ibcon#read 6, iclass 15, count 2 2006.201.08:49:35.09#ibcon#end of sib2, iclass 15, count 2 2006.201.08:49:35.09#ibcon#*after write, iclass 15, count 2 2006.201.08:49:35.09#ibcon#*before return 0, iclass 15, count 2 2006.201.08:49:35.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:35.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.08:49:35.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.08:49:35.09#ibcon#ireg 7 cls_cnt 0 2006.201.08:49:35.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:35.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:35.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:35.21#ibcon#enter wrdev, iclass 15, count 0 2006.201.08:49:35.21#ibcon#first serial, iclass 15, count 0 2006.201.08:49:35.21#ibcon#enter sib2, iclass 15, count 0 2006.201.08:49:35.21#ibcon#flushed, iclass 15, count 0 2006.201.08:49:35.21#ibcon#about to write, iclass 15, count 0 2006.201.08:49:35.21#ibcon#wrote, iclass 15, count 0 2006.201.08:49:35.21#ibcon#about to read 3, iclass 15, count 0 2006.201.08:49:35.23#ibcon#read 3, iclass 15, count 0 2006.201.08:49:35.23#ibcon#about to read 4, iclass 15, count 0 2006.201.08:49:35.23#ibcon#read 4, iclass 15, count 0 2006.201.08:49:35.23#ibcon#about to read 5, iclass 15, count 0 2006.201.08:49:35.23#ibcon#read 5, iclass 15, count 0 2006.201.08:49:35.23#ibcon#about to read 6, iclass 15, count 0 2006.201.08:49:35.23#ibcon#read 6, iclass 15, count 0 2006.201.08:49:35.23#ibcon#end of sib2, iclass 15, count 0 2006.201.08:49:35.23#ibcon#*mode == 0, iclass 15, count 0 2006.201.08:49:35.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.08:49:35.23#ibcon#[27=USB\r\n] 2006.201.08:49:35.23#ibcon#*before write, iclass 15, count 0 2006.201.08:49:35.23#ibcon#enter sib2, iclass 15, count 0 2006.201.08:49:35.23#ibcon#flushed, iclass 15, count 0 2006.201.08:49:35.23#ibcon#about to write, iclass 15, count 0 2006.201.08:49:35.23#ibcon#wrote, iclass 15, count 0 2006.201.08:49:35.23#ibcon#about to read 3, iclass 15, count 0 2006.201.08:49:35.26#ibcon#read 3, iclass 15, count 0 2006.201.08:49:35.26#ibcon#about to read 4, iclass 15, count 0 2006.201.08:49:35.26#ibcon#read 4, iclass 15, count 0 2006.201.08:49:35.26#ibcon#about to read 5, iclass 15, count 0 2006.201.08:49:35.26#ibcon#read 5, iclass 15, count 0 2006.201.08:49:35.26#ibcon#about to read 6, iclass 15, count 0 2006.201.08:49:35.26#ibcon#read 6, iclass 15, count 0 2006.201.08:49:35.26#ibcon#end of sib2, iclass 15, count 0 2006.201.08:49:35.26#ibcon#*after write, iclass 15, count 0 2006.201.08:49:35.26#ibcon#*before return 0, iclass 15, count 0 2006.201.08:49:35.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:35.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.08:49:35.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.08:49:35.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.08:49:35.26$vck44/vabw=wide 2006.201.08:49:35.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.08:49:35.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.08:49:35.26#ibcon#ireg 8 cls_cnt 0 2006.201.08:49:35.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:35.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:35.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:35.26#ibcon#enter wrdev, iclass 17, count 0 2006.201.08:49:35.26#ibcon#first serial, iclass 17, count 0 2006.201.08:49:35.26#ibcon#enter sib2, iclass 17, count 0 2006.201.08:49:35.26#ibcon#flushed, iclass 17, count 0 2006.201.08:49:35.26#ibcon#about to write, iclass 17, count 0 2006.201.08:49:35.26#ibcon#wrote, iclass 17, count 0 2006.201.08:49:35.26#ibcon#about to read 3, iclass 17, count 0 2006.201.08:49:35.28#ibcon#read 3, iclass 17, count 0 2006.201.08:49:35.28#ibcon#about to read 4, iclass 17, count 0 2006.201.08:49:35.28#ibcon#read 4, iclass 17, count 0 2006.201.08:49:35.28#ibcon#about to read 5, iclass 17, count 0 2006.201.08:49:35.28#ibcon#read 5, iclass 17, count 0 2006.201.08:49:35.28#ibcon#about to read 6, iclass 17, count 0 2006.201.08:49:35.28#ibcon#read 6, iclass 17, count 0 2006.201.08:49:35.28#ibcon#end of sib2, iclass 17, count 0 2006.201.08:49:35.28#ibcon#*mode == 0, iclass 17, count 0 2006.201.08:49:35.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.08:49:35.28#ibcon#[25=BW32\r\n] 2006.201.08:49:35.28#ibcon#*before write, iclass 17, count 0 2006.201.08:49:35.28#ibcon#enter sib2, iclass 17, count 0 2006.201.08:49:35.28#ibcon#flushed, iclass 17, count 0 2006.201.08:49:35.28#ibcon#about to write, iclass 17, count 0 2006.201.08:49:35.28#ibcon#wrote, iclass 17, count 0 2006.201.08:49:35.28#ibcon#about to read 3, iclass 17, count 0 2006.201.08:49:35.31#ibcon#read 3, iclass 17, count 0 2006.201.08:49:35.31#ibcon#about to read 4, iclass 17, count 0 2006.201.08:49:35.31#ibcon#read 4, iclass 17, count 0 2006.201.08:49:35.31#ibcon#about to read 5, iclass 17, count 0 2006.201.08:49:35.31#ibcon#read 5, iclass 17, count 0 2006.201.08:49:35.31#ibcon#about to read 6, iclass 17, count 0 2006.201.08:49:35.31#ibcon#read 6, iclass 17, count 0 2006.201.08:49:35.31#ibcon#end of sib2, iclass 17, count 0 2006.201.08:49:35.31#ibcon#*after write, iclass 17, count 0 2006.201.08:49:35.31#ibcon#*before return 0, iclass 17, count 0 2006.201.08:49:35.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:35.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.08:49:35.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.08:49:35.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.08:49:35.31$vck44/vbbw=wide 2006.201.08:49:35.31#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.08:49:35.31#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.08:49:35.31#ibcon#ireg 8 cls_cnt 0 2006.201.08:49:35.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:49:35.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:49:35.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:49:35.38#ibcon#enter wrdev, iclass 19, count 0 2006.201.08:49:35.38#ibcon#first serial, iclass 19, count 0 2006.201.08:49:35.38#ibcon#enter sib2, iclass 19, count 0 2006.201.08:49:35.38#ibcon#flushed, iclass 19, count 0 2006.201.08:49:35.38#ibcon#about to write, iclass 19, count 0 2006.201.08:49:35.38#ibcon#wrote, iclass 19, count 0 2006.201.08:49:35.38#ibcon#about to read 3, iclass 19, count 0 2006.201.08:49:35.40#ibcon#read 3, iclass 19, count 0 2006.201.08:49:35.40#ibcon#about to read 4, iclass 19, count 0 2006.201.08:49:35.40#ibcon#read 4, iclass 19, count 0 2006.201.08:49:35.40#ibcon#about to read 5, iclass 19, count 0 2006.201.08:49:35.40#ibcon#read 5, iclass 19, count 0 2006.201.08:49:35.40#ibcon#about to read 6, iclass 19, count 0 2006.201.08:49:35.40#ibcon#read 6, iclass 19, count 0 2006.201.08:49:35.40#ibcon#end of sib2, iclass 19, count 0 2006.201.08:49:35.40#ibcon#*mode == 0, iclass 19, count 0 2006.201.08:49:35.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.08:49:35.40#ibcon#[27=BW32\r\n] 2006.201.08:49:35.40#ibcon#*before write, iclass 19, count 0 2006.201.08:49:35.40#ibcon#enter sib2, iclass 19, count 0 2006.201.08:49:35.40#ibcon#flushed, iclass 19, count 0 2006.201.08:49:35.40#ibcon#about to write, iclass 19, count 0 2006.201.08:49:35.40#ibcon#wrote, iclass 19, count 0 2006.201.08:49:35.40#ibcon#about to read 3, iclass 19, count 0 2006.201.08:49:35.43#ibcon#read 3, iclass 19, count 0 2006.201.08:49:35.43#ibcon#about to read 4, iclass 19, count 0 2006.201.08:49:35.43#ibcon#read 4, iclass 19, count 0 2006.201.08:49:35.43#ibcon#about to read 5, iclass 19, count 0 2006.201.08:49:35.43#ibcon#read 5, iclass 19, count 0 2006.201.08:49:35.43#ibcon#about to read 6, iclass 19, count 0 2006.201.08:49:35.43#ibcon#read 6, iclass 19, count 0 2006.201.08:49:35.43#ibcon#end of sib2, iclass 19, count 0 2006.201.08:49:35.43#ibcon#*after write, iclass 19, count 0 2006.201.08:49:35.43#ibcon#*before return 0, iclass 19, count 0 2006.201.08:49:35.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:49:35.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.08:49:35.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.08:49:35.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.08:49:35.43$setupk4/ifdk4 2006.201.08:49:35.43$ifdk4/lo= 2006.201.08:49:35.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:49:35.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:49:35.43$ifdk4/patch= 2006.201.08:49:35.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:49:35.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:49:35.43$setupk4/!*+20s 2006.201.08:49:43.34#abcon#<5=/05 2.6 4.5 23.01 891003.7\r\n> 2006.201.08:49:43.36#abcon#{5=INTERFACE CLEAR} 2006.201.08:49:43.43#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:49:48.14#trakl#Source acquired 2006.201.08:49:49.14#flagr#flagr/antenna,acquired 2006.201.08:49:49.92$setupk4/"tpicd 2006.201.08:49:49.92$setupk4/echo=off 2006.201.08:49:49.92$setupk4/xlog=off 2006.201.08:49:49.92:!2006.201.08:50:11 2006.201.08:50:11.00:preob 2006.201.08:50:11.14/onsource/TRACKING 2006.201.08:50:11.14:!2006.201.08:50:21 2006.201.08:50:21.00:"tape 2006.201.08:50:21.00:"st=record 2006.201.08:50:21.00:data_valid=on 2006.201.08:50:21.00:midob 2006.201.08:50:22.14/onsource/TRACKING 2006.201.08:50:22.14/wx/23.00,1003.7,89 2006.201.08:50:22.36/cable/+6.4657E-03 2006.201.08:50:23.45/va/01,08,usb,yes,42,45 2006.201.08:50:23.45/va/02,07,usb,yes,45,46 2006.201.08:50:23.45/va/03,08,usb,yes,41,43 2006.201.08:50:23.45/va/04,07,usb,yes,46,49 2006.201.08:50:23.45/va/05,04,usb,yes,41,42 2006.201.08:50:23.45/va/06,05,usb,yes,41,42 2006.201.08:50:23.45/va/07,05,usb,yes,41,42 2006.201.08:50:23.45/va/08,04,usb,yes,40,48 2006.201.08:50:23.68/valo/01,524.99,yes,locked 2006.201.08:50:23.68/valo/02,534.99,yes,locked 2006.201.08:50:23.68/valo/03,564.99,yes,locked 2006.201.08:50:23.68/valo/04,624.99,yes,locked 2006.201.08:50:23.68/valo/05,734.99,yes,locked 2006.201.08:50:23.68/valo/06,814.99,yes,locked 2006.201.08:50:23.68/valo/07,864.99,yes,locked 2006.201.08:50:23.68/valo/08,884.99,yes,locked 2006.201.08:50:24.77/vb/01,04,usb,yes,47,98 2006.201.08:50:24.77/vb/02,05,usb,yes,29,95 2006.201.08:50:24.77/vb/03,04,usb,yes,28,79 2006.201.08:50:24.77/vb/04,05,usb,yes,29,28 2006.201.08:50:24.77/vb/05,04,usb,yes,28,31 2006.201.08:50:24.77/vb/06,04,usb,yes,33,28 2006.201.08:50:24.77/vb/07,04,usb,yes,30,29 2006.201.08:50:24.77/vb/08,04,usb,yes,28,31 2006.201.08:50:25.00/vblo/01,629.99,yes,locked 2006.201.08:50:25.00/vblo/02,634.99,yes,locked 2006.201.08:50:25.00/vblo/03,649.99,yes,locked 2006.201.08:50:25.00/vblo/04,679.99,yes,locked 2006.201.08:50:25.00/vblo/05,709.99,yes,locked 2006.201.08:50:25.00/vblo/06,719.99,yes,locked 2006.201.08:50:25.00/vblo/07,734.99,yes,locked 2006.201.08:50:25.00/vblo/08,744.99,yes,locked 2006.201.08:50:25.15/vabw/8 2006.201.08:50:25.30/vbbw/8 2006.201.08:50:25.39/xfe/off,on,16.2 2006.201.08:50:25.76/ifatt/23,28,28,28 2006.201.08:50:26.05/fmout-gps/S +4.55E-07 2006.201.08:50:26.12:!2006.201.08:57:01 2006.201.08:57:01.00:data_valid=off 2006.201.08:57:01.00:"et 2006.201.08:57:01.00:!+3s 2006.201.08:57:04.02:"tape 2006.201.08:57:04.02:postob 2006.201.08:57:04.11/cable/+6.4644E-03 2006.201.08:57:04.11/wx/22.94,1003.7,90 2006.201.08:57:04.19/fmout-gps/S +4.52E-07 2006.201.08:57:04.19:scan_name=201-0858,jd0607,230 2006.201.08:57:04.20:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.201.08:57:06.14#flagr#flagr/antenna,new-source 2006.201.08:57:06.14:checkk5 2006.201.08:57:06.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.08:57:06.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.08:57:07.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.08:57:07.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.08:57:08.02/chk_obsdata//k5ts1/T2010850??a.dat file size is correct (nominal:1600MB, actual:1600MB). 2006.201.08:57:08.39/chk_obsdata//k5ts2/T2010850??b.dat file size is correct (nominal:1600MB, actual:1600MB). 2006.201.08:57:08.76/chk_obsdata//k5ts3/T2010850??c.dat file size is correct (nominal:1600MB, actual:1600MB). 2006.201.08:57:09.13/chk_obsdata//k5ts4/T2010850??d.dat file size is correct (nominal:1600MB, actual:1600MB). 2006.201.08:57:09.83/k5log//k5ts1_log_newline 2006.201.08:57:10.55/k5log//k5ts2_log_newline 2006.201.08:57:11.24/k5log//k5ts3_log_newline 2006.201.08:57:11.95/k5log//k5ts4_log_newline 2006.201.08:57:11.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.08:57:11.97:setupk4=1 2006.201.08:57:11.97$setupk4/echo=on 2006.201.08:57:11.97$setupk4/pcalon 2006.201.08:57:11.97$pcalon/"no phase cal control is implemented here 2006.201.08:57:11.97$setupk4/"tpicd=stop 2006.201.08:57:11.97$setupk4/"rec=synch_on 2006.201.08:57:11.97$setupk4/"rec_mode=128 2006.201.08:57:11.97$setupk4/!* 2006.201.08:57:11.97$setupk4/recpk4 2006.201.08:57:11.97$recpk4/recpatch= 2006.201.08:57:11.98$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.08:57:11.98$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.08:57:11.98$setupk4/vck44 2006.201.08:57:11.98$vck44/valo=1,524.99 2006.201.08:57:11.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.08:57:11.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.08:57:11.98#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:11.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:11.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:11.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:11.98#ibcon#enter wrdev, iclass 24, count 0 2006.201.08:57:11.98#ibcon#first serial, iclass 24, count 0 2006.201.08:57:11.98#ibcon#enter sib2, iclass 24, count 0 2006.201.08:57:11.98#ibcon#flushed, iclass 24, count 0 2006.201.08:57:11.98#ibcon#about to write, iclass 24, count 0 2006.201.08:57:11.98#ibcon#wrote, iclass 24, count 0 2006.201.08:57:11.98#ibcon#about to read 3, iclass 24, count 0 2006.201.08:57:12.01#ibcon#read 3, iclass 24, count 0 2006.201.08:57:12.01#ibcon#about to read 4, iclass 24, count 0 2006.201.08:57:12.01#ibcon#read 4, iclass 24, count 0 2006.201.08:57:12.01#ibcon#about to read 5, iclass 24, count 0 2006.201.08:57:12.01#ibcon#read 5, iclass 24, count 0 2006.201.08:57:12.01#ibcon#about to read 6, iclass 24, count 0 2006.201.08:57:12.01#ibcon#read 6, iclass 24, count 0 2006.201.08:57:12.01#ibcon#end of sib2, iclass 24, count 0 2006.201.08:57:12.01#ibcon#*mode == 0, iclass 24, count 0 2006.201.08:57:12.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.08:57:12.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.08:57:12.01#ibcon#*before write, iclass 24, count 0 2006.201.08:57:12.01#ibcon#enter sib2, iclass 24, count 0 2006.201.08:57:12.01#ibcon#flushed, iclass 24, count 0 2006.201.08:57:12.01#ibcon#about to write, iclass 24, count 0 2006.201.08:57:12.01#ibcon#wrote, iclass 24, count 0 2006.201.08:57:12.01#ibcon#about to read 3, iclass 24, count 0 2006.201.08:57:12.07#ibcon#read 3, iclass 24, count 0 2006.201.08:57:12.07#ibcon#about to read 4, iclass 24, count 0 2006.201.08:57:12.07#ibcon#read 4, iclass 24, count 0 2006.201.08:57:12.07#ibcon#about to read 5, iclass 24, count 0 2006.201.08:57:12.07#ibcon#read 5, iclass 24, count 0 2006.201.08:57:12.07#ibcon#about to read 6, iclass 24, count 0 2006.201.08:57:12.07#ibcon#read 6, iclass 24, count 0 2006.201.08:57:12.07#ibcon#end of sib2, iclass 24, count 0 2006.201.08:57:12.07#ibcon#*after write, iclass 24, count 0 2006.201.08:57:12.07#ibcon#*before return 0, iclass 24, count 0 2006.201.08:57:12.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:12.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:12.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.08:57:12.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.08:57:12.07$vck44/va=1,8 2006.201.08:57:12.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.08:57:12.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.08:57:12.07#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:12.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:12.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:12.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:12.07#ibcon#enter wrdev, iclass 26, count 2 2006.201.08:57:12.07#ibcon#first serial, iclass 26, count 2 2006.201.08:57:12.07#ibcon#enter sib2, iclass 26, count 2 2006.201.08:57:12.07#ibcon#flushed, iclass 26, count 2 2006.201.08:57:12.07#ibcon#about to write, iclass 26, count 2 2006.201.08:57:12.07#ibcon#wrote, iclass 26, count 2 2006.201.08:57:12.07#ibcon#about to read 3, iclass 26, count 2 2006.201.08:57:12.09#ibcon#read 3, iclass 26, count 2 2006.201.08:57:12.09#ibcon#about to read 4, iclass 26, count 2 2006.201.08:57:12.09#ibcon#read 4, iclass 26, count 2 2006.201.08:57:12.09#ibcon#about to read 5, iclass 26, count 2 2006.201.08:57:12.09#ibcon#read 5, iclass 26, count 2 2006.201.08:57:12.09#ibcon#about to read 6, iclass 26, count 2 2006.201.08:57:12.09#ibcon#read 6, iclass 26, count 2 2006.201.08:57:12.09#ibcon#end of sib2, iclass 26, count 2 2006.201.08:57:12.09#ibcon#*mode == 0, iclass 26, count 2 2006.201.08:57:12.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.08:57:12.09#ibcon#[25=AT01-08\r\n] 2006.201.08:57:12.09#ibcon#*before write, iclass 26, count 2 2006.201.08:57:12.09#ibcon#enter sib2, iclass 26, count 2 2006.201.08:57:12.09#ibcon#flushed, iclass 26, count 2 2006.201.08:57:12.09#ibcon#about to write, iclass 26, count 2 2006.201.08:57:12.09#ibcon#wrote, iclass 26, count 2 2006.201.08:57:12.09#ibcon#about to read 3, iclass 26, count 2 2006.201.08:57:12.13#ibcon#read 3, iclass 26, count 2 2006.201.08:57:12.13#ibcon#about to read 4, iclass 26, count 2 2006.201.08:57:12.13#ibcon#read 4, iclass 26, count 2 2006.201.08:57:12.13#ibcon#about to read 5, iclass 26, count 2 2006.201.08:57:12.13#ibcon#read 5, iclass 26, count 2 2006.201.08:57:12.13#ibcon#about to read 6, iclass 26, count 2 2006.201.08:57:12.13#ibcon#read 6, iclass 26, count 2 2006.201.08:57:12.13#ibcon#end of sib2, iclass 26, count 2 2006.201.08:57:12.13#ibcon#*after write, iclass 26, count 2 2006.201.08:57:12.13#ibcon#*before return 0, iclass 26, count 2 2006.201.08:57:12.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:12.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:12.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.08:57:12.13#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:12.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:12.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:12.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:12.25#ibcon#enter wrdev, iclass 26, count 0 2006.201.08:57:12.25#ibcon#first serial, iclass 26, count 0 2006.201.08:57:12.25#ibcon#enter sib2, iclass 26, count 0 2006.201.08:57:12.25#ibcon#flushed, iclass 26, count 0 2006.201.08:57:12.25#ibcon#about to write, iclass 26, count 0 2006.201.08:57:12.25#ibcon#wrote, iclass 26, count 0 2006.201.08:57:12.25#ibcon#about to read 3, iclass 26, count 0 2006.201.08:57:12.27#ibcon#read 3, iclass 26, count 0 2006.201.08:57:12.27#ibcon#about to read 4, iclass 26, count 0 2006.201.08:57:12.27#ibcon#read 4, iclass 26, count 0 2006.201.08:57:12.27#ibcon#about to read 5, iclass 26, count 0 2006.201.08:57:12.27#ibcon#read 5, iclass 26, count 0 2006.201.08:57:12.27#ibcon#about to read 6, iclass 26, count 0 2006.201.08:57:12.27#ibcon#read 6, iclass 26, count 0 2006.201.08:57:12.27#ibcon#end of sib2, iclass 26, count 0 2006.201.08:57:12.27#ibcon#*mode == 0, iclass 26, count 0 2006.201.08:57:12.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.08:57:12.27#ibcon#[25=USB\r\n] 2006.201.08:57:12.27#ibcon#*before write, iclass 26, count 0 2006.201.08:57:12.27#ibcon#enter sib2, iclass 26, count 0 2006.201.08:57:12.27#ibcon#flushed, iclass 26, count 0 2006.201.08:57:12.27#ibcon#about to write, iclass 26, count 0 2006.201.08:57:12.27#ibcon#wrote, iclass 26, count 0 2006.201.08:57:12.27#ibcon#about to read 3, iclass 26, count 0 2006.201.08:57:12.30#ibcon#read 3, iclass 26, count 0 2006.201.08:57:12.30#ibcon#about to read 4, iclass 26, count 0 2006.201.08:57:12.30#ibcon#read 4, iclass 26, count 0 2006.201.08:57:12.30#ibcon#about to read 5, iclass 26, count 0 2006.201.08:57:12.30#ibcon#read 5, iclass 26, count 0 2006.201.08:57:12.30#ibcon#about to read 6, iclass 26, count 0 2006.201.08:57:12.30#ibcon#read 6, iclass 26, count 0 2006.201.08:57:12.30#ibcon#end of sib2, iclass 26, count 0 2006.201.08:57:12.30#ibcon#*after write, iclass 26, count 0 2006.201.08:57:12.30#ibcon#*before return 0, iclass 26, count 0 2006.201.08:57:12.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:12.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:12.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.08:57:12.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.08:57:12.30$vck44/valo=2,534.99 2006.201.08:57:12.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.08:57:12.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.08:57:12.30#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:12.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:12.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:12.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:12.30#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:57:12.30#ibcon#first serial, iclass 28, count 0 2006.201.08:57:12.30#ibcon#enter sib2, iclass 28, count 0 2006.201.08:57:12.30#ibcon#flushed, iclass 28, count 0 2006.201.08:57:12.30#ibcon#about to write, iclass 28, count 0 2006.201.08:57:12.30#ibcon#wrote, iclass 28, count 0 2006.201.08:57:12.30#ibcon#about to read 3, iclass 28, count 0 2006.201.08:57:12.32#ibcon#read 3, iclass 28, count 0 2006.201.08:57:12.32#ibcon#about to read 4, iclass 28, count 0 2006.201.08:57:12.32#ibcon#read 4, iclass 28, count 0 2006.201.08:57:12.32#ibcon#about to read 5, iclass 28, count 0 2006.201.08:57:12.32#ibcon#read 5, iclass 28, count 0 2006.201.08:57:12.32#ibcon#about to read 6, iclass 28, count 0 2006.201.08:57:12.32#ibcon#read 6, iclass 28, count 0 2006.201.08:57:12.32#ibcon#end of sib2, iclass 28, count 0 2006.201.08:57:12.32#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:57:12.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:57:12.32#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.08:57:12.32#ibcon#*before write, iclass 28, count 0 2006.201.08:57:12.32#ibcon#enter sib2, iclass 28, count 0 2006.201.08:57:12.32#ibcon#flushed, iclass 28, count 0 2006.201.08:57:12.32#ibcon#about to write, iclass 28, count 0 2006.201.08:57:12.32#ibcon#wrote, iclass 28, count 0 2006.201.08:57:12.32#ibcon#about to read 3, iclass 28, count 0 2006.201.08:57:12.37#ibcon#read 3, iclass 28, count 0 2006.201.08:57:12.37#ibcon#about to read 4, iclass 28, count 0 2006.201.08:57:12.37#ibcon#read 4, iclass 28, count 0 2006.201.08:57:12.37#ibcon#about to read 5, iclass 28, count 0 2006.201.08:57:12.37#ibcon#read 5, iclass 28, count 0 2006.201.08:57:12.37#ibcon#about to read 6, iclass 28, count 0 2006.201.08:57:12.37#ibcon#read 6, iclass 28, count 0 2006.201.08:57:12.37#ibcon#end of sib2, iclass 28, count 0 2006.201.08:57:12.37#ibcon#*after write, iclass 28, count 0 2006.201.08:57:12.37#ibcon#*before return 0, iclass 28, count 0 2006.201.08:57:12.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:12.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:12.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:57:12.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:57:12.37$vck44/va=2,7 2006.201.08:57:12.37#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.08:57:12.37#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.08:57:12.37#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:12.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:12.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:12.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:12.42#ibcon#enter wrdev, iclass 30, count 2 2006.201.08:57:12.42#ibcon#first serial, iclass 30, count 2 2006.201.08:57:12.42#ibcon#enter sib2, iclass 30, count 2 2006.201.08:57:12.42#ibcon#flushed, iclass 30, count 2 2006.201.08:57:12.42#ibcon#about to write, iclass 30, count 2 2006.201.08:57:12.42#ibcon#wrote, iclass 30, count 2 2006.201.08:57:12.42#ibcon#about to read 3, iclass 30, count 2 2006.201.08:57:12.44#ibcon#read 3, iclass 30, count 2 2006.201.08:57:12.44#ibcon#about to read 4, iclass 30, count 2 2006.201.08:57:12.44#ibcon#read 4, iclass 30, count 2 2006.201.08:57:12.44#ibcon#about to read 5, iclass 30, count 2 2006.201.08:57:12.44#ibcon#read 5, iclass 30, count 2 2006.201.08:57:12.44#ibcon#about to read 6, iclass 30, count 2 2006.201.08:57:12.44#ibcon#read 6, iclass 30, count 2 2006.201.08:57:12.44#ibcon#end of sib2, iclass 30, count 2 2006.201.08:57:12.44#ibcon#*mode == 0, iclass 30, count 2 2006.201.08:57:12.44#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.08:57:12.44#ibcon#[25=AT02-07\r\n] 2006.201.08:57:12.44#ibcon#*before write, iclass 30, count 2 2006.201.08:57:12.44#ibcon#enter sib2, iclass 30, count 2 2006.201.08:57:12.44#ibcon#flushed, iclass 30, count 2 2006.201.08:57:12.44#ibcon#about to write, iclass 30, count 2 2006.201.08:57:12.44#ibcon#wrote, iclass 30, count 2 2006.201.08:57:12.44#ibcon#about to read 3, iclass 30, count 2 2006.201.08:57:12.47#ibcon#read 3, iclass 30, count 2 2006.201.08:57:12.47#ibcon#about to read 4, iclass 30, count 2 2006.201.08:57:12.47#ibcon#read 4, iclass 30, count 2 2006.201.08:57:12.47#ibcon#about to read 5, iclass 30, count 2 2006.201.08:57:12.47#ibcon#read 5, iclass 30, count 2 2006.201.08:57:12.47#ibcon#about to read 6, iclass 30, count 2 2006.201.08:57:12.47#ibcon#read 6, iclass 30, count 2 2006.201.08:57:12.47#ibcon#end of sib2, iclass 30, count 2 2006.201.08:57:12.47#ibcon#*after write, iclass 30, count 2 2006.201.08:57:12.47#ibcon#*before return 0, iclass 30, count 2 2006.201.08:57:12.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:12.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:12.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.08:57:12.47#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:12.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:12.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:12.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:12.59#ibcon#enter wrdev, iclass 30, count 0 2006.201.08:57:12.59#ibcon#first serial, iclass 30, count 0 2006.201.08:57:12.59#ibcon#enter sib2, iclass 30, count 0 2006.201.08:57:12.59#ibcon#flushed, iclass 30, count 0 2006.201.08:57:12.59#ibcon#about to write, iclass 30, count 0 2006.201.08:57:12.59#ibcon#wrote, iclass 30, count 0 2006.201.08:57:12.59#ibcon#about to read 3, iclass 30, count 0 2006.201.08:57:12.61#ibcon#read 3, iclass 30, count 0 2006.201.08:57:12.61#ibcon#about to read 4, iclass 30, count 0 2006.201.08:57:12.61#ibcon#read 4, iclass 30, count 0 2006.201.08:57:12.61#ibcon#about to read 5, iclass 30, count 0 2006.201.08:57:12.61#ibcon#read 5, iclass 30, count 0 2006.201.08:57:12.61#ibcon#about to read 6, iclass 30, count 0 2006.201.08:57:12.61#ibcon#read 6, iclass 30, count 0 2006.201.08:57:12.61#ibcon#end of sib2, iclass 30, count 0 2006.201.08:57:12.61#ibcon#*mode == 0, iclass 30, count 0 2006.201.08:57:12.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.08:57:12.61#ibcon#[25=USB\r\n] 2006.201.08:57:12.61#ibcon#*before write, iclass 30, count 0 2006.201.08:57:12.61#ibcon#enter sib2, iclass 30, count 0 2006.201.08:57:12.61#ibcon#flushed, iclass 30, count 0 2006.201.08:57:12.61#ibcon#about to write, iclass 30, count 0 2006.201.08:57:12.61#ibcon#wrote, iclass 30, count 0 2006.201.08:57:12.61#ibcon#about to read 3, iclass 30, count 0 2006.201.08:57:12.64#ibcon#read 3, iclass 30, count 0 2006.201.08:57:12.64#ibcon#about to read 4, iclass 30, count 0 2006.201.08:57:12.64#ibcon#read 4, iclass 30, count 0 2006.201.08:57:12.64#ibcon#about to read 5, iclass 30, count 0 2006.201.08:57:12.64#ibcon#read 5, iclass 30, count 0 2006.201.08:57:12.64#ibcon#about to read 6, iclass 30, count 0 2006.201.08:57:12.64#ibcon#read 6, iclass 30, count 0 2006.201.08:57:12.64#ibcon#end of sib2, iclass 30, count 0 2006.201.08:57:12.64#ibcon#*after write, iclass 30, count 0 2006.201.08:57:12.64#ibcon#*before return 0, iclass 30, count 0 2006.201.08:57:12.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:12.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:12.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.08:57:12.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.08:57:12.64$vck44/valo=3,564.99 2006.201.08:57:12.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.08:57:12.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.08:57:12.64#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:12.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:12.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:12.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:12.64#ibcon#enter wrdev, iclass 32, count 0 2006.201.08:57:12.64#ibcon#first serial, iclass 32, count 0 2006.201.08:57:12.64#ibcon#enter sib2, iclass 32, count 0 2006.201.08:57:12.64#ibcon#flushed, iclass 32, count 0 2006.201.08:57:12.64#ibcon#about to write, iclass 32, count 0 2006.201.08:57:12.64#ibcon#wrote, iclass 32, count 0 2006.201.08:57:12.64#ibcon#about to read 3, iclass 32, count 0 2006.201.08:57:12.66#ibcon#read 3, iclass 32, count 0 2006.201.08:57:12.66#ibcon#about to read 4, iclass 32, count 0 2006.201.08:57:12.66#ibcon#read 4, iclass 32, count 0 2006.201.08:57:12.66#ibcon#about to read 5, iclass 32, count 0 2006.201.08:57:12.66#ibcon#read 5, iclass 32, count 0 2006.201.08:57:12.66#ibcon#about to read 6, iclass 32, count 0 2006.201.08:57:12.66#ibcon#read 6, iclass 32, count 0 2006.201.08:57:12.66#ibcon#end of sib2, iclass 32, count 0 2006.201.08:57:12.66#ibcon#*mode == 0, iclass 32, count 0 2006.201.08:57:12.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.08:57:12.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.08:57:12.66#ibcon#*before write, iclass 32, count 0 2006.201.08:57:12.66#ibcon#enter sib2, iclass 32, count 0 2006.201.08:57:12.66#ibcon#flushed, iclass 32, count 0 2006.201.08:57:12.66#ibcon#about to write, iclass 32, count 0 2006.201.08:57:12.66#ibcon#wrote, iclass 32, count 0 2006.201.08:57:12.66#ibcon#about to read 3, iclass 32, count 0 2006.201.08:57:12.71#ibcon#read 3, iclass 32, count 0 2006.201.08:57:12.71#ibcon#about to read 4, iclass 32, count 0 2006.201.08:57:12.71#ibcon#read 4, iclass 32, count 0 2006.201.08:57:12.71#ibcon#about to read 5, iclass 32, count 0 2006.201.08:57:12.71#ibcon#read 5, iclass 32, count 0 2006.201.08:57:12.71#ibcon#about to read 6, iclass 32, count 0 2006.201.08:57:12.71#ibcon#read 6, iclass 32, count 0 2006.201.08:57:12.71#ibcon#end of sib2, iclass 32, count 0 2006.201.08:57:12.71#ibcon#*after write, iclass 32, count 0 2006.201.08:57:12.71#ibcon#*before return 0, iclass 32, count 0 2006.201.08:57:12.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:12.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:12.71#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.08:57:12.71#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.08:57:12.71$vck44/va=3,8 2006.201.08:57:12.71#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.08:57:12.71#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.08:57:12.71#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:12.71#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:12.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:12.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:12.76#ibcon#enter wrdev, iclass 34, count 2 2006.201.08:57:12.76#ibcon#first serial, iclass 34, count 2 2006.201.08:57:12.76#ibcon#enter sib2, iclass 34, count 2 2006.201.08:57:12.76#ibcon#flushed, iclass 34, count 2 2006.201.08:57:12.76#ibcon#about to write, iclass 34, count 2 2006.201.08:57:12.76#ibcon#wrote, iclass 34, count 2 2006.201.08:57:12.76#ibcon#about to read 3, iclass 34, count 2 2006.201.08:57:12.78#ibcon#read 3, iclass 34, count 2 2006.201.08:57:12.78#ibcon#about to read 4, iclass 34, count 2 2006.201.08:57:12.78#ibcon#read 4, iclass 34, count 2 2006.201.08:57:12.78#ibcon#about to read 5, iclass 34, count 2 2006.201.08:57:12.78#ibcon#read 5, iclass 34, count 2 2006.201.08:57:12.78#ibcon#about to read 6, iclass 34, count 2 2006.201.08:57:12.78#ibcon#read 6, iclass 34, count 2 2006.201.08:57:12.78#ibcon#end of sib2, iclass 34, count 2 2006.201.08:57:12.78#ibcon#*mode == 0, iclass 34, count 2 2006.201.08:57:12.78#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.08:57:12.78#ibcon#[25=AT03-08\r\n] 2006.201.08:57:12.78#ibcon#*before write, iclass 34, count 2 2006.201.08:57:12.78#ibcon#enter sib2, iclass 34, count 2 2006.201.08:57:12.78#ibcon#flushed, iclass 34, count 2 2006.201.08:57:12.78#ibcon#about to write, iclass 34, count 2 2006.201.08:57:12.78#ibcon#wrote, iclass 34, count 2 2006.201.08:57:12.78#ibcon#about to read 3, iclass 34, count 2 2006.201.08:57:12.81#ibcon#read 3, iclass 34, count 2 2006.201.08:57:12.81#ibcon#about to read 4, iclass 34, count 2 2006.201.08:57:12.81#ibcon#read 4, iclass 34, count 2 2006.201.08:57:12.81#ibcon#about to read 5, iclass 34, count 2 2006.201.08:57:12.81#ibcon#read 5, iclass 34, count 2 2006.201.08:57:12.81#ibcon#about to read 6, iclass 34, count 2 2006.201.08:57:12.81#ibcon#read 6, iclass 34, count 2 2006.201.08:57:12.81#ibcon#end of sib2, iclass 34, count 2 2006.201.08:57:12.81#ibcon#*after write, iclass 34, count 2 2006.201.08:57:12.81#ibcon#*before return 0, iclass 34, count 2 2006.201.08:57:12.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:12.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:12.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.08:57:12.81#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:12.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:12.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:12.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:12.93#ibcon#enter wrdev, iclass 34, count 0 2006.201.08:57:12.93#ibcon#first serial, iclass 34, count 0 2006.201.08:57:12.93#ibcon#enter sib2, iclass 34, count 0 2006.201.08:57:12.93#ibcon#flushed, iclass 34, count 0 2006.201.08:57:12.93#ibcon#about to write, iclass 34, count 0 2006.201.08:57:12.93#ibcon#wrote, iclass 34, count 0 2006.201.08:57:12.93#ibcon#about to read 3, iclass 34, count 0 2006.201.08:57:12.95#ibcon#read 3, iclass 34, count 0 2006.201.08:57:12.95#ibcon#about to read 4, iclass 34, count 0 2006.201.08:57:12.95#ibcon#read 4, iclass 34, count 0 2006.201.08:57:12.95#ibcon#about to read 5, iclass 34, count 0 2006.201.08:57:12.95#ibcon#read 5, iclass 34, count 0 2006.201.08:57:12.95#ibcon#about to read 6, iclass 34, count 0 2006.201.08:57:12.95#ibcon#read 6, iclass 34, count 0 2006.201.08:57:12.95#ibcon#end of sib2, iclass 34, count 0 2006.201.08:57:12.95#ibcon#*mode == 0, iclass 34, count 0 2006.201.08:57:12.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.08:57:12.95#ibcon#[25=USB\r\n] 2006.201.08:57:12.95#ibcon#*before write, iclass 34, count 0 2006.201.08:57:12.95#ibcon#enter sib2, iclass 34, count 0 2006.201.08:57:12.95#ibcon#flushed, iclass 34, count 0 2006.201.08:57:12.95#ibcon#about to write, iclass 34, count 0 2006.201.08:57:12.95#ibcon#wrote, iclass 34, count 0 2006.201.08:57:12.95#ibcon#about to read 3, iclass 34, count 0 2006.201.08:57:12.98#ibcon#read 3, iclass 34, count 0 2006.201.08:57:12.98#ibcon#about to read 4, iclass 34, count 0 2006.201.08:57:12.98#ibcon#read 4, iclass 34, count 0 2006.201.08:57:12.98#ibcon#about to read 5, iclass 34, count 0 2006.201.08:57:12.98#ibcon#read 5, iclass 34, count 0 2006.201.08:57:12.98#ibcon#about to read 6, iclass 34, count 0 2006.201.08:57:12.98#ibcon#read 6, iclass 34, count 0 2006.201.08:57:12.98#ibcon#end of sib2, iclass 34, count 0 2006.201.08:57:12.98#ibcon#*after write, iclass 34, count 0 2006.201.08:57:12.98#ibcon#*before return 0, iclass 34, count 0 2006.201.08:57:12.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:12.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:12.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.08:57:12.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.08:57:12.98$vck44/valo=4,624.99 2006.201.08:57:12.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.08:57:12.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.08:57:12.98#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:12.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:12.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:12.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:12.98#ibcon#enter wrdev, iclass 36, count 0 2006.201.08:57:12.98#ibcon#first serial, iclass 36, count 0 2006.201.08:57:12.98#ibcon#enter sib2, iclass 36, count 0 2006.201.08:57:12.98#ibcon#flushed, iclass 36, count 0 2006.201.08:57:12.98#ibcon#about to write, iclass 36, count 0 2006.201.08:57:12.98#ibcon#wrote, iclass 36, count 0 2006.201.08:57:12.98#ibcon#about to read 3, iclass 36, count 0 2006.201.08:57:13.00#ibcon#read 3, iclass 36, count 0 2006.201.08:57:13.00#ibcon#about to read 4, iclass 36, count 0 2006.201.08:57:13.00#ibcon#read 4, iclass 36, count 0 2006.201.08:57:13.00#ibcon#about to read 5, iclass 36, count 0 2006.201.08:57:13.00#ibcon#read 5, iclass 36, count 0 2006.201.08:57:13.00#ibcon#about to read 6, iclass 36, count 0 2006.201.08:57:13.00#ibcon#read 6, iclass 36, count 0 2006.201.08:57:13.00#ibcon#end of sib2, iclass 36, count 0 2006.201.08:57:13.00#ibcon#*mode == 0, iclass 36, count 0 2006.201.08:57:13.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.08:57:13.00#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.08:57:13.00#ibcon#*before write, iclass 36, count 0 2006.201.08:57:13.00#ibcon#enter sib2, iclass 36, count 0 2006.201.08:57:13.00#ibcon#flushed, iclass 36, count 0 2006.201.08:57:13.00#ibcon#about to write, iclass 36, count 0 2006.201.08:57:13.00#ibcon#wrote, iclass 36, count 0 2006.201.08:57:13.00#ibcon#about to read 3, iclass 36, count 0 2006.201.08:57:13.05#ibcon#read 3, iclass 36, count 0 2006.201.08:57:13.05#ibcon#about to read 4, iclass 36, count 0 2006.201.08:57:13.05#ibcon#read 4, iclass 36, count 0 2006.201.08:57:13.05#ibcon#about to read 5, iclass 36, count 0 2006.201.08:57:13.05#ibcon#read 5, iclass 36, count 0 2006.201.08:57:13.05#ibcon#about to read 6, iclass 36, count 0 2006.201.08:57:13.05#ibcon#read 6, iclass 36, count 0 2006.201.08:57:13.05#ibcon#end of sib2, iclass 36, count 0 2006.201.08:57:13.05#ibcon#*after write, iclass 36, count 0 2006.201.08:57:13.05#ibcon#*before return 0, iclass 36, count 0 2006.201.08:57:13.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:13.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:13.05#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.08:57:13.05#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.08:57:13.05$vck44/va=4,7 2006.201.08:57:13.05#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.08:57:13.05#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.08:57:13.05#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:13.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:13.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:13.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:13.10#ibcon#enter wrdev, iclass 38, count 2 2006.201.08:57:13.10#ibcon#first serial, iclass 38, count 2 2006.201.08:57:13.10#ibcon#enter sib2, iclass 38, count 2 2006.201.08:57:13.10#ibcon#flushed, iclass 38, count 2 2006.201.08:57:13.10#ibcon#about to write, iclass 38, count 2 2006.201.08:57:13.10#ibcon#wrote, iclass 38, count 2 2006.201.08:57:13.10#ibcon#about to read 3, iclass 38, count 2 2006.201.08:57:13.12#ibcon#read 3, iclass 38, count 2 2006.201.08:57:13.12#ibcon#about to read 4, iclass 38, count 2 2006.201.08:57:13.12#ibcon#read 4, iclass 38, count 2 2006.201.08:57:13.12#ibcon#about to read 5, iclass 38, count 2 2006.201.08:57:13.12#ibcon#read 5, iclass 38, count 2 2006.201.08:57:13.12#ibcon#about to read 6, iclass 38, count 2 2006.201.08:57:13.12#ibcon#read 6, iclass 38, count 2 2006.201.08:57:13.12#ibcon#end of sib2, iclass 38, count 2 2006.201.08:57:13.12#ibcon#*mode == 0, iclass 38, count 2 2006.201.08:57:13.12#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.08:57:13.12#ibcon#[25=AT04-07\r\n] 2006.201.08:57:13.12#ibcon#*before write, iclass 38, count 2 2006.201.08:57:13.12#ibcon#enter sib2, iclass 38, count 2 2006.201.08:57:13.12#ibcon#flushed, iclass 38, count 2 2006.201.08:57:13.12#ibcon#about to write, iclass 38, count 2 2006.201.08:57:13.12#ibcon#wrote, iclass 38, count 2 2006.201.08:57:13.12#ibcon#about to read 3, iclass 38, count 2 2006.201.08:57:13.15#ibcon#read 3, iclass 38, count 2 2006.201.08:57:13.15#ibcon#about to read 4, iclass 38, count 2 2006.201.08:57:13.15#ibcon#read 4, iclass 38, count 2 2006.201.08:57:13.15#ibcon#about to read 5, iclass 38, count 2 2006.201.08:57:13.15#ibcon#read 5, iclass 38, count 2 2006.201.08:57:13.15#ibcon#about to read 6, iclass 38, count 2 2006.201.08:57:13.15#ibcon#read 6, iclass 38, count 2 2006.201.08:57:13.15#ibcon#end of sib2, iclass 38, count 2 2006.201.08:57:13.15#ibcon#*after write, iclass 38, count 2 2006.201.08:57:13.15#ibcon#*before return 0, iclass 38, count 2 2006.201.08:57:13.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:13.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:13.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.08:57:13.15#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:13.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:13.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:13.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:13.27#ibcon#enter wrdev, iclass 38, count 0 2006.201.08:57:13.27#ibcon#first serial, iclass 38, count 0 2006.201.08:57:13.27#ibcon#enter sib2, iclass 38, count 0 2006.201.08:57:13.27#ibcon#flushed, iclass 38, count 0 2006.201.08:57:13.27#ibcon#about to write, iclass 38, count 0 2006.201.08:57:13.27#ibcon#wrote, iclass 38, count 0 2006.201.08:57:13.27#ibcon#about to read 3, iclass 38, count 0 2006.201.08:57:13.29#ibcon#read 3, iclass 38, count 0 2006.201.08:57:13.29#ibcon#about to read 4, iclass 38, count 0 2006.201.08:57:13.29#ibcon#read 4, iclass 38, count 0 2006.201.08:57:13.29#ibcon#about to read 5, iclass 38, count 0 2006.201.08:57:13.29#ibcon#read 5, iclass 38, count 0 2006.201.08:57:13.29#ibcon#about to read 6, iclass 38, count 0 2006.201.08:57:13.29#ibcon#read 6, iclass 38, count 0 2006.201.08:57:13.29#ibcon#end of sib2, iclass 38, count 0 2006.201.08:57:13.29#ibcon#*mode == 0, iclass 38, count 0 2006.201.08:57:13.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.08:57:13.29#ibcon#[25=USB\r\n] 2006.201.08:57:13.29#ibcon#*before write, iclass 38, count 0 2006.201.08:57:13.29#ibcon#enter sib2, iclass 38, count 0 2006.201.08:57:13.29#ibcon#flushed, iclass 38, count 0 2006.201.08:57:13.29#ibcon#about to write, iclass 38, count 0 2006.201.08:57:13.29#ibcon#wrote, iclass 38, count 0 2006.201.08:57:13.29#ibcon#about to read 3, iclass 38, count 0 2006.201.08:57:13.32#ibcon#read 3, iclass 38, count 0 2006.201.08:57:13.32#ibcon#about to read 4, iclass 38, count 0 2006.201.08:57:13.32#ibcon#read 4, iclass 38, count 0 2006.201.08:57:13.32#ibcon#about to read 5, iclass 38, count 0 2006.201.08:57:13.32#ibcon#read 5, iclass 38, count 0 2006.201.08:57:13.32#ibcon#about to read 6, iclass 38, count 0 2006.201.08:57:13.32#ibcon#read 6, iclass 38, count 0 2006.201.08:57:13.32#ibcon#end of sib2, iclass 38, count 0 2006.201.08:57:13.32#ibcon#*after write, iclass 38, count 0 2006.201.08:57:13.32#ibcon#*before return 0, iclass 38, count 0 2006.201.08:57:13.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:13.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:13.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.08:57:13.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.08:57:13.32$vck44/valo=5,734.99 2006.201.08:57:13.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.08:57:13.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.08:57:13.32#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:13.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:13.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:13.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:13.32#ibcon#enter wrdev, iclass 40, count 0 2006.201.08:57:13.32#ibcon#first serial, iclass 40, count 0 2006.201.08:57:13.32#ibcon#enter sib2, iclass 40, count 0 2006.201.08:57:13.32#ibcon#flushed, iclass 40, count 0 2006.201.08:57:13.32#ibcon#about to write, iclass 40, count 0 2006.201.08:57:13.32#ibcon#wrote, iclass 40, count 0 2006.201.08:57:13.32#ibcon#about to read 3, iclass 40, count 0 2006.201.08:57:13.34#ibcon#read 3, iclass 40, count 0 2006.201.08:57:13.34#ibcon#about to read 4, iclass 40, count 0 2006.201.08:57:13.34#ibcon#read 4, iclass 40, count 0 2006.201.08:57:13.34#ibcon#about to read 5, iclass 40, count 0 2006.201.08:57:13.34#ibcon#read 5, iclass 40, count 0 2006.201.08:57:13.34#ibcon#about to read 6, iclass 40, count 0 2006.201.08:57:13.34#ibcon#read 6, iclass 40, count 0 2006.201.08:57:13.34#ibcon#end of sib2, iclass 40, count 0 2006.201.08:57:13.34#ibcon#*mode == 0, iclass 40, count 0 2006.201.08:57:13.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.08:57:13.34#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.08:57:13.34#ibcon#*before write, iclass 40, count 0 2006.201.08:57:13.34#ibcon#enter sib2, iclass 40, count 0 2006.201.08:57:13.34#ibcon#flushed, iclass 40, count 0 2006.201.08:57:13.34#ibcon#about to write, iclass 40, count 0 2006.201.08:57:13.34#ibcon#wrote, iclass 40, count 0 2006.201.08:57:13.34#ibcon#about to read 3, iclass 40, count 0 2006.201.08:57:13.38#ibcon#read 3, iclass 40, count 0 2006.201.08:57:13.38#ibcon#about to read 4, iclass 40, count 0 2006.201.08:57:13.38#ibcon#read 4, iclass 40, count 0 2006.201.08:57:13.38#ibcon#about to read 5, iclass 40, count 0 2006.201.08:57:13.38#ibcon#read 5, iclass 40, count 0 2006.201.08:57:13.38#ibcon#about to read 6, iclass 40, count 0 2006.201.08:57:13.38#ibcon#read 6, iclass 40, count 0 2006.201.08:57:13.38#ibcon#end of sib2, iclass 40, count 0 2006.201.08:57:13.38#ibcon#*after write, iclass 40, count 0 2006.201.08:57:13.38#ibcon#*before return 0, iclass 40, count 0 2006.201.08:57:13.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:13.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:13.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.08:57:13.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.08:57:13.38$vck44/va=5,4 2006.201.08:57:13.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.08:57:13.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.08:57:13.38#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:13.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:13.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:13.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:13.44#ibcon#enter wrdev, iclass 4, count 2 2006.201.08:57:13.44#ibcon#first serial, iclass 4, count 2 2006.201.08:57:13.44#ibcon#enter sib2, iclass 4, count 2 2006.201.08:57:13.44#ibcon#flushed, iclass 4, count 2 2006.201.08:57:13.44#ibcon#about to write, iclass 4, count 2 2006.201.08:57:13.44#ibcon#wrote, iclass 4, count 2 2006.201.08:57:13.44#ibcon#about to read 3, iclass 4, count 2 2006.201.08:57:13.46#ibcon#read 3, iclass 4, count 2 2006.201.08:57:13.46#ibcon#about to read 4, iclass 4, count 2 2006.201.08:57:13.46#ibcon#read 4, iclass 4, count 2 2006.201.08:57:13.46#ibcon#about to read 5, iclass 4, count 2 2006.201.08:57:13.46#ibcon#read 5, iclass 4, count 2 2006.201.08:57:13.46#ibcon#about to read 6, iclass 4, count 2 2006.201.08:57:13.46#ibcon#read 6, iclass 4, count 2 2006.201.08:57:13.46#ibcon#end of sib2, iclass 4, count 2 2006.201.08:57:13.46#ibcon#*mode == 0, iclass 4, count 2 2006.201.08:57:13.46#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.08:57:13.46#ibcon#[25=AT05-04\r\n] 2006.201.08:57:13.46#ibcon#*before write, iclass 4, count 2 2006.201.08:57:13.46#ibcon#enter sib2, iclass 4, count 2 2006.201.08:57:13.46#ibcon#flushed, iclass 4, count 2 2006.201.08:57:13.46#ibcon#about to write, iclass 4, count 2 2006.201.08:57:13.46#ibcon#wrote, iclass 4, count 2 2006.201.08:57:13.46#ibcon#about to read 3, iclass 4, count 2 2006.201.08:57:13.49#ibcon#read 3, iclass 4, count 2 2006.201.08:57:13.49#ibcon#about to read 4, iclass 4, count 2 2006.201.08:57:13.49#ibcon#read 4, iclass 4, count 2 2006.201.08:57:13.49#ibcon#about to read 5, iclass 4, count 2 2006.201.08:57:13.49#ibcon#read 5, iclass 4, count 2 2006.201.08:57:13.49#ibcon#about to read 6, iclass 4, count 2 2006.201.08:57:13.49#ibcon#read 6, iclass 4, count 2 2006.201.08:57:13.49#ibcon#end of sib2, iclass 4, count 2 2006.201.08:57:13.49#ibcon#*after write, iclass 4, count 2 2006.201.08:57:13.49#ibcon#*before return 0, iclass 4, count 2 2006.201.08:57:13.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:13.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:13.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.08:57:13.49#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:13.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:13.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:13.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:13.61#ibcon#enter wrdev, iclass 4, count 0 2006.201.08:57:13.61#ibcon#first serial, iclass 4, count 0 2006.201.08:57:13.61#ibcon#enter sib2, iclass 4, count 0 2006.201.08:57:13.61#ibcon#flushed, iclass 4, count 0 2006.201.08:57:13.61#ibcon#about to write, iclass 4, count 0 2006.201.08:57:13.61#ibcon#wrote, iclass 4, count 0 2006.201.08:57:13.61#ibcon#about to read 3, iclass 4, count 0 2006.201.08:57:13.63#ibcon#read 3, iclass 4, count 0 2006.201.08:57:13.63#ibcon#about to read 4, iclass 4, count 0 2006.201.08:57:13.63#ibcon#read 4, iclass 4, count 0 2006.201.08:57:13.63#ibcon#about to read 5, iclass 4, count 0 2006.201.08:57:13.63#ibcon#read 5, iclass 4, count 0 2006.201.08:57:13.63#ibcon#about to read 6, iclass 4, count 0 2006.201.08:57:13.63#ibcon#read 6, iclass 4, count 0 2006.201.08:57:13.63#ibcon#end of sib2, iclass 4, count 0 2006.201.08:57:13.63#ibcon#*mode == 0, iclass 4, count 0 2006.201.08:57:13.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.08:57:13.63#ibcon#[25=USB\r\n] 2006.201.08:57:13.63#ibcon#*before write, iclass 4, count 0 2006.201.08:57:13.63#ibcon#enter sib2, iclass 4, count 0 2006.201.08:57:13.63#ibcon#flushed, iclass 4, count 0 2006.201.08:57:13.63#ibcon#about to write, iclass 4, count 0 2006.201.08:57:13.63#ibcon#wrote, iclass 4, count 0 2006.201.08:57:13.63#ibcon#about to read 3, iclass 4, count 0 2006.201.08:57:13.66#ibcon#read 3, iclass 4, count 0 2006.201.08:57:13.66#ibcon#about to read 4, iclass 4, count 0 2006.201.08:57:13.66#ibcon#read 4, iclass 4, count 0 2006.201.08:57:13.66#ibcon#about to read 5, iclass 4, count 0 2006.201.08:57:13.66#ibcon#read 5, iclass 4, count 0 2006.201.08:57:13.66#ibcon#about to read 6, iclass 4, count 0 2006.201.08:57:13.66#ibcon#read 6, iclass 4, count 0 2006.201.08:57:13.66#ibcon#end of sib2, iclass 4, count 0 2006.201.08:57:13.66#ibcon#*after write, iclass 4, count 0 2006.201.08:57:13.66#ibcon#*before return 0, iclass 4, count 0 2006.201.08:57:13.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:13.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:13.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.08:57:13.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.08:57:13.66$vck44/valo=6,814.99 2006.201.08:57:13.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.08:57:13.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.08:57:13.66#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:13.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:13.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:13.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:13.66#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:57:13.66#ibcon#first serial, iclass 6, count 0 2006.201.08:57:13.66#ibcon#enter sib2, iclass 6, count 0 2006.201.08:57:13.66#ibcon#flushed, iclass 6, count 0 2006.201.08:57:13.66#ibcon#about to write, iclass 6, count 0 2006.201.08:57:13.66#ibcon#wrote, iclass 6, count 0 2006.201.08:57:13.66#ibcon#about to read 3, iclass 6, count 0 2006.201.08:57:13.68#ibcon#read 3, iclass 6, count 0 2006.201.08:57:13.68#ibcon#about to read 4, iclass 6, count 0 2006.201.08:57:13.68#ibcon#read 4, iclass 6, count 0 2006.201.08:57:13.68#ibcon#about to read 5, iclass 6, count 0 2006.201.08:57:13.68#ibcon#read 5, iclass 6, count 0 2006.201.08:57:13.68#ibcon#about to read 6, iclass 6, count 0 2006.201.08:57:13.68#ibcon#read 6, iclass 6, count 0 2006.201.08:57:13.68#ibcon#end of sib2, iclass 6, count 0 2006.201.08:57:13.68#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:57:13.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:57:13.68#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.08:57:13.68#ibcon#*before write, iclass 6, count 0 2006.201.08:57:13.68#ibcon#enter sib2, iclass 6, count 0 2006.201.08:57:13.68#ibcon#flushed, iclass 6, count 0 2006.201.08:57:13.68#ibcon#about to write, iclass 6, count 0 2006.201.08:57:13.68#ibcon#wrote, iclass 6, count 0 2006.201.08:57:13.68#ibcon#about to read 3, iclass 6, count 0 2006.201.08:57:13.73#ibcon#read 3, iclass 6, count 0 2006.201.08:57:13.73#ibcon#about to read 4, iclass 6, count 0 2006.201.08:57:13.73#ibcon#read 4, iclass 6, count 0 2006.201.08:57:13.73#ibcon#about to read 5, iclass 6, count 0 2006.201.08:57:13.73#ibcon#read 5, iclass 6, count 0 2006.201.08:57:13.73#ibcon#about to read 6, iclass 6, count 0 2006.201.08:57:13.73#ibcon#read 6, iclass 6, count 0 2006.201.08:57:13.73#ibcon#end of sib2, iclass 6, count 0 2006.201.08:57:13.73#ibcon#*after write, iclass 6, count 0 2006.201.08:57:13.73#ibcon#*before return 0, iclass 6, count 0 2006.201.08:57:13.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:13.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:13.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:57:13.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:57:13.73$vck44/va=6,5 2006.201.08:57:13.73#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.08:57:13.73#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.08:57:13.73#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:13.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:13.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:13.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:13.78#ibcon#enter wrdev, iclass 10, count 2 2006.201.08:57:13.78#ibcon#first serial, iclass 10, count 2 2006.201.08:57:13.78#ibcon#enter sib2, iclass 10, count 2 2006.201.08:57:13.78#ibcon#flushed, iclass 10, count 2 2006.201.08:57:13.78#ibcon#about to write, iclass 10, count 2 2006.201.08:57:13.78#ibcon#wrote, iclass 10, count 2 2006.201.08:57:13.78#ibcon#about to read 3, iclass 10, count 2 2006.201.08:57:13.80#ibcon#read 3, iclass 10, count 2 2006.201.08:57:13.80#ibcon#about to read 4, iclass 10, count 2 2006.201.08:57:13.80#ibcon#read 4, iclass 10, count 2 2006.201.08:57:13.80#ibcon#about to read 5, iclass 10, count 2 2006.201.08:57:13.80#ibcon#read 5, iclass 10, count 2 2006.201.08:57:13.80#ibcon#about to read 6, iclass 10, count 2 2006.201.08:57:13.80#ibcon#read 6, iclass 10, count 2 2006.201.08:57:13.80#ibcon#end of sib2, iclass 10, count 2 2006.201.08:57:13.80#ibcon#*mode == 0, iclass 10, count 2 2006.201.08:57:13.80#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.08:57:13.80#ibcon#[25=AT06-05\r\n] 2006.201.08:57:13.80#ibcon#*before write, iclass 10, count 2 2006.201.08:57:13.80#ibcon#enter sib2, iclass 10, count 2 2006.201.08:57:13.80#ibcon#flushed, iclass 10, count 2 2006.201.08:57:13.80#ibcon#about to write, iclass 10, count 2 2006.201.08:57:13.80#ibcon#wrote, iclass 10, count 2 2006.201.08:57:13.80#ibcon#about to read 3, iclass 10, count 2 2006.201.08:57:13.83#ibcon#read 3, iclass 10, count 2 2006.201.08:57:13.83#ibcon#about to read 4, iclass 10, count 2 2006.201.08:57:13.83#ibcon#read 4, iclass 10, count 2 2006.201.08:57:13.83#ibcon#about to read 5, iclass 10, count 2 2006.201.08:57:13.83#ibcon#read 5, iclass 10, count 2 2006.201.08:57:13.83#ibcon#about to read 6, iclass 10, count 2 2006.201.08:57:13.83#ibcon#read 6, iclass 10, count 2 2006.201.08:57:13.83#ibcon#end of sib2, iclass 10, count 2 2006.201.08:57:13.83#ibcon#*after write, iclass 10, count 2 2006.201.08:57:13.83#ibcon#*before return 0, iclass 10, count 2 2006.201.08:57:13.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:13.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:13.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.08:57:13.83#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:13.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:13.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:13.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:13.95#ibcon#enter wrdev, iclass 10, count 0 2006.201.08:57:13.95#ibcon#first serial, iclass 10, count 0 2006.201.08:57:13.95#ibcon#enter sib2, iclass 10, count 0 2006.201.08:57:13.95#ibcon#flushed, iclass 10, count 0 2006.201.08:57:13.95#ibcon#about to write, iclass 10, count 0 2006.201.08:57:13.95#ibcon#wrote, iclass 10, count 0 2006.201.08:57:13.95#ibcon#about to read 3, iclass 10, count 0 2006.201.08:57:13.97#ibcon#read 3, iclass 10, count 0 2006.201.08:57:13.97#ibcon#about to read 4, iclass 10, count 0 2006.201.08:57:13.97#ibcon#read 4, iclass 10, count 0 2006.201.08:57:13.97#ibcon#about to read 5, iclass 10, count 0 2006.201.08:57:13.97#ibcon#read 5, iclass 10, count 0 2006.201.08:57:13.97#ibcon#about to read 6, iclass 10, count 0 2006.201.08:57:13.97#ibcon#read 6, iclass 10, count 0 2006.201.08:57:13.97#ibcon#end of sib2, iclass 10, count 0 2006.201.08:57:13.97#ibcon#*mode == 0, iclass 10, count 0 2006.201.08:57:13.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.08:57:13.97#ibcon#[25=USB\r\n] 2006.201.08:57:13.97#ibcon#*before write, iclass 10, count 0 2006.201.08:57:13.97#ibcon#enter sib2, iclass 10, count 0 2006.201.08:57:13.97#ibcon#flushed, iclass 10, count 0 2006.201.08:57:13.97#ibcon#about to write, iclass 10, count 0 2006.201.08:57:13.97#ibcon#wrote, iclass 10, count 0 2006.201.08:57:13.97#ibcon#about to read 3, iclass 10, count 0 2006.201.08:57:14.00#ibcon#read 3, iclass 10, count 0 2006.201.08:57:14.00#ibcon#about to read 4, iclass 10, count 0 2006.201.08:57:14.00#ibcon#read 4, iclass 10, count 0 2006.201.08:57:14.00#ibcon#about to read 5, iclass 10, count 0 2006.201.08:57:14.00#ibcon#read 5, iclass 10, count 0 2006.201.08:57:14.00#ibcon#about to read 6, iclass 10, count 0 2006.201.08:57:14.00#ibcon#read 6, iclass 10, count 0 2006.201.08:57:14.00#ibcon#end of sib2, iclass 10, count 0 2006.201.08:57:14.00#ibcon#*after write, iclass 10, count 0 2006.201.08:57:14.00#ibcon#*before return 0, iclass 10, count 0 2006.201.08:57:14.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:14.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:14.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.08:57:14.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.08:57:14.00$vck44/valo=7,864.99 2006.201.08:57:14.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.08:57:14.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.08:57:14.00#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:14.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:14.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:14.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:14.00#ibcon#enter wrdev, iclass 12, count 0 2006.201.08:57:14.00#ibcon#first serial, iclass 12, count 0 2006.201.08:57:14.00#ibcon#enter sib2, iclass 12, count 0 2006.201.08:57:14.00#ibcon#flushed, iclass 12, count 0 2006.201.08:57:14.00#ibcon#about to write, iclass 12, count 0 2006.201.08:57:14.00#ibcon#wrote, iclass 12, count 0 2006.201.08:57:14.00#ibcon#about to read 3, iclass 12, count 0 2006.201.08:57:14.02#ibcon#read 3, iclass 12, count 0 2006.201.08:57:14.02#ibcon#about to read 4, iclass 12, count 0 2006.201.08:57:14.02#ibcon#read 4, iclass 12, count 0 2006.201.08:57:14.02#ibcon#about to read 5, iclass 12, count 0 2006.201.08:57:14.02#ibcon#read 5, iclass 12, count 0 2006.201.08:57:14.02#ibcon#about to read 6, iclass 12, count 0 2006.201.08:57:14.02#ibcon#read 6, iclass 12, count 0 2006.201.08:57:14.02#ibcon#end of sib2, iclass 12, count 0 2006.201.08:57:14.02#ibcon#*mode == 0, iclass 12, count 0 2006.201.08:57:14.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.08:57:14.02#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.08:57:14.02#ibcon#*before write, iclass 12, count 0 2006.201.08:57:14.02#ibcon#enter sib2, iclass 12, count 0 2006.201.08:57:14.02#ibcon#flushed, iclass 12, count 0 2006.201.08:57:14.02#ibcon#about to write, iclass 12, count 0 2006.201.08:57:14.02#ibcon#wrote, iclass 12, count 0 2006.201.08:57:14.02#ibcon#about to read 3, iclass 12, count 0 2006.201.08:57:14.07#ibcon#read 3, iclass 12, count 0 2006.201.08:57:14.07#ibcon#about to read 4, iclass 12, count 0 2006.201.08:57:14.07#ibcon#read 4, iclass 12, count 0 2006.201.08:57:14.07#ibcon#about to read 5, iclass 12, count 0 2006.201.08:57:14.07#ibcon#read 5, iclass 12, count 0 2006.201.08:57:14.07#ibcon#about to read 6, iclass 12, count 0 2006.201.08:57:14.07#ibcon#read 6, iclass 12, count 0 2006.201.08:57:14.07#ibcon#end of sib2, iclass 12, count 0 2006.201.08:57:14.07#ibcon#*after write, iclass 12, count 0 2006.201.08:57:14.07#ibcon#*before return 0, iclass 12, count 0 2006.201.08:57:14.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:14.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:14.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.08:57:14.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.08:57:14.07$vck44/va=7,5 2006.201.08:57:14.07#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.08:57:14.07#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.08:57:14.07#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:14.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:14.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:14.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:14.12#ibcon#enter wrdev, iclass 14, count 2 2006.201.08:57:14.12#ibcon#first serial, iclass 14, count 2 2006.201.08:57:14.12#ibcon#enter sib2, iclass 14, count 2 2006.201.08:57:14.12#ibcon#flushed, iclass 14, count 2 2006.201.08:57:14.12#ibcon#about to write, iclass 14, count 2 2006.201.08:57:14.12#ibcon#wrote, iclass 14, count 2 2006.201.08:57:14.12#ibcon#about to read 3, iclass 14, count 2 2006.201.08:57:14.14#ibcon#read 3, iclass 14, count 2 2006.201.08:57:14.14#ibcon#about to read 4, iclass 14, count 2 2006.201.08:57:14.14#ibcon#read 4, iclass 14, count 2 2006.201.08:57:14.14#ibcon#about to read 5, iclass 14, count 2 2006.201.08:57:14.14#ibcon#read 5, iclass 14, count 2 2006.201.08:57:14.14#ibcon#about to read 6, iclass 14, count 2 2006.201.08:57:14.14#ibcon#read 6, iclass 14, count 2 2006.201.08:57:14.14#ibcon#end of sib2, iclass 14, count 2 2006.201.08:57:14.14#ibcon#*mode == 0, iclass 14, count 2 2006.201.08:57:14.14#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.08:57:14.14#ibcon#[25=AT07-05\r\n] 2006.201.08:57:14.14#ibcon#*before write, iclass 14, count 2 2006.201.08:57:14.14#ibcon#enter sib2, iclass 14, count 2 2006.201.08:57:14.14#ibcon#flushed, iclass 14, count 2 2006.201.08:57:14.14#ibcon#about to write, iclass 14, count 2 2006.201.08:57:14.14#ibcon#wrote, iclass 14, count 2 2006.201.08:57:14.14#ibcon#about to read 3, iclass 14, count 2 2006.201.08:57:14.17#ibcon#read 3, iclass 14, count 2 2006.201.08:57:14.17#ibcon#about to read 4, iclass 14, count 2 2006.201.08:57:14.17#ibcon#read 4, iclass 14, count 2 2006.201.08:57:14.17#ibcon#about to read 5, iclass 14, count 2 2006.201.08:57:14.17#ibcon#read 5, iclass 14, count 2 2006.201.08:57:14.17#ibcon#about to read 6, iclass 14, count 2 2006.201.08:57:14.17#ibcon#read 6, iclass 14, count 2 2006.201.08:57:14.17#ibcon#end of sib2, iclass 14, count 2 2006.201.08:57:14.17#ibcon#*after write, iclass 14, count 2 2006.201.08:57:14.17#ibcon#*before return 0, iclass 14, count 2 2006.201.08:57:14.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:14.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:14.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.08:57:14.17#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:14.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:14.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:14.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:14.29#ibcon#enter wrdev, iclass 14, count 0 2006.201.08:57:14.29#ibcon#first serial, iclass 14, count 0 2006.201.08:57:14.29#ibcon#enter sib2, iclass 14, count 0 2006.201.08:57:14.29#ibcon#flushed, iclass 14, count 0 2006.201.08:57:14.29#ibcon#about to write, iclass 14, count 0 2006.201.08:57:14.29#ibcon#wrote, iclass 14, count 0 2006.201.08:57:14.29#ibcon#about to read 3, iclass 14, count 0 2006.201.08:57:14.31#ibcon#read 3, iclass 14, count 0 2006.201.08:57:14.31#ibcon#about to read 4, iclass 14, count 0 2006.201.08:57:14.31#ibcon#read 4, iclass 14, count 0 2006.201.08:57:14.31#ibcon#about to read 5, iclass 14, count 0 2006.201.08:57:14.31#ibcon#read 5, iclass 14, count 0 2006.201.08:57:14.31#ibcon#about to read 6, iclass 14, count 0 2006.201.08:57:14.31#ibcon#read 6, iclass 14, count 0 2006.201.08:57:14.31#ibcon#end of sib2, iclass 14, count 0 2006.201.08:57:14.31#ibcon#*mode == 0, iclass 14, count 0 2006.201.08:57:14.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.08:57:14.31#ibcon#[25=USB\r\n] 2006.201.08:57:14.31#ibcon#*before write, iclass 14, count 0 2006.201.08:57:14.31#ibcon#enter sib2, iclass 14, count 0 2006.201.08:57:14.31#ibcon#flushed, iclass 14, count 0 2006.201.08:57:14.31#ibcon#about to write, iclass 14, count 0 2006.201.08:57:14.31#ibcon#wrote, iclass 14, count 0 2006.201.08:57:14.31#ibcon#about to read 3, iclass 14, count 0 2006.201.08:57:14.34#ibcon#read 3, iclass 14, count 0 2006.201.08:57:14.34#ibcon#about to read 4, iclass 14, count 0 2006.201.08:57:14.34#ibcon#read 4, iclass 14, count 0 2006.201.08:57:14.34#ibcon#about to read 5, iclass 14, count 0 2006.201.08:57:14.34#ibcon#read 5, iclass 14, count 0 2006.201.08:57:14.34#ibcon#about to read 6, iclass 14, count 0 2006.201.08:57:14.34#ibcon#read 6, iclass 14, count 0 2006.201.08:57:14.34#ibcon#end of sib2, iclass 14, count 0 2006.201.08:57:14.34#ibcon#*after write, iclass 14, count 0 2006.201.08:57:14.34#ibcon#*before return 0, iclass 14, count 0 2006.201.08:57:14.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:14.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:14.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.08:57:14.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.08:57:14.34$vck44/valo=8,884.99 2006.201.08:57:14.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.08:57:14.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.08:57:14.34#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:14.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:14.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:14.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:14.34#ibcon#enter wrdev, iclass 16, count 0 2006.201.08:57:14.34#ibcon#first serial, iclass 16, count 0 2006.201.08:57:14.34#ibcon#enter sib2, iclass 16, count 0 2006.201.08:57:14.34#ibcon#flushed, iclass 16, count 0 2006.201.08:57:14.34#ibcon#about to write, iclass 16, count 0 2006.201.08:57:14.34#ibcon#wrote, iclass 16, count 0 2006.201.08:57:14.34#ibcon#about to read 3, iclass 16, count 0 2006.201.08:57:14.36#ibcon#read 3, iclass 16, count 0 2006.201.08:57:14.36#ibcon#about to read 4, iclass 16, count 0 2006.201.08:57:14.36#ibcon#read 4, iclass 16, count 0 2006.201.08:57:14.36#ibcon#about to read 5, iclass 16, count 0 2006.201.08:57:14.36#ibcon#read 5, iclass 16, count 0 2006.201.08:57:14.36#ibcon#about to read 6, iclass 16, count 0 2006.201.08:57:14.36#ibcon#read 6, iclass 16, count 0 2006.201.08:57:14.36#ibcon#end of sib2, iclass 16, count 0 2006.201.08:57:14.36#ibcon#*mode == 0, iclass 16, count 0 2006.201.08:57:14.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.08:57:14.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.08:57:14.36#ibcon#*before write, iclass 16, count 0 2006.201.08:57:14.36#ibcon#enter sib2, iclass 16, count 0 2006.201.08:57:14.36#ibcon#flushed, iclass 16, count 0 2006.201.08:57:14.36#ibcon#about to write, iclass 16, count 0 2006.201.08:57:14.36#ibcon#wrote, iclass 16, count 0 2006.201.08:57:14.36#ibcon#about to read 3, iclass 16, count 0 2006.201.08:57:14.40#ibcon#read 3, iclass 16, count 0 2006.201.08:57:14.40#ibcon#about to read 4, iclass 16, count 0 2006.201.08:57:14.40#ibcon#read 4, iclass 16, count 0 2006.201.08:57:14.40#ibcon#about to read 5, iclass 16, count 0 2006.201.08:57:14.40#ibcon#read 5, iclass 16, count 0 2006.201.08:57:14.40#ibcon#about to read 6, iclass 16, count 0 2006.201.08:57:14.40#ibcon#read 6, iclass 16, count 0 2006.201.08:57:14.40#ibcon#end of sib2, iclass 16, count 0 2006.201.08:57:14.40#ibcon#*after write, iclass 16, count 0 2006.201.08:57:14.40#ibcon#*before return 0, iclass 16, count 0 2006.201.08:57:14.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:14.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:14.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.08:57:14.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.08:57:14.40$vck44/va=8,4 2006.201.08:57:14.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.08:57:14.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.08:57:14.40#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:14.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:57:14.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:57:14.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:57:14.46#ibcon#enter wrdev, iclass 18, count 2 2006.201.08:57:14.46#ibcon#first serial, iclass 18, count 2 2006.201.08:57:14.46#ibcon#enter sib2, iclass 18, count 2 2006.201.08:57:14.46#ibcon#flushed, iclass 18, count 2 2006.201.08:57:14.46#ibcon#about to write, iclass 18, count 2 2006.201.08:57:14.46#ibcon#wrote, iclass 18, count 2 2006.201.08:57:14.46#ibcon#about to read 3, iclass 18, count 2 2006.201.08:57:14.48#ibcon#read 3, iclass 18, count 2 2006.201.08:57:14.48#ibcon#about to read 4, iclass 18, count 2 2006.201.08:57:14.48#ibcon#read 4, iclass 18, count 2 2006.201.08:57:14.48#ibcon#about to read 5, iclass 18, count 2 2006.201.08:57:14.48#ibcon#read 5, iclass 18, count 2 2006.201.08:57:14.48#ibcon#about to read 6, iclass 18, count 2 2006.201.08:57:14.48#ibcon#read 6, iclass 18, count 2 2006.201.08:57:14.48#ibcon#end of sib2, iclass 18, count 2 2006.201.08:57:14.48#ibcon#*mode == 0, iclass 18, count 2 2006.201.08:57:14.48#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.08:57:14.48#ibcon#[25=AT08-04\r\n] 2006.201.08:57:14.48#ibcon#*before write, iclass 18, count 2 2006.201.08:57:14.48#ibcon#enter sib2, iclass 18, count 2 2006.201.08:57:14.48#ibcon#flushed, iclass 18, count 2 2006.201.08:57:14.48#ibcon#about to write, iclass 18, count 2 2006.201.08:57:14.48#ibcon#wrote, iclass 18, count 2 2006.201.08:57:14.48#ibcon#about to read 3, iclass 18, count 2 2006.201.08:57:14.51#ibcon#read 3, iclass 18, count 2 2006.201.08:57:14.51#ibcon#about to read 4, iclass 18, count 2 2006.201.08:57:14.51#ibcon#read 4, iclass 18, count 2 2006.201.08:57:14.51#ibcon#about to read 5, iclass 18, count 2 2006.201.08:57:14.51#ibcon#read 5, iclass 18, count 2 2006.201.08:57:14.51#ibcon#about to read 6, iclass 18, count 2 2006.201.08:57:14.51#ibcon#read 6, iclass 18, count 2 2006.201.08:57:14.51#ibcon#end of sib2, iclass 18, count 2 2006.201.08:57:14.51#ibcon#*after write, iclass 18, count 2 2006.201.08:57:14.51#ibcon#*before return 0, iclass 18, count 2 2006.201.08:57:14.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:57:14.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.08:57:14.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.08:57:14.51#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:14.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:57:14.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:57:14.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:57:14.63#ibcon#enter wrdev, iclass 18, count 0 2006.201.08:57:14.63#ibcon#first serial, iclass 18, count 0 2006.201.08:57:14.63#ibcon#enter sib2, iclass 18, count 0 2006.201.08:57:14.63#ibcon#flushed, iclass 18, count 0 2006.201.08:57:14.63#ibcon#about to write, iclass 18, count 0 2006.201.08:57:14.63#ibcon#wrote, iclass 18, count 0 2006.201.08:57:14.63#ibcon#about to read 3, iclass 18, count 0 2006.201.08:57:14.65#ibcon#read 3, iclass 18, count 0 2006.201.08:57:14.65#ibcon#about to read 4, iclass 18, count 0 2006.201.08:57:14.65#ibcon#read 4, iclass 18, count 0 2006.201.08:57:14.65#ibcon#about to read 5, iclass 18, count 0 2006.201.08:57:14.65#ibcon#read 5, iclass 18, count 0 2006.201.08:57:14.65#ibcon#about to read 6, iclass 18, count 0 2006.201.08:57:14.65#ibcon#read 6, iclass 18, count 0 2006.201.08:57:14.65#ibcon#end of sib2, iclass 18, count 0 2006.201.08:57:14.65#ibcon#*mode == 0, iclass 18, count 0 2006.201.08:57:14.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.08:57:14.65#ibcon#[25=USB\r\n] 2006.201.08:57:14.65#ibcon#*before write, iclass 18, count 0 2006.201.08:57:14.65#ibcon#enter sib2, iclass 18, count 0 2006.201.08:57:14.65#ibcon#flushed, iclass 18, count 0 2006.201.08:57:14.65#ibcon#about to write, iclass 18, count 0 2006.201.08:57:14.65#ibcon#wrote, iclass 18, count 0 2006.201.08:57:14.65#ibcon#about to read 3, iclass 18, count 0 2006.201.08:57:14.68#ibcon#read 3, iclass 18, count 0 2006.201.08:57:14.68#ibcon#about to read 4, iclass 18, count 0 2006.201.08:57:14.68#ibcon#read 4, iclass 18, count 0 2006.201.08:57:14.68#ibcon#about to read 5, iclass 18, count 0 2006.201.08:57:14.68#ibcon#read 5, iclass 18, count 0 2006.201.08:57:14.68#ibcon#about to read 6, iclass 18, count 0 2006.201.08:57:14.68#ibcon#read 6, iclass 18, count 0 2006.201.08:57:14.68#ibcon#end of sib2, iclass 18, count 0 2006.201.08:57:14.68#ibcon#*after write, iclass 18, count 0 2006.201.08:57:14.68#ibcon#*before return 0, iclass 18, count 0 2006.201.08:57:14.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:57:14.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.08:57:14.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.08:57:14.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.08:57:14.68$vck44/vblo=1,629.99 2006.201.08:57:14.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.08:57:14.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.08:57:14.68#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:14.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:57:14.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:57:14.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:57:14.68#ibcon#enter wrdev, iclass 20, count 0 2006.201.08:57:14.68#ibcon#first serial, iclass 20, count 0 2006.201.08:57:14.68#ibcon#enter sib2, iclass 20, count 0 2006.201.08:57:14.68#ibcon#flushed, iclass 20, count 0 2006.201.08:57:14.68#ibcon#about to write, iclass 20, count 0 2006.201.08:57:14.68#ibcon#wrote, iclass 20, count 0 2006.201.08:57:14.68#ibcon#about to read 3, iclass 20, count 0 2006.201.08:57:14.70#ibcon#read 3, iclass 20, count 0 2006.201.08:57:14.70#ibcon#about to read 4, iclass 20, count 0 2006.201.08:57:14.70#ibcon#read 4, iclass 20, count 0 2006.201.08:57:14.70#ibcon#about to read 5, iclass 20, count 0 2006.201.08:57:14.70#ibcon#read 5, iclass 20, count 0 2006.201.08:57:14.70#ibcon#about to read 6, iclass 20, count 0 2006.201.08:57:14.70#ibcon#read 6, iclass 20, count 0 2006.201.08:57:14.70#ibcon#end of sib2, iclass 20, count 0 2006.201.08:57:14.70#ibcon#*mode == 0, iclass 20, count 0 2006.201.08:57:14.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.08:57:14.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.08:57:14.70#ibcon#*before write, iclass 20, count 0 2006.201.08:57:14.70#ibcon#enter sib2, iclass 20, count 0 2006.201.08:57:14.70#ibcon#flushed, iclass 20, count 0 2006.201.08:57:14.70#ibcon#about to write, iclass 20, count 0 2006.201.08:57:14.70#ibcon#wrote, iclass 20, count 0 2006.201.08:57:14.70#ibcon#about to read 3, iclass 20, count 0 2006.201.08:57:14.75#ibcon#read 3, iclass 20, count 0 2006.201.08:57:14.75#ibcon#about to read 4, iclass 20, count 0 2006.201.08:57:14.75#ibcon#read 4, iclass 20, count 0 2006.201.08:57:14.75#ibcon#about to read 5, iclass 20, count 0 2006.201.08:57:14.75#ibcon#read 5, iclass 20, count 0 2006.201.08:57:14.75#ibcon#about to read 6, iclass 20, count 0 2006.201.08:57:14.75#ibcon#read 6, iclass 20, count 0 2006.201.08:57:14.75#ibcon#end of sib2, iclass 20, count 0 2006.201.08:57:14.75#ibcon#*after write, iclass 20, count 0 2006.201.08:57:14.75#ibcon#*before return 0, iclass 20, count 0 2006.201.08:57:14.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:57:14.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.08:57:14.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.08:57:14.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.08:57:14.75$vck44/vb=1,4 2006.201.08:57:14.75#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.08:57:14.75#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.08:57:14.75#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:14.75#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:57:14.75#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:57:14.75#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:57:14.75#ibcon#enter wrdev, iclass 22, count 2 2006.201.08:57:14.75#ibcon#first serial, iclass 22, count 2 2006.201.08:57:14.75#ibcon#enter sib2, iclass 22, count 2 2006.201.08:57:14.75#ibcon#flushed, iclass 22, count 2 2006.201.08:57:14.75#ibcon#about to write, iclass 22, count 2 2006.201.08:57:14.75#ibcon#wrote, iclass 22, count 2 2006.201.08:57:14.75#ibcon#about to read 3, iclass 22, count 2 2006.201.08:57:14.77#ibcon#read 3, iclass 22, count 2 2006.201.08:57:14.77#ibcon#about to read 4, iclass 22, count 2 2006.201.08:57:14.77#ibcon#read 4, iclass 22, count 2 2006.201.08:57:14.77#ibcon#about to read 5, iclass 22, count 2 2006.201.08:57:14.77#ibcon#read 5, iclass 22, count 2 2006.201.08:57:14.77#ibcon#about to read 6, iclass 22, count 2 2006.201.08:57:14.77#ibcon#read 6, iclass 22, count 2 2006.201.08:57:14.77#ibcon#end of sib2, iclass 22, count 2 2006.201.08:57:14.77#ibcon#*mode == 0, iclass 22, count 2 2006.201.08:57:14.77#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.08:57:14.77#ibcon#[27=AT01-04\r\n] 2006.201.08:57:14.77#ibcon#*before write, iclass 22, count 2 2006.201.08:57:14.77#ibcon#enter sib2, iclass 22, count 2 2006.201.08:57:14.77#ibcon#flushed, iclass 22, count 2 2006.201.08:57:14.77#ibcon#about to write, iclass 22, count 2 2006.201.08:57:14.77#ibcon#wrote, iclass 22, count 2 2006.201.08:57:14.77#ibcon#about to read 3, iclass 22, count 2 2006.201.08:57:14.80#ibcon#read 3, iclass 22, count 2 2006.201.08:57:14.80#ibcon#about to read 4, iclass 22, count 2 2006.201.08:57:14.80#ibcon#read 4, iclass 22, count 2 2006.201.08:57:14.80#ibcon#about to read 5, iclass 22, count 2 2006.201.08:57:14.80#ibcon#read 5, iclass 22, count 2 2006.201.08:57:14.80#ibcon#about to read 6, iclass 22, count 2 2006.201.08:57:14.80#ibcon#read 6, iclass 22, count 2 2006.201.08:57:14.80#ibcon#end of sib2, iclass 22, count 2 2006.201.08:57:14.80#ibcon#*after write, iclass 22, count 2 2006.201.08:57:14.80#ibcon#*before return 0, iclass 22, count 2 2006.201.08:57:14.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:57:14.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.08:57:14.80#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.08:57:14.80#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:14.80#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:57:14.92#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:57:14.92#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:57:14.92#ibcon#enter wrdev, iclass 22, count 0 2006.201.08:57:14.92#ibcon#first serial, iclass 22, count 0 2006.201.08:57:14.92#ibcon#enter sib2, iclass 22, count 0 2006.201.08:57:14.92#ibcon#flushed, iclass 22, count 0 2006.201.08:57:14.92#ibcon#about to write, iclass 22, count 0 2006.201.08:57:14.92#ibcon#wrote, iclass 22, count 0 2006.201.08:57:14.92#ibcon#about to read 3, iclass 22, count 0 2006.201.08:57:14.94#ibcon#read 3, iclass 22, count 0 2006.201.08:57:14.94#ibcon#about to read 4, iclass 22, count 0 2006.201.08:57:14.94#ibcon#read 4, iclass 22, count 0 2006.201.08:57:14.94#ibcon#about to read 5, iclass 22, count 0 2006.201.08:57:14.94#ibcon#read 5, iclass 22, count 0 2006.201.08:57:14.94#ibcon#about to read 6, iclass 22, count 0 2006.201.08:57:14.94#ibcon#read 6, iclass 22, count 0 2006.201.08:57:14.94#ibcon#end of sib2, iclass 22, count 0 2006.201.08:57:14.94#ibcon#*mode == 0, iclass 22, count 0 2006.201.08:57:14.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.08:57:14.94#ibcon#[27=USB\r\n] 2006.201.08:57:14.94#ibcon#*before write, iclass 22, count 0 2006.201.08:57:14.94#ibcon#enter sib2, iclass 22, count 0 2006.201.08:57:14.94#ibcon#flushed, iclass 22, count 0 2006.201.08:57:14.94#ibcon#about to write, iclass 22, count 0 2006.201.08:57:14.94#ibcon#wrote, iclass 22, count 0 2006.201.08:57:14.94#ibcon#about to read 3, iclass 22, count 0 2006.201.08:57:14.97#ibcon#read 3, iclass 22, count 0 2006.201.08:57:14.97#ibcon#about to read 4, iclass 22, count 0 2006.201.08:57:14.97#ibcon#read 4, iclass 22, count 0 2006.201.08:57:14.97#ibcon#about to read 5, iclass 22, count 0 2006.201.08:57:14.97#ibcon#read 5, iclass 22, count 0 2006.201.08:57:14.97#ibcon#about to read 6, iclass 22, count 0 2006.201.08:57:14.97#ibcon#read 6, iclass 22, count 0 2006.201.08:57:14.97#ibcon#end of sib2, iclass 22, count 0 2006.201.08:57:14.97#ibcon#*after write, iclass 22, count 0 2006.201.08:57:14.97#ibcon#*before return 0, iclass 22, count 0 2006.201.08:57:14.97#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:57:14.97#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.08:57:14.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.08:57:14.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.08:57:14.97$vck44/vblo=2,634.99 2006.201.08:57:14.97#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.08:57:14.97#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.08:57:14.97#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:14.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:14.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:14.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:14.97#ibcon#enter wrdev, iclass 24, count 0 2006.201.08:57:14.97#ibcon#first serial, iclass 24, count 0 2006.201.08:57:14.97#ibcon#enter sib2, iclass 24, count 0 2006.201.08:57:14.97#ibcon#flushed, iclass 24, count 0 2006.201.08:57:14.97#ibcon#about to write, iclass 24, count 0 2006.201.08:57:14.97#ibcon#wrote, iclass 24, count 0 2006.201.08:57:14.97#ibcon#about to read 3, iclass 24, count 0 2006.201.08:57:14.99#ibcon#read 3, iclass 24, count 0 2006.201.08:57:14.99#ibcon#about to read 4, iclass 24, count 0 2006.201.08:57:14.99#ibcon#read 4, iclass 24, count 0 2006.201.08:57:14.99#ibcon#about to read 5, iclass 24, count 0 2006.201.08:57:14.99#ibcon#read 5, iclass 24, count 0 2006.201.08:57:14.99#ibcon#about to read 6, iclass 24, count 0 2006.201.08:57:14.99#ibcon#read 6, iclass 24, count 0 2006.201.08:57:14.99#ibcon#end of sib2, iclass 24, count 0 2006.201.08:57:14.99#ibcon#*mode == 0, iclass 24, count 0 2006.201.08:57:14.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.08:57:14.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.08:57:14.99#ibcon#*before write, iclass 24, count 0 2006.201.08:57:14.99#ibcon#enter sib2, iclass 24, count 0 2006.201.08:57:14.99#ibcon#flushed, iclass 24, count 0 2006.201.08:57:14.99#ibcon#about to write, iclass 24, count 0 2006.201.08:57:14.99#ibcon#wrote, iclass 24, count 0 2006.201.08:57:14.99#ibcon#about to read 3, iclass 24, count 0 2006.201.08:57:15.03#ibcon#read 3, iclass 24, count 0 2006.201.08:57:15.03#ibcon#about to read 4, iclass 24, count 0 2006.201.08:57:15.03#ibcon#read 4, iclass 24, count 0 2006.201.08:57:15.03#ibcon#about to read 5, iclass 24, count 0 2006.201.08:57:15.03#ibcon#read 5, iclass 24, count 0 2006.201.08:57:15.03#ibcon#about to read 6, iclass 24, count 0 2006.201.08:57:15.03#ibcon#read 6, iclass 24, count 0 2006.201.08:57:15.03#ibcon#end of sib2, iclass 24, count 0 2006.201.08:57:15.03#ibcon#*after write, iclass 24, count 0 2006.201.08:57:15.03#ibcon#*before return 0, iclass 24, count 0 2006.201.08:57:15.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:15.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.08:57:15.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.08:57:15.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.08:57:15.03$vck44/vb=2,5 2006.201.08:57:15.03#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.08:57:15.03#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.08:57:15.03#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:15.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:15.09#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:15.09#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:15.09#ibcon#enter wrdev, iclass 26, count 2 2006.201.08:57:15.09#ibcon#first serial, iclass 26, count 2 2006.201.08:57:15.09#ibcon#enter sib2, iclass 26, count 2 2006.201.08:57:15.09#ibcon#flushed, iclass 26, count 2 2006.201.08:57:15.09#ibcon#about to write, iclass 26, count 2 2006.201.08:57:15.09#ibcon#wrote, iclass 26, count 2 2006.201.08:57:15.09#ibcon#about to read 3, iclass 26, count 2 2006.201.08:57:15.11#ibcon#read 3, iclass 26, count 2 2006.201.08:57:15.11#ibcon#about to read 4, iclass 26, count 2 2006.201.08:57:15.11#ibcon#read 4, iclass 26, count 2 2006.201.08:57:15.11#ibcon#about to read 5, iclass 26, count 2 2006.201.08:57:15.11#ibcon#read 5, iclass 26, count 2 2006.201.08:57:15.11#ibcon#about to read 6, iclass 26, count 2 2006.201.08:57:15.11#ibcon#read 6, iclass 26, count 2 2006.201.08:57:15.11#ibcon#end of sib2, iclass 26, count 2 2006.201.08:57:15.11#ibcon#*mode == 0, iclass 26, count 2 2006.201.08:57:15.11#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.08:57:15.11#ibcon#[27=AT02-05\r\n] 2006.201.08:57:15.11#ibcon#*before write, iclass 26, count 2 2006.201.08:57:15.11#ibcon#enter sib2, iclass 26, count 2 2006.201.08:57:15.11#ibcon#flushed, iclass 26, count 2 2006.201.08:57:15.11#ibcon#about to write, iclass 26, count 2 2006.201.08:57:15.11#ibcon#wrote, iclass 26, count 2 2006.201.08:57:15.11#ibcon#about to read 3, iclass 26, count 2 2006.201.08:57:15.14#ibcon#read 3, iclass 26, count 2 2006.201.08:57:15.14#ibcon#about to read 4, iclass 26, count 2 2006.201.08:57:15.14#ibcon#read 4, iclass 26, count 2 2006.201.08:57:15.14#ibcon#about to read 5, iclass 26, count 2 2006.201.08:57:15.14#ibcon#read 5, iclass 26, count 2 2006.201.08:57:15.14#ibcon#about to read 6, iclass 26, count 2 2006.201.08:57:15.14#ibcon#read 6, iclass 26, count 2 2006.201.08:57:15.14#ibcon#end of sib2, iclass 26, count 2 2006.201.08:57:15.14#ibcon#*after write, iclass 26, count 2 2006.201.08:57:15.14#ibcon#*before return 0, iclass 26, count 2 2006.201.08:57:15.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:15.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.08:57:15.14#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.08:57:15.14#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:15.14#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:15.26#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:15.26#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:15.26#ibcon#enter wrdev, iclass 26, count 0 2006.201.08:57:15.26#ibcon#first serial, iclass 26, count 0 2006.201.08:57:15.26#ibcon#enter sib2, iclass 26, count 0 2006.201.08:57:15.26#ibcon#flushed, iclass 26, count 0 2006.201.08:57:15.26#ibcon#about to write, iclass 26, count 0 2006.201.08:57:15.26#ibcon#wrote, iclass 26, count 0 2006.201.08:57:15.26#ibcon#about to read 3, iclass 26, count 0 2006.201.08:57:15.28#ibcon#read 3, iclass 26, count 0 2006.201.08:57:15.28#ibcon#about to read 4, iclass 26, count 0 2006.201.08:57:15.28#ibcon#read 4, iclass 26, count 0 2006.201.08:57:15.28#ibcon#about to read 5, iclass 26, count 0 2006.201.08:57:15.28#ibcon#read 5, iclass 26, count 0 2006.201.08:57:15.28#ibcon#about to read 6, iclass 26, count 0 2006.201.08:57:15.28#ibcon#read 6, iclass 26, count 0 2006.201.08:57:15.28#ibcon#end of sib2, iclass 26, count 0 2006.201.08:57:15.28#ibcon#*mode == 0, iclass 26, count 0 2006.201.08:57:15.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.08:57:15.28#ibcon#[27=USB\r\n] 2006.201.08:57:15.28#ibcon#*before write, iclass 26, count 0 2006.201.08:57:15.28#ibcon#enter sib2, iclass 26, count 0 2006.201.08:57:15.28#ibcon#flushed, iclass 26, count 0 2006.201.08:57:15.28#ibcon#about to write, iclass 26, count 0 2006.201.08:57:15.28#ibcon#wrote, iclass 26, count 0 2006.201.08:57:15.28#ibcon#about to read 3, iclass 26, count 0 2006.201.08:57:15.31#ibcon#read 3, iclass 26, count 0 2006.201.08:57:15.31#ibcon#about to read 4, iclass 26, count 0 2006.201.08:57:15.31#ibcon#read 4, iclass 26, count 0 2006.201.08:57:15.31#ibcon#about to read 5, iclass 26, count 0 2006.201.08:57:15.31#ibcon#read 5, iclass 26, count 0 2006.201.08:57:15.31#ibcon#about to read 6, iclass 26, count 0 2006.201.08:57:15.31#ibcon#read 6, iclass 26, count 0 2006.201.08:57:15.31#ibcon#end of sib2, iclass 26, count 0 2006.201.08:57:15.31#ibcon#*after write, iclass 26, count 0 2006.201.08:57:15.31#ibcon#*before return 0, iclass 26, count 0 2006.201.08:57:15.31#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:15.31#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.08:57:15.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.08:57:15.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.08:57:15.31$vck44/vblo=3,649.99 2006.201.08:57:15.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.08:57:15.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.08:57:15.31#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:15.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:15.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:15.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:15.31#ibcon#enter wrdev, iclass 28, count 0 2006.201.08:57:15.31#ibcon#first serial, iclass 28, count 0 2006.201.08:57:15.31#ibcon#enter sib2, iclass 28, count 0 2006.201.08:57:15.31#ibcon#flushed, iclass 28, count 0 2006.201.08:57:15.31#ibcon#about to write, iclass 28, count 0 2006.201.08:57:15.31#ibcon#wrote, iclass 28, count 0 2006.201.08:57:15.31#ibcon#about to read 3, iclass 28, count 0 2006.201.08:57:15.33#ibcon#read 3, iclass 28, count 0 2006.201.08:57:15.33#ibcon#about to read 4, iclass 28, count 0 2006.201.08:57:15.33#ibcon#read 4, iclass 28, count 0 2006.201.08:57:15.33#ibcon#about to read 5, iclass 28, count 0 2006.201.08:57:15.33#ibcon#read 5, iclass 28, count 0 2006.201.08:57:15.33#ibcon#about to read 6, iclass 28, count 0 2006.201.08:57:15.33#ibcon#read 6, iclass 28, count 0 2006.201.08:57:15.33#ibcon#end of sib2, iclass 28, count 0 2006.201.08:57:15.33#ibcon#*mode == 0, iclass 28, count 0 2006.201.08:57:15.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.08:57:15.33#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.08:57:15.33#ibcon#*before write, iclass 28, count 0 2006.201.08:57:15.33#ibcon#enter sib2, iclass 28, count 0 2006.201.08:57:15.33#ibcon#flushed, iclass 28, count 0 2006.201.08:57:15.33#ibcon#about to write, iclass 28, count 0 2006.201.08:57:15.33#ibcon#wrote, iclass 28, count 0 2006.201.08:57:15.33#ibcon#about to read 3, iclass 28, count 0 2006.201.08:57:15.37#ibcon#read 3, iclass 28, count 0 2006.201.08:57:15.37#ibcon#about to read 4, iclass 28, count 0 2006.201.08:57:15.37#ibcon#read 4, iclass 28, count 0 2006.201.08:57:15.37#ibcon#about to read 5, iclass 28, count 0 2006.201.08:57:15.37#ibcon#read 5, iclass 28, count 0 2006.201.08:57:15.37#ibcon#about to read 6, iclass 28, count 0 2006.201.08:57:15.37#ibcon#read 6, iclass 28, count 0 2006.201.08:57:15.37#ibcon#end of sib2, iclass 28, count 0 2006.201.08:57:15.37#ibcon#*after write, iclass 28, count 0 2006.201.08:57:15.37#ibcon#*before return 0, iclass 28, count 0 2006.201.08:57:15.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:15.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.08:57:15.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.08:57:15.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.08:57:15.37$vck44/vb=3,4 2006.201.08:57:15.37#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.08:57:15.37#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.08:57:15.37#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:15.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:15.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:15.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:15.43#ibcon#enter wrdev, iclass 30, count 2 2006.201.08:57:15.43#ibcon#first serial, iclass 30, count 2 2006.201.08:57:15.43#ibcon#enter sib2, iclass 30, count 2 2006.201.08:57:15.43#ibcon#flushed, iclass 30, count 2 2006.201.08:57:15.43#ibcon#about to write, iclass 30, count 2 2006.201.08:57:15.43#ibcon#wrote, iclass 30, count 2 2006.201.08:57:15.43#ibcon#about to read 3, iclass 30, count 2 2006.201.08:57:15.45#ibcon#read 3, iclass 30, count 2 2006.201.08:57:15.45#ibcon#about to read 4, iclass 30, count 2 2006.201.08:57:15.45#ibcon#read 4, iclass 30, count 2 2006.201.08:57:15.45#ibcon#about to read 5, iclass 30, count 2 2006.201.08:57:15.45#ibcon#read 5, iclass 30, count 2 2006.201.08:57:15.45#ibcon#about to read 6, iclass 30, count 2 2006.201.08:57:15.45#ibcon#read 6, iclass 30, count 2 2006.201.08:57:15.45#ibcon#end of sib2, iclass 30, count 2 2006.201.08:57:15.45#ibcon#*mode == 0, iclass 30, count 2 2006.201.08:57:15.45#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.08:57:15.45#ibcon#[27=AT03-04\r\n] 2006.201.08:57:15.45#ibcon#*before write, iclass 30, count 2 2006.201.08:57:15.45#ibcon#enter sib2, iclass 30, count 2 2006.201.08:57:15.45#ibcon#flushed, iclass 30, count 2 2006.201.08:57:15.45#ibcon#about to write, iclass 30, count 2 2006.201.08:57:15.45#ibcon#wrote, iclass 30, count 2 2006.201.08:57:15.45#ibcon#about to read 3, iclass 30, count 2 2006.201.08:57:15.48#ibcon#read 3, iclass 30, count 2 2006.201.08:57:15.48#ibcon#about to read 4, iclass 30, count 2 2006.201.08:57:15.48#ibcon#read 4, iclass 30, count 2 2006.201.08:57:15.48#ibcon#about to read 5, iclass 30, count 2 2006.201.08:57:15.48#ibcon#read 5, iclass 30, count 2 2006.201.08:57:15.48#ibcon#about to read 6, iclass 30, count 2 2006.201.08:57:15.48#ibcon#read 6, iclass 30, count 2 2006.201.08:57:15.48#ibcon#end of sib2, iclass 30, count 2 2006.201.08:57:15.48#ibcon#*after write, iclass 30, count 2 2006.201.08:57:15.48#ibcon#*before return 0, iclass 30, count 2 2006.201.08:57:15.48#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:15.48#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.08:57:15.48#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.08:57:15.48#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:15.48#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:15.60#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:15.60#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:15.60#ibcon#enter wrdev, iclass 30, count 0 2006.201.08:57:15.60#ibcon#first serial, iclass 30, count 0 2006.201.08:57:15.60#ibcon#enter sib2, iclass 30, count 0 2006.201.08:57:15.60#ibcon#flushed, iclass 30, count 0 2006.201.08:57:15.60#ibcon#about to write, iclass 30, count 0 2006.201.08:57:15.60#ibcon#wrote, iclass 30, count 0 2006.201.08:57:15.60#ibcon#about to read 3, iclass 30, count 0 2006.201.08:57:15.62#ibcon#read 3, iclass 30, count 0 2006.201.08:57:15.62#ibcon#about to read 4, iclass 30, count 0 2006.201.08:57:15.62#ibcon#read 4, iclass 30, count 0 2006.201.08:57:15.62#ibcon#about to read 5, iclass 30, count 0 2006.201.08:57:15.62#ibcon#read 5, iclass 30, count 0 2006.201.08:57:15.62#ibcon#about to read 6, iclass 30, count 0 2006.201.08:57:15.62#ibcon#read 6, iclass 30, count 0 2006.201.08:57:15.62#ibcon#end of sib2, iclass 30, count 0 2006.201.08:57:15.62#ibcon#*mode == 0, iclass 30, count 0 2006.201.08:57:15.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.08:57:15.62#ibcon#[27=USB\r\n] 2006.201.08:57:15.62#ibcon#*before write, iclass 30, count 0 2006.201.08:57:15.62#ibcon#enter sib2, iclass 30, count 0 2006.201.08:57:15.62#ibcon#flushed, iclass 30, count 0 2006.201.08:57:15.62#ibcon#about to write, iclass 30, count 0 2006.201.08:57:15.62#ibcon#wrote, iclass 30, count 0 2006.201.08:57:15.62#ibcon#about to read 3, iclass 30, count 0 2006.201.08:57:15.65#ibcon#read 3, iclass 30, count 0 2006.201.08:57:15.65#ibcon#about to read 4, iclass 30, count 0 2006.201.08:57:15.65#ibcon#read 4, iclass 30, count 0 2006.201.08:57:15.65#ibcon#about to read 5, iclass 30, count 0 2006.201.08:57:15.65#ibcon#read 5, iclass 30, count 0 2006.201.08:57:15.65#ibcon#about to read 6, iclass 30, count 0 2006.201.08:57:15.65#ibcon#read 6, iclass 30, count 0 2006.201.08:57:15.65#ibcon#end of sib2, iclass 30, count 0 2006.201.08:57:15.65#ibcon#*after write, iclass 30, count 0 2006.201.08:57:15.65#ibcon#*before return 0, iclass 30, count 0 2006.201.08:57:15.65#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:15.65#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.08:57:15.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.08:57:15.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.08:57:15.65$vck44/vblo=4,679.99 2006.201.08:57:15.65#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.08:57:15.65#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.08:57:15.65#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:15.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:15.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:15.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:15.65#ibcon#enter wrdev, iclass 32, count 0 2006.201.08:57:15.65#ibcon#first serial, iclass 32, count 0 2006.201.08:57:15.65#ibcon#enter sib2, iclass 32, count 0 2006.201.08:57:15.65#ibcon#flushed, iclass 32, count 0 2006.201.08:57:15.65#ibcon#about to write, iclass 32, count 0 2006.201.08:57:15.65#ibcon#wrote, iclass 32, count 0 2006.201.08:57:15.65#ibcon#about to read 3, iclass 32, count 0 2006.201.08:57:15.67#ibcon#read 3, iclass 32, count 0 2006.201.08:57:15.67#ibcon#about to read 4, iclass 32, count 0 2006.201.08:57:15.67#ibcon#read 4, iclass 32, count 0 2006.201.08:57:15.67#ibcon#about to read 5, iclass 32, count 0 2006.201.08:57:15.67#ibcon#read 5, iclass 32, count 0 2006.201.08:57:15.67#ibcon#about to read 6, iclass 32, count 0 2006.201.08:57:15.67#ibcon#read 6, iclass 32, count 0 2006.201.08:57:15.67#ibcon#end of sib2, iclass 32, count 0 2006.201.08:57:15.67#ibcon#*mode == 0, iclass 32, count 0 2006.201.08:57:15.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.08:57:15.67#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.08:57:15.67#ibcon#*before write, iclass 32, count 0 2006.201.08:57:15.67#ibcon#enter sib2, iclass 32, count 0 2006.201.08:57:15.67#ibcon#flushed, iclass 32, count 0 2006.201.08:57:15.67#ibcon#about to write, iclass 32, count 0 2006.201.08:57:15.67#ibcon#wrote, iclass 32, count 0 2006.201.08:57:15.67#ibcon#about to read 3, iclass 32, count 0 2006.201.08:57:15.72#ibcon#read 3, iclass 32, count 0 2006.201.08:57:15.72#ibcon#about to read 4, iclass 32, count 0 2006.201.08:57:15.72#ibcon#read 4, iclass 32, count 0 2006.201.08:57:15.72#ibcon#about to read 5, iclass 32, count 0 2006.201.08:57:15.72#ibcon#read 5, iclass 32, count 0 2006.201.08:57:15.72#ibcon#about to read 6, iclass 32, count 0 2006.201.08:57:15.72#ibcon#read 6, iclass 32, count 0 2006.201.08:57:15.72#ibcon#end of sib2, iclass 32, count 0 2006.201.08:57:15.72#ibcon#*after write, iclass 32, count 0 2006.201.08:57:15.72#ibcon#*before return 0, iclass 32, count 0 2006.201.08:57:15.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:15.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.08:57:15.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.08:57:15.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.08:57:15.72$vck44/vb=4,5 2006.201.08:57:15.72#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.08:57:15.72#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.08:57:15.72#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:15.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:15.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:15.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:15.77#ibcon#enter wrdev, iclass 34, count 2 2006.201.08:57:15.77#ibcon#first serial, iclass 34, count 2 2006.201.08:57:15.77#ibcon#enter sib2, iclass 34, count 2 2006.201.08:57:15.77#ibcon#flushed, iclass 34, count 2 2006.201.08:57:15.77#ibcon#about to write, iclass 34, count 2 2006.201.08:57:15.77#ibcon#wrote, iclass 34, count 2 2006.201.08:57:15.77#ibcon#about to read 3, iclass 34, count 2 2006.201.08:57:15.79#ibcon#read 3, iclass 34, count 2 2006.201.08:57:15.79#ibcon#about to read 4, iclass 34, count 2 2006.201.08:57:15.79#ibcon#read 4, iclass 34, count 2 2006.201.08:57:15.79#ibcon#about to read 5, iclass 34, count 2 2006.201.08:57:15.79#ibcon#read 5, iclass 34, count 2 2006.201.08:57:15.79#ibcon#about to read 6, iclass 34, count 2 2006.201.08:57:15.79#ibcon#read 6, iclass 34, count 2 2006.201.08:57:15.79#ibcon#end of sib2, iclass 34, count 2 2006.201.08:57:15.79#ibcon#*mode == 0, iclass 34, count 2 2006.201.08:57:15.79#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.08:57:15.79#ibcon#[27=AT04-05\r\n] 2006.201.08:57:15.79#ibcon#*before write, iclass 34, count 2 2006.201.08:57:15.79#ibcon#enter sib2, iclass 34, count 2 2006.201.08:57:15.79#ibcon#flushed, iclass 34, count 2 2006.201.08:57:15.79#ibcon#about to write, iclass 34, count 2 2006.201.08:57:15.79#ibcon#wrote, iclass 34, count 2 2006.201.08:57:15.79#ibcon#about to read 3, iclass 34, count 2 2006.201.08:57:15.82#ibcon#read 3, iclass 34, count 2 2006.201.08:57:15.82#ibcon#about to read 4, iclass 34, count 2 2006.201.08:57:15.82#ibcon#read 4, iclass 34, count 2 2006.201.08:57:15.82#ibcon#about to read 5, iclass 34, count 2 2006.201.08:57:15.82#ibcon#read 5, iclass 34, count 2 2006.201.08:57:15.82#ibcon#about to read 6, iclass 34, count 2 2006.201.08:57:15.82#ibcon#read 6, iclass 34, count 2 2006.201.08:57:15.82#ibcon#end of sib2, iclass 34, count 2 2006.201.08:57:15.82#ibcon#*after write, iclass 34, count 2 2006.201.08:57:15.82#ibcon#*before return 0, iclass 34, count 2 2006.201.08:57:15.82#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:15.82#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.08:57:15.82#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.08:57:15.82#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:15.82#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:15.94#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:15.94#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:15.94#ibcon#enter wrdev, iclass 34, count 0 2006.201.08:57:15.94#ibcon#first serial, iclass 34, count 0 2006.201.08:57:15.94#ibcon#enter sib2, iclass 34, count 0 2006.201.08:57:15.94#ibcon#flushed, iclass 34, count 0 2006.201.08:57:15.94#ibcon#about to write, iclass 34, count 0 2006.201.08:57:15.94#ibcon#wrote, iclass 34, count 0 2006.201.08:57:15.94#ibcon#about to read 3, iclass 34, count 0 2006.201.08:57:15.96#ibcon#read 3, iclass 34, count 0 2006.201.08:57:15.96#ibcon#about to read 4, iclass 34, count 0 2006.201.08:57:15.96#ibcon#read 4, iclass 34, count 0 2006.201.08:57:15.96#ibcon#about to read 5, iclass 34, count 0 2006.201.08:57:15.96#ibcon#read 5, iclass 34, count 0 2006.201.08:57:15.96#ibcon#about to read 6, iclass 34, count 0 2006.201.08:57:15.96#ibcon#read 6, iclass 34, count 0 2006.201.08:57:15.96#ibcon#end of sib2, iclass 34, count 0 2006.201.08:57:15.96#ibcon#*mode == 0, iclass 34, count 0 2006.201.08:57:15.96#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.08:57:15.96#ibcon#[27=USB\r\n] 2006.201.08:57:15.96#ibcon#*before write, iclass 34, count 0 2006.201.08:57:15.96#ibcon#enter sib2, iclass 34, count 0 2006.201.08:57:15.96#ibcon#flushed, iclass 34, count 0 2006.201.08:57:15.96#ibcon#about to write, iclass 34, count 0 2006.201.08:57:15.96#ibcon#wrote, iclass 34, count 0 2006.201.08:57:15.96#ibcon#about to read 3, iclass 34, count 0 2006.201.08:57:15.99#ibcon#read 3, iclass 34, count 0 2006.201.08:57:15.99#ibcon#about to read 4, iclass 34, count 0 2006.201.08:57:15.99#ibcon#read 4, iclass 34, count 0 2006.201.08:57:15.99#ibcon#about to read 5, iclass 34, count 0 2006.201.08:57:15.99#ibcon#read 5, iclass 34, count 0 2006.201.08:57:15.99#ibcon#about to read 6, iclass 34, count 0 2006.201.08:57:15.99#ibcon#read 6, iclass 34, count 0 2006.201.08:57:15.99#ibcon#end of sib2, iclass 34, count 0 2006.201.08:57:15.99#ibcon#*after write, iclass 34, count 0 2006.201.08:57:15.99#ibcon#*before return 0, iclass 34, count 0 2006.201.08:57:15.99#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:15.99#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.08:57:15.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.08:57:15.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.08:57:15.99$vck44/vblo=5,709.99 2006.201.08:57:15.99#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.08:57:15.99#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.08:57:15.99#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:15.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:15.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:15.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:15.99#ibcon#enter wrdev, iclass 36, count 0 2006.201.08:57:15.99#ibcon#first serial, iclass 36, count 0 2006.201.08:57:15.99#ibcon#enter sib2, iclass 36, count 0 2006.201.08:57:15.99#ibcon#flushed, iclass 36, count 0 2006.201.08:57:15.99#ibcon#about to write, iclass 36, count 0 2006.201.08:57:15.99#ibcon#wrote, iclass 36, count 0 2006.201.08:57:15.99#ibcon#about to read 3, iclass 36, count 0 2006.201.08:57:16.01#ibcon#read 3, iclass 36, count 0 2006.201.08:57:16.01#ibcon#about to read 4, iclass 36, count 0 2006.201.08:57:16.01#ibcon#read 4, iclass 36, count 0 2006.201.08:57:16.01#ibcon#about to read 5, iclass 36, count 0 2006.201.08:57:16.01#ibcon#read 5, iclass 36, count 0 2006.201.08:57:16.01#ibcon#about to read 6, iclass 36, count 0 2006.201.08:57:16.01#ibcon#read 6, iclass 36, count 0 2006.201.08:57:16.01#ibcon#end of sib2, iclass 36, count 0 2006.201.08:57:16.01#ibcon#*mode == 0, iclass 36, count 0 2006.201.08:57:16.01#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.08:57:16.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.08:57:16.01#ibcon#*before write, iclass 36, count 0 2006.201.08:57:16.01#ibcon#enter sib2, iclass 36, count 0 2006.201.08:57:16.01#ibcon#flushed, iclass 36, count 0 2006.201.08:57:16.01#ibcon#about to write, iclass 36, count 0 2006.201.08:57:16.01#ibcon#wrote, iclass 36, count 0 2006.201.08:57:16.01#ibcon#about to read 3, iclass 36, count 0 2006.201.08:57:16.05#ibcon#read 3, iclass 36, count 0 2006.201.08:57:16.05#ibcon#about to read 4, iclass 36, count 0 2006.201.08:57:16.05#ibcon#read 4, iclass 36, count 0 2006.201.08:57:16.05#ibcon#about to read 5, iclass 36, count 0 2006.201.08:57:16.05#ibcon#read 5, iclass 36, count 0 2006.201.08:57:16.05#ibcon#about to read 6, iclass 36, count 0 2006.201.08:57:16.05#ibcon#read 6, iclass 36, count 0 2006.201.08:57:16.05#ibcon#end of sib2, iclass 36, count 0 2006.201.08:57:16.05#ibcon#*after write, iclass 36, count 0 2006.201.08:57:16.05#ibcon#*before return 0, iclass 36, count 0 2006.201.08:57:16.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:16.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.08:57:16.05#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.08:57:16.05#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.08:57:16.05$vck44/vb=5,4 2006.201.08:57:16.05#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.08:57:16.05#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.08:57:16.05#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:16.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:16.11#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:16.11#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:16.11#ibcon#enter wrdev, iclass 38, count 2 2006.201.08:57:16.11#ibcon#first serial, iclass 38, count 2 2006.201.08:57:16.11#ibcon#enter sib2, iclass 38, count 2 2006.201.08:57:16.11#ibcon#flushed, iclass 38, count 2 2006.201.08:57:16.11#ibcon#about to write, iclass 38, count 2 2006.201.08:57:16.11#ibcon#wrote, iclass 38, count 2 2006.201.08:57:16.11#ibcon#about to read 3, iclass 38, count 2 2006.201.08:57:16.13#ibcon#read 3, iclass 38, count 2 2006.201.08:57:16.13#ibcon#about to read 4, iclass 38, count 2 2006.201.08:57:16.13#ibcon#read 4, iclass 38, count 2 2006.201.08:57:16.13#ibcon#about to read 5, iclass 38, count 2 2006.201.08:57:16.13#ibcon#read 5, iclass 38, count 2 2006.201.08:57:16.13#ibcon#about to read 6, iclass 38, count 2 2006.201.08:57:16.13#ibcon#read 6, iclass 38, count 2 2006.201.08:57:16.13#ibcon#end of sib2, iclass 38, count 2 2006.201.08:57:16.13#ibcon#*mode == 0, iclass 38, count 2 2006.201.08:57:16.13#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.08:57:16.13#ibcon#[27=AT05-04\r\n] 2006.201.08:57:16.13#ibcon#*before write, iclass 38, count 2 2006.201.08:57:16.13#ibcon#enter sib2, iclass 38, count 2 2006.201.08:57:16.13#ibcon#flushed, iclass 38, count 2 2006.201.08:57:16.13#ibcon#about to write, iclass 38, count 2 2006.201.08:57:16.13#ibcon#wrote, iclass 38, count 2 2006.201.08:57:16.13#ibcon#about to read 3, iclass 38, count 2 2006.201.08:57:16.16#ibcon#read 3, iclass 38, count 2 2006.201.08:57:16.16#ibcon#about to read 4, iclass 38, count 2 2006.201.08:57:16.16#ibcon#read 4, iclass 38, count 2 2006.201.08:57:16.16#ibcon#about to read 5, iclass 38, count 2 2006.201.08:57:16.16#ibcon#read 5, iclass 38, count 2 2006.201.08:57:16.16#ibcon#about to read 6, iclass 38, count 2 2006.201.08:57:16.16#ibcon#read 6, iclass 38, count 2 2006.201.08:57:16.16#ibcon#end of sib2, iclass 38, count 2 2006.201.08:57:16.16#ibcon#*after write, iclass 38, count 2 2006.201.08:57:16.16#ibcon#*before return 0, iclass 38, count 2 2006.201.08:57:16.16#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:16.16#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.08:57:16.16#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.08:57:16.16#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:16.16#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:16.28#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:16.28#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:16.28#ibcon#enter wrdev, iclass 38, count 0 2006.201.08:57:16.28#ibcon#first serial, iclass 38, count 0 2006.201.08:57:16.28#ibcon#enter sib2, iclass 38, count 0 2006.201.08:57:16.28#ibcon#flushed, iclass 38, count 0 2006.201.08:57:16.28#ibcon#about to write, iclass 38, count 0 2006.201.08:57:16.28#ibcon#wrote, iclass 38, count 0 2006.201.08:57:16.28#ibcon#about to read 3, iclass 38, count 0 2006.201.08:57:16.30#ibcon#read 3, iclass 38, count 0 2006.201.08:57:16.30#ibcon#about to read 4, iclass 38, count 0 2006.201.08:57:16.30#ibcon#read 4, iclass 38, count 0 2006.201.08:57:16.30#ibcon#about to read 5, iclass 38, count 0 2006.201.08:57:16.30#ibcon#read 5, iclass 38, count 0 2006.201.08:57:16.30#ibcon#about to read 6, iclass 38, count 0 2006.201.08:57:16.30#ibcon#read 6, iclass 38, count 0 2006.201.08:57:16.30#ibcon#end of sib2, iclass 38, count 0 2006.201.08:57:16.30#ibcon#*mode == 0, iclass 38, count 0 2006.201.08:57:16.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.08:57:16.30#ibcon#[27=USB\r\n] 2006.201.08:57:16.30#ibcon#*before write, iclass 38, count 0 2006.201.08:57:16.30#ibcon#enter sib2, iclass 38, count 0 2006.201.08:57:16.30#ibcon#flushed, iclass 38, count 0 2006.201.08:57:16.30#ibcon#about to write, iclass 38, count 0 2006.201.08:57:16.30#ibcon#wrote, iclass 38, count 0 2006.201.08:57:16.30#ibcon#about to read 3, iclass 38, count 0 2006.201.08:57:16.33#ibcon#read 3, iclass 38, count 0 2006.201.08:57:16.33#ibcon#about to read 4, iclass 38, count 0 2006.201.08:57:16.33#ibcon#read 4, iclass 38, count 0 2006.201.08:57:16.33#ibcon#about to read 5, iclass 38, count 0 2006.201.08:57:16.33#ibcon#read 5, iclass 38, count 0 2006.201.08:57:16.33#ibcon#about to read 6, iclass 38, count 0 2006.201.08:57:16.33#ibcon#read 6, iclass 38, count 0 2006.201.08:57:16.33#ibcon#end of sib2, iclass 38, count 0 2006.201.08:57:16.33#ibcon#*after write, iclass 38, count 0 2006.201.08:57:16.33#ibcon#*before return 0, iclass 38, count 0 2006.201.08:57:16.33#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:16.33#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.08:57:16.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.08:57:16.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.08:57:16.33$vck44/vblo=6,719.99 2006.201.08:57:16.33#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.08:57:16.33#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.08:57:16.33#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:16.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:16.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:16.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:16.33#ibcon#enter wrdev, iclass 40, count 0 2006.201.08:57:16.33#ibcon#first serial, iclass 40, count 0 2006.201.08:57:16.33#ibcon#enter sib2, iclass 40, count 0 2006.201.08:57:16.33#ibcon#flushed, iclass 40, count 0 2006.201.08:57:16.33#ibcon#about to write, iclass 40, count 0 2006.201.08:57:16.33#ibcon#wrote, iclass 40, count 0 2006.201.08:57:16.33#ibcon#about to read 3, iclass 40, count 0 2006.201.08:57:16.35#ibcon#read 3, iclass 40, count 0 2006.201.08:57:16.35#ibcon#about to read 4, iclass 40, count 0 2006.201.08:57:16.35#ibcon#read 4, iclass 40, count 0 2006.201.08:57:16.35#ibcon#about to read 5, iclass 40, count 0 2006.201.08:57:16.35#ibcon#read 5, iclass 40, count 0 2006.201.08:57:16.35#ibcon#about to read 6, iclass 40, count 0 2006.201.08:57:16.35#ibcon#read 6, iclass 40, count 0 2006.201.08:57:16.35#ibcon#end of sib2, iclass 40, count 0 2006.201.08:57:16.35#ibcon#*mode == 0, iclass 40, count 0 2006.201.08:57:16.35#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.08:57:16.35#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.08:57:16.35#ibcon#*before write, iclass 40, count 0 2006.201.08:57:16.35#ibcon#enter sib2, iclass 40, count 0 2006.201.08:57:16.35#ibcon#flushed, iclass 40, count 0 2006.201.08:57:16.35#ibcon#about to write, iclass 40, count 0 2006.201.08:57:16.35#ibcon#wrote, iclass 40, count 0 2006.201.08:57:16.35#ibcon#about to read 3, iclass 40, count 0 2006.201.08:57:16.40#ibcon#read 3, iclass 40, count 0 2006.201.08:57:16.40#ibcon#about to read 4, iclass 40, count 0 2006.201.08:57:16.40#ibcon#read 4, iclass 40, count 0 2006.201.08:57:16.40#ibcon#about to read 5, iclass 40, count 0 2006.201.08:57:16.40#ibcon#read 5, iclass 40, count 0 2006.201.08:57:16.40#ibcon#about to read 6, iclass 40, count 0 2006.201.08:57:16.40#ibcon#read 6, iclass 40, count 0 2006.201.08:57:16.40#ibcon#end of sib2, iclass 40, count 0 2006.201.08:57:16.40#ibcon#*after write, iclass 40, count 0 2006.201.08:57:16.40#ibcon#*before return 0, iclass 40, count 0 2006.201.08:57:16.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:16.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.08:57:16.40#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.08:57:16.40#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.08:57:16.40$vck44/vb=6,4 2006.201.08:57:16.40#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.08:57:16.40#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.08:57:16.40#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:16.40#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:16.45#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:16.45#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:16.45#ibcon#enter wrdev, iclass 4, count 2 2006.201.08:57:16.45#ibcon#first serial, iclass 4, count 2 2006.201.08:57:16.45#ibcon#enter sib2, iclass 4, count 2 2006.201.08:57:16.45#ibcon#flushed, iclass 4, count 2 2006.201.08:57:16.45#ibcon#about to write, iclass 4, count 2 2006.201.08:57:16.45#ibcon#wrote, iclass 4, count 2 2006.201.08:57:16.45#ibcon#about to read 3, iclass 4, count 2 2006.201.08:57:16.47#ibcon#read 3, iclass 4, count 2 2006.201.08:57:16.47#ibcon#about to read 4, iclass 4, count 2 2006.201.08:57:16.47#ibcon#read 4, iclass 4, count 2 2006.201.08:57:16.47#ibcon#about to read 5, iclass 4, count 2 2006.201.08:57:16.47#ibcon#read 5, iclass 4, count 2 2006.201.08:57:16.47#ibcon#about to read 6, iclass 4, count 2 2006.201.08:57:16.47#ibcon#read 6, iclass 4, count 2 2006.201.08:57:16.47#ibcon#end of sib2, iclass 4, count 2 2006.201.08:57:16.47#ibcon#*mode == 0, iclass 4, count 2 2006.201.08:57:16.47#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.08:57:16.47#ibcon#[27=AT06-04\r\n] 2006.201.08:57:16.47#ibcon#*before write, iclass 4, count 2 2006.201.08:57:16.47#ibcon#enter sib2, iclass 4, count 2 2006.201.08:57:16.47#ibcon#flushed, iclass 4, count 2 2006.201.08:57:16.47#ibcon#about to write, iclass 4, count 2 2006.201.08:57:16.47#ibcon#wrote, iclass 4, count 2 2006.201.08:57:16.47#ibcon#about to read 3, iclass 4, count 2 2006.201.08:57:16.50#ibcon#read 3, iclass 4, count 2 2006.201.08:57:16.50#ibcon#about to read 4, iclass 4, count 2 2006.201.08:57:16.50#ibcon#read 4, iclass 4, count 2 2006.201.08:57:16.50#ibcon#about to read 5, iclass 4, count 2 2006.201.08:57:16.50#ibcon#read 5, iclass 4, count 2 2006.201.08:57:16.50#ibcon#about to read 6, iclass 4, count 2 2006.201.08:57:16.50#ibcon#read 6, iclass 4, count 2 2006.201.08:57:16.50#ibcon#end of sib2, iclass 4, count 2 2006.201.08:57:16.50#ibcon#*after write, iclass 4, count 2 2006.201.08:57:16.50#ibcon#*before return 0, iclass 4, count 2 2006.201.08:57:16.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:16.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.08:57:16.50#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.08:57:16.50#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:16.50#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:16.62#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:16.62#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:16.62#ibcon#enter wrdev, iclass 4, count 0 2006.201.08:57:16.62#ibcon#first serial, iclass 4, count 0 2006.201.08:57:16.62#ibcon#enter sib2, iclass 4, count 0 2006.201.08:57:16.62#ibcon#flushed, iclass 4, count 0 2006.201.08:57:16.62#ibcon#about to write, iclass 4, count 0 2006.201.08:57:16.62#ibcon#wrote, iclass 4, count 0 2006.201.08:57:16.62#ibcon#about to read 3, iclass 4, count 0 2006.201.08:57:16.64#ibcon#read 3, iclass 4, count 0 2006.201.08:57:16.64#ibcon#about to read 4, iclass 4, count 0 2006.201.08:57:16.64#ibcon#read 4, iclass 4, count 0 2006.201.08:57:16.64#ibcon#about to read 5, iclass 4, count 0 2006.201.08:57:16.64#ibcon#read 5, iclass 4, count 0 2006.201.08:57:16.64#ibcon#about to read 6, iclass 4, count 0 2006.201.08:57:16.64#ibcon#read 6, iclass 4, count 0 2006.201.08:57:16.64#ibcon#end of sib2, iclass 4, count 0 2006.201.08:57:16.64#ibcon#*mode == 0, iclass 4, count 0 2006.201.08:57:16.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.08:57:16.64#ibcon#[27=USB\r\n] 2006.201.08:57:16.64#ibcon#*before write, iclass 4, count 0 2006.201.08:57:16.64#ibcon#enter sib2, iclass 4, count 0 2006.201.08:57:16.64#ibcon#flushed, iclass 4, count 0 2006.201.08:57:16.64#ibcon#about to write, iclass 4, count 0 2006.201.08:57:16.64#ibcon#wrote, iclass 4, count 0 2006.201.08:57:16.64#ibcon#about to read 3, iclass 4, count 0 2006.201.08:57:16.67#ibcon#read 3, iclass 4, count 0 2006.201.08:57:16.67#ibcon#about to read 4, iclass 4, count 0 2006.201.08:57:16.67#ibcon#read 4, iclass 4, count 0 2006.201.08:57:16.67#ibcon#about to read 5, iclass 4, count 0 2006.201.08:57:16.67#ibcon#read 5, iclass 4, count 0 2006.201.08:57:16.67#ibcon#about to read 6, iclass 4, count 0 2006.201.08:57:16.67#ibcon#read 6, iclass 4, count 0 2006.201.08:57:16.67#ibcon#end of sib2, iclass 4, count 0 2006.201.08:57:16.67#ibcon#*after write, iclass 4, count 0 2006.201.08:57:16.67#ibcon#*before return 0, iclass 4, count 0 2006.201.08:57:16.67#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:16.67#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.08:57:16.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.08:57:16.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.08:57:16.67$vck44/vblo=7,734.99 2006.201.08:57:16.67#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.08:57:16.67#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.08:57:16.67#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:16.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:16.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:16.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:16.67#ibcon#enter wrdev, iclass 6, count 0 2006.201.08:57:16.67#ibcon#first serial, iclass 6, count 0 2006.201.08:57:16.67#ibcon#enter sib2, iclass 6, count 0 2006.201.08:57:16.67#ibcon#flushed, iclass 6, count 0 2006.201.08:57:16.67#ibcon#about to write, iclass 6, count 0 2006.201.08:57:16.67#ibcon#wrote, iclass 6, count 0 2006.201.08:57:16.67#ibcon#about to read 3, iclass 6, count 0 2006.201.08:57:16.69#ibcon#read 3, iclass 6, count 0 2006.201.08:57:16.69#ibcon#about to read 4, iclass 6, count 0 2006.201.08:57:16.69#ibcon#read 4, iclass 6, count 0 2006.201.08:57:16.69#ibcon#about to read 5, iclass 6, count 0 2006.201.08:57:16.69#ibcon#read 5, iclass 6, count 0 2006.201.08:57:16.69#ibcon#about to read 6, iclass 6, count 0 2006.201.08:57:16.69#ibcon#read 6, iclass 6, count 0 2006.201.08:57:16.69#ibcon#end of sib2, iclass 6, count 0 2006.201.08:57:16.69#ibcon#*mode == 0, iclass 6, count 0 2006.201.08:57:16.69#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.08:57:16.69#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.08:57:16.69#ibcon#*before write, iclass 6, count 0 2006.201.08:57:16.69#ibcon#enter sib2, iclass 6, count 0 2006.201.08:57:16.69#ibcon#flushed, iclass 6, count 0 2006.201.08:57:16.69#ibcon#about to write, iclass 6, count 0 2006.201.08:57:16.69#ibcon#wrote, iclass 6, count 0 2006.201.08:57:16.69#ibcon#about to read 3, iclass 6, count 0 2006.201.08:57:16.73#ibcon#read 3, iclass 6, count 0 2006.201.08:57:16.73#ibcon#about to read 4, iclass 6, count 0 2006.201.08:57:16.73#ibcon#read 4, iclass 6, count 0 2006.201.08:57:16.73#ibcon#about to read 5, iclass 6, count 0 2006.201.08:57:16.73#ibcon#read 5, iclass 6, count 0 2006.201.08:57:16.73#ibcon#about to read 6, iclass 6, count 0 2006.201.08:57:16.73#ibcon#read 6, iclass 6, count 0 2006.201.08:57:16.73#ibcon#end of sib2, iclass 6, count 0 2006.201.08:57:16.73#ibcon#*after write, iclass 6, count 0 2006.201.08:57:16.73#ibcon#*before return 0, iclass 6, count 0 2006.201.08:57:16.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:16.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.08:57:16.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.08:57:16.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.08:57:16.73$vck44/vb=7,4 2006.201.08:57:16.73#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.08:57:16.73#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.08:57:16.73#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:16.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:16.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:16.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:16.79#ibcon#enter wrdev, iclass 10, count 2 2006.201.08:57:16.79#ibcon#first serial, iclass 10, count 2 2006.201.08:57:16.79#ibcon#enter sib2, iclass 10, count 2 2006.201.08:57:16.79#ibcon#flushed, iclass 10, count 2 2006.201.08:57:16.79#ibcon#about to write, iclass 10, count 2 2006.201.08:57:16.79#ibcon#wrote, iclass 10, count 2 2006.201.08:57:16.79#ibcon#about to read 3, iclass 10, count 2 2006.201.08:57:16.81#ibcon#read 3, iclass 10, count 2 2006.201.08:57:16.81#ibcon#about to read 4, iclass 10, count 2 2006.201.08:57:16.81#ibcon#read 4, iclass 10, count 2 2006.201.08:57:16.81#ibcon#about to read 5, iclass 10, count 2 2006.201.08:57:16.81#ibcon#read 5, iclass 10, count 2 2006.201.08:57:16.81#ibcon#about to read 6, iclass 10, count 2 2006.201.08:57:16.81#ibcon#read 6, iclass 10, count 2 2006.201.08:57:16.81#ibcon#end of sib2, iclass 10, count 2 2006.201.08:57:16.81#ibcon#*mode == 0, iclass 10, count 2 2006.201.08:57:16.81#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.08:57:16.81#ibcon#[27=AT07-04\r\n] 2006.201.08:57:16.81#ibcon#*before write, iclass 10, count 2 2006.201.08:57:16.81#ibcon#enter sib2, iclass 10, count 2 2006.201.08:57:16.81#ibcon#flushed, iclass 10, count 2 2006.201.08:57:16.81#ibcon#about to write, iclass 10, count 2 2006.201.08:57:16.81#ibcon#wrote, iclass 10, count 2 2006.201.08:57:16.81#ibcon#about to read 3, iclass 10, count 2 2006.201.08:57:16.84#ibcon#read 3, iclass 10, count 2 2006.201.08:57:16.84#ibcon#about to read 4, iclass 10, count 2 2006.201.08:57:16.84#ibcon#read 4, iclass 10, count 2 2006.201.08:57:16.84#ibcon#about to read 5, iclass 10, count 2 2006.201.08:57:16.84#ibcon#read 5, iclass 10, count 2 2006.201.08:57:16.84#ibcon#about to read 6, iclass 10, count 2 2006.201.08:57:16.84#ibcon#read 6, iclass 10, count 2 2006.201.08:57:16.84#ibcon#end of sib2, iclass 10, count 2 2006.201.08:57:16.84#ibcon#*after write, iclass 10, count 2 2006.201.08:57:16.84#ibcon#*before return 0, iclass 10, count 2 2006.201.08:57:16.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:16.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.08:57:16.84#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.08:57:16.84#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:16.84#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:16.96#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:16.96#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:16.96#ibcon#enter wrdev, iclass 10, count 0 2006.201.08:57:16.96#ibcon#first serial, iclass 10, count 0 2006.201.08:57:16.96#ibcon#enter sib2, iclass 10, count 0 2006.201.08:57:16.96#ibcon#flushed, iclass 10, count 0 2006.201.08:57:16.96#ibcon#about to write, iclass 10, count 0 2006.201.08:57:16.96#ibcon#wrote, iclass 10, count 0 2006.201.08:57:16.96#ibcon#about to read 3, iclass 10, count 0 2006.201.08:57:16.98#ibcon#read 3, iclass 10, count 0 2006.201.08:57:16.98#ibcon#about to read 4, iclass 10, count 0 2006.201.08:57:16.98#ibcon#read 4, iclass 10, count 0 2006.201.08:57:16.98#ibcon#about to read 5, iclass 10, count 0 2006.201.08:57:16.98#ibcon#read 5, iclass 10, count 0 2006.201.08:57:16.98#ibcon#about to read 6, iclass 10, count 0 2006.201.08:57:16.98#ibcon#read 6, iclass 10, count 0 2006.201.08:57:16.98#ibcon#end of sib2, iclass 10, count 0 2006.201.08:57:16.98#ibcon#*mode == 0, iclass 10, count 0 2006.201.08:57:16.98#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.08:57:16.98#ibcon#[27=USB\r\n] 2006.201.08:57:16.98#ibcon#*before write, iclass 10, count 0 2006.201.08:57:16.98#ibcon#enter sib2, iclass 10, count 0 2006.201.08:57:16.98#ibcon#flushed, iclass 10, count 0 2006.201.08:57:16.98#ibcon#about to write, iclass 10, count 0 2006.201.08:57:16.98#ibcon#wrote, iclass 10, count 0 2006.201.08:57:16.98#ibcon#about to read 3, iclass 10, count 0 2006.201.08:57:17.01#ibcon#read 3, iclass 10, count 0 2006.201.08:57:17.01#ibcon#about to read 4, iclass 10, count 0 2006.201.08:57:17.01#ibcon#read 4, iclass 10, count 0 2006.201.08:57:17.01#ibcon#about to read 5, iclass 10, count 0 2006.201.08:57:17.01#ibcon#read 5, iclass 10, count 0 2006.201.08:57:17.01#ibcon#about to read 6, iclass 10, count 0 2006.201.08:57:17.01#ibcon#read 6, iclass 10, count 0 2006.201.08:57:17.01#ibcon#end of sib2, iclass 10, count 0 2006.201.08:57:17.01#ibcon#*after write, iclass 10, count 0 2006.201.08:57:17.01#ibcon#*before return 0, iclass 10, count 0 2006.201.08:57:17.01#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:17.01#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.08:57:17.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.08:57:17.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.08:57:17.01$vck44/vblo=8,744.99 2006.201.08:57:17.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.08:57:17.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.08:57:17.01#ibcon#ireg 17 cls_cnt 0 2006.201.08:57:17.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:17.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:17.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:17.01#ibcon#enter wrdev, iclass 12, count 0 2006.201.08:57:17.01#ibcon#first serial, iclass 12, count 0 2006.201.08:57:17.01#ibcon#enter sib2, iclass 12, count 0 2006.201.08:57:17.01#ibcon#flushed, iclass 12, count 0 2006.201.08:57:17.01#ibcon#about to write, iclass 12, count 0 2006.201.08:57:17.01#ibcon#wrote, iclass 12, count 0 2006.201.08:57:17.01#ibcon#about to read 3, iclass 12, count 0 2006.201.08:57:17.03#ibcon#read 3, iclass 12, count 0 2006.201.08:57:17.03#ibcon#about to read 4, iclass 12, count 0 2006.201.08:57:17.03#ibcon#read 4, iclass 12, count 0 2006.201.08:57:17.03#ibcon#about to read 5, iclass 12, count 0 2006.201.08:57:17.03#ibcon#read 5, iclass 12, count 0 2006.201.08:57:17.03#ibcon#about to read 6, iclass 12, count 0 2006.201.08:57:17.03#ibcon#read 6, iclass 12, count 0 2006.201.08:57:17.03#ibcon#end of sib2, iclass 12, count 0 2006.201.08:57:17.03#ibcon#*mode == 0, iclass 12, count 0 2006.201.08:57:17.03#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.08:57:17.03#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.08:57:17.03#ibcon#*before write, iclass 12, count 0 2006.201.08:57:17.03#ibcon#enter sib2, iclass 12, count 0 2006.201.08:57:17.03#ibcon#flushed, iclass 12, count 0 2006.201.08:57:17.03#ibcon#about to write, iclass 12, count 0 2006.201.08:57:17.03#ibcon#wrote, iclass 12, count 0 2006.201.08:57:17.03#ibcon#about to read 3, iclass 12, count 0 2006.201.08:57:17.07#ibcon#read 3, iclass 12, count 0 2006.201.08:57:17.07#ibcon#about to read 4, iclass 12, count 0 2006.201.08:57:17.07#ibcon#read 4, iclass 12, count 0 2006.201.08:57:17.07#ibcon#about to read 5, iclass 12, count 0 2006.201.08:57:17.07#ibcon#read 5, iclass 12, count 0 2006.201.08:57:17.07#ibcon#about to read 6, iclass 12, count 0 2006.201.08:57:17.07#ibcon#read 6, iclass 12, count 0 2006.201.08:57:17.07#ibcon#end of sib2, iclass 12, count 0 2006.201.08:57:17.07#ibcon#*after write, iclass 12, count 0 2006.201.08:57:17.07#ibcon#*before return 0, iclass 12, count 0 2006.201.08:57:17.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:17.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.08:57:17.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.08:57:17.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.08:57:17.07$vck44/vb=8,4 2006.201.08:57:17.07#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.08:57:17.07#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.08:57:17.07#ibcon#ireg 11 cls_cnt 2 2006.201.08:57:17.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:17.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:17.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:17.13#ibcon#enter wrdev, iclass 14, count 2 2006.201.08:57:17.13#ibcon#first serial, iclass 14, count 2 2006.201.08:57:17.13#ibcon#enter sib2, iclass 14, count 2 2006.201.08:57:17.13#ibcon#flushed, iclass 14, count 2 2006.201.08:57:17.13#ibcon#about to write, iclass 14, count 2 2006.201.08:57:17.13#ibcon#wrote, iclass 14, count 2 2006.201.08:57:17.13#ibcon#about to read 3, iclass 14, count 2 2006.201.08:57:17.15#ibcon#read 3, iclass 14, count 2 2006.201.08:57:17.15#ibcon#about to read 4, iclass 14, count 2 2006.201.08:57:17.15#ibcon#read 4, iclass 14, count 2 2006.201.08:57:17.15#ibcon#about to read 5, iclass 14, count 2 2006.201.08:57:17.15#ibcon#read 5, iclass 14, count 2 2006.201.08:57:17.15#ibcon#about to read 6, iclass 14, count 2 2006.201.08:57:17.15#ibcon#read 6, iclass 14, count 2 2006.201.08:57:17.15#ibcon#end of sib2, iclass 14, count 2 2006.201.08:57:17.15#ibcon#*mode == 0, iclass 14, count 2 2006.201.08:57:17.15#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.08:57:17.15#ibcon#[27=AT08-04\r\n] 2006.201.08:57:17.15#ibcon#*before write, iclass 14, count 2 2006.201.08:57:17.15#ibcon#enter sib2, iclass 14, count 2 2006.201.08:57:17.15#ibcon#flushed, iclass 14, count 2 2006.201.08:57:17.15#ibcon#about to write, iclass 14, count 2 2006.201.08:57:17.15#ibcon#wrote, iclass 14, count 2 2006.201.08:57:17.15#ibcon#about to read 3, iclass 14, count 2 2006.201.08:57:17.18#ibcon#read 3, iclass 14, count 2 2006.201.08:57:17.18#ibcon#about to read 4, iclass 14, count 2 2006.201.08:57:17.18#ibcon#read 4, iclass 14, count 2 2006.201.08:57:17.18#ibcon#about to read 5, iclass 14, count 2 2006.201.08:57:17.18#ibcon#read 5, iclass 14, count 2 2006.201.08:57:17.18#ibcon#about to read 6, iclass 14, count 2 2006.201.08:57:17.18#ibcon#read 6, iclass 14, count 2 2006.201.08:57:17.18#ibcon#end of sib2, iclass 14, count 2 2006.201.08:57:17.18#ibcon#*after write, iclass 14, count 2 2006.201.08:57:17.18#ibcon#*before return 0, iclass 14, count 2 2006.201.08:57:17.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:17.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.08:57:17.18#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.08:57:17.18#ibcon#ireg 7 cls_cnt 0 2006.201.08:57:17.18#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:17.30#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:17.30#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:17.30#ibcon#enter wrdev, iclass 14, count 0 2006.201.08:57:17.30#ibcon#first serial, iclass 14, count 0 2006.201.08:57:17.30#ibcon#enter sib2, iclass 14, count 0 2006.201.08:57:17.30#ibcon#flushed, iclass 14, count 0 2006.201.08:57:17.30#ibcon#about to write, iclass 14, count 0 2006.201.08:57:17.30#ibcon#wrote, iclass 14, count 0 2006.201.08:57:17.30#ibcon#about to read 3, iclass 14, count 0 2006.201.08:57:17.32#ibcon#read 3, iclass 14, count 0 2006.201.08:57:17.32#ibcon#about to read 4, iclass 14, count 0 2006.201.08:57:17.32#ibcon#read 4, iclass 14, count 0 2006.201.08:57:17.32#ibcon#about to read 5, iclass 14, count 0 2006.201.08:57:17.32#ibcon#read 5, iclass 14, count 0 2006.201.08:57:17.32#ibcon#about to read 6, iclass 14, count 0 2006.201.08:57:17.32#ibcon#read 6, iclass 14, count 0 2006.201.08:57:17.32#ibcon#end of sib2, iclass 14, count 0 2006.201.08:57:17.32#ibcon#*mode == 0, iclass 14, count 0 2006.201.08:57:17.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.08:57:17.32#ibcon#[27=USB\r\n] 2006.201.08:57:17.32#ibcon#*before write, iclass 14, count 0 2006.201.08:57:17.32#ibcon#enter sib2, iclass 14, count 0 2006.201.08:57:17.32#ibcon#flushed, iclass 14, count 0 2006.201.08:57:17.32#ibcon#about to write, iclass 14, count 0 2006.201.08:57:17.32#ibcon#wrote, iclass 14, count 0 2006.201.08:57:17.32#ibcon#about to read 3, iclass 14, count 0 2006.201.08:57:17.35#ibcon#read 3, iclass 14, count 0 2006.201.08:57:17.35#ibcon#about to read 4, iclass 14, count 0 2006.201.08:57:17.35#ibcon#read 4, iclass 14, count 0 2006.201.08:57:17.35#ibcon#about to read 5, iclass 14, count 0 2006.201.08:57:17.35#ibcon#read 5, iclass 14, count 0 2006.201.08:57:17.35#ibcon#about to read 6, iclass 14, count 0 2006.201.08:57:17.35#ibcon#read 6, iclass 14, count 0 2006.201.08:57:17.35#ibcon#end of sib2, iclass 14, count 0 2006.201.08:57:17.35#ibcon#*after write, iclass 14, count 0 2006.201.08:57:17.35#ibcon#*before return 0, iclass 14, count 0 2006.201.08:57:17.35#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:17.35#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.08:57:17.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.08:57:17.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.08:57:17.35$vck44/vabw=wide 2006.201.08:57:17.35#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.08:57:17.35#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.08:57:17.35#ibcon#ireg 8 cls_cnt 0 2006.201.08:57:17.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:17.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:17.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:17.35#ibcon#enter wrdev, iclass 16, count 0 2006.201.08:57:17.35#ibcon#first serial, iclass 16, count 0 2006.201.08:57:17.35#ibcon#enter sib2, iclass 16, count 0 2006.201.08:57:17.35#ibcon#flushed, iclass 16, count 0 2006.201.08:57:17.35#ibcon#about to write, iclass 16, count 0 2006.201.08:57:17.35#ibcon#wrote, iclass 16, count 0 2006.201.08:57:17.35#ibcon#about to read 3, iclass 16, count 0 2006.201.08:57:17.37#ibcon#read 3, iclass 16, count 0 2006.201.08:57:17.37#ibcon#about to read 4, iclass 16, count 0 2006.201.08:57:17.37#ibcon#read 4, iclass 16, count 0 2006.201.08:57:17.37#ibcon#about to read 5, iclass 16, count 0 2006.201.08:57:17.37#ibcon#read 5, iclass 16, count 0 2006.201.08:57:17.37#ibcon#about to read 6, iclass 16, count 0 2006.201.08:57:17.37#ibcon#read 6, iclass 16, count 0 2006.201.08:57:17.37#ibcon#end of sib2, iclass 16, count 0 2006.201.08:57:17.37#ibcon#*mode == 0, iclass 16, count 0 2006.201.08:57:17.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.08:57:17.37#ibcon#[25=BW32\r\n] 2006.201.08:57:17.37#ibcon#*before write, iclass 16, count 0 2006.201.08:57:17.37#ibcon#enter sib2, iclass 16, count 0 2006.201.08:57:17.37#ibcon#flushed, iclass 16, count 0 2006.201.08:57:17.37#ibcon#about to write, iclass 16, count 0 2006.201.08:57:17.37#ibcon#wrote, iclass 16, count 0 2006.201.08:57:17.37#ibcon#about to read 3, iclass 16, count 0 2006.201.08:57:17.41#ibcon#read 3, iclass 16, count 0 2006.201.08:57:17.41#ibcon#about to read 4, iclass 16, count 0 2006.201.08:57:17.41#ibcon#read 4, iclass 16, count 0 2006.201.08:57:17.41#ibcon#about to read 5, iclass 16, count 0 2006.201.08:57:17.41#ibcon#read 5, iclass 16, count 0 2006.201.08:57:17.41#ibcon#about to read 6, iclass 16, count 0 2006.201.08:57:17.41#ibcon#read 6, iclass 16, count 0 2006.201.08:57:17.41#ibcon#end of sib2, iclass 16, count 0 2006.201.08:57:17.41#ibcon#*after write, iclass 16, count 0 2006.201.08:57:17.41#ibcon#*before return 0, iclass 16, count 0 2006.201.08:57:17.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:17.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.08:57:17.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.08:57:17.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.08:57:17.41$vck44/vbbw=wide 2006.201.08:57:17.41#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.08:57:17.41#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.08:57:17.41#ibcon#ireg 8 cls_cnt 0 2006.201.08:57:17.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:57:17.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:57:17.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:57:17.47#ibcon#enter wrdev, iclass 18, count 0 2006.201.08:57:17.47#ibcon#first serial, iclass 18, count 0 2006.201.08:57:17.47#ibcon#enter sib2, iclass 18, count 0 2006.201.08:57:17.47#ibcon#flushed, iclass 18, count 0 2006.201.08:57:17.47#ibcon#about to write, iclass 18, count 0 2006.201.08:57:17.47#ibcon#wrote, iclass 18, count 0 2006.201.08:57:17.47#ibcon#about to read 3, iclass 18, count 0 2006.201.08:57:17.49#ibcon#read 3, iclass 18, count 0 2006.201.08:57:17.49#ibcon#about to read 4, iclass 18, count 0 2006.201.08:57:17.49#ibcon#read 4, iclass 18, count 0 2006.201.08:57:17.49#ibcon#about to read 5, iclass 18, count 0 2006.201.08:57:17.49#ibcon#read 5, iclass 18, count 0 2006.201.08:57:17.49#ibcon#about to read 6, iclass 18, count 0 2006.201.08:57:17.49#ibcon#read 6, iclass 18, count 0 2006.201.08:57:17.49#ibcon#end of sib2, iclass 18, count 0 2006.201.08:57:17.49#ibcon#*mode == 0, iclass 18, count 0 2006.201.08:57:17.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.08:57:17.49#ibcon#[27=BW32\r\n] 2006.201.08:57:17.49#ibcon#*before write, iclass 18, count 0 2006.201.08:57:17.49#ibcon#enter sib2, iclass 18, count 0 2006.201.08:57:17.49#ibcon#flushed, iclass 18, count 0 2006.201.08:57:17.49#ibcon#about to write, iclass 18, count 0 2006.201.08:57:17.49#ibcon#wrote, iclass 18, count 0 2006.201.08:57:17.49#ibcon#about to read 3, iclass 18, count 0 2006.201.08:57:17.52#ibcon#read 3, iclass 18, count 0 2006.201.08:57:17.52#ibcon#about to read 4, iclass 18, count 0 2006.201.08:57:17.52#ibcon#read 4, iclass 18, count 0 2006.201.08:57:17.52#ibcon#about to read 5, iclass 18, count 0 2006.201.08:57:17.52#ibcon#read 5, iclass 18, count 0 2006.201.08:57:17.52#ibcon#about to read 6, iclass 18, count 0 2006.201.08:57:17.52#ibcon#read 6, iclass 18, count 0 2006.201.08:57:17.52#ibcon#end of sib2, iclass 18, count 0 2006.201.08:57:17.52#ibcon#*after write, iclass 18, count 0 2006.201.08:57:17.52#ibcon#*before return 0, iclass 18, count 0 2006.201.08:57:17.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:57:17.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.08:57:17.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.08:57:17.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.08:57:17.52$setupk4/ifdk4 2006.201.08:57:17.52$ifdk4/lo= 2006.201.08:57:17.52$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.08:57:17.52$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.08:57:17.52$ifdk4/patch= 2006.201.08:57:17.52$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.08:57:17.52$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.08:57:17.52$setupk4/!*+20s 2006.201.08:57:21.15#abcon#<5=/05 2.8 4.1 22.94 901003.7\r\n> 2006.201.08:57:21.17#abcon#{5=INTERFACE CLEAR} 2006.201.08:57:21.23#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:57:24.14#trakl#Source acquired 2006.201.08:57:25.14#flagr#flagr/antenna,acquired 2006.201.08:57:31.32#abcon#<5=/05 2.7 4.1 22.94 901003.7\r\n> 2006.201.08:57:31.34#abcon#{5=INTERFACE CLEAR} 2006.201.08:57:31.40#abcon#[5=S1D000X0/0*\r\n] 2006.201.08:57:31.98$setupk4/"tpicd 2006.201.08:57:31.98$setupk4/echo=off 2006.201.08:57:31.98$setupk4/xlog=off 2006.201.08:57:31.98:!2006.201.08:58:20 2006.201.08:58:20.00:preob 2006.201.08:58:20.14/onsource/TRACKING 2006.201.08:58:20.14:!2006.201.08:58:30 2006.201.08:58:30.00:"tape 2006.201.08:58:30.00:"st=record 2006.201.08:58:30.00:data_valid=on 2006.201.08:58:30.00:midob 2006.201.08:58:31.14/onsource/TRACKING 2006.201.08:58:31.14/wx/22.93,1003.8,90 2006.201.08:58:31.20/cable/+6.4658E-03 2006.201.08:58:32.29/va/01,08,usb,yes,29,31 2006.201.08:58:32.29/va/02,07,usb,yes,31,32 2006.201.08:58:32.29/va/03,08,usb,yes,28,29 2006.201.08:58:32.29/va/04,07,usb,yes,32,34 2006.201.08:58:32.29/va/05,04,usb,yes,28,29 2006.201.08:58:32.29/va/06,05,usb,yes,28,28 2006.201.08:58:32.29/va/07,05,usb,yes,27,29 2006.201.08:58:32.29/va/08,04,usb,yes,27,33 2006.201.08:58:32.52/valo/01,524.99,yes,locked 2006.201.08:58:32.52/valo/02,534.99,yes,locked 2006.201.08:58:32.52/valo/03,564.99,yes,locked 2006.201.08:58:32.52/valo/04,624.99,yes,locked 2006.201.08:58:32.52/valo/05,734.99,yes,locked 2006.201.08:58:32.52/valo/06,814.99,yes,locked 2006.201.08:58:32.52/valo/07,864.99,yes,locked 2006.201.08:58:32.52/valo/08,884.99,yes,locked 2006.201.08:58:33.61/vb/01,04,usb,yes,29,27 2006.201.08:58:33.61/vb/02,05,usb,yes,27,27 2006.201.08:58:33.61/vb/03,04,usb,yes,28,31 2006.201.08:58:33.61/vb/04,05,usb,yes,29,28 2006.201.08:58:33.61/vb/05,04,usb,yes,25,28 2006.201.08:58:33.61/vb/06,04,usb,yes,30,26 2006.201.08:58:33.61/vb/07,04,usb,yes,29,29 2006.201.08:58:33.61/vb/08,04,usb,yes,27,30 2006.201.08:58:33.84/vblo/01,629.99,yes,locked 2006.201.08:58:33.84/vblo/02,634.99,yes,locked 2006.201.08:58:33.84/vblo/03,649.99,yes,locked 2006.201.08:58:33.84/vblo/04,679.99,yes,locked 2006.201.08:58:33.84/vblo/05,709.99,yes,locked 2006.201.08:58:33.84/vblo/06,719.99,yes,locked 2006.201.08:58:33.84/vblo/07,734.99,yes,locked 2006.201.08:58:33.84/vblo/08,744.99,yes,locked 2006.201.08:58:33.99/vabw/8 2006.201.08:58:34.14/vbbw/8 2006.201.08:58:34.23/xfe/off,on,15.0 2006.201.08:58:34.61/ifatt/23,28,28,28 2006.201.08:58:35.05/fmout-gps/S +4.53E-07 2006.201.08:58:35.12:!2006.201.09:02:20 2006.201.09:02:20.00:data_valid=off 2006.201.09:02:20.00:"et 2006.201.09:02:20.00:!+3s 2006.201.09:02:23.02:"tape 2006.201.09:02:23.02:postob 2006.201.09:02:23.13/cable/+6.4658E-03 2006.201.09:02:23.13/wx/22.91,1003.8,90 2006.201.09:02:23.20/fmout-gps/S +4.51E-07 2006.201.09:02:23.20:scan_name=201-0912,jd0607,40 2006.201.09:02:23.20:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.201.09:02:24.14#flagr#flagr/antenna,new-source 2006.201.09:02:24.14:checkk5 2006.201.09:02:24.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:02:24.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:02:25.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:02:25.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:02:26.01/chk_obsdata//k5ts1/T2010858??a.dat file size is correct (nominal:920MB, actual:920MB). 2006.201.09:02:26.37/chk_obsdata//k5ts2/T2010858??b.dat file size is correct (nominal:920MB, actual:920MB). 2006.201.09:02:26.74/chk_obsdata//k5ts3/T2010858??c.dat file size is correct (nominal:920MB, actual:920MB). 2006.201.09:02:27.11/chk_obsdata//k5ts4/T2010858??d.dat file size is correct (nominal:920MB, actual:920MB). 2006.201.09:02:27.80/k5log//k5ts1_log_newline 2006.201.09:02:28.48/k5log//k5ts2_log_newline 2006.201.09:02:29.16/k5log//k5ts3_log_newline 2006.201.09:02:29.85/k5log//k5ts4_log_newline 2006.201.09:02:29.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:02:29.87:setupk4=1 2006.201.09:02:29.87$setupk4/echo=on 2006.201.09:02:29.87$setupk4/pcalon 2006.201.09:02:29.87$pcalon/"no phase cal control is implemented here 2006.201.09:02:29.87$setupk4/"tpicd=stop 2006.201.09:02:29.87$setupk4/"rec=synch_on 2006.201.09:02:29.87$setupk4/"rec_mode=128 2006.201.09:02:29.87$setupk4/!* 2006.201.09:02:29.87$setupk4/recpk4 2006.201.09:02:29.87$recpk4/recpatch= 2006.201.09:02:29.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:02:29.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:02:29.88$setupk4/vck44 2006.201.09:02:29.88$vck44/valo=1,524.99 2006.201.09:02:29.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.09:02:29.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.09:02:29.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:29.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:29.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:29.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:29.88#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:02:29.88#ibcon#first serial, iclass 39, count 0 2006.201.09:02:29.88#ibcon#enter sib2, iclass 39, count 0 2006.201.09:02:29.88#ibcon#flushed, iclass 39, count 0 2006.201.09:02:29.88#ibcon#about to write, iclass 39, count 0 2006.201.09:02:29.88#ibcon#wrote, iclass 39, count 0 2006.201.09:02:29.88#ibcon#about to read 3, iclass 39, count 0 2006.201.09:02:29.91#ibcon#read 3, iclass 39, count 0 2006.201.09:02:29.91#ibcon#about to read 4, iclass 39, count 0 2006.201.09:02:29.91#ibcon#read 4, iclass 39, count 0 2006.201.09:02:29.91#ibcon#about to read 5, iclass 39, count 0 2006.201.09:02:29.91#ibcon#read 5, iclass 39, count 0 2006.201.09:02:29.91#ibcon#about to read 6, iclass 39, count 0 2006.201.09:02:29.91#ibcon#read 6, iclass 39, count 0 2006.201.09:02:29.91#ibcon#end of sib2, iclass 39, count 0 2006.201.09:02:29.91#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:02:29.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:02:29.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:02:29.91#ibcon#*before write, iclass 39, count 0 2006.201.09:02:29.91#ibcon#enter sib2, iclass 39, count 0 2006.201.09:02:29.91#ibcon#flushed, iclass 39, count 0 2006.201.09:02:29.91#ibcon#about to write, iclass 39, count 0 2006.201.09:02:29.91#ibcon#wrote, iclass 39, count 0 2006.201.09:02:29.91#ibcon#about to read 3, iclass 39, count 0 2006.201.09:02:29.97#ibcon#read 3, iclass 39, count 0 2006.201.09:02:29.97#ibcon#about to read 4, iclass 39, count 0 2006.201.09:02:29.97#ibcon#read 4, iclass 39, count 0 2006.201.09:02:29.97#ibcon#about to read 5, iclass 39, count 0 2006.201.09:02:29.97#ibcon#read 5, iclass 39, count 0 2006.201.09:02:29.97#ibcon#about to read 6, iclass 39, count 0 2006.201.09:02:29.97#ibcon#read 6, iclass 39, count 0 2006.201.09:02:29.97#ibcon#end of sib2, iclass 39, count 0 2006.201.09:02:29.97#ibcon#*after write, iclass 39, count 0 2006.201.09:02:29.97#ibcon#*before return 0, iclass 39, count 0 2006.201.09:02:29.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:29.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:29.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:02:29.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:02:29.97$vck44/va=1,8 2006.201.09:02:29.97#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.09:02:29.97#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.09:02:29.97#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:29.97#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:29.97#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:29.97#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:29.97#ibcon#enter wrdev, iclass 2, count 2 2006.201.09:02:29.97#ibcon#first serial, iclass 2, count 2 2006.201.09:02:29.97#ibcon#enter sib2, iclass 2, count 2 2006.201.09:02:29.97#ibcon#flushed, iclass 2, count 2 2006.201.09:02:29.97#ibcon#about to write, iclass 2, count 2 2006.201.09:02:29.97#ibcon#wrote, iclass 2, count 2 2006.201.09:02:29.97#ibcon#about to read 3, iclass 2, count 2 2006.201.09:02:29.99#ibcon#read 3, iclass 2, count 2 2006.201.09:02:29.99#ibcon#about to read 4, iclass 2, count 2 2006.201.09:02:29.99#ibcon#read 4, iclass 2, count 2 2006.201.09:02:29.99#ibcon#about to read 5, iclass 2, count 2 2006.201.09:02:29.99#ibcon#read 5, iclass 2, count 2 2006.201.09:02:29.99#ibcon#about to read 6, iclass 2, count 2 2006.201.09:02:29.99#ibcon#read 6, iclass 2, count 2 2006.201.09:02:29.99#ibcon#end of sib2, iclass 2, count 2 2006.201.09:02:29.99#ibcon#*mode == 0, iclass 2, count 2 2006.201.09:02:29.99#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.09:02:29.99#ibcon#[25=AT01-08\r\n] 2006.201.09:02:29.99#ibcon#*before write, iclass 2, count 2 2006.201.09:02:29.99#ibcon#enter sib2, iclass 2, count 2 2006.201.09:02:29.99#ibcon#flushed, iclass 2, count 2 2006.201.09:02:29.99#ibcon#about to write, iclass 2, count 2 2006.201.09:02:29.99#ibcon#wrote, iclass 2, count 2 2006.201.09:02:29.99#ibcon#about to read 3, iclass 2, count 2 2006.201.09:02:30.03#ibcon#read 3, iclass 2, count 2 2006.201.09:02:30.03#ibcon#about to read 4, iclass 2, count 2 2006.201.09:02:30.03#ibcon#read 4, iclass 2, count 2 2006.201.09:02:30.03#ibcon#about to read 5, iclass 2, count 2 2006.201.09:02:30.03#ibcon#read 5, iclass 2, count 2 2006.201.09:02:30.03#ibcon#about to read 6, iclass 2, count 2 2006.201.09:02:30.03#ibcon#read 6, iclass 2, count 2 2006.201.09:02:30.03#ibcon#end of sib2, iclass 2, count 2 2006.201.09:02:30.03#ibcon#*after write, iclass 2, count 2 2006.201.09:02:30.03#ibcon#*before return 0, iclass 2, count 2 2006.201.09:02:30.03#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:30.03#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:30.03#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.09:02:30.03#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:30.03#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:30.15#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:30.15#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:30.15#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:02:30.15#ibcon#first serial, iclass 2, count 0 2006.201.09:02:30.15#ibcon#enter sib2, iclass 2, count 0 2006.201.09:02:30.15#ibcon#flushed, iclass 2, count 0 2006.201.09:02:30.15#ibcon#about to write, iclass 2, count 0 2006.201.09:02:30.15#ibcon#wrote, iclass 2, count 0 2006.201.09:02:30.15#ibcon#about to read 3, iclass 2, count 0 2006.201.09:02:30.17#ibcon#read 3, iclass 2, count 0 2006.201.09:02:30.17#ibcon#about to read 4, iclass 2, count 0 2006.201.09:02:30.17#ibcon#read 4, iclass 2, count 0 2006.201.09:02:30.17#ibcon#about to read 5, iclass 2, count 0 2006.201.09:02:30.17#ibcon#read 5, iclass 2, count 0 2006.201.09:02:30.17#ibcon#about to read 6, iclass 2, count 0 2006.201.09:02:30.17#ibcon#read 6, iclass 2, count 0 2006.201.09:02:30.17#ibcon#end of sib2, iclass 2, count 0 2006.201.09:02:30.17#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:02:30.17#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:02:30.17#ibcon#[25=USB\r\n] 2006.201.09:02:30.17#ibcon#*before write, iclass 2, count 0 2006.201.09:02:30.17#ibcon#enter sib2, iclass 2, count 0 2006.201.09:02:30.17#ibcon#flushed, iclass 2, count 0 2006.201.09:02:30.17#ibcon#about to write, iclass 2, count 0 2006.201.09:02:30.17#ibcon#wrote, iclass 2, count 0 2006.201.09:02:30.17#ibcon#about to read 3, iclass 2, count 0 2006.201.09:02:30.20#ibcon#read 3, iclass 2, count 0 2006.201.09:02:30.20#ibcon#about to read 4, iclass 2, count 0 2006.201.09:02:30.20#ibcon#read 4, iclass 2, count 0 2006.201.09:02:30.20#ibcon#about to read 5, iclass 2, count 0 2006.201.09:02:30.20#ibcon#read 5, iclass 2, count 0 2006.201.09:02:30.20#ibcon#about to read 6, iclass 2, count 0 2006.201.09:02:30.20#ibcon#read 6, iclass 2, count 0 2006.201.09:02:30.20#ibcon#end of sib2, iclass 2, count 0 2006.201.09:02:30.20#ibcon#*after write, iclass 2, count 0 2006.201.09:02:30.20#ibcon#*before return 0, iclass 2, count 0 2006.201.09:02:30.20#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:30.20#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:30.20#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:02:30.20#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:02:30.20$vck44/valo=2,534.99 2006.201.09:02:30.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.09:02:30.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.09:02:30.20#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:30.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:30.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:30.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:30.20#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:02:30.20#ibcon#first serial, iclass 5, count 0 2006.201.09:02:30.20#ibcon#enter sib2, iclass 5, count 0 2006.201.09:02:30.20#ibcon#flushed, iclass 5, count 0 2006.201.09:02:30.20#ibcon#about to write, iclass 5, count 0 2006.201.09:02:30.20#ibcon#wrote, iclass 5, count 0 2006.201.09:02:30.20#ibcon#about to read 3, iclass 5, count 0 2006.201.09:02:30.22#ibcon#read 3, iclass 5, count 0 2006.201.09:02:30.22#ibcon#about to read 4, iclass 5, count 0 2006.201.09:02:30.22#ibcon#read 4, iclass 5, count 0 2006.201.09:02:30.22#ibcon#about to read 5, iclass 5, count 0 2006.201.09:02:30.22#ibcon#read 5, iclass 5, count 0 2006.201.09:02:30.22#ibcon#about to read 6, iclass 5, count 0 2006.201.09:02:30.22#ibcon#read 6, iclass 5, count 0 2006.201.09:02:30.22#ibcon#end of sib2, iclass 5, count 0 2006.201.09:02:30.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:02:30.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:02:30.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:02:30.22#ibcon#*before write, iclass 5, count 0 2006.201.09:02:30.22#ibcon#enter sib2, iclass 5, count 0 2006.201.09:02:30.22#ibcon#flushed, iclass 5, count 0 2006.201.09:02:30.22#ibcon#about to write, iclass 5, count 0 2006.201.09:02:30.22#ibcon#wrote, iclass 5, count 0 2006.201.09:02:30.22#ibcon#about to read 3, iclass 5, count 0 2006.201.09:02:30.26#ibcon#read 3, iclass 5, count 0 2006.201.09:02:30.26#ibcon#about to read 4, iclass 5, count 0 2006.201.09:02:30.26#ibcon#read 4, iclass 5, count 0 2006.201.09:02:30.26#ibcon#about to read 5, iclass 5, count 0 2006.201.09:02:30.26#ibcon#read 5, iclass 5, count 0 2006.201.09:02:30.26#ibcon#about to read 6, iclass 5, count 0 2006.201.09:02:30.26#ibcon#read 6, iclass 5, count 0 2006.201.09:02:30.26#ibcon#end of sib2, iclass 5, count 0 2006.201.09:02:30.26#ibcon#*after write, iclass 5, count 0 2006.201.09:02:30.26#ibcon#*before return 0, iclass 5, count 0 2006.201.09:02:30.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:30.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:30.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:02:30.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:02:30.26$vck44/va=2,7 2006.201.09:02:30.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.09:02:30.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.09:02:30.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:30.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:30.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:30.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:30.32#ibcon#enter wrdev, iclass 7, count 2 2006.201.09:02:30.32#ibcon#first serial, iclass 7, count 2 2006.201.09:02:30.32#ibcon#enter sib2, iclass 7, count 2 2006.201.09:02:30.32#ibcon#flushed, iclass 7, count 2 2006.201.09:02:30.32#ibcon#about to write, iclass 7, count 2 2006.201.09:02:30.32#ibcon#wrote, iclass 7, count 2 2006.201.09:02:30.32#ibcon#about to read 3, iclass 7, count 2 2006.201.09:02:30.34#ibcon#read 3, iclass 7, count 2 2006.201.09:02:30.34#ibcon#about to read 4, iclass 7, count 2 2006.201.09:02:30.34#ibcon#read 4, iclass 7, count 2 2006.201.09:02:30.34#ibcon#about to read 5, iclass 7, count 2 2006.201.09:02:30.34#ibcon#read 5, iclass 7, count 2 2006.201.09:02:30.34#ibcon#about to read 6, iclass 7, count 2 2006.201.09:02:30.34#ibcon#read 6, iclass 7, count 2 2006.201.09:02:30.34#ibcon#end of sib2, iclass 7, count 2 2006.201.09:02:30.34#ibcon#*mode == 0, iclass 7, count 2 2006.201.09:02:30.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.09:02:30.34#ibcon#[25=AT02-07\r\n] 2006.201.09:02:30.34#ibcon#*before write, iclass 7, count 2 2006.201.09:02:30.34#ibcon#enter sib2, iclass 7, count 2 2006.201.09:02:30.34#ibcon#flushed, iclass 7, count 2 2006.201.09:02:30.34#ibcon#about to write, iclass 7, count 2 2006.201.09:02:30.34#ibcon#wrote, iclass 7, count 2 2006.201.09:02:30.34#ibcon#about to read 3, iclass 7, count 2 2006.201.09:02:30.37#ibcon#read 3, iclass 7, count 2 2006.201.09:02:30.37#ibcon#about to read 4, iclass 7, count 2 2006.201.09:02:30.37#ibcon#read 4, iclass 7, count 2 2006.201.09:02:30.37#ibcon#about to read 5, iclass 7, count 2 2006.201.09:02:30.37#ibcon#read 5, iclass 7, count 2 2006.201.09:02:30.37#ibcon#about to read 6, iclass 7, count 2 2006.201.09:02:30.37#ibcon#read 6, iclass 7, count 2 2006.201.09:02:30.37#ibcon#end of sib2, iclass 7, count 2 2006.201.09:02:30.37#ibcon#*after write, iclass 7, count 2 2006.201.09:02:30.37#ibcon#*before return 0, iclass 7, count 2 2006.201.09:02:30.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:30.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:30.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.09:02:30.37#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:30.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:30.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:30.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:30.49#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:02:30.49#ibcon#first serial, iclass 7, count 0 2006.201.09:02:30.49#ibcon#enter sib2, iclass 7, count 0 2006.201.09:02:30.49#ibcon#flushed, iclass 7, count 0 2006.201.09:02:30.49#ibcon#about to write, iclass 7, count 0 2006.201.09:02:30.49#ibcon#wrote, iclass 7, count 0 2006.201.09:02:30.49#ibcon#about to read 3, iclass 7, count 0 2006.201.09:02:30.51#ibcon#read 3, iclass 7, count 0 2006.201.09:02:30.51#ibcon#about to read 4, iclass 7, count 0 2006.201.09:02:30.51#ibcon#read 4, iclass 7, count 0 2006.201.09:02:30.51#ibcon#about to read 5, iclass 7, count 0 2006.201.09:02:30.51#ibcon#read 5, iclass 7, count 0 2006.201.09:02:30.51#ibcon#about to read 6, iclass 7, count 0 2006.201.09:02:30.51#ibcon#read 6, iclass 7, count 0 2006.201.09:02:30.51#ibcon#end of sib2, iclass 7, count 0 2006.201.09:02:30.51#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:02:30.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:02:30.51#ibcon#[25=USB\r\n] 2006.201.09:02:30.51#ibcon#*before write, iclass 7, count 0 2006.201.09:02:30.51#ibcon#enter sib2, iclass 7, count 0 2006.201.09:02:30.51#ibcon#flushed, iclass 7, count 0 2006.201.09:02:30.51#ibcon#about to write, iclass 7, count 0 2006.201.09:02:30.51#ibcon#wrote, iclass 7, count 0 2006.201.09:02:30.51#ibcon#about to read 3, iclass 7, count 0 2006.201.09:02:30.54#ibcon#read 3, iclass 7, count 0 2006.201.09:02:30.54#ibcon#about to read 4, iclass 7, count 0 2006.201.09:02:30.54#ibcon#read 4, iclass 7, count 0 2006.201.09:02:30.54#ibcon#about to read 5, iclass 7, count 0 2006.201.09:02:30.54#ibcon#read 5, iclass 7, count 0 2006.201.09:02:30.54#ibcon#about to read 6, iclass 7, count 0 2006.201.09:02:30.54#ibcon#read 6, iclass 7, count 0 2006.201.09:02:30.54#ibcon#end of sib2, iclass 7, count 0 2006.201.09:02:30.54#ibcon#*after write, iclass 7, count 0 2006.201.09:02:30.54#ibcon#*before return 0, iclass 7, count 0 2006.201.09:02:30.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:30.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:30.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:02:30.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:02:30.54$vck44/valo=3,564.99 2006.201.09:02:30.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.09:02:30.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.09:02:30.54#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:30.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:30.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:30.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:30.54#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:02:30.54#ibcon#first serial, iclass 11, count 0 2006.201.09:02:30.54#ibcon#enter sib2, iclass 11, count 0 2006.201.09:02:30.54#ibcon#flushed, iclass 11, count 0 2006.201.09:02:30.54#ibcon#about to write, iclass 11, count 0 2006.201.09:02:30.54#ibcon#wrote, iclass 11, count 0 2006.201.09:02:30.54#ibcon#about to read 3, iclass 11, count 0 2006.201.09:02:30.56#ibcon#read 3, iclass 11, count 0 2006.201.09:02:30.56#ibcon#about to read 4, iclass 11, count 0 2006.201.09:02:30.56#ibcon#read 4, iclass 11, count 0 2006.201.09:02:30.56#ibcon#about to read 5, iclass 11, count 0 2006.201.09:02:30.56#ibcon#read 5, iclass 11, count 0 2006.201.09:02:30.56#ibcon#about to read 6, iclass 11, count 0 2006.201.09:02:30.56#ibcon#read 6, iclass 11, count 0 2006.201.09:02:30.56#ibcon#end of sib2, iclass 11, count 0 2006.201.09:02:30.56#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:02:30.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:02:30.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:02:30.56#ibcon#*before write, iclass 11, count 0 2006.201.09:02:30.56#ibcon#enter sib2, iclass 11, count 0 2006.201.09:02:30.56#ibcon#flushed, iclass 11, count 0 2006.201.09:02:30.56#ibcon#about to write, iclass 11, count 0 2006.201.09:02:30.56#ibcon#wrote, iclass 11, count 0 2006.201.09:02:30.56#ibcon#about to read 3, iclass 11, count 0 2006.201.09:02:30.61#ibcon#read 3, iclass 11, count 0 2006.201.09:02:30.61#ibcon#about to read 4, iclass 11, count 0 2006.201.09:02:30.61#ibcon#read 4, iclass 11, count 0 2006.201.09:02:30.61#ibcon#about to read 5, iclass 11, count 0 2006.201.09:02:30.61#ibcon#read 5, iclass 11, count 0 2006.201.09:02:30.61#ibcon#about to read 6, iclass 11, count 0 2006.201.09:02:30.61#ibcon#read 6, iclass 11, count 0 2006.201.09:02:30.61#ibcon#end of sib2, iclass 11, count 0 2006.201.09:02:30.61#ibcon#*after write, iclass 11, count 0 2006.201.09:02:30.61#ibcon#*before return 0, iclass 11, count 0 2006.201.09:02:30.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:30.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:30.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:02:30.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:02:30.61$vck44/va=3,8 2006.201.09:02:30.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.09:02:30.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.09:02:30.61#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:30.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:30.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:30.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:30.66#ibcon#enter wrdev, iclass 13, count 2 2006.201.09:02:30.66#ibcon#first serial, iclass 13, count 2 2006.201.09:02:30.66#ibcon#enter sib2, iclass 13, count 2 2006.201.09:02:30.66#ibcon#flushed, iclass 13, count 2 2006.201.09:02:30.66#ibcon#about to write, iclass 13, count 2 2006.201.09:02:30.66#ibcon#wrote, iclass 13, count 2 2006.201.09:02:30.66#ibcon#about to read 3, iclass 13, count 2 2006.201.09:02:30.68#ibcon#read 3, iclass 13, count 2 2006.201.09:02:30.68#ibcon#about to read 4, iclass 13, count 2 2006.201.09:02:30.68#ibcon#read 4, iclass 13, count 2 2006.201.09:02:30.68#ibcon#about to read 5, iclass 13, count 2 2006.201.09:02:30.68#ibcon#read 5, iclass 13, count 2 2006.201.09:02:30.68#ibcon#about to read 6, iclass 13, count 2 2006.201.09:02:30.68#ibcon#read 6, iclass 13, count 2 2006.201.09:02:30.68#ibcon#end of sib2, iclass 13, count 2 2006.201.09:02:30.68#ibcon#*mode == 0, iclass 13, count 2 2006.201.09:02:30.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.09:02:30.68#ibcon#[25=AT03-08\r\n] 2006.201.09:02:30.68#ibcon#*before write, iclass 13, count 2 2006.201.09:02:30.68#ibcon#enter sib2, iclass 13, count 2 2006.201.09:02:30.68#ibcon#flushed, iclass 13, count 2 2006.201.09:02:30.68#ibcon#about to write, iclass 13, count 2 2006.201.09:02:30.68#ibcon#wrote, iclass 13, count 2 2006.201.09:02:30.68#ibcon#about to read 3, iclass 13, count 2 2006.201.09:02:30.71#ibcon#read 3, iclass 13, count 2 2006.201.09:02:30.71#ibcon#about to read 4, iclass 13, count 2 2006.201.09:02:30.71#ibcon#read 4, iclass 13, count 2 2006.201.09:02:30.71#ibcon#about to read 5, iclass 13, count 2 2006.201.09:02:30.71#ibcon#read 5, iclass 13, count 2 2006.201.09:02:30.71#ibcon#about to read 6, iclass 13, count 2 2006.201.09:02:30.71#ibcon#read 6, iclass 13, count 2 2006.201.09:02:30.71#ibcon#end of sib2, iclass 13, count 2 2006.201.09:02:30.71#ibcon#*after write, iclass 13, count 2 2006.201.09:02:30.71#ibcon#*before return 0, iclass 13, count 2 2006.201.09:02:30.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:30.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:30.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.09:02:30.71#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:30.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:30.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:30.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:30.83#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:02:30.83#ibcon#first serial, iclass 13, count 0 2006.201.09:02:30.83#ibcon#enter sib2, iclass 13, count 0 2006.201.09:02:30.83#ibcon#flushed, iclass 13, count 0 2006.201.09:02:30.83#ibcon#about to write, iclass 13, count 0 2006.201.09:02:30.83#ibcon#wrote, iclass 13, count 0 2006.201.09:02:30.83#ibcon#about to read 3, iclass 13, count 0 2006.201.09:02:30.85#ibcon#read 3, iclass 13, count 0 2006.201.09:02:30.85#ibcon#about to read 4, iclass 13, count 0 2006.201.09:02:30.85#ibcon#read 4, iclass 13, count 0 2006.201.09:02:30.85#ibcon#about to read 5, iclass 13, count 0 2006.201.09:02:30.85#ibcon#read 5, iclass 13, count 0 2006.201.09:02:30.85#ibcon#about to read 6, iclass 13, count 0 2006.201.09:02:30.85#ibcon#read 6, iclass 13, count 0 2006.201.09:02:30.85#ibcon#end of sib2, iclass 13, count 0 2006.201.09:02:30.85#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:02:30.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:02:30.85#ibcon#[25=USB\r\n] 2006.201.09:02:30.85#ibcon#*before write, iclass 13, count 0 2006.201.09:02:30.85#ibcon#enter sib2, iclass 13, count 0 2006.201.09:02:30.85#ibcon#flushed, iclass 13, count 0 2006.201.09:02:30.85#ibcon#about to write, iclass 13, count 0 2006.201.09:02:30.85#ibcon#wrote, iclass 13, count 0 2006.201.09:02:30.85#ibcon#about to read 3, iclass 13, count 0 2006.201.09:02:30.88#ibcon#read 3, iclass 13, count 0 2006.201.09:02:30.88#ibcon#about to read 4, iclass 13, count 0 2006.201.09:02:30.88#ibcon#read 4, iclass 13, count 0 2006.201.09:02:30.88#ibcon#about to read 5, iclass 13, count 0 2006.201.09:02:30.88#ibcon#read 5, iclass 13, count 0 2006.201.09:02:30.88#ibcon#about to read 6, iclass 13, count 0 2006.201.09:02:30.88#ibcon#read 6, iclass 13, count 0 2006.201.09:02:30.88#ibcon#end of sib2, iclass 13, count 0 2006.201.09:02:30.88#ibcon#*after write, iclass 13, count 0 2006.201.09:02:30.88#ibcon#*before return 0, iclass 13, count 0 2006.201.09:02:30.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:30.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:30.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:02:30.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:02:30.88$vck44/valo=4,624.99 2006.201.09:02:30.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.09:02:30.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.09:02:30.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:30.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:30.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:30.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:30.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:02:30.88#ibcon#first serial, iclass 15, count 0 2006.201.09:02:30.88#ibcon#enter sib2, iclass 15, count 0 2006.201.09:02:30.88#ibcon#flushed, iclass 15, count 0 2006.201.09:02:30.88#ibcon#about to write, iclass 15, count 0 2006.201.09:02:30.88#ibcon#wrote, iclass 15, count 0 2006.201.09:02:30.88#ibcon#about to read 3, iclass 15, count 0 2006.201.09:02:30.90#ibcon#read 3, iclass 15, count 0 2006.201.09:02:30.90#ibcon#about to read 4, iclass 15, count 0 2006.201.09:02:30.90#ibcon#read 4, iclass 15, count 0 2006.201.09:02:30.90#ibcon#about to read 5, iclass 15, count 0 2006.201.09:02:30.90#ibcon#read 5, iclass 15, count 0 2006.201.09:02:30.90#ibcon#about to read 6, iclass 15, count 0 2006.201.09:02:30.90#ibcon#read 6, iclass 15, count 0 2006.201.09:02:30.90#ibcon#end of sib2, iclass 15, count 0 2006.201.09:02:30.90#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:02:30.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:02:30.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:02:30.90#ibcon#*before write, iclass 15, count 0 2006.201.09:02:30.90#ibcon#enter sib2, iclass 15, count 0 2006.201.09:02:30.90#ibcon#flushed, iclass 15, count 0 2006.201.09:02:30.90#ibcon#about to write, iclass 15, count 0 2006.201.09:02:30.90#ibcon#wrote, iclass 15, count 0 2006.201.09:02:30.90#ibcon#about to read 3, iclass 15, count 0 2006.201.09:02:30.94#ibcon#read 3, iclass 15, count 0 2006.201.09:02:30.94#ibcon#about to read 4, iclass 15, count 0 2006.201.09:02:30.94#ibcon#read 4, iclass 15, count 0 2006.201.09:02:30.94#ibcon#about to read 5, iclass 15, count 0 2006.201.09:02:30.94#ibcon#read 5, iclass 15, count 0 2006.201.09:02:30.94#ibcon#about to read 6, iclass 15, count 0 2006.201.09:02:30.94#ibcon#read 6, iclass 15, count 0 2006.201.09:02:30.94#ibcon#end of sib2, iclass 15, count 0 2006.201.09:02:30.94#ibcon#*after write, iclass 15, count 0 2006.201.09:02:30.94#ibcon#*before return 0, iclass 15, count 0 2006.201.09:02:30.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:30.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:30.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:02:30.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:02:30.94$vck44/va=4,7 2006.201.09:02:30.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.09:02:30.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.09:02:30.94#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:30.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:31.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:31.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:31.00#ibcon#enter wrdev, iclass 17, count 2 2006.201.09:02:31.00#ibcon#first serial, iclass 17, count 2 2006.201.09:02:31.00#ibcon#enter sib2, iclass 17, count 2 2006.201.09:02:31.00#ibcon#flushed, iclass 17, count 2 2006.201.09:02:31.00#ibcon#about to write, iclass 17, count 2 2006.201.09:02:31.00#ibcon#wrote, iclass 17, count 2 2006.201.09:02:31.00#ibcon#about to read 3, iclass 17, count 2 2006.201.09:02:31.02#ibcon#read 3, iclass 17, count 2 2006.201.09:02:31.02#ibcon#about to read 4, iclass 17, count 2 2006.201.09:02:31.02#ibcon#read 4, iclass 17, count 2 2006.201.09:02:31.02#ibcon#about to read 5, iclass 17, count 2 2006.201.09:02:31.02#ibcon#read 5, iclass 17, count 2 2006.201.09:02:31.02#ibcon#about to read 6, iclass 17, count 2 2006.201.09:02:31.02#ibcon#read 6, iclass 17, count 2 2006.201.09:02:31.02#ibcon#end of sib2, iclass 17, count 2 2006.201.09:02:31.02#ibcon#*mode == 0, iclass 17, count 2 2006.201.09:02:31.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.09:02:31.02#ibcon#[25=AT04-07\r\n] 2006.201.09:02:31.02#ibcon#*before write, iclass 17, count 2 2006.201.09:02:31.02#ibcon#enter sib2, iclass 17, count 2 2006.201.09:02:31.02#ibcon#flushed, iclass 17, count 2 2006.201.09:02:31.02#ibcon#about to write, iclass 17, count 2 2006.201.09:02:31.02#ibcon#wrote, iclass 17, count 2 2006.201.09:02:31.02#ibcon#about to read 3, iclass 17, count 2 2006.201.09:02:31.05#ibcon#read 3, iclass 17, count 2 2006.201.09:02:31.05#ibcon#about to read 4, iclass 17, count 2 2006.201.09:02:31.05#ibcon#read 4, iclass 17, count 2 2006.201.09:02:31.05#ibcon#about to read 5, iclass 17, count 2 2006.201.09:02:31.05#ibcon#read 5, iclass 17, count 2 2006.201.09:02:31.05#ibcon#about to read 6, iclass 17, count 2 2006.201.09:02:31.05#ibcon#read 6, iclass 17, count 2 2006.201.09:02:31.05#ibcon#end of sib2, iclass 17, count 2 2006.201.09:02:31.05#ibcon#*after write, iclass 17, count 2 2006.201.09:02:31.05#ibcon#*before return 0, iclass 17, count 2 2006.201.09:02:31.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:31.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:31.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.09:02:31.05#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:31.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:31.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:31.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:31.17#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:02:31.17#ibcon#first serial, iclass 17, count 0 2006.201.09:02:31.17#ibcon#enter sib2, iclass 17, count 0 2006.201.09:02:31.17#ibcon#flushed, iclass 17, count 0 2006.201.09:02:31.17#ibcon#about to write, iclass 17, count 0 2006.201.09:02:31.17#ibcon#wrote, iclass 17, count 0 2006.201.09:02:31.17#ibcon#about to read 3, iclass 17, count 0 2006.201.09:02:31.19#ibcon#read 3, iclass 17, count 0 2006.201.09:02:31.19#ibcon#about to read 4, iclass 17, count 0 2006.201.09:02:31.19#ibcon#read 4, iclass 17, count 0 2006.201.09:02:31.19#ibcon#about to read 5, iclass 17, count 0 2006.201.09:02:31.19#ibcon#read 5, iclass 17, count 0 2006.201.09:02:31.19#ibcon#about to read 6, iclass 17, count 0 2006.201.09:02:31.19#ibcon#read 6, iclass 17, count 0 2006.201.09:02:31.19#ibcon#end of sib2, iclass 17, count 0 2006.201.09:02:31.19#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:02:31.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:02:31.19#ibcon#[25=USB\r\n] 2006.201.09:02:31.19#ibcon#*before write, iclass 17, count 0 2006.201.09:02:31.19#ibcon#enter sib2, iclass 17, count 0 2006.201.09:02:31.19#ibcon#flushed, iclass 17, count 0 2006.201.09:02:31.19#ibcon#about to write, iclass 17, count 0 2006.201.09:02:31.19#ibcon#wrote, iclass 17, count 0 2006.201.09:02:31.19#ibcon#about to read 3, iclass 17, count 0 2006.201.09:02:31.22#ibcon#read 3, iclass 17, count 0 2006.201.09:02:31.22#ibcon#about to read 4, iclass 17, count 0 2006.201.09:02:31.22#ibcon#read 4, iclass 17, count 0 2006.201.09:02:31.22#ibcon#about to read 5, iclass 17, count 0 2006.201.09:02:31.22#ibcon#read 5, iclass 17, count 0 2006.201.09:02:31.22#ibcon#about to read 6, iclass 17, count 0 2006.201.09:02:31.22#ibcon#read 6, iclass 17, count 0 2006.201.09:02:31.22#ibcon#end of sib2, iclass 17, count 0 2006.201.09:02:31.22#ibcon#*after write, iclass 17, count 0 2006.201.09:02:31.22#ibcon#*before return 0, iclass 17, count 0 2006.201.09:02:31.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:31.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:31.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:02:31.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:02:31.22$vck44/valo=5,734.99 2006.201.09:02:31.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.09:02:31.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.09:02:31.22#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:31.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:31.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:31.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:31.22#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:02:31.22#ibcon#first serial, iclass 19, count 0 2006.201.09:02:31.22#ibcon#enter sib2, iclass 19, count 0 2006.201.09:02:31.22#ibcon#flushed, iclass 19, count 0 2006.201.09:02:31.22#ibcon#about to write, iclass 19, count 0 2006.201.09:02:31.22#ibcon#wrote, iclass 19, count 0 2006.201.09:02:31.22#ibcon#about to read 3, iclass 19, count 0 2006.201.09:02:31.24#ibcon#read 3, iclass 19, count 0 2006.201.09:02:31.24#ibcon#about to read 4, iclass 19, count 0 2006.201.09:02:31.24#ibcon#read 4, iclass 19, count 0 2006.201.09:02:31.24#ibcon#about to read 5, iclass 19, count 0 2006.201.09:02:31.24#ibcon#read 5, iclass 19, count 0 2006.201.09:02:31.24#ibcon#about to read 6, iclass 19, count 0 2006.201.09:02:31.24#ibcon#read 6, iclass 19, count 0 2006.201.09:02:31.24#ibcon#end of sib2, iclass 19, count 0 2006.201.09:02:31.24#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:02:31.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:02:31.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:02:31.24#ibcon#*before write, iclass 19, count 0 2006.201.09:02:31.24#ibcon#enter sib2, iclass 19, count 0 2006.201.09:02:31.24#ibcon#flushed, iclass 19, count 0 2006.201.09:02:31.24#ibcon#about to write, iclass 19, count 0 2006.201.09:02:31.24#ibcon#wrote, iclass 19, count 0 2006.201.09:02:31.24#ibcon#about to read 3, iclass 19, count 0 2006.201.09:02:31.28#ibcon#read 3, iclass 19, count 0 2006.201.09:02:31.28#ibcon#about to read 4, iclass 19, count 0 2006.201.09:02:31.28#ibcon#read 4, iclass 19, count 0 2006.201.09:02:31.28#ibcon#about to read 5, iclass 19, count 0 2006.201.09:02:31.28#ibcon#read 5, iclass 19, count 0 2006.201.09:02:31.28#ibcon#about to read 6, iclass 19, count 0 2006.201.09:02:31.28#ibcon#read 6, iclass 19, count 0 2006.201.09:02:31.28#ibcon#end of sib2, iclass 19, count 0 2006.201.09:02:31.28#ibcon#*after write, iclass 19, count 0 2006.201.09:02:31.28#ibcon#*before return 0, iclass 19, count 0 2006.201.09:02:31.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:31.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:31.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:02:31.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:02:31.28$vck44/va=5,4 2006.201.09:02:31.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.09:02:31.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.09:02:31.28#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:31.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:31.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:31.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:31.34#ibcon#enter wrdev, iclass 21, count 2 2006.201.09:02:31.34#ibcon#first serial, iclass 21, count 2 2006.201.09:02:31.34#ibcon#enter sib2, iclass 21, count 2 2006.201.09:02:31.34#ibcon#flushed, iclass 21, count 2 2006.201.09:02:31.34#ibcon#about to write, iclass 21, count 2 2006.201.09:02:31.34#ibcon#wrote, iclass 21, count 2 2006.201.09:02:31.34#ibcon#about to read 3, iclass 21, count 2 2006.201.09:02:31.36#ibcon#read 3, iclass 21, count 2 2006.201.09:02:31.36#ibcon#about to read 4, iclass 21, count 2 2006.201.09:02:31.36#ibcon#read 4, iclass 21, count 2 2006.201.09:02:31.36#ibcon#about to read 5, iclass 21, count 2 2006.201.09:02:31.36#ibcon#read 5, iclass 21, count 2 2006.201.09:02:31.36#ibcon#about to read 6, iclass 21, count 2 2006.201.09:02:31.36#ibcon#read 6, iclass 21, count 2 2006.201.09:02:31.36#ibcon#end of sib2, iclass 21, count 2 2006.201.09:02:31.36#ibcon#*mode == 0, iclass 21, count 2 2006.201.09:02:31.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.09:02:31.36#ibcon#[25=AT05-04\r\n] 2006.201.09:02:31.36#ibcon#*before write, iclass 21, count 2 2006.201.09:02:31.36#ibcon#enter sib2, iclass 21, count 2 2006.201.09:02:31.36#ibcon#flushed, iclass 21, count 2 2006.201.09:02:31.36#ibcon#about to write, iclass 21, count 2 2006.201.09:02:31.36#ibcon#wrote, iclass 21, count 2 2006.201.09:02:31.36#ibcon#about to read 3, iclass 21, count 2 2006.201.09:02:31.39#ibcon#read 3, iclass 21, count 2 2006.201.09:02:31.39#ibcon#about to read 4, iclass 21, count 2 2006.201.09:02:31.39#ibcon#read 4, iclass 21, count 2 2006.201.09:02:31.39#ibcon#about to read 5, iclass 21, count 2 2006.201.09:02:31.39#ibcon#read 5, iclass 21, count 2 2006.201.09:02:31.39#ibcon#about to read 6, iclass 21, count 2 2006.201.09:02:31.39#ibcon#read 6, iclass 21, count 2 2006.201.09:02:31.39#ibcon#end of sib2, iclass 21, count 2 2006.201.09:02:31.39#ibcon#*after write, iclass 21, count 2 2006.201.09:02:31.39#ibcon#*before return 0, iclass 21, count 2 2006.201.09:02:31.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:31.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:31.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.09:02:31.39#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:31.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:31.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:31.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:31.51#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:02:31.51#ibcon#first serial, iclass 21, count 0 2006.201.09:02:31.51#ibcon#enter sib2, iclass 21, count 0 2006.201.09:02:31.51#ibcon#flushed, iclass 21, count 0 2006.201.09:02:31.51#ibcon#about to write, iclass 21, count 0 2006.201.09:02:31.51#ibcon#wrote, iclass 21, count 0 2006.201.09:02:31.51#ibcon#about to read 3, iclass 21, count 0 2006.201.09:02:31.53#ibcon#read 3, iclass 21, count 0 2006.201.09:02:31.53#ibcon#about to read 4, iclass 21, count 0 2006.201.09:02:31.53#ibcon#read 4, iclass 21, count 0 2006.201.09:02:31.53#ibcon#about to read 5, iclass 21, count 0 2006.201.09:02:31.53#ibcon#read 5, iclass 21, count 0 2006.201.09:02:31.53#ibcon#about to read 6, iclass 21, count 0 2006.201.09:02:31.53#ibcon#read 6, iclass 21, count 0 2006.201.09:02:31.53#ibcon#end of sib2, iclass 21, count 0 2006.201.09:02:31.53#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:02:31.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:02:31.53#ibcon#[25=USB\r\n] 2006.201.09:02:31.53#ibcon#*before write, iclass 21, count 0 2006.201.09:02:31.53#ibcon#enter sib2, iclass 21, count 0 2006.201.09:02:31.53#ibcon#flushed, iclass 21, count 0 2006.201.09:02:31.53#ibcon#about to write, iclass 21, count 0 2006.201.09:02:31.53#ibcon#wrote, iclass 21, count 0 2006.201.09:02:31.53#ibcon#about to read 3, iclass 21, count 0 2006.201.09:02:31.56#ibcon#read 3, iclass 21, count 0 2006.201.09:02:31.56#ibcon#about to read 4, iclass 21, count 0 2006.201.09:02:31.56#ibcon#read 4, iclass 21, count 0 2006.201.09:02:31.56#ibcon#about to read 5, iclass 21, count 0 2006.201.09:02:31.56#ibcon#read 5, iclass 21, count 0 2006.201.09:02:31.56#ibcon#about to read 6, iclass 21, count 0 2006.201.09:02:31.56#ibcon#read 6, iclass 21, count 0 2006.201.09:02:31.56#ibcon#end of sib2, iclass 21, count 0 2006.201.09:02:31.56#ibcon#*after write, iclass 21, count 0 2006.201.09:02:31.56#ibcon#*before return 0, iclass 21, count 0 2006.201.09:02:31.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:31.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:31.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:02:31.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:02:31.56$vck44/valo=6,814.99 2006.201.09:02:31.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.09:02:31.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.09:02:31.56#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:31.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:31.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:31.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:31.56#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:02:31.56#ibcon#first serial, iclass 23, count 0 2006.201.09:02:31.56#ibcon#enter sib2, iclass 23, count 0 2006.201.09:02:31.56#ibcon#flushed, iclass 23, count 0 2006.201.09:02:31.56#ibcon#about to write, iclass 23, count 0 2006.201.09:02:31.56#ibcon#wrote, iclass 23, count 0 2006.201.09:02:31.56#ibcon#about to read 3, iclass 23, count 0 2006.201.09:02:31.58#ibcon#read 3, iclass 23, count 0 2006.201.09:02:31.58#ibcon#about to read 4, iclass 23, count 0 2006.201.09:02:31.58#ibcon#read 4, iclass 23, count 0 2006.201.09:02:31.58#ibcon#about to read 5, iclass 23, count 0 2006.201.09:02:31.58#ibcon#read 5, iclass 23, count 0 2006.201.09:02:31.58#ibcon#about to read 6, iclass 23, count 0 2006.201.09:02:31.58#ibcon#read 6, iclass 23, count 0 2006.201.09:02:31.58#ibcon#end of sib2, iclass 23, count 0 2006.201.09:02:31.58#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:02:31.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:02:31.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:02:31.58#ibcon#*before write, iclass 23, count 0 2006.201.09:02:31.58#ibcon#enter sib2, iclass 23, count 0 2006.201.09:02:31.58#ibcon#flushed, iclass 23, count 0 2006.201.09:02:31.58#ibcon#about to write, iclass 23, count 0 2006.201.09:02:31.58#ibcon#wrote, iclass 23, count 0 2006.201.09:02:31.58#ibcon#about to read 3, iclass 23, count 0 2006.201.09:02:31.62#ibcon#read 3, iclass 23, count 0 2006.201.09:02:31.62#ibcon#about to read 4, iclass 23, count 0 2006.201.09:02:31.62#ibcon#read 4, iclass 23, count 0 2006.201.09:02:31.62#ibcon#about to read 5, iclass 23, count 0 2006.201.09:02:31.62#ibcon#read 5, iclass 23, count 0 2006.201.09:02:31.62#ibcon#about to read 6, iclass 23, count 0 2006.201.09:02:31.62#ibcon#read 6, iclass 23, count 0 2006.201.09:02:31.62#ibcon#end of sib2, iclass 23, count 0 2006.201.09:02:31.62#ibcon#*after write, iclass 23, count 0 2006.201.09:02:31.62#ibcon#*before return 0, iclass 23, count 0 2006.201.09:02:31.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:31.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:31.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:02:31.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:02:31.62$vck44/va=6,5 2006.201.09:02:31.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.09:02:31.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.09:02:31.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:31.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:31.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:31.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:31.68#ibcon#enter wrdev, iclass 25, count 2 2006.201.09:02:31.68#ibcon#first serial, iclass 25, count 2 2006.201.09:02:31.68#ibcon#enter sib2, iclass 25, count 2 2006.201.09:02:31.68#ibcon#flushed, iclass 25, count 2 2006.201.09:02:31.68#ibcon#about to write, iclass 25, count 2 2006.201.09:02:31.68#ibcon#wrote, iclass 25, count 2 2006.201.09:02:31.68#ibcon#about to read 3, iclass 25, count 2 2006.201.09:02:31.70#ibcon#read 3, iclass 25, count 2 2006.201.09:02:31.70#ibcon#about to read 4, iclass 25, count 2 2006.201.09:02:31.70#ibcon#read 4, iclass 25, count 2 2006.201.09:02:31.70#ibcon#about to read 5, iclass 25, count 2 2006.201.09:02:31.70#ibcon#read 5, iclass 25, count 2 2006.201.09:02:31.70#ibcon#about to read 6, iclass 25, count 2 2006.201.09:02:31.70#ibcon#read 6, iclass 25, count 2 2006.201.09:02:31.70#ibcon#end of sib2, iclass 25, count 2 2006.201.09:02:31.70#ibcon#*mode == 0, iclass 25, count 2 2006.201.09:02:31.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.09:02:31.70#ibcon#[25=AT06-05\r\n] 2006.201.09:02:31.70#ibcon#*before write, iclass 25, count 2 2006.201.09:02:31.70#ibcon#enter sib2, iclass 25, count 2 2006.201.09:02:31.70#ibcon#flushed, iclass 25, count 2 2006.201.09:02:31.70#ibcon#about to write, iclass 25, count 2 2006.201.09:02:31.70#ibcon#wrote, iclass 25, count 2 2006.201.09:02:31.70#ibcon#about to read 3, iclass 25, count 2 2006.201.09:02:31.73#ibcon#read 3, iclass 25, count 2 2006.201.09:02:31.73#ibcon#about to read 4, iclass 25, count 2 2006.201.09:02:31.73#ibcon#read 4, iclass 25, count 2 2006.201.09:02:31.73#ibcon#about to read 5, iclass 25, count 2 2006.201.09:02:31.73#ibcon#read 5, iclass 25, count 2 2006.201.09:02:31.73#ibcon#about to read 6, iclass 25, count 2 2006.201.09:02:31.73#ibcon#read 6, iclass 25, count 2 2006.201.09:02:31.73#ibcon#end of sib2, iclass 25, count 2 2006.201.09:02:31.73#ibcon#*after write, iclass 25, count 2 2006.201.09:02:31.73#ibcon#*before return 0, iclass 25, count 2 2006.201.09:02:31.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:31.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:31.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.09:02:31.73#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:31.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:31.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:31.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:31.85#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:02:31.85#ibcon#first serial, iclass 25, count 0 2006.201.09:02:31.85#ibcon#enter sib2, iclass 25, count 0 2006.201.09:02:31.85#ibcon#flushed, iclass 25, count 0 2006.201.09:02:31.85#ibcon#about to write, iclass 25, count 0 2006.201.09:02:31.85#ibcon#wrote, iclass 25, count 0 2006.201.09:02:31.85#ibcon#about to read 3, iclass 25, count 0 2006.201.09:02:31.87#ibcon#read 3, iclass 25, count 0 2006.201.09:02:31.87#ibcon#about to read 4, iclass 25, count 0 2006.201.09:02:31.87#ibcon#read 4, iclass 25, count 0 2006.201.09:02:31.87#ibcon#about to read 5, iclass 25, count 0 2006.201.09:02:31.87#ibcon#read 5, iclass 25, count 0 2006.201.09:02:31.87#ibcon#about to read 6, iclass 25, count 0 2006.201.09:02:31.87#ibcon#read 6, iclass 25, count 0 2006.201.09:02:31.87#ibcon#end of sib2, iclass 25, count 0 2006.201.09:02:31.87#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:02:31.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:02:31.87#ibcon#[25=USB\r\n] 2006.201.09:02:31.87#ibcon#*before write, iclass 25, count 0 2006.201.09:02:31.87#ibcon#enter sib2, iclass 25, count 0 2006.201.09:02:31.87#ibcon#flushed, iclass 25, count 0 2006.201.09:02:31.87#ibcon#about to write, iclass 25, count 0 2006.201.09:02:31.87#ibcon#wrote, iclass 25, count 0 2006.201.09:02:31.87#ibcon#about to read 3, iclass 25, count 0 2006.201.09:02:31.90#ibcon#read 3, iclass 25, count 0 2006.201.09:02:31.90#ibcon#about to read 4, iclass 25, count 0 2006.201.09:02:31.90#ibcon#read 4, iclass 25, count 0 2006.201.09:02:31.90#ibcon#about to read 5, iclass 25, count 0 2006.201.09:02:31.90#ibcon#read 5, iclass 25, count 0 2006.201.09:02:31.90#ibcon#about to read 6, iclass 25, count 0 2006.201.09:02:31.90#ibcon#read 6, iclass 25, count 0 2006.201.09:02:31.90#ibcon#end of sib2, iclass 25, count 0 2006.201.09:02:31.90#ibcon#*after write, iclass 25, count 0 2006.201.09:02:31.90#ibcon#*before return 0, iclass 25, count 0 2006.201.09:02:31.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:31.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:31.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:02:31.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:02:31.90$vck44/valo=7,864.99 2006.201.09:02:31.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.09:02:31.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.09:02:31.90#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:31.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:31.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:31.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:31.90#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:02:31.90#ibcon#first serial, iclass 27, count 0 2006.201.09:02:31.90#ibcon#enter sib2, iclass 27, count 0 2006.201.09:02:31.90#ibcon#flushed, iclass 27, count 0 2006.201.09:02:31.90#ibcon#about to write, iclass 27, count 0 2006.201.09:02:31.90#ibcon#wrote, iclass 27, count 0 2006.201.09:02:31.90#ibcon#about to read 3, iclass 27, count 0 2006.201.09:02:31.92#ibcon#read 3, iclass 27, count 0 2006.201.09:02:31.92#ibcon#about to read 4, iclass 27, count 0 2006.201.09:02:31.92#ibcon#read 4, iclass 27, count 0 2006.201.09:02:31.92#ibcon#about to read 5, iclass 27, count 0 2006.201.09:02:31.92#ibcon#read 5, iclass 27, count 0 2006.201.09:02:31.92#ibcon#about to read 6, iclass 27, count 0 2006.201.09:02:31.92#ibcon#read 6, iclass 27, count 0 2006.201.09:02:31.92#ibcon#end of sib2, iclass 27, count 0 2006.201.09:02:31.92#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:02:31.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:02:31.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:02:31.92#ibcon#*before write, iclass 27, count 0 2006.201.09:02:31.92#ibcon#enter sib2, iclass 27, count 0 2006.201.09:02:31.92#ibcon#flushed, iclass 27, count 0 2006.201.09:02:31.92#ibcon#about to write, iclass 27, count 0 2006.201.09:02:31.92#ibcon#wrote, iclass 27, count 0 2006.201.09:02:31.92#ibcon#about to read 3, iclass 27, count 0 2006.201.09:02:31.96#ibcon#read 3, iclass 27, count 0 2006.201.09:02:31.96#ibcon#about to read 4, iclass 27, count 0 2006.201.09:02:31.96#ibcon#read 4, iclass 27, count 0 2006.201.09:02:31.96#ibcon#about to read 5, iclass 27, count 0 2006.201.09:02:31.96#ibcon#read 5, iclass 27, count 0 2006.201.09:02:31.96#ibcon#about to read 6, iclass 27, count 0 2006.201.09:02:31.96#ibcon#read 6, iclass 27, count 0 2006.201.09:02:31.96#ibcon#end of sib2, iclass 27, count 0 2006.201.09:02:31.96#ibcon#*after write, iclass 27, count 0 2006.201.09:02:31.96#ibcon#*before return 0, iclass 27, count 0 2006.201.09:02:31.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:31.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:31.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:02:31.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:02:31.96$vck44/va=7,5 2006.201.09:02:31.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.09:02:31.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.09:02:31.96#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:31.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:32.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:32.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:32.02#ibcon#enter wrdev, iclass 29, count 2 2006.201.09:02:32.02#ibcon#first serial, iclass 29, count 2 2006.201.09:02:32.02#ibcon#enter sib2, iclass 29, count 2 2006.201.09:02:32.02#ibcon#flushed, iclass 29, count 2 2006.201.09:02:32.02#ibcon#about to write, iclass 29, count 2 2006.201.09:02:32.02#ibcon#wrote, iclass 29, count 2 2006.201.09:02:32.02#ibcon#about to read 3, iclass 29, count 2 2006.201.09:02:32.04#ibcon#read 3, iclass 29, count 2 2006.201.09:02:32.04#ibcon#about to read 4, iclass 29, count 2 2006.201.09:02:32.04#ibcon#read 4, iclass 29, count 2 2006.201.09:02:32.04#ibcon#about to read 5, iclass 29, count 2 2006.201.09:02:32.04#ibcon#read 5, iclass 29, count 2 2006.201.09:02:32.04#ibcon#about to read 6, iclass 29, count 2 2006.201.09:02:32.04#ibcon#read 6, iclass 29, count 2 2006.201.09:02:32.04#ibcon#end of sib2, iclass 29, count 2 2006.201.09:02:32.04#ibcon#*mode == 0, iclass 29, count 2 2006.201.09:02:32.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.09:02:32.04#ibcon#[25=AT07-05\r\n] 2006.201.09:02:32.04#ibcon#*before write, iclass 29, count 2 2006.201.09:02:32.04#ibcon#enter sib2, iclass 29, count 2 2006.201.09:02:32.04#ibcon#flushed, iclass 29, count 2 2006.201.09:02:32.04#ibcon#about to write, iclass 29, count 2 2006.201.09:02:32.04#ibcon#wrote, iclass 29, count 2 2006.201.09:02:32.04#ibcon#about to read 3, iclass 29, count 2 2006.201.09:02:32.07#ibcon#read 3, iclass 29, count 2 2006.201.09:02:32.07#ibcon#about to read 4, iclass 29, count 2 2006.201.09:02:32.07#ibcon#read 4, iclass 29, count 2 2006.201.09:02:32.07#ibcon#about to read 5, iclass 29, count 2 2006.201.09:02:32.07#ibcon#read 5, iclass 29, count 2 2006.201.09:02:32.07#ibcon#about to read 6, iclass 29, count 2 2006.201.09:02:32.07#ibcon#read 6, iclass 29, count 2 2006.201.09:02:32.07#ibcon#end of sib2, iclass 29, count 2 2006.201.09:02:32.07#ibcon#*after write, iclass 29, count 2 2006.201.09:02:32.07#ibcon#*before return 0, iclass 29, count 2 2006.201.09:02:32.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:32.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:32.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.09:02:32.07#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:32.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:32.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:32.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:32.19#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:02:32.19#ibcon#first serial, iclass 29, count 0 2006.201.09:02:32.19#ibcon#enter sib2, iclass 29, count 0 2006.201.09:02:32.19#ibcon#flushed, iclass 29, count 0 2006.201.09:02:32.19#ibcon#about to write, iclass 29, count 0 2006.201.09:02:32.19#ibcon#wrote, iclass 29, count 0 2006.201.09:02:32.19#ibcon#about to read 3, iclass 29, count 0 2006.201.09:02:32.22#ibcon#read 3, iclass 29, count 0 2006.201.09:02:32.22#ibcon#about to read 4, iclass 29, count 0 2006.201.09:02:32.22#ibcon#read 4, iclass 29, count 0 2006.201.09:02:32.22#ibcon#about to read 5, iclass 29, count 0 2006.201.09:02:32.22#ibcon#read 5, iclass 29, count 0 2006.201.09:02:32.22#ibcon#about to read 6, iclass 29, count 0 2006.201.09:02:32.22#ibcon#read 6, iclass 29, count 0 2006.201.09:02:32.22#ibcon#end of sib2, iclass 29, count 0 2006.201.09:02:32.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:02:32.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:02:32.22#ibcon#[25=USB\r\n] 2006.201.09:02:32.22#ibcon#*before write, iclass 29, count 0 2006.201.09:02:32.22#ibcon#enter sib2, iclass 29, count 0 2006.201.09:02:32.22#ibcon#flushed, iclass 29, count 0 2006.201.09:02:32.22#ibcon#about to write, iclass 29, count 0 2006.201.09:02:32.22#ibcon#wrote, iclass 29, count 0 2006.201.09:02:32.22#ibcon#about to read 3, iclass 29, count 0 2006.201.09:02:32.25#ibcon#read 3, iclass 29, count 0 2006.201.09:02:32.25#ibcon#about to read 4, iclass 29, count 0 2006.201.09:02:32.25#ibcon#read 4, iclass 29, count 0 2006.201.09:02:32.25#ibcon#about to read 5, iclass 29, count 0 2006.201.09:02:32.25#ibcon#read 5, iclass 29, count 0 2006.201.09:02:32.25#ibcon#about to read 6, iclass 29, count 0 2006.201.09:02:32.25#ibcon#read 6, iclass 29, count 0 2006.201.09:02:32.25#ibcon#end of sib2, iclass 29, count 0 2006.201.09:02:32.25#ibcon#*after write, iclass 29, count 0 2006.201.09:02:32.25#ibcon#*before return 0, iclass 29, count 0 2006.201.09:02:32.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:32.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:32.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:02:32.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:02:32.25$vck44/valo=8,884.99 2006.201.09:02:32.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.09:02:32.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.09:02:32.25#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:32.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:32.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:32.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:32.25#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:02:32.25#ibcon#first serial, iclass 31, count 0 2006.201.09:02:32.25#ibcon#enter sib2, iclass 31, count 0 2006.201.09:02:32.25#ibcon#flushed, iclass 31, count 0 2006.201.09:02:32.25#ibcon#about to write, iclass 31, count 0 2006.201.09:02:32.25#ibcon#wrote, iclass 31, count 0 2006.201.09:02:32.25#ibcon#about to read 3, iclass 31, count 0 2006.201.09:02:32.27#ibcon#read 3, iclass 31, count 0 2006.201.09:02:32.27#ibcon#about to read 4, iclass 31, count 0 2006.201.09:02:32.27#ibcon#read 4, iclass 31, count 0 2006.201.09:02:32.27#ibcon#about to read 5, iclass 31, count 0 2006.201.09:02:32.27#ibcon#read 5, iclass 31, count 0 2006.201.09:02:32.27#ibcon#about to read 6, iclass 31, count 0 2006.201.09:02:32.27#ibcon#read 6, iclass 31, count 0 2006.201.09:02:32.27#ibcon#end of sib2, iclass 31, count 0 2006.201.09:02:32.27#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:02:32.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:02:32.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:02:32.27#ibcon#*before write, iclass 31, count 0 2006.201.09:02:32.27#ibcon#enter sib2, iclass 31, count 0 2006.201.09:02:32.27#ibcon#flushed, iclass 31, count 0 2006.201.09:02:32.27#ibcon#about to write, iclass 31, count 0 2006.201.09:02:32.27#ibcon#wrote, iclass 31, count 0 2006.201.09:02:32.27#ibcon#about to read 3, iclass 31, count 0 2006.201.09:02:32.31#ibcon#read 3, iclass 31, count 0 2006.201.09:02:32.31#ibcon#about to read 4, iclass 31, count 0 2006.201.09:02:32.31#ibcon#read 4, iclass 31, count 0 2006.201.09:02:32.31#ibcon#about to read 5, iclass 31, count 0 2006.201.09:02:32.31#ibcon#read 5, iclass 31, count 0 2006.201.09:02:32.31#ibcon#about to read 6, iclass 31, count 0 2006.201.09:02:32.31#ibcon#read 6, iclass 31, count 0 2006.201.09:02:32.31#ibcon#end of sib2, iclass 31, count 0 2006.201.09:02:32.31#ibcon#*after write, iclass 31, count 0 2006.201.09:02:32.31#ibcon#*before return 0, iclass 31, count 0 2006.201.09:02:32.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:32.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:32.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:02:32.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:02:32.31$vck44/va=8,4 2006.201.09:02:32.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.09:02:32.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.09:02:32.31#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:32.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:02:32.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:02:32.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:02:32.37#ibcon#enter wrdev, iclass 33, count 2 2006.201.09:02:32.37#ibcon#first serial, iclass 33, count 2 2006.201.09:02:32.37#ibcon#enter sib2, iclass 33, count 2 2006.201.09:02:32.37#ibcon#flushed, iclass 33, count 2 2006.201.09:02:32.37#ibcon#about to write, iclass 33, count 2 2006.201.09:02:32.37#ibcon#wrote, iclass 33, count 2 2006.201.09:02:32.37#ibcon#about to read 3, iclass 33, count 2 2006.201.09:02:32.39#ibcon#read 3, iclass 33, count 2 2006.201.09:02:32.39#ibcon#about to read 4, iclass 33, count 2 2006.201.09:02:32.39#ibcon#read 4, iclass 33, count 2 2006.201.09:02:32.39#ibcon#about to read 5, iclass 33, count 2 2006.201.09:02:32.39#ibcon#read 5, iclass 33, count 2 2006.201.09:02:32.39#ibcon#about to read 6, iclass 33, count 2 2006.201.09:02:32.39#ibcon#read 6, iclass 33, count 2 2006.201.09:02:32.39#ibcon#end of sib2, iclass 33, count 2 2006.201.09:02:32.39#ibcon#*mode == 0, iclass 33, count 2 2006.201.09:02:32.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.09:02:32.39#ibcon#[25=AT08-04\r\n] 2006.201.09:02:32.39#ibcon#*before write, iclass 33, count 2 2006.201.09:02:32.39#ibcon#enter sib2, iclass 33, count 2 2006.201.09:02:32.39#ibcon#flushed, iclass 33, count 2 2006.201.09:02:32.39#ibcon#about to write, iclass 33, count 2 2006.201.09:02:32.39#ibcon#wrote, iclass 33, count 2 2006.201.09:02:32.39#ibcon#about to read 3, iclass 33, count 2 2006.201.09:02:32.42#ibcon#read 3, iclass 33, count 2 2006.201.09:02:32.42#ibcon#about to read 4, iclass 33, count 2 2006.201.09:02:32.42#ibcon#read 4, iclass 33, count 2 2006.201.09:02:32.42#ibcon#about to read 5, iclass 33, count 2 2006.201.09:02:32.42#ibcon#read 5, iclass 33, count 2 2006.201.09:02:32.42#ibcon#about to read 6, iclass 33, count 2 2006.201.09:02:32.42#ibcon#read 6, iclass 33, count 2 2006.201.09:02:32.42#ibcon#end of sib2, iclass 33, count 2 2006.201.09:02:32.42#ibcon#*after write, iclass 33, count 2 2006.201.09:02:32.42#ibcon#*before return 0, iclass 33, count 2 2006.201.09:02:32.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:02:32.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:02:32.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.09:02:32.42#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:32.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:02:32.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:02:32.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:02:32.54#ibcon#enter wrdev, iclass 33, count 0 2006.201.09:02:32.54#ibcon#first serial, iclass 33, count 0 2006.201.09:02:32.54#ibcon#enter sib2, iclass 33, count 0 2006.201.09:02:32.54#ibcon#flushed, iclass 33, count 0 2006.201.09:02:32.54#ibcon#about to write, iclass 33, count 0 2006.201.09:02:32.54#ibcon#wrote, iclass 33, count 0 2006.201.09:02:32.54#ibcon#about to read 3, iclass 33, count 0 2006.201.09:02:32.56#ibcon#read 3, iclass 33, count 0 2006.201.09:02:32.56#ibcon#about to read 4, iclass 33, count 0 2006.201.09:02:32.56#ibcon#read 4, iclass 33, count 0 2006.201.09:02:32.56#ibcon#about to read 5, iclass 33, count 0 2006.201.09:02:32.56#ibcon#read 5, iclass 33, count 0 2006.201.09:02:32.56#ibcon#about to read 6, iclass 33, count 0 2006.201.09:02:32.56#ibcon#read 6, iclass 33, count 0 2006.201.09:02:32.56#ibcon#end of sib2, iclass 33, count 0 2006.201.09:02:32.56#ibcon#*mode == 0, iclass 33, count 0 2006.201.09:02:32.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.09:02:32.56#ibcon#[25=USB\r\n] 2006.201.09:02:32.56#ibcon#*before write, iclass 33, count 0 2006.201.09:02:32.56#ibcon#enter sib2, iclass 33, count 0 2006.201.09:02:32.56#ibcon#flushed, iclass 33, count 0 2006.201.09:02:32.56#ibcon#about to write, iclass 33, count 0 2006.201.09:02:32.56#ibcon#wrote, iclass 33, count 0 2006.201.09:02:32.56#ibcon#about to read 3, iclass 33, count 0 2006.201.09:02:32.59#ibcon#read 3, iclass 33, count 0 2006.201.09:02:32.59#ibcon#about to read 4, iclass 33, count 0 2006.201.09:02:32.59#ibcon#read 4, iclass 33, count 0 2006.201.09:02:32.59#ibcon#about to read 5, iclass 33, count 0 2006.201.09:02:32.59#ibcon#read 5, iclass 33, count 0 2006.201.09:02:32.59#ibcon#about to read 6, iclass 33, count 0 2006.201.09:02:32.59#ibcon#read 6, iclass 33, count 0 2006.201.09:02:32.59#ibcon#end of sib2, iclass 33, count 0 2006.201.09:02:32.59#ibcon#*after write, iclass 33, count 0 2006.201.09:02:32.59#ibcon#*before return 0, iclass 33, count 0 2006.201.09:02:32.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:02:32.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:02:32.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.09:02:32.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.09:02:32.59$vck44/vblo=1,629.99 2006.201.09:02:32.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.09:02:32.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.09:02:32.59#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:32.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:02:32.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:02:32.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:02:32.59#ibcon#enter wrdev, iclass 35, count 0 2006.201.09:02:32.59#ibcon#first serial, iclass 35, count 0 2006.201.09:02:32.59#ibcon#enter sib2, iclass 35, count 0 2006.201.09:02:32.59#ibcon#flushed, iclass 35, count 0 2006.201.09:02:32.59#ibcon#about to write, iclass 35, count 0 2006.201.09:02:32.59#ibcon#wrote, iclass 35, count 0 2006.201.09:02:32.59#ibcon#about to read 3, iclass 35, count 0 2006.201.09:02:32.61#ibcon#read 3, iclass 35, count 0 2006.201.09:02:32.61#ibcon#about to read 4, iclass 35, count 0 2006.201.09:02:32.61#ibcon#read 4, iclass 35, count 0 2006.201.09:02:32.61#ibcon#about to read 5, iclass 35, count 0 2006.201.09:02:32.61#ibcon#read 5, iclass 35, count 0 2006.201.09:02:32.61#ibcon#about to read 6, iclass 35, count 0 2006.201.09:02:32.61#ibcon#read 6, iclass 35, count 0 2006.201.09:02:32.61#ibcon#end of sib2, iclass 35, count 0 2006.201.09:02:32.61#ibcon#*mode == 0, iclass 35, count 0 2006.201.09:02:32.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.09:02:32.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:02:32.61#ibcon#*before write, iclass 35, count 0 2006.201.09:02:32.61#ibcon#enter sib2, iclass 35, count 0 2006.201.09:02:32.61#ibcon#flushed, iclass 35, count 0 2006.201.09:02:32.61#ibcon#about to write, iclass 35, count 0 2006.201.09:02:32.61#ibcon#wrote, iclass 35, count 0 2006.201.09:02:32.61#ibcon#about to read 3, iclass 35, count 0 2006.201.09:02:32.65#ibcon#read 3, iclass 35, count 0 2006.201.09:02:32.65#ibcon#about to read 4, iclass 35, count 0 2006.201.09:02:32.65#ibcon#read 4, iclass 35, count 0 2006.201.09:02:32.65#ibcon#about to read 5, iclass 35, count 0 2006.201.09:02:32.65#ibcon#read 5, iclass 35, count 0 2006.201.09:02:32.65#ibcon#about to read 6, iclass 35, count 0 2006.201.09:02:32.65#ibcon#read 6, iclass 35, count 0 2006.201.09:02:32.65#ibcon#end of sib2, iclass 35, count 0 2006.201.09:02:32.65#ibcon#*after write, iclass 35, count 0 2006.201.09:02:32.65#ibcon#*before return 0, iclass 35, count 0 2006.201.09:02:32.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:02:32.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:02:32.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.09:02:32.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.09:02:32.65$vck44/vb=1,4 2006.201.09:02:32.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.09:02:32.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.09:02:32.65#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:32.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:02:32.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:02:32.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:02:32.65#ibcon#enter wrdev, iclass 37, count 2 2006.201.09:02:32.65#ibcon#first serial, iclass 37, count 2 2006.201.09:02:32.65#ibcon#enter sib2, iclass 37, count 2 2006.201.09:02:32.65#ibcon#flushed, iclass 37, count 2 2006.201.09:02:32.65#ibcon#about to write, iclass 37, count 2 2006.201.09:02:32.65#ibcon#wrote, iclass 37, count 2 2006.201.09:02:32.65#ibcon#about to read 3, iclass 37, count 2 2006.201.09:02:32.67#ibcon#read 3, iclass 37, count 2 2006.201.09:02:32.67#ibcon#about to read 4, iclass 37, count 2 2006.201.09:02:32.67#ibcon#read 4, iclass 37, count 2 2006.201.09:02:32.67#ibcon#about to read 5, iclass 37, count 2 2006.201.09:02:32.67#ibcon#read 5, iclass 37, count 2 2006.201.09:02:32.67#ibcon#about to read 6, iclass 37, count 2 2006.201.09:02:32.67#ibcon#read 6, iclass 37, count 2 2006.201.09:02:32.67#ibcon#end of sib2, iclass 37, count 2 2006.201.09:02:32.67#ibcon#*mode == 0, iclass 37, count 2 2006.201.09:02:32.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.09:02:32.67#ibcon#[27=AT01-04\r\n] 2006.201.09:02:32.67#ibcon#*before write, iclass 37, count 2 2006.201.09:02:32.67#ibcon#enter sib2, iclass 37, count 2 2006.201.09:02:32.67#ibcon#flushed, iclass 37, count 2 2006.201.09:02:32.67#ibcon#about to write, iclass 37, count 2 2006.201.09:02:32.67#ibcon#wrote, iclass 37, count 2 2006.201.09:02:32.67#ibcon#about to read 3, iclass 37, count 2 2006.201.09:02:32.70#ibcon#read 3, iclass 37, count 2 2006.201.09:02:32.70#ibcon#about to read 4, iclass 37, count 2 2006.201.09:02:32.70#ibcon#read 4, iclass 37, count 2 2006.201.09:02:32.70#ibcon#about to read 5, iclass 37, count 2 2006.201.09:02:32.70#ibcon#read 5, iclass 37, count 2 2006.201.09:02:32.70#ibcon#about to read 6, iclass 37, count 2 2006.201.09:02:32.70#ibcon#read 6, iclass 37, count 2 2006.201.09:02:32.70#ibcon#end of sib2, iclass 37, count 2 2006.201.09:02:32.70#ibcon#*after write, iclass 37, count 2 2006.201.09:02:32.70#ibcon#*before return 0, iclass 37, count 2 2006.201.09:02:32.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:02:32.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:02:32.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.09:02:32.70#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:32.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:02:32.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:02:32.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:02:32.82#ibcon#enter wrdev, iclass 37, count 0 2006.201.09:02:32.82#ibcon#first serial, iclass 37, count 0 2006.201.09:02:32.82#ibcon#enter sib2, iclass 37, count 0 2006.201.09:02:32.82#ibcon#flushed, iclass 37, count 0 2006.201.09:02:32.82#ibcon#about to write, iclass 37, count 0 2006.201.09:02:32.82#ibcon#wrote, iclass 37, count 0 2006.201.09:02:32.82#ibcon#about to read 3, iclass 37, count 0 2006.201.09:02:32.84#ibcon#read 3, iclass 37, count 0 2006.201.09:02:32.84#ibcon#about to read 4, iclass 37, count 0 2006.201.09:02:32.84#ibcon#read 4, iclass 37, count 0 2006.201.09:02:32.84#ibcon#about to read 5, iclass 37, count 0 2006.201.09:02:32.84#ibcon#read 5, iclass 37, count 0 2006.201.09:02:32.84#ibcon#about to read 6, iclass 37, count 0 2006.201.09:02:32.84#ibcon#read 6, iclass 37, count 0 2006.201.09:02:32.84#ibcon#end of sib2, iclass 37, count 0 2006.201.09:02:32.84#ibcon#*mode == 0, iclass 37, count 0 2006.201.09:02:32.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.09:02:32.84#ibcon#[27=USB\r\n] 2006.201.09:02:32.84#ibcon#*before write, iclass 37, count 0 2006.201.09:02:32.84#ibcon#enter sib2, iclass 37, count 0 2006.201.09:02:32.84#ibcon#flushed, iclass 37, count 0 2006.201.09:02:32.84#ibcon#about to write, iclass 37, count 0 2006.201.09:02:32.84#ibcon#wrote, iclass 37, count 0 2006.201.09:02:32.84#ibcon#about to read 3, iclass 37, count 0 2006.201.09:02:32.87#ibcon#read 3, iclass 37, count 0 2006.201.09:02:32.87#ibcon#about to read 4, iclass 37, count 0 2006.201.09:02:32.87#ibcon#read 4, iclass 37, count 0 2006.201.09:02:32.87#ibcon#about to read 5, iclass 37, count 0 2006.201.09:02:32.87#ibcon#read 5, iclass 37, count 0 2006.201.09:02:32.87#ibcon#about to read 6, iclass 37, count 0 2006.201.09:02:32.87#ibcon#read 6, iclass 37, count 0 2006.201.09:02:32.87#ibcon#end of sib2, iclass 37, count 0 2006.201.09:02:32.87#ibcon#*after write, iclass 37, count 0 2006.201.09:02:32.87#ibcon#*before return 0, iclass 37, count 0 2006.201.09:02:32.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:02:32.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:02:32.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.09:02:32.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.09:02:32.87$vck44/vblo=2,634.99 2006.201.09:02:32.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.09:02:32.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.09:02:32.87#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:32.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:32.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:32.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:32.87#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:02:32.87#ibcon#first serial, iclass 39, count 0 2006.201.09:02:32.87#ibcon#enter sib2, iclass 39, count 0 2006.201.09:02:32.87#ibcon#flushed, iclass 39, count 0 2006.201.09:02:32.87#ibcon#about to write, iclass 39, count 0 2006.201.09:02:32.87#ibcon#wrote, iclass 39, count 0 2006.201.09:02:32.87#ibcon#about to read 3, iclass 39, count 0 2006.201.09:02:32.89#ibcon#read 3, iclass 39, count 0 2006.201.09:02:32.89#ibcon#about to read 4, iclass 39, count 0 2006.201.09:02:32.89#ibcon#read 4, iclass 39, count 0 2006.201.09:02:32.89#ibcon#about to read 5, iclass 39, count 0 2006.201.09:02:32.89#ibcon#read 5, iclass 39, count 0 2006.201.09:02:32.89#ibcon#about to read 6, iclass 39, count 0 2006.201.09:02:32.89#ibcon#read 6, iclass 39, count 0 2006.201.09:02:32.89#ibcon#end of sib2, iclass 39, count 0 2006.201.09:02:32.89#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:02:32.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:02:32.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:02:32.89#ibcon#*before write, iclass 39, count 0 2006.201.09:02:32.89#ibcon#enter sib2, iclass 39, count 0 2006.201.09:02:32.89#ibcon#flushed, iclass 39, count 0 2006.201.09:02:32.89#ibcon#about to write, iclass 39, count 0 2006.201.09:02:32.89#ibcon#wrote, iclass 39, count 0 2006.201.09:02:32.89#ibcon#about to read 3, iclass 39, count 0 2006.201.09:02:32.93#ibcon#read 3, iclass 39, count 0 2006.201.09:02:32.93#ibcon#about to read 4, iclass 39, count 0 2006.201.09:02:32.93#ibcon#read 4, iclass 39, count 0 2006.201.09:02:32.93#ibcon#about to read 5, iclass 39, count 0 2006.201.09:02:32.93#ibcon#read 5, iclass 39, count 0 2006.201.09:02:32.93#ibcon#about to read 6, iclass 39, count 0 2006.201.09:02:32.93#ibcon#read 6, iclass 39, count 0 2006.201.09:02:32.93#ibcon#end of sib2, iclass 39, count 0 2006.201.09:02:32.93#ibcon#*after write, iclass 39, count 0 2006.201.09:02:32.93#ibcon#*before return 0, iclass 39, count 0 2006.201.09:02:32.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:32.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:02:32.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:02:32.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:02:32.93$vck44/vb=2,5 2006.201.09:02:32.93#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.09:02:32.93#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.09:02:32.93#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:32.93#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:32.99#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:32.99#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:32.99#ibcon#enter wrdev, iclass 2, count 2 2006.201.09:02:32.99#ibcon#first serial, iclass 2, count 2 2006.201.09:02:32.99#ibcon#enter sib2, iclass 2, count 2 2006.201.09:02:32.99#ibcon#flushed, iclass 2, count 2 2006.201.09:02:32.99#ibcon#about to write, iclass 2, count 2 2006.201.09:02:32.99#ibcon#wrote, iclass 2, count 2 2006.201.09:02:32.99#ibcon#about to read 3, iclass 2, count 2 2006.201.09:02:33.01#ibcon#read 3, iclass 2, count 2 2006.201.09:02:33.01#ibcon#about to read 4, iclass 2, count 2 2006.201.09:02:33.01#ibcon#read 4, iclass 2, count 2 2006.201.09:02:33.01#ibcon#about to read 5, iclass 2, count 2 2006.201.09:02:33.01#ibcon#read 5, iclass 2, count 2 2006.201.09:02:33.01#ibcon#about to read 6, iclass 2, count 2 2006.201.09:02:33.01#ibcon#read 6, iclass 2, count 2 2006.201.09:02:33.01#ibcon#end of sib2, iclass 2, count 2 2006.201.09:02:33.01#ibcon#*mode == 0, iclass 2, count 2 2006.201.09:02:33.01#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.09:02:33.01#ibcon#[27=AT02-05\r\n] 2006.201.09:02:33.01#ibcon#*before write, iclass 2, count 2 2006.201.09:02:33.01#ibcon#enter sib2, iclass 2, count 2 2006.201.09:02:33.01#ibcon#flushed, iclass 2, count 2 2006.201.09:02:33.01#ibcon#about to write, iclass 2, count 2 2006.201.09:02:33.01#ibcon#wrote, iclass 2, count 2 2006.201.09:02:33.01#ibcon#about to read 3, iclass 2, count 2 2006.201.09:02:33.04#ibcon#read 3, iclass 2, count 2 2006.201.09:02:33.04#ibcon#about to read 4, iclass 2, count 2 2006.201.09:02:33.04#ibcon#read 4, iclass 2, count 2 2006.201.09:02:33.04#ibcon#about to read 5, iclass 2, count 2 2006.201.09:02:33.04#ibcon#read 5, iclass 2, count 2 2006.201.09:02:33.04#ibcon#about to read 6, iclass 2, count 2 2006.201.09:02:33.04#ibcon#read 6, iclass 2, count 2 2006.201.09:02:33.04#ibcon#end of sib2, iclass 2, count 2 2006.201.09:02:33.04#ibcon#*after write, iclass 2, count 2 2006.201.09:02:33.04#ibcon#*before return 0, iclass 2, count 2 2006.201.09:02:33.04#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:33.04#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:02:33.04#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.09:02:33.04#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:33.04#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:33.16#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:33.16#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:33.16#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:02:33.16#ibcon#first serial, iclass 2, count 0 2006.201.09:02:33.16#ibcon#enter sib2, iclass 2, count 0 2006.201.09:02:33.16#ibcon#flushed, iclass 2, count 0 2006.201.09:02:33.16#ibcon#about to write, iclass 2, count 0 2006.201.09:02:33.16#ibcon#wrote, iclass 2, count 0 2006.201.09:02:33.16#ibcon#about to read 3, iclass 2, count 0 2006.201.09:02:33.18#ibcon#read 3, iclass 2, count 0 2006.201.09:02:33.18#ibcon#about to read 4, iclass 2, count 0 2006.201.09:02:33.18#ibcon#read 4, iclass 2, count 0 2006.201.09:02:33.18#ibcon#about to read 5, iclass 2, count 0 2006.201.09:02:33.18#ibcon#read 5, iclass 2, count 0 2006.201.09:02:33.18#ibcon#about to read 6, iclass 2, count 0 2006.201.09:02:33.18#ibcon#read 6, iclass 2, count 0 2006.201.09:02:33.18#ibcon#end of sib2, iclass 2, count 0 2006.201.09:02:33.18#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:02:33.18#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:02:33.18#ibcon#[27=USB\r\n] 2006.201.09:02:33.18#ibcon#*before write, iclass 2, count 0 2006.201.09:02:33.18#ibcon#enter sib2, iclass 2, count 0 2006.201.09:02:33.18#ibcon#flushed, iclass 2, count 0 2006.201.09:02:33.18#ibcon#about to write, iclass 2, count 0 2006.201.09:02:33.18#ibcon#wrote, iclass 2, count 0 2006.201.09:02:33.18#ibcon#about to read 3, iclass 2, count 0 2006.201.09:02:33.21#ibcon#read 3, iclass 2, count 0 2006.201.09:02:33.21#ibcon#about to read 4, iclass 2, count 0 2006.201.09:02:33.21#ibcon#read 4, iclass 2, count 0 2006.201.09:02:33.21#ibcon#about to read 5, iclass 2, count 0 2006.201.09:02:33.21#ibcon#read 5, iclass 2, count 0 2006.201.09:02:33.21#ibcon#about to read 6, iclass 2, count 0 2006.201.09:02:33.21#ibcon#read 6, iclass 2, count 0 2006.201.09:02:33.21#ibcon#end of sib2, iclass 2, count 0 2006.201.09:02:33.21#ibcon#*after write, iclass 2, count 0 2006.201.09:02:33.21#ibcon#*before return 0, iclass 2, count 0 2006.201.09:02:33.21#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:33.21#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:02:33.21#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:02:33.21#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:02:33.21$vck44/vblo=3,649.99 2006.201.09:02:33.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.09:02:33.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.09:02:33.21#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:33.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:33.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:33.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:33.21#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:02:33.21#ibcon#first serial, iclass 5, count 0 2006.201.09:02:33.21#ibcon#enter sib2, iclass 5, count 0 2006.201.09:02:33.21#ibcon#flushed, iclass 5, count 0 2006.201.09:02:33.21#ibcon#about to write, iclass 5, count 0 2006.201.09:02:33.21#ibcon#wrote, iclass 5, count 0 2006.201.09:02:33.21#ibcon#about to read 3, iclass 5, count 0 2006.201.09:02:33.23#ibcon#read 3, iclass 5, count 0 2006.201.09:02:33.23#ibcon#about to read 4, iclass 5, count 0 2006.201.09:02:33.23#ibcon#read 4, iclass 5, count 0 2006.201.09:02:33.23#ibcon#about to read 5, iclass 5, count 0 2006.201.09:02:33.23#ibcon#read 5, iclass 5, count 0 2006.201.09:02:33.23#ibcon#about to read 6, iclass 5, count 0 2006.201.09:02:33.23#ibcon#read 6, iclass 5, count 0 2006.201.09:02:33.23#ibcon#end of sib2, iclass 5, count 0 2006.201.09:02:33.23#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:02:33.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:02:33.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:02:33.23#ibcon#*before write, iclass 5, count 0 2006.201.09:02:33.23#ibcon#enter sib2, iclass 5, count 0 2006.201.09:02:33.23#ibcon#flushed, iclass 5, count 0 2006.201.09:02:33.23#ibcon#about to write, iclass 5, count 0 2006.201.09:02:33.23#ibcon#wrote, iclass 5, count 0 2006.201.09:02:33.23#ibcon#about to read 3, iclass 5, count 0 2006.201.09:02:33.27#ibcon#read 3, iclass 5, count 0 2006.201.09:02:33.27#ibcon#about to read 4, iclass 5, count 0 2006.201.09:02:33.27#ibcon#read 4, iclass 5, count 0 2006.201.09:02:33.27#ibcon#about to read 5, iclass 5, count 0 2006.201.09:02:33.27#ibcon#read 5, iclass 5, count 0 2006.201.09:02:33.27#ibcon#about to read 6, iclass 5, count 0 2006.201.09:02:33.27#ibcon#read 6, iclass 5, count 0 2006.201.09:02:33.27#ibcon#end of sib2, iclass 5, count 0 2006.201.09:02:33.27#ibcon#*after write, iclass 5, count 0 2006.201.09:02:33.27#ibcon#*before return 0, iclass 5, count 0 2006.201.09:02:33.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:33.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:02:33.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:02:33.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:02:33.27$vck44/vb=3,4 2006.201.09:02:33.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.09:02:33.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.09:02:33.27#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:33.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:33.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:33.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:33.33#ibcon#enter wrdev, iclass 7, count 2 2006.201.09:02:33.33#ibcon#first serial, iclass 7, count 2 2006.201.09:02:33.33#ibcon#enter sib2, iclass 7, count 2 2006.201.09:02:33.33#ibcon#flushed, iclass 7, count 2 2006.201.09:02:33.33#ibcon#about to write, iclass 7, count 2 2006.201.09:02:33.33#ibcon#wrote, iclass 7, count 2 2006.201.09:02:33.33#ibcon#about to read 3, iclass 7, count 2 2006.201.09:02:33.35#ibcon#read 3, iclass 7, count 2 2006.201.09:02:33.35#ibcon#about to read 4, iclass 7, count 2 2006.201.09:02:33.35#ibcon#read 4, iclass 7, count 2 2006.201.09:02:33.35#ibcon#about to read 5, iclass 7, count 2 2006.201.09:02:33.35#ibcon#read 5, iclass 7, count 2 2006.201.09:02:33.35#ibcon#about to read 6, iclass 7, count 2 2006.201.09:02:33.35#ibcon#read 6, iclass 7, count 2 2006.201.09:02:33.35#ibcon#end of sib2, iclass 7, count 2 2006.201.09:02:33.35#ibcon#*mode == 0, iclass 7, count 2 2006.201.09:02:33.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.09:02:33.35#ibcon#[27=AT03-04\r\n] 2006.201.09:02:33.35#ibcon#*before write, iclass 7, count 2 2006.201.09:02:33.35#ibcon#enter sib2, iclass 7, count 2 2006.201.09:02:33.35#ibcon#flushed, iclass 7, count 2 2006.201.09:02:33.35#ibcon#about to write, iclass 7, count 2 2006.201.09:02:33.35#ibcon#wrote, iclass 7, count 2 2006.201.09:02:33.35#ibcon#about to read 3, iclass 7, count 2 2006.201.09:02:33.38#ibcon#read 3, iclass 7, count 2 2006.201.09:02:33.38#ibcon#about to read 4, iclass 7, count 2 2006.201.09:02:33.38#ibcon#read 4, iclass 7, count 2 2006.201.09:02:33.38#ibcon#about to read 5, iclass 7, count 2 2006.201.09:02:33.38#ibcon#read 5, iclass 7, count 2 2006.201.09:02:33.38#ibcon#about to read 6, iclass 7, count 2 2006.201.09:02:33.38#ibcon#read 6, iclass 7, count 2 2006.201.09:02:33.38#ibcon#end of sib2, iclass 7, count 2 2006.201.09:02:33.38#ibcon#*after write, iclass 7, count 2 2006.201.09:02:33.38#ibcon#*before return 0, iclass 7, count 2 2006.201.09:02:33.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:33.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:02:33.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.09:02:33.38#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:33.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:33.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:33.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:33.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:02:33.50#ibcon#first serial, iclass 7, count 0 2006.201.09:02:33.50#ibcon#enter sib2, iclass 7, count 0 2006.201.09:02:33.50#ibcon#flushed, iclass 7, count 0 2006.201.09:02:33.50#ibcon#about to write, iclass 7, count 0 2006.201.09:02:33.50#ibcon#wrote, iclass 7, count 0 2006.201.09:02:33.50#ibcon#about to read 3, iclass 7, count 0 2006.201.09:02:33.52#ibcon#read 3, iclass 7, count 0 2006.201.09:02:33.52#ibcon#about to read 4, iclass 7, count 0 2006.201.09:02:33.52#ibcon#read 4, iclass 7, count 0 2006.201.09:02:33.52#ibcon#about to read 5, iclass 7, count 0 2006.201.09:02:33.52#ibcon#read 5, iclass 7, count 0 2006.201.09:02:33.52#ibcon#about to read 6, iclass 7, count 0 2006.201.09:02:33.52#ibcon#read 6, iclass 7, count 0 2006.201.09:02:33.52#ibcon#end of sib2, iclass 7, count 0 2006.201.09:02:33.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:02:33.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:02:33.52#ibcon#[27=USB\r\n] 2006.201.09:02:33.52#ibcon#*before write, iclass 7, count 0 2006.201.09:02:33.52#ibcon#enter sib2, iclass 7, count 0 2006.201.09:02:33.52#ibcon#flushed, iclass 7, count 0 2006.201.09:02:33.52#ibcon#about to write, iclass 7, count 0 2006.201.09:02:33.52#ibcon#wrote, iclass 7, count 0 2006.201.09:02:33.52#ibcon#about to read 3, iclass 7, count 0 2006.201.09:02:33.55#ibcon#read 3, iclass 7, count 0 2006.201.09:02:33.55#ibcon#about to read 4, iclass 7, count 0 2006.201.09:02:33.55#ibcon#read 4, iclass 7, count 0 2006.201.09:02:33.55#ibcon#about to read 5, iclass 7, count 0 2006.201.09:02:33.55#ibcon#read 5, iclass 7, count 0 2006.201.09:02:33.55#ibcon#about to read 6, iclass 7, count 0 2006.201.09:02:33.55#ibcon#read 6, iclass 7, count 0 2006.201.09:02:33.55#ibcon#end of sib2, iclass 7, count 0 2006.201.09:02:33.55#ibcon#*after write, iclass 7, count 0 2006.201.09:02:33.55#ibcon#*before return 0, iclass 7, count 0 2006.201.09:02:33.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:33.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:02:33.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:02:33.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:02:33.55$vck44/vblo=4,679.99 2006.201.09:02:33.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.09:02:33.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.09:02:33.55#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:33.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:33.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:33.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:33.55#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:02:33.55#ibcon#first serial, iclass 11, count 0 2006.201.09:02:33.55#ibcon#enter sib2, iclass 11, count 0 2006.201.09:02:33.55#ibcon#flushed, iclass 11, count 0 2006.201.09:02:33.55#ibcon#about to write, iclass 11, count 0 2006.201.09:02:33.55#ibcon#wrote, iclass 11, count 0 2006.201.09:02:33.55#ibcon#about to read 3, iclass 11, count 0 2006.201.09:02:33.57#ibcon#read 3, iclass 11, count 0 2006.201.09:02:33.57#ibcon#about to read 4, iclass 11, count 0 2006.201.09:02:33.57#ibcon#read 4, iclass 11, count 0 2006.201.09:02:33.57#ibcon#about to read 5, iclass 11, count 0 2006.201.09:02:33.57#ibcon#read 5, iclass 11, count 0 2006.201.09:02:33.57#ibcon#about to read 6, iclass 11, count 0 2006.201.09:02:33.57#ibcon#read 6, iclass 11, count 0 2006.201.09:02:33.57#ibcon#end of sib2, iclass 11, count 0 2006.201.09:02:33.57#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:02:33.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:02:33.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:02:33.57#ibcon#*before write, iclass 11, count 0 2006.201.09:02:33.57#ibcon#enter sib2, iclass 11, count 0 2006.201.09:02:33.57#ibcon#flushed, iclass 11, count 0 2006.201.09:02:33.57#ibcon#about to write, iclass 11, count 0 2006.201.09:02:33.57#ibcon#wrote, iclass 11, count 0 2006.201.09:02:33.57#ibcon#about to read 3, iclass 11, count 0 2006.201.09:02:33.61#ibcon#read 3, iclass 11, count 0 2006.201.09:02:33.61#ibcon#about to read 4, iclass 11, count 0 2006.201.09:02:33.61#ibcon#read 4, iclass 11, count 0 2006.201.09:02:33.61#ibcon#about to read 5, iclass 11, count 0 2006.201.09:02:33.61#ibcon#read 5, iclass 11, count 0 2006.201.09:02:33.61#ibcon#about to read 6, iclass 11, count 0 2006.201.09:02:33.61#ibcon#read 6, iclass 11, count 0 2006.201.09:02:33.61#ibcon#end of sib2, iclass 11, count 0 2006.201.09:02:33.61#ibcon#*after write, iclass 11, count 0 2006.201.09:02:33.61#ibcon#*before return 0, iclass 11, count 0 2006.201.09:02:33.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:33.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:02:33.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:02:33.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:02:33.61$vck44/vb=4,5 2006.201.09:02:33.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.09:02:33.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.09:02:33.61#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:33.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:33.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:33.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:33.67#ibcon#enter wrdev, iclass 13, count 2 2006.201.09:02:33.67#ibcon#first serial, iclass 13, count 2 2006.201.09:02:33.67#ibcon#enter sib2, iclass 13, count 2 2006.201.09:02:33.67#ibcon#flushed, iclass 13, count 2 2006.201.09:02:33.67#ibcon#about to write, iclass 13, count 2 2006.201.09:02:33.67#ibcon#wrote, iclass 13, count 2 2006.201.09:02:33.67#ibcon#about to read 3, iclass 13, count 2 2006.201.09:02:33.69#ibcon#read 3, iclass 13, count 2 2006.201.09:02:33.69#ibcon#about to read 4, iclass 13, count 2 2006.201.09:02:33.69#ibcon#read 4, iclass 13, count 2 2006.201.09:02:33.69#ibcon#about to read 5, iclass 13, count 2 2006.201.09:02:33.69#ibcon#read 5, iclass 13, count 2 2006.201.09:02:33.69#ibcon#about to read 6, iclass 13, count 2 2006.201.09:02:33.69#ibcon#read 6, iclass 13, count 2 2006.201.09:02:33.69#ibcon#end of sib2, iclass 13, count 2 2006.201.09:02:33.69#ibcon#*mode == 0, iclass 13, count 2 2006.201.09:02:33.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.09:02:33.69#ibcon#[27=AT04-05\r\n] 2006.201.09:02:33.69#ibcon#*before write, iclass 13, count 2 2006.201.09:02:33.69#ibcon#enter sib2, iclass 13, count 2 2006.201.09:02:33.69#ibcon#flushed, iclass 13, count 2 2006.201.09:02:33.69#ibcon#about to write, iclass 13, count 2 2006.201.09:02:33.69#ibcon#wrote, iclass 13, count 2 2006.201.09:02:33.69#ibcon#about to read 3, iclass 13, count 2 2006.201.09:02:33.72#ibcon#read 3, iclass 13, count 2 2006.201.09:02:33.72#ibcon#about to read 4, iclass 13, count 2 2006.201.09:02:33.72#ibcon#read 4, iclass 13, count 2 2006.201.09:02:33.72#ibcon#about to read 5, iclass 13, count 2 2006.201.09:02:33.72#ibcon#read 5, iclass 13, count 2 2006.201.09:02:33.72#ibcon#about to read 6, iclass 13, count 2 2006.201.09:02:33.72#ibcon#read 6, iclass 13, count 2 2006.201.09:02:33.72#ibcon#end of sib2, iclass 13, count 2 2006.201.09:02:33.72#ibcon#*after write, iclass 13, count 2 2006.201.09:02:33.72#ibcon#*before return 0, iclass 13, count 2 2006.201.09:02:33.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:33.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:02:33.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.09:02:33.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:33.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:33.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:33.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:33.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:02:33.84#ibcon#first serial, iclass 13, count 0 2006.201.09:02:33.84#ibcon#enter sib2, iclass 13, count 0 2006.201.09:02:33.84#ibcon#flushed, iclass 13, count 0 2006.201.09:02:33.84#ibcon#about to write, iclass 13, count 0 2006.201.09:02:33.84#ibcon#wrote, iclass 13, count 0 2006.201.09:02:33.84#ibcon#about to read 3, iclass 13, count 0 2006.201.09:02:33.86#ibcon#read 3, iclass 13, count 0 2006.201.09:02:33.86#ibcon#about to read 4, iclass 13, count 0 2006.201.09:02:33.86#ibcon#read 4, iclass 13, count 0 2006.201.09:02:33.86#ibcon#about to read 5, iclass 13, count 0 2006.201.09:02:33.86#ibcon#read 5, iclass 13, count 0 2006.201.09:02:33.86#ibcon#about to read 6, iclass 13, count 0 2006.201.09:02:33.86#ibcon#read 6, iclass 13, count 0 2006.201.09:02:33.86#ibcon#end of sib2, iclass 13, count 0 2006.201.09:02:33.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:02:33.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:02:33.86#ibcon#[27=USB\r\n] 2006.201.09:02:33.86#ibcon#*before write, iclass 13, count 0 2006.201.09:02:33.86#ibcon#enter sib2, iclass 13, count 0 2006.201.09:02:33.86#ibcon#flushed, iclass 13, count 0 2006.201.09:02:33.86#ibcon#about to write, iclass 13, count 0 2006.201.09:02:33.86#ibcon#wrote, iclass 13, count 0 2006.201.09:02:33.86#ibcon#about to read 3, iclass 13, count 0 2006.201.09:02:33.89#ibcon#read 3, iclass 13, count 0 2006.201.09:02:33.89#ibcon#about to read 4, iclass 13, count 0 2006.201.09:02:33.89#ibcon#read 4, iclass 13, count 0 2006.201.09:02:33.89#ibcon#about to read 5, iclass 13, count 0 2006.201.09:02:33.89#ibcon#read 5, iclass 13, count 0 2006.201.09:02:33.89#ibcon#about to read 6, iclass 13, count 0 2006.201.09:02:33.89#ibcon#read 6, iclass 13, count 0 2006.201.09:02:33.89#ibcon#end of sib2, iclass 13, count 0 2006.201.09:02:33.89#ibcon#*after write, iclass 13, count 0 2006.201.09:02:33.89#ibcon#*before return 0, iclass 13, count 0 2006.201.09:02:33.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:33.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:02:33.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:02:33.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:02:33.89$vck44/vblo=5,709.99 2006.201.09:02:33.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.09:02:33.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.09:02:33.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:33.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:33.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:33.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:33.89#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:02:33.89#ibcon#first serial, iclass 15, count 0 2006.201.09:02:33.89#ibcon#enter sib2, iclass 15, count 0 2006.201.09:02:33.89#ibcon#flushed, iclass 15, count 0 2006.201.09:02:33.89#ibcon#about to write, iclass 15, count 0 2006.201.09:02:33.89#ibcon#wrote, iclass 15, count 0 2006.201.09:02:33.89#ibcon#about to read 3, iclass 15, count 0 2006.201.09:02:33.91#ibcon#read 3, iclass 15, count 0 2006.201.09:02:33.91#ibcon#about to read 4, iclass 15, count 0 2006.201.09:02:33.91#ibcon#read 4, iclass 15, count 0 2006.201.09:02:33.91#ibcon#about to read 5, iclass 15, count 0 2006.201.09:02:33.91#ibcon#read 5, iclass 15, count 0 2006.201.09:02:33.91#ibcon#about to read 6, iclass 15, count 0 2006.201.09:02:33.91#ibcon#read 6, iclass 15, count 0 2006.201.09:02:33.91#ibcon#end of sib2, iclass 15, count 0 2006.201.09:02:33.91#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:02:33.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:02:33.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:02:33.91#ibcon#*before write, iclass 15, count 0 2006.201.09:02:33.91#ibcon#enter sib2, iclass 15, count 0 2006.201.09:02:33.91#ibcon#flushed, iclass 15, count 0 2006.201.09:02:33.91#ibcon#about to write, iclass 15, count 0 2006.201.09:02:33.91#ibcon#wrote, iclass 15, count 0 2006.201.09:02:33.91#ibcon#about to read 3, iclass 15, count 0 2006.201.09:02:33.96#ibcon#read 3, iclass 15, count 0 2006.201.09:02:33.96#ibcon#about to read 4, iclass 15, count 0 2006.201.09:02:33.96#ibcon#read 4, iclass 15, count 0 2006.201.09:02:33.96#ibcon#about to read 5, iclass 15, count 0 2006.201.09:02:33.96#ibcon#read 5, iclass 15, count 0 2006.201.09:02:33.96#ibcon#about to read 6, iclass 15, count 0 2006.201.09:02:33.96#ibcon#read 6, iclass 15, count 0 2006.201.09:02:33.96#ibcon#end of sib2, iclass 15, count 0 2006.201.09:02:33.96#ibcon#*after write, iclass 15, count 0 2006.201.09:02:33.96#ibcon#*before return 0, iclass 15, count 0 2006.201.09:02:33.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:33.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:02:33.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:02:33.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:02:33.96$vck44/vb=5,4 2006.201.09:02:33.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.09:02:33.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.09:02:33.96#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:33.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:34.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:34.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:34.01#ibcon#enter wrdev, iclass 17, count 2 2006.201.09:02:34.01#ibcon#first serial, iclass 17, count 2 2006.201.09:02:34.01#ibcon#enter sib2, iclass 17, count 2 2006.201.09:02:34.01#ibcon#flushed, iclass 17, count 2 2006.201.09:02:34.01#ibcon#about to write, iclass 17, count 2 2006.201.09:02:34.01#ibcon#wrote, iclass 17, count 2 2006.201.09:02:34.01#ibcon#about to read 3, iclass 17, count 2 2006.201.09:02:34.03#ibcon#read 3, iclass 17, count 2 2006.201.09:02:34.03#ibcon#about to read 4, iclass 17, count 2 2006.201.09:02:34.03#ibcon#read 4, iclass 17, count 2 2006.201.09:02:34.03#ibcon#about to read 5, iclass 17, count 2 2006.201.09:02:34.03#ibcon#read 5, iclass 17, count 2 2006.201.09:02:34.03#ibcon#about to read 6, iclass 17, count 2 2006.201.09:02:34.03#ibcon#read 6, iclass 17, count 2 2006.201.09:02:34.03#ibcon#end of sib2, iclass 17, count 2 2006.201.09:02:34.03#ibcon#*mode == 0, iclass 17, count 2 2006.201.09:02:34.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.09:02:34.03#ibcon#[27=AT05-04\r\n] 2006.201.09:02:34.03#ibcon#*before write, iclass 17, count 2 2006.201.09:02:34.03#ibcon#enter sib2, iclass 17, count 2 2006.201.09:02:34.03#ibcon#flushed, iclass 17, count 2 2006.201.09:02:34.03#ibcon#about to write, iclass 17, count 2 2006.201.09:02:34.03#ibcon#wrote, iclass 17, count 2 2006.201.09:02:34.03#ibcon#about to read 3, iclass 17, count 2 2006.201.09:02:34.06#ibcon#read 3, iclass 17, count 2 2006.201.09:02:34.06#ibcon#about to read 4, iclass 17, count 2 2006.201.09:02:34.06#ibcon#read 4, iclass 17, count 2 2006.201.09:02:34.06#ibcon#about to read 5, iclass 17, count 2 2006.201.09:02:34.06#ibcon#read 5, iclass 17, count 2 2006.201.09:02:34.06#ibcon#about to read 6, iclass 17, count 2 2006.201.09:02:34.06#ibcon#read 6, iclass 17, count 2 2006.201.09:02:34.06#ibcon#end of sib2, iclass 17, count 2 2006.201.09:02:34.06#ibcon#*after write, iclass 17, count 2 2006.201.09:02:34.06#ibcon#*before return 0, iclass 17, count 2 2006.201.09:02:34.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:34.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:02:34.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.09:02:34.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:34.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:34.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:34.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:34.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:02:34.18#ibcon#first serial, iclass 17, count 0 2006.201.09:02:34.18#ibcon#enter sib2, iclass 17, count 0 2006.201.09:02:34.18#ibcon#flushed, iclass 17, count 0 2006.201.09:02:34.18#ibcon#about to write, iclass 17, count 0 2006.201.09:02:34.18#ibcon#wrote, iclass 17, count 0 2006.201.09:02:34.18#ibcon#about to read 3, iclass 17, count 0 2006.201.09:02:34.20#ibcon#read 3, iclass 17, count 0 2006.201.09:02:34.20#ibcon#about to read 4, iclass 17, count 0 2006.201.09:02:34.20#ibcon#read 4, iclass 17, count 0 2006.201.09:02:34.20#ibcon#about to read 5, iclass 17, count 0 2006.201.09:02:34.20#ibcon#read 5, iclass 17, count 0 2006.201.09:02:34.20#ibcon#about to read 6, iclass 17, count 0 2006.201.09:02:34.20#ibcon#read 6, iclass 17, count 0 2006.201.09:02:34.20#ibcon#end of sib2, iclass 17, count 0 2006.201.09:02:34.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:02:34.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:02:34.20#ibcon#[27=USB\r\n] 2006.201.09:02:34.20#ibcon#*before write, iclass 17, count 0 2006.201.09:02:34.20#ibcon#enter sib2, iclass 17, count 0 2006.201.09:02:34.20#ibcon#flushed, iclass 17, count 0 2006.201.09:02:34.20#ibcon#about to write, iclass 17, count 0 2006.201.09:02:34.20#ibcon#wrote, iclass 17, count 0 2006.201.09:02:34.20#ibcon#about to read 3, iclass 17, count 0 2006.201.09:02:34.23#ibcon#read 3, iclass 17, count 0 2006.201.09:02:34.23#ibcon#about to read 4, iclass 17, count 0 2006.201.09:02:34.23#ibcon#read 4, iclass 17, count 0 2006.201.09:02:34.23#ibcon#about to read 5, iclass 17, count 0 2006.201.09:02:34.23#ibcon#read 5, iclass 17, count 0 2006.201.09:02:34.23#ibcon#about to read 6, iclass 17, count 0 2006.201.09:02:34.23#ibcon#read 6, iclass 17, count 0 2006.201.09:02:34.23#ibcon#end of sib2, iclass 17, count 0 2006.201.09:02:34.23#ibcon#*after write, iclass 17, count 0 2006.201.09:02:34.23#ibcon#*before return 0, iclass 17, count 0 2006.201.09:02:34.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:34.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:02:34.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:02:34.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:02:34.23$vck44/vblo=6,719.99 2006.201.09:02:34.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.09:02:34.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.09:02:34.23#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:34.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:34.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:34.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:34.23#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:02:34.23#ibcon#first serial, iclass 19, count 0 2006.201.09:02:34.23#ibcon#enter sib2, iclass 19, count 0 2006.201.09:02:34.23#ibcon#flushed, iclass 19, count 0 2006.201.09:02:34.23#ibcon#about to write, iclass 19, count 0 2006.201.09:02:34.23#ibcon#wrote, iclass 19, count 0 2006.201.09:02:34.23#ibcon#about to read 3, iclass 19, count 0 2006.201.09:02:34.25#ibcon#read 3, iclass 19, count 0 2006.201.09:02:34.25#ibcon#about to read 4, iclass 19, count 0 2006.201.09:02:34.25#ibcon#read 4, iclass 19, count 0 2006.201.09:02:34.25#ibcon#about to read 5, iclass 19, count 0 2006.201.09:02:34.25#ibcon#read 5, iclass 19, count 0 2006.201.09:02:34.25#ibcon#about to read 6, iclass 19, count 0 2006.201.09:02:34.25#ibcon#read 6, iclass 19, count 0 2006.201.09:02:34.25#ibcon#end of sib2, iclass 19, count 0 2006.201.09:02:34.25#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:02:34.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:02:34.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:02:34.25#ibcon#*before write, iclass 19, count 0 2006.201.09:02:34.25#ibcon#enter sib2, iclass 19, count 0 2006.201.09:02:34.25#ibcon#flushed, iclass 19, count 0 2006.201.09:02:34.25#ibcon#about to write, iclass 19, count 0 2006.201.09:02:34.25#ibcon#wrote, iclass 19, count 0 2006.201.09:02:34.25#ibcon#about to read 3, iclass 19, count 0 2006.201.09:02:34.29#ibcon#read 3, iclass 19, count 0 2006.201.09:02:34.29#ibcon#about to read 4, iclass 19, count 0 2006.201.09:02:34.29#ibcon#read 4, iclass 19, count 0 2006.201.09:02:34.29#ibcon#about to read 5, iclass 19, count 0 2006.201.09:02:34.29#ibcon#read 5, iclass 19, count 0 2006.201.09:02:34.29#ibcon#about to read 6, iclass 19, count 0 2006.201.09:02:34.29#ibcon#read 6, iclass 19, count 0 2006.201.09:02:34.29#ibcon#end of sib2, iclass 19, count 0 2006.201.09:02:34.29#ibcon#*after write, iclass 19, count 0 2006.201.09:02:34.29#ibcon#*before return 0, iclass 19, count 0 2006.201.09:02:34.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:34.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:02:34.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:02:34.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:02:34.29$vck44/vb=6,4 2006.201.09:02:34.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.09:02:34.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.09:02:34.29#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:34.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:34.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:34.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:34.35#ibcon#enter wrdev, iclass 21, count 2 2006.201.09:02:34.35#ibcon#first serial, iclass 21, count 2 2006.201.09:02:34.35#ibcon#enter sib2, iclass 21, count 2 2006.201.09:02:34.35#ibcon#flushed, iclass 21, count 2 2006.201.09:02:34.35#ibcon#about to write, iclass 21, count 2 2006.201.09:02:34.35#ibcon#wrote, iclass 21, count 2 2006.201.09:02:34.35#ibcon#about to read 3, iclass 21, count 2 2006.201.09:02:34.37#ibcon#read 3, iclass 21, count 2 2006.201.09:02:34.37#ibcon#about to read 4, iclass 21, count 2 2006.201.09:02:34.37#ibcon#read 4, iclass 21, count 2 2006.201.09:02:34.37#ibcon#about to read 5, iclass 21, count 2 2006.201.09:02:34.37#ibcon#read 5, iclass 21, count 2 2006.201.09:02:34.37#ibcon#about to read 6, iclass 21, count 2 2006.201.09:02:34.37#ibcon#read 6, iclass 21, count 2 2006.201.09:02:34.37#ibcon#end of sib2, iclass 21, count 2 2006.201.09:02:34.37#ibcon#*mode == 0, iclass 21, count 2 2006.201.09:02:34.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.09:02:34.37#ibcon#[27=AT06-04\r\n] 2006.201.09:02:34.37#ibcon#*before write, iclass 21, count 2 2006.201.09:02:34.37#ibcon#enter sib2, iclass 21, count 2 2006.201.09:02:34.37#ibcon#flushed, iclass 21, count 2 2006.201.09:02:34.37#ibcon#about to write, iclass 21, count 2 2006.201.09:02:34.37#ibcon#wrote, iclass 21, count 2 2006.201.09:02:34.37#ibcon#about to read 3, iclass 21, count 2 2006.201.09:02:34.40#ibcon#read 3, iclass 21, count 2 2006.201.09:02:34.40#ibcon#about to read 4, iclass 21, count 2 2006.201.09:02:34.40#ibcon#read 4, iclass 21, count 2 2006.201.09:02:34.40#ibcon#about to read 5, iclass 21, count 2 2006.201.09:02:34.40#ibcon#read 5, iclass 21, count 2 2006.201.09:02:34.40#ibcon#about to read 6, iclass 21, count 2 2006.201.09:02:34.40#ibcon#read 6, iclass 21, count 2 2006.201.09:02:34.40#ibcon#end of sib2, iclass 21, count 2 2006.201.09:02:34.40#ibcon#*after write, iclass 21, count 2 2006.201.09:02:34.40#ibcon#*before return 0, iclass 21, count 2 2006.201.09:02:34.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:34.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:02:34.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.09:02:34.40#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:34.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:34.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:34.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:34.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:02:34.52#ibcon#first serial, iclass 21, count 0 2006.201.09:02:34.52#ibcon#enter sib2, iclass 21, count 0 2006.201.09:02:34.52#ibcon#flushed, iclass 21, count 0 2006.201.09:02:34.52#ibcon#about to write, iclass 21, count 0 2006.201.09:02:34.52#ibcon#wrote, iclass 21, count 0 2006.201.09:02:34.52#ibcon#about to read 3, iclass 21, count 0 2006.201.09:02:34.54#ibcon#read 3, iclass 21, count 0 2006.201.09:02:34.54#ibcon#about to read 4, iclass 21, count 0 2006.201.09:02:34.54#ibcon#read 4, iclass 21, count 0 2006.201.09:02:34.54#ibcon#about to read 5, iclass 21, count 0 2006.201.09:02:34.54#ibcon#read 5, iclass 21, count 0 2006.201.09:02:34.54#ibcon#about to read 6, iclass 21, count 0 2006.201.09:02:34.54#ibcon#read 6, iclass 21, count 0 2006.201.09:02:34.54#ibcon#end of sib2, iclass 21, count 0 2006.201.09:02:34.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:02:34.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:02:34.54#ibcon#[27=USB\r\n] 2006.201.09:02:34.54#ibcon#*before write, iclass 21, count 0 2006.201.09:02:34.54#ibcon#enter sib2, iclass 21, count 0 2006.201.09:02:34.54#ibcon#flushed, iclass 21, count 0 2006.201.09:02:34.54#ibcon#about to write, iclass 21, count 0 2006.201.09:02:34.54#ibcon#wrote, iclass 21, count 0 2006.201.09:02:34.54#ibcon#about to read 3, iclass 21, count 0 2006.201.09:02:34.57#ibcon#read 3, iclass 21, count 0 2006.201.09:02:34.57#ibcon#about to read 4, iclass 21, count 0 2006.201.09:02:34.57#ibcon#read 4, iclass 21, count 0 2006.201.09:02:34.57#ibcon#about to read 5, iclass 21, count 0 2006.201.09:02:34.57#ibcon#read 5, iclass 21, count 0 2006.201.09:02:34.57#ibcon#about to read 6, iclass 21, count 0 2006.201.09:02:34.57#ibcon#read 6, iclass 21, count 0 2006.201.09:02:34.57#ibcon#end of sib2, iclass 21, count 0 2006.201.09:02:34.57#ibcon#*after write, iclass 21, count 0 2006.201.09:02:34.57#ibcon#*before return 0, iclass 21, count 0 2006.201.09:02:34.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:34.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:02:34.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:02:34.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:02:34.57$vck44/vblo=7,734.99 2006.201.09:02:34.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.09:02:34.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.09:02:34.57#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:34.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:34.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:34.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:34.57#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:02:34.57#ibcon#first serial, iclass 23, count 0 2006.201.09:02:34.57#ibcon#enter sib2, iclass 23, count 0 2006.201.09:02:34.57#ibcon#flushed, iclass 23, count 0 2006.201.09:02:34.57#ibcon#about to write, iclass 23, count 0 2006.201.09:02:34.57#ibcon#wrote, iclass 23, count 0 2006.201.09:02:34.57#ibcon#about to read 3, iclass 23, count 0 2006.201.09:02:34.59#ibcon#read 3, iclass 23, count 0 2006.201.09:02:34.59#ibcon#about to read 4, iclass 23, count 0 2006.201.09:02:34.59#ibcon#read 4, iclass 23, count 0 2006.201.09:02:34.59#ibcon#about to read 5, iclass 23, count 0 2006.201.09:02:34.59#ibcon#read 5, iclass 23, count 0 2006.201.09:02:34.59#ibcon#about to read 6, iclass 23, count 0 2006.201.09:02:34.59#ibcon#read 6, iclass 23, count 0 2006.201.09:02:34.59#ibcon#end of sib2, iclass 23, count 0 2006.201.09:02:34.59#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:02:34.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:02:34.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:02:34.59#ibcon#*before write, iclass 23, count 0 2006.201.09:02:34.59#ibcon#enter sib2, iclass 23, count 0 2006.201.09:02:34.59#ibcon#flushed, iclass 23, count 0 2006.201.09:02:34.59#ibcon#about to write, iclass 23, count 0 2006.201.09:02:34.59#ibcon#wrote, iclass 23, count 0 2006.201.09:02:34.59#ibcon#about to read 3, iclass 23, count 0 2006.201.09:02:34.63#ibcon#read 3, iclass 23, count 0 2006.201.09:02:34.63#ibcon#about to read 4, iclass 23, count 0 2006.201.09:02:34.63#ibcon#read 4, iclass 23, count 0 2006.201.09:02:34.63#ibcon#about to read 5, iclass 23, count 0 2006.201.09:02:34.63#ibcon#read 5, iclass 23, count 0 2006.201.09:02:34.63#ibcon#about to read 6, iclass 23, count 0 2006.201.09:02:34.63#ibcon#read 6, iclass 23, count 0 2006.201.09:02:34.63#ibcon#end of sib2, iclass 23, count 0 2006.201.09:02:34.63#ibcon#*after write, iclass 23, count 0 2006.201.09:02:34.63#ibcon#*before return 0, iclass 23, count 0 2006.201.09:02:34.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:34.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:02:34.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:02:34.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:02:34.63$vck44/vb=7,4 2006.201.09:02:34.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.09:02:34.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.09:02:34.63#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:34.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:34.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:34.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:34.69#ibcon#enter wrdev, iclass 25, count 2 2006.201.09:02:34.69#ibcon#first serial, iclass 25, count 2 2006.201.09:02:34.69#ibcon#enter sib2, iclass 25, count 2 2006.201.09:02:34.69#ibcon#flushed, iclass 25, count 2 2006.201.09:02:34.69#ibcon#about to write, iclass 25, count 2 2006.201.09:02:34.69#ibcon#wrote, iclass 25, count 2 2006.201.09:02:34.69#ibcon#about to read 3, iclass 25, count 2 2006.201.09:02:34.71#ibcon#read 3, iclass 25, count 2 2006.201.09:02:34.71#ibcon#about to read 4, iclass 25, count 2 2006.201.09:02:34.71#ibcon#read 4, iclass 25, count 2 2006.201.09:02:34.71#ibcon#about to read 5, iclass 25, count 2 2006.201.09:02:34.71#ibcon#read 5, iclass 25, count 2 2006.201.09:02:34.71#ibcon#about to read 6, iclass 25, count 2 2006.201.09:02:34.71#ibcon#read 6, iclass 25, count 2 2006.201.09:02:34.71#ibcon#end of sib2, iclass 25, count 2 2006.201.09:02:34.71#ibcon#*mode == 0, iclass 25, count 2 2006.201.09:02:34.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.09:02:34.71#ibcon#[27=AT07-04\r\n] 2006.201.09:02:34.71#ibcon#*before write, iclass 25, count 2 2006.201.09:02:34.71#ibcon#enter sib2, iclass 25, count 2 2006.201.09:02:34.71#ibcon#flushed, iclass 25, count 2 2006.201.09:02:34.71#ibcon#about to write, iclass 25, count 2 2006.201.09:02:34.71#ibcon#wrote, iclass 25, count 2 2006.201.09:02:34.71#ibcon#about to read 3, iclass 25, count 2 2006.201.09:02:34.74#ibcon#read 3, iclass 25, count 2 2006.201.09:02:34.74#ibcon#about to read 4, iclass 25, count 2 2006.201.09:02:34.74#ibcon#read 4, iclass 25, count 2 2006.201.09:02:34.74#ibcon#about to read 5, iclass 25, count 2 2006.201.09:02:34.74#ibcon#read 5, iclass 25, count 2 2006.201.09:02:34.74#ibcon#about to read 6, iclass 25, count 2 2006.201.09:02:34.74#ibcon#read 6, iclass 25, count 2 2006.201.09:02:34.74#ibcon#end of sib2, iclass 25, count 2 2006.201.09:02:34.74#ibcon#*after write, iclass 25, count 2 2006.201.09:02:34.74#ibcon#*before return 0, iclass 25, count 2 2006.201.09:02:34.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:34.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:02:34.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.09:02:34.74#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:34.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:34.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:34.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:34.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:02:34.86#ibcon#first serial, iclass 25, count 0 2006.201.09:02:34.86#ibcon#enter sib2, iclass 25, count 0 2006.201.09:02:34.86#ibcon#flushed, iclass 25, count 0 2006.201.09:02:34.86#ibcon#about to write, iclass 25, count 0 2006.201.09:02:34.86#ibcon#wrote, iclass 25, count 0 2006.201.09:02:34.86#ibcon#about to read 3, iclass 25, count 0 2006.201.09:02:34.88#ibcon#read 3, iclass 25, count 0 2006.201.09:02:34.88#ibcon#about to read 4, iclass 25, count 0 2006.201.09:02:34.88#ibcon#read 4, iclass 25, count 0 2006.201.09:02:34.88#ibcon#about to read 5, iclass 25, count 0 2006.201.09:02:34.88#ibcon#read 5, iclass 25, count 0 2006.201.09:02:34.88#ibcon#about to read 6, iclass 25, count 0 2006.201.09:02:34.88#ibcon#read 6, iclass 25, count 0 2006.201.09:02:34.88#ibcon#end of sib2, iclass 25, count 0 2006.201.09:02:34.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:02:34.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:02:34.88#ibcon#[27=USB\r\n] 2006.201.09:02:34.88#ibcon#*before write, iclass 25, count 0 2006.201.09:02:34.88#ibcon#enter sib2, iclass 25, count 0 2006.201.09:02:34.88#ibcon#flushed, iclass 25, count 0 2006.201.09:02:34.88#ibcon#about to write, iclass 25, count 0 2006.201.09:02:34.88#ibcon#wrote, iclass 25, count 0 2006.201.09:02:34.88#ibcon#about to read 3, iclass 25, count 0 2006.201.09:02:34.91#ibcon#read 3, iclass 25, count 0 2006.201.09:02:34.91#ibcon#about to read 4, iclass 25, count 0 2006.201.09:02:34.91#ibcon#read 4, iclass 25, count 0 2006.201.09:02:34.91#ibcon#about to read 5, iclass 25, count 0 2006.201.09:02:34.91#ibcon#read 5, iclass 25, count 0 2006.201.09:02:34.91#ibcon#about to read 6, iclass 25, count 0 2006.201.09:02:34.91#ibcon#read 6, iclass 25, count 0 2006.201.09:02:34.91#ibcon#end of sib2, iclass 25, count 0 2006.201.09:02:34.91#ibcon#*after write, iclass 25, count 0 2006.201.09:02:34.91#ibcon#*before return 0, iclass 25, count 0 2006.201.09:02:34.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:34.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:02:34.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:02:34.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:02:34.91$vck44/vblo=8,744.99 2006.201.09:02:34.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.09:02:34.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.09:02:34.91#ibcon#ireg 17 cls_cnt 0 2006.201.09:02:34.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:34.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:34.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:34.91#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:02:34.91#ibcon#first serial, iclass 27, count 0 2006.201.09:02:34.91#ibcon#enter sib2, iclass 27, count 0 2006.201.09:02:34.91#ibcon#flushed, iclass 27, count 0 2006.201.09:02:34.91#ibcon#about to write, iclass 27, count 0 2006.201.09:02:34.91#ibcon#wrote, iclass 27, count 0 2006.201.09:02:34.91#ibcon#about to read 3, iclass 27, count 0 2006.201.09:02:34.93#ibcon#read 3, iclass 27, count 0 2006.201.09:02:34.93#ibcon#about to read 4, iclass 27, count 0 2006.201.09:02:34.93#ibcon#read 4, iclass 27, count 0 2006.201.09:02:34.93#ibcon#about to read 5, iclass 27, count 0 2006.201.09:02:34.93#ibcon#read 5, iclass 27, count 0 2006.201.09:02:34.93#ibcon#about to read 6, iclass 27, count 0 2006.201.09:02:34.93#ibcon#read 6, iclass 27, count 0 2006.201.09:02:34.93#ibcon#end of sib2, iclass 27, count 0 2006.201.09:02:34.93#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:02:34.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:02:34.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:02:34.93#ibcon#*before write, iclass 27, count 0 2006.201.09:02:34.93#ibcon#enter sib2, iclass 27, count 0 2006.201.09:02:34.93#ibcon#flushed, iclass 27, count 0 2006.201.09:02:34.93#ibcon#about to write, iclass 27, count 0 2006.201.09:02:34.93#ibcon#wrote, iclass 27, count 0 2006.201.09:02:34.93#ibcon#about to read 3, iclass 27, count 0 2006.201.09:02:34.98#ibcon#read 3, iclass 27, count 0 2006.201.09:02:34.98#ibcon#about to read 4, iclass 27, count 0 2006.201.09:02:34.98#ibcon#read 4, iclass 27, count 0 2006.201.09:02:34.98#ibcon#about to read 5, iclass 27, count 0 2006.201.09:02:34.98#ibcon#read 5, iclass 27, count 0 2006.201.09:02:34.98#ibcon#about to read 6, iclass 27, count 0 2006.201.09:02:34.98#ibcon#read 6, iclass 27, count 0 2006.201.09:02:34.98#ibcon#end of sib2, iclass 27, count 0 2006.201.09:02:34.98#ibcon#*after write, iclass 27, count 0 2006.201.09:02:34.98#ibcon#*before return 0, iclass 27, count 0 2006.201.09:02:34.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:34.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:02:34.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:02:34.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:02:34.98$vck44/vb=8,4 2006.201.09:02:34.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.09:02:34.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.09:02:34.98#ibcon#ireg 11 cls_cnt 2 2006.201.09:02:34.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:35.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:35.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:35.03#ibcon#enter wrdev, iclass 29, count 2 2006.201.09:02:35.03#ibcon#first serial, iclass 29, count 2 2006.201.09:02:35.03#ibcon#enter sib2, iclass 29, count 2 2006.201.09:02:35.03#ibcon#flushed, iclass 29, count 2 2006.201.09:02:35.03#ibcon#about to write, iclass 29, count 2 2006.201.09:02:35.03#ibcon#wrote, iclass 29, count 2 2006.201.09:02:35.03#ibcon#about to read 3, iclass 29, count 2 2006.201.09:02:35.05#ibcon#read 3, iclass 29, count 2 2006.201.09:02:35.05#ibcon#about to read 4, iclass 29, count 2 2006.201.09:02:35.05#ibcon#read 4, iclass 29, count 2 2006.201.09:02:35.05#ibcon#about to read 5, iclass 29, count 2 2006.201.09:02:35.05#ibcon#read 5, iclass 29, count 2 2006.201.09:02:35.05#ibcon#about to read 6, iclass 29, count 2 2006.201.09:02:35.05#ibcon#read 6, iclass 29, count 2 2006.201.09:02:35.05#ibcon#end of sib2, iclass 29, count 2 2006.201.09:02:35.05#ibcon#*mode == 0, iclass 29, count 2 2006.201.09:02:35.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.09:02:35.05#ibcon#[27=AT08-04\r\n] 2006.201.09:02:35.05#ibcon#*before write, iclass 29, count 2 2006.201.09:02:35.05#ibcon#enter sib2, iclass 29, count 2 2006.201.09:02:35.05#ibcon#flushed, iclass 29, count 2 2006.201.09:02:35.05#ibcon#about to write, iclass 29, count 2 2006.201.09:02:35.05#ibcon#wrote, iclass 29, count 2 2006.201.09:02:35.05#ibcon#about to read 3, iclass 29, count 2 2006.201.09:02:35.08#ibcon#read 3, iclass 29, count 2 2006.201.09:02:35.08#ibcon#about to read 4, iclass 29, count 2 2006.201.09:02:35.08#ibcon#read 4, iclass 29, count 2 2006.201.09:02:35.08#ibcon#about to read 5, iclass 29, count 2 2006.201.09:02:35.08#ibcon#read 5, iclass 29, count 2 2006.201.09:02:35.08#ibcon#about to read 6, iclass 29, count 2 2006.201.09:02:35.08#ibcon#read 6, iclass 29, count 2 2006.201.09:02:35.08#ibcon#end of sib2, iclass 29, count 2 2006.201.09:02:35.08#ibcon#*after write, iclass 29, count 2 2006.201.09:02:35.08#ibcon#*before return 0, iclass 29, count 2 2006.201.09:02:35.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:35.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:02:35.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.09:02:35.08#ibcon#ireg 7 cls_cnt 0 2006.201.09:02:35.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:35.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:35.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:35.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:02:35.20#ibcon#first serial, iclass 29, count 0 2006.201.09:02:35.20#ibcon#enter sib2, iclass 29, count 0 2006.201.09:02:35.20#ibcon#flushed, iclass 29, count 0 2006.201.09:02:35.20#ibcon#about to write, iclass 29, count 0 2006.201.09:02:35.20#ibcon#wrote, iclass 29, count 0 2006.201.09:02:35.20#ibcon#about to read 3, iclass 29, count 0 2006.201.09:02:35.22#ibcon#read 3, iclass 29, count 0 2006.201.09:02:35.22#ibcon#about to read 4, iclass 29, count 0 2006.201.09:02:35.22#ibcon#read 4, iclass 29, count 0 2006.201.09:02:35.22#ibcon#about to read 5, iclass 29, count 0 2006.201.09:02:35.22#ibcon#read 5, iclass 29, count 0 2006.201.09:02:35.22#ibcon#about to read 6, iclass 29, count 0 2006.201.09:02:35.22#ibcon#read 6, iclass 29, count 0 2006.201.09:02:35.22#ibcon#end of sib2, iclass 29, count 0 2006.201.09:02:35.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:02:35.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:02:35.22#ibcon#[27=USB\r\n] 2006.201.09:02:35.22#ibcon#*before write, iclass 29, count 0 2006.201.09:02:35.22#ibcon#enter sib2, iclass 29, count 0 2006.201.09:02:35.22#ibcon#flushed, iclass 29, count 0 2006.201.09:02:35.22#ibcon#about to write, iclass 29, count 0 2006.201.09:02:35.22#ibcon#wrote, iclass 29, count 0 2006.201.09:02:35.22#ibcon#about to read 3, iclass 29, count 0 2006.201.09:02:35.25#ibcon#read 3, iclass 29, count 0 2006.201.09:02:35.25#ibcon#about to read 4, iclass 29, count 0 2006.201.09:02:35.25#ibcon#read 4, iclass 29, count 0 2006.201.09:02:35.25#ibcon#about to read 5, iclass 29, count 0 2006.201.09:02:35.25#ibcon#read 5, iclass 29, count 0 2006.201.09:02:35.25#ibcon#about to read 6, iclass 29, count 0 2006.201.09:02:35.25#ibcon#read 6, iclass 29, count 0 2006.201.09:02:35.25#ibcon#end of sib2, iclass 29, count 0 2006.201.09:02:35.25#ibcon#*after write, iclass 29, count 0 2006.201.09:02:35.25#ibcon#*before return 0, iclass 29, count 0 2006.201.09:02:35.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:35.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:02:35.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:02:35.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:02:35.25$vck44/vabw=wide 2006.201.09:02:35.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.09:02:35.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.09:02:35.25#ibcon#ireg 8 cls_cnt 0 2006.201.09:02:35.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:35.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:35.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:35.25#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:02:35.25#ibcon#first serial, iclass 31, count 0 2006.201.09:02:35.25#ibcon#enter sib2, iclass 31, count 0 2006.201.09:02:35.25#ibcon#flushed, iclass 31, count 0 2006.201.09:02:35.25#ibcon#about to write, iclass 31, count 0 2006.201.09:02:35.25#ibcon#wrote, iclass 31, count 0 2006.201.09:02:35.25#ibcon#about to read 3, iclass 31, count 0 2006.201.09:02:35.27#ibcon#read 3, iclass 31, count 0 2006.201.09:02:35.27#ibcon#about to read 4, iclass 31, count 0 2006.201.09:02:35.27#ibcon#read 4, iclass 31, count 0 2006.201.09:02:35.27#ibcon#about to read 5, iclass 31, count 0 2006.201.09:02:35.27#ibcon#read 5, iclass 31, count 0 2006.201.09:02:35.27#ibcon#about to read 6, iclass 31, count 0 2006.201.09:02:35.27#ibcon#read 6, iclass 31, count 0 2006.201.09:02:35.27#ibcon#end of sib2, iclass 31, count 0 2006.201.09:02:35.27#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:02:35.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:02:35.27#ibcon#[25=BW32\r\n] 2006.201.09:02:35.27#ibcon#*before write, iclass 31, count 0 2006.201.09:02:35.27#ibcon#enter sib2, iclass 31, count 0 2006.201.09:02:35.27#ibcon#flushed, iclass 31, count 0 2006.201.09:02:35.27#ibcon#about to write, iclass 31, count 0 2006.201.09:02:35.27#ibcon#wrote, iclass 31, count 0 2006.201.09:02:35.27#ibcon#about to read 3, iclass 31, count 0 2006.201.09:02:35.30#ibcon#read 3, iclass 31, count 0 2006.201.09:02:35.30#ibcon#about to read 4, iclass 31, count 0 2006.201.09:02:35.30#ibcon#read 4, iclass 31, count 0 2006.201.09:02:35.30#ibcon#about to read 5, iclass 31, count 0 2006.201.09:02:35.30#ibcon#read 5, iclass 31, count 0 2006.201.09:02:35.30#ibcon#about to read 6, iclass 31, count 0 2006.201.09:02:35.30#ibcon#read 6, iclass 31, count 0 2006.201.09:02:35.30#ibcon#end of sib2, iclass 31, count 0 2006.201.09:02:35.30#ibcon#*after write, iclass 31, count 0 2006.201.09:02:35.30#ibcon#*before return 0, iclass 31, count 0 2006.201.09:02:35.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:35.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:02:35.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:02:35.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:02:35.30$vck44/vbbw=wide 2006.201.09:02:35.30#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.09:02:35.30#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.09:02:35.30#ibcon#ireg 8 cls_cnt 0 2006.201.09:02:35.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:02:35.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:02:35.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:02:35.37#ibcon#enter wrdev, iclass 33, count 0 2006.201.09:02:35.37#ibcon#first serial, iclass 33, count 0 2006.201.09:02:35.37#ibcon#enter sib2, iclass 33, count 0 2006.201.09:02:35.37#ibcon#flushed, iclass 33, count 0 2006.201.09:02:35.37#ibcon#about to write, iclass 33, count 0 2006.201.09:02:35.37#ibcon#wrote, iclass 33, count 0 2006.201.09:02:35.37#ibcon#about to read 3, iclass 33, count 0 2006.201.09:02:35.39#ibcon#read 3, iclass 33, count 0 2006.201.09:02:35.39#ibcon#about to read 4, iclass 33, count 0 2006.201.09:02:35.39#ibcon#read 4, iclass 33, count 0 2006.201.09:02:35.39#ibcon#about to read 5, iclass 33, count 0 2006.201.09:02:35.39#ibcon#read 5, iclass 33, count 0 2006.201.09:02:35.39#ibcon#about to read 6, iclass 33, count 0 2006.201.09:02:35.39#ibcon#read 6, iclass 33, count 0 2006.201.09:02:35.39#ibcon#end of sib2, iclass 33, count 0 2006.201.09:02:35.39#ibcon#*mode == 0, iclass 33, count 0 2006.201.09:02:35.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.09:02:35.39#ibcon#[27=BW32\r\n] 2006.201.09:02:35.39#ibcon#*before write, iclass 33, count 0 2006.201.09:02:35.39#ibcon#enter sib2, iclass 33, count 0 2006.201.09:02:35.39#ibcon#flushed, iclass 33, count 0 2006.201.09:02:35.39#ibcon#about to write, iclass 33, count 0 2006.201.09:02:35.39#ibcon#wrote, iclass 33, count 0 2006.201.09:02:35.39#ibcon#about to read 3, iclass 33, count 0 2006.201.09:02:35.42#ibcon#read 3, iclass 33, count 0 2006.201.09:02:35.42#ibcon#about to read 4, iclass 33, count 0 2006.201.09:02:35.42#ibcon#read 4, iclass 33, count 0 2006.201.09:02:35.42#ibcon#about to read 5, iclass 33, count 0 2006.201.09:02:35.42#ibcon#read 5, iclass 33, count 0 2006.201.09:02:35.42#ibcon#about to read 6, iclass 33, count 0 2006.201.09:02:35.42#ibcon#read 6, iclass 33, count 0 2006.201.09:02:35.42#ibcon#end of sib2, iclass 33, count 0 2006.201.09:02:35.42#ibcon#*after write, iclass 33, count 0 2006.201.09:02:35.42#ibcon#*before return 0, iclass 33, count 0 2006.201.09:02:35.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:02:35.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:02:35.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.09:02:35.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.09:02:35.42$setupk4/ifdk4 2006.201.09:02:35.42$ifdk4/lo= 2006.201.09:02:35.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:02:35.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:02:35.42$ifdk4/patch= 2006.201.09:02:35.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:02:35.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:02:35.42$setupk4/!*+20s 2006.201.09:02:36.57#abcon#<5=/05 2.4 4.1 22.91 901003.7\r\n> 2006.201.09:02:36.59#abcon#{5=INTERFACE CLEAR} 2006.201.09:02:36.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:02:46.74#abcon#<5=/05 2.4 4.1 22.91 901003.7\r\n> 2006.201.09:02:46.76#abcon#{5=INTERFACE CLEAR} 2006.201.09:02:46.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:02:49.88$setupk4/"tpicd 2006.201.09:02:49.88$setupk4/echo=off 2006.201.09:02:49.88$setupk4/xlog=off 2006.201.09:02:49.88:!2006.201.09:12:28 2006.201.09:03:09.14#trakl#Source acquired 2006.201.09:03:10.14#flagr#flagr/antenna,acquired 2006.201.09:12:28.00:preob 2006.201.09:12:29.14/onsource/TRACKING 2006.201.09:12:29.14:!2006.201.09:12:38 2006.201.09:12:38.00:"tape 2006.201.09:12:38.00:"st=record 2006.201.09:12:38.00:data_valid=on 2006.201.09:12:38.00:midob 2006.201.09:12:38.14/onsource/TRACKING 2006.201.09:12:38.14/wx/22.85,1003.7,90 2006.201.09:12:38.21/cable/+6.4660E-03 2006.201.09:12:39.30/va/01,08,usb,yes,29,31 2006.201.09:12:39.30/va/02,07,usb,yes,31,32 2006.201.09:12:39.30/va/03,08,usb,yes,28,29 2006.201.09:12:39.30/va/04,07,usb,yes,32,34 2006.201.09:12:39.30/va/05,04,usb,yes,28,29 2006.201.09:12:39.30/va/06,05,usb,yes,28,28 2006.201.09:12:39.30/va/07,05,usb,yes,28,29 2006.201.09:12:39.30/va/08,04,usb,yes,27,33 2006.201.09:12:39.53/valo/01,524.99,yes,locked 2006.201.09:12:39.53/valo/02,534.99,yes,locked 2006.201.09:12:39.53/valo/03,564.99,yes,locked 2006.201.09:12:39.53/valo/04,624.99,yes,locked 2006.201.09:12:39.53/valo/05,734.99,yes,locked 2006.201.09:12:39.53/valo/06,814.99,yes,locked 2006.201.09:12:39.53/valo/07,864.99,yes,locked 2006.201.09:12:39.53/valo/08,884.99,yes,locked 2006.201.09:12:40.62/vb/01,04,usb,yes,29,27 2006.201.09:12:40.62/vb/02,05,usb,yes,27,27 2006.201.09:12:40.62/vb/03,04,usb,yes,28,31 2006.201.09:12:40.62/vb/04,05,usb,yes,29,28 2006.201.09:12:40.62/vb/05,04,usb,yes,25,28 2006.201.09:12:40.62/vb/06,04,usb,yes,30,26 2006.201.09:12:40.62/vb/07,04,usb,yes,29,29 2006.201.09:12:40.62/vb/08,04,usb,yes,27,30 2006.201.09:12:40.85/vblo/01,629.99,yes,locked 2006.201.09:12:40.85/vblo/02,634.99,yes,locked 2006.201.09:12:40.85/vblo/03,649.99,yes,locked 2006.201.09:12:40.85/vblo/04,679.99,yes,locked 2006.201.09:12:40.85/vblo/05,709.99,yes,locked 2006.201.09:12:40.85/vblo/06,719.99,yes,locked 2006.201.09:12:40.85/vblo/07,734.99,yes,locked 2006.201.09:12:40.85/vblo/08,744.99,yes,locked 2006.201.09:12:41.00/vabw/8 2006.201.09:12:41.15/vbbw/8 2006.201.09:12:41.24/xfe/off,on,15.2 2006.201.09:12:41.61/ifatt/23,28,28,28 2006.201.09:12:42.04/fmout-gps/S +4.56E-07 2006.201.09:12:42.09:!2006.201.09:13:18 2006.201.09:13:18.00:data_valid=off 2006.201.09:13:18.00:"et 2006.201.09:13:18.00:!+3s 2006.201.09:13:21.02:"tape 2006.201.09:13:21.02:postob 2006.201.09:13:21.11/cable/+6.4656E-03 2006.201.09:13:21.11/wx/22.84,1003.8,90 2006.201.09:13:21.18/fmout-gps/S +4.55E-07 2006.201.09:13:21.18:scan_name=201-0914,jd0607,40 2006.201.09:13:21.18:source=3c345,164258.81,394837.0,2000.0,cw 2006.201.09:13:23.14#flagr#flagr/antenna,new-source 2006.201.09:13:23.14:checkk5 2006.201.09:13:23.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:13:23.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:13:24.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:13:24.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:13:25.01/chk_obsdata//k5ts1/T2010912??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:13:25.38/chk_obsdata//k5ts2/T2010912??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:13:25.74/chk_obsdata//k5ts3/T2010912??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:13:26.12/chk_obsdata//k5ts4/T2010912??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:13:26.81/k5log//k5ts1_log_newline 2006.201.09:13:27.50/k5log//k5ts2_log_newline 2006.201.09:13:28.18/k5log//k5ts3_log_newline 2006.201.09:13:28.87/k5log//k5ts4_log_newline 2006.201.09:13:28.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:13:28.90:setupk4=1 2006.201.09:13:28.90$setupk4/echo=on 2006.201.09:13:28.90$setupk4/pcalon 2006.201.09:13:28.90$pcalon/"no phase cal control is implemented here 2006.201.09:13:28.90$setupk4/"tpicd=stop 2006.201.09:13:28.90$setupk4/"rec=synch_on 2006.201.09:13:28.90$setupk4/"rec_mode=128 2006.201.09:13:28.90$setupk4/!* 2006.201.09:13:28.90$setupk4/recpk4 2006.201.09:13:28.90$recpk4/recpatch= 2006.201.09:13:28.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:13:28.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:13:28.90$setupk4/vck44 2006.201.09:13:28.90$vck44/valo=1,524.99 2006.201.09:13:28.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.09:13:28.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.09:13:28.90#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:28.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:28.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:28.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:28.90#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:13:28.90#ibcon#first serial, iclass 10, count 0 2006.201.09:13:28.90#ibcon#enter sib2, iclass 10, count 0 2006.201.09:13:28.90#ibcon#flushed, iclass 10, count 0 2006.201.09:13:28.90#ibcon#about to write, iclass 10, count 0 2006.201.09:13:28.90#ibcon#wrote, iclass 10, count 0 2006.201.09:13:28.90#ibcon#about to read 3, iclass 10, count 0 2006.201.09:13:28.94#ibcon#read 3, iclass 10, count 0 2006.201.09:13:28.94#ibcon#about to read 4, iclass 10, count 0 2006.201.09:13:28.94#ibcon#read 4, iclass 10, count 0 2006.201.09:13:28.94#ibcon#about to read 5, iclass 10, count 0 2006.201.09:13:28.94#ibcon#read 5, iclass 10, count 0 2006.201.09:13:28.94#ibcon#about to read 6, iclass 10, count 0 2006.201.09:13:28.94#ibcon#read 6, iclass 10, count 0 2006.201.09:13:28.94#ibcon#end of sib2, iclass 10, count 0 2006.201.09:13:28.94#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:13:28.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:13:28.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:13:28.94#ibcon#*before write, iclass 10, count 0 2006.201.09:13:28.94#ibcon#enter sib2, iclass 10, count 0 2006.201.09:13:28.94#ibcon#flushed, iclass 10, count 0 2006.201.09:13:28.94#ibcon#about to write, iclass 10, count 0 2006.201.09:13:28.94#ibcon#wrote, iclass 10, count 0 2006.201.09:13:28.94#ibcon#about to read 3, iclass 10, count 0 2006.201.09:13:28.99#ibcon#read 3, iclass 10, count 0 2006.201.09:13:28.99#ibcon#about to read 4, iclass 10, count 0 2006.201.09:13:28.99#ibcon#read 4, iclass 10, count 0 2006.201.09:13:28.99#ibcon#about to read 5, iclass 10, count 0 2006.201.09:13:28.99#ibcon#read 5, iclass 10, count 0 2006.201.09:13:28.99#ibcon#about to read 6, iclass 10, count 0 2006.201.09:13:28.99#ibcon#read 6, iclass 10, count 0 2006.201.09:13:28.99#ibcon#end of sib2, iclass 10, count 0 2006.201.09:13:28.99#ibcon#*after write, iclass 10, count 0 2006.201.09:13:28.99#ibcon#*before return 0, iclass 10, count 0 2006.201.09:13:28.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:28.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:28.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:13:28.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:13:28.99$vck44/va=1,8 2006.201.09:13:28.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.09:13:28.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.09:13:28.99#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:28.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:28.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:28.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:28.99#ibcon#enter wrdev, iclass 12, count 2 2006.201.09:13:28.99#ibcon#first serial, iclass 12, count 2 2006.201.09:13:28.99#ibcon#enter sib2, iclass 12, count 2 2006.201.09:13:28.99#ibcon#flushed, iclass 12, count 2 2006.201.09:13:28.99#ibcon#about to write, iclass 12, count 2 2006.201.09:13:28.99#ibcon#wrote, iclass 12, count 2 2006.201.09:13:28.99#ibcon#about to read 3, iclass 12, count 2 2006.201.09:13:29.01#ibcon#read 3, iclass 12, count 2 2006.201.09:13:29.01#ibcon#about to read 4, iclass 12, count 2 2006.201.09:13:29.01#ibcon#read 4, iclass 12, count 2 2006.201.09:13:29.01#ibcon#about to read 5, iclass 12, count 2 2006.201.09:13:29.01#ibcon#read 5, iclass 12, count 2 2006.201.09:13:29.01#ibcon#about to read 6, iclass 12, count 2 2006.201.09:13:29.01#ibcon#read 6, iclass 12, count 2 2006.201.09:13:29.01#ibcon#end of sib2, iclass 12, count 2 2006.201.09:13:29.01#ibcon#*mode == 0, iclass 12, count 2 2006.201.09:13:29.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.09:13:29.01#ibcon#[25=AT01-08\r\n] 2006.201.09:13:29.01#ibcon#*before write, iclass 12, count 2 2006.201.09:13:29.01#ibcon#enter sib2, iclass 12, count 2 2006.201.09:13:29.01#ibcon#flushed, iclass 12, count 2 2006.201.09:13:29.01#ibcon#about to write, iclass 12, count 2 2006.201.09:13:29.01#ibcon#wrote, iclass 12, count 2 2006.201.09:13:29.01#ibcon#about to read 3, iclass 12, count 2 2006.201.09:13:29.05#ibcon#read 3, iclass 12, count 2 2006.201.09:13:29.05#ibcon#about to read 4, iclass 12, count 2 2006.201.09:13:29.05#ibcon#read 4, iclass 12, count 2 2006.201.09:13:29.05#ibcon#about to read 5, iclass 12, count 2 2006.201.09:13:29.05#ibcon#read 5, iclass 12, count 2 2006.201.09:13:29.05#ibcon#about to read 6, iclass 12, count 2 2006.201.09:13:29.05#ibcon#read 6, iclass 12, count 2 2006.201.09:13:29.05#ibcon#end of sib2, iclass 12, count 2 2006.201.09:13:29.05#ibcon#*after write, iclass 12, count 2 2006.201.09:13:29.05#ibcon#*before return 0, iclass 12, count 2 2006.201.09:13:29.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:29.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:29.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.09:13:29.05#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:29.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:29.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:29.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:29.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:13:29.17#ibcon#first serial, iclass 12, count 0 2006.201.09:13:29.17#ibcon#enter sib2, iclass 12, count 0 2006.201.09:13:29.17#ibcon#flushed, iclass 12, count 0 2006.201.09:13:29.17#ibcon#about to write, iclass 12, count 0 2006.201.09:13:29.17#ibcon#wrote, iclass 12, count 0 2006.201.09:13:29.17#ibcon#about to read 3, iclass 12, count 0 2006.201.09:13:29.19#ibcon#read 3, iclass 12, count 0 2006.201.09:13:29.19#ibcon#about to read 4, iclass 12, count 0 2006.201.09:13:29.19#ibcon#read 4, iclass 12, count 0 2006.201.09:13:29.19#ibcon#about to read 5, iclass 12, count 0 2006.201.09:13:29.19#ibcon#read 5, iclass 12, count 0 2006.201.09:13:29.19#ibcon#about to read 6, iclass 12, count 0 2006.201.09:13:29.19#ibcon#read 6, iclass 12, count 0 2006.201.09:13:29.19#ibcon#end of sib2, iclass 12, count 0 2006.201.09:13:29.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:13:29.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:13:29.19#ibcon#[25=USB\r\n] 2006.201.09:13:29.19#ibcon#*before write, iclass 12, count 0 2006.201.09:13:29.19#ibcon#enter sib2, iclass 12, count 0 2006.201.09:13:29.19#ibcon#flushed, iclass 12, count 0 2006.201.09:13:29.19#ibcon#about to write, iclass 12, count 0 2006.201.09:13:29.19#ibcon#wrote, iclass 12, count 0 2006.201.09:13:29.19#ibcon#about to read 3, iclass 12, count 0 2006.201.09:13:29.22#ibcon#read 3, iclass 12, count 0 2006.201.09:13:29.22#ibcon#about to read 4, iclass 12, count 0 2006.201.09:13:29.22#ibcon#read 4, iclass 12, count 0 2006.201.09:13:29.22#ibcon#about to read 5, iclass 12, count 0 2006.201.09:13:29.22#ibcon#read 5, iclass 12, count 0 2006.201.09:13:29.22#ibcon#about to read 6, iclass 12, count 0 2006.201.09:13:29.22#ibcon#read 6, iclass 12, count 0 2006.201.09:13:29.22#ibcon#end of sib2, iclass 12, count 0 2006.201.09:13:29.22#ibcon#*after write, iclass 12, count 0 2006.201.09:13:29.22#ibcon#*before return 0, iclass 12, count 0 2006.201.09:13:29.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:29.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:29.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:13:29.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:13:29.22$vck44/valo=2,534.99 2006.201.09:13:29.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.09:13:29.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.09:13:29.22#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:29.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:29.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:29.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:29.22#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:13:29.22#ibcon#first serial, iclass 14, count 0 2006.201.09:13:29.22#ibcon#enter sib2, iclass 14, count 0 2006.201.09:13:29.22#ibcon#flushed, iclass 14, count 0 2006.201.09:13:29.22#ibcon#about to write, iclass 14, count 0 2006.201.09:13:29.22#ibcon#wrote, iclass 14, count 0 2006.201.09:13:29.22#ibcon#about to read 3, iclass 14, count 0 2006.201.09:13:29.24#ibcon#read 3, iclass 14, count 0 2006.201.09:13:29.24#ibcon#about to read 4, iclass 14, count 0 2006.201.09:13:29.24#ibcon#read 4, iclass 14, count 0 2006.201.09:13:29.24#ibcon#about to read 5, iclass 14, count 0 2006.201.09:13:29.24#ibcon#read 5, iclass 14, count 0 2006.201.09:13:29.24#ibcon#about to read 6, iclass 14, count 0 2006.201.09:13:29.24#ibcon#read 6, iclass 14, count 0 2006.201.09:13:29.24#ibcon#end of sib2, iclass 14, count 0 2006.201.09:13:29.24#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:13:29.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:13:29.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:13:29.24#ibcon#*before write, iclass 14, count 0 2006.201.09:13:29.24#ibcon#enter sib2, iclass 14, count 0 2006.201.09:13:29.24#ibcon#flushed, iclass 14, count 0 2006.201.09:13:29.24#ibcon#about to write, iclass 14, count 0 2006.201.09:13:29.24#ibcon#wrote, iclass 14, count 0 2006.201.09:13:29.24#ibcon#about to read 3, iclass 14, count 0 2006.201.09:13:29.28#ibcon#read 3, iclass 14, count 0 2006.201.09:13:29.28#ibcon#about to read 4, iclass 14, count 0 2006.201.09:13:29.28#ibcon#read 4, iclass 14, count 0 2006.201.09:13:29.28#ibcon#about to read 5, iclass 14, count 0 2006.201.09:13:29.28#ibcon#read 5, iclass 14, count 0 2006.201.09:13:29.28#ibcon#about to read 6, iclass 14, count 0 2006.201.09:13:29.28#ibcon#read 6, iclass 14, count 0 2006.201.09:13:29.28#ibcon#end of sib2, iclass 14, count 0 2006.201.09:13:29.28#ibcon#*after write, iclass 14, count 0 2006.201.09:13:29.28#ibcon#*before return 0, iclass 14, count 0 2006.201.09:13:29.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:29.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:29.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:13:29.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:13:29.28$vck44/va=2,7 2006.201.09:13:29.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.09:13:29.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.09:13:29.28#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:29.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:29.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:29.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:29.34#ibcon#enter wrdev, iclass 16, count 2 2006.201.09:13:29.34#ibcon#first serial, iclass 16, count 2 2006.201.09:13:29.34#ibcon#enter sib2, iclass 16, count 2 2006.201.09:13:29.34#ibcon#flushed, iclass 16, count 2 2006.201.09:13:29.34#ibcon#about to write, iclass 16, count 2 2006.201.09:13:29.34#ibcon#wrote, iclass 16, count 2 2006.201.09:13:29.34#ibcon#about to read 3, iclass 16, count 2 2006.201.09:13:29.36#ibcon#read 3, iclass 16, count 2 2006.201.09:13:29.36#ibcon#about to read 4, iclass 16, count 2 2006.201.09:13:29.36#ibcon#read 4, iclass 16, count 2 2006.201.09:13:29.36#ibcon#about to read 5, iclass 16, count 2 2006.201.09:13:29.36#ibcon#read 5, iclass 16, count 2 2006.201.09:13:29.36#ibcon#about to read 6, iclass 16, count 2 2006.201.09:13:29.36#ibcon#read 6, iclass 16, count 2 2006.201.09:13:29.36#ibcon#end of sib2, iclass 16, count 2 2006.201.09:13:29.36#ibcon#*mode == 0, iclass 16, count 2 2006.201.09:13:29.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.09:13:29.36#ibcon#[25=AT02-07\r\n] 2006.201.09:13:29.36#ibcon#*before write, iclass 16, count 2 2006.201.09:13:29.36#ibcon#enter sib2, iclass 16, count 2 2006.201.09:13:29.36#ibcon#flushed, iclass 16, count 2 2006.201.09:13:29.36#ibcon#about to write, iclass 16, count 2 2006.201.09:13:29.36#ibcon#wrote, iclass 16, count 2 2006.201.09:13:29.36#ibcon#about to read 3, iclass 16, count 2 2006.201.09:13:29.39#ibcon#read 3, iclass 16, count 2 2006.201.09:13:29.39#ibcon#about to read 4, iclass 16, count 2 2006.201.09:13:29.39#ibcon#read 4, iclass 16, count 2 2006.201.09:13:29.39#ibcon#about to read 5, iclass 16, count 2 2006.201.09:13:29.39#ibcon#read 5, iclass 16, count 2 2006.201.09:13:29.39#ibcon#about to read 6, iclass 16, count 2 2006.201.09:13:29.39#ibcon#read 6, iclass 16, count 2 2006.201.09:13:29.39#ibcon#end of sib2, iclass 16, count 2 2006.201.09:13:29.39#ibcon#*after write, iclass 16, count 2 2006.201.09:13:29.39#ibcon#*before return 0, iclass 16, count 2 2006.201.09:13:29.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:29.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:29.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.09:13:29.39#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:29.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:29.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:29.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:29.51#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:13:29.51#ibcon#first serial, iclass 16, count 0 2006.201.09:13:29.51#ibcon#enter sib2, iclass 16, count 0 2006.201.09:13:29.51#ibcon#flushed, iclass 16, count 0 2006.201.09:13:29.51#ibcon#about to write, iclass 16, count 0 2006.201.09:13:29.51#ibcon#wrote, iclass 16, count 0 2006.201.09:13:29.51#ibcon#about to read 3, iclass 16, count 0 2006.201.09:13:29.53#ibcon#read 3, iclass 16, count 0 2006.201.09:13:29.53#ibcon#about to read 4, iclass 16, count 0 2006.201.09:13:29.53#ibcon#read 4, iclass 16, count 0 2006.201.09:13:29.53#ibcon#about to read 5, iclass 16, count 0 2006.201.09:13:29.53#ibcon#read 5, iclass 16, count 0 2006.201.09:13:29.53#ibcon#about to read 6, iclass 16, count 0 2006.201.09:13:29.53#ibcon#read 6, iclass 16, count 0 2006.201.09:13:29.53#ibcon#end of sib2, iclass 16, count 0 2006.201.09:13:29.53#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:13:29.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:13:29.53#ibcon#[25=USB\r\n] 2006.201.09:13:29.53#ibcon#*before write, iclass 16, count 0 2006.201.09:13:29.53#ibcon#enter sib2, iclass 16, count 0 2006.201.09:13:29.53#ibcon#flushed, iclass 16, count 0 2006.201.09:13:29.53#ibcon#about to write, iclass 16, count 0 2006.201.09:13:29.53#ibcon#wrote, iclass 16, count 0 2006.201.09:13:29.53#ibcon#about to read 3, iclass 16, count 0 2006.201.09:13:29.56#ibcon#read 3, iclass 16, count 0 2006.201.09:13:29.56#ibcon#about to read 4, iclass 16, count 0 2006.201.09:13:29.56#ibcon#read 4, iclass 16, count 0 2006.201.09:13:29.56#ibcon#about to read 5, iclass 16, count 0 2006.201.09:13:29.56#ibcon#read 5, iclass 16, count 0 2006.201.09:13:29.56#ibcon#about to read 6, iclass 16, count 0 2006.201.09:13:29.56#ibcon#read 6, iclass 16, count 0 2006.201.09:13:29.56#ibcon#end of sib2, iclass 16, count 0 2006.201.09:13:29.56#ibcon#*after write, iclass 16, count 0 2006.201.09:13:29.56#ibcon#*before return 0, iclass 16, count 0 2006.201.09:13:29.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:29.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:29.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:13:29.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:13:29.56$vck44/valo=3,564.99 2006.201.09:13:29.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.09:13:29.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.09:13:29.56#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:29.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:29.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:29.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:29.56#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:13:29.56#ibcon#first serial, iclass 18, count 0 2006.201.09:13:29.56#ibcon#enter sib2, iclass 18, count 0 2006.201.09:13:29.56#ibcon#flushed, iclass 18, count 0 2006.201.09:13:29.56#ibcon#about to write, iclass 18, count 0 2006.201.09:13:29.56#ibcon#wrote, iclass 18, count 0 2006.201.09:13:29.56#ibcon#about to read 3, iclass 18, count 0 2006.201.09:13:29.58#ibcon#read 3, iclass 18, count 0 2006.201.09:13:29.58#ibcon#about to read 4, iclass 18, count 0 2006.201.09:13:29.58#ibcon#read 4, iclass 18, count 0 2006.201.09:13:29.58#ibcon#about to read 5, iclass 18, count 0 2006.201.09:13:29.58#ibcon#read 5, iclass 18, count 0 2006.201.09:13:29.58#ibcon#about to read 6, iclass 18, count 0 2006.201.09:13:29.58#ibcon#read 6, iclass 18, count 0 2006.201.09:13:29.58#ibcon#end of sib2, iclass 18, count 0 2006.201.09:13:29.58#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:13:29.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:13:29.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:13:29.58#ibcon#*before write, iclass 18, count 0 2006.201.09:13:29.58#ibcon#enter sib2, iclass 18, count 0 2006.201.09:13:29.58#ibcon#flushed, iclass 18, count 0 2006.201.09:13:29.58#ibcon#about to write, iclass 18, count 0 2006.201.09:13:29.58#ibcon#wrote, iclass 18, count 0 2006.201.09:13:29.58#ibcon#about to read 3, iclass 18, count 0 2006.201.09:13:29.63#ibcon#read 3, iclass 18, count 0 2006.201.09:13:29.63#ibcon#about to read 4, iclass 18, count 0 2006.201.09:13:29.63#ibcon#read 4, iclass 18, count 0 2006.201.09:13:29.63#ibcon#about to read 5, iclass 18, count 0 2006.201.09:13:29.63#ibcon#read 5, iclass 18, count 0 2006.201.09:13:29.63#ibcon#about to read 6, iclass 18, count 0 2006.201.09:13:29.63#ibcon#read 6, iclass 18, count 0 2006.201.09:13:29.63#ibcon#end of sib2, iclass 18, count 0 2006.201.09:13:29.63#ibcon#*after write, iclass 18, count 0 2006.201.09:13:29.63#ibcon#*before return 0, iclass 18, count 0 2006.201.09:13:29.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:29.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:29.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:13:29.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:13:29.63$vck44/va=3,8 2006.201.09:13:29.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.09:13:29.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.09:13:29.63#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:29.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:29.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:29.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:29.68#ibcon#enter wrdev, iclass 20, count 2 2006.201.09:13:29.68#ibcon#first serial, iclass 20, count 2 2006.201.09:13:29.68#ibcon#enter sib2, iclass 20, count 2 2006.201.09:13:29.68#ibcon#flushed, iclass 20, count 2 2006.201.09:13:29.68#ibcon#about to write, iclass 20, count 2 2006.201.09:13:29.68#ibcon#wrote, iclass 20, count 2 2006.201.09:13:29.68#ibcon#about to read 3, iclass 20, count 2 2006.201.09:13:29.70#ibcon#read 3, iclass 20, count 2 2006.201.09:13:29.70#ibcon#about to read 4, iclass 20, count 2 2006.201.09:13:29.70#ibcon#read 4, iclass 20, count 2 2006.201.09:13:29.70#ibcon#about to read 5, iclass 20, count 2 2006.201.09:13:29.70#ibcon#read 5, iclass 20, count 2 2006.201.09:13:29.70#ibcon#about to read 6, iclass 20, count 2 2006.201.09:13:29.70#ibcon#read 6, iclass 20, count 2 2006.201.09:13:29.70#ibcon#end of sib2, iclass 20, count 2 2006.201.09:13:29.70#ibcon#*mode == 0, iclass 20, count 2 2006.201.09:13:29.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.09:13:29.70#ibcon#[25=AT03-08\r\n] 2006.201.09:13:29.70#ibcon#*before write, iclass 20, count 2 2006.201.09:13:29.70#ibcon#enter sib2, iclass 20, count 2 2006.201.09:13:29.70#ibcon#flushed, iclass 20, count 2 2006.201.09:13:29.70#ibcon#about to write, iclass 20, count 2 2006.201.09:13:29.70#ibcon#wrote, iclass 20, count 2 2006.201.09:13:29.70#ibcon#about to read 3, iclass 20, count 2 2006.201.09:13:29.73#ibcon#read 3, iclass 20, count 2 2006.201.09:13:29.73#ibcon#about to read 4, iclass 20, count 2 2006.201.09:13:29.73#ibcon#read 4, iclass 20, count 2 2006.201.09:13:29.73#ibcon#about to read 5, iclass 20, count 2 2006.201.09:13:29.73#ibcon#read 5, iclass 20, count 2 2006.201.09:13:29.73#ibcon#about to read 6, iclass 20, count 2 2006.201.09:13:29.73#ibcon#read 6, iclass 20, count 2 2006.201.09:13:29.73#ibcon#end of sib2, iclass 20, count 2 2006.201.09:13:29.73#ibcon#*after write, iclass 20, count 2 2006.201.09:13:29.73#ibcon#*before return 0, iclass 20, count 2 2006.201.09:13:29.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:29.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:29.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.09:13:29.73#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:29.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:29.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:29.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:29.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.09:13:29.85#ibcon#first serial, iclass 20, count 0 2006.201.09:13:29.85#ibcon#enter sib2, iclass 20, count 0 2006.201.09:13:29.85#ibcon#flushed, iclass 20, count 0 2006.201.09:13:29.85#ibcon#about to write, iclass 20, count 0 2006.201.09:13:29.85#ibcon#wrote, iclass 20, count 0 2006.201.09:13:29.85#ibcon#about to read 3, iclass 20, count 0 2006.201.09:13:29.87#ibcon#read 3, iclass 20, count 0 2006.201.09:13:29.87#ibcon#about to read 4, iclass 20, count 0 2006.201.09:13:29.87#ibcon#read 4, iclass 20, count 0 2006.201.09:13:29.87#ibcon#about to read 5, iclass 20, count 0 2006.201.09:13:29.87#ibcon#read 5, iclass 20, count 0 2006.201.09:13:29.87#ibcon#about to read 6, iclass 20, count 0 2006.201.09:13:29.87#ibcon#read 6, iclass 20, count 0 2006.201.09:13:29.87#ibcon#end of sib2, iclass 20, count 0 2006.201.09:13:29.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.09:13:29.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.09:13:29.87#ibcon#[25=USB\r\n] 2006.201.09:13:29.87#ibcon#*before write, iclass 20, count 0 2006.201.09:13:29.87#ibcon#enter sib2, iclass 20, count 0 2006.201.09:13:29.87#ibcon#flushed, iclass 20, count 0 2006.201.09:13:29.87#ibcon#about to write, iclass 20, count 0 2006.201.09:13:29.87#ibcon#wrote, iclass 20, count 0 2006.201.09:13:29.87#ibcon#about to read 3, iclass 20, count 0 2006.201.09:13:29.90#ibcon#read 3, iclass 20, count 0 2006.201.09:13:29.90#ibcon#about to read 4, iclass 20, count 0 2006.201.09:13:29.90#ibcon#read 4, iclass 20, count 0 2006.201.09:13:29.90#ibcon#about to read 5, iclass 20, count 0 2006.201.09:13:29.90#ibcon#read 5, iclass 20, count 0 2006.201.09:13:29.90#ibcon#about to read 6, iclass 20, count 0 2006.201.09:13:29.90#ibcon#read 6, iclass 20, count 0 2006.201.09:13:29.90#ibcon#end of sib2, iclass 20, count 0 2006.201.09:13:29.90#ibcon#*after write, iclass 20, count 0 2006.201.09:13:29.90#ibcon#*before return 0, iclass 20, count 0 2006.201.09:13:29.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:29.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:29.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.09:13:29.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.09:13:29.90$vck44/valo=4,624.99 2006.201.09:13:29.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.09:13:29.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.09:13:29.90#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:29.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:29.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:29.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:29.90#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:13:29.90#ibcon#first serial, iclass 22, count 0 2006.201.09:13:29.90#ibcon#enter sib2, iclass 22, count 0 2006.201.09:13:29.90#ibcon#flushed, iclass 22, count 0 2006.201.09:13:29.90#ibcon#about to write, iclass 22, count 0 2006.201.09:13:29.90#ibcon#wrote, iclass 22, count 0 2006.201.09:13:29.90#ibcon#about to read 3, iclass 22, count 0 2006.201.09:13:29.92#ibcon#read 3, iclass 22, count 0 2006.201.09:13:29.92#ibcon#about to read 4, iclass 22, count 0 2006.201.09:13:29.92#ibcon#read 4, iclass 22, count 0 2006.201.09:13:29.92#ibcon#about to read 5, iclass 22, count 0 2006.201.09:13:29.92#ibcon#read 5, iclass 22, count 0 2006.201.09:13:29.92#ibcon#about to read 6, iclass 22, count 0 2006.201.09:13:29.92#ibcon#read 6, iclass 22, count 0 2006.201.09:13:29.92#ibcon#end of sib2, iclass 22, count 0 2006.201.09:13:29.92#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:13:29.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:13:29.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:13:29.92#ibcon#*before write, iclass 22, count 0 2006.201.09:13:29.92#ibcon#enter sib2, iclass 22, count 0 2006.201.09:13:29.92#ibcon#flushed, iclass 22, count 0 2006.201.09:13:29.92#ibcon#about to write, iclass 22, count 0 2006.201.09:13:29.92#ibcon#wrote, iclass 22, count 0 2006.201.09:13:29.92#ibcon#about to read 3, iclass 22, count 0 2006.201.09:13:29.96#ibcon#read 3, iclass 22, count 0 2006.201.09:13:29.96#ibcon#about to read 4, iclass 22, count 0 2006.201.09:13:29.96#ibcon#read 4, iclass 22, count 0 2006.201.09:13:29.96#ibcon#about to read 5, iclass 22, count 0 2006.201.09:13:29.96#ibcon#read 5, iclass 22, count 0 2006.201.09:13:29.96#ibcon#about to read 6, iclass 22, count 0 2006.201.09:13:29.96#ibcon#read 6, iclass 22, count 0 2006.201.09:13:29.96#ibcon#end of sib2, iclass 22, count 0 2006.201.09:13:29.96#ibcon#*after write, iclass 22, count 0 2006.201.09:13:29.96#ibcon#*before return 0, iclass 22, count 0 2006.201.09:13:29.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:29.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:29.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:13:29.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:13:29.96$vck44/va=4,7 2006.201.09:13:29.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.09:13:29.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.09:13:29.96#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:29.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:30.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:30.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:30.02#ibcon#enter wrdev, iclass 24, count 2 2006.201.09:13:30.02#ibcon#first serial, iclass 24, count 2 2006.201.09:13:30.02#ibcon#enter sib2, iclass 24, count 2 2006.201.09:13:30.02#ibcon#flushed, iclass 24, count 2 2006.201.09:13:30.02#ibcon#about to write, iclass 24, count 2 2006.201.09:13:30.02#ibcon#wrote, iclass 24, count 2 2006.201.09:13:30.02#ibcon#about to read 3, iclass 24, count 2 2006.201.09:13:30.04#ibcon#read 3, iclass 24, count 2 2006.201.09:13:30.04#ibcon#about to read 4, iclass 24, count 2 2006.201.09:13:30.04#ibcon#read 4, iclass 24, count 2 2006.201.09:13:30.04#ibcon#about to read 5, iclass 24, count 2 2006.201.09:13:30.04#ibcon#read 5, iclass 24, count 2 2006.201.09:13:30.04#ibcon#about to read 6, iclass 24, count 2 2006.201.09:13:30.04#ibcon#read 6, iclass 24, count 2 2006.201.09:13:30.04#ibcon#end of sib2, iclass 24, count 2 2006.201.09:13:30.04#ibcon#*mode == 0, iclass 24, count 2 2006.201.09:13:30.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.09:13:30.04#ibcon#[25=AT04-07\r\n] 2006.201.09:13:30.04#ibcon#*before write, iclass 24, count 2 2006.201.09:13:30.04#ibcon#enter sib2, iclass 24, count 2 2006.201.09:13:30.04#ibcon#flushed, iclass 24, count 2 2006.201.09:13:30.04#ibcon#about to write, iclass 24, count 2 2006.201.09:13:30.04#ibcon#wrote, iclass 24, count 2 2006.201.09:13:30.04#ibcon#about to read 3, iclass 24, count 2 2006.201.09:13:30.07#ibcon#read 3, iclass 24, count 2 2006.201.09:13:30.07#ibcon#about to read 4, iclass 24, count 2 2006.201.09:13:30.07#ibcon#read 4, iclass 24, count 2 2006.201.09:13:30.07#ibcon#about to read 5, iclass 24, count 2 2006.201.09:13:30.07#ibcon#read 5, iclass 24, count 2 2006.201.09:13:30.07#ibcon#about to read 6, iclass 24, count 2 2006.201.09:13:30.07#ibcon#read 6, iclass 24, count 2 2006.201.09:13:30.07#ibcon#end of sib2, iclass 24, count 2 2006.201.09:13:30.07#ibcon#*after write, iclass 24, count 2 2006.201.09:13:30.07#ibcon#*before return 0, iclass 24, count 2 2006.201.09:13:30.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:30.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:30.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.09:13:30.07#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:30.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:30.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:30.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:30.19#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:13:30.19#ibcon#first serial, iclass 24, count 0 2006.201.09:13:30.19#ibcon#enter sib2, iclass 24, count 0 2006.201.09:13:30.19#ibcon#flushed, iclass 24, count 0 2006.201.09:13:30.19#ibcon#about to write, iclass 24, count 0 2006.201.09:13:30.19#ibcon#wrote, iclass 24, count 0 2006.201.09:13:30.19#ibcon#about to read 3, iclass 24, count 0 2006.201.09:13:30.21#ibcon#read 3, iclass 24, count 0 2006.201.09:13:30.21#ibcon#about to read 4, iclass 24, count 0 2006.201.09:13:30.21#ibcon#read 4, iclass 24, count 0 2006.201.09:13:30.21#ibcon#about to read 5, iclass 24, count 0 2006.201.09:13:30.21#ibcon#read 5, iclass 24, count 0 2006.201.09:13:30.21#ibcon#about to read 6, iclass 24, count 0 2006.201.09:13:30.21#ibcon#read 6, iclass 24, count 0 2006.201.09:13:30.21#ibcon#end of sib2, iclass 24, count 0 2006.201.09:13:30.21#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:13:30.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:13:30.21#ibcon#[25=USB\r\n] 2006.201.09:13:30.21#ibcon#*before write, iclass 24, count 0 2006.201.09:13:30.21#ibcon#enter sib2, iclass 24, count 0 2006.201.09:13:30.21#ibcon#flushed, iclass 24, count 0 2006.201.09:13:30.21#ibcon#about to write, iclass 24, count 0 2006.201.09:13:30.21#ibcon#wrote, iclass 24, count 0 2006.201.09:13:30.21#ibcon#about to read 3, iclass 24, count 0 2006.201.09:13:30.24#ibcon#read 3, iclass 24, count 0 2006.201.09:13:30.24#ibcon#about to read 4, iclass 24, count 0 2006.201.09:13:30.24#ibcon#read 4, iclass 24, count 0 2006.201.09:13:30.24#ibcon#about to read 5, iclass 24, count 0 2006.201.09:13:30.24#ibcon#read 5, iclass 24, count 0 2006.201.09:13:30.24#ibcon#about to read 6, iclass 24, count 0 2006.201.09:13:30.24#ibcon#read 6, iclass 24, count 0 2006.201.09:13:30.24#ibcon#end of sib2, iclass 24, count 0 2006.201.09:13:30.24#ibcon#*after write, iclass 24, count 0 2006.201.09:13:30.24#ibcon#*before return 0, iclass 24, count 0 2006.201.09:13:30.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:30.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:30.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:13:30.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:13:30.24$vck44/valo=5,734.99 2006.201.09:13:30.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.09:13:30.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.09:13:30.24#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:30.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:30.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:30.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:30.24#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:13:30.24#ibcon#first serial, iclass 26, count 0 2006.201.09:13:30.24#ibcon#enter sib2, iclass 26, count 0 2006.201.09:13:30.24#ibcon#flushed, iclass 26, count 0 2006.201.09:13:30.24#ibcon#about to write, iclass 26, count 0 2006.201.09:13:30.24#ibcon#wrote, iclass 26, count 0 2006.201.09:13:30.24#ibcon#about to read 3, iclass 26, count 0 2006.201.09:13:30.26#ibcon#read 3, iclass 26, count 0 2006.201.09:13:30.26#ibcon#about to read 4, iclass 26, count 0 2006.201.09:13:30.26#ibcon#read 4, iclass 26, count 0 2006.201.09:13:30.26#ibcon#about to read 5, iclass 26, count 0 2006.201.09:13:30.26#ibcon#read 5, iclass 26, count 0 2006.201.09:13:30.26#ibcon#about to read 6, iclass 26, count 0 2006.201.09:13:30.26#ibcon#read 6, iclass 26, count 0 2006.201.09:13:30.26#ibcon#end of sib2, iclass 26, count 0 2006.201.09:13:30.26#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:13:30.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:13:30.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:13:30.26#ibcon#*before write, iclass 26, count 0 2006.201.09:13:30.26#ibcon#enter sib2, iclass 26, count 0 2006.201.09:13:30.26#ibcon#flushed, iclass 26, count 0 2006.201.09:13:30.26#ibcon#about to write, iclass 26, count 0 2006.201.09:13:30.26#ibcon#wrote, iclass 26, count 0 2006.201.09:13:30.26#ibcon#about to read 3, iclass 26, count 0 2006.201.09:13:30.30#ibcon#read 3, iclass 26, count 0 2006.201.09:13:30.30#ibcon#about to read 4, iclass 26, count 0 2006.201.09:13:30.30#ibcon#read 4, iclass 26, count 0 2006.201.09:13:30.30#ibcon#about to read 5, iclass 26, count 0 2006.201.09:13:30.30#ibcon#read 5, iclass 26, count 0 2006.201.09:13:30.30#ibcon#about to read 6, iclass 26, count 0 2006.201.09:13:30.30#ibcon#read 6, iclass 26, count 0 2006.201.09:13:30.30#ibcon#end of sib2, iclass 26, count 0 2006.201.09:13:30.30#ibcon#*after write, iclass 26, count 0 2006.201.09:13:30.30#ibcon#*before return 0, iclass 26, count 0 2006.201.09:13:30.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:30.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:30.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:13:30.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:13:30.30$vck44/va=5,4 2006.201.09:13:30.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.09:13:30.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.09:13:30.30#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:30.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:30.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:30.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:30.36#ibcon#enter wrdev, iclass 28, count 2 2006.201.09:13:30.36#ibcon#first serial, iclass 28, count 2 2006.201.09:13:30.36#ibcon#enter sib2, iclass 28, count 2 2006.201.09:13:30.36#ibcon#flushed, iclass 28, count 2 2006.201.09:13:30.36#ibcon#about to write, iclass 28, count 2 2006.201.09:13:30.36#ibcon#wrote, iclass 28, count 2 2006.201.09:13:30.36#ibcon#about to read 3, iclass 28, count 2 2006.201.09:13:30.38#ibcon#read 3, iclass 28, count 2 2006.201.09:13:30.38#ibcon#about to read 4, iclass 28, count 2 2006.201.09:13:30.38#ibcon#read 4, iclass 28, count 2 2006.201.09:13:30.38#ibcon#about to read 5, iclass 28, count 2 2006.201.09:13:30.38#ibcon#read 5, iclass 28, count 2 2006.201.09:13:30.38#ibcon#about to read 6, iclass 28, count 2 2006.201.09:13:30.38#ibcon#read 6, iclass 28, count 2 2006.201.09:13:30.38#ibcon#end of sib2, iclass 28, count 2 2006.201.09:13:30.38#ibcon#*mode == 0, iclass 28, count 2 2006.201.09:13:30.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.09:13:30.38#ibcon#[25=AT05-04\r\n] 2006.201.09:13:30.38#ibcon#*before write, iclass 28, count 2 2006.201.09:13:30.38#ibcon#enter sib2, iclass 28, count 2 2006.201.09:13:30.38#ibcon#flushed, iclass 28, count 2 2006.201.09:13:30.38#ibcon#about to write, iclass 28, count 2 2006.201.09:13:30.38#ibcon#wrote, iclass 28, count 2 2006.201.09:13:30.38#ibcon#about to read 3, iclass 28, count 2 2006.201.09:13:30.41#ibcon#read 3, iclass 28, count 2 2006.201.09:13:30.41#ibcon#about to read 4, iclass 28, count 2 2006.201.09:13:30.41#ibcon#read 4, iclass 28, count 2 2006.201.09:13:30.41#ibcon#about to read 5, iclass 28, count 2 2006.201.09:13:30.41#ibcon#read 5, iclass 28, count 2 2006.201.09:13:30.41#ibcon#about to read 6, iclass 28, count 2 2006.201.09:13:30.41#ibcon#read 6, iclass 28, count 2 2006.201.09:13:30.41#ibcon#end of sib2, iclass 28, count 2 2006.201.09:13:30.41#ibcon#*after write, iclass 28, count 2 2006.201.09:13:30.41#ibcon#*before return 0, iclass 28, count 2 2006.201.09:13:30.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:30.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:30.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.09:13:30.41#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:30.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:30.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:30.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:30.53#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:13:30.53#ibcon#first serial, iclass 28, count 0 2006.201.09:13:30.53#ibcon#enter sib2, iclass 28, count 0 2006.201.09:13:30.53#ibcon#flushed, iclass 28, count 0 2006.201.09:13:30.53#ibcon#about to write, iclass 28, count 0 2006.201.09:13:30.53#ibcon#wrote, iclass 28, count 0 2006.201.09:13:30.53#ibcon#about to read 3, iclass 28, count 0 2006.201.09:13:30.55#ibcon#read 3, iclass 28, count 0 2006.201.09:13:30.55#ibcon#about to read 4, iclass 28, count 0 2006.201.09:13:30.55#ibcon#read 4, iclass 28, count 0 2006.201.09:13:30.55#ibcon#about to read 5, iclass 28, count 0 2006.201.09:13:30.55#ibcon#read 5, iclass 28, count 0 2006.201.09:13:30.55#ibcon#about to read 6, iclass 28, count 0 2006.201.09:13:30.55#ibcon#read 6, iclass 28, count 0 2006.201.09:13:30.55#ibcon#end of sib2, iclass 28, count 0 2006.201.09:13:30.55#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:13:30.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:13:30.55#ibcon#[25=USB\r\n] 2006.201.09:13:30.55#ibcon#*before write, iclass 28, count 0 2006.201.09:13:30.55#ibcon#enter sib2, iclass 28, count 0 2006.201.09:13:30.55#ibcon#flushed, iclass 28, count 0 2006.201.09:13:30.55#ibcon#about to write, iclass 28, count 0 2006.201.09:13:30.55#ibcon#wrote, iclass 28, count 0 2006.201.09:13:30.55#ibcon#about to read 3, iclass 28, count 0 2006.201.09:13:30.58#ibcon#read 3, iclass 28, count 0 2006.201.09:13:30.58#ibcon#about to read 4, iclass 28, count 0 2006.201.09:13:30.58#ibcon#read 4, iclass 28, count 0 2006.201.09:13:30.58#ibcon#about to read 5, iclass 28, count 0 2006.201.09:13:30.58#ibcon#read 5, iclass 28, count 0 2006.201.09:13:30.58#ibcon#about to read 6, iclass 28, count 0 2006.201.09:13:30.58#ibcon#read 6, iclass 28, count 0 2006.201.09:13:30.58#ibcon#end of sib2, iclass 28, count 0 2006.201.09:13:30.58#ibcon#*after write, iclass 28, count 0 2006.201.09:13:30.58#ibcon#*before return 0, iclass 28, count 0 2006.201.09:13:30.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:30.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:30.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:13:30.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:13:30.58$vck44/valo=6,814.99 2006.201.09:13:30.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.09:13:30.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.09:13:30.58#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:30.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:30.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:30.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:30.58#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:13:30.58#ibcon#first serial, iclass 30, count 0 2006.201.09:13:30.58#ibcon#enter sib2, iclass 30, count 0 2006.201.09:13:30.58#ibcon#flushed, iclass 30, count 0 2006.201.09:13:30.58#ibcon#about to write, iclass 30, count 0 2006.201.09:13:30.58#ibcon#wrote, iclass 30, count 0 2006.201.09:13:30.58#ibcon#about to read 3, iclass 30, count 0 2006.201.09:13:30.60#ibcon#read 3, iclass 30, count 0 2006.201.09:13:30.60#ibcon#about to read 4, iclass 30, count 0 2006.201.09:13:30.60#ibcon#read 4, iclass 30, count 0 2006.201.09:13:30.60#ibcon#about to read 5, iclass 30, count 0 2006.201.09:13:30.60#ibcon#read 5, iclass 30, count 0 2006.201.09:13:30.60#ibcon#about to read 6, iclass 30, count 0 2006.201.09:13:30.60#ibcon#read 6, iclass 30, count 0 2006.201.09:13:30.60#ibcon#end of sib2, iclass 30, count 0 2006.201.09:13:30.60#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:13:30.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:13:30.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:13:30.60#ibcon#*before write, iclass 30, count 0 2006.201.09:13:30.60#ibcon#enter sib2, iclass 30, count 0 2006.201.09:13:30.60#ibcon#flushed, iclass 30, count 0 2006.201.09:13:30.60#ibcon#about to write, iclass 30, count 0 2006.201.09:13:30.60#ibcon#wrote, iclass 30, count 0 2006.201.09:13:30.60#ibcon#about to read 3, iclass 30, count 0 2006.201.09:13:30.64#ibcon#read 3, iclass 30, count 0 2006.201.09:13:30.64#ibcon#about to read 4, iclass 30, count 0 2006.201.09:13:30.64#ibcon#read 4, iclass 30, count 0 2006.201.09:13:30.64#ibcon#about to read 5, iclass 30, count 0 2006.201.09:13:30.64#ibcon#read 5, iclass 30, count 0 2006.201.09:13:30.64#ibcon#about to read 6, iclass 30, count 0 2006.201.09:13:30.64#ibcon#read 6, iclass 30, count 0 2006.201.09:13:30.64#ibcon#end of sib2, iclass 30, count 0 2006.201.09:13:30.64#ibcon#*after write, iclass 30, count 0 2006.201.09:13:30.64#ibcon#*before return 0, iclass 30, count 0 2006.201.09:13:30.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:30.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:30.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:13:30.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:13:30.64$vck44/va=6,5 2006.201.09:13:30.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.09:13:30.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.09:13:30.64#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:30.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:30.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:30.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:30.70#ibcon#enter wrdev, iclass 32, count 2 2006.201.09:13:30.70#ibcon#first serial, iclass 32, count 2 2006.201.09:13:30.70#ibcon#enter sib2, iclass 32, count 2 2006.201.09:13:30.70#ibcon#flushed, iclass 32, count 2 2006.201.09:13:30.70#ibcon#about to write, iclass 32, count 2 2006.201.09:13:30.70#ibcon#wrote, iclass 32, count 2 2006.201.09:13:30.70#ibcon#about to read 3, iclass 32, count 2 2006.201.09:13:30.72#ibcon#read 3, iclass 32, count 2 2006.201.09:13:30.72#ibcon#about to read 4, iclass 32, count 2 2006.201.09:13:30.72#ibcon#read 4, iclass 32, count 2 2006.201.09:13:30.72#ibcon#about to read 5, iclass 32, count 2 2006.201.09:13:30.72#ibcon#read 5, iclass 32, count 2 2006.201.09:13:30.72#ibcon#about to read 6, iclass 32, count 2 2006.201.09:13:30.72#ibcon#read 6, iclass 32, count 2 2006.201.09:13:30.72#ibcon#end of sib2, iclass 32, count 2 2006.201.09:13:30.72#ibcon#*mode == 0, iclass 32, count 2 2006.201.09:13:30.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.09:13:30.72#ibcon#[25=AT06-05\r\n] 2006.201.09:13:30.72#ibcon#*before write, iclass 32, count 2 2006.201.09:13:30.72#ibcon#enter sib2, iclass 32, count 2 2006.201.09:13:30.72#ibcon#flushed, iclass 32, count 2 2006.201.09:13:30.72#ibcon#about to write, iclass 32, count 2 2006.201.09:13:30.72#ibcon#wrote, iclass 32, count 2 2006.201.09:13:30.72#ibcon#about to read 3, iclass 32, count 2 2006.201.09:13:30.75#ibcon#read 3, iclass 32, count 2 2006.201.09:13:30.75#ibcon#about to read 4, iclass 32, count 2 2006.201.09:13:30.75#ibcon#read 4, iclass 32, count 2 2006.201.09:13:30.75#ibcon#about to read 5, iclass 32, count 2 2006.201.09:13:30.75#ibcon#read 5, iclass 32, count 2 2006.201.09:13:30.75#ibcon#about to read 6, iclass 32, count 2 2006.201.09:13:30.75#ibcon#read 6, iclass 32, count 2 2006.201.09:13:30.75#ibcon#end of sib2, iclass 32, count 2 2006.201.09:13:30.75#ibcon#*after write, iclass 32, count 2 2006.201.09:13:30.75#ibcon#*before return 0, iclass 32, count 2 2006.201.09:13:30.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:30.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:30.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.09:13:30.75#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:30.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:30.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:30.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:30.87#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:13:30.87#ibcon#first serial, iclass 32, count 0 2006.201.09:13:30.87#ibcon#enter sib2, iclass 32, count 0 2006.201.09:13:30.87#ibcon#flushed, iclass 32, count 0 2006.201.09:13:30.87#ibcon#about to write, iclass 32, count 0 2006.201.09:13:30.87#ibcon#wrote, iclass 32, count 0 2006.201.09:13:30.87#ibcon#about to read 3, iclass 32, count 0 2006.201.09:13:30.89#ibcon#read 3, iclass 32, count 0 2006.201.09:13:30.89#ibcon#about to read 4, iclass 32, count 0 2006.201.09:13:30.89#ibcon#read 4, iclass 32, count 0 2006.201.09:13:30.89#ibcon#about to read 5, iclass 32, count 0 2006.201.09:13:30.89#ibcon#read 5, iclass 32, count 0 2006.201.09:13:30.89#ibcon#about to read 6, iclass 32, count 0 2006.201.09:13:30.89#ibcon#read 6, iclass 32, count 0 2006.201.09:13:30.89#ibcon#end of sib2, iclass 32, count 0 2006.201.09:13:30.89#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:13:30.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:13:30.89#ibcon#[25=USB\r\n] 2006.201.09:13:30.89#ibcon#*before write, iclass 32, count 0 2006.201.09:13:30.89#ibcon#enter sib2, iclass 32, count 0 2006.201.09:13:30.89#ibcon#flushed, iclass 32, count 0 2006.201.09:13:30.89#ibcon#about to write, iclass 32, count 0 2006.201.09:13:30.89#ibcon#wrote, iclass 32, count 0 2006.201.09:13:30.89#ibcon#about to read 3, iclass 32, count 0 2006.201.09:13:30.92#ibcon#read 3, iclass 32, count 0 2006.201.09:13:30.92#ibcon#about to read 4, iclass 32, count 0 2006.201.09:13:30.92#ibcon#read 4, iclass 32, count 0 2006.201.09:13:30.92#ibcon#about to read 5, iclass 32, count 0 2006.201.09:13:30.92#ibcon#read 5, iclass 32, count 0 2006.201.09:13:30.92#ibcon#about to read 6, iclass 32, count 0 2006.201.09:13:30.92#ibcon#read 6, iclass 32, count 0 2006.201.09:13:30.92#ibcon#end of sib2, iclass 32, count 0 2006.201.09:13:30.92#ibcon#*after write, iclass 32, count 0 2006.201.09:13:30.92#ibcon#*before return 0, iclass 32, count 0 2006.201.09:13:30.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:30.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:30.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:13:30.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:13:30.92$vck44/valo=7,864.99 2006.201.09:13:30.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.09:13:30.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.09:13:30.92#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:30.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:30.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:30.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:30.92#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:13:30.92#ibcon#first serial, iclass 34, count 0 2006.201.09:13:30.92#ibcon#enter sib2, iclass 34, count 0 2006.201.09:13:30.92#ibcon#flushed, iclass 34, count 0 2006.201.09:13:30.92#ibcon#about to write, iclass 34, count 0 2006.201.09:13:30.92#ibcon#wrote, iclass 34, count 0 2006.201.09:13:30.92#ibcon#about to read 3, iclass 34, count 0 2006.201.09:13:30.94#ibcon#read 3, iclass 34, count 0 2006.201.09:13:30.94#ibcon#about to read 4, iclass 34, count 0 2006.201.09:13:30.94#ibcon#read 4, iclass 34, count 0 2006.201.09:13:30.94#ibcon#about to read 5, iclass 34, count 0 2006.201.09:13:30.94#ibcon#read 5, iclass 34, count 0 2006.201.09:13:30.94#ibcon#about to read 6, iclass 34, count 0 2006.201.09:13:30.94#ibcon#read 6, iclass 34, count 0 2006.201.09:13:30.94#ibcon#end of sib2, iclass 34, count 0 2006.201.09:13:30.94#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:13:30.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:13:30.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:13:30.94#ibcon#*before write, iclass 34, count 0 2006.201.09:13:30.94#ibcon#enter sib2, iclass 34, count 0 2006.201.09:13:30.94#ibcon#flushed, iclass 34, count 0 2006.201.09:13:30.94#ibcon#about to write, iclass 34, count 0 2006.201.09:13:30.94#ibcon#wrote, iclass 34, count 0 2006.201.09:13:30.94#ibcon#about to read 3, iclass 34, count 0 2006.201.09:13:30.98#ibcon#read 3, iclass 34, count 0 2006.201.09:13:30.98#ibcon#about to read 4, iclass 34, count 0 2006.201.09:13:30.98#ibcon#read 4, iclass 34, count 0 2006.201.09:13:30.98#ibcon#about to read 5, iclass 34, count 0 2006.201.09:13:30.98#ibcon#read 5, iclass 34, count 0 2006.201.09:13:30.98#ibcon#about to read 6, iclass 34, count 0 2006.201.09:13:30.98#ibcon#read 6, iclass 34, count 0 2006.201.09:13:30.98#ibcon#end of sib2, iclass 34, count 0 2006.201.09:13:30.98#ibcon#*after write, iclass 34, count 0 2006.201.09:13:30.98#ibcon#*before return 0, iclass 34, count 0 2006.201.09:13:30.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:30.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:30.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:13:30.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:13:30.98$vck44/va=7,5 2006.201.09:13:30.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.09:13:30.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.09:13:30.98#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:30.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:31.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:31.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:31.04#ibcon#enter wrdev, iclass 36, count 2 2006.201.09:13:31.04#ibcon#first serial, iclass 36, count 2 2006.201.09:13:31.04#ibcon#enter sib2, iclass 36, count 2 2006.201.09:13:31.04#ibcon#flushed, iclass 36, count 2 2006.201.09:13:31.04#ibcon#about to write, iclass 36, count 2 2006.201.09:13:31.04#ibcon#wrote, iclass 36, count 2 2006.201.09:13:31.04#ibcon#about to read 3, iclass 36, count 2 2006.201.09:13:31.06#ibcon#read 3, iclass 36, count 2 2006.201.09:13:31.06#ibcon#about to read 4, iclass 36, count 2 2006.201.09:13:31.06#ibcon#read 4, iclass 36, count 2 2006.201.09:13:31.06#ibcon#about to read 5, iclass 36, count 2 2006.201.09:13:31.06#ibcon#read 5, iclass 36, count 2 2006.201.09:13:31.06#ibcon#about to read 6, iclass 36, count 2 2006.201.09:13:31.06#ibcon#read 6, iclass 36, count 2 2006.201.09:13:31.06#ibcon#end of sib2, iclass 36, count 2 2006.201.09:13:31.06#ibcon#*mode == 0, iclass 36, count 2 2006.201.09:13:31.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.09:13:31.06#ibcon#[25=AT07-05\r\n] 2006.201.09:13:31.06#ibcon#*before write, iclass 36, count 2 2006.201.09:13:31.06#ibcon#enter sib2, iclass 36, count 2 2006.201.09:13:31.06#ibcon#flushed, iclass 36, count 2 2006.201.09:13:31.06#ibcon#about to write, iclass 36, count 2 2006.201.09:13:31.06#ibcon#wrote, iclass 36, count 2 2006.201.09:13:31.06#ibcon#about to read 3, iclass 36, count 2 2006.201.09:13:31.09#ibcon#read 3, iclass 36, count 2 2006.201.09:13:31.09#ibcon#about to read 4, iclass 36, count 2 2006.201.09:13:31.09#ibcon#read 4, iclass 36, count 2 2006.201.09:13:31.09#ibcon#about to read 5, iclass 36, count 2 2006.201.09:13:31.09#ibcon#read 5, iclass 36, count 2 2006.201.09:13:31.09#ibcon#about to read 6, iclass 36, count 2 2006.201.09:13:31.09#ibcon#read 6, iclass 36, count 2 2006.201.09:13:31.09#ibcon#end of sib2, iclass 36, count 2 2006.201.09:13:31.09#ibcon#*after write, iclass 36, count 2 2006.201.09:13:31.09#ibcon#*before return 0, iclass 36, count 2 2006.201.09:13:31.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:31.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:31.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.09:13:31.09#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:31.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:31.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:31.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:31.21#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:13:31.21#ibcon#first serial, iclass 36, count 0 2006.201.09:13:31.21#ibcon#enter sib2, iclass 36, count 0 2006.201.09:13:31.21#ibcon#flushed, iclass 36, count 0 2006.201.09:13:31.21#ibcon#about to write, iclass 36, count 0 2006.201.09:13:31.21#ibcon#wrote, iclass 36, count 0 2006.201.09:13:31.21#ibcon#about to read 3, iclass 36, count 0 2006.201.09:13:31.23#ibcon#read 3, iclass 36, count 0 2006.201.09:13:31.23#ibcon#about to read 4, iclass 36, count 0 2006.201.09:13:31.23#ibcon#read 4, iclass 36, count 0 2006.201.09:13:31.23#ibcon#about to read 5, iclass 36, count 0 2006.201.09:13:31.23#ibcon#read 5, iclass 36, count 0 2006.201.09:13:31.23#ibcon#about to read 6, iclass 36, count 0 2006.201.09:13:31.23#ibcon#read 6, iclass 36, count 0 2006.201.09:13:31.23#ibcon#end of sib2, iclass 36, count 0 2006.201.09:13:31.23#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:13:31.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:13:31.23#ibcon#[25=USB\r\n] 2006.201.09:13:31.23#ibcon#*before write, iclass 36, count 0 2006.201.09:13:31.23#ibcon#enter sib2, iclass 36, count 0 2006.201.09:13:31.23#ibcon#flushed, iclass 36, count 0 2006.201.09:13:31.23#ibcon#about to write, iclass 36, count 0 2006.201.09:13:31.23#ibcon#wrote, iclass 36, count 0 2006.201.09:13:31.23#ibcon#about to read 3, iclass 36, count 0 2006.201.09:13:31.26#ibcon#read 3, iclass 36, count 0 2006.201.09:13:31.26#ibcon#about to read 4, iclass 36, count 0 2006.201.09:13:31.26#ibcon#read 4, iclass 36, count 0 2006.201.09:13:31.26#ibcon#about to read 5, iclass 36, count 0 2006.201.09:13:31.26#ibcon#read 5, iclass 36, count 0 2006.201.09:13:31.26#ibcon#about to read 6, iclass 36, count 0 2006.201.09:13:31.26#ibcon#read 6, iclass 36, count 0 2006.201.09:13:31.26#ibcon#end of sib2, iclass 36, count 0 2006.201.09:13:31.26#ibcon#*after write, iclass 36, count 0 2006.201.09:13:31.26#ibcon#*before return 0, iclass 36, count 0 2006.201.09:13:31.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:31.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:31.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:13:31.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:13:31.26$vck44/valo=8,884.99 2006.201.09:13:31.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.09:13:31.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.09:13:31.26#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:31.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:31.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:31.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:31.26#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:13:31.26#ibcon#first serial, iclass 38, count 0 2006.201.09:13:31.26#ibcon#enter sib2, iclass 38, count 0 2006.201.09:13:31.26#ibcon#flushed, iclass 38, count 0 2006.201.09:13:31.26#ibcon#about to write, iclass 38, count 0 2006.201.09:13:31.26#ibcon#wrote, iclass 38, count 0 2006.201.09:13:31.26#ibcon#about to read 3, iclass 38, count 0 2006.201.09:13:31.28#ibcon#read 3, iclass 38, count 0 2006.201.09:13:31.28#ibcon#about to read 4, iclass 38, count 0 2006.201.09:13:31.28#ibcon#read 4, iclass 38, count 0 2006.201.09:13:31.28#ibcon#about to read 5, iclass 38, count 0 2006.201.09:13:31.28#ibcon#read 5, iclass 38, count 0 2006.201.09:13:31.28#ibcon#about to read 6, iclass 38, count 0 2006.201.09:13:31.28#ibcon#read 6, iclass 38, count 0 2006.201.09:13:31.28#ibcon#end of sib2, iclass 38, count 0 2006.201.09:13:31.28#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:13:31.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:13:31.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:13:31.28#ibcon#*before write, iclass 38, count 0 2006.201.09:13:31.28#ibcon#enter sib2, iclass 38, count 0 2006.201.09:13:31.28#ibcon#flushed, iclass 38, count 0 2006.201.09:13:31.28#ibcon#about to write, iclass 38, count 0 2006.201.09:13:31.28#ibcon#wrote, iclass 38, count 0 2006.201.09:13:31.28#ibcon#about to read 3, iclass 38, count 0 2006.201.09:13:31.32#ibcon#read 3, iclass 38, count 0 2006.201.09:13:31.32#ibcon#about to read 4, iclass 38, count 0 2006.201.09:13:31.32#ibcon#read 4, iclass 38, count 0 2006.201.09:13:31.32#ibcon#about to read 5, iclass 38, count 0 2006.201.09:13:31.32#ibcon#read 5, iclass 38, count 0 2006.201.09:13:31.32#ibcon#about to read 6, iclass 38, count 0 2006.201.09:13:31.32#ibcon#read 6, iclass 38, count 0 2006.201.09:13:31.32#ibcon#end of sib2, iclass 38, count 0 2006.201.09:13:31.32#ibcon#*after write, iclass 38, count 0 2006.201.09:13:31.32#ibcon#*before return 0, iclass 38, count 0 2006.201.09:13:31.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:31.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:31.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:13:31.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:13:31.32$vck44/va=8,4 2006.201.09:13:31.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.09:13:31.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.09:13:31.32#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:31.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:13:31.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:13:31.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:13:31.38#ibcon#enter wrdev, iclass 40, count 2 2006.201.09:13:31.38#ibcon#first serial, iclass 40, count 2 2006.201.09:13:31.38#ibcon#enter sib2, iclass 40, count 2 2006.201.09:13:31.38#ibcon#flushed, iclass 40, count 2 2006.201.09:13:31.38#ibcon#about to write, iclass 40, count 2 2006.201.09:13:31.38#ibcon#wrote, iclass 40, count 2 2006.201.09:13:31.38#ibcon#about to read 3, iclass 40, count 2 2006.201.09:13:31.40#ibcon#read 3, iclass 40, count 2 2006.201.09:13:31.40#ibcon#about to read 4, iclass 40, count 2 2006.201.09:13:31.40#ibcon#read 4, iclass 40, count 2 2006.201.09:13:31.40#ibcon#about to read 5, iclass 40, count 2 2006.201.09:13:31.40#ibcon#read 5, iclass 40, count 2 2006.201.09:13:31.40#ibcon#about to read 6, iclass 40, count 2 2006.201.09:13:31.40#ibcon#read 6, iclass 40, count 2 2006.201.09:13:31.40#ibcon#end of sib2, iclass 40, count 2 2006.201.09:13:31.40#ibcon#*mode == 0, iclass 40, count 2 2006.201.09:13:31.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.09:13:31.40#ibcon#[25=AT08-04\r\n] 2006.201.09:13:31.40#ibcon#*before write, iclass 40, count 2 2006.201.09:13:31.40#ibcon#enter sib2, iclass 40, count 2 2006.201.09:13:31.40#ibcon#flushed, iclass 40, count 2 2006.201.09:13:31.40#ibcon#about to write, iclass 40, count 2 2006.201.09:13:31.40#ibcon#wrote, iclass 40, count 2 2006.201.09:13:31.40#ibcon#about to read 3, iclass 40, count 2 2006.201.09:13:31.43#ibcon#read 3, iclass 40, count 2 2006.201.09:13:31.43#ibcon#about to read 4, iclass 40, count 2 2006.201.09:13:31.43#ibcon#read 4, iclass 40, count 2 2006.201.09:13:31.43#ibcon#about to read 5, iclass 40, count 2 2006.201.09:13:31.43#ibcon#read 5, iclass 40, count 2 2006.201.09:13:31.43#ibcon#about to read 6, iclass 40, count 2 2006.201.09:13:31.43#ibcon#read 6, iclass 40, count 2 2006.201.09:13:31.43#ibcon#end of sib2, iclass 40, count 2 2006.201.09:13:31.43#ibcon#*after write, iclass 40, count 2 2006.201.09:13:31.43#ibcon#*before return 0, iclass 40, count 2 2006.201.09:13:31.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:13:31.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:13:31.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.09:13:31.43#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:31.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:13:31.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:13:31.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:13:31.55#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:13:31.55#ibcon#first serial, iclass 40, count 0 2006.201.09:13:31.55#ibcon#enter sib2, iclass 40, count 0 2006.201.09:13:31.55#ibcon#flushed, iclass 40, count 0 2006.201.09:13:31.55#ibcon#about to write, iclass 40, count 0 2006.201.09:13:31.55#ibcon#wrote, iclass 40, count 0 2006.201.09:13:31.55#ibcon#about to read 3, iclass 40, count 0 2006.201.09:13:31.57#ibcon#read 3, iclass 40, count 0 2006.201.09:13:31.57#ibcon#about to read 4, iclass 40, count 0 2006.201.09:13:31.57#ibcon#read 4, iclass 40, count 0 2006.201.09:13:31.57#ibcon#about to read 5, iclass 40, count 0 2006.201.09:13:31.57#ibcon#read 5, iclass 40, count 0 2006.201.09:13:31.57#ibcon#about to read 6, iclass 40, count 0 2006.201.09:13:31.57#ibcon#read 6, iclass 40, count 0 2006.201.09:13:31.57#ibcon#end of sib2, iclass 40, count 0 2006.201.09:13:31.57#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:13:31.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:13:31.57#ibcon#[25=USB\r\n] 2006.201.09:13:31.57#ibcon#*before write, iclass 40, count 0 2006.201.09:13:31.57#ibcon#enter sib2, iclass 40, count 0 2006.201.09:13:31.57#ibcon#flushed, iclass 40, count 0 2006.201.09:13:31.57#ibcon#about to write, iclass 40, count 0 2006.201.09:13:31.57#ibcon#wrote, iclass 40, count 0 2006.201.09:13:31.57#ibcon#about to read 3, iclass 40, count 0 2006.201.09:13:31.60#ibcon#read 3, iclass 40, count 0 2006.201.09:13:31.60#ibcon#about to read 4, iclass 40, count 0 2006.201.09:13:31.60#ibcon#read 4, iclass 40, count 0 2006.201.09:13:31.60#ibcon#about to read 5, iclass 40, count 0 2006.201.09:13:31.60#ibcon#read 5, iclass 40, count 0 2006.201.09:13:31.60#ibcon#about to read 6, iclass 40, count 0 2006.201.09:13:31.60#ibcon#read 6, iclass 40, count 0 2006.201.09:13:31.60#ibcon#end of sib2, iclass 40, count 0 2006.201.09:13:31.60#ibcon#*after write, iclass 40, count 0 2006.201.09:13:31.60#ibcon#*before return 0, iclass 40, count 0 2006.201.09:13:31.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:13:31.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:13:31.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:13:31.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:13:31.60$vck44/vblo=1,629.99 2006.201.09:13:31.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.09:13:31.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.09:13:31.60#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:31.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:13:31.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:13:31.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:13:31.60#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:13:31.60#ibcon#first serial, iclass 4, count 0 2006.201.09:13:31.60#ibcon#enter sib2, iclass 4, count 0 2006.201.09:13:31.60#ibcon#flushed, iclass 4, count 0 2006.201.09:13:31.60#ibcon#about to write, iclass 4, count 0 2006.201.09:13:31.60#ibcon#wrote, iclass 4, count 0 2006.201.09:13:31.60#ibcon#about to read 3, iclass 4, count 0 2006.201.09:13:31.62#ibcon#read 3, iclass 4, count 0 2006.201.09:13:31.62#ibcon#about to read 4, iclass 4, count 0 2006.201.09:13:31.62#ibcon#read 4, iclass 4, count 0 2006.201.09:13:31.62#ibcon#about to read 5, iclass 4, count 0 2006.201.09:13:31.62#ibcon#read 5, iclass 4, count 0 2006.201.09:13:31.62#ibcon#about to read 6, iclass 4, count 0 2006.201.09:13:31.62#ibcon#read 6, iclass 4, count 0 2006.201.09:13:31.62#ibcon#end of sib2, iclass 4, count 0 2006.201.09:13:31.62#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:13:31.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:13:31.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:13:31.62#ibcon#*before write, iclass 4, count 0 2006.201.09:13:31.62#ibcon#enter sib2, iclass 4, count 0 2006.201.09:13:31.62#ibcon#flushed, iclass 4, count 0 2006.201.09:13:31.62#ibcon#about to write, iclass 4, count 0 2006.201.09:13:31.62#ibcon#wrote, iclass 4, count 0 2006.201.09:13:31.62#ibcon#about to read 3, iclass 4, count 0 2006.201.09:13:31.66#ibcon#read 3, iclass 4, count 0 2006.201.09:13:31.66#ibcon#about to read 4, iclass 4, count 0 2006.201.09:13:31.66#ibcon#read 4, iclass 4, count 0 2006.201.09:13:31.66#ibcon#about to read 5, iclass 4, count 0 2006.201.09:13:31.66#ibcon#read 5, iclass 4, count 0 2006.201.09:13:31.66#ibcon#about to read 6, iclass 4, count 0 2006.201.09:13:31.66#ibcon#read 6, iclass 4, count 0 2006.201.09:13:31.66#ibcon#end of sib2, iclass 4, count 0 2006.201.09:13:31.66#ibcon#*after write, iclass 4, count 0 2006.201.09:13:31.66#ibcon#*before return 0, iclass 4, count 0 2006.201.09:13:31.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:13:31.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:13:31.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:13:31.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:13:31.66$vck44/vb=1,4 2006.201.09:13:31.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.09:13:31.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.09:13:31.66#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:31.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:13:31.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:13:31.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:13:31.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.09:13:31.66#ibcon#first serial, iclass 6, count 2 2006.201.09:13:31.66#ibcon#enter sib2, iclass 6, count 2 2006.201.09:13:31.66#ibcon#flushed, iclass 6, count 2 2006.201.09:13:31.66#ibcon#about to write, iclass 6, count 2 2006.201.09:13:31.66#ibcon#wrote, iclass 6, count 2 2006.201.09:13:31.66#ibcon#about to read 3, iclass 6, count 2 2006.201.09:13:31.68#ibcon#read 3, iclass 6, count 2 2006.201.09:13:31.68#ibcon#about to read 4, iclass 6, count 2 2006.201.09:13:31.68#ibcon#read 4, iclass 6, count 2 2006.201.09:13:31.68#ibcon#about to read 5, iclass 6, count 2 2006.201.09:13:31.68#ibcon#read 5, iclass 6, count 2 2006.201.09:13:31.68#ibcon#about to read 6, iclass 6, count 2 2006.201.09:13:31.68#ibcon#read 6, iclass 6, count 2 2006.201.09:13:31.68#ibcon#end of sib2, iclass 6, count 2 2006.201.09:13:31.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.09:13:31.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.09:13:31.68#ibcon#[27=AT01-04\r\n] 2006.201.09:13:31.68#ibcon#*before write, iclass 6, count 2 2006.201.09:13:31.68#ibcon#enter sib2, iclass 6, count 2 2006.201.09:13:31.68#ibcon#flushed, iclass 6, count 2 2006.201.09:13:31.68#ibcon#about to write, iclass 6, count 2 2006.201.09:13:31.68#ibcon#wrote, iclass 6, count 2 2006.201.09:13:31.68#ibcon#about to read 3, iclass 6, count 2 2006.201.09:13:31.71#ibcon#read 3, iclass 6, count 2 2006.201.09:13:31.71#ibcon#about to read 4, iclass 6, count 2 2006.201.09:13:31.71#ibcon#read 4, iclass 6, count 2 2006.201.09:13:31.71#ibcon#about to read 5, iclass 6, count 2 2006.201.09:13:31.71#ibcon#read 5, iclass 6, count 2 2006.201.09:13:31.71#ibcon#about to read 6, iclass 6, count 2 2006.201.09:13:31.71#ibcon#read 6, iclass 6, count 2 2006.201.09:13:31.71#ibcon#end of sib2, iclass 6, count 2 2006.201.09:13:31.71#ibcon#*after write, iclass 6, count 2 2006.201.09:13:31.71#ibcon#*before return 0, iclass 6, count 2 2006.201.09:13:31.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:13:31.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:13:31.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.09:13:31.71#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:31.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:13:31.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:13:31.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:13:31.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:13:31.83#ibcon#first serial, iclass 6, count 0 2006.201.09:13:31.83#ibcon#enter sib2, iclass 6, count 0 2006.201.09:13:31.83#ibcon#flushed, iclass 6, count 0 2006.201.09:13:31.83#ibcon#about to write, iclass 6, count 0 2006.201.09:13:31.83#ibcon#wrote, iclass 6, count 0 2006.201.09:13:31.83#ibcon#about to read 3, iclass 6, count 0 2006.201.09:13:31.85#ibcon#read 3, iclass 6, count 0 2006.201.09:13:31.85#ibcon#about to read 4, iclass 6, count 0 2006.201.09:13:31.85#ibcon#read 4, iclass 6, count 0 2006.201.09:13:31.85#ibcon#about to read 5, iclass 6, count 0 2006.201.09:13:31.85#ibcon#read 5, iclass 6, count 0 2006.201.09:13:31.85#ibcon#about to read 6, iclass 6, count 0 2006.201.09:13:31.85#ibcon#read 6, iclass 6, count 0 2006.201.09:13:31.85#ibcon#end of sib2, iclass 6, count 0 2006.201.09:13:31.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:13:31.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:13:31.85#ibcon#[27=USB\r\n] 2006.201.09:13:31.85#ibcon#*before write, iclass 6, count 0 2006.201.09:13:31.85#ibcon#enter sib2, iclass 6, count 0 2006.201.09:13:31.85#ibcon#flushed, iclass 6, count 0 2006.201.09:13:31.85#ibcon#about to write, iclass 6, count 0 2006.201.09:13:31.85#ibcon#wrote, iclass 6, count 0 2006.201.09:13:31.85#ibcon#about to read 3, iclass 6, count 0 2006.201.09:13:31.88#ibcon#read 3, iclass 6, count 0 2006.201.09:13:31.88#ibcon#about to read 4, iclass 6, count 0 2006.201.09:13:31.88#ibcon#read 4, iclass 6, count 0 2006.201.09:13:31.88#ibcon#about to read 5, iclass 6, count 0 2006.201.09:13:31.88#ibcon#read 5, iclass 6, count 0 2006.201.09:13:31.88#ibcon#about to read 6, iclass 6, count 0 2006.201.09:13:31.88#ibcon#read 6, iclass 6, count 0 2006.201.09:13:31.88#ibcon#end of sib2, iclass 6, count 0 2006.201.09:13:31.88#ibcon#*after write, iclass 6, count 0 2006.201.09:13:31.88#ibcon#*before return 0, iclass 6, count 0 2006.201.09:13:31.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:13:31.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:13:31.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:13:31.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:13:31.88$vck44/vblo=2,634.99 2006.201.09:13:31.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.09:13:31.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.09:13:31.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:31.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:31.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:31.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:31.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:13:31.88#ibcon#first serial, iclass 10, count 0 2006.201.09:13:31.88#ibcon#enter sib2, iclass 10, count 0 2006.201.09:13:31.88#ibcon#flushed, iclass 10, count 0 2006.201.09:13:31.88#ibcon#about to write, iclass 10, count 0 2006.201.09:13:31.88#ibcon#wrote, iclass 10, count 0 2006.201.09:13:31.88#ibcon#about to read 3, iclass 10, count 0 2006.201.09:13:31.90#ibcon#read 3, iclass 10, count 0 2006.201.09:13:31.90#ibcon#about to read 4, iclass 10, count 0 2006.201.09:13:31.90#ibcon#read 4, iclass 10, count 0 2006.201.09:13:31.90#ibcon#about to read 5, iclass 10, count 0 2006.201.09:13:31.90#ibcon#read 5, iclass 10, count 0 2006.201.09:13:31.90#ibcon#about to read 6, iclass 10, count 0 2006.201.09:13:31.90#ibcon#read 6, iclass 10, count 0 2006.201.09:13:31.90#ibcon#end of sib2, iclass 10, count 0 2006.201.09:13:31.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:13:31.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:13:31.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:13:31.90#ibcon#*before write, iclass 10, count 0 2006.201.09:13:31.90#ibcon#enter sib2, iclass 10, count 0 2006.201.09:13:31.90#ibcon#flushed, iclass 10, count 0 2006.201.09:13:31.90#ibcon#about to write, iclass 10, count 0 2006.201.09:13:31.90#ibcon#wrote, iclass 10, count 0 2006.201.09:13:31.90#ibcon#about to read 3, iclass 10, count 0 2006.201.09:13:31.94#ibcon#read 3, iclass 10, count 0 2006.201.09:13:31.94#ibcon#about to read 4, iclass 10, count 0 2006.201.09:13:31.94#ibcon#read 4, iclass 10, count 0 2006.201.09:13:31.94#ibcon#about to read 5, iclass 10, count 0 2006.201.09:13:31.94#ibcon#read 5, iclass 10, count 0 2006.201.09:13:31.94#ibcon#about to read 6, iclass 10, count 0 2006.201.09:13:31.94#ibcon#read 6, iclass 10, count 0 2006.201.09:13:31.94#ibcon#end of sib2, iclass 10, count 0 2006.201.09:13:31.94#ibcon#*after write, iclass 10, count 0 2006.201.09:13:31.94#ibcon#*before return 0, iclass 10, count 0 2006.201.09:13:31.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:31.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:13:31.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:13:31.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:13:31.94$vck44/vb=2,5 2006.201.09:13:31.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.09:13:31.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.09:13:31.94#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:31.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:32.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:32.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:32.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.09:13:32.00#ibcon#first serial, iclass 12, count 2 2006.201.09:13:32.00#ibcon#enter sib2, iclass 12, count 2 2006.201.09:13:32.00#ibcon#flushed, iclass 12, count 2 2006.201.09:13:32.00#ibcon#about to write, iclass 12, count 2 2006.201.09:13:32.00#ibcon#wrote, iclass 12, count 2 2006.201.09:13:32.00#ibcon#about to read 3, iclass 12, count 2 2006.201.09:13:32.02#ibcon#read 3, iclass 12, count 2 2006.201.09:13:32.02#ibcon#about to read 4, iclass 12, count 2 2006.201.09:13:32.02#ibcon#read 4, iclass 12, count 2 2006.201.09:13:32.02#ibcon#about to read 5, iclass 12, count 2 2006.201.09:13:32.02#ibcon#read 5, iclass 12, count 2 2006.201.09:13:32.02#ibcon#about to read 6, iclass 12, count 2 2006.201.09:13:32.02#ibcon#read 6, iclass 12, count 2 2006.201.09:13:32.02#ibcon#end of sib2, iclass 12, count 2 2006.201.09:13:32.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.09:13:32.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.09:13:32.02#ibcon#[27=AT02-05\r\n] 2006.201.09:13:32.02#ibcon#*before write, iclass 12, count 2 2006.201.09:13:32.02#ibcon#enter sib2, iclass 12, count 2 2006.201.09:13:32.02#ibcon#flushed, iclass 12, count 2 2006.201.09:13:32.02#ibcon#about to write, iclass 12, count 2 2006.201.09:13:32.02#ibcon#wrote, iclass 12, count 2 2006.201.09:13:32.02#ibcon#about to read 3, iclass 12, count 2 2006.201.09:13:32.05#ibcon#read 3, iclass 12, count 2 2006.201.09:13:32.05#ibcon#about to read 4, iclass 12, count 2 2006.201.09:13:32.05#ibcon#read 4, iclass 12, count 2 2006.201.09:13:32.05#ibcon#about to read 5, iclass 12, count 2 2006.201.09:13:32.05#ibcon#read 5, iclass 12, count 2 2006.201.09:13:32.05#ibcon#about to read 6, iclass 12, count 2 2006.201.09:13:32.05#ibcon#read 6, iclass 12, count 2 2006.201.09:13:32.05#ibcon#end of sib2, iclass 12, count 2 2006.201.09:13:32.05#ibcon#*after write, iclass 12, count 2 2006.201.09:13:32.05#ibcon#*before return 0, iclass 12, count 2 2006.201.09:13:32.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:32.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:13:32.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.09:13:32.05#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:32.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:32.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:32.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:32.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:13:32.17#ibcon#first serial, iclass 12, count 0 2006.201.09:13:32.17#ibcon#enter sib2, iclass 12, count 0 2006.201.09:13:32.17#ibcon#flushed, iclass 12, count 0 2006.201.09:13:32.17#ibcon#about to write, iclass 12, count 0 2006.201.09:13:32.17#ibcon#wrote, iclass 12, count 0 2006.201.09:13:32.17#ibcon#about to read 3, iclass 12, count 0 2006.201.09:13:32.19#ibcon#read 3, iclass 12, count 0 2006.201.09:13:32.19#ibcon#about to read 4, iclass 12, count 0 2006.201.09:13:32.19#ibcon#read 4, iclass 12, count 0 2006.201.09:13:32.19#ibcon#about to read 5, iclass 12, count 0 2006.201.09:13:32.19#ibcon#read 5, iclass 12, count 0 2006.201.09:13:32.19#ibcon#about to read 6, iclass 12, count 0 2006.201.09:13:32.19#ibcon#read 6, iclass 12, count 0 2006.201.09:13:32.19#ibcon#end of sib2, iclass 12, count 0 2006.201.09:13:32.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:13:32.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:13:32.19#ibcon#[27=USB\r\n] 2006.201.09:13:32.19#ibcon#*before write, iclass 12, count 0 2006.201.09:13:32.19#ibcon#enter sib2, iclass 12, count 0 2006.201.09:13:32.19#ibcon#flushed, iclass 12, count 0 2006.201.09:13:32.19#ibcon#about to write, iclass 12, count 0 2006.201.09:13:32.19#ibcon#wrote, iclass 12, count 0 2006.201.09:13:32.19#ibcon#about to read 3, iclass 12, count 0 2006.201.09:13:32.22#ibcon#read 3, iclass 12, count 0 2006.201.09:13:32.22#ibcon#about to read 4, iclass 12, count 0 2006.201.09:13:32.22#ibcon#read 4, iclass 12, count 0 2006.201.09:13:32.22#ibcon#about to read 5, iclass 12, count 0 2006.201.09:13:32.22#ibcon#read 5, iclass 12, count 0 2006.201.09:13:32.22#ibcon#about to read 6, iclass 12, count 0 2006.201.09:13:32.22#ibcon#read 6, iclass 12, count 0 2006.201.09:13:32.22#ibcon#end of sib2, iclass 12, count 0 2006.201.09:13:32.22#ibcon#*after write, iclass 12, count 0 2006.201.09:13:32.22#ibcon#*before return 0, iclass 12, count 0 2006.201.09:13:32.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:32.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:13:32.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:13:32.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:13:32.22$vck44/vblo=3,649.99 2006.201.09:13:32.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.09:13:32.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.09:13:32.22#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:32.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:32.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:32.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:32.22#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:13:32.22#ibcon#first serial, iclass 14, count 0 2006.201.09:13:32.22#ibcon#enter sib2, iclass 14, count 0 2006.201.09:13:32.22#ibcon#flushed, iclass 14, count 0 2006.201.09:13:32.22#ibcon#about to write, iclass 14, count 0 2006.201.09:13:32.22#ibcon#wrote, iclass 14, count 0 2006.201.09:13:32.22#ibcon#about to read 3, iclass 14, count 0 2006.201.09:13:32.24#ibcon#read 3, iclass 14, count 0 2006.201.09:13:32.24#ibcon#about to read 4, iclass 14, count 0 2006.201.09:13:32.24#ibcon#read 4, iclass 14, count 0 2006.201.09:13:32.24#ibcon#about to read 5, iclass 14, count 0 2006.201.09:13:32.24#ibcon#read 5, iclass 14, count 0 2006.201.09:13:32.24#ibcon#about to read 6, iclass 14, count 0 2006.201.09:13:32.24#ibcon#read 6, iclass 14, count 0 2006.201.09:13:32.24#ibcon#end of sib2, iclass 14, count 0 2006.201.09:13:32.24#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:13:32.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:13:32.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:13:32.24#ibcon#*before write, iclass 14, count 0 2006.201.09:13:32.24#ibcon#enter sib2, iclass 14, count 0 2006.201.09:13:32.24#ibcon#flushed, iclass 14, count 0 2006.201.09:13:32.24#ibcon#about to write, iclass 14, count 0 2006.201.09:13:32.24#ibcon#wrote, iclass 14, count 0 2006.201.09:13:32.24#ibcon#about to read 3, iclass 14, count 0 2006.201.09:13:32.28#ibcon#read 3, iclass 14, count 0 2006.201.09:13:32.28#ibcon#about to read 4, iclass 14, count 0 2006.201.09:13:32.28#ibcon#read 4, iclass 14, count 0 2006.201.09:13:32.28#ibcon#about to read 5, iclass 14, count 0 2006.201.09:13:32.28#ibcon#read 5, iclass 14, count 0 2006.201.09:13:32.28#ibcon#about to read 6, iclass 14, count 0 2006.201.09:13:32.28#ibcon#read 6, iclass 14, count 0 2006.201.09:13:32.28#ibcon#end of sib2, iclass 14, count 0 2006.201.09:13:32.28#ibcon#*after write, iclass 14, count 0 2006.201.09:13:32.28#ibcon#*before return 0, iclass 14, count 0 2006.201.09:13:32.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:32.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:13:32.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:13:32.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:13:32.28$vck44/vb=3,4 2006.201.09:13:32.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.09:13:32.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.09:13:32.28#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:32.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:32.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:32.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:32.34#ibcon#enter wrdev, iclass 16, count 2 2006.201.09:13:32.34#ibcon#first serial, iclass 16, count 2 2006.201.09:13:32.34#ibcon#enter sib2, iclass 16, count 2 2006.201.09:13:32.34#ibcon#flushed, iclass 16, count 2 2006.201.09:13:32.34#ibcon#about to write, iclass 16, count 2 2006.201.09:13:32.34#ibcon#wrote, iclass 16, count 2 2006.201.09:13:32.34#ibcon#about to read 3, iclass 16, count 2 2006.201.09:13:32.36#ibcon#read 3, iclass 16, count 2 2006.201.09:13:32.36#ibcon#about to read 4, iclass 16, count 2 2006.201.09:13:32.36#ibcon#read 4, iclass 16, count 2 2006.201.09:13:32.36#ibcon#about to read 5, iclass 16, count 2 2006.201.09:13:32.36#ibcon#read 5, iclass 16, count 2 2006.201.09:13:32.36#ibcon#about to read 6, iclass 16, count 2 2006.201.09:13:32.36#ibcon#read 6, iclass 16, count 2 2006.201.09:13:32.36#ibcon#end of sib2, iclass 16, count 2 2006.201.09:13:32.36#ibcon#*mode == 0, iclass 16, count 2 2006.201.09:13:32.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.09:13:32.36#ibcon#[27=AT03-04\r\n] 2006.201.09:13:32.36#ibcon#*before write, iclass 16, count 2 2006.201.09:13:32.36#ibcon#enter sib2, iclass 16, count 2 2006.201.09:13:32.36#ibcon#flushed, iclass 16, count 2 2006.201.09:13:32.36#ibcon#about to write, iclass 16, count 2 2006.201.09:13:32.36#ibcon#wrote, iclass 16, count 2 2006.201.09:13:32.36#ibcon#about to read 3, iclass 16, count 2 2006.201.09:13:32.39#ibcon#read 3, iclass 16, count 2 2006.201.09:13:32.39#ibcon#about to read 4, iclass 16, count 2 2006.201.09:13:32.39#ibcon#read 4, iclass 16, count 2 2006.201.09:13:32.39#ibcon#about to read 5, iclass 16, count 2 2006.201.09:13:32.39#ibcon#read 5, iclass 16, count 2 2006.201.09:13:32.39#ibcon#about to read 6, iclass 16, count 2 2006.201.09:13:32.39#ibcon#read 6, iclass 16, count 2 2006.201.09:13:32.39#ibcon#end of sib2, iclass 16, count 2 2006.201.09:13:32.39#ibcon#*after write, iclass 16, count 2 2006.201.09:13:32.39#ibcon#*before return 0, iclass 16, count 2 2006.201.09:13:32.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:32.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:13:32.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.09:13:32.39#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:32.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:32.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:32.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:32.51#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:13:32.51#ibcon#first serial, iclass 16, count 0 2006.201.09:13:32.51#ibcon#enter sib2, iclass 16, count 0 2006.201.09:13:32.51#ibcon#flushed, iclass 16, count 0 2006.201.09:13:32.51#ibcon#about to write, iclass 16, count 0 2006.201.09:13:32.51#ibcon#wrote, iclass 16, count 0 2006.201.09:13:32.51#ibcon#about to read 3, iclass 16, count 0 2006.201.09:13:32.53#ibcon#read 3, iclass 16, count 0 2006.201.09:13:32.53#ibcon#about to read 4, iclass 16, count 0 2006.201.09:13:32.53#ibcon#read 4, iclass 16, count 0 2006.201.09:13:32.53#ibcon#about to read 5, iclass 16, count 0 2006.201.09:13:32.53#ibcon#read 5, iclass 16, count 0 2006.201.09:13:32.53#ibcon#about to read 6, iclass 16, count 0 2006.201.09:13:32.53#ibcon#read 6, iclass 16, count 0 2006.201.09:13:32.53#ibcon#end of sib2, iclass 16, count 0 2006.201.09:13:32.53#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:13:32.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:13:32.53#ibcon#[27=USB\r\n] 2006.201.09:13:32.53#ibcon#*before write, iclass 16, count 0 2006.201.09:13:32.53#ibcon#enter sib2, iclass 16, count 0 2006.201.09:13:32.53#ibcon#flushed, iclass 16, count 0 2006.201.09:13:32.53#ibcon#about to write, iclass 16, count 0 2006.201.09:13:32.53#ibcon#wrote, iclass 16, count 0 2006.201.09:13:32.53#ibcon#about to read 3, iclass 16, count 0 2006.201.09:13:32.56#ibcon#read 3, iclass 16, count 0 2006.201.09:13:32.56#ibcon#about to read 4, iclass 16, count 0 2006.201.09:13:32.56#ibcon#read 4, iclass 16, count 0 2006.201.09:13:32.56#ibcon#about to read 5, iclass 16, count 0 2006.201.09:13:32.56#ibcon#read 5, iclass 16, count 0 2006.201.09:13:32.56#ibcon#about to read 6, iclass 16, count 0 2006.201.09:13:32.56#ibcon#read 6, iclass 16, count 0 2006.201.09:13:32.56#ibcon#end of sib2, iclass 16, count 0 2006.201.09:13:32.56#ibcon#*after write, iclass 16, count 0 2006.201.09:13:32.56#ibcon#*before return 0, iclass 16, count 0 2006.201.09:13:32.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:32.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:13:32.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:13:32.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:13:32.56$vck44/vblo=4,679.99 2006.201.09:13:32.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.09:13:32.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.09:13:32.56#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:32.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:32.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:32.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:32.56#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:13:32.56#ibcon#first serial, iclass 18, count 0 2006.201.09:13:32.56#ibcon#enter sib2, iclass 18, count 0 2006.201.09:13:32.56#ibcon#flushed, iclass 18, count 0 2006.201.09:13:32.56#ibcon#about to write, iclass 18, count 0 2006.201.09:13:32.56#ibcon#wrote, iclass 18, count 0 2006.201.09:13:32.56#ibcon#about to read 3, iclass 18, count 0 2006.201.09:13:32.58#ibcon#read 3, iclass 18, count 0 2006.201.09:13:32.58#ibcon#about to read 4, iclass 18, count 0 2006.201.09:13:32.58#ibcon#read 4, iclass 18, count 0 2006.201.09:13:32.58#ibcon#about to read 5, iclass 18, count 0 2006.201.09:13:32.58#ibcon#read 5, iclass 18, count 0 2006.201.09:13:32.58#ibcon#about to read 6, iclass 18, count 0 2006.201.09:13:32.58#ibcon#read 6, iclass 18, count 0 2006.201.09:13:32.58#ibcon#end of sib2, iclass 18, count 0 2006.201.09:13:32.58#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:13:32.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:13:32.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:13:32.58#ibcon#*before write, iclass 18, count 0 2006.201.09:13:32.58#ibcon#enter sib2, iclass 18, count 0 2006.201.09:13:32.58#ibcon#flushed, iclass 18, count 0 2006.201.09:13:32.58#ibcon#about to write, iclass 18, count 0 2006.201.09:13:32.58#ibcon#wrote, iclass 18, count 0 2006.201.09:13:32.58#ibcon#about to read 3, iclass 18, count 0 2006.201.09:13:32.62#ibcon#read 3, iclass 18, count 0 2006.201.09:13:32.62#ibcon#about to read 4, iclass 18, count 0 2006.201.09:13:32.62#ibcon#read 4, iclass 18, count 0 2006.201.09:13:32.62#ibcon#about to read 5, iclass 18, count 0 2006.201.09:13:32.62#ibcon#read 5, iclass 18, count 0 2006.201.09:13:32.62#ibcon#about to read 6, iclass 18, count 0 2006.201.09:13:32.62#ibcon#read 6, iclass 18, count 0 2006.201.09:13:32.62#ibcon#end of sib2, iclass 18, count 0 2006.201.09:13:32.62#ibcon#*after write, iclass 18, count 0 2006.201.09:13:32.62#ibcon#*before return 0, iclass 18, count 0 2006.201.09:13:32.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:32.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:13:32.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:13:32.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:13:32.62$vck44/vb=4,5 2006.201.09:13:32.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.09:13:32.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.09:13:32.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:32.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:32.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:32.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:32.68#ibcon#enter wrdev, iclass 20, count 2 2006.201.09:13:32.68#ibcon#first serial, iclass 20, count 2 2006.201.09:13:32.68#ibcon#enter sib2, iclass 20, count 2 2006.201.09:13:32.68#ibcon#flushed, iclass 20, count 2 2006.201.09:13:32.68#ibcon#about to write, iclass 20, count 2 2006.201.09:13:32.68#ibcon#wrote, iclass 20, count 2 2006.201.09:13:32.68#ibcon#about to read 3, iclass 20, count 2 2006.201.09:13:32.70#ibcon#read 3, iclass 20, count 2 2006.201.09:13:32.70#ibcon#about to read 4, iclass 20, count 2 2006.201.09:13:32.70#ibcon#read 4, iclass 20, count 2 2006.201.09:13:32.70#ibcon#about to read 5, iclass 20, count 2 2006.201.09:13:32.70#ibcon#read 5, iclass 20, count 2 2006.201.09:13:32.70#ibcon#about to read 6, iclass 20, count 2 2006.201.09:13:32.70#ibcon#read 6, iclass 20, count 2 2006.201.09:13:32.70#ibcon#end of sib2, iclass 20, count 2 2006.201.09:13:32.70#ibcon#*mode == 0, iclass 20, count 2 2006.201.09:13:32.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.09:13:32.70#ibcon#[27=AT04-05\r\n] 2006.201.09:13:32.70#ibcon#*before write, iclass 20, count 2 2006.201.09:13:32.70#ibcon#enter sib2, iclass 20, count 2 2006.201.09:13:32.70#ibcon#flushed, iclass 20, count 2 2006.201.09:13:32.70#ibcon#about to write, iclass 20, count 2 2006.201.09:13:32.70#ibcon#wrote, iclass 20, count 2 2006.201.09:13:32.70#ibcon#about to read 3, iclass 20, count 2 2006.201.09:13:32.73#ibcon#read 3, iclass 20, count 2 2006.201.09:13:32.73#ibcon#about to read 4, iclass 20, count 2 2006.201.09:13:32.73#ibcon#read 4, iclass 20, count 2 2006.201.09:13:32.73#ibcon#about to read 5, iclass 20, count 2 2006.201.09:13:32.73#ibcon#read 5, iclass 20, count 2 2006.201.09:13:32.73#ibcon#about to read 6, iclass 20, count 2 2006.201.09:13:32.73#ibcon#read 6, iclass 20, count 2 2006.201.09:13:32.73#ibcon#end of sib2, iclass 20, count 2 2006.201.09:13:32.73#ibcon#*after write, iclass 20, count 2 2006.201.09:13:32.73#ibcon#*before return 0, iclass 20, count 2 2006.201.09:13:32.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:32.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:13:32.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.09:13:32.73#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:32.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:32.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:32.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:32.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.09:13:32.85#ibcon#first serial, iclass 20, count 0 2006.201.09:13:32.85#ibcon#enter sib2, iclass 20, count 0 2006.201.09:13:32.85#ibcon#flushed, iclass 20, count 0 2006.201.09:13:32.85#ibcon#about to write, iclass 20, count 0 2006.201.09:13:32.85#ibcon#wrote, iclass 20, count 0 2006.201.09:13:32.85#ibcon#about to read 3, iclass 20, count 0 2006.201.09:13:32.87#ibcon#read 3, iclass 20, count 0 2006.201.09:13:32.87#ibcon#about to read 4, iclass 20, count 0 2006.201.09:13:32.87#ibcon#read 4, iclass 20, count 0 2006.201.09:13:32.87#ibcon#about to read 5, iclass 20, count 0 2006.201.09:13:32.87#ibcon#read 5, iclass 20, count 0 2006.201.09:13:32.87#ibcon#about to read 6, iclass 20, count 0 2006.201.09:13:32.87#ibcon#read 6, iclass 20, count 0 2006.201.09:13:32.87#ibcon#end of sib2, iclass 20, count 0 2006.201.09:13:32.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.09:13:32.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.09:13:32.87#ibcon#[27=USB\r\n] 2006.201.09:13:32.87#ibcon#*before write, iclass 20, count 0 2006.201.09:13:32.87#ibcon#enter sib2, iclass 20, count 0 2006.201.09:13:32.87#ibcon#flushed, iclass 20, count 0 2006.201.09:13:32.87#ibcon#about to write, iclass 20, count 0 2006.201.09:13:32.87#ibcon#wrote, iclass 20, count 0 2006.201.09:13:32.87#ibcon#about to read 3, iclass 20, count 0 2006.201.09:13:32.90#ibcon#read 3, iclass 20, count 0 2006.201.09:13:32.90#ibcon#about to read 4, iclass 20, count 0 2006.201.09:13:32.90#ibcon#read 4, iclass 20, count 0 2006.201.09:13:32.90#ibcon#about to read 5, iclass 20, count 0 2006.201.09:13:32.90#ibcon#read 5, iclass 20, count 0 2006.201.09:13:32.90#ibcon#about to read 6, iclass 20, count 0 2006.201.09:13:32.90#ibcon#read 6, iclass 20, count 0 2006.201.09:13:32.90#ibcon#end of sib2, iclass 20, count 0 2006.201.09:13:32.90#ibcon#*after write, iclass 20, count 0 2006.201.09:13:32.90#ibcon#*before return 0, iclass 20, count 0 2006.201.09:13:32.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:32.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:13:32.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.09:13:32.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.09:13:32.90$vck44/vblo=5,709.99 2006.201.09:13:32.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.09:13:32.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.09:13:32.90#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:32.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:32.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:32.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:32.90#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:13:32.90#ibcon#first serial, iclass 22, count 0 2006.201.09:13:32.90#ibcon#enter sib2, iclass 22, count 0 2006.201.09:13:32.90#ibcon#flushed, iclass 22, count 0 2006.201.09:13:32.90#ibcon#about to write, iclass 22, count 0 2006.201.09:13:32.90#ibcon#wrote, iclass 22, count 0 2006.201.09:13:32.90#ibcon#about to read 3, iclass 22, count 0 2006.201.09:13:32.92#ibcon#read 3, iclass 22, count 0 2006.201.09:13:32.92#ibcon#about to read 4, iclass 22, count 0 2006.201.09:13:32.92#ibcon#read 4, iclass 22, count 0 2006.201.09:13:32.92#ibcon#about to read 5, iclass 22, count 0 2006.201.09:13:32.92#ibcon#read 5, iclass 22, count 0 2006.201.09:13:32.92#ibcon#about to read 6, iclass 22, count 0 2006.201.09:13:32.92#ibcon#read 6, iclass 22, count 0 2006.201.09:13:32.92#ibcon#end of sib2, iclass 22, count 0 2006.201.09:13:32.92#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:13:32.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:13:32.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:13:32.92#ibcon#*before write, iclass 22, count 0 2006.201.09:13:32.92#ibcon#enter sib2, iclass 22, count 0 2006.201.09:13:32.92#ibcon#flushed, iclass 22, count 0 2006.201.09:13:32.92#ibcon#about to write, iclass 22, count 0 2006.201.09:13:32.92#ibcon#wrote, iclass 22, count 0 2006.201.09:13:32.92#ibcon#about to read 3, iclass 22, count 0 2006.201.09:13:32.96#ibcon#read 3, iclass 22, count 0 2006.201.09:13:32.96#ibcon#about to read 4, iclass 22, count 0 2006.201.09:13:32.96#ibcon#read 4, iclass 22, count 0 2006.201.09:13:32.96#ibcon#about to read 5, iclass 22, count 0 2006.201.09:13:32.96#ibcon#read 5, iclass 22, count 0 2006.201.09:13:32.96#ibcon#about to read 6, iclass 22, count 0 2006.201.09:13:32.96#ibcon#read 6, iclass 22, count 0 2006.201.09:13:32.96#ibcon#end of sib2, iclass 22, count 0 2006.201.09:13:32.96#ibcon#*after write, iclass 22, count 0 2006.201.09:13:32.96#ibcon#*before return 0, iclass 22, count 0 2006.201.09:13:32.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:32.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:13:32.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:13:32.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:13:32.96$vck44/vb=5,4 2006.201.09:13:32.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.09:13:32.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.09:13:32.96#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:32.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:33.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:33.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:33.02#ibcon#enter wrdev, iclass 24, count 2 2006.201.09:13:33.02#ibcon#first serial, iclass 24, count 2 2006.201.09:13:33.02#ibcon#enter sib2, iclass 24, count 2 2006.201.09:13:33.02#ibcon#flushed, iclass 24, count 2 2006.201.09:13:33.02#ibcon#about to write, iclass 24, count 2 2006.201.09:13:33.02#ibcon#wrote, iclass 24, count 2 2006.201.09:13:33.02#ibcon#about to read 3, iclass 24, count 2 2006.201.09:13:33.04#ibcon#read 3, iclass 24, count 2 2006.201.09:13:33.04#ibcon#about to read 4, iclass 24, count 2 2006.201.09:13:33.04#ibcon#read 4, iclass 24, count 2 2006.201.09:13:33.04#ibcon#about to read 5, iclass 24, count 2 2006.201.09:13:33.04#ibcon#read 5, iclass 24, count 2 2006.201.09:13:33.04#ibcon#about to read 6, iclass 24, count 2 2006.201.09:13:33.04#ibcon#read 6, iclass 24, count 2 2006.201.09:13:33.04#ibcon#end of sib2, iclass 24, count 2 2006.201.09:13:33.04#ibcon#*mode == 0, iclass 24, count 2 2006.201.09:13:33.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.09:13:33.04#ibcon#[27=AT05-04\r\n] 2006.201.09:13:33.04#ibcon#*before write, iclass 24, count 2 2006.201.09:13:33.04#ibcon#enter sib2, iclass 24, count 2 2006.201.09:13:33.04#ibcon#flushed, iclass 24, count 2 2006.201.09:13:33.04#ibcon#about to write, iclass 24, count 2 2006.201.09:13:33.04#ibcon#wrote, iclass 24, count 2 2006.201.09:13:33.04#ibcon#about to read 3, iclass 24, count 2 2006.201.09:13:33.07#ibcon#read 3, iclass 24, count 2 2006.201.09:13:33.07#ibcon#about to read 4, iclass 24, count 2 2006.201.09:13:33.07#ibcon#read 4, iclass 24, count 2 2006.201.09:13:33.07#ibcon#about to read 5, iclass 24, count 2 2006.201.09:13:33.07#ibcon#read 5, iclass 24, count 2 2006.201.09:13:33.07#ibcon#about to read 6, iclass 24, count 2 2006.201.09:13:33.07#ibcon#read 6, iclass 24, count 2 2006.201.09:13:33.07#ibcon#end of sib2, iclass 24, count 2 2006.201.09:13:33.07#ibcon#*after write, iclass 24, count 2 2006.201.09:13:33.07#ibcon#*before return 0, iclass 24, count 2 2006.201.09:13:33.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:33.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:13:33.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.09:13:33.07#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:33.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:33.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:33.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:33.19#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:13:33.19#ibcon#first serial, iclass 24, count 0 2006.201.09:13:33.19#ibcon#enter sib2, iclass 24, count 0 2006.201.09:13:33.19#ibcon#flushed, iclass 24, count 0 2006.201.09:13:33.19#ibcon#about to write, iclass 24, count 0 2006.201.09:13:33.19#ibcon#wrote, iclass 24, count 0 2006.201.09:13:33.19#ibcon#about to read 3, iclass 24, count 0 2006.201.09:13:33.21#ibcon#read 3, iclass 24, count 0 2006.201.09:13:33.21#ibcon#about to read 4, iclass 24, count 0 2006.201.09:13:33.21#ibcon#read 4, iclass 24, count 0 2006.201.09:13:33.21#ibcon#about to read 5, iclass 24, count 0 2006.201.09:13:33.21#ibcon#read 5, iclass 24, count 0 2006.201.09:13:33.21#ibcon#about to read 6, iclass 24, count 0 2006.201.09:13:33.21#ibcon#read 6, iclass 24, count 0 2006.201.09:13:33.21#ibcon#end of sib2, iclass 24, count 0 2006.201.09:13:33.21#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:13:33.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:13:33.21#ibcon#[27=USB\r\n] 2006.201.09:13:33.21#ibcon#*before write, iclass 24, count 0 2006.201.09:13:33.21#ibcon#enter sib2, iclass 24, count 0 2006.201.09:13:33.21#ibcon#flushed, iclass 24, count 0 2006.201.09:13:33.21#ibcon#about to write, iclass 24, count 0 2006.201.09:13:33.21#ibcon#wrote, iclass 24, count 0 2006.201.09:13:33.21#ibcon#about to read 3, iclass 24, count 0 2006.201.09:13:33.24#ibcon#read 3, iclass 24, count 0 2006.201.09:13:33.24#ibcon#about to read 4, iclass 24, count 0 2006.201.09:13:33.24#ibcon#read 4, iclass 24, count 0 2006.201.09:13:33.24#ibcon#about to read 5, iclass 24, count 0 2006.201.09:13:33.24#ibcon#read 5, iclass 24, count 0 2006.201.09:13:33.24#ibcon#about to read 6, iclass 24, count 0 2006.201.09:13:33.24#ibcon#read 6, iclass 24, count 0 2006.201.09:13:33.24#ibcon#end of sib2, iclass 24, count 0 2006.201.09:13:33.24#ibcon#*after write, iclass 24, count 0 2006.201.09:13:33.24#ibcon#*before return 0, iclass 24, count 0 2006.201.09:13:33.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:33.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:13:33.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:13:33.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:13:33.24$vck44/vblo=6,719.99 2006.201.09:13:33.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.09:13:33.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.09:13:33.24#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:33.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:33.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:33.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:33.24#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:13:33.24#ibcon#first serial, iclass 26, count 0 2006.201.09:13:33.24#ibcon#enter sib2, iclass 26, count 0 2006.201.09:13:33.24#ibcon#flushed, iclass 26, count 0 2006.201.09:13:33.24#ibcon#about to write, iclass 26, count 0 2006.201.09:13:33.24#ibcon#wrote, iclass 26, count 0 2006.201.09:13:33.24#ibcon#about to read 3, iclass 26, count 0 2006.201.09:13:33.26#ibcon#read 3, iclass 26, count 0 2006.201.09:13:33.26#ibcon#about to read 4, iclass 26, count 0 2006.201.09:13:33.26#ibcon#read 4, iclass 26, count 0 2006.201.09:13:33.26#ibcon#about to read 5, iclass 26, count 0 2006.201.09:13:33.26#ibcon#read 5, iclass 26, count 0 2006.201.09:13:33.26#ibcon#about to read 6, iclass 26, count 0 2006.201.09:13:33.26#ibcon#read 6, iclass 26, count 0 2006.201.09:13:33.26#ibcon#end of sib2, iclass 26, count 0 2006.201.09:13:33.26#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:13:33.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:13:33.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:13:33.26#ibcon#*before write, iclass 26, count 0 2006.201.09:13:33.26#ibcon#enter sib2, iclass 26, count 0 2006.201.09:13:33.26#ibcon#flushed, iclass 26, count 0 2006.201.09:13:33.26#ibcon#about to write, iclass 26, count 0 2006.201.09:13:33.26#ibcon#wrote, iclass 26, count 0 2006.201.09:13:33.26#ibcon#about to read 3, iclass 26, count 0 2006.201.09:13:33.30#ibcon#read 3, iclass 26, count 0 2006.201.09:13:33.30#ibcon#about to read 4, iclass 26, count 0 2006.201.09:13:33.30#ibcon#read 4, iclass 26, count 0 2006.201.09:13:33.30#ibcon#about to read 5, iclass 26, count 0 2006.201.09:13:33.30#ibcon#read 5, iclass 26, count 0 2006.201.09:13:33.30#ibcon#about to read 6, iclass 26, count 0 2006.201.09:13:33.30#ibcon#read 6, iclass 26, count 0 2006.201.09:13:33.30#ibcon#end of sib2, iclass 26, count 0 2006.201.09:13:33.30#ibcon#*after write, iclass 26, count 0 2006.201.09:13:33.30#ibcon#*before return 0, iclass 26, count 0 2006.201.09:13:33.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:33.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:13:33.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:13:33.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:13:33.30$vck44/vb=6,4 2006.201.09:13:33.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.09:13:33.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.09:13:33.30#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:33.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:33.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:33.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:33.36#ibcon#enter wrdev, iclass 28, count 2 2006.201.09:13:33.36#ibcon#first serial, iclass 28, count 2 2006.201.09:13:33.36#ibcon#enter sib2, iclass 28, count 2 2006.201.09:13:33.36#ibcon#flushed, iclass 28, count 2 2006.201.09:13:33.36#ibcon#about to write, iclass 28, count 2 2006.201.09:13:33.36#ibcon#wrote, iclass 28, count 2 2006.201.09:13:33.36#ibcon#about to read 3, iclass 28, count 2 2006.201.09:13:33.38#ibcon#read 3, iclass 28, count 2 2006.201.09:13:33.38#ibcon#about to read 4, iclass 28, count 2 2006.201.09:13:33.38#ibcon#read 4, iclass 28, count 2 2006.201.09:13:33.38#ibcon#about to read 5, iclass 28, count 2 2006.201.09:13:33.38#ibcon#read 5, iclass 28, count 2 2006.201.09:13:33.38#ibcon#about to read 6, iclass 28, count 2 2006.201.09:13:33.38#ibcon#read 6, iclass 28, count 2 2006.201.09:13:33.38#ibcon#end of sib2, iclass 28, count 2 2006.201.09:13:33.38#ibcon#*mode == 0, iclass 28, count 2 2006.201.09:13:33.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.09:13:33.38#ibcon#[27=AT06-04\r\n] 2006.201.09:13:33.38#ibcon#*before write, iclass 28, count 2 2006.201.09:13:33.38#ibcon#enter sib2, iclass 28, count 2 2006.201.09:13:33.38#ibcon#flushed, iclass 28, count 2 2006.201.09:13:33.38#ibcon#about to write, iclass 28, count 2 2006.201.09:13:33.38#ibcon#wrote, iclass 28, count 2 2006.201.09:13:33.38#ibcon#about to read 3, iclass 28, count 2 2006.201.09:13:33.41#ibcon#read 3, iclass 28, count 2 2006.201.09:13:33.41#ibcon#about to read 4, iclass 28, count 2 2006.201.09:13:33.41#ibcon#read 4, iclass 28, count 2 2006.201.09:13:33.41#ibcon#about to read 5, iclass 28, count 2 2006.201.09:13:33.41#ibcon#read 5, iclass 28, count 2 2006.201.09:13:33.41#ibcon#about to read 6, iclass 28, count 2 2006.201.09:13:33.41#ibcon#read 6, iclass 28, count 2 2006.201.09:13:33.41#ibcon#end of sib2, iclass 28, count 2 2006.201.09:13:33.41#ibcon#*after write, iclass 28, count 2 2006.201.09:13:33.41#ibcon#*before return 0, iclass 28, count 2 2006.201.09:13:33.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:33.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:13:33.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.09:13:33.41#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:33.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:33.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:33.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:33.53#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:13:33.53#ibcon#first serial, iclass 28, count 0 2006.201.09:13:33.53#ibcon#enter sib2, iclass 28, count 0 2006.201.09:13:33.53#ibcon#flushed, iclass 28, count 0 2006.201.09:13:33.53#ibcon#about to write, iclass 28, count 0 2006.201.09:13:33.53#ibcon#wrote, iclass 28, count 0 2006.201.09:13:33.53#ibcon#about to read 3, iclass 28, count 0 2006.201.09:13:33.55#ibcon#read 3, iclass 28, count 0 2006.201.09:13:33.55#ibcon#about to read 4, iclass 28, count 0 2006.201.09:13:33.55#ibcon#read 4, iclass 28, count 0 2006.201.09:13:33.55#ibcon#about to read 5, iclass 28, count 0 2006.201.09:13:33.55#ibcon#read 5, iclass 28, count 0 2006.201.09:13:33.55#ibcon#about to read 6, iclass 28, count 0 2006.201.09:13:33.55#ibcon#read 6, iclass 28, count 0 2006.201.09:13:33.55#ibcon#end of sib2, iclass 28, count 0 2006.201.09:13:33.55#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:13:33.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:13:33.55#ibcon#[27=USB\r\n] 2006.201.09:13:33.55#ibcon#*before write, iclass 28, count 0 2006.201.09:13:33.55#ibcon#enter sib2, iclass 28, count 0 2006.201.09:13:33.55#ibcon#flushed, iclass 28, count 0 2006.201.09:13:33.55#ibcon#about to write, iclass 28, count 0 2006.201.09:13:33.55#ibcon#wrote, iclass 28, count 0 2006.201.09:13:33.55#ibcon#about to read 3, iclass 28, count 0 2006.201.09:13:33.58#ibcon#read 3, iclass 28, count 0 2006.201.09:13:33.58#ibcon#about to read 4, iclass 28, count 0 2006.201.09:13:33.58#ibcon#read 4, iclass 28, count 0 2006.201.09:13:33.58#ibcon#about to read 5, iclass 28, count 0 2006.201.09:13:33.58#ibcon#read 5, iclass 28, count 0 2006.201.09:13:33.58#ibcon#about to read 6, iclass 28, count 0 2006.201.09:13:33.58#ibcon#read 6, iclass 28, count 0 2006.201.09:13:33.58#ibcon#end of sib2, iclass 28, count 0 2006.201.09:13:33.58#ibcon#*after write, iclass 28, count 0 2006.201.09:13:33.58#ibcon#*before return 0, iclass 28, count 0 2006.201.09:13:33.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:33.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:13:33.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:13:33.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:13:33.58$vck44/vblo=7,734.99 2006.201.09:13:33.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.09:13:33.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.09:13:33.58#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:33.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:33.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:33.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:33.58#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:13:33.58#ibcon#first serial, iclass 30, count 0 2006.201.09:13:33.58#ibcon#enter sib2, iclass 30, count 0 2006.201.09:13:33.58#ibcon#flushed, iclass 30, count 0 2006.201.09:13:33.58#ibcon#about to write, iclass 30, count 0 2006.201.09:13:33.58#ibcon#wrote, iclass 30, count 0 2006.201.09:13:33.58#ibcon#about to read 3, iclass 30, count 0 2006.201.09:13:33.60#ibcon#read 3, iclass 30, count 0 2006.201.09:13:33.60#ibcon#about to read 4, iclass 30, count 0 2006.201.09:13:33.60#ibcon#read 4, iclass 30, count 0 2006.201.09:13:33.60#ibcon#about to read 5, iclass 30, count 0 2006.201.09:13:33.60#ibcon#read 5, iclass 30, count 0 2006.201.09:13:33.60#ibcon#about to read 6, iclass 30, count 0 2006.201.09:13:33.60#ibcon#read 6, iclass 30, count 0 2006.201.09:13:33.60#ibcon#end of sib2, iclass 30, count 0 2006.201.09:13:33.60#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:13:33.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:13:33.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:13:33.60#ibcon#*before write, iclass 30, count 0 2006.201.09:13:33.60#ibcon#enter sib2, iclass 30, count 0 2006.201.09:13:33.60#ibcon#flushed, iclass 30, count 0 2006.201.09:13:33.60#ibcon#about to write, iclass 30, count 0 2006.201.09:13:33.60#ibcon#wrote, iclass 30, count 0 2006.201.09:13:33.60#ibcon#about to read 3, iclass 30, count 0 2006.201.09:13:33.64#ibcon#read 3, iclass 30, count 0 2006.201.09:13:33.64#ibcon#about to read 4, iclass 30, count 0 2006.201.09:13:33.64#ibcon#read 4, iclass 30, count 0 2006.201.09:13:33.64#ibcon#about to read 5, iclass 30, count 0 2006.201.09:13:33.64#ibcon#read 5, iclass 30, count 0 2006.201.09:13:33.64#ibcon#about to read 6, iclass 30, count 0 2006.201.09:13:33.64#ibcon#read 6, iclass 30, count 0 2006.201.09:13:33.64#ibcon#end of sib2, iclass 30, count 0 2006.201.09:13:33.64#ibcon#*after write, iclass 30, count 0 2006.201.09:13:33.64#ibcon#*before return 0, iclass 30, count 0 2006.201.09:13:33.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:33.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:13:33.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:13:33.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:13:33.64$vck44/vb=7,4 2006.201.09:13:33.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.09:13:33.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.09:13:33.64#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:33.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:33.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:33.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:33.70#ibcon#enter wrdev, iclass 32, count 2 2006.201.09:13:33.70#ibcon#first serial, iclass 32, count 2 2006.201.09:13:33.70#ibcon#enter sib2, iclass 32, count 2 2006.201.09:13:33.70#ibcon#flushed, iclass 32, count 2 2006.201.09:13:33.70#ibcon#about to write, iclass 32, count 2 2006.201.09:13:33.70#ibcon#wrote, iclass 32, count 2 2006.201.09:13:33.70#ibcon#about to read 3, iclass 32, count 2 2006.201.09:13:33.72#ibcon#read 3, iclass 32, count 2 2006.201.09:13:33.72#ibcon#about to read 4, iclass 32, count 2 2006.201.09:13:33.72#ibcon#read 4, iclass 32, count 2 2006.201.09:13:33.72#ibcon#about to read 5, iclass 32, count 2 2006.201.09:13:33.72#ibcon#read 5, iclass 32, count 2 2006.201.09:13:33.72#ibcon#about to read 6, iclass 32, count 2 2006.201.09:13:33.72#ibcon#read 6, iclass 32, count 2 2006.201.09:13:33.72#ibcon#end of sib2, iclass 32, count 2 2006.201.09:13:33.72#ibcon#*mode == 0, iclass 32, count 2 2006.201.09:13:33.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.09:13:33.72#ibcon#[27=AT07-04\r\n] 2006.201.09:13:33.72#ibcon#*before write, iclass 32, count 2 2006.201.09:13:33.72#ibcon#enter sib2, iclass 32, count 2 2006.201.09:13:33.72#ibcon#flushed, iclass 32, count 2 2006.201.09:13:33.72#ibcon#about to write, iclass 32, count 2 2006.201.09:13:33.72#ibcon#wrote, iclass 32, count 2 2006.201.09:13:33.72#ibcon#about to read 3, iclass 32, count 2 2006.201.09:13:33.75#ibcon#read 3, iclass 32, count 2 2006.201.09:13:33.75#ibcon#about to read 4, iclass 32, count 2 2006.201.09:13:33.75#ibcon#read 4, iclass 32, count 2 2006.201.09:13:33.75#ibcon#about to read 5, iclass 32, count 2 2006.201.09:13:33.75#ibcon#read 5, iclass 32, count 2 2006.201.09:13:33.75#ibcon#about to read 6, iclass 32, count 2 2006.201.09:13:33.75#ibcon#read 6, iclass 32, count 2 2006.201.09:13:33.75#ibcon#end of sib2, iclass 32, count 2 2006.201.09:13:33.75#ibcon#*after write, iclass 32, count 2 2006.201.09:13:33.75#ibcon#*before return 0, iclass 32, count 2 2006.201.09:13:33.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:33.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:13:33.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.09:13:33.75#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:33.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:33.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:33.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:33.87#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:13:33.87#ibcon#first serial, iclass 32, count 0 2006.201.09:13:33.87#ibcon#enter sib2, iclass 32, count 0 2006.201.09:13:33.87#ibcon#flushed, iclass 32, count 0 2006.201.09:13:33.87#ibcon#about to write, iclass 32, count 0 2006.201.09:13:33.87#ibcon#wrote, iclass 32, count 0 2006.201.09:13:33.87#ibcon#about to read 3, iclass 32, count 0 2006.201.09:13:33.89#ibcon#read 3, iclass 32, count 0 2006.201.09:13:33.89#ibcon#about to read 4, iclass 32, count 0 2006.201.09:13:33.89#ibcon#read 4, iclass 32, count 0 2006.201.09:13:33.89#ibcon#about to read 5, iclass 32, count 0 2006.201.09:13:33.89#ibcon#read 5, iclass 32, count 0 2006.201.09:13:33.89#ibcon#about to read 6, iclass 32, count 0 2006.201.09:13:33.89#ibcon#read 6, iclass 32, count 0 2006.201.09:13:33.89#ibcon#end of sib2, iclass 32, count 0 2006.201.09:13:33.89#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:13:33.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:13:33.89#ibcon#[27=USB\r\n] 2006.201.09:13:33.89#ibcon#*before write, iclass 32, count 0 2006.201.09:13:33.89#ibcon#enter sib2, iclass 32, count 0 2006.201.09:13:33.89#ibcon#flushed, iclass 32, count 0 2006.201.09:13:33.89#ibcon#about to write, iclass 32, count 0 2006.201.09:13:33.89#ibcon#wrote, iclass 32, count 0 2006.201.09:13:33.89#ibcon#about to read 3, iclass 32, count 0 2006.201.09:13:33.92#ibcon#read 3, iclass 32, count 0 2006.201.09:13:33.92#ibcon#about to read 4, iclass 32, count 0 2006.201.09:13:33.92#ibcon#read 4, iclass 32, count 0 2006.201.09:13:33.92#ibcon#about to read 5, iclass 32, count 0 2006.201.09:13:33.92#ibcon#read 5, iclass 32, count 0 2006.201.09:13:33.92#ibcon#about to read 6, iclass 32, count 0 2006.201.09:13:33.92#ibcon#read 6, iclass 32, count 0 2006.201.09:13:33.92#ibcon#end of sib2, iclass 32, count 0 2006.201.09:13:33.92#ibcon#*after write, iclass 32, count 0 2006.201.09:13:33.92#ibcon#*before return 0, iclass 32, count 0 2006.201.09:13:33.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:33.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:13:33.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:13:33.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:13:33.92$vck44/vblo=8,744.99 2006.201.09:13:33.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.09:13:33.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.09:13:33.92#ibcon#ireg 17 cls_cnt 0 2006.201.09:13:33.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:33.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:33.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:33.92#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:13:33.92#ibcon#first serial, iclass 34, count 0 2006.201.09:13:33.92#ibcon#enter sib2, iclass 34, count 0 2006.201.09:13:33.92#ibcon#flushed, iclass 34, count 0 2006.201.09:13:33.92#ibcon#about to write, iclass 34, count 0 2006.201.09:13:33.92#ibcon#wrote, iclass 34, count 0 2006.201.09:13:33.92#ibcon#about to read 3, iclass 34, count 0 2006.201.09:13:33.94#ibcon#read 3, iclass 34, count 0 2006.201.09:13:33.94#ibcon#about to read 4, iclass 34, count 0 2006.201.09:13:33.94#ibcon#read 4, iclass 34, count 0 2006.201.09:13:33.94#ibcon#about to read 5, iclass 34, count 0 2006.201.09:13:33.94#ibcon#read 5, iclass 34, count 0 2006.201.09:13:33.94#ibcon#about to read 6, iclass 34, count 0 2006.201.09:13:33.94#ibcon#read 6, iclass 34, count 0 2006.201.09:13:33.94#ibcon#end of sib2, iclass 34, count 0 2006.201.09:13:33.94#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:13:33.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:13:33.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:13:33.94#ibcon#*before write, iclass 34, count 0 2006.201.09:13:33.94#ibcon#enter sib2, iclass 34, count 0 2006.201.09:13:33.94#ibcon#flushed, iclass 34, count 0 2006.201.09:13:33.94#ibcon#about to write, iclass 34, count 0 2006.201.09:13:33.94#ibcon#wrote, iclass 34, count 0 2006.201.09:13:33.94#ibcon#about to read 3, iclass 34, count 0 2006.201.09:13:33.99#ibcon#read 3, iclass 34, count 0 2006.201.09:13:33.99#ibcon#about to read 4, iclass 34, count 0 2006.201.09:13:33.99#ibcon#read 4, iclass 34, count 0 2006.201.09:13:33.99#ibcon#about to read 5, iclass 34, count 0 2006.201.09:13:33.99#ibcon#read 5, iclass 34, count 0 2006.201.09:13:33.99#ibcon#about to read 6, iclass 34, count 0 2006.201.09:13:33.99#ibcon#read 6, iclass 34, count 0 2006.201.09:13:33.99#ibcon#end of sib2, iclass 34, count 0 2006.201.09:13:33.99#ibcon#*after write, iclass 34, count 0 2006.201.09:13:33.99#ibcon#*before return 0, iclass 34, count 0 2006.201.09:13:33.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:33.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:13:33.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:13:33.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:13:33.99$vck44/vb=8,4 2006.201.09:13:33.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.09:13:33.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.09:13:33.99#ibcon#ireg 11 cls_cnt 2 2006.201.09:13:33.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:34.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:34.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:34.04#ibcon#enter wrdev, iclass 36, count 2 2006.201.09:13:34.04#ibcon#first serial, iclass 36, count 2 2006.201.09:13:34.04#ibcon#enter sib2, iclass 36, count 2 2006.201.09:13:34.04#ibcon#flushed, iclass 36, count 2 2006.201.09:13:34.04#ibcon#about to write, iclass 36, count 2 2006.201.09:13:34.04#ibcon#wrote, iclass 36, count 2 2006.201.09:13:34.04#ibcon#about to read 3, iclass 36, count 2 2006.201.09:13:34.06#ibcon#read 3, iclass 36, count 2 2006.201.09:13:34.06#ibcon#about to read 4, iclass 36, count 2 2006.201.09:13:34.06#ibcon#read 4, iclass 36, count 2 2006.201.09:13:34.06#ibcon#about to read 5, iclass 36, count 2 2006.201.09:13:34.06#ibcon#read 5, iclass 36, count 2 2006.201.09:13:34.06#ibcon#about to read 6, iclass 36, count 2 2006.201.09:13:34.06#ibcon#read 6, iclass 36, count 2 2006.201.09:13:34.06#ibcon#end of sib2, iclass 36, count 2 2006.201.09:13:34.06#ibcon#*mode == 0, iclass 36, count 2 2006.201.09:13:34.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.09:13:34.06#ibcon#[27=AT08-04\r\n] 2006.201.09:13:34.06#ibcon#*before write, iclass 36, count 2 2006.201.09:13:34.06#ibcon#enter sib2, iclass 36, count 2 2006.201.09:13:34.06#ibcon#flushed, iclass 36, count 2 2006.201.09:13:34.06#ibcon#about to write, iclass 36, count 2 2006.201.09:13:34.06#ibcon#wrote, iclass 36, count 2 2006.201.09:13:34.06#ibcon#about to read 3, iclass 36, count 2 2006.201.09:13:34.09#ibcon#read 3, iclass 36, count 2 2006.201.09:13:34.09#ibcon#about to read 4, iclass 36, count 2 2006.201.09:13:34.09#ibcon#read 4, iclass 36, count 2 2006.201.09:13:34.09#ibcon#about to read 5, iclass 36, count 2 2006.201.09:13:34.09#ibcon#read 5, iclass 36, count 2 2006.201.09:13:34.09#ibcon#about to read 6, iclass 36, count 2 2006.201.09:13:34.09#ibcon#read 6, iclass 36, count 2 2006.201.09:13:34.09#ibcon#end of sib2, iclass 36, count 2 2006.201.09:13:34.09#ibcon#*after write, iclass 36, count 2 2006.201.09:13:34.09#ibcon#*before return 0, iclass 36, count 2 2006.201.09:13:34.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:34.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:13:34.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.09:13:34.09#ibcon#ireg 7 cls_cnt 0 2006.201.09:13:34.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:34.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:34.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:34.21#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:13:34.21#ibcon#first serial, iclass 36, count 0 2006.201.09:13:34.21#ibcon#enter sib2, iclass 36, count 0 2006.201.09:13:34.21#ibcon#flushed, iclass 36, count 0 2006.201.09:13:34.21#ibcon#about to write, iclass 36, count 0 2006.201.09:13:34.21#ibcon#wrote, iclass 36, count 0 2006.201.09:13:34.21#ibcon#about to read 3, iclass 36, count 0 2006.201.09:13:34.23#ibcon#read 3, iclass 36, count 0 2006.201.09:13:34.23#ibcon#about to read 4, iclass 36, count 0 2006.201.09:13:34.23#ibcon#read 4, iclass 36, count 0 2006.201.09:13:34.23#ibcon#about to read 5, iclass 36, count 0 2006.201.09:13:34.23#ibcon#read 5, iclass 36, count 0 2006.201.09:13:34.23#ibcon#about to read 6, iclass 36, count 0 2006.201.09:13:34.23#ibcon#read 6, iclass 36, count 0 2006.201.09:13:34.23#ibcon#end of sib2, iclass 36, count 0 2006.201.09:13:34.23#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:13:34.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:13:34.23#ibcon#[27=USB\r\n] 2006.201.09:13:34.23#ibcon#*before write, iclass 36, count 0 2006.201.09:13:34.23#ibcon#enter sib2, iclass 36, count 0 2006.201.09:13:34.23#ibcon#flushed, iclass 36, count 0 2006.201.09:13:34.23#ibcon#about to write, iclass 36, count 0 2006.201.09:13:34.23#ibcon#wrote, iclass 36, count 0 2006.201.09:13:34.23#ibcon#about to read 3, iclass 36, count 0 2006.201.09:13:34.26#ibcon#read 3, iclass 36, count 0 2006.201.09:13:34.26#ibcon#about to read 4, iclass 36, count 0 2006.201.09:13:34.26#ibcon#read 4, iclass 36, count 0 2006.201.09:13:34.26#ibcon#about to read 5, iclass 36, count 0 2006.201.09:13:34.26#ibcon#read 5, iclass 36, count 0 2006.201.09:13:34.26#ibcon#about to read 6, iclass 36, count 0 2006.201.09:13:34.26#ibcon#read 6, iclass 36, count 0 2006.201.09:13:34.26#ibcon#end of sib2, iclass 36, count 0 2006.201.09:13:34.26#ibcon#*after write, iclass 36, count 0 2006.201.09:13:34.26#ibcon#*before return 0, iclass 36, count 0 2006.201.09:13:34.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:34.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:13:34.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:13:34.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:13:34.26$vck44/vabw=wide 2006.201.09:13:34.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.09:13:34.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.09:13:34.26#ibcon#ireg 8 cls_cnt 0 2006.201.09:13:34.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:34.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:34.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:34.26#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:13:34.26#ibcon#first serial, iclass 38, count 0 2006.201.09:13:34.26#ibcon#enter sib2, iclass 38, count 0 2006.201.09:13:34.26#ibcon#flushed, iclass 38, count 0 2006.201.09:13:34.26#ibcon#about to write, iclass 38, count 0 2006.201.09:13:34.26#ibcon#wrote, iclass 38, count 0 2006.201.09:13:34.26#ibcon#about to read 3, iclass 38, count 0 2006.201.09:13:34.28#ibcon#read 3, iclass 38, count 0 2006.201.09:13:34.28#ibcon#about to read 4, iclass 38, count 0 2006.201.09:13:34.28#ibcon#read 4, iclass 38, count 0 2006.201.09:13:34.28#ibcon#about to read 5, iclass 38, count 0 2006.201.09:13:34.28#ibcon#read 5, iclass 38, count 0 2006.201.09:13:34.28#ibcon#about to read 6, iclass 38, count 0 2006.201.09:13:34.28#ibcon#read 6, iclass 38, count 0 2006.201.09:13:34.28#ibcon#end of sib2, iclass 38, count 0 2006.201.09:13:34.28#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:13:34.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:13:34.28#ibcon#[25=BW32\r\n] 2006.201.09:13:34.28#ibcon#*before write, iclass 38, count 0 2006.201.09:13:34.28#ibcon#enter sib2, iclass 38, count 0 2006.201.09:13:34.28#ibcon#flushed, iclass 38, count 0 2006.201.09:13:34.28#ibcon#about to write, iclass 38, count 0 2006.201.09:13:34.28#ibcon#wrote, iclass 38, count 0 2006.201.09:13:34.28#ibcon#about to read 3, iclass 38, count 0 2006.201.09:13:34.31#ibcon#read 3, iclass 38, count 0 2006.201.09:13:34.31#ibcon#about to read 4, iclass 38, count 0 2006.201.09:13:34.31#ibcon#read 4, iclass 38, count 0 2006.201.09:13:34.31#ibcon#about to read 5, iclass 38, count 0 2006.201.09:13:34.31#ibcon#read 5, iclass 38, count 0 2006.201.09:13:34.31#ibcon#about to read 6, iclass 38, count 0 2006.201.09:13:34.31#ibcon#read 6, iclass 38, count 0 2006.201.09:13:34.31#ibcon#end of sib2, iclass 38, count 0 2006.201.09:13:34.31#ibcon#*after write, iclass 38, count 0 2006.201.09:13:34.31#ibcon#*before return 0, iclass 38, count 0 2006.201.09:13:34.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:34.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:13:34.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:13:34.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:13:34.31$vck44/vbbw=wide 2006.201.09:13:34.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.09:13:34.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.09:13:34.31#ibcon#ireg 8 cls_cnt 0 2006.201.09:13:34.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:13:34.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:13:34.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:13:34.38#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:13:34.38#ibcon#first serial, iclass 40, count 0 2006.201.09:13:34.38#ibcon#enter sib2, iclass 40, count 0 2006.201.09:13:34.38#ibcon#flushed, iclass 40, count 0 2006.201.09:13:34.38#ibcon#about to write, iclass 40, count 0 2006.201.09:13:34.38#ibcon#wrote, iclass 40, count 0 2006.201.09:13:34.38#ibcon#about to read 3, iclass 40, count 0 2006.201.09:13:34.40#ibcon#read 3, iclass 40, count 0 2006.201.09:13:34.40#ibcon#about to read 4, iclass 40, count 0 2006.201.09:13:34.40#ibcon#read 4, iclass 40, count 0 2006.201.09:13:34.40#ibcon#about to read 5, iclass 40, count 0 2006.201.09:13:34.40#ibcon#read 5, iclass 40, count 0 2006.201.09:13:34.40#ibcon#about to read 6, iclass 40, count 0 2006.201.09:13:34.40#ibcon#read 6, iclass 40, count 0 2006.201.09:13:34.40#ibcon#end of sib2, iclass 40, count 0 2006.201.09:13:34.40#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:13:34.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:13:34.40#ibcon#[27=BW32\r\n] 2006.201.09:13:34.40#ibcon#*before write, iclass 40, count 0 2006.201.09:13:34.40#ibcon#enter sib2, iclass 40, count 0 2006.201.09:13:34.40#ibcon#flushed, iclass 40, count 0 2006.201.09:13:34.40#ibcon#about to write, iclass 40, count 0 2006.201.09:13:34.40#ibcon#wrote, iclass 40, count 0 2006.201.09:13:34.40#ibcon#about to read 3, iclass 40, count 0 2006.201.09:13:34.43#ibcon#read 3, iclass 40, count 0 2006.201.09:13:34.43#ibcon#about to read 4, iclass 40, count 0 2006.201.09:13:34.43#ibcon#read 4, iclass 40, count 0 2006.201.09:13:34.43#ibcon#about to read 5, iclass 40, count 0 2006.201.09:13:34.43#ibcon#read 5, iclass 40, count 0 2006.201.09:13:34.43#ibcon#about to read 6, iclass 40, count 0 2006.201.09:13:34.43#ibcon#read 6, iclass 40, count 0 2006.201.09:13:34.43#ibcon#end of sib2, iclass 40, count 0 2006.201.09:13:34.43#ibcon#*after write, iclass 40, count 0 2006.201.09:13:34.43#ibcon#*before return 0, iclass 40, count 0 2006.201.09:13:34.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:13:34.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:13:34.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:13:34.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:13:34.43$setupk4/ifdk4 2006.201.09:13:34.43$ifdk4/lo= 2006.201.09:13:34.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:13:34.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:13:34.43$ifdk4/patch= 2006.201.09:13:34.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:13:34.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:13:34.43$setupk4/!*+20s 2006.201.09:13:37.79#abcon#<5=/05 2.2 3.9 22.84 901003.8\r\n> 2006.201.09:13:37.81#abcon#{5=INTERFACE CLEAR} 2006.201.09:13:37.87#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:13:47.14#trakl#Source acquired 2006.201.09:13:47.96#abcon#<5=/05 2.2 3.9 22.83 901003.8\r\n> 2006.201.09:13:47.98#abcon#{5=INTERFACE CLEAR} 2006.201.09:13:48.04#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:13:48.14#flagr#flagr/antenna,acquired 2006.201.09:13:48.91$setupk4/"tpicd 2006.201.09:13:48.91$setupk4/echo=off 2006.201.09:13:48.91$setupk4/xlog=off 2006.201.09:13:48.91:!2006.201.09:14:35 2006.201.09:14:35.00:preob 2006.201.09:14:35.14/onsource/TRACKING 2006.201.09:14:35.14:!2006.201.09:14:45 2006.201.09:14:45.00:"tape 2006.201.09:14:45.00:"st=record 2006.201.09:14:45.00:data_valid=on 2006.201.09:14:45.00:midob 2006.201.09:14:45.14/onsource/TRACKING 2006.201.09:14:45.14/wx/22.82,1003.8,90 2006.201.09:14:45.19/cable/+6.4648E-03 2006.201.09:14:46.28/va/01,08,usb,yes,28,30 2006.201.09:14:46.28/va/02,07,usb,yes,30,31 2006.201.09:14:46.28/va/03,08,usb,yes,27,28 2006.201.09:14:46.28/va/04,07,usb,yes,31,32 2006.201.09:14:46.28/va/05,04,usb,yes,27,28 2006.201.09:14:46.28/va/06,05,usb,yes,27,27 2006.201.09:14:46.28/va/07,05,usb,yes,26,28 2006.201.09:14:46.28/va/08,04,usb,yes,26,32 2006.201.09:14:46.51/valo/01,524.99,yes,locked 2006.201.09:14:46.51/valo/02,534.99,yes,locked 2006.201.09:14:46.51/valo/03,564.99,yes,locked 2006.201.09:14:46.51/valo/04,624.99,yes,locked 2006.201.09:14:46.51/valo/05,734.99,yes,locked 2006.201.09:14:46.51/valo/06,814.99,yes,locked 2006.201.09:14:46.51/valo/07,864.99,yes,locked 2006.201.09:14:46.51/valo/08,884.99,yes,locked 2006.201.09:14:47.60/vb/01,04,usb,yes,29,27 2006.201.09:14:47.60/vb/02,05,usb,yes,27,27 2006.201.09:14:47.60/vb/03,04,usb,yes,28,31 2006.201.09:14:47.60/vb/04,05,usb,yes,28,27 2006.201.09:14:47.60/vb/05,04,usb,yes,25,27 2006.201.09:14:47.60/vb/06,04,usb,yes,29,25 2006.201.09:14:47.60/vb/07,04,usb,yes,29,29 2006.201.09:14:47.60/vb/08,04,usb,yes,27,30 2006.201.09:14:47.84/vblo/01,629.99,yes,locked 2006.201.09:14:47.84/vblo/02,634.99,yes,locked 2006.201.09:14:47.84/vblo/03,649.99,yes,locked 2006.201.09:14:47.84/vblo/04,679.99,yes,locked 2006.201.09:14:47.84/vblo/05,709.99,yes,locked 2006.201.09:14:47.84/vblo/06,719.99,yes,locked 2006.201.09:14:47.84/vblo/07,734.99,yes,locked 2006.201.09:14:47.84/vblo/08,744.99,yes,locked 2006.201.09:14:47.99/vabw/8 2006.201.09:14:48.14/vbbw/8 2006.201.09:14:48.23/xfe/off,on,15.0 2006.201.09:14:48.62/ifatt/23,28,28,28 2006.201.09:14:49.05/fmout-gps/S +4.54E-07 2006.201.09:14:49.12:!2006.201.09:15:25 2006.201.09:15:25.00:data_valid=off 2006.201.09:15:25.00:"et 2006.201.09:15:25.00:!+3s 2006.201.09:15:28.02:"tape 2006.201.09:15:28.02:postob 2006.201.09:15:28.15/cable/+6.4655E-03 2006.201.09:15:28.15/wx/22.81,1003.8,90 2006.201.09:15:28.22/fmout-gps/S +4.53E-07 2006.201.09:15:28.22:scan_name=201-0917,jd0607,100 2006.201.09:15:28.23:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.201.09:15:30.14#flagr#flagr/antenna,new-source 2006.201.09:15:30.14:checkk5 2006.201.09:15:30.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:15:30.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:15:31.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:15:31.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:15:32.01/chk_obsdata//k5ts1/T2010914??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:15:32.37/chk_obsdata//k5ts2/T2010914??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:15:32.73/chk_obsdata//k5ts3/T2010914??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:15:33.09/chk_obsdata//k5ts4/T2010914??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:15:33.79/k5log//k5ts1_log_newline 2006.201.09:15:34.50/k5log//k5ts2_log_newline 2006.201.09:15:35.19/k5log//k5ts3_log_newline 2006.201.09:15:35.87/k5log//k5ts4_log_newline 2006.201.09:15:35.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:15:35.90:setupk4=1 2006.201.09:15:35.90$setupk4/echo=on 2006.201.09:15:35.90$setupk4/pcalon 2006.201.09:15:35.90$pcalon/"no phase cal control is implemented here 2006.201.09:15:35.90$setupk4/"tpicd=stop 2006.201.09:15:35.90$setupk4/"rec=synch_on 2006.201.09:15:35.90$setupk4/"rec_mode=128 2006.201.09:15:35.90$setupk4/!* 2006.201.09:15:35.90$setupk4/recpk4 2006.201.09:15:35.90$recpk4/recpatch= 2006.201.09:15:35.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:15:35.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:15:35.90$setupk4/vck44 2006.201.09:15:35.90$vck44/valo=1,524.99 2006.201.09:15:35.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.09:15:35.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.09:15:35.90#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:35.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:35.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:35.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:35.90#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:15:35.90#ibcon#first serial, iclass 21, count 0 2006.201.09:15:35.90#ibcon#enter sib2, iclass 21, count 0 2006.201.09:15:35.90#ibcon#flushed, iclass 21, count 0 2006.201.09:15:35.90#ibcon#about to write, iclass 21, count 0 2006.201.09:15:35.90#ibcon#wrote, iclass 21, count 0 2006.201.09:15:35.90#ibcon#about to read 3, iclass 21, count 0 2006.201.09:15:35.94#ibcon#read 3, iclass 21, count 0 2006.201.09:15:35.94#ibcon#about to read 4, iclass 21, count 0 2006.201.09:15:35.94#ibcon#read 4, iclass 21, count 0 2006.201.09:15:35.94#ibcon#about to read 5, iclass 21, count 0 2006.201.09:15:35.94#ibcon#read 5, iclass 21, count 0 2006.201.09:15:35.94#ibcon#about to read 6, iclass 21, count 0 2006.201.09:15:35.94#ibcon#read 6, iclass 21, count 0 2006.201.09:15:35.94#ibcon#end of sib2, iclass 21, count 0 2006.201.09:15:35.94#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:15:35.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:15:35.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:15:35.94#ibcon#*before write, iclass 21, count 0 2006.201.09:15:35.94#ibcon#enter sib2, iclass 21, count 0 2006.201.09:15:35.94#ibcon#flushed, iclass 21, count 0 2006.201.09:15:35.94#ibcon#about to write, iclass 21, count 0 2006.201.09:15:35.94#ibcon#wrote, iclass 21, count 0 2006.201.09:15:35.94#ibcon#about to read 3, iclass 21, count 0 2006.201.09:15:35.99#ibcon#read 3, iclass 21, count 0 2006.201.09:15:35.99#ibcon#about to read 4, iclass 21, count 0 2006.201.09:15:35.99#ibcon#read 4, iclass 21, count 0 2006.201.09:15:35.99#ibcon#about to read 5, iclass 21, count 0 2006.201.09:15:35.99#ibcon#read 5, iclass 21, count 0 2006.201.09:15:35.99#ibcon#about to read 6, iclass 21, count 0 2006.201.09:15:35.99#ibcon#read 6, iclass 21, count 0 2006.201.09:15:35.99#ibcon#end of sib2, iclass 21, count 0 2006.201.09:15:35.99#ibcon#*after write, iclass 21, count 0 2006.201.09:15:35.99#ibcon#*before return 0, iclass 21, count 0 2006.201.09:15:35.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:35.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:35.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:15:35.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:15:35.99$vck44/va=1,8 2006.201.09:15:35.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.09:15:35.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.09:15:35.99#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:35.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:35.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:35.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:35.99#ibcon#enter wrdev, iclass 23, count 2 2006.201.09:15:35.99#ibcon#first serial, iclass 23, count 2 2006.201.09:15:35.99#ibcon#enter sib2, iclass 23, count 2 2006.201.09:15:35.99#ibcon#flushed, iclass 23, count 2 2006.201.09:15:35.99#ibcon#about to write, iclass 23, count 2 2006.201.09:15:35.99#ibcon#wrote, iclass 23, count 2 2006.201.09:15:35.99#ibcon#about to read 3, iclass 23, count 2 2006.201.09:15:36.01#ibcon#read 3, iclass 23, count 2 2006.201.09:15:36.01#ibcon#about to read 4, iclass 23, count 2 2006.201.09:15:36.01#ibcon#read 4, iclass 23, count 2 2006.201.09:15:36.01#ibcon#about to read 5, iclass 23, count 2 2006.201.09:15:36.01#ibcon#read 5, iclass 23, count 2 2006.201.09:15:36.01#ibcon#about to read 6, iclass 23, count 2 2006.201.09:15:36.01#ibcon#read 6, iclass 23, count 2 2006.201.09:15:36.01#ibcon#end of sib2, iclass 23, count 2 2006.201.09:15:36.01#ibcon#*mode == 0, iclass 23, count 2 2006.201.09:15:36.01#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.09:15:36.01#ibcon#[25=AT01-08\r\n] 2006.201.09:15:36.01#ibcon#*before write, iclass 23, count 2 2006.201.09:15:36.01#ibcon#enter sib2, iclass 23, count 2 2006.201.09:15:36.01#ibcon#flushed, iclass 23, count 2 2006.201.09:15:36.01#ibcon#about to write, iclass 23, count 2 2006.201.09:15:36.01#ibcon#wrote, iclass 23, count 2 2006.201.09:15:36.01#ibcon#about to read 3, iclass 23, count 2 2006.201.09:15:36.04#ibcon#read 3, iclass 23, count 2 2006.201.09:15:36.04#ibcon#about to read 4, iclass 23, count 2 2006.201.09:15:36.04#ibcon#read 4, iclass 23, count 2 2006.201.09:15:36.04#ibcon#about to read 5, iclass 23, count 2 2006.201.09:15:36.04#ibcon#read 5, iclass 23, count 2 2006.201.09:15:36.04#ibcon#about to read 6, iclass 23, count 2 2006.201.09:15:36.04#ibcon#read 6, iclass 23, count 2 2006.201.09:15:36.04#ibcon#end of sib2, iclass 23, count 2 2006.201.09:15:36.04#ibcon#*after write, iclass 23, count 2 2006.201.09:15:36.04#ibcon#*before return 0, iclass 23, count 2 2006.201.09:15:36.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:36.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:36.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.09:15:36.04#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:36.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:36.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:36.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:36.16#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:15:36.16#ibcon#first serial, iclass 23, count 0 2006.201.09:15:36.16#ibcon#enter sib2, iclass 23, count 0 2006.201.09:15:36.16#ibcon#flushed, iclass 23, count 0 2006.201.09:15:36.16#ibcon#about to write, iclass 23, count 0 2006.201.09:15:36.16#ibcon#wrote, iclass 23, count 0 2006.201.09:15:36.16#ibcon#about to read 3, iclass 23, count 0 2006.201.09:15:36.18#ibcon#read 3, iclass 23, count 0 2006.201.09:15:36.18#ibcon#about to read 4, iclass 23, count 0 2006.201.09:15:36.18#ibcon#read 4, iclass 23, count 0 2006.201.09:15:36.18#ibcon#about to read 5, iclass 23, count 0 2006.201.09:15:36.18#ibcon#read 5, iclass 23, count 0 2006.201.09:15:36.18#ibcon#about to read 6, iclass 23, count 0 2006.201.09:15:36.18#ibcon#read 6, iclass 23, count 0 2006.201.09:15:36.18#ibcon#end of sib2, iclass 23, count 0 2006.201.09:15:36.18#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:15:36.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:15:36.18#ibcon#[25=USB\r\n] 2006.201.09:15:36.18#ibcon#*before write, iclass 23, count 0 2006.201.09:15:36.18#ibcon#enter sib2, iclass 23, count 0 2006.201.09:15:36.18#ibcon#flushed, iclass 23, count 0 2006.201.09:15:36.18#ibcon#about to write, iclass 23, count 0 2006.201.09:15:36.18#ibcon#wrote, iclass 23, count 0 2006.201.09:15:36.18#ibcon#about to read 3, iclass 23, count 0 2006.201.09:15:36.21#ibcon#read 3, iclass 23, count 0 2006.201.09:15:36.21#ibcon#about to read 4, iclass 23, count 0 2006.201.09:15:36.21#ibcon#read 4, iclass 23, count 0 2006.201.09:15:36.21#ibcon#about to read 5, iclass 23, count 0 2006.201.09:15:36.21#ibcon#read 5, iclass 23, count 0 2006.201.09:15:36.21#ibcon#about to read 6, iclass 23, count 0 2006.201.09:15:36.21#ibcon#read 6, iclass 23, count 0 2006.201.09:15:36.21#ibcon#end of sib2, iclass 23, count 0 2006.201.09:15:36.21#ibcon#*after write, iclass 23, count 0 2006.201.09:15:36.21#ibcon#*before return 0, iclass 23, count 0 2006.201.09:15:36.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:36.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:36.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:15:36.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:15:36.21$vck44/valo=2,534.99 2006.201.09:15:36.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.09:15:36.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.09:15:36.21#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:36.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:36.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:36.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:36.21#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:15:36.21#ibcon#first serial, iclass 25, count 0 2006.201.09:15:36.21#ibcon#enter sib2, iclass 25, count 0 2006.201.09:15:36.21#ibcon#flushed, iclass 25, count 0 2006.201.09:15:36.21#ibcon#about to write, iclass 25, count 0 2006.201.09:15:36.21#ibcon#wrote, iclass 25, count 0 2006.201.09:15:36.21#ibcon#about to read 3, iclass 25, count 0 2006.201.09:15:36.23#ibcon#read 3, iclass 25, count 0 2006.201.09:15:36.23#ibcon#about to read 4, iclass 25, count 0 2006.201.09:15:36.23#ibcon#read 4, iclass 25, count 0 2006.201.09:15:36.23#ibcon#about to read 5, iclass 25, count 0 2006.201.09:15:36.23#ibcon#read 5, iclass 25, count 0 2006.201.09:15:36.23#ibcon#about to read 6, iclass 25, count 0 2006.201.09:15:36.23#ibcon#read 6, iclass 25, count 0 2006.201.09:15:36.23#ibcon#end of sib2, iclass 25, count 0 2006.201.09:15:36.23#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:15:36.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:15:36.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:15:36.23#ibcon#*before write, iclass 25, count 0 2006.201.09:15:36.23#ibcon#enter sib2, iclass 25, count 0 2006.201.09:15:36.23#ibcon#flushed, iclass 25, count 0 2006.201.09:15:36.23#ibcon#about to write, iclass 25, count 0 2006.201.09:15:36.23#ibcon#wrote, iclass 25, count 0 2006.201.09:15:36.23#ibcon#about to read 3, iclass 25, count 0 2006.201.09:15:36.27#ibcon#read 3, iclass 25, count 0 2006.201.09:15:36.27#ibcon#about to read 4, iclass 25, count 0 2006.201.09:15:36.27#ibcon#read 4, iclass 25, count 0 2006.201.09:15:36.27#ibcon#about to read 5, iclass 25, count 0 2006.201.09:15:36.27#ibcon#read 5, iclass 25, count 0 2006.201.09:15:36.27#ibcon#about to read 6, iclass 25, count 0 2006.201.09:15:36.27#ibcon#read 6, iclass 25, count 0 2006.201.09:15:36.27#ibcon#end of sib2, iclass 25, count 0 2006.201.09:15:36.27#ibcon#*after write, iclass 25, count 0 2006.201.09:15:36.27#ibcon#*before return 0, iclass 25, count 0 2006.201.09:15:36.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:36.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:36.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:15:36.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:15:36.27$vck44/va=2,7 2006.201.09:15:36.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.09:15:36.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.09:15:36.27#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:36.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:36.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:36.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:36.33#ibcon#enter wrdev, iclass 27, count 2 2006.201.09:15:36.33#ibcon#first serial, iclass 27, count 2 2006.201.09:15:36.33#ibcon#enter sib2, iclass 27, count 2 2006.201.09:15:36.33#ibcon#flushed, iclass 27, count 2 2006.201.09:15:36.33#ibcon#about to write, iclass 27, count 2 2006.201.09:15:36.33#ibcon#wrote, iclass 27, count 2 2006.201.09:15:36.33#ibcon#about to read 3, iclass 27, count 2 2006.201.09:15:36.35#ibcon#read 3, iclass 27, count 2 2006.201.09:15:36.35#ibcon#about to read 4, iclass 27, count 2 2006.201.09:15:36.35#ibcon#read 4, iclass 27, count 2 2006.201.09:15:36.35#ibcon#about to read 5, iclass 27, count 2 2006.201.09:15:36.35#ibcon#read 5, iclass 27, count 2 2006.201.09:15:36.35#ibcon#about to read 6, iclass 27, count 2 2006.201.09:15:36.35#ibcon#read 6, iclass 27, count 2 2006.201.09:15:36.35#ibcon#end of sib2, iclass 27, count 2 2006.201.09:15:36.35#ibcon#*mode == 0, iclass 27, count 2 2006.201.09:15:36.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.09:15:36.35#ibcon#[25=AT02-07\r\n] 2006.201.09:15:36.35#ibcon#*before write, iclass 27, count 2 2006.201.09:15:36.35#ibcon#enter sib2, iclass 27, count 2 2006.201.09:15:36.35#ibcon#flushed, iclass 27, count 2 2006.201.09:15:36.35#ibcon#about to write, iclass 27, count 2 2006.201.09:15:36.35#ibcon#wrote, iclass 27, count 2 2006.201.09:15:36.35#ibcon#about to read 3, iclass 27, count 2 2006.201.09:15:36.38#ibcon#read 3, iclass 27, count 2 2006.201.09:15:36.38#ibcon#about to read 4, iclass 27, count 2 2006.201.09:15:36.38#ibcon#read 4, iclass 27, count 2 2006.201.09:15:36.38#ibcon#about to read 5, iclass 27, count 2 2006.201.09:15:36.38#ibcon#read 5, iclass 27, count 2 2006.201.09:15:36.38#ibcon#about to read 6, iclass 27, count 2 2006.201.09:15:36.38#ibcon#read 6, iclass 27, count 2 2006.201.09:15:36.38#ibcon#end of sib2, iclass 27, count 2 2006.201.09:15:36.38#ibcon#*after write, iclass 27, count 2 2006.201.09:15:36.38#ibcon#*before return 0, iclass 27, count 2 2006.201.09:15:36.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:36.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:36.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.09:15:36.38#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:36.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:36.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:36.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:36.50#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:15:36.50#ibcon#first serial, iclass 27, count 0 2006.201.09:15:36.50#ibcon#enter sib2, iclass 27, count 0 2006.201.09:15:36.50#ibcon#flushed, iclass 27, count 0 2006.201.09:15:36.50#ibcon#about to write, iclass 27, count 0 2006.201.09:15:36.50#ibcon#wrote, iclass 27, count 0 2006.201.09:15:36.50#ibcon#about to read 3, iclass 27, count 0 2006.201.09:15:36.52#ibcon#read 3, iclass 27, count 0 2006.201.09:15:36.52#ibcon#about to read 4, iclass 27, count 0 2006.201.09:15:36.52#ibcon#read 4, iclass 27, count 0 2006.201.09:15:36.52#ibcon#about to read 5, iclass 27, count 0 2006.201.09:15:36.52#ibcon#read 5, iclass 27, count 0 2006.201.09:15:36.52#ibcon#about to read 6, iclass 27, count 0 2006.201.09:15:36.52#ibcon#read 6, iclass 27, count 0 2006.201.09:15:36.52#ibcon#end of sib2, iclass 27, count 0 2006.201.09:15:36.52#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:15:36.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:15:36.52#ibcon#[25=USB\r\n] 2006.201.09:15:36.52#ibcon#*before write, iclass 27, count 0 2006.201.09:15:36.52#ibcon#enter sib2, iclass 27, count 0 2006.201.09:15:36.52#ibcon#flushed, iclass 27, count 0 2006.201.09:15:36.52#ibcon#about to write, iclass 27, count 0 2006.201.09:15:36.52#ibcon#wrote, iclass 27, count 0 2006.201.09:15:36.52#ibcon#about to read 3, iclass 27, count 0 2006.201.09:15:36.55#ibcon#read 3, iclass 27, count 0 2006.201.09:15:36.55#ibcon#about to read 4, iclass 27, count 0 2006.201.09:15:36.55#ibcon#read 4, iclass 27, count 0 2006.201.09:15:36.55#ibcon#about to read 5, iclass 27, count 0 2006.201.09:15:36.55#ibcon#read 5, iclass 27, count 0 2006.201.09:15:36.55#ibcon#about to read 6, iclass 27, count 0 2006.201.09:15:36.55#ibcon#read 6, iclass 27, count 0 2006.201.09:15:36.55#ibcon#end of sib2, iclass 27, count 0 2006.201.09:15:36.55#ibcon#*after write, iclass 27, count 0 2006.201.09:15:36.55#ibcon#*before return 0, iclass 27, count 0 2006.201.09:15:36.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:36.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:36.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:15:36.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:15:36.55$vck44/valo=3,564.99 2006.201.09:15:36.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.09:15:36.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.09:15:36.55#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:36.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:36.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:36.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:36.55#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:15:36.55#ibcon#first serial, iclass 29, count 0 2006.201.09:15:36.55#ibcon#enter sib2, iclass 29, count 0 2006.201.09:15:36.55#ibcon#flushed, iclass 29, count 0 2006.201.09:15:36.55#ibcon#about to write, iclass 29, count 0 2006.201.09:15:36.55#ibcon#wrote, iclass 29, count 0 2006.201.09:15:36.55#ibcon#about to read 3, iclass 29, count 0 2006.201.09:15:36.57#ibcon#read 3, iclass 29, count 0 2006.201.09:15:36.57#ibcon#about to read 4, iclass 29, count 0 2006.201.09:15:36.57#ibcon#read 4, iclass 29, count 0 2006.201.09:15:36.57#ibcon#about to read 5, iclass 29, count 0 2006.201.09:15:36.57#ibcon#read 5, iclass 29, count 0 2006.201.09:15:36.57#ibcon#about to read 6, iclass 29, count 0 2006.201.09:15:36.57#ibcon#read 6, iclass 29, count 0 2006.201.09:15:36.57#ibcon#end of sib2, iclass 29, count 0 2006.201.09:15:36.57#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:15:36.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:15:36.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:15:36.57#ibcon#*before write, iclass 29, count 0 2006.201.09:15:36.57#ibcon#enter sib2, iclass 29, count 0 2006.201.09:15:36.57#ibcon#flushed, iclass 29, count 0 2006.201.09:15:36.57#ibcon#about to write, iclass 29, count 0 2006.201.09:15:36.57#ibcon#wrote, iclass 29, count 0 2006.201.09:15:36.57#ibcon#about to read 3, iclass 29, count 0 2006.201.09:15:36.61#ibcon#read 3, iclass 29, count 0 2006.201.09:15:36.61#ibcon#about to read 4, iclass 29, count 0 2006.201.09:15:36.61#ibcon#read 4, iclass 29, count 0 2006.201.09:15:36.61#ibcon#about to read 5, iclass 29, count 0 2006.201.09:15:36.61#ibcon#read 5, iclass 29, count 0 2006.201.09:15:36.61#ibcon#about to read 6, iclass 29, count 0 2006.201.09:15:36.61#ibcon#read 6, iclass 29, count 0 2006.201.09:15:36.61#ibcon#end of sib2, iclass 29, count 0 2006.201.09:15:36.61#ibcon#*after write, iclass 29, count 0 2006.201.09:15:36.61#ibcon#*before return 0, iclass 29, count 0 2006.201.09:15:36.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:36.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:36.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:15:36.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:15:36.61$vck44/va=3,8 2006.201.09:15:36.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.09:15:36.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.09:15:36.61#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:36.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:36.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:36.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:36.67#ibcon#enter wrdev, iclass 31, count 2 2006.201.09:15:36.67#ibcon#first serial, iclass 31, count 2 2006.201.09:15:36.67#ibcon#enter sib2, iclass 31, count 2 2006.201.09:15:36.67#ibcon#flushed, iclass 31, count 2 2006.201.09:15:36.67#ibcon#about to write, iclass 31, count 2 2006.201.09:15:36.67#ibcon#wrote, iclass 31, count 2 2006.201.09:15:36.67#ibcon#about to read 3, iclass 31, count 2 2006.201.09:15:36.69#ibcon#read 3, iclass 31, count 2 2006.201.09:15:36.69#ibcon#about to read 4, iclass 31, count 2 2006.201.09:15:36.69#ibcon#read 4, iclass 31, count 2 2006.201.09:15:36.69#ibcon#about to read 5, iclass 31, count 2 2006.201.09:15:36.69#ibcon#read 5, iclass 31, count 2 2006.201.09:15:36.69#ibcon#about to read 6, iclass 31, count 2 2006.201.09:15:36.69#ibcon#read 6, iclass 31, count 2 2006.201.09:15:36.69#ibcon#end of sib2, iclass 31, count 2 2006.201.09:15:36.69#ibcon#*mode == 0, iclass 31, count 2 2006.201.09:15:36.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.09:15:36.69#ibcon#[25=AT03-08\r\n] 2006.201.09:15:36.69#ibcon#*before write, iclass 31, count 2 2006.201.09:15:36.69#ibcon#enter sib2, iclass 31, count 2 2006.201.09:15:36.69#ibcon#flushed, iclass 31, count 2 2006.201.09:15:36.69#ibcon#about to write, iclass 31, count 2 2006.201.09:15:36.69#ibcon#wrote, iclass 31, count 2 2006.201.09:15:36.69#ibcon#about to read 3, iclass 31, count 2 2006.201.09:15:36.72#ibcon#read 3, iclass 31, count 2 2006.201.09:15:36.72#ibcon#about to read 4, iclass 31, count 2 2006.201.09:15:36.72#ibcon#read 4, iclass 31, count 2 2006.201.09:15:36.72#ibcon#about to read 5, iclass 31, count 2 2006.201.09:15:36.72#ibcon#read 5, iclass 31, count 2 2006.201.09:15:36.72#ibcon#about to read 6, iclass 31, count 2 2006.201.09:15:36.72#ibcon#read 6, iclass 31, count 2 2006.201.09:15:36.72#ibcon#end of sib2, iclass 31, count 2 2006.201.09:15:36.72#ibcon#*after write, iclass 31, count 2 2006.201.09:15:36.72#ibcon#*before return 0, iclass 31, count 2 2006.201.09:15:36.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:36.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:36.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.09:15:36.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:36.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:36.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:36.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:36.84#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:15:36.84#ibcon#first serial, iclass 31, count 0 2006.201.09:15:36.84#ibcon#enter sib2, iclass 31, count 0 2006.201.09:15:36.84#ibcon#flushed, iclass 31, count 0 2006.201.09:15:36.84#ibcon#about to write, iclass 31, count 0 2006.201.09:15:36.84#ibcon#wrote, iclass 31, count 0 2006.201.09:15:36.84#ibcon#about to read 3, iclass 31, count 0 2006.201.09:15:36.86#ibcon#read 3, iclass 31, count 0 2006.201.09:15:36.86#ibcon#about to read 4, iclass 31, count 0 2006.201.09:15:36.86#ibcon#read 4, iclass 31, count 0 2006.201.09:15:36.86#ibcon#about to read 5, iclass 31, count 0 2006.201.09:15:36.86#ibcon#read 5, iclass 31, count 0 2006.201.09:15:36.86#ibcon#about to read 6, iclass 31, count 0 2006.201.09:15:36.86#ibcon#read 6, iclass 31, count 0 2006.201.09:15:36.86#ibcon#end of sib2, iclass 31, count 0 2006.201.09:15:36.86#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:15:36.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:15:36.86#ibcon#[25=USB\r\n] 2006.201.09:15:36.86#ibcon#*before write, iclass 31, count 0 2006.201.09:15:36.86#ibcon#enter sib2, iclass 31, count 0 2006.201.09:15:36.86#ibcon#flushed, iclass 31, count 0 2006.201.09:15:36.86#ibcon#about to write, iclass 31, count 0 2006.201.09:15:36.86#ibcon#wrote, iclass 31, count 0 2006.201.09:15:36.86#ibcon#about to read 3, iclass 31, count 0 2006.201.09:15:36.89#ibcon#read 3, iclass 31, count 0 2006.201.09:15:36.89#ibcon#about to read 4, iclass 31, count 0 2006.201.09:15:36.89#ibcon#read 4, iclass 31, count 0 2006.201.09:15:36.89#ibcon#about to read 5, iclass 31, count 0 2006.201.09:15:36.89#ibcon#read 5, iclass 31, count 0 2006.201.09:15:36.89#ibcon#about to read 6, iclass 31, count 0 2006.201.09:15:36.89#ibcon#read 6, iclass 31, count 0 2006.201.09:15:36.89#ibcon#end of sib2, iclass 31, count 0 2006.201.09:15:36.89#ibcon#*after write, iclass 31, count 0 2006.201.09:15:36.89#ibcon#*before return 0, iclass 31, count 0 2006.201.09:15:36.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:36.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:36.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:15:36.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:15:36.89$vck44/valo=4,624.99 2006.201.09:15:36.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.09:15:36.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.09:15:36.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:36.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:15:36.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:15:36.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:15:36.89#ibcon#enter wrdev, iclass 33, count 0 2006.201.09:15:36.89#ibcon#first serial, iclass 33, count 0 2006.201.09:15:36.89#ibcon#enter sib2, iclass 33, count 0 2006.201.09:15:36.89#ibcon#flushed, iclass 33, count 0 2006.201.09:15:36.89#ibcon#about to write, iclass 33, count 0 2006.201.09:15:36.89#ibcon#wrote, iclass 33, count 0 2006.201.09:15:36.89#ibcon#about to read 3, iclass 33, count 0 2006.201.09:15:36.91#ibcon#read 3, iclass 33, count 0 2006.201.09:15:36.91#ibcon#about to read 4, iclass 33, count 0 2006.201.09:15:36.91#ibcon#read 4, iclass 33, count 0 2006.201.09:15:36.91#ibcon#about to read 5, iclass 33, count 0 2006.201.09:15:36.91#ibcon#read 5, iclass 33, count 0 2006.201.09:15:36.91#ibcon#about to read 6, iclass 33, count 0 2006.201.09:15:36.91#ibcon#read 6, iclass 33, count 0 2006.201.09:15:36.91#ibcon#end of sib2, iclass 33, count 0 2006.201.09:15:36.91#ibcon#*mode == 0, iclass 33, count 0 2006.201.09:15:36.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.09:15:36.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:15:36.91#ibcon#*before write, iclass 33, count 0 2006.201.09:15:36.91#ibcon#enter sib2, iclass 33, count 0 2006.201.09:15:36.91#ibcon#flushed, iclass 33, count 0 2006.201.09:15:36.91#ibcon#about to write, iclass 33, count 0 2006.201.09:15:36.91#ibcon#wrote, iclass 33, count 0 2006.201.09:15:36.91#ibcon#about to read 3, iclass 33, count 0 2006.201.09:15:36.95#ibcon#read 3, iclass 33, count 0 2006.201.09:15:36.95#ibcon#about to read 4, iclass 33, count 0 2006.201.09:15:36.95#ibcon#read 4, iclass 33, count 0 2006.201.09:15:36.95#ibcon#about to read 5, iclass 33, count 0 2006.201.09:15:36.95#ibcon#read 5, iclass 33, count 0 2006.201.09:15:36.95#ibcon#about to read 6, iclass 33, count 0 2006.201.09:15:36.95#ibcon#read 6, iclass 33, count 0 2006.201.09:15:36.95#ibcon#end of sib2, iclass 33, count 0 2006.201.09:15:36.95#ibcon#*after write, iclass 33, count 0 2006.201.09:15:36.95#ibcon#*before return 0, iclass 33, count 0 2006.201.09:15:36.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:15:36.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:15:36.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.09:15:36.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.09:15:36.95$vck44/va=4,7 2006.201.09:15:36.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.09:15:36.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.09:15:36.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:36.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:15:37.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:15:37.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:15:37.01#ibcon#enter wrdev, iclass 35, count 2 2006.201.09:15:37.01#ibcon#first serial, iclass 35, count 2 2006.201.09:15:37.01#ibcon#enter sib2, iclass 35, count 2 2006.201.09:15:37.01#ibcon#flushed, iclass 35, count 2 2006.201.09:15:37.01#ibcon#about to write, iclass 35, count 2 2006.201.09:15:37.01#ibcon#wrote, iclass 35, count 2 2006.201.09:15:37.01#ibcon#about to read 3, iclass 35, count 2 2006.201.09:15:37.03#ibcon#read 3, iclass 35, count 2 2006.201.09:15:37.03#ibcon#about to read 4, iclass 35, count 2 2006.201.09:15:37.03#ibcon#read 4, iclass 35, count 2 2006.201.09:15:37.03#ibcon#about to read 5, iclass 35, count 2 2006.201.09:15:37.03#ibcon#read 5, iclass 35, count 2 2006.201.09:15:37.03#ibcon#about to read 6, iclass 35, count 2 2006.201.09:15:37.03#ibcon#read 6, iclass 35, count 2 2006.201.09:15:37.03#ibcon#end of sib2, iclass 35, count 2 2006.201.09:15:37.03#ibcon#*mode == 0, iclass 35, count 2 2006.201.09:15:37.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.09:15:37.03#ibcon#[25=AT04-07\r\n] 2006.201.09:15:37.03#ibcon#*before write, iclass 35, count 2 2006.201.09:15:37.03#ibcon#enter sib2, iclass 35, count 2 2006.201.09:15:37.03#ibcon#flushed, iclass 35, count 2 2006.201.09:15:37.03#ibcon#about to write, iclass 35, count 2 2006.201.09:15:37.03#ibcon#wrote, iclass 35, count 2 2006.201.09:15:37.03#ibcon#about to read 3, iclass 35, count 2 2006.201.09:15:37.06#ibcon#read 3, iclass 35, count 2 2006.201.09:15:37.06#ibcon#about to read 4, iclass 35, count 2 2006.201.09:15:37.06#ibcon#read 4, iclass 35, count 2 2006.201.09:15:37.06#ibcon#about to read 5, iclass 35, count 2 2006.201.09:15:37.06#ibcon#read 5, iclass 35, count 2 2006.201.09:15:37.06#ibcon#about to read 6, iclass 35, count 2 2006.201.09:15:37.06#ibcon#read 6, iclass 35, count 2 2006.201.09:15:37.06#ibcon#end of sib2, iclass 35, count 2 2006.201.09:15:37.06#ibcon#*after write, iclass 35, count 2 2006.201.09:15:37.06#ibcon#*before return 0, iclass 35, count 2 2006.201.09:15:37.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:15:37.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:15:37.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.09:15:37.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:37.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:15:37.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:15:37.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:15:37.18#ibcon#enter wrdev, iclass 35, count 0 2006.201.09:15:37.18#ibcon#first serial, iclass 35, count 0 2006.201.09:15:37.18#ibcon#enter sib2, iclass 35, count 0 2006.201.09:15:37.18#ibcon#flushed, iclass 35, count 0 2006.201.09:15:37.18#ibcon#about to write, iclass 35, count 0 2006.201.09:15:37.18#ibcon#wrote, iclass 35, count 0 2006.201.09:15:37.18#ibcon#about to read 3, iclass 35, count 0 2006.201.09:15:37.20#ibcon#read 3, iclass 35, count 0 2006.201.09:15:37.20#ibcon#about to read 4, iclass 35, count 0 2006.201.09:15:37.20#ibcon#read 4, iclass 35, count 0 2006.201.09:15:37.20#ibcon#about to read 5, iclass 35, count 0 2006.201.09:15:37.20#ibcon#read 5, iclass 35, count 0 2006.201.09:15:37.20#ibcon#about to read 6, iclass 35, count 0 2006.201.09:15:37.20#ibcon#read 6, iclass 35, count 0 2006.201.09:15:37.20#ibcon#end of sib2, iclass 35, count 0 2006.201.09:15:37.20#ibcon#*mode == 0, iclass 35, count 0 2006.201.09:15:37.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.09:15:37.20#ibcon#[25=USB\r\n] 2006.201.09:15:37.20#ibcon#*before write, iclass 35, count 0 2006.201.09:15:37.20#ibcon#enter sib2, iclass 35, count 0 2006.201.09:15:37.20#ibcon#flushed, iclass 35, count 0 2006.201.09:15:37.20#ibcon#about to write, iclass 35, count 0 2006.201.09:15:37.20#ibcon#wrote, iclass 35, count 0 2006.201.09:15:37.20#ibcon#about to read 3, iclass 35, count 0 2006.201.09:15:37.23#ibcon#read 3, iclass 35, count 0 2006.201.09:15:37.23#ibcon#about to read 4, iclass 35, count 0 2006.201.09:15:37.23#ibcon#read 4, iclass 35, count 0 2006.201.09:15:37.23#ibcon#about to read 5, iclass 35, count 0 2006.201.09:15:37.23#ibcon#read 5, iclass 35, count 0 2006.201.09:15:37.23#ibcon#about to read 6, iclass 35, count 0 2006.201.09:15:37.23#ibcon#read 6, iclass 35, count 0 2006.201.09:15:37.23#ibcon#end of sib2, iclass 35, count 0 2006.201.09:15:37.23#ibcon#*after write, iclass 35, count 0 2006.201.09:15:37.23#ibcon#*before return 0, iclass 35, count 0 2006.201.09:15:37.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:15:37.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:15:37.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.09:15:37.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.09:15:37.23$vck44/valo=5,734.99 2006.201.09:15:37.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.09:15:37.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.09:15:37.23#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:37.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:15:37.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:15:37.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:15:37.23#ibcon#enter wrdev, iclass 37, count 0 2006.201.09:15:37.23#ibcon#first serial, iclass 37, count 0 2006.201.09:15:37.23#ibcon#enter sib2, iclass 37, count 0 2006.201.09:15:37.23#ibcon#flushed, iclass 37, count 0 2006.201.09:15:37.23#ibcon#about to write, iclass 37, count 0 2006.201.09:15:37.23#ibcon#wrote, iclass 37, count 0 2006.201.09:15:37.23#ibcon#about to read 3, iclass 37, count 0 2006.201.09:15:37.25#ibcon#read 3, iclass 37, count 0 2006.201.09:15:37.25#ibcon#about to read 4, iclass 37, count 0 2006.201.09:15:37.25#ibcon#read 4, iclass 37, count 0 2006.201.09:15:37.25#ibcon#about to read 5, iclass 37, count 0 2006.201.09:15:37.25#ibcon#read 5, iclass 37, count 0 2006.201.09:15:37.25#ibcon#about to read 6, iclass 37, count 0 2006.201.09:15:37.25#ibcon#read 6, iclass 37, count 0 2006.201.09:15:37.25#ibcon#end of sib2, iclass 37, count 0 2006.201.09:15:37.25#ibcon#*mode == 0, iclass 37, count 0 2006.201.09:15:37.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.09:15:37.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:15:37.25#ibcon#*before write, iclass 37, count 0 2006.201.09:15:37.25#ibcon#enter sib2, iclass 37, count 0 2006.201.09:15:37.25#ibcon#flushed, iclass 37, count 0 2006.201.09:15:37.25#ibcon#about to write, iclass 37, count 0 2006.201.09:15:37.25#ibcon#wrote, iclass 37, count 0 2006.201.09:15:37.25#ibcon#about to read 3, iclass 37, count 0 2006.201.09:15:37.29#ibcon#read 3, iclass 37, count 0 2006.201.09:15:37.29#ibcon#about to read 4, iclass 37, count 0 2006.201.09:15:37.29#ibcon#read 4, iclass 37, count 0 2006.201.09:15:37.29#ibcon#about to read 5, iclass 37, count 0 2006.201.09:15:37.29#ibcon#read 5, iclass 37, count 0 2006.201.09:15:37.29#ibcon#about to read 6, iclass 37, count 0 2006.201.09:15:37.29#ibcon#read 6, iclass 37, count 0 2006.201.09:15:37.29#ibcon#end of sib2, iclass 37, count 0 2006.201.09:15:37.29#ibcon#*after write, iclass 37, count 0 2006.201.09:15:37.29#ibcon#*before return 0, iclass 37, count 0 2006.201.09:15:37.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:15:37.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:15:37.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.09:15:37.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.09:15:37.29$vck44/va=5,4 2006.201.09:15:37.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.09:15:37.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.09:15:37.29#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:37.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:37.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:37.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:37.35#ibcon#enter wrdev, iclass 39, count 2 2006.201.09:15:37.35#ibcon#first serial, iclass 39, count 2 2006.201.09:15:37.35#ibcon#enter sib2, iclass 39, count 2 2006.201.09:15:37.35#ibcon#flushed, iclass 39, count 2 2006.201.09:15:37.35#ibcon#about to write, iclass 39, count 2 2006.201.09:15:37.35#ibcon#wrote, iclass 39, count 2 2006.201.09:15:37.35#ibcon#about to read 3, iclass 39, count 2 2006.201.09:15:37.37#ibcon#read 3, iclass 39, count 2 2006.201.09:15:37.37#ibcon#about to read 4, iclass 39, count 2 2006.201.09:15:37.37#ibcon#read 4, iclass 39, count 2 2006.201.09:15:37.37#ibcon#about to read 5, iclass 39, count 2 2006.201.09:15:37.37#ibcon#read 5, iclass 39, count 2 2006.201.09:15:37.37#ibcon#about to read 6, iclass 39, count 2 2006.201.09:15:37.37#ibcon#read 6, iclass 39, count 2 2006.201.09:15:37.37#ibcon#end of sib2, iclass 39, count 2 2006.201.09:15:37.37#ibcon#*mode == 0, iclass 39, count 2 2006.201.09:15:37.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.09:15:37.37#ibcon#[25=AT05-04\r\n] 2006.201.09:15:37.37#ibcon#*before write, iclass 39, count 2 2006.201.09:15:37.37#ibcon#enter sib2, iclass 39, count 2 2006.201.09:15:37.37#ibcon#flushed, iclass 39, count 2 2006.201.09:15:37.37#ibcon#about to write, iclass 39, count 2 2006.201.09:15:37.37#ibcon#wrote, iclass 39, count 2 2006.201.09:15:37.37#ibcon#about to read 3, iclass 39, count 2 2006.201.09:15:37.40#ibcon#read 3, iclass 39, count 2 2006.201.09:15:37.40#ibcon#about to read 4, iclass 39, count 2 2006.201.09:15:37.40#ibcon#read 4, iclass 39, count 2 2006.201.09:15:37.40#ibcon#about to read 5, iclass 39, count 2 2006.201.09:15:37.40#ibcon#read 5, iclass 39, count 2 2006.201.09:15:37.40#ibcon#about to read 6, iclass 39, count 2 2006.201.09:15:37.40#ibcon#read 6, iclass 39, count 2 2006.201.09:15:37.40#ibcon#end of sib2, iclass 39, count 2 2006.201.09:15:37.40#ibcon#*after write, iclass 39, count 2 2006.201.09:15:37.40#ibcon#*before return 0, iclass 39, count 2 2006.201.09:15:37.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:37.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:37.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.09:15:37.40#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:37.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:37.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:37.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:37.52#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:15:37.52#ibcon#first serial, iclass 39, count 0 2006.201.09:15:37.52#ibcon#enter sib2, iclass 39, count 0 2006.201.09:15:37.52#ibcon#flushed, iclass 39, count 0 2006.201.09:15:37.52#ibcon#about to write, iclass 39, count 0 2006.201.09:15:37.52#ibcon#wrote, iclass 39, count 0 2006.201.09:15:37.52#ibcon#about to read 3, iclass 39, count 0 2006.201.09:15:37.54#ibcon#read 3, iclass 39, count 0 2006.201.09:15:37.54#ibcon#about to read 4, iclass 39, count 0 2006.201.09:15:37.54#ibcon#read 4, iclass 39, count 0 2006.201.09:15:37.54#ibcon#about to read 5, iclass 39, count 0 2006.201.09:15:37.54#ibcon#read 5, iclass 39, count 0 2006.201.09:15:37.54#ibcon#about to read 6, iclass 39, count 0 2006.201.09:15:37.54#ibcon#read 6, iclass 39, count 0 2006.201.09:15:37.54#ibcon#end of sib2, iclass 39, count 0 2006.201.09:15:37.54#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:15:37.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:15:37.54#ibcon#[25=USB\r\n] 2006.201.09:15:37.54#ibcon#*before write, iclass 39, count 0 2006.201.09:15:37.54#ibcon#enter sib2, iclass 39, count 0 2006.201.09:15:37.54#ibcon#flushed, iclass 39, count 0 2006.201.09:15:37.54#ibcon#about to write, iclass 39, count 0 2006.201.09:15:37.54#ibcon#wrote, iclass 39, count 0 2006.201.09:15:37.54#ibcon#about to read 3, iclass 39, count 0 2006.201.09:15:37.57#ibcon#read 3, iclass 39, count 0 2006.201.09:15:37.57#ibcon#about to read 4, iclass 39, count 0 2006.201.09:15:37.57#ibcon#read 4, iclass 39, count 0 2006.201.09:15:37.57#ibcon#about to read 5, iclass 39, count 0 2006.201.09:15:37.57#ibcon#read 5, iclass 39, count 0 2006.201.09:15:37.57#ibcon#about to read 6, iclass 39, count 0 2006.201.09:15:37.57#ibcon#read 6, iclass 39, count 0 2006.201.09:15:37.57#ibcon#end of sib2, iclass 39, count 0 2006.201.09:15:37.57#ibcon#*after write, iclass 39, count 0 2006.201.09:15:37.57#ibcon#*before return 0, iclass 39, count 0 2006.201.09:15:37.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:37.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:37.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:15:37.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:15:37.57$vck44/valo=6,814.99 2006.201.09:15:37.57#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.09:15:37.57#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.09:15:37.57#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:37.57#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:37.57#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:37.57#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:37.57#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:15:37.57#ibcon#first serial, iclass 2, count 0 2006.201.09:15:37.57#ibcon#enter sib2, iclass 2, count 0 2006.201.09:15:37.57#ibcon#flushed, iclass 2, count 0 2006.201.09:15:37.57#ibcon#about to write, iclass 2, count 0 2006.201.09:15:37.57#ibcon#wrote, iclass 2, count 0 2006.201.09:15:37.57#ibcon#about to read 3, iclass 2, count 0 2006.201.09:15:37.59#ibcon#read 3, iclass 2, count 0 2006.201.09:15:37.59#ibcon#about to read 4, iclass 2, count 0 2006.201.09:15:37.59#ibcon#read 4, iclass 2, count 0 2006.201.09:15:37.59#ibcon#about to read 5, iclass 2, count 0 2006.201.09:15:37.59#ibcon#read 5, iclass 2, count 0 2006.201.09:15:37.59#ibcon#about to read 6, iclass 2, count 0 2006.201.09:15:37.59#ibcon#read 6, iclass 2, count 0 2006.201.09:15:37.59#ibcon#end of sib2, iclass 2, count 0 2006.201.09:15:37.59#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:15:37.59#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:15:37.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:15:37.59#ibcon#*before write, iclass 2, count 0 2006.201.09:15:37.59#ibcon#enter sib2, iclass 2, count 0 2006.201.09:15:37.59#ibcon#flushed, iclass 2, count 0 2006.201.09:15:37.59#ibcon#about to write, iclass 2, count 0 2006.201.09:15:37.59#ibcon#wrote, iclass 2, count 0 2006.201.09:15:37.59#ibcon#about to read 3, iclass 2, count 0 2006.201.09:15:37.63#ibcon#read 3, iclass 2, count 0 2006.201.09:15:37.63#ibcon#about to read 4, iclass 2, count 0 2006.201.09:15:37.63#ibcon#read 4, iclass 2, count 0 2006.201.09:15:37.63#ibcon#about to read 5, iclass 2, count 0 2006.201.09:15:37.63#ibcon#read 5, iclass 2, count 0 2006.201.09:15:37.63#ibcon#about to read 6, iclass 2, count 0 2006.201.09:15:37.63#ibcon#read 6, iclass 2, count 0 2006.201.09:15:37.63#ibcon#end of sib2, iclass 2, count 0 2006.201.09:15:37.63#ibcon#*after write, iclass 2, count 0 2006.201.09:15:37.63#ibcon#*before return 0, iclass 2, count 0 2006.201.09:15:37.63#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:37.63#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:37.63#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:15:37.63#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:15:37.63$vck44/va=6,5 2006.201.09:15:37.63#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.09:15:37.63#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.09:15:37.63#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:37.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:37.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:37.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:37.69#ibcon#enter wrdev, iclass 5, count 2 2006.201.09:15:37.69#ibcon#first serial, iclass 5, count 2 2006.201.09:15:37.69#ibcon#enter sib2, iclass 5, count 2 2006.201.09:15:37.69#ibcon#flushed, iclass 5, count 2 2006.201.09:15:37.69#ibcon#about to write, iclass 5, count 2 2006.201.09:15:37.69#ibcon#wrote, iclass 5, count 2 2006.201.09:15:37.69#ibcon#about to read 3, iclass 5, count 2 2006.201.09:15:37.71#ibcon#read 3, iclass 5, count 2 2006.201.09:15:37.71#ibcon#about to read 4, iclass 5, count 2 2006.201.09:15:37.71#ibcon#read 4, iclass 5, count 2 2006.201.09:15:37.71#ibcon#about to read 5, iclass 5, count 2 2006.201.09:15:37.71#ibcon#read 5, iclass 5, count 2 2006.201.09:15:37.71#ibcon#about to read 6, iclass 5, count 2 2006.201.09:15:37.71#ibcon#read 6, iclass 5, count 2 2006.201.09:15:37.71#ibcon#end of sib2, iclass 5, count 2 2006.201.09:15:37.71#ibcon#*mode == 0, iclass 5, count 2 2006.201.09:15:37.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.09:15:37.71#ibcon#[25=AT06-05\r\n] 2006.201.09:15:37.71#ibcon#*before write, iclass 5, count 2 2006.201.09:15:37.71#ibcon#enter sib2, iclass 5, count 2 2006.201.09:15:37.71#ibcon#flushed, iclass 5, count 2 2006.201.09:15:37.71#ibcon#about to write, iclass 5, count 2 2006.201.09:15:37.71#ibcon#wrote, iclass 5, count 2 2006.201.09:15:37.71#ibcon#about to read 3, iclass 5, count 2 2006.201.09:15:37.74#ibcon#read 3, iclass 5, count 2 2006.201.09:15:37.74#ibcon#about to read 4, iclass 5, count 2 2006.201.09:15:37.74#ibcon#read 4, iclass 5, count 2 2006.201.09:15:37.74#ibcon#about to read 5, iclass 5, count 2 2006.201.09:15:37.74#ibcon#read 5, iclass 5, count 2 2006.201.09:15:37.74#ibcon#about to read 6, iclass 5, count 2 2006.201.09:15:37.74#ibcon#read 6, iclass 5, count 2 2006.201.09:15:37.74#ibcon#end of sib2, iclass 5, count 2 2006.201.09:15:37.74#ibcon#*after write, iclass 5, count 2 2006.201.09:15:37.74#ibcon#*before return 0, iclass 5, count 2 2006.201.09:15:37.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:37.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:37.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.09:15:37.74#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:37.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:37.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:37.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:37.86#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:15:37.86#ibcon#first serial, iclass 5, count 0 2006.201.09:15:37.86#ibcon#enter sib2, iclass 5, count 0 2006.201.09:15:37.86#ibcon#flushed, iclass 5, count 0 2006.201.09:15:37.86#ibcon#about to write, iclass 5, count 0 2006.201.09:15:37.86#ibcon#wrote, iclass 5, count 0 2006.201.09:15:37.86#ibcon#about to read 3, iclass 5, count 0 2006.201.09:15:37.88#ibcon#read 3, iclass 5, count 0 2006.201.09:15:37.88#ibcon#about to read 4, iclass 5, count 0 2006.201.09:15:37.88#ibcon#read 4, iclass 5, count 0 2006.201.09:15:37.88#ibcon#about to read 5, iclass 5, count 0 2006.201.09:15:37.88#ibcon#read 5, iclass 5, count 0 2006.201.09:15:37.88#ibcon#about to read 6, iclass 5, count 0 2006.201.09:15:37.88#ibcon#read 6, iclass 5, count 0 2006.201.09:15:37.88#ibcon#end of sib2, iclass 5, count 0 2006.201.09:15:37.88#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:15:37.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:15:37.88#ibcon#[25=USB\r\n] 2006.201.09:15:37.88#ibcon#*before write, iclass 5, count 0 2006.201.09:15:37.88#ibcon#enter sib2, iclass 5, count 0 2006.201.09:15:37.88#ibcon#flushed, iclass 5, count 0 2006.201.09:15:37.88#ibcon#about to write, iclass 5, count 0 2006.201.09:15:37.88#ibcon#wrote, iclass 5, count 0 2006.201.09:15:37.88#ibcon#about to read 3, iclass 5, count 0 2006.201.09:15:37.91#ibcon#read 3, iclass 5, count 0 2006.201.09:15:37.91#ibcon#about to read 4, iclass 5, count 0 2006.201.09:15:37.91#ibcon#read 4, iclass 5, count 0 2006.201.09:15:37.91#ibcon#about to read 5, iclass 5, count 0 2006.201.09:15:37.91#ibcon#read 5, iclass 5, count 0 2006.201.09:15:37.91#ibcon#about to read 6, iclass 5, count 0 2006.201.09:15:37.91#ibcon#read 6, iclass 5, count 0 2006.201.09:15:37.91#ibcon#end of sib2, iclass 5, count 0 2006.201.09:15:37.91#ibcon#*after write, iclass 5, count 0 2006.201.09:15:37.91#ibcon#*before return 0, iclass 5, count 0 2006.201.09:15:37.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:37.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:37.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:15:37.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:15:37.91$vck44/valo=7,864.99 2006.201.09:15:37.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.09:15:37.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.09:15:37.91#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:37.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:37.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:37.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:37.91#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:15:37.91#ibcon#first serial, iclass 7, count 0 2006.201.09:15:37.91#ibcon#enter sib2, iclass 7, count 0 2006.201.09:15:37.91#ibcon#flushed, iclass 7, count 0 2006.201.09:15:37.91#ibcon#about to write, iclass 7, count 0 2006.201.09:15:37.91#ibcon#wrote, iclass 7, count 0 2006.201.09:15:37.91#ibcon#about to read 3, iclass 7, count 0 2006.201.09:15:37.93#ibcon#read 3, iclass 7, count 0 2006.201.09:15:37.93#ibcon#about to read 4, iclass 7, count 0 2006.201.09:15:37.93#ibcon#read 4, iclass 7, count 0 2006.201.09:15:37.93#ibcon#about to read 5, iclass 7, count 0 2006.201.09:15:37.93#ibcon#read 5, iclass 7, count 0 2006.201.09:15:37.93#ibcon#about to read 6, iclass 7, count 0 2006.201.09:15:37.93#ibcon#read 6, iclass 7, count 0 2006.201.09:15:37.93#ibcon#end of sib2, iclass 7, count 0 2006.201.09:15:37.93#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:15:37.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:15:37.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:15:37.93#ibcon#*before write, iclass 7, count 0 2006.201.09:15:37.93#ibcon#enter sib2, iclass 7, count 0 2006.201.09:15:37.93#ibcon#flushed, iclass 7, count 0 2006.201.09:15:37.93#ibcon#about to write, iclass 7, count 0 2006.201.09:15:37.93#ibcon#wrote, iclass 7, count 0 2006.201.09:15:37.93#ibcon#about to read 3, iclass 7, count 0 2006.201.09:15:37.97#ibcon#read 3, iclass 7, count 0 2006.201.09:15:37.97#ibcon#about to read 4, iclass 7, count 0 2006.201.09:15:37.97#ibcon#read 4, iclass 7, count 0 2006.201.09:15:37.97#ibcon#about to read 5, iclass 7, count 0 2006.201.09:15:37.97#ibcon#read 5, iclass 7, count 0 2006.201.09:15:37.97#ibcon#about to read 6, iclass 7, count 0 2006.201.09:15:37.97#ibcon#read 6, iclass 7, count 0 2006.201.09:15:37.97#ibcon#end of sib2, iclass 7, count 0 2006.201.09:15:37.97#ibcon#*after write, iclass 7, count 0 2006.201.09:15:37.97#ibcon#*before return 0, iclass 7, count 0 2006.201.09:15:37.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:37.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:37.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:15:37.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:15:37.97$vck44/va=7,5 2006.201.09:15:37.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.09:15:37.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.09:15:37.97#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:37.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:38.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:38.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:38.03#ibcon#enter wrdev, iclass 11, count 2 2006.201.09:15:38.03#ibcon#first serial, iclass 11, count 2 2006.201.09:15:38.03#ibcon#enter sib2, iclass 11, count 2 2006.201.09:15:38.03#ibcon#flushed, iclass 11, count 2 2006.201.09:15:38.03#ibcon#about to write, iclass 11, count 2 2006.201.09:15:38.03#ibcon#wrote, iclass 11, count 2 2006.201.09:15:38.03#ibcon#about to read 3, iclass 11, count 2 2006.201.09:15:38.05#ibcon#read 3, iclass 11, count 2 2006.201.09:15:38.05#ibcon#about to read 4, iclass 11, count 2 2006.201.09:15:38.05#ibcon#read 4, iclass 11, count 2 2006.201.09:15:38.05#ibcon#about to read 5, iclass 11, count 2 2006.201.09:15:38.05#ibcon#read 5, iclass 11, count 2 2006.201.09:15:38.05#ibcon#about to read 6, iclass 11, count 2 2006.201.09:15:38.05#ibcon#read 6, iclass 11, count 2 2006.201.09:15:38.05#ibcon#end of sib2, iclass 11, count 2 2006.201.09:15:38.05#ibcon#*mode == 0, iclass 11, count 2 2006.201.09:15:38.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.09:15:38.05#ibcon#[25=AT07-05\r\n] 2006.201.09:15:38.05#ibcon#*before write, iclass 11, count 2 2006.201.09:15:38.05#ibcon#enter sib2, iclass 11, count 2 2006.201.09:15:38.05#ibcon#flushed, iclass 11, count 2 2006.201.09:15:38.05#ibcon#about to write, iclass 11, count 2 2006.201.09:15:38.05#ibcon#wrote, iclass 11, count 2 2006.201.09:15:38.05#ibcon#about to read 3, iclass 11, count 2 2006.201.09:15:38.08#ibcon#read 3, iclass 11, count 2 2006.201.09:15:38.08#ibcon#about to read 4, iclass 11, count 2 2006.201.09:15:38.08#ibcon#read 4, iclass 11, count 2 2006.201.09:15:38.08#ibcon#about to read 5, iclass 11, count 2 2006.201.09:15:38.08#ibcon#read 5, iclass 11, count 2 2006.201.09:15:38.08#ibcon#about to read 6, iclass 11, count 2 2006.201.09:15:38.08#ibcon#read 6, iclass 11, count 2 2006.201.09:15:38.08#ibcon#end of sib2, iclass 11, count 2 2006.201.09:15:38.08#ibcon#*after write, iclass 11, count 2 2006.201.09:15:38.08#ibcon#*before return 0, iclass 11, count 2 2006.201.09:15:38.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:38.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:38.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.09:15:38.08#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:38.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:38.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:38.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:38.20#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:15:38.20#ibcon#first serial, iclass 11, count 0 2006.201.09:15:38.20#ibcon#enter sib2, iclass 11, count 0 2006.201.09:15:38.20#ibcon#flushed, iclass 11, count 0 2006.201.09:15:38.20#ibcon#about to write, iclass 11, count 0 2006.201.09:15:38.20#ibcon#wrote, iclass 11, count 0 2006.201.09:15:38.20#ibcon#about to read 3, iclass 11, count 0 2006.201.09:15:38.22#ibcon#read 3, iclass 11, count 0 2006.201.09:15:38.22#ibcon#about to read 4, iclass 11, count 0 2006.201.09:15:38.22#ibcon#read 4, iclass 11, count 0 2006.201.09:15:38.22#ibcon#about to read 5, iclass 11, count 0 2006.201.09:15:38.22#ibcon#read 5, iclass 11, count 0 2006.201.09:15:38.22#ibcon#about to read 6, iclass 11, count 0 2006.201.09:15:38.22#ibcon#read 6, iclass 11, count 0 2006.201.09:15:38.22#ibcon#end of sib2, iclass 11, count 0 2006.201.09:15:38.22#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:15:38.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:15:38.22#ibcon#[25=USB\r\n] 2006.201.09:15:38.22#ibcon#*before write, iclass 11, count 0 2006.201.09:15:38.22#ibcon#enter sib2, iclass 11, count 0 2006.201.09:15:38.22#ibcon#flushed, iclass 11, count 0 2006.201.09:15:38.22#ibcon#about to write, iclass 11, count 0 2006.201.09:15:38.22#ibcon#wrote, iclass 11, count 0 2006.201.09:15:38.22#ibcon#about to read 3, iclass 11, count 0 2006.201.09:15:38.25#ibcon#read 3, iclass 11, count 0 2006.201.09:15:38.25#ibcon#about to read 4, iclass 11, count 0 2006.201.09:15:38.25#ibcon#read 4, iclass 11, count 0 2006.201.09:15:38.25#ibcon#about to read 5, iclass 11, count 0 2006.201.09:15:38.25#ibcon#read 5, iclass 11, count 0 2006.201.09:15:38.25#ibcon#about to read 6, iclass 11, count 0 2006.201.09:15:38.25#ibcon#read 6, iclass 11, count 0 2006.201.09:15:38.25#ibcon#end of sib2, iclass 11, count 0 2006.201.09:15:38.25#ibcon#*after write, iclass 11, count 0 2006.201.09:15:38.25#ibcon#*before return 0, iclass 11, count 0 2006.201.09:15:38.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:38.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:38.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:15:38.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:15:38.25$vck44/valo=8,884.99 2006.201.09:15:38.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.09:15:38.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.09:15:38.25#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:38.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:38.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:38.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:38.25#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:15:38.25#ibcon#first serial, iclass 13, count 0 2006.201.09:15:38.25#ibcon#enter sib2, iclass 13, count 0 2006.201.09:15:38.25#ibcon#flushed, iclass 13, count 0 2006.201.09:15:38.25#ibcon#about to write, iclass 13, count 0 2006.201.09:15:38.25#ibcon#wrote, iclass 13, count 0 2006.201.09:15:38.25#ibcon#about to read 3, iclass 13, count 0 2006.201.09:15:38.27#ibcon#read 3, iclass 13, count 0 2006.201.09:15:38.27#ibcon#about to read 4, iclass 13, count 0 2006.201.09:15:38.27#ibcon#read 4, iclass 13, count 0 2006.201.09:15:38.27#ibcon#about to read 5, iclass 13, count 0 2006.201.09:15:38.27#ibcon#read 5, iclass 13, count 0 2006.201.09:15:38.27#ibcon#about to read 6, iclass 13, count 0 2006.201.09:15:38.27#ibcon#read 6, iclass 13, count 0 2006.201.09:15:38.27#ibcon#end of sib2, iclass 13, count 0 2006.201.09:15:38.27#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:15:38.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:15:38.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:15:38.27#ibcon#*before write, iclass 13, count 0 2006.201.09:15:38.27#ibcon#enter sib2, iclass 13, count 0 2006.201.09:15:38.27#ibcon#flushed, iclass 13, count 0 2006.201.09:15:38.27#ibcon#about to write, iclass 13, count 0 2006.201.09:15:38.27#ibcon#wrote, iclass 13, count 0 2006.201.09:15:38.27#ibcon#about to read 3, iclass 13, count 0 2006.201.09:15:38.31#ibcon#read 3, iclass 13, count 0 2006.201.09:15:38.31#ibcon#about to read 4, iclass 13, count 0 2006.201.09:15:38.31#ibcon#read 4, iclass 13, count 0 2006.201.09:15:38.31#ibcon#about to read 5, iclass 13, count 0 2006.201.09:15:38.31#ibcon#read 5, iclass 13, count 0 2006.201.09:15:38.31#ibcon#about to read 6, iclass 13, count 0 2006.201.09:15:38.31#ibcon#read 6, iclass 13, count 0 2006.201.09:15:38.31#ibcon#end of sib2, iclass 13, count 0 2006.201.09:15:38.31#ibcon#*after write, iclass 13, count 0 2006.201.09:15:38.31#ibcon#*before return 0, iclass 13, count 0 2006.201.09:15:38.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:38.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:38.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:15:38.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:15:38.31$vck44/va=8,4 2006.201.09:15:38.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.09:15:38.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.09:15:38.31#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:38.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:38.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:38.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:38.37#ibcon#enter wrdev, iclass 15, count 2 2006.201.09:15:38.37#ibcon#first serial, iclass 15, count 2 2006.201.09:15:38.37#ibcon#enter sib2, iclass 15, count 2 2006.201.09:15:38.37#ibcon#flushed, iclass 15, count 2 2006.201.09:15:38.37#ibcon#about to write, iclass 15, count 2 2006.201.09:15:38.37#ibcon#wrote, iclass 15, count 2 2006.201.09:15:38.37#ibcon#about to read 3, iclass 15, count 2 2006.201.09:15:38.39#ibcon#read 3, iclass 15, count 2 2006.201.09:15:38.39#ibcon#about to read 4, iclass 15, count 2 2006.201.09:15:38.39#ibcon#read 4, iclass 15, count 2 2006.201.09:15:38.39#ibcon#about to read 5, iclass 15, count 2 2006.201.09:15:38.39#ibcon#read 5, iclass 15, count 2 2006.201.09:15:38.39#ibcon#about to read 6, iclass 15, count 2 2006.201.09:15:38.39#ibcon#read 6, iclass 15, count 2 2006.201.09:15:38.39#ibcon#end of sib2, iclass 15, count 2 2006.201.09:15:38.39#ibcon#*mode == 0, iclass 15, count 2 2006.201.09:15:38.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.09:15:38.39#ibcon#[25=AT08-04\r\n] 2006.201.09:15:38.39#ibcon#*before write, iclass 15, count 2 2006.201.09:15:38.39#ibcon#enter sib2, iclass 15, count 2 2006.201.09:15:38.39#ibcon#flushed, iclass 15, count 2 2006.201.09:15:38.39#ibcon#about to write, iclass 15, count 2 2006.201.09:15:38.39#ibcon#wrote, iclass 15, count 2 2006.201.09:15:38.39#ibcon#about to read 3, iclass 15, count 2 2006.201.09:15:38.42#ibcon#read 3, iclass 15, count 2 2006.201.09:15:38.42#ibcon#about to read 4, iclass 15, count 2 2006.201.09:15:38.42#ibcon#read 4, iclass 15, count 2 2006.201.09:15:38.42#ibcon#about to read 5, iclass 15, count 2 2006.201.09:15:38.42#ibcon#read 5, iclass 15, count 2 2006.201.09:15:38.42#ibcon#about to read 6, iclass 15, count 2 2006.201.09:15:38.42#ibcon#read 6, iclass 15, count 2 2006.201.09:15:38.42#ibcon#end of sib2, iclass 15, count 2 2006.201.09:15:38.42#ibcon#*after write, iclass 15, count 2 2006.201.09:15:38.42#ibcon#*before return 0, iclass 15, count 2 2006.201.09:15:38.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:38.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:38.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.09:15:38.42#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:38.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:38.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:38.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:38.54#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:15:38.54#ibcon#first serial, iclass 15, count 0 2006.201.09:15:38.54#ibcon#enter sib2, iclass 15, count 0 2006.201.09:15:38.54#ibcon#flushed, iclass 15, count 0 2006.201.09:15:38.54#ibcon#about to write, iclass 15, count 0 2006.201.09:15:38.54#ibcon#wrote, iclass 15, count 0 2006.201.09:15:38.54#ibcon#about to read 3, iclass 15, count 0 2006.201.09:15:38.56#ibcon#read 3, iclass 15, count 0 2006.201.09:15:38.56#ibcon#about to read 4, iclass 15, count 0 2006.201.09:15:38.56#ibcon#read 4, iclass 15, count 0 2006.201.09:15:38.56#ibcon#about to read 5, iclass 15, count 0 2006.201.09:15:38.56#ibcon#read 5, iclass 15, count 0 2006.201.09:15:38.56#ibcon#about to read 6, iclass 15, count 0 2006.201.09:15:38.56#ibcon#read 6, iclass 15, count 0 2006.201.09:15:38.56#ibcon#end of sib2, iclass 15, count 0 2006.201.09:15:38.56#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:15:38.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:15:38.56#ibcon#[25=USB\r\n] 2006.201.09:15:38.56#ibcon#*before write, iclass 15, count 0 2006.201.09:15:38.56#ibcon#enter sib2, iclass 15, count 0 2006.201.09:15:38.56#ibcon#flushed, iclass 15, count 0 2006.201.09:15:38.56#ibcon#about to write, iclass 15, count 0 2006.201.09:15:38.56#ibcon#wrote, iclass 15, count 0 2006.201.09:15:38.56#ibcon#about to read 3, iclass 15, count 0 2006.201.09:15:38.59#ibcon#read 3, iclass 15, count 0 2006.201.09:15:38.59#ibcon#about to read 4, iclass 15, count 0 2006.201.09:15:38.59#ibcon#read 4, iclass 15, count 0 2006.201.09:15:38.59#ibcon#about to read 5, iclass 15, count 0 2006.201.09:15:38.59#ibcon#read 5, iclass 15, count 0 2006.201.09:15:38.59#ibcon#about to read 6, iclass 15, count 0 2006.201.09:15:38.59#ibcon#read 6, iclass 15, count 0 2006.201.09:15:38.59#ibcon#end of sib2, iclass 15, count 0 2006.201.09:15:38.59#ibcon#*after write, iclass 15, count 0 2006.201.09:15:38.59#ibcon#*before return 0, iclass 15, count 0 2006.201.09:15:38.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:38.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:38.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:15:38.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:15:38.59$vck44/vblo=1,629.99 2006.201.09:15:38.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.09:15:38.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.09:15:38.59#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:38.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:38.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:38.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:38.59#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:15:38.59#ibcon#first serial, iclass 17, count 0 2006.201.09:15:38.59#ibcon#enter sib2, iclass 17, count 0 2006.201.09:15:38.59#ibcon#flushed, iclass 17, count 0 2006.201.09:15:38.59#ibcon#about to write, iclass 17, count 0 2006.201.09:15:38.59#ibcon#wrote, iclass 17, count 0 2006.201.09:15:38.59#ibcon#about to read 3, iclass 17, count 0 2006.201.09:15:38.61#ibcon#read 3, iclass 17, count 0 2006.201.09:15:38.61#ibcon#about to read 4, iclass 17, count 0 2006.201.09:15:38.61#ibcon#read 4, iclass 17, count 0 2006.201.09:15:38.61#ibcon#about to read 5, iclass 17, count 0 2006.201.09:15:38.61#ibcon#read 5, iclass 17, count 0 2006.201.09:15:38.61#ibcon#about to read 6, iclass 17, count 0 2006.201.09:15:38.61#ibcon#read 6, iclass 17, count 0 2006.201.09:15:38.61#ibcon#end of sib2, iclass 17, count 0 2006.201.09:15:38.61#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:15:38.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:15:38.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:15:38.61#ibcon#*before write, iclass 17, count 0 2006.201.09:15:38.61#ibcon#enter sib2, iclass 17, count 0 2006.201.09:15:38.61#ibcon#flushed, iclass 17, count 0 2006.201.09:15:38.61#ibcon#about to write, iclass 17, count 0 2006.201.09:15:38.61#ibcon#wrote, iclass 17, count 0 2006.201.09:15:38.61#ibcon#about to read 3, iclass 17, count 0 2006.201.09:15:38.65#ibcon#read 3, iclass 17, count 0 2006.201.09:15:38.65#ibcon#about to read 4, iclass 17, count 0 2006.201.09:15:38.65#ibcon#read 4, iclass 17, count 0 2006.201.09:15:38.65#ibcon#about to read 5, iclass 17, count 0 2006.201.09:15:38.65#ibcon#read 5, iclass 17, count 0 2006.201.09:15:38.65#ibcon#about to read 6, iclass 17, count 0 2006.201.09:15:38.65#ibcon#read 6, iclass 17, count 0 2006.201.09:15:38.65#ibcon#end of sib2, iclass 17, count 0 2006.201.09:15:38.65#ibcon#*after write, iclass 17, count 0 2006.201.09:15:38.65#ibcon#*before return 0, iclass 17, count 0 2006.201.09:15:38.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:38.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:38.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:15:38.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:15:38.65$vck44/vb=1,4 2006.201.09:15:38.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.09:15:38.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.09:15:38.65#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:38.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:15:38.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:15:38.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:15:38.65#ibcon#enter wrdev, iclass 19, count 2 2006.201.09:15:38.65#ibcon#first serial, iclass 19, count 2 2006.201.09:15:38.65#ibcon#enter sib2, iclass 19, count 2 2006.201.09:15:38.65#ibcon#flushed, iclass 19, count 2 2006.201.09:15:38.65#ibcon#about to write, iclass 19, count 2 2006.201.09:15:38.65#ibcon#wrote, iclass 19, count 2 2006.201.09:15:38.65#ibcon#about to read 3, iclass 19, count 2 2006.201.09:15:38.67#ibcon#read 3, iclass 19, count 2 2006.201.09:15:38.67#ibcon#about to read 4, iclass 19, count 2 2006.201.09:15:38.67#ibcon#read 4, iclass 19, count 2 2006.201.09:15:38.67#ibcon#about to read 5, iclass 19, count 2 2006.201.09:15:38.67#ibcon#read 5, iclass 19, count 2 2006.201.09:15:38.67#ibcon#about to read 6, iclass 19, count 2 2006.201.09:15:38.67#ibcon#read 6, iclass 19, count 2 2006.201.09:15:38.67#ibcon#end of sib2, iclass 19, count 2 2006.201.09:15:38.67#ibcon#*mode == 0, iclass 19, count 2 2006.201.09:15:38.67#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.09:15:38.67#ibcon#[27=AT01-04\r\n] 2006.201.09:15:38.67#ibcon#*before write, iclass 19, count 2 2006.201.09:15:38.67#ibcon#enter sib2, iclass 19, count 2 2006.201.09:15:38.67#ibcon#flushed, iclass 19, count 2 2006.201.09:15:38.67#ibcon#about to write, iclass 19, count 2 2006.201.09:15:38.67#ibcon#wrote, iclass 19, count 2 2006.201.09:15:38.67#ibcon#about to read 3, iclass 19, count 2 2006.201.09:15:38.70#ibcon#read 3, iclass 19, count 2 2006.201.09:15:38.70#ibcon#about to read 4, iclass 19, count 2 2006.201.09:15:38.70#ibcon#read 4, iclass 19, count 2 2006.201.09:15:38.70#ibcon#about to read 5, iclass 19, count 2 2006.201.09:15:38.70#ibcon#read 5, iclass 19, count 2 2006.201.09:15:38.70#ibcon#about to read 6, iclass 19, count 2 2006.201.09:15:38.70#ibcon#read 6, iclass 19, count 2 2006.201.09:15:38.70#ibcon#end of sib2, iclass 19, count 2 2006.201.09:15:38.70#ibcon#*after write, iclass 19, count 2 2006.201.09:15:38.70#ibcon#*before return 0, iclass 19, count 2 2006.201.09:15:38.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:15:38.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:15:38.70#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.09:15:38.70#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:38.70#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:15:38.82#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:15:38.82#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:15:38.82#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:15:38.82#ibcon#first serial, iclass 19, count 0 2006.201.09:15:38.82#ibcon#enter sib2, iclass 19, count 0 2006.201.09:15:38.82#ibcon#flushed, iclass 19, count 0 2006.201.09:15:38.82#ibcon#about to write, iclass 19, count 0 2006.201.09:15:38.82#ibcon#wrote, iclass 19, count 0 2006.201.09:15:38.82#ibcon#about to read 3, iclass 19, count 0 2006.201.09:15:38.84#ibcon#read 3, iclass 19, count 0 2006.201.09:15:38.84#ibcon#about to read 4, iclass 19, count 0 2006.201.09:15:38.84#ibcon#read 4, iclass 19, count 0 2006.201.09:15:38.84#ibcon#about to read 5, iclass 19, count 0 2006.201.09:15:38.84#ibcon#read 5, iclass 19, count 0 2006.201.09:15:38.84#ibcon#about to read 6, iclass 19, count 0 2006.201.09:15:38.84#ibcon#read 6, iclass 19, count 0 2006.201.09:15:38.84#ibcon#end of sib2, iclass 19, count 0 2006.201.09:15:38.84#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:15:38.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:15:38.84#ibcon#[27=USB\r\n] 2006.201.09:15:38.84#ibcon#*before write, iclass 19, count 0 2006.201.09:15:38.84#ibcon#enter sib2, iclass 19, count 0 2006.201.09:15:38.84#ibcon#flushed, iclass 19, count 0 2006.201.09:15:38.84#ibcon#about to write, iclass 19, count 0 2006.201.09:15:38.84#ibcon#wrote, iclass 19, count 0 2006.201.09:15:38.84#ibcon#about to read 3, iclass 19, count 0 2006.201.09:15:38.87#ibcon#read 3, iclass 19, count 0 2006.201.09:15:38.87#ibcon#about to read 4, iclass 19, count 0 2006.201.09:15:38.87#ibcon#read 4, iclass 19, count 0 2006.201.09:15:38.87#ibcon#about to read 5, iclass 19, count 0 2006.201.09:15:38.87#ibcon#read 5, iclass 19, count 0 2006.201.09:15:38.87#ibcon#about to read 6, iclass 19, count 0 2006.201.09:15:38.87#ibcon#read 6, iclass 19, count 0 2006.201.09:15:38.87#ibcon#end of sib2, iclass 19, count 0 2006.201.09:15:38.87#ibcon#*after write, iclass 19, count 0 2006.201.09:15:38.87#ibcon#*before return 0, iclass 19, count 0 2006.201.09:15:38.87#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:15:38.87#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:15:38.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:15:38.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:15:38.87$vck44/vblo=2,634.99 2006.201.09:15:38.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.09:15:38.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.09:15:38.87#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:38.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:38.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:38.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:38.87#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:15:38.87#ibcon#first serial, iclass 21, count 0 2006.201.09:15:38.87#ibcon#enter sib2, iclass 21, count 0 2006.201.09:15:38.87#ibcon#flushed, iclass 21, count 0 2006.201.09:15:38.87#ibcon#about to write, iclass 21, count 0 2006.201.09:15:38.87#ibcon#wrote, iclass 21, count 0 2006.201.09:15:38.87#ibcon#about to read 3, iclass 21, count 0 2006.201.09:15:38.89#ibcon#read 3, iclass 21, count 0 2006.201.09:15:38.89#ibcon#about to read 4, iclass 21, count 0 2006.201.09:15:38.89#ibcon#read 4, iclass 21, count 0 2006.201.09:15:38.89#ibcon#about to read 5, iclass 21, count 0 2006.201.09:15:38.89#ibcon#read 5, iclass 21, count 0 2006.201.09:15:38.89#ibcon#about to read 6, iclass 21, count 0 2006.201.09:15:38.89#ibcon#read 6, iclass 21, count 0 2006.201.09:15:38.89#ibcon#end of sib2, iclass 21, count 0 2006.201.09:15:38.89#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:15:38.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:15:38.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:15:38.89#ibcon#*before write, iclass 21, count 0 2006.201.09:15:38.89#ibcon#enter sib2, iclass 21, count 0 2006.201.09:15:38.89#ibcon#flushed, iclass 21, count 0 2006.201.09:15:38.89#ibcon#about to write, iclass 21, count 0 2006.201.09:15:38.89#ibcon#wrote, iclass 21, count 0 2006.201.09:15:38.89#ibcon#about to read 3, iclass 21, count 0 2006.201.09:15:38.93#ibcon#read 3, iclass 21, count 0 2006.201.09:15:38.93#ibcon#about to read 4, iclass 21, count 0 2006.201.09:15:38.93#ibcon#read 4, iclass 21, count 0 2006.201.09:15:38.93#ibcon#about to read 5, iclass 21, count 0 2006.201.09:15:38.93#ibcon#read 5, iclass 21, count 0 2006.201.09:15:38.93#ibcon#about to read 6, iclass 21, count 0 2006.201.09:15:38.93#ibcon#read 6, iclass 21, count 0 2006.201.09:15:38.93#ibcon#end of sib2, iclass 21, count 0 2006.201.09:15:38.93#ibcon#*after write, iclass 21, count 0 2006.201.09:15:38.93#ibcon#*before return 0, iclass 21, count 0 2006.201.09:15:38.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:38.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:15:38.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:15:38.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:15:38.93$vck44/vb=2,5 2006.201.09:15:38.93#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.09:15:38.93#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.09:15:38.93#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:38.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:38.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:38.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:38.99#ibcon#enter wrdev, iclass 23, count 2 2006.201.09:15:38.99#ibcon#first serial, iclass 23, count 2 2006.201.09:15:38.99#ibcon#enter sib2, iclass 23, count 2 2006.201.09:15:38.99#ibcon#flushed, iclass 23, count 2 2006.201.09:15:38.99#ibcon#about to write, iclass 23, count 2 2006.201.09:15:38.99#ibcon#wrote, iclass 23, count 2 2006.201.09:15:38.99#ibcon#about to read 3, iclass 23, count 2 2006.201.09:15:39.01#ibcon#read 3, iclass 23, count 2 2006.201.09:15:39.01#ibcon#about to read 4, iclass 23, count 2 2006.201.09:15:39.01#ibcon#read 4, iclass 23, count 2 2006.201.09:15:39.01#ibcon#about to read 5, iclass 23, count 2 2006.201.09:15:39.01#ibcon#read 5, iclass 23, count 2 2006.201.09:15:39.01#ibcon#about to read 6, iclass 23, count 2 2006.201.09:15:39.01#ibcon#read 6, iclass 23, count 2 2006.201.09:15:39.01#ibcon#end of sib2, iclass 23, count 2 2006.201.09:15:39.01#ibcon#*mode == 0, iclass 23, count 2 2006.201.09:15:39.01#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.09:15:39.01#ibcon#[27=AT02-05\r\n] 2006.201.09:15:39.01#ibcon#*before write, iclass 23, count 2 2006.201.09:15:39.01#ibcon#enter sib2, iclass 23, count 2 2006.201.09:15:39.01#ibcon#flushed, iclass 23, count 2 2006.201.09:15:39.01#ibcon#about to write, iclass 23, count 2 2006.201.09:15:39.01#ibcon#wrote, iclass 23, count 2 2006.201.09:15:39.01#ibcon#about to read 3, iclass 23, count 2 2006.201.09:15:39.04#ibcon#read 3, iclass 23, count 2 2006.201.09:15:39.04#ibcon#about to read 4, iclass 23, count 2 2006.201.09:15:39.04#ibcon#read 4, iclass 23, count 2 2006.201.09:15:39.04#ibcon#about to read 5, iclass 23, count 2 2006.201.09:15:39.04#ibcon#read 5, iclass 23, count 2 2006.201.09:15:39.04#ibcon#about to read 6, iclass 23, count 2 2006.201.09:15:39.04#ibcon#read 6, iclass 23, count 2 2006.201.09:15:39.04#ibcon#end of sib2, iclass 23, count 2 2006.201.09:15:39.04#ibcon#*after write, iclass 23, count 2 2006.201.09:15:39.04#ibcon#*before return 0, iclass 23, count 2 2006.201.09:15:39.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:39.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:15:39.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.09:15:39.04#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:39.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:39.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:39.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:39.16#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:15:39.16#ibcon#first serial, iclass 23, count 0 2006.201.09:15:39.16#ibcon#enter sib2, iclass 23, count 0 2006.201.09:15:39.16#ibcon#flushed, iclass 23, count 0 2006.201.09:15:39.16#ibcon#about to write, iclass 23, count 0 2006.201.09:15:39.16#ibcon#wrote, iclass 23, count 0 2006.201.09:15:39.16#ibcon#about to read 3, iclass 23, count 0 2006.201.09:15:39.18#ibcon#read 3, iclass 23, count 0 2006.201.09:15:39.18#ibcon#about to read 4, iclass 23, count 0 2006.201.09:15:39.18#ibcon#read 4, iclass 23, count 0 2006.201.09:15:39.18#ibcon#about to read 5, iclass 23, count 0 2006.201.09:15:39.18#ibcon#read 5, iclass 23, count 0 2006.201.09:15:39.18#ibcon#about to read 6, iclass 23, count 0 2006.201.09:15:39.18#ibcon#read 6, iclass 23, count 0 2006.201.09:15:39.18#ibcon#end of sib2, iclass 23, count 0 2006.201.09:15:39.18#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:15:39.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:15:39.18#ibcon#[27=USB\r\n] 2006.201.09:15:39.18#ibcon#*before write, iclass 23, count 0 2006.201.09:15:39.18#ibcon#enter sib2, iclass 23, count 0 2006.201.09:15:39.18#ibcon#flushed, iclass 23, count 0 2006.201.09:15:39.18#ibcon#about to write, iclass 23, count 0 2006.201.09:15:39.18#ibcon#wrote, iclass 23, count 0 2006.201.09:15:39.18#ibcon#about to read 3, iclass 23, count 0 2006.201.09:15:39.21#ibcon#read 3, iclass 23, count 0 2006.201.09:15:39.21#ibcon#about to read 4, iclass 23, count 0 2006.201.09:15:39.21#ibcon#read 4, iclass 23, count 0 2006.201.09:15:39.21#ibcon#about to read 5, iclass 23, count 0 2006.201.09:15:39.21#ibcon#read 5, iclass 23, count 0 2006.201.09:15:39.21#ibcon#about to read 6, iclass 23, count 0 2006.201.09:15:39.21#ibcon#read 6, iclass 23, count 0 2006.201.09:15:39.21#ibcon#end of sib2, iclass 23, count 0 2006.201.09:15:39.21#ibcon#*after write, iclass 23, count 0 2006.201.09:15:39.21#ibcon#*before return 0, iclass 23, count 0 2006.201.09:15:39.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:39.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:15:39.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:15:39.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:15:39.21$vck44/vblo=3,649.99 2006.201.09:15:39.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.09:15:39.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.09:15:39.21#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:39.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:39.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:39.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:39.21#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:15:39.21#ibcon#first serial, iclass 25, count 0 2006.201.09:15:39.21#ibcon#enter sib2, iclass 25, count 0 2006.201.09:15:39.21#ibcon#flushed, iclass 25, count 0 2006.201.09:15:39.21#ibcon#about to write, iclass 25, count 0 2006.201.09:15:39.21#ibcon#wrote, iclass 25, count 0 2006.201.09:15:39.21#ibcon#about to read 3, iclass 25, count 0 2006.201.09:15:39.23#ibcon#read 3, iclass 25, count 0 2006.201.09:15:39.23#ibcon#about to read 4, iclass 25, count 0 2006.201.09:15:39.23#ibcon#read 4, iclass 25, count 0 2006.201.09:15:39.23#ibcon#about to read 5, iclass 25, count 0 2006.201.09:15:39.23#ibcon#read 5, iclass 25, count 0 2006.201.09:15:39.23#ibcon#about to read 6, iclass 25, count 0 2006.201.09:15:39.23#ibcon#read 6, iclass 25, count 0 2006.201.09:15:39.23#ibcon#end of sib2, iclass 25, count 0 2006.201.09:15:39.23#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:15:39.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:15:39.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:15:39.23#ibcon#*before write, iclass 25, count 0 2006.201.09:15:39.23#ibcon#enter sib2, iclass 25, count 0 2006.201.09:15:39.23#ibcon#flushed, iclass 25, count 0 2006.201.09:15:39.23#ibcon#about to write, iclass 25, count 0 2006.201.09:15:39.23#ibcon#wrote, iclass 25, count 0 2006.201.09:15:39.23#ibcon#about to read 3, iclass 25, count 0 2006.201.09:15:39.27#ibcon#read 3, iclass 25, count 0 2006.201.09:15:39.27#ibcon#about to read 4, iclass 25, count 0 2006.201.09:15:39.27#ibcon#read 4, iclass 25, count 0 2006.201.09:15:39.27#ibcon#about to read 5, iclass 25, count 0 2006.201.09:15:39.27#ibcon#read 5, iclass 25, count 0 2006.201.09:15:39.27#ibcon#about to read 6, iclass 25, count 0 2006.201.09:15:39.27#ibcon#read 6, iclass 25, count 0 2006.201.09:15:39.27#ibcon#end of sib2, iclass 25, count 0 2006.201.09:15:39.27#ibcon#*after write, iclass 25, count 0 2006.201.09:15:39.27#ibcon#*before return 0, iclass 25, count 0 2006.201.09:15:39.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:39.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:15:39.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:15:39.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:15:39.27$vck44/vb=3,4 2006.201.09:15:39.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.09:15:39.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.09:15:39.27#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:39.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:39.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:39.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:39.33#ibcon#enter wrdev, iclass 27, count 2 2006.201.09:15:39.33#ibcon#first serial, iclass 27, count 2 2006.201.09:15:39.33#ibcon#enter sib2, iclass 27, count 2 2006.201.09:15:39.33#ibcon#flushed, iclass 27, count 2 2006.201.09:15:39.33#ibcon#about to write, iclass 27, count 2 2006.201.09:15:39.33#ibcon#wrote, iclass 27, count 2 2006.201.09:15:39.33#ibcon#about to read 3, iclass 27, count 2 2006.201.09:15:39.35#ibcon#read 3, iclass 27, count 2 2006.201.09:15:39.35#ibcon#about to read 4, iclass 27, count 2 2006.201.09:15:39.35#ibcon#read 4, iclass 27, count 2 2006.201.09:15:39.35#ibcon#about to read 5, iclass 27, count 2 2006.201.09:15:39.35#ibcon#read 5, iclass 27, count 2 2006.201.09:15:39.35#ibcon#about to read 6, iclass 27, count 2 2006.201.09:15:39.35#ibcon#read 6, iclass 27, count 2 2006.201.09:15:39.35#ibcon#end of sib2, iclass 27, count 2 2006.201.09:15:39.35#ibcon#*mode == 0, iclass 27, count 2 2006.201.09:15:39.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.09:15:39.35#ibcon#[27=AT03-04\r\n] 2006.201.09:15:39.35#ibcon#*before write, iclass 27, count 2 2006.201.09:15:39.35#ibcon#enter sib2, iclass 27, count 2 2006.201.09:15:39.35#ibcon#flushed, iclass 27, count 2 2006.201.09:15:39.35#ibcon#about to write, iclass 27, count 2 2006.201.09:15:39.35#ibcon#wrote, iclass 27, count 2 2006.201.09:15:39.35#ibcon#about to read 3, iclass 27, count 2 2006.201.09:15:39.38#ibcon#read 3, iclass 27, count 2 2006.201.09:15:39.38#ibcon#about to read 4, iclass 27, count 2 2006.201.09:15:39.38#ibcon#read 4, iclass 27, count 2 2006.201.09:15:39.38#ibcon#about to read 5, iclass 27, count 2 2006.201.09:15:39.38#ibcon#read 5, iclass 27, count 2 2006.201.09:15:39.38#ibcon#about to read 6, iclass 27, count 2 2006.201.09:15:39.38#ibcon#read 6, iclass 27, count 2 2006.201.09:15:39.38#ibcon#end of sib2, iclass 27, count 2 2006.201.09:15:39.38#ibcon#*after write, iclass 27, count 2 2006.201.09:15:39.38#ibcon#*before return 0, iclass 27, count 2 2006.201.09:15:39.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:39.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:15:39.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.09:15:39.38#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:39.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:39.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:39.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:39.50#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:15:39.50#ibcon#first serial, iclass 27, count 0 2006.201.09:15:39.50#ibcon#enter sib2, iclass 27, count 0 2006.201.09:15:39.50#ibcon#flushed, iclass 27, count 0 2006.201.09:15:39.50#ibcon#about to write, iclass 27, count 0 2006.201.09:15:39.50#ibcon#wrote, iclass 27, count 0 2006.201.09:15:39.50#ibcon#about to read 3, iclass 27, count 0 2006.201.09:15:39.52#ibcon#read 3, iclass 27, count 0 2006.201.09:15:39.52#ibcon#about to read 4, iclass 27, count 0 2006.201.09:15:39.52#ibcon#read 4, iclass 27, count 0 2006.201.09:15:39.52#ibcon#about to read 5, iclass 27, count 0 2006.201.09:15:39.52#ibcon#read 5, iclass 27, count 0 2006.201.09:15:39.52#ibcon#about to read 6, iclass 27, count 0 2006.201.09:15:39.52#ibcon#read 6, iclass 27, count 0 2006.201.09:15:39.52#ibcon#end of sib2, iclass 27, count 0 2006.201.09:15:39.52#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:15:39.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:15:39.52#ibcon#[27=USB\r\n] 2006.201.09:15:39.52#ibcon#*before write, iclass 27, count 0 2006.201.09:15:39.52#ibcon#enter sib2, iclass 27, count 0 2006.201.09:15:39.52#ibcon#flushed, iclass 27, count 0 2006.201.09:15:39.52#ibcon#about to write, iclass 27, count 0 2006.201.09:15:39.52#ibcon#wrote, iclass 27, count 0 2006.201.09:15:39.52#ibcon#about to read 3, iclass 27, count 0 2006.201.09:15:39.55#ibcon#read 3, iclass 27, count 0 2006.201.09:15:39.55#ibcon#about to read 4, iclass 27, count 0 2006.201.09:15:39.55#ibcon#read 4, iclass 27, count 0 2006.201.09:15:39.55#ibcon#about to read 5, iclass 27, count 0 2006.201.09:15:39.55#ibcon#read 5, iclass 27, count 0 2006.201.09:15:39.55#ibcon#about to read 6, iclass 27, count 0 2006.201.09:15:39.55#ibcon#read 6, iclass 27, count 0 2006.201.09:15:39.55#ibcon#end of sib2, iclass 27, count 0 2006.201.09:15:39.55#ibcon#*after write, iclass 27, count 0 2006.201.09:15:39.55#ibcon#*before return 0, iclass 27, count 0 2006.201.09:15:39.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:39.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:15:39.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:15:39.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:15:39.55$vck44/vblo=4,679.99 2006.201.09:15:39.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.09:15:39.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.09:15:39.55#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:39.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:39.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:39.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:39.55#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:15:39.55#ibcon#first serial, iclass 29, count 0 2006.201.09:15:39.55#ibcon#enter sib2, iclass 29, count 0 2006.201.09:15:39.55#ibcon#flushed, iclass 29, count 0 2006.201.09:15:39.55#ibcon#about to write, iclass 29, count 0 2006.201.09:15:39.55#ibcon#wrote, iclass 29, count 0 2006.201.09:15:39.55#ibcon#about to read 3, iclass 29, count 0 2006.201.09:15:39.57#ibcon#read 3, iclass 29, count 0 2006.201.09:15:39.57#ibcon#about to read 4, iclass 29, count 0 2006.201.09:15:39.57#ibcon#read 4, iclass 29, count 0 2006.201.09:15:39.57#ibcon#about to read 5, iclass 29, count 0 2006.201.09:15:39.57#ibcon#read 5, iclass 29, count 0 2006.201.09:15:39.57#ibcon#about to read 6, iclass 29, count 0 2006.201.09:15:39.57#ibcon#read 6, iclass 29, count 0 2006.201.09:15:39.57#ibcon#end of sib2, iclass 29, count 0 2006.201.09:15:39.57#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:15:39.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:15:39.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:15:39.57#ibcon#*before write, iclass 29, count 0 2006.201.09:15:39.57#ibcon#enter sib2, iclass 29, count 0 2006.201.09:15:39.57#ibcon#flushed, iclass 29, count 0 2006.201.09:15:39.57#ibcon#about to write, iclass 29, count 0 2006.201.09:15:39.57#ibcon#wrote, iclass 29, count 0 2006.201.09:15:39.57#ibcon#about to read 3, iclass 29, count 0 2006.201.09:15:39.62#ibcon#read 3, iclass 29, count 0 2006.201.09:15:39.62#ibcon#about to read 4, iclass 29, count 0 2006.201.09:15:39.62#ibcon#read 4, iclass 29, count 0 2006.201.09:15:39.62#ibcon#about to read 5, iclass 29, count 0 2006.201.09:15:39.62#ibcon#read 5, iclass 29, count 0 2006.201.09:15:39.62#ibcon#about to read 6, iclass 29, count 0 2006.201.09:15:39.62#ibcon#read 6, iclass 29, count 0 2006.201.09:15:39.62#ibcon#end of sib2, iclass 29, count 0 2006.201.09:15:39.62#ibcon#*after write, iclass 29, count 0 2006.201.09:15:39.62#ibcon#*before return 0, iclass 29, count 0 2006.201.09:15:39.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:39.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:15:39.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:15:39.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:15:39.62$vck44/vb=4,5 2006.201.09:15:39.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.09:15:39.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.09:15:39.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:39.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:39.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:39.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:39.67#ibcon#enter wrdev, iclass 31, count 2 2006.201.09:15:39.67#ibcon#first serial, iclass 31, count 2 2006.201.09:15:39.67#ibcon#enter sib2, iclass 31, count 2 2006.201.09:15:39.67#ibcon#flushed, iclass 31, count 2 2006.201.09:15:39.67#ibcon#about to write, iclass 31, count 2 2006.201.09:15:39.67#ibcon#wrote, iclass 31, count 2 2006.201.09:15:39.67#ibcon#about to read 3, iclass 31, count 2 2006.201.09:15:39.69#ibcon#read 3, iclass 31, count 2 2006.201.09:15:39.69#ibcon#about to read 4, iclass 31, count 2 2006.201.09:15:39.69#ibcon#read 4, iclass 31, count 2 2006.201.09:15:39.69#ibcon#about to read 5, iclass 31, count 2 2006.201.09:15:39.69#ibcon#read 5, iclass 31, count 2 2006.201.09:15:39.69#ibcon#about to read 6, iclass 31, count 2 2006.201.09:15:39.69#ibcon#read 6, iclass 31, count 2 2006.201.09:15:39.69#ibcon#end of sib2, iclass 31, count 2 2006.201.09:15:39.69#ibcon#*mode == 0, iclass 31, count 2 2006.201.09:15:39.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.09:15:39.69#ibcon#[27=AT04-05\r\n] 2006.201.09:15:39.69#ibcon#*before write, iclass 31, count 2 2006.201.09:15:39.69#ibcon#enter sib2, iclass 31, count 2 2006.201.09:15:39.69#ibcon#flushed, iclass 31, count 2 2006.201.09:15:39.69#ibcon#about to write, iclass 31, count 2 2006.201.09:15:39.69#ibcon#wrote, iclass 31, count 2 2006.201.09:15:39.69#ibcon#about to read 3, iclass 31, count 2 2006.201.09:15:39.72#ibcon#read 3, iclass 31, count 2 2006.201.09:15:39.72#ibcon#about to read 4, iclass 31, count 2 2006.201.09:15:39.72#ibcon#read 4, iclass 31, count 2 2006.201.09:15:39.72#ibcon#about to read 5, iclass 31, count 2 2006.201.09:15:39.72#ibcon#read 5, iclass 31, count 2 2006.201.09:15:39.72#ibcon#about to read 6, iclass 31, count 2 2006.201.09:15:39.72#ibcon#read 6, iclass 31, count 2 2006.201.09:15:39.72#ibcon#end of sib2, iclass 31, count 2 2006.201.09:15:39.72#ibcon#*after write, iclass 31, count 2 2006.201.09:15:39.72#ibcon#*before return 0, iclass 31, count 2 2006.201.09:15:39.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:39.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:15:39.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.09:15:39.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:39.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:39.84#abcon#<5=/05 2.4 4.9 22.81 901003.8\r\n> 2006.201.09:15:39.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:39.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:39.84#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:15:39.84#ibcon#first serial, iclass 31, count 0 2006.201.09:15:39.84#ibcon#enter sib2, iclass 31, count 0 2006.201.09:15:39.84#ibcon#flushed, iclass 31, count 0 2006.201.09:15:39.84#ibcon#about to write, iclass 31, count 0 2006.201.09:15:39.84#ibcon#wrote, iclass 31, count 0 2006.201.09:15:39.84#ibcon#about to read 3, iclass 31, count 0 2006.201.09:15:39.86#ibcon#read 3, iclass 31, count 0 2006.201.09:15:39.86#ibcon#about to read 4, iclass 31, count 0 2006.201.09:15:39.86#ibcon#read 4, iclass 31, count 0 2006.201.09:15:39.86#ibcon#about to read 5, iclass 31, count 0 2006.201.09:15:39.86#ibcon#read 5, iclass 31, count 0 2006.201.09:15:39.86#ibcon#about to read 6, iclass 31, count 0 2006.201.09:15:39.86#ibcon#read 6, iclass 31, count 0 2006.201.09:15:39.86#ibcon#end of sib2, iclass 31, count 0 2006.201.09:15:39.86#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:15:39.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:15:39.86#ibcon#[27=USB\r\n] 2006.201.09:15:39.86#ibcon#*before write, iclass 31, count 0 2006.201.09:15:39.86#ibcon#enter sib2, iclass 31, count 0 2006.201.09:15:39.86#ibcon#flushed, iclass 31, count 0 2006.201.09:15:39.86#ibcon#about to write, iclass 31, count 0 2006.201.09:15:39.86#ibcon#wrote, iclass 31, count 0 2006.201.09:15:39.86#ibcon#about to read 3, iclass 31, count 0 2006.201.09:15:39.86#abcon#{5=INTERFACE CLEAR} 2006.201.09:15:39.89#ibcon#read 3, iclass 31, count 0 2006.201.09:15:39.89#ibcon#about to read 4, iclass 31, count 0 2006.201.09:15:39.89#ibcon#read 4, iclass 31, count 0 2006.201.09:15:39.89#ibcon#about to read 5, iclass 31, count 0 2006.201.09:15:39.89#ibcon#read 5, iclass 31, count 0 2006.201.09:15:39.89#ibcon#about to read 6, iclass 31, count 0 2006.201.09:15:39.89#ibcon#read 6, iclass 31, count 0 2006.201.09:15:39.89#ibcon#end of sib2, iclass 31, count 0 2006.201.09:15:39.89#ibcon#*after write, iclass 31, count 0 2006.201.09:15:39.89#ibcon#*before return 0, iclass 31, count 0 2006.201.09:15:39.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:39.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:15:39.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:15:39.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:15:39.89$vck44/vblo=5,709.99 2006.201.09:15:39.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.09:15:39.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.09:15:39.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:39.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:15:39.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:15:39.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:15:39.89#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:15:39.89#ibcon#first serial, iclass 36, count 0 2006.201.09:15:39.89#ibcon#enter sib2, iclass 36, count 0 2006.201.09:15:39.89#ibcon#flushed, iclass 36, count 0 2006.201.09:15:39.89#ibcon#about to write, iclass 36, count 0 2006.201.09:15:39.89#ibcon#wrote, iclass 36, count 0 2006.201.09:15:39.89#ibcon#about to read 3, iclass 36, count 0 2006.201.09:15:39.91#ibcon#read 3, iclass 36, count 0 2006.201.09:15:39.91#ibcon#about to read 4, iclass 36, count 0 2006.201.09:15:39.91#ibcon#read 4, iclass 36, count 0 2006.201.09:15:39.91#ibcon#about to read 5, iclass 36, count 0 2006.201.09:15:39.91#ibcon#read 5, iclass 36, count 0 2006.201.09:15:39.91#ibcon#about to read 6, iclass 36, count 0 2006.201.09:15:39.91#ibcon#read 6, iclass 36, count 0 2006.201.09:15:39.91#ibcon#end of sib2, iclass 36, count 0 2006.201.09:15:39.91#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:15:39.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:15:39.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:15:39.91#ibcon#*before write, iclass 36, count 0 2006.201.09:15:39.91#ibcon#enter sib2, iclass 36, count 0 2006.201.09:15:39.91#ibcon#flushed, iclass 36, count 0 2006.201.09:15:39.91#ibcon#about to write, iclass 36, count 0 2006.201.09:15:39.91#ibcon#wrote, iclass 36, count 0 2006.201.09:15:39.91#ibcon#about to read 3, iclass 36, count 0 2006.201.09:15:39.92#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:15:39.95#ibcon#read 3, iclass 36, count 0 2006.201.09:15:39.95#ibcon#about to read 4, iclass 36, count 0 2006.201.09:15:39.95#ibcon#read 4, iclass 36, count 0 2006.201.09:15:39.95#ibcon#about to read 5, iclass 36, count 0 2006.201.09:15:39.95#ibcon#read 5, iclass 36, count 0 2006.201.09:15:39.95#ibcon#about to read 6, iclass 36, count 0 2006.201.09:15:39.95#ibcon#read 6, iclass 36, count 0 2006.201.09:15:39.95#ibcon#end of sib2, iclass 36, count 0 2006.201.09:15:39.95#ibcon#*after write, iclass 36, count 0 2006.201.09:15:39.95#ibcon#*before return 0, iclass 36, count 0 2006.201.09:15:39.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:15:39.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:15:39.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:15:39.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:15:39.95$vck44/vb=5,4 2006.201.09:15:39.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.09:15:39.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.09:15:39.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:39.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:40.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:40.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:40.01#ibcon#enter wrdev, iclass 39, count 2 2006.201.09:15:40.01#ibcon#first serial, iclass 39, count 2 2006.201.09:15:40.01#ibcon#enter sib2, iclass 39, count 2 2006.201.09:15:40.01#ibcon#flushed, iclass 39, count 2 2006.201.09:15:40.01#ibcon#about to write, iclass 39, count 2 2006.201.09:15:40.01#ibcon#wrote, iclass 39, count 2 2006.201.09:15:40.01#ibcon#about to read 3, iclass 39, count 2 2006.201.09:15:40.03#ibcon#read 3, iclass 39, count 2 2006.201.09:15:40.03#ibcon#about to read 4, iclass 39, count 2 2006.201.09:15:40.03#ibcon#read 4, iclass 39, count 2 2006.201.09:15:40.03#ibcon#about to read 5, iclass 39, count 2 2006.201.09:15:40.03#ibcon#read 5, iclass 39, count 2 2006.201.09:15:40.03#ibcon#about to read 6, iclass 39, count 2 2006.201.09:15:40.03#ibcon#read 6, iclass 39, count 2 2006.201.09:15:40.03#ibcon#end of sib2, iclass 39, count 2 2006.201.09:15:40.03#ibcon#*mode == 0, iclass 39, count 2 2006.201.09:15:40.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.09:15:40.03#ibcon#[27=AT05-04\r\n] 2006.201.09:15:40.03#ibcon#*before write, iclass 39, count 2 2006.201.09:15:40.03#ibcon#enter sib2, iclass 39, count 2 2006.201.09:15:40.03#ibcon#flushed, iclass 39, count 2 2006.201.09:15:40.03#ibcon#about to write, iclass 39, count 2 2006.201.09:15:40.03#ibcon#wrote, iclass 39, count 2 2006.201.09:15:40.03#ibcon#about to read 3, iclass 39, count 2 2006.201.09:15:40.06#ibcon#read 3, iclass 39, count 2 2006.201.09:15:40.06#ibcon#about to read 4, iclass 39, count 2 2006.201.09:15:40.06#ibcon#read 4, iclass 39, count 2 2006.201.09:15:40.06#ibcon#about to read 5, iclass 39, count 2 2006.201.09:15:40.06#ibcon#read 5, iclass 39, count 2 2006.201.09:15:40.06#ibcon#about to read 6, iclass 39, count 2 2006.201.09:15:40.06#ibcon#read 6, iclass 39, count 2 2006.201.09:15:40.06#ibcon#end of sib2, iclass 39, count 2 2006.201.09:15:40.06#ibcon#*after write, iclass 39, count 2 2006.201.09:15:40.06#ibcon#*before return 0, iclass 39, count 2 2006.201.09:15:40.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:40.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:15:40.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.09:15:40.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:40.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:40.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:40.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:40.18#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:15:40.18#ibcon#first serial, iclass 39, count 0 2006.201.09:15:40.18#ibcon#enter sib2, iclass 39, count 0 2006.201.09:15:40.18#ibcon#flushed, iclass 39, count 0 2006.201.09:15:40.18#ibcon#about to write, iclass 39, count 0 2006.201.09:15:40.18#ibcon#wrote, iclass 39, count 0 2006.201.09:15:40.18#ibcon#about to read 3, iclass 39, count 0 2006.201.09:15:40.20#ibcon#read 3, iclass 39, count 0 2006.201.09:15:40.20#ibcon#about to read 4, iclass 39, count 0 2006.201.09:15:40.20#ibcon#read 4, iclass 39, count 0 2006.201.09:15:40.20#ibcon#about to read 5, iclass 39, count 0 2006.201.09:15:40.20#ibcon#read 5, iclass 39, count 0 2006.201.09:15:40.20#ibcon#about to read 6, iclass 39, count 0 2006.201.09:15:40.20#ibcon#read 6, iclass 39, count 0 2006.201.09:15:40.20#ibcon#end of sib2, iclass 39, count 0 2006.201.09:15:40.20#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:15:40.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:15:40.20#ibcon#[27=USB\r\n] 2006.201.09:15:40.20#ibcon#*before write, iclass 39, count 0 2006.201.09:15:40.20#ibcon#enter sib2, iclass 39, count 0 2006.201.09:15:40.20#ibcon#flushed, iclass 39, count 0 2006.201.09:15:40.20#ibcon#about to write, iclass 39, count 0 2006.201.09:15:40.20#ibcon#wrote, iclass 39, count 0 2006.201.09:15:40.20#ibcon#about to read 3, iclass 39, count 0 2006.201.09:15:40.23#ibcon#read 3, iclass 39, count 0 2006.201.09:15:40.23#ibcon#about to read 4, iclass 39, count 0 2006.201.09:15:40.23#ibcon#read 4, iclass 39, count 0 2006.201.09:15:40.23#ibcon#about to read 5, iclass 39, count 0 2006.201.09:15:40.23#ibcon#read 5, iclass 39, count 0 2006.201.09:15:40.23#ibcon#about to read 6, iclass 39, count 0 2006.201.09:15:40.23#ibcon#read 6, iclass 39, count 0 2006.201.09:15:40.23#ibcon#end of sib2, iclass 39, count 0 2006.201.09:15:40.23#ibcon#*after write, iclass 39, count 0 2006.201.09:15:40.23#ibcon#*before return 0, iclass 39, count 0 2006.201.09:15:40.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:40.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:15:40.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:15:40.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:15:40.23$vck44/vblo=6,719.99 2006.201.09:15:40.23#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.09:15:40.23#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.09:15:40.23#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:40.23#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:40.23#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:40.23#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:40.23#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:15:40.23#ibcon#first serial, iclass 2, count 0 2006.201.09:15:40.23#ibcon#enter sib2, iclass 2, count 0 2006.201.09:15:40.23#ibcon#flushed, iclass 2, count 0 2006.201.09:15:40.23#ibcon#about to write, iclass 2, count 0 2006.201.09:15:40.23#ibcon#wrote, iclass 2, count 0 2006.201.09:15:40.23#ibcon#about to read 3, iclass 2, count 0 2006.201.09:15:40.25#ibcon#read 3, iclass 2, count 0 2006.201.09:15:40.25#ibcon#about to read 4, iclass 2, count 0 2006.201.09:15:40.25#ibcon#read 4, iclass 2, count 0 2006.201.09:15:40.25#ibcon#about to read 5, iclass 2, count 0 2006.201.09:15:40.25#ibcon#read 5, iclass 2, count 0 2006.201.09:15:40.25#ibcon#about to read 6, iclass 2, count 0 2006.201.09:15:40.25#ibcon#read 6, iclass 2, count 0 2006.201.09:15:40.25#ibcon#end of sib2, iclass 2, count 0 2006.201.09:15:40.25#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:15:40.25#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:15:40.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:15:40.25#ibcon#*before write, iclass 2, count 0 2006.201.09:15:40.25#ibcon#enter sib2, iclass 2, count 0 2006.201.09:15:40.25#ibcon#flushed, iclass 2, count 0 2006.201.09:15:40.25#ibcon#about to write, iclass 2, count 0 2006.201.09:15:40.25#ibcon#wrote, iclass 2, count 0 2006.201.09:15:40.25#ibcon#about to read 3, iclass 2, count 0 2006.201.09:15:40.29#ibcon#read 3, iclass 2, count 0 2006.201.09:15:40.29#ibcon#about to read 4, iclass 2, count 0 2006.201.09:15:40.29#ibcon#read 4, iclass 2, count 0 2006.201.09:15:40.29#ibcon#about to read 5, iclass 2, count 0 2006.201.09:15:40.29#ibcon#read 5, iclass 2, count 0 2006.201.09:15:40.29#ibcon#about to read 6, iclass 2, count 0 2006.201.09:15:40.29#ibcon#read 6, iclass 2, count 0 2006.201.09:15:40.29#ibcon#end of sib2, iclass 2, count 0 2006.201.09:15:40.29#ibcon#*after write, iclass 2, count 0 2006.201.09:15:40.29#ibcon#*before return 0, iclass 2, count 0 2006.201.09:15:40.29#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:40.29#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:15:40.29#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:15:40.29#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:15:40.29$vck44/vb=6,4 2006.201.09:15:40.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.09:15:40.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.09:15:40.29#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:40.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:40.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:40.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:40.35#ibcon#enter wrdev, iclass 5, count 2 2006.201.09:15:40.35#ibcon#first serial, iclass 5, count 2 2006.201.09:15:40.35#ibcon#enter sib2, iclass 5, count 2 2006.201.09:15:40.35#ibcon#flushed, iclass 5, count 2 2006.201.09:15:40.35#ibcon#about to write, iclass 5, count 2 2006.201.09:15:40.35#ibcon#wrote, iclass 5, count 2 2006.201.09:15:40.35#ibcon#about to read 3, iclass 5, count 2 2006.201.09:15:40.37#ibcon#read 3, iclass 5, count 2 2006.201.09:15:40.37#ibcon#about to read 4, iclass 5, count 2 2006.201.09:15:40.37#ibcon#read 4, iclass 5, count 2 2006.201.09:15:40.37#ibcon#about to read 5, iclass 5, count 2 2006.201.09:15:40.37#ibcon#read 5, iclass 5, count 2 2006.201.09:15:40.37#ibcon#about to read 6, iclass 5, count 2 2006.201.09:15:40.37#ibcon#read 6, iclass 5, count 2 2006.201.09:15:40.37#ibcon#end of sib2, iclass 5, count 2 2006.201.09:15:40.37#ibcon#*mode == 0, iclass 5, count 2 2006.201.09:15:40.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.09:15:40.37#ibcon#[27=AT06-04\r\n] 2006.201.09:15:40.37#ibcon#*before write, iclass 5, count 2 2006.201.09:15:40.37#ibcon#enter sib2, iclass 5, count 2 2006.201.09:15:40.37#ibcon#flushed, iclass 5, count 2 2006.201.09:15:40.37#ibcon#about to write, iclass 5, count 2 2006.201.09:15:40.37#ibcon#wrote, iclass 5, count 2 2006.201.09:15:40.37#ibcon#about to read 3, iclass 5, count 2 2006.201.09:15:40.41#ibcon#read 3, iclass 5, count 2 2006.201.09:15:40.41#ibcon#about to read 4, iclass 5, count 2 2006.201.09:15:40.41#ibcon#read 4, iclass 5, count 2 2006.201.09:15:40.41#ibcon#about to read 5, iclass 5, count 2 2006.201.09:15:40.41#ibcon#read 5, iclass 5, count 2 2006.201.09:15:40.41#ibcon#about to read 6, iclass 5, count 2 2006.201.09:15:40.41#ibcon#read 6, iclass 5, count 2 2006.201.09:15:40.41#ibcon#end of sib2, iclass 5, count 2 2006.201.09:15:40.41#ibcon#*after write, iclass 5, count 2 2006.201.09:15:40.41#ibcon#*before return 0, iclass 5, count 2 2006.201.09:15:40.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:40.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:15:40.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.09:15:40.41#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:40.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:40.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:40.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:40.53#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:15:40.53#ibcon#first serial, iclass 5, count 0 2006.201.09:15:40.53#ibcon#enter sib2, iclass 5, count 0 2006.201.09:15:40.53#ibcon#flushed, iclass 5, count 0 2006.201.09:15:40.53#ibcon#about to write, iclass 5, count 0 2006.201.09:15:40.53#ibcon#wrote, iclass 5, count 0 2006.201.09:15:40.53#ibcon#about to read 3, iclass 5, count 0 2006.201.09:15:40.55#ibcon#read 3, iclass 5, count 0 2006.201.09:15:40.55#ibcon#about to read 4, iclass 5, count 0 2006.201.09:15:40.55#ibcon#read 4, iclass 5, count 0 2006.201.09:15:40.55#ibcon#about to read 5, iclass 5, count 0 2006.201.09:15:40.55#ibcon#read 5, iclass 5, count 0 2006.201.09:15:40.55#ibcon#about to read 6, iclass 5, count 0 2006.201.09:15:40.55#ibcon#read 6, iclass 5, count 0 2006.201.09:15:40.55#ibcon#end of sib2, iclass 5, count 0 2006.201.09:15:40.55#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:15:40.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:15:40.55#ibcon#[27=USB\r\n] 2006.201.09:15:40.55#ibcon#*before write, iclass 5, count 0 2006.201.09:15:40.55#ibcon#enter sib2, iclass 5, count 0 2006.201.09:15:40.55#ibcon#flushed, iclass 5, count 0 2006.201.09:15:40.55#ibcon#about to write, iclass 5, count 0 2006.201.09:15:40.55#ibcon#wrote, iclass 5, count 0 2006.201.09:15:40.55#ibcon#about to read 3, iclass 5, count 0 2006.201.09:15:40.58#ibcon#read 3, iclass 5, count 0 2006.201.09:15:40.58#ibcon#about to read 4, iclass 5, count 0 2006.201.09:15:40.58#ibcon#read 4, iclass 5, count 0 2006.201.09:15:40.58#ibcon#about to read 5, iclass 5, count 0 2006.201.09:15:40.58#ibcon#read 5, iclass 5, count 0 2006.201.09:15:40.58#ibcon#about to read 6, iclass 5, count 0 2006.201.09:15:40.58#ibcon#read 6, iclass 5, count 0 2006.201.09:15:40.58#ibcon#end of sib2, iclass 5, count 0 2006.201.09:15:40.58#ibcon#*after write, iclass 5, count 0 2006.201.09:15:40.58#ibcon#*before return 0, iclass 5, count 0 2006.201.09:15:40.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:40.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:15:40.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:15:40.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:15:40.58$vck44/vblo=7,734.99 2006.201.09:15:40.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.09:15:40.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.09:15:40.58#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:40.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:40.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:40.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:40.58#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:15:40.58#ibcon#first serial, iclass 7, count 0 2006.201.09:15:40.58#ibcon#enter sib2, iclass 7, count 0 2006.201.09:15:40.58#ibcon#flushed, iclass 7, count 0 2006.201.09:15:40.58#ibcon#about to write, iclass 7, count 0 2006.201.09:15:40.58#ibcon#wrote, iclass 7, count 0 2006.201.09:15:40.58#ibcon#about to read 3, iclass 7, count 0 2006.201.09:15:40.60#ibcon#read 3, iclass 7, count 0 2006.201.09:15:40.60#ibcon#about to read 4, iclass 7, count 0 2006.201.09:15:40.60#ibcon#read 4, iclass 7, count 0 2006.201.09:15:40.60#ibcon#about to read 5, iclass 7, count 0 2006.201.09:15:40.60#ibcon#read 5, iclass 7, count 0 2006.201.09:15:40.60#ibcon#about to read 6, iclass 7, count 0 2006.201.09:15:40.60#ibcon#read 6, iclass 7, count 0 2006.201.09:15:40.60#ibcon#end of sib2, iclass 7, count 0 2006.201.09:15:40.60#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:15:40.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:15:40.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:15:40.60#ibcon#*before write, iclass 7, count 0 2006.201.09:15:40.60#ibcon#enter sib2, iclass 7, count 0 2006.201.09:15:40.60#ibcon#flushed, iclass 7, count 0 2006.201.09:15:40.60#ibcon#about to write, iclass 7, count 0 2006.201.09:15:40.60#ibcon#wrote, iclass 7, count 0 2006.201.09:15:40.60#ibcon#about to read 3, iclass 7, count 0 2006.201.09:15:40.64#ibcon#read 3, iclass 7, count 0 2006.201.09:15:40.64#ibcon#about to read 4, iclass 7, count 0 2006.201.09:15:40.64#ibcon#read 4, iclass 7, count 0 2006.201.09:15:40.64#ibcon#about to read 5, iclass 7, count 0 2006.201.09:15:40.64#ibcon#read 5, iclass 7, count 0 2006.201.09:15:40.64#ibcon#about to read 6, iclass 7, count 0 2006.201.09:15:40.64#ibcon#read 6, iclass 7, count 0 2006.201.09:15:40.64#ibcon#end of sib2, iclass 7, count 0 2006.201.09:15:40.64#ibcon#*after write, iclass 7, count 0 2006.201.09:15:40.64#ibcon#*before return 0, iclass 7, count 0 2006.201.09:15:40.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:40.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:15:40.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:15:40.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:15:40.64$vck44/vb=7,4 2006.201.09:15:40.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.09:15:40.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.09:15:40.64#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:40.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:40.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:40.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:40.70#ibcon#enter wrdev, iclass 11, count 2 2006.201.09:15:40.70#ibcon#first serial, iclass 11, count 2 2006.201.09:15:40.70#ibcon#enter sib2, iclass 11, count 2 2006.201.09:15:40.70#ibcon#flushed, iclass 11, count 2 2006.201.09:15:40.70#ibcon#about to write, iclass 11, count 2 2006.201.09:15:40.70#ibcon#wrote, iclass 11, count 2 2006.201.09:15:40.70#ibcon#about to read 3, iclass 11, count 2 2006.201.09:15:40.72#ibcon#read 3, iclass 11, count 2 2006.201.09:15:40.72#ibcon#about to read 4, iclass 11, count 2 2006.201.09:15:40.72#ibcon#read 4, iclass 11, count 2 2006.201.09:15:40.72#ibcon#about to read 5, iclass 11, count 2 2006.201.09:15:40.72#ibcon#read 5, iclass 11, count 2 2006.201.09:15:40.72#ibcon#about to read 6, iclass 11, count 2 2006.201.09:15:40.72#ibcon#read 6, iclass 11, count 2 2006.201.09:15:40.72#ibcon#end of sib2, iclass 11, count 2 2006.201.09:15:40.72#ibcon#*mode == 0, iclass 11, count 2 2006.201.09:15:40.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.09:15:40.72#ibcon#[27=AT07-04\r\n] 2006.201.09:15:40.72#ibcon#*before write, iclass 11, count 2 2006.201.09:15:40.72#ibcon#enter sib2, iclass 11, count 2 2006.201.09:15:40.72#ibcon#flushed, iclass 11, count 2 2006.201.09:15:40.72#ibcon#about to write, iclass 11, count 2 2006.201.09:15:40.72#ibcon#wrote, iclass 11, count 2 2006.201.09:15:40.72#ibcon#about to read 3, iclass 11, count 2 2006.201.09:15:40.75#ibcon#read 3, iclass 11, count 2 2006.201.09:15:40.75#ibcon#about to read 4, iclass 11, count 2 2006.201.09:15:40.75#ibcon#read 4, iclass 11, count 2 2006.201.09:15:40.75#ibcon#about to read 5, iclass 11, count 2 2006.201.09:15:40.75#ibcon#read 5, iclass 11, count 2 2006.201.09:15:40.75#ibcon#about to read 6, iclass 11, count 2 2006.201.09:15:40.75#ibcon#read 6, iclass 11, count 2 2006.201.09:15:40.75#ibcon#end of sib2, iclass 11, count 2 2006.201.09:15:40.75#ibcon#*after write, iclass 11, count 2 2006.201.09:15:40.75#ibcon#*before return 0, iclass 11, count 2 2006.201.09:15:40.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:40.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:15:40.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.09:15:40.75#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:40.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:40.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:40.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:40.87#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:15:40.87#ibcon#first serial, iclass 11, count 0 2006.201.09:15:40.87#ibcon#enter sib2, iclass 11, count 0 2006.201.09:15:40.87#ibcon#flushed, iclass 11, count 0 2006.201.09:15:40.87#ibcon#about to write, iclass 11, count 0 2006.201.09:15:40.87#ibcon#wrote, iclass 11, count 0 2006.201.09:15:40.87#ibcon#about to read 3, iclass 11, count 0 2006.201.09:15:40.89#ibcon#read 3, iclass 11, count 0 2006.201.09:15:40.89#ibcon#about to read 4, iclass 11, count 0 2006.201.09:15:40.89#ibcon#read 4, iclass 11, count 0 2006.201.09:15:40.89#ibcon#about to read 5, iclass 11, count 0 2006.201.09:15:40.89#ibcon#read 5, iclass 11, count 0 2006.201.09:15:40.89#ibcon#about to read 6, iclass 11, count 0 2006.201.09:15:40.89#ibcon#read 6, iclass 11, count 0 2006.201.09:15:40.89#ibcon#end of sib2, iclass 11, count 0 2006.201.09:15:40.89#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:15:40.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:15:40.89#ibcon#[27=USB\r\n] 2006.201.09:15:40.89#ibcon#*before write, iclass 11, count 0 2006.201.09:15:40.89#ibcon#enter sib2, iclass 11, count 0 2006.201.09:15:40.89#ibcon#flushed, iclass 11, count 0 2006.201.09:15:40.89#ibcon#about to write, iclass 11, count 0 2006.201.09:15:40.89#ibcon#wrote, iclass 11, count 0 2006.201.09:15:40.89#ibcon#about to read 3, iclass 11, count 0 2006.201.09:15:40.92#ibcon#read 3, iclass 11, count 0 2006.201.09:15:40.92#ibcon#about to read 4, iclass 11, count 0 2006.201.09:15:40.92#ibcon#read 4, iclass 11, count 0 2006.201.09:15:40.92#ibcon#about to read 5, iclass 11, count 0 2006.201.09:15:40.92#ibcon#read 5, iclass 11, count 0 2006.201.09:15:40.92#ibcon#about to read 6, iclass 11, count 0 2006.201.09:15:40.92#ibcon#read 6, iclass 11, count 0 2006.201.09:15:40.92#ibcon#end of sib2, iclass 11, count 0 2006.201.09:15:40.92#ibcon#*after write, iclass 11, count 0 2006.201.09:15:40.92#ibcon#*before return 0, iclass 11, count 0 2006.201.09:15:40.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:40.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:15:40.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:15:40.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:15:40.92$vck44/vblo=8,744.99 2006.201.09:15:40.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.09:15:40.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.09:15:40.92#ibcon#ireg 17 cls_cnt 0 2006.201.09:15:40.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:40.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:40.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:40.92#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:15:40.92#ibcon#first serial, iclass 13, count 0 2006.201.09:15:40.92#ibcon#enter sib2, iclass 13, count 0 2006.201.09:15:40.92#ibcon#flushed, iclass 13, count 0 2006.201.09:15:40.92#ibcon#about to write, iclass 13, count 0 2006.201.09:15:40.92#ibcon#wrote, iclass 13, count 0 2006.201.09:15:40.92#ibcon#about to read 3, iclass 13, count 0 2006.201.09:15:40.94#ibcon#read 3, iclass 13, count 0 2006.201.09:15:40.94#ibcon#about to read 4, iclass 13, count 0 2006.201.09:15:40.94#ibcon#read 4, iclass 13, count 0 2006.201.09:15:40.94#ibcon#about to read 5, iclass 13, count 0 2006.201.09:15:40.94#ibcon#read 5, iclass 13, count 0 2006.201.09:15:40.94#ibcon#about to read 6, iclass 13, count 0 2006.201.09:15:40.94#ibcon#read 6, iclass 13, count 0 2006.201.09:15:40.94#ibcon#end of sib2, iclass 13, count 0 2006.201.09:15:40.94#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:15:40.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:15:40.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:15:40.94#ibcon#*before write, iclass 13, count 0 2006.201.09:15:40.94#ibcon#enter sib2, iclass 13, count 0 2006.201.09:15:40.94#ibcon#flushed, iclass 13, count 0 2006.201.09:15:40.94#ibcon#about to write, iclass 13, count 0 2006.201.09:15:40.94#ibcon#wrote, iclass 13, count 0 2006.201.09:15:40.94#ibcon#about to read 3, iclass 13, count 0 2006.201.09:15:40.98#ibcon#read 3, iclass 13, count 0 2006.201.09:15:40.98#ibcon#about to read 4, iclass 13, count 0 2006.201.09:15:40.98#ibcon#read 4, iclass 13, count 0 2006.201.09:15:40.98#ibcon#about to read 5, iclass 13, count 0 2006.201.09:15:40.98#ibcon#read 5, iclass 13, count 0 2006.201.09:15:40.98#ibcon#about to read 6, iclass 13, count 0 2006.201.09:15:40.98#ibcon#read 6, iclass 13, count 0 2006.201.09:15:40.98#ibcon#end of sib2, iclass 13, count 0 2006.201.09:15:40.98#ibcon#*after write, iclass 13, count 0 2006.201.09:15:40.98#ibcon#*before return 0, iclass 13, count 0 2006.201.09:15:40.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:40.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:15:40.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:15:40.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:15:40.98$vck44/vb=8,4 2006.201.09:15:40.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.09:15:40.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.09:15:40.98#ibcon#ireg 11 cls_cnt 2 2006.201.09:15:40.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:41.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:41.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:41.04#ibcon#enter wrdev, iclass 15, count 2 2006.201.09:15:41.04#ibcon#first serial, iclass 15, count 2 2006.201.09:15:41.04#ibcon#enter sib2, iclass 15, count 2 2006.201.09:15:41.04#ibcon#flushed, iclass 15, count 2 2006.201.09:15:41.04#ibcon#about to write, iclass 15, count 2 2006.201.09:15:41.04#ibcon#wrote, iclass 15, count 2 2006.201.09:15:41.04#ibcon#about to read 3, iclass 15, count 2 2006.201.09:15:41.06#ibcon#read 3, iclass 15, count 2 2006.201.09:15:41.06#ibcon#about to read 4, iclass 15, count 2 2006.201.09:15:41.06#ibcon#read 4, iclass 15, count 2 2006.201.09:15:41.06#ibcon#about to read 5, iclass 15, count 2 2006.201.09:15:41.06#ibcon#read 5, iclass 15, count 2 2006.201.09:15:41.06#ibcon#about to read 6, iclass 15, count 2 2006.201.09:15:41.06#ibcon#read 6, iclass 15, count 2 2006.201.09:15:41.06#ibcon#end of sib2, iclass 15, count 2 2006.201.09:15:41.06#ibcon#*mode == 0, iclass 15, count 2 2006.201.09:15:41.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.09:15:41.06#ibcon#[27=AT08-04\r\n] 2006.201.09:15:41.06#ibcon#*before write, iclass 15, count 2 2006.201.09:15:41.06#ibcon#enter sib2, iclass 15, count 2 2006.201.09:15:41.06#ibcon#flushed, iclass 15, count 2 2006.201.09:15:41.06#ibcon#about to write, iclass 15, count 2 2006.201.09:15:41.06#ibcon#wrote, iclass 15, count 2 2006.201.09:15:41.06#ibcon#about to read 3, iclass 15, count 2 2006.201.09:15:41.09#ibcon#read 3, iclass 15, count 2 2006.201.09:15:41.09#ibcon#about to read 4, iclass 15, count 2 2006.201.09:15:41.09#ibcon#read 4, iclass 15, count 2 2006.201.09:15:41.09#ibcon#about to read 5, iclass 15, count 2 2006.201.09:15:41.09#ibcon#read 5, iclass 15, count 2 2006.201.09:15:41.09#ibcon#about to read 6, iclass 15, count 2 2006.201.09:15:41.09#ibcon#read 6, iclass 15, count 2 2006.201.09:15:41.09#ibcon#end of sib2, iclass 15, count 2 2006.201.09:15:41.09#ibcon#*after write, iclass 15, count 2 2006.201.09:15:41.09#ibcon#*before return 0, iclass 15, count 2 2006.201.09:15:41.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:41.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:15:41.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.09:15:41.09#ibcon#ireg 7 cls_cnt 0 2006.201.09:15:41.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:41.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:41.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:41.21#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:15:41.21#ibcon#first serial, iclass 15, count 0 2006.201.09:15:41.21#ibcon#enter sib2, iclass 15, count 0 2006.201.09:15:41.21#ibcon#flushed, iclass 15, count 0 2006.201.09:15:41.21#ibcon#about to write, iclass 15, count 0 2006.201.09:15:41.21#ibcon#wrote, iclass 15, count 0 2006.201.09:15:41.21#ibcon#about to read 3, iclass 15, count 0 2006.201.09:15:41.23#ibcon#read 3, iclass 15, count 0 2006.201.09:15:41.23#ibcon#about to read 4, iclass 15, count 0 2006.201.09:15:41.23#ibcon#read 4, iclass 15, count 0 2006.201.09:15:41.23#ibcon#about to read 5, iclass 15, count 0 2006.201.09:15:41.23#ibcon#read 5, iclass 15, count 0 2006.201.09:15:41.23#ibcon#about to read 6, iclass 15, count 0 2006.201.09:15:41.23#ibcon#read 6, iclass 15, count 0 2006.201.09:15:41.23#ibcon#end of sib2, iclass 15, count 0 2006.201.09:15:41.23#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:15:41.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:15:41.23#ibcon#[27=USB\r\n] 2006.201.09:15:41.23#ibcon#*before write, iclass 15, count 0 2006.201.09:15:41.23#ibcon#enter sib2, iclass 15, count 0 2006.201.09:15:41.23#ibcon#flushed, iclass 15, count 0 2006.201.09:15:41.23#ibcon#about to write, iclass 15, count 0 2006.201.09:15:41.23#ibcon#wrote, iclass 15, count 0 2006.201.09:15:41.23#ibcon#about to read 3, iclass 15, count 0 2006.201.09:15:41.26#ibcon#read 3, iclass 15, count 0 2006.201.09:15:41.26#ibcon#about to read 4, iclass 15, count 0 2006.201.09:15:41.26#ibcon#read 4, iclass 15, count 0 2006.201.09:15:41.26#ibcon#about to read 5, iclass 15, count 0 2006.201.09:15:41.26#ibcon#read 5, iclass 15, count 0 2006.201.09:15:41.26#ibcon#about to read 6, iclass 15, count 0 2006.201.09:15:41.26#ibcon#read 6, iclass 15, count 0 2006.201.09:15:41.26#ibcon#end of sib2, iclass 15, count 0 2006.201.09:15:41.26#ibcon#*after write, iclass 15, count 0 2006.201.09:15:41.26#ibcon#*before return 0, iclass 15, count 0 2006.201.09:15:41.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:41.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:15:41.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:15:41.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:15:41.26$vck44/vabw=wide 2006.201.09:15:41.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.09:15:41.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.09:15:41.26#ibcon#ireg 8 cls_cnt 0 2006.201.09:15:41.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:41.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:41.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:41.26#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:15:41.26#ibcon#first serial, iclass 17, count 0 2006.201.09:15:41.26#ibcon#enter sib2, iclass 17, count 0 2006.201.09:15:41.26#ibcon#flushed, iclass 17, count 0 2006.201.09:15:41.26#ibcon#about to write, iclass 17, count 0 2006.201.09:15:41.26#ibcon#wrote, iclass 17, count 0 2006.201.09:15:41.26#ibcon#about to read 3, iclass 17, count 0 2006.201.09:15:41.28#ibcon#read 3, iclass 17, count 0 2006.201.09:15:41.28#ibcon#about to read 4, iclass 17, count 0 2006.201.09:15:41.28#ibcon#read 4, iclass 17, count 0 2006.201.09:15:41.28#ibcon#about to read 5, iclass 17, count 0 2006.201.09:15:41.28#ibcon#read 5, iclass 17, count 0 2006.201.09:15:41.28#ibcon#about to read 6, iclass 17, count 0 2006.201.09:15:41.28#ibcon#read 6, iclass 17, count 0 2006.201.09:15:41.28#ibcon#end of sib2, iclass 17, count 0 2006.201.09:15:41.28#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:15:41.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:15:41.28#ibcon#[25=BW32\r\n] 2006.201.09:15:41.28#ibcon#*before write, iclass 17, count 0 2006.201.09:15:41.28#ibcon#enter sib2, iclass 17, count 0 2006.201.09:15:41.28#ibcon#flushed, iclass 17, count 0 2006.201.09:15:41.28#ibcon#about to write, iclass 17, count 0 2006.201.09:15:41.28#ibcon#wrote, iclass 17, count 0 2006.201.09:15:41.28#ibcon#about to read 3, iclass 17, count 0 2006.201.09:15:41.32#ibcon#read 3, iclass 17, count 0 2006.201.09:15:41.32#ibcon#about to read 4, iclass 17, count 0 2006.201.09:15:41.32#ibcon#read 4, iclass 17, count 0 2006.201.09:15:41.32#ibcon#about to read 5, iclass 17, count 0 2006.201.09:15:41.32#ibcon#read 5, iclass 17, count 0 2006.201.09:15:41.32#ibcon#about to read 6, iclass 17, count 0 2006.201.09:15:41.32#ibcon#read 6, iclass 17, count 0 2006.201.09:15:41.32#ibcon#end of sib2, iclass 17, count 0 2006.201.09:15:41.32#ibcon#*after write, iclass 17, count 0 2006.201.09:15:41.32#ibcon#*before return 0, iclass 17, count 0 2006.201.09:15:41.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:41.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:15:41.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:15:41.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:15:41.32$vck44/vbbw=wide 2006.201.09:15:41.32#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.09:15:41.32#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.09:15:41.32#ibcon#ireg 8 cls_cnt 0 2006.201.09:15:41.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:15:41.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:15:41.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:15:41.38#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:15:41.38#ibcon#first serial, iclass 19, count 0 2006.201.09:15:41.38#ibcon#enter sib2, iclass 19, count 0 2006.201.09:15:41.38#ibcon#flushed, iclass 19, count 0 2006.201.09:15:41.38#ibcon#about to write, iclass 19, count 0 2006.201.09:15:41.38#ibcon#wrote, iclass 19, count 0 2006.201.09:15:41.38#ibcon#about to read 3, iclass 19, count 0 2006.201.09:15:41.40#ibcon#read 3, iclass 19, count 0 2006.201.09:15:41.40#ibcon#about to read 4, iclass 19, count 0 2006.201.09:15:41.40#ibcon#read 4, iclass 19, count 0 2006.201.09:15:41.40#ibcon#about to read 5, iclass 19, count 0 2006.201.09:15:41.40#ibcon#read 5, iclass 19, count 0 2006.201.09:15:41.40#ibcon#about to read 6, iclass 19, count 0 2006.201.09:15:41.40#ibcon#read 6, iclass 19, count 0 2006.201.09:15:41.40#ibcon#end of sib2, iclass 19, count 0 2006.201.09:15:41.40#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:15:41.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:15:41.40#ibcon#[27=BW32\r\n] 2006.201.09:15:41.40#ibcon#*before write, iclass 19, count 0 2006.201.09:15:41.40#ibcon#enter sib2, iclass 19, count 0 2006.201.09:15:41.40#ibcon#flushed, iclass 19, count 0 2006.201.09:15:41.40#ibcon#about to write, iclass 19, count 0 2006.201.09:15:41.40#ibcon#wrote, iclass 19, count 0 2006.201.09:15:41.40#ibcon#about to read 3, iclass 19, count 0 2006.201.09:15:41.43#ibcon#read 3, iclass 19, count 0 2006.201.09:15:41.43#ibcon#about to read 4, iclass 19, count 0 2006.201.09:15:41.43#ibcon#read 4, iclass 19, count 0 2006.201.09:15:41.43#ibcon#about to read 5, iclass 19, count 0 2006.201.09:15:41.43#ibcon#read 5, iclass 19, count 0 2006.201.09:15:41.43#ibcon#about to read 6, iclass 19, count 0 2006.201.09:15:41.43#ibcon#read 6, iclass 19, count 0 2006.201.09:15:41.43#ibcon#end of sib2, iclass 19, count 0 2006.201.09:15:41.43#ibcon#*after write, iclass 19, count 0 2006.201.09:15:41.43#ibcon#*before return 0, iclass 19, count 0 2006.201.09:15:41.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:15:41.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:15:41.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:15:41.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:15:41.43$setupk4/ifdk4 2006.201.09:15:41.43$ifdk4/lo= 2006.201.09:15:41.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:15:41.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:15:41.43$ifdk4/patch= 2006.201.09:15:41.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:15:41.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:15:41.43$setupk4/!*+20s 2006.201.09:15:50.01#abcon#<5=/05 2.4 4.8 22.80 901003.8\r\n> 2006.201.09:15:50.03#abcon#{5=INTERFACE CLEAR} 2006.201.09:15:50.09#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:15:55.91$setupk4/"tpicd 2006.201.09:15:55.91$setupk4/echo=off 2006.201.09:15:55.91$setupk4/xlog=off 2006.201.09:15:55.91:!2006.201.09:17:31 2006.201.09:16:18.13#trakl#Source acquired 2006.201.09:16:19.13#flagr#flagr/antenna,acquired 2006.201.09:17:31.00:preob 2006.201.09:17:32.13/onsource/TRACKING 2006.201.09:17:32.13:!2006.201.09:17:41 2006.201.09:17:41.00:"tape 2006.201.09:17:41.00:"st=record 2006.201.09:17:41.00:data_valid=on 2006.201.09:17:41.00:midob 2006.201.09:17:41.13/onsource/TRACKING 2006.201.09:17:41.13/wx/22.78,1003.8,90 2006.201.09:17:41.23/cable/+6.4650E-03 2006.201.09:17:42.32/va/01,08,usb,yes,28,31 2006.201.09:17:42.32/va/02,07,usb,yes,31,31 2006.201.09:17:42.32/va/03,08,usb,yes,28,29 2006.201.09:17:42.32/va/04,07,usb,yes,31,33 2006.201.09:17:42.32/va/05,04,usb,yes,28,28 2006.201.09:17:42.32/va/06,05,usb,yes,28,28 2006.201.09:17:42.32/va/07,05,usb,yes,27,28 2006.201.09:17:42.32/va/08,04,usb,yes,27,32 2006.201.09:17:42.55/valo/01,524.99,yes,locked 2006.201.09:17:42.55/valo/02,534.99,yes,locked 2006.201.09:17:42.55/valo/03,564.99,yes,locked 2006.201.09:17:42.55/valo/04,624.99,yes,locked 2006.201.09:17:42.55/valo/05,734.99,yes,locked 2006.201.09:17:42.55/valo/06,814.99,yes,locked 2006.201.09:17:42.55/valo/07,864.99,yes,locked 2006.201.09:17:42.55/valo/08,884.99,yes,locked 2006.201.09:17:43.64/vb/01,04,usb,yes,28,26 2006.201.09:17:43.64/vb/02,05,usb,yes,27,27 2006.201.09:17:43.64/vb/03,04,usb,yes,28,31 2006.201.09:17:43.64/vb/04,05,usb,yes,28,27 2006.201.09:17:43.64/vb/05,04,usb,yes,25,27 2006.201.09:17:43.64/vb/06,04,usb,yes,29,25 2006.201.09:17:43.64/vb/07,04,usb,yes,29,29 2006.201.09:17:43.64/vb/08,04,usb,yes,26,30 2006.201.09:17:43.88/vblo/01,629.99,yes,locked 2006.201.09:17:43.88/vblo/02,634.99,yes,locked 2006.201.09:17:43.88/vblo/03,649.99,yes,locked 2006.201.09:17:43.88/vblo/04,679.99,yes,locked 2006.201.09:17:43.88/vblo/05,709.99,yes,locked 2006.201.09:17:43.88/vblo/06,719.99,yes,locked 2006.201.09:17:43.88/vblo/07,734.99,yes,locked 2006.201.09:17:43.88/vblo/08,744.99,yes,locked 2006.201.09:17:44.03/vabw/8 2006.201.09:17:44.18/vbbw/8 2006.201.09:17:44.27/xfe/off,on,15.0 2006.201.09:17:44.67/ifatt/23,28,28,28 2006.201.09:17:45.05/fmout-gps/S +4.53E-07 2006.201.09:17:45.12:!2006.201.09:19:21 2006.201.09:19:21.00:data_valid=off 2006.201.09:19:21.00:"et 2006.201.09:19:21.00:!+3s 2006.201.09:19:24.02:"tape 2006.201.09:19:24.02:postob 2006.201.09:19:24.11/cable/+6.4647E-03 2006.201.09:19:24.11/wx/22.75,1003.8,90 2006.201.09:19:24.19/fmout-gps/S +4.53E-07 2006.201.09:19:24.19:scan_name=201-0921,jd0607,90 2006.201.09:19:24.20:source=3c274,123049.42,122328.0,2000.0,cw 2006.201.09:19:26.14#flagr#flagr/antenna,new-source 2006.201.09:19:26.14:checkk5 2006.201.09:19:26.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:19:26.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:19:27.24/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:19:27.61/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:19:27.98/chk_obsdata//k5ts1/T2010917??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.09:19:28.35/chk_obsdata//k5ts2/T2010917??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.09:19:28.71/chk_obsdata//k5ts3/T2010917??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.09:19:29.08/chk_obsdata//k5ts4/T2010917??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.09:19:29.77/k5log//k5ts1_log_newline 2006.201.09:19:30.45/k5log//k5ts2_log_newline 2006.201.09:19:31.17/k5log//k5ts3_log_newline 2006.201.09:19:31.86/k5log//k5ts4_log_newline 2006.201.09:19:31.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:19:31.88:setupk4=1 2006.201.09:19:31.88$setupk4/echo=on 2006.201.09:19:31.88$setupk4/pcalon 2006.201.09:19:31.88$pcalon/"no phase cal control is implemented here 2006.201.09:19:31.88$setupk4/"tpicd=stop 2006.201.09:19:31.88$setupk4/"rec=synch_on 2006.201.09:19:31.88$setupk4/"rec_mode=128 2006.201.09:19:31.88$setupk4/!* 2006.201.09:19:31.88$setupk4/recpk4 2006.201.09:19:31.88$recpk4/recpatch= 2006.201.09:19:31.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:19:31.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:19:31.89$setupk4/vck44 2006.201.09:19:31.89$vck44/valo=1,524.99 2006.201.09:19:31.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.09:19:31.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.09:19:31.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:31.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:31.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:31.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:31.89#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:19:31.89#ibcon#first serial, iclass 40, count 0 2006.201.09:19:31.89#ibcon#enter sib2, iclass 40, count 0 2006.201.09:19:31.89#ibcon#flushed, iclass 40, count 0 2006.201.09:19:31.89#ibcon#about to write, iclass 40, count 0 2006.201.09:19:31.89#ibcon#wrote, iclass 40, count 0 2006.201.09:19:31.89#ibcon#about to read 3, iclass 40, count 0 2006.201.09:19:31.92#ibcon#read 3, iclass 40, count 0 2006.201.09:19:31.92#ibcon#about to read 4, iclass 40, count 0 2006.201.09:19:31.92#ibcon#read 4, iclass 40, count 0 2006.201.09:19:31.92#ibcon#about to read 5, iclass 40, count 0 2006.201.09:19:31.92#ibcon#read 5, iclass 40, count 0 2006.201.09:19:31.92#ibcon#about to read 6, iclass 40, count 0 2006.201.09:19:31.92#ibcon#read 6, iclass 40, count 0 2006.201.09:19:31.92#ibcon#end of sib2, iclass 40, count 0 2006.201.09:19:31.92#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:19:31.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:19:31.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:19:31.92#ibcon#*before write, iclass 40, count 0 2006.201.09:19:31.92#ibcon#enter sib2, iclass 40, count 0 2006.201.09:19:31.92#ibcon#flushed, iclass 40, count 0 2006.201.09:19:31.92#ibcon#about to write, iclass 40, count 0 2006.201.09:19:31.92#ibcon#wrote, iclass 40, count 0 2006.201.09:19:31.92#ibcon#about to read 3, iclass 40, count 0 2006.201.09:19:31.97#ibcon#read 3, iclass 40, count 0 2006.201.09:19:31.97#ibcon#about to read 4, iclass 40, count 0 2006.201.09:19:31.97#ibcon#read 4, iclass 40, count 0 2006.201.09:19:31.97#ibcon#about to read 5, iclass 40, count 0 2006.201.09:19:31.97#ibcon#read 5, iclass 40, count 0 2006.201.09:19:31.97#ibcon#about to read 6, iclass 40, count 0 2006.201.09:19:31.97#ibcon#read 6, iclass 40, count 0 2006.201.09:19:31.97#ibcon#end of sib2, iclass 40, count 0 2006.201.09:19:31.97#ibcon#*after write, iclass 40, count 0 2006.201.09:19:31.97#ibcon#*before return 0, iclass 40, count 0 2006.201.09:19:31.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:31.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:31.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:19:31.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:19:31.97$vck44/va=1,8 2006.201.09:19:31.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.09:19:31.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.09:19:31.97#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:31.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:31.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:31.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:31.97#ibcon#enter wrdev, iclass 4, count 2 2006.201.09:19:31.97#ibcon#first serial, iclass 4, count 2 2006.201.09:19:31.97#ibcon#enter sib2, iclass 4, count 2 2006.201.09:19:31.97#ibcon#flushed, iclass 4, count 2 2006.201.09:19:31.97#ibcon#about to write, iclass 4, count 2 2006.201.09:19:31.97#ibcon#wrote, iclass 4, count 2 2006.201.09:19:31.97#ibcon#about to read 3, iclass 4, count 2 2006.201.09:19:31.99#ibcon#read 3, iclass 4, count 2 2006.201.09:19:31.99#ibcon#about to read 4, iclass 4, count 2 2006.201.09:19:31.99#ibcon#read 4, iclass 4, count 2 2006.201.09:19:31.99#ibcon#about to read 5, iclass 4, count 2 2006.201.09:19:31.99#ibcon#read 5, iclass 4, count 2 2006.201.09:19:31.99#ibcon#about to read 6, iclass 4, count 2 2006.201.09:19:31.99#ibcon#read 6, iclass 4, count 2 2006.201.09:19:31.99#ibcon#end of sib2, iclass 4, count 2 2006.201.09:19:31.99#ibcon#*mode == 0, iclass 4, count 2 2006.201.09:19:31.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.09:19:31.99#ibcon#[25=AT01-08\r\n] 2006.201.09:19:31.99#ibcon#*before write, iclass 4, count 2 2006.201.09:19:31.99#ibcon#enter sib2, iclass 4, count 2 2006.201.09:19:31.99#ibcon#flushed, iclass 4, count 2 2006.201.09:19:31.99#ibcon#about to write, iclass 4, count 2 2006.201.09:19:31.99#ibcon#wrote, iclass 4, count 2 2006.201.09:19:31.99#ibcon#about to read 3, iclass 4, count 2 2006.201.09:19:32.02#ibcon#read 3, iclass 4, count 2 2006.201.09:19:32.02#ibcon#about to read 4, iclass 4, count 2 2006.201.09:19:32.02#ibcon#read 4, iclass 4, count 2 2006.201.09:19:32.02#ibcon#about to read 5, iclass 4, count 2 2006.201.09:19:32.02#ibcon#read 5, iclass 4, count 2 2006.201.09:19:32.02#ibcon#about to read 6, iclass 4, count 2 2006.201.09:19:32.02#ibcon#read 6, iclass 4, count 2 2006.201.09:19:32.02#ibcon#end of sib2, iclass 4, count 2 2006.201.09:19:32.02#ibcon#*after write, iclass 4, count 2 2006.201.09:19:32.02#ibcon#*before return 0, iclass 4, count 2 2006.201.09:19:32.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:32.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:32.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.09:19:32.02#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:32.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:32.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:32.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:32.14#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:19:32.14#ibcon#first serial, iclass 4, count 0 2006.201.09:19:32.14#ibcon#enter sib2, iclass 4, count 0 2006.201.09:19:32.14#ibcon#flushed, iclass 4, count 0 2006.201.09:19:32.14#ibcon#about to write, iclass 4, count 0 2006.201.09:19:32.14#ibcon#wrote, iclass 4, count 0 2006.201.09:19:32.14#ibcon#about to read 3, iclass 4, count 0 2006.201.09:19:32.16#ibcon#read 3, iclass 4, count 0 2006.201.09:19:32.16#ibcon#about to read 4, iclass 4, count 0 2006.201.09:19:32.16#ibcon#read 4, iclass 4, count 0 2006.201.09:19:32.16#ibcon#about to read 5, iclass 4, count 0 2006.201.09:19:32.16#ibcon#read 5, iclass 4, count 0 2006.201.09:19:32.16#ibcon#about to read 6, iclass 4, count 0 2006.201.09:19:32.16#ibcon#read 6, iclass 4, count 0 2006.201.09:19:32.16#ibcon#end of sib2, iclass 4, count 0 2006.201.09:19:32.16#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:19:32.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:19:32.16#ibcon#[25=USB\r\n] 2006.201.09:19:32.16#ibcon#*before write, iclass 4, count 0 2006.201.09:19:32.16#ibcon#enter sib2, iclass 4, count 0 2006.201.09:19:32.16#ibcon#flushed, iclass 4, count 0 2006.201.09:19:32.16#ibcon#about to write, iclass 4, count 0 2006.201.09:19:32.16#ibcon#wrote, iclass 4, count 0 2006.201.09:19:32.16#ibcon#about to read 3, iclass 4, count 0 2006.201.09:19:32.19#ibcon#read 3, iclass 4, count 0 2006.201.09:19:32.19#ibcon#about to read 4, iclass 4, count 0 2006.201.09:19:32.19#ibcon#read 4, iclass 4, count 0 2006.201.09:19:32.19#ibcon#about to read 5, iclass 4, count 0 2006.201.09:19:32.19#ibcon#read 5, iclass 4, count 0 2006.201.09:19:32.19#ibcon#about to read 6, iclass 4, count 0 2006.201.09:19:32.19#ibcon#read 6, iclass 4, count 0 2006.201.09:19:32.19#ibcon#end of sib2, iclass 4, count 0 2006.201.09:19:32.19#ibcon#*after write, iclass 4, count 0 2006.201.09:19:32.19#ibcon#*before return 0, iclass 4, count 0 2006.201.09:19:32.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:32.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:32.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:19:32.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:19:32.19$vck44/valo=2,534.99 2006.201.09:19:32.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.09:19:32.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.09:19:32.19#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:32.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:32.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:32.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:32.19#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:19:32.19#ibcon#first serial, iclass 6, count 0 2006.201.09:19:32.19#ibcon#enter sib2, iclass 6, count 0 2006.201.09:19:32.19#ibcon#flushed, iclass 6, count 0 2006.201.09:19:32.19#ibcon#about to write, iclass 6, count 0 2006.201.09:19:32.19#ibcon#wrote, iclass 6, count 0 2006.201.09:19:32.19#ibcon#about to read 3, iclass 6, count 0 2006.201.09:19:32.21#ibcon#read 3, iclass 6, count 0 2006.201.09:19:32.21#ibcon#about to read 4, iclass 6, count 0 2006.201.09:19:32.21#ibcon#read 4, iclass 6, count 0 2006.201.09:19:32.21#ibcon#about to read 5, iclass 6, count 0 2006.201.09:19:32.21#ibcon#read 5, iclass 6, count 0 2006.201.09:19:32.21#ibcon#about to read 6, iclass 6, count 0 2006.201.09:19:32.21#ibcon#read 6, iclass 6, count 0 2006.201.09:19:32.21#ibcon#end of sib2, iclass 6, count 0 2006.201.09:19:32.21#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:19:32.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:19:32.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:19:32.21#ibcon#*before write, iclass 6, count 0 2006.201.09:19:32.21#ibcon#enter sib2, iclass 6, count 0 2006.201.09:19:32.21#ibcon#flushed, iclass 6, count 0 2006.201.09:19:32.21#ibcon#about to write, iclass 6, count 0 2006.201.09:19:32.21#ibcon#wrote, iclass 6, count 0 2006.201.09:19:32.21#ibcon#about to read 3, iclass 6, count 0 2006.201.09:19:32.26#ibcon#read 3, iclass 6, count 0 2006.201.09:19:32.26#ibcon#about to read 4, iclass 6, count 0 2006.201.09:19:32.26#ibcon#read 4, iclass 6, count 0 2006.201.09:19:32.26#ibcon#about to read 5, iclass 6, count 0 2006.201.09:19:32.26#ibcon#read 5, iclass 6, count 0 2006.201.09:19:32.26#ibcon#about to read 6, iclass 6, count 0 2006.201.09:19:32.26#ibcon#read 6, iclass 6, count 0 2006.201.09:19:32.26#ibcon#end of sib2, iclass 6, count 0 2006.201.09:19:32.26#ibcon#*after write, iclass 6, count 0 2006.201.09:19:32.26#ibcon#*before return 0, iclass 6, count 0 2006.201.09:19:32.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:32.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:32.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:19:32.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:19:32.26$vck44/va=2,7 2006.201.09:19:32.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.09:19:32.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.09:19:32.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:32.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:32.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:32.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:32.31#ibcon#enter wrdev, iclass 10, count 2 2006.201.09:19:32.31#ibcon#first serial, iclass 10, count 2 2006.201.09:19:32.31#ibcon#enter sib2, iclass 10, count 2 2006.201.09:19:32.31#ibcon#flushed, iclass 10, count 2 2006.201.09:19:32.31#ibcon#about to write, iclass 10, count 2 2006.201.09:19:32.31#ibcon#wrote, iclass 10, count 2 2006.201.09:19:32.31#ibcon#about to read 3, iclass 10, count 2 2006.201.09:19:32.33#ibcon#read 3, iclass 10, count 2 2006.201.09:19:32.33#ibcon#about to read 4, iclass 10, count 2 2006.201.09:19:32.33#ibcon#read 4, iclass 10, count 2 2006.201.09:19:32.33#ibcon#about to read 5, iclass 10, count 2 2006.201.09:19:32.33#ibcon#read 5, iclass 10, count 2 2006.201.09:19:32.33#ibcon#about to read 6, iclass 10, count 2 2006.201.09:19:32.33#ibcon#read 6, iclass 10, count 2 2006.201.09:19:32.33#ibcon#end of sib2, iclass 10, count 2 2006.201.09:19:32.33#ibcon#*mode == 0, iclass 10, count 2 2006.201.09:19:32.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.09:19:32.33#ibcon#[25=AT02-07\r\n] 2006.201.09:19:32.33#ibcon#*before write, iclass 10, count 2 2006.201.09:19:32.33#ibcon#enter sib2, iclass 10, count 2 2006.201.09:19:32.33#ibcon#flushed, iclass 10, count 2 2006.201.09:19:32.33#ibcon#about to write, iclass 10, count 2 2006.201.09:19:32.33#ibcon#wrote, iclass 10, count 2 2006.201.09:19:32.33#ibcon#about to read 3, iclass 10, count 2 2006.201.09:19:32.36#ibcon#read 3, iclass 10, count 2 2006.201.09:19:32.36#ibcon#about to read 4, iclass 10, count 2 2006.201.09:19:32.36#ibcon#read 4, iclass 10, count 2 2006.201.09:19:32.36#ibcon#about to read 5, iclass 10, count 2 2006.201.09:19:32.36#ibcon#read 5, iclass 10, count 2 2006.201.09:19:32.36#ibcon#about to read 6, iclass 10, count 2 2006.201.09:19:32.36#ibcon#read 6, iclass 10, count 2 2006.201.09:19:32.36#ibcon#end of sib2, iclass 10, count 2 2006.201.09:19:32.36#ibcon#*after write, iclass 10, count 2 2006.201.09:19:32.36#ibcon#*before return 0, iclass 10, count 2 2006.201.09:19:32.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:32.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:32.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.09:19:32.36#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:32.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:32.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:32.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:32.48#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:19:32.48#ibcon#first serial, iclass 10, count 0 2006.201.09:19:32.48#ibcon#enter sib2, iclass 10, count 0 2006.201.09:19:32.48#ibcon#flushed, iclass 10, count 0 2006.201.09:19:32.48#ibcon#about to write, iclass 10, count 0 2006.201.09:19:32.48#ibcon#wrote, iclass 10, count 0 2006.201.09:19:32.48#ibcon#about to read 3, iclass 10, count 0 2006.201.09:19:32.50#ibcon#read 3, iclass 10, count 0 2006.201.09:19:32.50#ibcon#about to read 4, iclass 10, count 0 2006.201.09:19:32.50#ibcon#read 4, iclass 10, count 0 2006.201.09:19:32.50#ibcon#about to read 5, iclass 10, count 0 2006.201.09:19:32.50#ibcon#read 5, iclass 10, count 0 2006.201.09:19:32.50#ibcon#about to read 6, iclass 10, count 0 2006.201.09:19:32.50#ibcon#read 6, iclass 10, count 0 2006.201.09:19:32.50#ibcon#end of sib2, iclass 10, count 0 2006.201.09:19:32.50#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:19:32.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:19:32.50#ibcon#[25=USB\r\n] 2006.201.09:19:32.50#ibcon#*before write, iclass 10, count 0 2006.201.09:19:32.50#ibcon#enter sib2, iclass 10, count 0 2006.201.09:19:32.50#ibcon#flushed, iclass 10, count 0 2006.201.09:19:32.50#ibcon#about to write, iclass 10, count 0 2006.201.09:19:32.50#ibcon#wrote, iclass 10, count 0 2006.201.09:19:32.50#ibcon#about to read 3, iclass 10, count 0 2006.201.09:19:32.53#ibcon#read 3, iclass 10, count 0 2006.201.09:19:32.53#ibcon#about to read 4, iclass 10, count 0 2006.201.09:19:32.53#ibcon#read 4, iclass 10, count 0 2006.201.09:19:32.53#ibcon#about to read 5, iclass 10, count 0 2006.201.09:19:32.53#ibcon#read 5, iclass 10, count 0 2006.201.09:19:32.53#ibcon#about to read 6, iclass 10, count 0 2006.201.09:19:32.53#ibcon#read 6, iclass 10, count 0 2006.201.09:19:32.53#ibcon#end of sib2, iclass 10, count 0 2006.201.09:19:32.53#ibcon#*after write, iclass 10, count 0 2006.201.09:19:32.53#ibcon#*before return 0, iclass 10, count 0 2006.201.09:19:32.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:32.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:32.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:19:32.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:19:32.53$vck44/valo=3,564.99 2006.201.09:19:32.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.09:19:32.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.09:19:32.53#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:32.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:32.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:32.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:32.53#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:19:32.53#ibcon#first serial, iclass 12, count 0 2006.201.09:19:32.53#ibcon#enter sib2, iclass 12, count 0 2006.201.09:19:32.53#ibcon#flushed, iclass 12, count 0 2006.201.09:19:32.53#ibcon#about to write, iclass 12, count 0 2006.201.09:19:32.53#ibcon#wrote, iclass 12, count 0 2006.201.09:19:32.53#ibcon#about to read 3, iclass 12, count 0 2006.201.09:19:32.55#ibcon#read 3, iclass 12, count 0 2006.201.09:19:32.55#ibcon#about to read 4, iclass 12, count 0 2006.201.09:19:32.55#ibcon#read 4, iclass 12, count 0 2006.201.09:19:32.55#ibcon#about to read 5, iclass 12, count 0 2006.201.09:19:32.55#ibcon#read 5, iclass 12, count 0 2006.201.09:19:32.55#ibcon#about to read 6, iclass 12, count 0 2006.201.09:19:32.55#ibcon#read 6, iclass 12, count 0 2006.201.09:19:32.55#ibcon#end of sib2, iclass 12, count 0 2006.201.09:19:32.55#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:19:32.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:19:32.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:19:32.55#ibcon#*before write, iclass 12, count 0 2006.201.09:19:32.55#ibcon#enter sib2, iclass 12, count 0 2006.201.09:19:32.55#ibcon#flushed, iclass 12, count 0 2006.201.09:19:32.55#ibcon#about to write, iclass 12, count 0 2006.201.09:19:32.55#ibcon#wrote, iclass 12, count 0 2006.201.09:19:32.55#ibcon#about to read 3, iclass 12, count 0 2006.201.09:19:32.60#ibcon#read 3, iclass 12, count 0 2006.201.09:19:32.60#ibcon#about to read 4, iclass 12, count 0 2006.201.09:19:32.60#ibcon#read 4, iclass 12, count 0 2006.201.09:19:32.60#ibcon#about to read 5, iclass 12, count 0 2006.201.09:19:32.60#ibcon#read 5, iclass 12, count 0 2006.201.09:19:32.60#ibcon#about to read 6, iclass 12, count 0 2006.201.09:19:32.60#ibcon#read 6, iclass 12, count 0 2006.201.09:19:32.60#ibcon#end of sib2, iclass 12, count 0 2006.201.09:19:32.60#ibcon#*after write, iclass 12, count 0 2006.201.09:19:32.60#ibcon#*before return 0, iclass 12, count 0 2006.201.09:19:32.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:32.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:32.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:19:32.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:19:32.60$vck44/va=3,8 2006.201.09:19:32.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.09:19:32.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.09:19:32.60#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:32.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:32.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:32.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:32.65#ibcon#enter wrdev, iclass 14, count 2 2006.201.09:19:32.65#ibcon#first serial, iclass 14, count 2 2006.201.09:19:32.65#ibcon#enter sib2, iclass 14, count 2 2006.201.09:19:32.65#ibcon#flushed, iclass 14, count 2 2006.201.09:19:32.65#ibcon#about to write, iclass 14, count 2 2006.201.09:19:32.65#ibcon#wrote, iclass 14, count 2 2006.201.09:19:32.65#ibcon#about to read 3, iclass 14, count 2 2006.201.09:19:32.67#ibcon#read 3, iclass 14, count 2 2006.201.09:19:32.67#ibcon#about to read 4, iclass 14, count 2 2006.201.09:19:32.67#ibcon#read 4, iclass 14, count 2 2006.201.09:19:32.67#ibcon#about to read 5, iclass 14, count 2 2006.201.09:19:32.67#ibcon#read 5, iclass 14, count 2 2006.201.09:19:32.67#ibcon#about to read 6, iclass 14, count 2 2006.201.09:19:32.67#ibcon#read 6, iclass 14, count 2 2006.201.09:19:32.67#ibcon#end of sib2, iclass 14, count 2 2006.201.09:19:32.67#ibcon#*mode == 0, iclass 14, count 2 2006.201.09:19:32.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.09:19:32.67#ibcon#[25=AT03-08\r\n] 2006.201.09:19:32.67#ibcon#*before write, iclass 14, count 2 2006.201.09:19:32.67#ibcon#enter sib2, iclass 14, count 2 2006.201.09:19:32.67#ibcon#flushed, iclass 14, count 2 2006.201.09:19:32.67#ibcon#about to write, iclass 14, count 2 2006.201.09:19:32.67#ibcon#wrote, iclass 14, count 2 2006.201.09:19:32.67#ibcon#about to read 3, iclass 14, count 2 2006.201.09:19:32.70#ibcon#read 3, iclass 14, count 2 2006.201.09:19:32.70#ibcon#about to read 4, iclass 14, count 2 2006.201.09:19:32.70#ibcon#read 4, iclass 14, count 2 2006.201.09:19:32.70#ibcon#about to read 5, iclass 14, count 2 2006.201.09:19:32.70#ibcon#read 5, iclass 14, count 2 2006.201.09:19:32.70#ibcon#about to read 6, iclass 14, count 2 2006.201.09:19:32.70#ibcon#read 6, iclass 14, count 2 2006.201.09:19:32.70#ibcon#end of sib2, iclass 14, count 2 2006.201.09:19:32.70#ibcon#*after write, iclass 14, count 2 2006.201.09:19:32.70#ibcon#*before return 0, iclass 14, count 2 2006.201.09:19:32.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:32.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:32.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.09:19:32.70#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:32.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:32.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:32.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:32.82#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:19:32.82#ibcon#first serial, iclass 14, count 0 2006.201.09:19:32.82#ibcon#enter sib2, iclass 14, count 0 2006.201.09:19:32.82#ibcon#flushed, iclass 14, count 0 2006.201.09:19:32.82#ibcon#about to write, iclass 14, count 0 2006.201.09:19:32.82#ibcon#wrote, iclass 14, count 0 2006.201.09:19:32.82#ibcon#about to read 3, iclass 14, count 0 2006.201.09:19:32.84#ibcon#read 3, iclass 14, count 0 2006.201.09:19:32.84#ibcon#about to read 4, iclass 14, count 0 2006.201.09:19:32.84#ibcon#read 4, iclass 14, count 0 2006.201.09:19:32.84#ibcon#about to read 5, iclass 14, count 0 2006.201.09:19:32.84#ibcon#read 5, iclass 14, count 0 2006.201.09:19:32.84#ibcon#about to read 6, iclass 14, count 0 2006.201.09:19:32.84#ibcon#read 6, iclass 14, count 0 2006.201.09:19:32.84#ibcon#end of sib2, iclass 14, count 0 2006.201.09:19:32.84#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:19:32.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:19:32.84#ibcon#[25=USB\r\n] 2006.201.09:19:32.84#ibcon#*before write, iclass 14, count 0 2006.201.09:19:32.84#ibcon#enter sib2, iclass 14, count 0 2006.201.09:19:32.84#ibcon#flushed, iclass 14, count 0 2006.201.09:19:32.84#ibcon#about to write, iclass 14, count 0 2006.201.09:19:32.84#ibcon#wrote, iclass 14, count 0 2006.201.09:19:32.84#ibcon#about to read 3, iclass 14, count 0 2006.201.09:19:32.87#ibcon#read 3, iclass 14, count 0 2006.201.09:19:32.87#ibcon#about to read 4, iclass 14, count 0 2006.201.09:19:32.87#ibcon#read 4, iclass 14, count 0 2006.201.09:19:32.87#ibcon#about to read 5, iclass 14, count 0 2006.201.09:19:32.87#ibcon#read 5, iclass 14, count 0 2006.201.09:19:32.87#ibcon#about to read 6, iclass 14, count 0 2006.201.09:19:32.87#ibcon#read 6, iclass 14, count 0 2006.201.09:19:32.87#ibcon#end of sib2, iclass 14, count 0 2006.201.09:19:32.87#ibcon#*after write, iclass 14, count 0 2006.201.09:19:32.87#ibcon#*before return 0, iclass 14, count 0 2006.201.09:19:32.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:32.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:32.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:19:32.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:19:32.87$vck44/valo=4,624.99 2006.201.09:19:32.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.09:19:32.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.09:19:32.87#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:32.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:32.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:32.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:32.87#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:19:32.87#ibcon#first serial, iclass 16, count 0 2006.201.09:19:32.87#ibcon#enter sib2, iclass 16, count 0 2006.201.09:19:32.87#ibcon#flushed, iclass 16, count 0 2006.201.09:19:32.87#ibcon#about to write, iclass 16, count 0 2006.201.09:19:32.87#ibcon#wrote, iclass 16, count 0 2006.201.09:19:32.87#ibcon#about to read 3, iclass 16, count 0 2006.201.09:19:32.89#ibcon#read 3, iclass 16, count 0 2006.201.09:19:32.89#ibcon#about to read 4, iclass 16, count 0 2006.201.09:19:32.89#ibcon#read 4, iclass 16, count 0 2006.201.09:19:32.89#ibcon#about to read 5, iclass 16, count 0 2006.201.09:19:32.89#ibcon#read 5, iclass 16, count 0 2006.201.09:19:32.89#ibcon#about to read 6, iclass 16, count 0 2006.201.09:19:32.89#ibcon#read 6, iclass 16, count 0 2006.201.09:19:32.89#ibcon#end of sib2, iclass 16, count 0 2006.201.09:19:32.89#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:19:32.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:19:32.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:19:32.89#ibcon#*before write, iclass 16, count 0 2006.201.09:19:32.89#ibcon#enter sib2, iclass 16, count 0 2006.201.09:19:32.89#ibcon#flushed, iclass 16, count 0 2006.201.09:19:32.89#ibcon#about to write, iclass 16, count 0 2006.201.09:19:32.89#ibcon#wrote, iclass 16, count 0 2006.201.09:19:32.89#ibcon#about to read 3, iclass 16, count 0 2006.201.09:19:32.94#ibcon#read 3, iclass 16, count 0 2006.201.09:19:32.94#ibcon#about to read 4, iclass 16, count 0 2006.201.09:19:32.94#ibcon#read 4, iclass 16, count 0 2006.201.09:19:32.94#ibcon#about to read 5, iclass 16, count 0 2006.201.09:19:32.94#ibcon#read 5, iclass 16, count 0 2006.201.09:19:32.94#ibcon#about to read 6, iclass 16, count 0 2006.201.09:19:32.94#ibcon#read 6, iclass 16, count 0 2006.201.09:19:32.94#ibcon#end of sib2, iclass 16, count 0 2006.201.09:19:32.94#ibcon#*after write, iclass 16, count 0 2006.201.09:19:32.94#ibcon#*before return 0, iclass 16, count 0 2006.201.09:19:32.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:32.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:32.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:19:32.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:19:32.94$vck44/va=4,7 2006.201.09:19:32.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.09:19:32.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.09:19:32.94#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:32.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:32.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:32.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:32.99#ibcon#enter wrdev, iclass 18, count 2 2006.201.09:19:32.99#ibcon#first serial, iclass 18, count 2 2006.201.09:19:32.99#ibcon#enter sib2, iclass 18, count 2 2006.201.09:19:32.99#ibcon#flushed, iclass 18, count 2 2006.201.09:19:32.99#ibcon#about to write, iclass 18, count 2 2006.201.09:19:32.99#ibcon#wrote, iclass 18, count 2 2006.201.09:19:32.99#ibcon#about to read 3, iclass 18, count 2 2006.201.09:19:33.01#ibcon#read 3, iclass 18, count 2 2006.201.09:19:33.01#ibcon#about to read 4, iclass 18, count 2 2006.201.09:19:33.01#ibcon#read 4, iclass 18, count 2 2006.201.09:19:33.01#ibcon#about to read 5, iclass 18, count 2 2006.201.09:19:33.01#ibcon#read 5, iclass 18, count 2 2006.201.09:19:33.01#ibcon#about to read 6, iclass 18, count 2 2006.201.09:19:33.01#ibcon#read 6, iclass 18, count 2 2006.201.09:19:33.01#ibcon#end of sib2, iclass 18, count 2 2006.201.09:19:33.01#ibcon#*mode == 0, iclass 18, count 2 2006.201.09:19:33.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.09:19:33.01#ibcon#[25=AT04-07\r\n] 2006.201.09:19:33.01#ibcon#*before write, iclass 18, count 2 2006.201.09:19:33.01#ibcon#enter sib2, iclass 18, count 2 2006.201.09:19:33.01#ibcon#flushed, iclass 18, count 2 2006.201.09:19:33.01#ibcon#about to write, iclass 18, count 2 2006.201.09:19:33.01#ibcon#wrote, iclass 18, count 2 2006.201.09:19:33.01#ibcon#about to read 3, iclass 18, count 2 2006.201.09:19:33.04#ibcon#read 3, iclass 18, count 2 2006.201.09:19:33.04#ibcon#about to read 4, iclass 18, count 2 2006.201.09:19:33.04#ibcon#read 4, iclass 18, count 2 2006.201.09:19:33.04#ibcon#about to read 5, iclass 18, count 2 2006.201.09:19:33.04#ibcon#read 5, iclass 18, count 2 2006.201.09:19:33.04#ibcon#about to read 6, iclass 18, count 2 2006.201.09:19:33.04#ibcon#read 6, iclass 18, count 2 2006.201.09:19:33.04#ibcon#end of sib2, iclass 18, count 2 2006.201.09:19:33.04#ibcon#*after write, iclass 18, count 2 2006.201.09:19:33.04#ibcon#*before return 0, iclass 18, count 2 2006.201.09:19:33.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:33.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:33.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.09:19:33.04#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:33.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:33.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:33.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:33.16#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:19:33.16#ibcon#first serial, iclass 18, count 0 2006.201.09:19:33.16#ibcon#enter sib2, iclass 18, count 0 2006.201.09:19:33.16#ibcon#flushed, iclass 18, count 0 2006.201.09:19:33.16#ibcon#about to write, iclass 18, count 0 2006.201.09:19:33.16#ibcon#wrote, iclass 18, count 0 2006.201.09:19:33.16#ibcon#about to read 3, iclass 18, count 0 2006.201.09:19:33.18#ibcon#read 3, iclass 18, count 0 2006.201.09:19:33.18#ibcon#about to read 4, iclass 18, count 0 2006.201.09:19:33.18#ibcon#read 4, iclass 18, count 0 2006.201.09:19:33.18#ibcon#about to read 5, iclass 18, count 0 2006.201.09:19:33.18#ibcon#read 5, iclass 18, count 0 2006.201.09:19:33.18#ibcon#about to read 6, iclass 18, count 0 2006.201.09:19:33.18#ibcon#read 6, iclass 18, count 0 2006.201.09:19:33.18#ibcon#end of sib2, iclass 18, count 0 2006.201.09:19:33.18#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:19:33.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:19:33.18#ibcon#[25=USB\r\n] 2006.201.09:19:33.18#ibcon#*before write, iclass 18, count 0 2006.201.09:19:33.18#ibcon#enter sib2, iclass 18, count 0 2006.201.09:19:33.18#ibcon#flushed, iclass 18, count 0 2006.201.09:19:33.18#ibcon#about to write, iclass 18, count 0 2006.201.09:19:33.18#ibcon#wrote, iclass 18, count 0 2006.201.09:19:33.18#ibcon#about to read 3, iclass 18, count 0 2006.201.09:19:33.21#ibcon#read 3, iclass 18, count 0 2006.201.09:19:33.21#ibcon#about to read 4, iclass 18, count 0 2006.201.09:19:33.21#ibcon#read 4, iclass 18, count 0 2006.201.09:19:33.21#ibcon#about to read 5, iclass 18, count 0 2006.201.09:19:33.21#ibcon#read 5, iclass 18, count 0 2006.201.09:19:33.21#ibcon#about to read 6, iclass 18, count 0 2006.201.09:19:33.21#ibcon#read 6, iclass 18, count 0 2006.201.09:19:33.21#ibcon#end of sib2, iclass 18, count 0 2006.201.09:19:33.21#ibcon#*after write, iclass 18, count 0 2006.201.09:19:33.21#ibcon#*before return 0, iclass 18, count 0 2006.201.09:19:33.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:33.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:33.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:19:33.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:19:33.21$vck44/valo=5,734.99 2006.201.09:19:33.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.09:19:33.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.09:19:33.21#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:33.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:33.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:33.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:33.21#ibcon#enter wrdev, iclass 20, count 0 2006.201.09:19:33.21#ibcon#first serial, iclass 20, count 0 2006.201.09:19:33.21#ibcon#enter sib2, iclass 20, count 0 2006.201.09:19:33.21#ibcon#flushed, iclass 20, count 0 2006.201.09:19:33.21#ibcon#about to write, iclass 20, count 0 2006.201.09:19:33.21#ibcon#wrote, iclass 20, count 0 2006.201.09:19:33.21#ibcon#about to read 3, iclass 20, count 0 2006.201.09:19:33.23#ibcon#read 3, iclass 20, count 0 2006.201.09:19:33.23#ibcon#about to read 4, iclass 20, count 0 2006.201.09:19:33.23#ibcon#read 4, iclass 20, count 0 2006.201.09:19:33.23#ibcon#about to read 5, iclass 20, count 0 2006.201.09:19:33.23#ibcon#read 5, iclass 20, count 0 2006.201.09:19:33.23#ibcon#about to read 6, iclass 20, count 0 2006.201.09:19:33.23#ibcon#read 6, iclass 20, count 0 2006.201.09:19:33.23#ibcon#end of sib2, iclass 20, count 0 2006.201.09:19:33.23#ibcon#*mode == 0, iclass 20, count 0 2006.201.09:19:33.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.09:19:33.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:19:33.23#ibcon#*before write, iclass 20, count 0 2006.201.09:19:33.23#ibcon#enter sib2, iclass 20, count 0 2006.201.09:19:33.23#ibcon#flushed, iclass 20, count 0 2006.201.09:19:33.23#ibcon#about to write, iclass 20, count 0 2006.201.09:19:33.23#ibcon#wrote, iclass 20, count 0 2006.201.09:19:33.23#ibcon#about to read 3, iclass 20, count 0 2006.201.09:19:33.27#ibcon#read 3, iclass 20, count 0 2006.201.09:19:33.27#ibcon#about to read 4, iclass 20, count 0 2006.201.09:19:33.27#ibcon#read 4, iclass 20, count 0 2006.201.09:19:33.27#ibcon#about to read 5, iclass 20, count 0 2006.201.09:19:33.27#ibcon#read 5, iclass 20, count 0 2006.201.09:19:33.27#ibcon#about to read 6, iclass 20, count 0 2006.201.09:19:33.27#ibcon#read 6, iclass 20, count 0 2006.201.09:19:33.27#ibcon#end of sib2, iclass 20, count 0 2006.201.09:19:33.27#ibcon#*after write, iclass 20, count 0 2006.201.09:19:33.27#ibcon#*before return 0, iclass 20, count 0 2006.201.09:19:33.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:33.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:33.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.09:19:33.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.09:19:33.27$vck44/va=5,4 2006.201.09:19:33.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.09:19:33.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.09:19:33.27#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:33.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:33.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:33.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:33.33#ibcon#enter wrdev, iclass 22, count 2 2006.201.09:19:33.33#ibcon#first serial, iclass 22, count 2 2006.201.09:19:33.33#ibcon#enter sib2, iclass 22, count 2 2006.201.09:19:33.33#ibcon#flushed, iclass 22, count 2 2006.201.09:19:33.33#ibcon#about to write, iclass 22, count 2 2006.201.09:19:33.33#ibcon#wrote, iclass 22, count 2 2006.201.09:19:33.33#ibcon#about to read 3, iclass 22, count 2 2006.201.09:19:33.35#ibcon#read 3, iclass 22, count 2 2006.201.09:19:33.35#ibcon#about to read 4, iclass 22, count 2 2006.201.09:19:33.35#ibcon#read 4, iclass 22, count 2 2006.201.09:19:33.35#ibcon#about to read 5, iclass 22, count 2 2006.201.09:19:33.35#ibcon#read 5, iclass 22, count 2 2006.201.09:19:33.35#ibcon#about to read 6, iclass 22, count 2 2006.201.09:19:33.35#ibcon#read 6, iclass 22, count 2 2006.201.09:19:33.35#ibcon#end of sib2, iclass 22, count 2 2006.201.09:19:33.35#ibcon#*mode == 0, iclass 22, count 2 2006.201.09:19:33.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.09:19:33.35#ibcon#[25=AT05-04\r\n] 2006.201.09:19:33.35#ibcon#*before write, iclass 22, count 2 2006.201.09:19:33.35#ibcon#enter sib2, iclass 22, count 2 2006.201.09:19:33.35#ibcon#flushed, iclass 22, count 2 2006.201.09:19:33.35#ibcon#about to write, iclass 22, count 2 2006.201.09:19:33.35#ibcon#wrote, iclass 22, count 2 2006.201.09:19:33.35#ibcon#about to read 3, iclass 22, count 2 2006.201.09:19:33.38#ibcon#read 3, iclass 22, count 2 2006.201.09:19:33.38#ibcon#about to read 4, iclass 22, count 2 2006.201.09:19:33.38#ibcon#read 4, iclass 22, count 2 2006.201.09:19:33.38#ibcon#about to read 5, iclass 22, count 2 2006.201.09:19:33.38#ibcon#read 5, iclass 22, count 2 2006.201.09:19:33.38#ibcon#about to read 6, iclass 22, count 2 2006.201.09:19:33.38#ibcon#read 6, iclass 22, count 2 2006.201.09:19:33.38#ibcon#end of sib2, iclass 22, count 2 2006.201.09:19:33.38#ibcon#*after write, iclass 22, count 2 2006.201.09:19:33.38#ibcon#*before return 0, iclass 22, count 2 2006.201.09:19:33.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:33.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:33.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.09:19:33.38#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:33.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:33.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:33.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:33.50#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:19:33.50#ibcon#first serial, iclass 22, count 0 2006.201.09:19:33.50#ibcon#enter sib2, iclass 22, count 0 2006.201.09:19:33.50#ibcon#flushed, iclass 22, count 0 2006.201.09:19:33.50#ibcon#about to write, iclass 22, count 0 2006.201.09:19:33.50#ibcon#wrote, iclass 22, count 0 2006.201.09:19:33.50#ibcon#about to read 3, iclass 22, count 0 2006.201.09:19:33.52#ibcon#read 3, iclass 22, count 0 2006.201.09:19:33.52#ibcon#about to read 4, iclass 22, count 0 2006.201.09:19:33.52#ibcon#read 4, iclass 22, count 0 2006.201.09:19:33.52#ibcon#about to read 5, iclass 22, count 0 2006.201.09:19:33.52#ibcon#read 5, iclass 22, count 0 2006.201.09:19:33.52#ibcon#about to read 6, iclass 22, count 0 2006.201.09:19:33.52#ibcon#read 6, iclass 22, count 0 2006.201.09:19:33.52#ibcon#end of sib2, iclass 22, count 0 2006.201.09:19:33.52#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:19:33.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:19:33.52#ibcon#[25=USB\r\n] 2006.201.09:19:33.52#ibcon#*before write, iclass 22, count 0 2006.201.09:19:33.52#ibcon#enter sib2, iclass 22, count 0 2006.201.09:19:33.52#ibcon#flushed, iclass 22, count 0 2006.201.09:19:33.52#ibcon#about to write, iclass 22, count 0 2006.201.09:19:33.52#ibcon#wrote, iclass 22, count 0 2006.201.09:19:33.52#ibcon#about to read 3, iclass 22, count 0 2006.201.09:19:33.55#ibcon#read 3, iclass 22, count 0 2006.201.09:19:33.55#ibcon#about to read 4, iclass 22, count 0 2006.201.09:19:33.55#ibcon#read 4, iclass 22, count 0 2006.201.09:19:33.55#ibcon#about to read 5, iclass 22, count 0 2006.201.09:19:33.55#ibcon#read 5, iclass 22, count 0 2006.201.09:19:33.55#ibcon#about to read 6, iclass 22, count 0 2006.201.09:19:33.55#ibcon#read 6, iclass 22, count 0 2006.201.09:19:33.55#ibcon#end of sib2, iclass 22, count 0 2006.201.09:19:33.55#ibcon#*after write, iclass 22, count 0 2006.201.09:19:33.55#ibcon#*before return 0, iclass 22, count 0 2006.201.09:19:33.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:33.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:33.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:19:33.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:19:33.55$vck44/valo=6,814.99 2006.201.09:19:33.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.09:19:33.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.09:19:33.55#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:33.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:33.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:33.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:33.55#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:19:33.55#ibcon#first serial, iclass 24, count 0 2006.201.09:19:33.55#ibcon#enter sib2, iclass 24, count 0 2006.201.09:19:33.55#ibcon#flushed, iclass 24, count 0 2006.201.09:19:33.55#ibcon#about to write, iclass 24, count 0 2006.201.09:19:33.55#ibcon#wrote, iclass 24, count 0 2006.201.09:19:33.55#ibcon#about to read 3, iclass 24, count 0 2006.201.09:19:33.57#ibcon#read 3, iclass 24, count 0 2006.201.09:19:33.57#ibcon#about to read 4, iclass 24, count 0 2006.201.09:19:33.57#ibcon#read 4, iclass 24, count 0 2006.201.09:19:33.57#ibcon#about to read 5, iclass 24, count 0 2006.201.09:19:33.57#ibcon#read 5, iclass 24, count 0 2006.201.09:19:33.57#ibcon#about to read 6, iclass 24, count 0 2006.201.09:19:33.57#ibcon#read 6, iclass 24, count 0 2006.201.09:19:33.57#ibcon#end of sib2, iclass 24, count 0 2006.201.09:19:33.57#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:19:33.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:19:33.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:19:33.57#ibcon#*before write, iclass 24, count 0 2006.201.09:19:33.57#ibcon#enter sib2, iclass 24, count 0 2006.201.09:19:33.57#ibcon#flushed, iclass 24, count 0 2006.201.09:19:33.57#ibcon#about to write, iclass 24, count 0 2006.201.09:19:33.57#ibcon#wrote, iclass 24, count 0 2006.201.09:19:33.57#ibcon#about to read 3, iclass 24, count 0 2006.201.09:19:33.62#ibcon#read 3, iclass 24, count 0 2006.201.09:19:33.62#ibcon#about to read 4, iclass 24, count 0 2006.201.09:19:33.62#ibcon#read 4, iclass 24, count 0 2006.201.09:19:33.62#ibcon#about to read 5, iclass 24, count 0 2006.201.09:19:33.62#ibcon#read 5, iclass 24, count 0 2006.201.09:19:33.62#ibcon#about to read 6, iclass 24, count 0 2006.201.09:19:33.62#ibcon#read 6, iclass 24, count 0 2006.201.09:19:33.62#ibcon#end of sib2, iclass 24, count 0 2006.201.09:19:33.62#ibcon#*after write, iclass 24, count 0 2006.201.09:19:33.62#ibcon#*before return 0, iclass 24, count 0 2006.201.09:19:33.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:33.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:33.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:19:33.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:19:33.62$vck44/va=6,5 2006.201.09:19:33.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.09:19:33.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.09:19:33.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:33.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:33.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:33.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:33.67#ibcon#enter wrdev, iclass 26, count 2 2006.201.09:19:33.67#ibcon#first serial, iclass 26, count 2 2006.201.09:19:33.67#ibcon#enter sib2, iclass 26, count 2 2006.201.09:19:33.67#ibcon#flushed, iclass 26, count 2 2006.201.09:19:33.67#ibcon#about to write, iclass 26, count 2 2006.201.09:19:33.67#ibcon#wrote, iclass 26, count 2 2006.201.09:19:33.67#ibcon#about to read 3, iclass 26, count 2 2006.201.09:19:33.69#ibcon#read 3, iclass 26, count 2 2006.201.09:19:33.69#ibcon#about to read 4, iclass 26, count 2 2006.201.09:19:33.69#ibcon#read 4, iclass 26, count 2 2006.201.09:19:33.69#ibcon#about to read 5, iclass 26, count 2 2006.201.09:19:33.69#ibcon#read 5, iclass 26, count 2 2006.201.09:19:33.69#ibcon#about to read 6, iclass 26, count 2 2006.201.09:19:33.69#ibcon#read 6, iclass 26, count 2 2006.201.09:19:33.69#ibcon#end of sib2, iclass 26, count 2 2006.201.09:19:33.69#ibcon#*mode == 0, iclass 26, count 2 2006.201.09:19:33.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.09:19:33.69#ibcon#[25=AT06-05\r\n] 2006.201.09:19:33.69#ibcon#*before write, iclass 26, count 2 2006.201.09:19:33.69#ibcon#enter sib2, iclass 26, count 2 2006.201.09:19:33.69#ibcon#flushed, iclass 26, count 2 2006.201.09:19:33.69#ibcon#about to write, iclass 26, count 2 2006.201.09:19:33.69#ibcon#wrote, iclass 26, count 2 2006.201.09:19:33.69#ibcon#about to read 3, iclass 26, count 2 2006.201.09:19:33.72#ibcon#read 3, iclass 26, count 2 2006.201.09:19:33.72#ibcon#about to read 4, iclass 26, count 2 2006.201.09:19:33.72#ibcon#read 4, iclass 26, count 2 2006.201.09:19:33.72#ibcon#about to read 5, iclass 26, count 2 2006.201.09:19:33.72#ibcon#read 5, iclass 26, count 2 2006.201.09:19:33.72#ibcon#about to read 6, iclass 26, count 2 2006.201.09:19:33.72#ibcon#read 6, iclass 26, count 2 2006.201.09:19:33.72#ibcon#end of sib2, iclass 26, count 2 2006.201.09:19:33.72#ibcon#*after write, iclass 26, count 2 2006.201.09:19:33.72#ibcon#*before return 0, iclass 26, count 2 2006.201.09:19:33.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:33.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:33.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.09:19:33.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:33.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:33.75#abcon#<5=/05 2.6 4.9 22.74 901003.8\r\n> 2006.201.09:19:33.77#abcon#{5=INTERFACE CLEAR} 2006.201.09:19:33.83#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:19:33.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:33.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:33.84#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:19:33.84#ibcon#first serial, iclass 26, count 0 2006.201.09:19:33.84#ibcon#enter sib2, iclass 26, count 0 2006.201.09:19:33.84#ibcon#flushed, iclass 26, count 0 2006.201.09:19:33.84#ibcon#about to write, iclass 26, count 0 2006.201.09:19:33.84#ibcon#wrote, iclass 26, count 0 2006.201.09:19:33.84#ibcon#about to read 3, iclass 26, count 0 2006.201.09:19:33.86#ibcon#read 3, iclass 26, count 0 2006.201.09:19:33.86#ibcon#about to read 4, iclass 26, count 0 2006.201.09:19:33.86#ibcon#read 4, iclass 26, count 0 2006.201.09:19:33.86#ibcon#about to read 5, iclass 26, count 0 2006.201.09:19:33.86#ibcon#read 5, iclass 26, count 0 2006.201.09:19:33.86#ibcon#about to read 6, iclass 26, count 0 2006.201.09:19:33.86#ibcon#read 6, iclass 26, count 0 2006.201.09:19:33.86#ibcon#end of sib2, iclass 26, count 0 2006.201.09:19:33.86#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:19:33.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:19:33.86#ibcon#[25=USB\r\n] 2006.201.09:19:33.86#ibcon#*before write, iclass 26, count 0 2006.201.09:19:33.86#ibcon#enter sib2, iclass 26, count 0 2006.201.09:19:33.86#ibcon#flushed, iclass 26, count 0 2006.201.09:19:33.86#ibcon#about to write, iclass 26, count 0 2006.201.09:19:33.86#ibcon#wrote, iclass 26, count 0 2006.201.09:19:33.86#ibcon#about to read 3, iclass 26, count 0 2006.201.09:19:33.89#ibcon#read 3, iclass 26, count 0 2006.201.09:19:33.89#ibcon#about to read 4, iclass 26, count 0 2006.201.09:19:33.89#ibcon#read 4, iclass 26, count 0 2006.201.09:19:33.89#ibcon#about to read 5, iclass 26, count 0 2006.201.09:19:33.89#ibcon#read 5, iclass 26, count 0 2006.201.09:19:33.89#ibcon#about to read 6, iclass 26, count 0 2006.201.09:19:33.89#ibcon#read 6, iclass 26, count 0 2006.201.09:19:33.89#ibcon#end of sib2, iclass 26, count 0 2006.201.09:19:33.89#ibcon#*after write, iclass 26, count 0 2006.201.09:19:33.89#ibcon#*before return 0, iclass 26, count 0 2006.201.09:19:33.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:33.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:33.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:19:33.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:19:33.89$vck44/valo=7,864.99 2006.201.09:19:33.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.09:19:33.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.09:19:33.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:33.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:33.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:33.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:33.89#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:19:33.89#ibcon#first serial, iclass 32, count 0 2006.201.09:19:33.89#ibcon#enter sib2, iclass 32, count 0 2006.201.09:19:33.89#ibcon#flushed, iclass 32, count 0 2006.201.09:19:33.89#ibcon#about to write, iclass 32, count 0 2006.201.09:19:33.89#ibcon#wrote, iclass 32, count 0 2006.201.09:19:33.89#ibcon#about to read 3, iclass 32, count 0 2006.201.09:19:33.91#ibcon#read 3, iclass 32, count 0 2006.201.09:19:33.91#ibcon#about to read 4, iclass 32, count 0 2006.201.09:19:33.91#ibcon#read 4, iclass 32, count 0 2006.201.09:19:33.91#ibcon#about to read 5, iclass 32, count 0 2006.201.09:19:33.91#ibcon#read 5, iclass 32, count 0 2006.201.09:19:33.91#ibcon#about to read 6, iclass 32, count 0 2006.201.09:19:33.91#ibcon#read 6, iclass 32, count 0 2006.201.09:19:33.91#ibcon#end of sib2, iclass 32, count 0 2006.201.09:19:33.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:19:33.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:19:33.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:19:33.91#ibcon#*before write, iclass 32, count 0 2006.201.09:19:33.91#ibcon#enter sib2, iclass 32, count 0 2006.201.09:19:33.91#ibcon#flushed, iclass 32, count 0 2006.201.09:19:33.91#ibcon#about to write, iclass 32, count 0 2006.201.09:19:33.91#ibcon#wrote, iclass 32, count 0 2006.201.09:19:33.91#ibcon#about to read 3, iclass 32, count 0 2006.201.09:19:33.95#ibcon#read 3, iclass 32, count 0 2006.201.09:19:33.95#ibcon#about to read 4, iclass 32, count 0 2006.201.09:19:33.95#ibcon#read 4, iclass 32, count 0 2006.201.09:19:33.95#ibcon#about to read 5, iclass 32, count 0 2006.201.09:19:33.95#ibcon#read 5, iclass 32, count 0 2006.201.09:19:33.95#ibcon#about to read 6, iclass 32, count 0 2006.201.09:19:33.95#ibcon#read 6, iclass 32, count 0 2006.201.09:19:33.95#ibcon#end of sib2, iclass 32, count 0 2006.201.09:19:33.95#ibcon#*after write, iclass 32, count 0 2006.201.09:19:33.95#ibcon#*before return 0, iclass 32, count 0 2006.201.09:19:33.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:33.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:33.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:19:33.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:19:33.95$vck44/va=7,5 2006.201.09:19:33.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.09:19:33.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.09:19:33.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:33.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:34.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:34.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:34.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.09:19:34.01#ibcon#first serial, iclass 34, count 2 2006.201.09:19:34.01#ibcon#enter sib2, iclass 34, count 2 2006.201.09:19:34.01#ibcon#flushed, iclass 34, count 2 2006.201.09:19:34.01#ibcon#about to write, iclass 34, count 2 2006.201.09:19:34.01#ibcon#wrote, iclass 34, count 2 2006.201.09:19:34.01#ibcon#about to read 3, iclass 34, count 2 2006.201.09:19:34.03#ibcon#read 3, iclass 34, count 2 2006.201.09:19:34.03#ibcon#about to read 4, iclass 34, count 2 2006.201.09:19:34.03#ibcon#read 4, iclass 34, count 2 2006.201.09:19:34.03#ibcon#about to read 5, iclass 34, count 2 2006.201.09:19:34.03#ibcon#read 5, iclass 34, count 2 2006.201.09:19:34.03#ibcon#about to read 6, iclass 34, count 2 2006.201.09:19:34.03#ibcon#read 6, iclass 34, count 2 2006.201.09:19:34.03#ibcon#end of sib2, iclass 34, count 2 2006.201.09:19:34.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.09:19:34.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.09:19:34.03#ibcon#[25=AT07-05\r\n] 2006.201.09:19:34.03#ibcon#*before write, iclass 34, count 2 2006.201.09:19:34.03#ibcon#enter sib2, iclass 34, count 2 2006.201.09:19:34.03#ibcon#flushed, iclass 34, count 2 2006.201.09:19:34.03#ibcon#about to write, iclass 34, count 2 2006.201.09:19:34.03#ibcon#wrote, iclass 34, count 2 2006.201.09:19:34.03#ibcon#about to read 3, iclass 34, count 2 2006.201.09:19:34.06#ibcon#read 3, iclass 34, count 2 2006.201.09:19:34.06#ibcon#about to read 4, iclass 34, count 2 2006.201.09:19:34.06#ibcon#read 4, iclass 34, count 2 2006.201.09:19:34.06#ibcon#about to read 5, iclass 34, count 2 2006.201.09:19:34.06#ibcon#read 5, iclass 34, count 2 2006.201.09:19:34.06#ibcon#about to read 6, iclass 34, count 2 2006.201.09:19:34.06#ibcon#read 6, iclass 34, count 2 2006.201.09:19:34.06#ibcon#end of sib2, iclass 34, count 2 2006.201.09:19:34.06#ibcon#*after write, iclass 34, count 2 2006.201.09:19:34.06#ibcon#*before return 0, iclass 34, count 2 2006.201.09:19:34.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:34.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:34.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.09:19:34.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:34.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:34.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:34.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:34.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:19:34.18#ibcon#first serial, iclass 34, count 0 2006.201.09:19:34.18#ibcon#enter sib2, iclass 34, count 0 2006.201.09:19:34.18#ibcon#flushed, iclass 34, count 0 2006.201.09:19:34.18#ibcon#about to write, iclass 34, count 0 2006.201.09:19:34.18#ibcon#wrote, iclass 34, count 0 2006.201.09:19:34.18#ibcon#about to read 3, iclass 34, count 0 2006.201.09:19:34.20#ibcon#read 3, iclass 34, count 0 2006.201.09:19:34.20#ibcon#about to read 4, iclass 34, count 0 2006.201.09:19:34.20#ibcon#read 4, iclass 34, count 0 2006.201.09:19:34.20#ibcon#about to read 5, iclass 34, count 0 2006.201.09:19:34.20#ibcon#read 5, iclass 34, count 0 2006.201.09:19:34.20#ibcon#about to read 6, iclass 34, count 0 2006.201.09:19:34.20#ibcon#read 6, iclass 34, count 0 2006.201.09:19:34.20#ibcon#end of sib2, iclass 34, count 0 2006.201.09:19:34.20#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:19:34.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:19:34.20#ibcon#[25=USB\r\n] 2006.201.09:19:34.20#ibcon#*before write, iclass 34, count 0 2006.201.09:19:34.20#ibcon#enter sib2, iclass 34, count 0 2006.201.09:19:34.20#ibcon#flushed, iclass 34, count 0 2006.201.09:19:34.20#ibcon#about to write, iclass 34, count 0 2006.201.09:19:34.20#ibcon#wrote, iclass 34, count 0 2006.201.09:19:34.20#ibcon#about to read 3, iclass 34, count 0 2006.201.09:19:34.23#ibcon#read 3, iclass 34, count 0 2006.201.09:19:34.23#ibcon#about to read 4, iclass 34, count 0 2006.201.09:19:34.23#ibcon#read 4, iclass 34, count 0 2006.201.09:19:34.23#ibcon#about to read 5, iclass 34, count 0 2006.201.09:19:34.23#ibcon#read 5, iclass 34, count 0 2006.201.09:19:34.23#ibcon#about to read 6, iclass 34, count 0 2006.201.09:19:34.23#ibcon#read 6, iclass 34, count 0 2006.201.09:19:34.23#ibcon#end of sib2, iclass 34, count 0 2006.201.09:19:34.23#ibcon#*after write, iclass 34, count 0 2006.201.09:19:34.23#ibcon#*before return 0, iclass 34, count 0 2006.201.09:19:34.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:34.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:34.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:19:34.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:19:34.23$vck44/valo=8,884.99 2006.201.09:19:34.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.09:19:34.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.09:19:34.23#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:34.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:34.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:34.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:34.23#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:19:34.23#ibcon#first serial, iclass 36, count 0 2006.201.09:19:34.23#ibcon#enter sib2, iclass 36, count 0 2006.201.09:19:34.23#ibcon#flushed, iclass 36, count 0 2006.201.09:19:34.23#ibcon#about to write, iclass 36, count 0 2006.201.09:19:34.23#ibcon#wrote, iclass 36, count 0 2006.201.09:19:34.23#ibcon#about to read 3, iclass 36, count 0 2006.201.09:19:34.25#ibcon#read 3, iclass 36, count 0 2006.201.09:19:34.25#ibcon#about to read 4, iclass 36, count 0 2006.201.09:19:34.25#ibcon#read 4, iclass 36, count 0 2006.201.09:19:34.25#ibcon#about to read 5, iclass 36, count 0 2006.201.09:19:34.25#ibcon#read 5, iclass 36, count 0 2006.201.09:19:34.25#ibcon#about to read 6, iclass 36, count 0 2006.201.09:19:34.25#ibcon#read 6, iclass 36, count 0 2006.201.09:19:34.25#ibcon#end of sib2, iclass 36, count 0 2006.201.09:19:34.25#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:19:34.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:19:34.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:19:34.25#ibcon#*before write, iclass 36, count 0 2006.201.09:19:34.25#ibcon#enter sib2, iclass 36, count 0 2006.201.09:19:34.25#ibcon#flushed, iclass 36, count 0 2006.201.09:19:34.25#ibcon#about to write, iclass 36, count 0 2006.201.09:19:34.25#ibcon#wrote, iclass 36, count 0 2006.201.09:19:34.25#ibcon#about to read 3, iclass 36, count 0 2006.201.09:19:34.29#ibcon#read 3, iclass 36, count 0 2006.201.09:19:34.29#ibcon#about to read 4, iclass 36, count 0 2006.201.09:19:34.29#ibcon#read 4, iclass 36, count 0 2006.201.09:19:34.29#ibcon#about to read 5, iclass 36, count 0 2006.201.09:19:34.29#ibcon#read 5, iclass 36, count 0 2006.201.09:19:34.29#ibcon#about to read 6, iclass 36, count 0 2006.201.09:19:34.29#ibcon#read 6, iclass 36, count 0 2006.201.09:19:34.29#ibcon#end of sib2, iclass 36, count 0 2006.201.09:19:34.29#ibcon#*after write, iclass 36, count 0 2006.201.09:19:34.29#ibcon#*before return 0, iclass 36, count 0 2006.201.09:19:34.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:34.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:34.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:19:34.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:19:34.29$vck44/va=8,4 2006.201.09:19:34.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.09:19:34.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.09:19:34.29#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:34.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:19:34.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:19:34.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:19:34.35#ibcon#enter wrdev, iclass 38, count 2 2006.201.09:19:34.35#ibcon#first serial, iclass 38, count 2 2006.201.09:19:34.35#ibcon#enter sib2, iclass 38, count 2 2006.201.09:19:34.35#ibcon#flushed, iclass 38, count 2 2006.201.09:19:34.35#ibcon#about to write, iclass 38, count 2 2006.201.09:19:34.35#ibcon#wrote, iclass 38, count 2 2006.201.09:19:34.35#ibcon#about to read 3, iclass 38, count 2 2006.201.09:19:34.37#ibcon#read 3, iclass 38, count 2 2006.201.09:19:34.37#ibcon#about to read 4, iclass 38, count 2 2006.201.09:19:34.37#ibcon#read 4, iclass 38, count 2 2006.201.09:19:34.37#ibcon#about to read 5, iclass 38, count 2 2006.201.09:19:34.37#ibcon#read 5, iclass 38, count 2 2006.201.09:19:34.37#ibcon#about to read 6, iclass 38, count 2 2006.201.09:19:34.37#ibcon#read 6, iclass 38, count 2 2006.201.09:19:34.37#ibcon#end of sib2, iclass 38, count 2 2006.201.09:19:34.37#ibcon#*mode == 0, iclass 38, count 2 2006.201.09:19:34.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.09:19:34.37#ibcon#[25=AT08-04\r\n] 2006.201.09:19:34.37#ibcon#*before write, iclass 38, count 2 2006.201.09:19:34.37#ibcon#enter sib2, iclass 38, count 2 2006.201.09:19:34.37#ibcon#flushed, iclass 38, count 2 2006.201.09:19:34.37#ibcon#about to write, iclass 38, count 2 2006.201.09:19:34.37#ibcon#wrote, iclass 38, count 2 2006.201.09:19:34.37#ibcon#about to read 3, iclass 38, count 2 2006.201.09:19:34.40#ibcon#read 3, iclass 38, count 2 2006.201.09:19:34.40#ibcon#about to read 4, iclass 38, count 2 2006.201.09:19:34.40#ibcon#read 4, iclass 38, count 2 2006.201.09:19:34.40#ibcon#about to read 5, iclass 38, count 2 2006.201.09:19:34.40#ibcon#read 5, iclass 38, count 2 2006.201.09:19:34.40#ibcon#about to read 6, iclass 38, count 2 2006.201.09:19:34.40#ibcon#read 6, iclass 38, count 2 2006.201.09:19:34.40#ibcon#end of sib2, iclass 38, count 2 2006.201.09:19:34.40#ibcon#*after write, iclass 38, count 2 2006.201.09:19:34.40#ibcon#*before return 0, iclass 38, count 2 2006.201.09:19:34.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:19:34.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:19:34.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.09:19:34.40#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:34.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:19:34.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:19:34.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:19:34.52#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:19:34.52#ibcon#first serial, iclass 38, count 0 2006.201.09:19:34.52#ibcon#enter sib2, iclass 38, count 0 2006.201.09:19:34.52#ibcon#flushed, iclass 38, count 0 2006.201.09:19:34.52#ibcon#about to write, iclass 38, count 0 2006.201.09:19:34.52#ibcon#wrote, iclass 38, count 0 2006.201.09:19:34.52#ibcon#about to read 3, iclass 38, count 0 2006.201.09:19:34.54#ibcon#read 3, iclass 38, count 0 2006.201.09:19:34.54#ibcon#about to read 4, iclass 38, count 0 2006.201.09:19:34.54#ibcon#read 4, iclass 38, count 0 2006.201.09:19:34.54#ibcon#about to read 5, iclass 38, count 0 2006.201.09:19:34.54#ibcon#read 5, iclass 38, count 0 2006.201.09:19:34.54#ibcon#about to read 6, iclass 38, count 0 2006.201.09:19:34.54#ibcon#read 6, iclass 38, count 0 2006.201.09:19:34.54#ibcon#end of sib2, iclass 38, count 0 2006.201.09:19:34.54#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:19:34.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:19:34.54#ibcon#[25=USB\r\n] 2006.201.09:19:34.54#ibcon#*before write, iclass 38, count 0 2006.201.09:19:34.54#ibcon#enter sib2, iclass 38, count 0 2006.201.09:19:34.54#ibcon#flushed, iclass 38, count 0 2006.201.09:19:34.54#ibcon#about to write, iclass 38, count 0 2006.201.09:19:34.54#ibcon#wrote, iclass 38, count 0 2006.201.09:19:34.54#ibcon#about to read 3, iclass 38, count 0 2006.201.09:19:34.57#ibcon#read 3, iclass 38, count 0 2006.201.09:19:34.57#ibcon#about to read 4, iclass 38, count 0 2006.201.09:19:34.57#ibcon#read 4, iclass 38, count 0 2006.201.09:19:34.57#ibcon#about to read 5, iclass 38, count 0 2006.201.09:19:34.57#ibcon#read 5, iclass 38, count 0 2006.201.09:19:34.57#ibcon#about to read 6, iclass 38, count 0 2006.201.09:19:34.57#ibcon#read 6, iclass 38, count 0 2006.201.09:19:34.57#ibcon#end of sib2, iclass 38, count 0 2006.201.09:19:34.57#ibcon#*after write, iclass 38, count 0 2006.201.09:19:34.57#ibcon#*before return 0, iclass 38, count 0 2006.201.09:19:34.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:19:34.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:19:34.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:19:34.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:19:34.57$vck44/vblo=1,629.99 2006.201.09:19:34.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.09:19:34.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.09:19:34.57#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:34.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:34.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:34.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:34.57#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:19:34.57#ibcon#first serial, iclass 40, count 0 2006.201.09:19:34.57#ibcon#enter sib2, iclass 40, count 0 2006.201.09:19:34.57#ibcon#flushed, iclass 40, count 0 2006.201.09:19:34.57#ibcon#about to write, iclass 40, count 0 2006.201.09:19:34.57#ibcon#wrote, iclass 40, count 0 2006.201.09:19:34.57#ibcon#about to read 3, iclass 40, count 0 2006.201.09:19:34.59#ibcon#read 3, iclass 40, count 0 2006.201.09:19:34.59#ibcon#about to read 4, iclass 40, count 0 2006.201.09:19:34.59#ibcon#read 4, iclass 40, count 0 2006.201.09:19:34.59#ibcon#about to read 5, iclass 40, count 0 2006.201.09:19:34.59#ibcon#read 5, iclass 40, count 0 2006.201.09:19:34.59#ibcon#about to read 6, iclass 40, count 0 2006.201.09:19:34.59#ibcon#read 6, iclass 40, count 0 2006.201.09:19:34.59#ibcon#end of sib2, iclass 40, count 0 2006.201.09:19:34.59#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:19:34.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:19:34.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:19:34.59#ibcon#*before write, iclass 40, count 0 2006.201.09:19:34.59#ibcon#enter sib2, iclass 40, count 0 2006.201.09:19:34.59#ibcon#flushed, iclass 40, count 0 2006.201.09:19:34.59#ibcon#about to write, iclass 40, count 0 2006.201.09:19:34.59#ibcon#wrote, iclass 40, count 0 2006.201.09:19:34.59#ibcon#about to read 3, iclass 40, count 0 2006.201.09:19:34.64#ibcon#read 3, iclass 40, count 0 2006.201.09:19:34.64#ibcon#about to read 4, iclass 40, count 0 2006.201.09:19:34.64#ibcon#read 4, iclass 40, count 0 2006.201.09:19:34.64#ibcon#about to read 5, iclass 40, count 0 2006.201.09:19:34.64#ibcon#read 5, iclass 40, count 0 2006.201.09:19:34.64#ibcon#about to read 6, iclass 40, count 0 2006.201.09:19:34.64#ibcon#read 6, iclass 40, count 0 2006.201.09:19:34.64#ibcon#end of sib2, iclass 40, count 0 2006.201.09:19:34.64#ibcon#*after write, iclass 40, count 0 2006.201.09:19:34.64#ibcon#*before return 0, iclass 40, count 0 2006.201.09:19:34.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:34.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:19:34.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:19:34.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:19:34.64$vck44/vb=1,4 2006.201.09:19:34.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.09:19:34.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.09:19:34.64#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:34.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:34.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:34.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:34.64#ibcon#enter wrdev, iclass 4, count 2 2006.201.09:19:34.64#ibcon#first serial, iclass 4, count 2 2006.201.09:19:34.64#ibcon#enter sib2, iclass 4, count 2 2006.201.09:19:34.64#ibcon#flushed, iclass 4, count 2 2006.201.09:19:34.64#ibcon#about to write, iclass 4, count 2 2006.201.09:19:34.64#ibcon#wrote, iclass 4, count 2 2006.201.09:19:34.64#ibcon#about to read 3, iclass 4, count 2 2006.201.09:19:34.66#ibcon#read 3, iclass 4, count 2 2006.201.09:19:34.66#ibcon#about to read 4, iclass 4, count 2 2006.201.09:19:34.66#ibcon#read 4, iclass 4, count 2 2006.201.09:19:34.66#ibcon#about to read 5, iclass 4, count 2 2006.201.09:19:34.66#ibcon#read 5, iclass 4, count 2 2006.201.09:19:34.66#ibcon#about to read 6, iclass 4, count 2 2006.201.09:19:34.66#ibcon#read 6, iclass 4, count 2 2006.201.09:19:34.66#ibcon#end of sib2, iclass 4, count 2 2006.201.09:19:34.66#ibcon#*mode == 0, iclass 4, count 2 2006.201.09:19:34.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.09:19:34.66#ibcon#[27=AT01-04\r\n] 2006.201.09:19:34.66#ibcon#*before write, iclass 4, count 2 2006.201.09:19:34.66#ibcon#enter sib2, iclass 4, count 2 2006.201.09:19:34.66#ibcon#flushed, iclass 4, count 2 2006.201.09:19:34.66#ibcon#about to write, iclass 4, count 2 2006.201.09:19:34.66#ibcon#wrote, iclass 4, count 2 2006.201.09:19:34.66#ibcon#about to read 3, iclass 4, count 2 2006.201.09:19:34.69#ibcon#read 3, iclass 4, count 2 2006.201.09:19:34.69#ibcon#about to read 4, iclass 4, count 2 2006.201.09:19:34.69#ibcon#read 4, iclass 4, count 2 2006.201.09:19:34.69#ibcon#about to read 5, iclass 4, count 2 2006.201.09:19:34.69#ibcon#read 5, iclass 4, count 2 2006.201.09:19:34.69#ibcon#about to read 6, iclass 4, count 2 2006.201.09:19:34.69#ibcon#read 6, iclass 4, count 2 2006.201.09:19:34.69#ibcon#end of sib2, iclass 4, count 2 2006.201.09:19:34.69#ibcon#*after write, iclass 4, count 2 2006.201.09:19:34.69#ibcon#*before return 0, iclass 4, count 2 2006.201.09:19:34.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:34.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:19:34.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.09:19:34.69#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:34.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:34.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:34.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:34.81#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:19:34.81#ibcon#first serial, iclass 4, count 0 2006.201.09:19:34.81#ibcon#enter sib2, iclass 4, count 0 2006.201.09:19:34.81#ibcon#flushed, iclass 4, count 0 2006.201.09:19:34.81#ibcon#about to write, iclass 4, count 0 2006.201.09:19:34.81#ibcon#wrote, iclass 4, count 0 2006.201.09:19:34.81#ibcon#about to read 3, iclass 4, count 0 2006.201.09:19:34.83#ibcon#read 3, iclass 4, count 0 2006.201.09:19:34.83#ibcon#about to read 4, iclass 4, count 0 2006.201.09:19:34.83#ibcon#read 4, iclass 4, count 0 2006.201.09:19:34.83#ibcon#about to read 5, iclass 4, count 0 2006.201.09:19:34.83#ibcon#read 5, iclass 4, count 0 2006.201.09:19:34.83#ibcon#about to read 6, iclass 4, count 0 2006.201.09:19:34.83#ibcon#read 6, iclass 4, count 0 2006.201.09:19:34.83#ibcon#end of sib2, iclass 4, count 0 2006.201.09:19:34.83#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:19:34.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:19:34.83#ibcon#[27=USB\r\n] 2006.201.09:19:34.83#ibcon#*before write, iclass 4, count 0 2006.201.09:19:34.83#ibcon#enter sib2, iclass 4, count 0 2006.201.09:19:34.83#ibcon#flushed, iclass 4, count 0 2006.201.09:19:34.83#ibcon#about to write, iclass 4, count 0 2006.201.09:19:34.83#ibcon#wrote, iclass 4, count 0 2006.201.09:19:34.83#ibcon#about to read 3, iclass 4, count 0 2006.201.09:19:34.86#ibcon#read 3, iclass 4, count 0 2006.201.09:19:34.86#ibcon#about to read 4, iclass 4, count 0 2006.201.09:19:34.86#ibcon#read 4, iclass 4, count 0 2006.201.09:19:34.86#ibcon#about to read 5, iclass 4, count 0 2006.201.09:19:34.86#ibcon#read 5, iclass 4, count 0 2006.201.09:19:34.86#ibcon#about to read 6, iclass 4, count 0 2006.201.09:19:34.86#ibcon#read 6, iclass 4, count 0 2006.201.09:19:34.86#ibcon#end of sib2, iclass 4, count 0 2006.201.09:19:34.86#ibcon#*after write, iclass 4, count 0 2006.201.09:19:34.86#ibcon#*before return 0, iclass 4, count 0 2006.201.09:19:34.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:34.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:19:34.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:19:34.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:19:34.86$vck44/vblo=2,634.99 2006.201.09:19:34.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.09:19:34.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.09:19:34.86#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:34.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:34.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:34.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:34.86#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:19:34.86#ibcon#first serial, iclass 6, count 0 2006.201.09:19:34.86#ibcon#enter sib2, iclass 6, count 0 2006.201.09:19:34.86#ibcon#flushed, iclass 6, count 0 2006.201.09:19:34.86#ibcon#about to write, iclass 6, count 0 2006.201.09:19:34.86#ibcon#wrote, iclass 6, count 0 2006.201.09:19:34.86#ibcon#about to read 3, iclass 6, count 0 2006.201.09:19:34.88#ibcon#read 3, iclass 6, count 0 2006.201.09:19:34.88#ibcon#about to read 4, iclass 6, count 0 2006.201.09:19:34.88#ibcon#read 4, iclass 6, count 0 2006.201.09:19:34.88#ibcon#about to read 5, iclass 6, count 0 2006.201.09:19:34.88#ibcon#read 5, iclass 6, count 0 2006.201.09:19:34.88#ibcon#about to read 6, iclass 6, count 0 2006.201.09:19:34.88#ibcon#read 6, iclass 6, count 0 2006.201.09:19:34.88#ibcon#end of sib2, iclass 6, count 0 2006.201.09:19:34.88#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:19:34.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:19:34.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:19:34.88#ibcon#*before write, iclass 6, count 0 2006.201.09:19:34.88#ibcon#enter sib2, iclass 6, count 0 2006.201.09:19:34.88#ibcon#flushed, iclass 6, count 0 2006.201.09:19:34.88#ibcon#about to write, iclass 6, count 0 2006.201.09:19:34.88#ibcon#wrote, iclass 6, count 0 2006.201.09:19:34.88#ibcon#about to read 3, iclass 6, count 0 2006.201.09:19:34.92#ibcon#read 3, iclass 6, count 0 2006.201.09:19:34.92#ibcon#about to read 4, iclass 6, count 0 2006.201.09:19:34.92#ibcon#read 4, iclass 6, count 0 2006.201.09:19:34.92#ibcon#about to read 5, iclass 6, count 0 2006.201.09:19:34.92#ibcon#read 5, iclass 6, count 0 2006.201.09:19:34.92#ibcon#about to read 6, iclass 6, count 0 2006.201.09:19:34.92#ibcon#read 6, iclass 6, count 0 2006.201.09:19:34.92#ibcon#end of sib2, iclass 6, count 0 2006.201.09:19:34.92#ibcon#*after write, iclass 6, count 0 2006.201.09:19:34.92#ibcon#*before return 0, iclass 6, count 0 2006.201.09:19:34.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:34.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:19:34.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:19:34.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:19:34.92$vck44/vb=2,5 2006.201.09:19:34.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.09:19:34.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.09:19:34.92#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:34.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:34.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:34.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:34.98#ibcon#enter wrdev, iclass 10, count 2 2006.201.09:19:34.98#ibcon#first serial, iclass 10, count 2 2006.201.09:19:34.98#ibcon#enter sib2, iclass 10, count 2 2006.201.09:19:34.98#ibcon#flushed, iclass 10, count 2 2006.201.09:19:34.98#ibcon#about to write, iclass 10, count 2 2006.201.09:19:34.98#ibcon#wrote, iclass 10, count 2 2006.201.09:19:34.98#ibcon#about to read 3, iclass 10, count 2 2006.201.09:19:35.00#ibcon#read 3, iclass 10, count 2 2006.201.09:19:35.00#ibcon#about to read 4, iclass 10, count 2 2006.201.09:19:35.00#ibcon#read 4, iclass 10, count 2 2006.201.09:19:35.00#ibcon#about to read 5, iclass 10, count 2 2006.201.09:19:35.00#ibcon#read 5, iclass 10, count 2 2006.201.09:19:35.00#ibcon#about to read 6, iclass 10, count 2 2006.201.09:19:35.00#ibcon#read 6, iclass 10, count 2 2006.201.09:19:35.00#ibcon#end of sib2, iclass 10, count 2 2006.201.09:19:35.00#ibcon#*mode == 0, iclass 10, count 2 2006.201.09:19:35.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.09:19:35.00#ibcon#[27=AT02-05\r\n] 2006.201.09:19:35.00#ibcon#*before write, iclass 10, count 2 2006.201.09:19:35.00#ibcon#enter sib2, iclass 10, count 2 2006.201.09:19:35.00#ibcon#flushed, iclass 10, count 2 2006.201.09:19:35.00#ibcon#about to write, iclass 10, count 2 2006.201.09:19:35.00#ibcon#wrote, iclass 10, count 2 2006.201.09:19:35.00#ibcon#about to read 3, iclass 10, count 2 2006.201.09:19:35.03#ibcon#read 3, iclass 10, count 2 2006.201.09:19:35.03#ibcon#about to read 4, iclass 10, count 2 2006.201.09:19:35.03#ibcon#read 4, iclass 10, count 2 2006.201.09:19:35.03#ibcon#about to read 5, iclass 10, count 2 2006.201.09:19:35.03#ibcon#read 5, iclass 10, count 2 2006.201.09:19:35.03#ibcon#about to read 6, iclass 10, count 2 2006.201.09:19:35.03#ibcon#read 6, iclass 10, count 2 2006.201.09:19:35.03#ibcon#end of sib2, iclass 10, count 2 2006.201.09:19:35.03#ibcon#*after write, iclass 10, count 2 2006.201.09:19:35.03#ibcon#*before return 0, iclass 10, count 2 2006.201.09:19:35.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:35.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:19:35.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.09:19:35.03#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:35.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:35.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:35.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:35.15#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:19:35.15#ibcon#first serial, iclass 10, count 0 2006.201.09:19:35.15#ibcon#enter sib2, iclass 10, count 0 2006.201.09:19:35.15#ibcon#flushed, iclass 10, count 0 2006.201.09:19:35.15#ibcon#about to write, iclass 10, count 0 2006.201.09:19:35.15#ibcon#wrote, iclass 10, count 0 2006.201.09:19:35.15#ibcon#about to read 3, iclass 10, count 0 2006.201.09:19:35.17#ibcon#read 3, iclass 10, count 0 2006.201.09:19:35.17#ibcon#about to read 4, iclass 10, count 0 2006.201.09:19:35.17#ibcon#read 4, iclass 10, count 0 2006.201.09:19:35.17#ibcon#about to read 5, iclass 10, count 0 2006.201.09:19:35.17#ibcon#read 5, iclass 10, count 0 2006.201.09:19:35.17#ibcon#about to read 6, iclass 10, count 0 2006.201.09:19:35.17#ibcon#read 6, iclass 10, count 0 2006.201.09:19:35.17#ibcon#end of sib2, iclass 10, count 0 2006.201.09:19:35.17#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:19:35.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:19:35.17#ibcon#[27=USB\r\n] 2006.201.09:19:35.17#ibcon#*before write, iclass 10, count 0 2006.201.09:19:35.17#ibcon#enter sib2, iclass 10, count 0 2006.201.09:19:35.17#ibcon#flushed, iclass 10, count 0 2006.201.09:19:35.17#ibcon#about to write, iclass 10, count 0 2006.201.09:19:35.17#ibcon#wrote, iclass 10, count 0 2006.201.09:19:35.17#ibcon#about to read 3, iclass 10, count 0 2006.201.09:19:35.20#ibcon#read 3, iclass 10, count 0 2006.201.09:19:35.20#ibcon#about to read 4, iclass 10, count 0 2006.201.09:19:35.20#ibcon#read 4, iclass 10, count 0 2006.201.09:19:35.20#ibcon#about to read 5, iclass 10, count 0 2006.201.09:19:35.20#ibcon#read 5, iclass 10, count 0 2006.201.09:19:35.20#ibcon#about to read 6, iclass 10, count 0 2006.201.09:19:35.20#ibcon#read 6, iclass 10, count 0 2006.201.09:19:35.20#ibcon#end of sib2, iclass 10, count 0 2006.201.09:19:35.20#ibcon#*after write, iclass 10, count 0 2006.201.09:19:35.20#ibcon#*before return 0, iclass 10, count 0 2006.201.09:19:35.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:35.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:19:35.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:19:35.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:19:35.20$vck44/vblo=3,649.99 2006.201.09:19:35.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.09:19:35.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.09:19:35.20#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:35.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:35.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:35.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:35.20#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:19:35.20#ibcon#first serial, iclass 12, count 0 2006.201.09:19:35.20#ibcon#enter sib2, iclass 12, count 0 2006.201.09:19:35.20#ibcon#flushed, iclass 12, count 0 2006.201.09:19:35.20#ibcon#about to write, iclass 12, count 0 2006.201.09:19:35.20#ibcon#wrote, iclass 12, count 0 2006.201.09:19:35.20#ibcon#about to read 3, iclass 12, count 0 2006.201.09:19:35.22#ibcon#read 3, iclass 12, count 0 2006.201.09:19:35.22#ibcon#about to read 4, iclass 12, count 0 2006.201.09:19:35.22#ibcon#read 4, iclass 12, count 0 2006.201.09:19:35.22#ibcon#about to read 5, iclass 12, count 0 2006.201.09:19:35.22#ibcon#read 5, iclass 12, count 0 2006.201.09:19:35.22#ibcon#about to read 6, iclass 12, count 0 2006.201.09:19:35.22#ibcon#read 6, iclass 12, count 0 2006.201.09:19:35.22#ibcon#end of sib2, iclass 12, count 0 2006.201.09:19:35.22#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:19:35.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:19:35.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:19:35.22#ibcon#*before write, iclass 12, count 0 2006.201.09:19:35.22#ibcon#enter sib2, iclass 12, count 0 2006.201.09:19:35.22#ibcon#flushed, iclass 12, count 0 2006.201.09:19:35.22#ibcon#about to write, iclass 12, count 0 2006.201.09:19:35.22#ibcon#wrote, iclass 12, count 0 2006.201.09:19:35.22#ibcon#about to read 3, iclass 12, count 0 2006.201.09:19:35.26#ibcon#read 3, iclass 12, count 0 2006.201.09:19:35.26#ibcon#about to read 4, iclass 12, count 0 2006.201.09:19:35.26#ibcon#read 4, iclass 12, count 0 2006.201.09:19:35.26#ibcon#about to read 5, iclass 12, count 0 2006.201.09:19:35.26#ibcon#read 5, iclass 12, count 0 2006.201.09:19:35.26#ibcon#about to read 6, iclass 12, count 0 2006.201.09:19:35.26#ibcon#read 6, iclass 12, count 0 2006.201.09:19:35.26#ibcon#end of sib2, iclass 12, count 0 2006.201.09:19:35.26#ibcon#*after write, iclass 12, count 0 2006.201.09:19:35.26#ibcon#*before return 0, iclass 12, count 0 2006.201.09:19:35.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:35.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:19:35.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:19:35.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:19:35.26$vck44/vb=3,4 2006.201.09:19:35.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.09:19:35.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.09:19:35.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:35.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:35.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:35.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:35.32#ibcon#enter wrdev, iclass 14, count 2 2006.201.09:19:35.32#ibcon#first serial, iclass 14, count 2 2006.201.09:19:35.32#ibcon#enter sib2, iclass 14, count 2 2006.201.09:19:35.32#ibcon#flushed, iclass 14, count 2 2006.201.09:19:35.32#ibcon#about to write, iclass 14, count 2 2006.201.09:19:35.32#ibcon#wrote, iclass 14, count 2 2006.201.09:19:35.32#ibcon#about to read 3, iclass 14, count 2 2006.201.09:19:35.34#ibcon#read 3, iclass 14, count 2 2006.201.09:19:35.34#ibcon#about to read 4, iclass 14, count 2 2006.201.09:19:35.34#ibcon#read 4, iclass 14, count 2 2006.201.09:19:35.34#ibcon#about to read 5, iclass 14, count 2 2006.201.09:19:35.34#ibcon#read 5, iclass 14, count 2 2006.201.09:19:35.34#ibcon#about to read 6, iclass 14, count 2 2006.201.09:19:35.34#ibcon#read 6, iclass 14, count 2 2006.201.09:19:35.34#ibcon#end of sib2, iclass 14, count 2 2006.201.09:19:35.34#ibcon#*mode == 0, iclass 14, count 2 2006.201.09:19:35.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.09:19:35.34#ibcon#[27=AT03-04\r\n] 2006.201.09:19:35.34#ibcon#*before write, iclass 14, count 2 2006.201.09:19:35.34#ibcon#enter sib2, iclass 14, count 2 2006.201.09:19:35.34#ibcon#flushed, iclass 14, count 2 2006.201.09:19:35.34#ibcon#about to write, iclass 14, count 2 2006.201.09:19:35.34#ibcon#wrote, iclass 14, count 2 2006.201.09:19:35.34#ibcon#about to read 3, iclass 14, count 2 2006.201.09:19:35.37#ibcon#read 3, iclass 14, count 2 2006.201.09:19:35.37#ibcon#about to read 4, iclass 14, count 2 2006.201.09:19:35.37#ibcon#read 4, iclass 14, count 2 2006.201.09:19:35.37#ibcon#about to read 5, iclass 14, count 2 2006.201.09:19:35.37#ibcon#read 5, iclass 14, count 2 2006.201.09:19:35.37#ibcon#about to read 6, iclass 14, count 2 2006.201.09:19:35.37#ibcon#read 6, iclass 14, count 2 2006.201.09:19:35.37#ibcon#end of sib2, iclass 14, count 2 2006.201.09:19:35.37#ibcon#*after write, iclass 14, count 2 2006.201.09:19:35.37#ibcon#*before return 0, iclass 14, count 2 2006.201.09:19:35.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:35.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:19:35.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.09:19:35.37#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:35.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:35.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:35.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:35.49#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:19:35.49#ibcon#first serial, iclass 14, count 0 2006.201.09:19:35.49#ibcon#enter sib2, iclass 14, count 0 2006.201.09:19:35.49#ibcon#flushed, iclass 14, count 0 2006.201.09:19:35.49#ibcon#about to write, iclass 14, count 0 2006.201.09:19:35.49#ibcon#wrote, iclass 14, count 0 2006.201.09:19:35.49#ibcon#about to read 3, iclass 14, count 0 2006.201.09:19:35.51#ibcon#read 3, iclass 14, count 0 2006.201.09:19:35.51#ibcon#about to read 4, iclass 14, count 0 2006.201.09:19:35.51#ibcon#read 4, iclass 14, count 0 2006.201.09:19:35.51#ibcon#about to read 5, iclass 14, count 0 2006.201.09:19:35.51#ibcon#read 5, iclass 14, count 0 2006.201.09:19:35.51#ibcon#about to read 6, iclass 14, count 0 2006.201.09:19:35.51#ibcon#read 6, iclass 14, count 0 2006.201.09:19:35.51#ibcon#end of sib2, iclass 14, count 0 2006.201.09:19:35.51#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:19:35.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:19:35.51#ibcon#[27=USB\r\n] 2006.201.09:19:35.51#ibcon#*before write, iclass 14, count 0 2006.201.09:19:35.51#ibcon#enter sib2, iclass 14, count 0 2006.201.09:19:35.51#ibcon#flushed, iclass 14, count 0 2006.201.09:19:35.51#ibcon#about to write, iclass 14, count 0 2006.201.09:19:35.51#ibcon#wrote, iclass 14, count 0 2006.201.09:19:35.51#ibcon#about to read 3, iclass 14, count 0 2006.201.09:19:35.54#ibcon#read 3, iclass 14, count 0 2006.201.09:19:35.54#ibcon#about to read 4, iclass 14, count 0 2006.201.09:19:35.54#ibcon#read 4, iclass 14, count 0 2006.201.09:19:35.54#ibcon#about to read 5, iclass 14, count 0 2006.201.09:19:35.54#ibcon#read 5, iclass 14, count 0 2006.201.09:19:35.54#ibcon#about to read 6, iclass 14, count 0 2006.201.09:19:35.54#ibcon#read 6, iclass 14, count 0 2006.201.09:19:35.54#ibcon#end of sib2, iclass 14, count 0 2006.201.09:19:35.54#ibcon#*after write, iclass 14, count 0 2006.201.09:19:35.54#ibcon#*before return 0, iclass 14, count 0 2006.201.09:19:35.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:35.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:19:35.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:19:35.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:19:35.54$vck44/vblo=4,679.99 2006.201.09:19:35.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.09:19:35.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.09:19:35.54#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:35.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:35.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:35.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:35.54#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:19:35.54#ibcon#first serial, iclass 16, count 0 2006.201.09:19:35.54#ibcon#enter sib2, iclass 16, count 0 2006.201.09:19:35.54#ibcon#flushed, iclass 16, count 0 2006.201.09:19:35.54#ibcon#about to write, iclass 16, count 0 2006.201.09:19:35.54#ibcon#wrote, iclass 16, count 0 2006.201.09:19:35.54#ibcon#about to read 3, iclass 16, count 0 2006.201.09:19:35.56#ibcon#read 3, iclass 16, count 0 2006.201.09:19:35.56#ibcon#about to read 4, iclass 16, count 0 2006.201.09:19:35.56#ibcon#read 4, iclass 16, count 0 2006.201.09:19:35.56#ibcon#about to read 5, iclass 16, count 0 2006.201.09:19:35.56#ibcon#read 5, iclass 16, count 0 2006.201.09:19:35.56#ibcon#about to read 6, iclass 16, count 0 2006.201.09:19:35.56#ibcon#read 6, iclass 16, count 0 2006.201.09:19:35.56#ibcon#end of sib2, iclass 16, count 0 2006.201.09:19:35.56#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:19:35.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:19:35.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:19:35.56#ibcon#*before write, iclass 16, count 0 2006.201.09:19:35.56#ibcon#enter sib2, iclass 16, count 0 2006.201.09:19:35.56#ibcon#flushed, iclass 16, count 0 2006.201.09:19:35.56#ibcon#about to write, iclass 16, count 0 2006.201.09:19:35.56#ibcon#wrote, iclass 16, count 0 2006.201.09:19:35.56#ibcon#about to read 3, iclass 16, count 0 2006.201.09:19:35.61#ibcon#read 3, iclass 16, count 0 2006.201.09:19:35.61#ibcon#about to read 4, iclass 16, count 0 2006.201.09:19:35.61#ibcon#read 4, iclass 16, count 0 2006.201.09:19:35.61#ibcon#about to read 5, iclass 16, count 0 2006.201.09:19:35.61#ibcon#read 5, iclass 16, count 0 2006.201.09:19:35.61#ibcon#about to read 6, iclass 16, count 0 2006.201.09:19:35.61#ibcon#read 6, iclass 16, count 0 2006.201.09:19:35.61#ibcon#end of sib2, iclass 16, count 0 2006.201.09:19:35.61#ibcon#*after write, iclass 16, count 0 2006.201.09:19:35.61#ibcon#*before return 0, iclass 16, count 0 2006.201.09:19:35.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:35.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:19:35.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:19:35.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:19:35.61$vck44/vb=4,5 2006.201.09:19:35.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.09:19:35.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.09:19:35.61#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:35.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:35.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:35.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:35.66#ibcon#enter wrdev, iclass 18, count 2 2006.201.09:19:35.66#ibcon#first serial, iclass 18, count 2 2006.201.09:19:35.66#ibcon#enter sib2, iclass 18, count 2 2006.201.09:19:35.66#ibcon#flushed, iclass 18, count 2 2006.201.09:19:35.66#ibcon#about to write, iclass 18, count 2 2006.201.09:19:35.66#ibcon#wrote, iclass 18, count 2 2006.201.09:19:35.66#ibcon#about to read 3, iclass 18, count 2 2006.201.09:19:35.68#ibcon#read 3, iclass 18, count 2 2006.201.09:19:35.68#ibcon#about to read 4, iclass 18, count 2 2006.201.09:19:35.68#ibcon#read 4, iclass 18, count 2 2006.201.09:19:35.68#ibcon#about to read 5, iclass 18, count 2 2006.201.09:19:35.68#ibcon#read 5, iclass 18, count 2 2006.201.09:19:35.68#ibcon#about to read 6, iclass 18, count 2 2006.201.09:19:35.68#ibcon#read 6, iclass 18, count 2 2006.201.09:19:35.68#ibcon#end of sib2, iclass 18, count 2 2006.201.09:19:35.68#ibcon#*mode == 0, iclass 18, count 2 2006.201.09:19:35.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.09:19:35.68#ibcon#[27=AT04-05\r\n] 2006.201.09:19:35.68#ibcon#*before write, iclass 18, count 2 2006.201.09:19:35.68#ibcon#enter sib2, iclass 18, count 2 2006.201.09:19:35.68#ibcon#flushed, iclass 18, count 2 2006.201.09:19:35.68#ibcon#about to write, iclass 18, count 2 2006.201.09:19:35.68#ibcon#wrote, iclass 18, count 2 2006.201.09:19:35.68#ibcon#about to read 3, iclass 18, count 2 2006.201.09:19:35.71#ibcon#read 3, iclass 18, count 2 2006.201.09:19:35.71#ibcon#about to read 4, iclass 18, count 2 2006.201.09:19:35.71#ibcon#read 4, iclass 18, count 2 2006.201.09:19:35.71#ibcon#about to read 5, iclass 18, count 2 2006.201.09:19:35.71#ibcon#read 5, iclass 18, count 2 2006.201.09:19:35.71#ibcon#about to read 6, iclass 18, count 2 2006.201.09:19:35.71#ibcon#read 6, iclass 18, count 2 2006.201.09:19:35.71#ibcon#end of sib2, iclass 18, count 2 2006.201.09:19:35.71#ibcon#*after write, iclass 18, count 2 2006.201.09:19:35.71#ibcon#*before return 0, iclass 18, count 2 2006.201.09:19:35.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:35.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:19:35.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.09:19:35.71#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:35.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:35.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:35.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:35.83#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:19:35.83#ibcon#first serial, iclass 18, count 0 2006.201.09:19:35.83#ibcon#enter sib2, iclass 18, count 0 2006.201.09:19:35.83#ibcon#flushed, iclass 18, count 0 2006.201.09:19:35.83#ibcon#about to write, iclass 18, count 0 2006.201.09:19:35.83#ibcon#wrote, iclass 18, count 0 2006.201.09:19:35.83#ibcon#about to read 3, iclass 18, count 0 2006.201.09:19:35.85#ibcon#read 3, iclass 18, count 0 2006.201.09:19:35.85#ibcon#about to read 4, iclass 18, count 0 2006.201.09:19:35.85#ibcon#read 4, iclass 18, count 0 2006.201.09:19:35.85#ibcon#about to read 5, iclass 18, count 0 2006.201.09:19:35.85#ibcon#read 5, iclass 18, count 0 2006.201.09:19:35.85#ibcon#about to read 6, iclass 18, count 0 2006.201.09:19:35.85#ibcon#read 6, iclass 18, count 0 2006.201.09:19:35.85#ibcon#end of sib2, iclass 18, count 0 2006.201.09:19:35.85#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:19:35.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:19:35.85#ibcon#[27=USB\r\n] 2006.201.09:19:35.85#ibcon#*before write, iclass 18, count 0 2006.201.09:19:35.85#ibcon#enter sib2, iclass 18, count 0 2006.201.09:19:35.85#ibcon#flushed, iclass 18, count 0 2006.201.09:19:35.85#ibcon#about to write, iclass 18, count 0 2006.201.09:19:35.85#ibcon#wrote, iclass 18, count 0 2006.201.09:19:35.85#ibcon#about to read 3, iclass 18, count 0 2006.201.09:19:35.88#ibcon#read 3, iclass 18, count 0 2006.201.09:19:35.88#ibcon#about to read 4, iclass 18, count 0 2006.201.09:19:35.88#ibcon#read 4, iclass 18, count 0 2006.201.09:19:35.88#ibcon#about to read 5, iclass 18, count 0 2006.201.09:19:35.88#ibcon#read 5, iclass 18, count 0 2006.201.09:19:35.88#ibcon#about to read 6, iclass 18, count 0 2006.201.09:19:35.88#ibcon#read 6, iclass 18, count 0 2006.201.09:19:35.88#ibcon#end of sib2, iclass 18, count 0 2006.201.09:19:35.88#ibcon#*after write, iclass 18, count 0 2006.201.09:19:35.88#ibcon#*before return 0, iclass 18, count 0 2006.201.09:19:35.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:35.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:19:35.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:19:35.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:19:35.88$vck44/vblo=5,709.99 2006.201.09:19:35.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.09:19:35.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.09:19:35.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:35.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:35.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:35.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:35.88#ibcon#enter wrdev, iclass 20, count 0 2006.201.09:19:35.88#ibcon#first serial, iclass 20, count 0 2006.201.09:19:35.88#ibcon#enter sib2, iclass 20, count 0 2006.201.09:19:35.88#ibcon#flushed, iclass 20, count 0 2006.201.09:19:35.88#ibcon#about to write, iclass 20, count 0 2006.201.09:19:35.88#ibcon#wrote, iclass 20, count 0 2006.201.09:19:35.88#ibcon#about to read 3, iclass 20, count 0 2006.201.09:19:35.90#ibcon#read 3, iclass 20, count 0 2006.201.09:19:35.90#ibcon#about to read 4, iclass 20, count 0 2006.201.09:19:35.90#ibcon#read 4, iclass 20, count 0 2006.201.09:19:35.90#ibcon#about to read 5, iclass 20, count 0 2006.201.09:19:35.90#ibcon#read 5, iclass 20, count 0 2006.201.09:19:35.90#ibcon#about to read 6, iclass 20, count 0 2006.201.09:19:35.90#ibcon#read 6, iclass 20, count 0 2006.201.09:19:35.90#ibcon#end of sib2, iclass 20, count 0 2006.201.09:19:35.90#ibcon#*mode == 0, iclass 20, count 0 2006.201.09:19:35.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.09:19:35.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:19:35.90#ibcon#*before write, iclass 20, count 0 2006.201.09:19:35.90#ibcon#enter sib2, iclass 20, count 0 2006.201.09:19:35.90#ibcon#flushed, iclass 20, count 0 2006.201.09:19:35.90#ibcon#about to write, iclass 20, count 0 2006.201.09:19:35.90#ibcon#wrote, iclass 20, count 0 2006.201.09:19:35.90#ibcon#about to read 3, iclass 20, count 0 2006.201.09:19:35.94#ibcon#read 3, iclass 20, count 0 2006.201.09:19:35.94#ibcon#about to read 4, iclass 20, count 0 2006.201.09:19:35.94#ibcon#read 4, iclass 20, count 0 2006.201.09:19:35.94#ibcon#about to read 5, iclass 20, count 0 2006.201.09:19:35.94#ibcon#read 5, iclass 20, count 0 2006.201.09:19:35.94#ibcon#about to read 6, iclass 20, count 0 2006.201.09:19:35.94#ibcon#read 6, iclass 20, count 0 2006.201.09:19:35.94#ibcon#end of sib2, iclass 20, count 0 2006.201.09:19:35.94#ibcon#*after write, iclass 20, count 0 2006.201.09:19:35.94#ibcon#*before return 0, iclass 20, count 0 2006.201.09:19:35.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:35.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:19:35.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.09:19:35.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.09:19:35.94$vck44/vb=5,4 2006.201.09:19:35.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.09:19:35.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.09:19:35.94#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:35.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:36.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:36.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:36.00#ibcon#enter wrdev, iclass 22, count 2 2006.201.09:19:36.00#ibcon#first serial, iclass 22, count 2 2006.201.09:19:36.00#ibcon#enter sib2, iclass 22, count 2 2006.201.09:19:36.00#ibcon#flushed, iclass 22, count 2 2006.201.09:19:36.00#ibcon#about to write, iclass 22, count 2 2006.201.09:19:36.00#ibcon#wrote, iclass 22, count 2 2006.201.09:19:36.00#ibcon#about to read 3, iclass 22, count 2 2006.201.09:19:36.02#ibcon#read 3, iclass 22, count 2 2006.201.09:19:36.02#ibcon#about to read 4, iclass 22, count 2 2006.201.09:19:36.02#ibcon#read 4, iclass 22, count 2 2006.201.09:19:36.02#ibcon#about to read 5, iclass 22, count 2 2006.201.09:19:36.02#ibcon#read 5, iclass 22, count 2 2006.201.09:19:36.02#ibcon#about to read 6, iclass 22, count 2 2006.201.09:19:36.02#ibcon#read 6, iclass 22, count 2 2006.201.09:19:36.02#ibcon#end of sib2, iclass 22, count 2 2006.201.09:19:36.02#ibcon#*mode == 0, iclass 22, count 2 2006.201.09:19:36.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.09:19:36.02#ibcon#[27=AT05-04\r\n] 2006.201.09:19:36.02#ibcon#*before write, iclass 22, count 2 2006.201.09:19:36.02#ibcon#enter sib2, iclass 22, count 2 2006.201.09:19:36.02#ibcon#flushed, iclass 22, count 2 2006.201.09:19:36.02#ibcon#about to write, iclass 22, count 2 2006.201.09:19:36.02#ibcon#wrote, iclass 22, count 2 2006.201.09:19:36.02#ibcon#about to read 3, iclass 22, count 2 2006.201.09:19:36.05#ibcon#read 3, iclass 22, count 2 2006.201.09:19:36.05#ibcon#about to read 4, iclass 22, count 2 2006.201.09:19:36.05#ibcon#read 4, iclass 22, count 2 2006.201.09:19:36.05#ibcon#about to read 5, iclass 22, count 2 2006.201.09:19:36.05#ibcon#read 5, iclass 22, count 2 2006.201.09:19:36.05#ibcon#about to read 6, iclass 22, count 2 2006.201.09:19:36.05#ibcon#read 6, iclass 22, count 2 2006.201.09:19:36.05#ibcon#end of sib2, iclass 22, count 2 2006.201.09:19:36.05#ibcon#*after write, iclass 22, count 2 2006.201.09:19:36.05#ibcon#*before return 0, iclass 22, count 2 2006.201.09:19:36.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:36.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:19:36.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.09:19:36.05#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:36.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:36.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:36.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:36.17#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:19:36.17#ibcon#first serial, iclass 22, count 0 2006.201.09:19:36.17#ibcon#enter sib2, iclass 22, count 0 2006.201.09:19:36.17#ibcon#flushed, iclass 22, count 0 2006.201.09:19:36.17#ibcon#about to write, iclass 22, count 0 2006.201.09:19:36.17#ibcon#wrote, iclass 22, count 0 2006.201.09:19:36.17#ibcon#about to read 3, iclass 22, count 0 2006.201.09:19:36.19#ibcon#read 3, iclass 22, count 0 2006.201.09:19:36.19#ibcon#about to read 4, iclass 22, count 0 2006.201.09:19:36.19#ibcon#read 4, iclass 22, count 0 2006.201.09:19:36.19#ibcon#about to read 5, iclass 22, count 0 2006.201.09:19:36.19#ibcon#read 5, iclass 22, count 0 2006.201.09:19:36.19#ibcon#about to read 6, iclass 22, count 0 2006.201.09:19:36.19#ibcon#read 6, iclass 22, count 0 2006.201.09:19:36.19#ibcon#end of sib2, iclass 22, count 0 2006.201.09:19:36.19#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:19:36.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:19:36.19#ibcon#[27=USB\r\n] 2006.201.09:19:36.19#ibcon#*before write, iclass 22, count 0 2006.201.09:19:36.19#ibcon#enter sib2, iclass 22, count 0 2006.201.09:19:36.19#ibcon#flushed, iclass 22, count 0 2006.201.09:19:36.19#ibcon#about to write, iclass 22, count 0 2006.201.09:19:36.19#ibcon#wrote, iclass 22, count 0 2006.201.09:19:36.19#ibcon#about to read 3, iclass 22, count 0 2006.201.09:19:36.22#ibcon#read 3, iclass 22, count 0 2006.201.09:19:36.22#ibcon#about to read 4, iclass 22, count 0 2006.201.09:19:36.22#ibcon#read 4, iclass 22, count 0 2006.201.09:19:36.22#ibcon#about to read 5, iclass 22, count 0 2006.201.09:19:36.22#ibcon#read 5, iclass 22, count 0 2006.201.09:19:36.22#ibcon#about to read 6, iclass 22, count 0 2006.201.09:19:36.22#ibcon#read 6, iclass 22, count 0 2006.201.09:19:36.22#ibcon#end of sib2, iclass 22, count 0 2006.201.09:19:36.22#ibcon#*after write, iclass 22, count 0 2006.201.09:19:36.22#ibcon#*before return 0, iclass 22, count 0 2006.201.09:19:36.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:36.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:19:36.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:19:36.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:19:36.22$vck44/vblo=6,719.99 2006.201.09:19:36.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.09:19:36.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.09:19:36.22#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:36.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:36.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:36.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:36.22#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:19:36.22#ibcon#first serial, iclass 24, count 0 2006.201.09:19:36.22#ibcon#enter sib2, iclass 24, count 0 2006.201.09:19:36.22#ibcon#flushed, iclass 24, count 0 2006.201.09:19:36.22#ibcon#about to write, iclass 24, count 0 2006.201.09:19:36.22#ibcon#wrote, iclass 24, count 0 2006.201.09:19:36.22#ibcon#about to read 3, iclass 24, count 0 2006.201.09:19:36.24#ibcon#read 3, iclass 24, count 0 2006.201.09:19:36.24#ibcon#about to read 4, iclass 24, count 0 2006.201.09:19:36.24#ibcon#read 4, iclass 24, count 0 2006.201.09:19:36.24#ibcon#about to read 5, iclass 24, count 0 2006.201.09:19:36.24#ibcon#read 5, iclass 24, count 0 2006.201.09:19:36.24#ibcon#about to read 6, iclass 24, count 0 2006.201.09:19:36.24#ibcon#read 6, iclass 24, count 0 2006.201.09:19:36.24#ibcon#end of sib2, iclass 24, count 0 2006.201.09:19:36.24#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:19:36.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:19:36.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:19:36.24#ibcon#*before write, iclass 24, count 0 2006.201.09:19:36.24#ibcon#enter sib2, iclass 24, count 0 2006.201.09:19:36.24#ibcon#flushed, iclass 24, count 0 2006.201.09:19:36.24#ibcon#about to write, iclass 24, count 0 2006.201.09:19:36.24#ibcon#wrote, iclass 24, count 0 2006.201.09:19:36.24#ibcon#about to read 3, iclass 24, count 0 2006.201.09:19:36.28#ibcon#read 3, iclass 24, count 0 2006.201.09:19:36.28#ibcon#about to read 4, iclass 24, count 0 2006.201.09:19:36.28#ibcon#read 4, iclass 24, count 0 2006.201.09:19:36.28#ibcon#about to read 5, iclass 24, count 0 2006.201.09:19:36.28#ibcon#read 5, iclass 24, count 0 2006.201.09:19:36.28#ibcon#about to read 6, iclass 24, count 0 2006.201.09:19:36.28#ibcon#read 6, iclass 24, count 0 2006.201.09:19:36.28#ibcon#end of sib2, iclass 24, count 0 2006.201.09:19:36.28#ibcon#*after write, iclass 24, count 0 2006.201.09:19:36.28#ibcon#*before return 0, iclass 24, count 0 2006.201.09:19:36.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:36.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:19:36.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:19:36.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:19:36.28$vck44/vb=6,4 2006.201.09:19:36.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.09:19:36.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.09:19:36.28#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:36.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:36.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:36.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:36.34#ibcon#enter wrdev, iclass 26, count 2 2006.201.09:19:36.34#ibcon#first serial, iclass 26, count 2 2006.201.09:19:36.34#ibcon#enter sib2, iclass 26, count 2 2006.201.09:19:36.34#ibcon#flushed, iclass 26, count 2 2006.201.09:19:36.34#ibcon#about to write, iclass 26, count 2 2006.201.09:19:36.34#ibcon#wrote, iclass 26, count 2 2006.201.09:19:36.34#ibcon#about to read 3, iclass 26, count 2 2006.201.09:19:36.36#ibcon#read 3, iclass 26, count 2 2006.201.09:19:36.36#ibcon#about to read 4, iclass 26, count 2 2006.201.09:19:36.36#ibcon#read 4, iclass 26, count 2 2006.201.09:19:36.36#ibcon#about to read 5, iclass 26, count 2 2006.201.09:19:36.36#ibcon#read 5, iclass 26, count 2 2006.201.09:19:36.36#ibcon#about to read 6, iclass 26, count 2 2006.201.09:19:36.36#ibcon#read 6, iclass 26, count 2 2006.201.09:19:36.36#ibcon#end of sib2, iclass 26, count 2 2006.201.09:19:36.36#ibcon#*mode == 0, iclass 26, count 2 2006.201.09:19:36.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.09:19:36.36#ibcon#[27=AT06-04\r\n] 2006.201.09:19:36.36#ibcon#*before write, iclass 26, count 2 2006.201.09:19:36.36#ibcon#enter sib2, iclass 26, count 2 2006.201.09:19:36.36#ibcon#flushed, iclass 26, count 2 2006.201.09:19:36.36#ibcon#about to write, iclass 26, count 2 2006.201.09:19:36.36#ibcon#wrote, iclass 26, count 2 2006.201.09:19:36.36#ibcon#about to read 3, iclass 26, count 2 2006.201.09:19:36.39#ibcon#read 3, iclass 26, count 2 2006.201.09:19:36.39#ibcon#about to read 4, iclass 26, count 2 2006.201.09:19:36.39#ibcon#read 4, iclass 26, count 2 2006.201.09:19:36.39#ibcon#about to read 5, iclass 26, count 2 2006.201.09:19:36.39#ibcon#read 5, iclass 26, count 2 2006.201.09:19:36.39#ibcon#about to read 6, iclass 26, count 2 2006.201.09:19:36.39#ibcon#read 6, iclass 26, count 2 2006.201.09:19:36.39#ibcon#end of sib2, iclass 26, count 2 2006.201.09:19:36.39#ibcon#*after write, iclass 26, count 2 2006.201.09:19:36.39#ibcon#*before return 0, iclass 26, count 2 2006.201.09:19:36.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:36.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:19:36.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.09:19:36.39#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:36.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:36.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:36.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:36.51#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:19:36.51#ibcon#first serial, iclass 26, count 0 2006.201.09:19:36.51#ibcon#enter sib2, iclass 26, count 0 2006.201.09:19:36.51#ibcon#flushed, iclass 26, count 0 2006.201.09:19:36.51#ibcon#about to write, iclass 26, count 0 2006.201.09:19:36.51#ibcon#wrote, iclass 26, count 0 2006.201.09:19:36.51#ibcon#about to read 3, iclass 26, count 0 2006.201.09:19:36.53#ibcon#read 3, iclass 26, count 0 2006.201.09:19:36.53#ibcon#about to read 4, iclass 26, count 0 2006.201.09:19:36.53#ibcon#read 4, iclass 26, count 0 2006.201.09:19:36.53#ibcon#about to read 5, iclass 26, count 0 2006.201.09:19:36.53#ibcon#read 5, iclass 26, count 0 2006.201.09:19:36.53#ibcon#about to read 6, iclass 26, count 0 2006.201.09:19:36.53#ibcon#read 6, iclass 26, count 0 2006.201.09:19:36.53#ibcon#end of sib2, iclass 26, count 0 2006.201.09:19:36.53#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:19:36.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:19:36.53#ibcon#[27=USB\r\n] 2006.201.09:19:36.53#ibcon#*before write, iclass 26, count 0 2006.201.09:19:36.53#ibcon#enter sib2, iclass 26, count 0 2006.201.09:19:36.53#ibcon#flushed, iclass 26, count 0 2006.201.09:19:36.53#ibcon#about to write, iclass 26, count 0 2006.201.09:19:36.53#ibcon#wrote, iclass 26, count 0 2006.201.09:19:36.53#ibcon#about to read 3, iclass 26, count 0 2006.201.09:19:36.56#ibcon#read 3, iclass 26, count 0 2006.201.09:19:36.56#ibcon#about to read 4, iclass 26, count 0 2006.201.09:19:36.56#ibcon#read 4, iclass 26, count 0 2006.201.09:19:36.56#ibcon#about to read 5, iclass 26, count 0 2006.201.09:19:36.56#ibcon#read 5, iclass 26, count 0 2006.201.09:19:36.56#ibcon#about to read 6, iclass 26, count 0 2006.201.09:19:36.56#ibcon#read 6, iclass 26, count 0 2006.201.09:19:36.56#ibcon#end of sib2, iclass 26, count 0 2006.201.09:19:36.56#ibcon#*after write, iclass 26, count 0 2006.201.09:19:36.56#ibcon#*before return 0, iclass 26, count 0 2006.201.09:19:36.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:36.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:19:36.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:19:36.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:19:36.56$vck44/vblo=7,734.99 2006.201.09:19:36.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.09:19:36.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.09:19:36.56#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:36.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:19:36.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:19:36.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:19:36.56#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:19:36.56#ibcon#first serial, iclass 28, count 0 2006.201.09:19:36.56#ibcon#enter sib2, iclass 28, count 0 2006.201.09:19:36.56#ibcon#flushed, iclass 28, count 0 2006.201.09:19:36.56#ibcon#about to write, iclass 28, count 0 2006.201.09:19:36.56#ibcon#wrote, iclass 28, count 0 2006.201.09:19:36.56#ibcon#about to read 3, iclass 28, count 0 2006.201.09:19:36.58#ibcon#read 3, iclass 28, count 0 2006.201.09:19:36.58#ibcon#about to read 4, iclass 28, count 0 2006.201.09:19:36.58#ibcon#read 4, iclass 28, count 0 2006.201.09:19:36.58#ibcon#about to read 5, iclass 28, count 0 2006.201.09:19:36.58#ibcon#read 5, iclass 28, count 0 2006.201.09:19:36.58#ibcon#about to read 6, iclass 28, count 0 2006.201.09:19:36.58#ibcon#read 6, iclass 28, count 0 2006.201.09:19:36.58#ibcon#end of sib2, iclass 28, count 0 2006.201.09:19:36.58#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:19:36.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:19:36.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:19:36.58#ibcon#*before write, iclass 28, count 0 2006.201.09:19:36.58#ibcon#enter sib2, iclass 28, count 0 2006.201.09:19:36.58#ibcon#flushed, iclass 28, count 0 2006.201.09:19:36.58#ibcon#about to write, iclass 28, count 0 2006.201.09:19:36.58#ibcon#wrote, iclass 28, count 0 2006.201.09:19:36.58#ibcon#about to read 3, iclass 28, count 0 2006.201.09:19:36.62#ibcon#read 3, iclass 28, count 0 2006.201.09:19:36.62#ibcon#about to read 4, iclass 28, count 0 2006.201.09:19:36.62#ibcon#read 4, iclass 28, count 0 2006.201.09:19:36.62#ibcon#about to read 5, iclass 28, count 0 2006.201.09:19:36.62#ibcon#read 5, iclass 28, count 0 2006.201.09:19:36.62#ibcon#about to read 6, iclass 28, count 0 2006.201.09:19:36.62#ibcon#read 6, iclass 28, count 0 2006.201.09:19:36.62#ibcon#end of sib2, iclass 28, count 0 2006.201.09:19:36.62#ibcon#*after write, iclass 28, count 0 2006.201.09:19:36.62#ibcon#*before return 0, iclass 28, count 0 2006.201.09:19:36.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:19:36.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:19:36.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:19:36.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:19:36.62$vck44/vb=7,4 2006.201.09:19:36.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.09:19:36.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.09:19:36.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:36.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:19:36.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:19:36.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:19:36.68#ibcon#enter wrdev, iclass 30, count 2 2006.201.09:19:36.68#ibcon#first serial, iclass 30, count 2 2006.201.09:19:36.68#ibcon#enter sib2, iclass 30, count 2 2006.201.09:19:36.68#ibcon#flushed, iclass 30, count 2 2006.201.09:19:36.68#ibcon#about to write, iclass 30, count 2 2006.201.09:19:36.68#ibcon#wrote, iclass 30, count 2 2006.201.09:19:36.68#ibcon#about to read 3, iclass 30, count 2 2006.201.09:19:36.70#ibcon#read 3, iclass 30, count 2 2006.201.09:19:36.70#ibcon#about to read 4, iclass 30, count 2 2006.201.09:19:36.70#ibcon#read 4, iclass 30, count 2 2006.201.09:19:36.70#ibcon#about to read 5, iclass 30, count 2 2006.201.09:19:36.70#ibcon#read 5, iclass 30, count 2 2006.201.09:19:36.70#ibcon#about to read 6, iclass 30, count 2 2006.201.09:19:36.70#ibcon#read 6, iclass 30, count 2 2006.201.09:19:36.70#ibcon#end of sib2, iclass 30, count 2 2006.201.09:19:36.70#ibcon#*mode == 0, iclass 30, count 2 2006.201.09:19:36.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.09:19:36.70#ibcon#[27=AT07-04\r\n] 2006.201.09:19:36.70#ibcon#*before write, iclass 30, count 2 2006.201.09:19:36.70#ibcon#enter sib2, iclass 30, count 2 2006.201.09:19:36.70#ibcon#flushed, iclass 30, count 2 2006.201.09:19:36.70#ibcon#about to write, iclass 30, count 2 2006.201.09:19:36.70#ibcon#wrote, iclass 30, count 2 2006.201.09:19:36.70#ibcon#about to read 3, iclass 30, count 2 2006.201.09:19:36.73#ibcon#read 3, iclass 30, count 2 2006.201.09:19:36.73#ibcon#about to read 4, iclass 30, count 2 2006.201.09:19:36.73#ibcon#read 4, iclass 30, count 2 2006.201.09:19:36.73#ibcon#about to read 5, iclass 30, count 2 2006.201.09:19:36.73#ibcon#read 5, iclass 30, count 2 2006.201.09:19:36.73#ibcon#about to read 6, iclass 30, count 2 2006.201.09:19:36.73#ibcon#read 6, iclass 30, count 2 2006.201.09:19:36.73#ibcon#end of sib2, iclass 30, count 2 2006.201.09:19:36.73#ibcon#*after write, iclass 30, count 2 2006.201.09:19:36.73#ibcon#*before return 0, iclass 30, count 2 2006.201.09:19:36.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:19:36.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:19:36.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.09:19:36.73#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:36.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:19:36.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:19:36.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:19:36.85#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:19:36.85#ibcon#first serial, iclass 30, count 0 2006.201.09:19:36.85#ibcon#enter sib2, iclass 30, count 0 2006.201.09:19:36.85#ibcon#flushed, iclass 30, count 0 2006.201.09:19:36.85#ibcon#about to write, iclass 30, count 0 2006.201.09:19:36.85#ibcon#wrote, iclass 30, count 0 2006.201.09:19:36.85#ibcon#about to read 3, iclass 30, count 0 2006.201.09:19:36.87#ibcon#read 3, iclass 30, count 0 2006.201.09:19:36.87#ibcon#about to read 4, iclass 30, count 0 2006.201.09:19:36.87#ibcon#read 4, iclass 30, count 0 2006.201.09:19:36.87#ibcon#about to read 5, iclass 30, count 0 2006.201.09:19:36.87#ibcon#read 5, iclass 30, count 0 2006.201.09:19:36.87#ibcon#about to read 6, iclass 30, count 0 2006.201.09:19:36.87#ibcon#read 6, iclass 30, count 0 2006.201.09:19:36.87#ibcon#end of sib2, iclass 30, count 0 2006.201.09:19:36.87#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:19:36.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:19:36.87#ibcon#[27=USB\r\n] 2006.201.09:19:36.87#ibcon#*before write, iclass 30, count 0 2006.201.09:19:36.87#ibcon#enter sib2, iclass 30, count 0 2006.201.09:19:36.87#ibcon#flushed, iclass 30, count 0 2006.201.09:19:36.87#ibcon#about to write, iclass 30, count 0 2006.201.09:19:36.87#ibcon#wrote, iclass 30, count 0 2006.201.09:19:36.87#ibcon#about to read 3, iclass 30, count 0 2006.201.09:19:36.90#ibcon#read 3, iclass 30, count 0 2006.201.09:19:36.90#ibcon#about to read 4, iclass 30, count 0 2006.201.09:19:36.90#ibcon#read 4, iclass 30, count 0 2006.201.09:19:36.90#ibcon#about to read 5, iclass 30, count 0 2006.201.09:19:36.90#ibcon#read 5, iclass 30, count 0 2006.201.09:19:36.90#ibcon#about to read 6, iclass 30, count 0 2006.201.09:19:36.90#ibcon#read 6, iclass 30, count 0 2006.201.09:19:36.90#ibcon#end of sib2, iclass 30, count 0 2006.201.09:19:36.90#ibcon#*after write, iclass 30, count 0 2006.201.09:19:36.90#ibcon#*before return 0, iclass 30, count 0 2006.201.09:19:36.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:19:36.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:19:36.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:19:36.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:19:36.90$vck44/vblo=8,744.99 2006.201.09:19:36.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.09:19:36.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.09:19:36.90#ibcon#ireg 17 cls_cnt 0 2006.201.09:19:36.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:36.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:36.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:36.90#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:19:36.90#ibcon#first serial, iclass 32, count 0 2006.201.09:19:36.90#ibcon#enter sib2, iclass 32, count 0 2006.201.09:19:36.90#ibcon#flushed, iclass 32, count 0 2006.201.09:19:36.90#ibcon#about to write, iclass 32, count 0 2006.201.09:19:36.90#ibcon#wrote, iclass 32, count 0 2006.201.09:19:36.90#ibcon#about to read 3, iclass 32, count 0 2006.201.09:19:36.92#ibcon#read 3, iclass 32, count 0 2006.201.09:19:36.92#ibcon#about to read 4, iclass 32, count 0 2006.201.09:19:36.92#ibcon#read 4, iclass 32, count 0 2006.201.09:19:36.92#ibcon#about to read 5, iclass 32, count 0 2006.201.09:19:36.92#ibcon#read 5, iclass 32, count 0 2006.201.09:19:36.92#ibcon#about to read 6, iclass 32, count 0 2006.201.09:19:36.92#ibcon#read 6, iclass 32, count 0 2006.201.09:19:36.92#ibcon#end of sib2, iclass 32, count 0 2006.201.09:19:36.92#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:19:36.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:19:36.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:19:36.92#ibcon#*before write, iclass 32, count 0 2006.201.09:19:36.92#ibcon#enter sib2, iclass 32, count 0 2006.201.09:19:36.92#ibcon#flushed, iclass 32, count 0 2006.201.09:19:36.92#ibcon#about to write, iclass 32, count 0 2006.201.09:19:36.92#ibcon#wrote, iclass 32, count 0 2006.201.09:19:36.92#ibcon#about to read 3, iclass 32, count 0 2006.201.09:19:36.96#ibcon#read 3, iclass 32, count 0 2006.201.09:19:36.96#ibcon#about to read 4, iclass 32, count 0 2006.201.09:19:36.96#ibcon#read 4, iclass 32, count 0 2006.201.09:19:36.96#ibcon#about to read 5, iclass 32, count 0 2006.201.09:19:36.96#ibcon#read 5, iclass 32, count 0 2006.201.09:19:36.96#ibcon#about to read 6, iclass 32, count 0 2006.201.09:19:36.96#ibcon#read 6, iclass 32, count 0 2006.201.09:19:36.96#ibcon#end of sib2, iclass 32, count 0 2006.201.09:19:36.96#ibcon#*after write, iclass 32, count 0 2006.201.09:19:36.96#ibcon#*before return 0, iclass 32, count 0 2006.201.09:19:36.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:36.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:19:36.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:19:36.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:19:36.96$vck44/vb=8,4 2006.201.09:19:36.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.09:19:36.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.09:19:36.96#ibcon#ireg 11 cls_cnt 2 2006.201.09:19:36.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:37.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:37.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:37.02#ibcon#enter wrdev, iclass 34, count 2 2006.201.09:19:37.02#ibcon#first serial, iclass 34, count 2 2006.201.09:19:37.02#ibcon#enter sib2, iclass 34, count 2 2006.201.09:19:37.02#ibcon#flushed, iclass 34, count 2 2006.201.09:19:37.02#ibcon#about to write, iclass 34, count 2 2006.201.09:19:37.02#ibcon#wrote, iclass 34, count 2 2006.201.09:19:37.02#ibcon#about to read 3, iclass 34, count 2 2006.201.09:19:37.04#ibcon#read 3, iclass 34, count 2 2006.201.09:19:37.04#ibcon#about to read 4, iclass 34, count 2 2006.201.09:19:37.04#ibcon#read 4, iclass 34, count 2 2006.201.09:19:37.04#ibcon#about to read 5, iclass 34, count 2 2006.201.09:19:37.04#ibcon#read 5, iclass 34, count 2 2006.201.09:19:37.04#ibcon#about to read 6, iclass 34, count 2 2006.201.09:19:37.04#ibcon#read 6, iclass 34, count 2 2006.201.09:19:37.04#ibcon#end of sib2, iclass 34, count 2 2006.201.09:19:37.04#ibcon#*mode == 0, iclass 34, count 2 2006.201.09:19:37.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.09:19:37.04#ibcon#[27=AT08-04\r\n] 2006.201.09:19:37.04#ibcon#*before write, iclass 34, count 2 2006.201.09:19:37.04#ibcon#enter sib2, iclass 34, count 2 2006.201.09:19:37.04#ibcon#flushed, iclass 34, count 2 2006.201.09:19:37.04#ibcon#about to write, iclass 34, count 2 2006.201.09:19:37.04#ibcon#wrote, iclass 34, count 2 2006.201.09:19:37.04#ibcon#about to read 3, iclass 34, count 2 2006.201.09:19:37.07#ibcon#read 3, iclass 34, count 2 2006.201.09:19:37.07#ibcon#about to read 4, iclass 34, count 2 2006.201.09:19:37.07#ibcon#read 4, iclass 34, count 2 2006.201.09:19:37.07#ibcon#about to read 5, iclass 34, count 2 2006.201.09:19:37.07#ibcon#read 5, iclass 34, count 2 2006.201.09:19:37.07#ibcon#about to read 6, iclass 34, count 2 2006.201.09:19:37.07#ibcon#read 6, iclass 34, count 2 2006.201.09:19:37.07#ibcon#end of sib2, iclass 34, count 2 2006.201.09:19:37.07#ibcon#*after write, iclass 34, count 2 2006.201.09:19:37.07#ibcon#*before return 0, iclass 34, count 2 2006.201.09:19:37.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:37.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:19:37.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.09:19:37.07#ibcon#ireg 7 cls_cnt 0 2006.201.09:19:37.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:37.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:37.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:37.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:19:37.19#ibcon#first serial, iclass 34, count 0 2006.201.09:19:37.19#ibcon#enter sib2, iclass 34, count 0 2006.201.09:19:37.19#ibcon#flushed, iclass 34, count 0 2006.201.09:19:37.19#ibcon#about to write, iclass 34, count 0 2006.201.09:19:37.19#ibcon#wrote, iclass 34, count 0 2006.201.09:19:37.19#ibcon#about to read 3, iclass 34, count 0 2006.201.09:19:37.22#ibcon#read 3, iclass 34, count 0 2006.201.09:19:37.22#ibcon#about to read 4, iclass 34, count 0 2006.201.09:19:37.22#ibcon#read 4, iclass 34, count 0 2006.201.09:19:37.22#ibcon#about to read 5, iclass 34, count 0 2006.201.09:19:37.22#ibcon#read 5, iclass 34, count 0 2006.201.09:19:37.22#ibcon#about to read 6, iclass 34, count 0 2006.201.09:19:37.22#ibcon#read 6, iclass 34, count 0 2006.201.09:19:37.22#ibcon#end of sib2, iclass 34, count 0 2006.201.09:19:37.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:19:37.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:19:37.22#ibcon#[27=USB\r\n] 2006.201.09:19:37.22#ibcon#*before write, iclass 34, count 0 2006.201.09:19:37.22#ibcon#enter sib2, iclass 34, count 0 2006.201.09:19:37.22#ibcon#flushed, iclass 34, count 0 2006.201.09:19:37.22#ibcon#about to write, iclass 34, count 0 2006.201.09:19:37.22#ibcon#wrote, iclass 34, count 0 2006.201.09:19:37.22#ibcon#about to read 3, iclass 34, count 0 2006.201.09:19:37.25#ibcon#read 3, iclass 34, count 0 2006.201.09:19:37.25#ibcon#about to read 4, iclass 34, count 0 2006.201.09:19:37.25#ibcon#read 4, iclass 34, count 0 2006.201.09:19:37.25#ibcon#about to read 5, iclass 34, count 0 2006.201.09:19:37.25#ibcon#read 5, iclass 34, count 0 2006.201.09:19:37.25#ibcon#about to read 6, iclass 34, count 0 2006.201.09:19:37.25#ibcon#read 6, iclass 34, count 0 2006.201.09:19:37.25#ibcon#end of sib2, iclass 34, count 0 2006.201.09:19:37.25#ibcon#*after write, iclass 34, count 0 2006.201.09:19:37.25#ibcon#*before return 0, iclass 34, count 0 2006.201.09:19:37.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:37.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:19:37.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:19:37.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:19:37.25$vck44/vabw=wide 2006.201.09:19:37.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.09:19:37.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.09:19:37.25#ibcon#ireg 8 cls_cnt 0 2006.201.09:19:37.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:37.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:37.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:37.25#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:19:37.25#ibcon#first serial, iclass 36, count 0 2006.201.09:19:37.25#ibcon#enter sib2, iclass 36, count 0 2006.201.09:19:37.25#ibcon#flushed, iclass 36, count 0 2006.201.09:19:37.25#ibcon#about to write, iclass 36, count 0 2006.201.09:19:37.25#ibcon#wrote, iclass 36, count 0 2006.201.09:19:37.25#ibcon#about to read 3, iclass 36, count 0 2006.201.09:19:37.27#ibcon#read 3, iclass 36, count 0 2006.201.09:19:37.27#ibcon#about to read 4, iclass 36, count 0 2006.201.09:19:37.27#ibcon#read 4, iclass 36, count 0 2006.201.09:19:37.27#ibcon#about to read 5, iclass 36, count 0 2006.201.09:19:37.27#ibcon#read 5, iclass 36, count 0 2006.201.09:19:37.27#ibcon#about to read 6, iclass 36, count 0 2006.201.09:19:37.27#ibcon#read 6, iclass 36, count 0 2006.201.09:19:37.27#ibcon#end of sib2, iclass 36, count 0 2006.201.09:19:37.27#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:19:37.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:19:37.27#ibcon#[25=BW32\r\n] 2006.201.09:19:37.27#ibcon#*before write, iclass 36, count 0 2006.201.09:19:37.27#ibcon#enter sib2, iclass 36, count 0 2006.201.09:19:37.27#ibcon#flushed, iclass 36, count 0 2006.201.09:19:37.27#ibcon#about to write, iclass 36, count 0 2006.201.09:19:37.27#ibcon#wrote, iclass 36, count 0 2006.201.09:19:37.27#ibcon#about to read 3, iclass 36, count 0 2006.201.09:19:37.30#ibcon#read 3, iclass 36, count 0 2006.201.09:19:37.30#ibcon#about to read 4, iclass 36, count 0 2006.201.09:19:37.30#ibcon#read 4, iclass 36, count 0 2006.201.09:19:37.30#ibcon#about to read 5, iclass 36, count 0 2006.201.09:19:37.30#ibcon#read 5, iclass 36, count 0 2006.201.09:19:37.30#ibcon#about to read 6, iclass 36, count 0 2006.201.09:19:37.30#ibcon#read 6, iclass 36, count 0 2006.201.09:19:37.30#ibcon#end of sib2, iclass 36, count 0 2006.201.09:19:37.30#ibcon#*after write, iclass 36, count 0 2006.201.09:19:37.30#ibcon#*before return 0, iclass 36, count 0 2006.201.09:19:37.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:37.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:19:37.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:19:37.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:19:37.30$vck44/vbbw=wide 2006.201.09:19:37.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.09:19:37.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.09:19:37.30#ibcon#ireg 8 cls_cnt 0 2006.201.09:19:37.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:19:37.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:19:37.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:19:37.37#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:19:37.37#ibcon#first serial, iclass 38, count 0 2006.201.09:19:37.37#ibcon#enter sib2, iclass 38, count 0 2006.201.09:19:37.37#ibcon#flushed, iclass 38, count 0 2006.201.09:19:37.37#ibcon#about to write, iclass 38, count 0 2006.201.09:19:37.37#ibcon#wrote, iclass 38, count 0 2006.201.09:19:37.37#ibcon#about to read 3, iclass 38, count 0 2006.201.09:19:37.39#ibcon#read 3, iclass 38, count 0 2006.201.09:19:37.39#ibcon#about to read 4, iclass 38, count 0 2006.201.09:19:37.39#ibcon#read 4, iclass 38, count 0 2006.201.09:19:37.39#ibcon#about to read 5, iclass 38, count 0 2006.201.09:19:37.39#ibcon#read 5, iclass 38, count 0 2006.201.09:19:37.39#ibcon#about to read 6, iclass 38, count 0 2006.201.09:19:37.39#ibcon#read 6, iclass 38, count 0 2006.201.09:19:37.39#ibcon#end of sib2, iclass 38, count 0 2006.201.09:19:37.39#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:19:37.39#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:19:37.39#ibcon#[27=BW32\r\n] 2006.201.09:19:37.39#ibcon#*before write, iclass 38, count 0 2006.201.09:19:37.39#ibcon#enter sib2, iclass 38, count 0 2006.201.09:19:37.39#ibcon#flushed, iclass 38, count 0 2006.201.09:19:37.39#ibcon#about to write, iclass 38, count 0 2006.201.09:19:37.39#ibcon#wrote, iclass 38, count 0 2006.201.09:19:37.39#ibcon#about to read 3, iclass 38, count 0 2006.201.09:19:37.42#ibcon#read 3, iclass 38, count 0 2006.201.09:19:37.42#ibcon#about to read 4, iclass 38, count 0 2006.201.09:19:37.42#ibcon#read 4, iclass 38, count 0 2006.201.09:19:37.42#ibcon#about to read 5, iclass 38, count 0 2006.201.09:19:37.42#ibcon#read 5, iclass 38, count 0 2006.201.09:19:37.42#ibcon#about to read 6, iclass 38, count 0 2006.201.09:19:37.42#ibcon#read 6, iclass 38, count 0 2006.201.09:19:37.42#ibcon#end of sib2, iclass 38, count 0 2006.201.09:19:37.42#ibcon#*after write, iclass 38, count 0 2006.201.09:19:37.42#ibcon#*before return 0, iclass 38, count 0 2006.201.09:19:37.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:19:37.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:19:37.42#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:19:37.42#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:19:37.42$setupk4/ifdk4 2006.201.09:19:37.42$ifdk4/lo= 2006.201.09:19:37.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:19:37.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:19:37.42$ifdk4/patch= 2006.201.09:19:37.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:19:37.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:19:37.42$setupk4/!*+20s 2006.201.09:19:43.92#abcon#<5=/05 2.6 4.9 22.74 901003.8\r\n> 2006.201.09:19:43.94#abcon#{5=INTERFACE CLEAR} 2006.201.09:19:44.00#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:19:48.14#trakl#Source acquired 2006.201.09:19:48.14#flagr#flagr/antenna,acquired 2006.201.09:19:51.89$setupk4/"tpicd 2006.201.09:19:51.89$setupk4/echo=off 2006.201.09:19:51.89$setupk4/xlog=off 2006.201.09:19:51.89:!2006.201.09:20:58 2006.201.09:20:58.00:preob 2006.201.09:20:58.14/onsource/TRACKING 2006.201.09:20:58.14:!2006.201.09:21:08 2006.201.09:21:08.00:"tape 2006.201.09:21:08.00:"st=record 2006.201.09:21:08.00:data_valid=on 2006.201.09:21:08.00:midob 2006.201.09:21:09.14/onsource/TRACKING 2006.201.09:21:09.14/wx/22.71,1003.8,90 2006.201.09:21:09.32/cable/+6.4672E-03 2006.201.09:21:10.41/va/01,08,usb,yes,31,33 2006.201.09:21:10.41/va/02,07,usb,yes,33,34 2006.201.09:21:10.41/va/03,08,usb,yes,30,31 2006.201.09:21:10.41/va/04,07,usb,yes,34,36 2006.201.09:21:10.41/va/05,04,usb,yes,30,30 2006.201.09:21:10.41/va/06,05,usb,yes,30,30 2006.201.09:21:10.41/va/07,05,usb,yes,29,30 2006.201.09:21:10.41/va/08,04,usb,yes,29,34 2006.201.09:21:10.64/valo/01,524.99,yes,locked 2006.201.09:21:10.64/valo/02,534.99,yes,locked 2006.201.09:21:10.64/valo/03,564.99,yes,locked 2006.201.09:21:10.64/valo/04,624.99,yes,locked 2006.201.09:21:10.64/valo/05,734.99,yes,locked 2006.201.09:21:10.64/valo/06,814.99,yes,locked 2006.201.09:21:10.64/valo/07,864.99,yes,locked 2006.201.09:21:10.64/valo/08,884.99,yes,locked 2006.201.09:21:11.73/vb/01,04,usb,yes,36,33 2006.201.09:21:11.73/vb/02,05,usb,yes,34,33 2006.201.09:21:11.73/vb/03,04,usb,yes,35,38 2006.201.09:21:11.73/vb/04,05,usb,yes,35,34 2006.201.09:21:11.73/vb/05,04,usb,yes,31,34 2006.201.09:21:11.73/vb/06,04,usb,yes,36,32 2006.201.09:21:11.73/vb/07,04,usb,yes,36,35 2006.201.09:21:11.73/vb/08,04,usb,yes,32,36 2006.201.09:21:11.97/vblo/01,629.99,yes,locked 2006.201.09:21:11.97/vblo/02,634.99,yes,locked 2006.201.09:21:11.97/vblo/03,649.99,yes,locked 2006.201.09:21:11.97/vblo/04,679.99,yes,locked 2006.201.09:21:11.97/vblo/05,709.99,yes,locked 2006.201.09:21:11.97/vblo/06,719.99,yes,locked 2006.201.09:21:11.97/vblo/07,734.99,yes,locked 2006.201.09:21:11.97/vblo/08,744.99,yes,locked 2006.201.09:21:12.12/vabw/8 2006.201.09:21:12.27/vbbw/8 2006.201.09:21:12.37/xfe/off,on,14.5 2006.201.09:21:12.74/ifatt/23,28,28,28 2006.201.09:21:13.05/fmout-gps/S +4.53E-07 2006.201.09:21:13.12:!2006.201.09:22:38 2006.201.09:22:38.00:data_valid=off 2006.201.09:22:38.00:"et 2006.201.09:22:38.00:!+3s 2006.201.09:22:41.02:"tape 2006.201.09:22:41.02:postob 2006.201.09:22:41.23/cable/+6.4667E-03 2006.201.09:22:41.23/wx/22.69,1003.8,90 2006.201.09:22:41.31/fmout-gps/S +4.53E-07 2006.201.09:22:41.31:scan_name=201-0929,jd0607,40 2006.201.09:22:41.31:source=1424-418,142756.30,-420619.4,2000.0,cw 2006.201.09:22:42.14#flagr#flagr/antenna,new-source 2006.201.09:22:42.14:checkk5 2006.201.09:22:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:22:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:22:43.35/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:22:43.72/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:22:44.10/chk_obsdata//k5ts1/T2010921??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.09:22:44.47/chk_obsdata//k5ts2/T2010921??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.09:22:44.83/chk_obsdata//k5ts3/T2010921??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.09:22:45.20/chk_obsdata//k5ts4/T2010921??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.09:22:45.89/k5log//k5ts1_log_newline 2006.201.09:22:46.58/k5log//k5ts2_log_newline 2006.201.09:22:47.26/k5log//k5ts3_log_newline 2006.201.09:22:47.95/k5log//k5ts4_log_newline 2006.201.09:22:47.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:22:47.97:setupk4=1 2006.201.09:22:47.97$setupk4/echo=on 2006.201.09:22:47.97$setupk4/pcalon 2006.201.09:22:47.97$pcalon/"no phase cal control is implemented here 2006.201.09:22:47.97$setupk4/"tpicd=stop 2006.201.09:22:47.97$setupk4/"rec=synch_on 2006.201.09:22:47.97$setupk4/"rec_mode=128 2006.201.09:22:47.97$setupk4/!* 2006.201.09:22:47.97$setupk4/recpk4 2006.201.09:22:47.97$recpk4/recpatch= 2006.201.09:22:47.98$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:22:47.98$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:22:47.98$setupk4/vck44 2006.201.09:22:47.98$vck44/valo=1,524.99 2006.201.09:22:47.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.09:22:47.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.09:22:47.98#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:47.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:47.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:47.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:47.98#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:22:47.98#ibcon#first serial, iclass 11, count 0 2006.201.09:22:47.98#ibcon#enter sib2, iclass 11, count 0 2006.201.09:22:47.98#ibcon#flushed, iclass 11, count 0 2006.201.09:22:47.98#ibcon#about to write, iclass 11, count 0 2006.201.09:22:47.98#ibcon#wrote, iclass 11, count 0 2006.201.09:22:47.98#ibcon#about to read 3, iclass 11, count 0 2006.201.09:22:48.01#ibcon#read 3, iclass 11, count 0 2006.201.09:22:48.01#ibcon#about to read 4, iclass 11, count 0 2006.201.09:22:48.01#ibcon#read 4, iclass 11, count 0 2006.201.09:22:48.01#ibcon#about to read 5, iclass 11, count 0 2006.201.09:22:48.01#ibcon#read 5, iclass 11, count 0 2006.201.09:22:48.01#ibcon#about to read 6, iclass 11, count 0 2006.201.09:22:48.01#ibcon#read 6, iclass 11, count 0 2006.201.09:22:48.01#ibcon#end of sib2, iclass 11, count 0 2006.201.09:22:48.01#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:22:48.01#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:22:48.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:22:48.01#ibcon#*before write, iclass 11, count 0 2006.201.09:22:48.01#ibcon#enter sib2, iclass 11, count 0 2006.201.09:22:48.01#ibcon#flushed, iclass 11, count 0 2006.201.09:22:48.01#ibcon#about to write, iclass 11, count 0 2006.201.09:22:48.01#ibcon#wrote, iclass 11, count 0 2006.201.09:22:48.01#ibcon#about to read 3, iclass 11, count 0 2006.201.09:22:48.07#ibcon#read 3, iclass 11, count 0 2006.201.09:22:48.07#ibcon#about to read 4, iclass 11, count 0 2006.201.09:22:48.07#ibcon#read 4, iclass 11, count 0 2006.201.09:22:48.07#ibcon#about to read 5, iclass 11, count 0 2006.201.09:22:48.07#ibcon#read 5, iclass 11, count 0 2006.201.09:22:48.07#ibcon#about to read 6, iclass 11, count 0 2006.201.09:22:48.07#ibcon#read 6, iclass 11, count 0 2006.201.09:22:48.07#ibcon#end of sib2, iclass 11, count 0 2006.201.09:22:48.07#ibcon#*after write, iclass 11, count 0 2006.201.09:22:48.07#ibcon#*before return 0, iclass 11, count 0 2006.201.09:22:48.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:48.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:48.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:22:48.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:22:48.07$vck44/va=1,8 2006.201.09:22:48.07#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.09:22:48.07#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.09:22:48.07#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:48.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:48.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:48.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:48.07#ibcon#enter wrdev, iclass 13, count 2 2006.201.09:22:48.07#ibcon#first serial, iclass 13, count 2 2006.201.09:22:48.07#ibcon#enter sib2, iclass 13, count 2 2006.201.09:22:48.07#ibcon#flushed, iclass 13, count 2 2006.201.09:22:48.07#ibcon#about to write, iclass 13, count 2 2006.201.09:22:48.07#ibcon#wrote, iclass 13, count 2 2006.201.09:22:48.07#ibcon#about to read 3, iclass 13, count 2 2006.201.09:22:48.09#ibcon#read 3, iclass 13, count 2 2006.201.09:22:48.09#ibcon#about to read 4, iclass 13, count 2 2006.201.09:22:48.09#ibcon#read 4, iclass 13, count 2 2006.201.09:22:48.09#ibcon#about to read 5, iclass 13, count 2 2006.201.09:22:48.09#ibcon#read 5, iclass 13, count 2 2006.201.09:22:48.09#ibcon#about to read 6, iclass 13, count 2 2006.201.09:22:48.09#ibcon#read 6, iclass 13, count 2 2006.201.09:22:48.09#ibcon#end of sib2, iclass 13, count 2 2006.201.09:22:48.09#ibcon#*mode == 0, iclass 13, count 2 2006.201.09:22:48.09#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.09:22:48.09#ibcon#[25=AT01-08\r\n] 2006.201.09:22:48.09#ibcon#*before write, iclass 13, count 2 2006.201.09:22:48.09#ibcon#enter sib2, iclass 13, count 2 2006.201.09:22:48.09#ibcon#flushed, iclass 13, count 2 2006.201.09:22:48.09#ibcon#about to write, iclass 13, count 2 2006.201.09:22:48.09#ibcon#wrote, iclass 13, count 2 2006.201.09:22:48.09#ibcon#about to read 3, iclass 13, count 2 2006.201.09:22:48.13#ibcon#read 3, iclass 13, count 2 2006.201.09:22:48.13#ibcon#about to read 4, iclass 13, count 2 2006.201.09:22:48.13#ibcon#read 4, iclass 13, count 2 2006.201.09:22:48.13#ibcon#about to read 5, iclass 13, count 2 2006.201.09:22:48.13#ibcon#read 5, iclass 13, count 2 2006.201.09:22:48.13#ibcon#about to read 6, iclass 13, count 2 2006.201.09:22:48.13#ibcon#read 6, iclass 13, count 2 2006.201.09:22:48.13#ibcon#end of sib2, iclass 13, count 2 2006.201.09:22:48.13#ibcon#*after write, iclass 13, count 2 2006.201.09:22:48.13#ibcon#*before return 0, iclass 13, count 2 2006.201.09:22:48.13#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:48.13#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:48.13#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.09:22:48.13#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:48.13#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:48.25#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:48.25#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:48.25#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:22:48.25#ibcon#first serial, iclass 13, count 0 2006.201.09:22:48.25#ibcon#enter sib2, iclass 13, count 0 2006.201.09:22:48.25#ibcon#flushed, iclass 13, count 0 2006.201.09:22:48.25#ibcon#about to write, iclass 13, count 0 2006.201.09:22:48.25#ibcon#wrote, iclass 13, count 0 2006.201.09:22:48.25#ibcon#about to read 3, iclass 13, count 0 2006.201.09:22:48.27#ibcon#read 3, iclass 13, count 0 2006.201.09:22:48.27#ibcon#about to read 4, iclass 13, count 0 2006.201.09:22:48.27#ibcon#read 4, iclass 13, count 0 2006.201.09:22:48.27#ibcon#about to read 5, iclass 13, count 0 2006.201.09:22:48.27#ibcon#read 5, iclass 13, count 0 2006.201.09:22:48.27#ibcon#about to read 6, iclass 13, count 0 2006.201.09:22:48.27#ibcon#read 6, iclass 13, count 0 2006.201.09:22:48.27#ibcon#end of sib2, iclass 13, count 0 2006.201.09:22:48.27#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:22:48.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:22:48.27#ibcon#[25=USB\r\n] 2006.201.09:22:48.27#ibcon#*before write, iclass 13, count 0 2006.201.09:22:48.27#ibcon#enter sib2, iclass 13, count 0 2006.201.09:22:48.27#ibcon#flushed, iclass 13, count 0 2006.201.09:22:48.27#ibcon#about to write, iclass 13, count 0 2006.201.09:22:48.27#ibcon#wrote, iclass 13, count 0 2006.201.09:22:48.27#ibcon#about to read 3, iclass 13, count 0 2006.201.09:22:48.30#ibcon#read 3, iclass 13, count 0 2006.201.09:22:48.30#ibcon#about to read 4, iclass 13, count 0 2006.201.09:22:48.30#ibcon#read 4, iclass 13, count 0 2006.201.09:22:48.30#ibcon#about to read 5, iclass 13, count 0 2006.201.09:22:48.30#ibcon#read 5, iclass 13, count 0 2006.201.09:22:48.30#ibcon#about to read 6, iclass 13, count 0 2006.201.09:22:48.30#ibcon#read 6, iclass 13, count 0 2006.201.09:22:48.30#ibcon#end of sib2, iclass 13, count 0 2006.201.09:22:48.30#ibcon#*after write, iclass 13, count 0 2006.201.09:22:48.30#ibcon#*before return 0, iclass 13, count 0 2006.201.09:22:48.30#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:48.30#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:48.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:22:48.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:22:48.30$vck44/valo=2,534.99 2006.201.09:22:48.30#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.09:22:48.30#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.09:22:48.30#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:48.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:48.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:48.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:48.30#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:22:48.30#ibcon#first serial, iclass 15, count 0 2006.201.09:22:48.30#ibcon#enter sib2, iclass 15, count 0 2006.201.09:22:48.30#ibcon#flushed, iclass 15, count 0 2006.201.09:22:48.30#ibcon#about to write, iclass 15, count 0 2006.201.09:22:48.30#ibcon#wrote, iclass 15, count 0 2006.201.09:22:48.30#ibcon#about to read 3, iclass 15, count 0 2006.201.09:22:48.32#ibcon#read 3, iclass 15, count 0 2006.201.09:22:48.32#ibcon#about to read 4, iclass 15, count 0 2006.201.09:22:48.32#ibcon#read 4, iclass 15, count 0 2006.201.09:22:48.32#ibcon#about to read 5, iclass 15, count 0 2006.201.09:22:48.32#ibcon#read 5, iclass 15, count 0 2006.201.09:22:48.32#ibcon#about to read 6, iclass 15, count 0 2006.201.09:22:48.32#ibcon#read 6, iclass 15, count 0 2006.201.09:22:48.32#ibcon#end of sib2, iclass 15, count 0 2006.201.09:22:48.32#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:22:48.32#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:22:48.32#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:22:48.32#ibcon#*before write, iclass 15, count 0 2006.201.09:22:48.32#ibcon#enter sib2, iclass 15, count 0 2006.201.09:22:48.32#ibcon#flushed, iclass 15, count 0 2006.201.09:22:48.32#ibcon#about to write, iclass 15, count 0 2006.201.09:22:48.32#ibcon#wrote, iclass 15, count 0 2006.201.09:22:48.32#ibcon#about to read 3, iclass 15, count 0 2006.201.09:22:48.37#ibcon#read 3, iclass 15, count 0 2006.201.09:22:48.37#ibcon#about to read 4, iclass 15, count 0 2006.201.09:22:48.37#ibcon#read 4, iclass 15, count 0 2006.201.09:22:48.37#ibcon#about to read 5, iclass 15, count 0 2006.201.09:22:48.37#ibcon#read 5, iclass 15, count 0 2006.201.09:22:48.37#ibcon#about to read 6, iclass 15, count 0 2006.201.09:22:48.37#ibcon#read 6, iclass 15, count 0 2006.201.09:22:48.37#ibcon#end of sib2, iclass 15, count 0 2006.201.09:22:48.37#ibcon#*after write, iclass 15, count 0 2006.201.09:22:48.37#ibcon#*before return 0, iclass 15, count 0 2006.201.09:22:48.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:48.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:48.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:22:48.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:22:48.37$vck44/va=2,7 2006.201.09:22:48.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.09:22:48.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.09:22:48.37#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:48.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:48.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:48.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:48.42#ibcon#enter wrdev, iclass 17, count 2 2006.201.09:22:48.42#ibcon#first serial, iclass 17, count 2 2006.201.09:22:48.42#ibcon#enter sib2, iclass 17, count 2 2006.201.09:22:48.42#ibcon#flushed, iclass 17, count 2 2006.201.09:22:48.42#ibcon#about to write, iclass 17, count 2 2006.201.09:22:48.42#ibcon#wrote, iclass 17, count 2 2006.201.09:22:48.42#ibcon#about to read 3, iclass 17, count 2 2006.201.09:22:48.44#ibcon#read 3, iclass 17, count 2 2006.201.09:22:48.44#ibcon#about to read 4, iclass 17, count 2 2006.201.09:22:48.44#ibcon#read 4, iclass 17, count 2 2006.201.09:22:48.44#ibcon#about to read 5, iclass 17, count 2 2006.201.09:22:48.44#ibcon#read 5, iclass 17, count 2 2006.201.09:22:48.44#ibcon#about to read 6, iclass 17, count 2 2006.201.09:22:48.44#ibcon#read 6, iclass 17, count 2 2006.201.09:22:48.44#ibcon#end of sib2, iclass 17, count 2 2006.201.09:22:48.44#ibcon#*mode == 0, iclass 17, count 2 2006.201.09:22:48.44#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.09:22:48.44#ibcon#[25=AT02-07\r\n] 2006.201.09:22:48.44#ibcon#*before write, iclass 17, count 2 2006.201.09:22:48.44#ibcon#enter sib2, iclass 17, count 2 2006.201.09:22:48.44#ibcon#flushed, iclass 17, count 2 2006.201.09:22:48.44#ibcon#about to write, iclass 17, count 2 2006.201.09:22:48.44#ibcon#wrote, iclass 17, count 2 2006.201.09:22:48.44#ibcon#about to read 3, iclass 17, count 2 2006.201.09:22:48.47#ibcon#read 3, iclass 17, count 2 2006.201.09:22:48.47#ibcon#about to read 4, iclass 17, count 2 2006.201.09:22:48.47#ibcon#read 4, iclass 17, count 2 2006.201.09:22:48.47#ibcon#about to read 5, iclass 17, count 2 2006.201.09:22:48.47#ibcon#read 5, iclass 17, count 2 2006.201.09:22:48.47#ibcon#about to read 6, iclass 17, count 2 2006.201.09:22:48.47#ibcon#read 6, iclass 17, count 2 2006.201.09:22:48.47#ibcon#end of sib2, iclass 17, count 2 2006.201.09:22:48.47#ibcon#*after write, iclass 17, count 2 2006.201.09:22:48.47#ibcon#*before return 0, iclass 17, count 2 2006.201.09:22:48.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:48.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:48.47#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.09:22:48.47#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:48.47#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:48.59#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:48.59#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:48.59#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:22:48.59#ibcon#first serial, iclass 17, count 0 2006.201.09:22:48.59#ibcon#enter sib2, iclass 17, count 0 2006.201.09:22:48.59#ibcon#flushed, iclass 17, count 0 2006.201.09:22:48.59#ibcon#about to write, iclass 17, count 0 2006.201.09:22:48.59#ibcon#wrote, iclass 17, count 0 2006.201.09:22:48.59#ibcon#about to read 3, iclass 17, count 0 2006.201.09:22:48.61#ibcon#read 3, iclass 17, count 0 2006.201.09:22:48.61#ibcon#about to read 4, iclass 17, count 0 2006.201.09:22:48.61#ibcon#read 4, iclass 17, count 0 2006.201.09:22:48.61#ibcon#about to read 5, iclass 17, count 0 2006.201.09:22:48.61#ibcon#read 5, iclass 17, count 0 2006.201.09:22:48.61#ibcon#about to read 6, iclass 17, count 0 2006.201.09:22:48.61#ibcon#read 6, iclass 17, count 0 2006.201.09:22:48.61#ibcon#end of sib2, iclass 17, count 0 2006.201.09:22:48.61#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:22:48.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:22:48.61#ibcon#[25=USB\r\n] 2006.201.09:22:48.61#ibcon#*before write, iclass 17, count 0 2006.201.09:22:48.61#ibcon#enter sib2, iclass 17, count 0 2006.201.09:22:48.61#ibcon#flushed, iclass 17, count 0 2006.201.09:22:48.61#ibcon#about to write, iclass 17, count 0 2006.201.09:22:48.61#ibcon#wrote, iclass 17, count 0 2006.201.09:22:48.61#ibcon#about to read 3, iclass 17, count 0 2006.201.09:22:48.64#ibcon#read 3, iclass 17, count 0 2006.201.09:22:48.64#ibcon#about to read 4, iclass 17, count 0 2006.201.09:22:48.64#ibcon#read 4, iclass 17, count 0 2006.201.09:22:48.64#ibcon#about to read 5, iclass 17, count 0 2006.201.09:22:48.64#ibcon#read 5, iclass 17, count 0 2006.201.09:22:48.64#ibcon#about to read 6, iclass 17, count 0 2006.201.09:22:48.64#ibcon#read 6, iclass 17, count 0 2006.201.09:22:48.64#ibcon#end of sib2, iclass 17, count 0 2006.201.09:22:48.64#ibcon#*after write, iclass 17, count 0 2006.201.09:22:48.64#ibcon#*before return 0, iclass 17, count 0 2006.201.09:22:48.64#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:48.64#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:48.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:22:48.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:22:48.64$vck44/valo=3,564.99 2006.201.09:22:48.64#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.09:22:48.64#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.09:22:48.64#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:48.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:48.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:48.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:48.64#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:22:48.64#ibcon#first serial, iclass 19, count 0 2006.201.09:22:48.64#ibcon#enter sib2, iclass 19, count 0 2006.201.09:22:48.64#ibcon#flushed, iclass 19, count 0 2006.201.09:22:48.64#ibcon#about to write, iclass 19, count 0 2006.201.09:22:48.64#ibcon#wrote, iclass 19, count 0 2006.201.09:22:48.64#ibcon#about to read 3, iclass 19, count 0 2006.201.09:22:48.66#ibcon#read 3, iclass 19, count 0 2006.201.09:22:48.66#ibcon#about to read 4, iclass 19, count 0 2006.201.09:22:48.66#ibcon#read 4, iclass 19, count 0 2006.201.09:22:48.66#ibcon#about to read 5, iclass 19, count 0 2006.201.09:22:48.66#ibcon#read 5, iclass 19, count 0 2006.201.09:22:48.66#ibcon#about to read 6, iclass 19, count 0 2006.201.09:22:48.66#ibcon#read 6, iclass 19, count 0 2006.201.09:22:48.66#ibcon#end of sib2, iclass 19, count 0 2006.201.09:22:48.66#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:22:48.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:22:48.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:22:48.66#ibcon#*before write, iclass 19, count 0 2006.201.09:22:48.66#ibcon#enter sib2, iclass 19, count 0 2006.201.09:22:48.66#ibcon#flushed, iclass 19, count 0 2006.201.09:22:48.66#ibcon#about to write, iclass 19, count 0 2006.201.09:22:48.66#ibcon#wrote, iclass 19, count 0 2006.201.09:22:48.66#ibcon#about to read 3, iclass 19, count 0 2006.201.09:22:48.71#ibcon#read 3, iclass 19, count 0 2006.201.09:22:48.71#ibcon#about to read 4, iclass 19, count 0 2006.201.09:22:48.71#ibcon#read 4, iclass 19, count 0 2006.201.09:22:48.71#ibcon#about to read 5, iclass 19, count 0 2006.201.09:22:48.71#ibcon#read 5, iclass 19, count 0 2006.201.09:22:48.71#ibcon#about to read 6, iclass 19, count 0 2006.201.09:22:48.71#ibcon#read 6, iclass 19, count 0 2006.201.09:22:48.71#ibcon#end of sib2, iclass 19, count 0 2006.201.09:22:48.71#ibcon#*after write, iclass 19, count 0 2006.201.09:22:48.71#ibcon#*before return 0, iclass 19, count 0 2006.201.09:22:48.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:48.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:48.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:22:48.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:22:48.71$vck44/va=3,8 2006.201.09:22:48.71#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.09:22:48.71#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.09:22:48.71#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:48.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:48.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:48.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:48.76#ibcon#enter wrdev, iclass 21, count 2 2006.201.09:22:48.76#ibcon#first serial, iclass 21, count 2 2006.201.09:22:48.76#ibcon#enter sib2, iclass 21, count 2 2006.201.09:22:48.76#ibcon#flushed, iclass 21, count 2 2006.201.09:22:48.76#ibcon#about to write, iclass 21, count 2 2006.201.09:22:48.76#ibcon#wrote, iclass 21, count 2 2006.201.09:22:48.76#ibcon#about to read 3, iclass 21, count 2 2006.201.09:22:48.78#ibcon#read 3, iclass 21, count 2 2006.201.09:22:48.78#ibcon#about to read 4, iclass 21, count 2 2006.201.09:22:48.78#ibcon#read 4, iclass 21, count 2 2006.201.09:22:48.78#ibcon#about to read 5, iclass 21, count 2 2006.201.09:22:48.78#ibcon#read 5, iclass 21, count 2 2006.201.09:22:48.78#ibcon#about to read 6, iclass 21, count 2 2006.201.09:22:48.78#ibcon#read 6, iclass 21, count 2 2006.201.09:22:48.78#ibcon#end of sib2, iclass 21, count 2 2006.201.09:22:48.78#ibcon#*mode == 0, iclass 21, count 2 2006.201.09:22:48.78#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.09:22:48.78#ibcon#[25=AT03-08\r\n] 2006.201.09:22:48.78#ibcon#*before write, iclass 21, count 2 2006.201.09:22:48.78#ibcon#enter sib2, iclass 21, count 2 2006.201.09:22:48.78#ibcon#flushed, iclass 21, count 2 2006.201.09:22:48.78#ibcon#about to write, iclass 21, count 2 2006.201.09:22:48.78#ibcon#wrote, iclass 21, count 2 2006.201.09:22:48.78#ibcon#about to read 3, iclass 21, count 2 2006.201.09:22:48.81#ibcon#read 3, iclass 21, count 2 2006.201.09:22:48.81#ibcon#about to read 4, iclass 21, count 2 2006.201.09:22:48.81#ibcon#read 4, iclass 21, count 2 2006.201.09:22:48.81#ibcon#about to read 5, iclass 21, count 2 2006.201.09:22:48.81#ibcon#read 5, iclass 21, count 2 2006.201.09:22:48.81#ibcon#about to read 6, iclass 21, count 2 2006.201.09:22:48.81#ibcon#read 6, iclass 21, count 2 2006.201.09:22:48.81#ibcon#end of sib2, iclass 21, count 2 2006.201.09:22:48.81#ibcon#*after write, iclass 21, count 2 2006.201.09:22:48.81#ibcon#*before return 0, iclass 21, count 2 2006.201.09:22:48.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:48.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:48.81#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.09:22:48.81#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:48.81#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:48.93#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:48.93#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:48.93#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:22:48.93#ibcon#first serial, iclass 21, count 0 2006.201.09:22:48.93#ibcon#enter sib2, iclass 21, count 0 2006.201.09:22:48.93#ibcon#flushed, iclass 21, count 0 2006.201.09:22:48.93#ibcon#about to write, iclass 21, count 0 2006.201.09:22:48.93#ibcon#wrote, iclass 21, count 0 2006.201.09:22:48.93#ibcon#about to read 3, iclass 21, count 0 2006.201.09:22:48.95#ibcon#read 3, iclass 21, count 0 2006.201.09:22:48.95#ibcon#about to read 4, iclass 21, count 0 2006.201.09:22:48.95#ibcon#read 4, iclass 21, count 0 2006.201.09:22:48.95#ibcon#about to read 5, iclass 21, count 0 2006.201.09:22:48.95#ibcon#read 5, iclass 21, count 0 2006.201.09:22:48.95#ibcon#about to read 6, iclass 21, count 0 2006.201.09:22:48.95#ibcon#read 6, iclass 21, count 0 2006.201.09:22:48.95#ibcon#end of sib2, iclass 21, count 0 2006.201.09:22:48.95#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:22:48.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:22:48.95#ibcon#[25=USB\r\n] 2006.201.09:22:48.95#ibcon#*before write, iclass 21, count 0 2006.201.09:22:48.95#ibcon#enter sib2, iclass 21, count 0 2006.201.09:22:48.95#ibcon#flushed, iclass 21, count 0 2006.201.09:22:48.95#ibcon#about to write, iclass 21, count 0 2006.201.09:22:48.95#ibcon#wrote, iclass 21, count 0 2006.201.09:22:48.95#ibcon#about to read 3, iclass 21, count 0 2006.201.09:22:48.98#ibcon#read 3, iclass 21, count 0 2006.201.09:22:48.98#ibcon#about to read 4, iclass 21, count 0 2006.201.09:22:48.98#ibcon#read 4, iclass 21, count 0 2006.201.09:22:48.98#ibcon#about to read 5, iclass 21, count 0 2006.201.09:22:48.98#ibcon#read 5, iclass 21, count 0 2006.201.09:22:48.98#ibcon#about to read 6, iclass 21, count 0 2006.201.09:22:48.98#ibcon#read 6, iclass 21, count 0 2006.201.09:22:48.98#ibcon#end of sib2, iclass 21, count 0 2006.201.09:22:48.98#ibcon#*after write, iclass 21, count 0 2006.201.09:22:48.98#ibcon#*before return 0, iclass 21, count 0 2006.201.09:22:48.98#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:48.98#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:48.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:22:48.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:22:48.98$vck44/valo=4,624.99 2006.201.09:22:48.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.09:22:48.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.09:22:48.98#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:48.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:48.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:48.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:48.98#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:22:48.98#ibcon#first serial, iclass 23, count 0 2006.201.09:22:48.98#ibcon#enter sib2, iclass 23, count 0 2006.201.09:22:48.98#ibcon#flushed, iclass 23, count 0 2006.201.09:22:48.98#ibcon#about to write, iclass 23, count 0 2006.201.09:22:48.98#ibcon#wrote, iclass 23, count 0 2006.201.09:22:48.98#ibcon#about to read 3, iclass 23, count 0 2006.201.09:22:49.00#ibcon#read 3, iclass 23, count 0 2006.201.09:22:49.00#ibcon#about to read 4, iclass 23, count 0 2006.201.09:22:49.00#ibcon#read 4, iclass 23, count 0 2006.201.09:22:49.00#ibcon#about to read 5, iclass 23, count 0 2006.201.09:22:49.00#ibcon#read 5, iclass 23, count 0 2006.201.09:22:49.00#ibcon#about to read 6, iclass 23, count 0 2006.201.09:22:49.00#ibcon#read 6, iclass 23, count 0 2006.201.09:22:49.00#ibcon#end of sib2, iclass 23, count 0 2006.201.09:22:49.00#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:22:49.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:22:49.00#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:22:49.00#ibcon#*before write, iclass 23, count 0 2006.201.09:22:49.00#ibcon#enter sib2, iclass 23, count 0 2006.201.09:22:49.00#ibcon#flushed, iclass 23, count 0 2006.201.09:22:49.00#ibcon#about to write, iclass 23, count 0 2006.201.09:22:49.00#ibcon#wrote, iclass 23, count 0 2006.201.09:22:49.00#ibcon#about to read 3, iclass 23, count 0 2006.201.09:22:49.05#ibcon#read 3, iclass 23, count 0 2006.201.09:22:49.05#ibcon#about to read 4, iclass 23, count 0 2006.201.09:22:49.05#ibcon#read 4, iclass 23, count 0 2006.201.09:22:49.05#ibcon#about to read 5, iclass 23, count 0 2006.201.09:22:49.05#ibcon#read 5, iclass 23, count 0 2006.201.09:22:49.05#ibcon#about to read 6, iclass 23, count 0 2006.201.09:22:49.05#ibcon#read 6, iclass 23, count 0 2006.201.09:22:49.05#ibcon#end of sib2, iclass 23, count 0 2006.201.09:22:49.05#ibcon#*after write, iclass 23, count 0 2006.201.09:22:49.05#ibcon#*before return 0, iclass 23, count 0 2006.201.09:22:49.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:49.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:49.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:22:49.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:22:49.05$vck44/va=4,7 2006.201.09:22:49.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.09:22:49.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.09:22:49.05#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:49.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:49.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:49.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:49.10#ibcon#enter wrdev, iclass 25, count 2 2006.201.09:22:49.10#ibcon#first serial, iclass 25, count 2 2006.201.09:22:49.10#ibcon#enter sib2, iclass 25, count 2 2006.201.09:22:49.10#ibcon#flushed, iclass 25, count 2 2006.201.09:22:49.10#ibcon#about to write, iclass 25, count 2 2006.201.09:22:49.10#ibcon#wrote, iclass 25, count 2 2006.201.09:22:49.10#ibcon#about to read 3, iclass 25, count 2 2006.201.09:22:49.12#ibcon#read 3, iclass 25, count 2 2006.201.09:22:49.12#ibcon#about to read 4, iclass 25, count 2 2006.201.09:22:49.12#ibcon#read 4, iclass 25, count 2 2006.201.09:22:49.12#ibcon#about to read 5, iclass 25, count 2 2006.201.09:22:49.12#ibcon#read 5, iclass 25, count 2 2006.201.09:22:49.12#ibcon#about to read 6, iclass 25, count 2 2006.201.09:22:49.12#ibcon#read 6, iclass 25, count 2 2006.201.09:22:49.12#ibcon#end of sib2, iclass 25, count 2 2006.201.09:22:49.12#ibcon#*mode == 0, iclass 25, count 2 2006.201.09:22:49.12#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.09:22:49.12#ibcon#[25=AT04-07\r\n] 2006.201.09:22:49.12#ibcon#*before write, iclass 25, count 2 2006.201.09:22:49.12#ibcon#enter sib2, iclass 25, count 2 2006.201.09:22:49.12#ibcon#flushed, iclass 25, count 2 2006.201.09:22:49.12#ibcon#about to write, iclass 25, count 2 2006.201.09:22:49.12#ibcon#wrote, iclass 25, count 2 2006.201.09:22:49.12#ibcon#about to read 3, iclass 25, count 2 2006.201.09:22:49.15#ibcon#read 3, iclass 25, count 2 2006.201.09:22:49.15#ibcon#about to read 4, iclass 25, count 2 2006.201.09:22:49.15#ibcon#read 4, iclass 25, count 2 2006.201.09:22:49.15#ibcon#about to read 5, iclass 25, count 2 2006.201.09:22:49.15#ibcon#read 5, iclass 25, count 2 2006.201.09:22:49.15#ibcon#about to read 6, iclass 25, count 2 2006.201.09:22:49.15#ibcon#read 6, iclass 25, count 2 2006.201.09:22:49.15#ibcon#end of sib2, iclass 25, count 2 2006.201.09:22:49.15#ibcon#*after write, iclass 25, count 2 2006.201.09:22:49.15#ibcon#*before return 0, iclass 25, count 2 2006.201.09:22:49.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:49.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:49.15#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.09:22:49.15#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:49.15#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:49.27#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:49.27#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:49.27#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:22:49.27#ibcon#first serial, iclass 25, count 0 2006.201.09:22:49.27#ibcon#enter sib2, iclass 25, count 0 2006.201.09:22:49.27#ibcon#flushed, iclass 25, count 0 2006.201.09:22:49.27#ibcon#about to write, iclass 25, count 0 2006.201.09:22:49.27#ibcon#wrote, iclass 25, count 0 2006.201.09:22:49.27#ibcon#about to read 3, iclass 25, count 0 2006.201.09:22:49.29#ibcon#read 3, iclass 25, count 0 2006.201.09:22:49.29#ibcon#about to read 4, iclass 25, count 0 2006.201.09:22:49.29#ibcon#read 4, iclass 25, count 0 2006.201.09:22:49.29#ibcon#about to read 5, iclass 25, count 0 2006.201.09:22:49.29#ibcon#read 5, iclass 25, count 0 2006.201.09:22:49.29#ibcon#about to read 6, iclass 25, count 0 2006.201.09:22:49.29#ibcon#read 6, iclass 25, count 0 2006.201.09:22:49.29#ibcon#end of sib2, iclass 25, count 0 2006.201.09:22:49.29#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:22:49.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:22:49.29#ibcon#[25=USB\r\n] 2006.201.09:22:49.29#ibcon#*before write, iclass 25, count 0 2006.201.09:22:49.29#ibcon#enter sib2, iclass 25, count 0 2006.201.09:22:49.29#ibcon#flushed, iclass 25, count 0 2006.201.09:22:49.29#ibcon#about to write, iclass 25, count 0 2006.201.09:22:49.29#ibcon#wrote, iclass 25, count 0 2006.201.09:22:49.29#ibcon#about to read 3, iclass 25, count 0 2006.201.09:22:49.32#ibcon#read 3, iclass 25, count 0 2006.201.09:22:49.32#ibcon#about to read 4, iclass 25, count 0 2006.201.09:22:49.32#ibcon#read 4, iclass 25, count 0 2006.201.09:22:49.32#ibcon#about to read 5, iclass 25, count 0 2006.201.09:22:49.32#ibcon#read 5, iclass 25, count 0 2006.201.09:22:49.32#ibcon#about to read 6, iclass 25, count 0 2006.201.09:22:49.32#ibcon#read 6, iclass 25, count 0 2006.201.09:22:49.32#ibcon#end of sib2, iclass 25, count 0 2006.201.09:22:49.32#ibcon#*after write, iclass 25, count 0 2006.201.09:22:49.32#ibcon#*before return 0, iclass 25, count 0 2006.201.09:22:49.32#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:49.32#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:49.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:22:49.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:22:49.32$vck44/valo=5,734.99 2006.201.09:22:49.32#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.09:22:49.32#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.09:22:49.32#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:49.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:49.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:49.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:49.32#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:22:49.32#ibcon#first serial, iclass 27, count 0 2006.201.09:22:49.32#ibcon#enter sib2, iclass 27, count 0 2006.201.09:22:49.32#ibcon#flushed, iclass 27, count 0 2006.201.09:22:49.32#ibcon#about to write, iclass 27, count 0 2006.201.09:22:49.32#ibcon#wrote, iclass 27, count 0 2006.201.09:22:49.32#ibcon#about to read 3, iclass 27, count 0 2006.201.09:22:49.34#ibcon#read 3, iclass 27, count 0 2006.201.09:22:49.34#ibcon#about to read 4, iclass 27, count 0 2006.201.09:22:49.34#ibcon#read 4, iclass 27, count 0 2006.201.09:22:49.34#ibcon#about to read 5, iclass 27, count 0 2006.201.09:22:49.34#ibcon#read 5, iclass 27, count 0 2006.201.09:22:49.34#ibcon#about to read 6, iclass 27, count 0 2006.201.09:22:49.34#ibcon#read 6, iclass 27, count 0 2006.201.09:22:49.34#ibcon#end of sib2, iclass 27, count 0 2006.201.09:22:49.34#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:22:49.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:22:49.34#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:22:49.34#ibcon#*before write, iclass 27, count 0 2006.201.09:22:49.34#ibcon#enter sib2, iclass 27, count 0 2006.201.09:22:49.34#ibcon#flushed, iclass 27, count 0 2006.201.09:22:49.34#ibcon#about to write, iclass 27, count 0 2006.201.09:22:49.34#ibcon#wrote, iclass 27, count 0 2006.201.09:22:49.34#ibcon#about to read 3, iclass 27, count 0 2006.201.09:22:49.38#ibcon#read 3, iclass 27, count 0 2006.201.09:22:49.38#ibcon#about to read 4, iclass 27, count 0 2006.201.09:22:49.38#ibcon#read 4, iclass 27, count 0 2006.201.09:22:49.38#ibcon#about to read 5, iclass 27, count 0 2006.201.09:22:49.38#ibcon#read 5, iclass 27, count 0 2006.201.09:22:49.38#ibcon#about to read 6, iclass 27, count 0 2006.201.09:22:49.38#ibcon#read 6, iclass 27, count 0 2006.201.09:22:49.38#ibcon#end of sib2, iclass 27, count 0 2006.201.09:22:49.38#ibcon#*after write, iclass 27, count 0 2006.201.09:22:49.38#ibcon#*before return 0, iclass 27, count 0 2006.201.09:22:49.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:49.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:49.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:22:49.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:22:49.38$vck44/va=5,4 2006.201.09:22:49.38#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.09:22:49.38#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.09:22:49.38#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:49.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:49.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:49.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:49.44#ibcon#enter wrdev, iclass 29, count 2 2006.201.09:22:49.44#ibcon#first serial, iclass 29, count 2 2006.201.09:22:49.44#ibcon#enter sib2, iclass 29, count 2 2006.201.09:22:49.44#ibcon#flushed, iclass 29, count 2 2006.201.09:22:49.44#ibcon#about to write, iclass 29, count 2 2006.201.09:22:49.44#ibcon#wrote, iclass 29, count 2 2006.201.09:22:49.44#ibcon#about to read 3, iclass 29, count 2 2006.201.09:22:49.46#ibcon#read 3, iclass 29, count 2 2006.201.09:22:49.46#ibcon#about to read 4, iclass 29, count 2 2006.201.09:22:49.46#ibcon#read 4, iclass 29, count 2 2006.201.09:22:49.46#ibcon#about to read 5, iclass 29, count 2 2006.201.09:22:49.46#ibcon#read 5, iclass 29, count 2 2006.201.09:22:49.46#ibcon#about to read 6, iclass 29, count 2 2006.201.09:22:49.46#ibcon#read 6, iclass 29, count 2 2006.201.09:22:49.46#ibcon#end of sib2, iclass 29, count 2 2006.201.09:22:49.46#ibcon#*mode == 0, iclass 29, count 2 2006.201.09:22:49.46#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.09:22:49.46#ibcon#[25=AT05-04\r\n] 2006.201.09:22:49.46#ibcon#*before write, iclass 29, count 2 2006.201.09:22:49.46#ibcon#enter sib2, iclass 29, count 2 2006.201.09:22:49.46#ibcon#flushed, iclass 29, count 2 2006.201.09:22:49.46#ibcon#about to write, iclass 29, count 2 2006.201.09:22:49.46#ibcon#wrote, iclass 29, count 2 2006.201.09:22:49.46#ibcon#about to read 3, iclass 29, count 2 2006.201.09:22:49.49#ibcon#read 3, iclass 29, count 2 2006.201.09:22:49.49#ibcon#about to read 4, iclass 29, count 2 2006.201.09:22:49.49#ibcon#read 4, iclass 29, count 2 2006.201.09:22:49.49#ibcon#about to read 5, iclass 29, count 2 2006.201.09:22:49.49#ibcon#read 5, iclass 29, count 2 2006.201.09:22:49.49#ibcon#about to read 6, iclass 29, count 2 2006.201.09:22:49.49#ibcon#read 6, iclass 29, count 2 2006.201.09:22:49.49#ibcon#end of sib2, iclass 29, count 2 2006.201.09:22:49.49#ibcon#*after write, iclass 29, count 2 2006.201.09:22:49.49#ibcon#*before return 0, iclass 29, count 2 2006.201.09:22:49.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:49.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:49.49#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.09:22:49.49#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:49.49#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:49.61#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:49.61#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:49.61#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:22:49.61#ibcon#first serial, iclass 29, count 0 2006.201.09:22:49.61#ibcon#enter sib2, iclass 29, count 0 2006.201.09:22:49.61#ibcon#flushed, iclass 29, count 0 2006.201.09:22:49.61#ibcon#about to write, iclass 29, count 0 2006.201.09:22:49.61#ibcon#wrote, iclass 29, count 0 2006.201.09:22:49.61#ibcon#about to read 3, iclass 29, count 0 2006.201.09:22:49.63#ibcon#read 3, iclass 29, count 0 2006.201.09:22:49.63#ibcon#about to read 4, iclass 29, count 0 2006.201.09:22:49.63#ibcon#read 4, iclass 29, count 0 2006.201.09:22:49.63#ibcon#about to read 5, iclass 29, count 0 2006.201.09:22:49.63#ibcon#read 5, iclass 29, count 0 2006.201.09:22:49.63#ibcon#about to read 6, iclass 29, count 0 2006.201.09:22:49.63#ibcon#read 6, iclass 29, count 0 2006.201.09:22:49.63#ibcon#end of sib2, iclass 29, count 0 2006.201.09:22:49.63#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:22:49.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:22:49.63#ibcon#[25=USB\r\n] 2006.201.09:22:49.63#ibcon#*before write, iclass 29, count 0 2006.201.09:22:49.63#ibcon#enter sib2, iclass 29, count 0 2006.201.09:22:49.63#ibcon#flushed, iclass 29, count 0 2006.201.09:22:49.63#ibcon#about to write, iclass 29, count 0 2006.201.09:22:49.63#ibcon#wrote, iclass 29, count 0 2006.201.09:22:49.63#ibcon#about to read 3, iclass 29, count 0 2006.201.09:22:49.66#ibcon#read 3, iclass 29, count 0 2006.201.09:22:49.66#ibcon#about to read 4, iclass 29, count 0 2006.201.09:22:49.66#ibcon#read 4, iclass 29, count 0 2006.201.09:22:49.66#ibcon#about to read 5, iclass 29, count 0 2006.201.09:22:49.66#ibcon#read 5, iclass 29, count 0 2006.201.09:22:49.66#ibcon#about to read 6, iclass 29, count 0 2006.201.09:22:49.66#ibcon#read 6, iclass 29, count 0 2006.201.09:22:49.66#ibcon#end of sib2, iclass 29, count 0 2006.201.09:22:49.66#ibcon#*after write, iclass 29, count 0 2006.201.09:22:49.66#ibcon#*before return 0, iclass 29, count 0 2006.201.09:22:49.66#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:49.66#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:49.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:22:49.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:22:49.66$vck44/valo=6,814.99 2006.201.09:22:49.66#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.09:22:49.66#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.09:22:49.66#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:49.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:49.66#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:49.66#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:49.66#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:22:49.66#ibcon#first serial, iclass 31, count 0 2006.201.09:22:49.66#ibcon#enter sib2, iclass 31, count 0 2006.201.09:22:49.66#ibcon#flushed, iclass 31, count 0 2006.201.09:22:49.66#ibcon#about to write, iclass 31, count 0 2006.201.09:22:49.66#ibcon#wrote, iclass 31, count 0 2006.201.09:22:49.66#ibcon#about to read 3, iclass 31, count 0 2006.201.09:22:49.68#ibcon#read 3, iclass 31, count 0 2006.201.09:22:49.68#ibcon#about to read 4, iclass 31, count 0 2006.201.09:22:49.68#ibcon#read 4, iclass 31, count 0 2006.201.09:22:49.68#ibcon#about to read 5, iclass 31, count 0 2006.201.09:22:49.68#ibcon#read 5, iclass 31, count 0 2006.201.09:22:49.68#ibcon#about to read 6, iclass 31, count 0 2006.201.09:22:49.68#ibcon#read 6, iclass 31, count 0 2006.201.09:22:49.68#ibcon#end of sib2, iclass 31, count 0 2006.201.09:22:49.68#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:22:49.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:22:49.68#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:22:49.68#ibcon#*before write, iclass 31, count 0 2006.201.09:22:49.68#ibcon#enter sib2, iclass 31, count 0 2006.201.09:22:49.68#ibcon#flushed, iclass 31, count 0 2006.201.09:22:49.68#ibcon#about to write, iclass 31, count 0 2006.201.09:22:49.68#ibcon#wrote, iclass 31, count 0 2006.201.09:22:49.68#ibcon#about to read 3, iclass 31, count 0 2006.201.09:22:49.72#ibcon#read 3, iclass 31, count 0 2006.201.09:22:49.72#ibcon#about to read 4, iclass 31, count 0 2006.201.09:22:49.72#ibcon#read 4, iclass 31, count 0 2006.201.09:22:49.72#ibcon#about to read 5, iclass 31, count 0 2006.201.09:22:49.72#ibcon#read 5, iclass 31, count 0 2006.201.09:22:49.72#ibcon#about to read 6, iclass 31, count 0 2006.201.09:22:49.72#ibcon#read 6, iclass 31, count 0 2006.201.09:22:49.72#ibcon#end of sib2, iclass 31, count 0 2006.201.09:22:49.72#ibcon#*after write, iclass 31, count 0 2006.201.09:22:49.72#ibcon#*before return 0, iclass 31, count 0 2006.201.09:22:49.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:49.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:49.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:22:49.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:22:49.72$vck44/va=6,5 2006.201.09:22:49.72#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.09:22:49.72#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.09:22:49.72#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:49.72#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:49.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:49.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:49.78#ibcon#enter wrdev, iclass 33, count 2 2006.201.09:22:49.78#ibcon#first serial, iclass 33, count 2 2006.201.09:22:49.78#ibcon#enter sib2, iclass 33, count 2 2006.201.09:22:49.78#ibcon#flushed, iclass 33, count 2 2006.201.09:22:49.78#ibcon#about to write, iclass 33, count 2 2006.201.09:22:49.78#ibcon#wrote, iclass 33, count 2 2006.201.09:22:49.78#ibcon#about to read 3, iclass 33, count 2 2006.201.09:22:49.80#ibcon#read 3, iclass 33, count 2 2006.201.09:22:49.80#ibcon#about to read 4, iclass 33, count 2 2006.201.09:22:49.80#ibcon#read 4, iclass 33, count 2 2006.201.09:22:49.80#ibcon#about to read 5, iclass 33, count 2 2006.201.09:22:49.80#ibcon#read 5, iclass 33, count 2 2006.201.09:22:49.80#ibcon#about to read 6, iclass 33, count 2 2006.201.09:22:49.80#ibcon#read 6, iclass 33, count 2 2006.201.09:22:49.80#ibcon#end of sib2, iclass 33, count 2 2006.201.09:22:49.80#ibcon#*mode == 0, iclass 33, count 2 2006.201.09:22:49.80#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.09:22:49.80#ibcon#[25=AT06-05\r\n] 2006.201.09:22:49.80#ibcon#*before write, iclass 33, count 2 2006.201.09:22:49.80#ibcon#enter sib2, iclass 33, count 2 2006.201.09:22:49.80#ibcon#flushed, iclass 33, count 2 2006.201.09:22:49.80#ibcon#about to write, iclass 33, count 2 2006.201.09:22:49.80#ibcon#wrote, iclass 33, count 2 2006.201.09:22:49.80#ibcon#about to read 3, iclass 33, count 2 2006.201.09:22:49.83#ibcon#read 3, iclass 33, count 2 2006.201.09:22:49.83#ibcon#about to read 4, iclass 33, count 2 2006.201.09:22:49.83#ibcon#read 4, iclass 33, count 2 2006.201.09:22:49.83#ibcon#about to read 5, iclass 33, count 2 2006.201.09:22:49.83#ibcon#read 5, iclass 33, count 2 2006.201.09:22:49.83#ibcon#about to read 6, iclass 33, count 2 2006.201.09:22:49.83#ibcon#read 6, iclass 33, count 2 2006.201.09:22:49.83#ibcon#end of sib2, iclass 33, count 2 2006.201.09:22:49.83#ibcon#*after write, iclass 33, count 2 2006.201.09:22:49.83#ibcon#*before return 0, iclass 33, count 2 2006.201.09:22:49.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:49.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:49.83#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.09:22:49.83#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:49.83#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:49.95#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:49.95#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:49.95#ibcon#enter wrdev, iclass 33, count 0 2006.201.09:22:49.95#ibcon#first serial, iclass 33, count 0 2006.201.09:22:49.95#ibcon#enter sib2, iclass 33, count 0 2006.201.09:22:49.95#ibcon#flushed, iclass 33, count 0 2006.201.09:22:49.95#ibcon#about to write, iclass 33, count 0 2006.201.09:22:49.95#ibcon#wrote, iclass 33, count 0 2006.201.09:22:49.95#ibcon#about to read 3, iclass 33, count 0 2006.201.09:22:49.97#ibcon#read 3, iclass 33, count 0 2006.201.09:22:49.97#ibcon#about to read 4, iclass 33, count 0 2006.201.09:22:49.97#ibcon#read 4, iclass 33, count 0 2006.201.09:22:49.97#ibcon#about to read 5, iclass 33, count 0 2006.201.09:22:49.97#ibcon#read 5, iclass 33, count 0 2006.201.09:22:49.97#ibcon#about to read 6, iclass 33, count 0 2006.201.09:22:49.97#ibcon#read 6, iclass 33, count 0 2006.201.09:22:49.97#ibcon#end of sib2, iclass 33, count 0 2006.201.09:22:49.97#ibcon#*mode == 0, iclass 33, count 0 2006.201.09:22:49.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.09:22:49.97#ibcon#[25=USB\r\n] 2006.201.09:22:49.97#ibcon#*before write, iclass 33, count 0 2006.201.09:22:49.97#ibcon#enter sib2, iclass 33, count 0 2006.201.09:22:49.97#ibcon#flushed, iclass 33, count 0 2006.201.09:22:49.97#ibcon#about to write, iclass 33, count 0 2006.201.09:22:49.97#ibcon#wrote, iclass 33, count 0 2006.201.09:22:49.97#ibcon#about to read 3, iclass 33, count 0 2006.201.09:22:50.00#ibcon#read 3, iclass 33, count 0 2006.201.09:22:50.00#ibcon#about to read 4, iclass 33, count 0 2006.201.09:22:50.00#ibcon#read 4, iclass 33, count 0 2006.201.09:22:50.00#ibcon#about to read 5, iclass 33, count 0 2006.201.09:22:50.00#ibcon#read 5, iclass 33, count 0 2006.201.09:22:50.00#ibcon#about to read 6, iclass 33, count 0 2006.201.09:22:50.00#ibcon#read 6, iclass 33, count 0 2006.201.09:22:50.00#ibcon#end of sib2, iclass 33, count 0 2006.201.09:22:50.00#ibcon#*after write, iclass 33, count 0 2006.201.09:22:50.00#ibcon#*before return 0, iclass 33, count 0 2006.201.09:22:50.00#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:50.00#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:50.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.09:22:50.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.09:22:50.00$vck44/valo=7,864.99 2006.201.09:22:50.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.09:22:50.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.09:22:50.00#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:50.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:50.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:50.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:50.00#ibcon#enter wrdev, iclass 35, count 0 2006.201.09:22:50.00#ibcon#first serial, iclass 35, count 0 2006.201.09:22:50.00#ibcon#enter sib2, iclass 35, count 0 2006.201.09:22:50.00#ibcon#flushed, iclass 35, count 0 2006.201.09:22:50.00#ibcon#about to write, iclass 35, count 0 2006.201.09:22:50.00#ibcon#wrote, iclass 35, count 0 2006.201.09:22:50.00#ibcon#about to read 3, iclass 35, count 0 2006.201.09:22:50.02#ibcon#read 3, iclass 35, count 0 2006.201.09:22:50.02#ibcon#about to read 4, iclass 35, count 0 2006.201.09:22:50.02#ibcon#read 4, iclass 35, count 0 2006.201.09:22:50.02#ibcon#about to read 5, iclass 35, count 0 2006.201.09:22:50.02#ibcon#read 5, iclass 35, count 0 2006.201.09:22:50.02#ibcon#about to read 6, iclass 35, count 0 2006.201.09:22:50.02#ibcon#read 6, iclass 35, count 0 2006.201.09:22:50.02#ibcon#end of sib2, iclass 35, count 0 2006.201.09:22:50.02#ibcon#*mode == 0, iclass 35, count 0 2006.201.09:22:50.02#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.09:22:50.02#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:22:50.02#ibcon#*before write, iclass 35, count 0 2006.201.09:22:50.02#ibcon#enter sib2, iclass 35, count 0 2006.201.09:22:50.02#ibcon#flushed, iclass 35, count 0 2006.201.09:22:50.02#ibcon#about to write, iclass 35, count 0 2006.201.09:22:50.02#ibcon#wrote, iclass 35, count 0 2006.201.09:22:50.02#ibcon#about to read 3, iclass 35, count 0 2006.201.09:22:50.07#ibcon#read 3, iclass 35, count 0 2006.201.09:22:50.07#ibcon#about to read 4, iclass 35, count 0 2006.201.09:22:50.07#ibcon#read 4, iclass 35, count 0 2006.201.09:22:50.07#ibcon#about to read 5, iclass 35, count 0 2006.201.09:22:50.07#ibcon#read 5, iclass 35, count 0 2006.201.09:22:50.07#ibcon#about to read 6, iclass 35, count 0 2006.201.09:22:50.07#ibcon#read 6, iclass 35, count 0 2006.201.09:22:50.07#ibcon#end of sib2, iclass 35, count 0 2006.201.09:22:50.07#ibcon#*after write, iclass 35, count 0 2006.201.09:22:50.07#ibcon#*before return 0, iclass 35, count 0 2006.201.09:22:50.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:50.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:50.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.09:22:50.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.09:22:50.07$vck44/va=7,5 2006.201.09:22:50.07#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.09:22:50.07#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.09:22:50.07#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:50.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:50.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:50.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:50.12#ibcon#enter wrdev, iclass 37, count 2 2006.201.09:22:50.12#ibcon#first serial, iclass 37, count 2 2006.201.09:22:50.12#ibcon#enter sib2, iclass 37, count 2 2006.201.09:22:50.12#ibcon#flushed, iclass 37, count 2 2006.201.09:22:50.12#ibcon#about to write, iclass 37, count 2 2006.201.09:22:50.12#ibcon#wrote, iclass 37, count 2 2006.201.09:22:50.12#ibcon#about to read 3, iclass 37, count 2 2006.201.09:22:50.14#ibcon#read 3, iclass 37, count 2 2006.201.09:22:50.14#ibcon#about to read 4, iclass 37, count 2 2006.201.09:22:50.14#ibcon#read 4, iclass 37, count 2 2006.201.09:22:50.14#ibcon#about to read 5, iclass 37, count 2 2006.201.09:22:50.14#ibcon#read 5, iclass 37, count 2 2006.201.09:22:50.14#ibcon#about to read 6, iclass 37, count 2 2006.201.09:22:50.14#ibcon#read 6, iclass 37, count 2 2006.201.09:22:50.14#ibcon#end of sib2, iclass 37, count 2 2006.201.09:22:50.14#ibcon#*mode == 0, iclass 37, count 2 2006.201.09:22:50.14#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.09:22:50.14#ibcon#[25=AT07-05\r\n] 2006.201.09:22:50.14#ibcon#*before write, iclass 37, count 2 2006.201.09:22:50.14#ibcon#enter sib2, iclass 37, count 2 2006.201.09:22:50.14#ibcon#flushed, iclass 37, count 2 2006.201.09:22:50.14#ibcon#about to write, iclass 37, count 2 2006.201.09:22:50.14#ibcon#wrote, iclass 37, count 2 2006.201.09:22:50.14#ibcon#about to read 3, iclass 37, count 2 2006.201.09:22:50.17#ibcon#read 3, iclass 37, count 2 2006.201.09:22:50.17#ibcon#about to read 4, iclass 37, count 2 2006.201.09:22:50.17#ibcon#read 4, iclass 37, count 2 2006.201.09:22:50.17#ibcon#about to read 5, iclass 37, count 2 2006.201.09:22:50.17#ibcon#read 5, iclass 37, count 2 2006.201.09:22:50.17#ibcon#about to read 6, iclass 37, count 2 2006.201.09:22:50.17#ibcon#read 6, iclass 37, count 2 2006.201.09:22:50.17#ibcon#end of sib2, iclass 37, count 2 2006.201.09:22:50.17#ibcon#*after write, iclass 37, count 2 2006.201.09:22:50.17#ibcon#*before return 0, iclass 37, count 2 2006.201.09:22:50.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:50.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:50.17#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.09:22:50.17#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:50.17#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:50.29#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:50.29#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:50.29#ibcon#enter wrdev, iclass 37, count 0 2006.201.09:22:50.29#ibcon#first serial, iclass 37, count 0 2006.201.09:22:50.29#ibcon#enter sib2, iclass 37, count 0 2006.201.09:22:50.29#ibcon#flushed, iclass 37, count 0 2006.201.09:22:50.29#ibcon#about to write, iclass 37, count 0 2006.201.09:22:50.29#ibcon#wrote, iclass 37, count 0 2006.201.09:22:50.29#ibcon#about to read 3, iclass 37, count 0 2006.201.09:22:50.31#ibcon#read 3, iclass 37, count 0 2006.201.09:22:50.31#ibcon#about to read 4, iclass 37, count 0 2006.201.09:22:50.31#ibcon#read 4, iclass 37, count 0 2006.201.09:22:50.31#ibcon#about to read 5, iclass 37, count 0 2006.201.09:22:50.31#ibcon#read 5, iclass 37, count 0 2006.201.09:22:50.31#ibcon#about to read 6, iclass 37, count 0 2006.201.09:22:50.31#ibcon#read 6, iclass 37, count 0 2006.201.09:22:50.31#ibcon#end of sib2, iclass 37, count 0 2006.201.09:22:50.31#ibcon#*mode == 0, iclass 37, count 0 2006.201.09:22:50.31#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.09:22:50.31#ibcon#[25=USB\r\n] 2006.201.09:22:50.31#ibcon#*before write, iclass 37, count 0 2006.201.09:22:50.31#ibcon#enter sib2, iclass 37, count 0 2006.201.09:22:50.31#ibcon#flushed, iclass 37, count 0 2006.201.09:22:50.31#ibcon#about to write, iclass 37, count 0 2006.201.09:22:50.31#ibcon#wrote, iclass 37, count 0 2006.201.09:22:50.31#ibcon#about to read 3, iclass 37, count 0 2006.201.09:22:50.34#ibcon#read 3, iclass 37, count 0 2006.201.09:22:50.34#ibcon#about to read 4, iclass 37, count 0 2006.201.09:22:50.34#ibcon#read 4, iclass 37, count 0 2006.201.09:22:50.34#ibcon#about to read 5, iclass 37, count 0 2006.201.09:22:50.34#ibcon#read 5, iclass 37, count 0 2006.201.09:22:50.34#ibcon#about to read 6, iclass 37, count 0 2006.201.09:22:50.34#ibcon#read 6, iclass 37, count 0 2006.201.09:22:50.34#ibcon#end of sib2, iclass 37, count 0 2006.201.09:22:50.34#ibcon#*after write, iclass 37, count 0 2006.201.09:22:50.34#ibcon#*before return 0, iclass 37, count 0 2006.201.09:22:50.34#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:50.34#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:50.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.09:22:50.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.09:22:50.34$vck44/valo=8,884.99 2006.201.09:22:50.34#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.09:22:50.34#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.09:22:50.34#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:50.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:50.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:50.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:50.34#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:22:50.34#ibcon#first serial, iclass 39, count 0 2006.201.09:22:50.34#ibcon#enter sib2, iclass 39, count 0 2006.201.09:22:50.34#ibcon#flushed, iclass 39, count 0 2006.201.09:22:50.34#ibcon#about to write, iclass 39, count 0 2006.201.09:22:50.34#ibcon#wrote, iclass 39, count 0 2006.201.09:22:50.34#ibcon#about to read 3, iclass 39, count 0 2006.201.09:22:50.36#ibcon#read 3, iclass 39, count 0 2006.201.09:22:50.36#ibcon#about to read 4, iclass 39, count 0 2006.201.09:22:50.36#ibcon#read 4, iclass 39, count 0 2006.201.09:22:50.36#ibcon#about to read 5, iclass 39, count 0 2006.201.09:22:50.36#ibcon#read 5, iclass 39, count 0 2006.201.09:22:50.36#ibcon#about to read 6, iclass 39, count 0 2006.201.09:22:50.36#ibcon#read 6, iclass 39, count 0 2006.201.09:22:50.36#ibcon#end of sib2, iclass 39, count 0 2006.201.09:22:50.36#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:22:50.36#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:22:50.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:22:50.36#ibcon#*before write, iclass 39, count 0 2006.201.09:22:50.36#ibcon#enter sib2, iclass 39, count 0 2006.201.09:22:50.36#ibcon#flushed, iclass 39, count 0 2006.201.09:22:50.36#ibcon#about to write, iclass 39, count 0 2006.201.09:22:50.36#ibcon#wrote, iclass 39, count 0 2006.201.09:22:50.36#ibcon#about to read 3, iclass 39, count 0 2006.201.09:22:50.40#ibcon#read 3, iclass 39, count 0 2006.201.09:22:50.40#ibcon#about to read 4, iclass 39, count 0 2006.201.09:22:50.40#ibcon#read 4, iclass 39, count 0 2006.201.09:22:50.40#ibcon#about to read 5, iclass 39, count 0 2006.201.09:22:50.40#ibcon#read 5, iclass 39, count 0 2006.201.09:22:50.40#ibcon#about to read 6, iclass 39, count 0 2006.201.09:22:50.40#ibcon#read 6, iclass 39, count 0 2006.201.09:22:50.40#ibcon#end of sib2, iclass 39, count 0 2006.201.09:22:50.40#ibcon#*after write, iclass 39, count 0 2006.201.09:22:50.40#ibcon#*before return 0, iclass 39, count 0 2006.201.09:22:50.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:50.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:50.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:22:50.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:22:50.40$vck44/va=8,4 2006.201.09:22:50.40#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.09:22:50.40#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.09:22:50.40#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:50.40#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:22:50.46#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:22:50.46#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:22:50.46#ibcon#enter wrdev, iclass 2, count 2 2006.201.09:22:50.46#ibcon#first serial, iclass 2, count 2 2006.201.09:22:50.46#ibcon#enter sib2, iclass 2, count 2 2006.201.09:22:50.46#ibcon#flushed, iclass 2, count 2 2006.201.09:22:50.46#ibcon#about to write, iclass 2, count 2 2006.201.09:22:50.46#ibcon#wrote, iclass 2, count 2 2006.201.09:22:50.46#ibcon#about to read 3, iclass 2, count 2 2006.201.09:22:50.48#ibcon#read 3, iclass 2, count 2 2006.201.09:22:50.48#ibcon#about to read 4, iclass 2, count 2 2006.201.09:22:50.48#ibcon#read 4, iclass 2, count 2 2006.201.09:22:50.48#ibcon#about to read 5, iclass 2, count 2 2006.201.09:22:50.48#ibcon#read 5, iclass 2, count 2 2006.201.09:22:50.48#ibcon#about to read 6, iclass 2, count 2 2006.201.09:22:50.48#ibcon#read 6, iclass 2, count 2 2006.201.09:22:50.48#ibcon#end of sib2, iclass 2, count 2 2006.201.09:22:50.48#ibcon#*mode == 0, iclass 2, count 2 2006.201.09:22:50.48#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.09:22:50.48#ibcon#[25=AT08-04\r\n] 2006.201.09:22:50.48#ibcon#*before write, iclass 2, count 2 2006.201.09:22:50.48#ibcon#enter sib2, iclass 2, count 2 2006.201.09:22:50.48#ibcon#flushed, iclass 2, count 2 2006.201.09:22:50.48#ibcon#about to write, iclass 2, count 2 2006.201.09:22:50.48#ibcon#wrote, iclass 2, count 2 2006.201.09:22:50.48#ibcon#about to read 3, iclass 2, count 2 2006.201.09:22:50.51#ibcon#read 3, iclass 2, count 2 2006.201.09:22:50.51#ibcon#about to read 4, iclass 2, count 2 2006.201.09:22:50.51#ibcon#read 4, iclass 2, count 2 2006.201.09:22:50.51#ibcon#about to read 5, iclass 2, count 2 2006.201.09:22:50.51#ibcon#read 5, iclass 2, count 2 2006.201.09:22:50.51#ibcon#about to read 6, iclass 2, count 2 2006.201.09:22:50.51#ibcon#read 6, iclass 2, count 2 2006.201.09:22:50.51#ibcon#end of sib2, iclass 2, count 2 2006.201.09:22:50.51#ibcon#*after write, iclass 2, count 2 2006.201.09:22:50.51#ibcon#*before return 0, iclass 2, count 2 2006.201.09:22:50.51#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:22:50.51#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.09:22:50.51#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.09:22:50.51#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:50.51#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:22:50.63#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:22:50.63#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:22:50.63#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:22:50.63#ibcon#first serial, iclass 2, count 0 2006.201.09:22:50.63#ibcon#enter sib2, iclass 2, count 0 2006.201.09:22:50.63#ibcon#flushed, iclass 2, count 0 2006.201.09:22:50.63#ibcon#about to write, iclass 2, count 0 2006.201.09:22:50.63#ibcon#wrote, iclass 2, count 0 2006.201.09:22:50.63#ibcon#about to read 3, iclass 2, count 0 2006.201.09:22:50.65#ibcon#read 3, iclass 2, count 0 2006.201.09:22:50.65#ibcon#about to read 4, iclass 2, count 0 2006.201.09:22:50.65#ibcon#read 4, iclass 2, count 0 2006.201.09:22:50.65#ibcon#about to read 5, iclass 2, count 0 2006.201.09:22:50.65#ibcon#read 5, iclass 2, count 0 2006.201.09:22:50.65#ibcon#about to read 6, iclass 2, count 0 2006.201.09:22:50.65#ibcon#read 6, iclass 2, count 0 2006.201.09:22:50.65#ibcon#end of sib2, iclass 2, count 0 2006.201.09:22:50.65#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:22:50.65#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:22:50.65#ibcon#[25=USB\r\n] 2006.201.09:22:50.65#ibcon#*before write, iclass 2, count 0 2006.201.09:22:50.65#ibcon#enter sib2, iclass 2, count 0 2006.201.09:22:50.65#ibcon#flushed, iclass 2, count 0 2006.201.09:22:50.65#ibcon#about to write, iclass 2, count 0 2006.201.09:22:50.65#ibcon#wrote, iclass 2, count 0 2006.201.09:22:50.65#ibcon#about to read 3, iclass 2, count 0 2006.201.09:22:50.68#ibcon#read 3, iclass 2, count 0 2006.201.09:22:50.68#ibcon#about to read 4, iclass 2, count 0 2006.201.09:22:50.68#ibcon#read 4, iclass 2, count 0 2006.201.09:22:50.68#ibcon#about to read 5, iclass 2, count 0 2006.201.09:22:50.68#ibcon#read 5, iclass 2, count 0 2006.201.09:22:50.68#ibcon#about to read 6, iclass 2, count 0 2006.201.09:22:50.68#ibcon#read 6, iclass 2, count 0 2006.201.09:22:50.68#ibcon#end of sib2, iclass 2, count 0 2006.201.09:22:50.68#ibcon#*after write, iclass 2, count 0 2006.201.09:22:50.68#ibcon#*before return 0, iclass 2, count 0 2006.201.09:22:50.68#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:22:50.68#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.09:22:50.68#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:22:50.68#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:22:50.68$vck44/vblo=1,629.99 2006.201.09:22:50.68#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.09:22:50.68#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.09:22:50.68#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:50.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:22:50.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:22:50.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:22:50.68#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:22:50.68#ibcon#first serial, iclass 5, count 0 2006.201.09:22:50.68#ibcon#enter sib2, iclass 5, count 0 2006.201.09:22:50.68#ibcon#flushed, iclass 5, count 0 2006.201.09:22:50.68#ibcon#about to write, iclass 5, count 0 2006.201.09:22:50.68#ibcon#wrote, iclass 5, count 0 2006.201.09:22:50.68#ibcon#about to read 3, iclass 5, count 0 2006.201.09:22:50.70#ibcon#read 3, iclass 5, count 0 2006.201.09:22:50.70#ibcon#about to read 4, iclass 5, count 0 2006.201.09:22:50.70#ibcon#read 4, iclass 5, count 0 2006.201.09:22:50.70#ibcon#about to read 5, iclass 5, count 0 2006.201.09:22:50.70#ibcon#read 5, iclass 5, count 0 2006.201.09:22:50.70#ibcon#about to read 6, iclass 5, count 0 2006.201.09:22:50.70#ibcon#read 6, iclass 5, count 0 2006.201.09:22:50.70#ibcon#end of sib2, iclass 5, count 0 2006.201.09:22:50.70#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:22:50.70#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:22:50.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:22:50.70#ibcon#*before write, iclass 5, count 0 2006.201.09:22:50.70#ibcon#enter sib2, iclass 5, count 0 2006.201.09:22:50.70#ibcon#flushed, iclass 5, count 0 2006.201.09:22:50.70#ibcon#about to write, iclass 5, count 0 2006.201.09:22:50.70#ibcon#wrote, iclass 5, count 0 2006.201.09:22:50.70#ibcon#about to read 3, iclass 5, count 0 2006.201.09:22:50.75#ibcon#read 3, iclass 5, count 0 2006.201.09:22:50.75#ibcon#about to read 4, iclass 5, count 0 2006.201.09:22:50.75#ibcon#read 4, iclass 5, count 0 2006.201.09:22:50.75#ibcon#about to read 5, iclass 5, count 0 2006.201.09:22:50.75#ibcon#read 5, iclass 5, count 0 2006.201.09:22:50.75#ibcon#about to read 6, iclass 5, count 0 2006.201.09:22:50.75#ibcon#read 6, iclass 5, count 0 2006.201.09:22:50.75#ibcon#end of sib2, iclass 5, count 0 2006.201.09:22:50.75#ibcon#*after write, iclass 5, count 0 2006.201.09:22:50.75#ibcon#*before return 0, iclass 5, count 0 2006.201.09:22:50.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:22:50.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.09:22:50.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:22:50.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:22:50.75$vck44/vb=1,4 2006.201.09:22:50.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.09:22:50.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.09:22:50.75#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:50.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:22:50.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:22:50.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:22:50.75#ibcon#enter wrdev, iclass 7, count 2 2006.201.09:22:50.75#ibcon#first serial, iclass 7, count 2 2006.201.09:22:50.75#ibcon#enter sib2, iclass 7, count 2 2006.201.09:22:50.75#ibcon#flushed, iclass 7, count 2 2006.201.09:22:50.75#ibcon#about to write, iclass 7, count 2 2006.201.09:22:50.75#ibcon#wrote, iclass 7, count 2 2006.201.09:22:50.75#ibcon#about to read 3, iclass 7, count 2 2006.201.09:22:50.77#ibcon#read 3, iclass 7, count 2 2006.201.09:22:50.77#ibcon#about to read 4, iclass 7, count 2 2006.201.09:22:50.77#ibcon#read 4, iclass 7, count 2 2006.201.09:22:50.77#ibcon#about to read 5, iclass 7, count 2 2006.201.09:22:50.77#ibcon#read 5, iclass 7, count 2 2006.201.09:22:50.77#ibcon#about to read 6, iclass 7, count 2 2006.201.09:22:50.77#ibcon#read 6, iclass 7, count 2 2006.201.09:22:50.77#ibcon#end of sib2, iclass 7, count 2 2006.201.09:22:50.77#ibcon#*mode == 0, iclass 7, count 2 2006.201.09:22:50.77#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.09:22:50.77#ibcon#[27=AT01-04\r\n] 2006.201.09:22:50.77#ibcon#*before write, iclass 7, count 2 2006.201.09:22:50.77#ibcon#enter sib2, iclass 7, count 2 2006.201.09:22:50.77#ibcon#flushed, iclass 7, count 2 2006.201.09:22:50.77#ibcon#about to write, iclass 7, count 2 2006.201.09:22:50.77#ibcon#wrote, iclass 7, count 2 2006.201.09:22:50.77#ibcon#about to read 3, iclass 7, count 2 2006.201.09:22:50.80#ibcon#read 3, iclass 7, count 2 2006.201.09:22:50.80#ibcon#about to read 4, iclass 7, count 2 2006.201.09:22:50.80#ibcon#read 4, iclass 7, count 2 2006.201.09:22:50.80#ibcon#about to read 5, iclass 7, count 2 2006.201.09:22:50.80#ibcon#read 5, iclass 7, count 2 2006.201.09:22:50.80#ibcon#about to read 6, iclass 7, count 2 2006.201.09:22:50.80#ibcon#read 6, iclass 7, count 2 2006.201.09:22:50.80#ibcon#end of sib2, iclass 7, count 2 2006.201.09:22:50.80#ibcon#*after write, iclass 7, count 2 2006.201.09:22:50.80#ibcon#*before return 0, iclass 7, count 2 2006.201.09:22:50.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:22:50.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.09:22:50.80#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.09:22:50.80#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:50.80#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:22:50.92#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:22:50.92#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:22:50.92#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:22:50.92#ibcon#first serial, iclass 7, count 0 2006.201.09:22:50.92#ibcon#enter sib2, iclass 7, count 0 2006.201.09:22:50.92#ibcon#flushed, iclass 7, count 0 2006.201.09:22:50.92#ibcon#about to write, iclass 7, count 0 2006.201.09:22:50.92#ibcon#wrote, iclass 7, count 0 2006.201.09:22:50.92#ibcon#about to read 3, iclass 7, count 0 2006.201.09:22:50.94#ibcon#read 3, iclass 7, count 0 2006.201.09:22:50.94#ibcon#about to read 4, iclass 7, count 0 2006.201.09:22:50.94#ibcon#read 4, iclass 7, count 0 2006.201.09:22:50.94#ibcon#about to read 5, iclass 7, count 0 2006.201.09:22:50.94#ibcon#read 5, iclass 7, count 0 2006.201.09:22:50.94#ibcon#about to read 6, iclass 7, count 0 2006.201.09:22:50.94#ibcon#read 6, iclass 7, count 0 2006.201.09:22:50.94#ibcon#end of sib2, iclass 7, count 0 2006.201.09:22:50.94#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:22:50.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:22:50.94#ibcon#[27=USB\r\n] 2006.201.09:22:50.94#ibcon#*before write, iclass 7, count 0 2006.201.09:22:50.94#ibcon#enter sib2, iclass 7, count 0 2006.201.09:22:50.94#ibcon#flushed, iclass 7, count 0 2006.201.09:22:50.94#ibcon#about to write, iclass 7, count 0 2006.201.09:22:50.94#ibcon#wrote, iclass 7, count 0 2006.201.09:22:50.94#ibcon#about to read 3, iclass 7, count 0 2006.201.09:22:50.97#ibcon#read 3, iclass 7, count 0 2006.201.09:22:50.97#ibcon#about to read 4, iclass 7, count 0 2006.201.09:22:50.97#ibcon#read 4, iclass 7, count 0 2006.201.09:22:50.97#ibcon#about to read 5, iclass 7, count 0 2006.201.09:22:50.97#ibcon#read 5, iclass 7, count 0 2006.201.09:22:50.97#ibcon#about to read 6, iclass 7, count 0 2006.201.09:22:50.97#ibcon#read 6, iclass 7, count 0 2006.201.09:22:50.97#ibcon#end of sib2, iclass 7, count 0 2006.201.09:22:50.97#ibcon#*after write, iclass 7, count 0 2006.201.09:22:50.97#ibcon#*before return 0, iclass 7, count 0 2006.201.09:22:50.97#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:22:50.97#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.09:22:50.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:22:50.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:22:50.97$vck44/vblo=2,634.99 2006.201.09:22:50.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.09:22:50.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.09:22:50.97#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:50.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:50.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:50.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:50.97#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:22:50.97#ibcon#first serial, iclass 11, count 0 2006.201.09:22:50.97#ibcon#enter sib2, iclass 11, count 0 2006.201.09:22:50.97#ibcon#flushed, iclass 11, count 0 2006.201.09:22:50.97#ibcon#about to write, iclass 11, count 0 2006.201.09:22:50.97#ibcon#wrote, iclass 11, count 0 2006.201.09:22:50.97#ibcon#about to read 3, iclass 11, count 0 2006.201.09:22:50.99#ibcon#read 3, iclass 11, count 0 2006.201.09:22:50.99#ibcon#about to read 4, iclass 11, count 0 2006.201.09:22:50.99#ibcon#read 4, iclass 11, count 0 2006.201.09:22:50.99#ibcon#about to read 5, iclass 11, count 0 2006.201.09:22:50.99#ibcon#read 5, iclass 11, count 0 2006.201.09:22:50.99#ibcon#about to read 6, iclass 11, count 0 2006.201.09:22:50.99#ibcon#read 6, iclass 11, count 0 2006.201.09:22:50.99#ibcon#end of sib2, iclass 11, count 0 2006.201.09:22:50.99#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:22:50.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:22:50.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:22:50.99#ibcon#*before write, iclass 11, count 0 2006.201.09:22:50.99#ibcon#enter sib2, iclass 11, count 0 2006.201.09:22:50.99#ibcon#flushed, iclass 11, count 0 2006.201.09:22:50.99#ibcon#about to write, iclass 11, count 0 2006.201.09:22:50.99#ibcon#wrote, iclass 11, count 0 2006.201.09:22:50.99#ibcon#about to read 3, iclass 11, count 0 2006.201.09:22:51.03#ibcon#read 3, iclass 11, count 0 2006.201.09:22:51.03#ibcon#about to read 4, iclass 11, count 0 2006.201.09:22:51.03#ibcon#read 4, iclass 11, count 0 2006.201.09:22:51.03#ibcon#about to read 5, iclass 11, count 0 2006.201.09:22:51.03#ibcon#read 5, iclass 11, count 0 2006.201.09:22:51.03#ibcon#about to read 6, iclass 11, count 0 2006.201.09:22:51.03#ibcon#read 6, iclass 11, count 0 2006.201.09:22:51.03#ibcon#end of sib2, iclass 11, count 0 2006.201.09:22:51.03#ibcon#*after write, iclass 11, count 0 2006.201.09:22:51.03#ibcon#*before return 0, iclass 11, count 0 2006.201.09:22:51.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:51.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.09:22:51.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:22:51.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:22:51.03$vck44/vb=2,5 2006.201.09:22:51.03#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.09:22:51.03#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.09:22:51.03#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:51.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:51.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:51.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:51.09#ibcon#enter wrdev, iclass 13, count 2 2006.201.09:22:51.09#ibcon#first serial, iclass 13, count 2 2006.201.09:22:51.09#ibcon#enter sib2, iclass 13, count 2 2006.201.09:22:51.09#ibcon#flushed, iclass 13, count 2 2006.201.09:22:51.09#ibcon#about to write, iclass 13, count 2 2006.201.09:22:51.09#ibcon#wrote, iclass 13, count 2 2006.201.09:22:51.09#ibcon#about to read 3, iclass 13, count 2 2006.201.09:22:51.11#ibcon#read 3, iclass 13, count 2 2006.201.09:22:51.11#ibcon#about to read 4, iclass 13, count 2 2006.201.09:22:51.11#ibcon#read 4, iclass 13, count 2 2006.201.09:22:51.11#ibcon#about to read 5, iclass 13, count 2 2006.201.09:22:51.11#ibcon#read 5, iclass 13, count 2 2006.201.09:22:51.11#ibcon#about to read 6, iclass 13, count 2 2006.201.09:22:51.11#ibcon#read 6, iclass 13, count 2 2006.201.09:22:51.11#ibcon#end of sib2, iclass 13, count 2 2006.201.09:22:51.11#ibcon#*mode == 0, iclass 13, count 2 2006.201.09:22:51.11#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.09:22:51.11#ibcon#[27=AT02-05\r\n] 2006.201.09:22:51.11#ibcon#*before write, iclass 13, count 2 2006.201.09:22:51.11#ibcon#enter sib2, iclass 13, count 2 2006.201.09:22:51.11#ibcon#flushed, iclass 13, count 2 2006.201.09:22:51.11#ibcon#about to write, iclass 13, count 2 2006.201.09:22:51.11#ibcon#wrote, iclass 13, count 2 2006.201.09:22:51.11#ibcon#about to read 3, iclass 13, count 2 2006.201.09:22:51.14#ibcon#read 3, iclass 13, count 2 2006.201.09:22:51.14#ibcon#about to read 4, iclass 13, count 2 2006.201.09:22:51.14#ibcon#read 4, iclass 13, count 2 2006.201.09:22:51.14#ibcon#about to read 5, iclass 13, count 2 2006.201.09:22:51.14#ibcon#read 5, iclass 13, count 2 2006.201.09:22:51.14#ibcon#about to read 6, iclass 13, count 2 2006.201.09:22:51.14#ibcon#read 6, iclass 13, count 2 2006.201.09:22:51.14#ibcon#end of sib2, iclass 13, count 2 2006.201.09:22:51.14#ibcon#*after write, iclass 13, count 2 2006.201.09:22:51.14#ibcon#*before return 0, iclass 13, count 2 2006.201.09:22:51.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:51.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.09:22:51.14#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.09:22:51.14#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:51.14#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:51.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:51.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:51.26#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:22:51.26#ibcon#first serial, iclass 13, count 0 2006.201.09:22:51.26#ibcon#enter sib2, iclass 13, count 0 2006.201.09:22:51.26#ibcon#flushed, iclass 13, count 0 2006.201.09:22:51.26#ibcon#about to write, iclass 13, count 0 2006.201.09:22:51.26#ibcon#wrote, iclass 13, count 0 2006.201.09:22:51.26#ibcon#about to read 3, iclass 13, count 0 2006.201.09:22:51.28#ibcon#read 3, iclass 13, count 0 2006.201.09:22:51.28#ibcon#about to read 4, iclass 13, count 0 2006.201.09:22:51.28#ibcon#read 4, iclass 13, count 0 2006.201.09:22:51.28#ibcon#about to read 5, iclass 13, count 0 2006.201.09:22:51.28#ibcon#read 5, iclass 13, count 0 2006.201.09:22:51.28#ibcon#about to read 6, iclass 13, count 0 2006.201.09:22:51.28#ibcon#read 6, iclass 13, count 0 2006.201.09:22:51.28#ibcon#end of sib2, iclass 13, count 0 2006.201.09:22:51.28#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:22:51.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:22:51.28#ibcon#[27=USB\r\n] 2006.201.09:22:51.28#ibcon#*before write, iclass 13, count 0 2006.201.09:22:51.28#ibcon#enter sib2, iclass 13, count 0 2006.201.09:22:51.28#ibcon#flushed, iclass 13, count 0 2006.201.09:22:51.28#ibcon#about to write, iclass 13, count 0 2006.201.09:22:51.28#ibcon#wrote, iclass 13, count 0 2006.201.09:22:51.28#ibcon#about to read 3, iclass 13, count 0 2006.201.09:22:51.31#ibcon#read 3, iclass 13, count 0 2006.201.09:22:51.31#ibcon#about to read 4, iclass 13, count 0 2006.201.09:22:51.31#ibcon#read 4, iclass 13, count 0 2006.201.09:22:51.31#ibcon#about to read 5, iclass 13, count 0 2006.201.09:22:51.31#ibcon#read 5, iclass 13, count 0 2006.201.09:22:51.31#ibcon#about to read 6, iclass 13, count 0 2006.201.09:22:51.31#ibcon#read 6, iclass 13, count 0 2006.201.09:22:51.31#ibcon#end of sib2, iclass 13, count 0 2006.201.09:22:51.31#ibcon#*after write, iclass 13, count 0 2006.201.09:22:51.31#ibcon#*before return 0, iclass 13, count 0 2006.201.09:22:51.31#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:51.31#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.09:22:51.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:22:51.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:22:51.31$vck44/vblo=3,649.99 2006.201.09:22:51.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.09:22:51.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.09:22:51.31#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:51.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:51.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:51.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:51.31#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:22:51.31#ibcon#first serial, iclass 15, count 0 2006.201.09:22:51.31#ibcon#enter sib2, iclass 15, count 0 2006.201.09:22:51.31#ibcon#flushed, iclass 15, count 0 2006.201.09:22:51.31#ibcon#about to write, iclass 15, count 0 2006.201.09:22:51.31#ibcon#wrote, iclass 15, count 0 2006.201.09:22:51.31#ibcon#about to read 3, iclass 15, count 0 2006.201.09:22:51.33#ibcon#read 3, iclass 15, count 0 2006.201.09:22:51.33#ibcon#about to read 4, iclass 15, count 0 2006.201.09:22:51.33#ibcon#read 4, iclass 15, count 0 2006.201.09:22:51.33#ibcon#about to read 5, iclass 15, count 0 2006.201.09:22:51.33#ibcon#read 5, iclass 15, count 0 2006.201.09:22:51.33#ibcon#about to read 6, iclass 15, count 0 2006.201.09:22:51.33#ibcon#read 6, iclass 15, count 0 2006.201.09:22:51.33#ibcon#end of sib2, iclass 15, count 0 2006.201.09:22:51.33#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:22:51.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:22:51.33#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:22:51.33#ibcon#*before write, iclass 15, count 0 2006.201.09:22:51.33#ibcon#enter sib2, iclass 15, count 0 2006.201.09:22:51.33#ibcon#flushed, iclass 15, count 0 2006.201.09:22:51.33#ibcon#about to write, iclass 15, count 0 2006.201.09:22:51.33#ibcon#wrote, iclass 15, count 0 2006.201.09:22:51.33#ibcon#about to read 3, iclass 15, count 0 2006.201.09:22:51.37#ibcon#read 3, iclass 15, count 0 2006.201.09:22:51.37#ibcon#about to read 4, iclass 15, count 0 2006.201.09:22:51.37#ibcon#read 4, iclass 15, count 0 2006.201.09:22:51.37#ibcon#about to read 5, iclass 15, count 0 2006.201.09:22:51.37#ibcon#read 5, iclass 15, count 0 2006.201.09:22:51.37#ibcon#about to read 6, iclass 15, count 0 2006.201.09:22:51.37#ibcon#read 6, iclass 15, count 0 2006.201.09:22:51.37#ibcon#end of sib2, iclass 15, count 0 2006.201.09:22:51.37#ibcon#*after write, iclass 15, count 0 2006.201.09:22:51.37#ibcon#*before return 0, iclass 15, count 0 2006.201.09:22:51.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:51.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.09:22:51.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:22:51.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:22:51.37$vck44/vb=3,4 2006.201.09:22:51.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.09:22:51.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.09:22:51.37#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:51.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:51.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:51.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:51.43#ibcon#enter wrdev, iclass 17, count 2 2006.201.09:22:51.43#ibcon#first serial, iclass 17, count 2 2006.201.09:22:51.43#ibcon#enter sib2, iclass 17, count 2 2006.201.09:22:51.43#ibcon#flushed, iclass 17, count 2 2006.201.09:22:51.43#ibcon#about to write, iclass 17, count 2 2006.201.09:22:51.43#ibcon#wrote, iclass 17, count 2 2006.201.09:22:51.43#ibcon#about to read 3, iclass 17, count 2 2006.201.09:22:51.45#ibcon#read 3, iclass 17, count 2 2006.201.09:22:51.45#ibcon#about to read 4, iclass 17, count 2 2006.201.09:22:51.45#ibcon#read 4, iclass 17, count 2 2006.201.09:22:51.45#ibcon#about to read 5, iclass 17, count 2 2006.201.09:22:51.45#ibcon#read 5, iclass 17, count 2 2006.201.09:22:51.45#ibcon#about to read 6, iclass 17, count 2 2006.201.09:22:51.45#ibcon#read 6, iclass 17, count 2 2006.201.09:22:51.45#ibcon#end of sib2, iclass 17, count 2 2006.201.09:22:51.45#ibcon#*mode == 0, iclass 17, count 2 2006.201.09:22:51.45#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.09:22:51.45#ibcon#[27=AT03-04\r\n] 2006.201.09:22:51.45#ibcon#*before write, iclass 17, count 2 2006.201.09:22:51.45#ibcon#enter sib2, iclass 17, count 2 2006.201.09:22:51.45#ibcon#flushed, iclass 17, count 2 2006.201.09:22:51.45#ibcon#about to write, iclass 17, count 2 2006.201.09:22:51.45#ibcon#wrote, iclass 17, count 2 2006.201.09:22:51.45#ibcon#about to read 3, iclass 17, count 2 2006.201.09:22:51.48#ibcon#read 3, iclass 17, count 2 2006.201.09:22:51.48#ibcon#about to read 4, iclass 17, count 2 2006.201.09:22:51.48#ibcon#read 4, iclass 17, count 2 2006.201.09:22:51.48#ibcon#about to read 5, iclass 17, count 2 2006.201.09:22:51.48#ibcon#read 5, iclass 17, count 2 2006.201.09:22:51.48#ibcon#about to read 6, iclass 17, count 2 2006.201.09:22:51.48#ibcon#read 6, iclass 17, count 2 2006.201.09:22:51.48#ibcon#end of sib2, iclass 17, count 2 2006.201.09:22:51.48#ibcon#*after write, iclass 17, count 2 2006.201.09:22:51.48#ibcon#*before return 0, iclass 17, count 2 2006.201.09:22:51.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:51.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.09:22:51.48#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.09:22:51.48#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:51.48#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:51.60#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:51.60#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:51.60#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:22:51.60#ibcon#first serial, iclass 17, count 0 2006.201.09:22:51.60#ibcon#enter sib2, iclass 17, count 0 2006.201.09:22:51.60#ibcon#flushed, iclass 17, count 0 2006.201.09:22:51.60#ibcon#about to write, iclass 17, count 0 2006.201.09:22:51.60#ibcon#wrote, iclass 17, count 0 2006.201.09:22:51.60#ibcon#about to read 3, iclass 17, count 0 2006.201.09:22:51.62#ibcon#read 3, iclass 17, count 0 2006.201.09:22:51.62#ibcon#about to read 4, iclass 17, count 0 2006.201.09:22:51.62#ibcon#read 4, iclass 17, count 0 2006.201.09:22:51.62#ibcon#about to read 5, iclass 17, count 0 2006.201.09:22:51.62#ibcon#read 5, iclass 17, count 0 2006.201.09:22:51.62#ibcon#about to read 6, iclass 17, count 0 2006.201.09:22:51.62#ibcon#read 6, iclass 17, count 0 2006.201.09:22:51.62#ibcon#end of sib2, iclass 17, count 0 2006.201.09:22:51.62#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:22:51.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:22:51.62#ibcon#[27=USB\r\n] 2006.201.09:22:51.62#ibcon#*before write, iclass 17, count 0 2006.201.09:22:51.62#ibcon#enter sib2, iclass 17, count 0 2006.201.09:22:51.62#ibcon#flushed, iclass 17, count 0 2006.201.09:22:51.62#ibcon#about to write, iclass 17, count 0 2006.201.09:22:51.62#ibcon#wrote, iclass 17, count 0 2006.201.09:22:51.62#ibcon#about to read 3, iclass 17, count 0 2006.201.09:22:51.65#ibcon#read 3, iclass 17, count 0 2006.201.09:22:51.65#ibcon#about to read 4, iclass 17, count 0 2006.201.09:22:51.65#ibcon#read 4, iclass 17, count 0 2006.201.09:22:51.65#ibcon#about to read 5, iclass 17, count 0 2006.201.09:22:51.65#ibcon#read 5, iclass 17, count 0 2006.201.09:22:51.65#ibcon#about to read 6, iclass 17, count 0 2006.201.09:22:51.65#ibcon#read 6, iclass 17, count 0 2006.201.09:22:51.65#ibcon#end of sib2, iclass 17, count 0 2006.201.09:22:51.65#ibcon#*after write, iclass 17, count 0 2006.201.09:22:51.65#ibcon#*before return 0, iclass 17, count 0 2006.201.09:22:51.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:51.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.09:22:51.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:22:51.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:22:51.65$vck44/vblo=4,679.99 2006.201.09:22:51.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.09:22:51.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.09:22:51.65#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:51.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:51.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:51.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:51.65#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:22:51.65#ibcon#first serial, iclass 19, count 0 2006.201.09:22:51.65#ibcon#enter sib2, iclass 19, count 0 2006.201.09:22:51.65#ibcon#flushed, iclass 19, count 0 2006.201.09:22:51.65#ibcon#about to write, iclass 19, count 0 2006.201.09:22:51.65#ibcon#wrote, iclass 19, count 0 2006.201.09:22:51.65#ibcon#about to read 3, iclass 19, count 0 2006.201.09:22:51.67#ibcon#read 3, iclass 19, count 0 2006.201.09:22:51.67#ibcon#about to read 4, iclass 19, count 0 2006.201.09:22:51.67#ibcon#read 4, iclass 19, count 0 2006.201.09:22:51.67#ibcon#about to read 5, iclass 19, count 0 2006.201.09:22:51.67#ibcon#read 5, iclass 19, count 0 2006.201.09:22:51.67#ibcon#about to read 6, iclass 19, count 0 2006.201.09:22:51.67#ibcon#read 6, iclass 19, count 0 2006.201.09:22:51.67#ibcon#end of sib2, iclass 19, count 0 2006.201.09:22:51.67#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:22:51.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:22:51.67#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:22:51.67#ibcon#*before write, iclass 19, count 0 2006.201.09:22:51.67#ibcon#enter sib2, iclass 19, count 0 2006.201.09:22:51.67#ibcon#flushed, iclass 19, count 0 2006.201.09:22:51.67#ibcon#about to write, iclass 19, count 0 2006.201.09:22:51.67#ibcon#wrote, iclass 19, count 0 2006.201.09:22:51.67#ibcon#about to read 3, iclass 19, count 0 2006.201.09:22:51.72#ibcon#read 3, iclass 19, count 0 2006.201.09:22:51.72#ibcon#about to read 4, iclass 19, count 0 2006.201.09:22:51.72#ibcon#read 4, iclass 19, count 0 2006.201.09:22:51.72#ibcon#about to read 5, iclass 19, count 0 2006.201.09:22:51.72#ibcon#read 5, iclass 19, count 0 2006.201.09:22:51.72#ibcon#about to read 6, iclass 19, count 0 2006.201.09:22:51.72#ibcon#read 6, iclass 19, count 0 2006.201.09:22:51.72#ibcon#end of sib2, iclass 19, count 0 2006.201.09:22:51.72#ibcon#*after write, iclass 19, count 0 2006.201.09:22:51.72#ibcon#*before return 0, iclass 19, count 0 2006.201.09:22:51.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:51.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.09:22:51.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:22:51.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:22:51.72$vck44/vb=4,5 2006.201.09:22:51.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.09:22:51.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.09:22:51.72#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:51.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:51.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:51.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:51.77#ibcon#enter wrdev, iclass 21, count 2 2006.201.09:22:51.77#ibcon#first serial, iclass 21, count 2 2006.201.09:22:51.77#ibcon#enter sib2, iclass 21, count 2 2006.201.09:22:51.77#ibcon#flushed, iclass 21, count 2 2006.201.09:22:51.77#ibcon#about to write, iclass 21, count 2 2006.201.09:22:51.77#ibcon#wrote, iclass 21, count 2 2006.201.09:22:51.77#ibcon#about to read 3, iclass 21, count 2 2006.201.09:22:51.79#ibcon#read 3, iclass 21, count 2 2006.201.09:22:51.79#ibcon#about to read 4, iclass 21, count 2 2006.201.09:22:51.79#ibcon#read 4, iclass 21, count 2 2006.201.09:22:51.79#ibcon#about to read 5, iclass 21, count 2 2006.201.09:22:51.79#ibcon#read 5, iclass 21, count 2 2006.201.09:22:51.79#ibcon#about to read 6, iclass 21, count 2 2006.201.09:22:51.79#ibcon#read 6, iclass 21, count 2 2006.201.09:22:51.79#ibcon#end of sib2, iclass 21, count 2 2006.201.09:22:51.79#ibcon#*mode == 0, iclass 21, count 2 2006.201.09:22:51.79#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.09:22:51.79#ibcon#[27=AT04-05\r\n] 2006.201.09:22:51.79#ibcon#*before write, iclass 21, count 2 2006.201.09:22:51.79#ibcon#enter sib2, iclass 21, count 2 2006.201.09:22:51.79#ibcon#flushed, iclass 21, count 2 2006.201.09:22:51.79#ibcon#about to write, iclass 21, count 2 2006.201.09:22:51.79#ibcon#wrote, iclass 21, count 2 2006.201.09:22:51.79#ibcon#about to read 3, iclass 21, count 2 2006.201.09:22:51.82#ibcon#read 3, iclass 21, count 2 2006.201.09:22:51.82#ibcon#about to read 4, iclass 21, count 2 2006.201.09:22:51.82#ibcon#read 4, iclass 21, count 2 2006.201.09:22:51.82#ibcon#about to read 5, iclass 21, count 2 2006.201.09:22:51.82#ibcon#read 5, iclass 21, count 2 2006.201.09:22:51.82#ibcon#about to read 6, iclass 21, count 2 2006.201.09:22:51.82#ibcon#read 6, iclass 21, count 2 2006.201.09:22:51.82#ibcon#end of sib2, iclass 21, count 2 2006.201.09:22:51.82#ibcon#*after write, iclass 21, count 2 2006.201.09:22:51.82#ibcon#*before return 0, iclass 21, count 2 2006.201.09:22:51.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:51.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.09:22:51.82#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.09:22:51.82#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:51.82#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:51.94#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:51.94#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:51.94#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:22:51.94#ibcon#first serial, iclass 21, count 0 2006.201.09:22:51.94#ibcon#enter sib2, iclass 21, count 0 2006.201.09:22:51.94#ibcon#flushed, iclass 21, count 0 2006.201.09:22:51.94#ibcon#about to write, iclass 21, count 0 2006.201.09:22:51.94#ibcon#wrote, iclass 21, count 0 2006.201.09:22:51.94#ibcon#about to read 3, iclass 21, count 0 2006.201.09:22:51.96#ibcon#read 3, iclass 21, count 0 2006.201.09:22:51.96#ibcon#about to read 4, iclass 21, count 0 2006.201.09:22:51.96#ibcon#read 4, iclass 21, count 0 2006.201.09:22:51.96#ibcon#about to read 5, iclass 21, count 0 2006.201.09:22:51.96#ibcon#read 5, iclass 21, count 0 2006.201.09:22:51.96#ibcon#about to read 6, iclass 21, count 0 2006.201.09:22:51.96#ibcon#read 6, iclass 21, count 0 2006.201.09:22:51.96#ibcon#end of sib2, iclass 21, count 0 2006.201.09:22:51.96#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:22:51.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:22:51.96#ibcon#[27=USB\r\n] 2006.201.09:22:51.96#ibcon#*before write, iclass 21, count 0 2006.201.09:22:51.96#ibcon#enter sib2, iclass 21, count 0 2006.201.09:22:51.96#ibcon#flushed, iclass 21, count 0 2006.201.09:22:51.96#ibcon#about to write, iclass 21, count 0 2006.201.09:22:51.96#ibcon#wrote, iclass 21, count 0 2006.201.09:22:51.96#ibcon#about to read 3, iclass 21, count 0 2006.201.09:22:51.99#ibcon#read 3, iclass 21, count 0 2006.201.09:22:51.99#ibcon#about to read 4, iclass 21, count 0 2006.201.09:22:51.99#ibcon#read 4, iclass 21, count 0 2006.201.09:22:51.99#ibcon#about to read 5, iclass 21, count 0 2006.201.09:22:51.99#ibcon#read 5, iclass 21, count 0 2006.201.09:22:51.99#ibcon#about to read 6, iclass 21, count 0 2006.201.09:22:51.99#ibcon#read 6, iclass 21, count 0 2006.201.09:22:51.99#ibcon#end of sib2, iclass 21, count 0 2006.201.09:22:51.99#ibcon#*after write, iclass 21, count 0 2006.201.09:22:51.99#ibcon#*before return 0, iclass 21, count 0 2006.201.09:22:51.99#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:51.99#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.09:22:51.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:22:51.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:22:51.99$vck44/vblo=5,709.99 2006.201.09:22:51.99#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.09:22:51.99#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.09:22:51.99#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:51.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:51.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:51.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:51.99#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:22:51.99#ibcon#first serial, iclass 23, count 0 2006.201.09:22:51.99#ibcon#enter sib2, iclass 23, count 0 2006.201.09:22:51.99#ibcon#flushed, iclass 23, count 0 2006.201.09:22:51.99#ibcon#about to write, iclass 23, count 0 2006.201.09:22:51.99#ibcon#wrote, iclass 23, count 0 2006.201.09:22:51.99#ibcon#about to read 3, iclass 23, count 0 2006.201.09:22:52.01#ibcon#read 3, iclass 23, count 0 2006.201.09:22:52.01#ibcon#about to read 4, iclass 23, count 0 2006.201.09:22:52.01#ibcon#read 4, iclass 23, count 0 2006.201.09:22:52.01#ibcon#about to read 5, iclass 23, count 0 2006.201.09:22:52.01#ibcon#read 5, iclass 23, count 0 2006.201.09:22:52.01#ibcon#about to read 6, iclass 23, count 0 2006.201.09:22:52.01#ibcon#read 6, iclass 23, count 0 2006.201.09:22:52.01#ibcon#end of sib2, iclass 23, count 0 2006.201.09:22:52.01#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:22:52.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:22:52.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:22:52.01#ibcon#*before write, iclass 23, count 0 2006.201.09:22:52.01#ibcon#enter sib2, iclass 23, count 0 2006.201.09:22:52.01#ibcon#flushed, iclass 23, count 0 2006.201.09:22:52.01#ibcon#about to write, iclass 23, count 0 2006.201.09:22:52.01#ibcon#wrote, iclass 23, count 0 2006.201.09:22:52.01#ibcon#about to read 3, iclass 23, count 0 2006.201.09:22:52.05#ibcon#read 3, iclass 23, count 0 2006.201.09:22:52.05#ibcon#about to read 4, iclass 23, count 0 2006.201.09:22:52.05#ibcon#read 4, iclass 23, count 0 2006.201.09:22:52.05#ibcon#about to read 5, iclass 23, count 0 2006.201.09:22:52.05#ibcon#read 5, iclass 23, count 0 2006.201.09:22:52.05#ibcon#about to read 6, iclass 23, count 0 2006.201.09:22:52.05#ibcon#read 6, iclass 23, count 0 2006.201.09:22:52.05#ibcon#end of sib2, iclass 23, count 0 2006.201.09:22:52.05#ibcon#*after write, iclass 23, count 0 2006.201.09:22:52.05#ibcon#*before return 0, iclass 23, count 0 2006.201.09:22:52.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:52.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.09:22:52.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:22:52.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:22:52.05$vck44/vb=5,4 2006.201.09:22:52.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.09:22:52.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.09:22:52.05#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:52.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:52.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:52.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:52.11#ibcon#enter wrdev, iclass 25, count 2 2006.201.09:22:52.11#ibcon#first serial, iclass 25, count 2 2006.201.09:22:52.11#ibcon#enter sib2, iclass 25, count 2 2006.201.09:22:52.11#ibcon#flushed, iclass 25, count 2 2006.201.09:22:52.11#ibcon#about to write, iclass 25, count 2 2006.201.09:22:52.11#ibcon#wrote, iclass 25, count 2 2006.201.09:22:52.11#ibcon#about to read 3, iclass 25, count 2 2006.201.09:22:52.13#ibcon#read 3, iclass 25, count 2 2006.201.09:22:52.13#ibcon#about to read 4, iclass 25, count 2 2006.201.09:22:52.13#ibcon#read 4, iclass 25, count 2 2006.201.09:22:52.13#ibcon#about to read 5, iclass 25, count 2 2006.201.09:22:52.13#ibcon#read 5, iclass 25, count 2 2006.201.09:22:52.13#ibcon#about to read 6, iclass 25, count 2 2006.201.09:22:52.13#ibcon#read 6, iclass 25, count 2 2006.201.09:22:52.13#ibcon#end of sib2, iclass 25, count 2 2006.201.09:22:52.13#ibcon#*mode == 0, iclass 25, count 2 2006.201.09:22:52.13#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.09:22:52.13#ibcon#[27=AT05-04\r\n] 2006.201.09:22:52.13#ibcon#*before write, iclass 25, count 2 2006.201.09:22:52.13#ibcon#enter sib2, iclass 25, count 2 2006.201.09:22:52.13#ibcon#flushed, iclass 25, count 2 2006.201.09:22:52.13#ibcon#about to write, iclass 25, count 2 2006.201.09:22:52.13#ibcon#wrote, iclass 25, count 2 2006.201.09:22:52.13#ibcon#about to read 3, iclass 25, count 2 2006.201.09:22:52.16#ibcon#read 3, iclass 25, count 2 2006.201.09:22:52.16#ibcon#about to read 4, iclass 25, count 2 2006.201.09:22:52.16#ibcon#read 4, iclass 25, count 2 2006.201.09:22:52.16#ibcon#about to read 5, iclass 25, count 2 2006.201.09:22:52.16#ibcon#read 5, iclass 25, count 2 2006.201.09:22:52.16#ibcon#about to read 6, iclass 25, count 2 2006.201.09:22:52.16#ibcon#read 6, iclass 25, count 2 2006.201.09:22:52.16#ibcon#end of sib2, iclass 25, count 2 2006.201.09:22:52.16#ibcon#*after write, iclass 25, count 2 2006.201.09:22:52.16#ibcon#*before return 0, iclass 25, count 2 2006.201.09:22:52.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:52.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.09:22:52.16#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.09:22:52.16#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:52.16#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:52.28#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:52.28#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:52.28#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:22:52.28#ibcon#first serial, iclass 25, count 0 2006.201.09:22:52.28#ibcon#enter sib2, iclass 25, count 0 2006.201.09:22:52.28#ibcon#flushed, iclass 25, count 0 2006.201.09:22:52.28#ibcon#about to write, iclass 25, count 0 2006.201.09:22:52.28#ibcon#wrote, iclass 25, count 0 2006.201.09:22:52.28#ibcon#about to read 3, iclass 25, count 0 2006.201.09:22:52.30#ibcon#read 3, iclass 25, count 0 2006.201.09:22:52.30#ibcon#about to read 4, iclass 25, count 0 2006.201.09:22:52.30#ibcon#read 4, iclass 25, count 0 2006.201.09:22:52.30#ibcon#about to read 5, iclass 25, count 0 2006.201.09:22:52.30#ibcon#read 5, iclass 25, count 0 2006.201.09:22:52.30#ibcon#about to read 6, iclass 25, count 0 2006.201.09:22:52.30#ibcon#read 6, iclass 25, count 0 2006.201.09:22:52.30#ibcon#end of sib2, iclass 25, count 0 2006.201.09:22:52.30#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:22:52.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:22:52.30#ibcon#[27=USB\r\n] 2006.201.09:22:52.30#ibcon#*before write, iclass 25, count 0 2006.201.09:22:52.30#ibcon#enter sib2, iclass 25, count 0 2006.201.09:22:52.30#ibcon#flushed, iclass 25, count 0 2006.201.09:22:52.30#ibcon#about to write, iclass 25, count 0 2006.201.09:22:52.30#ibcon#wrote, iclass 25, count 0 2006.201.09:22:52.30#ibcon#about to read 3, iclass 25, count 0 2006.201.09:22:52.33#ibcon#read 3, iclass 25, count 0 2006.201.09:22:52.33#ibcon#about to read 4, iclass 25, count 0 2006.201.09:22:52.33#ibcon#read 4, iclass 25, count 0 2006.201.09:22:52.33#ibcon#about to read 5, iclass 25, count 0 2006.201.09:22:52.33#ibcon#read 5, iclass 25, count 0 2006.201.09:22:52.33#ibcon#about to read 6, iclass 25, count 0 2006.201.09:22:52.33#ibcon#read 6, iclass 25, count 0 2006.201.09:22:52.33#ibcon#end of sib2, iclass 25, count 0 2006.201.09:22:52.33#ibcon#*after write, iclass 25, count 0 2006.201.09:22:52.33#ibcon#*before return 0, iclass 25, count 0 2006.201.09:22:52.33#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:52.33#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.09:22:52.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:22:52.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:22:52.33$vck44/vblo=6,719.99 2006.201.09:22:52.33#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.09:22:52.33#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.09:22:52.33#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:52.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:52.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:52.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:52.33#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:22:52.33#ibcon#first serial, iclass 27, count 0 2006.201.09:22:52.33#ibcon#enter sib2, iclass 27, count 0 2006.201.09:22:52.33#ibcon#flushed, iclass 27, count 0 2006.201.09:22:52.33#ibcon#about to write, iclass 27, count 0 2006.201.09:22:52.33#ibcon#wrote, iclass 27, count 0 2006.201.09:22:52.33#ibcon#about to read 3, iclass 27, count 0 2006.201.09:22:52.35#ibcon#read 3, iclass 27, count 0 2006.201.09:22:52.35#ibcon#about to read 4, iclass 27, count 0 2006.201.09:22:52.35#ibcon#read 4, iclass 27, count 0 2006.201.09:22:52.35#ibcon#about to read 5, iclass 27, count 0 2006.201.09:22:52.35#ibcon#read 5, iclass 27, count 0 2006.201.09:22:52.35#ibcon#about to read 6, iclass 27, count 0 2006.201.09:22:52.35#ibcon#read 6, iclass 27, count 0 2006.201.09:22:52.35#ibcon#end of sib2, iclass 27, count 0 2006.201.09:22:52.35#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:22:52.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:22:52.35#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:22:52.35#ibcon#*before write, iclass 27, count 0 2006.201.09:22:52.35#ibcon#enter sib2, iclass 27, count 0 2006.201.09:22:52.35#ibcon#flushed, iclass 27, count 0 2006.201.09:22:52.35#ibcon#about to write, iclass 27, count 0 2006.201.09:22:52.35#ibcon#wrote, iclass 27, count 0 2006.201.09:22:52.35#ibcon#about to read 3, iclass 27, count 0 2006.201.09:22:52.40#ibcon#read 3, iclass 27, count 0 2006.201.09:22:52.40#ibcon#about to read 4, iclass 27, count 0 2006.201.09:22:52.40#ibcon#read 4, iclass 27, count 0 2006.201.09:22:52.40#ibcon#about to read 5, iclass 27, count 0 2006.201.09:22:52.40#ibcon#read 5, iclass 27, count 0 2006.201.09:22:52.40#ibcon#about to read 6, iclass 27, count 0 2006.201.09:22:52.40#ibcon#read 6, iclass 27, count 0 2006.201.09:22:52.40#ibcon#end of sib2, iclass 27, count 0 2006.201.09:22:52.40#ibcon#*after write, iclass 27, count 0 2006.201.09:22:52.40#ibcon#*before return 0, iclass 27, count 0 2006.201.09:22:52.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:52.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.09:22:52.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:22:52.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:22:52.40$vck44/vb=6,4 2006.201.09:22:52.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.09:22:52.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.09:22:52.40#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:52.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:52.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:52.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:52.45#ibcon#enter wrdev, iclass 29, count 2 2006.201.09:22:52.45#ibcon#first serial, iclass 29, count 2 2006.201.09:22:52.45#ibcon#enter sib2, iclass 29, count 2 2006.201.09:22:52.45#ibcon#flushed, iclass 29, count 2 2006.201.09:22:52.45#ibcon#about to write, iclass 29, count 2 2006.201.09:22:52.45#ibcon#wrote, iclass 29, count 2 2006.201.09:22:52.45#ibcon#about to read 3, iclass 29, count 2 2006.201.09:22:52.47#ibcon#read 3, iclass 29, count 2 2006.201.09:22:52.47#ibcon#about to read 4, iclass 29, count 2 2006.201.09:22:52.47#ibcon#read 4, iclass 29, count 2 2006.201.09:22:52.47#ibcon#about to read 5, iclass 29, count 2 2006.201.09:22:52.47#ibcon#read 5, iclass 29, count 2 2006.201.09:22:52.47#ibcon#about to read 6, iclass 29, count 2 2006.201.09:22:52.47#ibcon#read 6, iclass 29, count 2 2006.201.09:22:52.47#ibcon#end of sib2, iclass 29, count 2 2006.201.09:22:52.47#ibcon#*mode == 0, iclass 29, count 2 2006.201.09:22:52.47#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.09:22:52.47#ibcon#[27=AT06-04\r\n] 2006.201.09:22:52.47#ibcon#*before write, iclass 29, count 2 2006.201.09:22:52.47#ibcon#enter sib2, iclass 29, count 2 2006.201.09:22:52.47#ibcon#flushed, iclass 29, count 2 2006.201.09:22:52.47#ibcon#about to write, iclass 29, count 2 2006.201.09:22:52.47#ibcon#wrote, iclass 29, count 2 2006.201.09:22:52.47#ibcon#about to read 3, iclass 29, count 2 2006.201.09:22:52.50#ibcon#read 3, iclass 29, count 2 2006.201.09:22:52.50#ibcon#about to read 4, iclass 29, count 2 2006.201.09:22:52.50#ibcon#read 4, iclass 29, count 2 2006.201.09:22:52.50#ibcon#about to read 5, iclass 29, count 2 2006.201.09:22:52.50#ibcon#read 5, iclass 29, count 2 2006.201.09:22:52.50#ibcon#about to read 6, iclass 29, count 2 2006.201.09:22:52.50#ibcon#read 6, iclass 29, count 2 2006.201.09:22:52.50#ibcon#end of sib2, iclass 29, count 2 2006.201.09:22:52.50#ibcon#*after write, iclass 29, count 2 2006.201.09:22:52.50#ibcon#*before return 0, iclass 29, count 2 2006.201.09:22:52.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:52.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.09:22:52.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.09:22:52.50#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:52.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:52.62#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:52.62#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:52.62#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:22:52.62#ibcon#first serial, iclass 29, count 0 2006.201.09:22:52.62#ibcon#enter sib2, iclass 29, count 0 2006.201.09:22:52.62#ibcon#flushed, iclass 29, count 0 2006.201.09:22:52.62#ibcon#about to write, iclass 29, count 0 2006.201.09:22:52.62#ibcon#wrote, iclass 29, count 0 2006.201.09:22:52.62#ibcon#about to read 3, iclass 29, count 0 2006.201.09:22:52.64#ibcon#read 3, iclass 29, count 0 2006.201.09:22:52.64#ibcon#about to read 4, iclass 29, count 0 2006.201.09:22:52.64#ibcon#read 4, iclass 29, count 0 2006.201.09:22:52.64#ibcon#about to read 5, iclass 29, count 0 2006.201.09:22:52.64#ibcon#read 5, iclass 29, count 0 2006.201.09:22:52.64#ibcon#about to read 6, iclass 29, count 0 2006.201.09:22:52.64#ibcon#read 6, iclass 29, count 0 2006.201.09:22:52.64#ibcon#end of sib2, iclass 29, count 0 2006.201.09:22:52.64#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:22:52.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:22:52.64#ibcon#[27=USB\r\n] 2006.201.09:22:52.64#ibcon#*before write, iclass 29, count 0 2006.201.09:22:52.64#ibcon#enter sib2, iclass 29, count 0 2006.201.09:22:52.64#ibcon#flushed, iclass 29, count 0 2006.201.09:22:52.64#ibcon#about to write, iclass 29, count 0 2006.201.09:22:52.64#ibcon#wrote, iclass 29, count 0 2006.201.09:22:52.64#ibcon#about to read 3, iclass 29, count 0 2006.201.09:22:52.67#ibcon#read 3, iclass 29, count 0 2006.201.09:22:52.67#ibcon#about to read 4, iclass 29, count 0 2006.201.09:22:52.67#ibcon#read 4, iclass 29, count 0 2006.201.09:22:52.67#ibcon#about to read 5, iclass 29, count 0 2006.201.09:22:52.67#ibcon#read 5, iclass 29, count 0 2006.201.09:22:52.67#ibcon#about to read 6, iclass 29, count 0 2006.201.09:22:52.67#ibcon#read 6, iclass 29, count 0 2006.201.09:22:52.67#ibcon#end of sib2, iclass 29, count 0 2006.201.09:22:52.67#ibcon#*after write, iclass 29, count 0 2006.201.09:22:52.67#ibcon#*before return 0, iclass 29, count 0 2006.201.09:22:52.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:52.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.09:22:52.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:22:52.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:22:52.67$vck44/vblo=7,734.99 2006.201.09:22:52.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.09:22:52.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.09:22:52.67#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:52.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:52.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:52.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:52.67#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:22:52.67#ibcon#first serial, iclass 31, count 0 2006.201.09:22:52.67#ibcon#enter sib2, iclass 31, count 0 2006.201.09:22:52.67#ibcon#flushed, iclass 31, count 0 2006.201.09:22:52.67#ibcon#about to write, iclass 31, count 0 2006.201.09:22:52.67#ibcon#wrote, iclass 31, count 0 2006.201.09:22:52.67#ibcon#about to read 3, iclass 31, count 0 2006.201.09:22:52.69#ibcon#read 3, iclass 31, count 0 2006.201.09:22:52.69#ibcon#about to read 4, iclass 31, count 0 2006.201.09:22:52.69#ibcon#read 4, iclass 31, count 0 2006.201.09:22:52.69#ibcon#about to read 5, iclass 31, count 0 2006.201.09:22:52.69#ibcon#read 5, iclass 31, count 0 2006.201.09:22:52.69#ibcon#about to read 6, iclass 31, count 0 2006.201.09:22:52.69#ibcon#read 6, iclass 31, count 0 2006.201.09:22:52.69#ibcon#end of sib2, iclass 31, count 0 2006.201.09:22:52.69#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:22:52.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:22:52.69#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:22:52.69#ibcon#*before write, iclass 31, count 0 2006.201.09:22:52.69#ibcon#enter sib2, iclass 31, count 0 2006.201.09:22:52.69#ibcon#flushed, iclass 31, count 0 2006.201.09:22:52.69#ibcon#about to write, iclass 31, count 0 2006.201.09:22:52.69#ibcon#wrote, iclass 31, count 0 2006.201.09:22:52.69#ibcon#about to read 3, iclass 31, count 0 2006.201.09:22:52.73#ibcon#read 3, iclass 31, count 0 2006.201.09:22:52.73#ibcon#about to read 4, iclass 31, count 0 2006.201.09:22:52.73#ibcon#read 4, iclass 31, count 0 2006.201.09:22:52.73#ibcon#about to read 5, iclass 31, count 0 2006.201.09:22:52.73#ibcon#read 5, iclass 31, count 0 2006.201.09:22:52.73#ibcon#about to read 6, iclass 31, count 0 2006.201.09:22:52.73#ibcon#read 6, iclass 31, count 0 2006.201.09:22:52.73#ibcon#end of sib2, iclass 31, count 0 2006.201.09:22:52.73#ibcon#*after write, iclass 31, count 0 2006.201.09:22:52.73#ibcon#*before return 0, iclass 31, count 0 2006.201.09:22:52.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:52.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.09:22:52.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:22:52.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:22:52.73$vck44/vb=7,4 2006.201.09:22:52.73#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.09:22:52.73#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.09:22:52.73#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:52.73#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:52.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:52.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:52.79#ibcon#enter wrdev, iclass 33, count 2 2006.201.09:22:52.79#ibcon#first serial, iclass 33, count 2 2006.201.09:22:52.79#ibcon#enter sib2, iclass 33, count 2 2006.201.09:22:52.79#ibcon#flushed, iclass 33, count 2 2006.201.09:22:52.79#ibcon#about to write, iclass 33, count 2 2006.201.09:22:52.79#ibcon#wrote, iclass 33, count 2 2006.201.09:22:52.79#ibcon#about to read 3, iclass 33, count 2 2006.201.09:22:52.81#ibcon#read 3, iclass 33, count 2 2006.201.09:22:52.81#ibcon#about to read 4, iclass 33, count 2 2006.201.09:22:52.81#ibcon#read 4, iclass 33, count 2 2006.201.09:22:52.81#ibcon#about to read 5, iclass 33, count 2 2006.201.09:22:52.81#ibcon#read 5, iclass 33, count 2 2006.201.09:22:52.81#ibcon#about to read 6, iclass 33, count 2 2006.201.09:22:52.81#ibcon#read 6, iclass 33, count 2 2006.201.09:22:52.81#ibcon#end of sib2, iclass 33, count 2 2006.201.09:22:52.81#ibcon#*mode == 0, iclass 33, count 2 2006.201.09:22:52.81#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.09:22:52.81#ibcon#[27=AT07-04\r\n] 2006.201.09:22:52.81#ibcon#*before write, iclass 33, count 2 2006.201.09:22:52.81#ibcon#enter sib2, iclass 33, count 2 2006.201.09:22:52.81#ibcon#flushed, iclass 33, count 2 2006.201.09:22:52.81#ibcon#about to write, iclass 33, count 2 2006.201.09:22:52.81#ibcon#wrote, iclass 33, count 2 2006.201.09:22:52.81#ibcon#about to read 3, iclass 33, count 2 2006.201.09:22:52.84#ibcon#read 3, iclass 33, count 2 2006.201.09:22:52.84#ibcon#about to read 4, iclass 33, count 2 2006.201.09:22:52.84#ibcon#read 4, iclass 33, count 2 2006.201.09:22:52.84#ibcon#about to read 5, iclass 33, count 2 2006.201.09:22:52.84#ibcon#read 5, iclass 33, count 2 2006.201.09:22:52.84#ibcon#about to read 6, iclass 33, count 2 2006.201.09:22:52.84#ibcon#read 6, iclass 33, count 2 2006.201.09:22:52.84#ibcon#end of sib2, iclass 33, count 2 2006.201.09:22:52.84#ibcon#*after write, iclass 33, count 2 2006.201.09:22:52.84#ibcon#*before return 0, iclass 33, count 2 2006.201.09:22:52.84#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:52.84#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.09:22:52.84#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.09:22:52.84#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:52.84#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:52.96#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:52.96#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:52.96#ibcon#enter wrdev, iclass 33, count 0 2006.201.09:22:52.96#ibcon#first serial, iclass 33, count 0 2006.201.09:22:52.96#ibcon#enter sib2, iclass 33, count 0 2006.201.09:22:52.96#ibcon#flushed, iclass 33, count 0 2006.201.09:22:52.96#ibcon#about to write, iclass 33, count 0 2006.201.09:22:52.96#ibcon#wrote, iclass 33, count 0 2006.201.09:22:52.96#ibcon#about to read 3, iclass 33, count 0 2006.201.09:22:52.98#ibcon#read 3, iclass 33, count 0 2006.201.09:22:52.98#ibcon#about to read 4, iclass 33, count 0 2006.201.09:22:52.98#ibcon#read 4, iclass 33, count 0 2006.201.09:22:52.98#ibcon#about to read 5, iclass 33, count 0 2006.201.09:22:52.98#ibcon#read 5, iclass 33, count 0 2006.201.09:22:52.98#ibcon#about to read 6, iclass 33, count 0 2006.201.09:22:52.98#ibcon#read 6, iclass 33, count 0 2006.201.09:22:52.98#ibcon#end of sib2, iclass 33, count 0 2006.201.09:22:52.98#ibcon#*mode == 0, iclass 33, count 0 2006.201.09:22:52.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.09:22:52.98#ibcon#[27=USB\r\n] 2006.201.09:22:52.98#ibcon#*before write, iclass 33, count 0 2006.201.09:22:52.98#ibcon#enter sib2, iclass 33, count 0 2006.201.09:22:52.98#ibcon#flushed, iclass 33, count 0 2006.201.09:22:52.98#ibcon#about to write, iclass 33, count 0 2006.201.09:22:52.98#ibcon#wrote, iclass 33, count 0 2006.201.09:22:52.98#ibcon#about to read 3, iclass 33, count 0 2006.201.09:22:53.01#ibcon#read 3, iclass 33, count 0 2006.201.09:22:53.01#ibcon#about to read 4, iclass 33, count 0 2006.201.09:22:53.01#ibcon#read 4, iclass 33, count 0 2006.201.09:22:53.01#ibcon#about to read 5, iclass 33, count 0 2006.201.09:22:53.01#ibcon#read 5, iclass 33, count 0 2006.201.09:22:53.01#ibcon#about to read 6, iclass 33, count 0 2006.201.09:22:53.01#ibcon#read 6, iclass 33, count 0 2006.201.09:22:53.01#ibcon#end of sib2, iclass 33, count 0 2006.201.09:22:53.01#ibcon#*after write, iclass 33, count 0 2006.201.09:22:53.01#ibcon#*before return 0, iclass 33, count 0 2006.201.09:22:53.01#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:53.01#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.09:22:53.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.09:22:53.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.09:22:53.01$vck44/vblo=8,744.99 2006.201.09:22:53.01#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.09:22:53.01#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.09:22:53.01#ibcon#ireg 17 cls_cnt 0 2006.201.09:22:53.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:53.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:53.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:53.01#ibcon#enter wrdev, iclass 35, count 0 2006.201.09:22:53.01#ibcon#first serial, iclass 35, count 0 2006.201.09:22:53.01#ibcon#enter sib2, iclass 35, count 0 2006.201.09:22:53.01#ibcon#flushed, iclass 35, count 0 2006.201.09:22:53.01#ibcon#about to write, iclass 35, count 0 2006.201.09:22:53.01#ibcon#wrote, iclass 35, count 0 2006.201.09:22:53.01#ibcon#about to read 3, iclass 35, count 0 2006.201.09:22:53.03#ibcon#read 3, iclass 35, count 0 2006.201.09:22:53.03#ibcon#about to read 4, iclass 35, count 0 2006.201.09:22:53.03#ibcon#read 4, iclass 35, count 0 2006.201.09:22:53.03#ibcon#about to read 5, iclass 35, count 0 2006.201.09:22:53.03#ibcon#read 5, iclass 35, count 0 2006.201.09:22:53.03#ibcon#about to read 6, iclass 35, count 0 2006.201.09:22:53.03#ibcon#read 6, iclass 35, count 0 2006.201.09:22:53.03#ibcon#end of sib2, iclass 35, count 0 2006.201.09:22:53.03#ibcon#*mode == 0, iclass 35, count 0 2006.201.09:22:53.03#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.09:22:53.03#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:22:53.03#ibcon#*before write, iclass 35, count 0 2006.201.09:22:53.03#ibcon#enter sib2, iclass 35, count 0 2006.201.09:22:53.03#ibcon#flushed, iclass 35, count 0 2006.201.09:22:53.03#ibcon#about to write, iclass 35, count 0 2006.201.09:22:53.03#ibcon#wrote, iclass 35, count 0 2006.201.09:22:53.03#ibcon#about to read 3, iclass 35, count 0 2006.201.09:22:53.07#ibcon#read 3, iclass 35, count 0 2006.201.09:22:53.07#ibcon#about to read 4, iclass 35, count 0 2006.201.09:22:53.07#ibcon#read 4, iclass 35, count 0 2006.201.09:22:53.07#ibcon#about to read 5, iclass 35, count 0 2006.201.09:22:53.07#ibcon#read 5, iclass 35, count 0 2006.201.09:22:53.07#ibcon#about to read 6, iclass 35, count 0 2006.201.09:22:53.07#ibcon#read 6, iclass 35, count 0 2006.201.09:22:53.07#ibcon#end of sib2, iclass 35, count 0 2006.201.09:22:53.07#ibcon#*after write, iclass 35, count 0 2006.201.09:22:53.07#ibcon#*before return 0, iclass 35, count 0 2006.201.09:22:53.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:53.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:22:53.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.09:22:53.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.09:22:53.07$vck44/vb=8,4 2006.201.09:22:53.07#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.09:22:53.07#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.09:22:53.07#ibcon#ireg 11 cls_cnt 2 2006.201.09:22:53.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:53.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:53.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:53.13#ibcon#enter wrdev, iclass 37, count 2 2006.201.09:22:53.13#ibcon#first serial, iclass 37, count 2 2006.201.09:22:53.13#ibcon#enter sib2, iclass 37, count 2 2006.201.09:22:53.13#ibcon#flushed, iclass 37, count 2 2006.201.09:22:53.13#ibcon#about to write, iclass 37, count 2 2006.201.09:22:53.13#ibcon#wrote, iclass 37, count 2 2006.201.09:22:53.13#ibcon#about to read 3, iclass 37, count 2 2006.201.09:22:53.15#ibcon#read 3, iclass 37, count 2 2006.201.09:22:53.15#ibcon#about to read 4, iclass 37, count 2 2006.201.09:22:53.15#ibcon#read 4, iclass 37, count 2 2006.201.09:22:53.15#ibcon#about to read 5, iclass 37, count 2 2006.201.09:22:53.15#ibcon#read 5, iclass 37, count 2 2006.201.09:22:53.15#ibcon#about to read 6, iclass 37, count 2 2006.201.09:22:53.15#ibcon#read 6, iclass 37, count 2 2006.201.09:22:53.15#ibcon#end of sib2, iclass 37, count 2 2006.201.09:22:53.15#ibcon#*mode == 0, iclass 37, count 2 2006.201.09:22:53.15#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.09:22:53.15#ibcon#[27=AT08-04\r\n] 2006.201.09:22:53.15#ibcon#*before write, iclass 37, count 2 2006.201.09:22:53.15#ibcon#enter sib2, iclass 37, count 2 2006.201.09:22:53.15#ibcon#flushed, iclass 37, count 2 2006.201.09:22:53.15#ibcon#about to write, iclass 37, count 2 2006.201.09:22:53.15#ibcon#wrote, iclass 37, count 2 2006.201.09:22:53.15#ibcon#about to read 3, iclass 37, count 2 2006.201.09:22:53.18#ibcon#read 3, iclass 37, count 2 2006.201.09:22:53.18#ibcon#about to read 4, iclass 37, count 2 2006.201.09:22:53.18#ibcon#read 4, iclass 37, count 2 2006.201.09:22:53.18#ibcon#about to read 5, iclass 37, count 2 2006.201.09:22:53.18#ibcon#read 5, iclass 37, count 2 2006.201.09:22:53.18#ibcon#about to read 6, iclass 37, count 2 2006.201.09:22:53.18#ibcon#read 6, iclass 37, count 2 2006.201.09:22:53.18#ibcon#end of sib2, iclass 37, count 2 2006.201.09:22:53.18#ibcon#*after write, iclass 37, count 2 2006.201.09:22:53.18#ibcon#*before return 0, iclass 37, count 2 2006.201.09:22:53.18#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:53.18#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.09:22:53.18#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.09:22:53.18#ibcon#ireg 7 cls_cnt 0 2006.201.09:22:53.18#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:53.30#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:53.30#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:53.30#ibcon#enter wrdev, iclass 37, count 0 2006.201.09:22:53.30#ibcon#first serial, iclass 37, count 0 2006.201.09:22:53.30#ibcon#enter sib2, iclass 37, count 0 2006.201.09:22:53.30#ibcon#flushed, iclass 37, count 0 2006.201.09:22:53.30#ibcon#about to write, iclass 37, count 0 2006.201.09:22:53.30#ibcon#wrote, iclass 37, count 0 2006.201.09:22:53.30#ibcon#about to read 3, iclass 37, count 0 2006.201.09:22:53.32#ibcon#read 3, iclass 37, count 0 2006.201.09:22:53.32#ibcon#about to read 4, iclass 37, count 0 2006.201.09:22:53.32#ibcon#read 4, iclass 37, count 0 2006.201.09:22:53.32#ibcon#about to read 5, iclass 37, count 0 2006.201.09:22:53.32#ibcon#read 5, iclass 37, count 0 2006.201.09:22:53.32#ibcon#about to read 6, iclass 37, count 0 2006.201.09:22:53.32#ibcon#read 6, iclass 37, count 0 2006.201.09:22:53.32#ibcon#end of sib2, iclass 37, count 0 2006.201.09:22:53.32#ibcon#*mode == 0, iclass 37, count 0 2006.201.09:22:53.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.09:22:53.32#ibcon#[27=USB\r\n] 2006.201.09:22:53.32#ibcon#*before write, iclass 37, count 0 2006.201.09:22:53.32#ibcon#enter sib2, iclass 37, count 0 2006.201.09:22:53.32#ibcon#flushed, iclass 37, count 0 2006.201.09:22:53.32#ibcon#about to write, iclass 37, count 0 2006.201.09:22:53.32#ibcon#wrote, iclass 37, count 0 2006.201.09:22:53.32#ibcon#about to read 3, iclass 37, count 0 2006.201.09:22:53.35#ibcon#read 3, iclass 37, count 0 2006.201.09:22:53.35#ibcon#about to read 4, iclass 37, count 0 2006.201.09:22:53.35#ibcon#read 4, iclass 37, count 0 2006.201.09:22:53.35#ibcon#about to read 5, iclass 37, count 0 2006.201.09:22:53.35#ibcon#read 5, iclass 37, count 0 2006.201.09:22:53.35#ibcon#about to read 6, iclass 37, count 0 2006.201.09:22:53.35#ibcon#read 6, iclass 37, count 0 2006.201.09:22:53.35#ibcon#end of sib2, iclass 37, count 0 2006.201.09:22:53.35#ibcon#*after write, iclass 37, count 0 2006.201.09:22:53.35#ibcon#*before return 0, iclass 37, count 0 2006.201.09:22:53.35#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:53.35#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.09:22:53.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.09:22:53.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.09:22:53.35$vck44/vabw=wide 2006.201.09:22:53.35#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.09:22:53.35#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.09:22:53.35#ibcon#ireg 8 cls_cnt 0 2006.201.09:22:53.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:53.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:53.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:53.35#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:22:53.35#ibcon#first serial, iclass 39, count 0 2006.201.09:22:53.35#ibcon#enter sib2, iclass 39, count 0 2006.201.09:22:53.35#ibcon#flushed, iclass 39, count 0 2006.201.09:22:53.35#ibcon#about to write, iclass 39, count 0 2006.201.09:22:53.35#ibcon#wrote, iclass 39, count 0 2006.201.09:22:53.35#ibcon#about to read 3, iclass 39, count 0 2006.201.09:22:53.37#ibcon#read 3, iclass 39, count 0 2006.201.09:22:53.37#ibcon#about to read 4, iclass 39, count 0 2006.201.09:22:53.37#ibcon#read 4, iclass 39, count 0 2006.201.09:22:53.37#ibcon#about to read 5, iclass 39, count 0 2006.201.09:22:53.37#ibcon#read 5, iclass 39, count 0 2006.201.09:22:53.37#ibcon#about to read 6, iclass 39, count 0 2006.201.09:22:53.37#ibcon#read 6, iclass 39, count 0 2006.201.09:22:53.37#ibcon#end of sib2, iclass 39, count 0 2006.201.09:22:53.37#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:22:53.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:22:53.37#ibcon#[25=BW32\r\n] 2006.201.09:22:53.37#ibcon#*before write, iclass 39, count 0 2006.201.09:22:53.37#ibcon#enter sib2, iclass 39, count 0 2006.201.09:22:53.37#ibcon#flushed, iclass 39, count 0 2006.201.09:22:53.37#ibcon#about to write, iclass 39, count 0 2006.201.09:22:53.37#ibcon#wrote, iclass 39, count 0 2006.201.09:22:53.37#ibcon#about to read 3, iclass 39, count 0 2006.201.09:22:53.41#ibcon#read 3, iclass 39, count 0 2006.201.09:22:53.41#ibcon#about to read 4, iclass 39, count 0 2006.201.09:22:53.41#ibcon#read 4, iclass 39, count 0 2006.201.09:22:53.41#ibcon#about to read 5, iclass 39, count 0 2006.201.09:22:53.41#ibcon#read 5, iclass 39, count 0 2006.201.09:22:53.41#ibcon#about to read 6, iclass 39, count 0 2006.201.09:22:53.41#ibcon#read 6, iclass 39, count 0 2006.201.09:22:53.41#ibcon#end of sib2, iclass 39, count 0 2006.201.09:22:53.41#ibcon#*after write, iclass 39, count 0 2006.201.09:22:53.41#ibcon#*before return 0, iclass 39, count 0 2006.201.09:22:53.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:53.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:22:53.41#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:22:53.41#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:22:53.41$vck44/vbbw=wide 2006.201.09:22:53.41#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.09:22:53.41#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.09:22:53.41#ibcon#ireg 8 cls_cnt 0 2006.201.09:22:53.41#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:22:53.47#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:22:53.47#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:22:53.47#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:22:53.47#ibcon#first serial, iclass 2, count 0 2006.201.09:22:53.47#ibcon#enter sib2, iclass 2, count 0 2006.201.09:22:53.47#ibcon#flushed, iclass 2, count 0 2006.201.09:22:53.47#ibcon#about to write, iclass 2, count 0 2006.201.09:22:53.47#ibcon#wrote, iclass 2, count 0 2006.201.09:22:53.47#ibcon#about to read 3, iclass 2, count 0 2006.201.09:22:53.49#ibcon#read 3, iclass 2, count 0 2006.201.09:22:53.49#ibcon#about to read 4, iclass 2, count 0 2006.201.09:22:53.49#ibcon#read 4, iclass 2, count 0 2006.201.09:22:53.49#ibcon#about to read 5, iclass 2, count 0 2006.201.09:22:53.49#ibcon#read 5, iclass 2, count 0 2006.201.09:22:53.49#ibcon#about to read 6, iclass 2, count 0 2006.201.09:22:53.49#ibcon#read 6, iclass 2, count 0 2006.201.09:22:53.49#ibcon#end of sib2, iclass 2, count 0 2006.201.09:22:53.49#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:22:53.49#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:22:53.49#ibcon#[27=BW32\r\n] 2006.201.09:22:53.49#ibcon#*before write, iclass 2, count 0 2006.201.09:22:53.49#ibcon#enter sib2, iclass 2, count 0 2006.201.09:22:53.49#ibcon#flushed, iclass 2, count 0 2006.201.09:22:53.49#ibcon#about to write, iclass 2, count 0 2006.201.09:22:53.49#ibcon#wrote, iclass 2, count 0 2006.201.09:22:53.49#ibcon#about to read 3, iclass 2, count 0 2006.201.09:22:53.52#ibcon#read 3, iclass 2, count 0 2006.201.09:22:53.52#ibcon#about to read 4, iclass 2, count 0 2006.201.09:22:53.52#ibcon#read 4, iclass 2, count 0 2006.201.09:22:53.52#ibcon#about to read 5, iclass 2, count 0 2006.201.09:22:53.52#ibcon#read 5, iclass 2, count 0 2006.201.09:22:53.52#ibcon#about to read 6, iclass 2, count 0 2006.201.09:22:53.52#ibcon#read 6, iclass 2, count 0 2006.201.09:22:53.52#ibcon#end of sib2, iclass 2, count 0 2006.201.09:22:53.52#ibcon#*after write, iclass 2, count 0 2006.201.09:22:53.52#ibcon#*before return 0, iclass 2, count 0 2006.201.09:22:53.52#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:22:53.52#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:22:53.52#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:22:53.52#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:22:53.52$setupk4/ifdk4 2006.201.09:22:53.52$ifdk4/lo= 2006.201.09:22:53.52$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:22:53.52$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:22:53.52$ifdk4/patch= 2006.201.09:22:53.52$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:22:53.52$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:22:53.52$setupk4/!*+20s 2006.201.09:22:57.24#abcon#<5=/05 2.8 4.9 22.69 901003.8\r\n> 2006.201.09:22:57.26#abcon#{5=INTERFACE CLEAR} 2006.201.09:22:57.32#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:23:07.41#abcon#<5=/05 2.8 4.9 22.69 911003.8\r\n> 2006.201.09:23:07.43#abcon#{5=INTERFACE CLEAR} 2006.201.09:23:07.49#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:23:07.98$setupk4/"tpicd 2006.201.09:23:07.98$setupk4/echo=off 2006.201.09:23:07.98$setupk4/xlog=off 2006.201.09:23:07.98:!2006.201.09:29:47 2006.201.09:23:09.14#trakl#Source acquired 2006.201.09:23:11.14#flagr#flagr/antenna,acquired 2006.201.09:29:47.00:preob 2006.201.09:29:48.14/onsource/TRACKING 2006.201.09:29:48.14:!2006.201.09:29:57 2006.201.09:29:57.00:"tape 2006.201.09:29:57.00:"st=record 2006.201.09:29:57.00:data_valid=on 2006.201.09:29:57.00:midob 2006.201.09:29:57.14/onsource/TRACKING 2006.201.09:29:57.14/wx/22.60,1003.8,92 2006.201.09:29:57.27/cable/+6.4676E-03 2006.201.09:29:58.36/va/01,08,usb,yes,33,35 2006.201.09:29:58.36/va/02,07,usb,yes,35,36 2006.201.09:29:58.36/va/03,08,usb,yes,32,33 2006.201.09:29:58.36/va/04,07,usb,yes,36,38 2006.201.09:29:58.36/va/05,04,usb,yes,32,33 2006.201.09:29:58.36/va/06,05,usb,yes,32,32 2006.201.09:29:58.36/va/07,05,usb,yes,32,33 2006.201.09:29:58.36/va/08,04,usb,yes,31,37 2006.201.09:29:58.59/valo/01,524.99,yes,locked 2006.201.09:29:58.59/valo/02,534.99,yes,locked 2006.201.09:29:58.59/valo/03,564.99,yes,locked 2006.201.09:29:58.59/valo/04,624.99,yes,locked 2006.201.09:29:58.59/valo/05,734.99,yes,locked 2006.201.09:29:58.59/valo/06,814.99,yes,locked 2006.201.09:29:58.59/valo/07,864.99,yes,locked 2006.201.09:29:58.59/valo/08,884.99,yes,locked 2006.201.09:29:59.68/vb/01,04,usb,yes,31,28 2006.201.09:29:59.68/vb/02,05,usb,yes,29,29 2006.201.09:29:59.68/vb/03,04,usb,yes,30,33 2006.201.09:29:59.68/vb/04,05,usb,yes,30,29 2006.201.09:29:59.68/vb/05,04,usb,yes,27,29 2006.201.09:29:59.68/vb/06,04,usb,yes,31,28 2006.201.09:29:59.68/vb/07,04,usb,yes,31,31 2006.201.09:29:59.68/vb/08,04,usb,yes,29,32 2006.201.09:29:59.91/vblo/01,629.99,yes,locked 2006.201.09:29:59.91/vblo/02,634.99,yes,locked 2006.201.09:29:59.91/vblo/03,649.99,yes,locked 2006.201.09:29:59.91/vblo/04,679.99,yes,locked 2006.201.09:29:59.91/vblo/05,709.99,yes,locked 2006.201.09:29:59.91/vblo/06,719.99,yes,locked 2006.201.09:29:59.91/vblo/07,734.99,yes,locked 2006.201.09:29:59.91/vblo/08,744.99,yes,locked 2006.201.09:30:00.06/vabw/8 2006.201.09:30:00.21/vbbw/8 2006.201.09:30:00.37/xfe/off,on,16.0 2006.201.09:30:00.74/ifatt/23,28,28,28 2006.201.09:30:01.05/fmout-gps/S +4.55E-07 2006.201.09:30:01.12:!2006.201.09:30:37 2006.201.09:30:37.00:data_valid=off 2006.201.09:30:37.00:"et 2006.201.09:30:37.00:!+3s 2006.201.09:30:40.02:"tape 2006.201.09:30:40.02:postob 2006.201.09:30:40.21/cable/+6.4682E-03 2006.201.09:30:40.21/wx/22.59,1003.8,92 2006.201.09:30:40.27/fmout-gps/S +4.56E-07 2006.201.09:30:40.27:scan_name=201-0935,jd0607,40 2006.201.09:30:40.27:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.201.09:30:42.14#flagr#flagr/antenna,new-source 2006.201.09:30:42.14:checkk5 2006.201.09:30:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:30:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:30:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:30:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:30:44.02/chk_obsdata//k5ts1/T2010929??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:30:44.38/chk_obsdata//k5ts2/T2010929??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:30:44.75/chk_obsdata//k5ts3/T2010929??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:30:45.11/chk_obsdata//k5ts4/T2010929??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:30:45.80/k5log//k5ts1_log_newline 2006.201.09:30:46.50/k5log//k5ts2_log_newline 2006.201.09:30:47.19/k5log//k5ts3_log_newline 2006.201.09:30:47.87/k5log//k5ts4_log_newline 2006.201.09:30:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:30:47.89:setupk4=1 2006.201.09:30:47.89$setupk4/echo=on 2006.201.09:30:47.89$setupk4/pcalon 2006.201.09:30:47.89$pcalon/"no phase cal control is implemented here 2006.201.09:30:47.89$setupk4/"tpicd=stop 2006.201.09:30:47.89$setupk4/"rec=synch_on 2006.201.09:30:47.89$setupk4/"rec_mode=128 2006.201.09:30:47.89$setupk4/!* 2006.201.09:30:47.89$setupk4/recpk4 2006.201.09:30:47.89$recpk4/recpatch= 2006.201.09:30:47.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:30:47.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:30:47.90$setupk4/vck44 2006.201.09:30:47.90$vck44/valo=1,524.99 2006.201.09:30:47.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.09:30:47.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.09:30:47.90#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:47.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:47.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:47.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:47.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:30:47.90#ibcon#first serial, iclass 18, count 0 2006.201.09:30:47.90#ibcon#enter sib2, iclass 18, count 0 2006.201.09:30:47.90#ibcon#flushed, iclass 18, count 0 2006.201.09:30:47.90#ibcon#about to write, iclass 18, count 0 2006.201.09:30:47.90#ibcon#wrote, iclass 18, count 0 2006.201.09:30:47.90#ibcon#about to read 3, iclass 18, count 0 2006.201.09:30:47.94#ibcon#read 3, iclass 18, count 0 2006.201.09:30:47.94#ibcon#about to read 4, iclass 18, count 0 2006.201.09:30:47.94#ibcon#read 4, iclass 18, count 0 2006.201.09:30:47.94#ibcon#about to read 5, iclass 18, count 0 2006.201.09:30:47.94#ibcon#read 5, iclass 18, count 0 2006.201.09:30:47.94#ibcon#about to read 6, iclass 18, count 0 2006.201.09:30:47.94#ibcon#read 6, iclass 18, count 0 2006.201.09:30:47.94#ibcon#end of sib2, iclass 18, count 0 2006.201.09:30:47.94#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:30:47.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:30:47.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:30:47.94#ibcon#*before write, iclass 18, count 0 2006.201.09:30:47.94#ibcon#enter sib2, iclass 18, count 0 2006.201.09:30:47.94#ibcon#flushed, iclass 18, count 0 2006.201.09:30:47.94#ibcon#about to write, iclass 18, count 0 2006.201.09:30:47.94#ibcon#wrote, iclass 18, count 0 2006.201.09:30:47.94#ibcon#about to read 3, iclass 18, count 0 2006.201.09:30:47.99#ibcon#read 3, iclass 18, count 0 2006.201.09:30:47.99#ibcon#about to read 4, iclass 18, count 0 2006.201.09:30:47.99#ibcon#read 4, iclass 18, count 0 2006.201.09:30:47.99#ibcon#about to read 5, iclass 18, count 0 2006.201.09:30:47.99#ibcon#read 5, iclass 18, count 0 2006.201.09:30:47.99#ibcon#about to read 6, iclass 18, count 0 2006.201.09:30:47.99#ibcon#read 6, iclass 18, count 0 2006.201.09:30:47.99#ibcon#end of sib2, iclass 18, count 0 2006.201.09:30:47.99#ibcon#*after write, iclass 18, count 0 2006.201.09:30:47.99#ibcon#*before return 0, iclass 18, count 0 2006.201.09:30:47.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:47.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:47.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:30:47.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:30:47.99$vck44/va=1,8 2006.201.09:30:47.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.09:30:47.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.09:30:47.99#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:47.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:47.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:47.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:47.99#ibcon#enter wrdev, iclass 20, count 2 2006.201.09:30:47.99#ibcon#first serial, iclass 20, count 2 2006.201.09:30:47.99#ibcon#enter sib2, iclass 20, count 2 2006.201.09:30:47.99#ibcon#flushed, iclass 20, count 2 2006.201.09:30:47.99#ibcon#about to write, iclass 20, count 2 2006.201.09:30:47.99#ibcon#wrote, iclass 20, count 2 2006.201.09:30:47.99#ibcon#about to read 3, iclass 20, count 2 2006.201.09:30:48.01#ibcon#read 3, iclass 20, count 2 2006.201.09:30:48.01#ibcon#about to read 4, iclass 20, count 2 2006.201.09:30:48.01#ibcon#read 4, iclass 20, count 2 2006.201.09:30:48.01#ibcon#about to read 5, iclass 20, count 2 2006.201.09:30:48.01#ibcon#read 5, iclass 20, count 2 2006.201.09:30:48.01#ibcon#about to read 6, iclass 20, count 2 2006.201.09:30:48.01#ibcon#read 6, iclass 20, count 2 2006.201.09:30:48.01#ibcon#end of sib2, iclass 20, count 2 2006.201.09:30:48.01#ibcon#*mode == 0, iclass 20, count 2 2006.201.09:30:48.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.09:30:48.01#ibcon#[25=AT01-08\r\n] 2006.201.09:30:48.01#ibcon#*before write, iclass 20, count 2 2006.201.09:30:48.01#ibcon#enter sib2, iclass 20, count 2 2006.201.09:30:48.01#ibcon#flushed, iclass 20, count 2 2006.201.09:30:48.01#ibcon#about to write, iclass 20, count 2 2006.201.09:30:48.01#ibcon#wrote, iclass 20, count 2 2006.201.09:30:48.01#ibcon#about to read 3, iclass 20, count 2 2006.201.09:30:48.05#ibcon#read 3, iclass 20, count 2 2006.201.09:30:48.05#ibcon#about to read 4, iclass 20, count 2 2006.201.09:30:48.05#ibcon#read 4, iclass 20, count 2 2006.201.09:30:48.05#ibcon#about to read 5, iclass 20, count 2 2006.201.09:30:48.05#ibcon#read 5, iclass 20, count 2 2006.201.09:30:48.05#ibcon#about to read 6, iclass 20, count 2 2006.201.09:30:48.05#ibcon#read 6, iclass 20, count 2 2006.201.09:30:48.05#ibcon#end of sib2, iclass 20, count 2 2006.201.09:30:48.05#ibcon#*after write, iclass 20, count 2 2006.201.09:30:48.05#ibcon#*before return 0, iclass 20, count 2 2006.201.09:30:48.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:48.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:48.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.09:30:48.05#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:48.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:48.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:48.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:48.17#ibcon#enter wrdev, iclass 20, count 0 2006.201.09:30:48.17#ibcon#first serial, iclass 20, count 0 2006.201.09:30:48.17#ibcon#enter sib2, iclass 20, count 0 2006.201.09:30:48.17#ibcon#flushed, iclass 20, count 0 2006.201.09:30:48.17#ibcon#about to write, iclass 20, count 0 2006.201.09:30:48.17#ibcon#wrote, iclass 20, count 0 2006.201.09:30:48.17#ibcon#about to read 3, iclass 20, count 0 2006.201.09:30:48.19#ibcon#read 3, iclass 20, count 0 2006.201.09:30:48.19#ibcon#about to read 4, iclass 20, count 0 2006.201.09:30:48.19#ibcon#read 4, iclass 20, count 0 2006.201.09:30:48.19#ibcon#about to read 5, iclass 20, count 0 2006.201.09:30:48.19#ibcon#read 5, iclass 20, count 0 2006.201.09:30:48.19#ibcon#about to read 6, iclass 20, count 0 2006.201.09:30:48.19#ibcon#read 6, iclass 20, count 0 2006.201.09:30:48.19#ibcon#end of sib2, iclass 20, count 0 2006.201.09:30:48.19#ibcon#*mode == 0, iclass 20, count 0 2006.201.09:30:48.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.09:30:48.19#ibcon#[25=USB\r\n] 2006.201.09:30:48.19#ibcon#*before write, iclass 20, count 0 2006.201.09:30:48.19#ibcon#enter sib2, iclass 20, count 0 2006.201.09:30:48.19#ibcon#flushed, iclass 20, count 0 2006.201.09:30:48.19#ibcon#about to write, iclass 20, count 0 2006.201.09:30:48.19#ibcon#wrote, iclass 20, count 0 2006.201.09:30:48.19#ibcon#about to read 3, iclass 20, count 0 2006.201.09:30:48.22#ibcon#read 3, iclass 20, count 0 2006.201.09:30:48.22#ibcon#about to read 4, iclass 20, count 0 2006.201.09:30:48.22#ibcon#read 4, iclass 20, count 0 2006.201.09:30:48.22#ibcon#about to read 5, iclass 20, count 0 2006.201.09:30:48.22#ibcon#read 5, iclass 20, count 0 2006.201.09:30:48.22#ibcon#about to read 6, iclass 20, count 0 2006.201.09:30:48.22#ibcon#read 6, iclass 20, count 0 2006.201.09:30:48.22#ibcon#end of sib2, iclass 20, count 0 2006.201.09:30:48.22#ibcon#*after write, iclass 20, count 0 2006.201.09:30:48.22#ibcon#*before return 0, iclass 20, count 0 2006.201.09:30:48.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:48.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:48.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.09:30:48.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.09:30:48.22$vck44/valo=2,534.99 2006.201.09:30:48.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.09:30:48.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.09:30:48.22#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:48.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:48.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:48.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:48.22#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:30:48.22#ibcon#first serial, iclass 22, count 0 2006.201.09:30:48.22#ibcon#enter sib2, iclass 22, count 0 2006.201.09:30:48.22#ibcon#flushed, iclass 22, count 0 2006.201.09:30:48.22#ibcon#about to write, iclass 22, count 0 2006.201.09:30:48.22#ibcon#wrote, iclass 22, count 0 2006.201.09:30:48.22#ibcon#about to read 3, iclass 22, count 0 2006.201.09:30:48.24#ibcon#read 3, iclass 22, count 0 2006.201.09:30:48.24#ibcon#about to read 4, iclass 22, count 0 2006.201.09:30:48.24#ibcon#read 4, iclass 22, count 0 2006.201.09:30:48.24#ibcon#about to read 5, iclass 22, count 0 2006.201.09:30:48.24#ibcon#read 5, iclass 22, count 0 2006.201.09:30:48.24#ibcon#about to read 6, iclass 22, count 0 2006.201.09:30:48.24#ibcon#read 6, iclass 22, count 0 2006.201.09:30:48.24#ibcon#end of sib2, iclass 22, count 0 2006.201.09:30:48.24#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:30:48.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:30:48.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:30:48.24#ibcon#*before write, iclass 22, count 0 2006.201.09:30:48.24#ibcon#enter sib2, iclass 22, count 0 2006.201.09:30:48.24#ibcon#flushed, iclass 22, count 0 2006.201.09:30:48.24#ibcon#about to write, iclass 22, count 0 2006.201.09:30:48.24#ibcon#wrote, iclass 22, count 0 2006.201.09:30:48.24#ibcon#about to read 3, iclass 22, count 0 2006.201.09:30:48.28#ibcon#read 3, iclass 22, count 0 2006.201.09:30:48.28#ibcon#about to read 4, iclass 22, count 0 2006.201.09:30:48.28#ibcon#read 4, iclass 22, count 0 2006.201.09:30:48.28#ibcon#about to read 5, iclass 22, count 0 2006.201.09:30:48.28#ibcon#read 5, iclass 22, count 0 2006.201.09:30:48.28#ibcon#about to read 6, iclass 22, count 0 2006.201.09:30:48.28#ibcon#read 6, iclass 22, count 0 2006.201.09:30:48.28#ibcon#end of sib2, iclass 22, count 0 2006.201.09:30:48.28#ibcon#*after write, iclass 22, count 0 2006.201.09:30:48.28#ibcon#*before return 0, iclass 22, count 0 2006.201.09:30:48.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:48.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:48.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:30:48.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:30:48.28$vck44/va=2,7 2006.201.09:30:48.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.09:30:48.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.09:30:48.28#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:48.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:48.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:48.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:48.34#ibcon#enter wrdev, iclass 24, count 2 2006.201.09:30:48.34#ibcon#first serial, iclass 24, count 2 2006.201.09:30:48.34#ibcon#enter sib2, iclass 24, count 2 2006.201.09:30:48.34#ibcon#flushed, iclass 24, count 2 2006.201.09:30:48.34#ibcon#about to write, iclass 24, count 2 2006.201.09:30:48.34#ibcon#wrote, iclass 24, count 2 2006.201.09:30:48.34#ibcon#about to read 3, iclass 24, count 2 2006.201.09:30:48.36#ibcon#read 3, iclass 24, count 2 2006.201.09:30:48.36#ibcon#about to read 4, iclass 24, count 2 2006.201.09:30:48.36#ibcon#read 4, iclass 24, count 2 2006.201.09:30:48.36#ibcon#about to read 5, iclass 24, count 2 2006.201.09:30:48.36#ibcon#read 5, iclass 24, count 2 2006.201.09:30:48.36#ibcon#about to read 6, iclass 24, count 2 2006.201.09:30:48.36#ibcon#read 6, iclass 24, count 2 2006.201.09:30:48.36#ibcon#end of sib2, iclass 24, count 2 2006.201.09:30:48.36#ibcon#*mode == 0, iclass 24, count 2 2006.201.09:30:48.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.09:30:48.36#ibcon#[25=AT02-07\r\n] 2006.201.09:30:48.36#ibcon#*before write, iclass 24, count 2 2006.201.09:30:48.36#ibcon#enter sib2, iclass 24, count 2 2006.201.09:30:48.36#ibcon#flushed, iclass 24, count 2 2006.201.09:30:48.36#ibcon#about to write, iclass 24, count 2 2006.201.09:30:48.36#ibcon#wrote, iclass 24, count 2 2006.201.09:30:48.36#ibcon#about to read 3, iclass 24, count 2 2006.201.09:30:48.39#ibcon#read 3, iclass 24, count 2 2006.201.09:30:48.39#ibcon#about to read 4, iclass 24, count 2 2006.201.09:30:48.39#ibcon#read 4, iclass 24, count 2 2006.201.09:30:48.39#ibcon#about to read 5, iclass 24, count 2 2006.201.09:30:48.39#ibcon#read 5, iclass 24, count 2 2006.201.09:30:48.39#ibcon#about to read 6, iclass 24, count 2 2006.201.09:30:48.39#ibcon#read 6, iclass 24, count 2 2006.201.09:30:48.39#ibcon#end of sib2, iclass 24, count 2 2006.201.09:30:48.39#ibcon#*after write, iclass 24, count 2 2006.201.09:30:48.39#ibcon#*before return 0, iclass 24, count 2 2006.201.09:30:48.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:48.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:48.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.09:30:48.39#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:48.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:48.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:48.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:48.51#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:30:48.51#ibcon#first serial, iclass 24, count 0 2006.201.09:30:48.51#ibcon#enter sib2, iclass 24, count 0 2006.201.09:30:48.51#ibcon#flushed, iclass 24, count 0 2006.201.09:30:48.51#ibcon#about to write, iclass 24, count 0 2006.201.09:30:48.51#ibcon#wrote, iclass 24, count 0 2006.201.09:30:48.51#ibcon#about to read 3, iclass 24, count 0 2006.201.09:30:48.53#ibcon#read 3, iclass 24, count 0 2006.201.09:30:48.53#ibcon#about to read 4, iclass 24, count 0 2006.201.09:30:48.53#ibcon#read 4, iclass 24, count 0 2006.201.09:30:48.53#ibcon#about to read 5, iclass 24, count 0 2006.201.09:30:48.53#ibcon#read 5, iclass 24, count 0 2006.201.09:30:48.53#ibcon#about to read 6, iclass 24, count 0 2006.201.09:30:48.53#ibcon#read 6, iclass 24, count 0 2006.201.09:30:48.53#ibcon#end of sib2, iclass 24, count 0 2006.201.09:30:48.53#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:30:48.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:30:48.53#ibcon#[25=USB\r\n] 2006.201.09:30:48.53#ibcon#*before write, iclass 24, count 0 2006.201.09:30:48.53#ibcon#enter sib2, iclass 24, count 0 2006.201.09:30:48.53#ibcon#flushed, iclass 24, count 0 2006.201.09:30:48.53#ibcon#about to write, iclass 24, count 0 2006.201.09:30:48.53#ibcon#wrote, iclass 24, count 0 2006.201.09:30:48.53#ibcon#about to read 3, iclass 24, count 0 2006.201.09:30:48.56#ibcon#read 3, iclass 24, count 0 2006.201.09:30:48.56#ibcon#about to read 4, iclass 24, count 0 2006.201.09:30:48.56#ibcon#read 4, iclass 24, count 0 2006.201.09:30:48.56#ibcon#about to read 5, iclass 24, count 0 2006.201.09:30:48.56#ibcon#read 5, iclass 24, count 0 2006.201.09:30:48.56#ibcon#about to read 6, iclass 24, count 0 2006.201.09:30:48.56#ibcon#read 6, iclass 24, count 0 2006.201.09:30:48.56#ibcon#end of sib2, iclass 24, count 0 2006.201.09:30:48.56#ibcon#*after write, iclass 24, count 0 2006.201.09:30:48.56#ibcon#*before return 0, iclass 24, count 0 2006.201.09:30:48.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:48.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:48.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:30:48.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:30:48.56$vck44/valo=3,564.99 2006.201.09:30:48.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.09:30:48.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.09:30:48.56#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:48.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:48.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:48.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:48.56#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:30:48.56#ibcon#first serial, iclass 26, count 0 2006.201.09:30:48.56#ibcon#enter sib2, iclass 26, count 0 2006.201.09:30:48.56#ibcon#flushed, iclass 26, count 0 2006.201.09:30:48.56#ibcon#about to write, iclass 26, count 0 2006.201.09:30:48.56#ibcon#wrote, iclass 26, count 0 2006.201.09:30:48.56#ibcon#about to read 3, iclass 26, count 0 2006.201.09:30:48.58#ibcon#read 3, iclass 26, count 0 2006.201.09:30:48.58#ibcon#about to read 4, iclass 26, count 0 2006.201.09:30:48.58#ibcon#read 4, iclass 26, count 0 2006.201.09:30:48.58#ibcon#about to read 5, iclass 26, count 0 2006.201.09:30:48.58#ibcon#read 5, iclass 26, count 0 2006.201.09:30:48.58#ibcon#about to read 6, iclass 26, count 0 2006.201.09:30:48.58#ibcon#read 6, iclass 26, count 0 2006.201.09:30:48.58#ibcon#end of sib2, iclass 26, count 0 2006.201.09:30:48.58#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:30:48.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:30:48.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:30:48.58#ibcon#*before write, iclass 26, count 0 2006.201.09:30:48.58#ibcon#enter sib2, iclass 26, count 0 2006.201.09:30:48.58#ibcon#flushed, iclass 26, count 0 2006.201.09:30:48.58#ibcon#about to write, iclass 26, count 0 2006.201.09:30:48.58#ibcon#wrote, iclass 26, count 0 2006.201.09:30:48.58#ibcon#about to read 3, iclass 26, count 0 2006.201.09:30:48.63#ibcon#read 3, iclass 26, count 0 2006.201.09:30:48.63#ibcon#about to read 4, iclass 26, count 0 2006.201.09:30:48.63#ibcon#read 4, iclass 26, count 0 2006.201.09:30:48.63#ibcon#about to read 5, iclass 26, count 0 2006.201.09:30:48.63#ibcon#read 5, iclass 26, count 0 2006.201.09:30:48.63#ibcon#about to read 6, iclass 26, count 0 2006.201.09:30:48.63#ibcon#read 6, iclass 26, count 0 2006.201.09:30:48.63#ibcon#end of sib2, iclass 26, count 0 2006.201.09:30:48.63#ibcon#*after write, iclass 26, count 0 2006.201.09:30:48.63#ibcon#*before return 0, iclass 26, count 0 2006.201.09:30:48.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:48.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:48.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:30:48.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:30:48.63$vck44/va=3,8 2006.201.09:30:48.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.09:30:48.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.09:30:48.63#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:48.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:48.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:48.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:48.68#ibcon#enter wrdev, iclass 28, count 2 2006.201.09:30:48.68#ibcon#first serial, iclass 28, count 2 2006.201.09:30:48.68#ibcon#enter sib2, iclass 28, count 2 2006.201.09:30:48.68#ibcon#flushed, iclass 28, count 2 2006.201.09:30:48.68#ibcon#about to write, iclass 28, count 2 2006.201.09:30:48.68#ibcon#wrote, iclass 28, count 2 2006.201.09:30:48.68#ibcon#about to read 3, iclass 28, count 2 2006.201.09:30:48.70#ibcon#read 3, iclass 28, count 2 2006.201.09:30:48.70#ibcon#about to read 4, iclass 28, count 2 2006.201.09:30:48.70#ibcon#read 4, iclass 28, count 2 2006.201.09:30:48.70#ibcon#about to read 5, iclass 28, count 2 2006.201.09:30:48.70#ibcon#read 5, iclass 28, count 2 2006.201.09:30:48.70#ibcon#about to read 6, iclass 28, count 2 2006.201.09:30:48.70#ibcon#read 6, iclass 28, count 2 2006.201.09:30:48.70#ibcon#end of sib2, iclass 28, count 2 2006.201.09:30:48.70#ibcon#*mode == 0, iclass 28, count 2 2006.201.09:30:48.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.09:30:48.70#ibcon#[25=AT03-08\r\n] 2006.201.09:30:48.70#ibcon#*before write, iclass 28, count 2 2006.201.09:30:48.70#ibcon#enter sib2, iclass 28, count 2 2006.201.09:30:48.70#ibcon#flushed, iclass 28, count 2 2006.201.09:30:48.70#ibcon#about to write, iclass 28, count 2 2006.201.09:30:48.70#ibcon#wrote, iclass 28, count 2 2006.201.09:30:48.70#ibcon#about to read 3, iclass 28, count 2 2006.201.09:30:48.73#ibcon#read 3, iclass 28, count 2 2006.201.09:30:48.73#ibcon#about to read 4, iclass 28, count 2 2006.201.09:30:48.73#ibcon#read 4, iclass 28, count 2 2006.201.09:30:48.73#ibcon#about to read 5, iclass 28, count 2 2006.201.09:30:48.73#ibcon#read 5, iclass 28, count 2 2006.201.09:30:48.73#ibcon#about to read 6, iclass 28, count 2 2006.201.09:30:48.73#ibcon#read 6, iclass 28, count 2 2006.201.09:30:48.73#ibcon#end of sib2, iclass 28, count 2 2006.201.09:30:48.73#ibcon#*after write, iclass 28, count 2 2006.201.09:30:48.73#ibcon#*before return 0, iclass 28, count 2 2006.201.09:30:48.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:48.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:48.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.09:30:48.73#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:48.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:48.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:48.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:48.85#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:30:48.85#ibcon#first serial, iclass 28, count 0 2006.201.09:30:48.85#ibcon#enter sib2, iclass 28, count 0 2006.201.09:30:48.85#ibcon#flushed, iclass 28, count 0 2006.201.09:30:48.85#ibcon#about to write, iclass 28, count 0 2006.201.09:30:48.85#ibcon#wrote, iclass 28, count 0 2006.201.09:30:48.85#ibcon#about to read 3, iclass 28, count 0 2006.201.09:30:48.87#ibcon#read 3, iclass 28, count 0 2006.201.09:30:48.87#ibcon#about to read 4, iclass 28, count 0 2006.201.09:30:48.87#ibcon#read 4, iclass 28, count 0 2006.201.09:30:48.87#ibcon#about to read 5, iclass 28, count 0 2006.201.09:30:48.87#ibcon#read 5, iclass 28, count 0 2006.201.09:30:48.87#ibcon#about to read 6, iclass 28, count 0 2006.201.09:30:48.87#ibcon#read 6, iclass 28, count 0 2006.201.09:30:48.87#ibcon#end of sib2, iclass 28, count 0 2006.201.09:30:48.87#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:30:48.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:30:48.87#ibcon#[25=USB\r\n] 2006.201.09:30:48.87#ibcon#*before write, iclass 28, count 0 2006.201.09:30:48.87#ibcon#enter sib2, iclass 28, count 0 2006.201.09:30:48.87#ibcon#flushed, iclass 28, count 0 2006.201.09:30:48.87#ibcon#about to write, iclass 28, count 0 2006.201.09:30:48.87#ibcon#wrote, iclass 28, count 0 2006.201.09:30:48.87#ibcon#about to read 3, iclass 28, count 0 2006.201.09:30:48.90#ibcon#read 3, iclass 28, count 0 2006.201.09:30:48.90#ibcon#about to read 4, iclass 28, count 0 2006.201.09:30:48.90#ibcon#read 4, iclass 28, count 0 2006.201.09:30:48.90#ibcon#about to read 5, iclass 28, count 0 2006.201.09:30:48.90#ibcon#read 5, iclass 28, count 0 2006.201.09:30:48.90#ibcon#about to read 6, iclass 28, count 0 2006.201.09:30:48.90#ibcon#read 6, iclass 28, count 0 2006.201.09:30:48.90#ibcon#end of sib2, iclass 28, count 0 2006.201.09:30:48.90#ibcon#*after write, iclass 28, count 0 2006.201.09:30:48.90#ibcon#*before return 0, iclass 28, count 0 2006.201.09:30:48.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:48.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:48.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:30:48.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:30:48.90$vck44/valo=4,624.99 2006.201.09:30:48.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.09:30:48.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.09:30:48.90#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:48.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:48.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:48.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:48.90#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:30:48.90#ibcon#first serial, iclass 30, count 0 2006.201.09:30:48.90#ibcon#enter sib2, iclass 30, count 0 2006.201.09:30:48.90#ibcon#flushed, iclass 30, count 0 2006.201.09:30:48.90#ibcon#about to write, iclass 30, count 0 2006.201.09:30:48.90#ibcon#wrote, iclass 30, count 0 2006.201.09:30:48.90#ibcon#about to read 3, iclass 30, count 0 2006.201.09:30:48.92#ibcon#read 3, iclass 30, count 0 2006.201.09:30:48.92#ibcon#about to read 4, iclass 30, count 0 2006.201.09:30:48.92#ibcon#read 4, iclass 30, count 0 2006.201.09:30:48.92#ibcon#about to read 5, iclass 30, count 0 2006.201.09:30:48.92#ibcon#read 5, iclass 30, count 0 2006.201.09:30:48.92#ibcon#about to read 6, iclass 30, count 0 2006.201.09:30:48.92#ibcon#read 6, iclass 30, count 0 2006.201.09:30:48.92#ibcon#end of sib2, iclass 30, count 0 2006.201.09:30:48.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:30:48.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:30:48.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:30:48.92#ibcon#*before write, iclass 30, count 0 2006.201.09:30:48.92#ibcon#enter sib2, iclass 30, count 0 2006.201.09:30:48.92#ibcon#flushed, iclass 30, count 0 2006.201.09:30:48.92#ibcon#about to write, iclass 30, count 0 2006.201.09:30:48.92#ibcon#wrote, iclass 30, count 0 2006.201.09:30:48.92#ibcon#about to read 3, iclass 30, count 0 2006.201.09:30:48.97#ibcon#read 3, iclass 30, count 0 2006.201.09:30:48.97#ibcon#about to read 4, iclass 30, count 0 2006.201.09:30:48.97#ibcon#read 4, iclass 30, count 0 2006.201.09:30:48.97#ibcon#about to read 5, iclass 30, count 0 2006.201.09:30:48.97#ibcon#read 5, iclass 30, count 0 2006.201.09:30:48.97#ibcon#about to read 6, iclass 30, count 0 2006.201.09:30:48.97#ibcon#read 6, iclass 30, count 0 2006.201.09:30:48.97#ibcon#end of sib2, iclass 30, count 0 2006.201.09:30:48.97#ibcon#*after write, iclass 30, count 0 2006.201.09:30:48.97#ibcon#*before return 0, iclass 30, count 0 2006.201.09:30:48.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:48.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:48.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:30:48.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:30:48.97$vck44/va=4,7 2006.201.09:30:48.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.09:30:48.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.09:30:48.97#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:48.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:49.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:49.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:49.02#ibcon#enter wrdev, iclass 32, count 2 2006.201.09:30:49.02#ibcon#first serial, iclass 32, count 2 2006.201.09:30:49.02#ibcon#enter sib2, iclass 32, count 2 2006.201.09:30:49.02#ibcon#flushed, iclass 32, count 2 2006.201.09:30:49.02#ibcon#about to write, iclass 32, count 2 2006.201.09:30:49.02#ibcon#wrote, iclass 32, count 2 2006.201.09:30:49.02#ibcon#about to read 3, iclass 32, count 2 2006.201.09:30:49.04#ibcon#read 3, iclass 32, count 2 2006.201.09:30:49.04#ibcon#about to read 4, iclass 32, count 2 2006.201.09:30:49.04#ibcon#read 4, iclass 32, count 2 2006.201.09:30:49.04#ibcon#about to read 5, iclass 32, count 2 2006.201.09:30:49.04#ibcon#read 5, iclass 32, count 2 2006.201.09:30:49.04#ibcon#about to read 6, iclass 32, count 2 2006.201.09:30:49.04#ibcon#read 6, iclass 32, count 2 2006.201.09:30:49.04#ibcon#end of sib2, iclass 32, count 2 2006.201.09:30:49.04#ibcon#*mode == 0, iclass 32, count 2 2006.201.09:30:49.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.09:30:49.04#ibcon#[25=AT04-07\r\n] 2006.201.09:30:49.04#ibcon#*before write, iclass 32, count 2 2006.201.09:30:49.04#ibcon#enter sib2, iclass 32, count 2 2006.201.09:30:49.04#ibcon#flushed, iclass 32, count 2 2006.201.09:30:49.04#ibcon#about to write, iclass 32, count 2 2006.201.09:30:49.04#ibcon#wrote, iclass 32, count 2 2006.201.09:30:49.04#ibcon#about to read 3, iclass 32, count 2 2006.201.09:30:49.07#ibcon#read 3, iclass 32, count 2 2006.201.09:30:49.07#ibcon#about to read 4, iclass 32, count 2 2006.201.09:30:49.07#ibcon#read 4, iclass 32, count 2 2006.201.09:30:49.07#ibcon#about to read 5, iclass 32, count 2 2006.201.09:30:49.07#ibcon#read 5, iclass 32, count 2 2006.201.09:30:49.07#ibcon#about to read 6, iclass 32, count 2 2006.201.09:30:49.07#ibcon#read 6, iclass 32, count 2 2006.201.09:30:49.07#ibcon#end of sib2, iclass 32, count 2 2006.201.09:30:49.07#ibcon#*after write, iclass 32, count 2 2006.201.09:30:49.07#ibcon#*before return 0, iclass 32, count 2 2006.201.09:30:49.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:49.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:49.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.09:30:49.07#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:49.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:49.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:49.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:49.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:30:49.19#ibcon#first serial, iclass 32, count 0 2006.201.09:30:49.19#ibcon#enter sib2, iclass 32, count 0 2006.201.09:30:49.19#ibcon#flushed, iclass 32, count 0 2006.201.09:30:49.19#ibcon#about to write, iclass 32, count 0 2006.201.09:30:49.19#ibcon#wrote, iclass 32, count 0 2006.201.09:30:49.19#ibcon#about to read 3, iclass 32, count 0 2006.201.09:30:49.21#ibcon#read 3, iclass 32, count 0 2006.201.09:30:49.21#ibcon#about to read 4, iclass 32, count 0 2006.201.09:30:49.21#ibcon#read 4, iclass 32, count 0 2006.201.09:30:49.21#ibcon#about to read 5, iclass 32, count 0 2006.201.09:30:49.21#ibcon#read 5, iclass 32, count 0 2006.201.09:30:49.21#ibcon#about to read 6, iclass 32, count 0 2006.201.09:30:49.21#ibcon#read 6, iclass 32, count 0 2006.201.09:30:49.21#ibcon#end of sib2, iclass 32, count 0 2006.201.09:30:49.21#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:30:49.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:30:49.21#ibcon#[25=USB\r\n] 2006.201.09:30:49.21#ibcon#*before write, iclass 32, count 0 2006.201.09:30:49.21#ibcon#enter sib2, iclass 32, count 0 2006.201.09:30:49.21#ibcon#flushed, iclass 32, count 0 2006.201.09:30:49.21#ibcon#about to write, iclass 32, count 0 2006.201.09:30:49.21#ibcon#wrote, iclass 32, count 0 2006.201.09:30:49.21#ibcon#about to read 3, iclass 32, count 0 2006.201.09:30:49.24#ibcon#read 3, iclass 32, count 0 2006.201.09:30:49.24#ibcon#about to read 4, iclass 32, count 0 2006.201.09:30:49.24#ibcon#read 4, iclass 32, count 0 2006.201.09:30:49.24#ibcon#about to read 5, iclass 32, count 0 2006.201.09:30:49.24#ibcon#read 5, iclass 32, count 0 2006.201.09:30:49.24#ibcon#about to read 6, iclass 32, count 0 2006.201.09:30:49.24#ibcon#read 6, iclass 32, count 0 2006.201.09:30:49.24#ibcon#end of sib2, iclass 32, count 0 2006.201.09:30:49.24#ibcon#*after write, iclass 32, count 0 2006.201.09:30:49.24#ibcon#*before return 0, iclass 32, count 0 2006.201.09:30:49.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:49.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:49.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:30:49.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:30:49.24$vck44/valo=5,734.99 2006.201.09:30:49.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.09:30:49.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.09:30:49.24#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:49.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:49.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:49.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:49.24#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:30:49.24#ibcon#first serial, iclass 34, count 0 2006.201.09:30:49.24#ibcon#enter sib2, iclass 34, count 0 2006.201.09:30:49.24#ibcon#flushed, iclass 34, count 0 2006.201.09:30:49.24#ibcon#about to write, iclass 34, count 0 2006.201.09:30:49.24#ibcon#wrote, iclass 34, count 0 2006.201.09:30:49.24#ibcon#about to read 3, iclass 34, count 0 2006.201.09:30:49.26#ibcon#read 3, iclass 34, count 0 2006.201.09:30:49.26#ibcon#about to read 4, iclass 34, count 0 2006.201.09:30:49.26#ibcon#read 4, iclass 34, count 0 2006.201.09:30:49.26#ibcon#about to read 5, iclass 34, count 0 2006.201.09:30:49.26#ibcon#read 5, iclass 34, count 0 2006.201.09:30:49.26#ibcon#about to read 6, iclass 34, count 0 2006.201.09:30:49.26#ibcon#read 6, iclass 34, count 0 2006.201.09:30:49.26#ibcon#end of sib2, iclass 34, count 0 2006.201.09:30:49.26#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:30:49.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:30:49.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:30:49.26#ibcon#*before write, iclass 34, count 0 2006.201.09:30:49.26#ibcon#enter sib2, iclass 34, count 0 2006.201.09:30:49.26#ibcon#flushed, iclass 34, count 0 2006.201.09:30:49.26#ibcon#about to write, iclass 34, count 0 2006.201.09:30:49.26#ibcon#wrote, iclass 34, count 0 2006.201.09:30:49.26#ibcon#about to read 3, iclass 34, count 0 2006.201.09:30:49.30#ibcon#read 3, iclass 34, count 0 2006.201.09:30:49.30#ibcon#about to read 4, iclass 34, count 0 2006.201.09:30:49.30#ibcon#read 4, iclass 34, count 0 2006.201.09:30:49.30#ibcon#about to read 5, iclass 34, count 0 2006.201.09:30:49.30#ibcon#read 5, iclass 34, count 0 2006.201.09:30:49.30#ibcon#about to read 6, iclass 34, count 0 2006.201.09:30:49.30#ibcon#read 6, iclass 34, count 0 2006.201.09:30:49.30#ibcon#end of sib2, iclass 34, count 0 2006.201.09:30:49.30#ibcon#*after write, iclass 34, count 0 2006.201.09:30:49.30#ibcon#*before return 0, iclass 34, count 0 2006.201.09:30:49.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:49.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:49.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:30:49.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:30:49.30$vck44/va=5,4 2006.201.09:30:49.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.09:30:49.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.09:30:49.30#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:49.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:49.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:49.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:49.36#ibcon#enter wrdev, iclass 36, count 2 2006.201.09:30:49.36#ibcon#first serial, iclass 36, count 2 2006.201.09:30:49.36#ibcon#enter sib2, iclass 36, count 2 2006.201.09:30:49.36#ibcon#flushed, iclass 36, count 2 2006.201.09:30:49.36#ibcon#about to write, iclass 36, count 2 2006.201.09:30:49.36#ibcon#wrote, iclass 36, count 2 2006.201.09:30:49.36#ibcon#about to read 3, iclass 36, count 2 2006.201.09:30:49.38#ibcon#read 3, iclass 36, count 2 2006.201.09:30:49.38#ibcon#about to read 4, iclass 36, count 2 2006.201.09:30:49.38#ibcon#read 4, iclass 36, count 2 2006.201.09:30:49.38#ibcon#about to read 5, iclass 36, count 2 2006.201.09:30:49.38#ibcon#read 5, iclass 36, count 2 2006.201.09:30:49.38#ibcon#about to read 6, iclass 36, count 2 2006.201.09:30:49.38#ibcon#read 6, iclass 36, count 2 2006.201.09:30:49.38#ibcon#end of sib2, iclass 36, count 2 2006.201.09:30:49.38#ibcon#*mode == 0, iclass 36, count 2 2006.201.09:30:49.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.09:30:49.38#ibcon#[25=AT05-04\r\n] 2006.201.09:30:49.38#ibcon#*before write, iclass 36, count 2 2006.201.09:30:49.38#ibcon#enter sib2, iclass 36, count 2 2006.201.09:30:49.38#ibcon#flushed, iclass 36, count 2 2006.201.09:30:49.38#ibcon#about to write, iclass 36, count 2 2006.201.09:30:49.38#ibcon#wrote, iclass 36, count 2 2006.201.09:30:49.38#ibcon#about to read 3, iclass 36, count 2 2006.201.09:30:49.41#ibcon#read 3, iclass 36, count 2 2006.201.09:30:49.41#ibcon#about to read 4, iclass 36, count 2 2006.201.09:30:49.41#ibcon#read 4, iclass 36, count 2 2006.201.09:30:49.41#ibcon#about to read 5, iclass 36, count 2 2006.201.09:30:49.41#ibcon#read 5, iclass 36, count 2 2006.201.09:30:49.41#ibcon#about to read 6, iclass 36, count 2 2006.201.09:30:49.41#ibcon#read 6, iclass 36, count 2 2006.201.09:30:49.41#ibcon#end of sib2, iclass 36, count 2 2006.201.09:30:49.41#ibcon#*after write, iclass 36, count 2 2006.201.09:30:49.41#ibcon#*before return 0, iclass 36, count 2 2006.201.09:30:49.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:49.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:49.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.09:30:49.41#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:49.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:49.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:49.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:49.53#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:30:49.53#ibcon#first serial, iclass 36, count 0 2006.201.09:30:49.53#ibcon#enter sib2, iclass 36, count 0 2006.201.09:30:49.53#ibcon#flushed, iclass 36, count 0 2006.201.09:30:49.53#ibcon#about to write, iclass 36, count 0 2006.201.09:30:49.53#ibcon#wrote, iclass 36, count 0 2006.201.09:30:49.53#ibcon#about to read 3, iclass 36, count 0 2006.201.09:30:49.55#ibcon#read 3, iclass 36, count 0 2006.201.09:30:49.55#ibcon#about to read 4, iclass 36, count 0 2006.201.09:30:49.55#ibcon#read 4, iclass 36, count 0 2006.201.09:30:49.55#ibcon#about to read 5, iclass 36, count 0 2006.201.09:30:49.55#ibcon#read 5, iclass 36, count 0 2006.201.09:30:49.55#ibcon#about to read 6, iclass 36, count 0 2006.201.09:30:49.55#ibcon#read 6, iclass 36, count 0 2006.201.09:30:49.55#ibcon#end of sib2, iclass 36, count 0 2006.201.09:30:49.55#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:30:49.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:30:49.55#ibcon#[25=USB\r\n] 2006.201.09:30:49.55#ibcon#*before write, iclass 36, count 0 2006.201.09:30:49.55#ibcon#enter sib2, iclass 36, count 0 2006.201.09:30:49.55#ibcon#flushed, iclass 36, count 0 2006.201.09:30:49.55#ibcon#about to write, iclass 36, count 0 2006.201.09:30:49.55#ibcon#wrote, iclass 36, count 0 2006.201.09:30:49.55#ibcon#about to read 3, iclass 36, count 0 2006.201.09:30:49.58#ibcon#read 3, iclass 36, count 0 2006.201.09:30:49.58#ibcon#about to read 4, iclass 36, count 0 2006.201.09:30:49.58#ibcon#read 4, iclass 36, count 0 2006.201.09:30:49.58#ibcon#about to read 5, iclass 36, count 0 2006.201.09:30:49.58#ibcon#read 5, iclass 36, count 0 2006.201.09:30:49.58#ibcon#about to read 6, iclass 36, count 0 2006.201.09:30:49.58#ibcon#read 6, iclass 36, count 0 2006.201.09:30:49.58#ibcon#end of sib2, iclass 36, count 0 2006.201.09:30:49.58#ibcon#*after write, iclass 36, count 0 2006.201.09:30:49.58#ibcon#*before return 0, iclass 36, count 0 2006.201.09:30:49.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:49.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:49.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:30:49.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:30:49.58$vck44/valo=6,814.99 2006.201.09:30:49.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.09:30:49.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.09:30:49.58#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:49.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:49.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:49.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:49.58#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:30:49.58#ibcon#first serial, iclass 38, count 0 2006.201.09:30:49.58#ibcon#enter sib2, iclass 38, count 0 2006.201.09:30:49.58#ibcon#flushed, iclass 38, count 0 2006.201.09:30:49.58#ibcon#about to write, iclass 38, count 0 2006.201.09:30:49.58#ibcon#wrote, iclass 38, count 0 2006.201.09:30:49.58#ibcon#about to read 3, iclass 38, count 0 2006.201.09:30:49.60#ibcon#read 3, iclass 38, count 0 2006.201.09:30:49.60#ibcon#about to read 4, iclass 38, count 0 2006.201.09:30:49.60#ibcon#read 4, iclass 38, count 0 2006.201.09:30:49.60#ibcon#about to read 5, iclass 38, count 0 2006.201.09:30:49.60#ibcon#read 5, iclass 38, count 0 2006.201.09:30:49.60#ibcon#about to read 6, iclass 38, count 0 2006.201.09:30:49.60#ibcon#read 6, iclass 38, count 0 2006.201.09:30:49.60#ibcon#end of sib2, iclass 38, count 0 2006.201.09:30:49.60#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:30:49.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:30:49.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:30:49.60#ibcon#*before write, iclass 38, count 0 2006.201.09:30:49.60#ibcon#enter sib2, iclass 38, count 0 2006.201.09:30:49.60#ibcon#flushed, iclass 38, count 0 2006.201.09:30:49.60#ibcon#about to write, iclass 38, count 0 2006.201.09:30:49.60#ibcon#wrote, iclass 38, count 0 2006.201.09:30:49.60#ibcon#about to read 3, iclass 38, count 0 2006.201.09:30:49.64#ibcon#read 3, iclass 38, count 0 2006.201.09:30:49.64#ibcon#about to read 4, iclass 38, count 0 2006.201.09:30:49.64#ibcon#read 4, iclass 38, count 0 2006.201.09:30:49.64#ibcon#about to read 5, iclass 38, count 0 2006.201.09:30:49.64#ibcon#read 5, iclass 38, count 0 2006.201.09:30:49.64#ibcon#about to read 6, iclass 38, count 0 2006.201.09:30:49.64#ibcon#read 6, iclass 38, count 0 2006.201.09:30:49.64#ibcon#end of sib2, iclass 38, count 0 2006.201.09:30:49.64#ibcon#*after write, iclass 38, count 0 2006.201.09:30:49.64#ibcon#*before return 0, iclass 38, count 0 2006.201.09:30:49.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:49.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:49.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:30:49.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:30:49.64$vck44/va=6,5 2006.201.09:30:49.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.09:30:49.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.09:30:49.64#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:49.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:49.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:49.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:49.70#ibcon#enter wrdev, iclass 40, count 2 2006.201.09:30:49.70#ibcon#first serial, iclass 40, count 2 2006.201.09:30:49.70#ibcon#enter sib2, iclass 40, count 2 2006.201.09:30:49.70#ibcon#flushed, iclass 40, count 2 2006.201.09:30:49.70#ibcon#about to write, iclass 40, count 2 2006.201.09:30:49.70#ibcon#wrote, iclass 40, count 2 2006.201.09:30:49.70#ibcon#about to read 3, iclass 40, count 2 2006.201.09:30:49.72#ibcon#read 3, iclass 40, count 2 2006.201.09:30:49.72#ibcon#about to read 4, iclass 40, count 2 2006.201.09:30:49.72#ibcon#read 4, iclass 40, count 2 2006.201.09:30:49.72#ibcon#about to read 5, iclass 40, count 2 2006.201.09:30:49.72#ibcon#read 5, iclass 40, count 2 2006.201.09:30:49.72#ibcon#about to read 6, iclass 40, count 2 2006.201.09:30:49.72#ibcon#read 6, iclass 40, count 2 2006.201.09:30:49.72#ibcon#end of sib2, iclass 40, count 2 2006.201.09:30:49.72#ibcon#*mode == 0, iclass 40, count 2 2006.201.09:30:49.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.09:30:49.72#ibcon#[25=AT06-05\r\n] 2006.201.09:30:49.72#ibcon#*before write, iclass 40, count 2 2006.201.09:30:49.72#ibcon#enter sib2, iclass 40, count 2 2006.201.09:30:49.72#ibcon#flushed, iclass 40, count 2 2006.201.09:30:49.72#ibcon#about to write, iclass 40, count 2 2006.201.09:30:49.72#ibcon#wrote, iclass 40, count 2 2006.201.09:30:49.72#ibcon#about to read 3, iclass 40, count 2 2006.201.09:30:49.75#ibcon#read 3, iclass 40, count 2 2006.201.09:30:49.75#ibcon#about to read 4, iclass 40, count 2 2006.201.09:30:49.75#ibcon#read 4, iclass 40, count 2 2006.201.09:30:49.75#ibcon#about to read 5, iclass 40, count 2 2006.201.09:30:49.75#ibcon#read 5, iclass 40, count 2 2006.201.09:30:49.75#ibcon#about to read 6, iclass 40, count 2 2006.201.09:30:49.75#ibcon#read 6, iclass 40, count 2 2006.201.09:30:49.75#ibcon#end of sib2, iclass 40, count 2 2006.201.09:30:49.75#ibcon#*after write, iclass 40, count 2 2006.201.09:30:49.75#ibcon#*before return 0, iclass 40, count 2 2006.201.09:30:49.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:49.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:49.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.09:30:49.75#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:49.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:49.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:49.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:49.87#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:30:49.87#ibcon#first serial, iclass 40, count 0 2006.201.09:30:49.87#ibcon#enter sib2, iclass 40, count 0 2006.201.09:30:49.87#ibcon#flushed, iclass 40, count 0 2006.201.09:30:49.87#ibcon#about to write, iclass 40, count 0 2006.201.09:30:49.87#ibcon#wrote, iclass 40, count 0 2006.201.09:30:49.87#ibcon#about to read 3, iclass 40, count 0 2006.201.09:30:49.89#ibcon#read 3, iclass 40, count 0 2006.201.09:30:49.89#ibcon#about to read 4, iclass 40, count 0 2006.201.09:30:49.89#ibcon#read 4, iclass 40, count 0 2006.201.09:30:49.89#ibcon#about to read 5, iclass 40, count 0 2006.201.09:30:49.89#ibcon#read 5, iclass 40, count 0 2006.201.09:30:49.89#ibcon#about to read 6, iclass 40, count 0 2006.201.09:30:49.89#ibcon#read 6, iclass 40, count 0 2006.201.09:30:49.89#ibcon#end of sib2, iclass 40, count 0 2006.201.09:30:49.89#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:30:49.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:30:49.89#ibcon#[25=USB\r\n] 2006.201.09:30:49.89#ibcon#*before write, iclass 40, count 0 2006.201.09:30:49.89#ibcon#enter sib2, iclass 40, count 0 2006.201.09:30:49.89#ibcon#flushed, iclass 40, count 0 2006.201.09:30:49.89#ibcon#about to write, iclass 40, count 0 2006.201.09:30:49.89#ibcon#wrote, iclass 40, count 0 2006.201.09:30:49.89#ibcon#about to read 3, iclass 40, count 0 2006.201.09:30:49.92#ibcon#read 3, iclass 40, count 0 2006.201.09:30:49.92#ibcon#about to read 4, iclass 40, count 0 2006.201.09:30:49.92#ibcon#read 4, iclass 40, count 0 2006.201.09:30:49.92#ibcon#about to read 5, iclass 40, count 0 2006.201.09:30:49.92#ibcon#read 5, iclass 40, count 0 2006.201.09:30:49.92#ibcon#about to read 6, iclass 40, count 0 2006.201.09:30:49.92#ibcon#read 6, iclass 40, count 0 2006.201.09:30:49.92#ibcon#end of sib2, iclass 40, count 0 2006.201.09:30:49.92#ibcon#*after write, iclass 40, count 0 2006.201.09:30:49.92#ibcon#*before return 0, iclass 40, count 0 2006.201.09:30:49.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:49.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:49.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:30:49.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:30:49.92$vck44/valo=7,864.99 2006.201.09:30:49.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.09:30:49.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.09:30:49.92#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:49.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:49.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:49.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:49.92#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:30:49.92#ibcon#first serial, iclass 4, count 0 2006.201.09:30:49.92#ibcon#enter sib2, iclass 4, count 0 2006.201.09:30:49.92#ibcon#flushed, iclass 4, count 0 2006.201.09:30:49.92#ibcon#about to write, iclass 4, count 0 2006.201.09:30:49.92#ibcon#wrote, iclass 4, count 0 2006.201.09:30:49.92#ibcon#about to read 3, iclass 4, count 0 2006.201.09:30:49.94#ibcon#read 3, iclass 4, count 0 2006.201.09:30:49.94#ibcon#about to read 4, iclass 4, count 0 2006.201.09:30:49.94#ibcon#read 4, iclass 4, count 0 2006.201.09:30:49.94#ibcon#about to read 5, iclass 4, count 0 2006.201.09:30:49.94#ibcon#read 5, iclass 4, count 0 2006.201.09:30:49.94#ibcon#about to read 6, iclass 4, count 0 2006.201.09:30:49.94#ibcon#read 6, iclass 4, count 0 2006.201.09:30:49.94#ibcon#end of sib2, iclass 4, count 0 2006.201.09:30:49.94#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:30:49.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:30:49.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:30:49.94#ibcon#*before write, iclass 4, count 0 2006.201.09:30:49.94#ibcon#enter sib2, iclass 4, count 0 2006.201.09:30:49.94#ibcon#flushed, iclass 4, count 0 2006.201.09:30:49.94#ibcon#about to write, iclass 4, count 0 2006.201.09:30:49.94#ibcon#wrote, iclass 4, count 0 2006.201.09:30:49.94#ibcon#about to read 3, iclass 4, count 0 2006.201.09:30:49.99#ibcon#read 3, iclass 4, count 0 2006.201.09:30:49.99#ibcon#about to read 4, iclass 4, count 0 2006.201.09:30:49.99#ibcon#read 4, iclass 4, count 0 2006.201.09:30:49.99#ibcon#about to read 5, iclass 4, count 0 2006.201.09:30:49.99#ibcon#read 5, iclass 4, count 0 2006.201.09:30:49.99#ibcon#about to read 6, iclass 4, count 0 2006.201.09:30:49.99#ibcon#read 6, iclass 4, count 0 2006.201.09:30:49.99#ibcon#end of sib2, iclass 4, count 0 2006.201.09:30:49.99#ibcon#*after write, iclass 4, count 0 2006.201.09:30:49.99#ibcon#*before return 0, iclass 4, count 0 2006.201.09:30:49.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:49.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:49.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:30:49.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:30:49.99$vck44/va=7,5 2006.201.09:30:49.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.09:30:49.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.09:30:49.99#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:49.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:50.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:50.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:50.04#ibcon#enter wrdev, iclass 6, count 2 2006.201.09:30:50.04#ibcon#first serial, iclass 6, count 2 2006.201.09:30:50.04#ibcon#enter sib2, iclass 6, count 2 2006.201.09:30:50.04#ibcon#flushed, iclass 6, count 2 2006.201.09:30:50.04#ibcon#about to write, iclass 6, count 2 2006.201.09:30:50.04#ibcon#wrote, iclass 6, count 2 2006.201.09:30:50.04#ibcon#about to read 3, iclass 6, count 2 2006.201.09:30:50.06#ibcon#read 3, iclass 6, count 2 2006.201.09:30:50.06#ibcon#about to read 4, iclass 6, count 2 2006.201.09:30:50.06#ibcon#read 4, iclass 6, count 2 2006.201.09:30:50.06#ibcon#about to read 5, iclass 6, count 2 2006.201.09:30:50.06#ibcon#read 5, iclass 6, count 2 2006.201.09:30:50.06#ibcon#about to read 6, iclass 6, count 2 2006.201.09:30:50.06#ibcon#read 6, iclass 6, count 2 2006.201.09:30:50.06#ibcon#end of sib2, iclass 6, count 2 2006.201.09:30:50.06#ibcon#*mode == 0, iclass 6, count 2 2006.201.09:30:50.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.09:30:50.06#ibcon#[25=AT07-05\r\n] 2006.201.09:30:50.06#ibcon#*before write, iclass 6, count 2 2006.201.09:30:50.06#ibcon#enter sib2, iclass 6, count 2 2006.201.09:30:50.06#ibcon#flushed, iclass 6, count 2 2006.201.09:30:50.06#ibcon#about to write, iclass 6, count 2 2006.201.09:30:50.06#ibcon#wrote, iclass 6, count 2 2006.201.09:30:50.06#ibcon#about to read 3, iclass 6, count 2 2006.201.09:30:50.09#ibcon#read 3, iclass 6, count 2 2006.201.09:30:50.09#ibcon#about to read 4, iclass 6, count 2 2006.201.09:30:50.09#ibcon#read 4, iclass 6, count 2 2006.201.09:30:50.09#ibcon#about to read 5, iclass 6, count 2 2006.201.09:30:50.09#ibcon#read 5, iclass 6, count 2 2006.201.09:30:50.09#ibcon#about to read 6, iclass 6, count 2 2006.201.09:30:50.09#ibcon#read 6, iclass 6, count 2 2006.201.09:30:50.09#ibcon#end of sib2, iclass 6, count 2 2006.201.09:30:50.09#ibcon#*after write, iclass 6, count 2 2006.201.09:30:50.09#ibcon#*before return 0, iclass 6, count 2 2006.201.09:30:50.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:50.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:50.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.09:30:50.09#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:50.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:50.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:50.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:50.21#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:30:50.21#ibcon#first serial, iclass 6, count 0 2006.201.09:30:50.21#ibcon#enter sib2, iclass 6, count 0 2006.201.09:30:50.21#ibcon#flushed, iclass 6, count 0 2006.201.09:30:50.21#ibcon#about to write, iclass 6, count 0 2006.201.09:30:50.21#ibcon#wrote, iclass 6, count 0 2006.201.09:30:50.21#ibcon#about to read 3, iclass 6, count 0 2006.201.09:30:50.23#ibcon#read 3, iclass 6, count 0 2006.201.09:30:50.23#ibcon#about to read 4, iclass 6, count 0 2006.201.09:30:50.23#ibcon#read 4, iclass 6, count 0 2006.201.09:30:50.23#ibcon#about to read 5, iclass 6, count 0 2006.201.09:30:50.23#ibcon#read 5, iclass 6, count 0 2006.201.09:30:50.23#ibcon#about to read 6, iclass 6, count 0 2006.201.09:30:50.23#ibcon#read 6, iclass 6, count 0 2006.201.09:30:50.23#ibcon#end of sib2, iclass 6, count 0 2006.201.09:30:50.23#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:30:50.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:30:50.23#ibcon#[25=USB\r\n] 2006.201.09:30:50.23#ibcon#*before write, iclass 6, count 0 2006.201.09:30:50.23#ibcon#enter sib2, iclass 6, count 0 2006.201.09:30:50.23#ibcon#flushed, iclass 6, count 0 2006.201.09:30:50.23#ibcon#about to write, iclass 6, count 0 2006.201.09:30:50.23#ibcon#wrote, iclass 6, count 0 2006.201.09:30:50.23#ibcon#about to read 3, iclass 6, count 0 2006.201.09:30:50.26#ibcon#read 3, iclass 6, count 0 2006.201.09:30:50.26#ibcon#about to read 4, iclass 6, count 0 2006.201.09:30:50.26#ibcon#read 4, iclass 6, count 0 2006.201.09:30:50.26#ibcon#about to read 5, iclass 6, count 0 2006.201.09:30:50.26#ibcon#read 5, iclass 6, count 0 2006.201.09:30:50.26#ibcon#about to read 6, iclass 6, count 0 2006.201.09:30:50.26#ibcon#read 6, iclass 6, count 0 2006.201.09:30:50.26#ibcon#end of sib2, iclass 6, count 0 2006.201.09:30:50.26#ibcon#*after write, iclass 6, count 0 2006.201.09:30:50.26#ibcon#*before return 0, iclass 6, count 0 2006.201.09:30:50.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:50.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:50.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:30:50.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:30:50.26$vck44/valo=8,884.99 2006.201.09:30:50.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.09:30:50.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.09:30:50.26#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:50.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:50.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:50.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:50.26#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:30:50.26#ibcon#first serial, iclass 10, count 0 2006.201.09:30:50.26#ibcon#enter sib2, iclass 10, count 0 2006.201.09:30:50.26#ibcon#flushed, iclass 10, count 0 2006.201.09:30:50.26#ibcon#about to write, iclass 10, count 0 2006.201.09:30:50.26#ibcon#wrote, iclass 10, count 0 2006.201.09:30:50.26#ibcon#about to read 3, iclass 10, count 0 2006.201.09:30:50.28#ibcon#read 3, iclass 10, count 0 2006.201.09:30:50.28#ibcon#about to read 4, iclass 10, count 0 2006.201.09:30:50.28#ibcon#read 4, iclass 10, count 0 2006.201.09:30:50.28#ibcon#about to read 5, iclass 10, count 0 2006.201.09:30:50.28#ibcon#read 5, iclass 10, count 0 2006.201.09:30:50.28#ibcon#about to read 6, iclass 10, count 0 2006.201.09:30:50.28#ibcon#read 6, iclass 10, count 0 2006.201.09:30:50.28#ibcon#end of sib2, iclass 10, count 0 2006.201.09:30:50.28#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:30:50.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:30:50.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:30:50.28#ibcon#*before write, iclass 10, count 0 2006.201.09:30:50.28#ibcon#enter sib2, iclass 10, count 0 2006.201.09:30:50.28#ibcon#flushed, iclass 10, count 0 2006.201.09:30:50.28#ibcon#about to write, iclass 10, count 0 2006.201.09:30:50.28#ibcon#wrote, iclass 10, count 0 2006.201.09:30:50.28#ibcon#about to read 3, iclass 10, count 0 2006.201.09:30:50.32#ibcon#read 3, iclass 10, count 0 2006.201.09:30:50.32#ibcon#about to read 4, iclass 10, count 0 2006.201.09:30:50.32#ibcon#read 4, iclass 10, count 0 2006.201.09:30:50.32#ibcon#about to read 5, iclass 10, count 0 2006.201.09:30:50.32#ibcon#read 5, iclass 10, count 0 2006.201.09:30:50.32#ibcon#about to read 6, iclass 10, count 0 2006.201.09:30:50.32#ibcon#read 6, iclass 10, count 0 2006.201.09:30:50.32#ibcon#end of sib2, iclass 10, count 0 2006.201.09:30:50.32#ibcon#*after write, iclass 10, count 0 2006.201.09:30:50.32#ibcon#*before return 0, iclass 10, count 0 2006.201.09:30:50.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:50.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:50.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:30:50.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:30:50.32$vck44/va=8,4 2006.201.09:30:50.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.09:30:50.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.09:30:50.32#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:50.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:30:50.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:30:50.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:30:50.38#ibcon#enter wrdev, iclass 12, count 2 2006.201.09:30:50.38#ibcon#first serial, iclass 12, count 2 2006.201.09:30:50.38#ibcon#enter sib2, iclass 12, count 2 2006.201.09:30:50.38#ibcon#flushed, iclass 12, count 2 2006.201.09:30:50.38#ibcon#about to write, iclass 12, count 2 2006.201.09:30:50.38#ibcon#wrote, iclass 12, count 2 2006.201.09:30:50.38#ibcon#about to read 3, iclass 12, count 2 2006.201.09:30:50.40#ibcon#read 3, iclass 12, count 2 2006.201.09:30:50.40#ibcon#about to read 4, iclass 12, count 2 2006.201.09:30:50.40#ibcon#read 4, iclass 12, count 2 2006.201.09:30:50.40#ibcon#about to read 5, iclass 12, count 2 2006.201.09:30:50.40#ibcon#read 5, iclass 12, count 2 2006.201.09:30:50.40#ibcon#about to read 6, iclass 12, count 2 2006.201.09:30:50.40#ibcon#read 6, iclass 12, count 2 2006.201.09:30:50.40#ibcon#end of sib2, iclass 12, count 2 2006.201.09:30:50.40#ibcon#*mode == 0, iclass 12, count 2 2006.201.09:30:50.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.09:30:50.40#ibcon#[25=AT08-04\r\n] 2006.201.09:30:50.40#ibcon#*before write, iclass 12, count 2 2006.201.09:30:50.40#ibcon#enter sib2, iclass 12, count 2 2006.201.09:30:50.40#ibcon#flushed, iclass 12, count 2 2006.201.09:30:50.40#ibcon#about to write, iclass 12, count 2 2006.201.09:30:50.40#ibcon#wrote, iclass 12, count 2 2006.201.09:30:50.40#ibcon#about to read 3, iclass 12, count 2 2006.201.09:30:50.43#ibcon#read 3, iclass 12, count 2 2006.201.09:30:50.43#ibcon#about to read 4, iclass 12, count 2 2006.201.09:30:50.43#ibcon#read 4, iclass 12, count 2 2006.201.09:30:50.43#ibcon#about to read 5, iclass 12, count 2 2006.201.09:30:50.43#ibcon#read 5, iclass 12, count 2 2006.201.09:30:50.43#ibcon#about to read 6, iclass 12, count 2 2006.201.09:30:50.43#ibcon#read 6, iclass 12, count 2 2006.201.09:30:50.43#ibcon#end of sib2, iclass 12, count 2 2006.201.09:30:50.43#ibcon#*after write, iclass 12, count 2 2006.201.09:30:50.43#ibcon#*before return 0, iclass 12, count 2 2006.201.09:30:50.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:30:50.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:30:50.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.09:30:50.43#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:50.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:30:50.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:30:50.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:30:50.55#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:30:50.55#ibcon#first serial, iclass 12, count 0 2006.201.09:30:50.55#ibcon#enter sib2, iclass 12, count 0 2006.201.09:30:50.55#ibcon#flushed, iclass 12, count 0 2006.201.09:30:50.55#ibcon#about to write, iclass 12, count 0 2006.201.09:30:50.55#ibcon#wrote, iclass 12, count 0 2006.201.09:30:50.55#ibcon#about to read 3, iclass 12, count 0 2006.201.09:30:50.57#ibcon#read 3, iclass 12, count 0 2006.201.09:30:50.57#ibcon#about to read 4, iclass 12, count 0 2006.201.09:30:50.57#ibcon#read 4, iclass 12, count 0 2006.201.09:30:50.57#ibcon#about to read 5, iclass 12, count 0 2006.201.09:30:50.57#ibcon#read 5, iclass 12, count 0 2006.201.09:30:50.57#ibcon#about to read 6, iclass 12, count 0 2006.201.09:30:50.57#ibcon#read 6, iclass 12, count 0 2006.201.09:30:50.57#ibcon#end of sib2, iclass 12, count 0 2006.201.09:30:50.57#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:30:50.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:30:50.57#ibcon#[25=USB\r\n] 2006.201.09:30:50.57#ibcon#*before write, iclass 12, count 0 2006.201.09:30:50.57#ibcon#enter sib2, iclass 12, count 0 2006.201.09:30:50.57#ibcon#flushed, iclass 12, count 0 2006.201.09:30:50.57#ibcon#about to write, iclass 12, count 0 2006.201.09:30:50.57#ibcon#wrote, iclass 12, count 0 2006.201.09:30:50.57#ibcon#about to read 3, iclass 12, count 0 2006.201.09:30:50.60#ibcon#read 3, iclass 12, count 0 2006.201.09:30:50.60#ibcon#about to read 4, iclass 12, count 0 2006.201.09:30:50.60#ibcon#read 4, iclass 12, count 0 2006.201.09:30:50.60#ibcon#about to read 5, iclass 12, count 0 2006.201.09:30:50.60#ibcon#read 5, iclass 12, count 0 2006.201.09:30:50.60#ibcon#about to read 6, iclass 12, count 0 2006.201.09:30:50.60#ibcon#read 6, iclass 12, count 0 2006.201.09:30:50.60#ibcon#end of sib2, iclass 12, count 0 2006.201.09:30:50.60#ibcon#*after write, iclass 12, count 0 2006.201.09:30:50.60#ibcon#*before return 0, iclass 12, count 0 2006.201.09:30:50.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:30:50.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:30:50.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:30:50.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:30:50.60$vck44/vblo=1,629.99 2006.201.09:30:50.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.09:30:50.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.09:30:50.60#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:50.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:30:50.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:30:50.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:30:50.60#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:30:50.60#ibcon#first serial, iclass 14, count 0 2006.201.09:30:50.60#ibcon#enter sib2, iclass 14, count 0 2006.201.09:30:50.60#ibcon#flushed, iclass 14, count 0 2006.201.09:30:50.60#ibcon#about to write, iclass 14, count 0 2006.201.09:30:50.60#ibcon#wrote, iclass 14, count 0 2006.201.09:30:50.60#ibcon#about to read 3, iclass 14, count 0 2006.201.09:30:50.62#ibcon#read 3, iclass 14, count 0 2006.201.09:30:50.62#ibcon#about to read 4, iclass 14, count 0 2006.201.09:30:50.62#ibcon#read 4, iclass 14, count 0 2006.201.09:30:50.62#ibcon#about to read 5, iclass 14, count 0 2006.201.09:30:50.62#ibcon#read 5, iclass 14, count 0 2006.201.09:30:50.62#ibcon#about to read 6, iclass 14, count 0 2006.201.09:30:50.62#ibcon#read 6, iclass 14, count 0 2006.201.09:30:50.62#ibcon#end of sib2, iclass 14, count 0 2006.201.09:30:50.62#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:30:50.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:30:50.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:30:50.62#ibcon#*before write, iclass 14, count 0 2006.201.09:30:50.62#ibcon#enter sib2, iclass 14, count 0 2006.201.09:30:50.62#ibcon#flushed, iclass 14, count 0 2006.201.09:30:50.62#ibcon#about to write, iclass 14, count 0 2006.201.09:30:50.62#ibcon#wrote, iclass 14, count 0 2006.201.09:30:50.62#ibcon#about to read 3, iclass 14, count 0 2006.201.09:30:50.67#ibcon#read 3, iclass 14, count 0 2006.201.09:30:50.67#ibcon#about to read 4, iclass 14, count 0 2006.201.09:30:50.67#ibcon#read 4, iclass 14, count 0 2006.201.09:30:50.67#ibcon#about to read 5, iclass 14, count 0 2006.201.09:30:50.67#ibcon#read 5, iclass 14, count 0 2006.201.09:30:50.67#ibcon#about to read 6, iclass 14, count 0 2006.201.09:30:50.67#ibcon#read 6, iclass 14, count 0 2006.201.09:30:50.67#ibcon#end of sib2, iclass 14, count 0 2006.201.09:30:50.67#ibcon#*after write, iclass 14, count 0 2006.201.09:30:50.67#ibcon#*before return 0, iclass 14, count 0 2006.201.09:30:50.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:30:50.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:30:50.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:30:50.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:30:50.67$vck44/vb=1,4 2006.201.09:30:50.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.09:30:50.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.09:30:50.67#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:50.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:30:50.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:30:50.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:30:50.67#ibcon#enter wrdev, iclass 16, count 2 2006.201.09:30:50.67#ibcon#first serial, iclass 16, count 2 2006.201.09:30:50.67#ibcon#enter sib2, iclass 16, count 2 2006.201.09:30:50.67#ibcon#flushed, iclass 16, count 2 2006.201.09:30:50.67#ibcon#about to write, iclass 16, count 2 2006.201.09:30:50.67#ibcon#wrote, iclass 16, count 2 2006.201.09:30:50.67#ibcon#about to read 3, iclass 16, count 2 2006.201.09:30:50.69#ibcon#read 3, iclass 16, count 2 2006.201.09:30:50.69#ibcon#about to read 4, iclass 16, count 2 2006.201.09:30:50.69#ibcon#read 4, iclass 16, count 2 2006.201.09:30:50.69#ibcon#about to read 5, iclass 16, count 2 2006.201.09:30:50.69#ibcon#read 5, iclass 16, count 2 2006.201.09:30:50.69#ibcon#about to read 6, iclass 16, count 2 2006.201.09:30:50.69#ibcon#read 6, iclass 16, count 2 2006.201.09:30:50.69#ibcon#end of sib2, iclass 16, count 2 2006.201.09:30:50.69#ibcon#*mode == 0, iclass 16, count 2 2006.201.09:30:50.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.09:30:50.69#ibcon#[27=AT01-04\r\n] 2006.201.09:30:50.69#ibcon#*before write, iclass 16, count 2 2006.201.09:30:50.69#ibcon#enter sib2, iclass 16, count 2 2006.201.09:30:50.69#ibcon#flushed, iclass 16, count 2 2006.201.09:30:50.69#ibcon#about to write, iclass 16, count 2 2006.201.09:30:50.69#ibcon#wrote, iclass 16, count 2 2006.201.09:30:50.69#ibcon#about to read 3, iclass 16, count 2 2006.201.09:30:50.72#ibcon#read 3, iclass 16, count 2 2006.201.09:30:50.72#ibcon#about to read 4, iclass 16, count 2 2006.201.09:30:50.72#ibcon#read 4, iclass 16, count 2 2006.201.09:30:50.72#ibcon#about to read 5, iclass 16, count 2 2006.201.09:30:50.72#ibcon#read 5, iclass 16, count 2 2006.201.09:30:50.72#ibcon#about to read 6, iclass 16, count 2 2006.201.09:30:50.72#ibcon#read 6, iclass 16, count 2 2006.201.09:30:50.72#ibcon#end of sib2, iclass 16, count 2 2006.201.09:30:50.72#ibcon#*after write, iclass 16, count 2 2006.201.09:30:50.72#ibcon#*before return 0, iclass 16, count 2 2006.201.09:30:50.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:30:50.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:30:50.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.09:30:50.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:50.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:30:50.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:30:50.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:30:50.84#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:30:50.84#ibcon#first serial, iclass 16, count 0 2006.201.09:30:50.84#ibcon#enter sib2, iclass 16, count 0 2006.201.09:30:50.84#ibcon#flushed, iclass 16, count 0 2006.201.09:30:50.84#ibcon#about to write, iclass 16, count 0 2006.201.09:30:50.84#ibcon#wrote, iclass 16, count 0 2006.201.09:30:50.84#ibcon#about to read 3, iclass 16, count 0 2006.201.09:30:50.86#ibcon#read 3, iclass 16, count 0 2006.201.09:30:50.86#ibcon#about to read 4, iclass 16, count 0 2006.201.09:30:50.86#ibcon#read 4, iclass 16, count 0 2006.201.09:30:50.86#ibcon#about to read 5, iclass 16, count 0 2006.201.09:30:50.86#ibcon#read 5, iclass 16, count 0 2006.201.09:30:50.86#ibcon#about to read 6, iclass 16, count 0 2006.201.09:30:50.86#ibcon#read 6, iclass 16, count 0 2006.201.09:30:50.86#ibcon#end of sib2, iclass 16, count 0 2006.201.09:30:50.86#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:30:50.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:30:50.86#ibcon#[27=USB\r\n] 2006.201.09:30:50.86#ibcon#*before write, iclass 16, count 0 2006.201.09:30:50.86#ibcon#enter sib2, iclass 16, count 0 2006.201.09:30:50.86#ibcon#flushed, iclass 16, count 0 2006.201.09:30:50.86#ibcon#about to write, iclass 16, count 0 2006.201.09:30:50.86#ibcon#wrote, iclass 16, count 0 2006.201.09:30:50.86#ibcon#about to read 3, iclass 16, count 0 2006.201.09:30:50.89#ibcon#read 3, iclass 16, count 0 2006.201.09:30:50.89#ibcon#about to read 4, iclass 16, count 0 2006.201.09:30:50.89#ibcon#read 4, iclass 16, count 0 2006.201.09:30:50.89#ibcon#about to read 5, iclass 16, count 0 2006.201.09:30:50.89#ibcon#read 5, iclass 16, count 0 2006.201.09:30:50.89#ibcon#about to read 6, iclass 16, count 0 2006.201.09:30:50.89#ibcon#read 6, iclass 16, count 0 2006.201.09:30:50.89#ibcon#end of sib2, iclass 16, count 0 2006.201.09:30:50.89#ibcon#*after write, iclass 16, count 0 2006.201.09:30:50.89#ibcon#*before return 0, iclass 16, count 0 2006.201.09:30:50.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:30:50.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:30:50.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:30:50.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:30:50.89$vck44/vblo=2,634.99 2006.201.09:30:50.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.09:30:50.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.09:30:50.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:50.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:50.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:50.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:50.89#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:30:50.89#ibcon#first serial, iclass 18, count 0 2006.201.09:30:50.89#ibcon#enter sib2, iclass 18, count 0 2006.201.09:30:50.89#ibcon#flushed, iclass 18, count 0 2006.201.09:30:50.89#ibcon#about to write, iclass 18, count 0 2006.201.09:30:50.89#ibcon#wrote, iclass 18, count 0 2006.201.09:30:50.89#ibcon#about to read 3, iclass 18, count 0 2006.201.09:30:50.91#ibcon#read 3, iclass 18, count 0 2006.201.09:30:50.91#ibcon#about to read 4, iclass 18, count 0 2006.201.09:30:50.91#ibcon#read 4, iclass 18, count 0 2006.201.09:30:50.91#ibcon#about to read 5, iclass 18, count 0 2006.201.09:30:50.91#ibcon#read 5, iclass 18, count 0 2006.201.09:30:50.91#ibcon#about to read 6, iclass 18, count 0 2006.201.09:30:50.91#ibcon#read 6, iclass 18, count 0 2006.201.09:30:50.91#ibcon#end of sib2, iclass 18, count 0 2006.201.09:30:50.91#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:30:50.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:30:50.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:30:50.91#ibcon#*before write, iclass 18, count 0 2006.201.09:30:50.91#ibcon#enter sib2, iclass 18, count 0 2006.201.09:30:50.91#ibcon#flushed, iclass 18, count 0 2006.201.09:30:50.91#ibcon#about to write, iclass 18, count 0 2006.201.09:30:50.91#ibcon#wrote, iclass 18, count 0 2006.201.09:30:50.91#ibcon#about to read 3, iclass 18, count 0 2006.201.09:30:50.95#ibcon#read 3, iclass 18, count 0 2006.201.09:30:50.95#ibcon#about to read 4, iclass 18, count 0 2006.201.09:30:50.95#ibcon#read 4, iclass 18, count 0 2006.201.09:30:50.95#ibcon#about to read 5, iclass 18, count 0 2006.201.09:30:50.95#ibcon#read 5, iclass 18, count 0 2006.201.09:30:50.95#ibcon#about to read 6, iclass 18, count 0 2006.201.09:30:50.95#ibcon#read 6, iclass 18, count 0 2006.201.09:30:50.95#ibcon#end of sib2, iclass 18, count 0 2006.201.09:30:50.95#ibcon#*after write, iclass 18, count 0 2006.201.09:30:50.95#ibcon#*before return 0, iclass 18, count 0 2006.201.09:30:50.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:50.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:30:50.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:30:50.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:30:50.95$vck44/vb=2,5 2006.201.09:30:50.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.09:30:50.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.09:30:50.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:50.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:51.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:51.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:51.01#ibcon#enter wrdev, iclass 20, count 2 2006.201.09:30:51.01#ibcon#first serial, iclass 20, count 2 2006.201.09:30:51.01#ibcon#enter sib2, iclass 20, count 2 2006.201.09:30:51.01#ibcon#flushed, iclass 20, count 2 2006.201.09:30:51.01#ibcon#about to write, iclass 20, count 2 2006.201.09:30:51.01#ibcon#wrote, iclass 20, count 2 2006.201.09:30:51.01#ibcon#about to read 3, iclass 20, count 2 2006.201.09:30:51.03#ibcon#read 3, iclass 20, count 2 2006.201.09:30:51.03#ibcon#about to read 4, iclass 20, count 2 2006.201.09:30:51.03#ibcon#read 4, iclass 20, count 2 2006.201.09:30:51.03#ibcon#about to read 5, iclass 20, count 2 2006.201.09:30:51.03#ibcon#read 5, iclass 20, count 2 2006.201.09:30:51.03#ibcon#about to read 6, iclass 20, count 2 2006.201.09:30:51.03#ibcon#read 6, iclass 20, count 2 2006.201.09:30:51.03#ibcon#end of sib2, iclass 20, count 2 2006.201.09:30:51.03#ibcon#*mode == 0, iclass 20, count 2 2006.201.09:30:51.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.09:30:51.03#ibcon#[27=AT02-05\r\n] 2006.201.09:30:51.03#ibcon#*before write, iclass 20, count 2 2006.201.09:30:51.03#ibcon#enter sib2, iclass 20, count 2 2006.201.09:30:51.03#ibcon#flushed, iclass 20, count 2 2006.201.09:30:51.03#ibcon#about to write, iclass 20, count 2 2006.201.09:30:51.03#ibcon#wrote, iclass 20, count 2 2006.201.09:30:51.03#ibcon#about to read 3, iclass 20, count 2 2006.201.09:30:51.06#ibcon#read 3, iclass 20, count 2 2006.201.09:30:51.06#ibcon#about to read 4, iclass 20, count 2 2006.201.09:30:51.06#ibcon#read 4, iclass 20, count 2 2006.201.09:30:51.06#ibcon#about to read 5, iclass 20, count 2 2006.201.09:30:51.06#ibcon#read 5, iclass 20, count 2 2006.201.09:30:51.06#ibcon#about to read 6, iclass 20, count 2 2006.201.09:30:51.06#ibcon#read 6, iclass 20, count 2 2006.201.09:30:51.06#ibcon#end of sib2, iclass 20, count 2 2006.201.09:30:51.06#ibcon#*after write, iclass 20, count 2 2006.201.09:30:51.06#ibcon#*before return 0, iclass 20, count 2 2006.201.09:30:51.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:51.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:30:51.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.09:30:51.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:51.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:51.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:51.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:51.18#ibcon#enter wrdev, iclass 20, count 0 2006.201.09:30:51.18#ibcon#first serial, iclass 20, count 0 2006.201.09:30:51.18#ibcon#enter sib2, iclass 20, count 0 2006.201.09:30:51.18#ibcon#flushed, iclass 20, count 0 2006.201.09:30:51.18#ibcon#about to write, iclass 20, count 0 2006.201.09:30:51.18#ibcon#wrote, iclass 20, count 0 2006.201.09:30:51.18#ibcon#about to read 3, iclass 20, count 0 2006.201.09:30:51.20#ibcon#read 3, iclass 20, count 0 2006.201.09:30:51.20#ibcon#about to read 4, iclass 20, count 0 2006.201.09:30:51.20#ibcon#read 4, iclass 20, count 0 2006.201.09:30:51.20#ibcon#about to read 5, iclass 20, count 0 2006.201.09:30:51.20#ibcon#read 5, iclass 20, count 0 2006.201.09:30:51.20#ibcon#about to read 6, iclass 20, count 0 2006.201.09:30:51.20#ibcon#read 6, iclass 20, count 0 2006.201.09:30:51.20#ibcon#end of sib2, iclass 20, count 0 2006.201.09:30:51.20#ibcon#*mode == 0, iclass 20, count 0 2006.201.09:30:51.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.09:30:51.20#ibcon#[27=USB\r\n] 2006.201.09:30:51.20#ibcon#*before write, iclass 20, count 0 2006.201.09:30:51.20#ibcon#enter sib2, iclass 20, count 0 2006.201.09:30:51.20#ibcon#flushed, iclass 20, count 0 2006.201.09:30:51.20#ibcon#about to write, iclass 20, count 0 2006.201.09:30:51.20#ibcon#wrote, iclass 20, count 0 2006.201.09:30:51.20#ibcon#about to read 3, iclass 20, count 0 2006.201.09:30:51.23#ibcon#read 3, iclass 20, count 0 2006.201.09:30:51.23#ibcon#about to read 4, iclass 20, count 0 2006.201.09:30:51.23#ibcon#read 4, iclass 20, count 0 2006.201.09:30:51.23#ibcon#about to read 5, iclass 20, count 0 2006.201.09:30:51.23#ibcon#read 5, iclass 20, count 0 2006.201.09:30:51.23#ibcon#about to read 6, iclass 20, count 0 2006.201.09:30:51.23#ibcon#read 6, iclass 20, count 0 2006.201.09:30:51.23#ibcon#end of sib2, iclass 20, count 0 2006.201.09:30:51.23#ibcon#*after write, iclass 20, count 0 2006.201.09:30:51.23#ibcon#*before return 0, iclass 20, count 0 2006.201.09:30:51.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:51.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:30:51.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.09:30:51.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.09:30:51.23$vck44/vblo=3,649.99 2006.201.09:30:51.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.09:30:51.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.09:30:51.23#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:51.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:51.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:51.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:51.23#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:30:51.23#ibcon#first serial, iclass 22, count 0 2006.201.09:30:51.23#ibcon#enter sib2, iclass 22, count 0 2006.201.09:30:51.23#ibcon#flushed, iclass 22, count 0 2006.201.09:30:51.23#ibcon#about to write, iclass 22, count 0 2006.201.09:30:51.23#ibcon#wrote, iclass 22, count 0 2006.201.09:30:51.23#ibcon#about to read 3, iclass 22, count 0 2006.201.09:30:51.25#ibcon#read 3, iclass 22, count 0 2006.201.09:30:51.25#ibcon#about to read 4, iclass 22, count 0 2006.201.09:30:51.25#ibcon#read 4, iclass 22, count 0 2006.201.09:30:51.25#ibcon#about to read 5, iclass 22, count 0 2006.201.09:30:51.25#ibcon#read 5, iclass 22, count 0 2006.201.09:30:51.25#ibcon#about to read 6, iclass 22, count 0 2006.201.09:30:51.25#ibcon#read 6, iclass 22, count 0 2006.201.09:30:51.25#ibcon#end of sib2, iclass 22, count 0 2006.201.09:30:51.25#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:30:51.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:30:51.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:30:51.25#ibcon#*before write, iclass 22, count 0 2006.201.09:30:51.25#ibcon#enter sib2, iclass 22, count 0 2006.201.09:30:51.25#ibcon#flushed, iclass 22, count 0 2006.201.09:30:51.25#ibcon#about to write, iclass 22, count 0 2006.201.09:30:51.25#ibcon#wrote, iclass 22, count 0 2006.201.09:30:51.25#ibcon#about to read 3, iclass 22, count 0 2006.201.09:30:51.29#ibcon#read 3, iclass 22, count 0 2006.201.09:30:51.29#ibcon#about to read 4, iclass 22, count 0 2006.201.09:30:51.29#ibcon#read 4, iclass 22, count 0 2006.201.09:30:51.29#ibcon#about to read 5, iclass 22, count 0 2006.201.09:30:51.29#ibcon#read 5, iclass 22, count 0 2006.201.09:30:51.29#ibcon#about to read 6, iclass 22, count 0 2006.201.09:30:51.29#ibcon#read 6, iclass 22, count 0 2006.201.09:30:51.29#ibcon#end of sib2, iclass 22, count 0 2006.201.09:30:51.29#ibcon#*after write, iclass 22, count 0 2006.201.09:30:51.29#ibcon#*before return 0, iclass 22, count 0 2006.201.09:30:51.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:51.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:30:51.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:30:51.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:30:51.29$vck44/vb=3,4 2006.201.09:30:51.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.09:30:51.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.09:30:51.29#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:51.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:51.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:51.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:51.35#ibcon#enter wrdev, iclass 24, count 2 2006.201.09:30:51.35#ibcon#first serial, iclass 24, count 2 2006.201.09:30:51.35#ibcon#enter sib2, iclass 24, count 2 2006.201.09:30:51.35#ibcon#flushed, iclass 24, count 2 2006.201.09:30:51.35#ibcon#about to write, iclass 24, count 2 2006.201.09:30:51.35#ibcon#wrote, iclass 24, count 2 2006.201.09:30:51.35#ibcon#about to read 3, iclass 24, count 2 2006.201.09:30:51.37#ibcon#read 3, iclass 24, count 2 2006.201.09:30:51.37#ibcon#about to read 4, iclass 24, count 2 2006.201.09:30:51.37#ibcon#read 4, iclass 24, count 2 2006.201.09:30:51.37#ibcon#about to read 5, iclass 24, count 2 2006.201.09:30:51.37#ibcon#read 5, iclass 24, count 2 2006.201.09:30:51.37#ibcon#about to read 6, iclass 24, count 2 2006.201.09:30:51.37#ibcon#read 6, iclass 24, count 2 2006.201.09:30:51.37#ibcon#end of sib2, iclass 24, count 2 2006.201.09:30:51.37#ibcon#*mode == 0, iclass 24, count 2 2006.201.09:30:51.37#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.09:30:51.37#ibcon#[27=AT03-04\r\n] 2006.201.09:30:51.37#ibcon#*before write, iclass 24, count 2 2006.201.09:30:51.37#ibcon#enter sib2, iclass 24, count 2 2006.201.09:30:51.37#ibcon#flushed, iclass 24, count 2 2006.201.09:30:51.37#ibcon#about to write, iclass 24, count 2 2006.201.09:30:51.37#ibcon#wrote, iclass 24, count 2 2006.201.09:30:51.37#ibcon#about to read 3, iclass 24, count 2 2006.201.09:30:51.41#ibcon#read 3, iclass 24, count 2 2006.201.09:30:51.41#ibcon#about to read 4, iclass 24, count 2 2006.201.09:30:51.41#ibcon#read 4, iclass 24, count 2 2006.201.09:30:51.41#ibcon#about to read 5, iclass 24, count 2 2006.201.09:30:51.41#ibcon#read 5, iclass 24, count 2 2006.201.09:30:51.41#ibcon#about to read 6, iclass 24, count 2 2006.201.09:30:51.41#ibcon#read 6, iclass 24, count 2 2006.201.09:30:51.41#ibcon#end of sib2, iclass 24, count 2 2006.201.09:30:51.41#ibcon#*after write, iclass 24, count 2 2006.201.09:30:51.41#ibcon#*before return 0, iclass 24, count 2 2006.201.09:30:51.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:51.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:30:51.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.09:30:51.41#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:51.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:51.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:51.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:51.53#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:30:51.53#ibcon#first serial, iclass 24, count 0 2006.201.09:30:51.53#ibcon#enter sib2, iclass 24, count 0 2006.201.09:30:51.53#ibcon#flushed, iclass 24, count 0 2006.201.09:30:51.53#ibcon#about to write, iclass 24, count 0 2006.201.09:30:51.53#ibcon#wrote, iclass 24, count 0 2006.201.09:30:51.53#ibcon#about to read 3, iclass 24, count 0 2006.201.09:30:51.55#ibcon#read 3, iclass 24, count 0 2006.201.09:30:51.55#ibcon#about to read 4, iclass 24, count 0 2006.201.09:30:51.55#ibcon#read 4, iclass 24, count 0 2006.201.09:30:51.55#ibcon#about to read 5, iclass 24, count 0 2006.201.09:30:51.55#ibcon#read 5, iclass 24, count 0 2006.201.09:30:51.55#ibcon#about to read 6, iclass 24, count 0 2006.201.09:30:51.55#ibcon#read 6, iclass 24, count 0 2006.201.09:30:51.55#ibcon#end of sib2, iclass 24, count 0 2006.201.09:30:51.55#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:30:51.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:30:51.55#ibcon#[27=USB\r\n] 2006.201.09:30:51.55#ibcon#*before write, iclass 24, count 0 2006.201.09:30:51.55#ibcon#enter sib2, iclass 24, count 0 2006.201.09:30:51.55#ibcon#flushed, iclass 24, count 0 2006.201.09:30:51.55#ibcon#about to write, iclass 24, count 0 2006.201.09:30:51.55#ibcon#wrote, iclass 24, count 0 2006.201.09:30:51.55#ibcon#about to read 3, iclass 24, count 0 2006.201.09:30:51.58#ibcon#read 3, iclass 24, count 0 2006.201.09:30:51.58#ibcon#about to read 4, iclass 24, count 0 2006.201.09:30:51.58#ibcon#read 4, iclass 24, count 0 2006.201.09:30:51.58#ibcon#about to read 5, iclass 24, count 0 2006.201.09:30:51.58#ibcon#read 5, iclass 24, count 0 2006.201.09:30:51.58#ibcon#about to read 6, iclass 24, count 0 2006.201.09:30:51.58#ibcon#read 6, iclass 24, count 0 2006.201.09:30:51.58#ibcon#end of sib2, iclass 24, count 0 2006.201.09:30:51.58#ibcon#*after write, iclass 24, count 0 2006.201.09:30:51.58#ibcon#*before return 0, iclass 24, count 0 2006.201.09:30:51.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:51.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:30:51.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:30:51.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:30:51.58$vck44/vblo=4,679.99 2006.201.09:30:51.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.09:30:51.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.09:30:51.58#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:51.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:51.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:51.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:51.58#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:30:51.58#ibcon#first serial, iclass 26, count 0 2006.201.09:30:51.58#ibcon#enter sib2, iclass 26, count 0 2006.201.09:30:51.58#ibcon#flushed, iclass 26, count 0 2006.201.09:30:51.58#ibcon#about to write, iclass 26, count 0 2006.201.09:30:51.58#ibcon#wrote, iclass 26, count 0 2006.201.09:30:51.58#ibcon#about to read 3, iclass 26, count 0 2006.201.09:30:51.60#ibcon#read 3, iclass 26, count 0 2006.201.09:30:51.60#ibcon#about to read 4, iclass 26, count 0 2006.201.09:30:51.60#ibcon#read 4, iclass 26, count 0 2006.201.09:30:51.60#ibcon#about to read 5, iclass 26, count 0 2006.201.09:30:51.60#ibcon#read 5, iclass 26, count 0 2006.201.09:30:51.60#ibcon#about to read 6, iclass 26, count 0 2006.201.09:30:51.60#ibcon#read 6, iclass 26, count 0 2006.201.09:30:51.60#ibcon#end of sib2, iclass 26, count 0 2006.201.09:30:51.60#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:30:51.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:30:51.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:30:51.60#ibcon#*before write, iclass 26, count 0 2006.201.09:30:51.60#ibcon#enter sib2, iclass 26, count 0 2006.201.09:30:51.60#ibcon#flushed, iclass 26, count 0 2006.201.09:30:51.60#ibcon#about to write, iclass 26, count 0 2006.201.09:30:51.60#ibcon#wrote, iclass 26, count 0 2006.201.09:30:51.60#ibcon#about to read 3, iclass 26, count 0 2006.201.09:30:51.65#ibcon#read 3, iclass 26, count 0 2006.201.09:30:51.65#ibcon#about to read 4, iclass 26, count 0 2006.201.09:30:51.65#ibcon#read 4, iclass 26, count 0 2006.201.09:30:51.65#ibcon#about to read 5, iclass 26, count 0 2006.201.09:30:51.65#ibcon#read 5, iclass 26, count 0 2006.201.09:30:51.65#ibcon#about to read 6, iclass 26, count 0 2006.201.09:30:51.65#ibcon#read 6, iclass 26, count 0 2006.201.09:30:51.65#ibcon#end of sib2, iclass 26, count 0 2006.201.09:30:51.65#ibcon#*after write, iclass 26, count 0 2006.201.09:30:51.65#ibcon#*before return 0, iclass 26, count 0 2006.201.09:30:51.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:51.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:30:51.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:30:51.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:30:51.65$vck44/vb=4,5 2006.201.09:30:51.65#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.09:30:51.65#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.09:30:51.65#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:51.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:51.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:51.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:51.70#ibcon#enter wrdev, iclass 28, count 2 2006.201.09:30:51.70#ibcon#first serial, iclass 28, count 2 2006.201.09:30:51.70#ibcon#enter sib2, iclass 28, count 2 2006.201.09:30:51.70#ibcon#flushed, iclass 28, count 2 2006.201.09:30:51.70#ibcon#about to write, iclass 28, count 2 2006.201.09:30:51.70#ibcon#wrote, iclass 28, count 2 2006.201.09:30:51.70#ibcon#about to read 3, iclass 28, count 2 2006.201.09:30:51.72#ibcon#read 3, iclass 28, count 2 2006.201.09:30:51.72#ibcon#about to read 4, iclass 28, count 2 2006.201.09:30:51.72#ibcon#read 4, iclass 28, count 2 2006.201.09:30:51.72#ibcon#about to read 5, iclass 28, count 2 2006.201.09:30:51.72#ibcon#read 5, iclass 28, count 2 2006.201.09:30:51.72#ibcon#about to read 6, iclass 28, count 2 2006.201.09:30:51.72#ibcon#read 6, iclass 28, count 2 2006.201.09:30:51.72#ibcon#end of sib2, iclass 28, count 2 2006.201.09:30:51.72#ibcon#*mode == 0, iclass 28, count 2 2006.201.09:30:51.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.09:30:51.72#ibcon#[27=AT04-05\r\n] 2006.201.09:30:51.72#ibcon#*before write, iclass 28, count 2 2006.201.09:30:51.72#ibcon#enter sib2, iclass 28, count 2 2006.201.09:30:51.72#ibcon#flushed, iclass 28, count 2 2006.201.09:30:51.72#ibcon#about to write, iclass 28, count 2 2006.201.09:30:51.72#ibcon#wrote, iclass 28, count 2 2006.201.09:30:51.72#ibcon#about to read 3, iclass 28, count 2 2006.201.09:30:51.75#ibcon#read 3, iclass 28, count 2 2006.201.09:30:51.75#ibcon#about to read 4, iclass 28, count 2 2006.201.09:30:51.75#ibcon#read 4, iclass 28, count 2 2006.201.09:30:51.75#ibcon#about to read 5, iclass 28, count 2 2006.201.09:30:51.75#ibcon#read 5, iclass 28, count 2 2006.201.09:30:51.75#ibcon#about to read 6, iclass 28, count 2 2006.201.09:30:51.75#ibcon#read 6, iclass 28, count 2 2006.201.09:30:51.75#ibcon#end of sib2, iclass 28, count 2 2006.201.09:30:51.75#ibcon#*after write, iclass 28, count 2 2006.201.09:30:51.75#ibcon#*before return 0, iclass 28, count 2 2006.201.09:30:51.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:51.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:30:51.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.09:30:51.75#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:51.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:51.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:51.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:51.87#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:30:51.87#ibcon#first serial, iclass 28, count 0 2006.201.09:30:51.87#ibcon#enter sib2, iclass 28, count 0 2006.201.09:30:51.87#ibcon#flushed, iclass 28, count 0 2006.201.09:30:51.87#ibcon#about to write, iclass 28, count 0 2006.201.09:30:51.87#ibcon#wrote, iclass 28, count 0 2006.201.09:30:51.87#ibcon#about to read 3, iclass 28, count 0 2006.201.09:30:51.89#ibcon#read 3, iclass 28, count 0 2006.201.09:30:51.89#ibcon#about to read 4, iclass 28, count 0 2006.201.09:30:51.89#ibcon#read 4, iclass 28, count 0 2006.201.09:30:51.89#ibcon#about to read 5, iclass 28, count 0 2006.201.09:30:51.89#ibcon#read 5, iclass 28, count 0 2006.201.09:30:51.89#ibcon#about to read 6, iclass 28, count 0 2006.201.09:30:51.89#ibcon#read 6, iclass 28, count 0 2006.201.09:30:51.89#ibcon#end of sib2, iclass 28, count 0 2006.201.09:30:51.89#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:30:51.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:30:51.89#ibcon#[27=USB\r\n] 2006.201.09:30:51.89#ibcon#*before write, iclass 28, count 0 2006.201.09:30:51.89#ibcon#enter sib2, iclass 28, count 0 2006.201.09:30:51.89#ibcon#flushed, iclass 28, count 0 2006.201.09:30:51.89#ibcon#about to write, iclass 28, count 0 2006.201.09:30:51.89#ibcon#wrote, iclass 28, count 0 2006.201.09:30:51.89#ibcon#about to read 3, iclass 28, count 0 2006.201.09:30:51.92#ibcon#read 3, iclass 28, count 0 2006.201.09:30:51.92#ibcon#about to read 4, iclass 28, count 0 2006.201.09:30:51.92#ibcon#read 4, iclass 28, count 0 2006.201.09:30:51.92#ibcon#about to read 5, iclass 28, count 0 2006.201.09:30:51.92#ibcon#read 5, iclass 28, count 0 2006.201.09:30:51.92#ibcon#about to read 6, iclass 28, count 0 2006.201.09:30:51.92#ibcon#read 6, iclass 28, count 0 2006.201.09:30:51.92#ibcon#end of sib2, iclass 28, count 0 2006.201.09:30:51.92#ibcon#*after write, iclass 28, count 0 2006.201.09:30:51.92#ibcon#*before return 0, iclass 28, count 0 2006.201.09:30:51.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:51.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:30:51.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:30:51.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:30:51.92$vck44/vblo=5,709.99 2006.201.09:30:51.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.09:30:51.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.09:30:51.92#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:51.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:51.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:51.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:51.92#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:30:51.92#ibcon#first serial, iclass 30, count 0 2006.201.09:30:51.92#ibcon#enter sib2, iclass 30, count 0 2006.201.09:30:51.92#ibcon#flushed, iclass 30, count 0 2006.201.09:30:51.92#ibcon#about to write, iclass 30, count 0 2006.201.09:30:51.92#ibcon#wrote, iclass 30, count 0 2006.201.09:30:51.92#ibcon#about to read 3, iclass 30, count 0 2006.201.09:30:51.94#ibcon#read 3, iclass 30, count 0 2006.201.09:30:51.94#ibcon#about to read 4, iclass 30, count 0 2006.201.09:30:51.94#ibcon#read 4, iclass 30, count 0 2006.201.09:30:51.94#ibcon#about to read 5, iclass 30, count 0 2006.201.09:30:51.94#ibcon#read 5, iclass 30, count 0 2006.201.09:30:51.94#ibcon#about to read 6, iclass 30, count 0 2006.201.09:30:51.94#ibcon#read 6, iclass 30, count 0 2006.201.09:30:51.94#ibcon#end of sib2, iclass 30, count 0 2006.201.09:30:51.94#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:30:51.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:30:51.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:30:51.94#ibcon#*before write, iclass 30, count 0 2006.201.09:30:51.94#ibcon#enter sib2, iclass 30, count 0 2006.201.09:30:51.94#ibcon#flushed, iclass 30, count 0 2006.201.09:30:51.94#ibcon#about to write, iclass 30, count 0 2006.201.09:30:51.94#ibcon#wrote, iclass 30, count 0 2006.201.09:30:51.94#ibcon#about to read 3, iclass 30, count 0 2006.201.09:30:51.98#ibcon#read 3, iclass 30, count 0 2006.201.09:30:51.98#ibcon#about to read 4, iclass 30, count 0 2006.201.09:30:51.98#ibcon#read 4, iclass 30, count 0 2006.201.09:30:51.98#ibcon#about to read 5, iclass 30, count 0 2006.201.09:30:51.98#ibcon#read 5, iclass 30, count 0 2006.201.09:30:51.98#ibcon#about to read 6, iclass 30, count 0 2006.201.09:30:51.98#ibcon#read 6, iclass 30, count 0 2006.201.09:30:51.98#ibcon#end of sib2, iclass 30, count 0 2006.201.09:30:51.98#ibcon#*after write, iclass 30, count 0 2006.201.09:30:51.98#ibcon#*before return 0, iclass 30, count 0 2006.201.09:30:51.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:51.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:30:51.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:30:51.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:30:51.98$vck44/vb=5,4 2006.201.09:30:51.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.09:30:51.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.09:30:51.98#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:51.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:52.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:52.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:52.04#ibcon#enter wrdev, iclass 32, count 2 2006.201.09:30:52.04#ibcon#first serial, iclass 32, count 2 2006.201.09:30:52.04#ibcon#enter sib2, iclass 32, count 2 2006.201.09:30:52.04#ibcon#flushed, iclass 32, count 2 2006.201.09:30:52.04#ibcon#about to write, iclass 32, count 2 2006.201.09:30:52.04#ibcon#wrote, iclass 32, count 2 2006.201.09:30:52.04#ibcon#about to read 3, iclass 32, count 2 2006.201.09:30:52.06#ibcon#read 3, iclass 32, count 2 2006.201.09:30:52.06#ibcon#about to read 4, iclass 32, count 2 2006.201.09:30:52.06#ibcon#read 4, iclass 32, count 2 2006.201.09:30:52.06#ibcon#about to read 5, iclass 32, count 2 2006.201.09:30:52.06#ibcon#read 5, iclass 32, count 2 2006.201.09:30:52.06#ibcon#about to read 6, iclass 32, count 2 2006.201.09:30:52.06#ibcon#read 6, iclass 32, count 2 2006.201.09:30:52.06#ibcon#end of sib2, iclass 32, count 2 2006.201.09:30:52.06#ibcon#*mode == 0, iclass 32, count 2 2006.201.09:30:52.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.09:30:52.06#ibcon#[27=AT05-04\r\n] 2006.201.09:30:52.06#ibcon#*before write, iclass 32, count 2 2006.201.09:30:52.06#ibcon#enter sib2, iclass 32, count 2 2006.201.09:30:52.06#ibcon#flushed, iclass 32, count 2 2006.201.09:30:52.06#ibcon#about to write, iclass 32, count 2 2006.201.09:30:52.06#ibcon#wrote, iclass 32, count 2 2006.201.09:30:52.06#ibcon#about to read 3, iclass 32, count 2 2006.201.09:30:52.09#ibcon#read 3, iclass 32, count 2 2006.201.09:30:52.09#ibcon#about to read 4, iclass 32, count 2 2006.201.09:30:52.09#ibcon#read 4, iclass 32, count 2 2006.201.09:30:52.09#ibcon#about to read 5, iclass 32, count 2 2006.201.09:30:52.09#ibcon#read 5, iclass 32, count 2 2006.201.09:30:52.09#ibcon#about to read 6, iclass 32, count 2 2006.201.09:30:52.09#ibcon#read 6, iclass 32, count 2 2006.201.09:30:52.09#ibcon#end of sib2, iclass 32, count 2 2006.201.09:30:52.09#ibcon#*after write, iclass 32, count 2 2006.201.09:30:52.09#ibcon#*before return 0, iclass 32, count 2 2006.201.09:30:52.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:52.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:30:52.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.09:30:52.09#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:52.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:52.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:52.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:52.21#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:30:52.21#ibcon#first serial, iclass 32, count 0 2006.201.09:30:52.21#ibcon#enter sib2, iclass 32, count 0 2006.201.09:30:52.21#ibcon#flushed, iclass 32, count 0 2006.201.09:30:52.21#ibcon#about to write, iclass 32, count 0 2006.201.09:30:52.21#ibcon#wrote, iclass 32, count 0 2006.201.09:30:52.21#ibcon#about to read 3, iclass 32, count 0 2006.201.09:30:52.23#ibcon#read 3, iclass 32, count 0 2006.201.09:30:52.23#ibcon#about to read 4, iclass 32, count 0 2006.201.09:30:52.23#ibcon#read 4, iclass 32, count 0 2006.201.09:30:52.23#ibcon#about to read 5, iclass 32, count 0 2006.201.09:30:52.23#ibcon#read 5, iclass 32, count 0 2006.201.09:30:52.23#ibcon#about to read 6, iclass 32, count 0 2006.201.09:30:52.23#ibcon#read 6, iclass 32, count 0 2006.201.09:30:52.23#ibcon#end of sib2, iclass 32, count 0 2006.201.09:30:52.23#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:30:52.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:30:52.23#ibcon#[27=USB\r\n] 2006.201.09:30:52.23#ibcon#*before write, iclass 32, count 0 2006.201.09:30:52.23#ibcon#enter sib2, iclass 32, count 0 2006.201.09:30:52.23#ibcon#flushed, iclass 32, count 0 2006.201.09:30:52.23#ibcon#about to write, iclass 32, count 0 2006.201.09:30:52.23#ibcon#wrote, iclass 32, count 0 2006.201.09:30:52.23#ibcon#about to read 3, iclass 32, count 0 2006.201.09:30:52.26#ibcon#read 3, iclass 32, count 0 2006.201.09:30:52.26#ibcon#about to read 4, iclass 32, count 0 2006.201.09:30:52.26#ibcon#read 4, iclass 32, count 0 2006.201.09:30:52.26#ibcon#about to read 5, iclass 32, count 0 2006.201.09:30:52.26#ibcon#read 5, iclass 32, count 0 2006.201.09:30:52.26#ibcon#about to read 6, iclass 32, count 0 2006.201.09:30:52.26#ibcon#read 6, iclass 32, count 0 2006.201.09:30:52.26#ibcon#end of sib2, iclass 32, count 0 2006.201.09:30:52.26#ibcon#*after write, iclass 32, count 0 2006.201.09:30:52.26#ibcon#*before return 0, iclass 32, count 0 2006.201.09:30:52.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:52.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:30:52.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:30:52.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:30:52.26$vck44/vblo=6,719.99 2006.201.09:30:52.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.09:30:52.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.09:30:52.26#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:52.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:52.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:52.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:52.26#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:30:52.26#ibcon#first serial, iclass 34, count 0 2006.201.09:30:52.26#ibcon#enter sib2, iclass 34, count 0 2006.201.09:30:52.26#ibcon#flushed, iclass 34, count 0 2006.201.09:30:52.26#ibcon#about to write, iclass 34, count 0 2006.201.09:30:52.26#ibcon#wrote, iclass 34, count 0 2006.201.09:30:52.26#ibcon#about to read 3, iclass 34, count 0 2006.201.09:30:52.28#ibcon#read 3, iclass 34, count 0 2006.201.09:30:52.28#ibcon#about to read 4, iclass 34, count 0 2006.201.09:30:52.28#ibcon#read 4, iclass 34, count 0 2006.201.09:30:52.28#ibcon#about to read 5, iclass 34, count 0 2006.201.09:30:52.28#ibcon#read 5, iclass 34, count 0 2006.201.09:30:52.28#ibcon#about to read 6, iclass 34, count 0 2006.201.09:30:52.28#ibcon#read 6, iclass 34, count 0 2006.201.09:30:52.28#ibcon#end of sib2, iclass 34, count 0 2006.201.09:30:52.28#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:30:52.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:30:52.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:30:52.28#ibcon#*before write, iclass 34, count 0 2006.201.09:30:52.28#ibcon#enter sib2, iclass 34, count 0 2006.201.09:30:52.28#ibcon#flushed, iclass 34, count 0 2006.201.09:30:52.28#ibcon#about to write, iclass 34, count 0 2006.201.09:30:52.28#ibcon#wrote, iclass 34, count 0 2006.201.09:30:52.28#ibcon#about to read 3, iclass 34, count 0 2006.201.09:30:52.33#ibcon#read 3, iclass 34, count 0 2006.201.09:30:52.33#ibcon#about to read 4, iclass 34, count 0 2006.201.09:30:52.33#ibcon#read 4, iclass 34, count 0 2006.201.09:30:52.33#ibcon#about to read 5, iclass 34, count 0 2006.201.09:30:52.33#ibcon#read 5, iclass 34, count 0 2006.201.09:30:52.33#ibcon#about to read 6, iclass 34, count 0 2006.201.09:30:52.33#ibcon#read 6, iclass 34, count 0 2006.201.09:30:52.33#ibcon#end of sib2, iclass 34, count 0 2006.201.09:30:52.33#ibcon#*after write, iclass 34, count 0 2006.201.09:30:52.33#ibcon#*before return 0, iclass 34, count 0 2006.201.09:30:52.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:52.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:30:52.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:30:52.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:30:52.33$vck44/vb=6,4 2006.201.09:30:52.33#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.09:30:52.33#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.09:30:52.33#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:52.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:52.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:52.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:52.38#ibcon#enter wrdev, iclass 36, count 2 2006.201.09:30:52.38#ibcon#first serial, iclass 36, count 2 2006.201.09:30:52.38#ibcon#enter sib2, iclass 36, count 2 2006.201.09:30:52.38#ibcon#flushed, iclass 36, count 2 2006.201.09:30:52.38#ibcon#about to write, iclass 36, count 2 2006.201.09:30:52.38#ibcon#wrote, iclass 36, count 2 2006.201.09:30:52.38#ibcon#about to read 3, iclass 36, count 2 2006.201.09:30:52.40#ibcon#read 3, iclass 36, count 2 2006.201.09:30:52.40#ibcon#about to read 4, iclass 36, count 2 2006.201.09:30:52.40#ibcon#read 4, iclass 36, count 2 2006.201.09:30:52.40#ibcon#about to read 5, iclass 36, count 2 2006.201.09:30:52.40#ibcon#read 5, iclass 36, count 2 2006.201.09:30:52.40#ibcon#about to read 6, iclass 36, count 2 2006.201.09:30:52.40#ibcon#read 6, iclass 36, count 2 2006.201.09:30:52.40#ibcon#end of sib2, iclass 36, count 2 2006.201.09:30:52.40#ibcon#*mode == 0, iclass 36, count 2 2006.201.09:30:52.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.09:30:52.40#ibcon#[27=AT06-04\r\n] 2006.201.09:30:52.40#ibcon#*before write, iclass 36, count 2 2006.201.09:30:52.40#ibcon#enter sib2, iclass 36, count 2 2006.201.09:30:52.40#ibcon#flushed, iclass 36, count 2 2006.201.09:30:52.40#ibcon#about to write, iclass 36, count 2 2006.201.09:30:52.40#ibcon#wrote, iclass 36, count 2 2006.201.09:30:52.40#ibcon#about to read 3, iclass 36, count 2 2006.201.09:30:52.43#ibcon#read 3, iclass 36, count 2 2006.201.09:30:52.43#ibcon#about to read 4, iclass 36, count 2 2006.201.09:30:52.43#ibcon#read 4, iclass 36, count 2 2006.201.09:30:52.43#ibcon#about to read 5, iclass 36, count 2 2006.201.09:30:52.43#ibcon#read 5, iclass 36, count 2 2006.201.09:30:52.43#ibcon#about to read 6, iclass 36, count 2 2006.201.09:30:52.43#ibcon#read 6, iclass 36, count 2 2006.201.09:30:52.43#ibcon#end of sib2, iclass 36, count 2 2006.201.09:30:52.43#ibcon#*after write, iclass 36, count 2 2006.201.09:30:52.43#ibcon#*before return 0, iclass 36, count 2 2006.201.09:30:52.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:52.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:30:52.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.09:30:52.43#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:52.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:52.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:52.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:52.55#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:30:52.55#ibcon#first serial, iclass 36, count 0 2006.201.09:30:52.55#ibcon#enter sib2, iclass 36, count 0 2006.201.09:30:52.55#ibcon#flushed, iclass 36, count 0 2006.201.09:30:52.55#ibcon#about to write, iclass 36, count 0 2006.201.09:30:52.55#ibcon#wrote, iclass 36, count 0 2006.201.09:30:52.55#ibcon#about to read 3, iclass 36, count 0 2006.201.09:30:52.57#ibcon#read 3, iclass 36, count 0 2006.201.09:30:52.57#ibcon#about to read 4, iclass 36, count 0 2006.201.09:30:52.57#ibcon#read 4, iclass 36, count 0 2006.201.09:30:52.57#ibcon#about to read 5, iclass 36, count 0 2006.201.09:30:52.57#ibcon#read 5, iclass 36, count 0 2006.201.09:30:52.57#ibcon#about to read 6, iclass 36, count 0 2006.201.09:30:52.57#ibcon#read 6, iclass 36, count 0 2006.201.09:30:52.57#ibcon#end of sib2, iclass 36, count 0 2006.201.09:30:52.57#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:30:52.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:30:52.57#ibcon#[27=USB\r\n] 2006.201.09:30:52.57#ibcon#*before write, iclass 36, count 0 2006.201.09:30:52.57#ibcon#enter sib2, iclass 36, count 0 2006.201.09:30:52.57#ibcon#flushed, iclass 36, count 0 2006.201.09:30:52.57#ibcon#about to write, iclass 36, count 0 2006.201.09:30:52.57#ibcon#wrote, iclass 36, count 0 2006.201.09:30:52.57#ibcon#about to read 3, iclass 36, count 0 2006.201.09:30:52.60#ibcon#read 3, iclass 36, count 0 2006.201.09:30:52.60#ibcon#about to read 4, iclass 36, count 0 2006.201.09:30:52.60#ibcon#read 4, iclass 36, count 0 2006.201.09:30:52.60#ibcon#about to read 5, iclass 36, count 0 2006.201.09:30:52.60#ibcon#read 5, iclass 36, count 0 2006.201.09:30:52.60#ibcon#about to read 6, iclass 36, count 0 2006.201.09:30:52.60#ibcon#read 6, iclass 36, count 0 2006.201.09:30:52.60#ibcon#end of sib2, iclass 36, count 0 2006.201.09:30:52.60#ibcon#*after write, iclass 36, count 0 2006.201.09:30:52.60#ibcon#*before return 0, iclass 36, count 0 2006.201.09:30:52.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:52.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:30:52.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:30:52.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:30:52.60$vck44/vblo=7,734.99 2006.201.09:30:52.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.09:30:52.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.09:30:52.60#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:52.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:52.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:52.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:52.60#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:30:52.60#ibcon#first serial, iclass 38, count 0 2006.201.09:30:52.60#ibcon#enter sib2, iclass 38, count 0 2006.201.09:30:52.60#ibcon#flushed, iclass 38, count 0 2006.201.09:30:52.60#ibcon#about to write, iclass 38, count 0 2006.201.09:30:52.60#ibcon#wrote, iclass 38, count 0 2006.201.09:30:52.60#ibcon#about to read 3, iclass 38, count 0 2006.201.09:30:52.62#ibcon#read 3, iclass 38, count 0 2006.201.09:30:52.62#ibcon#about to read 4, iclass 38, count 0 2006.201.09:30:52.62#ibcon#read 4, iclass 38, count 0 2006.201.09:30:52.62#ibcon#about to read 5, iclass 38, count 0 2006.201.09:30:52.62#ibcon#read 5, iclass 38, count 0 2006.201.09:30:52.62#ibcon#about to read 6, iclass 38, count 0 2006.201.09:30:52.62#ibcon#read 6, iclass 38, count 0 2006.201.09:30:52.62#ibcon#end of sib2, iclass 38, count 0 2006.201.09:30:52.62#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:30:52.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:30:52.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:30:52.62#ibcon#*before write, iclass 38, count 0 2006.201.09:30:52.62#ibcon#enter sib2, iclass 38, count 0 2006.201.09:30:52.62#ibcon#flushed, iclass 38, count 0 2006.201.09:30:52.62#ibcon#about to write, iclass 38, count 0 2006.201.09:30:52.62#ibcon#wrote, iclass 38, count 0 2006.201.09:30:52.62#ibcon#about to read 3, iclass 38, count 0 2006.201.09:30:52.66#ibcon#read 3, iclass 38, count 0 2006.201.09:30:52.66#ibcon#about to read 4, iclass 38, count 0 2006.201.09:30:52.66#ibcon#read 4, iclass 38, count 0 2006.201.09:30:52.66#ibcon#about to read 5, iclass 38, count 0 2006.201.09:30:52.66#ibcon#read 5, iclass 38, count 0 2006.201.09:30:52.66#ibcon#about to read 6, iclass 38, count 0 2006.201.09:30:52.66#ibcon#read 6, iclass 38, count 0 2006.201.09:30:52.66#ibcon#end of sib2, iclass 38, count 0 2006.201.09:30:52.66#ibcon#*after write, iclass 38, count 0 2006.201.09:30:52.66#ibcon#*before return 0, iclass 38, count 0 2006.201.09:30:52.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:52.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:30:52.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:30:52.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:30:52.66$vck44/vb=7,4 2006.201.09:30:52.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.09:30:52.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.09:30:52.66#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:52.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:52.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:52.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:52.72#ibcon#enter wrdev, iclass 40, count 2 2006.201.09:30:52.72#ibcon#first serial, iclass 40, count 2 2006.201.09:30:52.72#ibcon#enter sib2, iclass 40, count 2 2006.201.09:30:52.72#ibcon#flushed, iclass 40, count 2 2006.201.09:30:52.72#ibcon#about to write, iclass 40, count 2 2006.201.09:30:52.72#ibcon#wrote, iclass 40, count 2 2006.201.09:30:52.72#ibcon#about to read 3, iclass 40, count 2 2006.201.09:30:52.74#ibcon#read 3, iclass 40, count 2 2006.201.09:30:52.74#ibcon#about to read 4, iclass 40, count 2 2006.201.09:30:52.74#ibcon#read 4, iclass 40, count 2 2006.201.09:30:52.74#ibcon#about to read 5, iclass 40, count 2 2006.201.09:30:52.74#ibcon#read 5, iclass 40, count 2 2006.201.09:30:52.74#ibcon#about to read 6, iclass 40, count 2 2006.201.09:30:52.74#ibcon#read 6, iclass 40, count 2 2006.201.09:30:52.74#ibcon#end of sib2, iclass 40, count 2 2006.201.09:30:52.74#ibcon#*mode == 0, iclass 40, count 2 2006.201.09:30:52.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.09:30:52.74#ibcon#[27=AT07-04\r\n] 2006.201.09:30:52.74#ibcon#*before write, iclass 40, count 2 2006.201.09:30:52.74#ibcon#enter sib2, iclass 40, count 2 2006.201.09:30:52.74#ibcon#flushed, iclass 40, count 2 2006.201.09:30:52.74#ibcon#about to write, iclass 40, count 2 2006.201.09:30:52.74#ibcon#wrote, iclass 40, count 2 2006.201.09:30:52.74#ibcon#about to read 3, iclass 40, count 2 2006.201.09:30:52.77#ibcon#read 3, iclass 40, count 2 2006.201.09:30:52.77#ibcon#about to read 4, iclass 40, count 2 2006.201.09:30:52.77#ibcon#read 4, iclass 40, count 2 2006.201.09:30:52.77#ibcon#about to read 5, iclass 40, count 2 2006.201.09:30:52.77#ibcon#read 5, iclass 40, count 2 2006.201.09:30:52.77#ibcon#about to read 6, iclass 40, count 2 2006.201.09:30:52.77#ibcon#read 6, iclass 40, count 2 2006.201.09:30:52.77#ibcon#end of sib2, iclass 40, count 2 2006.201.09:30:52.77#ibcon#*after write, iclass 40, count 2 2006.201.09:30:52.77#ibcon#*before return 0, iclass 40, count 2 2006.201.09:30:52.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:52.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:30:52.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.09:30:52.77#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:52.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:52.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:52.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:52.89#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:30:52.89#ibcon#first serial, iclass 40, count 0 2006.201.09:30:52.89#ibcon#enter sib2, iclass 40, count 0 2006.201.09:30:52.89#ibcon#flushed, iclass 40, count 0 2006.201.09:30:52.89#ibcon#about to write, iclass 40, count 0 2006.201.09:30:52.89#ibcon#wrote, iclass 40, count 0 2006.201.09:30:52.89#ibcon#about to read 3, iclass 40, count 0 2006.201.09:30:52.91#ibcon#read 3, iclass 40, count 0 2006.201.09:30:52.91#ibcon#about to read 4, iclass 40, count 0 2006.201.09:30:52.91#ibcon#read 4, iclass 40, count 0 2006.201.09:30:52.91#ibcon#about to read 5, iclass 40, count 0 2006.201.09:30:52.91#ibcon#read 5, iclass 40, count 0 2006.201.09:30:52.91#ibcon#about to read 6, iclass 40, count 0 2006.201.09:30:52.91#ibcon#read 6, iclass 40, count 0 2006.201.09:30:52.91#ibcon#end of sib2, iclass 40, count 0 2006.201.09:30:52.91#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:30:52.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:30:52.91#ibcon#[27=USB\r\n] 2006.201.09:30:52.91#ibcon#*before write, iclass 40, count 0 2006.201.09:30:52.91#ibcon#enter sib2, iclass 40, count 0 2006.201.09:30:52.91#ibcon#flushed, iclass 40, count 0 2006.201.09:30:52.91#ibcon#about to write, iclass 40, count 0 2006.201.09:30:52.91#ibcon#wrote, iclass 40, count 0 2006.201.09:30:52.91#ibcon#about to read 3, iclass 40, count 0 2006.201.09:30:52.94#ibcon#read 3, iclass 40, count 0 2006.201.09:30:52.94#ibcon#about to read 4, iclass 40, count 0 2006.201.09:30:52.94#ibcon#read 4, iclass 40, count 0 2006.201.09:30:52.94#ibcon#about to read 5, iclass 40, count 0 2006.201.09:30:52.94#ibcon#read 5, iclass 40, count 0 2006.201.09:30:52.94#ibcon#about to read 6, iclass 40, count 0 2006.201.09:30:52.94#ibcon#read 6, iclass 40, count 0 2006.201.09:30:52.94#ibcon#end of sib2, iclass 40, count 0 2006.201.09:30:52.94#ibcon#*after write, iclass 40, count 0 2006.201.09:30:52.94#ibcon#*before return 0, iclass 40, count 0 2006.201.09:30:52.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:52.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:30:52.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:30:52.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:30:52.94$vck44/vblo=8,744.99 2006.201.09:30:52.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.09:30:52.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.09:30:52.94#ibcon#ireg 17 cls_cnt 0 2006.201.09:30:52.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:52.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:52.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:52.94#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:30:52.94#ibcon#first serial, iclass 4, count 0 2006.201.09:30:52.94#ibcon#enter sib2, iclass 4, count 0 2006.201.09:30:52.94#ibcon#flushed, iclass 4, count 0 2006.201.09:30:52.94#ibcon#about to write, iclass 4, count 0 2006.201.09:30:52.94#ibcon#wrote, iclass 4, count 0 2006.201.09:30:52.94#ibcon#about to read 3, iclass 4, count 0 2006.201.09:30:52.96#ibcon#read 3, iclass 4, count 0 2006.201.09:30:52.96#ibcon#about to read 4, iclass 4, count 0 2006.201.09:30:52.96#ibcon#read 4, iclass 4, count 0 2006.201.09:30:52.96#ibcon#about to read 5, iclass 4, count 0 2006.201.09:30:52.96#ibcon#read 5, iclass 4, count 0 2006.201.09:30:52.96#ibcon#about to read 6, iclass 4, count 0 2006.201.09:30:52.96#ibcon#read 6, iclass 4, count 0 2006.201.09:30:52.96#ibcon#end of sib2, iclass 4, count 0 2006.201.09:30:52.96#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:30:52.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:30:52.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:30:52.96#ibcon#*before write, iclass 4, count 0 2006.201.09:30:52.96#ibcon#enter sib2, iclass 4, count 0 2006.201.09:30:52.96#ibcon#flushed, iclass 4, count 0 2006.201.09:30:52.96#ibcon#about to write, iclass 4, count 0 2006.201.09:30:52.96#ibcon#wrote, iclass 4, count 0 2006.201.09:30:52.96#ibcon#about to read 3, iclass 4, count 0 2006.201.09:30:53.00#ibcon#read 3, iclass 4, count 0 2006.201.09:30:53.00#ibcon#about to read 4, iclass 4, count 0 2006.201.09:30:53.00#ibcon#read 4, iclass 4, count 0 2006.201.09:30:53.00#ibcon#about to read 5, iclass 4, count 0 2006.201.09:30:53.00#ibcon#read 5, iclass 4, count 0 2006.201.09:30:53.00#ibcon#about to read 6, iclass 4, count 0 2006.201.09:30:53.00#ibcon#read 6, iclass 4, count 0 2006.201.09:30:53.00#ibcon#end of sib2, iclass 4, count 0 2006.201.09:30:53.00#ibcon#*after write, iclass 4, count 0 2006.201.09:30:53.00#ibcon#*before return 0, iclass 4, count 0 2006.201.09:30:53.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:53.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:30:53.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:30:53.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:30:53.00$vck44/vb=8,4 2006.201.09:30:53.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.09:30:53.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.09:30:53.00#ibcon#ireg 11 cls_cnt 2 2006.201.09:30:53.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:53.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:53.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:53.06#ibcon#enter wrdev, iclass 6, count 2 2006.201.09:30:53.06#ibcon#first serial, iclass 6, count 2 2006.201.09:30:53.06#ibcon#enter sib2, iclass 6, count 2 2006.201.09:30:53.06#ibcon#flushed, iclass 6, count 2 2006.201.09:30:53.06#ibcon#about to write, iclass 6, count 2 2006.201.09:30:53.06#ibcon#wrote, iclass 6, count 2 2006.201.09:30:53.06#ibcon#about to read 3, iclass 6, count 2 2006.201.09:30:53.08#ibcon#read 3, iclass 6, count 2 2006.201.09:30:53.08#ibcon#about to read 4, iclass 6, count 2 2006.201.09:30:53.08#ibcon#read 4, iclass 6, count 2 2006.201.09:30:53.08#ibcon#about to read 5, iclass 6, count 2 2006.201.09:30:53.08#ibcon#read 5, iclass 6, count 2 2006.201.09:30:53.08#ibcon#about to read 6, iclass 6, count 2 2006.201.09:30:53.08#ibcon#read 6, iclass 6, count 2 2006.201.09:30:53.08#ibcon#end of sib2, iclass 6, count 2 2006.201.09:30:53.08#ibcon#*mode == 0, iclass 6, count 2 2006.201.09:30:53.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.09:30:53.08#ibcon#[27=AT08-04\r\n] 2006.201.09:30:53.08#ibcon#*before write, iclass 6, count 2 2006.201.09:30:53.08#ibcon#enter sib2, iclass 6, count 2 2006.201.09:30:53.08#ibcon#flushed, iclass 6, count 2 2006.201.09:30:53.08#ibcon#about to write, iclass 6, count 2 2006.201.09:30:53.08#ibcon#wrote, iclass 6, count 2 2006.201.09:30:53.08#ibcon#about to read 3, iclass 6, count 2 2006.201.09:30:53.11#ibcon#read 3, iclass 6, count 2 2006.201.09:30:53.11#ibcon#about to read 4, iclass 6, count 2 2006.201.09:30:53.11#ibcon#read 4, iclass 6, count 2 2006.201.09:30:53.11#ibcon#about to read 5, iclass 6, count 2 2006.201.09:30:53.11#ibcon#read 5, iclass 6, count 2 2006.201.09:30:53.11#ibcon#about to read 6, iclass 6, count 2 2006.201.09:30:53.11#ibcon#read 6, iclass 6, count 2 2006.201.09:30:53.11#ibcon#end of sib2, iclass 6, count 2 2006.201.09:30:53.11#ibcon#*after write, iclass 6, count 2 2006.201.09:30:53.11#ibcon#*before return 0, iclass 6, count 2 2006.201.09:30:53.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:53.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:30:53.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.09:30:53.11#ibcon#ireg 7 cls_cnt 0 2006.201.09:30:53.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:53.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:53.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:53.23#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:30:53.23#ibcon#first serial, iclass 6, count 0 2006.201.09:30:53.23#ibcon#enter sib2, iclass 6, count 0 2006.201.09:30:53.23#ibcon#flushed, iclass 6, count 0 2006.201.09:30:53.23#ibcon#about to write, iclass 6, count 0 2006.201.09:30:53.23#ibcon#wrote, iclass 6, count 0 2006.201.09:30:53.23#ibcon#about to read 3, iclass 6, count 0 2006.201.09:30:53.25#ibcon#read 3, iclass 6, count 0 2006.201.09:30:53.25#ibcon#about to read 4, iclass 6, count 0 2006.201.09:30:53.25#ibcon#read 4, iclass 6, count 0 2006.201.09:30:53.25#ibcon#about to read 5, iclass 6, count 0 2006.201.09:30:53.25#ibcon#read 5, iclass 6, count 0 2006.201.09:30:53.25#ibcon#about to read 6, iclass 6, count 0 2006.201.09:30:53.25#ibcon#read 6, iclass 6, count 0 2006.201.09:30:53.25#ibcon#end of sib2, iclass 6, count 0 2006.201.09:30:53.25#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:30:53.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:30:53.25#ibcon#[27=USB\r\n] 2006.201.09:30:53.25#ibcon#*before write, iclass 6, count 0 2006.201.09:30:53.25#ibcon#enter sib2, iclass 6, count 0 2006.201.09:30:53.25#ibcon#flushed, iclass 6, count 0 2006.201.09:30:53.25#ibcon#about to write, iclass 6, count 0 2006.201.09:30:53.25#ibcon#wrote, iclass 6, count 0 2006.201.09:30:53.25#ibcon#about to read 3, iclass 6, count 0 2006.201.09:30:53.28#ibcon#read 3, iclass 6, count 0 2006.201.09:30:53.28#ibcon#about to read 4, iclass 6, count 0 2006.201.09:30:53.28#ibcon#read 4, iclass 6, count 0 2006.201.09:30:53.28#ibcon#about to read 5, iclass 6, count 0 2006.201.09:30:53.28#ibcon#read 5, iclass 6, count 0 2006.201.09:30:53.28#ibcon#about to read 6, iclass 6, count 0 2006.201.09:30:53.28#ibcon#read 6, iclass 6, count 0 2006.201.09:30:53.28#ibcon#end of sib2, iclass 6, count 0 2006.201.09:30:53.28#ibcon#*after write, iclass 6, count 0 2006.201.09:30:53.28#ibcon#*before return 0, iclass 6, count 0 2006.201.09:30:53.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:53.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:30:53.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:30:53.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:30:53.28$vck44/vabw=wide 2006.201.09:30:53.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.09:30:53.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.09:30:53.28#ibcon#ireg 8 cls_cnt 0 2006.201.09:30:53.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:53.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:53.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:53.28#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:30:53.28#ibcon#first serial, iclass 10, count 0 2006.201.09:30:53.28#ibcon#enter sib2, iclass 10, count 0 2006.201.09:30:53.28#ibcon#flushed, iclass 10, count 0 2006.201.09:30:53.28#ibcon#about to write, iclass 10, count 0 2006.201.09:30:53.28#ibcon#wrote, iclass 10, count 0 2006.201.09:30:53.28#ibcon#about to read 3, iclass 10, count 0 2006.201.09:30:53.30#ibcon#read 3, iclass 10, count 0 2006.201.09:30:53.30#ibcon#about to read 4, iclass 10, count 0 2006.201.09:30:53.30#ibcon#read 4, iclass 10, count 0 2006.201.09:30:53.30#ibcon#about to read 5, iclass 10, count 0 2006.201.09:30:53.30#ibcon#read 5, iclass 10, count 0 2006.201.09:30:53.30#ibcon#about to read 6, iclass 10, count 0 2006.201.09:30:53.30#ibcon#read 6, iclass 10, count 0 2006.201.09:30:53.30#ibcon#end of sib2, iclass 10, count 0 2006.201.09:30:53.30#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:30:53.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:30:53.30#ibcon#[25=BW32\r\n] 2006.201.09:30:53.30#ibcon#*before write, iclass 10, count 0 2006.201.09:30:53.30#ibcon#enter sib2, iclass 10, count 0 2006.201.09:30:53.30#ibcon#flushed, iclass 10, count 0 2006.201.09:30:53.30#ibcon#about to write, iclass 10, count 0 2006.201.09:30:53.30#ibcon#wrote, iclass 10, count 0 2006.201.09:30:53.30#ibcon#about to read 3, iclass 10, count 0 2006.201.09:30:53.33#ibcon#read 3, iclass 10, count 0 2006.201.09:30:53.33#ibcon#about to read 4, iclass 10, count 0 2006.201.09:30:53.33#ibcon#read 4, iclass 10, count 0 2006.201.09:30:53.33#ibcon#about to read 5, iclass 10, count 0 2006.201.09:30:53.33#ibcon#read 5, iclass 10, count 0 2006.201.09:30:53.33#ibcon#about to read 6, iclass 10, count 0 2006.201.09:30:53.33#ibcon#read 6, iclass 10, count 0 2006.201.09:30:53.33#ibcon#end of sib2, iclass 10, count 0 2006.201.09:30:53.33#ibcon#*after write, iclass 10, count 0 2006.201.09:30:53.33#ibcon#*before return 0, iclass 10, count 0 2006.201.09:30:53.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:53.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:30:53.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:30:53.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:30:53.33$vck44/vbbw=wide 2006.201.09:30:53.33#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.09:30:53.33#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.09:30:53.33#ibcon#ireg 8 cls_cnt 0 2006.201.09:30:53.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:30:53.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:30:53.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:30:53.40#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:30:53.40#ibcon#first serial, iclass 12, count 0 2006.201.09:30:53.40#ibcon#enter sib2, iclass 12, count 0 2006.201.09:30:53.40#ibcon#flushed, iclass 12, count 0 2006.201.09:30:53.40#ibcon#about to write, iclass 12, count 0 2006.201.09:30:53.40#ibcon#wrote, iclass 12, count 0 2006.201.09:30:53.40#ibcon#about to read 3, iclass 12, count 0 2006.201.09:30:53.42#ibcon#read 3, iclass 12, count 0 2006.201.09:30:53.42#ibcon#about to read 4, iclass 12, count 0 2006.201.09:30:53.42#ibcon#read 4, iclass 12, count 0 2006.201.09:30:53.42#ibcon#about to read 5, iclass 12, count 0 2006.201.09:30:53.42#ibcon#read 5, iclass 12, count 0 2006.201.09:30:53.42#ibcon#about to read 6, iclass 12, count 0 2006.201.09:30:53.42#ibcon#read 6, iclass 12, count 0 2006.201.09:30:53.42#ibcon#end of sib2, iclass 12, count 0 2006.201.09:30:53.42#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:30:53.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:30:53.42#ibcon#[27=BW32\r\n] 2006.201.09:30:53.42#ibcon#*before write, iclass 12, count 0 2006.201.09:30:53.42#ibcon#enter sib2, iclass 12, count 0 2006.201.09:30:53.42#ibcon#flushed, iclass 12, count 0 2006.201.09:30:53.42#ibcon#about to write, iclass 12, count 0 2006.201.09:30:53.42#ibcon#wrote, iclass 12, count 0 2006.201.09:30:53.42#ibcon#about to read 3, iclass 12, count 0 2006.201.09:30:53.45#ibcon#read 3, iclass 12, count 0 2006.201.09:30:53.45#ibcon#about to read 4, iclass 12, count 0 2006.201.09:30:53.45#ibcon#read 4, iclass 12, count 0 2006.201.09:30:53.45#ibcon#about to read 5, iclass 12, count 0 2006.201.09:30:53.45#ibcon#read 5, iclass 12, count 0 2006.201.09:30:53.45#ibcon#about to read 6, iclass 12, count 0 2006.201.09:30:53.45#ibcon#read 6, iclass 12, count 0 2006.201.09:30:53.45#ibcon#end of sib2, iclass 12, count 0 2006.201.09:30:53.45#ibcon#*after write, iclass 12, count 0 2006.201.09:30:53.45#ibcon#*before return 0, iclass 12, count 0 2006.201.09:30:53.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:30:53.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:30:53.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:30:53.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:30:53.45$setupk4/ifdk4 2006.201.09:30:53.45$ifdk4/lo= 2006.201.09:30:53.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:30:53.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:30:53.45$ifdk4/patch= 2006.201.09:30:53.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:30:53.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:30:53.45$setupk4/!*+20s 2006.201.09:30:55.39#abcon#<5=/05 2.7 4.5 22.59 921003.8\r\n> 2006.201.09:30:55.41#abcon#{5=INTERFACE CLEAR} 2006.201.09:30:55.47#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:31:05.56#abcon#<5=/05 2.7 4.5 22.59 921003.8\r\n> 2006.201.09:31:05.58#abcon#{5=INTERFACE CLEAR} 2006.201.09:31:05.64#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:31:07.90$setupk4/"tpicd 2006.201.09:31:07.90$setupk4/echo=off 2006.201.09:31:07.90$setupk4/xlog=off 2006.201.09:31:07.90:!2006.201.09:35:15 2006.201.09:31:11.14#trakl#Source acquired 2006.201.09:31:13.14#flagr#flagr/antenna,acquired 2006.201.09:35:15.00:preob 2006.201.09:35:15.14/onsource/TRACKING 2006.201.09:35:15.14:!2006.201.09:35:25 2006.201.09:35:25.00:"tape 2006.201.09:35:25.00:"st=record 2006.201.09:35:25.00:data_valid=on 2006.201.09:35:25.00:midob 2006.201.09:35:25.14/onsource/TRACKING 2006.201.09:35:25.14/wx/22.55,1003.8,92 2006.201.09:35:25.19/cable/+6.4644E-03 2006.201.09:35:26.28/va/01,08,usb,yes,37,39 2006.201.09:35:26.28/va/02,07,usb,yes,40,40 2006.201.09:35:26.28/va/03,08,usb,yes,36,37 2006.201.09:35:26.28/va/04,07,usb,yes,41,43 2006.201.09:35:26.28/va/05,04,usb,yes,36,37 2006.201.09:35:26.28/va/06,05,usb,yes,36,36 2006.201.09:35:26.28/va/07,05,usb,yes,35,37 2006.201.09:35:26.28/va/08,04,usb,yes,35,42 2006.201.09:35:26.51/valo/01,524.99,yes,locked 2006.201.09:35:26.51/valo/02,534.99,yes,locked 2006.201.09:35:26.51/valo/03,564.99,yes,locked 2006.201.09:35:26.51/valo/04,624.99,yes,locked 2006.201.09:35:26.51/valo/05,734.99,yes,locked 2006.201.09:35:26.51/valo/06,814.99,yes,locked 2006.201.09:35:26.51/valo/07,864.99,yes,locked 2006.201.09:35:26.51/valo/08,884.99,yes,locked 2006.201.09:35:27.60/vb/01,04,usb,yes,33,30 2006.201.09:35:27.60/vb/02,05,usb,yes,31,31 2006.201.09:35:27.60/vb/03,04,usb,yes,32,35 2006.201.09:35:27.60/vb/04,05,usb,yes,32,31 2006.201.09:35:27.60/vb/05,04,usb,yes,29,31 2006.201.09:35:27.60/vb/06,04,usb,yes,33,29 2006.201.09:35:27.60/vb/07,04,usb,yes,33,33 2006.201.09:35:27.60/vb/08,04,usb,yes,31,34 2006.201.09:35:27.83/vblo/01,629.99,yes,locked 2006.201.09:35:27.83/vblo/02,634.99,yes,locked 2006.201.09:35:27.83/vblo/03,649.99,yes,locked 2006.201.09:35:27.83/vblo/04,679.99,yes,locked 2006.201.09:35:27.83/vblo/05,709.99,yes,locked 2006.201.09:35:27.83/vblo/06,719.99,yes,locked 2006.201.09:35:27.83/vblo/07,734.99,yes,locked 2006.201.09:35:27.83/vblo/08,744.99,yes,locked 2006.201.09:35:27.98/vabw/8 2006.201.09:35:28.13/vbbw/8 2006.201.09:35:28.28/xfe/off,on,15.2 2006.201.09:35:28.65/ifatt/23,28,28,28 2006.201.09:35:29.06/fmout-gps/S +4.55E-07 2006.201.09:35:29.10:!2006.201.09:36:05 2006.201.09:36:05.00:data_valid=off 2006.201.09:36:05.00:"et 2006.201.09:36:05.00:!+3s 2006.201.09:36:08.02:"tape 2006.201.09:36:08.02:postob 2006.201.09:36:08.13/cable/+6.4650E-03 2006.201.09:36:08.13/wx/22.54,1003.9,92 2006.201.09:36:08.21/fmout-gps/S +4.57E-07 2006.201.09:36:08.21:scan_name=201-0936,jd0607,740 2006.201.09:36:08.21:source=1749+096,175132.82,093900.7,2000.0,cw 2006.201.09:36:10.14#flagr#flagr/antenna,new-source 2006.201.09:36:10.14:checkk5 2006.201.09:36:10.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:36:10.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:36:11.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:36:11.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:36:11.99/chk_obsdata//k5ts1/T2010935??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:36:12.35/chk_obsdata//k5ts2/T2010935??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:36:12.72/chk_obsdata//k5ts3/T2010935??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:36:13.09/chk_obsdata//k5ts4/T2010935??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.09:36:13.79/k5log//k5ts1_log_newline 2006.201.09:36:14.47/k5log//k5ts2_log_newline 2006.201.09:36:15.16/k5log//k5ts3_log_newline 2006.201.09:36:15.85/k5log//k5ts4_log_newline 2006.201.09:36:15.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:36:15.88:setupk4=1 2006.201.09:36:15.88$setupk4/echo=on 2006.201.09:36:15.88$setupk4/pcalon 2006.201.09:36:15.88$pcalon/"no phase cal control is implemented here 2006.201.09:36:15.88$setupk4/"tpicd=stop 2006.201.09:36:15.88$setupk4/"rec=synch_on 2006.201.09:36:15.88$setupk4/"rec_mode=128 2006.201.09:36:15.88$setupk4/!* 2006.201.09:36:15.88$setupk4/recpk4 2006.201.09:36:15.88$recpk4/recpatch= 2006.201.09:36:15.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:36:15.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:36:15.88$setupk4/vck44 2006.201.09:36:15.88$vck44/valo=1,524.99 2006.201.09:36:15.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.09:36:15.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.09:36:15.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:15.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:15.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:15.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:15.88#ibcon#enter wrdev, iclass 37, count 0 2006.201.09:36:15.88#ibcon#first serial, iclass 37, count 0 2006.201.09:36:15.88#ibcon#enter sib2, iclass 37, count 0 2006.201.09:36:15.88#ibcon#flushed, iclass 37, count 0 2006.201.09:36:15.88#ibcon#about to write, iclass 37, count 0 2006.201.09:36:15.88#ibcon#wrote, iclass 37, count 0 2006.201.09:36:15.88#ibcon#about to read 3, iclass 37, count 0 2006.201.09:36:15.92#ibcon#read 3, iclass 37, count 0 2006.201.09:36:15.92#ibcon#about to read 4, iclass 37, count 0 2006.201.09:36:15.92#ibcon#read 4, iclass 37, count 0 2006.201.09:36:15.92#ibcon#about to read 5, iclass 37, count 0 2006.201.09:36:15.92#ibcon#read 5, iclass 37, count 0 2006.201.09:36:15.92#ibcon#about to read 6, iclass 37, count 0 2006.201.09:36:15.92#ibcon#read 6, iclass 37, count 0 2006.201.09:36:15.92#ibcon#end of sib2, iclass 37, count 0 2006.201.09:36:15.92#ibcon#*mode == 0, iclass 37, count 0 2006.201.09:36:15.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.09:36:15.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:36:15.92#ibcon#*before write, iclass 37, count 0 2006.201.09:36:15.92#ibcon#enter sib2, iclass 37, count 0 2006.201.09:36:15.92#ibcon#flushed, iclass 37, count 0 2006.201.09:36:15.92#ibcon#about to write, iclass 37, count 0 2006.201.09:36:15.92#ibcon#wrote, iclass 37, count 0 2006.201.09:36:15.92#ibcon#about to read 3, iclass 37, count 0 2006.201.09:36:15.97#ibcon#read 3, iclass 37, count 0 2006.201.09:36:15.97#ibcon#about to read 4, iclass 37, count 0 2006.201.09:36:15.97#ibcon#read 4, iclass 37, count 0 2006.201.09:36:15.97#ibcon#about to read 5, iclass 37, count 0 2006.201.09:36:15.97#ibcon#read 5, iclass 37, count 0 2006.201.09:36:15.97#ibcon#about to read 6, iclass 37, count 0 2006.201.09:36:15.97#ibcon#read 6, iclass 37, count 0 2006.201.09:36:15.97#ibcon#end of sib2, iclass 37, count 0 2006.201.09:36:15.97#ibcon#*after write, iclass 37, count 0 2006.201.09:36:15.97#ibcon#*before return 0, iclass 37, count 0 2006.201.09:36:15.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:15.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:15.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.09:36:15.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.09:36:15.97$vck44/va=1,8 2006.201.09:36:15.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.09:36:15.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.09:36:15.97#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:15.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:15.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:15.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:15.97#ibcon#enter wrdev, iclass 39, count 2 2006.201.09:36:15.97#ibcon#first serial, iclass 39, count 2 2006.201.09:36:15.97#ibcon#enter sib2, iclass 39, count 2 2006.201.09:36:15.97#ibcon#flushed, iclass 39, count 2 2006.201.09:36:15.97#ibcon#about to write, iclass 39, count 2 2006.201.09:36:15.97#ibcon#wrote, iclass 39, count 2 2006.201.09:36:15.97#ibcon#about to read 3, iclass 39, count 2 2006.201.09:36:15.99#ibcon#read 3, iclass 39, count 2 2006.201.09:36:15.99#ibcon#about to read 4, iclass 39, count 2 2006.201.09:36:15.99#ibcon#read 4, iclass 39, count 2 2006.201.09:36:15.99#ibcon#about to read 5, iclass 39, count 2 2006.201.09:36:15.99#ibcon#read 5, iclass 39, count 2 2006.201.09:36:15.99#ibcon#about to read 6, iclass 39, count 2 2006.201.09:36:15.99#ibcon#read 6, iclass 39, count 2 2006.201.09:36:15.99#ibcon#end of sib2, iclass 39, count 2 2006.201.09:36:15.99#ibcon#*mode == 0, iclass 39, count 2 2006.201.09:36:15.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.09:36:15.99#ibcon#[25=AT01-08\r\n] 2006.201.09:36:15.99#ibcon#*before write, iclass 39, count 2 2006.201.09:36:15.99#ibcon#enter sib2, iclass 39, count 2 2006.201.09:36:15.99#ibcon#flushed, iclass 39, count 2 2006.201.09:36:15.99#ibcon#about to write, iclass 39, count 2 2006.201.09:36:15.99#ibcon#wrote, iclass 39, count 2 2006.201.09:36:15.99#ibcon#about to read 3, iclass 39, count 2 2006.201.09:36:16.02#ibcon#read 3, iclass 39, count 2 2006.201.09:36:16.02#ibcon#about to read 4, iclass 39, count 2 2006.201.09:36:16.02#ibcon#read 4, iclass 39, count 2 2006.201.09:36:16.02#ibcon#about to read 5, iclass 39, count 2 2006.201.09:36:16.02#ibcon#read 5, iclass 39, count 2 2006.201.09:36:16.02#ibcon#about to read 6, iclass 39, count 2 2006.201.09:36:16.02#ibcon#read 6, iclass 39, count 2 2006.201.09:36:16.02#ibcon#end of sib2, iclass 39, count 2 2006.201.09:36:16.02#ibcon#*after write, iclass 39, count 2 2006.201.09:36:16.02#ibcon#*before return 0, iclass 39, count 2 2006.201.09:36:16.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:16.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:16.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.09:36:16.02#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:16.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:16.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:16.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:16.14#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:36:16.14#ibcon#first serial, iclass 39, count 0 2006.201.09:36:16.14#ibcon#enter sib2, iclass 39, count 0 2006.201.09:36:16.14#ibcon#flushed, iclass 39, count 0 2006.201.09:36:16.14#ibcon#about to write, iclass 39, count 0 2006.201.09:36:16.14#ibcon#wrote, iclass 39, count 0 2006.201.09:36:16.14#ibcon#about to read 3, iclass 39, count 0 2006.201.09:36:16.16#ibcon#read 3, iclass 39, count 0 2006.201.09:36:16.16#ibcon#about to read 4, iclass 39, count 0 2006.201.09:36:16.16#ibcon#read 4, iclass 39, count 0 2006.201.09:36:16.16#ibcon#about to read 5, iclass 39, count 0 2006.201.09:36:16.16#ibcon#read 5, iclass 39, count 0 2006.201.09:36:16.16#ibcon#about to read 6, iclass 39, count 0 2006.201.09:36:16.16#ibcon#read 6, iclass 39, count 0 2006.201.09:36:16.16#ibcon#end of sib2, iclass 39, count 0 2006.201.09:36:16.16#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:36:16.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:36:16.16#ibcon#[25=USB\r\n] 2006.201.09:36:16.16#ibcon#*before write, iclass 39, count 0 2006.201.09:36:16.16#ibcon#enter sib2, iclass 39, count 0 2006.201.09:36:16.16#ibcon#flushed, iclass 39, count 0 2006.201.09:36:16.16#ibcon#about to write, iclass 39, count 0 2006.201.09:36:16.16#ibcon#wrote, iclass 39, count 0 2006.201.09:36:16.16#ibcon#about to read 3, iclass 39, count 0 2006.201.09:36:16.19#ibcon#read 3, iclass 39, count 0 2006.201.09:36:16.19#ibcon#about to read 4, iclass 39, count 0 2006.201.09:36:16.19#ibcon#read 4, iclass 39, count 0 2006.201.09:36:16.19#ibcon#about to read 5, iclass 39, count 0 2006.201.09:36:16.19#ibcon#read 5, iclass 39, count 0 2006.201.09:36:16.19#ibcon#about to read 6, iclass 39, count 0 2006.201.09:36:16.19#ibcon#read 6, iclass 39, count 0 2006.201.09:36:16.19#ibcon#end of sib2, iclass 39, count 0 2006.201.09:36:16.19#ibcon#*after write, iclass 39, count 0 2006.201.09:36:16.19#ibcon#*before return 0, iclass 39, count 0 2006.201.09:36:16.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:16.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:16.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:36:16.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:36:16.19$vck44/valo=2,534.99 2006.201.09:36:16.19#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.09:36:16.19#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.09:36:16.19#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:16.19#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:16.19#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:16.19#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:16.19#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:36:16.19#ibcon#first serial, iclass 2, count 0 2006.201.09:36:16.19#ibcon#enter sib2, iclass 2, count 0 2006.201.09:36:16.19#ibcon#flushed, iclass 2, count 0 2006.201.09:36:16.19#ibcon#about to write, iclass 2, count 0 2006.201.09:36:16.19#ibcon#wrote, iclass 2, count 0 2006.201.09:36:16.19#ibcon#about to read 3, iclass 2, count 0 2006.201.09:36:16.21#ibcon#read 3, iclass 2, count 0 2006.201.09:36:16.21#ibcon#about to read 4, iclass 2, count 0 2006.201.09:36:16.21#ibcon#read 4, iclass 2, count 0 2006.201.09:36:16.21#ibcon#about to read 5, iclass 2, count 0 2006.201.09:36:16.21#ibcon#read 5, iclass 2, count 0 2006.201.09:36:16.21#ibcon#about to read 6, iclass 2, count 0 2006.201.09:36:16.21#ibcon#read 6, iclass 2, count 0 2006.201.09:36:16.21#ibcon#end of sib2, iclass 2, count 0 2006.201.09:36:16.21#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:36:16.21#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:36:16.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:36:16.21#ibcon#*before write, iclass 2, count 0 2006.201.09:36:16.21#ibcon#enter sib2, iclass 2, count 0 2006.201.09:36:16.21#ibcon#flushed, iclass 2, count 0 2006.201.09:36:16.21#ibcon#about to write, iclass 2, count 0 2006.201.09:36:16.21#ibcon#wrote, iclass 2, count 0 2006.201.09:36:16.21#ibcon#about to read 3, iclass 2, count 0 2006.201.09:36:16.26#ibcon#read 3, iclass 2, count 0 2006.201.09:36:16.26#ibcon#about to read 4, iclass 2, count 0 2006.201.09:36:16.26#ibcon#read 4, iclass 2, count 0 2006.201.09:36:16.26#ibcon#about to read 5, iclass 2, count 0 2006.201.09:36:16.26#ibcon#read 5, iclass 2, count 0 2006.201.09:36:16.26#ibcon#about to read 6, iclass 2, count 0 2006.201.09:36:16.26#ibcon#read 6, iclass 2, count 0 2006.201.09:36:16.26#ibcon#end of sib2, iclass 2, count 0 2006.201.09:36:16.26#ibcon#*after write, iclass 2, count 0 2006.201.09:36:16.26#ibcon#*before return 0, iclass 2, count 0 2006.201.09:36:16.26#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:16.26#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:16.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:36:16.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:36:16.26$vck44/va=2,7 2006.201.09:36:16.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.09:36:16.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.09:36:16.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:16.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:16.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:16.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:16.31#ibcon#enter wrdev, iclass 5, count 2 2006.201.09:36:16.31#ibcon#first serial, iclass 5, count 2 2006.201.09:36:16.31#ibcon#enter sib2, iclass 5, count 2 2006.201.09:36:16.31#ibcon#flushed, iclass 5, count 2 2006.201.09:36:16.31#ibcon#about to write, iclass 5, count 2 2006.201.09:36:16.31#ibcon#wrote, iclass 5, count 2 2006.201.09:36:16.31#ibcon#about to read 3, iclass 5, count 2 2006.201.09:36:16.33#ibcon#read 3, iclass 5, count 2 2006.201.09:36:16.33#ibcon#about to read 4, iclass 5, count 2 2006.201.09:36:16.33#ibcon#read 4, iclass 5, count 2 2006.201.09:36:16.33#ibcon#about to read 5, iclass 5, count 2 2006.201.09:36:16.33#ibcon#read 5, iclass 5, count 2 2006.201.09:36:16.33#ibcon#about to read 6, iclass 5, count 2 2006.201.09:36:16.33#ibcon#read 6, iclass 5, count 2 2006.201.09:36:16.33#ibcon#end of sib2, iclass 5, count 2 2006.201.09:36:16.33#ibcon#*mode == 0, iclass 5, count 2 2006.201.09:36:16.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.09:36:16.33#ibcon#[25=AT02-07\r\n] 2006.201.09:36:16.33#ibcon#*before write, iclass 5, count 2 2006.201.09:36:16.33#ibcon#enter sib2, iclass 5, count 2 2006.201.09:36:16.33#ibcon#flushed, iclass 5, count 2 2006.201.09:36:16.33#ibcon#about to write, iclass 5, count 2 2006.201.09:36:16.33#ibcon#wrote, iclass 5, count 2 2006.201.09:36:16.33#ibcon#about to read 3, iclass 5, count 2 2006.201.09:36:16.36#ibcon#read 3, iclass 5, count 2 2006.201.09:36:16.36#ibcon#about to read 4, iclass 5, count 2 2006.201.09:36:16.36#ibcon#read 4, iclass 5, count 2 2006.201.09:36:16.36#ibcon#about to read 5, iclass 5, count 2 2006.201.09:36:16.36#ibcon#read 5, iclass 5, count 2 2006.201.09:36:16.36#ibcon#about to read 6, iclass 5, count 2 2006.201.09:36:16.36#ibcon#read 6, iclass 5, count 2 2006.201.09:36:16.36#ibcon#end of sib2, iclass 5, count 2 2006.201.09:36:16.36#ibcon#*after write, iclass 5, count 2 2006.201.09:36:16.36#ibcon#*before return 0, iclass 5, count 2 2006.201.09:36:16.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:16.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:16.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.09:36:16.36#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:16.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:16.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:16.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:16.48#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:36:16.48#ibcon#first serial, iclass 5, count 0 2006.201.09:36:16.48#ibcon#enter sib2, iclass 5, count 0 2006.201.09:36:16.48#ibcon#flushed, iclass 5, count 0 2006.201.09:36:16.48#ibcon#about to write, iclass 5, count 0 2006.201.09:36:16.48#ibcon#wrote, iclass 5, count 0 2006.201.09:36:16.48#ibcon#about to read 3, iclass 5, count 0 2006.201.09:36:16.50#ibcon#read 3, iclass 5, count 0 2006.201.09:36:16.50#ibcon#about to read 4, iclass 5, count 0 2006.201.09:36:16.50#ibcon#read 4, iclass 5, count 0 2006.201.09:36:16.50#ibcon#about to read 5, iclass 5, count 0 2006.201.09:36:16.50#ibcon#read 5, iclass 5, count 0 2006.201.09:36:16.50#ibcon#about to read 6, iclass 5, count 0 2006.201.09:36:16.50#ibcon#read 6, iclass 5, count 0 2006.201.09:36:16.50#ibcon#end of sib2, iclass 5, count 0 2006.201.09:36:16.50#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:36:16.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:36:16.50#ibcon#[25=USB\r\n] 2006.201.09:36:16.50#ibcon#*before write, iclass 5, count 0 2006.201.09:36:16.50#ibcon#enter sib2, iclass 5, count 0 2006.201.09:36:16.50#ibcon#flushed, iclass 5, count 0 2006.201.09:36:16.50#ibcon#about to write, iclass 5, count 0 2006.201.09:36:16.50#ibcon#wrote, iclass 5, count 0 2006.201.09:36:16.50#ibcon#about to read 3, iclass 5, count 0 2006.201.09:36:16.53#ibcon#read 3, iclass 5, count 0 2006.201.09:36:16.53#ibcon#about to read 4, iclass 5, count 0 2006.201.09:36:16.53#ibcon#read 4, iclass 5, count 0 2006.201.09:36:16.53#ibcon#about to read 5, iclass 5, count 0 2006.201.09:36:16.53#ibcon#read 5, iclass 5, count 0 2006.201.09:36:16.53#ibcon#about to read 6, iclass 5, count 0 2006.201.09:36:16.53#ibcon#read 6, iclass 5, count 0 2006.201.09:36:16.53#ibcon#end of sib2, iclass 5, count 0 2006.201.09:36:16.53#ibcon#*after write, iclass 5, count 0 2006.201.09:36:16.53#ibcon#*before return 0, iclass 5, count 0 2006.201.09:36:16.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:16.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:16.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:36:16.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:36:16.53$vck44/valo=3,564.99 2006.201.09:36:16.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.09:36:16.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.09:36:16.53#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:16.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:16.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:16.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:16.53#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:36:16.53#ibcon#first serial, iclass 7, count 0 2006.201.09:36:16.53#ibcon#enter sib2, iclass 7, count 0 2006.201.09:36:16.53#ibcon#flushed, iclass 7, count 0 2006.201.09:36:16.53#ibcon#about to write, iclass 7, count 0 2006.201.09:36:16.53#ibcon#wrote, iclass 7, count 0 2006.201.09:36:16.53#ibcon#about to read 3, iclass 7, count 0 2006.201.09:36:16.55#ibcon#read 3, iclass 7, count 0 2006.201.09:36:16.55#ibcon#about to read 4, iclass 7, count 0 2006.201.09:36:16.55#ibcon#read 4, iclass 7, count 0 2006.201.09:36:16.55#ibcon#about to read 5, iclass 7, count 0 2006.201.09:36:16.55#ibcon#read 5, iclass 7, count 0 2006.201.09:36:16.55#ibcon#about to read 6, iclass 7, count 0 2006.201.09:36:16.55#ibcon#read 6, iclass 7, count 0 2006.201.09:36:16.55#ibcon#end of sib2, iclass 7, count 0 2006.201.09:36:16.55#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:36:16.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:36:16.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:36:16.55#ibcon#*before write, iclass 7, count 0 2006.201.09:36:16.55#ibcon#enter sib2, iclass 7, count 0 2006.201.09:36:16.55#ibcon#flushed, iclass 7, count 0 2006.201.09:36:16.55#ibcon#about to write, iclass 7, count 0 2006.201.09:36:16.55#ibcon#wrote, iclass 7, count 0 2006.201.09:36:16.55#ibcon#about to read 3, iclass 7, count 0 2006.201.09:36:16.60#ibcon#read 3, iclass 7, count 0 2006.201.09:36:16.60#ibcon#about to read 4, iclass 7, count 0 2006.201.09:36:16.60#ibcon#read 4, iclass 7, count 0 2006.201.09:36:16.60#ibcon#about to read 5, iclass 7, count 0 2006.201.09:36:16.60#ibcon#read 5, iclass 7, count 0 2006.201.09:36:16.60#ibcon#about to read 6, iclass 7, count 0 2006.201.09:36:16.60#ibcon#read 6, iclass 7, count 0 2006.201.09:36:16.60#ibcon#end of sib2, iclass 7, count 0 2006.201.09:36:16.60#ibcon#*after write, iclass 7, count 0 2006.201.09:36:16.60#ibcon#*before return 0, iclass 7, count 0 2006.201.09:36:16.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:16.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:16.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:36:16.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:36:16.60$vck44/va=3,8 2006.201.09:36:16.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.09:36:16.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.09:36:16.60#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:16.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:16.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:16.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:16.65#ibcon#enter wrdev, iclass 11, count 2 2006.201.09:36:16.65#ibcon#first serial, iclass 11, count 2 2006.201.09:36:16.65#ibcon#enter sib2, iclass 11, count 2 2006.201.09:36:16.65#ibcon#flushed, iclass 11, count 2 2006.201.09:36:16.65#ibcon#about to write, iclass 11, count 2 2006.201.09:36:16.65#ibcon#wrote, iclass 11, count 2 2006.201.09:36:16.65#ibcon#about to read 3, iclass 11, count 2 2006.201.09:36:16.67#ibcon#read 3, iclass 11, count 2 2006.201.09:36:16.67#ibcon#about to read 4, iclass 11, count 2 2006.201.09:36:16.67#ibcon#read 4, iclass 11, count 2 2006.201.09:36:16.67#ibcon#about to read 5, iclass 11, count 2 2006.201.09:36:16.67#ibcon#read 5, iclass 11, count 2 2006.201.09:36:16.67#ibcon#about to read 6, iclass 11, count 2 2006.201.09:36:16.67#ibcon#read 6, iclass 11, count 2 2006.201.09:36:16.67#ibcon#end of sib2, iclass 11, count 2 2006.201.09:36:16.67#ibcon#*mode == 0, iclass 11, count 2 2006.201.09:36:16.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.09:36:16.67#ibcon#[25=AT03-08\r\n] 2006.201.09:36:16.67#ibcon#*before write, iclass 11, count 2 2006.201.09:36:16.67#ibcon#enter sib2, iclass 11, count 2 2006.201.09:36:16.67#ibcon#flushed, iclass 11, count 2 2006.201.09:36:16.67#ibcon#about to write, iclass 11, count 2 2006.201.09:36:16.67#ibcon#wrote, iclass 11, count 2 2006.201.09:36:16.67#ibcon#about to read 3, iclass 11, count 2 2006.201.09:36:16.70#ibcon#read 3, iclass 11, count 2 2006.201.09:36:16.70#ibcon#about to read 4, iclass 11, count 2 2006.201.09:36:16.70#ibcon#read 4, iclass 11, count 2 2006.201.09:36:16.70#ibcon#about to read 5, iclass 11, count 2 2006.201.09:36:16.70#ibcon#read 5, iclass 11, count 2 2006.201.09:36:16.70#ibcon#about to read 6, iclass 11, count 2 2006.201.09:36:16.70#ibcon#read 6, iclass 11, count 2 2006.201.09:36:16.70#ibcon#end of sib2, iclass 11, count 2 2006.201.09:36:16.70#ibcon#*after write, iclass 11, count 2 2006.201.09:36:16.70#ibcon#*before return 0, iclass 11, count 2 2006.201.09:36:16.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:16.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:16.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.09:36:16.70#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:16.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:16.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:16.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:16.82#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:36:16.82#ibcon#first serial, iclass 11, count 0 2006.201.09:36:16.82#ibcon#enter sib2, iclass 11, count 0 2006.201.09:36:16.82#ibcon#flushed, iclass 11, count 0 2006.201.09:36:16.82#ibcon#about to write, iclass 11, count 0 2006.201.09:36:16.82#ibcon#wrote, iclass 11, count 0 2006.201.09:36:16.82#ibcon#about to read 3, iclass 11, count 0 2006.201.09:36:16.84#ibcon#read 3, iclass 11, count 0 2006.201.09:36:16.84#ibcon#about to read 4, iclass 11, count 0 2006.201.09:36:16.84#ibcon#read 4, iclass 11, count 0 2006.201.09:36:16.84#ibcon#about to read 5, iclass 11, count 0 2006.201.09:36:16.84#ibcon#read 5, iclass 11, count 0 2006.201.09:36:16.84#ibcon#about to read 6, iclass 11, count 0 2006.201.09:36:16.84#ibcon#read 6, iclass 11, count 0 2006.201.09:36:16.84#ibcon#end of sib2, iclass 11, count 0 2006.201.09:36:16.84#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:36:16.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:36:16.84#ibcon#[25=USB\r\n] 2006.201.09:36:16.84#ibcon#*before write, iclass 11, count 0 2006.201.09:36:16.84#ibcon#enter sib2, iclass 11, count 0 2006.201.09:36:16.84#ibcon#flushed, iclass 11, count 0 2006.201.09:36:16.84#ibcon#about to write, iclass 11, count 0 2006.201.09:36:16.84#ibcon#wrote, iclass 11, count 0 2006.201.09:36:16.84#ibcon#about to read 3, iclass 11, count 0 2006.201.09:36:16.87#ibcon#read 3, iclass 11, count 0 2006.201.09:36:16.87#ibcon#about to read 4, iclass 11, count 0 2006.201.09:36:16.87#ibcon#read 4, iclass 11, count 0 2006.201.09:36:16.87#ibcon#about to read 5, iclass 11, count 0 2006.201.09:36:16.87#ibcon#read 5, iclass 11, count 0 2006.201.09:36:16.87#ibcon#about to read 6, iclass 11, count 0 2006.201.09:36:16.87#ibcon#read 6, iclass 11, count 0 2006.201.09:36:16.87#ibcon#end of sib2, iclass 11, count 0 2006.201.09:36:16.87#ibcon#*after write, iclass 11, count 0 2006.201.09:36:16.87#ibcon#*before return 0, iclass 11, count 0 2006.201.09:36:16.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:16.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:16.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:36:16.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:36:16.87$vck44/valo=4,624.99 2006.201.09:36:16.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.09:36:16.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.09:36:16.87#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:16.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:16.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:16.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:16.87#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:36:16.87#ibcon#first serial, iclass 13, count 0 2006.201.09:36:16.87#ibcon#enter sib2, iclass 13, count 0 2006.201.09:36:16.87#ibcon#flushed, iclass 13, count 0 2006.201.09:36:16.87#ibcon#about to write, iclass 13, count 0 2006.201.09:36:16.87#ibcon#wrote, iclass 13, count 0 2006.201.09:36:16.87#ibcon#about to read 3, iclass 13, count 0 2006.201.09:36:16.89#ibcon#read 3, iclass 13, count 0 2006.201.09:36:16.89#ibcon#about to read 4, iclass 13, count 0 2006.201.09:36:16.89#ibcon#read 4, iclass 13, count 0 2006.201.09:36:16.89#ibcon#about to read 5, iclass 13, count 0 2006.201.09:36:16.89#ibcon#read 5, iclass 13, count 0 2006.201.09:36:16.89#ibcon#about to read 6, iclass 13, count 0 2006.201.09:36:16.89#ibcon#read 6, iclass 13, count 0 2006.201.09:36:16.89#ibcon#end of sib2, iclass 13, count 0 2006.201.09:36:16.89#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:36:16.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:36:16.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:36:16.89#ibcon#*before write, iclass 13, count 0 2006.201.09:36:16.89#ibcon#enter sib2, iclass 13, count 0 2006.201.09:36:16.89#ibcon#flushed, iclass 13, count 0 2006.201.09:36:16.89#ibcon#about to write, iclass 13, count 0 2006.201.09:36:16.89#ibcon#wrote, iclass 13, count 0 2006.201.09:36:16.89#ibcon#about to read 3, iclass 13, count 0 2006.201.09:36:16.94#ibcon#read 3, iclass 13, count 0 2006.201.09:36:16.94#ibcon#about to read 4, iclass 13, count 0 2006.201.09:36:16.94#ibcon#read 4, iclass 13, count 0 2006.201.09:36:16.94#ibcon#about to read 5, iclass 13, count 0 2006.201.09:36:16.94#ibcon#read 5, iclass 13, count 0 2006.201.09:36:16.94#ibcon#about to read 6, iclass 13, count 0 2006.201.09:36:16.94#ibcon#read 6, iclass 13, count 0 2006.201.09:36:16.94#ibcon#end of sib2, iclass 13, count 0 2006.201.09:36:16.94#ibcon#*after write, iclass 13, count 0 2006.201.09:36:16.94#ibcon#*before return 0, iclass 13, count 0 2006.201.09:36:16.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:16.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:16.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:36:16.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:36:16.94$vck44/va=4,7 2006.201.09:36:16.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.09:36:16.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.09:36:16.94#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:16.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:16.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:16.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:16.99#ibcon#enter wrdev, iclass 15, count 2 2006.201.09:36:16.99#ibcon#first serial, iclass 15, count 2 2006.201.09:36:16.99#ibcon#enter sib2, iclass 15, count 2 2006.201.09:36:16.99#ibcon#flushed, iclass 15, count 2 2006.201.09:36:16.99#ibcon#about to write, iclass 15, count 2 2006.201.09:36:16.99#ibcon#wrote, iclass 15, count 2 2006.201.09:36:16.99#ibcon#about to read 3, iclass 15, count 2 2006.201.09:36:17.01#ibcon#read 3, iclass 15, count 2 2006.201.09:36:17.01#ibcon#about to read 4, iclass 15, count 2 2006.201.09:36:17.01#ibcon#read 4, iclass 15, count 2 2006.201.09:36:17.01#ibcon#about to read 5, iclass 15, count 2 2006.201.09:36:17.01#ibcon#read 5, iclass 15, count 2 2006.201.09:36:17.01#ibcon#about to read 6, iclass 15, count 2 2006.201.09:36:17.01#ibcon#read 6, iclass 15, count 2 2006.201.09:36:17.01#ibcon#end of sib2, iclass 15, count 2 2006.201.09:36:17.01#ibcon#*mode == 0, iclass 15, count 2 2006.201.09:36:17.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.09:36:17.01#ibcon#[25=AT04-07\r\n] 2006.201.09:36:17.01#ibcon#*before write, iclass 15, count 2 2006.201.09:36:17.01#ibcon#enter sib2, iclass 15, count 2 2006.201.09:36:17.01#ibcon#flushed, iclass 15, count 2 2006.201.09:36:17.01#ibcon#about to write, iclass 15, count 2 2006.201.09:36:17.01#ibcon#wrote, iclass 15, count 2 2006.201.09:36:17.01#ibcon#about to read 3, iclass 15, count 2 2006.201.09:36:17.04#ibcon#read 3, iclass 15, count 2 2006.201.09:36:17.04#ibcon#about to read 4, iclass 15, count 2 2006.201.09:36:17.04#ibcon#read 4, iclass 15, count 2 2006.201.09:36:17.04#ibcon#about to read 5, iclass 15, count 2 2006.201.09:36:17.04#ibcon#read 5, iclass 15, count 2 2006.201.09:36:17.04#ibcon#about to read 6, iclass 15, count 2 2006.201.09:36:17.04#ibcon#read 6, iclass 15, count 2 2006.201.09:36:17.04#ibcon#end of sib2, iclass 15, count 2 2006.201.09:36:17.04#ibcon#*after write, iclass 15, count 2 2006.201.09:36:17.04#ibcon#*before return 0, iclass 15, count 2 2006.201.09:36:17.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:17.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:17.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.09:36:17.04#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:17.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:17.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:17.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:17.16#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:36:17.16#ibcon#first serial, iclass 15, count 0 2006.201.09:36:17.16#ibcon#enter sib2, iclass 15, count 0 2006.201.09:36:17.16#ibcon#flushed, iclass 15, count 0 2006.201.09:36:17.16#ibcon#about to write, iclass 15, count 0 2006.201.09:36:17.16#ibcon#wrote, iclass 15, count 0 2006.201.09:36:17.16#ibcon#about to read 3, iclass 15, count 0 2006.201.09:36:17.18#ibcon#read 3, iclass 15, count 0 2006.201.09:36:17.18#ibcon#about to read 4, iclass 15, count 0 2006.201.09:36:17.18#ibcon#read 4, iclass 15, count 0 2006.201.09:36:17.18#ibcon#about to read 5, iclass 15, count 0 2006.201.09:36:17.18#ibcon#read 5, iclass 15, count 0 2006.201.09:36:17.18#ibcon#about to read 6, iclass 15, count 0 2006.201.09:36:17.18#ibcon#read 6, iclass 15, count 0 2006.201.09:36:17.18#ibcon#end of sib2, iclass 15, count 0 2006.201.09:36:17.18#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:36:17.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:36:17.18#ibcon#[25=USB\r\n] 2006.201.09:36:17.18#ibcon#*before write, iclass 15, count 0 2006.201.09:36:17.18#ibcon#enter sib2, iclass 15, count 0 2006.201.09:36:17.18#ibcon#flushed, iclass 15, count 0 2006.201.09:36:17.18#ibcon#about to write, iclass 15, count 0 2006.201.09:36:17.18#ibcon#wrote, iclass 15, count 0 2006.201.09:36:17.18#ibcon#about to read 3, iclass 15, count 0 2006.201.09:36:17.21#ibcon#read 3, iclass 15, count 0 2006.201.09:36:17.21#ibcon#about to read 4, iclass 15, count 0 2006.201.09:36:17.21#ibcon#read 4, iclass 15, count 0 2006.201.09:36:17.21#ibcon#about to read 5, iclass 15, count 0 2006.201.09:36:17.21#ibcon#read 5, iclass 15, count 0 2006.201.09:36:17.21#ibcon#about to read 6, iclass 15, count 0 2006.201.09:36:17.21#ibcon#read 6, iclass 15, count 0 2006.201.09:36:17.21#ibcon#end of sib2, iclass 15, count 0 2006.201.09:36:17.21#ibcon#*after write, iclass 15, count 0 2006.201.09:36:17.21#ibcon#*before return 0, iclass 15, count 0 2006.201.09:36:17.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:17.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:17.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:36:17.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:36:17.21$vck44/valo=5,734.99 2006.201.09:36:17.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.09:36:17.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.09:36:17.21#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:17.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:17.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:17.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:17.21#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:36:17.21#ibcon#first serial, iclass 17, count 0 2006.201.09:36:17.21#ibcon#enter sib2, iclass 17, count 0 2006.201.09:36:17.21#ibcon#flushed, iclass 17, count 0 2006.201.09:36:17.21#ibcon#about to write, iclass 17, count 0 2006.201.09:36:17.21#ibcon#wrote, iclass 17, count 0 2006.201.09:36:17.21#ibcon#about to read 3, iclass 17, count 0 2006.201.09:36:17.23#ibcon#read 3, iclass 17, count 0 2006.201.09:36:17.23#ibcon#about to read 4, iclass 17, count 0 2006.201.09:36:17.23#ibcon#read 4, iclass 17, count 0 2006.201.09:36:17.23#ibcon#about to read 5, iclass 17, count 0 2006.201.09:36:17.23#ibcon#read 5, iclass 17, count 0 2006.201.09:36:17.23#ibcon#about to read 6, iclass 17, count 0 2006.201.09:36:17.23#ibcon#read 6, iclass 17, count 0 2006.201.09:36:17.23#ibcon#end of sib2, iclass 17, count 0 2006.201.09:36:17.23#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:36:17.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:36:17.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:36:17.23#ibcon#*before write, iclass 17, count 0 2006.201.09:36:17.23#ibcon#enter sib2, iclass 17, count 0 2006.201.09:36:17.23#ibcon#flushed, iclass 17, count 0 2006.201.09:36:17.23#ibcon#about to write, iclass 17, count 0 2006.201.09:36:17.23#ibcon#wrote, iclass 17, count 0 2006.201.09:36:17.23#ibcon#about to read 3, iclass 17, count 0 2006.201.09:36:17.27#ibcon#read 3, iclass 17, count 0 2006.201.09:36:17.27#ibcon#about to read 4, iclass 17, count 0 2006.201.09:36:17.27#ibcon#read 4, iclass 17, count 0 2006.201.09:36:17.27#ibcon#about to read 5, iclass 17, count 0 2006.201.09:36:17.27#ibcon#read 5, iclass 17, count 0 2006.201.09:36:17.27#ibcon#about to read 6, iclass 17, count 0 2006.201.09:36:17.27#ibcon#read 6, iclass 17, count 0 2006.201.09:36:17.27#ibcon#end of sib2, iclass 17, count 0 2006.201.09:36:17.27#ibcon#*after write, iclass 17, count 0 2006.201.09:36:17.27#ibcon#*before return 0, iclass 17, count 0 2006.201.09:36:17.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:17.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:17.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:36:17.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:36:17.27$vck44/va=5,4 2006.201.09:36:17.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.09:36:17.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.09:36:17.27#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:17.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:17.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:17.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:17.33#ibcon#enter wrdev, iclass 19, count 2 2006.201.09:36:17.33#ibcon#first serial, iclass 19, count 2 2006.201.09:36:17.33#ibcon#enter sib2, iclass 19, count 2 2006.201.09:36:17.33#ibcon#flushed, iclass 19, count 2 2006.201.09:36:17.33#ibcon#about to write, iclass 19, count 2 2006.201.09:36:17.33#ibcon#wrote, iclass 19, count 2 2006.201.09:36:17.33#ibcon#about to read 3, iclass 19, count 2 2006.201.09:36:17.35#ibcon#read 3, iclass 19, count 2 2006.201.09:36:17.35#ibcon#about to read 4, iclass 19, count 2 2006.201.09:36:17.35#ibcon#read 4, iclass 19, count 2 2006.201.09:36:17.35#ibcon#about to read 5, iclass 19, count 2 2006.201.09:36:17.35#ibcon#read 5, iclass 19, count 2 2006.201.09:36:17.35#ibcon#about to read 6, iclass 19, count 2 2006.201.09:36:17.35#ibcon#read 6, iclass 19, count 2 2006.201.09:36:17.35#ibcon#end of sib2, iclass 19, count 2 2006.201.09:36:17.35#ibcon#*mode == 0, iclass 19, count 2 2006.201.09:36:17.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.09:36:17.35#ibcon#[25=AT05-04\r\n] 2006.201.09:36:17.35#ibcon#*before write, iclass 19, count 2 2006.201.09:36:17.35#ibcon#enter sib2, iclass 19, count 2 2006.201.09:36:17.35#ibcon#flushed, iclass 19, count 2 2006.201.09:36:17.35#ibcon#about to write, iclass 19, count 2 2006.201.09:36:17.35#ibcon#wrote, iclass 19, count 2 2006.201.09:36:17.35#ibcon#about to read 3, iclass 19, count 2 2006.201.09:36:17.38#ibcon#read 3, iclass 19, count 2 2006.201.09:36:17.38#ibcon#about to read 4, iclass 19, count 2 2006.201.09:36:17.38#ibcon#read 4, iclass 19, count 2 2006.201.09:36:17.38#ibcon#about to read 5, iclass 19, count 2 2006.201.09:36:17.38#ibcon#read 5, iclass 19, count 2 2006.201.09:36:17.38#ibcon#about to read 6, iclass 19, count 2 2006.201.09:36:17.38#ibcon#read 6, iclass 19, count 2 2006.201.09:36:17.38#ibcon#end of sib2, iclass 19, count 2 2006.201.09:36:17.38#ibcon#*after write, iclass 19, count 2 2006.201.09:36:17.38#ibcon#*before return 0, iclass 19, count 2 2006.201.09:36:17.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:17.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:17.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.09:36:17.38#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:17.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:17.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:17.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:17.50#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:36:17.50#ibcon#first serial, iclass 19, count 0 2006.201.09:36:17.50#ibcon#enter sib2, iclass 19, count 0 2006.201.09:36:17.50#ibcon#flushed, iclass 19, count 0 2006.201.09:36:17.50#ibcon#about to write, iclass 19, count 0 2006.201.09:36:17.50#ibcon#wrote, iclass 19, count 0 2006.201.09:36:17.50#ibcon#about to read 3, iclass 19, count 0 2006.201.09:36:17.52#ibcon#read 3, iclass 19, count 0 2006.201.09:36:17.52#ibcon#about to read 4, iclass 19, count 0 2006.201.09:36:17.52#ibcon#read 4, iclass 19, count 0 2006.201.09:36:17.52#ibcon#about to read 5, iclass 19, count 0 2006.201.09:36:17.52#ibcon#read 5, iclass 19, count 0 2006.201.09:36:17.52#ibcon#about to read 6, iclass 19, count 0 2006.201.09:36:17.52#ibcon#read 6, iclass 19, count 0 2006.201.09:36:17.52#ibcon#end of sib2, iclass 19, count 0 2006.201.09:36:17.52#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:36:17.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:36:17.52#ibcon#[25=USB\r\n] 2006.201.09:36:17.52#ibcon#*before write, iclass 19, count 0 2006.201.09:36:17.52#ibcon#enter sib2, iclass 19, count 0 2006.201.09:36:17.52#ibcon#flushed, iclass 19, count 0 2006.201.09:36:17.52#ibcon#about to write, iclass 19, count 0 2006.201.09:36:17.52#ibcon#wrote, iclass 19, count 0 2006.201.09:36:17.52#ibcon#about to read 3, iclass 19, count 0 2006.201.09:36:17.55#ibcon#read 3, iclass 19, count 0 2006.201.09:36:17.55#ibcon#about to read 4, iclass 19, count 0 2006.201.09:36:17.55#ibcon#read 4, iclass 19, count 0 2006.201.09:36:17.55#ibcon#about to read 5, iclass 19, count 0 2006.201.09:36:17.55#ibcon#read 5, iclass 19, count 0 2006.201.09:36:17.55#ibcon#about to read 6, iclass 19, count 0 2006.201.09:36:17.55#ibcon#read 6, iclass 19, count 0 2006.201.09:36:17.55#ibcon#end of sib2, iclass 19, count 0 2006.201.09:36:17.55#ibcon#*after write, iclass 19, count 0 2006.201.09:36:17.55#ibcon#*before return 0, iclass 19, count 0 2006.201.09:36:17.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:17.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:17.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:36:17.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:36:17.55$vck44/valo=6,814.99 2006.201.09:36:17.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.09:36:17.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.09:36:17.55#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:17.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:17.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:17.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:17.55#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:36:17.55#ibcon#first serial, iclass 21, count 0 2006.201.09:36:17.55#ibcon#enter sib2, iclass 21, count 0 2006.201.09:36:17.55#ibcon#flushed, iclass 21, count 0 2006.201.09:36:17.55#ibcon#about to write, iclass 21, count 0 2006.201.09:36:17.55#ibcon#wrote, iclass 21, count 0 2006.201.09:36:17.55#ibcon#about to read 3, iclass 21, count 0 2006.201.09:36:17.57#ibcon#read 3, iclass 21, count 0 2006.201.09:36:17.57#ibcon#about to read 4, iclass 21, count 0 2006.201.09:36:17.57#ibcon#read 4, iclass 21, count 0 2006.201.09:36:17.57#ibcon#about to read 5, iclass 21, count 0 2006.201.09:36:17.57#ibcon#read 5, iclass 21, count 0 2006.201.09:36:17.57#ibcon#about to read 6, iclass 21, count 0 2006.201.09:36:17.57#ibcon#read 6, iclass 21, count 0 2006.201.09:36:17.57#ibcon#end of sib2, iclass 21, count 0 2006.201.09:36:17.57#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:36:17.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:36:17.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:36:17.57#ibcon#*before write, iclass 21, count 0 2006.201.09:36:17.57#ibcon#enter sib2, iclass 21, count 0 2006.201.09:36:17.57#ibcon#flushed, iclass 21, count 0 2006.201.09:36:17.57#ibcon#about to write, iclass 21, count 0 2006.201.09:36:17.57#ibcon#wrote, iclass 21, count 0 2006.201.09:36:17.57#ibcon#about to read 3, iclass 21, count 0 2006.201.09:36:17.62#ibcon#read 3, iclass 21, count 0 2006.201.09:36:17.62#ibcon#about to read 4, iclass 21, count 0 2006.201.09:36:17.62#ibcon#read 4, iclass 21, count 0 2006.201.09:36:17.62#ibcon#about to read 5, iclass 21, count 0 2006.201.09:36:17.62#ibcon#read 5, iclass 21, count 0 2006.201.09:36:17.62#ibcon#about to read 6, iclass 21, count 0 2006.201.09:36:17.62#ibcon#read 6, iclass 21, count 0 2006.201.09:36:17.62#ibcon#end of sib2, iclass 21, count 0 2006.201.09:36:17.62#ibcon#*after write, iclass 21, count 0 2006.201.09:36:17.62#ibcon#*before return 0, iclass 21, count 0 2006.201.09:36:17.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:17.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:17.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:36:17.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:36:17.62$vck44/va=6,5 2006.201.09:36:17.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.09:36:17.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.09:36:17.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:17.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:17.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:17.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:17.67#ibcon#enter wrdev, iclass 23, count 2 2006.201.09:36:17.67#ibcon#first serial, iclass 23, count 2 2006.201.09:36:17.67#ibcon#enter sib2, iclass 23, count 2 2006.201.09:36:17.67#ibcon#flushed, iclass 23, count 2 2006.201.09:36:17.67#ibcon#about to write, iclass 23, count 2 2006.201.09:36:17.67#ibcon#wrote, iclass 23, count 2 2006.201.09:36:17.67#ibcon#about to read 3, iclass 23, count 2 2006.201.09:36:17.69#ibcon#read 3, iclass 23, count 2 2006.201.09:36:17.69#ibcon#about to read 4, iclass 23, count 2 2006.201.09:36:17.69#ibcon#read 4, iclass 23, count 2 2006.201.09:36:17.69#ibcon#about to read 5, iclass 23, count 2 2006.201.09:36:17.69#ibcon#read 5, iclass 23, count 2 2006.201.09:36:17.69#ibcon#about to read 6, iclass 23, count 2 2006.201.09:36:17.69#ibcon#read 6, iclass 23, count 2 2006.201.09:36:17.69#ibcon#end of sib2, iclass 23, count 2 2006.201.09:36:17.69#ibcon#*mode == 0, iclass 23, count 2 2006.201.09:36:17.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.09:36:17.69#ibcon#[25=AT06-05\r\n] 2006.201.09:36:17.69#ibcon#*before write, iclass 23, count 2 2006.201.09:36:17.69#ibcon#enter sib2, iclass 23, count 2 2006.201.09:36:17.69#ibcon#flushed, iclass 23, count 2 2006.201.09:36:17.69#ibcon#about to write, iclass 23, count 2 2006.201.09:36:17.69#ibcon#wrote, iclass 23, count 2 2006.201.09:36:17.69#ibcon#about to read 3, iclass 23, count 2 2006.201.09:36:17.72#ibcon#read 3, iclass 23, count 2 2006.201.09:36:17.72#ibcon#about to read 4, iclass 23, count 2 2006.201.09:36:17.72#ibcon#read 4, iclass 23, count 2 2006.201.09:36:17.72#ibcon#about to read 5, iclass 23, count 2 2006.201.09:36:17.72#ibcon#read 5, iclass 23, count 2 2006.201.09:36:17.72#ibcon#about to read 6, iclass 23, count 2 2006.201.09:36:17.72#ibcon#read 6, iclass 23, count 2 2006.201.09:36:17.72#ibcon#end of sib2, iclass 23, count 2 2006.201.09:36:17.72#ibcon#*after write, iclass 23, count 2 2006.201.09:36:17.72#ibcon#*before return 0, iclass 23, count 2 2006.201.09:36:17.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:17.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:17.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.09:36:17.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:17.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:17.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:17.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:17.84#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:36:17.84#ibcon#first serial, iclass 23, count 0 2006.201.09:36:17.84#ibcon#enter sib2, iclass 23, count 0 2006.201.09:36:17.84#ibcon#flushed, iclass 23, count 0 2006.201.09:36:17.84#ibcon#about to write, iclass 23, count 0 2006.201.09:36:17.84#ibcon#wrote, iclass 23, count 0 2006.201.09:36:17.84#ibcon#about to read 3, iclass 23, count 0 2006.201.09:36:17.86#ibcon#read 3, iclass 23, count 0 2006.201.09:36:17.86#ibcon#about to read 4, iclass 23, count 0 2006.201.09:36:17.86#ibcon#read 4, iclass 23, count 0 2006.201.09:36:17.86#ibcon#about to read 5, iclass 23, count 0 2006.201.09:36:17.86#ibcon#read 5, iclass 23, count 0 2006.201.09:36:17.86#ibcon#about to read 6, iclass 23, count 0 2006.201.09:36:17.86#ibcon#read 6, iclass 23, count 0 2006.201.09:36:17.86#ibcon#end of sib2, iclass 23, count 0 2006.201.09:36:17.86#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:36:17.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:36:17.86#ibcon#[25=USB\r\n] 2006.201.09:36:17.86#ibcon#*before write, iclass 23, count 0 2006.201.09:36:17.86#ibcon#enter sib2, iclass 23, count 0 2006.201.09:36:17.86#ibcon#flushed, iclass 23, count 0 2006.201.09:36:17.86#ibcon#about to write, iclass 23, count 0 2006.201.09:36:17.86#ibcon#wrote, iclass 23, count 0 2006.201.09:36:17.86#ibcon#about to read 3, iclass 23, count 0 2006.201.09:36:17.89#ibcon#read 3, iclass 23, count 0 2006.201.09:36:17.89#ibcon#about to read 4, iclass 23, count 0 2006.201.09:36:17.89#ibcon#read 4, iclass 23, count 0 2006.201.09:36:17.89#ibcon#about to read 5, iclass 23, count 0 2006.201.09:36:17.89#ibcon#read 5, iclass 23, count 0 2006.201.09:36:17.89#ibcon#about to read 6, iclass 23, count 0 2006.201.09:36:17.89#ibcon#read 6, iclass 23, count 0 2006.201.09:36:17.89#ibcon#end of sib2, iclass 23, count 0 2006.201.09:36:17.89#ibcon#*after write, iclass 23, count 0 2006.201.09:36:17.89#ibcon#*before return 0, iclass 23, count 0 2006.201.09:36:17.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:17.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:17.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:36:17.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:36:17.89$vck44/valo=7,864.99 2006.201.09:36:17.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.09:36:17.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.09:36:17.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:17.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:36:17.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:36:17.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:36:17.89#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:36:17.89#ibcon#first serial, iclass 25, count 0 2006.201.09:36:17.89#ibcon#enter sib2, iclass 25, count 0 2006.201.09:36:17.89#ibcon#flushed, iclass 25, count 0 2006.201.09:36:17.89#ibcon#about to write, iclass 25, count 0 2006.201.09:36:17.89#ibcon#wrote, iclass 25, count 0 2006.201.09:36:17.89#ibcon#about to read 3, iclass 25, count 0 2006.201.09:36:17.91#ibcon#read 3, iclass 25, count 0 2006.201.09:36:17.91#ibcon#about to read 4, iclass 25, count 0 2006.201.09:36:17.91#ibcon#read 4, iclass 25, count 0 2006.201.09:36:17.91#ibcon#about to read 5, iclass 25, count 0 2006.201.09:36:17.91#ibcon#read 5, iclass 25, count 0 2006.201.09:36:17.91#ibcon#about to read 6, iclass 25, count 0 2006.201.09:36:17.91#ibcon#read 6, iclass 25, count 0 2006.201.09:36:17.91#ibcon#end of sib2, iclass 25, count 0 2006.201.09:36:17.91#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:36:17.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:36:17.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:36:17.91#ibcon#*before write, iclass 25, count 0 2006.201.09:36:17.91#ibcon#enter sib2, iclass 25, count 0 2006.201.09:36:17.91#ibcon#flushed, iclass 25, count 0 2006.201.09:36:17.91#ibcon#about to write, iclass 25, count 0 2006.201.09:36:17.91#ibcon#wrote, iclass 25, count 0 2006.201.09:36:17.91#ibcon#about to read 3, iclass 25, count 0 2006.201.09:36:17.95#ibcon#read 3, iclass 25, count 0 2006.201.09:36:17.95#ibcon#about to read 4, iclass 25, count 0 2006.201.09:36:17.95#ibcon#read 4, iclass 25, count 0 2006.201.09:36:17.95#ibcon#about to read 5, iclass 25, count 0 2006.201.09:36:17.95#ibcon#read 5, iclass 25, count 0 2006.201.09:36:17.95#ibcon#about to read 6, iclass 25, count 0 2006.201.09:36:17.95#ibcon#read 6, iclass 25, count 0 2006.201.09:36:17.95#ibcon#end of sib2, iclass 25, count 0 2006.201.09:36:17.95#ibcon#*after write, iclass 25, count 0 2006.201.09:36:17.95#ibcon#*before return 0, iclass 25, count 0 2006.201.09:36:17.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:36:17.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:36:17.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:36:17.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:36:17.95$vck44/va=7,5 2006.201.09:36:17.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.09:36:17.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.09:36:17.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:17.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:36:18.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:36:18.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:36:18.01#ibcon#enter wrdev, iclass 27, count 2 2006.201.09:36:18.01#ibcon#first serial, iclass 27, count 2 2006.201.09:36:18.01#ibcon#enter sib2, iclass 27, count 2 2006.201.09:36:18.01#ibcon#flushed, iclass 27, count 2 2006.201.09:36:18.01#ibcon#about to write, iclass 27, count 2 2006.201.09:36:18.01#ibcon#wrote, iclass 27, count 2 2006.201.09:36:18.01#ibcon#about to read 3, iclass 27, count 2 2006.201.09:36:18.03#ibcon#read 3, iclass 27, count 2 2006.201.09:36:18.03#ibcon#about to read 4, iclass 27, count 2 2006.201.09:36:18.03#ibcon#read 4, iclass 27, count 2 2006.201.09:36:18.03#ibcon#about to read 5, iclass 27, count 2 2006.201.09:36:18.03#ibcon#read 5, iclass 27, count 2 2006.201.09:36:18.03#ibcon#about to read 6, iclass 27, count 2 2006.201.09:36:18.03#ibcon#read 6, iclass 27, count 2 2006.201.09:36:18.03#ibcon#end of sib2, iclass 27, count 2 2006.201.09:36:18.03#ibcon#*mode == 0, iclass 27, count 2 2006.201.09:36:18.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.09:36:18.03#ibcon#[25=AT07-05\r\n] 2006.201.09:36:18.03#ibcon#*before write, iclass 27, count 2 2006.201.09:36:18.03#ibcon#enter sib2, iclass 27, count 2 2006.201.09:36:18.03#ibcon#flushed, iclass 27, count 2 2006.201.09:36:18.03#ibcon#about to write, iclass 27, count 2 2006.201.09:36:18.03#ibcon#wrote, iclass 27, count 2 2006.201.09:36:18.03#ibcon#about to read 3, iclass 27, count 2 2006.201.09:36:18.06#ibcon#read 3, iclass 27, count 2 2006.201.09:36:18.06#ibcon#about to read 4, iclass 27, count 2 2006.201.09:36:18.06#ibcon#read 4, iclass 27, count 2 2006.201.09:36:18.06#ibcon#about to read 5, iclass 27, count 2 2006.201.09:36:18.06#ibcon#read 5, iclass 27, count 2 2006.201.09:36:18.06#ibcon#about to read 6, iclass 27, count 2 2006.201.09:36:18.06#ibcon#read 6, iclass 27, count 2 2006.201.09:36:18.06#ibcon#end of sib2, iclass 27, count 2 2006.201.09:36:18.06#ibcon#*after write, iclass 27, count 2 2006.201.09:36:18.06#ibcon#*before return 0, iclass 27, count 2 2006.201.09:36:18.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:36:18.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:36:18.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.09:36:18.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:18.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:36:18.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:36:18.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:36:18.18#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:36:18.18#ibcon#first serial, iclass 27, count 0 2006.201.09:36:18.18#ibcon#enter sib2, iclass 27, count 0 2006.201.09:36:18.18#ibcon#flushed, iclass 27, count 0 2006.201.09:36:18.18#ibcon#about to write, iclass 27, count 0 2006.201.09:36:18.18#ibcon#wrote, iclass 27, count 0 2006.201.09:36:18.18#ibcon#about to read 3, iclass 27, count 0 2006.201.09:36:18.21#ibcon#read 3, iclass 27, count 0 2006.201.09:36:18.21#ibcon#about to read 4, iclass 27, count 0 2006.201.09:36:18.21#ibcon#read 4, iclass 27, count 0 2006.201.09:36:18.21#ibcon#about to read 5, iclass 27, count 0 2006.201.09:36:18.21#ibcon#read 5, iclass 27, count 0 2006.201.09:36:18.21#ibcon#about to read 6, iclass 27, count 0 2006.201.09:36:18.21#ibcon#read 6, iclass 27, count 0 2006.201.09:36:18.21#ibcon#end of sib2, iclass 27, count 0 2006.201.09:36:18.21#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:36:18.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:36:18.21#ibcon#[25=USB\r\n] 2006.201.09:36:18.21#ibcon#*before write, iclass 27, count 0 2006.201.09:36:18.21#ibcon#enter sib2, iclass 27, count 0 2006.201.09:36:18.21#ibcon#flushed, iclass 27, count 0 2006.201.09:36:18.21#ibcon#about to write, iclass 27, count 0 2006.201.09:36:18.21#ibcon#wrote, iclass 27, count 0 2006.201.09:36:18.21#ibcon#about to read 3, iclass 27, count 0 2006.201.09:36:18.24#ibcon#read 3, iclass 27, count 0 2006.201.09:36:18.24#ibcon#about to read 4, iclass 27, count 0 2006.201.09:36:18.24#ibcon#read 4, iclass 27, count 0 2006.201.09:36:18.24#ibcon#about to read 5, iclass 27, count 0 2006.201.09:36:18.24#ibcon#read 5, iclass 27, count 0 2006.201.09:36:18.24#ibcon#about to read 6, iclass 27, count 0 2006.201.09:36:18.24#ibcon#read 6, iclass 27, count 0 2006.201.09:36:18.24#ibcon#end of sib2, iclass 27, count 0 2006.201.09:36:18.24#ibcon#*after write, iclass 27, count 0 2006.201.09:36:18.24#ibcon#*before return 0, iclass 27, count 0 2006.201.09:36:18.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:36:18.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:36:18.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:36:18.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:36:18.24$vck44/valo=8,884.99 2006.201.09:36:18.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.09:36:18.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.09:36:18.24#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:18.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:18.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:18.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:18.24#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:36:18.24#ibcon#first serial, iclass 29, count 0 2006.201.09:36:18.24#ibcon#enter sib2, iclass 29, count 0 2006.201.09:36:18.24#ibcon#flushed, iclass 29, count 0 2006.201.09:36:18.24#ibcon#about to write, iclass 29, count 0 2006.201.09:36:18.24#ibcon#wrote, iclass 29, count 0 2006.201.09:36:18.24#ibcon#about to read 3, iclass 29, count 0 2006.201.09:36:18.26#ibcon#read 3, iclass 29, count 0 2006.201.09:36:18.26#ibcon#about to read 4, iclass 29, count 0 2006.201.09:36:18.26#ibcon#read 4, iclass 29, count 0 2006.201.09:36:18.26#ibcon#about to read 5, iclass 29, count 0 2006.201.09:36:18.26#ibcon#read 5, iclass 29, count 0 2006.201.09:36:18.26#ibcon#about to read 6, iclass 29, count 0 2006.201.09:36:18.26#ibcon#read 6, iclass 29, count 0 2006.201.09:36:18.26#ibcon#end of sib2, iclass 29, count 0 2006.201.09:36:18.26#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:36:18.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:36:18.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:36:18.26#ibcon#*before write, iclass 29, count 0 2006.201.09:36:18.26#ibcon#enter sib2, iclass 29, count 0 2006.201.09:36:18.26#ibcon#flushed, iclass 29, count 0 2006.201.09:36:18.26#ibcon#about to write, iclass 29, count 0 2006.201.09:36:18.26#ibcon#wrote, iclass 29, count 0 2006.201.09:36:18.26#ibcon#about to read 3, iclass 29, count 0 2006.201.09:36:18.30#ibcon#read 3, iclass 29, count 0 2006.201.09:36:18.30#ibcon#about to read 4, iclass 29, count 0 2006.201.09:36:18.30#ibcon#read 4, iclass 29, count 0 2006.201.09:36:18.30#ibcon#about to read 5, iclass 29, count 0 2006.201.09:36:18.30#ibcon#read 5, iclass 29, count 0 2006.201.09:36:18.30#ibcon#about to read 6, iclass 29, count 0 2006.201.09:36:18.30#ibcon#read 6, iclass 29, count 0 2006.201.09:36:18.30#ibcon#end of sib2, iclass 29, count 0 2006.201.09:36:18.30#ibcon#*after write, iclass 29, count 0 2006.201.09:36:18.30#ibcon#*before return 0, iclass 29, count 0 2006.201.09:36:18.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:18.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:18.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:36:18.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:36:18.30$vck44/va=8,4 2006.201.09:36:18.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.09:36:18.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.09:36:18.30#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:18.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:18.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:18.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:18.36#ibcon#enter wrdev, iclass 31, count 2 2006.201.09:36:18.36#ibcon#first serial, iclass 31, count 2 2006.201.09:36:18.36#ibcon#enter sib2, iclass 31, count 2 2006.201.09:36:18.36#ibcon#flushed, iclass 31, count 2 2006.201.09:36:18.36#ibcon#about to write, iclass 31, count 2 2006.201.09:36:18.36#ibcon#wrote, iclass 31, count 2 2006.201.09:36:18.36#ibcon#about to read 3, iclass 31, count 2 2006.201.09:36:18.38#ibcon#read 3, iclass 31, count 2 2006.201.09:36:18.38#ibcon#about to read 4, iclass 31, count 2 2006.201.09:36:18.38#ibcon#read 4, iclass 31, count 2 2006.201.09:36:18.38#ibcon#about to read 5, iclass 31, count 2 2006.201.09:36:18.38#ibcon#read 5, iclass 31, count 2 2006.201.09:36:18.38#ibcon#about to read 6, iclass 31, count 2 2006.201.09:36:18.38#ibcon#read 6, iclass 31, count 2 2006.201.09:36:18.38#ibcon#end of sib2, iclass 31, count 2 2006.201.09:36:18.38#ibcon#*mode == 0, iclass 31, count 2 2006.201.09:36:18.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.09:36:18.38#ibcon#[25=AT08-04\r\n] 2006.201.09:36:18.38#ibcon#*before write, iclass 31, count 2 2006.201.09:36:18.38#ibcon#enter sib2, iclass 31, count 2 2006.201.09:36:18.38#ibcon#flushed, iclass 31, count 2 2006.201.09:36:18.38#ibcon#about to write, iclass 31, count 2 2006.201.09:36:18.38#ibcon#wrote, iclass 31, count 2 2006.201.09:36:18.38#ibcon#about to read 3, iclass 31, count 2 2006.201.09:36:18.41#ibcon#read 3, iclass 31, count 2 2006.201.09:36:18.41#ibcon#about to read 4, iclass 31, count 2 2006.201.09:36:18.41#ibcon#read 4, iclass 31, count 2 2006.201.09:36:18.41#ibcon#about to read 5, iclass 31, count 2 2006.201.09:36:18.41#ibcon#read 5, iclass 31, count 2 2006.201.09:36:18.41#ibcon#about to read 6, iclass 31, count 2 2006.201.09:36:18.41#ibcon#read 6, iclass 31, count 2 2006.201.09:36:18.41#ibcon#end of sib2, iclass 31, count 2 2006.201.09:36:18.41#ibcon#*after write, iclass 31, count 2 2006.201.09:36:18.41#ibcon#*before return 0, iclass 31, count 2 2006.201.09:36:18.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:18.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:18.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.09:36:18.41#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:18.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:18.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:18.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:18.53#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:36:18.53#ibcon#first serial, iclass 31, count 0 2006.201.09:36:18.53#ibcon#enter sib2, iclass 31, count 0 2006.201.09:36:18.53#ibcon#flushed, iclass 31, count 0 2006.201.09:36:18.53#ibcon#about to write, iclass 31, count 0 2006.201.09:36:18.53#ibcon#wrote, iclass 31, count 0 2006.201.09:36:18.53#ibcon#about to read 3, iclass 31, count 0 2006.201.09:36:18.55#ibcon#read 3, iclass 31, count 0 2006.201.09:36:18.55#ibcon#about to read 4, iclass 31, count 0 2006.201.09:36:18.55#ibcon#read 4, iclass 31, count 0 2006.201.09:36:18.55#ibcon#about to read 5, iclass 31, count 0 2006.201.09:36:18.55#ibcon#read 5, iclass 31, count 0 2006.201.09:36:18.55#ibcon#about to read 6, iclass 31, count 0 2006.201.09:36:18.55#ibcon#read 6, iclass 31, count 0 2006.201.09:36:18.55#ibcon#end of sib2, iclass 31, count 0 2006.201.09:36:18.55#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:36:18.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:36:18.55#ibcon#[25=USB\r\n] 2006.201.09:36:18.55#ibcon#*before write, iclass 31, count 0 2006.201.09:36:18.55#ibcon#enter sib2, iclass 31, count 0 2006.201.09:36:18.55#ibcon#flushed, iclass 31, count 0 2006.201.09:36:18.55#ibcon#about to write, iclass 31, count 0 2006.201.09:36:18.55#ibcon#wrote, iclass 31, count 0 2006.201.09:36:18.55#ibcon#about to read 3, iclass 31, count 0 2006.201.09:36:18.58#ibcon#read 3, iclass 31, count 0 2006.201.09:36:18.58#ibcon#about to read 4, iclass 31, count 0 2006.201.09:36:18.58#ibcon#read 4, iclass 31, count 0 2006.201.09:36:18.58#ibcon#about to read 5, iclass 31, count 0 2006.201.09:36:18.58#ibcon#read 5, iclass 31, count 0 2006.201.09:36:18.58#ibcon#about to read 6, iclass 31, count 0 2006.201.09:36:18.58#ibcon#read 6, iclass 31, count 0 2006.201.09:36:18.58#ibcon#end of sib2, iclass 31, count 0 2006.201.09:36:18.58#ibcon#*after write, iclass 31, count 0 2006.201.09:36:18.58#ibcon#*before return 0, iclass 31, count 0 2006.201.09:36:18.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:18.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:18.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:36:18.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:36:18.58$vck44/vblo=1,629.99 2006.201.09:36:18.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.09:36:18.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.09:36:18.58#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:18.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:18.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:18.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:18.58#ibcon#enter wrdev, iclass 33, count 0 2006.201.09:36:18.58#ibcon#first serial, iclass 33, count 0 2006.201.09:36:18.58#ibcon#enter sib2, iclass 33, count 0 2006.201.09:36:18.58#ibcon#flushed, iclass 33, count 0 2006.201.09:36:18.58#ibcon#about to write, iclass 33, count 0 2006.201.09:36:18.58#ibcon#wrote, iclass 33, count 0 2006.201.09:36:18.58#ibcon#about to read 3, iclass 33, count 0 2006.201.09:36:18.60#ibcon#read 3, iclass 33, count 0 2006.201.09:36:18.60#ibcon#about to read 4, iclass 33, count 0 2006.201.09:36:18.60#ibcon#read 4, iclass 33, count 0 2006.201.09:36:18.60#ibcon#about to read 5, iclass 33, count 0 2006.201.09:36:18.60#ibcon#read 5, iclass 33, count 0 2006.201.09:36:18.60#ibcon#about to read 6, iclass 33, count 0 2006.201.09:36:18.60#ibcon#read 6, iclass 33, count 0 2006.201.09:36:18.60#ibcon#end of sib2, iclass 33, count 0 2006.201.09:36:18.60#ibcon#*mode == 0, iclass 33, count 0 2006.201.09:36:18.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.09:36:18.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:36:18.60#ibcon#*before write, iclass 33, count 0 2006.201.09:36:18.60#ibcon#enter sib2, iclass 33, count 0 2006.201.09:36:18.60#ibcon#flushed, iclass 33, count 0 2006.201.09:36:18.60#ibcon#about to write, iclass 33, count 0 2006.201.09:36:18.60#ibcon#wrote, iclass 33, count 0 2006.201.09:36:18.60#ibcon#about to read 3, iclass 33, count 0 2006.201.09:36:18.64#ibcon#read 3, iclass 33, count 0 2006.201.09:36:18.64#ibcon#about to read 4, iclass 33, count 0 2006.201.09:36:18.64#ibcon#read 4, iclass 33, count 0 2006.201.09:36:18.64#ibcon#about to read 5, iclass 33, count 0 2006.201.09:36:18.64#ibcon#read 5, iclass 33, count 0 2006.201.09:36:18.64#ibcon#about to read 6, iclass 33, count 0 2006.201.09:36:18.64#ibcon#read 6, iclass 33, count 0 2006.201.09:36:18.64#ibcon#end of sib2, iclass 33, count 0 2006.201.09:36:18.64#ibcon#*after write, iclass 33, count 0 2006.201.09:36:18.64#ibcon#*before return 0, iclass 33, count 0 2006.201.09:36:18.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:18.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:18.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.09:36:18.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.09:36:18.64$vck44/vb=1,4 2006.201.09:36:18.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.09:36:18.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.09:36:18.64#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:18.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:36:18.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:36:18.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:36:18.64#ibcon#enter wrdev, iclass 35, count 2 2006.201.09:36:18.64#ibcon#first serial, iclass 35, count 2 2006.201.09:36:18.64#ibcon#enter sib2, iclass 35, count 2 2006.201.09:36:18.64#ibcon#flushed, iclass 35, count 2 2006.201.09:36:18.64#ibcon#about to write, iclass 35, count 2 2006.201.09:36:18.64#ibcon#wrote, iclass 35, count 2 2006.201.09:36:18.64#ibcon#about to read 3, iclass 35, count 2 2006.201.09:36:18.66#ibcon#read 3, iclass 35, count 2 2006.201.09:36:18.66#ibcon#about to read 4, iclass 35, count 2 2006.201.09:36:18.66#ibcon#read 4, iclass 35, count 2 2006.201.09:36:18.66#ibcon#about to read 5, iclass 35, count 2 2006.201.09:36:18.66#ibcon#read 5, iclass 35, count 2 2006.201.09:36:18.66#ibcon#about to read 6, iclass 35, count 2 2006.201.09:36:18.66#ibcon#read 6, iclass 35, count 2 2006.201.09:36:18.66#ibcon#end of sib2, iclass 35, count 2 2006.201.09:36:18.66#ibcon#*mode == 0, iclass 35, count 2 2006.201.09:36:18.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.09:36:18.66#ibcon#[27=AT01-04\r\n] 2006.201.09:36:18.66#ibcon#*before write, iclass 35, count 2 2006.201.09:36:18.66#ibcon#enter sib2, iclass 35, count 2 2006.201.09:36:18.66#ibcon#flushed, iclass 35, count 2 2006.201.09:36:18.66#ibcon#about to write, iclass 35, count 2 2006.201.09:36:18.66#ibcon#wrote, iclass 35, count 2 2006.201.09:36:18.66#ibcon#about to read 3, iclass 35, count 2 2006.201.09:36:18.69#ibcon#read 3, iclass 35, count 2 2006.201.09:36:18.69#ibcon#about to read 4, iclass 35, count 2 2006.201.09:36:18.69#ibcon#read 4, iclass 35, count 2 2006.201.09:36:18.69#ibcon#about to read 5, iclass 35, count 2 2006.201.09:36:18.69#ibcon#read 5, iclass 35, count 2 2006.201.09:36:18.69#ibcon#about to read 6, iclass 35, count 2 2006.201.09:36:18.69#ibcon#read 6, iclass 35, count 2 2006.201.09:36:18.69#ibcon#end of sib2, iclass 35, count 2 2006.201.09:36:18.69#ibcon#*after write, iclass 35, count 2 2006.201.09:36:18.69#ibcon#*before return 0, iclass 35, count 2 2006.201.09:36:18.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:36:18.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:36:18.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.09:36:18.69#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:18.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:36:18.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:36:18.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:36:18.81#ibcon#enter wrdev, iclass 35, count 0 2006.201.09:36:18.81#ibcon#first serial, iclass 35, count 0 2006.201.09:36:18.81#ibcon#enter sib2, iclass 35, count 0 2006.201.09:36:18.81#ibcon#flushed, iclass 35, count 0 2006.201.09:36:18.81#ibcon#about to write, iclass 35, count 0 2006.201.09:36:18.81#ibcon#wrote, iclass 35, count 0 2006.201.09:36:18.81#ibcon#about to read 3, iclass 35, count 0 2006.201.09:36:18.83#ibcon#read 3, iclass 35, count 0 2006.201.09:36:18.83#ibcon#about to read 4, iclass 35, count 0 2006.201.09:36:18.83#ibcon#read 4, iclass 35, count 0 2006.201.09:36:18.83#ibcon#about to read 5, iclass 35, count 0 2006.201.09:36:18.83#ibcon#read 5, iclass 35, count 0 2006.201.09:36:18.83#ibcon#about to read 6, iclass 35, count 0 2006.201.09:36:18.83#ibcon#read 6, iclass 35, count 0 2006.201.09:36:18.83#ibcon#end of sib2, iclass 35, count 0 2006.201.09:36:18.83#ibcon#*mode == 0, iclass 35, count 0 2006.201.09:36:18.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.09:36:18.83#ibcon#[27=USB\r\n] 2006.201.09:36:18.83#ibcon#*before write, iclass 35, count 0 2006.201.09:36:18.83#ibcon#enter sib2, iclass 35, count 0 2006.201.09:36:18.83#ibcon#flushed, iclass 35, count 0 2006.201.09:36:18.83#ibcon#about to write, iclass 35, count 0 2006.201.09:36:18.83#ibcon#wrote, iclass 35, count 0 2006.201.09:36:18.83#ibcon#about to read 3, iclass 35, count 0 2006.201.09:36:18.86#ibcon#read 3, iclass 35, count 0 2006.201.09:36:18.86#ibcon#about to read 4, iclass 35, count 0 2006.201.09:36:18.86#ibcon#read 4, iclass 35, count 0 2006.201.09:36:18.86#ibcon#about to read 5, iclass 35, count 0 2006.201.09:36:18.86#ibcon#read 5, iclass 35, count 0 2006.201.09:36:18.86#ibcon#about to read 6, iclass 35, count 0 2006.201.09:36:18.86#ibcon#read 6, iclass 35, count 0 2006.201.09:36:18.86#ibcon#end of sib2, iclass 35, count 0 2006.201.09:36:18.86#ibcon#*after write, iclass 35, count 0 2006.201.09:36:18.86#ibcon#*before return 0, iclass 35, count 0 2006.201.09:36:18.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:36:18.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:36:18.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.09:36:18.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.09:36:18.86$vck44/vblo=2,634.99 2006.201.09:36:18.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.09:36:18.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.09:36:18.86#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:18.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:18.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:18.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:18.86#ibcon#enter wrdev, iclass 37, count 0 2006.201.09:36:18.86#ibcon#first serial, iclass 37, count 0 2006.201.09:36:18.86#ibcon#enter sib2, iclass 37, count 0 2006.201.09:36:18.86#ibcon#flushed, iclass 37, count 0 2006.201.09:36:18.86#ibcon#about to write, iclass 37, count 0 2006.201.09:36:18.86#ibcon#wrote, iclass 37, count 0 2006.201.09:36:18.86#ibcon#about to read 3, iclass 37, count 0 2006.201.09:36:18.88#ibcon#read 3, iclass 37, count 0 2006.201.09:36:18.88#ibcon#about to read 4, iclass 37, count 0 2006.201.09:36:18.88#ibcon#read 4, iclass 37, count 0 2006.201.09:36:18.88#ibcon#about to read 5, iclass 37, count 0 2006.201.09:36:18.88#ibcon#read 5, iclass 37, count 0 2006.201.09:36:18.88#ibcon#about to read 6, iclass 37, count 0 2006.201.09:36:18.88#ibcon#read 6, iclass 37, count 0 2006.201.09:36:18.88#ibcon#end of sib2, iclass 37, count 0 2006.201.09:36:18.88#ibcon#*mode == 0, iclass 37, count 0 2006.201.09:36:18.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.09:36:18.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:36:18.88#ibcon#*before write, iclass 37, count 0 2006.201.09:36:18.88#ibcon#enter sib2, iclass 37, count 0 2006.201.09:36:18.88#ibcon#flushed, iclass 37, count 0 2006.201.09:36:18.88#ibcon#about to write, iclass 37, count 0 2006.201.09:36:18.88#ibcon#wrote, iclass 37, count 0 2006.201.09:36:18.88#ibcon#about to read 3, iclass 37, count 0 2006.201.09:36:18.92#ibcon#read 3, iclass 37, count 0 2006.201.09:36:18.92#ibcon#about to read 4, iclass 37, count 0 2006.201.09:36:18.92#ibcon#read 4, iclass 37, count 0 2006.201.09:36:18.92#ibcon#about to read 5, iclass 37, count 0 2006.201.09:36:18.92#ibcon#read 5, iclass 37, count 0 2006.201.09:36:18.92#ibcon#about to read 6, iclass 37, count 0 2006.201.09:36:18.92#ibcon#read 6, iclass 37, count 0 2006.201.09:36:18.92#ibcon#end of sib2, iclass 37, count 0 2006.201.09:36:18.92#ibcon#*after write, iclass 37, count 0 2006.201.09:36:18.92#ibcon#*before return 0, iclass 37, count 0 2006.201.09:36:18.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:18.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:36:18.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.09:36:18.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.09:36:18.92$vck44/vb=2,5 2006.201.09:36:18.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.09:36:18.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.09:36:18.92#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:18.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:18.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:18.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:18.98#ibcon#enter wrdev, iclass 39, count 2 2006.201.09:36:18.98#ibcon#first serial, iclass 39, count 2 2006.201.09:36:18.98#ibcon#enter sib2, iclass 39, count 2 2006.201.09:36:18.98#ibcon#flushed, iclass 39, count 2 2006.201.09:36:18.98#ibcon#about to write, iclass 39, count 2 2006.201.09:36:18.98#ibcon#wrote, iclass 39, count 2 2006.201.09:36:18.98#ibcon#about to read 3, iclass 39, count 2 2006.201.09:36:19.00#ibcon#read 3, iclass 39, count 2 2006.201.09:36:19.00#ibcon#about to read 4, iclass 39, count 2 2006.201.09:36:19.00#ibcon#read 4, iclass 39, count 2 2006.201.09:36:19.00#ibcon#about to read 5, iclass 39, count 2 2006.201.09:36:19.00#ibcon#read 5, iclass 39, count 2 2006.201.09:36:19.00#ibcon#about to read 6, iclass 39, count 2 2006.201.09:36:19.00#ibcon#read 6, iclass 39, count 2 2006.201.09:36:19.00#ibcon#end of sib2, iclass 39, count 2 2006.201.09:36:19.00#ibcon#*mode == 0, iclass 39, count 2 2006.201.09:36:19.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.09:36:19.00#ibcon#[27=AT02-05\r\n] 2006.201.09:36:19.00#ibcon#*before write, iclass 39, count 2 2006.201.09:36:19.00#ibcon#enter sib2, iclass 39, count 2 2006.201.09:36:19.00#ibcon#flushed, iclass 39, count 2 2006.201.09:36:19.00#ibcon#about to write, iclass 39, count 2 2006.201.09:36:19.00#ibcon#wrote, iclass 39, count 2 2006.201.09:36:19.00#ibcon#about to read 3, iclass 39, count 2 2006.201.09:36:19.03#ibcon#read 3, iclass 39, count 2 2006.201.09:36:19.03#ibcon#about to read 4, iclass 39, count 2 2006.201.09:36:19.03#ibcon#read 4, iclass 39, count 2 2006.201.09:36:19.03#ibcon#about to read 5, iclass 39, count 2 2006.201.09:36:19.03#ibcon#read 5, iclass 39, count 2 2006.201.09:36:19.03#ibcon#about to read 6, iclass 39, count 2 2006.201.09:36:19.03#ibcon#read 6, iclass 39, count 2 2006.201.09:36:19.03#ibcon#end of sib2, iclass 39, count 2 2006.201.09:36:19.03#ibcon#*after write, iclass 39, count 2 2006.201.09:36:19.03#ibcon#*before return 0, iclass 39, count 2 2006.201.09:36:19.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:19.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:36:19.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.09:36:19.03#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:19.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:19.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:19.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:19.15#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:36:19.15#ibcon#first serial, iclass 39, count 0 2006.201.09:36:19.15#ibcon#enter sib2, iclass 39, count 0 2006.201.09:36:19.15#ibcon#flushed, iclass 39, count 0 2006.201.09:36:19.15#ibcon#about to write, iclass 39, count 0 2006.201.09:36:19.15#ibcon#wrote, iclass 39, count 0 2006.201.09:36:19.15#ibcon#about to read 3, iclass 39, count 0 2006.201.09:36:19.17#ibcon#read 3, iclass 39, count 0 2006.201.09:36:19.17#ibcon#about to read 4, iclass 39, count 0 2006.201.09:36:19.17#ibcon#read 4, iclass 39, count 0 2006.201.09:36:19.17#ibcon#about to read 5, iclass 39, count 0 2006.201.09:36:19.17#ibcon#read 5, iclass 39, count 0 2006.201.09:36:19.17#ibcon#about to read 6, iclass 39, count 0 2006.201.09:36:19.17#ibcon#read 6, iclass 39, count 0 2006.201.09:36:19.17#ibcon#end of sib2, iclass 39, count 0 2006.201.09:36:19.17#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:36:19.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:36:19.17#ibcon#[27=USB\r\n] 2006.201.09:36:19.17#ibcon#*before write, iclass 39, count 0 2006.201.09:36:19.17#ibcon#enter sib2, iclass 39, count 0 2006.201.09:36:19.17#ibcon#flushed, iclass 39, count 0 2006.201.09:36:19.17#ibcon#about to write, iclass 39, count 0 2006.201.09:36:19.17#ibcon#wrote, iclass 39, count 0 2006.201.09:36:19.17#ibcon#about to read 3, iclass 39, count 0 2006.201.09:36:19.20#ibcon#read 3, iclass 39, count 0 2006.201.09:36:19.20#ibcon#about to read 4, iclass 39, count 0 2006.201.09:36:19.20#ibcon#read 4, iclass 39, count 0 2006.201.09:36:19.20#ibcon#about to read 5, iclass 39, count 0 2006.201.09:36:19.20#ibcon#read 5, iclass 39, count 0 2006.201.09:36:19.20#ibcon#about to read 6, iclass 39, count 0 2006.201.09:36:19.20#ibcon#read 6, iclass 39, count 0 2006.201.09:36:19.20#ibcon#end of sib2, iclass 39, count 0 2006.201.09:36:19.20#ibcon#*after write, iclass 39, count 0 2006.201.09:36:19.20#ibcon#*before return 0, iclass 39, count 0 2006.201.09:36:19.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:19.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:36:19.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:36:19.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:36:19.20$vck44/vblo=3,649.99 2006.201.09:36:19.20#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.09:36:19.20#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.09:36:19.20#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:19.20#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:19.20#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:19.20#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:19.20#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:36:19.20#ibcon#first serial, iclass 2, count 0 2006.201.09:36:19.20#ibcon#enter sib2, iclass 2, count 0 2006.201.09:36:19.20#ibcon#flushed, iclass 2, count 0 2006.201.09:36:19.20#ibcon#about to write, iclass 2, count 0 2006.201.09:36:19.20#ibcon#wrote, iclass 2, count 0 2006.201.09:36:19.20#ibcon#about to read 3, iclass 2, count 0 2006.201.09:36:19.22#ibcon#read 3, iclass 2, count 0 2006.201.09:36:19.22#ibcon#about to read 4, iclass 2, count 0 2006.201.09:36:19.22#ibcon#read 4, iclass 2, count 0 2006.201.09:36:19.22#ibcon#about to read 5, iclass 2, count 0 2006.201.09:36:19.22#ibcon#read 5, iclass 2, count 0 2006.201.09:36:19.22#ibcon#about to read 6, iclass 2, count 0 2006.201.09:36:19.22#ibcon#read 6, iclass 2, count 0 2006.201.09:36:19.22#ibcon#end of sib2, iclass 2, count 0 2006.201.09:36:19.22#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:36:19.22#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:36:19.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:36:19.22#ibcon#*before write, iclass 2, count 0 2006.201.09:36:19.22#ibcon#enter sib2, iclass 2, count 0 2006.201.09:36:19.22#ibcon#flushed, iclass 2, count 0 2006.201.09:36:19.22#ibcon#about to write, iclass 2, count 0 2006.201.09:36:19.22#ibcon#wrote, iclass 2, count 0 2006.201.09:36:19.22#ibcon#about to read 3, iclass 2, count 0 2006.201.09:36:19.26#ibcon#read 3, iclass 2, count 0 2006.201.09:36:19.26#ibcon#about to read 4, iclass 2, count 0 2006.201.09:36:19.26#ibcon#read 4, iclass 2, count 0 2006.201.09:36:19.26#ibcon#about to read 5, iclass 2, count 0 2006.201.09:36:19.26#ibcon#read 5, iclass 2, count 0 2006.201.09:36:19.26#ibcon#about to read 6, iclass 2, count 0 2006.201.09:36:19.26#ibcon#read 6, iclass 2, count 0 2006.201.09:36:19.26#ibcon#end of sib2, iclass 2, count 0 2006.201.09:36:19.26#ibcon#*after write, iclass 2, count 0 2006.201.09:36:19.26#ibcon#*before return 0, iclass 2, count 0 2006.201.09:36:19.26#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:19.26#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:36:19.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:36:19.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:36:19.26$vck44/vb=3,4 2006.201.09:36:19.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.09:36:19.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.09:36:19.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:19.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:19.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:19.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:19.32#ibcon#enter wrdev, iclass 5, count 2 2006.201.09:36:19.32#ibcon#first serial, iclass 5, count 2 2006.201.09:36:19.32#ibcon#enter sib2, iclass 5, count 2 2006.201.09:36:19.32#ibcon#flushed, iclass 5, count 2 2006.201.09:36:19.32#ibcon#about to write, iclass 5, count 2 2006.201.09:36:19.32#ibcon#wrote, iclass 5, count 2 2006.201.09:36:19.32#ibcon#about to read 3, iclass 5, count 2 2006.201.09:36:19.34#ibcon#read 3, iclass 5, count 2 2006.201.09:36:19.34#ibcon#about to read 4, iclass 5, count 2 2006.201.09:36:19.34#ibcon#read 4, iclass 5, count 2 2006.201.09:36:19.34#ibcon#about to read 5, iclass 5, count 2 2006.201.09:36:19.34#ibcon#read 5, iclass 5, count 2 2006.201.09:36:19.34#ibcon#about to read 6, iclass 5, count 2 2006.201.09:36:19.34#ibcon#read 6, iclass 5, count 2 2006.201.09:36:19.34#ibcon#end of sib2, iclass 5, count 2 2006.201.09:36:19.34#ibcon#*mode == 0, iclass 5, count 2 2006.201.09:36:19.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.09:36:19.34#ibcon#[27=AT03-04\r\n] 2006.201.09:36:19.34#ibcon#*before write, iclass 5, count 2 2006.201.09:36:19.34#ibcon#enter sib2, iclass 5, count 2 2006.201.09:36:19.34#ibcon#flushed, iclass 5, count 2 2006.201.09:36:19.34#ibcon#about to write, iclass 5, count 2 2006.201.09:36:19.34#ibcon#wrote, iclass 5, count 2 2006.201.09:36:19.34#ibcon#about to read 3, iclass 5, count 2 2006.201.09:36:19.37#ibcon#read 3, iclass 5, count 2 2006.201.09:36:19.37#ibcon#about to read 4, iclass 5, count 2 2006.201.09:36:19.37#ibcon#read 4, iclass 5, count 2 2006.201.09:36:19.37#ibcon#about to read 5, iclass 5, count 2 2006.201.09:36:19.37#ibcon#read 5, iclass 5, count 2 2006.201.09:36:19.37#ibcon#about to read 6, iclass 5, count 2 2006.201.09:36:19.37#ibcon#read 6, iclass 5, count 2 2006.201.09:36:19.37#ibcon#end of sib2, iclass 5, count 2 2006.201.09:36:19.37#ibcon#*after write, iclass 5, count 2 2006.201.09:36:19.37#ibcon#*before return 0, iclass 5, count 2 2006.201.09:36:19.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:19.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:36:19.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.09:36:19.37#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:19.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:19.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:19.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:19.49#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:36:19.49#ibcon#first serial, iclass 5, count 0 2006.201.09:36:19.49#ibcon#enter sib2, iclass 5, count 0 2006.201.09:36:19.49#ibcon#flushed, iclass 5, count 0 2006.201.09:36:19.49#ibcon#about to write, iclass 5, count 0 2006.201.09:36:19.49#ibcon#wrote, iclass 5, count 0 2006.201.09:36:19.49#ibcon#about to read 3, iclass 5, count 0 2006.201.09:36:19.51#ibcon#read 3, iclass 5, count 0 2006.201.09:36:19.51#ibcon#about to read 4, iclass 5, count 0 2006.201.09:36:19.51#ibcon#read 4, iclass 5, count 0 2006.201.09:36:19.51#ibcon#about to read 5, iclass 5, count 0 2006.201.09:36:19.51#ibcon#read 5, iclass 5, count 0 2006.201.09:36:19.51#ibcon#about to read 6, iclass 5, count 0 2006.201.09:36:19.51#ibcon#read 6, iclass 5, count 0 2006.201.09:36:19.51#ibcon#end of sib2, iclass 5, count 0 2006.201.09:36:19.51#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:36:19.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:36:19.51#ibcon#[27=USB\r\n] 2006.201.09:36:19.51#ibcon#*before write, iclass 5, count 0 2006.201.09:36:19.51#ibcon#enter sib2, iclass 5, count 0 2006.201.09:36:19.51#ibcon#flushed, iclass 5, count 0 2006.201.09:36:19.51#ibcon#about to write, iclass 5, count 0 2006.201.09:36:19.51#ibcon#wrote, iclass 5, count 0 2006.201.09:36:19.51#ibcon#about to read 3, iclass 5, count 0 2006.201.09:36:19.54#ibcon#read 3, iclass 5, count 0 2006.201.09:36:19.54#ibcon#about to read 4, iclass 5, count 0 2006.201.09:36:19.54#ibcon#read 4, iclass 5, count 0 2006.201.09:36:19.54#ibcon#about to read 5, iclass 5, count 0 2006.201.09:36:19.54#ibcon#read 5, iclass 5, count 0 2006.201.09:36:19.54#ibcon#about to read 6, iclass 5, count 0 2006.201.09:36:19.54#ibcon#read 6, iclass 5, count 0 2006.201.09:36:19.54#ibcon#end of sib2, iclass 5, count 0 2006.201.09:36:19.54#ibcon#*after write, iclass 5, count 0 2006.201.09:36:19.54#ibcon#*before return 0, iclass 5, count 0 2006.201.09:36:19.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:19.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:36:19.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:36:19.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:36:19.54$vck44/vblo=4,679.99 2006.201.09:36:19.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.09:36:19.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.09:36:19.54#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:19.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:19.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:19.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:19.54#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:36:19.54#ibcon#first serial, iclass 7, count 0 2006.201.09:36:19.54#ibcon#enter sib2, iclass 7, count 0 2006.201.09:36:19.54#ibcon#flushed, iclass 7, count 0 2006.201.09:36:19.54#ibcon#about to write, iclass 7, count 0 2006.201.09:36:19.54#ibcon#wrote, iclass 7, count 0 2006.201.09:36:19.54#ibcon#about to read 3, iclass 7, count 0 2006.201.09:36:19.56#ibcon#read 3, iclass 7, count 0 2006.201.09:36:19.56#ibcon#about to read 4, iclass 7, count 0 2006.201.09:36:19.56#ibcon#read 4, iclass 7, count 0 2006.201.09:36:19.56#ibcon#about to read 5, iclass 7, count 0 2006.201.09:36:19.56#ibcon#read 5, iclass 7, count 0 2006.201.09:36:19.56#ibcon#about to read 6, iclass 7, count 0 2006.201.09:36:19.56#ibcon#read 6, iclass 7, count 0 2006.201.09:36:19.56#ibcon#end of sib2, iclass 7, count 0 2006.201.09:36:19.56#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:36:19.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:36:19.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:36:19.56#ibcon#*before write, iclass 7, count 0 2006.201.09:36:19.56#ibcon#enter sib2, iclass 7, count 0 2006.201.09:36:19.56#ibcon#flushed, iclass 7, count 0 2006.201.09:36:19.56#ibcon#about to write, iclass 7, count 0 2006.201.09:36:19.56#ibcon#wrote, iclass 7, count 0 2006.201.09:36:19.56#ibcon#about to read 3, iclass 7, count 0 2006.201.09:36:19.60#ibcon#read 3, iclass 7, count 0 2006.201.09:36:19.60#ibcon#about to read 4, iclass 7, count 0 2006.201.09:36:19.60#ibcon#read 4, iclass 7, count 0 2006.201.09:36:19.60#ibcon#about to read 5, iclass 7, count 0 2006.201.09:36:19.60#ibcon#read 5, iclass 7, count 0 2006.201.09:36:19.60#ibcon#about to read 6, iclass 7, count 0 2006.201.09:36:19.60#ibcon#read 6, iclass 7, count 0 2006.201.09:36:19.60#ibcon#end of sib2, iclass 7, count 0 2006.201.09:36:19.60#ibcon#*after write, iclass 7, count 0 2006.201.09:36:19.60#ibcon#*before return 0, iclass 7, count 0 2006.201.09:36:19.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:19.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:36:19.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:36:19.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:36:19.60$vck44/vb=4,5 2006.201.09:36:19.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.09:36:19.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.09:36:19.60#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:19.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:19.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:19.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:19.66#ibcon#enter wrdev, iclass 11, count 2 2006.201.09:36:19.66#ibcon#first serial, iclass 11, count 2 2006.201.09:36:19.66#ibcon#enter sib2, iclass 11, count 2 2006.201.09:36:19.66#ibcon#flushed, iclass 11, count 2 2006.201.09:36:19.66#ibcon#about to write, iclass 11, count 2 2006.201.09:36:19.66#ibcon#wrote, iclass 11, count 2 2006.201.09:36:19.66#ibcon#about to read 3, iclass 11, count 2 2006.201.09:36:19.68#ibcon#read 3, iclass 11, count 2 2006.201.09:36:19.68#ibcon#about to read 4, iclass 11, count 2 2006.201.09:36:19.68#ibcon#read 4, iclass 11, count 2 2006.201.09:36:19.68#ibcon#about to read 5, iclass 11, count 2 2006.201.09:36:19.68#ibcon#read 5, iclass 11, count 2 2006.201.09:36:19.68#ibcon#about to read 6, iclass 11, count 2 2006.201.09:36:19.68#ibcon#read 6, iclass 11, count 2 2006.201.09:36:19.68#ibcon#end of sib2, iclass 11, count 2 2006.201.09:36:19.68#ibcon#*mode == 0, iclass 11, count 2 2006.201.09:36:19.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.09:36:19.68#ibcon#[27=AT04-05\r\n] 2006.201.09:36:19.68#ibcon#*before write, iclass 11, count 2 2006.201.09:36:19.68#ibcon#enter sib2, iclass 11, count 2 2006.201.09:36:19.68#ibcon#flushed, iclass 11, count 2 2006.201.09:36:19.68#ibcon#about to write, iclass 11, count 2 2006.201.09:36:19.68#ibcon#wrote, iclass 11, count 2 2006.201.09:36:19.68#ibcon#about to read 3, iclass 11, count 2 2006.201.09:36:19.71#ibcon#read 3, iclass 11, count 2 2006.201.09:36:19.71#ibcon#about to read 4, iclass 11, count 2 2006.201.09:36:19.71#ibcon#read 4, iclass 11, count 2 2006.201.09:36:19.71#ibcon#about to read 5, iclass 11, count 2 2006.201.09:36:19.71#ibcon#read 5, iclass 11, count 2 2006.201.09:36:19.71#ibcon#about to read 6, iclass 11, count 2 2006.201.09:36:19.71#ibcon#read 6, iclass 11, count 2 2006.201.09:36:19.71#ibcon#end of sib2, iclass 11, count 2 2006.201.09:36:19.71#ibcon#*after write, iclass 11, count 2 2006.201.09:36:19.71#ibcon#*before return 0, iclass 11, count 2 2006.201.09:36:19.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:19.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:36:19.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.09:36:19.71#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:19.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:19.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:19.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:19.83#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:36:19.83#ibcon#first serial, iclass 11, count 0 2006.201.09:36:19.83#ibcon#enter sib2, iclass 11, count 0 2006.201.09:36:19.83#ibcon#flushed, iclass 11, count 0 2006.201.09:36:19.83#ibcon#about to write, iclass 11, count 0 2006.201.09:36:19.83#ibcon#wrote, iclass 11, count 0 2006.201.09:36:19.83#ibcon#about to read 3, iclass 11, count 0 2006.201.09:36:19.85#ibcon#read 3, iclass 11, count 0 2006.201.09:36:19.85#ibcon#about to read 4, iclass 11, count 0 2006.201.09:36:19.85#ibcon#read 4, iclass 11, count 0 2006.201.09:36:19.85#ibcon#about to read 5, iclass 11, count 0 2006.201.09:36:19.85#ibcon#read 5, iclass 11, count 0 2006.201.09:36:19.85#ibcon#about to read 6, iclass 11, count 0 2006.201.09:36:19.85#ibcon#read 6, iclass 11, count 0 2006.201.09:36:19.85#ibcon#end of sib2, iclass 11, count 0 2006.201.09:36:19.85#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:36:19.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:36:19.85#ibcon#[27=USB\r\n] 2006.201.09:36:19.85#ibcon#*before write, iclass 11, count 0 2006.201.09:36:19.85#ibcon#enter sib2, iclass 11, count 0 2006.201.09:36:19.85#ibcon#flushed, iclass 11, count 0 2006.201.09:36:19.85#ibcon#about to write, iclass 11, count 0 2006.201.09:36:19.85#ibcon#wrote, iclass 11, count 0 2006.201.09:36:19.85#ibcon#about to read 3, iclass 11, count 0 2006.201.09:36:19.88#ibcon#read 3, iclass 11, count 0 2006.201.09:36:19.88#ibcon#about to read 4, iclass 11, count 0 2006.201.09:36:19.88#ibcon#read 4, iclass 11, count 0 2006.201.09:36:19.88#ibcon#about to read 5, iclass 11, count 0 2006.201.09:36:19.88#ibcon#read 5, iclass 11, count 0 2006.201.09:36:19.88#ibcon#about to read 6, iclass 11, count 0 2006.201.09:36:19.88#ibcon#read 6, iclass 11, count 0 2006.201.09:36:19.88#ibcon#end of sib2, iclass 11, count 0 2006.201.09:36:19.88#ibcon#*after write, iclass 11, count 0 2006.201.09:36:19.88#ibcon#*before return 0, iclass 11, count 0 2006.201.09:36:19.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:19.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:36:19.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:36:19.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:36:19.88$vck44/vblo=5,709.99 2006.201.09:36:19.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.09:36:19.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.09:36:19.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:19.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:19.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:19.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:19.88#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:36:19.88#ibcon#first serial, iclass 13, count 0 2006.201.09:36:19.88#ibcon#enter sib2, iclass 13, count 0 2006.201.09:36:19.88#ibcon#flushed, iclass 13, count 0 2006.201.09:36:19.88#ibcon#about to write, iclass 13, count 0 2006.201.09:36:19.88#ibcon#wrote, iclass 13, count 0 2006.201.09:36:19.88#ibcon#about to read 3, iclass 13, count 0 2006.201.09:36:19.90#ibcon#read 3, iclass 13, count 0 2006.201.09:36:19.90#ibcon#about to read 4, iclass 13, count 0 2006.201.09:36:19.90#ibcon#read 4, iclass 13, count 0 2006.201.09:36:19.90#ibcon#about to read 5, iclass 13, count 0 2006.201.09:36:19.90#ibcon#read 5, iclass 13, count 0 2006.201.09:36:19.90#ibcon#about to read 6, iclass 13, count 0 2006.201.09:36:19.90#ibcon#read 6, iclass 13, count 0 2006.201.09:36:19.90#ibcon#end of sib2, iclass 13, count 0 2006.201.09:36:19.90#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:36:19.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:36:19.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:36:19.90#ibcon#*before write, iclass 13, count 0 2006.201.09:36:19.90#ibcon#enter sib2, iclass 13, count 0 2006.201.09:36:19.90#ibcon#flushed, iclass 13, count 0 2006.201.09:36:19.90#ibcon#about to write, iclass 13, count 0 2006.201.09:36:19.90#ibcon#wrote, iclass 13, count 0 2006.201.09:36:19.90#ibcon#about to read 3, iclass 13, count 0 2006.201.09:36:19.95#ibcon#read 3, iclass 13, count 0 2006.201.09:36:19.95#ibcon#about to read 4, iclass 13, count 0 2006.201.09:36:19.95#ibcon#read 4, iclass 13, count 0 2006.201.09:36:19.95#ibcon#about to read 5, iclass 13, count 0 2006.201.09:36:19.95#ibcon#read 5, iclass 13, count 0 2006.201.09:36:19.95#ibcon#about to read 6, iclass 13, count 0 2006.201.09:36:19.95#ibcon#read 6, iclass 13, count 0 2006.201.09:36:19.95#ibcon#end of sib2, iclass 13, count 0 2006.201.09:36:19.95#ibcon#*after write, iclass 13, count 0 2006.201.09:36:19.95#ibcon#*before return 0, iclass 13, count 0 2006.201.09:36:19.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:19.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:36:19.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:36:19.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:36:19.95$vck44/vb=5,4 2006.201.09:36:19.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.09:36:19.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.09:36:19.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:19.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:20.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:20.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:20.00#ibcon#enter wrdev, iclass 15, count 2 2006.201.09:36:20.00#ibcon#first serial, iclass 15, count 2 2006.201.09:36:20.00#ibcon#enter sib2, iclass 15, count 2 2006.201.09:36:20.00#ibcon#flushed, iclass 15, count 2 2006.201.09:36:20.00#ibcon#about to write, iclass 15, count 2 2006.201.09:36:20.00#ibcon#wrote, iclass 15, count 2 2006.201.09:36:20.00#ibcon#about to read 3, iclass 15, count 2 2006.201.09:36:20.02#ibcon#read 3, iclass 15, count 2 2006.201.09:36:20.02#ibcon#about to read 4, iclass 15, count 2 2006.201.09:36:20.02#ibcon#read 4, iclass 15, count 2 2006.201.09:36:20.02#ibcon#about to read 5, iclass 15, count 2 2006.201.09:36:20.02#ibcon#read 5, iclass 15, count 2 2006.201.09:36:20.02#ibcon#about to read 6, iclass 15, count 2 2006.201.09:36:20.02#ibcon#read 6, iclass 15, count 2 2006.201.09:36:20.02#ibcon#end of sib2, iclass 15, count 2 2006.201.09:36:20.02#ibcon#*mode == 0, iclass 15, count 2 2006.201.09:36:20.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.09:36:20.02#ibcon#[27=AT05-04\r\n] 2006.201.09:36:20.02#ibcon#*before write, iclass 15, count 2 2006.201.09:36:20.02#ibcon#enter sib2, iclass 15, count 2 2006.201.09:36:20.02#ibcon#flushed, iclass 15, count 2 2006.201.09:36:20.02#ibcon#about to write, iclass 15, count 2 2006.201.09:36:20.02#ibcon#wrote, iclass 15, count 2 2006.201.09:36:20.02#ibcon#about to read 3, iclass 15, count 2 2006.201.09:36:20.05#ibcon#read 3, iclass 15, count 2 2006.201.09:36:20.05#ibcon#about to read 4, iclass 15, count 2 2006.201.09:36:20.05#ibcon#read 4, iclass 15, count 2 2006.201.09:36:20.05#ibcon#about to read 5, iclass 15, count 2 2006.201.09:36:20.05#ibcon#read 5, iclass 15, count 2 2006.201.09:36:20.05#ibcon#about to read 6, iclass 15, count 2 2006.201.09:36:20.05#ibcon#read 6, iclass 15, count 2 2006.201.09:36:20.05#ibcon#end of sib2, iclass 15, count 2 2006.201.09:36:20.05#ibcon#*after write, iclass 15, count 2 2006.201.09:36:20.05#ibcon#*before return 0, iclass 15, count 2 2006.201.09:36:20.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:20.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:36:20.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.09:36:20.05#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:20.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:20.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:20.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:20.17#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:36:20.17#ibcon#first serial, iclass 15, count 0 2006.201.09:36:20.17#ibcon#enter sib2, iclass 15, count 0 2006.201.09:36:20.17#ibcon#flushed, iclass 15, count 0 2006.201.09:36:20.17#ibcon#about to write, iclass 15, count 0 2006.201.09:36:20.17#ibcon#wrote, iclass 15, count 0 2006.201.09:36:20.17#ibcon#about to read 3, iclass 15, count 0 2006.201.09:36:20.20#ibcon#read 3, iclass 15, count 0 2006.201.09:36:20.20#ibcon#about to read 4, iclass 15, count 0 2006.201.09:36:20.20#ibcon#read 4, iclass 15, count 0 2006.201.09:36:20.20#ibcon#about to read 5, iclass 15, count 0 2006.201.09:36:20.20#ibcon#read 5, iclass 15, count 0 2006.201.09:36:20.20#ibcon#about to read 6, iclass 15, count 0 2006.201.09:36:20.20#ibcon#read 6, iclass 15, count 0 2006.201.09:36:20.20#ibcon#end of sib2, iclass 15, count 0 2006.201.09:36:20.20#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:36:20.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:36:20.20#ibcon#[27=USB\r\n] 2006.201.09:36:20.20#ibcon#*before write, iclass 15, count 0 2006.201.09:36:20.20#ibcon#enter sib2, iclass 15, count 0 2006.201.09:36:20.20#ibcon#flushed, iclass 15, count 0 2006.201.09:36:20.20#ibcon#about to write, iclass 15, count 0 2006.201.09:36:20.20#ibcon#wrote, iclass 15, count 0 2006.201.09:36:20.20#ibcon#about to read 3, iclass 15, count 0 2006.201.09:36:20.23#ibcon#read 3, iclass 15, count 0 2006.201.09:36:20.23#ibcon#about to read 4, iclass 15, count 0 2006.201.09:36:20.23#ibcon#read 4, iclass 15, count 0 2006.201.09:36:20.23#ibcon#about to read 5, iclass 15, count 0 2006.201.09:36:20.23#ibcon#read 5, iclass 15, count 0 2006.201.09:36:20.23#ibcon#about to read 6, iclass 15, count 0 2006.201.09:36:20.23#ibcon#read 6, iclass 15, count 0 2006.201.09:36:20.23#ibcon#end of sib2, iclass 15, count 0 2006.201.09:36:20.23#ibcon#*after write, iclass 15, count 0 2006.201.09:36:20.23#ibcon#*before return 0, iclass 15, count 0 2006.201.09:36:20.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:20.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:36:20.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:36:20.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:36:20.23$vck44/vblo=6,719.99 2006.201.09:36:20.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.09:36:20.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.09:36:20.23#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:20.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:20.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:20.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:20.23#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:36:20.23#ibcon#first serial, iclass 17, count 0 2006.201.09:36:20.23#ibcon#enter sib2, iclass 17, count 0 2006.201.09:36:20.23#ibcon#flushed, iclass 17, count 0 2006.201.09:36:20.23#ibcon#about to write, iclass 17, count 0 2006.201.09:36:20.23#ibcon#wrote, iclass 17, count 0 2006.201.09:36:20.23#ibcon#about to read 3, iclass 17, count 0 2006.201.09:36:20.25#ibcon#read 3, iclass 17, count 0 2006.201.09:36:20.25#ibcon#about to read 4, iclass 17, count 0 2006.201.09:36:20.25#ibcon#read 4, iclass 17, count 0 2006.201.09:36:20.25#ibcon#about to read 5, iclass 17, count 0 2006.201.09:36:20.25#ibcon#read 5, iclass 17, count 0 2006.201.09:36:20.25#ibcon#about to read 6, iclass 17, count 0 2006.201.09:36:20.25#ibcon#read 6, iclass 17, count 0 2006.201.09:36:20.25#ibcon#end of sib2, iclass 17, count 0 2006.201.09:36:20.25#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:36:20.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:36:20.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:36:20.25#ibcon#*before write, iclass 17, count 0 2006.201.09:36:20.25#ibcon#enter sib2, iclass 17, count 0 2006.201.09:36:20.25#ibcon#flushed, iclass 17, count 0 2006.201.09:36:20.25#ibcon#about to write, iclass 17, count 0 2006.201.09:36:20.25#ibcon#wrote, iclass 17, count 0 2006.201.09:36:20.25#ibcon#about to read 3, iclass 17, count 0 2006.201.09:36:20.29#ibcon#read 3, iclass 17, count 0 2006.201.09:36:20.29#ibcon#about to read 4, iclass 17, count 0 2006.201.09:36:20.29#ibcon#read 4, iclass 17, count 0 2006.201.09:36:20.29#ibcon#about to read 5, iclass 17, count 0 2006.201.09:36:20.29#ibcon#read 5, iclass 17, count 0 2006.201.09:36:20.29#ibcon#about to read 6, iclass 17, count 0 2006.201.09:36:20.29#ibcon#read 6, iclass 17, count 0 2006.201.09:36:20.29#ibcon#end of sib2, iclass 17, count 0 2006.201.09:36:20.29#ibcon#*after write, iclass 17, count 0 2006.201.09:36:20.29#ibcon#*before return 0, iclass 17, count 0 2006.201.09:36:20.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:20.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:36:20.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:36:20.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:36:20.29$vck44/vb=6,4 2006.201.09:36:20.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.09:36:20.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.09:36:20.29#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:20.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:20.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:20.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:20.35#ibcon#enter wrdev, iclass 19, count 2 2006.201.09:36:20.35#ibcon#first serial, iclass 19, count 2 2006.201.09:36:20.35#ibcon#enter sib2, iclass 19, count 2 2006.201.09:36:20.35#ibcon#flushed, iclass 19, count 2 2006.201.09:36:20.35#ibcon#about to write, iclass 19, count 2 2006.201.09:36:20.35#ibcon#wrote, iclass 19, count 2 2006.201.09:36:20.35#ibcon#about to read 3, iclass 19, count 2 2006.201.09:36:20.37#ibcon#read 3, iclass 19, count 2 2006.201.09:36:20.37#ibcon#about to read 4, iclass 19, count 2 2006.201.09:36:20.37#ibcon#read 4, iclass 19, count 2 2006.201.09:36:20.37#ibcon#about to read 5, iclass 19, count 2 2006.201.09:36:20.37#ibcon#read 5, iclass 19, count 2 2006.201.09:36:20.37#ibcon#about to read 6, iclass 19, count 2 2006.201.09:36:20.37#ibcon#read 6, iclass 19, count 2 2006.201.09:36:20.37#ibcon#end of sib2, iclass 19, count 2 2006.201.09:36:20.37#ibcon#*mode == 0, iclass 19, count 2 2006.201.09:36:20.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.09:36:20.37#ibcon#[27=AT06-04\r\n] 2006.201.09:36:20.37#ibcon#*before write, iclass 19, count 2 2006.201.09:36:20.37#ibcon#enter sib2, iclass 19, count 2 2006.201.09:36:20.37#ibcon#flushed, iclass 19, count 2 2006.201.09:36:20.37#ibcon#about to write, iclass 19, count 2 2006.201.09:36:20.37#ibcon#wrote, iclass 19, count 2 2006.201.09:36:20.37#ibcon#about to read 3, iclass 19, count 2 2006.201.09:36:20.40#ibcon#read 3, iclass 19, count 2 2006.201.09:36:20.40#ibcon#about to read 4, iclass 19, count 2 2006.201.09:36:20.40#ibcon#read 4, iclass 19, count 2 2006.201.09:36:20.40#ibcon#about to read 5, iclass 19, count 2 2006.201.09:36:20.40#ibcon#read 5, iclass 19, count 2 2006.201.09:36:20.40#ibcon#about to read 6, iclass 19, count 2 2006.201.09:36:20.40#ibcon#read 6, iclass 19, count 2 2006.201.09:36:20.40#ibcon#end of sib2, iclass 19, count 2 2006.201.09:36:20.40#ibcon#*after write, iclass 19, count 2 2006.201.09:36:20.40#ibcon#*before return 0, iclass 19, count 2 2006.201.09:36:20.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:20.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:36:20.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.09:36:20.40#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:20.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:20.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:20.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:20.52#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:36:20.52#ibcon#first serial, iclass 19, count 0 2006.201.09:36:20.52#ibcon#enter sib2, iclass 19, count 0 2006.201.09:36:20.52#ibcon#flushed, iclass 19, count 0 2006.201.09:36:20.52#ibcon#about to write, iclass 19, count 0 2006.201.09:36:20.52#ibcon#wrote, iclass 19, count 0 2006.201.09:36:20.52#ibcon#about to read 3, iclass 19, count 0 2006.201.09:36:20.54#ibcon#read 3, iclass 19, count 0 2006.201.09:36:20.54#ibcon#about to read 4, iclass 19, count 0 2006.201.09:36:20.54#ibcon#read 4, iclass 19, count 0 2006.201.09:36:20.54#ibcon#about to read 5, iclass 19, count 0 2006.201.09:36:20.54#ibcon#read 5, iclass 19, count 0 2006.201.09:36:20.54#ibcon#about to read 6, iclass 19, count 0 2006.201.09:36:20.54#ibcon#read 6, iclass 19, count 0 2006.201.09:36:20.54#ibcon#end of sib2, iclass 19, count 0 2006.201.09:36:20.54#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:36:20.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:36:20.54#ibcon#[27=USB\r\n] 2006.201.09:36:20.54#ibcon#*before write, iclass 19, count 0 2006.201.09:36:20.54#ibcon#enter sib2, iclass 19, count 0 2006.201.09:36:20.54#ibcon#flushed, iclass 19, count 0 2006.201.09:36:20.54#ibcon#about to write, iclass 19, count 0 2006.201.09:36:20.54#ibcon#wrote, iclass 19, count 0 2006.201.09:36:20.54#ibcon#about to read 3, iclass 19, count 0 2006.201.09:36:20.57#ibcon#read 3, iclass 19, count 0 2006.201.09:36:20.57#ibcon#about to read 4, iclass 19, count 0 2006.201.09:36:20.57#ibcon#read 4, iclass 19, count 0 2006.201.09:36:20.57#ibcon#about to read 5, iclass 19, count 0 2006.201.09:36:20.57#ibcon#read 5, iclass 19, count 0 2006.201.09:36:20.57#ibcon#about to read 6, iclass 19, count 0 2006.201.09:36:20.57#ibcon#read 6, iclass 19, count 0 2006.201.09:36:20.57#ibcon#end of sib2, iclass 19, count 0 2006.201.09:36:20.57#ibcon#*after write, iclass 19, count 0 2006.201.09:36:20.57#ibcon#*before return 0, iclass 19, count 0 2006.201.09:36:20.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:20.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:36:20.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:36:20.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:36:20.57$vck44/vblo=7,734.99 2006.201.09:36:20.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.09:36:20.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.09:36:20.57#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:20.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:20.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:20.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:20.57#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:36:20.57#ibcon#first serial, iclass 21, count 0 2006.201.09:36:20.57#ibcon#enter sib2, iclass 21, count 0 2006.201.09:36:20.57#ibcon#flushed, iclass 21, count 0 2006.201.09:36:20.57#ibcon#about to write, iclass 21, count 0 2006.201.09:36:20.57#ibcon#wrote, iclass 21, count 0 2006.201.09:36:20.57#ibcon#about to read 3, iclass 21, count 0 2006.201.09:36:20.59#ibcon#read 3, iclass 21, count 0 2006.201.09:36:20.59#ibcon#about to read 4, iclass 21, count 0 2006.201.09:36:20.59#ibcon#read 4, iclass 21, count 0 2006.201.09:36:20.59#ibcon#about to read 5, iclass 21, count 0 2006.201.09:36:20.59#ibcon#read 5, iclass 21, count 0 2006.201.09:36:20.59#ibcon#about to read 6, iclass 21, count 0 2006.201.09:36:20.59#ibcon#read 6, iclass 21, count 0 2006.201.09:36:20.59#ibcon#end of sib2, iclass 21, count 0 2006.201.09:36:20.59#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:36:20.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:36:20.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:36:20.59#ibcon#*before write, iclass 21, count 0 2006.201.09:36:20.59#ibcon#enter sib2, iclass 21, count 0 2006.201.09:36:20.59#ibcon#flushed, iclass 21, count 0 2006.201.09:36:20.59#ibcon#about to write, iclass 21, count 0 2006.201.09:36:20.59#ibcon#wrote, iclass 21, count 0 2006.201.09:36:20.59#ibcon#about to read 3, iclass 21, count 0 2006.201.09:36:20.63#ibcon#read 3, iclass 21, count 0 2006.201.09:36:20.63#ibcon#about to read 4, iclass 21, count 0 2006.201.09:36:20.63#ibcon#read 4, iclass 21, count 0 2006.201.09:36:20.63#ibcon#about to read 5, iclass 21, count 0 2006.201.09:36:20.63#ibcon#read 5, iclass 21, count 0 2006.201.09:36:20.63#ibcon#about to read 6, iclass 21, count 0 2006.201.09:36:20.63#ibcon#read 6, iclass 21, count 0 2006.201.09:36:20.63#ibcon#end of sib2, iclass 21, count 0 2006.201.09:36:20.63#ibcon#*after write, iclass 21, count 0 2006.201.09:36:20.63#ibcon#*before return 0, iclass 21, count 0 2006.201.09:36:20.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:20.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:36:20.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:36:20.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:36:20.63$vck44/vb=7,4 2006.201.09:36:20.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.09:36:20.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.09:36:20.63#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:20.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:20.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:20.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:20.69#ibcon#enter wrdev, iclass 23, count 2 2006.201.09:36:20.69#ibcon#first serial, iclass 23, count 2 2006.201.09:36:20.69#ibcon#enter sib2, iclass 23, count 2 2006.201.09:36:20.69#ibcon#flushed, iclass 23, count 2 2006.201.09:36:20.69#ibcon#about to write, iclass 23, count 2 2006.201.09:36:20.69#ibcon#wrote, iclass 23, count 2 2006.201.09:36:20.69#ibcon#about to read 3, iclass 23, count 2 2006.201.09:36:20.71#ibcon#read 3, iclass 23, count 2 2006.201.09:36:20.71#ibcon#about to read 4, iclass 23, count 2 2006.201.09:36:20.71#ibcon#read 4, iclass 23, count 2 2006.201.09:36:20.71#ibcon#about to read 5, iclass 23, count 2 2006.201.09:36:20.71#ibcon#read 5, iclass 23, count 2 2006.201.09:36:20.71#ibcon#about to read 6, iclass 23, count 2 2006.201.09:36:20.71#ibcon#read 6, iclass 23, count 2 2006.201.09:36:20.71#ibcon#end of sib2, iclass 23, count 2 2006.201.09:36:20.71#ibcon#*mode == 0, iclass 23, count 2 2006.201.09:36:20.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.09:36:20.71#ibcon#[27=AT07-04\r\n] 2006.201.09:36:20.71#ibcon#*before write, iclass 23, count 2 2006.201.09:36:20.71#ibcon#enter sib2, iclass 23, count 2 2006.201.09:36:20.71#ibcon#flushed, iclass 23, count 2 2006.201.09:36:20.71#ibcon#about to write, iclass 23, count 2 2006.201.09:36:20.71#ibcon#wrote, iclass 23, count 2 2006.201.09:36:20.71#ibcon#about to read 3, iclass 23, count 2 2006.201.09:36:20.74#ibcon#read 3, iclass 23, count 2 2006.201.09:36:20.74#ibcon#about to read 4, iclass 23, count 2 2006.201.09:36:20.74#ibcon#read 4, iclass 23, count 2 2006.201.09:36:20.74#ibcon#about to read 5, iclass 23, count 2 2006.201.09:36:20.74#ibcon#read 5, iclass 23, count 2 2006.201.09:36:20.74#ibcon#about to read 6, iclass 23, count 2 2006.201.09:36:20.74#ibcon#read 6, iclass 23, count 2 2006.201.09:36:20.74#ibcon#end of sib2, iclass 23, count 2 2006.201.09:36:20.74#ibcon#*after write, iclass 23, count 2 2006.201.09:36:20.74#ibcon#*before return 0, iclass 23, count 2 2006.201.09:36:20.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:20.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:36:20.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.09:36:20.74#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:20.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:20.83#abcon#<5=/05 2.4 4.4 22.54 921003.9\r\n> 2006.201.09:36:20.85#abcon#{5=INTERFACE CLEAR} 2006.201.09:36:20.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:20.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:20.86#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:36:20.86#ibcon#first serial, iclass 23, count 0 2006.201.09:36:20.86#ibcon#enter sib2, iclass 23, count 0 2006.201.09:36:20.86#ibcon#flushed, iclass 23, count 0 2006.201.09:36:20.86#ibcon#about to write, iclass 23, count 0 2006.201.09:36:20.86#ibcon#wrote, iclass 23, count 0 2006.201.09:36:20.86#ibcon#about to read 3, iclass 23, count 0 2006.201.09:36:20.88#ibcon#read 3, iclass 23, count 0 2006.201.09:36:20.88#ibcon#about to read 4, iclass 23, count 0 2006.201.09:36:20.88#ibcon#read 4, iclass 23, count 0 2006.201.09:36:20.88#ibcon#about to read 5, iclass 23, count 0 2006.201.09:36:20.88#ibcon#read 5, iclass 23, count 0 2006.201.09:36:20.88#ibcon#about to read 6, iclass 23, count 0 2006.201.09:36:20.88#ibcon#read 6, iclass 23, count 0 2006.201.09:36:20.88#ibcon#end of sib2, iclass 23, count 0 2006.201.09:36:20.88#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:36:20.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:36:20.88#ibcon#[27=USB\r\n] 2006.201.09:36:20.88#ibcon#*before write, iclass 23, count 0 2006.201.09:36:20.88#ibcon#enter sib2, iclass 23, count 0 2006.201.09:36:20.88#ibcon#flushed, iclass 23, count 0 2006.201.09:36:20.88#ibcon#about to write, iclass 23, count 0 2006.201.09:36:20.88#ibcon#wrote, iclass 23, count 0 2006.201.09:36:20.88#ibcon#about to read 3, iclass 23, count 0 2006.201.09:36:20.91#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:36:20.92#ibcon#read 3, iclass 23, count 0 2006.201.09:36:20.92#ibcon#about to read 4, iclass 23, count 0 2006.201.09:36:20.92#ibcon#read 4, iclass 23, count 0 2006.201.09:36:20.92#ibcon#about to read 5, iclass 23, count 0 2006.201.09:36:20.92#ibcon#read 5, iclass 23, count 0 2006.201.09:36:20.92#ibcon#about to read 6, iclass 23, count 0 2006.201.09:36:20.92#ibcon#read 6, iclass 23, count 0 2006.201.09:36:20.92#ibcon#end of sib2, iclass 23, count 0 2006.201.09:36:20.92#ibcon#*after write, iclass 23, count 0 2006.201.09:36:20.92#ibcon#*before return 0, iclass 23, count 0 2006.201.09:36:20.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:20.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:36:20.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:36:20.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:36:20.92$vck44/vblo=8,744.99 2006.201.09:36:20.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.09:36:20.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.09:36:20.92#ibcon#ireg 17 cls_cnt 0 2006.201.09:36:20.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:20.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:20.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:20.92#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:36:20.92#ibcon#first serial, iclass 29, count 0 2006.201.09:36:20.92#ibcon#enter sib2, iclass 29, count 0 2006.201.09:36:20.92#ibcon#flushed, iclass 29, count 0 2006.201.09:36:20.92#ibcon#about to write, iclass 29, count 0 2006.201.09:36:20.92#ibcon#wrote, iclass 29, count 0 2006.201.09:36:20.92#ibcon#about to read 3, iclass 29, count 0 2006.201.09:36:20.94#ibcon#read 3, iclass 29, count 0 2006.201.09:36:20.94#ibcon#about to read 4, iclass 29, count 0 2006.201.09:36:20.94#ibcon#read 4, iclass 29, count 0 2006.201.09:36:20.94#ibcon#about to read 5, iclass 29, count 0 2006.201.09:36:20.94#ibcon#read 5, iclass 29, count 0 2006.201.09:36:20.94#ibcon#about to read 6, iclass 29, count 0 2006.201.09:36:20.94#ibcon#read 6, iclass 29, count 0 2006.201.09:36:20.94#ibcon#end of sib2, iclass 29, count 0 2006.201.09:36:20.94#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:36:20.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:36:20.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:36:20.94#ibcon#*before write, iclass 29, count 0 2006.201.09:36:20.94#ibcon#enter sib2, iclass 29, count 0 2006.201.09:36:20.94#ibcon#flushed, iclass 29, count 0 2006.201.09:36:20.94#ibcon#about to write, iclass 29, count 0 2006.201.09:36:20.94#ibcon#wrote, iclass 29, count 0 2006.201.09:36:20.94#ibcon#about to read 3, iclass 29, count 0 2006.201.09:36:20.98#ibcon#read 3, iclass 29, count 0 2006.201.09:36:20.98#ibcon#about to read 4, iclass 29, count 0 2006.201.09:36:20.98#ibcon#read 4, iclass 29, count 0 2006.201.09:36:20.98#ibcon#about to read 5, iclass 29, count 0 2006.201.09:36:20.98#ibcon#read 5, iclass 29, count 0 2006.201.09:36:20.98#ibcon#about to read 6, iclass 29, count 0 2006.201.09:36:20.98#ibcon#read 6, iclass 29, count 0 2006.201.09:36:20.98#ibcon#end of sib2, iclass 29, count 0 2006.201.09:36:20.98#ibcon#*after write, iclass 29, count 0 2006.201.09:36:20.98#ibcon#*before return 0, iclass 29, count 0 2006.201.09:36:20.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:20.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:36:20.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:36:20.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:36:20.98$vck44/vb=8,4 2006.201.09:36:20.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.09:36:20.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.09:36:20.98#ibcon#ireg 11 cls_cnt 2 2006.201.09:36:20.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:21.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:21.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:21.04#ibcon#enter wrdev, iclass 31, count 2 2006.201.09:36:21.04#ibcon#first serial, iclass 31, count 2 2006.201.09:36:21.04#ibcon#enter sib2, iclass 31, count 2 2006.201.09:36:21.04#ibcon#flushed, iclass 31, count 2 2006.201.09:36:21.04#ibcon#about to write, iclass 31, count 2 2006.201.09:36:21.04#ibcon#wrote, iclass 31, count 2 2006.201.09:36:21.04#ibcon#about to read 3, iclass 31, count 2 2006.201.09:36:21.06#ibcon#read 3, iclass 31, count 2 2006.201.09:36:21.06#ibcon#about to read 4, iclass 31, count 2 2006.201.09:36:21.06#ibcon#read 4, iclass 31, count 2 2006.201.09:36:21.06#ibcon#about to read 5, iclass 31, count 2 2006.201.09:36:21.06#ibcon#read 5, iclass 31, count 2 2006.201.09:36:21.06#ibcon#about to read 6, iclass 31, count 2 2006.201.09:36:21.06#ibcon#read 6, iclass 31, count 2 2006.201.09:36:21.06#ibcon#end of sib2, iclass 31, count 2 2006.201.09:36:21.06#ibcon#*mode == 0, iclass 31, count 2 2006.201.09:36:21.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.09:36:21.06#ibcon#[27=AT08-04\r\n] 2006.201.09:36:21.06#ibcon#*before write, iclass 31, count 2 2006.201.09:36:21.06#ibcon#enter sib2, iclass 31, count 2 2006.201.09:36:21.06#ibcon#flushed, iclass 31, count 2 2006.201.09:36:21.06#ibcon#about to write, iclass 31, count 2 2006.201.09:36:21.06#ibcon#wrote, iclass 31, count 2 2006.201.09:36:21.06#ibcon#about to read 3, iclass 31, count 2 2006.201.09:36:21.09#ibcon#read 3, iclass 31, count 2 2006.201.09:36:21.09#ibcon#about to read 4, iclass 31, count 2 2006.201.09:36:21.09#ibcon#read 4, iclass 31, count 2 2006.201.09:36:21.09#ibcon#about to read 5, iclass 31, count 2 2006.201.09:36:21.09#ibcon#read 5, iclass 31, count 2 2006.201.09:36:21.09#ibcon#about to read 6, iclass 31, count 2 2006.201.09:36:21.09#ibcon#read 6, iclass 31, count 2 2006.201.09:36:21.09#ibcon#end of sib2, iclass 31, count 2 2006.201.09:36:21.09#ibcon#*after write, iclass 31, count 2 2006.201.09:36:21.09#ibcon#*before return 0, iclass 31, count 2 2006.201.09:36:21.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:21.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:36:21.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.09:36:21.09#ibcon#ireg 7 cls_cnt 0 2006.201.09:36:21.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:21.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:21.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:21.21#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:36:21.21#ibcon#first serial, iclass 31, count 0 2006.201.09:36:21.21#ibcon#enter sib2, iclass 31, count 0 2006.201.09:36:21.21#ibcon#flushed, iclass 31, count 0 2006.201.09:36:21.21#ibcon#about to write, iclass 31, count 0 2006.201.09:36:21.21#ibcon#wrote, iclass 31, count 0 2006.201.09:36:21.21#ibcon#about to read 3, iclass 31, count 0 2006.201.09:36:21.23#ibcon#read 3, iclass 31, count 0 2006.201.09:36:21.23#ibcon#about to read 4, iclass 31, count 0 2006.201.09:36:21.23#ibcon#read 4, iclass 31, count 0 2006.201.09:36:21.23#ibcon#about to read 5, iclass 31, count 0 2006.201.09:36:21.23#ibcon#read 5, iclass 31, count 0 2006.201.09:36:21.23#ibcon#about to read 6, iclass 31, count 0 2006.201.09:36:21.23#ibcon#read 6, iclass 31, count 0 2006.201.09:36:21.23#ibcon#end of sib2, iclass 31, count 0 2006.201.09:36:21.23#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:36:21.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:36:21.23#ibcon#[27=USB\r\n] 2006.201.09:36:21.23#ibcon#*before write, iclass 31, count 0 2006.201.09:36:21.23#ibcon#enter sib2, iclass 31, count 0 2006.201.09:36:21.23#ibcon#flushed, iclass 31, count 0 2006.201.09:36:21.23#ibcon#about to write, iclass 31, count 0 2006.201.09:36:21.23#ibcon#wrote, iclass 31, count 0 2006.201.09:36:21.23#ibcon#about to read 3, iclass 31, count 0 2006.201.09:36:21.26#ibcon#read 3, iclass 31, count 0 2006.201.09:36:21.26#ibcon#about to read 4, iclass 31, count 0 2006.201.09:36:21.26#ibcon#read 4, iclass 31, count 0 2006.201.09:36:21.26#ibcon#about to read 5, iclass 31, count 0 2006.201.09:36:21.26#ibcon#read 5, iclass 31, count 0 2006.201.09:36:21.26#ibcon#about to read 6, iclass 31, count 0 2006.201.09:36:21.26#ibcon#read 6, iclass 31, count 0 2006.201.09:36:21.26#ibcon#end of sib2, iclass 31, count 0 2006.201.09:36:21.26#ibcon#*after write, iclass 31, count 0 2006.201.09:36:21.26#ibcon#*before return 0, iclass 31, count 0 2006.201.09:36:21.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:21.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:36:21.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:36:21.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:36:21.26$vck44/vabw=wide 2006.201.09:36:21.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.09:36:21.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.09:36:21.26#ibcon#ireg 8 cls_cnt 0 2006.201.09:36:21.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:21.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:21.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:21.26#ibcon#enter wrdev, iclass 33, count 0 2006.201.09:36:21.26#ibcon#first serial, iclass 33, count 0 2006.201.09:36:21.26#ibcon#enter sib2, iclass 33, count 0 2006.201.09:36:21.26#ibcon#flushed, iclass 33, count 0 2006.201.09:36:21.26#ibcon#about to write, iclass 33, count 0 2006.201.09:36:21.26#ibcon#wrote, iclass 33, count 0 2006.201.09:36:21.26#ibcon#about to read 3, iclass 33, count 0 2006.201.09:36:21.28#ibcon#read 3, iclass 33, count 0 2006.201.09:36:21.28#ibcon#about to read 4, iclass 33, count 0 2006.201.09:36:21.28#ibcon#read 4, iclass 33, count 0 2006.201.09:36:21.28#ibcon#about to read 5, iclass 33, count 0 2006.201.09:36:21.28#ibcon#read 5, iclass 33, count 0 2006.201.09:36:21.28#ibcon#about to read 6, iclass 33, count 0 2006.201.09:36:21.28#ibcon#read 6, iclass 33, count 0 2006.201.09:36:21.28#ibcon#end of sib2, iclass 33, count 0 2006.201.09:36:21.28#ibcon#*mode == 0, iclass 33, count 0 2006.201.09:36:21.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.09:36:21.28#ibcon#[25=BW32\r\n] 2006.201.09:36:21.28#ibcon#*before write, iclass 33, count 0 2006.201.09:36:21.28#ibcon#enter sib2, iclass 33, count 0 2006.201.09:36:21.28#ibcon#flushed, iclass 33, count 0 2006.201.09:36:21.28#ibcon#about to write, iclass 33, count 0 2006.201.09:36:21.28#ibcon#wrote, iclass 33, count 0 2006.201.09:36:21.28#ibcon#about to read 3, iclass 33, count 0 2006.201.09:36:21.31#ibcon#read 3, iclass 33, count 0 2006.201.09:36:21.31#ibcon#about to read 4, iclass 33, count 0 2006.201.09:36:21.31#ibcon#read 4, iclass 33, count 0 2006.201.09:36:21.31#ibcon#about to read 5, iclass 33, count 0 2006.201.09:36:21.31#ibcon#read 5, iclass 33, count 0 2006.201.09:36:21.31#ibcon#about to read 6, iclass 33, count 0 2006.201.09:36:21.31#ibcon#read 6, iclass 33, count 0 2006.201.09:36:21.31#ibcon#end of sib2, iclass 33, count 0 2006.201.09:36:21.31#ibcon#*after write, iclass 33, count 0 2006.201.09:36:21.31#ibcon#*before return 0, iclass 33, count 0 2006.201.09:36:21.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:21.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:36:21.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.09:36:21.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.09:36:21.31$vck44/vbbw=wide 2006.201.09:36:21.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.09:36:21.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.09:36:21.31#ibcon#ireg 8 cls_cnt 0 2006.201.09:36:21.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:36:21.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:36:21.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:36:21.38#ibcon#enter wrdev, iclass 35, count 0 2006.201.09:36:21.38#ibcon#first serial, iclass 35, count 0 2006.201.09:36:21.38#ibcon#enter sib2, iclass 35, count 0 2006.201.09:36:21.38#ibcon#flushed, iclass 35, count 0 2006.201.09:36:21.38#ibcon#about to write, iclass 35, count 0 2006.201.09:36:21.38#ibcon#wrote, iclass 35, count 0 2006.201.09:36:21.38#ibcon#about to read 3, iclass 35, count 0 2006.201.09:36:21.40#ibcon#read 3, iclass 35, count 0 2006.201.09:36:21.40#ibcon#about to read 4, iclass 35, count 0 2006.201.09:36:21.40#ibcon#read 4, iclass 35, count 0 2006.201.09:36:21.40#ibcon#about to read 5, iclass 35, count 0 2006.201.09:36:21.40#ibcon#read 5, iclass 35, count 0 2006.201.09:36:21.40#ibcon#about to read 6, iclass 35, count 0 2006.201.09:36:21.40#ibcon#read 6, iclass 35, count 0 2006.201.09:36:21.40#ibcon#end of sib2, iclass 35, count 0 2006.201.09:36:21.40#ibcon#*mode == 0, iclass 35, count 0 2006.201.09:36:21.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.09:36:21.40#ibcon#[27=BW32\r\n] 2006.201.09:36:21.40#ibcon#*before write, iclass 35, count 0 2006.201.09:36:21.40#ibcon#enter sib2, iclass 35, count 0 2006.201.09:36:21.40#ibcon#flushed, iclass 35, count 0 2006.201.09:36:21.40#ibcon#about to write, iclass 35, count 0 2006.201.09:36:21.40#ibcon#wrote, iclass 35, count 0 2006.201.09:36:21.40#ibcon#about to read 3, iclass 35, count 0 2006.201.09:36:21.43#ibcon#read 3, iclass 35, count 0 2006.201.09:36:21.43#ibcon#about to read 4, iclass 35, count 0 2006.201.09:36:21.43#ibcon#read 4, iclass 35, count 0 2006.201.09:36:21.43#ibcon#about to read 5, iclass 35, count 0 2006.201.09:36:21.43#ibcon#read 5, iclass 35, count 0 2006.201.09:36:21.43#ibcon#about to read 6, iclass 35, count 0 2006.201.09:36:21.43#ibcon#read 6, iclass 35, count 0 2006.201.09:36:21.43#ibcon#end of sib2, iclass 35, count 0 2006.201.09:36:21.43#ibcon#*after write, iclass 35, count 0 2006.201.09:36:21.43#ibcon#*before return 0, iclass 35, count 0 2006.201.09:36:21.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:36:21.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.09:36:21.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.09:36:21.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.09:36:21.43$setupk4/ifdk4 2006.201.09:36:21.43$ifdk4/lo= 2006.201.09:36:21.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:36:21.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:36:21.43$ifdk4/patch= 2006.201.09:36:21.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:36:21.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:36:21.43$setupk4/!*+20s 2006.201.09:36:31.00#abcon#<5=/05 2.4 4.4 22.54 931003.8\r\n> 2006.201.09:36:31.02#abcon#{5=INTERFACE CLEAR} 2006.201.09:36:31.08#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:36:32.14#trakl#Source acquired 2006.201.09:36:32.14#flagr#flagr/antenna,acquired 2006.201.09:36:35.89$setupk4/"tpicd 2006.201.09:36:35.89$setupk4/echo=off 2006.201.09:36:35.89$setupk4/xlog=off 2006.201.09:36:35.89:!2006.201.09:36:47 2006.201.09:36:47.00:preob 2006.201.09:36:48.14/onsource/TRACKING 2006.201.09:36:48.14:!2006.201.09:36:57 2006.201.09:36:57.00:"tape 2006.201.09:36:57.00:"st=record 2006.201.09:36:57.00:data_valid=on 2006.201.09:36:57.00:midob 2006.201.09:36:57.14/onsource/TRACKING 2006.201.09:36:57.14/wx/22.53,1003.8,92 2006.201.09:36:57.20/cable/+6.4659E-03 2006.201.09:36:58.29/va/01,08,usb,yes,28,30 2006.201.09:36:58.29/va/02,07,usb,yes,30,31 2006.201.09:36:58.29/va/03,08,usb,yes,27,28 2006.201.09:36:58.29/va/04,07,usb,yes,31,33 2006.201.09:36:58.29/va/05,04,usb,yes,27,28 2006.201.09:36:58.29/va/06,05,usb,yes,28,27 2006.201.09:36:58.29/va/07,05,usb,yes,27,28 2006.201.09:36:58.29/va/08,04,usb,yes,27,32 2006.201.09:36:58.52/valo/01,524.99,yes,locked 2006.201.09:36:58.52/valo/02,534.99,yes,locked 2006.201.09:36:58.52/valo/03,564.99,yes,locked 2006.201.09:36:58.52/valo/04,624.99,yes,locked 2006.201.09:36:58.52/valo/05,734.99,yes,locked 2006.201.09:36:58.52/valo/06,814.99,yes,locked 2006.201.09:36:58.52/valo/07,864.99,yes,locked 2006.201.09:36:58.52/valo/08,884.99,yes,locked 2006.201.09:36:59.61/vb/01,04,usb,yes,28,26 2006.201.09:36:59.61/vb/02,05,usb,yes,27,27 2006.201.09:36:59.61/vb/03,04,usb,yes,28,30 2006.201.09:36:59.61/vb/04,05,usb,yes,28,27 2006.201.09:36:59.61/vb/05,04,usb,yes,25,27 2006.201.09:36:59.61/vb/06,04,usb,yes,29,25 2006.201.09:36:59.61/vb/07,04,usb,yes,29,29 2006.201.09:36:59.61/vb/08,04,usb,yes,26,30 2006.201.09:36:59.85/vblo/01,629.99,yes,locked 2006.201.09:36:59.85/vblo/02,634.99,yes,locked 2006.201.09:36:59.85/vblo/03,649.99,yes,locked 2006.201.09:36:59.85/vblo/04,679.99,yes,locked 2006.201.09:36:59.85/vblo/05,709.99,yes,locked 2006.201.09:36:59.85/vblo/06,719.99,yes,locked 2006.201.09:36:59.85/vblo/07,734.99,yes,locked 2006.201.09:36:59.85/vblo/08,744.99,yes,locked 2006.201.09:37:00.00/vabw/8 2006.201.09:37:00.15/vbbw/8 2006.201.09:37:00.24/xfe/off,on,15.0 2006.201.09:37:00.61/ifatt/23,28,28,28 2006.201.09:37:01.06/fmout-gps/S +4.57E-07 2006.201.09:37:01.13:!2006.201.09:49:17 2006.201.09:49:17.00:data_valid=off 2006.201.09:49:17.00:"et 2006.201.09:49:17.00:!+3s 2006.201.09:49:20.02:"tape 2006.201.09:49:20.02:postob 2006.201.09:49:20.18/cable/+6.4665E-03 2006.201.09:49:20.21/wx/22.38,1003.7,94 2006.201.09:49:20.29/fmout-gps/S +4.58E-07 2006.201.09:49:20.29:scan_name=201-0950,jd0607,290 2006.201.09:49:20.29:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.09:49:21.14#flagr#flagr/antenna,new-source 2006.201.09:49:21.14:checkk5 2006.201.09:49:21.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:49:21.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:49:22.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:49:22.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:49:23.35/chk_obsdata//k5ts1/T2010936??a.dat file size is correct (nominal:2960MB, actual:2956MB). 2006.201.09:49:24.02/chk_obsdata//k5ts2/T2010936??b.dat file size is correct (nominal:2960MB, actual:2956MB). 2006.201.09:49:24.69/chk_obsdata//k5ts3/T2010936??c.dat file size is correct (nominal:2960MB, actual:2956MB). 2006.201.09:49:25.37/chk_obsdata//k5ts4/T2010936??d.dat file size is correct (nominal:2960MB, actual:2956MB). 2006.201.09:49:26.06/k5log//k5ts1_log_newline 2006.201.09:49:26.74/k5log//k5ts2_log_newline 2006.201.09:49:27.42/k5log//k5ts3_log_newline 2006.201.09:49:28.12/k5log//k5ts4_log_newline 2006.201.09:49:28.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:49:28.15:setupk4=1 2006.201.09:49:28.15$setupk4/echo=on 2006.201.09:49:28.15$setupk4/pcalon 2006.201.09:49:28.15$pcalon/"no phase cal control is implemented here 2006.201.09:49:28.15$setupk4/"tpicd=stop 2006.201.09:49:28.15$setupk4/"rec=synch_on 2006.201.09:49:28.15$setupk4/"rec_mode=128 2006.201.09:49:28.15$setupk4/!* 2006.201.09:49:28.15$setupk4/recpk4 2006.201.09:49:28.15$recpk4/recpatch= 2006.201.09:49:28.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:49:28.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:49:28.15$setupk4/vck44 2006.201.09:49:28.15$vck44/valo=1,524.99 2006.201.09:49:28.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.09:49:28.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.09:49:28.15#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:28.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:28.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:28.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:28.15#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:49:28.15#ibcon#first serial, iclass 24, count 0 2006.201.09:49:28.15#ibcon#enter sib2, iclass 24, count 0 2006.201.09:49:28.15#ibcon#flushed, iclass 24, count 0 2006.201.09:49:28.15#ibcon#about to write, iclass 24, count 0 2006.201.09:49:28.15#ibcon#wrote, iclass 24, count 0 2006.201.09:49:28.15#ibcon#about to read 3, iclass 24, count 0 2006.201.09:49:28.19#ibcon#read 3, iclass 24, count 0 2006.201.09:49:28.19#ibcon#about to read 4, iclass 24, count 0 2006.201.09:49:28.19#ibcon#read 4, iclass 24, count 0 2006.201.09:49:28.19#ibcon#about to read 5, iclass 24, count 0 2006.201.09:49:28.19#ibcon#read 5, iclass 24, count 0 2006.201.09:49:28.19#ibcon#about to read 6, iclass 24, count 0 2006.201.09:49:28.19#ibcon#read 6, iclass 24, count 0 2006.201.09:49:28.19#ibcon#end of sib2, iclass 24, count 0 2006.201.09:49:28.19#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:49:28.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:49:28.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:49:28.19#ibcon#*before write, iclass 24, count 0 2006.201.09:49:28.19#ibcon#enter sib2, iclass 24, count 0 2006.201.09:49:28.19#ibcon#flushed, iclass 24, count 0 2006.201.09:49:28.19#ibcon#about to write, iclass 24, count 0 2006.201.09:49:28.19#ibcon#wrote, iclass 24, count 0 2006.201.09:49:28.19#ibcon#about to read 3, iclass 24, count 0 2006.201.09:49:28.24#ibcon#read 3, iclass 24, count 0 2006.201.09:49:28.24#ibcon#about to read 4, iclass 24, count 0 2006.201.09:49:28.24#ibcon#read 4, iclass 24, count 0 2006.201.09:49:28.24#ibcon#about to read 5, iclass 24, count 0 2006.201.09:49:28.24#ibcon#read 5, iclass 24, count 0 2006.201.09:49:28.24#ibcon#about to read 6, iclass 24, count 0 2006.201.09:49:28.24#ibcon#read 6, iclass 24, count 0 2006.201.09:49:28.24#ibcon#end of sib2, iclass 24, count 0 2006.201.09:49:28.24#ibcon#*after write, iclass 24, count 0 2006.201.09:49:28.24#ibcon#*before return 0, iclass 24, count 0 2006.201.09:49:28.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:28.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:28.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:49:28.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:49:28.24$vck44/va=1,8 2006.201.09:49:28.24#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.09:49:28.24#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.09:49:28.24#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:28.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:28.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:28.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:28.24#ibcon#enter wrdev, iclass 26, count 2 2006.201.09:49:28.24#ibcon#first serial, iclass 26, count 2 2006.201.09:49:28.24#ibcon#enter sib2, iclass 26, count 2 2006.201.09:49:28.24#ibcon#flushed, iclass 26, count 2 2006.201.09:49:28.24#ibcon#about to write, iclass 26, count 2 2006.201.09:49:28.24#ibcon#wrote, iclass 26, count 2 2006.201.09:49:28.24#ibcon#about to read 3, iclass 26, count 2 2006.201.09:49:28.26#ibcon#read 3, iclass 26, count 2 2006.201.09:49:28.26#ibcon#about to read 4, iclass 26, count 2 2006.201.09:49:28.26#ibcon#read 4, iclass 26, count 2 2006.201.09:49:28.26#ibcon#about to read 5, iclass 26, count 2 2006.201.09:49:28.26#ibcon#read 5, iclass 26, count 2 2006.201.09:49:28.26#ibcon#about to read 6, iclass 26, count 2 2006.201.09:49:28.26#ibcon#read 6, iclass 26, count 2 2006.201.09:49:28.26#ibcon#end of sib2, iclass 26, count 2 2006.201.09:49:28.26#ibcon#*mode == 0, iclass 26, count 2 2006.201.09:49:28.26#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.09:49:28.26#ibcon#[25=AT01-08\r\n] 2006.201.09:49:28.26#ibcon#*before write, iclass 26, count 2 2006.201.09:49:28.26#ibcon#enter sib2, iclass 26, count 2 2006.201.09:49:28.26#ibcon#flushed, iclass 26, count 2 2006.201.09:49:28.26#ibcon#about to write, iclass 26, count 2 2006.201.09:49:28.26#ibcon#wrote, iclass 26, count 2 2006.201.09:49:28.26#ibcon#about to read 3, iclass 26, count 2 2006.201.09:49:28.30#ibcon#read 3, iclass 26, count 2 2006.201.09:49:28.30#ibcon#about to read 4, iclass 26, count 2 2006.201.09:49:28.30#ibcon#read 4, iclass 26, count 2 2006.201.09:49:28.30#ibcon#about to read 5, iclass 26, count 2 2006.201.09:49:28.30#ibcon#read 5, iclass 26, count 2 2006.201.09:49:28.30#ibcon#about to read 6, iclass 26, count 2 2006.201.09:49:28.30#ibcon#read 6, iclass 26, count 2 2006.201.09:49:28.30#ibcon#end of sib2, iclass 26, count 2 2006.201.09:49:28.30#ibcon#*after write, iclass 26, count 2 2006.201.09:49:28.30#ibcon#*before return 0, iclass 26, count 2 2006.201.09:49:28.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:28.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:28.30#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.09:49:28.30#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:28.30#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:28.42#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:28.42#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:28.42#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:49:28.42#ibcon#first serial, iclass 26, count 0 2006.201.09:49:28.42#ibcon#enter sib2, iclass 26, count 0 2006.201.09:49:28.42#ibcon#flushed, iclass 26, count 0 2006.201.09:49:28.42#ibcon#about to write, iclass 26, count 0 2006.201.09:49:28.42#ibcon#wrote, iclass 26, count 0 2006.201.09:49:28.42#ibcon#about to read 3, iclass 26, count 0 2006.201.09:49:28.44#ibcon#read 3, iclass 26, count 0 2006.201.09:49:28.44#ibcon#about to read 4, iclass 26, count 0 2006.201.09:49:28.44#ibcon#read 4, iclass 26, count 0 2006.201.09:49:28.44#ibcon#about to read 5, iclass 26, count 0 2006.201.09:49:28.44#ibcon#read 5, iclass 26, count 0 2006.201.09:49:28.44#ibcon#about to read 6, iclass 26, count 0 2006.201.09:49:28.44#ibcon#read 6, iclass 26, count 0 2006.201.09:49:28.44#ibcon#end of sib2, iclass 26, count 0 2006.201.09:49:28.44#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:49:28.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:49:28.44#ibcon#[25=USB\r\n] 2006.201.09:49:28.44#ibcon#*before write, iclass 26, count 0 2006.201.09:49:28.44#ibcon#enter sib2, iclass 26, count 0 2006.201.09:49:28.44#ibcon#flushed, iclass 26, count 0 2006.201.09:49:28.44#ibcon#about to write, iclass 26, count 0 2006.201.09:49:28.44#ibcon#wrote, iclass 26, count 0 2006.201.09:49:28.44#ibcon#about to read 3, iclass 26, count 0 2006.201.09:49:28.47#ibcon#read 3, iclass 26, count 0 2006.201.09:49:28.47#ibcon#about to read 4, iclass 26, count 0 2006.201.09:49:28.47#ibcon#read 4, iclass 26, count 0 2006.201.09:49:28.47#ibcon#about to read 5, iclass 26, count 0 2006.201.09:49:28.47#ibcon#read 5, iclass 26, count 0 2006.201.09:49:28.47#ibcon#about to read 6, iclass 26, count 0 2006.201.09:49:28.47#ibcon#read 6, iclass 26, count 0 2006.201.09:49:28.47#ibcon#end of sib2, iclass 26, count 0 2006.201.09:49:28.47#ibcon#*after write, iclass 26, count 0 2006.201.09:49:28.47#ibcon#*before return 0, iclass 26, count 0 2006.201.09:49:28.47#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:28.47#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:28.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:49:28.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:49:28.47$vck44/valo=2,534.99 2006.201.09:49:28.47#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.09:49:28.47#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.09:49:28.47#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:28.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:28.47#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:28.47#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:28.47#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:49:28.47#ibcon#first serial, iclass 28, count 0 2006.201.09:49:28.47#ibcon#enter sib2, iclass 28, count 0 2006.201.09:49:28.47#ibcon#flushed, iclass 28, count 0 2006.201.09:49:28.47#ibcon#about to write, iclass 28, count 0 2006.201.09:49:28.47#ibcon#wrote, iclass 28, count 0 2006.201.09:49:28.47#ibcon#about to read 3, iclass 28, count 0 2006.201.09:49:28.49#ibcon#read 3, iclass 28, count 0 2006.201.09:49:28.49#ibcon#about to read 4, iclass 28, count 0 2006.201.09:49:28.49#ibcon#read 4, iclass 28, count 0 2006.201.09:49:28.49#ibcon#about to read 5, iclass 28, count 0 2006.201.09:49:28.49#ibcon#read 5, iclass 28, count 0 2006.201.09:49:28.49#ibcon#about to read 6, iclass 28, count 0 2006.201.09:49:28.49#ibcon#read 6, iclass 28, count 0 2006.201.09:49:28.49#ibcon#end of sib2, iclass 28, count 0 2006.201.09:49:28.49#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:49:28.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:49:28.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:49:28.49#ibcon#*before write, iclass 28, count 0 2006.201.09:49:28.49#ibcon#enter sib2, iclass 28, count 0 2006.201.09:49:28.49#ibcon#flushed, iclass 28, count 0 2006.201.09:49:28.49#ibcon#about to write, iclass 28, count 0 2006.201.09:49:28.49#ibcon#wrote, iclass 28, count 0 2006.201.09:49:28.49#ibcon#about to read 3, iclass 28, count 0 2006.201.09:49:28.54#ibcon#read 3, iclass 28, count 0 2006.201.09:49:28.54#ibcon#about to read 4, iclass 28, count 0 2006.201.09:49:28.54#ibcon#read 4, iclass 28, count 0 2006.201.09:49:28.54#ibcon#about to read 5, iclass 28, count 0 2006.201.09:49:28.54#ibcon#read 5, iclass 28, count 0 2006.201.09:49:28.54#ibcon#about to read 6, iclass 28, count 0 2006.201.09:49:28.54#ibcon#read 6, iclass 28, count 0 2006.201.09:49:28.54#ibcon#end of sib2, iclass 28, count 0 2006.201.09:49:28.54#ibcon#*after write, iclass 28, count 0 2006.201.09:49:28.54#ibcon#*before return 0, iclass 28, count 0 2006.201.09:49:28.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:28.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:28.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:49:28.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:49:28.54$vck44/va=2,7 2006.201.09:49:28.54#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.09:49:28.54#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.09:49:28.54#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:28.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:28.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:28.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:28.59#ibcon#enter wrdev, iclass 30, count 2 2006.201.09:49:28.59#ibcon#first serial, iclass 30, count 2 2006.201.09:49:28.59#ibcon#enter sib2, iclass 30, count 2 2006.201.09:49:28.59#ibcon#flushed, iclass 30, count 2 2006.201.09:49:28.59#ibcon#about to write, iclass 30, count 2 2006.201.09:49:28.59#ibcon#wrote, iclass 30, count 2 2006.201.09:49:28.59#ibcon#about to read 3, iclass 30, count 2 2006.201.09:49:28.61#ibcon#read 3, iclass 30, count 2 2006.201.09:49:28.61#ibcon#about to read 4, iclass 30, count 2 2006.201.09:49:28.61#ibcon#read 4, iclass 30, count 2 2006.201.09:49:28.61#ibcon#about to read 5, iclass 30, count 2 2006.201.09:49:28.61#ibcon#read 5, iclass 30, count 2 2006.201.09:49:28.61#ibcon#about to read 6, iclass 30, count 2 2006.201.09:49:28.61#ibcon#read 6, iclass 30, count 2 2006.201.09:49:28.61#ibcon#end of sib2, iclass 30, count 2 2006.201.09:49:28.61#ibcon#*mode == 0, iclass 30, count 2 2006.201.09:49:28.61#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.09:49:28.61#ibcon#[25=AT02-07\r\n] 2006.201.09:49:28.61#ibcon#*before write, iclass 30, count 2 2006.201.09:49:28.61#ibcon#enter sib2, iclass 30, count 2 2006.201.09:49:28.61#ibcon#flushed, iclass 30, count 2 2006.201.09:49:28.61#ibcon#about to write, iclass 30, count 2 2006.201.09:49:28.61#ibcon#wrote, iclass 30, count 2 2006.201.09:49:28.61#ibcon#about to read 3, iclass 30, count 2 2006.201.09:49:28.64#ibcon#read 3, iclass 30, count 2 2006.201.09:49:28.64#ibcon#about to read 4, iclass 30, count 2 2006.201.09:49:28.64#ibcon#read 4, iclass 30, count 2 2006.201.09:49:28.64#ibcon#about to read 5, iclass 30, count 2 2006.201.09:49:28.64#ibcon#read 5, iclass 30, count 2 2006.201.09:49:28.64#ibcon#about to read 6, iclass 30, count 2 2006.201.09:49:28.64#ibcon#read 6, iclass 30, count 2 2006.201.09:49:28.64#ibcon#end of sib2, iclass 30, count 2 2006.201.09:49:28.64#ibcon#*after write, iclass 30, count 2 2006.201.09:49:28.64#ibcon#*before return 0, iclass 30, count 2 2006.201.09:49:28.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:28.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:28.64#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.09:49:28.64#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:28.64#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:28.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:28.76#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:28.76#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:49:28.76#ibcon#first serial, iclass 30, count 0 2006.201.09:49:28.76#ibcon#enter sib2, iclass 30, count 0 2006.201.09:49:28.76#ibcon#flushed, iclass 30, count 0 2006.201.09:49:28.76#ibcon#about to write, iclass 30, count 0 2006.201.09:49:28.76#ibcon#wrote, iclass 30, count 0 2006.201.09:49:28.76#ibcon#about to read 3, iclass 30, count 0 2006.201.09:49:28.78#ibcon#read 3, iclass 30, count 0 2006.201.09:49:28.78#ibcon#about to read 4, iclass 30, count 0 2006.201.09:49:28.78#ibcon#read 4, iclass 30, count 0 2006.201.09:49:28.78#ibcon#about to read 5, iclass 30, count 0 2006.201.09:49:28.78#ibcon#read 5, iclass 30, count 0 2006.201.09:49:28.78#ibcon#about to read 6, iclass 30, count 0 2006.201.09:49:28.78#ibcon#read 6, iclass 30, count 0 2006.201.09:49:28.78#ibcon#end of sib2, iclass 30, count 0 2006.201.09:49:28.78#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:49:28.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:49:28.78#ibcon#[25=USB\r\n] 2006.201.09:49:28.78#ibcon#*before write, iclass 30, count 0 2006.201.09:49:28.78#ibcon#enter sib2, iclass 30, count 0 2006.201.09:49:28.78#ibcon#flushed, iclass 30, count 0 2006.201.09:49:28.78#ibcon#about to write, iclass 30, count 0 2006.201.09:49:28.78#ibcon#wrote, iclass 30, count 0 2006.201.09:49:28.78#ibcon#about to read 3, iclass 30, count 0 2006.201.09:49:28.81#ibcon#read 3, iclass 30, count 0 2006.201.09:49:28.81#ibcon#about to read 4, iclass 30, count 0 2006.201.09:49:28.81#ibcon#read 4, iclass 30, count 0 2006.201.09:49:28.81#ibcon#about to read 5, iclass 30, count 0 2006.201.09:49:28.81#ibcon#read 5, iclass 30, count 0 2006.201.09:49:28.81#ibcon#about to read 6, iclass 30, count 0 2006.201.09:49:28.81#ibcon#read 6, iclass 30, count 0 2006.201.09:49:28.81#ibcon#end of sib2, iclass 30, count 0 2006.201.09:49:28.81#ibcon#*after write, iclass 30, count 0 2006.201.09:49:28.81#ibcon#*before return 0, iclass 30, count 0 2006.201.09:49:28.81#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:28.81#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:28.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:49:28.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:49:28.81$vck44/valo=3,564.99 2006.201.09:49:28.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.09:49:28.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.09:49:28.81#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:28.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:28.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:28.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:28.81#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:49:28.81#ibcon#first serial, iclass 32, count 0 2006.201.09:49:28.81#ibcon#enter sib2, iclass 32, count 0 2006.201.09:49:28.81#ibcon#flushed, iclass 32, count 0 2006.201.09:49:28.81#ibcon#about to write, iclass 32, count 0 2006.201.09:49:28.81#ibcon#wrote, iclass 32, count 0 2006.201.09:49:28.81#ibcon#about to read 3, iclass 32, count 0 2006.201.09:49:28.83#ibcon#read 3, iclass 32, count 0 2006.201.09:49:28.83#ibcon#about to read 4, iclass 32, count 0 2006.201.09:49:28.83#ibcon#read 4, iclass 32, count 0 2006.201.09:49:28.83#ibcon#about to read 5, iclass 32, count 0 2006.201.09:49:28.83#ibcon#read 5, iclass 32, count 0 2006.201.09:49:28.83#ibcon#about to read 6, iclass 32, count 0 2006.201.09:49:28.83#ibcon#read 6, iclass 32, count 0 2006.201.09:49:28.83#ibcon#end of sib2, iclass 32, count 0 2006.201.09:49:28.83#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:49:28.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:49:28.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:49:28.83#ibcon#*before write, iclass 32, count 0 2006.201.09:49:28.83#ibcon#enter sib2, iclass 32, count 0 2006.201.09:49:28.83#ibcon#flushed, iclass 32, count 0 2006.201.09:49:28.83#ibcon#about to write, iclass 32, count 0 2006.201.09:49:28.83#ibcon#wrote, iclass 32, count 0 2006.201.09:49:28.83#ibcon#about to read 3, iclass 32, count 0 2006.201.09:49:28.88#ibcon#read 3, iclass 32, count 0 2006.201.09:49:28.88#ibcon#about to read 4, iclass 32, count 0 2006.201.09:49:28.88#ibcon#read 4, iclass 32, count 0 2006.201.09:49:28.88#ibcon#about to read 5, iclass 32, count 0 2006.201.09:49:28.88#ibcon#read 5, iclass 32, count 0 2006.201.09:49:28.88#ibcon#about to read 6, iclass 32, count 0 2006.201.09:49:28.88#ibcon#read 6, iclass 32, count 0 2006.201.09:49:28.88#ibcon#end of sib2, iclass 32, count 0 2006.201.09:49:28.88#ibcon#*after write, iclass 32, count 0 2006.201.09:49:28.88#ibcon#*before return 0, iclass 32, count 0 2006.201.09:49:28.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:28.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:28.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:49:28.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:49:28.88$vck44/va=3,8 2006.201.09:49:28.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.09:49:28.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.09:49:28.88#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:28.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:28.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:28.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:28.93#ibcon#enter wrdev, iclass 34, count 2 2006.201.09:49:28.93#ibcon#first serial, iclass 34, count 2 2006.201.09:49:28.93#ibcon#enter sib2, iclass 34, count 2 2006.201.09:49:28.93#ibcon#flushed, iclass 34, count 2 2006.201.09:49:28.93#ibcon#about to write, iclass 34, count 2 2006.201.09:49:28.93#ibcon#wrote, iclass 34, count 2 2006.201.09:49:28.93#ibcon#about to read 3, iclass 34, count 2 2006.201.09:49:28.95#ibcon#read 3, iclass 34, count 2 2006.201.09:49:28.95#ibcon#about to read 4, iclass 34, count 2 2006.201.09:49:28.95#ibcon#read 4, iclass 34, count 2 2006.201.09:49:28.95#ibcon#about to read 5, iclass 34, count 2 2006.201.09:49:28.95#ibcon#read 5, iclass 34, count 2 2006.201.09:49:28.95#ibcon#about to read 6, iclass 34, count 2 2006.201.09:49:28.95#ibcon#read 6, iclass 34, count 2 2006.201.09:49:28.95#ibcon#end of sib2, iclass 34, count 2 2006.201.09:49:28.95#ibcon#*mode == 0, iclass 34, count 2 2006.201.09:49:28.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.09:49:28.95#ibcon#[25=AT03-08\r\n] 2006.201.09:49:28.95#ibcon#*before write, iclass 34, count 2 2006.201.09:49:28.95#ibcon#enter sib2, iclass 34, count 2 2006.201.09:49:28.95#ibcon#flushed, iclass 34, count 2 2006.201.09:49:28.95#ibcon#about to write, iclass 34, count 2 2006.201.09:49:28.95#ibcon#wrote, iclass 34, count 2 2006.201.09:49:28.95#ibcon#about to read 3, iclass 34, count 2 2006.201.09:49:28.98#ibcon#read 3, iclass 34, count 2 2006.201.09:49:28.98#ibcon#about to read 4, iclass 34, count 2 2006.201.09:49:28.98#ibcon#read 4, iclass 34, count 2 2006.201.09:49:28.98#ibcon#about to read 5, iclass 34, count 2 2006.201.09:49:28.98#ibcon#read 5, iclass 34, count 2 2006.201.09:49:28.98#ibcon#about to read 6, iclass 34, count 2 2006.201.09:49:28.98#ibcon#read 6, iclass 34, count 2 2006.201.09:49:28.98#ibcon#end of sib2, iclass 34, count 2 2006.201.09:49:28.98#ibcon#*after write, iclass 34, count 2 2006.201.09:49:28.98#ibcon#*before return 0, iclass 34, count 2 2006.201.09:49:28.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:28.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:28.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.09:49:28.98#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:28.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:29.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:29.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:29.10#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:49:29.10#ibcon#first serial, iclass 34, count 0 2006.201.09:49:29.10#ibcon#enter sib2, iclass 34, count 0 2006.201.09:49:29.10#ibcon#flushed, iclass 34, count 0 2006.201.09:49:29.10#ibcon#about to write, iclass 34, count 0 2006.201.09:49:29.10#ibcon#wrote, iclass 34, count 0 2006.201.09:49:29.10#ibcon#about to read 3, iclass 34, count 0 2006.201.09:49:29.12#ibcon#read 3, iclass 34, count 0 2006.201.09:49:29.12#ibcon#about to read 4, iclass 34, count 0 2006.201.09:49:29.12#ibcon#read 4, iclass 34, count 0 2006.201.09:49:29.12#ibcon#about to read 5, iclass 34, count 0 2006.201.09:49:29.12#ibcon#read 5, iclass 34, count 0 2006.201.09:49:29.12#ibcon#about to read 6, iclass 34, count 0 2006.201.09:49:29.12#ibcon#read 6, iclass 34, count 0 2006.201.09:49:29.12#ibcon#end of sib2, iclass 34, count 0 2006.201.09:49:29.12#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:49:29.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:49:29.12#ibcon#[25=USB\r\n] 2006.201.09:49:29.12#ibcon#*before write, iclass 34, count 0 2006.201.09:49:29.12#ibcon#enter sib2, iclass 34, count 0 2006.201.09:49:29.12#ibcon#flushed, iclass 34, count 0 2006.201.09:49:29.12#ibcon#about to write, iclass 34, count 0 2006.201.09:49:29.12#ibcon#wrote, iclass 34, count 0 2006.201.09:49:29.12#ibcon#about to read 3, iclass 34, count 0 2006.201.09:49:29.15#ibcon#read 3, iclass 34, count 0 2006.201.09:49:29.15#ibcon#about to read 4, iclass 34, count 0 2006.201.09:49:29.15#ibcon#read 4, iclass 34, count 0 2006.201.09:49:29.15#ibcon#about to read 5, iclass 34, count 0 2006.201.09:49:29.15#ibcon#read 5, iclass 34, count 0 2006.201.09:49:29.15#ibcon#about to read 6, iclass 34, count 0 2006.201.09:49:29.15#ibcon#read 6, iclass 34, count 0 2006.201.09:49:29.15#ibcon#end of sib2, iclass 34, count 0 2006.201.09:49:29.15#ibcon#*after write, iclass 34, count 0 2006.201.09:49:29.15#ibcon#*before return 0, iclass 34, count 0 2006.201.09:49:29.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:29.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:29.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:49:29.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:49:29.15$vck44/valo=4,624.99 2006.201.09:49:29.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.09:49:29.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.09:49:29.15#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:29.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:29.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:29.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:29.15#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:49:29.15#ibcon#first serial, iclass 36, count 0 2006.201.09:49:29.15#ibcon#enter sib2, iclass 36, count 0 2006.201.09:49:29.15#ibcon#flushed, iclass 36, count 0 2006.201.09:49:29.15#ibcon#about to write, iclass 36, count 0 2006.201.09:49:29.15#ibcon#wrote, iclass 36, count 0 2006.201.09:49:29.15#ibcon#about to read 3, iclass 36, count 0 2006.201.09:49:29.17#ibcon#read 3, iclass 36, count 0 2006.201.09:49:29.17#ibcon#about to read 4, iclass 36, count 0 2006.201.09:49:29.17#ibcon#read 4, iclass 36, count 0 2006.201.09:49:29.17#ibcon#about to read 5, iclass 36, count 0 2006.201.09:49:29.17#ibcon#read 5, iclass 36, count 0 2006.201.09:49:29.17#ibcon#about to read 6, iclass 36, count 0 2006.201.09:49:29.17#ibcon#read 6, iclass 36, count 0 2006.201.09:49:29.17#ibcon#end of sib2, iclass 36, count 0 2006.201.09:49:29.17#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:49:29.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:49:29.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:49:29.17#ibcon#*before write, iclass 36, count 0 2006.201.09:49:29.17#ibcon#enter sib2, iclass 36, count 0 2006.201.09:49:29.17#ibcon#flushed, iclass 36, count 0 2006.201.09:49:29.17#ibcon#about to write, iclass 36, count 0 2006.201.09:49:29.17#ibcon#wrote, iclass 36, count 0 2006.201.09:49:29.17#ibcon#about to read 3, iclass 36, count 0 2006.201.09:49:29.21#ibcon#read 3, iclass 36, count 0 2006.201.09:49:29.21#ibcon#about to read 4, iclass 36, count 0 2006.201.09:49:29.21#ibcon#read 4, iclass 36, count 0 2006.201.09:49:29.21#ibcon#about to read 5, iclass 36, count 0 2006.201.09:49:29.21#ibcon#read 5, iclass 36, count 0 2006.201.09:49:29.21#ibcon#about to read 6, iclass 36, count 0 2006.201.09:49:29.21#ibcon#read 6, iclass 36, count 0 2006.201.09:49:29.21#ibcon#end of sib2, iclass 36, count 0 2006.201.09:49:29.21#ibcon#*after write, iclass 36, count 0 2006.201.09:49:29.21#ibcon#*before return 0, iclass 36, count 0 2006.201.09:49:29.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:29.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:29.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:49:29.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:49:29.21$vck44/va=4,7 2006.201.09:49:29.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.09:49:29.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.09:49:29.21#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:29.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:29.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:29.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:29.27#ibcon#enter wrdev, iclass 38, count 2 2006.201.09:49:29.27#ibcon#first serial, iclass 38, count 2 2006.201.09:49:29.27#ibcon#enter sib2, iclass 38, count 2 2006.201.09:49:29.27#ibcon#flushed, iclass 38, count 2 2006.201.09:49:29.27#ibcon#about to write, iclass 38, count 2 2006.201.09:49:29.27#ibcon#wrote, iclass 38, count 2 2006.201.09:49:29.27#ibcon#about to read 3, iclass 38, count 2 2006.201.09:49:29.29#ibcon#read 3, iclass 38, count 2 2006.201.09:49:29.29#ibcon#about to read 4, iclass 38, count 2 2006.201.09:49:29.29#ibcon#read 4, iclass 38, count 2 2006.201.09:49:29.29#ibcon#about to read 5, iclass 38, count 2 2006.201.09:49:29.29#ibcon#read 5, iclass 38, count 2 2006.201.09:49:29.29#ibcon#about to read 6, iclass 38, count 2 2006.201.09:49:29.29#ibcon#read 6, iclass 38, count 2 2006.201.09:49:29.29#ibcon#end of sib2, iclass 38, count 2 2006.201.09:49:29.29#ibcon#*mode == 0, iclass 38, count 2 2006.201.09:49:29.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.09:49:29.29#ibcon#[25=AT04-07\r\n] 2006.201.09:49:29.29#ibcon#*before write, iclass 38, count 2 2006.201.09:49:29.29#ibcon#enter sib2, iclass 38, count 2 2006.201.09:49:29.29#ibcon#flushed, iclass 38, count 2 2006.201.09:49:29.29#ibcon#about to write, iclass 38, count 2 2006.201.09:49:29.29#ibcon#wrote, iclass 38, count 2 2006.201.09:49:29.29#ibcon#about to read 3, iclass 38, count 2 2006.201.09:49:29.32#ibcon#read 3, iclass 38, count 2 2006.201.09:49:29.32#ibcon#about to read 4, iclass 38, count 2 2006.201.09:49:29.32#ibcon#read 4, iclass 38, count 2 2006.201.09:49:29.32#ibcon#about to read 5, iclass 38, count 2 2006.201.09:49:29.32#ibcon#read 5, iclass 38, count 2 2006.201.09:49:29.32#ibcon#about to read 6, iclass 38, count 2 2006.201.09:49:29.32#ibcon#read 6, iclass 38, count 2 2006.201.09:49:29.32#ibcon#end of sib2, iclass 38, count 2 2006.201.09:49:29.32#ibcon#*after write, iclass 38, count 2 2006.201.09:49:29.32#ibcon#*before return 0, iclass 38, count 2 2006.201.09:49:29.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:29.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:29.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.09:49:29.32#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:29.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:29.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:29.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:29.44#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:49:29.44#ibcon#first serial, iclass 38, count 0 2006.201.09:49:29.44#ibcon#enter sib2, iclass 38, count 0 2006.201.09:49:29.44#ibcon#flushed, iclass 38, count 0 2006.201.09:49:29.44#ibcon#about to write, iclass 38, count 0 2006.201.09:49:29.44#ibcon#wrote, iclass 38, count 0 2006.201.09:49:29.44#ibcon#about to read 3, iclass 38, count 0 2006.201.09:49:29.46#ibcon#read 3, iclass 38, count 0 2006.201.09:49:29.46#ibcon#about to read 4, iclass 38, count 0 2006.201.09:49:29.46#ibcon#read 4, iclass 38, count 0 2006.201.09:49:29.46#ibcon#about to read 5, iclass 38, count 0 2006.201.09:49:29.46#ibcon#read 5, iclass 38, count 0 2006.201.09:49:29.46#ibcon#about to read 6, iclass 38, count 0 2006.201.09:49:29.46#ibcon#read 6, iclass 38, count 0 2006.201.09:49:29.46#ibcon#end of sib2, iclass 38, count 0 2006.201.09:49:29.46#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:49:29.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:49:29.46#ibcon#[25=USB\r\n] 2006.201.09:49:29.46#ibcon#*before write, iclass 38, count 0 2006.201.09:49:29.46#ibcon#enter sib2, iclass 38, count 0 2006.201.09:49:29.46#ibcon#flushed, iclass 38, count 0 2006.201.09:49:29.46#ibcon#about to write, iclass 38, count 0 2006.201.09:49:29.46#ibcon#wrote, iclass 38, count 0 2006.201.09:49:29.46#ibcon#about to read 3, iclass 38, count 0 2006.201.09:49:29.49#ibcon#read 3, iclass 38, count 0 2006.201.09:49:29.49#ibcon#about to read 4, iclass 38, count 0 2006.201.09:49:29.49#ibcon#read 4, iclass 38, count 0 2006.201.09:49:29.49#ibcon#about to read 5, iclass 38, count 0 2006.201.09:49:29.49#ibcon#read 5, iclass 38, count 0 2006.201.09:49:29.49#ibcon#about to read 6, iclass 38, count 0 2006.201.09:49:29.49#ibcon#read 6, iclass 38, count 0 2006.201.09:49:29.49#ibcon#end of sib2, iclass 38, count 0 2006.201.09:49:29.49#ibcon#*after write, iclass 38, count 0 2006.201.09:49:29.49#ibcon#*before return 0, iclass 38, count 0 2006.201.09:49:29.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:29.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:29.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:49:29.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:49:29.49$vck44/valo=5,734.99 2006.201.09:49:29.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.09:49:29.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.09:49:29.49#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:29.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:29.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:29.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:29.49#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:49:29.49#ibcon#first serial, iclass 40, count 0 2006.201.09:49:29.49#ibcon#enter sib2, iclass 40, count 0 2006.201.09:49:29.49#ibcon#flushed, iclass 40, count 0 2006.201.09:49:29.49#ibcon#about to write, iclass 40, count 0 2006.201.09:49:29.49#ibcon#wrote, iclass 40, count 0 2006.201.09:49:29.49#ibcon#about to read 3, iclass 40, count 0 2006.201.09:49:29.51#ibcon#read 3, iclass 40, count 0 2006.201.09:49:29.51#ibcon#about to read 4, iclass 40, count 0 2006.201.09:49:29.51#ibcon#read 4, iclass 40, count 0 2006.201.09:49:29.51#ibcon#about to read 5, iclass 40, count 0 2006.201.09:49:29.51#ibcon#read 5, iclass 40, count 0 2006.201.09:49:29.51#ibcon#about to read 6, iclass 40, count 0 2006.201.09:49:29.51#ibcon#read 6, iclass 40, count 0 2006.201.09:49:29.51#ibcon#end of sib2, iclass 40, count 0 2006.201.09:49:29.51#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:49:29.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:49:29.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:49:29.51#ibcon#*before write, iclass 40, count 0 2006.201.09:49:29.51#ibcon#enter sib2, iclass 40, count 0 2006.201.09:49:29.51#ibcon#flushed, iclass 40, count 0 2006.201.09:49:29.51#ibcon#about to write, iclass 40, count 0 2006.201.09:49:29.51#ibcon#wrote, iclass 40, count 0 2006.201.09:49:29.51#ibcon#about to read 3, iclass 40, count 0 2006.201.09:49:29.55#ibcon#read 3, iclass 40, count 0 2006.201.09:49:29.55#ibcon#about to read 4, iclass 40, count 0 2006.201.09:49:29.55#ibcon#read 4, iclass 40, count 0 2006.201.09:49:29.55#ibcon#about to read 5, iclass 40, count 0 2006.201.09:49:29.55#ibcon#read 5, iclass 40, count 0 2006.201.09:49:29.55#ibcon#about to read 6, iclass 40, count 0 2006.201.09:49:29.55#ibcon#read 6, iclass 40, count 0 2006.201.09:49:29.55#ibcon#end of sib2, iclass 40, count 0 2006.201.09:49:29.55#ibcon#*after write, iclass 40, count 0 2006.201.09:49:29.55#ibcon#*before return 0, iclass 40, count 0 2006.201.09:49:29.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:29.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:29.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:49:29.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:49:29.55$vck44/va=5,4 2006.201.09:49:29.55#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.09:49:29.55#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.09:49:29.55#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:29.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:29.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:29.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:29.61#ibcon#enter wrdev, iclass 4, count 2 2006.201.09:49:29.61#ibcon#first serial, iclass 4, count 2 2006.201.09:49:29.61#ibcon#enter sib2, iclass 4, count 2 2006.201.09:49:29.61#ibcon#flushed, iclass 4, count 2 2006.201.09:49:29.61#ibcon#about to write, iclass 4, count 2 2006.201.09:49:29.61#ibcon#wrote, iclass 4, count 2 2006.201.09:49:29.61#ibcon#about to read 3, iclass 4, count 2 2006.201.09:49:29.63#ibcon#read 3, iclass 4, count 2 2006.201.09:49:29.63#ibcon#about to read 4, iclass 4, count 2 2006.201.09:49:29.63#ibcon#read 4, iclass 4, count 2 2006.201.09:49:29.63#ibcon#about to read 5, iclass 4, count 2 2006.201.09:49:29.63#ibcon#read 5, iclass 4, count 2 2006.201.09:49:29.63#ibcon#about to read 6, iclass 4, count 2 2006.201.09:49:29.63#ibcon#read 6, iclass 4, count 2 2006.201.09:49:29.63#ibcon#end of sib2, iclass 4, count 2 2006.201.09:49:29.63#ibcon#*mode == 0, iclass 4, count 2 2006.201.09:49:29.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.09:49:29.63#ibcon#[25=AT05-04\r\n] 2006.201.09:49:29.63#ibcon#*before write, iclass 4, count 2 2006.201.09:49:29.63#ibcon#enter sib2, iclass 4, count 2 2006.201.09:49:29.63#ibcon#flushed, iclass 4, count 2 2006.201.09:49:29.63#ibcon#about to write, iclass 4, count 2 2006.201.09:49:29.63#ibcon#wrote, iclass 4, count 2 2006.201.09:49:29.63#ibcon#about to read 3, iclass 4, count 2 2006.201.09:49:29.66#ibcon#read 3, iclass 4, count 2 2006.201.09:49:29.66#ibcon#about to read 4, iclass 4, count 2 2006.201.09:49:29.66#ibcon#read 4, iclass 4, count 2 2006.201.09:49:29.66#ibcon#about to read 5, iclass 4, count 2 2006.201.09:49:29.66#ibcon#read 5, iclass 4, count 2 2006.201.09:49:29.66#ibcon#about to read 6, iclass 4, count 2 2006.201.09:49:29.66#ibcon#read 6, iclass 4, count 2 2006.201.09:49:29.66#ibcon#end of sib2, iclass 4, count 2 2006.201.09:49:29.66#ibcon#*after write, iclass 4, count 2 2006.201.09:49:29.66#ibcon#*before return 0, iclass 4, count 2 2006.201.09:49:29.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:29.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:29.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.09:49:29.66#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:29.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:29.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:29.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:29.78#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:49:29.78#ibcon#first serial, iclass 4, count 0 2006.201.09:49:29.78#ibcon#enter sib2, iclass 4, count 0 2006.201.09:49:29.78#ibcon#flushed, iclass 4, count 0 2006.201.09:49:29.78#ibcon#about to write, iclass 4, count 0 2006.201.09:49:29.78#ibcon#wrote, iclass 4, count 0 2006.201.09:49:29.78#ibcon#about to read 3, iclass 4, count 0 2006.201.09:49:29.80#ibcon#read 3, iclass 4, count 0 2006.201.09:49:29.80#ibcon#about to read 4, iclass 4, count 0 2006.201.09:49:29.80#ibcon#read 4, iclass 4, count 0 2006.201.09:49:29.80#ibcon#about to read 5, iclass 4, count 0 2006.201.09:49:29.80#ibcon#read 5, iclass 4, count 0 2006.201.09:49:29.80#ibcon#about to read 6, iclass 4, count 0 2006.201.09:49:29.80#ibcon#read 6, iclass 4, count 0 2006.201.09:49:29.80#ibcon#end of sib2, iclass 4, count 0 2006.201.09:49:29.80#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:49:29.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:49:29.80#ibcon#[25=USB\r\n] 2006.201.09:49:29.80#ibcon#*before write, iclass 4, count 0 2006.201.09:49:29.80#ibcon#enter sib2, iclass 4, count 0 2006.201.09:49:29.80#ibcon#flushed, iclass 4, count 0 2006.201.09:49:29.80#ibcon#about to write, iclass 4, count 0 2006.201.09:49:29.80#ibcon#wrote, iclass 4, count 0 2006.201.09:49:29.80#ibcon#about to read 3, iclass 4, count 0 2006.201.09:49:29.83#ibcon#read 3, iclass 4, count 0 2006.201.09:49:29.83#ibcon#about to read 4, iclass 4, count 0 2006.201.09:49:29.83#ibcon#read 4, iclass 4, count 0 2006.201.09:49:29.83#ibcon#about to read 5, iclass 4, count 0 2006.201.09:49:29.83#ibcon#read 5, iclass 4, count 0 2006.201.09:49:29.83#ibcon#about to read 6, iclass 4, count 0 2006.201.09:49:29.83#ibcon#read 6, iclass 4, count 0 2006.201.09:49:29.83#ibcon#end of sib2, iclass 4, count 0 2006.201.09:49:29.83#ibcon#*after write, iclass 4, count 0 2006.201.09:49:29.83#ibcon#*before return 0, iclass 4, count 0 2006.201.09:49:29.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:29.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:29.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:49:29.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:49:29.83$vck44/valo=6,814.99 2006.201.09:49:29.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.09:49:29.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.09:49:29.83#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:29.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:29.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:29.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:29.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:49:29.83#ibcon#first serial, iclass 6, count 0 2006.201.09:49:29.83#ibcon#enter sib2, iclass 6, count 0 2006.201.09:49:29.83#ibcon#flushed, iclass 6, count 0 2006.201.09:49:29.83#ibcon#about to write, iclass 6, count 0 2006.201.09:49:29.83#ibcon#wrote, iclass 6, count 0 2006.201.09:49:29.83#ibcon#about to read 3, iclass 6, count 0 2006.201.09:49:29.85#ibcon#read 3, iclass 6, count 0 2006.201.09:49:29.85#ibcon#about to read 4, iclass 6, count 0 2006.201.09:49:29.85#ibcon#read 4, iclass 6, count 0 2006.201.09:49:29.85#ibcon#about to read 5, iclass 6, count 0 2006.201.09:49:29.85#ibcon#read 5, iclass 6, count 0 2006.201.09:49:29.85#ibcon#about to read 6, iclass 6, count 0 2006.201.09:49:29.85#ibcon#read 6, iclass 6, count 0 2006.201.09:49:29.85#ibcon#end of sib2, iclass 6, count 0 2006.201.09:49:29.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:49:29.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:49:29.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:49:29.85#ibcon#*before write, iclass 6, count 0 2006.201.09:49:29.85#ibcon#enter sib2, iclass 6, count 0 2006.201.09:49:29.85#ibcon#flushed, iclass 6, count 0 2006.201.09:49:29.85#ibcon#about to write, iclass 6, count 0 2006.201.09:49:29.85#ibcon#wrote, iclass 6, count 0 2006.201.09:49:29.85#ibcon#about to read 3, iclass 6, count 0 2006.201.09:49:29.90#ibcon#read 3, iclass 6, count 0 2006.201.09:49:29.90#ibcon#about to read 4, iclass 6, count 0 2006.201.09:49:29.90#ibcon#read 4, iclass 6, count 0 2006.201.09:49:29.90#ibcon#about to read 5, iclass 6, count 0 2006.201.09:49:29.90#ibcon#read 5, iclass 6, count 0 2006.201.09:49:29.90#ibcon#about to read 6, iclass 6, count 0 2006.201.09:49:29.90#ibcon#read 6, iclass 6, count 0 2006.201.09:49:29.90#ibcon#end of sib2, iclass 6, count 0 2006.201.09:49:29.90#ibcon#*after write, iclass 6, count 0 2006.201.09:49:29.90#ibcon#*before return 0, iclass 6, count 0 2006.201.09:49:29.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:29.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:29.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:49:29.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:49:29.90$vck44/va=6,5 2006.201.09:49:29.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.09:49:29.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.09:49:29.90#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:29.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:29.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:29.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:29.95#ibcon#enter wrdev, iclass 10, count 2 2006.201.09:49:29.95#ibcon#first serial, iclass 10, count 2 2006.201.09:49:29.95#ibcon#enter sib2, iclass 10, count 2 2006.201.09:49:29.95#ibcon#flushed, iclass 10, count 2 2006.201.09:49:29.95#ibcon#about to write, iclass 10, count 2 2006.201.09:49:29.95#ibcon#wrote, iclass 10, count 2 2006.201.09:49:29.95#ibcon#about to read 3, iclass 10, count 2 2006.201.09:49:29.97#ibcon#read 3, iclass 10, count 2 2006.201.09:49:29.97#ibcon#about to read 4, iclass 10, count 2 2006.201.09:49:29.97#ibcon#read 4, iclass 10, count 2 2006.201.09:49:29.97#ibcon#about to read 5, iclass 10, count 2 2006.201.09:49:29.97#ibcon#read 5, iclass 10, count 2 2006.201.09:49:29.97#ibcon#about to read 6, iclass 10, count 2 2006.201.09:49:29.97#ibcon#read 6, iclass 10, count 2 2006.201.09:49:29.97#ibcon#end of sib2, iclass 10, count 2 2006.201.09:49:29.97#ibcon#*mode == 0, iclass 10, count 2 2006.201.09:49:29.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.09:49:29.97#ibcon#[25=AT06-05\r\n] 2006.201.09:49:29.97#ibcon#*before write, iclass 10, count 2 2006.201.09:49:29.97#ibcon#enter sib2, iclass 10, count 2 2006.201.09:49:29.97#ibcon#flushed, iclass 10, count 2 2006.201.09:49:29.97#ibcon#about to write, iclass 10, count 2 2006.201.09:49:29.97#ibcon#wrote, iclass 10, count 2 2006.201.09:49:29.97#ibcon#about to read 3, iclass 10, count 2 2006.201.09:49:30.00#ibcon#read 3, iclass 10, count 2 2006.201.09:49:30.00#ibcon#about to read 4, iclass 10, count 2 2006.201.09:49:30.00#ibcon#read 4, iclass 10, count 2 2006.201.09:49:30.00#ibcon#about to read 5, iclass 10, count 2 2006.201.09:49:30.00#ibcon#read 5, iclass 10, count 2 2006.201.09:49:30.00#ibcon#about to read 6, iclass 10, count 2 2006.201.09:49:30.00#ibcon#read 6, iclass 10, count 2 2006.201.09:49:30.00#ibcon#end of sib2, iclass 10, count 2 2006.201.09:49:30.00#ibcon#*after write, iclass 10, count 2 2006.201.09:49:30.00#ibcon#*before return 0, iclass 10, count 2 2006.201.09:49:30.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:30.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:30.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.09:49:30.00#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:30.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:30.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:30.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:30.12#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:49:30.12#ibcon#first serial, iclass 10, count 0 2006.201.09:49:30.12#ibcon#enter sib2, iclass 10, count 0 2006.201.09:49:30.12#ibcon#flushed, iclass 10, count 0 2006.201.09:49:30.12#ibcon#about to write, iclass 10, count 0 2006.201.09:49:30.12#ibcon#wrote, iclass 10, count 0 2006.201.09:49:30.12#ibcon#about to read 3, iclass 10, count 0 2006.201.09:49:30.14#ibcon#read 3, iclass 10, count 0 2006.201.09:49:30.14#ibcon#about to read 4, iclass 10, count 0 2006.201.09:49:30.14#ibcon#read 4, iclass 10, count 0 2006.201.09:49:30.14#ibcon#about to read 5, iclass 10, count 0 2006.201.09:49:30.14#ibcon#read 5, iclass 10, count 0 2006.201.09:49:30.14#ibcon#about to read 6, iclass 10, count 0 2006.201.09:49:30.14#ibcon#read 6, iclass 10, count 0 2006.201.09:49:30.14#ibcon#end of sib2, iclass 10, count 0 2006.201.09:49:30.14#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:49:30.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:49:30.14#ibcon#[25=USB\r\n] 2006.201.09:49:30.14#ibcon#*before write, iclass 10, count 0 2006.201.09:49:30.14#ibcon#enter sib2, iclass 10, count 0 2006.201.09:49:30.14#ibcon#flushed, iclass 10, count 0 2006.201.09:49:30.14#ibcon#about to write, iclass 10, count 0 2006.201.09:49:30.14#ibcon#wrote, iclass 10, count 0 2006.201.09:49:30.14#ibcon#about to read 3, iclass 10, count 0 2006.201.09:49:30.17#ibcon#read 3, iclass 10, count 0 2006.201.09:49:30.17#ibcon#about to read 4, iclass 10, count 0 2006.201.09:49:30.17#ibcon#read 4, iclass 10, count 0 2006.201.09:49:30.17#ibcon#about to read 5, iclass 10, count 0 2006.201.09:49:30.17#ibcon#read 5, iclass 10, count 0 2006.201.09:49:30.17#ibcon#about to read 6, iclass 10, count 0 2006.201.09:49:30.17#ibcon#read 6, iclass 10, count 0 2006.201.09:49:30.17#ibcon#end of sib2, iclass 10, count 0 2006.201.09:49:30.17#ibcon#*after write, iclass 10, count 0 2006.201.09:49:30.17#ibcon#*before return 0, iclass 10, count 0 2006.201.09:49:30.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:30.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:30.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:49:30.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:49:30.17$vck44/valo=7,864.99 2006.201.09:49:30.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.09:49:30.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.09:49:30.17#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:30.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:30.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:30.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:30.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:49:30.17#ibcon#first serial, iclass 12, count 0 2006.201.09:49:30.17#ibcon#enter sib2, iclass 12, count 0 2006.201.09:49:30.17#ibcon#flushed, iclass 12, count 0 2006.201.09:49:30.17#ibcon#about to write, iclass 12, count 0 2006.201.09:49:30.17#ibcon#wrote, iclass 12, count 0 2006.201.09:49:30.17#ibcon#about to read 3, iclass 12, count 0 2006.201.09:49:30.19#ibcon#read 3, iclass 12, count 0 2006.201.09:49:30.19#ibcon#about to read 4, iclass 12, count 0 2006.201.09:49:30.19#ibcon#read 4, iclass 12, count 0 2006.201.09:49:30.19#ibcon#about to read 5, iclass 12, count 0 2006.201.09:49:30.19#ibcon#read 5, iclass 12, count 0 2006.201.09:49:30.19#ibcon#about to read 6, iclass 12, count 0 2006.201.09:49:30.19#ibcon#read 6, iclass 12, count 0 2006.201.09:49:30.19#ibcon#end of sib2, iclass 12, count 0 2006.201.09:49:30.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:49:30.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:49:30.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:49:30.19#ibcon#*before write, iclass 12, count 0 2006.201.09:49:30.19#ibcon#enter sib2, iclass 12, count 0 2006.201.09:49:30.19#ibcon#flushed, iclass 12, count 0 2006.201.09:49:30.19#ibcon#about to write, iclass 12, count 0 2006.201.09:49:30.19#ibcon#wrote, iclass 12, count 0 2006.201.09:49:30.19#ibcon#about to read 3, iclass 12, count 0 2006.201.09:49:30.23#ibcon#read 3, iclass 12, count 0 2006.201.09:49:30.23#ibcon#about to read 4, iclass 12, count 0 2006.201.09:49:30.23#ibcon#read 4, iclass 12, count 0 2006.201.09:49:30.23#ibcon#about to read 5, iclass 12, count 0 2006.201.09:49:30.23#ibcon#read 5, iclass 12, count 0 2006.201.09:49:30.23#ibcon#about to read 6, iclass 12, count 0 2006.201.09:49:30.23#ibcon#read 6, iclass 12, count 0 2006.201.09:49:30.23#ibcon#end of sib2, iclass 12, count 0 2006.201.09:49:30.23#ibcon#*after write, iclass 12, count 0 2006.201.09:49:30.23#ibcon#*before return 0, iclass 12, count 0 2006.201.09:49:30.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:30.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:30.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:49:30.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:49:30.23$vck44/va=7,5 2006.201.09:49:30.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.09:49:30.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.09:49:30.23#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:30.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:30.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:30.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:30.29#ibcon#enter wrdev, iclass 14, count 2 2006.201.09:49:30.29#ibcon#first serial, iclass 14, count 2 2006.201.09:49:30.29#ibcon#enter sib2, iclass 14, count 2 2006.201.09:49:30.29#ibcon#flushed, iclass 14, count 2 2006.201.09:49:30.29#ibcon#about to write, iclass 14, count 2 2006.201.09:49:30.29#ibcon#wrote, iclass 14, count 2 2006.201.09:49:30.29#ibcon#about to read 3, iclass 14, count 2 2006.201.09:49:30.31#ibcon#read 3, iclass 14, count 2 2006.201.09:49:30.31#ibcon#about to read 4, iclass 14, count 2 2006.201.09:49:30.31#ibcon#read 4, iclass 14, count 2 2006.201.09:49:30.31#ibcon#about to read 5, iclass 14, count 2 2006.201.09:49:30.31#ibcon#read 5, iclass 14, count 2 2006.201.09:49:30.31#ibcon#about to read 6, iclass 14, count 2 2006.201.09:49:30.31#ibcon#read 6, iclass 14, count 2 2006.201.09:49:30.31#ibcon#end of sib2, iclass 14, count 2 2006.201.09:49:30.31#ibcon#*mode == 0, iclass 14, count 2 2006.201.09:49:30.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.09:49:30.31#ibcon#[25=AT07-05\r\n] 2006.201.09:49:30.31#ibcon#*before write, iclass 14, count 2 2006.201.09:49:30.31#ibcon#enter sib2, iclass 14, count 2 2006.201.09:49:30.31#ibcon#flushed, iclass 14, count 2 2006.201.09:49:30.31#ibcon#about to write, iclass 14, count 2 2006.201.09:49:30.31#ibcon#wrote, iclass 14, count 2 2006.201.09:49:30.31#ibcon#about to read 3, iclass 14, count 2 2006.201.09:49:30.34#ibcon#read 3, iclass 14, count 2 2006.201.09:49:30.34#ibcon#about to read 4, iclass 14, count 2 2006.201.09:49:30.34#ibcon#read 4, iclass 14, count 2 2006.201.09:49:30.34#ibcon#about to read 5, iclass 14, count 2 2006.201.09:49:30.34#ibcon#read 5, iclass 14, count 2 2006.201.09:49:30.34#ibcon#about to read 6, iclass 14, count 2 2006.201.09:49:30.34#ibcon#read 6, iclass 14, count 2 2006.201.09:49:30.34#ibcon#end of sib2, iclass 14, count 2 2006.201.09:49:30.34#ibcon#*after write, iclass 14, count 2 2006.201.09:49:30.34#ibcon#*before return 0, iclass 14, count 2 2006.201.09:49:30.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:30.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:30.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.09:49:30.34#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:30.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:30.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:30.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:30.46#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:49:30.46#ibcon#first serial, iclass 14, count 0 2006.201.09:49:30.46#ibcon#enter sib2, iclass 14, count 0 2006.201.09:49:30.46#ibcon#flushed, iclass 14, count 0 2006.201.09:49:30.46#ibcon#about to write, iclass 14, count 0 2006.201.09:49:30.46#ibcon#wrote, iclass 14, count 0 2006.201.09:49:30.46#ibcon#about to read 3, iclass 14, count 0 2006.201.09:49:30.48#ibcon#read 3, iclass 14, count 0 2006.201.09:49:30.48#ibcon#about to read 4, iclass 14, count 0 2006.201.09:49:30.48#ibcon#read 4, iclass 14, count 0 2006.201.09:49:30.48#ibcon#about to read 5, iclass 14, count 0 2006.201.09:49:30.48#ibcon#read 5, iclass 14, count 0 2006.201.09:49:30.48#ibcon#about to read 6, iclass 14, count 0 2006.201.09:49:30.48#ibcon#read 6, iclass 14, count 0 2006.201.09:49:30.48#ibcon#end of sib2, iclass 14, count 0 2006.201.09:49:30.48#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:49:30.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:49:30.48#ibcon#[25=USB\r\n] 2006.201.09:49:30.48#ibcon#*before write, iclass 14, count 0 2006.201.09:49:30.48#ibcon#enter sib2, iclass 14, count 0 2006.201.09:49:30.48#ibcon#flushed, iclass 14, count 0 2006.201.09:49:30.48#ibcon#about to write, iclass 14, count 0 2006.201.09:49:30.48#ibcon#wrote, iclass 14, count 0 2006.201.09:49:30.48#ibcon#about to read 3, iclass 14, count 0 2006.201.09:49:30.51#ibcon#read 3, iclass 14, count 0 2006.201.09:49:30.51#ibcon#about to read 4, iclass 14, count 0 2006.201.09:49:30.51#ibcon#read 4, iclass 14, count 0 2006.201.09:49:30.51#ibcon#about to read 5, iclass 14, count 0 2006.201.09:49:30.51#ibcon#read 5, iclass 14, count 0 2006.201.09:49:30.51#ibcon#about to read 6, iclass 14, count 0 2006.201.09:49:30.51#ibcon#read 6, iclass 14, count 0 2006.201.09:49:30.51#ibcon#end of sib2, iclass 14, count 0 2006.201.09:49:30.51#ibcon#*after write, iclass 14, count 0 2006.201.09:49:30.51#ibcon#*before return 0, iclass 14, count 0 2006.201.09:49:30.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:30.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:30.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:49:30.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:49:30.51$vck44/valo=8,884.99 2006.201.09:49:30.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.09:49:30.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.09:49:30.51#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:30.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:30.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:30.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:30.51#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:49:30.51#ibcon#first serial, iclass 16, count 0 2006.201.09:49:30.51#ibcon#enter sib2, iclass 16, count 0 2006.201.09:49:30.51#ibcon#flushed, iclass 16, count 0 2006.201.09:49:30.51#ibcon#about to write, iclass 16, count 0 2006.201.09:49:30.51#ibcon#wrote, iclass 16, count 0 2006.201.09:49:30.51#ibcon#about to read 3, iclass 16, count 0 2006.201.09:49:30.53#ibcon#read 3, iclass 16, count 0 2006.201.09:49:30.53#ibcon#about to read 4, iclass 16, count 0 2006.201.09:49:30.53#ibcon#read 4, iclass 16, count 0 2006.201.09:49:30.53#ibcon#about to read 5, iclass 16, count 0 2006.201.09:49:30.53#ibcon#read 5, iclass 16, count 0 2006.201.09:49:30.53#ibcon#about to read 6, iclass 16, count 0 2006.201.09:49:30.53#ibcon#read 6, iclass 16, count 0 2006.201.09:49:30.53#ibcon#end of sib2, iclass 16, count 0 2006.201.09:49:30.53#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:49:30.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:49:30.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:49:30.53#ibcon#*before write, iclass 16, count 0 2006.201.09:49:30.53#ibcon#enter sib2, iclass 16, count 0 2006.201.09:49:30.53#ibcon#flushed, iclass 16, count 0 2006.201.09:49:30.53#ibcon#about to write, iclass 16, count 0 2006.201.09:49:30.53#ibcon#wrote, iclass 16, count 0 2006.201.09:49:30.53#ibcon#about to read 3, iclass 16, count 0 2006.201.09:49:30.58#ibcon#read 3, iclass 16, count 0 2006.201.09:49:30.58#ibcon#about to read 4, iclass 16, count 0 2006.201.09:49:30.58#ibcon#read 4, iclass 16, count 0 2006.201.09:49:30.58#ibcon#about to read 5, iclass 16, count 0 2006.201.09:49:30.58#ibcon#read 5, iclass 16, count 0 2006.201.09:49:30.58#ibcon#about to read 6, iclass 16, count 0 2006.201.09:49:30.58#ibcon#read 6, iclass 16, count 0 2006.201.09:49:30.58#ibcon#end of sib2, iclass 16, count 0 2006.201.09:49:30.58#ibcon#*after write, iclass 16, count 0 2006.201.09:49:30.58#ibcon#*before return 0, iclass 16, count 0 2006.201.09:49:30.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:30.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:30.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:49:30.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:49:30.58$vck44/va=8,4 2006.201.09:49:30.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.09:49:30.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.09:49:30.58#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:30.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:49:30.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:49:30.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:49:30.63#ibcon#enter wrdev, iclass 18, count 2 2006.201.09:49:30.63#ibcon#first serial, iclass 18, count 2 2006.201.09:49:30.63#ibcon#enter sib2, iclass 18, count 2 2006.201.09:49:30.63#ibcon#flushed, iclass 18, count 2 2006.201.09:49:30.63#ibcon#about to write, iclass 18, count 2 2006.201.09:49:30.63#ibcon#wrote, iclass 18, count 2 2006.201.09:49:30.63#ibcon#about to read 3, iclass 18, count 2 2006.201.09:49:30.65#ibcon#read 3, iclass 18, count 2 2006.201.09:49:30.65#ibcon#about to read 4, iclass 18, count 2 2006.201.09:49:30.65#ibcon#read 4, iclass 18, count 2 2006.201.09:49:30.65#ibcon#about to read 5, iclass 18, count 2 2006.201.09:49:30.65#ibcon#read 5, iclass 18, count 2 2006.201.09:49:30.65#ibcon#about to read 6, iclass 18, count 2 2006.201.09:49:30.65#ibcon#read 6, iclass 18, count 2 2006.201.09:49:30.65#ibcon#end of sib2, iclass 18, count 2 2006.201.09:49:30.65#ibcon#*mode == 0, iclass 18, count 2 2006.201.09:49:30.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.09:49:30.65#ibcon#[25=AT08-04\r\n] 2006.201.09:49:30.65#ibcon#*before write, iclass 18, count 2 2006.201.09:49:30.65#ibcon#enter sib2, iclass 18, count 2 2006.201.09:49:30.65#ibcon#flushed, iclass 18, count 2 2006.201.09:49:30.65#ibcon#about to write, iclass 18, count 2 2006.201.09:49:30.65#ibcon#wrote, iclass 18, count 2 2006.201.09:49:30.65#ibcon#about to read 3, iclass 18, count 2 2006.201.09:49:30.68#ibcon#read 3, iclass 18, count 2 2006.201.09:49:30.68#ibcon#about to read 4, iclass 18, count 2 2006.201.09:49:30.68#ibcon#read 4, iclass 18, count 2 2006.201.09:49:30.68#ibcon#about to read 5, iclass 18, count 2 2006.201.09:49:30.68#ibcon#read 5, iclass 18, count 2 2006.201.09:49:30.68#ibcon#about to read 6, iclass 18, count 2 2006.201.09:49:30.68#ibcon#read 6, iclass 18, count 2 2006.201.09:49:30.68#ibcon#end of sib2, iclass 18, count 2 2006.201.09:49:30.68#ibcon#*after write, iclass 18, count 2 2006.201.09:49:30.68#ibcon#*before return 0, iclass 18, count 2 2006.201.09:49:30.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:49:30.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.09:49:30.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.09:49:30.68#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:30.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:49:30.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:49:30.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:49:30.80#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:49:30.80#ibcon#first serial, iclass 18, count 0 2006.201.09:49:30.80#ibcon#enter sib2, iclass 18, count 0 2006.201.09:49:30.80#ibcon#flushed, iclass 18, count 0 2006.201.09:49:30.80#ibcon#about to write, iclass 18, count 0 2006.201.09:49:30.80#ibcon#wrote, iclass 18, count 0 2006.201.09:49:30.80#ibcon#about to read 3, iclass 18, count 0 2006.201.09:49:30.82#ibcon#read 3, iclass 18, count 0 2006.201.09:49:30.82#ibcon#about to read 4, iclass 18, count 0 2006.201.09:49:30.82#ibcon#read 4, iclass 18, count 0 2006.201.09:49:30.82#ibcon#about to read 5, iclass 18, count 0 2006.201.09:49:30.82#ibcon#read 5, iclass 18, count 0 2006.201.09:49:30.82#ibcon#about to read 6, iclass 18, count 0 2006.201.09:49:30.82#ibcon#read 6, iclass 18, count 0 2006.201.09:49:30.82#ibcon#end of sib2, iclass 18, count 0 2006.201.09:49:30.82#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:49:30.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:49:30.82#ibcon#[25=USB\r\n] 2006.201.09:49:30.82#ibcon#*before write, iclass 18, count 0 2006.201.09:49:30.82#ibcon#enter sib2, iclass 18, count 0 2006.201.09:49:30.82#ibcon#flushed, iclass 18, count 0 2006.201.09:49:30.82#ibcon#about to write, iclass 18, count 0 2006.201.09:49:30.82#ibcon#wrote, iclass 18, count 0 2006.201.09:49:30.82#ibcon#about to read 3, iclass 18, count 0 2006.201.09:49:30.85#ibcon#read 3, iclass 18, count 0 2006.201.09:49:30.85#ibcon#about to read 4, iclass 18, count 0 2006.201.09:49:30.85#ibcon#read 4, iclass 18, count 0 2006.201.09:49:30.85#ibcon#about to read 5, iclass 18, count 0 2006.201.09:49:30.85#ibcon#read 5, iclass 18, count 0 2006.201.09:49:30.85#ibcon#about to read 6, iclass 18, count 0 2006.201.09:49:30.85#ibcon#read 6, iclass 18, count 0 2006.201.09:49:30.85#ibcon#end of sib2, iclass 18, count 0 2006.201.09:49:30.85#ibcon#*after write, iclass 18, count 0 2006.201.09:49:30.85#ibcon#*before return 0, iclass 18, count 0 2006.201.09:49:30.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:49:30.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.09:49:30.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:49:30.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:49:30.85$vck44/vblo=1,629.99 2006.201.09:49:30.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.09:49:30.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.09:49:30.85#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:30.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:49:30.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:49:30.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:49:30.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.09:49:30.85#ibcon#first serial, iclass 20, count 0 2006.201.09:49:30.85#ibcon#enter sib2, iclass 20, count 0 2006.201.09:49:30.85#ibcon#flushed, iclass 20, count 0 2006.201.09:49:30.85#ibcon#about to write, iclass 20, count 0 2006.201.09:49:30.85#ibcon#wrote, iclass 20, count 0 2006.201.09:49:30.85#ibcon#about to read 3, iclass 20, count 0 2006.201.09:49:30.87#ibcon#read 3, iclass 20, count 0 2006.201.09:49:30.87#ibcon#about to read 4, iclass 20, count 0 2006.201.09:49:30.87#ibcon#read 4, iclass 20, count 0 2006.201.09:49:30.87#ibcon#about to read 5, iclass 20, count 0 2006.201.09:49:30.87#ibcon#read 5, iclass 20, count 0 2006.201.09:49:30.87#ibcon#about to read 6, iclass 20, count 0 2006.201.09:49:30.87#ibcon#read 6, iclass 20, count 0 2006.201.09:49:30.87#ibcon#end of sib2, iclass 20, count 0 2006.201.09:49:30.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.09:49:30.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.09:49:30.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:49:30.87#ibcon#*before write, iclass 20, count 0 2006.201.09:49:30.87#ibcon#enter sib2, iclass 20, count 0 2006.201.09:49:30.87#ibcon#flushed, iclass 20, count 0 2006.201.09:49:30.87#ibcon#about to write, iclass 20, count 0 2006.201.09:49:30.87#ibcon#wrote, iclass 20, count 0 2006.201.09:49:30.87#ibcon#about to read 3, iclass 20, count 0 2006.201.09:49:30.92#ibcon#read 3, iclass 20, count 0 2006.201.09:49:30.92#ibcon#about to read 4, iclass 20, count 0 2006.201.09:49:30.92#ibcon#read 4, iclass 20, count 0 2006.201.09:49:30.92#ibcon#about to read 5, iclass 20, count 0 2006.201.09:49:30.92#ibcon#read 5, iclass 20, count 0 2006.201.09:49:30.92#ibcon#about to read 6, iclass 20, count 0 2006.201.09:49:30.92#ibcon#read 6, iclass 20, count 0 2006.201.09:49:30.92#ibcon#end of sib2, iclass 20, count 0 2006.201.09:49:30.92#ibcon#*after write, iclass 20, count 0 2006.201.09:49:30.92#ibcon#*before return 0, iclass 20, count 0 2006.201.09:49:30.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:49:30.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.09:49:30.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.09:49:30.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.09:49:30.92$vck44/vb=1,4 2006.201.09:49:30.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.09:49:30.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.09:49:30.92#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:30.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:49:30.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:49:30.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:49:30.92#ibcon#enter wrdev, iclass 22, count 2 2006.201.09:49:30.92#ibcon#first serial, iclass 22, count 2 2006.201.09:49:30.92#ibcon#enter sib2, iclass 22, count 2 2006.201.09:49:30.92#ibcon#flushed, iclass 22, count 2 2006.201.09:49:30.92#ibcon#about to write, iclass 22, count 2 2006.201.09:49:30.92#ibcon#wrote, iclass 22, count 2 2006.201.09:49:30.92#ibcon#about to read 3, iclass 22, count 2 2006.201.09:49:30.94#ibcon#read 3, iclass 22, count 2 2006.201.09:49:30.94#ibcon#about to read 4, iclass 22, count 2 2006.201.09:49:30.94#ibcon#read 4, iclass 22, count 2 2006.201.09:49:30.94#ibcon#about to read 5, iclass 22, count 2 2006.201.09:49:30.94#ibcon#read 5, iclass 22, count 2 2006.201.09:49:30.94#ibcon#about to read 6, iclass 22, count 2 2006.201.09:49:30.94#ibcon#read 6, iclass 22, count 2 2006.201.09:49:30.94#ibcon#end of sib2, iclass 22, count 2 2006.201.09:49:30.94#ibcon#*mode == 0, iclass 22, count 2 2006.201.09:49:30.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.09:49:30.94#ibcon#[27=AT01-04\r\n] 2006.201.09:49:30.94#ibcon#*before write, iclass 22, count 2 2006.201.09:49:30.94#ibcon#enter sib2, iclass 22, count 2 2006.201.09:49:30.94#ibcon#flushed, iclass 22, count 2 2006.201.09:49:30.94#ibcon#about to write, iclass 22, count 2 2006.201.09:49:30.94#ibcon#wrote, iclass 22, count 2 2006.201.09:49:30.94#ibcon#about to read 3, iclass 22, count 2 2006.201.09:49:30.97#ibcon#read 3, iclass 22, count 2 2006.201.09:49:30.97#ibcon#about to read 4, iclass 22, count 2 2006.201.09:49:30.97#ibcon#read 4, iclass 22, count 2 2006.201.09:49:30.97#ibcon#about to read 5, iclass 22, count 2 2006.201.09:49:30.97#ibcon#read 5, iclass 22, count 2 2006.201.09:49:30.97#ibcon#about to read 6, iclass 22, count 2 2006.201.09:49:30.97#ibcon#read 6, iclass 22, count 2 2006.201.09:49:30.97#ibcon#end of sib2, iclass 22, count 2 2006.201.09:49:30.97#ibcon#*after write, iclass 22, count 2 2006.201.09:49:30.97#ibcon#*before return 0, iclass 22, count 2 2006.201.09:49:30.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:49:30.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.09:49:30.97#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.09:49:30.97#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:30.97#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:49:31.09#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:49:31.09#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:49:31.09#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:49:31.09#ibcon#first serial, iclass 22, count 0 2006.201.09:49:31.09#ibcon#enter sib2, iclass 22, count 0 2006.201.09:49:31.09#ibcon#flushed, iclass 22, count 0 2006.201.09:49:31.09#ibcon#about to write, iclass 22, count 0 2006.201.09:49:31.09#ibcon#wrote, iclass 22, count 0 2006.201.09:49:31.09#ibcon#about to read 3, iclass 22, count 0 2006.201.09:49:31.11#ibcon#read 3, iclass 22, count 0 2006.201.09:49:31.11#ibcon#about to read 4, iclass 22, count 0 2006.201.09:49:31.11#ibcon#read 4, iclass 22, count 0 2006.201.09:49:31.11#ibcon#about to read 5, iclass 22, count 0 2006.201.09:49:31.11#ibcon#read 5, iclass 22, count 0 2006.201.09:49:31.11#ibcon#about to read 6, iclass 22, count 0 2006.201.09:49:31.11#ibcon#read 6, iclass 22, count 0 2006.201.09:49:31.11#ibcon#end of sib2, iclass 22, count 0 2006.201.09:49:31.11#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:49:31.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:49:31.11#ibcon#[27=USB\r\n] 2006.201.09:49:31.11#ibcon#*before write, iclass 22, count 0 2006.201.09:49:31.11#ibcon#enter sib2, iclass 22, count 0 2006.201.09:49:31.11#ibcon#flushed, iclass 22, count 0 2006.201.09:49:31.11#ibcon#about to write, iclass 22, count 0 2006.201.09:49:31.11#ibcon#wrote, iclass 22, count 0 2006.201.09:49:31.11#ibcon#about to read 3, iclass 22, count 0 2006.201.09:49:31.14#ibcon#read 3, iclass 22, count 0 2006.201.09:49:31.14#ibcon#about to read 4, iclass 22, count 0 2006.201.09:49:31.14#ibcon#read 4, iclass 22, count 0 2006.201.09:49:31.14#ibcon#about to read 5, iclass 22, count 0 2006.201.09:49:31.14#ibcon#read 5, iclass 22, count 0 2006.201.09:49:31.14#ibcon#about to read 6, iclass 22, count 0 2006.201.09:49:31.14#ibcon#read 6, iclass 22, count 0 2006.201.09:49:31.14#ibcon#end of sib2, iclass 22, count 0 2006.201.09:49:31.14#ibcon#*after write, iclass 22, count 0 2006.201.09:49:31.14#ibcon#*before return 0, iclass 22, count 0 2006.201.09:49:31.14#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:49:31.14#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.09:49:31.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:49:31.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:49:31.14$vck44/vblo=2,634.99 2006.201.09:49:31.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.09:49:31.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.09:49:31.14#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:31.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:31.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:31.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:31.14#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:49:31.14#ibcon#first serial, iclass 24, count 0 2006.201.09:49:31.14#ibcon#enter sib2, iclass 24, count 0 2006.201.09:49:31.14#ibcon#flushed, iclass 24, count 0 2006.201.09:49:31.14#ibcon#about to write, iclass 24, count 0 2006.201.09:49:31.14#ibcon#wrote, iclass 24, count 0 2006.201.09:49:31.14#ibcon#about to read 3, iclass 24, count 0 2006.201.09:49:31.16#ibcon#read 3, iclass 24, count 0 2006.201.09:49:31.16#ibcon#about to read 4, iclass 24, count 0 2006.201.09:49:31.16#ibcon#read 4, iclass 24, count 0 2006.201.09:49:31.16#ibcon#about to read 5, iclass 24, count 0 2006.201.09:49:31.16#ibcon#read 5, iclass 24, count 0 2006.201.09:49:31.16#ibcon#about to read 6, iclass 24, count 0 2006.201.09:49:31.16#ibcon#read 6, iclass 24, count 0 2006.201.09:49:31.16#ibcon#end of sib2, iclass 24, count 0 2006.201.09:49:31.16#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:49:31.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:49:31.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:49:31.16#ibcon#*before write, iclass 24, count 0 2006.201.09:49:31.16#ibcon#enter sib2, iclass 24, count 0 2006.201.09:49:31.16#ibcon#flushed, iclass 24, count 0 2006.201.09:49:31.16#ibcon#about to write, iclass 24, count 0 2006.201.09:49:31.16#ibcon#wrote, iclass 24, count 0 2006.201.09:49:31.16#ibcon#about to read 3, iclass 24, count 0 2006.201.09:49:31.20#ibcon#read 3, iclass 24, count 0 2006.201.09:49:31.20#ibcon#about to read 4, iclass 24, count 0 2006.201.09:49:31.20#ibcon#read 4, iclass 24, count 0 2006.201.09:49:31.20#ibcon#about to read 5, iclass 24, count 0 2006.201.09:49:31.20#ibcon#read 5, iclass 24, count 0 2006.201.09:49:31.20#ibcon#about to read 6, iclass 24, count 0 2006.201.09:49:31.20#ibcon#read 6, iclass 24, count 0 2006.201.09:49:31.20#ibcon#end of sib2, iclass 24, count 0 2006.201.09:49:31.20#ibcon#*after write, iclass 24, count 0 2006.201.09:49:31.20#ibcon#*before return 0, iclass 24, count 0 2006.201.09:49:31.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:31.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.09:49:31.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:49:31.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:49:31.20$vck44/vb=2,5 2006.201.09:49:31.20#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.09:49:31.20#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.09:49:31.20#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:31.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:31.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:31.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:31.26#ibcon#enter wrdev, iclass 26, count 2 2006.201.09:49:31.26#ibcon#first serial, iclass 26, count 2 2006.201.09:49:31.26#ibcon#enter sib2, iclass 26, count 2 2006.201.09:49:31.26#ibcon#flushed, iclass 26, count 2 2006.201.09:49:31.26#ibcon#about to write, iclass 26, count 2 2006.201.09:49:31.26#ibcon#wrote, iclass 26, count 2 2006.201.09:49:31.26#ibcon#about to read 3, iclass 26, count 2 2006.201.09:49:31.28#ibcon#read 3, iclass 26, count 2 2006.201.09:49:31.28#ibcon#about to read 4, iclass 26, count 2 2006.201.09:49:31.28#ibcon#read 4, iclass 26, count 2 2006.201.09:49:31.28#ibcon#about to read 5, iclass 26, count 2 2006.201.09:49:31.28#ibcon#read 5, iclass 26, count 2 2006.201.09:49:31.28#ibcon#about to read 6, iclass 26, count 2 2006.201.09:49:31.28#ibcon#read 6, iclass 26, count 2 2006.201.09:49:31.28#ibcon#end of sib2, iclass 26, count 2 2006.201.09:49:31.28#ibcon#*mode == 0, iclass 26, count 2 2006.201.09:49:31.28#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.09:49:31.28#ibcon#[27=AT02-05\r\n] 2006.201.09:49:31.28#ibcon#*before write, iclass 26, count 2 2006.201.09:49:31.28#ibcon#enter sib2, iclass 26, count 2 2006.201.09:49:31.28#ibcon#flushed, iclass 26, count 2 2006.201.09:49:31.28#ibcon#about to write, iclass 26, count 2 2006.201.09:49:31.28#ibcon#wrote, iclass 26, count 2 2006.201.09:49:31.28#ibcon#about to read 3, iclass 26, count 2 2006.201.09:49:31.31#ibcon#read 3, iclass 26, count 2 2006.201.09:49:31.31#ibcon#about to read 4, iclass 26, count 2 2006.201.09:49:31.31#ibcon#read 4, iclass 26, count 2 2006.201.09:49:31.31#ibcon#about to read 5, iclass 26, count 2 2006.201.09:49:31.31#ibcon#read 5, iclass 26, count 2 2006.201.09:49:31.31#ibcon#about to read 6, iclass 26, count 2 2006.201.09:49:31.31#ibcon#read 6, iclass 26, count 2 2006.201.09:49:31.31#ibcon#end of sib2, iclass 26, count 2 2006.201.09:49:31.31#ibcon#*after write, iclass 26, count 2 2006.201.09:49:31.31#ibcon#*before return 0, iclass 26, count 2 2006.201.09:49:31.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:31.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.09:49:31.31#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.09:49:31.31#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:31.31#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:31.43#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:31.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:31.43#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:49:31.43#ibcon#first serial, iclass 26, count 0 2006.201.09:49:31.43#ibcon#enter sib2, iclass 26, count 0 2006.201.09:49:31.43#ibcon#flushed, iclass 26, count 0 2006.201.09:49:31.43#ibcon#about to write, iclass 26, count 0 2006.201.09:49:31.43#ibcon#wrote, iclass 26, count 0 2006.201.09:49:31.43#ibcon#about to read 3, iclass 26, count 0 2006.201.09:49:31.45#ibcon#read 3, iclass 26, count 0 2006.201.09:49:31.45#ibcon#about to read 4, iclass 26, count 0 2006.201.09:49:31.45#ibcon#read 4, iclass 26, count 0 2006.201.09:49:31.45#ibcon#about to read 5, iclass 26, count 0 2006.201.09:49:31.45#ibcon#read 5, iclass 26, count 0 2006.201.09:49:31.45#ibcon#about to read 6, iclass 26, count 0 2006.201.09:49:31.45#ibcon#read 6, iclass 26, count 0 2006.201.09:49:31.45#ibcon#end of sib2, iclass 26, count 0 2006.201.09:49:31.45#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:49:31.45#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:49:31.45#ibcon#[27=USB\r\n] 2006.201.09:49:31.45#ibcon#*before write, iclass 26, count 0 2006.201.09:49:31.45#ibcon#enter sib2, iclass 26, count 0 2006.201.09:49:31.45#ibcon#flushed, iclass 26, count 0 2006.201.09:49:31.45#ibcon#about to write, iclass 26, count 0 2006.201.09:49:31.45#ibcon#wrote, iclass 26, count 0 2006.201.09:49:31.45#ibcon#about to read 3, iclass 26, count 0 2006.201.09:49:31.48#ibcon#read 3, iclass 26, count 0 2006.201.09:49:31.48#ibcon#about to read 4, iclass 26, count 0 2006.201.09:49:31.48#ibcon#read 4, iclass 26, count 0 2006.201.09:49:31.48#ibcon#about to read 5, iclass 26, count 0 2006.201.09:49:31.48#ibcon#read 5, iclass 26, count 0 2006.201.09:49:31.48#ibcon#about to read 6, iclass 26, count 0 2006.201.09:49:31.48#ibcon#read 6, iclass 26, count 0 2006.201.09:49:31.48#ibcon#end of sib2, iclass 26, count 0 2006.201.09:49:31.48#ibcon#*after write, iclass 26, count 0 2006.201.09:49:31.48#ibcon#*before return 0, iclass 26, count 0 2006.201.09:49:31.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:31.48#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.09:49:31.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:49:31.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:49:31.48$vck44/vblo=3,649.99 2006.201.09:49:31.48#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.09:49:31.48#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.09:49:31.48#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:31.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:31.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:31.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:31.48#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:49:31.48#ibcon#first serial, iclass 28, count 0 2006.201.09:49:31.48#ibcon#enter sib2, iclass 28, count 0 2006.201.09:49:31.48#ibcon#flushed, iclass 28, count 0 2006.201.09:49:31.48#ibcon#about to write, iclass 28, count 0 2006.201.09:49:31.48#ibcon#wrote, iclass 28, count 0 2006.201.09:49:31.48#ibcon#about to read 3, iclass 28, count 0 2006.201.09:49:31.50#ibcon#read 3, iclass 28, count 0 2006.201.09:49:31.50#ibcon#about to read 4, iclass 28, count 0 2006.201.09:49:31.50#ibcon#read 4, iclass 28, count 0 2006.201.09:49:31.50#ibcon#about to read 5, iclass 28, count 0 2006.201.09:49:31.50#ibcon#read 5, iclass 28, count 0 2006.201.09:49:31.50#ibcon#about to read 6, iclass 28, count 0 2006.201.09:49:31.50#ibcon#read 6, iclass 28, count 0 2006.201.09:49:31.50#ibcon#end of sib2, iclass 28, count 0 2006.201.09:49:31.50#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:49:31.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:49:31.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:49:31.50#ibcon#*before write, iclass 28, count 0 2006.201.09:49:31.50#ibcon#enter sib2, iclass 28, count 0 2006.201.09:49:31.50#ibcon#flushed, iclass 28, count 0 2006.201.09:49:31.50#ibcon#about to write, iclass 28, count 0 2006.201.09:49:31.50#ibcon#wrote, iclass 28, count 0 2006.201.09:49:31.50#ibcon#about to read 3, iclass 28, count 0 2006.201.09:49:31.55#ibcon#read 3, iclass 28, count 0 2006.201.09:49:31.55#ibcon#about to read 4, iclass 28, count 0 2006.201.09:49:31.55#ibcon#read 4, iclass 28, count 0 2006.201.09:49:31.55#ibcon#about to read 5, iclass 28, count 0 2006.201.09:49:31.55#ibcon#read 5, iclass 28, count 0 2006.201.09:49:31.55#ibcon#about to read 6, iclass 28, count 0 2006.201.09:49:31.55#ibcon#read 6, iclass 28, count 0 2006.201.09:49:31.55#ibcon#end of sib2, iclass 28, count 0 2006.201.09:49:31.55#ibcon#*after write, iclass 28, count 0 2006.201.09:49:31.55#ibcon#*before return 0, iclass 28, count 0 2006.201.09:49:31.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:31.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.09:49:31.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:49:31.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:49:31.55$vck44/vb=3,4 2006.201.09:49:31.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.09:49:31.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.09:49:31.55#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:31.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:31.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:31.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:31.60#ibcon#enter wrdev, iclass 30, count 2 2006.201.09:49:31.60#ibcon#first serial, iclass 30, count 2 2006.201.09:49:31.60#ibcon#enter sib2, iclass 30, count 2 2006.201.09:49:31.60#ibcon#flushed, iclass 30, count 2 2006.201.09:49:31.60#ibcon#about to write, iclass 30, count 2 2006.201.09:49:31.60#ibcon#wrote, iclass 30, count 2 2006.201.09:49:31.60#ibcon#about to read 3, iclass 30, count 2 2006.201.09:49:31.62#ibcon#read 3, iclass 30, count 2 2006.201.09:49:31.62#ibcon#about to read 4, iclass 30, count 2 2006.201.09:49:31.62#ibcon#read 4, iclass 30, count 2 2006.201.09:49:31.62#ibcon#about to read 5, iclass 30, count 2 2006.201.09:49:31.62#ibcon#read 5, iclass 30, count 2 2006.201.09:49:31.62#ibcon#about to read 6, iclass 30, count 2 2006.201.09:49:31.62#ibcon#read 6, iclass 30, count 2 2006.201.09:49:31.62#ibcon#end of sib2, iclass 30, count 2 2006.201.09:49:31.62#ibcon#*mode == 0, iclass 30, count 2 2006.201.09:49:31.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.09:49:31.62#ibcon#[27=AT03-04\r\n] 2006.201.09:49:31.62#ibcon#*before write, iclass 30, count 2 2006.201.09:49:31.62#ibcon#enter sib2, iclass 30, count 2 2006.201.09:49:31.62#ibcon#flushed, iclass 30, count 2 2006.201.09:49:31.62#ibcon#about to write, iclass 30, count 2 2006.201.09:49:31.62#ibcon#wrote, iclass 30, count 2 2006.201.09:49:31.62#ibcon#about to read 3, iclass 30, count 2 2006.201.09:49:31.65#ibcon#read 3, iclass 30, count 2 2006.201.09:49:31.65#ibcon#about to read 4, iclass 30, count 2 2006.201.09:49:31.65#ibcon#read 4, iclass 30, count 2 2006.201.09:49:31.65#ibcon#about to read 5, iclass 30, count 2 2006.201.09:49:31.65#ibcon#read 5, iclass 30, count 2 2006.201.09:49:31.65#ibcon#about to read 6, iclass 30, count 2 2006.201.09:49:31.65#ibcon#read 6, iclass 30, count 2 2006.201.09:49:31.65#ibcon#end of sib2, iclass 30, count 2 2006.201.09:49:31.65#ibcon#*after write, iclass 30, count 2 2006.201.09:49:31.65#ibcon#*before return 0, iclass 30, count 2 2006.201.09:49:31.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:31.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.09:49:31.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.09:49:31.65#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:31.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:31.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:31.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:31.77#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:49:31.77#ibcon#first serial, iclass 30, count 0 2006.201.09:49:31.77#ibcon#enter sib2, iclass 30, count 0 2006.201.09:49:31.77#ibcon#flushed, iclass 30, count 0 2006.201.09:49:31.77#ibcon#about to write, iclass 30, count 0 2006.201.09:49:31.77#ibcon#wrote, iclass 30, count 0 2006.201.09:49:31.77#ibcon#about to read 3, iclass 30, count 0 2006.201.09:49:31.79#ibcon#read 3, iclass 30, count 0 2006.201.09:49:31.79#ibcon#about to read 4, iclass 30, count 0 2006.201.09:49:31.79#ibcon#read 4, iclass 30, count 0 2006.201.09:49:31.79#ibcon#about to read 5, iclass 30, count 0 2006.201.09:49:31.79#ibcon#read 5, iclass 30, count 0 2006.201.09:49:31.79#ibcon#about to read 6, iclass 30, count 0 2006.201.09:49:31.79#ibcon#read 6, iclass 30, count 0 2006.201.09:49:31.79#ibcon#end of sib2, iclass 30, count 0 2006.201.09:49:31.79#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:49:31.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:49:31.79#ibcon#[27=USB\r\n] 2006.201.09:49:31.79#ibcon#*before write, iclass 30, count 0 2006.201.09:49:31.79#ibcon#enter sib2, iclass 30, count 0 2006.201.09:49:31.79#ibcon#flushed, iclass 30, count 0 2006.201.09:49:31.79#ibcon#about to write, iclass 30, count 0 2006.201.09:49:31.79#ibcon#wrote, iclass 30, count 0 2006.201.09:49:31.79#ibcon#about to read 3, iclass 30, count 0 2006.201.09:49:31.82#ibcon#read 3, iclass 30, count 0 2006.201.09:49:31.82#ibcon#about to read 4, iclass 30, count 0 2006.201.09:49:31.82#ibcon#read 4, iclass 30, count 0 2006.201.09:49:31.82#ibcon#about to read 5, iclass 30, count 0 2006.201.09:49:31.82#ibcon#read 5, iclass 30, count 0 2006.201.09:49:31.82#ibcon#about to read 6, iclass 30, count 0 2006.201.09:49:31.82#ibcon#read 6, iclass 30, count 0 2006.201.09:49:31.82#ibcon#end of sib2, iclass 30, count 0 2006.201.09:49:31.82#ibcon#*after write, iclass 30, count 0 2006.201.09:49:31.82#ibcon#*before return 0, iclass 30, count 0 2006.201.09:49:31.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:31.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.09:49:31.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:49:31.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:49:31.82$vck44/vblo=4,679.99 2006.201.09:49:31.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.09:49:31.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.09:49:31.82#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:31.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:31.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:31.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:31.82#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:49:31.82#ibcon#first serial, iclass 32, count 0 2006.201.09:49:31.82#ibcon#enter sib2, iclass 32, count 0 2006.201.09:49:31.82#ibcon#flushed, iclass 32, count 0 2006.201.09:49:31.82#ibcon#about to write, iclass 32, count 0 2006.201.09:49:31.82#ibcon#wrote, iclass 32, count 0 2006.201.09:49:31.82#ibcon#about to read 3, iclass 32, count 0 2006.201.09:49:31.84#ibcon#read 3, iclass 32, count 0 2006.201.09:49:31.84#ibcon#about to read 4, iclass 32, count 0 2006.201.09:49:31.84#ibcon#read 4, iclass 32, count 0 2006.201.09:49:31.84#ibcon#about to read 5, iclass 32, count 0 2006.201.09:49:31.84#ibcon#read 5, iclass 32, count 0 2006.201.09:49:31.84#ibcon#about to read 6, iclass 32, count 0 2006.201.09:49:31.84#ibcon#read 6, iclass 32, count 0 2006.201.09:49:31.84#ibcon#end of sib2, iclass 32, count 0 2006.201.09:49:31.84#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:49:31.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:49:31.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:49:31.84#ibcon#*before write, iclass 32, count 0 2006.201.09:49:31.84#ibcon#enter sib2, iclass 32, count 0 2006.201.09:49:31.84#ibcon#flushed, iclass 32, count 0 2006.201.09:49:31.84#ibcon#about to write, iclass 32, count 0 2006.201.09:49:31.84#ibcon#wrote, iclass 32, count 0 2006.201.09:49:31.84#ibcon#about to read 3, iclass 32, count 0 2006.201.09:49:31.88#ibcon#read 3, iclass 32, count 0 2006.201.09:49:31.88#ibcon#about to read 4, iclass 32, count 0 2006.201.09:49:31.88#ibcon#read 4, iclass 32, count 0 2006.201.09:49:31.88#ibcon#about to read 5, iclass 32, count 0 2006.201.09:49:31.88#ibcon#read 5, iclass 32, count 0 2006.201.09:49:31.88#ibcon#about to read 6, iclass 32, count 0 2006.201.09:49:31.88#ibcon#read 6, iclass 32, count 0 2006.201.09:49:31.88#ibcon#end of sib2, iclass 32, count 0 2006.201.09:49:31.88#ibcon#*after write, iclass 32, count 0 2006.201.09:49:31.88#ibcon#*before return 0, iclass 32, count 0 2006.201.09:49:31.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:31.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.09:49:31.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:49:31.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:49:31.88$vck44/vb=4,5 2006.201.09:49:31.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.09:49:31.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.09:49:31.88#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:31.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:31.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:31.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:31.94#ibcon#enter wrdev, iclass 34, count 2 2006.201.09:49:31.94#ibcon#first serial, iclass 34, count 2 2006.201.09:49:31.94#ibcon#enter sib2, iclass 34, count 2 2006.201.09:49:31.94#ibcon#flushed, iclass 34, count 2 2006.201.09:49:31.94#ibcon#about to write, iclass 34, count 2 2006.201.09:49:31.94#ibcon#wrote, iclass 34, count 2 2006.201.09:49:31.94#ibcon#about to read 3, iclass 34, count 2 2006.201.09:49:31.96#ibcon#read 3, iclass 34, count 2 2006.201.09:49:31.96#ibcon#about to read 4, iclass 34, count 2 2006.201.09:49:31.96#ibcon#read 4, iclass 34, count 2 2006.201.09:49:31.96#ibcon#about to read 5, iclass 34, count 2 2006.201.09:49:31.96#ibcon#read 5, iclass 34, count 2 2006.201.09:49:31.96#ibcon#about to read 6, iclass 34, count 2 2006.201.09:49:31.96#ibcon#read 6, iclass 34, count 2 2006.201.09:49:31.96#ibcon#end of sib2, iclass 34, count 2 2006.201.09:49:31.96#ibcon#*mode == 0, iclass 34, count 2 2006.201.09:49:31.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.09:49:31.96#ibcon#[27=AT04-05\r\n] 2006.201.09:49:31.96#ibcon#*before write, iclass 34, count 2 2006.201.09:49:31.96#ibcon#enter sib2, iclass 34, count 2 2006.201.09:49:31.96#ibcon#flushed, iclass 34, count 2 2006.201.09:49:31.96#ibcon#about to write, iclass 34, count 2 2006.201.09:49:31.96#ibcon#wrote, iclass 34, count 2 2006.201.09:49:31.96#ibcon#about to read 3, iclass 34, count 2 2006.201.09:49:31.99#ibcon#read 3, iclass 34, count 2 2006.201.09:49:31.99#ibcon#about to read 4, iclass 34, count 2 2006.201.09:49:31.99#ibcon#read 4, iclass 34, count 2 2006.201.09:49:31.99#ibcon#about to read 5, iclass 34, count 2 2006.201.09:49:31.99#ibcon#read 5, iclass 34, count 2 2006.201.09:49:31.99#ibcon#about to read 6, iclass 34, count 2 2006.201.09:49:31.99#ibcon#read 6, iclass 34, count 2 2006.201.09:49:31.99#ibcon#end of sib2, iclass 34, count 2 2006.201.09:49:31.99#ibcon#*after write, iclass 34, count 2 2006.201.09:49:31.99#ibcon#*before return 0, iclass 34, count 2 2006.201.09:49:31.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:31.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:49:31.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.09:49:31.99#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:31.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:32.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:32.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:32.11#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:49:32.11#ibcon#first serial, iclass 34, count 0 2006.201.09:49:32.11#ibcon#enter sib2, iclass 34, count 0 2006.201.09:49:32.11#ibcon#flushed, iclass 34, count 0 2006.201.09:49:32.11#ibcon#about to write, iclass 34, count 0 2006.201.09:49:32.11#ibcon#wrote, iclass 34, count 0 2006.201.09:49:32.11#ibcon#about to read 3, iclass 34, count 0 2006.201.09:49:32.13#ibcon#read 3, iclass 34, count 0 2006.201.09:49:32.13#ibcon#about to read 4, iclass 34, count 0 2006.201.09:49:32.13#ibcon#read 4, iclass 34, count 0 2006.201.09:49:32.13#ibcon#about to read 5, iclass 34, count 0 2006.201.09:49:32.13#ibcon#read 5, iclass 34, count 0 2006.201.09:49:32.13#ibcon#about to read 6, iclass 34, count 0 2006.201.09:49:32.13#ibcon#read 6, iclass 34, count 0 2006.201.09:49:32.13#ibcon#end of sib2, iclass 34, count 0 2006.201.09:49:32.13#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:49:32.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:49:32.13#ibcon#[27=USB\r\n] 2006.201.09:49:32.13#ibcon#*before write, iclass 34, count 0 2006.201.09:49:32.13#ibcon#enter sib2, iclass 34, count 0 2006.201.09:49:32.13#ibcon#flushed, iclass 34, count 0 2006.201.09:49:32.13#ibcon#about to write, iclass 34, count 0 2006.201.09:49:32.13#ibcon#wrote, iclass 34, count 0 2006.201.09:49:32.13#ibcon#about to read 3, iclass 34, count 0 2006.201.09:49:32.16#ibcon#read 3, iclass 34, count 0 2006.201.09:49:32.16#ibcon#about to read 4, iclass 34, count 0 2006.201.09:49:32.16#ibcon#read 4, iclass 34, count 0 2006.201.09:49:32.16#ibcon#about to read 5, iclass 34, count 0 2006.201.09:49:32.16#ibcon#read 5, iclass 34, count 0 2006.201.09:49:32.16#ibcon#about to read 6, iclass 34, count 0 2006.201.09:49:32.16#ibcon#read 6, iclass 34, count 0 2006.201.09:49:32.16#ibcon#end of sib2, iclass 34, count 0 2006.201.09:49:32.16#ibcon#*after write, iclass 34, count 0 2006.201.09:49:32.16#ibcon#*before return 0, iclass 34, count 0 2006.201.09:49:32.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:32.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:49:32.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:49:32.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:49:32.16$vck44/vblo=5,709.99 2006.201.09:49:32.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.09:49:32.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.09:49:32.16#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:32.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:32.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:32.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:32.16#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:49:32.16#ibcon#first serial, iclass 36, count 0 2006.201.09:49:32.16#ibcon#enter sib2, iclass 36, count 0 2006.201.09:49:32.16#ibcon#flushed, iclass 36, count 0 2006.201.09:49:32.16#ibcon#about to write, iclass 36, count 0 2006.201.09:49:32.16#ibcon#wrote, iclass 36, count 0 2006.201.09:49:32.16#ibcon#about to read 3, iclass 36, count 0 2006.201.09:49:32.18#ibcon#read 3, iclass 36, count 0 2006.201.09:49:32.18#ibcon#about to read 4, iclass 36, count 0 2006.201.09:49:32.18#ibcon#read 4, iclass 36, count 0 2006.201.09:49:32.18#ibcon#about to read 5, iclass 36, count 0 2006.201.09:49:32.18#ibcon#read 5, iclass 36, count 0 2006.201.09:49:32.18#ibcon#about to read 6, iclass 36, count 0 2006.201.09:49:32.18#ibcon#read 6, iclass 36, count 0 2006.201.09:49:32.18#ibcon#end of sib2, iclass 36, count 0 2006.201.09:49:32.18#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:49:32.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:49:32.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:49:32.18#ibcon#*before write, iclass 36, count 0 2006.201.09:49:32.18#ibcon#enter sib2, iclass 36, count 0 2006.201.09:49:32.18#ibcon#flushed, iclass 36, count 0 2006.201.09:49:32.18#ibcon#about to write, iclass 36, count 0 2006.201.09:49:32.18#ibcon#wrote, iclass 36, count 0 2006.201.09:49:32.18#ibcon#about to read 3, iclass 36, count 0 2006.201.09:49:32.22#ibcon#read 3, iclass 36, count 0 2006.201.09:49:32.22#ibcon#about to read 4, iclass 36, count 0 2006.201.09:49:32.22#ibcon#read 4, iclass 36, count 0 2006.201.09:49:32.22#ibcon#about to read 5, iclass 36, count 0 2006.201.09:49:32.22#ibcon#read 5, iclass 36, count 0 2006.201.09:49:32.22#ibcon#about to read 6, iclass 36, count 0 2006.201.09:49:32.22#ibcon#read 6, iclass 36, count 0 2006.201.09:49:32.22#ibcon#end of sib2, iclass 36, count 0 2006.201.09:49:32.22#ibcon#*after write, iclass 36, count 0 2006.201.09:49:32.22#ibcon#*before return 0, iclass 36, count 0 2006.201.09:49:32.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:32.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.09:49:32.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:49:32.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:49:32.22$vck44/vb=5,4 2006.201.09:49:32.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.09:49:32.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.09:49:32.22#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:32.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:32.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:32.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:32.28#ibcon#enter wrdev, iclass 38, count 2 2006.201.09:49:32.28#ibcon#first serial, iclass 38, count 2 2006.201.09:49:32.28#ibcon#enter sib2, iclass 38, count 2 2006.201.09:49:32.28#ibcon#flushed, iclass 38, count 2 2006.201.09:49:32.28#ibcon#about to write, iclass 38, count 2 2006.201.09:49:32.28#ibcon#wrote, iclass 38, count 2 2006.201.09:49:32.28#ibcon#about to read 3, iclass 38, count 2 2006.201.09:49:32.30#ibcon#read 3, iclass 38, count 2 2006.201.09:49:32.30#ibcon#about to read 4, iclass 38, count 2 2006.201.09:49:32.30#ibcon#read 4, iclass 38, count 2 2006.201.09:49:32.30#ibcon#about to read 5, iclass 38, count 2 2006.201.09:49:32.30#ibcon#read 5, iclass 38, count 2 2006.201.09:49:32.30#ibcon#about to read 6, iclass 38, count 2 2006.201.09:49:32.30#ibcon#read 6, iclass 38, count 2 2006.201.09:49:32.30#ibcon#end of sib2, iclass 38, count 2 2006.201.09:49:32.30#ibcon#*mode == 0, iclass 38, count 2 2006.201.09:49:32.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.09:49:32.30#ibcon#[27=AT05-04\r\n] 2006.201.09:49:32.30#ibcon#*before write, iclass 38, count 2 2006.201.09:49:32.30#ibcon#enter sib2, iclass 38, count 2 2006.201.09:49:32.30#ibcon#flushed, iclass 38, count 2 2006.201.09:49:32.30#ibcon#about to write, iclass 38, count 2 2006.201.09:49:32.30#ibcon#wrote, iclass 38, count 2 2006.201.09:49:32.30#ibcon#about to read 3, iclass 38, count 2 2006.201.09:49:32.33#ibcon#read 3, iclass 38, count 2 2006.201.09:49:32.33#ibcon#about to read 4, iclass 38, count 2 2006.201.09:49:32.33#ibcon#read 4, iclass 38, count 2 2006.201.09:49:32.33#ibcon#about to read 5, iclass 38, count 2 2006.201.09:49:32.33#ibcon#read 5, iclass 38, count 2 2006.201.09:49:32.33#ibcon#about to read 6, iclass 38, count 2 2006.201.09:49:32.33#ibcon#read 6, iclass 38, count 2 2006.201.09:49:32.33#ibcon#end of sib2, iclass 38, count 2 2006.201.09:49:32.33#ibcon#*after write, iclass 38, count 2 2006.201.09:49:32.33#ibcon#*before return 0, iclass 38, count 2 2006.201.09:49:32.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:32.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.09:49:32.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.09:49:32.33#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:32.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:32.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:32.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:32.45#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:49:32.45#ibcon#first serial, iclass 38, count 0 2006.201.09:49:32.45#ibcon#enter sib2, iclass 38, count 0 2006.201.09:49:32.45#ibcon#flushed, iclass 38, count 0 2006.201.09:49:32.45#ibcon#about to write, iclass 38, count 0 2006.201.09:49:32.45#ibcon#wrote, iclass 38, count 0 2006.201.09:49:32.45#ibcon#about to read 3, iclass 38, count 0 2006.201.09:49:32.47#ibcon#read 3, iclass 38, count 0 2006.201.09:49:32.47#ibcon#about to read 4, iclass 38, count 0 2006.201.09:49:32.47#ibcon#read 4, iclass 38, count 0 2006.201.09:49:32.47#ibcon#about to read 5, iclass 38, count 0 2006.201.09:49:32.47#ibcon#read 5, iclass 38, count 0 2006.201.09:49:32.47#ibcon#about to read 6, iclass 38, count 0 2006.201.09:49:32.47#ibcon#read 6, iclass 38, count 0 2006.201.09:49:32.47#ibcon#end of sib2, iclass 38, count 0 2006.201.09:49:32.47#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:49:32.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:49:32.47#ibcon#[27=USB\r\n] 2006.201.09:49:32.47#ibcon#*before write, iclass 38, count 0 2006.201.09:49:32.47#ibcon#enter sib2, iclass 38, count 0 2006.201.09:49:32.47#ibcon#flushed, iclass 38, count 0 2006.201.09:49:32.47#ibcon#about to write, iclass 38, count 0 2006.201.09:49:32.47#ibcon#wrote, iclass 38, count 0 2006.201.09:49:32.47#ibcon#about to read 3, iclass 38, count 0 2006.201.09:49:32.50#ibcon#read 3, iclass 38, count 0 2006.201.09:49:32.50#ibcon#about to read 4, iclass 38, count 0 2006.201.09:49:32.50#ibcon#read 4, iclass 38, count 0 2006.201.09:49:32.50#ibcon#about to read 5, iclass 38, count 0 2006.201.09:49:32.50#ibcon#read 5, iclass 38, count 0 2006.201.09:49:32.50#ibcon#about to read 6, iclass 38, count 0 2006.201.09:49:32.50#ibcon#read 6, iclass 38, count 0 2006.201.09:49:32.50#ibcon#end of sib2, iclass 38, count 0 2006.201.09:49:32.50#ibcon#*after write, iclass 38, count 0 2006.201.09:49:32.50#ibcon#*before return 0, iclass 38, count 0 2006.201.09:49:32.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:32.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.09:49:32.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:49:32.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:49:32.50$vck44/vblo=6,719.99 2006.201.09:49:32.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.09:49:32.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.09:49:32.50#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:32.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:32.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:32.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:32.50#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:49:32.50#ibcon#first serial, iclass 40, count 0 2006.201.09:49:32.50#ibcon#enter sib2, iclass 40, count 0 2006.201.09:49:32.50#ibcon#flushed, iclass 40, count 0 2006.201.09:49:32.50#ibcon#about to write, iclass 40, count 0 2006.201.09:49:32.50#ibcon#wrote, iclass 40, count 0 2006.201.09:49:32.50#ibcon#about to read 3, iclass 40, count 0 2006.201.09:49:32.52#ibcon#read 3, iclass 40, count 0 2006.201.09:49:32.52#ibcon#about to read 4, iclass 40, count 0 2006.201.09:49:32.52#ibcon#read 4, iclass 40, count 0 2006.201.09:49:32.52#ibcon#about to read 5, iclass 40, count 0 2006.201.09:49:32.52#ibcon#read 5, iclass 40, count 0 2006.201.09:49:32.52#ibcon#about to read 6, iclass 40, count 0 2006.201.09:49:32.52#ibcon#read 6, iclass 40, count 0 2006.201.09:49:32.52#ibcon#end of sib2, iclass 40, count 0 2006.201.09:49:32.52#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:49:32.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:49:32.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:49:32.52#ibcon#*before write, iclass 40, count 0 2006.201.09:49:32.52#ibcon#enter sib2, iclass 40, count 0 2006.201.09:49:32.52#ibcon#flushed, iclass 40, count 0 2006.201.09:49:32.52#ibcon#about to write, iclass 40, count 0 2006.201.09:49:32.52#ibcon#wrote, iclass 40, count 0 2006.201.09:49:32.52#ibcon#about to read 3, iclass 40, count 0 2006.201.09:49:32.57#ibcon#read 3, iclass 40, count 0 2006.201.09:49:32.57#ibcon#about to read 4, iclass 40, count 0 2006.201.09:49:32.57#ibcon#read 4, iclass 40, count 0 2006.201.09:49:32.57#ibcon#about to read 5, iclass 40, count 0 2006.201.09:49:32.57#ibcon#read 5, iclass 40, count 0 2006.201.09:49:32.57#ibcon#about to read 6, iclass 40, count 0 2006.201.09:49:32.57#ibcon#read 6, iclass 40, count 0 2006.201.09:49:32.57#ibcon#end of sib2, iclass 40, count 0 2006.201.09:49:32.57#ibcon#*after write, iclass 40, count 0 2006.201.09:49:32.57#ibcon#*before return 0, iclass 40, count 0 2006.201.09:49:32.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:32.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.09:49:32.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:49:32.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:49:32.57$vck44/vb=6,4 2006.201.09:49:32.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.09:49:32.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.09:49:32.57#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:32.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:32.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:32.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:32.62#ibcon#enter wrdev, iclass 4, count 2 2006.201.09:49:32.62#ibcon#first serial, iclass 4, count 2 2006.201.09:49:32.62#ibcon#enter sib2, iclass 4, count 2 2006.201.09:49:32.62#ibcon#flushed, iclass 4, count 2 2006.201.09:49:32.62#ibcon#about to write, iclass 4, count 2 2006.201.09:49:32.62#ibcon#wrote, iclass 4, count 2 2006.201.09:49:32.62#ibcon#about to read 3, iclass 4, count 2 2006.201.09:49:32.64#ibcon#read 3, iclass 4, count 2 2006.201.09:49:32.64#ibcon#about to read 4, iclass 4, count 2 2006.201.09:49:32.64#ibcon#read 4, iclass 4, count 2 2006.201.09:49:32.64#ibcon#about to read 5, iclass 4, count 2 2006.201.09:49:32.64#ibcon#read 5, iclass 4, count 2 2006.201.09:49:32.64#ibcon#about to read 6, iclass 4, count 2 2006.201.09:49:32.64#ibcon#read 6, iclass 4, count 2 2006.201.09:49:32.64#ibcon#end of sib2, iclass 4, count 2 2006.201.09:49:32.64#ibcon#*mode == 0, iclass 4, count 2 2006.201.09:49:32.64#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.09:49:32.64#ibcon#[27=AT06-04\r\n] 2006.201.09:49:32.64#ibcon#*before write, iclass 4, count 2 2006.201.09:49:32.64#ibcon#enter sib2, iclass 4, count 2 2006.201.09:49:32.64#ibcon#flushed, iclass 4, count 2 2006.201.09:49:32.64#ibcon#about to write, iclass 4, count 2 2006.201.09:49:32.64#ibcon#wrote, iclass 4, count 2 2006.201.09:49:32.64#ibcon#about to read 3, iclass 4, count 2 2006.201.09:49:32.67#ibcon#read 3, iclass 4, count 2 2006.201.09:49:32.67#ibcon#about to read 4, iclass 4, count 2 2006.201.09:49:32.67#ibcon#read 4, iclass 4, count 2 2006.201.09:49:32.67#ibcon#about to read 5, iclass 4, count 2 2006.201.09:49:32.67#ibcon#read 5, iclass 4, count 2 2006.201.09:49:32.67#ibcon#about to read 6, iclass 4, count 2 2006.201.09:49:32.67#ibcon#read 6, iclass 4, count 2 2006.201.09:49:32.67#ibcon#end of sib2, iclass 4, count 2 2006.201.09:49:32.67#ibcon#*after write, iclass 4, count 2 2006.201.09:49:32.67#ibcon#*before return 0, iclass 4, count 2 2006.201.09:49:32.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:32.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.09:49:32.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.09:49:32.67#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:32.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:32.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:32.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:32.79#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:49:32.79#ibcon#first serial, iclass 4, count 0 2006.201.09:49:32.79#ibcon#enter sib2, iclass 4, count 0 2006.201.09:49:32.79#ibcon#flushed, iclass 4, count 0 2006.201.09:49:32.79#ibcon#about to write, iclass 4, count 0 2006.201.09:49:32.79#ibcon#wrote, iclass 4, count 0 2006.201.09:49:32.79#ibcon#about to read 3, iclass 4, count 0 2006.201.09:49:32.81#ibcon#read 3, iclass 4, count 0 2006.201.09:49:32.81#ibcon#about to read 4, iclass 4, count 0 2006.201.09:49:32.81#ibcon#read 4, iclass 4, count 0 2006.201.09:49:32.81#ibcon#about to read 5, iclass 4, count 0 2006.201.09:49:32.81#ibcon#read 5, iclass 4, count 0 2006.201.09:49:32.81#ibcon#about to read 6, iclass 4, count 0 2006.201.09:49:32.81#ibcon#read 6, iclass 4, count 0 2006.201.09:49:32.81#ibcon#end of sib2, iclass 4, count 0 2006.201.09:49:32.81#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:49:32.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:49:32.81#ibcon#[27=USB\r\n] 2006.201.09:49:32.81#ibcon#*before write, iclass 4, count 0 2006.201.09:49:32.81#ibcon#enter sib2, iclass 4, count 0 2006.201.09:49:32.81#ibcon#flushed, iclass 4, count 0 2006.201.09:49:32.81#ibcon#about to write, iclass 4, count 0 2006.201.09:49:32.81#ibcon#wrote, iclass 4, count 0 2006.201.09:49:32.81#ibcon#about to read 3, iclass 4, count 0 2006.201.09:49:32.84#ibcon#read 3, iclass 4, count 0 2006.201.09:49:32.84#ibcon#about to read 4, iclass 4, count 0 2006.201.09:49:32.84#ibcon#read 4, iclass 4, count 0 2006.201.09:49:32.84#ibcon#about to read 5, iclass 4, count 0 2006.201.09:49:32.84#ibcon#read 5, iclass 4, count 0 2006.201.09:49:32.84#ibcon#about to read 6, iclass 4, count 0 2006.201.09:49:32.84#ibcon#read 6, iclass 4, count 0 2006.201.09:49:32.84#ibcon#end of sib2, iclass 4, count 0 2006.201.09:49:32.84#ibcon#*after write, iclass 4, count 0 2006.201.09:49:32.84#ibcon#*before return 0, iclass 4, count 0 2006.201.09:49:32.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:32.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.09:49:32.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:49:32.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:49:32.84$vck44/vblo=7,734.99 2006.201.09:49:32.84#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.09:49:32.84#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.09:49:32.84#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:32.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:32.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:32.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:32.84#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:49:32.84#ibcon#first serial, iclass 6, count 0 2006.201.09:49:32.84#ibcon#enter sib2, iclass 6, count 0 2006.201.09:49:32.84#ibcon#flushed, iclass 6, count 0 2006.201.09:49:32.84#ibcon#about to write, iclass 6, count 0 2006.201.09:49:32.84#ibcon#wrote, iclass 6, count 0 2006.201.09:49:32.84#ibcon#about to read 3, iclass 6, count 0 2006.201.09:49:32.86#ibcon#read 3, iclass 6, count 0 2006.201.09:49:32.86#ibcon#about to read 4, iclass 6, count 0 2006.201.09:49:32.86#ibcon#read 4, iclass 6, count 0 2006.201.09:49:32.86#ibcon#about to read 5, iclass 6, count 0 2006.201.09:49:32.86#ibcon#read 5, iclass 6, count 0 2006.201.09:49:32.86#ibcon#about to read 6, iclass 6, count 0 2006.201.09:49:32.86#ibcon#read 6, iclass 6, count 0 2006.201.09:49:32.86#ibcon#end of sib2, iclass 6, count 0 2006.201.09:49:32.86#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:49:32.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:49:32.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:49:32.86#ibcon#*before write, iclass 6, count 0 2006.201.09:49:32.86#ibcon#enter sib2, iclass 6, count 0 2006.201.09:49:32.86#ibcon#flushed, iclass 6, count 0 2006.201.09:49:32.86#ibcon#about to write, iclass 6, count 0 2006.201.09:49:32.86#ibcon#wrote, iclass 6, count 0 2006.201.09:49:32.86#ibcon#about to read 3, iclass 6, count 0 2006.201.09:49:32.90#ibcon#read 3, iclass 6, count 0 2006.201.09:49:32.90#ibcon#about to read 4, iclass 6, count 0 2006.201.09:49:32.90#ibcon#read 4, iclass 6, count 0 2006.201.09:49:32.90#ibcon#about to read 5, iclass 6, count 0 2006.201.09:49:32.90#ibcon#read 5, iclass 6, count 0 2006.201.09:49:32.90#ibcon#about to read 6, iclass 6, count 0 2006.201.09:49:32.90#ibcon#read 6, iclass 6, count 0 2006.201.09:49:32.90#ibcon#end of sib2, iclass 6, count 0 2006.201.09:49:32.90#ibcon#*after write, iclass 6, count 0 2006.201.09:49:32.90#ibcon#*before return 0, iclass 6, count 0 2006.201.09:49:32.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:32.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.09:49:32.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:49:32.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:49:32.90$vck44/vb=7,4 2006.201.09:49:32.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.09:49:32.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.09:49:32.90#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:32.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:32.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:32.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:32.96#ibcon#enter wrdev, iclass 10, count 2 2006.201.09:49:32.96#ibcon#first serial, iclass 10, count 2 2006.201.09:49:32.96#ibcon#enter sib2, iclass 10, count 2 2006.201.09:49:32.96#ibcon#flushed, iclass 10, count 2 2006.201.09:49:32.96#ibcon#about to write, iclass 10, count 2 2006.201.09:49:32.96#ibcon#wrote, iclass 10, count 2 2006.201.09:49:32.96#ibcon#about to read 3, iclass 10, count 2 2006.201.09:49:32.98#ibcon#read 3, iclass 10, count 2 2006.201.09:49:32.98#ibcon#about to read 4, iclass 10, count 2 2006.201.09:49:32.98#ibcon#read 4, iclass 10, count 2 2006.201.09:49:32.98#ibcon#about to read 5, iclass 10, count 2 2006.201.09:49:32.98#ibcon#read 5, iclass 10, count 2 2006.201.09:49:32.98#ibcon#about to read 6, iclass 10, count 2 2006.201.09:49:32.98#ibcon#read 6, iclass 10, count 2 2006.201.09:49:32.98#ibcon#end of sib2, iclass 10, count 2 2006.201.09:49:32.98#ibcon#*mode == 0, iclass 10, count 2 2006.201.09:49:32.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.09:49:32.98#ibcon#[27=AT07-04\r\n] 2006.201.09:49:32.98#ibcon#*before write, iclass 10, count 2 2006.201.09:49:32.98#ibcon#enter sib2, iclass 10, count 2 2006.201.09:49:32.98#ibcon#flushed, iclass 10, count 2 2006.201.09:49:32.98#ibcon#about to write, iclass 10, count 2 2006.201.09:49:32.98#ibcon#wrote, iclass 10, count 2 2006.201.09:49:32.98#ibcon#about to read 3, iclass 10, count 2 2006.201.09:49:33.01#ibcon#read 3, iclass 10, count 2 2006.201.09:49:33.01#ibcon#about to read 4, iclass 10, count 2 2006.201.09:49:33.01#ibcon#read 4, iclass 10, count 2 2006.201.09:49:33.01#ibcon#about to read 5, iclass 10, count 2 2006.201.09:49:33.01#ibcon#read 5, iclass 10, count 2 2006.201.09:49:33.01#ibcon#about to read 6, iclass 10, count 2 2006.201.09:49:33.01#ibcon#read 6, iclass 10, count 2 2006.201.09:49:33.01#ibcon#end of sib2, iclass 10, count 2 2006.201.09:49:33.01#ibcon#*after write, iclass 10, count 2 2006.201.09:49:33.01#ibcon#*before return 0, iclass 10, count 2 2006.201.09:49:33.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:33.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.09:49:33.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.09:49:33.01#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:33.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:33.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:33.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:33.13#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:49:33.13#ibcon#first serial, iclass 10, count 0 2006.201.09:49:33.13#ibcon#enter sib2, iclass 10, count 0 2006.201.09:49:33.13#ibcon#flushed, iclass 10, count 0 2006.201.09:49:33.13#ibcon#about to write, iclass 10, count 0 2006.201.09:49:33.13#ibcon#wrote, iclass 10, count 0 2006.201.09:49:33.13#ibcon#about to read 3, iclass 10, count 0 2006.201.09:49:33.15#ibcon#read 3, iclass 10, count 0 2006.201.09:49:33.15#ibcon#about to read 4, iclass 10, count 0 2006.201.09:49:33.15#ibcon#read 4, iclass 10, count 0 2006.201.09:49:33.15#ibcon#about to read 5, iclass 10, count 0 2006.201.09:49:33.15#ibcon#read 5, iclass 10, count 0 2006.201.09:49:33.15#ibcon#about to read 6, iclass 10, count 0 2006.201.09:49:33.15#ibcon#read 6, iclass 10, count 0 2006.201.09:49:33.15#ibcon#end of sib2, iclass 10, count 0 2006.201.09:49:33.15#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:49:33.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:49:33.15#ibcon#[27=USB\r\n] 2006.201.09:49:33.15#ibcon#*before write, iclass 10, count 0 2006.201.09:49:33.15#ibcon#enter sib2, iclass 10, count 0 2006.201.09:49:33.15#ibcon#flushed, iclass 10, count 0 2006.201.09:49:33.15#ibcon#about to write, iclass 10, count 0 2006.201.09:49:33.15#ibcon#wrote, iclass 10, count 0 2006.201.09:49:33.15#ibcon#about to read 3, iclass 10, count 0 2006.201.09:49:33.18#ibcon#read 3, iclass 10, count 0 2006.201.09:49:33.18#ibcon#about to read 4, iclass 10, count 0 2006.201.09:49:33.18#ibcon#read 4, iclass 10, count 0 2006.201.09:49:33.18#ibcon#about to read 5, iclass 10, count 0 2006.201.09:49:33.18#ibcon#read 5, iclass 10, count 0 2006.201.09:49:33.18#ibcon#about to read 6, iclass 10, count 0 2006.201.09:49:33.18#ibcon#read 6, iclass 10, count 0 2006.201.09:49:33.18#ibcon#end of sib2, iclass 10, count 0 2006.201.09:49:33.18#ibcon#*after write, iclass 10, count 0 2006.201.09:49:33.18#ibcon#*before return 0, iclass 10, count 0 2006.201.09:49:33.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:33.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.09:49:33.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:49:33.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:49:33.18$vck44/vblo=8,744.99 2006.201.09:49:33.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.09:49:33.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.09:49:33.18#ibcon#ireg 17 cls_cnt 0 2006.201.09:49:33.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:33.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:33.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:33.18#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:49:33.18#ibcon#first serial, iclass 12, count 0 2006.201.09:49:33.18#ibcon#enter sib2, iclass 12, count 0 2006.201.09:49:33.18#ibcon#flushed, iclass 12, count 0 2006.201.09:49:33.18#ibcon#about to write, iclass 12, count 0 2006.201.09:49:33.18#ibcon#wrote, iclass 12, count 0 2006.201.09:49:33.18#ibcon#about to read 3, iclass 12, count 0 2006.201.09:49:33.20#ibcon#read 3, iclass 12, count 0 2006.201.09:49:33.20#ibcon#about to read 4, iclass 12, count 0 2006.201.09:49:33.20#ibcon#read 4, iclass 12, count 0 2006.201.09:49:33.20#ibcon#about to read 5, iclass 12, count 0 2006.201.09:49:33.20#ibcon#read 5, iclass 12, count 0 2006.201.09:49:33.20#ibcon#about to read 6, iclass 12, count 0 2006.201.09:49:33.20#ibcon#read 6, iclass 12, count 0 2006.201.09:49:33.20#ibcon#end of sib2, iclass 12, count 0 2006.201.09:49:33.20#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:49:33.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:49:33.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:49:33.20#ibcon#*before write, iclass 12, count 0 2006.201.09:49:33.20#ibcon#enter sib2, iclass 12, count 0 2006.201.09:49:33.20#ibcon#flushed, iclass 12, count 0 2006.201.09:49:33.20#ibcon#about to write, iclass 12, count 0 2006.201.09:49:33.20#ibcon#wrote, iclass 12, count 0 2006.201.09:49:33.20#ibcon#about to read 3, iclass 12, count 0 2006.201.09:49:33.25#ibcon#read 3, iclass 12, count 0 2006.201.09:49:33.25#ibcon#about to read 4, iclass 12, count 0 2006.201.09:49:33.25#ibcon#read 4, iclass 12, count 0 2006.201.09:49:33.25#ibcon#about to read 5, iclass 12, count 0 2006.201.09:49:33.25#ibcon#read 5, iclass 12, count 0 2006.201.09:49:33.25#ibcon#about to read 6, iclass 12, count 0 2006.201.09:49:33.25#ibcon#read 6, iclass 12, count 0 2006.201.09:49:33.25#ibcon#end of sib2, iclass 12, count 0 2006.201.09:49:33.25#ibcon#*after write, iclass 12, count 0 2006.201.09:49:33.25#ibcon#*before return 0, iclass 12, count 0 2006.201.09:49:33.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:33.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.09:49:33.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:49:33.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:49:33.25$vck44/vb=8,4 2006.201.09:49:33.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.09:49:33.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.09:49:33.25#ibcon#ireg 11 cls_cnt 2 2006.201.09:49:33.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:33.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:33.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:33.30#ibcon#enter wrdev, iclass 14, count 2 2006.201.09:49:33.30#ibcon#first serial, iclass 14, count 2 2006.201.09:49:33.30#ibcon#enter sib2, iclass 14, count 2 2006.201.09:49:33.30#ibcon#flushed, iclass 14, count 2 2006.201.09:49:33.30#ibcon#about to write, iclass 14, count 2 2006.201.09:49:33.30#ibcon#wrote, iclass 14, count 2 2006.201.09:49:33.30#ibcon#about to read 3, iclass 14, count 2 2006.201.09:49:33.32#ibcon#read 3, iclass 14, count 2 2006.201.09:49:33.32#ibcon#about to read 4, iclass 14, count 2 2006.201.09:49:33.32#ibcon#read 4, iclass 14, count 2 2006.201.09:49:33.32#ibcon#about to read 5, iclass 14, count 2 2006.201.09:49:33.32#ibcon#read 5, iclass 14, count 2 2006.201.09:49:33.32#ibcon#about to read 6, iclass 14, count 2 2006.201.09:49:33.32#ibcon#read 6, iclass 14, count 2 2006.201.09:49:33.32#ibcon#end of sib2, iclass 14, count 2 2006.201.09:49:33.32#ibcon#*mode == 0, iclass 14, count 2 2006.201.09:49:33.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.09:49:33.32#ibcon#[27=AT08-04\r\n] 2006.201.09:49:33.32#ibcon#*before write, iclass 14, count 2 2006.201.09:49:33.32#ibcon#enter sib2, iclass 14, count 2 2006.201.09:49:33.32#ibcon#flushed, iclass 14, count 2 2006.201.09:49:33.32#ibcon#about to write, iclass 14, count 2 2006.201.09:49:33.32#ibcon#wrote, iclass 14, count 2 2006.201.09:49:33.32#ibcon#about to read 3, iclass 14, count 2 2006.201.09:49:33.35#ibcon#read 3, iclass 14, count 2 2006.201.09:49:33.35#ibcon#about to read 4, iclass 14, count 2 2006.201.09:49:33.35#ibcon#read 4, iclass 14, count 2 2006.201.09:49:33.35#ibcon#about to read 5, iclass 14, count 2 2006.201.09:49:33.35#ibcon#read 5, iclass 14, count 2 2006.201.09:49:33.35#ibcon#about to read 6, iclass 14, count 2 2006.201.09:49:33.35#ibcon#read 6, iclass 14, count 2 2006.201.09:49:33.35#ibcon#end of sib2, iclass 14, count 2 2006.201.09:49:33.35#ibcon#*after write, iclass 14, count 2 2006.201.09:49:33.35#ibcon#*before return 0, iclass 14, count 2 2006.201.09:49:33.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:33.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.09:49:33.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.09:49:33.35#ibcon#ireg 7 cls_cnt 0 2006.201.09:49:33.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:33.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:33.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:33.47#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:49:33.47#ibcon#first serial, iclass 14, count 0 2006.201.09:49:33.47#ibcon#enter sib2, iclass 14, count 0 2006.201.09:49:33.47#ibcon#flushed, iclass 14, count 0 2006.201.09:49:33.47#ibcon#about to write, iclass 14, count 0 2006.201.09:49:33.47#ibcon#wrote, iclass 14, count 0 2006.201.09:49:33.47#ibcon#about to read 3, iclass 14, count 0 2006.201.09:49:33.49#ibcon#read 3, iclass 14, count 0 2006.201.09:49:33.49#ibcon#about to read 4, iclass 14, count 0 2006.201.09:49:33.49#ibcon#read 4, iclass 14, count 0 2006.201.09:49:33.49#ibcon#about to read 5, iclass 14, count 0 2006.201.09:49:33.49#ibcon#read 5, iclass 14, count 0 2006.201.09:49:33.49#ibcon#about to read 6, iclass 14, count 0 2006.201.09:49:33.49#ibcon#read 6, iclass 14, count 0 2006.201.09:49:33.49#ibcon#end of sib2, iclass 14, count 0 2006.201.09:49:33.49#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:49:33.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:49:33.49#ibcon#[27=USB\r\n] 2006.201.09:49:33.49#ibcon#*before write, iclass 14, count 0 2006.201.09:49:33.49#ibcon#enter sib2, iclass 14, count 0 2006.201.09:49:33.49#ibcon#flushed, iclass 14, count 0 2006.201.09:49:33.49#ibcon#about to write, iclass 14, count 0 2006.201.09:49:33.49#ibcon#wrote, iclass 14, count 0 2006.201.09:49:33.49#ibcon#about to read 3, iclass 14, count 0 2006.201.09:49:33.52#ibcon#read 3, iclass 14, count 0 2006.201.09:49:33.52#ibcon#about to read 4, iclass 14, count 0 2006.201.09:49:33.52#ibcon#read 4, iclass 14, count 0 2006.201.09:49:33.52#ibcon#about to read 5, iclass 14, count 0 2006.201.09:49:33.52#ibcon#read 5, iclass 14, count 0 2006.201.09:49:33.52#ibcon#about to read 6, iclass 14, count 0 2006.201.09:49:33.52#ibcon#read 6, iclass 14, count 0 2006.201.09:49:33.52#ibcon#end of sib2, iclass 14, count 0 2006.201.09:49:33.52#ibcon#*after write, iclass 14, count 0 2006.201.09:49:33.52#ibcon#*before return 0, iclass 14, count 0 2006.201.09:49:33.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:33.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.09:49:33.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:49:33.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:49:33.52$vck44/vabw=wide 2006.201.09:49:33.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.09:49:33.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.09:49:33.52#ibcon#ireg 8 cls_cnt 0 2006.201.09:49:33.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:33.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:33.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:33.52#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:49:33.52#ibcon#first serial, iclass 16, count 0 2006.201.09:49:33.52#ibcon#enter sib2, iclass 16, count 0 2006.201.09:49:33.52#ibcon#flushed, iclass 16, count 0 2006.201.09:49:33.52#ibcon#about to write, iclass 16, count 0 2006.201.09:49:33.52#ibcon#wrote, iclass 16, count 0 2006.201.09:49:33.52#ibcon#about to read 3, iclass 16, count 0 2006.201.09:49:33.54#ibcon#read 3, iclass 16, count 0 2006.201.09:49:33.54#ibcon#about to read 4, iclass 16, count 0 2006.201.09:49:33.54#ibcon#read 4, iclass 16, count 0 2006.201.09:49:33.54#ibcon#about to read 5, iclass 16, count 0 2006.201.09:49:33.54#ibcon#read 5, iclass 16, count 0 2006.201.09:49:33.54#ibcon#about to read 6, iclass 16, count 0 2006.201.09:49:33.54#ibcon#read 6, iclass 16, count 0 2006.201.09:49:33.54#ibcon#end of sib2, iclass 16, count 0 2006.201.09:49:33.54#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:49:33.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:49:33.54#ibcon#[25=BW32\r\n] 2006.201.09:49:33.54#ibcon#*before write, iclass 16, count 0 2006.201.09:49:33.54#ibcon#enter sib2, iclass 16, count 0 2006.201.09:49:33.54#ibcon#flushed, iclass 16, count 0 2006.201.09:49:33.54#ibcon#about to write, iclass 16, count 0 2006.201.09:49:33.54#ibcon#wrote, iclass 16, count 0 2006.201.09:49:33.54#ibcon#about to read 3, iclass 16, count 0 2006.201.09:49:33.58#ibcon#read 3, iclass 16, count 0 2006.201.09:49:33.58#ibcon#about to read 4, iclass 16, count 0 2006.201.09:49:33.58#ibcon#read 4, iclass 16, count 0 2006.201.09:49:33.58#ibcon#about to read 5, iclass 16, count 0 2006.201.09:49:33.58#ibcon#read 5, iclass 16, count 0 2006.201.09:49:33.58#ibcon#about to read 6, iclass 16, count 0 2006.201.09:49:33.58#ibcon#read 6, iclass 16, count 0 2006.201.09:49:33.58#ibcon#end of sib2, iclass 16, count 0 2006.201.09:49:33.58#ibcon#*after write, iclass 16, count 0 2006.201.09:49:33.58#ibcon#*before return 0, iclass 16, count 0 2006.201.09:49:33.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:33.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:49:33.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:49:33.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:49:33.58$vck44/vbbw=wide 2006.201.09:49:33.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.09:49:33.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.09:49:33.58#ibcon#ireg 8 cls_cnt 0 2006.201.09:49:33.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:49:33.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:49:33.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:49:33.64#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:49:33.64#ibcon#first serial, iclass 18, count 0 2006.201.09:49:33.64#ibcon#enter sib2, iclass 18, count 0 2006.201.09:49:33.64#ibcon#flushed, iclass 18, count 0 2006.201.09:49:33.64#ibcon#about to write, iclass 18, count 0 2006.201.09:49:33.64#ibcon#wrote, iclass 18, count 0 2006.201.09:49:33.64#ibcon#about to read 3, iclass 18, count 0 2006.201.09:49:33.66#ibcon#read 3, iclass 18, count 0 2006.201.09:49:33.66#ibcon#about to read 4, iclass 18, count 0 2006.201.09:49:33.66#ibcon#read 4, iclass 18, count 0 2006.201.09:49:33.66#ibcon#about to read 5, iclass 18, count 0 2006.201.09:49:33.66#ibcon#read 5, iclass 18, count 0 2006.201.09:49:33.66#ibcon#about to read 6, iclass 18, count 0 2006.201.09:49:33.66#ibcon#read 6, iclass 18, count 0 2006.201.09:49:33.66#ibcon#end of sib2, iclass 18, count 0 2006.201.09:49:33.66#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:49:33.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:49:33.66#ibcon#[27=BW32\r\n] 2006.201.09:49:33.66#ibcon#*before write, iclass 18, count 0 2006.201.09:49:33.66#ibcon#enter sib2, iclass 18, count 0 2006.201.09:49:33.66#ibcon#flushed, iclass 18, count 0 2006.201.09:49:33.66#ibcon#about to write, iclass 18, count 0 2006.201.09:49:33.66#ibcon#wrote, iclass 18, count 0 2006.201.09:49:33.66#ibcon#about to read 3, iclass 18, count 0 2006.201.09:49:33.69#ibcon#read 3, iclass 18, count 0 2006.201.09:49:33.69#ibcon#about to read 4, iclass 18, count 0 2006.201.09:49:33.69#ibcon#read 4, iclass 18, count 0 2006.201.09:49:33.69#ibcon#about to read 5, iclass 18, count 0 2006.201.09:49:33.69#ibcon#read 5, iclass 18, count 0 2006.201.09:49:33.69#ibcon#about to read 6, iclass 18, count 0 2006.201.09:49:33.69#ibcon#read 6, iclass 18, count 0 2006.201.09:49:33.69#ibcon#end of sib2, iclass 18, count 0 2006.201.09:49:33.69#ibcon#*after write, iclass 18, count 0 2006.201.09:49:33.69#ibcon#*before return 0, iclass 18, count 0 2006.201.09:49:33.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:49:33.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:49:33.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:49:33.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:49:33.69$setupk4/ifdk4 2006.201.09:49:33.69$ifdk4/lo= 2006.201.09:49:33.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:49:33.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:49:33.69$ifdk4/patch= 2006.201.09:49:33.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:49:33.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:49:33.69$setupk4/!*+20s 2006.201.09:49:34.21#abcon#<5=/05 2.8 5.1 22.37 941003.7\r\n> 2006.201.09:49:34.23#abcon#{5=INTERFACE CLEAR} 2006.201.09:49:34.29#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:49:44.38#abcon#<5=/05 2.8 5.1 22.37 941003.6\r\n> 2006.201.09:49:44.40#abcon#{5=INTERFACE CLEAR} 2006.201.09:49:44.46#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:49:48.16$setupk4/"tpicd 2006.201.09:49:48.16$setupk4/echo=off 2006.201.09:49:48.16$setupk4/xlog=off 2006.201.09:49:48.16:!2006.201.09:50:37 2006.201.09:49:49.14#trakl#Source acquired 2006.201.09:49:49.14#flagr#flagr/antenna,acquired 2006.201.09:50:37.00:preob 2006.201.09:50:38.13/onsource/TRACKING 2006.201.09:50:38.13:!2006.201.09:50:47 2006.201.09:50:47.00:"tape 2006.201.09:50:47.00:"st=record 2006.201.09:50:47.00:data_valid=on 2006.201.09:50:47.00:midob 2006.201.09:50:47.13/onsource/TRACKING 2006.201.09:50:47.13/wx/22.35,1003.6,94 2006.201.09:50:47.31/cable/+6.4658E-03 2006.201.09:50:48.40/va/01,08,usb,yes,35,38 2006.201.09:50:48.40/va/02,07,usb,yes,38,39 2006.201.09:50:48.40/va/03,08,usb,yes,34,36 2006.201.09:50:48.40/va/04,07,usb,yes,39,41 2006.201.09:50:48.40/va/05,04,usb,yes,35,35 2006.201.09:50:48.40/va/06,05,usb,yes,35,35 2006.201.09:50:48.40/va/07,05,usb,yes,34,35 2006.201.09:50:48.40/va/08,04,usb,yes,34,40 2006.201.09:50:48.63/valo/01,524.99,yes,locked 2006.201.09:50:48.63/valo/02,534.99,yes,locked 2006.201.09:50:48.63/valo/03,564.99,yes,locked 2006.201.09:50:48.63/valo/04,624.99,yes,locked 2006.201.09:50:48.63/valo/05,734.99,yes,locked 2006.201.09:50:48.63/valo/06,814.99,yes,locked 2006.201.09:50:48.63/valo/07,864.99,yes,locked 2006.201.09:50:48.63/valo/08,884.99,yes,locked 2006.201.09:50:49.72/vb/01,04,usb,yes,33,30 2006.201.09:50:49.72/vb/02,05,usb,yes,31,30 2006.201.09:50:49.72/vb/03,04,usb,yes,32,35 2006.201.09:50:49.72/vb/04,05,usb,yes,32,31 2006.201.09:50:49.72/vb/05,04,usb,yes,29,31 2006.201.09:50:49.72/vb/06,04,usb,yes,33,29 2006.201.09:50:49.72/vb/07,04,usb,yes,33,33 2006.201.09:50:49.72/vb/08,04,usb,yes,30,34 2006.201.09:50:49.95/vblo/01,629.99,yes,locked 2006.201.09:50:49.95/vblo/02,634.99,yes,locked 2006.201.09:50:49.95/vblo/03,649.99,yes,locked 2006.201.09:50:49.95/vblo/04,679.99,yes,locked 2006.201.09:50:49.95/vblo/05,709.99,yes,locked 2006.201.09:50:49.95/vblo/06,719.99,yes,locked 2006.201.09:50:49.95/vblo/07,734.99,yes,locked 2006.201.09:50:49.95/vblo/08,744.99,yes,locked 2006.201.09:50:50.10/vabw/8 2006.201.09:50:50.25/vbbw/8 2006.201.09:50:50.46/xfe/off,on,15.0 2006.201.09:50:50.84/ifatt/23,28,28,28 2006.201.09:50:51.05/fmout-gps/S +4.59E-07 2006.201.09:50:51.12:!2006.201.09:55:37 2006.201.09:55:37.00:data_valid=off 2006.201.09:55:37.00:"et 2006.201.09:55:37.00:!+3s 2006.201.09:55:40.02:"tape 2006.201.09:55:40.02:postob 2006.201.09:55:40.20/cable/+6.4674E-03 2006.201.09:55:40.20/wx/22.28,1003.6,95 2006.201.09:55:40.28/fmout-gps/S +4.58E-07 2006.201.09:55:40.28:scan_name=201-0957,jd0607,40 2006.201.09:55:40.28:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.201.09:55:41.14#flagr#flagr/antenna,new-source 2006.201.09:55:41.14:checkk5 2006.201.09:55:41.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:55:41.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:55:42.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:55:42.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:55:43.01/chk_obsdata//k5ts1/T2010950??a.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.201.09:55:43.38/chk_obsdata//k5ts2/T2010950??b.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.201.09:55:43.74/chk_obsdata//k5ts3/T2010950??c.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.201.09:55:44.10/chk_obsdata//k5ts4/T2010950??d.dat file size is correct (nominal:1160MB, actual:1156MB). 2006.201.09:55:44.79/k5log//k5ts1_log_newline 2006.201.09:55:45.48/k5log//k5ts2_log_newline 2006.201.09:55:46.16/k5log//k5ts3_log_newline 2006.201.09:55:46.85/k5log//k5ts4_log_newline 2006.201.09:55:46.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:55:46.88:setupk4=1 2006.201.09:55:46.88$setupk4/echo=on 2006.201.09:55:46.88$setupk4/pcalon 2006.201.09:55:46.88$pcalon/"no phase cal control is implemented here 2006.201.09:55:46.88$setupk4/"tpicd=stop 2006.201.09:55:46.88$setupk4/"rec=synch_on 2006.201.09:55:46.88$setupk4/"rec_mode=128 2006.201.09:55:46.88$setupk4/!* 2006.201.09:55:46.88$setupk4/recpk4 2006.201.09:55:46.88$recpk4/recpatch= 2006.201.09:55:46.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:55:46.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:55:46.88$setupk4/vck44 2006.201.09:55:46.88$vck44/valo=1,524.99 2006.201.09:55:46.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.09:55:46.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.09:55:46.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:46.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:46.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:46.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:46.88#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:55:46.88#ibcon#first serial, iclass 22, count 0 2006.201.09:55:46.88#ibcon#enter sib2, iclass 22, count 0 2006.201.09:55:46.88#ibcon#flushed, iclass 22, count 0 2006.201.09:55:46.88#ibcon#about to write, iclass 22, count 0 2006.201.09:55:46.88#ibcon#wrote, iclass 22, count 0 2006.201.09:55:46.88#ibcon#about to read 3, iclass 22, count 0 2006.201.09:55:46.92#ibcon#read 3, iclass 22, count 0 2006.201.09:55:46.92#ibcon#about to read 4, iclass 22, count 0 2006.201.09:55:46.92#ibcon#read 4, iclass 22, count 0 2006.201.09:55:46.92#ibcon#about to read 5, iclass 22, count 0 2006.201.09:55:46.92#ibcon#read 5, iclass 22, count 0 2006.201.09:55:46.92#ibcon#about to read 6, iclass 22, count 0 2006.201.09:55:46.92#ibcon#read 6, iclass 22, count 0 2006.201.09:55:46.92#ibcon#end of sib2, iclass 22, count 0 2006.201.09:55:46.92#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:55:46.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:55:46.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:55:46.92#ibcon#*before write, iclass 22, count 0 2006.201.09:55:46.92#ibcon#enter sib2, iclass 22, count 0 2006.201.09:55:46.92#ibcon#flushed, iclass 22, count 0 2006.201.09:55:46.92#ibcon#about to write, iclass 22, count 0 2006.201.09:55:46.92#ibcon#wrote, iclass 22, count 0 2006.201.09:55:46.92#ibcon#about to read 3, iclass 22, count 0 2006.201.09:55:46.97#ibcon#read 3, iclass 22, count 0 2006.201.09:55:46.97#ibcon#about to read 4, iclass 22, count 0 2006.201.09:55:46.97#ibcon#read 4, iclass 22, count 0 2006.201.09:55:46.97#ibcon#about to read 5, iclass 22, count 0 2006.201.09:55:46.97#ibcon#read 5, iclass 22, count 0 2006.201.09:55:46.97#ibcon#about to read 6, iclass 22, count 0 2006.201.09:55:46.97#ibcon#read 6, iclass 22, count 0 2006.201.09:55:46.97#ibcon#end of sib2, iclass 22, count 0 2006.201.09:55:46.97#ibcon#*after write, iclass 22, count 0 2006.201.09:55:46.97#ibcon#*before return 0, iclass 22, count 0 2006.201.09:55:46.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:46.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:46.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:55:46.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:55:46.97$vck44/va=1,8 2006.201.09:55:46.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.09:55:46.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.09:55:46.97#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:46.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:46.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:46.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:46.97#ibcon#enter wrdev, iclass 24, count 2 2006.201.09:55:46.97#ibcon#first serial, iclass 24, count 2 2006.201.09:55:46.97#ibcon#enter sib2, iclass 24, count 2 2006.201.09:55:46.97#ibcon#flushed, iclass 24, count 2 2006.201.09:55:46.97#ibcon#about to write, iclass 24, count 2 2006.201.09:55:46.97#ibcon#wrote, iclass 24, count 2 2006.201.09:55:46.97#ibcon#about to read 3, iclass 24, count 2 2006.201.09:55:46.99#ibcon#read 3, iclass 24, count 2 2006.201.09:55:46.99#ibcon#about to read 4, iclass 24, count 2 2006.201.09:55:46.99#ibcon#read 4, iclass 24, count 2 2006.201.09:55:46.99#ibcon#about to read 5, iclass 24, count 2 2006.201.09:55:46.99#ibcon#read 5, iclass 24, count 2 2006.201.09:55:46.99#ibcon#about to read 6, iclass 24, count 2 2006.201.09:55:46.99#ibcon#read 6, iclass 24, count 2 2006.201.09:55:46.99#ibcon#end of sib2, iclass 24, count 2 2006.201.09:55:46.99#ibcon#*mode == 0, iclass 24, count 2 2006.201.09:55:46.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.09:55:46.99#ibcon#[25=AT01-08\r\n] 2006.201.09:55:46.99#ibcon#*before write, iclass 24, count 2 2006.201.09:55:46.99#ibcon#enter sib2, iclass 24, count 2 2006.201.09:55:46.99#ibcon#flushed, iclass 24, count 2 2006.201.09:55:46.99#ibcon#about to write, iclass 24, count 2 2006.201.09:55:46.99#ibcon#wrote, iclass 24, count 2 2006.201.09:55:46.99#ibcon#about to read 3, iclass 24, count 2 2006.201.09:55:47.02#ibcon#read 3, iclass 24, count 2 2006.201.09:55:47.02#ibcon#about to read 4, iclass 24, count 2 2006.201.09:55:47.02#ibcon#read 4, iclass 24, count 2 2006.201.09:55:47.02#ibcon#about to read 5, iclass 24, count 2 2006.201.09:55:47.02#ibcon#read 5, iclass 24, count 2 2006.201.09:55:47.02#ibcon#about to read 6, iclass 24, count 2 2006.201.09:55:47.02#ibcon#read 6, iclass 24, count 2 2006.201.09:55:47.02#ibcon#end of sib2, iclass 24, count 2 2006.201.09:55:47.02#ibcon#*after write, iclass 24, count 2 2006.201.09:55:47.02#ibcon#*before return 0, iclass 24, count 2 2006.201.09:55:47.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:47.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:47.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.09:55:47.02#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:47.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:47.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:47.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:47.14#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:55:47.14#ibcon#first serial, iclass 24, count 0 2006.201.09:55:47.14#ibcon#enter sib2, iclass 24, count 0 2006.201.09:55:47.14#ibcon#flushed, iclass 24, count 0 2006.201.09:55:47.14#ibcon#about to write, iclass 24, count 0 2006.201.09:55:47.14#ibcon#wrote, iclass 24, count 0 2006.201.09:55:47.14#ibcon#about to read 3, iclass 24, count 0 2006.201.09:55:47.16#ibcon#read 3, iclass 24, count 0 2006.201.09:55:47.16#ibcon#about to read 4, iclass 24, count 0 2006.201.09:55:47.16#ibcon#read 4, iclass 24, count 0 2006.201.09:55:47.16#ibcon#about to read 5, iclass 24, count 0 2006.201.09:55:47.16#ibcon#read 5, iclass 24, count 0 2006.201.09:55:47.16#ibcon#about to read 6, iclass 24, count 0 2006.201.09:55:47.16#ibcon#read 6, iclass 24, count 0 2006.201.09:55:47.16#ibcon#end of sib2, iclass 24, count 0 2006.201.09:55:47.16#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:55:47.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:55:47.16#ibcon#[25=USB\r\n] 2006.201.09:55:47.16#ibcon#*before write, iclass 24, count 0 2006.201.09:55:47.16#ibcon#enter sib2, iclass 24, count 0 2006.201.09:55:47.16#ibcon#flushed, iclass 24, count 0 2006.201.09:55:47.16#ibcon#about to write, iclass 24, count 0 2006.201.09:55:47.16#ibcon#wrote, iclass 24, count 0 2006.201.09:55:47.16#ibcon#about to read 3, iclass 24, count 0 2006.201.09:55:47.19#ibcon#read 3, iclass 24, count 0 2006.201.09:55:47.19#ibcon#about to read 4, iclass 24, count 0 2006.201.09:55:47.19#ibcon#read 4, iclass 24, count 0 2006.201.09:55:47.19#ibcon#about to read 5, iclass 24, count 0 2006.201.09:55:47.19#ibcon#read 5, iclass 24, count 0 2006.201.09:55:47.19#ibcon#about to read 6, iclass 24, count 0 2006.201.09:55:47.19#ibcon#read 6, iclass 24, count 0 2006.201.09:55:47.19#ibcon#end of sib2, iclass 24, count 0 2006.201.09:55:47.19#ibcon#*after write, iclass 24, count 0 2006.201.09:55:47.19#ibcon#*before return 0, iclass 24, count 0 2006.201.09:55:47.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:47.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:47.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:55:47.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:55:47.19$vck44/valo=2,534.99 2006.201.09:55:47.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.09:55:47.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.09:55:47.19#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:47.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:47.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:47.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:47.19#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:55:47.19#ibcon#first serial, iclass 26, count 0 2006.201.09:55:47.19#ibcon#enter sib2, iclass 26, count 0 2006.201.09:55:47.19#ibcon#flushed, iclass 26, count 0 2006.201.09:55:47.19#ibcon#about to write, iclass 26, count 0 2006.201.09:55:47.19#ibcon#wrote, iclass 26, count 0 2006.201.09:55:47.19#ibcon#about to read 3, iclass 26, count 0 2006.201.09:55:47.21#ibcon#read 3, iclass 26, count 0 2006.201.09:55:47.21#ibcon#about to read 4, iclass 26, count 0 2006.201.09:55:47.21#ibcon#read 4, iclass 26, count 0 2006.201.09:55:47.21#ibcon#about to read 5, iclass 26, count 0 2006.201.09:55:47.21#ibcon#read 5, iclass 26, count 0 2006.201.09:55:47.21#ibcon#about to read 6, iclass 26, count 0 2006.201.09:55:47.21#ibcon#read 6, iclass 26, count 0 2006.201.09:55:47.21#ibcon#end of sib2, iclass 26, count 0 2006.201.09:55:47.21#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:55:47.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:55:47.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:55:47.21#ibcon#*before write, iclass 26, count 0 2006.201.09:55:47.21#ibcon#enter sib2, iclass 26, count 0 2006.201.09:55:47.21#ibcon#flushed, iclass 26, count 0 2006.201.09:55:47.21#ibcon#about to write, iclass 26, count 0 2006.201.09:55:47.21#ibcon#wrote, iclass 26, count 0 2006.201.09:55:47.21#ibcon#about to read 3, iclass 26, count 0 2006.201.09:55:47.26#ibcon#read 3, iclass 26, count 0 2006.201.09:55:47.26#ibcon#about to read 4, iclass 26, count 0 2006.201.09:55:47.26#ibcon#read 4, iclass 26, count 0 2006.201.09:55:47.26#ibcon#about to read 5, iclass 26, count 0 2006.201.09:55:47.26#ibcon#read 5, iclass 26, count 0 2006.201.09:55:47.26#ibcon#about to read 6, iclass 26, count 0 2006.201.09:55:47.26#ibcon#read 6, iclass 26, count 0 2006.201.09:55:47.26#ibcon#end of sib2, iclass 26, count 0 2006.201.09:55:47.26#ibcon#*after write, iclass 26, count 0 2006.201.09:55:47.26#ibcon#*before return 0, iclass 26, count 0 2006.201.09:55:47.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:47.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:47.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:55:47.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:55:47.26$vck44/va=2,7 2006.201.09:55:47.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.09:55:47.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.09:55:47.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:47.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:47.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:47.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:47.31#ibcon#enter wrdev, iclass 28, count 2 2006.201.09:55:47.31#ibcon#first serial, iclass 28, count 2 2006.201.09:55:47.31#ibcon#enter sib2, iclass 28, count 2 2006.201.09:55:47.31#ibcon#flushed, iclass 28, count 2 2006.201.09:55:47.31#ibcon#about to write, iclass 28, count 2 2006.201.09:55:47.31#ibcon#wrote, iclass 28, count 2 2006.201.09:55:47.31#ibcon#about to read 3, iclass 28, count 2 2006.201.09:55:47.33#ibcon#read 3, iclass 28, count 2 2006.201.09:55:47.33#ibcon#about to read 4, iclass 28, count 2 2006.201.09:55:47.33#ibcon#read 4, iclass 28, count 2 2006.201.09:55:47.33#ibcon#about to read 5, iclass 28, count 2 2006.201.09:55:47.33#ibcon#read 5, iclass 28, count 2 2006.201.09:55:47.33#ibcon#about to read 6, iclass 28, count 2 2006.201.09:55:47.33#ibcon#read 6, iclass 28, count 2 2006.201.09:55:47.33#ibcon#end of sib2, iclass 28, count 2 2006.201.09:55:47.33#ibcon#*mode == 0, iclass 28, count 2 2006.201.09:55:47.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.09:55:47.33#ibcon#[25=AT02-07\r\n] 2006.201.09:55:47.33#ibcon#*before write, iclass 28, count 2 2006.201.09:55:47.33#ibcon#enter sib2, iclass 28, count 2 2006.201.09:55:47.33#ibcon#flushed, iclass 28, count 2 2006.201.09:55:47.33#ibcon#about to write, iclass 28, count 2 2006.201.09:55:47.33#ibcon#wrote, iclass 28, count 2 2006.201.09:55:47.33#ibcon#about to read 3, iclass 28, count 2 2006.201.09:55:47.36#ibcon#read 3, iclass 28, count 2 2006.201.09:55:47.36#ibcon#about to read 4, iclass 28, count 2 2006.201.09:55:47.36#ibcon#read 4, iclass 28, count 2 2006.201.09:55:47.36#ibcon#about to read 5, iclass 28, count 2 2006.201.09:55:47.36#ibcon#read 5, iclass 28, count 2 2006.201.09:55:47.36#ibcon#about to read 6, iclass 28, count 2 2006.201.09:55:47.36#ibcon#read 6, iclass 28, count 2 2006.201.09:55:47.36#ibcon#end of sib2, iclass 28, count 2 2006.201.09:55:47.36#ibcon#*after write, iclass 28, count 2 2006.201.09:55:47.36#ibcon#*before return 0, iclass 28, count 2 2006.201.09:55:47.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:47.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:47.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.09:55:47.36#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:47.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:47.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:47.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:47.48#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:55:47.48#ibcon#first serial, iclass 28, count 0 2006.201.09:55:47.48#ibcon#enter sib2, iclass 28, count 0 2006.201.09:55:47.48#ibcon#flushed, iclass 28, count 0 2006.201.09:55:47.48#ibcon#about to write, iclass 28, count 0 2006.201.09:55:47.48#ibcon#wrote, iclass 28, count 0 2006.201.09:55:47.48#ibcon#about to read 3, iclass 28, count 0 2006.201.09:55:47.50#ibcon#read 3, iclass 28, count 0 2006.201.09:55:47.50#ibcon#about to read 4, iclass 28, count 0 2006.201.09:55:47.50#ibcon#read 4, iclass 28, count 0 2006.201.09:55:47.50#ibcon#about to read 5, iclass 28, count 0 2006.201.09:55:47.50#ibcon#read 5, iclass 28, count 0 2006.201.09:55:47.50#ibcon#about to read 6, iclass 28, count 0 2006.201.09:55:47.50#ibcon#read 6, iclass 28, count 0 2006.201.09:55:47.50#ibcon#end of sib2, iclass 28, count 0 2006.201.09:55:47.50#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:55:47.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:55:47.50#ibcon#[25=USB\r\n] 2006.201.09:55:47.50#ibcon#*before write, iclass 28, count 0 2006.201.09:55:47.50#ibcon#enter sib2, iclass 28, count 0 2006.201.09:55:47.50#ibcon#flushed, iclass 28, count 0 2006.201.09:55:47.50#ibcon#about to write, iclass 28, count 0 2006.201.09:55:47.50#ibcon#wrote, iclass 28, count 0 2006.201.09:55:47.50#ibcon#about to read 3, iclass 28, count 0 2006.201.09:55:47.53#ibcon#read 3, iclass 28, count 0 2006.201.09:55:47.53#ibcon#about to read 4, iclass 28, count 0 2006.201.09:55:47.53#ibcon#read 4, iclass 28, count 0 2006.201.09:55:47.53#ibcon#about to read 5, iclass 28, count 0 2006.201.09:55:47.53#ibcon#read 5, iclass 28, count 0 2006.201.09:55:47.53#ibcon#about to read 6, iclass 28, count 0 2006.201.09:55:47.53#ibcon#read 6, iclass 28, count 0 2006.201.09:55:47.53#ibcon#end of sib2, iclass 28, count 0 2006.201.09:55:47.53#ibcon#*after write, iclass 28, count 0 2006.201.09:55:47.53#ibcon#*before return 0, iclass 28, count 0 2006.201.09:55:47.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:47.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:47.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:55:47.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:55:47.53$vck44/valo=3,564.99 2006.201.09:55:47.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.09:55:47.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.09:55:47.53#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:47.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:47.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:47.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:47.53#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:55:47.53#ibcon#first serial, iclass 30, count 0 2006.201.09:55:47.53#ibcon#enter sib2, iclass 30, count 0 2006.201.09:55:47.53#ibcon#flushed, iclass 30, count 0 2006.201.09:55:47.53#ibcon#about to write, iclass 30, count 0 2006.201.09:55:47.53#ibcon#wrote, iclass 30, count 0 2006.201.09:55:47.53#ibcon#about to read 3, iclass 30, count 0 2006.201.09:55:47.55#ibcon#read 3, iclass 30, count 0 2006.201.09:55:47.55#ibcon#about to read 4, iclass 30, count 0 2006.201.09:55:47.55#ibcon#read 4, iclass 30, count 0 2006.201.09:55:47.55#ibcon#about to read 5, iclass 30, count 0 2006.201.09:55:47.55#ibcon#read 5, iclass 30, count 0 2006.201.09:55:47.55#ibcon#about to read 6, iclass 30, count 0 2006.201.09:55:47.55#ibcon#read 6, iclass 30, count 0 2006.201.09:55:47.55#ibcon#end of sib2, iclass 30, count 0 2006.201.09:55:47.55#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:55:47.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:55:47.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:55:47.55#ibcon#*before write, iclass 30, count 0 2006.201.09:55:47.55#ibcon#enter sib2, iclass 30, count 0 2006.201.09:55:47.55#ibcon#flushed, iclass 30, count 0 2006.201.09:55:47.55#ibcon#about to write, iclass 30, count 0 2006.201.09:55:47.55#ibcon#wrote, iclass 30, count 0 2006.201.09:55:47.55#ibcon#about to read 3, iclass 30, count 0 2006.201.09:55:47.60#ibcon#read 3, iclass 30, count 0 2006.201.09:55:47.60#ibcon#about to read 4, iclass 30, count 0 2006.201.09:55:47.60#ibcon#read 4, iclass 30, count 0 2006.201.09:55:47.60#ibcon#about to read 5, iclass 30, count 0 2006.201.09:55:47.60#ibcon#read 5, iclass 30, count 0 2006.201.09:55:47.60#ibcon#about to read 6, iclass 30, count 0 2006.201.09:55:47.60#ibcon#read 6, iclass 30, count 0 2006.201.09:55:47.60#ibcon#end of sib2, iclass 30, count 0 2006.201.09:55:47.60#ibcon#*after write, iclass 30, count 0 2006.201.09:55:47.60#ibcon#*before return 0, iclass 30, count 0 2006.201.09:55:47.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:47.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:47.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:55:47.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:55:47.60$vck44/va=3,8 2006.201.09:55:47.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.09:55:47.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.09:55:47.60#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:47.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:47.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:47.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:47.65#ibcon#enter wrdev, iclass 32, count 2 2006.201.09:55:47.65#ibcon#first serial, iclass 32, count 2 2006.201.09:55:47.65#ibcon#enter sib2, iclass 32, count 2 2006.201.09:55:47.65#ibcon#flushed, iclass 32, count 2 2006.201.09:55:47.65#ibcon#about to write, iclass 32, count 2 2006.201.09:55:47.65#ibcon#wrote, iclass 32, count 2 2006.201.09:55:47.65#ibcon#about to read 3, iclass 32, count 2 2006.201.09:55:47.67#ibcon#read 3, iclass 32, count 2 2006.201.09:55:47.67#ibcon#about to read 4, iclass 32, count 2 2006.201.09:55:47.67#ibcon#read 4, iclass 32, count 2 2006.201.09:55:47.67#ibcon#about to read 5, iclass 32, count 2 2006.201.09:55:47.67#ibcon#read 5, iclass 32, count 2 2006.201.09:55:47.67#ibcon#about to read 6, iclass 32, count 2 2006.201.09:55:47.67#ibcon#read 6, iclass 32, count 2 2006.201.09:55:47.67#ibcon#end of sib2, iclass 32, count 2 2006.201.09:55:47.67#ibcon#*mode == 0, iclass 32, count 2 2006.201.09:55:47.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.09:55:47.67#ibcon#[25=AT03-08\r\n] 2006.201.09:55:47.67#ibcon#*before write, iclass 32, count 2 2006.201.09:55:47.67#ibcon#enter sib2, iclass 32, count 2 2006.201.09:55:47.67#ibcon#flushed, iclass 32, count 2 2006.201.09:55:47.67#ibcon#about to write, iclass 32, count 2 2006.201.09:55:47.67#ibcon#wrote, iclass 32, count 2 2006.201.09:55:47.67#ibcon#about to read 3, iclass 32, count 2 2006.201.09:55:47.70#ibcon#read 3, iclass 32, count 2 2006.201.09:55:47.70#ibcon#about to read 4, iclass 32, count 2 2006.201.09:55:47.70#ibcon#read 4, iclass 32, count 2 2006.201.09:55:47.70#ibcon#about to read 5, iclass 32, count 2 2006.201.09:55:47.70#ibcon#read 5, iclass 32, count 2 2006.201.09:55:47.70#ibcon#about to read 6, iclass 32, count 2 2006.201.09:55:47.70#ibcon#read 6, iclass 32, count 2 2006.201.09:55:47.70#ibcon#end of sib2, iclass 32, count 2 2006.201.09:55:47.70#ibcon#*after write, iclass 32, count 2 2006.201.09:55:47.70#ibcon#*before return 0, iclass 32, count 2 2006.201.09:55:47.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:47.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:47.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.09:55:47.70#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:47.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:47.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:47.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:47.82#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:55:47.82#ibcon#first serial, iclass 32, count 0 2006.201.09:55:47.82#ibcon#enter sib2, iclass 32, count 0 2006.201.09:55:47.82#ibcon#flushed, iclass 32, count 0 2006.201.09:55:47.82#ibcon#about to write, iclass 32, count 0 2006.201.09:55:47.82#ibcon#wrote, iclass 32, count 0 2006.201.09:55:47.82#ibcon#about to read 3, iclass 32, count 0 2006.201.09:55:47.84#ibcon#read 3, iclass 32, count 0 2006.201.09:55:47.84#ibcon#about to read 4, iclass 32, count 0 2006.201.09:55:47.84#ibcon#read 4, iclass 32, count 0 2006.201.09:55:47.84#ibcon#about to read 5, iclass 32, count 0 2006.201.09:55:47.84#ibcon#read 5, iclass 32, count 0 2006.201.09:55:47.84#ibcon#about to read 6, iclass 32, count 0 2006.201.09:55:47.84#ibcon#read 6, iclass 32, count 0 2006.201.09:55:47.84#ibcon#end of sib2, iclass 32, count 0 2006.201.09:55:47.84#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:55:47.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:55:47.84#ibcon#[25=USB\r\n] 2006.201.09:55:47.84#ibcon#*before write, iclass 32, count 0 2006.201.09:55:47.84#ibcon#enter sib2, iclass 32, count 0 2006.201.09:55:47.84#ibcon#flushed, iclass 32, count 0 2006.201.09:55:47.84#ibcon#about to write, iclass 32, count 0 2006.201.09:55:47.84#ibcon#wrote, iclass 32, count 0 2006.201.09:55:47.84#ibcon#about to read 3, iclass 32, count 0 2006.201.09:55:47.87#ibcon#read 3, iclass 32, count 0 2006.201.09:55:47.87#ibcon#about to read 4, iclass 32, count 0 2006.201.09:55:47.87#ibcon#read 4, iclass 32, count 0 2006.201.09:55:47.87#ibcon#about to read 5, iclass 32, count 0 2006.201.09:55:47.87#ibcon#read 5, iclass 32, count 0 2006.201.09:55:47.87#ibcon#about to read 6, iclass 32, count 0 2006.201.09:55:47.87#ibcon#read 6, iclass 32, count 0 2006.201.09:55:47.87#ibcon#end of sib2, iclass 32, count 0 2006.201.09:55:47.87#ibcon#*after write, iclass 32, count 0 2006.201.09:55:47.87#ibcon#*before return 0, iclass 32, count 0 2006.201.09:55:47.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:47.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:47.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:55:47.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:55:47.87$vck44/valo=4,624.99 2006.201.09:55:47.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.09:55:47.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.09:55:47.87#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:47.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:47.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:47.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:47.87#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:55:47.87#ibcon#first serial, iclass 34, count 0 2006.201.09:55:47.87#ibcon#enter sib2, iclass 34, count 0 2006.201.09:55:47.87#ibcon#flushed, iclass 34, count 0 2006.201.09:55:47.87#ibcon#about to write, iclass 34, count 0 2006.201.09:55:47.87#ibcon#wrote, iclass 34, count 0 2006.201.09:55:47.87#ibcon#about to read 3, iclass 34, count 0 2006.201.09:55:47.89#ibcon#read 3, iclass 34, count 0 2006.201.09:55:47.89#ibcon#about to read 4, iclass 34, count 0 2006.201.09:55:47.89#ibcon#read 4, iclass 34, count 0 2006.201.09:55:47.89#ibcon#about to read 5, iclass 34, count 0 2006.201.09:55:47.89#ibcon#read 5, iclass 34, count 0 2006.201.09:55:47.89#ibcon#about to read 6, iclass 34, count 0 2006.201.09:55:47.89#ibcon#read 6, iclass 34, count 0 2006.201.09:55:47.89#ibcon#end of sib2, iclass 34, count 0 2006.201.09:55:47.89#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:55:47.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:55:47.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:55:47.89#ibcon#*before write, iclass 34, count 0 2006.201.09:55:47.89#ibcon#enter sib2, iclass 34, count 0 2006.201.09:55:47.89#ibcon#flushed, iclass 34, count 0 2006.201.09:55:47.89#ibcon#about to write, iclass 34, count 0 2006.201.09:55:47.89#ibcon#wrote, iclass 34, count 0 2006.201.09:55:47.89#ibcon#about to read 3, iclass 34, count 0 2006.201.09:55:47.94#ibcon#read 3, iclass 34, count 0 2006.201.09:55:47.94#ibcon#about to read 4, iclass 34, count 0 2006.201.09:55:47.94#ibcon#read 4, iclass 34, count 0 2006.201.09:55:47.94#ibcon#about to read 5, iclass 34, count 0 2006.201.09:55:47.94#ibcon#read 5, iclass 34, count 0 2006.201.09:55:47.94#ibcon#about to read 6, iclass 34, count 0 2006.201.09:55:47.94#ibcon#read 6, iclass 34, count 0 2006.201.09:55:47.94#ibcon#end of sib2, iclass 34, count 0 2006.201.09:55:47.94#ibcon#*after write, iclass 34, count 0 2006.201.09:55:47.94#ibcon#*before return 0, iclass 34, count 0 2006.201.09:55:47.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:47.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:47.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:55:47.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:55:47.94$vck44/va=4,7 2006.201.09:55:47.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.09:55:47.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.09:55:47.94#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:47.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:47.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:47.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:47.99#ibcon#enter wrdev, iclass 36, count 2 2006.201.09:55:47.99#ibcon#first serial, iclass 36, count 2 2006.201.09:55:47.99#ibcon#enter sib2, iclass 36, count 2 2006.201.09:55:47.99#ibcon#flushed, iclass 36, count 2 2006.201.09:55:47.99#ibcon#about to write, iclass 36, count 2 2006.201.09:55:47.99#ibcon#wrote, iclass 36, count 2 2006.201.09:55:47.99#ibcon#about to read 3, iclass 36, count 2 2006.201.09:55:48.01#ibcon#read 3, iclass 36, count 2 2006.201.09:55:48.01#ibcon#about to read 4, iclass 36, count 2 2006.201.09:55:48.01#ibcon#read 4, iclass 36, count 2 2006.201.09:55:48.01#ibcon#about to read 5, iclass 36, count 2 2006.201.09:55:48.01#ibcon#read 5, iclass 36, count 2 2006.201.09:55:48.01#ibcon#about to read 6, iclass 36, count 2 2006.201.09:55:48.01#ibcon#read 6, iclass 36, count 2 2006.201.09:55:48.01#ibcon#end of sib2, iclass 36, count 2 2006.201.09:55:48.01#ibcon#*mode == 0, iclass 36, count 2 2006.201.09:55:48.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.09:55:48.01#ibcon#[25=AT04-07\r\n] 2006.201.09:55:48.01#ibcon#*before write, iclass 36, count 2 2006.201.09:55:48.01#ibcon#enter sib2, iclass 36, count 2 2006.201.09:55:48.01#ibcon#flushed, iclass 36, count 2 2006.201.09:55:48.01#ibcon#about to write, iclass 36, count 2 2006.201.09:55:48.01#ibcon#wrote, iclass 36, count 2 2006.201.09:55:48.01#ibcon#about to read 3, iclass 36, count 2 2006.201.09:55:48.04#ibcon#read 3, iclass 36, count 2 2006.201.09:55:48.04#ibcon#about to read 4, iclass 36, count 2 2006.201.09:55:48.04#ibcon#read 4, iclass 36, count 2 2006.201.09:55:48.04#ibcon#about to read 5, iclass 36, count 2 2006.201.09:55:48.04#ibcon#read 5, iclass 36, count 2 2006.201.09:55:48.04#ibcon#about to read 6, iclass 36, count 2 2006.201.09:55:48.04#ibcon#read 6, iclass 36, count 2 2006.201.09:55:48.04#ibcon#end of sib2, iclass 36, count 2 2006.201.09:55:48.04#ibcon#*after write, iclass 36, count 2 2006.201.09:55:48.04#ibcon#*before return 0, iclass 36, count 2 2006.201.09:55:48.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:48.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:48.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.09:55:48.04#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:48.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:48.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:48.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:48.16#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:55:48.16#ibcon#first serial, iclass 36, count 0 2006.201.09:55:48.16#ibcon#enter sib2, iclass 36, count 0 2006.201.09:55:48.16#ibcon#flushed, iclass 36, count 0 2006.201.09:55:48.16#ibcon#about to write, iclass 36, count 0 2006.201.09:55:48.16#ibcon#wrote, iclass 36, count 0 2006.201.09:55:48.16#ibcon#about to read 3, iclass 36, count 0 2006.201.09:55:48.18#ibcon#read 3, iclass 36, count 0 2006.201.09:55:48.18#ibcon#about to read 4, iclass 36, count 0 2006.201.09:55:48.18#ibcon#read 4, iclass 36, count 0 2006.201.09:55:48.18#ibcon#about to read 5, iclass 36, count 0 2006.201.09:55:48.18#ibcon#read 5, iclass 36, count 0 2006.201.09:55:48.18#ibcon#about to read 6, iclass 36, count 0 2006.201.09:55:48.18#ibcon#read 6, iclass 36, count 0 2006.201.09:55:48.18#ibcon#end of sib2, iclass 36, count 0 2006.201.09:55:48.18#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:55:48.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:55:48.18#ibcon#[25=USB\r\n] 2006.201.09:55:48.18#ibcon#*before write, iclass 36, count 0 2006.201.09:55:48.18#ibcon#enter sib2, iclass 36, count 0 2006.201.09:55:48.18#ibcon#flushed, iclass 36, count 0 2006.201.09:55:48.18#ibcon#about to write, iclass 36, count 0 2006.201.09:55:48.18#ibcon#wrote, iclass 36, count 0 2006.201.09:55:48.18#ibcon#about to read 3, iclass 36, count 0 2006.201.09:55:48.21#ibcon#read 3, iclass 36, count 0 2006.201.09:55:48.21#ibcon#about to read 4, iclass 36, count 0 2006.201.09:55:48.21#ibcon#read 4, iclass 36, count 0 2006.201.09:55:48.21#ibcon#about to read 5, iclass 36, count 0 2006.201.09:55:48.21#ibcon#read 5, iclass 36, count 0 2006.201.09:55:48.21#ibcon#about to read 6, iclass 36, count 0 2006.201.09:55:48.21#ibcon#read 6, iclass 36, count 0 2006.201.09:55:48.21#ibcon#end of sib2, iclass 36, count 0 2006.201.09:55:48.21#ibcon#*after write, iclass 36, count 0 2006.201.09:55:48.21#ibcon#*before return 0, iclass 36, count 0 2006.201.09:55:48.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:48.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:48.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:55:48.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:55:48.21$vck44/valo=5,734.99 2006.201.09:55:48.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.09:55:48.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.09:55:48.21#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:48.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:48.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:48.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:48.21#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:55:48.21#ibcon#first serial, iclass 38, count 0 2006.201.09:55:48.21#ibcon#enter sib2, iclass 38, count 0 2006.201.09:55:48.21#ibcon#flushed, iclass 38, count 0 2006.201.09:55:48.21#ibcon#about to write, iclass 38, count 0 2006.201.09:55:48.21#ibcon#wrote, iclass 38, count 0 2006.201.09:55:48.21#ibcon#about to read 3, iclass 38, count 0 2006.201.09:55:48.23#ibcon#read 3, iclass 38, count 0 2006.201.09:55:48.23#ibcon#about to read 4, iclass 38, count 0 2006.201.09:55:48.23#ibcon#read 4, iclass 38, count 0 2006.201.09:55:48.23#ibcon#about to read 5, iclass 38, count 0 2006.201.09:55:48.23#ibcon#read 5, iclass 38, count 0 2006.201.09:55:48.23#ibcon#about to read 6, iclass 38, count 0 2006.201.09:55:48.23#ibcon#read 6, iclass 38, count 0 2006.201.09:55:48.23#ibcon#end of sib2, iclass 38, count 0 2006.201.09:55:48.23#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:55:48.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:55:48.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:55:48.23#ibcon#*before write, iclass 38, count 0 2006.201.09:55:48.23#ibcon#enter sib2, iclass 38, count 0 2006.201.09:55:48.23#ibcon#flushed, iclass 38, count 0 2006.201.09:55:48.23#ibcon#about to write, iclass 38, count 0 2006.201.09:55:48.23#ibcon#wrote, iclass 38, count 0 2006.201.09:55:48.23#ibcon#about to read 3, iclass 38, count 0 2006.201.09:55:48.27#ibcon#read 3, iclass 38, count 0 2006.201.09:55:48.27#ibcon#about to read 4, iclass 38, count 0 2006.201.09:55:48.27#ibcon#read 4, iclass 38, count 0 2006.201.09:55:48.27#ibcon#about to read 5, iclass 38, count 0 2006.201.09:55:48.27#ibcon#read 5, iclass 38, count 0 2006.201.09:55:48.27#ibcon#about to read 6, iclass 38, count 0 2006.201.09:55:48.27#ibcon#read 6, iclass 38, count 0 2006.201.09:55:48.27#ibcon#end of sib2, iclass 38, count 0 2006.201.09:55:48.27#ibcon#*after write, iclass 38, count 0 2006.201.09:55:48.27#ibcon#*before return 0, iclass 38, count 0 2006.201.09:55:48.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:48.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:48.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:55:48.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:55:48.27$vck44/va=5,4 2006.201.09:55:48.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.09:55:48.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.09:55:48.27#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:48.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:48.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:48.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:48.33#ibcon#enter wrdev, iclass 40, count 2 2006.201.09:55:48.33#ibcon#first serial, iclass 40, count 2 2006.201.09:55:48.33#ibcon#enter sib2, iclass 40, count 2 2006.201.09:55:48.33#ibcon#flushed, iclass 40, count 2 2006.201.09:55:48.33#ibcon#about to write, iclass 40, count 2 2006.201.09:55:48.33#ibcon#wrote, iclass 40, count 2 2006.201.09:55:48.33#ibcon#about to read 3, iclass 40, count 2 2006.201.09:55:48.35#ibcon#read 3, iclass 40, count 2 2006.201.09:55:48.35#ibcon#about to read 4, iclass 40, count 2 2006.201.09:55:48.35#ibcon#read 4, iclass 40, count 2 2006.201.09:55:48.35#ibcon#about to read 5, iclass 40, count 2 2006.201.09:55:48.35#ibcon#read 5, iclass 40, count 2 2006.201.09:55:48.35#ibcon#about to read 6, iclass 40, count 2 2006.201.09:55:48.35#ibcon#read 6, iclass 40, count 2 2006.201.09:55:48.35#ibcon#end of sib2, iclass 40, count 2 2006.201.09:55:48.35#ibcon#*mode == 0, iclass 40, count 2 2006.201.09:55:48.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.09:55:48.35#ibcon#[25=AT05-04\r\n] 2006.201.09:55:48.35#ibcon#*before write, iclass 40, count 2 2006.201.09:55:48.35#ibcon#enter sib2, iclass 40, count 2 2006.201.09:55:48.35#ibcon#flushed, iclass 40, count 2 2006.201.09:55:48.35#ibcon#about to write, iclass 40, count 2 2006.201.09:55:48.35#ibcon#wrote, iclass 40, count 2 2006.201.09:55:48.35#ibcon#about to read 3, iclass 40, count 2 2006.201.09:55:48.38#ibcon#read 3, iclass 40, count 2 2006.201.09:55:48.38#ibcon#about to read 4, iclass 40, count 2 2006.201.09:55:48.38#ibcon#read 4, iclass 40, count 2 2006.201.09:55:48.38#ibcon#about to read 5, iclass 40, count 2 2006.201.09:55:48.38#ibcon#read 5, iclass 40, count 2 2006.201.09:55:48.38#ibcon#about to read 6, iclass 40, count 2 2006.201.09:55:48.38#ibcon#read 6, iclass 40, count 2 2006.201.09:55:48.38#ibcon#end of sib2, iclass 40, count 2 2006.201.09:55:48.38#ibcon#*after write, iclass 40, count 2 2006.201.09:55:48.38#ibcon#*before return 0, iclass 40, count 2 2006.201.09:55:48.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:48.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:48.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.09:55:48.38#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:48.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:48.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:48.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:48.50#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:55:48.50#ibcon#first serial, iclass 40, count 0 2006.201.09:55:48.50#ibcon#enter sib2, iclass 40, count 0 2006.201.09:55:48.50#ibcon#flushed, iclass 40, count 0 2006.201.09:55:48.50#ibcon#about to write, iclass 40, count 0 2006.201.09:55:48.50#ibcon#wrote, iclass 40, count 0 2006.201.09:55:48.50#ibcon#about to read 3, iclass 40, count 0 2006.201.09:55:48.52#ibcon#read 3, iclass 40, count 0 2006.201.09:55:48.52#ibcon#about to read 4, iclass 40, count 0 2006.201.09:55:48.52#ibcon#read 4, iclass 40, count 0 2006.201.09:55:48.52#ibcon#about to read 5, iclass 40, count 0 2006.201.09:55:48.52#ibcon#read 5, iclass 40, count 0 2006.201.09:55:48.52#ibcon#about to read 6, iclass 40, count 0 2006.201.09:55:48.52#ibcon#read 6, iclass 40, count 0 2006.201.09:55:48.52#ibcon#end of sib2, iclass 40, count 0 2006.201.09:55:48.52#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:55:48.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:55:48.52#ibcon#[25=USB\r\n] 2006.201.09:55:48.52#ibcon#*before write, iclass 40, count 0 2006.201.09:55:48.52#ibcon#enter sib2, iclass 40, count 0 2006.201.09:55:48.52#ibcon#flushed, iclass 40, count 0 2006.201.09:55:48.52#ibcon#about to write, iclass 40, count 0 2006.201.09:55:48.52#ibcon#wrote, iclass 40, count 0 2006.201.09:55:48.52#ibcon#about to read 3, iclass 40, count 0 2006.201.09:55:48.55#ibcon#read 3, iclass 40, count 0 2006.201.09:55:48.55#ibcon#about to read 4, iclass 40, count 0 2006.201.09:55:48.55#ibcon#read 4, iclass 40, count 0 2006.201.09:55:48.55#ibcon#about to read 5, iclass 40, count 0 2006.201.09:55:48.55#ibcon#read 5, iclass 40, count 0 2006.201.09:55:48.55#ibcon#about to read 6, iclass 40, count 0 2006.201.09:55:48.55#ibcon#read 6, iclass 40, count 0 2006.201.09:55:48.55#ibcon#end of sib2, iclass 40, count 0 2006.201.09:55:48.55#ibcon#*after write, iclass 40, count 0 2006.201.09:55:48.55#ibcon#*before return 0, iclass 40, count 0 2006.201.09:55:48.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:48.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:48.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:55:48.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:55:48.55$vck44/valo=6,814.99 2006.201.09:55:48.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.09:55:48.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.09:55:48.55#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:48.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:48.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:48.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:48.55#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:55:48.55#ibcon#first serial, iclass 4, count 0 2006.201.09:55:48.55#ibcon#enter sib2, iclass 4, count 0 2006.201.09:55:48.55#ibcon#flushed, iclass 4, count 0 2006.201.09:55:48.55#ibcon#about to write, iclass 4, count 0 2006.201.09:55:48.55#ibcon#wrote, iclass 4, count 0 2006.201.09:55:48.55#ibcon#about to read 3, iclass 4, count 0 2006.201.09:55:48.57#ibcon#read 3, iclass 4, count 0 2006.201.09:55:48.57#ibcon#about to read 4, iclass 4, count 0 2006.201.09:55:48.57#ibcon#read 4, iclass 4, count 0 2006.201.09:55:48.57#ibcon#about to read 5, iclass 4, count 0 2006.201.09:55:48.57#ibcon#read 5, iclass 4, count 0 2006.201.09:55:48.57#ibcon#about to read 6, iclass 4, count 0 2006.201.09:55:48.57#ibcon#read 6, iclass 4, count 0 2006.201.09:55:48.57#ibcon#end of sib2, iclass 4, count 0 2006.201.09:55:48.57#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:55:48.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:55:48.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:55:48.57#ibcon#*before write, iclass 4, count 0 2006.201.09:55:48.57#ibcon#enter sib2, iclass 4, count 0 2006.201.09:55:48.57#ibcon#flushed, iclass 4, count 0 2006.201.09:55:48.57#ibcon#about to write, iclass 4, count 0 2006.201.09:55:48.57#ibcon#wrote, iclass 4, count 0 2006.201.09:55:48.57#ibcon#about to read 3, iclass 4, count 0 2006.201.09:55:48.62#ibcon#read 3, iclass 4, count 0 2006.201.09:55:48.62#ibcon#about to read 4, iclass 4, count 0 2006.201.09:55:48.62#ibcon#read 4, iclass 4, count 0 2006.201.09:55:48.62#ibcon#about to read 5, iclass 4, count 0 2006.201.09:55:48.62#ibcon#read 5, iclass 4, count 0 2006.201.09:55:48.62#ibcon#about to read 6, iclass 4, count 0 2006.201.09:55:48.62#ibcon#read 6, iclass 4, count 0 2006.201.09:55:48.62#ibcon#end of sib2, iclass 4, count 0 2006.201.09:55:48.62#ibcon#*after write, iclass 4, count 0 2006.201.09:55:48.62#ibcon#*before return 0, iclass 4, count 0 2006.201.09:55:48.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:48.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:48.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:55:48.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:55:48.62$vck44/va=6,5 2006.201.09:55:48.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.09:55:48.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.09:55:48.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:48.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:48.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:48.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:48.67#ibcon#enter wrdev, iclass 6, count 2 2006.201.09:55:48.67#ibcon#first serial, iclass 6, count 2 2006.201.09:55:48.67#ibcon#enter sib2, iclass 6, count 2 2006.201.09:55:48.67#ibcon#flushed, iclass 6, count 2 2006.201.09:55:48.67#ibcon#about to write, iclass 6, count 2 2006.201.09:55:48.67#ibcon#wrote, iclass 6, count 2 2006.201.09:55:48.67#ibcon#about to read 3, iclass 6, count 2 2006.201.09:55:48.69#ibcon#read 3, iclass 6, count 2 2006.201.09:55:48.69#ibcon#about to read 4, iclass 6, count 2 2006.201.09:55:48.69#ibcon#read 4, iclass 6, count 2 2006.201.09:55:48.69#ibcon#about to read 5, iclass 6, count 2 2006.201.09:55:48.69#ibcon#read 5, iclass 6, count 2 2006.201.09:55:48.69#ibcon#about to read 6, iclass 6, count 2 2006.201.09:55:48.69#ibcon#read 6, iclass 6, count 2 2006.201.09:55:48.69#ibcon#end of sib2, iclass 6, count 2 2006.201.09:55:48.69#ibcon#*mode == 0, iclass 6, count 2 2006.201.09:55:48.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.09:55:48.69#ibcon#[25=AT06-05\r\n] 2006.201.09:55:48.69#ibcon#*before write, iclass 6, count 2 2006.201.09:55:48.69#ibcon#enter sib2, iclass 6, count 2 2006.201.09:55:48.69#ibcon#flushed, iclass 6, count 2 2006.201.09:55:48.69#ibcon#about to write, iclass 6, count 2 2006.201.09:55:48.69#ibcon#wrote, iclass 6, count 2 2006.201.09:55:48.69#ibcon#about to read 3, iclass 6, count 2 2006.201.09:55:48.72#ibcon#read 3, iclass 6, count 2 2006.201.09:55:48.72#ibcon#about to read 4, iclass 6, count 2 2006.201.09:55:48.72#ibcon#read 4, iclass 6, count 2 2006.201.09:55:48.72#ibcon#about to read 5, iclass 6, count 2 2006.201.09:55:48.72#ibcon#read 5, iclass 6, count 2 2006.201.09:55:48.72#ibcon#about to read 6, iclass 6, count 2 2006.201.09:55:48.72#ibcon#read 6, iclass 6, count 2 2006.201.09:55:48.72#ibcon#end of sib2, iclass 6, count 2 2006.201.09:55:48.72#ibcon#*after write, iclass 6, count 2 2006.201.09:55:48.72#ibcon#*before return 0, iclass 6, count 2 2006.201.09:55:48.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:48.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:48.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.09:55:48.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:48.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:48.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:48.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:48.84#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:55:48.84#ibcon#first serial, iclass 6, count 0 2006.201.09:55:48.84#ibcon#enter sib2, iclass 6, count 0 2006.201.09:55:48.84#ibcon#flushed, iclass 6, count 0 2006.201.09:55:48.84#ibcon#about to write, iclass 6, count 0 2006.201.09:55:48.84#ibcon#wrote, iclass 6, count 0 2006.201.09:55:48.84#ibcon#about to read 3, iclass 6, count 0 2006.201.09:55:48.86#ibcon#read 3, iclass 6, count 0 2006.201.09:55:48.86#ibcon#about to read 4, iclass 6, count 0 2006.201.09:55:48.86#ibcon#read 4, iclass 6, count 0 2006.201.09:55:48.86#ibcon#about to read 5, iclass 6, count 0 2006.201.09:55:48.86#ibcon#read 5, iclass 6, count 0 2006.201.09:55:48.86#ibcon#about to read 6, iclass 6, count 0 2006.201.09:55:48.86#ibcon#read 6, iclass 6, count 0 2006.201.09:55:48.86#ibcon#end of sib2, iclass 6, count 0 2006.201.09:55:48.86#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:55:48.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:55:48.86#ibcon#[25=USB\r\n] 2006.201.09:55:48.86#ibcon#*before write, iclass 6, count 0 2006.201.09:55:48.86#ibcon#enter sib2, iclass 6, count 0 2006.201.09:55:48.86#ibcon#flushed, iclass 6, count 0 2006.201.09:55:48.86#ibcon#about to write, iclass 6, count 0 2006.201.09:55:48.86#ibcon#wrote, iclass 6, count 0 2006.201.09:55:48.86#ibcon#about to read 3, iclass 6, count 0 2006.201.09:55:48.89#ibcon#read 3, iclass 6, count 0 2006.201.09:55:48.89#ibcon#about to read 4, iclass 6, count 0 2006.201.09:55:48.89#ibcon#read 4, iclass 6, count 0 2006.201.09:55:48.89#ibcon#about to read 5, iclass 6, count 0 2006.201.09:55:48.89#ibcon#read 5, iclass 6, count 0 2006.201.09:55:48.89#ibcon#about to read 6, iclass 6, count 0 2006.201.09:55:48.89#ibcon#read 6, iclass 6, count 0 2006.201.09:55:48.89#ibcon#end of sib2, iclass 6, count 0 2006.201.09:55:48.89#ibcon#*after write, iclass 6, count 0 2006.201.09:55:48.89#ibcon#*before return 0, iclass 6, count 0 2006.201.09:55:48.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:48.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:48.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:55:48.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:55:48.89$vck44/valo=7,864.99 2006.201.09:55:48.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.09:55:48.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.09:55:48.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:48.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:48.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:48.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:48.89#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:55:48.89#ibcon#first serial, iclass 10, count 0 2006.201.09:55:48.89#ibcon#enter sib2, iclass 10, count 0 2006.201.09:55:48.89#ibcon#flushed, iclass 10, count 0 2006.201.09:55:48.89#ibcon#about to write, iclass 10, count 0 2006.201.09:55:48.89#ibcon#wrote, iclass 10, count 0 2006.201.09:55:48.89#ibcon#about to read 3, iclass 10, count 0 2006.201.09:55:48.91#ibcon#read 3, iclass 10, count 0 2006.201.09:55:48.91#ibcon#about to read 4, iclass 10, count 0 2006.201.09:55:48.91#ibcon#read 4, iclass 10, count 0 2006.201.09:55:48.91#ibcon#about to read 5, iclass 10, count 0 2006.201.09:55:48.91#ibcon#read 5, iclass 10, count 0 2006.201.09:55:48.91#ibcon#about to read 6, iclass 10, count 0 2006.201.09:55:48.91#ibcon#read 6, iclass 10, count 0 2006.201.09:55:48.91#ibcon#end of sib2, iclass 10, count 0 2006.201.09:55:48.91#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:55:48.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:55:48.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:55:48.91#ibcon#*before write, iclass 10, count 0 2006.201.09:55:48.91#ibcon#enter sib2, iclass 10, count 0 2006.201.09:55:48.91#ibcon#flushed, iclass 10, count 0 2006.201.09:55:48.91#ibcon#about to write, iclass 10, count 0 2006.201.09:55:48.91#ibcon#wrote, iclass 10, count 0 2006.201.09:55:48.91#ibcon#about to read 3, iclass 10, count 0 2006.201.09:55:48.95#ibcon#read 3, iclass 10, count 0 2006.201.09:55:48.95#ibcon#about to read 4, iclass 10, count 0 2006.201.09:55:48.95#ibcon#read 4, iclass 10, count 0 2006.201.09:55:48.95#ibcon#about to read 5, iclass 10, count 0 2006.201.09:55:48.95#ibcon#read 5, iclass 10, count 0 2006.201.09:55:48.95#ibcon#about to read 6, iclass 10, count 0 2006.201.09:55:48.95#ibcon#read 6, iclass 10, count 0 2006.201.09:55:48.95#ibcon#end of sib2, iclass 10, count 0 2006.201.09:55:48.95#ibcon#*after write, iclass 10, count 0 2006.201.09:55:48.95#ibcon#*before return 0, iclass 10, count 0 2006.201.09:55:48.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:48.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:48.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:55:48.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:55:48.95$vck44/va=7,5 2006.201.09:55:48.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.09:55:48.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.09:55:48.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:48.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:49.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:49.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:49.01#ibcon#enter wrdev, iclass 12, count 2 2006.201.09:55:49.01#ibcon#first serial, iclass 12, count 2 2006.201.09:55:49.01#ibcon#enter sib2, iclass 12, count 2 2006.201.09:55:49.01#ibcon#flushed, iclass 12, count 2 2006.201.09:55:49.01#ibcon#about to write, iclass 12, count 2 2006.201.09:55:49.01#ibcon#wrote, iclass 12, count 2 2006.201.09:55:49.01#ibcon#about to read 3, iclass 12, count 2 2006.201.09:55:49.03#ibcon#read 3, iclass 12, count 2 2006.201.09:55:49.03#ibcon#about to read 4, iclass 12, count 2 2006.201.09:55:49.03#ibcon#read 4, iclass 12, count 2 2006.201.09:55:49.03#ibcon#about to read 5, iclass 12, count 2 2006.201.09:55:49.03#ibcon#read 5, iclass 12, count 2 2006.201.09:55:49.03#ibcon#about to read 6, iclass 12, count 2 2006.201.09:55:49.03#ibcon#read 6, iclass 12, count 2 2006.201.09:55:49.03#ibcon#end of sib2, iclass 12, count 2 2006.201.09:55:49.03#ibcon#*mode == 0, iclass 12, count 2 2006.201.09:55:49.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.09:55:49.03#ibcon#[25=AT07-05\r\n] 2006.201.09:55:49.03#ibcon#*before write, iclass 12, count 2 2006.201.09:55:49.03#ibcon#enter sib2, iclass 12, count 2 2006.201.09:55:49.03#ibcon#flushed, iclass 12, count 2 2006.201.09:55:49.03#ibcon#about to write, iclass 12, count 2 2006.201.09:55:49.03#ibcon#wrote, iclass 12, count 2 2006.201.09:55:49.03#ibcon#about to read 3, iclass 12, count 2 2006.201.09:55:49.06#ibcon#read 3, iclass 12, count 2 2006.201.09:55:49.06#ibcon#about to read 4, iclass 12, count 2 2006.201.09:55:49.06#ibcon#read 4, iclass 12, count 2 2006.201.09:55:49.06#ibcon#about to read 5, iclass 12, count 2 2006.201.09:55:49.06#ibcon#read 5, iclass 12, count 2 2006.201.09:55:49.06#ibcon#about to read 6, iclass 12, count 2 2006.201.09:55:49.06#ibcon#read 6, iclass 12, count 2 2006.201.09:55:49.06#ibcon#end of sib2, iclass 12, count 2 2006.201.09:55:49.06#ibcon#*after write, iclass 12, count 2 2006.201.09:55:49.06#ibcon#*before return 0, iclass 12, count 2 2006.201.09:55:49.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:49.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:49.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.09:55:49.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:49.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:49.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:49.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:49.18#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:55:49.18#ibcon#first serial, iclass 12, count 0 2006.201.09:55:49.18#ibcon#enter sib2, iclass 12, count 0 2006.201.09:55:49.18#ibcon#flushed, iclass 12, count 0 2006.201.09:55:49.18#ibcon#about to write, iclass 12, count 0 2006.201.09:55:49.18#ibcon#wrote, iclass 12, count 0 2006.201.09:55:49.18#ibcon#about to read 3, iclass 12, count 0 2006.201.09:55:49.21#ibcon#read 3, iclass 12, count 0 2006.201.09:55:49.21#ibcon#about to read 4, iclass 12, count 0 2006.201.09:55:49.21#ibcon#read 4, iclass 12, count 0 2006.201.09:55:49.21#ibcon#about to read 5, iclass 12, count 0 2006.201.09:55:49.21#ibcon#read 5, iclass 12, count 0 2006.201.09:55:49.21#ibcon#about to read 6, iclass 12, count 0 2006.201.09:55:49.21#ibcon#read 6, iclass 12, count 0 2006.201.09:55:49.21#ibcon#end of sib2, iclass 12, count 0 2006.201.09:55:49.21#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:55:49.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:55:49.21#ibcon#[25=USB\r\n] 2006.201.09:55:49.21#ibcon#*before write, iclass 12, count 0 2006.201.09:55:49.21#ibcon#enter sib2, iclass 12, count 0 2006.201.09:55:49.21#ibcon#flushed, iclass 12, count 0 2006.201.09:55:49.21#ibcon#about to write, iclass 12, count 0 2006.201.09:55:49.21#ibcon#wrote, iclass 12, count 0 2006.201.09:55:49.21#ibcon#about to read 3, iclass 12, count 0 2006.201.09:55:49.24#ibcon#read 3, iclass 12, count 0 2006.201.09:55:49.24#ibcon#about to read 4, iclass 12, count 0 2006.201.09:55:49.24#ibcon#read 4, iclass 12, count 0 2006.201.09:55:49.24#ibcon#about to read 5, iclass 12, count 0 2006.201.09:55:49.24#ibcon#read 5, iclass 12, count 0 2006.201.09:55:49.24#ibcon#about to read 6, iclass 12, count 0 2006.201.09:55:49.24#ibcon#read 6, iclass 12, count 0 2006.201.09:55:49.24#ibcon#end of sib2, iclass 12, count 0 2006.201.09:55:49.24#ibcon#*after write, iclass 12, count 0 2006.201.09:55:49.24#ibcon#*before return 0, iclass 12, count 0 2006.201.09:55:49.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:49.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:49.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:55:49.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:55:49.24$vck44/valo=8,884.99 2006.201.09:55:49.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.09:55:49.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.09:55:49.24#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:49.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:49.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:49.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:49.24#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:55:49.24#ibcon#first serial, iclass 14, count 0 2006.201.09:55:49.24#ibcon#enter sib2, iclass 14, count 0 2006.201.09:55:49.24#ibcon#flushed, iclass 14, count 0 2006.201.09:55:49.24#ibcon#about to write, iclass 14, count 0 2006.201.09:55:49.24#ibcon#wrote, iclass 14, count 0 2006.201.09:55:49.24#ibcon#about to read 3, iclass 14, count 0 2006.201.09:55:49.26#ibcon#read 3, iclass 14, count 0 2006.201.09:55:49.26#ibcon#about to read 4, iclass 14, count 0 2006.201.09:55:49.26#ibcon#read 4, iclass 14, count 0 2006.201.09:55:49.26#ibcon#about to read 5, iclass 14, count 0 2006.201.09:55:49.26#ibcon#read 5, iclass 14, count 0 2006.201.09:55:49.26#ibcon#about to read 6, iclass 14, count 0 2006.201.09:55:49.26#ibcon#read 6, iclass 14, count 0 2006.201.09:55:49.26#ibcon#end of sib2, iclass 14, count 0 2006.201.09:55:49.26#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:55:49.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:55:49.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:55:49.26#ibcon#*before write, iclass 14, count 0 2006.201.09:55:49.26#ibcon#enter sib2, iclass 14, count 0 2006.201.09:55:49.26#ibcon#flushed, iclass 14, count 0 2006.201.09:55:49.26#ibcon#about to write, iclass 14, count 0 2006.201.09:55:49.26#ibcon#wrote, iclass 14, count 0 2006.201.09:55:49.26#ibcon#about to read 3, iclass 14, count 0 2006.201.09:55:49.30#ibcon#read 3, iclass 14, count 0 2006.201.09:55:49.30#ibcon#about to read 4, iclass 14, count 0 2006.201.09:55:49.30#ibcon#read 4, iclass 14, count 0 2006.201.09:55:49.30#ibcon#about to read 5, iclass 14, count 0 2006.201.09:55:49.30#ibcon#read 5, iclass 14, count 0 2006.201.09:55:49.30#ibcon#about to read 6, iclass 14, count 0 2006.201.09:55:49.30#ibcon#read 6, iclass 14, count 0 2006.201.09:55:49.30#ibcon#end of sib2, iclass 14, count 0 2006.201.09:55:49.30#ibcon#*after write, iclass 14, count 0 2006.201.09:55:49.30#ibcon#*before return 0, iclass 14, count 0 2006.201.09:55:49.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:49.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:49.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:55:49.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:55:49.30$vck44/va=8,4 2006.201.09:55:49.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.09:55:49.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.09:55:49.30#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:49.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:55:49.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:55:49.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:55:49.36#ibcon#enter wrdev, iclass 16, count 2 2006.201.09:55:49.36#ibcon#first serial, iclass 16, count 2 2006.201.09:55:49.36#ibcon#enter sib2, iclass 16, count 2 2006.201.09:55:49.36#ibcon#flushed, iclass 16, count 2 2006.201.09:55:49.36#ibcon#about to write, iclass 16, count 2 2006.201.09:55:49.36#ibcon#wrote, iclass 16, count 2 2006.201.09:55:49.36#ibcon#about to read 3, iclass 16, count 2 2006.201.09:55:49.38#ibcon#read 3, iclass 16, count 2 2006.201.09:55:49.38#ibcon#about to read 4, iclass 16, count 2 2006.201.09:55:49.38#ibcon#read 4, iclass 16, count 2 2006.201.09:55:49.38#ibcon#about to read 5, iclass 16, count 2 2006.201.09:55:49.38#ibcon#read 5, iclass 16, count 2 2006.201.09:55:49.38#ibcon#about to read 6, iclass 16, count 2 2006.201.09:55:49.38#ibcon#read 6, iclass 16, count 2 2006.201.09:55:49.38#ibcon#end of sib2, iclass 16, count 2 2006.201.09:55:49.38#ibcon#*mode == 0, iclass 16, count 2 2006.201.09:55:49.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.09:55:49.38#ibcon#[25=AT08-04\r\n] 2006.201.09:55:49.38#ibcon#*before write, iclass 16, count 2 2006.201.09:55:49.38#ibcon#enter sib2, iclass 16, count 2 2006.201.09:55:49.38#ibcon#flushed, iclass 16, count 2 2006.201.09:55:49.38#ibcon#about to write, iclass 16, count 2 2006.201.09:55:49.38#ibcon#wrote, iclass 16, count 2 2006.201.09:55:49.38#ibcon#about to read 3, iclass 16, count 2 2006.201.09:55:49.41#ibcon#read 3, iclass 16, count 2 2006.201.09:55:49.41#ibcon#about to read 4, iclass 16, count 2 2006.201.09:55:49.41#ibcon#read 4, iclass 16, count 2 2006.201.09:55:49.41#ibcon#about to read 5, iclass 16, count 2 2006.201.09:55:49.41#ibcon#read 5, iclass 16, count 2 2006.201.09:55:49.41#ibcon#about to read 6, iclass 16, count 2 2006.201.09:55:49.41#ibcon#read 6, iclass 16, count 2 2006.201.09:55:49.41#ibcon#end of sib2, iclass 16, count 2 2006.201.09:55:49.41#ibcon#*after write, iclass 16, count 2 2006.201.09:55:49.41#ibcon#*before return 0, iclass 16, count 2 2006.201.09:55:49.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:55:49.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.09:55:49.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.09:55:49.41#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:49.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:55:49.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:55:49.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:55:49.53#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:55:49.53#ibcon#first serial, iclass 16, count 0 2006.201.09:55:49.53#ibcon#enter sib2, iclass 16, count 0 2006.201.09:55:49.53#ibcon#flushed, iclass 16, count 0 2006.201.09:55:49.53#ibcon#about to write, iclass 16, count 0 2006.201.09:55:49.53#ibcon#wrote, iclass 16, count 0 2006.201.09:55:49.53#ibcon#about to read 3, iclass 16, count 0 2006.201.09:55:49.55#ibcon#read 3, iclass 16, count 0 2006.201.09:55:49.55#ibcon#about to read 4, iclass 16, count 0 2006.201.09:55:49.55#ibcon#read 4, iclass 16, count 0 2006.201.09:55:49.55#ibcon#about to read 5, iclass 16, count 0 2006.201.09:55:49.55#ibcon#read 5, iclass 16, count 0 2006.201.09:55:49.55#ibcon#about to read 6, iclass 16, count 0 2006.201.09:55:49.55#ibcon#read 6, iclass 16, count 0 2006.201.09:55:49.55#ibcon#end of sib2, iclass 16, count 0 2006.201.09:55:49.55#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:55:49.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:55:49.55#ibcon#[25=USB\r\n] 2006.201.09:55:49.55#ibcon#*before write, iclass 16, count 0 2006.201.09:55:49.55#ibcon#enter sib2, iclass 16, count 0 2006.201.09:55:49.55#ibcon#flushed, iclass 16, count 0 2006.201.09:55:49.55#ibcon#about to write, iclass 16, count 0 2006.201.09:55:49.55#ibcon#wrote, iclass 16, count 0 2006.201.09:55:49.55#ibcon#about to read 3, iclass 16, count 0 2006.201.09:55:49.58#ibcon#read 3, iclass 16, count 0 2006.201.09:55:49.58#ibcon#about to read 4, iclass 16, count 0 2006.201.09:55:49.58#ibcon#read 4, iclass 16, count 0 2006.201.09:55:49.58#ibcon#about to read 5, iclass 16, count 0 2006.201.09:55:49.58#ibcon#read 5, iclass 16, count 0 2006.201.09:55:49.58#ibcon#about to read 6, iclass 16, count 0 2006.201.09:55:49.58#ibcon#read 6, iclass 16, count 0 2006.201.09:55:49.58#ibcon#end of sib2, iclass 16, count 0 2006.201.09:55:49.58#ibcon#*after write, iclass 16, count 0 2006.201.09:55:49.58#ibcon#*before return 0, iclass 16, count 0 2006.201.09:55:49.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:55:49.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.09:55:49.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:55:49.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:55:49.58$vck44/vblo=1,629.99 2006.201.09:55:49.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.09:55:49.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.09:55:49.58#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:49.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:55:49.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:55:49.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:55:49.58#ibcon#enter wrdev, iclass 18, count 0 2006.201.09:55:49.58#ibcon#first serial, iclass 18, count 0 2006.201.09:55:49.58#ibcon#enter sib2, iclass 18, count 0 2006.201.09:55:49.58#ibcon#flushed, iclass 18, count 0 2006.201.09:55:49.58#ibcon#about to write, iclass 18, count 0 2006.201.09:55:49.58#ibcon#wrote, iclass 18, count 0 2006.201.09:55:49.58#ibcon#about to read 3, iclass 18, count 0 2006.201.09:55:49.60#ibcon#read 3, iclass 18, count 0 2006.201.09:55:49.60#ibcon#about to read 4, iclass 18, count 0 2006.201.09:55:49.60#ibcon#read 4, iclass 18, count 0 2006.201.09:55:49.60#ibcon#about to read 5, iclass 18, count 0 2006.201.09:55:49.60#ibcon#read 5, iclass 18, count 0 2006.201.09:55:49.60#ibcon#about to read 6, iclass 18, count 0 2006.201.09:55:49.60#ibcon#read 6, iclass 18, count 0 2006.201.09:55:49.60#ibcon#end of sib2, iclass 18, count 0 2006.201.09:55:49.60#ibcon#*mode == 0, iclass 18, count 0 2006.201.09:55:49.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.09:55:49.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:55:49.60#ibcon#*before write, iclass 18, count 0 2006.201.09:55:49.60#ibcon#enter sib2, iclass 18, count 0 2006.201.09:55:49.60#ibcon#flushed, iclass 18, count 0 2006.201.09:55:49.60#ibcon#about to write, iclass 18, count 0 2006.201.09:55:49.60#ibcon#wrote, iclass 18, count 0 2006.201.09:55:49.60#ibcon#about to read 3, iclass 18, count 0 2006.201.09:55:49.64#ibcon#read 3, iclass 18, count 0 2006.201.09:55:49.64#ibcon#about to read 4, iclass 18, count 0 2006.201.09:55:49.64#ibcon#read 4, iclass 18, count 0 2006.201.09:55:49.64#ibcon#about to read 5, iclass 18, count 0 2006.201.09:55:49.64#ibcon#read 5, iclass 18, count 0 2006.201.09:55:49.64#ibcon#about to read 6, iclass 18, count 0 2006.201.09:55:49.64#ibcon#read 6, iclass 18, count 0 2006.201.09:55:49.64#ibcon#end of sib2, iclass 18, count 0 2006.201.09:55:49.64#ibcon#*after write, iclass 18, count 0 2006.201.09:55:49.64#ibcon#*before return 0, iclass 18, count 0 2006.201.09:55:49.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:55:49.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.09:55:49.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.09:55:49.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.09:55:49.64$vck44/vb=1,4 2006.201.09:55:49.64#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.09:55:49.64#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.09:55:49.64#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:49.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:55:49.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:55:49.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:55:49.64#ibcon#enter wrdev, iclass 20, count 2 2006.201.09:55:49.64#ibcon#first serial, iclass 20, count 2 2006.201.09:55:49.64#ibcon#enter sib2, iclass 20, count 2 2006.201.09:55:49.64#ibcon#flushed, iclass 20, count 2 2006.201.09:55:49.64#ibcon#about to write, iclass 20, count 2 2006.201.09:55:49.64#ibcon#wrote, iclass 20, count 2 2006.201.09:55:49.64#ibcon#about to read 3, iclass 20, count 2 2006.201.09:55:49.66#ibcon#read 3, iclass 20, count 2 2006.201.09:55:49.66#ibcon#about to read 4, iclass 20, count 2 2006.201.09:55:49.66#ibcon#read 4, iclass 20, count 2 2006.201.09:55:49.66#ibcon#about to read 5, iclass 20, count 2 2006.201.09:55:49.66#ibcon#read 5, iclass 20, count 2 2006.201.09:55:49.66#ibcon#about to read 6, iclass 20, count 2 2006.201.09:55:49.66#ibcon#read 6, iclass 20, count 2 2006.201.09:55:49.66#ibcon#end of sib2, iclass 20, count 2 2006.201.09:55:49.66#ibcon#*mode == 0, iclass 20, count 2 2006.201.09:55:49.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.09:55:49.66#ibcon#[27=AT01-04\r\n] 2006.201.09:55:49.66#ibcon#*before write, iclass 20, count 2 2006.201.09:55:49.66#ibcon#enter sib2, iclass 20, count 2 2006.201.09:55:49.66#ibcon#flushed, iclass 20, count 2 2006.201.09:55:49.66#ibcon#about to write, iclass 20, count 2 2006.201.09:55:49.66#ibcon#wrote, iclass 20, count 2 2006.201.09:55:49.66#ibcon#about to read 3, iclass 20, count 2 2006.201.09:55:49.69#ibcon#read 3, iclass 20, count 2 2006.201.09:55:49.69#ibcon#about to read 4, iclass 20, count 2 2006.201.09:55:49.69#ibcon#read 4, iclass 20, count 2 2006.201.09:55:49.69#ibcon#about to read 5, iclass 20, count 2 2006.201.09:55:49.69#ibcon#read 5, iclass 20, count 2 2006.201.09:55:49.69#ibcon#about to read 6, iclass 20, count 2 2006.201.09:55:49.69#ibcon#read 6, iclass 20, count 2 2006.201.09:55:49.69#ibcon#end of sib2, iclass 20, count 2 2006.201.09:55:49.69#ibcon#*after write, iclass 20, count 2 2006.201.09:55:49.69#ibcon#*before return 0, iclass 20, count 2 2006.201.09:55:49.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:55:49.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.09:55:49.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.09:55:49.69#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:49.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:55:49.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:55:49.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:55:49.81#ibcon#enter wrdev, iclass 20, count 0 2006.201.09:55:49.81#ibcon#first serial, iclass 20, count 0 2006.201.09:55:49.81#ibcon#enter sib2, iclass 20, count 0 2006.201.09:55:49.81#ibcon#flushed, iclass 20, count 0 2006.201.09:55:49.81#ibcon#about to write, iclass 20, count 0 2006.201.09:55:49.81#ibcon#wrote, iclass 20, count 0 2006.201.09:55:49.81#ibcon#about to read 3, iclass 20, count 0 2006.201.09:55:49.83#ibcon#read 3, iclass 20, count 0 2006.201.09:55:49.83#ibcon#about to read 4, iclass 20, count 0 2006.201.09:55:49.83#ibcon#read 4, iclass 20, count 0 2006.201.09:55:49.83#ibcon#about to read 5, iclass 20, count 0 2006.201.09:55:49.83#ibcon#read 5, iclass 20, count 0 2006.201.09:55:49.83#ibcon#about to read 6, iclass 20, count 0 2006.201.09:55:49.83#ibcon#read 6, iclass 20, count 0 2006.201.09:55:49.83#ibcon#end of sib2, iclass 20, count 0 2006.201.09:55:49.83#ibcon#*mode == 0, iclass 20, count 0 2006.201.09:55:49.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.09:55:49.83#ibcon#[27=USB\r\n] 2006.201.09:55:49.83#ibcon#*before write, iclass 20, count 0 2006.201.09:55:49.83#ibcon#enter sib2, iclass 20, count 0 2006.201.09:55:49.83#ibcon#flushed, iclass 20, count 0 2006.201.09:55:49.83#ibcon#about to write, iclass 20, count 0 2006.201.09:55:49.83#ibcon#wrote, iclass 20, count 0 2006.201.09:55:49.83#ibcon#about to read 3, iclass 20, count 0 2006.201.09:55:49.86#ibcon#read 3, iclass 20, count 0 2006.201.09:55:49.86#ibcon#about to read 4, iclass 20, count 0 2006.201.09:55:49.86#ibcon#read 4, iclass 20, count 0 2006.201.09:55:49.86#ibcon#about to read 5, iclass 20, count 0 2006.201.09:55:49.86#ibcon#read 5, iclass 20, count 0 2006.201.09:55:49.86#ibcon#about to read 6, iclass 20, count 0 2006.201.09:55:49.86#ibcon#read 6, iclass 20, count 0 2006.201.09:55:49.86#ibcon#end of sib2, iclass 20, count 0 2006.201.09:55:49.86#ibcon#*after write, iclass 20, count 0 2006.201.09:55:49.86#ibcon#*before return 0, iclass 20, count 0 2006.201.09:55:49.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:55:49.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.09:55:49.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.09:55:49.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.09:55:49.86$vck44/vblo=2,634.99 2006.201.09:55:49.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.09:55:49.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.09:55:49.86#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:49.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:49.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:49.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:49.86#ibcon#enter wrdev, iclass 22, count 0 2006.201.09:55:49.86#ibcon#first serial, iclass 22, count 0 2006.201.09:55:49.86#ibcon#enter sib2, iclass 22, count 0 2006.201.09:55:49.86#ibcon#flushed, iclass 22, count 0 2006.201.09:55:49.86#ibcon#about to write, iclass 22, count 0 2006.201.09:55:49.86#ibcon#wrote, iclass 22, count 0 2006.201.09:55:49.86#ibcon#about to read 3, iclass 22, count 0 2006.201.09:55:49.88#ibcon#read 3, iclass 22, count 0 2006.201.09:55:49.88#ibcon#about to read 4, iclass 22, count 0 2006.201.09:55:49.88#ibcon#read 4, iclass 22, count 0 2006.201.09:55:49.88#ibcon#about to read 5, iclass 22, count 0 2006.201.09:55:49.88#ibcon#read 5, iclass 22, count 0 2006.201.09:55:49.88#ibcon#about to read 6, iclass 22, count 0 2006.201.09:55:49.88#ibcon#read 6, iclass 22, count 0 2006.201.09:55:49.88#ibcon#end of sib2, iclass 22, count 0 2006.201.09:55:49.88#ibcon#*mode == 0, iclass 22, count 0 2006.201.09:55:49.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.09:55:49.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:55:49.88#ibcon#*before write, iclass 22, count 0 2006.201.09:55:49.88#ibcon#enter sib2, iclass 22, count 0 2006.201.09:55:49.88#ibcon#flushed, iclass 22, count 0 2006.201.09:55:49.88#ibcon#about to write, iclass 22, count 0 2006.201.09:55:49.88#ibcon#wrote, iclass 22, count 0 2006.201.09:55:49.88#ibcon#about to read 3, iclass 22, count 0 2006.201.09:55:49.92#ibcon#read 3, iclass 22, count 0 2006.201.09:55:49.92#ibcon#about to read 4, iclass 22, count 0 2006.201.09:55:49.92#ibcon#read 4, iclass 22, count 0 2006.201.09:55:49.92#ibcon#about to read 5, iclass 22, count 0 2006.201.09:55:49.92#ibcon#read 5, iclass 22, count 0 2006.201.09:55:49.92#ibcon#about to read 6, iclass 22, count 0 2006.201.09:55:49.92#ibcon#read 6, iclass 22, count 0 2006.201.09:55:49.92#ibcon#end of sib2, iclass 22, count 0 2006.201.09:55:49.92#ibcon#*after write, iclass 22, count 0 2006.201.09:55:49.92#ibcon#*before return 0, iclass 22, count 0 2006.201.09:55:49.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:49.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.09:55:49.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.09:55:49.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.09:55:49.92$vck44/vb=2,5 2006.201.09:55:49.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.09:55:49.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.09:55:49.92#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:49.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:49.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:49.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:49.98#ibcon#enter wrdev, iclass 24, count 2 2006.201.09:55:49.98#ibcon#first serial, iclass 24, count 2 2006.201.09:55:49.98#ibcon#enter sib2, iclass 24, count 2 2006.201.09:55:49.98#ibcon#flushed, iclass 24, count 2 2006.201.09:55:49.98#ibcon#about to write, iclass 24, count 2 2006.201.09:55:49.98#ibcon#wrote, iclass 24, count 2 2006.201.09:55:49.98#ibcon#about to read 3, iclass 24, count 2 2006.201.09:55:50.00#ibcon#read 3, iclass 24, count 2 2006.201.09:55:50.00#ibcon#about to read 4, iclass 24, count 2 2006.201.09:55:50.00#ibcon#read 4, iclass 24, count 2 2006.201.09:55:50.00#ibcon#about to read 5, iclass 24, count 2 2006.201.09:55:50.00#ibcon#read 5, iclass 24, count 2 2006.201.09:55:50.00#ibcon#about to read 6, iclass 24, count 2 2006.201.09:55:50.00#ibcon#read 6, iclass 24, count 2 2006.201.09:55:50.00#ibcon#end of sib2, iclass 24, count 2 2006.201.09:55:50.00#ibcon#*mode == 0, iclass 24, count 2 2006.201.09:55:50.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.09:55:50.00#ibcon#[27=AT02-05\r\n] 2006.201.09:55:50.00#ibcon#*before write, iclass 24, count 2 2006.201.09:55:50.00#ibcon#enter sib2, iclass 24, count 2 2006.201.09:55:50.00#ibcon#flushed, iclass 24, count 2 2006.201.09:55:50.00#ibcon#about to write, iclass 24, count 2 2006.201.09:55:50.00#ibcon#wrote, iclass 24, count 2 2006.201.09:55:50.00#ibcon#about to read 3, iclass 24, count 2 2006.201.09:55:50.03#ibcon#read 3, iclass 24, count 2 2006.201.09:55:50.03#ibcon#about to read 4, iclass 24, count 2 2006.201.09:55:50.03#ibcon#read 4, iclass 24, count 2 2006.201.09:55:50.03#ibcon#about to read 5, iclass 24, count 2 2006.201.09:55:50.03#ibcon#read 5, iclass 24, count 2 2006.201.09:55:50.03#ibcon#about to read 6, iclass 24, count 2 2006.201.09:55:50.03#ibcon#read 6, iclass 24, count 2 2006.201.09:55:50.03#ibcon#end of sib2, iclass 24, count 2 2006.201.09:55:50.03#ibcon#*after write, iclass 24, count 2 2006.201.09:55:50.03#ibcon#*before return 0, iclass 24, count 2 2006.201.09:55:50.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:50.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.09:55:50.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.09:55:50.03#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:50.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:50.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:50.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:50.15#ibcon#enter wrdev, iclass 24, count 0 2006.201.09:55:50.15#ibcon#first serial, iclass 24, count 0 2006.201.09:55:50.15#ibcon#enter sib2, iclass 24, count 0 2006.201.09:55:50.15#ibcon#flushed, iclass 24, count 0 2006.201.09:55:50.15#ibcon#about to write, iclass 24, count 0 2006.201.09:55:50.15#ibcon#wrote, iclass 24, count 0 2006.201.09:55:50.15#ibcon#about to read 3, iclass 24, count 0 2006.201.09:55:50.17#ibcon#read 3, iclass 24, count 0 2006.201.09:55:50.17#ibcon#about to read 4, iclass 24, count 0 2006.201.09:55:50.17#ibcon#read 4, iclass 24, count 0 2006.201.09:55:50.17#ibcon#about to read 5, iclass 24, count 0 2006.201.09:55:50.17#ibcon#read 5, iclass 24, count 0 2006.201.09:55:50.17#ibcon#about to read 6, iclass 24, count 0 2006.201.09:55:50.17#ibcon#read 6, iclass 24, count 0 2006.201.09:55:50.17#ibcon#end of sib2, iclass 24, count 0 2006.201.09:55:50.17#ibcon#*mode == 0, iclass 24, count 0 2006.201.09:55:50.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.09:55:50.17#ibcon#[27=USB\r\n] 2006.201.09:55:50.17#ibcon#*before write, iclass 24, count 0 2006.201.09:55:50.17#ibcon#enter sib2, iclass 24, count 0 2006.201.09:55:50.17#ibcon#flushed, iclass 24, count 0 2006.201.09:55:50.17#ibcon#about to write, iclass 24, count 0 2006.201.09:55:50.17#ibcon#wrote, iclass 24, count 0 2006.201.09:55:50.17#ibcon#about to read 3, iclass 24, count 0 2006.201.09:55:50.20#ibcon#read 3, iclass 24, count 0 2006.201.09:55:50.20#ibcon#about to read 4, iclass 24, count 0 2006.201.09:55:50.20#ibcon#read 4, iclass 24, count 0 2006.201.09:55:50.20#ibcon#about to read 5, iclass 24, count 0 2006.201.09:55:50.20#ibcon#read 5, iclass 24, count 0 2006.201.09:55:50.20#ibcon#about to read 6, iclass 24, count 0 2006.201.09:55:50.20#ibcon#read 6, iclass 24, count 0 2006.201.09:55:50.20#ibcon#end of sib2, iclass 24, count 0 2006.201.09:55:50.20#ibcon#*after write, iclass 24, count 0 2006.201.09:55:50.20#ibcon#*before return 0, iclass 24, count 0 2006.201.09:55:50.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:50.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.09:55:50.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.09:55:50.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.09:55:50.20$vck44/vblo=3,649.99 2006.201.09:55:50.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.09:55:50.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.09:55:50.20#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:50.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:50.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:50.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:50.20#ibcon#enter wrdev, iclass 26, count 0 2006.201.09:55:50.20#ibcon#first serial, iclass 26, count 0 2006.201.09:55:50.20#ibcon#enter sib2, iclass 26, count 0 2006.201.09:55:50.20#ibcon#flushed, iclass 26, count 0 2006.201.09:55:50.20#ibcon#about to write, iclass 26, count 0 2006.201.09:55:50.20#ibcon#wrote, iclass 26, count 0 2006.201.09:55:50.20#ibcon#about to read 3, iclass 26, count 0 2006.201.09:55:50.22#ibcon#read 3, iclass 26, count 0 2006.201.09:55:50.22#ibcon#about to read 4, iclass 26, count 0 2006.201.09:55:50.22#ibcon#read 4, iclass 26, count 0 2006.201.09:55:50.22#ibcon#about to read 5, iclass 26, count 0 2006.201.09:55:50.22#ibcon#read 5, iclass 26, count 0 2006.201.09:55:50.22#ibcon#about to read 6, iclass 26, count 0 2006.201.09:55:50.22#ibcon#read 6, iclass 26, count 0 2006.201.09:55:50.22#ibcon#end of sib2, iclass 26, count 0 2006.201.09:55:50.22#ibcon#*mode == 0, iclass 26, count 0 2006.201.09:55:50.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.09:55:50.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:55:50.22#ibcon#*before write, iclass 26, count 0 2006.201.09:55:50.22#ibcon#enter sib2, iclass 26, count 0 2006.201.09:55:50.22#ibcon#flushed, iclass 26, count 0 2006.201.09:55:50.22#ibcon#about to write, iclass 26, count 0 2006.201.09:55:50.22#ibcon#wrote, iclass 26, count 0 2006.201.09:55:50.22#ibcon#about to read 3, iclass 26, count 0 2006.201.09:55:50.26#ibcon#read 3, iclass 26, count 0 2006.201.09:55:50.26#ibcon#about to read 4, iclass 26, count 0 2006.201.09:55:50.26#ibcon#read 4, iclass 26, count 0 2006.201.09:55:50.26#ibcon#about to read 5, iclass 26, count 0 2006.201.09:55:50.26#ibcon#read 5, iclass 26, count 0 2006.201.09:55:50.26#ibcon#about to read 6, iclass 26, count 0 2006.201.09:55:50.26#ibcon#read 6, iclass 26, count 0 2006.201.09:55:50.26#ibcon#end of sib2, iclass 26, count 0 2006.201.09:55:50.26#ibcon#*after write, iclass 26, count 0 2006.201.09:55:50.26#ibcon#*before return 0, iclass 26, count 0 2006.201.09:55:50.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:50.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.09:55:50.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.09:55:50.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.09:55:50.26$vck44/vb=3,4 2006.201.09:55:50.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.09:55:50.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.09:55:50.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:50.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:50.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:50.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:50.32#ibcon#enter wrdev, iclass 28, count 2 2006.201.09:55:50.32#ibcon#first serial, iclass 28, count 2 2006.201.09:55:50.32#ibcon#enter sib2, iclass 28, count 2 2006.201.09:55:50.32#ibcon#flushed, iclass 28, count 2 2006.201.09:55:50.32#ibcon#about to write, iclass 28, count 2 2006.201.09:55:50.32#ibcon#wrote, iclass 28, count 2 2006.201.09:55:50.32#ibcon#about to read 3, iclass 28, count 2 2006.201.09:55:50.34#ibcon#read 3, iclass 28, count 2 2006.201.09:55:50.34#ibcon#about to read 4, iclass 28, count 2 2006.201.09:55:50.34#ibcon#read 4, iclass 28, count 2 2006.201.09:55:50.34#ibcon#about to read 5, iclass 28, count 2 2006.201.09:55:50.34#ibcon#read 5, iclass 28, count 2 2006.201.09:55:50.34#ibcon#about to read 6, iclass 28, count 2 2006.201.09:55:50.34#ibcon#read 6, iclass 28, count 2 2006.201.09:55:50.34#ibcon#end of sib2, iclass 28, count 2 2006.201.09:55:50.34#ibcon#*mode == 0, iclass 28, count 2 2006.201.09:55:50.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.09:55:50.34#ibcon#[27=AT03-04\r\n] 2006.201.09:55:50.34#ibcon#*before write, iclass 28, count 2 2006.201.09:55:50.34#ibcon#enter sib2, iclass 28, count 2 2006.201.09:55:50.34#ibcon#flushed, iclass 28, count 2 2006.201.09:55:50.34#ibcon#about to write, iclass 28, count 2 2006.201.09:55:50.34#ibcon#wrote, iclass 28, count 2 2006.201.09:55:50.34#ibcon#about to read 3, iclass 28, count 2 2006.201.09:55:50.37#ibcon#read 3, iclass 28, count 2 2006.201.09:55:50.37#ibcon#about to read 4, iclass 28, count 2 2006.201.09:55:50.37#ibcon#read 4, iclass 28, count 2 2006.201.09:55:50.37#ibcon#about to read 5, iclass 28, count 2 2006.201.09:55:50.37#ibcon#read 5, iclass 28, count 2 2006.201.09:55:50.37#ibcon#about to read 6, iclass 28, count 2 2006.201.09:55:50.37#ibcon#read 6, iclass 28, count 2 2006.201.09:55:50.37#ibcon#end of sib2, iclass 28, count 2 2006.201.09:55:50.37#ibcon#*after write, iclass 28, count 2 2006.201.09:55:50.37#ibcon#*before return 0, iclass 28, count 2 2006.201.09:55:50.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:50.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.09:55:50.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.09:55:50.37#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:50.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:50.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:50.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:50.49#ibcon#enter wrdev, iclass 28, count 0 2006.201.09:55:50.49#ibcon#first serial, iclass 28, count 0 2006.201.09:55:50.49#ibcon#enter sib2, iclass 28, count 0 2006.201.09:55:50.49#ibcon#flushed, iclass 28, count 0 2006.201.09:55:50.49#ibcon#about to write, iclass 28, count 0 2006.201.09:55:50.49#ibcon#wrote, iclass 28, count 0 2006.201.09:55:50.49#ibcon#about to read 3, iclass 28, count 0 2006.201.09:55:50.51#ibcon#read 3, iclass 28, count 0 2006.201.09:55:50.51#ibcon#about to read 4, iclass 28, count 0 2006.201.09:55:50.51#ibcon#read 4, iclass 28, count 0 2006.201.09:55:50.51#ibcon#about to read 5, iclass 28, count 0 2006.201.09:55:50.51#ibcon#read 5, iclass 28, count 0 2006.201.09:55:50.51#ibcon#about to read 6, iclass 28, count 0 2006.201.09:55:50.51#ibcon#read 6, iclass 28, count 0 2006.201.09:55:50.51#ibcon#end of sib2, iclass 28, count 0 2006.201.09:55:50.51#ibcon#*mode == 0, iclass 28, count 0 2006.201.09:55:50.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.09:55:50.51#ibcon#[27=USB\r\n] 2006.201.09:55:50.51#ibcon#*before write, iclass 28, count 0 2006.201.09:55:50.51#ibcon#enter sib2, iclass 28, count 0 2006.201.09:55:50.51#ibcon#flushed, iclass 28, count 0 2006.201.09:55:50.51#ibcon#about to write, iclass 28, count 0 2006.201.09:55:50.51#ibcon#wrote, iclass 28, count 0 2006.201.09:55:50.51#ibcon#about to read 3, iclass 28, count 0 2006.201.09:55:50.54#ibcon#read 3, iclass 28, count 0 2006.201.09:55:50.54#ibcon#about to read 4, iclass 28, count 0 2006.201.09:55:50.54#ibcon#read 4, iclass 28, count 0 2006.201.09:55:50.54#ibcon#about to read 5, iclass 28, count 0 2006.201.09:55:50.54#ibcon#read 5, iclass 28, count 0 2006.201.09:55:50.54#ibcon#about to read 6, iclass 28, count 0 2006.201.09:55:50.54#ibcon#read 6, iclass 28, count 0 2006.201.09:55:50.54#ibcon#end of sib2, iclass 28, count 0 2006.201.09:55:50.54#ibcon#*after write, iclass 28, count 0 2006.201.09:55:50.54#ibcon#*before return 0, iclass 28, count 0 2006.201.09:55:50.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:50.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.09:55:50.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.09:55:50.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.09:55:50.54$vck44/vblo=4,679.99 2006.201.09:55:50.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.09:55:50.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.09:55:50.54#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:50.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:50.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:50.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:50.54#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:55:50.54#ibcon#first serial, iclass 30, count 0 2006.201.09:55:50.54#ibcon#enter sib2, iclass 30, count 0 2006.201.09:55:50.54#ibcon#flushed, iclass 30, count 0 2006.201.09:55:50.54#ibcon#about to write, iclass 30, count 0 2006.201.09:55:50.54#ibcon#wrote, iclass 30, count 0 2006.201.09:55:50.54#ibcon#about to read 3, iclass 30, count 0 2006.201.09:55:50.56#ibcon#read 3, iclass 30, count 0 2006.201.09:55:50.56#ibcon#about to read 4, iclass 30, count 0 2006.201.09:55:50.56#ibcon#read 4, iclass 30, count 0 2006.201.09:55:50.56#ibcon#about to read 5, iclass 30, count 0 2006.201.09:55:50.56#ibcon#read 5, iclass 30, count 0 2006.201.09:55:50.56#ibcon#about to read 6, iclass 30, count 0 2006.201.09:55:50.56#ibcon#read 6, iclass 30, count 0 2006.201.09:55:50.56#ibcon#end of sib2, iclass 30, count 0 2006.201.09:55:50.56#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:55:50.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:55:50.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:55:50.56#ibcon#*before write, iclass 30, count 0 2006.201.09:55:50.56#ibcon#enter sib2, iclass 30, count 0 2006.201.09:55:50.56#ibcon#flushed, iclass 30, count 0 2006.201.09:55:50.56#ibcon#about to write, iclass 30, count 0 2006.201.09:55:50.56#ibcon#wrote, iclass 30, count 0 2006.201.09:55:50.56#ibcon#about to read 3, iclass 30, count 0 2006.201.09:55:50.60#ibcon#read 3, iclass 30, count 0 2006.201.09:55:50.60#ibcon#about to read 4, iclass 30, count 0 2006.201.09:55:50.60#ibcon#read 4, iclass 30, count 0 2006.201.09:55:50.60#ibcon#about to read 5, iclass 30, count 0 2006.201.09:55:50.60#ibcon#read 5, iclass 30, count 0 2006.201.09:55:50.60#ibcon#about to read 6, iclass 30, count 0 2006.201.09:55:50.60#ibcon#read 6, iclass 30, count 0 2006.201.09:55:50.60#ibcon#end of sib2, iclass 30, count 0 2006.201.09:55:50.60#ibcon#*after write, iclass 30, count 0 2006.201.09:55:50.60#ibcon#*before return 0, iclass 30, count 0 2006.201.09:55:50.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:50.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:55:50.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:55:50.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:55:50.60$vck44/vb=4,5 2006.201.09:55:50.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.09:55:50.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.09:55:50.60#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:50.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:50.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:50.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:50.66#ibcon#enter wrdev, iclass 32, count 2 2006.201.09:55:50.66#ibcon#first serial, iclass 32, count 2 2006.201.09:55:50.66#ibcon#enter sib2, iclass 32, count 2 2006.201.09:55:50.66#ibcon#flushed, iclass 32, count 2 2006.201.09:55:50.66#ibcon#about to write, iclass 32, count 2 2006.201.09:55:50.66#ibcon#wrote, iclass 32, count 2 2006.201.09:55:50.66#ibcon#about to read 3, iclass 32, count 2 2006.201.09:55:50.68#ibcon#read 3, iclass 32, count 2 2006.201.09:55:50.68#ibcon#about to read 4, iclass 32, count 2 2006.201.09:55:50.68#ibcon#read 4, iclass 32, count 2 2006.201.09:55:50.68#ibcon#about to read 5, iclass 32, count 2 2006.201.09:55:50.68#ibcon#read 5, iclass 32, count 2 2006.201.09:55:50.68#ibcon#about to read 6, iclass 32, count 2 2006.201.09:55:50.68#ibcon#read 6, iclass 32, count 2 2006.201.09:55:50.68#ibcon#end of sib2, iclass 32, count 2 2006.201.09:55:50.68#ibcon#*mode == 0, iclass 32, count 2 2006.201.09:55:50.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.09:55:50.68#ibcon#[27=AT04-05\r\n] 2006.201.09:55:50.68#ibcon#*before write, iclass 32, count 2 2006.201.09:55:50.68#ibcon#enter sib2, iclass 32, count 2 2006.201.09:55:50.68#ibcon#flushed, iclass 32, count 2 2006.201.09:55:50.68#ibcon#about to write, iclass 32, count 2 2006.201.09:55:50.68#ibcon#wrote, iclass 32, count 2 2006.201.09:55:50.68#ibcon#about to read 3, iclass 32, count 2 2006.201.09:55:50.71#ibcon#read 3, iclass 32, count 2 2006.201.09:55:50.71#ibcon#about to read 4, iclass 32, count 2 2006.201.09:55:50.71#ibcon#read 4, iclass 32, count 2 2006.201.09:55:50.71#ibcon#about to read 5, iclass 32, count 2 2006.201.09:55:50.71#ibcon#read 5, iclass 32, count 2 2006.201.09:55:50.71#ibcon#about to read 6, iclass 32, count 2 2006.201.09:55:50.71#ibcon#read 6, iclass 32, count 2 2006.201.09:55:50.71#ibcon#end of sib2, iclass 32, count 2 2006.201.09:55:50.71#ibcon#*after write, iclass 32, count 2 2006.201.09:55:50.71#ibcon#*before return 0, iclass 32, count 2 2006.201.09:55:50.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:50.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.09:55:50.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.09:55:50.71#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:50.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:50.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:50.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:50.83#ibcon#enter wrdev, iclass 32, count 0 2006.201.09:55:50.83#ibcon#first serial, iclass 32, count 0 2006.201.09:55:50.83#ibcon#enter sib2, iclass 32, count 0 2006.201.09:55:50.83#ibcon#flushed, iclass 32, count 0 2006.201.09:55:50.83#ibcon#about to write, iclass 32, count 0 2006.201.09:55:50.83#ibcon#wrote, iclass 32, count 0 2006.201.09:55:50.83#ibcon#about to read 3, iclass 32, count 0 2006.201.09:55:50.85#ibcon#read 3, iclass 32, count 0 2006.201.09:55:50.85#ibcon#about to read 4, iclass 32, count 0 2006.201.09:55:50.85#ibcon#read 4, iclass 32, count 0 2006.201.09:55:50.85#ibcon#about to read 5, iclass 32, count 0 2006.201.09:55:50.85#ibcon#read 5, iclass 32, count 0 2006.201.09:55:50.85#ibcon#about to read 6, iclass 32, count 0 2006.201.09:55:50.85#ibcon#read 6, iclass 32, count 0 2006.201.09:55:50.85#ibcon#end of sib2, iclass 32, count 0 2006.201.09:55:50.85#ibcon#*mode == 0, iclass 32, count 0 2006.201.09:55:50.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.09:55:50.85#ibcon#[27=USB\r\n] 2006.201.09:55:50.85#ibcon#*before write, iclass 32, count 0 2006.201.09:55:50.85#ibcon#enter sib2, iclass 32, count 0 2006.201.09:55:50.85#ibcon#flushed, iclass 32, count 0 2006.201.09:55:50.85#ibcon#about to write, iclass 32, count 0 2006.201.09:55:50.85#ibcon#wrote, iclass 32, count 0 2006.201.09:55:50.85#ibcon#about to read 3, iclass 32, count 0 2006.201.09:55:50.88#ibcon#read 3, iclass 32, count 0 2006.201.09:55:50.88#ibcon#about to read 4, iclass 32, count 0 2006.201.09:55:50.88#ibcon#read 4, iclass 32, count 0 2006.201.09:55:50.88#ibcon#about to read 5, iclass 32, count 0 2006.201.09:55:50.88#ibcon#read 5, iclass 32, count 0 2006.201.09:55:50.88#ibcon#about to read 6, iclass 32, count 0 2006.201.09:55:50.88#ibcon#read 6, iclass 32, count 0 2006.201.09:55:50.88#ibcon#end of sib2, iclass 32, count 0 2006.201.09:55:50.88#ibcon#*after write, iclass 32, count 0 2006.201.09:55:50.88#ibcon#*before return 0, iclass 32, count 0 2006.201.09:55:50.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:50.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.09:55:50.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.09:55:50.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.09:55:50.88$vck44/vblo=5,709.99 2006.201.09:55:50.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.09:55:50.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.09:55:50.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:50.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:50.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:50.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:50.88#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:55:50.88#ibcon#first serial, iclass 34, count 0 2006.201.09:55:50.88#ibcon#enter sib2, iclass 34, count 0 2006.201.09:55:50.88#ibcon#flushed, iclass 34, count 0 2006.201.09:55:50.88#ibcon#about to write, iclass 34, count 0 2006.201.09:55:50.88#ibcon#wrote, iclass 34, count 0 2006.201.09:55:50.88#ibcon#about to read 3, iclass 34, count 0 2006.201.09:55:50.90#ibcon#read 3, iclass 34, count 0 2006.201.09:55:50.90#ibcon#about to read 4, iclass 34, count 0 2006.201.09:55:50.90#ibcon#read 4, iclass 34, count 0 2006.201.09:55:50.90#ibcon#about to read 5, iclass 34, count 0 2006.201.09:55:50.90#ibcon#read 5, iclass 34, count 0 2006.201.09:55:50.90#ibcon#about to read 6, iclass 34, count 0 2006.201.09:55:50.90#ibcon#read 6, iclass 34, count 0 2006.201.09:55:50.90#ibcon#end of sib2, iclass 34, count 0 2006.201.09:55:50.90#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:55:50.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:55:50.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:55:50.90#ibcon#*before write, iclass 34, count 0 2006.201.09:55:50.90#ibcon#enter sib2, iclass 34, count 0 2006.201.09:55:50.90#ibcon#flushed, iclass 34, count 0 2006.201.09:55:50.90#ibcon#about to write, iclass 34, count 0 2006.201.09:55:50.90#ibcon#wrote, iclass 34, count 0 2006.201.09:55:50.90#ibcon#about to read 3, iclass 34, count 0 2006.201.09:55:50.95#ibcon#read 3, iclass 34, count 0 2006.201.09:55:50.95#ibcon#about to read 4, iclass 34, count 0 2006.201.09:55:50.95#ibcon#read 4, iclass 34, count 0 2006.201.09:55:50.95#ibcon#about to read 5, iclass 34, count 0 2006.201.09:55:50.95#ibcon#read 5, iclass 34, count 0 2006.201.09:55:50.95#ibcon#about to read 6, iclass 34, count 0 2006.201.09:55:50.95#ibcon#read 6, iclass 34, count 0 2006.201.09:55:50.95#ibcon#end of sib2, iclass 34, count 0 2006.201.09:55:50.95#ibcon#*after write, iclass 34, count 0 2006.201.09:55:50.95#ibcon#*before return 0, iclass 34, count 0 2006.201.09:55:50.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:50.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.09:55:50.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:55:50.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:55:50.95$vck44/vb=5,4 2006.201.09:55:50.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.09:55:50.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.09:55:50.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:50.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:51.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:51.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:51.00#ibcon#enter wrdev, iclass 36, count 2 2006.201.09:55:51.00#ibcon#first serial, iclass 36, count 2 2006.201.09:55:51.00#ibcon#enter sib2, iclass 36, count 2 2006.201.09:55:51.00#ibcon#flushed, iclass 36, count 2 2006.201.09:55:51.00#ibcon#about to write, iclass 36, count 2 2006.201.09:55:51.00#ibcon#wrote, iclass 36, count 2 2006.201.09:55:51.00#ibcon#about to read 3, iclass 36, count 2 2006.201.09:55:51.02#ibcon#read 3, iclass 36, count 2 2006.201.09:55:51.02#ibcon#about to read 4, iclass 36, count 2 2006.201.09:55:51.02#ibcon#read 4, iclass 36, count 2 2006.201.09:55:51.02#ibcon#about to read 5, iclass 36, count 2 2006.201.09:55:51.02#ibcon#read 5, iclass 36, count 2 2006.201.09:55:51.02#ibcon#about to read 6, iclass 36, count 2 2006.201.09:55:51.02#ibcon#read 6, iclass 36, count 2 2006.201.09:55:51.02#ibcon#end of sib2, iclass 36, count 2 2006.201.09:55:51.02#ibcon#*mode == 0, iclass 36, count 2 2006.201.09:55:51.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.09:55:51.02#ibcon#[27=AT05-04\r\n] 2006.201.09:55:51.02#ibcon#*before write, iclass 36, count 2 2006.201.09:55:51.02#ibcon#enter sib2, iclass 36, count 2 2006.201.09:55:51.02#ibcon#flushed, iclass 36, count 2 2006.201.09:55:51.02#ibcon#about to write, iclass 36, count 2 2006.201.09:55:51.02#ibcon#wrote, iclass 36, count 2 2006.201.09:55:51.02#ibcon#about to read 3, iclass 36, count 2 2006.201.09:55:51.05#ibcon#read 3, iclass 36, count 2 2006.201.09:55:51.05#ibcon#about to read 4, iclass 36, count 2 2006.201.09:55:51.05#ibcon#read 4, iclass 36, count 2 2006.201.09:55:51.05#ibcon#about to read 5, iclass 36, count 2 2006.201.09:55:51.05#ibcon#read 5, iclass 36, count 2 2006.201.09:55:51.05#ibcon#about to read 6, iclass 36, count 2 2006.201.09:55:51.05#ibcon#read 6, iclass 36, count 2 2006.201.09:55:51.05#ibcon#end of sib2, iclass 36, count 2 2006.201.09:55:51.05#ibcon#*after write, iclass 36, count 2 2006.201.09:55:51.05#ibcon#*before return 0, iclass 36, count 2 2006.201.09:55:51.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:51.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.09:55:51.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.09:55:51.05#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:51.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:51.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:51.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:51.17#ibcon#enter wrdev, iclass 36, count 0 2006.201.09:55:51.17#ibcon#first serial, iclass 36, count 0 2006.201.09:55:51.17#ibcon#enter sib2, iclass 36, count 0 2006.201.09:55:51.17#ibcon#flushed, iclass 36, count 0 2006.201.09:55:51.17#ibcon#about to write, iclass 36, count 0 2006.201.09:55:51.17#ibcon#wrote, iclass 36, count 0 2006.201.09:55:51.17#ibcon#about to read 3, iclass 36, count 0 2006.201.09:55:51.20#ibcon#read 3, iclass 36, count 0 2006.201.09:55:51.20#ibcon#about to read 4, iclass 36, count 0 2006.201.09:55:51.20#ibcon#read 4, iclass 36, count 0 2006.201.09:55:51.20#ibcon#about to read 5, iclass 36, count 0 2006.201.09:55:51.20#ibcon#read 5, iclass 36, count 0 2006.201.09:55:51.20#ibcon#about to read 6, iclass 36, count 0 2006.201.09:55:51.20#ibcon#read 6, iclass 36, count 0 2006.201.09:55:51.20#ibcon#end of sib2, iclass 36, count 0 2006.201.09:55:51.20#ibcon#*mode == 0, iclass 36, count 0 2006.201.09:55:51.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.09:55:51.20#ibcon#[27=USB\r\n] 2006.201.09:55:51.20#ibcon#*before write, iclass 36, count 0 2006.201.09:55:51.20#ibcon#enter sib2, iclass 36, count 0 2006.201.09:55:51.20#ibcon#flushed, iclass 36, count 0 2006.201.09:55:51.20#ibcon#about to write, iclass 36, count 0 2006.201.09:55:51.20#ibcon#wrote, iclass 36, count 0 2006.201.09:55:51.20#ibcon#about to read 3, iclass 36, count 0 2006.201.09:55:51.23#ibcon#read 3, iclass 36, count 0 2006.201.09:55:51.23#ibcon#about to read 4, iclass 36, count 0 2006.201.09:55:51.23#ibcon#read 4, iclass 36, count 0 2006.201.09:55:51.23#ibcon#about to read 5, iclass 36, count 0 2006.201.09:55:51.23#ibcon#read 5, iclass 36, count 0 2006.201.09:55:51.23#ibcon#about to read 6, iclass 36, count 0 2006.201.09:55:51.23#ibcon#read 6, iclass 36, count 0 2006.201.09:55:51.23#ibcon#end of sib2, iclass 36, count 0 2006.201.09:55:51.23#ibcon#*after write, iclass 36, count 0 2006.201.09:55:51.23#ibcon#*before return 0, iclass 36, count 0 2006.201.09:55:51.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:51.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.09:55:51.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.09:55:51.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.09:55:51.23$vck44/vblo=6,719.99 2006.201.09:55:51.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.09:55:51.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.09:55:51.23#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:51.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:51.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:51.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:51.23#ibcon#enter wrdev, iclass 38, count 0 2006.201.09:55:51.23#ibcon#first serial, iclass 38, count 0 2006.201.09:55:51.23#ibcon#enter sib2, iclass 38, count 0 2006.201.09:55:51.23#ibcon#flushed, iclass 38, count 0 2006.201.09:55:51.23#ibcon#about to write, iclass 38, count 0 2006.201.09:55:51.23#ibcon#wrote, iclass 38, count 0 2006.201.09:55:51.23#ibcon#about to read 3, iclass 38, count 0 2006.201.09:55:51.25#ibcon#read 3, iclass 38, count 0 2006.201.09:55:51.25#ibcon#about to read 4, iclass 38, count 0 2006.201.09:55:51.25#ibcon#read 4, iclass 38, count 0 2006.201.09:55:51.25#ibcon#about to read 5, iclass 38, count 0 2006.201.09:55:51.25#ibcon#read 5, iclass 38, count 0 2006.201.09:55:51.25#ibcon#about to read 6, iclass 38, count 0 2006.201.09:55:51.25#ibcon#read 6, iclass 38, count 0 2006.201.09:55:51.25#ibcon#end of sib2, iclass 38, count 0 2006.201.09:55:51.25#ibcon#*mode == 0, iclass 38, count 0 2006.201.09:55:51.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.09:55:51.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:55:51.25#ibcon#*before write, iclass 38, count 0 2006.201.09:55:51.25#ibcon#enter sib2, iclass 38, count 0 2006.201.09:55:51.25#ibcon#flushed, iclass 38, count 0 2006.201.09:55:51.25#ibcon#about to write, iclass 38, count 0 2006.201.09:55:51.25#ibcon#wrote, iclass 38, count 0 2006.201.09:55:51.25#ibcon#about to read 3, iclass 38, count 0 2006.201.09:55:51.29#ibcon#read 3, iclass 38, count 0 2006.201.09:55:51.29#ibcon#about to read 4, iclass 38, count 0 2006.201.09:55:51.29#ibcon#read 4, iclass 38, count 0 2006.201.09:55:51.29#ibcon#about to read 5, iclass 38, count 0 2006.201.09:55:51.29#ibcon#read 5, iclass 38, count 0 2006.201.09:55:51.29#ibcon#about to read 6, iclass 38, count 0 2006.201.09:55:51.29#ibcon#read 6, iclass 38, count 0 2006.201.09:55:51.29#ibcon#end of sib2, iclass 38, count 0 2006.201.09:55:51.29#ibcon#*after write, iclass 38, count 0 2006.201.09:55:51.29#ibcon#*before return 0, iclass 38, count 0 2006.201.09:55:51.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:51.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.09:55:51.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.09:55:51.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.09:55:51.29$vck44/vb=6,4 2006.201.09:55:51.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.09:55:51.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.09:55:51.29#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:51.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:51.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:51.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:51.35#ibcon#enter wrdev, iclass 40, count 2 2006.201.09:55:51.35#ibcon#first serial, iclass 40, count 2 2006.201.09:55:51.35#ibcon#enter sib2, iclass 40, count 2 2006.201.09:55:51.35#ibcon#flushed, iclass 40, count 2 2006.201.09:55:51.35#ibcon#about to write, iclass 40, count 2 2006.201.09:55:51.35#ibcon#wrote, iclass 40, count 2 2006.201.09:55:51.35#ibcon#about to read 3, iclass 40, count 2 2006.201.09:55:51.37#ibcon#read 3, iclass 40, count 2 2006.201.09:55:51.37#ibcon#about to read 4, iclass 40, count 2 2006.201.09:55:51.37#ibcon#read 4, iclass 40, count 2 2006.201.09:55:51.37#ibcon#about to read 5, iclass 40, count 2 2006.201.09:55:51.37#ibcon#read 5, iclass 40, count 2 2006.201.09:55:51.37#ibcon#about to read 6, iclass 40, count 2 2006.201.09:55:51.37#ibcon#read 6, iclass 40, count 2 2006.201.09:55:51.37#ibcon#end of sib2, iclass 40, count 2 2006.201.09:55:51.37#ibcon#*mode == 0, iclass 40, count 2 2006.201.09:55:51.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.09:55:51.37#ibcon#[27=AT06-04\r\n] 2006.201.09:55:51.37#ibcon#*before write, iclass 40, count 2 2006.201.09:55:51.37#ibcon#enter sib2, iclass 40, count 2 2006.201.09:55:51.37#ibcon#flushed, iclass 40, count 2 2006.201.09:55:51.37#ibcon#about to write, iclass 40, count 2 2006.201.09:55:51.37#ibcon#wrote, iclass 40, count 2 2006.201.09:55:51.37#ibcon#about to read 3, iclass 40, count 2 2006.201.09:55:51.40#ibcon#read 3, iclass 40, count 2 2006.201.09:55:51.40#ibcon#about to read 4, iclass 40, count 2 2006.201.09:55:51.40#ibcon#read 4, iclass 40, count 2 2006.201.09:55:51.40#ibcon#about to read 5, iclass 40, count 2 2006.201.09:55:51.40#ibcon#read 5, iclass 40, count 2 2006.201.09:55:51.40#ibcon#about to read 6, iclass 40, count 2 2006.201.09:55:51.40#ibcon#read 6, iclass 40, count 2 2006.201.09:55:51.40#ibcon#end of sib2, iclass 40, count 2 2006.201.09:55:51.40#ibcon#*after write, iclass 40, count 2 2006.201.09:55:51.40#ibcon#*before return 0, iclass 40, count 2 2006.201.09:55:51.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:51.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.09:55:51.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.09:55:51.40#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:51.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:51.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:51.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:51.52#ibcon#enter wrdev, iclass 40, count 0 2006.201.09:55:51.52#ibcon#first serial, iclass 40, count 0 2006.201.09:55:51.52#ibcon#enter sib2, iclass 40, count 0 2006.201.09:55:51.52#ibcon#flushed, iclass 40, count 0 2006.201.09:55:51.52#ibcon#about to write, iclass 40, count 0 2006.201.09:55:51.52#ibcon#wrote, iclass 40, count 0 2006.201.09:55:51.52#ibcon#about to read 3, iclass 40, count 0 2006.201.09:55:51.54#ibcon#read 3, iclass 40, count 0 2006.201.09:55:51.54#ibcon#about to read 4, iclass 40, count 0 2006.201.09:55:51.54#ibcon#read 4, iclass 40, count 0 2006.201.09:55:51.54#ibcon#about to read 5, iclass 40, count 0 2006.201.09:55:51.54#ibcon#read 5, iclass 40, count 0 2006.201.09:55:51.54#ibcon#about to read 6, iclass 40, count 0 2006.201.09:55:51.54#ibcon#read 6, iclass 40, count 0 2006.201.09:55:51.54#ibcon#end of sib2, iclass 40, count 0 2006.201.09:55:51.54#ibcon#*mode == 0, iclass 40, count 0 2006.201.09:55:51.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.09:55:51.54#ibcon#[27=USB\r\n] 2006.201.09:55:51.54#ibcon#*before write, iclass 40, count 0 2006.201.09:55:51.54#ibcon#enter sib2, iclass 40, count 0 2006.201.09:55:51.54#ibcon#flushed, iclass 40, count 0 2006.201.09:55:51.54#ibcon#about to write, iclass 40, count 0 2006.201.09:55:51.54#ibcon#wrote, iclass 40, count 0 2006.201.09:55:51.54#ibcon#about to read 3, iclass 40, count 0 2006.201.09:55:51.57#ibcon#read 3, iclass 40, count 0 2006.201.09:55:51.57#ibcon#about to read 4, iclass 40, count 0 2006.201.09:55:51.57#ibcon#read 4, iclass 40, count 0 2006.201.09:55:51.57#ibcon#about to read 5, iclass 40, count 0 2006.201.09:55:51.57#ibcon#read 5, iclass 40, count 0 2006.201.09:55:51.57#ibcon#about to read 6, iclass 40, count 0 2006.201.09:55:51.57#ibcon#read 6, iclass 40, count 0 2006.201.09:55:51.57#ibcon#end of sib2, iclass 40, count 0 2006.201.09:55:51.57#ibcon#*after write, iclass 40, count 0 2006.201.09:55:51.57#ibcon#*before return 0, iclass 40, count 0 2006.201.09:55:51.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:51.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.09:55:51.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.09:55:51.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.09:55:51.57$vck44/vblo=7,734.99 2006.201.09:55:51.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.09:55:51.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.09:55:51.57#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:51.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:51.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:51.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:51.57#ibcon#enter wrdev, iclass 4, count 0 2006.201.09:55:51.57#ibcon#first serial, iclass 4, count 0 2006.201.09:55:51.57#ibcon#enter sib2, iclass 4, count 0 2006.201.09:55:51.57#ibcon#flushed, iclass 4, count 0 2006.201.09:55:51.57#ibcon#about to write, iclass 4, count 0 2006.201.09:55:51.57#ibcon#wrote, iclass 4, count 0 2006.201.09:55:51.57#ibcon#about to read 3, iclass 4, count 0 2006.201.09:55:51.59#ibcon#read 3, iclass 4, count 0 2006.201.09:55:51.59#ibcon#about to read 4, iclass 4, count 0 2006.201.09:55:51.59#ibcon#read 4, iclass 4, count 0 2006.201.09:55:51.59#ibcon#about to read 5, iclass 4, count 0 2006.201.09:55:51.59#ibcon#read 5, iclass 4, count 0 2006.201.09:55:51.59#ibcon#about to read 6, iclass 4, count 0 2006.201.09:55:51.59#ibcon#read 6, iclass 4, count 0 2006.201.09:55:51.59#ibcon#end of sib2, iclass 4, count 0 2006.201.09:55:51.59#ibcon#*mode == 0, iclass 4, count 0 2006.201.09:55:51.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.09:55:51.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:55:51.59#ibcon#*before write, iclass 4, count 0 2006.201.09:55:51.59#ibcon#enter sib2, iclass 4, count 0 2006.201.09:55:51.59#ibcon#flushed, iclass 4, count 0 2006.201.09:55:51.59#ibcon#about to write, iclass 4, count 0 2006.201.09:55:51.59#ibcon#wrote, iclass 4, count 0 2006.201.09:55:51.59#ibcon#about to read 3, iclass 4, count 0 2006.201.09:55:51.63#ibcon#read 3, iclass 4, count 0 2006.201.09:55:51.63#ibcon#about to read 4, iclass 4, count 0 2006.201.09:55:51.63#ibcon#read 4, iclass 4, count 0 2006.201.09:55:51.63#ibcon#about to read 5, iclass 4, count 0 2006.201.09:55:51.63#ibcon#read 5, iclass 4, count 0 2006.201.09:55:51.63#ibcon#about to read 6, iclass 4, count 0 2006.201.09:55:51.63#ibcon#read 6, iclass 4, count 0 2006.201.09:55:51.63#ibcon#end of sib2, iclass 4, count 0 2006.201.09:55:51.63#ibcon#*after write, iclass 4, count 0 2006.201.09:55:51.63#ibcon#*before return 0, iclass 4, count 0 2006.201.09:55:51.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:51.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.09:55:51.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.09:55:51.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.09:55:51.63$vck44/vb=7,4 2006.201.09:55:51.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.09:55:51.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.09:55:51.63#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:51.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:51.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:51.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:51.69#ibcon#enter wrdev, iclass 6, count 2 2006.201.09:55:51.69#ibcon#first serial, iclass 6, count 2 2006.201.09:55:51.69#ibcon#enter sib2, iclass 6, count 2 2006.201.09:55:51.69#ibcon#flushed, iclass 6, count 2 2006.201.09:55:51.69#ibcon#about to write, iclass 6, count 2 2006.201.09:55:51.69#ibcon#wrote, iclass 6, count 2 2006.201.09:55:51.69#ibcon#about to read 3, iclass 6, count 2 2006.201.09:55:51.71#ibcon#read 3, iclass 6, count 2 2006.201.09:55:51.71#ibcon#about to read 4, iclass 6, count 2 2006.201.09:55:51.71#ibcon#read 4, iclass 6, count 2 2006.201.09:55:51.71#ibcon#about to read 5, iclass 6, count 2 2006.201.09:55:51.71#ibcon#read 5, iclass 6, count 2 2006.201.09:55:51.71#ibcon#about to read 6, iclass 6, count 2 2006.201.09:55:51.71#ibcon#read 6, iclass 6, count 2 2006.201.09:55:51.71#ibcon#end of sib2, iclass 6, count 2 2006.201.09:55:51.71#ibcon#*mode == 0, iclass 6, count 2 2006.201.09:55:51.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.09:55:51.71#ibcon#[27=AT07-04\r\n] 2006.201.09:55:51.71#ibcon#*before write, iclass 6, count 2 2006.201.09:55:51.71#ibcon#enter sib2, iclass 6, count 2 2006.201.09:55:51.71#ibcon#flushed, iclass 6, count 2 2006.201.09:55:51.71#ibcon#about to write, iclass 6, count 2 2006.201.09:55:51.71#ibcon#wrote, iclass 6, count 2 2006.201.09:55:51.71#ibcon#about to read 3, iclass 6, count 2 2006.201.09:55:51.74#ibcon#read 3, iclass 6, count 2 2006.201.09:55:51.74#ibcon#about to read 4, iclass 6, count 2 2006.201.09:55:51.74#ibcon#read 4, iclass 6, count 2 2006.201.09:55:51.74#ibcon#about to read 5, iclass 6, count 2 2006.201.09:55:51.74#ibcon#read 5, iclass 6, count 2 2006.201.09:55:51.74#ibcon#about to read 6, iclass 6, count 2 2006.201.09:55:51.74#ibcon#read 6, iclass 6, count 2 2006.201.09:55:51.74#ibcon#end of sib2, iclass 6, count 2 2006.201.09:55:51.74#ibcon#*after write, iclass 6, count 2 2006.201.09:55:51.74#ibcon#*before return 0, iclass 6, count 2 2006.201.09:55:51.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:51.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.09:55:51.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.09:55:51.74#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:51.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:51.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:51.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:51.86#ibcon#enter wrdev, iclass 6, count 0 2006.201.09:55:51.86#ibcon#first serial, iclass 6, count 0 2006.201.09:55:51.86#ibcon#enter sib2, iclass 6, count 0 2006.201.09:55:51.86#ibcon#flushed, iclass 6, count 0 2006.201.09:55:51.86#ibcon#about to write, iclass 6, count 0 2006.201.09:55:51.86#ibcon#wrote, iclass 6, count 0 2006.201.09:55:51.86#ibcon#about to read 3, iclass 6, count 0 2006.201.09:55:51.88#ibcon#read 3, iclass 6, count 0 2006.201.09:55:51.88#ibcon#about to read 4, iclass 6, count 0 2006.201.09:55:51.88#ibcon#read 4, iclass 6, count 0 2006.201.09:55:51.88#ibcon#about to read 5, iclass 6, count 0 2006.201.09:55:51.88#ibcon#read 5, iclass 6, count 0 2006.201.09:55:51.88#ibcon#about to read 6, iclass 6, count 0 2006.201.09:55:51.88#ibcon#read 6, iclass 6, count 0 2006.201.09:55:51.88#ibcon#end of sib2, iclass 6, count 0 2006.201.09:55:51.88#ibcon#*mode == 0, iclass 6, count 0 2006.201.09:55:51.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.09:55:51.88#ibcon#[27=USB\r\n] 2006.201.09:55:51.88#ibcon#*before write, iclass 6, count 0 2006.201.09:55:51.88#ibcon#enter sib2, iclass 6, count 0 2006.201.09:55:51.88#ibcon#flushed, iclass 6, count 0 2006.201.09:55:51.88#ibcon#about to write, iclass 6, count 0 2006.201.09:55:51.88#ibcon#wrote, iclass 6, count 0 2006.201.09:55:51.88#ibcon#about to read 3, iclass 6, count 0 2006.201.09:55:51.91#ibcon#read 3, iclass 6, count 0 2006.201.09:55:51.91#ibcon#about to read 4, iclass 6, count 0 2006.201.09:55:51.91#ibcon#read 4, iclass 6, count 0 2006.201.09:55:51.91#ibcon#about to read 5, iclass 6, count 0 2006.201.09:55:51.91#ibcon#read 5, iclass 6, count 0 2006.201.09:55:51.91#ibcon#about to read 6, iclass 6, count 0 2006.201.09:55:51.91#ibcon#read 6, iclass 6, count 0 2006.201.09:55:51.91#ibcon#end of sib2, iclass 6, count 0 2006.201.09:55:51.91#ibcon#*after write, iclass 6, count 0 2006.201.09:55:51.91#ibcon#*before return 0, iclass 6, count 0 2006.201.09:55:51.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:51.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.09:55:51.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.09:55:51.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.09:55:51.91$vck44/vblo=8,744.99 2006.201.09:55:51.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.09:55:51.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.09:55:51.91#ibcon#ireg 17 cls_cnt 0 2006.201.09:55:51.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:51.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:51.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:51.91#ibcon#enter wrdev, iclass 10, count 0 2006.201.09:55:51.91#ibcon#first serial, iclass 10, count 0 2006.201.09:55:51.91#ibcon#enter sib2, iclass 10, count 0 2006.201.09:55:51.91#ibcon#flushed, iclass 10, count 0 2006.201.09:55:51.91#ibcon#about to write, iclass 10, count 0 2006.201.09:55:51.91#ibcon#wrote, iclass 10, count 0 2006.201.09:55:51.91#ibcon#about to read 3, iclass 10, count 0 2006.201.09:55:51.93#ibcon#read 3, iclass 10, count 0 2006.201.09:55:51.93#ibcon#about to read 4, iclass 10, count 0 2006.201.09:55:51.93#ibcon#read 4, iclass 10, count 0 2006.201.09:55:51.93#ibcon#about to read 5, iclass 10, count 0 2006.201.09:55:51.93#ibcon#read 5, iclass 10, count 0 2006.201.09:55:51.93#ibcon#about to read 6, iclass 10, count 0 2006.201.09:55:51.93#ibcon#read 6, iclass 10, count 0 2006.201.09:55:51.93#ibcon#end of sib2, iclass 10, count 0 2006.201.09:55:51.93#ibcon#*mode == 0, iclass 10, count 0 2006.201.09:55:51.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.09:55:51.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:55:51.93#ibcon#*before write, iclass 10, count 0 2006.201.09:55:51.93#ibcon#enter sib2, iclass 10, count 0 2006.201.09:55:51.93#ibcon#flushed, iclass 10, count 0 2006.201.09:55:51.93#ibcon#about to write, iclass 10, count 0 2006.201.09:55:51.93#ibcon#wrote, iclass 10, count 0 2006.201.09:55:51.93#ibcon#about to read 3, iclass 10, count 0 2006.201.09:55:51.98#ibcon#read 3, iclass 10, count 0 2006.201.09:55:51.98#ibcon#about to read 4, iclass 10, count 0 2006.201.09:55:51.98#ibcon#read 4, iclass 10, count 0 2006.201.09:55:51.98#ibcon#about to read 5, iclass 10, count 0 2006.201.09:55:51.98#ibcon#read 5, iclass 10, count 0 2006.201.09:55:51.98#ibcon#about to read 6, iclass 10, count 0 2006.201.09:55:51.98#ibcon#read 6, iclass 10, count 0 2006.201.09:55:51.98#ibcon#end of sib2, iclass 10, count 0 2006.201.09:55:51.98#ibcon#*after write, iclass 10, count 0 2006.201.09:55:51.98#ibcon#*before return 0, iclass 10, count 0 2006.201.09:55:51.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:51.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.09:55:51.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.09:55:51.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.09:55:51.98$vck44/vb=8,4 2006.201.09:55:51.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.09:55:51.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.09:55:51.98#ibcon#ireg 11 cls_cnt 2 2006.201.09:55:51.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:52.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:52.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:52.03#ibcon#enter wrdev, iclass 12, count 2 2006.201.09:55:52.03#ibcon#first serial, iclass 12, count 2 2006.201.09:55:52.03#ibcon#enter sib2, iclass 12, count 2 2006.201.09:55:52.03#ibcon#flushed, iclass 12, count 2 2006.201.09:55:52.03#ibcon#about to write, iclass 12, count 2 2006.201.09:55:52.03#ibcon#wrote, iclass 12, count 2 2006.201.09:55:52.03#ibcon#about to read 3, iclass 12, count 2 2006.201.09:55:52.05#ibcon#read 3, iclass 12, count 2 2006.201.09:55:52.05#ibcon#about to read 4, iclass 12, count 2 2006.201.09:55:52.05#ibcon#read 4, iclass 12, count 2 2006.201.09:55:52.05#ibcon#about to read 5, iclass 12, count 2 2006.201.09:55:52.05#ibcon#read 5, iclass 12, count 2 2006.201.09:55:52.05#ibcon#about to read 6, iclass 12, count 2 2006.201.09:55:52.05#ibcon#read 6, iclass 12, count 2 2006.201.09:55:52.05#ibcon#end of sib2, iclass 12, count 2 2006.201.09:55:52.05#ibcon#*mode == 0, iclass 12, count 2 2006.201.09:55:52.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.09:55:52.05#ibcon#[27=AT08-04\r\n] 2006.201.09:55:52.05#ibcon#*before write, iclass 12, count 2 2006.201.09:55:52.05#ibcon#enter sib2, iclass 12, count 2 2006.201.09:55:52.05#ibcon#flushed, iclass 12, count 2 2006.201.09:55:52.05#ibcon#about to write, iclass 12, count 2 2006.201.09:55:52.05#ibcon#wrote, iclass 12, count 2 2006.201.09:55:52.05#ibcon#about to read 3, iclass 12, count 2 2006.201.09:55:52.08#ibcon#read 3, iclass 12, count 2 2006.201.09:55:52.08#ibcon#about to read 4, iclass 12, count 2 2006.201.09:55:52.08#ibcon#read 4, iclass 12, count 2 2006.201.09:55:52.08#ibcon#about to read 5, iclass 12, count 2 2006.201.09:55:52.08#ibcon#read 5, iclass 12, count 2 2006.201.09:55:52.08#ibcon#about to read 6, iclass 12, count 2 2006.201.09:55:52.08#ibcon#read 6, iclass 12, count 2 2006.201.09:55:52.08#ibcon#end of sib2, iclass 12, count 2 2006.201.09:55:52.08#ibcon#*after write, iclass 12, count 2 2006.201.09:55:52.08#ibcon#*before return 0, iclass 12, count 2 2006.201.09:55:52.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:52.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.09:55:52.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.09:55:52.08#ibcon#ireg 7 cls_cnt 0 2006.201.09:55:52.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:52.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:52.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:52.20#ibcon#enter wrdev, iclass 12, count 0 2006.201.09:55:52.20#ibcon#first serial, iclass 12, count 0 2006.201.09:55:52.20#ibcon#enter sib2, iclass 12, count 0 2006.201.09:55:52.20#ibcon#flushed, iclass 12, count 0 2006.201.09:55:52.20#ibcon#about to write, iclass 12, count 0 2006.201.09:55:52.20#ibcon#wrote, iclass 12, count 0 2006.201.09:55:52.20#ibcon#about to read 3, iclass 12, count 0 2006.201.09:55:52.22#ibcon#read 3, iclass 12, count 0 2006.201.09:55:52.22#ibcon#about to read 4, iclass 12, count 0 2006.201.09:55:52.22#ibcon#read 4, iclass 12, count 0 2006.201.09:55:52.22#ibcon#about to read 5, iclass 12, count 0 2006.201.09:55:52.22#ibcon#read 5, iclass 12, count 0 2006.201.09:55:52.22#ibcon#about to read 6, iclass 12, count 0 2006.201.09:55:52.22#ibcon#read 6, iclass 12, count 0 2006.201.09:55:52.22#ibcon#end of sib2, iclass 12, count 0 2006.201.09:55:52.22#ibcon#*mode == 0, iclass 12, count 0 2006.201.09:55:52.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.09:55:52.22#ibcon#[27=USB\r\n] 2006.201.09:55:52.22#ibcon#*before write, iclass 12, count 0 2006.201.09:55:52.22#ibcon#enter sib2, iclass 12, count 0 2006.201.09:55:52.22#ibcon#flushed, iclass 12, count 0 2006.201.09:55:52.22#ibcon#about to write, iclass 12, count 0 2006.201.09:55:52.22#ibcon#wrote, iclass 12, count 0 2006.201.09:55:52.22#ibcon#about to read 3, iclass 12, count 0 2006.201.09:55:52.25#ibcon#read 3, iclass 12, count 0 2006.201.09:55:52.25#ibcon#about to read 4, iclass 12, count 0 2006.201.09:55:52.25#ibcon#read 4, iclass 12, count 0 2006.201.09:55:52.25#ibcon#about to read 5, iclass 12, count 0 2006.201.09:55:52.25#ibcon#read 5, iclass 12, count 0 2006.201.09:55:52.25#ibcon#about to read 6, iclass 12, count 0 2006.201.09:55:52.25#ibcon#read 6, iclass 12, count 0 2006.201.09:55:52.25#ibcon#end of sib2, iclass 12, count 0 2006.201.09:55:52.25#ibcon#*after write, iclass 12, count 0 2006.201.09:55:52.25#ibcon#*before return 0, iclass 12, count 0 2006.201.09:55:52.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:52.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.09:55:52.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.09:55:52.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.09:55:52.25$vck44/vabw=wide 2006.201.09:55:52.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.09:55:52.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.09:55:52.25#ibcon#ireg 8 cls_cnt 0 2006.201.09:55:52.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:52.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:52.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:52.25#ibcon#enter wrdev, iclass 14, count 0 2006.201.09:55:52.25#ibcon#first serial, iclass 14, count 0 2006.201.09:55:52.25#ibcon#enter sib2, iclass 14, count 0 2006.201.09:55:52.25#ibcon#flushed, iclass 14, count 0 2006.201.09:55:52.25#ibcon#about to write, iclass 14, count 0 2006.201.09:55:52.25#ibcon#wrote, iclass 14, count 0 2006.201.09:55:52.25#ibcon#about to read 3, iclass 14, count 0 2006.201.09:55:52.27#ibcon#read 3, iclass 14, count 0 2006.201.09:55:52.27#ibcon#about to read 4, iclass 14, count 0 2006.201.09:55:52.27#ibcon#read 4, iclass 14, count 0 2006.201.09:55:52.27#ibcon#about to read 5, iclass 14, count 0 2006.201.09:55:52.27#ibcon#read 5, iclass 14, count 0 2006.201.09:55:52.27#ibcon#about to read 6, iclass 14, count 0 2006.201.09:55:52.27#ibcon#read 6, iclass 14, count 0 2006.201.09:55:52.27#ibcon#end of sib2, iclass 14, count 0 2006.201.09:55:52.27#ibcon#*mode == 0, iclass 14, count 0 2006.201.09:55:52.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.09:55:52.27#ibcon#[25=BW32\r\n] 2006.201.09:55:52.27#ibcon#*before write, iclass 14, count 0 2006.201.09:55:52.27#ibcon#enter sib2, iclass 14, count 0 2006.201.09:55:52.27#ibcon#flushed, iclass 14, count 0 2006.201.09:55:52.27#ibcon#about to write, iclass 14, count 0 2006.201.09:55:52.27#ibcon#wrote, iclass 14, count 0 2006.201.09:55:52.27#ibcon#about to read 3, iclass 14, count 0 2006.201.09:55:52.30#ibcon#read 3, iclass 14, count 0 2006.201.09:55:52.30#ibcon#about to read 4, iclass 14, count 0 2006.201.09:55:52.30#ibcon#read 4, iclass 14, count 0 2006.201.09:55:52.30#ibcon#about to read 5, iclass 14, count 0 2006.201.09:55:52.30#ibcon#read 5, iclass 14, count 0 2006.201.09:55:52.30#ibcon#about to read 6, iclass 14, count 0 2006.201.09:55:52.30#ibcon#read 6, iclass 14, count 0 2006.201.09:55:52.30#ibcon#end of sib2, iclass 14, count 0 2006.201.09:55:52.30#ibcon#*after write, iclass 14, count 0 2006.201.09:55:52.30#ibcon#*before return 0, iclass 14, count 0 2006.201.09:55:52.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:52.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.09:55:52.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.09:55:52.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.09:55:52.30$vck44/vbbw=wide 2006.201.09:55:52.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.09:55:52.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.09:55:52.30#ibcon#ireg 8 cls_cnt 0 2006.201.09:55:52.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:55:52.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:55:52.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:55:52.37#ibcon#enter wrdev, iclass 16, count 0 2006.201.09:55:52.37#ibcon#first serial, iclass 16, count 0 2006.201.09:55:52.37#ibcon#enter sib2, iclass 16, count 0 2006.201.09:55:52.37#ibcon#flushed, iclass 16, count 0 2006.201.09:55:52.37#ibcon#about to write, iclass 16, count 0 2006.201.09:55:52.37#ibcon#wrote, iclass 16, count 0 2006.201.09:55:52.37#ibcon#about to read 3, iclass 16, count 0 2006.201.09:55:52.39#ibcon#read 3, iclass 16, count 0 2006.201.09:55:52.39#ibcon#about to read 4, iclass 16, count 0 2006.201.09:55:52.39#ibcon#read 4, iclass 16, count 0 2006.201.09:55:52.39#ibcon#about to read 5, iclass 16, count 0 2006.201.09:55:52.39#ibcon#read 5, iclass 16, count 0 2006.201.09:55:52.39#ibcon#about to read 6, iclass 16, count 0 2006.201.09:55:52.39#ibcon#read 6, iclass 16, count 0 2006.201.09:55:52.39#ibcon#end of sib2, iclass 16, count 0 2006.201.09:55:52.39#ibcon#*mode == 0, iclass 16, count 0 2006.201.09:55:52.39#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.09:55:52.39#ibcon#[27=BW32\r\n] 2006.201.09:55:52.39#ibcon#*before write, iclass 16, count 0 2006.201.09:55:52.39#ibcon#enter sib2, iclass 16, count 0 2006.201.09:55:52.39#ibcon#flushed, iclass 16, count 0 2006.201.09:55:52.39#ibcon#about to write, iclass 16, count 0 2006.201.09:55:52.39#ibcon#wrote, iclass 16, count 0 2006.201.09:55:52.39#ibcon#about to read 3, iclass 16, count 0 2006.201.09:55:52.42#ibcon#read 3, iclass 16, count 0 2006.201.09:55:52.42#ibcon#about to read 4, iclass 16, count 0 2006.201.09:55:52.42#ibcon#read 4, iclass 16, count 0 2006.201.09:55:52.42#ibcon#about to read 5, iclass 16, count 0 2006.201.09:55:52.42#ibcon#read 5, iclass 16, count 0 2006.201.09:55:52.42#ibcon#about to read 6, iclass 16, count 0 2006.201.09:55:52.42#ibcon#read 6, iclass 16, count 0 2006.201.09:55:52.42#ibcon#end of sib2, iclass 16, count 0 2006.201.09:55:52.42#ibcon#*after write, iclass 16, count 0 2006.201.09:55:52.42#ibcon#*before return 0, iclass 16, count 0 2006.201.09:55:52.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:55:52.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.09:55:52.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.09:55:52.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.09:55:52.42$setupk4/ifdk4 2006.201.09:55:52.42$ifdk4/lo= 2006.201.09:55:52.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:55:52.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:55:52.42$ifdk4/patch= 2006.201.09:55:52.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:55:52.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:55:52.42$setupk4/!*+20s 2006.201.09:55:53.33#abcon#<5=/05 2.6 5.1 22.27 951003.6\r\n> 2006.201.09:55:53.35#abcon#{5=INTERFACE CLEAR} 2006.201.09:55:53.41#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:56:03.50#abcon#<5=/05 2.7 5.1 22.27 951003.6\r\n> 2006.201.09:56:03.52#abcon#{5=INTERFACE CLEAR} 2006.201.09:56:03.58#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:56:06.89$setupk4/"tpicd 2006.201.09:56:06.89$setupk4/echo=off 2006.201.09:56:06.89$setupk4/xlog=off 2006.201.09:56:06.89:!2006.201.09:57:10 2006.201.09:56:13.14#trakl#Source acquired 2006.201.09:56:15.14#flagr#flagr/antenna,acquired 2006.201.09:57:10.00:preob 2006.201.09:57:10.14/onsource/TRACKING 2006.201.09:57:10.14:!2006.201.09:57:20 2006.201.09:57:20.00:"tape 2006.201.09:57:20.00:"st=record 2006.201.09:57:20.00:data_valid=on 2006.201.09:57:20.00:midob 2006.201.09:57:21.14/onsource/TRACKING 2006.201.09:57:21.14/wx/22.25,1003.6,95 2006.201.09:57:21.25/cable/+6.4679E-03 2006.201.09:57:22.34/va/01,08,usb,yes,28,31 2006.201.09:57:22.34/va/02,07,usb,yes,31,31 2006.201.09:57:22.34/va/03,08,usb,yes,28,29 2006.201.09:57:22.34/va/04,07,usb,yes,31,33 2006.201.09:57:22.34/va/05,04,usb,yes,28,28 2006.201.09:57:22.34/va/06,05,usb,yes,28,28 2006.201.09:57:22.34/va/07,05,usb,yes,27,28 2006.201.09:57:22.34/va/08,04,usb,yes,27,32 2006.201.09:57:22.57/valo/01,524.99,yes,locked 2006.201.09:57:22.57/valo/02,534.99,yes,locked 2006.201.09:57:22.57/valo/03,564.99,yes,locked 2006.201.09:57:22.57/valo/04,624.99,yes,locked 2006.201.09:57:22.57/valo/05,734.99,yes,locked 2006.201.09:57:22.57/valo/06,814.99,yes,locked 2006.201.09:57:22.57/valo/07,864.99,yes,locked 2006.201.09:57:22.57/valo/08,884.99,yes,locked 2006.201.09:57:23.66/vb/01,04,usb,yes,29,27 2006.201.09:57:23.66/vb/02,05,usb,yes,27,27 2006.201.09:57:23.66/vb/03,04,usb,yes,28,31 2006.201.09:57:23.66/vb/04,05,usb,yes,28,27 2006.201.09:57:23.66/vb/05,04,usb,yes,25,27 2006.201.09:57:23.66/vb/06,04,usb,yes,29,25 2006.201.09:57:23.66/vb/07,04,usb,yes,29,29 2006.201.09:57:23.66/vb/08,04,usb,yes,27,30 2006.201.09:57:23.89/vblo/01,629.99,yes,locked 2006.201.09:57:23.89/vblo/02,634.99,yes,locked 2006.201.09:57:23.89/vblo/03,649.99,yes,locked 2006.201.09:57:23.89/vblo/04,679.99,yes,locked 2006.201.09:57:23.89/vblo/05,709.99,yes,locked 2006.201.09:57:23.89/vblo/06,719.99,yes,locked 2006.201.09:57:23.89/vblo/07,734.99,yes,locked 2006.201.09:57:23.89/vblo/08,744.99,yes,locked 2006.201.09:57:24.04/vabw/8 2006.201.09:57:24.19/vbbw/8 2006.201.09:57:24.29/xfe/off,on,16.0 2006.201.09:57:24.66/ifatt/23,28,28,28 2006.201.09:57:25.05/fmout-gps/S +4.58E-07 2006.201.09:57:25.12:!2006.201.09:58:00 2006.201.09:58:00.00:data_valid=off 2006.201.09:58:00.00:"et 2006.201.09:58:00.00:!+3s 2006.201.09:58:03.02:"tape 2006.201.09:58:03.02:postob 2006.201.09:58:03.11/cable/+6.4655E-03 2006.201.09:58:03.11/wx/22.23,1003.6,94 2006.201.09:58:03.17/fmout-gps/S +4.58E-07 2006.201.09:58:03.17:scan_name=201-0959,jd0607,100 2006.201.09:58:03.17:source=1334-127,133739.78,-125724.7,2000.0,cw 2006.201.09:58:05.14#flagr#flagr/antenna,new-source 2006.201.09:58:05.14:checkk5 2006.201.09:58:05.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.09:58:05.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.09:58:06.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.09:58:06.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.09:58:07.00/chk_obsdata//k5ts1/T2010957??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.09:58:07.37/chk_obsdata//k5ts2/T2010957??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.09:58:07.73/chk_obsdata//k5ts3/T2010957??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.09:58:08.10/chk_obsdata//k5ts4/T2010957??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.09:58:08.79/k5log//k5ts1_log_newline 2006.201.09:58:09.48/k5log//k5ts2_log_newline 2006.201.09:58:10.16/k5log//k5ts3_log_newline 2006.201.09:58:10.85/k5log//k5ts4_log_newline 2006.201.09:58:10.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.09:58:10.88:setupk4=1 2006.201.09:58:10.88$setupk4/echo=on 2006.201.09:58:10.88$setupk4/pcalon 2006.201.09:58:10.88$pcalon/"no phase cal control is implemented here 2006.201.09:58:10.88$setupk4/"tpicd=stop 2006.201.09:58:10.88$setupk4/"rec=synch_on 2006.201.09:58:10.88$setupk4/"rec_mode=128 2006.201.09:58:10.88$setupk4/!* 2006.201.09:58:10.88$setupk4/recpk4 2006.201.09:58:10.88$recpk4/recpatch= 2006.201.09:58:10.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.09:58:10.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.09:58:10.88$setupk4/vck44 2006.201.09:58:10.88$vck44/valo=1,524.99 2006.201.09:58:10.88#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.09:58:10.88#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.09:58:10.88#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:10.88#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:10.88#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:10.88#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:10.88#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:58:10.88#ibcon#first serial, iclass 2, count 0 2006.201.09:58:10.88#ibcon#enter sib2, iclass 2, count 0 2006.201.09:58:10.88#ibcon#flushed, iclass 2, count 0 2006.201.09:58:10.88#ibcon#about to write, iclass 2, count 0 2006.201.09:58:10.88#ibcon#wrote, iclass 2, count 0 2006.201.09:58:10.88#ibcon#about to read 3, iclass 2, count 0 2006.201.09:58:10.92#ibcon#read 3, iclass 2, count 0 2006.201.09:58:10.92#ibcon#about to read 4, iclass 2, count 0 2006.201.09:58:10.92#ibcon#read 4, iclass 2, count 0 2006.201.09:58:10.92#ibcon#about to read 5, iclass 2, count 0 2006.201.09:58:10.92#ibcon#read 5, iclass 2, count 0 2006.201.09:58:10.92#ibcon#about to read 6, iclass 2, count 0 2006.201.09:58:10.92#ibcon#read 6, iclass 2, count 0 2006.201.09:58:10.92#ibcon#end of sib2, iclass 2, count 0 2006.201.09:58:10.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:58:10.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:58:10.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.09:58:10.92#ibcon#*before write, iclass 2, count 0 2006.201.09:58:10.92#ibcon#enter sib2, iclass 2, count 0 2006.201.09:58:10.92#ibcon#flushed, iclass 2, count 0 2006.201.09:58:10.92#ibcon#about to write, iclass 2, count 0 2006.201.09:58:10.92#ibcon#wrote, iclass 2, count 0 2006.201.09:58:10.92#ibcon#about to read 3, iclass 2, count 0 2006.201.09:58:10.97#ibcon#read 3, iclass 2, count 0 2006.201.09:58:10.97#ibcon#about to read 4, iclass 2, count 0 2006.201.09:58:10.97#ibcon#read 4, iclass 2, count 0 2006.201.09:58:10.97#ibcon#about to read 5, iclass 2, count 0 2006.201.09:58:10.97#ibcon#read 5, iclass 2, count 0 2006.201.09:58:10.97#ibcon#about to read 6, iclass 2, count 0 2006.201.09:58:10.97#ibcon#read 6, iclass 2, count 0 2006.201.09:58:10.97#ibcon#end of sib2, iclass 2, count 0 2006.201.09:58:10.97#ibcon#*after write, iclass 2, count 0 2006.201.09:58:10.97#ibcon#*before return 0, iclass 2, count 0 2006.201.09:58:10.97#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:10.97#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:10.97#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:58:10.97#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:58:10.97$vck44/va=1,8 2006.201.09:58:10.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.09:58:10.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.09:58:10.97#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:10.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:10.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:10.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:10.97#ibcon#enter wrdev, iclass 5, count 2 2006.201.09:58:10.97#ibcon#first serial, iclass 5, count 2 2006.201.09:58:10.97#ibcon#enter sib2, iclass 5, count 2 2006.201.09:58:10.97#ibcon#flushed, iclass 5, count 2 2006.201.09:58:10.97#ibcon#about to write, iclass 5, count 2 2006.201.09:58:10.97#ibcon#wrote, iclass 5, count 2 2006.201.09:58:10.97#ibcon#about to read 3, iclass 5, count 2 2006.201.09:58:10.99#ibcon#read 3, iclass 5, count 2 2006.201.09:58:10.99#ibcon#about to read 4, iclass 5, count 2 2006.201.09:58:10.99#ibcon#read 4, iclass 5, count 2 2006.201.09:58:10.99#ibcon#about to read 5, iclass 5, count 2 2006.201.09:58:10.99#ibcon#read 5, iclass 5, count 2 2006.201.09:58:10.99#ibcon#about to read 6, iclass 5, count 2 2006.201.09:58:10.99#ibcon#read 6, iclass 5, count 2 2006.201.09:58:10.99#ibcon#end of sib2, iclass 5, count 2 2006.201.09:58:10.99#ibcon#*mode == 0, iclass 5, count 2 2006.201.09:58:10.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.09:58:10.99#ibcon#[25=AT01-08\r\n] 2006.201.09:58:10.99#ibcon#*before write, iclass 5, count 2 2006.201.09:58:10.99#ibcon#enter sib2, iclass 5, count 2 2006.201.09:58:10.99#ibcon#flushed, iclass 5, count 2 2006.201.09:58:10.99#ibcon#about to write, iclass 5, count 2 2006.201.09:58:10.99#ibcon#wrote, iclass 5, count 2 2006.201.09:58:10.99#ibcon#about to read 3, iclass 5, count 2 2006.201.09:58:11.02#ibcon#read 3, iclass 5, count 2 2006.201.09:58:11.02#ibcon#about to read 4, iclass 5, count 2 2006.201.09:58:11.02#ibcon#read 4, iclass 5, count 2 2006.201.09:58:11.02#ibcon#about to read 5, iclass 5, count 2 2006.201.09:58:11.02#ibcon#read 5, iclass 5, count 2 2006.201.09:58:11.02#ibcon#about to read 6, iclass 5, count 2 2006.201.09:58:11.02#ibcon#read 6, iclass 5, count 2 2006.201.09:58:11.02#ibcon#end of sib2, iclass 5, count 2 2006.201.09:58:11.02#ibcon#*after write, iclass 5, count 2 2006.201.09:58:11.02#ibcon#*before return 0, iclass 5, count 2 2006.201.09:58:11.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:11.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:11.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.09:58:11.02#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:11.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:11.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:11.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:11.14#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:58:11.14#ibcon#first serial, iclass 5, count 0 2006.201.09:58:11.14#ibcon#enter sib2, iclass 5, count 0 2006.201.09:58:11.14#ibcon#flushed, iclass 5, count 0 2006.201.09:58:11.14#ibcon#about to write, iclass 5, count 0 2006.201.09:58:11.14#ibcon#wrote, iclass 5, count 0 2006.201.09:58:11.14#ibcon#about to read 3, iclass 5, count 0 2006.201.09:58:11.16#ibcon#read 3, iclass 5, count 0 2006.201.09:58:11.16#ibcon#about to read 4, iclass 5, count 0 2006.201.09:58:11.16#ibcon#read 4, iclass 5, count 0 2006.201.09:58:11.16#ibcon#about to read 5, iclass 5, count 0 2006.201.09:58:11.16#ibcon#read 5, iclass 5, count 0 2006.201.09:58:11.16#ibcon#about to read 6, iclass 5, count 0 2006.201.09:58:11.16#ibcon#read 6, iclass 5, count 0 2006.201.09:58:11.16#ibcon#end of sib2, iclass 5, count 0 2006.201.09:58:11.16#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:58:11.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:58:11.16#ibcon#[25=USB\r\n] 2006.201.09:58:11.16#ibcon#*before write, iclass 5, count 0 2006.201.09:58:11.16#ibcon#enter sib2, iclass 5, count 0 2006.201.09:58:11.16#ibcon#flushed, iclass 5, count 0 2006.201.09:58:11.16#ibcon#about to write, iclass 5, count 0 2006.201.09:58:11.16#ibcon#wrote, iclass 5, count 0 2006.201.09:58:11.16#ibcon#about to read 3, iclass 5, count 0 2006.201.09:58:11.19#ibcon#read 3, iclass 5, count 0 2006.201.09:58:11.19#ibcon#about to read 4, iclass 5, count 0 2006.201.09:58:11.19#ibcon#read 4, iclass 5, count 0 2006.201.09:58:11.19#ibcon#about to read 5, iclass 5, count 0 2006.201.09:58:11.19#ibcon#read 5, iclass 5, count 0 2006.201.09:58:11.19#ibcon#about to read 6, iclass 5, count 0 2006.201.09:58:11.19#ibcon#read 6, iclass 5, count 0 2006.201.09:58:11.19#ibcon#end of sib2, iclass 5, count 0 2006.201.09:58:11.19#ibcon#*after write, iclass 5, count 0 2006.201.09:58:11.19#ibcon#*before return 0, iclass 5, count 0 2006.201.09:58:11.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:11.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:11.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:58:11.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:58:11.19$vck44/valo=2,534.99 2006.201.09:58:11.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.09:58:11.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.09:58:11.19#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:11.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:11.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:11.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:11.19#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:58:11.19#ibcon#first serial, iclass 7, count 0 2006.201.09:58:11.19#ibcon#enter sib2, iclass 7, count 0 2006.201.09:58:11.19#ibcon#flushed, iclass 7, count 0 2006.201.09:58:11.19#ibcon#about to write, iclass 7, count 0 2006.201.09:58:11.19#ibcon#wrote, iclass 7, count 0 2006.201.09:58:11.19#ibcon#about to read 3, iclass 7, count 0 2006.201.09:58:11.21#ibcon#read 3, iclass 7, count 0 2006.201.09:58:11.21#ibcon#about to read 4, iclass 7, count 0 2006.201.09:58:11.21#ibcon#read 4, iclass 7, count 0 2006.201.09:58:11.21#ibcon#about to read 5, iclass 7, count 0 2006.201.09:58:11.21#ibcon#read 5, iclass 7, count 0 2006.201.09:58:11.21#ibcon#about to read 6, iclass 7, count 0 2006.201.09:58:11.21#ibcon#read 6, iclass 7, count 0 2006.201.09:58:11.21#ibcon#end of sib2, iclass 7, count 0 2006.201.09:58:11.21#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:58:11.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:58:11.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.09:58:11.21#ibcon#*before write, iclass 7, count 0 2006.201.09:58:11.21#ibcon#enter sib2, iclass 7, count 0 2006.201.09:58:11.21#ibcon#flushed, iclass 7, count 0 2006.201.09:58:11.21#ibcon#about to write, iclass 7, count 0 2006.201.09:58:11.21#ibcon#wrote, iclass 7, count 0 2006.201.09:58:11.21#ibcon#about to read 3, iclass 7, count 0 2006.201.09:58:11.26#ibcon#read 3, iclass 7, count 0 2006.201.09:58:11.26#ibcon#about to read 4, iclass 7, count 0 2006.201.09:58:11.26#ibcon#read 4, iclass 7, count 0 2006.201.09:58:11.26#ibcon#about to read 5, iclass 7, count 0 2006.201.09:58:11.26#ibcon#read 5, iclass 7, count 0 2006.201.09:58:11.26#ibcon#about to read 6, iclass 7, count 0 2006.201.09:58:11.26#ibcon#read 6, iclass 7, count 0 2006.201.09:58:11.26#ibcon#end of sib2, iclass 7, count 0 2006.201.09:58:11.26#ibcon#*after write, iclass 7, count 0 2006.201.09:58:11.26#ibcon#*before return 0, iclass 7, count 0 2006.201.09:58:11.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:11.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:11.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:58:11.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:58:11.26$vck44/va=2,7 2006.201.09:58:11.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.09:58:11.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.09:58:11.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:11.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:11.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:11.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:11.31#ibcon#enter wrdev, iclass 11, count 2 2006.201.09:58:11.31#ibcon#first serial, iclass 11, count 2 2006.201.09:58:11.31#ibcon#enter sib2, iclass 11, count 2 2006.201.09:58:11.31#ibcon#flushed, iclass 11, count 2 2006.201.09:58:11.31#ibcon#about to write, iclass 11, count 2 2006.201.09:58:11.31#ibcon#wrote, iclass 11, count 2 2006.201.09:58:11.31#ibcon#about to read 3, iclass 11, count 2 2006.201.09:58:11.33#ibcon#read 3, iclass 11, count 2 2006.201.09:58:11.33#ibcon#about to read 4, iclass 11, count 2 2006.201.09:58:11.33#ibcon#read 4, iclass 11, count 2 2006.201.09:58:11.33#ibcon#about to read 5, iclass 11, count 2 2006.201.09:58:11.33#ibcon#read 5, iclass 11, count 2 2006.201.09:58:11.33#ibcon#about to read 6, iclass 11, count 2 2006.201.09:58:11.33#ibcon#read 6, iclass 11, count 2 2006.201.09:58:11.33#ibcon#end of sib2, iclass 11, count 2 2006.201.09:58:11.33#ibcon#*mode == 0, iclass 11, count 2 2006.201.09:58:11.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.09:58:11.33#ibcon#[25=AT02-07\r\n] 2006.201.09:58:11.33#ibcon#*before write, iclass 11, count 2 2006.201.09:58:11.33#ibcon#enter sib2, iclass 11, count 2 2006.201.09:58:11.33#ibcon#flushed, iclass 11, count 2 2006.201.09:58:11.33#ibcon#about to write, iclass 11, count 2 2006.201.09:58:11.33#ibcon#wrote, iclass 11, count 2 2006.201.09:58:11.33#ibcon#about to read 3, iclass 11, count 2 2006.201.09:58:11.36#ibcon#read 3, iclass 11, count 2 2006.201.09:58:11.36#ibcon#about to read 4, iclass 11, count 2 2006.201.09:58:11.36#ibcon#read 4, iclass 11, count 2 2006.201.09:58:11.36#ibcon#about to read 5, iclass 11, count 2 2006.201.09:58:11.36#ibcon#read 5, iclass 11, count 2 2006.201.09:58:11.36#ibcon#about to read 6, iclass 11, count 2 2006.201.09:58:11.36#ibcon#read 6, iclass 11, count 2 2006.201.09:58:11.36#ibcon#end of sib2, iclass 11, count 2 2006.201.09:58:11.36#ibcon#*after write, iclass 11, count 2 2006.201.09:58:11.36#ibcon#*before return 0, iclass 11, count 2 2006.201.09:58:11.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:11.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:11.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.09:58:11.36#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:11.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:11.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:11.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:11.48#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:58:11.48#ibcon#first serial, iclass 11, count 0 2006.201.09:58:11.48#ibcon#enter sib2, iclass 11, count 0 2006.201.09:58:11.48#ibcon#flushed, iclass 11, count 0 2006.201.09:58:11.48#ibcon#about to write, iclass 11, count 0 2006.201.09:58:11.48#ibcon#wrote, iclass 11, count 0 2006.201.09:58:11.48#ibcon#about to read 3, iclass 11, count 0 2006.201.09:58:11.50#ibcon#read 3, iclass 11, count 0 2006.201.09:58:11.50#ibcon#about to read 4, iclass 11, count 0 2006.201.09:58:11.50#ibcon#read 4, iclass 11, count 0 2006.201.09:58:11.50#ibcon#about to read 5, iclass 11, count 0 2006.201.09:58:11.50#ibcon#read 5, iclass 11, count 0 2006.201.09:58:11.50#ibcon#about to read 6, iclass 11, count 0 2006.201.09:58:11.50#ibcon#read 6, iclass 11, count 0 2006.201.09:58:11.50#ibcon#end of sib2, iclass 11, count 0 2006.201.09:58:11.50#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:58:11.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:58:11.50#ibcon#[25=USB\r\n] 2006.201.09:58:11.50#ibcon#*before write, iclass 11, count 0 2006.201.09:58:11.50#ibcon#enter sib2, iclass 11, count 0 2006.201.09:58:11.50#ibcon#flushed, iclass 11, count 0 2006.201.09:58:11.50#ibcon#about to write, iclass 11, count 0 2006.201.09:58:11.50#ibcon#wrote, iclass 11, count 0 2006.201.09:58:11.50#ibcon#about to read 3, iclass 11, count 0 2006.201.09:58:11.53#ibcon#read 3, iclass 11, count 0 2006.201.09:58:11.53#ibcon#about to read 4, iclass 11, count 0 2006.201.09:58:11.53#ibcon#read 4, iclass 11, count 0 2006.201.09:58:11.53#ibcon#about to read 5, iclass 11, count 0 2006.201.09:58:11.53#ibcon#read 5, iclass 11, count 0 2006.201.09:58:11.53#ibcon#about to read 6, iclass 11, count 0 2006.201.09:58:11.53#ibcon#read 6, iclass 11, count 0 2006.201.09:58:11.53#ibcon#end of sib2, iclass 11, count 0 2006.201.09:58:11.53#ibcon#*after write, iclass 11, count 0 2006.201.09:58:11.53#ibcon#*before return 0, iclass 11, count 0 2006.201.09:58:11.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:11.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:11.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:58:11.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:58:11.53$vck44/valo=3,564.99 2006.201.09:58:11.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.09:58:11.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.09:58:11.53#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:11.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:11.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:11.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:11.53#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:58:11.53#ibcon#first serial, iclass 13, count 0 2006.201.09:58:11.53#ibcon#enter sib2, iclass 13, count 0 2006.201.09:58:11.53#ibcon#flushed, iclass 13, count 0 2006.201.09:58:11.53#ibcon#about to write, iclass 13, count 0 2006.201.09:58:11.53#ibcon#wrote, iclass 13, count 0 2006.201.09:58:11.53#ibcon#about to read 3, iclass 13, count 0 2006.201.09:58:11.55#ibcon#read 3, iclass 13, count 0 2006.201.09:58:11.55#ibcon#about to read 4, iclass 13, count 0 2006.201.09:58:11.55#ibcon#read 4, iclass 13, count 0 2006.201.09:58:11.55#ibcon#about to read 5, iclass 13, count 0 2006.201.09:58:11.55#ibcon#read 5, iclass 13, count 0 2006.201.09:58:11.55#ibcon#about to read 6, iclass 13, count 0 2006.201.09:58:11.55#ibcon#read 6, iclass 13, count 0 2006.201.09:58:11.55#ibcon#end of sib2, iclass 13, count 0 2006.201.09:58:11.55#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:58:11.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:58:11.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.09:58:11.55#ibcon#*before write, iclass 13, count 0 2006.201.09:58:11.55#ibcon#enter sib2, iclass 13, count 0 2006.201.09:58:11.55#ibcon#flushed, iclass 13, count 0 2006.201.09:58:11.55#ibcon#about to write, iclass 13, count 0 2006.201.09:58:11.55#ibcon#wrote, iclass 13, count 0 2006.201.09:58:11.55#ibcon#about to read 3, iclass 13, count 0 2006.201.09:58:11.59#ibcon#read 3, iclass 13, count 0 2006.201.09:58:11.59#ibcon#about to read 4, iclass 13, count 0 2006.201.09:58:11.59#ibcon#read 4, iclass 13, count 0 2006.201.09:58:11.59#ibcon#about to read 5, iclass 13, count 0 2006.201.09:58:11.59#ibcon#read 5, iclass 13, count 0 2006.201.09:58:11.59#ibcon#about to read 6, iclass 13, count 0 2006.201.09:58:11.59#ibcon#read 6, iclass 13, count 0 2006.201.09:58:11.59#ibcon#end of sib2, iclass 13, count 0 2006.201.09:58:11.59#ibcon#*after write, iclass 13, count 0 2006.201.09:58:11.59#ibcon#*before return 0, iclass 13, count 0 2006.201.09:58:11.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:11.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:11.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:58:11.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:58:11.59$vck44/va=3,8 2006.201.09:58:11.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.09:58:11.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.09:58:11.59#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:11.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:11.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:11.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:11.65#ibcon#enter wrdev, iclass 15, count 2 2006.201.09:58:11.65#ibcon#first serial, iclass 15, count 2 2006.201.09:58:11.65#ibcon#enter sib2, iclass 15, count 2 2006.201.09:58:11.65#ibcon#flushed, iclass 15, count 2 2006.201.09:58:11.65#ibcon#about to write, iclass 15, count 2 2006.201.09:58:11.65#ibcon#wrote, iclass 15, count 2 2006.201.09:58:11.65#ibcon#about to read 3, iclass 15, count 2 2006.201.09:58:11.67#ibcon#read 3, iclass 15, count 2 2006.201.09:58:11.67#ibcon#about to read 4, iclass 15, count 2 2006.201.09:58:11.67#ibcon#read 4, iclass 15, count 2 2006.201.09:58:11.67#ibcon#about to read 5, iclass 15, count 2 2006.201.09:58:11.67#ibcon#read 5, iclass 15, count 2 2006.201.09:58:11.67#ibcon#about to read 6, iclass 15, count 2 2006.201.09:58:11.67#ibcon#read 6, iclass 15, count 2 2006.201.09:58:11.67#ibcon#end of sib2, iclass 15, count 2 2006.201.09:58:11.67#ibcon#*mode == 0, iclass 15, count 2 2006.201.09:58:11.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.09:58:11.67#ibcon#[25=AT03-08\r\n] 2006.201.09:58:11.67#ibcon#*before write, iclass 15, count 2 2006.201.09:58:11.67#ibcon#enter sib2, iclass 15, count 2 2006.201.09:58:11.67#ibcon#flushed, iclass 15, count 2 2006.201.09:58:11.67#ibcon#about to write, iclass 15, count 2 2006.201.09:58:11.67#ibcon#wrote, iclass 15, count 2 2006.201.09:58:11.67#ibcon#about to read 3, iclass 15, count 2 2006.201.09:58:11.70#ibcon#read 3, iclass 15, count 2 2006.201.09:58:11.70#ibcon#about to read 4, iclass 15, count 2 2006.201.09:58:11.70#ibcon#read 4, iclass 15, count 2 2006.201.09:58:11.70#ibcon#about to read 5, iclass 15, count 2 2006.201.09:58:11.70#ibcon#read 5, iclass 15, count 2 2006.201.09:58:11.70#ibcon#about to read 6, iclass 15, count 2 2006.201.09:58:11.70#ibcon#read 6, iclass 15, count 2 2006.201.09:58:11.70#ibcon#end of sib2, iclass 15, count 2 2006.201.09:58:11.70#ibcon#*after write, iclass 15, count 2 2006.201.09:58:11.70#ibcon#*before return 0, iclass 15, count 2 2006.201.09:58:11.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:11.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:11.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.09:58:11.70#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:11.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:11.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:11.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:11.82#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:58:11.82#ibcon#first serial, iclass 15, count 0 2006.201.09:58:11.82#ibcon#enter sib2, iclass 15, count 0 2006.201.09:58:11.82#ibcon#flushed, iclass 15, count 0 2006.201.09:58:11.82#ibcon#about to write, iclass 15, count 0 2006.201.09:58:11.82#ibcon#wrote, iclass 15, count 0 2006.201.09:58:11.82#ibcon#about to read 3, iclass 15, count 0 2006.201.09:58:11.84#ibcon#read 3, iclass 15, count 0 2006.201.09:58:11.84#ibcon#about to read 4, iclass 15, count 0 2006.201.09:58:11.84#ibcon#read 4, iclass 15, count 0 2006.201.09:58:11.84#ibcon#about to read 5, iclass 15, count 0 2006.201.09:58:11.84#ibcon#read 5, iclass 15, count 0 2006.201.09:58:11.84#ibcon#about to read 6, iclass 15, count 0 2006.201.09:58:11.84#ibcon#read 6, iclass 15, count 0 2006.201.09:58:11.84#ibcon#end of sib2, iclass 15, count 0 2006.201.09:58:11.84#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:58:11.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:58:11.84#ibcon#[25=USB\r\n] 2006.201.09:58:11.84#ibcon#*before write, iclass 15, count 0 2006.201.09:58:11.84#ibcon#enter sib2, iclass 15, count 0 2006.201.09:58:11.84#ibcon#flushed, iclass 15, count 0 2006.201.09:58:11.84#ibcon#about to write, iclass 15, count 0 2006.201.09:58:11.84#ibcon#wrote, iclass 15, count 0 2006.201.09:58:11.84#ibcon#about to read 3, iclass 15, count 0 2006.201.09:58:11.87#ibcon#read 3, iclass 15, count 0 2006.201.09:58:11.87#ibcon#about to read 4, iclass 15, count 0 2006.201.09:58:11.87#ibcon#read 4, iclass 15, count 0 2006.201.09:58:11.87#ibcon#about to read 5, iclass 15, count 0 2006.201.09:58:11.87#ibcon#read 5, iclass 15, count 0 2006.201.09:58:11.87#ibcon#about to read 6, iclass 15, count 0 2006.201.09:58:11.87#ibcon#read 6, iclass 15, count 0 2006.201.09:58:11.87#ibcon#end of sib2, iclass 15, count 0 2006.201.09:58:11.87#ibcon#*after write, iclass 15, count 0 2006.201.09:58:11.87#ibcon#*before return 0, iclass 15, count 0 2006.201.09:58:11.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:11.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:11.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:58:11.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:58:11.87$vck44/valo=4,624.99 2006.201.09:58:11.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.09:58:11.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.09:58:11.87#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:11.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:11.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:11.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:11.87#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:58:11.87#ibcon#first serial, iclass 17, count 0 2006.201.09:58:11.87#ibcon#enter sib2, iclass 17, count 0 2006.201.09:58:11.87#ibcon#flushed, iclass 17, count 0 2006.201.09:58:11.87#ibcon#about to write, iclass 17, count 0 2006.201.09:58:11.87#ibcon#wrote, iclass 17, count 0 2006.201.09:58:11.87#ibcon#about to read 3, iclass 17, count 0 2006.201.09:58:11.89#ibcon#read 3, iclass 17, count 0 2006.201.09:58:11.89#ibcon#about to read 4, iclass 17, count 0 2006.201.09:58:11.89#ibcon#read 4, iclass 17, count 0 2006.201.09:58:11.89#ibcon#about to read 5, iclass 17, count 0 2006.201.09:58:11.89#ibcon#read 5, iclass 17, count 0 2006.201.09:58:11.89#ibcon#about to read 6, iclass 17, count 0 2006.201.09:58:11.89#ibcon#read 6, iclass 17, count 0 2006.201.09:58:11.89#ibcon#end of sib2, iclass 17, count 0 2006.201.09:58:11.89#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:58:11.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:58:11.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.09:58:11.89#ibcon#*before write, iclass 17, count 0 2006.201.09:58:11.89#ibcon#enter sib2, iclass 17, count 0 2006.201.09:58:11.89#ibcon#flushed, iclass 17, count 0 2006.201.09:58:11.89#ibcon#about to write, iclass 17, count 0 2006.201.09:58:11.89#ibcon#wrote, iclass 17, count 0 2006.201.09:58:11.89#ibcon#about to read 3, iclass 17, count 0 2006.201.09:58:11.94#ibcon#read 3, iclass 17, count 0 2006.201.09:58:11.94#ibcon#about to read 4, iclass 17, count 0 2006.201.09:58:11.94#ibcon#read 4, iclass 17, count 0 2006.201.09:58:11.94#ibcon#about to read 5, iclass 17, count 0 2006.201.09:58:11.94#ibcon#read 5, iclass 17, count 0 2006.201.09:58:11.94#ibcon#about to read 6, iclass 17, count 0 2006.201.09:58:11.94#ibcon#read 6, iclass 17, count 0 2006.201.09:58:11.94#ibcon#end of sib2, iclass 17, count 0 2006.201.09:58:11.94#ibcon#*after write, iclass 17, count 0 2006.201.09:58:11.94#ibcon#*before return 0, iclass 17, count 0 2006.201.09:58:11.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:11.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:11.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:58:11.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:58:11.94$vck44/va=4,7 2006.201.09:58:11.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.09:58:11.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.09:58:11.94#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:11.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:11.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:11.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:11.99#ibcon#enter wrdev, iclass 19, count 2 2006.201.09:58:11.99#ibcon#first serial, iclass 19, count 2 2006.201.09:58:11.99#ibcon#enter sib2, iclass 19, count 2 2006.201.09:58:11.99#ibcon#flushed, iclass 19, count 2 2006.201.09:58:11.99#ibcon#about to write, iclass 19, count 2 2006.201.09:58:11.99#ibcon#wrote, iclass 19, count 2 2006.201.09:58:11.99#ibcon#about to read 3, iclass 19, count 2 2006.201.09:58:12.01#ibcon#read 3, iclass 19, count 2 2006.201.09:58:12.01#ibcon#about to read 4, iclass 19, count 2 2006.201.09:58:12.01#ibcon#read 4, iclass 19, count 2 2006.201.09:58:12.01#ibcon#about to read 5, iclass 19, count 2 2006.201.09:58:12.01#ibcon#read 5, iclass 19, count 2 2006.201.09:58:12.01#ibcon#about to read 6, iclass 19, count 2 2006.201.09:58:12.01#ibcon#read 6, iclass 19, count 2 2006.201.09:58:12.01#ibcon#end of sib2, iclass 19, count 2 2006.201.09:58:12.01#ibcon#*mode == 0, iclass 19, count 2 2006.201.09:58:12.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.09:58:12.01#ibcon#[25=AT04-07\r\n] 2006.201.09:58:12.01#ibcon#*before write, iclass 19, count 2 2006.201.09:58:12.01#ibcon#enter sib2, iclass 19, count 2 2006.201.09:58:12.01#ibcon#flushed, iclass 19, count 2 2006.201.09:58:12.01#ibcon#about to write, iclass 19, count 2 2006.201.09:58:12.01#ibcon#wrote, iclass 19, count 2 2006.201.09:58:12.01#ibcon#about to read 3, iclass 19, count 2 2006.201.09:58:12.04#ibcon#read 3, iclass 19, count 2 2006.201.09:58:12.04#ibcon#about to read 4, iclass 19, count 2 2006.201.09:58:12.04#ibcon#read 4, iclass 19, count 2 2006.201.09:58:12.04#ibcon#about to read 5, iclass 19, count 2 2006.201.09:58:12.04#ibcon#read 5, iclass 19, count 2 2006.201.09:58:12.04#ibcon#about to read 6, iclass 19, count 2 2006.201.09:58:12.04#ibcon#read 6, iclass 19, count 2 2006.201.09:58:12.04#ibcon#end of sib2, iclass 19, count 2 2006.201.09:58:12.04#ibcon#*after write, iclass 19, count 2 2006.201.09:58:12.04#ibcon#*before return 0, iclass 19, count 2 2006.201.09:58:12.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:12.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:12.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.09:58:12.04#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:12.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:12.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:12.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:12.16#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:58:12.16#ibcon#first serial, iclass 19, count 0 2006.201.09:58:12.16#ibcon#enter sib2, iclass 19, count 0 2006.201.09:58:12.16#ibcon#flushed, iclass 19, count 0 2006.201.09:58:12.16#ibcon#about to write, iclass 19, count 0 2006.201.09:58:12.16#ibcon#wrote, iclass 19, count 0 2006.201.09:58:12.16#ibcon#about to read 3, iclass 19, count 0 2006.201.09:58:12.18#ibcon#read 3, iclass 19, count 0 2006.201.09:58:12.18#ibcon#about to read 4, iclass 19, count 0 2006.201.09:58:12.18#ibcon#read 4, iclass 19, count 0 2006.201.09:58:12.18#ibcon#about to read 5, iclass 19, count 0 2006.201.09:58:12.18#ibcon#read 5, iclass 19, count 0 2006.201.09:58:12.18#ibcon#about to read 6, iclass 19, count 0 2006.201.09:58:12.18#ibcon#read 6, iclass 19, count 0 2006.201.09:58:12.18#ibcon#end of sib2, iclass 19, count 0 2006.201.09:58:12.18#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:58:12.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:58:12.18#ibcon#[25=USB\r\n] 2006.201.09:58:12.18#ibcon#*before write, iclass 19, count 0 2006.201.09:58:12.18#ibcon#enter sib2, iclass 19, count 0 2006.201.09:58:12.18#ibcon#flushed, iclass 19, count 0 2006.201.09:58:12.18#ibcon#about to write, iclass 19, count 0 2006.201.09:58:12.18#ibcon#wrote, iclass 19, count 0 2006.201.09:58:12.18#ibcon#about to read 3, iclass 19, count 0 2006.201.09:58:12.21#ibcon#read 3, iclass 19, count 0 2006.201.09:58:12.21#ibcon#about to read 4, iclass 19, count 0 2006.201.09:58:12.21#ibcon#read 4, iclass 19, count 0 2006.201.09:58:12.21#ibcon#about to read 5, iclass 19, count 0 2006.201.09:58:12.21#ibcon#read 5, iclass 19, count 0 2006.201.09:58:12.21#ibcon#about to read 6, iclass 19, count 0 2006.201.09:58:12.21#ibcon#read 6, iclass 19, count 0 2006.201.09:58:12.21#ibcon#end of sib2, iclass 19, count 0 2006.201.09:58:12.21#ibcon#*after write, iclass 19, count 0 2006.201.09:58:12.21#ibcon#*before return 0, iclass 19, count 0 2006.201.09:58:12.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:12.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:12.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:58:12.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:58:12.21$vck44/valo=5,734.99 2006.201.09:58:12.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.09:58:12.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.09:58:12.21#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:12.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:12.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:12.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:12.21#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:58:12.21#ibcon#first serial, iclass 21, count 0 2006.201.09:58:12.21#ibcon#enter sib2, iclass 21, count 0 2006.201.09:58:12.21#ibcon#flushed, iclass 21, count 0 2006.201.09:58:12.21#ibcon#about to write, iclass 21, count 0 2006.201.09:58:12.21#ibcon#wrote, iclass 21, count 0 2006.201.09:58:12.21#ibcon#about to read 3, iclass 21, count 0 2006.201.09:58:12.23#ibcon#read 3, iclass 21, count 0 2006.201.09:58:12.23#ibcon#about to read 4, iclass 21, count 0 2006.201.09:58:12.23#ibcon#read 4, iclass 21, count 0 2006.201.09:58:12.23#ibcon#about to read 5, iclass 21, count 0 2006.201.09:58:12.23#ibcon#read 5, iclass 21, count 0 2006.201.09:58:12.23#ibcon#about to read 6, iclass 21, count 0 2006.201.09:58:12.23#ibcon#read 6, iclass 21, count 0 2006.201.09:58:12.23#ibcon#end of sib2, iclass 21, count 0 2006.201.09:58:12.23#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:58:12.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:58:12.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.09:58:12.23#ibcon#*before write, iclass 21, count 0 2006.201.09:58:12.23#ibcon#enter sib2, iclass 21, count 0 2006.201.09:58:12.23#ibcon#flushed, iclass 21, count 0 2006.201.09:58:12.23#ibcon#about to write, iclass 21, count 0 2006.201.09:58:12.23#ibcon#wrote, iclass 21, count 0 2006.201.09:58:12.23#ibcon#about to read 3, iclass 21, count 0 2006.201.09:58:12.27#ibcon#read 3, iclass 21, count 0 2006.201.09:58:12.27#ibcon#about to read 4, iclass 21, count 0 2006.201.09:58:12.27#ibcon#read 4, iclass 21, count 0 2006.201.09:58:12.27#ibcon#about to read 5, iclass 21, count 0 2006.201.09:58:12.27#ibcon#read 5, iclass 21, count 0 2006.201.09:58:12.27#ibcon#about to read 6, iclass 21, count 0 2006.201.09:58:12.27#ibcon#read 6, iclass 21, count 0 2006.201.09:58:12.27#ibcon#end of sib2, iclass 21, count 0 2006.201.09:58:12.27#ibcon#*after write, iclass 21, count 0 2006.201.09:58:12.27#ibcon#*before return 0, iclass 21, count 0 2006.201.09:58:12.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:12.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:12.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:58:12.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:58:12.27$vck44/va=5,4 2006.201.09:58:12.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.09:58:12.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.09:58:12.27#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:12.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:12.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:12.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:12.33#ibcon#enter wrdev, iclass 23, count 2 2006.201.09:58:12.33#ibcon#first serial, iclass 23, count 2 2006.201.09:58:12.33#ibcon#enter sib2, iclass 23, count 2 2006.201.09:58:12.33#ibcon#flushed, iclass 23, count 2 2006.201.09:58:12.33#ibcon#about to write, iclass 23, count 2 2006.201.09:58:12.33#ibcon#wrote, iclass 23, count 2 2006.201.09:58:12.33#ibcon#about to read 3, iclass 23, count 2 2006.201.09:58:12.35#ibcon#read 3, iclass 23, count 2 2006.201.09:58:12.35#ibcon#about to read 4, iclass 23, count 2 2006.201.09:58:12.35#ibcon#read 4, iclass 23, count 2 2006.201.09:58:12.35#ibcon#about to read 5, iclass 23, count 2 2006.201.09:58:12.35#ibcon#read 5, iclass 23, count 2 2006.201.09:58:12.35#ibcon#about to read 6, iclass 23, count 2 2006.201.09:58:12.35#ibcon#read 6, iclass 23, count 2 2006.201.09:58:12.35#ibcon#end of sib2, iclass 23, count 2 2006.201.09:58:12.35#ibcon#*mode == 0, iclass 23, count 2 2006.201.09:58:12.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.09:58:12.35#ibcon#[25=AT05-04\r\n] 2006.201.09:58:12.35#ibcon#*before write, iclass 23, count 2 2006.201.09:58:12.35#ibcon#enter sib2, iclass 23, count 2 2006.201.09:58:12.35#ibcon#flushed, iclass 23, count 2 2006.201.09:58:12.35#ibcon#about to write, iclass 23, count 2 2006.201.09:58:12.35#ibcon#wrote, iclass 23, count 2 2006.201.09:58:12.35#ibcon#about to read 3, iclass 23, count 2 2006.201.09:58:12.38#ibcon#read 3, iclass 23, count 2 2006.201.09:58:12.38#ibcon#about to read 4, iclass 23, count 2 2006.201.09:58:12.38#ibcon#read 4, iclass 23, count 2 2006.201.09:58:12.38#ibcon#about to read 5, iclass 23, count 2 2006.201.09:58:12.38#ibcon#read 5, iclass 23, count 2 2006.201.09:58:12.38#ibcon#about to read 6, iclass 23, count 2 2006.201.09:58:12.38#ibcon#read 6, iclass 23, count 2 2006.201.09:58:12.38#ibcon#end of sib2, iclass 23, count 2 2006.201.09:58:12.38#ibcon#*after write, iclass 23, count 2 2006.201.09:58:12.38#ibcon#*before return 0, iclass 23, count 2 2006.201.09:58:12.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:12.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:12.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.09:58:12.38#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:12.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:12.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:12.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:12.50#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:58:12.50#ibcon#first serial, iclass 23, count 0 2006.201.09:58:12.50#ibcon#enter sib2, iclass 23, count 0 2006.201.09:58:12.50#ibcon#flushed, iclass 23, count 0 2006.201.09:58:12.50#ibcon#about to write, iclass 23, count 0 2006.201.09:58:12.50#ibcon#wrote, iclass 23, count 0 2006.201.09:58:12.50#ibcon#about to read 3, iclass 23, count 0 2006.201.09:58:12.52#ibcon#read 3, iclass 23, count 0 2006.201.09:58:12.52#ibcon#about to read 4, iclass 23, count 0 2006.201.09:58:12.52#ibcon#read 4, iclass 23, count 0 2006.201.09:58:12.52#ibcon#about to read 5, iclass 23, count 0 2006.201.09:58:12.52#ibcon#read 5, iclass 23, count 0 2006.201.09:58:12.52#ibcon#about to read 6, iclass 23, count 0 2006.201.09:58:12.52#ibcon#read 6, iclass 23, count 0 2006.201.09:58:12.52#ibcon#end of sib2, iclass 23, count 0 2006.201.09:58:12.52#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:58:12.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:58:12.52#ibcon#[25=USB\r\n] 2006.201.09:58:12.52#ibcon#*before write, iclass 23, count 0 2006.201.09:58:12.52#ibcon#enter sib2, iclass 23, count 0 2006.201.09:58:12.52#ibcon#flushed, iclass 23, count 0 2006.201.09:58:12.52#ibcon#about to write, iclass 23, count 0 2006.201.09:58:12.52#ibcon#wrote, iclass 23, count 0 2006.201.09:58:12.52#ibcon#about to read 3, iclass 23, count 0 2006.201.09:58:12.55#ibcon#read 3, iclass 23, count 0 2006.201.09:58:12.55#ibcon#about to read 4, iclass 23, count 0 2006.201.09:58:12.55#ibcon#read 4, iclass 23, count 0 2006.201.09:58:12.55#ibcon#about to read 5, iclass 23, count 0 2006.201.09:58:12.55#ibcon#read 5, iclass 23, count 0 2006.201.09:58:12.55#ibcon#about to read 6, iclass 23, count 0 2006.201.09:58:12.55#ibcon#read 6, iclass 23, count 0 2006.201.09:58:12.55#ibcon#end of sib2, iclass 23, count 0 2006.201.09:58:12.55#ibcon#*after write, iclass 23, count 0 2006.201.09:58:12.55#ibcon#*before return 0, iclass 23, count 0 2006.201.09:58:12.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:12.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:12.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:58:12.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:58:12.55$vck44/valo=6,814.99 2006.201.09:58:12.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.09:58:12.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.09:58:12.55#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:12.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:12.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:12.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:12.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:58:12.55#ibcon#first serial, iclass 25, count 0 2006.201.09:58:12.55#ibcon#enter sib2, iclass 25, count 0 2006.201.09:58:12.55#ibcon#flushed, iclass 25, count 0 2006.201.09:58:12.55#ibcon#about to write, iclass 25, count 0 2006.201.09:58:12.55#ibcon#wrote, iclass 25, count 0 2006.201.09:58:12.55#ibcon#about to read 3, iclass 25, count 0 2006.201.09:58:12.57#ibcon#read 3, iclass 25, count 0 2006.201.09:58:12.57#ibcon#about to read 4, iclass 25, count 0 2006.201.09:58:12.57#ibcon#read 4, iclass 25, count 0 2006.201.09:58:12.57#ibcon#about to read 5, iclass 25, count 0 2006.201.09:58:12.57#ibcon#read 5, iclass 25, count 0 2006.201.09:58:12.57#ibcon#about to read 6, iclass 25, count 0 2006.201.09:58:12.57#ibcon#read 6, iclass 25, count 0 2006.201.09:58:12.57#ibcon#end of sib2, iclass 25, count 0 2006.201.09:58:12.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:58:12.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:58:12.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.09:58:12.57#ibcon#*before write, iclass 25, count 0 2006.201.09:58:12.57#ibcon#enter sib2, iclass 25, count 0 2006.201.09:58:12.57#ibcon#flushed, iclass 25, count 0 2006.201.09:58:12.57#ibcon#about to write, iclass 25, count 0 2006.201.09:58:12.57#ibcon#wrote, iclass 25, count 0 2006.201.09:58:12.57#ibcon#about to read 3, iclass 25, count 0 2006.201.09:58:12.62#ibcon#read 3, iclass 25, count 0 2006.201.09:58:12.62#ibcon#about to read 4, iclass 25, count 0 2006.201.09:58:12.62#ibcon#read 4, iclass 25, count 0 2006.201.09:58:12.62#ibcon#about to read 5, iclass 25, count 0 2006.201.09:58:12.62#ibcon#read 5, iclass 25, count 0 2006.201.09:58:12.62#ibcon#about to read 6, iclass 25, count 0 2006.201.09:58:12.62#ibcon#read 6, iclass 25, count 0 2006.201.09:58:12.62#ibcon#end of sib2, iclass 25, count 0 2006.201.09:58:12.62#ibcon#*after write, iclass 25, count 0 2006.201.09:58:12.62#ibcon#*before return 0, iclass 25, count 0 2006.201.09:58:12.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:12.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:12.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:58:12.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:58:12.62$vck44/va=6,5 2006.201.09:58:12.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.09:58:12.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.09:58:12.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:12.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:12.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:12.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:12.67#ibcon#enter wrdev, iclass 27, count 2 2006.201.09:58:12.67#ibcon#first serial, iclass 27, count 2 2006.201.09:58:12.67#ibcon#enter sib2, iclass 27, count 2 2006.201.09:58:12.67#ibcon#flushed, iclass 27, count 2 2006.201.09:58:12.67#ibcon#about to write, iclass 27, count 2 2006.201.09:58:12.67#ibcon#wrote, iclass 27, count 2 2006.201.09:58:12.67#ibcon#about to read 3, iclass 27, count 2 2006.201.09:58:12.69#ibcon#read 3, iclass 27, count 2 2006.201.09:58:12.69#ibcon#about to read 4, iclass 27, count 2 2006.201.09:58:12.69#ibcon#read 4, iclass 27, count 2 2006.201.09:58:12.69#ibcon#about to read 5, iclass 27, count 2 2006.201.09:58:12.69#ibcon#read 5, iclass 27, count 2 2006.201.09:58:12.69#ibcon#about to read 6, iclass 27, count 2 2006.201.09:58:12.69#ibcon#read 6, iclass 27, count 2 2006.201.09:58:12.69#ibcon#end of sib2, iclass 27, count 2 2006.201.09:58:12.69#ibcon#*mode == 0, iclass 27, count 2 2006.201.09:58:12.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.09:58:12.69#ibcon#[25=AT06-05\r\n] 2006.201.09:58:12.69#ibcon#*before write, iclass 27, count 2 2006.201.09:58:12.69#ibcon#enter sib2, iclass 27, count 2 2006.201.09:58:12.69#ibcon#flushed, iclass 27, count 2 2006.201.09:58:12.69#ibcon#about to write, iclass 27, count 2 2006.201.09:58:12.69#ibcon#wrote, iclass 27, count 2 2006.201.09:58:12.69#ibcon#about to read 3, iclass 27, count 2 2006.201.09:58:12.72#ibcon#read 3, iclass 27, count 2 2006.201.09:58:12.72#ibcon#about to read 4, iclass 27, count 2 2006.201.09:58:12.72#ibcon#read 4, iclass 27, count 2 2006.201.09:58:12.72#ibcon#about to read 5, iclass 27, count 2 2006.201.09:58:12.72#ibcon#read 5, iclass 27, count 2 2006.201.09:58:12.72#ibcon#about to read 6, iclass 27, count 2 2006.201.09:58:12.72#ibcon#read 6, iclass 27, count 2 2006.201.09:58:12.72#ibcon#end of sib2, iclass 27, count 2 2006.201.09:58:12.72#ibcon#*after write, iclass 27, count 2 2006.201.09:58:12.72#ibcon#*before return 0, iclass 27, count 2 2006.201.09:58:12.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:12.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:12.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.09:58:12.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:12.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:12.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:12.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:12.84#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:58:12.84#ibcon#first serial, iclass 27, count 0 2006.201.09:58:12.84#ibcon#enter sib2, iclass 27, count 0 2006.201.09:58:12.84#ibcon#flushed, iclass 27, count 0 2006.201.09:58:12.84#ibcon#about to write, iclass 27, count 0 2006.201.09:58:12.84#ibcon#wrote, iclass 27, count 0 2006.201.09:58:12.84#ibcon#about to read 3, iclass 27, count 0 2006.201.09:58:12.86#ibcon#read 3, iclass 27, count 0 2006.201.09:58:12.86#ibcon#about to read 4, iclass 27, count 0 2006.201.09:58:12.86#ibcon#read 4, iclass 27, count 0 2006.201.09:58:12.86#ibcon#about to read 5, iclass 27, count 0 2006.201.09:58:12.86#ibcon#read 5, iclass 27, count 0 2006.201.09:58:12.86#ibcon#about to read 6, iclass 27, count 0 2006.201.09:58:12.86#ibcon#read 6, iclass 27, count 0 2006.201.09:58:12.86#ibcon#end of sib2, iclass 27, count 0 2006.201.09:58:12.86#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:58:12.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:58:12.86#ibcon#[25=USB\r\n] 2006.201.09:58:12.86#ibcon#*before write, iclass 27, count 0 2006.201.09:58:12.86#ibcon#enter sib2, iclass 27, count 0 2006.201.09:58:12.86#ibcon#flushed, iclass 27, count 0 2006.201.09:58:12.86#ibcon#about to write, iclass 27, count 0 2006.201.09:58:12.86#ibcon#wrote, iclass 27, count 0 2006.201.09:58:12.86#ibcon#about to read 3, iclass 27, count 0 2006.201.09:58:12.89#ibcon#read 3, iclass 27, count 0 2006.201.09:58:12.89#ibcon#about to read 4, iclass 27, count 0 2006.201.09:58:12.89#ibcon#read 4, iclass 27, count 0 2006.201.09:58:12.89#ibcon#about to read 5, iclass 27, count 0 2006.201.09:58:12.89#ibcon#read 5, iclass 27, count 0 2006.201.09:58:12.89#ibcon#about to read 6, iclass 27, count 0 2006.201.09:58:12.89#ibcon#read 6, iclass 27, count 0 2006.201.09:58:12.89#ibcon#end of sib2, iclass 27, count 0 2006.201.09:58:12.89#ibcon#*after write, iclass 27, count 0 2006.201.09:58:12.89#ibcon#*before return 0, iclass 27, count 0 2006.201.09:58:12.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:12.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:12.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:58:12.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:58:12.89$vck44/valo=7,864.99 2006.201.09:58:12.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.09:58:12.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.09:58:12.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:12.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:58:12.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:58:12.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:58:12.89#ibcon#enter wrdev, iclass 29, count 0 2006.201.09:58:12.89#ibcon#first serial, iclass 29, count 0 2006.201.09:58:12.89#ibcon#enter sib2, iclass 29, count 0 2006.201.09:58:12.89#ibcon#flushed, iclass 29, count 0 2006.201.09:58:12.89#ibcon#about to write, iclass 29, count 0 2006.201.09:58:12.89#ibcon#wrote, iclass 29, count 0 2006.201.09:58:12.89#ibcon#about to read 3, iclass 29, count 0 2006.201.09:58:12.91#ibcon#read 3, iclass 29, count 0 2006.201.09:58:12.91#ibcon#about to read 4, iclass 29, count 0 2006.201.09:58:12.91#ibcon#read 4, iclass 29, count 0 2006.201.09:58:12.91#ibcon#about to read 5, iclass 29, count 0 2006.201.09:58:12.91#ibcon#read 5, iclass 29, count 0 2006.201.09:58:12.91#ibcon#about to read 6, iclass 29, count 0 2006.201.09:58:12.91#ibcon#read 6, iclass 29, count 0 2006.201.09:58:12.91#ibcon#end of sib2, iclass 29, count 0 2006.201.09:58:12.91#ibcon#*mode == 0, iclass 29, count 0 2006.201.09:58:12.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.09:58:12.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.09:58:12.91#ibcon#*before write, iclass 29, count 0 2006.201.09:58:12.91#ibcon#enter sib2, iclass 29, count 0 2006.201.09:58:12.91#ibcon#flushed, iclass 29, count 0 2006.201.09:58:12.91#ibcon#about to write, iclass 29, count 0 2006.201.09:58:12.91#ibcon#wrote, iclass 29, count 0 2006.201.09:58:12.91#ibcon#about to read 3, iclass 29, count 0 2006.201.09:58:12.95#ibcon#read 3, iclass 29, count 0 2006.201.09:58:12.95#ibcon#about to read 4, iclass 29, count 0 2006.201.09:58:12.95#ibcon#read 4, iclass 29, count 0 2006.201.09:58:12.95#ibcon#about to read 5, iclass 29, count 0 2006.201.09:58:12.95#ibcon#read 5, iclass 29, count 0 2006.201.09:58:12.95#ibcon#about to read 6, iclass 29, count 0 2006.201.09:58:12.95#ibcon#read 6, iclass 29, count 0 2006.201.09:58:12.95#ibcon#end of sib2, iclass 29, count 0 2006.201.09:58:12.95#ibcon#*after write, iclass 29, count 0 2006.201.09:58:12.95#ibcon#*before return 0, iclass 29, count 0 2006.201.09:58:12.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:58:12.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.09:58:12.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.09:58:12.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.09:58:12.95$vck44/va=7,5 2006.201.09:58:12.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.09:58:12.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.09:58:12.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:12.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:58:13.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:58:13.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:58:13.01#ibcon#enter wrdev, iclass 31, count 2 2006.201.09:58:13.01#ibcon#first serial, iclass 31, count 2 2006.201.09:58:13.01#ibcon#enter sib2, iclass 31, count 2 2006.201.09:58:13.01#ibcon#flushed, iclass 31, count 2 2006.201.09:58:13.01#ibcon#about to write, iclass 31, count 2 2006.201.09:58:13.01#ibcon#wrote, iclass 31, count 2 2006.201.09:58:13.01#ibcon#about to read 3, iclass 31, count 2 2006.201.09:58:13.03#ibcon#read 3, iclass 31, count 2 2006.201.09:58:13.03#ibcon#about to read 4, iclass 31, count 2 2006.201.09:58:13.03#ibcon#read 4, iclass 31, count 2 2006.201.09:58:13.03#ibcon#about to read 5, iclass 31, count 2 2006.201.09:58:13.03#ibcon#read 5, iclass 31, count 2 2006.201.09:58:13.03#ibcon#about to read 6, iclass 31, count 2 2006.201.09:58:13.03#ibcon#read 6, iclass 31, count 2 2006.201.09:58:13.03#ibcon#end of sib2, iclass 31, count 2 2006.201.09:58:13.03#ibcon#*mode == 0, iclass 31, count 2 2006.201.09:58:13.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.09:58:13.03#ibcon#[25=AT07-05\r\n] 2006.201.09:58:13.03#ibcon#*before write, iclass 31, count 2 2006.201.09:58:13.03#ibcon#enter sib2, iclass 31, count 2 2006.201.09:58:13.03#ibcon#flushed, iclass 31, count 2 2006.201.09:58:13.03#ibcon#about to write, iclass 31, count 2 2006.201.09:58:13.03#ibcon#wrote, iclass 31, count 2 2006.201.09:58:13.03#ibcon#about to read 3, iclass 31, count 2 2006.201.09:58:13.06#ibcon#read 3, iclass 31, count 2 2006.201.09:58:13.06#ibcon#about to read 4, iclass 31, count 2 2006.201.09:58:13.06#ibcon#read 4, iclass 31, count 2 2006.201.09:58:13.06#ibcon#about to read 5, iclass 31, count 2 2006.201.09:58:13.06#ibcon#read 5, iclass 31, count 2 2006.201.09:58:13.06#ibcon#about to read 6, iclass 31, count 2 2006.201.09:58:13.06#ibcon#read 6, iclass 31, count 2 2006.201.09:58:13.06#ibcon#end of sib2, iclass 31, count 2 2006.201.09:58:13.06#ibcon#*after write, iclass 31, count 2 2006.201.09:58:13.06#ibcon#*before return 0, iclass 31, count 2 2006.201.09:58:13.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:58:13.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.09:58:13.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.09:58:13.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:13.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:58:13.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:58:13.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:58:13.18#ibcon#enter wrdev, iclass 31, count 0 2006.201.09:58:13.18#ibcon#first serial, iclass 31, count 0 2006.201.09:58:13.18#ibcon#enter sib2, iclass 31, count 0 2006.201.09:58:13.18#ibcon#flushed, iclass 31, count 0 2006.201.09:58:13.18#ibcon#about to write, iclass 31, count 0 2006.201.09:58:13.18#ibcon#wrote, iclass 31, count 0 2006.201.09:58:13.18#ibcon#about to read 3, iclass 31, count 0 2006.201.09:58:13.20#ibcon#read 3, iclass 31, count 0 2006.201.09:58:13.20#ibcon#about to read 4, iclass 31, count 0 2006.201.09:58:13.20#ibcon#read 4, iclass 31, count 0 2006.201.09:58:13.20#ibcon#about to read 5, iclass 31, count 0 2006.201.09:58:13.20#ibcon#read 5, iclass 31, count 0 2006.201.09:58:13.20#ibcon#about to read 6, iclass 31, count 0 2006.201.09:58:13.20#ibcon#read 6, iclass 31, count 0 2006.201.09:58:13.20#ibcon#end of sib2, iclass 31, count 0 2006.201.09:58:13.20#ibcon#*mode == 0, iclass 31, count 0 2006.201.09:58:13.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.09:58:13.20#ibcon#[25=USB\r\n] 2006.201.09:58:13.20#ibcon#*before write, iclass 31, count 0 2006.201.09:58:13.20#ibcon#enter sib2, iclass 31, count 0 2006.201.09:58:13.20#ibcon#flushed, iclass 31, count 0 2006.201.09:58:13.20#ibcon#about to write, iclass 31, count 0 2006.201.09:58:13.20#ibcon#wrote, iclass 31, count 0 2006.201.09:58:13.20#ibcon#about to read 3, iclass 31, count 0 2006.201.09:58:13.23#ibcon#read 3, iclass 31, count 0 2006.201.09:58:13.23#ibcon#about to read 4, iclass 31, count 0 2006.201.09:58:13.23#ibcon#read 4, iclass 31, count 0 2006.201.09:58:13.23#ibcon#about to read 5, iclass 31, count 0 2006.201.09:58:13.23#ibcon#read 5, iclass 31, count 0 2006.201.09:58:13.23#ibcon#about to read 6, iclass 31, count 0 2006.201.09:58:13.23#ibcon#read 6, iclass 31, count 0 2006.201.09:58:13.23#ibcon#end of sib2, iclass 31, count 0 2006.201.09:58:13.23#ibcon#*after write, iclass 31, count 0 2006.201.09:58:13.23#ibcon#*before return 0, iclass 31, count 0 2006.201.09:58:13.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:58:13.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.09:58:13.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.09:58:13.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.09:58:13.23$vck44/valo=8,884.99 2006.201.09:58:13.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.09:58:13.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.09:58:13.23#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:13.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:58:13.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:58:13.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:58:13.23#ibcon#enter wrdev, iclass 33, count 0 2006.201.09:58:13.23#ibcon#first serial, iclass 33, count 0 2006.201.09:58:13.23#ibcon#enter sib2, iclass 33, count 0 2006.201.09:58:13.23#ibcon#flushed, iclass 33, count 0 2006.201.09:58:13.23#ibcon#about to write, iclass 33, count 0 2006.201.09:58:13.23#ibcon#wrote, iclass 33, count 0 2006.201.09:58:13.23#ibcon#about to read 3, iclass 33, count 0 2006.201.09:58:13.25#ibcon#read 3, iclass 33, count 0 2006.201.09:58:13.25#ibcon#about to read 4, iclass 33, count 0 2006.201.09:58:13.25#ibcon#read 4, iclass 33, count 0 2006.201.09:58:13.25#ibcon#about to read 5, iclass 33, count 0 2006.201.09:58:13.25#ibcon#read 5, iclass 33, count 0 2006.201.09:58:13.25#ibcon#about to read 6, iclass 33, count 0 2006.201.09:58:13.25#ibcon#read 6, iclass 33, count 0 2006.201.09:58:13.25#ibcon#end of sib2, iclass 33, count 0 2006.201.09:58:13.25#ibcon#*mode == 0, iclass 33, count 0 2006.201.09:58:13.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.09:58:13.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.09:58:13.25#ibcon#*before write, iclass 33, count 0 2006.201.09:58:13.25#ibcon#enter sib2, iclass 33, count 0 2006.201.09:58:13.25#ibcon#flushed, iclass 33, count 0 2006.201.09:58:13.25#ibcon#about to write, iclass 33, count 0 2006.201.09:58:13.25#ibcon#wrote, iclass 33, count 0 2006.201.09:58:13.25#ibcon#about to read 3, iclass 33, count 0 2006.201.09:58:13.30#ibcon#read 3, iclass 33, count 0 2006.201.09:58:13.30#ibcon#about to read 4, iclass 33, count 0 2006.201.09:58:13.30#ibcon#read 4, iclass 33, count 0 2006.201.09:58:13.30#ibcon#about to read 5, iclass 33, count 0 2006.201.09:58:13.30#ibcon#read 5, iclass 33, count 0 2006.201.09:58:13.30#ibcon#about to read 6, iclass 33, count 0 2006.201.09:58:13.30#ibcon#read 6, iclass 33, count 0 2006.201.09:58:13.30#ibcon#end of sib2, iclass 33, count 0 2006.201.09:58:13.30#ibcon#*after write, iclass 33, count 0 2006.201.09:58:13.30#ibcon#*before return 0, iclass 33, count 0 2006.201.09:58:13.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:58:13.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.09:58:13.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.09:58:13.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.09:58:13.30$vck44/va=8,4 2006.201.09:58:13.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.09:58:13.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.09:58:13.30#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:13.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:58:13.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:58:13.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:58:13.35#ibcon#enter wrdev, iclass 35, count 2 2006.201.09:58:13.35#ibcon#first serial, iclass 35, count 2 2006.201.09:58:13.35#ibcon#enter sib2, iclass 35, count 2 2006.201.09:58:13.35#ibcon#flushed, iclass 35, count 2 2006.201.09:58:13.35#ibcon#about to write, iclass 35, count 2 2006.201.09:58:13.35#ibcon#wrote, iclass 35, count 2 2006.201.09:58:13.35#ibcon#about to read 3, iclass 35, count 2 2006.201.09:58:13.37#ibcon#read 3, iclass 35, count 2 2006.201.09:58:13.37#ibcon#about to read 4, iclass 35, count 2 2006.201.09:58:13.37#ibcon#read 4, iclass 35, count 2 2006.201.09:58:13.37#ibcon#about to read 5, iclass 35, count 2 2006.201.09:58:13.37#ibcon#read 5, iclass 35, count 2 2006.201.09:58:13.37#ibcon#about to read 6, iclass 35, count 2 2006.201.09:58:13.37#ibcon#read 6, iclass 35, count 2 2006.201.09:58:13.37#ibcon#end of sib2, iclass 35, count 2 2006.201.09:58:13.37#ibcon#*mode == 0, iclass 35, count 2 2006.201.09:58:13.37#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.09:58:13.37#ibcon#[25=AT08-04\r\n] 2006.201.09:58:13.37#ibcon#*before write, iclass 35, count 2 2006.201.09:58:13.37#ibcon#enter sib2, iclass 35, count 2 2006.201.09:58:13.37#ibcon#flushed, iclass 35, count 2 2006.201.09:58:13.37#ibcon#about to write, iclass 35, count 2 2006.201.09:58:13.37#ibcon#wrote, iclass 35, count 2 2006.201.09:58:13.37#ibcon#about to read 3, iclass 35, count 2 2006.201.09:58:13.40#ibcon#read 3, iclass 35, count 2 2006.201.09:58:13.40#ibcon#about to read 4, iclass 35, count 2 2006.201.09:58:13.40#ibcon#read 4, iclass 35, count 2 2006.201.09:58:13.40#ibcon#about to read 5, iclass 35, count 2 2006.201.09:58:13.40#ibcon#read 5, iclass 35, count 2 2006.201.09:58:13.40#ibcon#about to read 6, iclass 35, count 2 2006.201.09:58:13.40#ibcon#read 6, iclass 35, count 2 2006.201.09:58:13.40#ibcon#end of sib2, iclass 35, count 2 2006.201.09:58:13.40#ibcon#*after write, iclass 35, count 2 2006.201.09:58:13.40#ibcon#*before return 0, iclass 35, count 2 2006.201.09:58:13.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:58:13.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.09:58:13.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.09:58:13.40#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:13.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:58:13.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:58:13.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:58:13.52#ibcon#enter wrdev, iclass 35, count 0 2006.201.09:58:13.52#ibcon#first serial, iclass 35, count 0 2006.201.09:58:13.52#ibcon#enter sib2, iclass 35, count 0 2006.201.09:58:13.52#ibcon#flushed, iclass 35, count 0 2006.201.09:58:13.52#ibcon#about to write, iclass 35, count 0 2006.201.09:58:13.52#ibcon#wrote, iclass 35, count 0 2006.201.09:58:13.52#ibcon#about to read 3, iclass 35, count 0 2006.201.09:58:13.54#ibcon#read 3, iclass 35, count 0 2006.201.09:58:13.54#ibcon#about to read 4, iclass 35, count 0 2006.201.09:58:13.54#ibcon#read 4, iclass 35, count 0 2006.201.09:58:13.54#ibcon#about to read 5, iclass 35, count 0 2006.201.09:58:13.54#ibcon#read 5, iclass 35, count 0 2006.201.09:58:13.54#ibcon#about to read 6, iclass 35, count 0 2006.201.09:58:13.54#ibcon#read 6, iclass 35, count 0 2006.201.09:58:13.54#ibcon#end of sib2, iclass 35, count 0 2006.201.09:58:13.54#ibcon#*mode == 0, iclass 35, count 0 2006.201.09:58:13.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.09:58:13.54#ibcon#[25=USB\r\n] 2006.201.09:58:13.54#ibcon#*before write, iclass 35, count 0 2006.201.09:58:13.54#ibcon#enter sib2, iclass 35, count 0 2006.201.09:58:13.54#ibcon#flushed, iclass 35, count 0 2006.201.09:58:13.54#ibcon#about to write, iclass 35, count 0 2006.201.09:58:13.54#ibcon#wrote, iclass 35, count 0 2006.201.09:58:13.54#ibcon#about to read 3, iclass 35, count 0 2006.201.09:58:13.57#ibcon#read 3, iclass 35, count 0 2006.201.09:58:13.57#ibcon#about to read 4, iclass 35, count 0 2006.201.09:58:13.57#ibcon#read 4, iclass 35, count 0 2006.201.09:58:13.57#ibcon#about to read 5, iclass 35, count 0 2006.201.09:58:13.57#ibcon#read 5, iclass 35, count 0 2006.201.09:58:13.57#ibcon#about to read 6, iclass 35, count 0 2006.201.09:58:13.57#ibcon#read 6, iclass 35, count 0 2006.201.09:58:13.57#ibcon#end of sib2, iclass 35, count 0 2006.201.09:58:13.57#ibcon#*after write, iclass 35, count 0 2006.201.09:58:13.57#ibcon#*before return 0, iclass 35, count 0 2006.201.09:58:13.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:58:13.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.09:58:13.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.09:58:13.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.09:58:13.57$vck44/vblo=1,629.99 2006.201.09:58:13.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.09:58:13.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.09:58:13.57#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:13.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:13.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:13.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:13.57#ibcon#enter wrdev, iclass 37, count 0 2006.201.09:58:13.57#ibcon#first serial, iclass 37, count 0 2006.201.09:58:13.57#ibcon#enter sib2, iclass 37, count 0 2006.201.09:58:13.57#ibcon#flushed, iclass 37, count 0 2006.201.09:58:13.57#ibcon#about to write, iclass 37, count 0 2006.201.09:58:13.57#ibcon#wrote, iclass 37, count 0 2006.201.09:58:13.57#ibcon#about to read 3, iclass 37, count 0 2006.201.09:58:13.59#ibcon#read 3, iclass 37, count 0 2006.201.09:58:13.59#ibcon#about to read 4, iclass 37, count 0 2006.201.09:58:13.59#ibcon#read 4, iclass 37, count 0 2006.201.09:58:13.59#ibcon#about to read 5, iclass 37, count 0 2006.201.09:58:13.59#ibcon#read 5, iclass 37, count 0 2006.201.09:58:13.59#ibcon#about to read 6, iclass 37, count 0 2006.201.09:58:13.59#ibcon#read 6, iclass 37, count 0 2006.201.09:58:13.59#ibcon#end of sib2, iclass 37, count 0 2006.201.09:58:13.59#ibcon#*mode == 0, iclass 37, count 0 2006.201.09:58:13.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.09:58:13.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.09:58:13.59#ibcon#*before write, iclass 37, count 0 2006.201.09:58:13.59#ibcon#enter sib2, iclass 37, count 0 2006.201.09:58:13.59#ibcon#flushed, iclass 37, count 0 2006.201.09:58:13.59#ibcon#about to write, iclass 37, count 0 2006.201.09:58:13.59#ibcon#wrote, iclass 37, count 0 2006.201.09:58:13.59#ibcon#about to read 3, iclass 37, count 0 2006.201.09:58:13.63#ibcon#read 3, iclass 37, count 0 2006.201.09:58:13.63#ibcon#about to read 4, iclass 37, count 0 2006.201.09:58:13.63#ibcon#read 4, iclass 37, count 0 2006.201.09:58:13.63#ibcon#about to read 5, iclass 37, count 0 2006.201.09:58:13.63#ibcon#read 5, iclass 37, count 0 2006.201.09:58:13.63#ibcon#about to read 6, iclass 37, count 0 2006.201.09:58:13.63#ibcon#read 6, iclass 37, count 0 2006.201.09:58:13.63#ibcon#end of sib2, iclass 37, count 0 2006.201.09:58:13.63#ibcon#*after write, iclass 37, count 0 2006.201.09:58:13.63#ibcon#*before return 0, iclass 37, count 0 2006.201.09:58:13.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:13.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:13.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.09:58:13.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.09:58:13.63$vck44/vb=1,4 2006.201.09:58:13.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.09:58:13.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.09:58:13.63#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:13.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:58:13.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:58:13.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:58:13.63#ibcon#enter wrdev, iclass 39, count 2 2006.201.09:58:13.63#ibcon#first serial, iclass 39, count 2 2006.201.09:58:13.63#ibcon#enter sib2, iclass 39, count 2 2006.201.09:58:13.63#ibcon#flushed, iclass 39, count 2 2006.201.09:58:13.63#ibcon#about to write, iclass 39, count 2 2006.201.09:58:13.63#ibcon#wrote, iclass 39, count 2 2006.201.09:58:13.63#ibcon#about to read 3, iclass 39, count 2 2006.201.09:58:13.65#ibcon#read 3, iclass 39, count 2 2006.201.09:58:13.65#ibcon#about to read 4, iclass 39, count 2 2006.201.09:58:13.65#ibcon#read 4, iclass 39, count 2 2006.201.09:58:13.65#ibcon#about to read 5, iclass 39, count 2 2006.201.09:58:13.65#ibcon#read 5, iclass 39, count 2 2006.201.09:58:13.65#ibcon#about to read 6, iclass 39, count 2 2006.201.09:58:13.65#ibcon#read 6, iclass 39, count 2 2006.201.09:58:13.65#ibcon#end of sib2, iclass 39, count 2 2006.201.09:58:13.65#ibcon#*mode == 0, iclass 39, count 2 2006.201.09:58:13.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.09:58:13.65#ibcon#[27=AT01-04\r\n] 2006.201.09:58:13.65#ibcon#*before write, iclass 39, count 2 2006.201.09:58:13.65#ibcon#enter sib2, iclass 39, count 2 2006.201.09:58:13.65#ibcon#flushed, iclass 39, count 2 2006.201.09:58:13.65#ibcon#about to write, iclass 39, count 2 2006.201.09:58:13.65#ibcon#wrote, iclass 39, count 2 2006.201.09:58:13.65#ibcon#about to read 3, iclass 39, count 2 2006.201.09:58:13.68#ibcon#read 3, iclass 39, count 2 2006.201.09:58:13.68#ibcon#about to read 4, iclass 39, count 2 2006.201.09:58:13.68#ibcon#read 4, iclass 39, count 2 2006.201.09:58:13.68#ibcon#about to read 5, iclass 39, count 2 2006.201.09:58:13.68#ibcon#read 5, iclass 39, count 2 2006.201.09:58:13.68#ibcon#about to read 6, iclass 39, count 2 2006.201.09:58:13.68#ibcon#read 6, iclass 39, count 2 2006.201.09:58:13.68#ibcon#end of sib2, iclass 39, count 2 2006.201.09:58:13.68#ibcon#*after write, iclass 39, count 2 2006.201.09:58:13.68#ibcon#*before return 0, iclass 39, count 2 2006.201.09:58:13.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:58:13.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.09:58:13.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.09:58:13.68#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:13.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:58:13.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:58:13.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:58:13.80#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:58:13.80#ibcon#first serial, iclass 39, count 0 2006.201.09:58:13.80#ibcon#enter sib2, iclass 39, count 0 2006.201.09:58:13.80#ibcon#flushed, iclass 39, count 0 2006.201.09:58:13.80#ibcon#about to write, iclass 39, count 0 2006.201.09:58:13.80#ibcon#wrote, iclass 39, count 0 2006.201.09:58:13.80#ibcon#about to read 3, iclass 39, count 0 2006.201.09:58:13.82#ibcon#read 3, iclass 39, count 0 2006.201.09:58:13.82#ibcon#about to read 4, iclass 39, count 0 2006.201.09:58:13.82#ibcon#read 4, iclass 39, count 0 2006.201.09:58:13.82#ibcon#about to read 5, iclass 39, count 0 2006.201.09:58:13.82#ibcon#read 5, iclass 39, count 0 2006.201.09:58:13.82#ibcon#about to read 6, iclass 39, count 0 2006.201.09:58:13.82#ibcon#read 6, iclass 39, count 0 2006.201.09:58:13.82#ibcon#end of sib2, iclass 39, count 0 2006.201.09:58:13.82#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:58:13.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:58:13.82#ibcon#[27=USB\r\n] 2006.201.09:58:13.82#ibcon#*before write, iclass 39, count 0 2006.201.09:58:13.82#ibcon#enter sib2, iclass 39, count 0 2006.201.09:58:13.82#ibcon#flushed, iclass 39, count 0 2006.201.09:58:13.82#ibcon#about to write, iclass 39, count 0 2006.201.09:58:13.82#ibcon#wrote, iclass 39, count 0 2006.201.09:58:13.82#ibcon#about to read 3, iclass 39, count 0 2006.201.09:58:13.85#ibcon#read 3, iclass 39, count 0 2006.201.09:58:13.85#ibcon#about to read 4, iclass 39, count 0 2006.201.09:58:13.85#ibcon#read 4, iclass 39, count 0 2006.201.09:58:13.85#ibcon#about to read 5, iclass 39, count 0 2006.201.09:58:13.85#ibcon#read 5, iclass 39, count 0 2006.201.09:58:13.85#ibcon#about to read 6, iclass 39, count 0 2006.201.09:58:13.85#ibcon#read 6, iclass 39, count 0 2006.201.09:58:13.85#ibcon#end of sib2, iclass 39, count 0 2006.201.09:58:13.85#ibcon#*after write, iclass 39, count 0 2006.201.09:58:13.85#ibcon#*before return 0, iclass 39, count 0 2006.201.09:58:13.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:58:13.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.09:58:13.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:58:13.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:58:13.85$vck44/vblo=2,634.99 2006.201.09:58:13.85#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.09:58:13.85#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.09:58:13.85#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:13.85#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:13.85#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:13.85#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:13.85#ibcon#enter wrdev, iclass 2, count 0 2006.201.09:58:13.85#ibcon#first serial, iclass 2, count 0 2006.201.09:58:13.85#ibcon#enter sib2, iclass 2, count 0 2006.201.09:58:13.85#ibcon#flushed, iclass 2, count 0 2006.201.09:58:13.85#ibcon#about to write, iclass 2, count 0 2006.201.09:58:13.85#ibcon#wrote, iclass 2, count 0 2006.201.09:58:13.85#ibcon#about to read 3, iclass 2, count 0 2006.201.09:58:13.87#ibcon#read 3, iclass 2, count 0 2006.201.09:58:13.87#ibcon#about to read 4, iclass 2, count 0 2006.201.09:58:13.87#ibcon#read 4, iclass 2, count 0 2006.201.09:58:13.87#ibcon#about to read 5, iclass 2, count 0 2006.201.09:58:13.87#ibcon#read 5, iclass 2, count 0 2006.201.09:58:13.87#ibcon#about to read 6, iclass 2, count 0 2006.201.09:58:13.87#ibcon#read 6, iclass 2, count 0 2006.201.09:58:13.87#ibcon#end of sib2, iclass 2, count 0 2006.201.09:58:13.87#ibcon#*mode == 0, iclass 2, count 0 2006.201.09:58:13.87#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.09:58:13.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.09:58:13.87#ibcon#*before write, iclass 2, count 0 2006.201.09:58:13.87#ibcon#enter sib2, iclass 2, count 0 2006.201.09:58:13.87#ibcon#flushed, iclass 2, count 0 2006.201.09:58:13.87#ibcon#about to write, iclass 2, count 0 2006.201.09:58:13.87#ibcon#wrote, iclass 2, count 0 2006.201.09:58:13.87#ibcon#about to read 3, iclass 2, count 0 2006.201.09:58:13.91#ibcon#read 3, iclass 2, count 0 2006.201.09:58:13.91#ibcon#about to read 4, iclass 2, count 0 2006.201.09:58:13.91#ibcon#read 4, iclass 2, count 0 2006.201.09:58:13.91#ibcon#about to read 5, iclass 2, count 0 2006.201.09:58:13.91#ibcon#read 5, iclass 2, count 0 2006.201.09:58:13.91#ibcon#about to read 6, iclass 2, count 0 2006.201.09:58:13.91#ibcon#read 6, iclass 2, count 0 2006.201.09:58:13.91#ibcon#end of sib2, iclass 2, count 0 2006.201.09:58:13.91#ibcon#*after write, iclass 2, count 0 2006.201.09:58:13.91#ibcon#*before return 0, iclass 2, count 0 2006.201.09:58:13.91#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:13.91#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.09:58:13.91#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.09:58:13.91#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.09:58:13.91$vck44/vb=2,5 2006.201.09:58:13.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.09:58:13.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.09:58:13.91#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:13.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:13.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:13.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:13.97#ibcon#enter wrdev, iclass 5, count 2 2006.201.09:58:13.97#ibcon#first serial, iclass 5, count 2 2006.201.09:58:13.97#ibcon#enter sib2, iclass 5, count 2 2006.201.09:58:13.97#ibcon#flushed, iclass 5, count 2 2006.201.09:58:13.97#ibcon#about to write, iclass 5, count 2 2006.201.09:58:13.97#ibcon#wrote, iclass 5, count 2 2006.201.09:58:13.97#ibcon#about to read 3, iclass 5, count 2 2006.201.09:58:13.99#ibcon#read 3, iclass 5, count 2 2006.201.09:58:13.99#ibcon#about to read 4, iclass 5, count 2 2006.201.09:58:13.99#ibcon#read 4, iclass 5, count 2 2006.201.09:58:13.99#ibcon#about to read 5, iclass 5, count 2 2006.201.09:58:13.99#ibcon#read 5, iclass 5, count 2 2006.201.09:58:13.99#ibcon#about to read 6, iclass 5, count 2 2006.201.09:58:13.99#ibcon#read 6, iclass 5, count 2 2006.201.09:58:13.99#ibcon#end of sib2, iclass 5, count 2 2006.201.09:58:13.99#ibcon#*mode == 0, iclass 5, count 2 2006.201.09:58:13.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.09:58:13.99#ibcon#[27=AT02-05\r\n] 2006.201.09:58:13.99#ibcon#*before write, iclass 5, count 2 2006.201.09:58:13.99#ibcon#enter sib2, iclass 5, count 2 2006.201.09:58:13.99#ibcon#flushed, iclass 5, count 2 2006.201.09:58:13.99#ibcon#about to write, iclass 5, count 2 2006.201.09:58:13.99#ibcon#wrote, iclass 5, count 2 2006.201.09:58:13.99#ibcon#about to read 3, iclass 5, count 2 2006.201.09:58:14.02#ibcon#read 3, iclass 5, count 2 2006.201.09:58:14.02#ibcon#about to read 4, iclass 5, count 2 2006.201.09:58:14.02#ibcon#read 4, iclass 5, count 2 2006.201.09:58:14.02#ibcon#about to read 5, iclass 5, count 2 2006.201.09:58:14.02#ibcon#read 5, iclass 5, count 2 2006.201.09:58:14.02#ibcon#about to read 6, iclass 5, count 2 2006.201.09:58:14.02#ibcon#read 6, iclass 5, count 2 2006.201.09:58:14.02#ibcon#end of sib2, iclass 5, count 2 2006.201.09:58:14.02#ibcon#*after write, iclass 5, count 2 2006.201.09:58:14.02#ibcon#*before return 0, iclass 5, count 2 2006.201.09:58:14.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:14.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.09:58:14.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.09:58:14.02#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:14.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:14.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:14.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:14.14#ibcon#enter wrdev, iclass 5, count 0 2006.201.09:58:14.14#ibcon#first serial, iclass 5, count 0 2006.201.09:58:14.14#ibcon#enter sib2, iclass 5, count 0 2006.201.09:58:14.14#ibcon#flushed, iclass 5, count 0 2006.201.09:58:14.14#ibcon#about to write, iclass 5, count 0 2006.201.09:58:14.14#ibcon#wrote, iclass 5, count 0 2006.201.09:58:14.14#ibcon#about to read 3, iclass 5, count 0 2006.201.09:58:14.16#ibcon#read 3, iclass 5, count 0 2006.201.09:58:14.16#ibcon#about to read 4, iclass 5, count 0 2006.201.09:58:14.16#ibcon#read 4, iclass 5, count 0 2006.201.09:58:14.16#ibcon#about to read 5, iclass 5, count 0 2006.201.09:58:14.16#ibcon#read 5, iclass 5, count 0 2006.201.09:58:14.16#ibcon#about to read 6, iclass 5, count 0 2006.201.09:58:14.16#ibcon#read 6, iclass 5, count 0 2006.201.09:58:14.16#ibcon#end of sib2, iclass 5, count 0 2006.201.09:58:14.16#ibcon#*mode == 0, iclass 5, count 0 2006.201.09:58:14.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.09:58:14.16#ibcon#[27=USB\r\n] 2006.201.09:58:14.16#ibcon#*before write, iclass 5, count 0 2006.201.09:58:14.16#ibcon#enter sib2, iclass 5, count 0 2006.201.09:58:14.16#ibcon#flushed, iclass 5, count 0 2006.201.09:58:14.16#ibcon#about to write, iclass 5, count 0 2006.201.09:58:14.16#ibcon#wrote, iclass 5, count 0 2006.201.09:58:14.16#ibcon#about to read 3, iclass 5, count 0 2006.201.09:58:14.19#ibcon#read 3, iclass 5, count 0 2006.201.09:58:14.19#ibcon#about to read 4, iclass 5, count 0 2006.201.09:58:14.19#ibcon#read 4, iclass 5, count 0 2006.201.09:58:14.19#ibcon#about to read 5, iclass 5, count 0 2006.201.09:58:14.19#ibcon#read 5, iclass 5, count 0 2006.201.09:58:14.19#ibcon#about to read 6, iclass 5, count 0 2006.201.09:58:14.19#ibcon#read 6, iclass 5, count 0 2006.201.09:58:14.19#ibcon#end of sib2, iclass 5, count 0 2006.201.09:58:14.19#ibcon#*after write, iclass 5, count 0 2006.201.09:58:14.19#ibcon#*before return 0, iclass 5, count 0 2006.201.09:58:14.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:14.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.09:58:14.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.09:58:14.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.09:58:14.19$vck44/vblo=3,649.99 2006.201.09:58:14.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.09:58:14.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.09:58:14.19#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:14.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:14.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:14.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:14.19#ibcon#enter wrdev, iclass 7, count 0 2006.201.09:58:14.19#ibcon#first serial, iclass 7, count 0 2006.201.09:58:14.19#ibcon#enter sib2, iclass 7, count 0 2006.201.09:58:14.19#ibcon#flushed, iclass 7, count 0 2006.201.09:58:14.19#ibcon#about to write, iclass 7, count 0 2006.201.09:58:14.19#ibcon#wrote, iclass 7, count 0 2006.201.09:58:14.19#ibcon#about to read 3, iclass 7, count 0 2006.201.09:58:14.21#ibcon#read 3, iclass 7, count 0 2006.201.09:58:14.21#ibcon#about to read 4, iclass 7, count 0 2006.201.09:58:14.21#ibcon#read 4, iclass 7, count 0 2006.201.09:58:14.21#ibcon#about to read 5, iclass 7, count 0 2006.201.09:58:14.21#ibcon#read 5, iclass 7, count 0 2006.201.09:58:14.21#ibcon#about to read 6, iclass 7, count 0 2006.201.09:58:14.21#ibcon#read 6, iclass 7, count 0 2006.201.09:58:14.21#ibcon#end of sib2, iclass 7, count 0 2006.201.09:58:14.21#ibcon#*mode == 0, iclass 7, count 0 2006.201.09:58:14.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.09:58:14.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.09:58:14.21#ibcon#*before write, iclass 7, count 0 2006.201.09:58:14.21#ibcon#enter sib2, iclass 7, count 0 2006.201.09:58:14.21#ibcon#flushed, iclass 7, count 0 2006.201.09:58:14.21#ibcon#about to write, iclass 7, count 0 2006.201.09:58:14.21#ibcon#wrote, iclass 7, count 0 2006.201.09:58:14.21#ibcon#about to read 3, iclass 7, count 0 2006.201.09:58:14.26#ibcon#read 3, iclass 7, count 0 2006.201.09:58:14.26#ibcon#about to read 4, iclass 7, count 0 2006.201.09:58:14.26#ibcon#read 4, iclass 7, count 0 2006.201.09:58:14.26#ibcon#about to read 5, iclass 7, count 0 2006.201.09:58:14.26#ibcon#read 5, iclass 7, count 0 2006.201.09:58:14.26#ibcon#about to read 6, iclass 7, count 0 2006.201.09:58:14.26#ibcon#read 6, iclass 7, count 0 2006.201.09:58:14.26#ibcon#end of sib2, iclass 7, count 0 2006.201.09:58:14.26#ibcon#*after write, iclass 7, count 0 2006.201.09:58:14.26#ibcon#*before return 0, iclass 7, count 0 2006.201.09:58:14.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:14.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.09:58:14.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.09:58:14.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.09:58:14.26$vck44/vb=3,4 2006.201.09:58:14.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.09:58:14.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.09:58:14.26#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:14.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:14.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:14.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:14.31#ibcon#enter wrdev, iclass 11, count 2 2006.201.09:58:14.31#ibcon#first serial, iclass 11, count 2 2006.201.09:58:14.31#ibcon#enter sib2, iclass 11, count 2 2006.201.09:58:14.31#ibcon#flushed, iclass 11, count 2 2006.201.09:58:14.31#ibcon#about to write, iclass 11, count 2 2006.201.09:58:14.31#ibcon#wrote, iclass 11, count 2 2006.201.09:58:14.31#ibcon#about to read 3, iclass 11, count 2 2006.201.09:58:14.33#ibcon#read 3, iclass 11, count 2 2006.201.09:58:14.33#ibcon#about to read 4, iclass 11, count 2 2006.201.09:58:14.33#ibcon#read 4, iclass 11, count 2 2006.201.09:58:14.33#ibcon#about to read 5, iclass 11, count 2 2006.201.09:58:14.33#ibcon#read 5, iclass 11, count 2 2006.201.09:58:14.33#ibcon#about to read 6, iclass 11, count 2 2006.201.09:58:14.33#ibcon#read 6, iclass 11, count 2 2006.201.09:58:14.33#ibcon#end of sib2, iclass 11, count 2 2006.201.09:58:14.33#ibcon#*mode == 0, iclass 11, count 2 2006.201.09:58:14.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.09:58:14.33#ibcon#[27=AT03-04\r\n] 2006.201.09:58:14.33#ibcon#*before write, iclass 11, count 2 2006.201.09:58:14.33#ibcon#enter sib2, iclass 11, count 2 2006.201.09:58:14.33#ibcon#flushed, iclass 11, count 2 2006.201.09:58:14.33#ibcon#about to write, iclass 11, count 2 2006.201.09:58:14.33#ibcon#wrote, iclass 11, count 2 2006.201.09:58:14.33#ibcon#about to read 3, iclass 11, count 2 2006.201.09:58:14.36#ibcon#read 3, iclass 11, count 2 2006.201.09:58:14.36#ibcon#about to read 4, iclass 11, count 2 2006.201.09:58:14.36#ibcon#read 4, iclass 11, count 2 2006.201.09:58:14.36#ibcon#about to read 5, iclass 11, count 2 2006.201.09:58:14.36#ibcon#read 5, iclass 11, count 2 2006.201.09:58:14.36#ibcon#about to read 6, iclass 11, count 2 2006.201.09:58:14.36#ibcon#read 6, iclass 11, count 2 2006.201.09:58:14.36#ibcon#end of sib2, iclass 11, count 2 2006.201.09:58:14.36#ibcon#*after write, iclass 11, count 2 2006.201.09:58:14.36#ibcon#*before return 0, iclass 11, count 2 2006.201.09:58:14.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:14.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.09:58:14.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.09:58:14.36#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:14.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:14.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:14.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:14.48#ibcon#enter wrdev, iclass 11, count 0 2006.201.09:58:14.48#ibcon#first serial, iclass 11, count 0 2006.201.09:58:14.48#ibcon#enter sib2, iclass 11, count 0 2006.201.09:58:14.48#ibcon#flushed, iclass 11, count 0 2006.201.09:58:14.48#ibcon#about to write, iclass 11, count 0 2006.201.09:58:14.48#ibcon#wrote, iclass 11, count 0 2006.201.09:58:14.48#ibcon#about to read 3, iclass 11, count 0 2006.201.09:58:14.50#ibcon#read 3, iclass 11, count 0 2006.201.09:58:14.50#ibcon#about to read 4, iclass 11, count 0 2006.201.09:58:14.50#ibcon#read 4, iclass 11, count 0 2006.201.09:58:14.50#ibcon#about to read 5, iclass 11, count 0 2006.201.09:58:14.50#ibcon#read 5, iclass 11, count 0 2006.201.09:58:14.50#ibcon#about to read 6, iclass 11, count 0 2006.201.09:58:14.50#ibcon#read 6, iclass 11, count 0 2006.201.09:58:14.50#ibcon#end of sib2, iclass 11, count 0 2006.201.09:58:14.50#ibcon#*mode == 0, iclass 11, count 0 2006.201.09:58:14.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.09:58:14.50#ibcon#[27=USB\r\n] 2006.201.09:58:14.50#ibcon#*before write, iclass 11, count 0 2006.201.09:58:14.50#ibcon#enter sib2, iclass 11, count 0 2006.201.09:58:14.50#ibcon#flushed, iclass 11, count 0 2006.201.09:58:14.50#ibcon#about to write, iclass 11, count 0 2006.201.09:58:14.50#ibcon#wrote, iclass 11, count 0 2006.201.09:58:14.50#ibcon#about to read 3, iclass 11, count 0 2006.201.09:58:14.53#ibcon#read 3, iclass 11, count 0 2006.201.09:58:14.53#ibcon#about to read 4, iclass 11, count 0 2006.201.09:58:14.53#ibcon#read 4, iclass 11, count 0 2006.201.09:58:14.53#ibcon#about to read 5, iclass 11, count 0 2006.201.09:58:14.53#ibcon#read 5, iclass 11, count 0 2006.201.09:58:14.53#ibcon#about to read 6, iclass 11, count 0 2006.201.09:58:14.53#ibcon#read 6, iclass 11, count 0 2006.201.09:58:14.53#ibcon#end of sib2, iclass 11, count 0 2006.201.09:58:14.53#ibcon#*after write, iclass 11, count 0 2006.201.09:58:14.53#ibcon#*before return 0, iclass 11, count 0 2006.201.09:58:14.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:14.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.09:58:14.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.09:58:14.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.09:58:14.53$vck44/vblo=4,679.99 2006.201.09:58:14.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.09:58:14.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.09:58:14.53#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:14.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:14.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:14.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:14.53#ibcon#enter wrdev, iclass 13, count 0 2006.201.09:58:14.53#ibcon#first serial, iclass 13, count 0 2006.201.09:58:14.53#ibcon#enter sib2, iclass 13, count 0 2006.201.09:58:14.53#ibcon#flushed, iclass 13, count 0 2006.201.09:58:14.53#ibcon#about to write, iclass 13, count 0 2006.201.09:58:14.53#ibcon#wrote, iclass 13, count 0 2006.201.09:58:14.53#ibcon#about to read 3, iclass 13, count 0 2006.201.09:58:14.55#ibcon#read 3, iclass 13, count 0 2006.201.09:58:14.55#ibcon#about to read 4, iclass 13, count 0 2006.201.09:58:14.55#ibcon#read 4, iclass 13, count 0 2006.201.09:58:14.55#ibcon#about to read 5, iclass 13, count 0 2006.201.09:58:14.55#ibcon#read 5, iclass 13, count 0 2006.201.09:58:14.55#ibcon#about to read 6, iclass 13, count 0 2006.201.09:58:14.55#ibcon#read 6, iclass 13, count 0 2006.201.09:58:14.55#ibcon#end of sib2, iclass 13, count 0 2006.201.09:58:14.55#ibcon#*mode == 0, iclass 13, count 0 2006.201.09:58:14.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.09:58:14.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.09:58:14.55#ibcon#*before write, iclass 13, count 0 2006.201.09:58:14.55#ibcon#enter sib2, iclass 13, count 0 2006.201.09:58:14.55#ibcon#flushed, iclass 13, count 0 2006.201.09:58:14.55#ibcon#about to write, iclass 13, count 0 2006.201.09:58:14.55#ibcon#wrote, iclass 13, count 0 2006.201.09:58:14.55#ibcon#about to read 3, iclass 13, count 0 2006.201.09:58:14.59#ibcon#read 3, iclass 13, count 0 2006.201.09:58:14.59#ibcon#about to read 4, iclass 13, count 0 2006.201.09:58:14.59#ibcon#read 4, iclass 13, count 0 2006.201.09:58:14.59#ibcon#about to read 5, iclass 13, count 0 2006.201.09:58:14.59#ibcon#read 5, iclass 13, count 0 2006.201.09:58:14.59#ibcon#about to read 6, iclass 13, count 0 2006.201.09:58:14.59#ibcon#read 6, iclass 13, count 0 2006.201.09:58:14.59#ibcon#end of sib2, iclass 13, count 0 2006.201.09:58:14.59#ibcon#*after write, iclass 13, count 0 2006.201.09:58:14.59#ibcon#*before return 0, iclass 13, count 0 2006.201.09:58:14.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:14.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.09:58:14.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.09:58:14.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.09:58:14.59$vck44/vb=4,5 2006.201.09:58:14.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.09:58:14.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.09:58:14.59#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:14.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:14.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:14.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:14.65#ibcon#enter wrdev, iclass 15, count 2 2006.201.09:58:14.65#ibcon#first serial, iclass 15, count 2 2006.201.09:58:14.65#ibcon#enter sib2, iclass 15, count 2 2006.201.09:58:14.65#ibcon#flushed, iclass 15, count 2 2006.201.09:58:14.65#ibcon#about to write, iclass 15, count 2 2006.201.09:58:14.65#ibcon#wrote, iclass 15, count 2 2006.201.09:58:14.65#ibcon#about to read 3, iclass 15, count 2 2006.201.09:58:14.67#ibcon#read 3, iclass 15, count 2 2006.201.09:58:14.67#ibcon#about to read 4, iclass 15, count 2 2006.201.09:58:14.67#ibcon#read 4, iclass 15, count 2 2006.201.09:58:14.67#ibcon#about to read 5, iclass 15, count 2 2006.201.09:58:14.67#ibcon#read 5, iclass 15, count 2 2006.201.09:58:14.67#ibcon#about to read 6, iclass 15, count 2 2006.201.09:58:14.67#ibcon#read 6, iclass 15, count 2 2006.201.09:58:14.67#ibcon#end of sib2, iclass 15, count 2 2006.201.09:58:14.67#ibcon#*mode == 0, iclass 15, count 2 2006.201.09:58:14.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.09:58:14.67#ibcon#[27=AT04-05\r\n] 2006.201.09:58:14.67#ibcon#*before write, iclass 15, count 2 2006.201.09:58:14.67#ibcon#enter sib2, iclass 15, count 2 2006.201.09:58:14.67#ibcon#flushed, iclass 15, count 2 2006.201.09:58:14.67#ibcon#about to write, iclass 15, count 2 2006.201.09:58:14.67#ibcon#wrote, iclass 15, count 2 2006.201.09:58:14.67#ibcon#about to read 3, iclass 15, count 2 2006.201.09:58:14.70#ibcon#read 3, iclass 15, count 2 2006.201.09:58:14.70#ibcon#about to read 4, iclass 15, count 2 2006.201.09:58:14.70#ibcon#read 4, iclass 15, count 2 2006.201.09:58:14.70#ibcon#about to read 5, iclass 15, count 2 2006.201.09:58:14.70#ibcon#read 5, iclass 15, count 2 2006.201.09:58:14.70#ibcon#about to read 6, iclass 15, count 2 2006.201.09:58:14.70#ibcon#read 6, iclass 15, count 2 2006.201.09:58:14.70#ibcon#end of sib2, iclass 15, count 2 2006.201.09:58:14.70#ibcon#*after write, iclass 15, count 2 2006.201.09:58:14.70#ibcon#*before return 0, iclass 15, count 2 2006.201.09:58:14.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:14.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.09:58:14.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.09:58:14.70#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:14.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:14.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:14.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:14.82#ibcon#enter wrdev, iclass 15, count 0 2006.201.09:58:14.82#ibcon#first serial, iclass 15, count 0 2006.201.09:58:14.82#ibcon#enter sib2, iclass 15, count 0 2006.201.09:58:14.82#ibcon#flushed, iclass 15, count 0 2006.201.09:58:14.82#ibcon#about to write, iclass 15, count 0 2006.201.09:58:14.82#ibcon#wrote, iclass 15, count 0 2006.201.09:58:14.82#ibcon#about to read 3, iclass 15, count 0 2006.201.09:58:14.84#ibcon#read 3, iclass 15, count 0 2006.201.09:58:14.84#ibcon#about to read 4, iclass 15, count 0 2006.201.09:58:14.84#ibcon#read 4, iclass 15, count 0 2006.201.09:58:14.84#ibcon#about to read 5, iclass 15, count 0 2006.201.09:58:14.84#ibcon#read 5, iclass 15, count 0 2006.201.09:58:14.84#ibcon#about to read 6, iclass 15, count 0 2006.201.09:58:14.84#ibcon#read 6, iclass 15, count 0 2006.201.09:58:14.84#ibcon#end of sib2, iclass 15, count 0 2006.201.09:58:14.84#ibcon#*mode == 0, iclass 15, count 0 2006.201.09:58:14.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.09:58:14.84#ibcon#[27=USB\r\n] 2006.201.09:58:14.84#ibcon#*before write, iclass 15, count 0 2006.201.09:58:14.84#ibcon#enter sib2, iclass 15, count 0 2006.201.09:58:14.84#ibcon#flushed, iclass 15, count 0 2006.201.09:58:14.84#ibcon#about to write, iclass 15, count 0 2006.201.09:58:14.84#ibcon#wrote, iclass 15, count 0 2006.201.09:58:14.84#ibcon#about to read 3, iclass 15, count 0 2006.201.09:58:14.87#ibcon#read 3, iclass 15, count 0 2006.201.09:58:14.87#ibcon#about to read 4, iclass 15, count 0 2006.201.09:58:14.87#ibcon#read 4, iclass 15, count 0 2006.201.09:58:14.87#ibcon#about to read 5, iclass 15, count 0 2006.201.09:58:14.87#ibcon#read 5, iclass 15, count 0 2006.201.09:58:14.87#ibcon#about to read 6, iclass 15, count 0 2006.201.09:58:14.87#ibcon#read 6, iclass 15, count 0 2006.201.09:58:14.87#ibcon#end of sib2, iclass 15, count 0 2006.201.09:58:14.87#ibcon#*after write, iclass 15, count 0 2006.201.09:58:14.87#ibcon#*before return 0, iclass 15, count 0 2006.201.09:58:14.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:14.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.09:58:14.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.09:58:14.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.09:58:14.87$vck44/vblo=5,709.99 2006.201.09:58:14.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.09:58:14.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.09:58:14.87#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:14.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:14.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:14.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:14.87#ibcon#enter wrdev, iclass 17, count 0 2006.201.09:58:14.87#ibcon#first serial, iclass 17, count 0 2006.201.09:58:14.87#ibcon#enter sib2, iclass 17, count 0 2006.201.09:58:14.87#ibcon#flushed, iclass 17, count 0 2006.201.09:58:14.87#ibcon#about to write, iclass 17, count 0 2006.201.09:58:14.87#ibcon#wrote, iclass 17, count 0 2006.201.09:58:14.87#ibcon#about to read 3, iclass 17, count 0 2006.201.09:58:14.89#ibcon#read 3, iclass 17, count 0 2006.201.09:58:14.89#ibcon#about to read 4, iclass 17, count 0 2006.201.09:58:14.89#ibcon#read 4, iclass 17, count 0 2006.201.09:58:14.89#ibcon#about to read 5, iclass 17, count 0 2006.201.09:58:14.89#ibcon#read 5, iclass 17, count 0 2006.201.09:58:14.89#ibcon#about to read 6, iclass 17, count 0 2006.201.09:58:14.89#ibcon#read 6, iclass 17, count 0 2006.201.09:58:14.89#ibcon#end of sib2, iclass 17, count 0 2006.201.09:58:14.89#ibcon#*mode == 0, iclass 17, count 0 2006.201.09:58:14.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.09:58:14.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.09:58:14.89#ibcon#*before write, iclass 17, count 0 2006.201.09:58:14.89#ibcon#enter sib2, iclass 17, count 0 2006.201.09:58:14.89#ibcon#flushed, iclass 17, count 0 2006.201.09:58:14.89#ibcon#about to write, iclass 17, count 0 2006.201.09:58:14.89#ibcon#wrote, iclass 17, count 0 2006.201.09:58:14.89#ibcon#about to read 3, iclass 17, count 0 2006.201.09:58:14.94#ibcon#read 3, iclass 17, count 0 2006.201.09:58:14.94#ibcon#about to read 4, iclass 17, count 0 2006.201.09:58:14.94#ibcon#read 4, iclass 17, count 0 2006.201.09:58:14.94#ibcon#about to read 5, iclass 17, count 0 2006.201.09:58:14.94#ibcon#read 5, iclass 17, count 0 2006.201.09:58:14.94#ibcon#about to read 6, iclass 17, count 0 2006.201.09:58:14.94#ibcon#read 6, iclass 17, count 0 2006.201.09:58:14.94#ibcon#end of sib2, iclass 17, count 0 2006.201.09:58:14.94#ibcon#*after write, iclass 17, count 0 2006.201.09:58:14.94#ibcon#*before return 0, iclass 17, count 0 2006.201.09:58:14.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:14.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.09:58:14.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.09:58:14.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.09:58:14.94$vck44/vb=5,4 2006.201.09:58:14.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.09:58:14.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.09:58:14.94#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:14.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:14.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:14.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:14.99#ibcon#enter wrdev, iclass 19, count 2 2006.201.09:58:14.99#ibcon#first serial, iclass 19, count 2 2006.201.09:58:14.99#ibcon#enter sib2, iclass 19, count 2 2006.201.09:58:14.99#ibcon#flushed, iclass 19, count 2 2006.201.09:58:14.99#ibcon#about to write, iclass 19, count 2 2006.201.09:58:14.99#ibcon#wrote, iclass 19, count 2 2006.201.09:58:14.99#ibcon#about to read 3, iclass 19, count 2 2006.201.09:58:15.01#ibcon#read 3, iclass 19, count 2 2006.201.09:58:15.01#ibcon#about to read 4, iclass 19, count 2 2006.201.09:58:15.01#ibcon#read 4, iclass 19, count 2 2006.201.09:58:15.01#ibcon#about to read 5, iclass 19, count 2 2006.201.09:58:15.01#ibcon#read 5, iclass 19, count 2 2006.201.09:58:15.01#ibcon#about to read 6, iclass 19, count 2 2006.201.09:58:15.01#ibcon#read 6, iclass 19, count 2 2006.201.09:58:15.01#ibcon#end of sib2, iclass 19, count 2 2006.201.09:58:15.01#ibcon#*mode == 0, iclass 19, count 2 2006.201.09:58:15.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.09:58:15.01#ibcon#[27=AT05-04\r\n] 2006.201.09:58:15.01#ibcon#*before write, iclass 19, count 2 2006.201.09:58:15.01#ibcon#enter sib2, iclass 19, count 2 2006.201.09:58:15.01#ibcon#flushed, iclass 19, count 2 2006.201.09:58:15.01#ibcon#about to write, iclass 19, count 2 2006.201.09:58:15.01#ibcon#wrote, iclass 19, count 2 2006.201.09:58:15.01#ibcon#about to read 3, iclass 19, count 2 2006.201.09:58:15.04#ibcon#read 3, iclass 19, count 2 2006.201.09:58:15.04#ibcon#about to read 4, iclass 19, count 2 2006.201.09:58:15.04#ibcon#read 4, iclass 19, count 2 2006.201.09:58:15.04#ibcon#about to read 5, iclass 19, count 2 2006.201.09:58:15.04#ibcon#read 5, iclass 19, count 2 2006.201.09:58:15.04#ibcon#about to read 6, iclass 19, count 2 2006.201.09:58:15.04#ibcon#read 6, iclass 19, count 2 2006.201.09:58:15.04#ibcon#end of sib2, iclass 19, count 2 2006.201.09:58:15.04#ibcon#*after write, iclass 19, count 2 2006.201.09:58:15.04#ibcon#*before return 0, iclass 19, count 2 2006.201.09:58:15.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:15.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.09:58:15.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.09:58:15.04#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:15.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:15.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:15.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:15.16#ibcon#enter wrdev, iclass 19, count 0 2006.201.09:58:15.16#ibcon#first serial, iclass 19, count 0 2006.201.09:58:15.16#ibcon#enter sib2, iclass 19, count 0 2006.201.09:58:15.16#ibcon#flushed, iclass 19, count 0 2006.201.09:58:15.16#ibcon#about to write, iclass 19, count 0 2006.201.09:58:15.16#ibcon#wrote, iclass 19, count 0 2006.201.09:58:15.16#ibcon#about to read 3, iclass 19, count 0 2006.201.09:58:15.18#ibcon#read 3, iclass 19, count 0 2006.201.09:58:15.18#ibcon#about to read 4, iclass 19, count 0 2006.201.09:58:15.18#ibcon#read 4, iclass 19, count 0 2006.201.09:58:15.18#ibcon#about to read 5, iclass 19, count 0 2006.201.09:58:15.18#ibcon#read 5, iclass 19, count 0 2006.201.09:58:15.18#ibcon#about to read 6, iclass 19, count 0 2006.201.09:58:15.18#ibcon#read 6, iclass 19, count 0 2006.201.09:58:15.18#ibcon#end of sib2, iclass 19, count 0 2006.201.09:58:15.18#ibcon#*mode == 0, iclass 19, count 0 2006.201.09:58:15.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.09:58:15.18#ibcon#[27=USB\r\n] 2006.201.09:58:15.18#ibcon#*before write, iclass 19, count 0 2006.201.09:58:15.18#ibcon#enter sib2, iclass 19, count 0 2006.201.09:58:15.18#ibcon#flushed, iclass 19, count 0 2006.201.09:58:15.18#ibcon#about to write, iclass 19, count 0 2006.201.09:58:15.18#ibcon#wrote, iclass 19, count 0 2006.201.09:58:15.18#ibcon#about to read 3, iclass 19, count 0 2006.201.09:58:15.21#ibcon#read 3, iclass 19, count 0 2006.201.09:58:15.21#ibcon#about to read 4, iclass 19, count 0 2006.201.09:58:15.21#ibcon#read 4, iclass 19, count 0 2006.201.09:58:15.21#ibcon#about to read 5, iclass 19, count 0 2006.201.09:58:15.21#ibcon#read 5, iclass 19, count 0 2006.201.09:58:15.21#ibcon#about to read 6, iclass 19, count 0 2006.201.09:58:15.21#ibcon#read 6, iclass 19, count 0 2006.201.09:58:15.21#ibcon#end of sib2, iclass 19, count 0 2006.201.09:58:15.21#ibcon#*after write, iclass 19, count 0 2006.201.09:58:15.21#ibcon#*before return 0, iclass 19, count 0 2006.201.09:58:15.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:15.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.09:58:15.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.09:58:15.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.09:58:15.21$vck44/vblo=6,719.99 2006.201.09:58:15.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.09:58:15.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.09:58:15.21#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:15.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:15.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:15.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:15.21#ibcon#enter wrdev, iclass 21, count 0 2006.201.09:58:15.21#ibcon#first serial, iclass 21, count 0 2006.201.09:58:15.21#ibcon#enter sib2, iclass 21, count 0 2006.201.09:58:15.21#ibcon#flushed, iclass 21, count 0 2006.201.09:58:15.21#ibcon#about to write, iclass 21, count 0 2006.201.09:58:15.21#ibcon#wrote, iclass 21, count 0 2006.201.09:58:15.21#ibcon#about to read 3, iclass 21, count 0 2006.201.09:58:15.23#ibcon#read 3, iclass 21, count 0 2006.201.09:58:15.23#ibcon#about to read 4, iclass 21, count 0 2006.201.09:58:15.23#ibcon#read 4, iclass 21, count 0 2006.201.09:58:15.23#ibcon#about to read 5, iclass 21, count 0 2006.201.09:58:15.23#ibcon#read 5, iclass 21, count 0 2006.201.09:58:15.23#ibcon#about to read 6, iclass 21, count 0 2006.201.09:58:15.23#ibcon#read 6, iclass 21, count 0 2006.201.09:58:15.23#ibcon#end of sib2, iclass 21, count 0 2006.201.09:58:15.23#ibcon#*mode == 0, iclass 21, count 0 2006.201.09:58:15.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.09:58:15.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.09:58:15.23#ibcon#*before write, iclass 21, count 0 2006.201.09:58:15.23#ibcon#enter sib2, iclass 21, count 0 2006.201.09:58:15.23#ibcon#flushed, iclass 21, count 0 2006.201.09:58:15.23#ibcon#about to write, iclass 21, count 0 2006.201.09:58:15.23#ibcon#wrote, iclass 21, count 0 2006.201.09:58:15.23#ibcon#about to read 3, iclass 21, count 0 2006.201.09:58:15.27#ibcon#read 3, iclass 21, count 0 2006.201.09:58:15.27#ibcon#about to read 4, iclass 21, count 0 2006.201.09:58:15.27#ibcon#read 4, iclass 21, count 0 2006.201.09:58:15.27#ibcon#about to read 5, iclass 21, count 0 2006.201.09:58:15.27#ibcon#read 5, iclass 21, count 0 2006.201.09:58:15.27#ibcon#about to read 6, iclass 21, count 0 2006.201.09:58:15.27#ibcon#read 6, iclass 21, count 0 2006.201.09:58:15.27#ibcon#end of sib2, iclass 21, count 0 2006.201.09:58:15.27#ibcon#*after write, iclass 21, count 0 2006.201.09:58:15.27#ibcon#*before return 0, iclass 21, count 0 2006.201.09:58:15.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:15.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.09:58:15.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.09:58:15.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.09:58:15.27$vck44/vb=6,4 2006.201.09:58:15.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.09:58:15.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.09:58:15.27#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:15.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:15.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:15.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:15.33#ibcon#enter wrdev, iclass 23, count 2 2006.201.09:58:15.33#ibcon#first serial, iclass 23, count 2 2006.201.09:58:15.33#ibcon#enter sib2, iclass 23, count 2 2006.201.09:58:15.33#ibcon#flushed, iclass 23, count 2 2006.201.09:58:15.33#ibcon#about to write, iclass 23, count 2 2006.201.09:58:15.33#ibcon#wrote, iclass 23, count 2 2006.201.09:58:15.33#ibcon#about to read 3, iclass 23, count 2 2006.201.09:58:15.35#ibcon#read 3, iclass 23, count 2 2006.201.09:58:15.35#ibcon#about to read 4, iclass 23, count 2 2006.201.09:58:15.35#ibcon#read 4, iclass 23, count 2 2006.201.09:58:15.35#ibcon#about to read 5, iclass 23, count 2 2006.201.09:58:15.35#ibcon#read 5, iclass 23, count 2 2006.201.09:58:15.35#ibcon#about to read 6, iclass 23, count 2 2006.201.09:58:15.35#ibcon#read 6, iclass 23, count 2 2006.201.09:58:15.35#ibcon#end of sib2, iclass 23, count 2 2006.201.09:58:15.35#ibcon#*mode == 0, iclass 23, count 2 2006.201.09:58:15.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.09:58:15.35#ibcon#[27=AT06-04\r\n] 2006.201.09:58:15.35#ibcon#*before write, iclass 23, count 2 2006.201.09:58:15.35#ibcon#enter sib2, iclass 23, count 2 2006.201.09:58:15.35#ibcon#flushed, iclass 23, count 2 2006.201.09:58:15.35#ibcon#about to write, iclass 23, count 2 2006.201.09:58:15.35#ibcon#wrote, iclass 23, count 2 2006.201.09:58:15.35#ibcon#about to read 3, iclass 23, count 2 2006.201.09:58:15.38#ibcon#read 3, iclass 23, count 2 2006.201.09:58:15.38#ibcon#about to read 4, iclass 23, count 2 2006.201.09:58:15.38#ibcon#read 4, iclass 23, count 2 2006.201.09:58:15.38#ibcon#about to read 5, iclass 23, count 2 2006.201.09:58:15.38#ibcon#read 5, iclass 23, count 2 2006.201.09:58:15.38#ibcon#about to read 6, iclass 23, count 2 2006.201.09:58:15.38#ibcon#read 6, iclass 23, count 2 2006.201.09:58:15.38#ibcon#end of sib2, iclass 23, count 2 2006.201.09:58:15.38#ibcon#*after write, iclass 23, count 2 2006.201.09:58:15.38#ibcon#*before return 0, iclass 23, count 2 2006.201.09:58:15.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:15.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.09:58:15.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.09:58:15.38#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:15.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:15.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:15.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:15.50#ibcon#enter wrdev, iclass 23, count 0 2006.201.09:58:15.50#ibcon#first serial, iclass 23, count 0 2006.201.09:58:15.50#ibcon#enter sib2, iclass 23, count 0 2006.201.09:58:15.50#ibcon#flushed, iclass 23, count 0 2006.201.09:58:15.50#ibcon#about to write, iclass 23, count 0 2006.201.09:58:15.50#ibcon#wrote, iclass 23, count 0 2006.201.09:58:15.50#ibcon#about to read 3, iclass 23, count 0 2006.201.09:58:15.52#ibcon#read 3, iclass 23, count 0 2006.201.09:58:15.52#ibcon#about to read 4, iclass 23, count 0 2006.201.09:58:15.52#ibcon#read 4, iclass 23, count 0 2006.201.09:58:15.52#ibcon#about to read 5, iclass 23, count 0 2006.201.09:58:15.52#ibcon#read 5, iclass 23, count 0 2006.201.09:58:15.52#ibcon#about to read 6, iclass 23, count 0 2006.201.09:58:15.52#ibcon#read 6, iclass 23, count 0 2006.201.09:58:15.52#ibcon#end of sib2, iclass 23, count 0 2006.201.09:58:15.52#ibcon#*mode == 0, iclass 23, count 0 2006.201.09:58:15.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.09:58:15.52#ibcon#[27=USB\r\n] 2006.201.09:58:15.52#ibcon#*before write, iclass 23, count 0 2006.201.09:58:15.52#ibcon#enter sib2, iclass 23, count 0 2006.201.09:58:15.52#ibcon#flushed, iclass 23, count 0 2006.201.09:58:15.52#ibcon#about to write, iclass 23, count 0 2006.201.09:58:15.52#ibcon#wrote, iclass 23, count 0 2006.201.09:58:15.52#ibcon#about to read 3, iclass 23, count 0 2006.201.09:58:15.55#ibcon#read 3, iclass 23, count 0 2006.201.09:58:15.55#ibcon#about to read 4, iclass 23, count 0 2006.201.09:58:15.55#ibcon#read 4, iclass 23, count 0 2006.201.09:58:15.55#ibcon#about to read 5, iclass 23, count 0 2006.201.09:58:15.55#ibcon#read 5, iclass 23, count 0 2006.201.09:58:15.55#ibcon#about to read 6, iclass 23, count 0 2006.201.09:58:15.55#ibcon#read 6, iclass 23, count 0 2006.201.09:58:15.55#ibcon#end of sib2, iclass 23, count 0 2006.201.09:58:15.55#ibcon#*after write, iclass 23, count 0 2006.201.09:58:15.55#ibcon#*before return 0, iclass 23, count 0 2006.201.09:58:15.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:15.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.09:58:15.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.09:58:15.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.09:58:15.55$vck44/vblo=7,734.99 2006.201.09:58:15.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.09:58:15.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.09:58:15.55#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:15.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:15.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:15.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:15.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.09:58:15.55#ibcon#first serial, iclass 25, count 0 2006.201.09:58:15.55#ibcon#enter sib2, iclass 25, count 0 2006.201.09:58:15.55#ibcon#flushed, iclass 25, count 0 2006.201.09:58:15.55#ibcon#about to write, iclass 25, count 0 2006.201.09:58:15.55#ibcon#wrote, iclass 25, count 0 2006.201.09:58:15.55#ibcon#about to read 3, iclass 25, count 0 2006.201.09:58:15.57#ibcon#read 3, iclass 25, count 0 2006.201.09:58:15.57#ibcon#about to read 4, iclass 25, count 0 2006.201.09:58:15.57#ibcon#read 4, iclass 25, count 0 2006.201.09:58:15.57#ibcon#about to read 5, iclass 25, count 0 2006.201.09:58:15.57#ibcon#read 5, iclass 25, count 0 2006.201.09:58:15.57#ibcon#about to read 6, iclass 25, count 0 2006.201.09:58:15.57#ibcon#read 6, iclass 25, count 0 2006.201.09:58:15.57#ibcon#end of sib2, iclass 25, count 0 2006.201.09:58:15.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.09:58:15.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.09:58:15.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.09:58:15.57#ibcon#*before write, iclass 25, count 0 2006.201.09:58:15.57#ibcon#enter sib2, iclass 25, count 0 2006.201.09:58:15.57#ibcon#flushed, iclass 25, count 0 2006.201.09:58:15.57#ibcon#about to write, iclass 25, count 0 2006.201.09:58:15.57#ibcon#wrote, iclass 25, count 0 2006.201.09:58:15.57#ibcon#about to read 3, iclass 25, count 0 2006.201.09:58:15.62#ibcon#read 3, iclass 25, count 0 2006.201.09:58:15.62#ibcon#about to read 4, iclass 25, count 0 2006.201.09:58:15.62#ibcon#read 4, iclass 25, count 0 2006.201.09:58:15.62#ibcon#about to read 5, iclass 25, count 0 2006.201.09:58:15.62#ibcon#read 5, iclass 25, count 0 2006.201.09:58:15.62#ibcon#about to read 6, iclass 25, count 0 2006.201.09:58:15.62#ibcon#read 6, iclass 25, count 0 2006.201.09:58:15.62#ibcon#end of sib2, iclass 25, count 0 2006.201.09:58:15.62#ibcon#*after write, iclass 25, count 0 2006.201.09:58:15.62#ibcon#*before return 0, iclass 25, count 0 2006.201.09:58:15.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:15.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.09:58:15.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.09:58:15.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.09:58:15.62$vck44/vb=7,4 2006.201.09:58:15.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.09:58:15.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.09:58:15.62#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:15.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:15.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:15.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:15.67#ibcon#enter wrdev, iclass 27, count 2 2006.201.09:58:15.67#ibcon#first serial, iclass 27, count 2 2006.201.09:58:15.67#ibcon#enter sib2, iclass 27, count 2 2006.201.09:58:15.67#ibcon#flushed, iclass 27, count 2 2006.201.09:58:15.67#ibcon#about to write, iclass 27, count 2 2006.201.09:58:15.67#ibcon#wrote, iclass 27, count 2 2006.201.09:58:15.67#ibcon#about to read 3, iclass 27, count 2 2006.201.09:58:15.69#ibcon#read 3, iclass 27, count 2 2006.201.09:58:15.69#ibcon#about to read 4, iclass 27, count 2 2006.201.09:58:15.69#ibcon#read 4, iclass 27, count 2 2006.201.09:58:15.69#ibcon#about to read 5, iclass 27, count 2 2006.201.09:58:15.69#ibcon#read 5, iclass 27, count 2 2006.201.09:58:15.69#ibcon#about to read 6, iclass 27, count 2 2006.201.09:58:15.69#ibcon#read 6, iclass 27, count 2 2006.201.09:58:15.69#ibcon#end of sib2, iclass 27, count 2 2006.201.09:58:15.69#ibcon#*mode == 0, iclass 27, count 2 2006.201.09:58:15.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.09:58:15.69#ibcon#[27=AT07-04\r\n] 2006.201.09:58:15.69#ibcon#*before write, iclass 27, count 2 2006.201.09:58:15.69#ibcon#enter sib2, iclass 27, count 2 2006.201.09:58:15.69#ibcon#flushed, iclass 27, count 2 2006.201.09:58:15.69#ibcon#about to write, iclass 27, count 2 2006.201.09:58:15.69#ibcon#wrote, iclass 27, count 2 2006.201.09:58:15.69#ibcon#about to read 3, iclass 27, count 2 2006.201.09:58:15.72#ibcon#read 3, iclass 27, count 2 2006.201.09:58:15.72#ibcon#about to read 4, iclass 27, count 2 2006.201.09:58:15.72#ibcon#read 4, iclass 27, count 2 2006.201.09:58:15.72#ibcon#about to read 5, iclass 27, count 2 2006.201.09:58:15.72#ibcon#read 5, iclass 27, count 2 2006.201.09:58:15.72#ibcon#about to read 6, iclass 27, count 2 2006.201.09:58:15.72#ibcon#read 6, iclass 27, count 2 2006.201.09:58:15.72#ibcon#end of sib2, iclass 27, count 2 2006.201.09:58:15.72#ibcon#*after write, iclass 27, count 2 2006.201.09:58:15.72#ibcon#*before return 0, iclass 27, count 2 2006.201.09:58:15.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:15.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.09:58:15.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.09:58:15.72#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:15.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:15.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:15.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:15.84#ibcon#enter wrdev, iclass 27, count 0 2006.201.09:58:15.84#ibcon#first serial, iclass 27, count 0 2006.201.09:58:15.84#ibcon#enter sib2, iclass 27, count 0 2006.201.09:58:15.84#ibcon#flushed, iclass 27, count 0 2006.201.09:58:15.84#ibcon#about to write, iclass 27, count 0 2006.201.09:58:15.84#ibcon#wrote, iclass 27, count 0 2006.201.09:58:15.84#ibcon#about to read 3, iclass 27, count 0 2006.201.09:58:15.86#ibcon#read 3, iclass 27, count 0 2006.201.09:58:15.86#ibcon#about to read 4, iclass 27, count 0 2006.201.09:58:15.86#ibcon#read 4, iclass 27, count 0 2006.201.09:58:15.86#ibcon#about to read 5, iclass 27, count 0 2006.201.09:58:15.86#ibcon#read 5, iclass 27, count 0 2006.201.09:58:15.86#ibcon#about to read 6, iclass 27, count 0 2006.201.09:58:15.86#ibcon#read 6, iclass 27, count 0 2006.201.09:58:15.86#ibcon#end of sib2, iclass 27, count 0 2006.201.09:58:15.86#ibcon#*mode == 0, iclass 27, count 0 2006.201.09:58:15.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.09:58:15.86#ibcon#[27=USB\r\n] 2006.201.09:58:15.86#ibcon#*before write, iclass 27, count 0 2006.201.09:58:15.86#ibcon#enter sib2, iclass 27, count 0 2006.201.09:58:15.86#ibcon#flushed, iclass 27, count 0 2006.201.09:58:15.86#ibcon#about to write, iclass 27, count 0 2006.201.09:58:15.86#ibcon#wrote, iclass 27, count 0 2006.201.09:58:15.86#ibcon#about to read 3, iclass 27, count 0 2006.201.09:58:15.89#ibcon#read 3, iclass 27, count 0 2006.201.09:58:15.89#ibcon#about to read 4, iclass 27, count 0 2006.201.09:58:15.89#ibcon#read 4, iclass 27, count 0 2006.201.09:58:15.89#ibcon#about to read 5, iclass 27, count 0 2006.201.09:58:15.89#ibcon#read 5, iclass 27, count 0 2006.201.09:58:15.89#ibcon#about to read 6, iclass 27, count 0 2006.201.09:58:15.89#ibcon#read 6, iclass 27, count 0 2006.201.09:58:15.89#ibcon#end of sib2, iclass 27, count 0 2006.201.09:58:15.89#ibcon#*after write, iclass 27, count 0 2006.201.09:58:15.89#ibcon#*before return 0, iclass 27, count 0 2006.201.09:58:15.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:15.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.09:58:15.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.09:58:15.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.09:58:15.89$vck44/vblo=8,744.99 2006.201.09:58:15.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.09:58:15.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.09:58:15.89#ibcon#ireg 17 cls_cnt 0 2006.201.09:58:15.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:58:15.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:58:15.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:58:15.89#ibcon#enter wrdev, iclass 30, count 0 2006.201.09:58:15.89#ibcon#first serial, iclass 30, count 0 2006.201.09:58:15.89#ibcon#enter sib2, iclass 30, count 0 2006.201.09:58:15.89#ibcon#flushed, iclass 30, count 0 2006.201.09:58:15.89#ibcon#about to write, iclass 30, count 0 2006.201.09:58:15.89#ibcon#wrote, iclass 30, count 0 2006.201.09:58:15.89#ibcon#about to read 3, iclass 30, count 0 2006.201.09:58:15.91#ibcon#read 3, iclass 30, count 0 2006.201.09:58:15.91#ibcon#about to read 4, iclass 30, count 0 2006.201.09:58:15.91#ibcon#read 4, iclass 30, count 0 2006.201.09:58:15.91#ibcon#about to read 5, iclass 30, count 0 2006.201.09:58:15.91#ibcon#read 5, iclass 30, count 0 2006.201.09:58:15.91#ibcon#about to read 6, iclass 30, count 0 2006.201.09:58:15.91#ibcon#read 6, iclass 30, count 0 2006.201.09:58:15.91#ibcon#end of sib2, iclass 30, count 0 2006.201.09:58:15.91#ibcon#*mode == 0, iclass 30, count 0 2006.201.09:58:15.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.09:58:15.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.09:58:15.91#ibcon#*before write, iclass 30, count 0 2006.201.09:58:15.91#ibcon#enter sib2, iclass 30, count 0 2006.201.09:58:15.91#ibcon#flushed, iclass 30, count 0 2006.201.09:58:15.91#ibcon#about to write, iclass 30, count 0 2006.201.09:58:15.91#ibcon#wrote, iclass 30, count 0 2006.201.09:58:15.91#ibcon#about to read 3, iclass 30, count 0 2006.201.09:58:15.91#abcon#<5=/05 2.7 5.1 22.23 941003.6\r\n> 2006.201.09:58:15.93#abcon#{5=INTERFACE CLEAR} 2006.201.09:58:15.95#ibcon#read 3, iclass 30, count 0 2006.201.09:58:15.95#ibcon#about to read 4, iclass 30, count 0 2006.201.09:58:15.95#ibcon#read 4, iclass 30, count 0 2006.201.09:58:15.95#ibcon#about to read 5, iclass 30, count 0 2006.201.09:58:15.95#ibcon#read 5, iclass 30, count 0 2006.201.09:58:15.95#ibcon#about to read 6, iclass 30, count 0 2006.201.09:58:15.95#ibcon#read 6, iclass 30, count 0 2006.201.09:58:15.95#ibcon#end of sib2, iclass 30, count 0 2006.201.09:58:15.95#ibcon#*after write, iclass 30, count 0 2006.201.09:58:15.95#ibcon#*before return 0, iclass 30, count 0 2006.201.09:58:15.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:58:15.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.09:58:15.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.09:58:15.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.09:58:15.95$vck44/vb=8,4 2006.201.09:58:15.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.09:58:15.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.09:58:15.95#ibcon#ireg 11 cls_cnt 2 2006.201.09:58:15.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:58:15.99#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:58:16.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:58:16.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:58:16.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.09:58:16.01#ibcon#first serial, iclass 34, count 2 2006.201.09:58:16.01#ibcon#enter sib2, iclass 34, count 2 2006.201.09:58:16.01#ibcon#flushed, iclass 34, count 2 2006.201.09:58:16.01#ibcon#about to write, iclass 34, count 2 2006.201.09:58:16.01#ibcon#wrote, iclass 34, count 2 2006.201.09:58:16.01#ibcon#about to read 3, iclass 34, count 2 2006.201.09:58:16.03#ibcon#read 3, iclass 34, count 2 2006.201.09:58:16.03#ibcon#about to read 4, iclass 34, count 2 2006.201.09:58:16.03#ibcon#read 4, iclass 34, count 2 2006.201.09:58:16.03#ibcon#about to read 5, iclass 34, count 2 2006.201.09:58:16.03#ibcon#read 5, iclass 34, count 2 2006.201.09:58:16.03#ibcon#about to read 6, iclass 34, count 2 2006.201.09:58:16.03#ibcon#read 6, iclass 34, count 2 2006.201.09:58:16.03#ibcon#end of sib2, iclass 34, count 2 2006.201.09:58:16.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.09:58:16.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.09:58:16.03#ibcon#[27=AT08-04\r\n] 2006.201.09:58:16.03#ibcon#*before write, iclass 34, count 2 2006.201.09:58:16.03#ibcon#enter sib2, iclass 34, count 2 2006.201.09:58:16.03#ibcon#flushed, iclass 34, count 2 2006.201.09:58:16.03#ibcon#about to write, iclass 34, count 2 2006.201.09:58:16.03#ibcon#wrote, iclass 34, count 2 2006.201.09:58:16.03#ibcon#about to read 3, iclass 34, count 2 2006.201.09:58:16.06#ibcon#read 3, iclass 34, count 2 2006.201.09:58:16.06#ibcon#about to read 4, iclass 34, count 2 2006.201.09:58:16.06#ibcon#read 4, iclass 34, count 2 2006.201.09:58:16.06#ibcon#about to read 5, iclass 34, count 2 2006.201.09:58:16.06#ibcon#read 5, iclass 34, count 2 2006.201.09:58:16.06#ibcon#about to read 6, iclass 34, count 2 2006.201.09:58:16.06#ibcon#read 6, iclass 34, count 2 2006.201.09:58:16.06#ibcon#end of sib2, iclass 34, count 2 2006.201.09:58:16.06#ibcon#*after write, iclass 34, count 2 2006.201.09:58:16.06#ibcon#*before return 0, iclass 34, count 2 2006.201.09:58:16.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:58:16.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.09:58:16.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.09:58:16.06#ibcon#ireg 7 cls_cnt 0 2006.201.09:58:16.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:58:16.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:58:16.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:58:16.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.09:58:16.18#ibcon#first serial, iclass 34, count 0 2006.201.09:58:16.18#ibcon#enter sib2, iclass 34, count 0 2006.201.09:58:16.18#ibcon#flushed, iclass 34, count 0 2006.201.09:58:16.18#ibcon#about to write, iclass 34, count 0 2006.201.09:58:16.18#ibcon#wrote, iclass 34, count 0 2006.201.09:58:16.18#ibcon#about to read 3, iclass 34, count 0 2006.201.09:58:16.20#ibcon#read 3, iclass 34, count 0 2006.201.09:58:16.20#ibcon#about to read 4, iclass 34, count 0 2006.201.09:58:16.20#ibcon#read 4, iclass 34, count 0 2006.201.09:58:16.20#ibcon#about to read 5, iclass 34, count 0 2006.201.09:58:16.20#ibcon#read 5, iclass 34, count 0 2006.201.09:58:16.20#ibcon#about to read 6, iclass 34, count 0 2006.201.09:58:16.20#ibcon#read 6, iclass 34, count 0 2006.201.09:58:16.20#ibcon#end of sib2, iclass 34, count 0 2006.201.09:58:16.20#ibcon#*mode == 0, iclass 34, count 0 2006.201.09:58:16.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.09:58:16.20#ibcon#[27=USB\r\n] 2006.201.09:58:16.20#ibcon#*before write, iclass 34, count 0 2006.201.09:58:16.20#ibcon#enter sib2, iclass 34, count 0 2006.201.09:58:16.20#ibcon#flushed, iclass 34, count 0 2006.201.09:58:16.20#ibcon#about to write, iclass 34, count 0 2006.201.09:58:16.20#ibcon#wrote, iclass 34, count 0 2006.201.09:58:16.20#ibcon#about to read 3, iclass 34, count 0 2006.201.09:58:16.23#ibcon#read 3, iclass 34, count 0 2006.201.09:58:16.23#ibcon#about to read 4, iclass 34, count 0 2006.201.09:58:16.23#ibcon#read 4, iclass 34, count 0 2006.201.09:58:16.23#ibcon#about to read 5, iclass 34, count 0 2006.201.09:58:16.23#ibcon#read 5, iclass 34, count 0 2006.201.09:58:16.23#ibcon#about to read 6, iclass 34, count 0 2006.201.09:58:16.23#ibcon#read 6, iclass 34, count 0 2006.201.09:58:16.23#ibcon#end of sib2, iclass 34, count 0 2006.201.09:58:16.23#ibcon#*after write, iclass 34, count 0 2006.201.09:58:16.23#ibcon#*before return 0, iclass 34, count 0 2006.201.09:58:16.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:58:16.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.09:58:16.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.09:58:16.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.09:58:16.23$vck44/vabw=wide 2006.201.09:58:16.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.09:58:16.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.09:58:16.23#ibcon#ireg 8 cls_cnt 0 2006.201.09:58:16.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:16.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:16.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:16.23#ibcon#enter wrdev, iclass 37, count 0 2006.201.09:58:16.23#ibcon#first serial, iclass 37, count 0 2006.201.09:58:16.23#ibcon#enter sib2, iclass 37, count 0 2006.201.09:58:16.23#ibcon#flushed, iclass 37, count 0 2006.201.09:58:16.23#ibcon#about to write, iclass 37, count 0 2006.201.09:58:16.23#ibcon#wrote, iclass 37, count 0 2006.201.09:58:16.23#ibcon#about to read 3, iclass 37, count 0 2006.201.09:58:16.25#ibcon#read 3, iclass 37, count 0 2006.201.09:58:16.25#ibcon#about to read 4, iclass 37, count 0 2006.201.09:58:16.25#ibcon#read 4, iclass 37, count 0 2006.201.09:58:16.25#ibcon#about to read 5, iclass 37, count 0 2006.201.09:58:16.25#ibcon#read 5, iclass 37, count 0 2006.201.09:58:16.25#ibcon#about to read 6, iclass 37, count 0 2006.201.09:58:16.25#ibcon#read 6, iclass 37, count 0 2006.201.09:58:16.25#ibcon#end of sib2, iclass 37, count 0 2006.201.09:58:16.25#ibcon#*mode == 0, iclass 37, count 0 2006.201.09:58:16.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.09:58:16.25#ibcon#[25=BW32\r\n] 2006.201.09:58:16.25#ibcon#*before write, iclass 37, count 0 2006.201.09:58:16.25#ibcon#enter sib2, iclass 37, count 0 2006.201.09:58:16.25#ibcon#flushed, iclass 37, count 0 2006.201.09:58:16.25#ibcon#about to write, iclass 37, count 0 2006.201.09:58:16.25#ibcon#wrote, iclass 37, count 0 2006.201.09:58:16.25#ibcon#about to read 3, iclass 37, count 0 2006.201.09:58:16.28#ibcon#read 3, iclass 37, count 0 2006.201.09:58:16.28#ibcon#about to read 4, iclass 37, count 0 2006.201.09:58:16.28#ibcon#read 4, iclass 37, count 0 2006.201.09:58:16.28#ibcon#about to read 5, iclass 37, count 0 2006.201.09:58:16.28#ibcon#read 5, iclass 37, count 0 2006.201.09:58:16.28#ibcon#about to read 6, iclass 37, count 0 2006.201.09:58:16.28#ibcon#read 6, iclass 37, count 0 2006.201.09:58:16.28#ibcon#end of sib2, iclass 37, count 0 2006.201.09:58:16.28#ibcon#*after write, iclass 37, count 0 2006.201.09:58:16.28#ibcon#*before return 0, iclass 37, count 0 2006.201.09:58:16.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:16.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.09:58:16.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.09:58:16.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.09:58:16.28$vck44/vbbw=wide 2006.201.09:58:16.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.09:58:16.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.09:58:16.28#ibcon#ireg 8 cls_cnt 0 2006.201.09:58:16.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:58:16.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:58:16.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:58:16.35#ibcon#enter wrdev, iclass 39, count 0 2006.201.09:58:16.35#ibcon#first serial, iclass 39, count 0 2006.201.09:58:16.35#ibcon#enter sib2, iclass 39, count 0 2006.201.09:58:16.35#ibcon#flushed, iclass 39, count 0 2006.201.09:58:16.35#ibcon#about to write, iclass 39, count 0 2006.201.09:58:16.35#ibcon#wrote, iclass 39, count 0 2006.201.09:58:16.35#ibcon#about to read 3, iclass 39, count 0 2006.201.09:58:16.37#ibcon#read 3, iclass 39, count 0 2006.201.09:58:16.37#ibcon#about to read 4, iclass 39, count 0 2006.201.09:58:16.37#ibcon#read 4, iclass 39, count 0 2006.201.09:58:16.37#ibcon#about to read 5, iclass 39, count 0 2006.201.09:58:16.37#ibcon#read 5, iclass 39, count 0 2006.201.09:58:16.37#ibcon#about to read 6, iclass 39, count 0 2006.201.09:58:16.37#ibcon#read 6, iclass 39, count 0 2006.201.09:58:16.37#ibcon#end of sib2, iclass 39, count 0 2006.201.09:58:16.37#ibcon#*mode == 0, iclass 39, count 0 2006.201.09:58:16.37#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.09:58:16.37#ibcon#[27=BW32\r\n] 2006.201.09:58:16.37#ibcon#*before write, iclass 39, count 0 2006.201.09:58:16.37#ibcon#enter sib2, iclass 39, count 0 2006.201.09:58:16.37#ibcon#flushed, iclass 39, count 0 2006.201.09:58:16.37#ibcon#about to write, iclass 39, count 0 2006.201.09:58:16.37#ibcon#wrote, iclass 39, count 0 2006.201.09:58:16.37#ibcon#about to read 3, iclass 39, count 0 2006.201.09:58:16.40#ibcon#read 3, iclass 39, count 0 2006.201.09:58:16.40#ibcon#about to read 4, iclass 39, count 0 2006.201.09:58:16.40#ibcon#read 4, iclass 39, count 0 2006.201.09:58:16.40#ibcon#about to read 5, iclass 39, count 0 2006.201.09:58:16.40#ibcon#read 5, iclass 39, count 0 2006.201.09:58:16.40#ibcon#about to read 6, iclass 39, count 0 2006.201.09:58:16.40#ibcon#read 6, iclass 39, count 0 2006.201.09:58:16.40#ibcon#end of sib2, iclass 39, count 0 2006.201.09:58:16.40#ibcon#*after write, iclass 39, count 0 2006.201.09:58:16.40#ibcon#*before return 0, iclass 39, count 0 2006.201.09:58:16.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:58:16.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.09:58:16.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.09:58:16.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.09:58:16.40$setupk4/ifdk4 2006.201.09:58:16.40$ifdk4/lo= 2006.201.09:58:16.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.09:58:16.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.09:58:16.40$ifdk4/patch= 2006.201.09:58:16.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.09:58:16.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.09:58:16.40$setupk4/!*+20s 2006.201.09:58:26.08#abcon#<5=/05 2.7 5.1 22.22 941003.6\r\n> 2006.201.09:58:26.10#abcon#{5=INTERFACE CLEAR} 2006.201.09:58:26.16#abcon#[5=S1D000X0/0*\r\n] 2006.201.09:58:30.89$setupk4/"tpicd 2006.201.09:58:30.89$setupk4/echo=off 2006.201.09:58:30.89$setupk4/xlog=off 2006.201.09:58:30.89:!2006.201.09:59:30 2006.201.09:58:39.13#trakl#Source acquired 2006.201.09:58:39.13#flagr#flagr/antenna,acquired 2006.201.09:59:30.00:preob 2006.201.09:59:31.13/onsource/TRACKING 2006.201.09:59:31.13:!2006.201.09:59:40 2006.201.09:59:40.00:"tape 2006.201.09:59:40.00:"st=record 2006.201.09:59:40.00:data_valid=on 2006.201.09:59:40.00:midob 2006.201.09:59:40.13/onsource/TRACKING 2006.201.09:59:40.13/wx/22.21,1003.6,94 2006.201.09:59:40.24/cable/+6.4661E-03 2006.201.09:59:41.33/va/01,08,usb,yes,28,30 2006.201.09:59:41.33/va/02,07,usb,yes,31,31 2006.201.09:59:41.33/va/03,08,usb,yes,27,29 2006.201.09:59:41.33/va/04,07,usb,yes,31,33 2006.201.09:59:41.33/va/05,04,usb,yes,28,28 2006.201.09:59:41.33/va/06,05,usb,yes,28,28 2006.201.09:59:41.33/va/07,05,usb,yes,27,28 2006.201.09:59:41.33/va/08,04,usb,yes,27,32 2006.201.09:59:41.56/valo/01,524.99,yes,locked 2006.201.09:59:41.56/valo/02,534.99,yes,locked 2006.201.09:59:41.56/valo/03,564.99,yes,locked 2006.201.09:59:41.56/valo/04,624.99,yes,locked 2006.201.09:59:41.56/valo/05,734.99,yes,locked 2006.201.09:59:41.56/valo/06,814.99,yes,locked 2006.201.09:59:41.56/valo/07,864.99,yes,locked 2006.201.09:59:41.56/valo/08,884.99,yes,locked 2006.201.09:59:42.65/vb/01,04,usb,yes,28,26 2006.201.09:59:42.65/vb/02,05,usb,yes,27,27 2006.201.09:59:42.65/vb/03,04,usb,yes,28,31 2006.201.09:59:42.65/vb/04,05,usb,yes,28,27 2006.201.09:59:42.65/vb/05,04,usb,yes,25,27 2006.201.09:59:42.65/vb/06,04,usb,yes,29,25 2006.201.09:59:42.65/vb/07,04,usb,yes,29,29 2006.201.09:59:42.65/vb/08,04,usb,yes,26,30 2006.201.09:59:42.89/vblo/01,629.99,yes,locked 2006.201.09:59:42.89/vblo/02,634.99,yes,locked 2006.201.09:59:42.89/vblo/03,649.99,yes,locked 2006.201.09:59:42.89/vblo/04,679.99,yes,locked 2006.201.09:59:42.89/vblo/05,709.99,yes,locked 2006.201.09:59:42.89/vblo/06,719.99,yes,locked 2006.201.09:59:42.89/vblo/07,734.99,yes,locked 2006.201.09:59:42.89/vblo/08,744.99,yes,locked 2006.201.09:59:43.04/vabw/8 2006.201.09:59:43.19/vbbw/8 2006.201.09:59:43.28/xfe/off,on,16.0 2006.201.09:59:43.66/ifatt/23,28,28,28 2006.201.09:59:44.05/fmout-gps/S +4.58E-07 2006.201.09:59:44.12:!2006.201.10:01:20 2006.201.10:01:20.00:data_valid=off 2006.201.10:01:20.00:"et 2006.201.10:01:20.00:!+3s 2006.201.10:01:23.02:"tape 2006.201.10:01:23.02:postob 2006.201.10:01:23.19/cable/+6.4687E-03 2006.201.10:01:23.19/wx/22.18,1003.6,95 2006.201.10:01:23.25/fmout-gps/S +4.59E-07 2006.201.10:01:23.25:scan_name=201-1003,jd0607,360 2006.201.10:01:23.25:source=1308+326,131028.66,322043.8,2000.0,cw 2006.201.10:01:25.14#flagr#flagr/antenna,new-source 2006.201.10:01:25.14:checkk5 2006.201.10:01:25.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:01:25.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:01:26.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:01:26.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:01:27.00/chk_obsdata//k5ts1/T2010959??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.10:01:27.37/chk_obsdata//k5ts2/T2010959??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.10:01:27.74/chk_obsdata//k5ts3/T2010959??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.10:01:28.10/chk_obsdata//k5ts4/T2010959??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.10:01:28.79/k5log//k5ts1_log_newline 2006.201.10:01:29.48/k5log//k5ts2_log_newline 2006.201.10:01:30.17/k5log//k5ts3_log_newline 2006.201.10:01:30.85/k5log//k5ts4_log_newline 2006.201.10:01:30.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:01:30.88:setupk4=1 2006.201.10:01:30.88$setupk4/echo=on 2006.201.10:01:30.88$setupk4/pcalon 2006.201.10:01:30.88$pcalon/"no phase cal control is implemented here 2006.201.10:01:30.88$setupk4/"tpicd=stop 2006.201.10:01:30.88$setupk4/"rec=synch_on 2006.201.10:01:30.88$setupk4/"rec_mode=128 2006.201.10:01:30.88$setupk4/!* 2006.201.10:01:30.88$setupk4/recpk4 2006.201.10:01:30.88$recpk4/recpatch= 2006.201.10:01:30.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:01:30.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:01:30.88$setupk4/vck44 2006.201.10:01:30.88$vck44/valo=1,524.99 2006.201.10:01:30.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.10:01:30.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.10:01:30.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:30.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:30.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:30.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:30.88#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:01:30.88#ibcon#first serial, iclass 12, count 0 2006.201.10:01:30.88#ibcon#enter sib2, iclass 12, count 0 2006.201.10:01:30.88#ibcon#flushed, iclass 12, count 0 2006.201.10:01:30.88#ibcon#about to write, iclass 12, count 0 2006.201.10:01:30.88#ibcon#wrote, iclass 12, count 0 2006.201.10:01:30.88#ibcon#about to read 3, iclass 12, count 0 2006.201.10:01:30.90#ibcon#read 3, iclass 12, count 0 2006.201.10:01:30.90#ibcon#about to read 4, iclass 12, count 0 2006.201.10:01:30.90#ibcon#read 4, iclass 12, count 0 2006.201.10:01:30.90#ibcon#about to read 5, iclass 12, count 0 2006.201.10:01:30.90#ibcon#read 5, iclass 12, count 0 2006.201.10:01:30.90#ibcon#about to read 6, iclass 12, count 0 2006.201.10:01:30.90#ibcon#read 6, iclass 12, count 0 2006.201.10:01:30.90#ibcon#end of sib2, iclass 12, count 0 2006.201.10:01:30.90#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:01:30.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:01:30.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:01:30.90#ibcon#*before write, iclass 12, count 0 2006.201.10:01:30.90#ibcon#enter sib2, iclass 12, count 0 2006.201.10:01:30.90#ibcon#flushed, iclass 12, count 0 2006.201.10:01:30.90#ibcon#about to write, iclass 12, count 0 2006.201.10:01:30.90#ibcon#wrote, iclass 12, count 0 2006.201.10:01:30.90#ibcon#about to read 3, iclass 12, count 0 2006.201.10:01:30.95#ibcon#read 3, iclass 12, count 0 2006.201.10:01:30.95#ibcon#about to read 4, iclass 12, count 0 2006.201.10:01:30.95#ibcon#read 4, iclass 12, count 0 2006.201.10:01:30.95#ibcon#about to read 5, iclass 12, count 0 2006.201.10:01:30.95#ibcon#read 5, iclass 12, count 0 2006.201.10:01:30.95#ibcon#about to read 6, iclass 12, count 0 2006.201.10:01:30.95#ibcon#read 6, iclass 12, count 0 2006.201.10:01:30.95#ibcon#end of sib2, iclass 12, count 0 2006.201.10:01:30.95#ibcon#*after write, iclass 12, count 0 2006.201.10:01:30.95#ibcon#*before return 0, iclass 12, count 0 2006.201.10:01:30.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:30.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:30.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:01:30.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:01:30.95$vck44/va=1,8 2006.201.10:01:30.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.10:01:30.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.10:01:30.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:30.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:30.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:30.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:30.95#ibcon#enter wrdev, iclass 14, count 2 2006.201.10:01:30.95#ibcon#first serial, iclass 14, count 2 2006.201.10:01:30.95#ibcon#enter sib2, iclass 14, count 2 2006.201.10:01:30.95#ibcon#flushed, iclass 14, count 2 2006.201.10:01:30.95#ibcon#about to write, iclass 14, count 2 2006.201.10:01:30.95#ibcon#wrote, iclass 14, count 2 2006.201.10:01:30.95#ibcon#about to read 3, iclass 14, count 2 2006.201.10:01:30.97#ibcon#read 3, iclass 14, count 2 2006.201.10:01:30.97#ibcon#about to read 4, iclass 14, count 2 2006.201.10:01:30.97#ibcon#read 4, iclass 14, count 2 2006.201.10:01:30.97#ibcon#about to read 5, iclass 14, count 2 2006.201.10:01:30.97#ibcon#read 5, iclass 14, count 2 2006.201.10:01:30.97#ibcon#about to read 6, iclass 14, count 2 2006.201.10:01:30.97#ibcon#read 6, iclass 14, count 2 2006.201.10:01:30.97#ibcon#end of sib2, iclass 14, count 2 2006.201.10:01:30.97#ibcon#*mode == 0, iclass 14, count 2 2006.201.10:01:30.97#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.10:01:30.97#ibcon#[25=AT01-08\r\n] 2006.201.10:01:30.97#ibcon#*before write, iclass 14, count 2 2006.201.10:01:30.97#ibcon#enter sib2, iclass 14, count 2 2006.201.10:01:30.97#ibcon#flushed, iclass 14, count 2 2006.201.10:01:30.97#ibcon#about to write, iclass 14, count 2 2006.201.10:01:30.97#ibcon#wrote, iclass 14, count 2 2006.201.10:01:30.97#ibcon#about to read 3, iclass 14, count 2 2006.201.10:01:31.00#ibcon#read 3, iclass 14, count 2 2006.201.10:01:31.00#ibcon#about to read 4, iclass 14, count 2 2006.201.10:01:31.00#ibcon#read 4, iclass 14, count 2 2006.201.10:01:31.00#ibcon#about to read 5, iclass 14, count 2 2006.201.10:01:31.00#ibcon#read 5, iclass 14, count 2 2006.201.10:01:31.00#ibcon#about to read 6, iclass 14, count 2 2006.201.10:01:31.00#ibcon#read 6, iclass 14, count 2 2006.201.10:01:31.00#ibcon#end of sib2, iclass 14, count 2 2006.201.10:01:31.00#ibcon#*after write, iclass 14, count 2 2006.201.10:01:31.00#ibcon#*before return 0, iclass 14, count 2 2006.201.10:01:31.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:31.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:31.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.10:01:31.00#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:31.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:31.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:31.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:31.12#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:01:31.12#ibcon#first serial, iclass 14, count 0 2006.201.10:01:31.12#ibcon#enter sib2, iclass 14, count 0 2006.201.10:01:31.12#ibcon#flushed, iclass 14, count 0 2006.201.10:01:31.12#ibcon#about to write, iclass 14, count 0 2006.201.10:01:31.12#ibcon#wrote, iclass 14, count 0 2006.201.10:01:31.12#ibcon#about to read 3, iclass 14, count 0 2006.201.10:01:31.14#ibcon#read 3, iclass 14, count 0 2006.201.10:01:31.14#ibcon#about to read 4, iclass 14, count 0 2006.201.10:01:31.14#ibcon#read 4, iclass 14, count 0 2006.201.10:01:31.14#ibcon#about to read 5, iclass 14, count 0 2006.201.10:01:31.14#ibcon#read 5, iclass 14, count 0 2006.201.10:01:31.14#ibcon#about to read 6, iclass 14, count 0 2006.201.10:01:31.14#ibcon#read 6, iclass 14, count 0 2006.201.10:01:31.14#ibcon#end of sib2, iclass 14, count 0 2006.201.10:01:31.14#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:01:31.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:01:31.14#ibcon#[25=USB\r\n] 2006.201.10:01:31.14#ibcon#*before write, iclass 14, count 0 2006.201.10:01:31.14#ibcon#enter sib2, iclass 14, count 0 2006.201.10:01:31.14#ibcon#flushed, iclass 14, count 0 2006.201.10:01:31.14#ibcon#about to write, iclass 14, count 0 2006.201.10:01:31.14#ibcon#wrote, iclass 14, count 0 2006.201.10:01:31.14#ibcon#about to read 3, iclass 14, count 0 2006.201.10:01:31.17#ibcon#read 3, iclass 14, count 0 2006.201.10:01:31.17#ibcon#about to read 4, iclass 14, count 0 2006.201.10:01:31.17#ibcon#read 4, iclass 14, count 0 2006.201.10:01:31.17#ibcon#about to read 5, iclass 14, count 0 2006.201.10:01:31.17#ibcon#read 5, iclass 14, count 0 2006.201.10:01:31.17#ibcon#about to read 6, iclass 14, count 0 2006.201.10:01:31.17#ibcon#read 6, iclass 14, count 0 2006.201.10:01:31.17#ibcon#end of sib2, iclass 14, count 0 2006.201.10:01:31.17#ibcon#*after write, iclass 14, count 0 2006.201.10:01:31.17#ibcon#*before return 0, iclass 14, count 0 2006.201.10:01:31.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:31.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:31.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:01:31.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:01:31.17$vck44/valo=2,534.99 2006.201.10:01:31.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.10:01:31.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.10:01:31.17#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:31.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:31.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:31.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:31.17#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:01:31.17#ibcon#first serial, iclass 16, count 0 2006.201.10:01:31.17#ibcon#enter sib2, iclass 16, count 0 2006.201.10:01:31.17#ibcon#flushed, iclass 16, count 0 2006.201.10:01:31.17#ibcon#about to write, iclass 16, count 0 2006.201.10:01:31.17#ibcon#wrote, iclass 16, count 0 2006.201.10:01:31.17#ibcon#about to read 3, iclass 16, count 0 2006.201.10:01:31.19#ibcon#read 3, iclass 16, count 0 2006.201.10:01:31.19#ibcon#about to read 4, iclass 16, count 0 2006.201.10:01:31.19#ibcon#read 4, iclass 16, count 0 2006.201.10:01:31.19#ibcon#about to read 5, iclass 16, count 0 2006.201.10:01:31.19#ibcon#read 5, iclass 16, count 0 2006.201.10:01:31.19#ibcon#about to read 6, iclass 16, count 0 2006.201.10:01:31.19#ibcon#read 6, iclass 16, count 0 2006.201.10:01:31.19#ibcon#end of sib2, iclass 16, count 0 2006.201.10:01:31.19#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:01:31.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:01:31.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:01:31.19#ibcon#*before write, iclass 16, count 0 2006.201.10:01:31.19#ibcon#enter sib2, iclass 16, count 0 2006.201.10:01:31.19#ibcon#flushed, iclass 16, count 0 2006.201.10:01:31.19#ibcon#about to write, iclass 16, count 0 2006.201.10:01:31.19#ibcon#wrote, iclass 16, count 0 2006.201.10:01:31.19#ibcon#about to read 3, iclass 16, count 0 2006.201.10:01:31.24#ibcon#read 3, iclass 16, count 0 2006.201.10:01:31.24#ibcon#about to read 4, iclass 16, count 0 2006.201.10:01:31.24#ibcon#read 4, iclass 16, count 0 2006.201.10:01:31.24#ibcon#about to read 5, iclass 16, count 0 2006.201.10:01:31.24#ibcon#read 5, iclass 16, count 0 2006.201.10:01:31.24#ibcon#about to read 6, iclass 16, count 0 2006.201.10:01:31.24#ibcon#read 6, iclass 16, count 0 2006.201.10:01:31.24#ibcon#end of sib2, iclass 16, count 0 2006.201.10:01:31.24#ibcon#*after write, iclass 16, count 0 2006.201.10:01:31.24#ibcon#*before return 0, iclass 16, count 0 2006.201.10:01:31.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:31.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:31.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:01:31.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:01:31.24$vck44/va=2,7 2006.201.10:01:31.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.10:01:31.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.10:01:31.24#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:31.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:31.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:31.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:31.29#ibcon#enter wrdev, iclass 18, count 2 2006.201.10:01:31.29#ibcon#first serial, iclass 18, count 2 2006.201.10:01:31.29#ibcon#enter sib2, iclass 18, count 2 2006.201.10:01:31.29#ibcon#flushed, iclass 18, count 2 2006.201.10:01:31.29#ibcon#about to write, iclass 18, count 2 2006.201.10:01:31.29#ibcon#wrote, iclass 18, count 2 2006.201.10:01:31.29#ibcon#about to read 3, iclass 18, count 2 2006.201.10:01:31.31#ibcon#read 3, iclass 18, count 2 2006.201.10:01:31.31#ibcon#about to read 4, iclass 18, count 2 2006.201.10:01:31.31#ibcon#read 4, iclass 18, count 2 2006.201.10:01:31.31#ibcon#about to read 5, iclass 18, count 2 2006.201.10:01:31.31#ibcon#read 5, iclass 18, count 2 2006.201.10:01:31.31#ibcon#about to read 6, iclass 18, count 2 2006.201.10:01:31.31#ibcon#read 6, iclass 18, count 2 2006.201.10:01:31.31#ibcon#end of sib2, iclass 18, count 2 2006.201.10:01:31.31#ibcon#*mode == 0, iclass 18, count 2 2006.201.10:01:31.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.10:01:31.31#ibcon#[25=AT02-07\r\n] 2006.201.10:01:31.31#ibcon#*before write, iclass 18, count 2 2006.201.10:01:31.31#ibcon#enter sib2, iclass 18, count 2 2006.201.10:01:31.31#ibcon#flushed, iclass 18, count 2 2006.201.10:01:31.31#ibcon#about to write, iclass 18, count 2 2006.201.10:01:31.31#ibcon#wrote, iclass 18, count 2 2006.201.10:01:31.31#ibcon#about to read 3, iclass 18, count 2 2006.201.10:01:31.34#ibcon#read 3, iclass 18, count 2 2006.201.10:01:31.34#ibcon#about to read 4, iclass 18, count 2 2006.201.10:01:31.34#ibcon#read 4, iclass 18, count 2 2006.201.10:01:31.34#ibcon#about to read 5, iclass 18, count 2 2006.201.10:01:31.34#ibcon#read 5, iclass 18, count 2 2006.201.10:01:31.34#ibcon#about to read 6, iclass 18, count 2 2006.201.10:01:31.34#ibcon#read 6, iclass 18, count 2 2006.201.10:01:31.34#ibcon#end of sib2, iclass 18, count 2 2006.201.10:01:31.34#ibcon#*after write, iclass 18, count 2 2006.201.10:01:31.34#ibcon#*before return 0, iclass 18, count 2 2006.201.10:01:31.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:31.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:31.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.10:01:31.34#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:31.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:31.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:31.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:31.46#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:01:31.46#ibcon#first serial, iclass 18, count 0 2006.201.10:01:31.46#ibcon#enter sib2, iclass 18, count 0 2006.201.10:01:31.46#ibcon#flushed, iclass 18, count 0 2006.201.10:01:31.46#ibcon#about to write, iclass 18, count 0 2006.201.10:01:31.46#ibcon#wrote, iclass 18, count 0 2006.201.10:01:31.46#ibcon#about to read 3, iclass 18, count 0 2006.201.10:01:31.48#ibcon#read 3, iclass 18, count 0 2006.201.10:01:31.48#ibcon#about to read 4, iclass 18, count 0 2006.201.10:01:31.48#ibcon#read 4, iclass 18, count 0 2006.201.10:01:31.48#ibcon#about to read 5, iclass 18, count 0 2006.201.10:01:31.48#ibcon#read 5, iclass 18, count 0 2006.201.10:01:31.48#ibcon#about to read 6, iclass 18, count 0 2006.201.10:01:31.48#ibcon#read 6, iclass 18, count 0 2006.201.10:01:31.48#ibcon#end of sib2, iclass 18, count 0 2006.201.10:01:31.48#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:01:31.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:01:31.48#ibcon#[25=USB\r\n] 2006.201.10:01:31.48#ibcon#*before write, iclass 18, count 0 2006.201.10:01:31.48#ibcon#enter sib2, iclass 18, count 0 2006.201.10:01:31.48#ibcon#flushed, iclass 18, count 0 2006.201.10:01:31.48#ibcon#about to write, iclass 18, count 0 2006.201.10:01:31.48#ibcon#wrote, iclass 18, count 0 2006.201.10:01:31.48#ibcon#about to read 3, iclass 18, count 0 2006.201.10:01:31.51#ibcon#read 3, iclass 18, count 0 2006.201.10:01:31.51#ibcon#about to read 4, iclass 18, count 0 2006.201.10:01:31.51#ibcon#read 4, iclass 18, count 0 2006.201.10:01:31.51#ibcon#about to read 5, iclass 18, count 0 2006.201.10:01:31.51#ibcon#read 5, iclass 18, count 0 2006.201.10:01:31.51#ibcon#about to read 6, iclass 18, count 0 2006.201.10:01:31.51#ibcon#read 6, iclass 18, count 0 2006.201.10:01:31.51#ibcon#end of sib2, iclass 18, count 0 2006.201.10:01:31.51#ibcon#*after write, iclass 18, count 0 2006.201.10:01:31.51#ibcon#*before return 0, iclass 18, count 0 2006.201.10:01:31.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:31.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:31.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:01:31.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:01:31.51$vck44/valo=3,564.99 2006.201.10:01:31.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.10:01:31.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.10:01:31.51#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:31.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:31.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:31.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:31.51#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:01:31.51#ibcon#first serial, iclass 20, count 0 2006.201.10:01:31.51#ibcon#enter sib2, iclass 20, count 0 2006.201.10:01:31.51#ibcon#flushed, iclass 20, count 0 2006.201.10:01:31.51#ibcon#about to write, iclass 20, count 0 2006.201.10:01:31.51#ibcon#wrote, iclass 20, count 0 2006.201.10:01:31.51#ibcon#about to read 3, iclass 20, count 0 2006.201.10:01:31.53#ibcon#read 3, iclass 20, count 0 2006.201.10:01:31.53#ibcon#about to read 4, iclass 20, count 0 2006.201.10:01:31.53#ibcon#read 4, iclass 20, count 0 2006.201.10:01:31.53#ibcon#about to read 5, iclass 20, count 0 2006.201.10:01:31.53#ibcon#read 5, iclass 20, count 0 2006.201.10:01:31.53#ibcon#about to read 6, iclass 20, count 0 2006.201.10:01:31.53#ibcon#read 6, iclass 20, count 0 2006.201.10:01:31.53#ibcon#end of sib2, iclass 20, count 0 2006.201.10:01:31.53#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:01:31.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:01:31.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:01:31.53#ibcon#*before write, iclass 20, count 0 2006.201.10:01:31.53#ibcon#enter sib2, iclass 20, count 0 2006.201.10:01:31.53#ibcon#flushed, iclass 20, count 0 2006.201.10:01:31.53#ibcon#about to write, iclass 20, count 0 2006.201.10:01:31.53#ibcon#wrote, iclass 20, count 0 2006.201.10:01:31.53#ibcon#about to read 3, iclass 20, count 0 2006.201.10:01:31.58#ibcon#read 3, iclass 20, count 0 2006.201.10:01:31.58#ibcon#about to read 4, iclass 20, count 0 2006.201.10:01:31.58#ibcon#read 4, iclass 20, count 0 2006.201.10:01:31.58#ibcon#about to read 5, iclass 20, count 0 2006.201.10:01:31.58#ibcon#read 5, iclass 20, count 0 2006.201.10:01:31.58#ibcon#about to read 6, iclass 20, count 0 2006.201.10:01:31.58#ibcon#read 6, iclass 20, count 0 2006.201.10:01:31.58#ibcon#end of sib2, iclass 20, count 0 2006.201.10:01:31.58#ibcon#*after write, iclass 20, count 0 2006.201.10:01:31.58#ibcon#*before return 0, iclass 20, count 0 2006.201.10:01:31.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:31.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:31.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:01:31.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:01:31.58$vck44/va=3,8 2006.201.10:01:31.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.10:01:31.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.10:01:31.58#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:31.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:31.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:31.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:31.63#ibcon#enter wrdev, iclass 22, count 2 2006.201.10:01:31.63#ibcon#first serial, iclass 22, count 2 2006.201.10:01:31.63#ibcon#enter sib2, iclass 22, count 2 2006.201.10:01:31.63#ibcon#flushed, iclass 22, count 2 2006.201.10:01:31.63#ibcon#about to write, iclass 22, count 2 2006.201.10:01:31.63#ibcon#wrote, iclass 22, count 2 2006.201.10:01:31.63#ibcon#about to read 3, iclass 22, count 2 2006.201.10:01:31.65#ibcon#read 3, iclass 22, count 2 2006.201.10:01:31.65#ibcon#about to read 4, iclass 22, count 2 2006.201.10:01:31.65#ibcon#read 4, iclass 22, count 2 2006.201.10:01:31.65#ibcon#about to read 5, iclass 22, count 2 2006.201.10:01:31.65#ibcon#read 5, iclass 22, count 2 2006.201.10:01:31.65#ibcon#about to read 6, iclass 22, count 2 2006.201.10:01:31.65#ibcon#read 6, iclass 22, count 2 2006.201.10:01:31.65#ibcon#end of sib2, iclass 22, count 2 2006.201.10:01:31.65#ibcon#*mode == 0, iclass 22, count 2 2006.201.10:01:31.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.10:01:31.65#ibcon#[25=AT03-08\r\n] 2006.201.10:01:31.65#ibcon#*before write, iclass 22, count 2 2006.201.10:01:31.65#ibcon#enter sib2, iclass 22, count 2 2006.201.10:01:31.65#ibcon#flushed, iclass 22, count 2 2006.201.10:01:31.65#ibcon#about to write, iclass 22, count 2 2006.201.10:01:31.65#ibcon#wrote, iclass 22, count 2 2006.201.10:01:31.65#ibcon#about to read 3, iclass 22, count 2 2006.201.10:01:31.68#ibcon#read 3, iclass 22, count 2 2006.201.10:01:31.68#ibcon#about to read 4, iclass 22, count 2 2006.201.10:01:31.68#ibcon#read 4, iclass 22, count 2 2006.201.10:01:31.68#ibcon#about to read 5, iclass 22, count 2 2006.201.10:01:31.68#ibcon#read 5, iclass 22, count 2 2006.201.10:01:31.68#ibcon#about to read 6, iclass 22, count 2 2006.201.10:01:31.68#ibcon#read 6, iclass 22, count 2 2006.201.10:01:31.68#ibcon#end of sib2, iclass 22, count 2 2006.201.10:01:31.68#ibcon#*after write, iclass 22, count 2 2006.201.10:01:31.68#ibcon#*before return 0, iclass 22, count 2 2006.201.10:01:31.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:31.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:31.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.10:01:31.68#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:31.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:31.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:31.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:31.80#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:01:31.80#ibcon#first serial, iclass 22, count 0 2006.201.10:01:31.80#ibcon#enter sib2, iclass 22, count 0 2006.201.10:01:31.80#ibcon#flushed, iclass 22, count 0 2006.201.10:01:31.80#ibcon#about to write, iclass 22, count 0 2006.201.10:01:31.80#ibcon#wrote, iclass 22, count 0 2006.201.10:01:31.80#ibcon#about to read 3, iclass 22, count 0 2006.201.10:01:31.82#ibcon#read 3, iclass 22, count 0 2006.201.10:01:31.82#ibcon#about to read 4, iclass 22, count 0 2006.201.10:01:31.82#ibcon#read 4, iclass 22, count 0 2006.201.10:01:31.82#ibcon#about to read 5, iclass 22, count 0 2006.201.10:01:31.82#ibcon#read 5, iclass 22, count 0 2006.201.10:01:31.82#ibcon#about to read 6, iclass 22, count 0 2006.201.10:01:31.82#ibcon#read 6, iclass 22, count 0 2006.201.10:01:31.82#ibcon#end of sib2, iclass 22, count 0 2006.201.10:01:31.82#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:01:31.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:01:31.82#ibcon#[25=USB\r\n] 2006.201.10:01:31.82#ibcon#*before write, iclass 22, count 0 2006.201.10:01:31.82#ibcon#enter sib2, iclass 22, count 0 2006.201.10:01:31.82#ibcon#flushed, iclass 22, count 0 2006.201.10:01:31.82#ibcon#about to write, iclass 22, count 0 2006.201.10:01:31.82#ibcon#wrote, iclass 22, count 0 2006.201.10:01:31.82#ibcon#about to read 3, iclass 22, count 0 2006.201.10:01:31.85#ibcon#read 3, iclass 22, count 0 2006.201.10:01:31.85#ibcon#about to read 4, iclass 22, count 0 2006.201.10:01:31.85#ibcon#read 4, iclass 22, count 0 2006.201.10:01:31.85#ibcon#about to read 5, iclass 22, count 0 2006.201.10:01:31.85#ibcon#read 5, iclass 22, count 0 2006.201.10:01:31.85#ibcon#about to read 6, iclass 22, count 0 2006.201.10:01:31.85#ibcon#read 6, iclass 22, count 0 2006.201.10:01:31.85#ibcon#end of sib2, iclass 22, count 0 2006.201.10:01:31.85#ibcon#*after write, iclass 22, count 0 2006.201.10:01:31.85#ibcon#*before return 0, iclass 22, count 0 2006.201.10:01:31.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:31.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:31.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:01:31.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:01:31.85$vck44/valo=4,624.99 2006.201.10:01:31.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.10:01:31.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.10:01:31.85#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:31.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:31.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:31.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:31.85#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:01:31.85#ibcon#first serial, iclass 24, count 0 2006.201.10:01:31.85#ibcon#enter sib2, iclass 24, count 0 2006.201.10:01:31.85#ibcon#flushed, iclass 24, count 0 2006.201.10:01:31.85#ibcon#about to write, iclass 24, count 0 2006.201.10:01:31.85#ibcon#wrote, iclass 24, count 0 2006.201.10:01:31.85#ibcon#about to read 3, iclass 24, count 0 2006.201.10:01:31.87#ibcon#read 3, iclass 24, count 0 2006.201.10:01:31.87#ibcon#about to read 4, iclass 24, count 0 2006.201.10:01:31.87#ibcon#read 4, iclass 24, count 0 2006.201.10:01:31.87#ibcon#about to read 5, iclass 24, count 0 2006.201.10:01:31.87#ibcon#read 5, iclass 24, count 0 2006.201.10:01:31.87#ibcon#about to read 6, iclass 24, count 0 2006.201.10:01:31.87#ibcon#read 6, iclass 24, count 0 2006.201.10:01:31.87#ibcon#end of sib2, iclass 24, count 0 2006.201.10:01:31.87#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:01:31.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:01:31.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:01:31.87#ibcon#*before write, iclass 24, count 0 2006.201.10:01:31.87#ibcon#enter sib2, iclass 24, count 0 2006.201.10:01:31.87#ibcon#flushed, iclass 24, count 0 2006.201.10:01:31.87#ibcon#about to write, iclass 24, count 0 2006.201.10:01:31.87#ibcon#wrote, iclass 24, count 0 2006.201.10:01:31.87#ibcon#about to read 3, iclass 24, count 0 2006.201.10:01:31.92#ibcon#read 3, iclass 24, count 0 2006.201.10:01:31.92#ibcon#about to read 4, iclass 24, count 0 2006.201.10:01:31.92#ibcon#read 4, iclass 24, count 0 2006.201.10:01:31.92#ibcon#about to read 5, iclass 24, count 0 2006.201.10:01:31.92#ibcon#read 5, iclass 24, count 0 2006.201.10:01:31.92#ibcon#about to read 6, iclass 24, count 0 2006.201.10:01:31.92#ibcon#read 6, iclass 24, count 0 2006.201.10:01:31.92#ibcon#end of sib2, iclass 24, count 0 2006.201.10:01:31.92#ibcon#*after write, iclass 24, count 0 2006.201.10:01:31.92#ibcon#*before return 0, iclass 24, count 0 2006.201.10:01:31.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:31.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:31.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:01:31.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:01:31.92$vck44/va=4,7 2006.201.10:01:31.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.10:01:31.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.10:01:31.92#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:31.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:31.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:31.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:31.97#ibcon#enter wrdev, iclass 26, count 2 2006.201.10:01:31.97#ibcon#first serial, iclass 26, count 2 2006.201.10:01:31.97#ibcon#enter sib2, iclass 26, count 2 2006.201.10:01:31.97#ibcon#flushed, iclass 26, count 2 2006.201.10:01:31.97#ibcon#about to write, iclass 26, count 2 2006.201.10:01:31.97#ibcon#wrote, iclass 26, count 2 2006.201.10:01:31.97#ibcon#about to read 3, iclass 26, count 2 2006.201.10:01:31.99#ibcon#read 3, iclass 26, count 2 2006.201.10:01:31.99#ibcon#about to read 4, iclass 26, count 2 2006.201.10:01:31.99#ibcon#read 4, iclass 26, count 2 2006.201.10:01:31.99#ibcon#about to read 5, iclass 26, count 2 2006.201.10:01:31.99#ibcon#read 5, iclass 26, count 2 2006.201.10:01:31.99#ibcon#about to read 6, iclass 26, count 2 2006.201.10:01:31.99#ibcon#read 6, iclass 26, count 2 2006.201.10:01:31.99#ibcon#end of sib2, iclass 26, count 2 2006.201.10:01:31.99#ibcon#*mode == 0, iclass 26, count 2 2006.201.10:01:31.99#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.10:01:31.99#ibcon#[25=AT04-07\r\n] 2006.201.10:01:31.99#ibcon#*before write, iclass 26, count 2 2006.201.10:01:31.99#ibcon#enter sib2, iclass 26, count 2 2006.201.10:01:31.99#ibcon#flushed, iclass 26, count 2 2006.201.10:01:31.99#ibcon#about to write, iclass 26, count 2 2006.201.10:01:31.99#ibcon#wrote, iclass 26, count 2 2006.201.10:01:31.99#ibcon#about to read 3, iclass 26, count 2 2006.201.10:01:32.02#ibcon#read 3, iclass 26, count 2 2006.201.10:01:32.02#ibcon#about to read 4, iclass 26, count 2 2006.201.10:01:32.02#ibcon#read 4, iclass 26, count 2 2006.201.10:01:32.02#ibcon#about to read 5, iclass 26, count 2 2006.201.10:01:32.02#ibcon#read 5, iclass 26, count 2 2006.201.10:01:32.02#ibcon#about to read 6, iclass 26, count 2 2006.201.10:01:32.02#ibcon#read 6, iclass 26, count 2 2006.201.10:01:32.02#ibcon#end of sib2, iclass 26, count 2 2006.201.10:01:32.02#ibcon#*after write, iclass 26, count 2 2006.201.10:01:32.02#ibcon#*before return 0, iclass 26, count 2 2006.201.10:01:32.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:32.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:32.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.10:01:32.02#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:32.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:32.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:32.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:32.14#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:01:32.14#ibcon#first serial, iclass 26, count 0 2006.201.10:01:32.14#ibcon#enter sib2, iclass 26, count 0 2006.201.10:01:32.14#ibcon#flushed, iclass 26, count 0 2006.201.10:01:32.14#ibcon#about to write, iclass 26, count 0 2006.201.10:01:32.14#ibcon#wrote, iclass 26, count 0 2006.201.10:01:32.14#ibcon#about to read 3, iclass 26, count 0 2006.201.10:01:32.16#ibcon#read 3, iclass 26, count 0 2006.201.10:01:32.16#ibcon#about to read 4, iclass 26, count 0 2006.201.10:01:32.16#ibcon#read 4, iclass 26, count 0 2006.201.10:01:32.16#ibcon#about to read 5, iclass 26, count 0 2006.201.10:01:32.16#ibcon#read 5, iclass 26, count 0 2006.201.10:01:32.16#ibcon#about to read 6, iclass 26, count 0 2006.201.10:01:32.16#ibcon#read 6, iclass 26, count 0 2006.201.10:01:32.16#ibcon#end of sib2, iclass 26, count 0 2006.201.10:01:32.16#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:01:32.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:01:32.16#ibcon#[25=USB\r\n] 2006.201.10:01:32.16#ibcon#*before write, iclass 26, count 0 2006.201.10:01:32.16#ibcon#enter sib2, iclass 26, count 0 2006.201.10:01:32.16#ibcon#flushed, iclass 26, count 0 2006.201.10:01:32.16#ibcon#about to write, iclass 26, count 0 2006.201.10:01:32.16#ibcon#wrote, iclass 26, count 0 2006.201.10:01:32.16#ibcon#about to read 3, iclass 26, count 0 2006.201.10:01:32.19#ibcon#read 3, iclass 26, count 0 2006.201.10:01:32.19#ibcon#about to read 4, iclass 26, count 0 2006.201.10:01:32.19#ibcon#read 4, iclass 26, count 0 2006.201.10:01:32.19#ibcon#about to read 5, iclass 26, count 0 2006.201.10:01:32.19#ibcon#read 5, iclass 26, count 0 2006.201.10:01:32.19#ibcon#about to read 6, iclass 26, count 0 2006.201.10:01:32.19#ibcon#read 6, iclass 26, count 0 2006.201.10:01:32.19#ibcon#end of sib2, iclass 26, count 0 2006.201.10:01:32.19#ibcon#*after write, iclass 26, count 0 2006.201.10:01:32.19#ibcon#*before return 0, iclass 26, count 0 2006.201.10:01:32.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:32.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:32.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:01:32.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:01:32.19$vck44/valo=5,734.99 2006.201.10:01:32.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.10:01:32.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.10:01:32.19#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:32.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:32.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:32.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:32.19#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:01:32.19#ibcon#first serial, iclass 28, count 0 2006.201.10:01:32.19#ibcon#enter sib2, iclass 28, count 0 2006.201.10:01:32.19#ibcon#flushed, iclass 28, count 0 2006.201.10:01:32.19#ibcon#about to write, iclass 28, count 0 2006.201.10:01:32.19#ibcon#wrote, iclass 28, count 0 2006.201.10:01:32.19#ibcon#about to read 3, iclass 28, count 0 2006.201.10:01:32.21#ibcon#read 3, iclass 28, count 0 2006.201.10:01:32.21#ibcon#about to read 4, iclass 28, count 0 2006.201.10:01:32.21#ibcon#read 4, iclass 28, count 0 2006.201.10:01:32.21#ibcon#about to read 5, iclass 28, count 0 2006.201.10:01:32.21#ibcon#read 5, iclass 28, count 0 2006.201.10:01:32.21#ibcon#about to read 6, iclass 28, count 0 2006.201.10:01:32.21#ibcon#read 6, iclass 28, count 0 2006.201.10:01:32.21#ibcon#end of sib2, iclass 28, count 0 2006.201.10:01:32.21#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:01:32.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:01:32.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:01:32.21#ibcon#*before write, iclass 28, count 0 2006.201.10:01:32.21#ibcon#enter sib2, iclass 28, count 0 2006.201.10:01:32.21#ibcon#flushed, iclass 28, count 0 2006.201.10:01:32.21#ibcon#about to write, iclass 28, count 0 2006.201.10:01:32.21#ibcon#wrote, iclass 28, count 0 2006.201.10:01:32.21#ibcon#about to read 3, iclass 28, count 0 2006.201.10:01:32.25#ibcon#read 3, iclass 28, count 0 2006.201.10:01:32.25#ibcon#about to read 4, iclass 28, count 0 2006.201.10:01:32.25#ibcon#read 4, iclass 28, count 0 2006.201.10:01:32.25#ibcon#about to read 5, iclass 28, count 0 2006.201.10:01:32.25#ibcon#read 5, iclass 28, count 0 2006.201.10:01:32.25#ibcon#about to read 6, iclass 28, count 0 2006.201.10:01:32.25#ibcon#read 6, iclass 28, count 0 2006.201.10:01:32.25#ibcon#end of sib2, iclass 28, count 0 2006.201.10:01:32.25#ibcon#*after write, iclass 28, count 0 2006.201.10:01:32.25#ibcon#*before return 0, iclass 28, count 0 2006.201.10:01:32.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:32.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:32.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:01:32.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:01:32.25$vck44/va=5,4 2006.201.10:01:32.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.10:01:32.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.10:01:32.25#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:32.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:32.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:32.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:32.31#ibcon#enter wrdev, iclass 30, count 2 2006.201.10:01:32.31#ibcon#first serial, iclass 30, count 2 2006.201.10:01:32.31#ibcon#enter sib2, iclass 30, count 2 2006.201.10:01:32.31#ibcon#flushed, iclass 30, count 2 2006.201.10:01:32.31#ibcon#about to write, iclass 30, count 2 2006.201.10:01:32.31#ibcon#wrote, iclass 30, count 2 2006.201.10:01:32.31#ibcon#about to read 3, iclass 30, count 2 2006.201.10:01:32.33#ibcon#read 3, iclass 30, count 2 2006.201.10:01:32.33#ibcon#about to read 4, iclass 30, count 2 2006.201.10:01:32.33#ibcon#read 4, iclass 30, count 2 2006.201.10:01:32.33#ibcon#about to read 5, iclass 30, count 2 2006.201.10:01:32.33#ibcon#read 5, iclass 30, count 2 2006.201.10:01:32.33#ibcon#about to read 6, iclass 30, count 2 2006.201.10:01:32.33#ibcon#read 6, iclass 30, count 2 2006.201.10:01:32.33#ibcon#end of sib2, iclass 30, count 2 2006.201.10:01:32.33#ibcon#*mode == 0, iclass 30, count 2 2006.201.10:01:32.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.10:01:32.33#ibcon#[25=AT05-04\r\n] 2006.201.10:01:32.33#ibcon#*before write, iclass 30, count 2 2006.201.10:01:32.33#ibcon#enter sib2, iclass 30, count 2 2006.201.10:01:32.33#ibcon#flushed, iclass 30, count 2 2006.201.10:01:32.33#ibcon#about to write, iclass 30, count 2 2006.201.10:01:32.33#ibcon#wrote, iclass 30, count 2 2006.201.10:01:32.33#ibcon#about to read 3, iclass 30, count 2 2006.201.10:01:32.36#ibcon#read 3, iclass 30, count 2 2006.201.10:01:32.36#ibcon#about to read 4, iclass 30, count 2 2006.201.10:01:32.36#ibcon#read 4, iclass 30, count 2 2006.201.10:01:32.36#ibcon#about to read 5, iclass 30, count 2 2006.201.10:01:32.36#ibcon#read 5, iclass 30, count 2 2006.201.10:01:32.36#ibcon#about to read 6, iclass 30, count 2 2006.201.10:01:32.36#ibcon#read 6, iclass 30, count 2 2006.201.10:01:32.36#ibcon#end of sib2, iclass 30, count 2 2006.201.10:01:32.36#ibcon#*after write, iclass 30, count 2 2006.201.10:01:32.36#ibcon#*before return 0, iclass 30, count 2 2006.201.10:01:32.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:32.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:32.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.10:01:32.36#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:32.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:32.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:32.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:32.48#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:01:32.48#ibcon#first serial, iclass 30, count 0 2006.201.10:01:32.48#ibcon#enter sib2, iclass 30, count 0 2006.201.10:01:32.48#ibcon#flushed, iclass 30, count 0 2006.201.10:01:32.48#ibcon#about to write, iclass 30, count 0 2006.201.10:01:32.48#ibcon#wrote, iclass 30, count 0 2006.201.10:01:32.48#ibcon#about to read 3, iclass 30, count 0 2006.201.10:01:32.50#ibcon#read 3, iclass 30, count 0 2006.201.10:01:32.50#ibcon#about to read 4, iclass 30, count 0 2006.201.10:01:32.50#ibcon#read 4, iclass 30, count 0 2006.201.10:01:32.50#ibcon#about to read 5, iclass 30, count 0 2006.201.10:01:32.50#ibcon#read 5, iclass 30, count 0 2006.201.10:01:32.50#ibcon#about to read 6, iclass 30, count 0 2006.201.10:01:32.50#ibcon#read 6, iclass 30, count 0 2006.201.10:01:32.50#ibcon#end of sib2, iclass 30, count 0 2006.201.10:01:32.50#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:01:32.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:01:32.50#ibcon#[25=USB\r\n] 2006.201.10:01:32.50#ibcon#*before write, iclass 30, count 0 2006.201.10:01:32.50#ibcon#enter sib2, iclass 30, count 0 2006.201.10:01:32.50#ibcon#flushed, iclass 30, count 0 2006.201.10:01:32.50#ibcon#about to write, iclass 30, count 0 2006.201.10:01:32.50#ibcon#wrote, iclass 30, count 0 2006.201.10:01:32.50#ibcon#about to read 3, iclass 30, count 0 2006.201.10:01:32.53#ibcon#read 3, iclass 30, count 0 2006.201.10:01:32.53#ibcon#about to read 4, iclass 30, count 0 2006.201.10:01:32.53#ibcon#read 4, iclass 30, count 0 2006.201.10:01:32.53#ibcon#about to read 5, iclass 30, count 0 2006.201.10:01:32.53#ibcon#read 5, iclass 30, count 0 2006.201.10:01:32.53#ibcon#about to read 6, iclass 30, count 0 2006.201.10:01:32.53#ibcon#read 6, iclass 30, count 0 2006.201.10:01:32.53#ibcon#end of sib2, iclass 30, count 0 2006.201.10:01:32.53#ibcon#*after write, iclass 30, count 0 2006.201.10:01:32.53#ibcon#*before return 0, iclass 30, count 0 2006.201.10:01:32.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:32.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:32.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:01:32.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:01:32.53$vck44/valo=6,814.99 2006.201.10:01:32.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.10:01:32.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.10:01:32.53#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:32.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:32.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:32.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:32.53#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:01:32.53#ibcon#first serial, iclass 32, count 0 2006.201.10:01:32.53#ibcon#enter sib2, iclass 32, count 0 2006.201.10:01:32.53#ibcon#flushed, iclass 32, count 0 2006.201.10:01:32.53#ibcon#about to write, iclass 32, count 0 2006.201.10:01:32.53#ibcon#wrote, iclass 32, count 0 2006.201.10:01:32.53#ibcon#about to read 3, iclass 32, count 0 2006.201.10:01:32.55#ibcon#read 3, iclass 32, count 0 2006.201.10:01:32.55#ibcon#about to read 4, iclass 32, count 0 2006.201.10:01:32.55#ibcon#read 4, iclass 32, count 0 2006.201.10:01:32.55#ibcon#about to read 5, iclass 32, count 0 2006.201.10:01:32.55#ibcon#read 5, iclass 32, count 0 2006.201.10:01:32.55#ibcon#about to read 6, iclass 32, count 0 2006.201.10:01:32.55#ibcon#read 6, iclass 32, count 0 2006.201.10:01:32.55#ibcon#end of sib2, iclass 32, count 0 2006.201.10:01:32.55#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:01:32.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:01:32.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:01:32.55#ibcon#*before write, iclass 32, count 0 2006.201.10:01:32.55#ibcon#enter sib2, iclass 32, count 0 2006.201.10:01:32.55#ibcon#flushed, iclass 32, count 0 2006.201.10:01:32.55#ibcon#about to write, iclass 32, count 0 2006.201.10:01:32.55#ibcon#wrote, iclass 32, count 0 2006.201.10:01:32.55#ibcon#about to read 3, iclass 32, count 0 2006.201.10:01:32.60#ibcon#read 3, iclass 32, count 0 2006.201.10:01:32.60#ibcon#about to read 4, iclass 32, count 0 2006.201.10:01:32.60#ibcon#read 4, iclass 32, count 0 2006.201.10:01:32.60#ibcon#about to read 5, iclass 32, count 0 2006.201.10:01:32.60#ibcon#read 5, iclass 32, count 0 2006.201.10:01:32.60#ibcon#about to read 6, iclass 32, count 0 2006.201.10:01:32.60#ibcon#read 6, iclass 32, count 0 2006.201.10:01:32.60#ibcon#end of sib2, iclass 32, count 0 2006.201.10:01:32.60#ibcon#*after write, iclass 32, count 0 2006.201.10:01:32.60#ibcon#*before return 0, iclass 32, count 0 2006.201.10:01:32.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:32.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:32.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:01:32.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:01:32.60$vck44/va=6,5 2006.201.10:01:32.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.10:01:32.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.10:01:32.60#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:32.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:32.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:32.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:32.65#ibcon#enter wrdev, iclass 34, count 2 2006.201.10:01:32.65#ibcon#first serial, iclass 34, count 2 2006.201.10:01:32.65#ibcon#enter sib2, iclass 34, count 2 2006.201.10:01:32.65#ibcon#flushed, iclass 34, count 2 2006.201.10:01:32.65#ibcon#about to write, iclass 34, count 2 2006.201.10:01:32.65#ibcon#wrote, iclass 34, count 2 2006.201.10:01:32.65#ibcon#about to read 3, iclass 34, count 2 2006.201.10:01:32.67#ibcon#read 3, iclass 34, count 2 2006.201.10:01:32.67#ibcon#about to read 4, iclass 34, count 2 2006.201.10:01:32.67#ibcon#read 4, iclass 34, count 2 2006.201.10:01:32.67#ibcon#about to read 5, iclass 34, count 2 2006.201.10:01:32.67#ibcon#read 5, iclass 34, count 2 2006.201.10:01:32.67#ibcon#about to read 6, iclass 34, count 2 2006.201.10:01:32.67#ibcon#read 6, iclass 34, count 2 2006.201.10:01:32.67#ibcon#end of sib2, iclass 34, count 2 2006.201.10:01:32.67#ibcon#*mode == 0, iclass 34, count 2 2006.201.10:01:32.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.10:01:32.67#ibcon#[25=AT06-05\r\n] 2006.201.10:01:32.67#ibcon#*before write, iclass 34, count 2 2006.201.10:01:32.67#ibcon#enter sib2, iclass 34, count 2 2006.201.10:01:32.67#ibcon#flushed, iclass 34, count 2 2006.201.10:01:32.67#ibcon#about to write, iclass 34, count 2 2006.201.10:01:32.67#ibcon#wrote, iclass 34, count 2 2006.201.10:01:32.67#ibcon#about to read 3, iclass 34, count 2 2006.201.10:01:32.70#ibcon#read 3, iclass 34, count 2 2006.201.10:01:32.70#ibcon#about to read 4, iclass 34, count 2 2006.201.10:01:32.70#ibcon#read 4, iclass 34, count 2 2006.201.10:01:32.70#ibcon#about to read 5, iclass 34, count 2 2006.201.10:01:32.70#ibcon#read 5, iclass 34, count 2 2006.201.10:01:32.70#ibcon#about to read 6, iclass 34, count 2 2006.201.10:01:32.70#ibcon#read 6, iclass 34, count 2 2006.201.10:01:32.70#ibcon#end of sib2, iclass 34, count 2 2006.201.10:01:32.70#ibcon#*after write, iclass 34, count 2 2006.201.10:01:32.70#ibcon#*before return 0, iclass 34, count 2 2006.201.10:01:32.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:32.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:32.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.10:01:32.70#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:32.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:32.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:32.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:32.82#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:01:32.82#ibcon#first serial, iclass 34, count 0 2006.201.10:01:32.82#ibcon#enter sib2, iclass 34, count 0 2006.201.10:01:32.82#ibcon#flushed, iclass 34, count 0 2006.201.10:01:32.82#ibcon#about to write, iclass 34, count 0 2006.201.10:01:32.82#ibcon#wrote, iclass 34, count 0 2006.201.10:01:32.82#ibcon#about to read 3, iclass 34, count 0 2006.201.10:01:32.84#ibcon#read 3, iclass 34, count 0 2006.201.10:01:32.84#ibcon#about to read 4, iclass 34, count 0 2006.201.10:01:32.84#ibcon#read 4, iclass 34, count 0 2006.201.10:01:32.84#ibcon#about to read 5, iclass 34, count 0 2006.201.10:01:32.84#ibcon#read 5, iclass 34, count 0 2006.201.10:01:32.84#ibcon#about to read 6, iclass 34, count 0 2006.201.10:01:32.84#ibcon#read 6, iclass 34, count 0 2006.201.10:01:32.84#ibcon#end of sib2, iclass 34, count 0 2006.201.10:01:32.84#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:01:32.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:01:32.84#ibcon#[25=USB\r\n] 2006.201.10:01:32.84#ibcon#*before write, iclass 34, count 0 2006.201.10:01:32.84#ibcon#enter sib2, iclass 34, count 0 2006.201.10:01:32.84#ibcon#flushed, iclass 34, count 0 2006.201.10:01:32.84#ibcon#about to write, iclass 34, count 0 2006.201.10:01:32.84#ibcon#wrote, iclass 34, count 0 2006.201.10:01:32.84#ibcon#about to read 3, iclass 34, count 0 2006.201.10:01:32.87#ibcon#read 3, iclass 34, count 0 2006.201.10:01:32.87#ibcon#about to read 4, iclass 34, count 0 2006.201.10:01:32.87#ibcon#read 4, iclass 34, count 0 2006.201.10:01:32.87#ibcon#about to read 5, iclass 34, count 0 2006.201.10:01:32.87#ibcon#read 5, iclass 34, count 0 2006.201.10:01:32.87#ibcon#about to read 6, iclass 34, count 0 2006.201.10:01:32.87#ibcon#read 6, iclass 34, count 0 2006.201.10:01:32.87#ibcon#end of sib2, iclass 34, count 0 2006.201.10:01:32.87#ibcon#*after write, iclass 34, count 0 2006.201.10:01:32.87#ibcon#*before return 0, iclass 34, count 0 2006.201.10:01:32.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:32.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:32.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:01:32.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:01:32.87$vck44/valo=7,864.99 2006.201.10:01:32.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.10:01:32.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.10:01:32.87#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:32.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:32.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:32.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:32.87#ibcon#enter wrdev, iclass 36, count 0 2006.201.10:01:32.87#ibcon#first serial, iclass 36, count 0 2006.201.10:01:32.87#ibcon#enter sib2, iclass 36, count 0 2006.201.10:01:32.87#ibcon#flushed, iclass 36, count 0 2006.201.10:01:32.87#ibcon#about to write, iclass 36, count 0 2006.201.10:01:32.87#ibcon#wrote, iclass 36, count 0 2006.201.10:01:32.87#ibcon#about to read 3, iclass 36, count 0 2006.201.10:01:32.89#ibcon#read 3, iclass 36, count 0 2006.201.10:01:32.89#ibcon#about to read 4, iclass 36, count 0 2006.201.10:01:32.89#ibcon#read 4, iclass 36, count 0 2006.201.10:01:32.89#ibcon#about to read 5, iclass 36, count 0 2006.201.10:01:32.89#ibcon#read 5, iclass 36, count 0 2006.201.10:01:32.89#ibcon#about to read 6, iclass 36, count 0 2006.201.10:01:32.89#ibcon#read 6, iclass 36, count 0 2006.201.10:01:32.89#ibcon#end of sib2, iclass 36, count 0 2006.201.10:01:32.89#ibcon#*mode == 0, iclass 36, count 0 2006.201.10:01:32.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.10:01:32.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:01:32.89#ibcon#*before write, iclass 36, count 0 2006.201.10:01:32.89#ibcon#enter sib2, iclass 36, count 0 2006.201.10:01:32.89#ibcon#flushed, iclass 36, count 0 2006.201.10:01:32.89#ibcon#about to write, iclass 36, count 0 2006.201.10:01:32.89#ibcon#wrote, iclass 36, count 0 2006.201.10:01:32.89#ibcon#about to read 3, iclass 36, count 0 2006.201.10:01:32.94#ibcon#read 3, iclass 36, count 0 2006.201.10:01:32.94#ibcon#about to read 4, iclass 36, count 0 2006.201.10:01:32.94#ibcon#read 4, iclass 36, count 0 2006.201.10:01:32.94#ibcon#about to read 5, iclass 36, count 0 2006.201.10:01:32.94#ibcon#read 5, iclass 36, count 0 2006.201.10:01:32.94#ibcon#about to read 6, iclass 36, count 0 2006.201.10:01:32.94#ibcon#read 6, iclass 36, count 0 2006.201.10:01:32.94#ibcon#end of sib2, iclass 36, count 0 2006.201.10:01:32.94#ibcon#*after write, iclass 36, count 0 2006.201.10:01:32.94#ibcon#*before return 0, iclass 36, count 0 2006.201.10:01:32.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:32.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:32.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.10:01:32.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.10:01:32.94$vck44/va=7,5 2006.201.10:01:32.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.10:01:32.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.10:01:32.94#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:32.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:32.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:32.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:32.99#ibcon#enter wrdev, iclass 38, count 2 2006.201.10:01:32.99#ibcon#first serial, iclass 38, count 2 2006.201.10:01:32.99#ibcon#enter sib2, iclass 38, count 2 2006.201.10:01:32.99#ibcon#flushed, iclass 38, count 2 2006.201.10:01:32.99#ibcon#about to write, iclass 38, count 2 2006.201.10:01:32.99#ibcon#wrote, iclass 38, count 2 2006.201.10:01:32.99#ibcon#about to read 3, iclass 38, count 2 2006.201.10:01:33.01#ibcon#read 3, iclass 38, count 2 2006.201.10:01:33.01#ibcon#about to read 4, iclass 38, count 2 2006.201.10:01:33.01#ibcon#read 4, iclass 38, count 2 2006.201.10:01:33.01#ibcon#about to read 5, iclass 38, count 2 2006.201.10:01:33.01#ibcon#read 5, iclass 38, count 2 2006.201.10:01:33.01#ibcon#about to read 6, iclass 38, count 2 2006.201.10:01:33.01#ibcon#read 6, iclass 38, count 2 2006.201.10:01:33.01#ibcon#end of sib2, iclass 38, count 2 2006.201.10:01:33.01#ibcon#*mode == 0, iclass 38, count 2 2006.201.10:01:33.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.10:01:33.01#ibcon#[25=AT07-05\r\n] 2006.201.10:01:33.01#ibcon#*before write, iclass 38, count 2 2006.201.10:01:33.01#ibcon#enter sib2, iclass 38, count 2 2006.201.10:01:33.01#ibcon#flushed, iclass 38, count 2 2006.201.10:01:33.01#ibcon#about to write, iclass 38, count 2 2006.201.10:01:33.01#ibcon#wrote, iclass 38, count 2 2006.201.10:01:33.01#ibcon#about to read 3, iclass 38, count 2 2006.201.10:01:33.04#ibcon#read 3, iclass 38, count 2 2006.201.10:01:33.04#ibcon#about to read 4, iclass 38, count 2 2006.201.10:01:33.04#ibcon#read 4, iclass 38, count 2 2006.201.10:01:33.04#ibcon#about to read 5, iclass 38, count 2 2006.201.10:01:33.04#ibcon#read 5, iclass 38, count 2 2006.201.10:01:33.04#ibcon#about to read 6, iclass 38, count 2 2006.201.10:01:33.04#ibcon#read 6, iclass 38, count 2 2006.201.10:01:33.04#ibcon#end of sib2, iclass 38, count 2 2006.201.10:01:33.04#ibcon#*after write, iclass 38, count 2 2006.201.10:01:33.04#ibcon#*before return 0, iclass 38, count 2 2006.201.10:01:33.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:33.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:33.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.10:01:33.04#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:33.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:33.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:33.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:33.16#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:01:33.16#ibcon#first serial, iclass 38, count 0 2006.201.10:01:33.16#ibcon#enter sib2, iclass 38, count 0 2006.201.10:01:33.16#ibcon#flushed, iclass 38, count 0 2006.201.10:01:33.16#ibcon#about to write, iclass 38, count 0 2006.201.10:01:33.16#ibcon#wrote, iclass 38, count 0 2006.201.10:01:33.16#ibcon#about to read 3, iclass 38, count 0 2006.201.10:01:33.18#ibcon#read 3, iclass 38, count 0 2006.201.10:01:33.18#ibcon#about to read 4, iclass 38, count 0 2006.201.10:01:33.18#ibcon#read 4, iclass 38, count 0 2006.201.10:01:33.18#ibcon#about to read 5, iclass 38, count 0 2006.201.10:01:33.18#ibcon#read 5, iclass 38, count 0 2006.201.10:01:33.18#ibcon#about to read 6, iclass 38, count 0 2006.201.10:01:33.18#ibcon#read 6, iclass 38, count 0 2006.201.10:01:33.18#ibcon#end of sib2, iclass 38, count 0 2006.201.10:01:33.18#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:01:33.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:01:33.18#ibcon#[25=USB\r\n] 2006.201.10:01:33.18#ibcon#*before write, iclass 38, count 0 2006.201.10:01:33.18#ibcon#enter sib2, iclass 38, count 0 2006.201.10:01:33.18#ibcon#flushed, iclass 38, count 0 2006.201.10:01:33.18#ibcon#about to write, iclass 38, count 0 2006.201.10:01:33.18#ibcon#wrote, iclass 38, count 0 2006.201.10:01:33.18#ibcon#about to read 3, iclass 38, count 0 2006.201.10:01:33.21#ibcon#read 3, iclass 38, count 0 2006.201.10:01:33.21#ibcon#about to read 4, iclass 38, count 0 2006.201.10:01:33.21#ibcon#read 4, iclass 38, count 0 2006.201.10:01:33.21#ibcon#about to read 5, iclass 38, count 0 2006.201.10:01:33.21#ibcon#read 5, iclass 38, count 0 2006.201.10:01:33.21#ibcon#about to read 6, iclass 38, count 0 2006.201.10:01:33.21#ibcon#read 6, iclass 38, count 0 2006.201.10:01:33.21#ibcon#end of sib2, iclass 38, count 0 2006.201.10:01:33.21#ibcon#*after write, iclass 38, count 0 2006.201.10:01:33.21#ibcon#*before return 0, iclass 38, count 0 2006.201.10:01:33.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:33.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:33.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:01:33.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:01:33.21$vck44/valo=8,884.99 2006.201.10:01:33.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.10:01:33.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.10:01:33.21#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:33.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:33.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:33.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:33.21#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:01:33.21#ibcon#first serial, iclass 40, count 0 2006.201.10:01:33.21#ibcon#enter sib2, iclass 40, count 0 2006.201.10:01:33.21#ibcon#flushed, iclass 40, count 0 2006.201.10:01:33.21#ibcon#about to write, iclass 40, count 0 2006.201.10:01:33.21#ibcon#wrote, iclass 40, count 0 2006.201.10:01:33.21#ibcon#about to read 3, iclass 40, count 0 2006.201.10:01:33.23#ibcon#read 3, iclass 40, count 0 2006.201.10:01:33.23#ibcon#about to read 4, iclass 40, count 0 2006.201.10:01:33.23#ibcon#read 4, iclass 40, count 0 2006.201.10:01:33.23#ibcon#about to read 5, iclass 40, count 0 2006.201.10:01:33.23#ibcon#read 5, iclass 40, count 0 2006.201.10:01:33.23#ibcon#about to read 6, iclass 40, count 0 2006.201.10:01:33.23#ibcon#read 6, iclass 40, count 0 2006.201.10:01:33.23#ibcon#end of sib2, iclass 40, count 0 2006.201.10:01:33.23#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:01:33.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:01:33.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:01:33.23#ibcon#*before write, iclass 40, count 0 2006.201.10:01:33.23#ibcon#enter sib2, iclass 40, count 0 2006.201.10:01:33.23#ibcon#flushed, iclass 40, count 0 2006.201.10:01:33.23#ibcon#about to write, iclass 40, count 0 2006.201.10:01:33.23#ibcon#wrote, iclass 40, count 0 2006.201.10:01:33.23#ibcon#about to read 3, iclass 40, count 0 2006.201.10:01:33.27#ibcon#read 3, iclass 40, count 0 2006.201.10:01:33.27#ibcon#about to read 4, iclass 40, count 0 2006.201.10:01:33.27#ibcon#read 4, iclass 40, count 0 2006.201.10:01:33.27#ibcon#about to read 5, iclass 40, count 0 2006.201.10:01:33.27#ibcon#read 5, iclass 40, count 0 2006.201.10:01:33.27#ibcon#about to read 6, iclass 40, count 0 2006.201.10:01:33.27#ibcon#read 6, iclass 40, count 0 2006.201.10:01:33.27#ibcon#end of sib2, iclass 40, count 0 2006.201.10:01:33.27#ibcon#*after write, iclass 40, count 0 2006.201.10:01:33.27#ibcon#*before return 0, iclass 40, count 0 2006.201.10:01:33.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:33.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:33.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:01:33.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:01:33.27$vck44/va=8,4 2006.201.10:01:33.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.10:01:33.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.10:01:33.27#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:33.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:01:33.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:01:33.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:01:33.33#ibcon#enter wrdev, iclass 4, count 2 2006.201.10:01:33.33#ibcon#first serial, iclass 4, count 2 2006.201.10:01:33.33#ibcon#enter sib2, iclass 4, count 2 2006.201.10:01:33.33#ibcon#flushed, iclass 4, count 2 2006.201.10:01:33.33#ibcon#about to write, iclass 4, count 2 2006.201.10:01:33.33#ibcon#wrote, iclass 4, count 2 2006.201.10:01:33.33#ibcon#about to read 3, iclass 4, count 2 2006.201.10:01:33.35#ibcon#read 3, iclass 4, count 2 2006.201.10:01:33.35#ibcon#about to read 4, iclass 4, count 2 2006.201.10:01:33.35#ibcon#read 4, iclass 4, count 2 2006.201.10:01:33.35#ibcon#about to read 5, iclass 4, count 2 2006.201.10:01:33.35#ibcon#read 5, iclass 4, count 2 2006.201.10:01:33.35#ibcon#about to read 6, iclass 4, count 2 2006.201.10:01:33.35#ibcon#read 6, iclass 4, count 2 2006.201.10:01:33.35#ibcon#end of sib2, iclass 4, count 2 2006.201.10:01:33.35#ibcon#*mode == 0, iclass 4, count 2 2006.201.10:01:33.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.10:01:33.35#ibcon#[25=AT08-04\r\n] 2006.201.10:01:33.35#ibcon#*before write, iclass 4, count 2 2006.201.10:01:33.35#ibcon#enter sib2, iclass 4, count 2 2006.201.10:01:33.35#ibcon#flushed, iclass 4, count 2 2006.201.10:01:33.35#ibcon#about to write, iclass 4, count 2 2006.201.10:01:33.35#ibcon#wrote, iclass 4, count 2 2006.201.10:01:33.35#ibcon#about to read 3, iclass 4, count 2 2006.201.10:01:33.38#ibcon#read 3, iclass 4, count 2 2006.201.10:01:33.38#ibcon#about to read 4, iclass 4, count 2 2006.201.10:01:33.38#ibcon#read 4, iclass 4, count 2 2006.201.10:01:33.38#ibcon#about to read 5, iclass 4, count 2 2006.201.10:01:33.38#ibcon#read 5, iclass 4, count 2 2006.201.10:01:33.38#ibcon#about to read 6, iclass 4, count 2 2006.201.10:01:33.38#ibcon#read 6, iclass 4, count 2 2006.201.10:01:33.38#ibcon#end of sib2, iclass 4, count 2 2006.201.10:01:33.38#ibcon#*after write, iclass 4, count 2 2006.201.10:01:33.38#ibcon#*before return 0, iclass 4, count 2 2006.201.10:01:33.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:01:33.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:01:33.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.10:01:33.38#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:33.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:01:33.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:01:33.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:01:33.50#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:01:33.50#ibcon#first serial, iclass 4, count 0 2006.201.10:01:33.50#ibcon#enter sib2, iclass 4, count 0 2006.201.10:01:33.50#ibcon#flushed, iclass 4, count 0 2006.201.10:01:33.50#ibcon#about to write, iclass 4, count 0 2006.201.10:01:33.50#ibcon#wrote, iclass 4, count 0 2006.201.10:01:33.50#ibcon#about to read 3, iclass 4, count 0 2006.201.10:01:33.52#ibcon#read 3, iclass 4, count 0 2006.201.10:01:33.52#ibcon#about to read 4, iclass 4, count 0 2006.201.10:01:33.52#ibcon#read 4, iclass 4, count 0 2006.201.10:01:33.52#ibcon#about to read 5, iclass 4, count 0 2006.201.10:01:33.52#ibcon#read 5, iclass 4, count 0 2006.201.10:01:33.52#ibcon#about to read 6, iclass 4, count 0 2006.201.10:01:33.52#ibcon#read 6, iclass 4, count 0 2006.201.10:01:33.52#ibcon#end of sib2, iclass 4, count 0 2006.201.10:01:33.52#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:01:33.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:01:33.52#ibcon#[25=USB\r\n] 2006.201.10:01:33.52#ibcon#*before write, iclass 4, count 0 2006.201.10:01:33.52#ibcon#enter sib2, iclass 4, count 0 2006.201.10:01:33.52#ibcon#flushed, iclass 4, count 0 2006.201.10:01:33.52#ibcon#about to write, iclass 4, count 0 2006.201.10:01:33.52#ibcon#wrote, iclass 4, count 0 2006.201.10:01:33.52#ibcon#about to read 3, iclass 4, count 0 2006.201.10:01:33.55#ibcon#read 3, iclass 4, count 0 2006.201.10:01:33.55#ibcon#about to read 4, iclass 4, count 0 2006.201.10:01:33.55#ibcon#read 4, iclass 4, count 0 2006.201.10:01:33.55#ibcon#about to read 5, iclass 4, count 0 2006.201.10:01:33.55#ibcon#read 5, iclass 4, count 0 2006.201.10:01:33.55#ibcon#about to read 6, iclass 4, count 0 2006.201.10:01:33.55#ibcon#read 6, iclass 4, count 0 2006.201.10:01:33.55#ibcon#end of sib2, iclass 4, count 0 2006.201.10:01:33.55#ibcon#*after write, iclass 4, count 0 2006.201.10:01:33.55#ibcon#*before return 0, iclass 4, count 0 2006.201.10:01:33.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:01:33.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:01:33.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:01:33.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:01:33.55$vck44/vblo=1,629.99 2006.201.10:01:33.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.10:01:33.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.10:01:33.55#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:33.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:01:33.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:01:33.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:01:33.55#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:01:33.55#ibcon#first serial, iclass 6, count 0 2006.201.10:01:33.55#ibcon#enter sib2, iclass 6, count 0 2006.201.10:01:33.55#ibcon#flushed, iclass 6, count 0 2006.201.10:01:33.55#ibcon#about to write, iclass 6, count 0 2006.201.10:01:33.55#ibcon#wrote, iclass 6, count 0 2006.201.10:01:33.55#ibcon#about to read 3, iclass 6, count 0 2006.201.10:01:33.57#ibcon#read 3, iclass 6, count 0 2006.201.10:01:33.57#ibcon#about to read 4, iclass 6, count 0 2006.201.10:01:33.57#ibcon#read 4, iclass 6, count 0 2006.201.10:01:33.57#ibcon#about to read 5, iclass 6, count 0 2006.201.10:01:33.57#ibcon#read 5, iclass 6, count 0 2006.201.10:01:33.57#ibcon#about to read 6, iclass 6, count 0 2006.201.10:01:33.57#ibcon#read 6, iclass 6, count 0 2006.201.10:01:33.57#ibcon#end of sib2, iclass 6, count 0 2006.201.10:01:33.57#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:01:33.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:01:33.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:01:33.57#ibcon#*before write, iclass 6, count 0 2006.201.10:01:33.57#ibcon#enter sib2, iclass 6, count 0 2006.201.10:01:33.57#ibcon#flushed, iclass 6, count 0 2006.201.10:01:33.57#ibcon#about to write, iclass 6, count 0 2006.201.10:01:33.57#ibcon#wrote, iclass 6, count 0 2006.201.10:01:33.57#ibcon#about to read 3, iclass 6, count 0 2006.201.10:01:33.62#ibcon#read 3, iclass 6, count 0 2006.201.10:01:33.62#ibcon#about to read 4, iclass 6, count 0 2006.201.10:01:33.62#ibcon#read 4, iclass 6, count 0 2006.201.10:01:33.62#ibcon#about to read 5, iclass 6, count 0 2006.201.10:01:33.62#ibcon#read 5, iclass 6, count 0 2006.201.10:01:33.62#ibcon#about to read 6, iclass 6, count 0 2006.201.10:01:33.62#ibcon#read 6, iclass 6, count 0 2006.201.10:01:33.62#ibcon#end of sib2, iclass 6, count 0 2006.201.10:01:33.62#ibcon#*after write, iclass 6, count 0 2006.201.10:01:33.62#ibcon#*before return 0, iclass 6, count 0 2006.201.10:01:33.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:01:33.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:01:33.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:01:33.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:01:33.62$vck44/vb=1,4 2006.201.10:01:33.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.10:01:33.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.10:01:33.62#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:33.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:01:33.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:01:33.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:01:33.62#ibcon#enter wrdev, iclass 10, count 2 2006.201.10:01:33.62#ibcon#first serial, iclass 10, count 2 2006.201.10:01:33.62#ibcon#enter sib2, iclass 10, count 2 2006.201.10:01:33.62#ibcon#flushed, iclass 10, count 2 2006.201.10:01:33.62#ibcon#about to write, iclass 10, count 2 2006.201.10:01:33.62#ibcon#wrote, iclass 10, count 2 2006.201.10:01:33.62#ibcon#about to read 3, iclass 10, count 2 2006.201.10:01:33.64#ibcon#read 3, iclass 10, count 2 2006.201.10:01:33.64#ibcon#about to read 4, iclass 10, count 2 2006.201.10:01:33.64#ibcon#read 4, iclass 10, count 2 2006.201.10:01:33.64#ibcon#about to read 5, iclass 10, count 2 2006.201.10:01:33.64#ibcon#read 5, iclass 10, count 2 2006.201.10:01:33.64#ibcon#about to read 6, iclass 10, count 2 2006.201.10:01:33.64#ibcon#read 6, iclass 10, count 2 2006.201.10:01:33.64#ibcon#end of sib2, iclass 10, count 2 2006.201.10:01:33.64#ibcon#*mode == 0, iclass 10, count 2 2006.201.10:01:33.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.10:01:33.64#ibcon#[27=AT01-04\r\n] 2006.201.10:01:33.64#ibcon#*before write, iclass 10, count 2 2006.201.10:01:33.64#ibcon#enter sib2, iclass 10, count 2 2006.201.10:01:33.64#ibcon#flushed, iclass 10, count 2 2006.201.10:01:33.64#ibcon#about to write, iclass 10, count 2 2006.201.10:01:33.64#ibcon#wrote, iclass 10, count 2 2006.201.10:01:33.64#ibcon#about to read 3, iclass 10, count 2 2006.201.10:01:33.67#ibcon#read 3, iclass 10, count 2 2006.201.10:01:33.67#ibcon#about to read 4, iclass 10, count 2 2006.201.10:01:33.67#ibcon#read 4, iclass 10, count 2 2006.201.10:01:33.67#ibcon#about to read 5, iclass 10, count 2 2006.201.10:01:33.67#ibcon#read 5, iclass 10, count 2 2006.201.10:01:33.67#ibcon#about to read 6, iclass 10, count 2 2006.201.10:01:33.67#ibcon#read 6, iclass 10, count 2 2006.201.10:01:33.67#ibcon#end of sib2, iclass 10, count 2 2006.201.10:01:33.67#ibcon#*after write, iclass 10, count 2 2006.201.10:01:33.67#ibcon#*before return 0, iclass 10, count 2 2006.201.10:01:33.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:01:33.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:01:33.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.10:01:33.67#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:33.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:01:33.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:01:33.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:01:33.79#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:01:33.79#ibcon#first serial, iclass 10, count 0 2006.201.10:01:33.79#ibcon#enter sib2, iclass 10, count 0 2006.201.10:01:33.79#ibcon#flushed, iclass 10, count 0 2006.201.10:01:33.79#ibcon#about to write, iclass 10, count 0 2006.201.10:01:33.79#ibcon#wrote, iclass 10, count 0 2006.201.10:01:33.79#ibcon#about to read 3, iclass 10, count 0 2006.201.10:01:33.81#ibcon#read 3, iclass 10, count 0 2006.201.10:01:33.81#ibcon#about to read 4, iclass 10, count 0 2006.201.10:01:33.81#ibcon#read 4, iclass 10, count 0 2006.201.10:01:33.81#ibcon#about to read 5, iclass 10, count 0 2006.201.10:01:33.81#ibcon#read 5, iclass 10, count 0 2006.201.10:01:33.81#ibcon#about to read 6, iclass 10, count 0 2006.201.10:01:33.81#ibcon#read 6, iclass 10, count 0 2006.201.10:01:33.81#ibcon#end of sib2, iclass 10, count 0 2006.201.10:01:33.81#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:01:33.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:01:33.81#ibcon#[27=USB\r\n] 2006.201.10:01:33.81#ibcon#*before write, iclass 10, count 0 2006.201.10:01:33.81#ibcon#enter sib2, iclass 10, count 0 2006.201.10:01:33.81#ibcon#flushed, iclass 10, count 0 2006.201.10:01:33.81#ibcon#about to write, iclass 10, count 0 2006.201.10:01:33.81#ibcon#wrote, iclass 10, count 0 2006.201.10:01:33.81#ibcon#about to read 3, iclass 10, count 0 2006.201.10:01:33.84#ibcon#read 3, iclass 10, count 0 2006.201.10:01:33.84#ibcon#about to read 4, iclass 10, count 0 2006.201.10:01:33.84#ibcon#read 4, iclass 10, count 0 2006.201.10:01:33.84#ibcon#about to read 5, iclass 10, count 0 2006.201.10:01:33.84#ibcon#read 5, iclass 10, count 0 2006.201.10:01:33.84#ibcon#about to read 6, iclass 10, count 0 2006.201.10:01:33.84#ibcon#read 6, iclass 10, count 0 2006.201.10:01:33.84#ibcon#end of sib2, iclass 10, count 0 2006.201.10:01:33.84#ibcon#*after write, iclass 10, count 0 2006.201.10:01:33.84#ibcon#*before return 0, iclass 10, count 0 2006.201.10:01:33.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:01:33.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:01:33.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:01:33.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:01:33.84$vck44/vblo=2,634.99 2006.201.10:01:33.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.10:01:33.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.10:01:33.84#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:33.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:33.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:33.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:33.84#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:01:33.84#ibcon#first serial, iclass 12, count 0 2006.201.10:01:33.84#ibcon#enter sib2, iclass 12, count 0 2006.201.10:01:33.84#ibcon#flushed, iclass 12, count 0 2006.201.10:01:33.84#ibcon#about to write, iclass 12, count 0 2006.201.10:01:33.84#ibcon#wrote, iclass 12, count 0 2006.201.10:01:33.84#ibcon#about to read 3, iclass 12, count 0 2006.201.10:01:33.86#ibcon#read 3, iclass 12, count 0 2006.201.10:01:33.86#ibcon#about to read 4, iclass 12, count 0 2006.201.10:01:33.86#ibcon#read 4, iclass 12, count 0 2006.201.10:01:33.86#ibcon#about to read 5, iclass 12, count 0 2006.201.10:01:33.86#ibcon#read 5, iclass 12, count 0 2006.201.10:01:33.86#ibcon#about to read 6, iclass 12, count 0 2006.201.10:01:33.86#ibcon#read 6, iclass 12, count 0 2006.201.10:01:33.86#ibcon#end of sib2, iclass 12, count 0 2006.201.10:01:33.86#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:01:33.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:01:33.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:01:33.86#ibcon#*before write, iclass 12, count 0 2006.201.10:01:33.86#ibcon#enter sib2, iclass 12, count 0 2006.201.10:01:33.86#ibcon#flushed, iclass 12, count 0 2006.201.10:01:33.86#ibcon#about to write, iclass 12, count 0 2006.201.10:01:33.86#ibcon#wrote, iclass 12, count 0 2006.201.10:01:33.86#ibcon#about to read 3, iclass 12, count 0 2006.201.10:01:33.90#ibcon#read 3, iclass 12, count 0 2006.201.10:01:33.90#ibcon#about to read 4, iclass 12, count 0 2006.201.10:01:33.90#ibcon#read 4, iclass 12, count 0 2006.201.10:01:33.90#ibcon#about to read 5, iclass 12, count 0 2006.201.10:01:33.90#ibcon#read 5, iclass 12, count 0 2006.201.10:01:33.90#ibcon#about to read 6, iclass 12, count 0 2006.201.10:01:33.90#ibcon#read 6, iclass 12, count 0 2006.201.10:01:33.90#ibcon#end of sib2, iclass 12, count 0 2006.201.10:01:33.90#ibcon#*after write, iclass 12, count 0 2006.201.10:01:33.90#ibcon#*before return 0, iclass 12, count 0 2006.201.10:01:33.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:33.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:01:33.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:01:33.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:01:33.90$vck44/vb=2,5 2006.201.10:01:33.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.10:01:33.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.10:01:33.90#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:33.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:33.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:33.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:33.96#ibcon#enter wrdev, iclass 14, count 2 2006.201.10:01:33.96#ibcon#first serial, iclass 14, count 2 2006.201.10:01:33.96#ibcon#enter sib2, iclass 14, count 2 2006.201.10:01:33.96#ibcon#flushed, iclass 14, count 2 2006.201.10:01:33.96#ibcon#about to write, iclass 14, count 2 2006.201.10:01:33.96#ibcon#wrote, iclass 14, count 2 2006.201.10:01:33.96#ibcon#about to read 3, iclass 14, count 2 2006.201.10:01:33.98#ibcon#read 3, iclass 14, count 2 2006.201.10:01:33.98#ibcon#about to read 4, iclass 14, count 2 2006.201.10:01:33.98#ibcon#read 4, iclass 14, count 2 2006.201.10:01:33.98#ibcon#about to read 5, iclass 14, count 2 2006.201.10:01:33.98#ibcon#read 5, iclass 14, count 2 2006.201.10:01:33.98#ibcon#about to read 6, iclass 14, count 2 2006.201.10:01:33.98#ibcon#read 6, iclass 14, count 2 2006.201.10:01:33.98#ibcon#end of sib2, iclass 14, count 2 2006.201.10:01:33.98#ibcon#*mode == 0, iclass 14, count 2 2006.201.10:01:33.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.10:01:33.98#ibcon#[27=AT02-05\r\n] 2006.201.10:01:33.98#ibcon#*before write, iclass 14, count 2 2006.201.10:01:33.98#ibcon#enter sib2, iclass 14, count 2 2006.201.10:01:33.98#ibcon#flushed, iclass 14, count 2 2006.201.10:01:33.98#ibcon#about to write, iclass 14, count 2 2006.201.10:01:33.98#ibcon#wrote, iclass 14, count 2 2006.201.10:01:33.98#ibcon#about to read 3, iclass 14, count 2 2006.201.10:01:34.01#ibcon#read 3, iclass 14, count 2 2006.201.10:01:34.01#ibcon#about to read 4, iclass 14, count 2 2006.201.10:01:34.01#ibcon#read 4, iclass 14, count 2 2006.201.10:01:34.01#ibcon#about to read 5, iclass 14, count 2 2006.201.10:01:34.01#ibcon#read 5, iclass 14, count 2 2006.201.10:01:34.01#ibcon#about to read 6, iclass 14, count 2 2006.201.10:01:34.01#ibcon#read 6, iclass 14, count 2 2006.201.10:01:34.01#ibcon#end of sib2, iclass 14, count 2 2006.201.10:01:34.01#ibcon#*after write, iclass 14, count 2 2006.201.10:01:34.01#ibcon#*before return 0, iclass 14, count 2 2006.201.10:01:34.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:34.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:01:34.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.10:01:34.01#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:34.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:34.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:34.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:34.13#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:01:34.13#ibcon#first serial, iclass 14, count 0 2006.201.10:01:34.13#ibcon#enter sib2, iclass 14, count 0 2006.201.10:01:34.13#ibcon#flushed, iclass 14, count 0 2006.201.10:01:34.13#ibcon#about to write, iclass 14, count 0 2006.201.10:01:34.13#ibcon#wrote, iclass 14, count 0 2006.201.10:01:34.13#ibcon#about to read 3, iclass 14, count 0 2006.201.10:01:34.15#ibcon#read 3, iclass 14, count 0 2006.201.10:01:34.15#ibcon#about to read 4, iclass 14, count 0 2006.201.10:01:34.15#ibcon#read 4, iclass 14, count 0 2006.201.10:01:34.15#ibcon#about to read 5, iclass 14, count 0 2006.201.10:01:34.15#ibcon#read 5, iclass 14, count 0 2006.201.10:01:34.15#ibcon#about to read 6, iclass 14, count 0 2006.201.10:01:34.15#ibcon#read 6, iclass 14, count 0 2006.201.10:01:34.15#ibcon#end of sib2, iclass 14, count 0 2006.201.10:01:34.15#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:01:34.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:01:34.15#ibcon#[27=USB\r\n] 2006.201.10:01:34.15#ibcon#*before write, iclass 14, count 0 2006.201.10:01:34.15#ibcon#enter sib2, iclass 14, count 0 2006.201.10:01:34.15#ibcon#flushed, iclass 14, count 0 2006.201.10:01:34.15#ibcon#about to write, iclass 14, count 0 2006.201.10:01:34.15#ibcon#wrote, iclass 14, count 0 2006.201.10:01:34.15#ibcon#about to read 3, iclass 14, count 0 2006.201.10:01:34.18#ibcon#read 3, iclass 14, count 0 2006.201.10:01:34.18#ibcon#about to read 4, iclass 14, count 0 2006.201.10:01:34.18#ibcon#read 4, iclass 14, count 0 2006.201.10:01:34.18#ibcon#about to read 5, iclass 14, count 0 2006.201.10:01:34.18#ibcon#read 5, iclass 14, count 0 2006.201.10:01:34.18#ibcon#about to read 6, iclass 14, count 0 2006.201.10:01:34.18#ibcon#read 6, iclass 14, count 0 2006.201.10:01:34.18#ibcon#end of sib2, iclass 14, count 0 2006.201.10:01:34.18#ibcon#*after write, iclass 14, count 0 2006.201.10:01:34.18#ibcon#*before return 0, iclass 14, count 0 2006.201.10:01:34.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:34.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:01:34.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:01:34.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:01:34.18$vck44/vblo=3,649.99 2006.201.10:01:34.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.10:01:34.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.10:01:34.18#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:34.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:34.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:34.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:34.18#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:01:34.18#ibcon#first serial, iclass 16, count 0 2006.201.10:01:34.18#ibcon#enter sib2, iclass 16, count 0 2006.201.10:01:34.18#ibcon#flushed, iclass 16, count 0 2006.201.10:01:34.18#ibcon#about to write, iclass 16, count 0 2006.201.10:01:34.18#ibcon#wrote, iclass 16, count 0 2006.201.10:01:34.18#ibcon#about to read 3, iclass 16, count 0 2006.201.10:01:34.20#ibcon#read 3, iclass 16, count 0 2006.201.10:01:34.20#ibcon#about to read 4, iclass 16, count 0 2006.201.10:01:34.20#ibcon#read 4, iclass 16, count 0 2006.201.10:01:34.20#ibcon#about to read 5, iclass 16, count 0 2006.201.10:01:34.20#ibcon#read 5, iclass 16, count 0 2006.201.10:01:34.20#ibcon#about to read 6, iclass 16, count 0 2006.201.10:01:34.20#ibcon#read 6, iclass 16, count 0 2006.201.10:01:34.20#ibcon#end of sib2, iclass 16, count 0 2006.201.10:01:34.20#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:01:34.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:01:34.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:01:34.20#ibcon#*before write, iclass 16, count 0 2006.201.10:01:34.20#ibcon#enter sib2, iclass 16, count 0 2006.201.10:01:34.20#ibcon#flushed, iclass 16, count 0 2006.201.10:01:34.20#ibcon#about to write, iclass 16, count 0 2006.201.10:01:34.20#ibcon#wrote, iclass 16, count 0 2006.201.10:01:34.20#ibcon#about to read 3, iclass 16, count 0 2006.201.10:01:34.25#ibcon#read 3, iclass 16, count 0 2006.201.10:01:34.25#ibcon#about to read 4, iclass 16, count 0 2006.201.10:01:34.25#ibcon#read 4, iclass 16, count 0 2006.201.10:01:34.25#ibcon#about to read 5, iclass 16, count 0 2006.201.10:01:34.25#ibcon#read 5, iclass 16, count 0 2006.201.10:01:34.25#ibcon#about to read 6, iclass 16, count 0 2006.201.10:01:34.25#ibcon#read 6, iclass 16, count 0 2006.201.10:01:34.25#ibcon#end of sib2, iclass 16, count 0 2006.201.10:01:34.25#ibcon#*after write, iclass 16, count 0 2006.201.10:01:34.25#ibcon#*before return 0, iclass 16, count 0 2006.201.10:01:34.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:34.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:01:34.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:01:34.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:01:34.25$vck44/vb=3,4 2006.201.10:01:34.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.10:01:34.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.10:01:34.25#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:34.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:34.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:34.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:34.30#ibcon#enter wrdev, iclass 18, count 2 2006.201.10:01:34.30#ibcon#first serial, iclass 18, count 2 2006.201.10:01:34.30#ibcon#enter sib2, iclass 18, count 2 2006.201.10:01:34.30#ibcon#flushed, iclass 18, count 2 2006.201.10:01:34.30#ibcon#about to write, iclass 18, count 2 2006.201.10:01:34.30#ibcon#wrote, iclass 18, count 2 2006.201.10:01:34.30#ibcon#about to read 3, iclass 18, count 2 2006.201.10:01:34.32#ibcon#read 3, iclass 18, count 2 2006.201.10:01:34.32#ibcon#about to read 4, iclass 18, count 2 2006.201.10:01:34.32#ibcon#read 4, iclass 18, count 2 2006.201.10:01:34.32#ibcon#about to read 5, iclass 18, count 2 2006.201.10:01:34.32#ibcon#read 5, iclass 18, count 2 2006.201.10:01:34.32#ibcon#about to read 6, iclass 18, count 2 2006.201.10:01:34.32#ibcon#read 6, iclass 18, count 2 2006.201.10:01:34.32#ibcon#end of sib2, iclass 18, count 2 2006.201.10:01:34.32#ibcon#*mode == 0, iclass 18, count 2 2006.201.10:01:34.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.10:01:34.32#ibcon#[27=AT03-04\r\n] 2006.201.10:01:34.32#ibcon#*before write, iclass 18, count 2 2006.201.10:01:34.32#ibcon#enter sib2, iclass 18, count 2 2006.201.10:01:34.32#ibcon#flushed, iclass 18, count 2 2006.201.10:01:34.32#ibcon#about to write, iclass 18, count 2 2006.201.10:01:34.32#ibcon#wrote, iclass 18, count 2 2006.201.10:01:34.32#ibcon#about to read 3, iclass 18, count 2 2006.201.10:01:34.35#ibcon#read 3, iclass 18, count 2 2006.201.10:01:34.35#ibcon#about to read 4, iclass 18, count 2 2006.201.10:01:34.35#ibcon#read 4, iclass 18, count 2 2006.201.10:01:34.35#ibcon#about to read 5, iclass 18, count 2 2006.201.10:01:34.35#ibcon#read 5, iclass 18, count 2 2006.201.10:01:34.35#ibcon#about to read 6, iclass 18, count 2 2006.201.10:01:34.35#ibcon#read 6, iclass 18, count 2 2006.201.10:01:34.35#ibcon#end of sib2, iclass 18, count 2 2006.201.10:01:34.35#ibcon#*after write, iclass 18, count 2 2006.201.10:01:34.35#ibcon#*before return 0, iclass 18, count 2 2006.201.10:01:34.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:34.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:01:34.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.10:01:34.35#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:34.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:34.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:34.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:34.47#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:01:34.47#ibcon#first serial, iclass 18, count 0 2006.201.10:01:34.47#ibcon#enter sib2, iclass 18, count 0 2006.201.10:01:34.47#ibcon#flushed, iclass 18, count 0 2006.201.10:01:34.47#ibcon#about to write, iclass 18, count 0 2006.201.10:01:34.47#ibcon#wrote, iclass 18, count 0 2006.201.10:01:34.47#ibcon#about to read 3, iclass 18, count 0 2006.201.10:01:34.49#ibcon#read 3, iclass 18, count 0 2006.201.10:01:34.49#ibcon#about to read 4, iclass 18, count 0 2006.201.10:01:34.49#ibcon#read 4, iclass 18, count 0 2006.201.10:01:34.49#ibcon#about to read 5, iclass 18, count 0 2006.201.10:01:34.49#ibcon#read 5, iclass 18, count 0 2006.201.10:01:34.49#ibcon#about to read 6, iclass 18, count 0 2006.201.10:01:34.49#ibcon#read 6, iclass 18, count 0 2006.201.10:01:34.49#ibcon#end of sib2, iclass 18, count 0 2006.201.10:01:34.49#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:01:34.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:01:34.49#ibcon#[27=USB\r\n] 2006.201.10:01:34.49#ibcon#*before write, iclass 18, count 0 2006.201.10:01:34.49#ibcon#enter sib2, iclass 18, count 0 2006.201.10:01:34.49#ibcon#flushed, iclass 18, count 0 2006.201.10:01:34.49#ibcon#about to write, iclass 18, count 0 2006.201.10:01:34.49#ibcon#wrote, iclass 18, count 0 2006.201.10:01:34.49#ibcon#about to read 3, iclass 18, count 0 2006.201.10:01:34.52#ibcon#read 3, iclass 18, count 0 2006.201.10:01:34.52#ibcon#about to read 4, iclass 18, count 0 2006.201.10:01:34.52#ibcon#read 4, iclass 18, count 0 2006.201.10:01:34.52#ibcon#about to read 5, iclass 18, count 0 2006.201.10:01:34.52#ibcon#read 5, iclass 18, count 0 2006.201.10:01:34.52#ibcon#about to read 6, iclass 18, count 0 2006.201.10:01:34.52#ibcon#read 6, iclass 18, count 0 2006.201.10:01:34.52#ibcon#end of sib2, iclass 18, count 0 2006.201.10:01:34.52#ibcon#*after write, iclass 18, count 0 2006.201.10:01:34.52#ibcon#*before return 0, iclass 18, count 0 2006.201.10:01:34.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:34.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:01:34.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:01:34.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:01:34.52$vck44/vblo=4,679.99 2006.201.10:01:34.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.10:01:34.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.10:01:34.52#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:34.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:34.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:34.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:34.52#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:01:34.52#ibcon#first serial, iclass 20, count 0 2006.201.10:01:34.52#ibcon#enter sib2, iclass 20, count 0 2006.201.10:01:34.52#ibcon#flushed, iclass 20, count 0 2006.201.10:01:34.52#ibcon#about to write, iclass 20, count 0 2006.201.10:01:34.52#ibcon#wrote, iclass 20, count 0 2006.201.10:01:34.52#ibcon#about to read 3, iclass 20, count 0 2006.201.10:01:34.54#ibcon#read 3, iclass 20, count 0 2006.201.10:01:34.54#ibcon#about to read 4, iclass 20, count 0 2006.201.10:01:34.54#ibcon#read 4, iclass 20, count 0 2006.201.10:01:34.54#ibcon#about to read 5, iclass 20, count 0 2006.201.10:01:34.54#ibcon#read 5, iclass 20, count 0 2006.201.10:01:34.54#ibcon#about to read 6, iclass 20, count 0 2006.201.10:01:34.54#ibcon#read 6, iclass 20, count 0 2006.201.10:01:34.54#ibcon#end of sib2, iclass 20, count 0 2006.201.10:01:34.54#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:01:34.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:01:34.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:01:34.54#ibcon#*before write, iclass 20, count 0 2006.201.10:01:34.54#ibcon#enter sib2, iclass 20, count 0 2006.201.10:01:34.54#ibcon#flushed, iclass 20, count 0 2006.201.10:01:34.54#ibcon#about to write, iclass 20, count 0 2006.201.10:01:34.54#ibcon#wrote, iclass 20, count 0 2006.201.10:01:34.54#ibcon#about to read 3, iclass 20, count 0 2006.201.10:01:34.58#ibcon#read 3, iclass 20, count 0 2006.201.10:01:34.58#ibcon#about to read 4, iclass 20, count 0 2006.201.10:01:34.58#ibcon#read 4, iclass 20, count 0 2006.201.10:01:34.58#ibcon#about to read 5, iclass 20, count 0 2006.201.10:01:34.58#ibcon#read 5, iclass 20, count 0 2006.201.10:01:34.58#ibcon#about to read 6, iclass 20, count 0 2006.201.10:01:34.58#ibcon#read 6, iclass 20, count 0 2006.201.10:01:34.58#ibcon#end of sib2, iclass 20, count 0 2006.201.10:01:34.58#ibcon#*after write, iclass 20, count 0 2006.201.10:01:34.58#ibcon#*before return 0, iclass 20, count 0 2006.201.10:01:34.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:34.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:01:34.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:01:34.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:01:34.58$vck44/vb=4,5 2006.201.10:01:34.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.10:01:34.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.10:01:34.58#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:34.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:34.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:34.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:34.64#ibcon#enter wrdev, iclass 22, count 2 2006.201.10:01:34.64#ibcon#first serial, iclass 22, count 2 2006.201.10:01:34.64#ibcon#enter sib2, iclass 22, count 2 2006.201.10:01:34.64#ibcon#flushed, iclass 22, count 2 2006.201.10:01:34.64#ibcon#about to write, iclass 22, count 2 2006.201.10:01:34.64#ibcon#wrote, iclass 22, count 2 2006.201.10:01:34.64#ibcon#about to read 3, iclass 22, count 2 2006.201.10:01:34.66#ibcon#read 3, iclass 22, count 2 2006.201.10:01:34.66#ibcon#about to read 4, iclass 22, count 2 2006.201.10:01:34.66#ibcon#read 4, iclass 22, count 2 2006.201.10:01:34.66#ibcon#about to read 5, iclass 22, count 2 2006.201.10:01:34.66#ibcon#read 5, iclass 22, count 2 2006.201.10:01:34.66#ibcon#about to read 6, iclass 22, count 2 2006.201.10:01:34.66#ibcon#read 6, iclass 22, count 2 2006.201.10:01:34.66#ibcon#end of sib2, iclass 22, count 2 2006.201.10:01:34.66#ibcon#*mode == 0, iclass 22, count 2 2006.201.10:01:34.66#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.10:01:34.66#ibcon#[27=AT04-05\r\n] 2006.201.10:01:34.66#ibcon#*before write, iclass 22, count 2 2006.201.10:01:34.66#ibcon#enter sib2, iclass 22, count 2 2006.201.10:01:34.66#ibcon#flushed, iclass 22, count 2 2006.201.10:01:34.66#ibcon#about to write, iclass 22, count 2 2006.201.10:01:34.66#ibcon#wrote, iclass 22, count 2 2006.201.10:01:34.66#ibcon#about to read 3, iclass 22, count 2 2006.201.10:01:34.69#ibcon#read 3, iclass 22, count 2 2006.201.10:01:34.69#ibcon#about to read 4, iclass 22, count 2 2006.201.10:01:34.69#ibcon#read 4, iclass 22, count 2 2006.201.10:01:34.69#ibcon#about to read 5, iclass 22, count 2 2006.201.10:01:34.69#ibcon#read 5, iclass 22, count 2 2006.201.10:01:34.69#ibcon#about to read 6, iclass 22, count 2 2006.201.10:01:34.69#ibcon#read 6, iclass 22, count 2 2006.201.10:01:34.69#ibcon#end of sib2, iclass 22, count 2 2006.201.10:01:34.69#ibcon#*after write, iclass 22, count 2 2006.201.10:01:34.69#ibcon#*before return 0, iclass 22, count 2 2006.201.10:01:34.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:34.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:01:34.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.10:01:34.69#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:34.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:34.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:34.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:34.81#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:01:34.81#ibcon#first serial, iclass 22, count 0 2006.201.10:01:34.81#ibcon#enter sib2, iclass 22, count 0 2006.201.10:01:34.81#ibcon#flushed, iclass 22, count 0 2006.201.10:01:34.81#ibcon#about to write, iclass 22, count 0 2006.201.10:01:34.81#ibcon#wrote, iclass 22, count 0 2006.201.10:01:34.81#ibcon#about to read 3, iclass 22, count 0 2006.201.10:01:34.83#ibcon#read 3, iclass 22, count 0 2006.201.10:01:34.83#ibcon#about to read 4, iclass 22, count 0 2006.201.10:01:34.83#ibcon#read 4, iclass 22, count 0 2006.201.10:01:34.83#ibcon#about to read 5, iclass 22, count 0 2006.201.10:01:34.83#ibcon#read 5, iclass 22, count 0 2006.201.10:01:34.83#ibcon#about to read 6, iclass 22, count 0 2006.201.10:01:34.83#ibcon#read 6, iclass 22, count 0 2006.201.10:01:34.83#ibcon#end of sib2, iclass 22, count 0 2006.201.10:01:34.83#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:01:34.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:01:34.83#ibcon#[27=USB\r\n] 2006.201.10:01:34.83#ibcon#*before write, iclass 22, count 0 2006.201.10:01:34.83#ibcon#enter sib2, iclass 22, count 0 2006.201.10:01:34.83#ibcon#flushed, iclass 22, count 0 2006.201.10:01:34.83#ibcon#about to write, iclass 22, count 0 2006.201.10:01:34.83#ibcon#wrote, iclass 22, count 0 2006.201.10:01:34.83#ibcon#about to read 3, iclass 22, count 0 2006.201.10:01:34.86#ibcon#read 3, iclass 22, count 0 2006.201.10:01:34.86#ibcon#about to read 4, iclass 22, count 0 2006.201.10:01:34.86#ibcon#read 4, iclass 22, count 0 2006.201.10:01:34.86#ibcon#about to read 5, iclass 22, count 0 2006.201.10:01:34.86#ibcon#read 5, iclass 22, count 0 2006.201.10:01:34.86#ibcon#about to read 6, iclass 22, count 0 2006.201.10:01:34.86#ibcon#read 6, iclass 22, count 0 2006.201.10:01:34.86#ibcon#end of sib2, iclass 22, count 0 2006.201.10:01:34.86#ibcon#*after write, iclass 22, count 0 2006.201.10:01:34.86#ibcon#*before return 0, iclass 22, count 0 2006.201.10:01:34.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:34.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:01:34.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:01:34.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:01:34.86$vck44/vblo=5,709.99 2006.201.10:01:34.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.10:01:34.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.10:01:34.86#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:34.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:34.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:34.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:34.86#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:01:34.86#ibcon#first serial, iclass 24, count 0 2006.201.10:01:34.86#ibcon#enter sib2, iclass 24, count 0 2006.201.10:01:34.86#ibcon#flushed, iclass 24, count 0 2006.201.10:01:34.86#ibcon#about to write, iclass 24, count 0 2006.201.10:01:34.86#ibcon#wrote, iclass 24, count 0 2006.201.10:01:34.86#ibcon#about to read 3, iclass 24, count 0 2006.201.10:01:34.88#ibcon#read 3, iclass 24, count 0 2006.201.10:01:34.88#ibcon#about to read 4, iclass 24, count 0 2006.201.10:01:34.88#ibcon#read 4, iclass 24, count 0 2006.201.10:01:34.88#ibcon#about to read 5, iclass 24, count 0 2006.201.10:01:34.88#ibcon#read 5, iclass 24, count 0 2006.201.10:01:34.88#ibcon#about to read 6, iclass 24, count 0 2006.201.10:01:34.88#ibcon#read 6, iclass 24, count 0 2006.201.10:01:34.88#ibcon#end of sib2, iclass 24, count 0 2006.201.10:01:34.88#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:01:34.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:01:34.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:01:34.88#ibcon#*before write, iclass 24, count 0 2006.201.10:01:34.88#ibcon#enter sib2, iclass 24, count 0 2006.201.10:01:34.88#ibcon#flushed, iclass 24, count 0 2006.201.10:01:34.88#ibcon#about to write, iclass 24, count 0 2006.201.10:01:34.88#ibcon#wrote, iclass 24, count 0 2006.201.10:01:34.88#ibcon#about to read 3, iclass 24, count 0 2006.201.10:01:34.93#ibcon#read 3, iclass 24, count 0 2006.201.10:01:34.93#ibcon#about to read 4, iclass 24, count 0 2006.201.10:01:34.93#ibcon#read 4, iclass 24, count 0 2006.201.10:01:34.93#ibcon#about to read 5, iclass 24, count 0 2006.201.10:01:34.93#ibcon#read 5, iclass 24, count 0 2006.201.10:01:34.93#ibcon#about to read 6, iclass 24, count 0 2006.201.10:01:34.93#ibcon#read 6, iclass 24, count 0 2006.201.10:01:34.93#ibcon#end of sib2, iclass 24, count 0 2006.201.10:01:34.93#ibcon#*after write, iclass 24, count 0 2006.201.10:01:34.93#ibcon#*before return 0, iclass 24, count 0 2006.201.10:01:34.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:34.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:01:34.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:01:34.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:01:34.93$vck44/vb=5,4 2006.201.10:01:34.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.10:01:34.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.10:01:34.93#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:34.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:34.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:34.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:34.98#ibcon#enter wrdev, iclass 26, count 2 2006.201.10:01:34.98#ibcon#first serial, iclass 26, count 2 2006.201.10:01:34.98#ibcon#enter sib2, iclass 26, count 2 2006.201.10:01:34.98#ibcon#flushed, iclass 26, count 2 2006.201.10:01:34.98#ibcon#about to write, iclass 26, count 2 2006.201.10:01:34.98#ibcon#wrote, iclass 26, count 2 2006.201.10:01:34.98#ibcon#about to read 3, iclass 26, count 2 2006.201.10:01:35.00#ibcon#read 3, iclass 26, count 2 2006.201.10:01:35.00#ibcon#about to read 4, iclass 26, count 2 2006.201.10:01:35.00#ibcon#read 4, iclass 26, count 2 2006.201.10:01:35.00#ibcon#about to read 5, iclass 26, count 2 2006.201.10:01:35.00#ibcon#read 5, iclass 26, count 2 2006.201.10:01:35.00#ibcon#about to read 6, iclass 26, count 2 2006.201.10:01:35.00#ibcon#read 6, iclass 26, count 2 2006.201.10:01:35.00#ibcon#end of sib2, iclass 26, count 2 2006.201.10:01:35.00#ibcon#*mode == 0, iclass 26, count 2 2006.201.10:01:35.00#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.10:01:35.00#ibcon#[27=AT05-04\r\n] 2006.201.10:01:35.00#ibcon#*before write, iclass 26, count 2 2006.201.10:01:35.00#ibcon#enter sib2, iclass 26, count 2 2006.201.10:01:35.00#ibcon#flushed, iclass 26, count 2 2006.201.10:01:35.00#ibcon#about to write, iclass 26, count 2 2006.201.10:01:35.00#ibcon#wrote, iclass 26, count 2 2006.201.10:01:35.00#ibcon#about to read 3, iclass 26, count 2 2006.201.10:01:35.03#ibcon#read 3, iclass 26, count 2 2006.201.10:01:35.03#ibcon#about to read 4, iclass 26, count 2 2006.201.10:01:35.03#ibcon#read 4, iclass 26, count 2 2006.201.10:01:35.03#ibcon#about to read 5, iclass 26, count 2 2006.201.10:01:35.03#ibcon#read 5, iclass 26, count 2 2006.201.10:01:35.03#ibcon#about to read 6, iclass 26, count 2 2006.201.10:01:35.03#ibcon#read 6, iclass 26, count 2 2006.201.10:01:35.03#ibcon#end of sib2, iclass 26, count 2 2006.201.10:01:35.03#ibcon#*after write, iclass 26, count 2 2006.201.10:01:35.03#ibcon#*before return 0, iclass 26, count 2 2006.201.10:01:35.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:35.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:01:35.03#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.10:01:35.03#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:35.03#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:35.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:35.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:35.15#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:01:35.15#ibcon#first serial, iclass 26, count 0 2006.201.10:01:35.15#ibcon#enter sib2, iclass 26, count 0 2006.201.10:01:35.15#ibcon#flushed, iclass 26, count 0 2006.201.10:01:35.15#ibcon#about to write, iclass 26, count 0 2006.201.10:01:35.15#ibcon#wrote, iclass 26, count 0 2006.201.10:01:35.15#ibcon#about to read 3, iclass 26, count 0 2006.201.10:01:35.17#ibcon#read 3, iclass 26, count 0 2006.201.10:01:35.17#ibcon#about to read 4, iclass 26, count 0 2006.201.10:01:35.17#ibcon#read 4, iclass 26, count 0 2006.201.10:01:35.17#ibcon#about to read 5, iclass 26, count 0 2006.201.10:01:35.17#ibcon#read 5, iclass 26, count 0 2006.201.10:01:35.17#ibcon#about to read 6, iclass 26, count 0 2006.201.10:01:35.17#ibcon#read 6, iclass 26, count 0 2006.201.10:01:35.17#ibcon#end of sib2, iclass 26, count 0 2006.201.10:01:35.17#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:01:35.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:01:35.17#ibcon#[27=USB\r\n] 2006.201.10:01:35.17#ibcon#*before write, iclass 26, count 0 2006.201.10:01:35.17#ibcon#enter sib2, iclass 26, count 0 2006.201.10:01:35.17#ibcon#flushed, iclass 26, count 0 2006.201.10:01:35.17#ibcon#about to write, iclass 26, count 0 2006.201.10:01:35.17#ibcon#wrote, iclass 26, count 0 2006.201.10:01:35.17#ibcon#about to read 3, iclass 26, count 0 2006.201.10:01:35.20#ibcon#read 3, iclass 26, count 0 2006.201.10:01:35.20#ibcon#about to read 4, iclass 26, count 0 2006.201.10:01:35.20#ibcon#read 4, iclass 26, count 0 2006.201.10:01:35.20#ibcon#about to read 5, iclass 26, count 0 2006.201.10:01:35.20#ibcon#read 5, iclass 26, count 0 2006.201.10:01:35.20#ibcon#about to read 6, iclass 26, count 0 2006.201.10:01:35.20#ibcon#read 6, iclass 26, count 0 2006.201.10:01:35.20#ibcon#end of sib2, iclass 26, count 0 2006.201.10:01:35.20#ibcon#*after write, iclass 26, count 0 2006.201.10:01:35.20#ibcon#*before return 0, iclass 26, count 0 2006.201.10:01:35.20#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:35.20#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:01:35.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:01:35.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:01:35.20$vck44/vblo=6,719.99 2006.201.10:01:35.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.10:01:35.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.10:01:35.20#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:35.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:35.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:35.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:35.20#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:01:35.20#ibcon#first serial, iclass 28, count 0 2006.201.10:01:35.20#ibcon#enter sib2, iclass 28, count 0 2006.201.10:01:35.20#ibcon#flushed, iclass 28, count 0 2006.201.10:01:35.20#ibcon#about to write, iclass 28, count 0 2006.201.10:01:35.20#ibcon#wrote, iclass 28, count 0 2006.201.10:01:35.20#ibcon#about to read 3, iclass 28, count 0 2006.201.10:01:35.22#ibcon#read 3, iclass 28, count 0 2006.201.10:01:35.22#ibcon#about to read 4, iclass 28, count 0 2006.201.10:01:35.22#ibcon#read 4, iclass 28, count 0 2006.201.10:01:35.22#ibcon#about to read 5, iclass 28, count 0 2006.201.10:01:35.22#ibcon#read 5, iclass 28, count 0 2006.201.10:01:35.22#ibcon#about to read 6, iclass 28, count 0 2006.201.10:01:35.22#ibcon#read 6, iclass 28, count 0 2006.201.10:01:35.22#ibcon#end of sib2, iclass 28, count 0 2006.201.10:01:35.22#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:01:35.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:01:35.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:01:35.22#ibcon#*before write, iclass 28, count 0 2006.201.10:01:35.22#ibcon#enter sib2, iclass 28, count 0 2006.201.10:01:35.22#ibcon#flushed, iclass 28, count 0 2006.201.10:01:35.22#ibcon#about to write, iclass 28, count 0 2006.201.10:01:35.22#ibcon#wrote, iclass 28, count 0 2006.201.10:01:35.22#ibcon#about to read 3, iclass 28, count 0 2006.201.10:01:35.26#ibcon#read 3, iclass 28, count 0 2006.201.10:01:35.26#ibcon#about to read 4, iclass 28, count 0 2006.201.10:01:35.26#ibcon#read 4, iclass 28, count 0 2006.201.10:01:35.26#ibcon#about to read 5, iclass 28, count 0 2006.201.10:01:35.26#ibcon#read 5, iclass 28, count 0 2006.201.10:01:35.26#ibcon#about to read 6, iclass 28, count 0 2006.201.10:01:35.26#ibcon#read 6, iclass 28, count 0 2006.201.10:01:35.26#ibcon#end of sib2, iclass 28, count 0 2006.201.10:01:35.26#ibcon#*after write, iclass 28, count 0 2006.201.10:01:35.26#ibcon#*before return 0, iclass 28, count 0 2006.201.10:01:35.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:35.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:01:35.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:01:35.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:01:35.26$vck44/vb=6,4 2006.201.10:01:35.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.10:01:35.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.10:01:35.26#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:35.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:35.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:35.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:35.32#ibcon#enter wrdev, iclass 30, count 2 2006.201.10:01:35.32#ibcon#first serial, iclass 30, count 2 2006.201.10:01:35.32#ibcon#enter sib2, iclass 30, count 2 2006.201.10:01:35.32#ibcon#flushed, iclass 30, count 2 2006.201.10:01:35.32#ibcon#about to write, iclass 30, count 2 2006.201.10:01:35.32#ibcon#wrote, iclass 30, count 2 2006.201.10:01:35.32#ibcon#about to read 3, iclass 30, count 2 2006.201.10:01:35.34#ibcon#read 3, iclass 30, count 2 2006.201.10:01:35.34#ibcon#about to read 4, iclass 30, count 2 2006.201.10:01:35.34#ibcon#read 4, iclass 30, count 2 2006.201.10:01:35.34#ibcon#about to read 5, iclass 30, count 2 2006.201.10:01:35.34#ibcon#read 5, iclass 30, count 2 2006.201.10:01:35.34#ibcon#about to read 6, iclass 30, count 2 2006.201.10:01:35.34#ibcon#read 6, iclass 30, count 2 2006.201.10:01:35.34#ibcon#end of sib2, iclass 30, count 2 2006.201.10:01:35.34#ibcon#*mode == 0, iclass 30, count 2 2006.201.10:01:35.34#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.10:01:35.34#ibcon#[27=AT06-04\r\n] 2006.201.10:01:35.34#ibcon#*before write, iclass 30, count 2 2006.201.10:01:35.34#ibcon#enter sib2, iclass 30, count 2 2006.201.10:01:35.34#ibcon#flushed, iclass 30, count 2 2006.201.10:01:35.34#ibcon#about to write, iclass 30, count 2 2006.201.10:01:35.34#ibcon#wrote, iclass 30, count 2 2006.201.10:01:35.34#ibcon#about to read 3, iclass 30, count 2 2006.201.10:01:35.37#ibcon#read 3, iclass 30, count 2 2006.201.10:01:35.37#ibcon#about to read 4, iclass 30, count 2 2006.201.10:01:35.37#ibcon#read 4, iclass 30, count 2 2006.201.10:01:35.37#ibcon#about to read 5, iclass 30, count 2 2006.201.10:01:35.37#ibcon#read 5, iclass 30, count 2 2006.201.10:01:35.37#ibcon#about to read 6, iclass 30, count 2 2006.201.10:01:35.37#ibcon#read 6, iclass 30, count 2 2006.201.10:01:35.37#ibcon#end of sib2, iclass 30, count 2 2006.201.10:01:35.37#ibcon#*after write, iclass 30, count 2 2006.201.10:01:35.37#ibcon#*before return 0, iclass 30, count 2 2006.201.10:01:35.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:35.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:01:35.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.10:01:35.37#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:35.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:35.49#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:35.49#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:35.49#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:01:35.49#ibcon#first serial, iclass 30, count 0 2006.201.10:01:35.49#ibcon#enter sib2, iclass 30, count 0 2006.201.10:01:35.49#ibcon#flushed, iclass 30, count 0 2006.201.10:01:35.49#ibcon#about to write, iclass 30, count 0 2006.201.10:01:35.49#ibcon#wrote, iclass 30, count 0 2006.201.10:01:35.49#ibcon#about to read 3, iclass 30, count 0 2006.201.10:01:35.51#ibcon#read 3, iclass 30, count 0 2006.201.10:01:35.51#ibcon#about to read 4, iclass 30, count 0 2006.201.10:01:35.51#ibcon#read 4, iclass 30, count 0 2006.201.10:01:35.51#ibcon#about to read 5, iclass 30, count 0 2006.201.10:01:35.51#ibcon#read 5, iclass 30, count 0 2006.201.10:01:35.51#ibcon#about to read 6, iclass 30, count 0 2006.201.10:01:35.51#ibcon#read 6, iclass 30, count 0 2006.201.10:01:35.51#ibcon#end of sib2, iclass 30, count 0 2006.201.10:01:35.51#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:01:35.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:01:35.51#ibcon#[27=USB\r\n] 2006.201.10:01:35.51#ibcon#*before write, iclass 30, count 0 2006.201.10:01:35.51#ibcon#enter sib2, iclass 30, count 0 2006.201.10:01:35.51#ibcon#flushed, iclass 30, count 0 2006.201.10:01:35.51#ibcon#about to write, iclass 30, count 0 2006.201.10:01:35.51#ibcon#wrote, iclass 30, count 0 2006.201.10:01:35.51#ibcon#about to read 3, iclass 30, count 0 2006.201.10:01:35.54#ibcon#read 3, iclass 30, count 0 2006.201.10:01:35.54#ibcon#about to read 4, iclass 30, count 0 2006.201.10:01:35.54#ibcon#read 4, iclass 30, count 0 2006.201.10:01:35.54#ibcon#about to read 5, iclass 30, count 0 2006.201.10:01:35.54#ibcon#read 5, iclass 30, count 0 2006.201.10:01:35.54#ibcon#about to read 6, iclass 30, count 0 2006.201.10:01:35.54#ibcon#read 6, iclass 30, count 0 2006.201.10:01:35.54#ibcon#end of sib2, iclass 30, count 0 2006.201.10:01:35.54#ibcon#*after write, iclass 30, count 0 2006.201.10:01:35.54#ibcon#*before return 0, iclass 30, count 0 2006.201.10:01:35.54#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:35.54#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:01:35.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:01:35.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:01:35.54$vck44/vblo=7,734.99 2006.201.10:01:35.54#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.10:01:35.54#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.10:01:35.54#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:35.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:35.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:35.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:35.54#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:01:35.54#ibcon#first serial, iclass 32, count 0 2006.201.10:01:35.54#ibcon#enter sib2, iclass 32, count 0 2006.201.10:01:35.54#ibcon#flushed, iclass 32, count 0 2006.201.10:01:35.54#ibcon#about to write, iclass 32, count 0 2006.201.10:01:35.54#ibcon#wrote, iclass 32, count 0 2006.201.10:01:35.54#ibcon#about to read 3, iclass 32, count 0 2006.201.10:01:35.56#ibcon#read 3, iclass 32, count 0 2006.201.10:01:35.56#ibcon#about to read 4, iclass 32, count 0 2006.201.10:01:35.56#ibcon#read 4, iclass 32, count 0 2006.201.10:01:35.56#ibcon#about to read 5, iclass 32, count 0 2006.201.10:01:35.56#ibcon#read 5, iclass 32, count 0 2006.201.10:01:35.56#ibcon#about to read 6, iclass 32, count 0 2006.201.10:01:35.56#ibcon#read 6, iclass 32, count 0 2006.201.10:01:35.56#ibcon#end of sib2, iclass 32, count 0 2006.201.10:01:35.56#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:01:35.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:01:35.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:01:35.56#ibcon#*before write, iclass 32, count 0 2006.201.10:01:35.56#ibcon#enter sib2, iclass 32, count 0 2006.201.10:01:35.56#ibcon#flushed, iclass 32, count 0 2006.201.10:01:35.56#ibcon#about to write, iclass 32, count 0 2006.201.10:01:35.56#ibcon#wrote, iclass 32, count 0 2006.201.10:01:35.56#ibcon#about to read 3, iclass 32, count 0 2006.201.10:01:35.60#ibcon#read 3, iclass 32, count 0 2006.201.10:01:35.60#ibcon#about to read 4, iclass 32, count 0 2006.201.10:01:35.60#ibcon#read 4, iclass 32, count 0 2006.201.10:01:35.60#ibcon#about to read 5, iclass 32, count 0 2006.201.10:01:35.60#ibcon#read 5, iclass 32, count 0 2006.201.10:01:35.60#ibcon#about to read 6, iclass 32, count 0 2006.201.10:01:35.60#ibcon#read 6, iclass 32, count 0 2006.201.10:01:35.60#ibcon#end of sib2, iclass 32, count 0 2006.201.10:01:35.60#ibcon#*after write, iclass 32, count 0 2006.201.10:01:35.60#ibcon#*before return 0, iclass 32, count 0 2006.201.10:01:35.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:35.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:01:35.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:01:35.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:01:35.60$vck44/vb=7,4 2006.201.10:01:35.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.10:01:35.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.10:01:35.60#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:35.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:35.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:35.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:35.66#ibcon#enter wrdev, iclass 34, count 2 2006.201.10:01:35.66#ibcon#first serial, iclass 34, count 2 2006.201.10:01:35.66#ibcon#enter sib2, iclass 34, count 2 2006.201.10:01:35.66#ibcon#flushed, iclass 34, count 2 2006.201.10:01:35.66#ibcon#about to write, iclass 34, count 2 2006.201.10:01:35.66#ibcon#wrote, iclass 34, count 2 2006.201.10:01:35.66#ibcon#about to read 3, iclass 34, count 2 2006.201.10:01:35.68#ibcon#read 3, iclass 34, count 2 2006.201.10:01:35.68#ibcon#about to read 4, iclass 34, count 2 2006.201.10:01:35.68#ibcon#read 4, iclass 34, count 2 2006.201.10:01:35.68#ibcon#about to read 5, iclass 34, count 2 2006.201.10:01:35.68#ibcon#read 5, iclass 34, count 2 2006.201.10:01:35.68#ibcon#about to read 6, iclass 34, count 2 2006.201.10:01:35.68#ibcon#read 6, iclass 34, count 2 2006.201.10:01:35.68#ibcon#end of sib2, iclass 34, count 2 2006.201.10:01:35.68#ibcon#*mode == 0, iclass 34, count 2 2006.201.10:01:35.68#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.10:01:35.68#ibcon#[27=AT07-04\r\n] 2006.201.10:01:35.68#ibcon#*before write, iclass 34, count 2 2006.201.10:01:35.68#ibcon#enter sib2, iclass 34, count 2 2006.201.10:01:35.68#ibcon#flushed, iclass 34, count 2 2006.201.10:01:35.68#ibcon#about to write, iclass 34, count 2 2006.201.10:01:35.68#ibcon#wrote, iclass 34, count 2 2006.201.10:01:35.68#ibcon#about to read 3, iclass 34, count 2 2006.201.10:01:35.71#ibcon#read 3, iclass 34, count 2 2006.201.10:01:35.71#ibcon#about to read 4, iclass 34, count 2 2006.201.10:01:35.71#ibcon#read 4, iclass 34, count 2 2006.201.10:01:35.71#ibcon#about to read 5, iclass 34, count 2 2006.201.10:01:35.71#ibcon#read 5, iclass 34, count 2 2006.201.10:01:35.71#ibcon#about to read 6, iclass 34, count 2 2006.201.10:01:35.71#ibcon#read 6, iclass 34, count 2 2006.201.10:01:35.71#ibcon#end of sib2, iclass 34, count 2 2006.201.10:01:35.71#ibcon#*after write, iclass 34, count 2 2006.201.10:01:35.71#ibcon#*before return 0, iclass 34, count 2 2006.201.10:01:35.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:35.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:01:35.71#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.10:01:35.71#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:35.71#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:35.83#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:35.83#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:35.83#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:01:35.83#ibcon#first serial, iclass 34, count 0 2006.201.10:01:35.83#ibcon#enter sib2, iclass 34, count 0 2006.201.10:01:35.83#ibcon#flushed, iclass 34, count 0 2006.201.10:01:35.83#ibcon#about to write, iclass 34, count 0 2006.201.10:01:35.83#ibcon#wrote, iclass 34, count 0 2006.201.10:01:35.83#ibcon#about to read 3, iclass 34, count 0 2006.201.10:01:35.85#ibcon#read 3, iclass 34, count 0 2006.201.10:01:35.85#ibcon#about to read 4, iclass 34, count 0 2006.201.10:01:35.85#ibcon#read 4, iclass 34, count 0 2006.201.10:01:35.85#ibcon#about to read 5, iclass 34, count 0 2006.201.10:01:35.85#ibcon#read 5, iclass 34, count 0 2006.201.10:01:35.85#ibcon#about to read 6, iclass 34, count 0 2006.201.10:01:35.85#ibcon#read 6, iclass 34, count 0 2006.201.10:01:35.85#ibcon#end of sib2, iclass 34, count 0 2006.201.10:01:35.85#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:01:35.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:01:35.85#ibcon#[27=USB\r\n] 2006.201.10:01:35.85#ibcon#*before write, iclass 34, count 0 2006.201.10:01:35.85#ibcon#enter sib2, iclass 34, count 0 2006.201.10:01:35.85#ibcon#flushed, iclass 34, count 0 2006.201.10:01:35.85#ibcon#about to write, iclass 34, count 0 2006.201.10:01:35.85#ibcon#wrote, iclass 34, count 0 2006.201.10:01:35.85#ibcon#about to read 3, iclass 34, count 0 2006.201.10:01:35.88#ibcon#read 3, iclass 34, count 0 2006.201.10:01:35.88#ibcon#about to read 4, iclass 34, count 0 2006.201.10:01:35.88#ibcon#read 4, iclass 34, count 0 2006.201.10:01:35.88#ibcon#about to read 5, iclass 34, count 0 2006.201.10:01:35.88#ibcon#read 5, iclass 34, count 0 2006.201.10:01:35.88#ibcon#about to read 6, iclass 34, count 0 2006.201.10:01:35.88#ibcon#read 6, iclass 34, count 0 2006.201.10:01:35.88#ibcon#end of sib2, iclass 34, count 0 2006.201.10:01:35.88#ibcon#*after write, iclass 34, count 0 2006.201.10:01:35.88#ibcon#*before return 0, iclass 34, count 0 2006.201.10:01:35.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:35.88#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:01:35.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:01:35.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:01:35.88$vck44/vblo=8,744.99 2006.201.10:01:35.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.10:01:35.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.10:01:35.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:01:35.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:35.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:35.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:35.88#ibcon#enter wrdev, iclass 36, count 0 2006.201.10:01:35.88#ibcon#first serial, iclass 36, count 0 2006.201.10:01:35.88#ibcon#enter sib2, iclass 36, count 0 2006.201.10:01:35.88#ibcon#flushed, iclass 36, count 0 2006.201.10:01:35.88#ibcon#about to write, iclass 36, count 0 2006.201.10:01:35.88#ibcon#wrote, iclass 36, count 0 2006.201.10:01:35.88#ibcon#about to read 3, iclass 36, count 0 2006.201.10:01:35.90#ibcon#read 3, iclass 36, count 0 2006.201.10:01:35.90#ibcon#about to read 4, iclass 36, count 0 2006.201.10:01:35.90#ibcon#read 4, iclass 36, count 0 2006.201.10:01:35.90#ibcon#about to read 5, iclass 36, count 0 2006.201.10:01:35.90#ibcon#read 5, iclass 36, count 0 2006.201.10:01:35.90#ibcon#about to read 6, iclass 36, count 0 2006.201.10:01:35.90#ibcon#read 6, iclass 36, count 0 2006.201.10:01:35.90#ibcon#end of sib2, iclass 36, count 0 2006.201.10:01:35.90#ibcon#*mode == 0, iclass 36, count 0 2006.201.10:01:35.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.10:01:35.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:01:35.90#ibcon#*before write, iclass 36, count 0 2006.201.10:01:35.90#ibcon#enter sib2, iclass 36, count 0 2006.201.10:01:35.90#ibcon#flushed, iclass 36, count 0 2006.201.10:01:35.90#ibcon#about to write, iclass 36, count 0 2006.201.10:01:35.90#ibcon#wrote, iclass 36, count 0 2006.201.10:01:35.90#ibcon#about to read 3, iclass 36, count 0 2006.201.10:01:35.95#ibcon#read 3, iclass 36, count 0 2006.201.10:01:35.95#ibcon#about to read 4, iclass 36, count 0 2006.201.10:01:35.95#ibcon#read 4, iclass 36, count 0 2006.201.10:01:35.95#ibcon#about to read 5, iclass 36, count 0 2006.201.10:01:35.95#ibcon#read 5, iclass 36, count 0 2006.201.10:01:35.95#ibcon#about to read 6, iclass 36, count 0 2006.201.10:01:35.95#ibcon#read 6, iclass 36, count 0 2006.201.10:01:35.95#ibcon#end of sib2, iclass 36, count 0 2006.201.10:01:35.95#ibcon#*after write, iclass 36, count 0 2006.201.10:01:35.95#ibcon#*before return 0, iclass 36, count 0 2006.201.10:01:35.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:35.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:01:35.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.10:01:35.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.10:01:35.95$vck44/vb=8,4 2006.201.10:01:35.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.10:01:35.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.10:01:35.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:01:35.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:36.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:36.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:36.00#ibcon#enter wrdev, iclass 38, count 2 2006.201.10:01:36.00#ibcon#first serial, iclass 38, count 2 2006.201.10:01:36.00#ibcon#enter sib2, iclass 38, count 2 2006.201.10:01:36.00#ibcon#flushed, iclass 38, count 2 2006.201.10:01:36.00#ibcon#about to write, iclass 38, count 2 2006.201.10:01:36.00#ibcon#wrote, iclass 38, count 2 2006.201.10:01:36.00#ibcon#about to read 3, iclass 38, count 2 2006.201.10:01:36.02#ibcon#read 3, iclass 38, count 2 2006.201.10:01:36.02#ibcon#about to read 4, iclass 38, count 2 2006.201.10:01:36.02#ibcon#read 4, iclass 38, count 2 2006.201.10:01:36.02#ibcon#about to read 5, iclass 38, count 2 2006.201.10:01:36.02#ibcon#read 5, iclass 38, count 2 2006.201.10:01:36.02#ibcon#about to read 6, iclass 38, count 2 2006.201.10:01:36.02#ibcon#read 6, iclass 38, count 2 2006.201.10:01:36.02#ibcon#end of sib2, iclass 38, count 2 2006.201.10:01:36.02#ibcon#*mode == 0, iclass 38, count 2 2006.201.10:01:36.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.10:01:36.02#ibcon#[27=AT08-04\r\n] 2006.201.10:01:36.02#ibcon#*before write, iclass 38, count 2 2006.201.10:01:36.02#ibcon#enter sib2, iclass 38, count 2 2006.201.10:01:36.02#ibcon#flushed, iclass 38, count 2 2006.201.10:01:36.02#ibcon#about to write, iclass 38, count 2 2006.201.10:01:36.02#ibcon#wrote, iclass 38, count 2 2006.201.10:01:36.02#ibcon#about to read 3, iclass 38, count 2 2006.201.10:01:36.05#ibcon#read 3, iclass 38, count 2 2006.201.10:01:36.05#ibcon#about to read 4, iclass 38, count 2 2006.201.10:01:36.05#ibcon#read 4, iclass 38, count 2 2006.201.10:01:36.05#ibcon#about to read 5, iclass 38, count 2 2006.201.10:01:36.05#ibcon#read 5, iclass 38, count 2 2006.201.10:01:36.05#ibcon#about to read 6, iclass 38, count 2 2006.201.10:01:36.05#ibcon#read 6, iclass 38, count 2 2006.201.10:01:36.05#ibcon#end of sib2, iclass 38, count 2 2006.201.10:01:36.05#ibcon#*after write, iclass 38, count 2 2006.201.10:01:36.05#ibcon#*before return 0, iclass 38, count 2 2006.201.10:01:36.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:36.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:01:36.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.10:01:36.05#ibcon#ireg 7 cls_cnt 0 2006.201.10:01:36.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:36.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:36.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:36.17#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:01:36.17#ibcon#first serial, iclass 38, count 0 2006.201.10:01:36.17#ibcon#enter sib2, iclass 38, count 0 2006.201.10:01:36.17#ibcon#flushed, iclass 38, count 0 2006.201.10:01:36.17#ibcon#about to write, iclass 38, count 0 2006.201.10:01:36.17#ibcon#wrote, iclass 38, count 0 2006.201.10:01:36.17#ibcon#about to read 3, iclass 38, count 0 2006.201.10:01:36.19#ibcon#read 3, iclass 38, count 0 2006.201.10:01:36.19#ibcon#about to read 4, iclass 38, count 0 2006.201.10:01:36.19#ibcon#read 4, iclass 38, count 0 2006.201.10:01:36.19#ibcon#about to read 5, iclass 38, count 0 2006.201.10:01:36.19#ibcon#read 5, iclass 38, count 0 2006.201.10:01:36.19#ibcon#about to read 6, iclass 38, count 0 2006.201.10:01:36.19#ibcon#read 6, iclass 38, count 0 2006.201.10:01:36.19#ibcon#end of sib2, iclass 38, count 0 2006.201.10:01:36.19#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:01:36.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:01:36.19#ibcon#[27=USB\r\n] 2006.201.10:01:36.19#ibcon#*before write, iclass 38, count 0 2006.201.10:01:36.19#ibcon#enter sib2, iclass 38, count 0 2006.201.10:01:36.19#ibcon#flushed, iclass 38, count 0 2006.201.10:01:36.19#ibcon#about to write, iclass 38, count 0 2006.201.10:01:36.19#ibcon#wrote, iclass 38, count 0 2006.201.10:01:36.19#ibcon#about to read 3, iclass 38, count 0 2006.201.10:01:36.22#ibcon#read 3, iclass 38, count 0 2006.201.10:01:36.22#ibcon#about to read 4, iclass 38, count 0 2006.201.10:01:36.22#ibcon#read 4, iclass 38, count 0 2006.201.10:01:36.22#ibcon#about to read 5, iclass 38, count 0 2006.201.10:01:36.22#ibcon#read 5, iclass 38, count 0 2006.201.10:01:36.22#ibcon#about to read 6, iclass 38, count 0 2006.201.10:01:36.22#ibcon#read 6, iclass 38, count 0 2006.201.10:01:36.22#ibcon#end of sib2, iclass 38, count 0 2006.201.10:01:36.22#ibcon#*after write, iclass 38, count 0 2006.201.10:01:36.22#ibcon#*before return 0, iclass 38, count 0 2006.201.10:01:36.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:36.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:01:36.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:01:36.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:01:36.22$vck44/vabw=wide 2006.201.10:01:36.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.10:01:36.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.10:01:36.22#ibcon#ireg 8 cls_cnt 0 2006.201.10:01:36.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:36.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:36.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:36.22#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:01:36.22#ibcon#first serial, iclass 40, count 0 2006.201.10:01:36.22#ibcon#enter sib2, iclass 40, count 0 2006.201.10:01:36.22#ibcon#flushed, iclass 40, count 0 2006.201.10:01:36.22#ibcon#about to write, iclass 40, count 0 2006.201.10:01:36.22#ibcon#wrote, iclass 40, count 0 2006.201.10:01:36.22#ibcon#about to read 3, iclass 40, count 0 2006.201.10:01:36.24#ibcon#read 3, iclass 40, count 0 2006.201.10:01:36.24#ibcon#about to read 4, iclass 40, count 0 2006.201.10:01:36.24#ibcon#read 4, iclass 40, count 0 2006.201.10:01:36.24#ibcon#about to read 5, iclass 40, count 0 2006.201.10:01:36.24#ibcon#read 5, iclass 40, count 0 2006.201.10:01:36.24#ibcon#about to read 6, iclass 40, count 0 2006.201.10:01:36.24#ibcon#read 6, iclass 40, count 0 2006.201.10:01:36.24#ibcon#end of sib2, iclass 40, count 0 2006.201.10:01:36.24#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:01:36.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:01:36.24#ibcon#[25=BW32\r\n] 2006.201.10:01:36.24#ibcon#*before write, iclass 40, count 0 2006.201.10:01:36.24#ibcon#enter sib2, iclass 40, count 0 2006.201.10:01:36.24#ibcon#flushed, iclass 40, count 0 2006.201.10:01:36.24#ibcon#about to write, iclass 40, count 0 2006.201.10:01:36.24#ibcon#wrote, iclass 40, count 0 2006.201.10:01:36.24#ibcon#about to read 3, iclass 40, count 0 2006.201.10:01:36.27#ibcon#read 3, iclass 40, count 0 2006.201.10:01:36.27#ibcon#about to read 4, iclass 40, count 0 2006.201.10:01:36.27#ibcon#read 4, iclass 40, count 0 2006.201.10:01:36.27#ibcon#about to read 5, iclass 40, count 0 2006.201.10:01:36.27#ibcon#read 5, iclass 40, count 0 2006.201.10:01:36.27#ibcon#about to read 6, iclass 40, count 0 2006.201.10:01:36.27#ibcon#read 6, iclass 40, count 0 2006.201.10:01:36.27#ibcon#end of sib2, iclass 40, count 0 2006.201.10:01:36.27#ibcon#*after write, iclass 40, count 0 2006.201.10:01:36.27#ibcon#*before return 0, iclass 40, count 0 2006.201.10:01:36.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:36.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:01:36.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:01:36.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:01:36.27$vck44/vbbw=wide 2006.201.10:01:36.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.10:01:36.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.10:01:36.27#ibcon#ireg 8 cls_cnt 0 2006.201.10:01:36.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:01:36.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:01:36.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:01:36.34#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:01:36.34#ibcon#first serial, iclass 4, count 0 2006.201.10:01:36.34#ibcon#enter sib2, iclass 4, count 0 2006.201.10:01:36.34#ibcon#flushed, iclass 4, count 0 2006.201.10:01:36.34#ibcon#about to write, iclass 4, count 0 2006.201.10:01:36.34#ibcon#wrote, iclass 4, count 0 2006.201.10:01:36.34#ibcon#about to read 3, iclass 4, count 0 2006.201.10:01:36.36#ibcon#read 3, iclass 4, count 0 2006.201.10:01:36.36#ibcon#about to read 4, iclass 4, count 0 2006.201.10:01:36.36#ibcon#read 4, iclass 4, count 0 2006.201.10:01:36.36#ibcon#about to read 5, iclass 4, count 0 2006.201.10:01:36.36#ibcon#read 5, iclass 4, count 0 2006.201.10:01:36.36#ibcon#about to read 6, iclass 4, count 0 2006.201.10:01:36.36#ibcon#read 6, iclass 4, count 0 2006.201.10:01:36.36#ibcon#end of sib2, iclass 4, count 0 2006.201.10:01:36.36#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:01:36.36#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:01:36.36#ibcon#[27=BW32\r\n] 2006.201.10:01:36.36#ibcon#*before write, iclass 4, count 0 2006.201.10:01:36.36#ibcon#enter sib2, iclass 4, count 0 2006.201.10:01:36.36#ibcon#flushed, iclass 4, count 0 2006.201.10:01:36.36#ibcon#about to write, iclass 4, count 0 2006.201.10:01:36.36#ibcon#wrote, iclass 4, count 0 2006.201.10:01:36.36#ibcon#about to read 3, iclass 4, count 0 2006.201.10:01:36.39#ibcon#read 3, iclass 4, count 0 2006.201.10:01:36.39#ibcon#about to read 4, iclass 4, count 0 2006.201.10:01:36.39#ibcon#read 4, iclass 4, count 0 2006.201.10:01:36.39#ibcon#about to read 5, iclass 4, count 0 2006.201.10:01:36.39#ibcon#read 5, iclass 4, count 0 2006.201.10:01:36.39#ibcon#about to read 6, iclass 4, count 0 2006.201.10:01:36.39#ibcon#read 6, iclass 4, count 0 2006.201.10:01:36.39#ibcon#end of sib2, iclass 4, count 0 2006.201.10:01:36.39#ibcon#*after write, iclass 4, count 0 2006.201.10:01:36.39#ibcon#*before return 0, iclass 4, count 0 2006.201.10:01:36.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:01:36.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:01:36.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:01:36.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:01:36.39$setupk4/ifdk4 2006.201.10:01:36.39$ifdk4/lo= 2006.201.10:01:36.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:01:36.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:01:36.39$ifdk4/patch= 2006.201.10:01:36.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:01:36.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:01:36.39$setupk4/!*+20s 2006.201.10:01:39.31#abcon#<5=/05 2.6 5.1 22.18 951003.6\r\n> 2006.201.10:01:39.33#abcon#{5=INTERFACE CLEAR} 2006.201.10:01:39.39#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:01:49.48#abcon#<5=/05 2.6 5.1 22.17 951003.6\r\n> 2006.201.10:01:49.50#abcon#{5=INTERFACE CLEAR} 2006.201.10:01:49.56#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:01:50.89$setupk4/"tpicd 2006.201.10:01:50.89$setupk4/echo=off 2006.201.10:01:50.89$setupk4/xlog=off 2006.201.10:01:50.89:!2006.201.10:03:02 2006.201.10:01:53.14#trakl#Source acquired 2006.201.10:01:53.14#flagr#flagr/antenna,acquired 2006.201.10:03:02.00:preob 2006.201.10:03:03.14/onsource/TRACKING 2006.201.10:03:03.14:!2006.201.10:03:12 2006.201.10:03:12.00:"tape 2006.201.10:03:12.00:"st=record 2006.201.10:03:12.00:data_valid=on 2006.201.10:03:12.00:midob 2006.201.10:03:12.14/onsource/TRACKING 2006.201.10:03:12.14/wx/22.15,1003.5,95 2006.201.10:03:12.23/cable/+6.4669E-03 2006.201.10:03:13.32/va/01,08,usb,yes,27,29 2006.201.10:03:13.32/va/02,07,usb,yes,30,30 2006.201.10:03:13.32/va/03,08,usb,yes,27,28 2006.201.10:03:13.32/va/04,07,usb,yes,30,32 2006.201.10:03:13.32/va/05,04,usb,yes,27,27 2006.201.10:03:13.32/va/06,05,usb,yes,27,27 2006.201.10:03:13.32/va/07,05,usb,yes,26,27 2006.201.10:03:13.32/va/08,04,usb,yes,26,31 2006.201.10:03:13.55/valo/01,524.99,yes,locked 2006.201.10:03:13.55/valo/02,534.99,yes,locked 2006.201.10:03:13.55/valo/03,564.99,yes,locked 2006.201.10:03:13.55/valo/04,624.99,yes,locked 2006.201.10:03:13.55/valo/05,734.99,yes,locked 2006.201.10:03:13.55/valo/06,814.99,yes,locked 2006.201.10:03:13.55/valo/07,864.99,yes,locked 2006.201.10:03:13.55/valo/08,884.99,yes,locked 2006.201.10:03:14.64/vb/01,04,usb,yes,28,26 2006.201.10:03:14.64/vb/02,05,usb,yes,27,27 2006.201.10:03:14.64/vb/03,04,usb,yes,28,30 2006.201.10:03:14.64/vb/04,05,usb,yes,28,27 2006.201.10:03:14.64/vb/05,04,usb,yes,24,27 2006.201.10:03:14.64/vb/06,04,usb,yes,29,25 2006.201.10:03:14.64/vb/07,04,usb,yes,28,28 2006.201.10:03:14.64/vb/08,04,usb,yes,26,29 2006.201.10:03:14.88/vblo/01,629.99,yes,locked 2006.201.10:03:14.88/vblo/02,634.99,yes,locked 2006.201.10:03:14.88/vblo/03,649.99,yes,locked 2006.201.10:03:14.88/vblo/04,679.99,yes,locked 2006.201.10:03:14.88/vblo/05,709.99,yes,locked 2006.201.10:03:14.88/vblo/06,719.99,yes,locked 2006.201.10:03:14.88/vblo/07,734.99,yes,locked 2006.201.10:03:14.88/vblo/08,744.99,yes,locked 2006.201.10:03:15.03/vabw/8 2006.201.10:03:15.18/vbbw/8 2006.201.10:03:15.32/xfe/off,on,15.2 2006.201.10:03:15.71/ifatt/23,28,28,28 2006.201.10:03:16.05/fmout-gps/S +4.58E-07 2006.201.10:03:16.12:!2006.201.10:09:12 2006.201.10:09:12.00:data_valid=off 2006.201.10:09:12.00:"et 2006.201.10:09:12.00:!+3s 2006.201.10:09:15.02:"tape 2006.201.10:09:15.02:postob 2006.201.10:09:15.09/cable/+6.4687E-03 2006.201.10:09:15.09/wx/22.04,1003.6,95 2006.201.10:09:15.17/fmout-gps/S +4.62E-07 2006.201.10:09:15.17:scan_name=201-1014,jd0607,90 2006.201.10:09:15.18:source=3c274,123049.42,122328.0,2000.0,cw 2006.201.10:09:16.14#flagr#flagr/antenna,new-source 2006.201.10:09:16.14:checkk5 2006.201.10:09:16.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:09:16.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:09:17.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:09:17.70/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:09:18.06/chk_obsdata//k5ts1/T2011003??a.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.201.10:09:18.43/chk_obsdata//k5ts2/T2011003??b.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.201.10:09:18.79/chk_obsdata//k5ts3/T2011003??c.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.201.10:09:19.16/chk_obsdata//k5ts4/T2011003??d.dat file size is correct (nominal:1440MB, actual:1436MB). 2006.201.10:09:19.85/k5log//k5ts1_log_newline 2006.201.10:09:20.53/k5log//k5ts2_log_newline 2006.201.10:09:21.22/k5log//k5ts3_log_newline 2006.201.10:09:21.91/k5log//k5ts4_log_newline 2006.201.10:09:21.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:09:21.93:setupk4=1 2006.201.10:09:21.93$setupk4/echo=on 2006.201.10:09:21.93$setupk4/pcalon 2006.201.10:09:21.93$pcalon/"no phase cal control is implemented here 2006.201.10:09:21.93$setupk4/"tpicd=stop 2006.201.10:09:21.93$setupk4/"rec=synch_on 2006.201.10:09:21.93$setupk4/"rec_mode=128 2006.201.10:09:21.93$setupk4/!* 2006.201.10:09:21.93$setupk4/recpk4 2006.201.10:09:21.93$recpk4/recpatch= 2006.201.10:09:21.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:09:21.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:09:21.94$setupk4/vck44 2006.201.10:09:21.94$vck44/valo=1,524.99 2006.201.10:09:21.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.10:09:21.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.10:09:21.94#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:21.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:21.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:21.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:21.94#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:09:21.94#ibcon#first serial, iclass 15, count 0 2006.201.10:09:21.94#ibcon#enter sib2, iclass 15, count 0 2006.201.10:09:21.94#ibcon#flushed, iclass 15, count 0 2006.201.10:09:21.94#ibcon#about to write, iclass 15, count 0 2006.201.10:09:21.94#ibcon#wrote, iclass 15, count 0 2006.201.10:09:21.94#ibcon#about to read 3, iclass 15, count 0 2006.201.10:09:21.97#ibcon#read 3, iclass 15, count 0 2006.201.10:09:21.97#ibcon#about to read 4, iclass 15, count 0 2006.201.10:09:21.97#ibcon#read 4, iclass 15, count 0 2006.201.10:09:21.97#ibcon#about to read 5, iclass 15, count 0 2006.201.10:09:21.97#ibcon#read 5, iclass 15, count 0 2006.201.10:09:21.97#ibcon#about to read 6, iclass 15, count 0 2006.201.10:09:21.97#ibcon#read 6, iclass 15, count 0 2006.201.10:09:21.97#ibcon#end of sib2, iclass 15, count 0 2006.201.10:09:21.97#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:09:21.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:09:21.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:09:21.97#ibcon#*before write, iclass 15, count 0 2006.201.10:09:21.97#ibcon#enter sib2, iclass 15, count 0 2006.201.10:09:21.97#ibcon#flushed, iclass 15, count 0 2006.201.10:09:21.97#ibcon#about to write, iclass 15, count 0 2006.201.10:09:21.97#ibcon#wrote, iclass 15, count 0 2006.201.10:09:21.97#ibcon#about to read 3, iclass 15, count 0 2006.201.10:09:22.02#ibcon#read 3, iclass 15, count 0 2006.201.10:09:22.02#ibcon#about to read 4, iclass 15, count 0 2006.201.10:09:22.02#ibcon#read 4, iclass 15, count 0 2006.201.10:09:22.02#ibcon#about to read 5, iclass 15, count 0 2006.201.10:09:22.02#ibcon#read 5, iclass 15, count 0 2006.201.10:09:22.02#ibcon#about to read 6, iclass 15, count 0 2006.201.10:09:22.02#ibcon#read 6, iclass 15, count 0 2006.201.10:09:22.02#ibcon#end of sib2, iclass 15, count 0 2006.201.10:09:22.02#ibcon#*after write, iclass 15, count 0 2006.201.10:09:22.02#ibcon#*before return 0, iclass 15, count 0 2006.201.10:09:22.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:22.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:22.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:09:22.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:09:22.02$vck44/va=1,8 2006.201.10:09:22.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.10:09:22.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.10:09:22.02#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:22.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:22.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:22.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:22.02#ibcon#enter wrdev, iclass 17, count 2 2006.201.10:09:22.02#ibcon#first serial, iclass 17, count 2 2006.201.10:09:22.02#ibcon#enter sib2, iclass 17, count 2 2006.201.10:09:22.02#ibcon#flushed, iclass 17, count 2 2006.201.10:09:22.02#ibcon#about to write, iclass 17, count 2 2006.201.10:09:22.02#ibcon#wrote, iclass 17, count 2 2006.201.10:09:22.02#ibcon#about to read 3, iclass 17, count 2 2006.201.10:09:22.04#ibcon#read 3, iclass 17, count 2 2006.201.10:09:22.04#ibcon#about to read 4, iclass 17, count 2 2006.201.10:09:22.04#ibcon#read 4, iclass 17, count 2 2006.201.10:09:22.04#ibcon#about to read 5, iclass 17, count 2 2006.201.10:09:22.04#ibcon#read 5, iclass 17, count 2 2006.201.10:09:22.04#ibcon#about to read 6, iclass 17, count 2 2006.201.10:09:22.04#ibcon#read 6, iclass 17, count 2 2006.201.10:09:22.04#ibcon#end of sib2, iclass 17, count 2 2006.201.10:09:22.04#ibcon#*mode == 0, iclass 17, count 2 2006.201.10:09:22.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.10:09:22.04#ibcon#[25=AT01-08\r\n] 2006.201.10:09:22.04#ibcon#*before write, iclass 17, count 2 2006.201.10:09:22.04#ibcon#enter sib2, iclass 17, count 2 2006.201.10:09:22.04#ibcon#flushed, iclass 17, count 2 2006.201.10:09:22.04#ibcon#about to write, iclass 17, count 2 2006.201.10:09:22.04#ibcon#wrote, iclass 17, count 2 2006.201.10:09:22.04#ibcon#about to read 3, iclass 17, count 2 2006.201.10:09:22.07#ibcon#read 3, iclass 17, count 2 2006.201.10:09:22.07#ibcon#about to read 4, iclass 17, count 2 2006.201.10:09:22.07#ibcon#read 4, iclass 17, count 2 2006.201.10:09:22.07#ibcon#about to read 5, iclass 17, count 2 2006.201.10:09:22.07#ibcon#read 5, iclass 17, count 2 2006.201.10:09:22.07#ibcon#about to read 6, iclass 17, count 2 2006.201.10:09:22.07#ibcon#read 6, iclass 17, count 2 2006.201.10:09:22.07#ibcon#end of sib2, iclass 17, count 2 2006.201.10:09:22.07#ibcon#*after write, iclass 17, count 2 2006.201.10:09:22.07#ibcon#*before return 0, iclass 17, count 2 2006.201.10:09:22.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:22.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:22.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.10:09:22.07#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:22.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:22.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:22.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:22.19#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:09:22.19#ibcon#first serial, iclass 17, count 0 2006.201.10:09:22.19#ibcon#enter sib2, iclass 17, count 0 2006.201.10:09:22.19#ibcon#flushed, iclass 17, count 0 2006.201.10:09:22.19#ibcon#about to write, iclass 17, count 0 2006.201.10:09:22.19#ibcon#wrote, iclass 17, count 0 2006.201.10:09:22.19#ibcon#about to read 3, iclass 17, count 0 2006.201.10:09:22.21#ibcon#read 3, iclass 17, count 0 2006.201.10:09:22.21#ibcon#about to read 4, iclass 17, count 0 2006.201.10:09:22.21#ibcon#read 4, iclass 17, count 0 2006.201.10:09:22.21#ibcon#about to read 5, iclass 17, count 0 2006.201.10:09:22.21#ibcon#read 5, iclass 17, count 0 2006.201.10:09:22.21#ibcon#about to read 6, iclass 17, count 0 2006.201.10:09:22.21#ibcon#read 6, iclass 17, count 0 2006.201.10:09:22.21#ibcon#end of sib2, iclass 17, count 0 2006.201.10:09:22.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:09:22.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:09:22.21#ibcon#[25=USB\r\n] 2006.201.10:09:22.21#ibcon#*before write, iclass 17, count 0 2006.201.10:09:22.21#ibcon#enter sib2, iclass 17, count 0 2006.201.10:09:22.21#ibcon#flushed, iclass 17, count 0 2006.201.10:09:22.21#ibcon#about to write, iclass 17, count 0 2006.201.10:09:22.21#ibcon#wrote, iclass 17, count 0 2006.201.10:09:22.21#ibcon#about to read 3, iclass 17, count 0 2006.201.10:09:22.24#ibcon#read 3, iclass 17, count 0 2006.201.10:09:22.24#ibcon#about to read 4, iclass 17, count 0 2006.201.10:09:22.24#ibcon#read 4, iclass 17, count 0 2006.201.10:09:22.24#ibcon#about to read 5, iclass 17, count 0 2006.201.10:09:22.24#ibcon#read 5, iclass 17, count 0 2006.201.10:09:22.24#ibcon#about to read 6, iclass 17, count 0 2006.201.10:09:22.24#ibcon#read 6, iclass 17, count 0 2006.201.10:09:22.24#ibcon#end of sib2, iclass 17, count 0 2006.201.10:09:22.24#ibcon#*after write, iclass 17, count 0 2006.201.10:09:22.24#ibcon#*before return 0, iclass 17, count 0 2006.201.10:09:22.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:22.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:22.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:09:22.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:09:22.24$vck44/valo=2,534.99 2006.201.10:09:22.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.10:09:22.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.10:09:22.24#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:22.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:22.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:22.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:22.24#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:09:22.24#ibcon#first serial, iclass 19, count 0 2006.201.10:09:22.24#ibcon#enter sib2, iclass 19, count 0 2006.201.10:09:22.24#ibcon#flushed, iclass 19, count 0 2006.201.10:09:22.24#ibcon#about to write, iclass 19, count 0 2006.201.10:09:22.24#ibcon#wrote, iclass 19, count 0 2006.201.10:09:22.24#ibcon#about to read 3, iclass 19, count 0 2006.201.10:09:22.26#ibcon#read 3, iclass 19, count 0 2006.201.10:09:22.26#ibcon#about to read 4, iclass 19, count 0 2006.201.10:09:22.26#ibcon#read 4, iclass 19, count 0 2006.201.10:09:22.26#ibcon#about to read 5, iclass 19, count 0 2006.201.10:09:22.26#ibcon#read 5, iclass 19, count 0 2006.201.10:09:22.26#ibcon#about to read 6, iclass 19, count 0 2006.201.10:09:22.26#ibcon#read 6, iclass 19, count 0 2006.201.10:09:22.26#ibcon#end of sib2, iclass 19, count 0 2006.201.10:09:22.26#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:09:22.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:09:22.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:09:22.26#ibcon#*before write, iclass 19, count 0 2006.201.10:09:22.26#ibcon#enter sib2, iclass 19, count 0 2006.201.10:09:22.26#ibcon#flushed, iclass 19, count 0 2006.201.10:09:22.26#ibcon#about to write, iclass 19, count 0 2006.201.10:09:22.26#ibcon#wrote, iclass 19, count 0 2006.201.10:09:22.26#ibcon#about to read 3, iclass 19, count 0 2006.201.10:09:22.30#ibcon#read 3, iclass 19, count 0 2006.201.10:09:22.30#ibcon#about to read 4, iclass 19, count 0 2006.201.10:09:22.30#ibcon#read 4, iclass 19, count 0 2006.201.10:09:22.30#ibcon#about to read 5, iclass 19, count 0 2006.201.10:09:22.30#ibcon#read 5, iclass 19, count 0 2006.201.10:09:22.30#ibcon#about to read 6, iclass 19, count 0 2006.201.10:09:22.30#ibcon#read 6, iclass 19, count 0 2006.201.10:09:22.30#ibcon#end of sib2, iclass 19, count 0 2006.201.10:09:22.30#ibcon#*after write, iclass 19, count 0 2006.201.10:09:22.30#ibcon#*before return 0, iclass 19, count 0 2006.201.10:09:22.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:22.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:22.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:09:22.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:09:22.30$vck44/va=2,7 2006.201.10:09:22.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.10:09:22.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.10:09:22.30#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:22.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:22.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:22.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:22.36#ibcon#enter wrdev, iclass 21, count 2 2006.201.10:09:22.36#ibcon#first serial, iclass 21, count 2 2006.201.10:09:22.36#ibcon#enter sib2, iclass 21, count 2 2006.201.10:09:22.36#ibcon#flushed, iclass 21, count 2 2006.201.10:09:22.36#ibcon#about to write, iclass 21, count 2 2006.201.10:09:22.36#ibcon#wrote, iclass 21, count 2 2006.201.10:09:22.36#ibcon#about to read 3, iclass 21, count 2 2006.201.10:09:22.38#ibcon#read 3, iclass 21, count 2 2006.201.10:09:22.38#ibcon#about to read 4, iclass 21, count 2 2006.201.10:09:22.38#ibcon#read 4, iclass 21, count 2 2006.201.10:09:22.38#ibcon#about to read 5, iclass 21, count 2 2006.201.10:09:22.38#ibcon#read 5, iclass 21, count 2 2006.201.10:09:22.38#ibcon#about to read 6, iclass 21, count 2 2006.201.10:09:22.38#ibcon#read 6, iclass 21, count 2 2006.201.10:09:22.38#ibcon#end of sib2, iclass 21, count 2 2006.201.10:09:22.38#ibcon#*mode == 0, iclass 21, count 2 2006.201.10:09:22.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.10:09:22.38#ibcon#[25=AT02-07\r\n] 2006.201.10:09:22.38#ibcon#*before write, iclass 21, count 2 2006.201.10:09:22.38#ibcon#enter sib2, iclass 21, count 2 2006.201.10:09:22.38#ibcon#flushed, iclass 21, count 2 2006.201.10:09:22.38#ibcon#about to write, iclass 21, count 2 2006.201.10:09:22.38#ibcon#wrote, iclass 21, count 2 2006.201.10:09:22.38#ibcon#about to read 3, iclass 21, count 2 2006.201.10:09:22.41#ibcon#read 3, iclass 21, count 2 2006.201.10:09:22.41#ibcon#about to read 4, iclass 21, count 2 2006.201.10:09:22.41#ibcon#read 4, iclass 21, count 2 2006.201.10:09:22.41#ibcon#about to read 5, iclass 21, count 2 2006.201.10:09:22.41#ibcon#read 5, iclass 21, count 2 2006.201.10:09:22.41#ibcon#about to read 6, iclass 21, count 2 2006.201.10:09:22.41#ibcon#read 6, iclass 21, count 2 2006.201.10:09:22.41#ibcon#end of sib2, iclass 21, count 2 2006.201.10:09:22.41#ibcon#*after write, iclass 21, count 2 2006.201.10:09:22.41#ibcon#*before return 0, iclass 21, count 2 2006.201.10:09:22.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:22.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:22.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.10:09:22.41#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:22.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:22.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:22.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:22.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:09:22.53#ibcon#first serial, iclass 21, count 0 2006.201.10:09:22.53#ibcon#enter sib2, iclass 21, count 0 2006.201.10:09:22.53#ibcon#flushed, iclass 21, count 0 2006.201.10:09:22.53#ibcon#about to write, iclass 21, count 0 2006.201.10:09:22.53#ibcon#wrote, iclass 21, count 0 2006.201.10:09:22.53#ibcon#about to read 3, iclass 21, count 0 2006.201.10:09:22.55#ibcon#read 3, iclass 21, count 0 2006.201.10:09:22.55#ibcon#about to read 4, iclass 21, count 0 2006.201.10:09:22.55#ibcon#read 4, iclass 21, count 0 2006.201.10:09:22.55#ibcon#about to read 5, iclass 21, count 0 2006.201.10:09:22.55#ibcon#read 5, iclass 21, count 0 2006.201.10:09:22.55#ibcon#about to read 6, iclass 21, count 0 2006.201.10:09:22.55#ibcon#read 6, iclass 21, count 0 2006.201.10:09:22.55#ibcon#end of sib2, iclass 21, count 0 2006.201.10:09:22.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:09:22.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:09:22.55#ibcon#[25=USB\r\n] 2006.201.10:09:22.55#ibcon#*before write, iclass 21, count 0 2006.201.10:09:22.55#ibcon#enter sib2, iclass 21, count 0 2006.201.10:09:22.55#ibcon#flushed, iclass 21, count 0 2006.201.10:09:22.55#ibcon#about to write, iclass 21, count 0 2006.201.10:09:22.55#ibcon#wrote, iclass 21, count 0 2006.201.10:09:22.55#ibcon#about to read 3, iclass 21, count 0 2006.201.10:09:22.58#ibcon#read 3, iclass 21, count 0 2006.201.10:09:22.58#ibcon#about to read 4, iclass 21, count 0 2006.201.10:09:22.58#ibcon#read 4, iclass 21, count 0 2006.201.10:09:22.58#ibcon#about to read 5, iclass 21, count 0 2006.201.10:09:22.58#ibcon#read 5, iclass 21, count 0 2006.201.10:09:22.58#ibcon#about to read 6, iclass 21, count 0 2006.201.10:09:22.58#ibcon#read 6, iclass 21, count 0 2006.201.10:09:22.58#ibcon#end of sib2, iclass 21, count 0 2006.201.10:09:22.58#ibcon#*after write, iclass 21, count 0 2006.201.10:09:22.58#ibcon#*before return 0, iclass 21, count 0 2006.201.10:09:22.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:22.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:22.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:09:22.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:09:22.58$vck44/valo=3,564.99 2006.201.10:09:22.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.10:09:22.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.10:09:22.58#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:22.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:22.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:22.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:22.58#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:09:22.58#ibcon#first serial, iclass 23, count 0 2006.201.10:09:22.58#ibcon#enter sib2, iclass 23, count 0 2006.201.10:09:22.58#ibcon#flushed, iclass 23, count 0 2006.201.10:09:22.58#ibcon#about to write, iclass 23, count 0 2006.201.10:09:22.58#ibcon#wrote, iclass 23, count 0 2006.201.10:09:22.58#ibcon#about to read 3, iclass 23, count 0 2006.201.10:09:22.60#ibcon#read 3, iclass 23, count 0 2006.201.10:09:22.60#ibcon#about to read 4, iclass 23, count 0 2006.201.10:09:22.60#ibcon#read 4, iclass 23, count 0 2006.201.10:09:22.60#ibcon#about to read 5, iclass 23, count 0 2006.201.10:09:22.60#ibcon#read 5, iclass 23, count 0 2006.201.10:09:22.60#ibcon#about to read 6, iclass 23, count 0 2006.201.10:09:22.60#ibcon#read 6, iclass 23, count 0 2006.201.10:09:22.60#ibcon#end of sib2, iclass 23, count 0 2006.201.10:09:22.60#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:09:22.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:09:22.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:09:22.60#ibcon#*before write, iclass 23, count 0 2006.201.10:09:22.60#ibcon#enter sib2, iclass 23, count 0 2006.201.10:09:22.60#ibcon#flushed, iclass 23, count 0 2006.201.10:09:22.60#ibcon#about to write, iclass 23, count 0 2006.201.10:09:22.60#ibcon#wrote, iclass 23, count 0 2006.201.10:09:22.60#ibcon#about to read 3, iclass 23, count 0 2006.201.10:09:22.65#ibcon#read 3, iclass 23, count 0 2006.201.10:09:22.65#ibcon#about to read 4, iclass 23, count 0 2006.201.10:09:22.65#ibcon#read 4, iclass 23, count 0 2006.201.10:09:22.65#ibcon#about to read 5, iclass 23, count 0 2006.201.10:09:22.65#ibcon#read 5, iclass 23, count 0 2006.201.10:09:22.65#ibcon#about to read 6, iclass 23, count 0 2006.201.10:09:22.65#ibcon#read 6, iclass 23, count 0 2006.201.10:09:22.65#ibcon#end of sib2, iclass 23, count 0 2006.201.10:09:22.65#ibcon#*after write, iclass 23, count 0 2006.201.10:09:22.65#ibcon#*before return 0, iclass 23, count 0 2006.201.10:09:22.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:22.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:22.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:09:22.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:09:22.65$vck44/va=3,8 2006.201.10:09:22.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.10:09:22.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.10:09:22.65#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:22.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:22.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:22.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:22.70#ibcon#enter wrdev, iclass 25, count 2 2006.201.10:09:22.70#ibcon#first serial, iclass 25, count 2 2006.201.10:09:22.70#ibcon#enter sib2, iclass 25, count 2 2006.201.10:09:22.70#ibcon#flushed, iclass 25, count 2 2006.201.10:09:22.70#ibcon#about to write, iclass 25, count 2 2006.201.10:09:22.70#ibcon#wrote, iclass 25, count 2 2006.201.10:09:22.70#ibcon#about to read 3, iclass 25, count 2 2006.201.10:09:22.72#ibcon#read 3, iclass 25, count 2 2006.201.10:09:22.72#ibcon#about to read 4, iclass 25, count 2 2006.201.10:09:22.72#ibcon#read 4, iclass 25, count 2 2006.201.10:09:22.72#ibcon#about to read 5, iclass 25, count 2 2006.201.10:09:22.72#ibcon#read 5, iclass 25, count 2 2006.201.10:09:22.72#ibcon#about to read 6, iclass 25, count 2 2006.201.10:09:22.72#ibcon#read 6, iclass 25, count 2 2006.201.10:09:22.72#ibcon#end of sib2, iclass 25, count 2 2006.201.10:09:22.72#ibcon#*mode == 0, iclass 25, count 2 2006.201.10:09:22.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.10:09:22.72#ibcon#[25=AT03-08\r\n] 2006.201.10:09:22.72#ibcon#*before write, iclass 25, count 2 2006.201.10:09:22.72#ibcon#enter sib2, iclass 25, count 2 2006.201.10:09:22.72#ibcon#flushed, iclass 25, count 2 2006.201.10:09:22.72#ibcon#about to write, iclass 25, count 2 2006.201.10:09:22.72#ibcon#wrote, iclass 25, count 2 2006.201.10:09:22.72#ibcon#about to read 3, iclass 25, count 2 2006.201.10:09:22.75#ibcon#read 3, iclass 25, count 2 2006.201.10:09:22.75#ibcon#about to read 4, iclass 25, count 2 2006.201.10:09:22.75#ibcon#read 4, iclass 25, count 2 2006.201.10:09:22.75#ibcon#about to read 5, iclass 25, count 2 2006.201.10:09:22.75#ibcon#read 5, iclass 25, count 2 2006.201.10:09:22.75#ibcon#about to read 6, iclass 25, count 2 2006.201.10:09:22.75#ibcon#read 6, iclass 25, count 2 2006.201.10:09:22.75#ibcon#end of sib2, iclass 25, count 2 2006.201.10:09:22.75#ibcon#*after write, iclass 25, count 2 2006.201.10:09:22.75#ibcon#*before return 0, iclass 25, count 2 2006.201.10:09:22.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:22.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:22.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.10:09:22.75#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:22.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:22.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:22.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:22.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:09:22.87#ibcon#first serial, iclass 25, count 0 2006.201.10:09:22.87#ibcon#enter sib2, iclass 25, count 0 2006.201.10:09:22.87#ibcon#flushed, iclass 25, count 0 2006.201.10:09:22.87#ibcon#about to write, iclass 25, count 0 2006.201.10:09:22.87#ibcon#wrote, iclass 25, count 0 2006.201.10:09:22.87#ibcon#about to read 3, iclass 25, count 0 2006.201.10:09:22.89#ibcon#read 3, iclass 25, count 0 2006.201.10:09:22.89#ibcon#about to read 4, iclass 25, count 0 2006.201.10:09:22.89#ibcon#read 4, iclass 25, count 0 2006.201.10:09:22.89#ibcon#about to read 5, iclass 25, count 0 2006.201.10:09:22.89#ibcon#read 5, iclass 25, count 0 2006.201.10:09:22.89#ibcon#about to read 6, iclass 25, count 0 2006.201.10:09:22.89#ibcon#read 6, iclass 25, count 0 2006.201.10:09:22.89#ibcon#end of sib2, iclass 25, count 0 2006.201.10:09:22.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:09:22.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:09:22.89#ibcon#[25=USB\r\n] 2006.201.10:09:22.89#ibcon#*before write, iclass 25, count 0 2006.201.10:09:22.89#ibcon#enter sib2, iclass 25, count 0 2006.201.10:09:22.89#ibcon#flushed, iclass 25, count 0 2006.201.10:09:22.89#ibcon#about to write, iclass 25, count 0 2006.201.10:09:22.89#ibcon#wrote, iclass 25, count 0 2006.201.10:09:22.89#ibcon#about to read 3, iclass 25, count 0 2006.201.10:09:22.92#ibcon#read 3, iclass 25, count 0 2006.201.10:09:22.92#ibcon#about to read 4, iclass 25, count 0 2006.201.10:09:22.92#ibcon#read 4, iclass 25, count 0 2006.201.10:09:22.92#ibcon#about to read 5, iclass 25, count 0 2006.201.10:09:22.92#ibcon#read 5, iclass 25, count 0 2006.201.10:09:22.92#ibcon#about to read 6, iclass 25, count 0 2006.201.10:09:22.92#ibcon#read 6, iclass 25, count 0 2006.201.10:09:22.92#ibcon#end of sib2, iclass 25, count 0 2006.201.10:09:22.92#ibcon#*after write, iclass 25, count 0 2006.201.10:09:22.92#ibcon#*before return 0, iclass 25, count 0 2006.201.10:09:22.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:22.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:22.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:09:22.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:09:22.92$vck44/valo=4,624.99 2006.201.10:09:22.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.10:09:22.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.10:09:22.92#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:22.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:22.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:22.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:22.92#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:09:22.92#ibcon#first serial, iclass 27, count 0 2006.201.10:09:22.92#ibcon#enter sib2, iclass 27, count 0 2006.201.10:09:22.92#ibcon#flushed, iclass 27, count 0 2006.201.10:09:22.92#ibcon#about to write, iclass 27, count 0 2006.201.10:09:22.92#ibcon#wrote, iclass 27, count 0 2006.201.10:09:22.92#ibcon#about to read 3, iclass 27, count 0 2006.201.10:09:22.94#ibcon#read 3, iclass 27, count 0 2006.201.10:09:22.94#ibcon#about to read 4, iclass 27, count 0 2006.201.10:09:22.94#ibcon#read 4, iclass 27, count 0 2006.201.10:09:22.94#ibcon#about to read 5, iclass 27, count 0 2006.201.10:09:22.94#ibcon#read 5, iclass 27, count 0 2006.201.10:09:22.94#ibcon#about to read 6, iclass 27, count 0 2006.201.10:09:22.94#ibcon#read 6, iclass 27, count 0 2006.201.10:09:22.94#ibcon#end of sib2, iclass 27, count 0 2006.201.10:09:22.94#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:09:22.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:09:22.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:09:22.94#ibcon#*before write, iclass 27, count 0 2006.201.10:09:22.94#ibcon#enter sib2, iclass 27, count 0 2006.201.10:09:22.94#ibcon#flushed, iclass 27, count 0 2006.201.10:09:22.94#ibcon#about to write, iclass 27, count 0 2006.201.10:09:22.94#ibcon#wrote, iclass 27, count 0 2006.201.10:09:22.94#ibcon#about to read 3, iclass 27, count 0 2006.201.10:09:22.98#ibcon#read 3, iclass 27, count 0 2006.201.10:09:22.98#ibcon#about to read 4, iclass 27, count 0 2006.201.10:09:22.98#ibcon#read 4, iclass 27, count 0 2006.201.10:09:22.98#ibcon#about to read 5, iclass 27, count 0 2006.201.10:09:22.98#ibcon#read 5, iclass 27, count 0 2006.201.10:09:22.98#ibcon#about to read 6, iclass 27, count 0 2006.201.10:09:22.98#ibcon#read 6, iclass 27, count 0 2006.201.10:09:22.98#ibcon#end of sib2, iclass 27, count 0 2006.201.10:09:22.98#ibcon#*after write, iclass 27, count 0 2006.201.10:09:22.98#ibcon#*before return 0, iclass 27, count 0 2006.201.10:09:22.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:22.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:22.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:09:22.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:09:22.98$vck44/va=4,7 2006.201.10:09:22.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.10:09:22.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.10:09:22.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:22.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:23.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:23.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:23.04#ibcon#enter wrdev, iclass 29, count 2 2006.201.10:09:23.04#ibcon#first serial, iclass 29, count 2 2006.201.10:09:23.04#ibcon#enter sib2, iclass 29, count 2 2006.201.10:09:23.04#ibcon#flushed, iclass 29, count 2 2006.201.10:09:23.04#ibcon#about to write, iclass 29, count 2 2006.201.10:09:23.04#ibcon#wrote, iclass 29, count 2 2006.201.10:09:23.04#ibcon#about to read 3, iclass 29, count 2 2006.201.10:09:23.06#ibcon#read 3, iclass 29, count 2 2006.201.10:09:23.06#ibcon#about to read 4, iclass 29, count 2 2006.201.10:09:23.06#ibcon#read 4, iclass 29, count 2 2006.201.10:09:23.06#ibcon#about to read 5, iclass 29, count 2 2006.201.10:09:23.06#ibcon#read 5, iclass 29, count 2 2006.201.10:09:23.06#ibcon#about to read 6, iclass 29, count 2 2006.201.10:09:23.06#ibcon#read 6, iclass 29, count 2 2006.201.10:09:23.06#ibcon#end of sib2, iclass 29, count 2 2006.201.10:09:23.06#ibcon#*mode == 0, iclass 29, count 2 2006.201.10:09:23.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.10:09:23.06#ibcon#[25=AT04-07\r\n] 2006.201.10:09:23.06#ibcon#*before write, iclass 29, count 2 2006.201.10:09:23.06#ibcon#enter sib2, iclass 29, count 2 2006.201.10:09:23.06#ibcon#flushed, iclass 29, count 2 2006.201.10:09:23.06#ibcon#about to write, iclass 29, count 2 2006.201.10:09:23.06#ibcon#wrote, iclass 29, count 2 2006.201.10:09:23.06#ibcon#about to read 3, iclass 29, count 2 2006.201.10:09:23.09#ibcon#read 3, iclass 29, count 2 2006.201.10:09:23.09#ibcon#about to read 4, iclass 29, count 2 2006.201.10:09:23.09#ibcon#read 4, iclass 29, count 2 2006.201.10:09:23.09#ibcon#about to read 5, iclass 29, count 2 2006.201.10:09:23.09#ibcon#read 5, iclass 29, count 2 2006.201.10:09:23.09#ibcon#about to read 6, iclass 29, count 2 2006.201.10:09:23.09#ibcon#read 6, iclass 29, count 2 2006.201.10:09:23.09#ibcon#end of sib2, iclass 29, count 2 2006.201.10:09:23.09#ibcon#*after write, iclass 29, count 2 2006.201.10:09:23.09#ibcon#*before return 0, iclass 29, count 2 2006.201.10:09:23.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:23.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:23.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.10:09:23.09#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:23.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:23.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:23.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:23.21#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:09:23.21#ibcon#first serial, iclass 29, count 0 2006.201.10:09:23.21#ibcon#enter sib2, iclass 29, count 0 2006.201.10:09:23.21#ibcon#flushed, iclass 29, count 0 2006.201.10:09:23.21#ibcon#about to write, iclass 29, count 0 2006.201.10:09:23.21#ibcon#wrote, iclass 29, count 0 2006.201.10:09:23.21#ibcon#about to read 3, iclass 29, count 0 2006.201.10:09:23.23#ibcon#read 3, iclass 29, count 0 2006.201.10:09:23.23#ibcon#about to read 4, iclass 29, count 0 2006.201.10:09:23.23#ibcon#read 4, iclass 29, count 0 2006.201.10:09:23.23#ibcon#about to read 5, iclass 29, count 0 2006.201.10:09:23.23#ibcon#read 5, iclass 29, count 0 2006.201.10:09:23.23#ibcon#about to read 6, iclass 29, count 0 2006.201.10:09:23.23#ibcon#read 6, iclass 29, count 0 2006.201.10:09:23.23#ibcon#end of sib2, iclass 29, count 0 2006.201.10:09:23.23#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:09:23.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:09:23.23#ibcon#[25=USB\r\n] 2006.201.10:09:23.23#ibcon#*before write, iclass 29, count 0 2006.201.10:09:23.23#ibcon#enter sib2, iclass 29, count 0 2006.201.10:09:23.23#ibcon#flushed, iclass 29, count 0 2006.201.10:09:23.23#ibcon#about to write, iclass 29, count 0 2006.201.10:09:23.23#ibcon#wrote, iclass 29, count 0 2006.201.10:09:23.23#ibcon#about to read 3, iclass 29, count 0 2006.201.10:09:23.26#ibcon#read 3, iclass 29, count 0 2006.201.10:09:23.26#ibcon#about to read 4, iclass 29, count 0 2006.201.10:09:23.26#ibcon#read 4, iclass 29, count 0 2006.201.10:09:23.26#ibcon#about to read 5, iclass 29, count 0 2006.201.10:09:23.26#ibcon#read 5, iclass 29, count 0 2006.201.10:09:23.26#ibcon#about to read 6, iclass 29, count 0 2006.201.10:09:23.26#ibcon#read 6, iclass 29, count 0 2006.201.10:09:23.26#ibcon#end of sib2, iclass 29, count 0 2006.201.10:09:23.26#ibcon#*after write, iclass 29, count 0 2006.201.10:09:23.26#ibcon#*before return 0, iclass 29, count 0 2006.201.10:09:23.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:23.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:23.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:09:23.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:09:23.26$vck44/valo=5,734.99 2006.201.10:09:23.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.10:09:23.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.10:09:23.26#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:23.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:23.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:23.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:23.26#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:09:23.26#ibcon#first serial, iclass 31, count 0 2006.201.10:09:23.26#ibcon#enter sib2, iclass 31, count 0 2006.201.10:09:23.26#ibcon#flushed, iclass 31, count 0 2006.201.10:09:23.26#ibcon#about to write, iclass 31, count 0 2006.201.10:09:23.26#ibcon#wrote, iclass 31, count 0 2006.201.10:09:23.26#ibcon#about to read 3, iclass 31, count 0 2006.201.10:09:23.28#ibcon#read 3, iclass 31, count 0 2006.201.10:09:23.28#ibcon#about to read 4, iclass 31, count 0 2006.201.10:09:23.28#ibcon#read 4, iclass 31, count 0 2006.201.10:09:23.28#ibcon#about to read 5, iclass 31, count 0 2006.201.10:09:23.28#ibcon#read 5, iclass 31, count 0 2006.201.10:09:23.28#ibcon#about to read 6, iclass 31, count 0 2006.201.10:09:23.28#ibcon#read 6, iclass 31, count 0 2006.201.10:09:23.28#ibcon#end of sib2, iclass 31, count 0 2006.201.10:09:23.28#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:09:23.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:09:23.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:09:23.28#ibcon#*before write, iclass 31, count 0 2006.201.10:09:23.28#ibcon#enter sib2, iclass 31, count 0 2006.201.10:09:23.28#ibcon#flushed, iclass 31, count 0 2006.201.10:09:23.28#ibcon#about to write, iclass 31, count 0 2006.201.10:09:23.28#ibcon#wrote, iclass 31, count 0 2006.201.10:09:23.28#ibcon#about to read 3, iclass 31, count 0 2006.201.10:09:23.32#ibcon#read 3, iclass 31, count 0 2006.201.10:09:23.32#ibcon#about to read 4, iclass 31, count 0 2006.201.10:09:23.32#ibcon#read 4, iclass 31, count 0 2006.201.10:09:23.32#ibcon#about to read 5, iclass 31, count 0 2006.201.10:09:23.32#ibcon#read 5, iclass 31, count 0 2006.201.10:09:23.32#ibcon#about to read 6, iclass 31, count 0 2006.201.10:09:23.32#ibcon#read 6, iclass 31, count 0 2006.201.10:09:23.32#ibcon#end of sib2, iclass 31, count 0 2006.201.10:09:23.32#ibcon#*after write, iclass 31, count 0 2006.201.10:09:23.32#ibcon#*before return 0, iclass 31, count 0 2006.201.10:09:23.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:23.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:23.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:09:23.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:09:23.32$vck44/va=5,4 2006.201.10:09:23.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.10:09:23.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.10:09:23.32#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:23.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:23.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:23.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:23.38#ibcon#enter wrdev, iclass 33, count 2 2006.201.10:09:23.38#ibcon#first serial, iclass 33, count 2 2006.201.10:09:23.38#ibcon#enter sib2, iclass 33, count 2 2006.201.10:09:23.38#ibcon#flushed, iclass 33, count 2 2006.201.10:09:23.38#ibcon#about to write, iclass 33, count 2 2006.201.10:09:23.38#ibcon#wrote, iclass 33, count 2 2006.201.10:09:23.38#ibcon#about to read 3, iclass 33, count 2 2006.201.10:09:23.40#ibcon#read 3, iclass 33, count 2 2006.201.10:09:23.40#ibcon#about to read 4, iclass 33, count 2 2006.201.10:09:23.40#ibcon#read 4, iclass 33, count 2 2006.201.10:09:23.40#ibcon#about to read 5, iclass 33, count 2 2006.201.10:09:23.40#ibcon#read 5, iclass 33, count 2 2006.201.10:09:23.40#ibcon#about to read 6, iclass 33, count 2 2006.201.10:09:23.40#ibcon#read 6, iclass 33, count 2 2006.201.10:09:23.40#ibcon#end of sib2, iclass 33, count 2 2006.201.10:09:23.40#ibcon#*mode == 0, iclass 33, count 2 2006.201.10:09:23.40#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.10:09:23.40#ibcon#[25=AT05-04\r\n] 2006.201.10:09:23.40#ibcon#*before write, iclass 33, count 2 2006.201.10:09:23.40#ibcon#enter sib2, iclass 33, count 2 2006.201.10:09:23.40#ibcon#flushed, iclass 33, count 2 2006.201.10:09:23.40#ibcon#about to write, iclass 33, count 2 2006.201.10:09:23.40#ibcon#wrote, iclass 33, count 2 2006.201.10:09:23.40#ibcon#about to read 3, iclass 33, count 2 2006.201.10:09:23.43#ibcon#read 3, iclass 33, count 2 2006.201.10:09:23.43#ibcon#about to read 4, iclass 33, count 2 2006.201.10:09:23.43#ibcon#read 4, iclass 33, count 2 2006.201.10:09:23.43#ibcon#about to read 5, iclass 33, count 2 2006.201.10:09:23.43#ibcon#read 5, iclass 33, count 2 2006.201.10:09:23.43#ibcon#about to read 6, iclass 33, count 2 2006.201.10:09:23.43#ibcon#read 6, iclass 33, count 2 2006.201.10:09:23.43#ibcon#end of sib2, iclass 33, count 2 2006.201.10:09:23.43#ibcon#*after write, iclass 33, count 2 2006.201.10:09:23.43#ibcon#*before return 0, iclass 33, count 2 2006.201.10:09:23.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:23.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:23.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.10:09:23.43#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:23.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:23.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:23.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:23.55#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:09:23.55#ibcon#first serial, iclass 33, count 0 2006.201.10:09:23.55#ibcon#enter sib2, iclass 33, count 0 2006.201.10:09:23.55#ibcon#flushed, iclass 33, count 0 2006.201.10:09:23.55#ibcon#about to write, iclass 33, count 0 2006.201.10:09:23.55#ibcon#wrote, iclass 33, count 0 2006.201.10:09:23.55#ibcon#about to read 3, iclass 33, count 0 2006.201.10:09:23.57#ibcon#read 3, iclass 33, count 0 2006.201.10:09:23.57#ibcon#about to read 4, iclass 33, count 0 2006.201.10:09:23.57#ibcon#read 4, iclass 33, count 0 2006.201.10:09:23.57#ibcon#about to read 5, iclass 33, count 0 2006.201.10:09:23.57#ibcon#read 5, iclass 33, count 0 2006.201.10:09:23.57#ibcon#about to read 6, iclass 33, count 0 2006.201.10:09:23.57#ibcon#read 6, iclass 33, count 0 2006.201.10:09:23.57#ibcon#end of sib2, iclass 33, count 0 2006.201.10:09:23.57#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:09:23.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:09:23.57#ibcon#[25=USB\r\n] 2006.201.10:09:23.57#ibcon#*before write, iclass 33, count 0 2006.201.10:09:23.57#ibcon#enter sib2, iclass 33, count 0 2006.201.10:09:23.57#ibcon#flushed, iclass 33, count 0 2006.201.10:09:23.57#ibcon#about to write, iclass 33, count 0 2006.201.10:09:23.57#ibcon#wrote, iclass 33, count 0 2006.201.10:09:23.57#ibcon#about to read 3, iclass 33, count 0 2006.201.10:09:23.60#ibcon#read 3, iclass 33, count 0 2006.201.10:09:23.60#ibcon#about to read 4, iclass 33, count 0 2006.201.10:09:23.60#ibcon#read 4, iclass 33, count 0 2006.201.10:09:23.60#ibcon#about to read 5, iclass 33, count 0 2006.201.10:09:23.60#ibcon#read 5, iclass 33, count 0 2006.201.10:09:23.60#ibcon#about to read 6, iclass 33, count 0 2006.201.10:09:23.60#ibcon#read 6, iclass 33, count 0 2006.201.10:09:23.60#ibcon#end of sib2, iclass 33, count 0 2006.201.10:09:23.60#ibcon#*after write, iclass 33, count 0 2006.201.10:09:23.60#ibcon#*before return 0, iclass 33, count 0 2006.201.10:09:23.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:23.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:23.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:09:23.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:09:23.60$vck44/valo=6,814.99 2006.201.10:09:23.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.10:09:23.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.10:09:23.60#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:23.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:23.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:23.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:23.60#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:09:23.60#ibcon#first serial, iclass 35, count 0 2006.201.10:09:23.60#ibcon#enter sib2, iclass 35, count 0 2006.201.10:09:23.60#ibcon#flushed, iclass 35, count 0 2006.201.10:09:23.60#ibcon#about to write, iclass 35, count 0 2006.201.10:09:23.60#ibcon#wrote, iclass 35, count 0 2006.201.10:09:23.60#ibcon#about to read 3, iclass 35, count 0 2006.201.10:09:23.62#ibcon#read 3, iclass 35, count 0 2006.201.10:09:23.62#ibcon#about to read 4, iclass 35, count 0 2006.201.10:09:23.62#ibcon#read 4, iclass 35, count 0 2006.201.10:09:23.62#ibcon#about to read 5, iclass 35, count 0 2006.201.10:09:23.62#ibcon#read 5, iclass 35, count 0 2006.201.10:09:23.62#ibcon#about to read 6, iclass 35, count 0 2006.201.10:09:23.62#ibcon#read 6, iclass 35, count 0 2006.201.10:09:23.62#ibcon#end of sib2, iclass 35, count 0 2006.201.10:09:23.62#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:09:23.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:09:23.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:09:23.62#ibcon#*before write, iclass 35, count 0 2006.201.10:09:23.62#ibcon#enter sib2, iclass 35, count 0 2006.201.10:09:23.62#ibcon#flushed, iclass 35, count 0 2006.201.10:09:23.62#ibcon#about to write, iclass 35, count 0 2006.201.10:09:23.62#ibcon#wrote, iclass 35, count 0 2006.201.10:09:23.62#ibcon#about to read 3, iclass 35, count 0 2006.201.10:09:23.67#ibcon#read 3, iclass 35, count 0 2006.201.10:09:23.67#ibcon#about to read 4, iclass 35, count 0 2006.201.10:09:23.67#ibcon#read 4, iclass 35, count 0 2006.201.10:09:23.67#ibcon#about to read 5, iclass 35, count 0 2006.201.10:09:23.67#ibcon#read 5, iclass 35, count 0 2006.201.10:09:23.67#ibcon#about to read 6, iclass 35, count 0 2006.201.10:09:23.67#ibcon#read 6, iclass 35, count 0 2006.201.10:09:23.67#ibcon#end of sib2, iclass 35, count 0 2006.201.10:09:23.67#ibcon#*after write, iclass 35, count 0 2006.201.10:09:23.67#ibcon#*before return 0, iclass 35, count 0 2006.201.10:09:23.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:23.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:23.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:09:23.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:09:23.67$vck44/va=6,5 2006.201.10:09:23.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.10:09:23.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.10:09:23.67#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:23.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:23.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:23.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:23.72#ibcon#enter wrdev, iclass 37, count 2 2006.201.10:09:23.72#ibcon#first serial, iclass 37, count 2 2006.201.10:09:23.72#ibcon#enter sib2, iclass 37, count 2 2006.201.10:09:23.72#ibcon#flushed, iclass 37, count 2 2006.201.10:09:23.72#ibcon#about to write, iclass 37, count 2 2006.201.10:09:23.72#ibcon#wrote, iclass 37, count 2 2006.201.10:09:23.72#ibcon#about to read 3, iclass 37, count 2 2006.201.10:09:23.74#ibcon#read 3, iclass 37, count 2 2006.201.10:09:23.74#ibcon#about to read 4, iclass 37, count 2 2006.201.10:09:23.74#ibcon#read 4, iclass 37, count 2 2006.201.10:09:23.74#ibcon#about to read 5, iclass 37, count 2 2006.201.10:09:23.74#ibcon#read 5, iclass 37, count 2 2006.201.10:09:23.74#ibcon#about to read 6, iclass 37, count 2 2006.201.10:09:23.74#ibcon#read 6, iclass 37, count 2 2006.201.10:09:23.74#ibcon#end of sib2, iclass 37, count 2 2006.201.10:09:23.74#ibcon#*mode == 0, iclass 37, count 2 2006.201.10:09:23.74#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.10:09:23.74#ibcon#[25=AT06-05\r\n] 2006.201.10:09:23.74#ibcon#*before write, iclass 37, count 2 2006.201.10:09:23.74#ibcon#enter sib2, iclass 37, count 2 2006.201.10:09:23.74#ibcon#flushed, iclass 37, count 2 2006.201.10:09:23.74#ibcon#about to write, iclass 37, count 2 2006.201.10:09:23.74#ibcon#wrote, iclass 37, count 2 2006.201.10:09:23.74#ibcon#about to read 3, iclass 37, count 2 2006.201.10:09:23.77#ibcon#read 3, iclass 37, count 2 2006.201.10:09:23.77#ibcon#about to read 4, iclass 37, count 2 2006.201.10:09:23.77#ibcon#read 4, iclass 37, count 2 2006.201.10:09:23.77#ibcon#about to read 5, iclass 37, count 2 2006.201.10:09:23.77#ibcon#read 5, iclass 37, count 2 2006.201.10:09:23.77#ibcon#about to read 6, iclass 37, count 2 2006.201.10:09:23.77#ibcon#read 6, iclass 37, count 2 2006.201.10:09:23.77#ibcon#end of sib2, iclass 37, count 2 2006.201.10:09:23.77#ibcon#*after write, iclass 37, count 2 2006.201.10:09:23.77#ibcon#*before return 0, iclass 37, count 2 2006.201.10:09:23.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:23.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:23.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.10:09:23.77#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:23.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:23.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:23.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:23.89#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:09:23.89#ibcon#first serial, iclass 37, count 0 2006.201.10:09:23.89#ibcon#enter sib2, iclass 37, count 0 2006.201.10:09:23.89#ibcon#flushed, iclass 37, count 0 2006.201.10:09:23.89#ibcon#about to write, iclass 37, count 0 2006.201.10:09:23.89#ibcon#wrote, iclass 37, count 0 2006.201.10:09:23.89#ibcon#about to read 3, iclass 37, count 0 2006.201.10:09:23.91#ibcon#read 3, iclass 37, count 0 2006.201.10:09:23.91#ibcon#about to read 4, iclass 37, count 0 2006.201.10:09:23.91#ibcon#read 4, iclass 37, count 0 2006.201.10:09:23.91#ibcon#about to read 5, iclass 37, count 0 2006.201.10:09:23.91#ibcon#read 5, iclass 37, count 0 2006.201.10:09:23.91#ibcon#about to read 6, iclass 37, count 0 2006.201.10:09:23.91#ibcon#read 6, iclass 37, count 0 2006.201.10:09:23.91#ibcon#end of sib2, iclass 37, count 0 2006.201.10:09:23.91#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:09:23.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:09:23.91#ibcon#[25=USB\r\n] 2006.201.10:09:23.91#ibcon#*before write, iclass 37, count 0 2006.201.10:09:23.91#ibcon#enter sib2, iclass 37, count 0 2006.201.10:09:23.91#ibcon#flushed, iclass 37, count 0 2006.201.10:09:23.91#ibcon#about to write, iclass 37, count 0 2006.201.10:09:23.91#ibcon#wrote, iclass 37, count 0 2006.201.10:09:23.91#ibcon#about to read 3, iclass 37, count 0 2006.201.10:09:23.94#ibcon#read 3, iclass 37, count 0 2006.201.10:09:23.94#ibcon#about to read 4, iclass 37, count 0 2006.201.10:09:23.94#ibcon#read 4, iclass 37, count 0 2006.201.10:09:23.94#ibcon#about to read 5, iclass 37, count 0 2006.201.10:09:23.94#ibcon#read 5, iclass 37, count 0 2006.201.10:09:23.94#ibcon#about to read 6, iclass 37, count 0 2006.201.10:09:23.94#ibcon#read 6, iclass 37, count 0 2006.201.10:09:23.94#ibcon#end of sib2, iclass 37, count 0 2006.201.10:09:23.94#ibcon#*after write, iclass 37, count 0 2006.201.10:09:23.94#ibcon#*before return 0, iclass 37, count 0 2006.201.10:09:23.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:23.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:23.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:09:23.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:09:23.94$vck44/valo=7,864.99 2006.201.10:09:23.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.10:09:23.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.10:09:23.94#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:23.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:23.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:23.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:23.94#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:09:23.94#ibcon#first serial, iclass 39, count 0 2006.201.10:09:23.94#ibcon#enter sib2, iclass 39, count 0 2006.201.10:09:23.94#ibcon#flushed, iclass 39, count 0 2006.201.10:09:23.94#ibcon#about to write, iclass 39, count 0 2006.201.10:09:23.94#ibcon#wrote, iclass 39, count 0 2006.201.10:09:23.94#ibcon#about to read 3, iclass 39, count 0 2006.201.10:09:23.96#ibcon#read 3, iclass 39, count 0 2006.201.10:09:23.96#ibcon#about to read 4, iclass 39, count 0 2006.201.10:09:23.96#ibcon#read 4, iclass 39, count 0 2006.201.10:09:23.96#ibcon#about to read 5, iclass 39, count 0 2006.201.10:09:23.96#ibcon#read 5, iclass 39, count 0 2006.201.10:09:23.96#ibcon#about to read 6, iclass 39, count 0 2006.201.10:09:23.96#ibcon#read 6, iclass 39, count 0 2006.201.10:09:23.96#ibcon#end of sib2, iclass 39, count 0 2006.201.10:09:23.96#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:09:23.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:09:23.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:09:23.96#ibcon#*before write, iclass 39, count 0 2006.201.10:09:23.96#ibcon#enter sib2, iclass 39, count 0 2006.201.10:09:23.96#ibcon#flushed, iclass 39, count 0 2006.201.10:09:23.96#ibcon#about to write, iclass 39, count 0 2006.201.10:09:23.96#ibcon#wrote, iclass 39, count 0 2006.201.10:09:23.96#ibcon#about to read 3, iclass 39, count 0 2006.201.10:09:24.00#ibcon#read 3, iclass 39, count 0 2006.201.10:09:24.00#ibcon#about to read 4, iclass 39, count 0 2006.201.10:09:24.00#ibcon#read 4, iclass 39, count 0 2006.201.10:09:24.00#ibcon#about to read 5, iclass 39, count 0 2006.201.10:09:24.00#ibcon#read 5, iclass 39, count 0 2006.201.10:09:24.00#ibcon#about to read 6, iclass 39, count 0 2006.201.10:09:24.00#ibcon#read 6, iclass 39, count 0 2006.201.10:09:24.00#ibcon#end of sib2, iclass 39, count 0 2006.201.10:09:24.00#ibcon#*after write, iclass 39, count 0 2006.201.10:09:24.00#ibcon#*before return 0, iclass 39, count 0 2006.201.10:09:24.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:24.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:24.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:09:24.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:09:24.00$vck44/va=7,5 2006.201.10:09:24.00#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.10:09:24.00#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.10:09:24.00#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:24.00#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:24.06#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:24.06#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:24.06#ibcon#enter wrdev, iclass 2, count 2 2006.201.10:09:24.06#ibcon#first serial, iclass 2, count 2 2006.201.10:09:24.06#ibcon#enter sib2, iclass 2, count 2 2006.201.10:09:24.06#ibcon#flushed, iclass 2, count 2 2006.201.10:09:24.06#ibcon#about to write, iclass 2, count 2 2006.201.10:09:24.06#ibcon#wrote, iclass 2, count 2 2006.201.10:09:24.06#ibcon#about to read 3, iclass 2, count 2 2006.201.10:09:24.08#ibcon#read 3, iclass 2, count 2 2006.201.10:09:24.08#ibcon#about to read 4, iclass 2, count 2 2006.201.10:09:24.08#ibcon#read 4, iclass 2, count 2 2006.201.10:09:24.08#ibcon#about to read 5, iclass 2, count 2 2006.201.10:09:24.08#ibcon#read 5, iclass 2, count 2 2006.201.10:09:24.08#ibcon#about to read 6, iclass 2, count 2 2006.201.10:09:24.08#ibcon#read 6, iclass 2, count 2 2006.201.10:09:24.08#ibcon#end of sib2, iclass 2, count 2 2006.201.10:09:24.08#ibcon#*mode == 0, iclass 2, count 2 2006.201.10:09:24.08#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.10:09:24.08#ibcon#[25=AT07-05\r\n] 2006.201.10:09:24.08#ibcon#*before write, iclass 2, count 2 2006.201.10:09:24.08#ibcon#enter sib2, iclass 2, count 2 2006.201.10:09:24.08#ibcon#flushed, iclass 2, count 2 2006.201.10:09:24.08#ibcon#about to write, iclass 2, count 2 2006.201.10:09:24.08#ibcon#wrote, iclass 2, count 2 2006.201.10:09:24.08#ibcon#about to read 3, iclass 2, count 2 2006.201.10:09:24.11#ibcon#read 3, iclass 2, count 2 2006.201.10:09:24.11#ibcon#about to read 4, iclass 2, count 2 2006.201.10:09:24.11#ibcon#read 4, iclass 2, count 2 2006.201.10:09:24.11#ibcon#about to read 5, iclass 2, count 2 2006.201.10:09:24.11#ibcon#read 5, iclass 2, count 2 2006.201.10:09:24.11#ibcon#about to read 6, iclass 2, count 2 2006.201.10:09:24.11#ibcon#read 6, iclass 2, count 2 2006.201.10:09:24.11#ibcon#end of sib2, iclass 2, count 2 2006.201.10:09:24.11#ibcon#*after write, iclass 2, count 2 2006.201.10:09:24.11#ibcon#*before return 0, iclass 2, count 2 2006.201.10:09:24.11#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:24.11#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:24.11#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.10:09:24.11#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:24.11#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:24.23#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:24.23#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:24.23#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:09:24.23#ibcon#first serial, iclass 2, count 0 2006.201.10:09:24.23#ibcon#enter sib2, iclass 2, count 0 2006.201.10:09:24.23#ibcon#flushed, iclass 2, count 0 2006.201.10:09:24.23#ibcon#about to write, iclass 2, count 0 2006.201.10:09:24.23#ibcon#wrote, iclass 2, count 0 2006.201.10:09:24.23#ibcon#about to read 3, iclass 2, count 0 2006.201.10:09:24.25#ibcon#read 3, iclass 2, count 0 2006.201.10:09:24.25#ibcon#about to read 4, iclass 2, count 0 2006.201.10:09:24.25#ibcon#read 4, iclass 2, count 0 2006.201.10:09:24.25#ibcon#about to read 5, iclass 2, count 0 2006.201.10:09:24.25#ibcon#read 5, iclass 2, count 0 2006.201.10:09:24.25#ibcon#about to read 6, iclass 2, count 0 2006.201.10:09:24.25#ibcon#read 6, iclass 2, count 0 2006.201.10:09:24.25#ibcon#end of sib2, iclass 2, count 0 2006.201.10:09:24.25#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:09:24.25#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:09:24.25#ibcon#[25=USB\r\n] 2006.201.10:09:24.25#ibcon#*before write, iclass 2, count 0 2006.201.10:09:24.25#ibcon#enter sib2, iclass 2, count 0 2006.201.10:09:24.25#ibcon#flushed, iclass 2, count 0 2006.201.10:09:24.25#ibcon#about to write, iclass 2, count 0 2006.201.10:09:24.25#ibcon#wrote, iclass 2, count 0 2006.201.10:09:24.25#ibcon#about to read 3, iclass 2, count 0 2006.201.10:09:24.28#ibcon#read 3, iclass 2, count 0 2006.201.10:09:24.28#ibcon#about to read 4, iclass 2, count 0 2006.201.10:09:24.28#ibcon#read 4, iclass 2, count 0 2006.201.10:09:24.28#ibcon#about to read 5, iclass 2, count 0 2006.201.10:09:24.28#ibcon#read 5, iclass 2, count 0 2006.201.10:09:24.28#ibcon#about to read 6, iclass 2, count 0 2006.201.10:09:24.28#ibcon#read 6, iclass 2, count 0 2006.201.10:09:24.28#ibcon#end of sib2, iclass 2, count 0 2006.201.10:09:24.28#ibcon#*after write, iclass 2, count 0 2006.201.10:09:24.28#ibcon#*before return 0, iclass 2, count 0 2006.201.10:09:24.28#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:24.28#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:24.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:09:24.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:09:24.28$vck44/valo=8,884.99 2006.201.10:09:24.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.10:09:24.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.10:09:24.28#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:24.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:09:24.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:09:24.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:09:24.28#ibcon#enter wrdev, iclass 5, count 0 2006.201.10:09:24.28#ibcon#first serial, iclass 5, count 0 2006.201.10:09:24.28#ibcon#enter sib2, iclass 5, count 0 2006.201.10:09:24.28#ibcon#flushed, iclass 5, count 0 2006.201.10:09:24.28#ibcon#about to write, iclass 5, count 0 2006.201.10:09:24.28#ibcon#wrote, iclass 5, count 0 2006.201.10:09:24.28#ibcon#about to read 3, iclass 5, count 0 2006.201.10:09:24.30#ibcon#read 3, iclass 5, count 0 2006.201.10:09:24.30#ibcon#about to read 4, iclass 5, count 0 2006.201.10:09:24.30#ibcon#read 4, iclass 5, count 0 2006.201.10:09:24.30#ibcon#about to read 5, iclass 5, count 0 2006.201.10:09:24.30#ibcon#read 5, iclass 5, count 0 2006.201.10:09:24.30#ibcon#about to read 6, iclass 5, count 0 2006.201.10:09:24.30#ibcon#read 6, iclass 5, count 0 2006.201.10:09:24.30#ibcon#end of sib2, iclass 5, count 0 2006.201.10:09:24.30#ibcon#*mode == 0, iclass 5, count 0 2006.201.10:09:24.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.10:09:24.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:09:24.30#ibcon#*before write, iclass 5, count 0 2006.201.10:09:24.30#ibcon#enter sib2, iclass 5, count 0 2006.201.10:09:24.30#ibcon#flushed, iclass 5, count 0 2006.201.10:09:24.30#ibcon#about to write, iclass 5, count 0 2006.201.10:09:24.30#ibcon#wrote, iclass 5, count 0 2006.201.10:09:24.30#ibcon#about to read 3, iclass 5, count 0 2006.201.10:09:24.34#ibcon#read 3, iclass 5, count 0 2006.201.10:09:24.34#ibcon#about to read 4, iclass 5, count 0 2006.201.10:09:24.34#ibcon#read 4, iclass 5, count 0 2006.201.10:09:24.34#ibcon#about to read 5, iclass 5, count 0 2006.201.10:09:24.34#ibcon#read 5, iclass 5, count 0 2006.201.10:09:24.34#ibcon#about to read 6, iclass 5, count 0 2006.201.10:09:24.34#ibcon#read 6, iclass 5, count 0 2006.201.10:09:24.34#ibcon#end of sib2, iclass 5, count 0 2006.201.10:09:24.34#ibcon#*after write, iclass 5, count 0 2006.201.10:09:24.34#ibcon#*before return 0, iclass 5, count 0 2006.201.10:09:24.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:09:24.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:09:24.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.10:09:24.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.10:09:24.34$vck44/va=8,4 2006.201.10:09:24.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.10:09:24.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.10:09:24.34#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:24.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:09:24.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:09:24.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:09:24.40#ibcon#enter wrdev, iclass 7, count 2 2006.201.10:09:24.40#ibcon#first serial, iclass 7, count 2 2006.201.10:09:24.40#ibcon#enter sib2, iclass 7, count 2 2006.201.10:09:24.40#ibcon#flushed, iclass 7, count 2 2006.201.10:09:24.40#ibcon#about to write, iclass 7, count 2 2006.201.10:09:24.40#ibcon#wrote, iclass 7, count 2 2006.201.10:09:24.40#ibcon#about to read 3, iclass 7, count 2 2006.201.10:09:24.42#ibcon#read 3, iclass 7, count 2 2006.201.10:09:24.42#ibcon#about to read 4, iclass 7, count 2 2006.201.10:09:24.42#ibcon#read 4, iclass 7, count 2 2006.201.10:09:24.42#ibcon#about to read 5, iclass 7, count 2 2006.201.10:09:24.42#ibcon#read 5, iclass 7, count 2 2006.201.10:09:24.42#ibcon#about to read 6, iclass 7, count 2 2006.201.10:09:24.42#ibcon#read 6, iclass 7, count 2 2006.201.10:09:24.42#ibcon#end of sib2, iclass 7, count 2 2006.201.10:09:24.42#ibcon#*mode == 0, iclass 7, count 2 2006.201.10:09:24.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.10:09:24.42#ibcon#[25=AT08-04\r\n] 2006.201.10:09:24.42#ibcon#*before write, iclass 7, count 2 2006.201.10:09:24.42#ibcon#enter sib2, iclass 7, count 2 2006.201.10:09:24.42#ibcon#flushed, iclass 7, count 2 2006.201.10:09:24.42#ibcon#about to write, iclass 7, count 2 2006.201.10:09:24.42#ibcon#wrote, iclass 7, count 2 2006.201.10:09:24.42#ibcon#about to read 3, iclass 7, count 2 2006.201.10:09:24.45#ibcon#read 3, iclass 7, count 2 2006.201.10:09:24.45#ibcon#about to read 4, iclass 7, count 2 2006.201.10:09:24.45#ibcon#read 4, iclass 7, count 2 2006.201.10:09:24.45#ibcon#about to read 5, iclass 7, count 2 2006.201.10:09:24.45#ibcon#read 5, iclass 7, count 2 2006.201.10:09:24.45#ibcon#about to read 6, iclass 7, count 2 2006.201.10:09:24.45#ibcon#read 6, iclass 7, count 2 2006.201.10:09:24.45#ibcon#end of sib2, iclass 7, count 2 2006.201.10:09:24.45#ibcon#*after write, iclass 7, count 2 2006.201.10:09:24.45#ibcon#*before return 0, iclass 7, count 2 2006.201.10:09:24.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:09:24.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:09:24.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.10:09:24.45#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:24.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:09:24.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:09:24.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:09:24.57#ibcon#enter wrdev, iclass 7, count 0 2006.201.10:09:24.57#ibcon#first serial, iclass 7, count 0 2006.201.10:09:24.57#ibcon#enter sib2, iclass 7, count 0 2006.201.10:09:24.57#ibcon#flushed, iclass 7, count 0 2006.201.10:09:24.57#ibcon#about to write, iclass 7, count 0 2006.201.10:09:24.57#ibcon#wrote, iclass 7, count 0 2006.201.10:09:24.57#ibcon#about to read 3, iclass 7, count 0 2006.201.10:09:24.59#ibcon#read 3, iclass 7, count 0 2006.201.10:09:24.59#ibcon#about to read 4, iclass 7, count 0 2006.201.10:09:24.59#ibcon#read 4, iclass 7, count 0 2006.201.10:09:24.59#ibcon#about to read 5, iclass 7, count 0 2006.201.10:09:24.59#ibcon#read 5, iclass 7, count 0 2006.201.10:09:24.59#ibcon#about to read 6, iclass 7, count 0 2006.201.10:09:24.59#ibcon#read 6, iclass 7, count 0 2006.201.10:09:24.59#ibcon#end of sib2, iclass 7, count 0 2006.201.10:09:24.59#ibcon#*mode == 0, iclass 7, count 0 2006.201.10:09:24.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.10:09:24.59#ibcon#[25=USB\r\n] 2006.201.10:09:24.59#ibcon#*before write, iclass 7, count 0 2006.201.10:09:24.59#ibcon#enter sib2, iclass 7, count 0 2006.201.10:09:24.59#ibcon#flushed, iclass 7, count 0 2006.201.10:09:24.59#ibcon#about to write, iclass 7, count 0 2006.201.10:09:24.59#ibcon#wrote, iclass 7, count 0 2006.201.10:09:24.59#ibcon#about to read 3, iclass 7, count 0 2006.201.10:09:24.62#ibcon#read 3, iclass 7, count 0 2006.201.10:09:24.62#ibcon#about to read 4, iclass 7, count 0 2006.201.10:09:24.62#ibcon#read 4, iclass 7, count 0 2006.201.10:09:24.62#ibcon#about to read 5, iclass 7, count 0 2006.201.10:09:24.62#ibcon#read 5, iclass 7, count 0 2006.201.10:09:24.62#ibcon#about to read 6, iclass 7, count 0 2006.201.10:09:24.62#ibcon#read 6, iclass 7, count 0 2006.201.10:09:24.62#ibcon#end of sib2, iclass 7, count 0 2006.201.10:09:24.62#ibcon#*after write, iclass 7, count 0 2006.201.10:09:24.62#ibcon#*before return 0, iclass 7, count 0 2006.201.10:09:24.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:09:24.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:09:24.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.10:09:24.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.10:09:24.62$vck44/vblo=1,629.99 2006.201.10:09:24.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.10:09:24.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.10:09:24.62#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:24.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:09:24.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:09:24.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:09:24.62#ibcon#enter wrdev, iclass 11, count 0 2006.201.10:09:24.62#ibcon#first serial, iclass 11, count 0 2006.201.10:09:24.62#ibcon#enter sib2, iclass 11, count 0 2006.201.10:09:24.62#ibcon#flushed, iclass 11, count 0 2006.201.10:09:24.62#ibcon#about to write, iclass 11, count 0 2006.201.10:09:24.62#ibcon#wrote, iclass 11, count 0 2006.201.10:09:24.62#ibcon#about to read 3, iclass 11, count 0 2006.201.10:09:24.64#ibcon#read 3, iclass 11, count 0 2006.201.10:09:24.64#ibcon#about to read 4, iclass 11, count 0 2006.201.10:09:24.64#ibcon#read 4, iclass 11, count 0 2006.201.10:09:24.64#ibcon#about to read 5, iclass 11, count 0 2006.201.10:09:24.64#ibcon#read 5, iclass 11, count 0 2006.201.10:09:24.64#ibcon#about to read 6, iclass 11, count 0 2006.201.10:09:24.64#ibcon#read 6, iclass 11, count 0 2006.201.10:09:24.64#ibcon#end of sib2, iclass 11, count 0 2006.201.10:09:24.64#ibcon#*mode == 0, iclass 11, count 0 2006.201.10:09:24.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.10:09:24.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:09:24.64#ibcon#*before write, iclass 11, count 0 2006.201.10:09:24.64#ibcon#enter sib2, iclass 11, count 0 2006.201.10:09:24.64#ibcon#flushed, iclass 11, count 0 2006.201.10:09:24.64#ibcon#about to write, iclass 11, count 0 2006.201.10:09:24.64#ibcon#wrote, iclass 11, count 0 2006.201.10:09:24.64#ibcon#about to read 3, iclass 11, count 0 2006.201.10:09:24.69#ibcon#read 3, iclass 11, count 0 2006.201.10:09:24.69#ibcon#about to read 4, iclass 11, count 0 2006.201.10:09:24.69#ibcon#read 4, iclass 11, count 0 2006.201.10:09:24.69#ibcon#about to read 5, iclass 11, count 0 2006.201.10:09:24.69#ibcon#read 5, iclass 11, count 0 2006.201.10:09:24.69#ibcon#about to read 6, iclass 11, count 0 2006.201.10:09:24.69#ibcon#read 6, iclass 11, count 0 2006.201.10:09:24.69#ibcon#end of sib2, iclass 11, count 0 2006.201.10:09:24.69#ibcon#*after write, iclass 11, count 0 2006.201.10:09:24.69#ibcon#*before return 0, iclass 11, count 0 2006.201.10:09:24.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:09:24.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:09:24.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.10:09:24.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.10:09:24.69$vck44/vb=1,4 2006.201.10:09:24.69#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.10:09:24.69#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.10:09:24.69#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:24.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:09:24.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:09:24.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:09:24.69#ibcon#enter wrdev, iclass 13, count 2 2006.201.10:09:24.69#ibcon#first serial, iclass 13, count 2 2006.201.10:09:24.69#ibcon#enter sib2, iclass 13, count 2 2006.201.10:09:24.69#ibcon#flushed, iclass 13, count 2 2006.201.10:09:24.69#ibcon#about to write, iclass 13, count 2 2006.201.10:09:24.69#ibcon#wrote, iclass 13, count 2 2006.201.10:09:24.69#ibcon#about to read 3, iclass 13, count 2 2006.201.10:09:24.71#ibcon#read 3, iclass 13, count 2 2006.201.10:09:24.71#ibcon#about to read 4, iclass 13, count 2 2006.201.10:09:24.71#ibcon#read 4, iclass 13, count 2 2006.201.10:09:24.71#ibcon#about to read 5, iclass 13, count 2 2006.201.10:09:24.71#ibcon#read 5, iclass 13, count 2 2006.201.10:09:24.71#ibcon#about to read 6, iclass 13, count 2 2006.201.10:09:24.71#ibcon#read 6, iclass 13, count 2 2006.201.10:09:24.71#ibcon#end of sib2, iclass 13, count 2 2006.201.10:09:24.71#ibcon#*mode == 0, iclass 13, count 2 2006.201.10:09:24.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.10:09:24.71#ibcon#[27=AT01-04\r\n] 2006.201.10:09:24.71#ibcon#*before write, iclass 13, count 2 2006.201.10:09:24.71#ibcon#enter sib2, iclass 13, count 2 2006.201.10:09:24.71#ibcon#flushed, iclass 13, count 2 2006.201.10:09:24.71#ibcon#about to write, iclass 13, count 2 2006.201.10:09:24.71#ibcon#wrote, iclass 13, count 2 2006.201.10:09:24.71#ibcon#about to read 3, iclass 13, count 2 2006.201.10:09:24.74#ibcon#read 3, iclass 13, count 2 2006.201.10:09:24.74#ibcon#about to read 4, iclass 13, count 2 2006.201.10:09:24.74#ibcon#read 4, iclass 13, count 2 2006.201.10:09:24.74#ibcon#about to read 5, iclass 13, count 2 2006.201.10:09:24.74#ibcon#read 5, iclass 13, count 2 2006.201.10:09:24.74#ibcon#about to read 6, iclass 13, count 2 2006.201.10:09:24.74#ibcon#read 6, iclass 13, count 2 2006.201.10:09:24.74#ibcon#end of sib2, iclass 13, count 2 2006.201.10:09:24.74#ibcon#*after write, iclass 13, count 2 2006.201.10:09:24.74#ibcon#*before return 0, iclass 13, count 2 2006.201.10:09:24.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:09:24.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:09:24.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.10:09:24.74#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:24.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:09:24.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:09:24.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:09:24.86#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:09:24.86#ibcon#first serial, iclass 13, count 0 2006.201.10:09:24.86#ibcon#enter sib2, iclass 13, count 0 2006.201.10:09:24.86#ibcon#flushed, iclass 13, count 0 2006.201.10:09:24.86#ibcon#about to write, iclass 13, count 0 2006.201.10:09:24.86#ibcon#wrote, iclass 13, count 0 2006.201.10:09:24.86#ibcon#about to read 3, iclass 13, count 0 2006.201.10:09:24.88#ibcon#read 3, iclass 13, count 0 2006.201.10:09:24.88#ibcon#about to read 4, iclass 13, count 0 2006.201.10:09:24.88#ibcon#read 4, iclass 13, count 0 2006.201.10:09:24.88#ibcon#about to read 5, iclass 13, count 0 2006.201.10:09:24.88#ibcon#read 5, iclass 13, count 0 2006.201.10:09:24.88#ibcon#about to read 6, iclass 13, count 0 2006.201.10:09:24.88#ibcon#read 6, iclass 13, count 0 2006.201.10:09:24.88#ibcon#end of sib2, iclass 13, count 0 2006.201.10:09:24.88#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:09:24.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:09:24.88#ibcon#[27=USB\r\n] 2006.201.10:09:24.88#ibcon#*before write, iclass 13, count 0 2006.201.10:09:24.88#ibcon#enter sib2, iclass 13, count 0 2006.201.10:09:24.88#ibcon#flushed, iclass 13, count 0 2006.201.10:09:24.88#ibcon#about to write, iclass 13, count 0 2006.201.10:09:24.88#ibcon#wrote, iclass 13, count 0 2006.201.10:09:24.88#ibcon#about to read 3, iclass 13, count 0 2006.201.10:09:24.91#ibcon#read 3, iclass 13, count 0 2006.201.10:09:24.91#ibcon#about to read 4, iclass 13, count 0 2006.201.10:09:24.91#ibcon#read 4, iclass 13, count 0 2006.201.10:09:24.91#ibcon#about to read 5, iclass 13, count 0 2006.201.10:09:24.91#ibcon#read 5, iclass 13, count 0 2006.201.10:09:24.91#ibcon#about to read 6, iclass 13, count 0 2006.201.10:09:24.91#ibcon#read 6, iclass 13, count 0 2006.201.10:09:24.91#ibcon#end of sib2, iclass 13, count 0 2006.201.10:09:24.91#ibcon#*after write, iclass 13, count 0 2006.201.10:09:24.91#ibcon#*before return 0, iclass 13, count 0 2006.201.10:09:24.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:09:24.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:09:24.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:09:24.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:09:24.91$vck44/vblo=2,634.99 2006.201.10:09:24.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.10:09:24.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.10:09:24.91#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:24.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:24.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:24.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:24.91#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:09:24.91#ibcon#first serial, iclass 15, count 0 2006.201.10:09:24.91#ibcon#enter sib2, iclass 15, count 0 2006.201.10:09:24.91#ibcon#flushed, iclass 15, count 0 2006.201.10:09:24.91#ibcon#about to write, iclass 15, count 0 2006.201.10:09:24.91#ibcon#wrote, iclass 15, count 0 2006.201.10:09:24.91#ibcon#about to read 3, iclass 15, count 0 2006.201.10:09:24.93#ibcon#read 3, iclass 15, count 0 2006.201.10:09:24.93#ibcon#about to read 4, iclass 15, count 0 2006.201.10:09:24.93#ibcon#read 4, iclass 15, count 0 2006.201.10:09:24.93#ibcon#about to read 5, iclass 15, count 0 2006.201.10:09:24.93#ibcon#read 5, iclass 15, count 0 2006.201.10:09:24.93#ibcon#about to read 6, iclass 15, count 0 2006.201.10:09:24.93#ibcon#read 6, iclass 15, count 0 2006.201.10:09:24.93#ibcon#end of sib2, iclass 15, count 0 2006.201.10:09:24.93#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:09:24.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:09:24.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:09:24.93#ibcon#*before write, iclass 15, count 0 2006.201.10:09:24.93#ibcon#enter sib2, iclass 15, count 0 2006.201.10:09:24.93#ibcon#flushed, iclass 15, count 0 2006.201.10:09:24.93#ibcon#about to write, iclass 15, count 0 2006.201.10:09:24.93#ibcon#wrote, iclass 15, count 0 2006.201.10:09:24.93#ibcon#about to read 3, iclass 15, count 0 2006.201.10:09:24.97#ibcon#read 3, iclass 15, count 0 2006.201.10:09:24.97#ibcon#about to read 4, iclass 15, count 0 2006.201.10:09:24.97#ibcon#read 4, iclass 15, count 0 2006.201.10:09:24.97#ibcon#about to read 5, iclass 15, count 0 2006.201.10:09:24.97#ibcon#read 5, iclass 15, count 0 2006.201.10:09:24.97#ibcon#about to read 6, iclass 15, count 0 2006.201.10:09:24.97#ibcon#read 6, iclass 15, count 0 2006.201.10:09:24.97#ibcon#end of sib2, iclass 15, count 0 2006.201.10:09:24.97#ibcon#*after write, iclass 15, count 0 2006.201.10:09:24.97#ibcon#*before return 0, iclass 15, count 0 2006.201.10:09:24.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:24.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:09:24.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:09:24.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:09:24.97$vck44/vb=2,5 2006.201.10:09:24.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.10:09:24.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.10:09:24.97#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:24.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:25.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:25.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:25.03#ibcon#enter wrdev, iclass 17, count 2 2006.201.10:09:25.03#ibcon#first serial, iclass 17, count 2 2006.201.10:09:25.03#ibcon#enter sib2, iclass 17, count 2 2006.201.10:09:25.03#ibcon#flushed, iclass 17, count 2 2006.201.10:09:25.03#ibcon#about to write, iclass 17, count 2 2006.201.10:09:25.03#ibcon#wrote, iclass 17, count 2 2006.201.10:09:25.03#ibcon#about to read 3, iclass 17, count 2 2006.201.10:09:25.05#ibcon#read 3, iclass 17, count 2 2006.201.10:09:25.05#ibcon#about to read 4, iclass 17, count 2 2006.201.10:09:25.05#ibcon#read 4, iclass 17, count 2 2006.201.10:09:25.05#ibcon#about to read 5, iclass 17, count 2 2006.201.10:09:25.05#ibcon#read 5, iclass 17, count 2 2006.201.10:09:25.05#ibcon#about to read 6, iclass 17, count 2 2006.201.10:09:25.05#ibcon#read 6, iclass 17, count 2 2006.201.10:09:25.05#ibcon#end of sib2, iclass 17, count 2 2006.201.10:09:25.05#ibcon#*mode == 0, iclass 17, count 2 2006.201.10:09:25.05#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.10:09:25.05#ibcon#[27=AT02-05\r\n] 2006.201.10:09:25.05#ibcon#*before write, iclass 17, count 2 2006.201.10:09:25.05#ibcon#enter sib2, iclass 17, count 2 2006.201.10:09:25.05#ibcon#flushed, iclass 17, count 2 2006.201.10:09:25.05#ibcon#about to write, iclass 17, count 2 2006.201.10:09:25.05#ibcon#wrote, iclass 17, count 2 2006.201.10:09:25.05#ibcon#about to read 3, iclass 17, count 2 2006.201.10:09:25.08#ibcon#read 3, iclass 17, count 2 2006.201.10:09:25.08#ibcon#about to read 4, iclass 17, count 2 2006.201.10:09:25.08#ibcon#read 4, iclass 17, count 2 2006.201.10:09:25.08#ibcon#about to read 5, iclass 17, count 2 2006.201.10:09:25.08#ibcon#read 5, iclass 17, count 2 2006.201.10:09:25.08#ibcon#about to read 6, iclass 17, count 2 2006.201.10:09:25.08#ibcon#read 6, iclass 17, count 2 2006.201.10:09:25.08#ibcon#end of sib2, iclass 17, count 2 2006.201.10:09:25.08#ibcon#*after write, iclass 17, count 2 2006.201.10:09:25.08#ibcon#*before return 0, iclass 17, count 2 2006.201.10:09:25.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:25.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:09:25.08#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.10:09:25.08#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:25.08#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:25.20#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:25.20#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:25.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:09:25.20#ibcon#first serial, iclass 17, count 0 2006.201.10:09:25.20#ibcon#enter sib2, iclass 17, count 0 2006.201.10:09:25.20#ibcon#flushed, iclass 17, count 0 2006.201.10:09:25.20#ibcon#about to write, iclass 17, count 0 2006.201.10:09:25.20#ibcon#wrote, iclass 17, count 0 2006.201.10:09:25.20#ibcon#about to read 3, iclass 17, count 0 2006.201.10:09:25.22#ibcon#read 3, iclass 17, count 0 2006.201.10:09:25.22#ibcon#about to read 4, iclass 17, count 0 2006.201.10:09:25.22#ibcon#read 4, iclass 17, count 0 2006.201.10:09:25.22#ibcon#about to read 5, iclass 17, count 0 2006.201.10:09:25.22#ibcon#read 5, iclass 17, count 0 2006.201.10:09:25.22#ibcon#about to read 6, iclass 17, count 0 2006.201.10:09:25.22#ibcon#read 6, iclass 17, count 0 2006.201.10:09:25.22#ibcon#end of sib2, iclass 17, count 0 2006.201.10:09:25.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:09:25.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:09:25.22#ibcon#[27=USB\r\n] 2006.201.10:09:25.22#ibcon#*before write, iclass 17, count 0 2006.201.10:09:25.22#ibcon#enter sib2, iclass 17, count 0 2006.201.10:09:25.22#ibcon#flushed, iclass 17, count 0 2006.201.10:09:25.22#ibcon#about to write, iclass 17, count 0 2006.201.10:09:25.22#ibcon#wrote, iclass 17, count 0 2006.201.10:09:25.22#ibcon#about to read 3, iclass 17, count 0 2006.201.10:09:25.25#ibcon#read 3, iclass 17, count 0 2006.201.10:09:25.25#ibcon#about to read 4, iclass 17, count 0 2006.201.10:09:25.25#ibcon#read 4, iclass 17, count 0 2006.201.10:09:25.25#ibcon#about to read 5, iclass 17, count 0 2006.201.10:09:25.25#ibcon#read 5, iclass 17, count 0 2006.201.10:09:25.25#ibcon#about to read 6, iclass 17, count 0 2006.201.10:09:25.25#ibcon#read 6, iclass 17, count 0 2006.201.10:09:25.25#ibcon#end of sib2, iclass 17, count 0 2006.201.10:09:25.25#ibcon#*after write, iclass 17, count 0 2006.201.10:09:25.25#ibcon#*before return 0, iclass 17, count 0 2006.201.10:09:25.25#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:25.25#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:09:25.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:09:25.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:09:25.25$vck44/vblo=3,649.99 2006.201.10:09:25.25#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.10:09:25.25#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.10:09:25.25#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:25.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:25.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:25.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:25.25#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:09:25.25#ibcon#first serial, iclass 19, count 0 2006.201.10:09:25.25#ibcon#enter sib2, iclass 19, count 0 2006.201.10:09:25.25#ibcon#flushed, iclass 19, count 0 2006.201.10:09:25.25#ibcon#about to write, iclass 19, count 0 2006.201.10:09:25.25#ibcon#wrote, iclass 19, count 0 2006.201.10:09:25.25#ibcon#about to read 3, iclass 19, count 0 2006.201.10:09:25.27#ibcon#read 3, iclass 19, count 0 2006.201.10:09:25.27#ibcon#about to read 4, iclass 19, count 0 2006.201.10:09:25.27#ibcon#read 4, iclass 19, count 0 2006.201.10:09:25.27#ibcon#about to read 5, iclass 19, count 0 2006.201.10:09:25.27#ibcon#read 5, iclass 19, count 0 2006.201.10:09:25.27#ibcon#about to read 6, iclass 19, count 0 2006.201.10:09:25.27#ibcon#read 6, iclass 19, count 0 2006.201.10:09:25.27#ibcon#end of sib2, iclass 19, count 0 2006.201.10:09:25.27#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:09:25.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:09:25.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:09:25.27#ibcon#*before write, iclass 19, count 0 2006.201.10:09:25.27#ibcon#enter sib2, iclass 19, count 0 2006.201.10:09:25.27#ibcon#flushed, iclass 19, count 0 2006.201.10:09:25.27#ibcon#about to write, iclass 19, count 0 2006.201.10:09:25.27#ibcon#wrote, iclass 19, count 0 2006.201.10:09:25.27#ibcon#about to read 3, iclass 19, count 0 2006.201.10:09:25.31#ibcon#read 3, iclass 19, count 0 2006.201.10:09:25.31#ibcon#about to read 4, iclass 19, count 0 2006.201.10:09:25.31#ibcon#read 4, iclass 19, count 0 2006.201.10:09:25.31#ibcon#about to read 5, iclass 19, count 0 2006.201.10:09:25.31#ibcon#read 5, iclass 19, count 0 2006.201.10:09:25.31#ibcon#about to read 6, iclass 19, count 0 2006.201.10:09:25.31#ibcon#read 6, iclass 19, count 0 2006.201.10:09:25.31#ibcon#end of sib2, iclass 19, count 0 2006.201.10:09:25.31#ibcon#*after write, iclass 19, count 0 2006.201.10:09:25.31#ibcon#*before return 0, iclass 19, count 0 2006.201.10:09:25.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:25.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:09:25.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:09:25.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:09:25.31$vck44/vb=3,4 2006.201.10:09:25.31#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.10:09:25.31#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.10:09:25.31#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:25.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:25.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:25.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:25.37#ibcon#enter wrdev, iclass 21, count 2 2006.201.10:09:25.37#ibcon#first serial, iclass 21, count 2 2006.201.10:09:25.37#ibcon#enter sib2, iclass 21, count 2 2006.201.10:09:25.37#ibcon#flushed, iclass 21, count 2 2006.201.10:09:25.37#ibcon#about to write, iclass 21, count 2 2006.201.10:09:25.37#ibcon#wrote, iclass 21, count 2 2006.201.10:09:25.37#ibcon#about to read 3, iclass 21, count 2 2006.201.10:09:25.39#ibcon#read 3, iclass 21, count 2 2006.201.10:09:25.39#ibcon#about to read 4, iclass 21, count 2 2006.201.10:09:25.39#ibcon#read 4, iclass 21, count 2 2006.201.10:09:25.39#ibcon#about to read 5, iclass 21, count 2 2006.201.10:09:25.39#ibcon#read 5, iclass 21, count 2 2006.201.10:09:25.39#ibcon#about to read 6, iclass 21, count 2 2006.201.10:09:25.39#ibcon#read 6, iclass 21, count 2 2006.201.10:09:25.39#ibcon#end of sib2, iclass 21, count 2 2006.201.10:09:25.39#ibcon#*mode == 0, iclass 21, count 2 2006.201.10:09:25.39#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.10:09:25.39#ibcon#[27=AT03-04\r\n] 2006.201.10:09:25.39#ibcon#*before write, iclass 21, count 2 2006.201.10:09:25.39#ibcon#enter sib2, iclass 21, count 2 2006.201.10:09:25.39#ibcon#flushed, iclass 21, count 2 2006.201.10:09:25.39#ibcon#about to write, iclass 21, count 2 2006.201.10:09:25.39#ibcon#wrote, iclass 21, count 2 2006.201.10:09:25.39#ibcon#about to read 3, iclass 21, count 2 2006.201.10:09:25.42#ibcon#read 3, iclass 21, count 2 2006.201.10:09:25.42#ibcon#about to read 4, iclass 21, count 2 2006.201.10:09:25.42#ibcon#read 4, iclass 21, count 2 2006.201.10:09:25.42#ibcon#about to read 5, iclass 21, count 2 2006.201.10:09:25.42#ibcon#read 5, iclass 21, count 2 2006.201.10:09:25.42#ibcon#about to read 6, iclass 21, count 2 2006.201.10:09:25.42#ibcon#read 6, iclass 21, count 2 2006.201.10:09:25.42#ibcon#end of sib2, iclass 21, count 2 2006.201.10:09:25.42#ibcon#*after write, iclass 21, count 2 2006.201.10:09:25.42#ibcon#*before return 0, iclass 21, count 2 2006.201.10:09:25.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:25.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:09:25.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.10:09:25.42#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:25.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:25.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:25.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:25.54#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:09:25.54#ibcon#first serial, iclass 21, count 0 2006.201.10:09:25.54#ibcon#enter sib2, iclass 21, count 0 2006.201.10:09:25.54#ibcon#flushed, iclass 21, count 0 2006.201.10:09:25.54#ibcon#about to write, iclass 21, count 0 2006.201.10:09:25.54#ibcon#wrote, iclass 21, count 0 2006.201.10:09:25.54#ibcon#about to read 3, iclass 21, count 0 2006.201.10:09:25.56#ibcon#read 3, iclass 21, count 0 2006.201.10:09:25.56#ibcon#about to read 4, iclass 21, count 0 2006.201.10:09:25.56#ibcon#read 4, iclass 21, count 0 2006.201.10:09:25.56#ibcon#about to read 5, iclass 21, count 0 2006.201.10:09:25.56#ibcon#read 5, iclass 21, count 0 2006.201.10:09:25.56#ibcon#about to read 6, iclass 21, count 0 2006.201.10:09:25.56#ibcon#read 6, iclass 21, count 0 2006.201.10:09:25.56#ibcon#end of sib2, iclass 21, count 0 2006.201.10:09:25.56#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:09:25.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:09:25.56#ibcon#[27=USB\r\n] 2006.201.10:09:25.56#ibcon#*before write, iclass 21, count 0 2006.201.10:09:25.56#ibcon#enter sib2, iclass 21, count 0 2006.201.10:09:25.56#ibcon#flushed, iclass 21, count 0 2006.201.10:09:25.56#ibcon#about to write, iclass 21, count 0 2006.201.10:09:25.56#ibcon#wrote, iclass 21, count 0 2006.201.10:09:25.56#ibcon#about to read 3, iclass 21, count 0 2006.201.10:09:25.59#ibcon#read 3, iclass 21, count 0 2006.201.10:09:25.59#ibcon#about to read 4, iclass 21, count 0 2006.201.10:09:25.59#ibcon#read 4, iclass 21, count 0 2006.201.10:09:25.59#ibcon#about to read 5, iclass 21, count 0 2006.201.10:09:25.59#ibcon#read 5, iclass 21, count 0 2006.201.10:09:25.59#ibcon#about to read 6, iclass 21, count 0 2006.201.10:09:25.59#ibcon#read 6, iclass 21, count 0 2006.201.10:09:25.59#ibcon#end of sib2, iclass 21, count 0 2006.201.10:09:25.59#ibcon#*after write, iclass 21, count 0 2006.201.10:09:25.59#ibcon#*before return 0, iclass 21, count 0 2006.201.10:09:25.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:25.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:09:25.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:09:25.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:09:25.59$vck44/vblo=4,679.99 2006.201.10:09:25.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.10:09:25.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.10:09:25.59#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:25.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:25.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:25.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:25.59#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:09:25.59#ibcon#first serial, iclass 23, count 0 2006.201.10:09:25.59#ibcon#enter sib2, iclass 23, count 0 2006.201.10:09:25.59#ibcon#flushed, iclass 23, count 0 2006.201.10:09:25.59#ibcon#about to write, iclass 23, count 0 2006.201.10:09:25.59#ibcon#wrote, iclass 23, count 0 2006.201.10:09:25.59#ibcon#about to read 3, iclass 23, count 0 2006.201.10:09:25.61#ibcon#read 3, iclass 23, count 0 2006.201.10:09:25.61#ibcon#about to read 4, iclass 23, count 0 2006.201.10:09:25.61#ibcon#read 4, iclass 23, count 0 2006.201.10:09:25.61#ibcon#about to read 5, iclass 23, count 0 2006.201.10:09:25.61#ibcon#read 5, iclass 23, count 0 2006.201.10:09:25.61#ibcon#about to read 6, iclass 23, count 0 2006.201.10:09:25.61#ibcon#read 6, iclass 23, count 0 2006.201.10:09:25.61#ibcon#end of sib2, iclass 23, count 0 2006.201.10:09:25.61#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:09:25.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:09:25.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:09:25.61#ibcon#*before write, iclass 23, count 0 2006.201.10:09:25.61#ibcon#enter sib2, iclass 23, count 0 2006.201.10:09:25.61#ibcon#flushed, iclass 23, count 0 2006.201.10:09:25.61#ibcon#about to write, iclass 23, count 0 2006.201.10:09:25.61#ibcon#wrote, iclass 23, count 0 2006.201.10:09:25.61#ibcon#about to read 3, iclass 23, count 0 2006.201.10:09:25.66#ibcon#read 3, iclass 23, count 0 2006.201.10:09:25.66#ibcon#about to read 4, iclass 23, count 0 2006.201.10:09:25.66#ibcon#read 4, iclass 23, count 0 2006.201.10:09:25.66#ibcon#about to read 5, iclass 23, count 0 2006.201.10:09:25.66#ibcon#read 5, iclass 23, count 0 2006.201.10:09:25.66#ibcon#about to read 6, iclass 23, count 0 2006.201.10:09:25.66#ibcon#read 6, iclass 23, count 0 2006.201.10:09:25.66#ibcon#end of sib2, iclass 23, count 0 2006.201.10:09:25.66#ibcon#*after write, iclass 23, count 0 2006.201.10:09:25.66#ibcon#*before return 0, iclass 23, count 0 2006.201.10:09:25.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:25.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:09:25.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:09:25.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:09:25.66$vck44/vb=4,5 2006.201.10:09:25.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.10:09:25.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.10:09:25.66#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:25.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:25.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:25.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:25.71#ibcon#enter wrdev, iclass 25, count 2 2006.201.10:09:25.71#ibcon#first serial, iclass 25, count 2 2006.201.10:09:25.71#ibcon#enter sib2, iclass 25, count 2 2006.201.10:09:25.71#ibcon#flushed, iclass 25, count 2 2006.201.10:09:25.71#ibcon#about to write, iclass 25, count 2 2006.201.10:09:25.71#ibcon#wrote, iclass 25, count 2 2006.201.10:09:25.71#ibcon#about to read 3, iclass 25, count 2 2006.201.10:09:25.73#ibcon#read 3, iclass 25, count 2 2006.201.10:09:25.73#ibcon#about to read 4, iclass 25, count 2 2006.201.10:09:25.73#ibcon#read 4, iclass 25, count 2 2006.201.10:09:25.73#ibcon#about to read 5, iclass 25, count 2 2006.201.10:09:25.73#ibcon#read 5, iclass 25, count 2 2006.201.10:09:25.73#ibcon#about to read 6, iclass 25, count 2 2006.201.10:09:25.73#ibcon#read 6, iclass 25, count 2 2006.201.10:09:25.73#ibcon#end of sib2, iclass 25, count 2 2006.201.10:09:25.73#ibcon#*mode == 0, iclass 25, count 2 2006.201.10:09:25.73#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.10:09:25.73#ibcon#[27=AT04-05\r\n] 2006.201.10:09:25.73#ibcon#*before write, iclass 25, count 2 2006.201.10:09:25.73#ibcon#enter sib2, iclass 25, count 2 2006.201.10:09:25.73#ibcon#flushed, iclass 25, count 2 2006.201.10:09:25.73#ibcon#about to write, iclass 25, count 2 2006.201.10:09:25.73#ibcon#wrote, iclass 25, count 2 2006.201.10:09:25.73#ibcon#about to read 3, iclass 25, count 2 2006.201.10:09:25.76#ibcon#read 3, iclass 25, count 2 2006.201.10:09:25.76#ibcon#about to read 4, iclass 25, count 2 2006.201.10:09:25.76#ibcon#read 4, iclass 25, count 2 2006.201.10:09:25.76#ibcon#about to read 5, iclass 25, count 2 2006.201.10:09:25.76#ibcon#read 5, iclass 25, count 2 2006.201.10:09:25.76#ibcon#about to read 6, iclass 25, count 2 2006.201.10:09:25.76#ibcon#read 6, iclass 25, count 2 2006.201.10:09:25.76#ibcon#end of sib2, iclass 25, count 2 2006.201.10:09:25.76#ibcon#*after write, iclass 25, count 2 2006.201.10:09:25.76#ibcon#*before return 0, iclass 25, count 2 2006.201.10:09:25.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:25.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:09:25.76#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.10:09:25.76#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:25.76#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:25.88#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:25.88#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:25.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:09:25.88#ibcon#first serial, iclass 25, count 0 2006.201.10:09:25.88#ibcon#enter sib2, iclass 25, count 0 2006.201.10:09:25.88#ibcon#flushed, iclass 25, count 0 2006.201.10:09:25.88#ibcon#about to write, iclass 25, count 0 2006.201.10:09:25.88#ibcon#wrote, iclass 25, count 0 2006.201.10:09:25.88#ibcon#about to read 3, iclass 25, count 0 2006.201.10:09:25.90#ibcon#read 3, iclass 25, count 0 2006.201.10:09:25.90#ibcon#about to read 4, iclass 25, count 0 2006.201.10:09:25.90#ibcon#read 4, iclass 25, count 0 2006.201.10:09:25.90#ibcon#about to read 5, iclass 25, count 0 2006.201.10:09:25.90#ibcon#read 5, iclass 25, count 0 2006.201.10:09:25.90#ibcon#about to read 6, iclass 25, count 0 2006.201.10:09:25.90#ibcon#read 6, iclass 25, count 0 2006.201.10:09:25.90#ibcon#end of sib2, iclass 25, count 0 2006.201.10:09:25.90#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:09:25.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:09:25.90#ibcon#[27=USB\r\n] 2006.201.10:09:25.90#ibcon#*before write, iclass 25, count 0 2006.201.10:09:25.90#ibcon#enter sib2, iclass 25, count 0 2006.201.10:09:25.90#ibcon#flushed, iclass 25, count 0 2006.201.10:09:25.90#ibcon#about to write, iclass 25, count 0 2006.201.10:09:25.90#ibcon#wrote, iclass 25, count 0 2006.201.10:09:25.90#ibcon#about to read 3, iclass 25, count 0 2006.201.10:09:25.93#ibcon#read 3, iclass 25, count 0 2006.201.10:09:25.93#ibcon#about to read 4, iclass 25, count 0 2006.201.10:09:25.93#ibcon#read 4, iclass 25, count 0 2006.201.10:09:25.93#ibcon#about to read 5, iclass 25, count 0 2006.201.10:09:25.93#ibcon#read 5, iclass 25, count 0 2006.201.10:09:25.93#ibcon#about to read 6, iclass 25, count 0 2006.201.10:09:25.93#ibcon#read 6, iclass 25, count 0 2006.201.10:09:25.93#ibcon#end of sib2, iclass 25, count 0 2006.201.10:09:25.93#ibcon#*after write, iclass 25, count 0 2006.201.10:09:25.93#ibcon#*before return 0, iclass 25, count 0 2006.201.10:09:25.93#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:25.93#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:09:25.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:09:25.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:09:25.93$vck44/vblo=5,709.99 2006.201.10:09:25.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.10:09:25.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.10:09:25.93#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:25.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:25.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:25.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:25.93#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:09:25.93#ibcon#first serial, iclass 27, count 0 2006.201.10:09:25.93#ibcon#enter sib2, iclass 27, count 0 2006.201.10:09:25.93#ibcon#flushed, iclass 27, count 0 2006.201.10:09:25.93#ibcon#about to write, iclass 27, count 0 2006.201.10:09:25.93#ibcon#wrote, iclass 27, count 0 2006.201.10:09:25.93#ibcon#about to read 3, iclass 27, count 0 2006.201.10:09:25.95#ibcon#read 3, iclass 27, count 0 2006.201.10:09:25.95#ibcon#about to read 4, iclass 27, count 0 2006.201.10:09:25.95#ibcon#read 4, iclass 27, count 0 2006.201.10:09:25.95#ibcon#about to read 5, iclass 27, count 0 2006.201.10:09:25.95#ibcon#read 5, iclass 27, count 0 2006.201.10:09:25.95#ibcon#about to read 6, iclass 27, count 0 2006.201.10:09:25.95#ibcon#read 6, iclass 27, count 0 2006.201.10:09:25.95#ibcon#end of sib2, iclass 27, count 0 2006.201.10:09:25.95#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:09:25.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:09:25.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:09:25.95#ibcon#*before write, iclass 27, count 0 2006.201.10:09:25.95#ibcon#enter sib2, iclass 27, count 0 2006.201.10:09:25.95#ibcon#flushed, iclass 27, count 0 2006.201.10:09:25.95#ibcon#about to write, iclass 27, count 0 2006.201.10:09:25.95#ibcon#wrote, iclass 27, count 0 2006.201.10:09:25.95#ibcon#about to read 3, iclass 27, count 0 2006.201.10:09:25.99#ibcon#read 3, iclass 27, count 0 2006.201.10:09:25.99#ibcon#about to read 4, iclass 27, count 0 2006.201.10:09:25.99#ibcon#read 4, iclass 27, count 0 2006.201.10:09:25.99#ibcon#about to read 5, iclass 27, count 0 2006.201.10:09:25.99#ibcon#read 5, iclass 27, count 0 2006.201.10:09:25.99#ibcon#about to read 6, iclass 27, count 0 2006.201.10:09:25.99#ibcon#read 6, iclass 27, count 0 2006.201.10:09:25.99#ibcon#end of sib2, iclass 27, count 0 2006.201.10:09:25.99#ibcon#*after write, iclass 27, count 0 2006.201.10:09:25.99#ibcon#*before return 0, iclass 27, count 0 2006.201.10:09:25.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:25.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:09:25.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:09:25.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:09:25.99$vck44/vb=5,4 2006.201.10:09:25.99#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.10:09:25.99#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.10:09:25.99#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:25.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:26.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:26.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:26.05#ibcon#enter wrdev, iclass 29, count 2 2006.201.10:09:26.05#ibcon#first serial, iclass 29, count 2 2006.201.10:09:26.05#ibcon#enter sib2, iclass 29, count 2 2006.201.10:09:26.05#ibcon#flushed, iclass 29, count 2 2006.201.10:09:26.05#ibcon#about to write, iclass 29, count 2 2006.201.10:09:26.05#ibcon#wrote, iclass 29, count 2 2006.201.10:09:26.05#ibcon#about to read 3, iclass 29, count 2 2006.201.10:09:26.07#ibcon#read 3, iclass 29, count 2 2006.201.10:09:26.07#ibcon#about to read 4, iclass 29, count 2 2006.201.10:09:26.07#ibcon#read 4, iclass 29, count 2 2006.201.10:09:26.07#ibcon#about to read 5, iclass 29, count 2 2006.201.10:09:26.07#ibcon#read 5, iclass 29, count 2 2006.201.10:09:26.07#ibcon#about to read 6, iclass 29, count 2 2006.201.10:09:26.07#ibcon#read 6, iclass 29, count 2 2006.201.10:09:26.07#ibcon#end of sib2, iclass 29, count 2 2006.201.10:09:26.07#ibcon#*mode == 0, iclass 29, count 2 2006.201.10:09:26.07#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.10:09:26.07#ibcon#[27=AT05-04\r\n] 2006.201.10:09:26.07#ibcon#*before write, iclass 29, count 2 2006.201.10:09:26.07#ibcon#enter sib2, iclass 29, count 2 2006.201.10:09:26.07#ibcon#flushed, iclass 29, count 2 2006.201.10:09:26.07#ibcon#about to write, iclass 29, count 2 2006.201.10:09:26.07#ibcon#wrote, iclass 29, count 2 2006.201.10:09:26.07#ibcon#about to read 3, iclass 29, count 2 2006.201.10:09:26.10#ibcon#read 3, iclass 29, count 2 2006.201.10:09:26.10#ibcon#about to read 4, iclass 29, count 2 2006.201.10:09:26.10#ibcon#read 4, iclass 29, count 2 2006.201.10:09:26.10#ibcon#about to read 5, iclass 29, count 2 2006.201.10:09:26.10#ibcon#read 5, iclass 29, count 2 2006.201.10:09:26.10#ibcon#about to read 6, iclass 29, count 2 2006.201.10:09:26.10#ibcon#read 6, iclass 29, count 2 2006.201.10:09:26.10#ibcon#end of sib2, iclass 29, count 2 2006.201.10:09:26.10#ibcon#*after write, iclass 29, count 2 2006.201.10:09:26.10#ibcon#*before return 0, iclass 29, count 2 2006.201.10:09:26.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:26.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:09:26.10#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.10:09:26.10#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:26.10#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:26.22#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:26.22#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:26.22#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:09:26.22#ibcon#first serial, iclass 29, count 0 2006.201.10:09:26.22#ibcon#enter sib2, iclass 29, count 0 2006.201.10:09:26.22#ibcon#flushed, iclass 29, count 0 2006.201.10:09:26.22#ibcon#about to write, iclass 29, count 0 2006.201.10:09:26.22#ibcon#wrote, iclass 29, count 0 2006.201.10:09:26.22#ibcon#about to read 3, iclass 29, count 0 2006.201.10:09:26.24#ibcon#read 3, iclass 29, count 0 2006.201.10:09:26.24#ibcon#about to read 4, iclass 29, count 0 2006.201.10:09:26.24#ibcon#read 4, iclass 29, count 0 2006.201.10:09:26.24#ibcon#about to read 5, iclass 29, count 0 2006.201.10:09:26.24#ibcon#read 5, iclass 29, count 0 2006.201.10:09:26.24#ibcon#about to read 6, iclass 29, count 0 2006.201.10:09:26.24#ibcon#read 6, iclass 29, count 0 2006.201.10:09:26.24#ibcon#end of sib2, iclass 29, count 0 2006.201.10:09:26.24#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:09:26.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:09:26.24#ibcon#[27=USB\r\n] 2006.201.10:09:26.24#ibcon#*before write, iclass 29, count 0 2006.201.10:09:26.24#ibcon#enter sib2, iclass 29, count 0 2006.201.10:09:26.24#ibcon#flushed, iclass 29, count 0 2006.201.10:09:26.24#ibcon#about to write, iclass 29, count 0 2006.201.10:09:26.24#ibcon#wrote, iclass 29, count 0 2006.201.10:09:26.24#ibcon#about to read 3, iclass 29, count 0 2006.201.10:09:26.27#ibcon#read 3, iclass 29, count 0 2006.201.10:09:26.27#ibcon#about to read 4, iclass 29, count 0 2006.201.10:09:26.27#ibcon#read 4, iclass 29, count 0 2006.201.10:09:26.27#ibcon#about to read 5, iclass 29, count 0 2006.201.10:09:26.27#ibcon#read 5, iclass 29, count 0 2006.201.10:09:26.27#ibcon#about to read 6, iclass 29, count 0 2006.201.10:09:26.27#ibcon#read 6, iclass 29, count 0 2006.201.10:09:26.27#ibcon#end of sib2, iclass 29, count 0 2006.201.10:09:26.27#ibcon#*after write, iclass 29, count 0 2006.201.10:09:26.27#ibcon#*before return 0, iclass 29, count 0 2006.201.10:09:26.27#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:26.27#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:09:26.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:09:26.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:09:26.27$vck44/vblo=6,719.99 2006.201.10:09:26.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.10:09:26.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.10:09:26.27#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:26.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:26.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:26.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:26.27#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:09:26.27#ibcon#first serial, iclass 31, count 0 2006.201.10:09:26.27#ibcon#enter sib2, iclass 31, count 0 2006.201.10:09:26.27#ibcon#flushed, iclass 31, count 0 2006.201.10:09:26.27#ibcon#about to write, iclass 31, count 0 2006.201.10:09:26.27#ibcon#wrote, iclass 31, count 0 2006.201.10:09:26.27#ibcon#about to read 3, iclass 31, count 0 2006.201.10:09:26.29#ibcon#read 3, iclass 31, count 0 2006.201.10:09:26.29#ibcon#about to read 4, iclass 31, count 0 2006.201.10:09:26.29#ibcon#read 4, iclass 31, count 0 2006.201.10:09:26.29#ibcon#about to read 5, iclass 31, count 0 2006.201.10:09:26.29#ibcon#read 5, iclass 31, count 0 2006.201.10:09:26.29#ibcon#about to read 6, iclass 31, count 0 2006.201.10:09:26.29#ibcon#read 6, iclass 31, count 0 2006.201.10:09:26.29#ibcon#end of sib2, iclass 31, count 0 2006.201.10:09:26.29#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:09:26.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:09:26.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:09:26.29#ibcon#*before write, iclass 31, count 0 2006.201.10:09:26.29#ibcon#enter sib2, iclass 31, count 0 2006.201.10:09:26.29#ibcon#flushed, iclass 31, count 0 2006.201.10:09:26.29#ibcon#about to write, iclass 31, count 0 2006.201.10:09:26.29#ibcon#wrote, iclass 31, count 0 2006.201.10:09:26.29#ibcon#about to read 3, iclass 31, count 0 2006.201.10:09:26.33#ibcon#read 3, iclass 31, count 0 2006.201.10:09:26.33#ibcon#about to read 4, iclass 31, count 0 2006.201.10:09:26.33#ibcon#read 4, iclass 31, count 0 2006.201.10:09:26.33#ibcon#about to read 5, iclass 31, count 0 2006.201.10:09:26.33#ibcon#read 5, iclass 31, count 0 2006.201.10:09:26.33#ibcon#about to read 6, iclass 31, count 0 2006.201.10:09:26.33#ibcon#read 6, iclass 31, count 0 2006.201.10:09:26.33#ibcon#end of sib2, iclass 31, count 0 2006.201.10:09:26.33#ibcon#*after write, iclass 31, count 0 2006.201.10:09:26.33#ibcon#*before return 0, iclass 31, count 0 2006.201.10:09:26.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:26.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:09:26.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:09:26.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:09:26.33$vck44/vb=6,4 2006.201.10:09:26.33#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.10:09:26.33#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.10:09:26.33#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:26.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:26.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:26.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:26.39#ibcon#enter wrdev, iclass 33, count 2 2006.201.10:09:26.39#ibcon#first serial, iclass 33, count 2 2006.201.10:09:26.39#ibcon#enter sib2, iclass 33, count 2 2006.201.10:09:26.39#ibcon#flushed, iclass 33, count 2 2006.201.10:09:26.39#ibcon#about to write, iclass 33, count 2 2006.201.10:09:26.39#ibcon#wrote, iclass 33, count 2 2006.201.10:09:26.39#ibcon#about to read 3, iclass 33, count 2 2006.201.10:09:26.41#ibcon#read 3, iclass 33, count 2 2006.201.10:09:26.41#ibcon#about to read 4, iclass 33, count 2 2006.201.10:09:26.41#ibcon#read 4, iclass 33, count 2 2006.201.10:09:26.41#ibcon#about to read 5, iclass 33, count 2 2006.201.10:09:26.41#ibcon#read 5, iclass 33, count 2 2006.201.10:09:26.41#ibcon#about to read 6, iclass 33, count 2 2006.201.10:09:26.41#ibcon#read 6, iclass 33, count 2 2006.201.10:09:26.41#ibcon#end of sib2, iclass 33, count 2 2006.201.10:09:26.41#ibcon#*mode == 0, iclass 33, count 2 2006.201.10:09:26.41#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.10:09:26.41#ibcon#[27=AT06-04\r\n] 2006.201.10:09:26.41#ibcon#*before write, iclass 33, count 2 2006.201.10:09:26.41#ibcon#enter sib2, iclass 33, count 2 2006.201.10:09:26.41#ibcon#flushed, iclass 33, count 2 2006.201.10:09:26.41#ibcon#about to write, iclass 33, count 2 2006.201.10:09:26.41#ibcon#wrote, iclass 33, count 2 2006.201.10:09:26.41#ibcon#about to read 3, iclass 33, count 2 2006.201.10:09:26.44#ibcon#read 3, iclass 33, count 2 2006.201.10:09:26.44#ibcon#about to read 4, iclass 33, count 2 2006.201.10:09:26.44#ibcon#read 4, iclass 33, count 2 2006.201.10:09:26.44#ibcon#about to read 5, iclass 33, count 2 2006.201.10:09:26.44#ibcon#read 5, iclass 33, count 2 2006.201.10:09:26.44#ibcon#about to read 6, iclass 33, count 2 2006.201.10:09:26.44#ibcon#read 6, iclass 33, count 2 2006.201.10:09:26.44#ibcon#end of sib2, iclass 33, count 2 2006.201.10:09:26.44#ibcon#*after write, iclass 33, count 2 2006.201.10:09:26.44#ibcon#*before return 0, iclass 33, count 2 2006.201.10:09:26.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:26.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:09:26.44#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.10:09:26.44#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:26.44#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:26.56#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:26.56#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:26.56#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:09:26.56#ibcon#first serial, iclass 33, count 0 2006.201.10:09:26.56#ibcon#enter sib2, iclass 33, count 0 2006.201.10:09:26.56#ibcon#flushed, iclass 33, count 0 2006.201.10:09:26.56#ibcon#about to write, iclass 33, count 0 2006.201.10:09:26.56#ibcon#wrote, iclass 33, count 0 2006.201.10:09:26.56#ibcon#about to read 3, iclass 33, count 0 2006.201.10:09:26.58#ibcon#read 3, iclass 33, count 0 2006.201.10:09:26.58#ibcon#about to read 4, iclass 33, count 0 2006.201.10:09:26.58#ibcon#read 4, iclass 33, count 0 2006.201.10:09:26.58#ibcon#about to read 5, iclass 33, count 0 2006.201.10:09:26.58#ibcon#read 5, iclass 33, count 0 2006.201.10:09:26.58#ibcon#about to read 6, iclass 33, count 0 2006.201.10:09:26.58#ibcon#read 6, iclass 33, count 0 2006.201.10:09:26.58#ibcon#end of sib2, iclass 33, count 0 2006.201.10:09:26.58#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:09:26.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:09:26.58#ibcon#[27=USB\r\n] 2006.201.10:09:26.58#ibcon#*before write, iclass 33, count 0 2006.201.10:09:26.58#ibcon#enter sib2, iclass 33, count 0 2006.201.10:09:26.58#ibcon#flushed, iclass 33, count 0 2006.201.10:09:26.58#ibcon#about to write, iclass 33, count 0 2006.201.10:09:26.58#ibcon#wrote, iclass 33, count 0 2006.201.10:09:26.58#ibcon#about to read 3, iclass 33, count 0 2006.201.10:09:26.61#ibcon#read 3, iclass 33, count 0 2006.201.10:09:26.61#ibcon#about to read 4, iclass 33, count 0 2006.201.10:09:26.61#ibcon#read 4, iclass 33, count 0 2006.201.10:09:26.61#ibcon#about to read 5, iclass 33, count 0 2006.201.10:09:26.61#ibcon#read 5, iclass 33, count 0 2006.201.10:09:26.61#ibcon#about to read 6, iclass 33, count 0 2006.201.10:09:26.61#ibcon#read 6, iclass 33, count 0 2006.201.10:09:26.61#ibcon#end of sib2, iclass 33, count 0 2006.201.10:09:26.61#ibcon#*after write, iclass 33, count 0 2006.201.10:09:26.61#ibcon#*before return 0, iclass 33, count 0 2006.201.10:09:26.61#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:26.61#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:09:26.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:09:26.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:09:26.61$vck44/vblo=7,734.99 2006.201.10:09:26.61#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.10:09:26.61#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.10:09:26.61#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:26.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:26.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:26.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:26.61#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:09:26.61#ibcon#first serial, iclass 35, count 0 2006.201.10:09:26.61#ibcon#enter sib2, iclass 35, count 0 2006.201.10:09:26.61#ibcon#flushed, iclass 35, count 0 2006.201.10:09:26.61#ibcon#about to write, iclass 35, count 0 2006.201.10:09:26.61#ibcon#wrote, iclass 35, count 0 2006.201.10:09:26.61#ibcon#about to read 3, iclass 35, count 0 2006.201.10:09:26.63#ibcon#read 3, iclass 35, count 0 2006.201.10:09:26.63#ibcon#about to read 4, iclass 35, count 0 2006.201.10:09:26.63#ibcon#read 4, iclass 35, count 0 2006.201.10:09:26.63#ibcon#about to read 5, iclass 35, count 0 2006.201.10:09:26.63#ibcon#read 5, iclass 35, count 0 2006.201.10:09:26.63#ibcon#about to read 6, iclass 35, count 0 2006.201.10:09:26.63#ibcon#read 6, iclass 35, count 0 2006.201.10:09:26.63#ibcon#end of sib2, iclass 35, count 0 2006.201.10:09:26.63#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:09:26.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:09:26.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:09:26.63#ibcon#*before write, iclass 35, count 0 2006.201.10:09:26.63#ibcon#enter sib2, iclass 35, count 0 2006.201.10:09:26.63#ibcon#flushed, iclass 35, count 0 2006.201.10:09:26.63#ibcon#about to write, iclass 35, count 0 2006.201.10:09:26.63#ibcon#wrote, iclass 35, count 0 2006.201.10:09:26.63#ibcon#about to read 3, iclass 35, count 0 2006.201.10:09:26.67#ibcon#read 3, iclass 35, count 0 2006.201.10:09:26.67#ibcon#about to read 4, iclass 35, count 0 2006.201.10:09:26.67#ibcon#read 4, iclass 35, count 0 2006.201.10:09:26.67#ibcon#about to read 5, iclass 35, count 0 2006.201.10:09:26.67#ibcon#read 5, iclass 35, count 0 2006.201.10:09:26.67#ibcon#about to read 6, iclass 35, count 0 2006.201.10:09:26.67#ibcon#read 6, iclass 35, count 0 2006.201.10:09:26.67#ibcon#end of sib2, iclass 35, count 0 2006.201.10:09:26.67#ibcon#*after write, iclass 35, count 0 2006.201.10:09:26.67#ibcon#*before return 0, iclass 35, count 0 2006.201.10:09:26.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:26.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:09:26.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:09:26.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:09:26.67$vck44/vb=7,4 2006.201.10:09:26.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.10:09:26.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.10:09:26.67#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:26.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:26.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:26.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:26.73#ibcon#enter wrdev, iclass 37, count 2 2006.201.10:09:26.73#ibcon#first serial, iclass 37, count 2 2006.201.10:09:26.73#ibcon#enter sib2, iclass 37, count 2 2006.201.10:09:26.73#ibcon#flushed, iclass 37, count 2 2006.201.10:09:26.73#ibcon#about to write, iclass 37, count 2 2006.201.10:09:26.73#ibcon#wrote, iclass 37, count 2 2006.201.10:09:26.73#ibcon#about to read 3, iclass 37, count 2 2006.201.10:09:26.75#ibcon#read 3, iclass 37, count 2 2006.201.10:09:26.75#ibcon#about to read 4, iclass 37, count 2 2006.201.10:09:26.75#ibcon#read 4, iclass 37, count 2 2006.201.10:09:26.75#ibcon#about to read 5, iclass 37, count 2 2006.201.10:09:26.75#ibcon#read 5, iclass 37, count 2 2006.201.10:09:26.75#ibcon#about to read 6, iclass 37, count 2 2006.201.10:09:26.75#ibcon#read 6, iclass 37, count 2 2006.201.10:09:26.75#ibcon#end of sib2, iclass 37, count 2 2006.201.10:09:26.75#ibcon#*mode == 0, iclass 37, count 2 2006.201.10:09:26.75#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.10:09:26.75#ibcon#[27=AT07-04\r\n] 2006.201.10:09:26.75#ibcon#*before write, iclass 37, count 2 2006.201.10:09:26.75#ibcon#enter sib2, iclass 37, count 2 2006.201.10:09:26.75#ibcon#flushed, iclass 37, count 2 2006.201.10:09:26.75#ibcon#about to write, iclass 37, count 2 2006.201.10:09:26.75#ibcon#wrote, iclass 37, count 2 2006.201.10:09:26.75#ibcon#about to read 3, iclass 37, count 2 2006.201.10:09:26.78#ibcon#read 3, iclass 37, count 2 2006.201.10:09:26.78#ibcon#about to read 4, iclass 37, count 2 2006.201.10:09:26.78#ibcon#read 4, iclass 37, count 2 2006.201.10:09:26.78#ibcon#about to read 5, iclass 37, count 2 2006.201.10:09:26.78#ibcon#read 5, iclass 37, count 2 2006.201.10:09:26.78#ibcon#about to read 6, iclass 37, count 2 2006.201.10:09:26.78#ibcon#read 6, iclass 37, count 2 2006.201.10:09:26.78#ibcon#end of sib2, iclass 37, count 2 2006.201.10:09:26.78#ibcon#*after write, iclass 37, count 2 2006.201.10:09:26.78#ibcon#*before return 0, iclass 37, count 2 2006.201.10:09:26.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:26.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:09:26.78#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.10:09:26.78#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:26.78#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:26.90#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:26.90#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:26.90#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:09:26.90#ibcon#first serial, iclass 37, count 0 2006.201.10:09:26.90#ibcon#enter sib2, iclass 37, count 0 2006.201.10:09:26.90#ibcon#flushed, iclass 37, count 0 2006.201.10:09:26.90#ibcon#about to write, iclass 37, count 0 2006.201.10:09:26.90#ibcon#wrote, iclass 37, count 0 2006.201.10:09:26.90#ibcon#about to read 3, iclass 37, count 0 2006.201.10:09:26.92#ibcon#read 3, iclass 37, count 0 2006.201.10:09:26.92#ibcon#about to read 4, iclass 37, count 0 2006.201.10:09:26.92#ibcon#read 4, iclass 37, count 0 2006.201.10:09:26.92#ibcon#about to read 5, iclass 37, count 0 2006.201.10:09:26.92#ibcon#read 5, iclass 37, count 0 2006.201.10:09:26.92#ibcon#about to read 6, iclass 37, count 0 2006.201.10:09:26.92#ibcon#read 6, iclass 37, count 0 2006.201.10:09:26.92#ibcon#end of sib2, iclass 37, count 0 2006.201.10:09:26.92#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:09:26.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:09:26.92#ibcon#[27=USB\r\n] 2006.201.10:09:26.92#ibcon#*before write, iclass 37, count 0 2006.201.10:09:26.92#ibcon#enter sib2, iclass 37, count 0 2006.201.10:09:26.92#ibcon#flushed, iclass 37, count 0 2006.201.10:09:26.92#ibcon#about to write, iclass 37, count 0 2006.201.10:09:26.92#ibcon#wrote, iclass 37, count 0 2006.201.10:09:26.92#ibcon#about to read 3, iclass 37, count 0 2006.201.10:09:26.95#ibcon#read 3, iclass 37, count 0 2006.201.10:09:26.95#ibcon#about to read 4, iclass 37, count 0 2006.201.10:09:26.95#ibcon#read 4, iclass 37, count 0 2006.201.10:09:26.95#ibcon#about to read 5, iclass 37, count 0 2006.201.10:09:26.95#ibcon#read 5, iclass 37, count 0 2006.201.10:09:26.95#ibcon#about to read 6, iclass 37, count 0 2006.201.10:09:26.95#ibcon#read 6, iclass 37, count 0 2006.201.10:09:26.95#ibcon#end of sib2, iclass 37, count 0 2006.201.10:09:26.95#ibcon#*after write, iclass 37, count 0 2006.201.10:09:26.95#ibcon#*before return 0, iclass 37, count 0 2006.201.10:09:26.95#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:26.95#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:09:26.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:09:26.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:09:26.95$vck44/vblo=8,744.99 2006.201.10:09:26.95#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.10:09:26.95#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.10:09:26.95#ibcon#ireg 17 cls_cnt 0 2006.201.10:09:26.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:26.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:26.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:26.95#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:09:26.95#ibcon#first serial, iclass 39, count 0 2006.201.10:09:26.95#ibcon#enter sib2, iclass 39, count 0 2006.201.10:09:26.95#ibcon#flushed, iclass 39, count 0 2006.201.10:09:26.95#ibcon#about to write, iclass 39, count 0 2006.201.10:09:26.95#ibcon#wrote, iclass 39, count 0 2006.201.10:09:26.95#ibcon#about to read 3, iclass 39, count 0 2006.201.10:09:26.97#ibcon#read 3, iclass 39, count 0 2006.201.10:09:26.97#ibcon#about to read 4, iclass 39, count 0 2006.201.10:09:26.97#ibcon#read 4, iclass 39, count 0 2006.201.10:09:26.97#ibcon#about to read 5, iclass 39, count 0 2006.201.10:09:26.97#ibcon#read 5, iclass 39, count 0 2006.201.10:09:26.97#ibcon#about to read 6, iclass 39, count 0 2006.201.10:09:26.97#ibcon#read 6, iclass 39, count 0 2006.201.10:09:26.97#ibcon#end of sib2, iclass 39, count 0 2006.201.10:09:26.97#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:09:26.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:09:26.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:09:26.97#ibcon#*before write, iclass 39, count 0 2006.201.10:09:26.97#ibcon#enter sib2, iclass 39, count 0 2006.201.10:09:26.97#ibcon#flushed, iclass 39, count 0 2006.201.10:09:26.97#ibcon#about to write, iclass 39, count 0 2006.201.10:09:26.97#ibcon#wrote, iclass 39, count 0 2006.201.10:09:26.97#ibcon#about to read 3, iclass 39, count 0 2006.201.10:09:27.01#ibcon#read 3, iclass 39, count 0 2006.201.10:09:27.01#ibcon#about to read 4, iclass 39, count 0 2006.201.10:09:27.01#ibcon#read 4, iclass 39, count 0 2006.201.10:09:27.01#ibcon#about to read 5, iclass 39, count 0 2006.201.10:09:27.01#ibcon#read 5, iclass 39, count 0 2006.201.10:09:27.01#ibcon#about to read 6, iclass 39, count 0 2006.201.10:09:27.01#ibcon#read 6, iclass 39, count 0 2006.201.10:09:27.01#ibcon#end of sib2, iclass 39, count 0 2006.201.10:09:27.01#ibcon#*after write, iclass 39, count 0 2006.201.10:09:27.01#ibcon#*before return 0, iclass 39, count 0 2006.201.10:09:27.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:27.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:09:27.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:09:27.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:09:27.01$vck44/vb=8,4 2006.201.10:09:27.01#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.10:09:27.01#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.10:09:27.01#ibcon#ireg 11 cls_cnt 2 2006.201.10:09:27.01#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:27.07#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:27.07#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:27.07#ibcon#enter wrdev, iclass 2, count 2 2006.201.10:09:27.07#ibcon#first serial, iclass 2, count 2 2006.201.10:09:27.07#ibcon#enter sib2, iclass 2, count 2 2006.201.10:09:27.07#ibcon#flushed, iclass 2, count 2 2006.201.10:09:27.07#ibcon#about to write, iclass 2, count 2 2006.201.10:09:27.07#ibcon#wrote, iclass 2, count 2 2006.201.10:09:27.07#ibcon#about to read 3, iclass 2, count 2 2006.201.10:09:27.09#ibcon#read 3, iclass 2, count 2 2006.201.10:09:27.09#ibcon#about to read 4, iclass 2, count 2 2006.201.10:09:27.09#ibcon#read 4, iclass 2, count 2 2006.201.10:09:27.09#ibcon#about to read 5, iclass 2, count 2 2006.201.10:09:27.09#ibcon#read 5, iclass 2, count 2 2006.201.10:09:27.09#ibcon#about to read 6, iclass 2, count 2 2006.201.10:09:27.09#ibcon#read 6, iclass 2, count 2 2006.201.10:09:27.09#ibcon#end of sib2, iclass 2, count 2 2006.201.10:09:27.09#ibcon#*mode == 0, iclass 2, count 2 2006.201.10:09:27.09#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.10:09:27.09#ibcon#[27=AT08-04\r\n] 2006.201.10:09:27.09#ibcon#*before write, iclass 2, count 2 2006.201.10:09:27.09#ibcon#enter sib2, iclass 2, count 2 2006.201.10:09:27.09#ibcon#flushed, iclass 2, count 2 2006.201.10:09:27.09#ibcon#about to write, iclass 2, count 2 2006.201.10:09:27.09#ibcon#wrote, iclass 2, count 2 2006.201.10:09:27.09#ibcon#about to read 3, iclass 2, count 2 2006.201.10:09:27.12#ibcon#read 3, iclass 2, count 2 2006.201.10:09:27.12#ibcon#about to read 4, iclass 2, count 2 2006.201.10:09:27.12#ibcon#read 4, iclass 2, count 2 2006.201.10:09:27.12#ibcon#about to read 5, iclass 2, count 2 2006.201.10:09:27.12#ibcon#read 5, iclass 2, count 2 2006.201.10:09:27.12#ibcon#about to read 6, iclass 2, count 2 2006.201.10:09:27.12#ibcon#read 6, iclass 2, count 2 2006.201.10:09:27.12#ibcon#end of sib2, iclass 2, count 2 2006.201.10:09:27.12#ibcon#*after write, iclass 2, count 2 2006.201.10:09:27.12#ibcon#*before return 0, iclass 2, count 2 2006.201.10:09:27.12#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:27.12#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:09:27.12#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.10:09:27.12#ibcon#ireg 7 cls_cnt 0 2006.201.10:09:27.12#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:27.24#abcon#<5=/05 2.8 4.7 22.03 951003.6\r\n> 2006.201.10:09:27.24#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:27.24#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:27.24#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:09:27.24#ibcon#first serial, iclass 2, count 0 2006.201.10:09:27.24#ibcon#enter sib2, iclass 2, count 0 2006.201.10:09:27.24#ibcon#flushed, iclass 2, count 0 2006.201.10:09:27.24#ibcon#about to write, iclass 2, count 0 2006.201.10:09:27.24#ibcon#wrote, iclass 2, count 0 2006.201.10:09:27.24#ibcon#about to read 3, iclass 2, count 0 2006.201.10:09:27.26#ibcon#read 3, iclass 2, count 0 2006.201.10:09:27.26#ibcon#about to read 4, iclass 2, count 0 2006.201.10:09:27.26#ibcon#read 4, iclass 2, count 0 2006.201.10:09:27.26#ibcon#about to read 5, iclass 2, count 0 2006.201.10:09:27.26#ibcon#read 5, iclass 2, count 0 2006.201.10:09:27.26#ibcon#about to read 6, iclass 2, count 0 2006.201.10:09:27.26#ibcon#read 6, iclass 2, count 0 2006.201.10:09:27.26#ibcon#end of sib2, iclass 2, count 0 2006.201.10:09:27.26#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:09:27.26#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:09:27.26#ibcon#[27=USB\r\n] 2006.201.10:09:27.26#ibcon#*before write, iclass 2, count 0 2006.201.10:09:27.26#ibcon#enter sib2, iclass 2, count 0 2006.201.10:09:27.26#ibcon#flushed, iclass 2, count 0 2006.201.10:09:27.26#ibcon#about to write, iclass 2, count 0 2006.201.10:09:27.26#ibcon#wrote, iclass 2, count 0 2006.201.10:09:27.26#ibcon#about to read 3, iclass 2, count 0 2006.201.10:09:27.26#abcon#{5=INTERFACE CLEAR} 2006.201.10:09:27.29#ibcon#read 3, iclass 2, count 0 2006.201.10:09:27.29#ibcon#about to read 4, iclass 2, count 0 2006.201.10:09:27.29#ibcon#read 4, iclass 2, count 0 2006.201.10:09:27.29#ibcon#about to read 5, iclass 2, count 0 2006.201.10:09:27.29#ibcon#read 5, iclass 2, count 0 2006.201.10:09:27.29#ibcon#about to read 6, iclass 2, count 0 2006.201.10:09:27.29#ibcon#read 6, iclass 2, count 0 2006.201.10:09:27.29#ibcon#end of sib2, iclass 2, count 0 2006.201.10:09:27.29#ibcon#*after write, iclass 2, count 0 2006.201.10:09:27.29#ibcon#*before return 0, iclass 2, count 0 2006.201.10:09:27.29#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:27.29#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:09:27.29#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:09:27.29#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:09:27.29$vck44/vabw=wide 2006.201.10:09:27.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.10:09:27.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.10:09:27.29#ibcon#ireg 8 cls_cnt 0 2006.201.10:09:27.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:09:27.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:09:27.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:09:27.29#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:09:27.29#ibcon#first serial, iclass 10, count 0 2006.201.10:09:27.29#ibcon#enter sib2, iclass 10, count 0 2006.201.10:09:27.29#ibcon#flushed, iclass 10, count 0 2006.201.10:09:27.29#ibcon#about to write, iclass 10, count 0 2006.201.10:09:27.29#ibcon#wrote, iclass 10, count 0 2006.201.10:09:27.29#ibcon#about to read 3, iclass 10, count 0 2006.201.10:09:27.31#ibcon#read 3, iclass 10, count 0 2006.201.10:09:27.31#ibcon#about to read 4, iclass 10, count 0 2006.201.10:09:27.31#ibcon#read 4, iclass 10, count 0 2006.201.10:09:27.31#ibcon#about to read 5, iclass 10, count 0 2006.201.10:09:27.31#ibcon#read 5, iclass 10, count 0 2006.201.10:09:27.31#ibcon#about to read 6, iclass 10, count 0 2006.201.10:09:27.31#ibcon#read 6, iclass 10, count 0 2006.201.10:09:27.31#ibcon#end of sib2, iclass 10, count 0 2006.201.10:09:27.31#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:09:27.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:09:27.31#ibcon#[25=BW32\r\n] 2006.201.10:09:27.31#ibcon#*before write, iclass 10, count 0 2006.201.10:09:27.31#ibcon#enter sib2, iclass 10, count 0 2006.201.10:09:27.31#ibcon#flushed, iclass 10, count 0 2006.201.10:09:27.31#ibcon#about to write, iclass 10, count 0 2006.201.10:09:27.31#ibcon#wrote, iclass 10, count 0 2006.201.10:09:27.31#ibcon#about to read 3, iclass 10, count 0 2006.201.10:09:27.32#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:09:27.35#ibcon#read 3, iclass 10, count 0 2006.201.10:09:27.35#ibcon#about to read 4, iclass 10, count 0 2006.201.10:09:27.35#ibcon#read 4, iclass 10, count 0 2006.201.10:09:27.35#ibcon#about to read 5, iclass 10, count 0 2006.201.10:09:27.35#ibcon#read 5, iclass 10, count 0 2006.201.10:09:27.35#ibcon#about to read 6, iclass 10, count 0 2006.201.10:09:27.35#ibcon#read 6, iclass 10, count 0 2006.201.10:09:27.35#ibcon#end of sib2, iclass 10, count 0 2006.201.10:09:27.35#ibcon#*after write, iclass 10, count 0 2006.201.10:09:27.35#ibcon#*before return 0, iclass 10, count 0 2006.201.10:09:27.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:09:27.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:09:27.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:09:27.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:09:27.35$vck44/vbbw=wide 2006.201.10:09:27.35#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.10:09:27.35#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.10:09:27.35#ibcon#ireg 8 cls_cnt 0 2006.201.10:09:27.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:09:27.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:09:27.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:09:27.41#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:09:27.41#ibcon#first serial, iclass 13, count 0 2006.201.10:09:27.41#ibcon#enter sib2, iclass 13, count 0 2006.201.10:09:27.41#ibcon#flushed, iclass 13, count 0 2006.201.10:09:27.41#ibcon#about to write, iclass 13, count 0 2006.201.10:09:27.41#ibcon#wrote, iclass 13, count 0 2006.201.10:09:27.41#ibcon#about to read 3, iclass 13, count 0 2006.201.10:09:27.43#ibcon#read 3, iclass 13, count 0 2006.201.10:09:27.43#ibcon#about to read 4, iclass 13, count 0 2006.201.10:09:27.43#ibcon#read 4, iclass 13, count 0 2006.201.10:09:27.43#ibcon#about to read 5, iclass 13, count 0 2006.201.10:09:27.43#ibcon#read 5, iclass 13, count 0 2006.201.10:09:27.43#ibcon#about to read 6, iclass 13, count 0 2006.201.10:09:27.43#ibcon#read 6, iclass 13, count 0 2006.201.10:09:27.43#ibcon#end of sib2, iclass 13, count 0 2006.201.10:09:27.43#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:09:27.43#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:09:27.43#ibcon#[27=BW32\r\n] 2006.201.10:09:27.43#ibcon#*before write, iclass 13, count 0 2006.201.10:09:27.43#ibcon#enter sib2, iclass 13, count 0 2006.201.10:09:27.43#ibcon#flushed, iclass 13, count 0 2006.201.10:09:27.43#ibcon#about to write, iclass 13, count 0 2006.201.10:09:27.43#ibcon#wrote, iclass 13, count 0 2006.201.10:09:27.43#ibcon#about to read 3, iclass 13, count 0 2006.201.10:09:27.46#ibcon#read 3, iclass 13, count 0 2006.201.10:09:27.46#ibcon#about to read 4, iclass 13, count 0 2006.201.10:09:27.46#ibcon#read 4, iclass 13, count 0 2006.201.10:09:27.46#ibcon#about to read 5, iclass 13, count 0 2006.201.10:09:27.46#ibcon#read 5, iclass 13, count 0 2006.201.10:09:27.46#ibcon#about to read 6, iclass 13, count 0 2006.201.10:09:27.46#ibcon#read 6, iclass 13, count 0 2006.201.10:09:27.46#ibcon#end of sib2, iclass 13, count 0 2006.201.10:09:27.46#ibcon#*after write, iclass 13, count 0 2006.201.10:09:27.46#ibcon#*before return 0, iclass 13, count 0 2006.201.10:09:27.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:09:27.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:09:27.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:09:27.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:09:27.46$setupk4/ifdk4 2006.201.10:09:27.46$ifdk4/lo= 2006.201.10:09:27.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:09:27.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:09:27.46$ifdk4/patch= 2006.201.10:09:27.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:09:27.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:09:27.46$setupk4/!*+20s 2006.201.10:09:34.14#trakl#Source acquired 2006.201.10:09:36.14#flagr#flagr/antenna,acquired 2006.201.10:09:37.41#abcon#<5=/05 2.8 4.7 22.03 951003.6\r\n> 2006.201.10:09:37.43#abcon#{5=INTERFACE CLEAR} 2006.201.10:09:37.49#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:09:41.94$setupk4/"tpicd 2006.201.10:09:41.94$setupk4/echo=off 2006.201.10:09:41.94$setupk4/xlog=off 2006.201.10:09:41.94:!2006.201.10:14:39 2006.201.10:14:39.00:preob 2006.201.10:14:40.14/onsource/TRACKING 2006.201.10:14:40.14:!2006.201.10:14:49 2006.201.10:14:49.00:"tape 2006.201.10:14:49.00:"st=record 2006.201.10:14:49.00:data_valid=on 2006.201.10:14:49.00:midob 2006.201.10:14:49.14/onsource/TRACKING 2006.201.10:14:49.14/wx/21.95,1003.6,95 2006.201.10:14:49.19/cable/+6.4683E-03 2006.201.10:14:50.28/va/01,08,usb,yes,31,33 2006.201.10:14:50.28/va/02,07,usb,yes,33,34 2006.201.10:14:50.28/va/03,08,usb,yes,30,31 2006.201.10:14:50.28/va/04,07,usb,yes,34,36 2006.201.10:14:50.28/va/05,04,usb,yes,30,30 2006.201.10:14:50.28/va/06,05,usb,yes,30,30 2006.201.10:14:50.28/va/07,05,usb,yes,29,30 2006.201.10:14:50.28/va/08,04,usb,yes,29,35 2006.201.10:14:50.51/valo/01,524.99,yes,locked 2006.201.10:14:50.51/valo/02,534.99,yes,locked 2006.201.10:14:50.51/valo/03,564.99,yes,locked 2006.201.10:14:50.51/valo/04,624.99,yes,locked 2006.201.10:14:50.51/valo/05,734.99,yes,locked 2006.201.10:14:50.51/valo/06,814.99,yes,locked 2006.201.10:14:50.51/valo/07,864.99,yes,locked 2006.201.10:14:50.51/valo/08,884.99,yes,locked 2006.201.10:14:51.60/vb/01,04,usb,yes,35,32 2006.201.10:14:51.60/vb/02,05,usb,yes,33,33 2006.201.10:14:51.60/vb/03,04,usb,yes,34,38 2006.201.10:14:51.60/vb/04,05,usb,yes,34,33 2006.201.10:14:51.60/vb/05,04,usb,yes,30,33 2006.201.10:14:51.60/vb/06,04,usb,yes,35,31 2006.201.10:14:51.60/vb/07,04,usb,yes,35,35 2006.201.10:14:51.60/vb/08,04,usb,yes,32,36 2006.201.10:14:51.83/vblo/01,629.99,yes,locked 2006.201.10:14:51.83/vblo/02,634.99,yes,locked 2006.201.10:14:51.83/vblo/03,649.99,yes,locked 2006.201.10:14:51.83/vblo/04,679.99,yes,locked 2006.201.10:14:51.83/vblo/05,709.99,yes,locked 2006.201.10:14:51.83/vblo/06,719.99,yes,locked 2006.201.10:14:51.83/vblo/07,734.99,yes,locked 2006.201.10:14:51.83/vblo/08,744.99,yes,locked 2006.201.10:14:51.98/vabw/8 2006.201.10:14:52.13/vbbw/8 2006.201.10:14:52.22/xfe/off,on,15.5 2006.201.10:14:52.61/ifatt/23,28,28,28 2006.201.10:14:53.06/fmout-gps/S +4.61E-07 2006.201.10:14:53.13:!2006.201.10:16:19 2006.201.10:16:19.00:data_valid=off 2006.201.10:16:19.00:"et 2006.201.10:16:19.00:!+3s 2006.201.10:16:22.02:"tape 2006.201.10:16:22.02:postob 2006.201.10:16:22.12/cable/+6.4677E-03 2006.201.10:16:22.12/wx/21.92,1003.5,95 2006.201.10:16:22.20/fmout-gps/S +4.62E-07 2006.201.10:16:22.20:scan_name=201-1025,jd0607,40 2006.201.10:16:22.21:source=3c345,164258.81,394837.0,2000.0,cw 2006.201.10:16:23.13#flagr#flagr/antenna,new-source 2006.201.10:16:23.13:checkk5 2006.201.10:16:23.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:16:23.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:16:24.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:16:24.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:16:25.00/chk_obsdata//k5ts1/T2011014??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.10:16:25.37/chk_obsdata//k5ts2/T2011014??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.10:16:25.74/chk_obsdata//k5ts3/T2011014??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.10:16:26.10/chk_obsdata//k5ts4/T2011014??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.10:16:26.80/k5log//k5ts1_log_newline 2006.201.10:16:27.49/k5log//k5ts2_log_newline 2006.201.10:16:28.18/k5log//k5ts3_log_newline 2006.201.10:16:28.86/k5log//k5ts4_log_newline 2006.201.10:16:28.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:16:28.88:setupk4=1 2006.201.10:16:28.88$setupk4/echo=on 2006.201.10:16:28.88$setupk4/pcalon 2006.201.10:16:28.88$pcalon/"no phase cal control is implemented here 2006.201.10:16:28.88$setupk4/"tpicd=stop 2006.201.10:16:28.88$setupk4/"rec=synch_on 2006.201.10:16:28.88$setupk4/"rec_mode=128 2006.201.10:16:28.88$setupk4/!* 2006.201.10:16:28.88$setupk4/recpk4 2006.201.10:16:28.88$recpk4/recpatch= 2006.201.10:16:28.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:16:28.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:16:28.89$setupk4/vck44 2006.201.10:16:28.89$vck44/valo=1,524.99 2006.201.10:16:28.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.10:16:28.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.10:16:28.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:28.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:28.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:28.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:28.89#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:16:28.89#ibcon#first serial, iclass 38, count 0 2006.201.10:16:28.89#ibcon#enter sib2, iclass 38, count 0 2006.201.10:16:28.89#ibcon#flushed, iclass 38, count 0 2006.201.10:16:28.89#ibcon#about to write, iclass 38, count 0 2006.201.10:16:28.89#ibcon#wrote, iclass 38, count 0 2006.201.10:16:28.89#ibcon#about to read 3, iclass 38, count 0 2006.201.10:16:28.92#ibcon#read 3, iclass 38, count 0 2006.201.10:16:28.93#ibcon#about to read 4, iclass 38, count 0 2006.201.10:16:28.93#ibcon#read 4, iclass 38, count 0 2006.201.10:16:28.93#ibcon#about to read 5, iclass 38, count 0 2006.201.10:16:28.93#ibcon#read 5, iclass 38, count 0 2006.201.10:16:28.93#ibcon#about to read 6, iclass 38, count 0 2006.201.10:16:28.93#ibcon#read 6, iclass 38, count 0 2006.201.10:16:28.93#ibcon#end of sib2, iclass 38, count 0 2006.201.10:16:28.93#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:16:28.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:16:28.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:16:28.93#ibcon#*before write, iclass 38, count 0 2006.201.10:16:28.93#ibcon#enter sib2, iclass 38, count 0 2006.201.10:16:28.93#ibcon#flushed, iclass 38, count 0 2006.201.10:16:28.93#ibcon#about to write, iclass 38, count 0 2006.201.10:16:28.93#ibcon#wrote, iclass 38, count 0 2006.201.10:16:28.93#ibcon#about to read 3, iclass 38, count 0 2006.201.10:16:28.98#ibcon#read 3, iclass 38, count 0 2006.201.10:16:28.98#ibcon#about to read 4, iclass 38, count 0 2006.201.10:16:28.98#ibcon#read 4, iclass 38, count 0 2006.201.10:16:28.98#ibcon#about to read 5, iclass 38, count 0 2006.201.10:16:28.98#ibcon#read 5, iclass 38, count 0 2006.201.10:16:28.98#ibcon#about to read 6, iclass 38, count 0 2006.201.10:16:28.98#ibcon#read 6, iclass 38, count 0 2006.201.10:16:28.98#ibcon#end of sib2, iclass 38, count 0 2006.201.10:16:28.98#ibcon#*after write, iclass 38, count 0 2006.201.10:16:28.98#ibcon#*before return 0, iclass 38, count 0 2006.201.10:16:28.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:28.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:28.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:16:28.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:16:28.98$vck44/va=1,8 2006.201.10:16:28.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.10:16:28.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.10:16:28.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:28.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:28.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:28.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:28.98#ibcon#enter wrdev, iclass 40, count 2 2006.201.10:16:28.98#ibcon#first serial, iclass 40, count 2 2006.201.10:16:28.98#ibcon#enter sib2, iclass 40, count 2 2006.201.10:16:28.98#ibcon#flushed, iclass 40, count 2 2006.201.10:16:28.98#ibcon#about to write, iclass 40, count 2 2006.201.10:16:28.98#ibcon#wrote, iclass 40, count 2 2006.201.10:16:28.98#ibcon#about to read 3, iclass 40, count 2 2006.201.10:16:29.00#ibcon#read 3, iclass 40, count 2 2006.201.10:16:29.00#ibcon#about to read 4, iclass 40, count 2 2006.201.10:16:29.00#ibcon#read 4, iclass 40, count 2 2006.201.10:16:29.00#ibcon#about to read 5, iclass 40, count 2 2006.201.10:16:29.00#ibcon#read 5, iclass 40, count 2 2006.201.10:16:29.00#ibcon#about to read 6, iclass 40, count 2 2006.201.10:16:29.00#ibcon#read 6, iclass 40, count 2 2006.201.10:16:29.00#ibcon#end of sib2, iclass 40, count 2 2006.201.10:16:29.00#ibcon#*mode == 0, iclass 40, count 2 2006.201.10:16:29.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.10:16:29.00#ibcon#[25=AT01-08\r\n] 2006.201.10:16:29.00#ibcon#*before write, iclass 40, count 2 2006.201.10:16:29.00#ibcon#enter sib2, iclass 40, count 2 2006.201.10:16:29.00#ibcon#flushed, iclass 40, count 2 2006.201.10:16:29.00#ibcon#about to write, iclass 40, count 2 2006.201.10:16:29.00#ibcon#wrote, iclass 40, count 2 2006.201.10:16:29.00#ibcon#about to read 3, iclass 40, count 2 2006.201.10:16:29.04#ibcon#read 3, iclass 40, count 2 2006.201.10:16:29.04#ibcon#about to read 4, iclass 40, count 2 2006.201.10:16:29.04#ibcon#read 4, iclass 40, count 2 2006.201.10:16:29.04#ibcon#about to read 5, iclass 40, count 2 2006.201.10:16:29.04#ibcon#read 5, iclass 40, count 2 2006.201.10:16:29.04#ibcon#about to read 6, iclass 40, count 2 2006.201.10:16:29.04#ibcon#read 6, iclass 40, count 2 2006.201.10:16:29.04#ibcon#end of sib2, iclass 40, count 2 2006.201.10:16:29.04#ibcon#*after write, iclass 40, count 2 2006.201.10:16:29.04#ibcon#*before return 0, iclass 40, count 2 2006.201.10:16:29.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:29.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:29.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.10:16:29.04#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:29.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:29.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:29.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:29.16#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:16:29.16#ibcon#first serial, iclass 40, count 0 2006.201.10:16:29.16#ibcon#enter sib2, iclass 40, count 0 2006.201.10:16:29.16#ibcon#flushed, iclass 40, count 0 2006.201.10:16:29.16#ibcon#about to write, iclass 40, count 0 2006.201.10:16:29.16#ibcon#wrote, iclass 40, count 0 2006.201.10:16:29.16#ibcon#about to read 3, iclass 40, count 0 2006.201.10:16:29.18#ibcon#read 3, iclass 40, count 0 2006.201.10:16:29.18#ibcon#about to read 4, iclass 40, count 0 2006.201.10:16:29.18#ibcon#read 4, iclass 40, count 0 2006.201.10:16:29.18#ibcon#about to read 5, iclass 40, count 0 2006.201.10:16:29.18#ibcon#read 5, iclass 40, count 0 2006.201.10:16:29.18#ibcon#about to read 6, iclass 40, count 0 2006.201.10:16:29.18#ibcon#read 6, iclass 40, count 0 2006.201.10:16:29.18#ibcon#end of sib2, iclass 40, count 0 2006.201.10:16:29.18#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:16:29.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:16:29.18#ibcon#[25=USB\r\n] 2006.201.10:16:29.18#ibcon#*before write, iclass 40, count 0 2006.201.10:16:29.18#ibcon#enter sib2, iclass 40, count 0 2006.201.10:16:29.18#ibcon#flushed, iclass 40, count 0 2006.201.10:16:29.18#ibcon#about to write, iclass 40, count 0 2006.201.10:16:29.18#ibcon#wrote, iclass 40, count 0 2006.201.10:16:29.18#ibcon#about to read 3, iclass 40, count 0 2006.201.10:16:29.21#ibcon#read 3, iclass 40, count 0 2006.201.10:16:29.21#ibcon#about to read 4, iclass 40, count 0 2006.201.10:16:29.21#ibcon#read 4, iclass 40, count 0 2006.201.10:16:29.21#ibcon#about to read 5, iclass 40, count 0 2006.201.10:16:29.21#ibcon#read 5, iclass 40, count 0 2006.201.10:16:29.21#ibcon#about to read 6, iclass 40, count 0 2006.201.10:16:29.21#ibcon#read 6, iclass 40, count 0 2006.201.10:16:29.21#ibcon#end of sib2, iclass 40, count 0 2006.201.10:16:29.21#ibcon#*after write, iclass 40, count 0 2006.201.10:16:29.21#ibcon#*before return 0, iclass 40, count 0 2006.201.10:16:29.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:29.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:29.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:16:29.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:16:29.21$vck44/valo=2,534.99 2006.201.10:16:29.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.10:16:29.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.10:16:29.21#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:29.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:29.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:29.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:29.21#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:16:29.21#ibcon#first serial, iclass 4, count 0 2006.201.10:16:29.21#ibcon#enter sib2, iclass 4, count 0 2006.201.10:16:29.21#ibcon#flushed, iclass 4, count 0 2006.201.10:16:29.21#ibcon#about to write, iclass 4, count 0 2006.201.10:16:29.21#ibcon#wrote, iclass 4, count 0 2006.201.10:16:29.21#ibcon#about to read 3, iclass 4, count 0 2006.201.10:16:29.23#ibcon#read 3, iclass 4, count 0 2006.201.10:16:29.23#ibcon#about to read 4, iclass 4, count 0 2006.201.10:16:29.23#ibcon#read 4, iclass 4, count 0 2006.201.10:16:29.23#ibcon#about to read 5, iclass 4, count 0 2006.201.10:16:29.23#ibcon#read 5, iclass 4, count 0 2006.201.10:16:29.23#ibcon#about to read 6, iclass 4, count 0 2006.201.10:16:29.23#ibcon#read 6, iclass 4, count 0 2006.201.10:16:29.23#ibcon#end of sib2, iclass 4, count 0 2006.201.10:16:29.23#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:16:29.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:16:29.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:16:29.23#ibcon#*before write, iclass 4, count 0 2006.201.10:16:29.23#ibcon#enter sib2, iclass 4, count 0 2006.201.10:16:29.23#ibcon#flushed, iclass 4, count 0 2006.201.10:16:29.23#ibcon#about to write, iclass 4, count 0 2006.201.10:16:29.23#ibcon#wrote, iclass 4, count 0 2006.201.10:16:29.23#ibcon#about to read 3, iclass 4, count 0 2006.201.10:16:29.27#ibcon#read 3, iclass 4, count 0 2006.201.10:16:29.27#ibcon#about to read 4, iclass 4, count 0 2006.201.10:16:29.27#ibcon#read 4, iclass 4, count 0 2006.201.10:16:29.27#ibcon#about to read 5, iclass 4, count 0 2006.201.10:16:29.27#ibcon#read 5, iclass 4, count 0 2006.201.10:16:29.27#ibcon#about to read 6, iclass 4, count 0 2006.201.10:16:29.27#ibcon#read 6, iclass 4, count 0 2006.201.10:16:29.27#ibcon#end of sib2, iclass 4, count 0 2006.201.10:16:29.27#ibcon#*after write, iclass 4, count 0 2006.201.10:16:29.27#ibcon#*before return 0, iclass 4, count 0 2006.201.10:16:29.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:29.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:29.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:16:29.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:16:29.27$vck44/va=2,7 2006.201.10:16:29.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.10:16:29.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.10:16:29.27#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:29.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:29.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:29.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:29.33#ibcon#enter wrdev, iclass 6, count 2 2006.201.10:16:29.33#ibcon#first serial, iclass 6, count 2 2006.201.10:16:29.33#ibcon#enter sib2, iclass 6, count 2 2006.201.10:16:29.33#ibcon#flushed, iclass 6, count 2 2006.201.10:16:29.33#ibcon#about to write, iclass 6, count 2 2006.201.10:16:29.33#ibcon#wrote, iclass 6, count 2 2006.201.10:16:29.33#ibcon#about to read 3, iclass 6, count 2 2006.201.10:16:29.35#ibcon#read 3, iclass 6, count 2 2006.201.10:16:29.35#ibcon#about to read 4, iclass 6, count 2 2006.201.10:16:29.35#ibcon#read 4, iclass 6, count 2 2006.201.10:16:29.35#ibcon#about to read 5, iclass 6, count 2 2006.201.10:16:29.35#ibcon#read 5, iclass 6, count 2 2006.201.10:16:29.35#ibcon#about to read 6, iclass 6, count 2 2006.201.10:16:29.35#ibcon#read 6, iclass 6, count 2 2006.201.10:16:29.35#ibcon#end of sib2, iclass 6, count 2 2006.201.10:16:29.35#ibcon#*mode == 0, iclass 6, count 2 2006.201.10:16:29.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.10:16:29.35#ibcon#[25=AT02-07\r\n] 2006.201.10:16:29.35#ibcon#*before write, iclass 6, count 2 2006.201.10:16:29.35#ibcon#enter sib2, iclass 6, count 2 2006.201.10:16:29.35#ibcon#flushed, iclass 6, count 2 2006.201.10:16:29.35#ibcon#about to write, iclass 6, count 2 2006.201.10:16:29.35#ibcon#wrote, iclass 6, count 2 2006.201.10:16:29.35#ibcon#about to read 3, iclass 6, count 2 2006.201.10:16:29.38#ibcon#read 3, iclass 6, count 2 2006.201.10:16:29.38#ibcon#about to read 4, iclass 6, count 2 2006.201.10:16:29.38#ibcon#read 4, iclass 6, count 2 2006.201.10:16:29.38#ibcon#about to read 5, iclass 6, count 2 2006.201.10:16:29.38#ibcon#read 5, iclass 6, count 2 2006.201.10:16:29.38#ibcon#about to read 6, iclass 6, count 2 2006.201.10:16:29.38#ibcon#read 6, iclass 6, count 2 2006.201.10:16:29.38#ibcon#end of sib2, iclass 6, count 2 2006.201.10:16:29.38#ibcon#*after write, iclass 6, count 2 2006.201.10:16:29.38#ibcon#*before return 0, iclass 6, count 2 2006.201.10:16:29.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:29.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:29.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.10:16:29.38#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:29.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:29.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:29.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:29.50#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:16:29.50#ibcon#first serial, iclass 6, count 0 2006.201.10:16:29.50#ibcon#enter sib2, iclass 6, count 0 2006.201.10:16:29.50#ibcon#flushed, iclass 6, count 0 2006.201.10:16:29.50#ibcon#about to write, iclass 6, count 0 2006.201.10:16:29.50#ibcon#wrote, iclass 6, count 0 2006.201.10:16:29.50#ibcon#about to read 3, iclass 6, count 0 2006.201.10:16:29.52#ibcon#read 3, iclass 6, count 0 2006.201.10:16:29.52#ibcon#about to read 4, iclass 6, count 0 2006.201.10:16:29.52#ibcon#read 4, iclass 6, count 0 2006.201.10:16:29.52#ibcon#about to read 5, iclass 6, count 0 2006.201.10:16:29.52#ibcon#read 5, iclass 6, count 0 2006.201.10:16:29.52#ibcon#about to read 6, iclass 6, count 0 2006.201.10:16:29.52#ibcon#read 6, iclass 6, count 0 2006.201.10:16:29.52#ibcon#end of sib2, iclass 6, count 0 2006.201.10:16:29.52#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:16:29.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:16:29.52#ibcon#[25=USB\r\n] 2006.201.10:16:29.52#ibcon#*before write, iclass 6, count 0 2006.201.10:16:29.52#ibcon#enter sib2, iclass 6, count 0 2006.201.10:16:29.52#ibcon#flushed, iclass 6, count 0 2006.201.10:16:29.52#ibcon#about to write, iclass 6, count 0 2006.201.10:16:29.52#ibcon#wrote, iclass 6, count 0 2006.201.10:16:29.52#ibcon#about to read 3, iclass 6, count 0 2006.201.10:16:29.55#ibcon#read 3, iclass 6, count 0 2006.201.10:16:29.55#ibcon#about to read 4, iclass 6, count 0 2006.201.10:16:29.55#ibcon#read 4, iclass 6, count 0 2006.201.10:16:29.55#ibcon#about to read 5, iclass 6, count 0 2006.201.10:16:29.55#ibcon#read 5, iclass 6, count 0 2006.201.10:16:29.55#ibcon#about to read 6, iclass 6, count 0 2006.201.10:16:29.55#ibcon#read 6, iclass 6, count 0 2006.201.10:16:29.55#ibcon#end of sib2, iclass 6, count 0 2006.201.10:16:29.55#ibcon#*after write, iclass 6, count 0 2006.201.10:16:29.55#ibcon#*before return 0, iclass 6, count 0 2006.201.10:16:29.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:29.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:29.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:16:29.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:16:29.55$vck44/valo=3,564.99 2006.201.10:16:29.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.10:16:29.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.10:16:29.55#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:29.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:29.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:29.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:29.55#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:16:29.55#ibcon#first serial, iclass 10, count 0 2006.201.10:16:29.55#ibcon#enter sib2, iclass 10, count 0 2006.201.10:16:29.55#ibcon#flushed, iclass 10, count 0 2006.201.10:16:29.55#ibcon#about to write, iclass 10, count 0 2006.201.10:16:29.55#ibcon#wrote, iclass 10, count 0 2006.201.10:16:29.55#ibcon#about to read 3, iclass 10, count 0 2006.201.10:16:29.57#ibcon#read 3, iclass 10, count 0 2006.201.10:16:29.57#ibcon#about to read 4, iclass 10, count 0 2006.201.10:16:29.57#ibcon#read 4, iclass 10, count 0 2006.201.10:16:29.57#ibcon#about to read 5, iclass 10, count 0 2006.201.10:16:29.57#ibcon#read 5, iclass 10, count 0 2006.201.10:16:29.57#ibcon#about to read 6, iclass 10, count 0 2006.201.10:16:29.57#ibcon#read 6, iclass 10, count 0 2006.201.10:16:29.57#ibcon#end of sib2, iclass 10, count 0 2006.201.10:16:29.57#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:16:29.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:16:29.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:16:29.57#ibcon#*before write, iclass 10, count 0 2006.201.10:16:29.57#ibcon#enter sib2, iclass 10, count 0 2006.201.10:16:29.57#ibcon#flushed, iclass 10, count 0 2006.201.10:16:29.57#ibcon#about to write, iclass 10, count 0 2006.201.10:16:29.57#ibcon#wrote, iclass 10, count 0 2006.201.10:16:29.57#ibcon#about to read 3, iclass 10, count 0 2006.201.10:16:29.62#ibcon#read 3, iclass 10, count 0 2006.201.10:16:29.62#ibcon#about to read 4, iclass 10, count 0 2006.201.10:16:29.62#ibcon#read 4, iclass 10, count 0 2006.201.10:16:29.62#ibcon#about to read 5, iclass 10, count 0 2006.201.10:16:29.62#ibcon#read 5, iclass 10, count 0 2006.201.10:16:29.62#ibcon#about to read 6, iclass 10, count 0 2006.201.10:16:29.62#ibcon#read 6, iclass 10, count 0 2006.201.10:16:29.62#ibcon#end of sib2, iclass 10, count 0 2006.201.10:16:29.62#ibcon#*after write, iclass 10, count 0 2006.201.10:16:29.62#ibcon#*before return 0, iclass 10, count 0 2006.201.10:16:29.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:29.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:29.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:16:29.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:16:29.62$vck44/va=3,8 2006.201.10:16:29.62#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.10:16:29.62#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.10:16:29.62#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:29.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:29.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:29.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:29.67#ibcon#enter wrdev, iclass 12, count 2 2006.201.10:16:29.67#ibcon#first serial, iclass 12, count 2 2006.201.10:16:29.67#ibcon#enter sib2, iclass 12, count 2 2006.201.10:16:29.67#ibcon#flushed, iclass 12, count 2 2006.201.10:16:29.67#ibcon#about to write, iclass 12, count 2 2006.201.10:16:29.67#ibcon#wrote, iclass 12, count 2 2006.201.10:16:29.67#ibcon#about to read 3, iclass 12, count 2 2006.201.10:16:29.69#ibcon#read 3, iclass 12, count 2 2006.201.10:16:29.69#ibcon#about to read 4, iclass 12, count 2 2006.201.10:16:29.69#ibcon#read 4, iclass 12, count 2 2006.201.10:16:29.69#ibcon#about to read 5, iclass 12, count 2 2006.201.10:16:29.69#ibcon#read 5, iclass 12, count 2 2006.201.10:16:29.69#ibcon#about to read 6, iclass 12, count 2 2006.201.10:16:29.69#ibcon#read 6, iclass 12, count 2 2006.201.10:16:29.69#ibcon#end of sib2, iclass 12, count 2 2006.201.10:16:29.69#ibcon#*mode == 0, iclass 12, count 2 2006.201.10:16:29.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.10:16:29.69#ibcon#[25=AT03-08\r\n] 2006.201.10:16:29.69#ibcon#*before write, iclass 12, count 2 2006.201.10:16:29.69#ibcon#enter sib2, iclass 12, count 2 2006.201.10:16:29.69#ibcon#flushed, iclass 12, count 2 2006.201.10:16:29.69#ibcon#about to write, iclass 12, count 2 2006.201.10:16:29.69#ibcon#wrote, iclass 12, count 2 2006.201.10:16:29.69#ibcon#about to read 3, iclass 12, count 2 2006.201.10:16:29.72#ibcon#read 3, iclass 12, count 2 2006.201.10:16:29.72#ibcon#about to read 4, iclass 12, count 2 2006.201.10:16:29.72#ibcon#read 4, iclass 12, count 2 2006.201.10:16:29.72#ibcon#about to read 5, iclass 12, count 2 2006.201.10:16:29.72#ibcon#read 5, iclass 12, count 2 2006.201.10:16:29.72#ibcon#about to read 6, iclass 12, count 2 2006.201.10:16:29.72#ibcon#read 6, iclass 12, count 2 2006.201.10:16:29.72#ibcon#end of sib2, iclass 12, count 2 2006.201.10:16:29.72#ibcon#*after write, iclass 12, count 2 2006.201.10:16:29.72#ibcon#*before return 0, iclass 12, count 2 2006.201.10:16:29.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:29.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:29.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.10:16:29.72#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:29.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:29.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:29.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:29.84#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:16:29.84#ibcon#first serial, iclass 12, count 0 2006.201.10:16:29.84#ibcon#enter sib2, iclass 12, count 0 2006.201.10:16:29.84#ibcon#flushed, iclass 12, count 0 2006.201.10:16:29.84#ibcon#about to write, iclass 12, count 0 2006.201.10:16:29.84#ibcon#wrote, iclass 12, count 0 2006.201.10:16:29.84#ibcon#about to read 3, iclass 12, count 0 2006.201.10:16:29.86#ibcon#read 3, iclass 12, count 0 2006.201.10:16:29.86#ibcon#about to read 4, iclass 12, count 0 2006.201.10:16:29.86#ibcon#read 4, iclass 12, count 0 2006.201.10:16:29.86#ibcon#about to read 5, iclass 12, count 0 2006.201.10:16:29.86#ibcon#read 5, iclass 12, count 0 2006.201.10:16:29.86#ibcon#about to read 6, iclass 12, count 0 2006.201.10:16:29.86#ibcon#read 6, iclass 12, count 0 2006.201.10:16:29.86#ibcon#end of sib2, iclass 12, count 0 2006.201.10:16:29.86#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:16:29.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:16:29.86#ibcon#[25=USB\r\n] 2006.201.10:16:29.86#ibcon#*before write, iclass 12, count 0 2006.201.10:16:29.86#ibcon#enter sib2, iclass 12, count 0 2006.201.10:16:29.86#ibcon#flushed, iclass 12, count 0 2006.201.10:16:29.86#ibcon#about to write, iclass 12, count 0 2006.201.10:16:29.86#ibcon#wrote, iclass 12, count 0 2006.201.10:16:29.86#ibcon#about to read 3, iclass 12, count 0 2006.201.10:16:29.89#ibcon#read 3, iclass 12, count 0 2006.201.10:16:29.89#ibcon#about to read 4, iclass 12, count 0 2006.201.10:16:29.89#ibcon#read 4, iclass 12, count 0 2006.201.10:16:29.89#ibcon#about to read 5, iclass 12, count 0 2006.201.10:16:29.89#ibcon#read 5, iclass 12, count 0 2006.201.10:16:29.89#ibcon#about to read 6, iclass 12, count 0 2006.201.10:16:29.89#ibcon#read 6, iclass 12, count 0 2006.201.10:16:29.89#ibcon#end of sib2, iclass 12, count 0 2006.201.10:16:29.89#ibcon#*after write, iclass 12, count 0 2006.201.10:16:29.89#ibcon#*before return 0, iclass 12, count 0 2006.201.10:16:29.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:29.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:29.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:16:29.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:16:29.89$vck44/valo=4,624.99 2006.201.10:16:29.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.10:16:29.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.10:16:29.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:29.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:29.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:29.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:29.89#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:16:29.89#ibcon#first serial, iclass 14, count 0 2006.201.10:16:29.89#ibcon#enter sib2, iclass 14, count 0 2006.201.10:16:29.89#ibcon#flushed, iclass 14, count 0 2006.201.10:16:29.89#ibcon#about to write, iclass 14, count 0 2006.201.10:16:29.89#ibcon#wrote, iclass 14, count 0 2006.201.10:16:29.89#ibcon#about to read 3, iclass 14, count 0 2006.201.10:16:29.91#ibcon#read 3, iclass 14, count 0 2006.201.10:16:29.91#ibcon#about to read 4, iclass 14, count 0 2006.201.10:16:29.91#ibcon#read 4, iclass 14, count 0 2006.201.10:16:29.91#ibcon#about to read 5, iclass 14, count 0 2006.201.10:16:29.91#ibcon#read 5, iclass 14, count 0 2006.201.10:16:29.91#ibcon#about to read 6, iclass 14, count 0 2006.201.10:16:29.91#ibcon#read 6, iclass 14, count 0 2006.201.10:16:29.91#ibcon#end of sib2, iclass 14, count 0 2006.201.10:16:29.91#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:16:29.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:16:29.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:16:29.91#ibcon#*before write, iclass 14, count 0 2006.201.10:16:29.91#ibcon#enter sib2, iclass 14, count 0 2006.201.10:16:29.91#ibcon#flushed, iclass 14, count 0 2006.201.10:16:29.91#ibcon#about to write, iclass 14, count 0 2006.201.10:16:29.91#ibcon#wrote, iclass 14, count 0 2006.201.10:16:29.91#ibcon#about to read 3, iclass 14, count 0 2006.201.10:16:29.96#ibcon#read 3, iclass 14, count 0 2006.201.10:16:29.96#ibcon#about to read 4, iclass 14, count 0 2006.201.10:16:29.96#ibcon#read 4, iclass 14, count 0 2006.201.10:16:29.96#ibcon#about to read 5, iclass 14, count 0 2006.201.10:16:29.96#ibcon#read 5, iclass 14, count 0 2006.201.10:16:29.96#ibcon#about to read 6, iclass 14, count 0 2006.201.10:16:29.96#ibcon#read 6, iclass 14, count 0 2006.201.10:16:29.96#ibcon#end of sib2, iclass 14, count 0 2006.201.10:16:29.96#ibcon#*after write, iclass 14, count 0 2006.201.10:16:29.96#ibcon#*before return 0, iclass 14, count 0 2006.201.10:16:29.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:29.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:29.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:16:29.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:16:29.96$vck44/va=4,7 2006.201.10:16:29.96#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.10:16:29.96#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.10:16:29.96#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:29.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:30.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:30.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:30.01#ibcon#enter wrdev, iclass 16, count 2 2006.201.10:16:30.01#ibcon#first serial, iclass 16, count 2 2006.201.10:16:30.01#ibcon#enter sib2, iclass 16, count 2 2006.201.10:16:30.01#ibcon#flushed, iclass 16, count 2 2006.201.10:16:30.01#ibcon#about to write, iclass 16, count 2 2006.201.10:16:30.01#ibcon#wrote, iclass 16, count 2 2006.201.10:16:30.01#ibcon#about to read 3, iclass 16, count 2 2006.201.10:16:30.03#ibcon#read 3, iclass 16, count 2 2006.201.10:16:30.03#ibcon#about to read 4, iclass 16, count 2 2006.201.10:16:30.03#ibcon#read 4, iclass 16, count 2 2006.201.10:16:30.03#ibcon#about to read 5, iclass 16, count 2 2006.201.10:16:30.03#ibcon#read 5, iclass 16, count 2 2006.201.10:16:30.03#ibcon#about to read 6, iclass 16, count 2 2006.201.10:16:30.03#ibcon#read 6, iclass 16, count 2 2006.201.10:16:30.03#ibcon#end of sib2, iclass 16, count 2 2006.201.10:16:30.03#ibcon#*mode == 0, iclass 16, count 2 2006.201.10:16:30.03#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.10:16:30.03#ibcon#[25=AT04-07\r\n] 2006.201.10:16:30.03#ibcon#*before write, iclass 16, count 2 2006.201.10:16:30.03#ibcon#enter sib2, iclass 16, count 2 2006.201.10:16:30.03#ibcon#flushed, iclass 16, count 2 2006.201.10:16:30.03#ibcon#about to write, iclass 16, count 2 2006.201.10:16:30.03#ibcon#wrote, iclass 16, count 2 2006.201.10:16:30.03#ibcon#about to read 3, iclass 16, count 2 2006.201.10:16:30.06#ibcon#read 3, iclass 16, count 2 2006.201.10:16:30.06#ibcon#about to read 4, iclass 16, count 2 2006.201.10:16:30.06#ibcon#read 4, iclass 16, count 2 2006.201.10:16:30.06#ibcon#about to read 5, iclass 16, count 2 2006.201.10:16:30.06#ibcon#read 5, iclass 16, count 2 2006.201.10:16:30.06#ibcon#about to read 6, iclass 16, count 2 2006.201.10:16:30.06#ibcon#read 6, iclass 16, count 2 2006.201.10:16:30.06#ibcon#end of sib2, iclass 16, count 2 2006.201.10:16:30.06#ibcon#*after write, iclass 16, count 2 2006.201.10:16:30.06#ibcon#*before return 0, iclass 16, count 2 2006.201.10:16:30.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:30.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:30.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.10:16:30.06#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:30.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:30.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:30.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:30.18#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:16:30.18#ibcon#first serial, iclass 16, count 0 2006.201.10:16:30.18#ibcon#enter sib2, iclass 16, count 0 2006.201.10:16:30.18#ibcon#flushed, iclass 16, count 0 2006.201.10:16:30.18#ibcon#about to write, iclass 16, count 0 2006.201.10:16:30.18#ibcon#wrote, iclass 16, count 0 2006.201.10:16:30.18#ibcon#about to read 3, iclass 16, count 0 2006.201.10:16:30.20#ibcon#read 3, iclass 16, count 0 2006.201.10:16:30.20#ibcon#about to read 4, iclass 16, count 0 2006.201.10:16:30.20#ibcon#read 4, iclass 16, count 0 2006.201.10:16:30.20#ibcon#about to read 5, iclass 16, count 0 2006.201.10:16:30.20#ibcon#read 5, iclass 16, count 0 2006.201.10:16:30.20#ibcon#about to read 6, iclass 16, count 0 2006.201.10:16:30.20#ibcon#read 6, iclass 16, count 0 2006.201.10:16:30.20#ibcon#end of sib2, iclass 16, count 0 2006.201.10:16:30.20#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:16:30.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:16:30.20#ibcon#[25=USB\r\n] 2006.201.10:16:30.20#ibcon#*before write, iclass 16, count 0 2006.201.10:16:30.20#ibcon#enter sib2, iclass 16, count 0 2006.201.10:16:30.20#ibcon#flushed, iclass 16, count 0 2006.201.10:16:30.20#ibcon#about to write, iclass 16, count 0 2006.201.10:16:30.20#ibcon#wrote, iclass 16, count 0 2006.201.10:16:30.20#ibcon#about to read 3, iclass 16, count 0 2006.201.10:16:30.23#ibcon#read 3, iclass 16, count 0 2006.201.10:16:30.23#ibcon#about to read 4, iclass 16, count 0 2006.201.10:16:30.23#ibcon#read 4, iclass 16, count 0 2006.201.10:16:30.23#ibcon#about to read 5, iclass 16, count 0 2006.201.10:16:30.23#ibcon#read 5, iclass 16, count 0 2006.201.10:16:30.23#ibcon#about to read 6, iclass 16, count 0 2006.201.10:16:30.23#ibcon#read 6, iclass 16, count 0 2006.201.10:16:30.23#ibcon#end of sib2, iclass 16, count 0 2006.201.10:16:30.23#ibcon#*after write, iclass 16, count 0 2006.201.10:16:30.23#ibcon#*before return 0, iclass 16, count 0 2006.201.10:16:30.23#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:30.23#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:30.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:16:30.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:16:30.23$vck44/valo=5,734.99 2006.201.10:16:30.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.10:16:30.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.10:16:30.23#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:30.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:30.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:30.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:30.23#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:16:30.23#ibcon#first serial, iclass 18, count 0 2006.201.10:16:30.23#ibcon#enter sib2, iclass 18, count 0 2006.201.10:16:30.23#ibcon#flushed, iclass 18, count 0 2006.201.10:16:30.23#ibcon#about to write, iclass 18, count 0 2006.201.10:16:30.23#ibcon#wrote, iclass 18, count 0 2006.201.10:16:30.23#ibcon#about to read 3, iclass 18, count 0 2006.201.10:16:30.25#ibcon#read 3, iclass 18, count 0 2006.201.10:16:30.25#ibcon#about to read 4, iclass 18, count 0 2006.201.10:16:30.25#ibcon#read 4, iclass 18, count 0 2006.201.10:16:30.25#ibcon#about to read 5, iclass 18, count 0 2006.201.10:16:30.25#ibcon#read 5, iclass 18, count 0 2006.201.10:16:30.25#ibcon#about to read 6, iclass 18, count 0 2006.201.10:16:30.25#ibcon#read 6, iclass 18, count 0 2006.201.10:16:30.25#ibcon#end of sib2, iclass 18, count 0 2006.201.10:16:30.25#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:16:30.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:16:30.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:16:30.25#ibcon#*before write, iclass 18, count 0 2006.201.10:16:30.25#ibcon#enter sib2, iclass 18, count 0 2006.201.10:16:30.25#ibcon#flushed, iclass 18, count 0 2006.201.10:16:30.25#ibcon#about to write, iclass 18, count 0 2006.201.10:16:30.25#ibcon#wrote, iclass 18, count 0 2006.201.10:16:30.25#ibcon#about to read 3, iclass 18, count 0 2006.201.10:16:30.29#ibcon#read 3, iclass 18, count 0 2006.201.10:16:30.29#ibcon#about to read 4, iclass 18, count 0 2006.201.10:16:30.29#ibcon#read 4, iclass 18, count 0 2006.201.10:16:30.29#ibcon#about to read 5, iclass 18, count 0 2006.201.10:16:30.29#ibcon#read 5, iclass 18, count 0 2006.201.10:16:30.29#ibcon#about to read 6, iclass 18, count 0 2006.201.10:16:30.29#ibcon#read 6, iclass 18, count 0 2006.201.10:16:30.29#ibcon#end of sib2, iclass 18, count 0 2006.201.10:16:30.29#ibcon#*after write, iclass 18, count 0 2006.201.10:16:30.29#ibcon#*before return 0, iclass 18, count 0 2006.201.10:16:30.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:30.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:30.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:16:30.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:16:30.29$vck44/va=5,4 2006.201.10:16:30.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.10:16:30.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.10:16:30.29#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:30.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:30.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:30.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:30.35#ibcon#enter wrdev, iclass 20, count 2 2006.201.10:16:30.35#ibcon#first serial, iclass 20, count 2 2006.201.10:16:30.35#ibcon#enter sib2, iclass 20, count 2 2006.201.10:16:30.35#ibcon#flushed, iclass 20, count 2 2006.201.10:16:30.35#ibcon#about to write, iclass 20, count 2 2006.201.10:16:30.35#ibcon#wrote, iclass 20, count 2 2006.201.10:16:30.35#ibcon#about to read 3, iclass 20, count 2 2006.201.10:16:30.37#ibcon#read 3, iclass 20, count 2 2006.201.10:16:30.37#ibcon#about to read 4, iclass 20, count 2 2006.201.10:16:30.37#ibcon#read 4, iclass 20, count 2 2006.201.10:16:30.37#ibcon#about to read 5, iclass 20, count 2 2006.201.10:16:30.37#ibcon#read 5, iclass 20, count 2 2006.201.10:16:30.37#ibcon#about to read 6, iclass 20, count 2 2006.201.10:16:30.37#ibcon#read 6, iclass 20, count 2 2006.201.10:16:30.37#ibcon#end of sib2, iclass 20, count 2 2006.201.10:16:30.37#ibcon#*mode == 0, iclass 20, count 2 2006.201.10:16:30.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.10:16:30.37#ibcon#[25=AT05-04\r\n] 2006.201.10:16:30.37#ibcon#*before write, iclass 20, count 2 2006.201.10:16:30.37#ibcon#enter sib2, iclass 20, count 2 2006.201.10:16:30.37#ibcon#flushed, iclass 20, count 2 2006.201.10:16:30.37#ibcon#about to write, iclass 20, count 2 2006.201.10:16:30.37#ibcon#wrote, iclass 20, count 2 2006.201.10:16:30.37#ibcon#about to read 3, iclass 20, count 2 2006.201.10:16:30.40#ibcon#read 3, iclass 20, count 2 2006.201.10:16:30.40#ibcon#about to read 4, iclass 20, count 2 2006.201.10:16:30.40#ibcon#read 4, iclass 20, count 2 2006.201.10:16:30.40#ibcon#about to read 5, iclass 20, count 2 2006.201.10:16:30.40#ibcon#read 5, iclass 20, count 2 2006.201.10:16:30.40#ibcon#about to read 6, iclass 20, count 2 2006.201.10:16:30.40#ibcon#read 6, iclass 20, count 2 2006.201.10:16:30.40#ibcon#end of sib2, iclass 20, count 2 2006.201.10:16:30.40#ibcon#*after write, iclass 20, count 2 2006.201.10:16:30.40#ibcon#*before return 0, iclass 20, count 2 2006.201.10:16:30.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:30.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:30.40#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.10:16:30.40#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:30.40#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:30.52#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:30.52#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:30.52#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:16:30.52#ibcon#first serial, iclass 20, count 0 2006.201.10:16:30.52#ibcon#enter sib2, iclass 20, count 0 2006.201.10:16:30.52#ibcon#flushed, iclass 20, count 0 2006.201.10:16:30.52#ibcon#about to write, iclass 20, count 0 2006.201.10:16:30.52#ibcon#wrote, iclass 20, count 0 2006.201.10:16:30.52#ibcon#about to read 3, iclass 20, count 0 2006.201.10:16:30.54#ibcon#read 3, iclass 20, count 0 2006.201.10:16:30.54#ibcon#about to read 4, iclass 20, count 0 2006.201.10:16:30.54#ibcon#read 4, iclass 20, count 0 2006.201.10:16:30.54#ibcon#about to read 5, iclass 20, count 0 2006.201.10:16:30.54#ibcon#read 5, iclass 20, count 0 2006.201.10:16:30.54#ibcon#about to read 6, iclass 20, count 0 2006.201.10:16:30.54#ibcon#read 6, iclass 20, count 0 2006.201.10:16:30.54#ibcon#end of sib2, iclass 20, count 0 2006.201.10:16:30.54#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:16:30.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:16:30.54#ibcon#[25=USB\r\n] 2006.201.10:16:30.54#ibcon#*before write, iclass 20, count 0 2006.201.10:16:30.54#ibcon#enter sib2, iclass 20, count 0 2006.201.10:16:30.54#ibcon#flushed, iclass 20, count 0 2006.201.10:16:30.54#ibcon#about to write, iclass 20, count 0 2006.201.10:16:30.54#ibcon#wrote, iclass 20, count 0 2006.201.10:16:30.54#ibcon#about to read 3, iclass 20, count 0 2006.201.10:16:30.57#ibcon#read 3, iclass 20, count 0 2006.201.10:16:30.57#ibcon#about to read 4, iclass 20, count 0 2006.201.10:16:30.57#ibcon#read 4, iclass 20, count 0 2006.201.10:16:30.57#ibcon#about to read 5, iclass 20, count 0 2006.201.10:16:30.57#ibcon#read 5, iclass 20, count 0 2006.201.10:16:30.57#ibcon#about to read 6, iclass 20, count 0 2006.201.10:16:30.57#ibcon#read 6, iclass 20, count 0 2006.201.10:16:30.57#ibcon#end of sib2, iclass 20, count 0 2006.201.10:16:30.57#ibcon#*after write, iclass 20, count 0 2006.201.10:16:30.57#ibcon#*before return 0, iclass 20, count 0 2006.201.10:16:30.57#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:30.57#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:30.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:16:30.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:16:30.57$vck44/valo=6,814.99 2006.201.10:16:30.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.10:16:30.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.10:16:30.57#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:30.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:30.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:30.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:30.57#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:16:30.57#ibcon#first serial, iclass 22, count 0 2006.201.10:16:30.57#ibcon#enter sib2, iclass 22, count 0 2006.201.10:16:30.57#ibcon#flushed, iclass 22, count 0 2006.201.10:16:30.57#ibcon#about to write, iclass 22, count 0 2006.201.10:16:30.57#ibcon#wrote, iclass 22, count 0 2006.201.10:16:30.57#ibcon#about to read 3, iclass 22, count 0 2006.201.10:16:30.59#ibcon#read 3, iclass 22, count 0 2006.201.10:16:30.59#ibcon#about to read 4, iclass 22, count 0 2006.201.10:16:30.59#ibcon#read 4, iclass 22, count 0 2006.201.10:16:30.59#ibcon#about to read 5, iclass 22, count 0 2006.201.10:16:30.59#ibcon#read 5, iclass 22, count 0 2006.201.10:16:30.59#ibcon#about to read 6, iclass 22, count 0 2006.201.10:16:30.59#ibcon#read 6, iclass 22, count 0 2006.201.10:16:30.59#ibcon#end of sib2, iclass 22, count 0 2006.201.10:16:30.59#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:16:30.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:16:30.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:16:30.59#ibcon#*before write, iclass 22, count 0 2006.201.10:16:30.59#ibcon#enter sib2, iclass 22, count 0 2006.201.10:16:30.59#ibcon#flushed, iclass 22, count 0 2006.201.10:16:30.59#ibcon#about to write, iclass 22, count 0 2006.201.10:16:30.59#ibcon#wrote, iclass 22, count 0 2006.201.10:16:30.59#ibcon#about to read 3, iclass 22, count 0 2006.201.10:16:30.64#ibcon#read 3, iclass 22, count 0 2006.201.10:16:30.64#ibcon#about to read 4, iclass 22, count 0 2006.201.10:16:30.64#ibcon#read 4, iclass 22, count 0 2006.201.10:16:30.64#ibcon#about to read 5, iclass 22, count 0 2006.201.10:16:30.64#ibcon#read 5, iclass 22, count 0 2006.201.10:16:30.64#ibcon#about to read 6, iclass 22, count 0 2006.201.10:16:30.64#ibcon#read 6, iclass 22, count 0 2006.201.10:16:30.64#ibcon#end of sib2, iclass 22, count 0 2006.201.10:16:30.64#ibcon#*after write, iclass 22, count 0 2006.201.10:16:30.64#ibcon#*before return 0, iclass 22, count 0 2006.201.10:16:30.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:30.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:30.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:16:30.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:16:30.64$vck44/va=6,5 2006.201.10:16:30.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.10:16:30.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.10:16:30.64#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:30.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:30.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:30.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:30.69#ibcon#enter wrdev, iclass 24, count 2 2006.201.10:16:30.69#ibcon#first serial, iclass 24, count 2 2006.201.10:16:30.69#ibcon#enter sib2, iclass 24, count 2 2006.201.10:16:30.69#ibcon#flushed, iclass 24, count 2 2006.201.10:16:30.69#ibcon#about to write, iclass 24, count 2 2006.201.10:16:30.69#ibcon#wrote, iclass 24, count 2 2006.201.10:16:30.69#ibcon#about to read 3, iclass 24, count 2 2006.201.10:16:30.71#ibcon#read 3, iclass 24, count 2 2006.201.10:16:30.71#ibcon#about to read 4, iclass 24, count 2 2006.201.10:16:30.71#ibcon#read 4, iclass 24, count 2 2006.201.10:16:30.71#ibcon#about to read 5, iclass 24, count 2 2006.201.10:16:30.71#ibcon#read 5, iclass 24, count 2 2006.201.10:16:30.71#ibcon#about to read 6, iclass 24, count 2 2006.201.10:16:30.71#ibcon#read 6, iclass 24, count 2 2006.201.10:16:30.71#ibcon#end of sib2, iclass 24, count 2 2006.201.10:16:30.71#ibcon#*mode == 0, iclass 24, count 2 2006.201.10:16:30.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.10:16:30.71#ibcon#[25=AT06-05\r\n] 2006.201.10:16:30.71#ibcon#*before write, iclass 24, count 2 2006.201.10:16:30.71#ibcon#enter sib2, iclass 24, count 2 2006.201.10:16:30.71#ibcon#flushed, iclass 24, count 2 2006.201.10:16:30.71#ibcon#about to write, iclass 24, count 2 2006.201.10:16:30.71#ibcon#wrote, iclass 24, count 2 2006.201.10:16:30.71#ibcon#about to read 3, iclass 24, count 2 2006.201.10:16:30.74#ibcon#read 3, iclass 24, count 2 2006.201.10:16:30.74#ibcon#about to read 4, iclass 24, count 2 2006.201.10:16:30.74#ibcon#read 4, iclass 24, count 2 2006.201.10:16:30.74#ibcon#about to read 5, iclass 24, count 2 2006.201.10:16:30.74#ibcon#read 5, iclass 24, count 2 2006.201.10:16:30.74#ibcon#about to read 6, iclass 24, count 2 2006.201.10:16:30.74#ibcon#read 6, iclass 24, count 2 2006.201.10:16:30.74#ibcon#end of sib2, iclass 24, count 2 2006.201.10:16:30.74#ibcon#*after write, iclass 24, count 2 2006.201.10:16:30.74#ibcon#*before return 0, iclass 24, count 2 2006.201.10:16:30.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:30.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:30.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.10:16:30.74#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:30.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:30.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:30.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:30.86#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:16:30.86#ibcon#first serial, iclass 24, count 0 2006.201.10:16:30.86#ibcon#enter sib2, iclass 24, count 0 2006.201.10:16:30.86#ibcon#flushed, iclass 24, count 0 2006.201.10:16:30.86#ibcon#about to write, iclass 24, count 0 2006.201.10:16:30.86#ibcon#wrote, iclass 24, count 0 2006.201.10:16:30.86#ibcon#about to read 3, iclass 24, count 0 2006.201.10:16:30.88#ibcon#read 3, iclass 24, count 0 2006.201.10:16:30.88#ibcon#about to read 4, iclass 24, count 0 2006.201.10:16:30.88#ibcon#read 4, iclass 24, count 0 2006.201.10:16:30.88#ibcon#about to read 5, iclass 24, count 0 2006.201.10:16:30.88#ibcon#read 5, iclass 24, count 0 2006.201.10:16:30.88#ibcon#about to read 6, iclass 24, count 0 2006.201.10:16:30.88#ibcon#read 6, iclass 24, count 0 2006.201.10:16:30.88#ibcon#end of sib2, iclass 24, count 0 2006.201.10:16:30.88#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:16:30.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:16:30.88#ibcon#[25=USB\r\n] 2006.201.10:16:30.88#ibcon#*before write, iclass 24, count 0 2006.201.10:16:30.88#ibcon#enter sib2, iclass 24, count 0 2006.201.10:16:30.88#ibcon#flushed, iclass 24, count 0 2006.201.10:16:30.88#ibcon#about to write, iclass 24, count 0 2006.201.10:16:30.88#ibcon#wrote, iclass 24, count 0 2006.201.10:16:30.88#ibcon#about to read 3, iclass 24, count 0 2006.201.10:16:30.91#ibcon#read 3, iclass 24, count 0 2006.201.10:16:30.91#ibcon#about to read 4, iclass 24, count 0 2006.201.10:16:30.91#ibcon#read 4, iclass 24, count 0 2006.201.10:16:30.91#ibcon#about to read 5, iclass 24, count 0 2006.201.10:16:30.91#ibcon#read 5, iclass 24, count 0 2006.201.10:16:30.91#ibcon#about to read 6, iclass 24, count 0 2006.201.10:16:30.91#ibcon#read 6, iclass 24, count 0 2006.201.10:16:30.91#ibcon#end of sib2, iclass 24, count 0 2006.201.10:16:30.91#ibcon#*after write, iclass 24, count 0 2006.201.10:16:30.91#ibcon#*before return 0, iclass 24, count 0 2006.201.10:16:30.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:30.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:30.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:16:30.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:16:30.91$vck44/valo=7,864.99 2006.201.10:16:30.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.10:16:30.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.10:16:30.91#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:30.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:30.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:30.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:30.91#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:16:30.91#ibcon#first serial, iclass 26, count 0 2006.201.10:16:30.91#ibcon#enter sib2, iclass 26, count 0 2006.201.10:16:30.91#ibcon#flushed, iclass 26, count 0 2006.201.10:16:30.91#ibcon#about to write, iclass 26, count 0 2006.201.10:16:30.91#ibcon#wrote, iclass 26, count 0 2006.201.10:16:30.91#ibcon#about to read 3, iclass 26, count 0 2006.201.10:16:30.93#ibcon#read 3, iclass 26, count 0 2006.201.10:16:30.93#ibcon#about to read 4, iclass 26, count 0 2006.201.10:16:30.93#ibcon#read 4, iclass 26, count 0 2006.201.10:16:30.93#ibcon#about to read 5, iclass 26, count 0 2006.201.10:16:30.93#ibcon#read 5, iclass 26, count 0 2006.201.10:16:30.93#ibcon#about to read 6, iclass 26, count 0 2006.201.10:16:30.93#ibcon#read 6, iclass 26, count 0 2006.201.10:16:30.93#ibcon#end of sib2, iclass 26, count 0 2006.201.10:16:30.93#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:16:30.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:16:30.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:16:30.93#ibcon#*before write, iclass 26, count 0 2006.201.10:16:30.93#ibcon#enter sib2, iclass 26, count 0 2006.201.10:16:30.93#ibcon#flushed, iclass 26, count 0 2006.201.10:16:30.93#ibcon#about to write, iclass 26, count 0 2006.201.10:16:30.93#ibcon#wrote, iclass 26, count 0 2006.201.10:16:30.93#ibcon#about to read 3, iclass 26, count 0 2006.201.10:16:30.98#ibcon#read 3, iclass 26, count 0 2006.201.10:16:30.98#ibcon#about to read 4, iclass 26, count 0 2006.201.10:16:30.98#ibcon#read 4, iclass 26, count 0 2006.201.10:16:30.98#ibcon#about to read 5, iclass 26, count 0 2006.201.10:16:30.98#ibcon#read 5, iclass 26, count 0 2006.201.10:16:30.98#ibcon#about to read 6, iclass 26, count 0 2006.201.10:16:30.98#ibcon#read 6, iclass 26, count 0 2006.201.10:16:30.98#ibcon#end of sib2, iclass 26, count 0 2006.201.10:16:30.98#ibcon#*after write, iclass 26, count 0 2006.201.10:16:30.98#ibcon#*before return 0, iclass 26, count 0 2006.201.10:16:30.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:30.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:30.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:16:30.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:16:30.98$vck44/va=7,5 2006.201.10:16:30.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.10:16:30.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.10:16:30.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:30.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:31.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:31.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:31.03#ibcon#enter wrdev, iclass 28, count 2 2006.201.10:16:31.03#ibcon#first serial, iclass 28, count 2 2006.201.10:16:31.03#ibcon#enter sib2, iclass 28, count 2 2006.201.10:16:31.03#ibcon#flushed, iclass 28, count 2 2006.201.10:16:31.03#ibcon#about to write, iclass 28, count 2 2006.201.10:16:31.03#ibcon#wrote, iclass 28, count 2 2006.201.10:16:31.03#ibcon#about to read 3, iclass 28, count 2 2006.201.10:16:31.05#ibcon#read 3, iclass 28, count 2 2006.201.10:16:31.05#ibcon#about to read 4, iclass 28, count 2 2006.201.10:16:31.05#ibcon#read 4, iclass 28, count 2 2006.201.10:16:31.05#ibcon#about to read 5, iclass 28, count 2 2006.201.10:16:31.05#ibcon#read 5, iclass 28, count 2 2006.201.10:16:31.05#ibcon#about to read 6, iclass 28, count 2 2006.201.10:16:31.05#ibcon#read 6, iclass 28, count 2 2006.201.10:16:31.05#ibcon#end of sib2, iclass 28, count 2 2006.201.10:16:31.05#ibcon#*mode == 0, iclass 28, count 2 2006.201.10:16:31.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.10:16:31.05#ibcon#[25=AT07-05\r\n] 2006.201.10:16:31.05#ibcon#*before write, iclass 28, count 2 2006.201.10:16:31.05#ibcon#enter sib2, iclass 28, count 2 2006.201.10:16:31.05#ibcon#flushed, iclass 28, count 2 2006.201.10:16:31.05#ibcon#about to write, iclass 28, count 2 2006.201.10:16:31.05#ibcon#wrote, iclass 28, count 2 2006.201.10:16:31.05#ibcon#about to read 3, iclass 28, count 2 2006.201.10:16:31.08#ibcon#read 3, iclass 28, count 2 2006.201.10:16:31.08#ibcon#about to read 4, iclass 28, count 2 2006.201.10:16:31.08#ibcon#read 4, iclass 28, count 2 2006.201.10:16:31.08#ibcon#about to read 5, iclass 28, count 2 2006.201.10:16:31.08#ibcon#read 5, iclass 28, count 2 2006.201.10:16:31.08#ibcon#about to read 6, iclass 28, count 2 2006.201.10:16:31.08#ibcon#read 6, iclass 28, count 2 2006.201.10:16:31.08#ibcon#end of sib2, iclass 28, count 2 2006.201.10:16:31.08#ibcon#*after write, iclass 28, count 2 2006.201.10:16:31.08#ibcon#*before return 0, iclass 28, count 2 2006.201.10:16:31.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:31.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:31.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.10:16:31.08#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:31.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:31.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:31.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:31.20#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:16:31.20#ibcon#first serial, iclass 28, count 0 2006.201.10:16:31.20#ibcon#enter sib2, iclass 28, count 0 2006.201.10:16:31.20#ibcon#flushed, iclass 28, count 0 2006.201.10:16:31.20#ibcon#about to write, iclass 28, count 0 2006.201.10:16:31.20#ibcon#wrote, iclass 28, count 0 2006.201.10:16:31.20#ibcon#about to read 3, iclass 28, count 0 2006.201.10:16:31.22#ibcon#read 3, iclass 28, count 0 2006.201.10:16:31.22#ibcon#about to read 4, iclass 28, count 0 2006.201.10:16:31.22#ibcon#read 4, iclass 28, count 0 2006.201.10:16:31.22#ibcon#about to read 5, iclass 28, count 0 2006.201.10:16:31.22#ibcon#read 5, iclass 28, count 0 2006.201.10:16:31.22#ibcon#about to read 6, iclass 28, count 0 2006.201.10:16:31.22#ibcon#read 6, iclass 28, count 0 2006.201.10:16:31.22#ibcon#end of sib2, iclass 28, count 0 2006.201.10:16:31.22#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:16:31.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:16:31.22#ibcon#[25=USB\r\n] 2006.201.10:16:31.22#ibcon#*before write, iclass 28, count 0 2006.201.10:16:31.22#ibcon#enter sib2, iclass 28, count 0 2006.201.10:16:31.22#ibcon#flushed, iclass 28, count 0 2006.201.10:16:31.22#ibcon#about to write, iclass 28, count 0 2006.201.10:16:31.22#ibcon#wrote, iclass 28, count 0 2006.201.10:16:31.22#ibcon#about to read 3, iclass 28, count 0 2006.201.10:16:31.25#ibcon#read 3, iclass 28, count 0 2006.201.10:16:31.25#ibcon#about to read 4, iclass 28, count 0 2006.201.10:16:31.25#ibcon#read 4, iclass 28, count 0 2006.201.10:16:31.25#ibcon#about to read 5, iclass 28, count 0 2006.201.10:16:31.25#ibcon#read 5, iclass 28, count 0 2006.201.10:16:31.25#ibcon#about to read 6, iclass 28, count 0 2006.201.10:16:31.25#ibcon#read 6, iclass 28, count 0 2006.201.10:16:31.25#ibcon#end of sib2, iclass 28, count 0 2006.201.10:16:31.25#ibcon#*after write, iclass 28, count 0 2006.201.10:16:31.25#ibcon#*before return 0, iclass 28, count 0 2006.201.10:16:31.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:31.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:31.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:16:31.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:16:31.25$vck44/valo=8,884.99 2006.201.10:16:31.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.10:16:31.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.10:16:31.25#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:31.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:31.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:31.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:31.25#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:16:31.25#ibcon#first serial, iclass 30, count 0 2006.201.10:16:31.25#ibcon#enter sib2, iclass 30, count 0 2006.201.10:16:31.25#ibcon#flushed, iclass 30, count 0 2006.201.10:16:31.25#ibcon#about to write, iclass 30, count 0 2006.201.10:16:31.25#ibcon#wrote, iclass 30, count 0 2006.201.10:16:31.25#ibcon#about to read 3, iclass 30, count 0 2006.201.10:16:31.27#ibcon#read 3, iclass 30, count 0 2006.201.10:16:31.27#ibcon#about to read 4, iclass 30, count 0 2006.201.10:16:31.27#ibcon#read 4, iclass 30, count 0 2006.201.10:16:31.27#ibcon#about to read 5, iclass 30, count 0 2006.201.10:16:31.27#ibcon#read 5, iclass 30, count 0 2006.201.10:16:31.27#ibcon#about to read 6, iclass 30, count 0 2006.201.10:16:31.27#ibcon#read 6, iclass 30, count 0 2006.201.10:16:31.27#ibcon#end of sib2, iclass 30, count 0 2006.201.10:16:31.27#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:16:31.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:16:31.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:16:31.27#ibcon#*before write, iclass 30, count 0 2006.201.10:16:31.27#ibcon#enter sib2, iclass 30, count 0 2006.201.10:16:31.27#ibcon#flushed, iclass 30, count 0 2006.201.10:16:31.27#ibcon#about to write, iclass 30, count 0 2006.201.10:16:31.27#ibcon#wrote, iclass 30, count 0 2006.201.10:16:31.27#ibcon#about to read 3, iclass 30, count 0 2006.201.10:16:31.31#ibcon#read 3, iclass 30, count 0 2006.201.10:16:31.31#ibcon#about to read 4, iclass 30, count 0 2006.201.10:16:31.31#ibcon#read 4, iclass 30, count 0 2006.201.10:16:31.31#ibcon#about to read 5, iclass 30, count 0 2006.201.10:16:31.31#ibcon#read 5, iclass 30, count 0 2006.201.10:16:31.31#ibcon#about to read 6, iclass 30, count 0 2006.201.10:16:31.31#ibcon#read 6, iclass 30, count 0 2006.201.10:16:31.31#ibcon#end of sib2, iclass 30, count 0 2006.201.10:16:31.31#ibcon#*after write, iclass 30, count 0 2006.201.10:16:31.31#ibcon#*before return 0, iclass 30, count 0 2006.201.10:16:31.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:31.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:31.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:16:31.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:16:31.31$vck44/va=8,4 2006.201.10:16:31.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.10:16:31.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.10:16:31.31#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:31.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:16:31.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:16:31.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:16:31.37#ibcon#enter wrdev, iclass 32, count 2 2006.201.10:16:31.37#ibcon#first serial, iclass 32, count 2 2006.201.10:16:31.37#ibcon#enter sib2, iclass 32, count 2 2006.201.10:16:31.37#ibcon#flushed, iclass 32, count 2 2006.201.10:16:31.37#ibcon#about to write, iclass 32, count 2 2006.201.10:16:31.37#ibcon#wrote, iclass 32, count 2 2006.201.10:16:31.37#ibcon#about to read 3, iclass 32, count 2 2006.201.10:16:31.39#ibcon#read 3, iclass 32, count 2 2006.201.10:16:31.39#ibcon#about to read 4, iclass 32, count 2 2006.201.10:16:31.39#ibcon#read 4, iclass 32, count 2 2006.201.10:16:31.39#ibcon#about to read 5, iclass 32, count 2 2006.201.10:16:31.39#ibcon#read 5, iclass 32, count 2 2006.201.10:16:31.39#ibcon#about to read 6, iclass 32, count 2 2006.201.10:16:31.39#ibcon#read 6, iclass 32, count 2 2006.201.10:16:31.39#ibcon#end of sib2, iclass 32, count 2 2006.201.10:16:31.39#ibcon#*mode == 0, iclass 32, count 2 2006.201.10:16:31.39#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.10:16:31.39#ibcon#[25=AT08-04\r\n] 2006.201.10:16:31.39#ibcon#*before write, iclass 32, count 2 2006.201.10:16:31.39#ibcon#enter sib2, iclass 32, count 2 2006.201.10:16:31.39#ibcon#flushed, iclass 32, count 2 2006.201.10:16:31.39#ibcon#about to write, iclass 32, count 2 2006.201.10:16:31.39#ibcon#wrote, iclass 32, count 2 2006.201.10:16:31.39#ibcon#about to read 3, iclass 32, count 2 2006.201.10:16:31.42#ibcon#read 3, iclass 32, count 2 2006.201.10:16:31.42#ibcon#about to read 4, iclass 32, count 2 2006.201.10:16:31.42#ibcon#read 4, iclass 32, count 2 2006.201.10:16:31.42#ibcon#about to read 5, iclass 32, count 2 2006.201.10:16:31.42#ibcon#read 5, iclass 32, count 2 2006.201.10:16:31.42#ibcon#about to read 6, iclass 32, count 2 2006.201.10:16:31.42#ibcon#read 6, iclass 32, count 2 2006.201.10:16:31.42#ibcon#end of sib2, iclass 32, count 2 2006.201.10:16:31.42#ibcon#*after write, iclass 32, count 2 2006.201.10:16:31.42#ibcon#*before return 0, iclass 32, count 2 2006.201.10:16:31.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:16:31.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:16:31.42#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.10:16:31.42#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:31.42#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:16:31.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:16:31.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:16:31.54#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:16:31.54#ibcon#first serial, iclass 32, count 0 2006.201.10:16:31.54#ibcon#enter sib2, iclass 32, count 0 2006.201.10:16:31.54#ibcon#flushed, iclass 32, count 0 2006.201.10:16:31.54#ibcon#about to write, iclass 32, count 0 2006.201.10:16:31.54#ibcon#wrote, iclass 32, count 0 2006.201.10:16:31.54#ibcon#about to read 3, iclass 32, count 0 2006.201.10:16:31.56#ibcon#read 3, iclass 32, count 0 2006.201.10:16:31.56#ibcon#about to read 4, iclass 32, count 0 2006.201.10:16:31.56#ibcon#read 4, iclass 32, count 0 2006.201.10:16:31.56#ibcon#about to read 5, iclass 32, count 0 2006.201.10:16:31.56#ibcon#read 5, iclass 32, count 0 2006.201.10:16:31.56#ibcon#about to read 6, iclass 32, count 0 2006.201.10:16:31.56#ibcon#read 6, iclass 32, count 0 2006.201.10:16:31.56#ibcon#end of sib2, iclass 32, count 0 2006.201.10:16:31.56#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:16:31.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:16:31.56#ibcon#[25=USB\r\n] 2006.201.10:16:31.56#ibcon#*before write, iclass 32, count 0 2006.201.10:16:31.56#ibcon#enter sib2, iclass 32, count 0 2006.201.10:16:31.56#ibcon#flushed, iclass 32, count 0 2006.201.10:16:31.56#ibcon#about to write, iclass 32, count 0 2006.201.10:16:31.56#ibcon#wrote, iclass 32, count 0 2006.201.10:16:31.56#ibcon#about to read 3, iclass 32, count 0 2006.201.10:16:31.59#ibcon#read 3, iclass 32, count 0 2006.201.10:16:31.59#ibcon#about to read 4, iclass 32, count 0 2006.201.10:16:31.59#ibcon#read 4, iclass 32, count 0 2006.201.10:16:31.59#ibcon#about to read 5, iclass 32, count 0 2006.201.10:16:31.59#ibcon#read 5, iclass 32, count 0 2006.201.10:16:31.59#ibcon#about to read 6, iclass 32, count 0 2006.201.10:16:31.59#ibcon#read 6, iclass 32, count 0 2006.201.10:16:31.59#ibcon#end of sib2, iclass 32, count 0 2006.201.10:16:31.59#ibcon#*after write, iclass 32, count 0 2006.201.10:16:31.59#ibcon#*before return 0, iclass 32, count 0 2006.201.10:16:31.59#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:16:31.59#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:16:31.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:16:31.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:16:31.59$vck44/vblo=1,629.99 2006.201.10:16:31.59#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.10:16:31.59#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.10:16:31.59#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:31.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:16:31.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:16:31.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:16:31.59#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:16:31.59#ibcon#first serial, iclass 34, count 0 2006.201.10:16:31.59#ibcon#enter sib2, iclass 34, count 0 2006.201.10:16:31.59#ibcon#flushed, iclass 34, count 0 2006.201.10:16:31.59#ibcon#about to write, iclass 34, count 0 2006.201.10:16:31.59#ibcon#wrote, iclass 34, count 0 2006.201.10:16:31.59#ibcon#about to read 3, iclass 34, count 0 2006.201.10:16:31.61#ibcon#read 3, iclass 34, count 0 2006.201.10:16:31.61#ibcon#about to read 4, iclass 34, count 0 2006.201.10:16:31.61#ibcon#read 4, iclass 34, count 0 2006.201.10:16:31.61#ibcon#about to read 5, iclass 34, count 0 2006.201.10:16:31.61#ibcon#read 5, iclass 34, count 0 2006.201.10:16:31.61#ibcon#about to read 6, iclass 34, count 0 2006.201.10:16:31.61#ibcon#read 6, iclass 34, count 0 2006.201.10:16:31.61#ibcon#end of sib2, iclass 34, count 0 2006.201.10:16:31.61#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:16:31.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:16:31.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:16:31.61#ibcon#*before write, iclass 34, count 0 2006.201.10:16:31.61#ibcon#enter sib2, iclass 34, count 0 2006.201.10:16:31.61#ibcon#flushed, iclass 34, count 0 2006.201.10:16:31.61#ibcon#about to write, iclass 34, count 0 2006.201.10:16:31.61#ibcon#wrote, iclass 34, count 0 2006.201.10:16:31.61#ibcon#about to read 3, iclass 34, count 0 2006.201.10:16:31.66#ibcon#read 3, iclass 34, count 0 2006.201.10:16:31.66#ibcon#about to read 4, iclass 34, count 0 2006.201.10:16:31.66#ibcon#read 4, iclass 34, count 0 2006.201.10:16:31.66#ibcon#about to read 5, iclass 34, count 0 2006.201.10:16:31.66#ibcon#read 5, iclass 34, count 0 2006.201.10:16:31.66#ibcon#about to read 6, iclass 34, count 0 2006.201.10:16:31.66#ibcon#read 6, iclass 34, count 0 2006.201.10:16:31.66#ibcon#end of sib2, iclass 34, count 0 2006.201.10:16:31.66#ibcon#*after write, iclass 34, count 0 2006.201.10:16:31.66#ibcon#*before return 0, iclass 34, count 0 2006.201.10:16:31.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:16:31.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:16:31.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:16:31.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:16:31.66$vck44/vb=1,4 2006.201.10:16:31.66#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.10:16:31.66#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.10:16:31.66#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:31.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:16:31.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:16:31.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:16:31.66#ibcon#enter wrdev, iclass 36, count 2 2006.201.10:16:31.66#ibcon#first serial, iclass 36, count 2 2006.201.10:16:31.66#ibcon#enter sib2, iclass 36, count 2 2006.201.10:16:31.66#ibcon#flushed, iclass 36, count 2 2006.201.10:16:31.66#ibcon#about to write, iclass 36, count 2 2006.201.10:16:31.66#ibcon#wrote, iclass 36, count 2 2006.201.10:16:31.66#ibcon#about to read 3, iclass 36, count 2 2006.201.10:16:31.68#ibcon#read 3, iclass 36, count 2 2006.201.10:16:31.68#ibcon#about to read 4, iclass 36, count 2 2006.201.10:16:31.68#ibcon#read 4, iclass 36, count 2 2006.201.10:16:31.68#ibcon#about to read 5, iclass 36, count 2 2006.201.10:16:31.68#ibcon#read 5, iclass 36, count 2 2006.201.10:16:31.68#ibcon#about to read 6, iclass 36, count 2 2006.201.10:16:31.68#ibcon#read 6, iclass 36, count 2 2006.201.10:16:31.68#ibcon#end of sib2, iclass 36, count 2 2006.201.10:16:31.68#ibcon#*mode == 0, iclass 36, count 2 2006.201.10:16:31.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.10:16:31.68#ibcon#[27=AT01-04\r\n] 2006.201.10:16:31.68#ibcon#*before write, iclass 36, count 2 2006.201.10:16:31.68#ibcon#enter sib2, iclass 36, count 2 2006.201.10:16:31.68#ibcon#flushed, iclass 36, count 2 2006.201.10:16:31.68#ibcon#about to write, iclass 36, count 2 2006.201.10:16:31.68#ibcon#wrote, iclass 36, count 2 2006.201.10:16:31.68#ibcon#about to read 3, iclass 36, count 2 2006.201.10:16:31.71#ibcon#read 3, iclass 36, count 2 2006.201.10:16:31.71#ibcon#about to read 4, iclass 36, count 2 2006.201.10:16:31.71#ibcon#read 4, iclass 36, count 2 2006.201.10:16:31.71#ibcon#about to read 5, iclass 36, count 2 2006.201.10:16:31.71#ibcon#read 5, iclass 36, count 2 2006.201.10:16:31.71#ibcon#about to read 6, iclass 36, count 2 2006.201.10:16:31.71#ibcon#read 6, iclass 36, count 2 2006.201.10:16:31.71#ibcon#end of sib2, iclass 36, count 2 2006.201.10:16:31.71#ibcon#*after write, iclass 36, count 2 2006.201.10:16:31.71#ibcon#*before return 0, iclass 36, count 2 2006.201.10:16:31.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:16:31.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:16:31.71#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.10:16:31.71#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:31.71#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:16:31.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:16:31.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:16:31.83#ibcon#enter wrdev, iclass 36, count 0 2006.201.10:16:31.83#ibcon#first serial, iclass 36, count 0 2006.201.10:16:31.83#ibcon#enter sib2, iclass 36, count 0 2006.201.10:16:31.83#ibcon#flushed, iclass 36, count 0 2006.201.10:16:31.83#ibcon#about to write, iclass 36, count 0 2006.201.10:16:31.83#ibcon#wrote, iclass 36, count 0 2006.201.10:16:31.83#ibcon#about to read 3, iclass 36, count 0 2006.201.10:16:31.85#ibcon#read 3, iclass 36, count 0 2006.201.10:16:31.85#ibcon#about to read 4, iclass 36, count 0 2006.201.10:16:31.85#ibcon#read 4, iclass 36, count 0 2006.201.10:16:31.85#ibcon#about to read 5, iclass 36, count 0 2006.201.10:16:31.85#ibcon#read 5, iclass 36, count 0 2006.201.10:16:31.85#ibcon#about to read 6, iclass 36, count 0 2006.201.10:16:31.85#ibcon#read 6, iclass 36, count 0 2006.201.10:16:31.85#ibcon#end of sib2, iclass 36, count 0 2006.201.10:16:31.85#ibcon#*mode == 0, iclass 36, count 0 2006.201.10:16:31.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.10:16:31.85#ibcon#[27=USB\r\n] 2006.201.10:16:31.85#ibcon#*before write, iclass 36, count 0 2006.201.10:16:31.85#ibcon#enter sib2, iclass 36, count 0 2006.201.10:16:31.85#ibcon#flushed, iclass 36, count 0 2006.201.10:16:31.85#ibcon#about to write, iclass 36, count 0 2006.201.10:16:31.85#ibcon#wrote, iclass 36, count 0 2006.201.10:16:31.85#ibcon#about to read 3, iclass 36, count 0 2006.201.10:16:31.88#ibcon#read 3, iclass 36, count 0 2006.201.10:16:31.88#ibcon#about to read 4, iclass 36, count 0 2006.201.10:16:31.88#ibcon#read 4, iclass 36, count 0 2006.201.10:16:31.88#ibcon#about to read 5, iclass 36, count 0 2006.201.10:16:31.88#ibcon#read 5, iclass 36, count 0 2006.201.10:16:31.88#ibcon#about to read 6, iclass 36, count 0 2006.201.10:16:31.88#ibcon#read 6, iclass 36, count 0 2006.201.10:16:31.88#ibcon#end of sib2, iclass 36, count 0 2006.201.10:16:31.88#ibcon#*after write, iclass 36, count 0 2006.201.10:16:31.88#ibcon#*before return 0, iclass 36, count 0 2006.201.10:16:31.88#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:16:31.88#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:16:31.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.10:16:31.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.10:16:31.88$vck44/vblo=2,634.99 2006.201.10:16:31.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.10:16:31.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.10:16:31.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:31.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:31.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:31.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:31.88#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:16:31.88#ibcon#first serial, iclass 38, count 0 2006.201.10:16:31.88#ibcon#enter sib2, iclass 38, count 0 2006.201.10:16:31.88#ibcon#flushed, iclass 38, count 0 2006.201.10:16:31.88#ibcon#about to write, iclass 38, count 0 2006.201.10:16:31.88#ibcon#wrote, iclass 38, count 0 2006.201.10:16:31.88#ibcon#about to read 3, iclass 38, count 0 2006.201.10:16:31.90#ibcon#read 3, iclass 38, count 0 2006.201.10:16:31.90#ibcon#about to read 4, iclass 38, count 0 2006.201.10:16:31.90#ibcon#read 4, iclass 38, count 0 2006.201.10:16:31.90#ibcon#about to read 5, iclass 38, count 0 2006.201.10:16:31.90#ibcon#read 5, iclass 38, count 0 2006.201.10:16:31.90#ibcon#about to read 6, iclass 38, count 0 2006.201.10:16:31.90#ibcon#read 6, iclass 38, count 0 2006.201.10:16:31.90#ibcon#end of sib2, iclass 38, count 0 2006.201.10:16:31.90#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:16:31.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:16:31.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:16:31.90#ibcon#*before write, iclass 38, count 0 2006.201.10:16:31.90#ibcon#enter sib2, iclass 38, count 0 2006.201.10:16:31.90#ibcon#flushed, iclass 38, count 0 2006.201.10:16:31.90#ibcon#about to write, iclass 38, count 0 2006.201.10:16:31.90#ibcon#wrote, iclass 38, count 0 2006.201.10:16:31.90#ibcon#about to read 3, iclass 38, count 0 2006.201.10:16:31.94#ibcon#read 3, iclass 38, count 0 2006.201.10:16:31.94#ibcon#about to read 4, iclass 38, count 0 2006.201.10:16:31.94#ibcon#read 4, iclass 38, count 0 2006.201.10:16:31.94#ibcon#about to read 5, iclass 38, count 0 2006.201.10:16:31.94#ibcon#read 5, iclass 38, count 0 2006.201.10:16:31.94#ibcon#about to read 6, iclass 38, count 0 2006.201.10:16:31.94#ibcon#read 6, iclass 38, count 0 2006.201.10:16:31.94#ibcon#end of sib2, iclass 38, count 0 2006.201.10:16:31.94#ibcon#*after write, iclass 38, count 0 2006.201.10:16:31.94#ibcon#*before return 0, iclass 38, count 0 2006.201.10:16:31.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:31.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:16:31.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:16:31.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:16:31.94$vck44/vb=2,5 2006.201.10:16:31.94#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.10:16:31.94#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.10:16:31.94#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:31.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:32.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:32.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:32.00#ibcon#enter wrdev, iclass 40, count 2 2006.201.10:16:32.00#ibcon#first serial, iclass 40, count 2 2006.201.10:16:32.00#ibcon#enter sib2, iclass 40, count 2 2006.201.10:16:32.00#ibcon#flushed, iclass 40, count 2 2006.201.10:16:32.00#ibcon#about to write, iclass 40, count 2 2006.201.10:16:32.00#ibcon#wrote, iclass 40, count 2 2006.201.10:16:32.00#ibcon#about to read 3, iclass 40, count 2 2006.201.10:16:32.02#ibcon#read 3, iclass 40, count 2 2006.201.10:16:32.02#ibcon#about to read 4, iclass 40, count 2 2006.201.10:16:32.02#ibcon#read 4, iclass 40, count 2 2006.201.10:16:32.02#ibcon#about to read 5, iclass 40, count 2 2006.201.10:16:32.02#ibcon#read 5, iclass 40, count 2 2006.201.10:16:32.02#ibcon#about to read 6, iclass 40, count 2 2006.201.10:16:32.02#ibcon#read 6, iclass 40, count 2 2006.201.10:16:32.02#ibcon#end of sib2, iclass 40, count 2 2006.201.10:16:32.02#ibcon#*mode == 0, iclass 40, count 2 2006.201.10:16:32.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.10:16:32.02#ibcon#[27=AT02-05\r\n] 2006.201.10:16:32.02#ibcon#*before write, iclass 40, count 2 2006.201.10:16:32.02#ibcon#enter sib2, iclass 40, count 2 2006.201.10:16:32.02#ibcon#flushed, iclass 40, count 2 2006.201.10:16:32.02#ibcon#about to write, iclass 40, count 2 2006.201.10:16:32.02#ibcon#wrote, iclass 40, count 2 2006.201.10:16:32.02#ibcon#about to read 3, iclass 40, count 2 2006.201.10:16:32.05#ibcon#read 3, iclass 40, count 2 2006.201.10:16:32.05#ibcon#about to read 4, iclass 40, count 2 2006.201.10:16:32.05#ibcon#read 4, iclass 40, count 2 2006.201.10:16:32.05#ibcon#about to read 5, iclass 40, count 2 2006.201.10:16:32.05#ibcon#read 5, iclass 40, count 2 2006.201.10:16:32.05#ibcon#about to read 6, iclass 40, count 2 2006.201.10:16:32.05#ibcon#read 6, iclass 40, count 2 2006.201.10:16:32.05#ibcon#end of sib2, iclass 40, count 2 2006.201.10:16:32.05#ibcon#*after write, iclass 40, count 2 2006.201.10:16:32.05#ibcon#*before return 0, iclass 40, count 2 2006.201.10:16:32.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:32.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:16:32.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.10:16:32.05#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:32.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:32.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:32.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:32.17#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:16:32.17#ibcon#first serial, iclass 40, count 0 2006.201.10:16:32.17#ibcon#enter sib2, iclass 40, count 0 2006.201.10:16:32.17#ibcon#flushed, iclass 40, count 0 2006.201.10:16:32.17#ibcon#about to write, iclass 40, count 0 2006.201.10:16:32.17#ibcon#wrote, iclass 40, count 0 2006.201.10:16:32.17#ibcon#about to read 3, iclass 40, count 0 2006.201.10:16:32.19#ibcon#read 3, iclass 40, count 0 2006.201.10:16:32.19#ibcon#about to read 4, iclass 40, count 0 2006.201.10:16:32.19#ibcon#read 4, iclass 40, count 0 2006.201.10:16:32.19#ibcon#about to read 5, iclass 40, count 0 2006.201.10:16:32.19#ibcon#read 5, iclass 40, count 0 2006.201.10:16:32.19#ibcon#about to read 6, iclass 40, count 0 2006.201.10:16:32.19#ibcon#read 6, iclass 40, count 0 2006.201.10:16:32.19#ibcon#end of sib2, iclass 40, count 0 2006.201.10:16:32.19#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:16:32.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:16:32.19#ibcon#[27=USB\r\n] 2006.201.10:16:32.19#ibcon#*before write, iclass 40, count 0 2006.201.10:16:32.19#ibcon#enter sib2, iclass 40, count 0 2006.201.10:16:32.19#ibcon#flushed, iclass 40, count 0 2006.201.10:16:32.19#ibcon#about to write, iclass 40, count 0 2006.201.10:16:32.19#ibcon#wrote, iclass 40, count 0 2006.201.10:16:32.19#ibcon#about to read 3, iclass 40, count 0 2006.201.10:16:32.22#ibcon#read 3, iclass 40, count 0 2006.201.10:16:32.22#ibcon#about to read 4, iclass 40, count 0 2006.201.10:16:32.22#ibcon#read 4, iclass 40, count 0 2006.201.10:16:32.22#ibcon#about to read 5, iclass 40, count 0 2006.201.10:16:32.22#ibcon#read 5, iclass 40, count 0 2006.201.10:16:32.22#ibcon#about to read 6, iclass 40, count 0 2006.201.10:16:32.22#ibcon#read 6, iclass 40, count 0 2006.201.10:16:32.22#ibcon#end of sib2, iclass 40, count 0 2006.201.10:16:32.22#ibcon#*after write, iclass 40, count 0 2006.201.10:16:32.22#ibcon#*before return 0, iclass 40, count 0 2006.201.10:16:32.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:32.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:16:32.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:16:32.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:16:32.22$vck44/vblo=3,649.99 2006.201.10:16:32.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.10:16:32.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.10:16:32.22#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:32.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:32.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:32.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:32.22#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:16:32.22#ibcon#first serial, iclass 4, count 0 2006.201.10:16:32.22#ibcon#enter sib2, iclass 4, count 0 2006.201.10:16:32.22#ibcon#flushed, iclass 4, count 0 2006.201.10:16:32.22#ibcon#about to write, iclass 4, count 0 2006.201.10:16:32.22#ibcon#wrote, iclass 4, count 0 2006.201.10:16:32.22#ibcon#about to read 3, iclass 4, count 0 2006.201.10:16:32.24#ibcon#read 3, iclass 4, count 0 2006.201.10:16:32.24#ibcon#about to read 4, iclass 4, count 0 2006.201.10:16:32.24#ibcon#read 4, iclass 4, count 0 2006.201.10:16:32.24#ibcon#about to read 5, iclass 4, count 0 2006.201.10:16:32.24#ibcon#read 5, iclass 4, count 0 2006.201.10:16:32.24#ibcon#about to read 6, iclass 4, count 0 2006.201.10:16:32.24#ibcon#read 6, iclass 4, count 0 2006.201.10:16:32.24#ibcon#end of sib2, iclass 4, count 0 2006.201.10:16:32.24#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:16:32.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:16:32.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:16:32.24#ibcon#*before write, iclass 4, count 0 2006.201.10:16:32.24#ibcon#enter sib2, iclass 4, count 0 2006.201.10:16:32.24#ibcon#flushed, iclass 4, count 0 2006.201.10:16:32.24#ibcon#about to write, iclass 4, count 0 2006.201.10:16:32.24#ibcon#wrote, iclass 4, count 0 2006.201.10:16:32.24#ibcon#about to read 3, iclass 4, count 0 2006.201.10:16:32.28#ibcon#read 3, iclass 4, count 0 2006.201.10:16:32.28#ibcon#about to read 4, iclass 4, count 0 2006.201.10:16:32.28#ibcon#read 4, iclass 4, count 0 2006.201.10:16:32.28#ibcon#about to read 5, iclass 4, count 0 2006.201.10:16:32.28#ibcon#read 5, iclass 4, count 0 2006.201.10:16:32.28#ibcon#about to read 6, iclass 4, count 0 2006.201.10:16:32.28#ibcon#read 6, iclass 4, count 0 2006.201.10:16:32.28#ibcon#end of sib2, iclass 4, count 0 2006.201.10:16:32.28#ibcon#*after write, iclass 4, count 0 2006.201.10:16:32.28#ibcon#*before return 0, iclass 4, count 0 2006.201.10:16:32.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:32.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:16:32.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:16:32.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:16:32.28$vck44/vb=3,4 2006.201.10:16:32.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.10:16:32.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.10:16:32.28#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:32.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:32.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:32.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:32.34#ibcon#enter wrdev, iclass 6, count 2 2006.201.10:16:32.34#ibcon#first serial, iclass 6, count 2 2006.201.10:16:32.34#ibcon#enter sib2, iclass 6, count 2 2006.201.10:16:32.34#ibcon#flushed, iclass 6, count 2 2006.201.10:16:32.34#ibcon#about to write, iclass 6, count 2 2006.201.10:16:32.34#ibcon#wrote, iclass 6, count 2 2006.201.10:16:32.34#ibcon#about to read 3, iclass 6, count 2 2006.201.10:16:32.36#ibcon#read 3, iclass 6, count 2 2006.201.10:16:32.36#ibcon#about to read 4, iclass 6, count 2 2006.201.10:16:32.36#ibcon#read 4, iclass 6, count 2 2006.201.10:16:32.36#ibcon#about to read 5, iclass 6, count 2 2006.201.10:16:32.36#ibcon#read 5, iclass 6, count 2 2006.201.10:16:32.36#ibcon#about to read 6, iclass 6, count 2 2006.201.10:16:32.36#ibcon#read 6, iclass 6, count 2 2006.201.10:16:32.36#ibcon#end of sib2, iclass 6, count 2 2006.201.10:16:32.36#ibcon#*mode == 0, iclass 6, count 2 2006.201.10:16:32.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.10:16:32.36#ibcon#[27=AT03-04\r\n] 2006.201.10:16:32.36#ibcon#*before write, iclass 6, count 2 2006.201.10:16:32.36#ibcon#enter sib2, iclass 6, count 2 2006.201.10:16:32.36#ibcon#flushed, iclass 6, count 2 2006.201.10:16:32.36#ibcon#about to write, iclass 6, count 2 2006.201.10:16:32.36#ibcon#wrote, iclass 6, count 2 2006.201.10:16:32.36#ibcon#about to read 3, iclass 6, count 2 2006.201.10:16:32.39#ibcon#read 3, iclass 6, count 2 2006.201.10:16:32.39#ibcon#about to read 4, iclass 6, count 2 2006.201.10:16:32.39#ibcon#read 4, iclass 6, count 2 2006.201.10:16:32.39#ibcon#about to read 5, iclass 6, count 2 2006.201.10:16:32.39#ibcon#read 5, iclass 6, count 2 2006.201.10:16:32.39#ibcon#about to read 6, iclass 6, count 2 2006.201.10:16:32.39#ibcon#read 6, iclass 6, count 2 2006.201.10:16:32.39#ibcon#end of sib2, iclass 6, count 2 2006.201.10:16:32.39#ibcon#*after write, iclass 6, count 2 2006.201.10:16:32.39#ibcon#*before return 0, iclass 6, count 2 2006.201.10:16:32.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:32.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:16:32.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.10:16:32.39#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:32.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:32.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:32.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:32.51#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:16:32.51#ibcon#first serial, iclass 6, count 0 2006.201.10:16:32.51#ibcon#enter sib2, iclass 6, count 0 2006.201.10:16:32.51#ibcon#flushed, iclass 6, count 0 2006.201.10:16:32.51#ibcon#about to write, iclass 6, count 0 2006.201.10:16:32.51#ibcon#wrote, iclass 6, count 0 2006.201.10:16:32.51#ibcon#about to read 3, iclass 6, count 0 2006.201.10:16:32.53#ibcon#read 3, iclass 6, count 0 2006.201.10:16:32.53#ibcon#about to read 4, iclass 6, count 0 2006.201.10:16:32.53#ibcon#read 4, iclass 6, count 0 2006.201.10:16:32.53#ibcon#about to read 5, iclass 6, count 0 2006.201.10:16:32.53#ibcon#read 5, iclass 6, count 0 2006.201.10:16:32.53#ibcon#about to read 6, iclass 6, count 0 2006.201.10:16:32.53#ibcon#read 6, iclass 6, count 0 2006.201.10:16:32.53#ibcon#end of sib2, iclass 6, count 0 2006.201.10:16:32.53#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:16:32.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:16:32.53#ibcon#[27=USB\r\n] 2006.201.10:16:32.53#ibcon#*before write, iclass 6, count 0 2006.201.10:16:32.53#ibcon#enter sib2, iclass 6, count 0 2006.201.10:16:32.53#ibcon#flushed, iclass 6, count 0 2006.201.10:16:32.53#ibcon#about to write, iclass 6, count 0 2006.201.10:16:32.53#ibcon#wrote, iclass 6, count 0 2006.201.10:16:32.53#ibcon#about to read 3, iclass 6, count 0 2006.201.10:16:32.56#ibcon#read 3, iclass 6, count 0 2006.201.10:16:32.56#ibcon#about to read 4, iclass 6, count 0 2006.201.10:16:32.56#ibcon#read 4, iclass 6, count 0 2006.201.10:16:32.56#ibcon#about to read 5, iclass 6, count 0 2006.201.10:16:32.56#ibcon#read 5, iclass 6, count 0 2006.201.10:16:32.56#ibcon#about to read 6, iclass 6, count 0 2006.201.10:16:32.56#ibcon#read 6, iclass 6, count 0 2006.201.10:16:32.56#ibcon#end of sib2, iclass 6, count 0 2006.201.10:16:32.56#ibcon#*after write, iclass 6, count 0 2006.201.10:16:32.56#ibcon#*before return 0, iclass 6, count 0 2006.201.10:16:32.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:32.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:16:32.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:16:32.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:16:32.56$vck44/vblo=4,679.99 2006.201.10:16:32.56#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.10:16:32.56#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.10:16:32.56#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:32.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:32.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:32.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:32.56#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:16:32.56#ibcon#first serial, iclass 10, count 0 2006.201.10:16:32.56#ibcon#enter sib2, iclass 10, count 0 2006.201.10:16:32.56#ibcon#flushed, iclass 10, count 0 2006.201.10:16:32.56#ibcon#about to write, iclass 10, count 0 2006.201.10:16:32.56#ibcon#wrote, iclass 10, count 0 2006.201.10:16:32.56#ibcon#about to read 3, iclass 10, count 0 2006.201.10:16:32.58#ibcon#read 3, iclass 10, count 0 2006.201.10:16:32.58#ibcon#about to read 4, iclass 10, count 0 2006.201.10:16:32.58#ibcon#read 4, iclass 10, count 0 2006.201.10:16:32.58#ibcon#about to read 5, iclass 10, count 0 2006.201.10:16:32.58#ibcon#read 5, iclass 10, count 0 2006.201.10:16:32.58#ibcon#about to read 6, iclass 10, count 0 2006.201.10:16:32.58#ibcon#read 6, iclass 10, count 0 2006.201.10:16:32.58#ibcon#end of sib2, iclass 10, count 0 2006.201.10:16:32.58#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:16:32.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:16:32.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:16:32.58#ibcon#*before write, iclass 10, count 0 2006.201.10:16:32.58#ibcon#enter sib2, iclass 10, count 0 2006.201.10:16:32.58#ibcon#flushed, iclass 10, count 0 2006.201.10:16:32.58#ibcon#about to write, iclass 10, count 0 2006.201.10:16:32.58#ibcon#wrote, iclass 10, count 0 2006.201.10:16:32.58#ibcon#about to read 3, iclass 10, count 0 2006.201.10:16:32.63#ibcon#read 3, iclass 10, count 0 2006.201.10:16:32.63#ibcon#about to read 4, iclass 10, count 0 2006.201.10:16:32.63#ibcon#read 4, iclass 10, count 0 2006.201.10:16:32.63#ibcon#about to read 5, iclass 10, count 0 2006.201.10:16:32.63#ibcon#read 5, iclass 10, count 0 2006.201.10:16:32.63#ibcon#about to read 6, iclass 10, count 0 2006.201.10:16:32.63#ibcon#read 6, iclass 10, count 0 2006.201.10:16:32.63#ibcon#end of sib2, iclass 10, count 0 2006.201.10:16:32.63#ibcon#*after write, iclass 10, count 0 2006.201.10:16:32.63#ibcon#*before return 0, iclass 10, count 0 2006.201.10:16:32.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:32.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:16:32.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:16:32.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:16:32.63$vck44/vb=4,5 2006.201.10:16:32.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.10:16:32.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.10:16:32.63#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:32.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:32.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:32.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:32.68#ibcon#enter wrdev, iclass 12, count 2 2006.201.10:16:32.68#ibcon#first serial, iclass 12, count 2 2006.201.10:16:32.68#ibcon#enter sib2, iclass 12, count 2 2006.201.10:16:32.68#ibcon#flushed, iclass 12, count 2 2006.201.10:16:32.68#ibcon#about to write, iclass 12, count 2 2006.201.10:16:32.68#ibcon#wrote, iclass 12, count 2 2006.201.10:16:32.68#ibcon#about to read 3, iclass 12, count 2 2006.201.10:16:32.70#ibcon#read 3, iclass 12, count 2 2006.201.10:16:32.70#ibcon#about to read 4, iclass 12, count 2 2006.201.10:16:32.70#ibcon#read 4, iclass 12, count 2 2006.201.10:16:32.70#ibcon#about to read 5, iclass 12, count 2 2006.201.10:16:32.70#ibcon#read 5, iclass 12, count 2 2006.201.10:16:32.70#ibcon#about to read 6, iclass 12, count 2 2006.201.10:16:32.70#ibcon#read 6, iclass 12, count 2 2006.201.10:16:32.70#ibcon#end of sib2, iclass 12, count 2 2006.201.10:16:32.70#ibcon#*mode == 0, iclass 12, count 2 2006.201.10:16:32.70#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.10:16:32.70#ibcon#[27=AT04-05\r\n] 2006.201.10:16:32.70#ibcon#*before write, iclass 12, count 2 2006.201.10:16:32.70#ibcon#enter sib2, iclass 12, count 2 2006.201.10:16:32.70#ibcon#flushed, iclass 12, count 2 2006.201.10:16:32.70#ibcon#about to write, iclass 12, count 2 2006.201.10:16:32.70#ibcon#wrote, iclass 12, count 2 2006.201.10:16:32.70#ibcon#about to read 3, iclass 12, count 2 2006.201.10:16:32.73#ibcon#read 3, iclass 12, count 2 2006.201.10:16:32.73#ibcon#about to read 4, iclass 12, count 2 2006.201.10:16:32.73#ibcon#read 4, iclass 12, count 2 2006.201.10:16:32.73#ibcon#about to read 5, iclass 12, count 2 2006.201.10:16:32.73#ibcon#read 5, iclass 12, count 2 2006.201.10:16:32.73#ibcon#about to read 6, iclass 12, count 2 2006.201.10:16:32.73#ibcon#read 6, iclass 12, count 2 2006.201.10:16:32.73#ibcon#end of sib2, iclass 12, count 2 2006.201.10:16:32.73#ibcon#*after write, iclass 12, count 2 2006.201.10:16:32.73#ibcon#*before return 0, iclass 12, count 2 2006.201.10:16:32.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:32.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:16:32.73#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.10:16:32.73#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:32.73#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:32.85#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:32.85#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:32.85#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:16:32.85#ibcon#first serial, iclass 12, count 0 2006.201.10:16:32.85#ibcon#enter sib2, iclass 12, count 0 2006.201.10:16:32.85#ibcon#flushed, iclass 12, count 0 2006.201.10:16:32.85#ibcon#about to write, iclass 12, count 0 2006.201.10:16:32.85#ibcon#wrote, iclass 12, count 0 2006.201.10:16:32.85#ibcon#about to read 3, iclass 12, count 0 2006.201.10:16:32.87#ibcon#read 3, iclass 12, count 0 2006.201.10:16:32.87#ibcon#about to read 4, iclass 12, count 0 2006.201.10:16:32.87#ibcon#read 4, iclass 12, count 0 2006.201.10:16:32.87#ibcon#about to read 5, iclass 12, count 0 2006.201.10:16:32.87#ibcon#read 5, iclass 12, count 0 2006.201.10:16:32.87#ibcon#about to read 6, iclass 12, count 0 2006.201.10:16:32.87#ibcon#read 6, iclass 12, count 0 2006.201.10:16:32.87#ibcon#end of sib2, iclass 12, count 0 2006.201.10:16:32.87#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:16:32.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:16:32.87#ibcon#[27=USB\r\n] 2006.201.10:16:32.87#ibcon#*before write, iclass 12, count 0 2006.201.10:16:32.87#ibcon#enter sib2, iclass 12, count 0 2006.201.10:16:32.87#ibcon#flushed, iclass 12, count 0 2006.201.10:16:32.87#ibcon#about to write, iclass 12, count 0 2006.201.10:16:32.87#ibcon#wrote, iclass 12, count 0 2006.201.10:16:32.87#ibcon#about to read 3, iclass 12, count 0 2006.201.10:16:32.90#ibcon#read 3, iclass 12, count 0 2006.201.10:16:32.90#ibcon#about to read 4, iclass 12, count 0 2006.201.10:16:32.90#ibcon#read 4, iclass 12, count 0 2006.201.10:16:32.90#ibcon#about to read 5, iclass 12, count 0 2006.201.10:16:32.90#ibcon#read 5, iclass 12, count 0 2006.201.10:16:32.90#ibcon#about to read 6, iclass 12, count 0 2006.201.10:16:32.90#ibcon#read 6, iclass 12, count 0 2006.201.10:16:32.90#ibcon#end of sib2, iclass 12, count 0 2006.201.10:16:32.90#ibcon#*after write, iclass 12, count 0 2006.201.10:16:32.90#ibcon#*before return 0, iclass 12, count 0 2006.201.10:16:32.90#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:32.90#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:16:32.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:16:32.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:16:32.90$vck44/vblo=5,709.99 2006.201.10:16:32.90#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.10:16:32.90#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.10:16:32.90#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:32.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:32.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:32.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:32.90#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:16:32.90#ibcon#first serial, iclass 14, count 0 2006.201.10:16:32.90#ibcon#enter sib2, iclass 14, count 0 2006.201.10:16:32.90#ibcon#flushed, iclass 14, count 0 2006.201.10:16:32.90#ibcon#about to write, iclass 14, count 0 2006.201.10:16:32.90#ibcon#wrote, iclass 14, count 0 2006.201.10:16:32.90#ibcon#about to read 3, iclass 14, count 0 2006.201.10:16:32.92#ibcon#read 3, iclass 14, count 0 2006.201.10:16:32.92#ibcon#about to read 4, iclass 14, count 0 2006.201.10:16:32.92#ibcon#read 4, iclass 14, count 0 2006.201.10:16:32.92#ibcon#about to read 5, iclass 14, count 0 2006.201.10:16:32.92#ibcon#read 5, iclass 14, count 0 2006.201.10:16:32.92#ibcon#about to read 6, iclass 14, count 0 2006.201.10:16:32.92#ibcon#read 6, iclass 14, count 0 2006.201.10:16:32.92#ibcon#end of sib2, iclass 14, count 0 2006.201.10:16:32.92#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:16:32.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:16:32.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:16:32.92#ibcon#*before write, iclass 14, count 0 2006.201.10:16:32.92#ibcon#enter sib2, iclass 14, count 0 2006.201.10:16:32.92#ibcon#flushed, iclass 14, count 0 2006.201.10:16:32.92#ibcon#about to write, iclass 14, count 0 2006.201.10:16:32.92#ibcon#wrote, iclass 14, count 0 2006.201.10:16:32.92#ibcon#about to read 3, iclass 14, count 0 2006.201.10:16:32.96#ibcon#read 3, iclass 14, count 0 2006.201.10:16:32.96#ibcon#about to read 4, iclass 14, count 0 2006.201.10:16:32.96#ibcon#read 4, iclass 14, count 0 2006.201.10:16:32.96#ibcon#about to read 5, iclass 14, count 0 2006.201.10:16:32.96#ibcon#read 5, iclass 14, count 0 2006.201.10:16:32.96#ibcon#about to read 6, iclass 14, count 0 2006.201.10:16:32.96#ibcon#read 6, iclass 14, count 0 2006.201.10:16:32.96#ibcon#end of sib2, iclass 14, count 0 2006.201.10:16:32.96#ibcon#*after write, iclass 14, count 0 2006.201.10:16:32.96#ibcon#*before return 0, iclass 14, count 0 2006.201.10:16:32.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:32.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:16:32.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:16:32.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:16:32.96$vck44/vb=5,4 2006.201.10:16:32.96#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.10:16:32.96#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.10:16:32.96#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:32.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:33.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:33.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:33.02#ibcon#enter wrdev, iclass 16, count 2 2006.201.10:16:33.02#ibcon#first serial, iclass 16, count 2 2006.201.10:16:33.02#ibcon#enter sib2, iclass 16, count 2 2006.201.10:16:33.02#ibcon#flushed, iclass 16, count 2 2006.201.10:16:33.02#ibcon#about to write, iclass 16, count 2 2006.201.10:16:33.02#ibcon#wrote, iclass 16, count 2 2006.201.10:16:33.02#ibcon#about to read 3, iclass 16, count 2 2006.201.10:16:33.04#ibcon#read 3, iclass 16, count 2 2006.201.10:16:33.04#ibcon#about to read 4, iclass 16, count 2 2006.201.10:16:33.04#ibcon#read 4, iclass 16, count 2 2006.201.10:16:33.04#ibcon#about to read 5, iclass 16, count 2 2006.201.10:16:33.04#ibcon#read 5, iclass 16, count 2 2006.201.10:16:33.04#ibcon#about to read 6, iclass 16, count 2 2006.201.10:16:33.04#ibcon#read 6, iclass 16, count 2 2006.201.10:16:33.04#ibcon#end of sib2, iclass 16, count 2 2006.201.10:16:33.04#ibcon#*mode == 0, iclass 16, count 2 2006.201.10:16:33.04#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.10:16:33.04#ibcon#[27=AT05-04\r\n] 2006.201.10:16:33.04#ibcon#*before write, iclass 16, count 2 2006.201.10:16:33.04#ibcon#enter sib2, iclass 16, count 2 2006.201.10:16:33.04#ibcon#flushed, iclass 16, count 2 2006.201.10:16:33.04#ibcon#about to write, iclass 16, count 2 2006.201.10:16:33.04#ibcon#wrote, iclass 16, count 2 2006.201.10:16:33.04#ibcon#about to read 3, iclass 16, count 2 2006.201.10:16:33.07#ibcon#read 3, iclass 16, count 2 2006.201.10:16:33.07#ibcon#about to read 4, iclass 16, count 2 2006.201.10:16:33.07#ibcon#read 4, iclass 16, count 2 2006.201.10:16:33.07#ibcon#about to read 5, iclass 16, count 2 2006.201.10:16:33.07#ibcon#read 5, iclass 16, count 2 2006.201.10:16:33.07#ibcon#about to read 6, iclass 16, count 2 2006.201.10:16:33.07#ibcon#read 6, iclass 16, count 2 2006.201.10:16:33.07#ibcon#end of sib2, iclass 16, count 2 2006.201.10:16:33.07#ibcon#*after write, iclass 16, count 2 2006.201.10:16:33.07#ibcon#*before return 0, iclass 16, count 2 2006.201.10:16:33.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:33.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:16:33.07#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.10:16:33.07#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:33.07#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:33.19#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:33.19#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:33.19#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:16:33.19#ibcon#first serial, iclass 16, count 0 2006.201.10:16:33.19#ibcon#enter sib2, iclass 16, count 0 2006.201.10:16:33.19#ibcon#flushed, iclass 16, count 0 2006.201.10:16:33.19#ibcon#about to write, iclass 16, count 0 2006.201.10:16:33.19#ibcon#wrote, iclass 16, count 0 2006.201.10:16:33.19#ibcon#about to read 3, iclass 16, count 0 2006.201.10:16:33.21#ibcon#read 3, iclass 16, count 0 2006.201.10:16:33.21#ibcon#about to read 4, iclass 16, count 0 2006.201.10:16:33.21#ibcon#read 4, iclass 16, count 0 2006.201.10:16:33.21#ibcon#about to read 5, iclass 16, count 0 2006.201.10:16:33.21#ibcon#read 5, iclass 16, count 0 2006.201.10:16:33.21#ibcon#about to read 6, iclass 16, count 0 2006.201.10:16:33.21#ibcon#read 6, iclass 16, count 0 2006.201.10:16:33.21#ibcon#end of sib2, iclass 16, count 0 2006.201.10:16:33.21#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:16:33.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:16:33.21#ibcon#[27=USB\r\n] 2006.201.10:16:33.21#ibcon#*before write, iclass 16, count 0 2006.201.10:16:33.21#ibcon#enter sib2, iclass 16, count 0 2006.201.10:16:33.21#ibcon#flushed, iclass 16, count 0 2006.201.10:16:33.21#ibcon#about to write, iclass 16, count 0 2006.201.10:16:33.21#ibcon#wrote, iclass 16, count 0 2006.201.10:16:33.21#ibcon#about to read 3, iclass 16, count 0 2006.201.10:16:33.24#ibcon#read 3, iclass 16, count 0 2006.201.10:16:33.24#ibcon#about to read 4, iclass 16, count 0 2006.201.10:16:33.24#ibcon#read 4, iclass 16, count 0 2006.201.10:16:33.24#ibcon#about to read 5, iclass 16, count 0 2006.201.10:16:33.24#ibcon#read 5, iclass 16, count 0 2006.201.10:16:33.24#ibcon#about to read 6, iclass 16, count 0 2006.201.10:16:33.24#ibcon#read 6, iclass 16, count 0 2006.201.10:16:33.24#ibcon#end of sib2, iclass 16, count 0 2006.201.10:16:33.24#ibcon#*after write, iclass 16, count 0 2006.201.10:16:33.24#ibcon#*before return 0, iclass 16, count 0 2006.201.10:16:33.24#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:33.24#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:16:33.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:16:33.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:16:33.24$vck44/vblo=6,719.99 2006.201.10:16:33.24#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.10:16:33.24#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.10:16:33.24#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:33.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:33.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:33.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:33.24#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:16:33.24#ibcon#first serial, iclass 18, count 0 2006.201.10:16:33.24#ibcon#enter sib2, iclass 18, count 0 2006.201.10:16:33.24#ibcon#flushed, iclass 18, count 0 2006.201.10:16:33.24#ibcon#about to write, iclass 18, count 0 2006.201.10:16:33.24#ibcon#wrote, iclass 18, count 0 2006.201.10:16:33.24#ibcon#about to read 3, iclass 18, count 0 2006.201.10:16:33.26#ibcon#read 3, iclass 18, count 0 2006.201.10:16:33.26#ibcon#about to read 4, iclass 18, count 0 2006.201.10:16:33.26#ibcon#read 4, iclass 18, count 0 2006.201.10:16:33.26#ibcon#about to read 5, iclass 18, count 0 2006.201.10:16:33.26#ibcon#read 5, iclass 18, count 0 2006.201.10:16:33.26#ibcon#about to read 6, iclass 18, count 0 2006.201.10:16:33.26#ibcon#read 6, iclass 18, count 0 2006.201.10:16:33.26#ibcon#end of sib2, iclass 18, count 0 2006.201.10:16:33.26#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:16:33.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:16:33.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:16:33.26#ibcon#*before write, iclass 18, count 0 2006.201.10:16:33.26#ibcon#enter sib2, iclass 18, count 0 2006.201.10:16:33.26#ibcon#flushed, iclass 18, count 0 2006.201.10:16:33.26#ibcon#about to write, iclass 18, count 0 2006.201.10:16:33.26#ibcon#wrote, iclass 18, count 0 2006.201.10:16:33.26#ibcon#about to read 3, iclass 18, count 0 2006.201.10:16:33.30#ibcon#read 3, iclass 18, count 0 2006.201.10:16:33.30#ibcon#about to read 4, iclass 18, count 0 2006.201.10:16:33.30#ibcon#read 4, iclass 18, count 0 2006.201.10:16:33.30#ibcon#about to read 5, iclass 18, count 0 2006.201.10:16:33.30#ibcon#read 5, iclass 18, count 0 2006.201.10:16:33.30#ibcon#about to read 6, iclass 18, count 0 2006.201.10:16:33.30#ibcon#read 6, iclass 18, count 0 2006.201.10:16:33.30#ibcon#end of sib2, iclass 18, count 0 2006.201.10:16:33.30#ibcon#*after write, iclass 18, count 0 2006.201.10:16:33.30#ibcon#*before return 0, iclass 18, count 0 2006.201.10:16:33.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:33.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:16:33.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:16:33.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:16:33.30$vck44/vb=6,4 2006.201.10:16:33.30#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.10:16:33.30#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.10:16:33.30#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:33.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:33.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:33.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:33.36#ibcon#enter wrdev, iclass 20, count 2 2006.201.10:16:33.36#ibcon#first serial, iclass 20, count 2 2006.201.10:16:33.36#ibcon#enter sib2, iclass 20, count 2 2006.201.10:16:33.36#ibcon#flushed, iclass 20, count 2 2006.201.10:16:33.36#ibcon#about to write, iclass 20, count 2 2006.201.10:16:33.36#ibcon#wrote, iclass 20, count 2 2006.201.10:16:33.36#ibcon#about to read 3, iclass 20, count 2 2006.201.10:16:33.38#ibcon#read 3, iclass 20, count 2 2006.201.10:16:33.38#ibcon#about to read 4, iclass 20, count 2 2006.201.10:16:33.38#ibcon#read 4, iclass 20, count 2 2006.201.10:16:33.38#ibcon#about to read 5, iclass 20, count 2 2006.201.10:16:33.38#ibcon#read 5, iclass 20, count 2 2006.201.10:16:33.38#ibcon#about to read 6, iclass 20, count 2 2006.201.10:16:33.38#ibcon#read 6, iclass 20, count 2 2006.201.10:16:33.38#ibcon#end of sib2, iclass 20, count 2 2006.201.10:16:33.38#ibcon#*mode == 0, iclass 20, count 2 2006.201.10:16:33.38#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.10:16:33.38#ibcon#[27=AT06-04\r\n] 2006.201.10:16:33.38#ibcon#*before write, iclass 20, count 2 2006.201.10:16:33.38#ibcon#enter sib2, iclass 20, count 2 2006.201.10:16:33.38#ibcon#flushed, iclass 20, count 2 2006.201.10:16:33.38#ibcon#about to write, iclass 20, count 2 2006.201.10:16:33.38#ibcon#wrote, iclass 20, count 2 2006.201.10:16:33.38#ibcon#about to read 3, iclass 20, count 2 2006.201.10:16:33.42#ibcon#read 3, iclass 20, count 2 2006.201.10:16:33.42#ibcon#about to read 4, iclass 20, count 2 2006.201.10:16:33.42#ibcon#read 4, iclass 20, count 2 2006.201.10:16:33.42#ibcon#about to read 5, iclass 20, count 2 2006.201.10:16:33.42#ibcon#read 5, iclass 20, count 2 2006.201.10:16:33.42#ibcon#about to read 6, iclass 20, count 2 2006.201.10:16:33.42#ibcon#read 6, iclass 20, count 2 2006.201.10:16:33.42#ibcon#end of sib2, iclass 20, count 2 2006.201.10:16:33.42#ibcon#*after write, iclass 20, count 2 2006.201.10:16:33.42#ibcon#*before return 0, iclass 20, count 2 2006.201.10:16:33.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:33.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:16:33.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.10:16:33.42#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:33.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:33.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:33.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:33.54#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:16:33.54#ibcon#first serial, iclass 20, count 0 2006.201.10:16:33.54#ibcon#enter sib2, iclass 20, count 0 2006.201.10:16:33.54#ibcon#flushed, iclass 20, count 0 2006.201.10:16:33.54#ibcon#about to write, iclass 20, count 0 2006.201.10:16:33.54#ibcon#wrote, iclass 20, count 0 2006.201.10:16:33.54#ibcon#about to read 3, iclass 20, count 0 2006.201.10:16:33.56#ibcon#read 3, iclass 20, count 0 2006.201.10:16:33.56#ibcon#about to read 4, iclass 20, count 0 2006.201.10:16:33.56#ibcon#read 4, iclass 20, count 0 2006.201.10:16:33.56#ibcon#about to read 5, iclass 20, count 0 2006.201.10:16:33.56#ibcon#read 5, iclass 20, count 0 2006.201.10:16:33.56#ibcon#about to read 6, iclass 20, count 0 2006.201.10:16:33.56#ibcon#read 6, iclass 20, count 0 2006.201.10:16:33.56#ibcon#end of sib2, iclass 20, count 0 2006.201.10:16:33.56#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:16:33.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:16:33.56#ibcon#[27=USB\r\n] 2006.201.10:16:33.56#ibcon#*before write, iclass 20, count 0 2006.201.10:16:33.56#ibcon#enter sib2, iclass 20, count 0 2006.201.10:16:33.56#ibcon#flushed, iclass 20, count 0 2006.201.10:16:33.56#ibcon#about to write, iclass 20, count 0 2006.201.10:16:33.56#ibcon#wrote, iclass 20, count 0 2006.201.10:16:33.56#ibcon#about to read 3, iclass 20, count 0 2006.201.10:16:33.59#ibcon#read 3, iclass 20, count 0 2006.201.10:16:33.59#ibcon#about to read 4, iclass 20, count 0 2006.201.10:16:33.59#ibcon#read 4, iclass 20, count 0 2006.201.10:16:33.59#ibcon#about to read 5, iclass 20, count 0 2006.201.10:16:33.59#ibcon#read 5, iclass 20, count 0 2006.201.10:16:33.59#ibcon#about to read 6, iclass 20, count 0 2006.201.10:16:33.59#ibcon#read 6, iclass 20, count 0 2006.201.10:16:33.59#ibcon#end of sib2, iclass 20, count 0 2006.201.10:16:33.59#ibcon#*after write, iclass 20, count 0 2006.201.10:16:33.59#ibcon#*before return 0, iclass 20, count 0 2006.201.10:16:33.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:33.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:16:33.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:16:33.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:16:33.59$vck44/vblo=7,734.99 2006.201.10:16:33.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.10:16:33.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.10:16:33.59#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:33.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:33.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:33.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:33.59#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:16:33.59#ibcon#first serial, iclass 22, count 0 2006.201.10:16:33.59#ibcon#enter sib2, iclass 22, count 0 2006.201.10:16:33.59#ibcon#flushed, iclass 22, count 0 2006.201.10:16:33.59#ibcon#about to write, iclass 22, count 0 2006.201.10:16:33.59#ibcon#wrote, iclass 22, count 0 2006.201.10:16:33.59#ibcon#about to read 3, iclass 22, count 0 2006.201.10:16:33.61#ibcon#read 3, iclass 22, count 0 2006.201.10:16:33.61#ibcon#about to read 4, iclass 22, count 0 2006.201.10:16:33.61#ibcon#read 4, iclass 22, count 0 2006.201.10:16:33.61#ibcon#about to read 5, iclass 22, count 0 2006.201.10:16:33.61#ibcon#read 5, iclass 22, count 0 2006.201.10:16:33.61#ibcon#about to read 6, iclass 22, count 0 2006.201.10:16:33.61#ibcon#read 6, iclass 22, count 0 2006.201.10:16:33.61#ibcon#end of sib2, iclass 22, count 0 2006.201.10:16:33.61#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:16:33.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:16:33.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:16:33.61#ibcon#*before write, iclass 22, count 0 2006.201.10:16:33.61#ibcon#enter sib2, iclass 22, count 0 2006.201.10:16:33.61#ibcon#flushed, iclass 22, count 0 2006.201.10:16:33.61#ibcon#about to write, iclass 22, count 0 2006.201.10:16:33.61#ibcon#wrote, iclass 22, count 0 2006.201.10:16:33.61#ibcon#about to read 3, iclass 22, count 0 2006.201.10:16:33.65#ibcon#read 3, iclass 22, count 0 2006.201.10:16:33.65#ibcon#about to read 4, iclass 22, count 0 2006.201.10:16:33.65#ibcon#read 4, iclass 22, count 0 2006.201.10:16:33.65#ibcon#about to read 5, iclass 22, count 0 2006.201.10:16:33.65#ibcon#read 5, iclass 22, count 0 2006.201.10:16:33.65#ibcon#about to read 6, iclass 22, count 0 2006.201.10:16:33.65#ibcon#read 6, iclass 22, count 0 2006.201.10:16:33.65#ibcon#end of sib2, iclass 22, count 0 2006.201.10:16:33.65#ibcon#*after write, iclass 22, count 0 2006.201.10:16:33.65#ibcon#*before return 0, iclass 22, count 0 2006.201.10:16:33.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:33.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:16:33.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:16:33.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:16:33.65$vck44/vb=7,4 2006.201.10:16:33.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.10:16:33.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.10:16:33.65#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:33.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:33.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:33.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:33.71#ibcon#enter wrdev, iclass 24, count 2 2006.201.10:16:33.71#ibcon#first serial, iclass 24, count 2 2006.201.10:16:33.71#ibcon#enter sib2, iclass 24, count 2 2006.201.10:16:33.71#ibcon#flushed, iclass 24, count 2 2006.201.10:16:33.71#ibcon#about to write, iclass 24, count 2 2006.201.10:16:33.71#ibcon#wrote, iclass 24, count 2 2006.201.10:16:33.71#ibcon#about to read 3, iclass 24, count 2 2006.201.10:16:33.73#ibcon#read 3, iclass 24, count 2 2006.201.10:16:33.73#ibcon#about to read 4, iclass 24, count 2 2006.201.10:16:33.73#ibcon#read 4, iclass 24, count 2 2006.201.10:16:33.73#ibcon#about to read 5, iclass 24, count 2 2006.201.10:16:33.73#ibcon#read 5, iclass 24, count 2 2006.201.10:16:33.73#ibcon#about to read 6, iclass 24, count 2 2006.201.10:16:33.73#ibcon#read 6, iclass 24, count 2 2006.201.10:16:33.73#ibcon#end of sib2, iclass 24, count 2 2006.201.10:16:33.73#ibcon#*mode == 0, iclass 24, count 2 2006.201.10:16:33.73#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.10:16:33.73#ibcon#[27=AT07-04\r\n] 2006.201.10:16:33.73#ibcon#*before write, iclass 24, count 2 2006.201.10:16:33.73#ibcon#enter sib2, iclass 24, count 2 2006.201.10:16:33.73#ibcon#flushed, iclass 24, count 2 2006.201.10:16:33.73#ibcon#about to write, iclass 24, count 2 2006.201.10:16:33.73#ibcon#wrote, iclass 24, count 2 2006.201.10:16:33.73#ibcon#about to read 3, iclass 24, count 2 2006.201.10:16:33.76#ibcon#read 3, iclass 24, count 2 2006.201.10:16:33.76#ibcon#about to read 4, iclass 24, count 2 2006.201.10:16:33.76#ibcon#read 4, iclass 24, count 2 2006.201.10:16:33.76#ibcon#about to read 5, iclass 24, count 2 2006.201.10:16:33.76#ibcon#read 5, iclass 24, count 2 2006.201.10:16:33.76#ibcon#about to read 6, iclass 24, count 2 2006.201.10:16:33.76#ibcon#read 6, iclass 24, count 2 2006.201.10:16:33.76#ibcon#end of sib2, iclass 24, count 2 2006.201.10:16:33.76#ibcon#*after write, iclass 24, count 2 2006.201.10:16:33.76#ibcon#*before return 0, iclass 24, count 2 2006.201.10:16:33.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:33.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:16:33.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.10:16:33.76#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:33.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:33.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:33.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:33.88#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:16:33.88#ibcon#first serial, iclass 24, count 0 2006.201.10:16:33.88#ibcon#enter sib2, iclass 24, count 0 2006.201.10:16:33.88#ibcon#flushed, iclass 24, count 0 2006.201.10:16:33.88#ibcon#about to write, iclass 24, count 0 2006.201.10:16:33.88#ibcon#wrote, iclass 24, count 0 2006.201.10:16:33.88#ibcon#about to read 3, iclass 24, count 0 2006.201.10:16:33.90#ibcon#read 3, iclass 24, count 0 2006.201.10:16:33.90#ibcon#about to read 4, iclass 24, count 0 2006.201.10:16:33.90#ibcon#read 4, iclass 24, count 0 2006.201.10:16:33.90#ibcon#about to read 5, iclass 24, count 0 2006.201.10:16:33.90#ibcon#read 5, iclass 24, count 0 2006.201.10:16:33.90#ibcon#about to read 6, iclass 24, count 0 2006.201.10:16:33.90#ibcon#read 6, iclass 24, count 0 2006.201.10:16:33.90#ibcon#end of sib2, iclass 24, count 0 2006.201.10:16:33.90#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:16:33.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:16:33.90#ibcon#[27=USB\r\n] 2006.201.10:16:33.90#ibcon#*before write, iclass 24, count 0 2006.201.10:16:33.90#ibcon#enter sib2, iclass 24, count 0 2006.201.10:16:33.90#ibcon#flushed, iclass 24, count 0 2006.201.10:16:33.90#ibcon#about to write, iclass 24, count 0 2006.201.10:16:33.90#ibcon#wrote, iclass 24, count 0 2006.201.10:16:33.90#ibcon#about to read 3, iclass 24, count 0 2006.201.10:16:33.93#ibcon#read 3, iclass 24, count 0 2006.201.10:16:33.93#ibcon#about to read 4, iclass 24, count 0 2006.201.10:16:33.93#ibcon#read 4, iclass 24, count 0 2006.201.10:16:33.93#ibcon#about to read 5, iclass 24, count 0 2006.201.10:16:33.93#ibcon#read 5, iclass 24, count 0 2006.201.10:16:33.93#ibcon#about to read 6, iclass 24, count 0 2006.201.10:16:33.93#ibcon#read 6, iclass 24, count 0 2006.201.10:16:33.93#ibcon#end of sib2, iclass 24, count 0 2006.201.10:16:33.93#ibcon#*after write, iclass 24, count 0 2006.201.10:16:33.93#ibcon#*before return 0, iclass 24, count 0 2006.201.10:16:33.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:33.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:16:33.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:16:33.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:16:33.93$vck44/vblo=8,744.99 2006.201.10:16:33.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.10:16:33.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.10:16:33.93#ibcon#ireg 17 cls_cnt 0 2006.201.10:16:33.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:33.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:33.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:33.93#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:16:33.93#ibcon#first serial, iclass 26, count 0 2006.201.10:16:33.93#ibcon#enter sib2, iclass 26, count 0 2006.201.10:16:33.93#ibcon#flushed, iclass 26, count 0 2006.201.10:16:33.93#ibcon#about to write, iclass 26, count 0 2006.201.10:16:33.93#ibcon#wrote, iclass 26, count 0 2006.201.10:16:33.93#ibcon#about to read 3, iclass 26, count 0 2006.201.10:16:33.95#ibcon#read 3, iclass 26, count 0 2006.201.10:16:33.95#ibcon#about to read 4, iclass 26, count 0 2006.201.10:16:33.95#ibcon#read 4, iclass 26, count 0 2006.201.10:16:33.95#ibcon#about to read 5, iclass 26, count 0 2006.201.10:16:33.95#ibcon#read 5, iclass 26, count 0 2006.201.10:16:33.95#ibcon#about to read 6, iclass 26, count 0 2006.201.10:16:33.95#ibcon#read 6, iclass 26, count 0 2006.201.10:16:33.95#ibcon#end of sib2, iclass 26, count 0 2006.201.10:16:33.95#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:16:33.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:16:33.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:16:33.95#ibcon#*before write, iclass 26, count 0 2006.201.10:16:33.95#ibcon#enter sib2, iclass 26, count 0 2006.201.10:16:33.95#ibcon#flushed, iclass 26, count 0 2006.201.10:16:33.95#ibcon#about to write, iclass 26, count 0 2006.201.10:16:33.95#ibcon#wrote, iclass 26, count 0 2006.201.10:16:33.95#ibcon#about to read 3, iclass 26, count 0 2006.201.10:16:33.99#ibcon#read 3, iclass 26, count 0 2006.201.10:16:33.99#ibcon#about to read 4, iclass 26, count 0 2006.201.10:16:33.99#ibcon#read 4, iclass 26, count 0 2006.201.10:16:33.99#ibcon#about to read 5, iclass 26, count 0 2006.201.10:16:33.99#ibcon#read 5, iclass 26, count 0 2006.201.10:16:33.99#ibcon#about to read 6, iclass 26, count 0 2006.201.10:16:33.99#ibcon#read 6, iclass 26, count 0 2006.201.10:16:33.99#ibcon#end of sib2, iclass 26, count 0 2006.201.10:16:33.99#ibcon#*after write, iclass 26, count 0 2006.201.10:16:33.99#ibcon#*before return 0, iclass 26, count 0 2006.201.10:16:33.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:33.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:16:33.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:16:33.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:16:33.99$vck44/vb=8,4 2006.201.10:16:33.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.10:16:33.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.10:16:33.99#ibcon#ireg 11 cls_cnt 2 2006.201.10:16:33.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:34.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:34.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:34.05#ibcon#enter wrdev, iclass 28, count 2 2006.201.10:16:34.05#ibcon#first serial, iclass 28, count 2 2006.201.10:16:34.05#ibcon#enter sib2, iclass 28, count 2 2006.201.10:16:34.05#ibcon#flushed, iclass 28, count 2 2006.201.10:16:34.05#ibcon#about to write, iclass 28, count 2 2006.201.10:16:34.05#ibcon#wrote, iclass 28, count 2 2006.201.10:16:34.05#ibcon#about to read 3, iclass 28, count 2 2006.201.10:16:34.07#ibcon#read 3, iclass 28, count 2 2006.201.10:16:34.07#ibcon#about to read 4, iclass 28, count 2 2006.201.10:16:34.07#ibcon#read 4, iclass 28, count 2 2006.201.10:16:34.07#ibcon#about to read 5, iclass 28, count 2 2006.201.10:16:34.07#ibcon#read 5, iclass 28, count 2 2006.201.10:16:34.07#ibcon#about to read 6, iclass 28, count 2 2006.201.10:16:34.07#ibcon#read 6, iclass 28, count 2 2006.201.10:16:34.07#ibcon#end of sib2, iclass 28, count 2 2006.201.10:16:34.07#ibcon#*mode == 0, iclass 28, count 2 2006.201.10:16:34.07#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.10:16:34.07#ibcon#[27=AT08-04\r\n] 2006.201.10:16:34.07#ibcon#*before write, iclass 28, count 2 2006.201.10:16:34.07#ibcon#enter sib2, iclass 28, count 2 2006.201.10:16:34.07#ibcon#flushed, iclass 28, count 2 2006.201.10:16:34.07#ibcon#about to write, iclass 28, count 2 2006.201.10:16:34.07#ibcon#wrote, iclass 28, count 2 2006.201.10:16:34.07#ibcon#about to read 3, iclass 28, count 2 2006.201.10:16:34.10#ibcon#read 3, iclass 28, count 2 2006.201.10:16:34.10#ibcon#about to read 4, iclass 28, count 2 2006.201.10:16:34.10#ibcon#read 4, iclass 28, count 2 2006.201.10:16:34.10#ibcon#about to read 5, iclass 28, count 2 2006.201.10:16:34.10#ibcon#read 5, iclass 28, count 2 2006.201.10:16:34.10#ibcon#about to read 6, iclass 28, count 2 2006.201.10:16:34.10#ibcon#read 6, iclass 28, count 2 2006.201.10:16:34.10#ibcon#end of sib2, iclass 28, count 2 2006.201.10:16:34.10#ibcon#*after write, iclass 28, count 2 2006.201.10:16:34.10#ibcon#*before return 0, iclass 28, count 2 2006.201.10:16:34.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:34.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:16:34.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.10:16:34.10#ibcon#ireg 7 cls_cnt 0 2006.201.10:16:34.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:34.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:34.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:34.22#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:16:34.22#ibcon#first serial, iclass 28, count 0 2006.201.10:16:34.22#ibcon#enter sib2, iclass 28, count 0 2006.201.10:16:34.22#ibcon#flushed, iclass 28, count 0 2006.201.10:16:34.22#ibcon#about to write, iclass 28, count 0 2006.201.10:16:34.22#ibcon#wrote, iclass 28, count 0 2006.201.10:16:34.22#ibcon#about to read 3, iclass 28, count 0 2006.201.10:16:34.24#ibcon#read 3, iclass 28, count 0 2006.201.10:16:34.24#ibcon#about to read 4, iclass 28, count 0 2006.201.10:16:34.24#ibcon#read 4, iclass 28, count 0 2006.201.10:16:34.24#ibcon#about to read 5, iclass 28, count 0 2006.201.10:16:34.24#ibcon#read 5, iclass 28, count 0 2006.201.10:16:34.24#ibcon#about to read 6, iclass 28, count 0 2006.201.10:16:34.24#ibcon#read 6, iclass 28, count 0 2006.201.10:16:34.24#ibcon#end of sib2, iclass 28, count 0 2006.201.10:16:34.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:16:34.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:16:34.24#ibcon#[27=USB\r\n] 2006.201.10:16:34.24#ibcon#*before write, iclass 28, count 0 2006.201.10:16:34.24#ibcon#enter sib2, iclass 28, count 0 2006.201.10:16:34.24#ibcon#flushed, iclass 28, count 0 2006.201.10:16:34.24#ibcon#about to write, iclass 28, count 0 2006.201.10:16:34.24#ibcon#wrote, iclass 28, count 0 2006.201.10:16:34.24#ibcon#about to read 3, iclass 28, count 0 2006.201.10:16:34.27#ibcon#read 3, iclass 28, count 0 2006.201.10:16:34.27#ibcon#about to read 4, iclass 28, count 0 2006.201.10:16:34.27#ibcon#read 4, iclass 28, count 0 2006.201.10:16:34.27#ibcon#about to read 5, iclass 28, count 0 2006.201.10:16:34.27#ibcon#read 5, iclass 28, count 0 2006.201.10:16:34.27#ibcon#about to read 6, iclass 28, count 0 2006.201.10:16:34.27#ibcon#read 6, iclass 28, count 0 2006.201.10:16:34.27#ibcon#end of sib2, iclass 28, count 0 2006.201.10:16:34.27#ibcon#*after write, iclass 28, count 0 2006.201.10:16:34.27#ibcon#*before return 0, iclass 28, count 0 2006.201.10:16:34.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:34.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:16:34.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:16:34.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:16:34.27$vck44/vabw=wide 2006.201.10:16:34.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.10:16:34.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.10:16:34.27#ibcon#ireg 8 cls_cnt 0 2006.201.10:16:34.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:34.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:34.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:34.27#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:16:34.27#ibcon#first serial, iclass 30, count 0 2006.201.10:16:34.27#ibcon#enter sib2, iclass 30, count 0 2006.201.10:16:34.27#ibcon#flushed, iclass 30, count 0 2006.201.10:16:34.27#ibcon#about to write, iclass 30, count 0 2006.201.10:16:34.27#ibcon#wrote, iclass 30, count 0 2006.201.10:16:34.27#ibcon#about to read 3, iclass 30, count 0 2006.201.10:16:34.29#ibcon#read 3, iclass 30, count 0 2006.201.10:16:34.29#ibcon#about to read 4, iclass 30, count 0 2006.201.10:16:34.29#ibcon#read 4, iclass 30, count 0 2006.201.10:16:34.29#ibcon#about to read 5, iclass 30, count 0 2006.201.10:16:34.29#ibcon#read 5, iclass 30, count 0 2006.201.10:16:34.29#ibcon#about to read 6, iclass 30, count 0 2006.201.10:16:34.29#ibcon#read 6, iclass 30, count 0 2006.201.10:16:34.29#ibcon#end of sib2, iclass 30, count 0 2006.201.10:16:34.29#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:16:34.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:16:34.29#ibcon#[25=BW32\r\n] 2006.201.10:16:34.29#ibcon#*before write, iclass 30, count 0 2006.201.10:16:34.29#ibcon#enter sib2, iclass 30, count 0 2006.201.10:16:34.29#ibcon#flushed, iclass 30, count 0 2006.201.10:16:34.29#ibcon#about to write, iclass 30, count 0 2006.201.10:16:34.29#ibcon#wrote, iclass 30, count 0 2006.201.10:16:34.29#ibcon#about to read 3, iclass 30, count 0 2006.201.10:16:34.33#ibcon#read 3, iclass 30, count 0 2006.201.10:16:34.33#ibcon#about to read 4, iclass 30, count 0 2006.201.10:16:34.33#ibcon#read 4, iclass 30, count 0 2006.201.10:16:34.33#ibcon#about to read 5, iclass 30, count 0 2006.201.10:16:34.33#ibcon#read 5, iclass 30, count 0 2006.201.10:16:34.33#ibcon#about to read 6, iclass 30, count 0 2006.201.10:16:34.33#ibcon#read 6, iclass 30, count 0 2006.201.10:16:34.33#ibcon#end of sib2, iclass 30, count 0 2006.201.10:16:34.33#ibcon#*after write, iclass 30, count 0 2006.201.10:16:34.33#ibcon#*before return 0, iclass 30, count 0 2006.201.10:16:34.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:34.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:16:34.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:16:34.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:16:34.33$vck44/vbbw=wide 2006.201.10:16:34.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.10:16:34.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.10:16:34.33#ibcon#ireg 8 cls_cnt 0 2006.201.10:16:34.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:16:34.38#abcon#<5=/05 2.8 4.7 21.92 951003.5\r\n> 2006.201.10:16:34.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:16:34.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:16:34.39#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:16:34.39#ibcon#first serial, iclass 32, count 0 2006.201.10:16:34.39#ibcon#enter sib2, iclass 32, count 0 2006.201.10:16:34.39#ibcon#flushed, iclass 32, count 0 2006.201.10:16:34.39#ibcon#about to write, iclass 32, count 0 2006.201.10:16:34.39#ibcon#wrote, iclass 32, count 0 2006.201.10:16:34.39#ibcon#about to read 3, iclass 32, count 0 2006.201.10:16:34.40#abcon#{5=INTERFACE CLEAR} 2006.201.10:16:34.41#ibcon#read 3, iclass 32, count 0 2006.201.10:16:34.41#ibcon#about to read 4, iclass 32, count 0 2006.201.10:16:34.41#ibcon#read 4, iclass 32, count 0 2006.201.10:16:34.41#ibcon#about to read 5, iclass 32, count 0 2006.201.10:16:34.41#ibcon#read 5, iclass 32, count 0 2006.201.10:16:34.41#ibcon#about to read 6, iclass 32, count 0 2006.201.10:16:34.41#ibcon#read 6, iclass 32, count 0 2006.201.10:16:34.41#ibcon#end of sib2, iclass 32, count 0 2006.201.10:16:34.41#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:16:34.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:16:34.41#ibcon#[27=BW32\r\n] 2006.201.10:16:34.41#ibcon#*before write, iclass 32, count 0 2006.201.10:16:34.41#ibcon#enter sib2, iclass 32, count 0 2006.201.10:16:34.41#ibcon#flushed, iclass 32, count 0 2006.201.10:16:34.41#ibcon#about to write, iclass 32, count 0 2006.201.10:16:34.41#ibcon#wrote, iclass 32, count 0 2006.201.10:16:34.41#ibcon#about to read 3, iclass 32, count 0 2006.201.10:16:34.44#ibcon#read 3, iclass 32, count 0 2006.201.10:16:34.44#ibcon#about to read 4, iclass 32, count 0 2006.201.10:16:34.44#ibcon#read 4, iclass 32, count 0 2006.201.10:16:34.44#ibcon#about to read 5, iclass 32, count 0 2006.201.10:16:34.44#ibcon#read 5, iclass 32, count 0 2006.201.10:16:34.44#ibcon#about to read 6, iclass 32, count 0 2006.201.10:16:34.44#ibcon#read 6, iclass 32, count 0 2006.201.10:16:34.44#ibcon#end of sib2, iclass 32, count 0 2006.201.10:16:34.44#ibcon#*after write, iclass 32, count 0 2006.201.10:16:34.44#ibcon#*before return 0, iclass 32, count 0 2006.201.10:16:34.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:16:34.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:16:34.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:16:34.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:16:34.44$setupk4/ifdk4 2006.201.10:16:34.44$ifdk4/lo= 2006.201.10:16:34.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:16:34.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:16:34.44$ifdk4/patch= 2006.201.10:16:34.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:16:34.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:16:34.44$setupk4/!*+20s 2006.201.10:16:34.46#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:16:44.55#abcon#<5=/05 2.7 4.7 21.91 951003.5\r\n> 2006.201.10:16:44.57#abcon#{5=INTERFACE CLEAR} 2006.201.10:16:44.63#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:16:48.89$setupk4/"tpicd 2006.201.10:16:48.89$setupk4/echo=off 2006.201.10:16:48.89$setupk4/xlog=off 2006.201.10:16:48.89:!2006.201.10:24:50 2006.201.10:17:28.13#trakl#Source acquired 2006.201.10:17:28.13#flagr#flagr/antenna,acquired 2006.201.10:24:50.00:preob 2006.201.10:24:50.13/onsource/TRACKING 2006.201.10:24:50.13:!2006.201.10:25:00 2006.201.10:25:00.00:"tape 2006.201.10:25:00.00:"st=record 2006.201.10:25:00.00:data_valid=on 2006.201.10:25:00.00:midob 2006.201.10:25:01.13/onsource/TRACKING 2006.201.10:25:01.13/wx/21.79,1003.5,96 2006.201.10:25:01.21/cable/+6.4671E-03 2006.201.10:25:02.30/va/01,08,usb,yes,28,30 2006.201.10:25:02.30/va/02,07,usb,yes,30,31 2006.201.10:25:02.30/va/03,08,usb,yes,27,28 2006.201.10:25:02.30/va/04,07,usb,yes,31,32 2006.201.10:25:02.30/va/05,04,usb,yes,27,28 2006.201.10:25:02.30/va/06,05,usb,yes,27,27 2006.201.10:25:02.30/va/07,05,usb,yes,26,28 2006.201.10:25:02.30/va/08,04,usb,yes,26,32 2006.201.10:25:02.53/valo/01,524.99,yes,locked 2006.201.10:25:02.53/valo/02,534.99,yes,locked 2006.201.10:25:02.53/valo/03,564.99,yes,locked 2006.201.10:25:02.53/valo/04,624.99,yes,locked 2006.201.10:25:02.53/valo/05,734.99,yes,locked 2006.201.10:25:02.53/valo/06,814.99,yes,locked 2006.201.10:25:02.53/valo/07,864.99,yes,locked 2006.201.10:25:02.53/valo/08,884.99,yes,locked 2006.201.10:25:03.62/vb/01,04,usb,yes,28,26 2006.201.10:25:03.62/vb/02,05,usb,yes,27,27 2006.201.10:25:03.62/vb/03,04,usb,yes,28,31 2006.201.10:25:03.62/vb/04,05,usb,yes,28,27 2006.201.10:25:03.62/vb/05,04,usb,yes,25,27 2006.201.10:25:03.62/vb/06,04,usb,yes,29,25 2006.201.10:25:03.62/vb/07,04,usb,yes,29,28 2006.201.10:25:03.62/vb/08,04,usb,yes,26,29 2006.201.10:25:03.86/vblo/01,629.99,yes,locked 2006.201.10:25:03.86/vblo/02,634.99,yes,locked 2006.201.10:25:03.86/vblo/03,649.99,yes,locked 2006.201.10:25:03.86/vblo/04,679.99,yes,locked 2006.201.10:25:03.86/vblo/05,709.99,yes,locked 2006.201.10:25:03.86/vblo/06,719.99,yes,locked 2006.201.10:25:03.86/vblo/07,734.99,yes,locked 2006.201.10:25:03.86/vblo/08,744.99,yes,locked 2006.201.10:25:04.01/vabw/8 2006.201.10:25:04.16/vbbw/8 2006.201.10:25:04.29/xfe/off,on,15.2 2006.201.10:25:04.68/ifatt/23,28,28,28 2006.201.10:25:05.06/fmout-gps/S +4.60E-07 2006.201.10:25:05.13:!2006.201.10:25:40 2006.201.10:25:40.00:data_valid=off 2006.201.10:25:40.00:"et 2006.201.10:25:40.00:!+3s 2006.201.10:25:43.02:"tape 2006.201.10:25:43.02:postob 2006.201.10:25:43.17/cable/+6.4697E-03 2006.201.10:25:43.20/wx/21.78,1003.5,96 2006.201.10:25:43.26/fmout-gps/S +4.60E-07 2006.201.10:25:43.26:scan_name=201-1027,jd0607,100 2006.201.10:25:43.26:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.201.10:25:45.13#flagr#flagr/antenna,new-source 2006.201.10:25:45.13:checkk5 2006.201.10:25:45.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:25:45.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:25:46.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:25:46.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:25:47.00/chk_obsdata//k5ts1/T2011025??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:25:47.37/chk_obsdata//k5ts2/T2011025??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:25:47.76/chk_obsdata//k5ts3/T2011025??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:25:48.13/chk_obsdata//k5ts4/T2011025??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:25:48.82/k5log//k5ts1_log_newline 2006.201.10:25:49.52/k5log//k5ts2_log_newline 2006.201.10:25:50.20/k5log//k5ts3_log_newline 2006.201.10:25:50.88/k5log//k5ts4_log_newline 2006.201.10:25:50.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:25:50.91:setupk4=1 2006.201.10:25:50.91$setupk4/echo=on 2006.201.10:25:50.91$setupk4/pcalon 2006.201.10:25:50.91$pcalon/"no phase cal control is implemented here 2006.201.10:25:50.91$setupk4/"tpicd=stop 2006.201.10:25:50.91$setupk4/"rec=synch_on 2006.201.10:25:50.91$setupk4/"rec_mode=128 2006.201.10:25:50.91$setupk4/!* 2006.201.10:25:50.91$setupk4/recpk4 2006.201.10:25:50.91$recpk4/recpatch= 2006.201.10:25:50.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:25:50.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:25:50.91$setupk4/vck44 2006.201.10:25:50.91$vck44/valo=1,524.99 2006.201.10:25:50.91#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.10:25:50.91#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.10:25:50.91#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:50.91#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:25:50.91#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:25:50.91#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:25:50.91#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:25:50.91#ibcon#first serial, iclass 2, count 0 2006.201.10:25:50.91#ibcon#enter sib2, iclass 2, count 0 2006.201.10:25:50.91#ibcon#flushed, iclass 2, count 0 2006.201.10:25:50.91#ibcon#about to write, iclass 2, count 0 2006.201.10:25:50.91#ibcon#wrote, iclass 2, count 0 2006.201.10:25:50.91#ibcon#about to read 3, iclass 2, count 0 2006.201.10:25:50.93#ibcon#read 3, iclass 2, count 0 2006.201.10:25:50.93#ibcon#about to read 4, iclass 2, count 0 2006.201.10:25:50.93#ibcon#read 4, iclass 2, count 0 2006.201.10:25:50.93#ibcon#about to read 5, iclass 2, count 0 2006.201.10:25:50.93#ibcon#read 5, iclass 2, count 0 2006.201.10:25:50.93#ibcon#about to read 6, iclass 2, count 0 2006.201.10:25:50.93#ibcon#read 6, iclass 2, count 0 2006.201.10:25:50.93#ibcon#end of sib2, iclass 2, count 0 2006.201.10:25:50.93#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:25:50.93#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:25:50.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:25:50.93#ibcon#*before write, iclass 2, count 0 2006.201.10:25:50.93#ibcon#enter sib2, iclass 2, count 0 2006.201.10:25:50.93#ibcon#flushed, iclass 2, count 0 2006.201.10:25:50.93#ibcon#about to write, iclass 2, count 0 2006.201.10:25:50.93#ibcon#wrote, iclass 2, count 0 2006.201.10:25:50.93#ibcon#about to read 3, iclass 2, count 0 2006.201.10:25:50.98#ibcon#read 3, iclass 2, count 0 2006.201.10:25:50.98#ibcon#about to read 4, iclass 2, count 0 2006.201.10:25:50.98#ibcon#read 4, iclass 2, count 0 2006.201.10:25:50.98#ibcon#about to read 5, iclass 2, count 0 2006.201.10:25:50.98#ibcon#read 5, iclass 2, count 0 2006.201.10:25:50.98#ibcon#about to read 6, iclass 2, count 0 2006.201.10:25:50.98#ibcon#read 6, iclass 2, count 0 2006.201.10:25:50.98#ibcon#end of sib2, iclass 2, count 0 2006.201.10:25:50.98#ibcon#*after write, iclass 2, count 0 2006.201.10:25:50.98#ibcon#*before return 0, iclass 2, count 0 2006.201.10:25:50.98#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:25:50.98#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:25:50.98#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:25:50.98#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:25:50.98$vck44/va=1,8 2006.201.10:25:50.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.10:25:50.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.10:25:50.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:50.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:25:50.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:25:50.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:25:50.98#ibcon#enter wrdev, iclass 5, count 2 2006.201.10:25:50.98#ibcon#first serial, iclass 5, count 2 2006.201.10:25:50.98#ibcon#enter sib2, iclass 5, count 2 2006.201.10:25:50.98#ibcon#flushed, iclass 5, count 2 2006.201.10:25:50.98#ibcon#about to write, iclass 5, count 2 2006.201.10:25:50.98#ibcon#wrote, iclass 5, count 2 2006.201.10:25:50.98#ibcon#about to read 3, iclass 5, count 2 2006.201.10:25:51.00#ibcon#read 3, iclass 5, count 2 2006.201.10:25:51.00#ibcon#about to read 4, iclass 5, count 2 2006.201.10:25:51.00#ibcon#read 4, iclass 5, count 2 2006.201.10:25:51.00#ibcon#about to read 5, iclass 5, count 2 2006.201.10:25:51.00#ibcon#read 5, iclass 5, count 2 2006.201.10:25:51.00#ibcon#about to read 6, iclass 5, count 2 2006.201.10:25:51.00#ibcon#read 6, iclass 5, count 2 2006.201.10:25:51.00#ibcon#end of sib2, iclass 5, count 2 2006.201.10:25:51.00#ibcon#*mode == 0, iclass 5, count 2 2006.201.10:25:51.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.10:25:51.00#ibcon#[25=AT01-08\r\n] 2006.201.10:25:51.00#ibcon#*before write, iclass 5, count 2 2006.201.10:25:51.00#ibcon#enter sib2, iclass 5, count 2 2006.201.10:25:51.00#ibcon#flushed, iclass 5, count 2 2006.201.10:25:51.00#ibcon#about to write, iclass 5, count 2 2006.201.10:25:51.00#ibcon#wrote, iclass 5, count 2 2006.201.10:25:51.00#ibcon#about to read 3, iclass 5, count 2 2006.201.10:25:51.03#ibcon#read 3, iclass 5, count 2 2006.201.10:25:51.03#ibcon#about to read 4, iclass 5, count 2 2006.201.10:25:51.03#ibcon#read 4, iclass 5, count 2 2006.201.10:25:51.03#ibcon#about to read 5, iclass 5, count 2 2006.201.10:25:51.03#ibcon#read 5, iclass 5, count 2 2006.201.10:25:51.03#ibcon#about to read 6, iclass 5, count 2 2006.201.10:25:51.03#ibcon#read 6, iclass 5, count 2 2006.201.10:25:51.03#ibcon#end of sib2, iclass 5, count 2 2006.201.10:25:51.03#ibcon#*after write, iclass 5, count 2 2006.201.10:25:51.03#ibcon#*before return 0, iclass 5, count 2 2006.201.10:25:51.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:25:51.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:25:51.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.10:25:51.03#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:51.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:25:51.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:25:51.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:25:51.15#ibcon#enter wrdev, iclass 5, count 0 2006.201.10:25:51.15#ibcon#first serial, iclass 5, count 0 2006.201.10:25:51.15#ibcon#enter sib2, iclass 5, count 0 2006.201.10:25:51.15#ibcon#flushed, iclass 5, count 0 2006.201.10:25:51.15#ibcon#about to write, iclass 5, count 0 2006.201.10:25:51.15#ibcon#wrote, iclass 5, count 0 2006.201.10:25:51.15#ibcon#about to read 3, iclass 5, count 0 2006.201.10:25:51.17#ibcon#read 3, iclass 5, count 0 2006.201.10:25:51.17#ibcon#about to read 4, iclass 5, count 0 2006.201.10:25:51.17#ibcon#read 4, iclass 5, count 0 2006.201.10:25:51.17#ibcon#about to read 5, iclass 5, count 0 2006.201.10:25:51.17#ibcon#read 5, iclass 5, count 0 2006.201.10:25:51.17#ibcon#about to read 6, iclass 5, count 0 2006.201.10:25:51.17#ibcon#read 6, iclass 5, count 0 2006.201.10:25:51.17#ibcon#end of sib2, iclass 5, count 0 2006.201.10:25:51.17#ibcon#*mode == 0, iclass 5, count 0 2006.201.10:25:51.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.10:25:51.17#ibcon#[25=USB\r\n] 2006.201.10:25:51.17#ibcon#*before write, iclass 5, count 0 2006.201.10:25:51.17#ibcon#enter sib2, iclass 5, count 0 2006.201.10:25:51.17#ibcon#flushed, iclass 5, count 0 2006.201.10:25:51.17#ibcon#about to write, iclass 5, count 0 2006.201.10:25:51.17#ibcon#wrote, iclass 5, count 0 2006.201.10:25:51.17#ibcon#about to read 3, iclass 5, count 0 2006.201.10:25:51.20#ibcon#read 3, iclass 5, count 0 2006.201.10:25:51.20#ibcon#about to read 4, iclass 5, count 0 2006.201.10:25:51.20#ibcon#read 4, iclass 5, count 0 2006.201.10:25:51.20#ibcon#about to read 5, iclass 5, count 0 2006.201.10:25:51.20#ibcon#read 5, iclass 5, count 0 2006.201.10:25:51.20#ibcon#about to read 6, iclass 5, count 0 2006.201.10:25:51.20#ibcon#read 6, iclass 5, count 0 2006.201.10:25:51.20#ibcon#end of sib2, iclass 5, count 0 2006.201.10:25:51.20#ibcon#*after write, iclass 5, count 0 2006.201.10:25:51.20#ibcon#*before return 0, iclass 5, count 0 2006.201.10:25:51.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:25:51.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:25:51.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.10:25:51.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.10:25:51.20$vck44/valo=2,534.99 2006.201.10:25:51.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.10:25:51.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.10:25:51.20#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:51.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:25:51.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:25:51.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:25:51.20#ibcon#enter wrdev, iclass 7, count 0 2006.201.10:25:51.20#ibcon#first serial, iclass 7, count 0 2006.201.10:25:51.20#ibcon#enter sib2, iclass 7, count 0 2006.201.10:25:51.20#ibcon#flushed, iclass 7, count 0 2006.201.10:25:51.20#ibcon#about to write, iclass 7, count 0 2006.201.10:25:51.20#ibcon#wrote, iclass 7, count 0 2006.201.10:25:51.20#ibcon#about to read 3, iclass 7, count 0 2006.201.10:25:51.22#ibcon#read 3, iclass 7, count 0 2006.201.10:25:51.22#ibcon#about to read 4, iclass 7, count 0 2006.201.10:25:51.22#ibcon#read 4, iclass 7, count 0 2006.201.10:25:51.22#ibcon#about to read 5, iclass 7, count 0 2006.201.10:25:51.22#ibcon#read 5, iclass 7, count 0 2006.201.10:25:51.22#ibcon#about to read 6, iclass 7, count 0 2006.201.10:25:51.22#ibcon#read 6, iclass 7, count 0 2006.201.10:25:51.22#ibcon#end of sib2, iclass 7, count 0 2006.201.10:25:51.22#ibcon#*mode == 0, iclass 7, count 0 2006.201.10:25:51.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.10:25:51.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:25:51.22#ibcon#*before write, iclass 7, count 0 2006.201.10:25:51.22#ibcon#enter sib2, iclass 7, count 0 2006.201.10:25:51.22#ibcon#flushed, iclass 7, count 0 2006.201.10:25:51.22#ibcon#about to write, iclass 7, count 0 2006.201.10:25:51.22#ibcon#wrote, iclass 7, count 0 2006.201.10:25:51.22#ibcon#about to read 3, iclass 7, count 0 2006.201.10:25:51.26#ibcon#read 3, iclass 7, count 0 2006.201.10:25:51.26#ibcon#about to read 4, iclass 7, count 0 2006.201.10:25:51.26#ibcon#read 4, iclass 7, count 0 2006.201.10:25:51.26#ibcon#about to read 5, iclass 7, count 0 2006.201.10:25:51.26#ibcon#read 5, iclass 7, count 0 2006.201.10:25:51.26#ibcon#about to read 6, iclass 7, count 0 2006.201.10:25:51.26#ibcon#read 6, iclass 7, count 0 2006.201.10:25:51.26#ibcon#end of sib2, iclass 7, count 0 2006.201.10:25:51.26#ibcon#*after write, iclass 7, count 0 2006.201.10:25:51.26#ibcon#*before return 0, iclass 7, count 0 2006.201.10:25:51.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:25:51.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:25:51.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.10:25:51.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.10:25:51.26$vck44/va=2,7 2006.201.10:25:51.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.10:25:51.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.10:25:51.26#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:51.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:25:51.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:25:51.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:25:51.32#ibcon#enter wrdev, iclass 11, count 2 2006.201.10:25:51.32#ibcon#first serial, iclass 11, count 2 2006.201.10:25:51.32#ibcon#enter sib2, iclass 11, count 2 2006.201.10:25:51.32#ibcon#flushed, iclass 11, count 2 2006.201.10:25:51.32#ibcon#about to write, iclass 11, count 2 2006.201.10:25:51.32#ibcon#wrote, iclass 11, count 2 2006.201.10:25:51.32#ibcon#about to read 3, iclass 11, count 2 2006.201.10:25:51.34#ibcon#read 3, iclass 11, count 2 2006.201.10:25:51.34#ibcon#about to read 4, iclass 11, count 2 2006.201.10:25:51.34#ibcon#read 4, iclass 11, count 2 2006.201.10:25:51.34#ibcon#about to read 5, iclass 11, count 2 2006.201.10:25:51.34#ibcon#read 5, iclass 11, count 2 2006.201.10:25:51.34#ibcon#about to read 6, iclass 11, count 2 2006.201.10:25:51.34#ibcon#read 6, iclass 11, count 2 2006.201.10:25:51.34#ibcon#end of sib2, iclass 11, count 2 2006.201.10:25:51.34#ibcon#*mode == 0, iclass 11, count 2 2006.201.10:25:51.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.10:25:51.34#ibcon#[25=AT02-07\r\n] 2006.201.10:25:51.34#ibcon#*before write, iclass 11, count 2 2006.201.10:25:51.34#ibcon#enter sib2, iclass 11, count 2 2006.201.10:25:51.34#ibcon#flushed, iclass 11, count 2 2006.201.10:25:51.34#ibcon#about to write, iclass 11, count 2 2006.201.10:25:51.34#ibcon#wrote, iclass 11, count 2 2006.201.10:25:51.34#ibcon#about to read 3, iclass 11, count 2 2006.201.10:25:51.37#ibcon#read 3, iclass 11, count 2 2006.201.10:25:51.37#ibcon#about to read 4, iclass 11, count 2 2006.201.10:25:51.37#ibcon#read 4, iclass 11, count 2 2006.201.10:25:51.37#ibcon#about to read 5, iclass 11, count 2 2006.201.10:25:51.37#ibcon#read 5, iclass 11, count 2 2006.201.10:25:51.37#ibcon#about to read 6, iclass 11, count 2 2006.201.10:25:51.37#ibcon#read 6, iclass 11, count 2 2006.201.10:25:51.37#ibcon#end of sib2, iclass 11, count 2 2006.201.10:25:51.37#ibcon#*after write, iclass 11, count 2 2006.201.10:25:51.37#ibcon#*before return 0, iclass 11, count 2 2006.201.10:25:51.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:25:51.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:25:51.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.10:25:51.37#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:51.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:25:51.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:25:51.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:25:51.49#ibcon#enter wrdev, iclass 11, count 0 2006.201.10:25:51.49#ibcon#first serial, iclass 11, count 0 2006.201.10:25:51.49#ibcon#enter sib2, iclass 11, count 0 2006.201.10:25:51.49#ibcon#flushed, iclass 11, count 0 2006.201.10:25:51.49#ibcon#about to write, iclass 11, count 0 2006.201.10:25:51.49#ibcon#wrote, iclass 11, count 0 2006.201.10:25:51.49#ibcon#about to read 3, iclass 11, count 0 2006.201.10:25:51.51#ibcon#read 3, iclass 11, count 0 2006.201.10:25:51.51#ibcon#about to read 4, iclass 11, count 0 2006.201.10:25:51.51#ibcon#read 4, iclass 11, count 0 2006.201.10:25:51.51#ibcon#about to read 5, iclass 11, count 0 2006.201.10:25:51.51#ibcon#read 5, iclass 11, count 0 2006.201.10:25:51.51#ibcon#about to read 6, iclass 11, count 0 2006.201.10:25:51.51#ibcon#read 6, iclass 11, count 0 2006.201.10:25:51.51#ibcon#end of sib2, iclass 11, count 0 2006.201.10:25:51.51#ibcon#*mode == 0, iclass 11, count 0 2006.201.10:25:51.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.10:25:51.51#ibcon#[25=USB\r\n] 2006.201.10:25:51.51#ibcon#*before write, iclass 11, count 0 2006.201.10:25:51.51#ibcon#enter sib2, iclass 11, count 0 2006.201.10:25:51.51#ibcon#flushed, iclass 11, count 0 2006.201.10:25:51.51#ibcon#about to write, iclass 11, count 0 2006.201.10:25:51.51#ibcon#wrote, iclass 11, count 0 2006.201.10:25:51.51#ibcon#about to read 3, iclass 11, count 0 2006.201.10:25:51.54#ibcon#read 3, iclass 11, count 0 2006.201.10:25:51.54#ibcon#about to read 4, iclass 11, count 0 2006.201.10:25:51.54#ibcon#read 4, iclass 11, count 0 2006.201.10:25:51.54#ibcon#about to read 5, iclass 11, count 0 2006.201.10:25:51.54#ibcon#read 5, iclass 11, count 0 2006.201.10:25:51.54#ibcon#about to read 6, iclass 11, count 0 2006.201.10:25:51.54#ibcon#read 6, iclass 11, count 0 2006.201.10:25:51.54#ibcon#end of sib2, iclass 11, count 0 2006.201.10:25:51.54#ibcon#*after write, iclass 11, count 0 2006.201.10:25:51.54#ibcon#*before return 0, iclass 11, count 0 2006.201.10:25:51.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:25:51.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:25:51.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.10:25:51.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.10:25:51.54$vck44/valo=3,564.99 2006.201.10:25:51.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.10:25:51.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.10:25:51.54#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:51.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:51.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:51.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:51.54#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:25:51.54#ibcon#first serial, iclass 13, count 0 2006.201.10:25:51.54#ibcon#enter sib2, iclass 13, count 0 2006.201.10:25:51.54#ibcon#flushed, iclass 13, count 0 2006.201.10:25:51.54#ibcon#about to write, iclass 13, count 0 2006.201.10:25:51.54#ibcon#wrote, iclass 13, count 0 2006.201.10:25:51.54#ibcon#about to read 3, iclass 13, count 0 2006.201.10:25:51.56#ibcon#read 3, iclass 13, count 0 2006.201.10:25:51.56#ibcon#about to read 4, iclass 13, count 0 2006.201.10:25:51.56#ibcon#read 4, iclass 13, count 0 2006.201.10:25:51.56#ibcon#about to read 5, iclass 13, count 0 2006.201.10:25:51.56#ibcon#read 5, iclass 13, count 0 2006.201.10:25:51.56#ibcon#about to read 6, iclass 13, count 0 2006.201.10:25:51.56#ibcon#read 6, iclass 13, count 0 2006.201.10:25:51.56#ibcon#end of sib2, iclass 13, count 0 2006.201.10:25:51.56#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:25:51.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:25:51.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:25:51.56#ibcon#*before write, iclass 13, count 0 2006.201.10:25:51.56#ibcon#enter sib2, iclass 13, count 0 2006.201.10:25:51.56#ibcon#flushed, iclass 13, count 0 2006.201.10:25:51.56#ibcon#about to write, iclass 13, count 0 2006.201.10:25:51.56#ibcon#wrote, iclass 13, count 0 2006.201.10:25:51.56#ibcon#about to read 3, iclass 13, count 0 2006.201.10:25:51.61#ibcon#read 3, iclass 13, count 0 2006.201.10:25:51.61#ibcon#about to read 4, iclass 13, count 0 2006.201.10:25:51.61#ibcon#read 4, iclass 13, count 0 2006.201.10:25:51.61#ibcon#about to read 5, iclass 13, count 0 2006.201.10:25:51.61#ibcon#read 5, iclass 13, count 0 2006.201.10:25:51.61#ibcon#about to read 6, iclass 13, count 0 2006.201.10:25:51.61#ibcon#read 6, iclass 13, count 0 2006.201.10:25:51.61#ibcon#end of sib2, iclass 13, count 0 2006.201.10:25:51.61#ibcon#*after write, iclass 13, count 0 2006.201.10:25:51.61#ibcon#*before return 0, iclass 13, count 0 2006.201.10:25:51.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:51.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:51.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:25:51.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:25:51.61$vck44/va=3,8 2006.201.10:25:51.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.10:25:51.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.10:25:51.61#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:51.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:51.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:51.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:51.66#ibcon#enter wrdev, iclass 15, count 2 2006.201.10:25:51.66#ibcon#first serial, iclass 15, count 2 2006.201.10:25:51.66#ibcon#enter sib2, iclass 15, count 2 2006.201.10:25:51.66#ibcon#flushed, iclass 15, count 2 2006.201.10:25:51.66#ibcon#about to write, iclass 15, count 2 2006.201.10:25:51.66#ibcon#wrote, iclass 15, count 2 2006.201.10:25:51.66#ibcon#about to read 3, iclass 15, count 2 2006.201.10:25:51.68#ibcon#read 3, iclass 15, count 2 2006.201.10:25:51.68#ibcon#about to read 4, iclass 15, count 2 2006.201.10:25:51.68#ibcon#read 4, iclass 15, count 2 2006.201.10:25:51.68#ibcon#about to read 5, iclass 15, count 2 2006.201.10:25:51.68#ibcon#read 5, iclass 15, count 2 2006.201.10:25:51.68#ibcon#about to read 6, iclass 15, count 2 2006.201.10:25:51.68#ibcon#read 6, iclass 15, count 2 2006.201.10:25:51.68#ibcon#end of sib2, iclass 15, count 2 2006.201.10:25:51.68#ibcon#*mode == 0, iclass 15, count 2 2006.201.10:25:51.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.10:25:51.68#ibcon#[25=AT03-08\r\n] 2006.201.10:25:51.68#ibcon#*before write, iclass 15, count 2 2006.201.10:25:51.68#ibcon#enter sib2, iclass 15, count 2 2006.201.10:25:51.68#ibcon#flushed, iclass 15, count 2 2006.201.10:25:51.68#ibcon#about to write, iclass 15, count 2 2006.201.10:25:51.68#ibcon#wrote, iclass 15, count 2 2006.201.10:25:51.68#ibcon#about to read 3, iclass 15, count 2 2006.201.10:25:51.71#ibcon#read 3, iclass 15, count 2 2006.201.10:25:51.71#ibcon#about to read 4, iclass 15, count 2 2006.201.10:25:51.71#ibcon#read 4, iclass 15, count 2 2006.201.10:25:51.71#ibcon#about to read 5, iclass 15, count 2 2006.201.10:25:51.71#ibcon#read 5, iclass 15, count 2 2006.201.10:25:51.71#ibcon#about to read 6, iclass 15, count 2 2006.201.10:25:51.71#ibcon#read 6, iclass 15, count 2 2006.201.10:25:51.71#ibcon#end of sib2, iclass 15, count 2 2006.201.10:25:51.71#ibcon#*after write, iclass 15, count 2 2006.201.10:25:51.71#ibcon#*before return 0, iclass 15, count 2 2006.201.10:25:51.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:51.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:51.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.10:25:51.71#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:51.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:51.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:51.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:51.83#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:25:51.83#ibcon#first serial, iclass 15, count 0 2006.201.10:25:51.83#ibcon#enter sib2, iclass 15, count 0 2006.201.10:25:51.83#ibcon#flushed, iclass 15, count 0 2006.201.10:25:51.83#ibcon#about to write, iclass 15, count 0 2006.201.10:25:51.83#ibcon#wrote, iclass 15, count 0 2006.201.10:25:51.83#ibcon#about to read 3, iclass 15, count 0 2006.201.10:25:51.85#ibcon#read 3, iclass 15, count 0 2006.201.10:25:51.85#ibcon#about to read 4, iclass 15, count 0 2006.201.10:25:51.85#ibcon#read 4, iclass 15, count 0 2006.201.10:25:51.85#ibcon#about to read 5, iclass 15, count 0 2006.201.10:25:51.85#ibcon#read 5, iclass 15, count 0 2006.201.10:25:51.85#ibcon#about to read 6, iclass 15, count 0 2006.201.10:25:51.85#ibcon#read 6, iclass 15, count 0 2006.201.10:25:51.85#ibcon#end of sib2, iclass 15, count 0 2006.201.10:25:51.85#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:25:51.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:25:51.85#ibcon#[25=USB\r\n] 2006.201.10:25:51.85#ibcon#*before write, iclass 15, count 0 2006.201.10:25:51.85#ibcon#enter sib2, iclass 15, count 0 2006.201.10:25:51.85#ibcon#flushed, iclass 15, count 0 2006.201.10:25:51.85#ibcon#about to write, iclass 15, count 0 2006.201.10:25:51.85#ibcon#wrote, iclass 15, count 0 2006.201.10:25:51.85#ibcon#about to read 3, iclass 15, count 0 2006.201.10:25:51.88#ibcon#read 3, iclass 15, count 0 2006.201.10:25:51.88#ibcon#about to read 4, iclass 15, count 0 2006.201.10:25:51.88#ibcon#read 4, iclass 15, count 0 2006.201.10:25:51.88#ibcon#about to read 5, iclass 15, count 0 2006.201.10:25:51.88#ibcon#read 5, iclass 15, count 0 2006.201.10:25:51.88#ibcon#about to read 6, iclass 15, count 0 2006.201.10:25:51.88#ibcon#read 6, iclass 15, count 0 2006.201.10:25:51.88#ibcon#end of sib2, iclass 15, count 0 2006.201.10:25:51.88#ibcon#*after write, iclass 15, count 0 2006.201.10:25:51.88#ibcon#*before return 0, iclass 15, count 0 2006.201.10:25:51.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:51.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:51.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:25:51.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:25:51.88$vck44/valo=4,624.99 2006.201.10:25:51.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.10:25:51.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.10:25:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:51.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:51.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:51.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:51.88#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:25:51.88#ibcon#first serial, iclass 17, count 0 2006.201.10:25:51.88#ibcon#enter sib2, iclass 17, count 0 2006.201.10:25:51.88#ibcon#flushed, iclass 17, count 0 2006.201.10:25:51.88#ibcon#about to write, iclass 17, count 0 2006.201.10:25:51.88#ibcon#wrote, iclass 17, count 0 2006.201.10:25:51.88#ibcon#about to read 3, iclass 17, count 0 2006.201.10:25:51.90#ibcon#read 3, iclass 17, count 0 2006.201.10:25:51.90#ibcon#about to read 4, iclass 17, count 0 2006.201.10:25:51.90#ibcon#read 4, iclass 17, count 0 2006.201.10:25:51.90#ibcon#about to read 5, iclass 17, count 0 2006.201.10:25:51.90#ibcon#read 5, iclass 17, count 0 2006.201.10:25:51.90#ibcon#about to read 6, iclass 17, count 0 2006.201.10:25:51.90#ibcon#read 6, iclass 17, count 0 2006.201.10:25:51.90#ibcon#end of sib2, iclass 17, count 0 2006.201.10:25:51.90#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:25:51.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:25:51.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:25:51.90#ibcon#*before write, iclass 17, count 0 2006.201.10:25:51.90#ibcon#enter sib2, iclass 17, count 0 2006.201.10:25:51.90#ibcon#flushed, iclass 17, count 0 2006.201.10:25:51.90#ibcon#about to write, iclass 17, count 0 2006.201.10:25:51.90#ibcon#wrote, iclass 17, count 0 2006.201.10:25:51.90#ibcon#about to read 3, iclass 17, count 0 2006.201.10:25:51.95#ibcon#read 3, iclass 17, count 0 2006.201.10:25:51.95#ibcon#about to read 4, iclass 17, count 0 2006.201.10:25:51.95#ibcon#read 4, iclass 17, count 0 2006.201.10:25:51.95#ibcon#about to read 5, iclass 17, count 0 2006.201.10:25:51.95#ibcon#read 5, iclass 17, count 0 2006.201.10:25:51.95#ibcon#about to read 6, iclass 17, count 0 2006.201.10:25:51.95#ibcon#read 6, iclass 17, count 0 2006.201.10:25:51.95#ibcon#end of sib2, iclass 17, count 0 2006.201.10:25:51.95#ibcon#*after write, iclass 17, count 0 2006.201.10:25:51.95#ibcon#*before return 0, iclass 17, count 0 2006.201.10:25:51.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:51.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:51.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:25:51.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:25:51.95$vck44/va=4,7 2006.201.10:25:51.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.10:25:51.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.10:25:51.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:51.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:52.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:52.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:52.00#ibcon#enter wrdev, iclass 19, count 2 2006.201.10:25:52.00#ibcon#first serial, iclass 19, count 2 2006.201.10:25:52.00#ibcon#enter sib2, iclass 19, count 2 2006.201.10:25:52.00#ibcon#flushed, iclass 19, count 2 2006.201.10:25:52.00#ibcon#about to write, iclass 19, count 2 2006.201.10:25:52.00#ibcon#wrote, iclass 19, count 2 2006.201.10:25:52.00#ibcon#about to read 3, iclass 19, count 2 2006.201.10:25:52.02#ibcon#read 3, iclass 19, count 2 2006.201.10:25:52.02#ibcon#about to read 4, iclass 19, count 2 2006.201.10:25:52.02#ibcon#read 4, iclass 19, count 2 2006.201.10:25:52.02#ibcon#about to read 5, iclass 19, count 2 2006.201.10:25:52.02#ibcon#read 5, iclass 19, count 2 2006.201.10:25:52.02#ibcon#about to read 6, iclass 19, count 2 2006.201.10:25:52.02#ibcon#read 6, iclass 19, count 2 2006.201.10:25:52.02#ibcon#end of sib2, iclass 19, count 2 2006.201.10:25:52.02#ibcon#*mode == 0, iclass 19, count 2 2006.201.10:25:52.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.10:25:52.02#ibcon#[25=AT04-07\r\n] 2006.201.10:25:52.02#ibcon#*before write, iclass 19, count 2 2006.201.10:25:52.02#ibcon#enter sib2, iclass 19, count 2 2006.201.10:25:52.02#ibcon#flushed, iclass 19, count 2 2006.201.10:25:52.02#ibcon#about to write, iclass 19, count 2 2006.201.10:25:52.02#ibcon#wrote, iclass 19, count 2 2006.201.10:25:52.02#ibcon#about to read 3, iclass 19, count 2 2006.201.10:25:52.05#ibcon#read 3, iclass 19, count 2 2006.201.10:25:52.05#ibcon#about to read 4, iclass 19, count 2 2006.201.10:25:52.05#ibcon#read 4, iclass 19, count 2 2006.201.10:25:52.05#ibcon#about to read 5, iclass 19, count 2 2006.201.10:25:52.05#ibcon#read 5, iclass 19, count 2 2006.201.10:25:52.05#ibcon#about to read 6, iclass 19, count 2 2006.201.10:25:52.05#ibcon#read 6, iclass 19, count 2 2006.201.10:25:52.05#ibcon#end of sib2, iclass 19, count 2 2006.201.10:25:52.05#ibcon#*after write, iclass 19, count 2 2006.201.10:25:52.05#ibcon#*before return 0, iclass 19, count 2 2006.201.10:25:52.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:52.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:52.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.10:25:52.05#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:52.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:52.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:52.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:52.17#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:25:52.17#ibcon#first serial, iclass 19, count 0 2006.201.10:25:52.17#ibcon#enter sib2, iclass 19, count 0 2006.201.10:25:52.17#ibcon#flushed, iclass 19, count 0 2006.201.10:25:52.17#ibcon#about to write, iclass 19, count 0 2006.201.10:25:52.17#ibcon#wrote, iclass 19, count 0 2006.201.10:25:52.17#ibcon#about to read 3, iclass 19, count 0 2006.201.10:25:52.19#ibcon#read 3, iclass 19, count 0 2006.201.10:25:52.19#ibcon#about to read 4, iclass 19, count 0 2006.201.10:25:52.19#ibcon#read 4, iclass 19, count 0 2006.201.10:25:52.19#ibcon#about to read 5, iclass 19, count 0 2006.201.10:25:52.19#ibcon#read 5, iclass 19, count 0 2006.201.10:25:52.19#ibcon#about to read 6, iclass 19, count 0 2006.201.10:25:52.19#ibcon#read 6, iclass 19, count 0 2006.201.10:25:52.19#ibcon#end of sib2, iclass 19, count 0 2006.201.10:25:52.19#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:25:52.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:25:52.19#ibcon#[25=USB\r\n] 2006.201.10:25:52.19#ibcon#*before write, iclass 19, count 0 2006.201.10:25:52.19#ibcon#enter sib2, iclass 19, count 0 2006.201.10:25:52.19#ibcon#flushed, iclass 19, count 0 2006.201.10:25:52.19#ibcon#about to write, iclass 19, count 0 2006.201.10:25:52.19#ibcon#wrote, iclass 19, count 0 2006.201.10:25:52.19#ibcon#about to read 3, iclass 19, count 0 2006.201.10:25:52.22#ibcon#read 3, iclass 19, count 0 2006.201.10:25:52.22#ibcon#about to read 4, iclass 19, count 0 2006.201.10:25:52.22#ibcon#read 4, iclass 19, count 0 2006.201.10:25:52.22#ibcon#about to read 5, iclass 19, count 0 2006.201.10:25:52.22#ibcon#read 5, iclass 19, count 0 2006.201.10:25:52.22#ibcon#about to read 6, iclass 19, count 0 2006.201.10:25:52.22#ibcon#read 6, iclass 19, count 0 2006.201.10:25:52.22#ibcon#end of sib2, iclass 19, count 0 2006.201.10:25:52.22#ibcon#*after write, iclass 19, count 0 2006.201.10:25:52.22#ibcon#*before return 0, iclass 19, count 0 2006.201.10:25:52.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:52.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:52.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:25:52.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:25:52.22$vck44/valo=5,734.99 2006.201.10:25:52.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.10:25:52.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.10:25:52.22#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:52.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:52.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:52.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:52.22#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:25:52.22#ibcon#first serial, iclass 21, count 0 2006.201.10:25:52.22#ibcon#enter sib2, iclass 21, count 0 2006.201.10:25:52.22#ibcon#flushed, iclass 21, count 0 2006.201.10:25:52.22#ibcon#about to write, iclass 21, count 0 2006.201.10:25:52.22#ibcon#wrote, iclass 21, count 0 2006.201.10:25:52.22#ibcon#about to read 3, iclass 21, count 0 2006.201.10:25:52.24#ibcon#read 3, iclass 21, count 0 2006.201.10:25:52.24#ibcon#about to read 4, iclass 21, count 0 2006.201.10:25:52.24#ibcon#read 4, iclass 21, count 0 2006.201.10:25:52.24#ibcon#about to read 5, iclass 21, count 0 2006.201.10:25:52.24#ibcon#read 5, iclass 21, count 0 2006.201.10:25:52.24#ibcon#about to read 6, iclass 21, count 0 2006.201.10:25:52.24#ibcon#read 6, iclass 21, count 0 2006.201.10:25:52.24#ibcon#end of sib2, iclass 21, count 0 2006.201.10:25:52.24#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:25:52.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:25:52.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:25:52.24#ibcon#*before write, iclass 21, count 0 2006.201.10:25:52.24#ibcon#enter sib2, iclass 21, count 0 2006.201.10:25:52.24#ibcon#flushed, iclass 21, count 0 2006.201.10:25:52.24#ibcon#about to write, iclass 21, count 0 2006.201.10:25:52.24#ibcon#wrote, iclass 21, count 0 2006.201.10:25:52.24#ibcon#about to read 3, iclass 21, count 0 2006.201.10:25:52.28#ibcon#read 3, iclass 21, count 0 2006.201.10:25:52.28#ibcon#about to read 4, iclass 21, count 0 2006.201.10:25:52.28#ibcon#read 4, iclass 21, count 0 2006.201.10:25:52.28#ibcon#about to read 5, iclass 21, count 0 2006.201.10:25:52.28#ibcon#read 5, iclass 21, count 0 2006.201.10:25:52.28#ibcon#about to read 6, iclass 21, count 0 2006.201.10:25:52.28#ibcon#read 6, iclass 21, count 0 2006.201.10:25:52.28#ibcon#end of sib2, iclass 21, count 0 2006.201.10:25:52.28#ibcon#*after write, iclass 21, count 0 2006.201.10:25:52.28#ibcon#*before return 0, iclass 21, count 0 2006.201.10:25:52.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:52.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:52.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:25:52.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:25:52.28$vck44/va=5,4 2006.201.10:25:52.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.10:25:52.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.10:25:52.28#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:52.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:52.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:52.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:52.34#ibcon#enter wrdev, iclass 23, count 2 2006.201.10:25:52.34#ibcon#first serial, iclass 23, count 2 2006.201.10:25:52.34#ibcon#enter sib2, iclass 23, count 2 2006.201.10:25:52.34#ibcon#flushed, iclass 23, count 2 2006.201.10:25:52.34#ibcon#about to write, iclass 23, count 2 2006.201.10:25:52.34#ibcon#wrote, iclass 23, count 2 2006.201.10:25:52.34#ibcon#about to read 3, iclass 23, count 2 2006.201.10:25:52.36#ibcon#read 3, iclass 23, count 2 2006.201.10:25:52.36#ibcon#about to read 4, iclass 23, count 2 2006.201.10:25:52.36#ibcon#read 4, iclass 23, count 2 2006.201.10:25:52.36#ibcon#about to read 5, iclass 23, count 2 2006.201.10:25:52.36#ibcon#read 5, iclass 23, count 2 2006.201.10:25:52.36#ibcon#about to read 6, iclass 23, count 2 2006.201.10:25:52.36#ibcon#read 6, iclass 23, count 2 2006.201.10:25:52.36#ibcon#end of sib2, iclass 23, count 2 2006.201.10:25:52.36#ibcon#*mode == 0, iclass 23, count 2 2006.201.10:25:52.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.10:25:52.36#ibcon#[25=AT05-04\r\n] 2006.201.10:25:52.36#ibcon#*before write, iclass 23, count 2 2006.201.10:25:52.36#ibcon#enter sib2, iclass 23, count 2 2006.201.10:25:52.36#ibcon#flushed, iclass 23, count 2 2006.201.10:25:52.36#ibcon#about to write, iclass 23, count 2 2006.201.10:25:52.36#ibcon#wrote, iclass 23, count 2 2006.201.10:25:52.36#ibcon#about to read 3, iclass 23, count 2 2006.201.10:25:52.39#ibcon#read 3, iclass 23, count 2 2006.201.10:25:52.39#ibcon#about to read 4, iclass 23, count 2 2006.201.10:25:52.39#ibcon#read 4, iclass 23, count 2 2006.201.10:25:52.39#ibcon#about to read 5, iclass 23, count 2 2006.201.10:25:52.39#ibcon#read 5, iclass 23, count 2 2006.201.10:25:52.39#ibcon#about to read 6, iclass 23, count 2 2006.201.10:25:52.39#ibcon#read 6, iclass 23, count 2 2006.201.10:25:52.39#ibcon#end of sib2, iclass 23, count 2 2006.201.10:25:52.39#ibcon#*after write, iclass 23, count 2 2006.201.10:25:52.39#ibcon#*before return 0, iclass 23, count 2 2006.201.10:25:52.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:52.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:52.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.10:25:52.39#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:52.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:52.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:52.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:52.51#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:25:52.51#ibcon#first serial, iclass 23, count 0 2006.201.10:25:52.51#ibcon#enter sib2, iclass 23, count 0 2006.201.10:25:52.51#ibcon#flushed, iclass 23, count 0 2006.201.10:25:52.51#ibcon#about to write, iclass 23, count 0 2006.201.10:25:52.51#ibcon#wrote, iclass 23, count 0 2006.201.10:25:52.51#ibcon#about to read 3, iclass 23, count 0 2006.201.10:25:52.53#ibcon#read 3, iclass 23, count 0 2006.201.10:25:52.53#ibcon#about to read 4, iclass 23, count 0 2006.201.10:25:52.53#ibcon#read 4, iclass 23, count 0 2006.201.10:25:52.53#ibcon#about to read 5, iclass 23, count 0 2006.201.10:25:52.53#ibcon#read 5, iclass 23, count 0 2006.201.10:25:52.53#ibcon#about to read 6, iclass 23, count 0 2006.201.10:25:52.53#ibcon#read 6, iclass 23, count 0 2006.201.10:25:52.53#ibcon#end of sib2, iclass 23, count 0 2006.201.10:25:52.53#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:25:52.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:25:52.53#ibcon#[25=USB\r\n] 2006.201.10:25:52.53#ibcon#*before write, iclass 23, count 0 2006.201.10:25:52.53#ibcon#enter sib2, iclass 23, count 0 2006.201.10:25:52.53#ibcon#flushed, iclass 23, count 0 2006.201.10:25:52.53#ibcon#about to write, iclass 23, count 0 2006.201.10:25:52.53#ibcon#wrote, iclass 23, count 0 2006.201.10:25:52.53#ibcon#about to read 3, iclass 23, count 0 2006.201.10:25:52.56#ibcon#read 3, iclass 23, count 0 2006.201.10:25:52.56#ibcon#about to read 4, iclass 23, count 0 2006.201.10:25:52.56#ibcon#read 4, iclass 23, count 0 2006.201.10:25:52.56#ibcon#about to read 5, iclass 23, count 0 2006.201.10:25:52.56#ibcon#read 5, iclass 23, count 0 2006.201.10:25:52.56#ibcon#about to read 6, iclass 23, count 0 2006.201.10:25:52.56#ibcon#read 6, iclass 23, count 0 2006.201.10:25:52.56#ibcon#end of sib2, iclass 23, count 0 2006.201.10:25:52.56#ibcon#*after write, iclass 23, count 0 2006.201.10:25:52.56#ibcon#*before return 0, iclass 23, count 0 2006.201.10:25:52.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:52.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:52.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:25:52.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:25:52.56$vck44/valo=6,814.99 2006.201.10:25:52.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.10:25:52.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.10:25:52.56#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:52.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:52.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:52.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:52.56#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:25:52.56#ibcon#first serial, iclass 25, count 0 2006.201.10:25:52.56#ibcon#enter sib2, iclass 25, count 0 2006.201.10:25:52.56#ibcon#flushed, iclass 25, count 0 2006.201.10:25:52.56#ibcon#about to write, iclass 25, count 0 2006.201.10:25:52.56#ibcon#wrote, iclass 25, count 0 2006.201.10:25:52.56#ibcon#about to read 3, iclass 25, count 0 2006.201.10:25:52.58#ibcon#read 3, iclass 25, count 0 2006.201.10:25:52.58#ibcon#about to read 4, iclass 25, count 0 2006.201.10:25:52.58#ibcon#read 4, iclass 25, count 0 2006.201.10:25:52.58#ibcon#about to read 5, iclass 25, count 0 2006.201.10:25:52.58#ibcon#read 5, iclass 25, count 0 2006.201.10:25:52.58#ibcon#about to read 6, iclass 25, count 0 2006.201.10:25:52.58#ibcon#read 6, iclass 25, count 0 2006.201.10:25:52.58#ibcon#end of sib2, iclass 25, count 0 2006.201.10:25:52.58#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:25:52.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:25:52.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:25:52.58#ibcon#*before write, iclass 25, count 0 2006.201.10:25:52.58#ibcon#enter sib2, iclass 25, count 0 2006.201.10:25:52.58#ibcon#flushed, iclass 25, count 0 2006.201.10:25:52.58#ibcon#about to write, iclass 25, count 0 2006.201.10:25:52.58#ibcon#wrote, iclass 25, count 0 2006.201.10:25:52.58#ibcon#about to read 3, iclass 25, count 0 2006.201.10:25:52.63#ibcon#read 3, iclass 25, count 0 2006.201.10:25:52.63#ibcon#about to read 4, iclass 25, count 0 2006.201.10:25:52.63#ibcon#read 4, iclass 25, count 0 2006.201.10:25:52.63#ibcon#about to read 5, iclass 25, count 0 2006.201.10:25:52.63#ibcon#read 5, iclass 25, count 0 2006.201.10:25:52.63#ibcon#about to read 6, iclass 25, count 0 2006.201.10:25:52.63#ibcon#read 6, iclass 25, count 0 2006.201.10:25:52.63#ibcon#end of sib2, iclass 25, count 0 2006.201.10:25:52.63#ibcon#*after write, iclass 25, count 0 2006.201.10:25:52.63#ibcon#*before return 0, iclass 25, count 0 2006.201.10:25:52.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:52.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:52.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:25:52.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:25:52.63$vck44/va=6,5 2006.201.10:25:52.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.10:25:52.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.10:25:52.63#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:52.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:52.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:52.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:52.68#ibcon#enter wrdev, iclass 27, count 2 2006.201.10:25:52.68#ibcon#first serial, iclass 27, count 2 2006.201.10:25:52.68#ibcon#enter sib2, iclass 27, count 2 2006.201.10:25:52.68#ibcon#flushed, iclass 27, count 2 2006.201.10:25:52.68#ibcon#about to write, iclass 27, count 2 2006.201.10:25:52.68#ibcon#wrote, iclass 27, count 2 2006.201.10:25:52.68#ibcon#about to read 3, iclass 27, count 2 2006.201.10:25:52.70#ibcon#read 3, iclass 27, count 2 2006.201.10:25:52.70#ibcon#about to read 4, iclass 27, count 2 2006.201.10:25:52.70#ibcon#read 4, iclass 27, count 2 2006.201.10:25:52.70#ibcon#about to read 5, iclass 27, count 2 2006.201.10:25:52.70#ibcon#read 5, iclass 27, count 2 2006.201.10:25:52.70#ibcon#about to read 6, iclass 27, count 2 2006.201.10:25:52.70#ibcon#read 6, iclass 27, count 2 2006.201.10:25:52.70#ibcon#end of sib2, iclass 27, count 2 2006.201.10:25:52.70#ibcon#*mode == 0, iclass 27, count 2 2006.201.10:25:52.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.10:25:52.70#ibcon#[25=AT06-05\r\n] 2006.201.10:25:52.70#ibcon#*before write, iclass 27, count 2 2006.201.10:25:52.70#ibcon#enter sib2, iclass 27, count 2 2006.201.10:25:52.70#ibcon#flushed, iclass 27, count 2 2006.201.10:25:52.70#ibcon#about to write, iclass 27, count 2 2006.201.10:25:52.70#ibcon#wrote, iclass 27, count 2 2006.201.10:25:52.70#ibcon#about to read 3, iclass 27, count 2 2006.201.10:25:52.73#ibcon#read 3, iclass 27, count 2 2006.201.10:25:52.73#ibcon#about to read 4, iclass 27, count 2 2006.201.10:25:52.73#ibcon#read 4, iclass 27, count 2 2006.201.10:25:52.73#ibcon#about to read 5, iclass 27, count 2 2006.201.10:25:52.73#ibcon#read 5, iclass 27, count 2 2006.201.10:25:52.73#ibcon#about to read 6, iclass 27, count 2 2006.201.10:25:52.73#ibcon#read 6, iclass 27, count 2 2006.201.10:25:52.73#ibcon#end of sib2, iclass 27, count 2 2006.201.10:25:52.73#ibcon#*after write, iclass 27, count 2 2006.201.10:25:52.73#ibcon#*before return 0, iclass 27, count 2 2006.201.10:25:52.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:52.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:52.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.10:25:52.73#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:52.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:52.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:52.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:52.85#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:25:52.85#ibcon#first serial, iclass 27, count 0 2006.201.10:25:52.85#ibcon#enter sib2, iclass 27, count 0 2006.201.10:25:52.85#ibcon#flushed, iclass 27, count 0 2006.201.10:25:52.85#ibcon#about to write, iclass 27, count 0 2006.201.10:25:52.85#ibcon#wrote, iclass 27, count 0 2006.201.10:25:52.85#ibcon#about to read 3, iclass 27, count 0 2006.201.10:25:52.87#ibcon#read 3, iclass 27, count 0 2006.201.10:25:52.87#ibcon#about to read 4, iclass 27, count 0 2006.201.10:25:52.87#ibcon#read 4, iclass 27, count 0 2006.201.10:25:52.87#ibcon#about to read 5, iclass 27, count 0 2006.201.10:25:52.87#ibcon#read 5, iclass 27, count 0 2006.201.10:25:52.87#ibcon#about to read 6, iclass 27, count 0 2006.201.10:25:52.87#ibcon#read 6, iclass 27, count 0 2006.201.10:25:52.87#ibcon#end of sib2, iclass 27, count 0 2006.201.10:25:52.87#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:25:52.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:25:52.87#ibcon#[25=USB\r\n] 2006.201.10:25:52.87#ibcon#*before write, iclass 27, count 0 2006.201.10:25:52.87#ibcon#enter sib2, iclass 27, count 0 2006.201.10:25:52.87#ibcon#flushed, iclass 27, count 0 2006.201.10:25:52.87#ibcon#about to write, iclass 27, count 0 2006.201.10:25:52.87#ibcon#wrote, iclass 27, count 0 2006.201.10:25:52.87#ibcon#about to read 3, iclass 27, count 0 2006.201.10:25:52.90#ibcon#read 3, iclass 27, count 0 2006.201.10:25:52.90#ibcon#about to read 4, iclass 27, count 0 2006.201.10:25:52.90#ibcon#read 4, iclass 27, count 0 2006.201.10:25:52.90#ibcon#about to read 5, iclass 27, count 0 2006.201.10:25:52.90#ibcon#read 5, iclass 27, count 0 2006.201.10:25:52.90#ibcon#about to read 6, iclass 27, count 0 2006.201.10:25:52.90#ibcon#read 6, iclass 27, count 0 2006.201.10:25:52.90#ibcon#end of sib2, iclass 27, count 0 2006.201.10:25:52.90#ibcon#*after write, iclass 27, count 0 2006.201.10:25:52.90#ibcon#*before return 0, iclass 27, count 0 2006.201.10:25:52.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:52.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:52.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:25:52.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:25:52.90$vck44/valo=7,864.99 2006.201.10:25:52.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.10:25:52.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.10:25:52.90#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:52.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:52.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:52.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:52.90#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:25:52.90#ibcon#first serial, iclass 29, count 0 2006.201.10:25:52.90#ibcon#enter sib2, iclass 29, count 0 2006.201.10:25:52.90#ibcon#flushed, iclass 29, count 0 2006.201.10:25:52.90#ibcon#about to write, iclass 29, count 0 2006.201.10:25:52.90#ibcon#wrote, iclass 29, count 0 2006.201.10:25:52.90#ibcon#about to read 3, iclass 29, count 0 2006.201.10:25:52.92#ibcon#read 3, iclass 29, count 0 2006.201.10:25:52.92#ibcon#about to read 4, iclass 29, count 0 2006.201.10:25:52.92#ibcon#read 4, iclass 29, count 0 2006.201.10:25:52.92#ibcon#about to read 5, iclass 29, count 0 2006.201.10:25:52.92#ibcon#read 5, iclass 29, count 0 2006.201.10:25:52.92#ibcon#about to read 6, iclass 29, count 0 2006.201.10:25:52.92#ibcon#read 6, iclass 29, count 0 2006.201.10:25:52.92#ibcon#end of sib2, iclass 29, count 0 2006.201.10:25:52.92#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:25:52.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:25:52.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:25:52.92#ibcon#*before write, iclass 29, count 0 2006.201.10:25:52.92#ibcon#enter sib2, iclass 29, count 0 2006.201.10:25:52.92#ibcon#flushed, iclass 29, count 0 2006.201.10:25:52.92#ibcon#about to write, iclass 29, count 0 2006.201.10:25:52.92#ibcon#wrote, iclass 29, count 0 2006.201.10:25:52.92#ibcon#about to read 3, iclass 29, count 0 2006.201.10:25:52.97#ibcon#read 3, iclass 29, count 0 2006.201.10:25:52.97#ibcon#about to read 4, iclass 29, count 0 2006.201.10:25:52.97#ibcon#read 4, iclass 29, count 0 2006.201.10:25:52.97#ibcon#about to read 5, iclass 29, count 0 2006.201.10:25:52.97#ibcon#read 5, iclass 29, count 0 2006.201.10:25:52.97#ibcon#about to read 6, iclass 29, count 0 2006.201.10:25:52.97#ibcon#read 6, iclass 29, count 0 2006.201.10:25:52.97#ibcon#end of sib2, iclass 29, count 0 2006.201.10:25:52.97#ibcon#*after write, iclass 29, count 0 2006.201.10:25:52.97#ibcon#*before return 0, iclass 29, count 0 2006.201.10:25:52.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:52.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:52.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:25:52.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:25:52.97$vck44/va=7,5 2006.201.10:25:52.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.10:25:52.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.10:25:52.97#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:52.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:53.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:53.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:53.02#ibcon#enter wrdev, iclass 31, count 2 2006.201.10:25:53.02#ibcon#first serial, iclass 31, count 2 2006.201.10:25:53.02#ibcon#enter sib2, iclass 31, count 2 2006.201.10:25:53.02#ibcon#flushed, iclass 31, count 2 2006.201.10:25:53.02#ibcon#about to write, iclass 31, count 2 2006.201.10:25:53.02#ibcon#wrote, iclass 31, count 2 2006.201.10:25:53.02#ibcon#about to read 3, iclass 31, count 2 2006.201.10:25:53.04#ibcon#read 3, iclass 31, count 2 2006.201.10:25:53.04#ibcon#about to read 4, iclass 31, count 2 2006.201.10:25:53.04#ibcon#read 4, iclass 31, count 2 2006.201.10:25:53.04#ibcon#about to read 5, iclass 31, count 2 2006.201.10:25:53.04#ibcon#read 5, iclass 31, count 2 2006.201.10:25:53.04#ibcon#about to read 6, iclass 31, count 2 2006.201.10:25:53.04#ibcon#read 6, iclass 31, count 2 2006.201.10:25:53.04#ibcon#end of sib2, iclass 31, count 2 2006.201.10:25:53.04#ibcon#*mode == 0, iclass 31, count 2 2006.201.10:25:53.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.10:25:53.04#ibcon#[25=AT07-05\r\n] 2006.201.10:25:53.04#ibcon#*before write, iclass 31, count 2 2006.201.10:25:53.04#ibcon#enter sib2, iclass 31, count 2 2006.201.10:25:53.04#ibcon#flushed, iclass 31, count 2 2006.201.10:25:53.04#ibcon#about to write, iclass 31, count 2 2006.201.10:25:53.04#ibcon#wrote, iclass 31, count 2 2006.201.10:25:53.04#ibcon#about to read 3, iclass 31, count 2 2006.201.10:25:53.07#ibcon#read 3, iclass 31, count 2 2006.201.10:25:53.07#ibcon#about to read 4, iclass 31, count 2 2006.201.10:25:53.07#ibcon#read 4, iclass 31, count 2 2006.201.10:25:53.07#ibcon#about to read 5, iclass 31, count 2 2006.201.10:25:53.07#ibcon#read 5, iclass 31, count 2 2006.201.10:25:53.07#ibcon#about to read 6, iclass 31, count 2 2006.201.10:25:53.07#ibcon#read 6, iclass 31, count 2 2006.201.10:25:53.07#ibcon#end of sib2, iclass 31, count 2 2006.201.10:25:53.07#ibcon#*after write, iclass 31, count 2 2006.201.10:25:53.07#ibcon#*before return 0, iclass 31, count 2 2006.201.10:25:53.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:53.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:53.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.10:25:53.07#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:53.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:53.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:53.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:53.19#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:25:53.19#ibcon#first serial, iclass 31, count 0 2006.201.10:25:53.19#ibcon#enter sib2, iclass 31, count 0 2006.201.10:25:53.19#ibcon#flushed, iclass 31, count 0 2006.201.10:25:53.19#ibcon#about to write, iclass 31, count 0 2006.201.10:25:53.19#ibcon#wrote, iclass 31, count 0 2006.201.10:25:53.19#ibcon#about to read 3, iclass 31, count 0 2006.201.10:25:53.21#ibcon#read 3, iclass 31, count 0 2006.201.10:25:53.21#ibcon#about to read 4, iclass 31, count 0 2006.201.10:25:53.21#ibcon#read 4, iclass 31, count 0 2006.201.10:25:53.21#ibcon#about to read 5, iclass 31, count 0 2006.201.10:25:53.21#ibcon#read 5, iclass 31, count 0 2006.201.10:25:53.21#ibcon#about to read 6, iclass 31, count 0 2006.201.10:25:53.21#ibcon#read 6, iclass 31, count 0 2006.201.10:25:53.21#ibcon#end of sib2, iclass 31, count 0 2006.201.10:25:53.21#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:25:53.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:25:53.21#ibcon#[25=USB\r\n] 2006.201.10:25:53.21#ibcon#*before write, iclass 31, count 0 2006.201.10:25:53.21#ibcon#enter sib2, iclass 31, count 0 2006.201.10:25:53.21#ibcon#flushed, iclass 31, count 0 2006.201.10:25:53.21#ibcon#about to write, iclass 31, count 0 2006.201.10:25:53.21#ibcon#wrote, iclass 31, count 0 2006.201.10:25:53.21#ibcon#about to read 3, iclass 31, count 0 2006.201.10:25:53.24#ibcon#read 3, iclass 31, count 0 2006.201.10:25:53.24#ibcon#about to read 4, iclass 31, count 0 2006.201.10:25:53.24#ibcon#read 4, iclass 31, count 0 2006.201.10:25:53.24#ibcon#about to read 5, iclass 31, count 0 2006.201.10:25:53.24#ibcon#read 5, iclass 31, count 0 2006.201.10:25:53.24#ibcon#about to read 6, iclass 31, count 0 2006.201.10:25:53.24#ibcon#read 6, iclass 31, count 0 2006.201.10:25:53.24#ibcon#end of sib2, iclass 31, count 0 2006.201.10:25:53.24#ibcon#*after write, iclass 31, count 0 2006.201.10:25:53.24#ibcon#*before return 0, iclass 31, count 0 2006.201.10:25:53.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:53.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:53.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:25:53.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:25:53.24$vck44/valo=8,884.99 2006.201.10:25:53.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.10:25:53.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.10:25:53.24#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:53.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:53.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:53.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:53.24#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:25:53.24#ibcon#first serial, iclass 33, count 0 2006.201.10:25:53.24#ibcon#enter sib2, iclass 33, count 0 2006.201.10:25:53.24#ibcon#flushed, iclass 33, count 0 2006.201.10:25:53.24#ibcon#about to write, iclass 33, count 0 2006.201.10:25:53.24#ibcon#wrote, iclass 33, count 0 2006.201.10:25:53.24#ibcon#about to read 3, iclass 33, count 0 2006.201.10:25:53.26#ibcon#read 3, iclass 33, count 0 2006.201.10:25:53.26#ibcon#about to read 4, iclass 33, count 0 2006.201.10:25:53.26#ibcon#read 4, iclass 33, count 0 2006.201.10:25:53.26#ibcon#about to read 5, iclass 33, count 0 2006.201.10:25:53.26#ibcon#read 5, iclass 33, count 0 2006.201.10:25:53.26#ibcon#about to read 6, iclass 33, count 0 2006.201.10:25:53.26#ibcon#read 6, iclass 33, count 0 2006.201.10:25:53.26#ibcon#end of sib2, iclass 33, count 0 2006.201.10:25:53.26#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:25:53.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:25:53.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:25:53.26#ibcon#*before write, iclass 33, count 0 2006.201.10:25:53.26#ibcon#enter sib2, iclass 33, count 0 2006.201.10:25:53.26#ibcon#flushed, iclass 33, count 0 2006.201.10:25:53.26#ibcon#about to write, iclass 33, count 0 2006.201.10:25:53.26#ibcon#wrote, iclass 33, count 0 2006.201.10:25:53.26#ibcon#about to read 3, iclass 33, count 0 2006.201.10:25:53.30#ibcon#read 3, iclass 33, count 0 2006.201.10:25:53.30#ibcon#about to read 4, iclass 33, count 0 2006.201.10:25:53.30#ibcon#read 4, iclass 33, count 0 2006.201.10:25:53.30#ibcon#about to read 5, iclass 33, count 0 2006.201.10:25:53.30#ibcon#read 5, iclass 33, count 0 2006.201.10:25:53.30#ibcon#about to read 6, iclass 33, count 0 2006.201.10:25:53.30#ibcon#read 6, iclass 33, count 0 2006.201.10:25:53.30#ibcon#end of sib2, iclass 33, count 0 2006.201.10:25:53.30#ibcon#*after write, iclass 33, count 0 2006.201.10:25:53.30#ibcon#*before return 0, iclass 33, count 0 2006.201.10:25:53.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:53.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:53.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:25:53.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:25:53.30$vck44/va=8,4 2006.201.10:25:53.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.10:25:53.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.10:25:53.30#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:53.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:53.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:53.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:53.36#ibcon#enter wrdev, iclass 35, count 2 2006.201.10:25:53.36#ibcon#first serial, iclass 35, count 2 2006.201.10:25:53.36#ibcon#enter sib2, iclass 35, count 2 2006.201.10:25:53.36#ibcon#flushed, iclass 35, count 2 2006.201.10:25:53.36#ibcon#about to write, iclass 35, count 2 2006.201.10:25:53.36#ibcon#wrote, iclass 35, count 2 2006.201.10:25:53.36#ibcon#about to read 3, iclass 35, count 2 2006.201.10:25:53.38#ibcon#read 3, iclass 35, count 2 2006.201.10:25:53.38#ibcon#about to read 4, iclass 35, count 2 2006.201.10:25:53.38#ibcon#read 4, iclass 35, count 2 2006.201.10:25:53.38#ibcon#about to read 5, iclass 35, count 2 2006.201.10:25:53.38#ibcon#read 5, iclass 35, count 2 2006.201.10:25:53.38#ibcon#about to read 6, iclass 35, count 2 2006.201.10:25:53.38#ibcon#read 6, iclass 35, count 2 2006.201.10:25:53.38#ibcon#end of sib2, iclass 35, count 2 2006.201.10:25:53.38#ibcon#*mode == 0, iclass 35, count 2 2006.201.10:25:53.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.10:25:53.38#ibcon#[25=AT08-04\r\n] 2006.201.10:25:53.38#ibcon#*before write, iclass 35, count 2 2006.201.10:25:53.38#ibcon#enter sib2, iclass 35, count 2 2006.201.10:25:53.38#ibcon#flushed, iclass 35, count 2 2006.201.10:25:53.38#ibcon#about to write, iclass 35, count 2 2006.201.10:25:53.38#ibcon#wrote, iclass 35, count 2 2006.201.10:25:53.38#ibcon#about to read 3, iclass 35, count 2 2006.201.10:25:53.41#ibcon#read 3, iclass 35, count 2 2006.201.10:25:53.41#ibcon#about to read 4, iclass 35, count 2 2006.201.10:25:53.41#ibcon#read 4, iclass 35, count 2 2006.201.10:25:53.41#ibcon#about to read 5, iclass 35, count 2 2006.201.10:25:53.41#ibcon#read 5, iclass 35, count 2 2006.201.10:25:53.41#ibcon#about to read 6, iclass 35, count 2 2006.201.10:25:53.41#ibcon#read 6, iclass 35, count 2 2006.201.10:25:53.41#ibcon#end of sib2, iclass 35, count 2 2006.201.10:25:53.41#ibcon#*after write, iclass 35, count 2 2006.201.10:25:53.41#ibcon#*before return 0, iclass 35, count 2 2006.201.10:25:53.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:53.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:53.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.10:25:53.41#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:53.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:53.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:53.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:53.53#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:25:53.53#ibcon#first serial, iclass 35, count 0 2006.201.10:25:53.53#ibcon#enter sib2, iclass 35, count 0 2006.201.10:25:53.53#ibcon#flushed, iclass 35, count 0 2006.201.10:25:53.53#ibcon#about to write, iclass 35, count 0 2006.201.10:25:53.53#ibcon#wrote, iclass 35, count 0 2006.201.10:25:53.53#ibcon#about to read 3, iclass 35, count 0 2006.201.10:25:53.55#ibcon#read 3, iclass 35, count 0 2006.201.10:25:53.55#ibcon#about to read 4, iclass 35, count 0 2006.201.10:25:53.55#ibcon#read 4, iclass 35, count 0 2006.201.10:25:53.55#ibcon#about to read 5, iclass 35, count 0 2006.201.10:25:53.55#ibcon#read 5, iclass 35, count 0 2006.201.10:25:53.55#ibcon#about to read 6, iclass 35, count 0 2006.201.10:25:53.55#ibcon#read 6, iclass 35, count 0 2006.201.10:25:53.55#ibcon#end of sib2, iclass 35, count 0 2006.201.10:25:53.55#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:25:53.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:25:53.55#ibcon#[25=USB\r\n] 2006.201.10:25:53.55#ibcon#*before write, iclass 35, count 0 2006.201.10:25:53.55#ibcon#enter sib2, iclass 35, count 0 2006.201.10:25:53.55#ibcon#flushed, iclass 35, count 0 2006.201.10:25:53.55#ibcon#about to write, iclass 35, count 0 2006.201.10:25:53.55#ibcon#wrote, iclass 35, count 0 2006.201.10:25:53.55#ibcon#about to read 3, iclass 35, count 0 2006.201.10:25:53.58#ibcon#read 3, iclass 35, count 0 2006.201.10:25:53.58#ibcon#about to read 4, iclass 35, count 0 2006.201.10:25:53.58#ibcon#read 4, iclass 35, count 0 2006.201.10:25:53.58#ibcon#about to read 5, iclass 35, count 0 2006.201.10:25:53.58#ibcon#read 5, iclass 35, count 0 2006.201.10:25:53.58#ibcon#about to read 6, iclass 35, count 0 2006.201.10:25:53.58#ibcon#read 6, iclass 35, count 0 2006.201.10:25:53.58#ibcon#end of sib2, iclass 35, count 0 2006.201.10:25:53.58#ibcon#*after write, iclass 35, count 0 2006.201.10:25:53.58#ibcon#*before return 0, iclass 35, count 0 2006.201.10:25:53.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:53.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:53.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:25:53.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:25:53.58$vck44/vblo=1,629.99 2006.201.10:25:53.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.10:25:53.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.10:25:53.58#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:53.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:53.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:53.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:53.58#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:25:53.58#ibcon#first serial, iclass 37, count 0 2006.201.10:25:53.58#ibcon#enter sib2, iclass 37, count 0 2006.201.10:25:53.58#ibcon#flushed, iclass 37, count 0 2006.201.10:25:53.58#ibcon#about to write, iclass 37, count 0 2006.201.10:25:53.58#ibcon#wrote, iclass 37, count 0 2006.201.10:25:53.58#ibcon#about to read 3, iclass 37, count 0 2006.201.10:25:53.60#ibcon#read 3, iclass 37, count 0 2006.201.10:25:53.60#ibcon#about to read 4, iclass 37, count 0 2006.201.10:25:53.60#ibcon#read 4, iclass 37, count 0 2006.201.10:25:53.60#ibcon#about to read 5, iclass 37, count 0 2006.201.10:25:53.60#ibcon#read 5, iclass 37, count 0 2006.201.10:25:53.60#ibcon#about to read 6, iclass 37, count 0 2006.201.10:25:53.60#ibcon#read 6, iclass 37, count 0 2006.201.10:25:53.60#ibcon#end of sib2, iclass 37, count 0 2006.201.10:25:53.60#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:25:53.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:25:53.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:25:53.60#ibcon#*before write, iclass 37, count 0 2006.201.10:25:53.60#ibcon#enter sib2, iclass 37, count 0 2006.201.10:25:53.60#ibcon#flushed, iclass 37, count 0 2006.201.10:25:53.60#ibcon#about to write, iclass 37, count 0 2006.201.10:25:53.60#ibcon#wrote, iclass 37, count 0 2006.201.10:25:53.60#ibcon#about to read 3, iclass 37, count 0 2006.201.10:25:53.65#ibcon#read 3, iclass 37, count 0 2006.201.10:25:53.65#ibcon#about to read 4, iclass 37, count 0 2006.201.10:25:53.65#ibcon#read 4, iclass 37, count 0 2006.201.10:25:53.65#ibcon#about to read 5, iclass 37, count 0 2006.201.10:25:53.65#ibcon#read 5, iclass 37, count 0 2006.201.10:25:53.65#ibcon#about to read 6, iclass 37, count 0 2006.201.10:25:53.65#ibcon#read 6, iclass 37, count 0 2006.201.10:25:53.65#ibcon#end of sib2, iclass 37, count 0 2006.201.10:25:53.65#ibcon#*after write, iclass 37, count 0 2006.201.10:25:53.65#ibcon#*before return 0, iclass 37, count 0 2006.201.10:25:53.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:53.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:53.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:25:53.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:25:53.65$vck44/vb=1,4 2006.201.10:25:53.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.10:25:53.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.10:25:53.65#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:53.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:25:53.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:25:53.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:25:53.65#ibcon#enter wrdev, iclass 39, count 2 2006.201.10:25:53.65#ibcon#first serial, iclass 39, count 2 2006.201.10:25:53.65#ibcon#enter sib2, iclass 39, count 2 2006.201.10:25:53.65#ibcon#flushed, iclass 39, count 2 2006.201.10:25:53.65#ibcon#about to write, iclass 39, count 2 2006.201.10:25:53.65#ibcon#wrote, iclass 39, count 2 2006.201.10:25:53.65#ibcon#about to read 3, iclass 39, count 2 2006.201.10:25:53.67#ibcon#read 3, iclass 39, count 2 2006.201.10:25:53.67#ibcon#about to read 4, iclass 39, count 2 2006.201.10:25:53.67#ibcon#read 4, iclass 39, count 2 2006.201.10:25:53.67#ibcon#about to read 5, iclass 39, count 2 2006.201.10:25:53.67#ibcon#read 5, iclass 39, count 2 2006.201.10:25:53.67#ibcon#about to read 6, iclass 39, count 2 2006.201.10:25:53.67#ibcon#read 6, iclass 39, count 2 2006.201.10:25:53.67#ibcon#end of sib2, iclass 39, count 2 2006.201.10:25:53.67#ibcon#*mode == 0, iclass 39, count 2 2006.201.10:25:53.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.10:25:53.67#ibcon#[27=AT01-04\r\n] 2006.201.10:25:53.67#ibcon#*before write, iclass 39, count 2 2006.201.10:25:53.67#ibcon#enter sib2, iclass 39, count 2 2006.201.10:25:53.67#ibcon#flushed, iclass 39, count 2 2006.201.10:25:53.67#ibcon#about to write, iclass 39, count 2 2006.201.10:25:53.67#ibcon#wrote, iclass 39, count 2 2006.201.10:25:53.67#ibcon#about to read 3, iclass 39, count 2 2006.201.10:25:53.70#ibcon#read 3, iclass 39, count 2 2006.201.10:25:53.70#ibcon#about to read 4, iclass 39, count 2 2006.201.10:25:53.70#ibcon#read 4, iclass 39, count 2 2006.201.10:25:53.70#ibcon#about to read 5, iclass 39, count 2 2006.201.10:25:53.70#ibcon#read 5, iclass 39, count 2 2006.201.10:25:53.70#ibcon#about to read 6, iclass 39, count 2 2006.201.10:25:53.70#ibcon#read 6, iclass 39, count 2 2006.201.10:25:53.70#ibcon#end of sib2, iclass 39, count 2 2006.201.10:25:53.70#ibcon#*after write, iclass 39, count 2 2006.201.10:25:53.70#ibcon#*before return 0, iclass 39, count 2 2006.201.10:25:53.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:25:53.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:25:53.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.10:25:53.70#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:53.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:25:53.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:25:53.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:25:53.82#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:25:53.82#ibcon#first serial, iclass 39, count 0 2006.201.10:25:53.82#ibcon#enter sib2, iclass 39, count 0 2006.201.10:25:53.82#ibcon#flushed, iclass 39, count 0 2006.201.10:25:53.82#ibcon#about to write, iclass 39, count 0 2006.201.10:25:53.82#ibcon#wrote, iclass 39, count 0 2006.201.10:25:53.82#ibcon#about to read 3, iclass 39, count 0 2006.201.10:25:53.84#ibcon#read 3, iclass 39, count 0 2006.201.10:25:53.84#ibcon#about to read 4, iclass 39, count 0 2006.201.10:25:53.84#ibcon#read 4, iclass 39, count 0 2006.201.10:25:53.84#ibcon#about to read 5, iclass 39, count 0 2006.201.10:25:53.84#ibcon#read 5, iclass 39, count 0 2006.201.10:25:53.84#ibcon#about to read 6, iclass 39, count 0 2006.201.10:25:53.84#ibcon#read 6, iclass 39, count 0 2006.201.10:25:53.84#ibcon#end of sib2, iclass 39, count 0 2006.201.10:25:53.84#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:25:53.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:25:53.84#ibcon#[27=USB\r\n] 2006.201.10:25:53.84#ibcon#*before write, iclass 39, count 0 2006.201.10:25:53.84#ibcon#enter sib2, iclass 39, count 0 2006.201.10:25:53.84#ibcon#flushed, iclass 39, count 0 2006.201.10:25:53.84#ibcon#about to write, iclass 39, count 0 2006.201.10:25:53.84#ibcon#wrote, iclass 39, count 0 2006.201.10:25:53.84#ibcon#about to read 3, iclass 39, count 0 2006.201.10:25:53.87#abcon#<5=/05 2.4 4.2 21.78 961003.5\r\n> 2006.201.10:25:53.87#ibcon#read 3, iclass 39, count 0 2006.201.10:25:53.87#ibcon#about to read 4, iclass 39, count 0 2006.201.10:25:53.87#ibcon#read 4, iclass 39, count 0 2006.201.10:25:53.87#ibcon#about to read 5, iclass 39, count 0 2006.201.10:25:53.87#ibcon#read 5, iclass 39, count 0 2006.201.10:25:53.87#ibcon#about to read 6, iclass 39, count 0 2006.201.10:25:53.87#ibcon#read 6, iclass 39, count 0 2006.201.10:25:53.87#ibcon#end of sib2, iclass 39, count 0 2006.201.10:25:53.87#ibcon#*after write, iclass 39, count 0 2006.201.10:25:53.87#ibcon#*before return 0, iclass 39, count 0 2006.201.10:25:53.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:25:53.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:25:53.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:25:53.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:25:53.87$vck44/vblo=2,634.99 2006.201.10:25:53.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.10:25:53.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.10:25:53.87#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:53.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:25:53.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:25:53.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:25:53.87#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:25:53.87#ibcon#first serial, iclass 6, count 0 2006.201.10:25:53.87#ibcon#enter sib2, iclass 6, count 0 2006.201.10:25:53.87#ibcon#flushed, iclass 6, count 0 2006.201.10:25:53.87#ibcon#about to write, iclass 6, count 0 2006.201.10:25:53.87#ibcon#wrote, iclass 6, count 0 2006.201.10:25:53.87#ibcon#about to read 3, iclass 6, count 0 2006.201.10:25:53.89#abcon#{5=INTERFACE CLEAR} 2006.201.10:25:53.89#ibcon#read 3, iclass 6, count 0 2006.201.10:25:53.89#ibcon#about to read 4, iclass 6, count 0 2006.201.10:25:53.89#ibcon#read 4, iclass 6, count 0 2006.201.10:25:53.89#ibcon#about to read 5, iclass 6, count 0 2006.201.10:25:53.89#ibcon#read 5, iclass 6, count 0 2006.201.10:25:53.89#ibcon#about to read 6, iclass 6, count 0 2006.201.10:25:53.89#ibcon#read 6, iclass 6, count 0 2006.201.10:25:53.89#ibcon#end of sib2, iclass 6, count 0 2006.201.10:25:53.89#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:25:53.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:25:53.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:25:53.89#ibcon#*before write, iclass 6, count 0 2006.201.10:25:53.89#ibcon#enter sib2, iclass 6, count 0 2006.201.10:25:53.89#ibcon#flushed, iclass 6, count 0 2006.201.10:25:53.89#ibcon#about to write, iclass 6, count 0 2006.201.10:25:53.89#ibcon#wrote, iclass 6, count 0 2006.201.10:25:53.89#ibcon#about to read 3, iclass 6, count 0 2006.201.10:25:53.93#ibcon#read 3, iclass 6, count 0 2006.201.10:25:53.93#ibcon#about to read 4, iclass 6, count 0 2006.201.10:25:53.93#ibcon#read 4, iclass 6, count 0 2006.201.10:25:53.93#ibcon#about to read 5, iclass 6, count 0 2006.201.10:25:53.93#ibcon#read 5, iclass 6, count 0 2006.201.10:25:53.93#ibcon#about to read 6, iclass 6, count 0 2006.201.10:25:53.93#ibcon#read 6, iclass 6, count 0 2006.201.10:25:53.93#ibcon#end of sib2, iclass 6, count 0 2006.201.10:25:53.93#ibcon#*after write, iclass 6, count 0 2006.201.10:25:53.93#ibcon#*before return 0, iclass 6, count 0 2006.201.10:25:53.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:25:53.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:25:53.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:25:53.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:25:53.93$vck44/vb=2,5 2006.201.10:25:53.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.10:25:53.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.10:25:53.93#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:53.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:25:53.95#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:25:53.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:25:53.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:25:53.99#ibcon#enter wrdev, iclass 10, count 2 2006.201.10:25:53.99#ibcon#first serial, iclass 10, count 2 2006.201.10:25:53.99#ibcon#enter sib2, iclass 10, count 2 2006.201.10:25:53.99#ibcon#flushed, iclass 10, count 2 2006.201.10:25:53.99#ibcon#about to write, iclass 10, count 2 2006.201.10:25:53.99#ibcon#wrote, iclass 10, count 2 2006.201.10:25:53.99#ibcon#about to read 3, iclass 10, count 2 2006.201.10:25:54.01#ibcon#read 3, iclass 10, count 2 2006.201.10:25:54.01#ibcon#about to read 4, iclass 10, count 2 2006.201.10:25:54.01#ibcon#read 4, iclass 10, count 2 2006.201.10:25:54.01#ibcon#about to read 5, iclass 10, count 2 2006.201.10:25:54.01#ibcon#read 5, iclass 10, count 2 2006.201.10:25:54.01#ibcon#about to read 6, iclass 10, count 2 2006.201.10:25:54.01#ibcon#read 6, iclass 10, count 2 2006.201.10:25:54.01#ibcon#end of sib2, iclass 10, count 2 2006.201.10:25:54.01#ibcon#*mode == 0, iclass 10, count 2 2006.201.10:25:54.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.10:25:54.01#ibcon#[27=AT02-05\r\n] 2006.201.10:25:54.01#ibcon#*before write, iclass 10, count 2 2006.201.10:25:54.01#ibcon#enter sib2, iclass 10, count 2 2006.201.10:25:54.01#ibcon#flushed, iclass 10, count 2 2006.201.10:25:54.01#ibcon#about to write, iclass 10, count 2 2006.201.10:25:54.01#ibcon#wrote, iclass 10, count 2 2006.201.10:25:54.01#ibcon#about to read 3, iclass 10, count 2 2006.201.10:25:54.04#ibcon#read 3, iclass 10, count 2 2006.201.10:25:54.04#ibcon#about to read 4, iclass 10, count 2 2006.201.10:25:54.04#ibcon#read 4, iclass 10, count 2 2006.201.10:25:54.04#ibcon#about to read 5, iclass 10, count 2 2006.201.10:25:54.04#ibcon#read 5, iclass 10, count 2 2006.201.10:25:54.04#ibcon#about to read 6, iclass 10, count 2 2006.201.10:25:54.04#ibcon#read 6, iclass 10, count 2 2006.201.10:25:54.04#ibcon#end of sib2, iclass 10, count 2 2006.201.10:25:54.04#ibcon#*after write, iclass 10, count 2 2006.201.10:25:54.04#ibcon#*before return 0, iclass 10, count 2 2006.201.10:25:54.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:25:54.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:25:54.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.10:25:54.04#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:54.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:25:54.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:25:54.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:25:54.16#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:25:54.16#ibcon#first serial, iclass 10, count 0 2006.201.10:25:54.16#ibcon#enter sib2, iclass 10, count 0 2006.201.10:25:54.16#ibcon#flushed, iclass 10, count 0 2006.201.10:25:54.16#ibcon#about to write, iclass 10, count 0 2006.201.10:25:54.16#ibcon#wrote, iclass 10, count 0 2006.201.10:25:54.16#ibcon#about to read 3, iclass 10, count 0 2006.201.10:25:54.18#ibcon#read 3, iclass 10, count 0 2006.201.10:25:54.18#ibcon#about to read 4, iclass 10, count 0 2006.201.10:25:54.18#ibcon#read 4, iclass 10, count 0 2006.201.10:25:54.18#ibcon#about to read 5, iclass 10, count 0 2006.201.10:25:54.18#ibcon#read 5, iclass 10, count 0 2006.201.10:25:54.18#ibcon#about to read 6, iclass 10, count 0 2006.201.10:25:54.18#ibcon#read 6, iclass 10, count 0 2006.201.10:25:54.18#ibcon#end of sib2, iclass 10, count 0 2006.201.10:25:54.18#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:25:54.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:25:54.18#ibcon#[27=USB\r\n] 2006.201.10:25:54.18#ibcon#*before write, iclass 10, count 0 2006.201.10:25:54.18#ibcon#enter sib2, iclass 10, count 0 2006.201.10:25:54.18#ibcon#flushed, iclass 10, count 0 2006.201.10:25:54.18#ibcon#about to write, iclass 10, count 0 2006.201.10:25:54.18#ibcon#wrote, iclass 10, count 0 2006.201.10:25:54.18#ibcon#about to read 3, iclass 10, count 0 2006.201.10:25:54.21#ibcon#read 3, iclass 10, count 0 2006.201.10:25:54.21#ibcon#about to read 4, iclass 10, count 0 2006.201.10:25:54.21#ibcon#read 4, iclass 10, count 0 2006.201.10:25:54.21#ibcon#about to read 5, iclass 10, count 0 2006.201.10:25:54.21#ibcon#read 5, iclass 10, count 0 2006.201.10:25:54.21#ibcon#about to read 6, iclass 10, count 0 2006.201.10:25:54.21#ibcon#read 6, iclass 10, count 0 2006.201.10:25:54.21#ibcon#end of sib2, iclass 10, count 0 2006.201.10:25:54.21#ibcon#*after write, iclass 10, count 0 2006.201.10:25:54.21#ibcon#*before return 0, iclass 10, count 0 2006.201.10:25:54.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:25:54.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:25:54.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:25:54.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:25:54.21$vck44/vblo=3,649.99 2006.201.10:25:54.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.10:25:54.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.10:25:54.21#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:54.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:54.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:54.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:54.21#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:25:54.21#ibcon#first serial, iclass 13, count 0 2006.201.10:25:54.21#ibcon#enter sib2, iclass 13, count 0 2006.201.10:25:54.21#ibcon#flushed, iclass 13, count 0 2006.201.10:25:54.21#ibcon#about to write, iclass 13, count 0 2006.201.10:25:54.21#ibcon#wrote, iclass 13, count 0 2006.201.10:25:54.21#ibcon#about to read 3, iclass 13, count 0 2006.201.10:25:54.23#ibcon#read 3, iclass 13, count 0 2006.201.10:25:54.23#ibcon#about to read 4, iclass 13, count 0 2006.201.10:25:54.23#ibcon#read 4, iclass 13, count 0 2006.201.10:25:54.23#ibcon#about to read 5, iclass 13, count 0 2006.201.10:25:54.23#ibcon#read 5, iclass 13, count 0 2006.201.10:25:54.23#ibcon#about to read 6, iclass 13, count 0 2006.201.10:25:54.23#ibcon#read 6, iclass 13, count 0 2006.201.10:25:54.23#ibcon#end of sib2, iclass 13, count 0 2006.201.10:25:54.23#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:25:54.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:25:54.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:25:54.23#ibcon#*before write, iclass 13, count 0 2006.201.10:25:54.23#ibcon#enter sib2, iclass 13, count 0 2006.201.10:25:54.23#ibcon#flushed, iclass 13, count 0 2006.201.10:25:54.23#ibcon#about to write, iclass 13, count 0 2006.201.10:25:54.23#ibcon#wrote, iclass 13, count 0 2006.201.10:25:54.23#ibcon#about to read 3, iclass 13, count 0 2006.201.10:25:54.27#ibcon#read 3, iclass 13, count 0 2006.201.10:25:54.27#ibcon#about to read 4, iclass 13, count 0 2006.201.10:25:54.27#ibcon#read 4, iclass 13, count 0 2006.201.10:25:54.27#ibcon#about to read 5, iclass 13, count 0 2006.201.10:25:54.27#ibcon#read 5, iclass 13, count 0 2006.201.10:25:54.27#ibcon#about to read 6, iclass 13, count 0 2006.201.10:25:54.27#ibcon#read 6, iclass 13, count 0 2006.201.10:25:54.27#ibcon#end of sib2, iclass 13, count 0 2006.201.10:25:54.27#ibcon#*after write, iclass 13, count 0 2006.201.10:25:54.27#ibcon#*before return 0, iclass 13, count 0 2006.201.10:25:54.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:54.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:25:54.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:25:54.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:25:54.27$vck44/vb=3,4 2006.201.10:25:54.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.10:25:54.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.10:25:54.27#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:54.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:54.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:54.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:54.33#ibcon#enter wrdev, iclass 15, count 2 2006.201.10:25:54.33#ibcon#first serial, iclass 15, count 2 2006.201.10:25:54.33#ibcon#enter sib2, iclass 15, count 2 2006.201.10:25:54.33#ibcon#flushed, iclass 15, count 2 2006.201.10:25:54.33#ibcon#about to write, iclass 15, count 2 2006.201.10:25:54.33#ibcon#wrote, iclass 15, count 2 2006.201.10:25:54.33#ibcon#about to read 3, iclass 15, count 2 2006.201.10:25:54.35#ibcon#read 3, iclass 15, count 2 2006.201.10:25:54.35#ibcon#about to read 4, iclass 15, count 2 2006.201.10:25:54.35#ibcon#read 4, iclass 15, count 2 2006.201.10:25:54.35#ibcon#about to read 5, iclass 15, count 2 2006.201.10:25:54.35#ibcon#read 5, iclass 15, count 2 2006.201.10:25:54.35#ibcon#about to read 6, iclass 15, count 2 2006.201.10:25:54.35#ibcon#read 6, iclass 15, count 2 2006.201.10:25:54.35#ibcon#end of sib2, iclass 15, count 2 2006.201.10:25:54.35#ibcon#*mode == 0, iclass 15, count 2 2006.201.10:25:54.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.10:25:54.35#ibcon#[27=AT03-04\r\n] 2006.201.10:25:54.35#ibcon#*before write, iclass 15, count 2 2006.201.10:25:54.35#ibcon#enter sib2, iclass 15, count 2 2006.201.10:25:54.35#ibcon#flushed, iclass 15, count 2 2006.201.10:25:54.35#ibcon#about to write, iclass 15, count 2 2006.201.10:25:54.35#ibcon#wrote, iclass 15, count 2 2006.201.10:25:54.35#ibcon#about to read 3, iclass 15, count 2 2006.201.10:25:54.38#ibcon#read 3, iclass 15, count 2 2006.201.10:25:54.38#ibcon#about to read 4, iclass 15, count 2 2006.201.10:25:54.38#ibcon#read 4, iclass 15, count 2 2006.201.10:25:54.38#ibcon#about to read 5, iclass 15, count 2 2006.201.10:25:54.38#ibcon#read 5, iclass 15, count 2 2006.201.10:25:54.38#ibcon#about to read 6, iclass 15, count 2 2006.201.10:25:54.38#ibcon#read 6, iclass 15, count 2 2006.201.10:25:54.38#ibcon#end of sib2, iclass 15, count 2 2006.201.10:25:54.38#ibcon#*after write, iclass 15, count 2 2006.201.10:25:54.38#ibcon#*before return 0, iclass 15, count 2 2006.201.10:25:54.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:54.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:25:54.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.10:25:54.38#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:54.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:54.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:54.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:54.50#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:25:54.50#ibcon#first serial, iclass 15, count 0 2006.201.10:25:54.50#ibcon#enter sib2, iclass 15, count 0 2006.201.10:25:54.50#ibcon#flushed, iclass 15, count 0 2006.201.10:25:54.50#ibcon#about to write, iclass 15, count 0 2006.201.10:25:54.50#ibcon#wrote, iclass 15, count 0 2006.201.10:25:54.50#ibcon#about to read 3, iclass 15, count 0 2006.201.10:25:54.52#ibcon#read 3, iclass 15, count 0 2006.201.10:25:54.52#ibcon#about to read 4, iclass 15, count 0 2006.201.10:25:54.52#ibcon#read 4, iclass 15, count 0 2006.201.10:25:54.52#ibcon#about to read 5, iclass 15, count 0 2006.201.10:25:54.52#ibcon#read 5, iclass 15, count 0 2006.201.10:25:54.52#ibcon#about to read 6, iclass 15, count 0 2006.201.10:25:54.52#ibcon#read 6, iclass 15, count 0 2006.201.10:25:54.52#ibcon#end of sib2, iclass 15, count 0 2006.201.10:25:54.52#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:25:54.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:25:54.52#ibcon#[27=USB\r\n] 2006.201.10:25:54.52#ibcon#*before write, iclass 15, count 0 2006.201.10:25:54.52#ibcon#enter sib2, iclass 15, count 0 2006.201.10:25:54.52#ibcon#flushed, iclass 15, count 0 2006.201.10:25:54.52#ibcon#about to write, iclass 15, count 0 2006.201.10:25:54.52#ibcon#wrote, iclass 15, count 0 2006.201.10:25:54.52#ibcon#about to read 3, iclass 15, count 0 2006.201.10:25:54.55#ibcon#read 3, iclass 15, count 0 2006.201.10:25:54.55#ibcon#about to read 4, iclass 15, count 0 2006.201.10:25:54.55#ibcon#read 4, iclass 15, count 0 2006.201.10:25:54.55#ibcon#about to read 5, iclass 15, count 0 2006.201.10:25:54.55#ibcon#read 5, iclass 15, count 0 2006.201.10:25:54.55#ibcon#about to read 6, iclass 15, count 0 2006.201.10:25:54.55#ibcon#read 6, iclass 15, count 0 2006.201.10:25:54.55#ibcon#end of sib2, iclass 15, count 0 2006.201.10:25:54.55#ibcon#*after write, iclass 15, count 0 2006.201.10:25:54.55#ibcon#*before return 0, iclass 15, count 0 2006.201.10:25:54.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:54.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:25:54.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:25:54.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:25:54.55$vck44/vblo=4,679.99 2006.201.10:25:54.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.10:25:54.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.10:25:54.55#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:54.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:54.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:54.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:54.55#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:25:54.55#ibcon#first serial, iclass 17, count 0 2006.201.10:25:54.55#ibcon#enter sib2, iclass 17, count 0 2006.201.10:25:54.55#ibcon#flushed, iclass 17, count 0 2006.201.10:25:54.55#ibcon#about to write, iclass 17, count 0 2006.201.10:25:54.55#ibcon#wrote, iclass 17, count 0 2006.201.10:25:54.55#ibcon#about to read 3, iclass 17, count 0 2006.201.10:25:54.57#ibcon#read 3, iclass 17, count 0 2006.201.10:25:54.57#ibcon#about to read 4, iclass 17, count 0 2006.201.10:25:54.57#ibcon#read 4, iclass 17, count 0 2006.201.10:25:54.57#ibcon#about to read 5, iclass 17, count 0 2006.201.10:25:54.57#ibcon#read 5, iclass 17, count 0 2006.201.10:25:54.57#ibcon#about to read 6, iclass 17, count 0 2006.201.10:25:54.57#ibcon#read 6, iclass 17, count 0 2006.201.10:25:54.57#ibcon#end of sib2, iclass 17, count 0 2006.201.10:25:54.57#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:25:54.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:25:54.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:25:54.57#ibcon#*before write, iclass 17, count 0 2006.201.10:25:54.57#ibcon#enter sib2, iclass 17, count 0 2006.201.10:25:54.57#ibcon#flushed, iclass 17, count 0 2006.201.10:25:54.57#ibcon#about to write, iclass 17, count 0 2006.201.10:25:54.57#ibcon#wrote, iclass 17, count 0 2006.201.10:25:54.57#ibcon#about to read 3, iclass 17, count 0 2006.201.10:25:54.62#ibcon#read 3, iclass 17, count 0 2006.201.10:25:54.62#ibcon#about to read 4, iclass 17, count 0 2006.201.10:25:54.62#ibcon#read 4, iclass 17, count 0 2006.201.10:25:54.62#ibcon#about to read 5, iclass 17, count 0 2006.201.10:25:54.62#ibcon#read 5, iclass 17, count 0 2006.201.10:25:54.62#ibcon#about to read 6, iclass 17, count 0 2006.201.10:25:54.62#ibcon#read 6, iclass 17, count 0 2006.201.10:25:54.62#ibcon#end of sib2, iclass 17, count 0 2006.201.10:25:54.62#ibcon#*after write, iclass 17, count 0 2006.201.10:25:54.62#ibcon#*before return 0, iclass 17, count 0 2006.201.10:25:54.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:54.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:25:54.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:25:54.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:25:54.62$vck44/vb=4,5 2006.201.10:25:54.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.10:25:54.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.10:25:54.62#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:54.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:54.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:54.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:54.67#ibcon#enter wrdev, iclass 19, count 2 2006.201.10:25:54.67#ibcon#first serial, iclass 19, count 2 2006.201.10:25:54.67#ibcon#enter sib2, iclass 19, count 2 2006.201.10:25:54.67#ibcon#flushed, iclass 19, count 2 2006.201.10:25:54.67#ibcon#about to write, iclass 19, count 2 2006.201.10:25:54.67#ibcon#wrote, iclass 19, count 2 2006.201.10:25:54.67#ibcon#about to read 3, iclass 19, count 2 2006.201.10:25:54.69#ibcon#read 3, iclass 19, count 2 2006.201.10:25:54.69#ibcon#about to read 4, iclass 19, count 2 2006.201.10:25:54.69#ibcon#read 4, iclass 19, count 2 2006.201.10:25:54.69#ibcon#about to read 5, iclass 19, count 2 2006.201.10:25:54.69#ibcon#read 5, iclass 19, count 2 2006.201.10:25:54.69#ibcon#about to read 6, iclass 19, count 2 2006.201.10:25:54.69#ibcon#read 6, iclass 19, count 2 2006.201.10:25:54.69#ibcon#end of sib2, iclass 19, count 2 2006.201.10:25:54.69#ibcon#*mode == 0, iclass 19, count 2 2006.201.10:25:54.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.10:25:54.69#ibcon#[27=AT04-05\r\n] 2006.201.10:25:54.69#ibcon#*before write, iclass 19, count 2 2006.201.10:25:54.69#ibcon#enter sib2, iclass 19, count 2 2006.201.10:25:54.69#ibcon#flushed, iclass 19, count 2 2006.201.10:25:54.69#ibcon#about to write, iclass 19, count 2 2006.201.10:25:54.69#ibcon#wrote, iclass 19, count 2 2006.201.10:25:54.69#ibcon#about to read 3, iclass 19, count 2 2006.201.10:25:54.72#ibcon#read 3, iclass 19, count 2 2006.201.10:25:54.72#ibcon#about to read 4, iclass 19, count 2 2006.201.10:25:54.72#ibcon#read 4, iclass 19, count 2 2006.201.10:25:54.72#ibcon#about to read 5, iclass 19, count 2 2006.201.10:25:54.72#ibcon#read 5, iclass 19, count 2 2006.201.10:25:54.72#ibcon#about to read 6, iclass 19, count 2 2006.201.10:25:54.72#ibcon#read 6, iclass 19, count 2 2006.201.10:25:54.72#ibcon#end of sib2, iclass 19, count 2 2006.201.10:25:54.72#ibcon#*after write, iclass 19, count 2 2006.201.10:25:54.72#ibcon#*before return 0, iclass 19, count 2 2006.201.10:25:54.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:54.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:25:54.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.10:25:54.72#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:54.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:54.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:54.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:54.84#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:25:54.84#ibcon#first serial, iclass 19, count 0 2006.201.10:25:54.84#ibcon#enter sib2, iclass 19, count 0 2006.201.10:25:54.84#ibcon#flushed, iclass 19, count 0 2006.201.10:25:54.84#ibcon#about to write, iclass 19, count 0 2006.201.10:25:54.84#ibcon#wrote, iclass 19, count 0 2006.201.10:25:54.84#ibcon#about to read 3, iclass 19, count 0 2006.201.10:25:54.86#ibcon#read 3, iclass 19, count 0 2006.201.10:25:54.86#ibcon#about to read 4, iclass 19, count 0 2006.201.10:25:54.86#ibcon#read 4, iclass 19, count 0 2006.201.10:25:54.86#ibcon#about to read 5, iclass 19, count 0 2006.201.10:25:54.86#ibcon#read 5, iclass 19, count 0 2006.201.10:25:54.86#ibcon#about to read 6, iclass 19, count 0 2006.201.10:25:54.86#ibcon#read 6, iclass 19, count 0 2006.201.10:25:54.86#ibcon#end of sib2, iclass 19, count 0 2006.201.10:25:54.86#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:25:54.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:25:54.86#ibcon#[27=USB\r\n] 2006.201.10:25:54.86#ibcon#*before write, iclass 19, count 0 2006.201.10:25:54.86#ibcon#enter sib2, iclass 19, count 0 2006.201.10:25:54.86#ibcon#flushed, iclass 19, count 0 2006.201.10:25:54.86#ibcon#about to write, iclass 19, count 0 2006.201.10:25:54.86#ibcon#wrote, iclass 19, count 0 2006.201.10:25:54.86#ibcon#about to read 3, iclass 19, count 0 2006.201.10:25:54.89#ibcon#read 3, iclass 19, count 0 2006.201.10:25:54.89#ibcon#about to read 4, iclass 19, count 0 2006.201.10:25:54.89#ibcon#read 4, iclass 19, count 0 2006.201.10:25:54.89#ibcon#about to read 5, iclass 19, count 0 2006.201.10:25:54.89#ibcon#read 5, iclass 19, count 0 2006.201.10:25:54.89#ibcon#about to read 6, iclass 19, count 0 2006.201.10:25:54.89#ibcon#read 6, iclass 19, count 0 2006.201.10:25:54.89#ibcon#end of sib2, iclass 19, count 0 2006.201.10:25:54.89#ibcon#*after write, iclass 19, count 0 2006.201.10:25:54.89#ibcon#*before return 0, iclass 19, count 0 2006.201.10:25:54.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:54.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:25:54.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:25:54.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:25:54.89$vck44/vblo=5,709.99 2006.201.10:25:54.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.10:25:54.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.10:25:54.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:54.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:54.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:54.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:54.89#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:25:54.89#ibcon#first serial, iclass 21, count 0 2006.201.10:25:54.89#ibcon#enter sib2, iclass 21, count 0 2006.201.10:25:54.89#ibcon#flushed, iclass 21, count 0 2006.201.10:25:54.89#ibcon#about to write, iclass 21, count 0 2006.201.10:25:54.89#ibcon#wrote, iclass 21, count 0 2006.201.10:25:54.89#ibcon#about to read 3, iclass 21, count 0 2006.201.10:25:54.91#ibcon#read 3, iclass 21, count 0 2006.201.10:25:54.91#ibcon#about to read 4, iclass 21, count 0 2006.201.10:25:54.91#ibcon#read 4, iclass 21, count 0 2006.201.10:25:54.91#ibcon#about to read 5, iclass 21, count 0 2006.201.10:25:54.91#ibcon#read 5, iclass 21, count 0 2006.201.10:25:54.91#ibcon#about to read 6, iclass 21, count 0 2006.201.10:25:54.91#ibcon#read 6, iclass 21, count 0 2006.201.10:25:54.91#ibcon#end of sib2, iclass 21, count 0 2006.201.10:25:54.91#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:25:54.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:25:54.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:25:54.91#ibcon#*before write, iclass 21, count 0 2006.201.10:25:54.91#ibcon#enter sib2, iclass 21, count 0 2006.201.10:25:54.91#ibcon#flushed, iclass 21, count 0 2006.201.10:25:54.91#ibcon#about to write, iclass 21, count 0 2006.201.10:25:54.91#ibcon#wrote, iclass 21, count 0 2006.201.10:25:54.91#ibcon#about to read 3, iclass 21, count 0 2006.201.10:25:54.95#ibcon#read 3, iclass 21, count 0 2006.201.10:25:54.95#ibcon#about to read 4, iclass 21, count 0 2006.201.10:25:54.95#ibcon#read 4, iclass 21, count 0 2006.201.10:25:54.95#ibcon#about to read 5, iclass 21, count 0 2006.201.10:25:54.95#ibcon#read 5, iclass 21, count 0 2006.201.10:25:54.95#ibcon#about to read 6, iclass 21, count 0 2006.201.10:25:54.95#ibcon#read 6, iclass 21, count 0 2006.201.10:25:54.95#ibcon#end of sib2, iclass 21, count 0 2006.201.10:25:54.95#ibcon#*after write, iclass 21, count 0 2006.201.10:25:54.95#ibcon#*before return 0, iclass 21, count 0 2006.201.10:25:54.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:54.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:25:54.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:25:54.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:25:54.95$vck44/vb=5,4 2006.201.10:25:54.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.10:25:54.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.10:25:54.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:54.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:55.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:55.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:55.01#ibcon#enter wrdev, iclass 23, count 2 2006.201.10:25:55.01#ibcon#first serial, iclass 23, count 2 2006.201.10:25:55.01#ibcon#enter sib2, iclass 23, count 2 2006.201.10:25:55.01#ibcon#flushed, iclass 23, count 2 2006.201.10:25:55.01#ibcon#about to write, iclass 23, count 2 2006.201.10:25:55.01#ibcon#wrote, iclass 23, count 2 2006.201.10:25:55.01#ibcon#about to read 3, iclass 23, count 2 2006.201.10:25:55.03#ibcon#read 3, iclass 23, count 2 2006.201.10:25:55.03#ibcon#about to read 4, iclass 23, count 2 2006.201.10:25:55.03#ibcon#read 4, iclass 23, count 2 2006.201.10:25:55.03#ibcon#about to read 5, iclass 23, count 2 2006.201.10:25:55.03#ibcon#read 5, iclass 23, count 2 2006.201.10:25:55.03#ibcon#about to read 6, iclass 23, count 2 2006.201.10:25:55.03#ibcon#read 6, iclass 23, count 2 2006.201.10:25:55.03#ibcon#end of sib2, iclass 23, count 2 2006.201.10:25:55.03#ibcon#*mode == 0, iclass 23, count 2 2006.201.10:25:55.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.10:25:55.03#ibcon#[27=AT05-04\r\n] 2006.201.10:25:55.03#ibcon#*before write, iclass 23, count 2 2006.201.10:25:55.03#ibcon#enter sib2, iclass 23, count 2 2006.201.10:25:55.03#ibcon#flushed, iclass 23, count 2 2006.201.10:25:55.03#ibcon#about to write, iclass 23, count 2 2006.201.10:25:55.03#ibcon#wrote, iclass 23, count 2 2006.201.10:25:55.03#ibcon#about to read 3, iclass 23, count 2 2006.201.10:25:55.06#ibcon#read 3, iclass 23, count 2 2006.201.10:25:55.06#ibcon#about to read 4, iclass 23, count 2 2006.201.10:25:55.06#ibcon#read 4, iclass 23, count 2 2006.201.10:25:55.06#ibcon#about to read 5, iclass 23, count 2 2006.201.10:25:55.06#ibcon#read 5, iclass 23, count 2 2006.201.10:25:55.06#ibcon#about to read 6, iclass 23, count 2 2006.201.10:25:55.06#ibcon#read 6, iclass 23, count 2 2006.201.10:25:55.06#ibcon#end of sib2, iclass 23, count 2 2006.201.10:25:55.06#ibcon#*after write, iclass 23, count 2 2006.201.10:25:55.06#ibcon#*before return 0, iclass 23, count 2 2006.201.10:25:55.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:55.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:25:55.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.10:25:55.06#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:55.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:55.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:55.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:55.18#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:25:55.18#ibcon#first serial, iclass 23, count 0 2006.201.10:25:55.18#ibcon#enter sib2, iclass 23, count 0 2006.201.10:25:55.18#ibcon#flushed, iclass 23, count 0 2006.201.10:25:55.18#ibcon#about to write, iclass 23, count 0 2006.201.10:25:55.18#ibcon#wrote, iclass 23, count 0 2006.201.10:25:55.18#ibcon#about to read 3, iclass 23, count 0 2006.201.10:25:55.20#ibcon#read 3, iclass 23, count 0 2006.201.10:25:55.20#ibcon#about to read 4, iclass 23, count 0 2006.201.10:25:55.20#ibcon#read 4, iclass 23, count 0 2006.201.10:25:55.20#ibcon#about to read 5, iclass 23, count 0 2006.201.10:25:55.20#ibcon#read 5, iclass 23, count 0 2006.201.10:25:55.20#ibcon#about to read 6, iclass 23, count 0 2006.201.10:25:55.20#ibcon#read 6, iclass 23, count 0 2006.201.10:25:55.20#ibcon#end of sib2, iclass 23, count 0 2006.201.10:25:55.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:25:55.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:25:55.20#ibcon#[27=USB\r\n] 2006.201.10:25:55.20#ibcon#*before write, iclass 23, count 0 2006.201.10:25:55.20#ibcon#enter sib2, iclass 23, count 0 2006.201.10:25:55.20#ibcon#flushed, iclass 23, count 0 2006.201.10:25:55.20#ibcon#about to write, iclass 23, count 0 2006.201.10:25:55.20#ibcon#wrote, iclass 23, count 0 2006.201.10:25:55.20#ibcon#about to read 3, iclass 23, count 0 2006.201.10:25:55.23#ibcon#read 3, iclass 23, count 0 2006.201.10:25:55.23#ibcon#about to read 4, iclass 23, count 0 2006.201.10:25:55.23#ibcon#read 4, iclass 23, count 0 2006.201.10:25:55.23#ibcon#about to read 5, iclass 23, count 0 2006.201.10:25:55.23#ibcon#read 5, iclass 23, count 0 2006.201.10:25:55.23#ibcon#about to read 6, iclass 23, count 0 2006.201.10:25:55.23#ibcon#read 6, iclass 23, count 0 2006.201.10:25:55.23#ibcon#end of sib2, iclass 23, count 0 2006.201.10:25:55.23#ibcon#*after write, iclass 23, count 0 2006.201.10:25:55.23#ibcon#*before return 0, iclass 23, count 0 2006.201.10:25:55.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:55.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:25:55.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:25:55.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:25:55.23$vck44/vblo=6,719.99 2006.201.10:25:55.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.10:25:55.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.10:25:55.23#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:55.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:55.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:55.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:55.23#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:25:55.23#ibcon#first serial, iclass 25, count 0 2006.201.10:25:55.23#ibcon#enter sib2, iclass 25, count 0 2006.201.10:25:55.23#ibcon#flushed, iclass 25, count 0 2006.201.10:25:55.23#ibcon#about to write, iclass 25, count 0 2006.201.10:25:55.23#ibcon#wrote, iclass 25, count 0 2006.201.10:25:55.23#ibcon#about to read 3, iclass 25, count 0 2006.201.10:25:55.25#ibcon#read 3, iclass 25, count 0 2006.201.10:25:55.25#ibcon#about to read 4, iclass 25, count 0 2006.201.10:25:55.25#ibcon#read 4, iclass 25, count 0 2006.201.10:25:55.25#ibcon#about to read 5, iclass 25, count 0 2006.201.10:25:55.25#ibcon#read 5, iclass 25, count 0 2006.201.10:25:55.25#ibcon#about to read 6, iclass 25, count 0 2006.201.10:25:55.25#ibcon#read 6, iclass 25, count 0 2006.201.10:25:55.25#ibcon#end of sib2, iclass 25, count 0 2006.201.10:25:55.25#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:25:55.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:25:55.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:25:55.25#ibcon#*before write, iclass 25, count 0 2006.201.10:25:55.25#ibcon#enter sib2, iclass 25, count 0 2006.201.10:25:55.25#ibcon#flushed, iclass 25, count 0 2006.201.10:25:55.25#ibcon#about to write, iclass 25, count 0 2006.201.10:25:55.25#ibcon#wrote, iclass 25, count 0 2006.201.10:25:55.25#ibcon#about to read 3, iclass 25, count 0 2006.201.10:25:55.29#ibcon#read 3, iclass 25, count 0 2006.201.10:25:55.29#ibcon#about to read 4, iclass 25, count 0 2006.201.10:25:55.29#ibcon#read 4, iclass 25, count 0 2006.201.10:25:55.29#ibcon#about to read 5, iclass 25, count 0 2006.201.10:25:55.29#ibcon#read 5, iclass 25, count 0 2006.201.10:25:55.29#ibcon#about to read 6, iclass 25, count 0 2006.201.10:25:55.29#ibcon#read 6, iclass 25, count 0 2006.201.10:25:55.29#ibcon#end of sib2, iclass 25, count 0 2006.201.10:25:55.29#ibcon#*after write, iclass 25, count 0 2006.201.10:25:55.29#ibcon#*before return 0, iclass 25, count 0 2006.201.10:25:55.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:55.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:25:55.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:25:55.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:25:55.29$vck44/vb=6,4 2006.201.10:25:55.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.10:25:55.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.10:25:55.29#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:55.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:55.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:55.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:55.35#ibcon#enter wrdev, iclass 27, count 2 2006.201.10:25:55.35#ibcon#first serial, iclass 27, count 2 2006.201.10:25:55.35#ibcon#enter sib2, iclass 27, count 2 2006.201.10:25:55.35#ibcon#flushed, iclass 27, count 2 2006.201.10:25:55.35#ibcon#about to write, iclass 27, count 2 2006.201.10:25:55.35#ibcon#wrote, iclass 27, count 2 2006.201.10:25:55.35#ibcon#about to read 3, iclass 27, count 2 2006.201.10:25:55.37#ibcon#read 3, iclass 27, count 2 2006.201.10:25:55.37#ibcon#about to read 4, iclass 27, count 2 2006.201.10:25:55.37#ibcon#read 4, iclass 27, count 2 2006.201.10:25:55.37#ibcon#about to read 5, iclass 27, count 2 2006.201.10:25:55.37#ibcon#read 5, iclass 27, count 2 2006.201.10:25:55.37#ibcon#about to read 6, iclass 27, count 2 2006.201.10:25:55.37#ibcon#read 6, iclass 27, count 2 2006.201.10:25:55.37#ibcon#end of sib2, iclass 27, count 2 2006.201.10:25:55.37#ibcon#*mode == 0, iclass 27, count 2 2006.201.10:25:55.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.10:25:55.37#ibcon#[27=AT06-04\r\n] 2006.201.10:25:55.37#ibcon#*before write, iclass 27, count 2 2006.201.10:25:55.37#ibcon#enter sib2, iclass 27, count 2 2006.201.10:25:55.37#ibcon#flushed, iclass 27, count 2 2006.201.10:25:55.37#ibcon#about to write, iclass 27, count 2 2006.201.10:25:55.37#ibcon#wrote, iclass 27, count 2 2006.201.10:25:55.37#ibcon#about to read 3, iclass 27, count 2 2006.201.10:25:55.41#ibcon#read 3, iclass 27, count 2 2006.201.10:25:55.41#ibcon#about to read 4, iclass 27, count 2 2006.201.10:25:55.41#ibcon#read 4, iclass 27, count 2 2006.201.10:25:55.41#ibcon#about to read 5, iclass 27, count 2 2006.201.10:25:55.41#ibcon#read 5, iclass 27, count 2 2006.201.10:25:55.41#ibcon#about to read 6, iclass 27, count 2 2006.201.10:25:55.41#ibcon#read 6, iclass 27, count 2 2006.201.10:25:55.41#ibcon#end of sib2, iclass 27, count 2 2006.201.10:25:55.41#ibcon#*after write, iclass 27, count 2 2006.201.10:25:55.41#ibcon#*before return 0, iclass 27, count 2 2006.201.10:25:55.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:55.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:25:55.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.10:25:55.41#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:55.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:55.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:55.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:55.53#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:25:55.53#ibcon#first serial, iclass 27, count 0 2006.201.10:25:55.53#ibcon#enter sib2, iclass 27, count 0 2006.201.10:25:55.53#ibcon#flushed, iclass 27, count 0 2006.201.10:25:55.53#ibcon#about to write, iclass 27, count 0 2006.201.10:25:55.53#ibcon#wrote, iclass 27, count 0 2006.201.10:25:55.53#ibcon#about to read 3, iclass 27, count 0 2006.201.10:25:55.55#ibcon#read 3, iclass 27, count 0 2006.201.10:25:55.55#ibcon#about to read 4, iclass 27, count 0 2006.201.10:25:55.55#ibcon#read 4, iclass 27, count 0 2006.201.10:25:55.55#ibcon#about to read 5, iclass 27, count 0 2006.201.10:25:55.55#ibcon#read 5, iclass 27, count 0 2006.201.10:25:55.55#ibcon#about to read 6, iclass 27, count 0 2006.201.10:25:55.55#ibcon#read 6, iclass 27, count 0 2006.201.10:25:55.55#ibcon#end of sib2, iclass 27, count 0 2006.201.10:25:55.55#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:25:55.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:25:55.55#ibcon#[27=USB\r\n] 2006.201.10:25:55.55#ibcon#*before write, iclass 27, count 0 2006.201.10:25:55.55#ibcon#enter sib2, iclass 27, count 0 2006.201.10:25:55.55#ibcon#flushed, iclass 27, count 0 2006.201.10:25:55.55#ibcon#about to write, iclass 27, count 0 2006.201.10:25:55.55#ibcon#wrote, iclass 27, count 0 2006.201.10:25:55.55#ibcon#about to read 3, iclass 27, count 0 2006.201.10:25:55.58#ibcon#read 3, iclass 27, count 0 2006.201.10:25:55.58#ibcon#about to read 4, iclass 27, count 0 2006.201.10:25:55.58#ibcon#read 4, iclass 27, count 0 2006.201.10:25:55.58#ibcon#about to read 5, iclass 27, count 0 2006.201.10:25:55.58#ibcon#read 5, iclass 27, count 0 2006.201.10:25:55.58#ibcon#about to read 6, iclass 27, count 0 2006.201.10:25:55.58#ibcon#read 6, iclass 27, count 0 2006.201.10:25:55.58#ibcon#end of sib2, iclass 27, count 0 2006.201.10:25:55.58#ibcon#*after write, iclass 27, count 0 2006.201.10:25:55.58#ibcon#*before return 0, iclass 27, count 0 2006.201.10:25:55.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:55.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:25:55.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:25:55.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:25:55.58$vck44/vblo=7,734.99 2006.201.10:25:55.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.10:25:55.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.10:25:55.58#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:55.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:55.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:55.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:55.58#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:25:55.58#ibcon#first serial, iclass 29, count 0 2006.201.10:25:55.58#ibcon#enter sib2, iclass 29, count 0 2006.201.10:25:55.58#ibcon#flushed, iclass 29, count 0 2006.201.10:25:55.58#ibcon#about to write, iclass 29, count 0 2006.201.10:25:55.58#ibcon#wrote, iclass 29, count 0 2006.201.10:25:55.58#ibcon#about to read 3, iclass 29, count 0 2006.201.10:25:55.60#ibcon#read 3, iclass 29, count 0 2006.201.10:25:55.60#ibcon#about to read 4, iclass 29, count 0 2006.201.10:25:55.60#ibcon#read 4, iclass 29, count 0 2006.201.10:25:55.60#ibcon#about to read 5, iclass 29, count 0 2006.201.10:25:55.60#ibcon#read 5, iclass 29, count 0 2006.201.10:25:55.60#ibcon#about to read 6, iclass 29, count 0 2006.201.10:25:55.60#ibcon#read 6, iclass 29, count 0 2006.201.10:25:55.60#ibcon#end of sib2, iclass 29, count 0 2006.201.10:25:55.60#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:25:55.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:25:55.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:25:55.60#ibcon#*before write, iclass 29, count 0 2006.201.10:25:55.60#ibcon#enter sib2, iclass 29, count 0 2006.201.10:25:55.60#ibcon#flushed, iclass 29, count 0 2006.201.10:25:55.60#ibcon#about to write, iclass 29, count 0 2006.201.10:25:55.60#ibcon#wrote, iclass 29, count 0 2006.201.10:25:55.60#ibcon#about to read 3, iclass 29, count 0 2006.201.10:25:55.64#ibcon#read 3, iclass 29, count 0 2006.201.10:25:55.64#ibcon#about to read 4, iclass 29, count 0 2006.201.10:25:55.64#ibcon#read 4, iclass 29, count 0 2006.201.10:25:55.64#ibcon#about to read 5, iclass 29, count 0 2006.201.10:25:55.64#ibcon#read 5, iclass 29, count 0 2006.201.10:25:55.64#ibcon#about to read 6, iclass 29, count 0 2006.201.10:25:55.64#ibcon#read 6, iclass 29, count 0 2006.201.10:25:55.64#ibcon#end of sib2, iclass 29, count 0 2006.201.10:25:55.64#ibcon#*after write, iclass 29, count 0 2006.201.10:25:55.64#ibcon#*before return 0, iclass 29, count 0 2006.201.10:25:55.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:55.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:25:55.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:25:55.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:25:55.64$vck44/vb=7,4 2006.201.10:25:55.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.10:25:55.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.10:25:55.64#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:55.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:55.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:55.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:55.70#ibcon#enter wrdev, iclass 31, count 2 2006.201.10:25:55.70#ibcon#first serial, iclass 31, count 2 2006.201.10:25:55.70#ibcon#enter sib2, iclass 31, count 2 2006.201.10:25:55.70#ibcon#flushed, iclass 31, count 2 2006.201.10:25:55.70#ibcon#about to write, iclass 31, count 2 2006.201.10:25:55.70#ibcon#wrote, iclass 31, count 2 2006.201.10:25:55.70#ibcon#about to read 3, iclass 31, count 2 2006.201.10:25:55.72#ibcon#read 3, iclass 31, count 2 2006.201.10:25:55.72#ibcon#about to read 4, iclass 31, count 2 2006.201.10:25:55.72#ibcon#read 4, iclass 31, count 2 2006.201.10:25:55.72#ibcon#about to read 5, iclass 31, count 2 2006.201.10:25:55.72#ibcon#read 5, iclass 31, count 2 2006.201.10:25:55.72#ibcon#about to read 6, iclass 31, count 2 2006.201.10:25:55.72#ibcon#read 6, iclass 31, count 2 2006.201.10:25:55.72#ibcon#end of sib2, iclass 31, count 2 2006.201.10:25:55.72#ibcon#*mode == 0, iclass 31, count 2 2006.201.10:25:55.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.10:25:55.72#ibcon#[27=AT07-04\r\n] 2006.201.10:25:55.72#ibcon#*before write, iclass 31, count 2 2006.201.10:25:55.72#ibcon#enter sib2, iclass 31, count 2 2006.201.10:25:55.72#ibcon#flushed, iclass 31, count 2 2006.201.10:25:55.72#ibcon#about to write, iclass 31, count 2 2006.201.10:25:55.72#ibcon#wrote, iclass 31, count 2 2006.201.10:25:55.72#ibcon#about to read 3, iclass 31, count 2 2006.201.10:25:55.75#ibcon#read 3, iclass 31, count 2 2006.201.10:25:55.75#ibcon#about to read 4, iclass 31, count 2 2006.201.10:25:55.75#ibcon#read 4, iclass 31, count 2 2006.201.10:25:55.75#ibcon#about to read 5, iclass 31, count 2 2006.201.10:25:55.75#ibcon#read 5, iclass 31, count 2 2006.201.10:25:55.75#ibcon#about to read 6, iclass 31, count 2 2006.201.10:25:55.75#ibcon#read 6, iclass 31, count 2 2006.201.10:25:55.75#ibcon#end of sib2, iclass 31, count 2 2006.201.10:25:55.75#ibcon#*after write, iclass 31, count 2 2006.201.10:25:55.75#ibcon#*before return 0, iclass 31, count 2 2006.201.10:25:55.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:55.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:25:55.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.10:25:55.75#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:55.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:55.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:55.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:55.87#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:25:55.87#ibcon#first serial, iclass 31, count 0 2006.201.10:25:55.87#ibcon#enter sib2, iclass 31, count 0 2006.201.10:25:55.87#ibcon#flushed, iclass 31, count 0 2006.201.10:25:55.87#ibcon#about to write, iclass 31, count 0 2006.201.10:25:55.87#ibcon#wrote, iclass 31, count 0 2006.201.10:25:55.87#ibcon#about to read 3, iclass 31, count 0 2006.201.10:25:55.89#ibcon#read 3, iclass 31, count 0 2006.201.10:25:55.89#ibcon#about to read 4, iclass 31, count 0 2006.201.10:25:55.89#ibcon#read 4, iclass 31, count 0 2006.201.10:25:55.89#ibcon#about to read 5, iclass 31, count 0 2006.201.10:25:55.89#ibcon#read 5, iclass 31, count 0 2006.201.10:25:55.89#ibcon#about to read 6, iclass 31, count 0 2006.201.10:25:55.89#ibcon#read 6, iclass 31, count 0 2006.201.10:25:55.89#ibcon#end of sib2, iclass 31, count 0 2006.201.10:25:55.89#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:25:55.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:25:55.89#ibcon#[27=USB\r\n] 2006.201.10:25:55.89#ibcon#*before write, iclass 31, count 0 2006.201.10:25:55.89#ibcon#enter sib2, iclass 31, count 0 2006.201.10:25:55.89#ibcon#flushed, iclass 31, count 0 2006.201.10:25:55.89#ibcon#about to write, iclass 31, count 0 2006.201.10:25:55.89#ibcon#wrote, iclass 31, count 0 2006.201.10:25:55.89#ibcon#about to read 3, iclass 31, count 0 2006.201.10:25:55.92#ibcon#read 3, iclass 31, count 0 2006.201.10:25:55.92#ibcon#about to read 4, iclass 31, count 0 2006.201.10:25:55.92#ibcon#read 4, iclass 31, count 0 2006.201.10:25:55.92#ibcon#about to read 5, iclass 31, count 0 2006.201.10:25:55.92#ibcon#read 5, iclass 31, count 0 2006.201.10:25:55.92#ibcon#about to read 6, iclass 31, count 0 2006.201.10:25:55.92#ibcon#read 6, iclass 31, count 0 2006.201.10:25:55.92#ibcon#end of sib2, iclass 31, count 0 2006.201.10:25:55.92#ibcon#*after write, iclass 31, count 0 2006.201.10:25:55.92#ibcon#*before return 0, iclass 31, count 0 2006.201.10:25:55.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:55.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:25:55.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:25:55.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:25:55.92$vck44/vblo=8,744.99 2006.201.10:25:55.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.10:25:55.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.10:25:55.92#ibcon#ireg 17 cls_cnt 0 2006.201.10:25:55.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:55.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:55.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:55.92#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:25:55.92#ibcon#first serial, iclass 33, count 0 2006.201.10:25:55.92#ibcon#enter sib2, iclass 33, count 0 2006.201.10:25:55.92#ibcon#flushed, iclass 33, count 0 2006.201.10:25:55.92#ibcon#about to write, iclass 33, count 0 2006.201.10:25:55.92#ibcon#wrote, iclass 33, count 0 2006.201.10:25:55.92#ibcon#about to read 3, iclass 33, count 0 2006.201.10:25:55.94#ibcon#read 3, iclass 33, count 0 2006.201.10:25:55.94#ibcon#about to read 4, iclass 33, count 0 2006.201.10:25:55.94#ibcon#read 4, iclass 33, count 0 2006.201.10:25:55.94#ibcon#about to read 5, iclass 33, count 0 2006.201.10:25:55.94#ibcon#read 5, iclass 33, count 0 2006.201.10:25:55.94#ibcon#about to read 6, iclass 33, count 0 2006.201.10:25:55.94#ibcon#read 6, iclass 33, count 0 2006.201.10:25:55.94#ibcon#end of sib2, iclass 33, count 0 2006.201.10:25:55.94#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:25:55.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:25:55.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:25:55.94#ibcon#*before write, iclass 33, count 0 2006.201.10:25:55.94#ibcon#enter sib2, iclass 33, count 0 2006.201.10:25:55.94#ibcon#flushed, iclass 33, count 0 2006.201.10:25:55.94#ibcon#about to write, iclass 33, count 0 2006.201.10:25:55.94#ibcon#wrote, iclass 33, count 0 2006.201.10:25:55.94#ibcon#about to read 3, iclass 33, count 0 2006.201.10:25:55.98#ibcon#read 3, iclass 33, count 0 2006.201.10:25:55.98#ibcon#about to read 4, iclass 33, count 0 2006.201.10:25:55.98#ibcon#read 4, iclass 33, count 0 2006.201.10:25:55.98#ibcon#about to read 5, iclass 33, count 0 2006.201.10:25:55.98#ibcon#read 5, iclass 33, count 0 2006.201.10:25:55.98#ibcon#about to read 6, iclass 33, count 0 2006.201.10:25:55.98#ibcon#read 6, iclass 33, count 0 2006.201.10:25:55.98#ibcon#end of sib2, iclass 33, count 0 2006.201.10:25:55.98#ibcon#*after write, iclass 33, count 0 2006.201.10:25:55.98#ibcon#*before return 0, iclass 33, count 0 2006.201.10:25:55.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:55.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:25:55.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:25:55.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:25:55.98$vck44/vb=8,4 2006.201.10:25:55.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.10:25:55.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.10:25:55.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:25:55.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:56.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:56.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:56.04#ibcon#enter wrdev, iclass 35, count 2 2006.201.10:25:56.04#ibcon#first serial, iclass 35, count 2 2006.201.10:25:56.04#ibcon#enter sib2, iclass 35, count 2 2006.201.10:25:56.04#ibcon#flushed, iclass 35, count 2 2006.201.10:25:56.04#ibcon#about to write, iclass 35, count 2 2006.201.10:25:56.04#ibcon#wrote, iclass 35, count 2 2006.201.10:25:56.04#ibcon#about to read 3, iclass 35, count 2 2006.201.10:25:56.06#ibcon#read 3, iclass 35, count 2 2006.201.10:25:56.06#ibcon#about to read 4, iclass 35, count 2 2006.201.10:25:56.06#ibcon#read 4, iclass 35, count 2 2006.201.10:25:56.06#ibcon#about to read 5, iclass 35, count 2 2006.201.10:25:56.06#ibcon#read 5, iclass 35, count 2 2006.201.10:25:56.06#ibcon#about to read 6, iclass 35, count 2 2006.201.10:25:56.06#ibcon#read 6, iclass 35, count 2 2006.201.10:25:56.06#ibcon#end of sib2, iclass 35, count 2 2006.201.10:25:56.06#ibcon#*mode == 0, iclass 35, count 2 2006.201.10:25:56.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.10:25:56.06#ibcon#[27=AT08-04\r\n] 2006.201.10:25:56.06#ibcon#*before write, iclass 35, count 2 2006.201.10:25:56.06#ibcon#enter sib2, iclass 35, count 2 2006.201.10:25:56.06#ibcon#flushed, iclass 35, count 2 2006.201.10:25:56.06#ibcon#about to write, iclass 35, count 2 2006.201.10:25:56.06#ibcon#wrote, iclass 35, count 2 2006.201.10:25:56.06#ibcon#about to read 3, iclass 35, count 2 2006.201.10:25:56.09#ibcon#read 3, iclass 35, count 2 2006.201.10:25:56.09#ibcon#about to read 4, iclass 35, count 2 2006.201.10:25:56.09#ibcon#read 4, iclass 35, count 2 2006.201.10:25:56.09#ibcon#about to read 5, iclass 35, count 2 2006.201.10:25:56.09#ibcon#read 5, iclass 35, count 2 2006.201.10:25:56.09#ibcon#about to read 6, iclass 35, count 2 2006.201.10:25:56.09#ibcon#read 6, iclass 35, count 2 2006.201.10:25:56.09#ibcon#end of sib2, iclass 35, count 2 2006.201.10:25:56.09#ibcon#*after write, iclass 35, count 2 2006.201.10:25:56.09#ibcon#*before return 0, iclass 35, count 2 2006.201.10:25:56.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:56.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:25:56.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.10:25:56.09#ibcon#ireg 7 cls_cnt 0 2006.201.10:25:56.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:56.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:56.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:56.21#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:25:56.21#ibcon#first serial, iclass 35, count 0 2006.201.10:25:56.21#ibcon#enter sib2, iclass 35, count 0 2006.201.10:25:56.21#ibcon#flushed, iclass 35, count 0 2006.201.10:25:56.21#ibcon#about to write, iclass 35, count 0 2006.201.10:25:56.21#ibcon#wrote, iclass 35, count 0 2006.201.10:25:56.21#ibcon#about to read 3, iclass 35, count 0 2006.201.10:25:56.23#ibcon#read 3, iclass 35, count 0 2006.201.10:25:56.23#ibcon#about to read 4, iclass 35, count 0 2006.201.10:25:56.23#ibcon#read 4, iclass 35, count 0 2006.201.10:25:56.23#ibcon#about to read 5, iclass 35, count 0 2006.201.10:25:56.23#ibcon#read 5, iclass 35, count 0 2006.201.10:25:56.23#ibcon#about to read 6, iclass 35, count 0 2006.201.10:25:56.23#ibcon#read 6, iclass 35, count 0 2006.201.10:25:56.23#ibcon#end of sib2, iclass 35, count 0 2006.201.10:25:56.23#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:25:56.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:25:56.23#ibcon#[27=USB\r\n] 2006.201.10:25:56.23#ibcon#*before write, iclass 35, count 0 2006.201.10:25:56.23#ibcon#enter sib2, iclass 35, count 0 2006.201.10:25:56.23#ibcon#flushed, iclass 35, count 0 2006.201.10:25:56.23#ibcon#about to write, iclass 35, count 0 2006.201.10:25:56.23#ibcon#wrote, iclass 35, count 0 2006.201.10:25:56.23#ibcon#about to read 3, iclass 35, count 0 2006.201.10:25:56.26#ibcon#read 3, iclass 35, count 0 2006.201.10:25:56.26#ibcon#about to read 4, iclass 35, count 0 2006.201.10:25:56.26#ibcon#read 4, iclass 35, count 0 2006.201.10:25:56.26#ibcon#about to read 5, iclass 35, count 0 2006.201.10:25:56.26#ibcon#read 5, iclass 35, count 0 2006.201.10:25:56.26#ibcon#about to read 6, iclass 35, count 0 2006.201.10:25:56.26#ibcon#read 6, iclass 35, count 0 2006.201.10:25:56.26#ibcon#end of sib2, iclass 35, count 0 2006.201.10:25:56.26#ibcon#*after write, iclass 35, count 0 2006.201.10:25:56.26#ibcon#*before return 0, iclass 35, count 0 2006.201.10:25:56.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:56.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:25:56.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:25:56.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:25:56.26$vck44/vabw=wide 2006.201.10:25:56.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.10:25:56.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.10:25:56.26#ibcon#ireg 8 cls_cnt 0 2006.201.10:25:56.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:56.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:56.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:56.26#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:25:56.26#ibcon#first serial, iclass 37, count 0 2006.201.10:25:56.26#ibcon#enter sib2, iclass 37, count 0 2006.201.10:25:56.26#ibcon#flushed, iclass 37, count 0 2006.201.10:25:56.26#ibcon#about to write, iclass 37, count 0 2006.201.10:25:56.26#ibcon#wrote, iclass 37, count 0 2006.201.10:25:56.26#ibcon#about to read 3, iclass 37, count 0 2006.201.10:25:56.28#ibcon#read 3, iclass 37, count 0 2006.201.10:25:56.28#ibcon#about to read 4, iclass 37, count 0 2006.201.10:25:56.28#ibcon#read 4, iclass 37, count 0 2006.201.10:25:56.28#ibcon#about to read 5, iclass 37, count 0 2006.201.10:25:56.28#ibcon#read 5, iclass 37, count 0 2006.201.10:25:56.28#ibcon#about to read 6, iclass 37, count 0 2006.201.10:25:56.28#ibcon#read 6, iclass 37, count 0 2006.201.10:25:56.28#ibcon#end of sib2, iclass 37, count 0 2006.201.10:25:56.28#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:25:56.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:25:56.28#ibcon#[25=BW32\r\n] 2006.201.10:25:56.28#ibcon#*before write, iclass 37, count 0 2006.201.10:25:56.28#ibcon#enter sib2, iclass 37, count 0 2006.201.10:25:56.28#ibcon#flushed, iclass 37, count 0 2006.201.10:25:56.28#ibcon#about to write, iclass 37, count 0 2006.201.10:25:56.28#ibcon#wrote, iclass 37, count 0 2006.201.10:25:56.28#ibcon#about to read 3, iclass 37, count 0 2006.201.10:25:56.32#ibcon#read 3, iclass 37, count 0 2006.201.10:25:56.32#ibcon#about to read 4, iclass 37, count 0 2006.201.10:25:56.32#ibcon#read 4, iclass 37, count 0 2006.201.10:25:56.32#ibcon#about to read 5, iclass 37, count 0 2006.201.10:25:56.32#ibcon#read 5, iclass 37, count 0 2006.201.10:25:56.32#ibcon#about to read 6, iclass 37, count 0 2006.201.10:25:56.32#ibcon#read 6, iclass 37, count 0 2006.201.10:25:56.32#ibcon#end of sib2, iclass 37, count 0 2006.201.10:25:56.32#ibcon#*after write, iclass 37, count 0 2006.201.10:25:56.32#ibcon#*before return 0, iclass 37, count 0 2006.201.10:25:56.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:56.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:25:56.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:25:56.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:25:56.32$vck44/vbbw=wide 2006.201.10:25:56.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.10:25:56.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.10:25:56.32#ibcon#ireg 8 cls_cnt 0 2006.201.10:25:56.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:25:56.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:25:56.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:25:56.38#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:25:56.38#ibcon#first serial, iclass 39, count 0 2006.201.10:25:56.38#ibcon#enter sib2, iclass 39, count 0 2006.201.10:25:56.38#ibcon#flushed, iclass 39, count 0 2006.201.10:25:56.38#ibcon#about to write, iclass 39, count 0 2006.201.10:25:56.38#ibcon#wrote, iclass 39, count 0 2006.201.10:25:56.38#ibcon#about to read 3, iclass 39, count 0 2006.201.10:25:56.40#ibcon#read 3, iclass 39, count 0 2006.201.10:25:56.40#ibcon#about to read 4, iclass 39, count 0 2006.201.10:25:56.40#ibcon#read 4, iclass 39, count 0 2006.201.10:25:56.40#ibcon#about to read 5, iclass 39, count 0 2006.201.10:25:56.40#ibcon#read 5, iclass 39, count 0 2006.201.10:25:56.40#ibcon#about to read 6, iclass 39, count 0 2006.201.10:25:56.40#ibcon#read 6, iclass 39, count 0 2006.201.10:25:56.40#ibcon#end of sib2, iclass 39, count 0 2006.201.10:25:56.40#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:25:56.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:25:56.40#ibcon#[27=BW32\r\n] 2006.201.10:25:56.40#ibcon#*before write, iclass 39, count 0 2006.201.10:25:56.40#ibcon#enter sib2, iclass 39, count 0 2006.201.10:25:56.40#ibcon#flushed, iclass 39, count 0 2006.201.10:25:56.40#ibcon#about to write, iclass 39, count 0 2006.201.10:25:56.40#ibcon#wrote, iclass 39, count 0 2006.201.10:25:56.40#ibcon#about to read 3, iclass 39, count 0 2006.201.10:25:56.43#ibcon#read 3, iclass 39, count 0 2006.201.10:25:56.43#ibcon#about to read 4, iclass 39, count 0 2006.201.10:25:56.43#ibcon#read 4, iclass 39, count 0 2006.201.10:25:56.43#ibcon#about to read 5, iclass 39, count 0 2006.201.10:25:56.43#ibcon#read 5, iclass 39, count 0 2006.201.10:25:56.43#ibcon#about to read 6, iclass 39, count 0 2006.201.10:25:56.43#ibcon#read 6, iclass 39, count 0 2006.201.10:25:56.43#ibcon#end of sib2, iclass 39, count 0 2006.201.10:25:56.43#ibcon#*after write, iclass 39, count 0 2006.201.10:25:56.43#ibcon#*before return 0, iclass 39, count 0 2006.201.10:25:56.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:25:56.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:25:56.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:25:56.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:25:56.43$setupk4/ifdk4 2006.201.10:25:56.43$ifdk4/lo= 2006.201.10:25:56.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:25:56.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:25:56.43$ifdk4/patch= 2006.201.10:25:56.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:25:56.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:25:56.43$setupk4/!*+20s 2006.201.10:26:04.04#abcon#<5=/05 2.4 4.2 21.78 961003.5\r\n> 2006.201.10:26:04.06#abcon#{5=INTERFACE CLEAR} 2006.201.10:26:04.12#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:26:10.92$setupk4/"tpicd 2006.201.10:26:10.92$setupk4/echo=off 2006.201.10:26:10.92$setupk4/xlog=off 2006.201.10:26:10.92:!2006.201.10:27:04 2006.201.10:26:17.14#trakl#Source acquired 2006.201.10:26:19.14#flagr#flagr/antenna,acquired 2006.201.10:27:04.00:preob 2006.201.10:27:05.14/onsource/TRACKING 2006.201.10:27:05.14:!2006.201.10:27:14 2006.201.10:27:14.00:"tape 2006.201.10:27:14.00:"st=record 2006.201.10:27:14.00:data_valid=on 2006.201.10:27:14.00:midob 2006.201.10:27:14.14/onsource/TRACKING 2006.201.10:27:14.14/wx/21.76,1003.6,96 2006.201.10:27:14.20/cable/+6.4683E-03 2006.201.10:27:15.29/va/01,08,usb,yes,31,33 2006.201.10:27:15.29/va/02,07,usb,yes,33,34 2006.201.10:27:15.29/va/03,08,usb,yes,30,31 2006.201.10:27:15.29/va/04,07,usb,yes,34,36 2006.201.10:27:15.29/va/05,04,usb,yes,30,31 2006.201.10:27:15.29/va/06,05,usb,yes,30,30 2006.201.10:27:15.29/va/07,05,usb,yes,30,31 2006.201.10:27:15.29/va/08,04,usb,yes,29,35 2006.201.10:27:15.52/valo/01,524.99,yes,locked 2006.201.10:27:15.52/valo/02,534.99,yes,locked 2006.201.10:27:15.52/valo/03,564.99,yes,locked 2006.201.10:27:15.52/valo/04,624.99,yes,locked 2006.201.10:27:15.52/valo/05,734.99,yes,locked 2006.201.10:27:15.52/valo/06,814.99,yes,locked 2006.201.10:27:15.52/valo/07,864.99,yes,locked 2006.201.10:27:15.52/valo/08,884.99,yes,locked 2006.201.10:27:16.61/vb/01,04,usb,yes,28,26 2006.201.10:27:16.61/vb/02,05,usb,yes,26,27 2006.201.10:27:16.61/vb/03,04,usb,yes,27,30 2006.201.10:27:16.61/vb/04,05,usb,yes,27,26 2006.201.10:27:16.61/vb/05,04,usb,yes,24,27 2006.201.10:27:16.61/vb/06,04,usb,yes,29,25 2006.201.10:27:16.61/vb/07,04,usb,yes,28,28 2006.201.10:27:16.61/vb/08,04,usb,yes,26,29 2006.201.10:27:16.84/vblo/01,629.99,yes,locked 2006.201.10:27:16.84/vblo/02,634.99,yes,locked 2006.201.10:27:16.84/vblo/03,649.99,yes,locked 2006.201.10:27:16.84/vblo/04,679.99,yes,locked 2006.201.10:27:16.84/vblo/05,709.99,yes,locked 2006.201.10:27:16.84/vblo/06,719.99,yes,locked 2006.201.10:27:16.84/vblo/07,734.99,yes,locked 2006.201.10:27:16.84/vblo/08,744.99,yes,locked 2006.201.10:27:16.99/vabw/8 2006.201.10:27:17.14/vbbw/8 2006.201.10:27:17.23/xfe/off,on,14.5 2006.201.10:27:17.61/ifatt/23,28,28,28 2006.201.10:27:18.06/fmout-gps/S +4.60E-07 2006.201.10:27:18.10:!2006.201.10:28:54 2006.201.10:28:54.00:data_valid=off 2006.201.10:28:54.00:"et 2006.201.10:28:54.00:!+3s 2006.201.10:28:57.02:"tape 2006.201.10:28:57.02:postob 2006.201.10:28:57.24/cable/+6.4670E-03 2006.201.10:28:57.24/wx/21.74,1003.6,97 2006.201.10:28:57.32/fmout-gps/S +4.57E-07 2006.201.10:28:57.32:scan_name=201-1031,jd0607,300 2006.201.10:28:57.32:source=0059+581,010245.76,582411.1,2000.0,cw 2006.201.10:28:59.14#flagr#flagr/antenna,new-source 2006.201.10:28:59.14:checkk5 2006.201.10:28:59.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:28:59.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:29:00.24/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:29:00.61/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:29:00.98/chk_obsdata//k5ts1/T2011027??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.10:29:01.35/chk_obsdata//k5ts2/T2011027??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.10:29:01.71/chk_obsdata//k5ts3/T2011027??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.10:29:02.08/chk_obsdata//k5ts4/T2011027??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.10:29:02.77/k5log//k5ts1_log_newline 2006.201.10:29:03.47/k5log//k5ts2_log_newline 2006.201.10:29:04.16/k5log//k5ts3_log_newline 2006.201.10:29:04.85/k5log//k5ts4_log_newline 2006.201.10:29:04.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:29:04.87:setupk4=1 2006.201.10:29:04.87$setupk4/echo=on 2006.201.10:29:04.87$setupk4/pcalon 2006.201.10:29:04.87$pcalon/"no phase cal control is implemented here 2006.201.10:29:04.87$setupk4/"tpicd=stop 2006.201.10:29:04.87$setupk4/"rec=synch_on 2006.201.10:29:04.87$setupk4/"rec_mode=128 2006.201.10:29:04.87$setupk4/!* 2006.201.10:29:04.87$setupk4/recpk4 2006.201.10:29:04.87$recpk4/recpatch= 2006.201.10:29:04.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:29:04.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:29:04.88$setupk4/vck44 2006.201.10:29:04.88$vck44/valo=1,524.99 2006.201.10:29:04.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.10:29:04.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.10:29:04.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:04.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:04.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:04.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:04.88#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:29:04.88#ibcon#first serial, iclass 6, count 0 2006.201.10:29:04.88#ibcon#enter sib2, iclass 6, count 0 2006.201.10:29:04.88#ibcon#flushed, iclass 6, count 0 2006.201.10:29:04.88#ibcon#about to write, iclass 6, count 0 2006.201.10:29:04.88#ibcon#wrote, iclass 6, count 0 2006.201.10:29:04.88#ibcon#about to read 3, iclass 6, count 0 2006.201.10:29:04.91#ibcon#read 3, iclass 6, count 0 2006.201.10:29:04.91#ibcon#about to read 4, iclass 6, count 0 2006.201.10:29:04.91#ibcon#read 4, iclass 6, count 0 2006.201.10:29:04.91#ibcon#about to read 5, iclass 6, count 0 2006.201.10:29:04.91#ibcon#read 5, iclass 6, count 0 2006.201.10:29:04.91#ibcon#about to read 6, iclass 6, count 0 2006.201.10:29:04.91#ibcon#read 6, iclass 6, count 0 2006.201.10:29:04.91#ibcon#end of sib2, iclass 6, count 0 2006.201.10:29:04.91#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:29:04.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:29:04.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:29:04.91#ibcon#*before write, iclass 6, count 0 2006.201.10:29:04.91#ibcon#enter sib2, iclass 6, count 0 2006.201.10:29:04.91#ibcon#flushed, iclass 6, count 0 2006.201.10:29:04.91#ibcon#about to write, iclass 6, count 0 2006.201.10:29:04.91#ibcon#wrote, iclass 6, count 0 2006.201.10:29:04.91#ibcon#about to read 3, iclass 6, count 0 2006.201.10:29:04.96#ibcon#read 3, iclass 6, count 0 2006.201.10:29:04.96#ibcon#about to read 4, iclass 6, count 0 2006.201.10:29:04.96#ibcon#read 4, iclass 6, count 0 2006.201.10:29:04.96#ibcon#about to read 5, iclass 6, count 0 2006.201.10:29:04.96#ibcon#read 5, iclass 6, count 0 2006.201.10:29:04.96#ibcon#about to read 6, iclass 6, count 0 2006.201.10:29:04.96#ibcon#read 6, iclass 6, count 0 2006.201.10:29:04.96#ibcon#end of sib2, iclass 6, count 0 2006.201.10:29:04.96#ibcon#*after write, iclass 6, count 0 2006.201.10:29:04.96#ibcon#*before return 0, iclass 6, count 0 2006.201.10:29:04.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:04.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:04.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:29:04.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:29:04.96$vck44/va=1,8 2006.201.10:29:04.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.10:29:04.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.10:29:04.96#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:04.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:04.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:04.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:04.96#ibcon#enter wrdev, iclass 10, count 2 2006.201.10:29:04.96#ibcon#first serial, iclass 10, count 2 2006.201.10:29:04.96#ibcon#enter sib2, iclass 10, count 2 2006.201.10:29:04.96#ibcon#flushed, iclass 10, count 2 2006.201.10:29:04.96#ibcon#about to write, iclass 10, count 2 2006.201.10:29:04.96#ibcon#wrote, iclass 10, count 2 2006.201.10:29:04.96#ibcon#about to read 3, iclass 10, count 2 2006.201.10:29:04.98#ibcon#read 3, iclass 10, count 2 2006.201.10:29:04.98#ibcon#about to read 4, iclass 10, count 2 2006.201.10:29:04.98#ibcon#read 4, iclass 10, count 2 2006.201.10:29:04.98#ibcon#about to read 5, iclass 10, count 2 2006.201.10:29:04.98#ibcon#read 5, iclass 10, count 2 2006.201.10:29:04.98#ibcon#about to read 6, iclass 10, count 2 2006.201.10:29:04.98#ibcon#read 6, iclass 10, count 2 2006.201.10:29:04.98#ibcon#end of sib2, iclass 10, count 2 2006.201.10:29:04.98#ibcon#*mode == 0, iclass 10, count 2 2006.201.10:29:04.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.10:29:04.98#ibcon#[25=AT01-08\r\n] 2006.201.10:29:04.98#ibcon#*before write, iclass 10, count 2 2006.201.10:29:04.98#ibcon#enter sib2, iclass 10, count 2 2006.201.10:29:04.98#ibcon#flushed, iclass 10, count 2 2006.201.10:29:04.98#ibcon#about to write, iclass 10, count 2 2006.201.10:29:04.98#ibcon#wrote, iclass 10, count 2 2006.201.10:29:04.98#ibcon#about to read 3, iclass 10, count 2 2006.201.10:29:05.01#ibcon#read 3, iclass 10, count 2 2006.201.10:29:05.01#ibcon#about to read 4, iclass 10, count 2 2006.201.10:29:05.01#ibcon#read 4, iclass 10, count 2 2006.201.10:29:05.01#ibcon#about to read 5, iclass 10, count 2 2006.201.10:29:05.01#ibcon#read 5, iclass 10, count 2 2006.201.10:29:05.01#ibcon#about to read 6, iclass 10, count 2 2006.201.10:29:05.01#ibcon#read 6, iclass 10, count 2 2006.201.10:29:05.01#ibcon#end of sib2, iclass 10, count 2 2006.201.10:29:05.01#ibcon#*after write, iclass 10, count 2 2006.201.10:29:05.01#ibcon#*before return 0, iclass 10, count 2 2006.201.10:29:05.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:05.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:05.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.10:29:05.01#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:05.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:05.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:05.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:05.13#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:29:05.13#ibcon#first serial, iclass 10, count 0 2006.201.10:29:05.13#ibcon#enter sib2, iclass 10, count 0 2006.201.10:29:05.13#ibcon#flushed, iclass 10, count 0 2006.201.10:29:05.13#ibcon#about to write, iclass 10, count 0 2006.201.10:29:05.13#ibcon#wrote, iclass 10, count 0 2006.201.10:29:05.13#ibcon#about to read 3, iclass 10, count 0 2006.201.10:29:05.15#ibcon#read 3, iclass 10, count 0 2006.201.10:29:05.15#ibcon#about to read 4, iclass 10, count 0 2006.201.10:29:05.15#ibcon#read 4, iclass 10, count 0 2006.201.10:29:05.15#ibcon#about to read 5, iclass 10, count 0 2006.201.10:29:05.15#ibcon#read 5, iclass 10, count 0 2006.201.10:29:05.15#ibcon#about to read 6, iclass 10, count 0 2006.201.10:29:05.15#ibcon#read 6, iclass 10, count 0 2006.201.10:29:05.15#ibcon#end of sib2, iclass 10, count 0 2006.201.10:29:05.15#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:29:05.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:29:05.15#ibcon#[25=USB\r\n] 2006.201.10:29:05.15#ibcon#*before write, iclass 10, count 0 2006.201.10:29:05.15#ibcon#enter sib2, iclass 10, count 0 2006.201.10:29:05.15#ibcon#flushed, iclass 10, count 0 2006.201.10:29:05.15#ibcon#about to write, iclass 10, count 0 2006.201.10:29:05.15#ibcon#wrote, iclass 10, count 0 2006.201.10:29:05.15#ibcon#about to read 3, iclass 10, count 0 2006.201.10:29:05.18#ibcon#read 3, iclass 10, count 0 2006.201.10:29:05.18#ibcon#about to read 4, iclass 10, count 0 2006.201.10:29:05.18#ibcon#read 4, iclass 10, count 0 2006.201.10:29:05.18#ibcon#about to read 5, iclass 10, count 0 2006.201.10:29:05.18#ibcon#read 5, iclass 10, count 0 2006.201.10:29:05.18#ibcon#about to read 6, iclass 10, count 0 2006.201.10:29:05.18#ibcon#read 6, iclass 10, count 0 2006.201.10:29:05.18#ibcon#end of sib2, iclass 10, count 0 2006.201.10:29:05.18#ibcon#*after write, iclass 10, count 0 2006.201.10:29:05.18#ibcon#*before return 0, iclass 10, count 0 2006.201.10:29:05.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:05.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:05.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:29:05.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:29:05.18$vck44/valo=2,534.99 2006.201.10:29:05.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.10:29:05.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.10:29:05.18#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:05.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:05.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:05.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:05.18#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:29:05.18#ibcon#first serial, iclass 12, count 0 2006.201.10:29:05.18#ibcon#enter sib2, iclass 12, count 0 2006.201.10:29:05.18#ibcon#flushed, iclass 12, count 0 2006.201.10:29:05.18#ibcon#about to write, iclass 12, count 0 2006.201.10:29:05.18#ibcon#wrote, iclass 12, count 0 2006.201.10:29:05.18#ibcon#about to read 3, iclass 12, count 0 2006.201.10:29:05.20#ibcon#read 3, iclass 12, count 0 2006.201.10:29:05.20#ibcon#about to read 4, iclass 12, count 0 2006.201.10:29:05.20#ibcon#read 4, iclass 12, count 0 2006.201.10:29:05.20#ibcon#about to read 5, iclass 12, count 0 2006.201.10:29:05.20#ibcon#read 5, iclass 12, count 0 2006.201.10:29:05.20#ibcon#about to read 6, iclass 12, count 0 2006.201.10:29:05.20#ibcon#read 6, iclass 12, count 0 2006.201.10:29:05.20#ibcon#end of sib2, iclass 12, count 0 2006.201.10:29:05.20#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:29:05.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:29:05.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:29:05.20#ibcon#*before write, iclass 12, count 0 2006.201.10:29:05.20#ibcon#enter sib2, iclass 12, count 0 2006.201.10:29:05.20#ibcon#flushed, iclass 12, count 0 2006.201.10:29:05.20#ibcon#about to write, iclass 12, count 0 2006.201.10:29:05.20#ibcon#wrote, iclass 12, count 0 2006.201.10:29:05.20#ibcon#about to read 3, iclass 12, count 0 2006.201.10:29:05.25#ibcon#read 3, iclass 12, count 0 2006.201.10:29:05.25#ibcon#about to read 4, iclass 12, count 0 2006.201.10:29:05.25#ibcon#read 4, iclass 12, count 0 2006.201.10:29:05.25#ibcon#about to read 5, iclass 12, count 0 2006.201.10:29:05.25#ibcon#read 5, iclass 12, count 0 2006.201.10:29:05.25#ibcon#about to read 6, iclass 12, count 0 2006.201.10:29:05.25#ibcon#read 6, iclass 12, count 0 2006.201.10:29:05.25#ibcon#end of sib2, iclass 12, count 0 2006.201.10:29:05.25#ibcon#*after write, iclass 12, count 0 2006.201.10:29:05.25#ibcon#*before return 0, iclass 12, count 0 2006.201.10:29:05.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:05.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:05.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:29:05.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:29:05.25$vck44/va=2,7 2006.201.10:29:05.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.10:29:05.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.10:29:05.25#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:05.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:05.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:05.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:05.30#ibcon#enter wrdev, iclass 14, count 2 2006.201.10:29:05.30#ibcon#first serial, iclass 14, count 2 2006.201.10:29:05.30#ibcon#enter sib2, iclass 14, count 2 2006.201.10:29:05.30#ibcon#flushed, iclass 14, count 2 2006.201.10:29:05.30#ibcon#about to write, iclass 14, count 2 2006.201.10:29:05.30#ibcon#wrote, iclass 14, count 2 2006.201.10:29:05.30#ibcon#about to read 3, iclass 14, count 2 2006.201.10:29:05.32#ibcon#read 3, iclass 14, count 2 2006.201.10:29:05.32#ibcon#about to read 4, iclass 14, count 2 2006.201.10:29:05.32#ibcon#read 4, iclass 14, count 2 2006.201.10:29:05.32#ibcon#about to read 5, iclass 14, count 2 2006.201.10:29:05.32#ibcon#read 5, iclass 14, count 2 2006.201.10:29:05.32#ibcon#about to read 6, iclass 14, count 2 2006.201.10:29:05.32#ibcon#read 6, iclass 14, count 2 2006.201.10:29:05.32#ibcon#end of sib2, iclass 14, count 2 2006.201.10:29:05.32#ibcon#*mode == 0, iclass 14, count 2 2006.201.10:29:05.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.10:29:05.32#ibcon#[25=AT02-07\r\n] 2006.201.10:29:05.32#ibcon#*before write, iclass 14, count 2 2006.201.10:29:05.32#ibcon#enter sib2, iclass 14, count 2 2006.201.10:29:05.32#ibcon#flushed, iclass 14, count 2 2006.201.10:29:05.32#ibcon#about to write, iclass 14, count 2 2006.201.10:29:05.32#ibcon#wrote, iclass 14, count 2 2006.201.10:29:05.32#ibcon#about to read 3, iclass 14, count 2 2006.201.10:29:05.35#ibcon#read 3, iclass 14, count 2 2006.201.10:29:05.35#ibcon#about to read 4, iclass 14, count 2 2006.201.10:29:05.35#ibcon#read 4, iclass 14, count 2 2006.201.10:29:05.35#ibcon#about to read 5, iclass 14, count 2 2006.201.10:29:05.35#ibcon#read 5, iclass 14, count 2 2006.201.10:29:05.35#ibcon#about to read 6, iclass 14, count 2 2006.201.10:29:05.35#ibcon#read 6, iclass 14, count 2 2006.201.10:29:05.35#ibcon#end of sib2, iclass 14, count 2 2006.201.10:29:05.35#ibcon#*after write, iclass 14, count 2 2006.201.10:29:05.35#ibcon#*before return 0, iclass 14, count 2 2006.201.10:29:05.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:05.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:05.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.10:29:05.35#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:05.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:05.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:05.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:05.47#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:29:05.47#ibcon#first serial, iclass 14, count 0 2006.201.10:29:05.47#ibcon#enter sib2, iclass 14, count 0 2006.201.10:29:05.47#ibcon#flushed, iclass 14, count 0 2006.201.10:29:05.47#ibcon#about to write, iclass 14, count 0 2006.201.10:29:05.47#ibcon#wrote, iclass 14, count 0 2006.201.10:29:05.47#ibcon#about to read 3, iclass 14, count 0 2006.201.10:29:05.49#ibcon#read 3, iclass 14, count 0 2006.201.10:29:05.49#ibcon#about to read 4, iclass 14, count 0 2006.201.10:29:05.49#ibcon#read 4, iclass 14, count 0 2006.201.10:29:05.49#ibcon#about to read 5, iclass 14, count 0 2006.201.10:29:05.49#ibcon#read 5, iclass 14, count 0 2006.201.10:29:05.49#ibcon#about to read 6, iclass 14, count 0 2006.201.10:29:05.49#ibcon#read 6, iclass 14, count 0 2006.201.10:29:05.49#ibcon#end of sib2, iclass 14, count 0 2006.201.10:29:05.49#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:29:05.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:29:05.49#ibcon#[25=USB\r\n] 2006.201.10:29:05.49#ibcon#*before write, iclass 14, count 0 2006.201.10:29:05.49#ibcon#enter sib2, iclass 14, count 0 2006.201.10:29:05.49#ibcon#flushed, iclass 14, count 0 2006.201.10:29:05.49#ibcon#about to write, iclass 14, count 0 2006.201.10:29:05.49#ibcon#wrote, iclass 14, count 0 2006.201.10:29:05.49#ibcon#about to read 3, iclass 14, count 0 2006.201.10:29:05.52#ibcon#read 3, iclass 14, count 0 2006.201.10:29:05.52#ibcon#about to read 4, iclass 14, count 0 2006.201.10:29:05.52#ibcon#read 4, iclass 14, count 0 2006.201.10:29:05.52#ibcon#about to read 5, iclass 14, count 0 2006.201.10:29:05.52#ibcon#read 5, iclass 14, count 0 2006.201.10:29:05.52#ibcon#about to read 6, iclass 14, count 0 2006.201.10:29:05.52#ibcon#read 6, iclass 14, count 0 2006.201.10:29:05.52#ibcon#end of sib2, iclass 14, count 0 2006.201.10:29:05.52#ibcon#*after write, iclass 14, count 0 2006.201.10:29:05.52#ibcon#*before return 0, iclass 14, count 0 2006.201.10:29:05.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:05.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:05.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:29:05.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:29:05.52$vck44/valo=3,564.99 2006.201.10:29:05.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.10:29:05.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.10:29:05.52#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:05.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:05.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:05.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:05.52#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:29:05.52#ibcon#first serial, iclass 16, count 0 2006.201.10:29:05.52#ibcon#enter sib2, iclass 16, count 0 2006.201.10:29:05.52#ibcon#flushed, iclass 16, count 0 2006.201.10:29:05.52#ibcon#about to write, iclass 16, count 0 2006.201.10:29:05.52#ibcon#wrote, iclass 16, count 0 2006.201.10:29:05.52#ibcon#about to read 3, iclass 16, count 0 2006.201.10:29:05.54#ibcon#read 3, iclass 16, count 0 2006.201.10:29:05.54#ibcon#about to read 4, iclass 16, count 0 2006.201.10:29:05.54#ibcon#read 4, iclass 16, count 0 2006.201.10:29:05.54#ibcon#about to read 5, iclass 16, count 0 2006.201.10:29:05.54#ibcon#read 5, iclass 16, count 0 2006.201.10:29:05.54#ibcon#about to read 6, iclass 16, count 0 2006.201.10:29:05.54#ibcon#read 6, iclass 16, count 0 2006.201.10:29:05.54#ibcon#end of sib2, iclass 16, count 0 2006.201.10:29:05.54#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:29:05.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:29:05.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:29:05.54#ibcon#*before write, iclass 16, count 0 2006.201.10:29:05.54#ibcon#enter sib2, iclass 16, count 0 2006.201.10:29:05.54#ibcon#flushed, iclass 16, count 0 2006.201.10:29:05.54#ibcon#about to write, iclass 16, count 0 2006.201.10:29:05.54#ibcon#wrote, iclass 16, count 0 2006.201.10:29:05.54#ibcon#about to read 3, iclass 16, count 0 2006.201.10:29:05.59#ibcon#read 3, iclass 16, count 0 2006.201.10:29:05.59#ibcon#about to read 4, iclass 16, count 0 2006.201.10:29:05.59#ibcon#read 4, iclass 16, count 0 2006.201.10:29:05.59#ibcon#about to read 5, iclass 16, count 0 2006.201.10:29:05.59#ibcon#read 5, iclass 16, count 0 2006.201.10:29:05.59#ibcon#about to read 6, iclass 16, count 0 2006.201.10:29:05.59#ibcon#read 6, iclass 16, count 0 2006.201.10:29:05.59#ibcon#end of sib2, iclass 16, count 0 2006.201.10:29:05.59#ibcon#*after write, iclass 16, count 0 2006.201.10:29:05.59#ibcon#*before return 0, iclass 16, count 0 2006.201.10:29:05.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:05.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:05.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:29:05.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:29:05.59$vck44/va=3,8 2006.201.10:29:05.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.10:29:05.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.10:29:05.59#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:05.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:05.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:05.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:05.64#ibcon#enter wrdev, iclass 18, count 2 2006.201.10:29:05.64#ibcon#first serial, iclass 18, count 2 2006.201.10:29:05.64#ibcon#enter sib2, iclass 18, count 2 2006.201.10:29:05.64#ibcon#flushed, iclass 18, count 2 2006.201.10:29:05.64#ibcon#about to write, iclass 18, count 2 2006.201.10:29:05.64#ibcon#wrote, iclass 18, count 2 2006.201.10:29:05.64#ibcon#about to read 3, iclass 18, count 2 2006.201.10:29:05.66#ibcon#read 3, iclass 18, count 2 2006.201.10:29:05.66#ibcon#about to read 4, iclass 18, count 2 2006.201.10:29:05.66#ibcon#read 4, iclass 18, count 2 2006.201.10:29:05.66#ibcon#about to read 5, iclass 18, count 2 2006.201.10:29:05.66#ibcon#read 5, iclass 18, count 2 2006.201.10:29:05.66#ibcon#about to read 6, iclass 18, count 2 2006.201.10:29:05.66#ibcon#read 6, iclass 18, count 2 2006.201.10:29:05.66#ibcon#end of sib2, iclass 18, count 2 2006.201.10:29:05.66#ibcon#*mode == 0, iclass 18, count 2 2006.201.10:29:05.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.10:29:05.66#ibcon#[25=AT03-08\r\n] 2006.201.10:29:05.66#ibcon#*before write, iclass 18, count 2 2006.201.10:29:05.66#ibcon#enter sib2, iclass 18, count 2 2006.201.10:29:05.66#ibcon#flushed, iclass 18, count 2 2006.201.10:29:05.66#ibcon#about to write, iclass 18, count 2 2006.201.10:29:05.66#ibcon#wrote, iclass 18, count 2 2006.201.10:29:05.66#ibcon#about to read 3, iclass 18, count 2 2006.201.10:29:05.69#ibcon#read 3, iclass 18, count 2 2006.201.10:29:05.69#ibcon#about to read 4, iclass 18, count 2 2006.201.10:29:05.69#ibcon#read 4, iclass 18, count 2 2006.201.10:29:05.69#ibcon#about to read 5, iclass 18, count 2 2006.201.10:29:05.69#ibcon#read 5, iclass 18, count 2 2006.201.10:29:05.69#ibcon#about to read 6, iclass 18, count 2 2006.201.10:29:05.69#ibcon#read 6, iclass 18, count 2 2006.201.10:29:05.69#ibcon#end of sib2, iclass 18, count 2 2006.201.10:29:05.69#ibcon#*after write, iclass 18, count 2 2006.201.10:29:05.69#ibcon#*before return 0, iclass 18, count 2 2006.201.10:29:05.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:05.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:05.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.10:29:05.69#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:05.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:05.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:05.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:05.81#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:29:05.81#ibcon#first serial, iclass 18, count 0 2006.201.10:29:05.81#ibcon#enter sib2, iclass 18, count 0 2006.201.10:29:05.81#ibcon#flushed, iclass 18, count 0 2006.201.10:29:05.81#ibcon#about to write, iclass 18, count 0 2006.201.10:29:05.81#ibcon#wrote, iclass 18, count 0 2006.201.10:29:05.81#ibcon#about to read 3, iclass 18, count 0 2006.201.10:29:05.83#ibcon#read 3, iclass 18, count 0 2006.201.10:29:05.83#ibcon#about to read 4, iclass 18, count 0 2006.201.10:29:05.83#ibcon#read 4, iclass 18, count 0 2006.201.10:29:05.83#ibcon#about to read 5, iclass 18, count 0 2006.201.10:29:05.83#ibcon#read 5, iclass 18, count 0 2006.201.10:29:05.83#ibcon#about to read 6, iclass 18, count 0 2006.201.10:29:05.83#ibcon#read 6, iclass 18, count 0 2006.201.10:29:05.83#ibcon#end of sib2, iclass 18, count 0 2006.201.10:29:05.83#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:29:05.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:29:05.83#ibcon#[25=USB\r\n] 2006.201.10:29:05.83#ibcon#*before write, iclass 18, count 0 2006.201.10:29:05.83#ibcon#enter sib2, iclass 18, count 0 2006.201.10:29:05.83#ibcon#flushed, iclass 18, count 0 2006.201.10:29:05.83#ibcon#about to write, iclass 18, count 0 2006.201.10:29:05.83#ibcon#wrote, iclass 18, count 0 2006.201.10:29:05.83#ibcon#about to read 3, iclass 18, count 0 2006.201.10:29:05.86#ibcon#read 3, iclass 18, count 0 2006.201.10:29:05.86#ibcon#about to read 4, iclass 18, count 0 2006.201.10:29:05.86#ibcon#read 4, iclass 18, count 0 2006.201.10:29:05.86#ibcon#about to read 5, iclass 18, count 0 2006.201.10:29:05.86#ibcon#read 5, iclass 18, count 0 2006.201.10:29:05.86#ibcon#about to read 6, iclass 18, count 0 2006.201.10:29:05.86#ibcon#read 6, iclass 18, count 0 2006.201.10:29:05.86#ibcon#end of sib2, iclass 18, count 0 2006.201.10:29:05.86#ibcon#*after write, iclass 18, count 0 2006.201.10:29:05.86#ibcon#*before return 0, iclass 18, count 0 2006.201.10:29:05.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:05.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:05.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:29:05.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:29:05.86$vck44/valo=4,624.99 2006.201.10:29:05.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.10:29:05.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.10:29:05.86#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:05.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:05.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:05.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:05.86#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:29:05.86#ibcon#first serial, iclass 20, count 0 2006.201.10:29:05.86#ibcon#enter sib2, iclass 20, count 0 2006.201.10:29:05.86#ibcon#flushed, iclass 20, count 0 2006.201.10:29:05.86#ibcon#about to write, iclass 20, count 0 2006.201.10:29:05.86#ibcon#wrote, iclass 20, count 0 2006.201.10:29:05.86#ibcon#about to read 3, iclass 20, count 0 2006.201.10:29:05.88#ibcon#read 3, iclass 20, count 0 2006.201.10:29:05.88#ibcon#about to read 4, iclass 20, count 0 2006.201.10:29:05.88#ibcon#read 4, iclass 20, count 0 2006.201.10:29:05.88#ibcon#about to read 5, iclass 20, count 0 2006.201.10:29:05.88#ibcon#read 5, iclass 20, count 0 2006.201.10:29:05.88#ibcon#about to read 6, iclass 20, count 0 2006.201.10:29:05.88#ibcon#read 6, iclass 20, count 0 2006.201.10:29:05.88#ibcon#end of sib2, iclass 20, count 0 2006.201.10:29:05.88#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:29:05.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:29:05.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:29:05.88#ibcon#*before write, iclass 20, count 0 2006.201.10:29:05.88#ibcon#enter sib2, iclass 20, count 0 2006.201.10:29:05.88#ibcon#flushed, iclass 20, count 0 2006.201.10:29:05.88#ibcon#about to write, iclass 20, count 0 2006.201.10:29:05.88#ibcon#wrote, iclass 20, count 0 2006.201.10:29:05.88#ibcon#about to read 3, iclass 20, count 0 2006.201.10:29:05.93#ibcon#read 3, iclass 20, count 0 2006.201.10:29:05.93#ibcon#about to read 4, iclass 20, count 0 2006.201.10:29:05.93#ibcon#read 4, iclass 20, count 0 2006.201.10:29:05.93#ibcon#about to read 5, iclass 20, count 0 2006.201.10:29:05.93#ibcon#read 5, iclass 20, count 0 2006.201.10:29:05.93#ibcon#about to read 6, iclass 20, count 0 2006.201.10:29:05.93#ibcon#read 6, iclass 20, count 0 2006.201.10:29:05.93#ibcon#end of sib2, iclass 20, count 0 2006.201.10:29:05.93#ibcon#*after write, iclass 20, count 0 2006.201.10:29:05.93#ibcon#*before return 0, iclass 20, count 0 2006.201.10:29:05.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:05.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:05.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:29:05.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:29:05.93$vck44/va=4,7 2006.201.10:29:05.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.10:29:05.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.10:29:05.93#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:05.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:05.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:05.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:05.98#ibcon#enter wrdev, iclass 22, count 2 2006.201.10:29:05.98#ibcon#first serial, iclass 22, count 2 2006.201.10:29:05.98#ibcon#enter sib2, iclass 22, count 2 2006.201.10:29:05.98#ibcon#flushed, iclass 22, count 2 2006.201.10:29:05.98#ibcon#about to write, iclass 22, count 2 2006.201.10:29:05.98#ibcon#wrote, iclass 22, count 2 2006.201.10:29:05.98#ibcon#about to read 3, iclass 22, count 2 2006.201.10:29:06.00#ibcon#read 3, iclass 22, count 2 2006.201.10:29:06.00#ibcon#about to read 4, iclass 22, count 2 2006.201.10:29:06.00#ibcon#read 4, iclass 22, count 2 2006.201.10:29:06.00#ibcon#about to read 5, iclass 22, count 2 2006.201.10:29:06.00#ibcon#read 5, iclass 22, count 2 2006.201.10:29:06.00#ibcon#about to read 6, iclass 22, count 2 2006.201.10:29:06.00#ibcon#read 6, iclass 22, count 2 2006.201.10:29:06.00#ibcon#end of sib2, iclass 22, count 2 2006.201.10:29:06.00#ibcon#*mode == 0, iclass 22, count 2 2006.201.10:29:06.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.10:29:06.00#ibcon#[25=AT04-07\r\n] 2006.201.10:29:06.00#ibcon#*before write, iclass 22, count 2 2006.201.10:29:06.00#ibcon#enter sib2, iclass 22, count 2 2006.201.10:29:06.00#ibcon#flushed, iclass 22, count 2 2006.201.10:29:06.00#ibcon#about to write, iclass 22, count 2 2006.201.10:29:06.00#ibcon#wrote, iclass 22, count 2 2006.201.10:29:06.00#ibcon#about to read 3, iclass 22, count 2 2006.201.10:29:06.03#ibcon#read 3, iclass 22, count 2 2006.201.10:29:06.03#ibcon#about to read 4, iclass 22, count 2 2006.201.10:29:06.03#ibcon#read 4, iclass 22, count 2 2006.201.10:29:06.03#ibcon#about to read 5, iclass 22, count 2 2006.201.10:29:06.03#ibcon#read 5, iclass 22, count 2 2006.201.10:29:06.03#ibcon#about to read 6, iclass 22, count 2 2006.201.10:29:06.03#ibcon#read 6, iclass 22, count 2 2006.201.10:29:06.03#ibcon#end of sib2, iclass 22, count 2 2006.201.10:29:06.03#ibcon#*after write, iclass 22, count 2 2006.201.10:29:06.03#ibcon#*before return 0, iclass 22, count 2 2006.201.10:29:06.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:06.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:06.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.10:29:06.03#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:06.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:06.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:06.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:06.15#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:29:06.15#ibcon#first serial, iclass 22, count 0 2006.201.10:29:06.15#ibcon#enter sib2, iclass 22, count 0 2006.201.10:29:06.15#ibcon#flushed, iclass 22, count 0 2006.201.10:29:06.15#ibcon#about to write, iclass 22, count 0 2006.201.10:29:06.15#ibcon#wrote, iclass 22, count 0 2006.201.10:29:06.15#ibcon#about to read 3, iclass 22, count 0 2006.201.10:29:06.17#ibcon#read 3, iclass 22, count 0 2006.201.10:29:06.17#ibcon#about to read 4, iclass 22, count 0 2006.201.10:29:06.17#ibcon#read 4, iclass 22, count 0 2006.201.10:29:06.17#ibcon#about to read 5, iclass 22, count 0 2006.201.10:29:06.17#ibcon#read 5, iclass 22, count 0 2006.201.10:29:06.17#ibcon#about to read 6, iclass 22, count 0 2006.201.10:29:06.17#ibcon#read 6, iclass 22, count 0 2006.201.10:29:06.17#ibcon#end of sib2, iclass 22, count 0 2006.201.10:29:06.17#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:29:06.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:29:06.17#ibcon#[25=USB\r\n] 2006.201.10:29:06.17#ibcon#*before write, iclass 22, count 0 2006.201.10:29:06.17#ibcon#enter sib2, iclass 22, count 0 2006.201.10:29:06.17#ibcon#flushed, iclass 22, count 0 2006.201.10:29:06.17#ibcon#about to write, iclass 22, count 0 2006.201.10:29:06.17#ibcon#wrote, iclass 22, count 0 2006.201.10:29:06.17#ibcon#about to read 3, iclass 22, count 0 2006.201.10:29:06.20#ibcon#read 3, iclass 22, count 0 2006.201.10:29:06.20#ibcon#about to read 4, iclass 22, count 0 2006.201.10:29:06.20#ibcon#read 4, iclass 22, count 0 2006.201.10:29:06.20#ibcon#about to read 5, iclass 22, count 0 2006.201.10:29:06.20#ibcon#read 5, iclass 22, count 0 2006.201.10:29:06.20#ibcon#about to read 6, iclass 22, count 0 2006.201.10:29:06.20#ibcon#read 6, iclass 22, count 0 2006.201.10:29:06.20#ibcon#end of sib2, iclass 22, count 0 2006.201.10:29:06.20#ibcon#*after write, iclass 22, count 0 2006.201.10:29:06.20#ibcon#*before return 0, iclass 22, count 0 2006.201.10:29:06.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:06.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:06.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:29:06.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:29:06.20$vck44/valo=5,734.99 2006.201.10:29:06.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.10:29:06.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.10:29:06.20#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:06.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:06.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:06.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:06.20#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:29:06.20#ibcon#first serial, iclass 24, count 0 2006.201.10:29:06.20#ibcon#enter sib2, iclass 24, count 0 2006.201.10:29:06.20#ibcon#flushed, iclass 24, count 0 2006.201.10:29:06.20#ibcon#about to write, iclass 24, count 0 2006.201.10:29:06.20#ibcon#wrote, iclass 24, count 0 2006.201.10:29:06.20#ibcon#about to read 3, iclass 24, count 0 2006.201.10:29:06.22#ibcon#read 3, iclass 24, count 0 2006.201.10:29:06.22#ibcon#about to read 4, iclass 24, count 0 2006.201.10:29:06.22#ibcon#read 4, iclass 24, count 0 2006.201.10:29:06.22#ibcon#about to read 5, iclass 24, count 0 2006.201.10:29:06.22#ibcon#read 5, iclass 24, count 0 2006.201.10:29:06.22#ibcon#about to read 6, iclass 24, count 0 2006.201.10:29:06.22#ibcon#read 6, iclass 24, count 0 2006.201.10:29:06.22#ibcon#end of sib2, iclass 24, count 0 2006.201.10:29:06.22#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:29:06.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:29:06.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:29:06.22#ibcon#*before write, iclass 24, count 0 2006.201.10:29:06.22#ibcon#enter sib2, iclass 24, count 0 2006.201.10:29:06.22#ibcon#flushed, iclass 24, count 0 2006.201.10:29:06.22#ibcon#about to write, iclass 24, count 0 2006.201.10:29:06.22#ibcon#wrote, iclass 24, count 0 2006.201.10:29:06.22#ibcon#about to read 3, iclass 24, count 0 2006.201.10:29:06.26#ibcon#read 3, iclass 24, count 0 2006.201.10:29:06.26#ibcon#about to read 4, iclass 24, count 0 2006.201.10:29:06.26#ibcon#read 4, iclass 24, count 0 2006.201.10:29:06.26#ibcon#about to read 5, iclass 24, count 0 2006.201.10:29:06.26#ibcon#read 5, iclass 24, count 0 2006.201.10:29:06.26#ibcon#about to read 6, iclass 24, count 0 2006.201.10:29:06.26#ibcon#read 6, iclass 24, count 0 2006.201.10:29:06.26#ibcon#end of sib2, iclass 24, count 0 2006.201.10:29:06.26#ibcon#*after write, iclass 24, count 0 2006.201.10:29:06.26#ibcon#*before return 0, iclass 24, count 0 2006.201.10:29:06.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:06.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:06.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:29:06.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:29:06.26$vck44/va=5,4 2006.201.10:29:06.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.10:29:06.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.10:29:06.26#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:06.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:06.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:06.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:06.32#ibcon#enter wrdev, iclass 26, count 2 2006.201.10:29:06.32#ibcon#first serial, iclass 26, count 2 2006.201.10:29:06.32#ibcon#enter sib2, iclass 26, count 2 2006.201.10:29:06.32#ibcon#flushed, iclass 26, count 2 2006.201.10:29:06.32#ibcon#about to write, iclass 26, count 2 2006.201.10:29:06.32#ibcon#wrote, iclass 26, count 2 2006.201.10:29:06.32#ibcon#about to read 3, iclass 26, count 2 2006.201.10:29:06.34#ibcon#read 3, iclass 26, count 2 2006.201.10:29:06.34#ibcon#about to read 4, iclass 26, count 2 2006.201.10:29:06.34#ibcon#read 4, iclass 26, count 2 2006.201.10:29:06.34#ibcon#about to read 5, iclass 26, count 2 2006.201.10:29:06.34#ibcon#read 5, iclass 26, count 2 2006.201.10:29:06.34#ibcon#about to read 6, iclass 26, count 2 2006.201.10:29:06.34#ibcon#read 6, iclass 26, count 2 2006.201.10:29:06.34#ibcon#end of sib2, iclass 26, count 2 2006.201.10:29:06.34#ibcon#*mode == 0, iclass 26, count 2 2006.201.10:29:06.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.10:29:06.34#ibcon#[25=AT05-04\r\n] 2006.201.10:29:06.34#ibcon#*before write, iclass 26, count 2 2006.201.10:29:06.34#ibcon#enter sib2, iclass 26, count 2 2006.201.10:29:06.34#ibcon#flushed, iclass 26, count 2 2006.201.10:29:06.34#ibcon#about to write, iclass 26, count 2 2006.201.10:29:06.34#ibcon#wrote, iclass 26, count 2 2006.201.10:29:06.34#ibcon#about to read 3, iclass 26, count 2 2006.201.10:29:06.37#ibcon#read 3, iclass 26, count 2 2006.201.10:29:06.37#ibcon#about to read 4, iclass 26, count 2 2006.201.10:29:06.37#ibcon#read 4, iclass 26, count 2 2006.201.10:29:06.37#ibcon#about to read 5, iclass 26, count 2 2006.201.10:29:06.37#ibcon#read 5, iclass 26, count 2 2006.201.10:29:06.37#ibcon#about to read 6, iclass 26, count 2 2006.201.10:29:06.37#ibcon#read 6, iclass 26, count 2 2006.201.10:29:06.37#ibcon#end of sib2, iclass 26, count 2 2006.201.10:29:06.37#ibcon#*after write, iclass 26, count 2 2006.201.10:29:06.37#ibcon#*before return 0, iclass 26, count 2 2006.201.10:29:06.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:06.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:06.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.10:29:06.37#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:06.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:06.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:06.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:06.49#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:29:06.49#ibcon#first serial, iclass 26, count 0 2006.201.10:29:06.49#ibcon#enter sib2, iclass 26, count 0 2006.201.10:29:06.49#ibcon#flushed, iclass 26, count 0 2006.201.10:29:06.49#ibcon#about to write, iclass 26, count 0 2006.201.10:29:06.49#ibcon#wrote, iclass 26, count 0 2006.201.10:29:06.49#ibcon#about to read 3, iclass 26, count 0 2006.201.10:29:06.51#ibcon#read 3, iclass 26, count 0 2006.201.10:29:06.51#ibcon#about to read 4, iclass 26, count 0 2006.201.10:29:06.51#ibcon#read 4, iclass 26, count 0 2006.201.10:29:06.51#ibcon#about to read 5, iclass 26, count 0 2006.201.10:29:06.51#ibcon#read 5, iclass 26, count 0 2006.201.10:29:06.51#ibcon#about to read 6, iclass 26, count 0 2006.201.10:29:06.51#ibcon#read 6, iclass 26, count 0 2006.201.10:29:06.51#ibcon#end of sib2, iclass 26, count 0 2006.201.10:29:06.51#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:29:06.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:29:06.51#ibcon#[25=USB\r\n] 2006.201.10:29:06.51#ibcon#*before write, iclass 26, count 0 2006.201.10:29:06.51#ibcon#enter sib2, iclass 26, count 0 2006.201.10:29:06.51#ibcon#flushed, iclass 26, count 0 2006.201.10:29:06.51#ibcon#about to write, iclass 26, count 0 2006.201.10:29:06.51#ibcon#wrote, iclass 26, count 0 2006.201.10:29:06.51#ibcon#about to read 3, iclass 26, count 0 2006.201.10:29:06.54#ibcon#read 3, iclass 26, count 0 2006.201.10:29:06.54#ibcon#about to read 4, iclass 26, count 0 2006.201.10:29:06.54#ibcon#read 4, iclass 26, count 0 2006.201.10:29:06.54#ibcon#about to read 5, iclass 26, count 0 2006.201.10:29:06.54#ibcon#read 5, iclass 26, count 0 2006.201.10:29:06.54#ibcon#about to read 6, iclass 26, count 0 2006.201.10:29:06.54#ibcon#read 6, iclass 26, count 0 2006.201.10:29:06.54#ibcon#end of sib2, iclass 26, count 0 2006.201.10:29:06.54#ibcon#*after write, iclass 26, count 0 2006.201.10:29:06.54#ibcon#*before return 0, iclass 26, count 0 2006.201.10:29:06.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:06.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:06.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:29:06.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:29:06.54$vck44/valo=6,814.99 2006.201.10:29:06.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.10:29:06.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.10:29:06.54#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:06.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:06.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:06.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:06.54#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:29:06.54#ibcon#first serial, iclass 28, count 0 2006.201.10:29:06.54#ibcon#enter sib2, iclass 28, count 0 2006.201.10:29:06.54#ibcon#flushed, iclass 28, count 0 2006.201.10:29:06.54#ibcon#about to write, iclass 28, count 0 2006.201.10:29:06.54#ibcon#wrote, iclass 28, count 0 2006.201.10:29:06.54#ibcon#about to read 3, iclass 28, count 0 2006.201.10:29:06.56#ibcon#read 3, iclass 28, count 0 2006.201.10:29:06.56#ibcon#about to read 4, iclass 28, count 0 2006.201.10:29:06.56#ibcon#read 4, iclass 28, count 0 2006.201.10:29:06.56#ibcon#about to read 5, iclass 28, count 0 2006.201.10:29:06.56#ibcon#read 5, iclass 28, count 0 2006.201.10:29:06.56#ibcon#about to read 6, iclass 28, count 0 2006.201.10:29:06.56#ibcon#read 6, iclass 28, count 0 2006.201.10:29:06.56#ibcon#end of sib2, iclass 28, count 0 2006.201.10:29:06.56#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:29:06.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:29:06.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:29:06.56#ibcon#*before write, iclass 28, count 0 2006.201.10:29:06.56#ibcon#enter sib2, iclass 28, count 0 2006.201.10:29:06.56#ibcon#flushed, iclass 28, count 0 2006.201.10:29:06.56#ibcon#about to write, iclass 28, count 0 2006.201.10:29:06.56#ibcon#wrote, iclass 28, count 0 2006.201.10:29:06.56#ibcon#about to read 3, iclass 28, count 0 2006.201.10:29:06.60#ibcon#read 3, iclass 28, count 0 2006.201.10:29:06.60#ibcon#about to read 4, iclass 28, count 0 2006.201.10:29:06.60#ibcon#read 4, iclass 28, count 0 2006.201.10:29:06.60#ibcon#about to read 5, iclass 28, count 0 2006.201.10:29:06.60#ibcon#read 5, iclass 28, count 0 2006.201.10:29:06.60#ibcon#about to read 6, iclass 28, count 0 2006.201.10:29:06.60#ibcon#read 6, iclass 28, count 0 2006.201.10:29:06.60#ibcon#end of sib2, iclass 28, count 0 2006.201.10:29:06.60#ibcon#*after write, iclass 28, count 0 2006.201.10:29:06.60#ibcon#*before return 0, iclass 28, count 0 2006.201.10:29:06.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:06.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:06.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:29:06.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:29:06.60$vck44/va=6,5 2006.201.10:29:06.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.10:29:06.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.10:29:06.60#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:06.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:06.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:06.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:06.66#ibcon#enter wrdev, iclass 30, count 2 2006.201.10:29:06.66#ibcon#first serial, iclass 30, count 2 2006.201.10:29:06.66#ibcon#enter sib2, iclass 30, count 2 2006.201.10:29:06.66#ibcon#flushed, iclass 30, count 2 2006.201.10:29:06.66#ibcon#about to write, iclass 30, count 2 2006.201.10:29:06.66#ibcon#wrote, iclass 30, count 2 2006.201.10:29:06.66#ibcon#about to read 3, iclass 30, count 2 2006.201.10:29:06.68#ibcon#read 3, iclass 30, count 2 2006.201.10:29:06.68#ibcon#about to read 4, iclass 30, count 2 2006.201.10:29:06.68#ibcon#read 4, iclass 30, count 2 2006.201.10:29:06.68#ibcon#about to read 5, iclass 30, count 2 2006.201.10:29:06.68#ibcon#read 5, iclass 30, count 2 2006.201.10:29:06.68#ibcon#about to read 6, iclass 30, count 2 2006.201.10:29:06.68#ibcon#read 6, iclass 30, count 2 2006.201.10:29:06.68#ibcon#end of sib2, iclass 30, count 2 2006.201.10:29:06.68#ibcon#*mode == 0, iclass 30, count 2 2006.201.10:29:06.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.10:29:06.68#ibcon#[25=AT06-05\r\n] 2006.201.10:29:06.68#ibcon#*before write, iclass 30, count 2 2006.201.10:29:06.68#ibcon#enter sib2, iclass 30, count 2 2006.201.10:29:06.68#ibcon#flushed, iclass 30, count 2 2006.201.10:29:06.68#ibcon#about to write, iclass 30, count 2 2006.201.10:29:06.68#ibcon#wrote, iclass 30, count 2 2006.201.10:29:06.68#ibcon#about to read 3, iclass 30, count 2 2006.201.10:29:06.71#ibcon#read 3, iclass 30, count 2 2006.201.10:29:06.71#ibcon#about to read 4, iclass 30, count 2 2006.201.10:29:06.71#ibcon#read 4, iclass 30, count 2 2006.201.10:29:06.71#ibcon#about to read 5, iclass 30, count 2 2006.201.10:29:06.71#ibcon#read 5, iclass 30, count 2 2006.201.10:29:06.71#ibcon#about to read 6, iclass 30, count 2 2006.201.10:29:06.71#ibcon#read 6, iclass 30, count 2 2006.201.10:29:06.71#ibcon#end of sib2, iclass 30, count 2 2006.201.10:29:06.71#ibcon#*after write, iclass 30, count 2 2006.201.10:29:06.71#ibcon#*before return 0, iclass 30, count 2 2006.201.10:29:06.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:06.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:06.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.10:29:06.71#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:06.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:06.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:06.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:06.83#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:29:06.83#ibcon#first serial, iclass 30, count 0 2006.201.10:29:06.83#ibcon#enter sib2, iclass 30, count 0 2006.201.10:29:06.83#ibcon#flushed, iclass 30, count 0 2006.201.10:29:06.83#ibcon#about to write, iclass 30, count 0 2006.201.10:29:06.83#ibcon#wrote, iclass 30, count 0 2006.201.10:29:06.83#ibcon#about to read 3, iclass 30, count 0 2006.201.10:29:06.85#ibcon#read 3, iclass 30, count 0 2006.201.10:29:06.85#ibcon#about to read 4, iclass 30, count 0 2006.201.10:29:06.85#ibcon#read 4, iclass 30, count 0 2006.201.10:29:06.85#ibcon#about to read 5, iclass 30, count 0 2006.201.10:29:06.85#ibcon#read 5, iclass 30, count 0 2006.201.10:29:06.85#ibcon#about to read 6, iclass 30, count 0 2006.201.10:29:06.85#ibcon#read 6, iclass 30, count 0 2006.201.10:29:06.85#ibcon#end of sib2, iclass 30, count 0 2006.201.10:29:06.85#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:29:06.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:29:06.85#ibcon#[25=USB\r\n] 2006.201.10:29:06.85#ibcon#*before write, iclass 30, count 0 2006.201.10:29:06.85#ibcon#enter sib2, iclass 30, count 0 2006.201.10:29:06.85#ibcon#flushed, iclass 30, count 0 2006.201.10:29:06.85#ibcon#about to write, iclass 30, count 0 2006.201.10:29:06.85#ibcon#wrote, iclass 30, count 0 2006.201.10:29:06.85#ibcon#about to read 3, iclass 30, count 0 2006.201.10:29:06.88#ibcon#read 3, iclass 30, count 0 2006.201.10:29:06.88#ibcon#about to read 4, iclass 30, count 0 2006.201.10:29:06.88#ibcon#read 4, iclass 30, count 0 2006.201.10:29:06.88#ibcon#about to read 5, iclass 30, count 0 2006.201.10:29:06.88#ibcon#read 5, iclass 30, count 0 2006.201.10:29:06.88#ibcon#about to read 6, iclass 30, count 0 2006.201.10:29:06.88#ibcon#read 6, iclass 30, count 0 2006.201.10:29:06.88#ibcon#end of sib2, iclass 30, count 0 2006.201.10:29:06.88#ibcon#*after write, iclass 30, count 0 2006.201.10:29:06.88#ibcon#*before return 0, iclass 30, count 0 2006.201.10:29:06.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:06.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:06.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:29:06.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:29:06.88$vck44/valo=7,864.99 2006.201.10:29:06.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.10:29:06.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.10:29:06.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:06.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:06.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:06.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:06.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:29:06.88#ibcon#first serial, iclass 32, count 0 2006.201.10:29:06.88#ibcon#enter sib2, iclass 32, count 0 2006.201.10:29:06.88#ibcon#flushed, iclass 32, count 0 2006.201.10:29:06.88#ibcon#about to write, iclass 32, count 0 2006.201.10:29:06.88#ibcon#wrote, iclass 32, count 0 2006.201.10:29:06.88#ibcon#about to read 3, iclass 32, count 0 2006.201.10:29:06.90#ibcon#read 3, iclass 32, count 0 2006.201.10:29:06.90#ibcon#about to read 4, iclass 32, count 0 2006.201.10:29:06.90#ibcon#read 4, iclass 32, count 0 2006.201.10:29:06.90#ibcon#about to read 5, iclass 32, count 0 2006.201.10:29:06.90#ibcon#read 5, iclass 32, count 0 2006.201.10:29:06.90#ibcon#about to read 6, iclass 32, count 0 2006.201.10:29:06.90#ibcon#read 6, iclass 32, count 0 2006.201.10:29:06.90#ibcon#end of sib2, iclass 32, count 0 2006.201.10:29:06.90#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:29:06.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:29:06.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:29:06.90#ibcon#*before write, iclass 32, count 0 2006.201.10:29:06.90#ibcon#enter sib2, iclass 32, count 0 2006.201.10:29:06.90#ibcon#flushed, iclass 32, count 0 2006.201.10:29:06.90#ibcon#about to write, iclass 32, count 0 2006.201.10:29:06.90#ibcon#wrote, iclass 32, count 0 2006.201.10:29:06.90#ibcon#about to read 3, iclass 32, count 0 2006.201.10:29:06.95#ibcon#read 3, iclass 32, count 0 2006.201.10:29:06.95#ibcon#about to read 4, iclass 32, count 0 2006.201.10:29:06.95#ibcon#read 4, iclass 32, count 0 2006.201.10:29:06.95#ibcon#about to read 5, iclass 32, count 0 2006.201.10:29:06.95#ibcon#read 5, iclass 32, count 0 2006.201.10:29:06.95#ibcon#about to read 6, iclass 32, count 0 2006.201.10:29:06.95#ibcon#read 6, iclass 32, count 0 2006.201.10:29:06.95#ibcon#end of sib2, iclass 32, count 0 2006.201.10:29:06.95#ibcon#*after write, iclass 32, count 0 2006.201.10:29:06.95#ibcon#*before return 0, iclass 32, count 0 2006.201.10:29:06.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:06.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:06.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:29:06.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:29:06.95$vck44/va=7,5 2006.201.10:29:06.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.10:29:06.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.10:29:06.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:06.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:07.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:07.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:07.00#ibcon#enter wrdev, iclass 34, count 2 2006.201.10:29:07.00#ibcon#first serial, iclass 34, count 2 2006.201.10:29:07.00#ibcon#enter sib2, iclass 34, count 2 2006.201.10:29:07.00#ibcon#flushed, iclass 34, count 2 2006.201.10:29:07.00#ibcon#about to write, iclass 34, count 2 2006.201.10:29:07.00#ibcon#wrote, iclass 34, count 2 2006.201.10:29:07.00#ibcon#about to read 3, iclass 34, count 2 2006.201.10:29:07.02#ibcon#read 3, iclass 34, count 2 2006.201.10:29:07.02#ibcon#about to read 4, iclass 34, count 2 2006.201.10:29:07.02#ibcon#read 4, iclass 34, count 2 2006.201.10:29:07.02#ibcon#about to read 5, iclass 34, count 2 2006.201.10:29:07.02#ibcon#read 5, iclass 34, count 2 2006.201.10:29:07.02#ibcon#about to read 6, iclass 34, count 2 2006.201.10:29:07.02#ibcon#read 6, iclass 34, count 2 2006.201.10:29:07.02#ibcon#end of sib2, iclass 34, count 2 2006.201.10:29:07.02#ibcon#*mode == 0, iclass 34, count 2 2006.201.10:29:07.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.10:29:07.02#ibcon#[25=AT07-05\r\n] 2006.201.10:29:07.02#ibcon#*before write, iclass 34, count 2 2006.201.10:29:07.02#ibcon#enter sib2, iclass 34, count 2 2006.201.10:29:07.02#ibcon#flushed, iclass 34, count 2 2006.201.10:29:07.02#ibcon#about to write, iclass 34, count 2 2006.201.10:29:07.02#ibcon#wrote, iclass 34, count 2 2006.201.10:29:07.02#ibcon#about to read 3, iclass 34, count 2 2006.201.10:29:07.05#ibcon#read 3, iclass 34, count 2 2006.201.10:29:07.05#ibcon#about to read 4, iclass 34, count 2 2006.201.10:29:07.05#ibcon#read 4, iclass 34, count 2 2006.201.10:29:07.05#ibcon#about to read 5, iclass 34, count 2 2006.201.10:29:07.05#ibcon#read 5, iclass 34, count 2 2006.201.10:29:07.05#ibcon#about to read 6, iclass 34, count 2 2006.201.10:29:07.05#ibcon#read 6, iclass 34, count 2 2006.201.10:29:07.05#ibcon#end of sib2, iclass 34, count 2 2006.201.10:29:07.05#ibcon#*after write, iclass 34, count 2 2006.201.10:29:07.05#ibcon#*before return 0, iclass 34, count 2 2006.201.10:29:07.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:07.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:07.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.10:29:07.05#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:07.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:07.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:07.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:07.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:29:07.17#ibcon#first serial, iclass 34, count 0 2006.201.10:29:07.17#ibcon#enter sib2, iclass 34, count 0 2006.201.10:29:07.17#ibcon#flushed, iclass 34, count 0 2006.201.10:29:07.17#ibcon#about to write, iclass 34, count 0 2006.201.10:29:07.17#ibcon#wrote, iclass 34, count 0 2006.201.10:29:07.17#ibcon#about to read 3, iclass 34, count 0 2006.201.10:29:07.19#ibcon#read 3, iclass 34, count 0 2006.201.10:29:07.19#ibcon#about to read 4, iclass 34, count 0 2006.201.10:29:07.19#ibcon#read 4, iclass 34, count 0 2006.201.10:29:07.19#ibcon#about to read 5, iclass 34, count 0 2006.201.10:29:07.19#ibcon#read 5, iclass 34, count 0 2006.201.10:29:07.19#ibcon#about to read 6, iclass 34, count 0 2006.201.10:29:07.19#ibcon#read 6, iclass 34, count 0 2006.201.10:29:07.19#ibcon#end of sib2, iclass 34, count 0 2006.201.10:29:07.19#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:29:07.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:29:07.19#ibcon#[25=USB\r\n] 2006.201.10:29:07.19#ibcon#*before write, iclass 34, count 0 2006.201.10:29:07.19#ibcon#enter sib2, iclass 34, count 0 2006.201.10:29:07.19#ibcon#flushed, iclass 34, count 0 2006.201.10:29:07.19#ibcon#about to write, iclass 34, count 0 2006.201.10:29:07.19#ibcon#wrote, iclass 34, count 0 2006.201.10:29:07.19#ibcon#about to read 3, iclass 34, count 0 2006.201.10:29:07.22#ibcon#read 3, iclass 34, count 0 2006.201.10:29:07.22#ibcon#about to read 4, iclass 34, count 0 2006.201.10:29:07.22#ibcon#read 4, iclass 34, count 0 2006.201.10:29:07.22#ibcon#about to read 5, iclass 34, count 0 2006.201.10:29:07.22#ibcon#read 5, iclass 34, count 0 2006.201.10:29:07.22#ibcon#about to read 6, iclass 34, count 0 2006.201.10:29:07.22#ibcon#read 6, iclass 34, count 0 2006.201.10:29:07.22#ibcon#end of sib2, iclass 34, count 0 2006.201.10:29:07.22#ibcon#*after write, iclass 34, count 0 2006.201.10:29:07.22#ibcon#*before return 0, iclass 34, count 0 2006.201.10:29:07.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:07.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:07.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:29:07.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:29:07.22$vck44/valo=8,884.99 2006.201.10:29:07.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.10:29:07.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.10:29:07.22#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:07.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:29:07.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:29:07.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:29:07.22#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:29:07.22#ibcon#first serial, iclass 37, count 0 2006.201.10:29:07.22#ibcon#enter sib2, iclass 37, count 0 2006.201.10:29:07.22#ibcon#flushed, iclass 37, count 0 2006.201.10:29:07.22#ibcon#about to write, iclass 37, count 0 2006.201.10:29:07.22#ibcon#wrote, iclass 37, count 0 2006.201.10:29:07.22#ibcon#about to read 3, iclass 37, count 0 2006.201.10:29:07.23#abcon#<5=/05 2.1 3.6 21.74 971003.6\r\n> 2006.201.10:29:07.24#ibcon#read 3, iclass 37, count 0 2006.201.10:29:07.24#ibcon#about to read 4, iclass 37, count 0 2006.201.10:29:07.24#ibcon#read 4, iclass 37, count 0 2006.201.10:29:07.24#ibcon#about to read 5, iclass 37, count 0 2006.201.10:29:07.24#ibcon#read 5, iclass 37, count 0 2006.201.10:29:07.24#ibcon#about to read 6, iclass 37, count 0 2006.201.10:29:07.24#ibcon#read 6, iclass 37, count 0 2006.201.10:29:07.24#ibcon#end of sib2, iclass 37, count 0 2006.201.10:29:07.24#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:29:07.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:29:07.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:29:07.24#ibcon#*before write, iclass 37, count 0 2006.201.10:29:07.24#ibcon#enter sib2, iclass 37, count 0 2006.201.10:29:07.24#ibcon#flushed, iclass 37, count 0 2006.201.10:29:07.24#ibcon#about to write, iclass 37, count 0 2006.201.10:29:07.24#ibcon#wrote, iclass 37, count 0 2006.201.10:29:07.24#ibcon#about to read 3, iclass 37, count 0 2006.201.10:29:07.25#abcon#{5=INTERFACE CLEAR} 2006.201.10:29:07.28#ibcon#read 3, iclass 37, count 0 2006.201.10:29:07.28#ibcon#about to read 4, iclass 37, count 0 2006.201.10:29:07.28#ibcon#read 4, iclass 37, count 0 2006.201.10:29:07.28#ibcon#about to read 5, iclass 37, count 0 2006.201.10:29:07.28#ibcon#read 5, iclass 37, count 0 2006.201.10:29:07.28#ibcon#about to read 6, iclass 37, count 0 2006.201.10:29:07.28#ibcon#read 6, iclass 37, count 0 2006.201.10:29:07.28#ibcon#end of sib2, iclass 37, count 0 2006.201.10:29:07.28#ibcon#*after write, iclass 37, count 0 2006.201.10:29:07.28#ibcon#*before return 0, iclass 37, count 0 2006.201.10:29:07.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:29:07.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:29:07.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:29:07.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:29:07.28$vck44/va=8,4 2006.201.10:29:07.28#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.10:29:07.28#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.10:29:07.28#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:07.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:29:07.31#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:29:07.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:29:07.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:29:07.34#ibcon#enter wrdev, iclass 2, count 2 2006.201.10:29:07.34#ibcon#first serial, iclass 2, count 2 2006.201.10:29:07.34#ibcon#enter sib2, iclass 2, count 2 2006.201.10:29:07.34#ibcon#flushed, iclass 2, count 2 2006.201.10:29:07.34#ibcon#about to write, iclass 2, count 2 2006.201.10:29:07.34#ibcon#wrote, iclass 2, count 2 2006.201.10:29:07.34#ibcon#about to read 3, iclass 2, count 2 2006.201.10:29:07.36#ibcon#read 3, iclass 2, count 2 2006.201.10:29:07.36#ibcon#about to read 4, iclass 2, count 2 2006.201.10:29:07.36#ibcon#read 4, iclass 2, count 2 2006.201.10:29:07.36#ibcon#about to read 5, iclass 2, count 2 2006.201.10:29:07.36#ibcon#read 5, iclass 2, count 2 2006.201.10:29:07.36#ibcon#about to read 6, iclass 2, count 2 2006.201.10:29:07.36#ibcon#read 6, iclass 2, count 2 2006.201.10:29:07.36#ibcon#end of sib2, iclass 2, count 2 2006.201.10:29:07.36#ibcon#*mode == 0, iclass 2, count 2 2006.201.10:29:07.36#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.10:29:07.36#ibcon#[25=AT08-04\r\n] 2006.201.10:29:07.36#ibcon#*before write, iclass 2, count 2 2006.201.10:29:07.36#ibcon#enter sib2, iclass 2, count 2 2006.201.10:29:07.36#ibcon#flushed, iclass 2, count 2 2006.201.10:29:07.36#ibcon#about to write, iclass 2, count 2 2006.201.10:29:07.36#ibcon#wrote, iclass 2, count 2 2006.201.10:29:07.36#ibcon#about to read 3, iclass 2, count 2 2006.201.10:29:07.39#ibcon#read 3, iclass 2, count 2 2006.201.10:29:07.39#ibcon#about to read 4, iclass 2, count 2 2006.201.10:29:07.39#ibcon#read 4, iclass 2, count 2 2006.201.10:29:07.39#ibcon#about to read 5, iclass 2, count 2 2006.201.10:29:07.39#ibcon#read 5, iclass 2, count 2 2006.201.10:29:07.39#ibcon#about to read 6, iclass 2, count 2 2006.201.10:29:07.39#ibcon#read 6, iclass 2, count 2 2006.201.10:29:07.39#ibcon#end of sib2, iclass 2, count 2 2006.201.10:29:07.39#ibcon#*after write, iclass 2, count 2 2006.201.10:29:07.39#ibcon#*before return 0, iclass 2, count 2 2006.201.10:29:07.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:29:07.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:29:07.39#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.10:29:07.39#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:07.39#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:29:07.51#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:29:07.51#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:29:07.51#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:29:07.51#ibcon#first serial, iclass 2, count 0 2006.201.10:29:07.51#ibcon#enter sib2, iclass 2, count 0 2006.201.10:29:07.51#ibcon#flushed, iclass 2, count 0 2006.201.10:29:07.51#ibcon#about to write, iclass 2, count 0 2006.201.10:29:07.51#ibcon#wrote, iclass 2, count 0 2006.201.10:29:07.51#ibcon#about to read 3, iclass 2, count 0 2006.201.10:29:07.53#ibcon#read 3, iclass 2, count 0 2006.201.10:29:07.53#ibcon#about to read 4, iclass 2, count 0 2006.201.10:29:07.53#ibcon#read 4, iclass 2, count 0 2006.201.10:29:07.53#ibcon#about to read 5, iclass 2, count 0 2006.201.10:29:07.53#ibcon#read 5, iclass 2, count 0 2006.201.10:29:07.53#ibcon#about to read 6, iclass 2, count 0 2006.201.10:29:07.53#ibcon#read 6, iclass 2, count 0 2006.201.10:29:07.53#ibcon#end of sib2, iclass 2, count 0 2006.201.10:29:07.53#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:29:07.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:29:07.53#ibcon#[25=USB\r\n] 2006.201.10:29:07.53#ibcon#*before write, iclass 2, count 0 2006.201.10:29:07.53#ibcon#enter sib2, iclass 2, count 0 2006.201.10:29:07.53#ibcon#flushed, iclass 2, count 0 2006.201.10:29:07.53#ibcon#about to write, iclass 2, count 0 2006.201.10:29:07.53#ibcon#wrote, iclass 2, count 0 2006.201.10:29:07.53#ibcon#about to read 3, iclass 2, count 0 2006.201.10:29:07.56#ibcon#read 3, iclass 2, count 0 2006.201.10:29:07.56#ibcon#about to read 4, iclass 2, count 0 2006.201.10:29:07.56#ibcon#read 4, iclass 2, count 0 2006.201.10:29:07.56#ibcon#about to read 5, iclass 2, count 0 2006.201.10:29:07.56#ibcon#read 5, iclass 2, count 0 2006.201.10:29:07.56#ibcon#about to read 6, iclass 2, count 0 2006.201.10:29:07.56#ibcon#read 6, iclass 2, count 0 2006.201.10:29:07.56#ibcon#end of sib2, iclass 2, count 0 2006.201.10:29:07.56#ibcon#*after write, iclass 2, count 0 2006.201.10:29:07.56#ibcon#*before return 0, iclass 2, count 0 2006.201.10:29:07.56#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:29:07.56#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:29:07.56#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:29:07.56#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:29:07.56$vck44/vblo=1,629.99 2006.201.10:29:07.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.10:29:07.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.10:29:07.56#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:07.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:07.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:07.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:07.56#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:29:07.56#ibcon#first serial, iclass 6, count 0 2006.201.10:29:07.56#ibcon#enter sib2, iclass 6, count 0 2006.201.10:29:07.56#ibcon#flushed, iclass 6, count 0 2006.201.10:29:07.56#ibcon#about to write, iclass 6, count 0 2006.201.10:29:07.56#ibcon#wrote, iclass 6, count 0 2006.201.10:29:07.56#ibcon#about to read 3, iclass 6, count 0 2006.201.10:29:07.58#ibcon#read 3, iclass 6, count 0 2006.201.10:29:07.58#ibcon#about to read 4, iclass 6, count 0 2006.201.10:29:07.58#ibcon#read 4, iclass 6, count 0 2006.201.10:29:07.58#ibcon#about to read 5, iclass 6, count 0 2006.201.10:29:07.58#ibcon#read 5, iclass 6, count 0 2006.201.10:29:07.58#ibcon#about to read 6, iclass 6, count 0 2006.201.10:29:07.58#ibcon#read 6, iclass 6, count 0 2006.201.10:29:07.58#ibcon#end of sib2, iclass 6, count 0 2006.201.10:29:07.58#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:29:07.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:29:07.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:29:07.58#ibcon#*before write, iclass 6, count 0 2006.201.10:29:07.58#ibcon#enter sib2, iclass 6, count 0 2006.201.10:29:07.58#ibcon#flushed, iclass 6, count 0 2006.201.10:29:07.58#ibcon#about to write, iclass 6, count 0 2006.201.10:29:07.58#ibcon#wrote, iclass 6, count 0 2006.201.10:29:07.58#ibcon#about to read 3, iclass 6, count 0 2006.201.10:29:07.63#ibcon#read 3, iclass 6, count 0 2006.201.10:29:07.63#ibcon#about to read 4, iclass 6, count 0 2006.201.10:29:07.63#ibcon#read 4, iclass 6, count 0 2006.201.10:29:07.63#ibcon#about to read 5, iclass 6, count 0 2006.201.10:29:07.63#ibcon#read 5, iclass 6, count 0 2006.201.10:29:07.63#ibcon#about to read 6, iclass 6, count 0 2006.201.10:29:07.63#ibcon#read 6, iclass 6, count 0 2006.201.10:29:07.63#ibcon#end of sib2, iclass 6, count 0 2006.201.10:29:07.63#ibcon#*after write, iclass 6, count 0 2006.201.10:29:07.63#ibcon#*before return 0, iclass 6, count 0 2006.201.10:29:07.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:07.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:29:07.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:29:07.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:29:07.63$vck44/vb=1,4 2006.201.10:29:07.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.10:29:07.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.10:29:07.63#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:07.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:07.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:07.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:07.63#ibcon#enter wrdev, iclass 10, count 2 2006.201.10:29:07.63#ibcon#first serial, iclass 10, count 2 2006.201.10:29:07.63#ibcon#enter sib2, iclass 10, count 2 2006.201.10:29:07.63#ibcon#flushed, iclass 10, count 2 2006.201.10:29:07.63#ibcon#about to write, iclass 10, count 2 2006.201.10:29:07.63#ibcon#wrote, iclass 10, count 2 2006.201.10:29:07.63#ibcon#about to read 3, iclass 10, count 2 2006.201.10:29:07.65#ibcon#read 3, iclass 10, count 2 2006.201.10:29:07.65#ibcon#about to read 4, iclass 10, count 2 2006.201.10:29:07.65#ibcon#read 4, iclass 10, count 2 2006.201.10:29:07.65#ibcon#about to read 5, iclass 10, count 2 2006.201.10:29:07.65#ibcon#read 5, iclass 10, count 2 2006.201.10:29:07.65#ibcon#about to read 6, iclass 10, count 2 2006.201.10:29:07.65#ibcon#read 6, iclass 10, count 2 2006.201.10:29:07.65#ibcon#end of sib2, iclass 10, count 2 2006.201.10:29:07.65#ibcon#*mode == 0, iclass 10, count 2 2006.201.10:29:07.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.10:29:07.65#ibcon#[27=AT01-04\r\n] 2006.201.10:29:07.65#ibcon#*before write, iclass 10, count 2 2006.201.10:29:07.65#ibcon#enter sib2, iclass 10, count 2 2006.201.10:29:07.65#ibcon#flushed, iclass 10, count 2 2006.201.10:29:07.65#ibcon#about to write, iclass 10, count 2 2006.201.10:29:07.65#ibcon#wrote, iclass 10, count 2 2006.201.10:29:07.65#ibcon#about to read 3, iclass 10, count 2 2006.201.10:29:07.68#ibcon#read 3, iclass 10, count 2 2006.201.10:29:07.68#ibcon#about to read 4, iclass 10, count 2 2006.201.10:29:07.68#ibcon#read 4, iclass 10, count 2 2006.201.10:29:07.68#ibcon#about to read 5, iclass 10, count 2 2006.201.10:29:07.68#ibcon#read 5, iclass 10, count 2 2006.201.10:29:07.68#ibcon#about to read 6, iclass 10, count 2 2006.201.10:29:07.68#ibcon#read 6, iclass 10, count 2 2006.201.10:29:07.68#ibcon#end of sib2, iclass 10, count 2 2006.201.10:29:07.68#ibcon#*after write, iclass 10, count 2 2006.201.10:29:07.68#ibcon#*before return 0, iclass 10, count 2 2006.201.10:29:07.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:07.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:29:07.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.10:29:07.68#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:07.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:07.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:07.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:07.80#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:29:07.80#ibcon#first serial, iclass 10, count 0 2006.201.10:29:07.80#ibcon#enter sib2, iclass 10, count 0 2006.201.10:29:07.80#ibcon#flushed, iclass 10, count 0 2006.201.10:29:07.80#ibcon#about to write, iclass 10, count 0 2006.201.10:29:07.80#ibcon#wrote, iclass 10, count 0 2006.201.10:29:07.80#ibcon#about to read 3, iclass 10, count 0 2006.201.10:29:07.82#ibcon#read 3, iclass 10, count 0 2006.201.10:29:07.82#ibcon#about to read 4, iclass 10, count 0 2006.201.10:29:07.82#ibcon#read 4, iclass 10, count 0 2006.201.10:29:07.82#ibcon#about to read 5, iclass 10, count 0 2006.201.10:29:07.82#ibcon#read 5, iclass 10, count 0 2006.201.10:29:07.82#ibcon#about to read 6, iclass 10, count 0 2006.201.10:29:07.82#ibcon#read 6, iclass 10, count 0 2006.201.10:29:07.82#ibcon#end of sib2, iclass 10, count 0 2006.201.10:29:07.82#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:29:07.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:29:07.82#ibcon#[27=USB\r\n] 2006.201.10:29:07.82#ibcon#*before write, iclass 10, count 0 2006.201.10:29:07.82#ibcon#enter sib2, iclass 10, count 0 2006.201.10:29:07.82#ibcon#flushed, iclass 10, count 0 2006.201.10:29:07.82#ibcon#about to write, iclass 10, count 0 2006.201.10:29:07.82#ibcon#wrote, iclass 10, count 0 2006.201.10:29:07.82#ibcon#about to read 3, iclass 10, count 0 2006.201.10:29:07.85#ibcon#read 3, iclass 10, count 0 2006.201.10:29:07.85#ibcon#about to read 4, iclass 10, count 0 2006.201.10:29:07.85#ibcon#read 4, iclass 10, count 0 2006.201.10:29:07.85#ibcon#about to read 5, iclass 10, count 0 2006.201.10:29:07.85#ibcon#read 5, iclass 10, count 0 2006.201.10:29:07.85#ibcon#about to read 6, iclass 10, count 0 2006.201.10:29:07.85#ibcon#read 6, iclass 10, count 0 2006.201.10:29:07.85#ibcon#end of sib2, iclass 10, count 0 2006.201.10:29:07.85#ibcon#*after write, iclass 10, count 0 2006.201.10:29:07.85#ibcon#*before return 0, iclass 10, count 0 2006.201.10:29:07.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:07.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:29:07.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:29:07.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:29:07.85$vck44/vblo=2,634.99 2006.201.10:29:07.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.10:29:07.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.10:29:07.85#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:07.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:07.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:07.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:07.85#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:29:07.85#ibcon#first serial, iclass 12, count 0 2006.201.10:29:07.85#ibcon#enter sib2, iclass 12, count 0 2006.201.10:29:07.85#ibcon#flushed, iclass 12, count 0 2006.201.10:29:07.85#ibcon#about to write, iclass 12, count 0 2006.201.10:29:07.85#ibcon#wrote, iclass 12, count 0 2006.201.10:29:07.85#ibcon#about to read 3, iclass 12, count 0 2006.201.10:29:07.87#ibcon#read 3, iclass 12, count 0 2006.201.10:29:07.87#ibcon#about to read 4, iclass 12, count 0 2006.201.10:29:07.87#ibcon#read 4, iclass 12, count 0 2006.201.10:29:07.87#ibcon#about to read 5, iclass 12, count 0 2006.201.10:29:07.87#ibcon#read 5, iclass 12, count 0 2006.201.10:29:07.87#ibcon#about to read 6, iclass 12, count 0 2006.201.10:29:07.87#ibcon#read 6, iclass 12, count 0 2006.201.10:29:07.87#ibcon#end of sib2, iclass 12, count 0 2006.201.10:29:07.87#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:29:07.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:29:07.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:29:07.87#ibcon#*before write, iclass 12, count 0 2006.201.10:29:07.87#ibcon#enter sib2, iclass 12, count 0 2006.201.10:29:07.87#ibcon#flushed, iclass 12, count 0 2006.201.10:29:07.87#ibcon#about to write, iclass 12, count 0 2006.201.10:29:07.87#ibcon#wrote, iclass 12, count 0 2006.201.10:29:07.87#ibcon#about to read 3, iclass 12, count 0 2006.201.10:29:07.91#ibcon#read 3, iclass 12, count 0 2006.201.10:29:07.91#ibcon#about to read 4, iclass 12, count 0 2006.201.10:29:07.91#ibcon#read 4, iclass 12, count 0 2006.201.10:29:07.91#ibcon#about to read 5, iclass 12, count 0 2006.201.10:29:07.91#ibcon#read 5, iclass 12, count 0 2006.201.10:29:07.91#ibcon#about to read 6, iclass 12, count 0 2006.201.10:29:07.91#ibcon#read 6, iclass 12, count 0 2006.201.10:29:07.91#ibcon#end of sib2, iclass 12, count 0 2006.201.10:29:07.91#ibcon#*after write, iclass 12, count 0 2006.201.10:29:07.91#ibcon#*before return 0, iclass 12, count 0 2006.201.10:29:07.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:07.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:29:07.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:29:07.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:29:07.91$vck44/vb=2,5 2006.201.10:29:07.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.10:29:07.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.10:29:07.91#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:07.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:07.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:07.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:07.97#ibcon#enter wrdev, iclass 14, count 2 2006.201.10:29:07.97#ibcon#first serial, iclass 14, count 2 2006.201.10:29:07.97#ibcon#enter sib2, iclass 14, count 2 2006.201.10:29:07.97#ibcon#flushed, iclass 14, count 2 2006.201.10:29:07.97#ibcon#about to write, iclass 14, count 2 2006.201.10:29:07.97#ibcon#wrote, iclass 14, count 2 2006.201.10:29:07.97#ibcon#about to read 3, iclass 14, count 2 2006.201.10:29:07.99#ibcon#read 3, iclass 14, count 2 2006.201.10:29:07.99#ibcon#about to read 4, iclass 14, count 2 2006.201.10:29:07.99#ibcon#read 4, iclass 14, count 2 2006.201.10:29:07.99#ibcon#about to read 5, iclass 14, count 2 2006.201.10:29:07.99#ibcon#read 5, iclass 14, count 2 2006.201.10:29:07.99#ibcon#about to read 6, iclass 14, count 2 2006.201.10:29:07.99#ibcon#read 6, iclass 14, count 2 2006.201.10:29:07.99#ibcon#end of sib2, iclass 14, count 2 2006.201.10:29:07.99#ibcon#*mode == 0, iclass 14, count 2 2006.201.10:29:07.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.10:29:07.99#ibcon#[27=AT02-05\r\n] 2006.201.10:29:07.99#ibcon#*before write, iclass 14, count 2 2006.201.10:29:07.99#ibcon#enter sib2, iclass 14, count 2 2006.201.10:29:07.99#ibcon#flushed, iclass 14, count 2 2006.201.10:29:07.99#ibcon#about to write, iclass 14, count 2 2006.201.10:29:07.99#ibcon#wrote, iclass 14, count 2 2006.201.10:29:07.99#ibcon#about to read 3, iclass 14, count 2 2006.201.10:29:08.02#ibcon#read 3, iclass 14, count 2 2006.201.10:29:08.02#ibcon#about to read 4, iclass 14, count 2 2006.201.10:29:08.02#ibcon#read 4, iclass 14, count 2 2006.201.10:29:08.02#ibcon#about to read 5, iclass 14, count 2 2006.201.10:29:08.02#ibcon#read 5, iclass 14, count 2 2006.201.10:29:08.02#ibcon#about to read 6, iclass 14, count 2 2006.201.10:29:08.02#ibcon#read 6, iclass 14, count 2 2006.201.10:29:08.02#ibcon#end of sib2, iclass 14, count 2 2006.201.10:29:08.02#ibcon#*after write, iclass 14, count 2 2006.201.10:29:08.02#ibcon#*before return 0, iclass 14, count 2 2006.201.10:29:08.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:08.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:29:08.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.10:29:08.02#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:08.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:08.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:08.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:08.14#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:29:08.14#ibcon#first serial, iclass 14, count 0 2006.201.10:29:08.14#ibcon#enter sib2, iclass 14, count 0 2006.201.10:29:08.14#ibcon#flushed, iclass 14, count 0 2006.201.10:29:08.14#ibcon#about to write, iclass 14, count 0 2006.201.10:29:08.14#ibcon#wrote, iclass 14, count 0 2006.201.10:29:08.14#ibcon#about to read 3, iclass 14, count 0 2006.201.10:29:08.16#ibcon#read 3, iclass 14, count 0 2006.201.10:29:08.16#ibcon#about to read 4, iclass 14, count 0 2006.201.10:29:08.16#ibcon#read 4, iclass 14, count 0 2006.201.10:29:08.16#ibcon#about to read 5, iclass 14, count 0 2006.201.10:29:08.16#ibcon#read 5, iclass 14, count 0 2006.201.10:29:08.16#ibcon#about to read 6, iclass 14, count 0 2006.201.10:29:08.16#ibcon#read 6, iclass 14, count 0 2006.201.10:29:08.16#ibcon#end of sib2, iclass 14, count 0 2006.201.10:29:08.16#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:29:08.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:29:08.16#ibcon#[27=USB\r\n] 2006.201.10:29:08.16#ibcon#*before write, iclass 14, count 0 2006.201.10:29:08.16#ibcon#enter sib2, iclass 14, count 0 2006.201.10:29:08.16#ibcon#flushed, iclass 14, count 0 2006.201.10:29:08.16#ibcon#about to write, iclass 14, count 0 2006.201.10:29:08.16#ibcon#wrote, iclass 14, count 0 2006.201.10:29:08.16#ibcon#about to read 3, iclass 14, count 0 2006.201.10:29:08.19#ibcon#read 3, iclass 14, count 0 2006.201.10:29:08.19#ibcon#about to read 4, iclass 14, count 0 2006.201.10:29:08.19#ibcon#read 4, iclass 14, count 0 2006.201.10:29:08.19#ibcon#about to read 5, iclass 14, count 0 2006.201.10:29:08.19#ibcon#read 5, iclass 14, count 0 2006.201.10:29:08.19#ibcon#about to read 6, iclass 14, count 0 2006.201.10:29:08.19#ibcon#read 6, iclass 14, count 0 2006.201.10:29:08.19#ibcon#end of sib2, iclass 14, count 0 2006.201.10:29:08.19#ibcon#*after write, iclass 14, count 0 2006.201.10:29:08.19#ibcon#*before return 0, iclass 14, count 0 2006.201.10:29:08.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:08.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:29:08.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:29:08.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:29:08.19$vck44/vblo=3,649.99 2006.201.10:29:08.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.10:29:08.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.10:29:08.19#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:08.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:08.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:08.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:08.19#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:29:08.19#ibcon#first serial, iclass 16, count 0 2006.201.10:29:08.19#ibcon#enter sib2, iclass 16, count 0 2006.201.10:29:08.19#ibcon#flushed, iclass 16, count 0 2006.201.10:29:08.19#ibcon#about to write, iclass 16, count 0 2006.201.10:29:08.19#ibcon#wrote, iclass 16, count 0 2006.201.10:29:08.19#ibcon#about to read 3, iclass 16, count 0 2006.201.10:29:08.21#ibcon#read 3, iclass 16, count 0 2006.201.10:29:08.21#ibcon#about to read 4, iclass 16, count 0 2006.201.10:29:08.21#ibcon#read 4, iclass 16, count 0 2006.201.10:29:08.21#ibcon#about to read 5, iclass 16, count 0 2006.201.10:29:08.21#ibcon#read 5, iclass 16, count 0 2006.201.10:29:08.21#ibcon#about to read 6, iclass 16, count 0 2006.201.10:29:08.21#ibcon#read 6, iclass 16, count 0 2006.201.10:29:08.21#ibcon#end of sib2, iclass 16, count 0 2006.201.10:29:08.21#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:29:08.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:29:08.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:29:08.21#ibcon#*before write, iclass 16, count 0 2006.201.10:29:08.21#ibcon#enter sib2, iclass 16, count 0 2006.201.10:29:08.21#ibcon#flushed, iclass 16, count 0 2006.201.10:29:08.21#ibcon#about to write, iclass 16, count 0 2006.201.10:29:08.21#ibcon#wrote, iclass 16, count 0 2006.201.10:29:08.21#ibcon#about to read 3, iclass 16, count 0 2006.201.10:29:08.25#ibcon#read 3, iclass 16, count 0 2006.201.10:29:08.25#ibcon#about to read 4, iclass 16, count 0 2006.201.10:29:08.25#ibcon#read 4, iclass 16, count 0 2006.201.10:29:08.25#ibcon#about to read 5, iclass 16, count 0 2006.201.10:29:08.25#ibcon#read 5, iclass 16, count 0 2006.201.10:29:08.25#ibcon#about to read 6, iclass 16, count 0 2006.201.10:29:08.25#ibcon#read 6, iclass 16, count 0 2006.201.10:29:08.25#ibcon#end of sib2, iclass 16, count 0 2006.201.10:29:08.25#ibcon#*after write, iclass 16, count 0 2006.201.10:29:08.25#ibcon#*before return 0, iclass 16, count 0 2006.201.10:29:08.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:08.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:29:08.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:29:08.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:29:08.25$vck44/vb=3,4 2006.201.10:29:08.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.10:29:08.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.10:29:08.25#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:08.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:08.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:08.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:08.31#ibcon#enter wrdev, iclass 18, count 2 2006.201.10:29:08.31#ibcon#first serial, iclass 18, count 2 2006.201.10:29:08.31#ibcon#enter sib2, iclass 18, count 2 2006.201.10:29:08.31#ibcon#flushed, iclass 18, count 2 2006.201.10:29:08.31#ibcon#about to write, iclass 18, count 2 2006.201.10:29:08.31#ibcon#wrote, iclass 18, count 2 2006.201.10:29:08.31#ibcon#about to read 3, iclass 18, count 2 2006.201.10:29:08.33#ibcon#read 3, iclass 18, count 2 2006.201.10:29:08.33#ibcon#about to read 4, iclass 18, count 2 2006.201.10:29:08.33#ibcon#read 4, iclass 18, count 2 2006.201.10:29:08.33#ibcon#about to read 5, iclass 18, count 2 2006.201.10:29:08.33#ibcon#read 5, iclass 18, count 2 2006.201.10:29:08.33#ibcon#about to read 6, iclass 18, count 2 2006.201.10:29:08.33#ibcon#read 6, iclass 18, count 2 2006.201.10:29:08.33#ibcon#end of sib2, iclass 18, count 2 2006.201.10:29:08.33#ibcon#*mode == 0, iclass 18, count 2 2006.201.10:29:08.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.10:29:08.33#ibcon#[27=AT03-04\r\n] 2006.201.10:29:08.33#ibcon#*before write, iclass 18, count 2 2006.201.10:29:08.33#ibcon#enter sib2, iclass 18, count 2 2006.201.10:29:08.33#ibcon#flushed, iclass 18, count 2 2006.201.10:29:08.33#ibcon#about to write, iclass 18, count 2 2006.201.10:29:08.33#ibcon#wrote, iclass 18, count 2 2006.201.10:29:08.33#ibcon#about to read 3, iclass 18, count 2 2006.201.10:29:08.36#ibcon#read 3, iclass 18, count 2 2006.201.10:29:08.36#ibcon#about to read 4, iclass 18, count 2 2006.201.10:29:08.36#ibcon#read 4, iclass 18, count 2 2006.201.10:29:08.36#ibcon#about to read 5, iclass 18, count 2 2006.201.10:29:08.36#ibcon#read 5, iclass 18, count 2 2006.201.10:29:08.36#ibcon#about to read 6, iclass 18, count 2 2006.201.10:29:08.36#ibcon#read 6, iclass 18, count 2 2006.201.10:29:08.36#ibcon#end of sib2, iclass 18, count 2 2006.201.10:29:08.36#ibcon#*after write, iclass 18, count 2 2006.201.10:29:08.36#ibcon#*before return 0, iclass 18, count 2 2006.201.10:29:08.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:08.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:29:08.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.10:29:08.36#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:08.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:08.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:08.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:08.48#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:29:08.48#ibcon#first serial, iclass 18, count 0 2006.201.10:29:08.48#ibcon#enter sib2, iclass 18, count 0 2006.201.10:29:08.48#ibcon#flushed, iclass 18, count 0 2006.201.10:29:08.48#ibcon#about to write, iclass 18, count 0 2006.201.10:29:08.48#ibcon#wrote, iclass 18, count 0 2006.201.10:29:08.48#ibcon#about to read 3, iclass 18, count 0 2006.201.10:29:08.50#ibcon#read 3, iclass 18, count 0 2006.201.10:29:08.50#ibcon#about to read 4, iclass 18, count 0 2006.201.10:29:08.50#ibcon#read 4, iclass 18, count 0 2006.201.10:29:08.50#ibcon#about to read 5, iclass 18, count 0 2006.201.10:29:08.50#ibcon#read 5, iclass 18, count 0 2006.201.10:29:08.50#ibcon#about to read 6, iclass 18, count 0 2006.201.10:29:08.50#ibcon#read 6, iclass 18, count 0 2006.201.10:29:08.50#ibcon#end of sib2, iclass 18, count 0 2006.201.10:29:08.50#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:29:08.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:29:08.50#ibcon#[27=USB\r\n] 2006.201.10:29:08.50#ibcon#*before write, iclass 18, count 0 2006.201.10:29:08.50#ibcon#enter sib2, iclass 18, count 0 2006.201.10:29:08.50#ibcon#flushed, iclass 18, count 0 2006.201.10:29:08.50#ibcon#about to write, iclass 18, count 0 2006.201.10:29:08.50#ibcon#wrote, iclass 18, count 0 2006.201.10:29:08.50#ibcon#about to read 3, iclass 18, count 0 2006.201.10:29:08.53#ibcon#read 3, iclass 18, count 0 2006.201.10:29:08.53#ibcon#about to read 4, iclass 18, count 0 2006.201.10:29:08.53#ibcon#read 4, iclass 18, count 0 2006.201.10:29:08.53#ibcon#about to read 5, iclass 18, count 0 2006.201.10:29:08.53#ibcon#read 5, iclass 18, count 0 2006.201.10:29:08.53#ibcon#about to read 6, iclass 18, count 0 2006.201.10:29:08.53#ibcon#read 6, iclass 18, count 0 2006.201.10:29:08.53#ibcon#end of sib2, iclass 18, count 0 2006.201.10:29:08.53#ibcon#*after write, iclass 18, count 0 2006.201.10:29:08.53#ibcon#*before return 0, iclass 18, count 0 2006.201.10:29:08.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:08.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:29:08.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:29:08.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:29:08.53$vck44/vblo=4,679.99 2006.201.10:29:08.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.10:29:08.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.10:29:08.53#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:08.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:08.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:08.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:08.53#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:29:08.53#ibcon#first serial, iclass 20, count 0 2006.201.10:29:08.53#ibcon#enter sib2, iclass 20, count 0 2006.201.10:29:08.53#ibcon#flushed, iclass 20, count 0 2006.201.10:29:08.53#ibcon#about to write, iclass 20, count 0 2006.201.10:29:08.53#ibcon#wrote, iclass 20, count 0 2006.201.10:29:08.53#ibcon#about to read 3, iclass 20, count 0 2006.201.10:29:08.55#ibcon#read 3, iclass 20, count 0 2006.201.10:29:08.55#ibcon#about to read 4, iclass 20, count 0 2006.201.10:29:08.55#ibcon#read 4, iclass 20, count 0 2006.201.10:29:08.55#ibcon#about to read 5, iclass 20, count 0 2006.201.10:29:08.55#ibcon#read 5, iclass 20, count 0 2006.201.10:29:08.55#ibcon#about to read 6, iclass 20, count 0 2006.201.10:29:08.55#ibcon#read 6, iclass 20, count 0 2006.201.10:29:08.55#ibcon#end of sib2, iclass 20, count 0 2006.201.10:29:08.55#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:29:08.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:29:08.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:29:08.55#ibcon#*before write, iclass 20, count 0 2006.201.10:29:08.55#ibcon#enter sib2, iclass 20, count 0 2006.201.10:29:08.55#ibcon#flushed, iclass 20, count 0 2006.201.10:29:08.55#ibcon#about to write, iclass 20, count 0 2006.201.10:29:08.55#ibcon#wrote, iclass 20, count 0 2006.201.10:29:08.55#ibcon#about to read 3, iclass 20, count 0 2006.201.10:29:08.60#ibcon#read 3, iclass 20, count 0 2006.201.10:29:08.60#ibcon#about to read 4, iclass 20, count 0 2006.201.10:29:08.60#ibcon#read 4, iclass 20, count 0 2006.201.10:29:08.60#ibcon#about to read 5, iclass 20, count 0 2006.201.10:29:08.60#ibcon#read 5, iclass 20, count 0 2006.201.10:29:08.60#ibcon#about to read 6, iclass 20, count 0 2006.201.10:29:08.60#ibcon#read 6, iclass 20, count 0 2006.201.10:29:08.60#ibcon#end of sib2, iclass 20, count 0 2006.201.10:29:08.60#ibcon#*after write, iclass 20, count 0 2006.201.10:29:08.60#ibcon#*before return 0, iclass 20, count 0 2006.201.10:29:08.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:08.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:29:08.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:29:08.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:29:08.60$vck44/vb=4,5 2006.201.10:29:08.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.10:29:08.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.10:29:08.60#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:08.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:08.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:08.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:08.65#ibcon#enter wrdev, iclass 22, count 2 2006.201.10:29:08.65#ibcon#first serial, iclass 22, count 2 2006.201.10:29:08.65#ibcon#enter sib2, iclass 22, count 2 2006.201.10:29:08.65#ibcon#flushed, iclass 22, count 2 2006.201.10:29:08.65#ibcon#about to write, iclass 22, count 2 2006.201.10:29:08.65#ibcon#wrote, iclass 22, count 2 2006.201.10:29:08.65#ibcon#about to read 3, iclass 22, count 2 2006.201.10:29:08.67#ibcon#read 3, iclass 22, count 2 2006.201.10:29:08.67#ibcon#about to read 4, iclass 22, count 2 2006.201.10:29:08.67#ibcon#read 4, iclass 22, count 2 2006.201.10:29:08.67#ibcon#about to read 5, iclass 22, count 2 2006.201.10:29:08.67#ibcon#read 5, iclass 22, count 2 2006.201.10:29:08.67#ibcon#about to read 6, iclass 22, count 2 2006.201.10:29:08.67#ibcon#read 6, iclass 22, count 2 2006.201.10:29:08.67#ibcon#end of sib2, iclass 22, count 2 2006.201.10:29:08.67#ibcon#*mode == 0, iclass 22, count 2 2006.201.10:29:08.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.10:29:08.67#ibcon#[27=AT04-05\r\n] 2006.201.10:29:08.67#ibcon#*before write, iclass 22, count 2 2006.201.10:29:08.67#ibcon#enter sib2, iclass 22, count 2 2006.201.10:29:08.67#ibcon#flushed, iclass 22, count 2 2006.201.10:29:08.67#ibcon#about to write, iclass 22, count 2 2006.201.10:29:08.67#ibcon#wrote, iclass 22, count 2 2006.201.10:29:08.67#ibcon#about to read 3, iclass 22, count 2 2006.201.10:29:08.70#ibcon#read 3, iclass 22, count 2 2006.201.10:29:08.70#ibcon#about to read 4, iclass 22, count 2 2006.201.10:29:08.70#ibcon#read 4, iclass 22, count 2 2006.201.10:29:08.70#ibcon#about to read 5, iclass 22, count 2 2006.201.10:29:08.70#ibcon#read 5, iclass 22, count 2 2006.201.10:29:08.70#ibcon#about to read 6, iclass 22, count 2 2006.201.10:29:08.70#ibcon#read 6, iclass 22, count 2 2006.201.10:29:08.70#ibcon#end of sib2, iclass 22, count 2 2006.201.10:29:08.70#ibcon#*after write, iclass 22, count 2 2006.201.10:29:08.70#ibcon#*before return 0, iclass 22, count 2 2006.201.10:29:08.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:08.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:29:08.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.10:29:08.70#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:08.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:08.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:08.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:08.82#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:29:08.82#ibcon#first serial, iclass 22, count 0 2006.201.10:29:08.82#ibcon#enter sib2, iclass 22, count 0 2006.201.10:29:08.82#ibcon#flushed, iclass 22, count 0 2006.201.10:29:08.82#ibcon#about to write, iclass 22, count 0 2006.201.10:29:08.82#ibcon#wrote, iclass 22, count 0 2006.201.10:29:08.82#ibcon#about to read 3, iclass 22, count 0 2006.201.10:29:08.84#ibcon#read 3, iclass 22, count 0 2006.201.10:29:08.84#ibcon#about to read 4, iclass 22, count 0 2006.201.10:29:08.84#ibcon#read 4, iclass 22, count 0 2006.201.10:29:08.84#ibcon#about to read 5, iclass 22, count 0 2006.201.10:29:08.84#ibcon#read 5, iclass 22, count 0 2006.201.10:29:08.84#ibcon#about to read 6, iclass 22, count 0 2006.201.10:29:08.84#ibcon#read 6, iclass 22, count 0 2006.201.10:29:08.84#ibcon#end of sib2, iclass 22, count 0 2006.201.10:29:08.84#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:29:08.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:29:08.84#ibcon#[27=USB\r\n] 2006.201.10:29:08.84#ibcon#*before write, iclass 22, count 0 2006.201.10:29:08.84#ibcon#enter sib2, iclass 22, count 0 2006.201.10:29:08.84#ibcon#flushed, iclass 22, count 0 2006.201.10:29:08.84#ibcon#about to write, iclass 22, count 0 2006.201.10:29:08.84#ibcon#wrote, iclass 22, count 0 2006.201.10:29:08.84#ibcon#about to read 3, iclass 22, count 0 2006.201.10:29:08.87#ibcon#read 3, iclass 22, count 0 2006.201.10:29:08.87#ibcon#about to read 4, iclass 22, count 0 2006.201.10:29:08.87#ibcon#read 4, iclass 22, count 0 2006.201.10:29:08.87#ibcon#about to read 5, iclass 22, count 0 2006.201.10:29:08.87#ibcon#read 5, iclass 22, count 0 2006.201.10:29:08.87#ibcon#about to read 6, iclass 22, count 0 2006.201.10:29:08.87#ibcon#read 6, iclass 22, count 0 2006.201.10:29:08.87#ibcon#end of sib2, iclass 22, count 0 2006.201.10:29:08.87#ibcon#*after write, iclass 22, count 0 2006.201.10:29:08.87#ibcon#*before return 0, iclass 22, count 0 2006.201.10:29:08.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:08.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:29:08.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:29:08.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:29:08.87$vck44/vblo=5,709.99 2006.201.10:29:08.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.10:29:08.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.10:29:08.87#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:08.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:08.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:08.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:08.87#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:29:08.87#ibcon#first serial, iclass 24, count 0 2006.201.10:29:08.87#ibcon#enter sib2, iclass 24, count 0 2006.201.10:29:08.87#ibcon#flushed, iclass 24, count 0 2006.201.10:29:08.87#ibcon#about to write, iclass 24, count 0 2006.201.10:29:08.87#ibcon#wrote, iclass 24, count 0 2006.201.10:29:08.87#ibcon#about to read 3, iclass 24, count 0 2006.201.10:29:08.89#ibcon#read 3, iclass 24, count 0 2006.201.10:29:08.89#ibcon#about to read 4, iclass 24, count 0 2006.201.10:29:08.89#ibcon#read 4, iclass 24, count 0 2006.201.10:29:08.89#ibcon#about to read 5, iclass 24, count 0 2006.201.10:29:08.89#ibcon#read 5, iclass 24, count 0 2006.201.10:29:08.89#ibcon#about to read 6, iclass 24, count 0 2006.201.10:29:08.89#ibcon#read 6, iclass 24, count 0 2006.201.10:29:08.89#ibcon#end of sib2, iclass 24, count 0 2006.201.10:29:08.89#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:29:08.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:29:08.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:29:08.89#ibcon#*before write, iclass 24, count 0 2006.201.10:29:08.89#ibcon#enter sib2, iclass 24, count 0 2006.201.10:29:08.89#ibcon#flushed, iclass 24, count 0 2006.201.10:29:08.89#ibcon#about to write, iclass 24, count 0 2006.201.10:29:08.89#ibcon#wrote, iclass 24, count 0 2006.201.10:29:08.89#ibcon#about to read 3, iclass 24, count 0 2006.201.10:29:08.93#ibcon#read 3, iclass 24, count 0 2006.201.10:29:08.93#ibcon#about to read 4, iclass 24, count 0 2006.201.10:29:08.93#ibcon#read 4, iclass 24, count 0 2006.201.10:29:08.93#ibcon#about to read 5, iclass 24, count 0 2006.201.10:29:08.93#ibcon#read 5, iclass 24, count 0 2006.201.10:29:08.93#ibcon#about to read 6, iclass 24, count 0 2006.201.10:29:08.93#ibcon#read 6, iclass 24, count 0 2006.201.10:29:08.93#ibcon#end of sib2, iclass 24, count 0 2006.201.10:29:08.93#ibcon#*after write, iclass 24, count 0 2006.201.10:29:08.93#ibcon#*before return 0, iclass 24, count 0 2006.201.10:29:08.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:08.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:29:08.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:29:08.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:29:08.93$vck44/vb=5,4 2006.201.10:29:08.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.10:29:08.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.10:29:08.93#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:08.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:08.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:08.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:08.99#ibcon#enter wrdev, iclass 26, count 2 2006.201.10:29:08.99#ibcon#first serial, iclass 26, count 2 2006.201.10:29:08.99#ibcon#enter sib2, iclass 26, count 2 2006.201.10:29:08.99#ibcon#flushed, iclass 26, count 2 2006.201.10:29:08.99#ibcon#about to write, iclass 26, count 2 2006.201.10:29:08.99#ibcon#wrote, iclass 26, count 2 2006.201.10:29:08.99#ibcon#about to read 3, iclass 26, count 2 2006.201.10:29:09.01#ibcon#read 3, iclass 26, count 2 2006.201.10:29:09.01#ibcon#about to read 4, iclass 26, count 2 2006.201.10:29:09.01#ibcon#read 4, iclass 26, count 2 2006.201.10:29:09.01#ibcon#about to read 5, iclass 26, count 2 2006.201.10:29:09.01#ibcon#read 5, iclass 26, count 2 2006.201.10:29:09.01#ibcon#about to read 6, iclass 26, count 2 2006.201.10:29:09.01#ibcon#read 6, iclass 26, count 2 2006.201.10:29:09.01#ibcon#end of sib2, iclass 26, count 2 2006.201.10:29:09.01#ibcon#*mode == 0, iclass 26, count 2 2006.201.10:29:09.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.10:29:09.01#ibcon#[27=AT05-04\r\n] 2006.201.10:29:09.01#ibcon#*before write, iclass 26, count 2 2006.201.10:29:09.01#ibcon#enter sib2, iclass 26, count 2 2006.201.10:29:09.01#ibcon#flushed, iclass 26, count 2 2006.201.10:29:09.01#ibcon#about to write, iclass 26, count 2 2006.201.10:29:09.01#ibcon#wrote, iclass 26, count 2 2006.201.10:29:09.01#ibcon#about to read 3, iclass 26, count 2 2006.201.10:29:09.04#ibcon#read 3, iclass 26, count 2 2006.201.10:29:09.04#ibcon#about to read 4, iclass 26, count 2 2006.201.10:29:09.04#ibcon#read 4, iclass 26, count 2 2006.201.10:29:09.04#ibcon#about to read 5, iclass 26, count 2 2006.201.10:29:09.04#ibcon#read 5, iclass 26, count 2 2006.201.10:29:09.04#ibcon#about to read 6, iclass 26, count 2 2006.201.10:29:09.04#ibcon#read 6, iclass 26, count 2 2006.201.10:29:09.04#ibcon#end of sib2, iclass 26, count 2 2006.201.10:29:09.04#ibcon#*after write, iclass 26, count 2 2006.201.10:29:09.04#ibcon#*before return 0, iclass 26, count 2 2006.201.10:29:09.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:09.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:29:09.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.10:29:09.04#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:09.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:09.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:09.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:09.16#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:29:09.16#ibcon#first serial, iclass 26, count 0 2006.201.10:29:09.16#ibcon#enter sib2, iclass 26, count 0 2006.201.10:29:09.16#ibcon#flushed, iclass 26, count 0 2006.201.10:29:09.16#ibcon#about to write, iclass 26, count 0 2006.201.10:29:09.16#ibcon#wrote, iclass 26, count 0 2006.201.10:29:09.16#ibcon#about to read 3, iclass 26, count 0 2006.201.10:29:09.18#ibcon#read 3, iclass 26, count 0 2006.201.10:29:09.18#ibcon#about to read 4, iclass 26, count 0 2006.201.10:29:09.18#ibcon#read 4, iclass 26, count 0 2006.201.10:29:09.18#ibcon#about to read 5, iclass 26, count 0 2006.201.10:29:09.18#ibcon#read 5, iclass 26, count 0 2006.201.10:29:09.18#ibcon#about to read 6, iclass 26, count 0 2006.201.10:29:09.18#ibcon#read 6, iclass 26, count 0 2006.201.10:29:09.18#ibcon#end of sib2, iclass 26, count 0 2006.201.10:29:09.18#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:29:09.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:29:09.18#ibcon#[27=USB\r\n] 2006.201.10:29:09.18#ibcon#*before write, iclass 26, count 0 2006.201.10:29:09.18#ibcon#enter sib2, iclass 26, count 0 2006.201.10:29:09.18#ibcon#flushed, iclass 26, count 0 2006.201.10:29:09.18#ibcon#about to write, iclass 26, count 0 2006.201.10:29:09.18#ibcon#wrote, iclass 26, count 0 2006.201.10:29:09.18#ibcon#about to read 3, iclass 26, count 0 2006.201.10:29:09.21#ibcon#read 3, iclass 26, count 0 2006.201.10:29:09.21#ibcon#about to read 4, iclass 26, count 0 2006.201.10:29:09.21#ibcon#read 4, iclass 26, count 0 2006.201.10:29:09.21#ibcon#about to read 5, iclass 26, count 0 2006.201.10:29:09.21#ibcon#read 5, iclass 26, count 0 2006.201.10:29:09.21#ibcon#about to read 6, iclass 26, count 0 2006.201.10:29:09.21#ibcon#read 6, iclass 26, count 0 2006.201.10:29:09.21#ibcon#end of sib2, iclass 26, count 0 2006.201.10:29:09.21#ibcon#*after write, iclass 26, count 0 2006.201.10:29:09.21#ibcon#*before return 0, iclass 26, count 0 2006.201.10:29:09.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:09.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:29:09.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:29:09.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:29:09.21$vck44/vblo=6,719.99 2006.201.10:29:09.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.10:29:09.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.10:29:09.21#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:09.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:09.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:09.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:09.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:29:09.21#ibcon#first serial, iclass 28, count 0 2006.201.10:29:09.21#ibcon#enter sib2, iclass 28, count 0 2006.201.10:29:09.21#ibcon#flushed, iclass 28, count 0 2006.201.10:29:09.21#ibcon#about to write, iclass 28, count 0 2006.201.10:29:09.21#ibcon#wrote, iclass 28, count 0 2006.201.10:29:09.21#ibcon#about to read 3, iclass 28, count 0 2006.201.10:29:09.23#ibcon#read 3, iclass 28, count 0 2006.201.10:29:09.23#ibcon#about to read 4, iclass 28, count 0 2006.201.10:29:09.23#ibcon#read 4, iclass 28, count 0 2006.201.10:29:09.23#ibcon#about to read 5, iclass 28, count 0 2006.201.10:29:09.23#ibcon#read 5, iclass 28, count 0 2006.201.10:29:09.23#ibcon#about to read 6, iclass 28, count 0 2006.201.10:29:09.23#ibcon#read 6, iclass 28, count 0 2006.201.10:29:09.23#ibcon#end of sib2, iclass 28, count 0 2006.201.10:29:09.23#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:29:09.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:29:09.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:29:09.23#ibcon#*before write, iclass 28, count 0 2006.201.10:29:09.23#ibcon#enter sib2, iclass 28, count 0 2006.201.10:29:09.23#ibcon#flushed, iclass 28, count 0 2006.201.10:29:09.23#ibcon#about to write, iclass 28, count 0 2006.201.10:29:09.23#ibcon#wrote, iclass 28, count 0 2006.201.10:29:09.23#ibcon#about to read 3, iclass 28, count 0 2006.201.10:29:09.28#ibcon#read 3, iclass 28, count 0 2006.201.10:29:09.28#ibcon#about to read 4, iclass 28, count 0 2006.201.10:29:09.28#ibcon#read 4, iclass 28, count 0 2006.201.10:29:09.28#ibcon#about to read 5, iclass 28, count 0 2006.201.10:29:09.28#ibcon#read 5, iclass 28, count 0 2006.201.10:29:09.28#ibcon#about to read 6, iclass 28, count 0 2006.201.10:29:09.28#ibcon#read 6, iclass 28, count 0 2006.201.10:29:09.28#ibcon#end of sib2, iclass 28, count 0 2006.201.10:29:09.28#ibcon#*after write, iclass 28, count 0 2006.201.10:29:09.28#ibcon#*before return 0, iclass 28, count 0 2006.201.10:29:09.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:09.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:29:09.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:29:09.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:29:09.28$vck44/vb=6,4 2006.201.10:29:09.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.10:29:09.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.10:29:09.28#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:09.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:09.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:09.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:09.33#ibcon#enter wrdev, iclass 30, count 2 2006.201.10:29:09.33#ibcon#first serial, iclass 30, count 2 2006.201.10:29:09.33#ibcon#enter sib2, iclass 30, count 2 2006.201.10:29:09.33#ibcon#flushed, iclass 30, count 2 2006.201.10:29:09.33#ibcon#about to write, iclass 30, count 2 2006.201.10:29:09.33#ibcon#wrote, iclass 30, count 2 2006.201.10:29:09.33#ibcon#about to read 3, iclass 30, count 2 2006.201.10:29:09.35#ibcon#read 3, iclass 30, count 2 2006.201.10:29:09.35#ibcon#about to read 4, iclass 30, count 2 2006.201.10:29:09.35#ibcon#read 4, iclass 30, count 2 2006.201.10:29:09.35#ibcon#about to read 5, iclass 30, count 2 2006.201.10:29:09.35#ibcon#read 5, iclass 30, count 2 2006.201.10:29:09.35#ibcon#about to read 6, iclass 30, count 2 2006.201.10:29:09.35#ibcon#read 6, iclass 30, count 2 2006.201.10:29:09.35#ibcon#end of sib2, iclass 30, count 2 2006.201.10:29:09.35#ibcon#*mode == 0, iclass 30, count 2 2006.201.10:29:09.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.10:29:09.35#ibcon#[27=AT06-04\r\n] 2006.201.10:29:09.35#ibcon#*before write, iclass 30, count 2 2006.201.10:29:09.35#ibcon#enter sib2, iclass 30, count 2 2006.201.10:29:09.35#ibcon#flushed, iclass 30, count 2 2006.201.10:29:09.35#ibcon#about to write, iclass 30, count 2 2006.201.10:29:09.35#ibcon#wrote, iclass 30, count 2 2006.201.10:29:09.35#ibcon#about to read 3, iclass 30, count 2 2006.201.10:29:09.38#ibcon#read 3, iclass 30, count 2 2006.201.10:29:09.38#ibcon#about to read 4, iclass 30, count 2 2006.201.10:29:09.38#ibcon#read 4, iclass 30, count 2 2006.201.10:29:09.38#ibcon#about to read 5, iclass 30, count 2 2006.201.10:29:09.38#ibcon#read 5, iclass 30, count 2 2006.201.10:29:09.38#ibcon#about to read 6, iclass 30, count 2 2006.201.10:29:09.38#ibcon#read 6, iclass 30, count 2 2006.201.10:29:09.38#ibcon#end of sib2, iclass 30, count 2 2006.201.10:29:09.38#ibcon#*after write, iclass 30, count 2 2006.201.10:29:09.38#ibcon#*before return 0, iclass 30, count 2 2006.201.10:29:09.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:09.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:29:09.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.10:29:09.38#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:09.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:09.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:09.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:09.50#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:29:09.50#ibcon#first serial, iclass 30, count 0 2006.201.10:29:09.50#ibcon#enter sib2, iclass 30, count 0 2006.201.10:29:09.50#ibcon#flushed, iclass 30, count 0 2006.201.10:29:09.50#ibcon#about to write, iclass 30, count 0 2006.201.10:29:09.50#ibcon#wrote, iclass 30, count 0 2006.201.10:29:09.50#ibcon#about to read 3, iclass 30, count 0 2006.201.10:29:09.52#ibcon#read 3, iclass 30, count 0 2006.201.10:29:09.52#ibcon#about to read 4, iclass 30, count 0 2006.201.10:29:09.52#ibcon#read 4, iclass 30, count 0 2006.201.10:29:09.52#ibcon#about to read 5, iclass 30, count 0 2006.201.10:29:09.52#ibcon#read 5, iclass 30, count 0 2006.201.10:29:09.52#ibcon#about to read 6, iclass 30, count 0 2006.201.10:29:09.52#ibcon#read 6, iclass 30, count 0 2006.201.10:29:09.52#ibcon#end of sib2, iclass 30, count 0 2006.201.10:29:09.52#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:29:09.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:29:09.52#ibcon#[27=USB\r\n] 2006.201.10:29:09.52#ibcon#*before write, iclass 30, count 0 2006.201.10:29:09.52#ibcon#enter sib2, iclass 30, count 0 2006.201.10:29:09.52#ibcon#flushed, iclass 30, count 0 2006.201.10:29:09.52#ibcon#about to write, iclass 30, count 0 2006.201.10:29:09.52#ibcon#wrote, iclass 30, count 0 2006.201.10:29:09.52#ibcon#about to read 3, iclass 30, count 0 2006.201.10:29:09.55#ibcon#read 3, iclass 30, count 0 2006.201.10:29:09.55#ibcon#about to read 4, iclass 30, count 0 2006.201.10:29:09.55#ibcon#read 4, iclass 30, count 0 2006.201.10:29:09.55#ibcon#about to read 5, iclass 30, count 0 2006.201.10:29:09.55#ibcon#read 5, iclass 30, count 0 2006.201.10:29:09.55#ibcon#about to read 6, iclass 30, count 0 2006.201.10:29:09.55#ibcon#read 6, iclass 30, count 0 2006.201.10:29:09.55#ibcon#end of sib2, iclass 30, count 0 2006.201.10:29:09.55#ibcon#*after write, iclass 30, count 0 2006.201.10:29:09.55#ibcon#*before return 0, iclass 30, count 0 2006.201.10:29:09.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:09.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:29:09.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:29:09.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:29:09.55$vck44/vblo=7,734.99 2006.201.10:29:09.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.10:29:09.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.10:29:09.55#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:09.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:09.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:09.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:09.55#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:29:09.55#ibcon#first serial, iclass 32, count 0 2006.201.10:29:09.55#ibcon#enter sib2, iclass 32, count 0 2006.201.10:29:09.55#ibcon#flushed, iclass 32, count 0 2006.201.10:29:09.55#ibcon#about to write, iclass 32, count 0 2006.201.10:29:09.55#ibcon#wrote, iclass 32, count 0 2006.201.10:29:09.55#ibcon#about to read 3, iclass 32, count 0 2006.201.10:29:09.57#ibcon#read 3, iclass 32, count 0 2006.201.10:29:09.57#ibcon#about to read 4, iclass 32, count 0 2006.201.10:29:09.57#ibcon#read 4, iclass 32, count 0 2006.201.10:29:09.57#ibcon#about to read 5, iclass 32, count 0 2006.201.10:29:09.57#ibcon#read 5, iclass 32, count 0 2006.201.10:29:09.57#ibcon#about to read 6, iclass 32, count 0 2006.201.10:29:09.57#ibcon#read 6, iclass 32, count 0 2006.201.10:29:09.57#ibcon#end of sib2, iclass 32, count 0 2006.201.10:29:09.57#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:29:09.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:29:09.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:29:09.57#ibcon#*before write, iclass 32, count 0 2006.201.10:29:09.57#ibcon#enter sib2, iclass 32, count 0 2006.201.10:29:09.57#ibcon#flushed, iclass 32, count 0 2006.201.10:29:09.57#ibcon#about to write, iclass 32, count 0 2006.201.10:29:09.57#ibcon#wrote, iclass 32, count 0 2006.201.10:29:09.57#ibcon#about to read 3, iclass 32, count 0 2006.201.10:29:09.61#ibcon#read 3, iclass 32, count 0 2006.201.10:29:09.61#ibcon#about to read 4, iclass 32, count 0 2006.201.10:29:09.61#ibcon#read 4, iclass 32, count 0 2006.201.10:29:09.61#ibcon#about to read 5, iclass 32, count 0 2006.201.10:29:09.61#ibcon#read 5, iclass 32, count 0 2006.201.10:29:09.61#ibcon#about to read 6, iclass 32, count 0 2006.201.10:29:09.61#ibcon#read 6, iclass 32, count 0 2006.201.10:29:09.61#ibcon#end of sib2, iclass 32, count 0 2006.201.10:29:09.61#ibcon#*after write, iclass 32, count 0 2006.201.10:29:09.61#ibcon#*before return 0, iclass 32, count 0 2006.201.10:29:09.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:09.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:29:09.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:29:09.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:29:09.61$vck44/vb=7,4 2006.201.10:29:09.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.10:29:09.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.10:29:09.61#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:09.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:09.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:09.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:09.67#ibcon#enter wrdev, iclass 34, count 2 2006.201.10:29:09.67#ibcon#first serial, iclass 34, count 2 2006.201.10:29:09.67#ibcon#enter sib2, iclass 34, count 2 2006.201.10:29:09.67#ibcon#flushed, iclass 34, count 2 2006.201.10:29:09.67#ibcon#about to write, iclass 34, count 2 2006.201.10:29:09.67#ibcon#wrote, iclass 34, count 2 2006.201.10:29:09.67#ibcon#about to read 3, iclass 34, count 2 2006.201.10:29:09.69#ibcon#read 3, iclass 34, count 2 2006.201.10:29:09.69#ibcon#about to read 4, iclass 34, count 2 2006.201.10:29:09.69#ibcon#read 4, iclass 34, count 2 2006.201.10:29:09.69#ibcon#about to read 5, iclass 34, count 2 2006.201.10:29:09.69#ibcon#read 5, iclass 34, count 2 2006.201.10:29:09.69#ibcon#about to read 6, iclass 34, count 2 2006.201.10:29:09.69#ibcon#read 6, iclass 34, count 2 2006.201.10:29:09.69#ibcon#end of sib2, iclass 34, count 2 2006.201.10:29:09.69#ibcon#*mode == 0, iclass 34, count 2 2006.201.10:29:09.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.10:29:09.69#ibcon#[27=AT07-04\r\n] 2006.201.10:29:09.69#ibcon#*before write, iclass 34, count 2 2006.201.10:29:09.69#ibcon#enter sib2, iclass 34, count 2 2006.201.10:29:09.69#ibcon#flushed, iclass 34, count 2 2006.201.10:29:09.69#ibcon#about to write, iclass 34, count 2 2006.201.10:29:09.69#ibcon#wrote, iclass 34, count 2 2006.201.10:29:09.69#ibcon#about to read 3, iclass 34, count 2 2006.201.10:29:09.72#ibcon#read 3, iclass 34, count 2 2006.201.10:29:09.72#ibcon#about to read 4, iclass 34, count 2 2006.201.10:29:09.72#ibcon#read 4, iclass 34, count 2 2006.201.10:29:09.72#ibcon#about to read 5, iclass 34, count 2 2006.201.10:29:09.72#ibcon#read 5, iclass 34, count 2 2006.201.10:29:09.72#ibcon#about to read 6, iclass 34, count 2 2006.201.10:29:09.72#ibcon#read 6, iclass 34, count 2 2006.201.10:29:09.72#ibcon#end of sib2, iclass 34, count 2 2006.201.10:29:09.72#ibcon#*after write, iclass 34, count 2 2006.201.10:29:09.72#ibcon#*before return 0, iclass 34, count 2 2006.201.10:29:09.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:09.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:29:09.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.10:29:09.72#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:09.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:09.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:09.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:09.84#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:29:09.84#ibcon#first serial, iclass 34, count 0 2006.201.10:29:09.84#ibcon#enter sib2, iclass 34, count 0 2006.201.10:29:09.84#ibcon#flushed, iclass 34, count 0 2006.201.10:29:09.84#ibcon#about to write, iclass 34, count 0 2006.201.10:29:09.84#ibcon#wrote, iclass 34, count 0 2006.201.10:29:09.84#ibcon#about to read 3, iclass 34, count 0 2006.201.10:29:09.86#ibcon#read 3, iclass 34, count 0 2006.201.10:29:09.86#ibcon#about to read 4, iclass 34, count 0 2006.201.10:29:09.86#ibcon#read 4, iclass 34, count 0 2006.201.10:29:09.86#ibcon#about to read 5, iclass 34, count 0 2006.201.10:29:09.86#ibcon#read 5, iclass 34, count 0 2006.201.10:29:09.86#ibcon#about to read 6, iclass 34, count 0 2006.201.10:29:09.86#ibcon#read 6, iclass 34, count 0 2006.201.10:29:09.86#ibcon#end of sib2, iclass 34, count 0 2006.201.10:29:09.86#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:29:09.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:29:09.86#ibcon#[27=USB\r\n] 2006.201.10:29:09.86#ibcon#*before write, iclass 34, count 0 2006.201.10:29:09.86#ibcon#enter sib2, iclass 34, count 0 2006.201.10:29:09.86#ibcon#flushed, iclass 34, count 0 2006.201.10:29:09.86#ibcon#about to write, iclass 34, count 0 2006.201.10:29:09.86#ibcon#wrote, iclass 34, count 0 2006.201.10:29:09.86#ibcon#about to read 3, iclass 34, count 0 2006.201.10:29:09.89#ibcon#read 3, iclass 34, count 0 2006.201.10:29:09.89#ibcon#about to read 4, iclass 34, count 0 2006.201.10:29:09.89#ibcon#read 4, iclass 34, count 0 2006.201.10:29:09.89#ibcon#about to read 5, iclass 34, count 0 2006.201.10:29:09.89#ibcon#read 5, iclass 34, count 0 2006.201.10:29:09.89#ibcon#about to read 6, iclass 34, count 0 2006.201.10:29:09.89#ibcon#read 6, iclass 34, count 0 2006.201.10:29:09.89#ibcon#end of sib2, iclass 34, count 0 2006.201.10:29:09.89#ibcon#*after write, iclass 34, count 0 2006.201.10:29:09.89#ibcon#*before return 0, iclass 34, count 0 2006.201.10:29:09.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:09.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:29:09.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:29:09.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:29:09.89$vck44/vblo=8,744.99 2006.201.10:29:09.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.10:29:09.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.10:29:09.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:29:09.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:29:09.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:29:09.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:29:09.89#ibcon#enter wrdev, iclass 36, count 0 2006.201.10:29:09.89#ibcon#first serial, iclass 36, count 0 2006.201.10:29:09.89#ibcon#enter sib2, iclass 36, count 0 2006.201.10:29:09.89#ibcon#flushed, iclass 36, count 0 2006.201.10:29:09.89#ibcon#about to write, iclass 36, count 0 2006.201.10:29:09.89#ibcon#wrote, iclass 36, count 0 2006.201.10:29:09.89#ibcon#about to read 3, iclass 36, count 0 2006.201.10:29:09.91#ibcon#read 3, iclass 36, count 0 2006.201.10:29:09.91#ibcon#about to read 4, iclass 36, count 0 2006.201.10:29:09.91#ibcon#read 4, iclass 36, count 0 2006.201.10:29:09.91#ibcon#about to read 5, iclass 36, count 0 2006.201.10:29:09.91#ibcon#read 5, iclass 36, count 0 2006.201.10:29:09.91#ibcon#about to read 6, iclass 36, count 0 2006.201.10:29:09.91#ibcon#read 6, iclass 36, count 0 2006.201.10:29:09.91#ibcon#end of sib2, iclass 36, count 0 2006.201.10:29:09.91#ibcon#*mode == 0, iclass 36, count 0 2006.201.10:29:09.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.10:29:09.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:29:09.91#ibcon#*before write, iclass 36, count 0 2006.201.10:29:09.91#ibcon#enter sib2, iclass 36, count 0 2006.201.10:29:09.91#ibcon#flushed, iclass 36, count 0 2006.201.10:29:09.91#ibcon#about to write, iclass 36, count 0 2006.201.10:29:09.91#ibcon#wrote, iclass 36, count 0 2006.201.10:29:09.91#ibcon#about to read 3, iclass 36, count 0 2006.201.10:29:09.95#ibcon#read 3, iclass 36, count 0 2006.201.10:29:09.95#ibcon#about to read 4, iclass 36, count 0 2006.201.10:29:09.95#ibcon#read 4, iclass 36, count 0 2006.201.10:29:09.95#ibcon#about to read 5, iclass 36, count 0 2006.201.10:29:09.95#ibcon#read 5, iclass 36, count 0 2006.201.10:29:09.95#ibcon#about to read 6, iclass 36, count 0 2006.201.10:29:09.95#ibcon#read 6, iclass 36, count 0 2006.201.10:29:09.95#ibcon#end of sib2, iclass 36, count 0 2006.201.10:29:09.95#ibcon#*after write, iclass 36, count 0 2006.201.10:29:09.95#ibcon#*before return 0, iclass 36, count 0 2006.201.10:29:09.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:29:09.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:29:09.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.10:29:09.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.10:29:09.95$vck44/vb=8,4 2006.201.10:29:09.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.10:29:09.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.10:29:09.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:29:09.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:29:10.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:29:10.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:29:10.01#ibcon#enter wrdev, iclass 38, count 2 2006.201.10:29:10.01#ibcon#first serial, iclass 38, count 2 2006.201.10:29:10.01#ibcon#enter sib2, iclass 38, count 2 2006.201.10:29:10.01#ibcon#flushed, iclass 38, count 2 2006.201.10:29:10.01#ibcon#about to write, iclass 38, count 2 2006.201.10:29:10.01#ibcon#wrote, iclass 38, count 2 2006.201.10:29:10.01#ibcon#about to read 3, iclass 38, count 2 2006.201.10:29:10.03#ibcon#read 3, iclass 38, count 2 2006.201.10:29:10.03#ibcon#about to read 4, iclass 38, count 2 2006.201.10:29:10.03#ibcon#read 4, iclass 38, count 2 2006.201.10:29:10.03#ibcon#about to read 5, iclass 38, count 2 2006.201.10:29:10.03#ibcon#read 5, iclass 38, count 2 2006.201.10:29:10.03#ibcon#about to read 6, iclass 38, count 2 2006.201.10:29:10.03#ibcon#read 6, iclass 38, count 2 2006.201.10:29:10.03#ibcon#end of sib2, iclass 38, count 2 2006.201.10:29:10.03#ibcon#*mode == 0, iclass 38, count 2 2006.201.10:29:10.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.10:29:10.03#ibcon#[27=AT08-04\r\n] 2006.201.10:29:10.03#ibcon#*before write, iclass 38, count 2 2006.201.10:29:10.03#ibcon#enter sib2, iclass 38, count 2 2006.201.10:29:10.03#ibcon#flushed, iclass 38, count 2 2006.201.10:29:10.03#ibcon#about to write, iclass 38, count 2 2006.201.10:29:10.03#ibcon#wrote, iclass 38, count 2 2006.201.10:29:10.03#ibcon#about to read 3, iclass 38, count 2 2006.201.10:29:10.06#ibcon#read 3, iclass 38, count 2 2006.201.10:29:10.06#ibcon#about to read 4, iclass 38, count 2 2006.201.10:29:10.06#ibcon#read 4, iclass 38, count 2 2006.201.10:29:10.06#ibcon#about to read 5, iclass 38, count 2 2006.201.10:29:10.06#ibcon#read 5, iclass 38, count 2 2006.201.10:29:10.06#ibcon#about to read 6, iclass 38, count 2 2006.201.10:29:10.06#ibcon#read 6, iclass 38, count 2 2006.201.10:29:10.06#ibcon#end of sib2, iclass 38, count 2 2006.201.10:29:10.06#ibcon#*after write, iclass 38, count 2 2006.201.10:29:10.06#ibcon#*before return 0, iclass 38, count 2 2006.201.10:29:10.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:29:10.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:29:10.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.10:29:10.06#ibcon#ireg 7 cls_cnt 0 2006.201.10:29:10.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:29:10.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:29:10.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:29:10.18#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:29:10.18#ibcon#first serial, iclass 38, count 0 2006.201.10:29:10.18#ibcon#enter sib2, iclass 38, count 0 2006.201.10:29:10.18#ibcon#flushed, iclass 38, count 0 2006.201.10:29:10.18#ibcon#about to write, iclass 38, count 0 2006.201.10:29:10.18#ibcon#wrote, iclass 38, count 0 2006.201.10:29:10.18#ibcon#about to read 3, iclass 38, count 0 2006.201.10:29:10.21#ibcon#read 3, iclass 38, count 0 2006.201.10:29:10.21#ibcon#about to read 4, iclass 38, count 0 2006.201.10:29:10.21#ibcon#read 4, iclass 38, count 0 2006.201.10:29:10.21#ibcon#about to read 5, iclass 38, count 0 2006.201.10:29:10.21#ibcon#read 5, iclass 38, count 0 2006.201.10:29:10.21#ibcon#about to read 6, iclass 38, count 0 2006.201.10:29:10.21#ibcon#read 6, iclass 38, count 0 2006.201.10:29:10.21#ibcon#end of sib2, iclass 38, count 0 2006.201.10:29:10.21#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:29:10.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:29:10.21#ibcon#[27=USB\r\n] 2006.201.10:29:10.21#ibcon#*before write, iclass 38, count 0 2006.201.10:29:10.21#ibcon#enter sib2, iclass 38, count 0 2006.201.10:29:10.21#ibcon#flushed, iclass 38, count 0 2006.201.10:29:10.21#ibcon#about to write, iclass 38, count 0 2006.201.10:29:10.21#ibcon#wrote, iclass 38, count 0 2006.201.10:29:10.21#ibcon#about to read 3, iclass 38, count 0 2006.201.10:29:10.24#ibcon#read 3, iclass 38, count 0 2006.201.10:29:10.24#ibcon#about to read 4, iclass 38, count 0 2006.201.10:29:10.24#ibcon#read 4, iclass 38, count 0 2006.201.10:29:10.24#ibcon#about to read 5, iclass 38, count 0 2006.201.10:29:10.24#ibcon#read 5, iclass 38, count 0 2006.201.10:29:10.24#ibcon#about to read 6, iclass 38, count 0 2006.201.10:29:10.24#ibcon#read 6, iclass 38, count 0 2006.201.10:29:10.24#ibcon#end of sib2, iclass 38, count 0 2006.201.10:29:10.24#ibcon#*after write, iclass 38, count 0 2006.201.10:29:10.24#ibcon#*before return 0, iclass 38, count 0 2006.201.10:29:10.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:29:10.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:29:10.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:29:10.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:29:10.24$vck44/vabw=wide 2006.201.10:29:10.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.10:29:10.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.10:29:10.24#ibcon#ireg 8 cls_cnt 0 2006.201.10:29:10.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:29:10.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:29:10.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:29:10.24#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:29:10.24#ibcon#first serial, iclass 40, count 0 2006.201.10:29:10.24#ibcon#enter sib2, iclass 40, count 0 2006.201.10:29:10.24#ibcon#flushed, iclass 40, count 0 2006.201.10:29:10.24#ibcon#about to write, iclass 40, count 0 2006.201.10:29:10.24#ibcon#wrote, iclass 40, count 0 2006.201.10:29:10.24#ibcon#about to read 3, iclass 40, count 0 2006.201.10:29:10.26#ibcon#read 3, iclass 40, count 0 2006.201.10:29:10.26#ibcon#about to read 4, iclass 40, count 0 2006.201.10:29:10.26#ibcon#read 4, iclass 40, count 0 2006.201.10:29:10.26#ibcon#about to read 5, iclass 40, count 0 2006.201.10:29:10.26#ibcon#read 5, iclass 40, count 0 2006.201.10:29:10.26#ibcon#about to read 6, iclass 40, count 0 2006.201.10:29:10.26#ibcon#read 6, iclass 40, count 0 2006.201.10:29:10.26#ibcon#end of sib2, iclass 40, count 0 2006.201.10:29:10.26#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:29:10.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:29:10.26#ibcon#[25=BW32\r\n] 2006.201.10:29:10.26#ibcon#*before write, iclass 40, count 0 2006.201.10:29:10.26#ibcon#enter sib2, iclass 40, count 0 2006.201.10:29:10.26#ibcon#flushed, iclass 40, count 0 2006.201.10:29:10.26#ibcon#about to write, iclass 40, count 0 2006.201.10:29:10.26#ibcon#wrote, iclass 40, count 0 2006.201.10:29:10.26#ibcon#about to read 3, iclass 40, count 0 2006.201.10:29:10.29#ibcon#read 3, iclass 40, count 0 2006.201.10:29:10.29#ibcon#about to read 4, iclass 40, count 0 2006.201.10:29:10.29#ibcon#read 4, iclass 40, count 0 2006.201.10:29:10.29#ibcon#about to read 5, iclass 40, count 0 2006.201.10:29:10.29#ibcon#read 5, iclass 40, count 0 2006.201.10:29:10.29#ibcon#about to read 6, iclass 40, count 0 2006.201.10:29:10.29#ibcon#read 6, iclass 40, count 0 2006.201.10:29:10.29#ibcon#end of sib2, iclass 40, count 0 2006.201.10:29:10.29#ibcon#*after write, iclass 40, count 0 2006.201.10:29:10.29#ibcon#*before return 0, iclass 40, count 0 2006.201.10:29:10.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:29:10.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:29:10.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:29:10.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:29:10.29$vck44/vbbw=wide 2006.201.10:29:10.29#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.10:29:10.29#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.10:29:10.29#ibcon#ireg 8 cls_cnt 0 2006.201.10:29:10.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:29:10.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:29:10.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:29:10.36#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:29:10.36#ibcon#first serial, iclass 4, count 0 2006.201.10:29:10.36#ibcon#enter sib2, iclass 4, count 0 2006.201.10:29:10.36#ibcon#flushed, iclass 4, count 0 2006.201.10:29:10.36#ibcon#about to write, iclass 4, count 0 2006.201.10:29:10.36#ibcon#wrote, iclass 4, count 0 2006.201.10:29:10.36#ibcon#about to read 3, iclass 4, count 0 2006.201.10:29:10.38#ibcon#read 3, iclass 4, count 0 2006.201.10:29:10.38#ibcon#about to read 4, iclass 4, count 0 2006.201.10:29:10.38#ibcon#read 4, iclass 4, count 0 2006.201.10:29:10.38#ibcon#about to read 5, iclass 4, count 0 2006.201.10:29:10.38#ibcon#read 5, iclass 4, count 0 2006.201.10:29:10.38#ibcon#about to read 6, iclass 4, count 0 2006.201.10:29:10.38#ibcon#read 6, iclass 4, count 0 2006.201.10:29:10.38#ibcon#end of sib2, iclass 4, count 0 2006.201.10:29:10.38#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:29:10.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:29:10.38#ibcon#[27=BW32\r\n] 2006.201.10:29:10.38#ibcon#*before write, iclass 4, count 0 2006.201.10:29:10.38#ibcon#enter sib2, iclass 4, count 0 2006.201.10:29:10.38#ibcon#flushed, iclass 4, count 0 2006.201.10:29:10.38#ibcon#about to write, iclass 4, count 0 2006.201.10:29:10.38#ibcon#wrote, iclass 4, count 0 2006.201.10:29:10.38#ibcon#about to read 3, iclass 4, count 0 2006.201.10:29:10.41#ibcon#read 3, iclass 4, count 0 2006.201.10:29:10.41#ibcon#about to read 4, iclass 4, count 0 2006.201.10:29:10.41#ibcon#read 4, iclass 4, count 0 2006.201.10:29:10.41#ibcon#about to read 5, iclass 4, count 0 2006.201.10:29:10.41#ibcon#read 5, iclass 4, count 0 2006.201.10:29:10.41#ibcon#about to read 6, iclass 4, count 0 2006.201.10:29:10.41#ibcon#read 6, iclass 4, count 0 2006.201.10:29:10.41#ibcon#end of sib2, iclass 4, count 0 2006.201.10:29:10.41#ibcon#*after write, iclass 4, count 0 2006.201.10:29:10.41#ibcon#*before return 0, iclass 4, count 0 2006.201.10:29:10.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:29:10.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:29:10.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:29:10.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:29:10.41$setupk4/ifdk4 2006.201.10:29:10.41$ifdk4/lo= 2006.201.10:29:10.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:29:10.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:29:10.41$ifdk4/patch= 2006.201.10:29:10.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:29:10.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:29:10.41$setupk4/!*+20s 2006.201.10:29:17.40#abcon#<5=/05 2.1 3.6 21.74 971003.6\r\n> 2006.201.10:29:17.42#abcon#{5=INTERFACE CLEAR} 2006.201.10:29:17.48#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:29:24.88$setupk4/"tpicd 2006.201.10:29:24.88$setupk4/echo=off 2006.201.10:29:24.88$setupk4/xlog=off 2006.201.10:29:24.88:!2006.201.10:31:01 2006.201.10:29:43.14#trakl#Source acquired 2006.201.10:29:45.14#flagr#flagr/antenna,acquired 2006.201.10:31:01.00:preob 2006.201.10:31:01.14/onsource/TRACKING 2006.201.10:31:01.14:!2006.201.10:31:11 2006.201.10:31:11.00:"tape 2006.201.10:31:11.00:"st=record 2006.201.10:31:11.00:data_valid=on 2006.201.10:31:11.00:midob 2006.201.10:31:12.14/onsource/TRACKING 2006.201.10:31:12.14/wx/21.71,1003.6,97 2006.201.10:31:12.19/cable/+6.4684E-03 2006.201.10:31:13.28/va/01,08,usb,yes,33,36 2006.201.10:31:13.28/va/02,07,usb,yes,36,37 2006.201.10:31:13.28/va/03,08,usb,yes,32,34 2006.201.10:31:13.28/va/04,07,usb,yes,37,39 2006.201.10:31:13.28/va/05,04,usb,yes,33,33 2006.201.10:31:13.28/va/06,05,usb,yes,33,33 2006.201.10:31:13.28/va/07,05,usb,yes,32,33 2006.201.10:31:13.28/va/08,04,usb,yes,31,38 2006.201.10:31:13.51/valo/01,524.99,yes,locked 2006.201.10:31:13.51/valo/02,534.99,yes,locked 2006.201.10:31:13.51/valo/03,564.99,yes,locked 2006.201.10:31:13.51/valo/04,624.99,yes,locked 2006.201.10:31:13.51/valo/05,734.99,yes,locked 2006.201.10:31:13.51/valo/06,814.99,yes,locked 2006.201.10:31:13.51/valo/07,864.99,yes,locked 2006.201.10:31:13.51/valo/08,884.99,yes,locked 2006.201.10:31:14.60/vb/01,04,usb,yes,31,50 2006.201.10:31:14.60/vb/02,05,usb,yes,29,48 2006.201.10:31:14.60/vb/03,04,usb,yes,31,37 2006.201.10:31:14.60/vb/04,05,usb,yes,30,29 2006.201.10:31:14.60/vb/05,04,usb,yes,29,30 2006.201.10:31:14.60/vb/06,04,usb,yes,34,29 2006.201.10:31:14.60/vb/07,04,usb,yes,32,33 2006.201.10:31:14.60/vb/08,04,usb,yes,29,33 2006.201.10:31:14.84/vblo/01,629.99,yes,locked 2006.201.10:31:14.84/vblo/02,634.99,yes,locked 2006.201.10:31:14.84/vblo/03,649.99,yes,locked 2006.201.10:31:14.84/vblo/04,679.99,yes,locked 2006.201.10:31:14.84/vblo/05,709.99,yes,locked 2006.201.10:31:14.84/vblo/06,719.99,yes,locked 2006.201.10:31:14.84/vblo/07,734.99,yes,locked 2006.201.10:31:14.84/vblo/08,744.99,yes,locked 2006.201.10:31:14.99/vabw/8 2006.201.10:31:15.14/vbbw/8 2006.201.10:31:15.23/xfe/off,on,16.0 2006.201.10:31:15.62/ifatt/23,28,28,28 2006.201.10:31:16.05/fmout-gps/S +4.57E-07 2006.201.10:31:16.10:!2006.201.10:36:11 2006.201.10:36:11.00:data_valid=off 2006.201.10:36:11.00:"et 2006.201.10:36:11.00:!+3s 2006.201.10:36:14.02:"tape 2006.201.10:36:14.02:postob 2006.201.10:36:14.23/cable/+6.4683E-03 2006.201.10:36:14.23/wx/21.66,1003.7,97 2006.201.10:36:14.31/fmout-gps/S +4.55E-07 2006.201.10:36:14.31:scan_name=201-1037,jd0607,220 2006.201.10:36:14.31:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.201.10:36:15.14#flagr#flagr/antenna,new-source 2006.201.10:36:15.14:checkk5 2006.201.10:36:15.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:36:15.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:36:16.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:36:16.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:36:16.99/chk_obsdata//k5ts1/T2011031??a.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.201.10:36:17.36/chk_obsdata//k5ts2/T2011031??b.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.201.10:36:17.73/chk_obsdata//k5ts3/T2011031??c.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.201.10:36:18.10/chk_obsdata//k5ts4/T2011031??d.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.201.10:36:18.80/k5log//k5ts1_log_newline 2006.201.10:36:19.50/k5log//k5ts2_log_newline 2006.201.10:36:20.19/k5log//k5ts3_log_newline 2006.201.10:36:20.89/k5log//k5ts4_log_newline 2006.201.10:36:20.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:36:20.91:setupk4=1 2006.201.10:36:20.91$setupk4/echo=on 2006.201.10:36:20.91$setupk4/pcalon 2006.201.10:36:20.91$pcalon/"no phase cal control is implemented here 2006.201.10:36:20.91$setupk4/"tpicd=stop 2006.201.10:36:20.91$setupk4/"rec=synch_on 2006.201.10:36:20.91$setupk4/"rec_mode=128 2006.201.10:36:20.91$setupk4/!* 2006.201.10:36:20.91$setupk4/recpk4 2006.201.10:36:20.91$recpk4/recpatch= 2006.201.10:36:20.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:36:20.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:36:20.92$setupk4/vck44 2006.201.10:36:20.92$vck44/valo=1,524.99 2006.201.10:36:20.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.10:36:20.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.10:36:20.92#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:20.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:20.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:20.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:20.92#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:36:20.92#ibcon#first serial, iclass 35, count 0 2006.201.10:36:20.92#ibcon#enter sib2, iclass 35, count 0 2006.201.10:36:20.92#ibcon#flushed, iclass 35, count 0 2006.201.10:36:20.92#ibcon#about to write, iclass 35, count 0 2006.201.10:36:20.92#ibcon#wrote, iclass 35, count 0 2006.201.10:36:20.92#ibcon#about to read 3, iclass 35, count 0 2006.201.10:36:20.95#ibcon#read 3, iclass 35, count 0 2006.201.10:36:20.95#ibcon#about to read 4, iclass 35, count 0 2006.201.10:36:20.95#ibcon#read 4, iclass 35, count 0 2006.201.10:36:20.95#ibcon#about to read 5, iclass 35, count 0 2006.201.10:36:20.95#ibcon#read 5, iclass 35, count 0 2006.201.10:36:20.95#ibcon#about to read 6, iclass 35, count 0 2006.201.10:36:20.95#ibcon#read 6, iclass 35, count 0 2006.201.10:36:20.95#ibcon#end of sib2, iclass 35, count 0 2006.201.10:36:20.95#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:36:20.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:36:20.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:36:20.95#ibcon#*before write, iclass 35, count 0 2006.201.10:36:20.95#ibcon#enter sib2, iclass 35, count 0 2006.201.10:36:20.95#ibcon#flushed, iclass 35, count 0 2006.201.10:36:20.95#ibcon#about to write, iclass 35, count 0 2006.201.10:36:20.95#ibcon#wrote, iclass 35, count 0 2006.201.10:36:20.95#ibcon#about to read 3, iclass 35, count 0 2006.201.10:36:21.01#ibcon#read 3, iclass 35, count 0 2006.201.10:36:21.01#ibcon#about to read 4, iclass 35, count 0 2006.201.10:36:21.01#ibcon#read 4, iclass 35, count 0 2006.201.10:36:21.01#ibcon#about to read 5, iclass 35, count 0 2006.201.10:36:21.01#ibcon#read 5, iclass 35, count 0 2006.201.10:36:21.01#ibcon#about to read 6, iclass 35, count 0 2006.201.10:36:21.01#ibcon#read 6, iclass 35, count 0 2006.201.10:36:21.01#ibcon#end of sib2, iclass 35, count 0 2006.201.10:36:21.01#ibcon#*after write, iclass 35, count 0 2006.201.10:36:21.01#ibcon#*before return 0, iclass 35, count 0 2006.201.10:36:21.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:21.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:21.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:36:21.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:36:21.01$vck44/va=1,8 2006.201.10:36:21.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.10:36:21.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.10:36:21.01#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:21.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:21.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:21.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:21.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.10:36:21.01#ibcon#first serial, iclass 37, count 2 2006.201.10:36:21.01#ibcon#enter sib2, iclass 37, count 2 2006.201.10:36:21.01#ibcon#flushed, iclass 37, count 2 2006.201.10:36:21.01#ibcon#about to write, iclass 37, count 2 2006.201.10:36:21.01#ibcon#wrote, iclass 37, count 2 2006.201.10:36:21.01#ibcon#about to read 3, iclass 37, count 2 2006.201.10:36:21.03#ibcon#read 3, iclass 37, count 2 2006.201.10:36:21.03#ibcon#about to read 4, iclass 37, count 2 2006.201.10:36:21.03#ibcon#read 4, iclass 37, count 2 2006.201.10:36:21.03#ibcon#about to read 5, iclass 37, count 2 2006.201.10:36:21.03#ibcon#read 5, iclass 37, count 2 2006.201.10:36:21.03#ibcon#about to read 6, iclass 37, count 2 2006.201.10:36:21.03#ibcon#read 6, iclass 37, count 2 2006.201.10:36:21.03#ibcon#end of sib2, iclass 37, count 2 2006.201.10:36:21.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.10:36:21.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.10:36:21.03#ibcon#[25=AT01-08\r\n] 2006.201.10:36:21.03#ibcon#*before write, iclass 37, count 2 2006.201.10:36:21.03#ibcon#enter sib2, iclass 37, count 2 2006.201.10:36:21.03#ibcon#flushed, iclass 37, count 2 2006.201.10:36:21.03#ibcon#about to write, iclass 37, count 2 2006.201.10:36:21.03#ibcon#wrote, iclass 37, count 2 2006.201.10:36:21.03#ibcon#about to read 3, iclass 37, count 2 2006.201.10:36:21.07#ibcon#read 3, iclass 37, count 2 2006.201.10:36:21.07#ibcon#about to read 4, iclass 37, count 2 2006.201.10:36:21.07#ibcon#read 4, iclass 37, count 2 2006.201.10:36:21.07#ibcon#about to read 5, iclass 37, count 2 2006.201.10:36:21.07#ibcon#read 5, iclass 37, count 2 2006.201.10:36:21.07#ibcon#about to read 6, iclass 37, count 2 2006.201.10:36:21.07#ibcon#read 6, iclass 37, count 2 2006.201.10:36:21.07#ibcon#end of sib2, iclass 37, count 2 2006.201.10:36:21.07#ibcon#*after write, iclass 37, count 2 2006.201.10:36:21.07#ibcon#*before return 0, iclass 37, count 2 2006.201.10:36:21.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:21.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:21.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.10:36:21.07#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:21.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:21.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:21.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:21.19#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:36:21.19#ibcon#first serial, iclass 37, count 0 2006.201.10:36:21.19#ibcon#enter sib2, iclass 37, count 0 2006.201.10:36:21.19#ibcon#flushed, iclass 37, count 0 2006.201.10:36:21.19#ibcon#about to write, iclass 37, count 0 2006.201.10:36:21.19#ibcon#wrote, iclass 37, count 0 2006.201.10:36:21.19#ibcon#about to read 3, iclass 37, count 0 2006.201.10:36:21.22#ibcon#read 3, iclass 37, count 0 2006.201.10:36:21.22#ibcon#about to read 4, iclass 37, count 0 2006.201.10:36:21.22#ibcon#read 4, iclass 37, count 0 2006.201.10:36:21.22#ibcon#about to read 5, iclass 37, count 0 2006.201.10:36:21.22#ibcon#read 5, iclass 37, count 0 2006.201.10:36:21.22#ibcon#about to read 6, iclass 37, count 0 2006.201.10:36:21.22#ibcon#read 6, iclass 37, count 0 2006.201.10:36:21.22#ibcon#end of sib2, iclass 37, count 0 2006.201.10:36:21.22#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:36:21.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:36:21.22#ibcon#[25=USB\r\n] 2006.201.10:36:21.22#ibcon#*before write, iclass 37, count 0 2006.201.10:36:21.22#ibcon#enter sib2, iclass 37, count 0 2006.201.10:36:21.22#ibcon#flushed, iclass 37, count 0 2006.201.10:36:21.22#ibcon#about to write, iclass 37, count 0 2006.201.10:36:21.22#ibcon#wrote, iclass 37, count 0 2006.201.10:36:21.22#ibcon#about to read 3, iclass 37, count 0 2006.201.10:36:21.25#ibcon#read 3, iclass 37, count 0 2006.201.10:36:21.25#ibcon#about to read 4, iclass 37, count 0 2006.201.10:36:21.25#ibcon#read 4, iclass 37, count 0 2006.201.10:36:21.25#ibcon#about to read 5, iclass 37, count 0 2006.201.10:36:21.25#ibcon#read 5, iclass 37, count 0 2006.201.10:36:21.25#ibcon#about to read 6, iclass 37, count 0 2006.201.10:36:21.25#ibcon#read 6, iclass 37, count 0 2006.201.10:36:21.25#ibcon#end of sib2, iclass 37, count 0 2006.201.10:36:21.25#ibcon#*after write, iclass 37, count 0 2006.201.10:36:21.25#ibcon#*before return 0, iclass 37, count 0 2006.201.10:36:21.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:21.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:21.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:36:21.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:36:21.25$vck44/valo=2,534.99 2006.201.10:36:21.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.10:36:21.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.10:36:21.25#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:21.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:21.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:21.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:21.25#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:36:21.25#ibcon#first serial, iclass 39, count 0 2006.201.10:36:21.25#ibcon#enter sib2, iclass 39, count 0 2006.201.10:36:21.25#ibcon#flushed, iclass 39, count 0 2006.201.10:36:21.25#ibcon#about to write, iclass 39, count 0 2006.201.10:36:21.25#ibcon#wrote, iclass 39, count 0 2006.201.10:36:21.25#ibcon#about to read 3, iclass 39, count 0 2006.201.10:36:21.27#ibcon#read 3, iclass 39, count 0 2006.201.10:36:21.27#ibcon#about to read 4, iclass 39, count 0 2006.201.10:36:21.27#ibcon#read 4, iclass 39, count 0 2006.201.10:36:21.27#ibcon#about to read 5, iclass 39, count 0 2006.201.10:36:21.27#ibcon#read 5, iclass 39, count 0 2006.201.10:36:21.27#ibcon#about to read 6, iclass 39, count 0 2006.201.10:36:21.27#ibcon#read 6, iclass 39, count 0 2006.201.10:36:21.27#ibcon#end of sib2, iclass 39, count 0 2006.201.10:36:21.27#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:36:21.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:36:21.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:36:21.27#ibcon#*before write, iclass 39, count 0 2006.201.10:36:21.27#ibcon#enter sib2, iclass 39, count 0 2006.201.10:36:21.27#ibcon#flushed, iclass 39, count 0 2006.201.10:36:21.27#ibcon#about to write, iclass 39, count 0 2006.201.10:36:21.27#ibcon#wrote, iclass 39, count 0 2006.201.10:36:21.27#ibcon#about to read 3, iclass 39, count 0 2006.201.10:36:21.31#ibcon#read 3, iclass 39, count 0 2006.201.10:36:21.31#ibcon#about to read 4, iclass 39, count 0 2006.201.10:36:21.31#ibcon#read 4, iclass 39, count 0 2006.201.10:36:21.31#ibcon#about to read 5, iclass 39, count 0 2006.201.10:36:21.31#ibcon#read 5, iclass 39, count 0 2006.201.10:36:21.31#ibcon#about to read 6, iclass 39, count 0 2006.201.10:36:21.31#ibcon#read 6, iclass 39, count 0 2006.201.10:36:21.31#ibcon#end of sib2, iclass 39, count 0 2006.201.10:36:21.31#ibcon#*after write, iclass 39, count 0 2006.201.10:36:21.31#ibcon#*before return 0, iclass 39, count 0 2006.201.10:36:21.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:21.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:21.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:36:21.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:36:21.31$vck44/va=2,7 2006.201.10:36:21.31#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.10:36:21.31#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.10:36:21.31#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:21.31#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:21.37#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:21.37#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:21.37#ibcon#enter wrdev, iclass 2, count 2 2006.201.10:36:21.37#ibcon#first serial, iclass 2, count 2 2006.201.10:36:21.37#ibcon#enter sib2, iclass 2, count 2 2006.201.10:36:21.37#ibcon#flushed, iclass 2, count 2 2006.201.10:36:21.37#ibcon#about to write, iclass 2, count 2 2006.201.10:36:21.37#ibcon#wrote, iclass 2, count 2 2006.201.10:36:21.37#ibcon#about to read 3, iclass 2, count 2 2006.201.10:36:21.39#ibcon#read 3, iclass 2, count 2 2006.201.10:36:21.39#ibcon#about to read 4, iclass 2, count 2 2006.201.10:36:21.39#ibcon#read 4, iclass 2, count 2 2006.201.10:36:21.39#ibcon#about to read 5, iclass 2, count 2 2006.201.10:36:21.39#ibcon#read 5, iclass 2, count 2 2006.201.10:36:21.39#ibcon#about to read 6, iclass 2, count 2 2006.201.10:36:21.39#ibcon#read 6, iclass 2, count 2 2006.201.10:36:21.39#ibcon#end of sib2, iclass 2, count 2 2006.201.10:36:21.39#ibcon#*mode == 0, iclass 2, count 2 2006.201.10:36:21.39#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.10:36:21.39#ibcon#[25=AT02-07\r\n] 2006.201.10:36:21.39#ibcon#*before write, iclass 2, count 2 2006.201.10:36:21.39#ibcon#enter sib2, iclass 2, count 2 2006.201.10:36:21.39#ibcon#flushed, iclass 2, count 2 2006.201.10:36:21.39#ibcon#about to write, iclass 2, count 2 2006.201.10:36:21.39#ibcon#wrote, iclass 2, count 2 2006.201.10:36:21.39#ibcon#about to read 3, iclass 2, count 2 2006.201.10:36:21.42#ibcon#read 3, iclass 2, count 2 2006.201.10:36:21.42#ibcon#about to read 4, iclass 2, count 2 2006.201.10:36:21.42#ibcon#read 4, iclass 2, count 2 2006.201.10:36:21.42#ibcon#about to read 5, iclass 2, count 2 2006.201.10:36:21.42#ibcon#read 5, iclass 2, count 2 2006.201.10:36:21.42#ibcon#about to read 6, iclass 2, count 2 2006.201.10:36:21.42#ibcon#read 6, iclass 2, count 2 2006.201.10:36:21.42#ibcon#end of sib2, iclass 2, count 2 2006.201.10:36:21.42#ibcon#*after write, iclass 2, count 2 2006.201.10:36:21.42#ibcon#*before return 0, iclass 2, count 2 2006.201.10:36:21.42#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:21.42#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:21.42#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.10:36:21.42#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:21.42#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:21.54#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:21.54#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:21.54#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:36:21.54#ibcon#first serial, iclass 2, count 0 2006.201.10:36:21.54#ibcon#enter sib2, iclass 2, count 0 2006.201.10:36:21.54#ibcon#flushed, iclass 2, count 0 2006.201.10:36:21.54#ibcon#about to write, iclass 2, count 0 2006.201.10:36:21.54#ibcon#wrote, iclass 2, count 0 2006.201.10:36:21.54#ibcon#about to read 3, iclass 2, count 0 2006.201.10:36:21.56#ibcon#read 3, iclass 2, count 0 2006.201.10:36:21.56#ibcon#about to read 4, iclass 2, count 0 2006.201.10:36:21.56#ibcon#read 4, iclass 2, count 0 2006.201.10:36:21.56#ibcon#about to read 5, iclass 2, count 0 2006.201.10:36:21.56#ibcon#read 5, iclass 2, count 0 2006.201.10:36:21.56#ibcon#about to read 6, iclass 2, count 0 2006.201.10:36:21.56#ibcon#read 6, iclass 2, count 0 2006.201.10:36:21.56#ibcon#end of sib2, iclass 2, count 0 2006.201.10:36:21.56#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:36:21.56#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:36:21.56#ibcon#[25=USB\r\n] 2006.201.10:36:21.56#ibcon#*before write, iclass 2, count 0 2006.201.10:36:21.56#ibcon#enter sib2, iclass 2, count 0 2006.201.10:36:21.56#ibcon#flushed, iclass 2, count 0 2006.201.10:36:21.56#ibcon#about to write, iclass 2, count 0 2006.201.10:36:21.56#ibcon#wrote, iclass 2, count 0 2006.201.10:36:21.56#ibcon#about to read 3, iclass 2, count 0 2006.201.10:36:21.59#ibcon#read 3, iclass 2, count 0 2006.201.10:36:21.59#ibcon#about to read 4, iclass 2, count 0 2006.201.10:36:21.59#ibcon#read 4, iclass 2, count 0 2006.201.10:36:21.59#ibcon#about to read 5, iclass 2, count 0 2006.201.10:36:21.59#ibcon#read 5, iclass 2, count 0 2006.201.10:36:21.59#ibcon#about to read 6, iclass 2, count 0 2006.201.10:36:21.59#ibcon#read 6, iclass 2, count 0 2006.201.10:36:21.59#ibcon#end of sib2, iclass 2, count 0 2006.201.10:36:21.59#ibcon#*after write, iclass 2, count 0 2006.201.10:36:21.59#ibcon#*before return 0, iclass 2, count 0 2006.201.10:36:21.59#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:21.59#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:21.59#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:36:21.59#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:36:21.59$vck44/valo=3,564.99 2006.201.10:36:21.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.10:36:21.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.10:36:21.59#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:21.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:36:21.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:36:21.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:36:21.59#ibcon#enter wrdev, iclass 5, count 0 2006.201.10:36:21.59#ibcon#first serial, iclass 5, count 0 2006.201.10:36:21.59#ibcon#enter sib2, iclass 5, count 0 2006.201.10:36:21.59#ibcon#flushed, iclass 5, count 0 2006.201.10:36:21.59#ibcon#about to write, iclass 5, count 0 2006.201.10:36:21.59#ibcon#wrote, iclass 5, count 0 2006.201.10:36:21.59#ibcon#about to read 3, iclass 5, count 0 2006.201.10:36:21.61#ibcon#read 3, iclass 5, count 0 2006.201.10:36:21.61#ibcon#about to read 4, iclass 5, count 0 2006.201.10:36:21.61#ibcon#read 4, iclass 5, count 0 2006.201.10:36:21.61#ibcon#about to read 5, iclass 5, count 0 2006.201.10:36:21.61#ibcon#read 5, iclass 5, count 0 2006.201.10:36:21.61#ibcon#about to read 6, iclass 5, count 0 2006.201.10:36:21.61#ibcon#read 6, iclass 5, count 0 2006.201.10:36:21.61#ibcon#end of sib2, iclass 5, count 0 2006.201.10:36:21.61#ibcon#*mode == 0, iclass 5, count 0 2006.201.10:36:21.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.10:36:21.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:36:21.61#ibcon#*before write, iclass 5, count 0 2006.201.10:36:21.61#ibcon#enter sib2, iclass 5, count 0 2006.201.10:36:21.61#ibcon#flushed, iclass 5, count 0 2006.201.10:36:21.61#ibcon#about to write, iclass 5, count 0 2006.201.10:36:21.61#ibcon#wrote, iclass 5, count 0 2006.201.10:36:21.61#ibcon#about to read 3, iclass 5, count 0 2006.201.10:36:21.66#ibcon#read 3, iclass 5, count 0 2006.201.10:36:21.66#ibcon#about to read 4, iclass 5, count 0 2006.201.10:36:21.66#ibcon#read 4, iclass 5, count 0 2006.201.10:36:21.66#ibcon#about to read 5, iclass 5, count 0 2006.201.10:36:21.66#ibcon#read 5, iclass 5, count 0 2006.201.10:36:21.66#ibcon#about to read 6, iclass 5, count 0 2006.201.10:36:21.66#ibcon#read 6, iclass 5, count 0 2006.201.10:36:21.66#ibcon#end of sib2, iclass 5, count 0 2006.201.10:36:21.66#ibcon#*after write, iclass 5, count 0 2006.201.10:36:21.66#ibcon#*before return 0, iclass 5, count 0 2006.201.10:36:21.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:36:21.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:36:21.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.10:36:21.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.10:36:21.66$vck44/va=3,8 2006.201.10:36:21.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.10:36:21.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.10:36:21.66#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:21.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:36:21.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:36:21.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:36:21.71#ibcon#enter wrdev, iclass 7, count 2 2006.201.10:36:21.71#ibcon#first serial, iclass 7, count 2 2006.201.10:36:21.71#ibcon#enter sib2, iclass 7, count 2 2006.201.10:36:21.71#ibcon#flushed, iclass 7, count 2 2006.201.10:36:21.71#ibcon#about to write, iclass 7, count 2 2006.201.10:36:21.71#ibcon#wrote, iclass 7, count 2 2006.201.10:36:21.71#ibcon#about to read 3, iclass 7, count 2 2006.201.10:36:21.73#ibcon#read 3, iclass 7, count 2 2006.201.10:36:21.73#ibcon#about to read 4, iclass 7, count 2 2006.201.10:36:21.73#ibcon#read 4, iclass 7, count 2 2006.201.10:36:21.73#ibcon#about to read 5, iclass 7, count 2 2006.201.10:36:21.73#ibcon#read 5, iclass 7, count 2 2006.201.10:36:21.73#ibcon#about to read 6, iclass 7, count 2 2006.201.10:36:21.73#ibcon#read 6, iclass 7, count 2 2006.201.10:36:21.73#ibcon#end of sib2, iclass 7, count 2 2006.201.10:36:21.73#ibcon#*mode == 0, iclass 7, count 2 2006.201.10:36:21.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.10:36:21.73#ibcon#[25=AT03-08\r\n] 2006.201.10:36:21.73#ibcon#*before write, iclass 7, count 2 2006.201.10:36:21.73#ibcon#enter sib2, iclass 7, count 2 2006.201.10:36:21.73#ibcon#flushed, iclass 7, count 2 2006.201.10:36:21.73#ibcon#about to write, iclass 7, count 2 2006.201.10:36:21.73#ibcon#wrote, iclass 7, count 2 2006.201.10:36:21.73#ibcon#about to read 3, iclass 7, count 2 2006.201.10:36:21.76#ibcon#read 3, iclass 7, count 2 2006.201.10:36:21.76#ibcon#about to read 4, iclass 7, count 2 2006.201.10:36:21.76#ibcon#read 4, iclass 7, count 2 2006.201.10:36:21.76#ibcon#about to read 5, iclass 7, count 2 2006.201.10:36:21.76#ibcon#read 5, iclass 7, count 2 2006.201.10:36:21.76#ibcon#about to read 6, iclass 7, count 2 2006.201.10:36:21.76#ibcon#read 6, iclass 7, count 2 2006.201.10:36:21.76#ibcon#end of sib2, iclass 7, count 2 2006.201.10:36:21.76#ibcon#*after write, iclass 7, count 2 2006.201.10:36:21.76#ibcon#*before return 0, iclass 7, count 2 2006.201.10:36:21.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:36:21.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:36:21.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.10:36:21.76#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:21.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:36:21.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:36:21.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:36:21.88#ibcon#enter wrdev, iclass 7, count 0 2006.201.10:36:21.88#ibcon#first serial, iclass 7, count 0 2006.201.10:36:21.88#ibcon#enter sib2, iclass 7, count 0 2006.201.10:36:21.88#ibcon#flushed, iclass 7, count 0 2006.201.10:36:21.88#ibcon#about to write, iclass 7, count 0 2006.201.10:36:21.88#ibcon#wrote, iclass 7, count 0 2006.201.10:36:21.88#ibcon#about to read 3, iclass 7, count 0 2006.201.10:36:21.90#ibcon#read 3, iclass 7, count 0 2006.201.10:36:21.90#ibcon#about to read 4, iclass 7, count 0 2006.201.10:36:21.90#ibcon#read 4, iclass 7, count 0 2006.201.10:36:21.90#ibcon#about to read 5, iclass 7, count 0 2006.201.10:36:21.90#ibcon#read 5, iclass 7, count 0 2006.201.10:36:21.90#ibcon#about to read 6, iclass 7, count 0 2006.201.10:36:21.90#ibcon#read 6, iclass 7, count 0 2006.201.10:36:21.90#ibcon#end of sib2, iclass 7, count 0 2006.201.10:36:21.90#ibcon#*mode == 0, iclass 7, count 0 2006.201.10:36:21.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.10:36:21.90#ibcon#[25=USB\r\n] 2006.201.10:36:21.90#ibcon#*before write, iclass 7, count 0 2006.201.10:36:21.90#ibcon#enter sib2, iclass 7, count 0 2006.201.10:36:21.90#ibcon#flushed, iclass 7, count 0 2006.201.10:36:21.90#ibcon#about to write, iclass 7, count 0 2006.201.10:36:21.90#ibcon#wrote, iclass 7, count 0 2006.201.10:36:21.90#ibcon#about to read 3, iclass 7, count 0 2006.201.10:36:21.93#ibcon#read 3, iclass 7, count 0 2006.201.10:36:21.93#ibcon#about to read 4, iclass 7, count 0 2006.201.10:36:21.93#ibcon#read 4, iclass 7, count 0 2006.201.10:36:21.93#ibcon#about to read 5, iclass 7, count 0 2006.201.10:36:21.93#ibcon#read 5, iclass 7, count 0 2006.201.10:36:21.93#ibcon#about to read 6, iclass 7, count 0 2006.201.10:36:21.93#ibcon#read 6, iclass 7, count 0 2006.201.10:36:21.93#ibcon#end of sib2, iclass 7, count 0 2006.201.10:36:21.93#ibcon#*after write, iclass 7, count 0 2006.201.10:36:21.93#ibcon#*before return 0, iclass 7, count 0 2006.201.10:36:21.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:36:21.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:36:21.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.10:36:21.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.10:36:21.93$vck44/valo=4,624.99 2006.201.10:36:21.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.10:36:21.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.10:36:21.93#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:21.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:36:21.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:36:21.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:36:21.93#ibcon#enter wrdev, iclass 11, count 0 2006.201.10:36:21.93#ibcon#first serial, iclass 11, count 0 2006.201.10:36:21.93#ibcon#enter sib2, iclass 11, count 0 2006.201.10:36:21.93#ibcon#flushed, iclass 11, count 0 2006.201.10:36:21.93#ibcon#about to write, iclass 11, count 0 2006.201.10:36:21.93#ibcon#wrote, iclass 11, count 0 2006.201.10:36:21.93#ibcon#about to read 3, iclass 11, count 0 2006.201.10:36:21.95#ibcon#read 3, iclass 11, count 0 2006.201.10:36:21.95#ibcon#about to read 4, iclass 11, count 0 2006.201.10:36:21.95#ibcon#read 4, iclass 11, count 0 2006.201.10:36:21.95#ibcon#about to read 5, iclass 11, count 0 2006.201.10:36:21.95#ibcon#read 5, iclass 11, count 0 2006.201.10:36:21.95#ibcon#about to read 6, iclass 11, count 0 2006.201.10:36:21.95#ibcon#read 6, iclass 11, count 0 2006.201.10:36:21.95#ibcon#end of sib2, iclass 11, count 0 2006.201.10:36:21.95#ibcon#*mode == 0, iclass 11, count 0 2006.201.10:36:21.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.10:36:21.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:36:21.95#ibcon#*before write, iclass 11, count 0 2006.201.10:36:21.95#ibcon#enter sib2, iclass 11, count 0 2006.201.10:36:21.95#ibcon#flushed, iclass 11, count 0 2006.201.10:36:21.95#ibcon#about to write, iclass 11, count 0 2006.201.10:36:21.95#ibcon#wrote, iclass 11, count 0 2006.201.10:36:21.95#ibcon#about to read 3, iclass 11, count 0 2006.201.10:36:21.99#ibcon#read 3, iclass 11, count 0 2006.201.10:36:21.99#ibcon#about to read 4, iclass 11, count 0 2006.201.10:36:21.99#ibcon#read 4, iclass 11, count 0 2006.201.10:36:21.99#ibcon#about to read 5, iclass 11, count 0 2006.201.10:36:21.99#ibcon#read 5, iclass 11, count 0 2006.201.10:36:21.99#ibcon#about to read 6, iclass 11, count 0 2006.201.10:36:21.99#ibcon#read 6, iclass 11, count 0 2006.201.10:36:21.99#ibcon#end of sib2, iclass 11, count 0 2006.201.10:36:21.99#ibcon#*after write, iclass 11, count 0 2006.201.10:36:21.99#ibcon#*before return 0, iclass 11, count 0 2006.201.10:36:21.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:36:21.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:36:21.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.10:36:21.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.10:36:21.99$vck44/va=4,7 2006.201.10:36:21.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.10:36:21.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.10:36:21.99#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:21.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:36:22.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:36:22.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:36:22.05#ibcon#enter wrdev, iclass 13, count 2 2006.201.10:36:22.05#ibcon#first serial, iclass 13, count 2 2006.201.10:36:22.05#ibcon#enter sib2, iclass 13, count 2 2006.201.10:36:22.05#ibcon#flushed, iclass 13, count 2 2006.201.10:36:22.05#ibcon#about to write, iclass 13, count 2 2006.201.10:36:22.05#ibcon#wrote, iclass 13, count 2 2006.201.10:36:22.05#ibcon#about to read 3, iclass 13, count 2 2006.201.10:36:22.07#ibcon#read 3, iclass 13, count 2 2006.201.10:36:22.07#ibcon#about to read 4, iclass 13, count 2 2006.201.10:36:22.07#ibcon#read 4, iclass 13, count 2 2006.201.10:36:22.07#ibcon#about to read 5, iclass 13, count 2 2006.201.10:36:22.07#ibcon#read 5, iclass 13, count 2 2006.201.10:36:22.07#ibcon#about to read 6, iclass 13, count 2 2006.201.10:36:22.07#ibcon#read 6, iclass 13, count 2 2006.201.10:36:22.07#ibcon#end of sib2, iclass 13, count 2 2006.201.10:36:22.07#ibcon#*mode == 0, iclass 13, count 2 2006.201.10:36:22.07#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.10:36:22.07#ibcon#[25=AT04-07\r\n] 2006.201.10:36:22.07#ibcon#*before write, iclass 13, count 2 2006.201.10:36:22.07#ibcon#enter sib2, iclass 13, count 2 2006.201.10:36:22.07#ibcon#flushed, iclass 13, count 2 2006.201.10:36:22.07#ibcon#about to write, iclass 13, count 2 2006.201.10:36:22.07#ibcon#wrote, iclass 13, count 2 2006.201.10:36:22.07#ibcon#about to read 3, iclass 13, count 2 2006.201.10:36:22.10#ibcon#read 3, iclass 13, count 2 2006.201.10:36:22.10#ibcon#about to read 4, iclass 13, count 2 2006.201.10:36:22.10#ibcon#read 4, iclass 13, count 2 2006.201.10:36:22.10#ibcon#about to read 5, iclass 13, count 2 2006.201.10:36:22.10#ibcon#read 5, iclass 13, count 2 2006.201.10:36:22.10#ibcon#about to read 6, iclass 13, count 2 2006.201.10:36:22.10#ibcon#read 6, iclass 13, count 2 2006.201.10:36:22.10#ibcon#end of sib2, iclass 13, count 2 2006.201.10:36:22.10#ibcon#*after write, iclass 13, count 2 2006.201.10:36:22.10#ibcon#*before return 0, iclass 13, count 2 2006.201.10:36:22.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:36:22.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:36:22.10#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.10:36:22.10#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:22.10#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:36:22.22#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:36:22.22#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:36:22.22#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:36:22.22#ibcon#first serial, iclass 13, count 0 2006.201.10:36:22.22#ibcon#enter sib2, iclass 13, count 0 2006.201.10:36:22.22#ibcon#flushed, iclass 13, count 0 2006.201.10:36:22.22#ibcon#about to write, iclass 13, count 0 2006.201.10:36:22.22#ibcon#wrote, iclass 13, count 0 2006.201.10:36:22.22#ibcon#about to read 3, iclass 13, count 0 2006.201.10:36:22.24#ibcon#read 3, iclass 13, count 0 2006.201.10:36:22.24#ibcon#about to read 4, iclass 13, count 0 2006.201.10:36:22.24#ibcon#read 4, iclass 13, count 0 2006.201.10:36:22.24#ibcon#about to read 5, iclass 13, count 0 2006.201.10:36:22.24#ibcon#read 5, iclass 13, count 0 2006.201.10:36:22.24#ibcon#about to read 6, iclass 13, count 0 2006.201.10:36:22.24#ibcon#read 6, iclass 13, count 0 2006.201.10:36:22.24#ibcon#end of sib2, iclass 13, count 0 2006.201.10:36:22.24#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:36:22.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:36:22.24#ibcon#[25=USB\r\n] 2006.201.10:36:22.24#ibcon#*before write, iclass 13, count 0 2006.201.10:36:22.24#ibcon#enter sib2, iclass 13, count 0 2006.201.10:36:22.24#ibcon#flushed, iclass 13, count 0 2006.201.10:36:22.24#ibcon#about to write, iclass 13, count 0 2006.201.10:36:22.24#ibcon#wrote, iclass 13, count 0 2006.201.10:36:22.24#ibcon#about to read 3, iclass 13, count 0 2006.201.10:36:22.27#ibcon#read 3, iclass 13, count 0 2006.201.10:36:22.27#ibcon#about to read 4, iclass 13, count 0 2006.201.10:36:22.27#ibcon#read 4, iclass 13, count 0 2006.201.10:36:22.27#ibcon#about to read 5, iclass 13, count 0 2006.201.10:36:22.27#ibcon#read 5, iclass 13, count 0 2006.201.10:36:22.27#ibcon#about to read 6, iclass 13, count 0 2006.201.10:36:22.27#ibcon#read 6, iclass 13, count 0 2006.201.10:36:22.27#ibcon#end of sib2, iclass 13, count 0 2006.201.10:36:22.27#ibcon#*after write, iclass 13, count 0 2006.201.10:36:22.27#ibcon#*before return 0, iclass 13, count 0 2006.201.10:36:22.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:36:22.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:36:22.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:36:22.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:36:22.27$vck44/valo=5,734.99 2006.201.10:36:22.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.10:36:22.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.10:36:22.27#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:22.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:22.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:22.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:22.27#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:36:22.27#ibcon#first serial, iclass 15, count 0 2006.201.10:36:22.27#ibcon#enter sib2, iclass 15, count 0 2006.201.10:36:22.27#ibcon#flushed, iclass 15, count 0 2006.201.10:36:22.27#ibcon#about to write, iclass 15, count 0 2006.201.10:36:22.27#ibcon#wrote, iclass 15, count 0 2006.201.10:36:22.27#ibcon#about to read 3, iclass 15, count 0 2006.201.10:36:22.29#ibcon#read 3, iclass 15, count 0 2006.201.10:36:22.29#ibcon#about to read 4, iclass 15, count 0 2006.201.10:36:22.29#ibcon#read 4, iclass 15, count 0 2006.201.10:36:22.29#ibcon#about to read 5, iclass 15, count 0 2006.201.10:36:22.29#ibcon#read 5, iclass 15, count 0 2006.201.10:36:22.29#ibcon#about to read 6, iclass 15, count 0 2006.201.10:36:22.29#ibcon#read 6, iclass 15, count 0 2006.201.10:36:22.29#ibcon#end of sib2, iclass 15, count 0 2006.201.10:36:22.29#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:36:22.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:36:22.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:36:22.29#ibcon#*before write, iclass 15, count 0 2006.201.10:36:22.29#ibcon#enter sib2, iclass 15, count 0 2006.201.10:36:22.29#ibcon#flushed, iclass 15, count 0 2006.201.10:36:22.29#ibcon#about to write, iclass 15, count 0 2006.201.10:36:22.29#ibcon#wrote, iclass 15, count 0 2006.201.10:36:22.29#ibcon#about to read 3, iclass 15, count 0 2006.201.10:36:22.33#ibcon#read 3, iclass 15, count 0 2006.201.10:36:22.33#ibcon#about to read 4, iclass 15, count 0 2006.201.10:36:22.33#ibcon#read 4, iclass 15, count 0 2006.201.10:36:22.33#ibcon#about to read 5, iclass 15, count 0 2006.201.10:36:22.33#ibcon#read 5, iclass 15, count 0 2006.201.10:36:22.33#ibcon#about to read 6, iclass 15, count 0 2006.201.10:36:22.33#ibcon#read 6, iclass 15, count 0 2006.201.10:36:22.33#ibcon#end of sib2, iclass 15, count 0 2006.201.10:36:22.33#ibcon#*after write, iclass 15, count 0 2006.201.10:36:22.33#ibcon#*before return 0, iclass 15, count 0 2006.201.10:36:22.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:22.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:22.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:36:22.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:36:22.33$vck44/va=5,4 2006.201.10:36:22.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.10:36:22.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.10:36:22.33#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:22.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:22.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:22.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:22.39#ibcon#enter wrdev, iclass 17, count 2 2006.201.10:36:22.39#ibcon#first serial, iclass 17, count 2 2006.201.10:36:22.39#ibcon#enter sib2, iclass 17, count 2 2006.201.10:36:22.39#ibcon#flushed, iclass 17, count 2 2006.201.10:36:22.39#ibcon#about to write, iclass 17, count 2 2006.201.10:36:22.39#ibcon#wrote, iclass 17, count 2 2006.201.10:36:22.39#ibcon#about to read 3, iclass 17, count 2 2006.201.10:36:22.41#ibcon#read 3, iclass 17, count 2 2006.201.10:36:22.41#ibcon#about to read 4, iclass 17, count 2 2006.201.10:36:22.41#ibcon#read 4, iclass 17, count 2 2006.201.10:36:22.41#ibcon#about to read 5, iclass 17, count 2 2006.201.10:36:22.41#ibcon#read 5, iclass 17, count 2 2006.201.10:36:22.41#ibcon#about to read 6, iclass 17, count 2 2006.201.10:36:22.41#ibcon#read 6, iclass 17, count 2 2006.201.10:36:22.41#ibcon#end of sib2, iclass 17, count 2 2006.201.10:36:22.41#ibcon#*mode == 0, iclass 17, count 2 2006.201.10:36:22.41#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.10:36:22.41#ibcon#[25=AT05-04\r\n] 2006.201.10:36:22.41#ibcon#*before write, iclass 17, count 2 2006.201.10:36:22.41#ibcon#enter sib2, iclass 17, count 2 2006.201.10:36:22.41#ibcon#flushed, iclass 17, count 2 2006.201.10:36:22.41#ibcon#about to write, iclass 17, count 2 2006.201.10:36:22.41#ibcon#wrote, iclass 17, count 2 2006.201.10:36:22.41#ibcon#about to read 3, iclass 17, count 2 2006.201.10:36:22.44#ibcon#read 3, iclass 17, count 2 2006.201.10:36:22.44#ibcon#about to read 4, iclass 17, count 2 2006.201.10:36:22.44#ibcon#read 4, iclass 17, count 2 2006.201.10:36:22.44#ibcon#about to read 5, iclass 17, count 2 2006.201.10:36:22.44#ibcon#read 5, iclass 17, count 2 2006.201.10:36:22.44#ibcon#about to read 6, iclass 17, count 2 2006.201.10:36:22.44#ibcon#read 6, iclass 17, count 2 2006.201.10:36:22.44#ibcon#end of sib2, iclass 17, count 2 2006.201.10:36:22.44#ibcon#*after write, iclass 17, count 2 2006.201.10:36:22.44#ibcon#*before return 0, iclass 17, count 2 2006.201.10:36:22.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:22.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:22.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.10:36:22.44#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:22.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:22.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:22.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:22.56#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:36:22.56#ibcon#first serial, iclass 17, count 0 2006.201.10:36:22.56#ibcon#enter sib2, iclass 17, count 0 2006.201.10:36:22.56#ibcon#flushed, iclass 17, count 0 2006.201.10:36:22.56#ibcon#about to write, iclass 17, count 0 2006.201.10:36:22.56#ibcon#wrote, iclass 17, count 0 2006.201.10:36:22.56#ibcon#about to read 3, iclass 17, count 0 2006.201.10:36:22.58#ibcon#read 3, iclass 17, count 0 2006.201.10:36:22.58#ibcon#about to read 4, iclass 17, count 0 2006.201.10:36:22.58#ibcon#read 4, iclass 17, count 0 2006.201.10:36:22.58#ibcon#about to read 5, iclass 17, count 0 2006.201.10:36:22.58#ibcon#read 5, iclass 17, count 0 2006.201.10:36:22.58#ibcon#about to read 6, iclass 17, count 0 2006.201.10:36:22.58#ibcon#read 6, iclass 17, count 0 2006.201.10:36:22.58#ibcon#end of sib2, iclass 17, count 0 2006.201.10:36:22.58#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:36:22.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:36:22.58#ibcon#[25=USB\r\n] 2006.201.10:36:22.58#ibcon#*before write, iclass 17, count 0 2006.201.10:36:22.58#ibcon#enter sib2, iclass 17, count 0 2006.201.10:36:22.58#ibcon#flushed, iclass 17, count 0 2006.201.10:36:22.58#ibcon#about to write, iclass 17, count 0 2006.201.10:36:22.58#ibcon#wrote, iclass 17, count 0 2006.201.10:36:22.58#ibcon#about to read 3, iclass 17, count 0 2006.201.10:36:22.61#ibcon#read 3, iclass 17, count 0 2006.201.10:36:22.61#ibcon#about to read 4, iclass 17, count 0 2006.201.10:36:22.61#ibcon#read 4, iclass 17, count 0 2006.201.10:36:22.61#ibcon#about to read 5, iclass 17, count 0 2006.201.10:36:22.61#ibcon#read 5, iclass 17, count 0 2006.201.10:36:22.61#ibcon#about to read 6, iclass 17, count 0 2006.201.10:36:22.61#ibcon#read 6, iclass 17, count 0 2006.201.10:36:22.61#ibcon#end of sib2, iclass 17, count 0 2006.201.10:36:22.61#ibcon#*after write, iclass 17, count 0 2006.201.10:36:22.61#ibcon#*before return 0, iclass 17, count 0 2006.201.10:36:22.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:22.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:22.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:36:22.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:36:22.61$vck44/valo=6,814.99 2006.201.10:36:22.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.10:36:22.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.10:36:22.61#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:22.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:22.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:22.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:22.61#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:36:22.61#ibcon#first serial, iclass 19, count 0 2006.201.10:36:22.61#ibcon#enter sib2, iclass 19, count 0 2006.201.10:36:22.61#ibcon#flushed, iclass 19, count 0 2006.201.10:36:22.61#ibcon#about to write, iclass 19, count 0 2006.201.10:36:22.61#ibcon#wrote, iclass 19, count 0 2006.201.10:36:22.61#ibcon#about to read 3, iclass 19, count 0 2006.201.10:36:22.63#ibcon#read 3, iclass 19, count 0 2006.201.10:36:22.63#ibcon#about to read 4, iclass 19, count 0 2006.201.10:36:22.63#ibcon#read 4, iclass 19, count 0 2006.201.10:36:22.63#ibcon#about to read 5, iclass 19, count 0 2006.201.10:36:22.63#ibcon#read 5, iclass 19, count 0 2006.201.10:36:22.63#ibcon#about to read 6, iclass 19, count 0 2006.201.10:36:22.63#ibcon#read 6, iclass 19, count 0 2006.201.10:36:22.63#ibcon#end of sib2, iclass 19, count 0 2006.201.10:36:22.63#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:36:22.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:36:22.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:36:22.63#ibcon#*before write, iclass 19, count 0 2006.201.10:36:22.63#ibcon#enter sib2, iclass 19, count 0 2006.201.10:36:22.63#ibcon#flushed, iclass 19, count 0 2006.201.10:36:22.63#ibcon#about to write, iclass 19, count 0 2006.201.10:36:22.63#ibcon#wrote, iclass 19, count 0 2006.201.10:36:22.63#ibcon#about to read 3, iclass 19, count 0 2006.201.10:36:22.67#ibcon#read 3, iclass 19, count 0 2006.201.10:36:22.67#ibcon#about to read 4, iclass 19, count 0 2006.201.10:36:22.67#ibcon#read 4, iclass 19, count 0 2006.201.10:36:22.67#ibcon#about to read 5, iclass 19, count 0 2006.201.10:36:22.67#ibcon#read 5, iclass 19, count 0 2006.201.10:36:22.67#ibcon#about to read 6, iclass 19, count 0 2006.201.10:36:22.67#ibcon#read 6, iclass 19, count 0 2006.201.10:36:22.67#ibcon#end of sib2, iclass 19, count 0 2006.201.10:36:22.67#ibcon#*after write, iclass 19, count 0 2006.201.10:36:22.67#ibcon#*before return 0, iclass 19, count 0 2006.201.10:36:22.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:22.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:22.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:36:22.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:36:22.67$vck44/va=6,5 2006.201.10:36:22.67#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.10:36:22.67#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.10:36:22.67#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:22.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:22.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:22.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:22.73#ibcon#enter wrdev, iclass 21, count 2 2006.201.10:36:22.73#ibcon#first serial, iclass 21, count 2 2006.201.10:36:22.73#ibcon#enter sib2, iclass 21, count 2 2006.201.10:36:22.73#ibcon#flushed, iclass 21, count 2 2006.201.10:36:22.73#ibcon#about to write, iclass 21, count 2 2006.201.10:36:22.73#ibcon#wrote, iclass 21, count 2 2006.201.10:36:22.73#ibcon#about to read 3, iclass 21, count 2 2006.201.10:36:22.75#ibcon#read 3, iclass 21, count 2 2006.201.10:36:22.75#ibcon#about to read 4, iclass 21, count 2 2006.201.10:36:22.75#ibcon#read 4, iclass 21, count 2 2006.201.10:36:22.75#ibcon#about to read 5, iclass 21, count 2 2006.201.10:36:22.75#ibcon#read 5, iclass 21, count 2 2006.201.10:36:22.75#ibcon#about to read 6, iclass 21, count 2 2006.201.10:36:22.75#ibcon#read 6, iclass 21, count 2 2006.201.10:36:22.75#ibcon#end of sib2, iclass 21, count 2 2006.201.10:36:22.75#ibcon#*mode == 0, iclass 21, count 2 2006.201.10:36:22.75#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.10:36:22.75#ibcon#[25=AT06-05\r\n] 2006.201.10:36:22.75#ibcon#*before write, iclass 21, count 2 2006.201.10:36:22.75#ibcon#enter sib2, iclass 21, count 2 2006.201.10:36:22.75#ibcon#flushed, iclass 21, count 2 2006.201.10:36:22.75#ibcon#about to write, iclass 21, count 2 2006.201.10:36:22.75#ibcon#wrote, iclass 21, count 2 2006.201.10:36:22.75#ibcon#about to read 3, iclass 21, count 2 2006.201.10:36:22.78#ibcon#read 3, iclass 21, count 2 2006.201.10:36:22.78#ibcon#about to read 4, iclass 21, count 2 2006.201.10:36:22.78#ibcon#read 4, iclass 21, count 2 2006.201.10:36:22.78#ibcon#about to read 5, iclass 21, count 2 2006.201.10:36:22.78#ibcon#read 5, iclass 21, count 2 2006.201.10:36:22.78#ibcon#about to read 6, iclass 21, count 2 2006.201.10:36:22.78#ibcon#read 6, iclass 21, count 2 2006.201.10:36:22.78#ibcon#end of sib2, iclass 21, count 2 2006.201.10:36:22.78#ibcon#*after write, iclass 21, count 2 2006.201.10:36:22.78#ibcon#*before return 0, iclass 21, count 2 2006.201.10:36:22.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:22.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:22.78#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.10:36:22.78#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:22.78#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:22.90#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:22.90#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:22.90#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:36:22.90#ibcon#first serial, iclass 21, count 0 2006.201.10:36:22.90#ibcon#enter sib2, iclass 21, count 0 2006.201.10:36:22.90#ibcon#flushed, iclass 21, count 0 2006.201.10:36:22.90#ibcon#about to write, iclass 21, count 0 2006.201.10:36:22.90#ibcon#wrote, iclass 21, count 0 2006.201.10:36:22.90#ibcon#about to read 3, iclass 21, count 0 2006.201.10:36:22.92#ibcon#read 3, iclass 21, count 0 2006.201.10:36:22.92#ibcon#about to read 4, iclass 21, count 0 2006.201.10:36:22.92#ibcon#read 4, iclass 21, count 0 2006.201.10:36:22.92#ibcon#about to read 5, iclass 21, count 0 2006.201.10:36:22.92#ibcon#read 5, iclass 21, count 0 2006.201.10:36:22.92#ibcon#about to read 6, iclass 21, count 0 2006.201.10:36:22.92#ibcon#read 6, iclass 21, count 0 2006.201.10:36:22.92#ibcon#end of sib2, iclass 21, count 0 2006.201.10:36:22.92#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:36:22.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:36:22.92#ibcon#[25=USB\r\n] 2006.201.10:36:22.92#ibcon#*before write, iclass 21, count 0 2006.201.10:36:22.92#ibcon#enter sib2, iclass 21, count 0 2006.201.10:36:22.92#ibcon#flushed, iclass 21, count 0 2006.201.10:36:22.92#ibcon#about to write, iclass 21, count 0 2006.201.10:36:22.92#ibcon#wrote, iclass 21, count 0 2006.201.10:36:22.92#ibcon#about to read 3, iclass 21, count 0 2006.201.10:36:22.95#ibcon#read 3, iclass 21, count 0 2006.201.10:36:22.95#ibcon#about to read 4, iclass 21, count 0 2006.201.10:36:22.95#ibcon#read 4, iclass 21, count 0 2006.201.10:36:22.95#ibcon#about to read 5, iclass 21, count 0 2006.201.10:36:22.95#ibcon#read 5, iclass 21, count 0 2006.201.10:36:22.95#ibcon#about to read 6, iclass 21, count 0 2006.201.10:36:22.95#ibcon#read 6, iclass 21, count 0 2006.201.10:36:22.95#ibcon#end of sib2, iclass 21, count 0 2006.201.10:36:22.95#ibcon#*after write, iclass 21, count 0 2006.201.10:36:22.95#ibcon#*before return 0, iclass 21, count 0 2006.201.10:36:22.95#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:22.95#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:22.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:36:22.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:36:22.95$vck44/valo=7,864.99 2006.201.10:36:22.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.10:36:22.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.10:36:22.95#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:22.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:22.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:22.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:22.95#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:36:22.95#ibcon#first serial, iclass 23, count 0 2006.201.10:36:22.95#ibcon#enter sib2, iclass 23, count 0 2006.201.10:36:22.95#ibcon#flushed, iclass 23, count 0 2006.201.10:36:22.95#ibcon#about to write, iclass 23, count 0 2006.201.10:36:22.95#ibcon#wrote, iclass 23, count 0 2006.201.10:36:22.95#ibcon#about to read 3, iclass 23, count 0 2006.201.10:36:22.97#ibcon#read 3, iclass 23, count 0 2006.201.10:36:22.97#ibcon#about to read 4, iclass 23, count 0 2006.201.10:36:22.97#ibcon#read 4, iclass 23, count 0 2006.201.10:36:22.97#ibcon#about to read 5, iclass 23, count 0 2006.201.10:36:22.97#ibcon#read 5, iclass 23, count 0 2006.201.10:36:22.97#ibcon#about to read 6, iclass 23, count 0 2006.201.10:36:22.97#ibcon#read 6, iclass 23, count 0 2006.201.10:36:22.97#ibcon#end of sib2, iclass 23, count 0 2006.201.10:36:22.97#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:36:22.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:36:22.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:36:22.97#ibcon#*before write, iclass 23, count 0 2006.201.10:36:22.97#ibcon#enter sib2, iclass 23, count 0 2006.201.10:36:22.97#ibcon#flushed, iclass 23, count 0 2006.201.10:36:22.97#ibcon#about to write, iclass 23, count 0 2006.201.10:36:22.97#ibcon#wrote, iclass 23, count 0 2006.201.10:36:22.97#ibcon#about to read 3, iclass 23, count 0 2006.201.10:36:23.02#ibcon#read 3, iclass 23, count 0 2006.201.10:36:23.02#ibcon#about to read 4, iclass 23, count 0 2006.201.10:36:23.02#ibcon#read 4, iclass 23, count 0 2006.201.10:36:23.02#ibcon#about to read 5, iclass 23, count 0 2006.201.10:36:23.02#ibcon#read 5, iclass 23, count 0 2006.201.10:36:23.02#ibcon#about to read 6, iclass 23, count 0 2006.201.10:36:23.02#ibcon#read 6, iclass 23, count 0 2006.201.10:36:23.02#ibcon#end of sib2, iclass 23, count 0 2006.201.10:36:23.02#ibcon#*after write, iclass 23, count 0 2006.201.10:36:23.02#ibcon#*before return 0, iclass 23, count 0 2006.201.10:36:23.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:23.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:23.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:36:23.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:36:23.02$vck44/va=7,5 2006.201.10:36:23.02#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.10:36:23.02#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.10:36:23.02#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:23.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:23.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:23.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:23.07#ibcon#enter wrdev, iclass 25, count 2 2006.201.10:36:23.07#ibcon#first serial, iclass 25, count 2 2006.201.10:36:23.07#ibcon#enter sib2, iclass 25, count 2 2006.201.10:36:23.07#ibcon#flushed, iclass 25, count 2 2006.201.10:36:23.07#ibcon#about to write, iclass 25, count 2 2006.201.10:36:23.07#ibcon#wrote, iclass 25, count 2 2006.201.10:36:23.07#ibcon#about to read 3, iclass 25, count 2 2006.201.10:36:23.09#ibcon#read 3, iclass 25, count 2 2006.201.10:36:23.09#ibcon#about to read 4, iclass 25, count 2 2006.201.10:36:23.09#ibcon#read 4, iclass 25, count 2 2006.201.10:36:23.09#ibcon#about to read 5, iclass 25, count 2 2006.201.10:36:23.09#ibcon#read 5, iclass 25, count 2 2006.201.10:36:23.09#ibcon#about to read 6, iclass 25, count 2 2006.201.10:36:23.09#ibcon#read 6, iclass 25, count 2 2006.201.10:36:23.09#ibcon#end of sib2, iclass 25, count 2 2006.201.10:36:23.09#ibcon#*mode == 0, iclass 25, count 2 2006.201.10:36:23.09#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.10:36:23.09#ibcon#[25=AT07-05\r\n] 2006.201.10:36:23.09#ibcon#*before write, iclass 25, count 2 2006.201.10:36:23.09#ibcon#enter sib2, iclass 25, count 2 2006.201.10:36:23.09#ibcon#flushed, iclass 25, count 2 2006.201.10:36:23.09#ibcon#about to write, iclass 25, count 2 2006.201.10:36:23.09#ibcon#wrote, iclass 25, count 2 2006.201.10:36:23.09#ibcon#about to read 3, iclass 25, count 2 2006.201.10:36:23.12#ibcon#read 3, iclass 25, count 2 2006.201.10:36:23.12#ibcon#about to read 4, iclass 25, count 2 2006.201.10:36:23.12#ibcon#read 4, iclass 25, count 2 2006.201.10:36:23.12#ibcon#about to read 5, iclass 25, count 2 2006.201.10:36:23.12#ibcon#read 5, iclass 25, count 2 2006.201.10:36:23.12#ibcon#about to read 6, iclass 25, count 2 2006.201.10:36:23.12#ibcon#read 6, iclass 25, count 2 2006.201.10:36:23.12#ibcon#end of sib2, iclass 25, count 2 2006.201.10:36:23.12#ibcon#*after write, iclass 25, count 2 2006.201.10:36:23.12#ibcon#*before return 0, iclass 25, count 2 2006.201.10:36:23.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:23.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:23.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.10:36:23.12#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:23.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:23.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:23.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:23.24#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:36:23.24#ibcon#first serial, iclass 25, count 0 2006.201.10:36:23.24#ibcon#enter sib2, iclass 25, count 0 2006.201.10:36:23.24#ibcon#flushed, iclass 25, count 0 2006.201.10:36:23.24#ibcon#about to write, iclass 25, count 0 2006.201.10:36:23.24#ibcon#wrote, iclass 25, count 0 2006.201.10:36:23.24#ibcon#about to read 3, iclass 25, count 0 2006.201.10:36:23.26#ibcon#read 3, iclass 25, count 0 2006.201.10:36:23.26#ibcon#about to read 4, iclass 25, count 0 2006.201.10:36:23.26#ibcon#read 4, iclass 25, count 0 2006.201.10:36:23.26#ibcon#about to read 5, iclass 25, count 0 2006.201.10:36:23.26#ibcon#read 5, iclass 25, count 0 2006.201.10:36:23.26#ibcon#about to read 6, iclass 25, count 0 2006.201.10:36:23.26#ibcon#read 6, iclass 25, count 0 2006.201.10:36:23.26#ibcon#end of sib2, iclass 25, count 0 2006.201.10:36:23.26#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:36:23.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:36:23.26#ibcon#[25=USB\r\n] 2006.201.10:36:23.26#ibcon#*before write, iclass 25, count 0 2006.201.10:36:23.26#ibcon#enter sib2, iclass 25, count 0 2006.201.10:36:23.26#ibcon#flushed, iclass 25, count 0 2006.201.10:36:23.26#ibcon#about to write, iclass 25, count 0 2006.201.10:36:23.26#ibcon#wrote, iclass 25, count 0 2006.201.10:36:23.26#ibcon#about to read 3, iclass 25, count 0 2006.201.10:36:23.29#ibcon#read 3, iclass 25, count 0 2006.201.10:36:23.29#ibcon#about to read 4, iclass 25, count 0 2006.201.10:36:23.29#ibcon#read 4, iclass 25, count 0 2006.201.10:36:23.29#ibcon#about to read 5, iclass 25, count 0 2006.201.10:36:23.29#ibcon#read 5, iclass 25, count 0 2006.201.10:36:23.29#ibcon#about to read 6, iclass 25, count 0 2006.201.10:36:23.29#ibcon#read 6, iclass 25, count 0 2006.201.10:36:23.29#ibcon#end of sib2, iclass 25, count 0 2006.201.10:36:23.29#ibcon#*after write, iclass 25, count 0 2006.201.10:36:23.29#ibcon#*before return 0, iclass 25, count 0 2006.201.10:36:23.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:23.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:23.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:36:23.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:36:23.29$vck44/valo=8,884.99 2006.201.10:36:23.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.10:36:23.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.10:36:23.29#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:23.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:23.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:23.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:23.29#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:36:23.29#ibcon#first serial, iclass 27, count 0 2006.201.10:36:23.29#ibcon#enter sib2, iclass 27, count 0 2006.201.10:36:23.29#ibcon#flushed, iclass 27, count 0 2006.201.10:36:23.29#ibcon#about to write, iclass 27, count 0 2006.201.10:36:23.29#ibcon#wrote, iclass 27, count 0 2006.201.10:36:23.29#ibcon#about to read 3, iclass 27, count 0 2006.201.10:36:23.31#ibcon#read 3, iclass 27, count 0 2006.201.10:36:23.31#ibcon#about to read 4, iclass 27, count 0 2006.201.10:36:23.31#ibcon#read 4, iclass 27, count 0 2006.201.10:36:23.31#ibcon#about to read 5, iclass 27, count 0 2006.201.10:36:23.31#ibcon#read 5, iclass 27, count 0 2006.201.10:36:23.31#ibcon#about to read 6, iclass 27, count 0 2006.201.10:36:23.31#ibcon#read 6, iclass 27, count 0 2006.201.10:36:23.31#ibcon#end of sib2, iclass 27, count 0 2006.201.10:36:23.31#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:36:23.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:36:23.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:36:23.31#ibcon#*before write, iclass 27, count 0 2006.201.10:36:23.31#ibcon#enter sib2, iclass 27, count 0 2006.201.10:36:23.31#ibcon#flushed, iclass 27, count 0 2006.201.10:36:23.31#ibcon#about to write, iclass 27, count 0 2006.201.10:36:23.31#ibcon#wrote, iclass 27, count 0 2006.201.10:36:23.31#ibcon#about to read 3, iclass 27, count 0 2006.201.10:36:23.35#ibcon#read 3, iclass 27, count 0 2006.201.10:36:23.35#ibcon#about to read 4, iclass 27, count 0 2006.201.10:36:23.35#ibcon#read 4, iclass 27, count 0 2006.201.10:36:23.35#ibcon#about to read 5, iclass 27, count 0 2006.201.10:36:23.35#ibcon#read 5, iclass 27, count 0 2006.201.10:36:23.35#ibcon#about to read 6, iclass 27, count 0 2006.201.10:36:23.35#ibcon#read 6, iclass 27, count 0 2006.201.10:36:23.35#ibcon#end of sib2, iclass 27, count 0 2006.201.10:36:23.35#ibcon#*after write, iclass 27, count 0 2006.201.10:36:23.35#ibcon#*before return 0, iclass 27, count 0 2006.201.10:36:23.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:23.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:23.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:36:23.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:36:23.35$vck44/va=8,4 2006.201.10:36:23.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.10:36:23.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.10:36:23.35#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:23.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:23.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:23.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:23.41#ibcon#enter wrdev, iclass 29, count 2 2006.201.10:36:23.41#ibcon#first serial, iclass 29, count 2 2006.201.10:36:23.41#ibcon#enter sib2, iclass 29, count 2 2006.201.10:36:23.41#ibcon#flushed, iclass 29, count 2 2006.201.10:36:23.41#ibcon#about to write, iclass 29, count 2 2006.201.10:36:23.41#ibcon#wrote, iclass 29, count 2 2006.201.10:36:23.41#ibcon#about to read 3, iclass 29, count 2 2006.201.10:36:23.43#ibcon#read 3, iclass 29, count 2 2006.201.10:36:23.43#ibcon#about to read 4, iclass 29, count 2 2006.201.10:36:23.43#ibcon#read 4, iclass 29, count 2 2006.201.10:36:23.43#ibcon#about to read 5, iclass 29, count 2 2006.201.10:36:23.43#ibcon#read 5, iclass 29, count 2 2006.201.10:36:23.43#ibcon#about to read 6, iclass 29, count 2 2006.201.10:36:23.43#ibcon#read 6, iclass 29, count 2 2006.201.10:36:23.43#ibcon#end of sib2, iclass 29, count 2 2006.201.10:36:23.43#ibcon#*mode == 0, iclass 29, count 2 2006.201.10:36:23.43#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.10:36:23.43#ibcon#[25=AT08-04\r\n] 2006.201.10:36:23.43#ibcon#*before write, iclass 29, count 2 2006.201.10:36:23.43#ibcon#enter sib2, iclass 29, count 2 2006.201.10:36:23.43#ibcon#flushed, iclass 29, count 2 2006.201.10:36:23.43#ibcon#about to write, iclass 29, count 2 2006.201.10:36:23.43#ibcon#wrote, iclass 29, count 2 2006.201.10:36:23.43#ibcon#about to read 3, iclass 29, count 2 2006.201.10:36:23.46#ibcon#read 3, iclass 29, count 2 2006.201.10:36:23.46#ibcon#about to read 4, iclass 29, count 2 2006.201.10:36:23.46#ibcon#read 4, iclass 29, count 2 2006.201.10:36:23.46#ibcon#about to read 5, iclass 29, count 2 2006.201.10:36:23.46#ibcon#read 5, iclass 29, count 2 2006.201.10:36:23.46#ibcon#about to read 6, iclass 29, count 2 2006.201.10:36:23.46#ibcon#read 6, iclass 29, count 2 2006.201.10:36:23.46#ibcon#end of sib2, iclass 29, count 2 2006.201.10:36:23.46#ibcon#*after write, iclass 29, count 2 2006.201.10:36:23.46#ibcon#*before return 0, iclass 29, count 2 2006.201.10:36:23.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:23.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:23.46#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.10:36:23.46#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:23.46#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:23.58#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:23.58#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:23.58#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:36:23.58#ibcon#first serial, iclass 29, count 0 2006.201.10:36:23.58#ibcon#enter sib2, iclass 29, count 0 2006.201.10:36:23.58#ibcon#flushed, iclass 29, count 0 2006.201.10:36:23.58#ibcon#about to write, iclass 29, count 0 2006.201.10:36:23.58#ibcon#wrote, iclass 29, count 0 2006.201.10:36:23.58#ibcon#about to read 3, iclass 29, count 0 2006.201.10:36:23.60#ibcon#read 3, iclass 29, count 0 2006.201.10:36:23.60#ibcon#about to read 4, iclass 29, count 0 2006.201.10:36:23.60#ibcon#read 4, iclass 29, count 0 2006.201.10:36:23.60#ibcon#about to read 5, iclass 29, count 0 2006.201.10:36:23.60#ibcon#read 5, iclass 29, count 0 2006.201.10:36:23.60#ibcon#about to read 6, iclass 29, count 0 2006.201.10:36:23.60#ibcon#read 6, iclass 29, count 0 2006.201.10:36:23.60#ibcon#end of sib2, iclass 29, count 0 2006.201.10:36:23.60#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:36:23.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:36:23.60#ibcon#[25=USB\r\n] 2006.201.10:36:23.60#ibcon#*before write, iclass 29, count 0 2006.201.10:36:23.60#ibcon#enter sib2, iclass 29, count 0 2006.201.10:36:23.60#ibcon#flushed, iclass 29, count 0 2006.201.10:36:23.60#ibcon#about to write, iclass 29, count 0 2006.201.10:36:23.60#ibcon#wrote, iclass 29, count 0 2006.201.10:36:23.60#ibcon#about to read 3, iclass 29, count 0 2006.201.10:36:23.63#ibcon#read 3, iclass 29, count 0 2006.201.10:36:23.63#ibcon#about to read 4, iclass 29, count 0 2006.201.10:36:23.63#ibcon#read 4, iclass 29, count 0 2006.201.10:36:23.63#ibcon#about to read 5, iclass 29, count 0 2006.201.10:36:23.63#ibcon#read 5, iclass 29, count 0 2006.201.10:36:23.63#ibcon#about to read 6, iclass 29, count 0 2006.201.10:36:23.63#ibcon#read 6, iclass 29, count 0 2006.201.10:36:23.63#ibcon#end of sib2, iclass 29, count 0 2006.201.10:36:23.63#ibcon#*after write, iclass 29, count 0 2006.201.10:36:23.63#ibcon#*before return 0, iclass 29, count 0 2006.201.10:36:23.63#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:23.63#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:23.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:36:23.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:36:23.63$vck44/vblo=1,629.99 2006.201.10:36:23.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.10:36:23.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.10:36:23.63#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:23.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:23.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:23.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:23.63#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:36:23.63#ibcon#first serial, iclass 31, count 0 2006.201.10:36:23.63#ibcon#enter sib2, iclass 31, count 0 2006.201.10:36:23.63#ibcon#flushed, iclass 31, count 0 2006.201.10:36:23.63#ibcon#about to write, iclass 31, count 0 2006.201.10:36:23.63#ibcon#wrote, iclass 31, count 0 2006.201.10:36:23.63#ibcon#about to read 3, iclass 31, count 0 2006.201.10:36:23.65#ibcon#read 3, iclass 31, count 0 2006.201.10:36:23.65#ibcon#about to read 4, iclass 31, count 0 2006.201.10:36:23.65#ibcon#read 4, iclass 31, count 0 2006.201.10:36:23.65#ibcon#about to read 5, iclass 31, count 0 2006.201.10:36:23.65#ibcon#read 5, iclass 31, count 0 2006.201.10:36:23.65#ibcon#about to read 6, iclass 31, count 0 2006.201.10:36:23.65#ibcon#read 6, iclass 31, count 0 2006.201.10:36:23.65#ibcon#end of sib2, iclass 31, count 0 2006.201.10:36:23.65#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:36:23.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:36:23.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:36:23.65#ibcon#*before write, iclass 31, count 0 2006.201.10:36:23.65#ibcon#enter sib2, iclass 31, count 0 2006.201.10:36:23.65#ibcon#flushed, iclass 31, count 0 2006.201.10:36:23.65#ibcon#about to write, iclass 31, count 0 2006.201.10:36:23.65#ibcon#wrote, iclass 31, count 0 2006.201.10:36:23.65#ibcon#about to read 3, iclass 31, count 0 2006.201.10:36:23.69#ibcon#read 3, iclass 31, count 0 2006.201.10:36:23.69#ibcon#about to read 4, iclass 31, count 0 2006.201.10:36:23.69#ibcon#read 4, iclass 31, count 0 2006.201.10:36:23.69#ibcon#about to read 5, iclass 31, count 0 2006.201.10:36:23.69#ibcon#read 5, iclass 31, count 0 2006.201.10:36:23.69#ibcon#about to read 6, iclass 31, count 0 2006.201.10:36:23.69#ibcon#read 6, iclass 31, count 0 2006.201.10:36:23.69#ibcon#end of sib2, iclass 31, count 0 2006.201.10:36:23.69#ibcon#*after write, iclass 31, count 0 2006.201.10:36:23.69#ibcon#*before return 0, iclass 31, count 0 2006.201.10:36:23.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:23.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:23.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:36:23.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:36:23.69$vck44/vb=1,4 2006.201.10:36:23.69#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.10:36:23.69#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.10:36:23.69#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:23.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:36:23.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:36:23.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:36:23.69#ibcon#enter wrdev, iclass 33, count 2 2006.201.10:36:23.69#ibcon#first serial, iclass 33, count 2 2006.201.10:36:23.69#ibcon#enter sib2, iclass 33, count 2 2006.201.10:36:23.69#ibcon#flushed, iclass 33, count 2 2006.201.10:36:23.69#ibcon#about to write, iclass 33, count 2 2006.201.10:36:23.69#ibcon#wrote, iclass 33, count 2 2006.201.10:36:23.69#ibcon#about to read 3, iclass 33, count 2 2006.201.10:36:23.71#ibcon#read 3, iclass 33, count 2 2006.201.10:36:23.71#ibcon#about to read 4, iclass 33, count 2 2006.201.10:36:23.71#ibcon#read 4, iclass 33, count 2 2006.201.10:36:23.71#ibcon#about to read 5, iclass 33, count 2 2006.201.10:36:23.71#ibcon#read 5, iclass 33, count 2 2006.201.10:36:23.71#ibcon#about to read 6, iclass 33, count 2 2006.201.10:36:23.71#ibcon#read 6, iclass 33, count 2 2006.201.10:36:23.71#ibcon#end of sib2, iclass 33, count 2 2006.201.10:36:23.71#ibcon#*mode == 0, iclass 33, count 2 2006.201.10:36:23.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.10:36:23.71#ibcon#[27=AT01-04\r\n] 2006.201.10:36:23.71#ibcon#*before write, iclass 33, count 2 2006.201.10:36:23.71#ibcon#enter sib2, iclass 33, count 2 2006.201.10:36:23.71#ibcon#flushed, iclass 33, count 2 2006.201.10:36:23.71#ibcon#about to write, iclass 33, count 2 2006.201.10:36:23.71#ibcon#wrote, iclass 33, count 2 2006.201.10:36:23.71#ibcon#about to read 3, iclass 33, count 2 2006.201.10:36:23.74#ibcon#read 3, iclass 33, count 2 2006.201.10:36:23.74#ibcon#about to read 4, iclass 33, count 2 2006.201.10:36:23.74#ibcon#read 4, iclass 33, count 2 2006.201.10:36:23.74#ibcon#about to read 5, iclass 33, count 2 2006.201.10:36:23.74#ibcon#read 5, iclass 33, count 2 2006.201.10:36:23.74#ibcon#about to read 6, iclass 33, count 2 2006.201.10:36:23.74#ibcon#read 6, iclass 33, count 2 2006.201.10:36:23.74#ibcon#end of sib2, iclass 33, count 2 2006.201.10:36:23.74#ibcon#*after write, iclass 33, count 2 2006.201.10:36:23.74#ibcon#*before return 0, iclass 33, count 2 2006.201.10:36:23.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:36:23.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:36:23.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.10:36:23.74#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:23.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:36:23.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:36:23.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:36:23.86#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:36:23.86#ibcon#first serial, iclass 33, count 0 2006.201.10:36:23.86#ibcon#enter sib2, iclass 33, count 0 2006.201.10:36:23.86#ibcon#flushed, iclass 33, count 0 2006.201.10:36:23.86#ibcon#about to write, iclass 33, count 0 2006.201.10:36:23.86#ibcon#wrote, iclass 33, count 0 2006.201.10:36:23.86#ibcon#about to read 3, iclass 33, count 0 2006.201.10:36:23.88#ibcon#read 3, iclass 33, count 0 2006.201.10:36:23.88#ibcon#about to read 4, iclass 33, count 0 2006.201.10:36:23.88#ibcon#read 4, iclass 33, count 0 2006.201.10:36:23.88#ibcon#about to read 5, iclass 33, count 0 2006.201.10:36:23.88#ibcon#read 5, iclass 33, count 0 2006.201.10:36:23.88#ibcon#about to read 6, iclass 33, count 0 2006.201.10:36:23.88#ibcon#read 6, iclass 33, count 0 2006.201.10:36:23.88#ibcon#end of sib2, iclass 33, count 0 2006.201.10:36:23.88#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:36:23.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:36:23.88#ibcon#[27=USB\r\n] 2006.201.10:36:23.88#ibcon#*before write, iclass 33, count 0 2006.201.10:36:23.88#ibcon#enter sib2, iclass 33, count 0 2006.201.10:36:23.88#ibcon#flushed, iclass 33, count 0 2006.201.10:36:23.88#ibcon#about to write, iclass 33, count 0 2006.201.10:36:23.88#ibcon#wrote, iclass 33, count 0 2006.201.10:36:23.88#ibcon#about to read 3, iclass 33, count 0 2006.201.10:36:23.91#ibcon#read 3, iclass 33, count 0 2006.201.10:36:23.91#ibcon#about to read 4, iclass 33, count 0 2006.201.10:36:23.91#ibcon#read 4, iclass 33, count 0 2006.201.10:36:23.91#ibcon#about to read 5, iclass 33, count 0 2006.201.10:36:23.91#ibcon#read 5, iclass 33, count 0 2006.201.10:36:23.91#ibcon#about to read 6, iclass 33, count 0 2006.201.10:36:23.91#ibcon#read 6, iclass 33, count 0 2006.201.10:36:23.91#ibcon#end of sib2, iclass 33, count 0 2006.201.10:36:23.91#ibcon#*after write, iclass 33, count 0 2006.201.10:36:23.91#ibcon#*before return 0, iclass 33, count 0 2006.201.10:36:23.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:36:23.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:36:23.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:36:23.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:36:23.91$vck44/vblo=2,634.99 2006.201.10:36:23.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.10:36:23.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.10:36:23.91#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:23.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:23.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:23.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:23.91#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:36:23.91#ibcon#first serial, iclass 35, count 0 2006.201.10:36:23.91#ibcon#enter sib2, iclass 35, count 0 2006.201.10:36:23.91#ibcon#flushed, iclass 35, count 0 2006.201.10:36:23.91#ibcon#about to write, iclass 35, count 0 2006.201.10:36:23.91#ibcon#wrote, iclass 35, count 0 2006.201.10:36:23.91#ibcon#about to read 3, iclass 35, count 0 2006.201.10:36:23.93#ibcon#read 3, iclass 35, count 0 2006.201.10:36:23.93#ibcon#about to read 4, iclass 35, count 0 2006.201.10:36:23.93#ibcon#read 4, iclass 35, count 0 2006.201.10:36:23.93#ibcon#about to read 5, iclass 35, count 0 2006.201.10:36:23.93#ibcon#read 5, iclass 35, count 0 2006.201.10:36:23.93#ibcon#about to read 6, iclass 35, count 0 2006.201.10:36:23.93#ibcon#read 6, iclass 35, count 0 2006.201.10:36:23.93#ibcon#end of sib2, iclass 35, count 0 2006.201.10:36:23.93#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:36:23.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:36:23.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:36:23.93#ibcon#*before write, iclass 35, count 0 2006.201.10:36:23.93#ibcon#enter sib2, iclass 35, count 0 2006.201.10:36:23.93#ibcon#flushed, iclass 35, count 0 2006.201.10:36:23.93#ibcon#about to write, iclass 35, count 0 2006.201.10:36:23.93#ibcon#wrote, iclass 35, count 0 2006.201.10:36:23.93#ibcon#about to read 3, iclass 35, count 0 2006.201.10:36:23.98#ibcon#read 3, iclass 35, count 0 2006.201.10:36:23.98#ibcon#about to read 4, iclass 35, count 0 2006.201.10:36:23.98#ibcon#read 4, iclass 35, count 0 2006.201.10:36:23.98#ibcon#about to read 5, iclass 35, count 0 2006.201.10:36:23.98#ibcon#read 5, iclass 35, count 0 2006.201.10:36:23.98#ibcon#about to read 6, iclass 35, count 0 2006.201.10:36:23.98#ibcon#read 6, iclass 35, count 0 2006.201.10:36:23.98#ibcon#end of sib2, iclass 35, count 0 2006.201.10:36:23.98#ibcon#*after write, iclass 35, count 0 2006.201.10:36:23.98#ibcon#*before return 0, iclass 35, count 0 2006.201.10:36:23.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:23.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:36:23.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:36:23.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:36:23.98$vck44/vb=2,5 2006.201.10:36:23.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.10:36:23.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.10:36:23.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:23.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:24.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:24.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:24.03#ibcon#enter wrdev, iclass 37, count 2 2006.201.10:36:24.03#ibcon#first serial, iclass 37, count 2 2006.201.10:36:24.03#ibcon#enter sib2, iclass 37, count 2 2006.201.10:36:24.03#ibcon#flushed, iclass 37, count 2 2006.201.10:36:24.03#ibcon#about to write, iclass 37, count 2 2006.201.10:36:24.03#ibcon#wrote, iclass 37, count 2 2006.201.10:36:24.03#ibcon#about to read 3, iclass 37, count 2 2006.201.10:36:24.05#ibcon#read 3, iclass 37, count 2 2006.201.10:36:24.05#ibcon#about to read 4, iclass 37, count 2 2006.201.10:36:24.05#ibcon#read 4, iclass 37, count 2 2006.201.10:36:24.05#ibcon#about to read 5, iclass 37, count 2 2006.201.10:36:24.05#ibcon#read 5, iclass 37, count 2 2006.201.10:36:24.05#ibcon#about to read 6, iclass 37, count 2 2006.201.10:36:24.05#ibcon#read 6, iclass 37, count 2 2006.201.10:36:24.05#ibcon#end of sib2, iclass 37, count 2 2006.201.10:36:24.05#ibcon#*mode == 0, iclass 37, count 2 2006.201.10:36:24.05#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.10:36:24.05#ibcon#[27=AT02-05\r\n] 2006.201.10:36:24.05#ibcon#*before write, iclass 37, count 2 2006.201.10:36:24.05#ibcon#enter sib2, iclass 37, count 2 2006.201.10:36:24.05#ibcon#flushed, iclass 37, count 2 2006.201.10:36:24.05#ibcon#about to write, iclass 37, count 2 2006.201.10:36:24.05#ibcon#wrote, iclass 37, count 2 2006.201.10:36:24.05#ibcon#about to read 3, iclass 37, count 2 2006.201.10:36:24.08#ibcon#read 3, iclass 37, count 2 2006.201.10:36:24.08#ibcon#about to read 4, iclass 37, count 2 2006.201.10:36:24.08#ibcon#read 4, iclass 37, count 2 2006.201.10:36:24.08#ibcon#about to read 5, iclass 37, count 2 2006.201.10:36:24.08#ibcon#read 5, iclass 37, count 2 2006.201.10:36:24.08#ibcon#about to read 6, iclass 37, count 2 2006.201.10:36:24.08#ibcon#read 6, iclass 37, count 2 2006.201.10:36:24.08#ibcon#end of sib2, iclass 37, count 2 2006.201.10:36:24.08#ibcon#*after write, iclass 37, count 2 2006.201.10:36:24.08#ibcon#*before return 0, iclass 37, count 2 2006.201.10:36:24.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:24.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:36:24.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.10:36:24.08#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:24.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:24.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:24.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:24.20#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:36:24.20#ibcon#first serial, iclass 37, count 0 2006.201.10:36:24.20#ibcon#enter sib2, iclass 37, count 0 2006.201.10:36:24.20#ibcon#flushed, iclass 37, count 0 2006.201.10:36:24.20#ibcon#about to write, iclass 37, count 0 2006.201.10:36:24.20#ibcon#wrote, iclass 37, count 0 2006.201.10:36:24.20#ibcon#about to read 3, iclass 37, count 0 2006.201.10:36:24.22#ibcon#read 3, iclass 37, count 0 2006.201.10:36:24.22#ibcon#about to read 4, iclass 37, count 0 2006.201.10:36:24.22#ibcon#read 4, iclass 37, count 0 2006.201.10:36:24.22#ibcon#about to read 5, iclass 37, count 0 2006.201.10:36:24.22#ibcon#read 5, iclass 37, count 0 2006.201.10:36:24.22#ibcon#about to read 6, iclass 37, count 0 2006.201.10:36:24.22#ibcon#read 6, iclass 37, count 0 2006.201.10:36:24.22#ibcon#end of sib2, iclass 37, count 0 2006.201.10:36:24.22#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:36:24.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:36:24.22#ibcon#[27=USB\r\n] 2006.201.10:36:24.22#ibcon#*before write, iclass 37, count 0 2006.201.10:36:24.22#ibcon#enter sib2, iclass 37, count 0 2006.201.10:36:24.22#ibcon#flushed, iclass 37, count 0 2006.201.10:36:24.22#ibcon#about to write, iclass 37, count 0 2006.201.10:36:24.22#ibcon#wrote, iclass 37, count 0 2006.201.10:36:24.22#ibcon#about to read 3, iclass 37, count 0 2006.201.10:36:24.25#ibcon#read 3, iclass 37, count 0 2006.201.10:36:24.25#ibcon#about to read 4, iclass 37, count 0 2006.201.10:36:24.25#ibcon#read 4, iclass 37, count 0 2006.201.10:36:24.25#ibcon#about to read 5, iclass 37, count 0 2006.201.10:36:24.25#ibcon#read 5, iclass 37, count 0 2006.201.10:36:24.25#ibcon#about to read 6, iclass 37, count 0 2006.201.10:36:24.25#ibcon#read 6, iclass 37, count 0 2006.201.10:36:24.25#ibcon#end of sib2, iclass 37, count 0 2006.201.10:36:24.25#ibcon#*after write, iclass 37, count 0 2006.201.10:36:24.25#ibcon#*before return 0, iclass 37, count 0 2006.201.10:36:24.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:24.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:36:24.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:36:24.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:36:24.25$vck44/vblo=3,649.99 2006.201.10:36:24.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.10:36:24.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.10:36:24.25#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:24.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:24.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:24.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:24.25#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:36:24.25#ibcon#first serial, iclass 39, count 0 2006.201.10:36:24.25#ibcon#enter sib2, iclass 39, count 0 2006.201.10:36:24.25#ibcon#flushed, iclass 39, count 0 2006.201.10:36:24.25#ibcon#about to write, iclass 39, count 0 2006.201.10:36:24.25#ibcon#wrote, iclass 39, count 0 2006.201.10:36:24.25#ibcon#about to read 3, iclass 39, count 0 2006.201.10:36:24.27#ibcon#read 3, iclass 39, count 0 2006.201.10:36:24.27#ibcon#about to read 4, iclass 39, count 0 2006.201.10:36:24.27#ibcon#read 4, iclass 39, count 0 2006.201.10:36:24.27#ibcon#about to read 5, iclass 39, count 0 2006.201.10:36:24.27#ibcon#read 5, iclass 39, count 0 2006.201.10:36:24.27#ibcon#about to read 6, iclass 39, count 0 2006.201.10:36:24.27#ibcon#read 6, iclass 39, count 0 2006.201.10:36:24.27#ibcon#end of sib2, iclass 39, count 0 2006.201.10:36:24.27#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:36:24.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:36:24.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:36:24.27#ibcon#*before write, iclass 39, count 0 2006.201.10:36:24.27#ibcon#enter sib2, iclass 39, count 0 2006.201.10:36:24.27#ibcon#flushed, iclass 39, count 0 2006.201.10:36:24.27#ibcon#about to write, iclass 39, count 0 2006.201.10:36:24.27#ibcon#wrote, iclass 39, count 0 2006.201.10:36:24.27#ibcon#about to read 3, iclass 39, count 0 2006.201.10:36:24.31#ibcon#read 3, iclass 39, count 0 2006.201.10:36:24.31#ibcon#about to read 4, iclass 39, count 0 2006.201.10:36:24.31#ibcon#read 4, iclass 39, count 0 2006.201.10:36:24.31#ibcon#about to read 5, iclass 39, count 0 2006.201.10:36:24.31#ibcon#read 5, iclass 39, count 0 2006.201.10:36:24.31#ibcon#about to read 6, iclass 39, count 0 2006.201.10:36:24.31#ibcon#read 6, iclass 39, count 0 2006.201.10:36:24.31#ibcon#end of sib2, iclass 39, count 0 2006.201.10:36:24.31#ibcon#*after write, iclass 39, count 0 2006.201.10:36:24.31#ibcon#*before return 0, iclass 39, count 0 2006.201.10:36:24.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:24.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:36:24.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:36:24.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:36:24.31$vck44/vb=3,4 2006.201.10:36:24.31#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.10:36:24.31#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.10:36:24.31#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:24.31#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:24.37#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:24.37#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:24.37#ibcon#enter wrdev, iclass 2, count 2 2006.201.10:36:24.37#ibcon#first serial, iclass 2, count 2 2006.201.10:36:24.37#ibcon#enter sib2, iclass 2, count 2 2006.201.10:36:24.37#ibcon#flushed, iclass 2, count 2 2006.201.10:36:24.37#ibcon#about to write, iclass 2, count 2 2006.201.10:36:24.37#ibcon#wrote, iclass 2, count 2 2006.201.10:36:24.37#ibcon#about to read 3, iclass 2, count 2 2006.201.10:36:24.39#ibcon#read 3, iclass 2, count 2 2006.201.10:36:24.39#ibcon#about to read 4, iclass 2, count 2 2006.201.10:36:24.39#ibcon#read 4, iclass 2, count 2 2006.201.10:36:24.39#ibcon#about to read 5, iclass 2, count 2 2006.201.10:36:24.39#ibcon#read 5, iclass 2, count 2 2006.201.10:36:24.39#ibcon#about to read 6, iclass 2, count 2 2006.201.10:36:24.39#ibcon#read 6, iclass 2, count 2 2006.201.10:36:24.39#ibcon#end of sib2, iclass 2, count 2 2006.201.10:36:24.39#ibcon#*mode == 0, iclass 2, count 2 2006.201.10:36:24.39#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.10:36:24.39#ibcon#[27=AT03-04\r\n] 2006.201.10:36:24.39#ibcon#*before write, iclass 2, count 2 2006.201.10:36:24.39#ibcon#enter sib2, iclass 2, count 2 2006.201.10:36:24.39#ibcon#flushed, iclass 2, count 2 2006.201.10:36:24.39#ibcon#about to write, iclass 2, count 2 2006.201.10:36:24.39#ibcon#wrote, iclass 2, count 2 2006.201.10:36:24.39#ibcon#about to read 3, iclass 2, count 2 2006.201.10:36:24.42#ibcon#read 3, iclass 2, count 2 2006.201.10:36:24.42#ibcon#about to read 4, iclass 2, count 2 2006.201.10:36:24.42#ibcon#read 4, iclass 2, count 2 2006.201.10:36:24.42#ibcon#about to read 5, iclass 2, count 2 2006.201.10:36:24.42#ibcon#read 5, iclass 2, count 2 2006.201.10:36:24.42#ibcon#about to read 6, iclass 2, count 2 2006.201.10:36:24.42#ibcon#read 6, iclass 2, count 2 2006.201.10:36:24.42#ibcon#end of sib2, iclass 2, count 2 2006.201.10:36:24.42#ibcon#*after write, iclass 2, count 2 2006.201.10:36:24.42#ibcon#*before return 0, iclass 2, count 2 2006.201.10:36:24.42#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:24.42#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:36:24.42#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.10:36:24.42#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:24.42#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:24.54#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:24.54#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:24.54#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:36:24.54#ibcon#first serial, iclass 2, count 0 2006.201.10:36:24.54#ibcon#enter sib2, iclass 2, count 0 2006.201.10:36:24.54#ibcon#flushed, iclass 2, count 0 2006.201.10:36:24.54#ibcon#about to write, iclass 2, count 0 2006.201.10:36:24.54#ibcon#wrote, iclass 2, count 0 2006.201.10:36:24.54#ibcon#about to read 3, iclass 2, count 0 2006.201.10:36:24.56#ibcon#read 3, iclass 2, count 0 2006.201.10:36:24.56#ibcon#about to read 4, iclass 2, count 0 2006.201.10:36:24.56#ibcon#read 4, iclass 2, count 0 2006.201.10:36:24.56#ibcon#about to read 5, iclass 2, count 0 2006.201.10:36:24.56#ibcon#read 5, iclass 2, count 0 2006.201.10:36:24.56#ibcon#about to read 6, iclass 2, count 0 2006.201.10:36:24.56#ibcon#read 6, iclass 2, count 0 2006.201.10:36:24.56#ibcon#end of sib2, iclass 2, count 0 2006.201.10:36:24.56#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:36:24.56#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:36:24.56#ibcon#[27=USB\r\n] 2006.201.10:36:24.56#ibcon#*before write, iclass 2, count 0 2006.201.10:36:24.56#ibcon#enter sib2, iclass 2, count 0 2006.201.10:36:24.56#ibcon#flushed, iclass 2, count 0 2006.201.10:36:24.56#ibcon#about to write, iclass 2, count 0 2006.201.10:36:24.56#ibcon#wrote, iclass 2, count 0 2006.201.10:36:24.56#ibcon#about to read 3, iclass 2, count 0 2006.201.10:36:24.59#ibcon#read 3, iclass 2, count 0 2006.201.10:36:24.59#ibcon#about to read 4, iclass 2, count 0 2006.201.10:36:24.59#ibcon#read 4, iclass 2, count 0 2006.201.10:36:24.59#ibcon#about to read 5, iclass 2, count 0 2006.201.10:36:24.59#ibcon#read 5, iclass 2, count 0 2006.201.10:36:24.59#ibcon#about to read 6, iclass 2, count 0 2006.201.10:36:24.59#ibcon#read 6, iclass 2, count 0 2006.201.10:36:24.59#ibcon#end of sib2, iclass 2, count 0 2006.201.10:36:24.59#ibcon#*after write, iclass 2, count 0 2006.201.10:36:24.59#ibcon#*before return 0, iclass 2, count 0 2006.201.10:36:24.59#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:24.59#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:36:24.59#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:36:24.59#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:36:24.59$vck44/vblo=4,679.99 2006.201.10:36:24.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.10:36:24.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.10:36:24.59#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:24.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:36:24.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:36:24.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:36:24.59#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:36:24.59#ibcon#first serial, iclass 6, count 0 2006.201.10:36:24.59#ibcon#enter sib2, iclass 6, count 0 2006.201.10:36:24.59#ibcon#flushed, iclass 6, count 0 2006.201.10:36:24.59#ibcon#about to write, iclass 6, count 0 2006.201.10:36:24.59#ibcon#wrote, iclass 6, count 0 2006.201.10:36:24.59#ibcon#about to read 3, iclass 6, count 0 2006.201.10:36:24.61#ibcon#read 3, iclass 6, count 0 2006.201.10:36:24.61#ibcon#about to read 4, iclass 6, count 0 2006.201.10:36:24.61#ibcon#read 4, iclass 6, count 0 2006.201.10:36:24.61#ibcon#about to read 5, iclass 6, count 0 2006.201.10:36:24.61#ibcon#read 5, iclass 6, count 0 2006.201.10:36:24.61#ibcon#about to read 6, iclass 6, count 0 2006.201.10:36:24.61#ibcon#read 6, iclass 6, count 0 2006.201.10:36:24.61#ibcon#end of sib2, iclass 6, count 0 2006.201.10:36:24.61#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:36:24.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:36:24.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:36:24.61#ibcon#*before write, iclass 6, count 0 2006.201.10:36:24.61#ibcon#enter sib2, iclass 6, count 0 2006.201.10:36:24.61#ibcon#flushed, iclass 6, count 0 2006.201.10:36:24.61#ibcon#about to write, iclass 6, count 0 2006.201.10:36:24.61#ibcon#wrote, iclass 6, count 0 2006.201.10:36:24.61#ibcon#about to read 3, iclass 6, count 0 2006.201.10:36:24.63#abcon#<5=/05 2.1 3.8 21.66 971003.7\r\n> 2006.201.10:36:24.65#abcon#{5=INTERFACE CLEAR} 2006.201.10:36:24.65#ibcon#read 3, iclass 6, count 0 2006.201.10:36:24.65#ibcon#about to read 4, iclass 6, count 0 2006.201.10:36:24.65#ibcon#read 4, iclass 6, count 0 2006.201.10:36:24.65#ibcon#about to read 5, iclass 6, count 0 2006.201.10:36:24.65#ibcon#read 5, iclass 6, count 0 2006.201.10:36:24.65#ibcon#about to read 6, iclass 6, count 0 2006.201.10:36:24.65#ibcon#read 6, iclass 6, count 0 2006.201.10:36:24.65#ibcon#end of sib2, iclass 6, count 0 2006.201.10:36:24.65#ibcon#*after write, iclass 6, count 0 2006.201.10:36:24.65#ibcon#*before return 0, iclass 6, count 0 2006.201.10:36:24.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:36:24.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:36:24.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:36:24.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:36:24.65$vck44/vb=4,5 2006.201.10:36:24.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.10:36:24.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.10:36:24.65#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:24.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:36:24.71#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:36:24.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:36:24.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:36:24.71#ibcon#enter wrdev, iclass 12, count 2 2006.201.10:36:24.71#ibcon#first serial, iclass 12, count 2 2006.201.10:36:24.71#ibcon#enter sib2, iclass 12, count 2 2006.201.10:36:24.71#ibcon#flushed, iclass 12, count 2 2006.201.10:36:24.71#ibcon#about to write, iclass 12, count 2 2006.201.10:36:24.71#ibcon#wrote, iclass 12, count 2 2006.201.10:36:24.71#ibcon#about to read 3, iclass 12, count 2 2006.201.10:36:24.73#ibcon#read 3, iclass 12, count 2 2006.201.10:36:24.73#ibcon#about to read 4, iclass 12, count 2 2006.201.10:36:24.73#ibcon#read 4, iclass 12, count 2 2006.201.10:36:24.73#ibcon#about to read 5, iclass 12, count 2 2006.201.10:36:24.73#ibcon#read 5, iclass 12, count 2 2006.201.10:36:24.73#ibcon#about to read 6, iclass 12, count 2 2006.201.10:36:24.73#ibcon#read 6, iclass 12, count 2 2006.201.10:36:24.73#ibcon#end of sib2, iclass 12, count 2 2006.201.10:36:24.73#ibcon#*mode == 0, iclass 12, count 2 2006.201.10:36:24.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.10:36:24.73#ibcon#[27=AT04-05\r\n] 2006.201.10:36:24.73#ibcon#*before write, iclass 12, count 2 2006.201.10:36:24.73#ibcon#enter sib2, iclass 12, count 2 2006.201.10:36:24.73#ibcon#flushed, iclass 12, count 2 2006.201.10:36:24.73#ibcon#about to write, iclass 12, count 2 2006.201.10:36:24.73#ibcon#wrote, iclass 12, count 2 2006.201.10:36:24.73#ibcon#about to read 3, iclass 12, count 2 2006.201.10:36:24.76#ibcon#read 3, iclass 12, count 2 2006.201.10:36:24.76#ibcon#about to read 4, iclass 12, count 2 2006.201.10:36:24.76#ibcon#read 4, iclass 12, count 2 2006.201.10:36:24.76#ibcon#about to read 5, iclass 12, count 2 2006.201.10:36:24.76#ibcon#read 5, iclass 12, count 2 2006.201.10:36:24.76#ibcon#about to read 6, iclass 12, count 2 2006.201.10:36:24.76#ibcon#read 6, iclass 12, count 2 2006.201.10:36:24.76#ibcon#end of sib2, iclass 12, count 2 2006.201.10:36:24.76#ibcon#*after write, iclass 12, count 2 2006.201.10:36:24.76#ibcon#*before return 0, iclass 12, count 2 2006.201.10:36:24.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:36:24.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:36:24.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.10:36:24.76#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:24.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:36:24.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:36:24.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:36:24.88#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:36:24.88#ibcon#first serial, iclass 12, count 0 2006.201.10:36:24.88#ibcon#enter sib2, iclass 12, count 0 2006.201.10:36:24.88#ibcon#flushed, iclass 12, count 0 2006.201.10:36:24.88#ibcon#about to write, iclass 12, count 0 2006.201.10:36:24.88#ibcon#wrote, iclass 12, count 0 2006.201.10:36:24.88#ibcon#about to read 3, iclass 12, count 0 2006.201.10:36:24.90#ibcon#read 3, iclass 12, count 0 2006.201.10:36:24.90#ibcon#about to read 4, iclass 12, count 0 2006.201.10:36:24.90#ibcon#read 4, iclass 12, count 0 2006.201.10:36:24.90#ibcon#about to read 5, iclass 12, count 0 2006.201.10:36:24.90#ibcon#read 5, iclass 12, count 0 2006.201.10:36:24.90#ibcon#about to read 6, iclass 12, count 0 2006.201.10:36:24.90#ibcon#read 6, iclass 12, count 0 2006.201.10:36:24.90#ibcon#end of sib2, iclass 12, count 0 2006.201.10:36:24.90#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:36:24.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:36:24.90#ibcon#[27=USB\r\n] 2006.201.10:36:24.90#ibcon#*before write, iclass 12, count 0 2006.201.10:36:24.90#ibcon#enter sib2, iclass 12, count 0 2006.201.10:36:24.90#ibcon#flushed, iclass 12, count 0 2006.201.10:36:24.90#ibcon#about to write, iclass 12, count 0 2006.201.10:36:24.90#ibcon#wrote, iclass 12, count 0 2006.201.10:36:24.90#ibcon#about to read 3, iclass 12, count 0 2006.201.10:36:24.93#ibcon#read 3, iclass 12, count 0 2006.201.10:36:24.93#ibcon#about to read 4, iclass 12, count 0 2006.201.10:36:24.93#ibcon#read 4, iclass 12, count 0 2006.201.10:36:24.93#ibcon#about to read 5, iclass 12, count 0 2006.201.10:36:24.93#ibcon#read 5, iclass 12, count 0 2006.201.10:36:24.93#ibcon#about to read 6, iclass 12, count 0 2006.201.10:36:24.93#ibcon#read 6, iclass 12, count 0 2006.201.10:36:24.93#ibcon#end of sib2, iclass 12, count 0 2006.201.10:36:24.93#ibcon#*after write, iclass 12, count 0 2006.201.10:36:24.93#ibcon#*before return 0, iclass 12, count 0 2006.201.10:36:24.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:36:24.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:36:24.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:36:24.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:36:24.93$vck44/vblo=5,709.99 2006.201.10:36:24.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.10:36:24.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.10:36:24.93#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:24.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:24.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:24.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:24.93#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:36:24.93#ibcon#first serial, iclass 15, count 0 2006.201.10:36:24.93#ibcon#enter sib2, iclass 15, count 0 2006.201.10:36:24.93#ibcon#flushed, iclass 15, count 0 2006.201.10:36:24.93#ibcon#about to write, iclass 15, count 0 2006.201.10:36:24.93#ibcon#wrote, iclass 15, count 0 2006.201.10:36:24.93#ibcon#about to read 3, iclass 15, count 0 2006.201.10:36:24.95#ibcon#read 3, iclass 15, count 0 2006.201.10:36:24.95#ibcon#about to read 4, iclass 15, count 0 2006.201.10:36:24.95#ibcon#read 4, iclass 15, count 0 2006.201.10:36:24.95#ibcon#about to read 5, iclass 15, count 0 2006.201.10:36:24.95#ibcon#read 5, iclass 15, count 0 2006.201.10:36:24.95#ibcon#about to read 6, iclass 15, count 0 2006.201.10:36:24.95#ibcon#read 6, iclass 15, count 0 2006.201.10:36:24.95#ibcon#end of sib2, iclass 15, count 0 2006.201.10:36:24.95#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:36:24.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:36:24.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:36:24.95#ibcon#*before write, iclass 15, count 0 2006.201.10:36:24.95#ibcon#enter sib2, iclass 15, count 0 2006.201.10:36:24.95#ibcon#flushed, iclass 15, count 0 2006.201.10:36:24.95#ibcon#about to write, iclass 15, count 0 2006.201.10:36:24.95#ibcon#wrote, iclass 15, count 0 2006.201.10:36:24.95#ibcon#about to read 3, iclass 15, count 0 2006.201.10:36:25.00#ibcon#read 3, iclass 15, count 0 2006.201.10:36:25.00#ibcon#about to read 4, iclass 15, count 0 2006.201.10:36:25.00#ibcon#read 4, iclass 15, count 0 2006.201.10:36:25.00#ibcon#about to read 5, iclass 15, count 0 2006.201.10:36:25.00#ibcon#read 5, iclass 15, count 0 2006.201.10:36:25.00#ibcon#about to read 6, iclass 15, count 0 2006.201.10:36:25.00#ibcon#read 6, iclass 15, count 0 2006.201.10:36:25.00#ibcon#end of sib2, iclass 15, count 0 2006.201.10:36:25.00#ibcon#*after write, iclass 15, count 0 2006.201.10:36:25.00#ibcon#*before return 0, iclass 15, count 0 2006.201.10:36:25.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:25.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:36:25.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:36:25.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:36:25.00$vck44/vb=5,4 2006.201.10:36:25.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.10:36:25.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.10:36:25.00#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:25.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:25.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:25.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:25.05#ibcon#enter wrdev, iclass 17, count 2 2006.201.10:36:25.05#ibcon#first serial, iclass 17, count 2 2006.201.10:36:25.05#ibcon#enter sib2, iclass 17, count 2 2006.201.10:36:25.05#ibcon#flushed, iclass 17, count 2 2006.201.10:36:25.05#ibcon#about to write, iclass 17, count 2 2006.201.10:36:25.05#ibcon#wrote, iclass 17, count 2 2006.201.10:36:25.05#ibcon#about to read 3, iclass 17, count 2 2006.201.10:36:25.07#ibcon#read 3, iclass 17, count 2 2006.201.10:36:25.07#ibcon#about to read 4, iclass 17, count 2 2006.201.10:36:25.07#ibcon#read 4, iclass 17, count 2 2006.201.10:36:25.07#ibcon#about to read 5, iclass 17, count 2 2006.201.10:36:25.07#ibcon#read 5, iclass 17, count 2 2006.201.10:36:25.07#ibcon#about to read 6, iclass 17, count 2 2006.201.10:36:25.07#ibcon#read 6, iclass 17, count 2 2006.201.10:36:25.07#ibcon#end of sib2, iclass 17, count 2 2006.201.10:36:25.07#ibcon#*mode == 0, iclass 17, count 2 2006.201.10:36:25.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.10:36:25.07#ibcon#[27=AT05-04\r\n] 2006.201.10:36:25.07#ibcon#*before write, iclass 17, count 2 2006.201.10:36:25.07#ibcon#enter sib2, iclass 17, count 2 2006.201.10:36:25.07#ibcon#flushed, iclass 17, count 2 2006.201.10:36:25.07#ibcon#about to write, iclass 17, count 2 2006.201.10:36:25.07#ibcon#wrote, iclass 17, count 2 2006.201.10:36:25.07#ibcon#about to read 3, iclass 17, count 2 2006.201.10:36:25.10#ibcon#read 3, iclass 17, count 2 2006.201.10:36:25.10#ibcon#about to read 4, iclass 17, count 2 2006.201.10:36:25.10#ibcon#read 4, iclass 17, count 2 2006.201.10:36:25.10#ibcon#about to read 5, iclass 17, count 2 2006.201.10:36:25.10#ibcon#read 5, iclass 17, count 2 2006.201.10:36:25.10#ibcon#about to read 6, iclass 17, count 2 2006.201.10:36:25.10#ibcon#read 6, iclass 17, count 2 2006.201.10:36:25.10#ibcon#end of sib2, iclass 17, count 2 2006.201.10:36:25.10#ibcon#*after write, iclass 17, count 2 2006.201.10:36:25.10#ibcon#*before return 0, iclass 17, count 2 2006.201.10:36:25.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:25.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:36:25.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.10:36:25.10#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:25.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:25.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:25.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:25.22#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:36:25.22#ibcon#first serial, iclass 17, count 0 2006.201.10:36:25.22#ibcon#enter sib2, iclass 17, count 0 2006.201.10:36:25.22#ibcon#flushed, iclass 17, count 0 2006.201.10:36:25.22#ibcon#about to write, iclass 17, count 0 2006.201.10:36:25.22#ibcon#wrote, iclass 17, count 0 2006.201.10:36:25.22#ibcon#about to read 3, iclass 17, count 0 2006.201.10:36:25.24#ibcon#read 3, iclass 17, count 0 2006.201.10:36:25.24#ibcon#about to read 4, iclass 17, count 0 2006.201.10:36:25.24#ibcon#read 4, iclass 17, count 0 2006.201.10:36:25.24#ibcon#about to read 5, iclass 17, count 0 2006.201.10:36:25.24#ibcon#read 5, iclass 17, count 0 2006.201.10:36:25.24#ibcon#about to read 6, iclass 17, count 0 2006.201.10:36:25.24#ibcon#read 6, iclass 17, count 0 2006.201.10:36:25.24#ibcon#end of sib2, iclass 17, count 0 2006.201.10:36:25.24#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:36:25.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:36:25.24#ibcon#[27=USB\r\n] 2006.201.10:36:25.24#ibcon#*before write, iclass 17, count 0 2006.201.10:36:25.24#ibcon#enter sib2, iclass 17, count 0 2006.201.10:36:25.24#ibcon#flushed, iclass 17, count 0 2006.201.10:36:25.24#ibcon#about to write, iclass 17, count 0 2006.201.10:36:25.24#ibcon#wrote, iclass 17, count 0 2006.201.10:36:25.24#ibcon#about to read 3, iclass 17, count 0 2006.201.10:36:25.27#ibcon#read 3, iclass 17, count 0 2006.201.10:36:25.27#ibcon#about to read 4, iclass 17, count 0 2006.201.10:36:25.27#ibcon#read 4, iclass 17, count 0 2006.201.10:36:25.27#ibcon#about to read 5, iclass 17, count 0 2006.201.10:36:25.27#ibcon#read 5, iclass 17, count 0 2006.201.10:36:25.27#ibcon#about to read 6, iclass 17, count 0 2006.201.10:36:25.27#ibcon#read 6, iclass 17, count 0 2006.201.10:36:25.27#ibcon#end of sib2, iclass 17, count 0 2006.201.10:36:25.27#ibcon#*after write, iclass 17, count 0 2006.201.10:36:25.27#ibcon#*before return 0, iclass 17, count 0 2006.201.10:36:25.27#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:25.27#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:36:25.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:36:25.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:36:25.27$vck44/vblo=6,719.99 2006.201.10:36:25.27#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.10:36:25.27#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.10:36:25.27#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:25.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:25.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:25.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:25.27#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:36:25.27#ibcon#first serial, iclass 19, count 0 2006.201.10:36:25.27#ibcon#enter sib2, iclass 19, count 0 2006.201.10:36:25.27#ibcon#flushed, iclass 19, count 0 2006.201.10:36:25.27#ibcon#about to write, iclass 19, count 0 2006.201.10:36:25.27#ibcon#wrote, iclass 19, count 0 2006.201.10:36:25.27#ibcon#about to read 3, iclass 19, count 0 2006.201.10:36:25.29#ibcon#read 3, iclass 19, count 0 2006.201.10:36:25.29#ibcon#about to read 4, iclass 19, count 0 2006.201.10:36:25.29#ibcon#read 4, iclass 19, count 0 2006.201.10:36:25.29#ibcon#about to read 5, iclass 19, count 0 2006.201.10:36:25.29#ibcon#read 5, iclass 19, count 0 2006.201.10:36:25.29#ibcon#about to read 6, iclass 19, count 0 2006.201.10:36:25.29#ibcon#read 6, iclass 19, count 0 2006.201.10:36:25.29#ibcon#end of sib2, iclass 19, count 0 2006.201.10:36:25.29#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:36:25.29#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:36:25.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:36:25.29#ibcon#*before write, iclass 19, count 0 2006.201.10:36:25.29#ibcon#enter sib2, iclass 19, count 0 2006.201.10:36:25.29#ibcon#flushed, iclass 19, count 0 2006.201.10:36:25.29#ibcon#about to write, iclass 19, count 0 2006.201.10:36:25.29#ibcon#wrote, iclass 19, count 0 2006.201.10:36:25.29#ibcon#about to read 3, iclass 19, count 0 2006.201.10:36:25.33#ibcon#read 3, iclass 19, count 0 2006.201.10:36:25.33#ibcon#about to read 4, iclass 19, count 0 2006.201.10:36:25.33#ibcon#read 4, iclass 19, count 0 2006.201.10:36:25.33#ibcon#about to read 5, iclass 19, count 0 2006.201.10:36:25.33#ibcon#read 5, iclass 19, count 0 2006.201.10:36:25.33#ibcon#about to read 6, iclass 19, count 0 2006.201.10:36:25.33#ibcon#read 6, iclass 19, count 0 2006.201.10:36:25.33#ibcon#end of sib2, iclass 19, count 0 2006.201.10:36:25.33#ibcon#*after write, iclass 19, count 0 2006.201.10:36:25.33#ibcon#*before return 0, iclass 19, count 0 2006.201.10:36:25.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:25.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:36:25.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:36:25.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:36:25.33$vck44/vb=6,4 2006.201.10:36:25.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.10:36:25.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.10:36:25.33#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:25.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:25.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:25.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:25.39#ibcon#enter wrdev, iclass 21, count 2 2006.201.10:36:25.39#ibcon#first serial, iclass 21, count 2 2006.201.10:36:25.39#ibcon#enter sib2, iclass 21, count 2 2006.201.10:36:25.39#ibcon#flushed, iclass 21, count 2 2006.201.10:36:25.39#ibcon#about to write, iclass 21, count 2 2006.201.10:36:25.39#ibcon#wrote, iclass 21, count 2 2006.201.10:36:25.39#ibcon#about to read 3, iclass 21, count 2 2006.201.10:36:25.41#ibcon#read 3, iclass 21, count 2 2006.201.10:36:25.41#ibcon#about to read 4, iclass 21, count 2 2006.201.10:36:25.41#ibcon#read 4, iclass 21, count 2 2006.201.10:36:25.41#ibcon#about to read 5, iclass 21, count 2 2006.201.10:36:25.41#ibcon#read 5, iclass 21, count 2 2006.201.10:36:25.41#ibcon#about to read 6, iclass 21, count 2 2006.201.10:36:25.41#ibcon#read 6, iclass 21, count 2 2006.201.10:36:25.41#ibcon#end of sib2, iclass 21, count 2 2006.201.10:36:25.41#ibcon#*mode == 0, iclass 21, count 2 2006.201.10:36:25.41#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.10:36:25.41#ibcon#[27=AT06-04\r\n] 2006.201.10:36:25.41#ibcon#*before write, iclass 21, count 2 2006.201.10:36:25.41#ibcon#enter sib2, iclass 21, count 2 2006.201.10:36:25.41#ibcon#flushed, iclass 21, count 2 2006.201.10:36:25.41#ibcon#about to write, iclass 21, count 2 2006.201.10:36:25.41#ibcon#wrote, iclass 21, count 2 2006.201.10:36:25.41#ibcon#about to read 3, iclass 21, count 2 2006.201.10:36:25.44#ibcon#read 3, iclass 21, count 2 2006.201.10:36:25.44#ibcon#about to read 4, iclass 21, count 2 2006.201.10:36:25.44#ibcon#read 4, iclass 21, count 2 2006.201.10:36:25.44#ibcon#about to read 5, iclass 21, count 2 2006.201.10:36:25.44#ibcon#read 5, iclass 21, count 2 2006.201.10:36:25.44#ibcon#about to read 6, iclass 21, count 2 2006.201.10:36:25.44#ibcon#read 6, iclass 21, count 2 2006.201.10:36:25.44#ibcon#end of sib2, iclass 21, count 2 2006.201.10:36:25.44#ibcon#*after write, iclass 21, count 2 2006.201.10:36:25.44#ibcon#*before return 0, iclass 21, count 2 2006.201.10:36:25.44#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:25.44#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:36:25.44#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.10:36:25.44#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:25.44#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:25.56#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:25.56#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:25.56#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:36:25.56#ibcon#first serial, iclass 21, count 0 2006.201.10:36:25.56#ibcon#enter sib2, iclass 21, count 0 2006.201.10:36:25.56#ibcon#flushed, iclass 21, count 0 2006.201.10:36:25.56#ibcon#about to write, iclass 21, count 0 2006.201.10:36:25.56#ibcon#wrote, iclass 21, count 0 2006.201.10:36:25.56#ibcon#about to read 3, iclass 21, count 0 2006.201.10:36:25.58#ibcon#read 3, iclass 21, count 0 2006.201.10:36:25.58#ibcon#about to read 4, iclass 21, count 0 2006.201.10:36:25.58#ibcon#read 4, iclass 21, count 0 2006.201.10:36:25.58#ibcon#about to read 5, iclass 21, count 0 2006.201.10:36:25.58#ibcon#read 5, iclass 21, count 0 2006.201.10:36:25.58#ibcon#about to read 6, iclass 21, count 0 2006.201.10:36:25.58#ibcon#read 6, iclass 21, count 0 2006.201.10:36:25.58#ibcon#end of sib2, iclass 21, count 0 2006.201.10:36:25.58#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:36:25.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:36:25.58#ibcon#[27=USB\r\n] 2006.201.10:36:25.58#ibcon#*before write, iclass 21, count 0 2006.201.10:36:25.58#ibcon#enter sib2, iclass 21, count 0 2006.201.10:36:25.58#ibcon#flushed, iclass 21, count 0 2006.201.10:36:25.58#ibcon#about to write, iclass 21, count 0 2006.201.10:36:25.58#ibcon#wrote, iclass 21, count 0 2006.201.10:36:25.58#ibcon#about to read 3, iclass 21, count 0 2006.201.10:36:25.61#ibcon#read 3, iclass 21, count 0 2006.201.10:36:25.61#ibcon#about to read 4, iclass 21, count 0 2006.201.10:36:25.61#ibcon#read 4, iclass 21, count 0 2006.201.10:36:25.61#ibcon#about to read 5, iclass 21, count 0 2006.201.10:36:25.61#ibcon#read 5, iclass 21, count 0 2006.201.10:36:25.61#ibcon#about to read 6, iclass 21, count 0 2006.201.10:36:25.61#ibcon#read 6, iclass 21, count 0 2006.201.10:36:25.61#ibcon#end of sib2, iclass 21, count 0 2006.201.10:36:25.61#ibcon#*after write, iclass 21, count 0 2006.201.10:36:25.61#ibcon#*before return 0, iclass 21, count 0 2006.201.10:36:25.61#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:25.61#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:36:25.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:36:25.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:36:25.61$vck44/vblo=7,734.99 2006.201.10:36:25.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.10:36:25.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.10:36:25.61#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:25.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:25.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:25.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:25.61#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:36:25.61#ibcon#first serial, iclass 23, count 0 2006.201.10:36:25.61#ibcon#enter sib2, iclass 23, count 0 2006.201.10:36:25.61#ibcon#flushed, iclass 23, count 0 2006.201.10:36:25.61#ibcon#about to write, iclass 23, count 0 2006.201.10:36:25.61#ibcon#wrote, iclass 23, count 0 2006.201.10:36:25.61#ibcon#about to read 3, iclass 23, count 0 2006.201.10:36:25.63#ibcon#read 3, iclass 23, count 0 2006.201.10:36:25.63#ibcon#about to read 4, iclass 23, count 0 2006.201.10:36:25.63#ibcon#read 4, iclass 23, count 0 2006.201.10:36:25.63#ibcon#about to read 5, iclass 23, count 0 2006.201.10:36:25.63#ibcon#read 5, iclass 23, count 0 2006.201.10:36:25.63#ibcon#about to read 6, iclass 23, count 0 2006.201.10:36:25.63#ibcon#read 6, iclass 23, count 0 2006.201.10:36:25.63#ibcon#end of sib2, iclass 23, count 0 2006.201.10:36:25.63#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:36:25.63#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:36:25.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:36:25.63#ibcon#*before write, iclass 23, count 0 2006.201.10:36:25.63#ibcon#enter sib2, iclass 23, count 0 2006.201.10:36:25.63#ibcon#flushed, iclass 23, count 0 2006.201.10:36:25.63#ibcon#about to write, iclass 23, count 0 2006.201.10:36:25.63#ibcon#wrote, iclass 23, count 0 2006.201.10:36:25.63#ibcon#about to read 3, iclass 23, count 0 2006.201.10:36:25.68#ibcon#read 3, iclass 23, count 0 2006.201.10:36:25.68#ibcon#about to read 4, iclass 23, count 0 2006.201.10:36:25.68#ibcon#read 4, iclass 23, count 0 2006.201.10:36:25.68#ibcon#about to read 5, iclass 23, count 0 2006.201.10:36:25.68#ibcon#read 5, iclass 23, count 0 2006.201.10:36:25.68#ibcon#about to read 6, iclass 23, count 0 2006.201.10:36:25.68#ibcon#read 6, iclass 23, count 0 2006.201.10:36:25.68#ibcon#end of sib2, iclass 23, count 0 2006.201.10:36:25.68#ibcon#*after write, iclass 23, count 0 2006.201.10:36:25.68#ibcon#*before return 0, iclass 23, count 0 2006.201.10:36:25.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:25.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:36:25.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:36:25.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:36:25.68$vck44/vb=7,4 2006.201.10:36:25.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.10:36:25.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.10:36:25.68#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:25.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:25.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:25.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:25.73#ibcon#enter wrdev, iclass 25, count 2 2006.201.10:36:25.73#ibcon#first serial, iclass 25, count 2 2006.201.10:36:25.73#ibcon#enter sib2, iclass 25, count 2 2006.201.10:36:25.73#ibcon#flushed, iclass 25, count 2 2006.201.10:36:25.73#ibcon#about to write, iclass 25, count 2 2006.201.10:36:25.73#ibcon#wrote, iclass 25, count 2 2006.201.10:36:25.73#ibcon#about to read 3, iclass 25, count 2 2006.201.10:36:25.75#ibcon#read 3, iclass 25, count 2 2006.201.10:36:25.75#ibcon#about to read 4, iclass 25, count 2 2006.201.10:36:25.75#ibcon#read 4, iclass 25, count 2 2006.201.10:36:25.75#ibcon#about to read 5, iclass 25, count 2 2006.201.10:36:25.75#ibcon#read 5, iclass 25, count 2 2006.201.10:36:25.75#ibcon#about to read 6, iclass 25, count 2 2006.201.10:36:25.75#ibcon#read 6, iclass 25, count 2 2006.201.10:36:25.75#ibcon#end of sib2, iclass 25, count 2 2006.201.10:36:25.75#ibcon#*mode == 0, iclass 25, count 2 2006.201.10:36:25.75#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.10:36:25.75#ibcon#[27=AT07-04\r\n] 2006.201.10:36:25.75#ibcon#*before write, iclass 25, count 2 2006.201.10:36:25.75#ibcon#enter sib2, iclass 25, count 2 2006.201.10:36:25.75#ibcon#flushed, iclass 25, count 2 2006.201.10:36:25.75#ibcon#about to write, iclass 25, count 2 2006.201.10:36:25.75#ibcon#wrote, iclass 25, count 2 2006.201.10:36:25.75#ibcon#about to read 3, iclass 25, count 2 2006.201.10:36:25.78#ibcon#read 3, iclass 25, count 2 2006.201.10:36:25.78#ibcon#about to read 4, iclass 25, count 2 2006.201.10:36:25.78#ibcon#read 4, iclass 25, count 2 2006.201.10:36:25.78#ibcon#about to read 5, iclass 25, count 2 2006.201.10:36:25.78#ibcon#read 5, iclass 25, count 2 2006.201.10:36:25.78#ibcon#about to read 6, iclass 25, count 2 2006.201.10:36:25.78#ibcon#read 6, iclass 25, count 2 2006.201.10:36:25.78#ibcon#end of sib2, iclass 25, count 2 2006.201.10:36:25.78#ibcon#*after write, iclass 25, count 2 2006.201.10:36:25.78#ibcon#*before return 0, iclass 25, count 2 2006.201.10:36:25.78#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:25.78#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:36:25.78#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.10:36:25.78#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:25.78#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:25.90#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:25.90#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:25.90#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:36:25.90#ibcon#first serial, iclass 25, count 0 2006.201.10:36:25.90#ibcon#enter sib2, iclass 25, count 0 2006.201.10:36:25.90#ibcon#flushed, iclass 25, count 0 2006.201.10:36:25.90#ibcon#about to write, iclass 25, count 0 2006.201.10:36:25.90#ibcon#wrote, iclass 25, count 0 2006.201.10:36:25.90#ibcon#about to read 3, iclass 25, count 0 2006.201.10:36:25.92#ibcon#read 3, iclass 25, count 0 2006.201.10:36:25.92#ibcon#about to read 4, iclass 25, count 0 2006.201.10:36:25.92#ibcon#read 4, iclass 25, count 0 2006.201.10:36:25.92#ibcon#about to read 5, iclass 25, count 0 2006.201.10:36:25.92#ibcon#read 5, iclass 25, count 0 2006.201.10:36:25.92#ibcon#about to read 6, iclass 25, count 0 2006.201.10:36:25.92#ibcon#read 6, iclass 25, count 0 2006.201.10:36:25.92#ibcon#end of sib2, iclass 25, count 0 2006.201.10:36:25.92#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:36:25.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:36:25.92#ibcon#[27=USB\r\n] 2006.201.10:36:25.92#ibcon#*before write, iclass 25, count 0 2006.201.10:36:25.92#ibcon#enter sib2, iclass 25, count 0 2006.201.10:36:25.92#ibcon#flushed, iclass 25, count 0 2006.201.10:36:25.92#ibcon#about to write, iclass 25, count 0 2006.201.10:36:25.92#ibcon#wrote, iclass 25, count 0 2006.201.10:36:25.92#ibcon#about to read 3, iclass 25, count 0 2006.201.10:36:25.95#ibcon#read 3, iclass 25, count 0 2006.201.10:36:25.95#ibcon#about to read 4, iclass 25, count 0 2006.201.10:36:25.95#ibcon#read 4, iclass 25, count 0 2006.201.10:36:25.95#ibcon#about to read 5, iclass 25, count 0 2006.201.10:36:25.95#ibcon#read 5, iclass 25, count 0 2006.201.10:36:25.95#ibcon#about to read 6, iclass 25, count 0 2006.201.10:36:25.95#ibcon#read 6, iclass 25, count 0 2006.201.10:36:25.95#ibcon#end of sib2, iclass 25, count 0 2006.201.10:36:25.95#ibcon#*after write, iclass 25, count 0 2006.201.10:36:25.95#ibcon#*before return 0, iclass 25, count 0 2006.201.10:36:25.95#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:25.95#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:36:25.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:36:25.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:36:25.95$vck44/vblo=8,744.99 2006.201.10:36:25.95#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.10:36:25.95#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.10:36:25.95#ibcon#ireg 17 cls_cnt 0 2006.201.10:36:25.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:25.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:25.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:25.95#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:36:25.95#ibcon#first serial, iclass 27, count 0 2006.201.10:36:25.95#ibcon#enter sib2, iclass 27, count 0 2006.201.10:36:25.95#ibcon#flushed, iclass 27, count 0 2006.201.10:36:25.95#ibcon#about to write, iclass 27, count 0 2006.201.10:36:25.95#ibcon#wrote, iclass 27, count 0 2006.201.10:36:25.95#ibcon#about to read 3, iclass 27, count 0 2006.201.10:36:25.97#ibcon#read 3, iclass 27, count 0 2006.201.10:36:25.97#ibcon#about to read 4, iclass 27, count 0 2006.201.10:36:25.97#ibcon#read 4, iclass 27, count 0 2006.201.10:36:25.97#ibcon#about to read 5, iclass 27, count 0 2006.201.10:36:25.97#ibcon#read 5, iclass 27, count 0 2006.201.10:36:25.97#ibcon#about to read 6, iclass 27, count 0 2006.201.10:36:25.97#ibcon#read 6, iclass 27, count 0 2006.201.10:36:25.97#ibcon#end of sib2, iclass 27, count 0 2006.201.10:36:25.97#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:36:25.97#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:36:25.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:36:25.97#ibcon#*before write, iclass 27, count 0 2006.201.10:36:25.97#ibcon#enter sib2, iclass 27, count 0 2006.201.10:36:25.97#ibcon#flushed, iclass 27, count 0 2006.201.10:36:25.97#ibcon#about to write, iclass 27, count 0 2006.201.10:36:25.97#ibcon#wrote, iclass 27, count 0 2006.201.10:36:25.97#ibcon#about to read 3, iclass 27, count 0 2006.201.10:36:26.01#ibcon#read 3, iclass 27, count 0 2006.201.10:36:26.01#ibcon#about to read 4, iclass 27, count 0 2006.201.10:36:26.01#ibcon#read 4, iclass 27, count 0 2006.201.10:36:26.01#ibcon#about to read 5, iclass 27, count 0 2006.201.10:36:26.01#ibcon#read 5, iclass 27, count 0 2006.201.10:36:26.01#ibcon#about to read 6, iclass 27, count 0 2006.201.10:36:26.01#ibcon#read 6, iclass 27, count 0 2006.201.10:36:26.01#ibcon#end of sib2, iclass 27, count 0 2006.201.10:36:26.01#ibcon#*after write, iclass 27, count 0 2006.201.10:36:26.01#ibcon#*before return 0, iclass 27, count 0 2006.201.10:36:26.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:26.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:36:26.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:36:26.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:36:26.01$vck44/vb=8,4 2006.201.10:36:26.01#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.10:36:26.01#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.10:36:26.01#ibcon#ireg 11 cls_cnt 2 2006.201.10:36:26.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:26.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:26.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:26.07#ibcon#enter wrdev, iclass 29, count 2 2006.201.10:36:26.07#ibcon#first serial, iclass 29, count 2 2006.201.10:36:26.07#ibcon#enter sib2, iclass 29, count 2 2006.201.10:36:26.07#ibcon#flushed, iclass 29, count 2 2006.201.10:36:26.07#ibcon#about to write, iclass 29, count 2 2006.201.10:36:26.07#ibcon#wrote, iclass 29, count 2 2006.201.10:36:26.07#ibcon#about to read 3, iclass 29, count 2 2006.201.10:36:26.09#ibcon#read 3, iclass 29, count 2 2006.201.10:36:26.09#ibcon#about to read 4, iclass 29, count 2 2006.201.10:36:26.09#ibcon#read 4, iclass 29, count 2 2006.201.10:36:26.09#ibcon#about to read 5, iclass 29, count 2 2006.201.10:36:26.09#ibcon#read 5, iclass 29, count 2 2006.201.10:36:26.09#ibcon#about to read 6, iclass 29, count 2 2006.201.10:36:26.09#ibcon#read 6, iclass 29, count 2 2006.201.10:36:26.09#ibcon#end of sib2, iclass 29, count 2 2006.201.10:36:26.09#ibcon#*mode == 0, iclass 29, count 2 2006.201.10:36:26.09#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.10:36:26.09#ibcon#[27=AT08-04\r\n] 2006.201.10:36:26.09#ibcon#*before write, iclass 29, count 2 2006.201.10:36:26.09#ibcon#enter sib2, iclass 29, count 2 2006.201.10:36:26.09#ibcon#flushed, iclass 29, count 2 2006.201.10:36:26.09#ibcon#about to write, iclass 29, count 2 2006.201.10:36:26.09#ibcon#wrote, iclass 29, count 2 2006.201.10:36:26.09#ibcon#about to read 3, iclass 29, count 2 2006.201.10:36:26.12#ibcon#read 3, iclass 29, count 2 2006.201.10:36:26.12#ibcon#about to read 4, iclass 29, count 2 2006.201.10:36:26.12#ibcon#read 4, iclass 29, count 2 2006.201.10:36:26.12#ibcon#about to read 5, iclass 29, count 2 2006.201.10:36:26.12#ibcon#read 5, iclass 29, count 2 2006.201.10:36:26.12#ibcon#about to read 6, iclass 29, count 2 2006.201.10:36:26.12#ibcon#read 6, iclass 29, count 2 2006.201.10:36:26.12#ibcon#end of sib2, iclass 29, count 2 2006.201.10:36:26.12#ibcon#*after write, iclass 29, count 2 2006.201.10:36:26.12#ibcon#*before return 0, iclass 29, count 2 2006.201.10:36:26.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:26.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:36:26.12#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.10:36:26.12#ibcon#ireg 7 cls_cnt 0 2006.201.10:36:26.12#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:26.24#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:26.24#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:26.24#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:36:26.24#ibcon#first serial, iclass 29, count 0 2006.201.10:36:26.24#ibcon#enter sib2, iclass 29, count 0 2006.201.10:36:26.24#ibcon#flushed, iclass 29, count 0 2006.201.10:36:26.24#ibcon#about to write, iclass 29, count 0 2006.201.10:36:26.24#ibcon#wrote, iclass 29, count 0 2006.201.10:36:26.24#ibcon#about to read 3, iclass 29, count 0 2006.201.10:36:26.26#ibcon#read 3, iclass 29, count 0 2006.201.10:36:26.26#ibcon#about to read 4, iclass 29, count 0 2006.201.10:36:26.26#ibcon#read 4, iclass 29, count 0 2006.201.10:36:26.26#ibcon#about to read 5, iclass 29, count 0 2006.201.10:36:26.26#ibcon#read 5, iclass 29, count 0 2006.201.10:36:26.26#ibcon#about to read 6, iclass 29, count 0 2006.201.10:36:26.26#ibcon#read 6, iclass 29, count 0 2006.201.10:36:26.26#ibcon#end of sib2, iclass 29, count 0 2006.201.10:36:26.26#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:36:26.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:36:26.26#ibcon#[27=USB\r\n] 2006.201.10:36:26.26#ibcon#*before write, iclass 29, count 0 2006.201.10:36:26.26#ibcon#enter sib2, iclass 29, count 0 2006.201.10:36:26.26#ibcon#flushed, iclass 29, count 0 2006.201.10:36:26.26#ibcon#about to write, iclass 29, count 0 2006.201.10:36:26.26#ibcon#wrote, iclass 29, count 0 2006.201.10:36:26.26#ibcon#about to read 3, iclass 29, count 0 2006.201.10:36:26.29#ibcon#read 3, iclass 29, count 0 2006.201.10:36:26.29#ibcon#about to read 4, iclass 29, count 0 2006.201.10:36:26.29#ibcon#read 4, iclass 29, count 0 2006.201.10:36:26.29#ibcon#about to read 5, iclass 29, count 0 2006.201.10:36:26.29#ibcon#read 5, iclass 29, count 0 2006.201.10:36:26.29#ibcon#about to read 6, iclass 29, count 0 2006.201.10:36:26.29#ibcon#read 6, iclass 29, count 0 2006.201.10:36:26.29#ibcon#end of sib2, iclass 29, count 0 2006.201.10:36:26.29#ibcon#*after write, iclass 29, count 0 2006.201.10:36:26.29#ibcon#*before return 0, iclass 29, count 0 2006.201.10:36:26.29#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:26.29#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:36:26.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:36:26.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:36:26.29$vck44/vabw=wide 2006.201.10:36:26.29#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.10:36:26.29#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.10:36:26.29#ibcon#ireg 8 cls_cnt 0 2006.201.10:36:26.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:26.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:26.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:26.29#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:36:26.29#ibcon#first serial, iclass 31, count 0 2006.201.10:36:26.29#ibcon#enter sib2, iclass 31, count 0 2006.201.10:36:26.29#ibcon#flushed, iclass 31, count 0 2006.201.10:36:26.29#ibcon#about to write, iclass 31, count 0 2006.201.10:36:26.29#ibcon#wrote, iclass 31, count 0 2006.201.10:36:26.29#ibcon#about to read 3, iclass 31, count 0 2006.201.10:36:26.31#ibcon#read 3, iclass 31, count 0 2006.201.10:36:26.31#ibcon#about to read 4, iclass 31, count 0 2006.201.10:36:26.31#ibcon#read 4, iclass 31, count 0 2006.201.10:36:26.31#ibcon#about to read 5, iclass 31, count 0 2006.201.10:36:26.31#ibcon#read 5, iclass 31, count 0 2006.201.10:36:26.31#ibcon#about to read 6, iclass 31, count 0 2006.201.10:36:26.31#ibcon#read 6, iclass 31, count 0 2006.201.10:36:26.31#ibcon#end of sib2, iclass 31, count 0 2006.201.10:36:26.31#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:36:26.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:36:26.31#ibcon#[25=BW32\r\n] 2006.201.10:36:26.31#ibcon#*before write, iclass 31, count 0 2006.201.10:36:26.31#ibcon#enter sib2, iclass 31, count 0 2006.201.10:36:26.31#ibcon#flushed, iclass 31, count 0 2006.201.10:36:26.31#ibcon#about to write, iclass 31, count 0 2006.201.10:36:26.31#ibcon#wrote, iclass 31, count 0 2006.201.10:36:26.31#ibcon#about to read 3, iclass 31, count 0 2006.201.10:36:26.35#ibcon#read 3, iclass 31, count 0 2006.201.10:36:26.35#ibcon#about to read 4, iclass 31, count 0 2006.201.10:36:26.35#ibcon#read 4, iclass 31, count 0 2006.201.10:36:26.35#ibcon#about to read 5, iclass 31, count 0 2006.201.10:36:26.35#ibcon#read 5, iclass 31, count 0 2006.201.10:36:26.35#ibcon#about to read 6, iclass 31, count 0 2006.201.10:36:26.35#ibcon#read 6, iclass 31, count 0 2006.201.10:36:26.35#ibcon#end of sib2, iclass 31, count 0 2006.201.10:36:26.35#ibcon#*after write, iclass 31, count 0 2006.201.10:36:26.35#ibcon#*before return 0, iclass 31, count 0 2006.201.10:36:26.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:26.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:36:26.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:36:26.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:36:26.35$vck44/vbbw=wide 2006.201.10:36:26.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.10:36:26.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.10:36:26.35#ibcon#ireg 8 cls_cnt 0 2006.201.10:36:26.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:36:26.41#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:36:26.41#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:36:26.41#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:36:26.41#ibcon#first serial, iclass 33, count 0 2006.201.10:36:26.41#ibcon#enter sib2, iclass 33, count 0 2006.201.10:36:26.41#ibcon#flushed, iclass 33, count 0 2006.201.10:36:26.41#ibcon#about to write, iclass 33, count 0 2006.201.10:36:26.41#ibcon#wrote, iclass 33, count 0 2006.201.10:36:26.41#ibcon#about to read 3, iclass 33, count 0 2006.201.10:36:26.43#ibcon#read 3, iclass 33, count 0 2006.201.10:36:26.43#ibcon#about to read 4, iclass 33, count 0 2006.201.10:36:26.43#ibcon#read 4, iclass 33, count 0 2006.201.10:36:26.43#ibcon#about to read 5, iclass 33, count 0 2006.201.10:36:26.43#ibcon#read 5, iclass 33, count 0 2006.201.10:36:26.43#ibcon#about to read 6, iclass 33, count 0 2006.201.10:36:26.43#ibcon#read 6, iclass 33, count 0 2006.201.10:36:26.43#ibcon#end of sib2, iclass 33, count 0 2006.201.10:36:26.43#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:36:26.43#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:36:26.43#ibcon#[27=BW32\r\n] 2006.201.10:36:26.43#ibcon#*before write, iclass 33, count 0 2006.201.10:36:26.43#ibcon#enter sib2, iclass 33, count 0 2006.201.10:36:26.43#ibcon#flushed, iclass 33, count 0 2006.201.10:36:26.43#ibcon#about to write, iclass 33, count 0 2006.201.10:36:26.43#ibcon#wrote, iclass 33, count 0 2006.201.10:36:26.43#ibcon#about to read 3, iclass 33, count 0 2006.201.10:36:26.46#ibcon#read 3, iclass 33, count 0 2006.201.10:36:26.46#ibcon#about to read 4, iclass 33, count 0 2006.201.10:36:26.46#ibcon#read 4, iclass 33, count 0 2006.201.10:36:26.46#ibcon#about to read 5, iclass 33, count 0 2006.201.10:36:26.46#ibcon#read 5, iclass 33, count 0 2006.201.10:36:26.46#ibcon#about to read 6, iclass 33, count 0 2006.201.10:36:26.46#ibcon#read 6, iclass 33, count 0 2006.201.10:36:26.46#ibcon#end of sib2, iclass 33, count 0 2006.201.10:36:26.46#ibcon#*after write, iclass 33, count 0 2006.201.10:36:26.46#ibcon#*before return 0, iclass 33, count 0 2006.201.10:36:26.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:36:26.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:36:26.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:36:26.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:36:26.46$setupk4/ifdk4 2006.201.10:36:26.46$ifdk4/lo= 2006.201.10:36:26.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:36:26.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:36:26.46$ifdk4/patch= 2006.201.10:36:26.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:36:26.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:36:26.46$setupk4/!*+20s 2006.201.10:36:34.80#abcon#<5=/05 2.1 3.8 21.66 971003.7\r\n> 2006.201.10:36:34.82#abcon#{5=INTERFACE CLEAR} 2006.201.10:36:34.89#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:36:38.14#trakl#Source acquired 2006.201.10:36:38.14#flagr#flagr/antenna,acquired 2006.201.10:36:40.92$setupk4/"tpicd 2006.201.10:36:40.92$setupk4/echo=off 2006.201.10:36:40.92$setupk4/xlog=off 2006.201.10:36:40.92:!2006.201.10:37:15 2006.201.10:37:15.00:preob 2006.201.10:37:15.14/onsource/TRACKING 2006.201.10:37:15.14:!2006.201.10:37:25 2006.201.10:37:25.00:"tape 2006.201.10:37:25.00:"st=record 2006.201.10:37:25.00:data_valid=on 2006.201.10:37:25.00:midob 2006.201.10:37:26.14/onsource/TRACKING 2006.201.10:37:26.14/wx/21.65,1003.7,97 2006.201.10:37:26.25/cable/+6.4692E-03 2006.201.10:37:27.34/va/01,08,usb,yes,28,30 2006.201.10:37:27.34/va/02,07,usb,yes,30,31 2006.201.10:37:27.34/va/03,08,usb,yes,27,28 2006.201.10:37:27.34/va/04,07,usb,yes,31,33 2006.201.10:37:27.34/va/05,04,usb,yes,27,28 2006.201.10:37:27.34/va/06,05,usb,yes,28,27 2006.201.10:37:27.34/va/07,05,usb,yes,27,28 2006.201.10:37:27.34/va/08,04,usb,yes,26,32 2006.201.10:37:27.57/valo/01,524.99,yes,locked 2006.201.10:37:27.57/valo/02,534.99,yes,locked 2006.201.10:37:27.57/valo/03,564.99,yes,locked 2006.201.10:37:27.57/valo/04,624.99,yes,locked 2006.201.10:37:27.57/valo/05,734.99,yes,locked 2006.201.10:37:27.57/valo/06,814.99,yes,locked 2006.201.10:37:27.57/valo/07,864.99,yes,locked 2006.201.10:37:27.57/valo/08,884.99,yes,locked 2006.201.10:37:28.66/vb/01,04,usb,yes,29,27 2006.201.10:37:28.66/vb/02,05,usb,yes,27,27 2006.201.10:37:28.66/vb/03,04,usb,yes,28,31 2006.201.10:37:28.66/vb/04,05,usb,yes,28,27 2006.201.10:37:28.66/vb/05,04,usb,yes,25,27 2006.201.10:37:28.66/vb/06,04,usb,yes,29,26 2006.201.10:37:28.66/vb/07,04,usb,yes,29,29 2006.201.10:37:28.66/vb/08,04,usb,yes,27,30 2006.201.10:37:28.89/vblo/01,629.99,yes,locked 2006.201.10:37:28.89/vblo/02,634.99,yes,locked 2006.201.10:37:28.89/vblo/03,649.99,yes,locked 2006.201.10:37:28.89/vblo/04,679.99,yes,locked 2006.201.10:37:28.89/vblo/05,709.99,yes,locked 2006.201.10:37:28.89/vblo/06,719.99,yes,locked 2006.201.10:37:28.89/vblo/07,734.99,yes,locked 2006.201.10:37:28.89/vblo/08,744.99,yes,locked 2006.201.10:37:29.04/vabw/8 2006.201.10:37:29.19/vbbw/8 2006.201.10:37:29.28/xfe/off,on,14.7 2006.201.10:37:29.66/ifatt/23,28,28,28 2006.201.10:37:30.05/fmout-gps/S +4.56E-07 2006.201.10:37:30.12:!2006.201.10:41:05 2006.201.10:41:05.00:data_valid=off 2006.201.10:41:05.00:"et 2006.201.10:41:05.00:!+3s 2006.201.10:41:08.02:"tape 2006.201.10:41:08.02:postob 2006.201.10:41:08.15/cable/+6.4697E-03 2006.201.10:41:08.15/wx/21.62,1003.6,98 2006.201.10:41:08.21/fmout-gps/S +4.53E-07 2006.201.10:41:08.21:scan_name=201-1045,jd0607,110 2006.201.10:41:08.22:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.201.10:41:10.13#flagr#flagr/antenna,new-source 2006.201.10:41:10.13:checkk5 2006.201.10:41:10.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:41:10.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:41:11.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:41:11.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:41:11.98/chk_obsdata//k5ts1/T2011037??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.10:41:12.35/chk_obsdata//k5ts2/T2011037??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.10:41:12.71/chk_obsdata//k5ts3/T2011037??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.10:41:13.08/chk_obsdata//k5ts4/T2011037??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.10:41:13.77/k5log//k5ts1_log_newline 2006.201.10:41:14.46/k5log//k5ts2_log_newline 2006.201.10:41:15.14/k5log//k5ts3_log_newline 2006.201.10:41:15.83/k5log//k5ts4_log_newline 2006.201.10:41:15.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:41:15.85:setupk4=1 2006.201.10:41:15.85$setupk4/echo=on 2006.201.10:41:15.86$setupk4/pcalon 2006.201.10:41:15.86$pcalon/"no phase cal control is implemented here 2006.201.10:41:15.86$setupk4/"tpicd=stop 2006.201.10:41:15.86$setupk4/"rec=synch_on 2006.201.10:41:15.86$setupk4/"rec_mode=128 2006.201.10:41:15.86$setupk4/!* 2006.201.10:41:15.86$setupk4/recpk4 2006.201.10:41:15.86$recpk4/recpatch= 2006.201.10:41:15.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:41:15.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:41:15.86$setupk4/vck44 2006.201.10:41:15.86$vck44/valo=1,524.99 2006.201.10:41:15.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.10:41:15.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.10:41:15.86#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:15.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:15.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:15.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:15.86#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:41:15.86#ibcon#first serial, iclass 37, count 0 2006.201.10:41:15.86#ibcon#enter sib2, iclass 37, count 0 2006.201.10:41:15.86#ibcon#flushed, iclass 37, count 0 2006.201.10:41:15.86#ibcon#about to write, iclass 37, count 0 2006.201.10:41:15.86#ibcon#wrote, iclass 37, count 0 2006.201.10:41:15.86#ibcon#about to read 3, iclass 37, count 0 2006.201.10:41:15.90#ibcon#read 3, iclass 37, count 0 2006.201.10:41:15.90#ibcon#about to read 4, iclass 37, count 0 2006.201.10:41:15.90#ibcon#read 4, iclass 37, count 0 2006.201.10:41:15.90#ibcon#about to read 5, iclass 37, count 0 2006.201.10:41:15.90#ibcon#read 5, iclass 37, count 0 2006.201.10:41:15.90#ibcon#about to read 6, iclass 37, count 0 2006.201.10:41:15.90#ibcon#read 6, iclass 37, count 0 2006.201.10:41:15.90#ibcon#end of sib2, iclass 37, count 0 2006.201.10:41:15.90#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:41:15.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:41:15.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:41:15.90#ibcon#*before write, iclass 37, count 0 2006.201.10:41:15.90#ibcon#enter sib2, iclass 37, count 0 2006.201.10:41:15.90#ibcon#flushed, iclass 37, count 0 2006.201.10:41:15.90#ibcon#about to write, iclass 37, count 0 2006.201.10:41:15.90#ibcon#wrote, iclass 37, count 0 2006.201.10:41:15.90#ibcon#about to read 3, iclass 37, count 0 2006.201.10:41:15.95#ibcon#read 3, iclass 37, count 0 2006.201.10:41:15.95#ibcon#about to read 4, iclass 37, count 0 2006.201.10:41:15.95#ibcon#read 4, iclass 37, count 0 2006.201.10:41:15.95#ibcon#about to read 5, iclass 37, count 0 2006.201.10:41:15.95#ibcon#read 5, iclass 37, count 0 2006.201.10:41:15.95#ibcon#about to read 6, iclass 37, count 0 2006.201.10:41:15.95#ibcon#read 6, iclass 37, count 0 2006.201.10:41:15.95#ibcon#end of sib2, iclass 37, count 0 2006.201.10:41:15.95#ibcon#*after write, iclass 37, count 0 2006.201.10:41:15.95#ibcon#*before return 0, iclass 37, count 0 2006.201.10:41:15.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:15.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:15.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:41:15.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:41:15.95$vck44/va=1,8 2006.201.10:41:15.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.10:41:15.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.10:41:15.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:15.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:15.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:15.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:15.95#ibcon#enter wrdev, iclass 39, count 2 2006.201.10:41:15.95#ibcon#first serial, iclass 39, count 2 2006.201.10:41:15.95#ibcon#enter sib2, iclass 39, count 2 2006.201.10:41:15.95#ibcon#flushed, iclass 39, count 2 2006.201.10:41:15.95#ibcon#about to write, iclass 39, count 2 2006.201.10:41:15.95#ibcon#wrote, iclass 39, count 2 2006.201.10:41:15.95#ibcon#about to read 3, iclass 39, count 2 2006.201.10:41:15.97#ibcon#read 3, iclass 39, count 2 2006.201.10:41:15.97#ibcon#about to read 4, iclass 39, count 2 2006.201.10:41:15.97#ibcon#read 4, iclass 39, count 2 2006.201.10:41:15.97#ibcon#about to read 5, iclass 39, count 2 2006.201.10:41:15.97#ibcon#read 5, iclass 39, count 2 2006.201.10:41:15.97#ibcon#about to read 6, iclass 39, count 2 2006.201.10:41:15.97#ibcon#read 6, iclass 39, count 2 2006.201.10:41:15.97#ibcon#end of sib2, iclass 39, count 2 2006.201.10:41:15.97#ibcon#*mode == 0, iclass 39, count 2 2006.201.10:41:15.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.10:41:15.97#ibcon#[25=AT01-08\r\n] 2006.201.10:41:15.97#ibcon#*before write, iclass 39, count 2 2006.201.10:41:15.97#ibcon#enter sib2, iclass 39, count 2 2006.201.10:41:15.97#ibcon#flushed, iclass 39, count 2 2006.201.10:41:15.97#ibcon#about to write, iclass 39, count 2 2006.201.10:41:15.97#ibcon#wrote, iclass 39, count 2 2006.201.10:41:15.97#ibcon#about to read 3, iclass 39, count 2 2006.201.10:41:16.01#ibcon#read 3, iclass 39, count 2 2006.201.10:41:16.01#ibcon#about to read 4, iclass 39, count 2 2006.201.10:41:16.01#ibcon#read 4, iclass 39, count 2 2006.201.10:41:16.01#ibcon#about to read 5, iclass 39, count 2 2006.201.10:41:16.01#ibcon#read 5, iclass 39, count 2 2006.201.10:41:16.01#ibcon#about to read 6, iclass 39, count 2 2006.201.10:41:16.01#ibcon#read 6, iclass 39, count 2 2006.201.10:41:16.01#ibcon#end of sib2, iclass 39, count 2 2006.201.10:41:16.01#ibcon#*after write, iclass 39, count 2 2006.201.10:41:16.01#ibcon#*before return 0, iclass 39, count 2 2006.201.10:41:16.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:16.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:16.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.10:41:16.01#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:16.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:16.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:16.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:16.13#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:41:16.13#ibcon#first serial, iclass 39, count 0 2006.201.10:41:16.13#ibcon#enter sib2, iclass 39, count 0 2006.201.10:41:16.13#ibcon#flushed, iclass 39, count 0 2006.201.10:41:16.13#ibcon#about to write, iclass 39, count 0 2006.201.10:41:16.13#ibcon#wrote, iclass 39, count 0 2006.201.10:41:16.13#ibcon#about to read 3, iclass 39, count 0 2006.201.10:41:16.15#ibcon#read 3, iclass 39, count 0 2006.201.10:41:16.15#ibcon#about to read 4, iclass 39, count 0 2006.201.10:41:16.15#ibcon#read 4, iclass 39, count 0 2006.201.10:41:16.15#ibcon#about to read 5, iclass 39, count 0 2006.201.10:41:16.15#ibcon#read 5, iclass 39, count 0 2006.201.10:41:16.15#ibcon#about to read 6, iclass 39, count 0 2006.201.10:41:16.15#ibcon#read 6, iclass 39, count 0 2006.201.10:41:16.15#ibcon#end of sib2, iclass 39, count 0 2006.201.10:41:16.15#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:41:16.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:41:16.15#ibcon#[25=USB\r\n] 2006.201.10:41:16.15#ibcon#*before write, iclass 39, count 0 2006.201.10:41:16.15#ibcon#enter sib2, iclass 39, count 0 2006.201.10:41:16.15#ibcon#flushed, iclass 39, count 0 2006.201.10:41:16.15#ibcon#about to write, iclass 39, count 0 2006.201.10:41:16.15#ibcon#wrote, iclass 39, count 0 2006.201.10:41:16.15#ibcon#about to read 3, iclass 39, count 0 2006.201.10:41:16.18#ibcon#read 3, iclass 39, count 0 2006.201.10:41:16.18#ibcon#about to read 4, iclass 39, count 0 2006.201.10:41:16.18#ibcon#read 4, iclass 39, count 0 2006.201.10:41:16.18#ibcon#about to read 5, iclass 39, count 0 2006.201.10:41:16.18#ibcon#read 5, iclass 39, count 0 2006.201.10:41:16.18#ibcon#about to read 6, iclass 39, count 0 2006.201.10:41:16.18#ibcon#read 6, iclass 39, count 0 2006.201.10:41:16.18#ibcon#end of sib2, iclass 39, count 0 2006.201.10:41:16.18#ibcon#*after write, iclass 39, count 0 2006.201.10:41:16.18#ibcon#*before return 0, iclass 39, count 0 2006.201.10:41:16.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:16.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:16.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:41:16.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:41:16.18$vck44/valo=2,534.99 2006.201.10:41:16.18#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.10:41:16.18#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.10:41:16.18#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:16.18#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:16.18#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:16.18#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:16.18#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:41:16.18#ibcon#first serial, iclass 2, count 0 2006.201.10:41:16.18#ibcon#enter sib2, iclass 2, count 0 2006.201.10:41:16.18#ibcon#flushed, iclass 2, count 0 2006.201.10:41:16.18#ibcon#about to write, iclass 2, count 0 2006.201.10:41:16.18#ibcon#wrote, iclass 2, count 0 2006.201.10:41:16.18#ibcon#about to read 3, iclass 2, count 0 2006.201.10:41:16.20#ibcon#read 3, iclass 2, count 0 2006.201.10:41:16.20#ibcon#about to read 4, iclass 2, count 0 2006.201.10:41:16.20#ibcon#read 4, iclass 2, count 0 2006.201.10:41:16.20#ibcon#about to read 5, iclass 2, count 0 2006.201.10:41:16.20#ibcon#read 5, iclass 2, count 0 2006.201.10:41:16.20#ibcon#about to read 6, iclass 2, count 0 2006.201.10:41:16.20#ibcon#read 6, iclass 2, count 0 2006.201.10:41:16.20#ibcon#end of sib2, iclass 2, count 0 2006.201.10:41:16.20#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:41:16.20#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:41:16.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:41:16.20#ibcon#*before write, iclass 2, count 0 2006.201.10:41:16.20#ibcon#enter sib2, iclass 2, count 0 2006.201.10:41:16.20#ibcon#flushed, iclass 2, count 0 2006.201.10:41:16.20#ibcon#about to write, iclass 2, count 0 2006.201.10:41:16.20#ibcon#wrote, iclass 2, count 0 2006.201.10:41:16.20#ibcon#about to read 3, iclass 2, count 0 2006.201.10:41:16.25#ibcon#read 3, iclass 2, count 0 2006.201.10:41:16.25#ibcon#about to read 4, iclass 2, count 0 2006.201.10:41:16.25#ibcon#read 4, iclass 2, count 0 2006.201.10:41:16.25#ibcon#about to read 5, iclass 2, count 0 2006.201.10:41:16.25#ibcon#read 5, iclass 2, count 0 2006.201.10:41:16.25#ibcon#about to read 6, iclass 2, count 0 2006.201.10:41:16.25#ibcon#read 6, iclass 2, count 0 2006.201.10:41:16.25#ibcon#end of sib2, iclass 2, count 0 2006.201.10:41:16.25#ibcon#*after write, iclass 2, count 0 2006.201.10:41:16.25#ibcon#*before return 0, iclass 2, count 0 2006.201.10:41:16.25#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:16.25#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:16.25#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:41:16.25#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:41:16.25$vck44/va=2,7 2006.201.10:41:16.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.10:41:16.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.10:41:16.25#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:16.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:16.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:16.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:16.30#ibcon#enter wrdev, iclass 5, count 2 2006.201.10:41:16.30#ibcon#first serial, iclass 5, count 2 2006.201.10:41:16.30#ibcon#enter sib2, iclass 5, count 2 2006.201.10:41:16.30#ibcon#flushed, iclass 5, count 2 2006.201.10:41:16.30#ibcon#about to write, iclass 5, count 2 2006.201.10:41:16.30#ibcon#wrote, iclass 5, count 2 2006.201.10:41:16.30#ibcon#about to read 3, iclass 5, count 2 2006.201.10:41:16.32#ibcon#read 3, iclass 5, count 2 2006.201.10:41:16.32#ibcon#about to read 4, iclass 5, count 2 2006.201.10:41:16.32#ibcon#read 4, iclass 5, count 2 2006.201.10:41:16.32#ibcon#about to read 5, iclass 5, count 2 2006.201.10:41:16.32#ibcon#read 5, iclass 5, count 2 2006.201.10:41:16.32#ibcon#about to read 6, iclass 5, count 2 2006.201.10:41:16.32#ibcon#read 6, iclass 5, count 2 2006.201.10:41:16.32#ibcon#end of sib2, iclass 5, count 2 2006.201.10:41:16.32#ibcon#*mode == 0, iclass 5, count 2 2006.201.10:41:16.32#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.10:41:16.32#ibcon#[25=AT02-07\r\n] 2006.201.10:41:16.32#ibcon#*before write, iclass 5, count 2 2006.201.10:41:16.32#ibcon#enter sib2, iclass 5, count 2 2006.201.10:41:16.32#ibcon#flushed, iclass 5, count 2 2006.201.10:41:16.32#ibcon#about to write, iclass 5, count 2 2006.201.10:41:16.32#ibcon#wrote, iclass 5, count 2 2006.201.10:41:16.32#ibcon#about to read 3, iclass 5, count 2 2006.201.10:41:16.35#ibcon#read 3, iclass 5, count 2 2006.201.10:41:16.35#ibcon#about to read 4, iclass 5, count 2 2006.201.10:41:16.35#ibcon#read 4, iclass 5, count 2 2006.201.10:41:16.35#ibcon#about to read 5, iclass 5, count 2 2006.201.10:41:16.35#ibcon#read 5, iclass 5, count 2 2006.201.10:41:16.35#ibcon#about to read 6, iclass 5, count 2 2006.201.10:41:16.35#ibcon#read 6, iclass 5, count 2 2006.201.10:41:16.35#ibcon#end of sib2, iclass 5, count 2 2006.201.10:41:16.35#ibcon#*after write, iclass 5, count 2 2006.201.10:41:16.35#ibcon#*before return 0, iclass 5, count 2 2006.201.10:41:16.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:16.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:16.35#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.10:41:16.35#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:16.35#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:16.47#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:16.47#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:16.47#ibcon#enter wrdev, iclass 5, count 0 2006.201.10:41:16.47#ibcon#first serial, iclass 5, count 0 2006.201.10:41:16.47#ibcon#enter sib2, iclass 5, count 0 2006.201.10:41:16.47#ibcon#flushed, iclass 5, count 0 2006.201.10:41:16.47#ibcon#about to write, iclass 5, count 0 2006.201.10:41:16.47#ibcon#wrote, iclass 5, count 0 2006.201.10:41:16.47#ibcon#about to read 3, iclass 5, count 0 2006.201.10:41:16.49#ibcon#read 3, iclass 5, count 0 2006.201.10:41:16.49#ibcon#about to read 4, iclass 5, count 0 2006.201.10:41:16.49#ibcon#read 4, iclass 5, count 0 2006.201.10:41:16.49#ibcon#about to read 5, iclass 5, count 0 2006.201.10:41:16.49#ibcon#read 5, iclass 5, count 0 2006.201.10:41:16.49#ibcon#about to read 6, iclass 5, count 0 2006.201.10:41:16.49#ibcon#read 6, iclass 5, count 0 2006.201.10:41:16.49#ibcon#end of sib2, iclass 5, count 0 2006.201.10:41:16.49#ibcon#*mode == 0, iclass 5, count 0 2006.201.10:41:16.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.10:41:16.49#ibcon#[25=USB\r\n] 2006.201.10:41:16.49#ibcon#*before write, iclass 5, count 0 2006.201.10:41:16.49#ibcon#enter sib2, iclass 5, count 0 2006.201.10:41:16.49#ibcon#flushed, iclass 5, count 0 2006.201.10:41:16.49#ibcon#about to write, iclass 5, count 0 2006.201.10:41:16.49#ibcon#wrote, iclass 5, count 0 2006.201.10:41:16.49#ibcon#about to read 3, iclass 5, count 0 2006.201.10:41:16.52#ibcon#read 3, iclass 5, count 0 2006.201.10:41:16.52#ibcon#about to read 4, iclass 5, count 0 2006.201.10:41:16.52#ibcon#read 4, iclass 5, count 0 2006.201.10:41:16.52#ibcon#about to read 5, iclass 5, count 0 2006.201.10:41:16.52#ibcon#read 5, iclass 5, count 0 2006.201.10:41:16.52#ibcon#about to read 6, iclass 5, count 0 2006.201.10:41:16.52#ibcon#read 6, iclass 5, count 0 2006.201.10:41:16.52#ibcon#end of sib2, iclass 5, count 0 2006.201.10:41:16.52#ibcon#*after write, iclass 5, count 0 2006.201.10:41:16.52#ibcon#*before return 0, iclass 5, count 0 2006.201.10:41:16.52#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:16.52#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:16.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.10:41:16.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.10:41:16.52$vck44/valo=3,564.99 2006.201.10:41:16.52#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.10:41:16.52#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.10:41:16.52#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:16.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:16.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:16.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:16.52#ibcon#enter wrdev, iclass 7, count 0 2006.201.10:41:16.52#ibcon#first serial, iclass 7, count 0 2006.201.10:41:16.52#ibcon#enter sib2, iclass 7, count 0 2006.201.10:41:16.52#ibcon#flushed, iclass 7, count 0 2006.201.10:41:16.52#ibcon#about to write, iclass 7, count 0 2006.201.10:41:16.52#ibcon#wrote, iclass 7, count 0 2006.201.10:41:16.52#ibcon#about to read 3, iclass 7, count 0 2006.201.10:41:16.54#ibcon#read 3, iclass 7, count 0 2006.201.10:41:16.54#ibcon#about to read 4, iclass 7, count 0 2006.201.10:41:16.54#ibcon#read 4, iclass 7, count 0 2006.201.10:41:16.54#ibcon#about to read 5, iclass 7, count 0 2006.201.10:41:16.54#ibcon#read 5, iclass 7, count 0 2006.201.10:41:16.54#ibcon#about to read 6, iclass 7, count 0 2006.201.10:41:16.54#ibcon#read 6, iclass 7, count 0 2006.201.10:41:16.54#ibcon#end of sib2, iclass 7, count 0 2006.201.10:41:16.54#ibcon#*mode == 0, iclass 7, count 0 2006.201.10:41:16.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.10:41:16.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:41:16.54#ibcon#*before write, iclass 7, count 0 2006.201.10:41:16.54#ibcon#enter sib2, iclass 7, count 0 2006.201.10:41:16.54#ibcon#flushed, iclass 7, count 0 2006.201.10:41:16.54#ibcon#about to write, iclass 7, count 0 2006.201.10:41:16.54#ibcon#wrote, iclass 7, count 0 2006.201.10:41:16.54#ibcon#about to read 3, iclass 7, count 0 2006.201.10:41:16.59#ibcon#read 3, iclass 7, count 0 2006.201.10:41:16.59#ibcon#about to read 4, iclass 7, count 0 2006.201.10:41:16.59#ibcon#read 4, iclass 7, count 0 2006.201.10:41:16.59#ibcon#about to read 5, iclass 7, count 0 2006.201.10:41:16.59#ibcon#read 5, iclass 7, count 0 2006.201.10:41:16.59#ibcon#about to read 6, iclass 7, count 0 2006.201.10:41:16.59#ibcon#read 6, iclass 7, count 0 2006.201.10:41:16.59#ibcon#end of sib2, iclass 7, count 0 2006.201.10:41:16.59#ibcon#*after write, iclass 7, count 0 2006.201.10:41:16.59#ibcon#*before return 0, iclass 7, count 0 2006.201.10:41:16.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:16.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:16.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.10:41:16.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.10:41:16.59$vck44/va=3,8 2006.201.10:41:16.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.10:41:16.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.10:41:16.59#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:16.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:16.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:16.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:16.64#ibcon#enter wrdev, iclass 11, count 2 2006.201.10:41:16.64#ibcon#first serial, iclass 11, count 2 2006.201.10:41:16.64#ibcon#enter sib2, iclass 11, count 2 2006.201.10:41:16.64#ibcon#flushed, iclass 11, count 2 2006.201.10:41:16.64#ibcon#about to write, iclass 11, count 2 2006.201.10:41:16.64#ibcon#wrote, iclass 11, count 2 2006.201.10:41:16.64#ibcon#about to read 3, iclass 11, count 2 2006.201.10:41:16.66#ibcon#read 3, iclass 11, count 2 2006.201.10:41:16.66#ibcon#about to read 4, iclass 11, count 2 2006.201.10:41:16.66#ibcon#read 4, iclass 11, count 2 2006.201.10:41:16.66#ibcon#about to read 5, iclass 11, count 2 2006.201.10:41:16.66#ibcon#read 5, iclass 11, count 2 2006.201.10:41:16.66#ibcon#about to read 6, iclass 11, count 2 2006.201.10:41:16.66#ibcon#read 6, iclass 11, count 2 2006.201.10:41:16.66#ibcon#end of sib2, iclass 11, count 2 2006.201.10:41:16.66#ibcon#*mode == 0, iclass 11, count 2 2006.201.10:41:16.66#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.10:41:16.66#ibcon#[25=AT03-08\r\n] 2006.201.10:41:16.66#ibcon#*before write, iclass 11, count 2 2006.201.10:41:16.66#ibcon#enter sib2, iclass 11, count 2 2006.201.10:41:16.66#ibcon#flushed, iclass 11, count 2 2006.201.10:41:16.66#ibcon#about to write, iclass 11, count 2 2006.201.10:41:16.66#ibcon#wrote, iclass 11, count 2 2006.201.10:41:16.66#ibcon#about to read 3, iclass 11, count 2 2006.201.10:41:16.69#ibcon#read 3, iclass 11, count 2 2006.201.10:41:16.69#ibcon#about to read 4, iclass 11, count 2 2006.201.10:41:16.69#ibcon#read 4, iclass 11, count 2 2006.201.10:41:16.69#ibcon#about to read 5, iclass 11, count 2 2006.201.10:41:16.69#ibcon#read 5, iclass 11, count 2 2006.201.10:41:16.69#ibcon#about to read 6, iclass 11, count 2 2006.201.10:41:16.69#ibcon#read 6, iclass 11, count 2 2006.201.10:41:16.69#ibcon#end of sib2, iclass 11, count 2 2006.201.10:41:16.69#ibcon#*after write, iclass 11, count 2 2006.201.10:41:16.69#ibcon#*before return 0, iclass 11, count 2 2006.201.10:41:16.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:16.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:16.69#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.10:41:16.69#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:16.69#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:16.81#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:16.81#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:16.81#ibcon#enter wrdev, iclass 11, count 0 2006.201.10:41:16.81#ibcon#first serial, iclass 11, count 0 2006.201.10:41:16.81#ibcon#enter sib2, iclass 11, count 0 2006.201.10:41:16.81#ibcon#flushed, iclass 11, count 0 2006.201.10:41:16.81#ibcon#about to write, iclass 11, count 0 2006.201.10:41:16.81#ibcon#wrote, iclass 11, count 0 2006.201.10:41:16.81#ibcon#about to read 3, iclass 11, count 0 2006.201.10:41:16.83#ibcon#read 3, iclass 11, count 0 2006.201.10:41:16.83#ibcon#about to read 4, iclass 11, count 0 2006.201.10:41:16.83#ibcon#read 4, iclass 11, count 0 2006.201.10:41:16.83#ibcon#about to read 5, iclass 11, count 0 2006.201.10:41:16.83#ibcon#read 5, iclass 11, count 0 2006.201.10:41:16.83#ibcon#about to read 6, iclass 11, count 0 2006.201.10:41:16.83#ibcon#read 6, iclass 11, count 0 2006.201.10:41:16.83#ibcon#end of sib2, iclass 11, count 0 2006.201.10:41:16.83#ibcon#*mode == 0, iclass 11, count 0 2006.201.10:41:16.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.10:41:16.83#ibcon#[25=USB\r\n] 2006.201.10:41:16.83#ibcon#*before write, iclass 11, count 0 2006.201.10:41:16.83#ibcon#enter sib2, iclass 11, count 0 2006.201.10:41:16.83#ibcon#flushed, iclass 11, count 0 2006.201.10:41:16.83#ibcon#about to write, iclass 11, count 0 2006.201.10:41:16.83#ibcon#wrote, iclass 11, count 0 2006.201.10:41:16.83#ibcon#about to read 3, iclass 11, count 0 2006.201.10:41:16.86#ibcon#read 3, iclass 11, count 0 2006.201.10:41:16.86#ibcon#about to read 4, iclass 11, count 0 2006.201.10:41:16.86#ibcon#read 4, iclass 11, count 0 2006.201.10:41:16.86#ibcon#about to read 5, iclass 11, count 0 2006.201.10:41:16.86#ibcon#read 5, iclass 11, count 0 2006.201.10:41:16.86#ibcon#about to read 6, iclass 11, count 0 2006.201.10:41:16.86#ibcon#read 6, iclass 11, count 0 2006.201.10:41:16.86#ibcon#end of sib2, iclass 11, count 0 2006.201.10:41:16.86#ibcon#*after write, iclass 11, count 0 2006.201.10:41:16.86#ibcon#*before return 0, iclass 11, count 0 2006.201.10:41:16.86#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:16.86#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:16.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.10:41:16.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.10:41:16.86$vck44/valo=4,624.99 2006.201.10:41:16.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.10:41:16.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.10:41:16.86#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:16.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:16.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:16.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:16.86#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:41:16.86#ibcon#first serial, iclass 13, count 0 2006.201.10:41:16.86#ibcon#enter sib2, iclass 13, count 0 2006.201.10:41:16.86#ibcon#flushed, iclass 13, count 0 2006.201.10:41:16.86#ibcon#about to write, iclass 13, count 0 2006.201.10:41:16.86#ibcon#wrote, iclass 13, count 0 2006.201.10:41:16.86#ibcon#about to read 3, iclass 13, count 0 2006.201.10:41:16.88#ibcon#read 3, iclass 13, count 0 2006.201.10:41:16.88#ibcon#about to read 4, iclass 13, count 0 2006.201.10:41:16.88#ibcon#read 4, iclass 13, count 0 2006.201.10:41:16.88#ibcon#about to read 5, iclass 13, count 0 2006.201.10:41:16.88#ibcon#read 5, iclass 13, count 0 2006.201.10:41:16.88#ibcon#about to read 6, iclass 13, count 0 2006.201.10:41:16.88#ibcon#read 6, iclass 13, count 0 2006.201.10:41:16.88#ibcon#end of sib2, iclass 13, count 0 2006.201.10:41:16.88#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:41:16.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:41:16.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:41:16.88#ibcon#*before write, iclass 13, count 0 2006.201.10:41:16.88#ibcon#enter sib2, iclass 13, count 0 2006.201.10:41:16.88#ibcon#flushed, iclass 13, count 0 2006.201.10:41:16.88#ibcon#about to write, iclass 13, count 0 2006.201.10:41:16.88#ibcon#wrote, iclass 13, count 0 2006.201.10:41:16.88#ibcon#about to read 3, iclass 13, count 0 2006.201.10:41:16.93#ibcon#read 3, iclass 13, count 0 2006.201.10:41:16.93#ibcon#about to read 4, iclass 13, count 0 2006.201.10:41:16.93#ibcon#read 4, iclass 13, count 0 2006.201.10:41:16.93#ibcon#about to read 5, iclass 13, count 0 2006.201.10:41:16.93#ibcon#read 5, iclass 13, count 0 2006.201.10:41:16.93#ibcon#about to read 6, iclass 13, count 0 2006.201.10:41:16.93#ibcon#read 6, iclass 13, count 0 2006.201.10:41:16.93#ibcon#end of sib2, iclass 13, count 0 2006.201.10:41:16.93#ibcon#*after write, iclass 13, count 0 2006.201.10:41:16.93#ibcon#*before return 0, iclass 13, count 0 2006.201.10:41:16.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:16.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:16.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:41:16.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:41:16.93$vck44/va=4,7 2006.201.10:41:16.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.10:41:16.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.10:41:16.93#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:16.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:16.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:16.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:16.98#ibcon#enter wrdev, iclass 15, count 2 2006.201.10:41:16.98#ibcon#first serial, iclass 15, count 2 2006.201.10:41:16.98#ibcon#enter sib2, iclass 15, count 2 2006.201.10:41:16.98#ibcon#flushed, iclass 15, count 2 2006.201.10:41:16.98#ibcon#about to write, iclass 15, count 2 2006.201.10:41:16.98#ibcon#wrote, iclass 15, count 2 2006.201.10:41:16.98#ibcon#about to read 3, iclass 15, count 2 2006.201.10:41:17.00#ibcon#read 3, iclass 15, count 2 2006.201.10:41:17.00#ibcon#about to read 4, iclass 15, count 2 2006.201.10:41:17.00#ibcon#read 4, iclass 15, count 2 2006.201.10:41:17.00#ibcon#about to read 5, iclass 15, count 2 2006.201.10:41:17.00#ibcon#read 5, iclass 15, count 2 2006.201.10:41:17.00#ibcon#about to read 6, iclass 15, count 2 2006.201.10:41:17.00#ibcon#read 6, iclass 15, count 2 2006.201.10:41:17.00#ibcon#end of sib2, iclass 15, count 2 2006.201.10:41:17.00#ibcon#*mode == 0, iclass 15, count 2 2006.201.10:41:17.00#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.10:41:17.00#ibcon#[25=AT04-07\r\n] 2006.201.10:41:17.00#ibcon#*before write, iclass 15, count 2 2006.201.10:41:17.00#ibcon#enter sib2, iclass 15, count 2 2006.201.10:41:17.00#ibcon#flushed, iclass 15, count 2 2006.201.10:41:17.00#ibcon#about to write, iclass 15, count 2 2006.201.10:41:17.00#ibcon#wrote, iclass 15, count 2 2006.201.10:41:17.00#ibcon#about to read 3, iclass 15, count 2 2006.201.10:41:17.03#ibcon#read 3, iclass 15, count 2 2006.201.10:41:17.03#ibcon#about to read 4, iclass 15, count 2 2006.201.10:41:17.03#ibcon#read 4, iclass 15, count 2 2006.201.10:41:17.03#ibcon#about to read 5, iclass 15, count 2 2006.201.10:41:17.03#ibcon#read 5, iclass 15, count 2 2006.201.10:41:17.03#ibcon#about to read 6, iclass 15, count 2 2006.201.10:41:17.03#ibcon#read 6, iclass 15, count 2 2006.201.10:41:17.03#ibcon#end of sib2, iclass 15, count 2 2006.201.10:41:17.03#ibcon#*after write, iclass 15, count 2 2006.201.10:41:17.03#ibcon#*before return 0, iclass 15, count 2 2006.201.10:41:17.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:17.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:17.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.10:41:17.03#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:17.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:17.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:17.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:17.15#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:41:17.15#ibcon#first serial, iclass 15, count 0 2006.201.10:41:17.15#ibcon#enter sib2, iclass 15, count 0 2006.201.10:41:17.15#ibcon#flushed, iclass 15, count 0 2006.201.10:41:17.15#ibcon#about to write, iclass 15, count 0 2006.201.10:41:17.15#ibcon#wrote, iclass 15, count 0 2006.201.10:41:17.15#ibcon#about to read 3, iclass 15, count 0 2006.201.10:41:17.17#ibcon#read 3, iclass 15, count 0 2006.201.10:41:17.17#ibcon#about to read 4, iclass 15, count 0 2006.201.10:41:17.17#ibcon#read 4, iclass 15, count 0 2006.201.10:41:17.17#ibcon#about to read 5, iclass 15, count 0 2006.201.10:41:17.17#ibcon#read 5, iclass 15, count 0 2006.201.10:41:17.17#ibcon#about to read 6, iclass 15, count 0 2006.201.10:41:17.17#ibcon#read 6, iclass 15, count 0 2006.201.10:41:17.17#ibcon#end of sib2, iclass 15, count 0 2006.201.10:41:17.17#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:41:17.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:41:17.17#ibcon#[25=USB\r\n] 2006.201.10:41:17.17#ibcon#*before write, iclass 15, count 0 2006.201.10:41:17.17#ibcon#enter sib2, iclass 15, count 0 2006.201.10:41:17.17#ibcon#flushed, iclass 15, count 0 2006.201.10:41:17.17#ibcon#about to write, iclass 15, count 0 2006.201.10:41:17.17#ibcon#wrote, iclass 15, count 0 2006.201.10:41:17.17#ibcon#about to read 3, iclass 15, count 0 2006.201.10:41:17.20#ibcon#read 3, iclass 15, count 0 2006.201.10:41:17.20#ibcon#about to read 4, iclass 15, count 0 2006.201.10:41:17.20#ibcon#read 4, iclass 15, count 0 2006.201.10:41:17.20#ibcon#about to read 5, iclass 15, count 0 2006.201.10:41:17.20#ibcon#read 5, iclass 15, count 0 2006.201.10:41:17.20#ibcon#about to read 6, iclass 15, count 0 2006.201.10:41:17.20#ibcon#read 6, iclass 15, count 0 2006.201.10:41:17.20#ibcon#end of sib2, iclass 15, count 0 2006.201.10:41:17.20#ibcon#*after write, iclass 15, count 0 2006.201.10:41:17.20#ibcon#*before return 0, iclass 15, count 0 2006.201.10:41:17.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:17.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:17.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:41:17.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:41:17.20$vck44/valo=5,734.99 2006.201.10:41:17.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.10:41:17.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.10:41:17.20#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:17.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:17.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:17.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:17.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:41:17.20#ibcon#first serial, iclass 17, count 0 2006.201.10:41:17.20#ibcon#enter sib2, iclass 17, count 0 2006.201.10:41:17.20#ibcon#flushed, iclass 17, count 0 2006.201.10:41:17.20#ibcon#about to write, iclass 17, count 0 2006.201.10:41:17.20#ibcon#wrote, iclass 17, count 0 2006.201.10:41:17.20#ibcon#about to read 3, iclass 17, count 0 2006.201.10:41:17.22#ibcon#read 3, iclass 17, count 0 2006.201.10:41:17.22#ibcon#about to read 4, iclass 17, count 0 2006.201.10:41:17.22#ibcon#read 4, iclass 17, count 0 2006.201.10:41:17.22#ibcon#about to read 5, iclass 17, count 0 2006.201.10:41:17.22#ibcon#read 5, iclass 17, count 0 2006.201.10:41:17.22#ibcon#about to read 6, iclass 17, count 0 2006.201.10:41:17.22#ibcon#read 6, iclass 17, count 0 2006.201.10:41:17.22#ibcon#end of sib2, iclass 17, count 0 2006.201.10:41:17.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:41:17.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:41:17.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:41:17.22#ibcon#*before write, iclass 17, count 0 2006.201.10:41:17.22#ibcon#enter sib2, iclass 17, count 0 2006.201.10:41:17.22#ibcon#flushed, iclass 17, count 0 2006.201.10:41:17.22#ibcon#about to write, iclass 17, count 0 2006.201.10:41:17.22#ibcon#wrote, iclass 17, count 0 2006.201.10:41:17.22#ibcon#about to read 3, iclass 17, count 0 2006.201.10:41:17.26#ibcon#read 3, iclass 17, count 0 2006.201.10:41:17.26#ibcon#about to read 4, iclass 17, count 0 2006.201.10:41:17.26#ibcon#read 4, iclass 17, count 0 2006.201.10:41:17.26#ibcon#about to read 5, iclass 17, count 0 2006.201.10:41:17.26#ibcon#read 5, iclass 17, count 0 2006.201.10:41:17.26#ibcon#about to read 6, iclass 17, count 0 2006.201.10:41:17.26#ibcon#read 6, iclass 17, count 0 2006.201.10:41:17.26#ibcon#end of sib2, iclass 17, count 0 2006.201.10:41:17.26#ibcon#*after write, iclass 17, count 0 2006.201.10:41:17.26#ibcon#*before return 0, iclass 17, count 0 2006.201.10:41:17.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:17.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:17.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:41:17.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:41:17.26$vck44/va=5,4 2006.201.10:41:17.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.10:41:17.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.10:41:17.26#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:17.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:17.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:17.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:17.32#ibcon#enter wrdev, iclass 19, count 2 2006.201.10:41:17.32#ibcon#first serial, iclass 19, count 2 2006.201.10:41:17.32#ibcon#enter sib2, iclass 19, count 2 2006.201.10:41:17.32#ibcon#flushed, iclass 19, count 2 2006.201.10:41:17.32#ibcon#about to write, iclass 19, count 2 2006.201.10:41:17.32#ibcon#wrote, iclass 19, count 2 2006.201.10:41:17.32#ibcon#about to read 3, iclass 19, count 2 2006.201.10:41:17.34#ibcon#read 3, iclass 19, count 2 2006.201.10:41:17.34#ibcon#about to read 4, iclass 19, count 2 2006.201.10:41:17.34#ibcon#read 4, iclass 19, count 2 2006.201.10:41:17.34#ibcon#about to read 5, iclass 19, count 2 2006.201.10:41:17.34#ibcon#read 5, iclass 19, count 2 2006.201.10:41:17.34#ibcon#about to read 6, iclass 19, count 2 2006.201.10:41:17.34#ibcon#read 6, iclass 19, count 2 2006.201.10:41:17.34#ibcon#end of sib2, iclass 19, count 2 2006.201.10:41:17.34#ibcon#*mode == 0, iclass 19, count 2 2006.201.10:41:17.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.10:41:17.34#ibcon#[25=AT05-04\r\n] 2006.201.10:41:17.34#ibcon#*before write, iclass 19, count 2 2006.201.10:41:17.34#ibcon#enter sib2, iclass 19, count 2 2006.201.10:41:17.34#ibcon#flushed, iclass 19, count 2 2006.201.10:41:17.34#ibcon#about to write, iclass 19, count 2 2006.201.10:41:17.34#ibcon#wrote, iclass 19, count 2 2006.201.10:41:17.34#ibcon#about to read 3, iclass 19, count 2 2006.201.10:41:17.37#ibcon#read 3, iclass 19, count 2 2006.201.10:41:17.37#ibcon#about to read 4, iclass 19, count 2 2006.201.10:41:17.37#ibcon#read 4, iclass 19, count 2 2006.201.10:41:17.37#ibcon#about to read 5, iclass 19, count 2 2006.201.10:41:17.37#ibcon#read 5, iclass 19, count 2 2006.201.10:41:17.37#ibcon#about to read 6, iclass 19, count 2 2006.201.10:41:17.37#ibcon#read 6, iclass 19, count 2 2006.201.10:41:17.37#ibcon#end of sib2, iclass 19, count 2 2006.201.10:41:17.37#ibcon#*after write, iclass 19, count 2 2006.201.10:41:17.37#ibcon#*before return 0, iclass 19, count 2 2006.201.10:41:17.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:17.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:17.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.10:41:17.37#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:17.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:17.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:17.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:17.49#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:41:17.49#ibcon#first serial, iclass 19, count 0 2006.201.10:41:17.49#ibcon#enter sib2, iclass 19, count 0 2006.201.10:41:17.49#ibcon#flushed, iclass 19, count 0 2006.201.10:41:17.49#ibcon#about to write, iclass 19, count 0 2006.201.10:41:17.49#ibcon#wrote, iclass 19, count 0 2006.201.10:41:17.49#ibcon#about to read 3, iclass 19, count 0 2006.201.10:41:17.51#ibcon#read 3, iclass 19, count 0 2006.201.10:41:17.51#ibcon#about to read 4, iclass 19, count 0 2006.201.10:41:17.51#ibcon#read 4, iclass 19, count 0 2006.201.10:41:17.51#ibcon#about to read 5, iclass 19, count 0 2006.201.10:41:17.51#ibcon#read 5, iclass 19, count 0 2006.201.10:41:17.51#ibcon#about to read 6, iclass 19, count 0 2006.201.10:41:17.51#ibcon#read 6, iclass 19, count 0 2006.201.10:41:17.51#ibcon#end of sib2, iclass 19, count 0 2006.201.10:41:17.51#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:41:17.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:41:17.51#ibcon#[25=USB\r\n] 2006.201.10:41:17.51#ibcon#*before write, iclass 19, count 0 2006.201.10:41:17.51#ibcon#enter sib2, iclass 19, count 0 2006.201.10:41:17.51#ibcon#flushed, iclass 19, count 0 2006.201.10:41:17.51#ibcon#about to write, iclass 19, count 0 2006.201.10:41:17.51#ibcon#wrote, iclass 19, count 0 2006.201.10:41:17.51#ibcon#about to read 3, iclass 19, count 0 2006.201.10:41:17.54#ibcon#read 3, iclass 19, count 0 2006.201.10:41:17.54#ibcon#about to read 4, iclass 19, count 0 2006.201.10:41:17.54#ibcon#read 4, iclass 19, count 0 2006.201.10:41:17.54#ibcon#about to read 5, iclass 19, count 0 2006.201.10:41:17.54#ibcon#read 5, iclass 19, count 0 2006.201.10:41:17.54#ibcon#about to read 6, iclass 19, count 0 2006.201.10:41:17.54#ibcon#read 6, iclass 19, count 0 2006.201.10:41:17.54#ibcon#end of sib2, iclass 19, count 0 2006.201.10:41:17.54#ibcon#*after write, iclass 19, count 0 2006.201.10:41:17.54#ibcon#*before return 0, iclass 19, count 0 2006.201.10:41:17.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:17.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:17.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:41:17.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:41:17.54$vck44/valo=6,814.99 2006.201.10:41:17.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.10:41:17.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.10:41:17.54#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:17.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:17.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:17.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:17.54#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:41:17.54#ibcon#first serial, iclass 21, count 0 2006.201.10:41:17.54#ibcon#enter sib2, iclass 21, count 0 2006.201.10:41:17.54#ibcon#flushed, iclass 21, count 0 2006.201.10:41:17.54#ibcon#about to write, iclass 21, count 0 2006.201.10:41:17.54#ibcon#wrote, iclass 21, count 0 2006.201.10:41:17.54#ibcon#about to read 3, iclass 21, count 0 2006.201.10:41:17.56#ibcon#read 3, iclass 21, count 0 2006.201.10:41:17.56#ibcon#about to read 4, iclass 21, count 0 2006.201.10:41:17.56#ibcon#read 4, iclass 21, count 0 2006.201.10:41:17.56#ibcon#about to read 5, iclass 21, count 0 2006.201.10:41:17.56#ibcon#read 5, iclass 21, count 0 2006.201.10:41:17.56#ibcon#about to read 6, iclass 21, count 0 2006.201.10:41:17.56#ibcon#read 6, iclass 21, count 0 2006.201.10:41:17.56#ibcon#end of sib2, iclass 21, count 0 2006.201.10:41:17.56#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:41:17.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:41:17.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:41:17.56#ibcon#*before write, iclass 21, count 0 2006.201.10:41:17.56#ibcon#enter sib2, iclass 21, count 0 2006.201.10:41:17.56#ibcon#flushed, iclass 21, count 0 2006.201.10:41:17.56#ibcon#about to write, iclass 21, count 0 2006.201.10:41:17.56#ibcon#wrote, iclass 21, count 0 2006.201.10:41:17.56#ibcon#about to read 3, iclass 21, count 0 2006.201.10:41:17.61#ibcon#read 3, iclass 21, count 0 2006.201.10:41:17.61#ibcon#about to read 4, iclass 21, count 0 2006.201.10:41:17.61#ibcon#read 4, iclass 21, count 0 2006.201.10:41:17.61#ibcon#about to read 5, iclass 21, count 0 2006.201.10:41:17.61#ibcon#read 5, iclass 21, count 0 2006.201.10:41:17.61#ibcon#about to read 6, iclass 21, count 0 2006.201.10:41:17.61#ibcon#read 6, iclass 21, count 0 2006.201.10:41:17.61#ibcon#end of sib2, iclass 21, count 0 2006.201.10:41:17.61#ibcon#*after write, iclass 21, count 0 2006.201.10:41:17.61#ibcon#*before return 0, iclass 21, count 0 2006.201.10:41:17.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:17.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:17.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:41:17.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:41:17.61$vck44/va=6,5 2006.201.10:41:17.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.10:41:17.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.10:41:17.61#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:17.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:17.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:17.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:17.66#ibcon#enter wrdev, iclass 23, count 2 2006.201.10:41:17.66#ibcon#first serial, iclass 23, count 2 2006.201.10:41:17.66#ibcon#enter sib2, iclass 23, count 2 2006.201.10:41:17.66#ibcon#flushed, iclass 23, count 2 2006.201.10:41:17.66#ibcon#about to write, iclass 23, count 2 2006.201.10:41:17.66#ibcon#wrote, iclass 23, count 2 2006.201.10:41:17.66#ibcon#about to read 3, iclass 23, count 2 2006.201.10:41:17.68#ibcon#read 3, iclass 23, count 2 2006.201.10:41:17.68#ibcon#about to read 4, iclass 23, count 2 2006.201.10:41:17.68#ibcon#read 4, iclass 23, count 2 2006.201.10:41:17.68#ibcon#about to read 5, iclass 23, count 2 2006.201.10:41:17.68#ibcon#read 5, iclass 23, count 2 2006.201.10:41:17.68#ibcon#about to read 6, iclass 23, count 2 2006.201.10:41:17.68#ibcon#read 6, iclass 23, count 2 2006.201.10:41:17.68#ibcon#end of sib2, iclass 23, count 2 2006.201.10:41:17.68#ibcon#*mode == 0, iclass 23, count 2 2006.201.10:41:17.68#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.10:41:17.68#ibcon#[25=AT06-05\r\n] 2006.201.10:41:17.68#ibcon#*before write, iclass 23, count 2 2006.201.10:41:17.68#ibcon#enter sib2, iclass 23, count 2 2006.201.10:41:17.68#ibcon#flushed, iclass 23, count 2 2006.201.10:41:17.68#ibcon#about to write, iclass 23, count 2 2006.201.10:41:17.68#ibcon#wrote, iclass 23, count 2 2006.201.10:41:17.68#ibcon#about to read 3, iclass 23, count 2 2006.201.10:41:17.71#ibcon#read 3, iclass 23, count 2 2006.201.10:41:17.71#ibcon#about to read 4, iclass 23, count 2 2006.201.10:41:17.71#ibcon#read 4, iclass 23, count 2 2006.201.10:41:17.71#ibcon#about to read 5, iclass 23, count 2 2006.201.10:41:17.71#ibcon#read 5, iclass 23, count 2 2006.201.10:41:17.71#ibcon#about to read 6, iclass 23, count 2 2006.201.10:41:17.71#ibcon#read 6, iclass 23, count 2 2006.201.10:41:17.71#ibcon#end of sib2, iclass 23, count 2 2006.201.10:41:17.71#ibcon#*after write, iclass 23, count 2 2006.201.10:41:17.71#ibcon#*before return 0, iclass 23, count 2 2006.201.10:41:17.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:17.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:17.71#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.10:41:17.71#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:17.71#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:17.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:17.83#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:17.83#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:41:17.83#ibcon#first serial, iclass 23, count 0 2006.201.10:41:17.83#ibcon#enter sib2, iclass 23, count 0 2006.201.10:41:17.83#ibcon#flushed, iclass 23, count 0 2006.201.10:41:17.83#ibcon#about to write, iclass 23, count 0 2006.201.10:41:17.83#ibcon#wrote, iclass 23, count 0 2006.201.10:41:17.83#ibcon#about to read 3, iclass 23, count 0 2006.201.10:41:17.85#ibcon#read 3, iclass 23, count 0 2006.201.10:41:17.85#ibcon#about to read 4, iclass 23, count 0 2006.201.10:41:17.85#ibcon#read 4, iclass 23, count 0 2006.201.10:41:17.85#ibcon#about to read 5, iclass 23, count 0 2006.201.10:41:17.85#ibcon#read 5, iclass 23, count 0 2006.201.10:41:17.85#ibcon#about to read 6, iclass 23, count 0 2006.201.10:41:17.85#ibcon#read 6, iclass 23, count 0 2006.201.10:41:17.85#ibcon#end of sib2, iclass 23, count 0 2006.201.10:41:17.85#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:41:17.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:41:17.85#ibcon#[25=USB\r\n] 2006.201.10:41:17.85#ibcon#*before write, iclass 23, count 0 2006.201.10:41:17.85#ibcon#enter sib2, iclass 23, count 0 2006.201.10:41:17.85#ibcon#flushed, iclass 23, count 0 2006.201.10:41:17.85#ibcon#about to write, iclass 23, count 0 2006.201.10:41:17.85#ibcon#wrote, iclass 23, count 0 2006.201.10:41:17.85#ibcon#about to read 3, iclass 23, count 0 2006.201.10:41:17.88#ibcon#read 3, iclass 23, count 0 2006.201.10:41:17.88#ibcon#about to read 4, iclass 23, count 0 2006.201.10:41:17.88#ibcon#read 4, iclass 23, count 0 2006.201.10:41:17.88#ibcon#about to read 5, iclass 23, count 0 2006.201.10:41:17.88#ibcon#read 5, iclass 23, count 0 2006.201.10:41:17.88#ibcon#about to read 6, iclass 23, count 0 2006.201.10:41:17.88#ibcon#read 6, iclass 23, count 0 2006.201.10:41:17.88#ibcon#end of sib2, iclass 23, count 0 2006.201.10:41:17.88#ibcon#*after write, iclass 23, count 0 2006.201.10:41:17.88#ibcon#*before return 0, iclass 23, count 0 2006.201.10:41:17.88#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:17.88#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:17.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:41:17.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:41:17.88$vck44/valo=7,864.99 2006.201.10:41:17.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.10:41:17.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.10:41:17.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:17.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:17.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:17.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:17.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:41:17.88#ibcon#first serial, iclass 25, count 0 2006.201.10:41:17.88#ibcon#enter sib2, iclass 25, count 0 2006.201.10:41:17.88#ibcon#flushed, iclass 25, count 0 2006.201.10:41:17.88#ibcon#about to write, iclass 25, count 0 2006.201.10:41:17.88#ibcon#wrote, iclass 25, count 0 2006.201.10:41:17.88#ibcon#about to read 3, iclass 25, count 0 2006.201.10:41:17.90#ibcon#read 3, iclass 25, count 0 2006.201.10:41:17.90#ibcon#about to read 4, iclass 25, count 0 2006.201.10:41:17.90#ibcon#read 4, iclass 25, count 0 2006.201.10:41:17.90#ibcon#about to read 5, iclass 25, count 0 2006.201.10:41:17.90#ibcon#read 5, iclass 25, count 0 2006.201.10:41:17.90#ibcon#about to read 6, iclass 25, count 0 2006.201.10:41:17.90#ibcon#read 6, iclass 25, count 0 2006.201.10:41:17.90#ibcon#end of sib2, iclass 25, count 0 2006.201.10:41:17.90#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:41:17.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:41:17.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:41:17.90#ibcon#*before write, iclass 25, count 0 2006.201.10:41:17.90#ibcon#enter sib2, iclass 25, count 0 2006.201.10:41:17.90#ibcon#flushed, iclass 25, count 0 2006.201.10:41:17.90#ibcon#about to write, iclass 25, count 0 2006.201.10:41:17.90#ibcon#wrote, iclass 25, count 0 2006.201.10:41:17.90#ibcon#about to read 3, iclass 25, count 0 2006.201.10:41:17.94#ibcon#read 3, iclass 25, count 0 2006.201.10:41:17.94#ibcon#about to read 4, iclass 25, count 0 2006.201.10:41:17.94#ibcon#read 4, iclass 25, count 0 2006.201.10:41:17.94#ibcon#about to read 5, iclass 25, count 0 2006.201.10:41:17.94#ibcon#read 5, iclass 25, count 0 2006.201.10:41:17.94#ibcon#about to read 6, iclass 25, count 0 2006.201.10:41:17.94#ibcon#read 6, iclass 25, count 0 2006.201.10:41:17.94#ibcon#end of sib2, iclass 25, count 0 2006.201.10:41:17.94#ibcon#*after write, iclass 25, count 0 2006.201.10:41:17.94#ibcon#*before return 0, iclass 25, count 0 2006.201.10:41:17.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:17.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:17.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:41:17.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:41:17.94$vck44/va=7,5 2006.201.10:41:17.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.10:41:17.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.10:41:17.94#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:17.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:18.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:18.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:18.00#ibcon#enter wrdev, iclass 27, count 2 2006.201.10:41:18.00#ibcon#first serial, iclass 27, count 2 2006.201.10:41:18.00#ibcon#enter sib2, iclass 27, count 2 2006.201.10:41:18.00#ibcon#flushed, iclass 27, count 2 2006.201.10:41:18.00#ibcon#about to write, iclass 27, count 2 2006.201.10:41:18.00#ibcon#wrote, iclass 27, count 2 2006.201.10:41:18.00#ibcon#about to read 3, iclass 27, count 2 2006.201.10:41:18.02#ibcon#read 3, iclass 27, count 2 2006.201.10:41:18.02#ibcon#about to read 4, iclass 27, count 2 2006.201.10:41:18.02#ibcon#read 4, iclass 27, count 2 2006.201.10:41:18.02#ibcon#about to read 5, iclass 27, count 2 2006.201.10:41:18.02#ibcon#read 5, iclass 27, count 2 2006.201.10:41:18.02#ibcon#about to read 6, iclass 27, count 2 2006.201.10:41:18.02#ibcon#read 6, iclass 27, count 2 2006.201.10:41:18.02#ibcon#end of sib2, iclass 27, count 2 2006.201.10:41:18.02#ibcon#*mode == 0, iclass 27, count 2 2006.201.10:41:18.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.10:41:18.02#ibcon#[25=AT07-05\r\n] 2006.201.10:41:18.02#ibcon#*before write, iclass 27, count 2 2006.201.10:41:18.02#ibcon#enter sib2, iclass 27, count 2 2006.201.10:41:18.02#ibcon#flushed, iclass 27, count 2 2006.201.10:41:18.02#ibcon#about to write, iclass 27, count 2 2006.201.10:41:18.02#ibcon#wrote, iclass 27, count 2 2006.201.10:41:18.02#ibcon#about to read 3, iclass 27, count 2 2006.201.10:41:18.05#ibcon#read 3, iclass 27, count 2 2006.201.10:41:18.05#ibcon#about to read 4, iclass 27, count 2 2006.201.10:41:18.05#ibcon#read 4, iclass 27, count 2 2006.201.10:41:18.05#ibcon#about to read 5, iclass 27, count 2 2006.201.10:41:18.05#ibcon#read 5, iclass 27, count 2 2006.201.10:41:18.05#ibcon#about to read 6, iclass 27, count 2 2006.201.10:41:18.05#ibcon#read 6, iclass 27, count 2 2006.201.10:41:18.05#ibcon#end of sib2, iclass 27, count 2 2006.201.10:41:18.05#ibcon#*after write, iclass 27, count 2 2006.201.10:41:18.05#ibcon#*before return 0, iclass 27, count 2 2006.201.10:41:18.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:18.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:18.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.10:41:18.05#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:18.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:18.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:18.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:18.17#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:41:18.17#ibcon#first serial, iclass 27, count 0 2006.201.10:41:18.17#ibcon#enter sib2, iclass 27, count 0 2006.201.10:41:18.17#ibcon#flushed, iclass 27, count 0 2006.201.10:41:18.17#ibcon#about to write, iclass 27, count 0 2006.201.10:41:18.17#ibcon#wrote, iclass 27, count 0 2006.201.10:41:18.17#ibcon#about to read 3, iclass 27, count 0 2006.201.10:41:18.20#ibcon#read 3, iclass 27, count 0 2006.201.10:41:18.20#ibcon#about to read 4, iclass 27, count 0 2006.201.10:41:18.20#ibcon#read 4, iclass 27, count 0 2006.201.10:41:18.20#ibcon#about to read 5, iclass 27, count 0 2006.201.10:41:18.20#ibcon#read 5, iclass 27, count 0 2006.201.10:41:18.20#ibcon#about to read 6, iclass 27, count 0 2006.201.10:41:18.20#ibcon#read 6, iclass 27, count 0 2006.201.10:41:18.20#ibcon#end of sib2, iclass 27, count 0 2006.201.10:41:18.20#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:41:18.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:41:18.20#ibcon#[25=USB\r\n] 2006.201.10:41:18.20#ibcon#*before write, iclass 27, count 0 2006.201.10:41:18.20#ibcon#enter sib2, iclass 27, count 0 2006.201.10:41:18.20#ibcon#flushed, iclass 27, count 0 2006.201.10:41:18.20#ibcon#about to write, iclass 27, count 0 2006.201.10:41:18.20#ibcon#wrote, iclass 27, count 0 2006.201.10:41:18.20#ibcon#about to read 3, iclass 27, count 0 2006.201.10:41:18.23#ibcon#read 3, iclass 27, count 0 2006.201.10:41:18.23#ibcon#about to read 4, iclass 27, count 0 2006.201.10:41:18.23#ibcon#read 4, iclass 27, count 0 2006.201.10:41:18.23#ibcon#about to read 5, iclass 27, count 0 2006.201.10:41:18.23#ibcon#read 5, iclass 27, count 0 2006.201.10:41:18.23#ibcon#about to read 6, iclass 27, count 0 2006.201.10:41:18.23#ibcon#read 6, iclass 27, count 0 2006.201.10:41:18.23#ibcon#end of sib2, iclass 27, count 0 2006.201.10:41:18.23#ibcon#*after write, iclass 27, count 0 2006.201.10:41:18.23#ibcon#*before return 0, iclass 27, count 0 2006.201.10:41:18.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:18.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:18.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:41:18.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:41:18.23$vck44/valo=8,884.99 2006.201.10:41:18.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.10:41:18.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.10:41:18.23#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:18.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:18.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:18.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:18.23#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:41:18.23#ibcon#first serial, iclass 29, count 0 2006.201.10:41:18.23#ibcon#enter sib2, iclass 29, count 0 2006.201.10:41:18.23#ibcon#flushed, iclass 29, count 0 2006.201.10:41:18.23#ibcon#about to write, iclass 29, count 0 2006.201.10:41:18.23#ibcon#wrote, iclass 29, count 0 2006.201.10:41:18.23#ibcon#about to read 3, iclass 29, count 0 2006.201.10:41:18.25#ibcon#read 3, iclass 29, count 0 2006.201.10:41:18.25#ibcon#about to read 4, iclass 29, count 0 2006.201.10:41:18.25#ibcon#read 4, iclass 29, count 0 2006.201.10:41:18.25#ibcon#about to read 5, iclass 29, count 0 2006.201.10:41:18.25#ibcon#read 5, iclass 29, count 0 2006.201.10:41:18.25#ibcon#about to read 6, iclass 29, count 0 2006.201.10:41:18.25#ibcon#read 6, iclass 29, count 0 2006.201.10:41:18.25#ibcon#end of sib2, iclass 29, count 0 2006.201.10:41:18.25#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:41:18.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:41:18.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:41:18.25#ibcon#*before write, iclass 29, count 0 2006.201.10:41:18.25#ibcon#enter sib2, iclass 29, count 0 2006.201.10:41:18.25#ibcon#flushed, iclass 29, count 0 2006.201.10:41:18.25#ibcon#about to write, iclass 29, count 0 2006.201.10:41:18.25#ibcon#wrote, iclass 29, count 0 2006.201.10:41:18.25#ibcon#about to read 3, iclass 29, count 0 2006.201.10:41:18.29#ibcon#read 3, iclass 29, count 0 2006.201.10:41:18.29#ibcon#about to read 4, iclass 29, count 0 2006.201.10:41:18.29#ibcon#read 4, iclass 29, count 0 2006.201.10:41:18.29#ibcon#about to read 5, iclass 29, count 0 2006.201.10:41:18.29#ibcon#read 5, iclass 29, count 0 2006.201.10:41:18.29#ibcon#about to read 6, iclass 29, count 0 2006.201.10:41:18.29#ibcon#read 6, iclass 29, count 0 2006.201.10:41:18.29#ibcon#end of sib2, iclass 29, count 0 2006.201.10:41:18.29#ibcon#*after write, iclass 29, count 0 2006.201.10:41:18.29#ibcon#*before return 0, iclass 29, count 0 2006.201.10:41:18.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:18.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:18.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:41:18.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:41:18.29$vck44/va=8,4 2006.201.10:41:18.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.10:41:18.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.10:41:18.29#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:18.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:41:18.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:41:18.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:41:18.35#ibcon#enter wrdev, iclass 31, count 2 2006.201.10:41:18.35#ibcon#first serial, iclass 31, count 2 2006.201.10:41:18.35#ibcon#enter sib2, iclass 31, count 2 2006.201.10:41:18.35#ibcon#flushed, iclass 31, count 2 2006.201.10:41:18.35#ibcon#about to write, iclass 31, count 2 2006.201.10:41:18.35#ibcon#wrote, iclass 31, count 2 2006.201.10:41:18.35#ibcon#about to read 3, iclass 31, count 2 2006.201.10:41:18.37#ibcon#read 3, iclass 31, count 2 2006.201.10:41:18.37#ibcon#about to read 4, iclass 31, count 2 2006.201.10:41:18.37#ibcon#read 4, iclass 31, count 2 2006.201.10:41:18.37#ibcon#about to read 5, iclass 31, count 2 2006.201.10:41:18.37#ibcon#read 5, iclass 31, count 2 2006.201.10:41:18.37#ibcon#about to read 6, iclass 31, count 2 2006.201.10:41:18.37#ibcon#read 6, iclass 31, count 2 2006.201.10:41:18.37#ibcon#end of sib2, iclass 31, count 2 2006.201.10:41:18.37#ibcon#*mode == 0, iclass 31, count 2 2006.201.10:41:18.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.10:41:18.37#ibcon#[25=AT08-04\r\n] 2006.201.10:41:18.37#ibcon#*before write, iclass 31, count 2 2006.201.10:41:18.37#ibcon#enter sib2, iclass 31, count 2 2006.201.10:41:18.37#ibcon#flushed, iclass 31, count 2 2006.201.10:41:18.37#ibcon#about to write, iclass 31, count 2 2006.201.10:41:18.37#ibcon#wrote, iclass 31, count 2 2006.201.10:41:18.37#ibcon#about to read 3, iclass 31, count 2 2006.201.10:41:18.41#ibcon#read 3, iclass 31, count 2 2006.201.10:41:18.41#ibcon#about to read 4, iclass 31, count 2 2006.201.10:41:18.41#ibcon#read 4, iclass 31, count 2 2006.201.10:41:18.41#ibcon#about to read 5, iclass 31, count 2 2006.201.10:41:18.41#ibcon#read 5, iclass 31, count 2 2006.201.10:41:18.41#ibcon#about to read 6, iclass 31, count 2 2006.201.10:41:18.41#ibcon#read 6, iclass 31, count 2 2006.201.10:41:18.41#ibcon#end of sib2, iclass 31, count 2 2006.201.10:41:18.41#ibcon#*after write, iclass 31, count 2 2006.201.10:41:18.41#ibcon#*before return 0, iclass 31, count 2 2006.201.10:41:18.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:41:18.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.10:41:18.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.10:41:18.41#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:18.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:41:18.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:41:18.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:41:18.53#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:41:18.53#ibcon#first serial, iclass 31, count 0 2006.201.10:41:18.53#ibcon#enter sib2, iclass 31, count 0 2006.201.10:41:18.53#ibcon#flushed, iclass 31, count 0 2006.201.10:41:18.53#ibcon#about to write, iclass 31, count 0 2006.201.10:41:18.53#ibcon#wrote, iclass 31, count 0 2006.201.10:41:18.53#ibcon#about to read 3, iclass 31, count 0 2006.201.10:41:18.55#ibcon#read 3, iclass 31, count 0 2006.201.10:41:18.55#ibcon#about to read 4, iclass 31, count 0 2006.201.10:41:18.55#ibcon#read 4, iclass 31, count 0 2006.201.10:41:18.55#ibcon#about to read 5, iclass 31, count 0 2006.201.10:41:18.55#ibcon#read 5, iclass 31, count 0 2006.201.10:41:18.55#ibcon#about to read 6, iclass 31, count 0 2006.201.10:41:18.55#ibcon#read 6, iclass 31, count 0 2006.201.10:41:18.55#ibcon#end of sib2, iclass 31, count 0 2006.201.10:41:18.55#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:41:18.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:41:18.55#ibcon#[25=USB\r\n] 2006.201.10:41:18.55#ibcon#*before write, iclass 31, count 0 2006.201.10:41:18.55#ibcon#enter sib2, iclass 31, count 0 2006.201.10:41:18.55#ibcon#flushed, iclass 31, count 0 2006.201.10:41:18.55#ibcon#about to write, iclass 31, count 0 2006.201.10:41:18.55#ibcon#wrote, iclass 31, count 0 2006.201.10:41:18.55#ibcon#about to read 3, iclass 31, count 0 2006.201.10:41:18.58#ibcon#read 3, iclass 31, count 0 2006.201.10:41:18.58#ibcon#about to read 4, iclass 31, count 0 2006.201.10:41:18.58#ibcon#read 4, iclass 31, count 0 2006.201.10:41:18.58#ibcon#about to read 5, iclass 31, count 0 2006.201.10:41:18.58#ibcon#read 5, iclass 31, count 0 2006.201.10:41:18.58#ibcon#about to read 6, iclass 31, count 0 2006.201.10:41:18.58#ibcon#read 6, iclass 31, count 0 2006.201.10:41:18.58#ibcon#end of sib2, iclass 31, count 0 2006.201.10:41:18.58#ibcon#*after write, iclass 31, count 0 2006.201.10:41:18.58#ibcon#*before return 0, iclass 31, count 0 2006.201.10:41:18.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:41:18.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.10:41:18.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:41:18.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:41:18.58$vck44/vblo=1,629.99 2006.201.10:41:18.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.10:41:18.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.10:41:18.58#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:18.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:41:18.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:41:18.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:41:18.58#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:41:18.58#ibcon#first serial, iclass 33, count 0 2006.201.10:41:18.58#ibcon#enter sib2, iclass 33, count 0 2006.201.10:41:18.58#ibcon#flushed, iclass 33, count 0 2006.201.10:41:18.58#ibcon#about to write, iclass 33, count 0 2006.201.10:41:18.58#ibcon#wrote, iclass 33, count 0 2006.201.10:41:18.58#ibcon#about to read 3, iclass 33, count 0 2006.201.10:41:18.60#ibcon#read 3, iclass 33, count 0 2006.201.10:41:18.60#ibcon#about to read 4, iclass 33, count 0 2006.201.10:41:18.60#ibcon#read 4, iclass 33, count 0 2006.201.10:41:18.60#ibcon#about to read 5, iclass 33, count 0 2006.201.10:41:18.60#ibcon#read 5, iclass 33, count 0 2006.201.10:41:18.60#ibcon#about to read 6, iclass 33, count 0 2006.201.10:41:18.60#ibcon#read 6, iclass 33, count 0 2006.201.10:41:18.60#ibcon#end of sib2, iclass 33, count 0 2006.201.10:41:18.60#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:41:18.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:41:18.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:41:18.60#ibcon#*before write, iclass 33, count 0 2006.201.10:41:18.60#ibcon#enter sib2, iclass 33, count 0 2006.201.10:41:18.60#ibcon#flushed, iclass 33, count 0 2006.201.10:41:18.60#ibcon#about to write, iclass 33, count 0 2006.201.10:41:18.60#ibcon#wrote, iclass 33, count 0 2006.201.10:41:18.60#ibcon#about to read 3, iclass 33, count 0 2006.201.10:41:18.64#ibcon#read 3, iclass 33, count 0 2006.201.10:41:18.64#ibcon#about to read 4, iclass 33, count 0 2006.201.10:41:18.64#ibcon#read 4, iclass 33, count 0 2006.201.10:41:18.64#ibcon#about to read 5, iclass 33, count 0 2006.201.10:41:18.64#ibcon#read 5, iclass 33, count 0 2006.201.10:41:18.64#ibcon#about to read 6, iclass 33, count 0 2006.201.10:41:18.64#ibcon#read 6, iclass 33, count 0 2006.201.10:41:18.64#ibcon#end of sib2, iclass 33, count 0 2006.201.10:41:18.64#ibcon#*after write, iclass 33, count 0 2006.201.10:41:18.64#ibcon#*before return 0, iclass 33, count 0 2006.201.10:41:18.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:41:18.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.10:41:18.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:41:18.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:41:18.64$vck44/vb=1,4 2006.201.10:41:18.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.10:41:18.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.10:41:18.64#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:18.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:41:18.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:41:18.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:41:18.64#ibcon#enter wrdev, iclass 35, count 2 2006.201.10:41:18.64#ibcon#first serial, iclass 35, count 2 2006.201.10:41:18.64#ibcon#enter sib2, iclass 35, count 2 2006.201.10:41:18.64#ibcon#flushed, iclass 35, count 2 2006.201.10:41:18.64#ibcon#about to write, iclass 35, count 2 2006.201.10:41:18.64#ibcon#wrote, iclass 35, count 2 2006.201.10:41:18.64#ibcon#about to read 3, iclass 35, count 2 2006.201.10:41:18.66#ibcon#read 3, iclass 35, count 2 2006.201.10:41:18.66#ibcon#about to read 4, iclass 35, count 2 2006.201.10:41:18.66#ibcon#read 4, iclass 35, count 2 2006.201.10:41:18.66#ibcon#about to read 5, iclass 35, count 2 2006.201.10:41:18.66#ibcon#read 5, iclass 35, count 2 2006.201.10:41:18.66#ibcon#about to read 6, iclass 35, count 2 2006.201.10:41:18.66#ibcon#read 6, iclass 35, count 2 2006.201.10:41:18.66#ibcon#end of sib2, iclass 35, count 2 2006.201.10:41:18.66#ibcon#*mode == 0, iclass 35, count 2 2006.201.10:41:18.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.10:41:18.66#ibcon#[27=AT01-04\r\n] 2006.201.10:41:18.66#ibcon#*before write, iclass 35, count 2 2006.201.10:41:18.66#ibcon#enter sib2, iclass 35, count 2 2006.201.10:41:18.66#ibcon#flushed, iclass 35, count 2 2006.201.10:41:18.66#ibcon#about to write, iclass 35, count 2 2006.201.10:41:18.66#ibcon#wrote, iclass 35, count 2 2006.201.10:41:18.66#ibcon#about to read 3, iclass 35, count 2 2006.201.10:41:18.69#ibcon#read 3, iclass 35, count 2 2006.201.10:41:18.69#ibcon#about to read 4, iclass 35, count 2 2006.201.10:41:18.69#ibcon#read 4, iclass 35, count 2 2006.201.10:41:18.69#ibcon#about to read 5, iclass 35, count 2 2006.201.10:41:18.69#ibcon#read 5, iclass 35, count 2 2006.201.10:41:18.69#ibcon#about to read 6, iclass 35, count 2 2006.201.10:41:18.69#ibcon#read 6, iclass 35, count 2 2006.201.10:41:18.69#ibcon#end of sib2, iclass 35, count 2 2006.201.10:41:18.69#ibcon#*after write, iclass 35, count 2 2006.201.10:41:18.69#ibcon#*before return 0, iclass 35, count 2 2006.201.10:41:18.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:41:18.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.10:41:18.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.10:41:18.69#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:18.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:41:18.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:41:18.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:41:18.81#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:41:18.81#ibcon#first serial, iclass 35, count 0 2006.201.10:41:18.81#ibcon#enter sib2, iclass 35, count 0 2006.201.10:41:18.81#ibcon#flushed, iclass 35, count 0 2006.201.10:41:18.81#ibcon#about to write, iclass 35, count 0 2006.201.10:41:18.81#ibcon#wrote, iclass 35, count 0 2006.201.10:41:18.81#ibcon#about to read 3, iclass 35, count 0 2006.201.10:41:18.83#ibcon#read 3, iclass 35, count 0 2006.201.10:41:18.83#ibcon#about to read 4, iclass 35, count 0 2006.201.10:41:18.83#ibcon#read 4, iclass 35, count 0 2006.201.10:41:18.83#ibcon#about to read 5, iclass 35, count 0 2006.201.10:41:18.83#ibcon#read 5, iclass 35, count 0 2006.201.10:41:18.83#ibcon#about to read 6, iclass 35, count 0 2006.201.10:41:18.83#ibcon#read 6, iclass 35, count 0 2006.201.10:41:18.83#ibcon#end of sib2, iclass 35, count 0 2006.201.10:41:18.83#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:41:18.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:41:18.83#ibcon#[27=USB\r\n] 2006.201.10:41:18.83#ibcon#*before write, iclass 35, count 0 2006.201.10:41:18.83#ibcon#enter sib2, iclass 35, count 0 2006.201.10:41:18.83#ibcon#flushed, iclass 35, count 0 2006.201.10:41:18.83#ibcon#about to write, iclass 35, count 0 2006.201.10:41:18.83#ibcon#wrote, iclass 35, count 0 2006.201.10:41:18.83#ibcon#about to read 3, iclass 35, count 0 2006.201.10:41:18.86#ibcon#read 3, iclass 35, count 0 2006.201.10:41:18.86#ibcon#about to read 4, iclass 35, count 0 2006.201.10:41:18.86#ibcon#read 4, iclass 35, count 0 2006.201.10:41:18.86#ibcon#about to read 5, iclass 35, count 0 2006.201.10:41:18.86#ibcon#read 5, iclass 35, count 0 2006.201.10:41:18.86#ibcon#about to read 6, iclass 35, count 0 2006.201.10:41:18.86#ibcon#read 6, iclass 35, count 0 2006.201.10:41:18.86#ibcon#end of sib2, iclass 35, count 0 2006.201.10:41:18.86#ibcon#*after write, iclass 35, count 0 2006.201.10:41:18.86#ibcon#*before return 0, iclass 35, count 0 2006.201.10:41:18.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:41:18.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.10:41:18.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:41:18.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:41:18.86$vck44/vblo=2,634.99 2006.201.10:41:18.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.10:41:18.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.10:41:18.86#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:18.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:18.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:18.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:18.86#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:41:18.86#ibcon#first serial, iclass 37, count 0 2006.201.10:41:18.86#ibcon#enter sib2, iclass 37, count 0 2006.201.10:41:18.86#ibcon#flushed, iclass 37, count 0 2006.201.10:41:18.86#ibcon#about to write, iclass 37, count 0 2006.201.10:41:18.86#ibcon#wrote, iclass 37, count 0 2006.201.10:41:18.86#ibcon#about to read 3, iclass 37, count 0 2006.201.10:41:18.88#ibcon#read 3, iclass 37, count 0 2006.201.10:41:18.88#ibcon#about to read 4, iclass 37, count 0 2006.201.10:41:18.88#ibcon#read 4, iclass 37, count 0 2006.201.10:41:18.88#ibcon#about to read 5, iclass 37, count 0 2006.201.10:41:18.88#ibcon#read 5, iclass 37, count 0 2006.201.10:41:18.88#ibcon#about to read 6, iclass 37, count 0 2006.201.10:41:18.88#ibcon#read 6, iclass 37, count 0 2006.201.10:41:18.88#ibcon#end of sib2, iclass 37, count 0 2006.201.10:41:18.88#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:41:18.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:41:18.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:41:18.88#ibcon#*before write, iclass 37, count 0 2006.201.10:41:18.88#ibcon#enter sib2, iclass 37, count 0 2006.201.10:41:18.88#ibcon#flushed, iclass 37, count 0 2006.201.10:41:18.88#ibcon#about to write, iclass 37, count 0 2006.201.10:41:18.88#ibcon#wrote, iclass 37, count 0 2006.201.10:41:18.88#ibcon#about to read 3, iclass 37, count 0 2006.201.10:41:18.92#ibcon#read 3, iclass 37, count 0 2006.201.10:41:18.92#ibcon#about to read 4, iclass 37, count 0 2006.201.10:41:18.92#ibcon#read 4, iclass 37, count 0 2006.201.10:41:18.92#ibcon#about to read 5, iclass 37, count 0 2006.201.10:41:18.92#ibcon#read 5, iclass 37, count 0 2006.201.10:41:18.92#ibcon#about to read 6, iclass 37, count 0 2006.201.10:41:18.92#ibcon#read 6, iclass 37, count 0 2006.201.10:41:18.92#ibcon#end of sib2, iclass 37, count 0 2006.201.10:41:18.92#ibcon#*after write, iclass 37, count 0 2006.201.10:41:18.92#ibcon#*before return 0, iclass 37, count 0 2006.201.10:41:18.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:18.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.10:41:18.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:41:18.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:41:18.92$vck44/vb=2,5 2006.201.10:41:18.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.10:41:18.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.10:41:18.92#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:18.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:18.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:18.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:18.98#ibcon#enter wrdev, iclass 39, count 2 2006.201.10:41:18.98#ibcon#first serial, iclass 39, count 2 2006.201.10:41:18.98#ibcon#enter sib2, iclass 39, count 2 2006.201.10:41:18.98#ibcon#flushed, iclass 39, count 2 2006.201.10:41:18.98#ibcon#about to write, iclass 39, count 2 2006.201.10:41:18.98#ibcon#wrote, iclass 39, count 2 2006.201.10:41:18.98#ibcon#about to read 3, iclass 39, count 2 2006.201.10:41:19.00#ibcon#read 3, iclass 39, count 2 2006.201.10:41:19.00#ibcon#about to read 4, iclass 39, count 2 2006.201.10:41:19.00#ibcon#read 4, iclass 39, count 2 2006.201.10:41:19.00#ibcon#about to read 5, iclass 39, count 2 2006.201.10:41:19.00#ibcon#read 5, iclass 39, count 2 2006.201.10:41:19.00#ibcon#about to read 6, iclass 39, count 2 2006.201.10:41:19.00#ibcon#read 6, iclass 39, count 2 2006.201.10:41:19.00#ibcon#end of sib2, iclass 39, count 2 2006.201.10:41:19.00#ibcon#*mode == 0, iclass 39, count 2 2006.201.10:41:19.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.10:41:19.00#ibcon#[27=AT02-05\r\n] 2006.201.10:41:19.00#ibcon#*before write, iclass 39, count 2 2006.201.10:41:19.00#ibcon#enter sib2, iclass 39, count 2 2006.201.10:41:19.00#ibcon#flushed, iclass 39, count 2 2006.201.10:41:19.00#ibcon#about to write, iclass 39, count 2 2006.201.10:41:19.00#ibcon#wrote, iclass 39, count 2 2006.201.10:41:19.00#ibcon#about to read 3, iclass 39, count 2 2006.201.10:41:19.03#ibcon#read 3, iclass 39, count 2 2006.201.10:41:19.03#ibcon#about to read 4, iclass 39, count 2 2006.201.10:41:19.03#ibcon#read 4, iclass 39, count 2 2006.201.10:41:19.03#ibcon#about to read 5, iclass 39, count 2 2006.201.10:41:19.03#ibcon#read 5, iclass 39, count 2 2006.201.10:41:19.03#ibcon#about to read 6, iclass 39, count 2 2006.201.10:41:19.03#ibcon#read 6, iclass 39, count 2 2006.201.10:41:19.03#ibcon#end of sib2, iclass 39, count 2 2006.201.10:41:19.03#ibcon#*after write, iclass 39, count 2 2006.201.10:41:19.03#ibcon#*before return 0, iclass 39, count 2 2006.201.10:41:19.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:19.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.10:41:19.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.10:41:19.03#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:19.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:19.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:19.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:19.15#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:41:19.15#ibcon#first serial, iclass 39, count 0 2006.201.10:41:19.15#ibcon#enter sib2, iclass 39, count 0 2006.201.10:41:19.15#ibcon#flushed, iclass 39, count 0 2006.201.10:41:19.15#ibcon#about to write, iclass 39, count 0 2006.201.10:41:19.15#ibcon#wrote, iclass 39, count 0 2006.201.10:41:19.15#ibcon#about to read 3, iclass 39, count 0 2006.201.10:41:19.17#ibcon#read 3, iclass 39, count 0 2006.201.10:41:19.17#ibcon#about to read 4, iclass 39, count 0 2006.201.10:41:19.17#ibcon#read 4, iclass 39, count 0 2006.201.10:41:19.17#ibcon#about to read 5, iclass 39, count 0 2006.201.10:41:19.17#ibcon#read 5, iclass 39, count 0 2006.201.10:41:19.17#ibcon#about to read 6, iclass 39, count 0 2006.201.10:41:19.17#ibcon#read 6, iclass 39, count 0 2006.201.10:41:19.17#ibcon#end of sib2, iclass 39, count 0 2006.201.10:41:19.17#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:41:19.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:41:19.17#ibcon#[27=USB\r\n] 2006.201.10:41:19.17#ibcon#*before write, iclass 39, count 0 2006.201.10:41:19.17#ibcon#enter sib2, iclass 39, count 0 2006.201.10:41:19.17#ibcon#flushed, iclass 39, count 0 2006.201.10:41:19.17#ibcon#about to write, iclass 39, count 0 2006.201.10:41:19.17#ibcon#wrote, iclass 39, count 0 2006.201.10:41:19.17#ibcon#about to read 3, iclass 39, count 0 2006.201.10:41:19.20#ibcon#read 3, iclass 39, count 0 2006.201.10:41:19.20#ibcon#about to read 4, iclass 39, count 0 2006.201.10:41:19.20#ibcon#read 4, iclass 39, count 0 2006.201.10:41:19.20#ibcon#about to read 5, iclass 39, count 0 2006.201.10:41:19.20#ibcon#read 5, iclass 39, count 0 2006.201.10:41:19.20#ibcon#about to read 6, iclass 39, count 0 2006.201.10:41:19.20#ibcon#read 6, iclass 39, count 0 2006.201.10:41:19.20#ibcon#end of sib2, iclass 39, count 0 2006.201.10:41:19.20#ibcon#*after write, iclass 39, count 0 2006.201.10:41:19.20#ibcon#*before return 0, iclass 39, count 0 2006.201.10:41:19.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:19.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.10:41:19.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:41:19.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:41:19.20$vck44/vblo=3,649.99 2006.201.10:41:19.20#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.10:41:19.20#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.10:41:19.20#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:19.20#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:19.20#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:19.20#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:19.20#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:41:19.20#ibcon#first serial, iclass 2, count 0 2006.201.10:41:19.20#ibcon#enter sib2, iclass 2, count 0 2006.201.10:41:19.20#ibcon#flushed, iclass 2, count 0 2006.201.10:41:19.20#ibcon#about to write, iclass 2, count 0 2006.201.10:41:19.20#ibcon#wrote, iclass 2, count 0 2006.201.10:41:19.20#ibcon#about to read 3, iclass 2, count 0 2006.201.10:41:19.22#ibcon#read 3, iclass 2, count 0 2006.201.10:41:19.22#ibcon#about to read 4, iclass 2, count 0 2006.201.10:41:19.22#ibcon#read 4, iclass 2, count 0 2006.201.10:41:19.22#ibcon#about to read 5, iclass 2, count 0 2006.201.10:41:19.22#ibcon#read 5, iclass 2, count 0 2006.201.10:41:19.22#ibcon#about to read 6, iclass 2, count 0 2006.201.10:41:19.22#ibcon#read 6, iclass 2, count 0 2006.201.10:41:19.22#ibcon#end of sib2, iclass 2, count 0 2006.201.10:41:19.22#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:41:19.22#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:41:19.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:41:19.22#ibcon#*before write, iclass 2, count 0 2006.201.10:41:19.22#ibcon#enter sib2, iclass 2, count 0 2006.201.10:41:19.22#ibcon#flushed, iclass 2, count 0 2006.201.10:41:19.22#ibcon#about to write, iclass 2, count 0 2006.201.10:41:19.22#ibcon#wrote, iclass 2, count 0 2006.201.10:41:19.22#ibcon#about to read 3, iclass 2, count 0 2006.201.10:41:19.26#ibcon#read 3, iclass 2, count 0 2006.201.10:41:19.26#ibcon#about to read 4, iclass 2, count 0 2006.201.10:41:19.26#ibcon#read 4, iclass 2, count 0 2006.201.10:41:19.26#ibcon#about to read 5, iclass 2, count 0 2006.201.10:41:19.26#ibcon#read 5, iclass 2, count 0 2006.201.10:41:19.26#ibcon#about to read 6, iclass 2, count 0 2006.201.10:41:19.26#ibcon#read 6, iclass 2, count 0 2006.201.10:41:19.26#ibcon#end of sib2, iclass 2, count 0 2006.201.10:41:19.26#ibcon#*after write, iclass 2, count 0 2006.201.10:41:19.26#ibcon#*before return 0, iclass 2, count 0 2006.201.10:41:19.26#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:19.26#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.10:41:19.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:41:19.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:41:19.26$vck44/vb=3,4 2006.201.10:41:19.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.10:41:19.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.10:41:19.26#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:19.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:19.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:19.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:19.32#ibcon#enter wrdev, iclass 5, count 2 2006.201.10:41:19.32#ibcon#first serial, iclass 5, count 2 2006.201.10:41:19.32#ibcon#enter sib2, iclass 5, count 2 2006.201.10:41:19.32#ibcon#flushed, iclass 5, count 2 2006.201.10:41:19.32#ibcon#about to write, iclass 5, count 2 2006.201.10:41:19.32#ibcon#wrote, iclass 5, count 2 2006.201.10:41:19.32#ibcon#about to read 3, iclass 5, count 2 2006.201.10:41:19.34#ibcon#read 3, iclass 5, count 2 2006.201.10:41:19.34#ibcon#about to read 4, iclass 5, count 2 2006.201.10:41:19.34#ibcon#read 4, iclass 5, count 2 2006.201.10:41:19.34#ibcon#about to read 5, iclass 5, count 2 2006.201.10:41:19.34#ibcon#read 5, iclass 5, count 2 2006.201.10:41:19.34#ibcon#about to read 6, iclass 5, count 2 2006.201.10:41:19.34#ibcon#read 6, iclass 5, count 2 2006.201.10:41:19.34#ibcon#end of sib2, iclass 5, count 2 2006.201.10:41:19.34#ibcon#*mode == 0, iclass 5, count 2 2006.201.10:41:19.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.10:41:19.34#ibcon#[27=AT03-04\r\n] 2006.201.10:41:19.34#ibcon#*before write, iclass 5, count 2 2006.201.10:41:19.34#ibcon#enter sib2, iclass 5, count 2 2006.201.10:41:19.34#ibcon#flushed, iclass 5, count 2 2006.201.10:41:19.34#ibcon#about to write, iclass 5, count 2 2006.201.10:41:19.34#ibcon#wrote, iclass 5, count 2 2006.201.10:41:19.34#ibcon#about to read 3, iclass 5, count 2 2006.201.10:41:19.37#ibcon#read 3, iclass 5, count 2 2006.201.10:41:19.37#ibcon#about to read 4, iclass 5, count 2 2006.201.10:41:19.37#ibcon#read 4, iclass 5, count 2 2006.201.10:41:19.37#ibcon#about to read 5, iclass 5, count 2 2006.201.10:41:19.37#ibcon#read 5, iclass 5, count 2 2006.201.10:41:19.37#ibcon#about to read 6, iclass 5, count 2 2006.201.10:41:19.37#ibcon#read 6, iclass 5, count 2 2006.201.10:41:19.37#ibcon#end of sib2, iclass 5, count 2 2006.201.10:41:19.37#ibcon#*after write, iclass 5, count 2 2006.201.10:41:19.37#ibcon#*before return 0, iclass 5, count 2 2006.201.10:41:19.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:19.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.10:41:19.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.10:41:19.37#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:19.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:19.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:19.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:19.49#ibcon#enter wrdev, iclass 5, count 0 2006.201.10:41:19.49#ibcon#first serial, iclass 5, count 0 2006.201.10:41:19.49#ibcon#enter sib2, iclass 5, count 0 2006.201.10:41:19.49#ibcon#flushed, iclass 5, count 0 2006.201.10:41:19.49#ibcon#about to write, iclass 5, count 0 2006.201.10:41:19.49#ibcon#wrote, iclass 5, count 0 2006.201.10:41:19.49#ibcon#about to read 3, iclass 5, count 0 2006.201.10:41:19.51#ibcon#read 3, iclass 5, count 0 2006.201.10:41:19.51#ibcon#about to read 4, iclass 5, count 0 2006.201.10:41:19.51#ibcon#read 4, iclass 5, count 0 2006.201.10:41:19.51#ibcon#about to read 5, iclass 5, count 0 2006.201.10:41:19.51#ibcon#read 5, iclass 5, count 0 2006.201.10:41:19.51#ibcon#about to read 6, iclass 5, count 0 2006.201.10:41:19.51#ibcon#read 6, iclass 5, count 0 2006.201.10:41:19.51#ibcon#end of sib2, iclass 5, count 0 2006.201.10:41:19.51#ibcon#*mode == 0, iclass 5, count 0 2006.201.10:41:19.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.10:41:19.51#ibcon#[27=USB\r\n] 2006.201.10:41:19.51#ibcon#*before write, iclass 5, count 0 2006.201.10:41:19.51#ibcon#enter sib2, iclass 5, count 0 2006.201.10:41:19.51#ibcon#flushed, iclass 5, count 0 2006.201.10:41:19.51#ibcon#about to write, iclass 5, count 0 2006.201.10:41:19.51#ibcon#wrote, iclass 5, count 0 2006.201.10:41:19.51#ibcon#about to read 3, iclass 5, count 0 2006.201.10:41:19.54#ibcon#read 3, iclass 5, count 0 2006.201.10:41:19.54#ibcon#about to read 4, iclass 5, count 0 2006.201.10:41:19.54#ibcon#read 4, iclass 5, count 0 2006.201.10:41:19.54#ibcon#about to read 5, iclass 5, count 0 2006.201.10:41:19.54#ibcon#read 5, iclass 5, count 0 2006.201.10:41:19.54#ibcon#about to read 6, iclass 5, count 0 2006.201.10:41:19.54#ibcon#read 6, iclass 5, count 0 2006.201.10:41:19.54#ibcon#end of sib2, iclass 5, count 0 2006.201.10:41:19.54#ibcon#*after write, iclass 5, count 0 2006.201.10:41:19.54#ibcon#*before return 0, iclass 5, count 0 2006.201.10:41:19.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:19.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.10:41:19.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.10:41:19.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.10:41:19.54$vck44/vblo=4,679.99 2006.201.10:41:19.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.10:41:19.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.10:41:19.54#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:19.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:19.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:19.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:19.54#ibcon#enter wrdev, iclass 7, count 0 2006.201.10:41:19.54#ibcon#first serial, iclass 7, count 0 2006.201.10:41:19.54#ibcon#enter sib2, iclass 7, count 0 2006.201.10:41:19.54#ibcon#flushed, iclass 7, count 0 2006.201.10:41:19.54#ibcon#about to write, iclass 7, count 0 2006.201.10:41:19.54#ibcon#wrote, iclass 7, count 0 2006.201.10:41:19.54#ibcon#about to read 3, iclass 7, count 0 2006.201.10:41:19.56#ibcon#read 3, iclass 7, count 0 2006.201.10:41:19.56#ibcon#about to read 4, iclass 7, count 0 2006.201.10:41:19.56#ibcon#read 4, iclass 7, count 0 2006.201.10:41:19.56#ibcon#about to read 5, iclass 7, count 0 2006.201.10:41:19.56#ibcon#read 5, iclass 7, count 0 2006.201.10:41:19.56#ibcon#about to read 6, iclass 7, count 0 2006.201.10:41:19.56#ibcon#read 6, iclass 7, count 0 2006.201.10:41:19.56#ibcon#end of sib2, iclass 7, count 0 2006.201.10:41:19.56#ibcon#*mode == 0, iclass 7, count 0 2006.201.10:41:19.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.10:41:19.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:41:19.56#ibcon#*before write, iclass 7, count 0 2006.201.10:41:19.56#ibcon#enter sib2, iclass 7, count 0 2006.201.10:41:19.56#ibcon#flushed, iclass 7, count 0 2006.201.10:41:19.56#ibcon#about to write, iclass 7, count 0 2006.201.10:41:19.56#ibcon#wrote, iclass 7, count 0 2006.201.10:41:19.56#ibcon#about to read 3, iclass 7, count 0 2006.201.10:41:19.60#ibcon#read 3, iclass 7, count 0 2006.201.10:41:19.60#ibcon#about to read 4, iclass 7, count 0 2006.201.10:41:19.60#ibcon#read 4, iclass 7, count 0 2006.201.10:41:19.60#ibcon#about to read 5, iclass 7, count 0 2006.201.10:41:19.60#ibcon#read 5, iclass 7, count 0 2006.201.10:41:19.60#ibcon#about to read 6, iclass 7, count 0 2006.201.10:41:19.60#ibcon#read 6, iclass 7, count 0 2006.201.10:41:19.60#ibcon#end of sib2, iclass 7, count 0 2006.201.10:41:19.60#ibcon#*after write, iclass 7, count 0 2006.201.10:41:19.60#ibcon#*before return 0, iclass 7, count 0 2006.201.10:41:19.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:19.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.10:41:19.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.10:41:19.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.10:41:19.60$vck44/vb=4,5 2006.201.10:41:19.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.10:41:19.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.10:41:19.60#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:19.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:19.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:19.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:19.66#ibcon#enter wrdev, iclass 11, count 2 2006.201.10:41:19.66#ibcon#first serial, iclass 11, count 2 2006.201.10:41:19.66#ibcon#enter sib2, iclass 11, count 2 2006.201.10:41:19.66#ibcon#flushed, iclass 11, count 2 2006.201.10:41:19.66#ibcon#about to write, iclass 11, count 2 2006.201.10:41:19.66#ibcon#wrote, iclass 11, count 2 2006.201.10:41:19.66#ibcon#about to read 3, iclass 11, count 2 2006.201.10:41:19.68#ibcon#read 3, iclass 11, count 2 2006.201.10:41:19.68#ibcon#about to read 4, iclass 11, count 2 2006.201.10:41:19.68#ibcon#read 4, iclass 11, count 2 2006.201.10:41:19.68#ibcon#about to read 5, iclass 11, count 2 2006.201.10:41:19.68#ibcon#read 5, iclass 11, count 2 2006.201.10:41:19.68#ibcon#about to read 6, iclass 11, count 2 2006.201.10:41:19.68#ibcon#read 6, iclass 11, count 2 2006.201.10:41:19.68#ibcon#end of sib2, iclass 11, count 2 2006.201.10:41:19.68#ibcon#*mode == 0, iclass 11, count 2 2006.201.10:41:19.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.10:41:19.68#ibcon#[27=AT04-05\r\n] 2006.201.10:41:19.68#ibcon#*before write, iclass 11, count 2 2006.201.10:41:19.68#ibcon#enter sib2, iclass 11, count 2 2006.201.10:41:19.68#ibcon#flushed, iclass 11, count 2 2006.201.10:41:19.68#ibcon#about to write, iclass 11, count 2 2006.201.10:41:19.68#ibcon#wrote, iclass 11, count 2 2006.201.10:41:19.68#ibcon#about to read 3, iclass 11, count 2 2006.201.10:41:19.71#ibcon#read 3, iclass 11, count 2 2006.201.10:41:19.71#ibcon#about to read 4, iclass 11, count 2 2006.201.10:41:19.71#ibcon#read 4, iclass 11, count 2 2006.201.10:41:19.71#ibcon#about to read 5, iclass 11, count 2 2006.201.10:41:19.71#ibcon#read 5, iclass 11, count 2 2006.201.10:41:19.71#ibcon#about to read 6, iclass 11, count 2 2006.201.10:41:19.71#ibcon#read 6, iclass 11, count 2 2006.201.10:41:19.71#ibcon#end of sib2, iclass 11, count 2 2006.201.10:41:19.71#ibcon#*after write, iclass 11, count 2 2006.201.10:41:19.71#ibcon#*before return 0, iclass 11, count 2 2006.201.10:41:19.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:19.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.10:41:19.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.10:41:19.71#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:19.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:19.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:19.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:19.83#ibcon#enter wrdev, iclass 11, count 0 2006.201.10:41:19.83#ibcon#first serial, iclass 11, count 0 2006.201.10:41:19.83#ibcon#enter sib2, iclass 11, count 0 2006.201.10:41:19.83#ibcon#flushed, iclass 11, count 0 2006.201.10:41:19.83#ibcon#about to write, iclass 11, count 0 2006.201.10:41:19.83#ibcon#wrote, iclass 11, count 0 2006.201.10:41:19.83#ibcon#about to read 3, iclass 11, count 0 2006.201.10:41:19.85#ibcon#read 3, iclass 11, count 0 2006.201.10:41:19.85#ibcon#about to read 4, iclass 11, count 0 2006.201.10:41:19.85#ibcon#read 4, iclass 11, count 0 2006.201.10:41:19.85#ibcon#about to read 5, iclass 11, count 0 2006.201.10:41:19.85#ibcon#read 5, iclass 11, count 0 2006.201.10:41:19.85#ibcon#about to read 6, iclass 11, count 0 2006.201.10:41:19.85#ibcon#read 6, iclass 11, count 0 2006.201.10:41:19.85#ibcon#end of sib2, iclass 11, count 0 2006.201.10:41:19.85#ibcon#*mode == 0, iclass 11, count 0 2006.201.10:41:19.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.10:41:19.85#ibcon#[27=USB\r\n] 2006.201.10:41:19.85#ibcon#*before write, iclass 11, count 0 2006.201.10:41:19.85#ibcon#enter sib2, iclass 11, count 0 2006.201.10:41:19.85#ibcon#flushed, iclass 11, count 0 2006.201.10:41:19.85#ibcon#about to write, iclass 11, count 0 2006.201.10:41:19.85#ibcon#wrote, iclass 11, count 0 2006.201.10:41:19.85#ibcon#about to read 3, iclass 11, count 0 2006.201.10:41:19.88#ibcon#read 3, iclass 11, count 0 2006.201.10:41:19.88#ibcon#about to read 4, iclass 11, count 0 2006.201.10:41:19.88#ibcon#read 4, iclass 11, count 0 2006.201.10:41:19.88#ibcon#about to read 5, iclass 11, count 0 2006.201.10:41:19.88#ibcon#read 5, iclass 11, count 0 2006.201.10:41:19.88#ibcon#about to read 6, iclass 11, count 0 2006.201.10:41:19.88#ibcon#read 6, iclass 11, count 0 2006.201.10:41:19.88#ibcon#end of sib2, iclass 11, count 0 2006.201.10:41:19.88#ibcon#*after write, iclass 11, count 0 2006.201.10:41:19.88#ibcon#*before return 0, iclass 11, count 0 2006.201.10:41:19.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:19.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.10:41:19.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.10:41:19.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.10:41:19.88$vck44/vblo=5,709.99 2006.201.10:41:19.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.10:41:19.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.10:41:19.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:19.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:19.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:19.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:19.88#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:41:19.88#ibcon#first serial, iclass 13, count 0 2006.201.10:41:19.88#ibcon#enter sib2, iclass 13, count 0 2006.201.10:41:19.88#ibcon#flushed, iclass 13, count 0 2006.201.10:41:19.88#ibcon#about to write, iclass 13, count 0 2006.201.10:41:19.88#ibcon#wrote, iclass 13, count 0 2006.201.10:41:19.88#ibcon#about to read 3, iclass 13, count 0 2006.201.10:41:19.90#ibcon#read 3, iclass 13, count 0 2006.201.10:41:19.90#ibcon#about to read 4, iclass 13, count 0 2006.201.10:41:19.90#ibcon#read 4, iclass 13, count 0 2006.201.10:41:19.90#ibcon#about to read 5, iclass 13, count 0 2006.201.10:41:19.90#ibcon#read 5, iclass 13, count 0 2006.201.10:41:19.90#ibcon#about to read 6, iclass 13, count 0 2006.201.10:41:19.90#ibcon#read 6, iclass 13, count 0 2006.201.10:41:19.90#ibcon#end of sib2, iclass 13, count 0 2006.201.10:41:19.90#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:41:19.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:41:19.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:41:19.90#ibcon#*before write, iclass 13, count 0 2006.201.10:41:19.90#ibcon#enter sib2, iclass 13, count 0 2006.201.10:41:19.90#ibcon#flushed, iclass 13, count 0 2006.201.10:41:19.90#ibcon#about to write, iclass 13, count 0 2006.201.10:41:19.90#ibcon#wrote, iclass 13, count 0 2006.201.10:41:19.90#ibcon#about to read 3, iclass 13, count 0 2006.201.10:41:19.95#ibcon#read 3, iclass 13, count 0 2006.201.10:41:19.95#ibcon#about to read 4, iclass 13, count 0 2006.201.10:41:19.95#ibcon#read 4, iclass 13, count 0 2006.201.10:41:19.95#ibcon#about to read 5, iclass 13, count 0 2006.201.10:41:19.95#ibcon#read 5, iclass 13, count 0 2006.201.10:41:19.95#ibcon#about to read 6, iclass 13, count 0 2006.201.10:41:19.95#ibcon#read 6, iclass 13, count 0 2006.201.10:41:19.95#ibcon#end of sib2, iclass 13, count 0 2006.201.10:41:19.95#ibcon#*after write, iclass 13, count 0 2006.201.10:41:19.95#ibcon#*before return 0, iclass 13, count 0 2006.201.10:41:19.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:19.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.10:41:19.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:41:19.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:41:19.95$vck44/vb=5,4 2006.201.10:41:19.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.10:41:19.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.10:41:19.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:19.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:20.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:20.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:20.00#ibcon#enter wrdev, iclass 15, count 2 2006.201.10:41:20.00#ibcon#first serial, iclass 15, count 2 2006.201.10:41:20.00#ibcon#enter sib2, iclass 15, count 2 2006.201.10:41:20.00#ibcon#flushed, iclass 15, count 2 2006.201.10:41:20.00#ibcon#about to write, iclass 15, count 2 2006.201.10:41:20.00#ibcon#wrote, iclass 15, count 2 2006.201.10:41:20.00#ibcon#about to read 3, iclass 15, count 2 2006.201.10:41:20.02#ibcon#read 3, iclass 15, count 2 2006.201.10:41:20.02#ibcon#about to read 4, iclass 15, count 2 2006.201.10:41:20.02#ibcon#read 4, iclass 15, count 2 2006.201.10:41:20.02#ibcon#about to read 5, iclass 15, count 2 2006.201.10:41:20.02#ibcon#read 5, iclass 15, count 2 2006.201.10:41:20.02#ibcon#about to read 6, iclass 15, count 2 2006.201.10:41:20.02#ibcon#read 6, iclass 15, count 2 2006.201.10:41:20.02#ibcon#end of sib2, iclass 15, count 2 2006.201.10:41:20.02#ibcon#*mode == 0, iclass 15, count 2 2006.201.10:41:20.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.10:41:20.02#ibcon#[27=AT05-04\r\n] 2006.201.10:41:20.02#ibcon#*before write, iclass 15, count 2 2006.201.10:41:20.02#ibcon#enter sib2, iclass 15, count 2 2006.201.10:41:20.02#ibcon#flushed, iclass 15, count 2 2006.201.10:41:20.02#ibcon#about to write, iclass 15, count 2 2006.201.10:41:20.02#ibcon#wrote, iclass 15, count 2 2006.201.10:41:20.02#ibcon#about to read 3, iclass 15, count 2 2006.201.10:41:20.05#ibcon#read 3, iclass 15, count 2 2006.201.10:41:20.05#ibcon#about to read 4, iclass 15, count 2 2006.201.10:41:20.05#ibcon#read 4, iclass 15, count 2 2006.201.10:41:20.05#ibcon#about to read 5, iclass 15, count 2 2006.201.10:41:20.05#ibcon#read 5, iclass 15, count 2 2006.201.10:41:20.05#ibcon#about to read 6, iclass 15, count 2 2006.201.10:41:20.05#ibcon#read 6, iclass 15, count 2 2006.201.10:41:20.05#ibcon#end of sib2, iclass 15, count 2 2006.201.10:41:20.05#ibcon#*after write, iclass 15, count 2 2006.201.10:41:20.05#ibcon#*before return 0, iclass 15, count 2 2006.201.10:41:20.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:20.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.10:41:20.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.10:41:20.05#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:20.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:20.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:20.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:20.17#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:41:20.17#ibcon#first serial, iclass 15, count 0 2006.201.10:41:20.17#ibcon#enter sib2, iclass 15, count 0 2006.201.10:41:20.17#ibcon#flushed, iclass 15, count 0 2006.201.10:41:20.17#ibcon#about to write, iclass 15, count 0 2006.201.10:41:20.17#ibcon#wrote, iclass 15, count 0 2006.201.10:41:20.17#ibcon#about to read 3, iclass 15, count 0 2006.201.10:41:20.20#ibcon#read 3, iclass 15, count 0 2006.201.10:41:20.20#ibcon#about to read 4, iclass 15, count 0 2006.201.10:41:20.20#ibcon#read 4, iclass 15, count 0 2006.201.10:41:20.20#ibcon#about to read 5, iclass 15, count 0 2006.201.10:41:20.20#ibcon#read 5, iclass 15, count 0 2006.201.10:41:20.20#ibcon#about to read 6, iclass 15, count 0 2006.201.10:41:20.20#ibcon#read 6, iclass 15, count 0 2006.201.10:41:20.20#ibcon#end of sib2, iclass 15, count 0 2006.201.10:41:20.20#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:41:20.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:41:20.20#ibcon#[27=USB\r\n] 2006.201.10:41:20.20#ibcon#*before write, iclass 15, count 0 2006.201.10:41:20.20#ibcon#enter sib2, iclass 15, count 0 2006.201.10:41:20.20#ibcon#flushed, iclass 15, count 0 2006.201.10:41:20.20#ibcon#about to write, iclass 15, count 0 2006.201.10:41:20.20#ibcon#wrote, iclass 15, count 0 2006.201.10:41:20.20#ibcon#about to read 3, iclass 15, count 0 2006.201.10:41:20.23#ibcon#read 3, iclass 15, count 0 2006.201.10:41:20.23#ibcon#about to read 4, iclass 15, count 0 2006.201.10:41:20.23#ibcon#read 4, iclass 15, count 0 2006.201.10:41:20.23#ibcon#about to read 5, iclass 15, count 0 2006.201.10:41:20.23#ibcon#read 5, iclass 15, count 0 2006.201.10:41:20.23#ibcon#about to read 6, iclass 15, count 0 2006.201.10:41:20.23#ibcon#read 6, iclass 15, count 0 2006.201.10:41:20.23#ibcon#end of sib2, iclass 15, count 0 2006.201.10:41:20.23#ibcon#*after write, iclass 15, count 0 2006.201.10:41:20.23#ibcon#*before return 0, iclass 15, count 0 2006.201.10:41:20.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:20.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.10:41:20.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:41:20.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:41:20.23$vck44/vblo=6,719.99 2006.201.10:41:20.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.10:41:20.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.10:41:20.23#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:20.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:20.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:20.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:20.23#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:41:20.23#ibcon#first serial, iclass 17, count 0 2006.201.10:41:20.23#ibcon#enter sib2, iclass 17, count 0 2006.201.10:41:20.23#ibcon#flushed, iclass 17, count 0 2006.201.10:41:20.23#ibcon#about to write, iclass 17, count 0 2006.201.10:41:20.23#ibcon#wrote, iclass 17, count 0 2006.201.10:41:20.23#ibcon#about to read 3, iclass 17, count 0 2006.201.10:41:20.25#ibcon#read 3, iclass 17, count 0 2006.201.10:41:20.25#ibcon#about to read 4, iclass 17, count 0 2006.201.10:41:20.25#ibcon#read 4, iclass 17, count 0 2006.201.10:41:20.25#ibcon#about to read 5, iclass 17, count 0 2006.201.10:41:20.25#ibcon#read 5, iclass 17, count 0 2006.201.10:41:20.25#ibcon#about to read 6, iclass 17, count 0 2006.201.10:41:20.25#ibcon#read 6, iclass 17, count 0 2006.201.10:41:20.25#ibcon#end of sib2, iclass 17, count 0 2006.201.10:41:20.25#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:41:20.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:41:20.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:41:20.25#ibcon#*before write, iclass 17, count 0 2006.201.10:41:20.25#ibcon#enter sib2, iclass 17, count 0 2006.201.10:41:20.25#ibcon#flushed, iclass 17, count 0 2006.201.10:41:20.25#ibcon#about to write, iclass 17, count 0 2006.201.10:41:20.25#ibcon#wrote, iclass 17, count 0 2006.201.10:41:20.25#ibcon#about to read 3, iclass 17, count 0 2006.201.10:41:20.29#ibcon#read 3, iclass 17, count 0 2006.201.10:41:20.29#ibcon#about to read 4, iclass 17, count 0 2006.201.10:41:20.29#ibcon#read 4, iclass 17, count 0 2006.201.10:41:20.29#ibcon#about to read 5, iclass 17, count 0 2006.201.10:41:20.29#ibcon#read 5, iclass 17, count 0 2006.201.10:41:20.29#ibcon#about to read 6, iclass 17, count 0 2006.201.10:41:20.29#ibcon#read 6, iclass 17, count 0 2006.201.10:41:20.29#ibcon#end of sib2, iclass 17, count 0 2006.201.10:41:20.29#ibcon#*after write, iclass 17, count 0 2006.201.10:41:20.29#ibcon#*before return 0, iclass 17, count 0 2006.201.10:41:20.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:20.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:41:20.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:41:20.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:41:20.29$vck44/vb=6,4 2006.201.10:41:20.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.10:41:20.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.10:41:20.29#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:20.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:20.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:20.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:20.35#ibcon#enter wrdev, iclass 19, count 2 2006.201.10:41:20.35#ibcon#first serial, iclass 19, count 2 2006.201.10:41:20.35#ibcon#enter sib2, iclass 19, count 2 2006.201.10:41:20.35#ibcon#flushed, iclass 19, count 2 2006.201.10:41:20.35#ibcon#about to write, iclass 19, count 2 2006.201.10:41:20.35#ibcon#wrote, iclass 19, count 2 2006.201.10:41:20.35#ibcon#about to read 3, iclass 19, count 2 2006.201.10:41:20.37#ibcon#read 3, iclass 19, count 2 2006.201.10:41:20.37#ibcon#about to read 4, iclass 19, count 2 2006.201.10:41:20.37#ibcon#read 4, iclass 19, count 2 2006.201.10:41:20.37#ibcon#about to read 5, iclass 19, count 2 2006.201.10:41:20.37#ibcon#read 5, iclass 19, count 2 2006.201.10:41:20.37#ibcon#about to read 6, iclass 19, count 2 2006.201.10:41:20.37#ibcon#read 6, iclass 19, count 2 2006.201.10:41:20.37#ibcon#end of sib2, iclass 19, count 2 2006.201.10:41:20.37#ibcon#*mode == 0, iclass 19, count 2 2006.201.10:41:20.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.10:41:20.37#ibcon#[27=AT06-04\r\n] 2006.201.10:41:20.37#ibcon#*before write, iclass 19, count 2 2006.201.10:41:20.37#ibcon#enter sib2, iclass 19, count 2 2006.201.10:41:20.37#ibcon#flushed, iclass 19, count 2 2006.201.10:41:20.37#ibcon#about to write, iclass 19, count 2 2006.201.10:41:20.37#ibcon#wrote, iclass 19, count 2 2006.201.10:41:20.37#ibcon#about to read 3, iclass 19, count 2 2006.201.10:41:20.40#ibcon#read 3, iclass 19, count 2 2006.201.10:41:20.40#ibcon#about to read 4, iclass 19, count 2 2006.201.10:41:20.40#ibcon#read 4, iclass 19, count 2 2006.201.10:41:20.40#ibcon#about to read 5, iclass 19, count 2 2006.201.10:41:20.40#ibcon#read 5, iclass 19, count 2 2006.201.10:41:20.40#ibcon#about to read 6, iclass 19, count 2 2006.201.10:41:20.40#ibcon#read 6, iclass 19, count 2 2006.201.10:41:20.40#ibcon#end of sib2, iclass 19, count 2 2006.201.10:41:20.40#ibcon#*after write, iclass 19, count 2 2006.201.10:41:20.40#ibcon#*before return 0, iclass 19, count 2 2006.201.10:41:20.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:20.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.10:41:20.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.10:41:20.40#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:20.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:20.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:20.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:20.52#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:41:20.52#ibcon#first serial, iclass 19, count 0 2006.201.10:41:20.52#ibcon#enter sib2, iclass 19, count 0 2006.201.10:41:20.52#ibcon#flushed, iclass 19, count 0 2006.201.10:41:20.52#ibcon#about to write, iclass 19, count 0 2006.201.10:41:20.52#ibcon#wrote, iclass 19, count 0 2006.201.10:41:20.52#ibcon#about to read 3, iclass 19, count 0 2006.201.10:41:20.54#ibcon#read 3, iclass 19, count 0 2006.201.10:41:20.54#ibcon#about to read 4, iclass 19, count 0 2006.201.10:41:20.54#ibcon#read 4, iclass 19, count 0 2006.201.10:41:20.54#ibcon#about to read 5, iclass 19, count 0 2006.201.10:41:20.54#ibcon#read 5, iclass 19, count 0 2006.201.10:41:20.54#ibcon#about to read 6, iclass 19, count 0 2006.201.10:41:20.54#ibcon#read 6, iclass 19, count 0 2006.201.10:41:20.54#ibcon#end of sib2, iclass 19, count 0 2006.201.10:41:20.54#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:41:20.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:41:20.54#ibcon#[27=USB\r\n] 2006.201.10:41:20.54#ibcon#*before write, iclass 19, count 0 2006.201.10:41:20.54#ibcon#enter sib2, iclass 19, count 0 2006.201.10:41:20.54#ibcon#flushed, iclass 19, count 0 2006.201.10:41:20.54#ibcon#about to write, iclass 19, count 0 2006.201.10:41:20.54#ibcon#wrote, iclass 19, count 0 2006.201.10:41:20.54#ibcon#about to read 3, iclass 19, count 0 2006.201.10:41:20.57#ibcon#read 3, iclass 19, count 0 2006.201.10:41:20.57#ibcon#about to read 4, iclass 19, count 0 2006.201.10:41:20.57#ibcon#read 4, iclass 19, count 0 2006.201.10:41:20.57#ibcon#about to read 5, iclass 19, count 0 2006.201.10:41:20.57#ibcon#read 5, iclass 19, count 0 2006.201.10:41:20.57#ibcon#about to read 6, iclass 19, count 0 2006.201.10:41:20.57#ibcon#read 6, iclass 19, count 0 2006.201.10:41:20.57#ibcon#end of sib2, iclass 19, count 0 2006.201.10:41:20.57#ibcon#*after write, iclass 19, count 0 2006.201.10:41:20.57#ibcon#*before return 0, iclass 19, count 0 2006.201.10:41:20.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:20.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.10:41:20.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:41:20.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:41:20.57$vck44/vblo=7,734.99 2006.201.10:41:20.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.10:41:20.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.10:41:20.57#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:20.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:20.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:20.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:20.57#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:41:20.57#ibcon#first serial, iclass 21, count 0 2006.201.10:41:20.57#ibcon#enter sib2, iclass 21, count 0 2006.201.10:41:20.57#ibcon#flushed, iclass 21, count 0 2006.201.10:41:20.57#ibcon#about to write, iclass 21, count 0 2006.201.10:41:20.57#ibcon#wrote, iclass 21, count 0 2006.201.10:41:20.57#ibcon#about to read 3, iclass 21, count 0 2006.201.10:41:20.59#ibcon#read 3, iclass 21, count 0 2006.201.10:41:20.59#ibcon#about to read 4, iclass 21, count 0 2006.201.10:41:20.59#ibcon#read 4, iclass 21, count 0 2006.201.10:41:20.59#ibcon#about to read 5, iclass 21, count 0 2006.201.10:41:20.59#ibcon#read 5, iclass 21, count 0 2006.201.10:41:20.59#ibcon#about to read 6, iclass 21, count 0 2006.201.10:41:20.59#ibcon#read 6, iclass 21, count 0 2006.201.10:41:20.59#ibcon#end of sib2, iclass 21, count 0 2006.201.10:41:20.59#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:41:20.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:41:20.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:41:20.59#ibcon#*before write, iclass 21, count 0 2006.201.10:41:20.59#ibcon#enter sib2, iclass 21, count 0 2006.201.10:41:20.59#ibcon#flushed, iclass 21, count 0 2006.201.10:41:20.59#ibcon#about to write, iclass 21, count 0 2006.201.10:41:20.59#ibcon#wrote, iclass 21, count 0 2006.201.10:41:20.59#ibcon#about to read 3, iclass 21, count 0 2006.201.10:41:20.63#ibcon#read 3, iclass 21, count 0 2006.201.10:41:20.63#ibcon#about to read 4, iclass 21, count 0 2006.201.10:41:20.63#ibcon#read 4, iclass 21, count 0 2006.201.10:41:20.63#ibcon#about to read 5, iclass 21, count 0 2006.201.10:41:20.63#ibcon#read 5, iclass 21, count 0 2006.201.10:41:20.63#ibcon#about to read 6, iclass 21, count 0 2006.201.10:41:20.63#ibcon#read 6, iclass 21, count 0 2006.201.10:41:20.63#ibcon#end of sib2, iclass 21, count 0 2006.201.10:41:20.63#ibcon#*after write, iclass 21, count 0 2006.201.10:41:20.63#ibcon#*before return 0, iclass 21, count 0 2006.201.10:41:20.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:20.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.10:41:20.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:41:20.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:41:20.63$vck44/vb=7,4 2006.201.10:41:20.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.10:41:20.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.10:41:20.63#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:20.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:20.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:20.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:20.69#ibcon#enter wrdev, iclass 23, count 2 2006.201.10:41:20.69#ibcon#first serial, iclass 23, count 2 2006.201.10:41:20.69#ibcon#enter sib2, iclass 23, count 2 2006.201.10:41:20.69#ibcon#flushed, iclass 23, count 2 2006.201.10:41:20.69#ibcon#about to write, iclass 23, count 2 2006.201.10:41:20.69#ibcon#wrote, iclass 23, count 2 2006.201.10:41:20.69#ibcon#about to read 3, iclass 23, count 2 2006.201.10:41:20.71#ibcon#read 3, iclass 23, count 2 2006.201.10:41:20.71#ibcon#about to read 4, iclass 23, count 2 2006.201.10:41:20.71#ibcon#read 4, iclass 23, count 2 2006.201.10:41:20.71#ibcon#about to read 5, iclass 23, count 2 2006.201.10:41:20.71#ibcon#read 5, iclass 23, count 2 2006.201.10:41:20.71#ibcon#about to read 6, iclass 23, count 2 2006.201.10:41:20.71#ibcon#read 6, iclass 23, count 2 2006.201.10:41:20.71#ibcon#end of sib2, iclass 23, count 2 2006.201.10:41:20.71#ibcon#*mode == 0, iclass 23, count 2 2006.201.10:41:20.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.10:41:20.71#ibcon#[27=AT07-04\r\n] 2006.201.10:41:20.71#ibcon#*before write, iclass 23, count 2 2006.201.10:41:20.71#ibcon#enter sib2, iclass 23, count 2 2006.201.10:41:20.71#ibcon#flushed, iclass 23, count 2 2006.201.10:41:20.71#ibcon#about to write, iclass 23, count 2 2006.201.10:41:20.71#ibcon#wrote, iclass 23, count 2 2006.201.10:41:20.71#ibcon#about to read 3, iclass 23, count 2 2006.201.10:41:20.74#ibcon#read 3, iclass 23, count 2 2006.201.10:41:20.74#ibcon#about to read 4, iclass 23, count 2 2006.201.10:41:20.74#ibcon#read 4, iclass 23, count 2 2006.201.10:41:20.74#ibcon#about to read 5, iclass 23, count 2 2006.201.10:41:20.74#ibcon#read 5, iclass 23, count 2 2006.201.10:41:20.74#ibcon#about to read 6, iclass 23, count 2 2006.201.10:41:20.74#ibcon#read 6, iclass 23, count 2 2006.201.10:41:20.74#ibcon#end of sib2, iclass 23, count 2 2006.201.10:41:20.74#ibcon#*after write, iclass 23, count 2 2006.201.10:41:20.74#ibcon#*before return 0, iclass 23, count 2 2006.201.10:41:20.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:20.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.10:41:20.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.10:41:20.74#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:20.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:20.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:20.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:20.86#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:41:20.86#ibcon#first serial, iclass 23, count 0 2006.201.10:41:20.86#ibcon#enter sib2, iclass 23, count 0 2006.201.10:41:20.86#ibcon#flushed, iclass 23, count 0 2006.201.10:41:20.86#ibcon#about to write, iclass 23, count 0 2006.201.10:41:20.86#ibcon#wrote, iclass 23, count 0 2006.201.10:41:20.86#ibcon#about to read 3, iclass 23, count 0 2006.201.10:41:20.88#ibcon#read 3, iclass 23, count 0 2006.201.10:41:20.88#ibcon#about to read 4, iclass 23, count 0 2006.201.10:41:20.88#ibcon#read 4, iclass 23, count 0 2006.201.10:41:20.88#ibcon#about to read 5, iclass 23, count 0 2006.201.10:41:20.88#ibcon#read 5, iclass 23, count 0 2006.201.10:41:20.88#ibcon#about to read 6, iclass 23, count 0 2006.201.10:41:20.88#ibcon#read 6, iclass 23, count 0 2006.201.10:41:20.88#ibcon#end of sib2, iclass 23, count 0 2006.201.10:41:20.88#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:41:20.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:41:20.88#ibcon#[27=USB\r\n] 2006.201.10:41:20.88#ibcon#*before write, iclass 23, count 0 2006.201.10:41:20.88#ibcon#enter sib2, iclass 23, count 0 2006.201.10:41:20.88#ibcon#flushed, iclass 23, count 0 2006.201.10:41:20.88#ibcon#about to write, iclass 23, count 0 2006.201.10:41:20.88#ibcon#wrote, iclass 23, count 0 2006.201.10:41:20.88#ibcon#about to read 3, iclass 23, count 0 2006.201.10:41:20.91#ibcon#read 3, iclass 23, count 0 2006.201.10:41:20.91#ibcon#about to read 4, iclass 23, count 0 2006.201.10:41:20.91#ibcon#read 4, iclass 23, count 0 2006.201.10:41:20.91#ibcon#about to read 5, iclass 23, count 0 2006.201.10:41:20.91#ibcon#read 5, iclass 23, count 0 2006.201.10:41:20.91#ibcon#about to read 6, iclass 23, count 0 2006.201.10:41:20.91#ibcon#read 6, iclass 23, count 0 2006.201.10:41:20.91#ibcon#end of sib2, iclass 23, count 0 2006.201.10:41:20.91#ibcon#*after write, iclass 23, count 0 2006.201.10:41:20.91#ibcon#*before return 0, iclass 23, count 0 2006.201.10:41:20.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:20.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.10:41:20.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:41:20.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:41:20.91$vck44/vblo=8,744.99 2006.201.10:41:20.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.10:41:20.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.10:41:20.91#ibcon#ireg 17 cls_cnt 0 2006.201.10:41:20.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:20.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:20.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:20.91#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:41:20.91#ibcon#first serial, iclass 25, count 0 2006.201.10:41:20.91#ibcon#enter sib2, iclass 25, count 0 2006.201.10:41:20.91#ibcon#flushed, iclass 25, count 0 2006.201.10:41:20.91#ibcon#about to write, iclass 25, count 0 2006.201.10:41:20.91#ibcon#wrote, iclass 25, count 0 2006.201.10:41:20.91#ibcon#about to read 3, iclass 25, count 0 2006.201.10:41:20.93#ibcon#read 3, iclass 25, count 0 2006.201.10:41:20.93#ibcon#about to read 4, iclass 25, count 0 2006.201.10:41:20.93#ibcon#read 4, iclass 25, count 0 2006.201.10:41:20.93#ibcon#about to read 5, iclass 25, count 0 2006.201.10:41:20.93#ibcon#read 5, iclass 25, count 0 2006.201.10:41:20.93#ibcon#about to read 6, iclass 25, count 0 2006.201.10:41:20.93#ibcon#read 6, iclass 25, count 0 2006.201.10:41:20.93#ibcon#end of sib2, iclass 25, count 0 2006.201.10:41:20.93#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:41:20.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:41:20.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:41:20.93#ibcon#*before write, iclass 25, count 0 2006.201.10:41:20.93#ibcon#enter sib2, iclass 25, count 0 2006.201.10:41:20.93#ibcon#flushed, iclass 25, count 0 2006.201.10:41:20.93#ibcon#about to write, iclass 25, count 0 2006.201.10:41:20.93#ibcon#wrote, iclass 25, count 0 2006.201.10:41:20.93#ibcon#about to read 3, iclass 25, count 0 2006.201.10:41:20.98#ibcon#read 3, iclass 25, count 0 2006.201.10:41:20.98#ibcon#about to read 4, iclass 25, count 0 2006.201.10:41:20.98#ibcon#read 4, iclass 25, count 0 2006.201.10:41:20.98#ibcon#about to read 5, iclass 25, count 0 2006.201.10:41:20.98#ibcon#read 5, iclass 25, count 0 2006.201.10:41:20.98#ibcon#about to read 6, iclass 25, count 0 2006.201.10:41:20.98#ibcon#read 6, iclass 25, count 0 2006.201.10:41:20.98#ibcon#end of sib2, iclass 25, count 0 2006.201.10:41:20.98#ibcon#*after write, iclass 25, count 0 2006.201.10:41:20.98#ibcon#*before return 0, iclass 25, count 0 2006.201.10:41:20.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:20.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:41:20.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:41:20.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:41:20.98$vck44/vb=8,4 2006.201.10:41:20.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.10:41:20.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.10:41:20.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:41:20.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:21.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:21.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:21.03#ibcon#enter wrdev, iclass 27, count 2 2006.201.10:41:21.03#ibcon#first serial, iclass 27, count 2 2006.201.10:41:21.03#ibcon#enter sib2, iclass 27, count 2 2006.201.10:41:21.03#ibcon#flushed, iclass 27, count 2 2006.201.10:41:21.03#ibcon#about to write, iclass 27, count 2 2006.201.10:41:21.03#ibcon#wrote, iclass 27, count 2 2006.201.10:41:21.03#ibcon#about to read 3, iclass 27, count 2 2006.201.10:41:21.05#ibcon#read 3, iclass 27, count 2 2006.201.10:41:21.05#ibcon#about to read 4, iclass 27, count 2 2006.201.10:41:21.05#ibcon#read 4, iclass 27, count 2 2006.201.10:41:21.05#ibcon#about to read 5, iclass 27, count 2 2006.201.10:41:21.05#ibcon#read 5, iclass 27, count 2 2006.201.10:41:21.05#ibcon#about to read 6, iclass 27, count 2 2006.201.10:41:21.05#ibcon#read 6, iclass 27, count 2 2006.201.10:41:21.05#ibcon#end of sib2, iclass 27, count 2 2006.201.10:41:21.05#ibcon#*mode == 0, iclass 27, count 2 2006.201.10:41:21.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.10:41:21.05#ibcon#[27=AT08-04\r\n] 2006.201.10:41:21.05#ibcon#*before write, iclass 27, count 2 2006.201.10:41:21.05#ibcon#enter sib2, iclass 27, count 2 2006.201.10:41:21.05#ibcon#flushed, iclass 27, count 2 2006.201.10:41:21.05#ibcon#about to write, iclass 27, count 2 2006.201.10:41:21.05#ibcon#wrote, iclass 27, count 2 2006.201.10:41:21.05#ibcon#about to read 3, iclass 27, count 2 2006.201.10:41:21.08#ibcon#read 3, iclass 27, count 2 2006.201.10:41:21.08#ibcon#about to read 4, iclass 27, count 2 2006.201.10:41:21.08#ibcon#read 4, iclass 27, count 2 2006.201.10:41:21.08#ibcon#about to read 5, iclass 27, count 2 2006.201.10:41:21.08#ibcon#read 5, iclass 27, count 2 2006.201.10:41:21.08#ibcon#about to read 6, iclass 27, count 2 2006.201.10:41:21.08#ibcon#read 6, iclass 27, count 2 2006.201.10:41:21.08#ibcon#end of sib2, iclass 27, count 2 2006.201.10:41:21.08#ibcon#*after write, iclass 27, count 2 2006.201.10:41:21.08#ibcon#*before return 0, iclass 27, count 2 2006.201.10:41:21.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:21.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.10:41:21.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.10:41:21.08#ibcon#ireg 7 cls_cnt 0 2006.201.10:41:21.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:21.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:21.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:21.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:41:21.20#ibcon#first serial, iclass 27, count 0 2006.201.10:41:21.20#ibcon#enter sib2, iclass 27, count 0 2006.201.10:41:21.20#ibcon#flushed, iclass 27, count 0 2006.201.10:41:21.20#ibcon#about to write, iclass 27, count 0 2006.201.10:41:21.20#ibcon#wrote, iclass 27, count 0 2006.201.10:41:21.20#ibcon#about to read 3, iclass 27, count 0 2006.201.10:41:21.22#ibcon#read 3, iclass 27, count 0 2006.201.10:41:21.22#ibcon#about to read 4, iclass 27, count 0 2006.201.10:41:21.22#ibcon#read 4, iclass 27, count 0 2006.201.10:41:21.22#ibcon#about to read 5, iclass 27, count 0 2006.201.10:41:21.22#ibcon#read 5, iclass 27, count 0 2006.201.10:41:21.22#ibcon#about to read 6, iclass 27, count 0 2006.201.10:41:21.22#ibcon#read 6, iclass 27, count 0 2006.201.10:41:21.22#ibcon#end of sib2, iclass 27, count 0 2006.201.10:41:21.22#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:41:21.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:41:21.22#ibcon#[27=USB\r\n] 2006.201.10:41:21.22#ibcon#*before write, iclass 27, count 0 2006.201.10:41:21.22#ibcon#enter sib2, iclass 27, count 0 2006.201.10:41:21.22#ibcon#flushed, iclass 27, count 0 2006.201.10:41:21.22#ibcon#about to write, iclass 27, count 0 2006.201.10:41:21.22#ibcon#wrote, iclass 27, count 0 2006.201.10:41:21.22#ibcon#about to read 3, iclass 27, count 0 2006.201.10:41:21.25#ibcon#read 3, iclass 27, count 0 2006.201.10:41:21.25#ibcon#about to read 4, iclass 27, count 0 2006.201.10:41:21.25#ibcon#read 4, iclass 27, count 0 2006.201.10:41:21.25#ibcon#about to read 5, iclass 27, count 0 2006.201.10:41:21.25#ibcon#read 5, iclass 27, count 0 2006.201.10:41:21.25#ibcon#about to read 6, iclass 27, count 0 2006.201.10:41:21.25#ibcon#read 6, iclass 27, count 0 2006.201.10:41:21.25#ibcon#end of sib2, iclass 27, count 0 2006.201.10:41:21.25#ibcon#*after write, iclass 27, count 0 2006.201.10:41:21.25#ibcon#*before return 0, iclass 27, count 0 2006.201.10:41:21.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:21.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.10:41:21.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:41:21.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:41:21.25$vck44/vabw=wide 2006.201.10:41:21.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.10:41:21.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.10:41:21.25#ibcon#ireg 8 cls_cnt 0 2006.201.10:41:21.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:21.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:21.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:21.25#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:41:21.25#ibcon#first serial, iclass 29, count 0 2006.201.10:41:21.25#ibcon#enter sib2, iclass 29, count 0 2006.201.10:41:21.25#ibcon#flushed, iclass 29, count 0 2006.201.10:41:21.25#ibcon#about to write, iclass 29, count 0 2006.201.10:41:21.25#ibcon#wrote, iclass 29, count 0 2006.201.10:41:21.25#ibcon#about to read 3, iclass 29, count 0 2006.201.10:41:21.27#ibcon#read 3, iclass 29, count 0 2006.201.10:41:21.27#ibcon#about to read 4, iclass 29, count 0 2006.201.10:41:21.27#ibcon#read 4, iclass 29, count 0 2006.201.10:41:21.27#ibcon#about to read 5, iclass 29, count 0 2006.201.10:41:21.27#ibcon#read 5, iclass 29, count 0 2006.201.10:41:21.27#ibcon#about to read 6, iclass 29, count 0 2006.201.10:41:21.27#ibcon#read 6, iclass 29, count 0 2006.201.10:41:21.27#ibcon#end of sib2, iclass 29, count 0 2006.201.10:41:21.27#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:41:21.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:41:21.27#ibcon#[25=BW32\r\n] 2006.201.10:41:21.27#ibcon#*before write, iclass 29, count 0 2006.201.10:41:21.27#ibcon#enter sib2, iclass 29, count 0 2006.201.10:41:21.27#ibcon#flushed, iclass 29, count 0 2006.201.10:41:21.27#ibcon#about to write, iclass 29, count 0 2006.201.10:41:21.27#ibcon#wrote, iclass 29, count 0 2006.201.10:41:21.27#ibcon#about to read 3, iclass 29, count 0 2006.201.10:41:21.30#ibcon#read 3, iclass 29, count 0 2006.201.10:41:21.30#ibcon#about to read 4, iclass 29, count 0 2006.201.10:41:21.30#ibcon#read 4, iclass 29, count 0 2006.201.10:41:21.30#ibcon#about to read 5, iclass 29, count 0 2006.201.10:41:21.30#ibcon#read 5, iclass 29, count 0 2006.201.10:41:21.30#ibcon#about to read 6, iclass 29, count 0 2006.201.10:41:21.30#ibcon#read 6, iclass 29, count 0 2006.201.10:41:21.30#ibcon#end of sib2, iclass 29, count 0 2006.201.10:41:21.30#ibcon#*after write, iclass 29, count 0 2006.201.10:41:21.30#ibcon#*before return 0, iclass 29, count 0 2006.201.10:41:21.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:21.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.10:41:21.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:41:21.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:41:21.30$vck44/vbbw=wide 2006.201.10:41:21.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.10:41:21.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.10:41:21.30#ibcon#ireg 8 cls_cnt 0 2006.201.10:41:21.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:41:21.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:41:21.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:41:21.37#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:41:21.37#ibcon#first serial, iclass 31, count 0 2006.201.10:41:21.37#ibcon#enter sib2, iclass 31, count 0 2006.201.10:41:21.37#ibcon#flushed, iclass 31, count 0 2006.201.10:41:21.37#ibcon#about to write, iclass 31, count 0 2006.201.10:41:21.37#ibcon#wrote, iclass 31, count 0 2006.201.10:41:21.37#ibcon#about to read 3, iclass 31, count 0 2006.201.10:41:21.39#ibcon#read 3, iclass 31, count 0 2006.201.10:41:21.39#ibcon#about to read 4, iclass 31, count 0 2006.201.10:41:21.39#ibcon#read 4, iclass 31, count 0 2006.201.10:41:21.39#ibcon#about to read 5, iclass 31, count 0 2006.201.10:41:21.39#ibcon#read 5, iclass 31, count 0 2006.201.10:41:21.39#ibcon#about to read 6, iclass 31, count 0 2006.201.10:41:21.39#ibcon#read 6, iclass 31, count 0 2006.201.10:41:21.39#ibcon#end of sib2, iclass 31, count 0 2006.201.10:41:21.39#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:41:21.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:41:21.39#ibcon#[27=BW32\r\n] 2006.201.10:41:21.39#ibcon#*before write, iclass 31, count 0 2006.201.10:41:21.39#ibcon#enter sib2, iclass 31, count 0 2006.201.10:41:21.39#ibcon#flushed, iclass 31, count 0 2006.201.10:41:21.39#ibcon#about to write, iclass 31, count 0 2006.201.10:41:21.39#ibcon#wrote, iclass 31, count 0 2006.201.10:41:21.39#ibcon#about to read 3, iclass 31, count 0 2006.201.10:41:21.42#ibcon#read 3, iclass 31, count 0 2006.201.10:41:21.42#ibcon#about to read 4, iclass 31, count 0 2006.201.10:41:21.42#ibcon#read 4, iclass 31, count 0 2006.201.10:41:21.42#ibcon#about to read 5, iclass 31, count 0 2006.201.10:41:21.42#ibcon#read 5, iclass 31, count 0 2006.201.10:41:21.42#ibcon#about to read 6, iclass 31, count 0 2006.201.10:41:21.42#ibcon#read 6, iclass 31, count 0 2006.201.10:41:21.42#ibcon#end of sib2, iclass 31, count 0 2006.201.10:41:21.42#ibcon#*after write, iclass 31, count 0 2006.201.10:41:21.42#ibcon#*before return 0, iclass 31, count 0 2006.201.10:41:21.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:41:21.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:41:21.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:41:21.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:41:21.42$setupk4/ifdk4 2006.201.10:41:21.42$ifdk4/lo= 2006.201.10:41:21.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:41:21.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:41:21.42$ifdk4/patch= 2006.201.10:41:21.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:41:21.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:41:21.42$setupk4/!*+20s 2006.201.10:41:22.40#abcon#<5=/05 2.4 4.2 21.61 981003.7\r\n> 2006.201.10:41:22.42#abcon#{5=INTERFACE CLEAR} 2006.201.10:41:22.48#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:41:32.57#abcon#<5=/05 2.4 4.2 21.61 981003.6\r\n> 2006.201.10:41:32.59#abcon#{5=INTERFACE CLEAR} 2006.201.10:41:32.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:41:35.87$setupk4/"tpicd 2006.201.10:41:35.87$setupk4/echo=off 2006.201.10:41:35.87$setupk4/xlog=off 2006.201.10:41:35.87:!2006.201.10:45:04 2006.201.10:41:56.13#trakl#Source acquired 2006.201.10:41:56.13#flagr#flagr/antenna,acquired 2006.201.10:45:04.00:preob 2006.201.10:45:04.14/onsource/TRACKING 2006.201.10:45:04.14:!2006.201.10:45:14 2006.201.10:45:14.00:"tape 2006.201.10:45:14.00:"st=record 2006.201.10:45:14.00:data_valid=on 2006.201.10:45:14.00:midob 2006.201.10:45:14.14/onsource/TRACKING 2006.201.10:45:14.14/wx/21.58,1003.7,98 2006.201.10:45:14.36/cable/+6.4704E-03 2006.201.10:45:15.45/va/01,08,usb,yes,29,31 2006.201.10:45:15.45/va/02,07,usb,yes,31,32 2006.201.10:45:15.45/va/03,08,usb,yes,28,29 2006.201.10:45:15.45/va/04,07,usb,yes,32,34 2006.201.10:45:15.45/va/05,04,usb,yes,28,29 2006.201.10:45:15.45/va/06,05,usb,yes,28,28 2006.201.10:45:15.45/va/07,05,usb,yes,27,29 2006.201.10:45:15.45/va/08,04,usb,yes,27,33 2006.201.10:45:15.68/valo/01,524.99,yes,locked 2006.201.10:45:15.68/valo/02,534.99,yes,locked 2006.201.10:45:15.68/valo/03,564.99,yes,locked 2006.201.10:45:15.68/valo/04,624.99,yes,locked 2006.201.10:45:15.68/valo/05,734.99,yes,locked 2006.201.10:45:15.68/valo/06,814.99,yes,locked 2006.201.10:45:15.68/valo/07,864.99,yes,locked 2006.201.10:45:15.68/valo/08,884.99,yes,locked 2006.201.10:45:16.77/vb/01,04,usb,yes,29,27 2006.201.10:45:16.77/vb/02,05,usb,yes,27,27 2006.201.10:45:16.77/vb/03,04,usb,yes,28,31 2006.201.10:45:16.77/vb/04,05,usb,yes,28,27 2006.201.10:45:16.77/vb/05,04,usb,yes,25,27 2006.201.10:45:16.77/vb/06,04,usb,yes,29,25 2006.201.10:45:16.77/vb/07,04,usb,yes,29,29 2006.201.10:45:16.77/vb/08,04,usb,yes,27,30 2006.201.10:45:17.01/vblo/01,629.99,yes,locked 2006.201.10:45:17.01/vblo/02,634.99,yes,locked 2006.201.10:45:17.01/vblo/03,649.99,yes,locked 2006.201.10:45:17.01/vblo/04,679.99,yes,locked 2006.201.10:45:17.01/vblo/05,709.99,yes,locked 2006.201.10:45:17.01/vblo/06,719.99,yes,locked 2006.201.10:45:17.01/vblo/07,734.99,yes,locked 2006.201.10:45:17.01/vblo/08,744.99,yes,locked 2006.201.10:45:17.16/vabw/8 2006.201.10:45:17.31/vbbw/8 2006.201.10:45:17.42/xfe/off,on,15.5 2006.201.10:45:17.79/ifatt/23,28,28,28 2006.201.10:45:18.05/fmout-gps/S +4.55E-07 2006.201.10:45:18.12:!2006.201.10:47:04 2006.201.10:47:04.00:data_valid=off 2006.201.10:47:04.00:"et 2006.201.10:47:04.00:!+3s 2006.201.10:47:07.02:"tape 2006.201.10:47:07.02:postob 2006.201.10:47:07.16/cable/+6.4709E-03 2006.201.10:47:07.16/wx/21.56,1003.7,98 2006.201.10:47:07.22/fmout-gps/S +4.54E-07 2006.201.10:47:07.22:scan_name=201-1049,jd0607,40 2006.201.10:47:07.22:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.201.10:47:08.14#flagr#flagr/antenna,new-source 2006.201.10:47:08.14:checkk5 2006.201.10:47:08.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:47:08.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:47:09.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:47:09.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:47:10.03/chk_obsdata//k5ts1/T2011045??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.10:47:10.39/chk_obsdata//k5ts2/T2011045??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.10:47:10.76/chk_obsdata//k5ts3/T2011045??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.10:47:11.13/chk_obsdata//k5ts4/T2011045??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.10:47:11.82/k5log//k5ts1_log_newline 2006.201.10:47:12.51/k5log//k5ts2_log_newline 2006.201.10:47:13.20/k5log//k5ts3_log_newline 2006.201.10:47:13.88/k5log//k5ts4_log_newline 2006.201.10:47:13.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:47:13.91:setupk4=1 2006.201.10:47:13.91$setupk4/echo=on 2006.201.10:47:13.91$setupk4/pcalon 2006.201.10:47:13.91$pcalon/"no phase cal control is implemented here 2006.201.10:47:13.91$setupk4/"tpicd=stop 2006.201.10:47:13.91$setupk4/"rec=synch_on 2006.201.10:47:13.91$setupk4/"rec_mode=128 2006.201.10:47:13.91$setupk4/!* 2006.201.10:47:13.91$setupk4/recpk4 2006.201.10:47:13.91$recpk4/recpatch= 2006.201.10:47:13.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:47:13.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:47:13.91$setupk4/vck44 2006.201.10:47:13.91$vck44/valo=1,524.99 2006.201.10:47:13.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.10:47:13.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.10:47:13.91#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:13.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:13.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:13.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:13.91#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:47:13.91#ibcon#first serial, iclass 32, count 0 2006.201.10:47:13.91#ibcon#enter sib2, iclass 32, count 0 2006.201.10:47:13.91#ibcon#flushed, iclass 32, count 0 2006.201.10:47:13.91#ibcon#about to write, iclass 32, count 0 2006.201.10:47:13.91#ibcon#wrote, iclass 32, count 0 2006.201.10:47:13.91#ibcon#about to read 3, iclass 32, count 0 2006.201.10:47:13.95#ibcon#read 3, iclass 32, count 0 2006.201.10:47:13.95#ibcon#about to read 4, iclass 32, count 0 2006.201.10:47:13.95#ibcon#read 4, iclass 32, count 0 2006.201.10:47:13.95#ibcon#about to read 5, iclass 32, count 0 2006.201.10:47:13.95#ibcon#read 5, iclass 32, count 0 2006.201.10:47:13.95#ibcon#about to read 6, iclass 32, count 0 2006.201.10:47:13.95#ibcon#read 6, iclass 32, count 0 2006.201.10:47:13.95#ibcon#end of sib2, iclass 32, count 0 2006.201.10:47:13.95#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:47:13.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:47:13.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:47:13.95#ibcon#*before write, iclass 32, count 0 2006.201.10:47:13.95#ibcon#enter sib2, iclass 32, count 0 2006.201.10:47:13.95#ibcon#flushed, iclass 32, count 0 2006.201.10:47:13.95#ibcon#about to write, iclass 32, count 0 2006.201.10:47:13.95#ibcon#wrote, iclass 32, count 0 2006.201.10:47:13.95#ibcon#about to read 3, iclass 32, count 0 2006.201.10:47:14.00#ibcon#read 3, iclass 32, count 0 2006.201.10:47:14.00#ibcon#about to read 4, iclass 32, count 0 2006.201.10:47:14.00#ibcon#read 4, iclass 32, count 0 2006.201.10:47:14.00#ibcon#about to read 5, iclass 32, count 0 2006.201.10:47:14.00#ibcon#read 5, iclass 32, count 0 2006.201.10:47:14.00#ibcon#about to read 6, iclass 32, count 0 2006.201.10:47:14.00#ibcon#read 6, iclass 32, count 0 2006.201.10:47:14.00#ibcon#end of sib2, iclass 32, count 0 2006.201.10:47:14.00#ibcon#*after write, iclass 32, count 0 2006.201.10:47:14.00#ibcon#*before return 0, iclass 32, count 0 2006.201.10:47:14.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:14.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:14.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:47:14.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:47:14.00$vck44/va=1,8 2006.201.10:47:14.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.10:47:14.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.10:47:14.00#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:14.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:14.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:14.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:14.00#ibcon#enter wrdev, iclass 34, count 2 2006.201.10:47:14.00#ibcon#first serial, iclass 34, count 2 2006.201.10:47:14.00#ibcon#enter sib2, iclass 34, count 2 2006.201.10:47:14.00#ibcon#flushed, iclass 34, count 2 2006.201.10:47:14.00#ibcon#about to write, iclass 34, count 2 2006.201.10:47:14.00#ibcon#wrote, iclass 34, count 2 2006.201.10:47:14.00#ibcon#about to read 3, iclass 34, count 2 2006.201.10:47:14.02#ibcon#read 3, iclass 34, count 2 2006.201.10:47:14.02#ibcon#about to read 4, iclass 34, count 2 2006.201.10:47:14.02#ibcon#read 4, iclass 34, count 2 2006.201.10:47:14.02#ibcon#about to read 5, iclass 34, count 2 2006.201.10:47:14.02#ibcon#read 5, iclass 34, count 2 2006.201.10:47:14.02#ibcon#about to read 6, iclass 34, count 2 2006.201.10:47:14.02#ibcon#read 6, iclass 34, count 2 2006.201.10:47:14.02#ibcon#end of sib2, iclass 34, count 2 2006.201.10:47:14.02#ibcon#*mode == 0, iclass 34, count 2 2006.201.10:47:14.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.10:47:14.02#ibcon#[25=AT01-08\r\n] 2006.201.10:47:14.02#ibcon#*before write, iclass 34, count 2 2006.201.10:47:14.02#ibcon#enter sib2, iclass 34, count 2 2006.201.10:47:14.02#ibcon#flushed, iclass 34, count 2 2006.201.10:47:14.02#ibcon#about to write, iclass 34, count 2 2006.201.10:47:14.02#ibcon#wrote, iclass 34, count 2 2006.201.10:47:14.02#ibcon#about to read 3, iclass 34, count 2 2006.201.10:47:14.05#ibcon#read 3, iclass 34, count 2 2006.201.10:47:14.05#ibcon#about to read 4, iclass 34, count 2 2006.201.10:47:14.05#ibcon#read 4, iclass 34, count 2 2006.201.10:47:14.05#ibcon#about to read 5, iclass 34, count 2 2006.201.10:47:14.05#ibcon#read 5, iclass 34, count 2 2006.201.10:47:14.05#ibcon#about to read 6, iclass 34, count 2 2006.201.10:47:14.05#ibcon#read 6, iclass 34, count 2 2006.201.10:47:14.05#ibcon#end of sib2, iclass 34, count 2 2006.201.10:47:14.05#ibcon#*after write, iclass 34, count 2 2006.201.10:47:14.05#ibcon#*before return 0, iclass 34, count 2 2006.201.10:47:14.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:14.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:14.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.10:47:14.05#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:14.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:14.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:14.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:14.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:47:14.17#ibcon#first serial, iclass 34, count 0 2006.201.10:47:14.17#ibcon#enter sib2, iclass 34, count 0 2006.201.10:47:14.17#ibcon#flushed, iclass 34, count 0 2006.201.10:47:14.17#ibcon#about to write, iclass 34, count 0 2006.201.10:47:14.17#ibcon#wrote, iclass 34, count 0 2006.201.10:47:14.17#ibcon#about to read 3, iclass 34, count 0 2006.201.10:47:14.19#ibcon#read 3, iclass 34, count 0 2006.201.10:47:14.19#ibcon#about to read 4, iclass 34, count 0 2006.201.10:47:14.19#ibcon#read 4, iclass 34, count 0 2006.201.10:47:14.19#ibcon#about to read 5, iclass 34, count 0 2006.201.10:47:14.19#ibcon#read 5, iclass 34, count 0 2006.201.10:47:14.19#ibcon#about to read 6, iclass 34, count 0 2006.201.10:47:14.19#ibcon#read 6, iclass 34, count 0 2006.201.10:47:14.19#ibcon#end of sib2, iclass 34, count 0 2006.201.10:47:14.19#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:47:14.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:47:14.19#ibcon#[25=USB\r\n] 2006.201.10:47:14.19#ibcon#*before write, iclass 34, count 0 2006.201.10:47:14.19#ibcon#enter sib2, iclass 34, count 0 2006.201.10:47:14.19#ibcon#flushed, iclass 34, count 0 2006.201.10:47:14.19#ibcon#about to write, iclass 34, count 0 2006.201.10:47:14.19#ibcon#wrote, iclass 34, count 0 2006.201.10:47:14.19#ibcon#about to read 3, iclass 34, count 0 2006.201.10:47:14.22#ibcon#read 3, iclass 34, count 0 2006.201.10:47:14.22#ibcon#about to read 4, iclass 34, count 0 2006.201.10:47:14.22#ibcon#read 4, iclass 34, count 0 2006.201.10:47:14.22#ibcon#about to read 5, iclass 34, count 0 2006.201.10:47:14.22#ibcon#read 5, iclass 34, count 0 2006.201.10:47:14.22#ibcon#about to read 6, iclass 34, count 0 2006.201.10:47:14.22#ibcon#read 6, iclass 34, count 0 2006.201.10:47:14.22#ibcon#end of sib2, iclass 34, count 0 2006.201.10:47:14.22#ibcon#*after write, iclass 34, count 0 2006.201.10:47:14.22#ibcon#*before return 0, iclass 34, count 0 2006.201.10:47:14.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:14.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:14.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:47:14.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:47:14.22$vck44/valo=2,534.99 2006.201.10:47:14.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.10:47:14.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.10:47:14.22#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:14.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:14.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:14.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:14.22#ibcon#enter wrdev, iclass 36, count 0 2006.201.10:47:14.22#ibcon#first serial, iclass 36, count 0 2006.201.10:47:14.22#ibcon#enter sib2, iclass 36, count 0 2006.201.10:47:14.22#ibcon#flushed, iclass 36, count 0 2006.201.10:47:14.22#ibcon#about to write, iclass 36, count 0 2006.201.10:47:14.22#ibcon#wrote, iclass 36, count 0 2006.201.10:47:14.22#ibcon#about to read 3, iclass 36, count 0 2006.201.10:47:14.24#ibcon#read 3, iclass 36, count 0 2006.201.10:47:14.24#ibcon#about to read 4, iclass 36, count 0 2006.201.10:47:14.24#ibcon#read 4, iclass 36, count 0 2006.201.10:47:14.24#ibcon#about to read 5, iclass 36, count 0 2006.201.10:47:14.24#ibcon#read 5, iclass 36, count 0 2006.201.10:47:14.24#ibcon#about to read 6, iclass 36, count 0 2006.201.10:47:14.24#ibcon#read 6, iclass 36, count 0 2006.201.10:47:14.24#ibcon#end of sib2, iclass 36, count 0 2006.201.10:47:14.24#ibcon#*mode == 0, iclass 36, count 0 2006.201.10:47:14.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.10:47:14.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:47:14.24#ibcon#*before write, iclass 36, count 0 2006.201.10:47:14.24#ibcon#enter sib2, iclass 36, count 0 2006.201.10:47:14.24#ibcon#flushed, iclass 36, count 0 2006.201.10:47:14.24#ibcon#about to write, iclass 36, count 0 2006.201.10:47:14.24#ibcon#wrote, iclass 36, count 0 2006.201.10:47:14.24#ibcon#about to read 3, iclass 36, count 0 2006.201.10:47:14.28#ibcon#read 3, iclass 36, count 0 2006.201.10:47:14.28#ibcon#about to read 4, iclass 36, count 0 2006.201.10:47:14.28#ibcon#read 4, iclass 36, count 0 2006.201.10:47:14.28#ibcon#about to read 5, iclass 36, count 0 2006.201.10:47:14.28#ibcon#read 5, iclass 36, count 0 2006.201.10:47:14.28#ibcon#about to read 6, iclass 36, count 0 2006.201.10:47:14.28#ibcon#read 6, iclass 36, count 0 2006.201.10:47:14.28#ibcon#end of sib2, iclass 36, count 0 2006.201.10:47:14.28#ibcon#*after write, iclass 36, count 0 2006.201.10:47:14.28#ibcon#*before return 0, iclass 36, count 0 2006.201.10:47:14.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:14.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:14.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.10:47:14.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.10:47:14.28$vck44/va=2,7 2006.201.10:47:14.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.10:47:14.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.10:47:14.28#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:14.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:14.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:14.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:14.34#ibcon#enter wrdev, iclass 38, count 2 2006.201.10:47:14.34#ibcon#first serial, iclass 38, count 2 2006.201.10:47:14.34#ibcon#enter sib2, iclass 38, count 2 2006.201.10:47:14.34#ibcon#flushed, iclass 38, count 2 2006.201.10:47:14.34#ibcon#about to write, iclass 38, count 2 2006.201.10:47:14.34#ibcon#wrote, iclass 38, count 2 2006.201.10:47:14.34#ibcon#about to read 3, iclass 38, count 2 2006.201.10:47:14.36#ibcon#read 3, iclass 38, count 2 2006.201.10:47:14.36#ibcon#about to read 4, iclass 38, count 2 2006.201.10:47:14.36#ibcon#read 4, iclass 38, count 2 2006.201.10:47:14.36#ibcon#about to read 5, iclass 38, count 2 2006.201.10:47:14.36#ibcon#read 5, iclass 38, count 2 2006.201.10:47:14.36#ibcon#about to read 6, iclass 38, count 2 2006.201.10:47:14.36#ibcon#read 6, iclass 38, count 2 2006.201.10:47:14.36#ibcon#end of sib2, iclass 38, count 2 2006.201.10:47:14.36#ibcon#*mode == 0, iclass 38, count 2 2006.201.10:47:14.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.10:47:14.36#ibcon#[25=AT02-07\r\n] 2006.201.10:47:14.36#ibcon#*before write, iclass 38, count 2 2006.201.10:47:14.36#ibcon#enter sib2, iclass 38, count 2 2006.201.10:47:14.36#ibcon#flushed, iclass 38, count 2 2006.201.10:47:14.36#ibcon#about to write, iclass 38, count 2 2006.201.10:47:14.36#ibcon#wrote, iclass 38, count 2 2006.201.10:47:14.36#ibcon#about to read 3, iclass 38, count 2 2006.201.10:47:14.39#ibcon#read 3, iclass 38, count 2 2006.201.10:47:14.39#ibcon#about to read 4, iclass 38, count 2 2006.201.10:47:14.39#ibcon#read 4, iclass 38, count 2 2006.201.10:47:14.39#ibcon#about to read 5, iclass 38, count 2 2006.201.10:47:14.39#ibcon#read 5, iclass 38, count 2 2006.201.10:47:14.39#ibcon#about to read 6, iclass 38, count 2 2006.201.10:47:14.39#ibcon#read 6, iclass 38, count 2 2006.201.10:47:14.39#ibcon#end of sib2, iclass 38, count 2 2006.201.10:47:14.39#ibcon#*after write, iclass 38, count 2 2006.201.10:47:14.39#ibcon#*before return 0, iclass 38, count 2 2006.201.10:47:14.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:14.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:14.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.10:47:14.39#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:14.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:14.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:14.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:14.51#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:47:14.51#ibcon#first serial, iclass 38, count 0 2006.201.10:47:14.51#ibcon#enter sib2, iclass 38, count 0 2006.201.10:47:14.51#ibcon#flushed, iclass 38, count 0 2006.201.10:47:14.51#ibcon#about to write, iclass 38, count 0 2006.201.10:47:14.51#ibcon#wrote, iclass 38, count 0 2006.201.10:47:14.51#ibcon#about to read 3, iclass 38, count 0 2006.201.10:47:14.53#ibcon#read 3, iclass 38, count 0 2006.201.10:47:14.53#ibcon#about to read 4, iclass 38, count 0 2006.201.10:47:14.53#ibcon#read 4, iclass 38, count 0 2006.201.10:47:14.53#ibcon#about to read 5, iclass 38, count 0 2006.201.10:47:14.53#ibcon#read 5, iclass 38, count 0 2006.201.10:47:14.53#ibcon#about to read 6, iclass 38, count 0 2006.201.10:47:14.53#ibcon#read 6, iclass 38, count 0 2006.201.10:47:14.53#ibcon#end of sib2, iclass 38, count 0 2006.201.10:47:14.53#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:47:14.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:47:14.53#ibcon#[25=USB\r\n] 2006.201.10:47:14.53#ibcon#*before write, iclass 38, count 0 2006.201.10:47:14.53#ibcon#enter sib2, iclass 38, count 0 2006.201.10:47:14.53#ibcon#flushed, iclass 38, count 0 2006.201.10:47:14.53#ibcon#about to write, iclass 38, count 0 2006.201.10:47:14.53#ibcon#wrote, iclass 38, count 0 2006.201.10:47:14.53#ibcon#about to read 3, iclass 38, count 0 2006.201.10:47:14.56#ibcon#read 3, iclass 38, count 0 2006.201.10:47:14.56#ibcon#about to read 4, iclass 38, count 0 2006.201.10:47:14.56#ibcon#read 4, iclass 38, count 0 2006.201.10:47:14.56#ibcon#about to read 5, iclass 38, count 0 2006.201.10:47:14.56#ibcon#read 5, iclass 38, count 0 2006.201.10:47:14.56#ibcon#about to read 6, iclass 38, count 0 2006.201.10:47:14.56#ibcon#read 6, iclass 38, count 0 2006.201.10:47:14.56#ibcon#end of sib2, iclass 38, count 0 2006.201.10:47:14.56#ibcon#*after write, iclass 38, count 0 2006.201.10:47:14.56#ibcon#*before return 0, iclass 38, count 0 2006.201.10:47:14.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:14.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:14.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:47:14.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:47:14.56$vck44/valo=3,564.99 2006.201.10:47:14.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.10:47:14.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.10:47:14.56#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:14.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:14.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:14.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:14.56#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:47:14.56#ibcon#first serial, iclass 40, count 0 2006.201.10:47:14.56#ibcon#enter sib2, iclass 40, count 0 2006.201.10:47:14.56#ibcon#flushed, iclass 40, count 0 2006.201.10:47:14.56#ibcon#about to write, iclass 40, count 0 2006.201.10:47:14.56#ibcon#wrote, iclass 40, count 0 2006.201.10:47:14.56#ibcon#about to read 3, iclass 40, count 0 2006.201.10:47:14.58#ibcon#read 3, iclass 40, count 0 2006.201.10:47:14.58#ibcon#about to read 4, iclass 40, count 0 2006.201.10:47:14.58#ibcon#read 4, iclass 40, count 0 2006.201.10:47:14.58#ibcon#about to read 5, iclass 40, count 0 2006.201.10:47:14.58#ibcon#read 5, iclass 40, count 0 2006.201.10:47:14.58#ibcon#about to read 6, iclass 40, count 0 2006.201.10:47:14.58#ibcon#read 6, iclass 40, count 0 2006.201.10:47:14.58#ibcon#end of sib2, iclass 40, count 0 2006.201.10:47:14.58#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:47:14.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:47:14.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:47:14.58#ibcon#*before write, iclass 40, count 0 2006.201.10:47:14.58#ibcon#enter sib2, iclass 40, count 0 2006.201.10:47:14.58#ibcon#flushed, iclass 40, count 0 2006.201.10:47:14.58#ibcon#about to write, iclass 40, count 0 2006.201.10:47:14.58#ibcon#wrote, iclass 40, count 0 2006.201.10:47:14.58#ibcon#about to read 3, iclass 40, count 0 2006.201.10:47:14.63#ibcon#read 3, iclass 40, count 0 2006.201.10:47:14.63#ibcon#about to read 4, iclass 40, count 0 2006.201.10:47:14.63#ibcon#read 4, iclass 40, count 0 2006.201.10:47:14.63#ibcon#about to read 5, iclass 40, count 0 2006.201.10:47:14.63#ibcon#read 5, iclass 40, count 0 2006.201.10:47:14.63#ibcon#about to read 6, iclass 40, count 0 2006.201.10:47:14.63#ibcon#read 6, iclass 40, count 0 2006.201.10:47:14.63#ibcon#end of sib2, iclass 40, count 0 2006.201.10:47:14.63#ibcon#*after write, iclass 40, count 0 2006.201.10:47:14.63#ibcon#*before return 0, iclass 40, count 0 2006.201.10:47:14.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:14.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:14.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:47:14.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:47:14.63$vck44/va=3,8 2006.201.10:47:14.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.10:47:14.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.10:47:14.63#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:14.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:14.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:14.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:14.68#ibcon#enter wrdev, iclass 4, count 2 2006.201.10:47:14.68#ibcon#first serial, iclass 4, count 2 2006.201.10:47:14.68#ibcon#enter sib2, iclass 4, count 2 2006.201.10:47:14.68#ibcon#flushed, iclass 4, count 2 2006.201.10:47:14.68#ibcon#about to write, iclass 4, count 2 2006.201.10:47:14.68#ibcon#wrote, iclass 4, count 2 2006.201.10:47:14.68#ibcon#about to read 3, iclass 4, count 2 2006.201.10:47:14.70#ibcon#read 3, iclass 4, count 2 2006.201.10:47:14.70#ibcon#about to read 4, iclass 4, count 2 2006.201.10:47:14.70#ibcon#read 4, iclass 4, count 2 2006.201.10:47:14.70#ibcon#about to read 5, iclass 4, count 2 2006.201.10:47:14.70#ibcon#read 5, iclass 4, count 2 2006.201.10:47:14.70#ibcon#about to read 6, iclass 4, count 2 2006.201.10:47:14.70#ibcon#read 6, iclass 4, count 2 2006.201.10:47:14.70#ibcon#end of sib2, iclass 4, count 2 2006.201.10:47:14.70#ibcon#*mode == 0, iclass 4, count 2 2006.201.10:47:14.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.10:47:14.70#ibcon#[25=AT03-08\r\n] 2006.201.10:47:14.70#ibcon#*before write, iclass 4, count 2 2006.201.10:47:14.70#ibcon#enter sib2, iclass 4, count 2 2006.201.10:47:14.70#ibcon#flushed, iclass 4, count 2 2006.201.10:47:14.70#ibcon#about to write, iclass 4, count 2 2006.201.10:47:14.70#ibcon#wrote, iclass 4, count 2 2006.201.10:47:14.70#ibcon#about to read 3, iclass 4, count 2 2006.201.10:47:14.73#ibcon#read 3, iclass 4, count 2 2006.201.10:47:14.73#ibcon#about to read 4, iclass 4, count 2 2006.201.10:47:14.73#ibcon#read 4, iclass 4, count 2 2006.201.10:47:14.73#ibcon#about to read 5, iclass 4, count 2 2006.201.10:47:14.73#ibcon#read 5, iclass 4, count 2 2006.201.10:47:14.73#ibcon#about to read 6, iclass 4, count 2 2006.201.10:47:14.73#ibcon#read 6, iclass 4, count 2 2006.201.10:47:14.73#ibcon#end of sib2, iclass 4, count 2 2006.201.10:47:14.73#ibcon#*after write, iclass 4, count 2 2006.201.10:47:14.73#ibcon#*before return 0, iclass 4, count 2 2006.201.10:47:14.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:14.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:14.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.10:47:14.73#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:14.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:14.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:14.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:14.85#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:47:14.85#ibcon#first serial, iclass 4, count 0 2006.201.10:47:14.85#ibcon#enter sib2, iclass 4, count 0 2006.201.10:47:14.85#ibcon#flushed, iclass 4, count 0 2006.201.10:47:14.85#ibcon#about to write, iclass 4, count 0 2006.201.10:47:14.85#ibcon#wrote, iclass 4, count 0 2006.201.10:47:14.85#ibcon#about to read 3, iclass 4, count 0 2006.201.10:47:14.87#ibcon#read 3, iclass 4, count 0 2006.201.10:47:14.87#ibcon#about to read 4, iclass 4, count 0 2006.201.10:47:14.87#ibcon#read 4, iclass 4, count 0 2006.201.10:47:14.87#ibcon#about to read 5, iclass 4, count 0 2006.201.10:47:14.87#ibcon#read 5, iclass 4, count 0 2006.201.10:47:14.87#ibcon#about to read 6, iclass 4, count 0 2006.201.10:47:14.87#ibcon#read 6, iclass 4, count 0 2006.201.10:47:14.87#ibcon#end of sib2, iclass 4, count 0 2006.201.10:47:14.87#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:47:14.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:47:14.87#ibcon#[25=USB\r\n] 2006.201.10:47:14.87#ibcon#*before write, iclass 4, count 0 2006.201.10:47:14.87#ibcon#enter sib2, iclass 4, count 0 2006.201.10:47:14.87#ibcon#flushed, iclass 4, count 0 2006.201.10:47:14.87#ibcon#about to write, iclass 4, count 0 2006.201.10:47:14.87#ibcon#wrote, iclass 4, count 0 2006.201.10:47:14.87#ibcon#about to read 3, iclass 4, count 0 2006.201.10:47:14.90#ibcon#read 3, iclass 4, count 0 2006.201.10:47:14.90#ibcon#about to read 4, iclass 4, count 0 2006.201.10:47:14.90#ibcon#read 4, iclass 4, count 0 2006.201.10:47:14.90#ibcon#about to read 5, iclass 4, count 0 2006.201.10:47:14.90#ibcon#read 5, iclass 4, count 0 2006.201.10:47:14.90#ibcon#about to read 6, iclass 4, count 0 2006.201.10:47:14.90#ibcon#read 6, iclass 4, count 0 2006.201.10:47:14.90#ibcon#end of sib2, iclass 4, count 0 2006.201.10:47:14.90#ibcon#*after write, iclass 4, count 0 2006.201.10:47:14.90#ibcon#*before return 0, iclass 4, count 0 2006.201.10:47:14.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:14.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:14.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:47:14.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:47:14.90$vck44/valo=4,624.99 2006.201.10:47:14.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.10:47:14.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.10:47:14.90#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:14.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:14.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:14.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:14.90#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:47:14.90#ibcon#first serial, iclass 6, count 0 2006.201.10:47:14.90#ibcon#enter sib2, iclass 6, count 0 2006.201.10:47:14.90#ibcon#flushed, iclass 6, count 0 2006.201.10:47:14.90#ibcon#about to write, iclass 6, count 0 2006.201.10:47:14.90#ibcon#wrote, iclass 6, count 0 2006.201.10:47:14.90#ibcon#about to read 3, iclass 6, count 0 2006.201.10:47:14.92#ibcon#read 3, iclass 6, count 0 2006.201.10:47:14.92#ibcon#about to read 4, iclass 6, count 0 2006.201.10:47:14.92#ibcon#read 4, iclass 6, count 0 2006.201.10:47:14.92#ibcon#about to read 5, iclass 6, count 0 2006.201.10:47:14.92#ibcon#read 5, iclass 6, count 0 2006.201.10:47:14.92#ibcon#about to read 6, iclass 6, count 0 2006.201.10:47:14.92#ibcon#read 6, iclass 6, count 0 2006.201.10:47:14.92#ibcon#end of sib2, iclass 6, count 0 2006.201.10:47:14.92#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:47:14.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:47:14.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:47:14.92#ibcon#*before write, iclass 6, count 0 2006.201.10:47:14.92#ibcon#enter sib2, iclass 6, count 0 2006.201.10:47:14.92#ibcon#flushed, iclass 6, count 0 2006.201.10:47:14.92#ibcon#about to write, iclass 6, count 0 2006.201.10:47:14.92#ibcon#wrote, iclass 6, count 0 2006.201.10:47:14.92#ibcon#about to read 3, iclass 6, count 0 2006.201.10:47:14.97#ibcon#read 3, iclass 6, count 0 2006.201.10:47:14.97#ibcon#about to read 4, iclass 6, count 0 2006.201.10:47:14.97#ibcon#read 4, iclass 6, count 0 2006.201.10:47:14.97#ibcon#about to read 5, iclass 6, count 0 2006.201.10:47:14.97#ibcon#read 5, iclass 6, count 0 2006.201.10:47:14.97#ibcon#about to read 6, iclass 6, count 0 2006.201.10:47:14.97#ibcon#read 6, iclass 6, count 0 2006.201.10:47:14.97#ibcon#end of sib2, iclass 6, count 0 2006.201.10:47:14.97#ibcon#*after write, iclass 6, count 0 2006.201.10:47:14.97#ibcon#*before return 0, iclass 6, count 0 2006.201.10:47:14.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:14.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:14.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:47:14.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:47:14.97$vck44/va=4,7 2006.201.10:47:14.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.10:47:14.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.10:47:14.97#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:14.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:15.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:15.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:15.02#ibcon#enter wrdev, iclass 10, count 2 2006.201.10:47:15.02#ibcon#first serial, iclass 10, count 2 2006.201.10:47:15.02#ibcon#enter sib2, iclass 10, count 2 2006.201.10:47:15.02#ibcon#flushed, iclass 10, count 2 2006.201.10:47:15.02#ibcon#about to write, iclass 10, count 2 2006.201.10:47:15.02#ibcon#wrote, iclass 10, count 2 2006.201.10:47:15.02#ibcon#about to read 3, iclass 10, count 2 2006.201.10:47:15.04#ibcon#read 3, iclass 10, count 2 2006.201.10:47:15.04#ibcon#about to read 4, iclass 10, count 2 2006.201.10:47:15.04#ibcon#read 4, iclass 10, count 2 2006.201.10:47:15.04#ibcon#about to read 5, iclass 10, count 2 2006.201.10:47:15.04#ibcon#read 5, iclass 10, count 2 2006.201.10:47:15.04#ibcon#about to read 6, iclass 10, count 2 2006.201.10:47:15.04#ibcon#read 6, iclass 10, count 2 2006.201.10:47:15.04#ibcon#end of sib2, iclass 10, count 2 2006.201.10:47:15.04#ibcon#*mode == 0, iclass 10, count 2 2006.201.10:47:15.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.10:47:15.04#ibcon#[25=AT04-07\r\n] 2006.201.10:47:15.04#ibcon#*before write, iclass 10, count 2 2006.201.10:47:15.04#ibcon#enter sib2, iclass 10, count 2 2006.201.10:47:15.04#ibcon#flushed, iclass 10, count 2 2006.201.10:47:15.04#ibcon#about to write, iclass 10, count 2 2006.201.10:47:15.04#ibcon#wrote, iclass 10, count 2 2006.201.10:47:15.04#ibcon#about to read 3, iclass 10, count 2 2006.201.10:47:15.07#ibcon#read 3, iclass 10, count 2 2006.201.10:47:15.07#ibcon#about to read 4, iclass 10, count 2 2006.201.10:47:15.07#ibcon#read 4, iclass 10, count 2 2006.201.10:47:15.07#ibcon#about to read 5, iclass 10, count 2 2006.201.10:47:15.07#ibcon#read 5, iclass 10, count 2 2006.201.10:47:15.07#ibcon#about to read 6, iclass 10, count 2 2006.201.10:47:15.07#ibcon#read 6, iclass 10, count 2 2006.201.10:47:15.07#ibcon#end of sib2, iclass 10, count 2 2006.201.10:47:15.07#ibcon#*after write, iclass 10, count 2 2006.201.10:47:15.07#ibcon#*before return 0, iclass 10, count 2 2006.201.10:47:15.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:15.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:15.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.10:47:15.07#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:15.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:15.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:15.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:15.19#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:47:15.19#ibcon#first serial, iclass 10, count 0 2006.201.10:47:15.19#ibcon#enter sib2, iclass 10, count 0 2006.201.10:47:15.19#ibcon#flushed, iclass 10, count 0 2006.201.10:47:15.19#ibcon#about to write, iclass 10, count 0 2006.201.10:47:15.19#ibcon#wrote, iclass 10, count 0 2006.201.10:47:15.19#ibcon#about to read 3, iclass 10, count 0 2006.201.10:47:15.21#ibcon#read 3, iclass 10, count 0 2006.201.10:47:15.21#ibcon#about to read 4, iclass 10, count 0 2006.201.10:47:15.21#ibcon#read 4, iclass 10, count 0 2006.201.10:47:15.21#ibcon#about to read 5, iclass 10, count 0 2006.201.10:47:15.21#ibcon#read 5, iclass 10, count 0 2006.201.10:47:15.21#ibcon#about to read 6, iclass 10, count 0 2006.201.10:47:15.21#ibcon#read 6, iclass 10, count 0 2006.201.10:47:15.21#ibcon#end of sib2, iclass 10, count 0 2006.201.10:47:15.21#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:47:15.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:47:15.21#ibcon#[25=USB\r\n] 2006.201.10:47:15.21#ibcon#*before write, iclass 10, count 0 2006.201.10:47:15.21#ibcon#enter sib2, iclass 10, count 0 2006.201.10:47:15.21#ibcon#flushed, iclass 10, count 0 2006.201.10:47:15.21#ibcon#about to write, iclass 10, count 0 2006.201.10:47:15.21#ibcon#wrote, iclass 10, count 0 2006.201.10:47:15.21#ibcon#about to read 3, iclass 10, count 0 2006.201.10:47:15.24#ibcon#read 3, iclass 10, count 0 2006.201.10:47:15.24#ibcon#about to read 4, iclass 10, count 0 2006.201.10:47:15.24#ibcon#read 4, iclass 10, count 0 2006.201.10:47:15.24#ibcon#about to read 5, iclass 10, count 0 2006.201.10:47:15.24#ibcon#read 5, iclass 10, count 0 2006.201.10:47:15.24#ibcon#about to read 6, iclass 10, count 0 2006.201.10:47:15.24#ibcon#read 6, iclass 10, count 0 2006.201.10:47:15.24#ibcon#end of sib2, iclass 10, count 0 2006.201.10:47:15.24#ibcon#*after write, iclass 10, count 0 2006.201.10:47:15.24#ibcon#*before return 0, iclass 10, count 0 2006.201.10:47:15.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:15.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:15.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:47:15.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:47:15.24$vck44/valo=5,734.99 2006.201.10:47:15.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.10:47:15.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.10:47:15.24#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:15.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:15.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:15.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:15.24#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:47:15.24#ibcon#first serial, iclass 12, count 0 2006.201.10:47:15.24#ibcon#enter sib2, iclass 12, count 0 2006.201.10:47:15.24#ibcon#flushed, iclass 12, count 0 2006.201.10:47:15.24#ibcon#about to write, iclass 12, count 0 2006.201.10:47:15.24#ibcon#wrote, iclass 12, count 0 2006.201.10:47:15.24#ibcon#about to read 3, iclass 12, count 0 2006.201.10:47:15.26#ibcon#read 3, iclass 12, count 0 2006.201.10:47:15.26#ibcon#about to read 4, iclass 12, count 0 2006.201.10:47:15.26#ibcon#read 4, iclass 12, count 0 2006.201.10:47:15.26#ibcon#about to read 5, iclass 12, count 0 2006.201.10:47:15.26#ibcon#read 5, iclass 12, count 0 2006.201.10:47:15.26#ibcon#about to read 6, iclass 12, count 0 2006.201.10:47:15.26#ibcon#read 6, iclass 12, count 0 2006.201.10:47:15.26#ibcon#end of sib2, iclass 12, count 0 2006.201.10:47:15.26#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:47:15.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:47:15.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:47:15.26#ibcon#*before write, iclass 12, count 0 2006.201.10:47:15.26#ibcon#enter sib2, iclass 12, count 0 2006.201.10:47:15.26#ibcon#flushed, iclass 12, count 0 2006.201.10:47:15.26#ibcon#about to write, iclass 12, count 0 2006.201.10:47:15.26#ibcon#wrote, iclass 12, count 0 2006.201.10:47:15.26#ibcon#about to read 3, iclass 12, count 0 2006.201.10:47:15.30#ibcon#read 3, iclass 12, count 0 2006.201.10:47:15.30#ibcon#about to read 4, iclass 12, count 0 2006.201.10:47:15.30#ibcon#read 4, iclass 12, count 0 2006.201.10:47:15.30#ibcon#about to read 5, iclass 12, count 0 2006.201.10:47:15.30#ibcon#read 5, iclass 12, count 0 2006.201.10:47:15.30#ibcon#about to read 6, iclass 12, count 0 2006.201.10:47:15.30#ibcon#read 6, iclass 12, count 0 2006.201.10:47:15.30#ibcon#end of sib2, iclass 12, count 0 2006.201.10:47:15.30#ibcon#*after write, iclass 12, count 0 2006.201.10:47:15.30#ibcon#*before return 0, iclass 12, count 0 2006.201.10:47:15.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:15.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:15.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:47:15.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:47:15.30$vck44/va=5,4 2006.201.10:47:15.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.10:47:15.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.10:47:15.30#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:15.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:15.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:15.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:15.36#ibcon#enter wrdev, iclass 14, count 2 2006.201.10:47:15.36#ibcon#first serial, iclass 14, count 2 2006.201.10:47:15.36#ibcon#enter sib2, iclass 14, count 2 2006.201.10:47:15.36#ibcon#flushed, iclass 14, count 2 2006.201.10:47:15.36#ibcon#about to write, iclass 14, count 2 2006.201.10:47:15.36#ibcon#wrote, iclass 14, count 2 2006.201.10:47:15.36#ibcon#about to read 3, iclass 14, count 2 2006.201.10:47:15.38#ibcon#read 3, iclass 14, count 2 2006.201.10:47:15.38#ibcon#about to read 4, iclass 14, count 2 2006.201.10:47:15.38#ibcon#read 4, iclass 14, count 2 2006.201.10:47:15.38#ibcon#about to read 5, iclass 14, count 2 2006.201.10:47:15.38#ibcon#read 5, iclass 14, count 2 2006.201.10:47:15.38#ibcon#about to read 6, iclass 14, count 2 2006.201.10:47:15.38#ibcon#read 6, iclass 14, count 2 2006.201.10:47:15.38#ibcon#end of sib2, iclass 14, count 2 2006.201.10:47:15.38#ibcon#*mode == 0, iclass 14, count 2 2006.201.10:47:15.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.10:47:15.38#ibcon#[25=AT05-04\r\n] 2006.201.10:47:15.38#ibcon#*before write, iclass 14, count 2 2006.201.10:47:15.38#ibcon#enter sib2, iclass 14, count 2 2006.201.10:47:15.38#ibcon#flushed, iclass 14, count 2 2006.201.10:47:15.38#ibcon#about to write, iclass 14, count 2 2006.201.10:47:15.38#ibcon#wrote, iclass 14, count 2 2006.201.10:47:15.38#ibcon#about to read 3, iclass 14, count 2 2006.201.10:47:15.41#ibcon#read 3, iclass 14, count 2 2006.201.10:47:15.41#ibcon#about to read 4, iclass 14, count 2 2006.201.10:47:15.41#ibcon#read 4, iclass 14, count 2 2006.201.10:47:15.41#ibcon#about to read 5, iclass 14, count 2 2006.201.10:47:15.41#ibcon#read 5, iclass 14, count 2 2006.201.10:47:15.41#ibcon#about to read 6, iclass 14, count 2 2006.201.10:47:15.41#ibcon#read 6, iclass 14, count 2 2006.201.10:47:15.41#ibcon#end of sib2, iclass 14, count 2 2006.201.10:47:15.41#ibcon#*after write, iclass 14, count 2 2006.201.10:47:15.41#ibcon#*before return 0, iclass 14, count 2 2006.201.10:47:15.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:15.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:15.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.10:47:15.41#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:15.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:15.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:15.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:15.53#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:47:15.53#ibcon#first serial, iclass 14, count 0 2006.201.10:47:15.53#ibcon#enter sib2, iclass 14, count 0 2006.201.10:47:15.53#ibcon#flushed, iclass 14, count 0 2006.201.10:47:15.53#ibcon#about to write, iclass 14, count 0 2006.201.10:47:15.53#ibcon#wrote, iclass 14, count 0 2006.201.10:47:15.53#ibcon#about to read 3, iclass 14, count 0 2006.201.10:47:15.55#ibcon#read 3, iclass 14, count 0 2006.201.10:47:15.55#ibcon#about to read 4, iclass 14, count 0 2006.201.10:47:15.55#ibcon#read 4, iclass 14, count 0 2006.201.10:47:15.55#ibcon#about to read 5, iclass 14, count 0 2006.201.10:47:15.55#ibcon#read 5, iclass 14, count 0 2006.201.10:47:15.55#ibcon#about to read 6, iclass 14, count 0 2006.201.10:47:15.55#ibcon#read 6, iclass 14, count 0 2006.201.10:47:15.55#ibcon#end of sib2, iclass 14, count 0 2006.201.10:47:15.55#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:47:15.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:47:15.55#ibcon#[25=USB\r\n] 2006.201.10:47:15.55#ibcon#*before write, iclass 14, count 0 2006.201.10:47:15.55#ibcon#enter sib2, iclass 14, count 0 2006.201.10:47:15.55#ibcon#flushed, iclass 14, count 0 2006.201.10:47:15.55#ibcon#about to write, iclass 14, count 0 2006.201.10:47:15.55#ibcon#wrote, iclass 14, count 0 2006.201.10:47:15.55#ibcon#about to read 3, iclass 14, count 0 2006.201.10:47:15.58#ibcon#read 3, iclass 14, count 0 2006.201.10:47:15.58#ibcon#about to read 4, iclass 14, count 0 2006.201.10:47:15.58#ibcon#read 4, iclass 14, count 0 2006.201.10:47:15.58#ibcon#about to read 5, iclass 14, count 0 2006.201.10:47:15.58#ibcon#read 5, iclass 14, count 0 2006.201.10:47:15.58#ibcon#about to read 6, iclass 14, count 0 2006.201.10:47:15.58#ibcon#read 6, iclass 14, count 0 2006.201.10:47:15.58#ibcon#end of sib2, iclass 14, count 0 2006.201.10:47:15.58#ibcon#*after write, iclass 14, count 0 2006.201.10:47:15.58#ibcon#*before return 0, iclass 14, count 0 2006.201.10:47:15.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:15.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:15.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:47:15.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:47:15.58$vck44/valo=6,814.99 2006.201.10:47:15.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.10:47:15.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.10:47:15.58#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:15.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:47:15.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:47:15.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:47:15.58#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:47:15.58#ibcon#first serial, iclass 16, count 0 2006.201.10:47:15.58#ibcon#enter sib2, iclass 16, count 0 2006.201.10:47:15.58#ibcon#flushed, iclass 16, count 0 2006.201.10:47:15.58#ibcon#about to write, iclass 16, count 0 2006.201.10:47:15.58#ibcon#wrote, iclass 16, count 0 2006.201.10:47:15.58#ibcon#about to read 3, iclass 16, count 0 2006.201.10:47:15.60#ibcon#read 3, iclass 16, count 0 2006.201.10:47:15.60#ibcon#about to read 4, iclass 16, count 0 2006.201.10:47:15.60#ibcon#read 4, iclass 16, count 0 2006.201.10:47:15.60#ibcon#about to read 5, iclass 16, count 0 2006.201.10:47:15.60#ibcon#read 5, iclass 16, count 0 2006.201.10:47:15.60#ibcon#about to read 6, iclass 16, count 0 2006.201.10:47:15.60#ibcon#read 6, iclass 16, count 0 2006.201.10:47:15.60#ibcon#end of sib2, iclass 16, count 0 2006.201.10:47:15.60#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:47:15.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:47:15.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:47:15.60#ibcon#*before write, iclass 16, count 0 2006.201.10:47:15.60#ibcon#enter sib2, iclass 16, count 0 2006.201.10:47:15.60#ibcon#flushed, iclass 16, count 0 2006.201.10:47:15.60#ibcon#about to write, iclass 16, count 0 2006.201.10:47:15.60#ibcon#wrote, iclass 16, count 0 2006.201.10:47:15.60#ibcon#about to read 3, iclass 16, count 0 2006.201.10:47:15.65#ibcon#read 3, iclass 16, count 0 2006.201.10:47:15.65#ibcon#about to read 4, iclass 16, count 0 2006.201.10:47:15.65#ibcon#read 4, iclass 16, count 0 2006.201.10:47:15.65#ibcon#about to read 5, iclass 16, count 0 2006.201.10:47:15.65#ibcon#read 5, iclass 16, count 0 2006.201.10:47:15.65#ibcon#about to read 6, iclass 16, count 0 2006.201.10:47:15.65#ibcon#read 6, iclass 16, count 0 2006.201.10:47:15.65#ibcon#end of sib2, iclass 16, count 0 2006.201.10:47:15.65#ibcon#*after write, iclass 16, count 0 2006.201.10:47:15.65#ibcon#*before return 0, iclass 16, count 0 2006.201.10:47:15.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:47:15.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.10:47:15.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:47:15.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:47:15.65$vck44/va=6,5 2006.201.10:47:15.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.10:47:15.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.10:47:15.65#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:15.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:47:15.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:47:15.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:47:15.70#ibcon#enter wrdev, iclass 18, count 2 2006.201.10:47:15.70#ibcon#first serial, iclass 18, count 2 2006.201.10:47:15.70#ibcon#enter sib2, iclass 18, count 2 2006.201.10:47:15.70#ibcon#flushed, iclass 18, count 2 2006.201.10:47:15.70#ibcon#about to write, iclass 18, count 2 2006.201.10:47:15.70#ibcon#wrote, iclass 18, count 2 2006.201.10:47:15.70#ibcon#about to read 3, iclass 18, count 2 2006.201.10:47:15.72#ibcon#read 3, iclass 18, count 2 2006.201.10:47:15.72#ibcon#about to read 4, iclass 18, count 2 2006.201.10:47:15.72#ibcon#read 4, iclass 18, count 2 2006.201.10:47:15.72#ibcon#about to read 5, iclass 18, count 2 2006.201.10:47:15.72#ibcon#read 5, iclass 18, count 2 2006.201.10:47:15.72#ibcon#about to read 6, iclass 18, count 2 2006.201.10:47:15.72#ibcon#read 6, iclass 18, count 2 2006.201.10:47:15.72#ibcon#end of sib2, iclass 18, count 2 2006.201.10:47:15.72#ibcon#*mode == 0, iclass 18, count 2 2006.201.10:47:15.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.10:47:15.72#ibcon#[25=AT06-05\r\n] 2006.201.10:47:15.72#ibcon#*before write, iclass 18, count 2 2006.201.10:47:15.72#ibcon#enter sib2, iclass 18, count 2 2006.201.10:47:15.72#ibcon#flushed, iclass 18, count 2 2006.201.10:47:15.72#ibcon#about to write, iclass 18, count 2 2006.201.10:47:15.72#ibcon#wrote, iclass 18, count 2 2006.201.10:47:15.72#ibcon#about to read 3, iclass 18, count 2 2006.201.10:47:15.75#ibcon#read 3, iclass 18, count 2 2006.201.10:47:15.75#ibcon#about to read 4, iclass 18, count 2 2006.201.10:47:15.75#ibcon#read 4, iclass 18, count 2 2006.201.10:47:15.75#ibcon#about to read 5, iclass 18, count 2 2006.201.10:47:15.75#ibcon#read 5, iclass 18, count 2 2006.201.10:47:15.75#ibcon#about to read 6, iclass 18, count 2 2006.201.10:47:15.75#ibcon#read 6, iclass 18, count 2 2006.201.10:47:15.75#ibcon#end of sib2, iclass 18, count 2 2006.201.10:47:15.75#ibcon#*after write, iclass 18, count 2 2006.201.10:47:15.75#ibcon#*before return 0, iclass 18, count 2 2006.201.10:47:15.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:47:15.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.10:47:15.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.10:47:15.75#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:15.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:47:15.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:47:15.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:47:15.87#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:47:15.87#ibcon#first serial, iclass 18, count 0 2006.201.10:47:15.87#ibcon#enter sib2, iclass 18, count 0 2006.201.10:47:15.87#ibcon#flushed, iclass 18, count 0 2006.201.10:47:15.87#ibcon#about to write, iclass 18, count 0 2006.201.10:47:15.87#ibcon#wrote, iclass 18, count 0 2006.201.10:47:15.87#ibcon#about to read 3, iclass 18, count 0 2006.201.10:47:15.89#ibcon#read 3, iclass 18, count 0 2006.201.10:47:15.89#ibcon#about to read 4, iclass 18, count 0 2006.201.10:47:15.89#ibcon#read 4, iclass 18, count 0 2006.201.10:47:15.89#ibcon#about to read 5, iclass 18, count 0 2006.201.10:47:15.89#ibcon#read 5, iclass 18, count 0 2006.201.10:47:15.89#ibcon#about to read 6, iclass 18, count 0 2006.201.10:47:15.89#ibcon#read 6, iclass 18, count 0 2006.201.10:47:15.89#ibcon#end of sib2, iclass 18, count 0 2006.201.10:47:15.89#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:47:15.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:47:15.89#ibcon#[25=USB\r\n] 2006.201.10:47:15.89#ibcon#*before write, iclass 18, count 0 2006.201.10:47:15.89#ibcon#enter sib2, iclass 18, count 0 2006.201.10:47:15.89#ibcon#flushed, iclass 18, count 0 2006.201.10:47:15.89#ibcon#about to write, iclass 18, count 0 2006.201.10:47:15.89#ibcon#wrote, iclass 18, count 0 2006.201.10:47:15.89#ibcon#about to read 3, iclass 18, count 0 2006.201.10:47:15.92#ibcon#read 3, iclass 18, count 0 2006.201.10:47:15.92#ibcon#about to read 4, iclass 18, count 0 2006.201.10:47:15.92#ibcon#read 4, iclass 18, count 0 2006.201.10:47:15.92#ibcon#about to read 5, iclass 18, count 0 2006.201.10:47:15.92#ibcon#read 5, iclass 18, count 0 2006.201.10:47:15.92#ibcon#about to read 6, iclass 18, count 0 2006.201.10:47:15.92#ibcon#read 6, iclass 18, count 0 2006.201.10:47:15.92#ibcon#end of sib2, iclass 18, count 0 2006.201.10:47:15.92#ibcon#*after write, iclass 18, count 0 2006.201.10:47:15.92#ibcon#*before return 0, iclass 18, count 0 2006.201.10:47:15.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:47:15.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.10:47:15.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:47:15.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:47:15.92$vck44/valo=7,864.99 2006.201.10:47:15.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.10:47:15.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.10:47:15.92#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:15.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:15.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:15.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:15.92#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:47:15.92#ibcon#first serial, iclass 20, count 0 2006.201.10:47:15.92#ibcon#enter sib2, iclass 20, count 0 2006.201.10:47:15.92#ibcon#flushed, iclass 20, count 0 2006.201.10:47:15.92#ibcon#about to write, iclass 20, count 0 2006.201.10:47:15.92#ibcon#wrote, iclass 20, count 0 2006.201.10:47:15.92#ibcon#about to read 3, iclass 20, count 0 2006.201.10:47:15.94#ibcon#read 3, iclass 20, count 0 2006.201.10:47:15.94#ibcon#about to read 4, iclass 20, count 0 2006.201.10:47:15.94#ibcon#read 4, iclass 20, count 0 2006.201.10:47:15.94#ibcon#about to read 5, iclass 20, count 0 2006.201.10:47:15.94#ibcon#read 5, iclass 20, count 0 2006.201.10:47:15.94#ibcon#about to read 6, iclass 20, count 0 2006.201.10:47:15.94#ibcon#read 6, iclass 20, count 0 2006.201.10:47:15.94#ibcon#end of sib2, iclass 20, count 0 2006.201.10:47:15.94#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:47:15.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:47:15.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:47:15.94#ibcon#*before write, iclass 20, count 0 2006.201.10:47:15.94#ibcon#enter sib2, iclass 20, count 0 2006.201.10:47:15.94#ibcon#flushed, iclass 20, count 0 2006.201.10:47:15.94#ibcon#about to write, iclass 20, count 0 2006.201.10:47:15.94#ibcon#wrote, iclass 20, count 0 2006.201.10:47:15.94#ibcon#about to read 3, iclass 20, count 0 2006.201.10:47:15.98#ibcon#read 3, iclass 20, count 0 2006.201.10:47:15.98#ibcon#about to read 4, iclass 20, count 0 2006.201.10:47:15.98#ibcon#read 4, iclass 20, count 0 2006.201.10:47:15.98#ibcon#about to read 5, iclass 20, count 0 2006.201.10:47:15.98#ibcon#read 5, iclass 20, count 0 2006.201.10:47:15.98#ibcon#about to read 6, iclass 20, count 0 2006.201.10:47:15.98#ibcon#read 6, iclass 20, count 0 2006.201.10:47:15.98#ibcon#end of sib2, iclass 20, count 0 2006.201.10:47:15.98#ibcon#*after write, iclass 20, count 0 2006.201.10:47:15.98#ibcon#*before return 0, iclass 20, count 0 2006.201.10:47:15.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:15.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:15.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:47:15.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:47:15.98$vck44/va=7,5 2006.201.10:47:15.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.10:47:15.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.10:47:15.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:15.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:16.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:16.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:16.04#ibcon#enter wrdev, iclass 22, count 2 2006.201.10:47:16.04#ibcon#first serial, iclass 22, count 2 2006.201.10:47:16.04#ibcon#enter sib2, iclass 22, count 2 2006.201.10:47:16.04#ibcon#flushed, iclass 22, count 2 2006.201.10:47:16.04#ibcon#about to write, iclass 22, count 2 2006.201.10:47:16.04#ibcon#wrote, iclass 22, count 2 2006.201.10:47:16.04#ibcon#about to read 3, iclass 22, count 2 2006.201.10:47:16.06#ibcon#read 3, iclass 22, count 2 2006.201.10:47:16.06#ibcon#about to read 4, iclass 22, count 2 2006.201.10:47:16.06#ibcon#read 4, iclass 22, count 2 2006.201.10:47:16.06#ibcon#about to read 5, iclass 22, count 2 2006.201.10:47:16.06#ibcon#read 5, iclass 22, count 2 2006.201.10:47:16.06#ibcon#about to read 6, iclass 22, count 2 2006.201.10:47:16.06#ibcon#read 6, iclass 22, count 2 2006.201.10:47:16.06#ibcon#end of sib2, iclass 22, count 2 2006.201.10:47:16.06#ibcon#*mode == 0, iclass 22, count 2 2006.201.10:47:16.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.10:47:16.06#ibcon#[25=AT07-05\r\n] 2006.201.10:47:16.06#ibcon#*before write, iclass 22, count 2 2006.201.10:47:16.06#ibcon#enter sib2, iclass 22, count 2 2006.201.10:47:16.06#ibcon#flushed, iclass 22, count 2 2006.201.10:47:16.06#ibcon#about to write, iclass 22, count 2 2006.201.10:47:16.06#ibcon#wrote, iclass 22, count 2 2006.201.10:47:16.06#ibcon#about to read 3, iclass 22, count 2 2006.201.10:47:16.09#ibcon#read 3, iclass 22, count 2 2006.201.10:47:16.09#ibcon#about to read 4, iclass 22, count 2 2006.201.10:47:16.09#ibcon#read 4, iclass 22, count 2 2006.201.10:47:16.09#ibcon#about to read 5, iclass 22, count 2 2006.201.10:47:16.09#ibcon#read 5, iclass 22, count 2 2006.201.10:47:16.09#ibcon#about to read 6, iclass 22, count 2 2006.201.10:47:16.09#ibcon#read 6, iclass 22, count 2 2006.201.10:47:16.09#ibcon#end of sib2, iclass 22, count 2 2006.201.10:47:16.09#ibcon#*after write, iclass 22, count 2 2006.201.10:47:16.09#ibcon#*before return 0, iclass 22, count 2 2006.201.10:47:16.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:16.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:16.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.10:47:16.09#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:16.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:16.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:16.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:16.21#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:47:16.21#ibcon#first serial, iclass 22, count 0 2006.201.10:47:16.21#ibcon#enter sib2, iclass 22, count 0 2006.201.10:47:16.21#ibcon#flushed, iclass 22, count 0 2006.201.10:47:16.21#ibcon#about to write, iclass 22, count 0 2006.201.10:47:16.21#ibcon#wrote, iclass 22, count 0 2006.201.10:47:16.21#ibcon#about to read 3, iclass 22, count 0 2006.201.10:47:16.23#ibcon#read 3, iclass 22, count 0 2006.201.10:47:16.23#ibcon#about to read 4, iclass 22, count 0 2006.201.10:47:16.23#ibcon#read 4, iclass 22, count 0 2006.201.10:47:16.23#ibcon#about to read 5, iclass 22, count 0 2006.201.10:47:16.23#ibcon#read 5, iclass 22, count 0 2006.201.10:47:16.23#ibcon#about to read 6, iclass 22, count 0 2006.201.10:47:16.23#ibcon#read 6, iclass 22, count 0 2006.201.10:47:16.23#ibcon#end of sib2, iclass 22, count 0 2006.201.10:47:16.23#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:47:16.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:47:16.23#ibcon#[25=USB\r\n] 2006.201.10:47:16.23#ibcon#*before write, iclass 22, count 0 2006.201.10:47:16.23#ibcon#enter sib2, iclass 22, count 0 2006.201.10:47:16.23#ibcon#flushed, iclass 22, count 0 2006.201.10:47:16.23#ibcon#about to write, iclass 22, count 0 2006.201.10:47:16.23#ibcon#wrote, iclass 22, count 0 2006.201.10:47:16.23#ibcon#about to read 3, iclass 22, count 0 2006.201.10:47:16.26#ibcon#read 3, iclass 22, count 0 2006.201.10:47:16.26#ibcon#about to read 4, iclass 22, count 0 2006.201.10:47:16.26#ibcon#read 4, iclass 22, count 0 2006.201.10:47:16.26#ibcon#about to read 5, iclass 22, count 0 2006.201.10:47:16.26#ibcon#read 5, iclass 22, count 0 2006.201.10:47:16.26#ibcon#about to read 6, iclass 22, count 0 2006.201.10:47:16.26#ibcon#read 6, iclass 22, count 0 2006.201.10:47:16.26#ibcon#end of sib2, iclass 22, count 0 2006.201.10:47:16.26#ibcon#*after write, iclass 22, count 0 2006.201.10:47:16.26#ibcon#*before return 0, iclass 22, count 0 2006.201.10:47:16.26#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:16.26#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:16.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:47:16.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:47:16.26$vck44/valo=8,884.99 2006.201.10:47:16.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.10:47:16.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.10:47:16.26#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:16.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:16.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:16.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:16.26#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:47:16.26#ibcon#first serial, iclass 24, count 0 2006.201.10:47:16.26#ibcon#enter sib2, iclass 24, count 0 2006.201.10:47:16.26#ibcon#flushed, iclass 24, count 0 2006.201.10:47:16.26#ibcon#about to write, iclass 24, count 0 2006.201.10:47:16.26#ibcon#wrote, iclass 24, count 0 2006.201.10:47:16.26#ibcon#about to read 3, iclass 24, count 0 2006.201.10:47:16.28#ibcon#read 3, iclass 24, count 0 2006.201.10:47:16.28#ibcon#about to read 4, iclass 24, count 0 2006.201.10:47:16.28#ibcon#read 4, iclass 24, count 0 2006.201.10:47:16.28#ibcon#about to read 5, iclass 24, count 0 2006.201.10:47:16.28#ibcon#read 5, iclass 24, count 0 2006.201.10:47:16.28#ibcon#about to read 6, iclass 24, count 0 2006.201.10:47:16.28#ibcon#read 6, iclass 24, count 0 2006.201.10:47:16.28#ibcon#end of sib2, iclass 24, count 0 2006.201.10:47:16.28#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:47:16.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:47:16.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:47:16.28#ibcon#*before write, iclass 24, count 0 2006.201.10:47:16.28#ibcon#enter sib2, iclass 24, count 0 2006.201.10:47:16.28#ibcon#flushed, iclass 24, count 0 2006.201.10:47:16.28#ibcon#about to write, iclass 24, count 0 2006.201.10:47:16.28#ibcon#wrote, iclass 24, count 0 2006.201.10:47:16.28#ibcon#about to read 3, iclass 24, count 0 2006.201.10:47:16.32#ibcon#read 3, iclass 24, count 0 2006.201.10:47:16.32#ibcon#about to read 4, iclass 24, count 0 2006.201.10:47:16.32#ibcon#read 4, iclass 24, count 0 2006.201.10:47:16.32#ibcon#about to read 5, iclass 24, count 0 2006.201.10:47:16.32#ibcon#read 5, iclass 24, count 0 2006.201.10:47:16.32#ibcon#about to read 6, iclass 24, count 0 2006.201.10:47:16.32#ibcon#read 6, iclass 24, count 0 2006.201.10:47:16.32#ibcon#end of sib2, iclass 24, count 0 2006.201.10:47:16.32#ibcon#*after write, iclass 24, count 0 2006.201.10:47:16.32#ibcon#*before return 0, iclass 24, count 0 2006.201.10:47:16.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:16.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:16.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:47:16.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:47:16.32$vck44/va=8,4 2006.201.10:47:16.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.10:47:16.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.10:47:16.32#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:16.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:16.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:16.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:16.38#ibcon#enter wrdev, iclass 26, count 2 2006.201.10:47:16.38#ibcon#first serial, iclass 26, count 2 2006.201.10:47:16.38#ibcon#enter sib2, iclass 26, count 2 2006.201.10:47:16.38#ibcon#flushed, iclass 26, count 2 2006.201.10:47:16.38#ibcon#about to write, iclass 26, count 2 2006.201.10:47:16.38#ibcon#wrote, iclass 26, count 2 2006.201.10:47:16.38#ibcon#about to read 3, iclass 26, count 2 2006.201.10:47:16.40#ibcon#read 3, iclass 26, count 2 2006.201.10:47:16.40#ibcon#about to read 4, iclass 26, count 2 2006.201.10:47:16.40#ibcon#read 4, iclass 26, count 2 2006.201.10:47:16.40#ibcon#about to read 5, iclass 26, count 2 2006.201.10:47:16.40#ibcon#read 5, iclass 26, count 2 2006.201.10:47:16.40#ibcon#about to read 6, iclass 26, count 2 2006.201.10:47:16.40#ibcon#read 6, iclass 26, count 2 2006.201.10:47:16.40#ibcon#end of sib2, iclass 26, count 2 2006.201.10:47:16.40#ibcon#*mode == 0, iclass 26, count 2 2006.201.10:47:16.40#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.10:47:16.40#ibcon#[25=AT08-04\r\n] 2006.201.10:47:16.40#ibcon#*before write, iclass 26, count 2 2006.201.10:47:16.40#ibcon#enter sib2, iclass 26, count 2 2006.201.10:47:16.40#ibcon#flushed, iclass 26, count 2 2006.201.10:47:16.40#ibcon#about to write, iclass 26, count 2 2006.201.10:47:16.40#ibcon#wrote, iclass 26, count 2 2006.201.10:47:16.40#ibcon#about to read 3, iclass 26, count 2 2006.201.10:47:16.43#ibcon#read 3, iclass 26, count 2 2006.201.10:47:16.43#ibcon#about to read 4, iclass 26, count 2 2006.201.10:47:16.43#ibcon#read 4, iclass 26, count 2 2006.201.10:47:16.43#ibcon#about to read 5, iclass 26, count 2 2006.201.10:47:16.43#ibcon#read 5, iclass 26, count 2 2006.201.10:47:16.43#ibcon#about to read 6, iclass 26, count 2 2006.201.10:47:16.43#ibcon#read 6, iclass 26, count 2 2006.201.10:47:16.43#ibcon#end of sib2, iclass 26, count 2 2006.201.10:47:16.43#ibcon#*after write, iclass 26, count 2 2006.201.10:47:16.43#ibcon#*before return 0, iclass 26, count 2 2006.201.10:47:16.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:16.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:16.43#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.10:47:16.43#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:16.43#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:16.55#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:16.55#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:16.55#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:47:16.55#ibcon#first serial, iclass 26, count 0 2006.201.10:47:16.55#ibcon#enter sib2, iclass 26, count 0 2006.201.10:47:16.55#ibcon#flushed, iclass 26, count 0 2006.201.10:47:16.55#ibcon#about to write, iclass 26, count 0 2006.201.10:47:16.55#ibcon#wrote, iclass 26, count 0 2006.201.10:47:16.55#ibcon#about to read 3, iclass 26, count 0 2006.201.10:47:16.57#ibcon#read 3, iclass 26, count 0 2006.201.10:47:16.57#ibcon#about to read 4, iclass 26, count 0 2006.201.10:47:16.57#ibcon#read 4, iclass 26, count 0 2006.201.10:47:16.57#ibcon#about to read 5, iclass 26, count 0 2006.201.10:47:16.57#ibcon#read 5, iclass 26, count 0 2006.201.10:47:16.57#ibcon#about to read 6, iclass 26, count 0 2006.201.10:47:16.57#ibcon#read 6, iclass 26, count 0 2006.201.10:47:16.57#ibcon#end of sib2, iclass 26, count 0 2006.201.10:47:16.57#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:47:16.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:47:16.57#ibcon#[25=USB\r\n] 2006.201.10:47:16.57#ibcon#*before write, iclass 26, count 0 2006.201.10:47:16.57#ibcon#enter sib2, iclass 26, count 0 2006.201.10:47:16.57#ibcon#flushed, iclass 26, count 0 2006.201.10:47:16.57#ibcon#about to write, iclass 26, count 0 2006.201.10:47:16.57#ibcon#wrote, iclass 26, count 0 2006.201.10:47:16.57#ibcon#about to read 3, iclass 26, count 0 2006.201.10:47:16.60#ibcon#read 3, iclass 26, count 0 2006.201.10:47:16.60#ibcon#about to read 4, iclass 26, count 0 2006.201.10:47:16.60#ibcon#read 4, iclass 26, count 0 2006.201.10:47:16.60#ibcon#about to read 5, iclass 26, count 0 2006.201.10:47:16.60#ibcon#read 5, iclass 26, count 0 2006.201.10:47:16.60#ibcon#about to read 6, iclass 26, count 0 2006.201.10:47:16.60#ibcon#read 6, iclass 26, count 0 2006.201.10:47:16.60#ibcon#end of sib2, iclass 26, count 0 2006.201.10:47:16.60#ibcon#*after write, iclass 26, count 0 2006.201.10:47:16.60#ibcon#*before return 0, iclass 26, count 0 2006.201.10:47:16.60#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:16.60#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:16.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:47:16.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:47:16.60$vck44/vblo=1,629.99 2006.201.10:47:16.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.10:47:16.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.10:47:16.60#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:16.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:16.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:16.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:16.60#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:47:16.60#ibcon#first serial, iclass 28, count 0 2006.201.10:47:16.60#ibcon#enter sib2, iclass 28, count 0 2006.201.10:47:16.60#ibcon#flushed, iclass 28, count 0 2006.201.10:47:16.60#ibcon#about to write, iclass 28, count 0 2006.201.10:47:16.60#ibcon#wrote, iclass 28, count 0 2006.201.10:47:16.60#ibcon#about to read 3, iclass 28, count 0 2006.201.10:47:16.62#ibcon#read 3, iclass 28, count 0 2006.201.10:47:16.62#ibcon#about to read 4, iclass 28, count 0 2006.201.10:47:16.62#ibcon#read 4, iclass 28, count 0 2006.201.10:47:16.62#ibcon#about to read 5, iclass 28, count 0 2006.201.10:47:16.62#ibcon#read 5, iclass 28, count 0 2006.201.10:47:16.62#ibcon#about to read 6, iclass 28, count 0 2006.201.10:47:16.62#ibcon#read 6, iclass 28, count 0 2006.201.10:47:16.62#ibcon#end of sib2, iclass 28, count 0 2006.201.10:47:16.62#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:47:16.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:47:16.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:47:16.62#ibcon#*before write, iclass 28, count 0 2006.201.10:47:16.62#ibcon#enter sib2, iclass 28, count 0 2006.201.10:47:16.62#ibcon#flushed, iclass 28, count 0 2006.201.10:47:16.62#ibcon#about to write, iclass 28, count 0 2006.201.10:47:16.62#ibcon#wrote, iclass 28, count 0 2006.201.10:47:16.62#ibcon#about to read 3, iclass 28, count 0 2006.201.10:47:16.67#ibcon#read 3, iclass 28, count 0 2006.201.10:47:16.67#ibcon#about to read 4, iclass 28, count 0 2006.201.10:47:16.67#ibcon#read 4, iclass 28, count 0 2006.201.10:47:16.67#ibcon#about to read 5, iclass 28, count 0 2006.201.10:47:16.67#ibcon#read 5, iclass 28, count 0 2006.201.10:47:16.67#ibcon#about to read 6, iclass 28, count 0 2006.201.10:47:16.67#ibcon#read 6, iclass 28, count 0 2006.201.10:47:16.67#ibcon#end of sib2, iclass 28, count 0 2006.201.10:47:16.67#ibcon#*after write, iclass 28, count 0 2006.201.10:47:16.67#ibcon#*before return 0, iclass 28, count 0 2006.201.10:47:16.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:16.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:16.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:47:16.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:47:16.67$vck44/vb=1,4 2006.201.10:47:16.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.10:47:16.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.10:47:16.67#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:16.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:47:16.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:47:16.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:47:16.67#ibcon#enter wrdev, iclass 30, count 2 2006.201.10:47:16.67#ibcon#first serial, iclass 30, count 2 2006.201.10:47:16.67#ibcon#enter sib2, iclass 30, count 2 2006.201.10:47:16.67#ibcon#flushed, iclass 30, count 2 2006.201.10:47:16.67#ibcon#about to write, iclass 30, count 2 2006.201.10:47:16.67#ibcon#wrote, iclass 30, count 2 2006.201.10:47:16.67#ibcon#about to read 3, iclass 30, count 2 2006.201.10:47:16.69#ibcon#read 3, iclass 30, count 2 2006.201.10:47:16.69#ibcon#about to read 4, iclass 30, count 2 2006.201.10:47:16.69#ibcon#read 4, iclass 30, count 2 2006.201.10:47:16.69#ibcon#about to read 5, iclass 30, count 2 2006.201.10:47:16.69#ibcon#read 5, iclass 30, count 2 2006.201.10:47:16.69#ibcon#about to read 6, iclass 30, count 2 2006.201.10:47:16.69#ibcon#read 6, iclass 30, count 2 2006.201.10:47:16.69#ibcon#end of sib2, iclass 30, count 2 2006.201.10:47:16.69#ibcon#*mode == 0, iclass 30, count 2 2006.201.10:47:16.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.10:47:16.69#ibcon#[27=AT01-04\r\n] 2006.201.10:47:16.69#ibcon#*before write, iclass 30, count 2 2006.201.10:47:16.69#ibcon#enter sib2, iclass 30, count 2 2006.201.10:47:16.69#ibcon#flushed, iclass 30, count 2 2006.201.10:47:16.69#ibcon#about to write, iclass 30, count 2 2006.201.10:47:16.69#ibcon#wrote, iclass 30, count 2 2006.201.10:47:16.69#ibcon#about to read 3, iclass 30, count 2 2006.201.10:47:16.72#ibcon#read 3, iclass 30, count 2 2006.201.10:47:16.72#ibcon#about to read 4, iclass 30, count 2 2006.201.10:47:16.72#ibcon#read 4, iclass 30, count 2 2006.201.10:47:16.72#ibcon#about to read 5, iclass 30, count 2 2006.201.10:47:16.72#ibcon#read 5, iclass 30, count 2 2006.201.10:47:16.72#ibcon#about to read 6, iclass 30, count 2 2006.201.10:47:16.72#ibcon#read 6, iclass 30, count 2 2006.201.10:47:16.72#ibcon#end of sib2, iclass 30, count 2 2006.201.10:47:16.72#ibcon#*after write, iclass 30, count 2 2006.201.10:47:16.72#ibcon#*before return 0, iclass 30, count 2 2006.201.10:47:16.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:47:16.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.10:47:16.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.10:47:16.72#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:16.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:47:16.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:47:16.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:47:16.84#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:47:16.84#ibcon#first serial, iclass 30, count 0 2006.201.10:47:16.84#ibcon#enter sib2, iclass 30, count 0 2006.201.10:47:16.84#ibcon#flushed, iclass 30, count 0 2006.201.10:47:16.84#ibcon#about to write, iclass 30, count 0 2006.201.10:47:16.84#ibcon#wrote, iclass 30, count 0 2006.201.10:47:16.84#ibcon#about to read 3, iclass 30, count 0 2006.201.10:47:16.86#ibcon#read 3, iclass 30, count 0 2006.201.10:47:16.86#ibcon#about to read 4, iclass 30, count 0 2006.201.10:47:16.86#ibcon#read 4, iclass 30, count 0 2006.201.10:47:16.86#ibcon#about to read 5, iclass 30, count 0 2006.201.10:47:16.86#ibcon#read 5, iclass 30, count 0 2006.201.10:47:16.86#ibcon#about to read 6, iclass 30, count 0 2006.201.10:47:16.86#ibcon#read 6, iclass 30, count 0 2006.201.10:47:16.86#ibcon#end of sib2, iclass 30, count 0 2006.201.10:47:16.86#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:47:16.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:47:16.86#ibcon#[27=USB\r\n] 2006.201.10:47:16.86#ibcon#*before write, iclass 30, count 0 2006.201.10:47:16.86#ibcon#enter sib2, iclass 30, count 0 2006.201.10:47:16.86#ibcon#flushed, iclass 30, count 0 2006.201.10:47:16.86#ibcon#about to write, iclass 30, count 0 2006.201.10:47:16.86#ibcon#wrote, iclass 30, count 0 2006.201.10:47:16.86#ibcon#about to read 3, iclass 30, count 0 2006.201.10:47:16.89#ibcon#read 3, iclass 30, count 0 2006.201.10:47:16.89#ibcon#about to read 4, iclass 30, count 0 2006.201.10:47:16.89#ibcon#read 4, iclass 30, count 0 2006.201.10:47:16.89#ibcon#about to read 5, iclass 30, count 0 2006.201.10:47:16.89#ibcon#read 5, iclass 30, count 0 2006.201.10:47:16.89#ibcon#about to read 6, iclass 30, count 0 2006.201.10:47:16.89#ibcon#read 6, iclass 30, count 0 2006.201.10:47:16.89#ibcon#end of sib2, iclass 30, count 0 2006.201.10:47:16.89#ibcon#*after write, iclass 30, count 0 2006.201.10:47:16.89#ibcon#*before return 0, iclass 30, count 0 2006.201.10:47:16.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:47:16.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.10:47:16.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:47:16.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:47:16.89$vck44/vblo=2,634.99 2006.201.10:47:16.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.10:47:16.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.10:47:16.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:16.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:16.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:16.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:16.89#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:47:16.89#ibcon#first serial, iclass 32, count 0 2006.201.10:47:16.89#ibcon#enter sib2, iclass 32, count 0 2006.201.10:47:16.89#ibcon#flushed, iclass 32, count 0 2006.201.10:47:16.89#ibcon#about to write, iclass 32, count 0 2006.201.10:47:16.89#ibcon#wrote, iclass 32, count 0 2006.201.10:47:16.89#ibcon#about to read 3, iclass 32, count 0 2006.201.10:47:16.91#ibcon#read 3, iclass 32, count 0 2006.201.10:47:16.91#ibcon#about to read 4, iclass 32, count 0 2006.201.10:47:16.91#ibcon#read 4, iclass 32, count 0 2006.201.10:47:16.91#ibcon#about to read 5, iclass 32, count 0 2006.201.10:47:16.91#ibcon#read 5, iclass 32, count 0 2006.201.10:47:16.91#ibcon#about to read 6, iclass 32, count 0 2006.201.10:47:16.91#ibcon#read 6, iclass 32, count 0 2006.201.10:47:16.91#ibcon#end of sib2, iclass 32, count 0 2006.201.10:47:16.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:47:16.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:47:16.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:47:16.91#ibcon#*before write, iclass 32, count 0 2006.201.10:47:16.91#ibcon#enter sib2, iclass 32, count 0 2006.201.10:47:16.91#ibcon#flushed, iclass 32, count 0 2006.201.10:47:16.91#ibcon#about to write, iclass 32, count 0 2006.201.10:47:16.91#ibcon#wrote, iclass 32, count 0 2006.201.10:47:16.91#ibcon#about to read 3, iclass 32, count 0 2006.201.10:47:16.95#ibcon#read 3, iclass 32, count 0 2006.201.10:47:16.95#ibcon#about to read 4, iclass 32, count 0 2006.201.10:47:16.95#ibcon#read 4, iclass 32, count 0 2006.201.10:47:16.95#ibcon#about to read 5, iclass 32, count 0 2006.201.10:47:16.95#ibcon#read 5, iclass 32, count 0 2006.201.10:47:16.95#ibcon#about to read 6, iclass 32, count 0 2006.201.10:47:16.95#ibcon#read 6, iclass 32, count 0 2006.201.10:47:16.95#ibcon#end of sib2, iclass 32, count 0 2006.201.10:47:16.95#ibcon#*after write, iclass 32, count 0 2006.201.10:47:16.95#ibcon#*before return 0, iclass 32, count 0 2006.201.10:47:16.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:16.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.10:47:16.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:47:16.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:47:16.95$vck44/vb=2,5 2006.201.10:47:16.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.10:47:16.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.10:47:16.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:16.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:17.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:17.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:17.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.10:47:17.01#ibcon#first serial, iclass 34, count 2 2006.201.10:47:17.01#ibcon#enter sib2, iclass 34, count 2 2006.201.10:47:17.01#ibcon#flushed, iclass 34, count 2 2006.201.10:47:17.01#ibcon#about to write, iclass 34, count 2 2006.201.10:47:17.01#ibcon#wrote, iclass 34, count 2 2006.201.10:47:17.01#ibcon#about to read 3, iclass 34, count 2 2006.201.10:47:17.03#ibcon#read 3, iclass 34, count 2 2006.201.10:47:17.03#ibcon#about to read 4, iclass 34, count 2 2006.201.10:47:17.03#ibcon#read 4, iclass 34, count 2 2006.201.10:47:17.03#ibcon#about to read 5, iclass 34, count 2 2006.201.10:47:17.03#ibcon#read 5, iclass 34, count 2 2006.201.10:47:17.03#ibcon#about to read 6, iclass 34, count 2 2006.201.10:47:17.03#ibcon#read 6, iclass 34, count 2 2006.201.10:47:17.03#ibcon#end of sib2, iclass 34, count 2 2006.201.10:47:17.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.10:47:17.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.10:47:17.03#ibcon#[27=AT02-05\r\n] 2006.201.10:47:17.03#ibcon#*before write, iclass 34, count 2 2006.201.10:47:17.03#ibcon#enter sib2, iclass 34, count 2 2006.201.10:47:17.03#ibcon#flushed, iclass 34, count 2 2006.201.10:47:17.03#ibcon#about to write, iclass 34, count 2 2006.201.10:47:17.03#ibcon#wrote, iclass 34, count 2 2006.201.10:47:17.03#ibcon#about to read 3, iclass 34, count 2 2006.201.10:47:17.06#ibcon#read 3, iclass 34, count 2 2006.201.10:47:17.06#ibcon#about to read 4, iclass 34, count 2 2006.201.10:47:17.06#ibcon#read 4, iclass 34, count 2 2006.201.10:47:17.06#ibcon#about to read 5, iclass 34, count 2 2006.201.10:47:17.06#ibcon#read 5, iclass 34, count 2 2006.201.10:47:17.06#ibcon#about to read 6, iclass 34, count 2 2006.201.10:47:17.06#ibcon#read 6, iclass 34, count 2 2006.201.10:47:17.06#ibcon#end of sib2, iclass 34, count 2 2006.201.10:47:17.06#ibcon#*after write, iclass 34, count 2 2006.201.10:47:17.06#ibcon#*before return 0, iclass 34, count 2 2006.201.10:47:17.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:17.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.10:47:17.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.10:47:17.06#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:17.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:17.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:17.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:17.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:47:17.18#ibcon#first serial, iclass 34, count 0 2006.201.10:47:17.18#ibcon#enter sib2, iclass 34, count 0 2006.201.10:47:17.18#ibcon#flushed, iclass 34, count 0 2006.201.10:47:17.18#ibcon#about to write, iclass 34, count 0 2006.201.10:47:17.18#ibcon#wrote, iclass 34, count 0 2006.201.10:47:17.18#ibcon#about to read 3, iclass 34, count 0 2006.201.10:47:17.20#ibcon#read 3, iclass 34, count 0 2006.201.10:47:17.20#ibcon#about to read 4, iclass 34, count 0 2006.201.10:47:17.20#ibcon#read 4, iclass 34, count 0 2006.201.10:47:17.20#ibcon#about to read 5, iclass 34, count 0 2006.201.10:47:17.20#ibcon#read 5, iclass 34, count 0 2006.201.10:47:17.20#ibcon#about to read 6, iclass 34, count 0 2006.201.10:47:17.20#ibcon#read 6, iclass 34, count 0 2006.201.10:47:17.20#ibcon#end of sib2, iclass 34, count 0 2006.201.10:47:17.20#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:47:17.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:47:17.20#ibcon#[27=USB\r\n] 2006.201.10:47:17.20#ibcon#*before write, iclass 34, count 0 2006.201.10:47:17.20#ibcon#enter sib2, iclass 34, count 0 2006.201.10:47:17.20#ibcon#flushed, iclass 34, count 0 2006.201.10:47:17.20#ibcon#about to write, iclass 34, count 0 2006.201.10:47:17.20#ibcon#wrote, iclass 34, count 0 2006.201.10:47:17.20#ibcon#about to read 3, iclass 34, count 0 2006.201.10:47:17.23#ibcon#read 3, iclass 34, count 0 2006.201.10:47:17.23#ibcon#about to read 4, iclass 34, count 0 2006.201.10:47:17.23#ibcon#read 4, iclass 34, count 0 2006.201.10:47:17.23#ibcon#about to read 5, iclass 34, count 0 2006.201.10:47:17.23#ibcon#read 5, iclass 34, count 0 2006.201.10:47:17.23#ibcon#about to read 6, iclass 34, count 0 2006.201.10:47:17.23#ibcon#read 6, iclass 34, count 0 2006.201.10:47:17.23#ibcon#end of sib2, iclass 34, count 0 2006.201.10:47:17.23#ibcon#*after write, iclass 34, count 0 2006.201.10:47:17.23#ibcon#*before return 0, iclass 34, count 0 2006.201.10:47:17.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:17.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.10:47:17.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:47:17.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:47:17.23$vck44/vblo=3,649.99 2006.201.10:47:17.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.10:47:17.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.10:47:17.23#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:17.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:17.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:17.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:17.23#ibcon#enter wrdev, iclass 36, count 0 2006.201.10:47:17.23#ibcon#first serial, iclass 36, count 0 2006.201.10:47:17.23#ibcon#enter sib2, iclass 36, count 0 2006.201.10:47:17.23#ibcon#flushed, iclass 36, count 0 2006.201.10:47:17.23#ibcon#about to write, iclass 36, count 0 2006.201.10:47:17.23#ibcon#wrote, iclass 36, count 0 2006.201.10:47:17.23#ibcon#about to read 3, iclass 36, count 0 2006.201.10:47:17.25#ibcon#read 3, iclass 36, count 0 2006.201.10:47:17.25#ibcon#about to read 4, iclass 36, count 0 2006.201.10:47:17.25#ibcon#read 4, iclass 36, count 0 2006.201.10:47:17.25#ibcon#about to read 5, iclass 36, count 0 2006.201.10:47:17.25#ibcon#read 5, iclass 36, count 0 2006.201.10:47:17.25#ibcon#about to read 6, iclass 36, count 0 2006.201.10:47:17.25#ibcon#read 6, iclass 36, count 0 2006.201.10:47:17.25#ibcon#end of sib2, iclass 36, count 0 2006.201.10:47:17.25#ibcon#*mode == 0, iclass 36, count 0 2006.201.10:47:17.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.10:47:17.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:47:17.25#ibcon#*before write, iclass 36, count 0 2006.201.10:47:17.25#ibcon#enter sib2, iclass 36, count 0 2006.201.10:47:17.25#ibcon#flushed, iclass 36, count 0 2006.201.10:47:17.25#ibcon#about to write, iclass 36, count 0 2006.201.10:47:17.25#ibcon#wrote, iclass 36, count 0 2006.201.10:47:17.25#ibcon#about to read 3, iclass 36, count 0 2006.201.10:47:17.29#ibcon#read 3, iclass 36, count 0 2006.201.10:47:17.29#ibcon#about to read 4, iclass 36, count 0 2006.201.10:47:17.29#ibcon#read 4, iclass 36, count 0 2006.201.10:47:17.29#ibcon#about to read 5, iclass 36, count 0 2006.201.10:47:17.29#ibcon#read 5, iclass 36, count 0 2006.201.10:47:17.29#ibcon#about to read 6, iclass 36, count 0 2006.201.10:47:17.29#ibcon#read 6, iclass 36, count 0 2006.201.10:47:17.29#ibcon#end of sib2, iclass 36, count 0 2006.201.10:47:17.29#ibcon#*after write, iclass 36, count 0 2006.201.10:47:17.29#ibcon#*before return 0, iclass 36, count 0 2006.201.10:47:17.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:17.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.10:47:17.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.10:47:17.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.10:47:17.29$vck44/vb=3,4 2006.201.10:47:17.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.10:47:17.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.10:47:17.29#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:17.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:17.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:17.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:17.35#ibcon#enter wrdev, iclass 38, count 2 2006.201.10:47:17.35#ibcon#first serial, iclass 38, count 2 2006.201.10:47:17.35#ibcon#enter sib2, iclass 38, count 2 2006.201.10:47:17.35#ibcon#flushed, iclass 38, count 2 2006.201.10:47:17.35#ibcon#about to write, iclass 38, count 2 2006.201.10:47:17.35#ibcon#wrote, iclass 38, count 2 2006.201.10:47:17.35#ibcon#about to read 3, iclass 38, count 2 2006.201.10:47:17.37#ibcon#read 3, iclass 38, count 2 2006.201.10:47:17.37#ibcon#about to read 4, iclass 38, count 2 2006.201.10:47:17.37#ibcon#read 4, iclass 38, count 2 2006.201.10:47:17.37#ibcon#about to read 5, iclass 38, count 2 2006.201.10:47:17.37#ibcon#read 5, iclass 38, count 2 2006.201.10:47:17.37#ibcon#about to read 6, iclass 38, count 2 2006.201.10:47:17.37#ibcon#read 6, iclass 38, count 2 2006.201.10:47:17.37#ibcon#end of sib2, iclass 38, count 2 2006.201.10:47:17.37#ibcon#*mode == 0, iclass 38, count 2 2006.201.10:47:17.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.10:47:17.37#ibcon#[27=AT03-04\r\n] 2006.201.10:47:17.37#ibcon#*before write, iclass 38, count 2 2006.201.10:47:17.37#ibcon#enter sib2, iclass 38, count 2 2006.201.10:47:17.37#ibcon#flushed, iclass 38, count 2 2006.201.10:47:17.37#ibcon#about to write, iclass 38, count 2 2006.201.10:47:17.37#ibcon#wrote, iclass 38, count 2 2006.201.10:47:17.37#ibcon#about to read 3, iclass 38, count 2 2006.201.10:47:17.41#ibcon#read 3, iclass 38, count 2 2006.201.10:47:17.41#ibcon#about to read 4, iclass 38, count 2 2006.201.10:47:17.41#ibcon#read 4, iclass 38, count 2 2006.201.10:47:17.41#ibcon#about to read 5, iclass 38, count 2 2006.201.10:47:17.41#ibcon#read 5, iclass 38, count 2 2006.201.10:47:17.41#ibcon#about to read 6, iclass 38, count 2 2006.201.10:47:17.41#ibcon#read 6, iclass 38, count 2 2006.201.10:47:17.41#ibcon#end of sib2, iclass 38, count 2 2006.201.10:47:17.41#ibcon#*after write, iclass 38, count 2 2006.201.10:47:17.41#ibcon#*before return 0, iclass 38, count 2 2006.201.10:47:17.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:17.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.10:47:17.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.10:47:17.41#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:17.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:17.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:17.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:17.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:47:17.53#ibcon#first serial, iclass 38, count 0 2006.201.10:47:17.53#ibcon#enter sib2, iclass 38, count 0 2006.201.10:47:17.53#ibcon#flushed, iclass 38, count 0 2006.201.10:47:17.53#ibcon#about to write, iclass 38, count 0 2006.201.10:47:17.53#ibcon#wrote, iclass 38, count 0 2006.201.10:47:17.53#ibcon#about to read 3, iclass 38, count 0 2006.201.10:47:17.55#ibcon#read 3, iclass 38, count 0 2006.201.10:47:17.55#ibcon#about to read 4, iclass 38, count 0 2006.201.10:47:17.55#ibcon#read 4, iclass 38, count 0 2006.201.10:47:17.55#ibcon#about to read 5, iclass 38, count 0 2006.201.10:47:17.55#ibcon#read 5, iclass 38, count 0 2006.201.10:47:17.55#ibcon#about to read 6, iclass 38, count 0 2006.201.10:47:17.55#ibcon#read 6, iclass 38, count 0 2006.201.10:47:17.55#ibcon#end of sib2, iclass 38, count 0 2006.201.10:47:17.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:47:17.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:47:17.55#ibcon#[27=USB\r\n] 2006.201.10:47:17.55#ibcon#*before write, iclass 38, count 0 2006.201.10:47:17.55#ibcon#enter sib2, iclass 38, count 0 2006.201.10:47:17.55#ibcon#flushed, iclass 38, count 0 2006.201.10:47:17.55#ibcon#about to write, iclass 38, count 0 2006.201.10:47:17.55#ibcon#wrote, iclass 38, count 0 2006.201.10:47:17.55#ibcon#about to read 3, iclass 38, count 0 2006.201.10:47:17.58#ibcon#read 3, iclass 38, count 0 2006.201.10:47:17.58#ibcon#about to read 4, iclass 38, count 0 2006.201.10:47:17.58#ibcon#read 4, iclass 38, count 0 2006.201.10:47:17.58#ibcon#about to read 5, iclass 38, count 0 2006.201.10:47:17.58#ibcon#read 5, iclass 38, count 0 2006.201.10:47:17.58#ibcon#about to read 6, iclass 38, count 0 2006.201.10:47:17.58#ibcon#read 6, iclass 38, count 0 2006.201.10:47:17.58#ibcon#end of sib2, iclass 38, count 0 2006.201.10:47:17.58#ibcon#*after write, iclass 38, count 0 2006.201.10:47:17.58#ibcon#*before return 0, iclass 38, count 0 2006.201.10:47:17.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:17.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.10:47:17.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:47:17.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:47:17.58$vck44/vblo=4,679.99 2006.201.10:47:17.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.10:47:17.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.10:47:17.58#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:17.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:17.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:17.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:17.58#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:47:17.58#ibcon#first serial, iclass 40, count 0 2006.201.10:47:17.58#ibcon#enter sib2, iclass 40, count 0 2006.201.10:47:17.58#ibcon#flushed, iclass 40, count 0 2006.201.10:47:17.58#ibcon#about to write, iclass 40, count 0 2006.201.10:47:17.58#ibcon#wrote, iclass 40, count 0 2006.201.10:47:17.58#ibcon#about to read 3, iclass 40, count 0 2006.201.10:47:17.60#ibcon#read 3, iclass 40, count 0 2006.201.10:47:17.60#ibcon#about to read 4, iclass 40, count 0 2006.201.10:47:17.60#ibcon#read 4, iclass 40, count 0 2006.201.10:47:17.60#ibcon#about to read 5, iclass 40, count 0 2006.201.10:47:17.60#ibcon#read 5, iclass 40, count 0 2006.201.10:47:17.60#ibcon#about to read 6, iclass 40, count 0 2006.201.10:47:17.60#ibcon#read 6, iclass 40, count 0 2006.201.10:47:17.60#ibcon#end of sib2, iclass 40, count 0 2006.201.10:47:17.60#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:47:17.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:47:17.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:47:17.60#ibcon#*before write, iclass 40, count 0 2006.201.10:47:17.60#ibcon#enter sib2, iclass 40, count 0 2006.201.10:47:17.60#ibcon#flushed, iclass 40, count 0 2006.201.10:47:17.60#ibcon#about to write, iclass 40, count 0 2006.201.10:47:17.60#ibcon#wrote, iclass 40, count 0 2006.201.10:47:17.60#ibcon#about to read 3, iclass 40, count 0 2006.201.10:47:17.64#ibcon#read 3, iclass 40, count 0 2006.201.10:47:17.64#ibcon#about to read 4, iclass 40, count 0 2006.201.10:47:17.64#ibcon#read 4, iclass 40, count 0 2006.201.10:47:17.64#ibcon#about to read 5, iclass 40, count 0 2006.201.10:47:17.64#ibcon#read 5, iclass 40, count 0 2006.201.10:47:17.64#ibcon#about to read 6, iclass 40, count 0 2006.201.10:47:17.64#ibcon#read 6, iclass 40, count 0 2006.201.10:47:17.64#ibcon#end of sib2, iclass 40, count 0 2006.201.10:47:17.64#ibcon#*after write, iclass 40, count 0 2006.201.10:47:17.64#ibcon#*before return 0, iclass 40, count 0 2006.201.10:47:17.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:17.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.10:47:17.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:47:17.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:47:17.64$vck44/vb=4,5 2006.201.10:47:17.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.10:47:17.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.10:47:17.64#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:17.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:17.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:17.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:17.70#ibcon#enter wrdev, iclass 4, count 2 2006.201.10:47:17.70#ibcon#first serial, iclass 4, count 2 2006.201.10:47:17.70#ibcon#enter sib2, iclass 4, count 2 2006.201.10:47:17.70#ibcon#flushed, iclass 4, count 2 2006.201.10:47:17.70#ibcon#about to write, iclass 4, count 2 2006.201.10:47:17.70#ibcon#wrote, iclass 4, count 2 2006.201.10:47:17.70#ibcon#about to read 3, iclass 4, count 2 2006.201.10:47:17.72#ibcon#read 3, iclass 4, count 2 2006.201.10:47:17.72#ibcon#about to read 4, iclass 4, count 2 2006.201.10:47:17.72#ibcon#read 4, iclass 4, count 2 2006.201.10:47:17.72#ibcon#about to read 5, iclass 4, count 2 2006.201.10:47:17.72#ibcon#read 5, iclass 4, count 2 2006.201.10:47:17.72#ibcon#about to read 6, iclass 4, count 2 2006.201.10:47:17.72#ibcon#read 6, iclass 4, count 2 2006.201.10:47:17.72#ibcon#end of sib2, iclass 4, count 2 2006.201.10:47:17.72#ibcon#*mode == 0, iclass 4, count 2 2006.201.10:47:17.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.10:47:17.72#ibcon#[27=AT04-05\r\n] 2006.201.10:47:17.72#ibcon#*before write, iclass 4, count 2 2006.201.10:47:17.72#ibcon#enter sib2, iclass 4, count 2 2006.201.10:47:17.72#ibcon#flushed, iclass 4, count 2 2006.201.10:47:17.72#ibcon#about to write, iclass 4, count 2 2006.201.10:47:17.72#ibcon#wrote, iclass 4, count 2 2006.201.10:47:17.72#ibcon#about to read 3, iclass 4, count 2 2006.201.10:47:17.75#ibcon#read 3, iclass 4, count 2 2006.201.10:47:17.75#ibcon#about to read 4, iclass 4, count 2 2006.201.10:47:17.75#ibcon#read 4, iclass 4, count 2 2006.201.10:47:17.75#ibcon#about to read 5, iclass 4, count 2 2006.201.10:47:17.75#ibcon#read 5, iclass 4, count 2 2006.201.10:47:17.75#ibcon#about to read 6, iclass 4, count 2 2006.201.10:47:17.75#ibcon#read 6, iclass 4, count 2 2006.201.10:47:17.75#ibcon#end of sib2, iclass 4, count 2 2006.201.10:47:17.75#ibcon#*after write, iclass 4, count 2 2006.201.10:47:17.75#ibcon#*before return 0, iclass 4, count 2 2006.201.10:47:17.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:17.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.10:47:17.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.10:47:17.75#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:17.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:17.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:17.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:17.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:47:17.87#ibcon#first serial, iclass 4, count 0 2006.201.10:47:17.87#ibcon#enter sib2, iclass 4, count 0 2006.201.10:47:17.87#ibcon#flushed, iclass 4, count 0 2006.201.10:47:17.87#ibcon#about to write, iclass 4, count 0 2006.201.10:47:17.87#ibcon#wrote, iclass 4, count 0 2006.201.10:47:17.87#ibcon#about to read 3, iclass 4, count 0 2006.201.10:47:17.89#ibcon#read 3, iclass 4, count 0 2006.201.10:47:17.89#ibcon#about to read 4, iclass 4, count 0 2006.201.10:47:17.89#ibcon#read 4, iclass 4, count 0 2006.201.10:47:17.89#ibcon#about to read 5, iclass 4, count 0 2006.201.10:47:17.89#ibcon#read 5, iclass 4, count 0 2006.201.10:47:17.89#ibcon#about to read 6, iclass 4, count 0 2006.201.10:47:17.89#ibcon#read 6, iclass 4, count 0 2006.201.10:47:17.89#ibcon#end of sib2, iclass 4, count 0 2006.201.10:47:17.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:47:17.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:47:17.89#ibcon#[27=USB\r\n] 2006.201.10:47:17.89#ibcon#*before write, iclass 4, count 0 2006.201.10:47:17.89#ibcon#enter sib2, iclass 4, count 0 2006.201.10:47:17.89#ibcon#flushed, iclass 4, count 0 2006.201.10:47:17.89#ibcon#about to write, iclass 4, count 0 2006.201.10:47:17.89#ibcon#wrote, iclass 4, count 0 2006.201.10:47:17.89#ibcon#about to read 3, iclass 4, count 0 2006.201.10:47:17.92#ibcon#read 3, iclass 4, count 0 2006.201.10:47:17.92#ibcon#about to read 4, iclass 4, count 0 2006.201.10:47:17.92#ibcon#read 4, iclass 4, count 0 2006.201.10:47:17.92#ibcon#about to read 5, iclass 4, count 0 2006.201.10:47:17.92#ibcon#read 5, iclass 4, count 0 2006.201.10:47:17.92#ibcon#about to read 6, iclass 4, count 0 2006.201.10:47:17.92#ibcon#read 6, iclass 4, count 0 2006.201.10:47:17.92#ibcon#end of sib2, iclass 4, count 0 2006.201.10:47:17.92#ibcon#*after write, iclass 4, count 0 2006.201.10:47:17.92#ibcon#*before return 0, iclass 4, count 0 2006.201.10:47:17.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:17.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.10:47:17.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:47:17.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:47:17.92$vck44/vblo=5,709.99 2006.201.10:47:17.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.10:47:17.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.10:47:17.92#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:17.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:17.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:17.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:17.92#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:47:17.92#ibcon#first serial, iclass 6, count 0 2006.201.10:47:17.92#ibcon#enter sib2, iclass 6, count 0 2006.201.10:47:17.92#ibcon#flushed, iclass 6, count 0 2006.201.10:47:17.92#ibcon#about to write, iclass 6, count 0 2006.201.10:47:17.92#ibcon#wrote, iclass 6, count 0 2006.201.10:47:17.92#ibcon#about to read 3, iclass 6, count 0 2006.201.10:47:17.94#ibcon#read 3, iclass 6, count 0 2006.201.10:47:17.94#ibcon#about to read 4, iclass 6, count 0 2006.201.10:47:17.94#ibcon#read 4, iclass 6, count 0 2006.201.10:47:17.94#ibcon#about to read 5, iclass 6, count 0 2006.201.10:47:17.94#ibcon#read 5, iclass 6, count 0 2006.201.10:47:17.94#ibcon#about to read 6, iclass 6, count 0 2006.201.10:47:17.94#ibcon#read 6, iclass 6, count 0 2006.201.10:47:17.94#ibcon#end of sib2, iclass 6, count 0 2006.201.10:47:17.94#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:47:17.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:47:17.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:47:17.94#ibcon#*before write, iclass 6, count 0 2006.201.10:47:17.94#ibcon#enter sib2, iclass 6, count 0 2006.201.10:47:17.94#ibcon#flushed, iclass 6, count 0 2006.201.10:47:17.94#ibcon#about to write, iclass 6, count 0 2006.201.10:47:17.94#ibcon#wrote, iclass 6, count 0 2006.201.10:47:17.94#ibcon#about to read 3, iclass 6, count 0 2006.201.10:47:17.98#ibcon#read 3, iclass 6, count 0 2006.201.10:47:17.98#ibcon#about to read 4, iclass 6, count 0 2006.201.10:47:17.98#ibcon#read 4, iclass 6, count 0 2006.201.10:47:17.98#ibcon#about to read 5, iclass 6, count 0 2006.201.10:47:17.98#ibcon#read 5, iclass 6, count 0 2006.201.10:47:17.98#ibcon#about to read 6, iclass 6, count 0 2006.201.10:47:17.98#ibcon#read 6, iclass 6, count 0 2006.201.10:47:17.98#ibcon#end of sib2, iclass 6, count 0 2006.201.10:47:17.98#ibcon#*after write, iclass 6, count 0 2006.201.10:47:17.98#ibcon#*before return 0, iclass 6, count 0 2006.201.10:47:17.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:17.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.10:47:17.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:47:17.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:47:17.98$vck44/vb=5,4 2006.201.10:47:17.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.10:47:17.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.10:47:17.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:17.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:18.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:18.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:18.04#ibcon#enter wrdev, iclass 10, count 2 2006.201.10:47:18.04#ibcon#first serial, iclass 10, count 2 2006.201.10:47:18.04#ibcon#enter sib2, iclass 10, count 2 2006.201.10:47:18.04#ibcon#flushed, iclass 10, count 2 2006.201.10:47:18.04#ibcon#about to write, iclass 10, count 2 2006.201.10:47:18.04#ibcon#wrote, iclass 10, count 2 2006.201.10:47:18.04#ibcon#about to read 3, iclass 10, count 2 2006.201.10:47:18.06#ibcon#read 3, iclass 10, count 2 2006.201.10:47:18.06#ibcon#about to read 4, iclass 10, count 2 2006.201.10:47:18.06#ibcon#read 4, iclass 10, count 2 2006.201.10:47:18.06#ibcon#about to read 5, iclass 10, count 2 2006.201.10:47:18.06#ibcon#read 5, iclass 10, count 2 2006.201.10:47:18.06#ibcon#about to read 6, iclass 10, count 2 2006.201.10:47:18.06#ibcon#read 6, iclass 10, count 2 2006.201.10:47:18.06#ibcon#end of sib2, iclass 10, count 2 2006.201.10:47:18.06#ibcon#*mode == 0, iclass 10, count 2 2006.201.10:47:18.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.10:47:18.06#ibcon#[27=AT05-04\r\n] 2006.201.10:47:18.06#ibcon#*before write, iclass 10, count 2 2006.201.10:47:18.06#ibcon#enter sib2, iclass 10, count 2 2006.201.10:47:18.06#ibcon#flushed, iclass 10, count 2 2006.201.10:47:18.06#ibcon#about to write, iclass 10, count 2 2006.201.10:47:18.06#ibcon#wrote, iclass 10, count 2 2006.201.10:47:18.06#ibcon#about to read 3, iclass 10, count 2 2006.201.10:47:18.09#ibcon#read 3, iclass 10, count 2 2006.201.10:47:18.09#ibcon#about to read 4, iclass 10, count 2 2006.201.10:47:18.09#ibcon#read 4, iclass 10, count 2 2006.201.10:47:18.09#ibcon#about to read 5, iclass 10, count 2 2006.201.10:47:18.09#ibcon#read 5, iclass 10, count 2 2006.201.10:47:18.09#ibcon#about to read 6, iclass 10, count 2 2006.201.10:47:18.09#ibcon#read 6, iclass 10, count 2 2006.201.10:47:18.09#ibcon#end of sib2, iclass 10, count 2 2006.201.10:47:18.09#ibcon#*after write, iclass 10, count 2 2006.201.10:47:18.09#ibcon#*before return 0, iclass 10, count 2 2006.201.10:47:18.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:18.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.10:47:18.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.10:47:18.09#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:18.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:18.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:18.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:18.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:47:18.21#ibcon#first serial, iclass 10, count 0 2006.201.10:47:18.21#ibcon#enter sib2, iclass 10, count 0 2006.201.10:47:18.21#ibcon#flushed, iclass 10, count 0 2006.201.10:47:18.21#ibcon#about to write, iclass 10, count 0 2006.201.10:47:18.21#ibcon#wrote, iclass 10, count 0 2006.201.10:47:18.21#ibcon#about to read 3, iclass 10, count 0 2006.201.10:47:18.23#ibcon#read 3, iclass 10, count 0 2006.201.10:47:18.23#ibcon#about to read 4, iclass 10, count 0 2006.201.10:47:18.23#ibcon#read 4, iclass 10, count 0 2006.201.10:47:18.23#ibcon#about to read 5, iclass 10, count 0 2006.201.10:47:18.23#ibcon#read 5, iclass 10, count 0 2006.201.10:47:18.23#ibcon#about to read 6, iclass 10, count 0 2006.201.10:47:18.23#ibcon#read 6, iclass 10, count 0 2006.201.10:47:18.23#ibcon#end of sib2, iclass 10, count 0 2006.201.10:47:18.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:47:18.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:47:18.23#ibcon#[27=USB\r\n] 2006.201.10:47:18.23#ibcon#*before write, iclass 10, count 0 2006.201.10:47:18.23#ibcon#enter sib2, iclass 10, count 0 2006.201.10:47:18.23#ibcon#flushed, iclass 10, count 0 2006.201.10:47:18.23#ibcon#about to write, iclass 10, count 0 2006.201.10:47:18.23#ibcon#wrote, iclass 10, count 0 2006.201.10:47:18.23#ibcon#about to read 3, iclass 10, count 0 2006.201.10:47:18.26#ibcon#read 3, iclass 10, count 0 2006.201.10:47:18.26#ibcon#about to read 4, iclass 10, count 0 2006.201.10:47:18.26#ibcon#read 4, iclass 10, count 0 2006.201.10:47:18.26#ibcon#about to read 5, iclass 10, count 0 2006.201.10:47:18.26#ibcon#read 5, iclass 10, count 0 2006.201.10:47:18.26#ibcon#about to read 6, iclass 10, count 0 2006.201.10:47:18.26#ibcon#read 6, iclass 10, count 0 2006.201.10:47:18.26#ibcon#end of sib2, iclass 10, count 0 2006.201.10:47:18.26#ibcon#*after write, iclass 10, count 0 2006.201.10:47:18.26#ibcon#*before return 0, iclass 10, count 0 2006.201.10:47:18.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:18.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.10:47:18.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:47:18.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:47:18.26$vck44/vblo=6,719.99 2006.201.10:47:18.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.10:47:18.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.10:47:18.26#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:18.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:18.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:18.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:18.26#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:47:18.26#ibcon#first serial, iclass 12, count 0 2006.201.10:47:18.26#ibcon#enter sib2, iclass 12, count 0 2006.201.10:47:18.26#ibcon#flushed, iclass 12, count 0 2006.201.10:47:18.26#ibcon#about to write, iclass 12, count 0 2006.201.10:47:18.26#ibcon#wrote, iclass 12, count 0 2006.201.10:47:18.26#ibcon#about to read 3, iclass 12, count 0 2006.201.10:47:18.28#ibcon#read 3, iclass 12, count 0 2006.201.10:47:18.28#ibcon#about to read 4, iclass 12, count 0 2006.201.10:47:18.28#ibcon#read 4, iclass 12, count 0 2006.201.10:47:18.28#ibcon#about to read 5, iclass 12, count 0 2006.201.10:47:18.28#ibcon#read 5, iclass 12, count 0 2006.201.10:47:18.28#ibcon#about to read 6, iclass 12, count 0 2006.201.10:47:18.28#ibcon#read 6, iclass 12, count 0 2006.201.10:47:18.28#ibcon#end of sib2, iclass 12, count 0 2006.201.10:47:18.28#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:47:18.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:47:18.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:47:18.28#ibcon#*before write, iclass 12, count 0 2006.201.10:47:18.28#ibcon#enter sib2, iclass 12, count 0 2006.201.10:47:18.28#ibcon#flushed, iclass 12, count 0 2006.201.10:47:18.28#ibcon#about to write, iclass 12, count 0 2006.201.10:47:18.28#ibcon#wrote, iclass 12, count 0 2006.201.10:47:18.28#ibcon#about to read 3, iclass 12, count 0 2006.201.10:47:18.33#ibcon#read 3, iclass 12, count 0 2006.201.10:47:18.33#ibcon#about to read 4, iclass 12, count 0 2006.201.10:47:18.33#ibcon#read 4, iclass 12, count 0 2006.201.10:47:18.33#ibcon#about to read 5, iclass 12, count 0 2006.201.10:47:18.33#ibcon#read 5, iclass 12, count 0 2006.201.10:47:18.33#ibcon#about to read 6, iclass 12, count 0 2006.201.10:47:18.33#ibcon#read 6, iclass 12, count 0 2006.201.10:47:18.33#ibcon#end of sib2, iclass 12, count 0 2006.201.10:47:18.33#ibcon#*after write, iclass 12, count 0 2006.201.10:47:18.33#ibcon#*before return 0, iclass 12, count 0 2006.201.10:47:18.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:18.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.10:47:18.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:47:18.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:47:18.33$vck44/vb=6,4 2006.201.10:47:18.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.10:47:18.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.10:47:18.33#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:18.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:18.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:18.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:18.38#ibcon#enter wrdev, iclass 14, count 2 2006.201.10:47:18.38#ibcon#first serial, iclass 14, count 2 2006.201.10:47:18.38#ibcon#enter sib2, iclass 14, count 2 2006.201.10:47:18.38#ibcon#flushed, iclass 14, count 2 2006.201.10:47:18.38#ibcon#about to write, iclass 14, count 2 2006.201.10:47:18.38#ibcon#wrote, iclass 14, count 2 2006.201.10:47:18.38#ibcon#about to read 3, iclass 14, count 2 2006.201.10:47:18.40#ibcon#read 3, iclass 14, count 2 2006.201.10:47:18.40#ibcon#about to read 4, iclass 14, count 2 2006.201.10:47:18.40#ibcon#read 4, iclass 14, count 2 2006.201.10:47:18.40#ibcon#about to read 5, iclass 14, count 2 2006.201.10:47:18.40#ibcon#read 5, iclass 14, count 2 2006.201.10:47:18.40#ibcon#about to read 6, iclass 14, count 2 2006.201.10:47:18.40#ibcon#read 6, iclass 14, count 2 2006.201.10:47:18.40#ibcon#end of sib2, iclass 14, count 2 2006.201.10:47:18.40#ibcon#*mode == 0, iclass 14, count 2 2006.201.10:47:18.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.10:47:18.40#ibcon#[27=AT06-04\r\n] 2006.201.10:47:18.40#ibcon#*before write, iclass 14, count 2 2006.201.10:47:18.40#ibcon#enter sib2, iclass 14, count 2 2006.201.10:47:18.40#ibcon#flushed, iclass 14, count 2 2006.201.10:47:18.40#ibcon#about to write, iclass 14, count 2 2006.201.10:47:18.40#ibcon#wrote, iclass 14, count 2 2006.201.10:47:18.40#ibcon#about to read 3, iclass 14, count 2 2006.201.10:47:18.43#ibcon#read 3, iclass 14, count 2 2006.201.10:47:18.43#ibcon#about to read 4, iclass 14, count 2 2006.201.10:47:18.43#ibcon#read 4, iclass 14, count 2 2006.201.10:47:18.43#ibcon#about to read 5, iclass 14, count 2 2006.201.10:47:18.43#ibcon#read 5, iclass 14, count 2 2006.201.10:47:18.43#ibcon#about to read 6, iclass 14, count 2 2006.201.10:47:18.43#ibcon#read 6, iclass 14, count 2 2006.201.10:47:18.43#ibcon#end of sib2, iclass 14, count 2 2006.201.10:47:18.43#ibcon#*after write, iclass 14, count 2 2006.201.10:47:18.43#ibcon#*before return 0, iclass 14, count 2 2006.201.10:47:18.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:18.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.10:47:18.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.10:47:18.43#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:18.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:18.52#abcon#<5=/05 1.9 4.2 21.56 981003.7\r\n> 2006.201.10:47:18.54#abcon#{5=INTERFACE CLEAR} 2006.201.10:47:18.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:18.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:18.55#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:47:18.55#ibcon#first serial, iclass 14, count 0 2006.201.10:47:18.55#ibcon#enter sib2, iclass 14, count 0 2006.201.10:47:18.55#ibcon#flushed, iclass 14, count 0 2006.201.10:47:18.55#ibcon#about to write, iclass 14, count 0 2006.201.10:47:18.55#ibcon#wrote, iclass 14, count 0 2006.201.10:47:18.55#ibcon#about to read 3, iclass 14, count 0 2006.201.10:47:18.57#ibcon#read 3, iclass 14, count 0 2006.201.10:47:18.57#ibcon#about to read 4, iclass 14, count 0 2006.201.10:47:18.57#ibcon#read 4, iclass 14, count 0 2006.201.10:47:18.57#ibcon#about to read 5, iclass 14, count 0 2006.201.10:47:18.57#ibcon#read 5, iclass 14, count 0 2006.201.10:47:18.57#ibcon#about to read 6, iclass 14, count 0 2006.201.10:47:18.57#ibcon#read 6, iclass 14, count 0 2006.201.10:47:18.57#ibcon#end of sib2, iclass 14, count 0 2006.201.10:47:18.57#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:47:18.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:47:18.57#ibcon#[27=USB\r\n] 2006.201.10:47:18.57#ibcon#*before write, iclass 14, count 0 2006.201.10:47:18.57#ibcon#enter sib2, iclass 14, count 0 2006.201.10:47:18.57#ibcon#flushed, iclass 14, count 0 2006.201.10:47:18.57#ibcon#about to write, iclass 14, count 0 2006.201.10:47:18.57#ibcon#wrote, iclass 14, count 0 2006.201.10:47:18.57#ibcon#about to read 3, iclass 14, count 0 2006.201.10:47:18.60#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:47:18.60#ibcon#read 3, iclass 14, count 0 2006.201.10:47:18.60#ibcon#about to read 4, iclass 14, count 0 2006.201.10:47:18.60#ibcon#read 4, iclass 14, count 0 2006.201.10:47:18.60#ibcon#about to read 5, iclass 14, count 0 2006.201.10:47:18.60#ibcon#read 5, iclass 14, count 0 2006.201.10:47:18.60#ibcon#about to read 6, iclass 14, count 0 2006.201.10:47:18.60#ibcon#read 6, iclass 14, count 0 2006.201.10:47:18.60#ibcon#end of sib2, iclass 14, count 0 2006.201.10:47:18.60#ibcon#*after write, iclass 14, count 0 2006.201.10:47:18.60#ibcon#*before return 0, iclass 14, count 0 2006.201.10:47:18.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:18.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.10:47:18.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:47:18.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:47:18.60$vck44/vblo=7,734.99 2006.201.10:47:18.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.10:47:18.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.10:47:18.60#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:18.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:18.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:18.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:18.60#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:47:18.60#ibcon#first serial, iclass 20, count 0 2006.201.10:47:18.60#ibcon#enter sib2, iclass 20, count 0 2006.201.10:47:18.60#ibcon#flushed, iclass 20, count 0 2006.201.10:47:18.60#ibcon#about to write, iclass 20, count 0 2006.201.10:47:18.60#ibcon#wrote, iclass 20, count 0 2006.201.10:47:18.60#ibcon#about to read 3, iclass 20, count 0 2006.201.10:47:18.62#ibcon#read 3, iclass 20, count 0 2006.201.10:47:18.62#ibcon#about to read 4, iclass 20, count 0 2006.201.10:47:18.62#ibcon#read 4, iclass 20, count 0 2006.201.10:47:18.62#ibcon#about to read 5, iclass 20, count 0 2006.201.10:47:18.62#ibcon#read 5, iclass 20, count 0 2006.201.10:47:18.62#ibcon#about to read 6, iclass 20, count 0 2006.201.10:47:18.62#ibcon#read 6, iclass 20, count 0 2006.201.10:47:18.62#ibcon#end of sib2, iclass 20, count 0 2006.201.10:47:18.62#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:47:18.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:47:18.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:47:18.62#ibcon#*before write, iclass 20, count 0 2006.201.10:47:18.62#ibcon#enter sib2, iclass 20, count 0 2006.201.10:47:18.62#ibcon#flushed, iclass 20, count 0 2006.201.10:47:18.62#ibcon#about to write, iclass 20, count 0 2006.201.10:47:18.62#ibcon#wrote, iclass 20, count 0 2006.201.10:47:18.62#ibcon#about to read 3, iclass 20, count 0 2006.201.10:47:18.66#ibcon#read 3, iclass 20, count 0 2006.201.10:47:18.66#ibcon#about to read 4, iclass 20, count 0 2006.201.10:47:18.66#ibcon#read 4, iclass 20, count 0 2006.201.10:47:18.66#ibcon#about to read 5, iclass 20, count 0 2006.201.10:47:18.66#ibcon#read 5, iclass 20, count 0 2006.201.10:47:18.66#ibcon#about to read 6, iclass 20, count 0 2006.201.10:47:18.66#ibcon#read 6, iclass 20, count 0 2006.201.10:47:18.66#ibcon#end of sib2, iclass 20, count 0 2006.201.10:47:18.66#ibcon#*after write, iclass 20, count 0 2006.201.10:47:18.66#ibcon#*before return 0, iclass 20, count 0 2006.201.10:47:18.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:18.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.10:47:18.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:47:18.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:47:18.66$vck44/vb=7,4 2006.201.10:47:18.66#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.10:47:18.66#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.10:47:18.66#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:18.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:18.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:18.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:18.72#ibcon#enter wrdev, iclass 22, count 2 2006.201.10:47:18.72#ibcon#first serial, iclass 22, count 2 2006.201.10:47:18.72#ibcon#enter sib2, iclass 22, count 2 2006.201.10:47:18.72#ibcon#flushed, iclass 22, count 2 2006.201.10:47:18.72#ibcon#about to write, iclass 22, count 2 2006.201.10:47:18.72#ibcon#wrote, iclass 22, count 2 2006.201.10:47:18.72#ibcon#about to read 3, iclass 22, count 2 2006.201.10:47:18.74#ibcon#read 3, iclass 22, count 2 2006.201.10:47:18.74#ibcon#about to read 4, iclass 22, count 2 2006.201.10:47:18.74#ibcon#read 4, iclass 22, count 2 2006.201.10:47:18.74#ibcon#about to read 5, iclass 22, count 2 2006.201.10:47:18.74#ibcon#read 5, iclass 22, count 2 2006.201.10:47:18.74#ibcon#about to read 6, iclass 22, count 2 2006.201.10:47:18.74#ibcon#read 6, iclass 22, count 2 2006.201.10:47:18.74#ibcon#end of sib2, iclass 22, count 2 2006.201.10:47:18.74#ibcon#*mode == 0, iclass 22, count 2 2006.201.10:47:18.74#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.10:47:18.74#ibcon#[27=AT07-04\r\n] 2006.201.10:47:18.74#ibcon#*before write, iclass 22, count 2 2006.201.10:47:18.74#ibcon#enter sib2, iclass 22, count 2 2006.201.10:47:18.74#ibcon#flushed, iclass 22, count 2 2006.201.10:47:18.74#ibcon#about to write, iclass 22, count 2 2006.201.10:47:18.74#ibcon#wrote, iclass 22, count 2 2006.201.10:47:18.74#ibcon#about to read 3, iclass 22, count 2 2006.201.10:47:18.77#ibcon#read 3, iclass 22, count 2 2006.201.10:47:18.77#ibcon#about to read 4, iclass 22, count 2 2006.201.10:47:18.77#ibcon#read 4, iclass 22, count 2 2006.201.10:47:18.77#ibcon#about to read 5, iclass 22, count 2 2006.201.10:47:18.77#ibcon#read 5, iclass 22, count 2 2006.201.10:47:18.77#ibcon#about to read 6, iclass 22, count 2 2006.201.10:47:18.77#ibcon#read 6, iclass 22, count 2 2006.201.10:47:18.77#ibcon#end of sib2, iclass 22, count 2 2006.201.10:47:18.77#ibcon#*after write, iclass 22, count 2 2006.201.10:47:18.77#ibcon#*before return 0, iclass 22, count 2 2006.201.10:47:18.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:18.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.10:47:18.77#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.10:47:18.77#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:18.77#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:18.89#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:18.89#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:18.89#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:47:18.89#ibcon#first serial, iclass 22, count 0 2006.201.10:47:18.89#ibcon#enter sib2, iclass 22, count 0 2006.201.10:47:18.89#ibcon#flushed, iclass 22, count 0 2006.201.10:47:18.89#ibcon#about to write, iclass 22, count 0 2006.201.10:47:18.89#ibcon#wrote, iclass 22, count 0 2006.201.10:47:18.89#ibcon#about to read 3, iclass 22, count 0 2006.201.10:47:18.91#ibcon#read 3, iclass 22, count 0 2006.201.10:47:18.91#ibcon#about to read 4, iclass 22, count 0 2006.201.10:47:18.91#ibcon#read 4, iclass 22, count 0 2006.201.10:47:18.91#ibcon#about to read 5, iclass 22, count 0 2006.201.10:47:18.91#ibcon#read 5, iclass 22, count 0 2006.201.10:47:18.91#ibcon#about to read 6, iclass 22, count 0 2006.201.10:47:18.91#ibcon#read 6, iclass 22, count 0 2006.201.10:47:18.91#ibcon#end of sib2, iclass 22, count 0 2006.201.10:47:18.91#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:47:18.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:47:18.91#ibcon#[27=USB\r\n] 2006.201.10:47:18.91#ibcon#*before write, iclass 22, count 0 2006.201.10:47:18.91#ibcon#enter sib2, iclass 22, count 0 2006.201.10:47:18.91#ibcon#flushed, iclass 22, count 0 2006.201.10:47:18.91#ibcon#about to write, iclass 22, count 0 2006.201.10:47:18.91#ibcon#wrote, iclass 22, count 0 2006.201.10:47:18.91#ibcon#about to read 3, iclass 22, count 0 2006.201.10:47:18.94#ibcon#read 3, iclass 22, count 0 2006.201.10:47:18.94#ibcon#about to read 4, iclass 22, count 0 2006.201.10:47:18.94#ibcon#read 4, iclass 22, count 0 2006.201.10:47:18.94#ibcon#about to read 5, iclass 22, count 0 2006.201.10:47:18.94#ibcon#read 5, iclass 22, count 0 2006.201.10:47:18.94#ibcon#about to read 6, iclass 22, count 0 2006.201.10:47:18.94#ibcon#read 6, iclass 22, count 0 2006.201.10:47:18.94#ibcon#end of sib2, iclass 22, count 0 2006.201.10:47:18.94#ibcon#*after write, iclass 22, count 0 2006.201.10:47:18.94#ibcon#*before return 0, iclass 22, count 0 2006.201.10:47:18.94#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:18.94#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.10:47:18.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:47:18.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:47:18.94$vck44/vblo=8,744.99 2006.201.10:47:18.94#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.10:47:18.94#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.10:47:18.94#ibcon#ireg 17 cls_cnt 0 2006.201.10:47:18.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:18.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:18.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:18.94#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:47:18.94#ibcon#first serial, iclass 24, count 0 2006.201.10:47:18.94#ibcon#enter sib2, iclass 24, count 0 2006.201.10:47:18.94#ibcon#flushed, iclass 24, count 0 2006.201.10:47:18.94#ibcon#about to write, iclass 24, count 0 2006.201.10:47:18.94#ibcon#wrote, iclass 24, count 0 2006.201.10:47:18.94#ibcon#about to read 3, iclass 24, count 0 2006.201.10:47:18.96#ibcon#read 3, iclass 24, count 0 2006.201.10:47:18.96#ibcon#about to read 4, iclass 24, count 0 2006.201.10:47:18.96#ibcon#read 4, iclass 24, count 0 2006.201.10:47:18.96#ibcon#about to read 5, iclass 24, count 0 2006.201.10:47:18.96#ibcon#read 5, iclass 24, count 0 2006.201.10:47:18.96#ibcon#about to read 6, iclass 24, count 0 2006.201.10:47:18.96#ibcon#read 6, iclass 24, count 0 2006.201.10:47:18.96#ibcon#end of sib2, iclass 24, count 0 2006.201.10:47:18.96#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:47:18.96#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:47:18.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:47:18.96#ibcon#*before write, iclass 24, count 0 2006.201.10:47:18.96#ibcon#enter sib2, iclass 24, count 0 2006.201.10:47:18.96#ibcon#flushed, iclass 24, count 0 2006.201.10:47:18.96#ibcon#about to write, iclass 24, count 0 2006.201.10:47:18.96#ibcon#wrote, iclass 24, count 0 2006.201.10:47:18.96#ibcon#about to read 3, iclass 24, count 0 2006.201.10:47:19.01#ibcon#read 3, iclass 24, count 0 2006.201.10:47:19.01#ibcon#about to read 4, iclass 24, count 0 2006.201.10:47:19.01#ibcon#read 4, iclass 24, count 0 2006.201.10:47:19.01#ibcon#about to read 5, iclass 24, count 0 2006.201.10:47:19.01#ibcon#read 5, iclass 24, count 0 2006.201.10:47:19.01#ibcon#about to read 6, iclass 24, count 0 2006.201.10:47:19.01#ibcon#read 6, iclass 24, count 0 2006.201.10:47:19.01#ibcon#end of sib2, iclass 24, count 0 2006.201.10:47:19.01#ibcon#*after write, iclass 24, count 0 2006.201.10:47:19.01#ibcon#*before return 0, iclass 24, count 0 2006.201.10:47:19.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:19.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.10:47:19.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:47:19.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:47:19.01$vck44/vb=8,4 2006.201.10:47:19.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.10:47:19.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.10:47:19.01#ibcon#ireg 11 cls_cnt 2 2006.201.10:47:19.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:19.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:19.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:19.06#ibcon#enter wrdev, iclass 26, count 2 2006.201.10:47:19.06#ibcon#first serial, iclass 26, count 2 2006.201.10:47:19.06#ibcon#enter sib2, iclass 26, count 2 2006.201.10:47:19.06#ibcon#flushed, iclass 26, count 2 2006.201.10:47:19.06#ibcon#about to write, iclass 26, count 2 2006.201.10:47:19.06#ibcon#wrote, iclass 26, count 2 2006.201.10:47:19.06#ibcon#about to read 3, iclass 26, count 2 2006.201.10:47:19.08#ibcon#read 3, iclass 26, count 2 2006.201.10:47:19.08#ibcon#about to read 4, iclass 26, count 2 2006.201.10:47:19.08#ibcon#read 4, iclass 26, count 2 2006.201.10:47:19.08#ibcon#about to read 5, iclass 26, count 2 2006.201.10:47:19.08#ibcon#read 5, iclass 26, count 2 2006.201.10:47:19.08#ibcon#about to read 6, iclass 26, count 2 2006.201.10:47:19.08#ibcon#read 6, iclass 26, count 2 2006.201.10:47:19.08#ibcon#end of sib2, iclass 26, count 2 2006.201.10:47:19.08#ibcon#*mode == 0, iclass 26, count 2 2006.201.10:47:19.08#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.10:47:19.08#ibcon#[27=AT08-04\r\n] 2006.201.10:47:19.08#ibcon#*before write, iclass 26, count 2 2006.201.10:47:19.08#ibcon#enter sib2, iclass 26, count 2 2006.201.10:47:19.08#ibcon#flushed, iclass 26, count 2 2006.201.10:47:19.08#ibcon#about to write, iclass 26, count 2 2006.201.10:47:19.08#ibcon#wrote, iclass 26, count 2 2006.201.10:47:19.08#ibcon#about to read 3, iclass 26, count 2 2006.201.10:47:19.11#ibcon#read 3, iclass 26, count 2 2006.201.10:47:19.11#ibcon#about to read 4, iclass 26, count 2 2006.201.10:47:19.11#ibcon#read 4, iclass 26, count 2 2006.201.10:47:19.11#ibcon#about to read 5, iclass 26, count 2 2006.201.10:47:19.11#ibcon#read 5, iclass 26, count 2 2006.201.10:47:19.11#ibcon#about to read 6, iclass 26, count 2 2006.201.10:47:19.11#ibcon#read 6, iclass 26, count 2 2006.201.10:47:19.11#ibcon#end of sib2, iclass 26, count 2 2006.201.10:47:19.11#ibcon#*after write, iclass 26, count 2 2006.201.10:47:19.11#ibcon#*before return 0, iclass 26, count 2 2006.201.10:47:19.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:19.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.10:47:19.11#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.10:47:19.11#ibcon#ireg 7 cls_cnt 0 2006.201.10:47:19.11#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:19.23#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:19.23#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:19.23#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:47:19.23#ibcon#first serial, iclass 26, count 0 2006.201.10:47:19.23#ibcon#enter sib2, iclass 26, count 0 2006.201.10:47:19.23#ibcon#flushed, iclass 26, count 0 2006.201.10:47:19.23#ibcon#about to write, iclass 26, count 0 2006.201.10:47:19.23#ibcon#wrote, iclass 26, count 0 2006.201.10:47:19.23#ibcon#about to read 3, iclass 26, count 0 2006.201.10:47:19.25#ibcon#read 3, iclass 26, count 0 2006.201.10:47:19.25#ibcon#about to read 4, iclass 26, count 0 2006.201.10:47:19.25#ibcon#read 4, iclass 26, count 0 2006.201.10:47:19.25#ibcon#about to read 5, iclass 26, count 0 2006.201.10:47:19.25#ibcon#read 5, iclass 26, count 0 2006.201.10:47:19.25#ibcon#about to read 6, iclass 26, count 0 2006.201.10:47:19.25#ibcon#read 6, iclass 26, count 0 2006.201.10:47:19.25#ibcon#end of sib2, iclass 26, count 0 2006.201.10:47:19.25#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:47:19.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:47:19.25#ibcon#[27=USB\r\n] 2006.201.10:47:19.25#ibcon#*before write, iclass 26, count 0 2006.201.10:47:19.25#ibcon#enter sib2, iclass 26, count 0 2006.201.10:47:19.25#ibcon#flushed, iclass 26, count 0 2006.201.10:47:19.25#ibcon#about to write, iclass 26, count 0 2006.201.10:47:19.25#ibcon#wrote, iclass 26, count 0 2006.201.10:47:19.25#ibcon#about to read 3, iclass 26, count 0 2006.201.10:47:19.28#ibcon#read 3, iclass 26, count 0 2006.201.10:47:19.28#ibcon#about to read 4, iclass 26, count 0 2006.201.10:47:19.28#ibcon#read 4, iclass 26, count 0 2006.201.10:47:19.28#ibcon#about to read 5, iclass 26, count 0 2006.201.10:47:19.28#ibcon#read 5, iclass 26, count 0 2006.201.10:47:19.28#ibcon#about to read 6, iclass 26, count 0 2006.201.10:47:19.28#ibcon#read 6, iclass 26, count 0 2006.201.10:47:19.28#ibcon#end of sib2, iclass 26, count 0 2006.201.10:47:19.28#ibcon#*after write, iclass 26, count 0 2006.201.10:47:19.28#ibcon#*before return 0, iclass 26, count 0 2006.201.10:47:19.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:19.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.10:47:19.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:47:19.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:47:19.28$vck44/vabw=wide 2006.201.10:47:19.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.10:47:19.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.10:47:19.28#ibcon#ireg 8 cls_cnt 0 2006.201.10:47:19.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:19.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:19.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:19.28#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:47:19.28#ibcon#first serial, iclass 28, count 0 2006.201.10:47:19.28#ibcon#enter sib2, iclass 28, count 0 2006.201.10:47:19.28#ibcon#flushed, iclass 28, count 0 2006.201.10:47:19.28#ibcon#about to write, iclass 28, count 0 2006.201.10:47:19.28#ibcon#wrote, iclass 28, count 0 2006.201.10:47:19.28#ibcon#about to read 3, iclass 28, count 0 2006.201.10:47:19.30#ibcon#read 3, iclass 28, count 0 2006.201.10:47:19.30#ibcon#about to read 4, iclass 28, count 0 2006.201.10:47:19.30#ibcon#read 4, iclass 28, count 0 2006.201.10:47:19.30#ibcon#about to read 5, iclass 28, count 0 2006.201.10:47:19.30#ibcon#read 5, iclass 28, count 0 2006.201.10:47:19.30#ibcon#about to read 6, iclass 28, count 0 2006.201.10:47:19.30#ibcon#read 6, iclass 28, count 0 2006.201.10:47:19.30#ibcon#end of sib2, iclass 28, count 0 2006.201.10:47:19.30#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:47:19.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:47:19.30#ibcon#[25=BW32\r\n] 2006.201.10:47:19.30#ibcon#*before write, iclass 28, count 0 2006.201.10:47:19.30#ibcon#enter sib2, iclass 28, count 0 2006.201.10:47:19.30#ibcon#flushed, iclass 28, count 0 2006.201.10:47:19.30#ibcon#about to write, iclass 28, count 0 2006.201.10:47:19.30#ibcon#wrote, iclass 28, count 0 2006.201.10:47:19.30#ibcon#about to read 3, iclass 28, count 0 2006.201.10:47:19.33#ibcon#read 3, iclass 28, count 0 2006.201.10:47:19.33#ibcon#about to read 4, iclass 28, count 0 2006.201.10:47:19.33#ibcon#read 4, iclass 28, count 0 2006.201.10:47:19.33#ibcon#about to read 5, iclass 28, count 0 2006.201.10:47:19.33#ibcon#read 5, iclass 28, count 0 2006.201.10:47:19.33#ibcon#about to read 6, iclass 28, count 0 2006.201.10:47:19.33#ibcon#read 6, iclass 28, count 0 2006.201.10:47:19.33#ibcon#end of sib2, iclass 28, count 0 2006.201.10:47:19.33#ibcon#*after write, iclass 28, count 0 2006.201.10:47:19.33#ibcon#*before return 0, iclass 28, count 0 2006.201.10:47:19.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:19.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:47:19.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:47:19.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:47:19.33$vck44/vbbw=wide 2006.201.10:47:19.33#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.10:47:19.33#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.10:47:19.33#ibcon#ireg 8 cls_cnt 0 2006.201.10:47:19.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:47:19.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:47:19.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:47:19.40#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:47:19.40#ibcon#first serial, iclass 30, count 0 2006.201.10:47:19.40#ibcon#enter sib2, iclass 30, count 0 2006.201.10:47:19.40#ibcon#flushed, iclass 30, count 0 2006.201.10:47:19.40#ibcon#about to write, iclass 30, count 0 2006.201.10:47:19.40#ibcon#wrote, iclass 30, count 0 2006.201.10:47:19.40#ibcon#about to read 3, iclass 30, count 0 2006.201.10:47:19.42#ibcon#read 3, iclass 30, count 0 2006.201.10:47:19.42#ibcon#about to read 4, iclass 30, count 0 2006.201.10:47:19.42#ibcon#read 4, iclass 30, count 0 2006.201.10:47:19.42#ibcon#about to read 5, iclass 30, count 0 2006.201.10:47:19.42#ibcon#read 5, iclass 30, count 0 2006.201.10:47:19.42#ibcon#about to read 6, iclass 30, count 0 2006.201.10:47:19.42#ibcon#read 6, iclass 30, count 0 2006.201.10:47:19.42#ibcon#end of sib2, iclass 30, count 0 2006.201.10:47:19.42#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:47:19.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:47:19.42#ibcon#[27=BW32\r\n] 2006.201.10:47:19.42#ibcon#*before write, iclass 30, count 0 2006.201.10:47:19.42#ibcon#enter sib2, iclass 30, count 0 2006.201.10:47:19.42#ibcon#flushed, iclass 30, count 0 2006.201.10:47:19.42#ibcon#about to write, iclass 30, count 0 2006.201.10:47:19.42#ibcon#wrote, iclass 30, count 0 2006.201.10:47:19.42#ibcon#about to read 3, iclass 30, count 0 2006.201.10:47:19.45#ibcon#read 3, iclass 30, count 0 2006.201.10:47:19.45#ibcon#about to read 4, iclass 30, count 0 2006.201.10:47:19.45#ibcon#read 4, iclass 30, count 0 2006.201.10:47:19.45#ibcon#about to read 5, iclass 30, count 0 2006.201.10:47:19.45#ibcon#read 5, iclass 30, count 0 2006.201.10:47:19.45#ibcon#about to read 6, iclass 30, count 0 2006.201.10:47:19.45#ibcon#read 6, iclass 30, count 0 2006.201.10:47:19.45#ibcon#end of sib2, iclass 30, count 0 2006.201.10:47:19.45#ibcon#*after write, iclass 30, count 0 2006.201.10:47:19.45#ibcon#*before return 0, iclass 30, count 0 2006.201.10:47:19.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:47:19.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:47:19.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:47:19.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:47:19.45$setupk4/ifdk4 2006.201.10:47:19.45$ifdk4/lo= 2006.201.10:47:19.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:47:19.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:47:19.45$ifdk4/patch= 2006.201.10:47:19.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:47:19.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:47:19.45$setupk4/!*+20s 2006.201.10:47:28.69#abcon#<5=/05 1.9 4.2 21.55 981003.7\r\n> 2006.201.10:47:28.71#abcon#{5=INTERFACE CLEAR} 2006.201.10:47:28.77#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:47:33.92$setupk4/"tpicd 2006.201.10:47:33.92$setupk4/echo=off 2006.201.10:47:33.92$setupk4/xlog=off 2006.201.10:47:33.92:!2006.201.10:48:50 2006.201.10:47:42.14#trakl#Source acquired 2006.201.10:47:42.14#flagr#flagr/antenna,acquired 2006.201.10:48:50.00:preob 2006.201.10:48:50.14/onsource/TRACKING 2006.201.10:48:50.14:!2006.201.10:49:00 2006.201.10:49:00.00:"tape 2006.201.10:49:00.00:"st=record 2006.201.10:49:00.00:data_valid=on 2006.201.10:49:00.00:midob 2006.201.10:49:00.14/onsource/TRACKING 2006.201.10:49:00.14/wx/21.54,1003.7,99 2006.201.10:49:00.31/cable/+6.4703E-03 2006.201.10:49:01.40/va/01,08,usb,yes,28,30 2006.201.10:49:01.40/va/02,07,usb,yes,30,31 2006.201.10:49:01.40/va/03,08,usb,yes,27,28 2006.201.10:49:01.40/va/04,07,usb,yes,31,33 2006.201.10:49:01.40/va/05,04,usb,yes,27,28 2006.201.10:49:01.40/va/06,05,usb,yes,27,27 2006.201.10:49:01.40/va/07,05,usb,yes,27,28 2006.201.10:49:01.40/va/08,04,usb,yes,26,32 2006.201.10:49:01.63/valo/01,524.99,yes,locked 2006.201.10:49:01.63/valo/02,534.99,yes,locked 2006.201.10:49:01.63/valo/03,564.99,yes,locked 2006.201.10:49:01.63/valo/04,624.99,yes,locked 2006.201.10:49:01.63/valo/05,734.99,yes,locked 2006.201.10:49:01.63/valo/06,814.99,yes,locked 2006.201.10:49:01.63/valo/07,864.99,yes,locked 2006.201.10:49:01.63/valo/08,884.99,yes,locked 2006.201.10:49:02.72/vb/01,04,usb,yes,29,27 2006.201.10:49:02.72/vb/02,05,usb,yes,27,27 2006.201.10:49:02.72/vb/03,04,usb,yes,28,31 2006.201.10:49:02.72/vb/04,05,usb,yes,28,27 2006.201.10:49:02.72/vb/05,04,usb,yes,25,27 2006.201.10:49:02.72/vb/06,04,usb,yes,29,25 2006.201.10:49:02.72/vb/07,04,usb,yes,29,29 2006.201.10:49:02.72/vb/08,04,usb,yes,27,30 2006.201.10:49:02.96/vblo/01,629.99,yes,locked 2006.201.10:49:02.96/vblo/02,634.99,yes,locked 2006.201.10:49:02.96/vblo/03,649.99,yes,locked 2006.201.10:49:02.96/vblo/04,679.99,yes,locked 2006.201.10:49:02.96/vblo/05,709.99,yes,locked 2006.201.10:49:02.96/vblo/06,719.99,yes,locked 2006.201.10:49:02.96/vblo/07,734.99,yes,locked 2006.201.10:49:02.96/vblo/08,744.99,yes,locked 2006.201.10:49:03.11/vabw/8 2006.201.10:49:03.26/vbbw/8 2006.201.10:49:03.35/xfe/off,on,15.2 2006.201.10:49:03.73/ifatt/23,28,28,28 2006.201.10:49:04.05/fmout-gps/S +4.55E-07 2006.201.10:49:04.10:!2006.201.10:49:40 2006.201.10:49:40.00:data_valid=off 2006.201.10:49:40.00:"et 2006.201.10:49:40.00:!+3s 2006.201.10:49:43.01:"tape 2006.201.10:49:43.01:postob 2006.201.10:49:43.20/cable/+6.4696E-03 2006.201.10:49:43.20/wx/21.53,1003.7,99 2006.201.10:49:43.27/fmout-gps/S +4.55E-07 2006.201.10:49:43.27:scan_name=201-1050,jd0607,40 2006.201.10:49:43.27:source=1424-418,142756.30,-420619.4,2000.0,ccw 2006.201.10:49:45.14#flagr#flagr/antenna,new-source 2006.201.10:49:45.14:checkk5 2006.201.10:49:45.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:49:45.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:49:46.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:49:46.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:49:47.01/chk_obsdata//k5ts1/T2011049??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:49:47.38/chk_obsdata//k5ts2/T2011049??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:49:47.75/chk_obsdata//k5ts3/T2011049??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:49:48.11/chk_obsdata//k5ts4/T2011049??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:49:48.80/k5log//k5ts1_log_newline 2006.201.10:49:49.49/k5log//k5ts2_log_newline 2006.201.10:49:50.18/k5log//k5ts3_log_newline 2006.201.10:49:50.86/k5log//k5ts4_log_newline 2006.201.10:49:50.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:49:50.89:setupk4=1 2006.201.10:49:50.89$setupk4/echo=on 2006.201.10:49:50.89$setupk4/pcalon 2006.201.10:49:50.89$pcalon/"no phase cal control is implemented here 2006.201.10:49:50.89$setupk4/"tpicd=stop 2006.201.10:49:50.89$setupk4/"rec=synch_on 2006.201.10:49:50.89$setupk4/"rec_mode=128 2006.201.10:49:50.89$setupk4/!* 2006.201.10:49:50.89$setupk4/recpk4 2006.201.10:49:50.89$recpk4/recpatch= 2006.201.10:49:50.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:49:50.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:49:50.89$setupk4/vck44 2006.201.10:49:50.89$vck44/valo=1,524.99 2006.201.10:49:50.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.10:49:50.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.10:49:50.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:50.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:50.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:50.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:50.89#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:49:50.89#ibcon#first serial, iclass 19, count 0 2006.201.10:49:50.89#ibcon#enter sib2, iclass 19, count 0 2006.201.10:49:50.89#ibcon#flushed, iclass 19, count 0 2006.201.10:49:50.89#ibcon#about to write, iclass 19, count 0 2006.201.10:49:50.89#ibcon#wrote, iclass 19, count 0 2006.201.10:49:50.89#ibcon#about to read 3, iclass 19, count 0 2006.201.10:49:50.93#ibcon#read 3, iclass 19, count 0 2006.201.10:49:50.93#ibcon#about to read 4, iclass 19, count 0 2006.201.10:49:50.93#ibcon#read 4, iclass 19, count 0 2006.201.10:49:50.93#ibcon#about to read 5, iclass 19, count 0 2006.201.10:49:50.93#ibcon#read 5, iclass 19, count 0 2006.201.10:49:50.93#ibcon#about to read 6, iclass 19, count 0 2006.201.10:49:50.93#ibcon#read 6, iclass 19, count 0 2006.201.10:49:50.93#ibcon#end of sib2, iclass 19, count 0 2006.201.10:49:50.93#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:49:50.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:49:50.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:49:50.93#ibcon#*before write, iclass 19, count 0 2006.201.10:49:50.93#ibcon#enter sib2, iclass 19, count 0 2006.201.10:49:50.93#ibcon#flushed, iclass 19, count 0 2006.201.10:49:50.93#ibcon#about to write, iclass 19, count 0 2006.201.10:49:50.93#ibcon#wrote, iclass 19, count 0 2006.201.10:49:50.93#ibcon#about to read 3, iclass 19, count 0 2006.201.10:49:50.98#ibcon#read 3, iclass 19, count 0 2006.201.10:49:50.98#ibcon#about to read 4, iclass 19, count 0 2006.201.10:49:50.98#ibcon#read 4, iclass 19, count 0 2006.201.10:49:50.98#ibcon#about to read 5, iclass 19, count 0 2006.201.10:49:50.98#ibcon#read 5, iclass 19, count 0 2006.201.10:49:50.98#ibcon#about to read 6, iclass 19, count 0 2006.201.10:49:50.98#ibcon#read 6, iclass 19, count 0 2006.201.10:49:50.98#ibcon#end of sib2, iclass 19, count 0 2006.201.10:49:50.98#ibcon#*after write, iclass 19, count 0 2006.201.10:49:50.98#ibcon#*before return 0, iclass 19, count 0 2006.201.10:49:50.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:50.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:50.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:49:50.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:49:50.98$vck44/va=1,8 2006.201.10:49:50.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.10:49:50.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.10:49:50.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:50.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:50.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:50.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:50.98#ibcon#enter wrdev, iclass 21, count 2 2006.201.10:49:50.98#ibcon#first serial, iclass 21, count 2 2006.201.10:49:50.98#ibcon#enter sib2, iclass 21, count 2 2006.201.10:49:50.98#ibcon#flushed, iclass 21, count 2 2006.201.10:49:50.98#ibcon#about to write, iclass 21, count 2 2006.201.10:49:50.98#ibcon#wrote, iclass 21, count 2 2006.201.10:49:50.98#ibcon#about to read 3, iclass 21, count 2 2006.201.10:49:51.00#ibcon#read 3, iclass 21, count 2 2006.201.10:49:51.00#ibcon#about to read 4, iclass 21, count 2 2006.201.10:49:51.00#ibcon#read 4, iclass 21, count 2 2006.201.10:49:51.00#ibcon#about to read 5, iclass 21, count 2 2006.201.10:49:51.00#ibcon#read 5, iclass 21, count 2 2006.201.10:49:51.00#ibcon#about to read 6, iclass 21, count 2 2006.201.10:49:51.00#ibcon#read 6, iclass 21, count 2 2006.201.10:49:51.00#ibcon#end of sib2, iclass 21, count 2 2006.201.10:49:51.00#ibcon#*mode == 0, iclass 21, count 2 2006.201.10:49:51.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.10:49:51.00#ibcon#[25=AT01-08\r\n] 2006.201.10:49:51.00#ibcon#*before write, iclass 21, count 2 2006.201.10:49:51.00#ibcon#enter sib2, iclass 21, count 2 2006.201.10:49:51.00#ibcon#flushed, iclass 21, count 2 2006.201.10:49:51.00#ibcon#about to write, iclass 21, count 2 2006.201.10:49:51.00#ibcon#wrote, iclass 21, count 2 2006.201.10:49:51.00#ibcon#about to read 3, iclass 21, count 2 2006.201.10:49:51.03#ibcon#read 3, iclass 21, count 2 2006.201.10:49:51.03#ibcon#about to read 4, iclass 21, count 2 2006.201.10:49:51.03#ibcon#read 4, iclass 21, count 2 2006.201.10:49:51.03#ibcon#about to read 5, iclass 21, count 2 2006.201.10:49:51.03#ibcon#read 5, iclass 21, count 2 2006.201.10:49:51.03#ibcon#about to read 6, iclass 21, count 2 2006.201.10:49:51.03#ibcon#read 6, iclass 21, count 2 2006.201.10:49:51.03#ibcon#end of sib2, iclass 21, count 2 2006.201.10:49:51.03#ibcon#*after write, iclass 21, count 2 2006.201.10:49:51.03#ibcon#*before return 0, iclass 21, count 2 2006.201.10:49:51.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:51.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:51.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.10:49:51.03#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:51.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:51.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:51.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:51.15#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:49:51.15#ibcon#first serial, iclass 21, count 0 2006.201.10:49:51.15#ibcon#enter sib2, iclass 21, count 0 2006.201.10:49:51.15#ibcon#flushed, iclass 21, count 0 2006.201.10:49:51.15#ibcon#about to write, iclass 21, count 0 2006.201.10:49:51.15#ibcon#wrote, iclass 21, count 0 2006.201.10:49:51.15#ibcon#about to read 3, iclass 21, count 0 2006.201.10:49:51.17#ibcon#read 3, iclass 21, count 0 2006.201.10:49:51.17#ibcon#about to read 4, iclass 21, count 0 2006.201.10:49:51.17#ibcon#read 4, iclass 21, count 0 2006.201.10:49:51.17#ibcon#about to read 5, iclass 21, count 0 2006.201.10:49:51.17#ibcon#read 5, iclass 21, count 0 2006.201.10:49:51.17#ibcon#about to read 6, iclass 21, count 0 2006.201.10:49:51.17#ibcon#read 6, iclass 21, count 0 2006.201.10:49:51.17#ibcon#end of sib2, iclass 21, count 0 2006.201.10:49:51.17#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:49:51.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:49:51.17#ibcon#[25=USB\r\n] 2006.201.10:49:51.17#ibcon#*before write, iclass 21, count 0 2006.201.10:49:51.17#ibcon#enter sib2, iclass 21, count 0 2006.201.10:49:51.17#ibcon#flushed, iclass 21, count 0 2006.201.10:49:51.17#ibcon#about to write, iclass 21, count 0 2006.201.10:49:51.17#ibcon#wrote, iclass 21, count 0 2006.201.10:49:51.17#ibcon#about to read 3, iclass 21, count 0 2006.201.10:49:51.17#abcon#<5=/05 1.8 3.1 21.53 991003.7\r\n> 2006.201.10:49:51.19#abcon#{5=INTERFACE CLEAR} 2006.201.10:49:51.20#ibcon#read 3, iclass 21, count 0 2006.201.10:49:51.20#ibcon#about to read 4, iclass 21, count 0 2006.201.10:49:51.20#ibcon#read 4, iclass 21, count 0 2006.201.10:49:51.20#ibcon#about to read 5, iclass 21, count 0 2006.201.10:49:51.20#ibcon#read 5, iclass 21, count 0 2006.201.10:49:51.20#ibcon#about to read 6, iclass 21, count 0 2006.201.10:49:51.20#ibcon#read 6, iclass 21, count 0 2006.201.10:49:51.20#ibcon#end of sib2, iclass 21, count 0 2006.201.10:49:51.20#ibcon#*after write, iclass 21, count 0 2006.201.10:49:51.20#ibcon#*before return 0, iclass 21, count 0 2006.201.10:49:51.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:51.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:51.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:49:51.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:49:51.20$vck44/valo=2,534.99 2006.201.10:49:51.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.10:49:51.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.10:49:51.20#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:51.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:49:51.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:49:51.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:49:51.20#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:49:51.20#ibcon#first serial, iclass 26, count 0 2006.201.10:49:51.20#ibcon#enter sib2, iclass 26, count 0 2006.201.10:49:51.20#ibcon#flushed, iclass 26, count 0 2006.201.10:49:51.20#ibcon#about to write, iclass 26, count 0 2006.201.10:49:51.20#ibcon#wrote, iclass 26, count 0 2006.201.10:49:51.20#ibcon#about to read 3, iclass 26, count 0 2006.201.10:49:51.22#ibcon#read 3, iclass 26, count 0 2006.201.10:49:51.22#ibcon#about to read 4, iclass 26, count 0 2006.201.10:49:51.22#ibcon#read 4, iclass 26, count 0 2006.201.10:49:51.22#ibcon#about to read 5, iclass 26, count 0 2006.201.10:49:51.22#ibcon#read 5, iclass 26, count 0 2006.201.10:49:51.22#ibcon#about to read 6, iclass 26, count 0 2006.201.10:49:51.22#ibcon#read 6, iclass 26, count 0 2006.201.10:49:51.22#ibcon#end of sib2, iclass 26, count 0 2006.201.10:49:51.22#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:49:51.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:49:51.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:49:51.22#ibcon#*before write, iclass 26, count 0 2006.201.10:49:51.22#ibcon#enter sib2, iclass 26, count 0 2006.201.10:49:51.22#ibcon#flushed, iclass 26, count 0 2006.201.10:49:51.22#ibcon#about to write, iclass 26, count 0 2006.201.10:49:51.22#ibcon#wrote, iclass 26, count 0 2006.201.10:49:51.22#ibcon#about to read 3, iclass 26, count 0 2006.201.10:49:51.25#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:49:51.26#ibcon#read 3, iclass 26, count 0 2006.201.10:49:51.26#ibcon#about to read 4, iclass 26, count 0 2006.201.10:49:51.26#ibcon#read 4, iclass 26, count 0 2006.201.10:49:51.26#ibcon#about to read 5, iclass 26, count 0 2006.201.10:49:51.26#ibcon#read 5, iclass 26, count 0 2006.201.10:49:51.26#ibcon#about to read 6, iclass 26, count 0 2006.201.10:49:51.26#ibcon#read 6, iclass 26, count 0 2006.201.10:49:51.26#ibcon#end of sib2, iclass 26, count 0 2006.201.10:49:51.26#ibcon#*after write, iclass 26, count 0 2006.201.10:49:51.26#ibcon#*before return 0, iclass 26, count 0 2006.201.10:49:51.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:49:51.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:49:51.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:49:51.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:49:51.26$vck44/va=2,7 2006.201.10:49:51.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.10:49:51.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.10:49:51.26#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:51.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:51.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:51.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:51.32#ibcon#enter wrdev, iclass 29, count 2 2006.201.10:49:51.32#ibcon#first serial, iclass 29, count 2 2006.201.10:49:51.32#ibcon#enter sib2, iclass 29, count 2 2006.201.10:49:51.32#ibcon#flushed, iclass 29, count 2 2006.201.10:49:51.32#ibcon#about to write, iclass 29, count 2 2006.201.10:49:51.32#ibcon#wrote, iclass 29, count 2 2006.201.10:49:51.32#ibcon#about to read 3, iclass 29, count 2 2006.201.10:49:51.34#ibcon#read 3, iclass 29, count 2 2006.201.10:49:51.34#ibcon#about to read 4, iclass 29, count 2 2006.201.10:49:51.34#ibcon#read 4, iclass 29, count 2 2006.201.10:49:51.34#ibcon#about to read 5, iclass 29, count 2 2006.201.10:49:51.34#ibcon#read 5, iclass 29, count 2 2006.201.10:49:51.34#ibcon#about to read 6, iclass 29, count 2 2006.201.10:49:51.34#ibcon#read 6, iclass 29, count 2 2006.201.10:49:51.34#ibcon#end of sib2, iclass 29, count 2 2006.201.10:49:51.34#ibcon#*mode == 0, iclass 29, count 2 2006.201.10:49:51.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.10:49:51.34#ibcon#[25=AT02-07\r\n] 2006.201.10:49:51.34#ibcon#*before write, iclass 29, count 2 2006.201.10:49:51.34#ibcon#enter sib2, iclass 29, count 2 2006.201.10:49:51.34#ibcon#flushed, iclass 29, count 2 2006.201.10:49:51.34#ibcon#about to write, iclass 29, count 2 2006.201.10:49:51.34#ibcon#wrote, iclass 29, count 2 2006.201.10:49:51.34#ibcon#about to read 3, iclass 29, count 2 2006.201.10:49:51.37#ibcon#read 3, iclass 29, count 2 2006.201.10:49:51.37#ibcon#about to read 4, iclass 29, count 2 2006.201.10:49:51.37#ibcon#read 4, iclass 29, count 2 2006.201.10:49:51.37#ibcon#about to read 5, iclass 29, count 2 2006.201.10:49:51.37#ibcon#read 5, iclass 29, count 2 2006.201.10:49:51.37#ibcon#about to read 6, iclass 29, count 2 2006.201.10:49:51.37#ibcon#read 6, iclass 29, count 2 2006.201.10:49:51.37#ibcon#end of sib2, iclass 29, count 2 2006.201.10:49:51.37#ibcon#*after write, iclass 29, count 2 2006.201.10:49:51.37#ibcon#*before return 0, iclass 29, count 2 2006.201.10:49:51.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:51.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:51.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.10:49:51.37#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:51.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:51.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:51.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:51.49#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:49:51.49#ibcon#first serial, iclass 29, count 0 2006.201.10:49:51.49#ibcon#enter sib2, iclass 29, count 0 2006.201.10:49:51.49#ibcon#flushed, iclass 29, count 0 2006.201.10:49:51.49#ibcon#about to write, iclass 29, count 0 2006.201.10:49:51.49#ibcon#wrote, iclass 29, count 0 2006.201.10:49:51.49#ibcon#about to read 3, iclass 29, count 0 2006.201.10:49:51.51#ibcon#read 3, iclass 29, count 0 2006.201.10:49:51.51#ibcon#about to read 4, iclass 29, count 0 2006.201.10:49:51.51#ibcon#read 4, iclass 29, count 0 2006.201.10:49:51.51#ibcon#about to read 5, iclass 29, count 0 2006.201.10:49:51.51#ibcon#read 5, iclass 29, count 0 2006.201.10:49:51.51#ibcon#about to read 6, iclass 29, count 0 2006.201.10:49:51.51#ibcon#read 6, iclass 29, count 0 2006.201.10:49:51.51#ibcon#end of sib2, iclass 29, count 0 2006.201.10:49:51.51#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:49:51.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:49:51.51#ibcon#[25=USB\r\n] 2006.201.10:49:51.51#ibcon#*before write, iclass 29, count 0 2006.201.10:49:51.51#ibcon#enter sib2, iclass 29, count 0 2006.201.10:49:51.51#ibcon#flushed, iclass 29, count 0 2006.201.10:49:51.51#ibcon#about to write, iclass 29, count 0 2006.201.10:49:51.51#ibcon#wrote, iclass 29, count 0 2006.201.10:49:51.51#ibcon#about to read 3, iclass 29, count 0 2006.201.10:49:51.54#ibcon#read 3, iclass 29, count 0 2006.201.10:49:51.54#ibcon#about to read 4, iclass 29, count 0 2006.201.10:49:51.54#ibcon#read 4, iclass 29, count 0 2006.201.10:49:51.54#ibcon#about to read 5, iclass 29, count 0 2006.201.10:49:51.54#ibcon#read 5, iclass 29, count 0 2006.201.10:49:51.54#ibcon#about to read 6, iclass 29, count 0 2006.201.10:49:51.54#ibcon#read 6, iclass 29, count 0 2006.201.10:49:51.54#ibcon#end of sib2, iclass 29, count 0 2006.201.10:49:51.54#ibcon#*after write, iclass 29, count 0 2006.201.10:49:51.54#ibcon#*before return 0, iclass 29, count 0 2006.201.10:49:51.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:51.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:51.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:49:51.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:49:51.54$vck44/valo=3,564.99 2006.201.10:49:51.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.10:49:51.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.10:49:51.54#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:51.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:51.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:51.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:51.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:49:51.54#ibcon#first serial, iclass 31, count 0 2006.201.10:49:51.54#ibcon#enter sib2, iclass 31, count 0 2006.201.10:49:51.54#ibcon#flushed, iclass 31, count 0 2006.201.10:49:51.54#ibcon#about to write, iclass 31, count 0 2006.201.10:49:51.54#ibcon#wrote, iclass 31, count 0 2006.201.10:49:51.54#ibcon#about to read 3, iclass 31, count 0 2006.201.10:49:51.56#ibcon#read 3, iclass 31, count 0 2006.201.10:49:51.56#ibcon#about to read 4, iclass 31, count 0 2006.201.10:49:51.56#ibcon#read 4, iclass 31, count 0 2006.201.10:49:51.56#ibcon#about to read 5, iclass 31, count 0 2006.201.10:49:51.56#ibcon#read 5, iclass 31, count 0 2006.201.10:49:51.56#ibcon#about to read 6, iclass 31, count 0 2006.201.10:49:51.56#ibcon#read 6, iclass 31, count 0 2006.201.10:49:51.56#ibcon#end of sib2, iclass 31, count 0 2006.201.10:49:51.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:49:51.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:49:51.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:49:51.56#ibcon#*before write, iclass 31, count 0 2006.201.10:49:51.56#ibcon#enter sib2, iclass 31, count 0 2006.201.10:49:51.56#ibcon#flushed, iclass 31, count 0 2006.201.10:49:51.56#ibcon#about to write, iclass 31, count 0 2006.201.10:49:51.56#ibcon#wrote, iclass 31, count 0 2006.201.10:49:51.56#ibcon#about to read 3, iclass 31, count 0 2006.201.10:49:51.61#ibcon#read 3, iclass 31, count 0 2006.201.10:49:51.61#ibcon#about to read 4, iclass 31, count 0 2006.201.10:49:51.61#ibcon#read 4, iclass 31, count 0 2006.201.10:49:51.61#ibcon#about to read 5, iclass 31, count 0 2006.201.10:49:51.61#ibcon#read 5, iclass 31, count 0 2006.201.10:49:51.61#ibcon#about to read 6, iclass 31, count 0 2006.201.10:49:51.61#ibcon#read 6, iclass 31, count 0 2006.201.10:49:51.61#ibcon#end of sib2, iclass 31, count 0 2006.201.10:49:51.61#ibcon#*after write, iclass 31, count 0 2006.201.10:49:51.61#ibcon#*before return 0, iclass 31, count 0 2006.201.10:49:51.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:51.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:51.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:49:51.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:49:51.61$vck44/va=3,8 2006.201.10:49:51.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.10:49:51.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.10:49:51.61#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:51.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:51.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:51.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:51.66#ibcon#enter wrdev, iclass 33, count 2 2006.201.10:49:51.66#ibcon#first serial, iclass 33, count 2 2006.201.10:49:51.66#ibcon#enter sib2, iclass 33, count 2 2006.201.10:49:51.66#ibcon#flushed, iclass 33, count 2 2006.201.10:49:51.66#ibcon#about to write, iclass 33, count 2 2006.201.10:49:51.66#ibcon#wrote, iclass 33, count 2 2006.201.10:49:51.66#ibcon#about to read 3, iclass 33, count 2 2006.201.10:49:51.68#ibcon#read 3, iclass 33, count 2 2006.201.10:49:51.68#ibcon#about to read 4, iclass 33, count 2 2006.201.10:49:51.68#ibcon#read 4, iclass 33, count 2 2006.201.10:49:51.68#ibcon#about to read 5, iclass 33, count 2 2006.201.10:49:51.68#ibcon#read 5, iclass 33, count 2 2006.201.10:49:51.68#ibcon#about to read 6, iclass 33, count 2 2006.201.10:49:51.68#ibcon#read 6, iclass 33, count 2 2006.201.10:49:51.68#ibcon#end of sib2, iclass 33, count 2 2006.201.10:49:51.68#ibcon#*mode == 0, iclass 33, count 2 2006.201.10:49:51.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.10:49:51.68#ibcon#[25=AT03-08\r\n] 2006.201.10:49:51.68#ibcon#*before write, iclass 33, count 2 2006.201.10:49:51.68#ibcon#enter sib2, iclass 33, count 2 2006.201.10:49:51.68#ibcon#flushed, iclass 33, count 2 2006.201.10:49:51.68#ibcon#about to write, iclass 33, count 2 2006.201.10:49:51.68#ibcon#wrote, iclass 33, count 2 2006.201.10:49:51.68#ibcon#about to read 3, iclass 33, count 2 2006.201.10:49:51.71#ibcon#read 3, iclass 33, count 2 2006.201.10:49:51.71#ibcon#about to read 4, iclass 33, count 2 2006.201.10:49:51.71#ibcon#read 4, iclass 33, count 2 2006.201.10:49:51.71#ibcon#about to read 5, iclass 33, count 2 2006.201.10:49:51.71#ibcon#read 5, iclass 33, count 2 2006.201.10:49:51.71#ibcon#about to read 6, iclass 33, count 2 2006.201.10:49:51.71#ibcon#read 6, iclass 33, count 2 2006.201.10:49:51.71#ibcon#end of sib2, iclass 33, count 2 2006.201.10:49:51.71#ibcon#*after write, iclass 33, count 2 2006.201.10:49:51.71#ibcon#*before return 0, iclass 33, count 2 2006.201.10:49:51.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:51.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:51.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.10:49:51.71#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:51.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:51.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:51.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:51.83#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:49:51.83#ibcon#first serial, iclass 33, count 0 2006.201.10:49:51.83#ibcon#enter sib2, iclass 33, count 0 2006.201.10:49:51.83#ibcon#flushed, iclass 33, count 0 2006.201.10:49:51.83#ibcon#about to write, iclass 33, count 0 2006.201.10:49:51.83#ibcon#wrote, iclass 33, count 0 2006.201.10:49:51.83#ibcon#about to read 3, iclass 33, count 0 2006.201.10:49:51.85#ibcon#read 3, iclass 33, count 0 2006.201.10:49:51.85#ibcon#about to read 4, iclass 33, count 0 2006.201.10:49:51.85#ibcon#read 4, iclass 33, count 0 2006.201.10:49:51.85#ibcon#about to read 5, iclass 33, count 0 2006.201.10:49:51.85#ibcon#read 5, iclass 33, count 0 2006.201.10:49:51.85#ibcon#about to read 6, iclass 33, count 0 2006.201.10:49:51.85#ibcon#read 6, iclass 33, count 0 2006.201.10:49:51.85#ibcon#end of sib2, iclass 33, count 0 2006.201.10:49:51.85#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:49:51.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:49:51.85#ibcon#[25=USB\r\n] 2006.201.10:49:51.85#ibcon#*before write, iclass 33, count 0 2006.201.10:49:51.85#ibcon#enter sib2, iclass 33, count 0 2006.201.10:49:51.85#ibcon#flushed, iclass 33, count 0 2006.201.10:49:51.85#ibcon#about to write, iclass 33, count 0 2006.201.10:49:51.85#ibcon#wrote, iclass 33, count 0 2006.201.10:49:51.85#ibcon#about to read 3, iclass 33, count 0 2006.201.10:49:51.88#ibcon#read 3, iclass 33, count 0 2006.201.10:49:51.88#ibcon#about to read 4, iclass 33, count 0 2006.201.10:49:51.88#ibcon#read 4, iclass 33, count 0 2006.201.10:49:51.88#ibcon#about to read 5, iclass 33, count 0 2006.201.10:49:51.88#ibcon#read 5, iclass 33, count 0 2006.201.10:49:51.88#ibcon#about to read 6, iclass 33, count 0 2006.201.10:49:51.88#ibcon#read 6, iclass 33, count 0 2006.201.10:49:51.88#ibcon#end of sib2, iclass 33, count 0 2006.201.10:49:51.88#ibcon#*after write, iclass 33, count 0 2006.201.10:49:51.88#ibcon#*before return 0, iclass 33, count 0 2006.201.10:49:51.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:51.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:51.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:49:51.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:49:51.88$vck44/valo=4,624.99 2006.201.10:49:51.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.10:49:51.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.10:49:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:51.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:51.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:51.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:51.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:49:51.88#ibcon#first serial, iclass 35, count 0 2006.201.10:49:51.88#ibcon#enter sib2, iclass 35, count 0 2006.201.10:49:51.88#ibcon#flushed, iclass 35, count 0 2006.201.10:49:51.88#ibcon#about to write, iclass 35, count 0 2006.201.10:49:51.88#ibcon#wrote, iclass 35, count 0 2006.201.10:49:51.88#ibcon#about to read 3, iclass 35, count 0 2006.201.10:49:51.90#ibcon#read 3, iclass 35, count 0 2006.201.10:49:51.90#ibcon#about to read 4, iclass 35, count 0 2006.201.10:49:51.90#ibcon#read 4, iclass 35, count 0 2006.201.10:49:51.90#ibcon#about to read 5, iclass 35, count 0 2006.201.10:49:51.90#ibcon#read 5, iclass 35, count 0 2006.201.10:49:51.90#ibcon#about to read 6, iclass 35, count 0 2006.201.10:49:51.90#ibcon#read 6, iclass 35, count 0 2006.201.10:49:51.90#ibcon#end of sib2, iclass 35, count 0 2006.201.10:49:51.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:49:51.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:49:51.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:49:51.90#ibcon#*before write, iclass 35, count 0 2006.201.10:49:51.90#ibcon#enter sib2, iclass 35, count 0 2006.201.10:49:51.90#ibcon#flushed, iclass 35, count 0 2006.201.10:49:51.90#ibcon#about to write, iclass 35, count 0 2006.201.10:49:51.90#ibcon#wrote, iclass 35, count 0 2006.201.10:49:51.90#ibcon#about to read 3, iclass 35, count 0 2006.201.10:49:51.95#ibcon#read 3, iclass 35, count 0 2006.201.10:49:51.95#ibcon#about to read 4, iclass 35, count 0 2006.201.10:49:51.95#ibcon#read 4, iclass 35, count 0 2006.201.10:49:51.95#ibcon#about to read 5, iclass 35, count 0 2006.201.10:49:51.95#ibcon#read 5, iclass 35, count 0 2006.201.10:49:51.95#ibcon#about to read 6, iclass 35, count 0 2006.201.10:49:51.95#ibcon#read 6, iclass 35, count 0 2006.201.10:49:51.95#ibcon#end of sib2, iclass 35, count 0 2006.201.10:49:51.95#ibcon#*after write, iclass 35, count 0 2006.201.10:49:51.95#ibcon#*before return 0, iclass 35, count 0 2006.201.10:49:51.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:51.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:51.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:49:51.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:49:51.95$vck44/va=4,7 2006.201.10:49:51.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.10:49:51.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.10:49:51.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:51.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:52.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:52.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:52.00#ibcon#enter wrdev, iclass 37, count 2 2006.201.10:49:52.00#ibcon#first serial, iclass 37, count 2 2006.201.10:49:52.00#ibcon#enter sib2, iclass 37, count 2 2006.201.10:49:52.00#ibcon#flushed, iclass 37, count 2 2006.201.10:49:52.00#ibcon#about to write, iclass 37, count 2 2006.201.10:49:52.00#ibcon#wrote, iclass 37, count 2 2006.201.10:49:52.00#ibcon#about to read 3, iclass 37, count 2 2006.201.10:49:52.02#ibcon#read 3, iclass 37, count 2 2006.201.10:49:52.02#ibcon#about to read 4, iclass 37, count 2 2006.201.10:49:52.02#ibcon#read 4, iclass 37, count 2 2006.201.10:49:52.02#ibcon#about to read 5, iclass 37, count 2 2006.201.10:49:52.02#ibcon#read 5, iclass 37, count 2 2006.201.10:49:52.02#ibcon#about to read 6, iclass 37, count 2 2006.201.10:49:52.02#ibcon#read 6, iclass 37, count 2 2006.201.10:49:52.02#ibcon#end of sib2, iclass 37, count 2 2006.201.10:49:52.02#ibcon#*mode == 0, iclass 37, count 2 2006.201.10:49:52.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.10:49:52.02#ibcon#[25=AT04-07\r\n] 2006.201.10:49:52.02#ibcon#*before write, iclass 37, count 2 2006.201.10:49:52.02#ibcon#enter sib2, iclass 37, count 2 2006.201.10:49:52.02#ibcon#flushed, iclass 37, count 2 2006.201.10:49:52.02#ibcon#about to write, iclass 37, count 2 2006.201.10:49:52.02#ibcon#wrote, iclass 37, count 2 2006.201.10:49:52.02#ibcon#about to read 3, iclass 37, count 2 2006.201.10:49:52.05#ibcon#read 3, iclass 37, count 2 2006.201.10:49:52.05#ibcon#about to read 4, iclass 37, count 2 2006.201.10:49:52.05#ibcon#read 4, iclass 37, count 2 2006.201.10:49:52.05#ibcon#about to read 5, iclass 37, count 2 2006.201.10:49:52.05#ibcon#read 5, iclass 37, count 2 2006.201.10:49:52.05#ibcon#about to read 6, iclass 37, count 2 2006.201.10:49:52.05#ibcon#read 6, iclass 37, count 2 2006.201.10:49:52.05#ibcon#end of sib2, iclass 37, count 2 2006.201.10:49:52.05#ibcon#*after write, iclass 37, count 2 2006.201.10:49:52.05#ibcon#*before return 0, iclass 37, count 2 2006.201.10:49:52.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:52.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:52.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.10:49:52.05#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:52.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:52.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:52.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:52.17#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:49:52.17#ibcon#first serial, iclass 37, count 0 2006.201.10:49:52.17#ibcon#enter sib2, iclass 37, count 0 2006.201.10:49:52.17#ibcon#flushed, iclass 37, count 0 2006.201.10:49:52.17#ibcon#about to write, iclass 37, count 0 2006.201.10:49:52.17#ibcon#wrote, iclass 37, count 0 2006.201.10:49:52.17#ibcon#about to read 3, iclass 37, count 0 2006.201.10:49:52.19#ibcon#read 3, iclass 37, count 0 2006.201.10:49:52.19#ibcon#about to read 4, iclass 37, count 0 2006.201.10:49:52.19#ibcon#read 4, iclass 37, count 0 2006.201.10:49:52.19#ibcon#about to read 5, iclass 37, count 0 2006.201.10:49:52.19#ibcon#read 5, iclass 37, count 0 2006.201.10:49:52.19#ibcon#about to read 6, iclass 37, count 0 2006.201.10:49:52.19#ibcon#read 6, iclass 37, count 0 2006.201.10:49:52.19#ibcon#end of sib2, iclass 37, count 0 2006.201.10:49:52.19#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:49:52.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:49:52.19#ibcon#[25=USB\r\n] 2006.201.10:49:52.19#ibcon#*before write, iclass 37, count 0 2006.201.10:49:52.19#ibcon#enter sib2, iclass 37, count 0 2006.201.10:49:52.19#ibcon#flushed, iclass 37, count 0 2006.201.10:49:52.19#ibcon#about to write, iclass 37, count 0 2006.201.10:49:52.19#ibcon#wrote, iclass 37, count 0 2006.201.10:49:52.19#ibcon#about to read 3, iclass 37, count 0 2006.201.10:49:52.22#ibcon#read 3, iclass 37, count 0 2006.201.10:49:52.22#ibcon#about to read 4, iclass 37, count 0 2006.201.10:49:52.22#ibcon#read 4, iclass 37, count 0 2006.201.10:49:52.22#ibcon#about to read 5, iclass 37, count 0 2006.201.10:49:52.22#ibcon#read 5, iclass 37, count 0 2006.201.10:49:52.22#ibcon#about to read 6, iclass 37, count 0 2006.201.10:49:52.22#ibcon#read 6, iclass 37, count 0 2006.201.10:49:52.22#ibcon#end of sib2, iclass 37, count 0 2006.201.10:49:52.22#ibcon#*after write, iclass 37, count 0 2006.201.10:49:52.22#ibcon#*before return 0, iclass 37, count 0 2006.201.10:49:52.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:52.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:52.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:49:52.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:49:52.22$vck44/valo=5,734.99 2006.201.10:49:52.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.10:49:52.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.10:49:52.22#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:52.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:52.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:52.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:52.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:49:52.22#ibcon#first serial, iclass 39, count 0 2006.201.10:49:52.22#ibcon#enter sib2, iclass 39, count 0 2006.201.10:49:52.22#ibcon#flushed, iclass 39, count 0 2006.201.10:49:52.22#ibcon#about to write, iclass 39, count 0 2006.201.10:49:52.22#ibcon#wrote, iclass 39, count 0 2006.201.10:49:52.22#ibcon#about to read 3, iclass 39, count 0 2006.201.10:49:52.24#ibcon#read 3, iclass 39, count 0 2006.201.10:49:52.24#ibcon#about to read 4, iclass 39, count 0 2006.201.10:49:52.24#ibcon#read 4, iclass 39, count 0 2006.201.10:49:52.24#ibcon#about to read 5, iclass 39, count 0 2006.201.10:49:52.24#ibcon#read 5, iclass 39, count 0 2006.201.10:49:52.24#ibcon#about to read 6, iclass 39, count 0 2006.201.10:49:52.24#ibcon#read 6, iclass 39, count 0 2006.201.10:49:52.24#ibcon#end of sib2, iclass 39, count 0 2006.201.10:49:52.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:49:52.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:49:52.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:49:52.24#ibcon#*before write, iclass 39, count 0 2006.201.10:49:52.24#ibcon#enter sib2, iclass 39, count 0 2006.201.10:49:52.24#ibcon#flushed, iclass 39, count 0 2006.201.10:49:52.24#ibcon#about to write, iclass 39, count 0 2006.201.10:49:52.24#ibcon#wrote, iclass 39, count 0 2006.201.10:49:52.24#ibcon#about to read 3, iclass 39, count 0 2006.201.10:49:52.28#ibcon#read 3, iclass 39, count 0 2006.201.10:49:52.28#ibcon#about to read 4, iclass 39, count 0 2006.201.10:49:52.28#ibcon#read 4, iclass 39, count 0 2006.201.10:49:52.28#ibcon#about to read 5, iclass 39, count 0 2006.201.10:49:52.28#ibcon#read 5, iclass 39, count 0 2006.201.10:49:52.28#ibcon#about to read 6, iclass 39, count 0 2006.201.10:49:52.28#ibcon#read 6, iclass 39, count 0 2006.201.10:49:52.28#ibcon#end of sib2, iclass 39, count 0 2006.201.10:49:52.28#ibcon#*after write, iclass 39, count 0 2006.201.10:49:52.28#ibcon#*before return 0, iclass 39, count 0 2006.201.10:49:52.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:52.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:52.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:49:52.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:49:52.28$vck44/va=5,4 2006.201.10:49:52.28#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.10:49:52.28#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.10:49:52.28#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:52.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:52.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:52.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:52.34#ibcon#enter wrdev, iclass 2, count 2 2006.201.10:49:52.34#ibcon#first serial, iclass 2, count 2 2006.201.10:49:52.34#ibcon#enter sib2, iclass 2, count 2 2006.201.10:49:52.34#ibcon#flushed, iclass 2, count 2 2006.201.10:49:52.34#ibcon#about to write, iclass 2, count 2 2006.201.10:49:52.34#ibcon#wrote, iclass 2, count 2 2006.201.10:49:52.34#ibcon#about to read 3, iclass 2, count 2 2006.201.10:49:52.36#ibcon#read 3, iclass 2, count 2 2006.201.10:49:52.36#ibcon#about to read 4, iclass 2, count 2 2006.201.10:49:52.36#ibcon#read 4, iclass 2, count 2 2006.201.10:49:52.36#ibcon#about to read 5, iclass 2, count 2 2006.201.10:49:52.36#ibcon#read 5, iclass 2, count 2 2006.201.10:49:52.36#ibcon#about to read 6, iclass 2, count 2 2006.201.10:49:52.36#ibcon#read 6, iclass 2, count 2 2006.201.10:49:52.36#ibcon#end of sib2, iclass 2, count 2 2006.201.10:49:52.36#ibcon#*mode == 0, iclass 2, count 2 2006.201.10:49:52.36#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.10:49:52.36#ibcon#[25=AT05-04\r\n] 2006.201.10:49:52.36#ibcon#*before write, iclass 2, count 2 2006.201.10:49:52.36#ibcon#enter sib2, iclass 2, count 2 2006.201.10:49:52.36#ibcon#flushed, iclass 2, count 2 2006.201.10:49:52.36#ibcon#about to write, iclass 2, count 2 2006.201.10:49:52.36#ibcon#wrote, iclass 2, count 2 2006.201.10:49:52.36#ibcon#about to read 3, iclass 2, count 2 2006.201.10:49:52.39#ibcon#read 3, iclass 2, count 2 2006.201.10:49:52.39#ibcon#about to read 4, iclass 2, count 2 2006.201.10:49:52.39#ibcon#read 4, iclass 2, count 2 2006.201.10:49:52.39#ibcon#about to read 5, iclass 2, count 2 2006.201.10:49:52.39#ibcon#read 5, iclass 2, count 2 2006.201.10:49:52.39#ibcon#about to read 6, iclass 2, count 2 2006.201.10:49:52.39#ibcon#read 6, iclass 2, count 2 2006.201.10:49:52.39#ibcon#end of sib2, iclass 2, count 2 2006.201.10:49:52.39#ibcon#*after write, iclass 2, count 2 2006.201.10:49:52.39#ibcon#*before return 0, iclass 2, count 2 2006.201.10:49:52.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:52.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:52.39#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.10:49:52.39#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:52.39#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:52.51#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:52.51#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:52.51#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:49:52.51#ibcon#first serial, iclass 2, count 0 2006.201.10:49:52.51#ibcon#enter sib2, iclass 2, count 0 2006.201.10:49:52.51#ibcon#flushed, iclass 2, count 0 2006.201.10:49:52.51#ibcon#about to write, iclass 2, count 0 2006.201.10:49:52.51#ibcon#wrote, iclass 2, count 0 2006.201.10:49:52.51#ibcon#about to read 3, iclass 2, count 0 2006.201.10:49:52.53#ibcon#read 3, iclass 2, count 0 2006.201.10:49:52.53#ibcon#about to read 4, iclass 2, count 0 2006.201.10:49:52.53#ibcon#read 4, iclass 2, count 0 2006.201.10:49:52.53#ibcon#about to read 5, iclass 2, count 0 2006.201.10:49:52.53#ibcon#read 5, iclass 2, count 0 2006.201.10:49:52.53#ibcon#about to read 6, iclass 2, count 0 2006.201.10:49:52.53#ibcon#read 6, iclass 2, count 0 2006.201.10:49:52.53#ibcon#end of sib2, iclass 2, count 0 2006.201.10:49:52.53#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:49:52.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:49:52.53#ibcon#[25=USB\r\n] 2006.201.10:49:52.53#ibcon#*before write, iclass 2, count 0 2006.201.10:49:52.53#ibcon#enter sib2, iclass 2, count 0 2006.201.10:49:52.53#ibcon#flushed, iclass 2, count 0 2006.201.10:49:52.53#ibcon#about to write, iclass 2, count 0 2006.201.10:49:52.53#ibcon#wrote, iclass 2, count 0 2006.201.10:49:52.53#ibcon#about to read 3, iclass 2, count 0 2006.201.10:49:52.56#ibcon#read 3, iclass 2, count 0 2006.201.10:49:52.56#ibcon#about to read 4, iclass 2, count 0 2006.201.10:49:52.56#ibcon#read 4, iclass 2, count 0 2006.201.10:49:52.56#ibcon#about to read 5, iclass 2, count 0 2006.201.10:49:52.56#ibcon#read 5, iclass 2, count 0 2006.201.10:49:52.56#ibcon#about to read 6, iclass 2, count 0 2006.201.10:49:52.56#ibcon#read 6, iclass 2, count 0 2006.201.10:49:52.56#ibcon#end of sib2, iclass 2, count 0 2006.201.10:49:52.56#ibcon#*after write, iclass 2, count 0 2006.201.10:49:52.56#ibcon#*before return 0, iclass 2, count 0 2006.201.10:49:52.56#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:52.56#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:52.56#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:49:52.56#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:49:52.56$vck44/valo=6,814.99 2006.201.10:49:52.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.10:49:52.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.10:49:52.56#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:52.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:52.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:52.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:52.56#ibcon#enter wrdev, iclass 5, count 0 2006.201.10:49:52.56#ibcon#first serial, iclass 5, count 0 2006.201.10:49:52.56#ibcon#enter sib2, iclass 5, count 0 2006.201.10:49:52.56#ibcon#flushed, iclass 5, count 0 2006.201.10:49:52.56#ibcon#about to write, iclass 5, count 0 2006.201.10:49:52.56#ibcon#wrote, iclass 5, count 0 2006.201.10:49:52.56#ibcon#about to read 3, iclass 5, count 0 2006.201.10:49:52.58#ibcon#read 3, iclass 5, count 0 2006.201.10:49:52.58#ibcon#about to read 4, iclass 5, count 0 2006.201.10:49:52.58#ibcon#read 4, iclass 5, count 0 2006.201.10:49:52.58#ibcon#about to read 5, iclass 5, count 0 2006.201.10:49:52.58#ibcon#read 5, iclass 5, count 0 2006.201.10:49:52.58#ibcon#about to read 6, iclass 5, count 0 2006.201.10:49:52.58#ibcon#read 6, iclass 5, count 0 2006.201.10:49:52.58#ibcon#end of sib2, iclass 5, count 0 2006.201.10:49:52.58#ibcon#*mode == 0, iclass 5, count 0 2006.201.10:49:52.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.10:49:52.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:49:52.58#ibcon#*before write, iclass 5, count 0 2006.201.10:49:52.58#ibcon#enter sib2, iclass 5, count 0 2006.201.10:49:52.58#ibcon#flushed, iclass 5, count 0 2006.201.10:49:52.58#ibcon#about to write, iclass 5, count 0 2006.201.10:49:52.58#ibcon#wrote, iclass 5, count 0 2006.201.10:49:52.58#ibcon#about to read 3, iclass 5, count 0 2006.201.10:49:52.63#ibcon#read 3, iclass 5, count 0 2006.201.10:49:52.63#ibcon#about to read 4, iclass 5, count 0 2006.201.10:49:52.63#ibcon#read 4, iclass 5, count 0 2006.201.10:49:52.63#ibcon#about to read 5, iclass 5, count 0 2006.201.10:49:52.63#ibcon#read 5, iclass 5, count 0 2006.201.10:49:52.63#ibcon#about to read 6, iclass 5, count 0 2006.201.10:49:52.63#ibcon#read 6, iclass 5, count 0 2006.201.10:49:52.63#ibcon#end of sib2, iclass 5, count 0 2006.201.10:49:52.63#ibcon#*after write, iclass 5, count 0 2006.201.10:49:52.63#ibcon#*before return 0, iclass 5, count 0 2006.201.10:49:52.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:52.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:52.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.10:49:52.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.10:49:52.63$vck44/va=6,5 2006.201.10:49:52.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.10:49:52.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.10:49:52.63#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:52.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:52.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:52.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:52.68#ibcon#enter wrdev, iclass 7, count 2 2006.201.10:49:52.68#ibcon#first serial, iclass 7, count 2 2006.201.10:49:52.68#ibcon#enter sib2, iclass 7, count 2 2006.201.10:49:52.68#ibcon#flushed, iclass 7, count 2 2006.201.10:49:52.68#ibcon#about to write, iclass 7, count 2 2006.201.10:49:52.68#ibcon#wrote, iclass 7, count 2 2006.201.10:49:52.68#ibcon#about to read 3, iclass 7, count 2 2006.201.10:49:52.70#ibcon#read 3, iclass 7, count 2 2006.201.10:49:52.70#ibcon#about to read 4, iclass 7, count 2 2006.201.10:49:52.70#ibcon#read 4, iclass 7, count 2 2006.201.10:49:52.70#ibcon#about to read 5, iclass 7, count 2 2006.201.10:49:52.70#ibcon#read 5, iclass 7, count 2 2006.201.10:49:52.70#ibcon#about to read 6, iclass 7, count 2 2006.201.10:49:52.70#ibcon#read 6, iclass 7, count 2 2006.201.10:49:52.70#ibcon#end of sib2, iclass 7, count 2 2006.201.10:49:52.70#ibcon#*mode == 0, iclass 7, count 2 2006.201.10:49:52.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.10:49:52.70#ibcon#[25=AT06-05\r\n] 2006.201.10:49:52.70#ibcon#*before write, iclass 7, count 2 2006.201.10:49:52.70#ibcon#enter sib2, iclass 7, count 2 2006.201.10:49:52.70#ibcon#flushed, iclass 7, count 2 2006.201.10:49:52.70#ibcon#about to write, iclass 7, count 2 2006.201.10:49:52.70#ibcon#wrote, iclass 7, count 2 2006.201.10:49:52.70#ibcon#about to read 3, iclass 7, count 2 2006.201.10:49:52.73#ibcon#read 3, iclass 7, count 2 2006.201.10:49:52.73#ibcon#about to read 4, iclass 7, count 2 2006.201.10:49:52.73#ibcon#read 4, iclass 7, count 2 2006.201.10:49:52.73#ibcon#about to read 5, iclass 7, count 2 2006.201.10:49:52.73#ibcon#read 5, iclass 7, count 2 2006.201.10:49:52.73#ibcon#about to read 6, iclass 7, count 2 2006.201.10:49:52.73#ibcon#read 6, iclass 7, count 2 2006.201.10:49:52.73#ibcon#end of sib2, iclass 7, count 2 2006.201.10:49:52.73#ibcon#*after write, iclass 7, count 2 2006.201.10:49:52.73#ibcon#*before return 0, iclass 7, count 2 2006.201.10:49:52.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:52.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:52.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.10:49:52.73#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:52.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:52.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:52.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:52.85#ibcon#enter wrdev, iclass 7, count 0 2006.201.10:49:52.85#ibcon#first serial, iclass 7, count 0 2006.201.10:49:52.85#ibcon#enter sib2, iclass 7, count 0 2006.201.10:49:52.85#ibcon#flushed, iclass 7, count 0 2006.201.10:49:52.85#ibcon#about to write, iclass 7, count 0 2006.201.10:49:52.85#ibcon#wrote, iclass 7, count 0 2006.201.10:49:52.85#ibcon#about to read 3, iclass 7, count 0 2006.201.10:49:52.87#ibcon#read 3, iclass 7, count 0 2006.201.10:49:52.87#ibcon#about to read 4, iclass 7, count 0 2006.201.10:49:52.87#ibcon#read 4, iclass 7, count 0 2006.201.10:49:52.87#ibcon#about to read 5, iclass 7, count 0 2006.201.10:49:52.87#ibcon#read 5, iclass 7, count 0 2006.201.10:49:52.87#ibcon#about to read 6, iclass 7, count 0 2006.201.10:49:52.87#ibcon#read 6, iclass 7, count 0 2006.201.10:49:52.87#ibcon#end of sib2, iclass 7, count 0 2006.201.10:49:52.87#ibcon#*mode == 0, iclass 7, count 0 2006.201.10:49:52.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.10:49:52.87#ibcon#[25=USB\r\n] 2006.201.10:49:52.87#ibcon#*before write, iclass 7, count 0 2006.201.10:49:52.87#ibcon#enter sib2, iclass 7, count 0 2006.201.10:49:52.87#ibcon#flushed, iclass 7, count 0 2006.201.10:49:52.87#ibcon#about to write, iclass 7, count 0 2006.201.10:49:52.87#ibcon#wrote, iclass 7, count 0 2006.201.10:49:52.87#ibcon#about to read 3, iclass 7, count 0 2006.201.10:49:52.90#ibcon#read 3, iclass 7, count 0 2006.201.10:49:52.90#ibcon#about to read 4, iclass 7, count 0 2006.201.10:49:52.90#ibcon#read 4, iclass 7, count 0 2006.201.10:49:52.90#ibcon#about to read 5, iclass 7, count 0 2006.201.10:49:52.90#ibcon#read 5, iclass 7, count 0 2006.201.10:49:52.90#ibcon#about to read 6, iclass 7, count 0 2006.201.10:49:52.90#ibcon#read 6, iclass 7, count 0 2006.201.10:49:52.90#ibcon#end of sib2, iclass 7, count 0 2006.201.10:49:52.90#ibcon#*after write, iclass 7, count 0 2006.201.10:49:52.90#ibcon#*before return 0, iclass 7, count 0 2006.201.10:49:52.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:52.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:52.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.10:49:52.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.10:49:52.90$vck44/valo=7,864.99 2006.201.10:49:52.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.10:49:52.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.10:49:52.90#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:52.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:52.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:52.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:52.90#ibcon#enter wrdev, iclass 11, count 0 2006.201.10:49:52.90#ibcon#first serial, iclass 11, count 0 2006.201.10:49:52.90#ibcon#enter sib2, iclass 11, count 0 2006.201.10:49:52.90#ibcon#flushed, iclass 11, count 0 2006.201.10:49:52.90#ibcon#about to write, iclass 11, count 0 2006.201.10:49:52.90#ibcon#wrote, iclass 11, count 0 2006.201.10:49:52.90#ibcon#about to read 3, iclass 11, count 0 2006.201.10:49:52.92#ibcon#read 3, iclass 11, count 0 2006.201.10:49:52.92#ibcon#about to read 4, iclass 11, count 0 2006.201.10:49:52.92#ibcon#read 4, iclass 11, count 0 2006.201.10:49:52.92#ibcon#about to read 5, iclass 11, count 0 2006.201.10:49:52.92#ibcon#read 5, iclass 11, count 0 2006.201.10:49:52.92#ibcon#about to read 6, iclass 11, count 0 2006.201.10:49:52.92#ibcon#read 6, iclass 11, count 0 2006.201.10:49:52.92#ibcon#end of sib2, iclass 11, count 0 2006.201.10:49:52.92#ibcon#*mode == 0, iclass 11, count 0 2006.201.10:49:52.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.10:49:52.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:49:52.92#ibcon#*before write, iclass 11, count 0 2006.201.10:49:52.92#ibcon#enter sib2, iclass 11, count 0 2006.201.10:49:52.92#ibcon#flushed, iclass 11, count 0 2006.201.10:49:52.92#ibcon#about to write, iclass 11, count 0 2006.201.10:49:52.92#ibcon#wrote, iclass 11, count 0 2006.201.10:49:52.92#ibcon#about to read 3, iclass 11, count 0 2006.201.10:49:52.96#ibcon#read 3, iclass 11, count 0 2006.201.10:49:52.96#ibcon#about to read 4, iclass 11, count 0 2006.201.10:49:52.96#ibcon#read 4, iclass 11, count 0 2006.201.10:49:52.96#ibcon#about to read 5, iclass 11, count 0 2006.201.10:49:52.96#ibcon#read 5, iclass 11, count 0 2006.201.10:49:52.96#ibcon#about to read 6, iclass 11, count 0 2006.201.10:49:52.96#ibcon#read 6, iclass 11, count 0 2006.201.10:49:52.96#ibcon#end of sib2, iclass 11, count 0 2006.201.10:49:52.96#ibcon#*after write, iclass 11, count 0 2006.201.10:49:52.96#ibcon#*before return 0, iclass 11, count 0 2006.201.10:49:52.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:52.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:52.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.10:49:52.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.10:49:52.96$vck44/va=7,5 2006.201.10:49:52.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.10:49:52.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.10:49:52.96#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:52.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:53.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:53.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:53.02#ibcon#enter wrdev, iclass 13, count 2 2006.201.10:49:53.02#ibcon#first serial, iclass 13, count 2 2006.201.10:49:53.02#ibcon#enter sib2, iclass 13, count 2 2006.201.10:49:53.02#ibcon#flushed, iclass 13, count 2 2006.201.10:49:53.02#ibcon#about to write, iclass 13, count 2 2006.201.10:49:53.02#ibcon#wrote, iclass 13, count 2 2006.201.10:49:53.02#ibcon#about to read 3, iclass 13, count 2 2006.201.10:49:53.04#ibcon#read 3, iclass 13, count 2 2006.201.10:49:53.04#ibcon#about to read 4, iclass 13, count 2 2006.201.10:49:53.04#ibcon#read 4, iclass 13, count 2 2006.201.10:49:53.04#ibcon#about to read 5, iclass 13, count 2 2006.201.10:49:53.04#ibcon#read 5, iclass 13, count 2 2006.201.10:49:53.04#ibcon#about to read 6, iclass 13, count 2 2006.201.10:49:53.04#ibcon#read 6, iclass 13, count 2 2006.201.10:49:53.04#ibcon#end of sib2, iclass 13, count 2 2006.201.10:49:53.04#ibcon#*mode == 0, iclass 13, count 2 2006.201.10:49:53.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.10:49:53.04#ibcon#[25=AT07-05\r\n] 2006.201.10:49:53.04#ibcon#*before write, iclass 13, count 2 2006.201.10:49:53.04#ibcon#enter sib2, iclass 13, count 2 2006.201.10:49:53.04#ibcon#flushed, iclass 13, count 2 2006.201.10:49:53.04#ibcon#about to write, iclass 13, count 2 2006.201.10:49:53.04#ibcon#wrote, iclass 13, count 2 2006.201.10:49:53.04#ibcon#about to read 3, iclass 13, count 2 2006.201.10:49:53.07#ibcon#read 3, iclass 13, count 2 2006.201.10:49:53.07#ibcon#about to read 4, iclass 13, count 2 2006.201.10:49:53.07#ibcon#read 4, iclass 13, count 2 2006.201.10:49:53.07#ibcon#about to read 5, iclass 13, count 2 2006.201.10:49:53.07#ibcon#read 5, iclass 13, count 2 2006.201.10:49:53.07#ibcon#about to read 6, iclass 13, count 2 2006.201.10:49:53.07#ibcon#read 6, iclass 13, count 2 2006.201.10:49:53.07#ibcon#end of sib2, iclass 13, count 2 2006.201.10:49:53.07#ibcon#*after write, iclass 13, count 2 2006.201.10:49:53.07#ibcon#*before return 0, iclass 13, count 2 2006.201.10:49:53.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:53.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:53.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.10:49:53.07#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:53.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:53.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:53.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:53.19#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:49:53.19#ibcon#first serial, iclass 13, count 0 2006.201.10:49:53.19#ibcon#enter sib2, iclass 13, count 0 2006.201.10:49:53.19#ibcon#flushed, iclass 13, count 0 2006.201.10:49:53.19#ibcon#about to write, iclass 13, count 0 2006.201.10:49:53.19#ibcon#wrote, iclass 13, count 0 2006.201.10:49:53.19#ibcon#about to read 3, iclass 13, count 0 2006.201.10:49:53.21#ibcon#read 3, iclass 13, count 0 2006.201.10:49:53.21#ibcon#about to read 4, iclass 13, count 0 2006.201.10:49:53.21#ibcon#read 4, iclass 13, count 0 2006.201.10:49:53.21#ibcon#about to read 5, iclass 13, count 0 2006.201.10:49:53.21#ibcon#read 5, iclass 13, count 0 2006.201.10:49:53.21#ibcon#about to read 6, iclass 13, count 0 2006.201.10:49:53.21#ibcon#read 6, iclass 13, count 0 2006.201.10:49:53.21#ibcon#end of sib2, iclass 13, count 0 2006.201.10:49:53.21#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:49:53.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:49:53.21#ibcon#[25=USB\r\n] 2006.201.10:49:53.21#ibcon#*before write, iclass 13, count 0 2006.201.10:49:53.21#ibcon#enter sib2, iclass 13, count 0 2006.201.10:49:53.21#ibcon#flushed, iclass 13, count 0 2006.201.10:49:53.21#ibcon#about to write, iclass 13, count 0 2006.201.10:49:53.21#ibcon#wrote, iclass 13, count 0 2006.201.10:49:53.21#ibcon#about to read 3, iclass 13, count 0 2006.201.10:49:53.24#ibcon#read 3, iclass 13, count 0 2006.201.10:49:53.24#ibcon#about to read 4, iclass 13, count 0 2006.201.10:49:53.24#ibcon#read 4, iclass 13, count 0 2006.201.10:49:53.24#ibcon#about to read 5, iclass 13, count 0 2006.201.10:49:53.24#ibcon#read 5, iclass 13, count 0 2006.201.10:49:53.24#ibcon#about to read 6, iclass 13, count 0 2006.201.10:49:53.24#ibcon#read 6, iclass 13, count 0 2006.201.10:49:53.24#ibcon#end of sib2, iclass 13, count 0 2006.201.10:49:53.24#ibcon#*after write, iclass 13, count 0 2006.201.10:49:53.24#ibcon#*before return 0, iclass 13, count 0 2006.201.10:49:53.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:53.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:53.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:49:53.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:49:53.24$vck44/valo=8,884.99 2006.201.10:49:53.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.10:49:53.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.10:49:53.24#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:53.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:53.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:53.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:53.24#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:49:53.24#ibcon#first serial, iclass 15, count 0 2006.201.10:49:53.24#ibcon#enter sib2, iclass 15, count 0 2006.201.10:49:53.24#ibcon#flushed, iclass 15, count 0 2006.201.10:49:53.24#ibcon#about to write, iclass 15, count 0 2006.201.10:49:53.24#ibcon#wrote, iclass 15, count 0 2006.201.10:49:53.24#ibcon#about to read 3, iclass 15, count 0 2006.201.10:49:53.26#ibcon#read 3, iclass 15, count 0 2006.201.10:49:53.26#ibcon#about to read 4, iclass 15, count 0 2006.201.10:49:53.26#ibcon#read 4, iclass 15, count 0 2006.201.10:49:53.26#ibcon#about to read 5, iclass 15, count 0 2006.201.10:49:53.26#ibcon#read 5, iclass 15, count 0 2006.201.10:49:53.26#ibcon#about to read 6, iclass 15, count 0 2006.201.10:49:53.26#ibcon#read 6, iclass 15, count 0 2006.201.10:49:53.26#ibcon#end of sib2, iclass 15, count 0 2006.201.10:49:53.26#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:49:53.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:49:53.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:49:53.26#ibcon#*before write, iclass 15, count 0 2006.201.10:49:53.26#ibcon#enter sib2, iclass 15, count 0 2006.201.10:49:53.26#ibcon#flushed, iclass 15, count 0 2006.201.10:49:53.26#ibcon#about to write, iclass 15, count 0 2006.201.10:49:53.26#ibcon#wrote, iclass 15, count 0 2006.201.10:49:53.26#ibcon#about to read 3, iclass 15, count 0 2006.201.10:49:53.30#ibcon#read 3, iclass 15, count 0 2006.201.10:49:53.30#ibcon#about to read 4, iclass 15, count 0 2006.201.10:49:53.30#ibcon#read 4, iclass 15, count 0 2006.201.10:49:53.30#ibcon#about to read 5, iclass 15, count 0 2006.201.10:49:53.30#ibcon#read 5, iclass 15, count 0 2006.201.10:49:53.30#ibcon#about to read 6, iclass 15, count 0 2006.201.10:49:53.30#ibcon#read 6, iclass 15, count 0 2006.201.10:49:53.30#ibcon#end of sib2, iclass 15, count 0 2006.201.10:49:53.30#ibcon#*after write, iclass 15, count 0 2006.201.10:49:53.30#ibcon#*before return 0, iclass 15, count 0 2006.201.10:49:53.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:53.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:53.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:49:53.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:49:53.30$vck44/va=8,4 2006.201.10:49:53.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.10:49:53.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.10:49:53.30#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:53.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:49:53.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:49:53.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:49:53.36#ibcon#enter wrdev, iclass 17, count 2 2006.201.10:49:53.36#ibcon#first serial, iclass 17, count 2 2006.201.10:49:53.36#ibcon#enter sib2, iclass 17, count 2 2006.201.10:49:53.36#ibcon#flushed, iclass 17, count 2 2006.201.10:49:53.36#ibcon#about to write, iclass 17, count 2 2006.201.10:49:53.36#ibcon#wrote, iclass 17, count 2 2006.201.10:49:53.36#ibcon#about to read 3, iclass 17, count 2 2006.201.10:49:53.38#ibcon#read 3, iclass 17, count 2 2006.201.10:49:53.38#ibcon#about to read 4, iclass 17, count 2 2006.201.10:49:53.38#ibcon#read 4, iclass 17, count 2 2006.201.10:49:53.38#ibcon#about to read 5, iclass 17, count 2 2006.201.10:49:53.38#ibcon#read 5, iclass 17, count 2 2006.201.10:49:53.38#ibcon#about to read 6, iclass 17, count 2 2006.201.10:49:53.38#ibcon#read 6, iclass 17, count 2 2006.201.10:49:53.38#ibcon#end of sib2, iclass 17, count 2 2006.201.10:49:53.38#ibcon#*mode == 0, iclass 17, count 2 2006.201.10:49:53.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.10:49:53.38#ibcon#[25=AT08-04\r\n] 2006.201.10:49:53.38#ibcon#*before write, iclass 17, count 2 2006.201.10:49:53.38#ibcon#enter sib2, iclass 17, count 2 2006.201.10:49:53.38#ibcon#flushed, iclass 17, count 2 2006.201.10:49:53.38#ibcon#about to write, iclass 17, count 2 2006.201.10:49:53.38#ibcon#wrote, iclass 17, count 2 2006.201.10:49:53.38#ibcon#about to read 3, iclass 17, count 2 2006.201.10:49:53.41#ibcon#read 3, iclass 17, count 2 2006.201.10:49:53.41#ibcon#about to read 4, iclass 17, count 2 2006.201.10:49:53.41#ibcon#read 4, iclass 17, count 2 2006.201.10:49:53.41#ibcon#about to read 5, iclass 17, count 2 2006.201.10:49:53.41#ibcon#read 5, iclass 17, count 2 2006.201.10:49:53.41#ibcon#about to read 6, iclass 17, count 2 2006.201.10:49:53.41#ibcon#read 6, iclass 17, count 2 2006.201.10:49:53.41#ibcon#end of sib2, iclass 17, count 2 2006.201.10:49:53.41#ibcon#*after write, iclass 17, count 2 2006.201.10:49:53.41#ibcon#*before return 0, iclass 17, count 2 2006.201.10:49:53.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:49:53.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.10:49:53.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.10:49:53.41#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:53.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:49:53.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:49:53.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:49:53.53#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:49:53.53#ibcon#first serial, iclass 17, count 0 2006.201.10:49:53.53#ibcon#enter sib2, iclass 17, count 0 2006.201.10:49:53.53#ibcon#flushed, iclass 17, count 0 2006.201.10:49:53.53#ibcon#about to write, iclass 17, count 0 2006.201.10:49:53.53#ibcon#wrote, iclass 17, count 0 2006.201.10:49:53.53#ibcon#about to read 3, iclass 17, count 0 2006.201.10:49:53.55#ibcon#read 3, iclass 17, count 0 2006.201.10:49:53.55#ibcon#about to read 4, iclass 17, count 0 2006.201.10:49:53.55#ibcon#read 4, iclass 17, count 0 2006.201.10:49:53.55#ibcon#about to read 5, iclass 17, count 0 2006.201.10:49:53.55#ibcon#read 5, iclass 17, count 0 2006.201.10:49:53.55#ibcon#about to read 6, iclass 17, count 0 2006.201.10:49:53.55#ibcon#read 6, iclass 17, count 0 2006.201.10:49:53.55#ibcon#end of sib2, iclass 17, count 0 2006.201.10:49:53.55#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:49:53.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:49:53.55#ibcon#[25=USB\r\n] 2006.201.10:49:53.55#ibcon#*before write, iclass 17, count 0 2006.201.10:49:53.55#ibcon#enter sib2, iclass 17, count 0 2006.201.10:49:53.55#ibcon#flushed, iclass 17, count 0 2006.201.10:49:53.55#ibcon#about to write, iclass 17, count 0 2006.201.10:49:53.55#ibcon#wrote, iclass 17, count 0 2006.201.10:49:53.55#ibcon#about to read 3, iclass 17, count 0 2006.201.10:49:53.58#ibcon#read 3, iclass 17, count 0 2006.201.10:49:53.58#ibcon#about to read 4, iclass 17, count 0 2006.201.10:49:53.58#ibcon#read 4, iclass 17, count 0 2006.201.10:49:53.58#ibcon#about to read 5, iclass 17, count 0 2006.201.10:49:53.58#ibcon#read 5, iclass 17, count 0 2006.201.10:49:53.58#ibcon#about to read 6, iclass 17, count 0 2006.201.10:49:53.58#ibcon#read 6, iclass 17, count 0 2006.201.10:49:53.58#ibcon#end of sib2, iclass 17, count 0 2006.201.10:49:53.58#ibcon#*after write, iclass 17, count 0 2006.201.10:49:53.58#ibcon#*before return 0, iclass 17, count 0 2006.201.10:49:53.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:49:53.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.10:49:53.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:49:53.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:49:53.58$vck44/vblo=1,629.99 2006.201.10:49:53.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.10:49:53.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.10:49:53.58#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:53.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:53.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:53.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:53.58#ibcon#enter wrdev, iclass 19, count 0 2006.201.10:49:53.58#ibcon#first serial, iclass 19, count 0 2006.201.10:49:53.58#ibcon#enter sib2, iclass 19, count 0 2006.201.10:49:53.58#ibcon#flushed, iclass 19, count 0 2006.201.10:49:53.58#ibcon#about to write, iclass 19, count 0 2006.201.10:49:53.58#ibcon#wrote, iclass 19, count 0 2006.201.10:49:53.58#ibcon#about to read 3, iclass 19, count 0 2006.201.10:49:53.60#ibcon#read 3, iclass 19, count 0 2006.201.10:49:53.60#ibcon#about to read 4, iclass 19, count 0 2006.201.10:49:53.60#ibcon#read 4, iclass 19, count 0 2006.201.10:49:53.60#ibcon#about to read 5, iclass 19, count 0 2006.201.10:49:53.60#ibcon#read 5, iclass 19, count 0 2006.201.10:49:53.60#ibcon#about to read 6, iclass 19, count 0 2006.201.10:49:53.60#ibcon#read 6, iclass 19, count 0 2006.201.10:49:53.60#ibcon#end of sib2, iclass 19, count 0 2006.201.10:49:53.60#ibcon#*mode == 0, iclass 19, count 0 2006.201.10:49:53.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.10:49:53.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:49:53.60#ibcon#*before write, iclass 19, count 0 2006.201.10:49:53.60#ibcon#enter sib2, iclass 19, count 0 2006.201.10:49:53.60#ibcon#flushed, iclass 19, count 0 2006.201.10:49:53.60#ibcon#about to write, iclass 19, count 0 2006.201.10:49:53.60#ibcon#wrote, iclass 19, count 0 2006.201.10:49:53.60#ibcon#about to read 3, iclass 19, count 0 2006.201.10:49:53.65#ibcon#read 3, iclass 19, count 0 2006.201.10:49:53.65#ibcon#about to read 4, iclass 19, count 0 2006.201.10:49:53.65#ibcon#read 4, iclass 19, count 0 2006.201.10:49:53.65#ibcon#about to read 5, iclass 19, count 0 2006.201.10:49:53.65#ibcon#read 5, iclass 19, count 0 2006.201.10:49:53.65#ibcon#about to read 6, iclass 19, count 0 2006.201.10:49:53.65#ibcon#read 6, iclass 19, count 0 2006.201.10:49:53.65#ibcon#end of sib2, iclass 19, count 0 2006.201.10:49:53.65#ibcon#*after write, iclass 19, count 0 2006.201.10:49:53.65#ibcon#*before return 0, iclass 19, count 0 2006.201.10:49:53.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:53.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.10:49:53.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.10:49:53.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.10:49:53.65$vck44/vb=1,4 2006.201.10:49:53.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.10:49:53.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.10:49:53.65#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:53.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:53.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:53.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:53.65#ibcon#enter wrdev, iclass 21, count 2 2006.201.10:49:53.65#ibcon#first serial, iclass 21, count 2 2006.201.10:49:53.65#ibcon#enter sib2, iclass 21, count 2 2006.201.10:49:53.65#ibcon#flushed, iclass 21, count 2 2006.201.10:49:53.65#ibcon#about to write, iclass 21, count 2 2006.201.10:49:53.65#ibcon#wrote, iclass 21, count 2 2006.201.10:49:53.65#ibcon#about to read 3, iclass 21, count 2 2006.201.10:49:53.67#ibcon#read 3, iclass 21, count 2 2006.201.10:49:53.67#ibcon#about to read 4, iclass 21, count 2 2006.201.10:49:53.67#ibcon#read 4, iclass 21, count 2 2006.201.10:49:53.67#ibcon#about to read 5, iclass 21, count 2 2006.201.10:49:53.67#ibcon#read 5, iclass 21, count 2 2006.201.10:49:53.67#ibcon#about to read 6, iclass 21, count 2 2006.201.10:49:53.67#ibcon#read 6, iclass 21, count 2 2006.201.10:49:53.67#ibcon#end of sib2, iclass 21, count 2 2006.201.10:49:53.67#ibcon#*mode == 0, iclass 21, count 2 2006.201.10:49:53.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.10:49:53.67#ibcon#[27=AT01-04\r\n] 2006.201.10:49:53.67#ibcon#*before write, iclass 21, count 2 2006.201.10:49:53.67#ibcon#enter sib2, iclass 21, count 2 2006.201.10:49:53.67#ibcon#flushed, iclass 21, count 2 2006.201.10:49:53.67#ibcon#about to write, iclass 21, count 2 2006.201.10:49:53.67#ibcon#wrote, iclass 21, count 2 2006.201.10:49:53.67#ibcon#about to read 3, iclass 21, count 2 2006.201.10:49:53.70#ibcon#read 3, iclass 21, count 2 2006.201.10:49:53.70#ibcon#about to read 4, iclass 21, count 2 2006.201.10:49:53.70#ibcon#read 4, iclass 21, count 2 2006.201.10:49:53.70#ibcon#about to read 5, iclass 21, count 2 2006.201.10:49:53.70#ibcon#read 5, iclass 21, count 2 2006.201.10:49:53.70#ibcon#about to read 6, iclass 21, count 2 2006.201.10:49:53.70#ibcon#read 6, iclass 21, count 2 2006.201.10:49:53.70#ibcon#end of sib2, iclass 21, count 2 2006.201.10:49:53.70#ibcon#*after write, iclass 21, count 2 2006.201.10:49:53.70#ibcon#*before return 0, iclass 21, count 2 2006.201.10:49:53.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:53.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.10:49:53.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.10:49:53.70#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:53.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:53.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:53.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:53.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.10:49:53.82#ibcon#first serial, iclass 21, count 0 2006.201.10:49:53.82#ibcon#enter sib2, iclass 21, count 0 2006.201.10:49:53.82#ibcon#flushed, iclass 21, count 0 2006.201.10:49:53.82#ibcon#about to write, iclass 21, count 0 2006.201.10:49:53.82#ibcon#wrote, iclass 21, count 0 2006.201.10:49:53.82#ibcon#about to read 3, iclass 21, count 0 2006.201.10:49:53.84#ibcon#read 3, iclass 21, count 0 2006.201.10:49:53.84#ibcon#about to read 4, iclass 21, count 0 2006.201.10:49:53.84#ibcon#read 4, iclass 21, count 0 2006.201.10:49:53.84#ibcon#about to read 5, iclass 21, count 0 2006.201.10:49:53.84#ibcon#read 5, iclass 21, count 0 2006.201.10:49:53.84#ibcon#about to read 6, iclass 21, count 0 2006.201.10:49:53.84#ibcon#read 6, iclass 21, count 0 2006.201.10:49:53.84#ibcon#end of sib2, iclass 21, count 0 2006.201.10:49:53.84#ibcon#*mode == 0, iclass 21, count 0 2006.201.10:49:53.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.10:49:53.84#ibcon#[27=USB\r\n] 2006.201.10:49:53.84#ibcon#*before write, iclass 21, count 0 2006.201.10:49:53.84#ibcon#enter sib2, iclass 21, count 0 2006.201.10:49:53.84#ibcon#flushed, iclass 21, count 0 2006.201.10:49:53.84#ibcon#about to write, iclass 21, count 0 2006.201.10:49:53.84#ibcon#wrote, iclass 21, count 0 2006.201.10:49:53.84#ibcon#about to read 3, iclass 21, count 0 2006.201.10:49:53.87#ibcon#read 3, iclass 21, count 0 2006.201.10:49:53.87#ibcon#about to read 4, iclass 21, count 0 2006.201.10:49:53.87#ibcon#read 4, iclass 21, count 0 2006.201.10:49:53.87#ibcon#about to read 5, iclass 21, count 0 2006.201.10:49:53.87#ibcon#read 5, iclass 21, count 0 2006.201.10:49:53.87#ibcon#about to read 6, iclass 21, count 0 2006.201.10:49:53.87#ibcon#read 6, iclass 21, count 0 2006.201.10:49:53.87#ibcon#end of sib2, iclass 21, count 0 2006.201.10:49:53.87#ibcon#*after write, iclass 21, count 0 2006.201.10:49:53.87#ibcon#*before return 0, iclass 21, count 0 2006.201.10:49:53.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:53.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.10:49:53.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.10:49:53.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.10:49:53.87$vck44/vblo=2,634.99 2006.201.10:49:53.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.10:49:53.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.10:49:53.87#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:53.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:49:53.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:49:53.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:49:53.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.10:49:53.87#ibcon#first serial, iclass 23, count 0 2006.201.10:49:53.87#ibcon#enter sib2, iclass 23, count 0 2006.201.10:49:53.87#ibcon#flushed, iclass 23, count 0 2006.201.10:49:53.87#ibcon#about to write, iclass 23, count 0 2006.201.10:49:53.87#ibcon#wrote, iclass 23, count 0 2006.201.10:49:53.87#ibcon#about to read 3, iclass 23, count 0 2006.201.10:49:53.89#ibcon#read 3, iclass 23, count 0 2006.201.10:49:53.89#ibcon#about to read 4, iclass 23, count 0 2006.201.10:49:53.89#ibcon#read 4, iclass 23, count 0 2006.201.10:49:53.89#ibcon#about to read 5, iclass 23, count 0 2006.201.10:49:53.89#ibcon#read 5, iclass 23, count 0 2006.201.10:49:53.89#ibcon#about to read 6, iclass 23, count 0 2006.201.10:49:53.89#ibcon#read 6, iclass 23, count 0 2006.201.10:49:53.89#ibcon#end of sib2, iclass 23, count 0 2006.201.10:49:53.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.10:49:53.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.10:49:53.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:49:53.89#ibcon#*before write, iclass 23, count 0 2006.201.10:49:53.89#ibcon#enter sib2, iclass 23, count 0 2006.201.10:49:53.89#ibcon#flushed, iclass 23, count 0 2006.201.10:49:53.89#ibcon#about to write, iclass 23, count 0 2006.201.10:49:53.89#ibcon#wrote, iclass 23, count 0 2006.201.10:49:53.89#ibcon#about to read 3, iclass 23, count 0 2006.201.10:49:53.93#ibcon#read 3, iclass 23, count 0 2006.201.10:49:53.93#ibcon#about to read 4, iclass 23, count 0 2006.201.10:49:53.93#ibcon#read 4, iclass 23, count 0 2006.201.10:49:53.93#ibcon#about to read 5, iclass 23, count 0 2006.201.10:49:53.93#ibcon#read 5, iclass 23, count 0 2006.201.10:49:53.93#ibcon#about to read 6, iclass 23, count 0 2006.201.10:49:53.93#ibcon#read 6, iclass 23, count 0 2006.201.10:49:53.93#ibcon#end of sib2, iclass 23, count 0 2006.201.10:49:53.93#ibcon#*after write, iclass 23, count 0 2006.201.10:49:53.93#ibcon#*before return 0, iclass 23, count 0 2006.201.10:49:53.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:49:53.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.10:49:53.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.10:49:53.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.10:49:53.93$vck44/vb=2,5 2006.201.10:49:53.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.10:49:53.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.10:49:53.93#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:53.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:49:53.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:49:53.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:49:53.99#ibcon#enter wrdev, iclass 25, count 2 2006.201.10:49:53.99#ibcon#first serial, iclass 25, count 2 2006.201.10:49:53.99#ibcon#enter sib2, iclass 25, count 2 2006.201.10:49:53.99#ibcon#flushed, iclass 25, count 2 2006.201.10:49:53.99#ibcon#about to write, iclass 25, count 2 2006.201.10:49:53.99#ibcon#wrote, iclass 25, count 2 2006.201.10:49:53.99#ibcon#about to read 3, iclass 25, count 2 2006.201.10:49:54.01#ibcon#read 3, iclass 25, count 2 2006.201.10:49:54.01#ibcon#about to read 4, iclass 25, count 2 2006.201.10:49:54.01#ibcon#read 4, iclass 25, count 2 2006.201.10:49:54.01#ibcon#about to read 5, iclass 25, count 2 2006.201.10:49:54.01#ibcon#read 5, iclass 25, count 2 2006.201.10:49:54.01#ibcon#about to read 6, iclass 25, count 2 2006.201.10:49:54.01#ibcon#read 6, iclass 25, count 2 2006.201.10:49:54.01#ibcon#end of sib2, iclass 25, count 2 2006.201.10:49:54.01#ibcon#*mode == 0, iclass 25, count 2 2006.201.10:49:54.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.10:49:54.01#ibcon#[27=AT02-05\r\n] 2006.201.10:49:54.01#ibcon#*before write, iclass 25, count 2 2006.201.10:49:54.01#ibcon#enter sib2, iclass 25, count 2 2006.201.10:49:54.01#ibcon#flushed, iclass 25, count 2 2006.201.10:49:54.01#ibcon#about to write, iclass 25, count 2 2006.201.10:49:54.01#ibcon#wrote, iclass 25, count 2 2006.201.10:49:54.01#ibcon#about to read 3, iclass 25, count 2 2006.201.10:49:54.04#ibcon#read 3, iclass 25, count 2 2006.201.10:49:54.04#ibcon#about to read 4, iclass 25, count 2 2006.201.10:49:54.04#ibcon#read 4, iclass 25, count 2 2006.201.10:49:54.04#ibcon#about to read 5, iclass 25, count 2 2006.201.10:49:54.04#ibcon#read 5, iclass 25, count 2 2006.201.10:49:54.04#ibcon#about to read 6, iclass 25, count 2 2006.201.10:49:54.04#ibcon#read 6, iclass 25, count 2 2006.201.10:49:54.04#ibcon#end of sib2, iclass 25, count 2 2006.201.10:49:54.04#ibcon#*after write, iclass 25, count 2 2006.201.10:49:54.04#ibcon#*before return 0, iclass 25, count 2 2006.201.10:49:54.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:49:54.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.10:49:54.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.10:49:54.04#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:54.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:49:54.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:49:54.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:49:54.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:49:54.16#ibcon#first serial, iclass 25, count 0 2006.201.10:49:54.16#ibcon#enter sib2, iclass 25, count 0 2006.201.10:49:54.16#ibcon#flushed, iclass 25, count 0 2006.201.10:49:54.16#ibcon#about to write, iclass 25, count 0 2006.201.10:49:54.16#ibcon#wrote, iclass 25, count 0 2006.201.10:49:54.16#ibcon#about to read 3, iclass 25, count 0 2006.201.10:49:54.18#ibcon#read 3, iclass 25, count 0 2006.201.10:49:54.18#ibcon#about to read 4, iclass 25, count 0 2006.201.10:49:54.18#ibcon#read 4, iclass 25, count 0 2006.201.10:49:54.18#ibcon#about to read 5, iclass 25, count 0 2006.201.10:49:54.18#ibcon#read 5, iclass 25, count 0 2006.201.10:49:54.18#ibcon#about to read 6, iclass 25, count 0 2006.201.10:49:54.18#ibcon#read 6, iclass 25, count 0 2006.201.10:49:54.18#ibcon#end of sib2, iclass 25, count 0 2006.201.10:49:54.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:49:54.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:49:54.18#ibcon#[27=USB\r\n] 2006.201.10:49:54.18#ibcon#*before write, iclass 25, count 0 2006.201.10:49:54.18#ibcon#enter sib2, iclass 25, count 0 2006.201.10:49:54.18#ibcon#flushed, iclass 25, count 0 2006.201.10:49:54.18#ibcon#about to write, iclass 25, count 0 2006.201.10:49:54.18#ibcon#wrote, iclass 25, count 0 2006.201.10:49:54.18#ibcon#about to read 3, iclass 25, count 0 2006.201.10:49:54.21#ibcon#read 3, iclass 25, count 0 2006.201.10:49:54.21#ibcon#about to read 4, iclass 25, count 0 2006.201.10:49:54.21#ibcon#read 4, iclass 25, count 0 2006.201.10:49:54.21#ibcon#about to read 5, iclass 25, count 0 2006.201.10:49:54.21#ibcon#read 5, iclass 25, count 0 2006.201.10:49:54.21#ibcon#about to read 6, iclass 25, count 0 2006.201.10:49:54.21#ibcon#read 6, iclass 25, count 0 2006.201.10:49:54.21#ibcon#end of sib2, iclass 25, count 0 2006.201.10:49:54.21#ibcon#*after write, iclass 25, count 0 2006.201.10:49:54.21#ibcon#*before return 0, iclass 25, count 0 2006.201.10:49:54.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:49:54.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.10:49:54.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:49:54.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:49:54.21$vck44/vblo=3,649.99 2006.201.10:49:54.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.10:49:54.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.10:49:54.21#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:54.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:49:54.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:49:54.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:49:54.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.10:49:54.21#ibcon#first serial, iclass 27, count 0 2006.201.10:49:54.21#ibcon#enter sib2, iclass 27, count 0 2006.201.10:49:54.21#ibcon#flushed, iclass 27, count 0 2006.201.10:49:54.21#ibcon#about to write, iclass 27, count 0 2006.201.10:49:54.21#ibcon#wrote, iclass 27, count 0 2006.201.10:49:54.21#ibcon#about to read 3, iclass 27, count 0 2006.201.10:49:54.23#ibcon#read 3, iclass 27, count 0 2006.201.10:49:54.23#ibcon#about to read 4, iclass 27, count 0 2006.201.10:49:54.23#ibcon#read 4, iclass 27, count 0 2006.201.10:49:54.23#ibcon#about to read 5, iclass 27, count 0 2006.201.10:49:54.23#ibcon#read 5, iclass 27, count 0 2006.201.10:49:54.23#ibcon#about to read 6, iclass 27, count 0 2006.201.10:49:54.23#ibcon#read 6, iclass 27, count 0 2006.201.10:49:54.23#ibcon#end of sib2, iclass 27, count 0 2006.201.10:49:54.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.10:49:54.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.10:49:54.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:49:54.23#ibcon#*before write, iclass 27, count 0 2006.201.10:49:54.23#ibcon#enter sib2, iclass 27, count 0 2006.201.10:49:54.23#ibcon#flushed, iclass 27, count 0 2006.201.10:49:54.23#ibcon#about to write, iclass 27, count 0 2006.201.10:49:54.23#ibcon#wrote, iclass 27, count 0 2006.201.10:49:54.23#ibcon#about to read 3, iclass 27, count 0 2006.201.10:49:54.27#ibcon#read 3, iclass 27, count 0 2006.201.10:49:54.27#ibcon#about to read 4, iclass 27, count 0 2006.201.10:49:54.27#ibcon#read 4, iclass 27, count 0 2006.201.10:49:54.27#ibcon#about to read 5, iclass 27, count 0 2006.201.10:49:54.27#ibcon#read 5, iclass 27, count 0 2006.201.10:49:54.27#ibcon#about to read 6, iclass 27, count 0 2006.201.10:49:54.27#ibcon#read 6, iclass 27, count 0 2006.201.10:49:54.27#ibcon#end of sib2, iclass 27, count 0 2006.201.10:49:54.27#ibcon#*after write, iclass 27, count 0 2006.201.10:49:54.27#ibcon#*before return 0, iclass 27, count 0 2006.201.10:49:54.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:49:54.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.10:49:54.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.10:49:54.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.10:49:54.27$vck44/vb=3,4 2006.201.10:49:54.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.10:49:54.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.10:49:54.27#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:54.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:54.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:54.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:54.33#ibcon#enter wrdev, iclass 29, count 2 2006.201.10:49:54.33#ibcon#first serial, iclass 29, count 2 2006.201.10:49:54.33#ibcon#enter sib2, iclass 29, count 2 2006.201.10:49:54.33#ibcon#flushed, iclass 29, count 2 2006.201.10:49:54.33#ibcon#about to write, iclass 29, count 2 2006.201.10:49:54.33#ibcon#wrote, iclass 29, count 2 2006.201.10:49:54.33#ibcon#about to read 3, iclass 29, count 2 2006.201.10:49:54.35#ibcon#read 3, iclass 29, count 2 2006.201.10:49:54.35#ibcon#about to read 4, iclass 29, count 2 2006.201.10:49:54.35#ibcon#read 4, iclass 29, count 2 2006.201.10:49:54.35#ibcon#about to read 5, iclass 29, count 2 2006.201.10:49:54.35#ibcon#read 5, iclass 29, count 2 2006.201.10:49:54.35#ibcon#about to read 6, iclass 29, count 2 2006.201.10:49:54.35#ibcon#read 6, iclass 29, count 2 2006.201.10:49:54.35#ibcon#end of sib2, iclass 29, count 2 2006.201.10:49:54.35#ibcon#*mode == 0, iclass 29, count 2 2006.201.10:49:54.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.10:49:54.35#ibcon#[27=AT03-04\r\n] 2006.201.10:49:54.35#ibcon#*before write, iclass 29, count 2 2006.201.10:49:54.35#ibcon#enter sib2, iclass 29, count 2 2006.201.10:49:54.35#ibcon#flushed, iclass 29, count 2 2006.201.10:49:54.35#ibcon#about to write, iclass 29, count 2 2006.201.10:49:54.35#ibcon#wrote, iclass 29, count 2 2006.201.10:49:54.35#ibcon#about to read 3, iclass 29, count 2 2006.201.10:49:54.38#ibcon#read 3, iclass 29, count 2 2006.201.10:49:54.38#ibcon#about to read 4, iclass 29, count 2 2006.201.10:49:54.38#ibcon#read 4, iclass 29, count 2 2006.201.10:49:54.38#ibcon#about to read 5, iclass 29, count 2 2006.201.10:49:54.38#ibcon#read 5, iclass 29, count 2 2006.201.10:49:54.38#ibcon#about to read 6, iclass 29, count 2 2006.201.10:49:54.38#ibcon#read 6, iclass 29, count 2 2006.201.10:49:54.38#ibcon#end of sib2, iclass 29, count 2 2006.201.10:49:54.38#ibcon#*after write, iclass 29, count 2 2006.201.10:49:54.38#ibcon#*before return 0, iclass 29, count 2 2006.201.10:49:54.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:54.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.10:49:54.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.10:49:54.38#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:54.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:54.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:54.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:54.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.10:49:54.50#ibcon#first serial, iclass 29, count 0 2006.201.10:49:54.50#ibcon#enter sib2, iclass 29, count 0 2006.201.10:49:54.50#ibcon#flushed, iclass 29, count 0 2006.201.10:49:54.50#ibcon#about to write, iclass 29, count 0 2006.201.10:49:54.50#ibcon#wrote, iclass 29, count 0 2006.201.10:49:54.50#ibcon#about to read 3, iclass 29, count 0 2006.201.10:49:54.52#ibcon#read 3, iclass 29, count 0 2006.201.10:49:54.52#ibcon#about to read 4, iclass 29, count 0 2006.201.10:49:54.52#ibcon#read 4, iclass 29, count 0 2006.201.10:49:54.52#ibcon#about to read 5, iclass 29, count 0 2006.201.10:49:54.52#ibcon#read 5, iclass 29, count 0 2006.201.10:49:54.52#ibcon#about to read 6, iclass 29, count 0 2006.201.10:49:54.52#ibcon#read 6, iclass 29, count 0 2006.201.10:49:54.52#ibcon#end of sib2, iclass 29, count 0 2006.201.10:49:54.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.10:49:54.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.10:49:54.52#ibcon#[27=USB\r\n] 2006.201.10:49:54.52#ibcon#*before write, iclass 29, count 0 2006.201.10:49:54.52#ibcon#enter sib2, iclass 29, count 0 2006.201.10:49:54.52#ibcon#flushed, iclass 29, count 0 2006.201.10:49:54.52#ibcon#about to write, iclass 29, count 0 2006.201.10:49:54.52#ibcon#wrote, iclass 29, count 0 2006.201.10:49:54.52#ibcon#about to read 3, iclass 29, count 0 2006.201.10:49:54.55#ibcon#read 3, iclass 29, count 0 2006.201.10:49:54.55#ibcon#about to read 4, iclass 29, count 0 2006.201.10:49:54.55#ibcon#read 4, iclass 29, count 0 2006.201.10:49:54.55#ibcon#about to read 5, iclass 29, count 0 2006.201.10:49:54.55#ibcon#read 5, iclass 29, count 0 2006.201.10:49:54.55#ibcon#about to read 6, iclass 29, count 0 2006.201.10:49:54.55#ibcon#read 6, iclass 29, count 0 2006.201.10:49:54.55#ibcon#end of sib2, iclass 29, count 0 2006.201.10:49:54.55#ibcon#*after write, iclass 29, count 0 2006.201.10:49:54.55#ibcon#*before return 0, iclass 29, count 0 2006.201.10:49:54.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:54.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.10:49:54.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.10:49:54.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.10:49:54.55$vck44/vblo=4,679.99 2006.201.10:49:54.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.10:49:54.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.10:49:54.55#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:54.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:54.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:54.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:54.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.10:49:54.55#ibcon#first serial, iclass 31, count 0 2006.201.10:49:54.55#ibcon#enter sib2, iclass 31, count 0 2006.201.10:49:54.55#ibcon#flushed, iclass 31, count 0 2006.201.10:49:54.55#ibcon#about to write, iclass 31, count 0 2006.201.10:49:54.55#ibcon#wrote, iclass 31, count 0 2006.201.10:49:54.55#ibcon#about to read 3, iclass 31, count 0 2006.201.10:49:54.57#ibcon#read 3, iclass 31, count 0 2006.201.10:49:54.57#ibcon#about to read 4, iclass 31, count 0 2006.201.10:49:54.57#ibcon#read 4, iclass 31, count 0 2006.201.10:49:54.57#ibcon#about to read 5, iclass 31, count 0 2006.201.10:49:54.57#ibcon#read 5, iclass 31, count 0 2006.201.10:49:54.57#ibcon#about to read 6, iclass 31, count 0 2006.201.10:49:54.57#ibcon#read 6, iclass 31, count 0 2006.201.10:49:54.57#ibcon#end of sib2, iclass 31, count 0 2006.201.10:49:54.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.10:49:54.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.10:49:54.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:49:54.57#ibcon#*before write, iclass 31, count 0 2006.201.10:49:54.57#ibcon#enter sib2, iclass 31, count 0 2006.201.10:49:54.57#ibcon#flushed, iclass 31, count 0 2006.201.10:49:54.57#ibcon#about to write, iclass 31, count 0 2006.201.10:49:54.57#ibcon#wrote, iclass 31, count 0 2006.201.10:49:54.57#ibcon#about to read 3, iclass 31, count 0 2006.201.10:49:54.61#ibcon#read 3, iclass 31, count 0 2006.201.10:49:54.61#ibcon#about to read 4, iclass 31, count 0 2006.201.10:49:54.61#ibcon#read 4, iclass 31, count 0 2006.201.10:49:54.61#ibcon#about to read 5, iclass 31, count 0 2006.201.10:49:54.61#ibcon#read 5, iclass 31, count 0 2006.201.10:49:54.61#ibcon#about to read 6, iclass 31, count 0 2006.201.10:49:54.61#ibcon#read 6, iclass 31, count 0 2006.201.10:49:54.61#ibcon#end of sib2, iclass 31, count 0 2006.201.10:49:54.61#ibcon#*after write, iclass 31, count 0 2006.201.10:49:54.61#ibcon#*before return 0, iclass 31, count 0 2006.201.10:49:54.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:54.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.10:49:54.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.10:49:54.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.10:49:54.61$vck44/vb=4,5 2006.201.10:49:54.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.10:49:54.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.10:49:54.61#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:54.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:54.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:54.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:54.67#ibcon#enter wrdev, iclass 33, count 2 2006.201.10:49:54.67#ibcon#first serial, iclass 33, count 2 2006.201.10:49:54.67#ibcon#enter sib2, iclass 33, count 2 2006.201.10:49:54.67#ibcon#flushed, iclass 33, count 2 2006.201.10:49:54.67#ibcon#about to write, iclass 33, count 2 2006.201.10:49:54.67#ibcon#wrote, iclass 33, count 2 2006.201.10:49:54.67#ibcon#about to read 3, iclass 33, count 2 2006.201.10:49:54.69#ibcon#read 3, iclass 33, count 2 2006.201.10:49:54.69#ibcon#about to read 4, iclass 33, count 2 2006.201.10:49:54.69#ibcon#read 4, iclass 33, count 2 2006.201.10:49:54.69#ibcon#about to read 5, iclass 33, count 2 2006.201.10:49:54.69#ibcon#read 5, iclass 33, count 2 2006.201.10:49:54.69#ibcon#about to read 6, iclass 33, count 2 2006.201.10:49:54.69#ibcon#read 6, iclass 33, count 2 2006.201.10:49:54.69#ibcon#end of sib2, iclass 33, count 2 2006.201.10:49:54.69#ibcon#*mode == 0, iclass 33, count 2 2006.201.10:49:54.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.10:49:54.69#ibcon#[27=AT04-05\r\n] 2006.201.10:49:54.69#ibcon#*before write, iclass 33, count 2 2006.201.10:49:54.69#ibcon#enter sib2, iclass 33, count 2 2006.201.10:49:54.69#ibcon#flushed, iclass 33, count 2 2006.201.10:49:54.69#ibcon#about to write, iclass 33, count 2 2006.201.10:49:54.69#ibcon#wrote, iclass 33, count 2 2006.201.10:49:54.69#ibcon#about to read 3, iclass 33, count 2 2006.201.10:49:54.72#ibcon#read 3, iclass 33, count 2 2006.201.10:49:54.72#ibcon#about to read 4, iclass 33, count 2 2006.201.10:49:54.72#ibcon#read 4, iclass 33, count 2 2006.201.10:49:54.72#ibcon#about to read 5, iclass 33, count 2 2006.201.10:49:54.72#ibcon#read 5, iclass 33, count 2 2006.201.10:49:54.72#ibcon#about to read 6, iclass 33, count 2 2006.201.10:49:54.72#ibcon#read 6, iclass 33, count 2 2006.201.10:49:54.72#ibcon#end of sib2, iclass 33, count 2 2006.201.10:49:54.72#ibcon#*after write, iclass 33, count 2 2006.201.10:49:54.72#ibcon#*before return 0, iclass 33, count 2 2006.201.10:49:54.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:54.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.10:49:54.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.10:49:54.72#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:54.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:54.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:54.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:54.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.10:49:54.84#ibcon#first serial, iclass 33, count 0 2006.201.10:49:54.84#ibcon#enter sib2, iclass 33, count 0 2006.201.10:49:54.84#ibcon#flushed, iclass 33, count 0 2006.201.10:49:54.84#ibcon#about to write, iclass 33, count 0 2006.201.10:49:54.84#ibcon#wrote, iclass 33, count 0 2006.201.10:49:54.84#ibcon#about to read 3, iclass 33, count 0 2006.201.10:49:54.86#ibcon#read 3, iclass 33, count 0 2006.201.10:49:54.86#ibcon#about to read 4, iclass 33, count 0 2006.201.10:49:54.86#ibcon#read 4, iclass 33, count 0 2006.201.10:49:54.86#ibcon#about to read 5, iclass 33, count 0 2006.201.10:49:54.86#ibcon#read 5, iclass 33, count 0 2006.201.10:49:54.86#ibcon#about to read 6, iclass 33, count 0 2006.201.10:49:54.86#ibcon#read 6, iclass 33, count 0 2006.201.10:49:54.86#ibcon#end of sib2, iclass 33, count 0 2006.201.10:49:54.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.10:49:54.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.10:49:54.86#ibcon#[27=USB\r\n] 2006.201.10:49:54.86#ibcon#*before write, iclass 33, count 0 2006.201.10:49:54.86#ibcon#enter sib2, iclass 33, count 0 2006.201.10:49:54.86#ibcon#flushed, iclass 33, count 0 2006.201.10:49:54.86#ibcon#about to write, iclass 33, count 0 2006.201.10:49:54.86#ibcon#wrote, iclass 33, count 0 2006.201.10:49:54.86#ibcon#about to read 3, iclass 33, count 0 2006.201.10:49:54.89#ibcon#read 3, iclass 33, count 0 2006.201.10:49:54.89#ibcon#about to read 4, iclass 33, count 0 2006.201.10:49:54.89#ibcon#read 4, iclass 33, count 0 2006.201.10:49:54.89#ibcon#about to read 5, iclass 33, count 0 2006.201.10:49:54.89#ibcon#read 5, iclass 33, count 0 2006.201.10:49:54.89#ibcon#about to read 6, iclass 33, count 0 2006.201.10:49:54.89#ibcon#read 6, iclass 33, count 0 2006.201.10:49:54.89#ibcon#end of sib2, iclass 33, count 0 2006.201.10:49:54.89#ibcon#*after write, iclass 33, count 0 2006.201.10:49:54.89#ibcon#*before return 0, iclass 33, count 0 2006.201.10:49:54.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:54.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.10:49:54.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.10:49:54.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.10:49:54.89$vck44/vblo=5,709.99 2006.201.10:49:54.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.10:49:54.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.10:49:54.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:54.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:54.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:54.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:54.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.10:49:54.89#ibcon#first serial, iclass 35, count 0 2006.201.10:49:54.89#ibcon#enter sib2, iclass 35, count 0 2006.201.10:49:54.89#ibcon#flushed, iclass 35, count 0 2006.201.10:49:54.89#ibcon#about to write, iclass 35, count 0 2006.201.10:49:54.89#ibcon#wrote, iclass 35, count 0 2006.201.10:49:54.89#ibcon#about to read 3, iclass 35, count 0 2006.201.10:49:54.91#ibcon#read 3, iclass 35, count 0 2006.201.10:49:54.91#ibcon#about to read 4, iclass 35, count 0 2006.201.10:49:54.91#ibcon#read 4, iclass 35, count 0 2006.201.10:49:54.91#ibcon#about to read 5, iclass 35, count 0 2006.201.10:49:54.91#ibcon#read 5, iclass 35, count 0 2006.201.10:49:54.91#ibcon#about to read 6, iclass 35, count 0 2006.201.10:49:54.91#ibcon#read 6, iclass 35, count 0 2006.201.10:49:54.91#ibcon#end of sib2, iclass 35, count 0 2006.201.10:49:54.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.10:49:54.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.10:49:54.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:49:54.91#ibcon#*before write, iclass 35, count 0 2006.201.10:49:54.91#ibcon#enter sib2, iclass 35, count 0 2006.201.10:49:54.91#ibcon#flushed, iclass 35, count 0 2006.201.10:49:54.91#ibcon#about to write, iclass 35, count 0 2006.201.10:49:54.91#ibcon#wrote, iclass 35, count 0 2006.201.10:49:54.91#ibcon#about to read 3, iclass 35, count 0 2006.201.10:49:54.95#ibcon#read 3, iclass 35, count 0 2006.201.10:49:54.95#ibcon#about to read 4, iclass 35, count 0 2006.201.10:49:54.95#ibcon#read 4, iclass 35, count 0 2006.201.10:49:54.95#ibcon#about to read 5, iclass 35, count 0 2006.201.10:49:54.95#ibcon#read 5, iclass 35, count 0 2006.201.10:49:54.95#ibcon#about to read 6, iclass 35, count 0 2006.201.10:49:54.95#ibcon#read 6, iclass 35, count 0 2006.201.10:49:54.95#ibcon#end of sib2, iclass 35, count 0 2006.201.10:49:54.95#ibcon#*after write, iclass 35, count 0 2006.201.10:49:54.95#ibcon#*before return 0, iclass 35, count 0 2006.201.10:49:54.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:54.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.10:49:54.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.10:49:54.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.10:49:54.95$vck44/vb=5,4 2006.201.10:49:54.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.10:49:54.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.10:49:54.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:54.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:55.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:55.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:55.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.10:49:55.01#ibcon#first serial, iclass 37, count 2 2006.201.10:49:55.01#ibcon#enter sib2, iclass 37, count 2 2006.201.10:49:55.01#ibcon#flushed, iclass 37, count 2 2006.201.10:49:55.01#ibcon#about to write, iclass 37, count 2 2006.201.10:49:55.01#ibcon#wrote, iclass 37, count 2 2006.201.10:49:55.01#ibcon#about to read 3, iclass 37, count 2 2006.201.10:49:55.03#ibcon#read 3, iclass 37, count 2 2006.201.10:49:55.03#ibcon#about to read 4, iclass 37, count 2 2006.201.10:49:55.03#ibcon#read 4, iclass 37, count 2 2006.201.10:49:55.03#ibcon#about to read 5, iclass 37, count 2 2006.201.10:49:55.03#ibcon#read 5, iclass 37, count 2 2006.201.10:49:55.03#ibcon#about to read 6, iclass 37, count 2 2006.201.10:49:55.03#ibcon#read 6, iclass 37, count 2 2006.201.10:49:55.03#ibcon#end of sib2, iclass 37, count 2 2006.201.10:49:55.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.10:49:55.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.10:49:55.03#ibcon#[27=AT05-04\r\n] 2006.201.10:49:55.03#ibcon#*before write, iclass 37, count 2 2006.201.10:49:55.03#ibcon#enter sib2, iclass 37, count 2 2006.201.10:49:55.03#ibcon#flushed, iclass 37, count 2 2006.201.10:49:55.03#ibcon#about to write, iclass 37, count 2 2006.201.10:49:55.03#ibcon#wrote, iclass 37, count 2 2006.201.10:49:55.03#ibcon#about to read 3, iclass 37, count 2 2006.201.10:49:55.06#ibcon#read 3, iclass 37, count 2 2006.201.10:49:55.06#ibcon#about to read 4, iclass 37, count 2 2006.201.10:49:55.06#ibcon#read 4, iclass 37, count 2 2006.201.10:49:55.06#ibcon#about to read 5, iclass 37, count 2 2006.201.10:49:55.06#ibcon#read 5, iclass 37, count 2 2006.201.10:49:55.06#ibcon#about to read 6, iclass 37, count 2 2006.201.10:49:55.06#ibcon#read 6, iclass 37, count 2 2006.201.10:49:55.06#ibcon#end of sib2, iclass 37, count 2 2006.201.10:49:55.06#ibcon#*after write, iclass 37, count 2 2006.201.10:49:55.06#ibcon#*before return 0, iclass 37, count 2 2006.201.10:49:55.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:55.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.10:49:55.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.10:49:55.06#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:55.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:55.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:55.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:55.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.10:49:55.18#ibcon#first serial, iclass 37, count 0 2006.201.10:49:55.18#ibcon#enter sib2, iclass 37, count 0 2006.201.10:49:55.18#ibcon#flushed, iclass 37, count 0 2006.201.10:49:55.18#ibcon#about to write, iclass 37, count 0 2006.201.10:49:55.18#ibcon#wrote, iclass 37, count 0 2006.201.10:49:55.18#ibcon#about to read 3, iclass 37, count 0 2006.201.10:49:55.21#ibcon#read 3, iclass 37, count 0 2006.201.10:49:55.21#ibcon#about to read 4, iclass 37, count 0 2006.201.10:49:55.21#ibcon#read 4, iclass 37, count 0 2006.201.10:49:55.21#ibcon#about to read 5, iclass 37, count 0 2006.201.10:49:55.21#ibcon#read 5, iclass 37, count 0 2006.201.10:49:55.21#ibcon#about to read 6, iclass 37, count 0 2006.201.10:49:55.21#ibcon#read 6, iclass 37, count 0 2006.201.10:49:55.21#ibcon#end of sib2, iclass 37, count 0 2006.201.10:49:55.21#ibcon#*mode == 0, iclass 37, count 0 2006.201.10:49:55.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.10:49:55.21#ibcon#[27=USB\r\n] 2006.201.10:49:55.21#ibcon#*before write, iclass 37, count 0 2006.201.10:49:55.21#ibcon#enter sib2, iclass 37, count 0 2006.201.10:49:55.21#ibcon#flushed, iclass 37, count 0 2006.201.10:49:55.21#ibcon#about to write, iclass 37, count 0 2006.201.10:49:55.21#ibcon#wrote, iclass 37, count 0 2006.201.10:49:55.21#ibcon#about to read 3, iclass 37, count 0 2006.201.10:49:55.24#ibcon#read 3, iclass 37, count 0 2006.201.10:49:55.24#ibcon#about to read 4, iclass 37, count 0 2006.201.10:49:55.24#ibcon#read 4, iclass 37, count 0 2006.201.10:49:55.24#ibcon#about to read 5, iclass 37, count 0 2006.201.10:49:55.24#ibcon#read 5, iclass 37, count 0 2006.201.10:49:55.24#ibcon#about to read 6, iclass 37, count 0 2006.201.10:49:55.24#ibcon#read 6, iclass 37, count 0 2006.201.10:49:55.24#ibcon#end of sib2, iclass 37, count 0 2006.201.10:49:55.24#ibcon#*after write, iclass 37, count 0 2006.201.10:49:55.24#ibcon#*before return 0, iclass 37, count 0 2006.201.10:49:55.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:55.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.10:49:55.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.10:49:55.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.10:49:55.24$vck44/vblo=6,719.99 2006.201.10:49:55.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.10:49:55.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.10:49:55.24#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:55.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:55.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:55.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:55.24#ibcon#enter wrdev, iclass 39, count 0 2006.201.10:49:55.24#ibcon#first serial, iclass 39, count 0 2006.201.10:49:55.24#ibcon#enter sib2, iclass 39, count 0 2006.201.10:49:55.24#ibcon#flushed, iclass 39, count 0 2006.201.10:49:55.24#ibcon#about to write, iclass 39, count 0 2006.201.10:49:55.24#ibcon#wrote, iclass 39, count 0 2006.201.10:49:55.24#ibcon#about to read 3, iclass 39, count 0 2006.201.10:49:55.26#ibcon#read 3, iclass 39, count 0 2006.201.10:49:55.26#ibcon#about to read 4, iclass 39, count 0 2006.201.10:49:55.26#ibcon#read 4, iclass 39, count 0 2006.201.10:49:55.26#ibcon#about to read 5, iclass 39, count 0 2006.201.10:49:55.26#ibcon#read 5, iclass 39, count 0 2006.201.10:49:55.26#ibcon#about to read 6, iclass 39, count 0 2006.201.10:49:55.26#ibcon#read 6, iclass 39, count 0 2006.201.10:49:55.26#ibcon#end of sib2, iclass 39, count 0 2006.201.10:49:55.26#ibcon#*mode == 0, iclass 39, count 0 2006.201.10:49:55.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.10:49:55.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:49:55.26#ibcon#*before write, iclass 39, count 0 2006.201.10:49:55.26#ibcon#enter sib2, iclass 39, count 0 2006.201.10:49:55.26#ibcon#flushed, iclass 39, count 0 2006.201.10:49:55.26#ibcon#about to write, iclass 39, count 0 2006.201.10:49:55.26#ibcon#wrote, iclass 39, count 0 2006.201.10:49:55.26#ibcon#about to read 3, iclass 39, count 0 2006.201.10:49:55.30#ibcon#read 3, iclass 39, count 0 2006.201.10:49:55.30#ibcon#about to read 4, iclass 39, count 0 2006.201.10:49:55.30#ibcon#read 4, iclass 39, count 0 2006.201.10:49:55.30#ibcon#about to read 5, iclass 39, count 0 2006.201.10:49:55.30#ibcon#read 5, iclass 39, count 0 2006.201.10:49:55.30#ibcon#about to read 6, iclass 39, count 0 2006.201.10:49:55.30#ibcon#read 6, iclass 39, count 0 2006.201.10:49:55.30#ibcon#end of sib2, iclass 39, count 0 2006.201.10:49:55.30#ibcon#*after write, iclass 39, count 0 2006.201.10:49:55.30#ibcon#*before return 0, iclass 39, count 0 2006.201.10:49:55.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:55.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.10:49:55.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.10:49:55.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.10:49:55.30$vck44/vb=6,4 2006.201.10:49:55.30#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.10:49:55.30#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.10:49:55.30#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:55.30#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:55.36#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:55.36#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:55.36#ibcon#enter wrdev, iclass 2, count 2 2006.201.10:49:55.36#ibcon#first serial, iclass 2, count 2 2006.201.10:49:55.36#ibcon#enter sib2, iclass 2, count 2 2006.201.10:49:55.36#ibcon#flushed, iclass 2, count 2 2006.201.10:49:55.36#ibcon#about to write, iclass 2, count 2 2006.201.10:49:55.36#ibcon#wrote, iclass 2, count 2 2006.201.10:49:55.36#ibcon#about to read 3, iclass 2, count 2 2006.201.10:49:55.38#ibcon#read 3, iclass 2, count 2 2006.201.10:49:55.38#ibcon#about to read 4, iclass 2, count 2 2006.201.10:49:55.38#ibcon#read 4, iclass 2, count 2 2006.201.10:49:55.38#ibcon#about to read 5, iclass 2, count 2 2006.201.10:49:55.38#ibcon#read 5, iclass 2, count 2 2006.201.10:49:55.38#ibcon#about to read 6, iclass 2, count 2 2006.201.10:49:55.38#ibcon#read 6, iclass 2, count 2 2006.201.10:49:55.38#ibcon#end of sib2, iclass 2, count 2 2006.201.10:49:55.38#ibcon#*mode == 0, iclass 2, count 2 2006.201.10:49:55.38#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.10:49:55.38#ibcon#[27=AT06-04\r\n] 2006.201.10:49:55.38#ibcon#*before write, iclass 2, count 2 2006.201.10:49:55.38#ibcon#enter sib2, iclass 2, count 2 2006.201.10:49:55.38#ibcon#flushed, iclass 2, count 2 2006.201.10:49:55.38#ibcon#about to write, iclass 2, count 2 2006.201.10:49:55.38#ibcon#wrote, iclass 2, count 2 2006.201.10:49:55.38#ibcon#about to read 3, iclass 2, count 2 2006.201.10:49:55.41#ibcon#read 3, iclass 2, count 2 2006.201.10:49:55.41#ibcon#about to read 4, iclass 2, count 2 2006.201.10:49:55.41#ibcon#read 4, iclass 2, count 2 2006.201.10:49:55.41#ibcon#about to read 5, iclass 2, count 2 2006.201.10:49:55.41#ibcon#read 5, iclass 2, count 2 2006.201.10:49:55.41#ibcon#about to read 6, iclass 2, count 2 2006.201.10:49:55.41#ibcon#read 6, iclass 2, count 2 2006.201.10:49:55.41#ibcon#end of sib2, iclass 2, count 2 2006.201.10:49:55.41#ibcon#*after write, iclass 2, count 2 2006.201.10:49:55.41#ibcon#*before return 0, iclass 2, count 2 2006.201.10:49:55.41#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:55.41#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.10:49:55.41#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.10:49:55.41#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:55.41#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:55.53#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:55.53#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:55.53#ibcon#enter wrdev, iclass 2, count 0 2006.201.10:49:55.53#ibcon#first serial, iclass 2, count 0 2006.201.10:49:55.53#ibcon#enter sib2, iclass 2, count 0 2006.201.10:49:55.53#ibcon#flushed, iclass 2, count 0 2006.201.10:49:55.53#ibcon#about to write, iclass 2, count 0 2006.201.10:49:55.53#ibcon#wrote, iclass 2, count 0 2006.201.10:49:55.53#ibcon#about to read 3, iclass 2, count 0 2006.201.10:49:55.55#ibcon#read 3, iclass 2, count 0 2006.201.10:49:55.55#ibcon#about to read 4, iclass 2, count 0 2006.201.10:49:55.55#ibcon#read 4, iclass 2, count 0 2006.201.10:49:55.55#ibcon#about to read 5, iclass 2, count 0 2006.201.10:49:55.55#ibcon#read 5, iclass 2, count 0 2006.201.10:49:55.55#ibcon#about to read 6, iclass 2, count 0 2006.201.10:49:55.55#ibcon#read 6, iclass 2, count 0 2006.201.10:49:55.55#ibcon#end of sib2, iclass 2, count 0 2006.201.10:49:55.55#ibcon#*mode == 0, iclass 2, count 0 2006.201.10:49:55.55#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.10:49:55.55#ibcon#[27=USB\r\n] 2006.201.10:49:55.55#ibcon#*before write, iclass 2, count 0 2006.201.10:49:55.55#ibcon#enter sib2, iclass 2, count 0 2006.201.10:49:55.55#ibcon#flushed, iclass 2, count 0 2006.201.10:49:55.55#ibcon#about to write, iclass 2, count 0 2006.201.10:49:55.55#ibcon#wrote, iclass 2, count 0 2006.201.10:49:55.55#ibcon#about to read 3, iclass 2, count 0 2006.201.10:49:55.58#ibcon#read 3, iclass 2, count 0 2006.201.10:49:55.58#ibcon#about to read 4, iclass 2, count 0 2006.201.10:49:55.58#ibcon#read 4, iclass 2, count 0 2006.201.10:49:55.58#ibcon#about to read 5, iclass 2, count 0 2006.201.10:49:55.58#ibcon#read 5, iclass 2, count 0 2006.201.10:49:55.58#ibcon#about to read 6, iclass 2, count 0 2006.201.10:49:55.58#ibcon#read 6, iclass 2, count 0 2006.201.10:49:55.58#ibcon#end of sib2, iclass 2, count 0 2006.201.10:49:55.58#ibcon#*after write, iclass 2, count 0 2006.201.10:49:55.58#ibcon#*before return 0, iclass 2, count 0 2006.201.10:49:55.58#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:55.58#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.10:49:55.58#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.10:49:55.58#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.10:49:55.58$vck44/vblo=7,734.99 2006.201.10:49:55.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.10:49:55.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.10:49:55.58#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:55.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:55.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:55.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:55.58#ibcon#enter wrdev, iclass 5, count 0 2006.201.10:49:55.58#ibcon#first serial, iclass 5, count 0 2006.201.10:49:55.58#ibcon#enter sib2, iclass 5, count 0 2006.201.10:49:55.58#ibcon#flushed, iclass 5, count 0 2006.201.10:49:55.58#ibcon#about to write, iclass 5, count 0 2006.201.10:49:55.58#ibcon#wrote, iclass 5, count 0 2006.201.10:49:55.58#ibcon#about to read 3, iclass 5, count 0 2006.201.10:49:55.60#ibcon#read 3, iclass 5, count 0 2006.201.10:49:55.60#ibcon#about to read 4, iclass 5, count 0 2006.201.10:49:55.60#ibcon#read 4, iclass 5, count 0 2006.201.10:49:55.60#ibcon#about to read 5, iclass 5, count 0 2006.201.10:49:55.60#ibcon#read 5, iclass 5, count 0 2006.201.10:49:55.60#ibcon#about to read 6, iclass 5, count 0 2006.201.10:49:55.60#ibcon#read 6, iclass 5, count 0 2006.201.10:49:55.60#ibcon#end of sib2, iclass 5, count 0 2006.201.10:49:55.60#ibcon#*mode == 0, iclass 5, count 0 2006.201.10:49:55.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.10:49:55.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:49:55.60#ibcon#*before write, iclass 5, count 0 2006.201.10:49:55.60#ibcon#enter sib2, iclass 5, count 0 2006.201.10:49:55.60#ibcon#flushed, iclass 5, count 0 2006.201.10:49:55.60#ibcon#about to write, iclass 5, count 0 2006.201.10:49:55.60#ibcon#wrote, iclass 5, count 0 2006.201.10:49:55.60#ibcon#about to read 3, iclass 5, count 0 2006.201.10:49:55.64#ibcon#read 3, iclass 5, count 0 2006.201.10:49:55.64#ibcon#about to read 4, iclass 5, count 0 2006.201.10:49:55.64#ibcon#read 4, iclass 5, count 0 2006.201.10:49:55.64#ibcon#about to read 5, iclass 5, count 0 2006.201.10:49:55.64#ibcon#read 5, iclass 5, count 0 2006.201.10:49:55.64#ibcon#about to read 6, iclass 5, count 0 2006.201.10:49:55.64#ibcon#read 6, iclass 5, count 0 2006.201.10:49:55.64#ibcon#end of sib2, iclass 5, count 0 2006.201.10:49:55.64#ibcon#*after write, iclass 5, count 0 2006.201.10:49:55.64#ibcon#*before return 0, iclass 5, count 0 2006.201.10:49:55.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:55.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.10:49:55.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.10:49:55.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.10:49:55.64$vck44/vb=7,4 2006.201.10:49:55.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.10:49:55.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.10:49:55.64#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:55.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:55.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:55.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:55.70#ibcon#enter wrdev, iclass 7, count 2 2006.201.10:49:55.70#ibcon#first serial, iclass 7, count 2 2006.201.10:49:55.70#ibcon#enter sib2, iclass 7, count 2 2006.201.10:49:55.70#ibcon#flushed, iclass 7, count 2 2006.201.10:49:55.70#ibcon#about to write, iclass 7, count 2 2006.201.10:49:55.70#ibcon#wrote, iclass 7, count 2 2006.201.10:49:55.70#ibcon#about to read 3, iclass 7, count 2 2006.201.10:49:55.72#ibcon#read 3, iclass 7, count 2 2006.201.10:49:55.72#ibcon#about to read 4, iclass 7, count 2 2006.201.10:49:55.72#ibcon#read 4, iclass 7, count 2 2006.201.10:49:55.72#ibcon#about to read 5, iclass 7, count 2 2006.201.10:49:55.72#ibcon#read 5, iclass 7, count 2 2006.201.10:49:55.72#ibcon#about to read 6, iclass 7, count 2 2006.201.10:49:55.72#ibcon#read 6, iclass 7, count 2 2006.201.10:49:55.72#ibcon#end of sib2, iclass 7, count 2 2006.201.10:49:55.72#ibcon#*mode == 0, iclass 7, count 2 2006.201.10:49:55.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.10:49:55.72#ibcon#[27=AT07-04\r\n] 2006.201.10:49:55.72#ibcon#*before write, iclass 7, count 2 2006.201.10:49:55.72#ibcon#enter sib2, iclass 7, count 2 2006.201.10:49:55.72#ibcon#flushed, iclass 7, count 2 2006.201.10:49:55.72#ibcon#about to write, iclass 7, count 2 2006.201.10:49:55.72#ibcon#wrote, iclass 7, count 2 2006.201.10:49:55.72#ibcon#about to read 3, iclass 7, count 2 2006.201.10:49:55.75#ibcon#read 3, iclass 7, count 2 2006.201.10:49:55.75#ibcon#about to read 4, iclass 7, count 2 2006.201.10:49:55.75#ibcon#read 4, iclass 7, count 2 2006.201.10:49:55.75#ibcon#about to read 5, iclass 7, count 2 2006.201.10:49:55.75#ibcon#read 5, iclass 7, count 2 2006.201.10:49:55.75#ibcon#about to read 6, iclass 7, count 2 2006.201.10:49:55.75#ibcon#read 6, iclass 7, count 2 2006.201.10:49:55.75#ibcon#end of sib2, iclass 7, count 2 2006.201.10:49:55.75#ibcon#*after write, iclass 7, count 2 2006.201.10:49:55.75#ibcon#*before return 0, iclass 7, count 2 2006.201.10:49:55.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:55.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.10:49:55.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.10:49:55.75#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:55.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:55.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:55.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:55.87#ibcon#enter wrdev, iclass 7, count 0 2006.201.10:49:55.87#ibcon#first serial, iclass 7, count 0 2006.201.10:49:55.87#ibcon#enter sib2, iclass 7, count 0 2006.201.10:49:55.87#ibcon#flushed, iclass 7, count 0 2006.201.10:49:55.87#ibcon#about to write, iclass 7, count 0 2006.201.10:49:55.87#ibcon#wrote, iclass 7, count 0 2006.201.10:49:55.87#ibcon#about to read 3, iclass 7, count 0 2006.201.10:49:55.89#ibcon#read 3, iclass 7, count 0 2006.201.10:49:55.89#ibcon#about to read 4, iclass 7, count 0 2006.201.10:49:55.89#ibcon#read 4, iclass 7, count 0 2006.201.10:49:55.89#ibcon#about to read 5, iclass 7, count 0 2006.201.10:49:55.89#ibcon#read 5, iclass 7, count 0 2006.201.10:49:55.89#ibcon#about to read 6, iclass 7, count 0 2006.201.10:49:55.89#ibcon#read 6, iclass 7, count 0 2006.201.10:49:55.89#ibcon#end of sib2, iclass 7, count 0 2006.201.10:49:55.89#ibcon#*mode == 0, iclass 7, count 0 2006.201.10:49:55.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.10:49:55.89#ibcon#[27=USB\r\n] 2006.201.10:49:55.89#ibcon#*before write, iclass 7, count 0 2006.201.10:49:55.89#ibcon#enter sib2, iclass 7, count 0 2006.201.10:49:55.89#ibcon#flushed, iclass 7, count 0 2006.201.10:49:55.89#ibcon#about to write, iclass 7, count 0 2006.201.10:49:55.89#ibcon#wrote, iclass 7, count 0 2006.201.10:49:55.89#ibcon#about to read 3, iclass 7, count 0 2006.201.10:49:55.92#ibcon#read 3, iclass 7, count 0 2006.201.10:49:55.92#ibcon#about to read 4, iclass 7, count 0 2006.201.10:49:55.92#ibcon#read 4, iclass 7, count 0 2006.201.10:49:55.92#ibcon#about to read 5, iclass 7, count 0 2006.201.10:49:55.92#ibcon#read 5, iclass 7, count 0 2006.201.10:49:55.92#ibcon#about to read 6, iclass 7, count 0 2006.201.10:49:55.92#ibcon#read 6, iclass 7, count 0 2006.201.10:49:55.92#ibcon#end of sib2, iclass 7, count 0 2006.201.10:49:55.92#ibcon#*after write, iclass 7, count 0 2006.201.10:49:55.92#ibcon#*before return 0, iclass 7, count 0 2006.201.10:49:55.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:55.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.10:49:55.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.10:49:55.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.10:49:55.92$vck44/vblo=8,744.99 2006.201.10:49:55.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.10:49:55.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.10:49:55.92#ibcon#ireg 17 cls_cnt 0 2006.201.10:49:55.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:55.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:55.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:55.92#ibcon#enter wrdev, iclass 11, count 0 2006.201.10:49:55.92#ibcon#first serial, iclass 11, count 0 2006.201.10:49:55.92#ibcon#enter sib2, iclass 11, count 0 2006.201.10:49:55.92#ibcon#flushed, iclass 11, count 0 2006.201.10:49:55.92#ibcon#about to write, iclass 11, count 0 2006.201.10:49:55.92#ibcon#wrote, iclass 11, count 0 2006.201.10:49:55.92#ibcon#about to read 3, iclass 11, count 0 2006.201.10:49:55.94#ibcon#read 3, iclass 11, count 0 2006.201.10:49:55.94#ibcon#about to read 4, iclass 11, count 0 2006.201.10:49:55.94#ibcon#read 4, iclass 11, count 0 2006.201.10:49:55.94#ibcon#about to read 5, iclass 11, count 0 2006.201.10:49:55.94#ibcon#read 5, iclass 11, count 0 2006.201.10:49:55.94#ibcon#about to read 6, iclass 11, count 0 2006.201.10:49:55.94#ibcon#read 6, iclass 11, count 0 2006.201.10:49:55.94#ibcon#end of sib2, iclass 11, count 0 2006.201.10:49:55.94#ibcon#*mode == 0, iclass 11, count 0 2006.201.10:49:55.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.10:49:55.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:49:55.94#ibcon#*before write, iclass 11, count 0 2006.201.10:49:55.94#ibcon#enter sib2, iclass 11, count 0 2006.201.10:49:55.94#ibcon#flushed, iclass 11, count 0 2006.201.10:49:55.94#ibcon#about to write, iclass 11, count 0 2006.201.10:49:55.94#ibcon#wrote, iclass 11, count 0 2006.201.10:49:55.94#ibcon#about to read 3, iclass 11, count 0 2006.201.10:49:55.99#ibcon#read 3, iclass 11, count 0 2006.201.10:49:55.99#ibcon#about to read 4, iclass 11, count 0 2006.201.10:49:55.99#ibcon#read 4, iclass 11, count 0 2006.201.10:49:55.99#ibcon#about to read 5, iclass 11, count 0 2006.201.10:49:55.99#ibcon#read 5, iclass 11, count 0 2006.201.10:49:55.99#ibcon#about to read 6, iclass 11, count 0 2006.201.10:49:55.99#ibcon#read 6, iclass 11, count 0 2006.201.10:49:55.99#ibcon#end of sib2, iclass 11, count 0 2006.201.10:49:55.99#ibcon#*after write, iclass 11, count 0 2006.201.10:49:55.99#ibcon#*before return 0, iclass 11, count 0 2006.201.10:49:55.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:55.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.10:49:55.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.10:49:55.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.10:49:55.99$vck44/vb=8,4 2006.201.10:49:55.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.10:49:55.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.10:49:55.99#ibcon#ireg 11 cls_cnt 2 2006.201.10:49:55.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:56.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:56.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:56.04#ibcon#enter wrdev, iclass 13, count 2 2006.201.10:49:56.04#ibcon#first serial, iclass 13, count 2 2006.201.10:49:56.04#ibcon#enter sib2, iclass 13, count 2 2006.201.10:49:56.04#ibcon#flushed, iclass 13, count 2 2006.201.10:49:56.04#ibcon#about to write, iclass 13, count 2 2006.201.10:49:56.04#ibcon#wrote, iclass 13, count 2 2006.201.10:49:56.04#ibcon#about to read 3, iclass 13, count 2 2006.201.10:49:56.06#ibcon#read 3, iclass 13, count 2 2006.201.10:49:56.06#ibcon#about to read 4, iclass 13, count 2 2006.201.10:49:56.06#ibcon#read 4, iclass 13, count 2 2006.201.10:49:56.06#ibcon#about to read 5, iclass 13, count 2 2006.201.10:49:56.06#ibcon#read 5, iclass 13, count 2 2006.201.10:49:56.06#ibcon#about to read 6, iclass 13, count 2 2006.201.10:49:56.06#ibcon#read 6, iclass 13, count 2 2006.201.10:49:56.06#ibcon#end of sib2, iclass 13, count 2 2006.201.10:49:56.06#ibcon#*mode == 0, iclass 13, count 2 2006.201.10:49:56.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.10:49:56.06#ibcon#[27=AT08-04\r\n] 2006.201.10:49:56.06#ibcon#*before write, iclass 13, count 2 2006.201.10:49:56.06#ibcon#enter sib2, iclass 13, count 2 2006.201.10:49:56.06#ibcon#flushed, iclass 13, count 2 2006.201.10:49:56.06#ibcon#about to write, iclass 13, count 2 2006.201.10:49:56.06#ibcon#wrote, iclass 13, count 2 2006.201.10:49:56.06#ibcon#about to read 3, iclass 13, count 2 2006.201.10:49:56.09#ibcon#read 3, iclass 13, count 2 2006.201.10:49:56.09#ibcon#about to read 4, iclass 13, count 2 2006.201.10:49:56.09#ibcon#read 4, iclass 13, count 2 2006.201.10:49:56.09#ibcon#about to read 5, iclass 13, count 2 2006.201.10:49:56.09#ibcon#read 5, iclass 13, count 2 2006.201.10:49:56.09#ibcon#about to read 6, iclass 13, count 2 2006.201.10:49:56.09#ibcon#read 6, iclass 13, count 2 2006.201.10:49:56.09#ibcon#end of sib2, iclass 13, count 2 2006.201.10:49:56.09#ibcon#*after write, iclass 13, count 2 2006.201.10:49:56.09#ibcon#*before return 0, iclass 13, count 2 2006.201.10:49:56.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:56.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.10:49:56.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.10:49:56.09#ibcon#ireg 7 cls_cnt 0 2006.201.10:49:56.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:56.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:56.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:56.21#ibcon#enter wrdev, iclass 13, count 0 2006.201.10:49:56.21#ibcon#first serial, iclass 13, count 0 2006.201.10:49:56.21#ibcon#enter sib2, iclass 13, count 0 2006.201.10:49:56.21#ibcon#flushed, iclass 13, count 0 2006.201.10:49:56.21#ibcon#about to write, iclass 13, count 0 2006.201.10:49:56.21#ibcon#wrote, iclass 13, count 0 2006.201.10:49:56.21#ibcon#about to read 3, iclass 13, count 0 2006.201.10:49:56.24#ibcon#read 3, iclass 13, count 0 2006.201.10:49:56.24#ibcon#about to read 4, iclass 13, count 0 2006.201.10:49:56.24#ibcon#read 4, iclass 13, count 0 2006.201.10:49:56.24#ibcon#about to read 5, iclass 13, count 0 2006.201.10:49:56.24#ibcon#read 5, iclass 13, count 0 2006.201.10:49:56.24#ibcon#about to read 6, iclass 13, count 0 2006.201.10:49:56.24#ibcon#read 6, iclass 13, count 0 2006.201.10:49:56.24#ibcon#end of sib2, iclass 13, count 0 2006.201.10:49:56.24#ibcon#*mode == 0, iclass 13, count 0 2006.201.10:49:56.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.10:49:56.24#ibcon#[27=USB\r\n] 2006.201.10:49:56.24#ibcon#*before write, iclass 13, count 0 2006.201.10:49:56.24#ibcon#enter sib2, iclass 13, count 0 2006.201.10:49:56.24#ibcon#flushed, iclass 13, count 0 2006.201.10:49:56.24#ibcon#about to write, iclass 13, count 0 2006.201.10:49:56.24#ibcon#wrote, iclass 13, count 0 2006.201.10:49:56.24#ibcon#about to read 3, iclass 13, count 0 2006.201.10:49:56.27#ibcon#read 3, iclass 13, count 0 2006.201.10:49:56.27#ibcon#about to read 4, iclass 13, count 0 2006.201.10:49:56.27#ibcon#read 4, iclass 13, count 0 2006.201.10:49:56.27#ibcon#about to read 5, iclass 13, count 0 2006.201.10:49:56.27#ibcon#read 5, iclass 13, count 0 2006.201.10:49:56.27#ibcon#about to read 6, iclass 13, count 0 2006.201.10:49:56.27#ibcon#read 6, iclass 13, count 0 2006.201.10:49:56.27#ibcon#end of sib2, iclass 13, count 0 2006.201.10:49:56.27#ibcon#*after write, iclass 13, count 0 2006.201.10:49:56.27#ibcon#*before return 0, iclass 13, count 0 2006.201.10:49:56.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:56.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.10:49:56.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.10:49:56.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.10:49:56.27$vck44/vabw=wide 2006.201.10:49:56.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.10:49:56.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.10:49:56.27#ibcon#ireg 8 cls_cnt 0 2006.201.10:49:56.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:56.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:56.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:56.27#ibcon#enter wrdev, iclass 15, count 0 2006.201.10:49:56.27#ibcon#first serial, iclass 15, count 0 2006.201.10:49:56.27#ibcon#enter sib2, iclass 15, count 0 2006.201.10:49:56.27#ibcon#flushed, iclass 15, count 0 2006.201.10:49:56.27#ibcon#about to write, iclass 15, count 0 2006.201.10:49:56.27#ibcon#wrote, iclass 15, count 0 2006.201.10:49:56.27#ibcon#about to read 3, iclass 15, count 0 2006.201.10:49:56.29#ibcon#read 3, iclass 15, count 0 2006.201.10:49:56.29#ibcon#about to read 4, iclass 15, count 0 2006.201.10:49:56.29#ibcon#read 4, iclass 15, count 0 2006.201.10:49:56.29#ibcon#about to read 5, iclass 15, count 0 2006.201.10:49:56.29#ibcon#read 5, iclass 15, count 0 2006.201.10:49:56.29#ibcon#about to read 6, iclass 15, count 0 2006.201.10:49:56.29#ibcon#read 6, iclass 15, count 0 2006.201.10:49:56.29#ibcon#end of sib2, iclass 15, count 0 2006.201.10:49:56.29#ibcon#*mode == 0, iclass 15, count 0 2006.201.10:49:56.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.10:49:56.29#ibcon#[25=BW32\r\n] 2006.201.10:49:56.29#ibcon#*before write, iclass 15, count 0 2006.201.10:49:56.29#ibcon#enter sib2, iclass 15, count 0 2006.201.10:49:56.29#ibcon#flushed, iclass 15, count 0 2006.201.10:49:56.29#ibcon#about to write, iclass 15, count 0 2006.201.10:49:56.29#ibcon#wrote, iclass 15, count 0 2006.201.10:49:56.29#ibcon#about to read 3, iclass 15, count 0 2006.201.10:49:56.32#ibcon#read 3, iclass 15, count 0 2006.201.10:49:56.32#ibcon#about to read 4, iclass 15, count 0 2006.201.10:49:56.32#ibcon#read 4, iclass 15, count 0 2006.201.10:49:56.32#ibcon#about to read 5, iclass 15, count 0 2006.201.10:49:56.32#ibcon#read 5, iclass 15, count 0 2006.201.10:49:56.32#ibcon#about to read 6, iclass 15, count 0 2006.201.10:49:56.32#ibcon#read 6, iclass 15, count 0 2006.201.10:49:56.32#ibcon#end of sib2, iclass 15, count 0 2006.201.10:49:56.32#ibcon#*after write, iclass 15, count 0 2006.201.10:49:56.32#ibcon#*before return 0, iclass 15, count 0 2006.201.10:49:56.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:56.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.10:49:56.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.10:49:56.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.10:49:56.32$vck44/vbbw=wide 2006.201.10:49:56.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.10:49:56.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.10:49:56.32#ibcon#ireg 8 cls_cnt 0 2006.201.10:49:56.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:49:56.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:49:56.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:49:56.39#ibcon#enter wrdev, iclass 17, count 0 2006.201.10:49:56.39#ibcon#first serial, iclass 17, count 0 2006.201.10:49:56.39#ibcon#enter sib2, iclass 17, count 0 2006.201.10:49:56.39#ibcon#flushed, iclass 17, count 0 2006.201.10:49:56.39#ibcon#about to write, iclass 17, count 0 2006.201.10:49:56.39#ibcon#wrote, iclass 17, count 0 2006.201.10:49:56.39#ibcon#about to read 3, iclass 17, count 0 2006.201.10:49:56.41#ibcon#read 3, iclass 17, count 0 2006.201.10:49:56.41#ibcon#about to read 4, iclass 17, count 0 2006.201.10:49:56.41#ibcon#read 4, iclass 17, count 0 2006.201.10:49:56.41#ibcon#about to read 5, iclass 17, count 0 2006.201.10:49:56.41#ibcon#read 5, iclass 17, count 0 2006.201.10:49:56.41#ibcon#about to read 6, iclass 17, count 0 2006.201.10:49:56.41#ibcon#read 6, iclass 17, count 0 2006.201.10:49:56.41#ibcon#end of sib2, iclass 17, count 0 2006.201.10:49:56.41#ibcon#*mode == 0, iclass 17, count 0 2006.201.10:49:56.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.10:49:56.41#ibcon#[27=BW32\r\n] 2006.201.10:49:56.41#ibcon#*before write, iclass 17, count 0 2006.201.10:49:56.41#ibcon#enter sib2, iclass 17, count 0 2006.201.10:49:56.41#ibcon#flushed, iclass 17, count 0 2006.201.10:49:56.41#ibcon#about to write, iclass 17, count 0 2006.201.10:49:56.41#ibcon#wrote, iclass 17, count 0 2006.201.10:49:56.41#ibcon#about to read 3, iclass 17, count 0 2006.201.10:49:56.44#ibcon#read 3, iclass 17, count 0 2006.201.10:49:56.44#ibcon#about to read 4, iclass 17, count 0 2006.201.10:49:56.44#ibcon#read 4, iclass 17, count 0 2006.201.10:49:56.44#ibcon#about to read 5, iclass 17, count 0 2006.201.10:49:56.44#ibcon#read 5, iclass 17, count 0 2006.201.10:49:56.44#ibcon#about to read 6, iclass 17, count 0 2006.201.10:49:56.44#ibcon#read 6, iclass 17, count 0 2006.201.10:49:56.44#ibcon#end of sib2, iclass 17, count 0 2006.201.10:49:56.44#ibcon#*after write, iclass 17, count 0 2006.201.10:49:56.44#ibcon#*before return 0, iclass 17, count 0 2006.201.10:49:56.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:49:56.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.10:49:56.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.10:49:56.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.10:49:56.44$setupk4/ifdk4 2006.201.10:49:56.44$ifdk4/lo= 2006.201.10:49:56.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:49:56.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:49:56.44$ifdk4/patch= 2006.201.10:49:56.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:49:56.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:49:56.44$setupk4/!*+20s 2006.201.10:50:01.34#abcon#<5=/05 1.8 3.1 21.52 991003.7\r\n> 2006.201.10:50:01.36#abcon#{5=INTERFACE CLEAR} 2006.201.10:50:01.42#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:50:10.90$setupk4/"tpicd 2006.201.10:50:10.90$setupk4/echo=off 2006.201.10:50:10.90$setupk4/xlog=off 2006.201.10:50:10.90:!2006.201.10:50:47 2006.201.10:50:11.14#trakl#Source acquired 2006.201.10:50:13.14#flagr#flagr/antenna,acquired 2006.201.10:50:47.00:preob 2006.201.10:50:47.13/onsource/TRACKING 2006.201.10:50:47.13:!2006.201.10:50:57 2006.201.10:50:57.00:"tape 2006.201.10:50:57.00:"st=record 2006.201.10:50:57.00:data_valid=on 2006.201.10:50:57.00:midob 2006.201.10:50:58.13/onsource/TRACKING 2006.201.10:50:58.13/wx/21.52,1003.6,99 2006.201.10:50:58.28/cable/+6.4713E-03 2006.201.10:50:59.37/va/01,08,usb,yes,35,37 2006.201.10:50:59.37/va/02,07,usb,yes,38,38 2006.201.10:50:59.37/va/03,08,usb,yes,34,35 2006.201.10:50:59.37/va/04,07,usb,yes,39,41 2006.201.10:50:59.37/va/05,04,usb,yes,34,35 2006.201.10:50:59.37/va/06,05,usb,yes,34,34 2006.201.10:50:59.37/va/07,05,usb,yes,33,35 2006.201.10:50:59.37/va/08,04,usb,yes,33,40 2006.201.10:50:59.60/valo/01,524.99,yes,locked 2006.201.10:50:59.60/valo/02,534.99,yes,locked 2006.201.10:50:59.60/valo/03,564.99,yes,locked 2006.201.10:50:59.60/valo/04,624.99,yes,locked 2006.201.10:50:59.60/valo/05,734.99,yes,locked 2006.201.10:50:59.60/valo/06,814.99,yes,locked 2006.201.10:50:59.60/valo/07,864.99,yes,locked 2006.201.10:50:59.60/valo/08,884.99,yes,locked 2006.201.10:51:00.69/vb/01,04,usb,yes,32,30 2006.201.10:51:00.69/vb/02,05,usb,yes,31,30 2006.201.10:51:00.69/vb/03,04,usb,yes,32,35 2006.201.10:51:00.69/vb/04,05,usb,yes,32,31 2006.201.10:51:00.69/vb/05,04,usb,yes,28,31 2006.201.10:51:00.69/vb/06,04,usb,yes,33,29 2006.201.10:51:00.69/vb/07,04,usb,yes,33,33 2006.201.10:51:00.69/vb/08,04,usb,yes,30,34 2006.201.10:51:00.93/vblo/01,629.99,yes,locked 2006.201.10:51:00.93/vblo/02,634.99,yes,locked 2006.201.10:51:00.93/vblo/03,649.99,yes,locked 2006.201.10:51:00.93/vblo/04,679.99,yes,locked 2006.201.10:51:00.93/vblo/05,709.99,yes,locked 2006.201.10:51:00.93/vblo/06,719.99,yes,locked 2006.201.10:51:00.93/vblo/07,734.99,yes,locked 2006.201.10:51:00.93/vblo/08,744.99,yes,locked 2006.201.10:51:01.08/vabw/8 2006.201.10:51:01.23/vbbw/8 2006.201.10:51:01.32/xfe/off,on,14.7 2006.201.10:51:01.71/ifatt/23,28,28,28 2006.201.10:51:02.05/fmout-gps/S +4.56E-07 2006.201.10:51:02.12:!2006.201.10:51:37 2006.201.10:51:37.00:data_valid=off 2006.201.10:51:37.00:"et 2006.201.10:51:37.00:!+3s 2006.201.10:51:40.02:"tape 2006.201.10:51:40.02:postob 2006.201.10:51:40.15/cable/+6.4715E-03 2006.201.10:51:40.15/wx/21.51,1003.7,99 2006.201.10:51:40.22/fmout-gps/S +4.55E-07 2006.201.10:51:40.22:scan_name=201-1057,jd0607,370 2006.201.10:51:40.22:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.201.10:51:42.14#flagr#flagr/antenna,new-source 2006.201.10:51:42.14:checkk5 2006.201.10:51:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.10:51:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.10:51:43.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.10:51:43.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.10:51:44.01/chk_obsdata//k5ts1/T2011050??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:51:44.40/chk_obsdata//k5ts2/T2011050??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:51:44.77/chk_obsdata//k5ts3/T2011050??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:51:45.14/chk_obsdata//k5ts4/T2011050??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.10:51:45.82/k5log//k5ts1_log_newline 2006.201.10:51:46.50/k5log//k5ts2_log_newline 2006.201.10:51:47.19/k5log//k5ts3_log_newline 2006.201.10:51:47.87/k5log//k5ts4_log_newline 2006.201.10:51:47.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.10:51:47.90:setupk4=1 2006.201.10:51:47.90$setupk4/echo=on 2006.201.10:51:47.90$setupk4/pcalon 2006.201.10:51:47.90$pcalon/"no phase cal control is implemented here 2006.201.10:51:47.90$setupk4/"tpicd=stop 2006.201.10:51:47.90$setupk4/"rec=synch_on 2006.201.10:51:47.90$setupk4/"rec_mode=128 2006.201.10:51:47.90$setupk4/!* 2006.201.10:51:47.90$setupk4/recpk4 2006.201.10:51:47.90$recpk4/recpatch= 2006.201.10:51:47.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.10:51:47.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.10:51:47.90$setupk4/vck44 2006.201.10:51:47.90$vck44/valo=1,524.99 2006.201.10:51:47.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.10:51:47.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.10:51:47.90#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:47.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:47.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:47.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:47.90#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:51:47.90#ibcon#first serial, iclass 30, count 0 2006.201.10:51:47.90#ibcon#enter sib2, iclass 30, count 0 2006.201.10:51:47.90#ibcon#flushed, iclass 30, count 0 2006.201.10:51:47.90#ibcon#about to write, iclass 30, count 0 2006.201.10:51:47.90#ibcon#wrote, iclass 30, count 0 2006.201.10:51:47.90#ibcon#about to read 3, iclass 30, count 0 2006.201.10:51:47.92#ibcon#read 3, iclass 30, count 0 2006.201.10:51:47.92#ibcon#about to read 4, iclass 30, count 0 2006.201.10:51:47.92#ibcon#read 4, iclass 30, count 0 2006.201.10:51:47.92#ibcon#about to read 5, iclass 30, count 0 2006.201.10:51:47.92#ibcon#read 5, iclass 30, count 0 2006.201.10:51:47.92#ibcon#about to read 6, iclass 30, count 0 2006.201.10:51:47.92#ibcon#read 6, iclass 30, count 0 2006.201.10:51:47.92#ibcon#end of sib2, iclass 30, count 0 2006.201.10:51:47.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:51:47.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:51:47.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.10:51:47.92#ibcon#*before write, iclass 30, count 0 2006.201.10:51:47.92#ibcon#enter sib2, iclass 30, count 0 2006.201.10:51:47.92#ibcon#flushed, iclass 30, count 0 2006.201.10:51:47.92#ibcon#about to write, iclass 30, count 0 2006.201.10:51:47.92#ibcon#wrote, iclass 30, count 0 2006.201.10:51:47.92#ibcon#about to read 3, iclass 30, count 0 2006.201.10:51:47.97#ibcon#read 3, iclass 30, count 0 2006.201.10:51:47.97#ibcon#about to read 4, iclass 30, count 0 2006.201.10:51:47.97#ibcon#read 4, iclass 30, count 0 2006.201.10:51:47.97#ibcon#about to read 5, iclass 30, count 0 2006.201.10:51:47.97#ibcon#read 5, iclass 30, count 0 2006.201.10:51:47.97#ibcon#about to read 6, iclass 30, count 0 2006.201.10:51:47.97#ibcon#read 6, iclass 30, count 0 2006.201.10:51:47.97#ibcon#end of sib2, iclass 30, count 0 2006.201.10:51:47.97#ibcon#*after write, iclass 30, count 0 2006.201.10:51:47.97#ibcon#*before return 0, iclass 30, count 0 2006.201.10:51:47.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:47.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:47.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:51:47.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:51:47.97$vck44/va=1,8 2006.201.10:51:47.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.10:51:47.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.10:51:47.97#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:47.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:47.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:47.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:47.97#ibcon#enter wrdev, iclass 32, count 2 2006.201.10:51:47.97#ibcon#first serial, iclass 32, count 2 2006.201.10:51:47.97#ibcon#enter sib2, iclass 32, count 2 2006.201.10:51:47.97#ibcon#flushed, iclass 32, count 2 2006.201.10:51:47.97#ibcon#about to write, iclass 32, count 2 2006.201.10:51:47.97#ibcon#wrote, iclass 32, count 2 2006.201.10:51:47.97#ibcon#about to read 3, iclass 32, count 2 2006.201.10:51:47.99#ibcon#read 3, iclass 32, count 2 2006.201.10:51:47.99#ibcon#about to read 4, iclass 32, count 2 2006.201.10:51:47.99#ibcon#read 4, iclass 32, count 2 2006.201.10:51:47.99#ibcon#about to read 5, iclass 32, count 2 2006.201.10:51:47.99#ibcon#read 5, iclass 32, count 2 2006.201.10:51:47.99#ibcon#about to read 6, iclass 32, count 2 2006.201.10:51:47.99#ibcon#read 6, iclass 32, count 2 2006.201.10:51:47.99#ibcon#end of sib2, iclass 32, count 2 2006.201.10:51:47.99#ibcon#*mode == 0, iclass 32, count 2 2006.201.10:51:47.99#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.10:51:47.99#ibcon#[25=AT01-08\r\n] 2006.201.10:51:47.99#ibcon#*before write, iclass 32, count 2 2006.201.10:51:47.99#ibcon#enter sib2, iclass 32, count 2 2006.201.10:51:47.99#ibcon#flushed, iclass 32, count 2 2006.201.10:51:47.99#ibcon#about to write, iclass 32, count 2 2006.201.10:51:47.99#ibcon#wrote, iclass 32, count 2 2006.201.10:51:47.99#ibcon#about to read 3, iclass 32, count 2 2006.201.10:51:48.02#ibcon#read 3, iclass 32, count 2 2006.201.10:51:48.02#ibcon#about to read 4, iclass 32, count 2 2006.201.10:51:48.02#ibcon#read 4, iclass 32, count 2 2006.201.10:51:48.02#ibcon#about to read 5, iclass 32, count 2 2006.201.10:51:48.02#ibcon#read 5, iclass 32, count 2 2006.201.10:51:48.02#ibcon#about to read 6, iclass 32, count 2 2006.201.10:51:48.02#ibcon#read 6, iclass 32, count 2 2006.201.10:51:48.02#ibcon#end of sib2, iclass 32, count 2 2006.201.10:51:48.02#ibcon#*after write, iclass 32, count 2 2006.201.10:51:48.02#ibcon#*before return 0, iclass 32, count 2 2006.201.10:51:48.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:48.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:48.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.10:51:48.02#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:48.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:48.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:48.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:48.14#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:51:48.14#ibcon#first serial, iclass 32, count 0 2006.201.10:51:48.14#ibcon#enter sib2, iclass 32, count 0 2006.201.10:51:48.14#ibcon#flushed, iclass 32, count 0 2006.201.10:51:48.14#ibcon#about to write, iclass 32, count 0 2006.201.10:51:48.14#ibcon#wrote, iclass 32, count 0 2006.201.10:51:48.14#ibcon#about to read 3, iclass 32, count 0 2006.201.10:51:48.16#ibcon#read 3, iclass 32, count 0 2006.201.10:51:48.16#ibcon#about to read 4, iclass 32, count 0 2006.201.10:51:48.16#ibcon#read 4, iclass 32, count 0 2006.201.10:51:48.16#ibcon#about to read 5, iclass 32, count 0 2006.201.10:51:48.16#ibcon#read 5, iclass 32, count 0 2006.201.10:51:48.16#ibcon#about to read 6, iclass 32, count 0 2006.201.10:51:48.16#ibcon#read 6, iclass 32, count 0 2006.201.10:51:48.16#ibcon#end of sib2, iclass 32, count 0 2006.201.10:51:48.16#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:51:48.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:51:48.16#ibcon#[25=USB\r\n] 2006.201.10:51:48.16#ibcon#*before write, iclass 32, count 0 2006.201.10:51:48.16#ibcon#enter sib2, iclass 32, count 0 2006.201.10:51:48.16#ibcon#flushed, iclass 32, count 0 2006.201.10:51:48.16#ibcon#about to write, iclass 32, count 0 2006.201.10:51:48.16#ibcon#wrote, iclass 32, count 0 2006.201.10:51:48.16#ibcon#about to read 3, iclass 32, count 0 2006.201.10:51:48.19#ibcon#read 3, iclass 32, count 0 2006.201.10:51:48.19#ibcon#about to read 4, iclass 32, count 0 2006.201.10:51:48.19#ibcon#read 4, iclass 32, count 0 2006.201.10:51:48.19#ibcon#about to read 5, iclass 32, count 0 2006.201.10:51:48.19#ibcon#read 5, iclass 32, count 0 2006.201.10:51:48.19#ibcon#about to read 6, iclass 32, count 0 2006.201.10:51:48.19#ibcon#read 6, iclass 32, count 0 2006.201.10:51:48.19#ibcon#end of sib2, iclass 32, count 0 2006.201.10:51:48.19#ibcon#*after write, iclass 32, count 0 2006.201.10:51:48.19#ibcon#*before return 0, iclass 32, count 0 2006.201.10:51:48.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:48.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:48.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:51:48.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:51:48.19$vck44/valo=2,534.99 2006.201.10:51:48.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.10:51:48.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.10:51:48.19#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:48.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:48.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:48.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:48.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:51:48.19#ibcon#first serial, iclass 34, count 0 2006.201.10:51:48.19#ibcon#enter sib2, iclass 34, count 0 2006.201.10:51:48.19#ibcon#flushed, iclass 34, count 0 2006.201.10:51:48.19#ibcon#about to write, iclass 34, count 0 2006.201.10:51:48.19#ibcon#wrote, iclass 34, count 0 2006.201.10:51:48.19#ibcon#about to read 3, iclass 34, count 0 2006.201.10:51:48.21#ibcon#read 3, iclass 34, count 0 2006.201.10:51:48.21#ibcon#about to read 4, iclass 34, count 0 2006.201.10:51:48.21#ibcon#read 4, iclass 34, count 0 2006.201.10:51:48.21#ibcon#about to read 5, iclass 34, count 0 2006.201.10:51:48.21#ibcon#read 5, iclass 34, count 0 2006.201.10:51:48.21#ibcon#about to read 6, iclass 34, count 0 2006.201.10:51:48.21#ibcon#read 6, iclass 34, count 0 2006.201.10:51:48.21#ibcon#end of sib2, iclass 34, count 0 2006.201.10:51:48.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:51:48.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:51:48.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.10:51:48.21#ibcon#*before write, iclass 34, count 0 2006.201.10:51:48.21#ibcon#enter sib2, iclass 34, count 0 2006.201.10:51:48.21#ibcon#flushed, iclass 34, count 0 2006.201.10:51:48.21#ibcon#about to write, iclass 34, count 0 2006.201.10:51:48.21#ibcon#wrote, iclass 34, count 0 2006.201.10:51:48.21#ibcon#about to read 3, iclass 34, count 0 2006.201.10:51:48.26#ibcon#read 3, iclass 34, count 0 2006.201.10:51:48.26#ibcon#about to read 4, iclass 34, count 0 2006.201.10:51:48.26#ibcon#read 4, iclass 34, count 0 2006.201.10:51:48.26#ibcon#about to read 5, iclass 34, count 0 2006.201.10:51:48.26#ibcon#read 5, iclass 34, count 0 2006.201.10:51:48.26#ibcon#about to read 6, iclass 34, count 0 2006.201.10:51:48.26#ibcon#read 6, iclass 34, count 0 2006.201.10:51:48.26#ibcon#end of sib2, iclass 34, count 0 2006.201.10:51:48.26#ibcon#*after write, iclass 34, count 0 2006.201.10:51:48.26#ibcon#*before return 0, iclass 34, count 0 2006.201.10:51:48.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:48.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:48.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:51:48.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:51:48.26$vck44/va=2,7 2006.201.10:51:48.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.10:51:48.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.10:51:48.26#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:48.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:48.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:48.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:48.31#ibcon#enter wrdev, iclass 36, count 2 2006.201.10:51:48.31#ibcon#first serial, iclass 36, count 2 2006.201.10:51:48.31#ibcon#enter sib2, iclass 36, count 2 2006.201.10:51:48.31#ibcon#flushed, iclass 36, count 2 2006.201.10:51:48.31#ibcon#about to write, iclass 36, count 2 2006.201.10:51:48.31#ibcon#wrote, iclass 36, count 2 2006.201.10:51:48.31#ibcon#about to read 3, iclass 36, count 2 2006.201.10:51:48.33#ibcon#read 3, iclass 36, count 2 2006.201.10:51:48.33#ibcon#about to read 4, iclass 36, count 2 2006.201.10:51:48.33#ibcon#read 4, iclass 36, count 2 2006.201.10:51:48.33#ibcon#about to read 5, iclass 36, count 2 2006.201.10:51:48.33#ibcon#read 5, iclass 36, count 2 2006.201.10:51:48.33#ibcon#about to read 6, iclass 36, count 2 2006.201.10:51:48.33#ibcon#read 6, iclass 36, count 2 2006.201.10:51:48.33#ibcon#end of sib2, iclass 36, count 2 2006.201.10:51:48.33#ibcon#*mode == 0, iclass 36, count 2 2006.201.10:51:48.33#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.10:51:48.33#ibcon#[25=AT02-07\r\n] 2006.201.10:51:48.33#ibcon#*before write, iclass 36, count 2 2006.201.10:51:48.33#ibcon#enter sib2, iclass 36, count 2 2006.201.10:51:48.33#ibcon#flushed, iclass 36, count 2 2006.201.10:51:48.33#ibcon#about to write, iclass 36, count 2 2006.201.10:51:48.33#ibcon#wrote, iclass 36, count 2 2006.201.10:51:48.33#ibcon#about to read 3, iclass 36, count 2 2006.201.10:51:48.36#ibcon#read 3, iclass 36, count 2 2006.201.10:51:48.36#ibcon#about to read 4, iclass 36, count 2 2006.201.10:51:48.36#ibcon#read 4, iclass 36, count 2 2006.201.10:51:48.36#ibcon#about to read 5, iclass 36, count 2 2006.201.10:51:48.36#ibcon#read 5, iclass 36, count 2 2006.201.10:51:48.36#ibcon#about to read 6, iclass 36, count 2 2006.201.10:51:48.36#ibcon#read 6, iclass 36, count 2 2006.201.10:51:48.36#ibcon#end of sib2, iclass 36, count 2 2006.201.10:51:48.36#ibcon#*after write, iclass 36, count 2 2006.201.10:51:48.36#ibcon#*before return 0, iclass 36, count 2 2006.201.10:51:48.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:48.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:48.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.10:51:48.36#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:48.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:48.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:48.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:48.48#ibcon#enter wrdev, iclass 36, count 0 2006.201.10:51:48.48#ibcon#first serial, iclass 36, count 0 2006.201.10:51:48.48#ibcon#enter sib2, iclass 36, count 0 2006.201.10:51:48.48#ibcon#flushed, iclass 36, count 0 2006.201.10:51:48.48#ibcon#about to write, iclass 36, count 0 2006.201.10:51:48.48#ibcon#wrote, iclass 36, count 0 2006.201.10:51:48.48#ibcon#about to read 3, iclass 36, count 0 2006.201.10:51:48.50#ibcon#read 3, iclass 36, count 0 2006.201.10:51:48.50#ibcon#about to read 4, iclass 36, count 0 2006.201.10:51:48.50#ibcon#read 4, iclass 36, count 0 2006.201.10:51:48.50#ibcon#about to read 5, iclass 36, count 0 2006.201.10:51:48.50#ibcon#read 5, iclass 36, count 0 2006.201.10:51:48.50#ibcon#about to read 6, iclass 36, count 0 2006.201.10:51:48.50#ibcon#read 6, iclass 36, count 0 2006.201.10:51:48.50#ibcon#end of sib2, iclass 36, count 0 2006.201.10:51:48.50#ibcon#*mode == 0, iclass 36, count 0 2006.201.10:51:48.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.10:51:48.50#ibcon#[25=USB\r\n] 2006.201.10:51:48.50#ibcon#*before write, iclass 36, count 0 2006.201.10:51:48.50#ibcon#enter sib2, iclass 36, count 0 2006.201.10:51:48.50#ibcon#flushed, iclass 36, count 0 2006.201.10:51:48.50#ibcon#about to write, iclass 36, count 0 2006.201.10:51:48.50#ibcon#wrote, iclass 36, count 0 2006.201.10:51:48.50#ibcon#about to read 3, iclass 36, count 0 2006.201.10:51:48.53#ibcon#read 3, iclass 36, count 0 2006.201.10:51:48.53#ibcon#about to read 4, iclass 36, count 0 2006.201.10:51:48.53#ibcon#read 4, iclass 36, count 0 2006.201.10:51:48.53#ibcon#about to read 5, iclass 36, count 0 2006.201.10:51:48.53#ibcon#read 5, iclass 36, count 0 2006.201.10:51:48.53#ibcon#about to read 6, iclass 36, count 0 2006.201.10:51:48.53#ibcon#read 6, iclass 36, count 0 2006.201.10:51:48.53#ibcon#end of sib2, iclass 36, count 0 2006.201.10:51:48.53#ibcon#*after write, iclass 36, count 0 2006.201.10:51:48.53#ibcon#*before return 0, iclass 36, count 0 2006.201.10:51:48.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:48.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:48.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.10:51:48.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.10:51:48.53$vck44/valo=3,564.99 2006.201.10:51:48.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.10:51:48.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.10:51:48.53#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:48.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:48.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:48.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:48.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:51:48.53#ibcon#first serial, iclass 38, count 0 2006.201.10:51:48.53#ibcon#enter sib2, iclass 38, count 0 2006.201.10:51:48.53#ibcon#flushed, iclass 38, count 0 2006.201.10:51:48.53#ibcon#about to write, iclass 38, count 0 2006.201.10:51:48.53#ibcon#wrote, iclass 38, count 0 2006.201.10:51:48.53#ibcon#about to read 3, iclass 38, count 0 2006.201.10:51:48.55#ibcon#read 3, iclass 38, count 0 2006.201.10:51:48.55#ibcon#about to read 4, iclass 38, count 0 2006.201.10:51:48.55#ibcon#read 4, iclass 38, count 0 2006.201.10:51:48.55#ibcon#about to read 5, iclass 38, count 0 2006.201.10:51:48.55#ibcon#read 5, iclass 38, count 0 2006.201.10:51:48.55#ibcon#about to read 6, iclass 38, count 0 2006.201.10:51:48.55#ibcon#read 6, iclass 38, count 0 2006.201.10:51:48.55#ibcon#end of sib2, iclass 38, count 0 2006.201.10:51:48.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:51:48.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:51:48.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.10:51:48.55#ibcon#*before write, iclass 38, count 0 2006.201.10:51:48.55#ibcon#enter sib2, iclass 38, count 0 2006.201.10:51:48.55#ibcon#flushed, iclass 38, count 0 2006.201.10:51:48.55#ibcon#about to write, iclass 38, count 0 2006.201.10:51:48.55#ibcon#wrote, iclass 38, count 0 2006.201.10:51:48.55#ibcon#about to read 3, iclass 38, count 0 2006.201.10:51:48.60#ibcon#read 3, iclass 38, count 0 2006.201.10:51:48.60#ibcon#about to read 4, iclass 38, count 0 2006.201.10:51:48.60#ibcon#read 4, iclass 38, count 0 2006.201.10:51:48.60#ibcon#about to read 5, iclass 38, count 0 2006.201.10:51:48.60#ibcon#read 5, iclass 38, count 0 2006.201.10:51:48.60#ibcon#about to read 6, iclass 38, count 0 2006.201.10:51:48.60#ibcon#read 6, iclass 38, count 0 2006.201.10:51:48.60#ibcon#end of sib2, iclass 38, count 0 2006.201.10:51:48.60#ibcon#*after write, iclass 38, count 0 2006.201.10:51:48.60#ibcon#*before return 0, iclass 38, count 0 2006.201.10:51:48.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:48.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:48.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:51:48.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:51:48.60$vck44/va=3,8 2006.201.10:51:48.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.10:51:48.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.10:51:48.60#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:48.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:48.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:48.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:48.65#ibcon#enter wrdev, iclass 40, count 2 2006.201.10:51:48.65#ibcon#first serial, iclass 40, count 2 2006.201.10:51:48.65#ibcon#enter sib2, iclass 40, count 2 2006.201.10:51:48.65#ibcon#flushed, iclass 40, count 2 2006.201.10:51:48.65#ibcon#about to write, iclass 40, count 2 2006.201.10:51:48.65#ibcon#wrote, iclass 40, count 2 2006.201.10:51:48.65#ibcon#about to read 3, iclass 40, count 2 2006.201.10:51:48.67#ibcon#read 3, iclass 40, count 2 2006.201.10:51:48.67#ibcon#about to read 4, iclass 40, count 2 2006.201.10:51:48.67#ibcon#read 4, iclass 40, count 2 2006.201.10:51:48.67#ibcon#about to read 5, iclass 40, count 2 2006.201.10:51:48.67#ibcon#read 5, iclass 40, count 2 2006.201.10:51:48.67#ibcon#about to read 6, iclass 40, count 2 2006.201.10:51:48.67#ibcon#read 6, iclass 40, count 2 2006.201.10:51:48.67#ibcon#end of sib2, iclass 40, count 2 2006.201.10:51:48.67#ibcon#*mode == 0, iclass 40, count 2 2006.201.10:51:48.67#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.10:51:48.67#ibcon#[25=AT03-08\r\n] 2006.201.10:51:48.67#ibcon#*before write, iclass 40, count 2 2006.201.10:51:48.67#ibcon#enter sib2, iclass 40, count 2 2006.201.10:51:48.67#ibcon#flushed, iclass 40, count 2 2006.201.10:51:48.67#ibcon#about to write, iclass 40, count 2 2006.201.10:51:48.67#ibcon#wrote, iclass 40, count 2 2006.201.10:51:48.67#ibcon#about to read 3, iclass 40, count 2 2006.201.10:51:48.70#ibcon#read 3, iclass 40, count 2 2006.201.10:51:48.70#ibcon#about to read 4, iclass 40, count 2 2006.201.10:51:48.70#ibcon#read 4, iclass 40, count 2 2006.201.10:51:48.70#ibcon#about to read 5, iclass 40, count 2 2006.201.10:51:48.70#ibcon#read 5, iclass 40, count 2 2006.201.10:51:48.70#ibcon#about to read 6, iclass 40, count 2 2006.201.10:51:48.70#ibcon#read 6, iclass 40, count 2 2006.201.10:51:48.70#ibcon#end of sib2, iclass 40, count 2 2006.201.10:51:48.70#ibcon#*after write, iclass 40, count 2 2006.201.10:51:48.70#ibcon#*before return 0, iclass 40, count 2 2006.201.10:51:48.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:48.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:48.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.10:51:48.70#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:48.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:48.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:48.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:48.82#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:51:48.82#ibcon#first serial, iclass 40, count 0 2006.201.10:51:48.82#ibcon#enter sib2, iclass 40, count 0 2006.201.10:51:48.82#ibcon#flushed, iclass 40, count 0 2006.201.10:51:48.82#ibcon#about to write, iclass 40, count 0 2006.201.10:51:48.82#ibcon#wrote, iclass 40, count 0 2006.201.10:51:48.82#ibcon#about to read 3, iclass 40, count 0 2006.201.10:51:48.84#ibcon#read 3, iclass 40, count 0 2006.201.10:51:48.84#ibcon#about to read 4, iclass 40, count 0 2006.201.10:51:48.84#ibcon#read 4, iclass 40, count 0 2006.201.10:51:48.84#ibcon#about to read 5, iclass 40, count 0 2006.201.10:51:48.84#ibcon#read 5, iclass 40, count 0 2006.201.10:51:48.84#ibcon#about to read 6, iclass 40, count 0 2006.201.10:51:48.84#ibcon#read 6, iclass 40, count 0 2006.201.10:51:48.84#ibcon#end of sib2, iclass 40, count 0 2006.201.10:51:48.84#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:51:48.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:51:48.84#ibcon#[25=USB\r\n] 2006.201.10:51:48.84#ibcon#*before write, iclass 40, count 0 2006.201.10:51:48.84#ibcon#enter sib2, iclass 40, count 0 2006.201.10:51:48.84#ibcon#flushed, iclass 40, count 0 2006.201.10:51:48.84#ibcon#about to write, iclass 40, count 0 2006.201.10:51:48.84#ibcon#wrote, iclass 40, count 0 2006.201.10:51:48.84#ibcon#about to read 3, iclass 40, count 0 2006.201.10:51:48.87#ibcon#read 3, iclass 40, count 0 2006.201.10:51:48.87#ibcon#about to read 4, iclass 40, count 0 2006.201.10:51:48.87#ibcon#read 4, iclass 40, count 0 2006.201.10:51:48.87#ibcon#about to read 5, iclass 40, count 0 2006.201.10:51:48.87#ibcon#read 5, iclass 40, count 0 2006.201.10:51:48.87#ibcon#about to read 6, iclass 40, count 0 2006.201.10:51:48.87#ibcon#read 6, iclass 40, count 0 2006.201.10:51:48.87#ibcon#end of sib2, iclass 40, count 0 2006.201.10:51:48.87#ibcon#*after write, iclass 40, count 0 2006.201.10:51:48.87#ibcon#*before return 0, iclass 40, count 0 2006.201.10:51:48.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:48.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:48.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:51:48.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:51:48.87$vck44/valo=4,624.99 2006.201.10:51:48.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.10:51:48.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.10:51:48.87#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:48.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:48.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:48.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:48.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:51:48.87#ibcon#first serial, iclass 4, count 0 2006.201.10:51:48.87#ibcon#enter sib2, iclass 4, count 0 2006.201.10:51:48.87#ibcon#flushed, iclass 4, count 0 2006.201.10:51:48.87#ibcon#about to write, iclass 4, count 0 2006.201.10:51:48.87#ibcon#wrote, iclass 4, count 0 2006.201.10:51:48.87#ibcon#about to read 3, iclass 4, count 0 2006.201.10:51:48.89#ibcon#read 3, iclass 4, count 0 2006.201.10:51:48.89#ibcon#about to read 4, iclass 4, count 0 2006.201.10:51:48.89#ibcon#read 4, iclass 4, count 0 2006.201.10:51:48.89#ibcon#about to read 5, iclass 4, count 0 2006.201.10:51:48.89#ibcon#read 5, iclass 4, count 0 2006.201.10:51:48.89#ibcon#about to read 6, iclass 4, count 0 2006.201.10:51:48.89#ibcon#read 6, iclass 4, count 0 2006.201.10:51:48.89#ibcon#end of sib2, iclass 4, count 0 2006.201.10:51:48.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:51:48.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:51:48.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.10:51:48.89#ibcon#*before write, iclass 4, count 0 2006.201.10:51:48.89#ibcon#enter sib2, iclass 4, count 0 2006.201.10:51:48.89#ibcon#flushed, iclass 4, count 0 2006.201.10:51:48.89#ibcon#about to write, iclass 4, count 0 2006.201.10:51:48.89#ibcon#wrote, iclass 4, count 0 2006.201.10:51:48.89#ibcon#about to read 3, iclass 4, count 0 2006.201.10:51:48.94#ibcon#read 3, iclass 4, count 0 2006.201.10:51:48.94#ibcon#about to read 4, iclass 4, count 0 2006.201.10:51:48.94#ibcon#read 4, iclass 4, count 0 2006.201.10:51:48.94#ibcon#about to read 5, iclass 4, count 0 2006.201.10:51:48.94#ibcon#read 5, iclass 4, count 0 2006.201.10:51:48.94#ibcon#about to read 6, iclass 4, count 0 2006.201.10:51:48.94#ibcon#read 6, iclass 4, count 0 2006.201.10:51:48.94#ibcon#end of sib2, iclass 4, count 0 2006.201.10:51:48.94#ibcon#*after write, iclass 4, count 0 2006.201.10:51:48.94#ibcon#*before return 0, iclass 4, count 0 2006.201.10:51:48.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:48.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:48.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:51:48.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:51:48.94$vck44/va=4,7 2006.201.10:51:48.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.10:51:48.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.10:51:48.94#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:48.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:48.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:48.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:48.99#ibcon#enter wrdev, iclass 6, count 2 2006.201.10:51:48.99#ibcon#first serial, iclass 6, count 2 2006.201.10:51:48.99#ibcon#enter sib2, iclass 6, count 2 2006.201.10:51:48.99#ibcon#flushed, iclass 6, count 2 2006.201.10:51:48.99#ibcon#about to write, iclass 6, count 2 2006.201.10:51:48.99#ibcon#wrote, iclass 6, count 2 2006.201.10:51:48.99#ibcon#about to read 3, iclass 6, count 2 2006.201.10:51:49.01#ibcon#read 3, iclass 6, count 2 2006.201.10:51:49.01#ibcon#about to read 4, iclass 6, count 2 2006.201.10:51:49.01#ibcon#read 4, iclass 6, count 2 2006.201.10:51:49.01#ibcon#about to read 5, iclass 6, count 2 2006.201.10:51:49.01#ibcon#read 5, iclass 6, count 2 2006.201.10:51:49.01#ibcon#about to read 6, iclass 6, count 2 2006.201.10:51:49.01#ibcon#read 6, iclass 6, count 2 2006.201.10:51:49.01#ibcon#end of sib2, iclass 6, count 2 2006.201.10:51:49.01#ibcon#*mode == 0, iclass 6, count 2 2006.201.10:51:49.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.10:51:49.01#ibcon#[25=AT04-07\r\n] 2006.201.10:51:49.01#ibcon#*before write, iclass 6, count 2 2006.201.10:51:49.01#ibcon#enter sib2, iclass 6, count 2 2006.201.10:51:49.01#ibcon#flushed, iclass 6, count 2 2006.201.10:51:49.01#ibcon#about to write, iclass 6, count 2 2006.201.10:51:49.01#ibcon#wrote, iclass 6, count 2 2006.201.10:51:49.01#ibcon#about to read 3, iclass 6, count 2 2006.201.10:51:49.04#ibcon#read 3, iclass 6, count 2 2006.201.10:51:49.04#ibcon#about to read 4, iclass 6, count 2 2006.201.10:51:49.04#ibcon#read 4, iclass 6, count 2 2006.201.10:51:49.04#ibcon#about to read 5, iclass 6, count 2 2006.201.10:51:49.04#ibcon#read 5, iclass 6, count 2 2006.201.10:51:49.04#ibcon#about to read 6, iclass 6, count 2 2006.201.10:51:49.04#ibcon#read 6, iclass 6, count 2 2006.201.10:51:49.04#ibcon#end of sib2, iclass 6, count 2 2006.201.10:51:49.04#ibcon#*after write, iclass 6, count 2 2006.201.10:51:49.04#ibcon#*before return 0, iclass 6, count 2 2006.201.10:51:49.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:49.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:49.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.10:51:49.04#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:49.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:49.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:49.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:49.16#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:51:49.16#ibcon#first serial, iclass 6, count 0 2006.201.10:51:49.16#ibcon#enter sib2, iclass 6, count 0 2006.201.10:51:49.16#ibcon#flushed, iclass 6, count 0 2006.201.10:51:49.16#ibcon#about to write, iclass 6, count 0 2006.201.10:51:49.16#ibcon#wrote, iclass 6, count 0 2006.201.10:51:49.16#ibcon#about to read 3, iclass 6, count 0 2006.201.10:51:49.18#ibcon#read 3, iclass 6, count 0 2006.201.10:51:49.18#ibcon#about to read 4, iclass 6, count 0 2006.201.10:51:49.18#ibcon#read 4, iclass 6, count 0 2006.201.10:51:49.18#ibcon#about to read 5, iclass 6, count 0 2006.201.10:51:49.18#ibcon#read 5, iclass 6, count 0 2006.201.10:51:49.18#ibcon#about to read 6, iclass 6, count 0 2006.201.10:51:49.18#ibcon#read 6, iclass 6, count 0 2006.201.10:51:49.18#ibcon#end of sib2, iclass 6, count 0 2006.201.10:51:49.18#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:51:49.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:51:49.18#ibcon#[25=USB\r\n] 2006.201.10:51:49.18#ibcon#*before write, iclass 6, count 0 2006.201.10:51:49.18#ibcon#enter sib2, iclass 6, count 0 2006.201.10:51:49.18#ibcon#flushed, iclass 6, count 0 2006.201.10:51:49.18#ibcon#about to write, iclass 6, count 0 2006.201.10:51:49.18#ibcon#wrote, iclass 6, count 0 2006.201.10:51:49.18#ibcon#about to read 3, iclass 6, count 0 2006.201.10:51:49.21#ibcon#read 3, iclass 6, count 0 2006.201.10:51:49.21#ibcon#about to read 4, iclass 6, count 0 2006.201.10:51:49.21#ibcon#read 4, iclass 6, count 0 2006.201.10:51:49.21#ibcon#about to read 5, iclass 6, count 0 2006.201.10:51:49.21#ibcon#read 5, iclass 6, count 0 2006.201.10:51:49.21#ibcon#about to read 6, iclass 6, count 0 2006.201.10:51:49.21#ibcon#read 6, iclass 6, count 0 2006.201.10:51:49.21#ibcon#end of sib2, iclass 6, count 0 2006.201.10:51:49.21#ibcon#*after write, iclass 6, count 0 2006.201.10:51:49.21#ibcon#*before return 0, iclass 6, count 0 2006.201.10:51:49.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:49.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:49.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:51:49.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:51:49.21$vck44/valo=5,734.99 2006.201.10:51:49.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.10:51:49.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.10:51:49.21#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:49.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:49.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:49.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:49.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:51:49.21#ibcon#first serial, iclass 10, count 0 2006.201.10:51:49.21#ibcon#enter sib2, iclass 10, count 0 2006.201.10:51:49.21#ibcon#flushed, iclass 10, count 0 2006.201.10:51:49.21#ibcon#about to write, iclass 10, count 0 2006.201.10:51:49.21#ibcon#wrote, iclass 10, count 0 2006.201.10:51:49.21#ibcon#about to read 3, iclass 10, count 0 2006.201.10:51:49.23#ibcon#read 3, iclass 10, count 0 2006.201.10:51:49.23#ibcon#about to read 4, iclass 10, count 0 2006.201.10:51:49.23#ibcon#read 4, iclass 10, count 0 2006.201.10:51:49.23#ibcon#about to read 5, iclass 10, count 0 2006.201.10:51:49.23#ibcon#read 5, iclass 10, count 0 2006.201.10:51:49.23#ibcon#about to read 6, iclass 10, count 0 2006.201.10:51:49.23#ibcon#read 6, iclass 10, count 0 2006.201.10:51:49.23#ibcon#end of sib2, iclass 10, count 0 2006.201.10:51:49.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:51:49.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:51:49.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.10:51:49.23#ibcon#*before write, iclass 10, count 0 2006.201.10:51:49.23#ibcon#enter sib2, iclass 10, count 0 2006.201.10:51:49.23#ibcon#flushed, iclass 10, count 0 2006.201.10:51:49.23#ibcon#about to write, iclass 10, count 0 2006.201.10:51:49.23#ibcon#wrote, iclass 10, count 0 2006.201.10:51:49.23#ibcon#about to read 3, iclass 10, count 0 2006.201.10:51:49.27#ibcon#read 3, iclass 10, count 0 2006.201.10:51:49.27#ibcon#about to read 4, iclass 10, count 0 2006.201.10:51:49.27#ibcon#read 4, iclass 10, count 0 2006.201.10:51:49.27#ibcon#about to read 5, iclass 10, count 0 2006.201.10:51:49.27#ibcon#read 5, iclass 10, count 0 2006.201.10:51:49.27#ibcon#about to read 6, iclass 10, count 0 2006.201.10:51:49.27#ibcon#read 6, iclass 10, count 0 2006.201.10:51:49.27#ibcon#end of sib2, iclass 10, count 0 2006.201.10:51:49.27#ibcon#*after write, iclass 10, count 0 2006.201.10:51:49.27#ibcon#*before return 0, iclass 10, count 0 2006.201.10:51:49.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:49.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:49.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:51:49.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:51:49.27$vck44/va=5,4 2006.201.10:51:49.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.10:51:49.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.10:51:49.27#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:49.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:49.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:49.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:49.33#ibcon#enter wrdev, iclass 12, count 2 2006.201.10:51:49.33#ibcon#first serial, iclass 12, count 2 2006.201.10:51:49.33#ibcon#enter sib2, iclass 12, count 2 2006.201.10:51:49.33#ibcon#flushed, iclass 12, count 2 2006.201.10:51:49.33#ibcon#about to write, iclass 12, count 2 2006.201.10:51:49.33#ibcon#wrote, iclass 12, count 2 2006.201.10:51:49.33#ibcon#about to read 3, iclass 12, count 2 2006.201.10:51:49.35#ibcon#read 3, iclass 12, count 2 2006.201.10:51:49.35#ibcon#about to read 4, iclass 12, count 2 2006.201.10:51:49.35#ibcon#read 4, iclass 12, count 2 2006.201.10:51:49.35#ibcon#about to read 5, iclass 12, count 2 2006.201.10:51:49.35#ibcon#read 5, iclass 12, count 2 2006.201.10:51:49.35#ibcon#about to read 6, iclass 12, count 2 2006.201.10:51:49.35#ibcon#read 6, iclass 12, count 2 2006.201.10:51:49.35#ibcon#end of sib2, iclass 12, count 2 2006.201.10:51:49.35#ibcon#*mode == 0, iclass 12, count 2 2006.201.10:51:49.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.10:51:49.35#ibcon#[25=AT05-04\r\n] 2006.201.10:51:49.35#ibcon#*before write, iclass 12, count 2 2006.201.10:51:49.35#ibcon#enter sib2, iclass 12, count 2 2006.201.10:51:49.35#ibcon#flushed, iclass 12, count 2 2006.201.10:51:49.35#ibcon#about to write, iclass 12, count 2 2006.201.10:51:49.35#ibcon#wrote, iclass 12, count 2 2006.201.10:51:49.35#ibcon#about to read 3, iclass 12, count 2 2006.201.10:51:49.38#ibcon#read 3, iclass 12, count 2 2006.201.10:51:49.38#ibcon#about to read 4, iclass 12, count 2 2006.201.10:51:49.38#ibcon#read 4, iclass 12, count 2 2006.201.10:51:49.38#ibcon#about to read 5, iclass 12, count 2 2006.201.10:51:49.38#ibcon#read 5, iclass 12, count 2 2006.201.10:51:49.38#ibcon#about to read 6, iclass 12, count 2 2006.201.10:51:49.38#ibcon#read 6, iclass 12, count 2 2006.201.10:51:49.38#ibcon#end of sib2, iclass 12, count 2 2006.201.10:51:49.38#ibcon#*after write, iclass 12, count 2 2006.201.10:51:49.38#ibcon#*before return 0, iclass 12, count 2 2006.201.10:51:49.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:49.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:49.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.10:51:49.38#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:49.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:49.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:49.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:49.50#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:51:49.50#ibcon#first serial, iclass 12, count 0 2006.201.10:51:49.50#ibcon#enter sib2, iclass 12, count 0 2006.201.10:51:49.50#ibcon#flushed, iclass 12, count 0 2006.201.10:51:49.50#ibcon#about to write, iclass 12, count 0 2006.201.10:51:49.50#ibcon#wrote, iclass 12, count 0 2006.201.10:51:49.50#ibcon#about to read 3, iclass 12, count 0 2006.201.10:51:49.52#ibcon#read 3, iclass 12, count 0 2006.201.10:51:49.52#ibcon#about to read 4, iclass 12, count 0 2006.201.10:51:49.52#ibcon#read 4, iclass 12, count 0 2006.201.10:51:49.52#ibcon#about to read 5, iclass 12, count 0 2006.201.10:51:49.52#ibcon#read 5, iclass 12, count 0 2006.201.10:51:49.52#ibcon#about to read 6, iclass 12, count 0 2006.201.10:51:49.52#ibcon#read 6, iclass 12, count 0 2006.201.10:51:49.52#ibcon#end of sib2, iclass 12, count 0 2006.201.10:51:49.52#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:51:49.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:51:49.52#ibcon#[25=USB\r\n] 2006.201.10:51:49.52#ibcon#*before write, iclass 12, count 0 2006.201.10:51:49.52#ibcon#enter sib2, iclass 12, count 0 2006.201.10:51:49.52#ibcon#flushed, iclass 12, count 0 2006.201.10:51:49.52#ibcon#about to write, iclass 12, count 0 2006.201.10:51:49.52#ibcon#wrote, iclass 12, count 0 2006.201.10:51:49.52#ibcon#about to read 3, iclass 12, count 0 2006.201.10:51:49.55#ibcon#read 3, iclass 12, count 0 2006.201.10:51:49.55#ibcon#about to read 4, iclass 12, count 0 2006.201.10:51:49.55#ibcon#read 4, iclass 12, count 0 2006.201.10:51:49.55#ibcon#about to read 5, iclass 12, count 0 2006.201.10:51:49.55#ibcon#read 5, iclass 12, count 0 2006.201.10:51:49.55#ibcon#about to read 6, iclass 12, count 0 2006.201.10:51:49.55#ibcon#read 6, iclass 12, count 0 2006.201.10:51:49.55#ibcon#end of sib2, iclass 12, count 0 2006.201.10:51:49.55#ibcon#*after write, iclass 12, count 0 2006.201.10:51:49.55#ibcon#*before return 0, iclass 12, count 0 2006.201.10:51:49.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:49.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:49.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:51:49.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:51:49.55$vck44/valo=6,814.99 2006.201.10:51:49.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.10:51:49.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.10:51:49.55#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:49.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:49.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:49.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:49.55#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:51:49.55#ibcon#first serial, iclass 14, count 0 2006.201.10:51:49.55#ibcon#enter sib2, iclass 14, count 0 2006.201.10:51:49.55#ibcon#flushed, iclass 14, count 0 2006.201.10:51:49.55#ibcon#about to write, iclass 14, count 0 2006.201.10:51:49.55#ibcon#wrote, iclass 14, count 0 2006.201.10:51:49.55#ibcon#about to read 3, iclass 14, count 0 2006.201.10:51:49.57#ibcon#read 3, iclass 14, count 0 2006.201.10:51:49.57#ibcon#about to read 4, iclass 14, count 0 2006.201.10:51:49.57#ibcon#read 4, iclass 14, count 0 2006.201.10:51:49.57#ibcon#about to read 5, iclass 14, count 0 2006.201.10:51:49.57#ibcon#read 5, iclass 14, count 0 2006.201.10:51:49.57#ibcon#about to read 6, iclass 14, count 0 2006.201.10:51:49.57#ibcon#read 6, iclass 14, count 0 2006.201.10:51:49.57#ibcon#end of sib2, iclass 14, count 0 2006.201.10:51:49.57#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:51:49.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:51:49.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.10:51:49.57#ibcon#*before write, iclass 14, count 0 2006.201.10:51:49.57#ibcon#enter sib2, iclass 14, count 0 2006.201.10:51:49.57#ibcon#flushed, iclass 14, count 0 2006.201.10:51:49.57#ibcon#about to write, iclass 14, count 0 2006.201.10:51:49.57#ibcon#wrote, iclass 14, count 0 2006.201.10:51:49.57#ibcon#about to read 3, iclass 14, count 0 2006.201.10:51:49.62#ibcon#read 3, iclass 14, count 0 2006.201.10:51:49.62#ibcon#about to read 4, iclass 14, count 0 2006.201.10:51:49.62#ibcon#read 4, iclass 14, count 0 2006.201.10:51:49.62#ibcon#about to read 5, iclass 14, count 0 2006.201.10:51:49.62#ibcon#read 5, iclass 14, count 0 2006.201.10:51:49.62#ibcon#about to read 6, iclass 14, count 0 2006.201.10:51:49.62#ibcon#read 6, iclass 14, count 0 2006.201.10:51:49.62#ibcon#end of sib2, iclass 14, count 0 2006.201.10:51:49.62#ibcon#*after write, iclass 14, count 0 2006.201.10:51:49.62#ibcon#*before return 0, iclass 14, count 0 2006.201.10:51:49.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:49.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:49.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:51:49.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:51:49.62$vck44/va=6,5 2006.201.10:51:49.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.10:51:49.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.10:51:49.62#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:49.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:49.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:49.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:49.67#ibcon#enter wrdev, iclass 16, count 2 2006.201.10:51:49.67#ibcon#first serial, iclass 16, count 2 2006.201.10:51:49.67#ibcon#enter sib2, iclass 16, count 2 2006.201.10:51:49.67#ibcon#flushed, iclass 16, count 2 2006.201.10:51:49.67#ibcon#about to write, iclass 16, count 2 2006.201.10:51:49.67#ibcon#wrote, iclass 16, count 2 2006.201.10:51:49.67#ibcon#about to read 3, iclass 16, count 2 2006.201.10:51:49.69#ibcon#read 3, iclass 16, count 2 2006.201.10:51:49.69#ibcon#about to read 4, iclass 16, count 2 2006.201.10:51:49.69#ibcon#read 4, iclass 16, count 2 2006.201.10:51:49.69#ibcon#about to read 5, iclass 16, count 2 2006.201.10:51:49.69#ibcon#read 5, iclass 16, count 2 2006.201.10:51:49.69#ibcon#about to read 6, iclass 16, count 2 2006.201.10:51:49.69#ibcon#read 6, iclass 16, count 2 2006.201.10:51:49.69#ibcon#end of sib2, iclass 16, count 2 2006.201.10:51:49.69#ibcon#*mode == 0, iclass 16, count 2 2006.201.10:51:49.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.10:51:49.69#ibcon#[25=AT06-05\r\n] 2006.201.10:51:49.69#ibcon#*before write, iclass 16, count 2 2006.201.10:51:49.69#ibcon#enter sib2, iclass 16, count 2 2006.201.10:51:49.69#ibcon#flushed, iclass 16, count 2 2006.201.10:51:49.69#ibcon#about to write, iclass 16, count 2 2006.201.10:51:49.69#ibcon#wrote, iclass 16, count 2 2006.201.10:51:49.69#ibcon#about to read 3, iclass 16, count 2 2006.201.10:51:49.72#ibcon#read 3, iclass 16, count 2 2006.201.10:51:49.72#ibcon#about to read 4, iclass 16, count 2 2006.201.10:51:49.72#ibcon#read 4, iclass 16, count 2 2006.201.10:51:49.72#ibcon#about to read 5, iclass 16, count 2 2006.201.10:51:49.72#ibcon#read 5, iclass 16, count 2 2006.201.10:51:49.72#ibcon#about to read 6, iclass 16, count 2 2006.201.10:51:49.72#ibcon#read 6, iclass 16, count 2 2006.201.10:51:49.72#ibcon#end of sib2, iclass 16, count 2 2006.201.10:51:49.72#ibcon#*after write, iclass 16, count 2 2006.201.10:51:49.72#ibcon#*before return 0, iclass 16, count 2 2006.201.10:51:49.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:49.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:49.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.10:51:49.72#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:49.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:49.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:49.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:49.84#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:51:49.84#ibcon#first serial, iclass 16, count 0 2006.201.10:51:49.84#ibcon#enter sib2, iclass 16, count 0 2006.201.10:51:49.84#ibcon#flushed, iclass 16, count 0 2006.201.10:51:49.84#ibcon#about to write, iclass 16, count 0 2006.201.10:51:49.84#ibcon#wrote, iclass 16, count 0 2006.201.10:51:49.84#ibcon#about to read 3, iclass 16, count 0 2006.201.10:51:49.86#ibcon#read 3, iclass 16, count 0 2006.201.10:51:49.86#ibcon#about to read 4, iclass 16, count 0 2006.201.10:51:49.86#ibcon#read 4, iclass 16, count 0 2006.201.10:51:49.86#ibcon#about to read 5, iclass 16, count 0 2006.201.10:51:49.86#ibcon#read 5, iclass 16, count 0 2006.201.10:51:49.86#ibcon#about to read 6, iclass 16, count 0 2006.201.10:51:49.86#ibcon#read 6, iclass 16, count 0 2006.201.10:51:49.86#ibcon#end of sib2, iclass 16, count 0 2006.201.10:51:49.86#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:51:49.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:51:49.86#ibcon#[25=USB\r\n] 2006.201.10:51:49.86#ibcon#*before write, iclass 16, count 0 2006.201.10:51:49.86#ibcon#enter sib2, iclass 16, count 0 2006.201.10:51:49.86#ibcon#flushed, iclass 16, count 0 2006.201.10:51:49.86#ibcon#about to write, iclass 16, count 0 2006.201.10:51:49.86#ibcon#wrote, iclass 16, count 0 2006.201.10:51:49.86#ibcon#about to read 3, iclass 16, count 0 2006.201.10:51:49.89#ibcon#read 3, iclass 16, count 0 2006.201.10:51:49.89#ibcon#about to read 4, iclass 16, count 0 2006.201.10:51:49.89#ibcon#read 4, iclass 16, count 0 2006.201.10:51:49.89#ibcon#about to read 5, iclass 16, count 0 2006.201.10:51:49.89#ibcon#read 5, iclass 16, count 0 2006.201.10:51:49.89#ibcon#about to read 6, iclass 16, count 0 2006.201.10:51:49.89#ibcon#read 6, iclass 16, count 0 2006.201.10:51:49.89#ibcon#end of sib2, iclass 16, count 0 2006.201.10:51:49.89#ibcon#*after write, iclass 16, count 0 2006.201.10:51:49.89#ibcon#*before return 0, iclass 16, count 0 2006.201.10:51:49.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:49.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:49.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:51:49.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:51:49.89$vck44/valo=7,864.99 2006.201.10:51:49.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.10:51:49.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.10:51:49.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:49.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:49.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:49.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:49.89#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:51:49.89#ibcon#first serial, iclass 18, count 0 2006.201.10:51:49.89#ibcon#enter sib2, iclass 18, count 0 2006.201.10:51:49.89#ibcon#flushed, iclass 18, count 0 2006.201.10:51:49.89#ibcon#about to write, iclass 18, count 0 2006.201.10:51:49.89#ibcon#wrote, iclass 18, count 0 2006.201.10:51:49.89#ibcon#about to read 3, iclass 18, count 0 2006.201.10:51:49.91#ibcon#read 3, iclass 18, count 0 2006.201.10:51:49.91#ibcon#about to read 4, iclass 18, count 0 2006.201.10:51:49.91#ibcon#read 4, iclass 18, count 0 2006.201.10:51:49.91#ibcon#about to read 5, iclass 18, count 0 2006.201.10:51:49.91#ibcon#read 5, iclass 18, count 0 2006.201.10:51:49.91#ibcon#about to read 6, iclass 18, count 0 2006.201.10:51:49.91#ibcon#read 6, iclass 18, count 0 2006.201.10:51:49.91#ibcon#end of sib2, iclass 18, count 0 2006.201.10:51:49.91#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:51:49.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:51:49.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.10:51:49.91#ibcon#*before write, iclass 18, count 0 2006.201.10:51:49.91#ibcon#enter sib2, iclass 18, count 0 2006.201.10:51:49.91#ibcon#flushed, iclass 18, count 0 2006.201.10:51:49.91#ibcon#about to write, iclass 18, count 0 2006.201.10:51:49.91#ibcon#wrote, iclass 18, count 0 2006.201.10:51:49.91#ibcon#about to read 3, iclass 18, count 0 2006.201.10:51:49.95#ibcon#read 3, iclass 18, count 0 2006.201.10:51:49.95#ibcon#about to read 4, iclass 18, count 0 2006.201.10:51:49.95#ibcon#read 4, iclass 18, count 0 2006.201.10:51:49.95#ibcon#about to read 5, iclass 18, count 0 2006.201.10:51:49.95#ibcon#read 5, iclass 18, count 0 2006.201.10:51:49.95#ibcon#about to read 6, iclass 18, count 0 2006.201.10:51:49.95#ibcon#read 6, iclass 18, count 0 2006.201.10:51:49.95#ibcon#end of sib2, iclass 18, count 0 2006.201.10:51:49.95#ibcon#*after write, iclass 18, count 0 2006.201.10:51:49.95#ibcon#*before return 0, iclass 18, count 0 2006.201.10:51:49.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:49.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:49.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:51:49.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:51:49.95$vck44/va=7,5 2006.201.10:51:49.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.10:51:49.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.10:51:49.95#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:49.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:50.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:50.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:50.01#ibcon#enter wrdev, iclass 20, count 2 2006.201.10:51:50.01#ibcon#first serial, iclass 20, count 2 2006.201.10:51:50.01#ibcon#enter sib2, iclass 20, count 2 2006.201.10:51:50.01#ibcon#flushed, iclass 20, count 2 2006.201.10:51:50.01#ibcon#about to write, iclass 20, count 2 2006.201.10:51:50.01#ibcon#wrote, iclass 20, count 2 2006.201.10:51:50.01#ibcon#about to read 3, iclass 20, count 2 2006.201.10:51:50.03#ibcon#read 3, iclass 20, count 2 2006.201.10:51:50.03#ibcon#about to read 4, iclass 20, count 2 2006.201.10:51:50.03#ibcon#read 4, iclass 20, count 2 2006.201.10:51:50.03#ibcon#about to read 5, iclass 20, count 2 2006.201.10:51:50.03#ibcon#read 5, iclass 20, count 2 2006.201.10:51:50.03#ibcon#about to read 6, iclass 20, count 2 2006.201.10:51:50.03#ibcon#read 6, iclass 20, count 2 2006.201.10:51:50.03#ibcon#end of sib2, iclass 20, count 2 2006.201.10:51:50.03#ibcon#*mode == 0, iclass 20, count 2 2006.201.10:51:50.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.10:51:50.03#ibcon#[25=AT07-05\r\n] 2006.201.10:51:50.03#ibcon#*before write, iclass 20, count 2 2006.201.10:51:50.03#ibcon#enter sib2, iclass 20, count 2 2006.201.10:51:50.03#ibcon#flushed, iclass 20, count 2 2006.201.10:51:50.03#ibcon#about to write, iclass 20, count 2 2006.201.10:51:50.03#ibcon#wrote, iclass 20, count 2 2006.201.10:51:50.03#ibcon#about to read 3, iclass 20, count 2 2006.201.10:51:50.06#ibcon#read 3, iclass 20, count 2 2006.201.10:51:50.06#ibcon#about to read 4, iclass 20, count 2 2006.201.10:51:50.06#ibcon#read 4, iclass 20, count 2 2006.201.10:51:50.06#ibcon#about to read 5, iclass 20, count 2 2006.201.10:51:50.06#ibcon#read 5, iclass 20, count 2 2006.201.10:51:50.06#ibcon#about to read 6, iclass 20, count 2 2006.201.10:51:50.06#ibcon#read 6, iclass 20, count 2 2006.201.10:51:50.06#ibcon#end of sib2, iclass 20, count 2 2006.201.10:51:50.06#ibcon#*after write, iclass 20, count 2 2006.201.10:51:50.06#ibcon#*before return 0, iclass 20, count 2 2006.201.10:51:50.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:50.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:50.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.10:51:50.06#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:50.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:50.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:50.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:50.18#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:51:50.18#ibcon#first serial, iclass 20, count 0 2006.201.10:51:50.18#ibcon#enter sib2, iclass 20, count 0 2006.201.10:51:50.18#ibcon#flushed, iclass 20, count 0 2006.201.10:51:50.18#ibcon#about to write, iclass 20, count 0 2006.201.10:51:50.18#ibcon#wrote, iclass 20, count 0 2006.201.10:51:50.18#ibcon#about to read 3, iclass 20, count 0 2006.201.10:51:50.21#ibcon#read 3, iclass 20, count 0 2006.201.10:51:50.21#ibcon#about to read 4, iclass 20, count 0 2006.201.10:51:50.21#ibcon#read 4, iclass 20, count 0 2006.201.10:51:50.21#ibcon#about to read 5, iclass 20, count 0 2006.201.10:51:50.21#ibcon#read 5, iclass 20, count 0 2006.201.10:51:50.21#ibcon#about to read 6, iclass 20, count 0 2006.201.10:51:50.21#ibcon#read 6, iclass 20, count 0 2006.201.10:51:50.21#ibcon#end of sib2, iclass 20, count 0 2006.201.10:51:50.21#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:51:50.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:51:50.21#ibcon#[25=USB\r\n] 2006.201.10:51:50.21#ibcon#*before write, iclass 20, count 0 2006.201.10:51:50.21#ibcon#enter sib2, iclass 20, count 0 2006.201.10:51:50.21#ibcon#flushed, iclass 20, count 0 2006.201.10:51:50.21#ibcon#about to write, iclass 20, count 0 2006.201.10:51:50.21#ibcon#wrote, iclass 20, count 0 2006.201.10:51:50.21#ibcon#about to read 3, iclass 20, count 0 2006.201.10:51:50.24#ibcon#read 3, iclass 20, count 0 2006.201.10:51:50.24#ibcon#about to read 4, iclass 20, count 0 2006.201.10:51:50.24#ibcon#read 4, iclass 20, count 0 2006.201.10:51:50.24#ibcon#about to read 5, iclass 20, count 0 2006.201.10:51:50.24#ibcon#read 5, iclass 20, count 0 2006.201.10:51:50.24#ibcon#about to read 6, iclass 20, count 0 2006.201.10:51:50.24#ibcon#read 6, iclass 20, count 0 2006.201.10:51:50.24#ibcon#end of sib2, iclass 20, count 0 2006.201.10:51:50.24#ibcon#*after write, iclass 20, count 0 2006.201.10:51:50.24#ibcon#*before return 0, iclass 20, count 0 2006.201.10:51:50.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:50.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:50.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:51:50.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:51:50.24$vck44/valo=8,884.99 2006.201.10:51:50.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.10:51:50.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.10:51:50.24#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:50.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:51:50.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:51:50.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:51:50.24#ibcon#enter wrdev, iclass 22, count 0 2006.201.10:51:50.24#ibcon#first serial, iclass 22, count 0 2006.201.10:51:50.24#ibcon#enter sib2, iclass 22, count 0 2006.201.10:51:50.24#ibcon#flushed, iclass 22, count 0 2006.201.10:51:50.24#ibcon#about to write, iclass 22, count 0 2006.201.10:51:50.24#ibcon#wrote, iclass 22, count 0 2006.201.10:51:50.24#ibcon#about to read 3, iclass 22, count 0 2006.201.10:51:50.26#ibcon#read 3, iclass 22, count 0 2006.201.10:51:50.26#ibcon#about to read 4, iclass 22, count 0 2006.201.10:51:50.26#ibcon#read 4, iclass 22, count 0 2006.201.10:51:50.26#ibcon#about to read 5, iclass 22, count 0 2006.201.10:51:50.26#ibcon#read 5, iclass 22, count 0 2006.201.10:51:50.26#ibcon#about to read 6, iclass 22, count 0 2006.201.10:51:50.26#ibcon#read 6, iclass 22, count 0 2006.201.10:51:50.26#ibcon#end of sib2, iclass 22, count 0 2006.201.10:51:50.26#ibcon#*mode == 0, iclass 22, count 0 2006.201.10:51:50.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.10:51:50.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.10:51:50.26#ibcon#*before write, iclass 22, count 0 2006.201.10:51:50.26#ibcon#enter sib2, iclass 22, count 0 2006.201.10:51:50.26#ibcon#flushed, iclass 22, count 0 2006.201.10:51:50.26#ibcon#about to write, iclass 22, count 0 2006.201.10:51:50.26#ibcon#wrote, iclass 22, count 0 2006.201.10:51:50.26#ibcon#about to read 3, iclass 22, count 0 2006.201.10:51:50.30#ibcon#read 3, iclass 22, count 0 2006.201.10:51:50.30#ibcon#about to read 4, iclass 22, count 0 2006.201.10:51:50.30#ibcon#read 4, iclass 22, count 0 2006.201.10:51:50.30#ibcon#about to read 5, iclass 22, count 0 2006.201.10:51:50.30#ibcon#read 5, iclass 22, count 0 2006.201.10:51:50.30#ibcon#about to read 6, iclass 22, count 0 2006.201.10:51:50.30#ibcon#read 6, iclass 22, count 0 2006.201.10:51:50.30#ibcon#end of sib2, iclass 22, count 0 2006.201.10:51:50.30#ibcon#*after write, iclass 22, count 0 2006.201.10:51:50.30#ibcon#*before return 0, iclass 22, count 0 2006.201.10:51:50.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:51:50.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.10:51:50.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.10:51:50.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.10:51:50.30$vck44/va=8,4 2006.201.10:51:50.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.10:51:50.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.10:51:50.30#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:50.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:51:50.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:51:50.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:51:50.36#ibcon#enter wrdev, iclass 24, count 2 2006.201.10:51:50.36#ibcon#first serial, iclass 24, count 2 2006.201.10:51:50.36#ibcon#enter sib2, iclass 24, count 2 2006.201.10:51:50.36#ibcon#flushed, iclass 24, count 2 2006.201.10:51:50.36#ibcon#about to write, iclass 24, count 2 2006.201.10:51:50.36#ibcon#wrote, iclass 24, count 2 2006.201.10:51:50.36#ibcon#about to read 3, iclass 24, count 2 2006.201.10:51:50.38#ibcon#read 3, iclass 24, count 2 2006.201.10:51:50.38#ibcon#about to read 4, iclass 24, count 2 2006.201.10:51:50.38#ibcon#read 4, iclass 24, count 2 2006.201.10:51:50.38#ibcon#about to read 5, iclass 24, count 2 2006.201.10:51:50.38#ibcon#read 5, iclass 24, count 2 2006.201.10:51:50.38#ibcon#about to read 6, iclass 24, count 2 2006.201.10:51:50.38#ibcon#read 6, iclass 24, count 2 2006.201.10:51:50.38#ibcon#end of sib2, iclass 24, count 2 2006.201.10:51:50.38#ibcon#*mode == 0, iclass 24, count 2 2006.201.10:51:50.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.10:51:50.38#ibcon#[25=AT08-04\r\n] 2006.201.10:51:50.38#ibcon#*before write, iclass 24, count 2 2006.201.10:51:50.38#ibcon#enter sib2, iclass 24, count 2 2006.201.10:51:50.38#ibcon#flushed, iclass 24, count 2 2006.201.10:51:50.38#ibcon#about to write, iclass 24, count 2 2006.201.10:51:50.38#ibcon#wrote, iclass 24, count 2 2006.201.10:51:50.38#ibcon#about to read 3, iclass 24, count 2 2006.201.10:51:50.42#ibcon#read 3, iclass 24, count 2 2006.201.10:51:50.42#ibcon#about to read 4, iclass 24, count 2 2006.201.10:51:50.42#ibcon#read 4, iclass 24, count 2 2006.201.10:51:50.42#ibcon#about to read 5, iclass 24, count 2 2006.201.10:51:50.42#ibcon#read 5, iclass 24, count 2 2006.201.10:51:50.42#ibcon#about to read 6, iclass 24, count 2 2006.201.10:51:50.42#ibcon#read 6, iclass 24, count 2 2006.201.10:51:50.42#ibcon#end of sib2, iclass 24, count 2 2006.201.10:51:50.42#ibcon#*after write, iclass 24, count 2 2006.201.10:51:50.42#ibcon#*before return 0, iclass 24, count 2 2006.201.10:51:50.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:51:50.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.10:51:50.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.10:51:50.42#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:50.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:51:50.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:51:50.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:51:50.54#ibcon#enter wrdev, iclass 24, count 0 2006.201.10:51:50.54#ibcon#first serial, iclass 24, count 0 2006.201.10:51:50.54#ibcon#enter sib2, iclass 24, count 0 2006.201.10:51:50.54#ibcon#flushed, iclass 24, count 0 2006.201.10:51:50.54#ibcon#about to write, iclass 24, count 0 2006.201.10:51:50.54#ibcon#wrote, iclass 24, count 0 2006.201.10:51:50.54#ibcon#about to read 3, iclass 24, count 0 2006.201.10:51:50.56#ibcon#read 3, iclass 24, count 0 2006.201.10:51:50.56#ibcon#about to read 4, iclass 24, count 0 2006.201.10:51:50.56#ibcon#read 4, iclass 24, count 0 2006.201.10:51:50.56#ibcon#about to read 5, iclass 24, count 0 2006.201.10:51:50.56#ibcon#read 5, iclass 24, count 0 2006.201.10:51:50.56#ibcon#about to read 6, iclass 24, count 0 2006.201.10:51:50.56#ibcon#read 6, iclass 24, count 0 2006.201.10:51:50.56#ibcon#end of sib2, iclass 24, count 0 2006.201.10:51:50.56#ibcon#*mode == 0, iclass 24, count 0 2006.201.10:51:50.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.10:51:50.56#ibcon#[25=USB\r\n] 2006.201.10:51:50.56#ibcon#*before write, iclass 24, count 0 2006.201.10:51:50.56#ibcon#enter sib2, iclass 24, count 0 2006.201.10:51:50.56#ibcon#flushed, iclass 24, count 0 2006.201.10:51:50.56#ibcon#about to write, iclass 24, count 0 2006.201.10:51:50.56#ibcon#wrote, iclass 24, count 0 2006.201.10:51:50.56#ibcon#about to read 3, iclass 24, count 0 2006.201.10:51:50.59#ibcon#read 3, iclass 24, count 0 2006.201.10:51:50.59#ibcon#about to read 4, iclass 24, count 0 2006.201.10:51:50.59#ibcon#read 4, iclass 24, count 0 2006.201.10:51:50.59#ibcon#about to read 5, iclass 24, count 0 2006.201.10:51:50.59#ibcon#read 5, iclass 24, count 0 2006.201.10:51:50.59#ibcon#about to read 6, iclass 24, count 0 2006.201.10:51:50.59#ibcon#read 6, iclass 24, count 0 2006.201.10:51:50.59#ibcon#end of sib2, iclass 24, count 0 2006.201.10:51:50.59#ibcon#*after write, iclass 24, count 0 2006.201.10:51:50.59#ibcon#*before return 0, iclass 24, count 0 2006.201.10:51:50.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:51:50.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.10:51:50.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.10:51:50.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.10:51:50.59$vck44/vblo=1,629.99 2006.201.10:51:50.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.10:51:50.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.10:51:50.59#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:50.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:51:50.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:51:50.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:51:50.59#ibcon#enter wrdev, iclass 26, count 0 2006.201.10:51:50.59#ibcon#first serial, iclass 26, count 0 2006.201.10:51:50.59#ibcon#enter sib2, iclass 26, count 0 2006.201.10:51:50.59#ibcon#flushed, iclass 26, count 0 2006.201.10:51:50.59#ibcon#about to write, iclass 26, count 0 2006.201.10:51:50.59#ibcon#wrote, iclass 26, count 0 2006.201.10:51:50.59#ibcon#about to read 3, iclass 26, count 0 2006.201.10:51:50.61#ibcon#read 3, iclass 26, count 0 2006.201.10:51:50.61#ibcon#about to read 4, iclass 26, count 0 2006.201.10:51:50.61#ibcon#read 4, iclass 26, count 0 2006.201.10:51:50.61#ibcon#about to read 5, iclass 26, count 0 2006.201.10:51:50.61#ibcon#read 5, iclass 26, count 0 2006.201.10:51:50.61#ibcon#about to read 6, iclass 26, count 0 2006.201.10:51:50.61#ibcon#read 6, iclass 26, count 0 2006.201.10:51:50.61#ibcon#end of sib2, iclass 26, count 0 2006.201.10:51:50.61#ibcon#*mode == 0, iclass 26, count 0 2006.201.10:51:50.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.10:51:50.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.10:51:50.61#ibcon#*before write, iclass 26, count 0 2006.201.10:51:50.61#ibcon#enter sib2, iclass 26, count 0 2006.201.10:51:50.61#ibcon#flushed, iclass 26, count 0 2006.201.10:51:50.61#ibcon#about to write, iclass 26, count 0 2006.201.10:51:50.61#ibcon#wrote, iclass 26, count 0 2006.201.10:51:50.61#ibcon#about to read 3, iclass 26, count 0 2006.201.10:51:50.65#ibcon#read 3, iclass 26, count 0 2006.201.10:51:50.65#ibcon#about to read 4, iclass 26, count 0 2006.201.10:51:50.65#ibcon#read 4, iclass 26, count 0 2006.201.10:51:50.65#ibcon#about to read 5, iclass 26, count 0 2006.201.10:51:50.65#ibcon#read 5, iclass 26, count 0 2006.201.10:51:50.65#ibcon#about to read 6, iclass 26, count 0 2006.201.10:51:50.65#ibcon#read 6, iclass 26, count 0 2006.201.10:51:50.65#ibcon#end of sib2, iclass 26, count 0 2006.201.10:51:50.65#ibcon#*after write, iclass 26, count 0 2006.201.10:51:50.65#ibcon#*before return 0, iclass 26, count 0 2006.201.10:51:50.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:51:50.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.10:51:50.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.10:51:50.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.10:51:50.65$vck44/vb=1,4 2006.201.10:51:50.65#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.10:51:50.65#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.10:51:50.65#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:50.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:51:50.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:51:50.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:51:50.65#ibcon#enter wrdev, iclass 28, count 2 2006.201.10:51:50.65#ibcon#first serial, iclass 28, count 2 2006.201.10:51:50.65#ibcon#enter sib2, iclass 28, count 2 2006.201.10:51:50.65#ibcon#flushed, iclass 28, count 2 2006.201.10:51:50.65#ibcon#about to write, iclass 28, count 2 2006.201.10:51:50.65#ibcon#wrote, iclass 28, count 2 2006.201.10:51:50.65#ibcon#about to read 3, iclass 28, count 2 2006.201.10:51:50.67#ibcon#read 3, iclass 28, count 2 2006.201.10:51:50.67#ibcon#about to read 4, iclass 28, count 2 2006.201.10:51:50.67#ibcon#read 4, iclass 28, count 2 2006.201.10:51:50.67#ibcon#about to read 5, iclass 28, count 2 2006.201.10:51:50.67#ibcon#read 5, iclass 28, count 2 2006.201.10:51:50.67#ibcon#about to read 6, iclass 28, count 2 2006.201.10:51:50.67#ibcon#read 6, iclass 28, count 2 2006.201.10:51:50.67#ibcon#end of sib2, iclass 28, count 2 2006.201.10:51:50.67#ibcon#*mode == 0, iclass 28, count 2 2006.201.10:51:50.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.10:51:50.67#ibcon#[27=AT01-04\r\n] 2006.201.10:51:50.67#ibcon#*before write, iclass 28, count 2 2006.201.10:51:50.67#ibcon#enter sib2, iclass 28, count 2 2006.201.10:51:50.67#ibcon#flushed, iclass 28, count 2 2006.201.10:51:50.67#ibcon#about to write, iclass 28, count 2 2006.201.10:51:50.67#ibcon#wrote, iclass 28, count 2 2006.201.10:51:50.67#ibcon#about to read 3, iclass 28, count 2 2006.201.10:51:50.70#ibcon#read 3, iclass 28, count 2 2006.201.10:51:50.70#ibcon#about to read 4, iclass 28, count 2 2006.201.10:51:50.70#ibcon#read 4, iclass 28, count 2 2006.201.10:51:50.70#ibcon#about to read 5, iclass 28, count 2 2006.201.10:51:50.70#ibcon#read 5, iclass 28, count 2 2006.201.10:51:50.70#ibcon#about to read 6, iclass 28, count 2 2006.201.10:51:50.70#ibcon#read 6, iclass 28, count 2 2006.201.10:51:50.70#ibcon#end of sib2, iclass 28, count 2 2006.201.10:51:50.70#ibcon#*after write, iclass 28, count 2 2006.201.10:51:50.70#ibcon#*before return 0, iclass 28, count 2 2006.201.10:51:50.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:51:50.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.10:51:50.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.10:51:50.70#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:50.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:51:50.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:51:50.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:51:50.82#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:51:50.82#ibcon#first serial, iclass 28, count 0 2006.201.10:51:50.82#ibcon#enter sib2, iclass 28, count 0 2006.201.10:51:50.82#ibcon#flushed, iclass 28, count 0 2006.201.10:51:50.82#ibcon#about to write, iclass 28, count 0 2006.201.10:51:50.82#ibcon#wrote, iclass 28, count 0 2006.201.10:51:50.82#ibcon#about to read 3, iclass 28, count 0 2006.201.10:51:50.84#ibcon#read 3, iclass 28, count 0 2006.201.10:51:50.84#ibcon#about to read 4, iclass 28, count 0 2006.201.10:51:50.84#ibcon#read 4, iclass 28, count 0 2006.201.10:51:50.84#ibcon#about to read 5, iclass 28, count 0 2006.201.10:51:50.84#ibcon#read 5, iclass 28, count 0 2006.201.10:51:50.84#ibcon#about to read 6, iclass 28, count 0 2006.201.10:51:50.84#ibcon#read 6, iclass 28, count 0 2006.201.10:51:50.84#ibcon#end of sib2, iclass 28, count 0 2006.201.10:51:50.84#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:51:50.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:51:50.84#ibcon#[27=USB\r\n] 2006.201.10:51:50.84#ibcon#*before write, iclass 28, count 0 2006.201.10:51:50.84#ibcon#enter sib2, iclass 28, count 0 2006.201.10:51:50.84#ibcon#flushed, iclass 28, count 0 2006.201.10:51:50.84#ibcon#about to write, iclass 28, count 0 2006.201.10:51:50.84#ibcon#wrote, iclass 28, count 0 2006.201.10:51:50.84#ibcon#about to read 3, iclass 28, count 0 2006.201.10:51:50.87#ibcon#read 3, iclass 28, count 0 2006.201.10:51:50.87#ibcon#about to read 4, iclass 28, count 0 2006.201.10:51:50.87#ibcon#read 4, iclass 28, count 0 2006.201.10:51:50.87#ibcon#about to read 5, iclass 28, count 0 2006.201.10:51:50.87#ibcon#read 5, iclass 28, count 0 2006.201.10:51:50.87#ibcon#about to read 6, iclass 28, count 0 2006.201.10:51:50.87#ibcon#read 6, iclass 28, count 0 2006.201.10:51:50.87#ibcon#end of sib2, iclass 28, count 0 2006.201.10:51:50.87#ibcon#*after write, iclass 28, count 0 2006.201.10:51:50.87#ibcon#*before return 0, iclass 28, count 0 2006.201.10:51:50.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:51:50.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.10:51:50.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:51:50.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:51:50.87$vck44/vblo=2,634.99 2006.201.10:51:50.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.10:51:50.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.10:51:50.87#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:50.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:50.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:50.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:50.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.10:51:50.87#ibcon#first serial, iclass 30, count 0 2006.201.10:51:50.87#ibcon#enter sib2, iclass 30, count 0 2006.201.10:51:50.87#ibcon#flushed, iclass 30, count 0 2006.201.10:51:50.87#ibcon#about to write, iclass 30, count 0 2006.201.10:51:50.87#ibcon#wrote, iclass 30, count 0 2006.201.10:51:50.87#ibcon#about to read 3, iclass 30, count 0 2006.201.10:51:50.89#ibcon#read 3, iclass 30, count 0 2006.201.10:51:50.89#ibcon#about to read 4, iclass 30, count 0 2006.201.10:51:50.89#ibcon#read 4, iclass 30, count 0 2006.201.10:51:50.89#ibcon#about to read 5, iclass 30, count 0 2006.201.10:51:50.89#ibcon#read 5, iclass 30, count 0 2006.201.10:51:50.89#ibcon#about to read 6, iclass 30, count 0 2006.201.10:51:50.89#ibcon#read 6, iclass 30, count 0 2006.201.10:51:50.89#ibcon#end of sib2, iclass 30, count 0 2006.201.10:51:50.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.10:51:50.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.10:51:50.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.10:51:50.89#ibcon#*before write, iclass 30, count 0 2006.201.10:51:50.89#ibcon#enter sib2, iclass 30, count 0 2006.201.10:51:50.89#ibcon#flushed, iclass 30, count 0 2006.201.10:51:50.89#ibcon#about to write, iclass 30, count 0 2006.201.10:51:50.89#ibcon#wrote, iclass 30, count 0 2006.201.10:51:50.89#ibcon#about to read 3, iclass 30, count 0 2006.201.10:51:50.94#ibcon#read 3, iclass 30, count 0 2006.201.10:51:50.94#ibcon#about to read 4, iclass 30, count 0 2006.201.10:51:50.94#ibcon#read 4, iclass 30, count 0 2006.201.10:51:50.94#ibcon#about to read 5, iclass 30, count 0 2006.201.10:51:50.94#ibcon#read 5, iclass 30, count 0 2006.201.10:51:50.94#ibcon#about to read 6, iclass 30, count 0 2006.201.10:51:50.94#ibcon#read 6, iclass 30, count 0 2006.201.10:51:50.94#ibcon#end of sib2, iclass 30, count 0 2006.201.10:51:50.94#ibcon#*after write, iclass 30, count 0 2006.201.10:51:50.94#ibcon#*before return 0, iclass 30, count 0 2006.201.10:51:50.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:50.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.10:51:50.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.10:51:50.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.10:51:50.94$vck44/vb=2,5 2006.201.10:51:50.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.10:51:50.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.10:51:50.94#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:50.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:50.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:50.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:50.99#ibcon#enter wrdev, iclass 32, count 2 2006.201.10:51:50.99#ibcon#first serial, iclass 32, count 2 2006.201.10:51:50.99#ibcon#enter sib2, iclass 32, count 2 2006.201.10:51:50.99#ibcon#flushed, iclass 32, count 2 2006.201.10:51:50.99#ibcon#about to write, iclass 32, count 2 2006.201.10:51:50.99#ibcon#wrote, iclass 32, count 2 2006.201.10:51:50.99#ibcon#about to read 3, iclass 32, count 2 2006.201.10:51:51.01#ibcon#read 3, iclass 32, count 2 2006.201.10:51:51.01#ibcon#about to read 4, iclass 32, count 2 2006.201.10:51:51.01#ibcon#read 4, iclass 32, count 2 2006.201.10:51:51.01#ibcon#about to read 5, iclass 32, count 2 2006.201.10:51:51.01#ibcon#read 5, iclass 32, count 2 2006.201.10:51:51.01#ibcon#about to read 6, iclass 32, count 2 2006.201.10:51:51.01#ibcon#read 6, iclass 32, count 2 2006.201.10:51:51.01#ibcon#end of sib2, iclass 32, count 2 2006.201.10:51:51.01#ibcon#*mode == 0, iclass 32, count 2 2006.201.10:51:51.01#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.10:51:51.01#ibcon#[27=AT02-05\r\n] 2006.201.10:51:51.01#ibcon#*before write, iclass 32, count 2 2006.201.10:51:51.01#ibcon#enter sib2, iclass 32, count 2 2006.201.10:51:51.01#ibcon#flushed, iclass 32, count 2 2006.201.10:51:51.01#ibcon#about to write, iclass 32, count 2 2006.201.10:51:51.01#ibcon#wrote, iclass 32, count 2 2006.201.10:51:51.01#ibcon#about to read 3, iclass 32, count 2 2006.201.10:51:51.04#ibcon#read 3, iclass 32, count 2 2006.201.10:51:51.04#ibcon#about to read 4, iclass 32, count 2 2006.201.10:51:51.04#ibcon#read 4, iclass 32, count 2 2006.201.10:51:51.04#ibcon#about to read 5, iclass 32, count 2 2006.201.10:51:51.04#ibcon#read 5, iclass 32, count 2 2006.201.10:51:51.04#ibcon#about to read 6, iclass 32, count 2 2006.201.10:51:51.04#ibcon#read 6, iclass 32, count 2 2006.201.10:51:51.04#ibcon#end of sib2, iclass 32, count 2 2006.201.10:51:51.04#ibcon#*after write, iclass 32, count 2 2006.201.10:51:51.04#ibcon#*before return 0, iclass 32, count 2 2006.201.10:51:51.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:51.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.10:51:51.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.10:51:51.04#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:51.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:51.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:51.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:51.16#ibcon#enter wrdev, iclass 32, count 0 2006.201.10:51:51.16#ibcon#first serial, iclass 32, count 0 2006.201.10:51:51.16#ibcon#enter sib2, iclass 32, count 0 2006.201.10:51:51.16#ibcon#flushed, iclass 32, count 0 2006.201.10:51:51.16#ibcon#about to write, iclass 32, count 0 2006.201.10:51:51.16#ibcon#wrote, iclass 32, count 0 2006.201.10:51:51.16#ibcon#about to read 3, iclass 32, count 0 2006.201.10:51:51.18#ibcon#read 3, iclass 32, count 0 2006.201.10:51:51.18#ibcon#about to read 4, iclass 32, count 0 2006.201.10:51:51.18#ibcon#read 4, iclass 32, count 0 2006.201.10:51:51.18#ibcon#about to read 5, iclass 32, count 0 2006.201.10:51:51.18#ibcon#read 5, iclass 32, count 0 2006.201.10:51:51.18#ibcon#about to read 6, iclass 32, count 0 2006.201.10:51:51.18#ibcon#read 6, iclass 32, count 0 2006.201.10:51:51.18#ibcon#end of sib2, iclass 32, count 0 2006.201.10:51:51.18#ibcon#*mode == 0, iclass 32, count 0 2006.201.10:51:51.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.10:51:51.18#ibcon#[27=USB\r\n] 2006.201.10:51:51.18#ibcon#*before write, iclass 32, count 0 2006.201.10:51:51.18#ibcon#enter sib2, iclass 32, count 0 2006.201.10:51:51.18#ibcon#flushed, iclass 32, count 0 2006.201.10:51:51.18#ibcon#about to write, iclass 32, count 0 2006.201.10:51:51.18#ibcon#wrote, iclass 32, count 0 2006.201.10:51:51.18#ibcon#about to read 3, iclass 32, count 0 2006.201.10:51:51.21#ibcon#read 3, iclass 32, count 0 2006.201.10:51:51.21#ibcon#about to read 4, iclass 32, count 0 2006.201.10:51:51.21#ibcon#read 4, iclass 32, count 0 2006.201.10:51:51.21#ibcon#about to read 5, iclass 32, count 0 2006.201.10:51:51.21#ibcon#read 5, iclass 32, count 0 2006.201.10:51:51.21#ibcon#about to read 6, iclass 32, count 0 2006.201.10:51:51.21#ibcon#read 6, iclass 32, count 0 2006.201.10:51:51.21#ibcon#end of sib2, iclass 32, count 0 2006.201.10:51:51.21#ibcon#*after write, iclass 32, count 0 2006.201.10:51:51.21#ibcon#*before return 0, iclass 32, count 0 2006.201.10:51:51.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:51.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.10:51:51.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.10:51:51.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.10:51:51.21$vck44/vblo=3,649.99 2006.201.10:51:51.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.10:51:51.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.10:51:51.21#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:51.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:51.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:51.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:51.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.10:51:51.21#ibcon#first serial, iclass 34, count 0 2006.201.10:51:51.21#ibcon#enter sib2, iclass 34, count 0 2006.201.10:51:51.21#ibcon#flushed, iclass 34, count 0 2006.201.10:51:51.21#ibcon#about to write, iclass 34, count 0 2006.201.10:51:51.21#ibcon#wrote, iclass 34, count 0 2006.201.10:51:51.21#ibcon#about to read 3, iclass 34, count 0 2006.201.10:51:51.23#ibcon#read 3, iclass 34, count 0 2006.201.10:51:51.23#ibcon#about to read 4, iclass 34, count 0 2006.201.10:51:51.23#ibcon#read 4, iclass 34, count 0 2006.201.10:51:51.23#ibcon#about to read 5, iclass 34, count 0 2006.201.10:51:51.23#ibcon#read 5, iclass 34, count 0 2006.201.10:51:51.23#ibcon#about to read 6, iclass 34, count 0 2006.201.10:51:51.23#ibcon#read 6, iclass 34, count 0 2006.201.10:51:51.23#ibcon#end of sib2, iclass 34, count 0 2006.201.10:51:51.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.10:51:51.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.10:51:51.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.10:51:51.23#ibcon#*before write, iclass 34, count 0 2006.201.10:51:51.23#ibcon#enter sib2, iclass 34, count 0 2006.201.10:51:51.23#ibcon#flushed, iclass 34, count 0 2006.201.10:51:51.23#ibcon#about to write, iclass 34, count 0 2006.201.10:51:51.23#ibcon#wrote, iclass 34, count 0 2006.201.10:51:51.23#ibcon#about to read 3, iclass 34, count 0 2006.201.10:51:51.27#ibcon#read 3, iclass 34, count 0 2006.201.10:51:51.27#ibcon#about to read 4, iclass 34, count 0 2006.201.10:51:51.27#ibcon#read 4, iclass 34, count 0 2006.201.10:51:51.27#ibcon#about to read 5, iclass 34, count 0 2006.201.10:51:51.27#ibcon#read 5, iclass 34, count 0 2006.201.10:51:51.27#ibcon#about to read 6, iclass 34, count 0 2006.201.10:51:51.27#ibcon#read 6, iclass 34, count 0 2006.201.10:51:51.27#ibcon#end of sib2, iclass 34, count 0 2006.201.10:51:51.27#ibcon#*after write, iclass 34, count 0 2006.201.10:51:51.27#ibcon#*before return 0, iclass 34, count 0 2006.201.10:51:51.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:51.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.10:51:51.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.10:51:51.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.10:51:51.27$vck44/vb=3,4 2006.201.10:51:51.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.10:51:51.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.10:51:51.27#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:51.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:51.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:51.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:51.33#ibcon#enter wrdev, iclass 36, count 2 2006.201.10:51:51.33#ibcon#first serial, iclass 36, count 2 2006.201.10:51:51.33#ibcon#enter sib2, iclass 36, count 2 2006.201.10:51:51.33#ibcon#flushed, iclass 36, count 2 2006.201.10:51:51.33#ibcon#about to write, iclass 36, count 2 2006.201.10:51:51.33#ibcon#wrote, iclass 36, count 2 2006.201.10:51:51.33#ibcon#about to read 3, iclass 36, count 2 2006.201.10:51:51.35#ibcon#read 3, iclass 36, count 2 2006.201.10:51:51.35#ibcon#about to read 4, iclass 36, count 2 2006.201.10:51:51.35#ibcon#read 4, iclass 36, count 2 2006.201.10:51:51.35#ibcon#about to read 5, iclass 36, count 2 2006.201.10:51:51.35#ibcon#read 5, iclass 36, count 2 2006.201.10:51:51.35#ibcon#about to read 6, iclass 36, count 2 2006.201.10:51:51.35#ibcon#read 6, iclass 36, count 2 2006.201.10:51:51.35#ibcon#end of sib2, iclass 36, count 2 2006.201.10:51:51.35#ibcon#*mode == 0, iclass 36, count 2 2006.201.10:51:51.35#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.10:51:51.35#ibcon#[27=AT03-04\r\n] 2006.201.10:51:51.35#ibcon#*before write, iclass 36, count 2 2006.201.10:51:51.35#ibcon#enter sib2, iclass 36, count 2 2006.201.10:51:51.35#ibcon#flushed, iclass 36, count 2 2006.201.10:51:51.35#ibcon#about to write, iclass 36, count 2 2006.201.10:51:51.35#ibcon#wrote, iclass 36, count 2 2006.201.10:51:51.35#ibcon#about to read 3, iclass 36, count 2 2006.201.10:51:51.38#ibcon#read 3, iclass 36, count 2 2006.201.10:51:51.38#ibcon#about to read 4, iclass 36, count 2 2006.201.10:51:51.38#ibcon#read 4, iclass 36, count 2 2006.201.10:51:51.38#ibcon#about to read 5, iclass 36, count 2 2006.201.10:51:51.38#ibcon#read 5, iclass 36, count 2 2006.201.10:51:51.38#ibcon#about to read 6, iclass 36, count 2 2006.201.10:51:51.38#ibcon#read 6, iclass 36, count 2 2006.201.10:51:51.38#ibcon#end of sib2, iclass 36, count 2 2006.201.10:51:51.38#ibcon#*after write, iclass 36, count 2 2006.201.10:51:51.38#ibcon#*before return 0, iclass 36, count 2 2006.201.10:51:51.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:51.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.10:51:51.38#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.10:51:51.38#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:51.38#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:51.50#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:51.50#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:51.50#ibcon#enter wrdev, iclass 36, count 0 2006.201.10:51:51.50#ibcon#first serial, iclass 36, count 0 2006.201.10:51:51.50#ibcon#enter sib2, iclass 36, count 0 2006.201.10:51:51.50#ibcon#flushed, iclass 36, count 0 2006.201.10:51:51.50#ibcon#about to write, iclass 36, count 0 2006.201.10:51:51.50#ibcon#wrote, iclass 36, count 0 2006.201.10:51:51.50#ibcon#about to read 3, iclass 36, count 0 2006.201.10:51:51.52#ibcon#read 3, iclass 36, count 0 2006.201.10:51:51.52#ibcon#about to read 4, iclass 36, count 0 2006.201.10:51:51.52#ibcon#read 4, iclass 36, count 0 2006.201.10:51:51.52#ibcon#about to read 5, iclass 36, count 0 2006.201.10:51:51.52#ibcon#read 5, iclass 36, count 0 2006.201.10:51:51.52#ibcon#about to read 6, iclass 36, count 0 2006.201.10:51:51.52#ibcon#read 6, iclass 36, count 0 2006.201.10:51:51.52#ibcon#end of sib2, iclass 36, count 0 2006.201.10:51:51.52#ibcon#*mode == 0, iclass 36, count 0 2006.201.10:51:51.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.10:51:51.52#ibcon#[27=USB\r\n] 2006.201.10:51:51.52#ibcon#*before write, iclass 36, count 0 2006.201.10:51:51.52#ibcon#enter sib2, iclass 36, count 0 2006.201.10:51:51.52#ibcon#flushed, iclass 36, count 0 2006.201.10:51:51.52#ibcon#about to write, iclass 36, count 0 2006.201.10:51:51.52#ibcon#wrote, iclass 36, count 0 2006.201.10:51:51.52#ibcon#about to read 3, iclass 36, count 0 2006.201.10:51:51.55#ibcon#read 3, iclass 36, count 0 2006.201.10:51:51.55#ibcon#about to read 4, iclass 36, count 0 2006.201.10:51:51.55#ibcon#read 4, iclass 36, count 0 2006.201.10:51:51.55#ibcon#about to read 5, iclass 36, count 0 2006.201.10:51:51.55#ibcon#read 5, iclass 36, count 0 2006.201.10:51:51.55#ibcon#about to read 6, iclass 36, count 0 2006.201.10:51:51.55#ibcon#read 6, iclass 36, count 0 2006.201.10:51:51.55#ibcon#end of sib2, iclass 36, count 0 2006.201.10:51:51.55#ibcon#*after write, iclass 36, count 0 2006.201.10:51:51.55#ibcon#*before return 0, iclass 36, count 0 2006.201.10:51:51.55#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:51.55#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.10:51:51.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.10:51:51.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.10:51:51.55$vck44/vblo=4,679.99 2006.201.10:51:51.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.10:51:51.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.10:51:51.55#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:51.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:51.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:51.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:51.55#ibcon#enter wrdev, iclass 38, count 0 2006.201.10:51:51.55#ibcon#first serial, iclass 38, count 0 2006.201.10:51:51.55#ibcon#enter sib2, iclass 38, count 0 2006.201.10:51:51.55#ibcon#flushed, iclass 38, count 0 2006.201.10:51:51.55#ibcon#about to write, iclass 38, count 0 2006.201.10:51:51.55#ibcon#wrote, iclass 38, count 0 2006.201.10:51:51.55#ibcon#about to read 3, iclass 38, count 0 2006.201.10:51:51.57#ibcon#read 3, iclass 38, count 0 2006.201.10:51:51.57#ibcon#about to read 4, iclass 38, count 0 2006.201.10:51:51.57#ibcon#read 4, iclass 38, count 0 2006.201.10:51:51.57#ibcon#about to read 5, iclass 38, count 0 2006.201.10:51:51.57#ibcon#read 5, iclass 38, count 0 2006.201.10:51:51.57#ibcon#about to read 6, iclass 38, count 0 2006.201.10:51:51.57#ibcon#read 6, iclass 38, count 0 2006.201.10:51:51.57#ibcon#end of sib2, iclass 38, count 0 2006.201.10:51:51.57#ibcon#*mode == 0, iclass 38, count 0 2006.201.10:51:51.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.10:51:51.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.10:51:51.57#ibcon#*before write, iclass 38, count 0 2006.201.10:51:51.57#ibcon#enter sib2, iclass 38, count 0 2006.201.10:51:51.57#ibcon#flushed, iclass 38, count 0 2006.201.10:51:51.57#ibcon#about to write, iclass 38, count 0 2006.201.10:51:51.57#ibcon#wrote, iclass 38, count 0 2006.201.10:51:51.57#ibcon#about to read 3, iclass 38, count 0 2006.201.10:51:51.61#ibcon#read 3, iclass 38, count 0 2006.201.10:51:51.61#ibcon#about to read 4, iclass 38, count 0 2006.201.10:51:51.61#ibcon#read 4, iclass 38, count 0 2006.201.10:51:51.61#ibcon#about to read 5, iclass 38, count 0 2006.201.10:51:51.61#ibcon#read 5, iclass 38, count 0 2006.201.10:51:51.61#ibcon#about to read 6, iclass 38, count 0 2006.201.10:51:51.61#ibcon#read 6, iclass 38, count 0 2006.201.10:51:51.61#ibcon#end of sib2, iclass 38, count 0 2006.201.10:51:51.61#ibcon#*after write, iclass 38, count 0 2006.201.10:51:51.61#ibcon#*before return 0, iclass 38, count 0 2006.201.10:51:51.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:51.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.10:51:51.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.10:51:51.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.10:51:51.61$vck44/vb=4,5 2006.201.10:51:51.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.10:51:51.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.10:51:51.61#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:51.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:51.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:51.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:51.67#ibcon#enter wrdev, iclass 40, count 2 2006.201.10:51:51.67#ibcon#first serial, iclass 40, count 2 2006.201.10:51:51.67#ibcon#enter sib2, iclass 40, count 2 2006.201.10:51:51.67#ibcon#flushed, iclass 40, count 2 2006.201.10:51:51.67#ibcon#about to write, iclass 40, count 2 2006.201.10:51:51.67#ibcon#wrote, iclass 40, count 2 2006.201.10:51:51.67#ibcon#about to read 3, iclass 40, count 2 2006.201.10:51:51.69#ibcon#read 3, iclass 40, count 2 2006.201.10:51:51.69#ibcon#about to read 4, iclass 40, count 2 2006.201.10:51:51.69#ibcon#read 4, iclass 40, count 2 2006.201.10:51:51.69#ibcon#about to read 5, iclass 40, count 2 2006.201.10:51:51.69#ibcon#read 5, iclass 40, count 2 2006.201.10:51:51.69#ibcon#about to read 6, iclass 40, count 2 2006.201.10:51:51.69#ibcon#read 6, iclass 40, count 2 2006.201.10:51:51.69#ibcon#end of sib2, iclass 40, count 2 2006.201.10:51:51.69#ibcon#*mode == 0, iclass 40, count 2 2006.201.10:51:51.69#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.10:51:51.69#ibcon#[27=AT04-05\r\n] 2006.201.10:51:51.69#ibcon#*before write, iclass 40, count 2 2006.201.10:51:51.69#ibcon#enter sib2, iclass 40, count 2 2006.201.10:51:51.69#ibcon#flushed, iclass 40, count 2 2006.201.10:51:51.69#ibcon#about to write, iclass 40, count 2 2006.201.10:51:51.69#ibcon#wrote, iclass 40, count 2 2006.201.10:51:51.69#ibcon#about to read 3, iclass 40, count 2 2006.201.10:51:51.72#ibcon#read 3, iclass 40, count 2 2006.201.10:51:51.72#ibcon#about to read 4, iclass 40, count 2 2006.201.10:51:51.72#ibcon#read 4, iclass 40, count 2 2006.201.10:51:51.72#ibcon#about to read 5, iclass 40, count 2 2006.201.10:51:51.72#ibcon#read 5, iclass 40, count 2 2006.201.10:51:51.72#ibcon#about to read 6, iclass 40, count 2 2006.201.10:51:51.72#ibcon#read 6, iclass 40, count 2 2006.201.10:51:51.72#ibcon#end of sib2, iclass 40, count 2 2006.201.10:51:51.72#ibcon#*after write, iclass 40, count 2 2006.201.10:51:51.72#ibcon#*before return 0, iclass 40, count 2 2006.201.10:51:51.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:51.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.10:51:51.72#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.10:51:51.72#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:51.72#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:51.84#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:51.84#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:51.84#ibcon#enter wrdev, iclass 40, count 0 2006.201.10:51:51.84#ibcon#first serial, iclass 40, count 0 2006.201.10:51:51.84#ibcon#enter sib2, iclass 40, count 0 2006.201.10:51:51.84#ibcon#flushed, iclass 40, count 0 2006.201.10:51:51.84#ibcon#about to write, iclass 40, count 0 2006.201.10:51:51.84#ibcon#wrote, iclass 40, count 0 2006.201.10:51:51.84#ibcon#about to read 3, iclass 40, count 0 2006.201.10:51:51.86#ibcon#read 3, iclass 40, count 0 2006.201.10:51:51.86#ibcon#about to read 4, iclass 40, count 0 2006.201.10:51:51.86#ibcon#read 4, iclass 40, count 0 2006.201.10:51:51.86#ibcon#about to read 5, iclass 40, count 0 2006.201.10:51:51.86#ibcon#read 5, iclass 40, count 0 2006.201.10:51:51.86#ibcon#about to read 6, iclass 40, count 0 2006.201.10:51:51.86#ibcon#read 6, iclass 40, count 0 2006.201.10:51:51.86#ibcon#end of sib2, iclass 40, count 0 2006.201.10:51:51.86#ibcon#*mode == 0, iclass 40, count 0 2006.201.10:51:51.86#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.10:51:51.86#ibcon#[27=USB\r\n] 2006.201.10:51:51.86#ibcon#*before write, iclass 40, count 0 2006.201.10:51:51.86#ibcon#enter sib2, iclass 40, count 0 2006.201.10:51:51.86#ibcon#flushed, iclass 40, count 0 2006.201.10:51:51.86#ibcon#about to write, iclass 40, count 0 2006.201.10:51:51.86#ibcon#wrote, iclass 40, count 0 2006.201.10:51:51.86#ibcon#about to read 3, iclass 40, count 0 2006.201.10:51:51.89#ibcon#read 3, iclass 40, count 0 2006.201.10:51:51.89#ibcon#about to read 4, iclass 40, count 0 2006.201.10:51:51.89#ibcon#read 4, iclass 40, count 0 2006.201.10:51:51.89#ibcon#about to read 5, iclass 40, count 0 2006.201.10:51:51.89#ibcon#read 5, iclass 40, count 0 2006.201.10:51:51.89#ibcon#about to read 6, iclass 40, count 0 2006.201.10:51:51.89#ibcon#read 6, iclass 40, count 0 2006.201.10:51:51.89#ibcon#end of sib2, iclass 40, count 0 2006.201.10:51:51.89#ibcon#*after write, iclass 40, count 0 2006.201.10:51:51.89#ibcon#*before return 0, iclass 40, count 0 2006.201.10:51:51.89#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:51.89#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.10:51:51.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.10:51:51.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.10:51:51.89$vck44/vblo=5,709.99 2006.201.10:51:51.89#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.10:51:51.89#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.10:51:51.89#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:51.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:51.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:51.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:51.89#ibcon#enter wrdev, iclass 4, count 0 2006.201.10:51:51.89#ibcon#first serial, iclass 4, count 0 2006.201.10:51:51.89#ibcon#enter sib2, iclass 4, count 0 2006.201.10:51:51.89#ibcon#flushed, iclass 4, count 0 2006.201.10:51:51.89#ibcon#about to write, iclass 4, count 0 2006.201.10:51:51.89#ibcon#wrote, iclass 4, count 0 2006.201.10:51:51.89#ibcon#about to read 3, iclass 4, count 0 2006.201.10:51:51.91#ibcon#read 3, iclass 4, count 0 2006.201.10:51:51.91#ibcon#about to read 4, iclass 4, count 0 2006.201.10:51:51.91#ibcon#read 4, iclass 4, count 0 2006.201.10:51:51.91#ibcon#about to read 5, iclass 4, count 0 2006.201.10:51:51.91#ibcon#read 5, iclass 4, count 0 2006.201.10:51:51.91#ibcon#about to read 6, iclass 4, count 0 2006.201.10:51:51.91#ibcon#read 6, iclass 4, count 0 2006.201.10:51:51.91#ibcon#end of sib2, iclass 4, count 0 2006.201.10:51:51.91#ibcon#*mode == 0, iclass 4, count 0 2006.201.10:51:51.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.10:51:51.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.10:51:51.91#ibcon#*before write, iclass 4, count 0 2006.201.10:51:51.91#ibcon#enter sib2, iclass 4, count 0 2006.201.10:51:51.91#ibcon#flushed, iclass 4, count 0 2006.201.10:51:51.91#ibcon#about to write, iclass 4, count 0 2006.201.10:51:51.91#ibcon#wrote, iclass 4, count 0 2006.201.10:51:51.91#ibcon#about to read 3, iclass 4, count 0 2006.201.10:51:51.96#ibcon#read 3, iclass 4, count 0 2006.201.10:51:51.96#ibcon#about to read 4, iclass 4, count 0 2006.201.10:51:51.96#ibcon#read 4, iclass 4, count 0 2006.201.10:51:51.96#ibcon#about to read 5, iclass 4, count 0 2006.201.10:51:51.96#ibcon#read 5, iclass 4, count 0 2006.201.10:51:51.96#ibcon#about to read 6, iclass 4, count 0 2006.201.10:51:51.96#ibcon#read 6, iclass 4, count 0 2006.201.10:51:51.96#ibcon#end of sib2, iclass 4, count 0 2006.201.10:51:51.96#ibcon#*after write, iclass 4, count 0 2006.201.10:51:51.96#ibcon#*before return 0, iclass 4, count 0 2006.201.10:51:51.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:51.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.10:51:51.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.10:51:51.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.10:51:51.96$vck44/vb=5,4 2006.201.10:51:51.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.10:51:51.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.10:51:51.96#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:51.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:52.01#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:52.01#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:52.01#ibcon#enter wrdev, iclass 6, count 2 2006.201.10:51:52.01#ibcon#first serial, iclass 6, count 2 2006.201.10:51:52.01#ibcon#enter sib2, iclass 6, count 2 2006.201.10:51:52.01#ibcon#flushed, iclass 6, count 2 2006.201.10:51:52.01#ibcon#about to write, iclass 6, count 2 2006.201.10:51:52.01#ibcon#wrote, iclass 6, count 2 2006.201.10:51:52.01#ibcon#about to read 3, iclass 6, count 2 2006.201.10:51:52.03#ibcon#read 3, iclass 6, count 2 2006.201.10:51:52.03#ibcon#about to read 4, iclass 6, count 2 2006.201.10:51:52.03#ibcon#read 4, iclass 6, count 2 2006.201.10:51:52.03#ibcon#about to read 5, iclass 6, count 2 2006.201.10:51:52.03#ibcon#read 5, iclass 6, count 2 2006.201.10:51:52.03#ibcon#about to read 6, iclass 6, count 2 2006.201.10:51:52.03#ibcon#read 6, iclass 6, count 2 2006.201.10:51:52.03#ibcon#end of sib2, iclass 6, count 2 2006.201.10:51:52.03#ibcon#*mode == 0, iclass 6, count 2 2006.201.10:51:52.03#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.10:51:52.03#ibcon#[27=AT05-04\r\n] 2006.201.10:51:52.03#ibcon#*before write, iclass 6, count 2 2006.201.10:51:52.03#ibcon#enter sib2, iclass 6, count 2 2006.201.10:51:52.03#ibcon#flushed, iclass 6, count 2 2006.201.10:51:52.03#ibcon#about to write, iclass 6, count 2 2006.201.10:51:52.03#ibcon#wrote, iclass 6, count 2 2006.201.10:51:52.03#ibcon#about to read 3, iclass 6, count 2 2006.201.10:51:52.06#ibcon#read 3, iclass 6, count 2 2006.201.10:51:52.06#ibcon#about to read 4, iclass 6, count 2 2006.201.10:51:52.06#ibcon#read 4, iclass 6, count 2 2006.201.10:51:52.06#ibcon#about to read 5, iclass 6, count 2 2006.201.10:51:52.06#ibcon#read 5, iclass 6, count 2 2006.201.10:51:52.06#ibcon#about to read 6, iclass 6, count 2 2006.201.10:51:52.06#ibcon#read 6, iclass 6, count 2 2006.201.10:51:52.06#ibcon#end of sib2, iclass 6, count 2 2006.201.10:51:52.06#ibcon#*after write, iclass 6, count 2 2006.201.10:51:52.06#ibcon#*before return 0, iclass 6, count 2 2006.201.10:51:52.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:52.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.10:51:52.06#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.10:51:52.06#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:52.06#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:52.18#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:52.18#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:52.18#ibcon#enter wrdev, iclass 6, count 0 2006.201.10:51:52.18#ibcon#first serial, iclass 6, count 0 2006.201.10:51:52.18#ibcon#enter sib2, iclass 6, count 0 2006.201.10:51:52.18#ibcon#flushed, iclass 6, count 0 2006.201.10:51:52.18#ibcon#about to write, iclass 6, count 0 2006.201.10:51:52.18#ibcon#wrote, iclass 6, count 0 2006.201.10:51:52.18#ibcon#about to read 3, iclass 6, count 0 2006.201.10:51:52.20#ibcon#read 3, iclass 6, count 0 2006.201.10:51:52.20#ibcon#about to read 4, iclass 6, count 0 2006.201.10:51:52.20#ibcon#read 4, iclass 6, count 0 2006.201.10:51:52.20#ibcon#about to read 5, iclass 6, count 0 2006.201.10:51:52.20#ibcon#read 5, iclass 6, count 0 2006.201.10:51:52.20#ibcon#about to read 6, iclass 6, count 0 2006.201.10:51:52.20#ibcon#read 6, iclass 6, count 0 2006.201.10:51:52.20#ibcon#end of sib2, iclass 6, count 0 2006.201.10:51:52.20#ibcon#*mode == 0, iclass 6, count 0 2006.201.10:51:52.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.10:51:52.20#ibcon#[27=USB\r\n] 2006.201.10:51:52.20#ibcon#*before write, iclass 6, count 0 2006.201.10:51:52.20#ibcon#enter sib2, iclass 6, count 0 2006.201.10:51:52.20#ibcon#flushed, iclass 6, count 0 2006.201.10:51:52.20#ibcon#about to write, iclass 6, count 0 2006.201.10:51:52.20#ibcon#wrote, iclass 6, count 0 2006.201.10:51:52.20#ibcon#about to read 3, iclass 6, count 0 2006.201.10:51:52.23#ibcon#read 3, iclass 6, count 0 2006.201.10:51:52.23#ibcon#about to read 4, iclass 6, count 0 2006.201.10:51:52.23#ibcon#read 4, iclass 6, count 0 2006.201.10:51:52.23#ibcon#about to read 5, iclass 6, count 0 2006.201.10:51:52.23#ibcon#read 5, iclass 6, count 0 2006.201.10:51:52.23#ibcon#about to read 6, iclass 6, count 0 2006.201.10:51:52.23#ibcon#read 6, iclass 6, count 0 2006.201.10:51:52.23#ibcon#end of sib2, iclass 6, count 0 2006.201.10:51:52.23#ibcon#*after write, iclass 6, count 0 2006.201.10:51:52.23#ibcon#*before return 0, iclass 6, count 0 2006.201.10:51:52.23#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:52.23#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.10:51:52.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.10:51:52.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.10:51:52.23$vck44/vblo=6,719.99 2006.201.10:51:52.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.10:51:52.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.10:51:52.23#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:52.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:52.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:52.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:52.23#ibcon#enter wrdev, iclass 10, count 0 2006.201.10:51:52.23#ibcon#first serial, iclass 10, count 0 2006.201.10:51:52.23#ibcon#enter sib2, iclass 10, count 0 2006.201.10:51:52.23#ibcon#flushed, iclass 10, count 0 2006.201.10:51:52.23#ibcon#about to write, iclass 10, count 0 2006.201.10:51:52.23#ibcon#wrote, iclass 10, count 0 2006.201.10:51:52.23#ibcon#about to read 3, iclass 10, count 0 2006.201.10:51:52.25#ibcon#read 3, iclass 10, count 0 2006.201.10:51:52.25#ibcon#about to read 4, iclass 10, count 0 2006.201.10:51:52.25#ibcon#read 4, iclass 10, count 0 2006.201.10:51:52.25#ibcon#about to read 5, iclass 10, count 0 2006.201.10:51:52.25#ibcon#read 5, iclass 10, count 0 2006.201.10:51:52.25#ibcon#about to read 6, iclass 10, count 0 2006.201.10:51:52.25#ibcon#read 6, iclass 10, count 0 2006.201.10:51:52.25#ibcon#end of sib2, iclass 10, count 0 2006.201.10:51:52.25#ibcon#*mode == 0, iclass 10, count 0 2006.201.10:51:52.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.10:51:52.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.10:51:52.25#ibcon#*before write, iclass 10, count 0 2006.201.10:51:52.25#ibcon#enter sib2, iclass 10, count 0 2006.201.10:51:52.25#ibcon#flushed, iclass 10, count 0 2006.201.10:51:52.25#ibcon#about to write, iclass 10, count 0 2006.201.10:51:52.25#ibcon#wrote, iclass 10, count 0 2006.201.10:51:52.25#ibcon#about to read 3, iclass 10, count 0 2006.201.10:51:52.29#ibcon#read 3, iclass 10, count 0 2006.201.10:51:52.29#ibcon#about to read 4, iclass 10, count 0 2006.201.10:51:52.29#ibcon#read 4, iclass 10, count 0 2006.201.10:51:52.29#ibcon#about to read 5, iclass 10, count 0 2006.201.10:51:52.29#ibcon#read 5, iclass 10, count 0 2006.201.10:51:52.29#ibcon#about to read 6, iclass 10, count 0 2006.201.10:51:52.29#ibcon#read 6, iclass 10, count 0 2006.201.10:51:52.29#ibcon#end of sib2, iclass 10, count 0 2006.201.10:51:52.29#ibcon#*after write, iclass 10, count 0 2006.201.10:51:52.29#ibcon#*before return 0, iclass 10, count 0 2006.201.10:51:52.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:52.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.10:51:52.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.10:51:52.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.10:51:52.29$vck44/vb=6,4 2006.201.10:51:52.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.10:51:52.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.10:51:52.29#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:52.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:52.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:52.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:52.35#ibcon#enter wrdev, iclass 12, count 2 2006.201.10:51:52.35#ibcon#first serial, iclass 12, count 2 2006.201.10:51:52.35#ibcon#enter sib2, iclass 12, count 2 2006.201.10:51:52.35#ibcon#flushed, iclass 12, count 2 2006.201.10:51:52.35#ibcon#about to write, iclass 12, count 2 2006.201.10:51:52.35#ibcon#wrote, iclass 12, count 2 2006.201.10:51:52.35#ibcon#about to read 3, iclass 12, count 2 2006.201.10:51:52.37#ibcon#read 3, iclass 12, count 2 2006.201.10:51:52.37#ibcon#about to read 4, iclass 12, count 2 2006.201.10:51:52.37#ibcon#read 4, iclass 12, count 2 2006.201.10:51:52.37#ibcon#about to read 5, iclass 12, count 2 2006.201.10:51:52.37#ibcon#read 5, iclass 12, count 2 2006.201.10:51:52.37#ibcon#about to read 6, iclass 12, count 2 2006.201.10:51:52.37#ibcon#read 6, iclass 12, count 2 2006.201.10:51:52.37#ibcon#end of sib2, iclass 12, count 2 2006.201.10:51:52.37#ibcon#*mode == 0, iclass 12, count 2 2006.201.10:51:52.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.10:51:52.37#ibcon#[27=AT06-04\r\n] 2006.201.10:51:52.37#ibcon#*before write, iclass 12, count 2 2006.201.10:51:52.37#ibcon#enter sib2, iclass 12, count 2 2006.201.10:51:52.37#ibcon#flushed, iclass 12, count 2 2006.201.10:51:52.37#ibcon#about to write, iclass 12, count 2 2006.201.10:51:52.37#ibcon#wrote, iclass 12, count 2 2006.201.10:51:52.37#ibcon#about to read 3, iclass 12, count 2 2006.201.10:51:52.40#ibcon#read 3, iclass 12, count 2 2006.201.10:51:52.40#ibcon#about to read 4, iclass 12, count 2 2006.201.10:51:52.40#ibcon#read 4, iclass 12, count 2 2006.201.10:51:52.40#ibcon#about to read 5, iclass 12, count 2 2006.201.10:51:52.40#ibcon#read 5, iclass 12, count 2 2006.201.10:51:52.40#ibcon#about to read 6, iclass 12, count 2 2006.201.10:51:52.40#ibcon#read 6, iclass 12, count 2 2006.201.10:51:52.40#ibcon#end of sib2, iclass 12, count 2 2006.201.10:51:52.40#ibcon#*after write, iclass 12, count 2 2006.201.10:51:52.40#ibcon#*before return 0, iclass 12, count 2 2006.201.10:51:52.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:52.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.10:51:52.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.10:51:52.40#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:52.40#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:52.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:52.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:52.52#ibcon#enter wrdev, iclass 12, count 0 2006.201.10:51:52.52#ibcon#first serial, iclass 12, count 0 2006.201.10:51:52.52#ibcon#enter sib2, iclass 12, count 0 2006.201.10:51:52.52#ibcon#flushed, iclass 12, count 0 2006.201.10:51:52.52#ibcon#about to write, iclass 12, count 0 2006.201.10:51:52.52#ibcon#wrote, iclass 12, count 0 2006.201.10:51:52.52#ibcon#about to read 3, iclass 12, count 0 2006.201.10:51:52.54#ibcon#read 3, iclass 12, count 0 2006.201.10:51:52.54#ibcon#about to read 4, iclass 12, count 0 2006.201.10:51:52.54#ibcon#read 4, iclass 12, count 0 2006.201.10:51:52.54#ibcon#about to read 5, iclass 12, count 0 2006.201.10:51:52.54#ibcon#read 5, iclass 12, count 0 2006.201.10:51:52.54#ibcon#about to read 6, iclass 12, count 0 2006.201.10:51:52.54#ibcon#read 6, iclass 12, count 0 2006.201.10:51:52.54#ibcon#end of sib2, iclass 12, count 0 2006.201.10:51:52.54#ibcon#*mode == 0, iclass 12, count 0 2006.201.10:51:52.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.10:51:52.54#ibcon#[27=USB\r\n] 2006.201.10:51:52.54#ibcon#*before write, iclass 12, count 0 2006.201.10:51:52.54#ibcon#enter sib2, iclass 12, count 0 2006.201.10:51:52.54#ibcon#flushed, iclass 12, count 0 2006.201.10:51:52.54#ibcon#about to write, iclass 12, count 0 2006.201.10:51:52.54#ibcon#wrote, iclass 12, count 0 2006.201.10:51:52.54#ibcon#about to read 3, iclass 12, count 0 2006.201.10:51:52.57#ibcon#read 3, iclass 12, count 0 2006.201.10:51:52.57#ibcon#about to read 4, iclass 12, count 0 2006.201.10:51:52.57#ibcon#read 4, iclass 12, count 0 2006.201.10:51:52.57#ibcon#about to read 5, iclass 12, count 0 2006.201.10:51:52.57#ibcon#read 5, iclass 12, count 0 2006.201.10:51:52.57#ibcon#about to read 6, iclass 12, count 0 2006.201.10:51:52.57#ibcon#read 6, iclass 12, count 0 2006.201.10:51:52.57#ibcon#end of sib2, iclass 12, count 0 2006.201.10:51:52.57#ibcon#*after write, iclass 12, count 0 2006.201.10:51:52.57#ibcon#*before return 0, iclass 12, count 0 2006.201.10:51:52.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:52.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.10:51:52.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.10:51:52.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.10:51:52.57$vck44/vblo=7,734.99 2006.201.10:51:52.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.10:51:52.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.10:51:52.57#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:52.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:52.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:52.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:52.57#ibcon#enter wrdev, iclass 14, count 0 2006.201.10:51:52.57#ibcon#first serial, iclass 14, count 0 2006.201.10:51:52.57#ibcon#enter sib2, iclass 14, count 0 2006.201.10:51:52.57#ibcon#flushed, iclass 14, count 0 2006.201.10:51:52.57#ibcon#about to write, iclass 14, count 0 2006.201.10:51:52.57#ibcon#wrote, iclass 14, count 0 2006.201.10:51:52.57#ibcon#about to read 3, iclass 14, count 0 2006.201.10:51:52.59#ibcon#read 3, iclass 14, count 0 2006.201.10:51:52.59#ibcon#about to read 4, iclass 14, count 0 2006.201.10:51:52.59#ibcon#read 4, iclass 14, count 0 2006.201.10:51:52.59#ibcon#about to read 5, iclass 14, count 0 2006.201.10:51:52.59#ibcon#read 5, iclass 14, count 0 2006.201.10:51:52.59#ibcon#about to read 6, iclass 14, count 0 2006.201.10:51:52.59#ibcon#read 6, iclass 14, count 0 2006.201.10:51:52.59#ibcon#end of sib2, iclass 14, count 0 2006.201.10:51:52.59#ibcon#*mode == 0, iclass 14, count 0 2006.201.10:51:52.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.10:51:52.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.10:51:52.59#ibcon#*before write, iclass 14, count 0 2006.201.10:51:52.59#ibcon#enter sib2, iclass 14, count 0 2006.201.10:51:52.59#ibcon#flushed, iclass 14, count 0 2006.201.10:51:52.59#ibcon#about to write, iclass 14, count 0 2006.201.10:51:52.59#ibcon#wrote, iclass 14, count 0 2006.201.10:51:52.59#ibcon#about to read 3, iclass 14, count 0 2006.201.10:51:52.63#ibcon#read 3, iclass 14, count 0 2006.201.10:51:52.63#ibcon#about to read 4, iclass 14, count 0 2006.201.10:51:52.63#ibcon#read 4, iclass 14, count 0 2006.201.10:51:52.63#ibcon#about to read 5, iclass 14, count 0 2006.201.10:51:52.63#ibcon#read 5, iclass 14, count 0 2006.201.10:51:52.63#ibcon#about to read 6, iclass 14, count 0 2006.201.10:51:52.63#ibcon#read 6, iclass 14, count 0 2006.201.10:51:52.63#ibcon#end of sib2, iclass 14, count 0 2006.201.10:51:52.63#ibcon#*after write, iclass 14, count 0 2006.201.10:51:52.63#ibcon#*before return 0, iclass 14, count 0 2006.201.10:51:52.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:52.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.10:51:52.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.10:51:52.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.10:51:52.63$vck44/vb=7,4 2006.201.10:51:52.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.10:51:52.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.10:51:52.63#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:52.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:52.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:52.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:52.69#ibcon#enter wrdev, iclass 16, count 2 2006.201.10:51:52.69#ibcon#first serial, iclass 16, count 2 2006.201.10:51:52.69#ibcon#enter sib2, iclass 16, count 2 2006.201.10:51:52.69#ibcon#flushed, iclass 16, count 2 2006.201.10:51:52.69#ibcon#about to write, iclass 16, count 2 2006.201.10:51:52.69#ibcon#wrote, iclass 16, count 2 2006.201.10:51:52.69#ibcon#about to read 3, iclass 16, count 2 2006.201.10:51:52.71#ibcon#read 3, iclass 16, count 2 2006.201.10:51:52.71#ibcon#about to read 4, iclass 16, count 2 2006.201.10:51:52.71#ibcon#read 4, iclass 16, count 2 2006.201.10:51:52.71#ibcon#about to read 5, iclass 16, count 2 2006.201.10:51:52.71#ibcon#read 5, iclass 16, count 2 2006.201.10:51:52.71#ibcon#about to read 6, iclass 16, count 2 2006.201.10:51:52.71#ibcon#read 6, iclass 16, count 2 2006.201.10:51:52.71#ibcon#end of sib2, iclass 16, count 2 2006.201.10:51:52.71#ibcon#*mode == 0, iclass 16, count 2 2006.201.10:51:52.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.10:51:52.71#ibcon#[27=AT07-04\r\n] 2006.201.10:51:52.71#ibcon#*before write, iclass 16, count 2 2006.201.10:51:52.71#ibcon#enter sib2, iclass 16, count 2 2006.201.10:51:52.71#ibcon#flushed, iclass 16, count 2 2006.201.10:51:52.71#ibcon#about to write, iclass 16, count 2 2006.201.10:51:52.71#ibcon#wrote, iclass 16, count 2 2006.201.10:51:52.71#ibcon#about to read 3, iclass 16, count 2 2006.201.10:51:52.74#ibcon#read 3, iclass 16, count 2 2006.201.10:51:52.74#ibcon#about to read 4, iclass 16, count 2 2006.201.10:51:52.74#ibcon#read 4, iclass 16, count 2 2006.201.10:51:52.74#ibcon#about to read 5, iclass 16, count 2 2006.201.10:51:52.74#ibcon#read 5, iclass 16, count 2 2006.201.10:51:52.74#ibcon#about to read 6, iclass 16, count 2 2006.201.10:51:52.74#ibcon#read 6, iclass 16, count 2 2006.201.10:51:52.74#ibcon#end of sib2, iclass 16, count 2 2006.201.10:51:52.74#ibcon#*after write, iclass 16, count 2 2006.201.10:51:52.74#ibcon#*before return 0, iclass 16, count 2 2006.201.10:51:52.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:52.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.10:51:52.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.10:51:52.74#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:52.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:52.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:52.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:52.86#ibcon#enter wrdev, iclass 16, count 0 2006.201.10:51:52.86#ibcon#first serial, iclass 16, count 0 2006.201.10:51:52.86#ibcon#enter sib2, iclass 16, count 0 2006.201.10:51:52.86#ibcon#flushed, iclass 16, count 0 2006.201.10:51:52.86#ibcon#about to write, iclass 16, count 0 2006.201.10:51:52.86#ibcon#wrote, iclass 16, count 0 2006.201.10:51:52.86#ibcon#about to read 3, iclass 16, count 0 2006.201.10:51:52.88#ibcon#read 3, iclass 16, count 0 2006.201.10:51:52.88#ibcon#about to read 4, iclass 16, count 0 2006.201.10:51:52.88#ibcon#read 4, iclass 16, count 0 2006.201.10:51:52.88#ibcon#about to read 5, iclass 16, count 0 2006.201.10:51:52.88#ibcon#read 5, iclass 16, count 0 2006.201.10:51:52.88#ibcon#about to read 6, iclass 16, count 0 2006.201.10:51:52.88#ibcon#read 6, iclass 16, count 0 2006.201.10:51:52.88#ibcon#end of sib2, iclass 16, count 0 2006.201.10:51:52.88#ibcon#*mode == 0, iclass 16, count 0 2006.201.10:51:52.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.10:51:52.88#ibcon#[27=USB\r\n] 2006.201.10:51:52.88#ibcon#*before write, iclass 16, count 0 2006.201.10:51:52.88#ibcon#enter sib2, iclass 16, count 0 2006.201.10:51:52.88#ibcon#flushed, iclass 16, count 0 2006.201.10:51:52.88#ibcon#about to write, iclass 16, count 0 2006.201.10:51:52.88#ibcon#wrote, iclass 16, count 0 2006.201.10:51:52.88#ibcon#about to read 3, iclass 16, count 0 2006.201.10:51:52.91#ibcon#read 3, iclass 16, count 0 2006.201.10:51:52.91#ibcon#about to read 4, iclass 16, count 0 2006.201.10:51:52.91#ibcon#read 4, iclass 16, count 0 2006.201.10:51:52.91#ibcon#about to read 5, iclass 16, count 0 2006.201.10:51:52.91#ibcon#read 5, iclass 16, count 0 2006.201.10:51:52.91#ibcon#about to read 6, iclass 16, count 0 2006.201.10:51:52.91#ibcon#read 6, iclass 16, count 0 2006.201.10:51:52.91#ibcon#end of sib2, iclass 16, count 0 2006.201.10:51:52.91#ibcon#*after write, iclass 16, count 0 2006.201.10:51:52.91#ibcon#*before return 0, iclass 16, count 0 2006.201.10:51:52.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:52.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.10:51:52.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.10:51:52.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.10:51:52.91$vck44/vblo=8,744.99 2006.201.10:51:52.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.10:51:52.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.10:51:52.91#ibcon#ireg 17 cls_cnt 0 2006.201.10:51:52.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:52.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:52.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:52.91#ibcon#enter wrdev, iclass 18, count 0 2006.201.10:51:52.91#ibcon#first serial, iclass 18, count 0 2006.201.10:51:52.91#ibcon#enter sib2, iclass 18, count 0 2006.201.10:51:52.91#ibcon#flushed, iclass 18, count 0 2006.201.10:51:52.91#ibcon#about to write, iclass 18, count 0 2006.201.10:51:52.91#ibcon#wrote, iclass 18, count 0 2006.201.10:51:52.91#ibcon#about to read 3, iclass 18, count 0 2006.201.10:51:52.93#ibcon#read 3, iclass 18, count 0 2006.201.10:51:52.93#ibcon#about to read 4, iclass 18, count 0 2006.201.10:51:52.93#ibcon#read 4, iclass 18, count 0 2006.201.10:51:52.93#ibcon#about to read 5, iclass 18, count 0 2006.201.10:51:52.93#ibcon#read 5, iclass 18, count 0 2006.201.10:51:52.93#ibcon#about to read 6, iclass 18, count 0 2006.201.10:51:52.93#ibcon#read 6, iclass 18, count 0 2006.201.10:51:52.93#ibcon#end of sib2, iclass 18, count 0 2006.201.10:51:52.93#ibcon#*mode == 0, iclass 18, count 0 2006.201.10:51:52.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.10:51:52.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.10:51:52.93#ibcon#*before write, iclass 18, count 0 2006.201.10:51:52.93#ibcon#enter sib2, iclass 18, count 0 2006.201.10:51:52.93#ibcon#flushed, iclass 18, count 0 2006.201.10:51:52.93#ibcon#about to write, iclass 18, count 0 2006.201.10:51:52.93#ibcon#wrote, iclass 18, count 0 2006.201.10:51:52.93#ibcon#about to read 3, iclass 18, count 0 2006.201.10:51:52.98#ibcon#read 3, iclass 18, count 0 2006.201.10:51:52.98#ibcon#about to read 4, iclass 18, count 0 2006.201.10:51:52.98#ibcon#read 4, iclass 18, count 0 2006.201.10:51:52.98#ibcon#about to read 5, iclass 18, count 0 2006.201.10:51:52.98#ibcon#read 5, iclass 18, count 0 2006.201.10:51:52.98#ibcon#about to read 6, iclass 18, count 0 2006.201.10:51:52.98#ibcon#read 6, iclass 18, count 0 2006.201.10:51:52.98#ibcon#end of sib2, iclass 18, count 0 2006.201.10:51:52.98#ibcon#*after write, iclass 18, count 0 2006.201.10:51:52.98#ibcon#*before return 0, iclass 18, count 0 2006.201.10:51:52.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:52.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.10:51:52.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.10:51:52.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.10:51:52.98$vck44/vb=8,4 2006.201.10:51:52.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.10:51:52.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.10:51:52.98#ibcon#ireg 11 cls_cnt 2 2006.201.10:51:52.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:53.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:53.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:53.03#ibcon#enter wrdev, iclass 20, count 2 2006.201.10:51:53.03#ibcon#first serial, iclass 20, count 2 2006.201.10:51:53.03#ibcon#enter sib2, iclass 20, count 2 2006.201.10:51:53.03#ibcon#flushed, iclass 20, count 2 2006.201.10:51:53.03#ibcon#about to write, iclass 20, count 2 2006.201.10:51:53.03#ibcon#wrote, iclass 20, count 2 2006.201.10:51:53.03#ibcon#about to read 3, iclass 20, count 2 2006.201.10:51:53.05#ibcon#read 3, iclass 20, count 2 2006.201.10:51:53.05#ibcon#about to read 4, iclass 20, count 2 2006.201.10:51:53.05#ibcon#read 4, iclass 20, count 2 2006.201.10:51:53.05#ibcon#about to read 5, iclass 20, count 2 2006.201.10:51:53.05#ibcon#read 5, iclass 20, count 2 2006.201.10:51:53.05#ibcon#about to read 6, iclass 20, count 2 2006.201.10:51:53.05#ibcon#read 6, iclass 20, count 2 2006.201.10:51:53.05#ibcon#end of sib2, iclass 20, count 2 2006.201.10:51:53.05#ibcon#*mode == 0, iclass 20, count 2 2006.201.10:51:53.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.10:51:53.05#ibcon#[27=AT08-04\r\n] 2006.201.10:51:53.05#ibcon#*before write, iclass 20, count 2 2006.201.10:51:53.05#ibcon#enter sib2, iclass 20, count 2 2006.201.10:51:53.05#ibcon#flushed, iclass 20, count 2 2006.201.10:51:53.05#ibcon#about to write, iclass 20, count 2 2006.201.10:51:53.05#ibcon#wrote, iclass 20, count 2 2006.201.10:51:53.05#ibcon#about to read 3, iclass 20, count 2 2006.201.10:51:53.08#ibcon#read 3, iclass 20, count 2 2006.201.10:51:53.08#ibcon#about to read 4, iclass 20, count 2 2006.201.10:51:53.08#ibcon#read 4, iclass 20, count 2 2006.201.10:51:53.08#ibcon#about to read 5, iclass 20, count 2 2006.201.10:51:53.08#ibcon#read 5, iclass 20, count 2 2006.201.10:51:53.08#ibcon#about to read 6, iclass 20, count 2 2006.201.10:51:53.08#ibcon#read 6, iclass 20, count 2 2006.201.10:51:53.08#ibcon#end of sib2, iclass 20, count 2 2006.201.10:51:53.08#ibcon#*after write, iclass 20, count 2 2006.201.10:51:53.08#ibcon#*before return 0, iclass 20, count 2 2006.201.10:51:53.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:53.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.10:51:53.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.10:51:53.08#ibcon#ireg 7 cls_cnt 0 2006.201.10:51:53.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:53.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:53.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:53.20#ibcon#enter wrdev, iclass 20, count 0 2006.201.10:51:53.20#ibcon#first serial, iclass 20, count 0 2006.201.10:51:53.20#ibcon#enter sib2, iclass 20, count 0 2006.201.10:51:53.20#ibcon#flushed, iclass 20, count 0 2006.201.10:51:53.20#ibcon#about to write, iclass 20, count 0 2006.201.10:51:53.20#ibcon#wrote, iclass 20, count 0 2006.201.10:51:53.20#ibcon#about to read 3, iclass 20, count 0 2006.201.10:51:53.21#abcon#<5=/05 1.8 3.1 21.51 991003.7\r\n> 2006.201.10:51:53.22#ibcon#read 3, iclass 20, count 0 2006.201.10:51:53.22#ibcon#about to read 4, iclass 20, count 0 2006.201.10:51:53.22#ibcon#read 4, iclass 20, count 0 2006.201.10:51:53.22#ibcon#about to read 5, iclass 20, count 0 2006.201.10:51:53.22#ibcon#read 5, iclass 20, count 0 2006.201.10:51:53.22#ibcon#about to read 6, iclass 20, count 0 2006.201.10:51:53.22#ibcon#read 6, iclass 20, count 0 2006.201.10:51:53.22#ibcon#end of sib2, iclass 20, count 0 2006.201.10:51:53.22#ibcon#*mode == 0, iclass 20, count 0 2006.201.10:51:53.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.10:51:53.22#ibcon#[27=USB\r\n] 2006.201.10:51:53.22#ibcon#*before write, iclass 20, count 0 2006.201.10:51:53.22#ibcon#enter sib2, iclass 20, count 0 2006.201.10:51:53.22#ibcon#flushed, iclass 20, count 0 2006.201.10:51:53.22#ibcon#about to write, iclass 20, count 0 2006.201.10:51:53.22#ibcon#wrote, iclass 20, count 0 2006.201.10:51:53.22#ibcon#about to read 3, iclass 20, count 0 2006.201.10:51:53.23#abcon#{5=INTERFACE CLEAR} 2006.201.10:51:53.25#ibcon#read 3, iclass 20, count 0 2006.201.10:51:53.25#ibcon#about to read 4, iclass 20, count 0 2006.201.10:51:53.25#ibcon#read 4, iclass 20, count 0 2006.201.10:51:53.25#ibcon#about to read 5, iclass 20, count 0 2006.201.10:51:53.25#ibcon#read 5, iclass 20, count 0 2006.201.10:51:53.25#ibcon#about to read 6, iclass 20, count 0 2006.201.10:51:53.25#ibcon#read 6, iclass 20, count 0 2006.201.10:51:53.25#ibcon#end of sib2, iclass 20, count 0 2006.201.10:51:53.25#ibcon#*after write, iclass 20, count 0 2006.201.10:51:53.25#ibcon#*before return 0, iclass 20, count 0 2006.201.10:51:53.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:53.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.10:51:53.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.10:51:53.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.10:51:53.25$vck44/vabw=wide 2006.201.10:51:53.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.10:51:53.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.10:51:53.25#ibcon#ireg 8 cls_cnt 0 2006.201.10:51:53.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:51:53.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:51:53.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:51:53.25#ibcon#enter wrdev, iclass 25, count 0 2006.201.10:51:53.25#ibcon#first serial, iclass 25, count 0 2006.201.10:51:53.25#ibcon#enter sib2, iclass 25, count 0 2006.201.10:51:53.25#ibcon#flushed, iclass 25, count 0 2006.201.10:51:53.25#ibcon#about to write, iclass 25, count 0 2006.201.10:51:53.25#ibcon#wrote, iclass 25, count 0 2006.201.10:51:53.25#ibcon#about to read 3, iclass 25, count 0 2006.201.10:51:53.27#ibcon#read 3, iclass 25, count 0 2006.201.10:51:53.27#ibcon#about to read 4, iclass 25, count 0 2006.201.10:51:53.27#ibcon#read 4, iclass 25, count 0 2006.201.10:51:53.27#ibcon#about to read 5, iclass 25, count 0 2006.201.10:51:53.27#ibcon#read 5, iclass 25, count 0 2006.201.10:51:53.27#ibcon#about to read 6, iclass 25, count 0 2006.201.10:51:53.27#ibcon#read 6, iclass 25, count 0 2006.201.10:51:53.27#ibcon#end of sib2, iclass 25, count 0 2006.201.10:51:53.27#ibcon#*mode == 0, iclass 25, count 0 2006.201.10:51:53.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.10:51:53.27#ibcon#[25=BW32\r\n] 2006.201.10:51:53.27#ibcon#*before write, iclass 25, count 0 2006.201.10:51:53.27#ibcon#enter sib2, iclass 25, count 0 2006.201.10:51:53.27#ibcon#flushed, iclass 25, count 0 2006.201.10:51:53.27#ibcon#about to write, iclass 25, count 0 2006.201.10:51:53.27#ibcon#wrote, iclass 25, count 0 2006.201.10:51:53.27#ibcon#about to read 3, iclass 25, count 0 2006.201.10:51:53.29#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:51:53.30#ibcon#read 3, iclass 25, count 0 2006.201.10:51:53.30#ibcon#about to read 4, iclass 25, count 0 2006.201.10:51:53.30#ibcon#read 4, iclass 25, count 0 2006.201.10:51:53.30#ibcon#about to read 5, iclass 25, count 0 2006.201.10:51:53.30#ibcon#read 5, iclass 25, count 0 2006.201.10:51:53.30#ibcon#about to read 6, iclass 25, count 0 2006.201.10:51:53.30#ibcon#read 6, iclass 25, count 0 2006.201.10:51:53.30#ibcon#end of sib2, iclass 25, count 0 2006.201.10:51:53.30#ibcon#*after write, iclass 25, count 0 2006.201.10:51:53.30#ibcon#*before return 0, iclass 25, count 0 2006.201.10:51:53.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:51:53.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.10:51:53.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.10:51:53.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.10:51:53.30$vck44/vbbw=wide 2006.201.10:51:53.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.10:51:53.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.10:51:53.30#ibcon#ireg 8 cls_cnt 0 2006.201.10:51:53.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:51:53.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:51:53.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:51:53.37#ibcon#enter wrdev, iclass 28, count 0 2006.201.10:51:53.37#ibcon#first serial, iclass 28, count 0 2006.201.10:51:53.37#ibcon#enter sib2, iclass 28, count 0 2006.201.10:51:53.37#ibcon#flushed, iclass 28, count 0 2006.201.10:51:53.37#ibcon#about to write, iclass 28, count 0 2006.201.10:51:53.37#ibcon#wrote, iclass 28, count 0 2006.201.10:51:53.37#ibcon#about to read 3, iclass 28, count 0 2006.201.10:51:53.39#ibcon#read 3, iclass 28, count 0 2006.201.10:51:53.39#ibcon#about to read 4, iclass 28, count 0 2006.201.10:51:53.39#ibcon#read 4, iclass 28, count 0 2006.201.10:51:53.39#ibcon#about to read 5, iclass 28, count 0 2006.201.10:51:53.39#ibcon#read 5, iclass 28, count 0 2006.201.10:51:53.39#ibcon#about to read 6, iclass 28, count 0 2006.201.10:51:53.39#ibcon#read 6, iclass 28, count 0 2006.201.10:51:53.39#ibcon#end of sib2, iclass 28, count 0 2006.201.10:51:53.39#ibcon#*mode == 0, iclass 28, count 0 2006.201.10:51:53.39#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.10:51:53.39#ibcon#[27=BW32\r\n] 2006.201.10:51:53.39#ibcon#*before write, iclass 28, count 0 2006.201.10:51:53.39#ibcon#enter sib2, iclass 28, count 0 2006.201.10:51:53.39#ibcon#flushed, iclass 28, count 0 2006.201.10:51:53.39#ibcon#about to write, iclass 28, count 0 2006.201.10:51:53.39#ibcon#wrote, iclass 28, count 0 2006.201.10:51:53.39#ibcon#about to read 3, iclass 28, count 0 2006.201.10:51:53.42#ibcon#read 3, iclass 28, count 0 2006.201.10:51:53.42#ibcon#about to read 4, iclass 28, count 0 2006.201.10:51:53.42#ibcon#read 4, iclass 28, count 0 2006.201.10:51:53.42#ibcon#about to read 5, iclass 28, count 0 2006.201.10:51:53.42#ibcon#read 5, iclass 28, count 0 2006.201.10:51:53.42#ibcon#about to read 6, iclass 28, count 0 2006.201.10:51:53.42#ibcon#read 6, iclass 28, count 0 2006.201.10:51:53.42#ibcon#end of sib2, iclass 28, count 0 2006.201.10:51:53.42#ibcon#*after write, iclass 28, count 0 2006.201.10:51:53.42#ibcon#*before return 0, iclass 28, count 0 2006.201.10:51:53.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:51:53.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.10:51:53.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.10:51:53.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.10:51:53.42$setupk4/ifdk4 2006.201.10:51:53.42$ifdk4/lo= 2006.201.10:51:53.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.10:51:53.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.10:51:53.42$ifdk4/patch= 2006.201.10:51:53.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.10:51:53.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.10:51:53.42$setupk4/!*+20s 2006.201.10:52:03.38#abcon#<5=/05 1.8 3.0 21.51 991003.7\r\n> 2006.201.10:52:03.40#abcon#{5=INTERFACE CLEAR} 2006.201.10:52:03.46#abcon#[5=S1D000X0/0*\r\n] 2006.201.10:52:07.91$setupk4/"tpicd 2006.201.10:52:07.91$setupk4/echo=off 2006.201.10:52:07.91$setupk4/xlog=off 2006.201.10:52:07.91:!2006.201.10:56:53 2006.201.10:52:16.14#trakl#Source acquired 2006.201.10:52:16.14#flagr#flagr/antenna,acquired 2006.201.10:56:53.00:preob 2006.201.10:56:53.14/onsource/TRACKING 2006.201.10:56:53.14:!2006.201.10:57:03 2006.201.10:57:03.00:"tape 2006.201.10:57:03.00:"st=record 2006.201.10:57:03.00:data_valid=on 2006.201.10:57:03.00:midob 2006.201.10:57:04.14/onsource/TRACKING 2006.201.10:57:04.14/wx/21.46,1003.6,99 2006.201.10:57:04.29/cable/+6.4689E-03 2006.201.10:57:05.38/va/01,08,usb,yes,27,30 2006.201.10:57:05.38/va/02,07,usb,yes,30,30 2006.201.10:57:05.38/va/03,08,usb,yes,27,28 2006.201.10:57:05.38/va/04,07,usb,yes,30,32 2006.201.10:57:05.38/va/05,04,usb,yes,27,27 2006.201.10:57:05.38/va/06,05,usb,yes,27,27 2006.201.10:57:05.38/va/07,05,usb,yes,26,27 2006.201.10:57:05.38/va/08,04,usb,yes,26,31 2006.201.10:57:05.61/valo/01,524.99,yes,locked 2006.201.10:57:05.61/valo/02,534.99,yes,locked 2006.201.10:57:05.61/valo/03,564.99,yes,locked 2006.201.10:57:05.61/valo/04,624.99,yes,locked 2006.201.10:57:05.61/valo/05,734.99,yes,locked 2006.201.10:57:05.61/valo/06,814.99,yes,locked 2006.201.10:57:05.61/valo/07,864.99,yes,locked 2006.201.10:57:05.61/valo/08,884.99,yes,locked 2006.201.10:57:06.70/vb/01,04,usb,yes,28,26 2006.201.10:57:06.70/vb/02,05,usb,yes,27,27 2006.201.10:57:06.70/vb/03,04,usb,yes,28,30 2006.201.10:57:06.70/vb/04,05,usb,yes,28,27 2006.201.10:57:06.70/vb/05,04,usb,yes,24,27 2006.201.10:57:06.70/vb/06,04,usb,yes,29,25 2006.201.10:57:06.70/vb/07,04,usb,yes,29,28 2006.201.10:57:06.70/vb/08,04,usb,yes,26,29 2006.201.10:57:06.94/vblo/01,629.99,yes,locked 2006.201.10:57:06.94/vblo/02,634.99,yes,locked 2006.201.10:57:06.94/vblo/03,649.99,yes,locked 2006.201.10:57:06.94/vblo/04,679.99,yes,locked 2006.201.10:57:06.94/vblo/05,709.99,yes,locked 2006.201.10:57:06.94/vblo/06,719.99,yes,locked 2006.201.10:57:06.94/vblo/07,734.99,yes,locked 2006.201.10:57:06.94/vblo/08,744.99,yes,locked 2006.201.10:57:07.09/vabw/8 2006.201.10:57:07.24/vbbw/8 2006.201.10:57:07.33/xfe/off,on,15.2 2006.201.10:57:07.70/ifatt/23,28,28,28 2006.201.10:57:08.06/fmout-gps/S +4.56E-07 2006.201.10:57:08.12:!2006.201.11:03:13 2006.201.11:03:13.00:data_valid=off 2006.201.11:03:13.00:"et 2006.201.11:03:13.00:!+3s 2006.201.11:03:16.02:"tape 2006.201.11:03:16.02:postob 2006.201.11:03:16.09/cable/+6.4718E-03 2006.201.11:03:16.09/wx/21.42,1003.8,99 2006.201.11:03:16.16/fmout-gps/S +4.59E-07 2006.201.11:03:16.16:scan_name=201-1108,jd0607,40 2006.201.11:03:16.17:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.201.11:03:18.14#flagr#flagr/antenna,new-source 2006.201.11:03:18.14:checkk5 2006.201.11:03:18.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:03:18.93/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:03:19.31/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:03:19.69/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:03:20.06/chk_obsdata//k5ts1/T2011057??a.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.201.11:03:20.42/chk_obsdata//k5ts2/T2011057??b.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.201.11:03:20.78/chk_obsdata//k5ts3/T2011057??c.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.201.11:03:21.14/chk_obsdata//k5ts4/T2011057??d.dat file size is correct (nominal:1480MB, actual:1476MB). 2006.201.11:03:21.83/k5log//k5ts1_log_newline 2006.201.11:03:22.51/k5log//k5ts2_log_newline 2006.201.11:03:23.19/k5log//k5ts3_log_newline 2006.201.11:03:23.88/k5log//k5ts4_log_newline 2006.201.11:03:23.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:03:23.90:setupk4=1 2006.201.11:03:23.90$setupk4/echo=on 2006.201.11:03:23.90$setupk4/pcalon 2006.201.11:03:23.90$pcalon/"no phase cal control is implemented here 2006.201.11:03:23.90$setupk4/"tpicd=stop 2006.201.11:03:23.90$setupk4/"rec=synch_on 2006.201.11:03:23.90$setupk4/"rec_mode=128 2006.201.11:03:23.90$setupk4/!* 2006.201.11:03:23.90$setupk4/recpk4 2006.201.11:03:23.90$recpk4/recpatch= 2006.201.11:03:23.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:03:23.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:03:23.91$setupk4/vck44 2006.201.11:03:23.91$vck44/valo=1,524.99 2006.201.11:03:23.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.11:03:23.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.11:03:23.91#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:23.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:23.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:23.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:23.91#ibcon#enter wrdev, iclass 13, count 0 2006.201.11:03:23.91#ibcon#first serial, iclass 13, count 0 2006.201.11:03:23.91#ibcon#enter sib2, iclass 13, count 0 2006.201.11:03:23.91#ibcon#flushed, iclass 13, count 0 2006.201.11:03:23.91#ibcon#about to write, iclass 13, count 0 2006.201.11:03:23.91#ibcon#wrote, iclass 13, count 0 2006.201.11:03:23.91#ibcon#about to read 3, iclass 13, count 0 2006.201.11:03:23.94#ibcon#read 3, iclass 13, count 0 2006.201.11:03:23.94#ibcon#about to read 4, iclass 13, count 0 2006.201.11:03:23.94#ibcon#read 4, iclass 13, count 0 2006.201.11:03:23.94#ibcon#about to read 5, iclass 13, count 0 2006.201.11:03:23.94#ibcon#read 5, iclass 13, count 0 2006.201.11:03:23.94#ibcon#about to read 6, iclass 13, count 0 2006.201.11:03:23.94#ibcon#read 6, iclass 13, count 0 2006.201.11:03:23.94#ibcon#end of sib2, iclass 13, count 0 2006.201.11:03:23.94#ibcon#*mode == 0, iclass 13, count 0 2006.201.11:03:23.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.11:03:23.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:03:23.94#ibcon#*before write, iclass 13, count 0 2006.201.11:03:23.94#ibcon#enter sib2, iclass 13, count 0 2006.201.11:03:23.94#ibcon#flushed, iclass 13, count 0 2006.201.11:03:23.94#ibcon#about to write, iclass 13, count 0 2006.201.11:03:23.94#ibcon#wrote, iclass 13, count 0 2006.201.11:03:23.94#ibcon#about to read 3, iclass 13, count 0 2006.201.11:03:24.00#ibcon#read 3, iclass 13, count 0 2006.201.11:03:24.00#ibcon#about to read 4, iclass 13, count 0 2006.201.11:03:24.00#ibcon#read 4, iclass 13, count 0 2006.201.11:03:24.00#ibcon#about to read 5, iclass 13, count 0 2006.201.11:03:24.00#ibcon#read 5, iclass 13, count 0 2006.201.11:03:24.00#ibcon#about to read 6, iclass 13, count 0 2006.201.11:03:24.00#ibcon#read 6, iclass 13, count 0 2006.201.11:03:24.00#ibcon#end of sib2, iclass 13, count 0 2006.201.11:03:24.00#ibcon#*after write, iclass 13, count 0 2006.201.11:03:24.00#ibcon#*before return 0, iclass 13, count 0 2006.201.11:03:24.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:24.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:24.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.11:03:24.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.11:03:24.00$vck44/va=1,8 2006.201.11:03:24.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.11:03:24.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.11:03:24.00#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:24.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:24.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:24.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:24.00#ibcon#enter wrdev, iclass 15, count 2 2006.201.11:03:24.00#ibcon#first serial, iclass 15, count 2 2006.201.11:03:24.00#ibcon#enter sib2, iclass 15, count 2 2006.201.11:03:24.00#ibcon#flushed, iclass 15, count 2 2006.201.11:03:24.00#ibcon#about to write, iclass 15, count 2 2006.201.11:03:24.00#ibcon#wrote, iclass 15, count 2 2006.201.11:03:24.00#ibcon#about to read 3, iclass 15, count 2 2006.201.11:03:24.02#ibcon#read 3, iclass 15, count 2 2006.201.11:03:24.02#ibcon#about to read 4, iclass 15, count 2 2006.201.11:03:24.02#ibcon#read 4, iclass 15, count 2 2006.201.11:03:24.02#ibcon#about to read 5, iclass 15, count 2 2006.201.11:03:24.02#ibcon#read 5, iclass 15, count 2 2006.201.11:03:24.02#ibcon#about to read 6, iclass 15, count 2 2006.201.11:03:24.02#ibcon#read 6, iclass 15, count 2 2006.201.11:03:24.02#ibcon#end of sib2, iclass 15, count 2 2006.201.11:03:24.02#ibcon#*mode == 0, iclass 15, count 2 2006.201.11:03:24.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.11:03:24.02#ibcon#[25=AT01-08\r\n] 2006.201.11:03:24.02#ibcon#*before write, iclass 15, count 2 2006.201.11:03:24.02#ibcon#enter sib2, iclass 15, count 2 2006.201.11:03:24.02#ibcon#flushed, iclass 15, count 2 2006.201.11:03:24.02#ibcon#about to write, iclass 15, count 2 2006.201.11:03:24.02#ibcon#wrote, iclass 15, count 2 2006.201.11:03:24.02#ibcon#about to read 3, iclass 15, count 2 2006.201.11:03:24.06#ibcon#read 3, iclass 15, count 2 2006.201.11:03:24.06#ibcon#about to read 4, iclass 15, count 2 2006.201.11:03:24.06#ibcon#read 4, iclass 15, count 2 2006.201.11:03:24.06#ibcon#about to read 5, iclass 15, count 2 2006.201.11:03:24.06#ibcon#read 5, iclass 15, count 2 2006.201.11:03:24.06#ibcon#about to read 6, iclass 15, count 2 2006.201.11:03:24.06#ibcon#read 6, iclass 15, count 2 2006.201.11:03:24.06#ibcon#end of sib2, iclass 15, count 2 2006.201.11:03:24.06#ibcon#*after write, iclass 15, count 2 2006.201.11:03:24.06#ibcon#*before return 0, iclass 15, count 2 2006.201.11:03:24.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:24.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:24.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.11:03:24.06#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:24.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:24.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:24.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:24.18#ibcon#enter wrdev, iclass 15, count 0 2006.201.11:03:24.18#ibcon#first serial, iclass 15, count 0 2006.201.11:03:24.18#ibcon#enter sib2, iclass 15, count 0 2006.201.11:03:24.18#ibcon#flushed, iclass 15, count 0 2006.201.11:03:24.18#ibcon#about to write, iclass 15, count 0 2006.201.11:03:24.18#ibcon#wrote, iclass 15, count 0 2006.201.11:03:24.18#ibcon#about to read 3, iclass 15, count 0 2006.201.11:03:24.21#ibcon#read 3, iclass 15, count 0 2006.201.11:03:24.21#ibcon#about to read 4, iclass 15, count 0 2006.201.11:03:24.21#ibcon#read 4, iclass 15, count 0 2006.201.11:03:24.21#ibcon#about to read 5, iclass 15, count 0 2006.201.11:03:24.21#ibcon#read 5, iclass 15, count 0 2006.201.11:03:24.21#ibcon#about to read 6, iclass 15, count 0 2006.201.11:03:24.21#ibcon#read 6, iclass 15, count 0 2006.201.11:03:24.21#ibcon#end of sib2, iclass 15, count 0 2006.201.11:03:24.21#ibcon#*mode == 0, iclass 15, count 0 2006.201.11:03:24.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.11:03:24.21#ibcon#[25=USB\r\n] 2006.201.11:03:24.21#ibcon#*before write, iclass 15, count 0 2006.201.11:03:24.21#ibcon#enter sib2, iclass 15, count 0 2006.201.11:03:24.21#ibcon#flushed, iclass 15, count 0 2006.201.11:03:24.21#ibcon#about to write, iclass 15, count 0 2006.201.11:03:24.21#ibcon#wrote, iclass 15, count 0 2006.201.11:03:24.21#ibcon#about to read 3, iclass 15, count 0 2006.201.11:03:24.24#ibcon#read 3, iclass 15, count 0 2006.201.11:03:24.24#ibcon#about to read 4, iclass 15, count 0 2006.201.11:03:24.24#ibcon#read 4, iclass 15, count 0 2006.201.11:03:24.24#ibcon#about to read 5, iclass 15, count 0 2006.201.11:03:24.24#ibcon#read 5, iclass 15, count 0 2006.201.11:03:24.24#ibcon#about to read 6, iclass 15, count 0 2006.201.11:03:24.24#ibcon#read 6, iclass 15, count 0 2006.201.11:03:24.24#ibcon#end of sib2, iclass 15, count 0 2006.201.11:03:24.24#ibcon#*after write, iclass 15, count 0 2006.201.11:03:24.24#ibcon#*before return 0, iclass 15, count 0 2006.201.11:03:24.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:24.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:24.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.11:03:24.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.11:03:24.24$vck44/valo=2,534.99 2006.201.11:03:24.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.11:03:24.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.11:03:24.24#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:24.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:24.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:24.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:24.24#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:03:24.24#ibcon#first serial, iclass 17, count 0 2006.201.11:03:24.24#ibcon#enter sib2, iclass 17, count 0 2006.201.11:03:24.24#ibcon#flushed, iclass 17, count 0 2006.201.11:03:24.24#ibcon#about to write, iclass 17, count 0 2006.201.11:03:24.24#ibcon#wrote, iclass 17, count 0 2006.201.11:03:24.24#ibcon#about to read 3, iclass 17, count 0 2006.201.11:03:24.26#ibcon#read 3, iclass 17, count 0 2006.201.11:03:24.26#ibcon#about to read 4, iclass 17, count 0 2006.201.11:03:24.26#ibcon#read 4, iclass 17, count 0 2006.201.11:03:24.26#ibcon#about to read 5, iclass 17, count 0 2006.201.11:03:24.26#ibcon#read 5, iclass 17, count 0 2006.201.11:03:24.26#ibcon#about to read 6, iclass 17, count 0 2006.201.11:03:24.26#ibcon#read 6, iclass 17, count 0 2006.201.11:03:24.26#ibcon#end of sib2, iclass 17, count 0 2006.201.11:03:24.26#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:03:24.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:03:24.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:03:24.26#ibcon#*before write, iclass 17, count 0 2006.201.11:03:24.26#ibcon#enter sib2, iclass 17, count 0 2006.201.11:03:24.26#ibcon#flushed, iclass 17, count 0 2006.201.11:03:24.26#ibcon#about to write, iclass 17, count 0 2006.201.11:03:24.26#ibcon#wrote, iclass 17, count 0 2006.201.11:03:24.26#ibcon#about to read 3, iclass 17, count 0 2006.201.11:03:24.30#ibcon#read 3, iclass 17, count 0 2006.201.11:03:24.30#ibcon#about to read 4, iclass 17, count 0 2006.201.11:03:24.30#ibcon#read 4, iclass 17, count 0 2006.201.11:03:24.30#ibcon#about to read 5, iclass 17, count 0 2006.201.11:03:24.30#ibcon#read 5, iclass 17, count 0 2006.201.11:03:24.30#ibcon#about to read 6, iclass 17, count 0 2006.201.11:03:24.30#ibcon#read 6, iclass 17, count 0 2006.201.11:03:24.30#ibcon#end of sib2, iclass 17, count 0 2006.201.11:03:24.30#ibcon#*after write, iclass 17, count 0 2006.201.11:03:24.30#ibcon#*before return 0, iclass 17, count 0 2006.201.11:03:24.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:24.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:24.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:03:24.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:03:24.30$vck44/va=2,7 2006.201.11:03:24.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.11:03:24.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.11:03:24.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:24.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:24.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:24.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:24.36#ibcon#enter wrdev, iclass 19, count 2 2006.201.11:03:24.36#ibcon#first serial, iclass 19, count 2 2006.201.11:03:24.36#ibcon#enter sib2, iclass 19, count 2 2006.201.11:03:24.36#ibcon#flushed, iclass 19, count 2 2006.201.11:03:24.36#ibcon#about to write, iclass 19, count 2 2006.201.11:03:24.36#ibcon#wrote, iclass 19, count 2 2006.201.11:03:24.36#ibcon#about to read 3, iclass 19, count 2 2006.201.11:03:24.38#ibcon#read 3, iclass 19, count 2 2006.201.11:03:24.38#ibcon#about to read 4, iclass 19, count 2 2006.201.11:03:24.38#ibcon#read 4, iclass 19, count 2 2006.201.11:03:24.38#ibcon#about to read 5, iclass 19, count 2 2006.201.11:03:24.38#ibcon#read 5, iclass 19, count 2 2006.201.11:03:24.38#ibcon#about to read 6, iclass 19, count 2 2006.201.11:03:24.38#ibcon#read 6, iclass 19, count 2 2006.201.11:03:24.38#ibcon#end of sib2, iclass 19, count 2 2006.201.11:03:24.38#ibcon#*mode == 0, iclass 19, count 2 2006.201.11:03:24.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.11:03:24.38#ibcon#[25=AT02-07\r\n] 2006.201.11:03:24.38#ibcon#*before write, iclass 19, count 2 2006.201.11:03:24.38#ibcon#enter sib2, iclass 19, count 2 2006.201.11:03:24.38#ibcon#flushed, iclass 19, count 2 2006.201.11:03:24.38#ibcon#about to write, iclass 19, count 2 2006.201.11:03:24.38#ibcon#wrote, iclass 19, count 2 2006.201.11:03:24.38#ibcon#about to read 3, iclass 19, count 2 2006.201.11:03:24.41#ibcon#read 3, iclass 19, count 2 2006.201.11:03:24.41#ibcon#about to read 4, iclass 19, count 2 2006.201.11:03:24.41#ibcon#read 4, iclass 19, count 2 2006.201.11:03:24.41#ibcon#about to read 5, iclass 19, count 2 2006.201.11:03:24.41#ibcon#read 5, iclass 19, count 2 2006.201.11:03:24.41#ibcon#about to read 6, iclass 19, count 2 2006.201.11:03:24.41#ibcon#read 6, iclass 19, count 2 2006.201.11:03:24.41#ibcon#end of sib2, iclass 19, count 2 2006.201.11:03:24.41#ibcon#*after write, iclass 19, count 2 2006.201.11:03:24.41#ibcon#*before return 0, iclass 19, count 2 2006.201.11:03:24.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:24.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:24.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.11:03:24.41#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:24.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:24.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:24.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:24.53#ibcon#enter wrdev, iclass 19, count 0 2006.201.11:03:24.53#ibcon#first serial, iclass 19, count 0 2006.201.11:03:24.53#ibcon#enter sib2, iclass 19, count 0 2006.201.11:03:24.53#ibcon#flushed, iclass 19, count 0 2006.201.11:03:24.53#ibcon#about to write, iclass 19, count 0 2006.201.11:03:24.53#ibcon#wrote, iclass 19, count 0 2006.201.11:03:24.53#ibcon#about to read 3, iclass 19, count 0 2006.201.11:03:24.55#ibcon#read 3, iclass 19, count 0 2006.201.11:03:24.55#ibcon#about to read 4, iclass 19, count 0 2006.201.11:03:24.55#ibcon#read 4, iclass 19, count 0 2006.201.11:03:24.55#ibcon#about to read 5, iclass 19, count 0 2006.201.11:03:24.55#ibcon#read 5, iclass 19, count 0 2006.201.11:03:24.55#ibcon#about to read 6, iclass 19, count 0 2006.201.11:03:24.55#ibcon#read 6, iclass 19, count 0 2006.201.11:03:24.55#ibcon#end of sib2, iclass 19, count 0 2006.201.11:03:24.55#ibcon#*mode == 0, iclass 19, count 0 2006.201.11:03:24.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.11:03:24.55#ibcon#[25=USB\r\n] 2006.201.11:03:24.55#ibcon#*before write, iclass 19, count 0 2006.201.11:03:24.55#ibcon#enter sib2, iclass 19, count 0 2006.201.11:03:24.55#ibcon#flushed, iclass 19, count 0 2006.201.11:03:24.55#ibcon#about to write, iclass 19, count 0 2006.201.11:03:24.55#ibcon#wrote, iclass 19, count 0 2006.201.11:03:24.55#ibcon#about to read 3, iclass 19, count 0 2006.201.11:03:24.58#ibcon#read 3, iclass 19, count 0 2006.201.11:03:24.58#ibcon#about to read 4, iclass 19, count 0 2006.201.11:03:24.58#ibcon#read 4, iclass 19, count 0 2006.201.11:03:24.58#ibcon#about to read 5, iclass 19, count 0 2006.201.11:03:24.58#ibcon#read 5, iclass 19, count 0 2006.201.11:03:24.58#ibcon#about to read 6, iclass 19, count 0 2006.201.11:03:24.58#ibcon#read 6, iclass 19, count 0 2006.201.11:03:24.58#ibcon#end of sib2, iclass 19, count 0 2006.201.11:03:24.58#ibcon#*after write, iclass 19, count 0 2006.201.11:03:24.58#ibcon#*before return 0, iclass 19, count 0 2006.201.11:03:24.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:24.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:24.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.11:03:24.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.11:03:24.58$vck44/valo=3,564.99 2006.201.11:03:24.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.11:03:24.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.11:03:24.58#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:24.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:24.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:24.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:24.58#ibcon#enter wrdev, iclass 21, count 0 2006.201.11:03:24.58#ibcon#first serial, iclass 21, count 0 2006.201.11:03:24.58#ibcon#enter sib2, iclass 21, count 0 2006.201.11:03:24.58#ibcon#flushed, iclass 21, count 0 2006.201.11:03:24.58#ibcon#about to write, iclass 21, count 0 2006.201.11:03:24.58#ibcon#wrote, iclass 21, count 0 2006.201.11:03:24.58#ibcon#about to read 3, iclass 21, count 0 2006.201.11:03:24.60#ibcon#read 3, iclass 21, count 0 2006.201.11:03:24.60#ibcon#about to read 4, iclass 21, count 0 2006.201.11:03:24.60#ibcon#read 4, iclass 21, count 0 2006.201.11:03:24.60#ibcon#about to read 5, iclass 21, count 0 2006.201.11:03:24.60#ibcon#read 5, iclass 21, count 0 2006.201.11:03:24.60#ibcon#about to read 6, iclass 21, count 0 2006.201.11:03:24.60#ibcon#read 6, iclass 21, count 0 2006.201.11:03:24.60#ibcon#end of sib2, iclass 21, count 0 2006.201.11:03:24.60#ibcon#*mode == 0, iclass 21, count 0 2006.201.11:03:24.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.11:03:24.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:03:24.60#ibcon#*before write, iclass 21, count 0 2006.201.11:03:24.60#ibcon#enter sib2, iclass 21, count 0 2006.201.11:03:24.60#ibcon#flushed, iclass 21, count 0 2006.201.11:03:24.60#ibcon#about to write, iclass 21, count 0 2006.201.11:03:24.60#ibcon#wrote, iclass 21, count 0 2006.201.11:03:24.60#ibcon#about to read 3, iclass 21, count 0 2006.201.11:03:24.64#ibcon#read 3, iclass 21, count 0 2006.201.11:03:24.64#ibcon#about to read 4, iclass 21, count 0 2006.201.11:03:24.64#ibcon#read 4, iclass 21, count 0 2006.201.11:03:24.64#ibcon#about to read 5, iclass 21, count 0 2006.201.11:03:24.64#ibcon#read 5, iclass 21, count 0 2006.201.11:03:24.64#ibcon#about to read 6, iclass 21, count 0 2006.201.11:03:24.64#ibcon#read 6, iclass 21, count 0 2006.201.11:03:24.64#ibcon#end of sib2, iclass 21, count 0 2006.201.11:03:24.64#ibcon#*after write, iclass 21, count 0 2006.201.11:03:24.64#ibcon#*before return 0, iclass 21, count 0 2006.201.11:03:24.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:24.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:24.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.11:03:24.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.11:03:24.64$vck44/va=3,8 2006.201.11:03:24.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.11:03:24.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.11:03:24.64#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:24.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:24.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:24.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:24.70#ibcon#enter wrdev, iclass 23, count 2 2006.201.11:03:24.70#ibcon#first serial, iclass 23, count 2 2006.201.11:03:24.70#ibcon#enter sib2, iclass 23, count 2 2006.201.11:03:24.70#ibcon#flushed, iclass 23, count 2 2006.201.11:03:24.70#ibcon#about to write, iclass 23, count 2 2006.201.11:03:24.70#ibcon#wrote, iclass 23, count 2 2006.201.11:03:24.70#ibcon#about to read 3, iclass 23, count 2 2006.201.11:03:24.72#ibcon#read 3, iclass 23, count 2 2006.201.11:03:24.72#ibcon#about to read 4, iclass 23, count 2 2006.201.11:03:24.72#ibcon#read 4, iclass 23, count 2 2006.201.11:03:24.72#ibcon#about to read 5, iclass 23, count 2 2006.201.11:03:24.72#ibcon#read 5, iclass 23, count 2 2006.201.11:03:24.72#ibcon#about to read 6, iclass 23, count 2 2006.201.11:03:24.72#ibcon#read 6, iclass 23, count 2 2006.201.11:03:24.72#ibcon#end of sib2, iclass 23, count 2 2006.201.11:03:24.72#ibcon#*mode == 0, iclass 23, count 2 2006.201.11:03:24.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.11:03:24.72#ibcon#[25=AT03-08\r\n] 2006.201.11:03:24.72#ibcon#*before write, iclass 23, count 2 2006.201.11:03:24.72#ibcon#enter sib2, iclass 23, count 2 2006.201.11:03:24.72#ibcon#flushed, iclass 23, count 2 2006.201.11:03:24.72#ibcon#about to write, iclass 23, count 2 2006.201.11:03:24.72#ibcon#wrote, iclass 23, count 2 2006.201.11:03:24.72#ibcon#about to read 3, iclass 23, count 2 2006.201.11:03:24.75#ibcon#read 3, iclass 23, count 2 2006.201.11:03:24.75#ibcon#about to read 4, iclass 23, count 2 2006.201.11:03:24.75#ibcon#read 4, iclass 23, count 2 2006.201.11:03:24.75#ibcon#about to read 5, iclass 23, count 2 2006.201.11:03:24.75#ibcon#read 5, iclass 23, count 2 2006.201.11:03:24.75#ibcon#about to read 6, iclass 23, count 2 2006.201.11:03:24.75#ibcon#read 6, iclass 23, count 2 2006.201.11:03:24.75#ibcon#end of sib2, iclass 23, count 2 2006.201.11:03:24.75#ibcon#*after write, iclass 23, count 2 2006.201.11:03:24.75#ibcon#*before return 0, iclass 23, count 2 2006.201.11:03:24.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:24.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:24.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.11:03:24.75#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:24.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:24.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:24.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:24.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.11:03:24.87#ibcon#first serial, iclass 23, count 0 2006.201.11:03:24.87#ibcon#enter sib2, iclass 23, count 0 2006.201.11:03:24.87#ibcon#flushed, iclass 23, count 0 2006.201.11:03:24.87#ibcon#about to write, iclass 23, count 0 2006.201.11:03:24.87#ibcon#wrote, iclass 23, count 0 2006.201.11:03:24.87#ibcon#about to read 3, iclass 23, count 0 2006.201.11:03:24.89#ibcon#read 3, iclass 23, count 0 2006.201.11:03:24.89#ibcon#about to read 4, iclass 23, count 0 2006.201.11:03:24.89#ibcon#read 4, iclass 23, count 0 2006.201.11:03:24.89#ibcon#about to read 5, iclass 23, count 0 2006.201.11:03:24.89#ibcon#read 5, iclass 23, count 0 2006.201.11:03:24.89#ibcon#about to read 6, iclass 23, count 0 2006.201.11:03:24.89#ibcon#read 6, iclass 23, count 0 2006.201.11:03:24.89#ibcon#end of sib2, iclass 23, count 0 2006.201.11:03:24.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.11:03:24.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.11:03:24.89#ibcon#[25=USB\r\n] 2006.201.11:03:24.89#ibcon#*before write, iclass 23, count 0 2006.201.11:03:24.89#ibcon#enter sib2, iclass 23, count 0 2006.201.11:03:24.89#ibcon#flushed, iclass 23, count 0 2006.201.11:03:24.89#ibcon#about to write, iclass 23, count 0 2006.201.11:03:24.89#ibcon#wrote, iclass 23, count 0 2006.201.11:03:24.89#ibcon#about to read 3, iclass 23, count 0 2006.201.11:03:24.92#ibcon#read 3, iclass 23, count 0 2006.201.11:03:24.92#ibcon#about to read 4, iclass 23, count 0 2006.201.11:03:24.92#ibcon#read 4, iclass 23, count 0 2006.201.11:03:24.92#ibcon#about to read 5, iclass 23, count 0 2006.201.11:03:24.92#ibcon#read 5, iclass 23, count 0 2006.201.11:03:24.92#ibcon#about to read 6, iclass 23, count 0 2006.201.11:03:24.92#ibcon#read 6, iclass 23, count 0 2006.201.11:03:24.92#ibcon#end of sib2, iclass 23, count 0 2006.201.11:03:24.92#ibcon#*after write, iclass 23, count 0 2006.201.11:03:24.92#ibcon#*before return 0, iclass 23, count 0 2006.201.11:03:24.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:24.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:24.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.11:03:24.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.11:03:24.92$vck44/valo=4,624.99 2006.201.11:03:24.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.11:03:24.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.11:03:24.92#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:24.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:03:24.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:03:24.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:03:24.92#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:03:24.92#ibcon#first serial, iclass 26, count 0 2006.201.11:03:24.92#ibcon#enter sib2, iclass 26, count 0 2006.201.11:03:24.92#ibcon#flushed, iclass 26, count 0 2006.201.11:03:24.92#ibcon#about to write, iclass 26, count 0 2006.201.11:03:24.92#ibcon#wrote, iclass 26, count 0 2006.201.11:03:24.92#ibcon#about to read 3, iclass 26, count 0 2006.201.11:03:24.94#ibcon#read 3, iclass 26, count 0 2006.201.11:03:24.94#ibcon#about to read 4, iclass 26, count 0 2006.201.11:03:24.94#ibcon#read 4, iclass 26, count 0 2006.201.11:03:24.94#ibcon#about to read 5, iclass 26, count 0 2006.201.11:03:24.94#ibcon#read 5, iclass 26, count 0 2006.201.11:03:24.94#ibcon#about to read 6, iclass 26, count 0 2006.201.11:03:24.94#ibcon#read 6, iclass 26, count 0 2006.201.11:03:24.94#ibcon#end of sib2, iclass 26, count 0 2006.201.11:03:24.94#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:03:24.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:03:24.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:03:24.94#ibcon#*before write, iclass 26, count 0 2006.201.11:03:24.94#ibcon#enter sib2, iclass 26, count 0 2006.201.11:03:24.94#ibcon#flushed, iclass 26, count 0 2006.201.11:03:24.94#ibcon#about to write, iclass 26, count 0 2006.201.11:03:24.94#ibcon#wrote, iclass 26, count 0 2006.201.11:03:24.94#ibcon#about to read 3, iclass 26, count 0 2006.201.11:03:24.98#ibcon#read 3, iclass 26, count 0 2006.201.11:03:24.98#ibcon#about to read 4, iclass 26, count 0 2006.201.11:03:24.98#ibcon#read 4, iclass 26, count 0 2006.201.11:03:24.98#ibcon#about to read 5, iclass 26, count 0 2006.201.11:03:24.98#ibcon#read 5, iclass 26, count 0 2006.201.11:03:24.98#ibcon#about to read 6, iclass 26, count 0 2006.201.11:03:24.98#ibcon#read 6, iclass 26, count 0 2006.201.11:03:24.98#ibcon#end of sib2, iclass 26, count 0 2006.201.11:03:24.98#ibcon#*after write, iclass 26, count 0 2006.201.11:03:24.98#ibcon#*before return 0, iclass 26, count 0 2006.201.11:03:24.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:03:24.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:03:24.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:03:24.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:03:24.98$vck44/va=4,7 2006.201.11:03:24.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.11:03:24.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.11:03:24.98#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:24.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:03:25.03#abcon#<5=/04 1.6 2.8 21.42 991003.8\r\n> 2006.201.11:03:25.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:03:25.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:03:25.04#ibcon#enter wrdev, iclass 28, count 2 2006.201.11:03:25.04#ibcon#first serial, iclass 28, count 2 2006.201.11:03:25.04#ibcon#enter sib2, iclass 28, count 2 2006.201.11:03:25.04#ibcon#flushed, iclass 28, count 2 2006.201.11:03:25.04#ibcon#about to write, iclass 28, count 2 2006.201.11:03:25.04#ibcon#wrote, iclass 28, count 2 2006.201.11:03:25.04#ibcon#about to read 3, iclass 28, count 2 2006.201.11:03:25.05#abcon#{5=INTERFACE CLEAR} 2006.201.11:03:25.06#ibcon#read 3, iclass 28, count 2 2006.201.11:03:25.06#ibcon#about to read 4, iclass 28, count 2 2006.201.11:03:25.06#ibcon#read 4, iclass 28, count 2 2006.201.11:03:25.06#ibcon#about to read 5, iclass 28, count 2 2006.201.11:03:25.06#ibcon#read 5, iclass 28, count 2 2006.201.11:03:25.06#ibcon#about to read 6, iclass 28, count 2 2006.201.11:03:25.06#ibcon#read 6, iclass 28, count 2 2006.201.11:03:25.06#ibcon#end of sib2, iclass 28, count 2 2006.201.11:03:25.06#ibcon#*mode == 0, iclass 28, count 2 2006.201.11:03:25.06#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.11:03:25.06#ibcon#[25=AT04-07\r\n] 2006.201.11:03:25.06#ibcon#*before write, iclass 28, count 2 2006.201.11:03:25.06#ibcon#enter sib2, iclass 28, count 2 2006.201.11:03:25.06#ibcon#flushed, iclass 28, count 2 2006.201.11:03:25.06#ibcon#about to write, iclass 28, count 2 2006.201.11:03:25.06#ibcon#wrote, iclass 28, count 2 2006.201.11:03:25.06#ibcon#about to read 3, iclass 28, count 2 2006.201.11:03:25.09#ibcon#read 3, iclass 28, count 2 2006.201.11:03:25.09#ibcon#about to read 4, iclass 28, count 2 2006.201.11:03:25.09#ibcon#read 4, iclass 28, count 2 2006.201.11:03:25.09#ibcon#about to read 5, iclass 28, count 2 2006.201.11:03:25.09#ibcon#read 5, iclass 28, count 2 2006.201.11:03:25.09#ibcon#about to read 6, iclass 28, count 2 2006.201.11:03:25.09#ibcon#read 6, iclass 28, count 2 2006.201.11:03:25.09#ibcon#end of sib2, iclass 28, count 2 2006.201.11:03:25.09#ibcon#*after write, iclass 28, count 2 2006.201.11:03:25.09#ibcon#*before return 0, iclass 28, count 2 2006.201.11:03:25.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:03:25.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:03:25.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.11:03:25.09#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:25.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:03:25.11#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:03:25.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:03:25.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:03:25.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:03:25.21#ibcon#first serial, iclass 28, count 0 2006.201.11:03:25.21#ibcon#enter sib2, iclass 28, count 0 2006.201.11:03:25.21#ibcon#flushed, iclass 28, count 0 2006.201.11:03:25.21#ibcon#about to write, iclass 28, count 0 2006.201.11:03:25.21#ibcon#wrote, iclass 28, count 0 2006.201.11:03:25.21#ibcon#about to read 3, iclass 28, count 0 2006.201.11:03:25.23#ibcon#read 3, iclass 28, count 0 2006.201.11:03:25.23#ibcon#about to read 4, iclass 28, count 0 2006.201.11:03:25.23#ibcon#read 4, iclass 28, count 0 2006.201.11:03:25.23#ibcon#about to read 5, iclass 28, count 0 2006.201.11:03:25.23#ibcon#read 5, iclass 28, count 0 2006.201.11:03:25.23#ibcon#about to read 6, iclass 28, count 0 2006.201.11:03:25.23#ibcon#read 6, iclass 28, count 0 2006.201.11:03:25.23#ibcon#end of sib2, iclass 28, count 0 2006.201.11:03:25.23#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:03:25.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:03:25.23#ibcon#[25=USB\r\n] 2006.201.11:03:25.23#ibcon#*before write, iclass 28, count 0 2006.201.11:03:25.23#ibcon#enter sib2, iclass 28, count 0 2006.201.11:03:25.23#ibcon#flushed, iclass 28, count 0 2006.201.11:03:25.23#ibcon#about to write, iclass 28, count 0 2006.201.11:03:25.23#ibcon#wrote, iclass 28, count 0 2006.201.11:03:25.23#ibcon#about to read 3, iclass 28, count 0 2006.201.11:03:25.26#ibcon#read 3, iclass 28, count 0 2006.201.11:03:25.26#ibcon#about to read 4, iclass 28, count 0 2006.201.11:03:25.26#ibcon#read 4, iclass 28, count 0 2006.201.11:03:25.26#ibcon#about to read 5, iclass 28, count 0 2006.201.11:03:25.26#ibcon#read 5, iclass 28, count 0 2006.201.11:03:25.26#ibcon#about to read 6, iclass 28, count 0 2006.201.11:03:25.26#ibcon#read 6, iclass 28, count 0 2006.201.11:03:25.26#ibcon#end of sib2, iclass 28, count 0 2006.201.11:03:25.26#ibcon#*after write, iclass 28, count 0 2006.201.11:03:25.26#ibcon#*before return 0, iclass 28, count 0 2006.201.11:03:25.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:03:25.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:03:25.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:03:25.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:03:25.26$vck44/valo=5,734.99 2006.201.11:03:25.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.11:03:25.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.11:03:25.26#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:25.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:25.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:25.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:25.26#ibcon#enter wrdev, iclass 33, count 0 2006.201.11:03:25.26#ibcon#first serial, iclass 33, count 0 2006.201.11:03:25.26#ibcon#enter sib2, iclass 33, count 0 2006.201.11:03:25.26#ibcon#flushed, iclass 33, count 0 2006.201.11:03:25.26#ibcon#about to write, iclass 33, count 0 2006.201.11:03:25.26#ibcon#wrote, iclass 33, count 0 2006.201.11:03:25.26#ibcon#about to read 3, iclass 33, count 0 2006.201.11:03:25.28#ibcon#read 3, iclass 33, count 0 2006.201.11:03:25.28#ibcon#about to read 4, iclass 33, count 0 2006.201.11:03:25.28#ibcon#read 4, iclass 33, count 0 2006.201.11:03:25.28#ibcon#about to read 5, iclass 33, count 0 2006.201.11:03:25.28#ibcon#read 5, iclass 33, count 0 2006.201.11:03:25.28#ibcon#about to read 6, iclass 33, count 0 2006.201.11:03:25.28#ibcon#read 6, iclass 33, count 0 2006.201.11:03:25.28#ibcon#end of sib2, iclass 33, count 0 2006.201.11:03:25.28#ibcon#*mode == 0, iclass 33, count 0 2006.201.11:03:25.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.11:03:25.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:03:25.28#ibcon#*before write, iclass 33, count 0 2006.201.11:03:25.28#ibcon#enter sib2, iclass 33, count 0 2006.201.11:03:25.28#ibcon#flushed, iclass 33, count 0 2006.201.11:03:25.28#ibcon#about to write, iclass 33, count 0 2006.201.11:03:25.28#ibcon#wrote, iclass 33, count 0 2006.201.11:03:25.28#ibcon#about to read 3, iclass 33, count 0 2006.201.11:03:25.32#ibcon#read 3, iclass 33, count 0 2006.201.11:03:25.32#ibcon#about to read 4, iclass 33, count 0 2006.201.11:03:25.32#ibcon#read 4, iclass 33, count 0 2006.201.11:03:25.32#ibcon#about to read 5, iclass 33, count 0 2006.201.11:03:25.32#ibcon#read 5, iclass 33, count 0 2006.201.11:03:25.32#ibcon#about to read 6, iclass 33, count 0 2006.201.11:03:25.32#ibcon#read 6, iclass 33, count 0 2006.201.11:03:25.32#ibcon#end of sib2, iclass 33, count 0 2006.201.11:03:25.32#ibcon#*after write, iclass 33, count 0 2006.201.11:03:25.32#ibcon#*before return 0, iclass 33, count 0 2006.201.11:03:25.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:25.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:25.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.11:03:25.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.11:03:25.32$vck44/va=5,4 2006.201.11:03:25.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.11:03:25.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.11:03:25.32#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:25.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:25.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:25.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:25.38#ibcon#enter wrdev, iclass 35, count 2 2006.201.11:03:25.38#ibcon#first serial, iclass 35, count 2 2006.201.11:03:25.38#ibcon#enter sib2, iclass 35, count 2 2006.201.11:03:25.38#ibcon#flushed, iclass 35, count 2 2006.201.11:03:25.38#ibcon#about to write, iclass 35, count 2 2006.201.11:03:25.38#ibcon#wrote, iclass 35, count 2 2006.201.11:03:25.38#ibcon#about to read 3, iclass 35, count 2 2006.201.11:03:25.40#ibcon#read 3, iclass 35, count 2 2006.201.11:03:25.40#ibcon#about to read 4, iclass 35, count 2 2006.201.11:03:25.40#ibcon#read 4, iclass 35, count 2 2006.201.11:03:25.40#ibcon#about to read 5, iclass 35, count 2 2006.201.11:03:25.40#ibcon#read 5, iclass 35, count 2 2006.201.11:03:25.40#ibcon#about to read 6, iclass 35, count 2 2006.201.11:03:25.40#ibcon#read 6, iclass 35, count 2 2006.201.11:03:25.40#ibcon#end of sib2, iclass 35, count 2 2006.201.11:03:25.40#ibcon#*mode == 0, iclass 35, count 2 2006.201.11:03:25.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.11:03:25.40#ibcon#[25=AT05-04\r\n] 2006.201.11:03:25.40#ibcon#*before write, iclass 35, count 2 2006.201.11:03:25.40#ibcon#enter sib2, iclass 35, count 2 2006.201.11:03:25.40#ibcon#flushed, iclass 35, count 2 2006.201.11:03:25.40#ibcon#about to write, iclass 35, count 2 2006.201.11:03:25.40#ibcon#wrote, iclass 35, count 2 2006.201.11:03:25.40#ibcon#about to read 3, iclass 35, count 2 2006.201.11:03:25.43#ibcon#read 3, iclass 35, count 2 2006.201.11:03:25.43#ibcon#about to read 4, iclass 35, count 2 2006.201.11:03:25.43#ibcon#read 4, iclass 35, count 2 2006.201.11:03:25.43#ibcon#about to read 5, iclass 35, count 2 2006.201.11:03:25.43#ibcon#read 5, iclass 35, count 2 2006.201.11:03:25.43#ibcon#about to read 6, iclass 35, count 2 2006.201.11:03:25.43#ibcon#read 6, iclass 35, count 2 2006.201.11:03:25.43#ibcon#end of sib2, iclass 35, count 2 2006.201.11:03:25.43#ibcon#*after write, iclass 35, count 2 2006.201.11:03:25.43#ibcon#*before return 0, iclass 35, count 2 2006.201.11:03:25.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:25.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:25.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.11:03:25.43#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:25.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:25.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:25.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:25.55#ibcon#enter wrdev, iclass 35, count 0 2006.201.11:03:25.55#ibcon#first serial, iclass 35, count 0 2006.201.11:03:25.55#ibcon#enter sib2, iclass 35, count 0 2006.201.11:03:25.55#ibcon#flushed, iclass 35, count 0 2006.201.11:03:25.55#ibcon#about to write, iclass 35, count 0 2006.201.11:03:25.55#ibcon#wrote, iclass 35, count 0 2006.201.11:03:25.55#ibcon#about to read 3, iclass 35, count 0 2006.201.11:03:25.57#ibcon#read 3, iclass 35, count 0 2006.201.11:03:25.57#ibcon#about to read 4, iclass 35, count 0 2006.201.11:03:25.57#ibcon#read 4, iclass 35, count 0 2006.201.11:03:25.57#ibcon#about to read 5, iclass 35, count 0 2006.201.11:03:25.57#ibcon#read 5, iclass 35, count 0 2006.201.11:03:25.57#ibcon#about to read 6, iclass 35, count 0 2006.201.11:03:25.57#ibcon#read 6, iclass 35, count 0 2006.201.11:03:25.57#ibcon#end of sib2, iclass 35, count 0 2006.201.11:03:25.57#ibcon#*mode == 0, iclass 35, count 0 2006.201.11:03:25.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.11:03:25.57#ibcon#[25=USB\r\n] 2006.201.11:03:25.57#ibcon#*before write, iclass 35, count 0 2006.201.11:03:25.57#ibcon#enter sib2, iclass 35, count 0 2006.201.11:03:25.57#ibcon#flushed, iclass 35, count 0 2006.201.11:03:25.57#ibcon#about to write, iclass 35, count 0 2006.201.11:03:25.57#ibcon#wrote, iclass 35, count 0 2006.201.11:03:25.57#ibcon#about to read 3, iclass 35, count 0 2006.201.11:03:25.60#ibcon#read 3, iclass 35, count 0 2006.201.11:03:25.60#ibcon#about to read 4, iclass 35, count 0 2006.201.11:03:25.60#ibcon#read 4, iclass 35, count 0 2006.201.11:03:25.60#ibcon#about to read 5, iclass 35, count 0 2006.201.11:03:25.60#ibcon#read 5, iclass 35, count 0 2006.201.11:03:25.60#ibcon#about to read 6, iclass 35, count 0 2006.201.11:03:25.60#ibcon#read 6, iclass 35, count 0 2006.201.11:03:25.60#ibcon#end of sib2, iclass 35, count 0 2006.201.11:03:25.60#ibcon#*after write, iclass 35, count 0 2006.201.11:03:25.60#ibcon#*before return 0, iclass 35, count 0 2006.201.11:03:25.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:25.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:25.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.11:03:25.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.11:03:25.60$vck44/valo=6,814.99 2006.201.11:03:25.60#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.11:03:25.60#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.11:03:25.60#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:25.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:25.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:25.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:25.60#ibcon#enter wrdev, iclass 37, count 0 2006.201.11:03:25.60#ibcon#first serial, iclass 37, count 0 2006.201.11:03:25.60#ibcon#enter sib2, iclass 37, count 0 2006.201.11:03:25.60#ibcon#flushed, iclass 37, count 0 2006.201.11:03:25.60#ibcon#about to write, iclass 37, count 0 2006.201.11:03:25.60#ibcon#wrote, iclass 37, count 0 2006.201.11:03:25.60#ibcon#about to read 3, iclass 37, count 0 2006.201.11:03:25.62#ibcon#read 3, iclass 37, count 0 2006.201.11:03:25.62#ibcon#about to read 4, iclass 37, count 0 2006.201.11:03:25.62#ibcon#read 4, iclass 37, count 0 2006.201.11:03:25.62#ibcon#about to read 5, iclass 37, count 0 2006.201.11:03:25.62#ibcon#read 5, iclass 37, count 0 2006.201.11:03:25.62#ibcon#about to read 6, iclass 37, count 0 2006.201.11:03:25.62#ibcon#read 6, iclass 37, count 0 2006.201.11:03:25.62#ibcon#end of sib2, iclass 37, count 0 2006.201.11:03:25.62#ibcon#*mode == 0, iclass 37, count 0 2006.201.11:03:25.62#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.11:03:25.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:03:25.62#ibcon#*before write, iclass 37, count 0 2006.201.11:03:25.62#ibcon#enter sib2, iclass 37, count 0 2006.201.11:03:25.62#ibcon#flushed, iclass 37, count 0 2006.201.11:03:25.62#ibcon#about to write, iclass 37, count 0 2006.201.11:03:25.62#ibcon#wrote, iclass 37, count 0 2006.201.11:03:25.62#ibcon#about to read 3, iclass 37, count 0 2006.201.11:03:25.66#ibcon#read 3, iclass 37, count 0 2006.201.11:03:25.66#ibcon#about to read 4, iclass 37, count 0 2006.201.11:03:25.66#ibcon#read 4, iclass 37, count 0 2006.201.11:03:25.66#ibcon#about to read 5, iclass 37, count 0 2006.201.11:03:25.66#ibcon#read 5, iclass 37, count 0 2006.201.11:03:25.66#ibcon#about to read 6, iclass 37, count 0 2006.201.11:03:25.66#ibcon#read 6, iclass 37, count 0 2006.201.11:03:25.66#ibcon#end of sib2, iclass 37, count 0 2006.201.11:03:25.66#ibcon#*after write, iclass 37, count 0 2006.201.11:03:25.66#ibcon#*before return 0, iclass 37, count 0 2006.201.11:03:25.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:25.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:25.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.11:03:25.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.11:03:25.66$vck44/va=6,5 2006.201.11:03:25.66#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.11:03:25.66#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.11:03:25.66#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:25.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:25.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:25.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:25.72#ibcon#enter wrdev, iclass 39, count 2 2006.201.11:03:25.72#ibcon#first serial, iclass 39, count 2 2006.201.11:03:25.72#ibcon#enter sib2, iclass 39, count 2 2006.201.11:03:25.72#ibcon#flushed, iclass 39, count 2 2006.201.11:03:25.72#ibcon#about to write, iclass 39, count 2 2006.201.11:03:25.72#ibcon#wrote, iclass 39, count 2 2006.201.11:03:25.72#ibcon#about to read 3, iclass 39, count 2 2006.201.11:03:25.74#ibcon#read 3, iclass 39, count 2 2006.201.11:03:25.74#ibcon#about to read 4, iclass 39, count 2 2006.201.11:03:25.74#ibcon#read 4, iclass 39, count 2 2006.201.11:03:25.74#ibcon#about to read 5, iclass 39, count 2 2006.201.11:03:25.74#ibcon#read 5, iclass 39, count 2 2006.201.11:03:25.74#ibcon#about to read 6, iclass 39, count 2 2006.201.11:03:25.74#ibcon#read 6, iclass 39, count 2 2006.201.11:03:25.74#ibcon#end of sib2, iclass 39, count 2 2006.201.11:03:25.74#ibcon#*mode == 0, iclass 39, count 2 2006.201.11:03:25.74#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.11:03:25.74#ibcon#[25=AT06-05\r\n] 2006.201.11:03:25.74#ibcon#*before write, iclass 39, count 2 2006.201.11:03:25.74#ibcon#enter sib2, iclass 39, count 2 2006.201.11:03:25.74#ibcon#flushed, iclass 39, count 2 2006.201.11:03:25.74#ibcon#about to write, iclass 39, count 2 2006.201.11:03:25.74#ibcon#wrote, iclass 39, count 2 2006.201.11:03:25.74#ibcon#about to read 3, iclass 39, count 2 2006.201.11:03:25.77#ibcon#read 3, iclass 39, count 2 2006.201.11:03:25.77#ibcon#about to read 4, iclass 39, count 2 2006.201.11:03:25.77#ibcon#read 4, iclass 39, count 2 2006.201.11:03:25.77#ibcon#about to read 5, iclass 39, count 2 2006.201.11:03:25.77#ibcon#read 5, iclass 39, count 2 2006.201.11:03:25.77#ibcon#about to read 6, iclass 39, count 2 2006.201.11:03:25.77#ibcon#read 6, iclass 39, count 2 2006.201.11:03:25.77#ibcon#end of sib2, iclass 39, count 2 2006.201.11:03:25.77#ibcon#*after write, iclass 39, count 2 2006.201.11:03:25.77#ibcon#*before return 0, iclass 39, count 2 2006.201.11:03:25.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:25.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:25.77#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.11:03:25.77#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:25.77#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:25.89#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:25.89#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:25.89#ibcon#enter wrdev, iclass 39, count 0 2006.201.11:03:25.89#ibcon#first serial, iclass 39, count 0 2006.201.11:03:25.89#ibcon#enter sib2, iclass 39, count 0 2006.201.11:03:25.89#ibcon#flushed, iclass 39, count 0 2006.201.11:03:25.89#ibcon#about to write, iclass 39, count 0 2006.201.11:03:25.89#ibcon#wrote, iclass 39, count 0 2006.201.11:03:25.89#ibcon#about to read 3, iclass 39, count 0 2006.201.11:03:25.91#ibcon#read 3, iclass 39, count 0 2006.201.11:03:25.91#ibcon#about to read 4, iclass 39, count 0 2006.201.11:03:25.91#ibcon#read 4, iclass 39, count 0 2006.201.11:03:25.91#ibcon#about to read 5, iclass 39, count 0 2006.201.11:03:25.91#ibcon#read 5, iclass 39, count 0 2006.201.11:03:25.91#ibcon#about to read 6, iclass 39, count 0 2006.201.11:03:25.91#ibcon#read 6, iclass 39, count 0 2006.201.11:03:25.91#ibcon#end of sib2, iclass 39, count 0 2006.201.11:03:25.91#ibcon#*mode == 0, iclass 39, count 0 2006.201.11:03:25.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.11:03:25.91#ibcon#[25=USB\r\n] 2006.201.11:03:25.91#ibcon#*before write, iclass 39, count 0 2006.201.11:03:25.91#ibcon#enter sib2, iclass 39, count 0 2006.201.11:03:25.91#ibcon#flushed, iclass 39, count 0 2006.201.11:03:25.91#ibcon#about to write, iclass 39, count 0 2006.201.11:03:25.91#ibcon#wrote, iclass 39, count 0 2006.201.11:03:25.91#ibcon#about to read 3, iclass 39, count 0 2006.201.11:03:25.94#ibcon#read 3, iclass 39, count 0 2006.201.11:03:25.94#ibcon#about to read 4, iclass 39, count 0 2006.201.11:03:25.94#ibcon#read 4, iclass 39, count 0 2006.201.11:03:25.94#ibcon#about to read 5, iclass 39, count 0 2006.201.11:03:25.94#ibcon#read 5, iclass 39, count 0 2006.201.11:03:25.94#ibcon#about to read 6, iclass 39, count 0 2006.201.11:03:25.94#ibcon#read 6, iclass 39, count 0 2006.201.11:03:25.94#ibcon#end of sib2, iclass 39, count 0 2006.201.11:03:25.94#ibcon#*after write, iclass 39, count 0 2006.201.11:03:25.94#ibcon#*before return 0, iclass 39, count 0 2006.201.11:03:25.94#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:25.94#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:25.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.11:03:25.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.11:03:25.94$vck44/valo=7,864.99 2006.201.11:03:25.94#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.11:03:25.94#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.11:03:25.94#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:25.94#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:25.94#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:25.94#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:25.94#ibcon#enter wrdev, iclass 2, count 0 2006.201.11:03:25.94#ibcon#first serial, iclass 2, count 0 2006.201.11:03:25.94#ibcon#enter sib2, iclass 2, count 0 2006.201.11:03:25.94#ibcon#flushed, iclass 2, count 0 2006.201.11:03:25.94#ibcon#about to write, iclass 2, count 0 2006.201.11:03:25.94#ibcon#wrote, iclass 2, count 0 2006.201.11:03:25.94#ibcon#about to read 3, iclass 2, count 0 2006.201.11:03:25.96#ibcon#read 3, iclass 2, count 0 2006.201.11:03:25.96#ibcon#about to read 4, iclass 2, count 0 2006.201.11:03:25.96#ibcon#read 4, iclass 2, count 0 2006.201.11:03:25.96#ibcon#about to read 5, iclass 2, count 0 2006.201.11:03:25.96#ibcon#read 5, iclass 2, count 0 2006.201.11:03:25.96#ibcon#about to read 6, iclass 2, count 0 2006.201.11:03:25.96#ibcon#read 6, iclass 2, count 0 2006.201.11:03:25.96#ibcon#end of sib2, iclass 2, count 0 2006.201.11:03:25.96#ibcon#*mode == 0, iclass 2, count 0 2006.201.11:03:25.96#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.11:03:25.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:03:25.96#ibcon#*before write, iclass 2, count 0 2006.201.11:03:25.96#ibcon#enter sib2, iclass 2, count 0 2006.201.11:03:25.96#ibcon#flushed, iclass 2, count 0 2006.201.11:03:25.96#ibcon#about to write, iclass 2, count 0 2006.201.11:03:25.96#ibcon#wrote, iclass 2, count 0 2006.201.11:03:25.96#ibcon#about to read 3, iclass 2, count 0 2006.201.11:03:26.00#ibcon#read 3, iclass 2, count 0 2006.201.11:03:26.00#ibcon#about to read 4, iclass 2, count 0 2006.201.11:03:26.00#ibcon#read 4, iclass 2, count 0 2006.201.11:03:26.00#ibcon#about to read 5, iclass 2, count 0 2006.201.11:03:26.00#ibcon#read 5, iclass 2, count 0 2006.201.11:03:26.00#ibcon#about to read 6, iclass 2, count 0 2006.201.11:03:26.00#ibcon#read 6, iclass 2, count 0 2006.201.11:03:26.00#ibcon#end of sib2, iclass 2, count 0 2006.201.11:03:26.00#ibcon#*after write, iclass 2, count 0 2006.201.11:03:26.00#ibcon#*before return 0, iclass 2, count 0 2006.201.11:03:26.00#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:26.00#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:26.00#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.11:03:26.00#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.11:03:26.00$vck44/va=7,5 2006.201.11:03:26.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.11:03:26.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.11:03:26.00#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:26.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:26.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:26.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:26.06#ibcon#enter wrdev, iclass 5, count 2 2006.201.11:03:26.06#ibcon#first serial, iclass 5, count 2 2006.201.11:03:26.06#ibcon#enter sib2, iclass 5, count 2 2006.201.11:03:26.06#ibcon#flushed, iclass 5, count 2 2006.201.11:03:26.06#ibcon#about to write, iclass 5, count 2 2006.201.11:03:26.06#ibcon#wrote, iclass 5, count 2 2006.201.11:03:26.06#ibcon#about to read 3, iclass 5, count 2 2006.201.11:03:26.08#ibcon#read 3, iclass 5, count 2 2006.201.11:03:26.08#ibcon#about to read 4, iclass 5, count 2 2006.201.11:03:26.08#ibcon#read 4, iclass 5, count 2 2006.201.11:03:26.08#ibcon#about to read 5, iclass 5, count 2 2006.201.11:03:26.08#ibcon#read 5, iclass 5, count 2 2006.201.11:03:26.08#ibcon#about to read 6, iclass 5, count 2 2006.201.11:03:26.08#ibcon#read 6, iclass 5, count 2 2006.201.11:03:26.08#ibcon#end of sib2, iclass 5, count 2 2006.201.11:03:26.08#ibcon#*mode == 0, iclass 5, count 2 2006.201.11:03:26.08#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.11:03:26.08#ibcon#[25=AT07-05\r\n] 2006.201.11:03:26.08#ibcon#*before write, iclass 5, count 2 2006.201.11:03:26.08#ibcon#enter sib2, iclass 5, count 2 2006.201.11:03:26.08#ibcon#flushed, iclass 5, count 2 2006.201.11:03:26.08#ibcon#about to write, iclass 5, count 2 2006.201.11:03:26.08#ibcon#wrote, iclass 5, count 2 2006.201.11:03:26.08#ibcon#about to read 3, iclass 5, count 2 2006.201.11:03:26.11#ibcon#read 3, iclass 5, count 2 2006.201.11:03:26.11#ibcon#about to read 4, iclass 5, count 2 2006.201.11:03:26.11#ibcon#read 4, iclass 5, count 2 2006.201.11:03:26.11#ibcon#about to read 5, iclass 5, count 2 2006.201.11:03:26.11#ibcon#read 5, iclass 5, count 2 2006.201.11:03:26.11#ibcon#about to read 6, iclass 5, count 2 2006.201.11:03:26.11#ibcon#read 6, iclass 5, count 2 2006.201.11:03:26.11#ibcon#end of sib2, iclass 5, count 2 2006.201.11:03:26.11#ibcon#*after write, iclass 5, count 2 2006.201.11:03:26.11#ibcon#*before return 0, iclass 5, count 2 2006.201.11:03:26.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:26.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:26.11#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.11:03:26.11#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:26.11#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:26.23#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:26.23#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:26.23#ibcon#enter wrdev, iclass 5, count 0 2006.201.11:03:26.23#ibcon#first serial, iclass 5, count 0 2006.201.11:03:26.23#ibcon#enter sib2, iclass 5, count 0 2006.201.11:03:26.23#ibcon#flushed, iclass 5, count 0 2006.201.11:03:26.23#ibcon#about to write, iclass 5, count 0 2006.201.11:03:26.23#ibcon#wrote, iclass 5, count 0 2006.201.11:03:26.23#ibcon#about to read 3, iclass 5, count 0 2006.201.11:03:26.25#ibcon#read 3, iclass 5, count 0 2006.201.11:03:26.25#ibcon#about to read 4, iclass 5, count 0 2006.201.11:03:26.25#ibcon#read 4, iclass 5, count 0 2006.201.11:03:26.25#ibcon#about to read 5, iclass 5, count 0 2006.201.11:03:26.25#ibcon#read 5, iclass 5, count 0 2006.201.11:03:26.25#ibcon#about to read 6, iclass 5, count 0 2006.201.11:03:26.25#ibcon#read 6, iclass 5, count 0 2006.201.11:03:26.25#ibcon#end of sib2, iclass 5, count 0 2006.201.11:03:26.25#ibcon#*mode == 0, iclass 5, count 0 2006.201.11:03:26.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.11:03:26.25#ibcon#[25=USB\r\n] 2006.201.11:03:26.25#ibcon#*before write, iclass 5, count 0 2006.201.11:03:26.25#ibcon#enter sib2, iclass 5, count 0 2006.201.11:03:26.25#ibcon#flushed, iclass 5, count 0 2006.201.11:03:26.25#ibcon#about to write, iclass 5, count 0 2006.201.11:03:26.25#ibcon#wrote, iclass 5, count 0 2006.201.11:03:26.25#ibcon#about to read 3, iclass 5, count 0 2006.201.11:03:26.28#ibcon#read 3, iclass 5, count 0 2006.201.11:03:26.28#ibcon#about to read 4, iclass 5, count 0 2006.201.11:03:26.28#ibcon#read 4, iclass 5, count 0 2006.201.11:03:26.28#ibcon#about to read 5, iclass 5, count 0 2006.201.11:03:26.28#ibcon#read 5, iclass 5, count 0 2006.201.11:03:26.28#ibcon#about to read 6, iclass 5, count 0 2006.201.11:03:26.28#ibcon#read 6, iclass 5, count 0 2006.201.11:03:26.28#ibcon#end of sib2, iclass 5, count 0 2006.201.11:03:26.28#ibcon#*after write, iclass 5, count 0 2006.201.11:03:26.28#ibcon#*before return 0, iclass 5, count 0 2006.201.11:03:26.28#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:26.28#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:26.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.11:03:26.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.11:03:26.28$vck44/valo=8,884.99 2006.201.11:03:26.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.11:03:26.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.11:03:26.28#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:26.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:26.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:26.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:26.28#ibcon#enter wrdev, iclass 7, count 0 2006.201.11:03:26.28#ibcon#first serial, iclass 7, count 0 2006.201.11:03:26.28#ibcon#enter sib2, iclass 7, count 0 2006.201.11:03:26.28#ibcon#flushed, iclass 7, count 0 2006.201.11:03:26.28#ibcon#about to write, iclass 7, count 0 2006.201.11:03:26.28#ibcon#wrote, iclass 7, count 0 2006.201.11:03:26.28#ibcon#about to read 3, iclass 7, count 0 2006.201.11:03:26.30#ibcon#read 3, iclass 7, count 0 2006.201.11:03:26.30#ibcon#about to read 4, iclass 7, count 0 2006.201.11:03:26.30#ibcon#read 4, iclass 7, count 0 2006.201.11:03:26.30#ibcon#about to read 5, iclass 7, count 0 2006.201.11:03:26.30#ibcon#read 5, iclass 7, count 0 2006.201.11:03:26.30#ibcon#about to read 6, iclass 7, count 0 2006.201.11:03:26.30#ibcon#read 6, iclass 7, count 0 2006.201.11:03:26.30#ibcon#end of sib2, iclass 7, count 0 2006.201.11:03:26.30#ibcon#*mode == 0, iclass 7, count 0 2006.201.11:03:26.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.11:03:26.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:03:26.30#ibcon#*before write, iclass 7, count 0 2006.201.11:03:26.30#ibcon#enter sib2, iclass 7, count 0 2006.201.11:03:26.30#ibcon#flushed, iclass 7, count 0 2006.201.11:03:26.30#ibcon#about to write, iclass 7, count 0 2006.201.11:03:26.30#ibcon#wrote, iclass 7, count 0 2006.201.11:03:26.30#ibcon#about to read 3, iclass 7, count 0 2006.201.11:03:26.34#ibcon#read 3, iclass 7, count 0 2006.201.11:03:26.34#ibcon#about to read 4, iclass 7, count 0 2006.201.11:03:26.34#ibcon#read 4, iclass 7, count 0 2006.201.11:03:26.34#ibcon#about to read 5, iclass 7, count 0 2006.201.11:03:26.34#ibcon#read 5, iclass 7, count 0 2006.201.11:03:26.34#ibcon#about to read 6, iclass 7, count 0 2006.201.11:03:26.34#ibcon#read 6, iclass 7, count 0 2006.201.11:03:26.34#ibcon#end of sib2, iclass 7, count 0 2006.201.11:03:26.34#ibcon#*after write, iclass 7, count 0 2006.201.11:03:26.34#ibcon#*before return 0, iclass 7, count 0 2006.201.11:03:26.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:26.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:26.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.11:03:26.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.11:03:26.34$vck44/va=8,4 2006.201.11:03:26.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.11:03:26.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.11:03:26.34#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:26.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:03:26.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:03:26.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:03:26.40#ibcon#enter wrdev, iclass 11, count 2 2006.201.11:03:26.40#ibcon#first serial, iclass 11, count 2 2006.201.11:03:26.40#ibcon#enter sib2, iclass 11, count 2 2006.201.11:03:26.40#ibcon#flushed, iclass 11, count 2 2006.201.11:03:26.40#ibcon#about to write, iclass 11, count 2 2006.201.11:03:26.40#ibcon#wrote, iclass 11, count 2 2006.201.11:03:26.40#ibcon#about to read 3, iclass 11, count 2 2006.201.11:03:26.42#ibcon#read 3, iclass 11, count 2 2006.201.11:03:26.42#ibcon#about to read 4, iclass 11, count 2 2006.201.11:03:26.42#ibcon#read 4, iclass 11, count 2 2006.201.11:03:26.42#ibcon#about to read 5, iclass 11, count 2 2006.201.11:03:26.42#ibcon#read 5, iclass 11, count 2 2006.201.11:03:26.42#ibcon#about to read 6, iclass 11, count 2 2006.201.11:03:26.42#ibcon#read 6, iclass 11, count 2 2006.201.11:03:26.42#ibcon#end of sib2, iclass 11, count 2 2006.201.11:03:26.42#ibcon#*mode == 0, iclass 11, count 2 2006.201.11:03:26.42#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.11:03:26.42#ibcon#[25=AT08-04\r\n] 2006.201.11:03:26.42#ibcon#*before write, iclass 11, count 2 2006.201.11:03:26.42#ibcon#enter sib2, iclass 11, count 2 2006.201.11:03:26.42#ibcon#flushed, iclass 11, count 2 2006.201.11:03:26.42#ibcon#about to write, iclass 11, count 2 2006.201.11:03:26.42#ibcon#wrote, iclass 11, count 2 2006.201.11:03:26.42#ibcon#about to read 3, iclass 11, count 2 2006.201.11:03:26.45#ibcon#read 3, iclass 11, count 2 2006.201.11:03:26.45#ibcon#about to read 4, iclass 11, count 2 2006.201.11:03:26.45#ibcon#read 4, iclass 11, count 2 2006.201.11:03:26.45#ibcon#about to read 5, iclass 11, count 2 2006.201.11:03:26.45#ibcon#read 5, iclass 11, count 2 2006.201.11:03:26.45#ibcon#about to read 6, iclass 11, count 2 2006.201.11:03:26.45#ibcon#read 6, iclass 11, count 2 2006.201.11:03:26.45#ibcon#end of sib2, iclass 11, count 2 2006.201.11:03:26.45#ibcon#*after write, iclass 11, count 2 2006.201.11:03:26.45#ibcon#*before return 0, iclass 11, count 2 2006.201.11:03:26.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:03:26.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:03:26.45#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.11:03:26.45#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:26.45#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:03:26.57#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:03:26.57#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:03:26.57#ibcon#enter wrdev, iclass 11, count 0 2006.201.11:03:26.57#ibcon#first serial, iclass 11, count 0 2006.201.11:03:26.57#ibcon#enter sib2, iclass 11, count 0 2006.201.11:03:26.57#ibcon#flushed, iclass 11, count 0 2006.201.11:03:26.57#ibcon#about to write, iclass 11, count 0 2006.201.11:03:26.57#ibcon#wrote, iclass 11, count 0 2006.201.11:03:26.57#ibcon#about to read 3, iclass 11, count 0 2006.201.11:03:26.59#ibcon#read 3, iclass 11, count 0 2006.201.11:03:26.59#ibcon#about to read 4, iclass 11, count 0 2006.201.11:03:26.59#ibcon#read 4, iclass 11, count 0 2006.201.11:03:26.59#ibcon#about to read 5, iclass 11, count 0 2006.201.11:03:26.59#ibcon#read 5, iclass 11, count 0 2006.201.11:03:26.59#ibcon#about to read 6, iclass 11, count 0 2006.201.11:03:26.59#ibcon#read 6, iclass 11, count 0 2006.201.11:03:26.59#ibcon#end of sib2, iclass 11, count 0 2006.201.11:03:26.59#ibcon#*mode == 0, iclass 11, count 0 2006.201.11:03:26.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.11:03:26.59#ibcon#[25=USB\r\n] 2006.201.11:03:26.59#ibcon#*before write, iclass 11, count 0 2006.201.11:03:26.59#ibcon#enter sib2, iclass 11, count 0 2006.201.11:03:26.59#ibcon#flushed, iclass 11, count 0 2006.201.11:03:26.59#ibcon#about to write, iclass 11, count 0 2006.201.11:03:26.59#ibcon#wrote, iclass 11, count 0 2006.201.11:03:26.59#ibcon#about to read 3, iclass 11, count 0 2006.201.11:03:26.62#ibcon#read 3, iclass 11, count 0 2006.201.11:03:26.62#ibcon#about to read 4, iclass 11, count 0 2006.201.11:03:26.62#ibcon#read 4, iclass 11, count 0 2006.201.11:03:26.62#ibcon#about to read 5, iclass 11, count 0 2006.201.11:03:26.62#ibcon#read 5, iclass 11, count 0 2006.201.11:03:26.62#ibcon#about to read 6, iclass 11, count 0 2006.201.11:03:26.62#ibcon#read 6, iclass 11, count 0 2006.201.11:03:26.62#ibcon#end of sib2, iclass 11, count 0 2006.201.11:03:26.62#ibcon#*after write, iclass 11, count 0 2006.201.11:03:26.62#ibcon#*before return 0, iclass 11, count 0 2006.201.11:03:26.62#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:03:26.62#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:03:26.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.11:03:26.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.11:03:26.62$vck44/vblo=1,629.99 2006.201.11:03:26.62#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.11:03:26.62#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.11:03:26.62#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:26.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:26.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:26.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:26.62#ibcon#enter wrdev, iclass 13, count 0 2006.201.11:03:26.62#ibcon#first serial, iclass 13, count 0 2006.201.11:03:26.62#ibcon#enter sib2, iclass 13, count 0 2006.201.11:03:26.62#ibcon#flushed, iclass 13, count 0 2006.201.11:03:26.62#ibcon#about to write, iclass 13, count 0 2006.201.11:03:26.62#ibcon#wrote, iclass 13, count 0 2006.201.11:03:26.62#ibcon#about to read 3, iclass 13, count 0 2006.201.11:03:26.64#ibcon#read 3, iclass 13, count 0 2006.201.11:03:26.64#ibcon#about to read 4, iclass 13, count 0 2006.201.11:03:26.64#ibcon#read 4, iclass 13, count 0 2006.201.11:03:26.64#ibcon#about to read 5, iclass 13, count 0 2006.201.11:03:26.64#ibcon#read 5, iclass 13, count 0 2006.201.11:03:26.64#ibcon#about to read 6, iclass 13, count 0 2006.201.11:03:26.64#ibcon#read 6, iclass 13, count 0 2006.201.11:03:26.64#ibcon#end of sib2, iclass 13, count 0 2006.201.11:03:26.64#ibcon#*mode == 0, iclass 13, count 0 2006.201.11:03:26.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.11:03:26.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:03:26.64#ibcon#*before write, iclass 13, count 0 2006.201.11:03:26.64#ibcon#enter sib2, iclass 13, count 0 2006.201.11:03:26.64#ibcon#flushed, iclass 13, count 0 2006.201.11:03:26.64#ibcon#about to write, iclass 13, count 0 2006.201.11:03:26.64#ibcon#wrote, iclass 13, count 0 2006.201.11:03:26.64#ibcon#about to read 3, iclass 13, count 0 2006.201.11:03:26.68#ibcon#read 3, iclass 13, count 0 2006.201.11:03:26.68#ibcon#about to read 4, iclass 13, count 0 2006.201.11:03:26.68#ibcon#read 4, iclass 13, count 0 2006.201.11:03:26.68#ibcon#about to read 5, iclass 13, count 0 2006.201.11:03:26.68#ibcon#read 5, iclass 13, count 0 2006.201.11:03:26.68#ibcon#about to read 6, iclass 13, count 0 2006.201.11:03:26.68#ibcon#read 6, iclass 13, count 0 2006.201.11:03:26.68#ibcon#end of sib2, iclass 13, count 0 2006.201.11:03:26.68#ibcon#*after write, iclass 13, count 0 2006.201.11:03:26.68#ibcon#*before return 0, iclass 13, count 0 2006.201.11:03:26.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:26.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:03:26.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.11:03:26.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.11:03:26.68$vck44/vb=1,4 2006.201.11:03:26.68#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.11:03:26.68#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.11:03:26.68#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:26.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:26.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:26.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:26.68#ibcon#enter wrdev, iclass 15, count 2 2006.201.11:03:26.68#ibcon#first serial, iclass 15, count 2 2006.201.11:03:26.68#ibcon#enter sib2, iclass 15, count 2 2006.201.11:03:26.68#ibcon#flushed, iclass 15, count 2 2006.201.11:03:26.68#ibcon#about to write, iclass 15, count 2 2006.201.11:03:26.68#ibcon#wrote, iclass 15, count 2 2006.201.11:03:26.68#ibcon#about to read 3, iclass 15, count 2 2006.201.11:03:26.70#ibcon#read 3, iclass 15, count 2 2006.201.11:03:26.70#ibcon#about to read 4, iclass 15, count 2 2006.201.11:03:26.70#ibcon#read 4, iclass 15, count 2 2006.201.11:03:26.70#ibcon#about to read 5, iclass 15, count 2 2006.201.11:03:26.70#ibcon#read 5, iclass 15, count 2 2006.201.11:03:26.70#ibcon#about to read 6, iclass 15, count 2 2006.201.11:03:26.70#ibcon#read 6, iclass 15, count 2 2006.201.11:03:26.70#ibcon#end of sib2, iclass 15, count 2 2006.201.11:03:26.70#ibcon#*mode == 0, iclass 15, count 2 2006.201.11:03:26.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.11:03:26.70#ibcon#[27=AT01-04\r\n] 2006.201.11:03:26.70#ibcon#*before write, iclass 15, count 2 2006.201.11:03:26.70#ibcon#enter sib2, iclass 15, count 2 2006.201.11:03:26.70#ibcon#flushed, iclass 15, count 2 2006.201.11:03:26.70#ibcon#about to write, iclass 15, count 2 2006.201.11:03:26.70#ibcon#wrote, iclass 15, count 2 2006.201.11:03:26.70#ibcon#about to read 3, iclass 15, count 2 2006.201.11:03:26.73#ibcon#read 3, iclass 15, count 2 2006.201.11:03:26.73#ibcon#about to read 4, iclass 15, count 2 2006.201.11:03:26.73#ibcon#read 4, iclass 15, count 2 2006.201.11:03:26.73#ibcon#about to read 5, iclass 15, count 2 2006.201.11:03:26.73#ibcon#read 5, iclass 15, count 2 2006.201.11:03:26.73#ibcon#about to read 6, iclass 15, count 2 2006.201.11:03:26.73#ibcon#read 6, iclass 15, count 2 2006.201.11:03:26.73#ibcon#end of sib2, iclass 15, count 2 2006.201.11:03:26.73#ibcon#*after write, iclass 15, count 2 2006.201.11:03:26.73#ibcon#*before return 0, iclass 15, count 2 2006.201.11:03:26.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:26.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:03:26.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.11:03:26.73#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:26.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:26.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:26.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:26.85#ibcon#enter wrdev, iclass 15, count 0 2006.201.11:03:26.85#ibcon#first serial, iclass 15, count 0 2006.201.11:03:26.85#ibcon#enter sib2, iclass 15, count 0 2006.201.11:03:26.85#ibcon#flushed, iclass 15, count 0 2006.201.11:03:26.85#ibcon#about to write, iclass 15, count 0 2006.201.11:03:26.85#ibcon#wrote, iclass 15, count 0 2006.201.11:03:26.85#ibcon#about to read 3, iclass 15, count 0 2006.201.11:03:26.87#ibcon#read 3, iclass 15, count 0 2006.201.11:03:26.87#ibcon#about to read 4, iclass 15, count 0 2006.201.11:03:26.87#ibcon#read 4, iclass 15, count 0 2006.201.11:03:26.87#ibcon#about to read 5, iclass 15, count 0 2006.201.11:03:26.87#ibcon#read 5, iclass 15, count 0 2006.201.11:03:26.87#ibcon#about to read 6, iclass 15, count 0 2006.201.11:03:26.87#ibcon#read 6, iclass 15, count 0 2006.201.11:03:26.87#ibcon#end of sib2, iclass 15, count 0 2006.201.11:03:26.87#ibcon#*mode == 0, iclass 15, count 0 2006.201.11:03:26.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.11:03:26.87#ibcon#[27=USB\r\n] 2006.201.11:03:26.87#ibcon#*before write, iclass 15, count 0 2006.201.11:03:26.87#ibcon#enter sib2, iclass 15, count 0 2006.201.11:03:26.87#ibcon#flushed, iclass 15, count 0 2006.201.11:03:26.87#ibcon#about to write, iclass 15, count 0 2006.201.11:03:26.87#ibcon#wrote, iclass 15, count 0 2006.201.11:03:26.87#ibcon#about to read 3, iclass 15, count 0 2006.201.11:03:26.90#ibcon#read 3, iclass 15, count 0 2006.201.11:03:26.90#ibcon#about to read 4, iclass 15, count 0 2006.201.11:03:26.90#ibcon#read 4, iclass 15, count 0 2006.201.11:03:26.90#ibcon#about to read 5, iclass 15, count 0 2006.201.11:03:26.90#ibcon#read 5, iclass 15, count 0 2006.201.11:03:26.90#ibcon#about to read 6, iclass 15, count 0 2006.201.11:03:26.90#ibcon#read 6, iclass 15, count 0 2006.201.11:03:26.90#ibcon#end of sib2, iclass 15, count 0 2006.201.11:03:26.90#ibcon#*after write, iclass 15, count 0 2006.201.11:03:26.90#ibcon#*before return 0, iclass 15, count 0 2006.201.11:03:26.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:26.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:03:26.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.11:03:26.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.11:03:26.90$vck44/vblo=2,634.99 2006.201.11:03:26.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.11:03:26.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.11:03:26.90#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:26.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:26.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:26.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:26.90#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:03:26.90#ibcon#first serial, iclass 17, count 0 2006.201.11:03:26.90#ibcon#enter sib2, iclass 17, count 0 2006.201.11:03:26.90#ibcon#flushed, iclass 17, count 0 2006.201.11:03:26.90#ibcon#about to write, iclass 17, count 0 2006.201.11:03:26.90#ibcon#wrote, iclass 17, count 0 2006.201.11:03:26.90#ibcon#about to read 3, iclass 17, count 0 2006.201.11:03:26.92#ibcon#read 3, iclass 17, count 0 2006.201.11:03:26.92#ibcon#about to read 4, iclass 17, count 0 2006.201.11:03:26.92#ibcon#read 4, iclass 17, count 0 2006.201.11:03:26.92#ibcon#about to read 5, iclass 17, count 0 2006.201.11:03:26.92#ibcon#read 5, iclass 17, count 0 2006.201.11:03:26.92#ibcon#about to read 6, iclass 17, count 0 2006.201.11:03:26.92#ibcon#read 6, iclass 17, count 0 2006.201.11:03:26.92#ibcon#end of sib2, iclass 17, count 0 2006.201.11:03:26.92#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:03:26.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:03:26.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:03:26.92#ibcon#*before write, iclass 17, count 0 2006.201.11:03:26.92#ibcon#enter sib2, iclass 17, count 0 2006.201.11:03:26.92#ibcon#flushed, iclass 17, count 0 2006.201.11:03:26.92#ibcon#about to write, iclass 17, count 0 2006.201.11:03:26.92#ibcon#wrote, iclass 17, count 0 2006.201.11:03:26.92#ibcon#about to read 3, iclass 17, count 0 2006.201.11:03:26.96#ibcon#read 3, iclass 17, count 0 2006.201.11:03:26.96#ibcon#about to read 4, iclass 17, count 0 2006.201.11:03:26.96#ibcon#read 4, iclass 17, count 0 2006.201.11:03:26.96#ibcon#about to read 5, iclass 17, count 0 2006.201.11:03:26.96#ibcon#read 5, iclass 17, count 0 2006.201.11:03:26.96#ibcon#about to read 6, iclass 17, count 0 2006.201.11:03:26.96#ibcon#read 6, iclass 17, count 0 2006.201.11:03:26.96#ibcon#end of sib2, iclass 17, count 0 2006.201.11:03:26.96#ibcon#*after write, iclass 17, count 0 2006.201.11:03:26.96#ibcon#*before return 0, iclass 17, count 0 2006.201.11:03:26.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:26.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:03:26.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:03:26.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:03:26.96$vck44/vb=2,5 2006.201.11:03:26.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.11:03:26.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.11:03:26.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:26.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:27.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:27.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:27.02#ibcon#enter wrdev, iclass 19, count 2 2006.201.11:03:27.02#ibcon#first serial, iclass 19, count 2 2006.201.11:03:27.02#ibcon#enter sib2, iclass 19, count 2 2006.201.11:03:27.02#ibcon#flushed, iclass 19, count 2 2006.201.11:03:27.02#ibcon#about to write, iclass 19, count 2 2006.201.11:03:27.02#ibcon#wrote, iclass 19, count 2 2006.201.11:03:27.02#ibcon#about to read 3, iclass 19, count 2 2006.201.11:03:27.04#ibcon#read 3, iclass 19, count 2 2006.201.11:03:27.04#ibcon#about to read 4, iclass 19, count 2 2006.201.11:03:27.04#ibcon#read 4, iclass 19, count 2 2006.201.11:03:27.04#ibcon#about to read 5, iclass 19, count 2 2006.201.11:03:27.04#ibcon#read 5, iclass 19, count 2 2006.201.11:03:27.04#ibcon#about to read 6, iclass 19, count 2 2006.201.11:03:27.04#ibcon#read 6, iclass 19, count 2 2006.201.11:03:27.04#ibcon#end of sib2, iclass 19, count 2 2006.201.11:03:27.04#ibcon#*mode == 0, iclass 19, count 2 2006.201.11:03:27.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.11:03:27.04#ibcon#[27=AT02-05\r\n] 2006.201.11:03:27.04#ibcon#*before write, iclass 19, count 2 2006.201.11:03:27.04#ibcon#enter sib2, iclass 19, count 2 2006.201.11:03:27.04#ibcon#flushed, iclass 19, count 2 2006.201.11:03:27.04#ibcon#about to write, iclass 19, count 2 2006.201.11:03:27.04#ibcon#wrote, iclass 19, count 2 2006.201.11:03:27.04#ibcon#about to read 3, iclass 19, count 2 2006.201.11:03:27.07#ibcon#read 3, iclass 19, count 2 2006.201.11:03:27.07#ibcon#about to read 4, iclass 19, count 2 2006.201.11:03:27.07#ibcon#read 4, iclass 19, count 2 2006.201.11:03:27.07#ibcon#about to read 5, iclass 19, count 2 2006.201.11:03:27.07#ibcon#read 5, iclass 19, count 2 2006.201.11:03:27.07#ibcon#about to read 6, iclass 19, count 2 2006.201.11:03:27.07#ibcon#read 6, iclass 19, count 2 2006.201.11:03:27.07#ibcon#end of sib2, iclass 19, count 2 2006.201.11:03:27.07#ibcon#*after write, iclass 19, count 2 2006.201.11:03:27.07#ibcon#*before return 0, iclass 19, count 2 2006.201.11:03:27.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:27.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:03:27.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.11:03:27.07#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:27.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:27.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:27.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:27.19#ibcon#enter wrdev, iclass 19, count 0 2006.201.11:03:27.19#ibcon#first serial, iclass 19, count 0 2006.201.11:03:27.19#ibcon#enter sib2, iclass 19, count 0 2006.201.11:03:27.19#ibcon#flushed, iclass 19, count 0 2006.201.11:03:27.19#ibcon#about to write, iclass 19, count 0 2006.201.11:03:27.19#ibcon#wrote, iclass 19, count 0 2006.201.11:03:27.19#ibcon#about to read 3, iclass 19, count 0 2006.201.11:03:27.21#ibcon#read 3, iclass 19, count 0 2006.201.11:03:27.21#ibcon#about to read 4, iclass 19, count 0 2006.201.11:03:27.21#ibcon#read 4, iclass 19, count 0 2006.201.11:03:27.21#ibcon#about to read 5, iclass 19, count 0 2006.201.11:03:27.21#ibcon#read 5, iclass 19, count 0 2006.201.11:03:27.21#ibcon#about to read 6, iclass 19, count 0 2006.201.11:03:27.21#ibcon#read 6, iclass 19, count 0 2006.201.11:03:27.21#ibcon#end of sib2, iclass 19, count 0 2006.201.11:03:27.21#ibcon#*mode == 0, iclass 19, count 0 2006.201.11:03:27.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.11:03:27.21#ibcon#[27=USB\r\n] 2006.201.11:03:27.21#ibcon#*before write, iclass 19, count 0 2006.201.11:03:27.21#ibcon#enter sib2, iclass 19, count 0 2006.201.11:03:27.21#ibcon#flushed, iclass 19, count 0 2006.201.11:03:27.21#ibcon#about to write, iclass 19, count 0 2006.201.11:03:27.21#ibcon#wrote, iclass 19, count 0 2006.201.11:03:27.21#ibcon#about to read 3, iclass 19, count 0 2006.201.11:03:27.24#ibcon#read 3, iclass 19, count 0 2006.201.11:03:27.24#ibcon#about to read 4, iclass 19, count 0 2006.201.11:03:27.24#ibcon#read 4, iclass 19, count 0 2006.201.11:03:27.24#ibcon#about to read 5, iclass 19, count 0 2006.201.11:03:27.24#ibcon#read 5, iclass 19, count 0 2006.201.11:03:27.24#ibcon#about to read 6, iclass 19, count 0 2006.201.11:03:27.24#ibcon#read 6, iclass 19, count 0 2006.201.11:03:27.24#ibcon#end of sib2, iclass 19, count 0 2006.201.11:03:27.24#ibcon#*after write, iclass 19, count 0 2006.201.11:03:27.24#ibcon#*before return 0, iclass 19, count 0 2006.201.11:03:27.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:27.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:03:27.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.11:03:27.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.11:03:27.24$vck44/vblo=3,649.99 2006.201.11:03:27.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.11:03:27.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.11:03:27.24#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:27.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:27.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:27.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:27.24#ibcon#enter wrdev, iclass 21, count 0 2006.201.11:03:27.24#ibcon#first serial, iclass 21, count 0 2006.201.11:03:27.24#ibcon#enter sib2, iclass 21, count 0 2006.201.11:03:27.24#ibcon#flushed, iclass 21, count 0 2006.201.11:03:27.24#ibcon#about to write, iclass 21, count 0 2006.201.11:03:27.24#ibcon#wrote, iclass 21, count 0 2006.201.11:03:27.24#ibcon#about to read 3, iclass 21, count 0 2006.201.11:03:27.26#ibcon#read 3, iclass 21, count 0 2006.201.11:03:27.26#ibcon#about to read 4, iclass 21, count 0 2006.201.11:03:27.26#ibcon#read 4, iclass 21, count 0 2006.201.11:03:27.26#ibcon#about to read 5, iclass 21, count 0 2006.201.11:03:27.26#ibcon#read 5, iclass 21, count 0 2006.201.11:03:27.26#ibcon#about to read 6, iclass 21, count 0 2006.201.11:03:27.26#ibcon#read 6, iclass 21, count 0 2006.201.11:03:27.26#ibcon#end of sib2, iclass 21, count 0 2006.201.11:03:27.26#ibcon#*mode == 0, iclass 21, count 0 2006.201.11:03:27.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.11:03:27.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:03:27.26#ibcon#*before write, iclass 21, count 0 2006.201.11:03:27.26#ibcon#enter sib2, iclass 21, count 0 2006.201.11:03:27.26#ibcon#flushed, iclass 21, count 0 2006.201.11:03:27.26#ibcon#about to write, iclass 21, count 0 2006.201.11:03:27.26#ibcon#wrote, iclass 21, count 0 2006.201.11:03:27.26#ibcon#about to read 3, iclass 21, count 0 2006.201.11:03:27.30#ibcon#read 3, iclass 21, count 0 2006.201.11:03:27.30#ibcon#about to read 4, iclass 21, count 0 2006.201.11:03:27.30#ibcon#read 4, iclass 21, count 0 2006.201.11:03:27.30#ibcon#about to read 5, iclass 21, count 0 2006.201.11:03:27.30#ibcon#read 5, iclass 21, count 0 2006.201.11:03:27.30#ibcon#about to read 6, iclass 21, count 0 2006.201.11:03:27.30#ibcon#read 6, iclass 21, count 0 2006.201.11:03:27.30#ibcon#end of sib2, iclass 21, count 0 2006.201.11:03:27.30#ibcon#*after write, iclass 21, count 0 2006.201.11:03:27.30#ibcon#*before return 0, iclass 21, count 0 2006.201.11:03:27.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:27.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:03:27.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.11:03:27.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.11:03:27.30$vck44/vb=3,4 2006.201.11:03:27.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.11:03:27.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.11:03:27.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:27.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:27.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:27.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:27.36#ibcon#enter wrdev, iclass 23, count 2 2006.201.11:03:27.36#ibcon#first serial, iclass 23, count 2 2006.201.11:03:27.36#ibcon#enter sib2, iclass 23, count 2 2006.201.11:03:27.36#ibcon#flushed, iclass 23, count 2 2006.201.11:03:27.36#ibcon#about to write, iclass 23, count 2 2006.201.11:03:27.36#ibcon#wrote, iclass 23, count 2 2006.201.11:03:27.36#ibcon#about to read 3, iclass 23, count 2 2006.201.11:03:27.38#ibcon#read 3, iclass 23, count 2 2006.201.11:03:27.38#ibcon#about to read 4, iclass 23, count 2 2006.201.11:03:27.38#ibcon#read 4, iclass 23, count 2 2006.201.11:03:27.38#ibcon#about to read 5, iclass 23, count 2 2006.201.11:03:27.38#ibcon#read 5, iclass 23, count 2 2006.201.11:03:27.38#ibcon#about to read 6, iclass 23, count 2 2006.201.11:03:27.38#ibcon#read 6, iclass 23, count 2 2006.201.11:03:27.38#ibcon#end of sib2, iclass 23, count 2 2006.201.11:03:27.38#ibcon#*mode == 0, iclass 23, count 2 2006.201.11:03:27.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.11:03:27.38#ibcon#[27=AT03-04\r\n] 2006.201.11:03:27.38#ibcon#*before write, iclass 23, count 2 2006.201.11:03:27.38#ibcon#enter sib2, iclass 23, count 2 2006.201.11:03:27.38#ibcon#flushed, iclass 23, count 2 2006.201.11:03:27.38#ibcon#about to write, iclass 23, count 2 2006.201.11:03:27.38#ibcon#wrote, iclass 23, count 2 2006.201.11:03:27.38#ibcon#about to read 3, iclass 23, count 2 2006.201.11:03:27.42#ibcon#read 3, iclass 23, count 2 2006.201.11:03:27.42#ibcon#about to read 4, iclass 23, count 2 2006.201.11:03:27.42#ibcon#read 4, iclass 23, count 2 2006.201.11:03:27.42#ibcon#about to read 5, iclass 23, count 2 2006.201.11:03:27.42#ibcon#read 5, iclass 23, count 2 2006.201.11:03:27.42#ibcon#about to read 6, iclass 23, count 2 2006.201.11:03:27.42#ibcon#read 6, iclass 23, count 2 2006.201.11:03:27.42#ibcon#end of sib2, iclass 23, count 2 2006.201.11:03:27.42#ibcon#*after write, iclass 23, count 2 2006.201.11:03:27.42#ibcon#*before return 0, iclass 23, count 2 2006.201.11:03:27.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:27.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:03:27.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.11:03:27.42#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:27.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:27.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:27.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:27.54#ibcon#enter wrdev, iclass 23, count 0 2006.201.11:03:27.54#ibcon#first serial, iclass 23, count 0 2006.201.11:03:27.54#ibcon#enter sib2, iclass 23, count 0 2006.201.11:03:27.54#ibcon#flushed, iclass 23, count 0 2006.201.11:03:27.54#ibcon#about to write, iclass 23, count 0 2006.201.11:03:27.54#ibcon#wrote, iclass 23, count 0 2006.201.11:03:27.54#ibcon#about to read 3, iclass 23, count 0 2006.201.11:03:27.56#ibcon#read 3, iclass 23, count 0 2006.201.11:03:27.56#ibcon#about to read 4, iclass 23, count 0 2006.201.11:03:27.56#ibcon#read 4, iclass 23, count 0 2006.201.11:03:27.56#ibcon#about to read 5, iclass 23, count 0 2006.201.11:03:27.56#ibcon#read 5, iclass 23, count 0 2006.201.11:03:27.56#ibcon#about to read 6, iclass 23, count 0 2006.201.11:03:27.56#ibcon#read 6, iclass 23, count 0 2006.201.11:03:27.56#ibcon#end of sib2, iclass 23, count 0 2006.201.11:03:27.56#ibcon#*mode == 0, iclass 23, count 0 2006.201.11:03:27.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.11:03:27.56#ibcon#[27=USB\r\n] 2006.201.11:03:27.56#ibcon#*before write, iclass 23, count 0 2006.201.11:03:27.56#ibcon#enter sib2, iclass 23, count 0 2006.201.11:03:27.56#ibcon#flushed, iclass 23, count 0 2006.201.11:03:27.56#ibcon#about to write, iclass 23, count 0 2006.201.11:03:27.56#ibcon#wrote, iclass 23, count 0 2006.201.11:03:27.56#ibcon#about to read 3, iclass 23, count 0 2006.201.11:03:27.59#ibcon#read 3, iclass 23, count 0 2006.201.11:03:27.59#ibcon#about to read 4, iclass 23, count 0 2006.201.11:03:27.59#ibcon#read 4, iclass 23, count 0 2006.201.11:03:27.59#ibcon#about to read 5, iclass 23, count 0 2006.201.11:03:27.59#ibcon#read 5, iclass 23, count 0 2006.201.11:03:27.59#ibcon#about to read 6, iclass 23, count 0 2006.201.11:03:27.59#ibcon#read 6, iclass 23, count 0 2006.201.11:03:27.59#ibcon#end of sib2, iclass 23, count 0 2006.201.11:03:27.59#ibcon#*after write, iclass 23, count 0 2006.201.11:03:27.59#ibcon#*before return 0, iclass 23, count 0 2006.201.11:03:27.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:27.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:03:27.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.11:03:27.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.11:03:27.59$vck44/vblo=4,679.99 2006.201.11:03:27.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.11:03:27.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.11:03:27.59#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:27.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:03:27.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:03:27.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:03:27.59#ibcon#enter wrdev, iclass 25, count 0 2006.201.11:03:27.59#ibcon#first serial, iclass 25, count 0 2006.201.11:03:27.59#ibcon#enter sib2, iclass 25, count 0 2006.201.11:03:27.59#ibcon#flushed, iclass 25, count 0 2006.201.11:03:27.59#ibcon#about to write, iclass 25, count 0 2006.201.11:03:27.59#ibcon#wrote, iclass 25, count 0 2006.201.11:03:27.59#ibcon#about to read 3, iclass 25, count 0 2006.201.11:03:27.61#ibcon#read 3, iclass 25, count 0 2006.201.11:03:27.61#ibcon#about to read 4, iclass 25, count 0 2006.201.11:03:27.61#ibcon#read 4, iclass 25, count 0 2006.201.11:03:27.61#ibcon#about to read 5, iclass 25, count 0 2006.201.11:03:27.61#ibcon#read 5, iclass 25, count 0 2006.201.11:03:27.61#ibcon#about to read 6, iclass 25, count 0 2006.201.11:03:27.61#ibcon#read 6, iclass 25, count 0 2006.201.11:03:27.61#ibcon#end of sib2, iclass 25, count 0 2006.201.11:03:27.61#ibcon#*mode == 0, iclass 25, count 0 2006.201.11:03:27.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.11:03:27.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:03:27.61#ibcon#*before write, iclass 25, count 0 2006.201.11:03:27.61#ibcon#enter sib2, iclass 25, count 0 2006.201.11:03:27.61#ibcon#flushed, iclass 25, count 0 2006.201.11:03:27.61#ibcon#about to write, iclass 25, count 0 2006.201.11:03:27.61#ibcon#wrote, iclass 25, count 0 2006.201.11:03:27.61#ibcon#about to read 3, iclass 25, count 0 2006.201.11:03:27.65#ibcon#read 3, iclass 25, count 0 2006.201.11:03:27.65#ibcon#about to read 4, iclass 25, count 0 2006.201.11:03:27.65#ibcon#read 4, iclass 25, count 0 2006.201.11:03:27.65#ibcon#about to read 5, iclass 25, count 0 2006.201.11:03:27.65#ibcon#read 5, iclass 25, count 0 2006.201.11:03:27.65#ibcon#about to read 6, iclass 25, count 0 2006.201.11:03:27.65#ibcon#read 6, iclass 25, count 0 2006.201.11:03:27.65#ibcon#end of sib2, iclass 25, count 0 2006.201.11:03:27.65#ibcon#*after write, iclass 25, count 0 2006.201.11:03:27.65#ibcon#*before return 0, iclass 25, count 0 2006.201.11:03:27.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:03:27.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:03:27.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.11:03:27.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.11:03:27.65$vck44/vb=4,5 2006.201.11:03:27.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.11:03:27.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.11:03:27.65#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:27.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:03:27.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:03:27.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:03:27.71#ibcon#enter wrdev, iclass 27, count 2 2006.201.11:03:27.71#ibcon#first serial, iclass 27, count 2 2006.201.11:03:27.71#ibcon#enter sib2, iclass 27, count 2 2006.201.11:03:27.71#ibcon#flushed, iclass 27, count 2 2006.201.11:03:27.71#ibcon#about to write, iclass 27, count 2 2006.201.11:03:27.71#ibcon#wrote, iclass 27, count 2 2006.201.11:03:27.71#ibcon#about to read 3, iclass 27, count 2 2006.201.11:03:27.73#ibcon#read 3, iclass 27, count 2 2006.201.11:03:27.73#ibcon#about to read 4, iclass 27, count 2 2006.201.11:03:27.73#ibcon#read 4, iclass 27, count 2 2006.201.11:03:27.73#ibcon#about to read 5, iclass 27, count 2 2006.201.11:03:27.73#ibcon#read 5, iclass 27, count 2 2006.201.11:03:27.73#ibcon#about to read 6, iclass 27, count 2 2006.201.11:03:27.73#ibcon#read 6, iclass 27, count 2 2006.201.11:03:27.73#ibcon#end of sib2, iclass 27, count 2 2006.201.11:03:27.73#ibcon#*mode == 0, iclass 27, count 2 2006.201.11:03:27.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.11:03:27.73#ibcon#[27=AT04-05\r\n] 2006.201.11:03:27.73#ibcon#*before write, iclass 27, count 2 2006.201.11:03:27.73#ibcon#enter sib2, iclass 27, count 2 2006.201.11:03:27.73#ibcon#flushed, iclass 27, count 2 2006.201.11:03:27.73#ibcon#about to write, iclass 27, count 2 2006.201.11:03:27.73#ibcon#wrote, iclass 27, count 2 2006.201.11:03:27.73#ibcon#about to read 3, iclass 27, count 2 2006.201.11:03:27.76#ibcon#read 3, iclass 27, count 2 2006.201.11:03:27.76#ibcon#about to read 4, iclass 27, count 2 2006.201.11:03:27.76#ibcon#read 4, iclass 27, count 2 2006.201.11:03:27.76#ibcon#about to read 5, iclass 27, count 2 2006.201.11:03:27.76#ibcon#read 5, iclass 27, count 2 2006.201.11:03:27.76#ibcon#about to read 6, iclass 27, count 2 2006.201.11:03:27.76#ibcon#read 6, iclass 27, count 2 2006.201.11:03:27.76#ibcon#end of sib2, iclass 27, count 2 2006.201.11:03:27.76#ibcon#*after write, iclass 27, count 2 2006.201.11:03:27.76#ibcon#*before return 0, iclass 27, count 2 2006.201.11:03:27.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:03:27.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:03:27.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.11:03:27.76#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:27.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:03:27.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:03:27.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:03:27.88#ibcon#enter wrdev, iclass 27, count 0 2006.201.11:03:27.88#ibcon#first serial, iclass 27, count 0 2006.201.11:03:27.88#ibcon#enter sib2, iclass 27, count 0 2006.201.11:03:27.88#ibcon#flushed, iclass 27, count 0 2006.201.11:03:27.88#ibcon#about to write, iclass 27, count 0 2006.201.11:03:27.88#ibcon#wrote, iclass 27, count 0 2006.201.11:03:27.88#ibcon#about to read 3, iclass 27, count 0 2006.201.11:03:27.90#ibcon#read 3, iclass 27, count 0 2006.201.11:03:27.90#ibcon#about to read 4, iclass 27, count 0 2006.201.11:03:27.90#ibcon#read 4, iclass 27, count 0 2006.201.11:03:27.90#ibcon#about to read 5, iclass 27, count 0 2006.201.11:03:27.90#ibcon#read 5, iclass 27, count 0 2006.201.11:03:27.90#ibcon#about to read 6, iclass 27, count 0 2006.201.11:03:27.90#ibcon#read 6, iclass 27, count 0 2006.201.11:03:27.90#ibcon#end of sib2, iclass 27, count 0 2006.201.11:03:27.90#ibcon#*mode == 0, iclass 27, count 0 2006.201.11:03:27.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.11:03:27.90#ibcon#[27=USB\r\n] 2006.201.11:03:27.90#ibcon#*before write, iclass 27, count 0 2006.201.11:03:27.90#ibcon#enter sib2, iclass 27, count 0 2006.201.11:03:27.90#ibcon#flushed, iclass 27, count 0 2006.201.11:03:27.90#ibcon#about to write, iclass 27, count 0 2006.201.11:03:27.90#ibcon#wrote, iclass 27, count 0 2006.201.11:03:27.90#ibcon#about to read 3, iclass 27, count 0 2006.201.11:03:27.93#ibcon#read 3, iclass 27, count 0 2006.201.11:03:27.93#ibcon#about to read 4, iclass 27, count 0 2006.201.11:03:27.93#ibcon#read 4, iclass 27, count 0 2006.201.11:03:27.93#ibcon#about to read 5, iclass 27, count 0 2006.201.11:03:27.93#ibcon#read 5, iclass 27, count 0 2006.201.11:03:27.93#ibcon#about to read 6, iclass 27, count 0 2006.201.11:03:27.93#ibcon#read 6, iclass 27, count 0 2006.201.11:03:27.93#ibcon#end of sib2, iclass 27, count 0 2006.201.11:03:27.93#ibcon#*after write, iclass 27, count 0 2006.201.11:03:27.93#ibcon#*before return 0, iclass 27, count 0 2006.201.11:03:27.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:03:27.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:03:27.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.11:03:27.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.11:03:27.93$vck44/vblo=5,709.99 2006.201.11:03:27.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.11:03:27.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.11:03:27.93#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:27.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:03:27.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:03:27.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:03:27.93#ibcon#enter wrdev, iclass 29, count 0 2006.201.11:03:27.93#ibcon#first serial, iclass 29, count 0 2006.201.11:03:27.93#ibcon#enter sib2, iclass 29, count 0 2006.201.11:03:27.93#ibcon#flushed, iclass 29, count 0 2006.201.11:03:27.93#ibcon#about to write, iclass 29, count 0 2006.201.11:03:27.93#ibcon#wrote, iclass 29, count 0 2006.201.11:03:27.93#ibcon#about to read 3, iclass 29, count 0 2006.201.11:03:27.95#ibcon#read 3, iclass 29, count 0 2006.201.11:03:27.95#ibcon#about to read 4, iclass 29, count 0 2006.201.11:03:27.95#ibcon#read 4, iclass 29, count 0 2006.201.11:03:27.95#ibcon#about to read 5, iclass 29, count 0 2006.201.11:03:27.95#ibcon#read 5, iclass 29, count 0 2006.201.11:03:27.95#ibcon#about to read 6, iclass 29, count 0 2006.201.11:03:27.95#ibcon#read 6, iclass 29, count 0 2006.201.11:03:27.95#ibcon#end of sib2, iclass 29, count 0 2006.201.11:03:27.95#ibcon#*mode == 0, iclass 29, count 0 2006.201.11:03:27.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.11:03:27.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:03:27.95#ibcon#*before write, iclass 29, count 0 2006.201.11:03:27.95#ibcon#enter sib2, iclass 29, count 0 2006.201.11:03:27.95#ibcon#flushed, iclass 29, count 0 2006.201.11:03:27.95#ibcon#about to write, iclass 29, count 0 2006.201.11:03:27.95#ibcon#wrote, iclass 29, count 0 2006.201.11:03:27.95#ibcon#about to read 3, iclass 29, count 0 2006.201.11:03:27.99#ibcon#read 3, iclass 29, count 0 2006.201.11:03:27.99#ibcon#about to read 4, iclass 29, count 0 2006.201.11:03:27.99#ibcon#read 4, iclass 29, count 0 2006.201.11:03:27.99#ibcon#about to read 5, iclass 29, count 0 2006.201.11:03:27.99#ibcon#read 5, iclass 29, count 0 2006.201.11:03:27.99#ibcon#about to read 6, iclass 29, count 0 2006.201.11:03:27.99#ibcon#read 6, iclass 29, count 0 2006.201.11:03:27.99#ibcon#end of sib2, iclass 29, count 0 2006.201.11:03:27.99#ibcon#*after write, iclass 29, count 0 2006.201.11:03:27.99#ibcon#*before return 0, iclass 29, count 0 2006.201.11:03:27.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:03:27.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:03:27.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.11:03:27.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.11:03:27.99$vck44/vb=5,4 2006.201.11:03:27.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.11:03:27.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.11:03:27.99#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:27.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:03:28.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:03:28.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:03:28.05#ibcon#enter wrdev, iclass 31, count 2 2006.201.11:03:28.05#ibcon#first serial, iclass 31, count 2 2006.201.11:03:28.05#ibcon#enter sib2, iclass 31, count 2 2006.201.11:03:28.05#ibcon#flushed, iclass 31, count 2 2006.201.11:03:28.05#ibcon#about to write, iclass 31, count 2 2006.201.11:03:28.05#ibcon#wrote, iclass 31, count 2 2006.201.11:03:28.05#ibcon#about to read 3, iclass 31, count 2 2006.201.11:03:28.07#ibcon#read 3, iclass 31, count 2 2006.201.11:03:28.07#ibcon#about to read 4, iclass 31, count 2 2006.201.11:03:28.07#ibcon#read 4, iclass 31, count 2 2006.201.11:03:28.07#ibcon#about to read 5, iclass 31, count 2 2006.201.11:03:28.07#ibcon#read 5, iclass 31, count 2 2006.201.11:03:28.07#ibcon#about to read 6, iclass 31, count 2 2006.201.11:03:28.07#ibcon#read 6, iclass 31, count 2 2006.201.11:03:28.07#ibcon#end of sib2, iclass 31, count 2 2006.201.11:03:28.07#ibcon#*mode == 0, iclass 31, count 2 2006.201.11:03:28.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.11:03:28.07#ibcon#[27=AT05-04\r\n] 2006.201.11:03:28.07#ibcon#*before write, iclass 31, count 2 2006.201.11:03:28.07#ibcon#enter sib2, iclass 31, count 2 2006.201.11:03:28.07#ibcon#flushed, iclass 31, count 2 2006.201.11:03:28.07#ibcon#about to write, iclass 31, count 2 2006.201.11:03:28.07#ibcon#wrote, iclass 31, count 2 2006.201.11:03:28.07#ibcon#about to read 3, iclass 31, count 2 2006.201.11:03:28.10#ibcon#read 3, iclass 31, count 2 2006.201.11:03:28.10#ibcon#about to read 4, iclass 31, count 2 2006.201.11:03:28.10#ibcon#read 4, iclass 31, count 2 2006.201.11:03:28.10#ibcon#about to read 5, iclass 31, count 2 2006.201.11:03:28.10#ibcon#read 5, iclass 31, count 2 2006.201.11:03:28.10#ibcon#about to read 6, iclass 31, count 2 2006.201.11:03:28.10#ibcon#read 6, iclass 31, count 2 2006.201.11:03:28.10#ibcon#end of sib2, iclass 31, count 2 2006.201.11:03:28.10#ibcon#*after write, iclass 31, count 2 2006.201.11:03:28.10#ibcon#*before return 0, iclass 31, count 2 2006.201.11:03:28.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:03:28.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:03:28.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.11:03:28.10#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:28.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:03:28.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:03:28.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:03:28.22#ibcon#enter wrdev, iclass 31, count 0 2006.201.11:03:28.22#ibcon#first serial, iclass 31, count 0 2006.201.11:03:28.22#ibcon#enter sib2, iclass 31, count 0 2006.201.11:03:28.22#ibcon#flushed, iclass 31, count 0 2006.201.11:03:28.22#ibcon#about to write, iclass 31, count 0 2006.201.11:03:28.22#ibcon#wrote, iclass 31, count 0 2006.201.11:03:28.22#ibcon#about to read 3, iclass 31, count 0 2006.201.11:03:28.24#ibcon#read 3, iclass 31, count 0 2006.201.11:03:28.24#ibcon#about to read 4, iclass 31, count 0 2006.201.11:03:28.24#ibcon#read 4, iclass 31, count 0 2006.201.11:03:28.24#ibcon#about to read 5, iclass 31, count 0 2006.201.11:03:28.24#ibcon#read 5, iclass 31, count 0 2006.201.11:03:28.24#ibcon#about to read 6, iclass 31, count 0 2006.201.11:03:28.24#ibcon#read 6, iclass 31, count 0 2006.201.11:03:28.24#ibcon#end of sib2, iclass 31, count 0 2006.201.11:03:28.24#ibcon#*mode == 0, iclass 31, count 0 2006.201.11:03:28.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.11:03:28.24#ibcon#[27=USB\r\n] 2006.201.11:03:28.24#ibcon#*before write, iclass 31, count 0 2006.201.11:03:28.24#ibcon#enter sib2, iclass 31, count 0 2006.201.11:03:28.24#ibcon#flushed, iclass 31, count 0 2006.201.11:03:28.24#ibcon#about to write, iclass 31, count 0 2006.201.11:03:28.24#ibcon#wrote, iclass 31, count 0 2006.201.11:03:28.24#ibcon#about to read 3, iclass 31, count 0 2006.201.11:03:28.27#ibcon#read 3, iclass 31, count 0 2006.201.11:03:28.27#ibcon#about to read 4, iclass 31, count 0 2006.201.11:03:28.27#ibcon#read 4, iclass 31, count 0 2006.201.11:03:28.27#ibcon#about to read 5, iclass 31, count 0 2006.201.11:03:28.27#ibcon#read 5, iclass 31, count 0 2006.201.11:03:28.27#ibcon#about to read 6, iclass 31, count 0 2006.201.11:03:28.27#ibcon#read 6, iclass 31, count 0 2006.201.11:03:28.27#ibcon#end of sib2, iclass 31, count 0 2006.201.11:03:28.27#ibcon#*after write, iclass 31, count 0 2006.201.11:03:28.27#ibcon#*before return 0, iclass 31, count 0 2006.201.11:03:28.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:03:28.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:03:28.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.11:03:28.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.11:03:28.27$vck44/vblo=6,719.99 2006.201.11:03:28.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.11:03:28.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.11:03:28.27#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:28.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:28.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:28.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:28.27#ibcon#enter wrdev, iclass 33, count 0 2006.201.11:03:28.27#ibcon#first serial, iclass 33, count 0 2006.201.11:03:28.27#ibcon#enter sib2, iclass 33, count 0 2006.201.11:03:28.27#ibcon#flushed, iclass 33, count 0 2006.201.11:03:28.27#ibcon#about to write, iclass 33, count 0 2006.201.11:03:28.27#ibcon#wrote, iclass 33, count 0 2006.201.11:03:28.27#ibcon#about to read 3, iclass 33, count 0 2006.201.11:03:28.29#ibcon#read 3, iclass 33, count 0 2006.201.11:03:28.29#ibcon#about to read 4, iclass 33, count 0 2006.201.11:03:28.29#ibcon#read 4, iclass 33, count 0 2006.201.11:03:28.29#ibcon#about to read 5, iclass 33, count 0 2006.201.11:03:28.29#ibcon#read 5, iclass 33, count 0 2006.201.11:03:28.29#ibcon#about to read 6, iclass 33, count 0 2006.201.11:03:28.29#ibcon#read 6, iclass 33, count 0 2006.201.11:03:28.29#ibcon#end of sib2, iclass 33, count 0 2006.201.11:03:28.29#ibcon#*mode == 0, iclass 33, count 0 2006.201.11:03:28.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.11:03:28.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:03:28.29#ibcon#*before write, iclass 33, count 0 2006.201.11:03:28.29#ibcon#enter sib2, iclass 33, count 0 2006.201.11:03:28.29#ibcon#flushed, iclass 33, count 0 2006.201.11:03:28.29#ibcon#about to write, iclass 33, count 0 2006.201.11:03:28.29#ibcon#wrote, iclass 33, count 0 2006.201.11:03:28.29#ibcon#about to read 3, iclass 33, count 0 2006.201.11:03:28.33#ibcon#read 3, iclass 33, count 0 2006.201.11:03:28.33#ibcon#about to read 4, iclass 33, count 0 2006.201.11:03:28.33#ibcon#read 4, iclass 33, count 0 2006.201.11:03:28.33#ibcon#about to read 5, iclass 33, count 0 2006.201.11:03:28.33#ibcon#read 5, iclass 33, count 0 2006.201.11:03:28.33#ibcon#about to read 6, iclass 33, count 0 2006.201.11:03:28.33#ibcon#read 6, iclass 33, count 0 2006.201.11:03:28.33#ibcon#end of sib2, iclass 33, count 0 2006.201.11:03:28.33#ibcon#*after write, iclass 33, count 0 2006.201.11:03:28.33#ibcon#*before return 0, iclass 33, count 0 2006.201.11:03:28.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:28.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:03:28.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.11:03:28.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.11:03:28.33$vck44/vb=6,4 2006.201.11:03:28.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.11:03:28.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.11:03:28.33#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:28.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:28.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:28.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:28.39#ibcon#enter wrdev, iclass 35, count 2 2006.201.11:03:28.39#ibcon#first serial, iclass 35, count 2 2006.201.11:03:28.39#ibcon#enter sib2, iclass 35, count 2 2006.201.11:03:28.39#ibcon#flushed, iclass 35, count 2 2006.201.11:03:28.39#ibcon#about to write, iclass 35, count 2 2006.201.11:03:28.39#ibcon#wrote, iclass 35, count 2 2006.201.11:03:28.39#ibcon#about to read 3, iclass 35, count 2 2006.201.11:03:28.41#ibcon#read 3, iclass 35, count 2 2006.201.11:03:28.41#ibcon#about to read 4, iclass 35, count 2 2006.201.11:03:28.41#ibcon#read 4, iclass 35, count 2 2006.201.11:03:28.41#ibcon#about to read 5, iclass 35, count 2 2006.201.11:03:28.41#ibcon#read 5, iclass 35, count 2 2006.201.11:03:28.41#ibcon#about to read 6, iclass 35, count 2 2006.201.11:03:28.41#ibcon#read 6, iclass 35, count 2 2006.201.11:03:28.41#ibcon#end of sib2, iclass 35, count 2 2006.201.11:03:28.41#ibcon#*mode == 0, iclass 35, count 2 2006.201.11:03:28.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.11:03:28.41#ibcon#[27=AT06-04\r\n] 2006.201.11:03:28.41#ibcon#*before write, iclass 35, count 2 2006.201.11:03:28.41#ibcon#enter sib2, iclass 35, count 2 2006.201.11:03:28.41#ibcon#flushed, iclass 35, count 2 2006.201.11:03:28.41#ibcon#about to write, iclass 35, count 2 2006.201.11:03:28.41#ibcon#wrote, iclass 35, count 2 2006.201.11:03:28.41#ibcon#about to read 3, iclass 35, count 2 2006.201.11:03:28.44#ibcon#read 3, iclass 35, count 2 2006.201.11:03:28.44#ibcon#about to read 4, iclass 35, count 2 2006.201.11:03:28.44#ibcon#read 4, iclass 35, count 2 2006.201.11:03:28.44#ibcon#about to read 5, iclass 35, count 2 2006.201.11:03:28.44#ibcon#read 5, iclass 35, count 2 2006.201.11:03:28.44#ibcon#about to read 6, iclass 35, count 2 2006.201.11:03:28.44#ibcon#read 6, iclass 35, count 2 2006.201.11:03:28.44#ibcon#end of sib2, iclass 35, count 2 2006.201.11:03:28.44#ibcon#*after write, iclass 35, count 2 2006.201.11:03:28.44#ibcon#*before return 0, iclass 35, count 2 2006.201.11:03:28.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:28.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:03:28.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.11:03:28.44#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:28.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:28.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:28.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:28.56#ibcon#enter wrdev, iclass 35, count 0 2006.201.11:03:28.56#ibcon#first serial, iclass 35, count 0 2006.201.11:03:28.56#ibcon#enter sib2, iclass 35, count 0 2006.201.11:03:28.56#ibcon#flushed, iclass 35, count 0 2006.201.11:03:28.56#ibcon#about to write, iclass 35, count 0 2006.201.11:03:28.56#ibcon#wrote, iclass 35, count 0 2006.201.11:03:28.56#ibcon#about to read 3, iclass 35, count 0 2006.201.11:03:28.58#ibcon#read 3, iclass 35, count 0 2006.201.11:03:28.58#ibcon#about to read 4, iclass 35, count 0 2006.201.11:03:28.58#ibcon#read 4, iclass 35, count 0 2006.201.11:03:28.58#ibcon#about to read 5, iclass 35, count 0 2006.201.11:03:28.58#ibcon#read 5, iclass 35, count 0 2006.201.11:03:28.58#ibcon#about to read 6, iclass 35, count 0 2006.201.11:03:28.58#ibcon#read 6, iclass 35, count 0 2006.201.11:03:28.58#ibcon#end of sib2, iclass 35, count 0 2006.201.11:03:28.58#ibcon#*mode == 0, iclass 35, count 0 2006.201.11:03:28.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.11:03:28.58#ibcon#[27=USB\r\n] 2006.201.11:03:28.58#ibcon#*before write, iclass 35, count 0 2006.201.11:03:28.58#ibcon#enter sib2, iclass 35, count 0 2006.201.11:03:28.58#ibcon#flushed, iclass 35, count 0 2006.201.11:03:28.58#ibcon#about to write, iclass 35, count 0 2006.201.11:03:28.58#ibcon#wrote, iclass 35, count 0 2006.201.11:03:28.58#ibcon#about to read 3, iclass 35, count 0 2006.201.11:03:28.61#ibcon#read 3, iclass 35, count 0 2006.201.11:03:28.61#ibcon#about to read 4, iclass 35, count 0 2006.201.11:03:28.61#ibcon#read 4, iclass 35, count 0 2006.201.11:03:28.61#ibcon#about to read 5, iclass 35, count 0 2006.201.11:03:28.61#ibcon#read 5, iclass 35, count 0 2006.201.11:03:28.61#ibcon#about to read 6, iclass 35, count 0 2006.201.11:03:28.61#ibcon#read 6, iclass 35, count 0 2006.201.11:03:28.61#ibcon#end of sib2, iclass 35, count 0 2006.201.11:03:28.61#ibcon#*after write, iclass 35, count 0 2006.201.11:03:28.61#ibcon#*before return 0, iclass 35, count 0 2006.201.11:03:28.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:28.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:03:28.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.11:03:28.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.11:03:28.61$vck44/vblo=7,734.99 2006.201.11:03:28.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.11:03:28.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.11:03:28.61#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:28.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:28.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:28.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:28.61#ibcon#enter wrdev, iclass 37, count 0 2006.201.11:03:28.61#ibcon#first serial, iclass 37, count 0 2006.201.11:03:28.61#ibcon#enter sib2, iclass 37, count 0 2006.201.11:03:28.61#ibcon#flushed, iclass 37, count 0 2006.201.11:03:28.61#ibcon#about to write, iclass 37, count 0 2006.201.11:03:28.61#ibcon#wrote, iclass 37, count 0 2006.201.11:03:28.61#ibcon#about to read 3, iclass 37, count 0 2006.201.11:03:28.63#ibcon#read 3, iclass 37, count 0 2006.201.11:03:28.63#ibcon#about to read 4, iclass 37, count 0 2006.201.11:03:28.63#ibcon#read 4, iclass 37, count 0 2006.201.11:03:28.63#ibcon#about to read 5, iclass 37, count 0 2006.201.11:03:28.63#ibcon#read 5, iclass 37, count 0 2006.201.11:03:28.63#ibcon#about to read 6, iclass 37, count 0 2006.201.11:03:28.63#ibcon#read 6, iclass 37, count 0 2006.201.11:03:28.63#ibcon#end of sib2, iclass 37, count 0 2006.201.11:03:28.63#ibcon#*mode == 0, iclass 37, count 0 2006.201.11:03:28.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.11:03:28.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:03:28.63#ibcon#*before write, iclass 37, count 0 2006.201.11:03:28.63#ibcon#enter sib2, iclass 37, count 0 2006.201.11:03:28.63#ibcon#flushed, iclass 37, count 0 2006.201.11:03:28.63#ibcon#about to write, iclass 37, count 0 2006.201.11:03:28.63#ibcon#wrote, iclass 37, count 0 2006.201.11:03:28.63#ibcon#about to read 3, iclass 37, count 0 2006.201.11:03:28.67#ibcon#read 3, iclass 37, count 0 2006.201.11:03:28.67#ibcon#about to read 4, iclass 37, count 0 2006.201.11:03:28.67#ibcon#read 4, iclass 37, count 0 2006.201.11:03:28.67#ibcon#about to read 5, iclass 37, count 0 2006.201.11:03:28.67#ibcon#read 5, iclass 37, count 0 2006.201.11:03:28.67#ibcon#about to read 6, iclass 37, count 0 2006.201.11:03:28.67#ibcon#read 6, iclass 37, count 0 2006.201.11:03:28.67#ibcon#end of sib2, iclass 37, count 0 2006.201.11:03:28.67#ibcon#*after write, iclass 37, count 0 2006.201.11:03:28.67#ibcon#*before return 0, iclass 37, count 0 2006.201.11:03:28.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:28.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:03:28.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.11:03:28.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.11:03:28.67$vck44/vb=7,4 2006.201.11:03:28.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.11:03:28.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.11:03:28.67#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:28.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:28.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:28.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:28.73#ibcon#enter wrdev, iclass 39, count 2 2006.201.11:03:28.73#ibcon#first serial, iclass 39, count 2 2006.201.11:03:28.73#ibcon#enter sib2, iclass 39, count 2 2006.201.11:03:28.73#ibcon#flushed, iclass 39, count 2 2006.201.11:03:28.73#ibcon#about to write, iclass 39, count 2 2006.201.11:03:28.73#ibcon#wrote, iclass 39, count 2 2006.201.11:03:28.73#ibcon#about to read 3, iclass 39, count 2 2006.201.11:03:28.75#ibcon#read 3, iclass 39, count 2 2006.201.11:03:28.75#ibcon#about to read 4, iclass 39, count 2 2006.201.11:03:28.75#ibcon#read 4, iclass 39, count 2 2006.201.11:03:28.75#ibcon#about to read 5, iclass 39, count 2 2006.201.11:03:28.75#ibcon#read 5, iclass 39, count 2 2006.201.11:03:28.75#ibcon#about to read 6, iclass 39, count 2 2006.201.11:03:28.75#ibcon#read 6, iclass 39, count 2 2006.201.11:03:28.75#ibcon#end of sib2, iclass 39, count 2 2006.201.11:03:28.75#ibcon#*mode == 0, iclass 39, count 2 2006.201.11:03:28.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.11:03:28.75#ibcon#[27=AT07-04\r\n] 2006.201.11:03:28.75#ibcon#*before write, iclass 39, count 2 2006.201.11:03:28.75#ibcon#enter sib2, iclass 39, count 2 2006.201.11:03:28.75#ibcon#flushed, iclass 39, count 2 2006.201.11:03:28.75#ibcon#about to write, iclass 39, count 2 2006.201.11:03:28.75#ibcon#wrote, iclass 39, count 2 2006.201.11:03:28.75#ibcon#about to read 3, iclass 39, count 2 2006.201.11:03:28.78#ibcon#read 3, iclass 39, count 2 2006.201.11:03:28.78#ibcon#about to read 4, iclass 39, count 2 2006.201.11:03:28.78#ibcon#read 4, iclass 39, count 2 2006.201.11:03:28.78#ibcon#about to read 5, iclass 39, count 2 2006.201.11:03:28.78#ibcon#read 5, iclass 39, count 2 2006.201.11:03:28.78#ibcon#about to read 6, iclass 39, count 2 2006.201.11:03:28.78#ibcon#read 6, iclass 39, count 2 2006.201.11:03:28.78#ibcon#end of sib2, iclass 39, count 2 2006.201.11:03:28.78#ibcon#*after write, iclass 39, count 2 2006.201.11:03:28.78#ibcon#*before return 0, iclass 39, count 2 2006.201.11:03:28.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:28.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:03:28.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.11:03:28.78#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:28.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:28.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:28.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:28.90#ibcon#enter wrdev, iclass 39, count 0 2006.201.11:03:28.90#ibcon#first serial, iclass 39, count 0 2006.201.11:03:28.90#ibcon#enter sib2, iclass 39, count 0 2006.201.11:03:28.90#ibcon#flushed, iclass 39, count 0 2006.201.11:03:28.90#ibcon#about to write, iclass 39, count 0 2006.201.11:03:28.90#ibcon#wrote, iclass 39, count 0 2006.201.11:03:28.90#ibcon#about to read 3, iclass 39, count 0 2006.201.11:03:28.92#ibcon#read 3, iclass 39, count 0 2006.201.11:03:28.92#ibcon#about to read 4, iclass 39, count 0 2006.201.11:03:28.92#ibcon#read 4, iclass 39, count 0 2006.201.11:03:28.92#ibcon#about to read 5, iclass 39, count 0 2006.201.11:03:28.92#ibcon#read 5, iclass 39, count 0 2006.201.11:03:28.92#ibcon#about to read 6, iclass 39, count 0 2006.201.11:03:28.92#ibcon#read 6, iclass 39, count 0 2006.201.11:03:28.92#ibcon#end of sib2, iclass 39, count 0 2006.201.11:03:28.92#ibcon#*mode == 0, iclass 39, count 0 2006.201.11:03:28.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.11:03:28.92#ibcon#[27=USB\r\n] 2006.201.11:03:28.92#ibcon#*before write, iclass 39, count 0 2006.201.11:03:28.92#ibcon#enter sib2, iclass 39, count 0 2006.201.11:03:28.92#ibcon#flushed, iclass 39, count 0 2006.201.11:03:28.92#ibcon#about to write, iclass 39, count 0 2006.201.11:03:28.92#ibcon#wrote, iclass 39, count 0 2006.201.11:03:28.92#ibcon#about to read 3, iclass 39, count 0 2006.201.11:03:28.95#ibcon#read 3, iclass 39, count 0 2006.201.11:03:28.95#ibcon#about to read 4, iclass 39, count 0 2006.201.11:03:28.95#ibcon#read 4, iclass 39, count 0 2006.201.11:03:28.95#ibcon#about to read 5, iclass 39, count 0 2006.201.11:03:28.95#ibcon#read 5, iclass 39, count 0 2006.201.11:03:28.95#ibcon#about to read 6, iclass 39, count 0 2006.201.11:03:28.95#ibcon#read 6, iclass 39, count 0 2006.201.11:03:28.95#ibcon#end of sib2, iclass 39, count 0 2006.201.11:03:28.95#ibcon#*after write, iclass 39, count 0 2006.201.11:03:28.95#ibcon#*before return 0, iclass 39, count 0 2006.201.11:03:28.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:28.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:03:28.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.11:03:28.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.11:03:28.95$vck44/vblo=8,744.99 2006.201.11:03:28.95#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.11:03:28.95#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.11:03:28.95#ibcon#ireg 17 cls_cnt 0 2006.201.11:03:28.95#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:28.95#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:28.95#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:28.95#ibcon#enter wrdev, iclass 2, count 0 2006.201.11:03:28.95#ibcon#first serial, iclass 2, count 0 2006.201.11:03:28.95#ibcon#enter sib2, iclass 2, count 0 2006.201.11:03:28.95#ibcon#flushed, iclass 2, count 0 2006.201.11:03:28.95#ibcon#about to write, iclass 2, count 0 2006.201.11:03:28.95#ibcon#wrote, iclass 2, count 0 2006.201.11:03:28.95#ibcon#about to read 3, iclass 2, count 0 2006.201.11:03:28.97#ibcon#read 3, iclass 2, count 0 2006.201.11:03:28.97#ibcon#about to read 4, iclass 2, count 0 2006.201.11:03:28.97#ibcon#read 4, iclass 2, count 0 2006.201.11:03:28.97#ibcon#about to read 5, iclass 2, count 0 2006.201.11:03:28.97#ibcon#read 5, iclass 2, count 0 2006.201.11:03:28.97#ibcon#about to read 6, iclass 2, count 0 2006.201.11:03:28.97#ibcon#read 6, iclass 2, count 0 2006.201.11:03:28.97#ibcon#end of sib2, iclass 2, count 0 2006.201.11:03:28.97#ibcon#*mode == 0, iclass 2, count 0 2006.201.11:03:28.97#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.11:03:28.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:03:28.97#ibcon#*before write, iclass 2, count 0 2006.201.11:03:28.97#ibcon#enter sib2, iclass 2, count 0 2006.201.11:03:28.97#ibcon#flushed, iclass 2, count 0 2006.201.11:03:28.97#ibcon#about to write, iclass 2, count 0 2006.201.11:03:28.97#ibcon#wrote, iclass 2, count 0 2006.201.11:03:28.97#ibcon#about to read 3, iclass 2, count 0 2006.201.11:03:29.01#ibcon#read 3, iclass 2, count 0 2006.201.11:03:29.01#ibcon#about to read 4, iclass 2, count 0 2006.201.11:03:29.01#ibcon#read 4, iclass 2, count 0 2006.201.11:03:29.01#ibcon#about to read 5, iclass 2, count 0 2006.201.11:03:29.01#ibcon#read 5, iclass 2, count 0 2006.201.11:03:29.01#ibcon#about to read 6, iclass 2, count 0 2006.201.11:03:29.01#ibcon#read 6, iclass 2, count 0 2006.201.11:03:29.01#ibcon#end of sib2, iclass 2, count 0 2006.201.11:03:29.01#ibcon#*after write, iclass 2, count 0 2006.201.11:03:29.01#ibcon#*before return 0, iclass 2, count 0 2006.201.11:03:29.01#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:29.01#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:03:29.01#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.11:03:29.01#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.11:03:29.01$vck44/vb=8,4 2006.201.11:03:29.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.11:03:29.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.11:03:29.01#ibcon#ireg 11 cls_cnt 2 2006.201.11:03:29.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:29.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:29.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:29.07#ibcon#enter wrdev, iclass 5, count 2 2006.201.11:03:29.07#ibcon#first serial, iclass 5, count 2 2006.201.11:03:29.07#ibcon#enter sib2, iclass 5, count 2 2006.201.11:03:29.07#ibcon#flushed, iclass 5, count 2 2006.201.11:03:29.07#ibcon#about to write, iclass 5, count 2 2006.201.11:03:29.07#ibcon#wrote, iclass 5, count 2 2006.201.11:03:29.07#ibcon#about to read 3, iclass 5, count 2 2006.201.11:03:29.09#ibcon#read 3, iclass 5, count 2 2006.201.11:03:29.09#ibcon#about to read 4, iclass 5, count 2 2006.201.11:03:29.09#ibcon#read 4, iclass 5, count 2 2006.201.11:03:29.09#ibcon#about to read 5, iclass 5, count 2 2006.201.11:03:29.09#ibcon#read 5, iclass 5, count 2 2006.201.11:03:29.09#ibcon#about to read 6, iclass 5, count 2 2006.201.11:03:29.09#ibcon#read 6, iclass 5, count 2 2006.201.11:03:29.09#ibcon#end of sib2, iclass 5, count 2 2006.201.11:03:29.09#ibcon#*mode == 0, iclass 5, count 2 2006.201.11:03:29.09#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.11:03:29.09#ibcon#[27=AT08-04\r\n] 2006.201.11:03:29.09#ibcon#*before write, iclass 5, count 2 2006.201.11:03:29.09#ibcon#enter sib2, iclass 5, count 2 2006.201.11:03:29.09#ibcon#flushed, iclass 5, count 2 2006.201.11:03:29.09#ibcon#about to write, iclass 5, count 2 2006.201.11:03:29.09#ibcon#wrote, iclass 5, count 2 2006.201.11:03:29.09#ibcon#about to read 3, iclass 5, count 2 2006.201.11:03:29.12#ibcon#read 3, iclass 5, count 2 2006.201.11:03:29.12#ibcon#about to read 4, iclass 5, count 2 2006.201.11:03:29.12#ibcon#read 4, iclass 5, count 2 2006.201.11:03:29.12#ibcon#about to read 5, iclass 5, count 2 2006.201.11:03:29.12#ibcon#read 5, iclass 5, count 2 2006.201.11:03:29.12#ibcon#about to read 6, iclass 5, count 2 2006.201.11:03:29.12#ibcon#read 6, iclass 5, count 2 2006.201.11:03:29.12#ibcon#end of sib2, iclass 5, count 2 2006.201.11:03:29.12#ibcon#*after write, iclass 5, count 2 2006.201.11:03:29.12#ibcon#*before return 0, iclass 5, count 2 2006.201.11:03:29.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:29.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:03:29.12#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.11:03:29.12#ibcon#ireg 7 cls_cnt 0 2006.201.11:03:29.12#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:29.24#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:29.24#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:29.24#ibcon#enter wrdev, iclass 5, count 0 2006.201.11:03:29.24#ibcon#first serial, iclass 5, count 0 2006.201.11:03:29.24#ibcon#enter sib2, iclass 5, count 0 2006.201.11:03:29.24#ibcon#flushed, iclass 5, count 0 2006.201.11:03:29.24#ibcon#about to write, iclass 5, count 0 2006.201.11:03:29.24#ibcon#wrote, iclass 5, count 0 2006.201.11:03:29.24#ibcon#about to read 3, iclass 5, count 0 2006.201.11:03:29.26#ibcon#read 3, iclass 5, count 0 2006.201.11:03:29.26#ibcon#about to read 4, iclass 5, count 0 2006.201.11:03:29.26#ibcon#read 4, iclass 5, count 0 2006.201.11:03:29.26#ibcon#about to read 5, iclass 5, count 0 2006.201.11:03:29.26#ibcon#read 5, iclass 5, count 0 2006.201.11:03:29.26#ibcon#about to read 6, iclass 5, count 0 2006.201.11:03:29.26#ibcon#read 6, iclass 5, count 0 2006.201.11:03:29.26#ibcon#end of sib2, iclass 5, count 0 2006.201.11:03:29.26#ibcon#*mode == 0, iclass 5, count 0 2006.201.11:03:29.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.11:03:29.26#ibcon#[27=USB\r\n] 2006.201.11:03:29.26#ibcon#*before write, iclass 5, count 0 2006.201.11:03:29.26#ibcon#enter sib2, iclass 5, count 0 2006.201.11:03:29.26#ibcon#flushed, iclass 5, count 0 2006.201.11:03:29.26#ibcon#about to write, iclass 5, count 0 2006.201.11:03:29.26#ibcon#wrote, iclass 5, count 0 2006.201.11:03:29.26#ibcon#about to read 3, iclass 5, count 0 2006.201.11:03:29.29#ibcon#read 3, iclass 5, count 0 2006.201.11:03:29.29#ibcon#about to read 4, iclass 5, count 0 2006.201.11:03:29.29#ibcon#read 4, iclass 5, count 0 2006.201.11:03:29.29#ibcon#about to read 5, iclass 5, count 0 2006.201.11:03:29.29#ibcon#read 5, iclass 5, count 0 2006.201.11:03:29.29#ibcon#about to read 6, iclass 5, count 0 2006.201.11:03:29.29#ibcon#read 6, iclass 5, count 0 2006.201.11:03:29.29#ibcon#end of sib2, iclass 5, count 0 2006.201.11:03:29.29#ibcon#*after write, iclass 5, count 0 2006.201.11:03:29.29#ibcon#*before return 0, iclass 5, count 0 2006.201.11:03:29.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:29.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:03:29.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.11:03:29.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.11:03:29.29$vck44/vabw=wide 2006.201.11:03:29.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.11:03:29.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.11:03:29.29#ibcon#ireg 8 cls_cnt 0 2006.201.11:03:29.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:29.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:29.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:29.29#ibcon#enter wrdev, iclass 7, count 0 2006.201.11:03:29.29#ibcon#first serial, iclass 7, count 0 2006.201.11:03:29.29#ibcon#enter sib2, iclass 7, count 0 2006.201.11:03:29.29#ibcon#flushed, iclass 7, count 0 2006.201.11:03:29.29#ibcon#about to write, iclass 7, count 0 2006.201.11:03:29.29#ibcon#wrote, iclass 7, count 0 2006.201.11:03:29.29#ibcon#about to read 3, iclass 7, count 0 2006.201.11:03:29.31#ibcon#read 3, iclass 7, count 0 2006.201.11:03:29.31#ibcon#about to read 4, iclass 7, count 0 2006.201.11:03:29.31#ibcon#read 4, iclass 7, count 0 2006.201.11:03:29.31#ibcon#about to read 5, iclass 7, count 0 2006.201.11:03:29.31#ibcon#read 5, iclass 7, count 0 2006.201.11:03:29.31#ibcon#about to read 6, iclass 7, count 0 2006.201.11:03:29.31#ibcon#read 6, iclass 7, count 0 2006.201.11:03:29.31#ibcon#end of sib2, iclass 7, count 0 2006.201.11:03:29.31#ibcon#*mode == 0, iclass 7, count 0 2006.201.11:03:29.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.11:03:29.31#ibcon#[25=BW32\r\n] 2006.201.11:03:29.31#ibcon#*before write, iclass 7, count 0 2006.201.11:03:29.31#ibcon#enter sib2, iclass 7, count 0 2006.201.11:03:29.31#ibcon#flushed, iclass 7, count 0 2006.201.11:03:29.31#ibcon#about to write, iclass 7, count 0 2006.201.11:03:29.31#ibcon#wrote, iclass 7, count 0 2006.201.11:03:29.31#ibcon#about to read 3, iclass 7, count 0 2006.201.11:03:29.34#ibcon#read 3, iclass 7, count 0 2006.201.11:03:29.34#ibcon#about to read 4, iclass 7, count 0 2006.201.11:03:29.34#ibcon#read 4, iclass 7, count 0 2006.201.11:03:29.34#ibcon#about to read 5, iclass 7, count 0 2006.201.11:03:29.34#ibcon#read 5, iclass 7, count 0 2006.201.11:03:29.34#ibcon#about to read 6, iclass 7, count 0 2006.201.11:03:29.34#ibcon#read 6, iclass 7, count 0 2006.201.11:03:29.34#ibcon#end of sib2, iclass 7, count 0 2006.201.11:03:29.34#ibcon#*after write, iclass 7, count 0 2006.201.11:03:29.34#ibcon#*before return 0, iclass 7, count 0 2006.201.11:03:29.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:29.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:03:29.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.11:03:29.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.11:03:29.34$vck44/vbbw=wide 2006.201.11:03:29.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.11:03:29.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.11:03:29.34#ibcon#ireg 8 cls_cnt 0 2006.201.11:03:29.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:03:29.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:03:29.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:03:29.41#ibcon#enter wrdev, iclass 11, count 0 2006.201.11:03:29.41#ibcon#first serial, iclass 11, count 0 2006.201.11:03:29.41#ibcon#enter sib2, iclass 11, count 0 2006.201.11:03:29.41#ibcon#flushed, iclass 11, count 0 2006.201.11:03:29.41#ibcon#about to write, iclass 11, count 0 2006.201.11:03:29.41#ibcon#wrote, iclass 11, count 0 2006.201.11:03:29.41#ibcon#about to read 3, iclass 11, count 0 2006.201.11:03:29.43#ibcon#read 3, iclass 11, count 0 2006.201.11:03:29.43#ibcon#about to read 4, iclass 11, count 0 2006.201.11:03:29.43#ibcon#read 4, iclass 11, count 0 2006.201.11:03:29.43#ibcon#about to read 5, iclass 11, count 0 2006.201.11:03:29.43#ibcon#read 5, iclass 11, count 0 2006.201.11:03:29.43#ibcon#about to read 6, iclass 11, count 0 2006.201.11:03:29.43#ibcon#read 6, iclass 11, count 0 2006.201.11:03:29.43#ibcon#end of sib2, iclass 11, count 0 2006.201.11:03:29.43#ibcon#*mode == 0, iclass 11, count 0 2006.201.11:03:29.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.11:03:29.43#ibcon#[27=BW32\r\n] 2006.201.11:03:29.43#ibcon#*before write, iclass 11, count 0 2006.201.11:03:29.43#ibcon#enter sib2, iclass 11, count 0 2006.201.11:03:29.43#ibcon#flushed, iclass 11, count 0 2006.201.11:03:29.43#ibcon#about to write, iclass 11, count 0 2006.201.11:03:29.43#ibcon#wrote, iclass 11, count 0 2006.201.11:03:29.43#ibcon#about to read 3, iclass 11, count 0 2006.201.11:03:29.46#ibcon#read 3, iclass 11, count 0 2006.201.11:03:29.46#ibcon#about to read 4, iclass 11, count 0 2006.201.11:03:29.46#ibcon#read 4, iclass 11, count 0 2006.201.11:03:29.46#ibcon#about to read 5, iclass 11, count 0 2006.201.11:03:29.46#ibcon#read 5, iclass 11, count 0 2006.201.11:03:29.46#ibcon#about to read 6, iclass 11, count 0 2006.201.11:03:29.46#ibcon#read 6, iclass 11, count 0 2006.201.11:03:29.46#ibcon#end of sib2, iclass 11, count 0 2006.201.11:03:29.46#ibcon#*after write, iclass 11, count 0 2006.201.11:03:29.46#ibcon#*before return 0, iclass 11, count 0 2006.201.11:03:29.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:03:29.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:03:29.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.11:03:29.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.11:03:29.46$setupk4/ifdk4 2006.201.11:03:29.46$ifdk4/lo= 2006.201.11:03:29.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:03:29.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:03:29.46$ifdk4/patch= 2006.201.11:03:29.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:03:29.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:03:29.46$setupk4/!*+20s 2006.201.11:03:35.20#abcon#<5=/04 1.6 2.8 21.42 991003.8\r\n> 2006.201.11:03:35.22#abcon#{5=INTERFACE CLEAR} 2006.201.11:03:35.28#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:03:43.14#trakl#Source acquired 2006.201.11:03:43.14#flagr#flagr/antenna,acquired 2006.201.11:03:43.91$setupk4/"tpicd 2006.201.11:03:43.91$setupk4/echo=off 2006.201.11:03:43.91$setupk4/xlog=off 2006.201.11:03:43.91:!2006.201.11:08:30 2006.201.11:08:30.00:preob 2006.201.11:08:30.14/onsource/TRACKING 2006.201.11:08:30.14:!2006.201.11:08:40 2006.201.11:08:40.00:"tape 2006.201.11:08:40.00:"st=record 2006.201.11:08:40.00:data_valid=on 2006.201.11:08:40.00:midob 2006.201.11:08:40.14/onsource/TRACKING 2006.201.11:08:40.14/wx/21.40,1003.9,99 2006.201.11:08:40.33/cable/+6.4718E-03 2006.201.11:08:41.42/va/01,08,usb,yes,41,44 2006.201.11:08:41.42/va/02,07,usb,yes,45,46 2006.201.11:08:41.42/va/03,08,usb,yes,40,42 2006.201.11:08:41.42/va/04,07,usb,yes,45,47 2006.201.11:08:41.42/va/05,04,usb,yes,40,41 2006.201.11:08:41.42/va/06,05,usb,yes,40,40 2006.201.11:08:41.42/va/07,05,usb,yes,39,41 2006.201.11:08:41.42/va/08,04,usb,yes,39,46 2006.201.11:08:41.65/valo/01,524.99,yes,locked 2006.201.11:08:41.65/valo/02,534.99,yes,locked 2006.201.11:08:41.65/valo/03,564.99,yes,locked 2006.201.11:08:41.65/valo/04,624.99,yes,locked 2006.201.11:08:41.65/valo/05,734.99,yes,locked 2006.201.11:08:41.65/valo/06,814.99,yes,locked 2006.201.11:08:41.65/valo/07,864.99,yes,locked 2006.201.11:08:41.65/valo/08,884.99,yes,locked 2006.201.11:08:42.74/vb/01,04,usb,yes,36,33 2006.201.11:08:42.74/vb/02,05,usb,yes,34,34 2006.201.11:08:42.74/vb/03,04,usb,yes,35,39 2006.201.11:08:42.74/vb/04,05,usb,yes,35,34 2006.201.11:08:42.74/vb/05,04,usb,yes,32,35 2006.201.11:08:42.74/vb/06,04,usb,yes,37,33 2006.201.11:08:42.74/vb/07,04,usb,yes,37,37 2006.201.11:08:42.74/vb/08,04,usb,yes,34,38 2006.201.11:08:42.98/vblo/01,629.99,yes,locked 2006.201.11:08:42.98/vblo/02,634.99,yes,locked 2006.201.11:08:42.98/vblo/03,649.99,yes,locked 2006.201.11:08:42.98/vblo/04,679.99,yes,locked 2006.201.11:08:42.98/vblo/05,709.99,yes,locked 2006.201.11:08:42.98/vblo/06,719.99,yes,locked 2006.201.11:08:42.98/vblo/07,734.99,yes,locked 2006.201.11:08:42.98/vblo/08,744.99,yes,locked 2006.201.11:08:43.13/vabw/8 2006.201.11:08:43.28/vbbw/8 2006.201.11:08:43.37/xfe/off,on,14.7 2006.201.11:08:43.75/ifatt/23,28,28,28 2006.201.11:08:44.05/fmout-gps/S +4.60E-07 2006.201.11:08:44.12:!2006.201.11:09:20 2006.201.11:09:20.00:data_valid=off 2006.201.11:09:20.00:"et 2006.201.11:09:20.00:!+3s 2006.201.11:09:23.02:"tape 2006.201.11:09:23.02:postob 2006.201.11:09:23.16/cable/+6.4717E-03 2006.201.11:09:23.16/wx/21.40,1003.9,99 2006.201.11:09:23.22/fmout-gps/S +4.61E-07 2006.201.11:09:23.22:scan_name=201-1110,jd0607,100 2006.201.11:09:23.22:source=3c274,123049.42,122328.0,2000.0,ccw 2006.201.11:09:25.14#flagr#flagr/antenna,new-source 2006.201.11:09:25.14:checkk5 2006.201.11:09:25.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:09:25.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:09:26.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:09:26.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:09:27.01/chk_obsdata//k5ts1/T2011108??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:09:27.38/chk_obsdata//k5ts2/T2011108??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:09:27.75/chk_obsdata//k5ts3/T2011108??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:09:28.11/chk_obsdata//k5ts4/T2011108??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:09:28.80/k5log//k5ts1_log_newline 2006.201.11:09:29.49/k5log//k5ts2_log_newline 2006.201.11:09:30.17/k5log//k5ts3_log_newline 2006.201.11:09:30.85/k5log//k5ts4_log_newline 2006.201.11:09:30.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:09:30.88:setupk4=1 2006.201.11:09:30.88$setupk4/echo=on 2006.201.11:09:30.88$setupk4/pcalon 2006.201.11:09:30.88$pcalon/"no phase cal control is implemented here 2006.201.11:09:30.88$setupk4/"tpicd=stop 2006.201.11:09:30.88$setupk4/"rec=synch_on 2006.201.11:09:30.88$setupk4/"rec_mode=128 2006.201.11:09:30.88$setupk4/!* 2006.201.11:09:30.88$setupk4/recpk4 2006.201.11:09:30.88$recpk4/recpatch= 2006.201.11:09:30.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:09:30.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:09:30.88$setupk4/vck44 2006.201.11:09:30.88$vck44/valo=1,524.99 2006.201.11:09:30.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.11:09:30.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.11:09:30.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:30.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:30.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:30.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:30.88#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:09:30.88#ibcon#first serial, iclass 12, count 0 2006.201.11:09:30.88#ibcon#enter sib2, iclass 12, count 0 2006.201.11:09:30.88#ibcon#flushed, iclass 12, count 0 2006.201.11:09:30.88#ibcon#about to write, iclass 12, count 0 2006.201.11:09:30.88#ibcon#wrote, iclass 12, count 0 2006.201.11:09:30.88#ibcon#about to read 3, iclass 12, count 0 2006.201.11:09:30.92#ibcon#read 3, iclass 12, count 0 2006.201.11:09:30.92#ibcon#about to read 4, iclass 12, count 0 2006.201.11:09:30.92#ibcon#read 4, iclass 12, count 0 2006.201.11:09:30.92#ibcon#about to read 5, iclass 12, count 0 2006.201.11:09:30.92#ibcon#read 5, iclass 12, count 0 2006.201.11:09:30.92#ibcon#about to read 6, iclass 12, count 0 2006.201.11:09:30.92#ibcon#read 6, iclass 12, count 0 2006.201.11:09:30.92#ibcon#end of sib2, iclass 12, count 0 2006.201.11:09:30.92#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:09:30.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:09:30.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:09:30.92#ibcon#*before write, iclass 12, count 0 2006.201.11:09:30.92#ibcon#enter sib2, iclass 12, count 0 2006.201.11:09:30.92#ibcon#flushed, iclass 12, count 0 2006.201.11:09:30.92#ibcon#about to write, iclass 12, count 0 2006.201.11:09:30.92#ibcon#wrote, iclass 12, count 0 2006.201.11:09:30.92#ibcon#about to read 3, iclass 12, count 0 2006.201.11:09:30.97#ibcon#read 3, iclass 12, count 0 2006.201.11:09:30.97#ibcon#about to read 4, iclass 12, count 0 2006.201.11:09:30.97#ibcon#read 4, iclass 12, count 0 2006.201.11:09:30.97#ibcon#about to read 5, iclass 12, count 0 2006.201.11:09:30.97#ibcon#read 5, iclass 12, count 0 2006.201.11:09:30.97#ibcon#about to read 6, iclass 12, count 0 2006.201.11:09:30.97#ibcon#read 6, iclass 12, count 0 2006.201.11:09:30.97#ibcon#end of sib2, iclass 12, count 0 2006.201.11:09:30.97#ibcon#*after write, iclass 12, count 0 2006.201.11:09:30.97#ibcon#*before return 0, iclass 12, count 0 2006.201.11:09:30.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:30.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:30.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:09:30.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:09:30.97$vck44/va=1,8 2006.201.11:09:30.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.11:09:30.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.11:09:30.97#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:30.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:30.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:30.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:30.97#ibcon#enter wrdev, iclass 14, count 2 2006.201.11:09:30.97#ibcon#first serial, iclass 14, count 2 2006.201.11:09:30.97#ibcon#enter sib2, iclass 14, count 2 2006.201.11:09:30.97#ibcon#flushed, iclass 14, count 2 2006.201.11:09:30.97#ibcon#about to write, iclass 14, count 2 2006.201.11:09:30.97#ibcon#wrote, iclass 14, count 2 2006.201.11:09:30.97#ibcon#about to read 3, iclass 14, count 2 2006.201.11:09:30.99#ibcon#read 3, iclass 14, count 2 2006.201.11:09:30.99#ibcon#about to read 4, iclass 14, count 2 2006.201.11:09:30.99#ibcon#read 4, iclass 14, count 2 2006.201.11:09:30.99#ibcon#about to read 5, iclass 14, count 2 2006.201.11:09:30.99#ibcon#read 5, iclass 14, count 2 2006.201.11:09:30.99#ibcon#about to read 6, iclass 14, count 2 2006.201.11:09:30.99#ibcon#read 6, iclass 14, count 2 2006.201.11:09:30.99#ibcon#end of sib2, iclass 14, count 2 2006.201.11:09:30.99#ibcon#*mode == 0, iclass 14, count 2 2006.201.11:09:30.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.11:09:30.99#ibcon#[25=AT01-08\r\n] 2006.201.11:09:30.99#ibcon#*before write, iclass 14, count 2 2006.201.11:09:30.99#ibcon#enter sib2, iclass 14, count 2 2006.201.11:09:30.99#ibcon#flushed, iclass 14, count 2 2006.201.11:09:30.99#ibcon#about to write, iclass 14, count 2 2006.201.11:09:30.99#ibcon#wrote, iclass 14, count 2 2006.201.11:09:30.99#ibcon#about to read 3, iclass 14, count 2 2006.201.11:09:31.02#ibcon#read 3, iclass 14, count 2 2006.201.11:09:31.02#ibcon#about to read 4, iclass 14, count 2 2006.201.11:09:31.02#ibcon#read 4, iclass 14, count 2 2006.201.11:09:31.02#ibcon#about to read 5, iclass 14, count 2 2006.201.11:09:31.02#ibcon#read 5, iclass 14, count 2 2006.201.11:09:31.02#ibcon#about to read 6, iclass 14, count 2 2006.201.11:09:31.02#ibcon#read 6, iclass 14, count 2 2006.201.11:09:31.02#ibcon#end of sib2, iclass 14, count 2 2006.201.11:09:31.02#ibcon#*after write, iclass 14, count 2 2006.201.11:09:31.02#ibcon#*before return 0, iclass 14, count 2 2006.201.11:09:31.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:31.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:31.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.11:09:31.02#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:31.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:31.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:31.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:31.14#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:09:31.14#ibcon#first serial, iclass 14, count 0 2006.201.11:09:31.14#ibcon#enter sib2, iclass 14, count 0 2006.201.11:09:31.14#ibcon#flushed, iclass 14, count 0 2006.201.11:09:31.14#ibcon#about to write, iclass 14, count 0 2006.201.11:09:31.14#ibcon#wrote, iclass 14, count 0 2006.201.11:09:31.14#ibcon#about to read 3, iclass 14, count 0 2006.201.11:09:31.16#ibcon#read 3, iclass 14, count 0 2006.201.11:09:31.16#ibcon#about to read 4, iclass 14, count 0 2006.201.11:09:31.16#ibcon#read 4, iclass 14, count 0 2006.201.11:09:31.16#ibcon#about to read 5, iclass 14, count 0 2006.201.11:09:31.16#ibcon#read 5, iclass 14, count 0 2006.201.11:09:31.16#ibcon#about to read 6, iclass 14, count 0 2006.201.11:09:31.16#ibcon#read 6, iclass 14, count 0 2006.201.11:09:31.16#ibcon#end of sib2, iclass 14, count 0 2006.201.11:09:31.16#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:09:31.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:09:31.16#ibcon#[25=USB\r\n] 2006.201.11:09:31.16#ibcon#*before write, iclass 14, count 0 2006.201.11:09:31.16#ibcon#enter sib2, iclass 14, count 0 2006.201.11:09:31.16#ibcon#flushed, iclass 14, count 0 2006.201.11:09:31.16#ibcon#about to write, iclass 14, count 0 2006.201.11:09:31.16#ibcon#wrote, iclass 14, count 0 2006.201.11:09:31.16#ibcon#about to read 3, iclass 14, count 0 2006.201.11:09:31.19#ibcon#read 3, iclass 14, count 0 2006.201.11:09:31.19#ibcon#about to read 4, iclass 14, count 0 2006.201.11:09:31.19#ibcon#read 4, iclass 14, count 0 2006.201.11:09:31.19#ibcon#about to read 5, iclass 14, count 0 2006.201.11:09:31.19#ibcon#read 5, iclass 14, count 0 2006.201.11:09:31.19#ibcon#about to read 6, iclass 14, count 0 2006.201.11:09:31.19#ibcon#read 6, iclass 14, count 0 2006.201.11:09:31.19#ibcon#end of sib2, iclass 14, count 0 2006.201.11:09:31.19#ibcon#*after write, iclass 14, count 0 2006.201.11:09:31.19#ibcon#*before return 0, iclass 14, count 0 2006.201.11:09:31.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:31.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:31.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:09:31.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:09:31.19$vck44/valo=2,534.99 2006.201.11:09:31.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.11:09:31.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.11:09:31.19#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:31.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:09:31.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:09:31.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:09:31.19#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:09:31.19#ibcon#first serial, iclass 17, count 0 2006.201.11:09:31.19#ibcon#enter sib2, iclass 17, count 0 2006.201.11:09:31.19#ibcon#flushed, iclass 17, count 0 2006.201.11:09:31.19#ibcon#about to write, iclass 17, count 0 2006.201.11:09:31.19#ibcon#wrote, iclass 17, count 0 2006.201.11:09:31.19#ibcon#about to read 3, iclass 17, count 0 2006.201.11:09:31.21#ibcon#read 3, iclass 17, count 0 2006.201.11:09:31.21#ibcon#about to read 4, iclass 17, count 0 2006.201.11:09:31.21#ibcon#read 4, iclass 17, count 0 2006.201.11:09:31.21#ibcon#about to read 5, iclass 17, count 0 2006.201.11:09:31.21#ibcon#read 5, iclass 17, count 0 2006.201.11:09:31.21#ibcon#about to read 6, iclass 17, count 0 2006.201.11:09:31.21#ibcon#read 6, iclass 17, count 0 2006.201.11:09:31.21#ibcon#end of sib2, iclass 17, count 0 2006.201.11:09:31.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:09:31.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:09:31.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:09:31.21#ibcon#*before write, iclass 17, count 0 2006.201.11:09:31.21#ibcon#enter sib2, iclass 17, count 0 2006.201.11:09:31.21#ibcon#flushed, iclass 17, count 0 2006.201.11:09:31.21#ibcon#about to write, iclass 17, count 0 2006.201.11:09:31.21#ibcon#wrote, iclass 17, count 0 2006.201.11:09:31.21#ibcon#about to read 3, iclass 17, count 0 2006.201.11:09:31.23#abcon#<5=/04 1.5 2.8 21.40 991003.9\r\n> 2006.201.11:09:31.25#abcon#{5=INTERFACE CLEAR} 2006.201.11:09:31.26#ibcon#read 3, iclass 17, count 0 2006.201.11:09:31.26#ibcon#about to read 4, iclass 17, count 0 2006.201.11:09:31.26#ibcon#read 4, iclass 17, count 0 2006.201.11:09:31.26#ibcon#about to read 5, iclass 17, count 0 2006.201.11:09:31.26#ibcon#read 5, iclass 17, count 0 2006.201.11:09:31.26#ibcon#about to read 6, iclass 17, count 0 2006.201.11:09:31.26#ibcon#read 6, iclass 17, count 0 2006.201.11:09:31.26#ibcon#end of sib2, iclass 17, count 0 2006.201.11:09:31.26#ibcon#*after write, iclass 17, count 0 2006.201.11:09:31.26#ibcon#*before return 0, iclass 17, count 0 2006.201.11:09:31.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:09:31.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:09:31.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:09:31.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:09:31.26$vck44/va=2,7 2006.201.11:09:31.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.11:09:31.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.11:09:31.26#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:31.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:09:31.31#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:09:31.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:09:31.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:09:31.31#ibcon#enter wrdev, iclass 21, count 2 2006.201.11:09:31.31#ibcon#first serial, iclass 21, count 2 2006.201.11:09:31.31#ibcon#enter sib2, iclass 21, count 2 2006.201.11:09:31.31#ibcon#flushed, iclass 21, count 2 2006.201.11:09:31.31#ibcon#about to write, iclass 21, count 2 2006.201.11:09:31.31#ibcon#wrote, iclass 21, count 2 2006.201.11:09:31.31#ibcon#about to read 3, iclass 21, count 2 2006.201.11:09:31.33#ibcon#read 3, iclass 21, count 2 2006.201.11:09:31.33#ibcon#about to read 4, iclass 21, count 2 2006.201.11:09:31.33#ibcon#read 4, iclass 21, count 2 2006.201.11:09:31.33#ibcon#about to read 5, iclass 21, count 2 2006.201.11:09:31.33#ibcon#read 5, iclass 21, count 2 2006.201.11:09:31.33#ibcon#about to read 6, iclass 21, count 2 2006.201.11:09:31.33#ibcon#read 6, iclass 21, count 2 2006.201.11:09:31.33#ibcon#end of sib2, iclass 21, count 2 2006.201.11:09:31.33#ibcon#*mode == 0, iclass 21, count 2 2006.201.11:09:31.33#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.11:09:31.33#ibcon#[25=AT02-07\r\n] 2006.201.11:09:31.33#ibcon#*before write, iclass 21, count 2 2006.201.11:09:31.33#ibcon#enter sib2, iclass 21, count 2 2006.201.11:09:31.33#ibcon#flushed, iclass 21, count 2 2006.201.11:09:31.33#ibcon#about to write, iclass 21, count 2 2006.201.11:09:31.33#ibcon#wrote, iclass 21, count 2 2006.201.11:09:31.33#ibcon#about to read 3, iclass 21, count 2 2006.201.11:09:31.36#ibcon#read 3, iclass 21, count 2 2006.201.11:09:31.36#ibcon#about to read 4, iclass 21, count 2 2006.201.11:09:31.36#ibcon#read 4, iclass 21, count 2 2006.201.11:09:31.36#ibcon#about to read 5, iclass 21, count 2 2006.201.11:09:31.36#ibcon#read 5, iclass 21, count 2 2006.201.11:09:31.36#ibcon#about to read 6, iclass 21, count 2 2006.201.11:09:31.36#ibcon#read 6, iclass 21, count 2 2006.201.11:09:31.36#ibcon#end of sib2, iclass 21, count 2 2006.201.11:09:31.36#ibcon#*after write, iclass 21, count 2 2006.201.11:09:31.36#ibcon#*before return 0, iclass 21, count 2 2006.201.11:09:31.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:09:31.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:09:31.36#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.11:09:31.36#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:31.36#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:09:31.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:09:31.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:09:31.48#ibcon#enter wrdev, iclass 21, count 0 2006.201.11:09:31.48#ibcon#first serial, iclass 21, count 0 2006.201.11:09:31.48#ibcon#enter sib2, iclass 21, count 0 2006.201.11:09:31.48#ibcon#flushed, iclass 21, count 0 2006.201.11:09:31.48#ibcon#about to write, iclass 21, count 0 2006.201.11:09:31.48#ibcon#wrote, iclass 21, count 0 2006.201.11:09:31.48#ibcon#about to read 3, iclass 21, count 0 2006.201.11:09:31.50#ibcon#read 3, iclass 21, count 0 2006.201.11:09:31.50#ibcon#about to read 4, iclass 21, count 0 2006.201.11:09:31.50#ibcon#read 4, iclass 21, count 0 2006.201.11:09:31.50#ibcon#about to read 5, iclass 21, count 0 2006.201.11:09:31.50#ibcon#read 5, iclass 21, count 0 2006.201.11:09:31.50#ibcon#about to read 6, iclass 21, count 0 2006.201.11:09:31.50#ibcon#read 6, iclass 21, count 0 2006.201.11:09:31.50#ibcon#end of sib2, iclass 21, count 0 2006.201.11:09:31.50#ibcon#*mode == 0, iclass 21, count 0 2006.201.11:09:31.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.11:09:31.50#ibcon#[25=USB\r\n] 2006.201.11:09:31.50#ibcon#*before write, iclass 21, count 0 2006.201.11:09:31.50#ibcon#enter sib2, iclass 21, count 0 2006.201.11:09:31.50#ibcon#flushed, iclass 21, count 0 2006.201.11:09:31.50#ibcon#about to write, iclass 21, count 0 2006.201.11:09:31.50#ibcon#wrote, iclass 21, count 0 2006.201.11:09:31.50#ibcon#about to read 3, iclass 21, count 0 2006.201.11:09:31.53#ibcon#read 3, iclass 21, count 0 2006.201.11:09:31.53#ibcon#about to read 4, iclass 21, count 0 2006.201.11:09:31.53#ibcon#read 4, iclass 21, count 0 2006.201.11:09:31.53#ibcon#about to read 5, iclass 21, count 0 2006.201.11:09:31.53#ibcon#read 5, iclass 21, count 0 2006.201.11:09:31.53#ibcon#about to read 6, iclass 21, count 0 2006.201.11:09:31.53#ibcon#read 6, iclass 21, count 0 2006.201.11:09:31.53#ibcon#end of sib2, iclass 21, count 0 2006.201.11:09:31.53#ibcon#*after write, iclass 21, count 0 2006.201.11:09:31.53#ibcon#*before return 0, iclass 21, count 0 2006.201.11:09:31.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:09:31.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:09:31.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.11:09:31.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.11:09:31.53$vck44/valo=3,564.99 2006.201.11:09:31.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.11:09:31.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.11:09:31.53#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:31.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:31.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:31.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:31.53#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:09:31.53#ibcon#first serial, iclass 24, count 0 2006.201.11:09:31.53#ibcon#enter sib2, iclass 24, count 0 2006.201.11:09:31.53#ibcon#flushed, iclass 24, count 0 2006.201.11:09:31.53#ibcon#about to write, iclass 24, count 0 2006.201.11:09:31.53#ibcon#wrote, iclass 24, count 0 2006.201.11:09:31.53#ibcon#about to read 3, iclass 24, count 0 2006.201.11:09:31.55#ibcon#read 3, iclass 24, count 0 2006.201.11:09:31.55#ibcon#about to read 4, iclass 24, count 0 2006.201.11:09:31.55#ibcon#read 4, iclass 24, count 0 2006.201.11:09:31.55#ibcon#about to read 5, iclass 24, count 0 2006.201.11:09:31.55#ibcon#read 5, iclass 24, count 0 2006.201.11:09:31.55#ibcon#about to read 6, iclass 24, count 0 2006.201.11:09:31.55#ibcon#read 6, iclass 24, count 0 2006.201.11:09:31.55#ibcon#end of sib2, iclass 24, count 0 2006.201.11:09:31.55#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:09:31.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:09:31.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:09:31.55#ibcon#*before write, iclass 24, count 0 2006.201.11:09:31.55#ibcon#enter sib2, iclass 24, count 0 2006.201.11:09:31.55#ibcon#flushed, iclass 24, count 0 2006.201.11:09:31.55#ibcon#about to write, iclass 24, count 0 2006.201.11:09:31.55#ibcon#wrote, iclass 24, count 0 2006.201.11:09:31.55#ibcon#about to read 3, iclass 24, count 0 2006.201.11:09:31.60#ibcon#read 3, iclass 24, count 0 2006.201.11:09:31.60#ibcon#about to read 4, iclass 24, count 0 2006.201.11:09:31.60#ibcon#read 4, iclass 24, count 0 2006.201.11:09:31.60#ibcon#about to read 5, iclass 24, count 0 2006.201.11:09:31.60#ibcon#read 5, iclass 24, count 0 2006.201.11:09:31.60#ibcon#about to read 6, iclass 24, count 0 2006.201.11:09:31.60#ibcon#read 6, iclass 24, count 0 2006.201.11:09:31.60#ibcon#end of sib2, iclass 24, count 0 2006.201.11:09:31.60#ibcon#*after write, iclass 24, count 0 2006.201.11:09:31.60#ibcon#*before return 0, iclass 24, count 0 2006.201.11:09:31.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:31.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:31.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:09:31.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:09:31.60$vck44/va=3,8 2006.201.11:09:31.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.11:09:31.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.11:09:31.60#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:31.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:31.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:31.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:31.65#ibcon#enter wrdev, iclass 26, count 2 2006.201.11:09:31.65#ibcon#first serial, iclass 26, count 2 2006.201.11:09:31.65#ibcon#enter sib2, iclass 26, count 2 2006.201.11:09:31.65#ibcon#flushed, iclass 26, count 2 2006.201.11:09:31.65#ibcon#about to write, iclass 26, count 2 2006.201.11:09:31.65#ibcon#wrote, iclass 26, count 2 2006.201.11:09:31.65#ibcon#about to read 3, iclass 26, count 2 2006.201.11:09:31.67#ibcon#read 3, iclass 26, count 2 2006.201.11:09:31.67#ibcon#about to read 4, iclass 26, count 2 2006.201.11:09:31.67#ibcon#read 4, iclass 26, count 2 2006.201.11:09:31.67#ibcon#about to read 5, iclass 26, count 2 2006.201.11:09:31.67#ibcon#read 5, iclass 26, count 2 2006.201.11:09:31.67#ibcon#about to read 6, iclass 26, count 2 2006.201.11:09:31.67#ibcon#read 6, iclass 26, count 2 2006.201.11:09:31.67#ibcon#end of sib2, iclass 26, count 2 2006.201.11:09:31.67#ibcon#*mode == 0, iclass 26, count 2 2006.201.11:09:31.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.11:09:31.67#ibcon#[25=AT03-08\r\n] 2006.201.11:09:31.67#ibcon#*before write, iclass 26, count 2 2006.201.11:09:31.67#ibcon#enter sib2, iclass 26, count 2 2006.201.11:09:31.67#ibcon#flushed, iclass 26, count 2 2006.201.11:09:31.67#ibcon#about to write, iclass 26, count 2 2006.201.11:09:31.67#ibcon#wrote, iclass 26, count 2 2006.201.11:09:31.67#ibcon#about to read 3, iclass 26, count 2 2006.201.11:09:31.70#ibcon#read 3, iclass 26, count 2 2006.201.11:09:31.70#ibcon#about to read 4, iclass 26, count 2 2006.201.11:09:31.70#ibcon#read 4, iclass 26, count 2 2006.201.11:09:31.70#ibcon#about to read 5, iclass 26, count 2 2006.201.11:09:31.70#ibcon#read 5, iclass 26, count 2 2006.201.11:09:31.70#ibcon#about to read 6, iclass 26, count 2 2006.201.11:09:31.70#ibcon#read 6, iclass 26, count 2 2006.201.11:09:31.70#ibcon#end of sib2, iclass 26, count 2 2006.201.11:09:31.70#ibcon#*after write, iclass 26, count 2 2006.201.11:09:31.70#ibcon#*before return 0, iclass 26, count 2 2006.201.11:09:31.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:31.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:31.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.11:09:31.70#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:31.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:31.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:31.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:31.82#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:09:31.82#ibcon#first serial, iclass 26, count 0 2006.201.11:09:31.82#ibcon#enter sib2, iclass 26, count 0 2006.201.11:09:31.82#ibcon#flushed, iclass 26, count 0 2006.201.11:09:31.82#ibcon#about to write, iclass 26, count 0 2006.201.11:09:31.82#ibcon#wrote, iclass 26, count 0 2006.201.11:09:31.82#ibcon#about to read 3, iclass 26, count 0 2006.201.11:09:31.84#ibcon#read 3, iclass 26, count 0 2006.201.11:09:31.84#ibcon#about to read 4, iclass 26, count 0 2006.201.11:09:31.84#ibcon#read 4, iclass 26, count 0 2006.201.11:09:31.84#ibcon#about to read 5, iclass 26, count 0 2006.201.11:09:31.84#ibcon#read 5, iclass 26, count 0 2006.201.11:09:31.84#ibcon#about to read 6, iclass 26, count 0 2006.201.11:09:31.84#ibcon#read 6, iclass 26, count 0 2006.201.11:09:31.84#ibcon#end of sib2, iclass 26, count 0 2006.201.11:09:31.84#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:09:31.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:09:31.84#ibcon#[25=USB\r\n] 2006.201.11:09:31.84#ibcon#*before write, iclass 26, count 0 2006.201.11:09:31.84#ibcon#enter sib2, iclass 26, count 0 2006.201.11:09:31.84#ibcon#flushed, iclass 26, count 0 2006.201.11:09:31.84#ibcon#about to write, iclass 26, count 0 2006.201.11:09:31.84#ibcon#wrote, iclass 26, count 0 2006.201.11:09:31.84#ibcon#about to read 3, iclass 26, count 0 2006.201.11:09:31.87#ibcon#read 3, iclass 26, count 0 2006.201.11:09:31.87#ibcon#about to read 4, iclass 26, count 0 2006.201.11:09:31.87#ibcon#read 4, iclass 26, count 0 2006.201.11:09:31.87#ibcon#about to read 5, iclass 26, count 0 2006.201.11:09:31.87#ibcon#read 5, iclass 26, count 0 2006.201.11:09:31.87#ibcon#about to read 6, iclass 26, count 0 2006.201.11:09:31.87#ibcon#read 6, iclass 26, count 0 2006.201.11:09:31.87#ibcon#end of sib2, iclass 26, count 0 2006.201.11:09:31.87#ibcon#*after write, iclass 26, count 0 2006.201.11:09:31.87#ibcon#*before return 0, iclass 26, count 0 2006.201.11:09:31.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:31.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:31.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:09:31.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:09:31.87$vck44/valo=4,624.99 2006.201.11:09:31.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.11:09:31.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.11:09:31.87#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:31.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:31.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:31.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:31.87#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:09:31.87#ibcon#first serial, iclass 28, count 0 2006.201.11:09:31.87#ibcon#enter sib2, iclass 28, count 0 2006.201.11:09:31.87#ibcon#flushed, iclass 28, count 0 2006.201.11:09:31.87#ibcon#about to write, iclass 28, count 0 2006.201.11:09:31.87#ibcon#wrote, iclass 28, count 0 2006.201.11:09:31.87#ibcon#about to read 3, iclass 28, count 0 2006.201.11:09:31.89#ibcon#read 3, iclass 28, count 0 2006.201.11:09:31.89#ibcon#about to read 4, iclass 28, count 0 2006.201.11:09:31.89#ibcon#read 4, iclass 28, count 0 2006.201.11:09:31.89#ibcon#about to read 5, iclass 28, count 0 2006.201.11:09:31.89#ibcon#read 5, iclass 28, count 0 2006.201.11:09:31.89#ibcon#about to read 6, iclass 28, count 0 2006.201.11:09:31.89#ibcon#read 6, iclass 28, count 0 2006.201.11:09:31.89#ibcon#end of sib2, iclass 28, count 0 2006.201.11:09:31.89#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:09:31.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:09:31.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:09:31.89#ibcon#*before write, iclass 28, count 0 2006.201.11:09:31.89#ibcon#enter sib2, iclass 28, count 0 2006.201.11:09:31.89#ibcon#flushed, iclass 28, count 0 2006.201.11:09:31.89#ibcon#about to write, iclass 28, count 0 2006.201.11:09:31.89#ibcon#wrote, iclass 28, count 0 2006.201.11:09:31.89#ibcon#about to read 3, iclass 28, count 0 2006.201.11:09:31.94#ibcon#read 3, iclass 28, count 0 2006.201.11:09:31.94#ibcon#about to read 4, iclass 28, count 0 2006.201.11:09:31.94#ibcon#read 4, iclass 28, count 0 2006.201.11:09:31.94#ibcon#about to read 5, iclass 28, count 0 2006.201.11:09:31.94#ibcon#read 5, iclass 28, count 0 2006.201.11:09:31.94#ibcon#about to read 6, iclass 28, count 0 2006.201.11:09:31.94#ibcon#read 6, iclass 28, count 0 2006.201.11:09:31.94#ibcon#end of sib2, iclass 28, count 0 2006.201.11:09:31.94#ibcon#*after write, iclass 28, count 0 2006.201.11:09:31.94#ibcon#*before return 0, iclass 28, count 0 2006.201.11:09:31.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:31.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:31.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:09:31.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:09:31.94$vck44/va=4,7 2006.201.11:09:31.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.11:09:31.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.11:09:31.94#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:31.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:31.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:31.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:31.99#ibcon#enter wrdev, iclass 30, count 2 2006.201.11:09:31.99#ibcon#first serial, iclass 30, count 2 2006.201.11:09:31.99#ibcon#enter sib2, iclass 30, count 2 2006.201.11:09:31.99#ibcon#flushed, iclass 30, count 2 2006.201.11:09:31.99#ibcon#about to write, iclass 30, count 2 2006.201.11:09:31.99#ibcon#wrote, iclass 30, count 2 2006.201.11:09:31.99#ibcon#about to read 3, iclass 30, count 2 2006.201.11:09:32.01#ibcon#read 3, iclass 30, count 2 2006.201.11:09:32.01#ibcon#about to read 4, iclass 30, count 2 2006.201.11:09:32.01#ibcon#read 4, iclass 30, count 2 2006.201.11:09:32.01#ibcon#about to read 5, iclass 30, count 2 2006.201.11:09:32.01#ibcon#read 5, iclass 30, count 2 2006.201.11:09:32.01#ibcon#about to read 6, iclass 30, count 2 2006.201.11:09:32.01#ibcon#read 6, iclass 30, count 2 2006.201.11:09:32.01#ibcon#end of sib2, iclass 30, count 2 2006.201.11:09:32.01#ibcon#*mode == 0, iclass 30, count 2 2006.201.11:09:32.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.11:09:32.01#ibcon#[25=AT04-07\r\n] 2006.201.11:09:32.01#ibcon#*before write, iclass 30, count 2 2006.201.11:09:32.01#ibcon#enter sib2, iclass 30, count 2 2006.201.11:09:32.01#ibcon#flushed, iclass 30, count 2 2006.201.11:09:32.01#ibcon#about to write, iclass 30, count 2 2006.201.11:09:32.01#ibcon#wrote, iclass 30, count 2 2006.201.11:09:32.01#ibcon#about to read 3, iclass 30, count 2 2006.201.11:09:32.04#ibcon#read 3, iclass 30, count 2 2006.201.11:09:32.04#ibcon#about to read 4, iclass 30, count 2 2006.201.11:09:32.04#ibcon#read 4, iclass 30, count 2 2006.201.11:09:32.04#ibcon#about to read 5, iclass 30, count 2 2006.201.11:09:32.04#ibcon#read 5, iclass 30, count 2 2006.201.11:09:32.04#ibcon#about to read 6, iclass 30, count 2 2006.201.11:09:32.04#ibcon#read 6, iclass 30, count 2 2006.201.11:09:32.04#ibcon#end of sib2, iclass 30, count 2 2006.201.11:09:32.04#ibcon#*after write, iclass 30, count 2 2006.201.11:09:32.04#ibcon#*before return 0, iclass 30, count 2 2006.201.11:09:32.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:32.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:32.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.11:09:32.04#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:32.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:32.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:32.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:32.16#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:09:32.16#ibcon#first serial, iclass 30, count 0 2006.201.11:09:32.16#ibcon#enter sib2, iclass 30, count 0 2006.201.11:09:32.16#ibcon#flushed, iclass 30, count 0 2006.201.11:09:32.16#ibcon#about to write, iclass 30, count 0 2006.201.11:09:32.16#ibcon#wrote, iclass 30, count 0 2006.201.11:09:32.16#ibcon#about to read 3, iclass 30, count 0 2006.201.11:09:32.18#ibcon#read 3, iclass 30, count 0 2006.201.11:09:32.18#ibcon#about to read 4, iclass 30, count 0 2006.201.11:09:32.18#ibcon#read 4, iclass 30, count 0 2006.201.11:09:32.18#ibcon#about to read 5, iclass 30, count 0 2006.201.11:09:32.18#ibcon#read 5, iclass 30, count 0 2006.201.11:09:32.18#ibcon#about to read 6, iclass 30, count 0 2006.201.11:09:32.18#ibcon#read 6, iclass 30, count 0 2006.201.11:09:32.18#ibcon#end of sib2, iclass 30, count 0 2006.201.11:09:32.18#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:09:32.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:09:32.18#ibcon#[25=USB\r\n] 2006.201.11:09:32.18#ibcon#*before write, iclass 30, count 0 2006.201.11:09:32.18#ibcon#enter sib2, iclass 30, count 0 2006.201.11:09:32.18#ibcon#flushed, iclass 30, count 0 2006.201.11:09:32.18#ibcon#about to write, iclass 30, count 0 2006.201.11:09:32.18#ibcon#wrote, iclass 30, count 0 2006.201.11:09:32.18#ibcon#about to read 3, iclass 30, count 0 2006.201.11:09:32.21#ibcon#read 3, iclass 30, count 0 2006.201.11:09:32.21#ibcon#about to read 4, iclass 30, count 0 2006.201.11:09:32.21#ibcon#read 4, iclass 30, count 0 2006.201.11:09:32.21#ibcon#about to read 5, iclass 30, count 0 2006.201.11:09:32.21#ibcon#read 5, iclass 30, count 0 2006.201.11:09:32.21#ibcon#about to read 6, iclass 30, count 0 2006.201.11:09:32.21#ibcon#read 6, iclass 30, count 0 2006.201.11:09:32.21#ibcon#end of sib2, iclass 30, count 0 2006.201.11:09:32.21#ibcon#*after write, iclass 30, count 0 2006.201.11:09:32.21#ibcon#*before return 0, iclass 30, count 0 2006.201.11:09:32.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:32.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:32.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:09:32.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:09:32.21$vck44/valo=5,734.99 2006.201.11:09:32.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.11:09:32.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.11:09:32.21#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:32.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:32.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:32.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:32.21#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:09:32.21#ibcon#first serial, iclass 32, count 0 2006.201.11:09:32.21#ibcon#enter sib2, iclass 32, count 0 2006.201.11:09:32.21#ibcon#flushed, iclass 32, count 0 2006.201.11:09:32.21#ibcon#about to write, iclass 32, count 0 2006.201.11:09:32.21#ibcon#wrote, iclass 32, count 0 2006.201.11:09:32.21#ibcon#about to read 3, iclass 32, count 0 2006.201.11:09:32.23#ibcon#read 3, iclass 32, count 0 2006.201.11:09:32.23#ibcon#about to read 4, iclass 32, count 0 2006.201.11:09:32.23#ibcon#read 4, iclass 32, count 0 2006.201.11:09:32.23#ibcon#about to read 5, iclass 32, count 0 2006.201.11:09:32.23#ibcon#read 5, iclass 32, count 0 2006.201.11:09:32.23#ibcon#about to read 6, iclass 32, count 0 2006.201.11:09:32.23#ibcon#read 6, iclass 32, count 0 2006.201.11:09:32.23#ibcon#end of sib2, iclass 32, count 0 2006.201.11:09:32.23#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:09:32.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:09:32.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:09:32.23#ibcon#*before write, iclass 32, count 0 2006.201.11:09:32.23#ibcon#enter sib2, iclass 32, count 0 2006.201.11:09:32.23#ibcon#flushed, iclass 32, count 0 2006.201.11:09:32.23#ibcon#about to write, iclass 32, count 0 2006.201.11:09:32.23#ibcon#wrote, iclass 32, count 0 2006.201.11:09:32.23#ibcon#about to read 3, iclass 32, count 0 2006.201.11:09:32.27#ibcon#read 3, iclass 32, count 0 2006.201.11:09:32.27#ibcon#about to read 4, iclass 32, count 0 2006.201.11:09:32.27#ibcon#read 4, iclass 32, count 0 2006.201.11:09:32.27#ibcon#about to read 5, iclass 32, count 0 2006.201.11:09:32.27#ibcon#read 5, iclass 32, count 0 2006.201.11:09:32.27#ibcon#about to read 6, iclass 32, count 0 2006.201.11:09:32.27#ibcon#read 6, iclass 32, count 0 2006.201.11:09:32.27#ibcon#end of sib2, iclass 32, count 0 2006.201.11:09:32.27#ibcon#*after write, iclass 32, count 0 2006.201.11:09:32.27#ibcon#*before return 0, iclass 32, count 0 2006.201.11:09:32.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:32.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:32.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:09:32.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:09:32.27$vck44/va=5,4 2006.201.11:09:32.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.11:09:32.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.11:09:32.27#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:32.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:32.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:32.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:32.33#ibcon#enter wrdev, iclass 34, count 2 2006.201.11:09:32.33#ibcon#first serial, iclass 34, count 2 2006.201.11:09:32.33#ibcon#enter sib2, iclass 34, count 2 2006.201.11:09:32.33#ibcon#flushed, iclass 34, count 2 2006.201.11:09:32.33#ibcon#about to write, iclass 34, count 2 2006.201.11:09:32.33#ibcon#wrote, iclass 34, count 2 2006.201.11:09:32.33#ibcon#about to read 3, iclass 34, count 2 2006.201.11:09:32.35#ibcon#read 3, iclass 34, count 2 2006.201.11:09:32.35#ibcon#about to read 4, iclass 34, count 2 2006.201.11:09:32.35#ibcon#read 4, iclass 34, count 2 2006.201.11:09:32.35#ibcon#about to read 5, iclass 34, count 2 2006.201.11:09:32.35#ibcon#read 5, iclass 34, count 2 2006.201.11:09:32.35#ibcon#about to read 6, iclass 34, count 2 2006.201.11:09:32.35#ibcon#read 6, iclass 34, count 2 2006.201.11:09:32.35#ibcon#end of sib2, iclass 34, count 2 2006.201.11:09:32.35#ibcon#*mode == 0, iclass 34, count 2 2006.201.11:09:32.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.11:09:32.35#ibcon#[25=AT05-04\r\n] 2006.201.11:09:32.35#ibcon#*before write, iclass 34, count 2 2006.201.11:09:32.35#ibcon#enter sib2, iclass 34, count 2 2006.201.11:09:32.35#ibcon#flushed, iclass 34, count 2 2006.201.11:09:32.35#ibcon#about to write, iclass 34, count 2 2006.201.11:09:32.35#ibcon#wrote, iclass 34, count 2 2006.201.11:09:32.35#ibcon#about to read 3, iclass 34, count 2 2006.201.11:09:32.38#ibcon#read 3, iclass 34, count 2 2006.201.11:09:32.38#ibcon#about to read 4, iclass 34, count 2 2006.201.11:09:32.38#ibcon#read 4, iclass 34, count 2 2006.201.11:09:32.38#ibcon#about to read 5, iclass 34, count 2 2006.201.11:09:32.38#ibcon#read 5, iclass 34, count 2 2006.201.11:09:32.38#ibcon#about to read 6, iclass 34, count 2 2006.201.11:09:32.38#ibcon#read 6, iclass 34, count 2 2006.201.11:09:32.38#ibcon#end of sib2, iclass 34, count 2 2006.201.11:09:32.38#ibcon#*after write, iclass 34, count 2 2006.201.11:09:32.38#ibcon#*before return 0, iclass 34, count 2 2006.201.11:09:32.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:32.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:32.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.11:09:32.38#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:32.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:32.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:32.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:32.50#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:09:32.50#ibcon#first serial, iclass 34, count 0 2006.201.11:09:32.50#ibcon#enter sib2, iclass 34, count 0 2006.201.11:09:32.50#ibcon#flushed, iclass 34, count 0 2006.201.11:09:32.50#ibcon#about to write, iclass 34, count 0 2006.201.11:09:32.50#ibcon#wrote, iclass 34, count 0 2006.201.11:09:32.50#ibcon#about to read 3, iclass 34, count 0 2006.201.11:09:32.52#ibcon#read 3, iclass 34, count 0 2006.201.11:09:32.52#ibcon#about to read 4, iclass 34, count 0 2006.201.11:09:32.52#ibcon#read 4, iclass 34, count 0 2006.201.11:09:32.52#ibcon#about to read 5, iclass 34, count 0 2006.201.11:09:32.52#ibcon#read 5, iclass 34, count 0 2006.201.11:09:32.52#ibcon#about to read 6, iclass 34, count 0 2006.201.11:09:32.52#ibcon#read 6, iclass 34, count 0 2006.201.11:09:32.52#ibcon#end of sib2, iclass 34, count 0 2006.201.11:09:32.52#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:09:32.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:09:32.52#ibcon#[25=USB\r\n] 2006.201.11:09:32.52#ibcon#*before write, iclass 34, count 0 2006.201.11:09:32.52#ibcon#enter sib2, iclass 34, count 0 2006.201.11:09:32.52#ibcon#flushed, iclass 34, count 0 2006.201.11:09:32.52#ibcon#about to write, iclass 34, count 0 2006.201.11:09:32.52#ibcon#wrote, iclass 34, count 0 2006.201.11:09:32.52#ibcon#about to read 3, iclass 34, count 0 2006.201.11:09:32.55#ibcon#read 3, iclass 34, count 0 2006.201.11:09:32.55#ibcon#about to read 4, iclass 34, count 0 2006.201.11:09:32.55#ibcon#read 4, iclass 34, count 0 2006.201.11:09:32.55#ibcon#about to read 5, iclass 34, count 0 2006.201.11:09:32.55#ibcon#read 5, iclass 34, count 0 2006.201.11:09:32.55#ibcon#about to read 6, iclass 34, count 0 2006.201.11:09:32.55#ibcon#read 6, iclass 34, count 0 2006.201.11:09:32.55#ibcon#end of sib2, iclass 34, count 0 2006.201.11:09:32.55#ibcon#*after write, iclass 34, count 0 2006.201.11:09:32.55#ibcon#*before return 0, iclass 34, count 0 2006.201.11:09:32.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:32.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:32.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:09:32.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:09:32.55$vck44/valo=6,814.99 2006.201.11:09:32.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.11:09:32.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.11:09:32.55#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:32.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:32.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:32.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:32.55#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:09:32.55#ibcon#first serial, iclass 36, count 0 2006.201.11:09:32.55#ibcon#enter sib2, iclass 36, count 0 2006.201.11:09:32.55#ibcon#flushed, iclass 36, count 0 2006.201.11:09:32.55#ibcon#about to write, iclass 36, count 0 2006.201.11:09:32.55#ibcon#wrote, iclass 36, count 0 2006.201.11:09:32.55#ibcon#about to read 3, iclass 36, count 0 2006.201.11:09:32.57#ibcon#read 3, iclass 36, count 0 2006.201.11:09:32.57#ibcon#about to read 4, iclass 36, count 0 2006.201.11:09:32.57#ibcon#read 4, iclass 36, count 0 2006.201.11:09:32.57#ibcon#about to read 5, iclass 36, count 0 2006.201.11:09:32.57#ibcon#read 5, iclass 36, count 0 2006.201.11:09:32.57#ibcon#about to read 6, iclass 36, count 0 2006.201.11:09:32.57#ibcon#read 6, iclass 36, count 0 2006.201.11:09:32.57#ibcon#end of sib2, iclass 36, count 0 2006.201.11:09:32.57#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:09:32.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:09:32.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:09:32.57#ibcon#*before write, iclass 36, count 0 2006.201.11:09:32.57#ibcon#enter sib2, iclass 36, count 0 2006.201.11:09:32.57#ibcon#flushed, iclass 36, count 0 2006.201.11:09:32.57#ibcon#about to write, iclass 36, count 0 2006.201.11:09:32.57#ibcon#wrote, iclass 36, count 0 2006.201.11:09:32.57#ibcon#about to read 3, iclass 36, count 0 2006.201.11:09:32.62#ibcon#read 3, iclass 36, count 0 2006.201.11:09:32.62#ibcon#about to read 4, iclass 36, count 0 2006.201.11:09:32.62#ibcon#read 4, iclass 36, count 0 2006.201.11:09:32.62#ibcon#about to read 5, iclass 36, count 0 2006.201.11:09:32.62#ibcon#read 5, iclass 36, count 0 2006.201.11:09:32.62#ibcon#about to read 6, iclass 36, count 0 2006.201.11:09:32.62#ibcon#read 6, iclass 36, count 0 2006.201.11:09:32.62#ibcon#end of sib2, iclass 36, count 0 2006.201.11:09:32.62#ibcon#*after write, iclass 36, count 0 2006.201.11:09:32.62#ibcon#*before return 0, iclass 36, count 0 2006.201.11:09:32.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:32.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:32.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:09:32.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:09:32.62$vck44/va=6,5 2006.201.11:09:32.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.11:09:32.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.11:09:32.62#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:32.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:32.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:32.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:32.67#ibcon#enter wrdev, iclass 38, count 2 2006.201.11:09:32.67#ibcon#first serial, iclass 38, count 2 2006.201.11:09:32.67#ibcon#enter sib2, iclass 38, count 2 2006.201.11:09:32.67#ibcon#flushed, iclass 38, count 2 2006.201.11:09:32.67#ibcon#about to write, iclass 38, count 2 2006.201.11:09:32.67#ibcon#wrote, iclass 38, count 2 2006.201.11:09:32.67#ibcon#about to read 3, iclass 38, count 2 2006.201.11:09:32.69#ibcon#read 3, iclass 38, count 2 2006.201.11:09:32.69#ibcon#about to read 4, iclass 38, count 2 2006.201.11:09:32.69#ibcon#read 4, iclass 38, count 2 2006.201.11:09:32.69#ibcon#about to read 5, iclass 38, count 2 2006.201.11:09:32.69#ibcon#read 5, iclass 38, count 2 2006.201.11:09:32.69#ibcon#about to read 6, iclass 38, count 2 2006.201.11:09:32.69#ibcon#read 6, iclass 38, count 2 2006.201.11:09:32.69#ibcon#end of sib2, iclass 38, count 2 2006.201.11:09:32.69#ibcon#*mode == 0, iclass 38, count 2 2006.201.11:09:32.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.11:09:32.69#ibcon#[25=AT06-05\r\n] 2006.201.11:09:32.69#ibcon#*before write, iclass 38, count 2 2006.201.11:09:32.69#ibcon#enter sib2, iclass 38, count 2 2006.201.11:09:32.69#ibcon#flushed, iclass 38, count 2 2006.201.11:09:32.69#ibcon#about to write, iclass 38, count 2 2006.201.11:09:32.69#ibcon#wrote, iclass 38, count 2 2006.201.11:09:32.69#ibcon#about to read 3, iclass 38, count 2 2006.201.11:09:32.72#ibcon#read 3, iclass 38, count 2 2006.201.11:09:32.72#ibcon#about to read 4, iclass 38, count 2 2006.201.11:09:32.72#ibcon#read 4, iclass 38, count 2 2006.201.11:09:32.72#ibcon#about to read 5, iclass 38, count 2 2006.201.11:09:32.72#ibcon#read 5, iclass 38, count 2 2006.201.11:09:32.72#ibcon#about to read 6, iclass 38, count 2 2006.201.11:09:32.72#ibcon#read 6, iclass 38, count 2 2006.201.11:09:32.72#ibcon#end of sib2, iclass 38, count 2 2006.201.11:09:32.72#ibcon#*after write, iclass 38, count 2 2006.201.11:09:32.72#ibcon#*before return 0, iclass 38, count 2 2006.201.11:09:32.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:32.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:32.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.11:09:32.72#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:32.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:32.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:32.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:32.84#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:09:32.84#ibcon#first serial, iclass 38, count 0 2006.201.11:09:32.84#ibcon#enter sib2, iclass 38, count 0 2006.201.11:09:32.84#ibcon#flushed, iclass 38, count 0 2006.201.11:09:32.84#ibcon#about to write, iclass 38, count 0 2006.201.11:09:32.84#ibcon#wrote, iclass 38, count 0 2006.201.11:09:32.84#ibcon#about to read 3, iclass 38, count 0 2006.201.11:09:32.86#ibcon#read 3, iclass 38, count 0 2006.201.11:09:32.86#ibcon#about to read 4, iclass 38, count 0 2006.201.11:09:32.86#ibcon#read 4, iclass 38, count 0 2006.201.11:09:32.86#ibcon#about to read 5, iclass 38, count 0 2006.201.11:09:32.86#ibcon#read 5, iclass 38, count 0 2006.201.11:09:32.86#ibcon#about to read 6, iclass 38, count 0 2006.201.11:09:32.86#ibcon#read 6, iclass 38, count 0 2006.201.11:09:32.86#ibcon#end of sib2, iclass 38, count 0 2006.201.11:09:32.86#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:09:32.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:09:32.86#ibcon#[25=USB\r\n] 2006.201.11:09:32.86#ibcon#*before write, iclass 38, count 0 2006.201.11:09:32.86#ibcon#enter sib2, iclass 38, count 0 2006.201.11:09:32.86#ibcon#flushed, iclass 38, count 0 2006.201.11:09:32.86#ibcon#about to write, iclass 38, count 0 2006.201.11:09:32.86#ibcon#wrote, iclass 38, count 0 2006.201.11:09:32.86#ibcon#about to read 3, iclass 38, count 0 2006.201.11:09:32.89#ibcon#read 3, iclass 38, count 0 2006.201.11:09:32.89#ibcon#about to read 4, iclass 38, count 0 2006.201.11:09:32.89#ibcon#read 4, iclass 38, count 0 2006.201.11:09:32.89#ibcon#about to read 5, iclass 38, count 0 2006.201.11:09:32.89#ibcon#read 5, iclass 38, count 0 2006.201.11:09:32.89#ibcon#about to read 6, iclass 38, count 0 2006.201.11:09:32.89#ibcon#read 6, iclass 38, count 0 2006.201.11:09:32.89#ibcon#end of sib2, iclass 38, count 0 2006.201.11:09:32.89#ibcon#*after write, iclass 38, count 0 2006.201.11:09:32.89#ibcon#*before return 0, iclass 38, count 0 2006.201.11:09:32.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:32.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:32.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:09:32.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:09:32.89$vck44/valo=7,864.99 2006.201.11:09:32.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.11:09:32.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.11:09:32.89#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:32.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:32.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:32.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:32.89#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:09:32.89#ibcon#first serial, iclass 40, count 0 2006.201.11:09:32.89#ibcon#enter sib2, iclass 40, count 0 2006.201.11:09:32.89#ibcon#flushed, iclass 40, count 0 2006.201.11:09:32.89#ibcon#about to write, iclass 40, count 0 2006.201.11:09:32.89#ibcon#wrote, iclass 40, count 0 2006.201.11:09:32.89#ibcon#about to read 3, iclass 40, count 0 2006.201.11:09:32.91#ibcon#read 3, iclass 40, count 0 2006.201.11:09:32.91#ibcon#about to read 4, iclass 40, count 0 2006.201.11:09:32.91#ibcon#read 4, iclass 40, count 0 2006.201.11:09:32.91#ibcon#about to read 5, iclass 40, count 0 2006.201.11:09:32.91#ibcon#read 5, iclass 40, count 0 2006.201.11:09:32.91#ibcon#about to read 6, iclass 40, count 0 2006.201.11:09:32.91#ibcon#read 6, iclass 40, count 0 2006.201.11:09:32.91#ibcon#end of sib2, iclass 40, count 0 2006.201.11:09:32.91#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:09:32.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:09:32.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:09:32.91#ibcon#*before write, iclass 40, count 0 2006.201.11:09:32.91#ibcon#enter sib2, iclass 40, count 0 2006.201.11:09:32.91#ibcon#flushed, iclass 40, count 0 2006.201.11:09:32.91#ibcon#about to write, iclass 40, count 0 2006.201.11:09:32.91#ibcon#wrote, iclass 40, count 0 2006.201.11:09:32.91#ibcon#about to read 3, iclass 40, count 0 2006.201.11:09:32.95#ibcon#read 3, iclass 40, count 0 2006.201.11:09:32.95#ibcon#about to read 4, iclass 40, count 0 2006.201.11:09:32.95#ibcon#read 4, iclass 40, count 0 2006.201.11:09:32.95#ibcon#about to read 5, iclass 40, count 0 2006.201.11:09:32.95#ibcon#read 5, iclass 40, count 0 2006.201.11:09:32.95#ibcon#about to read 6, iclass 40, count 0 2006.201.11:09:32.95#ibcon#read 6, iclass 40, count 0 2006.201.11:09:32.95#ibcon#end of sib2, iclass 40, count 0 2006.201.11:09:32.95#ibcon#*after write, iclass 40, count 0 2006.201.11:09:32.95#ibcon#*before return 0, iclass 40, count 0 2006.201.11:09:32.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:32.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:32.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:09:32.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:09:32.95$vck44/va=7,5 2006.201.11:09:32.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.11:09:32.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.11:09:32.95#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:32.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:33.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:33.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:33.01#ibcon#enter wrdev, iclass 4, count 2 2006.201.11:09:33.01#ibcon#first serial, iclass 4, count 2 2006.201.11:09:33.01#ibcon#enter sib2, iclass 4, count 2 2006.201.11:09:33.01#ibcon#flushed, iclass 4, count 2 2006.201.11:09:33.01#ibcon#about to write, iclass 4, count 2 2006.201.11:09:33.01#ibcon#wrote, iclass 4, count 2 2006.201.11:09:33.01#ibcon#about to read 3, iclass 4, count 2 2006.201.11:09:33.03#ibcon#read 3, iclass 4, count 2 2006.201.11:09:33.03#ibcon#about to read 4, iclass 4, count 2 2006.201.11:09:33.03#ibcon#read 4, iclass 4, count 2 2006.201.11:09:33.03#ibcon#about to read 5, iclass 4, count 2 2006.201.11:09:33.03#ibcon#read 5, iclass 4, count 2 2006.201.11:09:33.03#ibcon#about to read 6, iclass 4, count 2 2006.201.11:09:33.03#ibcon#read 6, iclass 4, count 2 2006.201.11:09:33.03#ibcon#end of sib2, iclass 4, count 2 2006.201.11:09:33.03#ibcon#*mode == 0, iclass 4, count 2 2006.201.11:09:33.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.11:09:33.03#ibcon#[25=AT07-05\r\n] 2006.201.11:09:33.03#ibcon#*before write, iclass 4, count 2 2006.201.11:09:33.03#ibcon#enter sib2, iclass 4, count 2 2006.201.11:09:33.03#ibcon#flushed, iclass 4, count 2 2006.201.11:09:33.03#ibcon#about to write, iclass 4, count 2 2006.201.11:09:33.03#ibcon#wrote, iclass 4, count 2 2006.201.11:09:33.03#ibcon#about to read 3, iclass 4, count 2 2006.201.11:09:33.06#ibcon#read 3, iclass 4, count 2 2006.201.11:09:33.06#ibcon#about to read 4, iclass 4, count 2 2006.201.11:09:33.06#ibcon#read 4, iclass 4, count 2 2006.201.11:09:33.06#ibcon#about to read 5, iclass 4, count 2 2006.201.11:09:33.06#ibcon#read 5, iclass 4, count 2 2006.201.11:09:33.06#ibcon#about to read 6, iclass 4, count 2 2006.201.11:09:33.06#ibcon#read 6, iclass 4, count 2 2006.201.11:09:33.06#ibcon#end of sib2, iclass 4, count 2 2006.201.11:09:33.06#ibcon#*after write, iclass 4, count 2 2006.201.11:09:33.06#ibcon#*before return 0, iclass 4, count 2 2006.201.11:09:33.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:33.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:33.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.11:09:33.06#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:33.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:33.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:33.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:33.18#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:09:33.18#ibcon#first serial, iclass 4, count 0 2006.201.11:09:33.18#ibcon#enter sib2, iclass 4, count 0 2006.201.11:09:33.18#ibcon#flushed, iclass 4, count 0 2006.201.11:09:33.18#ibcon#about to write, iclass 4, count 0 2006.201.11:09:33.18#ibcon#wrote, iclass 4, count 0 2006.201.11:09:33.18#ibcon#about to read 3, iclass 4, count 0 2006.201.11:09:33.21#ibcon#read 3, iclass 4, count 0 2006.201.11:09:33.21#ibcon#about to read 4, iclass 4, count 0 2006.201.11:09:33.21#ibcon#read 4, iclass 4, count 0 2006.201.11:09:33.21#ibcon#about to read 5, iclass 4, count 0 2006.201.11:09:33.21#ibcon#read 5, iclass 4, count 0 2006.201.11:09:33.21#ibcon#about to read 6, iclass 4, count 0 2006.201.11:09:33.21#ibcon#read 6, iclass 4, count 0 2006.201.11:09:33.21#ibcon#end of sib2, iclass 4, count 0 2006.201.11:09:33.21#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:09:33.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:09:33.21#ibcon#[25=USB\r\n] 2006.201.11:09:33.21#ibcon#*before write, iclass 4, count 0 2006.201.11:09:33.21#ibcon#enter sib2, iclass 4, count 0 2006.201.11:09:33.21#ibcon#flushed, iclass 4, count 0 2006.201.11:09:33.21#ibcon#about to write, iclass 4, count 0 2006.201.11:09:33.21#ibcon#wrote, iclass 4, count 0 2006.201.11:09:33.21#ibcon#about to read 3, iclass 4, count 0 2006.201.11:09:33.24#ibcon#read 3, iclass 4, count 0 2006.201.11:09:33.24#ibcon#about to read 4, iclass 4, count 0 2006.201.11:09:33.24#ibcon#read 4, iclass 4, count 0 2006.201.11:09:33.24#ibcon#about to read 5, iclass 4, count 0 2006.201.11:09:33.24#ibcon#read 5, iclass 4, count 0 2006.201.11:09:33.24#ibcon#about to read 6, iclass 4, count 0 2006.201.11:09:33.24#ibcon#read 6, iclass 4, count 0 2006.201.11:09:33.24#ibcon#end of sib2, iclass 4, count 0 2006.201.11:09:33.24#ibcon#*after write, iclass 4, count 0 2006.201.11:09:33.24#ibcon#*before return 0, iclass 4, count 0 2006.201.11:09:33.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:33.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:33.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:09:33.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:09:33.24$vck44/valo=8,884.99 2006.201.11:09:33.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.11:09:33.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.11:09:33.24#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:33.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:33.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:33.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:33.24#ibcon#enter wrdev, iclass 6, count 0 2006.201.11:09:33.24#ibcon#first serial, iclass 6, count 0 2006.201.11:09:33.24#ibcon#enter sib2, iclass 6, count 0 2006.201.11:09:33.24#ibcon#flushed, iclass 6, count 0 2006.201.11:09:33.24#ibcon#about to write, iclass 6, count 0 2006.201.11:09:33.24#ibcon#wrote, iclass 6, count 0 2006.201.11:09:33.24#ibcon#about to read 3, iclass 6, count 0 2006.201.11:09:33.26#ibcon#read 3, iclass 6, count 0 2006.201.11:09:33.26#ibcon#about to read 4, iclass 6, count 0 2006.201.11:09:33.26#ibcon#read 4, iclass 6, count 0 2006.201.11:09:33.26#ibcon#about to read 5, iclass 6, count 0 2006.201.11:09:33.26#ibcon#read 5, iclass 6, count 0 2006.201.11:09:33.26#ibcon#about to read 6, iclass 6, count 0 2006.201.11:09:33.26#ibcon#read 6, iclass 6, count 0 2006.201.11:09:33.26#ibcon#end of sib2, iclass 6, count 0 2006.201.11:09:33.26#ibcon#*mode == 0, iclass 6, count 0 2006.201.11:09:33.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.11:09:33.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:09:33.26#ibcon#*before write, iclass 6, count 0 2006.201.11:09:33.26#ibcon#enter sib2, iclass 6, count 0 2006.201.11:09:33.26#ibcon#flushed, iclass 6, count 0 2006.201.11:09:33.26#ibcon#about to write, iclass 6, count 0 2006.201.11:09:33.26#ibcon#wrote, iclass 6, count 0 2006.201.11:09:33.26#ibcon#about to read 3, iclass 6, count 0 2006.201.11:09:33.30#ibcon#read 3, iclass 6, count 0 2006.201.11:09:33.30#ibcon#about to read 4, iclass 6, count 0 2006.201.11:09:33.30#ibcon#read 4, iclass 6, count 0 2006.201.11:09:33.30#ibcon#about to read 5, iclass 6, count 0 2006.201.11:09:33.30#ibcon#read 5, iclass 6, count 0 2006.201.11:09:33.30#ibcon#about to read 6, iclass 6, count 0 2006.201.11:09:33.30#ibcon#read 6, iclass 6, count 0 2006.201.11:09:33.30#ibcon#end of sib2, iclass 6, count 0 2006.201.11:09:33.30#ibcon#*after write, iclass 6, count 0 2006.201.11:09:33.30#ibcon#*before return 0, iclass 6, count 0 2006.201.11:09:33.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:33.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:33.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.11:09:33.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.11:09:33.30$vck44/va=8,4 2006.201.11:09:33.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.11:09:33.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.11:09:33.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:33.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:09:33.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:09:33.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:09:33.36#ibcon#enter wrdev, iclass 10, count 2 2006.201.11:09:33.36#ibcon#first serial, iclass 10, count 2 2006.201.11:09:33.36#ibcon#enter sib2, iclass 10, count 2 2006.201.11:09:33.36#ibcon#flushed, iclass 10, count 2 2006.201.11:09:33.36#ibcon#about to write, iclass 10, count 2 2006.201.11:09:33.36#ibcon#wrote, iclass 10, count 2 2006.201.11:09:33.36#ibcon#about to read 3, iclass 10, count 2 2006.201.11:09:33.38#ibcon#read 3, iclass 10, count 2 2006.201.11:09:33.38#ibcon#about to read 4, iclass 10, count 2 2006.201.11:09:33.38#ibcon#read 4, iclass 10, count 2 2006.201.11:09:33.38#ibcon#about to read 5, iclass 10, count 2 2006.201.11:09:33.38#ibcon#read 5, iclass 10, count 2 2006.201.11:09:33.38#ibcon#about to read 6, iclass 10, count 2 2006.201.11:09:33.38#ibcon#read 6, iclass 10, count 2 2006.201.11:09:33.38#ibcon#end of sib2, iclass 10, count 2 2006.201.11:09:33.38#ibcon#*mode == 0, iclass 10, count 2 2006.201.11:09:33.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.11:09:33.38#ibcon#[25=AT08-04\r\n] 2006.201.11:09:33.38#ibcon#*before write, iclass 10, count 2 2006.201.11:09:33.38#ibcon#enter sib2, iclass 10, count 2 2006.201.11:09:33.38#ibcon#flushed, iclass 10, count 2 2006.201.11:09:33.38#ibcon#about to write, iclass 10, count 2 2006.201.11:09:33.38#ibcon#wrote, iclass 10, count 2 2006.201.11:09:33.38#ibcon#about to read 3, iclass 10, count 2 2006.201.11:09:33.41#ibcon#read 3, iclass 10, count 2 2006.201.11:09:33.41#ibcon#about to read 4, iclass 10, count 2 2006.201.11:09:33.41#ibcon#read 4, iclass 10, count 2 2006.201.11:09:33.41#ibcon#about to read 5, iclass 10, count 2 2006.201.11:09:33.41#ibcon#read 5, iclass 10, count 2 2006.201.11:09:33.41#ibcon#about to read 6, iclass 10, count 2 2006.201.11:09:33.41#ibcon#read 6, iclass 10, count 2 2006.201.11:09:33.41#ibcon#end of sib2, iclass 10, count 2 2006.201.11:09:33.41#ibcon#*after write, iclass 10, count 2 2006.201.11:09:33.41#ibcon#*before return 0, iclass 10, count 2 2006.201.11:09:33.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:09:33.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:09:33.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.11:09:33.41#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:33.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:09:33.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:09:33.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:09:33.53#ibcon#enter wrdev, iclass 10, count 0 2006.201.11:09:33.53#ibcon#first serial, iclass 10, count 0 2006.201.11:09:33.53#ibcon#enter sib2, iclass 10, count 0 2006.201.11:09:33.53#ibcon#flushed, iclass 10, count 0 2006.201.11:09:33.53#ibcon#about to write, iclass 10, count 0 2006.201.11:09:33.53#ibcon#wrote, iclass 10, count 0 2006.201.11:09:33.53#ibcon#about to read 3, iclass 10, count 0 2006.201.11:09:33.55#ibcon#read 3, iclass 10, count 0 2006.201.11:09:33.55#ibcon#about to read 4, iclass 10, count 0 2006.201.11:09:33.55#ibcon#read 4, iclass 10, count 0 2006.201.11:09:33.55#ibcon#about to read 5, iclass 10, count 0 2006.201.11:09:33.55#ibcon#read 5, iclass 10, count 0 2006.201.11:09:33.55#ibcon#about to read 6, iclass 10, count 0 2006.201.11:09:33.55#ibcon#read 6, iclass 10, count 0 2006.201.11:09:33.55#ibcon#end of sib2, iclass 10, count 0 2006.201.11:09:33.55#ibcon#*mode == 0, iclass 10, count 0 2006.201.11:09:33.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.11:09:33.55#ibcon#[25=USB\r\n] 2006.201.11:09:33.55#ibcon#*before write, iclass 10, count 0 2006.201.11:09:33.55#ibcon#enter sib2, iclass 10, count 0 2006.201.11:09:33.55#ibcon#flushed, iclass 10, count 0 2006.201.11:09:33.55#ibcon#about to write, iclass 10, count 0 2006.201.11:09:33.55#ibcon#wrote, iclass 10, count 0 2006.201.11:09:33.55#ibcon#about to read 3, iclass 10, count 0 2006.201.11:09:33.58#ibcon#read 3, iclass 10, count 0 2006.201.11:09:33.58#ibcon#about to read 4, iclass 10, count 0 2006.201.11:09:33.58#ibcon#read 4, iclass 10, count 0 2006.201.11:09:33.58#ibcon#about to read 5, iclass 10, count 0 2006.201.11:09:33.58#ibcon#read 5, iclass 10, count 0 2006.201.11:09:33.58#ibcon#about to read 6, iclass 10, count 0 2006.201.11:09:33.58#ibcon#read 6, iclass 10, count 0 2006.201.11:09:33.58#ibcon#end of sib2, iclass 10, count 0 2006.201.11:09:33.58#ibcon#*after write, iclass 10, count 0 2006.201.11:09:33.58#ibcon#*before return 0, iclass 10, count 0 2006.201.11:09:33.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:09:33.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:09:33.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.11:09:33.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.11:09:33.58$vck44/vblo=1,629.99 2006.201.11:09:33.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.11:09:33.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.11:09:33.58#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:33.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:33.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:33.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:33.58#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:09:33.58#ibcon#first serial, iclass 12, count 0 2006.201.11:09:33.58#ibcon#enter sib2, iclass 12, count 0 2006.201.11:09:33.58#ibcon#flushed, iclass 12, count 0 2006.201.11:09:33.58#ibcon#about to write, iclass 12, count 0 2006.201.11:09:33.58#ibcon#wrote, iclass 12, count 0 2006.201.11:09:33.58#ibcon#about to read 3, iclass 12, count 0 2006.201.11:09:33.60#ibcon#read 3, iclass 12, count 0 2006.201.11:09:33.60#ibcon#about to read 4, iclass 12, count 0 2006.201.11:09:33.60#ibcon#read 4, iclass 12, count 0 2006.201.11:09:33.60#ibcon#about to read 5, iclass 12, count 0 2006.201.11:09:33.60#ibcon#read 5, iclass 12, count 0 2006.201.11:09:33.60#ibcon#about to read 6, iclass 12, count 0 2006.201.11:09:33.60#ibcon#read 6, iclass 12, count 0 2006.201.11:09:33.60#ibcon#end of sib2, iclass 12, count 0 2006.201.11:09:33.60#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:09:33.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:09:33.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:09:33.60#ibcon#*before write, iclass 12, count 0 2006.201.11:09:33.60#ibcon#enter sib2, iclass 12, count 0 2006.201.11:09:33.60#ibcon#flushed, iclass 12, count 0 2006.201.11:09:33.60#ibcon#about to write, iclass 12, count 0 2006.201.11:09:33.60#ibcon#wrote, iclass 12, count 0 2006.201.11:09:33.60#ibcon#about to read 3, iclass 12, count 0 2006.201.11:09:33.64#ibcon#read 3, iclass 12, count 0 2006.201.11:09:33.64#ibcon#about to read 4, iclass 12, count 0 2006.201.11:09:33.64#ibcon#read 4, iclass 12, count 0 2006.201.11:09:33.64#ibcon#about to read 5, iclass 12, count 0 2006.201.11:09:33.64#ibcon#read 5, iclass 12, count 0 2006.201.11:09:33.64#ibcon#about to read 6, iclass 12, count 0 2006.201.11:09:33.64#ibcon#read 6, iclass 12, count 0 2006.201.11:09:33.64#ibcon#end of sib2, iclass 12, count 0 2006.201.11:09:33.64#ibcon#*after write, iclass 12, count 0 2006.201.11:09:33.64#ibcon#*before return 0, iclass 12, count 0 2006.201.11:09:33.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:33.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:09:33.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:09:33.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:09:33.64$vck44/vb=1,4 2006.201.11:09:33.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.11:09:33.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.11:09:33.64#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:33.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:33.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:33.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:33.64#ibcon#enter wrdev, iclass 14, count 2 2006.201.11:09:33.64#ibcon#first serial, iclass 14, count 2 2006.201.11:09:33.64#ibcon#enter sib2, iclass 14, count 2 2006.201.11:09:33.64#ibcon#flushed, iclass 14, count 2 2006.201.11:09:33.64#ibcon#about to write, iclass 14, count 2 2006.201.11:09:33.64#ibcon#wrote, iclass 14, count 2 2006.201.11:09:33.64#ibcon#about to read 3, iclass 14, count 2 2006.201.11:09:33.66#ibcon#read 3, iclass 14, count 2 2006.201.11:09:33.66#ibcon#about to read 4, iclass 14, count 2 2006.201.11:09:33.66#ibcon#read 4, iclass 14, count 2 2006.201.11:09:33.66#ibcon#about to read 5, iclass 14, count 2 2006.201.11:09:33.66#ibcon#read 5, iclass 14, count 2 2006.201.11:09:33.66#ibcon#about to read 6, iclass 14, count 2 2006.201.11:09:33.66#ibcon#read 6, iclass 14, count 2 2006.201.11:09:33.66#ibcon#end of sib2, iclass 14, count 2 2006.201.11:09:33.66#ibcon#*mode == 0, iclass 14, count 2 2006.201.11:09:33.66#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.11:09:33.66#ibcon#[27=AT01-04\r\n] 2006.201.11:09:33.66#ibcon#*before write, iclass 14, count 2 2006.201.11:09:33.66#ibcon#enter sib2, iclass 14, count 2 2006.201.11:09:33.66#ibcon#flushed, iclass 14, count 2 2006.201.11:09:33.66#ibcon#about to write, iclass 14, count 2 2006.201.11:09:33.66#ibcon#wrote, iclass 14, count 2 2006.201.11:09:33.66#ibcon#about to read 3, iclass 14, count 2 2006.201.11:09:33.69#ibcon#read 3, iclass 14, count 2 2006.201.11:09:33.69#ibcon#about to read 4, iclass 14, count 2 2006.201.11:09:33.69#ibcon#read 4, iclass 14, count 2 2006.201.11:09:33.69#ibcon#about to read 5, iclass 14, count 2 2006.201.11:09:33.69#ibcon#read 5, iclass 14, count 2 2006.201.11:09:33.69#ibcon#about to read 6, iclass 14, count 2 2006.201.11:09:33.69#ibcon#read 6, iclass 14, count 2 2006.201.11:09:33.69#ibcon#end of sib2, iclass 14, count 2 2006.201.11:09:33.69#ibcon#*after write, iclass 14, count 2 2006.201.11:09:33.69#ibcon#*before return 0, iclass 14, count 2 2006.201.11:09:33.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:33.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:09:33.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.11:09:33.69#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:33.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:33.81#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:33.81#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:33.81#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:09:33.81#ibcon#first serial, iclass 14, count 0 2006.201.11:09:33.81#ibcon#enter sib2, iclass 14, count 0 2006.201.11:09:33.81#ibcon#flushed, iclass 14, count 0 2006.201.11:09:33.81#ibcon#about to write, iclass 14, count 0 2006.201.11:09:33.81#ibcon#wrote, iclass 14, count 0 2006.201.11:09:33.81#ibcon#about to read 3, iclass 14, count 0 2006.201.11:09:33.83#ibcon#read 3, iclass 14, count 0 2006.201.11:09:33.83#ibcon#about to read 4, iclass 14, count 0 2006.201.11:09:33.83#ibcon#read 4, iclass 14, count 0 2006.201.11:09:33.83#ibcon#about to read 5, iclass 14, count 0 2006.201.11:09:33.83#ibcon#read 5, iclass 14, count 0 2006.201.11:09:33.83#ibcon#about to read 6, iclass 14, count 0 2006.201.11:09:33.83#ibcon#read 6, iclass 14, count 0 2006.201.11:09:33.83#ibcon#end of sib2, iclass 14, count 0 2006.201.11:09:33.83#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:09:33.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:09:33.83#ibcon#[27=USB\r\n] 2006.201.11:09:33.83#ibcon#*before write, iclass 14, count 0 2006.201.11:09:33.83#ibcon#enter sib2, iclass 14, count 0 2006.201.11:09:33.83#ibcon#flushed, iclass 14, count 0 2006.201.11:09:33.83#ibcon#about to write, iclass 14, count 0 2006.201.11:09:33.83#ibcon#wrote, iclass 14, count 0 2006.201.11:09:33.83#ibcon#about to read 3, iclass 14, count 0 2006.201.11:09:33.86#ibcon#read 3, iclass 14, count 0 2006.201.11:09:33.86#ibcon#about to read 4, iclass 14, count 0 2006.201.11:09:33.86#ibcon#read 4, iclass 14, count 0 2006.201.11:09:33.86#ibcon#about to read 5, iclass 14, count 0 2006.201.11:09:33.86#ibcon#read 5, iclass 14, count 0 2006.201.11:09:33.86#ibcon#about to read 6, iclass 14, count 0 2006.201.11:09:33.86#ibcon#read 6, iclass 14, count 0 2006.201.11:09:33.86#ibcon#end of sib2, iclass 14, count 0 2006.201.11:09:33.86#ibcon#*after write, iclass 14, count 0 2006.201.11:09:33.86#ibcon#*before return 0, iclass 14, count 0 2006.201.11:09:33.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:33.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:09:33.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:09:33.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:09:33.86$vck44/vblo=2,634.99 2006.201.11:09:33.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.11:09:33.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.11:09:33.86#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:33.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:09:33.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:09:33.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:09:33.86#ibcon#enter wrdev, iclass 16, count 0 2006.201.11:09:33.86#ibcon#first serial, iclass 16, count 0 2006.201.11:09:33.86#ibcon#enter sib2, iclass 16, count 0 2006.201.11:09:33.86#ibcon#flushed, iclass 16, count 0 2006.201.11:09:33.86#ibcon#about to write, iclass 16, count 0 2006.201.11:09:33.86#ibcon#wrote, iclass 16, count 0 2006.201.11:09:33.86#ibcon#about to read 3, iclass 16, count 0 2006.201.11:09:33.88#ibcon#read 3, iclass 16, count 0 2006.201.11:09:33.88#ibcon#about to read 4, iclass 16, count 0 2006.201.11:09:33.88#ibcon#read 4, iclass 16, count 0 2006.201.11:09:33.88#ibcon#about to read 5, iclass 16, count 0 2006.201.11:09:33.88#ibcon#read 5, iclass 16, count 0 2006.201.11:09:33.88#ibcon#about to read 6, iclass 16, count 0 2006.201.11:09:33.88#ibcon#read 6, iclass 16, count 0 2006.201.11:09:33.88#ibcon#end of sib2, iclass 16, count 0 2006.201.11:09:33.88#ibcon#*mode == 0, iclass 16, count 0 2006.201.11:09:33.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.11:09:33.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:09:33.88#ibcon#*before write, iclass 16, count 0 2006.201.11:09:33.88#ibcon#enter sib2, iclass 16, count 0 2006.201.11:09:33.88#ibcon#flushed, iclass 16, count 0 2006.201.11:09:33.88#ibcon#about to write, iclass 16, count 0 2006.201.11:09:33.88#ibcon#wrote, iclass 16, count 0 2006.201.11:09:33.88#ibcon#about to read 3, iclass 16, count 0 2006.201.11:09:33.92#ibcon#read 3, iclass 16, count 0 2006.201.11:09:33.92#ibcon#about to read 4, iclass 16, count 0 2006.201.11:09:33.92#ibcon#read 4, iclass 16, count 0 2006.201.11:09:33.92#ibcon#about to read 5, iclass 16, count 0 2006.201.11:09:33.92#ibcon#read 5, iclass 16, count 0 2006.201.11:09:33.92#ibcon#about to read 6, iclass 16, count 0 2006.201.11:09:33.92#ibcon#read 6, iclass 16, count 0 2006.201.11:09:33.92#ibcon#end of sib2, iclass 16, count 0 2006.201.11:09:33.92#ibcon#*after write, iclass 16, count 0 2006.201.11:09:33.92#ibcon#*before return 0, iclass 16, count 0 2006.201.11:09:33.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:09:33.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:09:33.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.11:09:33.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.11:09:33.92$vck44/vb=2,5 2006.201.11:09:33.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.11:09:33.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.11:09:33.92#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:33.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:09:33.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:09:33.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:09:33.98#ibcon#enter wrdev, iclass 18, count 2 2006.201.11:09:33.98#ibcon#first serial, iclass 18, count 2 2006.201.11:09:33.98#ibcon#enter sib2, iclass 18, count 2 2006.201.11:09:33.98#ibcon#flushed, iclass 18, count 2 2006.201.11:09:33.98#ibcon#about to write, iclass 18, count 2 2006.201.11:09:33.98#ibcon#wrote, iclass 18, count 2 2006.201.11:09:33.98#ibcon#about to read 3, iclass 18, count 2 2006.201.11:09:34.00#ibcon#read 3, iclass 18, count 2 2006.201.11:09:34.00#ibcon#about to read 4, iclass 18, count 2 2006.201.11:09:34.00#ibcon#read 4, iclass 18, count 2 2006.201.11:09:34.00#ibcon#about to read 5, iclass 18, count 2 2006.201.11:09:34.00#ibcon#read 5, iclass 18, count 2 2006.201.11:09:34.00#ibcon#about to read 6, iclass 18, count 2 2006.201.11:09:34.00#ibcon#read 6, iclass 18, count 2 2006.201.11:09:34.00#ibcon#end of sib2, iclass 18, count 2 2006.201.11:09:34.00#ibcon#*mode == 0, iclass 18, count 2 2006.201.11:09:34.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.11:09:34.00#ibcon#[27=AT02-05\r\n] 2006.201.11:09:34.00#ibcon#*before write, iclass 18, count 2 2006.201.11:09:34.00#ibcon#enter sib2, iclass 18, count 2 2006.201.11:09:34.00#ibcon#flushed, iclass 18, count 2 2006.201.11:09:34.00#ibcon#about to write, iclass 18, count 2 2006.201.11:09:34.00#ibcon#wrote, iclass 18, count 2 2006.201.11:09:34.00#ibcon#about to read 3, iclass 18, count 2 2006.201.11:09:34.03#ibcon#read 3, iclass 18, count 2 2006.201.11:09:34.03#ibcon#about to read 4, iclass 18, count 2 2006.201.11:09:34.03#ibcon#read 4, iclass 18, count 2 2006.201.11:09:34.03#ibcon#about to read 5, iclass 18, count 2 2006.201.11:09:34.03#ibcon#read 5, iclass 18, count 2 2006.201.11:09:34.03#ibcon#about to read 6, iclass 18, count 2 2006.201.11:09:34.03#ibcon#read 6, iclass 18, count 2 2006.201.11:09:34.03#ibcon#end of sib2, iclass 18, count 2 2006.201.11:09:34.03#ibcon#*after write, iclass 18, count 2 2006.201.11:09:34.03#ibcon#*before return 0, iclass 18, count 2 2006.201.11:09:34.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:09:34.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:09:34.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.11:09:34.03#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:34.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:09:34.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:09:34.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:09:34.15#ibcon#enter wrdev, iclass 18, count 0 2006.201.11:09:34.15#ibcon#first serial, iclass 18, count 0 2006.201.11:09:34.15#ibcon#enter sib2, iclass 18, count 0 2006.201.11:09:34.15#ibcon#flushed, iclass 18, count 0 2006.201.11:09:34.15#ibcon#about to write, iclass 18, count 0 2006.201.11:09:34.15#ibcon#wrote, iclass 18, count 0 2006.201.11:09:34.15#ibcon#about to read 3, iclass 18, count 0 2006.201.11:09:34.17#ibcon#read 3, iclass 18, count 0 2006.201.11:09:34.17#ibcon#about to read 4, iclass 18, count 0 2006.201.11:09:34.17#ibcon#read 4, iclass 18, count 0 2006.201.11:09:34.17#ibcon#about to read 5, iclass 18, count 0 2006.201.11:09:34.17#ibcon#read 5, iclass 18, count 0 2006.201.11:09:34.17#ibcon#about to read 6, iclass 18, count 0 2006.201.11:09:34.17#ibcon#read 6, iclass 18, count 0 2006.201.11:09:34.17#ibcon#end of sib2, iclass 18, count 0 2006.201.11:09:34.17#ibcon#*mode == 0, iclass 18, count 0 2006.201.11:09:34.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.11:09:34.17#ibcon#[27=USB\r\n] 2006.201.11:09:34.17#ibcon#*before write, iclass 18, count 0 2006.201.11:09:34.17#ibcon#enter sib2, iclass 18, count 0 2006.201.11:09:34.17#ibcon#flushed, iclass 18, count 0 2006.201.11:09:34.17#ibcon#about to write, iclass 18, count 0 2006.201.11:09:34.17#ibcon#wrote, iclass 18, count 0 2006.201.11:09:34.17#ibcon#about to read 3, iclass 18, count 0 2006.201.11:09:34.20#ibcon#read 3, iclass 18, count 0 2006.201.11:09:34.20#ibcon#about to read 4, iclass 18, count 0 2006.201.11:09:34.20#ibcon#read 4, iclass 18, count 0 2006.201.11:09:34.20#ibcon#about to read 5, iclass 18, count 0 2006.201.11:09:34.20#ibcon#read 5, iclass 18, count 0 2006.201.11:09:34.20#ibcon#about to read 6, iclass 18, count 0 2006.201.11:09:34.20#ibcon#read 6, iclass 18, count 0 2006.201.11:09:34.20#ibcon#end of sib2, iclass 18, count 0 2006.201.11:09:34.20#ibcon#*after write, iclass 18, count 0 2006.201.11:09:34.20#ibcon#*before return 0, iclass 18, count 0 2006.201.11:09:34.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:09:34.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:09:34.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.11:09:34.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.11:09:34.20$vck44/vblo=3,649.99 2006.201.11:09:34.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.11:09:34.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.11:09:34.20#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:34.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:09:34.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:09:34.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:09:34.20#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:09:34.20#ibcon#first serial, iclass 20, count 0 2006.201.11:09:34.20#ibcon#enter sib2, iclass 20, count 0 2006.201.11:09:34.20#ibcon#flushed, iclass 20, count 0 2006.201.11:09:34.20#ibcon#about to write, iclass 20, count 0 2006.201.11:09:34.20#ibcon#wrote, iclass 20, count 0 2006.201.11:09:34.20#ibcon#about to read 3, iclass 20, count 0 2006.201.11:09:34.22#ibcon#read 3, iclass 20, count 0 2006.201.11:09:34.22#ibcon#about to read 4, iclass 20, count 0 2006.201.11:09:34.22#ibcon#read 4, iclass 20, count 0 2006.201.11:09:34.22#ibcon#about to read 5, iclass 20, count 0 2006.201.11:09:34.22#ibcon#read 5, iclass 20, count 0 2006.201.11:09:34.22#ibcon#about to read 6, iclass 20, count 0 2006.201.11:09:34.22#ibcon#read 6, iclass 20, count 0 2006.201.11:09:34.22#ibcon#end of sib2, iclass 20, count 0 2006.201.11:09:34.22#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:09:34.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:09:34.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:09:34.22#ibcon#*before write, iclass 20, count 0 2006.201.11:09:34.22#ibcon#enter sib2, iclass 20, count 0 2006.201.11:09:34.22#ibcon#flushed, iclass 20, count 0 2006.201.11:09:34.22#ibcon#about to write, iclass 20, count 0 2006.201.11:09:34.22#ibcon#wrote, iclass 20, count 0 2006.201.11:09:34.22#ibcon#about to read 3, iclass 20, count 0 2006.201.11:09:34.27#ibcon#read 3, iclass 20, count 0 2006.201.11:09:34.27#ibcon#about to read 4, iclass 20, count 0 2006.201.11:09:34.27#ibcon#read 4, iclass 20, count 0 2006.201.11:09:34.27#ibcon#about to read 5, iclass 20, count 0 2006.201.11:09:34.27#ibcon#read 5, iclass 20, count 0 2006.201.11:09:34.27#ibcon#about to read 6, iclass 20, count 0 2006.201.11:09:34.27#ibcon#read 6, iclass 20, count 0 2006.201.11:09:34.27#ibcon#end of sib2, iclass 20, count 0 2006.201.11:09:34.27#ibcon#*after write, iclass 20, count 0 2006.201.11:09:34.27#ibcon#*before return 0, iclass 20, count 0 2006.201.11:09:34.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:09:34.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:09:34.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:09:34.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:09:34.27$vck44/vb=3,4 2006.201.11:09:34.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.11:09:34.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.11:09:34.27#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:34.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:09:34.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:09:34.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:09:34.32#ibcon#enter wrdev, iclass 22, count 2 2006.201.11:09:34.32#ibcon#first serial, iclass 22, count 2 2006.201.11:09:34.32#ibcon#enter sib2, iclass 22, count 2 2006.201.11:09:34.32#ibcon#flushed, iclass 22, count 2 2006.201.11:09:34.32#ibcon#about to write, iclass 22, count 2 2006.201.11:09:34.32#ibcon#wrote, iclass 22, count 2 2006.201.11:09:34.32#ibcon#about to read 3, iclass 22, count 2 2006.201.11:09:34.34#ibcon#read 3, iclass 22, count 2 2006.201.11:09:34.34#ibcon#about to read 4, iclass 22, count 2 2006.201.11:09:34.34#ibcon#read 4, iclass 22, count 2 2006.201.11:09:34.34#ibcon#about to read 5, iclass 22, count 2 2006.201.11:09:34.34#ibcon#read 5, iclass 22, count 2 2006.201.11:09:34.34#ibcon#about to read 6, iclass 22, count 2 2006.201.11:09:34.34#ibcon#read 6, iclass 22, count 2 2006.201.11:09:34.34#ibcon#end of sib2, iclass 22, count 2 2006.201.11:09:34.34#ibcon#*mode == 0, iclass 22, count 2 2006.201.11:09:34.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.11:09:34.34#ibcon#[27=AT03-04\r\n] 2006.201.11:09:34.34#ibcon#*before write, iclass 22, count 2 2006.201.11:09:34.34#ibcon#enter sib2, iclass 22, count 2 2006.201.11:09:34.34#ibcon#flushed, iclass 22, count 2 2006.201.11:09:34.34#ibcon#about to write, iclass 22, count 2 2006.201.11:09:34.34#ibcon#wrote, iclass 22, count 2 2006.201.11:09:34.34#ibcon#about to read 3, iclass 22, count 2 2006.201.11:09:34.37#ibcon#read 3, iclass 22, count 2 2006.201.11:09:34.37#ibcon#about to read 4, iclass 22, count 2 2006.201.11:09:34.37#ibcon#read 4, iclass 22, count 2 2006.201.11:09:34.37#ibcon#about to read 5, iclass 22, count 2 2006.201.11:09:34.37#ibcon#read 5, iclass 22, count 2 2006.201.11:09:34.37#ibcon#about to read 6, iclass 22, count 2 2006.201.11:09:34.37#ibcon#read 6, iclass 22, count 2 2006.201.11:09:34.37#ibcon#end of sib2, iclass 22, count 2 2006.201.11:09:34.37#ibcon#*after write, iclass 22, count 2 2006.201.11:09:34.37#ibcon#*before return 0, iclass 22, count 2 2006.201.11:09:34.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:09:34.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:09:34.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.11:09:34.37#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:34.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:09:34.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:09:34.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:09:34.49#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:09:34.49#ibcon#first serial, iclass 22, count 0 2006.201.11:09:34.49#ibcon#enter sib2, iclass 22, count 0 2006.201.11:09:34.49#ibcon#flushed, iclass 22, count 0 2006.201.11:09:34.49#ibcon#about to write, iclass 22, count 0 2006.201.11:09:34.49#ibcon#wrote, iclass 22, count 0 2006.201.11:09:34.49#ibcon#about to read 3, iclass 22, count 0 2006.201.11:09:34.51#ibcon#read 3, iclass 22, count 0 2006.201.11:09:34.51#ibcon#about to read 4, iclass 22, count 0 2006.201.11:09:34.51#ibcon#read 4, iclass 22, count 0 2006.201.11:09:34.51#ibcon#about to read 5, iclass 22, count 0 2006.201.11:09:34.51#ibcon#read 5, iclass 22, count 0 2006.201.11:09:34.51#ibcon#about to read 6, iclass 22, count 0 2006.201.11:09:34.51#ibcon#read 6, iclass 22, count 0 2006.201.11:09:34.51#ibcon#end of sib2, iclass 22, count 0 2006.201.11:09:34.51#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:09:34.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:09:34.51#ibcon#[27=USB\r\n] 2006.201.11:09:34.51#ibcon#*before write, iclass 22, count 0 2006.201.11:09:34.51#ibcon#enter sib2, iclass 22, count 0 2006.201.11:09:34.51#ibcon#flushed, iclass 22, count 0 2006.201.11:09:34.51#ibcon#about to write, iclass 22, count 0 2006.201.11:09:34.51#ibcon#wrote, iclass 22, count 0 2006.201.11:09:34.51#ibcon#about to read 3, iclass 22, count 0 2006.201.11:09:34.54#ibcon#read 3, iclass 22, count 0 2006.201.11:09:34.54#ibcon#about to read 4, iclass 22, count 0 2006.201.11:09:34.54#ibcon#read 4, iclass 22, count 0 2006.201.11:09:34.54#ibcon#about to read 5, iclass 22, count 0 2006.201.11:09:34.54#ibcon#read 5, iclass 22, count 0 2006.201.11:09:34.54#ibcon#about to read 6, iclass 22, count 0 2006.201.11:09:34.54#ibcon#read 6, iclass 22, count 0 2006.201.11:09:34.54#ibcon#end of sib2, iclass 22, count 0 2006.201.11:09:34.54#ibcon#*after write, iclass 22, count 0 2006.201.11:09:34.54#ibcon#*before return 0, iclass 22, count 0 2006.201.11:09:34.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:09:34.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:09:34.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:09:34.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:09:34.54$vck44/vblo=4,679.99 2006.201.11:09:34.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.11:09:34.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.11:09:34.54#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:34.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:34.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:34.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:34.54#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:09:34.54#ibcon#first serial, iclass 24, count 0 2006.201.11:09:34.54#ibcon#enter sib2, iclass 24, count 0 2006.201.11:09:34.54#ibcon#flushed, iclass 24, count 0 2006.201.11:09:34.54#ibcon#about to write, iclass 24, count 0 2006.201.11:09:34.54#ibcon#wrote, iclass 24, count 0 2006.201.11:09:34.54#ibcon#about to read 3, iclass 24, count 0 2006.201.11:09:34.56#ibcon#read 3, iclass 24, count 0 2006.201.11:09:34.56#ibcon#about to read 4, iclass 24, count 0 2006.201.11:09:34.56#ibcon#read 4, iclass 24, count 0 2006.201.11:09:34.56#ibcon#about to read 5, iclass 24, count 0 2006.201.11:09:34.56#ibcon#read 5, iclass 24, count 0 2006.201.11:09:34.56#ibcon#about to read 6, iclass 24, count 0 2006.201.11:09:34.56#ibcon#read 6, iclass 24, count 0 2006.201.11:09:34.56#ibcon#end of sib2, iclass 24, count 0 2006.201.11:09:34.56#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:09:34.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:09:34.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:09:34.56#ibcon#*before write, iclass 24, count 0 2006.201.11:09:34.56#ibcon#enter sib2, iclass 24, count 0 2006.201.11:09:34.56#ibcon#flushed, iclass 24, count 0 2006.201.11:09:34.56#ibcon#about to write, iclass 24, count 0 2006.201.11:09:34.56#ibcon#wrote, iclass 24, count 0 2006.201.11:09:34.56#ibcon#about to read 3, iclass 24, count 0 2006.201.11:09:34.60#ibcon#read 3, iclass 24, count 0 2006.201.11:09:34.60#ibcon#about to read 4, iclass 24, count 0 2006.201.11:09:34.60#ibcon#read 4, iclass 24, count 0 2006.201.11:09:34.60#ibcon#about to read 5, iclass 24, count 0 2006.201.11:09:34.60#ibcon#read 5, iclass 24, count 0 2006.201.11:09:34.60#ibcon#about to read 6, iclass 24, count 0 2006.201.11:09:34.60#ibcon#read 6, iclass 24, count 0 2006.201.11:09:34.60#ibcon#end of sib2, iclass 24, count 0 2006.201.11:09:34.60#ibcon#*after write, iclass 24, count 0 2006.201.11:09:34.60#ibcon#*before return 0, iclass 24, count 0 2006.201.11:09:34.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:34.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:09:34.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:09:34.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:09:34.60$vck44/vb=4,5 2006.201.11:09:34.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.11:09:34.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.11:09:34.60#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:34.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:34.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:34.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:34.66#ibcon#enter wrdev, iclass 26, count 2 2006.201.11:09:34.66#ibcon#first serial, iclass 26, count 2 2006.201.11:09:34.66#ibcon#enter sib2, iclass 26, count 2 2006.201.11:09:34.66#ibcon#flushed, iclass 26, count 2 2006.201.11:09:34.66#ibcon#about to write, iclass 26, count 2 2006.201.11:09:34.66#ibcon#wrote, iclass 26, count 2 2006.201.11:09:34.66#ibcon#about to read 3, iclass 26, count 2 2006.201.11:09:34.68#ibcon#read 3, iclass 26, count 2 2006.201.11:09:34.68#ibcon#about to read 4, iclass 26, count 2 2006.201.11:09:34.68#ibcon#read 4, iclass 26, count 2 2006.201.11:09:34.68#ibcon#about to read 5, iclass 26, count 2 2006.201.11:09:34.68#ibcon#read 5, iclass 26, count 2 2006.201.11:09:34.68#ibcon#about to read 6, iclass 26, count 2 2006.201.11:09:34.68#ibcon#read 6, iclass 26, count 2 2006.201.11:09:34.68#ibcon#end of sib2, iclass 26, count 2 2006.201.11:09:34.68#ibcon#*mode == 0, iclass 26, count 2 2006.201.11:09:34.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.11:09:34.68#ibcon#[27=AT04-05\r\n] 2006.201.11:09:34.68#ibcon#*before write, iclass 26, count 2 2006.201.11:09:34.68#ibcon#enter sib2, iclass 26, count 2 2006.201.11:09:34.68#ibcon#flushed, iclass 26, count 2 2006.201.11:09:34.68#ibcon#about to write, iclass 26, count 2 2006.201.11:09:34.68#ibcon#wrote, iclass 26, count 2 2006.201.11:09:34.68#ibcon#about to read 3, iclass 26, count 2 2006.201.11:09:34.71#ibcon#read 3, iclass 26, count 2 2006.201.11:09:34.71#ibcon#about to read 4, iclass 26, count 2 2006.201.11:09:34.71#ibcon#read 4, iclass 26, count 2 2006.201.11:09:34.71#ibcon#about to read 5, iclass 26, count 2 2006.201.11:09:34.71#ibcon#read 5, iclass 26, count 2 2006.201.11:09:34.71#ibcon#about to read 6, iclass 26, count 2 2006.201.11:09:34.71#ibcon#read 6, iclass 26, count 2 2006.201.11:09:34.71#ibcon#end of sib2, iclass 26, count 2 2006.201.11:09:34.71#ibcon#*after write, iclass 26, count 2 2006.201.11:09:34.71#ibcon#*before return 0, iclass 26, count 2 2006.201.11:09:34.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:34.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:09:34.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.11:09:34.71#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:34.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:34.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:34.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:34.83#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:09:34.83#ibcon#first serial, iclass 26, count 0 2006.201.11:09:34.83#ibcon#enter sib2, iclass 26, count 0 2006.201.11:09:34.83#ibcon#flushed, iclass 26, count 0 2006.201.11:09:34.83#ibcon#about to write, iclass 26, count 0 2006.201.11:09:34.83#ibcon#wrote, iclass 26, count 0 2006.201.11:09:34.83#ibcon#about to read 3, iclass 26, count 0 2006.201.11:09:34.85#ibcon#read 3, iclass 26, count 0 2006.201.11:09:34.85#ibcon#about to read 4, iclass 26, count 0 2006.201.11:09:34.85#ibcon#read 4, iclass 26, count 0 2006.201.11:09:34.85#ibcon#about to read 5, iclass 26, count 0 2006.201.11:09:34.85#ibcon#read 5, iclass 26, count 0 2006.201.11:09:34.85#ibcon#about to read 6, iclass 26, count 0 2006.201.11:09:34.85#ibcon#read 6, iclass 26, count 0 2006.201.11:09:34.85#ibcon#end of sib2, iclass 26, count 0 2006.201.11:09:34.85#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:09:34.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:09:34.85#ibcon#[27=USB\r\n] 2006.201.11:09:34.85#ibcon#*before write, iclass 26, count 0 2006.201.11:09:34.85#ibcon#enter sib2, iclass 26, count 0 2006.201.11:09:34.85#ibcon#flushed, iclass 26, count 0 2006.201.11:09:34.85#ibcon#about to write, iclass 26, count 0 2006.201.11:09:34.85#ibcon#wrote, iclass 26, count 0 2006.201.11:09:34.85#ibcon#about to read 3, iclass 26, count 0 2006.201.11:09:34.88#ibcon#read 3, iclass 26, count 0 2006.201.11:09:34.88#ibcon#about to read 4, iclass 26, count 0 2006.201.11:09:34.88#ibcon#read 4, iclass 26, count 0 2006.201.11:09:34.88#ibcon#about to read 5, iclass 26, count 0 2006.201.11:09:34.88#ibcon#read 5, iclass 26, count 0 2006.201.11:09:34.88#ibcon#about to read 6, iclass 26, count 0 2006.201.11:09:34.88#ibcon#read 6, iclass 26, count 0 2006.201.11:09:34.88#ibcon#end of sib2, iclass 26, count 0 2006.201.11:09:34.88#ibcon#*after write, iclass 26, count 0 2006.201.11:09:34.88#ibcon#*before return 0, iclass 26, count 0 2006.201.11:09:34.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:34.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:09:34.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:09:34.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:09:34.88$vck44/vblo=5,709.99 2006.201.11:09:34.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.11:09:34.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.11:09:34.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:34.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:34.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:34.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:34.88#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:09:34.88#ibcon#first serial, iclass 28, count 0 2006.201.11:09:34.88#ibcon#enter sib2, iclass 28, count 0 2006.201.11:09:34.88#ibcon#flushed, iclass 28, count 0 2006.201.11:09:34.88#ibcon#about to write, iclass 28, count 0 2006.201.11:09:34.88#ibcon#wrote, iclass 28, count 0 2006.201.11:09:34.88#ibcon#about to read 3, iclass 28, count 0 2006.201.11:09:34.90#ibcon#read 3, iclass 28, count 0 2006.201.11:09:34.90#ibcon#about to read 4, iclass 28, count 0 2006.201.11:09:34.90#ibcon#read 4, iclass 28, count 0 2006.201.11:09:34.90#ibcon#about to read 5, iclass 28, count 0 2006.201.11:09:34.90#ibcon#read 5, iclass 28, count 0 2006.201.11:09:34.90#ibcon#about to read 6, iclass 28, count 0 2006.201.11:09:34.90#ibcon#read 6, iclass 28, count 0 2006.201.11:09:34.90#ibcon#end of sib2, iclass 28, count 0 2006.201.11:09:34.90#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:09:34.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:09:34.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:09:34.90#ibcon#*before write, iclass 28, count 0 2006.201.11:09:34.90#ibcon#enter sib2, iclass 28, count 0 2006.201.11:09:34.90#ibcon#flushed, iclass 28, count 0 2006.201.11:09:34.90#ibcon#about to write, iclass 28, count 0 2006.201.11:09:34.90#ibcon#wrote, iclass 28, count 0 2006.201.11:09:34.90#ibcon#about to read 3, iclass 28, count 0 2006.201.11:09:34.94#ibcon#read 3, iclass 28, count 0 2006.201.11:09:34.94#ibcon#about to read 4, iclass 28, count 0 2006.201.11:09:34.94#ibcon#read 4, iclass 28, count 0 2006.201.11:09:34.94#ibcon#about to read 5, iclass 28, count 0 2006.201.11:09:34.94#ibcon#read 5, iclass 28, count 0 2006.201.11:09:34.94#ibcon#about to read 6, iclass 28, count 0 2006.201.11:09:34.94#ibcon#read 6, iclass 28, count 0 2006.201.11:09:34.94#ibcon#end of sib2, iclass 28, count 0 2006.201.11:09:34.94#ibcon#*after write, iclass 28, count 0 2006.201.11:09:34.94#ibcon#*before return 0, iclass 28, count 0 2006.201.11:09:34.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:34.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:09:34.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:09:34.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:09:34.94$vck44/vb=5,4 2006.201.11:09:34.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.11:09:34.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.11:09:34.94#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:34.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:35.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:35.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:35.00#ibcon#enter wrdev, iclass 30, count 2 2006.201.11:09:35.00#ibcon#first serial, iclass 30, count 2 2006.201.11:09:35.00#ibcon#enter sib2, iclass 30, count 2 2006.201.11:09:35.00#ibcon#flushed, iclass 30, count 2 2006.201.11:09:35.00#ibcon#about to write, iclass 30, count 2 2006.201.11:09:35.00#ibcon#wrote, iclass 30, count 2 2006.201.11:09:35.00#ibcon#about to read 3, iclass 30, count 2 2006.201.11:09:35.02#ibcon#read 3, iclass 30, count 2 2006.201.11:09:35.02#ibcon#about to read 4, iclass 30, count 2 2006.201.11:09:35.02#ibcon#read 4, iclass 30, count 2 2006.201.11:09:35.02#ibcon#about to read 5, iclass 30, count 2 2006.201.11:09:35.02#ibcon#read 5, iclass 30, count 2 2006.201.11:09:35.02#ibcon#about to read 6, iclass 30, count 2 2006.201.11:09:35.02#ibcon#read 6, iclass 30, count 2 2006.201.11:09:35.02#ibcon#end of sib2, iclass 30, count 2 2006.201.11:09:35.02#ibcon#*mode == 0, iclass 30, count 2 2006.201.11:09:35.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.11:09:35.02#ibcon#[27=AT05-04\r\n] 2006.201.11:09:35.02#ibcon#*before write, iclass 30, count 2 2006.201.11:09:35.02#ibcon#enter sib2, iclass 30, count 2 2006.201.11:09:35.02#ibcon#flushed, iclass 30, count 2 2006.201.11:09:35.02#ibcon#about to write, iclass 30, count 2 2006.201.11:09:35.02#ibcon#wrote, iclass 30, count 2 2006.201.11:09:35.02#ibcon#about to read 3, iclass 30, count 2 2006.201.11:09:35.05#ibcon#read 3, iclass 30, count 2 2006.201.11:09:35.05#ibcon#about to read 4, iclass 30, count 2 2006.201.11:09:35.05#ibcon#read 4, iclass 30, count 2 2006.201.11:09:35.05#ibcon#about to read 5, iclass 30, count 2 2006.201.11:09:35.05#ibcon#read 5, iclass 30, count 2 2006.201.11:09:35.05#ibcon#about to read 6, iclass 30, count 2 2006.201.11:09:35.05#ibcon#read 6, iclass 30, count 2 2006.201.11:09:35.05#ibcon#end of sib2, iclass 30, count 2 2006.201.11:09:35.05#ibcon#*after write, iclass 30, count 2 2006.201.11:09:35.05#ibcon#*before return 0, iclass 30, count 2 2006.201.11:09:35.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:35.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:09:35.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.11:09:35.05#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:35.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:35.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:35.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:35.17#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:09:35.17#ibcon#first serial, iclass 30, count 0 2006.201.11:09:35.17#ibcon#enter sib2, iclass 30, count 0 2006.201.11:09:35.17#ibcon#flushed, iclass 30, count 0 2006.201.11:09:35.17#ibcon#about to write, iclass 30, count 0 2006.201.11:09:35.17#ibcon#wrote, iclass 30, count 0 2006.201.11:09:35.17#ibcon#about to read 3, iclass 30, count 0 2006.201.11:09:35.19#ibcon#read 3, iclass 30, count 0 2006.201.11:09:35.19#ibcon#about to read 4, iclass 30, count 0 2006.201.11:09:35.19#ibcon#read 4, iclass 30, count 0 2006.201.11:09:35.19#ibcon#about to read 5, iclass 30, count 0 2006.201.11:09:35.19#ibcon#read 5, iclass 30, count 0 2006.201.11:09:35.19#ibcon#about to read 6, iclass 30, count 0 2006.201.11:09:35.19#ibcon#read 6, iclass 30, count 0 2006.201.11:09:35.19#ibcon#end of sib2, iclass 30, count 0 2006.201.11:09:35.19#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:09:35.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:09:35.19#ibcon#[27=USB\r\n] 2006.201.11:09:35.19#ibcon#*before write, iclass 30, count 0 2006.201.11:09:35.19#ibcon#enter sib2, iclass 30, count 0 2006.201.11:09:35.19#ibcon#flushed, iclass 30, count 0 2006.201.11:09:35.19#ibcon#about to write, iclass 30, count 0 2006.201.11:09:35.19#ibcon#wrote, iclass 30, count 0 2006.201.11:09:35.19#ibcon#about to read 3, iclass 30, count 0 2006.201.11:09:35.22#ibcon#read 3, iclass 30, count 0 2006.201.11:09:35.22#ibcon#about to read 4, iclass 30, count 0 2006.201.11:09:35.22#ibcon#read 4, iclass 30, count 0 2006.201.11:09:35.22#ibcon#about to read 5, iclass 30, count 0 2006.201.11:09:35.22#ibcon#read 5, iclass 30, count 0 2006.201.11:09:35.22#ibcon#about to read 6, iclass 30, count 0 2006.201.11:09:35.22#ibcon#read 6, iclass 30, count 0 2006.201.11:09:35.22#ibcon#end of sib2, iclass 30, count 0 2006.201.11:09:35.22#ibcon#*after write, iclass 30, count 0 2006.201.11:09:35.22#ibcon#*before return 0, iclass 30, count 0 2006.201.11:09:35.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:35.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:09:35.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:09:35.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:09:35.22$vck44/vblo=6,719.99 2006.201.11:09:35.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.11:09:35.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.11:09:35.22#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:35.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:35.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:35.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:35.22#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:09:35.22#ibcon#first serial, iclass 32, count 0 2006.201.11:09:35.22#ibcon#enter sib2, iclass 32, count 0 2006.201.11:09:35.22#ibcon#flushed, iclass 32, count 0 2006.201.11:09:35.22#ibcon#about to write, iclass 32, count 0 2006.201.11:09:35.22#ibcon#wrote, iclass 32, count 0 2006.201.11:09:35.22#ibcon#about to read 3, iclass 32, count 0 2006.201.11:09:35.24#ibcon#read 3, iclass 32, count 0 2006.201.11:09:35.24#ibcon#about to read 4, iclass 32, count 0 2006.201.11:09:35.24#ibcon#read 4, iclass 32, count 0 2006.201.11:09:35.24#ibcon#about to read 5, iclass 32, count 0 2006.201.11:09:35.24#ibcon#read 5, iclass 32, count 0 2006.201.11:09:35.24#ibcon#about to read 6, iclass 32, count 0 2006.201.11:09:35.24#ibcon#read 6, iclass 32, count 0 2006.201.11:09:35.24#ibcon#end of sib2, iclass 32, count 0 2006.201.11:09:35.24#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:09:35.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:09:35.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:09:35.24#ibcon#*before write, iclass 32, count 0 2006.201.11:09:35.24#ibcon#enter sib2, iclass 32, count 0 2006.201.11:09:35.24#ibcon#flushed, iclass 32, count 0 2006.201.11:09:35.24#ibcon#about to write, iclass 32, count 0 2006.201.11:09:35.24#ibcon#wrote, iclass 32, count 0 2006.201.11:09:35.24#ibcon#about to read 3, iclass 32, count 0 2006.201.11:09:35.28#ibcon#read 3, iclass 32, count 0 2006.201.11:09:35.28#ibcon#about to read 4, iclass 32, count 0 2006.201.11:09:35.28#ibcon#read 4, iclass 32, count 0 2006.201.11:09:35.28#ibcon#about to read 5, iclass 32, count 0 2006.201.11:09:35.28#ibcon#read 5, iclass 32, count 0 2006.201.11:09:35.28#ibcon#about to read 6, iclass 32, count 0 2006.201.11:09:35.28#ibcon#read 6, iclass 32, count 0 2006.201.11:09:35.28#ibcon#end of sib2, iclass 32, count 0 2006.201.11:09:35.28#ibcon#*after write, iclass 32, count 0 2006.201.11:09:35.28#ibcon#*before return 0, iclass 32, count 0 2006.201.11:09:35.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:35.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:09:35.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:09:35.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:09:35.28$vck44/vb=6,4 2006.201.11:09:35.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.11:09:35.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.11:09:35.28#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:35.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:35.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:35.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:35.34#ibcon#enter wrdev, iclass 34, count 2 2006.201.11:09:35.34#ibcon#first serial, iclass 34, count 2 2006.201.11:09:35.34#ibcon#enter sib2, iclass 34, count 2 2006.201.11:09:35.34#ibcon#flushed, iclass 34, count 2 2006.201.11:09:35.34#ibcon#about to write, iclass 34, count 2 2006.201.11:09:35.34#ibcon#wrote, iclass 34, count 2 2006.201.11:09:35.34#ibcon#about to read 3, iclass 34, count 2 2006.201.11:09:35.36#ibcon#read 3, iclass 34, count 2 2006.201.11:09:35.36#ibcon#about to read 4, iclass 34, count 2 2006.201.11:09:35.36#ibcon#read 4, iclass 34, count 2 2006.201.11:09:35.36#ibcon#about to read 5, iclass 34, count 2 2006.201.11:09:35.36#ibcon#read 5, iclass 34, count 2 2006.201.11:09:35.36#ibcon#about to read 6, iclass 34, count 2 2006.201.11:09:35.36#ibcon#read 6, iclass 34, count 2 2006.201.11:09:35.36#ibcon#end of sib2, iclass 34, count 2 2006.201.11:09:35.36#ibcon#*mode == 0, iclass 34, count 2 2006.201.11:09:35.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.11:09:35.36#ibcon#[27=AT06-04\r\n] 2006.201.11:09:35.36#ibcon#*before write, iclass 34, count 2 2006.201.11:09:35.36#ibcon#enter sib2, iclass 34, count 2 2006.201.11:09:35.36#ibcon#flushed, iclass 34, count 2 2006.201.11:09:35.36#ibcon#about to write, iclass 34, count 2 2006.201.11:09:35.36#ibcon#wrote, iclass 34, count 2 2006.201.11:09:35.36#ibcon#about to read 3, iclass 34, count 2 2006.201.11:09:35.39#ibcon#read 3, iclass 34, count 2 2006.201.11:09:35.39#ibcon#about to read 4, iclass 34, count 2 2006.201.11:09:35.39#ibcon#read 4, iclass 34, count 2 2006.201.11:09:35.39#ibcon#about to read 5, iclass 34, count 2 2006.201.11:09:35.39#ibcon#read 5, iclass 34, count 2 2006.201.11:09:35.39#ibcon#about to read 6, iclass 34, count 2 2006.201.11:09:35.39#ibcon#read 6, iclass 34, count 2 2006.201.11:09:35.39#ibcon#end of sib2, iclass 34, count 2 2006.201.11:09:35.39#ibcon#*after write, iclass 34, count 2 2006.201.11:09:35.39#ibcon#*before return 0, iclass 34, count 2 2006.201.11:09:35.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:35.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:09:35.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.11:09:35.39#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:35.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:35.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:35.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:35.51#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:09:35.51#ibcon#first serial, iclass 34, count 0 2006.201.11:09:35.51#ibcon#enter sib2, iclass 34, count 0 2006.201.11:09:35.51#ibcon#flushed, iclass 34, count 0 2006.201.11:09:35.51#ibcon#about to write, iclass 34, count 0 2006.201.11:09:35.51#ibcon#wrote, iclass 34, count 0 2006.201.11:09:35.51#ibcon#about to read 3, iclass 34, count 0 2006.201.11:09:35.53#ibcon#read 3, iclass 34, count 0 2006.201.11:09:35.53#ibcon#about to read 4, iclass 34, count 0 2006.201.11:09:35.53#ibcon#read 4, iclass 34, count 0 2006.201.11:09:35.53#ibcon#about to read 5, iclass 34, count 0 2006.201.11:09:35.53#ibcon#read 5, iclass 34, count 0 2006.201.11:09:35.53#ibcon#about to read 6, iclass 34, count 0 2006.201.11:09:35.53#ibcon#read 6, iclass 34, count 0 2006.201.11:09:35.53#ibcon#end of sib2, iclass 34, count 0 2006.201.11:09:35.53#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:09:35.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:09:35.53#ibcon#[27=USB\r\n] 2006.201.11:09:35.53#ibcon#*before write, iclass 34, count 0 2006.201.11:09:35.53#ibcon#enter sib2, iclass 34, count 0 2006.201.11:09:35.53#ibcon#flushed, iclass 34, count 0 2006.201.11:09:35.53#ibcon#about to write, iclass 34, count 0 2006.201.11:09:35.53#ibcon#wrote, iclass 34, count 0 2006.201.11:09:35.53#ibcon#about to read 3, iclass 34, count 0 2006.201.11:09:35.56#ibcon#read 3, iclass 34, count 0 2006.201.11:09:35.56#ibcon#about to read 4, iclass 34, count 0 2006.201.11:09:35.56#ibcon#read 4, iclass 34, count 0 2006.201.11:09:35.56#ibcon#about to read 5, iclass 34, count 0 2006.201.11:09:35.56#ibcon#read 5, iclass 34, count 0 2006.201.11:09:35.56#ibcon#about to read 6, iclass 34, count 0 2006.201.11:09:35.56#ibcon#read 6, iclass 34, count 0 2006.201.11:09:35.56#ibcon#end of sib2, iclass 34, count 0 2006.201.11:09:35.56#ibcon#*after write, iclass 34, count 0 2006.201.11:09:35.56#ibcon#*before return 0, iclass 34, count 0 2006.201.11:09:35.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:35.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:09:35.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:09:35.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:09:35.56$vck44/vblo=7,734.99 2006.201.11:09:35.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.11:09:35.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.11:09:35.56#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:35.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:35.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:35.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:35.56#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:09:35.56#ibcon#first serial, iclass 36, count 0 2006.201.11:09:35.56#ibcon#enter sib2, iclass 36, count 0 2006.201.11:09:35.56#ibcon#flushed, iclass 36, count 0 2006.201.11:09:35.56#ibcon#about to write, iclass 36, count 0 2006.201.11:09:35.56#ibcon#wrote, iclass 36, count 0 2006.201.11:09:35.56#ibcon#about to read 3, iclass 36, count 0 2006.201.11:09:35.58#ibcon#read 3, iclass 36, count 0 2006.201.11:09:35.58#ibcon#about to read 4, iclass 36, count 0 2006.201.11:09:35.58#ibcon#read 4, iclass 36, count 0 2006.201.11:09:35.58#ibcon#about to read 5, iclass 36, count 0 2006.201.11:09:35.58#ibcon#read 5, iclass 36, count 0 2006.201.11:09:35.58#ibcon#about to read 6, iclass 36, count 0 2006.201.11:09:35.58#ibcon#read 6, iclass 36, count 0 2006.201.11:09:35.58#ibcon#end of sib2, iclass 36, count 0 2006.201.11:09:35.58#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:09:35.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:09:35.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:09:35.58#ibcon#*before write, iclass 36, count 0 2006.201.11:09:35.58#ibcon#enter sib2, iclass 36, count 0 2006.201.11:09:35.58#ibcon#flushed, iclass 36, count 0 2006.201.11:09:35.58#ibcon#about to write, iclass 36, count 0 2006.201.11:09:35.58#ibcon#wrote, iclass 36, count 0 2006.201.11:09:35.58#ibcon#about to read 3, iclass 36, count 0 2006.201.11:09:35.62#ibcon#read 3, iclass 36, count 0 2006.201.11:09:35.62#ibcon#about to read 4, iclass 36, count 0 2006.201.11:09:35.62#ibcon#read 4, iclass 36, count 0 2006.201.11:09:35.62#ibcon#about to read 5, iclass 36, count 0 2006.201.11:09:35.62#ibcon#read 5, iclass 36, count 0 2006.201.11:09:35.62#ibcon#about to read 6, iclass 36, count 0 2006.201.11:09:35.62#ibcon#read 6, iclass 36, count 0 2006.201.11:09:35.62#ibcon#end of sib2, iclass 36, count 0 2006.201.11:09:35.62#ibcon#*after write, iclass 36, count 0 2006.201.11:09:35.62#ibcon#*before return 0, iclass 36, count 0 2006.201.11:09:35.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:35.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:09:35.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:09:35.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:09:35.62$vck44/vb=7,4 2006.201.11:09:35.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.11:09:35.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.11:09:35.62#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:35.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:35.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:35.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:35.68#ibcon#enter wrdev, iclass 38, count 2 2006.201.11:09:35.68#ibcon#first serial, iclass 38, count 2 2006.201.11:09:35.68#ibcon#enter sib2, iclass 38, count 2 2006.201.11:09:35.68#ibcon#flushed, iclass 38, count 2 2006.201.11:09:35.68#ibcon#about to write, iclass 38, count 2 2006.201.11:09:35.68#ibcon#wrote, iclass 38, count 2 2006.201.11:09:35.68#ibcon#about to read 3, iclass 38, count 2 2006.201.11:09:35.70#ibcon#read 3, iclass 38, count 2 2006.201.11:09:35.70#ibcon#about to read 4, iclass 38, count 2 2006.201.11:09:35.70#ibcon#read 4, iclass 38, count 2 2006.201.11:09:35.70#ibcon#about to read 5, iclass 38, count 2 2006.201.11:09:35.70#ibcon#read 5, iclass 38, count 2 2006.201.11:09:35.70#ibcon#about to read 6, iclass 38, count 2 2006.201.11:09:35.70#ibcon#read 6, iclass 38, count 2 2006.201.11:09:35.70#ibcon#end of sib2, iclass 38, count 2 2006.201.11:09:35.70#ibcon#*mode == 0, iclass 38, count 2 2006.201.11:09:35.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.11:09:35.70#ibcon#[27=AT07-04\r\n] 2006.201.11:09:35.70#ibcon#*before write, iclass 38, count 2 2006.201.11:09:35.70#ibcon#enter sib2, iclass 38, count 2 2006.201.11:09:35.70#ibcon#flushed, iclass 38, count 2 2006.201.11:09:35.70#ibcon#about to write, iclass 38, count 2 2006.201.11:09:35.70#ibcon#wrote, iclass 38, count 2 2006.201.11:09:35.70#ibcon#about to read 3, iclass 38, count 2 2006.201.11:09:35.73#ibcon#read 3, iclass 38, count 2 2006.201.11:09:35.73#ibcon#about to read 4, iclass 38, count 2 2006.201.11:09:35.73#ibcon#read 4, iclass 38, count 2 2006.201.11:09:35.73#ibcon#about to read 5, iclass 38, count 2 2006.201.11:09:35.73#ibcon#read 5, iclass 38, count 2 2006.201.11:09:35.73#ibcon#about to read 6, iclass 38, count 2 2006.201.11:09:35.73#ibcon#read 6, iclass 38, count 2 2006.201.11:09:35.73#ibcon#end of sib2, iclass 38, count 2 2006.201.11:09:35.73#ibcon#*after write, iclass 38, count 2 2006.201.11:09:35.73#ibcon#*before return 0, iclass 38, count 2 2006.201.11:09:35.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:35.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:09:35.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.11:09:35.73#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:35.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:35.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:35.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:35.85#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:09:35.85#ibcon#first serial, iclass 38, count 0 2006.201.11:09:35.85#ibcon#enter sib2, iclass 38, count 0 2006.201.11:09:35.85#ibcon#flushed, iclass 38, count 0 2006.201.11:09:35.85#ibcon#about to write, iclass 38, count 0 2006.201.11:09:35.85#ibcon#wrote, iclass 38, count 0 2006.201.11:09:35.85#ibcon#about to read 3, iclass 38, count 0 2006.201.11:09:35.87#ibcon#read 3, iclass 38, count 0 2006.201.11:09:35.87#ibcon#about to read 4, iclass 38, count 0 2006.201.11:09:35.87#ibcon#read 4, iclass 38, count 0 2006.201.11:09:35.87#ibcon#about to read 5, iclass 38, count 0 2006.201.11:09:35.87#ibcon#read 5, iclass 38, count 0 2006.201.11:09:35.87#ibcon#about to read 6, iclass 38, count 0 2006.201.11:09:35.87#ibcon#read 6, iclass 38, count 0 2006.201.11:09:35.87#ibcon#end of sib2, iclass 38, count 0 2006.201.11:09:35.87#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:09:35.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:09:35.87#ibcon#[27=USB\r\n] 2006.201.11:09:35.87#ibcon#*before write, iclass 38, count 0 2006.201.11:09:35.87#ibcon#enter sib2, iclass 38, count 0 2006.201.11:09:35.87#ibcon#flushed, iclass 38, count 0 2006.201.11:09:35.87#ibcon#about to write, iclass 38, count 0 2006.201.11:09:35.87#ibcon#wrote, iclass 38, count 0 2006.201.11:09:35.87#ibcon#about to read 3, iclass 38, count 0 2006.201.11:09:35.90#ibcon#read 3, iclass 38, count 0 2006.201.11:09:35.90#ibcon#about to read 4, iclass 38, count 0 2006.201.11:09:35.90#ibcon#read 4, iclass 38, count 0 2006.201.11:09:35.90#ibcon#about to read 5, iclass 38, count 0 2006.201.11:09:35.90#ibcon#read 5, iclass 38, count 0 2006.201.11:09:35.90#ibcon#about to read 6, iclass 38, count 0 2006.201.11:09:35.90#ibcon#read 6, iclass 38, count 0 2006.201.11:09:35.90#ibcon#end of sib2, iclass 38, count 0 2006.201.11:09:35.90#ibcon#*after write, iclass 38, count 0 2006.201.11:09:35.90#ibcon#*before return 0, iclass 38, count 0 2006.201.11:09:35.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:35.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:09:35.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:09:35.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:09:35.90$vck44/vblo=8,744.99 2006.201.11:09:35.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.11:09:35.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.11:09:35.90#ibcon#ireg 17 cls_cnt 0 2006.201.11:09:35.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:35.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:35.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:35.90#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:09:35.90#ibcon#first serial, iclass 40, count 0 2006.201.11:09:35.90#ibcon#enter sib2, iclass 40, count 0 2006.201.11:09:35.90#ibcon#flushed, iclass 40, count 0 2006.201.11:09:35.90#ibcon#about to write, iclass 40, count 0 2006.201.11:09:35.90#ibcon#wrote, iclass 40, count 0 2006.201.11:09:35.90#ibcon#about to read 3, iclass 40, count 0 2006.201.11:09:35.92#ibcon#read 3, iclass 40, count 0 2006.201.11:09:35.92#ibcon#about to read 4, iclass 40, count 0 2006.201.11:09:35.92#ibcon#read 4, iclass 40, count 0 2006.201.11:09:35.92#ibcon#about to read 5, iclass 40, count 0 2006.201.11:09:35.92#ibcon#read 5, iclass 40, count 0 2006.201.11:09:35.92#ibcon#about to read 6, iclass 40, count 0 2006.201.11:09:35.92#ibcon#read 6, iclass 40, count 0 2006.201.11:09:35.92#ibcon#end of sib2, iclass 40, count 0 2006.201.11:09:35.92#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:09:35.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:09:35.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:09:35.92#ibcon#*before write, iclass 40, count 0 2006.201.11:09:35.92#ibcon#enter sib2, iclass 40, count 0 2006.201.11:09:35.92#ibcon#flushed, iclass 40, count 0 2006.201.11:09:35.92#ibcon#about to write, iclass 40, count 0 2006.201.11:09:35.92#ibcon#wrote, iclass 40, count 0 2006.201.11:09:35.92#ibcon#about to read 3, iclass 40, count 0 2006.201.11:09:35.97#ibcon#read 3, iclass 40, count 0 2006.201.11:09:35.97#ibcon#about to read 4, iclass 40, count 0 2006.201.11:09:35.97#ibcon#read 4, iclass 40, count 0 2006.201.11:09:35.97#ibcon#about to read 5, iclass 40, count 0 2006.201.11:09:35.97#ibcon#read 5, iclass 40, count 0 2006.201.11:09:35.97#ibcon#about to read 6, iclass 40, count 0 2006.201.11:09:35.97#ibcon#read 6, iclass 40, count 0 2006.201.11:09:35.97#ibcon#end of sib2, iclass 40, count 0 2006.201.11:09:35.97#ibcon#*after write, iclass 40, count 0 2006.201.11:09:35.97#ibcon#*before return 0, iclass 40, count 0 2006.201.11:09:35.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:35.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:09:35.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:09:35.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:09:35.97$vck44/vb=8,4 2006.201.11:09:35.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.11:09:35.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.11:09:35.97#ibcon#ireg 11 cls_cnt 2 2006.201.11:09:35.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:36.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:36.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:36.02#ibcon#enter wrdev, iclass 4, count 2 2006.201.11:09:36.02#ibcon#first serial, iclass 4, count 2 2006.201.11:09:36.02#ibcon#enter sib2, iclass 4, count 2 2006.201.11:09:36.02#ibcon#flushed, iclass 4, count 2 2006.201.11:09:36.02#ibcon#about to write, iclass 4, count 2 2006.201.11:09:36.02#ibcon#wrote, iclass 4, count 2 2006.201.11:09:36.02#ibcon#about to read 3, iclass 4, count 2 2006.201.11:09:36.04#ibcon#read 3, iclass 4, count 2 2006.201.11:09:36.04#ibcon#about to read 4, iclass 4, count 2 2006.201.11:09:36.04#ibcon#read 4, iclass 4, count 2 2006.201.11:09:36.04#ibcon#about to read 5, iclass 4, count 2 2006.201.11:09:36.04#ibcon#read 5, iclass 4, count 2 2006.201.11:09:36.04#ibcon#about to read 6, iclass 4, count 2 2006.201.11:09:36.04#ibcon#read 6, iclass 4, count 2 2006.201.11:09:36.04#ibcon#end of sib2, iclass 4, count 2 2006.201.11:09:36.04#ibcon#*mode == 0, iclass 4, count 2 2006.201.11:09:36.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.11:09:36.04#ibcon#[27=AT08-04\r\n] 2006.201.11:09:36.04#ibcon#*before write, iclass 4, count 2 2006.201.11:09:36.04#ibcon#enter sib2, iclass 4, count 2 2006.201.11:09:36.04#ibcon#flushed, iclass 4, count 2 2006.201.11:09:36.04#ibcon#about to write, iclass 4, count 2 2006.201.11:09:36.04#ibcon#wrote, iclass 4, count 2 2006.201.11:09:36.04#ibcon#about to read 3, iclass 4, count 2 2006.201.11:09:36.07#ibcon#read 3, iclass 4, count 2 2006.201.11:09:36.07#ibcon#about to read 4, iclass 4, count 2 2006.201.11:09:36.07#ibcon#read 4, iclass 4, count 2 2006.201.11:09:36.07#ibcon#about to read 5, iclass 4, count 2 2006.201.11:09:36.07#ibcon#read 5, iclass 4, count 2 2006.201.11:09:36.07#ibcon#about to read 6, iclass 4, count 2 2006.201.11:09:36.07#ibcon#read 6, iclass 4, count 2 2006.201.11:09:36.07#ibcon#end of sib2, iclass 4, count 2 2006.201.11:09:36.07#ibcon#*after write, iclass 4, count 2 2006.201.11:09:36.07#ibcon#*before return 0, iclass 4, count 2 2006.201.11:09:36.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:36.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:09:36.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.11:09:36.07#ibcon#ireg 7 cls_cnt 0 2006.201.11:09:36.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:36.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:36.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:36.19#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:09:36.19#ibcon#first serial, iclass 4, count 0 2006.201.11:09:36.19#ibcon#enter sib2, iclass 4, count 0 2006.201.11:09:36.19#ibcon#flushed, iclass 4, count 0 2006.201.11:09:36.19#ibcon#about to write, iclass 4, count 0 2006.201.11:09:36.19#ibcon#wrote, iclass 4, count 0 2006.201.11:09:36.19#ibcon#about to read 3, iclass 4, count 0 2006.201.11:09:36.21#ibcon#read 3, iclass 4, count 0 2006.201.11:09:36.21#ibcon#about to read 4, iclass 4, count 0 2006.201.11:09:36.21#ibcon#read 4, iclass 4, count 0 2006.201.11:09:36.21#ibcon#about to read 5, iclass 4, count 0 2006.201.11:09:36.21#ibcon#read 5, iclass 4, count 0 2006.201.11:09:36.21#ibcon#about to read 6, iclass 4, count 0 2006.201.11:09:36.21#ibcon#read 6, iclass 4, count 0 2006.201.11:09:36.21#ibcon#end of sib2, iclass 4, count 0 2006.201.11:09:36.21#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:09:36.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:09:36.21#ibcon#[27=USB\r\n] 2006.201.11:09:36.21#ibcon#*before write, iclass 4, count 0 2006.201.11:09:36.21#ibcon#enter sib2, iclass 4, count 0 2006.201.11:09:36.21#ibcon#flushed, iclass 4, count 0 2006.201.11:09:36.21#ibcon#about to write, iclass 4, count 0 2006.201.11:09:36.21#ibcon#wrote, iclass 4, count 0 2006.201.11:09:36.21#ibcon#about to read 3, iclass 4, count 0 2006.201.11:09:36.24#ibcon#read 3, iclass 4, count 0 2006.201.11:09:36.24#ibcon#about to read 4, iclass 4, count 0 2006.201.11:09:36.24#ibcon#read 4, iclass 4, count 0 2006.201.11:09:36.24#ibcon#about to read 5, iclass 4, count 0 2006.201.11:09:36.24#ibcon#read 5, iclass 4, count 0 2006.201.11:09:36.24#ibcon#about to read 6, iclass 4, count 0 2006.201.11:09:36.24#ibcon#read 6, iclass 4, count 0 2006.201.11:09:36.24#ibcon#end of sib2, iclass 4, count 0 2006.201.11:09:36.24#ibcon#*after write, iclass 4, count 0 2006.201.11:09:36.24#ibcon#*before return 0, iclass 4, count 0 2006.201.11:09:36.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:36.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:09:36.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:09:36.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:09:36.24$vck44/vabw=wide 2006.201.11:09:36.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.11:09:36.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.11:09:36.24#ibcon#ireg 8 cls_cnt 0 2006.201.11:09:36.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:36.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:36.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:36.24#ibcon#enter wrdev, iclass 6, count 0 2006.201.11:09:36.24#ibcon#first serial, iclass 6, count 0 2006.201.11:09:36.24#ibcon#enter sib2, iclass 6, count 0 2006.201.11:09:36.24#ibcon#flushed, iclass 6, count 0 2006.201.11:09:36.24#ibcon#about to write, iclass 6, count 0 2006.201.11:09:36.24#ibcon#wrote, iclass 6, count 0 2006.201.11:09:36.24#ibcon#about to read 3, iclass 6, count 0 2006.201.11:09:36.26#ibcon#read 3, iclass 6, count 0 2006.201.11:09:36.26#ibcon#about to read 4, iclass 6, count 0 2006.201.11:09:36.26#ibcon#read 4, iclass 6, count 0 2006.201.11:09:36.26#ibcon#about to read 5, iclass 6, count 0 2006.201.11:09:36.26#ibcon#read 5, iclass 6, count 0 2006.201.11:09:36.26#ibcon#about to read 6, iclass 6, count 0 2006.201.11:09:36.26#ibcon#read 6, iclass 6, count 0 2006.201.11:09:36.26#ibcon#end of sib2, iclass 6, count 0 2006.201.11:09:36.26#ibcon#*mode == 0, iclass 6, count 0 2006.201.11:09:36.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.11:09:36.26#ibcon#[25=BW32\r\n] 2006.201.11:09:36.26#ibcon#*before write, iclass 6, count 0 2006.201.11:09:36.26#ibcon#enter sib2, iclass 6, count 0 2006.201.11:09:36.26#ibcon#flushed, iclass 6, count 0 2006.201.11:09:36.26#ibcon#about to write, iclass 6, count 0 2006.201.11:09:36.26#ibcon#wrote, iclass 6, count 0 2006.201.11:09:36.26#ibcon#about to read 3, iclass 6, count 0 2006.201.11:09:36.29#ibcon#read 3, iclass 6, count 0 2006.201.11:09:36.29#ibcon#about to read 4, iclass 6, count 0 2006.201.11:09:36.29#ibcon#read 4, iclass 6, count 0 2006.201.11:09:36.29#ibcon#about to read 5, iclass 6, count 0 2006.201.11:09:36.29#ibcon#read 5, iclass 6, count 0 2006.201.11:09:36.29#ibcon#about to read 6, iclass 6, count 0 2006.201.11:09:36.29#ibcon#read 6, iclass 6, count 0 2006.201.11:09:36.29#ibcon#end of sib2, iclass 6, count 0 2006.201.11:09:36.29#ibcon#*after write, iclass 6, count 0 2006.201.11:09:36.29#ibcon#*before return 0, iclass 6, count 0 2006.201.11:09:36.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:36.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:09:36.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.11:09:36.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.11:09:36.29$vck44/vbbw=wide 2006.201.11:09:36.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.11:09:36.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.11:09:36.29#ibcon#ireg 8 cls_cnt 0 2006.201.11:09:36.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:09:36.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:09:36.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:09:36.36#ibcon#enter wrdev, iclass 10, count 0 2006.201.11:09:36.36#ibcon#first serial, iclass 10, count 0 2006.201.11:09:36.36#ibcon#enter sib2, iclass 10, count 0 2006.201.11:09:36.36#ibcon#flushed, iclass 10, count 0 2006.201.11:09:36.36#ibcon#about to write, iclass 10, count 0 2006.201.11:09:36.36#ibcon#wrote, iclass 10, count 0 2006.201.11:09:36.36#ibcon#about to read 3, iclass 10, count 0 2006.201.11:09:36.38#ibcon#read 3, iclass 10, count 0 2006.201.11:09:36.38#ibcon#about to read 4, iclass 10, count 0 2006.201.11:09:36.38#ibcon#read 4, iclass 10, count 0 2006.201.11:09:36.38#ibcon#about to read 5, iclass 10, count 0 2006.201.11:09:36.38#ibcon#read 5, iclass 10, count 0 2006.201.11:09:36.38#ibcon#about to read 6, iclass 10, count 0 2006.201.11:09:36.38#ibcon#read 6, iclass 10, count 0 2006.201.11:09:36.38#ibcon#end of sib2, iclass 10, count 0 2006.201.11:09:36.38#ibcon#*mode == 0, iclass 10, count 0 2006.201.11:09:36.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.11:09:36.38#ibcon#[27=BW32\r\n] 2006.201.11:09:36.38#ibcon#*before write, iclass 10, count 0 2006.201.11:09:36.38#ibcon#enter sib2, iclass 10, count 0 2006.201.11:09:36.38#ibcon#flushed, iclass 10, count 0 2006.201.11:09:36.38#ibcon#about to write, iclass 10, count 0 2006.201.11:09:36.38#ibcon#wrote, iclass 10, count 0 2006.201.11:09:36.38#ibcon#about to read 3, iclass 10, count 0 2006.201.11:09:36.41#ibcon#read 3, iclass 10, count 0 2006.201.11:09:36.41#ibcon#about to read 4, iclass 10, count 0 2006.201.11:09:36.41#ibcon#read 4, iclass 10, count 0 2006.201.11:09:36.41#ibcon#about to read 5, iclass 10, count 0 2006.201.11:09:36.41#ibcon#read 5, iclass 10, count 0 2006.201.11:09:36.41#ibcon#about to read 6, iclass 10, count 0 2006.201.11:09:36.41#ibcon#read 6, iclass 10, count 0 2006.201.11:09:36.41#ibcon#end of sib2, iclass 10, count 0 2006.201.11:09:36.41#ibcon#*after write, iclass 10, count 0 2006.201.11:09:36.41#ibcon#*before return 0, iclass 10, count 0 2006.201.11:09:36.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:09:36.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:09:36.41#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.11:09:36.41#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.11:09:36.41$setupk4/ifdk4 2006.201.11:09:36.41$ifdk4/lo= 2006.201.11:09:36.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:09:36.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:09:36.41$ifdk4/patch= 2006.201.11:09:36.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:09:36.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:09:36.41$setupk4/!*+20s 2006.201.11:09:41.41#abcon#<5=/04 1.5 2.8 21.40 991003.9\r\n> 2006.201.11:09:41.43#abcon#{5=INTERFACE CLEAR} 2006.201.11:09:41.49#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:09:50.14#trakl#Source acquired 2006.201.11:09:50.14#flagr#flagr/antenna,acquired 2006.201.11:09:50.89$setupk4/"tpicd 2006.201.11:09:50.89$setupk4/echo=off 2006.201.11:09:50.89$setupk4/xlog=off 2006.201.11:09:50.89:!2006.201.11:10:27 2006.201.11:10:27.00:preob 2006.201.11:10:27.14/onsource/TRACKING 2006.201.11:10:27.14:!2006.201.11:10:37 2006.201.11:10:37.00:"tape 2006.201.11:10:37.00:"st=record 2006.201.11:10:37.00:data_valid=on 2006.201.11:10:37.00:midob 2006.201.11:10:38.14/onsource/TRACKING 2006.201.11:10:38.14/wx/21.40,1003.9,99 2006.201.11:10:38.24/cable/+6.4720E-03 2006.201.11:10:39.33/va/01,08,usb,yes,31,33 2006.201.11:10:39.33/va/02,07,usb,yes,34,34 2006.201.11:10:39.33/va/03,08,usb,yes,30,32 2006.201.11:10:39.33/va/04,07,usb,yes,34,36 2006.201.11:10:39.33/va/05,04,usb,yes,30,31 2006.201.11:10:39.33/va/06,05,usb,yes,30,30 2006.201.11:10:39.33/va/07,05,usb,yes,29,31 2006.201.11:10:39.33/va/08,04,usb,yes,29,35 2006.201.11:10:39.56/valo/01,524.99,yes,locked 2006.201.11:10:39.56/valo/02,534.99,yes,locked 2006.201.11:10:39.56/valo/03,564.99,yes,locked 2006.201.11:10:39.56/valo/04,624.99,yes,locked 2006.201.11:10:39.56/valo/05,734.99,yes,locked 2006.201.11:10:39.56/valo/06,814.99,yes,locked 2006.201.11:10:39.56/valo/07,864.99,yes,locked 2006.201.11:10:39.56/valo/08,884.99,yes,locked 2006.201.11:10:40.65/vb/01,04,usb,yes,36,33 2006.201.11:10:40.65/vb/02,05,usb,yes,34,34 2006.201.11:10:40.65/vb/03,04,usb,yes,35,39 2006.201.11:10:40.65/vb/04,05,usb,yes,35,34 2006.201.11:10:40.65/vb/05,04,usb,yes,31,34 2006.201.11:10:40.65/vb/06,04,usb,yes,36,32 2006.201.11:10:40.65/vb/07,04,usb,yes,36,36 2006.201.11:10:40.65/vb/08,04,usb,yes,33,37 2006.201.11:10:40.88/vblo/01,629.99,yes,locked 2006.201.11:10:40.88/vblo/02,634.99,yes,locked 2006.201.11:10:40.88/vblo/03,649.99,yes,locked 2006.201.11:10:40.88/vblo/04,679.99,yes,locked 2006.201.11:10:40.88/vblo/05,709.99,yes,locked 2006.201.11:10:40.88/vblo/06,719.99,yes,locked 2006.201.11:10:40.88/vblo/07,734.99,yes,locked 2006.201.11:10:40.88/vblo/08,744.99,yes,locked 2006.201.11:10:41.03/vabw/8 2006.201.11:10:41.18/vbbw/8 2006.201.11:10:41.27/xfe/off,on,15.5 2006.201.11:10:41.65/ifatt/23,28,28,28 2006.201.11:10:42.05/fmout-gps/S +4.60E-07 2006.201.11:10:42.12:!2006.201.11:12:17 2006.201.11:12:17.00:data_valid=off 2006.201.11:12:17.00:"et 2006.201.11:12:17.00:!+3s 2006.201.11:12:20.02:"tape 2006.201.11:12:20.02:postob 2006.201.11:12:20.15/cable/+6.4716E-03 2006.201.11:12:20.15/wx/21.40,1004.0,99 2006.201.11:12:20.22/fmout-gps/S +4.60E-07 2006.201.11:12:20.22:scan_name=201-1120,jd0607,80 2006.201.11:12:20.22:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.201.11:12:22.14#flagr#flagr/antenna,new-source 2006.201.11:12:22.14:checkk5 2006.201.11:12:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:12:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:12:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:12:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:12:24.00/chk_obsdata//k5ts1/T2011110??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.11:12:24.37/chk_obsdata//k5ts2/T2011110??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.11:12:24.73/chk_obsdata//k5ts3/T2011110??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.11:12:25.10/chk_obsdata//k5ts4/T2011110??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.11:12:25.78/k5log//k5ts1_log_newline 2006.201.11:12:26.47/k5log//k5ts2_log_newline 2006.201.11:12:27.16/k5log//k5ts3_log_newline 2006.201.11:12:27.84/k5log//k5ts4_log_newline 2006.201.11:12:27.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:12:27.87:setupk4=1 2006.201.11:12:27.87$setupk4/echo=on 2006.201.11:12:27.87$setupk4/pcalon 2006.201.11:12:27.87$pcalon/"no phase cal control is implemented here 2006.201.11:12:27.87$setupk4/"tpicd=stop 2006.201.11:12:27.87$setupk4/"rec=synch_on 2006.201.11:12:27.87$setupk4/"rec_mode=128 2006.201.11:12:27.87$setupk4/!* 2006.201.11:12:27.87$setupk4/recpk4 2006.201.11:12:27.87$recpk4/recpatch= 2006.201.11:12:27.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:12:27.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:12:27.87$setupk4/vck44 2006.201.11:12:27.87$vck44/valo=1,524.99 2006.201.11:12:27.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.11:12:27.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.11:12:27.87#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:27.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:27.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:27.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:27.87#ibcon#enter wrdev, iclass 11, count 0 2006.201.11:12:27.87#ibcon#first serial, iclass 11, count 0 2006.201.11:12:27.87#ibcon#enter sib2, iclass 11, count 0 2006.201.11:12:27.87#ibcon#flushed, iclass 11, count 0 2006.201.11:12:27.87#ibcon#about to write, iclass 11, count 0 2006.201.11:12:27.87#ibcon#wrote, iclass 11, count 0 2006.201.11:12:27.87#ibcon#about to read 3, iclass 11, count 0 2006.201.11:12:27.91#ibcon#read 3, iclass 11, count 0 2006.201.11:12:27.91#ibcon#about to read 4, iclass 11, count 0 2006.201.11:12:27.91#ibcon#read 4, iclass 11, count 0 2006.201.11:12:27.91#ibcon#about to read 5, iclass 11, count 0 2006.201.11:12:27.91#ibcon#read 5, iclass 11, count 0 2006.201.11:12:27.91#ibcon#about to read 6, iclass 11, count 0 2006.201.11:12:27.91#ibcon#read 6, iclass 11, count 0 2006.201.11:12:27.91#ibcon#end of sib2, iclass 11, count 0 2006.201.11:12:27.91#ibcon#*mode == 0, iclass 11, count 0 2006.201.11:12:27.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.11:12:27.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:12:27.91#ibcon#*before write, iclass 11, count 0 2006.201.11:12:27.91#ibcon#enter sib2, iclass 11, count 0 2006.201.11:12:27.91#ibcon#flushed, iclass 11, count 0 2006.201.11:12:27.91#ibcon#about to write, iclass 11, count 0 2006.201.11:12:27.91#ibcon#wrote, iclass 11, count 0 2006.201.11:12:27.91#ibcon#about to read 3, iclass 11, count 0 2006.201.11:12:27.96#ibcon#read 3, iclass 11, count 0 2006.201.11:12:27.96#ibcon#about to read 4, iclass 11, count 0 2006.201.11:12:27.96#ibcon#read 4, iclass 11, count 0 2006.201.11:12:27.96#ibcon#about to read 5, iclass 11, count 0 2006.201.11:12:27.96#ibcon#read 5, iclass 11, count 0 2006.201.11:12:27.96#ibcon#about to read 6, iclass 11, count 0 2006.201.11:12:27.96#ibcon#read 6, iclass 11, count 0 2006.201.11:12:27.96#ibcon#end of sib2, iclass 11, count 0 2006.201.11:12:27.96#ibcon#*after write, iclass 11, count 0 2006.201.11:12:27.96#ibcon#*before return 0, iclass 11, count 0 2006.201.11:12:27.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:27.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:27.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.11:12:27.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.11:12:27.96$vck44/va=1,8 2006.201.11:12:27.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.11:12:27.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.11:12:27.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:27.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:27.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:27.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:27.96#ibcon#enter wrdev, iclass 13, count 2 2006.201.11:12:27.96#ibcon#first serial, iclass 13, count 2 2006.201.11:12:27.96#ibcon#enter sib2, iclass 13, count 2 2006.201.11:12:27.96#ibcon#flushed, iclass 13, count 2 2006.201.11:12:27.96#ibcon#about to write, iclass 13, count 2 2006.201.11:12:27.96#ibcon#wrote, iclass 13, count 2 2006.201.11:12:27.96#ibcon#about to read 3, iclass 13, count 2 2006.201.11:12:27.98#ibcon#read 3, iclass 13, count 2 2006.201.11:12:27.98#ibcon#about to read 4, iclass 13, count 2 2006.201.11:12:27.98#ibcon#read 4, iclass 13, count 2 2006.201.11:12:27.98#ibcon#about to read 5, iclass 13, count 2 2006.201.11:12:27.98#ibcon#read 5, iclass 13, count 2 2006.201.11:12:27.98#ibcon#about to read 6, iclass 13, count 2 2006.201.11:12:27.98#ibcon#read 6, iclass 13, count 2 2006.201.11:12:27.98#ibcon#end of sib2, iclass 13, count 2 2006.201.11:12:27.98#ibcon#*mode == 0, iclass 13, count 2 2006.201.11:12:27.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.11:12:27.98#ibcon#[25=AT01-08\r\n] 2006.201.11:12:27.98#ibcon#*before write, iclass 13, count 2 2006.201.11:12:27.98#ibcon#enter sib2, iclass 13, count 2 2006.201.11:12:27.98#ibcon#flushed, iclass 13, count 2 2006.201.11:12:27.98#ibcon#about to write, iclass 13, count 2 2006.201.11:12:27.98#ibcon#wrote, iclass 13, count 2 2006.201.11:12:27.98#ibcon#about to read 3, iclass 13, count 2 2006.201.11:12:28.01#ibcon#read 3, iclass 13, count 2 2006.201.11:12:28.01#ibcon#about to read 4, iclass 13, count 2 2006.201.11:12:28.01#ibcon#read 4, iclass 13, count 2 2006.201.11:12:28.01#ibcon#about to read 5, iclass 13, count 2 2006.201.11:12:28.01#ibcon#read 5, iclass 13, count 2 2006.201.11:12:28.01#ibcon#about to read 6, iclass 13, count 2 2006.201.11:12:28.01#ibcon#read 6, iclass 13, count 2 2006.201.11:12:28.01#ibcon#end of sib2, iclass 13, count 2 2006.201.11:12:28.01#ibcon#*after write, iclass 13, count 2 2006.201.11:12:28.01#ibcon#*before return 0, iclass 13, count 2 2006.201.11:12:28.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:28.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:28.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.11:12:28.01#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:28.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:28.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:28.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:28.13#ibcon#enter wrdev, iclass 13, count 0 2006.201.11:12:28.13#ibcon#first serial, iclass 13, count 0 2006.201.11:12:28.13#ibcon#enter sib2, iclass 13, count 0 2006.201.11:12:28.13#ibcon#flushed, iclass 13, count 0 2006.201.11:12:28.13#ibcon#about to write, iclass 13, count 0 2006.201.11:12:28.13#ibcon#wrote, iclass 13, count 0 2006.201.11:12:28.13#ibcon#about to read 3, iclass 13, count 0 2006.201.11:12:28.15#ibcon#read 3, iclass 13, count 0 2006.201.11:12:28.15#ibcon#about to read 4, iclass 13, count 0 2006.201.11:12:28.15#ibcon#read 4, iclass 13, count 0 2006.201.11:12:28.15#ibcon#about to read 5, iclass 13, count 0 2006.201.11:12:28.15#ibcon#read 5, iclass 13, count 0 2006.201.11:12:28.15#ibcon#about to read 6, iclass 13, count 0 2006.201.11:12:28.15#ibcon#read 6, iclass 13, count 0 2006.201.11:12:28.15#ibcon#end of sib2, iclass 13, count 0 2006.201.11:12:28.15#ibcon#*mode == 0, iclass 13, count 0 2006.201.11:12:28.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.11:12:28.15#ibcon#[25=USB\r\n] 2006.201.11:12:28.15#ibcon#*before write, iclass 13, count 0 2006.201.11:12:28.15#ibcon#enter sib2, iclass 13, count 0 2006.201.11:12:28.15#ibcon#flushed, iclass 13, count 0 2006.201.11:12:28.15#ibcon#about to write, iclass 13, count 0 2006.201.11:12:28.15#ibcon#wrote, iclass 13, count 0 2006.201.11:12:28.15#ibcon#about to read 3, iclass 13, count 0 2006.201.11:12:28.18#ibcon#read 3, iclass 13, count 0 2006.201.11:12:28.18#ibcon#about to read 4, iclass 13, count 0 2006.201.11:12:28.18#ibcon#read 4, iclass 13, count 0 2006.201.11:12:28.18#ibcon#about to read 5, iclass 13, count 0 2006.201.11:12:28.18#ibcon#read 5, iclass 13, count 0 2006.201.11:12:28.18#ibcon#about to read 6, iclass 13, count 0 2006.201.11:12:28.18#ibcon#read 6, iclass 13, count 0 2006.201.11:12:28.18#ibcon#end of sib2, iclass 13, count 0 2006.201.11:12:28.18#ibcon#*after write, iclass 13, count 0 2006.201.11:12:28.18#ibcon#*before return 0, iclass 13, count 0 2006.201.11:12:28.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:28.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:28.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.11:12:28.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.11:12:28.18$vck44/valo=2,534.99 2006.201.11:12:28.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.11:12:28.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.11:12:28.18#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:28.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:28.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:28.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:28.18#ibcon#enter wrdev, iclass 15, count 0 2006.201.11:12:28.18#ibcon#first serial, iclass 15, count 0 2006.201.11:12:28.18#ibcon#enter sib2, iclass 15, count 0 2006.201.11:12:28.18#ibcon#flushed, iclass 15, count 0 2006.201.11:12:28.18#ibcon#about to write, iclass 15, count 0 2006.201.11:12:28.18#ibcon#wrote, iclass 15, count 0 2006.201.11:12:28.18#ibcon#about to read 3, iclass 15, count 0 2006.201.11:12:28.20#ibcon#read 3, iclass 15, count 0 2006.201.11:12:28.20#ibcon#about to read 4, iclass 15, count 0 2006.201.11:12:28.20#ibcon#read 4, iclass 15, count 0 2006.201.11:12:28.20#ibcon#about to read 5, iclass 15, count 0 2006.201.11:12:28.20#ibcon#read 5, iclass 15, count 0 2006.201.11:12:28.20#ibcon#about to read 6, iclass 15, count 0 2006.201.11:12:28.20#ibcon#read 6, iclass 15, count 0 2006.201.11:12:28.20#ibcon#end of sib2, iclass 15, count 0 2006.201.11:12:28.20#ibcon#*mode == 0, iclass 15, count 0 2006.201.11:12:28.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.11:12:28.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:12:28.20#ibcon#*before write, iclass 15, count 0 2006.201.11:12:28.20#ibcon#enter sib2, iclass 15, count 0 2006.201.11:12:28.20#ibcon#flushed, iclass 15, count 0 2006.201.11:12:28.20#ibcon#about to write, iclass 15, count 0 2006.201.11:12:28.20#ibcon#wrote, iclass 15, count 0 2006.201.11:12:28.20#ibcon#about to read 3, iclass 15, count 0 2006.201.11:12:28.25#ibcon#read 3, iclass 15, count 0 2006.201.11:12:28.25#ibcon#about to read 4, iclass 15, count 0 2006.201.11:12:28.25#ibcon#read 4, iclass 15, count 0 2006.201.11:12:28.25#ibcon#about to read 5, iclass 15, count 0 2006.201.11:12:28.25#ibcon#read 5, iclass 15, count 0 2006.201.11:12:28.25#ibcon#about to read 6, iclass 15, count 0 2006.201.11:12:28.25#ibcon#read 6, iclass 15, count 0 2006.201.11:12:28.25#ibcon#end of sib2, iclass 15, count 0 2006.201.11:12:28.25#ibcon#*after write, iclass 15, count 0 2006.201.11:12:28.25#ibcon#*before return 0, iclass 15, count 0 2006.201.11:12:28.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:28.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:28.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.11:12:28.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.11:12:28.25$vck44/va=2,7 2006.201.11:12:28.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.11:12:28.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.11:12:28.25#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:28.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:28.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:28.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:28.30#ibcon#enter wrdev, iclass 17, count 2 2006.201.11:12:28.30#ibcon#first serial, iclass 17, count 2 2006.201.11:12:28.30#ibcon#enter sib2, iclass 17, count 2 2006.201.11:12:28.30#ibcon#flushed, iclass 17, count 2 2006.201.11:12:28.30#ibcon#about to write, iclass 17, count 2 2006.201.11:12:28.30#ibcon#wrote, iclass 17, count 2 2006.201.11:12:28.30#ibcon#about to read 3, iclass 17, count 2 2006.201.11:12:28.32#ibcon#read 3, iclass 17, count 2 2006.201.11:12:28.32#ibcon#about to read 4, iclass 17, count 2 2006.201.11:12:28.32#ibcon#read 4, iclass 17, count 2 2006.201.11:12:28.32#ibcon#about to read 5, iclass 17, count 2 2006.201.11:12:28.32#ibcon#read 5, iclass 17, count 2 2006.201.11:12:28.32#ibcon#about to read 6, iclass 17, count 2 2006.201.11:12:28.32#ibcon#read 6, iclass 17, count 2 2006.201.11:12:28.32#ibcon#end of sib2, iclass 17, count 2 2006.201.11:12:28.32#ibcon#*mode == 0, iclass 17, count 2 2006.201.11:12:28.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.11:12:28.32#ibcon#[25=AT02-07\r\n] 2006.201.11:12:28.32#ibcon#*before write, iclass 17, count 2 2006.201.11:12:28.32#ibcon#enter sib2, iclass 17, count 2 2006.201.11:12:28.32#ibcon#flushed, iclass 17, count 2 2006.201.11:12:28.32#ibcon#about to write, iclass 17, count 2 2006.201.11:12:28.32#ibcon#wrote, iclass 17, count 2 2006.201.11:12:28.32#ibcon#about to read 3, iclass 17, count 2 2006.201.11:12:28.35#ibcon#read 3, iclass 17, count 2 2006.201.11:12:28.35#ibcon#about to read 4, iclass 17, count 2 2006.201.11:12:28.35#ibcon#read 4, iclass 17, count 2 2006.201.11:12:28.35#ibcon#about to read 5, iclass 17, count 2 2006.201.11:12:28.35#ibcon#read 5, iclass 17, count 2 2006.201.11:12:28.35#ibcon#about to read 6, iclass 17, count 2 2006.201.11:12:28.35#ibcon#read 6, iclass 17, count 2 2006.201.11:12:28.35#ibcon#end of sib2, iclass 17, count 2 2006.201.11:12:28.35#ibcon#*after write, iclass 17, count 2 2006.201.11:12:28.35#ibcon#*before return 0, iclass 17, count 2 2006.201.11:12:28.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:28.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:28.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.11:12:28.35#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:28.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:28.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:28.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:28.47#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:12:28.47#ibcon#first serial, iclass 17, count 0 2006.201.11:12:28.47#ibcon#enter sib2, iclass 17, count 0 2006.201.11:12:28.47#ibcon#flushed, iclass 17, count 0 2006.201.11:12:28.47#ibcon#about to write, iclass 17, count 0 2006.201.11:12:28.47#ibcon#wrote, iclass 17, count 0 2006.201.11:12:28.47#ibcon#about to read 3, iclass 17, count 0 2006.201.11:12:28.49#ibcon#read 3, iclass 17, count 0 2006.201.11:12:28.49#ibcon#about to read 4, iclass 17, count 0 2006.201.11:12:28.49#ibcon#read 4, iclass 17, count 0 2006.201.11:12:28.49#ibcon#about to read 5, iclass 17, count 0 2006.201.11:12:28.49#ibcon#read 5, iclass 17, count 0 2006.201.11:12:28.49#ibcon#about to read 6, iclass 17, count 0 2006.201.11:12:28.49#ibcon#read 6, iclass 17, count 0 2006.201.11:12:28.49#ibcon#end of sib2, iclass 17, count 0 2006.201.11:12:28.49#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:12:28.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:12:28.49#ibcon#[25=USB\r\n] 2006.201.11:12:28.49#ibcon#*before write, iclass 17, count 0 2006.201.11:12:28.49#ibcon#enter sib2, iclass 17, count 0 2006.201.11:12:28.49#ibcon#flushed, iclass 17, count 0 2006.201.11:12:28.49#ibcon#about to write, iclass 17, count 0 2006.201.11:12:28.49#ibcon#wrote, iclass 17, count 0 2006.201.11:12:28.49#ibcon#about to read 3, iclass 17, count 0 2006.201.11:12:28.52#ibcon#read 3, iclass 17, count 0 2006.201.11:12:28.52#ibcon#about to read 4, iclass 17, count 0 2006.201.11:12:28.52#ibcon#read 4, iclass 17, count 0 2006.201.11:12:28.52#ibcon#about to read 5, iclass 17, count 0 2006.201.11:12:28.52#ibcon#read 5, iclass 17, count 0 2006.201.11:12:28.52#ibcon#about to read 6, iclass 17, count 0 2006.201.11:12:28.52#ibcon#read 6, iclass 17, count 0 2006.201.11:12:28.52#ibcon#end of sib2, iclass 17, count 0 2006.201.11:12:28.52#ibcon#*after write, iclass 17, count 0 2006.201.11:12:28.52#ibcon#*before return 0, iclass 17, count 0 2006.201.11:12:28.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:28.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:28.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:12:28.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:12:28.52$vck44/valo=3,564.99 2006.201.11:12:28.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.11:12:28.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.11:12:28.52#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:28.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:28.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:28.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:28.52#ibcon#enter wrdev, iclass 19, count 0 2006.201.11:12:28.52#ibcon#first serial, iclass 19, count 0 2006.201.11:12:28.52#ibcon#enter sib2, iclass 19, count 0 2006.201.11:12:28.52#ibcon#flushed, iclass 19, count 0 2006.201.11:12:28.52#ibcon#about to write, iclass 19, count 0 2006.201.11:12:28.52#ibcon#wrote, iclass 19, count 0 2006.201.11:12:28.52#ibcon#about to read 3, iclass 19, count 0 2006.201.11:12:28.54#ibcon#read 3, iclass 19, count 0 2006.201.11:12:28.54#ibcon#about to read 4, iclass 19, count 0 2006.201.11:12:28.54#ibcon#read 4, iclass 19, count 0 2006.201.11:12:28.54#ibcon#about to read 5, iclass 19, count 0 2006.201.11:12:28.54#ibcon#read 5, iclass 19, count 0 2006.201.11:12:28.54#ibcon#about to read 6, iclass 19, count 0 2006.201.11:12:28.54#ibcon#read 6, iclass 19, count 0 2006.201.11:12:28.54#ibcon#end of sib2, iclass 19, count 0 2006.201.11:12:28.54#ibcon#*mode == 0, iclass 19, count 0 2006.201.11:12:28.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.11:12:28.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:12:28.54#ibcon#*before write, iclass 19, count 0 2006.201.11:12:28.54#ibcon#enter sib2, iclass 19, count 0 2006.201.11:12:28.54#ibcon#flushed, iclass 19, count 0 2006.201.11:12:28.54#ibcon#about to write, iclass 19, count 0 2006.201.11:12:28.54#ibcon#wrote, iclass 19, count 0 2006.201.11:12:28.54#ibcon#about to read 3, iclass 19, count 0 2006.201.11:12:28.59#ibcon#read 3, iclass 19, count 0 2006.201.11:12:28.59#ibcon#about to read 4, iclass 19, count 0 2006.201.11:12:28.59#ibcon#read 4, iclass 19, count 0 2006.201.11:12:28.59#ibcon#about to read 5, iclass 19, count 0 2006.201.11:12:28.59#ibcon#read 5, iclass 19, count 0 2006.201.11:12:28.59#ibcon#about to read 6, iclass 19, count 0 2006.201.11:12:28.59#ibcon#read 6, iclass 19, count 0 2006.201.11:12:28.59#ibcon#end of sib2, iclass 19, count 0 2006.201.11:12:28.59#ibcon#*after write, iclass 19, count 0 2006.201.11:12:28.59#ibcon#*before return 0, iclass 19, count 0 2006.201.11:12:28.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:28.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:28.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.11:12:28.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.11:12:28.59$vck44/va=3,8 2006.201.11:12:28.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.11:12:28.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.11:12:28.59#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:28.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:28.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:28.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:28.64#ibcon#enter wrdev, iclass 21, count 2 2006.201.11:12:28.64#ibcon#first serial, iclass 21, count 2 2006.201.11:12:28.64#ibcon#enter sib2, iclass 21, count 2 2006.201.11:12:28.64#ibcon#flushed, iclass 21, count 2 2006.201.11:12:28.64#ibcon#about to write, iclass 21, count 2 2006.201.11:12:28.64#ibcon#wrote, iclass 21, count 2 2006.201.11:12:28.64#ibcon#about to read 3, iclass 21, count 2 2006.201.11:12:28.66#ibcon#read 3, iclass 21, count 2 2006.201.11:12:28.66#ibcon#about to read 4, iclass 21, count 2 2006.201.11:12:28.66#ibcon#read 4, iclass 21, count 2 2006.201.11:12:28.66#ibcon#about to read 5, iclass 21, count 2 2006.201.11:12:28.66#ibcon#read 5, iclass 21, count 2 2006.201.11:12:28.66#ibcon#about to read 6, iclass 21, count 2 2006.201.11:12:28.66#ibcon#read 6, iclass 21, count 2 2006.201.11:12:28.66#ibcon#end of sib2, iclass 21, count 2 2006.201.11:12:28.66#ibcon#*mode == 0, iclass 21, count 2 2006.201.11:12:28.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.11:12:28.66#ibcon#[25=AT03-08\r\n] 2006.201.11:12:28.66#ibcon#*before write, iclass 21, count 2 2006.201.11:12:28.66#ibcon#enter sib2, iclass 21, count 2 2006.201.11:12:28.66#ibcon#flushed, iclass 21, count 2 2006.201.11:12:28.66#ibcon#about to write, iclass 21, count 2 2006.201.11:12:28.66#ibcon#wrote, iclass 21, count 2 2006.201.11:12:28.66#ibcon#about to read 3, iclass 21, count 2 2006.201.11:12:28.69#ibcon#read 3, iclass 21, count 2 2006.201.11:12:28.69#ibcon#about to read 4, iclass 21, count 2 2006.201.11:12:28.69#ibcon#read 4, iclass 21, count 2 2006.201.11:12:28.69#ibcon#about to read 5, iclass 21, count 2 2006.201.11:12:28.69#ibcon#read 5, iclass 21, count 2 2006.201.11:12:28.69#ibcon#about to read 6, iclass 21, count 2 2006.201.11:12:28.69#ibcon#read 6, iclass 21, count 2 2006.201.11:12:28.69#ibcon#end of sib2, iclass 21, count 2 2006.201.11:12:28.69#ibcon#*after write, iclass 21, count 2 2006.201.11:12:28.69#ibcon#*before return 0, iclass 21, count 2 2006.201.11:12:28.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:28.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:28.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.11:12:28.69#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:28.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:28.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:28.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:28.81#ibcon#enter wrdev, iclass 21, count 0 2006.201.11:12:28.81#ibcon#first serial, iclass 21, count 0 2006.201.11:12:28.81#ibcon#enter sib2, iclass 21, count 0 2006.201.11:12:28.81#ibcon#flushed, iclass 21, count 0 2006.201.11:12:28.81#ibcon#about to write, iclass 21, count 0 2006.201.11:12:28.81#ibcon#wrote, iclass 21, count 0 2006.201.11:12:28.81#ibcon#about to read 3, iclass 21, count 0 2006.201.11:12:28.83#ibcon#read 3, iclass 21, count 0 2006.201.11:12:28.83#ibcon#about to read 4, iclass 21, count 0 2006.201.11:12:28.83#ibcon#read 4, iclass 21, count 0 2006.201.11:12:28.83#ibcon#about to read 5, iclass 21, count 0 2006.201.11:12:28.83#ibcon#read 5, iclass 21, count 0 2006.201.11:12:28.83#ibcon#about to read 6, iclass 21, count 0 2006.201.11:12:28.83#ibcon#read 6, iclass 21, count 0 2006.201.11:12:28.83#ibcon#end of sib2, iclass 21, count 0 2006.201.11:12:28.83#ibcon#*mode == 0, iclass 21, count 0 2006.201.11:12:28.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.11:12:28.83#ibcon#[25=USB\r\n] 2006.201.11:12:28.83#ibcon#*before write, iclass 21, count 0 2006.201.11:12:28.83#ibcon#enter sib2, iclass 21, count 0 2006.201.11:12:28.83#ibcon#flushed, iclass 21, count 0 2006.201.11:12:28.83#ibcon#about to write, iclass 21, count 0 2006.201.11:12:28.83#ibcon#wrote, iclass 21, count 0 2006.201.11:12:28.83#ibcon#about to read 3, iclass 21, count 0 2006.201.11:12:28.86#ibcon#read 3, iclass 21, count 0 2006.201.11:12:28.86#ibcon#about to read 4, iclass 21, count 0 2006.201.11:12:28.86#ibcon#read 4, iclass 21, count 0 2006.201.11:12:28.86#ibcon#about to read 5, iclass 21, count 0 2006.201.11:12:28.86#ibcon#read 5, iclass 21, count 0 2006.201.11:12:28.86#ibcon#about to read 6, iclass 21, count 0 2006.201.11:12:28.86#ibcon#read 6, iclass 21, count 0 2006.201.11:12:28.86#ibcon#end of sib2, iclass 21, count 0 2006.201.11:12:28.86#ibcon#*after write, iclass 21, count 0 2006.201.11:12:28.86#ibcon#*before return 0, iclass 21, count 0 2006.201.11:12:28.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:28.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:28.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.11:12:28.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.11:12:28.86$vck44/valo=4,624.99 2006.201.11:12:28.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.11:12:28.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.11:12:28.86#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:28.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:28.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:28.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:28.86#ibcon#enter wrdev, iclass 23, count 0 2006.201.11:12:28.86#ibcon#first serial, iclass 23, count 0 2006.201.11:12:28.86#ibcon#enter sib2, iclass 23, count 0 2006.201.11:12:28.86#ibcon#flushed, iclass 23, count 0 2006.201.11:12:28.86#ibcon#about to write, iclass 23, count 0 2006.201.11:12:28.86#ibcon#wrote, iclass 23, count 0 2006.201.11:12:28.86#ibcon#about to read 3, iclass 23, count 0 2006.201.11:12:28.88#ibcon#read 3, iclass 23, count 0 2006.201.11:12:28.88#ibcon#about to read 4, iclass 23, count 0 2006.201.11:12:28.88#ibcon#read 4, iclass 23, count 0 2006.201.11:12:28.88#ibcon#about to read 5, iclass 23, count 0 2006.201.11:12:28.88#ibcon#read 5, iclass 23, count 0 2006.201.11:12:28.88#ibcon#about to read 6, iclass 23, count 0 2006.201.11:12:28.88#ibcon#read 6, iclass 23, count 0 2006.201.11:12:28.88#ibcon#end of sib2, iclass 23, count 0 2006.201.11:12:28.88#ibcon#*mode == 0, iclass 23, count 0 2006.201.11:12:28.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.11:12:28.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:12:28.88#ibcon#*before write, iclass 23, count 0 2006.201.11:12:28.88#ibcon#enter sib2, iclass 23, count 0 2006.201.11:12:28.88#ibcon#flushed, iclass 23, count 0 2006.201.11:12:28.88#ibcon#about to write, iclass 23, count 0 2006.201.11:12:28.88#ibcon#wrote, iclass 23, count 0 2006.201.11:12:28.88#ibcon#about to read 3, iclass 23, count 0 2006.201.11:12:28.93#ibcon#read 3, iclass 23, count 0 2006.201.11:12:28.93#ibcon#about to read 4, iclass 23, count 0 2006.201.11:12:28.93#ibcon#read 4, iclass 23, count 0 2006.201.11:12:28.93#ibcon#about to read 5, iclass 23, count 0 2006.201.11:12:28.93#ibcon#read 5, iclass 23, count 0 2006.201.11:12:28.93#ibcon#about to read 6, iclass 23, count 0 2006.201.11:12:28.93#ibcon#read 6, iclass 23, count 0 2006.201.11:12:28.93#ibcon#end of sib2, iclass 23, count 0 2006.201.11:12:28.93#ibcon#*after write, iclass 23, count 0 2006.201.11:12:28.93#ibcon#*before return 0, iclass 23, count 0 2006.201.11:12:28.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:28.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:28.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.11:12:28.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.11:12:28.93$vck44/va=4,7 2006.201.11:12:28.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.11:12:28.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.11:12:28.93#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:28.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:28.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:28.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:28.98#ibcon#enter wrdev, iclass 25, count 2 2006.201.11:12:28.98#ibcon#first serial, iclass 25, count 2 2006.201.11:12:28.98#ibcon#enter sib2, iclass 25, count 2 2006.201.11:12:28.98#ibcon#flushed, iclass 25, count 2 2006.201.11:12:28.98#ibcon#about to write, iclass 25, count 2 2006.201.11:12:28.98#ibcon#wrote, iclass 25, count 2 2006.201.11:12:28.98#ibcon#about to read 3, iclass 25, count 2 2006.201.11:12:29.00#ibcon#read 3, iclass 25, count 2 2006.201.11:12:29.00#ibcon#about to read 4, iclass 25, count 2 2006.201.11:12:29.00#ibcon#read 4, iclass 25, count 2 2006.201.11:12:29.00#ibcon#about to read 5, iclass 25, count 2 2006.201.11:12:29.00#ibcon#read 5, iclass 25, count 2 2006.201.11:12:29.00#ibcon#about to read 6, iclass 25, count 2 2006.201.11:12:29.00#ibcon#read 6, iclass 25, count 2 2006.201.11:12:29.00#ibcon#end of sib2, iclass 25, count 2 2006.201.11:12:29.00#ibcon#*mode == 0, iclass 25, count 2 2006.201.11:12:29.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.11:12:29.00#ibcon#[25=AT04-07\r\n] 2006.201.11:12:29.00#ibcon#*before write, iclass 25, count 2 2006.201.11:12:29.00#ibcon#enter sib2, iclass 25, count 2 2006.201.11:12:29.00#ibcon#flushed, iclass 25, count 2 2006.201.11:12:29.00#ibcon#about to write, iclass 25, count 2 2006.201.11:12:29.00#ibcon#wrote, iclass 25, count 2 2006.201.11:12:29.00#ibcon#about to read 3, iclass 25, count 2 2006.201.11:12:29.03#ibcon#read 3, iclass 25, count 2 2006.201.11:12:29.03#ibcon#about to read 4, iclass 25, count 2 2006.201.11:12:29.03#ibcon#read 4, iclass 25, count 2 2006.201.11:12:29.03#ibcon#about to read 5, iclass 25, count 2 2006.201.11:12:29.03#ibcon#read 5, iclass 25, count 2 2006.201.11:12:29.03#ibcon#about to read 6, iclass 25, count 2 2006.201.11:12:29.03#ibcon#read 6, iclass 25, count 2 2006.201.11:12:29.03#ibcon#end of sib2, iclass 25, count 2 2006.201.11:12:29.03#ibcon#*after write, iclass 25, count 2 2006.201.11:12:29.03#ibcon#*before return 0, iclass 25, count 2 2006.201.11:12:29.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:29.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:29.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.11:12:29.03#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:29.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:29.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:29.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:29.15#ibcon#enter wrdev, iclass 25, count 0 2006.201.11:12:29.15#ibcon#first serial, iclass 25, count 0 2006.201.11:12:29.15#ibcon#enter sib2, iclass 25, count 0 2006.201.11:12:29.15#ibcon#flushed, iclass 25, count 0 2006.201.11:12:29.15#ibcon#about to write, iclass 25, count 0 2006.201.11:12:29.15#ibcon#wrote, iclass 25, count 0 2006.201.11:12:29.15#ibcon#about to read 3, iclass 25, count 0 2006.201.11:12:29.17#ibcon#read 3, iclass 25, count 0 2006.201.11:12:29.17#ibcon#about to read 4, iclass 25, count 0 2006.201.11:12:29.17#ibcon#read 4, iclass 25, count 0 2006.201.11:12:29.17#ibcon#about to read 5, iclass 25, count 0 2006.201.11:12:29.17#ibcon#read 5, iclass 25, count 0 2006.201.11:12:29.17#ibcon#about to read 6, iclass 25, count 0 2006.201.11:12:29.17#ibcon#read 6, iclass 25, count 0 2006.201.11:12:29.17#ibcon#end of sib2, iclass 25, count 0 2006.201.11:12:29.17#ibcon#*mode == 0, iclass 25, count 0 2006.201.11:12:29.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.11:12:29.17#ibcon#[25=USB\r\n] 2006.201.11:12:29.17#ibcon#*before write, iclass 25, count 0 2006.201.11:12:29.17#ibcon#enter sib2, iclass 25, count 0 2006.201.11:12:29.17#ibcon#flushed, iclass 25, count 0 2006.201.11:12:29.17#ibcon#about to write, iclass 25, count 0 2006.201.11:12:29.17#ibcon#wrote, iclass 25, count 0 2006.201.11:12:29.17#ibcon#about to read 3, iclass 25, count 0 2006.201.11:12:29.20#ibcon#read 3, iclass 25, count 0 2006.201.11:12:29.20#ibcon#about to read 4, iclass 25, count 0 2006.201.11:12:29.20#ibcon#read 4, iclass 25, count 0 2006.201.11:12:29.20#ibcon#about to read 5, iclass 25, count 0 2006.201.11:12:29.20#ibcon#read 5, iclass 25, count 0 2006.201.11:12:29.20#ibcon#about to read 6, iclass 25, count 0 2006.201.11:12:29.20#ibcon#read 6, iclass 25, count 0 2006.201.11:12:29.20#ibcon#end of sib2, iclass 25, count 0 2006.201.11:12:29.20#ibcon#*after write, iclass 25, count 0 2006.201.11:12:29.20#ibcon#*before return 0, iclass 25, count 0 2006.201.11:12:29.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:29.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:29.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.11:12:29.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.11:12:29.20$vck44/valo=5,734.99 2006.201.11:12:29.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.11:12:29.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.11:12:29.20#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:29.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:29.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:29.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:29.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.11:12:29.20#ibcon#first serial, iclass 27, count 0 2006.201.11:12:29.20#ibcon#enter sib2, iclass 27, count 0 2006.201.11:12:29.20#ibcon#flushed, iclass 27, count 0 2006.201.11:12:29.20#ibcon#about to write, iclass 27, count 0 2006.201.11:12:29.20#ibcon#wrote, iclass 27, count 0 2006.201.11:12:29.20#ibcon#about to read 3, iclass 27, count 0 2006.201.11:12:29.22#ibcon#read 3, iclass 27, count 0 2006.201.11:12:29.22#ibcon#about to read 4, iclass 27, count 0 2006.201.11:12:29.22#ibcon#read 4, iclass 27, count 0 2006.201.11:12:29.22#ibcon#about to read 5, iclass 27, count 0 2006.201.11:12:29.22#ibcon#read 5, iclass 27, count 0 2006.201.11:12:29.22#ibcon#about to read 6, iclass 27, count 0 2006.201.11:12:29.22#ibcon#read 6, iclass 27, count 0 2006.201.11:12:29.22#ibcon#end of sib2, iclass 27, count 0 2006.201.11:12:29.22#ibcon#*mode == 0, iclass 27, count 0 2006.201.11:12:29.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.11:12:29.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:12:29.22#ibcon#*before write, iclass 27, count 0 2006.201.11:12:29.22#ibcon#enter sib2, iclass 27, count 0 2006.201.11:12:29.22#ibcon#flushed, iclass 27, count 0 2006.201.11:12:29.22#ibcon#about to write, iclass 27, count 0 2006.201.11:12:29.22#ibcon#wrote, iclass 27, count 0 2006.201.11:12:29.22#ibcon#about to read 3, iclass 27, count 0 2006.201.11:12:29.26#ibcon#read 3, iclass 27, count 0 2006.201.11:12:29.26#ibcon#about to read 4, iclass 27, count 0 2006.201.11:12:29.26#ibcon#read 4, iclass 27, count 0 2006.201.11:12:29.26#ibcon#about to read 5, iclass 27, count 0 2006.201.11:12:29.26#ibcon#read 5, iclass 27, count 0 2006.201.11:12:29.26#ibcon#about to read 6, iclass 27, count 0 2006.201.11:12:29.26#ibcon#read 6, iclass 27, count 0 2006.201.11:12:29.26#ibcon#end of sib2, iclass 27, count 0 2006.201.11:12:29.26#ibcon#*after write, iclass 27, count 0 2006.201.11:12:29.26#ibcon#*before return 0, iclass 27, count 0 2006.201.11:12:29.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:29.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:29.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.11:12:29.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.11:12:29.26$vck44/va=5,4 2006.201.11:12:29.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.11:12:29.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.11:12:29.26#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:29.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:29.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:29.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:29.32#ibcon#enter wrdev, iclass 29, count 2 2006.201.11:12:29.32#ibcon#first serial, iclass 29, count 2 2006.201.11:12:29.32#ibcon#enter sib2, iclass 29, count 2 2006.201.11:12:29.32#ibcon#flushed, iclass 29, count 2 2006.201.11:12:29.32#ibcon#about to write, iclass 29, count 2 2006.201.11:12:29.32#ibcon#wrote, iclass 29, count 2 2006.201.11:12:29.32#ibcon#about to read 3, iclass 29, count 2 2006.201.11:12:29.34#ibcon#read 3, iclass 29, count 2 2006.201.11:12:29.34#ibcon#about to read 4, iclass 29, count 2 2006.201.11:12:29.34#ibcon#read 4, iclass 29, count 2 2006.201.11:12:29.34#ibcon#about to read 5, iclass 29, count 2 2006.201.11:12:29.34#ibcon#read 5, iclass 29, count 2 2006.201.11:12:29.34#ibcon#about to read 6, iclass 29, count 2 2006.201.11:12:29.34#ibcon#read 6, iclass 29, count 2 2006.201.11:12:29.34#ibcon#end of sib2, iclass 29, count 2 2006.201.11:12:29.34#ibcon#*mode == 0, iclass 29, count 2 2006.201.11:12:29.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.11:12:29.34#ibcon#[25=AT05-04\r\n] 2006.201.11:12:29.34#ibcon#*before write, iclass 29, count 2 2006.201.11:12:29.34#ibcon#enter sib2, iclass 29, count 2 2006.201.11:12:29.34#ibcon#flushed, iclass 29, count 2 2006.201.11:12:29.34#ibcon#about to write, iclass 29, count 2 2006.201.11:12:29.34#ibcon#wrote, iclass 29, count 2 2006.201.11:12:29.34#ibcon#about to read 3, iclass 29, count 2 2006.201.11:12:29.37#ibcon#read 3, iclass 29, count 2 2006.201.11:12:29.37#ibcon#about to read 4, iclass 29, count 2 2006.201.11:12:29.37#ibcon#read 4, iclass 29, count 2 2006.201.11:12:29.37#ibcon#about to read 5, iclass 29, count 2 2006.201.11:12:29.37#ibcon#read 5, iclass 29, count 2 2006.201.11:12:29.37#ibcon#about to read 6, iclass 29, count 2 2006.201.11:12:29.37#ibcon#read 6, iclass 29, count 2 2006.201.11:12:29.37#ibcon#end of sib2, iclass 29, count 2 2006.201.11:12:29.37#ibcon#*after write, iclass 29, count 2 2006.201.11:12:29.37#ibcon#*before return 0, iclass 29, count 2 2006.201.11:12:29.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:29.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:29.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.11:12:29.37#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:29.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:29.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:29.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:29.49#ibcon#enter wrdev, iclass 29, count 0 2006.201.11:12:29.49#ibcon#first serial, iclass 29, count 0 2006.201.11:12:29.49#ibcon#enter sib2, iclass 29, count 0 2006.201.11:12:29.49#ibcon#flushed, iclass 29, count 0 2006.201.11:12:29.49#ibcon#about to write, iclass 29, count 0 2006.201.11:12:29.49#ibcon#wrote, iclass 29, count 0 2006.201.11:12:29.49#ibcon#about to read 3, iclass 29, count 0 2006.201.11:12:29.51#ibcon#read 3, iclass 29, count 0 2006.201.11:12:29.51#ibcon#about to read 4, iclass 29, count 0 2006.201.11:12:29.51#ibcon#read 4, iclass 29, count 0 2006.201.11:12:29.51#ibcon#about to read 5, iclass 29, count 0 2006.201.11:12:29.51#ibcon#read 5, iclass 29, count 0 2006.201.11:12:29.51#ibcon#about to read 6, iclass 29, count 0 2006.201.11:12:29.51#ibcon#read 6, iclass 29, count 0 2006.201.11:12:29.51#ibcon#end of sib2, iclass 29, count 0 2006.201.11:12:29.51#ibcon#*mode == 0, iclass 29, count 0 2006.201.11:12:29.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.11:12:29.51#ibcon#[25=USB\r\n] 2006.201.11:12:29.51#ibcon#*before write, iclass 29, count 0 2006.201.11:12:29.51#ibcon#enter sib2, iclass 29, count 0 2006.201.11:12:29.51#ibcon#flushed, iclass 29, count 0 2006.201.11:12:29.51#ibcon#about to write, iclass 29, count 0 2006.201.11:12:29.51#ibcon#wrote, iclass 29, count 0 2006.201.11:12:29.51#ibcon#about to read 3, iclass 29, count 0 2006.201.11:12:29.54#ibcon#read 3, iclass 29, count 0 2006.201.11:12:29.54#ibcon#about to read 4, iclass 29, count 0 2006.201.11:12:29.54#ibcon#read 4, iclass 29, count 0 2006.201.11:12:29.54#ibcon#about to read 5, iclass 29, count 0 2006.201.11:12:29.54#ibcon#read 5, iclass 29, count 0 2006.201.11:12:29.54#ibcon#about to read 6, iclass 29, count 0 2006.201.11:12:29.54#ibcon#read 6, iclass 29, count 0 2006.201.11:12:29.54#ibcon#end of sib2, iclass 29, count 0 2006.201.11:12:29.54#ibcon#*after write, iclass 29, count 0 2006.201.11:12:29.54#ibcon#*before return 0, iclass 29, count 0 2006.201.11:12:29.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:29.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:29.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.11:12:29.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.11:12:29.54$vck44/valo=6,814.99 2006.201.11:12:29.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.11:12:29.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.11:12:29.54#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:29.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:29.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:29.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:29.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.11:12:29.54#ibcon#first serial, iclass 31, count 0 2006.201.11:12:29.54#ibcon#enter sib2, iclass 31, count 0 2006.201.11:12:29.54#ibcon#flushed, iclass 31, count 0 2006.201.11:12:29.54#ibcon#about to write, iclass 31, count 0 2006.201.11:12:29.54#ibcon#wrote, iclass 31, count 0 2006.201.11:12:29.54#ibcon#about to read 3, iclass 31, count 0 2006.201.11:12:29.56#ibcon#read 3, iclass 31, count 0 2006.201.11:12:29.56#ibcon#about to read 4, iclass 31, count 0 2006.201.11:12:29.56#ibcon#read 4, iclass 31, count 0 2006.201.11:12:29.56#ibcon#about to read 5, iclass 31, count 0 2006.201.11:12:29.56#ibcon#read 5, iclass 31, count 0 2006.201.11:12:29.56#ibcon#about to read 6, iclass 31, count 0 2006.201.11:12:29.56#ibcon#read 6, iclass 31, count 0 2006.201.11:12:29.56#ibcon#end of sib2, iclass 31, count 0 2006.201.11:12:29.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.11:12:29.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.11:12:29.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:12:29.56#ibcon#*before write, iclass 31, count 0 2006.201.11:12:29.56#ibcon#enter sib2, iclass 31, count 0 2006.201.11:12:29.56#ibcon#flushed, iclass 31, count 0 2006.201.11:12:29.56#ibcon#about to write, iclass 31, count 0 2006.201.11:12:29.56#ibcon#wrote, iclass 31, count 0 2006.201.11:12:29.56#ibcon#about to read 3, iclass 31, count 0 2006.201.11:12:29.61#ibcon#read 3, iclass 31, count 0 2006.201.11:12:29.61#ibcon#about to read 4, iclass 31, count 0 2006.201.11:12:29.61#ibcon#read 4, iclass 31, count 0 2006.201.11:12:29.61#ibcon#about to read 5, iclass 31, count 0 2006.201.11:12:29.61#ibcon#read 5, iclass 31, count 0 2006.201.11:12:29.61#ibcon#about to read 6, iclass 31, count 0 2006.201.11:12:29.61#ibcon#read 6, iclass 31, count 0 2006.201.11:12:29.61#ibcon#end of sib2, iclass 31, count 0 2006.201.11:12:29.61#ibcon#*after write, iclass 31, count 0 2006.201.11:12:29.61#ibcon#*before return 0, iclass 31, count 0 2006.201.11:12:29.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:29.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:29.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.11:12:29.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.11:12:29.61$vck44/va=6,5 2006.201.11:12:29.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.11:12:29.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.11:12:29.61#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:29.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:29.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:29.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:29.66#ibcon#enter wrdev, iclass 33, count 2 2006.201.11:12:29.66#ibcon#first serial, iclass 33, count 2 2006.201.11:12:29.66#ibcon#enter sib2, iclass 33, count 2 2006.201.11:12:29.66#ibcon#flushed, iclass 33, count 2 2006.201.11:12:29.66#ibcon#about to write, iclass 33, count 2 2006.201.11:12:29.66#ibcon#wrote, iclass 33, count 2 2006.201.11:12:29.66#ibcon#about to read 3, iclass 33, count 2 2006.201.11:12:29.68#ibcon#read 3, iclass 33, count 2 2006.201.11:12:29.68#ibcon#about to read 4, iclass 33, count 2 2006.201.11:12:29.68#ibcon#read 4, iclass 33, count 2 2006.201.11:12:29.68#ibcon#about to read 5, iclass 33, count 2 2006.201.11:12:29.68#ibcon#read 5, iclass 33, count 2 2006.201.11:12:29.68#ibcon#about to read 6, iclass 33, count 2 2006.201.11:12:29.68#ibcon#read 6, iclass 33, count 2 2006.201.11:12:29.68#ibcon#end of sib2, iclass 33, count 2 2006.201.11:12:29.68#ibcon#*mode == 0, iclass 33, count 2 2006.201.11:12:29.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.11:12:29.68#ibcon#[25=AT06-05\r\n] 2006.201.11:12:29.68#ibcon#*before write, iclass 33, count 2 2006.201.11:12:29.68#ibcon#enter sib2, iclass 33, count 2 2006.201.11:12:29.68#ibcon#flushed, iclass 33, count 2 2006.201.11:12:29.68#ibcon#about to write, iclass 33, count 2 2006.201.11:12:29.68#ibcon#wrote, iclass 33, count 2 2006.201.11:12:29.68#ibcon#about to read 3, iclass 33, count 2 2006.201.11:12:29.71#ibcon#read 3, iclass 33, count 2 2006.201.11:12:29.71#ibcon#about to read 4, iclass 33, count 2 2006.201.11:12:29.71#ibcon#read 4, iclass 33, count 2 2006.201.11:12:29.71#ibcon#about to read 5, iclass 33, count 2 2006.201.11:12:29.71#ibcon#read 5, iclass 33, count 2 2006.201.11:12:29.71#ibcon#about to read 6, iclass 33, count 2 2006.201.11:12:29.71#ibcon#read 6, iclass 33, count 2 2006.201.11:12:29.71#ibcon#end of sib2, iclass 33, count 2 2006.201.11:12:29.71#ibcon#*after write, iclass 33, count 2 2006.201.11:12:29.71#ibcon#*before return 0, iclass 33, count 2 2006.201.11:12:29.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:29.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:29.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.11:12:29.71#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:29.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:29.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:29.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:29.83#ibcon#enter wrdev, iclass 33, count 0 2006.201.11:12:29.83#ibcon#first serial, iclass 33, count 0 2006.201.11:12:29.83#ibcon#enter sib2, iclass 33, count 0 2006.201.11:12:29.83#ibcon#flushed, iclass 33, count 0 2006.201.11:12:29.83#ibcon#about to write, iclass 33, count 0 2006.201.11:12:29.83#ibcon#wrote, iclass 33, count 0 2006.201.11:12:29.83#ibcon#about to read 3, iclass 33, count 0 2006.201.11:12:29.85#ibcon#read 3, iclass 33, count 0 2006.201.11:12:29.85#ibcon#about to read 4, iclass 33, count 0 2006.201.11:12:29.85#ibcon#read 4, iclass 33, count 0 2006.201.11:12:29.85#ibcon#about to read 5, iclass 33, count 0 2006.201.11:12:29.85#ibcon#read 5, iclass 33, count 0 2006.201.11:12:29.85#ibcon#about to read 6, iclass 33, count 0 2006.201.11:12:29.85#ibcon#read 6, iclass 33, count 0 2006.201.11:12:29.85#ibcon#end of sib2, iclass 33, count 0 2006.201.11:12:29.85#ibcon#*mode == 0, iclass 33, count 0 2006.201.11:12:29.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.11:12:29.85#ibcon#[25=USB\r\n] 2006.201.11:12:29.85#ibcon#*before write, iclass 33, count 0 2006.201.11:12:29.85#ibcon#enter sib2, iclass 33, count 0 2006.201.11:12:29.85#ibcon#flushed, iclass 33, count 0 2006.201.11:12:29.85#ibcon#about to write, iclass 33, count 0 2006.201.11:12:29.85#ibcon#wrote, iclass 33, count 0 2006.201.11:12:29.85#ibcon#about to read 3, iclass 33, count 0 2006.201.11:12:29.88#ibcon#read 3, iclass 33, count 0 2006.201.11:12:29.88#ibcon#about to read 4, iclass 33, count 0 2006.201.11:12:29.88#ibcon#read 4, iclass 33, count 0 2006.201.11:12:29.88#ibcon#about to read 5, iclass 33, count 0 2006.201.11:12:29.88#ibcon#read 5, iclass 33, count 0 2006.201.11:12:29.88#ibcon#about to read 6, iclass 33, count 0 2006.201.11:12:29.88#ibcon#read 6, iclass 33, count 0 2006.201.11:12:29.88#ibcon#end of sib2, iclass 33, count 0 2006.201.11:12:29.88#ibcon#*after write, iclass 33, count 0 2006.201.11:12:29.88#ibcon#*before return 0, iclass 33, count 0 2006.201.11:12:29.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:29.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:29.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.11:12:29.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.11:12:29.88$vck44/valo=7,864.99 2006.201.11:12:29.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.11:12:29.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.11:12:29.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:29.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:29.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:29.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:29.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.11:12:29.88#ibcon#first serial, iclass 35, count 0 2006.201.11:12:29.88#ibcon#enter sib2, iclass 35, count 0 2006.201.11:12:29.88#ibcon#flushed, iclass 35, count 0 2006.201.11:12:29.88#ibcon#about to write, iclass 35, count 0 2006.201.11:12:29.88#ibcon#wrote, iclass 35, count 0 2006.201.11:12:29.88#ibcon#about to read 3, iclass 35, count 0 2006.201.11:12:29.90#ibcon#read 3, iclass 35, count 0 2006.201.11:12:29.90#ibcon#about to read 4, iclass 35, count 0 2006.201.11:12:29.90#ibcon#read 4, iclass 35, count 0 2006.201.11:12:29.90#ibcon#about to read 5, iclass 35, count 0 2006.201.11:12:29.90#ibcon#read 5, iclass 35, count 0 2006.201.11:12:29.90#ibcon#about to read 6, iclass 35, count 0 2006.201.11:12:29.90#ibcon#read 6, iclass 35, count 0 2006.201.11:12:29.90#ibcon#end of sib2, iclass 35, count 0 2006.201.11:12:29.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.11:12:29.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.11:12:29.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:12:29.90#ibcon#*before write, iclass 35, count 0 2006.201.11:12:29.90#ibcon#enter sib2, iclass 35, count 0 2006.201.11:12:29.90#ibcon#flushed, iclass 35, count 0 2006.201.11:12:29.90#ibcon#about to write, iclass 35, count 0 2006.201.11:12:29.90#ibcon#wrote, iclass 35, count 0 2006.201.11:12:29.90#ibcon#about to read 3, iclass 35, count 0 2006.201.11:12:29.95#ibcon#read 3, iclass 35, count 0 2006.201.11:12:29.95#ibcon#about to read 4, iclass 35, count 0 2006.201.11:12:29.95#ibcon#read 4, iclass 35, count 0 2006.201.11:12:29.95#ibcon#about to read 5, iclass 35, count 0 2006.201.11:12:29.95#ibcon#read 5, iclass 35, count 0 2006.201.11:12:29.95#ibcon#about to read 6, iclass 35, count 0 2006.201.11:12:29.95#ibcon#read 6, iclass 35, count 0 2006.201.11:12:29.95#ibcon#end of sib2, iclass 35, count 0 2006.201.11:12:29.95#ibcon#*after write, iclass 35, count 0 2006.201.11:12:29.95#ibcon#*before return 0, iclass 35, count 0 2006.201.11:12:29.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:29.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:29.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.11:12:29.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.11:12:29.95$vck44/va=7,5 2006.201.11:12:29.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.11:12:29.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.11:12:29.95#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:29.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:30.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:30.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:30.00#ibcon#enter wrdev, iclass 37, count 2 2006.201.11:12:30.00#ibcon#first serial, iclass 37, count 2 2006.201.11:12:30.00#ibcon#enter sib2, iclass 37, count 2 2006.201.11:12:30.00#ibcon#flushed, iclass 37, count 2 2006.201.11:12:30.00#ibcon#about to write, iclass 37, count 2 2006.201.11:12:30.00#ibcon#wrote, iclass 37, count 2 2006.201.11:12:30.00#ibcon#about to read 3, iclass 37, count 2 2006.201.11:12:30.02#ibcon#read 3, iclass 37, count 2 2006.201.11:12:30.02#ibcon#about to read 4, iclass 37, count 2 2006.201.11:12:30.02#ibcon#read 4, iclass 37, count 2 2006.201.11:12:30.02#ibcon#about to read 5, iclass 37, count 2 2006.201.11:12:30.02#ibcon#read 5, iclass 37, count 2 2006.201.11:12:30.02#ibcon#about to read 6, iclass 37, count 2 2006.201.11:12:30.02#ibcon#read 6, iclass 37, count 2 2006.201.11:12:30.02#ibcon#end of sib2, iclass 37, count 2 2006.201.11:12:30.02#ibcon#*mode == 0, iclass 37, count 2 2006.201.11:12:30.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.11:12:30.02#ibcon#[25=AT07-05\r\n] 2006.201.11:12:30.02#ibcon#*before write, iclass 37, count 2 2006.201.11:12:30.02#ibcon#enter sib2, iclass 37, count 2 2006.201.11:12:30.02#ibcon#flushed, iclass 37, count 2 2006.201.11:12:30.02#ibcon#about to write, iclass 37, count 2 2006.201.11:12:30.02#ibcon#wrote, iclass 37, count 2 2006.201.11:12:30.02#ibcon#about to read 3, iclass 37, count 2 2006.201.11:12:30.05#ibcon#read 3, iclass 37, count 2 2006.201.11:12:30.05#ibcon#about to read 4, iclass 37, count 2 2006.201.11:12:30.05#ibcon#read 4, iclass 37, count 2 2006.201.11:12:30.05#ibcon#about to read 5, iclass 37, count 2 2006.201.11:12:30.05#ibcon#read 5, iclass 37, count 2 2006.201.11:12:30.05#ibcon#about to read 6, iclass 37, count 2 2006.201.11:12:30.05#ibcon#read 6, iclass 37, count 2 2006.201.11:12:30.05#ibcon#end of sib2, iclass 37, count 2 2006.201.11:12:30.05#ibcon#*after write, iclass 37, count 2 2006.201.11:12:30.05#ibcon#*before return 0, iclass 37, count 2 2006.201.11:12:30.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:30.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:30.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.11:12:30.05#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:30.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:30.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:30.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:30.17#ibcon#enter wrdev, iclass 37, count 0 2006.201.11:12:30.17#ibcon#first serial, iclass 37, count 0 2006.201.11:12:30.17#ibcon#enter sib2, iclass 37, count 0 2006.201.11:12:30.17#ibcon#flushed, iclass 37, count 0 2006.201.11:12:30.17#ibcon#about to write, iclass 37, count 0 2006.201.11:12:30.17#ibcon#wrote, iclass 37, count 0 2006.201.11:12:30.17#ibcon#about to read 3, iclass 37, count 0 2006.201.11:12:30.19#ibcon#read 3, iclass 37, count 0 2006.201.11:12:30.19#ibcon#about to read 4, iclass 37, count 0 2006.201.11:12:30.19#ibcon#read 4, iclass 37, count 0 2006.201.11:12:30.19#ibcon#about to read 5, iclass 37, count 0 2006.201.11:12:30.19#ibcon#read 5, iclass 37, count 0 2006.201.11:12:30.19#ibcon#about to read 6, iclass 37, count 0 2006.201.11:12:30.19#ibcon#read 6, iclass 37, count 0 2006.201.11:12:30.19#ibcon#end of sib2, iclass 37, count 0 2006.201.11:12:30.19#ibcon#*mode == 0, iclass 37, count 0 2006.201.11:12:30.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.11:12:30.19#ibcon#[25=USB\r\n] 2006.201.11:12:30.19#ibcon#*before write, iclass 37, count 0 2006.201.11:12:30.19#ibcon#enter sib2, iclass 37, count 0 2006.201.11:12:30.19#ibcon#flushed, iclass 37, count 0 2006.201.11:12:30.19#ibcon#about to write, iclass 37, count 0 2006.201.11:12:30.19#ibcon#wrote, iclass 37, count 0 2006.201.11:12:30.19#ibcon#about to read 3, iclass 37, count 0 2006.201.11:12:30.22#ibcon#read 3, iclass 37, count 0 2006.201.11:12:30.22#ibcon#about to read 4, iclass 37, count 0 2006.201.11:12:30.22#ibcon#read 4, iclass 37, count 0 2006.201.11:12:30.22#ibcon#about to read 5, iclass 37, count 0 2006.201.11:12:30.22#ibcon#read 5, iclass 37, count 0 2006.201.11:12:30.22#ibcon#about to read 6, iclass 37, count 0 2006.201.11:12:30.22#ibcon#read 6, iclass 37, count 0 2006.201.11:12:30.22#ibcon#end of sib2, iclass 37, count 0 2006.201.11:12:30.22#ibcon#*after write, iclass 37, count 0 2006.201.11:12:30.22#ibcon#*before return 0, iclass 37, count 0 2006.201.11:12:30.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:30.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:30.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.11:12:30.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.11:12:30.22$vck44/valo=8,884.99 2006.201.11:12:30.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.11:12:30.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.11:12:30.22#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:30.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:30.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:30.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:30.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.11:12:30.22#ibcon#first serial, iclass 39, count 0 2006.201.11:12:30.22#ibcon#enter sib2, iclass 39, count 0 2006.201.11:12:30.22#ibcon#flushed, iclass 39, count 0 2006.201.11:12:30.22#ibcon#about to write, iclass 39, count 0 2006.201.11:12:30.22#ibcon#wrote, iclass 39, count 0 2006.201.11:12:30.22#ibcon#about to read 3, iclass 39, count 0 2006.201.11:12:30.24#ibcon#read 3, iclass 39, count 0 2006.201.11:12:30.24#ibcon#about to read 4, iclass 39, count 0 2006.201.11:12:30.24#ibcon#read 4, iclass 39, count 0 2006.201.11:12:30.24#ibcon#about to read 5, iclass 39, count 0 2006.201.11:12:30.24#ibcon#read 5, iclass 39, count 0 2006.201.11:12:30.24#ibcon#about to read 6, iclass 39, count 0 2006.201.11:12:30.24#ibcon#read 6, iclass 39, count 0 2006.201.11:12:30.24#ibcon#end of sib2, iclass 39, count 0 2006.201.11:12:30.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.11:12:30.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.11:12:30.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:12:30.24#ibcon#*before write, iclass 39, count 0 2006.201.11:12:30.24#ibcon#enter sib2, iclass 39, count 0 2006.201.11:12:30.24#ibcon#flushed, iclass 39, count 0 2006.201.11:12:30.24#ibcon#about to write, iclass 39, count 0 2006.201.11:12:30.24#ibcon#wrote, iclass 39, count 0 2006.201.11:12:30.24#ibcon#about to read 3, iclass 39, count 0 2006.201.11:12:30.28#ibcon#read 3, iclass 39, count 0 2006.201.11:12:30.28#ibcon#about to read 4, iclass 39, count 0 2006.201.11:12:30.28#ibcon#read 4, iclass 39, count 0 2006.201.11:12:30.28#ibcon#about to read 5, iclass 39, count 0 2006.201.11:12:30.28#ibcon#read 5, iclass 39, count 0 2006.201.11:12:30.28#ibcon#about to read 6, iclass 39, count 0 2006.201.11:12:30.28#ibcon#read 6, iclass 39, count 0 2006.201.11:12:30.28#ibcon#end of sib2, iclass 39, count 0 2006.201.11:12:30.28#ibcon#*after write, iclass 39, count 0 2006.201.11:12:30.28#ibcon#*before return 0, iclass 39, count 0 2006.201.11:12:30.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:30.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:30.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.11:12:30.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.11:12:30.28$vck44/va=8,4 2006.201.11:12:30.28#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.11:12:30.28#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.11:12:30.28#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:30.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:12:30.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:12:30.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:12:30.34#ibcon#enter wrdev, iclass 2, count 2 2006.201.11:12:30.34#ibcon#first serial, iclass 2, count 2 2006.201.11:12:30.34#ibcon#enter sib2, iclass 2, count 2 2006.201.11:12:30.34#ibcon#flushed, iclass 2, count 2 2006.201.11:12:30.34#ibcon#about to write, iclass 2, count 2 2006.201.11:12:30.34#ibcon#wrote, iclass 2, count 2 2006.201.11:12:30.34#ibcon#about to read 3, iclass 2, count 2 2006.201.11:12:30.36#ibcon#read 3, iclass 2, count 2 2006.201.11:12:30.36#ibcon#about to read 4, iclass 2, count 2 2006.201.11:12:30.36#ibcon#read 4, iclass 2, count 2 2006.201.11:12:30.36#ibcon#about to read 5, iclass 2, count 2 2006.201.11:12:30.36#ibcon#read 5, iclass 2, count 2 2006.201.11:12:30.36#ibcon#about to read 6, iclass 2, count 2 2006.201.11:12:30.36#ibcon#read 6, iclass 2, count 2 2006.201.11:12:30.36#ibcon#end of sib2, iclass 2, count 2 2006.201.11:12:30.36#ibcon#*mode == 0, iclass 2, count 2 2006.201.11:12:30.36#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.11:12:30.36#ibcon#[25=AT08-04\r\n] 2006.201.11:12:30.36#ibcon#*before write, iclass 2, count 2 2006.201.11:12:30.36#ibcon#enter sib2, iclass 2, count 2 2006.201.11:12:30.36#ibcon#flushed, iclass 2, count 2 2006.201.11:12:30.36#ibcon#about to write, iclass 2, count 2 2006.201.11:12:30.36#ibcon#wrote, iclass 2, count 2 2006.201.11:12:30.36#ibcon#about to read 3, iclass 2, count 2 2006.201.11:12:30.39#ibcon#read 3, iclass 2, count 2 2006.201.11:12:30.39#ibcon#about to read 4, iclass 2, count 2 2006.201.11:12:30.39#ibcon#read 4, iclass 2, count 2 2006.201.11:12:30.39#ibcon#about to read 5, iclass 2, count 2 2006.201.11:12:30.39#ibcon#read 5, iclass 2, count 2 2006.201.11:12:30.39#ibcon#about to read 6, iclass 2, count 2 2006.201.11:12:30.39#ibcon#read 6, iclass 2, count 2 2006.201.11:12:30.39#ibcon#end of sib2, iclass 2, count 2 2006.201.11:12:30.39#ibcon#*after write, iclass 2, count 2 2006.201.11:12:30.39#ibcon#*before return 0, iclass 2, count 2 2006.201.11:12:30.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:12:30.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:12:30.39#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.11:12:30.39#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:30.39#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:12:30.51#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:12:30.51#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:12:30.51#ibcon#enter wrdev, iclass 2, count 0 2006.201.11:12:30.51#ibcon#first serial, iclass 2, count 0 2006.201.11:12:30.51#ibcon#enter sib2, iclass 2, count 0 2006.201.11:12:30.51#ibcon#flushed, iclass 2, count 0 2006.201.11:12:30.51#ibcon#about to write, iclass 2, count 0 2006.201.11:12:30.51#ibcon#wrote, iclass 2, count 0 2006.201.11:12:30.51#ibcon#about to read 3, iclass 2, count 0 2006.201.11:12:30.53#ibcon#read 3, iclass 2, count 0 2006.201.11:12:30.53#ibcon#about to read 4, iclass 2, count 0 2006.201.11:12:30.53#ibcon#read 4, iclass 2, count 0 2006.201.11:12:30.53#ibcon#about to read 5, iclass 2, count 0 2006.201.11:12:30.53#ibcon#read 5, iclass 2, count 0 2006.201.11:12:30.53#ibcon#about to read 6, iclass 2, count 0 2006.201.11:12:30.53#ibcon#read 6, iclass 2, count 0 2006.201.11:12:30.53#ibcon#end of sib2, iclass 2, count 0 2006.201.11:12:30.53#ibcon#*mode == 0, iclass 2, count 0 2006.201.11:12:30.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.11:12:30.53#ibcon#[25=USB\r\n] 2006.201.11:12:30.53#ibcon#*before write, iclass 2, count 0 2006.201.11:12:30.53#ibcon#enter sib2, iclass 2, count 0 2006.201.11:12:30.53#ibcon#flushed, iclass 2, count 0 2006.201.11:12:30.53#ibcon#about to write, iclass 2, count 0 2006.201.11:12:30.53#ibcon#wrote, iclass 2, count 0 2006.201.11:12:30.53#ibcon#about to read 3, iclass 2, count 0 2006.201.11:12:30.56#ibcon#read 3, iclass 2, count 0 2006.201.11:12:30.56#ibcon#about to read 4, iclass 2, count 0 2006.201.11:12:30.56#ibcon#read 4, iclass 2, count 0 2006.201.11:12:30.56#ibcon#about to read 5, iclass 2, count 0 2006.201.11:12:30.56#ibcon#read 5, iclass 2, count 0 2006.201.11:12:30.56#ibcon#about to read 6, iclass 2, count 0 2006.201.11:12:30.56#ibcon#read 6, iclass 2, count 0 2006.201.11:12:30.56#ibcon#end of sib2, iclass 2, count 0 2006.201.11:12:30.56#ibcon#*after write, iclass 2, count 0 2006.201.11:12:30.56#ibcon#*before return 0, iclass 2, count 0 2006.201.11:12:30.56#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:12:30.56#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:12:30.56#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.11:12:30.56#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.11:12:30.56$vck44/vblo=1,629.99 2006.201.11:12:30.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.11:12:30.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.11:12:30.56#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:30.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:12:30.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:12:30.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:12:30.56#ibcon#enter wrdev, iclass 5, count 0 2006.201.11:12:30.56#ibcon#first serial, iclass 5, count 0 2006.201.11:12:30.56#ibcon#enter sib2, iclass 5, count 0 2006.201.11:12:30.56#ibcon#flushed, iclass 5, count 0 2006.201.11:12:30.56#ibcon#about to write, iclass 5, count 0 2006.201.11:12:30.56#ibcon#wrote, iclass 5, count 0 2006.201.11:12:30.56#ibcon#about to read 3, iclass 5, count 0 2006.201.11:12:30.58#ibcon#read 3, iclass 5, count 0 2006.201.11:12:30.58#ibcon#about to read 4, iclass 5, count 0 2006.201.11:12:30.58#ibcon#read 4, iclass 5, count 0 2006.201.11:12:30.58#ibcon#about to read 5, iclass 5, count 0 2006.201.11:12:30.58#ibcon#read 5, iclass 5, count 0 2006.201.11:12:30.58#ibcon#about to read 6, iclass 5, count 0 2006.201.11:12:30.58#ibcon#read 6, iclass 5, count 0 2006.201.11:12:30.58#ibcon#end of sib2, iclass 5, count 0 2006.201.11:12:30.58#ibcon#*mode == 0, iclass 5, count 0 2006.201.11:12:30.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.11:12:30.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:12:30.58#ibcon#*before write, iclass 5, count 0 2006.201.11:12:30.58#ibcon#enter sib2, iclass 5, count 0 2006.201.11:12:30.58#ibcon#flushed, iclass 5, count 0 2006.201.11:12:30.58#ibcon#about to write, iclass 5, count 0 2006.201.11:12:30.58#ibcon#wrote, iclass 5, count 0 2006.201.11:12:30.58#ibcon#about to read 3, iclass 5, count 0 2006.201.11:12:30.63#ibcon#read 3, iclass 5, count 0 2006.201.11:12:30.63#ibcon#about to read 4, iclass 5, count 0 2006.201.11:12:30.63#ibcon#read 4, iclass 5, count 0 2006.201.11:12:30.63#ibcon#about to read 5, iclass 5, count 0 2006.201.11:12:30.63#ibcon#read 5, iclass 5, count 0 2006.201.11:12:30.63#ibcon#about to read 6, iclass 5, count 0 2006.201.11:12:30.63#ibcon#read 6, iclass 5, count 0 2006.201.11:12:30.63#ibcon#end of sib2, iclass 5, count 0 2006.201.11:12:30.63#ibcon#*after write, iclass 5, count 0 2006.201.11:12:30.63#ibcon#*before return 0, iclass 5, count 0 2006.201.11:12:30.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:12:30.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:12:30.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.11:12:30.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.11:12:30.63$vck44/vb=1,4 2006.201.11:12:30.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.11:12:30.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.11:12:30.63#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:30.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:12:30.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:12:30.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:12:30.63#ibcon#enter wrdev, iclass 7, count 2 2006.201.11:12:30.63#ibcon#first serial, iclass 7, count 2 2006.201.11:12:30.63#ibcon#enter sib2, iclass 7, count 2 2006.201.11:12:30.63#ibcon#flushed, iclass 7, count 2 2006.201.11:12:30.63#ibcon#about to write, iclass 7, count 2 2006.201.11:12:30.63#ibcon#wrote, iclass 7, count 2 2006.201.11:12:30.63#ibcon#about to read 3, iclass 7, count 2 2006.201.11:12:30.65#ibcon#read 3, iclass 7, count 2 2006.201.11:12:30.65#ibcon#about to read 4, iclass 7, count 2 2006.201.11:12:30.65#ibcon#read 4, iclass 7, count 2 2006.201.11:12:30.65#ibcon#about to read 5, iclass 7, count 2 2006.201.11:12:30.65#ibcon#read 5, iclass 7, count 2 2006.201.11:12:30.65#ibcon#about to read 6, iclass 7, count 2 2006.201.11:12:30.65#ibcon#read 6, iclass 7, count 2 2006.201.11:12:30.65#ibcon#end of sib2, iclass 7, count 2 2006.201.11:12:30.65#ibcon#*mode == 0, iclass 7, count 2 2006.201.11:12:30.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.11:12:30.65#ibcon#[27=AT01-04\r\n] 2006.201.11:12:30.65#ibcon#*before write, iclass 7, count 2 2006.201.11:12:30.65#ibcon#enter sib2, iclass 7, count 2 2006.201.11:12:30.65#ibcon#flushed, iclass 7, count 2 2006.201.11:12:30.65#ibcon#about to write, iclass 7, count 2 2006.201.11:12:30.65#ibcon#wrote, iclass 7, count 2 2006.201.11:12:30.65#ibcon#about to read 3, iclass 7, count 2 2006.201.11:12:30.68#ibcon#read 3, iclass 7, count 2 2006.201.11:12:30.68#ibcon#about to read 4, iclass 7, count 2 2006.201.11:12:30.68#ibcon#read 4, iclass 7, count 2 2006.201.11:12:30.68#ibcon#about to read 5, iclass 7, count 2 2006.201.11:12:30.68#ibcon#read 5, iclass 7, count 2 2006.201.11:12:30.68#ibcon#about to read 6, iclass 7, count 2 2006.201.11:12:30.68#ibcon#read 6, iclass 7, count 2 2006.201.11:12:30.68#ibcon#end of sib2, iclass 7, count 2 2006.201.11:12:30.68#ibcon#*after write, iclass 7, count 2 2006.201.11:12:30.68#ibcon#*before return 0, iclass 7, count 2 2006.201.11:12:30.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:12:30.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:12:30.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.11:12:30.68#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:30.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:12:30.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:12:30.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:12:30.80#ibcon#enter wrdev, iclass 7, count 0 2006.201.11:12:30.80#ibcon#first serial, iclass 7, count 0 2006.201.11:12:30.80#ibcon#enter sib2, iclass 7, count 0 2006.201.11:12:30.80#ibcon#flushed, iclass 7, count 0 2006.201.11:12:30.80#ibcon#about to write, iclass 7, count 0 2006.201.11:12:30.80#ibcon#wrote, iclass 7, count 0 2006.201.11:12:30.80#ibcon#about to read 3, iclass 7, count 0 2006.201.11:12:30.82#ibcon#read 3, iclass 7, count 0 2006.201.11:12:30.82#ibcon#about to read 4, iclass 7, count 0 2006.201.11:12:30.82#ibcon#read 4, iclass 7, count 0 2006.201.11:12:30.82#ibcon#about to read 5, iclass 7, count 0 2006.201.11:12:30.82#ibcon#read 5, iclass 7, count 0 2006.201.11:12:30.82#ibcon#about to read 6, iclass 7, count 0 2006.201.11:12:30.82#ibcon#read 6, iclass 7, count 0 2006.201.11:12:30.82#ibcon#end of sib2, iclass 7, count 0 2006.201.11:12:30.82#ibcon#*mode == 0, iclass 7, count 0 2006.201.11:12:30.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.11:12:30.82#ibcon#[27=USB\r\n] 2006.201.11:12:30.82#ibcon#*before write, iclass 7, count 0 2006.201.11:12:30.82#ibcon#enter sib2, iclass 7, count 0 2006.201.11:12:30.82#ibcon#flushed, iclass 7, count 0 2006.201.11:12:30.82#ibcon#about to write, iclass 7, count 0 2006.201.11:12:30.82#ibcon#wrote, iclass 7, count 0 2006.201.11:12:30.82#ibcon#about to read 3, iclass 7, count 0 2006.201.11:12:30.85#ibcon#read 3, iclass 7, count 0 2006.201.11:12:30.85#ibcon#about to read 4, iclass 7, count 0 2006.201.11:12:30.85#ibcon#read 4, iclass 7, count 0 2006.201.11:12:30.85#ibcon#about to read 5, iclass 7, count 0 2006.201.11:12:30.85#ibcon#read 5, iclass 7, count 0 2006.201.11:12:30.85#ibcon#about to read 6, iclass 7, count 0 2006.201.11:12:30.85#ibcon#read 6, iclass 7, count 0 2006.201.11:12:30.85#ibcon#end of sib2, iclass 7, count 0 2006.201.11:12:30.85#ibcon#*after write, iclass 7, count 0 2006.201.11:12:30.85#ibcon#*before return 0, iclass 7, count 0 2006.201.11:12:30.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:12:30.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:12:30.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.11:12:30.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.11:12:30.85$vck44/vblo=2,634.99 2006.201.11:12:30.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.11:12:30.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.11:12:30.85#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:30.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:30.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:30.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:30.85#ibcon#enter wrdev, iclass 11, count 0 2006.201.11:12:30.85#ibcon#first serial, iclass 11, count 0 2006.201.11:12:30.85#ibcon#enter sib2, iclass 11, count 0 2006.201.11:12:30.85#ibcon#flushed, iclass 11, count 0 2006.201.11:12:30.85#ibcon#about to write, iclass 11, count 0 2006.201.11:12:30.85#ibcon#wrote, iclass 11, count 0 2006.201.11:12:30.85#ibcon#about to read 3, iclass 11, count 0 2006.201.11:12:30.87#ibcon#read 3, iclass 11, count 0 2006.201.11:12:30.87#ibcon#about to read 4, iclass 11, count 0 2006.201.11:12:30.87#ibcon#read 4, iclass 11, count 0 2006.201.11:12:30.87#ibcon#about to read 5, iclass 11, count 0 2006.201.11:12:30.87#ibcon#read 5, iclass 11, count 0 2006.201.11:12:30.87#ibcon#about to read 6, iclass 11, count 0 2006.201.11:12:30.87#ibcon#read 6, iclass 11, count 0 2006.201.11:12:30.87#ibcon#end of sib2, iclass 11, count 0 2006.201.11:12:30.87#ibcon#*mode == 0, iclass 11, count 0 2006.201.11:12:30.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.11:12:30.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:12:30.87#ibcon#*before write, iclass 11, count 0 2006.201.11:12:30.87#ibcon#enter sib2, iclass 11, count 0 2006.201.11:12:30.87#ibcon#flushed, iclass 11, count 0 2006.201.11:12:30.87#ibcon#about to write, iclass 11, count 0 2006.201.11:12:30.87#ibcon#wrote, iclass 11, count 0 2006.201.11:12:30.87#ibcon#about to read 3, iclass 11, count 0 2006.201.11:12:30.91#ibcon#read 3, iclass 11, count 0 2006.201.11:12:30.91#ibcon#about to read 4, iclass 11, count 0 2006.201.11:12:30.91#ibcon#read 4, iclass 11, count 0 2006.201.11:12:30.91#ibcon#about to read 5, iclass 11, count 0 2006.201.11:12:30.91#ibcon#read 5, iclass 11, count 0 2006.201.11:12:30.91#ibcon#about to read 6, iclass 11, count 0 2006.201.11:12:30.91#ibcon#read 6, iclass 11, count 0 2006.201.11:12:30.91#ibcon#end of sib2, iclass 11, count 0 2006.201.11:12:30.91#ibcon#*after write, iclass 11, count 0 2006.201.11:12:30.91#ibcon#*before return 0, iclass 11, count 0 2006.201.11:12:30.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:30.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:12:30.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.11:12:30.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.11:12:30.91$vck44/vb=2,5 2006.201.11:12:30.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.11:12:30.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.11:12:30.91#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:30.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:30.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:30.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:30.97#ibcon#enter wrdev, iclass 13, count 2 2006.201.11:12:30.97#ibcon#first serial, iclass 13, count 2 2006.201.11:12:30.97#ibcon#enter sib2, iclass 13, count 2 2006.201.11:12:30.97#ibcon#flushed, iclass 13, count 2 2006.201.11:12:30.97#ibcon#about to write, iclass 13, count 2 2006.201.11:12:30.97#ibcon#wrote, iclass 13, count 2 2006.201.11:12:30.97#ibcon#about to read 3, iclass 13, count 2 2006.201.11:12:30.99#ibcon#read 3, iclass 13, count 2 2006.201.11:12:30.99#ibcon#about to read 4, iclass 13, count 2 2006.201.11:12:30.99#ibcon#read 4, iclass 13, count 2 2006.201.11:12:30.99#ibcon#about to read 5, iclass 13, count 2 2006.201.11:12:30.99#ibcon#read 5, iclass 13, count 2 2006.201.11:12:30.99#ibcon#about to read 6, iclass 13, count 2 2006.201.11:12:30.99#ibcon#read 6, iclass 13, count 2 2006.201.11:12:30.99#ibcon#end of sib2, iclass 13, count 2 2006.201.11:12:30.99#ibcon#*mode == 0, iclass 13, count 2 2006.201.11:12:30.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.11:12:30.99#ibcon#[27=AT02-05\r\n] 2006.201.11:12:30.99#ibcon#*before write, iclass 13, count 2 2006.201.11:12:30.99#ibcon#enter sib2, iclass 13, count 2 2006.201.11:12:30.99#ibcon#flushed, iclass 13, count 2 2006.201.11:12:30.99#ibcon#about to write, iclass 13, count 2 2006.201.11:12:30.99#ibcon#wrote, iclass 13, count 2 2006.201.11:12:30.99#ibcon#about to read 3, iclass 13, count 2 2006.201.11:12:31.02#ibcon#read 3, iclass 13, count 2 2006.201.11:12:31.02#ibcon#about to read 4, iclass 13, count 2 2006.201.11:12:31.02#ibcon#read 4, iclass 13, count 2 2006.201.11:12:31.02#ibcon#about to read 5, iclass 13, count 2 2006.201.11:12:31.02#ibcon#read 5, iclass 13, count 2 2006.201.11:12:31.02#ibcon#about to read 6, iclass 13, count 2 2006.201.11:12:31.02#ibcon#read 6, iclass 13, count 2 2006.201.11:12:31.02#ibcon#end of sib2, iclass 13, count 2 2006.201.11:12:31.02#ibcon#*after write, iclass 13, count 2 2006.201.11:12:31.02#ibcon#*before return 0, iclass 13, count 2 2006.201.11:12:31.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:31.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:12:31.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.11:12:31.02#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:31.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:31.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:31.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:31.14#ibcon#enter wrdev, iclass 13, count 0 2006.201.11:12:31.14#ibcon#first serial, iclass 13, count 0 2006.201.11:12:31.14#ibcon#enter sib2, iclass 13, count 0 2006.201.11:12:31.14#ibcon#flushed, iclass 13, count 0 2006.201.11:12:31.14#ibcon#about to write, iclass 13, count 0 2006.201.11:12:31.14#ibcon#wrote, iclass 13, count 0 2006.201.11:12:31.14#ibcon#about to read 3, iclass 13, count 0 2006.201.11:12:31.16#ibcon#read 3, iclass 13, count 0 2006.201.11:12:31.16#ibcon#about to read 4, iclass 13, count 0 2006.201.11:12:31.16#ibcon#read 4, iclass 13, count 0 2006.201.11:12:31.16#ibcon#about to read 5, iclass 13, count 0 2006.201.11:12:31.16#ibcon#read 5, iclass 13, count 0 2006.201.11:12:31.16#ibcon#about to read 6, iclass 13, count 0 2006.201.11:12:31.16#ibcon#read 6, iclass 13, count 0 2006.201.11:12:31.16#ibcon#end of sib2, iclass 13, count 0 2006.201.11:12:31.16#ibcon#*mode == 0, iclass 13, count 0 2006.201.11:12:31.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.11:12:31.16#ibcon#[27=USB\r\n] 2006.201.11:12:31.16#ibcon#*before write, iclass 13, count 0 2006.201.11:12:31.16#ibcon#enter sib2, iclass 13, count 0 2006.201.11:12:31.16#ibcon#flushed, iclass 13, count 0 2006.201.11:12:31.16#ibcon#about to write, iclass 13, count 0 2006.201.11:12:31.16#ibcon#wrote, iclass 13, count 0 2006.201.11:12:31.16#ibcon#about to read 3, iclass 13, count 0 2006.201.11:12:31.19#ibcon#read 3, iclass 13, count 0 2006.201.11:12:31.19#ibcon#about to read 4, iclass 13, count 0 2006.201.11:12:31.19#ibcon#read 4, iclass 13, count 0 2006.201.11:12:31.19#ibcon#about to read 5, iclass 13, count 0 2006.201.11:12:31.19#ibcon#read 5, iclass 13, count 0 2006.201.11:12:31.19#ibcon#about to read 6, iclass 13, count 0 2006.201.11:12:31.19#ibcon#read 6, iclass 13, count 0 2006.201.11:12:31.19#ibcon#end of sib2, iclass 13, count 0 2006.201.11:12:31.19#ibcon#*after write, iclass 13, count 0 2006.201.11:12:31.19#ibcon#*before return 0, iclass 13, count 0 2006.201.11:12:31.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:31.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:12:31.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.11:12:31.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.11:12:31.19$vck44/vblo=3,649.99 2006.201.11:12:31.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.11:12:31.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.11:12:31.19#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:31.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:31.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:31.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:31.19#ibcon#enter wrdev, iclass 15, count 0 2006.201.11:12:31.19#ibcon#first serial, iclass 15, count 0 2006.201.11:12:31.19#ibcon#enter sib2, iclass 15, count 0 2006.201.11:12:31.19#ibcon#flushed, iclass 15, count 0 2006.201.11:12:31.19#ibcon#about to write, iclass 15, count 0 2006.201.11:12:31.19#ibcon#wrote, iclass 15, count 0 2006.201.11:12:31.19#ibcon#about to read 3, iclass 15, count 0 2006.201.11:12:31.21#ibcon#read 3, iclass 15, count 0 2006.201.11:12:31.21#ibcon#about to read 4, iclass 15, count 0 2006.201.11:12:31.21#ibcon#read 4, iclass 15, count 0 2006.201.11:12:31.21#ibcon#about to read 5, iclass 15, count 0 2006.201.11:12:31.21#ibcon#read 5, iclass 15, count 0 2006.201.11:12:31.21#ibcon#about to read 6, iclass 15, count 0 2006.201.11:12:31.21#ibcon#read 6, iclass 15, count 0 2006.201.11:12:31.21#ibcon#end of sib2, iclass 15, count 0 2006.201.11:12:31.21#ibcon#*mode == 0, iclass 15, count 0 2006.201.11:12:31.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.11:12:31.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:12:31.21#ibcon#*before write, iclass 15, count 0 2006.201.11:12:31.21#ibcon#enter sib2, iclass 15, count 0 2006.201.11:12:31.21#ibcon#flushed, iclass 15, count 0 2006.201.11:12:31.21#ibcon#about to write, iclass 15, count 0 2006.201.11:12:31.21#ibcon#wrote, iclass 15, count 0 2006.201.11:12:31.21#ibcon#about to read 3, iclass 15, count 0 2006.201.11:12:31.26#ibcon#read 3, iclass 15, count 0 2006.201.11:12:31.26#ibcon#about to read 4, iclass 15, count 0 2006.201.11:12:31.26#ibcon#read 4, iclass 15, count 0 2006.201.11:12:31.26#ibcon#about to read 5, iclass 15, count 0 2006.201.11:12:31.26#ibcon#read 5, iclass 15, count 0 2006.201.11:12:31.26#ibcon#about to read 6, iclass 15, count 0 2006.201.11:12:31.26#ibcon#read 6, iclass 15, count 0 2006.201.11:12:31.26#ibcon#end of sib2, iclass 15, count 0 2006.201.11:12:31.26#ibcon#*after write, iclass 15, count 0 2006.201.11:12:31.26#ibcon#*before return 0, iclass 15, count 0 2006.201.11:12:31.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:31.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:12:31.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.11:12:31.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.11:12:31.26$vck44/vb=3,4 2006.201.11:12:31.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.11:12:31.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.11:12:31.26#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:31.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:31.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:31.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:31.31#ibcon#enter wrdev, iclass 17, count 2 2006.201.11:12:31.31#ibcon#first serial, iclass 17, count 2 2006.201.11:12:31.31#ibcon#enter sib2, iclass 17, count 2 2006.201.11:12:31.31#ibcon#flushed, iclass 17, count 2 2006.201.11:12:31.31#ibcon#about to write, iclass 17, count 2 2006.201.11:12:31.31#ibcon#wrote, iclass 17, count 2 2006.201.11:12:31.31#ibcon#about to read 3, iclass 17, count 2 2006.201.11:12:31.33#ibcon#read 3, iclass 17, count 2 2006.201.11:12:31.33#ibcon#about to read 4, iclass 17, count 2 2006.201.11:12:31.33#ibcon#read 4, iclass 17, count 2 2006.201.11:12:31.33#ibcon#about to read 5, iclass 17, count 2 2006.201.11:12:31.33#ibcon#read 5, iclass 17, count 2 2006.201.11:12:31.33#ibcon#about to read 6, iclass 17, count 2 2006.201.11:12:31.33#ibcon#read 6, iclass 17, count 2 2006.201.11:12:31.33#ibcon#end of sib2, iclass 17, count 2 2006.201.11:12:31.33#ibcon#*mode == 0, iclass 17, count 2 2006.201.11:12:31.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.11:12:31.33#ibcon#[27=AT03-04\r\n] 2006.201.11:12:31.33#ibcon#*before write, iclass 17, count 2 2006.201.11:12:31.33#ibcon#enter sib2, iclass 17, count 2 2006.201.11:12:31.33#ibcon#flushed, iclass 17, count 2 2006.201.11:12:31.33#ibcon#about to write, iclass 17, count 2 2006.201.11:12:31.33#ibcon#wrote, iclass 17, count 2 2006.201.11:12:31.33#ibcon#about to read 3, iclass 17, count 2 2006.201.11:12:31.36#ibcon#read 3, iclass 17, count 2 2006.201.11:12:31.36#ibcon#about to read 4, iclass 17, count 2 2006.201.11:12:31.36#ibcon#read 4, iclass 17, count 2 2006.201.11:12:31.36#ibcon#about to read 5, iclass 17, count 2 2006.201.11:12:31.36#ibcon#read 5, iclass 17, count 2 2006.201.11:12:31.36#ibcon#about to read 6, iclass 17, count 2 2006.201.11:12:31.36#ibcon#read 6, iclass 17, count 2 2006.201.11:12:31.36#ibcon#end of sib2, iclass 17, count 2 2006.201.11:12:31.36#ibcon#*after write, iclass 17, count 2 2006.201.11:12:31.36#ibcon#*before return 0, iclass 17, count 2 2006.201.11:12:31.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:31.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:12:31.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.11:12:31.36#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:31.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:31.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:31.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:31.48#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:12:31.48#ibcon#first serial, iclass 17, count 0 2006.201.11:12:31.48#ibcon#enter sib2, iclass 17, count 0 2006.201.11:12:31.48#ibcon#flushed, iclass 17, count 0 2006.201.11:12:31.48#ibcon#about to write, iclass 17, count 0 2006.201.11:12:31.48#ibcon#wrote, iclass 17, count 0 2006.201.11:12:31.48#ibcon#about to read 3, iclass 17, count 0 2006.201.11:12:31.50#ibcon#read 3, iclass 17, count 0 2006.201.11:12:31.50#ibcon#about to read 4, iclass 17, count 0 2006.201.11:12:31.50#ibcon#read 4, iclass 17, count 0 2006.201.11:12:31.50#ibcon#about to read 5, iclass 17, count 0 2006.201.11:12:31.50#ibcon#read 5, iclass 17, count 0 2006.201.11:12:31.50#ibcon#about to read 6, iclass 17, count 0 2006.201.11:12:31.50#ibcon#read 6, iclass 17, count 0 2006.201.11:12:31.50#ibcon#end of sib2, iclass 17, count 0 2006.201.11:12:31.50#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:12:31.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:12:31.50#ibcon#[27=USB\r\n] 2006.201.11:12:31.50#ibcon#*before write, iclass 17, count 0 2006.201.11:12:31.50#ibcon#enter sib2, iclass 17, count 0 2006.201.11:12:31.50#ibcon#flushed, iclass 17, count 0 2006.201.11:12:31.50#ibcon#about to write, iclass 17, count 0 2006.201.11:12:31.50#ibcon#wrote, iclass 17, count 0 2006.201.11:12:31.50#ibcon#about to read 3, iclass 17, count 0 2006.201.11:12:31.53#ibcon#read 3, iclass 17, count 0 2006.201.11:12:31.53#ibcon#about to read 4, iclass 17, count 0 2006.201.11:12:31.53#ibcon#read 4, iclass 17, count 0 2006.201.11:12:31.53#ibcon#about to read 5, iclass 17, count 0 2006.201.11:12:31.53#ibcon#read 5, iclass 17, count 0 2006.201.11:12:31.53#ibcon#about to read 6, iclass 17, count 0 2006.201.11:12:31.53#ibcon#read 6, iclass 17, count 0 2006.201.11:12:31.53#ibcon#end of sib2, iclass 17, count 0 2006.201.11:12:31.53#ibcon#*after write, iclass 17, count 0 2006.201.11:12:31.53#ibcon#*before return 0, iclass 17, count 0 2006.201.11:12:31.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:31.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:12:31.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:12:31.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:12:31.53$vck44/vblo=4,679.99 2006.201.11:12:31.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.11:12:31.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.11:12:31.53#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:31.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:31.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:31.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:31.53#ibcon#enter wrdev, iclass 19, count 0 2006.201.11:12:31.53#ibcon#first serial, iclass 19, count 0 2006.201.11:12:31.53#ibcon#enter sib2, iclass 19, count 0 2006.201.11:12:31.53#ibcon#flushed, iclass 19, count 0 2006.201.11:12:31.53#ibcon#about to write, iclass 19, count 0 2006.201.11:12:31.53#ibcon#wrote, iclass 19, count 0 2006.201.11:12:31.53#ibcon#about to read 3, iclass 19, count 0 2006.201.11:12:31.55#ibcon#read 3, iclass 19, count 0 2006.201.11:12:31.55#ibcon#about to read 4, iclass 19, count 0 2006.201.11:12:31.55#ibcon#read 4, iclass 19, count 0 2006.201.11:12:31.55#ibcon#about to read 5, iclass 19, count 0 2006.201.11:12:31.55#ibcon#read 5, iclass 19, count 0 2006.201.11:12:31.55#ibcon#about to read 6, iclass 19, count 0 2006.201.11:12:31.55#ibcon#read 6, iclass 19, count 0 2006.201.11:12:31.55#ibcon#end of sib2, iclass 19, count 0 2006.201.11:12:31.55#ibcon#*mode == 0, iclass 19, count 0 2006.201.11:12:31.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.11:12:31.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:12:31.55#ibcon#*before write, iclass 19, count 0 2006.201.11:12:31.55#ibcon#enter sib2, iclass 19, count 0 2006.201.11:12:31.55#ibcon#flushed, iclass 19, count 0 2006.201.11:12:31.55#ibcon#about to write, iclass 19, count 0 2006.201.11:12:31.55#ibcon#wrote, iclass 19, count 0 2006.201.11:12:31.55#ibcon#about to read 3, iclass 19, count 0 2006.201.11:12:31.60#ibcon#read 3, iclass 19, count 0 2006.201.11:12:31.60#ibcon#about to read 4, iclass 19, count 0 2006.201.11:12:31.60#ibcon#read 4, iclass 19, count 0 2006.201.11:12:31.60#ibcon#about to read 5, iclass 19, count 0 2006.201.11:12:31.60#ibcon#read 5, iclass 19, count 0 2006.201.11:12:31.60#ibcon#about to read 6, iclass 19, count 0 2006.201.11:12:31.60#ibcon#read 6, iclass 19, count 0 2006.201.11:12:31.60#ibcon#end of sib2, iclass 19, count 0 2006.201.11:12:31.60#ibcon#*after write, iclass 19, count 0 2006.201.11:12:31.60#ibcon#*before return 0, iclass 19, count 0 2006.201.11:12:31.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:31.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:12:31.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.11:12:31.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.11:12:31.60$vck44/vb=4,5 2006.201.11:12:31.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.11:12:31.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.11:12:31.60#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:31.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:31.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:31.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:31.65#ibcon#enter wrdev, iclass 21, count 2 2006.201.11:12:31.65#ibcon#first serial, iclass 21, count 2 2006.201.11:12:31.65#ibcon#enter sib2, iclass 21, count 2 2006.201.11:12:31.65#ibcon#flushed, iclass 21, count 2 2006.201.11:12:31.65#ibcon#about to write, iclass 21, count 2 2006.201.11:12:31.65#ibcon#wrote, iclass 21, count 2 2006.201.11:12:31.65#ibcon#about to read 3, iclass 21, count 2 2006.201.11:12:31.67#ibcon#read 3, iclass 21, count 2 2006.201.11:12:31.67#ibcon#about to read 4, iclass 21, count 2 2006.201.11:12:31.67#ibcon#read 4, iclass 21, count 2 2006.201.11:12:31.67#ibcon#about to read 5, iclass 21, count 2 2006.201.11:12:31.67#ibcon#read 5, iclass 21, count 2 2006.201.11:12:31.67#ibcon#about to read 6, iclass 21, count 2 2006.201.11:12:31.67#ibcon#read 6, iclass 21, count 2 2006.201.11:12:31.67#ibcon#end of sib2, iclass 21, count 2 2006.201.11:12:31.67#ibcon#*mode == 0, iclass 21, count 2 2006.201.11:12:31.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.11:12:31.67#ibcon#[27=AT04-05\r\n] 2006.201.11:12:31.67#ibcon#*before write, iclass 21, count 2 2006.201.11:12:31.67#ibcon#enter sib2, iclass 21, count 2 2006.201.11:12:31.67#ibcon#flushed, iclass 21, count 2 2006.201.11:12:31.67#ibcon#about to write, iclass 21, count 2 2006.201.11:12:31.67#ibcon#wrote, iclass 21, count 2 2006.201.11:12:31.67#ibcon#about to read 3, iclass 21, count 2 2006.201.11:12:31.70#ibcon#read 3, iclass 21, count 2 2006.201.11:12:31.70#ibcon#about to read 4, iclass 21, count 2 2006.201.11:12:31.70#ibcon#read 4, iclass 21, count 2 2006.201.11:12:31.70#ibcon#about to read 5, iclass 21, count 2 2006.201.11:12:31.70#ibcon#read 5, iclass 21, count 2 2006.201.11:12:31.70#ibcon#about to read 6, iclass 21, count 2 2006.201.11:12:31.70#ibcon#read 6, iclass 21, count 2 2006.201.11:12:31.70#ibcon#end of sib2, iclass 21, count 2 2006.201.11:12:31.70#ibcon#*after write, iclass 21, count 2 2006.201.11:12:31.70#ibcon#*before return 0, iclass 21, count 2 2006.201.11:12:31.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:31.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:12:31.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.11:12:31.70#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:31.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:31.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:31.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:31.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.11:12:31.82#ibcon#first serial, iclass 21, count 0 2006.201.11:12:31.82#ibcon#enter sib2, iclass 21, count 0 2006.201.11:12:31.82#ibcon#flushed, iclass 21, count 0 2006.201.11:12:31.82#ibcon#about to write, iclass 21, count 0 2006.201.11:12:31.82#ibcon#wrote, iclass 21, count 0 2006.201.11:12:31.82#ibcon#about to read 3, iclass 21, count 0 2006.201.11:12:31.84#ibcon#read 3, iclass 21, count 0 2006.201.11:12:31.84#ibcon#about to read 4, iclass 21, count 0 2006.201.11:12:31.84#ibcon#read 4, iclass 21, count 0 2006.201.11:12:31.84#ibcon#about to read 5, iclass 21, count 0 2006.201.11:12:31.84#ibcon#read 5, iclass 21, count 0 2006.201.11:12:31.84#ibcon#about to read 6, iclass 21, count 0 2006.201.11:12:31.84#ibcon#read 6, iclass 21, count 0 2006.201.11:12:31.84#ibcon#end of sib2, iclass 21, count 0 2006.201.11:12:31.84#ibcon#*mode == 0, iclass 21, count 0 2006.201.11:12:31.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.11:12:31.84#ibcon#[27=USB\r\n] 2006.201.11:12:31.84#ibcon#*before write, iclass 21, count 0 2006.201.11:12:31.84#ibcon#enter sib2, iclass 21, count 0 2006.201.11:12:31.84#ibcon#flushed, iclass 21, count 0 2006.201.11:12:31.84#ibcon#about to write, iclass 21, count 0 2006.201.11:12:31.84#ibcon#wrote, iclass 21, count 0 2006.201.11:12:31.84#ibcon#about to read 3, iclass 21, count 0 2006.201.11:12:31.87#ibcon#read 3, iclass 21, count 0 2006.201.11:12:31.87#ibcon#about to read 4, iclass 21, count 0 2006.201.11:12:31.87#ibcon#read 4, iclass 21, count 0 2006.201.11:12:31.87#ibcon#about to read 5, iclass 21, count 0 2006.201.11:12:31.87#ibcon#read 5, iclass 21, count 0 2006.201.11:12:31.87#ibcon#about to read 6, iclass 21, count 0 2006.201.11:12:31.87#ibcon#read 6, iclass 21, count 0 2006.201.11:12:31.87#ibcon#end of sib2, iclass 21, count 0 2006.201.11:12:31.87#ibcon#*after write, iclass 21, count 0 2006.201.11:12:31.87#ibcon#*before return 0, iclass 21, count 0 2006.201.11:12:31.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:31.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:12:31.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.11:12:31.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.11:12:31.87$vck44/vblo=5,709.99 2006.201.11:12:31.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.11:12:31.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.11:12:31.87#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:31.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:31.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:31.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:31.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.11:12:31.87#ibcon#first serial, iclass 23, count 0 2006.201.11:12:31.87#ibcon#enter sib2, iclass 23, count 0 2006.201.11:12:31.87#ibcon#flushed, iclass 23, count 0 2006.201.11:12:31.87#ibcon#about to write, iclass 23, count 0 2006.201.11:12:31.87#ibcon#wrote, iclass 23, count 0 2006.201.11:12:31.87#ibcon#about to read 3, iclass 23, count 0 2006.201.11:12:31.89#ibcon#read 3, iclass 23, count 0 2006.201.11:12:31.89#ibcon#about to read 4, iclass 23, count 0 2006.201.11:12:31.89#ibcon#read 4, iclass 23, count 0 2006.201.11:12:31.89#ibcon#about to read 5, iclass 23, count 0 2006.201.11:12:31.89#ibcon#read 5, iclass 23, count 0 2006.201.11:12:31.89#ibcon#about to read 6, iclass 23, count 0 2006.201.11:12:31.89#ibcon#read 6, iclass 23, count 0 2006.201.11:12:31.89#ibcon#end of sib2, iclass 23, count 0 2006.201.11:12:31.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.11:12:31.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.11:12:31.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:12:31.89#ibcon#*before write, iclass 23, count 0 2006.201.11:12:31.89#ibcon#enter sib2, iclass 23, count 0 2006.201.11:12:31.89#ibcon#flushed, iclass 23, count 0 2006.201.11:12:31.89#ibcon#about to write, iclass 23, count 0 2006.201.11:12:31.89#ibcon#wrote, iclass 23, count 0 2006.201.11:12:31.89#ibcon#about to read 3, iclass 23, count 0 2006.201.11:12:31.93#ibcon#read 3, iclass 23, count 0 2006.201.11:12:31.93#ibcon#about to read 4, iclass 23, count 0 2006.201.11:12:31.93#ibcon#read 4, iclass 23, count 0 2006.201.11:12:31.93#ibcon#about to read 5, iclass 23, count 0 2006.201.11:12:31.93#ibcon#read 5, iclass 23, count 0 2006.201.11:12:31.93#ibcon#about to read 6, iclass 23, count 0 2006.201.11:12:31.93#ibcon#read 6, iclass 23, count 0 2006.201.11:12:31.93#ibcon#end of sib2, iclass 23, count 0 2006.201.11:12:31.93#ibcon#*after write, iclass 23, count 0 2006.201.11:12:31.93#ibcon#*before return 0, iclass 23, count 0 2006.201.11:12:31.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:31.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:12:31.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.11:12:31.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.11:12:31.93$vck44/vb=5,4 2006.201.11:12:31.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.11:12:31.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.11:12:31.93#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:31.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:31.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:31.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:31.99#ibcon#enter wrdev, iclass 25, count 2 2006.201.11:12:31.99#ibcon#first serial, iclass 25, count 2 2006.201.11:12:31.99#ibcon#enter sib2, iclass 25, count 2 2006.201.11:12:31.99#ibcon#flushed, iclass 25, count 2 2006.201.11:12:31.99#ibcon#about to write, iclass 25, count 2 2006.201.11:12:31.99#ibcon#wrote, iclass 25, count 2 2006.201.11:12:31.99#ibcon#about to read 3, iclass 25, count 2 2006.201.11:12:32.01#ibcon#read 3, iclass 25, count 2 2006.201.11:12:32.01#ibcon#about to read 4, iclass 25, count 2 2006.201.11:12:32.01#ibcon#read 4, iclass 25, count 2 2006.201.11:12:32.01#ibcon#about to read 5, iclass 25, count 2 2006.201.11:12:32.01#ibcon#read 5, iclass 25, count 2 2006.201.11:12:32.01#ibcon#about to read 6, iclass 25, count 2 2006.201.11:12:32.01#ibcon#read 6, iclass 25, count 2 2006.201.11:12:32.01#ibcon#end of sib2, iclass 25, count 2 2006.201.11:12:32.01#ibcon#*mode == 0, iclass 25, count 2 2006.201.11:12:32.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.11:12:32.01#ibcon#[27=AT05-04\r\n] 2006.201.11:12:32.01#ibcon#*before write, iclass 25, count 2 2006.201.11:12:32.01#ibcon#enter sib2, iclass 25, count 2 2006.201.11:12:32.01#ibcon#flushed, iclass 25, count 2 2006.201.11:12:32.01#ibcon#about to write, iclass 25, count 2 2006.201.11:12:32.01#ibcon#wrote, iclass 25, count 2 2006.201.11:12:32.01#ibcon#about to read 3, iclass 25, count 2 2006.201.11:12:32.04#ibcon#read 3, iclass 25, count 2 2006.201.11:12:32.04#ibcon#about to read 4, iclass 25, count 2 2006.201.11:12:32.04#ibcon#read 4, iclass 25, count 2 2006.201.11:12:32.04#ibcon#about to read 5, iclass 25, count 2 2006.201.11:12:32.04#ibcon#read 5, iclass 25, count 2 2006.201.11:12:32.04#ibcon#about to read 6, iclass 25, count 2 2006.201.11:12:32.04#ibcon#read 6, iclass 25, count 2 2006.201.11:12:32.04#ibcon#end of sib2, iclass 25, count 2 2006.201.11:12:32.04#ibcon#*after write, iclass 25, count 2 2006.201.11:12:32.04#ibcon#*before return 0, iclass 25, count 2 2006.201.11:12:32.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:32.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:12:32.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.11:12:32.04#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:32.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:32.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:32.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:32.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.11:12:32.16#ibcon#first serial, iclass 25, count 0 2006.201.11:12:32.16#ibcon#enter sib2, iclass 25, count 0 2006.201.11:12:32.16#ibcon#flushed, iclass 25, count 0 2006.201.11:12:32.16#ibcon#about to write, iclass 25, count 0 2006.201.11:12:32.16#ibcon#wrote, iclass 25, count 0 2006.201.11:12:32.16#ibcon#about to read 3, iclass 25, count 0 2006.201.11:12:32.18#ibcon#read 3, iclass 25, count 0 2006.201.11:12:32.18#ibcon#about to read 4, iclass 25, count 0 2006.201.11:12:32.18#ibcon#read 4, iclass 25, count 0 2006.201.11:12:32.18#ibcon#about to read 5, iclass 25, count 0 2006.201.11:12:32.18#ibcon#read 5, iclass 25, count 0 2006.201.11:12:32.18#ibcon#about to read 6, iclass 25, count 0 2006.201.11:12:32.18#ibcon#read 6, iclass 25, count 0 2006.201.11:12:32.18#ibcon#end of sib2, iclass 25, count 0 2006.201.11:12:32.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.11:12:32.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.11:12:32.18#ibcon#[27=USB\r\n] 2006.201.11:12:32.18#ibcon#*before write, iclass 25, count 0 2006.201.11:12:32.18#ibcon#enter sib2, iclass 25, count 0 2006.201.11:12:32.18#ibcon#flushed, iclass 25, count 0 2006.201.11:12:32.18#ibcon#about to write, iclass 25, count 0 2006.201.11:12:32.18#ibcon#wrote, iclass 25, count 0 2006.201.11:12:32.18#ibcon#about to read 3, iclass 25, count 0 2006.201.11:12:32.21#ibcon#read 3, iclass 25, count 0 2006.201.11:12:32.21#ibcon#about to read 4, iclass 25, count 0 2006.201.11:12:32.21#ibcon#read 4, iclass 25, count 0 2006.201.11:12:32.21#ibcon#about to read 5, iclass 25, count 0 2006.201.11:12:32.21#ibcon#read 5, iclass 25, count 0 2006.201.11:12:32.21#ibcon#about to read 6, iclass 25, count 0 2006.201.11:12:32.21#ibcon#read 6, iclass 25, count 0 2006.201.11:12:32.21#ibcon#end of sib2, iclass 25, count 0 2006.201.11:12:32.21#ibcon#*after write, iclass 25, count 0 2006.201.11:12:32.21#ibcon#*before return 0, iclass 25, count 0 2006.201.11:12:32.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:32.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:12:32.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.11:12:32.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.11:12:32.21$vck44/vblo=6,719.99 2006.201.11:12:32.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.11:12:32.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.11:12:32.21#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:32.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:32.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:32.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:32.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.11:12:32.21#ibcon#first serial, iclass 27, count 0 2006.201.11:12:32.21#ibcon#enter sib2, iclass 27, count 0 2006.201.11:12:32.21#ibcon#flushed, iclass 27, count 0 2006.201.11:12:32.21#ibcon#about to write, iclass 27, count 0 2006.201.11:12:32.21#ibcon#wrote, iclass 27, count 0 2006.201.11:12:32.21#ibcon#about to read 3, iclass 27, count 0 2006.201.11:12:32.23#ibcon#read 3, iclass 27, count 0 2006.201.11:12:32.23#ibcon#about to read 4, iclass 27, count 0 2006.201.11:12:32.23#ibcon#read 4, iclass 27, count 0 2006.201.11:12:32.23#ibcon#about to read 5, iclass 27, count 0 2006.201.11:12:32.23#ibcon#read 5, iclass 27, count 0 2006.201.11:12:32.23#ibcon#about to read 6, iclass 27, count 0 2006.201.11:12:32.23#ibcon#read 6, iclass 27, count 0 2006.201.11:12:32.23#ibcon#end of sib2, iclass 27, count 0 2006.201.11:12:32.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.11:12:32.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.11:12:32.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:12:32.23#ibcon#*before write, iclass 27, count 0 2006.201.11:12:32.23#ibcon#enter sib2, iclass 27, count 0 2006.201.11:12:32.23#ibcon#flushed, iclass 27, count 0 2006.201.11:12:32.23#ibcon#about to write, iclass 27, count 0 2006.201.11:12:32.23#ibcon#wrote, iclass 27, count 0 2006.201.11:12:32.23#ibcon#about to read 3, iclass 27, count 0 2006.201.11:12:32.27#ibcon#read 3, iclass 27, count 0 2006.201.11:12:32.27#ibcon#about to read 4, iclass 27, count 0 2006.201.11:12:32.27#ibcon#read 4, iclass 27, count 0 2006.201.11:12:32.27#ibcon#about to read 5, iclass 27, count 0 2006.201.11:12:32.27#ibcon#read 5, iclass 27, count 0 2006.201.11:12:32.27#ibcon#about to read 6, iclass 27, count 0 2006.201.11:12:32.27#ibcon#read 6, iclass 27, count 0 2006.201.11:12:32.27#ibcon#end of sib2, iclass 27, count 0 2006.201.11:12:32.27#ibcon#*after write, iclass 27, count 0 2006.201.11:12:32.27#ibcon#*before return 0, iclass 27, count 0 2006.201.11:12:32.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:32.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:12:32.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.11:12:32.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.11:12:32.27$vck44/vb=6,4 2006.201.11:12:32.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.11:12:32.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.11:12:32.27#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:32.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:32.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:32.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:32.33#ibcon#enter wrdev, iclass 29, count 2 2006.201.11:12:32.33#ibcon#first serial, iclass 29, count 2 2006.201.11:12:32.33#ibcon#enter sib2, iclass 29, count 2 2006.201.11:12:32.33#ibcon#flushed, iclass 29, count 2 2006.201.11:12:32.33#ibcon#about to write, iclass 29, count 2 2006.201.11:12:32.33#ibcon#wrote, iclass 29, count 2 2006.201.11:12:32.33#ibcon#about to read 3, iclass 29, count 2 2006.201.11:12:32.35#ibcon#read 3, iclass 29, count 2 2006.201.11:12:32.35#ibcon#about to read 4, iclass 29, count 2 2006.201.11:12:32.35#ibcon#read 4, iclass 29, count 2 2006.201.11:12:32.35#ibcon#about to read 5, iclass 29, count 2 2006.201.11:12:32.35#ibcon#read 5, iclass 29, count 2 2006.201.11:12:32.35#ibcon#about to read 6, iclass 29, count 2 2006.201.11:12:32.35#ibcon#read 6, iclass 29, count 2 2006.201.11:12:32.35#ibcon#end of sib2, iclass 29, count 2 2006.201.11:12:32.35#ibcon#*mode == 0, iclass 29, count 2 2006.201.11:12:32.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.11:12:32.35#ibcon#[27=AT06-04\r\n] 2006.201.11:12:32.35#ibcon#*before write, iclass 29, count 2 2006.201.11:12:32.35#ibcon#enter sib2, iclass 29, count 2 2006.201.11:12:32.35#ibcon#flushed, iclass 29, count 2 2006.201.11:12:32.35#ibcon#about to write, iclass 29, count 2 2006.201.11:12:32.35#ibcon#wrote, iclass 29, count 2 2006.201.11:12:32.35#ibcon#about to read 3, iclass 29, count 2 2006.201.11:12:32.38#ibcon#read 3, iclass 29, count 2 2006.201.11:12:32.38#ibcon#about to read 4, iclass 29, count 2 2006.201.11:12:32.38#ibcon#read 4, iclass 29, count 2 2006.201.11:12:32.38#ibcon#about to read 5, iclass 29, count 2 2006.201.11:12:32.38#ibcon#read 5, iclass 29, count 2 2006.201.11:12:32.38#ibcon#about to read 6, iclass 29, count 2 2006.201.11:12:32.38#ibcon#read 6, iclass 29, count 2 2006.201.11:12:32.38#ibcon#end of sib2, iclass 29, count 2 2006.201.11:12:32.38#ibcon#*after write, iclass 29, count 2 2006.201.11:12:32.38#ibcon#*before return 0, iclass 29, count 2 2006.201.11:12:32.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:32.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:12:32.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.11:12:32.38#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:32.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:32.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:32.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:32.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.11:12:32.50#ibcon#first serial, iclass 29, count 0 2006.201.11:12:32.50#ibcon#enter sib2, iclass 29, count 0 2006.201.11:12:32.50#ibcon#flushed, iclass 29, count 0 2006.201.11:12:32.50#ibcon#about to write, iclass 29, count 0 2006.201.11:12:32.50#ibcon#wrote, iclass 29, count 0 2006.201.11:12:32.50#ibcon#about to read 3, iclass 29, count 0 2006.201.11:12:32.52#ibcon#read 3, iclass 29, count 0 2006.201.11:12:32.52#ibcon#about to read 4, iclass 29, count 0 2006.201.11:12:32.52#ibcon#read 4, iclass 29, count 0 2006.201.11:12:32.52#ibcon#about to read 5, iclass 29, count 0 2006.201.11:12:32.52#ibcon#read 5, iclass 29, count 0 2006.201.11:12:32.52#ibcon#about to read 6, iclass 29, count 0 2006.201.11:12:32.52#ibcon#read 6, iclass 29, count 0 2006.201.11:12:32.52#ibcon#end of sib2, iclass 29, count 0 2006.201.11:12:32.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.11:12:32.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.11:12:32.52#ibcon#[27=USB\r\n] 2006.201.11:12:32.52#ibcon#*before write, iclass 29, count 0 2006.201.11:12:32.52#ibcon#enter sib2, iclass 29, count 0 2006.201.11:12:32.52#ibcon#flushed, iclass 29, count 0 2006.201.11:12:32.52#ibcon#about to write, iclass 29, count 0 2006.201.11:12:32.52#ibcon#wrote, iclass 29, count 0 2006.201.11:12:32.52#ibcon#about to read 3, iclass 29, count 0 2006.201.11:12:32.55#ibcon#read 3, iclass 29, count 0 2006.201.11:12:32.55#ibcon#about to read 4, iclass 29, count 0 2006.201.11:12:32.55#ibcon#read 4, iclass 29, count 0 2006.201.11:12:32.55#ibcon#about to read 5, iclass 29, count 0 2006.201.11:12:32.55#ibcon#read 5, iclass 29, count 0 2006.201.11:12:32.55#ibcon#about to read 6, iclass 29, count 0 2006.201.11:12:32.55#ibcon#read 6, iclass 29, count 0 2006.201.11:12:32.55#ibcon#end of sib2, iclass 29, count 0 2006.201.11:12:32.55#ibcon#*after write, iclass 29, count 0 2006.201.11:12:32.55#ibcon#*before return 0, iclass 29, count 0 2006.201.11:12:32.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:32.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:12:32.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.11:12:32.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.11:12:32.55$vck44/vblo=7,734.99 2006.201.11:12:32.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.11:12:32.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.11:12:32.55#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:32.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:32.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:32.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:32.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.11:12:32.55#ibcon#first serial, iclass 31, count 0 2006.201.11:12:32.55#ibcon#enter sib2, iclass 31, count 0 2006.201.11:12:32.55#ibcon#flushed, iclass 31, count 0 2006.201.11:12:32.55#ibcon#about to write, iclass 31, count 0 2006.201.11:12:32.55#ibcon#wrote, iclass 31, count 0 2006.201.11:12:32.55#ibcon#about to read 3, iclass 31, count 0 2006.201.11:12:32.57#ibcon#read 3, iclass 31, count 0 2006.201.11:12:32.57#ibcon#about to read 4, iclass 31, count 0 2006.201.11:12:32.57#ibcon#read 4, iclass 31, count 0 2006.201.11:12:32.57#ibcon#about to read 5, iclass 31, count 0 2006.201.11:12:32.57#ibcon#read 5, iclass 31, count 0 2006.201.11:12:32.57#ibcon#about to read 6, iclass 31, count 0 2006.201.11:12:32.57#ibcon#read 6, iclass 31, count 0 2006.201.11:12:32.57#ibcon#end of sib2, iclass 31, count 0 2006.201.11:12:32.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.11:12:32.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.11:12:32.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:12:32.57#ibcon#*before write, iclass 31, count 0 2006.201.11:12:32.57#ibcon#enter sib2, iclass 31, count 0 2006.201.11:12:32.57#ibcon#flushed, iclass 31, count 0 2006.201.11:12:32.57#ibcon#about to write, iclass 31, count 0 2006.201.11:12:32.57#ibcon#wrote, iclass 31, count 0 2006.201.11:12:32.57#ibcon#about to read 3, iclass 31, count 0 2006.201.11:12:32.61#ibcon#read 3, iclass 31, count 0 2006.201.11:12:32.61#ibcon#about to read 4, iclass 31, count 0 2006.201.11:12:32.61#ibcon#read 4, iclass 31, count 0 2006.201.11:12:32.61#ibcon#about to read 5, iclass 31, count 0 2006.201.11:12:32.61#ibcon#read 5, iclass 31, count 0 2006.201.11:12:32.61#ibcon#about to read 6, iclass 31, count 0 2006.201.11:12:32.61#ibcon#read 6, iclass 31, count 0 2006.201.11:12:32.61#ibcon#end of sib2, iclass 31, count 0 2006.201.11:12:32.61#ibcon#*after write, iclass 31, count 0 2006.201.11:12:32.61#ibcon#*before return 0, iclass 31, count 0 2006.201.11:12:32.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:32.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:12:32.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.11:12:32.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.11:12:32.61$vck44/vb=7,4 2006.201.11:12:32.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.11:12:32.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.11:12:32.61#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:32.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:32.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:32.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:32.67#ibcon#enter wrdev, iclass 33, count 2 2006.201.11:12:32.67#ibcon#first serial, iclass 33, count 2 2006.201.11:12:32.67#ibcon#enter sib2, iclass 33, count 2 2006.201.11:12:32.67#ibcon#flushed, iclass 33, count 2 2006.201.11:12:32.67#ibcon#about to write, iclass 33, count 2 2006.201.11:12:32.67#ibcon#wrote, iclass 33, count 2 2006.201.11:12:32.67#ibcon#about to read 3, iclass 33, count 2 2006.201.11:12:32.69#ibcon#read 3, iclass 33, count 2 2006.201.11:12:32.69#ibcon#about to read 4, iclass 33, count 2 2006.201.11:12:32.69#ibcon#read 4, iclass 33, count 2 2006.201.11:12:32.69#ibcon#about to read 5, iclass 33, count 2 2006.201.11:12:32.69#ibcon#read 5, iclass 33, count 2 2006.201.11:12:32.69#ibcon#about to read 6, iclass 33, count 2 2006.201.11:12:32.69#ibcon#read 6, iclass 33, count 2 2006.201.11:12:32.69#ibcon#end of sib2, iclass 33, count 2 2006.201.11:12:32.69#ibcon#*mode == 0, iclass 33, count 2 2006.201.11:12:32.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.11:12:32.69#ibcon#[27=AT07-04\r\n] 2006.201.11:12:32.69#ibcon#*before write, iclass 33, count 2 2006.201.11:12:32.69#ibcon#enter sib2, iclass 33, count 2 2006.201.11:12:32.69#ibcon#flushed, iclass 33, count 2 2006.201.11:12:32.69#ibcon#about to write, iclass 33, count 2 2006.201.11:12:32.69#ibcon#wrote, iclass 33, count 2 2006.201.11:12:32.69#ibcon#about to read 3, iclass 33, count 2 2006.201.11:12:32.72#ibcon#read 3, iclass 33, count 2 2006.201.11:12:32.72#ibcon#about to read 4, iclass 33, count 2 2006.201.11:12:32.72#ibcon#read 4, iclass 33, count 2 2006.201.11:12:32.72#ibcon#about to read 5, iclass 33, count 2 2006.201.11:12:32.72#ibcon#read 5, iclass 33, count 2 2006.201.11:12:32.72#ibcon#about to read 6, iclass 33, count 2 2006.201.11:12:32.72#ibcon#read 6, iclass 33, count 2 2006.201.11:12:32.72#ibcon#end of sib2, iclass 33, count 2 2006.201.11:12:32.72#ibcon#*after write, iclass 33, count 2 2006.201.11:12:32.72#ibcon#*before return 0, iclass 33, count 2 2006.201.11:12:32.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:32.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:12:32.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.11:12:32.72#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:32.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:32.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:32.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:32.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.11:12:32.84#ibcon#first serial, iclass 33, count 0 2006.201.11:12:32.84#ibcon#enter sib2, iclass 33, count 0 2006.201.11:12:32.84#ibcon#flushed, iclass 33, count 0 2006.201.11:12:32.84#ibcon#about to write, iclass 33, count 0 2006.201.11:12:32.84#ibcon#wrote, iclass 33, count 0 2006.201.11:12:32.84#ibcon#about to read 3, iclass 33, count 0 2006.201.11:12:32.86#ibcon#read 3, iclass 33, count 0 2006.201.11:12:32.86#ibcon#about to read 4, iclass 33, count 0 2006.201.11:12:32.86#ibcon#read 4, iclass 33, count 0 2006.201.11:12:32.86#ibcon#about to read 5, iclass 33, count 0 2006.201.11:12:32.86#ibcon#read 5, iclass 33, count 0 2006.201.11:12:32.86#ibcon#about to read 6, iclass 33, count 0 2006.201.11:12:32.86#ibcon#read 6, iclass 33, count 0 2006.201.11:12:32.86#ibcon#end of sib2, iclass 33, count 0 2006.201.11:12:32.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.11:12:32.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.11:12:32.86#ibcon#[27=USB\r\n] 2006.201.11:12:32.86#ibcon#*before write, iclass 33, count 0 2006.201.11:12:32.86#ibcon#enter sib2, iclass 33, count 0 2006.201.11:12:32.86#ibcon#flushed, iclass 33, count 0 2006.201.11:12:32.86#ibcon#about to write, iclass 33, count 0 2006.201.11:12:32.86#ibcon#wrote, iclass 33, count 0 2006.201.11:12:32.86#ibcon#about to read 3, iclass 33, count 0 2006.201.11:12:32.89#ibcon#read 3, iclass 33, count 0 2006.201.11:12:32.89#ibcon#about to read 4, iclass 33, count 0 2006.201.11:12:32.89#ibcon#read 4, iclass 33, count 0 2006.201.11:12:32.89#ibcon#about to read 5, iclass 33, count 0 2006.201.11:12:32.89#ibcon#read 5, iclass 33, count 0 2006.201.11:12:32.89#ibcon#about to read 6, iclass 33, count 0 2006.201.11:12:32.89#ibcon#read 6, iclass 33, count 0 2006.201.11:12:32.89#ibcon#end of sib2, iclass 33, count 0 2006.201.11:12:32.89#ibcon#*after write, iclass 33, count 0 2006.201.11:12:32.89#ibcon#*before return 0, iclass 33, count 0 2006.201.11:12:32.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:32.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:12:32.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.11:12:32.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.11:12:32.89$vck44/vblo=8,744.99 2006.201.11:12:32.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.11:12:32.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.11:12:32.89#ibcon#ireg 17 cls_cnt 0 2006.201.11:12:32.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:32.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:32.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:32.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.11:12:32.89#ibcon#first serial, iclass 35, count 0 2006.201.11:12:32.89#ibcon#enter sib2, iclass 35, count 0 2006.201.11:12:32.89#ibcon#flushed, iclass 35, count 0 2006.201.11:12:32.89#ibcon#about to write, iclass 35, count 0 2006.201.11:12:32.89#ibcon#wrote, iclass 35, count 0 2006.201.11:12:32.89#ibcon#about to read 3, iclass 35, count 0 2006.201.11:12:32.91#ibcon#read 3, iclass 35, count 0 2006.201.11:12:32.91#ibcon#about to read 4, iclass 35, count 0 2006.201.11:12:32.91#ibcon#read 4, iclass 35, count 0 2006.201.11:12:32.91#ibcon#about to read 5, iclass 35, count 0 2006.201.11:12:32.91#ibcon#read 5, iclass 35, count 0 2006.201.11:12:32.91#ibcon#about to read 6, iclass 35, count 0 2006.201.11:12:32.91#ibcon#read 6, iclass 35, count 0 2006.201.11:12:32.91#ibcon#end of sib2, iclass 35, count 0 2006.201.11:12:32.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.11:12:32.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.11:12:32.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:12:32.91#ibcon#*before write, iclass 35, count 0 2006.201.11:12:32.91#ibcon#enter sib2, iclass 35, count 0 2006.201.11:12:32.91#ibcon#flushed, iclass 35, count 0 2006.201.11:12:32.91#ibcon#about to write, iclass 35, count 0 2006.201.11:12:32.91#ibcon#wrote, iclass 35, count 0 2006.201.11:12:32.91#ibcon#about to read 3, iclass 35, count 0 2006.201.11:12:32.96#ibcon#read 3, iclass 35, count 0 2006.201.11:12:32.96#ibcon#about to read 4, iclass 35, count 0 2006.201.11:12:32.96#ibcon#read 4, iclass 35, count 0 2006.201.11:12:32.96#ibcon#about to read 5, iclass 35, count 0 2006.201.11:12:32.96#ibcon#read 5, iclass 35, count 0 2006.201.11:12:32.96#ibcon#about to read 6, iclass 35, count 0 2006.201.11:12:32.96#ibcon#read 6, iclass 35, count 0 2006.201.11:12:32.96#ibcon#end of sib2, iclass 35, count 0 2006.201.11:12:32.96#ibcon#*after write, iclass 35, count 0 2006.201.11:12:32.96#ibcon#*before return 0, iclass 35, count 0 2006.201.11:12:32.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:32.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:12:32.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.11:12:32.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.11:12:32.96$vck44/vb=8,4 2006.201.11:12:32.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.11:12:32.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.11:12:32.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:12:32.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:33.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:33.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:33.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.11:12:33.01#ibcon#first serial, iclass 37, count 2 2006.201.11:12:33.01#ibcon#enter sib2, iclass 37, count 2 2006.201.11:12:33.01#ibcon#flushed, iclass 37, count 2 2006.201.11:12:33.01#ibcon#about to write, iclass 37, count 2 2006.201.11:12:33.01#ibcon#wrote, iclass 37, count 2 2006.201.11:12:33.01#ibcon#about to read 3, iclass 37, count 2 2006.201.11:12:33.03#ibcon#read 3, iclass 37, count 2 2006.201.11:12:33.03#ibcon#about to read 4, iclass 37, count 2 2006.201.11:12:33.03#ibcon#read 4, iclass 37, count 2 2006.201.11:12:33.03#ibcon#about to read 5, iclass 37, count 2 2006.201.11:12:33.03#ibcon#read 5, iclass 37, count 2 2006.201.11:12:33.03#ibcon#about to read 6, iclass 37, count 2 2006.201.11:12:33.03#ibcon#read 6, iclass 37, count 2 2006.201.11:12:33.03#ibcon#end of sib2, iclass 37, count 2 2006.201.11:12:33.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.11:12:33.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.11:12:33.03#ibcon#[27=AT08-04\r\n] 2006.201.11:12:33.03#ibcon#*before write, iclass 37, count 2 2006.201.11:12:33.03#ibcon#enter sib2, iclass 37, count 2 2006.201.11:12:33.03#ibcon#flushed, iclass 37, count 2 2006.201.11:12:33.03#ibcon#about to write, iclass 37, count 2 2006.201.11:12:33.03#ibcon#wrote, iclass 37, count 2 2006.201.11:12:33.03#ibcon#about to read 3, iclass 37, count 2 2006.201.11:12:33.06#ibcon#read 3, iclass 37, count 2 2006.201.11:12:33.06#ibcon#about to read 4, iclass 37, count 2 2006.201.11:12:33.06#ibcon#read 4, iclass 37, count 2 2006.201.11:12:33.06#ibcon#about to read 5, iclass 37, count 2 2006.201.11:12:33.06#ibcon#read 5, iclass 37, count 2 2006.201.11:12:33.06#ibcon#about to read 6, iclass 37, count 2 2006.201.11:12:33.06#ibcon#read 6, iclass 37, count 2 2006.201.11:12:33.06#ibcon#end of sib2, iclass 37, count 2 2006.201.11:12:33.06#ibcon#*after write, iclass 37, count 2 2006.201.11:12:33.06#ibcon#*before return 0, iclass 37, count 2 2006.201.11:12:33.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:33.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:12:33.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.11:12:33.06#ibcon#ireg 7 cls_cnt 0 2006.201.11:12:33.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:33.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:33.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:33.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.11:12:33.18#ibcon#first serial, iclass 37, count 0 2006.201.11:12:33.18#ibcon#enter sib2, iclass 37, count 0 2006.201.11:12:33.18#ibcon#flushed, iclass 37, count 0 2006.201.11:12:33.18#ibcon#about to write, iclass 37, count 0 2006.201.11:12:33.18#ibcon#wrote, iclass 37, count 0 2006.201.11:12:33.18#ibcon#about to read 3, iclass 37, count 0 2006.201.11:12:33.21#ibcon#read 3, iclass 37, count 0 2006.201.11:12:33.21#ibcon#about to read 4, iclass 37, count 0 2006.201.11:12:33.21#ibcon#read 4, iclass 37, count 0 2006.201.11:12:33.21#ibcon#about to read 5, iclass 37, count 0 2006.201.11:12:33.21#ibcon#read 5, iclass 37, count 0 2006.201.11:12:33.21#ibcon#about to read 6, iclass 37, count 0 2006.201.11:12:33.21#ibcon#read 6, iclass 37, count 0 2006.201.11:12:33.21#ibcon#end of sib2, iclass 37, count 0 2006.201.11:12:33.21#ibcon#*mode == 0, iclass 37, count 0 2006.201.11:12:33.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.11:12:33.21#ibcon#[27=USB\r\n] 2006.201.11:12:33.21#ibcon#*before write, iclass 37, count 0 2006.201.11:12:33.21#ibcon#enter sib2, iclass 37, count 0 2006.201.11:12:33.21#ibcon#flushed, iclass 37, count 0 2006.201.11:12:33.21#ibcon#about to write, iclass 37, count 0 2006.201.11:12:33.21#ibcon#wrote, iclass 37, count 0 2006.201.11:12:33.21#ibcon#about to read 3, iclass 37, count 0 2006.201.11:12:33.24#ibcon#read 3, iclass 37, count 0 2006.201.11:12:33.24#ibcon#about to read 4, iclass 37, count 0 2006.201.11:12:33.24#ibcon#read 4, iclass 37, count 0 2006.201.11:12:33.24#ibcon#about to read 5, iclass 37, count 0 2006.201.11:12:33.24#ibcon#read 5, iclass 37, count 0 2006.201.11:12:33.24#ibcon#about to read 6, iclass 37, count 0 2006.201.11:12:33.24#ibcon#read 6, iclass 37, count 0 2006.201.11:12:33.24#ibcon#end of sib2, iclass 37, count 0 2006.201.11:12:33.24#ibcon#*after write, iclass 37, count 0 2006.201.11:12:33.24#ibcon#*before return 0, iclass 37, count 0 2006.201.11:12:33.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:33.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:12:33.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.11:12:33.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.11:12:33.24$vck44/vabw=wide 2006.201.11:12:33.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.11:12:33.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.11:12:33.24#ibcon#ireg 8 cls_cnt 0 2006.201.11:12:33.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:33.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:33.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:33.24#ibcon#enter wrdev, iclass 39, count 0 2006.201.11:12:33.24#ibcon#first serial, iclass 39, count 0 2006.201.11:12:33.24#ibcon#enter sib2, iclass 39, count 0 2006.201.11:12:33.24#ibcon#flushed, iclass 39, count 0 2006.201.11:12:33.24#ibcon#about to write, iclass 39, count 0 2006.201.11:12:33.24#ibcon#wrote, iclass 39, count 0 2006.201.11:12:33.24#ibcon#about to read 3, iclass 39, count 0 2006.201.11:12:33.26#ibcon#read 3, iclass 39, count 0 2006.201.11:12:33.26#ibcon#about to read 4, iclass 39, count 0 2006.201.11:12:33.26#ibcon#read 4, iclass 39, count 0 2006.201.11:12:33.26#ibcon#about to read 5, iclass 39, count 0 2006.201.11:12:33.26#ibcon#read 5, iclass 39, count 0 2006.201.11:12:33.26#ibcon#about to read 6, iclass 39, count 0 2006.201.11:12:33.26#ibcon#read 6, iclass 39, count 0 2006.201.11:12:33.26#ibcon#end of sib2, iclass 39, count 0 2006.201.11:12:33.26#ibcon#*mode == 0, iclass 39, count 0 2006.201.11:12:33.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.11:12:33.26#ibcon#[25=BW32\r\n] 2006.201.11:12:33.26#ibcon#*before write, iclass 39, count 0 2006.201.11:12:33.26#ibcon#enter sib2, iclass 39, count 0 2006.201.11:12:33.26#ibcon#flushed, iclass 39, count 0 2006.201.11:12:33.26#ibcon#about to write, iclass 39, count 0 2006.201.11:12:33.26#ibcon#wrote, iclass 39, count 0 2006.201.11:12:33.26#ibcon#about to read 3, iclass 39, count 0 2006.201.11:12:33.29#ibcon#read 3, iclass 39, count 0 2006.201.11:12:33.29#ibcon#about to read 4, iclass 39, count 0 2006.201.11:12:33.29#ibcon#read 4, iclass 39, count 0 2006.201.11:12:33.29#ibcon#about to read 5, iclass 39, count 0 2006.201.11:12:33.29#ibcon#read 5, iclass 39, count 0 2006.201.11:12:33.29#ibcon#about to read 6, iclass 39, count 0 2006.201.11:12:33.29#ibcon#read 6, iclass 39, count 0 2006.201.11:12:33.29#ibcon#end of sib2, iclass 39, count 0 2006.201.11:12:33.29#ibcon#*after write, iclass 39, count 0 2006.201.11:12:33.29#ibcon#*before return 0, iclass 39, count 0 2006.201.11:12:33.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:33.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:12:33.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.11:12:33.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.11:12:33.29$vck44/vbbw=wide 2006.201.11:12:33.29#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.11:12:33.29#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.11:12:33.29#ibcon#ireg 8 cls_cnt 0 2006.201.11:12:33.29#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:12:33.36#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:12:33.36#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:12:33.36#ibcon#enter wrdev, iclass 2, count 0 2006.201.11:12:33.36#ibcon#first serial, iclass 2, count 0 2006.201.11:12:33.36#ibcon#enter sib2, iclass 2, count 0 2006.201.11:12:33.36#ibcon#flushed, iclass 2, count 0 2006.201.11:12:33.36#ibcon#about to write, iclass 2, count 0 2006.201.11:12:33.36#ibcon#wrote, iclass 2, count 0 2006.201.11:12:33.36#ibcon#about to read 3, iclass 2, count 0 2006.201.11:12:33.38#ibcon#read 3, iclass 2, count 0 2006.201.11:12:33.38#ibcon#about to read 4, iclass 2, count 0 2006.201.11:12:33.38#ibcon#read 4, iclass 2, count 0 2006.201.11:12:33.38#ibcon#about to read 5, iclass 2, count 0 2006.201.11:12:33.38#ibcon#read 5, iclass 2, count 0 2006.201.11:12:33.38#ibcon#about to read 6, iclass 2, count 0 2006.201.11:12:33.38#ibcon#read 6, iclass 2, count 0 2006.201.11:12:33.38#ibcon#end of sib2, iclass 2, count 0 2006.201.11:12:33.38#ibcon#*mode == 0, iclass 2, count 0 2006.201.11:12:33.38#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.11:12:33.38#ibcon#[27=BW32\r\n] 2006.201.11:12:33.38#ibcon#*before write, iclass 2, count 0 2006.201.11:12:33.38#ibcon#enter sib2, iclass 2, count 0 2006.201.11:12:33.38#ibcon#flushed, iclass 2, count 0 2006.201.11:12:33.38#ibcon#about to write, iclass 2, count 0 2006.201.11:12:33.38#ibcon#wrote, iclass 2, count 0 2006.201.11:12:33.38#ibcon#about to read 3, iclass 2, count 0 2006.201.11:12:33.41#ibcon#read 3, iclass 2, count 0 2006.201.11:12:33.41#ibcon#about to read 4, iclass 2, count 0 2006.201.11:12:33.41#ibcon#read 4, iclass 2, count 0 2006.201.11:12:33.41#ibcon#about to read 5, iclass 2, count 0 2006.201.11:12:33.41#ibcon#read 5, iclass 2, count 0 2006.201.11:12:33.41#ibcon#about to read 6, iclass 2, count 0 2006.201.11:12:33.41#ibcon#read 6, iclass 2, count 0 2006.201.11:12:33.41#ibcon#end of sib2, iclass 2, count 0 2006.201.11:12:33.41#ibcon#*after write, iclass 2, count 0 2006.201.11:12:33.41#ibcon#*before return 0, iclass 2, count 0 2006.201.11:12:33.41#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:12:33.41#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:12:33.41#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.11:12:33.41#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.11:12:33.41$setupk4/ifdk4 2006.201.11:12:33.41$ifdk4/lo= 2006.201.11:12:33.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:12:33.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:12:33.41$ifdk4/patch= 2006.201.11:12:33.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:12:33.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:12:33.41$setupk4/!*+20s 2006.201.11:12:34.30#abcon#<5=/04 1.4 2.9 21.40 991004.0\r\n> 2006.201.11:12:34.32#abcon#{5=INTERFACE CLEAR} 2006.201.11:12:34.38#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:12:44.47#abcon#<5=/04 1.4 2.9 21.40 991004.0\r\n> 2006.201.11:12:44.49#abcon#{5=INTERFACE CLEAR} 2006.201.11:12:44.55#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:12:47.88$setupk4/"tpicd 2006.201.11:12:47.88$setupk4/echo=off 2006.201.11:12:47.88$setupk4/xlog=off 2006.201.11:12:47.88:!2006.201.11:20:47 2006.201.11:13:10.14#trakl#Source acquired 2006.201.11:13:11.14#flagr#flagr/antenna,acquired 2006.201.11:20:47.00:preob 2006.201.11:20:48.14/onsource/TRACKING 2006.201.11:20:48.14:!2006.201.11:20:57 2006.201.11:20:57.00:"tape 2006.201.11:20:57.00:"st=record 2006.201.11:20:57.00:data_valid=on 2006.201.11:20:57.00:midob 2006.201.11:20:57.14/onsource/TRACKING 2006.201.11:20:57.14/wx/21.40,1003.9,100 2006.201.11:20:57.19/cable/+6.4707E-03 2006.201.11:20:58.28/va/01,08,usb,yes,30,32 2006.201.11:20:58.28/va/02,07,usb,yes,32,33 2006.201.11:20:58.28/va/03,08,usb,yes,29,30 2006.201.11:20:58.28/va/04,07,usb,yes,33,35 2006.201.11:20:58.28/va/05,04,usb,yes,29,30 2006.201.11:20:58.28/va/06,05,usb,yes,29,29 2006.201.11:20:58.28/va/07,05,usb,yes,28,30 2006.201.11:20:58.28/va/08,04,usb,yes,28,34 2006.201.11:20:58.51/valo/01,524.99,yes,locked 2006.201.11:20:58.51/valo/02,534.99,yes,locked 2006.201.11:20:58.51/valo/03,564.99,yes,locked 2006.201.11:20:58.51/valo/04,624.99,yes,locked 2006.201.11:20:58.51/valo/05,734.99,yes,locked 2006.201.11:20:58.51/valo/06,814.99,yes,locked 2006.201.11:20:58.51/valo/07,864.99,yes,locked 2006.201.11:20:58.51/valo/08,884.99,yes,locked 2006.201.11:20:59.60/vb/01,04,usb,yes,29,27 2006.201.11:20:59.60/vb/02,05,usb,yes,28,27 2006.201.11:20:59.60/vb/03,04,usb,yes,28,31 2006.201.11:20:59.60/vb/04,05,usb,yes,29,28 2006.201.11:20:59.60/vb/05,04,usb,yes,25,28 2006.201.11:20:59.60/vb/06,04,usb,yes,30,26 2006.201.11:20:59.60/vb/07,04,usb,yes,30,29 2006.201.11:20:59.60/vb/08,04,usb,yes,27,30 2006.201.11:20:59.84/vblo/01,629.99,yes,locked 2006.201.11:20:59.84/vblo/02,634.99,yes,locked 2006.201.11:20:59.84/vblo/03,649.99,yes,locked 2006.201.11:20:59.84/vblo/04,679.99,yes,locked 2006.201.11:20:59.84/vblo/05,709.99,yes,locked 2006.201.11:20:59.84/vblo/06,719.99,yes,locked 2006.201.11:20:59.84/vblo/07,734.99,yes,locked 2006.201.11:20:59.84/vblo/08,744.99,yes,locked 2006.201.11:20:59.99/vabw/8 2006.201.11:21:00.14/vbbw/8 2006.201.11:21:00.23/xfe/off,on,14.7 2006.201.11:21:00.62/ifatt/23,28,28,28 2006.201.11:21:01.05/fmout-gps/S +4.59E-07 2006.201.11:21:01.12:!2006.201.11:22:17 2006.201.11:22:17.00:data_valid=off 2006.201.11:22:17.00:"et 2006.201.11:22:17.00:!+3s 2006.201.11:22:20.02:"tape 2006.201.11:22:20.02:postob 2006.201.11:22:20.21/cable/+6.4696E-03 2006.201.11:22:20.21/wx/21.40,1004.0,100 2006.201.11:22:20.29/fmout-gps/S +4.58E-07 2006.201.11:22:20.29:scan_name=201-1126,jd0607,40 2006.201.11:22:20.29:source=2134+00,213638.59,004154.2,2000.0,ccw 2006.201.11:22:21.14#flagr#flagr/antenna,new-source 2006.201.11:22:21.14:checkk5 2006.201.11:22:21.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:22:21.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:22:22.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:22:22.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:22:23.01/chk_obsdata//k5ts1/T2011120??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.11:22:23.37/chk_obsdata//k5ts2/T2011120??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.11:22:23.74/chk_obsdata//k5ts3/T2011120??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.11:22:24.10/chk_obsdata//k5ts4/T2011120??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.11:22:24.79/k5log//k5ts1_log_newline 2006.201.11:22:25.47/k5log//k5ts2_log_newline 2006.201.11:22:26.16/k5log//k5ts3_log_newline 2006.201.11:22:26.85/k5log//k5ts4_log_newline 2006.201.11:22:26.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:22:26.87:setupk4=1 2006.201.11:22:26.87$setupk4/echo=on 2006.201.11:22:26.87$setupk4/pcalon 2006.201.11:22:26.87$pcalon/"no phase cal control is implemented here 2006.201.11:22:26.87$setupk4/"tpicd=stop 2006.201.11:22:26.87$setupk4/"rec=synch_on 2006.201.11:22:26.87$setupk4/"rec_mode=128 2006.201.11:22:26.87$setupk4/!* 2006.201.11:22:26.87$setupk4/recpk4 2006.201.11:22:26.87$recpk4/recpatch= 2006.201.11:22:26.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:22:26.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:22:26.88$setupk4/vck44 2006.201.11:22:26.88$vck44/valo=1,524.99 2006.201.11:22:26.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.11:22:26.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.11:22:26.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:26.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:26.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:26.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:26.88#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:22:26.88#ibcon#first serial, iclass 30, count 0 2006.201.11:22:26.88#ibcon#enter sib2, iclass 30, count 0 2006.201.11:22:26.88#ibcon#flushed, iclass 30, count 0 2006.201.11:22:26.88#ibcon#about to write, iclass 30, count 0 2006.201.11:22:26.88#ibcon#wrote, iclass 30, count 0 2006.201.11:22:26.88#ibcon#about to read 3, iclass 30, count 0 2006.201.11:22:26.91#ibcon#read 3, iclass 30, count 0 2006.201.11:22:26.91#ibcon#about to read 4, iclass 30, count 0 2006.201.11:22:26.91#ibcon#read 4, iclass 30, count 0 2006.201.11:22:26.91#ibcon#about to read 5, iclass 30, count 0 2006.201.11:22:26.91#ibcon#read 5, iclass 30, count 0 2006.201.11:22:26.91#ibcon#about to read 6, iclass 30, count 0 2006.201.11:22:26.91#ibcon#read 6, iclass 30, count 0 2006.201.11:22:26.91#ibcon#end of sib2, iclass 30, count 0 2006.201.11:22:26.91#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:22:26.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:22:26.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:22:26.91#ibcon#*before write, iclass 30, count 0 2006.201.11:22:26.91#ibcon#enter sib2, iclass 30, count 0 2006.201.11:22:26.91#ibcon#flushed, iclass 30, count 0 2006.201.11:22:26.91#ibcon#about to write, iclass 30, count 0 2006.201.11:22:26.91#ibcon#wrote, iclass 30, count 0 2006.201.11:22:26.91#ibcon#about to read 3, iclass 30, count 0 2006.201.11:22:26.96#ibcon#read 3, iclass 30, count 0 2006.201.11:22:26.96#ibcon#about to read 4, iclass 30, count 0 2006.201.11:22:26.96#ibcon#read 4, iclass 30, count 0 2006.201.11:22:26.96#ibcon#about to read 5, iclass 30, count 0 2006.201.11:22:26.96#ibcon#read 5, iclass 30, count 0 2006.201.11:22:26.96#ibcon#about to read 6, iclass 30, count 0 2006.201.11:22:26.96#ibcon#read 6, iclass 30, count 0 2006.201.11:22:26.96#ibcon#end of sib2, iclass 30, count 0 2006.201.11:22:26.96#ibcon#*after write, iclass 30, count 0 2006.201.11:22:26.96#ibcon#*before return 0, iclass 30, count 0 2006.201.11:22:26.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:26.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:26.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:22:26.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:22:26.96$vck44/va=1,8 2006.201.11:22:26.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.11:22:26.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.11:22:26.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:26.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:26.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:26.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:26.96#ibcon#enter wrdev, iclass 32, count 2 2006.201.11:22:26.96#ibcon#first serial, iclass 32, count 2 2006.201.11:22:26.96#ibcon#enter sib2, iclass 32, count 2 2006.201.11:22:26.96#ibcon#flushed, iclass 32, count 2 2006.201.11:22:26.96#ibcon#about to write, iclass 32, count 2 2006.201.11:22:26.96#ibcon#wrote, iclass 32, count 2 2006.201.11:22:26.96#ibcon#about to read 3, iclass 32, count 2 2006.201.11:22:26.98#ibcon#read 3, iclass 32, count 2 2006.201.11:22:26.98#ibcon#about to read 4, iclass 32, count 2 2006.201.11:22:26.98#ibcon#read 4, iclass 32, count 2 2006.201.11:22:26.98#ibcon#about to read 5, iclass 32, count 2 2006.201.11:22:26.98#ibcon#read 5, iclass 32, count 2 2006.201.11:22:26.98#ibcon#about to read 6, iclass 32, count 2 2006.201.11:22:26.98#ibcon#read 6, iclass 32, count 2 2006.201.11:22:26.98#ibcon#end of sib2, iclass 32, count 2 2006.201.11:22:26.98#ibcon#*mode == 0, iclass 32, count 2 2006.201.11:22:26.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.11:22:26.98#ibcon#[25=AT01-08\r\n] 2006.201.11:22:26.98#ibcon#*before write, iclass 32, count 2 2006.201.11:22:26.98#ibcon#enter sib2, iclass 32, count 2 2006.201.11:22:26.98#ibcon#flushed, iclass 32, count 2 2006.201.11:22:26.98#ibcon#about to write, iclass 32, count 2 2006.201.11:22:26.98#ibcon#wrote, iclass 32, count 2 2006.201.11:22:26.98#ibcon#about to read 3, iclass 32, count 2 2006.201.11:22:27.01#ibcon#read 3, iclass 32, count 2 2006.201.11:22:27.01#ibcon#about to read 4, iclass 32, count 2 2006.201.11:22:27.01#ibcon#read 4, iclass 32, count 2 2006.201.11:22:27.01#ibcon#about to read 5, iclass 32, count 2 2006.201.11:22:27.01#ibcon#read 5, iclass 32, count 2 2006.201.11:22:27.01#ibcon#about to read 6, iclass 32, count 2 2006.201.11:22:27.01#ibcon#read 6, iclass 32, count 2 2006.201.11:22:27.01#ibcon#end of sib2, iclass 32, count 2 2006.201.11:22:27.01#ibcon#*after write, iclass 32, count 2 2006.201.11:22:27.01#ibcon#*before return 0, iclass 32, count 2 2006.201.11:22:27.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:27.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:27.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.11:22:27.01#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:27.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:27.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:27.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:27.13#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:22:27.13#ibcon#first serial, iclass 32, count 0 2006.201.11:22:27.13#ibcon#enter sib2, iclass 32, count 0 2006.201.11:22:27.13#ibcon#flushed, iclass 32, count 0 2006.201.11:22:27.13#ibcon#about to write, iclass 32, count 0 2006.201.11:22:27.13#ibcon#wrote, iclass 32, count 0 2006.201.11:22:27.13#ibcon#about to read 3, iclass 32, count 0 2006.201.11:22:27.15#ibcon#read 3, iclass 32, count 0 2006.201.11:22:27.15#ibcon#about to read 4, iclass 32, count 0 2006.201.11:22:27.15#ibcon#read 4, iclass 32, count 0 2006.201.11:22:27.15#ibcon#about to read 5, iclass 32, count 0 2006.201.11:22:27.15#ibcon#read 5, iclass 32, count 0 2006.201.11:22:27.15#ibcon#about to read 6, iclass 32, count 0 2006.201.11:22:27.15#ibcon#read 6, iclass 32, count 0 2006.201.11:22:27.15#ibcon#end of sib2, iclass 32, count 0 2006.201.11:22:27.15#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:22:27.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:22:27.15#ibcon#[25=USB\r\n] 2006.201.11:22:27.15#ibcon#*before write, iclass 32, count 0 2006.201.11:22:27.15#ibcon#enter sib2, iclass 32, count 0 2006.201.11:22:27.15#ibcon#flushed, iclass 32, count 0 2006.201.11:22:27.15#ibcon#about to write, iclass 32, count 0 2006.201.11:22:27.15#ibcon#wrote, iclass 32, count 0 2006.201.11:22:27.15#ibcon#about to read 3, iclass 32, count 0 2006.201.11:22:27.18#ibcon#read 3, iclass 32, count 0 2006.201.11:22:27.18#ibcon#about to read 4, iclass 32, count 0 2006.201.11:22:27.18#ibcon#read 4, iclass 32, count 0 2006.201.11:22:27.18#ibcon#about to read 5, iclass 32, count 0 2006.201.11:22:27.18#ibcon#read 5, iclass 32, count 0 2006.201.11:22:27.18#ibcon#about to read 6, iclass 32, count 0 2006.201.11:22:27.18#ibcon#read 6, iclass 32, count 0 2006.201.11:22:27.18#ibcon#end of sib2, iclass 32, count 0 2006.201.11:22:27.18#ibcon#*after write, iclass 32, count 0 2006.201.11:22:27.18#ibcon#*before return 0, iclass 32, count 0 2006.201.11:22:27.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:27.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:27.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:22:27.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:22:27.18$vck44/valo=2,534.99 2006.201.11:22:27.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.11:22:27.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.11:22:27.18#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:27.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:27.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:27.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:27.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:22:27.18#ibcon#first serial, iclass 34, count 0 2006.201.11:22:27.18#ibcon#enter sib2, iclass 34, count 0 2006.201.11:22:27.18#ibcon#flushed, iclass 34, count 0 2006.201.11:22:27.18#ibcon#about to write, iclass 34, count 0 2006.201.11:22:27.18#ibcon#wrote, iclass 34, count 0 2006.201.11:22:27.18#ibcon#about to read 3, iclass 34, count 0 2006.201.11:22:27.20#ibcon#read 3, iclass 34, count 0 2006.201.11:22:27.20#ibcon#about to read 4, iclass 34, count 0 2006.201.11:22:27.20#ibcon#read 4, iclass 34, count 0 2006.201.11:22:27.20#ibcon#about to read 5, iclass 34, count 0 2006.201.11:22:27.20#ibcon#read 5, iclass 34, count 0 2006.201.11:22:27.20#ibcon#about to read 6, iclass 34, count 0 2006.201.11:22:27.20#ibcon#read 6, iclass 34, count 0 2006.201.11:22:27.20#ibcon#end of sib2, iclass 34, count 0 2006.201.11:22:27.20#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:22:27.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:22:27.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:22:27.20#ibcon#*before write, iclass 34, count 0 2006.201.11:22:27.20#ibcon#enter sib2, iclass 34, count 0 2006.201.11:22:27.20#ibcon#flushed, iclass 34, count 0 2006.201.11:22:27.20#ibcon#about to write, iclass 34, count 0 2006.201.11:22:27.20#ibcon#wrote, iclass 34, count 0 2006.201.11:22:27.20#ibcon#about to read 3, iclass 34, count 0 2006.201.11:22:27.25#ibcon#read 3, iclass 34, count 0 2006.201.11:22:27.25#ibcon#about to read 4, iclass 34, count 0 2006.201.11:22:27.25#ibcon#read 4, iclass 34, count 0 2006.201.11:22:27.25#ibcon#about to read 5, iclass 34, count 0 2006.201.11:22:27.25#ibcon#read 5, iclass 34, count 0 2006.201.11:22:27.25#ibcon#about to read 6, iclass 34, count 0 2006.201.11:22:27.25#ibcon#read 6, iclass 34, count 0 2006.201.11:22:27.25#ibcon#end of sib2, iclass 34, count 0 2006.201.11:22:27.25#ibcon#*after write, iclass 34, count 0 2006.201.11:22:27.25#ibcon#*before return 0, iclass 34, count 0 2006.201.11:22:27.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:27.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:27.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:22:27.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:22:27.25$vck44/va=2,7 2006.201.11:22:27.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.11:22:27.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.11:22:27.25#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:27.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:27.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:27.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:27.30#ibcon#enter wrdev, iclass 36, count 2 2006.201.11:22:27.30#ibcon#first serial, iclass 36, count 2 2006.201.11:22:27.30#ibcon#enter sib2, iclass 36, count 2 2006.201.11:22:27.30#ibcon#flushed, iclass 36, count 2 2006.201.11:22:27.30#ibcon#about to write, iclass 36, count 2 2006.201.11:22:27.30#ibcon#wrote, iclass 36, count 2 2006.201.11:22:27.30#ibcon#about to read 3, iclass 36, count 2 2006.201.11:22:27.32#ibcon#read 3, iclass 36, count 2 2006.201.11:22:27.32#ibcon#about to read 4, iclass 36, count 2 2006.201.11:22:27.32#ibcon#read 4, iclass 36, count 2 2006.201.11:22:27.32#ibcon#about to read 5, iclass 36, count 2 2006.201.11:22:27.32#ibcon#read 5, iclass 36, count 2 2006.201.11:22:27.32#ibcon#about to read 6, iclass 36, count 2 2006.201.11:22:27.32#ibcon#read 6, iclass 36, count 2 2006.201.11:22:27.32#ibcon#end of sib2, iclass 36, count 2 2006.201.11:22:27.32#ibcon#*mode == 0, iclass 36, count 2 2006.201.11:22:27.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.11:22:27.32#ibcon#[25=AT02-07\r\n] 2006.201.11:22:27.32#ibcon#*before write, iclass 36, count 2 2006.201.11:22:27.32#ibcon#enter sib2, iclass 36, count 2 2006.201.11:22:27.32#ibcon#flushed, iclass 36, count 2 2006.201.11:22:27.32#ibcon#about to write, iclass 36, count 2 2006.201.11:22:27.32#ibcon#wrote, iclass 36, count 2 2006.201.11:22:27.32#ibcon#about to read 3, iclass 36, count 2 2006.201.11:22:27.35#ibcon#read 3, iclass 36, count 2 2006.201.11:22:27.35#ibcon#about to read 4, iclass 36, count 2 2006.201.11:22:27.35#ibcon#read 4, iclass 36, count 2 2006.201.11:22:27.35#ibcon#about to read 5, iclass 36, count 2 2006.201.11:22:27.35#ibcon#read 5, iclass 36, count 2 2006.201.11:22:27.35#ibcon#about to read 6, iclass 36, count 2 2006.201.11:22:27.35#ibcon#read 6, iclass 36, count 2 2006.201.11:22:27.35#ibcon#end of sib2, iclass 36, count 2 2006.201.11:22:27.35#ibcon#*after write, iclass 36, count 2 2006.201.11:22:27.35#ibcon#*before return 0, iclass 36, count 2 2006.201.11:22:27.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:27.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:27.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.11:22:27.35#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:27.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:27.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:27.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:27.47#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:22:27.47#ibcon#first serial, iclass 36, count 0 2006.201.11:22:27.47#ibcon#enter sib2, iclass 36, count 0 2006.201.11:22:27.47#ibcon#flushed, iclass 36, count 0 2006.201.11:22:27.47#ibcon#about to write, iclass 36, count 0 2006.201.11:22:27.47#ibcon#wrote, iclass 36, count 0 2006.201.11:22:27.47#ibcon#about to read 3, iclass 36, count 0 2006.201.11:22:27.49#ibcon#read 3, iclass 36, count 0 2006.201.11:22:27.49#ibcon#about to read 4, iclass 36, count 0 2006.201.11:22:27.49#ibcon#read 4, iclass 36, count 0 2006.201.11:22:27.49#ibcon#about to read 5, iclass 36, count 0 2006.201.11:22:27.49#ibcon#read 5, iclass 36, count 0 2006.201.11:22:27.49#ibcon#about to read 6, iclass 36, count 0 2006.201.11:22:27.49#ibcon#read 6, iclass 36, count 0 2006.201.11:22:27.49#ibcon#end of sib2, iclass 36, count 0 2006.201.11:22:27.49#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:22:27.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:22:27.49#ibcon#[25=USB\r\n] 2006.201.11:22:27.49#ibcon#*before write, iclass 36, count 0 2006.201.11:22:27.49#ibcon#enter sib2, iclass 36, count 0 2006.201.11:22:27.49#ibcon#flushed, iclass 36, count 0 2006.201.11:22:27.49#ibcon#about to write, iclass 36, count 0 2006.201.11:22:27.49#ibcon#wrote, iclass 36, count 0 2006.201.11:22:27.49#ibcon#about to read 3, iclass 36, count 0 2006.201.11:22:27.52#ibcon#read 3, iclass 36, count 0 2006.201.11:22:27.52#ibcon#about to read 4, iclass 36, count 0 2006.201.11:22:27.52#ibcon#read 4, iclass 36, count 0 2006.201.11:22:27.52#ibcon#about to read 5, iclass 36, count 0 2006.201.11:22:27.52#ibcon#read 5, iclass 36, count 0 2006.201.11:22:27.52#ibcon#about to read 6, iclass 36, count 0 2006.201.11:22:27.52#ibcon#read 6, iclass 36, count 0 2006.201.11:22:27.52#ibcon#end of sib2, iclass 36, count 0 2006.201.11:22:27.52#ibcon#*after write, iclass 36, count 0 2006.201.11:22:27.52#ibcon#*before return 0, iclass 36, count 0 2006.201.11:22:27.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:27.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:27.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:22:27.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:22:27.52$vck44/valo=3,564.99 2006.201.11:22:27.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.11:22:27.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.11:22:27.52#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:27.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:27.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:27.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:27.52#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:22:27.52#ibcon#first serial, iclass 38, count 0 2006.201.11:22:27.52#ibcon#enter sib2, iclass 38, count 0 2006.201.11:22:27.52#ibcon#flushed, iclass 38, count 0 2006.201.11:22:27.52#ibcon#about to write, iclass 38, count 0 2006.201.11:22:27.52#ibcon#wrote, iclass 38, count 0 2006.201.11:22:27.52#ibcon#about to read 3, iclass 38, count 0 2006.201.11:22:27.54#ibcon#read 3, iclass 38, count 0 2006.201.11:22:27.54#ibcon#about to read 4, iclass 38, count 0 2006.201.11:22:27.54#ibcon#read 4, iclass 38, count 0 2006.201.11:22:27.54#ibcon#about to read 5, iclass 38, count 0 2006.201.11:22:27.54#ibcon#read 5, iclass 38, count 0 2006.201.11:22:27.54#ibcon#about to read 6, iclass 38, count 0 2006.201.11:22:27.54#ibcon#read 6, iclass 38, count 0 2006.201.11:22:27.54#ibcon#end of sib2, iclass 38, count 0 2006.201.11:22:27.54#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:22:27.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:22:27.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:22:27.54#ibcon#*before write, iclass 38, count 0 2006.201.11:22:27.54#ibcon#enter sib2, iclass 38, count 0 2006.201.11:22:27.54#ibcon#flushed, iclass 38, count 0 2006.201.11:22:27.54#ibcon#about to write, iclass 38, count 0 2006.201.11:22:27.54#ibcon#wrote, iclass 38, count 0 2006.201.11:22:27.54#ibcon#about to read 3, iclass 38, count 0 2006.201.11:22:27.59#ibcon#read 3, iclass 38, count 0 2006.201.11:22:27.59#ibcon#about to read 4, iclass 38, count 0 2006.201.11:22:27.59#ibcon#read 4, iclass 38, count 0 2006.201.11:22:27.59#ibcon#about to read 5, iclass 38, count 0 2006.201.11:22:27.59#ibcon#read 5, iclass 38, count 0 2006.201.11:22:27.59#ibcon#about to read 6, iclass 38, count 0 2006.201.11:22:27.59#ibcon#read 6, iclass 38, count 0 2006.201.11:22:27.59#ibcon#end of sib2, iclass 38, count 0 2006.201.11:22:27.59#ibcon#*after write, iclass 38, count 0 2006.201.11:22:27.59#ibcon#*before return 0, iclass 38, count 0 2006.201.11:22:27.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:27.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:27.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:22:27.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:22:27.59$vck44/va=3,8 2006.201.11:22:27.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.11:22:27.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.11:22:27.59#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:27.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:27.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:27.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:27.64#ibcon#enter wrdev, iclass 40, count 2 2006.201.11:22:27.64#ibcon#first serial, iclass 40, count 2 2006.201.11:22:27.64#ibcon#enter sib2, iclass 40, count 2 2006.201.11:22:27.64#ibcon#flushed, iclass 40, count 2 2006.201.11:22:27.64#ibcon#about to write, iclass 40, count 2 2006.201.11:22:27.64#ibcon#wrote, iclass 40, count 2 2006.201.11:22:27.64#ibcon#about to read 3, iclass 40, count 2 2006.201.11:22:27.66#ibcon#read 3, iclass 40, count 2 2006.201.11:22:27.66#ibcon#about to read 4, iclass 40, count 2 2006.201.11:22:27.66#ibcon#read 4, iclass 40, count 2 2006.201.11:22:27.66#ibcon#about to read 5, iclass 40, count 2 2006.201.11:22:27.66#ibcon#read 5, iclass 40, count 2 2006.201.11:22:27.66#ibcon#about to read 6, iclass 40, count 2 2006.201.11:22:27.66#ibcon#read 6, iclass 40, count 2 2006.201.11:22:27.66#ibcon#end of sib2, iclass 40, count 2 2006.201.11:22:27.66#ibcon#*mode == 0, iclass 40, count 2 2006.201.11:22:27.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.11:22:27.66#ibcon#[25=AT03-08\r\n] 2006.201.11:22:27.66#ibcon#*before write, iclass 40, count 2 2006.201.11:22:27.66#ibcon#enter sib2, iclass 40, count 2 2006.201.11:22:27.66#ibcon#flushed, iclass 40, count 2 2006.201.11:22:27.66#ibcon#about to write, iclass 40, count 2 2006.201.11:22:27.66#ibcon#wrote, iclass 40, count 2 2006.201.11:22:27.66#ibcon#about to read 3, iclass 40, count 2 2006.201.11:22:27.69#ibcon#read 3, iclass 40, count 2 2006.201.11:22:27.69#ibcon#about to read 4, iclass 40, count 2 2006.201.11:22:27.69#ibcon#read 4, iclass 40, count 2 2006.201.11:22:27.69#ibcon#about to read 5, iclass 40, count 2 2006.201.11:22:27.69#ibcon#read 5, iclass 40, count 2 2006.201.11:22:27.69#ibcon#about to read 6, iclass 40, count 2 2006.201.11:22:27.69#ibcon#read 6, iclass 40, count 2 2006.201.11:22:27.69#ibcon#end of sib2, iclass 40, count 2 2006.201.11:22:27.69#ibcon#*after write, iclass 40, count 2 2006.201.11:22:27.69#ibcon#*before return 0, iclass 40, count 2 2006.201.11:22:27.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:27.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:27.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.11:22:27.69#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:27.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:27.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:27.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:27.81#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:22:27.81#ibcon#first serial, iclass 40, count 0 2006.201.11:22:27.81#ibcon#enter sib2, iclass 40, count 0 2006.201.11:22:27.81#ibcon#flushed, iclass 40, count 0 2006.201.11:22:27.81#ibcon#about to write, iclass 40, count 0 2006.201.11:22:27.81#ibcon#wrote, iclass 40, count 0 2006.201.11:22:27.81#ibcon#about to read 3, iclass 40, count 0 2006.201.11:22:27.83#ibcon#read 3, iclass 40, count 0 2006.201.11:22:27.83#ibcon#about to read 4, iclass 40, count 0 2006.201.11:22:27.83#ibcon#read 4, iclass 40, count 0 2006.201.11:22:27.83#ibcon#about to read 5, iclass 40, count 0 2006.201.11:22:27.83#ibcon#read 5, iclass 40, count 0 2006.201.11:22:27.83#ibcon#about to read 6, iclass 40, count 0 2006.201.11:22:27.83#ibcon#read 6, iclass 40, count 0 2006.201.11:22:27.83#ibcon#end of sib2, iclass 40, count 0 2006.201.11:22:27.83#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:22:27.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:22:27.83#ibcon#[25=USB\r\n] 2006.201.11:22:27.83#ibcon#*before write, iclass 40, count 0 2006.201.11:22:27.83#ibcon#enter sib2, iclass 40, count 0 2006.201.11:22:27.83#ibcon#flushed, iclass 40, count 0 2006.201.11:22:27.83#ibcon#about to write, iclass 40, count 0 2006.201.11:22:27.83#ibcon#wrote, iclass 40, count 0 2006.201.11:22:27.83#ibcon#about to read 3, iclass 40, count 0 2006.201.11:22:27.86#ibcon#read 3, iclass 40, count 0 2006.201.11:22:27.86#ibcon#about to read 4, iclass 40, count 0 2006.201.11:22:27.86#ibcon#read 4, iclass 40, count 0 2006.201.11:22:27.86#ibcon#about to read 5, iclass 40, count 0 2006.201.11:22:27.86#ibcon#read 5, iclass 40, count 0 2006.201.11:22:27.86#ibcon#about to read 6, iclass 40, count 0 2006.201.11:22:27.86#ibcon#read 6, iclass 40, count 0 2006.201.11:22:27.86#ibcon#end of sib2, iclass 40, count 0 2006.201.11:22:27.86#ibcon#*after write, iclass 40, count 0 2006.201.11:22:27.86#ibcon#*before return 0, iclass 40, count 0 2006.201.11:22:27.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:27.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:27.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:22:27.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:22:27.86$vck44/valo=4,624.99 2006.201.11:22:27.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.11:22:27.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.11:22:27.86#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:27.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:27.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:27.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:27.86#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:22:27.86#ibcon#first serial, iclass 4, count 0 2006.201.11:22:27.86#ibcon#enter sib2, iclass 4, count 0 2006.201.11:22:27.86#ibcon#flushed, iclass 4, count 0 2006.201.11:22:27.86#ibcon#about to write, iclass 4, count 0 2006.201.11:22:27.86#ibcon#wrote, iclass 4, count 0 2006.201.11:22:27.86#ibcon#about to read 3, iclass 4, count 0 2006.201.11:22:27.88#ibcon#read 3, iclass 4, count 0 2006.201.11:22:27.88#ibcon#about to read 4, iclass 4, count 0 2006.201.11:22:27.88#ibcon#read 4, iclass 4, count 0 2006.201.11:22:27.88#ibcon#about to read 5, iclass 4, count 0 2006.201.11:22:27.88#ibcon#read 5, iclass 4, count 0 2006.201.11:22:27.88#ibcon#about to read 6, iclass 4, count 0 2006.201.11:22:27.88#ibcon#read 6, iclass 4, count 0 2006.201.11:22:27.88#ibcon#end of sib2, iclass 4, count 0 2006.201.11:22:27.88#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:22:27.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:22:27.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:22:27.88#ibcon#*before write, iclass 4, count 0 2006.201.11:22:27.88#ibcon#enter sib2, iclass 4, count 0 2006.201.11:22:27.88#ibcon#flushed, iclass 4, count 0 2006.201.11:22:27.88#ibcon#about to write, iclass 4, count 0 2006.201.11:22:27.88#ibcon#wrote, iclass 4, count 0 2006.201.11:22:27.88#ibcon#about to read 3, iclass 4, count 0 2006.201.11:22:27.93#ibcon#read 3, iclass 4, count 0 2006.201.11:22:27.93#ibcon#about to read 4, iclass 4, count 0 2006.201.11:22:27.93#ibcon#read 4, iclass 4, count 0 2006.201.11:22:27.93#ibcon#about to read 5, iclass 4, count 0 2006.201.11:22:27.93#ibcon#read 5, iclass 4, count 0 2006.201.11:22:27.93#ibcon#about to read 6, iclass 4, count 0 2006.201.11:22:27.93#ibcon#read 6, iclass 4, count 0 2006.201.11:22:27.93#ibcon#end of sib2, iclass 4, count 0 2006.201.11:22:27.93#ibcon#*after write, iclass 4, count 0 2006.201.11:22:27.93#ibcon#*before return 0, iclass 4, count 0 2006.201.11:22:27.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:27.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:27.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:22:27.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:22:27.93$vck44/va=4,7 2006.201.11:22:27.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.11:22:27.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.11:22:27.93#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:27.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:27.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:27.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:27.98#ibcon#enter wrdev, iclass 6, count 2 2006.201.11:22:27.98#ibcon#first serial, iclass 6, count 2 2006.201.11:22:27.98#ibcon#enter sib2, iclass 6, count 2 2006.201.11:22:27.98#ibcon#flushed, iclass 6, count 2 2006.201.11:22:27.98#ibcon#about to write, iclass 6, count 2 2006.201.11:22:27.98#ibcon#wrote, iclass 6, count 2 2006.201.11:22:27.98#ibcon#about to read 3, iclass 6, count 2 2006.201.11:22:28.00#ibcon#read 3, iclass 6, count 2 2006.201.11:22:28.00#ibcon#about to read 4, iclass 6, count 2 2006.201.11:22:28.00#ibcon#read 4, iclass 6, count 2 2006.201.11:22:28.00#ibcon#about to read 5, iclass 6, count 2 2006.201.11:22:28.00#ibcon#read 5, iclass 6, count 2 2006.201.11:22:28.00#ibcon#about to read 6, iclass 6, count 2 2006.201.11:22:28.00#ibcon#read 6, iclass 6, count 2 2006.201.11:22:28.00#ibcon#end of sib2, iclass 6, count 2 2006.201.11:22:28.00#ibcon#*mode == 0, iclass 6, count 2 2006.201.11:22:28.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.11:22:28.00#ibcon#[25=AT04-07\r\n] 2006.201.11:22:28.00#ibcon#*before write, iclass 6, count 2 2006.201.11:22:28.00#ibcon#enter sib2, iclass 6, count 2 2006.201.11:22:28.00#ibcon#flushed, iclass 6, count 2 2006.201.11:22:28.00#ibcon#about to write, iclass 6, count 2 2006.201.11:22:28.00#ibcon#wrote, iclass 6, count 2 2006.201.11:22:28.00#ibcon#about to read 3, iclass 6, count 2 2006.201.11:22:28.03#ibcon#read 3, iclass 6, count 2 2006.201.11:22:28.03#ibcon#about to read 4, iclass 6, count 2 2006.201.11:22:28.03#ibcon#read 4, iclass 6, count 2 2006.201.11:22:28.03#ibcon#about to read 5, iclass 6, count 2 2006.201.11:22:28.03#ibcon#read 5, iclass 6, count 2 2006.201.11:22:28.03#ibcon#about to read 6, iclass 6, count 2 2006.201.11:22:28.03#ibcon#read 6, iclass 6, count 2 2006.201.11:22:28.03#ibcon#end of sib2, iclass 6, count 2 2006.201.11:22:28.03#ibcon#*after write, iclass 6, count 2 2006.201.11:22:28.03#ibcon#*before return 0, iclass 6, count 2 2006.201.11:22:28.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:28.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:28.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.11:22:28.03#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:28.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:28.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:28.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:28.15#ibcon#enter wrdev, iclass 6, count 0 2006.201.11:22:28.15#ibcon#first serial, iclass 6, count 0 2006.201.11:22:28.15#ibcon#enter sib2, iclass 6, count 0 2006.201.11:22:28.15#ibcon#flushed, iclass 6, count 0 2006.201.11:22:28.15#ibcon#about to write, iclass 6, count 0 2006.201.11:22:28.15#ibcon#wrote, iclass 6, count 0 2006.201.11:22:28.15#ibcon#about to read 3, iclass 6, count 0 2006.201.11:22:28.17#ibcon#read 3, iclass 6, count 0 2006.201.11:22:28.17#ibcon#about to read 4, iclass 6, count 0 2006.201.11:22:28.17#ibcon#read 4, iclass 6, count 0 2006.201.11:22:28.17#ibcon#about to read 5, iclass 6, count 0 2006.201.11:22:28.17#ibcon#read 5, iclass 6, count 0 2006.201.11:22:28.17#ibcon#about to read 6, iclass 6, count 0 2006.201.11:22:28.17#ibcon#read 6, iclass 6, count 0 2006.201.11:22:28.17#ibcon#end of sib2, iclass 6, count 0 2006.201.11:22:28.17#ibcon#*mode == 0, iclass 6, count 0 2006.201.11:22:28.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.11:22:28.17#ibcon#[25=USB\r\n] 2006.201.11:22:28.17#ibcon#*before write, iclass 6, count 0 2006.201.11:22:28.17#ibcon#enter sib2, iclass 6, count 0 2006.201.11:22:28.17#ibcon#flushed, iclass 6, count 0 2006.201.11:22:28.17#ibcon#about to write, iclass 6, count 0 2006.201.11:22:28.17#ibcon#wrote, iclass 6, count 0 2006.201.11:22:28.17#ibcon#about to read 3, iclass 6, count 0 2006.201.11:22:28.20#ibcon#read 3, iclass 6, count 0 2006.201.11:22:28.20#ibcon#about to read 4, iclass 6, count 0 2006.201.11:22:28.20#ibcon#read 4, iclass 6, count 0 2006.201.11:22:28.20#ibcon#about to read 5, iclass 6, count 0 2006.201.11:22:28.20#ibcon#read 5, iclass 6, count 0 2006.201.11:22:28.20#ibcon#about to read 6, iclass 6, count 0 2006.201.11:22:28.20#ibcon#read 6, iclass 6, count 0 2006.201.11:22:28.20#ibcon#end of sib2, iclass 6, count 0 2006.201.11:22:28.20#ibcon#*after write, iclass 6, count 0 2006.201.11:22:28.20#ibcon#*before return 0, iclass 6, count 0 2006.201.11:22:28.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:28.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:28.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.11:22:28.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.11:22:28.20$vck44/valo=5,734.99 2006.201.11:22:28.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.11:22:28.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.11:22:28.20#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:28.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:28.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:28.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:28.20#ibcon#enter wrdev, iclass 10, count 0 2006.201.11:22:28.20#ibcon#first serial, iclass 10, count 0 2006.201.11:22:28.20#ibcon#enter sib2, iclass 10, count 0 2006.201.11:22:28.20#ibcon#flushed, iclass 10, count 0 2006.201.11:22:28.20#ibcon#about to write, iclass 10, count 0 2006.201.11:22:28.20#ibcon#wrote, iclass 10, count 0 2006.201.11:22:28.20#ibcon#about to read 3, iclass 10, count 0 2006.201.11:22:28.22#ibcon#read 3, iclass 10, count 0 2006.201.11:22:28.22#ibcon#about to read 4, iclass 10, count 0 2006.201.11:22:28.22#ibcon#read 4, iclass 10, count 0 2006.201.11:22:28.22#ibcon#about to read 5, iclass 10, count 0 2006.201.11:22:28.22#ibcon#read 5, iclass 10, count 0 2006.201.11:22:28.22#ibcon#about to read 6, iclass 10, count 0 2006.201.11:22:28.22#ibcon#read 6, iclass 10, count 0 2006.201.11:22:28.22#ibcon#end of sib2, iclass 10, count 0 2006.201.11:22:28.22#ibcon#*mode == 0, iclass 10, count 0 2006.201.11:22:28.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.11:22:28.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:22:28.22#ibcon#*before write, iclass 10, count 0 2006.201.11:22:28.22#ibcon#enter sib2, iclass 10, count 0 2006.201.11:22:28.22#ibcon#flushed, iclass 10, count 0 2006.201.11:22:28.22#ibcon#about to write, iclass 10, count 0 2006.201.11:22:28.22#ibcon#wrote, iclass 10, count 0 2006.201.11:22:28.22#ibcon#about to read 3, iclass 10, count 0 2006.201.11:22:28.26#ibcon#read 3, iclass 10, count 0 2006.201.11:22:28.26#ibcon#about to read 4, iclass 10, count 0 2006.201.11:22:28.26#ibcon#read 4, iclass 10, count 0 2006.201.11:22:28.26#ibcon#about to read 5, iclass 10, count 0 2006.201.11:22:28.26#ibcon#read 5, iclass 10, count 0 2006.201.11:22:28.26#ibcon#about to read 6, iclass 10, count 0 2006.201.11:22:28.26#ibcon#read 6, iclass 10, count 0 2006.201.11:22:28.26#ibcon#end of sib2, iclass 10, count 0 2006.201.11:22:28.26#ibcon#*after write, iclass 10, count 0 2006.201.11:22:28.26#ibcon#*before return 0, iclass 10, count 0 2006.201.11:22:28.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:28.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:28.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.11:22:28.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.11:22:28.26$vck44/va=5,4 2006.201.11:22:28.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.11:22:28.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.11:22:28.26#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:28.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:28.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:28.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:28.32#ibcon#enter wrdev, iclass 12, count 2 2006.201.11:22:28.32#ibcon#first serial, iclass 12, count 2 2006.201.11:22:28.32#ibcon#enter sib2, iclass 12, count 2 2006.201.11:22:28.32#ibcon#flushed, iclass 12, count 2 2006.201.11:22:28.32#ibcon#about to write, iclass 12, count 2 2006.201.11:22:28.32#ibcon#wrote, iclass 12, count 2 2006.201.11:22:28.32#ibcon#about to read 3, iclass 12, count 2 2006.201.11:22:28.34#ibcon#read 3, iclass 12, count 2 2006.201.11:22:28.34#ibcon#about to read 4, iclass 12, count 2 2006.201.11:22:28.34#ibcon#read 4, iclass 12, count 2 2006.201.11:22:28.34#ibcon#about to read 5, iclass 12, count 2 2006.201.11:22:28.34#ibcon#read 5, iclass 12, count 2 2006.201.11:22:28.34#ibcon#about to read 6, iclass 12, count 2 2006.201.11:22:28.34#ibcon#read 6, iclass 12, count 2 2006.201.11:22:28.34#ibcon#end of sib2, iclass 12, count 2 2006.201.11:22:28.34#ibcon#*mode == 0, iclass 12, count 2 2006.201.11:22:28.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.11:22:28.34#ibcon#[25=AT05-04\r\n] 2006.201.11:22:28.34#ibcon#*before write, iclass 12, count 2 2006.201.11:22:28.34#ibcon#enter sib2, iclass 12, count 2 2006.201.11:22:28.34#ibcon#flushed, iclass 12, count 2 2006.201.11:22:28.34#ibcon#about to write, iclass 12, count 2 2006.201.11:22:28.34#ibcon#wrote, iclass 12, count 2 2006.201.11:22:28.34#ibcon#about to read 3, iclass 12, count 2 2006.201.11:22:28.37#ibcon#read 3, iclass 12, count 2 2006.201.11:22:28.37#ibcon#about to read 4, iclass 12, count 2 2006.201.11:22:28.37#ibcon#read 4, iclass 12, count 2 2006.201.11:22:28.37#ibcon#about to read 5, iclass 12, count 2 2006.201.11:22:28.37#ibcon#read 5, iclass 12, count 2 2006.201.11:22:28.37#ibcon#about to read 6, iclass 12, count 2 2006.201.11:22:28.37#ibcon#read 6, iclass 12, count 2 2006.201.11:22:28.37#ibcon#end of sib2, iclass 12, count 2 2006.201.11:22:28.37#ibcon#*after write, iclass 12, count 2 2006.201.11:22:28.37#ibcon#*before return 0, iclass 12, count 2 2006.201.11:22:28.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:28.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:28.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.11:22:28.37#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:28.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:28.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:28.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:28.49#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:22:28.49#ibcon#first serial, iclass 12, count 0 2006.201.11:22:28.49#ibcon#enter sib2, iclass 12, count 0 2006.201.11:22:28.49#ibcon#flushed, iclass 12, count 0 2006.201.11:22:28.49#ibcon#about to write, iclass 12, count 0 2006.201.11:22:28.49#ibcon#wrote, iclass 12, count 0 2006.201.11:22:28.49#ibcon#about to read 3, iclass 12, count 0 2006.201.11:22:28.51#ibcon#read 3, iclass 12, count 0 2006.201.11:22:28.51#ibcon#about to read 4, iclass 12, count 0 2006.201.11:22:28.51#ibcon#read 4, iclass 12, count 0 2006.201.11:22:28.51#ibcon#about to read 5, iclass 12, count 0 2006.201.11:22:28.51#ibcon#read 5, iclass 12, count 0 2006.201.11:22:28.51#ibcon#about to read 6, iclass 12, count 0 2006.201.11:22:28.51#ibcon#read 6, iclass 12, count 0 2006.201.11:22:28.51#ibcon#end of sib2, iclass 12, count 0 2006.201.11:22:28.51#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:22:28.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:22:28.51#ibcon#[25=USB\r\n] 2006.201.11:22:28.51#ibcon#*before write, iclass 12, count 0 2006.201.11:22:28.51#ibcon#enter sib2, iclass 12, count 0 2006.201.11:22:28.51#ibcon#flushed, iclass 12, count 0 2006.201.11:22:28.51#ibcon#about to write, iclass 12, count 0 2006.201.11:22:28.51#ibcon#wrote, iclass 12, count 0 2006.201.11:22:28.51#ibcon#about to read 3, iclass 12, count 0 2006.201.11:22:28.54#ibcon#read 3, iclass 12, count 0 2006.201.11:22:28.54#ibcon#about to read 4, iclass 12, count 0 2006.201.11:22:28.54#ibcon#read 4, iclass 12, count 0 2006.201.11:22:28.54#ibcon#about to read 5, iclass 12, count 0 2006.201.11:22:28.54#ibcon#read 5, iclass 12, count 0 2006.201.11:22:28.54#ibcon#about to read 6, iclass 12, count 0 2006.201.11:22:28.54#ibcon#read 6, iclass 12, count 0 2006.201.11:22:28.54#ibcon#end of sib2, iclass 12, count 0 2006.201.11:22:28.54#ibcon#*after write, iclass 12, count 0 2006.201.11:22:28.54#ibcon#*before return 0, iclass 12, count 0 2006.201.11:22:28.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:28.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:28.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:22:28.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:22:28.54$vck44/valo=6,814.99 2006.201.11:22:28.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.11:22:28.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.11:22:28.54#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:28.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:28.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:28.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:28.54#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:22:28.54#ibcon#first serial, iclass 14, count 0 2006.201.11:22:28.54#ibcon#enter sib2, iclass 14, count 0 2006.201.11:22:28.54#ibcon#flushed, iclass 14, count 0 2006.201.11:22:28.54#ibcon#about to write, iclass 14, count 0 2006.201.11:22:28.54#ibcon#wrote, iclass 14, count 0 2006.201.11:22:28.54#ibcon#about to read 3, iclass 14, count 0 2006.201.11:22:28.56#ibcon#read 3, iclass 14, count 0 2006.201.11:22:28.56#ibcon#about to read 4, iclass 14, count 0 2006.201.11:22:28.56#ibcon#read 4, iclass 14, count 0 2006.201.11:22:28.56#ibcon#about to read 5, iclass 14, count 0 2006.201.11:22:28.56#ibcon#read 5, iclass 14, count 0 2006.201.11:22:28.56#ibcon#about to read 6, iclass 14, count 0 2006.201.11:22:28.56#ibcon#read 6, iclass 14, count 0 2006.201.11:22:28.56#ibcon#end of sib2, iclass 14, count 0 2006.201.11:22:28.56#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:22:28.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:22:28.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:22:28.56#ibcon#*before write, iclass 14, count 0 2006.201.11:22:28.56#ibcon#enter sib2, iclass 14, count 0 2006.201.11:22:28.56#ibcon#flushed, iclass 14, count 0 2006.201.11:22:28.56#ibcon#about to write, iclass 14, count 0 2006.201.11:22:28.56#ibcon#wrote, iclass 14, count 0 2006.201.11:22:28.56#ibcon#about to read 3, iclass 14, count 0 2006.201.11:22:28.61#ibcon#read 3, iclass 14, count 0 2006.201.11:22:28.61#ibcon#about to read 4, iclass 14, count 0 2006.201.11:22:28.61#ibcon#read 4, iclass 14, count 0 2006.201.11:22:28.61#ibcon#about to read 5, iclass 14, count 0 2006.201.11:22:28.61#ibcon#read 5, iclass 14, count 0 2006.201.11:22:28.61#ibcon#about to read 6, iclass 14, count 0 2006.201.11:22:28.61#ibcon#read 6, iclass 14, count 0 2006.201.11:22:28.61#ibcon#end of sib2, iclass 14, count 0 2006.201.11:22:28.61#ibcon#*after write, iclass 14, count 0 2006.201.11:22:28.61#ibcon#*before return 0, iclass 14, count 0 2006.201.11:22:28.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:28.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:28.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:22:28.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:22:28.61$vck44/va=6,5 2006.201.11:22:28.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.11:22:28.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.11:22:28.61#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:28.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:28.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:28.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:28.66#ibcon#enter wrdev, iclass 16, count 2 2006.201.11:22:28.66#ibcon#first serial, iclass 16, count 2 2006.201.11:22:28.66#ibcon#enter sib2, iclass 16, count 2 2006.201.11:22:28.66#ibcon#flushed, iclass 16, count 2 2006.201.11:22:28.66#ibcon#about to write, iclass 16, count 2 2006.201.11:22:28.66#ibcon#wrote, iclass 16, count 2 2006.201.11:22:28.66#ibcon#about to read 3, iclass 16, count 2 2006.201.11:22:28.68#ibcon#read 3, iclass 16, count 2 2006.201.11:22:28.68#ibcon#about to read 4, iclass 16, count 2 2006.201.11:22:28.68#ibcon#read 4, iclass 16, count 2 2006.201.11:22:28.68#ibcon#about to read 5, iclass 16, count 2 2006.201.11:22:28.68#ibcon#read 5, iclass 16, count 2 2006.201.11:22:28.68#ibcon#about to read 6, iclass 16, count 2 2006.201.11:22:28.68#ibcon#read 6, iclass 16, count 2 2006.201.11:22:28.68#ibcon#end of sib2, iclass 16, count 2 2006.201.11:22:28.68#ibcon#*mode == 0, iclass 16, count 2 2006.201.11:22:28.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.11:22:28.68#ibcon#[25=AT06-05\r\n] 2006.201.11:22:28.68#ibcon#*before write, iclass 16, count 2 2006.201.11:22:28.68#ibcon#enter sib2, iclass 16, count 2 2006.201.11:22:28.68#ibcon#flushed, iclass 16, count 2 2006.201.11:22:28.68#ibcon#about to write, iclass 16, count 2 2006.201.11:22:28.68#ibcon#wrote, iclass 16, count 2 2006.201.11:22:28.68#ibcon#about to read 3, iclass 16, count 2 2006.201.11:22:28.71#ibcon#read 3, iclass 16, count 2 2006.201.11:22:28.71#ibcon#about to read 4, iclass 16, count 2 2006.201.11:22:28.71#ibcon#read 4, iclass 16, count 2 2006.201.11:22:28.71#ibcon#about to read 5, iclass 16, count 2 2006.201.11:22:28.71#ibcon#read 5, iclass 16, count 2 2006.201.11:22:28.71#ibcon#about to read 6, iclass 16, count 2 2006.201.11:22:28.71#ibcon#read 6, iclass 16, count 2 2006.201.11:22:28.71#ibcon#end of sib2, iclass 16, count 2 2006.201.11:22:28.71#ibcon#*after write, iclass 16, count 2 2006.201.11:22:28.71#ibcon#*before return 0, iclass 16, count 2 2006.201.11:22:28.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:28.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:28.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.11:22:28.71#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:28.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:28.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:28.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:28.83#ibcon#enter wrdev, iclass 16, count 0 2006.201.11:22:28.83#ibcon#first serial, iclass 16, count 0 2006.201.11:22:28.83#ibcon#enter sib2, iclass 16, count 0 2006.201.11:22:28.83#ibcon#flushed, iclass 16, count 0 2006.201.11:22:28.83#ibcon#about to write, iclass 16, count 0 2006.201.11:22:28.83#ibcon#wrote, iclass 16, count 0 2006.201.11:22:28.83#ibcon#about to read 3, iclass 16, count 0 2006.201.11:22:28.85#ibcon#read 3, iclass 16, count 0 2006.201.11:22:28.85#ibcon#about to read 4, iclass 16, count 0 2006.201.11:22:28.85#ibcon#read 4, iclass 16, count 0 2006.201.11:22:28.85#ibcon#about to read 5, iclass 16, count 0 2006.201.11:22:28.85#ibcon#read 5, iclass 16, count 0 2006.201.11:22:28.85#ibcon#about to read 6, iclass 16, count 0 2006.201.11:22:28.85#ibcon#read 6, iclass 16, count 0 2006.201.11:22:28.85#ibcon#end of sib2, iclass 16, count 0 2006.201.11:22:28.85#ibcon#*mode == 0, iclass 16, count 0 2006.201.11:22:28.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.11:22:28.85#ibcon#[25=USB\r\n] 2006.201.11:22:28.85#ibcon#*before write, iclass 16, count 0 2006.201.11:22:28.85#ibcon#enter sib2, iclass 16, count 0 2006.201.11:22:28.85#ibcon#flushed, iclass 16, count 0 2006.201.11:22:28.85#ibcon#about to write, iclass 16, count 0 2006.201.11:22:28.85#ibcon#wrote, iclass 16, count 0 2006.201.11:22:28.85#ibcon#about to read 3, iclass 16, count 0 2006.201.11:22:28.88#ibcon#read 3, iclass 16, count 0 2006.201.11:22:28.88#ibcon#about to read 4, iclass 16, count 0 2006.201.11:22:28.88#ibcon#read 4, iclass 16, count 0 2006.201.11:22:28.88#ibcon#about to read 5, iclass 16, count 0 2006.201.11:22:28.88#ibcon#read 5, iclass 16, count 0 2006.201.11:22:28.88#ibcon#about to read 6, iclass 16, count 0 2006.201.11:22:28.88#ibcon#read 6, iclass 16, count 0 2006.201.11:22:28.88#ibcon#end of sib2, iclass 16, count 0 2006.201.11:22:28.88#ibcon#*after write, iclass 16, count 0 2006.201.11:22:28.88#ibcon#*before return 0, iclass 16, count 0 2006.201.11:22:28.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:28.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:28.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.11:22:28.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.11:22:28.88$vck44/valo=7,864.99 2006.201.11:22:28.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.11:22:28.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.11:22:28.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:28.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:28.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:28.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:28.88#ibcon#enter wrdev, iclass 18, count 0 2006.201.11:22:28.88#ibcon#first serial, iclass 18, count 0 2006.201.11:22:28.88#ibcon#enter sib2, iclass 18, count 0 2006.201.11:22:28.88#ibcon#flushed, iclass 18, count 0 2006.201.11:22:28.88#ibcon#about to write, iclass 18, count 0 2006.201.11:22:28.88#ibcon#wrote, iclass 18, count 0 2006.201.11:22:28.88#ibcon#about to read 3, iclass 18, count 0 2006.201.11:22:28.90#ibcon#read 3, iclass 18, count 0 2006.201.11:22:28.90#ibcon#about to read 4, iclass 18, count 0 2006.201.11:22:28.90#ibcon#read 4, iclass 18, count 0 2006.201.11:22:28.90#ibcon#about to read 5, iclass 18, count 0 2006.201.11:22:28.90#ibcon#read 5, iclass 18, count 0 2006.201.11:22:28.90#ibcon#about to read 6, iclass 18, count 0 2006.201.11:22:28.90#ibcon#read 6, iclass 18, count 0 2006.201.11:22:28.90#ibcon#end of sib2, iclass 18, count 0 2006.201.11:22:28.90#ibcon#*mode == 0, iclass 18, count 0 2006.201.11:22:28.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.11:22:28.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:22:28.90#ibcon#*before write, iclass 18, count 0 2006.201.11:22:28.90#ibcon#enter sib2, iclass 18, count 0 2006.201.11:22:28.90#ibcon#flushed, iclass 18, count 0 2006.201.11:22:28.90#ibcon#about to write, iclass 18, count 0 2006.201.11:22:28.90#ibcon#wrote, iclass 18, count 0 2006.201.11:22:28.90#ibcon#about to read 3, iclass 18, count 0 2006.201.11:22:28.95#ibcon#read 3, iclass 18, count 0 2006.201.11:22:28.95#ibcon#about to read 4, iclass 18, count 0 2006.201.11:22:28.95#ibcon#read 4, iclass 18, count 0 2006.201.11:22:28.95#ibcon#about to read 5, iclass 18, count 0 2006.201.11:22:28.95#ibcon#read 5, iclass 18, count 0 2006.201.11:22:28.95#ibcon#about to read 6, iclass 18, count 0 2006.201.11:22:28.95#ibcon#read 6, iclass 18, count 0 2006.201.11:22:28.95#ibcon#end of sib2, iclass 18, count 0 2006.201.11:22:28.95#ibcon#*after write, iclass 18, count 0 2006.201.11:22:28.95#ibcon#*before return 0, iclass 18, count 0 2006.201.11:22:28.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:28.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:28.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.11:22:28.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.11:22:28.95$vck44/va=7,5 2006.201.11:22:28.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.11:22:28.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.11:22:28.95#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:28.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:29.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:29.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:29.00#ibcon#enter wrdev, iclass 20, count 2 2006.201.11:22:29.00#ibcon#first serial, iclass 20, count 2 2006.201.11:22:29.00#ibcon#enter sib2, iclass 20, count 2 2006.201.11:22:29.00#ibcon#flushed, iclass 20, count 2 2006.201.11:22:29.00#ibcon#about to write, iclass 20, count 2 2006.201.11:22:29.00#ibcon#wrote, iclass 20, count 2 2006.201.11:22:29.00#ibcon#about to read 3, iclass 20, count 2 2006.201.11:22:29.02#ibcon#read 3, iclass 20, count 2 2006.201.11:22:29.02#ibcon#about to read 4, iclass 20, count 2 2006.201.11:22:29.02#ibcon#read 4, iclass 20, count 2 2006.201.11:22:29.02#ibcon#about to read 5, iclass 20, count 2 2006.201.11:22:29.02#ibcon#read 5, iclass 20, count 2 2006.201.11:22:29.02#ibcon#about to read 6, iclass 20, count 2 2006.201.11:22:29.02#ibcon#read 6, iclass 20, count 2 2006.201.11:22:29.02#ibcon#end of sib2, iclass 20, count 2 2006.201.11:22:29.02#ibcon#*mode == 0, iclass 20, count 2 2006.201.11:22:29.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.11:22:29.02#ibcon#[25=AT07-05\r\n] 2006.201.11:22:29.02#ibcon#*before write, iclass 20, count 2 2006.201.11:22:29.02#ibcon#enter sib2, iclass 20, count 2 2006.201.11:22:29.02#ibcon#flushed, iclass 20, count 2 2006.201.11:22:29.02#ibcon#about to write, iclass 20, count 2 2006.201.11:22:29.02#ibcon#wrote, iclass 20, count 2 2006.201.11:22:29.02#ibcon#about to read 3, iclass 20, count 2 2006.201.11:22:29.05#ibcon#read 3, iclass 20, count 2 2006.201.11:22:29.05#ibcon#about to read 4, iclass 20, count 2 2006.201.11:22:29.05#ibcon#read 4, iclass 20, count 2 2006.201.11:22:29.05#ibcon#about to read 5, iclass 20, count 2 2006.201.11:22:29.05#ibcon#read 5, iclass 20, count 2 2006.201.11:22:29.05#ibcon#about to read 6, iclass 20, count 2 2006.201.11:22:29.05#ibcon#read 6, iclass 20, count 2 2006.201.11:22:29.05#ibcon#end of sib2, iclass 20, count 2 2006.201.11:22:29.05#ibcon#*after write, iclass 20, count 2 2006.201.11:22:29.05#ibcon#*before return 0, iclass 20, count 2 2006.201.11:22:29.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:29.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:29.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.11:22:29.05#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:29.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:29.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:29.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:29.17#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:22:29.17#ibcon#first serial, iclass 20, count 0 2006.201.11:22:29.17#ibcon#enter sib2, iclass 20, count 0 2006.201.11:22:29.17#ibcon#flushed, iclass 20, count 0 2006.201.11:22:29.17#ibcon#about to write, iclass 20, count 0 2006.201.11:22:29.17#ibcon#wrote, iclass 20, count 0 2006.201.11:22:29.17#ibcon#about to read 3, iclass 20, count 0 2006.201.11:22:29.20#ibcon#read 3, iclass 20, count 0 2006.201.11:22:29.20#ibcon#about to read 4, iclass 20, count 0 2006.201.11:22:29.20#ibcon#read 4, iclass 20, count 0 2006.201.11:22:29.20#ibcon#about to read 5, iclass 20, count 0 2006.201.11:22:29.20#ibcon#read 5, iclass 20, count 0 2006.201.11:22:29.20#ibcon#about to read 6, iclass 20, count 0 2006.201.11:22:29.20#ibcon#read 6, iclass 20, count 0 2006.201.11:22:29.20#ibcon#end of sib2, iclass 20, count 0 2006.201.11:22:29.20#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:22:29.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:22:29.20#ibcon#[25=USB\r\n] 2006.201.11:22:29.20#ibcon#*before write, iclass 20, count 0 2006.201.11:22:29.20#ibcon#enter sib2, iclass 20, count 0 2006.201.11:22:29.20#ibcon#flushed, iclass 20, count 0 2006.201.11:22:29.20#ibcon#about to write, iclass 20, count 0 2006.201.11:22:29.20#ibcon#wrote, iclass 20, count 0 2006.201.11:22:29.20#ibcon#about to read 3, iclass 20, count 0 2006.201.11:22:29.23#ibcon#read 3, iclass 20, count 0 2006.201.11:22:29.23#ibcon#about to read 4, iclass 20, count 0 2006.201.11:22:29.23#ibcon#read 4, iclass 20, count 0 2006.201.11:22:29.23#ibcon#about to read 5, iclass 20, count 0 2006.201.11:22:29.23#ibcon#read 5, iclass 20, count 0 2006.201.11:22:29.23#ibcon#about to read 6, iclass 20, count 0 2006.201.11:22:29.23#ibcon#read 6, iclass 20, count 0 2006.201.11:22:29.23#ibcon#end of sib2, iclass 20, count 0 2006.201.11:22:29.23#ibcon#*after write, iclass 20, count 0 2006.201.11:22:29.23#ibcon#*before return 0, iclass 20, count 0 2006.201.11:22:29.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:29.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:29.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:22:29.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:22:29.23$vck44/valo=8,884.99 2006.201.11:22:29.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.11:22:29.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.11:22:29.23#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:29.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:29.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:29.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:29.23#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:22:29.23#ibcon#first serial, iclass 22, count 0 2006.201.11:22:29.23#ibcon#enter sib2, iclass 22, count 0 2006.201.11:22:29.23#ibcon#flushed, iclass 22, count 0 2006.201.11:22:29.23#ibcon#about to write, iclass 22, count 0 2006.201.11:22:29.23#ibcon#wrote, iclass 22, count 0 2006.201.11:22:29.23#ibcon#about to read 3, iclass 22, count 0 2006.201.11:22:29.25#ibcon#read 3, iclass 22, count 0 2006.201.11:22:29.25#ibcon#about to read 4, iclass 22, count 0 2006.201.11:22:29.25#ibcon#read 4, iclass 22, count 0 2006.201.11:22:29.25#ibcon#about to read 5, iclass 22, count 0 2006.201.11:22:29.25#ibcon#read 5, iclass 22, count 0 2006.201.11:22:29.25#ibcon#about to read 6, iclass 22, count 0 2006.201.11:22:29.25#ibcon#read 6, iclass 22, count 0 2006.201.11:22:29.25#ibcon#end of sib2, iclass 22, count 0 2006.201.11:22:29.25#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:22:29.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:22:29.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:22:29.25#ibcon#*before write, iclass 22, count 0 2006.201.11:22:29.25#ibcon#enter sib2, iclass 22, count 0 2006.201.11:22:29.25#ibcon#flushed, iclass 22, count 0 2006.201.11:22:29.25#ibcon#about to write, iclass 22, count 0 2006.201.11:22:29.25#ibcon#wrote, iclass 22, count 0 2006.201.11:22:29.25#ibcon#about to read 3, iclass 22, count 0 2006.201.11:22:29.29#ibcon#read 3, iclass 22, count 0 2006.201.11:22:29.29#ibcon#about to read 4, iclass 22, count 0 2006.201.11:22:29.29#ibcon#read 4, iclass 22, count 0 2006.201.11:22:29.29#ibcon#about to read 5, iclass 22, count 0 2006.201.11:22:29.29#ibcon#read 5, iclass 22, count 0 2006.201.11:22:29.29#ibcon#about to read 6, iclass 22, count 0 2006.201.11:22:29.29#ibcon#read 6, iclass 22, count 0 2006.201.11:22:29.29#ibcon#end of sib2, iclass 22, count 0 2006.201.11:22:29.29#ibcon#*after write, iclass 22, count 0 2006.201.11:22:29.29#ibcon#*before return 0, iclass 22, count 0 2006.201.11:22:29.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:29.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:29.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:22:29.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:22:29.29$vck44/va=8,4 2006.201.11:22:29.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.11:22:29.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.11:22:29.29#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:29.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:22:29.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:22:29.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:22:29.35#ibcon#enter wrdev, iclass 24, count 2 2006.201.11:22:29.35#ibcon#first serial, iclass 24, count 2 2006.201.11:22:29.35#ibcon#enter sib2, iclass 24, count 2 2006.201.11:22:29.35#ibcon#flushed, iclass 24, count 2 2006.201.11:22:29.35#ibcon#about to write, iclass 24, count 2 2006.201.11:22:29.35#ibcon#wrote, iclass 24, count 2 2006.201.11:22:29.35#ibcon#about to read 3, iclass 24, count 2 2006.201.11:22:29.37#ibcon#read 3, iclass 24, count 2 2006.201.11:22:29.37#ibcon#about to read 4, iclass 24, count 2 2006.201.11:22:29.37#ibcon#read 4, iclass 24, count 2 2006.201.11:22:29.37#ibcon#about to read 5, iclass 24, count 2 2006.201.11:22:29.37#ibcon#read 5, iclass 24, count 2 2006.201.11:22:29.37#ibcon#about to read 6, iclass 24, count 2 2006.201.11:22:29.37#ibcon#read 6, iclass 24, count 2 2006.201.11:22:29.37#ibcon#end of sib2, iclass 24, count 2 2006.201.11:22:29.37#ibcon#*mode == 0, iclass 24, count 2 2006.201.11:22:29.37#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.11:22:29.37#ibcon#[25=AT08-04\r\n] 2006.201.11:22:29.37#ibcon#*before write, iclass 24, count 2 2006.201.11:22:29.37#ibcon#enter sib2, iclass 24, count 2 2006.201.11:22:29.37#ibcon#flushed, iclass 24, count 2 2006.201.11:22:29.37#ibcon#about to write, iclass 24, count 2 2006.201.11:22:29.37#ibcon#wrote, iclass 24, count 2 2006.201.11:22:29.37#ibcon#about to read 3, iclass 24, count 2 2006.201.11:22:29.40#ibcon#read 3, iclass 24, count 2 2006.201.11:22:29.40#ibcon#about to read 4, iclass 24, count 2 2006.201.11:22:29.40#ibcon#read 4, iclass 24, count 2 2006.201.11:22:29.40#ibcon#about to read 5, iclass 24, count 2 2006.201.11:22:29.40#ibcon#read 5, iclass 24, count 2 2006.201.11:22:29.40#ibcon#about to read 6, iclass 24, count 2 2006.201.11:22:29.40#ibcon#read 6, iclass 24, count 2 2006.201.11:22:29.40#ibcon#end of sib2, iclass 24, count 2 2006.201.11:22:29.40#ibcon#*after write, iclass 24, count 2 2006.201.11:22:29.40#ibcon#*before return 0, iclass 24, count 2 2006.201.11:22:29.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:22:29.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:22:29.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.11:22:29.40#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:29.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:22:29.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:22:29.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:22:29.52#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:22:29.52#ibcon#first serial, iclass 24, count 0 2006.201.11:22:29.52#ibcon#enter sib2, iclass 24, count 0 2006.201.11:22:29.52#ibcon#flushed, iclass 24, count 0 2006.201.11:22:29.52#ibcon#about to write, iclass 24, count 0 2006.201.11:22:29.52#ibcon#wrote, iclass 24, count 0 2006.201.11:22:29.52#ibcon#about to read 3, iclass 24, count 0 2006.201.11:22:29.54#ibcon#read 3, iclass 24, count 0 2006.201.11:22:29.54#ibcon#about to read 4, iclass 24, count 0 2006.201.11:22:29.54#ibcon#read 4, iclass 24, count 0 2006.201.11:22:29.54#ibcon#about to read 5, iclass 24, count 0 2006.201.11:22:29.54#ibcon#read 5, iclass 24, count 0 2006.201.11:22:29.54#ibcon#about to read 6, iclass 24, count 0 2006.201.11:22:29.54#ibcon#read 6, iclass 24, count 0 2006.201.11:22:29.54#ibcon#end of sib2, iclass 24, count 0 2006.201.11:22:29.54#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:22:29.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:22:29.54#ibcon#[25=USB\r\n] 2006.201.11:22:29.54#ibcon#*before write, iclass 24, count 0 2006.201.11:22:29.54#ibcon#enter sib2, iclass 24, count 0 2006.201.11:22:29.54#ibcon#flushed, iclass 24, count 0 2006.201.11:22:29.54#ibcon#about to write, iclass 24, count 0 2006.201.11:22:29.54#ibcon#wrote, iclass 24, count 0 2006.201.11:22:29.54#ibcon#about to read 3, iclass 24, count 0 2006.201.11:22:29.57#ibcon#read 3, iclass 24, count 0 2006.201.11:22:29.57#ibcon#about to read 4, iclass 24, count 0 2006.201.11:22:29.57#ibcon#read 4, iclass 24, count 0 2006.201.11:22:29.57#ibcon#about to read 5, iclass 24, count 0 2006.201.11:22:29.57#ibcon#read 5, iclass 24, count 0 2006.201.11:22:29.57#ibcon#about to read 6, iclass 24, count 0 2006.201.11:22:29.57#ibcon#read 6, iclass 24, count 0 2006.201.11:22:29.57#ibcon#end of sib2, iclass 24, count 0 2006.201.11:22:29.57#ibcon#*after write, iclass 24, count 0 2006.201.11:22:29.57#ibcon#*before return 0, iclass 24, count 0 2006.201.11:22:29.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:22:29.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:22:29.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:22:29.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:22:29.57$vck44/vblo=1,629.99 2006.201.11:22:29.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.11:22:29.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.11:22:29.57#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:29.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:22:29.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:22:29.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:22:29.57#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:22:29.57#ibcon#first serial, iclass 26, count 0 2006.201.11:22:29.57#ibcon#enter sib2, iclass 26, count 0 2006.201.11:22:29.57#ibcon#flushed, iclass 26, count 0 2006.201.11:22:29.57#ibcon#about to write, iclass 26, count 0 2006.201.11:22:29.57#ibcon#wrote, iclass 26, count 0 2006.201.11:22:29.57#ibcon#about to read 3, iclass 26, count 0 2006.201.11:22:29.59#ibcon#read 3, iclass 26, count 0 2006.201.11:22:29.59#ibcon#about to read 4, iclass 26, count 0 2006.201.11:22:29.59#ibcon#read 4, iclass 26, count 0 2006.201.11:22:29.59#ibcon#about to read 5, iclass 26, count 0 2006.201.11:22:29.59#ibcon#read 5, iclass 26, count 0 2006.201.11:22:29.59#ibcon#about to read 6, iclass 26, count 0 2006.201.11:22:29.59#ibcon#read 6, iclass 26, count 0 2006.201.11:22:29.59#ibcon#end of sib2, iclass 26, count 0 2006.201.11:22:29.59#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:22:29.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:22:29.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:22:29.59#ibcon#*before write, iclass 26, count 0 2006.201.11:22:29.59#ibcon#enter sib2, iclass 26, count 0 2006.201.11:22:29.59#ibcon#flushed, iclass 26, count 0 2006.201.11:22:29.59#ibcon#about to write, iclass 26, count 0 2006.201.11:22:29.59#ibcon#wrote, iclass 26, count 0 2006.201.11:22:29.59#ibcon#about to read 3, iclass 26, count 0 2006.201.11:22:29.64#ibcon#read 3, iclass 26, count 0 2006.201.11:22:29.64#ibcon#about to read 4, iclass 26, count 0 2006.201.11:22:29.64#ibcon#read 4, iclass 26, count 0 2006.201.11:22:29.64#ibcon#about to read 5, iclass 26, count 0 2006.201.11:22:29.64#ibcon#read 5, iclass 26, count 0 2006.201.11:22:29.64#ibcon#about to read 6, iclass 26, count 0 2006.201.11:22:29.64#ibcon#read 6, iclass 26, count 0 2006.201.11:22:29.64#ibcon#end of sib2, iclass 26, count 0 2006.201.11:22:29.64#ibcon#*after write, iclass 26, count 0 2006.201.11:22:29.64#ibcon#*before return 0, iclass 26, count 0 2006.201.11:22:29.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:22:29.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:22:29.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:22:29.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:22:29.64$vck44/vb=1,4 2006.201.11:22:29.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.11:22:29.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.11:22:29.64#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:29.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:22:29.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:22:29.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:22:29.64#ibcon#enter wrdev, iclass 28, count 2 2006.201.11:22:29.64#ibcon#first serial, iclass 28, count 2 2006.201.11:22:29.64#ibcon#enter sib2, iclass 28, count 2 2006.201.11:22:29.64#ibcon#flushed, iclass 28, count 2 2006.201.11:22:29.64#ibcon#about to write, iclass 28, count 2 2006.201.11:22:29.64#ibcon#wrote, iclass 28, count 2 2006.201.11:22:29.64#ibcon#about to read 3, iclass 28, count 2 2006.201.11:22:29.66#ibcon#read 3, iclass 28, count 2 2006.201.11:22:29.66#ibcon#about to read 4, iclass 28, count 2 2006.201.11:22:29.66#ibcon#read 4, iclass 28, count 2 2006.201.11:22:29.66#ibcon#about to read 5, iclass 28, count 2 2006.201.11:22:29.66#ibcon#read 5, iclass 28, count 2 2006.201.11:22:29.66#ibcon#about to read 6, iclass 28, count 2 2006.201.11:22:29.66#ibcon#read 6, iclass 28, count 2 2006.201.11:22:29.66#ibcon#end of sib2, iclass 28, count 2 2006.201.11:22:29.66#ibcon#*mode == 0, iclass 28, count 2 2006.201.11:22:29.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.11:22:29.66#ibcon#[27=AT01-04\r\n] 2006.201.11:22:29.66#ibcon#*before write, iclass 28, count 2 2006.201.11:22:29.66#ibcon#enter sib2, iclass 28, count 2 2006.201.11:22:29.66#ibcon#flushed, iclass 28, count 2 2006.201.11:22:29.66#ibcon#about to write, iclass 28, count 2 2006.201.11:22:29.66#ibcon#wrote, iclass 28, count 2 2006.201.11:22:29.66#ibcon#about to read 3, iclass 28, count 2 2006.201.11:22:29.69#ibcon#read 3, iclass 28, count 2 2006.201.11:22:29.69#ibcon#about to read 4, iclass 28, count 2 2006.201.11:22:29.69#ibcon#read 4, iclass 28, count 2 2006.201.11:22:29.69#ibcon#about to read 5, iclass 28, count 2 2006.201.11:22:29.69#ibcon#read 5, iclass 28, count 2 2006.201.11:22:29.69#ibcon#about to read 6, iclass 28, count 2 2006.201.11:22:29.69#ibcon#read 6, iclass 28, count 2 2006.201.11:22:29.69#ibcon#end of sib2, iclass 28, count 2 2006.201.11:22:29.69#ibcon#*after write, iclass 28, count 2 2006.201.11:22:29.69#ibcon#*before return 0, iclass 28, count 2 2006.201.11:22:29.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:22:29.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:22:29.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.11:22:29.69#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:29.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:22:29.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:22:29.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:22:29.81#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:22:29.81#ibcon#first serial, iclass 28, count 0 2006.201.11:22:29.81#ibcon#enter sib2, iclass 28, count 0 2006.201.11:22:29.81#ibcon#flushed, iclass 28, count 0 2006.201.11:22:29.81#ibcon#about to write, iclass 28, count 0 2006.201.11:22:29.81#ibcon#wrote, iclass 28, count 0 2006.201.11:22:29.81#ibcon#about to read 3, iclass 28, count 0 2006.201.11:22:29.83#ibcon#read 3, iclass 28, count 0 2006.201.11:22:29.83#ibcon#about to read 4, iclass 28, count 0 2006.201.11:22:29.83#ibcon#read 4, iclass 28, count 0 2006.201.11:22:29.83#ibcon#about to read 5, iclass 28, count 0 2006.201.11:22:29.83#ibcon#read 5, iclass 28, count 0 2006.201.11:22:29.83#ibcon#about to read 6, iclass 28, count 0 2006.201.11:22:29.83#ibcon#read 6, iclass 28, count 0 2006.201.11:22:29.83#ibcon#end of sib2, iclass 28, count 0 2006.201.11:22:29.83#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:22:29.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:22:29.83#ibcon#[27=USB\r\n] 2006.201.11:22:29.83#ibcon#*before write, iclass 28, count 0 2006.201.11:22:29.83#ibcon#enter sib2, iclass 28, count 0 2006.201.11:22:29.83#ibcon#flushed, iclass 28, count 0 2006.201.11:22:29.83#ibcon#about to write, iclass 28, count 0 2006.201.11:22:29.83#ibcon#wrote, iclass 28, count 0 2006.201.11:22:29.83#ibcon#about to read 3, iclass 28, count 0 2006.201.11:22:29.86#ibcon#read 3, iclass 28, count 0 2006.201.11:22:29.86#ibcon#about to read 4, iclass 28, count 0 2006.201.11:22:29.86#ibcon#read 4, iclass 28, count 0 2006.201.11:22:29.86#ibcon#about to read 5, iclass 28, count 0 2006.201.11:22:29.86#ibcon#read 5, iclass 28, count 0 2006.201.11:22:29.86#ibcon#about to read 6, iclass 28, count 0 2006.201.11:22:29.86#ibcon#read 6, iclass 28, count 0 2006.201.11:22:29.86#ibcon#end of sib2, iclass 28, count 0 2006.201.11:22:29.86#ibcon#*after write, iclass 28, count 0 2006.201.11:22:29.86#ibcon#*before return 0, iclass 28, count 0 2006.201.11:22:29.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:22:29.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:22:29.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:22:29.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:22:29.86$vck44/vblo=2,634.99 2006.201.11:22:29.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.11:22:29.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.11:22:29.86#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:29.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:29.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:29.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:29.86#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:22:29.86#ibcon#first serial, iclass 30, count 0 2006.201.11:22:29.86#ibcon#enter sib2, iclass 30, count 0 2006.201.11:22:29.86#ibcon#flushed, iclass 30, count 0 2006.201.11:22:29.86#ibcon#about to write, iclass 30, count 0 2006.201.11:22:29.86#ibcon#wrote, iclass 30, count 0 2006.201.11:22:29.86#ibcon#about to read 3, iclass 30, count 0 2006.201.11:22:29.88#ibcon#read 3, iclass 30, count 0 2006.201.11:22:29.88#ibcon#about to read 4, iclass 30, count 0 2006.201.11:22:29.88#ibcon#read 4, iclass 30, count 0 2006.201.11:22:29.88#ibcon#about to read 5, iclass 30, count 0 2006.201.11:22:29.88#ibcon#read 5, iclass 30, count 0 2006.201.11:22:29.88#ibcon#about to read 6, iclass 30, count 0 2006.201.11:22:29.88#ibcon#read 6, iclass 30, count 0 2006.201.11:22:29.88#ibcon#end of sib2, iclass 30, count 0 2006.201.11:22:29.88#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:22:29.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:22:29.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:22:29.88#ibcon#*before write, iclass 30, count 0 2006.201.11:22:29.88#ibcon#enter sib2, iclass 30, count 0 2006.201.11:22:29.88#ibcon#flushed, iclass 30, count 0 2006.201.11:22:29.88#ibcon#about to write, iclass 30, count 0 2006.201.11:22:29.88#ibcon#wrote, iclass 30, count 0 2006.201.11:22:29.88#ibcon#about to read 3, iclass 30, count 0 2006.201.11:22:29.92#ibcon#read 3, iclass 30, count 0 2006.201.11:22:29.92#ibcon#about to read 4, iclass 30, count 0 2006.201.11:22:29.92#ibcon#read 4, iclass 30, count 0 2006.201.11:22:29.92#ibcon#about to read 5, iclass 30, count 0 2006.201.11:22:29.92#ibcon#read 5, iclass 30, count 0 2006.201.11:22:29.92#ibcon#about to read 6, iclass 30, count 0 2006.201.11:22:29.92#ibcon#read 6, iclass 30, count 0 2006.201.11:22:29.92#ibcon#end of sib2, iclass 30, count 0 2006.201.11:22:29.92#ibcon#*after write, iclass 30, count 0 2006.201.11:22:29.92#ibcon#*before return 0, iclass 30, count 0 2006.201.11:22:29.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:29.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:22:29.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:22:29.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:22:29.92$vck44/vb=2,5 2006.201.11:22:29.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.11:22:29.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.11:22:29.92#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:29.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:29.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:29.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:29.98#ibcon#enter wrdev, iclass 32, count 2 2006.201.11:22:29.98#ibcon#first serial, iclass 32, count 2 2006.201.11:22:29.98#ibcon#enter sib2, iclass 32, count 2 2006.201.11:22:29.98#ibcon#flushed, iclass 32, count 2 2006.201.11:22:29.98#ibcon#about to write, iclass 32, count 2 2006.201.11:22:29.98#ibcon#wrote, iclass 32, count 2 2006.201.11:22:29.98#ibcon#about to read 3, iclass 32, count 2 2006.201.11:22:30.00#ibcon#read 3, iclass 32, count 2 2006.201.11:22:30.00#ibcon#about to read 4, iclass 32, count 2 2006.201.11:22:30.00#ibcon#read 4, iclass 32, count 2 2006.201.11:22:30.00#ibcon#about to read 5, iclass 32, count 2 2006.201.11:22:30.00#ibcon#read 5, iclass 32, count 2 2006.201.11:22:30.00#ibcon#about to read 6, iclass 32, count 2 2006.201.11:22:30.00#ibcon#read 6, iclass 32, count 2 2006.201.11:22:30.00#ibcon#end of sib2, iclass 32, count 2 2006.201.11:22:30.00#ibcon#*mode == 0, iclass 32, count 2 2006.201.11:22:30.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.11:22:30.00#ibcon#[27=AT02-05\r\n] 2006.201.11:22:30.00#ibcon#*before write, iclass 32, count 2 2006.201.11:22:30.00#ibcon#enter sib2, iclass 32, count 2 2006.201.11:22:30.00#ibcon#flushed, iclass 32, count 2 2006.201.11:22:30.00#ibcon#about to write, iclass 32, count 2 2006.201.11:22:30.00#ibcon#wrote, iclass 32, count 2 2006.201.11:22:30.00#ibcon#about to read 3, iclass 32, count 2 2006.201.11:22:30.03#ibcon#read 3, iclass 32, count 2 2006.201.11:22:30.03#ibcon#about to read 4, iclass 32, count 2 2006.201.11:22:30.03#ibcon#read 4, iclass 32, count 2 2006.201.11:22:30.03#ibcon#about to read 5, iclass 32, count 2 2006.201.11:22:30.03#ibcon#read 5, iclass 32, count 2 2006.201.11:22:30.03#ibcon#about to read 6, iclass 32, count 2 2006.201.11:22:30.03#ibcon#read 6, iclass 32, count 2 2006.201.11:22:30.03#ibcon#end of sib2, iclass 32, count 2 2006.201.11:22:30.03#ibcon#*after write, iclass 32, count 2 2006.201.11:22:30.03#ibcon#*before return 0, iclass 32, count 2 2006.201.11:22:30.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:30.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:22:30.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.11:22:30.03#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:30.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:30.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:30.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:30.15#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:22:30.15#ibcon#first serial, iclass 32, count 0 2006.201.11:22:30.15#ibcon#enter sib2, iclass 32, count 0 2006.201.11:22:30.15#ibcon#flushed, iclass 32, count 0 2006.201.11:22:30.15#ibcon#about to write, iclass 32, count 0 2006.201.11:22:30.15#ibcon#wrote, iclass 32, count 0 2006.201.11:22:30.15#ibcon#about to read 3, iclass 32, count 0 2006.201.11:22:30.17#ibcon#read 3, iclass 32, count 0 2006.201.11:22:30.17#ibcon#about to read 4, iclass 32, count 0 2006.201.11:22:30.17#ibcon#read 4, iclass 32, count 0 2006.201.11:22:30.17#ibcon#about to read 5, iclass 32, count 0 2006.201.11:22:30.17#ibcon#read 5, iclass 32, count 0 2006.201.11:22:30.17#ibcon#about to read 6, iclass 32, count 0 2006.201.11:22:30.17#ibcon#read 6, iclass 32, count 0 2006.201.11:22:30.17#ibcon#end of sib2, iclass 32, count 0 2006.201.11:22:30.17#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:22:30.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:22:30.17#ibcon#[27=USB\r\n] 2006.201.11:22:30.17#ibcon#*before write, iclass 32, count 0 2006.201.11:22:30.17#ibcon#enter sib2, iclass 32, count 0 2006.201.11:22:30.17#ibcon#flushed, iclass 32, count 0 2006.201.11:22:30.17#ibcon#about to write, iclass 32, count 0 2006.201.11:22:30.17#ibcon#wrote, iclass 32, count 0 2006.201.11:22:30.17#ibcon#about to read 3, iclass 32, count 0 2006.201.11:22:30.20#ibcon#read 3, iclass 32, count 0 2006.201.11:22:30.20#ibcon#about to read 4, iclass 32, count 0 2006.201.11:22:30.20#ibcon#read 4, iclass 32, count 0 2006.201.11:22:30.20#ibcon#about to read 5, iclass 32, count 0 2006.201.11:22:30.20#ibcon#read 5, iclass 32, count 0 2006.201.11:22:30.20#ibcon#about to read 6, iclass 32, count 0 2006.201.11:22:30.20#ibcon#read 6, iclass 32, count 0 2006.201.11:22:30.20#ibcon#end of sib2, iclass 32, count 0 2006.201.11:22:30.20#ibcon#*after write, iclass 32, count 0 2006.201.11:22:30.20#ibcon#*before return 0, iclass 32, count 0 2006.201.11:22:30.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:30.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:22:30.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:22:30.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:22:30.20$vck44/vblo=3,649.99 2006.201.11:22:30.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.11:22:30.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.11:22:30.20#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:30.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:30.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:30.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:30.20#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:22:30.20#ibcon#first serial, iclass 34, count 0 2006.201.11:22:30.20#ibcon#enter sib2, iclass 34, count 0 2006.201.11:22:30.20#ibcon#flushed, iclass 34, count 0 2006.201.11:22:30.20#ibcon#about to write, iclass 34, count 0 2006.201.11:22:30.20#ibcon#wrote, iclass 34, count 0 2006.201.11:22:30.20#ibcon#about to read 3, iclass 34, count 0 2006.201.11:22:30.22#ibcon#read 3, iclass 34, count 0 2006.201.11:22:30.22#ibcon#about to read 4, iclass 34, count 0 2006.201.11:22:30.22#ibcon#read 4, iclass 34, count 0 2006.201.11:22:30.22#ibcon#about to read 5, iclass 34, count 0 2006.201.11:22:30.22#ibcon#read 5, iclass 34, count 0 2006.201.11:22:30.22#ibcon#about to read 6, iclass 34, count 0 2006.201.11:22:30.22#ibcon#read 6, iclass 34, count 0 2006.201.11:22:30.22#ibcon#end of sib2, iclass 34, count 0 2006.201.11:22:30.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:22:30.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:22:30.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:22:30.22#ibcon#*before write, iclass 34, count 0 2006.201.11:22:30.22#ibcon#enter sib2, iclass 34, count 0 2006.201.11:22:30.22#ibcon#flushed, iclass 34, count 0 2006.201.11:22:30.22#ibcon#about to write, iclass 34, count 0 2006.201.11:22:30.22#ibcon#wrote, iclass 34, count 0 2006.201.11:22:30.22#ibcon#about to read 3, iclass 34, count 0 2006.201.11:22:30.26#ibcon#read 3, iclass 34, count 0 2006.201.11:22:30.26#ibcon#about to read 4, iclass 34, count 0 2006.201.11:22:30.26#ibcon#read 4, iclass 34, count 0 2006.201.11:22:30.26#ibcon#about to read 5, iclass 34, count 0 2006.201.11:22:30.26#ibcon#read 5, iclass 34, count 0 2006.201.11:22:30.26#ibcon#about to read 6, iclass 34, count 0 2006.201.11:22:30.26#ibcon#read 6, iclass 34, count 0 2006.201.11:22:30.26#ibcon#end of sib2, iclass 34, count 0 2006.201.11:22:30.26#ibcon#*after write, iclass 34, count 0 2006.201.11:22:30.26#ibcon#*before return 0, iclass 34, count 0 2006.201.11:22:30.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:30.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:22:30.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:22:30.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:22:30.26$vck44/vb=3,4 2006.201.11:22:30.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.11:22:30.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.11:22:30.26#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:30.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:30.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:30.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:30.32#ibcon#enter wrdev, iclass 36, count 2 2006.201.11:22:30.32#ibcon#first serial, iclass 36, count 2 2006.201.11:22:30.32#ibcon#enter sib2, iclass 36, count 2 2006.201.11:22:30.32#ibcon#flushed, iclass 36, count 2 2006.201.11:22:30.32#ibcon#about to write, iclass 36, count 2 2006.201.11:22:30.32#ibcon#wrote, iclass 36, count 2 2006.201.11:22:30.32#ibcon#about to read 3, iclass 36, count 2 2006.201.11:22:30.34#ibcon#read 3, iclass 36, count 2 2006.201.11:22:30.34#ibcon#about to read 4, iclass 36, count 2 2006.201.11:22:30.34#ibcon#read 4, iclass 36, count 2 2006.201.11:22:30.34#ibcon#about to read 5, iclass 36, count 2 2006.201.11:22:30.34#ibcon#read 5, iclass 36, count 2 2006.201.11:22:30.34#ibcon#about to read 6, iclass 36, count 2 2006.201.11:22:30.34#ibcon#read 6, iclass 36, count 2 2006.201.11:22:30.34#ibcon#end of sib2, iclass 36, count 2 2006.201.11:22:30.34#ibcon#*mode == 0, iclass 36, count 2 2006.201.11:22:30.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.11:22:30.34#ibcon#[27=AT03-04\r\n] 2006.201.11:22:30.34#ibcon#*before write, iclass 36, count 2 2006.201.11:22:30.34#ibcon#enter sib2, iclass 36, count 2 2006.201.11:22:30.34#ibcon#flushed, iclass 36, count 2 2006.201.11:22:30.34#ibcon#about to write, iclass 36, count 2 2006.201.11:22:30.34#ibcon#wrote, iclass 36, count 2 2006.201.11:22:30.34#ibcon#about to read 3, iclass 36, count 2 2006.201.11:22:30.37#ibcon#read 3, iclass 36, count 2 2006.201.11:22:30.37#ibcon#about to read 4, iclass 36, count 2 2006.201.11:22:30.37#ibcon#read 4, iclass 36, count 2 2006.201.11:22:30.37#ibcon#about to read 5, iclass 36, count 2 2006.201.11:22:30.37#ibcon#read 5, iclass 36, count 2 2006.201.11:22:30.37#ibcon#about to read 6, iclass 36, count 2 2006.201.11:22:30.37#ibcon#read 6, iclass 36, count 2 2006.201.11:22:30.37#ibcon#end of sib2, iclass 36, count 2 2006.201.11:22:30.37#ibcon#*after write, iclass 36, count 2 2006.201.11:22:30.37#ibcon#*before return 0, iclass 36, count 2 2006.201.11:22:30.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:30.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:22:30.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.11:22:30.37#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:30.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:30.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:30.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:30.49#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:22:30.49#ibcon#first serial, iclass 36, count 0 2006.201.11:22:30.49#ibcon#enter sib2, iclass 36, count 0 2006.201.11:22:30.49#ibcon#flushed, iclass 36, count 0 2006.201.11:22:30.49#ibcon#about to write, iclass 36, count 0 2006.201.11:22:30.49#ibcon#wrote, iclass 36, count 0 2006.201.11:22:30.49#ibcon#about to read 3, iclass 36, count 0 2006.201.11:22:30.51#ibcon#read 3, iclass 36, count 0 2006.201.11:22:30.51#ibcon#about to read 4, iclass 36, count 0 2006.201.11:22:30.51#ibcon#read 4, iclass 36, count 0 2006.201.11:22:30.51#ibcon#about to read 5, iclass 36, count 0 2006.201.11:22:30.51#ibcon#read 5, iclass 36, count 0 2006.201.11:22:30.51#ibcon#about to read 6, iclass 36, count 0 2006.201.11:22:30.51#ibcon#read 6, iclass 36, count 0 2006.201.11:22:30.51#ibcon#end of sib2, iclass 36, count 0 2006.201.11:22:30.51#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:22:30.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:22:30.51#ibcon#[27=USB\r\n] 2006.201.11:22:30.51#ibcon#*before write, iclass 36, count 0 2006.201.11:22:30.51#ibcon#enter sib2, iclass 36, count 0 2006.201.11:22:30.51#ibcon#flushed, iclass 36, count 0 2006.201.11:22:30.51#ibcon#about to write, iclass 36, count 0 2006.201.11:22:30.51#ibcon#wrote, iclass 36, count 0 2006.201.11:22:30.51#ibcon#about to read 3, iclass 36, count 0 2006.201.11:22:30.54#ibcon#read 3, iclass 36, count 0 2006.201.11:22:30.54#ibcon#about to read 4, iclass 36, count 0 2006.201.11:22:30.54#ibcon#read 4, iclass 36, count 0 2006.201.11:22:30.54#ibcon#about to read 5, iclass 36, count 0 2006.201.11:22:30.54#ibcon#read 5, iclass 36, count 0 2006.201.11:22:30.54#ibcon#about to read 6, iclass 36, count 0 2006.201.11:22:30.54#ibcon#read 6, iclass 36, count 0 2006.201.11:22:30.54#ibcon#end of sib2, iclass 36, count 0 2006.201.11:22:30.54#ibcon#*after write, iclass 36, count 0 2006.201.11:22:30.54#ibcon#*before return 0, iclass 36, count 0 2006.201.11:22:30.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:30.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:22:30.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:22:30.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:22:30.54$vck44/vblo=4,679.99 2006.201.11:22:30.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.11:22:30.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.11:22:30.54#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:30.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:30.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:30.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:30.54#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:22:30.54#ibcon#first serial, iclass 38, count 0 2006.201.11:22:30.54#ibcon#enter sib2, iclass 38, count 0 2006.201.11:22:30.54#ibcon#flushed, iclass 38, count 0 2006.201.11:22:30.54#ibcon#about to write, iclass 38, count 0 2006.201.11:22:30.54#ibcon#wrote, iclass 38, count 0 2006.201.11:22:30.54#ibcon#about to read 3, iclass 38, count 0 2006.201.11:22:30.56#ibcon#read 3, iclass 38, count 0 2006.201.11:22:30.56#ibcon#about to read 4, iclass 38, count 0 2006.201.11:22:30.56#ibcon#read 4, iclass 38, count 0 2006.201.11:22:30.56#ibcon#about to read 5, iclass 38, count 0 2006.201.11:22:30.56#ibcon#read 5, iclass 38, count 0 2006.201.11:22:30.56#ibcon#about to read 6, iclass 38, count 0 2006.201.11:22:30.56#ibcon#read 6, iclass 38, count 0 2006.201.11:22:30.56#ibcon#end of sib2, iclass 38, count 0 2006.201.11:22:30.56#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:22:30.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:22:30.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:22:30.56#ibcon#*before write, iclass 38, count 0 2006.201.11:22:30.56#ibcon#enter sib2, iclass 38, count 0 2006.201.11:22:30.56#ibcon#flushed, iclass 38, count 0 2006.201.11:22:30.56#ibcon#about to write, iclass 38, count 0 2006.201.11:22:30.56#ibcon#wrote, iclass 38, count 0 2006.201.11:22:30.56#ibcon#about to read 3, iclass 38, count 0 2006.201.11:22:30.60#ibcon#read 3, iclass 38, count 0 2006.201.11:22:30.60#ibcon#about to read 4, iclass 38, count 0 2006.201.11:22:30.60#ibcon#read 4, iclass 38, count 0 2006.201.11:22:30.60#ibcon#about to read 5, iclass 38, count 0 2006.201.11:22:30.60#ibcon#read 5, iclass 38, count 0 2006.201.11:22:30.60#ibcon#about to read 6, iclass 38, count 0 2006.201.11:22:30.60#ibcon#read 6, iclass 38, count 0 2006.201.11:22:30.60#ibcon#end of sib2, iclass 38, count 0 2006.201.11:22:30.60#ibcon#*after write, iclass 38, count 0 2006.201.11:22:30.60#ibcon#*before return 0, iclass 38, count 0 2006.201.11:22:30.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:30.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:22:30.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:22:30.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:22:30.60$vck44/vb=4,5 2006.201.11:22:30.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.11:22:30.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.11:22:30.60#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:30.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:30.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:30.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:30.66#ibcon#enter wrdev, iclass 40, count 2 2006.201.11:22:30.66#ibcon#first serial, iclass 40, count 2 2006.201.11:22:30.66#ibcon#enter sib2, iclass 40, count 2 2006.201.11:22:30.66#ibcon#flushed, iclass 40, count 2 2006.201.11:22:30.66#ibcon#about to write, iclass 40, count 2 2006.201.11:22:30.66#ibcon#wrote, iclass 40, count 2 2006.201.11:22:30.66#ibcon#about to read 3, iclass 40, count 2 2006.201.11:22:30.68#ibcon#read 3, iclass 40, count 2 2006.201.11:22:30.68#ibcon#about to read 4, iclass 40, count 2 2006.201.11:22:30.68#ibcon#read 4, iclass 40, count 2 2006.201.11:22:30.68#ibcon#about to read 5, iclass 40, count 2 2006.201.11:22:30.68#ibcon#read 5, iclass 40, count 2 2006.201.11:22:30.68#ibcon#about to read 6, iclass 40, count 2 2006.201.11:22:30.68#ibcon#read 6, iclass 40, count 2 2006.201.11:22:30.68#ibcon#end of sib2, iclass 40, count 2 2006.201.11:22:30.68#ibcon#*mode == 0, iclass 40, count 2 2006.201.11:22:30.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.11:22:30.68#ibcon#[27=AT04-05\r\n] 2006.201.11:22:30.68#ibcon#*before write, iclass 40, count 2 2006.201.11:22:30.68#ibcon#enter sib2, iclass 40, count 2 2006.201.11:22:30.68#ibcon#flushed, iclass 40, count 2 2006.201.11:22:30.68#ibcon#about to write, iclass 40, count 2 2006.201.11:22:30.68#ibcon#wrote, iclass 40, count 2 2006.201.11:22:30.68#ibcon#about to read 3, iclass 40, count 2 2006.201.11:22:30.71#ibcon#read 3, iclass 40, count 2 2006.201.11:22:30.71#ibcon#about to read 4, iclass 40, count 2 2006.201.11:22:30.71#ibcon#read 4, iclass 40, count 2 2006.201.11:22:30.71#ibcon#about to read 5, iclass 40, count 2 2006.201.11:22:30.71#ibcon#read 5, iclass 40, count 2 2006.201.11:22:30.71#ibcon#about to read 6, iclass 40, count 2 2006.201.11:22:30.71#ibcon#read 6, iclass 40, count 2 2006.201.11:22:30.71#ibcon#end of sib2, iclass 40, count 2 2006.201.11:22:30.71#ibcon#*after write, iclass 40, count 2 2006.201.11:22:30.71#ibcon#*before return 0, iclass 40, count 2 2006.201.11:22:30.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:30.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:22:30.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.11:22:30.71#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:30.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:30.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:30.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:30.83#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:22:30.83#ibcon#first serial, iclass 40, count 0 2006.201.11:22:30.83#ibcon#enter sib2, iclass 40, count 0 2006.201.11:22:30.83#ibcon#flushed, iclass 40, count 0 2006.201.11:22:30.83#ibcon#about to write, iclass 40, count 0 2006.201.11:22:30.83#ibcon#wrote, iclass 40, count 0 2006.201.11:22:30.83#ibcon#about to read 3, iclass 40, count 0 2006.201.11:22:30.85#ibcon#read 3, iclass 40, count 0 2006.201.11:22:30.85#ibcon#about to read 4, iclass 40, count 0 2006.201.11:22:30.85#ibcon#read 4, iclass 40, count 0 2006.201.11:22:30.85#ibcon#about to read 5, iclass 40, count 0 2006.201.11:22:30.85#ibcon#read 5, iclass 40, count 0 2006.201.11:22:30.85#ibcon#about to read 6, iclass 40, count 0 2006.201.11:22:30.85#ibcon#read 6, iclass 40, count 0 2006.201.11:22:30.85#ibcon#end of sib2, iclass 40, count 0 2006.201.11:22:30.85#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:22:30.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:22:30.85#ibcon#[27=USB\r\n] 2006.201.11:22:30.85#ibcon#*before write, iclass 40, count 0 2006.201.11:22:30.85#ibcon#enter sib2, iclass 40, count 0 2006.201.11:22:30.85#ibcon#flushed, iclass 40, count 0 2006.201.11:22:30.85#ibcon#about to write, iclass 40, count 0 2006.201.11:22:30.85#ibcon#wrote, iclass 40, count 0 2006.201.11:22:30.85#ibcon#about to read 3, iclass 40, count 0 2006.201.11:22:30.88#ibcon#read 3, iclass 40, count 0 2006.201.11:22:30.88#ibcon#about to read 4, iclass 40, count 0 2006.201.11:22:30.88#ibcon#read 4, iclass 40, count 0 2006.201.11:22:30.88#ibcon#about to read 5, iclass 40, count 0 2006.201.11:22:30.88#ibcon#read 5, iclass 40, count 0 2006.201.11:22:30.88#ibcon#about to read 6, iclass 40, count 0 2006.201.11:22:30.88#ibcon#read 6, iclass 40, count 0 2006.201.11:22:30.88#ibcon#end of sib2, iclass 40, count 0 2006.201.11:22:30.88#ibcon#*after write, iclass 40, count 0 2006.201.11:22:30.88#ibcon#*before return 0, iclass 40, count 0 2006.201.11:22:30.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:30.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:22:30.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:22:30.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:22:30.88$vck44/vblo=5,709.99 2006.201.11:22:30.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.11:22:30.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.11:22:30.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:30.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:30.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:30.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:30.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:22:30.88#ibcon#first serial, iclass 4, count 0 2006.201.11:22:30.88#ibcon#enter sib2, iclass 4, count 0 2006.201.11:22:30.88#ibcon#flushed, iclass 4, count 0 2006.201.11:22:30.88#ibcon#about to write, iclass 4, count 0 2006.201.11:22:30.88#ibcon#wrote, iclass 4, count 0 2006.201.11:22:30.88#ibcon#about to read 3, iclass 4, count 0 2006.201.11:22:30.90#ibcon#read 3, iclass 4, count 0 2006.201.11:22:30.90#ibcon#about to read 4, iclass 4, count 0 2006.201.11:22:30.90#ibcon#read 4, iclass 4, count 0 2006.201.11:22:30.90#ibcon#about to read 5, iclass 4, count 0 2006.201.11:22:30.90#ibcon#read 5, iclass 4, count 0 2006.201.11:22:30.90#ibcon#about to read 6, iclass 4, count 0 2006.201.11:22:30.90#ibcon#read 6, iclass 4, count 0 2006.201.11:22:30.90#ibcon#end of sib2, iclass 4, count 0 2006.201.11:22:30.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:22:30.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:22:30.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:22:30.90#ibcon#*before write, iclass 4, count 0 2006.201.11:22:30.90#ibcon#enter sib2, iclass 4, count 0 2006.201.11:22:30.90#ibcon#flushed, iclass 4, count 0 2006.201.11:22:30.90#ibcon#about to write, iclass 4, count 0 2006.201.11:22:30.90#ibcon#wrote, iclass 4, count 0 2006.201.11:22:30.90#ibcon#about to read 3, iclass 4, count 0 2006.201.11:22:30.94#ibcon#read 3, iclass 4, count 0 2006.201.11:22:30.94#ibcon#about to read 4, iclass 4, count 0 2006.201.11:22:30.94#ibcon#read 4, iclass 4, count 0 2006.201.11:22:30.94#ibcon#about to read 5, iclass 4, count 0 2006.201.11:22:30.94#ibcon#read 5, iclass 4, count 0 2006.201.11:22:30.94#ibcon#about to read 6, iclass 4, count 0 2006.201.11:22:30.94#ibcon#read 6, iclass 4, count 0 2006.201.11:22:30.94#ibcon#end of sib2, iclass 4, count 0 2006.201.11:22:30.94#ibcon#*after write, iclass 4, count 0 2006.201.11:22:30.94#ibcon#*before return 0, iclass 4, count 0 2006.201.11:22:30.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:30.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:22:30.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:22:30.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:22:30.94$vck44/vb=5,4 2006.201.11:22:30.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.11:22:30.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.11:22:30.94#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:30.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:31.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:31.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:31.00#ibcon#enter wrdev, iclass 6, count 2 2006.201.11:22:31.00#ibcon#first serial, iclass 6, count 2 2006.201.11:22:31.00#ibcon#enter sib2, iclass 6, count 2 2006.201.11:22:31.00#ibcon#flushed, iclass 6, count 2 2006.201.11:22:31.00#ibcon#about to write, iclass 6, count 2 2006.201.11:22:31.00#ibcon#wrote, iclass 6, count 2 2006.201.11:22:31.00#ibcon#about to read 3, iclass 6, count 2 2006.201.11:22:31.02#ibcon#read 3, iclass 6, count 2 2006.201.11:22:31.02#ibcon#about to read 4, iclass 6, count 2 2006.201.11:22:31.02#ibcon#read 4, iclass 6, count 2 2006.201.11:22:31.02#ibcon#about to read 5, iclass 6, count 2 2006.201.11:22:31.02#ibcon#read 5, iclass 6, count 2 2006.201.11:22:31.02#ibcon#about to read 6, iclass 6, count 2 2006.201.11:22:31.02#ibcon#read 6, iclass 6, count 2 2006.201.11:22:31.02#ibcon#end of sib2, iclass 6, count 2 2006.201.11:22:31.02#ibcon#*mode == 0, iclass 6, count 2 2006.201.11:22:31.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.11:22:31.02#ibcon#[27=AT05-04\r\n] 2006.201.11:22:31.02#ibcon#*before write, iclass 6, count 2 2006.201.11:22:31.02#ibcon#enter sib2, iclass 6, count 2 2006.201.11:22:31.02#ibcon#flushed, iclass 6, count 2 2006.201.11:22:31.02#ibcon#about to write, iclass 6, count 2 2006.201.11:22:31.02#ibcon#wrote, iclass 6, count 2 2006.201.11:22:31.02#ibcon#about to read 3, iclass 6, count 2 2006.201.11:22:31.05#ibcon#read 3, iclass 6, count 2 2006.201.11:22:31.05#ibcon#about to read 4, iclass 6, count 2 2006.201.11:22:31.05#ibcon#read 4, iclass 6, count 2 2006.201.11:22:31.05#ibcon#about to read 5, iclass 6, count 2 2006.201.11:22:31.05#ibcon#read 5, iclass 6, count 2 2006.201.11:22:31.05#ibcon#about to read 6, iclass 6, count 2 2006.201.11:22:31.05#ibcon#read 6, iclass 6, count 2 2006.201.11:22:31.05#ibcon#end of sib2, iclass 6, count 2 2006.201.11:22:31.05#ibcon#*after write, iclass 6, count 2 2006.201.11:22:31.05#ibcon#*before return 0, iclass 6, count 2 2006.201.11:22:31.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:31.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:22:31.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.11:22:31.05#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:31.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:31.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:31.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:31.17#ibcon#enter wrdev, iclass 6, count 0 2006.201.11:22:31.17#ibcon#first serial, iclass 6, count 0 2006.201.11:22:31.17#ibcon#enter sib2, iclass 6, count 0 2006.201.11:22:31.17#ibcon#flushed, iclass 6, count 0 2006.201.11:22:31.17#ibcon#about to write, iclass 6, count 0 2006.201.11:22:31.17#ibcon#wrote, iclass 6, count 0 2006.201.11:22:31.17#ibcon#about to read 3, iclass 6, count 0 2006.201.11:22:31.20#ibcon#read 3, iclass 6, count 0 2006.201.11:22:31.20#ibcon#about to read 4, iclass 6, count 0 2006.201.11:22:31.20#ibcon#read 4, iclass 6, count 0 2006.201.11:22:31.20#ibcon#about to read 5, iclass 6, count 0 2006.201.11:22:31.20#ibcon#read 5, iclass 6, count 0 2006.201.11:22:31.20#ibcon#about to read 6, iclass 6, count 0 2006.201.11:22:31.20#ibcon#read 6, iclass 6, count 0 2006.201.11:22:31.20#ibcon#end of sib2, iclass 6, count 0 2006.201.11:22:31.20#ibcon#*mode == 0, iclass 6, count 0 2006.201.11:22:31.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.11:22:31.20#ibcon#[27=USB\r\n] 2006.201.11:22:31.20#ibcon#*before write, iclass 6, count 0 2006.201.11:22:31.20#ibcon#enter sib2, iclass 6, count 0 2006.201.11:22:31.20#ibcon#flushed, iclass 6, count 0 2006.201.11:22:31.20#ibcon#about to write, iclass 6, count 0 2006.201.11:22:31.20#ibcon#wrote, iclass 6, count 0 2006.201.11:22:31.20#ibcon#about to read 3, iclass 6, count 0 2006.201.11:22:31.23#ibcon#read 3, iclass 6, count 0 2006.201.11:22:31.23#ibcon#about to read 4, iclass 6, count 0 2006.201.11:22:31.23#ibcon#read 4, iclass 6, count 0 2006.201.11:22:31.23#ibcon#about to read 5, iclass 6, count 0 2006.201.11:22:31.23#ibcon#read 5, iclass 6, count 0 2006.201.11:22:31.23#ibcon#about to read 6, iclass 6, count 0 2006.201.11:22:31.23#ibcon#read 6, iclass 6, count 0 2006.201.11:22:31.23#ibcon#end of sib2, iclass 6, count 0 2006.201.11:22:31.23#ibcon#*after write, iclass 6, count 0 2006.201.11:22:31.23#ibcon#*before return 0, iclass 6, count 0 2006.201.11:22:31.23#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:31.23#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:22:31.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.11:22:31.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.11:22:31.23$vck44/vblo=6,719.99 2006.201.11:22:31.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.11:22:31.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.11:22:31.23#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:31.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:31.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:31.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:31.23#ibcon#enter wrdev, iclass 10, count 0 2006.201.11:22:31.23#ibcon#first serial, iclass 10, count 0 2006.201.11:22:31.23#ibcon#enter sib2, iclass 10, count 0 2006.201.11:22:31.23#ibcon#flushed, iclass 10, count 0 2006.201.11:22:31.23#ibcon#about to write, iclass 10, count 0 2006.201.11:22:31.23#ibcon#wrote, iclass 10, count 0 2006.201.11:22:31.23#ibcon#about to read 3, iclass 10, count 0 2006.201.11:22:31.25#ibcon#read 3, iclass 10, count 0 2006.201.11:22:31.25#ibcon#about to read 4, iclass 10, count 0 2006.201.11:22:31.25#ibcon#read 4, iclass 10, count 0 2006.201.11:22:31.25#ibcon#about to read 5, iclass 10, count 0 2006.201.11:22:31.25#ibcon#read 5, iclass 10, count 0 2006.201.11:22:31.25#ibcon#about to read 6, iclass 10, count 0 2006.201.11:22:31.25#ibcon#read 6, iclass 10, count 0 2006.201.11:22:31.25#ibcon#end of sib2, iclass 10, count 0 2006.201.11:22:31.25#ibcon#*mode == 0, iclass 10, count 0 2006.201.11:22:31.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.11:22:31.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:22:31.25#ibcon#*before write, iclass 10, count 0 2006.201.11:22:31.25#ibcon#enter sib2, iclass 10, count 0 2006.201.11:22:31.25#ibcon#flushed, iclass 10, count 0 2006.201.11:22:31.25#ibcon#about to write, iclass 10, count 0 2006.201.11:22:31.25#ibcon#wrote, iclass 10, count 0 2006.201.11:22:31.25#ibcon#about to read 3, iclass 10, count 0 2006.201.11:22:31.29#ibcon#read 3, iclass 10, count 0 2006.201.11:22:31.29#ibcon#about to read 4, iclass 10, count 0 2006.201.11:22:31.29#ibcon#read 4, iclass 10, count 0 2006.201.11:22:31.29#ibcon#about to read 5, iclass 10, count 0 2006.201.11:22:31.29#ibcon#read 5, iclass 10, count 0 2006.201.11:22:31.29#ibcon#about to read 6, iclass 10, count 0 2006.201.11:22:31.29#ibcon#read 6, iclass 10, count 0 2006.201.11:22:31.29#ibcon#end of sib2, iclass 10, count 0 2006.201.11:22:31.29#ibcon#*after write, iclass 10, count 0 2006.201.11:22:31.29#ibcon#*before return 0, iclass 10, count 0 2006.201.11:22:31.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:31.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:22:31.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.11:22:31.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.11:22:31.29$vck44/vb=6,4 2006.201.11:22:31.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.11:22:31.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.11:22:31.29#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:31.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:31.35#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:31.35#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:31.35#ibcon#enter wrdev, iclass 12, count 2 2006.201.11:22:31.35#ibcon#first serial, iclass 12, count 2 2006.201.11:22:31.35#ibcon#enter sib2, iclass 12, count 2 2006.201.11:22:31.35#ibcon#flushed, iclass 12, count 2 2006.201.11:22:31.35#ibcon#about to write, iclass 12, count 2 2006.201.11:22:31.35#ibcon#wrote, iclass 12, count 2 2006.201.11:22:31.35#ibcon#about to read 3, iclass 12, count 2 2006.201.11:22:31.37#ibcon#read 3, iclass 12, count 2 2006.201.11:22:31.37#ibcon#about to read 4, iclass 12, count 2 2006.201.11:22:31.37#ibcon#read 4, iclass 12, count 2 2006.201.11:22:31.37#ibcon#about to read 5, iclass 12, count 2 2006.201.11:22:31.37#ibcon#read 5, iclass 12, count 2 2006.201.11:22:31.37#ibcon#about to read 6, iclass 12, count 2 2006.201.11:22:31.37#ibcon#read 6, iclass 12, count 2 2006.201.11:22:31.37#ibcon#end of sib2, iclass 12, count 2 2006.201.11:22:31.37#ibcon#*mode == 0, iclass 12, count 2 2006.201.11:22:31.37#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.11:22:31.37#ibcon#[27=AT06-04\r\n] 2006.201.11:22:31.37#ibcon#*before write, iclass 12, count 2 2006.201.11:22:31.37#ibcon#enter sib2, iclass 12, count 2 2006.201.11:22:31.37#ibcon#flushed, iclass 12, count 2 2006.201.11:22:31.37#ibcon#about to write, iclass 12, count 2 2006.201.11:22:31.37#ibcon#wrote, iclass 12, count 2 2006.201.11:22:31.37#ibcon#about to read 3, iclass 12, count 2 2006.201.11:22:31.40#ibcon#read 3, iclass 12, count 2 2006.201.11:22:31.40#ibcon#about to read 4, iclass 12, count 2 2006.201.11:22:31.40#ibcon#read 4, iclass 12, count 2 2006.201.11:22:31.40#ibcon#about to read 5, iclass 12, count 2 2006.201.11:22:31.40#ibcon#read 5, iclass 12, count 2 2006.201.11:22:31.40#ibcon#about to read 6, iclass 12, count 2 2006.201.11:22:31.40#ibcon#read 6, iclass 12, count 2 2006.201.11:22:31.40#ibcon#end of sib2, iclass 12, count 2 2006.201.11:22:31.40#ibcon#*after write, iclass 12, count 2 2006.201.11:22:31.40#ibcon#*before return 0, iclass 12, count 2 2006.201.11:22:31.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:31.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:22:31.40#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.11:22:31.40#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:31.40#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:31.52#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:31.52#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:31.52#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:22:31.52#ibcon#first serial, iclass 12, count 0 2006.201.11:22:31.52#ibcon#enter sib2, iclass 12, count 0 2006.201.11:22:31.52#ibcon#flushed, iclass 12, count 0 2006.201.11:22:31.52#ibcon#about to write, iclass 12, count 0 2006.201.11:22:31.52#ibcon#wrote, iclass 12, count 0 2006.201.11:22:31.52#ibcon#about to read 3, iclass 12, count 0 2006.201.11:22:31.54#ibcon#read 3, iclass 12, count 0 2006.201.11:22:31.54#ibcon#about to read 4, iclass 12, count 0 2006.201.11:22:31.54#ibcon#read 4, iclass 12, count 0 2006.201.11:22:31.54#ibcon#about to read 5, iclass 12, count 0 2006.201.11:22:31.54#ibcon#read 5, iclass 12, count 0 2006.201.11:22:31.54#ibcon#about to read 6, iclass 12, count 0 2006.201.11:22:31.54#ibcon#read 6, iclass 12, count 0 2006.201.11:22:31.54#ibcon#end of sib2, iclass 12, count 0 2006.201.11:22:31.54#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:22:31.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:22:31.54#ibcon#[27=USB\r\n] 2006.201.11:22:31.54#ibcon#*before write, iclass 12, count 0 2006.201.11:22:31.54#ibcon#enter sib2, iclass 12, count 0 2006.201.11:22:31.54#ibcon#flushed, iclass 12, count 0 2006.201.11:22:31.54#ibcon#about to write, iclass 12, count 0 2006.201.11:22:31.54#ibcon#wrote, iclass 12, count 0 2006.201.11:22:31.54#ibcon#about to read 3, iclass 12, count 0 2006.201.11:22:31.57#ibcon#read 3, iclass 12, count 0 2006.201.11:22:31.57#ibcon#about to read 4, iclass 12, count 0 2006.201.11:22:31.57#ibcon#read 4, iclass 12, count 0 2006.201.11:22:31.57#ibcon#about to read 5, iclass 12, count 0 2006.201.11:22:31.57#ibcon#read 5, iclass 12, count 0 2006.201.11:22:31.57#ibcon#about to read 6, iclass 12, count 0 2006.201.11:22:31.57#ibcon#read 6, iclass 12, count 0 2006.201.11:22:31.57#ibcon#end of sib2, iclass 12, count 0 2006.201.11:22:31.57#ibcon#*after write, iclass 12, count 0 2006.201.11:22:31.57#ibcon#*before return 0, iclass 12, count 0 2006.201.11:22:31.57#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:31.57#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:22:31.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:22:31.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:22:31.57$vck44/vblo=7,734.99 2006.201.11:22:31.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.11:22:31.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.11:22:31.57#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:31.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:31.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:31.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:31.57#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:22:31.57#ibcon#first serial, iclass 14, count 0 2006.201.11:22:31.57#ibcon#enter sib2, iclass 14, count 0 2006.201.11:22:31.57#ibcon#flushed, iclass 14, count 0 2006.201.11:22:31.57#ibcon#about to write, iclass 14, count 0 2006.201.11:22:31.57#ibcon#wrote, iclass 14, count 0 2006.201.11:22:31.57#ibcon#about to read 3, iclass 14, count 0 2006.201.11:22:31.59#ibcon#read 3, iclass 14, count 0 2006.201.11:22:31.59#ibcon#about to read 4, iclass 14, count 0 2006.201.11:22:31.59#ibcon#read 4, iclass 14, count 0 2006.201.11:22:31.59#ibcon#about to read 5, iclass 14, count 0 2006.201.11:22:31.59#ibcon#read 5, iclass 14, count 0 2006.201.11:22:31.59#ibcon#about to read 6, iclass 14, count 0 2006.201.11:22:31.59#ibcon#read 6, iclass 14, count 0 2006.201.11:22:31.59#ibcon#end of sib2, iclass 14, count 0 2006.201.11:22:31.59#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:22:31.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:22:31.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:22:31.59#ibcon#*before write, iclass 14, count 0 2006.201.11:22:31.59#ibcon#enter sib2, iclass 14, count 0 2006.201.11:22:31.59#ibcon#flushed, iclass 14, count 0 2006.201.11:22:31.59#ibcon#about to write, iclass 14, count 0 2006.201.11:22:31.59#ibcon#wrote, iclass 14, count 0 2006.201.11:22:31.59#ibcon#about to read 3, iclass 14, count 0 2006.201.11:22:31.63#ibcon#read 3, iclass 14, count 0 2006.201.11:22:31.63#ibcon#about to read 4, iclass 14, count 0 2006.201.11:22:31.63#ibcon#read 4, iclass 14, count 0 2006.201.11:22:31.63#ibcon#about to read 5, iclass 14, count 0 2006.201.11:22:31.63#ibcon#read 5, iclass 14, count 0 2006.201.11:22:31.63#ibcon#about to read 6, iclass 14, count 0 2006.201.11:22:31.63#ibcon#read 6, iclass 14, count 0 2006.201.11:22:31.63#ibcon#end of sib2, iclass 14, count 0 2006.201.11:22:31.63#ibcon#*after write, iclass 14, count 0 2006.201.11:22:31.63#ibcon#*before return 0, iclass 14, count 0 2006.201.11:22:31.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:31.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:22:31.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:22:31.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:22:31.63$vck44/vb=7,4 2006.201.11:22:31.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.11:22:31.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.11:22:31.63#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:31.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:31.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:31.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:31.69#ibcon#enter wrdev, iclass 16, count 2 2006.201.11:22:31.69#ibcon#first serial, iclass 16, count 2 2006.201.11:22:31.69#ibcon#enter sib2, iclass 16, count 2 2006.201.11:22:31.69#ibcon#flushed, iclass 16, count 2 2006.201.11:22:31.69#ibcon#about to write, iclass 16, count 2 2006.201.11:22:31.69#ibcon#wrote, iclass 16, count 2 2006.201.11:22:31.69#ibcon#about to read 3, iclass 16, count 2 2006.201.11:22:31.71#ibcon#read 3, iclass 16, count 2 2006.201.11:22:31.71#ibcon#about to read 4, iclass 16, count 2 2006.201.11:22:31.71#ibcon#read 4, iclass 16, count 2 2006.201.11:22:31.71#ibcon#about to read 5, iclass 16, count 2 2006.201.11:22:31.71#ibcon#read 5, iclass 16, count 2 2006.201.11:22:31.71#ibcon#about to read 6, iclass 16, count 2 2006.201.11:22:31.71#ibcon#read 6, iclass 16, count 2 2006.201.11:22:31.71#ibcon#end of sib2, iclass 16, count 2 2006.201.11:22:31.71#ibcon#*mode == 0, iclass 16, count 2 2006.201.11:22:31.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.11:22:31.71#ibcon#[27=AT07-04\r\n] 2006.201.11:22:31.71#ibcon#*before write, iclass 16, count 2 2006.201.11:22:31.71#ibcon#enter sib2, iclass 16, count 2 2006.201.11:22:31.71#ibcon#flushed, iclass 16, count 2 2006.201.11:22:31.71#ibcon#about to write, iclass 16, count 2 2006.201.11:22:31.71#ibcon#wrote, iclass 16, count 2 2006.201.11:22:31.71#ibcon#about to read 3, iclass 16, count 2 2006.201.11:22:31.74#ibcon#read 3, iclass 16, count 2 2006.201.11:22:31.74#ibcon#about to read 4, iclass 16, count 2 2006.201.11:22:31.74#ibcon#read 4, iclass 16, count 2 2006.201.11:22:31.74#ibcon#about to read 5, iclass 16, count 2 2006.201.11:22:31.74#ibcon#read 5, iclass 16, count 2 2006.201.11:22:31.74#ibcon#about to read 6, iclass 16, count 2 2006.201.11:22:31.74#ibcon#read 6, iclass 16, count 2 2006.201.11:22:31.74#ibcon#end of sib2, iclass 16, count 2 2006.201.11:22:31.74#ibcon#*after write, iclass 16, count 2 2006.201.11:22:31.74#ibcon#*before return 0, iclass 16, count 2 2006.201.11:22:31.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:31.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:22:31.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.11:22:31.74#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:31.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:31.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:31.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:31.86#ibcon#enter wrdev, iclass 16, count 0 2006.201.11:22:31.86#ibcon#first serial, iclass 16, count 0 2006.201.11:22:31.86#ibcon#enter sib2, iclass 16, count 0 2006.201.11:22:31.86#ibcon#flushed, iclass 16, count 0 2006.201.11:22:31.86#ibcon#about to write, iclass 16, count 0 2006.201.11:22:31.86#ibcon#wrote, iclass 16, count 0 2006.201.11:22:31.86#ibcon#about to read 3, iclass 16, count 0 2006.201.11:22:31.88#ibcon#read 3, iclass 16, count 0 2006.201.11:22:31.88#ibcon#about to read 4, iclass 16, count 0 2006.201.11:22:31.88#ibcon#read 4, iclass 16, count 0 2006.201.11:22:31.88#ibcon#about to read 5, iclass 16, count 0 2006.201.11:22:31.88#ibcon#read 5, iclass 16, count 0 2006.201.11:22:31.88#ibcon#about to read 6, iclass 16, count 0 2006.201.11:22:31.88#ibcon#read 6, iclass 16, count 0 2006.201.11:22:31.88#ibcon#end of sib2, iclass 16, count 0 2006.201.11:22:31.88#ibcon#*mode == 0, iclass 16, count 0 2006.201.11:22:31.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.11:22:31.88#ibcon#[27=USB\r\n] 2006.201.11:22:31.88#ibcon#*before write, iclass 16, count 0 2006.201.11:22:31.88#ibcon#enter sib2, iclass 16, count 0 2006.201.11:22:31.88#ibcon#flushed, iclass 16, count 0 2006.201.11:22:31.88#ibcon#about to write, iclass 16, count 0 2006.201.11:22:31.88#ibcon#wrote, iclass 16, count 0 2006.201.11:22:31.88#ibcon#about to read 3, iclass 16, count 0 2006.201.11:22:31.91#ibcon#read 3, iclass 16, count 0 2006.201.11:22:31.91#ibcon#about to read 4, iclass 16, count 0 2006.201.11:22:31.91#ibcon#read 4, iclass 16, count 0 2006.201.11:22:31.91#ibcon#about to read 5, iclass 16, count 0 2006.201.11:22:31.91#ibcon#read 5, iclass 16, count 0 2006.201.11:22:31.91#ibcon#about to read 6, iclass 16, count 0 2006.201.11:22:31.91#ibcon#read 6, iclass 16, count 0 2006.201.11:22:31.91#ibcon#end of sib2, iclass 16, count 0 2006.201.11:22:31.91#ibcon#*after write, iclass 16, count 0 2006.201.11:22:31.91#ibcon#*before return 0, iclass 16, count 0 2006.201.11:22:31.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:31.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:22:31.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.11:22:31.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.11:22:31.91$vck44/vblo=8,744.99 2006.201.11:22:31.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.11:22:31.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.11:22:31.91#ibcon#ireg 17 cls_cnt 0 2006.201.11:22:31.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:31.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:31.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:31.91#ibcon#enter wrdev, iclass 18, count 0 2006.201.11:22:31.91#ibcon#first serial, iclass 18, count 0 2006.201.11:22:31.91#ibcon#enter sib2, iclass 18, count 0 2006.201.11:22:31.91#ibcon#flushed, iclass 18, count 0 2006.201.11:22:31.91#ibcon#about to write, iclass 18, count 0 2006.201.11:22:31.91#ibcon#wrote, iclass 18, count 0 2006.201.11:22:31.91#ibcon#about to read 3, iclass 18, count 0 2006.201.11:22:31.93#ibcon#read 3, iclass 18, count 0 2006.201.11:22:31.93#ibcon#about to read 4, iclass 18, count 0 2006.201.11:22:31.93#ibcon#read 4, iclass 18, count 0 2006.201.11:22:31.93#ibcon#about to read 5, iclass 18, count 0 2006.201.11:22:31.93#ibcon#read 5, iclass 18, count 0 2006.201.11:22:31.93#ibcon#about to read 6, iclass 18, count 0 2006.201.11:22:31.93#ibcon#read 6, iclass 18, count 0 2006.201.11:22:31.93#ibcon#end of sib2, iclass 18, count 0 2006.201.11:22:31.93#ibcon#*mode == 0, iclass 18, count 0 2006.201.11:22:31.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.11:22:31.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:22:31.93#ibcon#*before write, iclass 18, count 0 2006.201.11:22:31.93#ibcon#enter sib2, iclass 18, count 0 2006.201.11:22:31.93#ibcon#flushed, iclass 18, count 0 2006.201.11:22:31.93#ibcon#about to write, iclass 18, count 0 2006.201.11:22:31.93#ibcon#wrote, iclass 18, count 0 2006.201.11:22:31.93#ibcon#about to read 3, iclass 18, count 0 2006.201.11:22:31.98#ibcon#read 3, iclass 18, count 0 2006.201.11:22:31.98#ibcon#about to read 4, iclass 18, count 0 2006.201.11:22:31.98#ibcon#read 4, iclass 18, count 0 2006.201.11:22:31.98#ibcon#about to read 5, iclass 18, count 0 2006.201.11:22:31.98#ibcon#read 5, iclass 18, count 0 2006.201.11:22:31.98#ibcon#about to read 6, iclass 18, count 0 2006.201.11:22:31.98#ibcon#read 6, iclass 18, count 0 2006.201.11:22:31.98#ibcon#end of sib2, iclass 18, count 0 2006.201.11:22:31.98#ibcon#*after write, iclass 18, count 0 2006.201.11:22:31.98#ibcon#*before return 0, iclass 18, count 0 2006.201.11:22:31.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:31.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:22:31.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.11:22:31.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.11:22:31.98$vck44/vb=8,4 2006.201.11:22:31.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.11:22:31.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.11:22:31.98#ibcon#ireg 11 cls_cnt 2 2006.201.11:22:31.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:32.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:32.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:32.03#ibcon#enter wrdev, iclass 20, count 2 2006.201.11:22:32.03#ibcon#first serial, iclass 20, count 2 2006.201.11:22:32.03#ibcon#enter sib2, iclass 20, count 2 2006.201.11:22:32.03#ibcon#flushed, iclass 20, count 2 2006.201.11:22:32.03#ibcon#about to write, iclass 20, count 2 2006.201.11:22:32.03#ibcon#wrote, iclass 20, count 2 2006.201.11:22:32.03#ibcon#about to read 3, iclass 20, count 2 2006.201.11:22:32.05#ibcon#read 3, iclass 20, count 2 2006.201.11:22:32.05#ibcon#about to read 4, iclass 20, count 2 2006.201.11:22:32.05#ibcon#read 4, iclass 20, count 2 2006.201.11:22:32.05#ibcon#about to read 5, iclass 20, count 2 2006.201.11:22:32.05#ibcon#read 5, iclass 20, count 2 2006.201.11:22:32.05#ibcon#about to read 6, iclass 20, count 2 2006.201.11:22:32.05#ibcon#read 6, iclass 20, count 2 2006.201.11:22:32.05#ibcon#end of sib2, iclass 20, count 2 2006.201.11:22:32.05#ibcon#*mode == 0, iclass 20, count 2 2006.201.11:22:32.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.11:22:32.05#ibcon#[27=AT08-04\r\n] 2006.201.11:22:32.05#ibcon#*before write, iclass 20, count 2 2006.201.11:22:32.05#ibcon#enter sib2, iclass 20, count 2 2006.201.11:22:32.05#ibcon#flushed, iclass 20, count 2 2006.201.11:22:32.05#ibcon#about to write, iclass 20, count 2 2006.201.11:22:32.05#ibcon#wrote, iclass 20, count 2 2006.201.11:22:32.05#ibcon#about to read 3, iclass 20, count 2 2006.201.11:22:32.08#ibcon#read 3, iclass 20, count 2 2006.201.11:22:32.08#ibcon#about to read 4, iclass 20, count 2 2006.201.11:22:32.08#ibcon#read 4, iclass 20, count 2 2006.201.11:22:32.08#ibcon#about to read 5, iclass 20, count 2 2006.201.11:22:32.08#ibcon#read 5, iclass 20, count 2 2006.201.11:22:32.08#ibcon#about to read 6, iclass 20, count 2 2006.201.11:22:32.08#ibcon#read 6, iclass 20, count 2 2006.201.11:22:32.08#ibcon#end of sib2, iclass 20, count 2 2006.201.11:22:32.08#ibcon#*after write, iclass 20, count 2 2006.201.11:22:32.08#ibcon#*before return 0, iclass 20, count 2 2006.201.11:22:32.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:32.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:22:32.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.11:22:32.08#ibcon#ireg 7 cls_cnt 0 2006.201.11:22:32.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:32.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:32.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:32.20#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:22:32.20#ibcon#first serial, iclass 20, count 0 2006.201.11:22:32.20#ibcon#enter sib2, iclass 20, count 0 2006.201.11:22:32.20#ibcon#flushed, iclass 20, count 0 2006.201.11:22:32.20#ibcon#about to write, iclass 20, count 0 2006.201.11:22:32.20#ibcon#wrote, iclass 20, count 0 2006.201.11:22:32.20#ibcon#about to read 3, iclass 20, count 0 2006.201.11:22:32.22#ibcon#read 3, iclass 20, count 0 2006.201.11:22:32.22#ibcon#about to read 4, iclass 20, count 0 2006.201.11:22:32.22#ibcon#read 4, iclass 20, count 0 2006.201.11:22:32.22#ibcon#about to read 5, iclass 20, count 0 2006.201.11:22:32.22#ibcon#read 5, iclass 20, count 0 2006.201.11:22:32.22#ibcon#about to read 6, iclass 20, count 0 2006.201.11:22:32.22#ibcon#read 6, iclass 20, count 0 2006.201.11:22:32.22#ibcon#end of sib2, iclass 20, count 0 2006.201.11:22:32.22#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:22:32.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:22:32.22#ibcon#[27=USB\r\n] 2006.201.11:22:32.22#ibcon#*before write, iclass 20, count 0 2006.201.11:22:32.22#ibcon#enter sib2, iclass 20, count 0 2006.201.11:22:32.22#ibcon#flushed, iclass 20, count 0 2006.201.11:22:32.22#ibcon#about to write, iclass 20, count 0 2006.201.11:22:32.22#ibcon#wrote, iclass 20, count 0 2006.201.11:22:32.22#ibcon#about to read 3, iclass 20, count 0 2006.201.11:22:32.25#ibcon#read 3, iclass 20, count 0 2006.201.11:22:32.25#ibcon#about to read 4, iclass 20, count 0 2006.201.11:22:32.25#ibcon#read 4, iclass 20, count 0 2006.201.11:22:32.25#ibcon#about to read 5, iclass 20, count 0 2006.201.11:22:32.25#ibcon#read 5, iclass 20, count 0 2006.201.11:22:32.25#ibcon#about to read 6, iclass 20, count 0 2006.201.11:22:32.25#ibcon#read 6, iclass 20, count 0 2006.201.11:22:32.25#ibcon#end of sib2, iclass 20, count 0 2006.201.11:22:32.25#ibcon#*after write, iclass 20, count 0 2006.201.11:22:32.25#ibcon#*before return 0, iclass 20, count 0 2006.201.11:22:32.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:32.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:22:32.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:22:32.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:22:32.25$vck44/vabw=wide 2006.201.11:22:32.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.11:22:32.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.11:22:32.25#ibcon#ireg 8 cls_cnt 0 2006.201.11:22:32.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:32.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:32.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:32.25#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:22:32.25#ibcon#first serial, iclass 22, count 0 2006.201.11:22:32.25#ibcon#enter sib2, iclass 22, count 0 2006.201.11:22:32.25#ibcon#flushed, iclass 22, count 0 2006.201.11:22:32.25#ibcon#about to write, iclass 22, count 0 2006.201.11:22:32.25#ibcon#wrote, iclass 22, count 0 2006.201.11:22:32.25#ibcon#about to read 3, iclass 22, count 0 2006.201.11:22:32.27#ibcon#read 3, iclass 22, count 0 2006.201.11:22:32.27#ibcon#about to read 4, iclass 22, count 0 2006.201.11:22:32.27#ibcon#read 4, iclass 22, count 0 2006.201.11:22:32.27#ibcon#about to read 5, iclass 22, count 0 2006.201.11:22:32.27#ibcon#read 5, iclass 22, count 0 2006.201.11:22:32.27#ibcon#about to read 6, iclass 22, count 0 2006.201.11:22:32.27#ibcon#read 6, iclass 22, count 0 2006.201.11:22:32.27#ibcon#end of sib2, iclass 22, count 0 2006.201.11:22:32.27#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:22:32.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:22:32.27#ibcon#[25=BW32\r\n] 2006.201.11:22:32.27#ibcon#*before write, iclass 22, count 0 2006.201.11:22:32.27#ibcon#enter sib2, iclass 22, count 0 2006.201.11:22:32.27#ibcon#flushed, iclass 22, count 0 2006.201.11:22:32.27#ibcon#about to write, iclass 22, count 0 2006.201.11:22:32.27#ibcon#wrote, iclass 22, count 0 2006.201.11:22:32.27#ibcon#about to read 3, iclass 22, count 0 2006.201.11:22:32.30#ibcon#read 3, iclass 22, count 0 2006.201.11:22:32.30#ibcon#about to read 4, iclass 22, count 0 2006.201.11:22:32.30#ibcon#read 4, iclass 22, count 0 2006.201.11:22:32.30#ibcon#about to read 5, iclass 22, count 0 2006.201.11:22:32.30#ibcon#read 5, iclass 22, count 0 2006.201.11:22:32.30#ibcon#about to read 6, iclass 22, count 0 2006.201.11:22:32.30#ibcon#read 6, iclass 22, count 0 2006.201.11:22:32.30#ibcon#end of sib2, iclass 22, count 0 2006.201.11:22:32.30#ibcon#*after write, iclass 22, count 0 2006.201.11:22:32.30#ibcon#*before return 0, iclass 22, count 0 2006.201.11:22:32.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:32.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:22:32.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:22:32.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:22:32.30$vck44/vbbw=wide 2006.201.11:22:32.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.11:22:32.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.11:22:32.30#ibcon#ireg 8 cls_cnt 0 2006.201.11:22:32.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:22:32.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:22:32.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:22:32.37#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:22:32.37#ibcon#first serial, iclass 24, count 0 2006.201.11:22:32.37#ibcon#enter sib2, iclass 24, count 0 2006.201.11:22:32.37#ibcon#flushed, iclass 24, count 0 2006.201.11:22:32.37#ibcon#about to write, iclass 24, count 0 2006.201.11:22:32.37#ibcon#wrote, iclass 24, count 0 2006.201.11:22:32.37#ibcon#about to read 3, iclass 24, count 0 2006.201.11:22:32.39#ibcon#read 3, iclass 24, count 0 2006.201.11:22:32.39#ibcon#about to read 4, iclass 24, count 0 2006.201.11:22:32.39#ibcon#read 4, iclass 24, count 0 2006.201.11:22:32.39#ibcon#about to read 5, iclass 24, count 0 2006.201.11:22:32.39#ibcon#read 5, iclass 24, count 0 2006.201.11:22:32.39#ibcon#about to read 6, iclass 24, count 0 2006.201.11:22:32.39#ibcon#read 6, iclass 24, count 0 2006.201.11:22:32.39#ibcon#end of sib2, iclass 24, count 0 2006.201.11:22:32.39#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:22:32.39#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:22:32.39#ibcon#[27=BW32\r\n] 2006.201.11:22:32.39#ibcon#*before write, iclass 24, count 0 2006.201.11:22:32.39#ibcon#enter sib2, iclass 24, count 0 2006.201.11:22:32.39#ibcon#flushed, iclass 24, count 0 2006.201.11:22:32.39#ibcon#about to write, iclass 24, count 0 2006.201.11:22:32.39#ibcon#wrote, iclass 24, count 0 2006.201.11:22:32.39#ibcon#about to read 3, iclass 24, count 0 2006.201.11:22:32.42#ibcon#read 3, iclass 24, count 0 2006.201.11:22:32.42#ibcon#about to read 4, iclass 24, count 0 2006.201.11:22:32.42#ibcon#read 4, iclass 24, count 0 2006.201.11:22:32.42#ibcon#about to read 5, iclass 24, count 0 2006.201.11:22:32.42#ibcon#read 5, iclass 24, count 0 2006.201.11:22:32.42#ibcon#about to read 6, iclass 24, count 0 2006.201.11:22:32.42#ibcon#read 6, iclass 24, count 0 2006.201.11:22:32.42#ibcon#end of sib2, iclass 24, count 0 2006.201.11:22:32.42#ibcon#*after write, iclass 24, count 0 2006.201.11:22:32.42#ibcon#*before return 0, iclass 24, count 0 2006.201.11:22:32.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:22:32.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:22:32.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:22:32.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:22:32.42$setupk4/ifdk4 2006.201.11:22:32.42$ifdk4/lo= 2006.201.11:22:32.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:22:32.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:22:32.42$ifdk4/patch= 2006.201.11:22:32.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:22:32.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:22:32.42$setupk4/!*+20s 2006.201.11:22:34.54#abcon#<5=/03 1.9 3.7 21.411001004.0\r\n> 2006.201.11:22:34.56#abcon#{5=INTERFACE CLEAR} 2006.201.11:22:34.62#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:22:44.71#abcon#<5=/03 1.9 3.6 21.411001004.0\r\n> 2006.201.11:22:44.73#abcon#{5=INTERFACE CLEAR} 2006.201.11:22:44.79#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:22:46.14#trakl#Source acquired 2006.201.11:22:46.14#flagr#flagr/antenna,acquired 2006.201.11:22:46.88$setupk4/"tpicd 2006.201.11:22:46.88$setupk4/echo=off 2006.201.11:22:46.88$setupk4/xlog=off 2006.201.11:22:46.88:!2006.201.11:25:54 2006.201.11:25:54.00:preob 2006.201.11:25:54.14/onsource/TRACKING 2006.201.11:25:54.14:!2006.201.11:26:04 2006.201.11:26:04.00:"tape 2006.201.11:26:04.00:"st=record 2006.201.11:26:04.00:data_valid=on 2006.201.11:26:04.00:midob 2006.201.11:26:04.14/onsource/TRACKING 2006.201.11:26:04.14/wx/21.41,1004.0,100 2006.201.11:26:04.32/cable/+6.4701E-03 2006.201.11:26:05.41/va/01,08,usb,yes,33,35 2006.201.11:26:05.41/va/02,07,usb,yes,35,36 2006.201.11:26:05.41/va/03,08,usb,yes,32,33 2006.201.11:26:05.41/va/04,07,usb,yes,36,38 2006.201.11:26:05.41/va/05,04,usb,yes,32,33 2006.201.11:26:05.41/va/06,05,usb,yes,32,32 2006.201.11:26:05.41/va/07,05,usb,yes,31,33 2006.201.11:26:05.41/va/08,04,usb,yes,31,37 2006.201.11:26:05.64/valo/01,524.99,yes,locked 2006.201.11:26:05.64/valo/02,534.99,yes,locked 2006.201.11:26:05.64/valo/03,564.99,yes,locked 2006.201.11:26:05.64/valo/04,624.99,yes,locked 2006.201.11:26:05.64/valo/05,734.99,yes,locked 2006.201.11:26:05.64/valo/06,814.99,yes,locked 2006.201.11:26:05.64/valo/07,864.99,yes,locked 2006.201.11:26:05.64/valo/08,884.99,yes,locked 2006.201.11:26:06.73/vb/01,04,usb,yes,31,29 2006.201.11:26:06.73/vb/02,05,usb,yes,30,29 2006.201.11:26:06.73/vb/03,04,usb,yes,31,34 2006.201.11:26:06.73/vb/04,05,usb,yes,31,30 2006.201.11:26:06.73/vb/05,04,usb,yes,27,30 2006.201.11:26:06.73/vb/06,04,usb,yes,32,28 2006.201.11:26:06.73/vb/07,04,usb,yes,32,32 2006.201.11:26:06.73/vb/08,04,usb,yes,29,33 2006.201.11:26:06.96/vblo/01,629.99,yes,locked 2006.201.11:26:06.96/vblo/02,634.99,yes,locked 2006.201.11:26:06.96/vblo/03,649.99,yes,locked 2006.201.11:26:06.96/vblo/04,679.99,yes,locked 2006.201.11:26:06.96/vblo/05,709.99,yes,locked 2006.201.11:26:06.96/vblo/06,719.99,yes,locked 2006.201.11:26:06.96/vblo/07,734.99,yes,locked 2006.201.11:26:06.96/vblo/08,744.99,yes,locked 2006.201.11:26:07.11/vabw/8 2006.201.11:26:07.26/vbbw/8 2006.201.11:26:07.35/xfe/off,on,14.7 2006.201.11:26:07.73/ifatt/23,28,28,28 2006.201.11:26:08.05/fmout-gps/S +4.59E-07 2006.201.11:26:08.12:!2006.201.11:26:44 2006.201.11:26:44.00:data_valid=off 2006.201.11:26:44.00:"et 2006.201.11:26:44.00:!+3s 2006.201.11:26:47.02:"tape 2006.201.11:26:47.02:postob 2006.201.11:26:47.25/cable/+6.4698E-03 2006.201.11:26:47.25/wx/21.41,1004.0,100 2006.201.11:26:47.33/fmout-gps/S +4.58E-07 2006.201.11:26:47.33:scan_name=201-1129,jd0607,110 2006.201.11:26:47.33:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.201.11:26:49.14#flagr#flagr/antenna,new-source 2006.201.11:26:49.14:checkk5 2006.201.11:26:49.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:26:49.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:26:50.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:26:50.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:26:51.02/chk_obsdata//k5ts1/T2011126??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:26:51.39/chk_obsdata//k5ts2/T2011126??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:26:51.75/chk_obsdata//k5ts3/T2011126??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:26:52.12/chk_obsdata//k5ts4/T2011126??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:26:52.81/k5log//k5ts1_log_newline 2006.201.11:26:53.50/k5log//k5ts2_log_newline 2006.201.11:26:54.18/k5log//k5ts3_log_newline 2006.201.11:26:54.87/k5log//k5ts4_log_newline 2006.201.11:26:54.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:26:54.89:setupk4=1 2006.201.11:26:54.89$setupk4/echo=on 2006.201.11:26:54.89$setupk4/pcalon 2006.201.11:26:54.89$pcalon/"no phase cal control is implemented here 2006.201.11:26:54.89$setupk4/"tpicd=stop 2006.201.11:26:54.89$setupk4/"rec=synch_on 2006.201.11:26:54.89$setupk4/"rec_mode=128 2006.201.11:26:54.89$setupk4/!* 2006.201.11:26:54.89$setupk4/recpk4 2006.201.11:26:54.89$recpk4/recpatch= 2006.201.11:26:54.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:26:54.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:26:54.90$setupk4/vck44 2006.201.11:26:54.90$vck44/valo=1,524.99 2006.201.11:26:54.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.11:26:54.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.11:26:54.90#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:54.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:54.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:54.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:54.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:26:54.90#ibcon#first serial, iclass 20, count 0 2006.201.11:26:54.90#ibcon#enter sib2, iclass 20, count 0 2006.201.11:26:54.90#ibcon#flushed, iclass 20, count 0 2006.201.11:26:54.90#ibcon#about to write, iclass 20, count 0 2006.201.11:26:54.90#ibcon#wrote, iclass 20, count 0 2006.201.11:26:54.90#ibcon#about to read 3, iclass 20, count 0 2006.201.11:26:54.94#ibcon#read 3, iclass 20, count 0 2006.201.11:26:54.94#ibcon#about to read 4, iclass 20, count 0 2006.201.11:26:54.94#ibcon#read 4, iclass 20, count 0 2006.201.11:26:54.94#ibcon#about to read 5, iclass 20, count 0 2006.201.11:26:54.94#ibcon#read 5, iclass 20, count 0 2006.201.11:26:54.94#ibcon#about to read 6, iclass 20, count 0 2006.201.11:26:54.94#ibcon#read 6, iclass 20, count 0 2006.201.11:26:54.94#ibcon#end of sib2, iclass 20, count 0 2006.201.11:26:54.94#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:26:54.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:26:54.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:26:54.94#ibcon#*before write, iclass 20, count 0 2006.201.11:26:54.94#ibcon#enter sib2, iclass 20, count 0 2006.201.11:26:54.94#ibcon#flushed, iclass 20, count 0 2006.201.11:26:54.94#ibcon#about to write, iclass 20, count 0 2006.201.11:26:54.94#ibcon#wrote, iclass 20, count 0 2006.201.11:26:54.94#ibcon#about to read 3, iclass 20, count 0 2006.201.11:26:54.99#ibcon#read 3, iclass 20, count 0 2006.201.11:26:54.99#ibcon#about to read 4, iclass 20, count 0 2006.201.11:26:54.99#ibcon#read 4, iclass 20, count 0 2006.201.11:26:54.99#ibcon#about to read 5, iclass 20, count 0 2006.201.11:26:54.99#ibcon#read 5, iclass 20, count 0 2006.201.11:26:54.99#ibcon#about to read 6, iclass 20, count 0 2006.201.11:26:54.99#ibcon#read 6, iclass 20, count 0 2006.201.11:26:54.99#ibcon#end of sib2, iclass 20, count 0 2006.201.11:26:54.99#ibcon#*after write, iclass 20, count 0 2006.201.11:26:54.99#ibcon#*before return 0, iclass 20, count 0 2006.201.11:26:54.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:54.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:54.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:26:54.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:26:54.99$vck44/va=1,8 2006.201.11:26:54.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.11:26:54.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.11:26:54.99#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:54.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:54.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:54.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:54.99#ibcon#enter wrdev, iclass 22, count 2 2006.201.11:26:54.99#ibcon#first serial, iclass 22, count 2 2006.201.11:26:54.99#ibcon#enter sib2, iclass 22, count 2 2006.201.11:26:54.99#ibcon#flushed, iclass 22, count 2 2006.201.11:26:54.99#ibcon#about to write, iclass 22, count 2 2006.201.11:26:54.99#ibcon#wrote, iclass 22, count 2 2006.201.11:26:54.99#ibcon#about to read 3, iclass 22, count 2 2006.201.11:26:55.01#ibcon#read 3, iclass 22, count 2 2006.201.11:26:55.01#ibcon#about to read 4, iclass 22, count 2 2006.201.11:26:55.01#ibcon#read 4, iclass 22, count 2 2006.201.11:26:55.01#ibcon#about to read 5, iclass 22, count 2 2006.201.11:26:55.01#ibcon#read 5, iclass 22, count 2 2006.201.11:26:55.01#ibcon#about to read 6, iclass 22, count 2 2006.201.11:26:55.01#ibcon#read 6, iclass 22, count 2 2006.201.11:26:55.01#ibcon#end of sib2, iclass 22, count 2 2006.201.11:26:55.01#ibcon#*mode == 0, iclass 22, count 2 2006.201.11:26:55.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.11:26:55.01#ibcon#[25=AT01-08\r\n] 2006.201.11:26:55.01#ibcon#*before write, iclass 22, count 2 2006.201.11:26:55.01#ibcon#enter sib2, iclass 22, count 2 2006.201.11:26:55.01#ibcon#flushed, iclass 22, count 2 2006.201.11:26:55.01#ibcon#about to write, iclass 22, count 2 2006.201.11:26:55.01#ibcon#wrote, iclass 22, count 2 2006.201.11:26:55.01#ibcon#about to read 3, iclass 22, count 2 2006.201.11:26:55.05#ibcon#read 3, iclass 22, count 2 2006.201.11:26:55.05#ibcon#about to read 4, iclass 22, count 2 2006.201.11:26:55.05#ibcon#read 4, iclass 22, count 2 2006.201.11:26:55.05#ibcon#about to read 5, iclass 22, count 2 2006.201.11:26:55.05#ibcon#read 5, iclass 22, count 2 2006.201.11:26:55.05#ibcon#about to read 6, iclass 22, count 2 2006.201.11:26:55.05#ibcon#read 6, iclass 22, count 2 2006.201.11:26:55.05#ibcon#end of sib2, iclass 22, count 2 2006.201.11:26:55.05#ibcon#*after write, iclass 22, count 2 2006.201.11:26:55.05#ibcon#*before return 0, iclass 22, count 2 2006.201.11:26:55.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:55.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:55.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.11:26:55.05#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:55.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:55.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:55.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:55.17#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:26:55.17#ibcon#first serial, iclass 22, count 0 2006.201.11:26:55.17#ibcon#enter sib2, iclass 22, count 0 2006.201.11:26:55.17#ibcon#flushed, iclass 22, count 0 2006.201.11:26:55.17#ibcon#about to write, iclass 22, count 0 2006.201.11:26:55.17#ibcon#wrote, iclass 22, count 0 2006.201.11:26:55.17#ibcon#about to read 3, iclass 22, count 0 2006.201.11:26:55.19#ibcon#read 3, iclass 22, count 0 2006.201.11:26:55.19#ibcon#about to read 4, iclass 22, count 0 2006.201.11:26:55.19#ibcon#read 4, iclass 22, count 0 2006.201.11:26:55.19#ibcon#about to read 5, iclass 22, count 0 2006.201.11:26:55.19#ibcon#read 5, iclass 22, count 0 2006.201.11:26:55.19#ibcon#about to read 6, iclass 22, count 0 2006.201.11:26:55.19#ibcon#read 6, iclass 22, count 0 2006.201.11:26:55.19#ibcon#end of sib2, iclass 22, count 0 2006.201.11:26:55.19#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:26:55.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:26:55.19#ibcon#[25=USB\r\n] 2006.201.11:26:55.19#ibcon#*before write, iclass 22, count 0 2006.201.11:26:55.19#ibcon#enter sib2, iclass 22, count 0 2006.201.11:26:55.19#ibcon#flushed, iclass 22, count 0 2006.201.11:26:55.19#ibcon#about to write, iclass 22, count 0 2006.201.11:26:55.19#ibcon#wrote, iclass 22, count 0 2006.201.11:26:55.19#ibcon#about to read 3, iclass 22, count 0 2006.201.11:26:55.22#ibcon#read 3, iclass 22, count 0 2006.201.11:26:55.22#ibcon#about to read 4, iclass 22, count 0 2006.201.11:26:55.22#ibcon#read 4, iclass 22, count 0 2006.201.11:26:55.22#ibcon#about to read 5, iclass 22, count 0 2006.201.11:26:55.22#ibcon#read 5, iclass 22, count 0 2006.201.11:26:55.22#ibcon#about to read 6, iclass 22, count 0 2006.201.11:26:55.22#ibcon#read 6, iclass 22, count 0 2006.201.11:26:55.22#ibcon#end of sib2, iclass 22, count 0 2006.201.11:26:55.22#ibcon#*after write, iclass 22, count 0 2006.201.11:26:55.22#ibcon#*before return 0, iclass 22, count 0 2006.201.11:26:55.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:55.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:55.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:26:55.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:26:55.22$vck44/valo=2,534.99 2006.201.11:26:55.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.11:26:55.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.11:26:55.22#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:55.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:55.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:55.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:55.22#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:26:55.22#ibcon#first serial, iclass 24, count 0 2006.201.11:26:55.22#ibcon#enter sib2, iclass 24, count 0 2006.201.11:26:55.22#ibcon#flushed, iclass 24, count 0 2006.201.11:26:55.22#ibcon#about to write, iclass 24, count 0 2006.201.11:26:55.22#ibcon#wrote, iclass 24, count 0 2006.201.11:26:55.22#ibcon#about to read 3, iclass 24, count 0 2006.201.11:26:55.24#ibcon#read 3, iclass 24, count 0 2006.201.11:26:55.24#ibcon#about to read 4, iclass 24, count 0 2006.201.11:26:55.24#ibcon#read 4, iclass 24, count 0 2006.201.11:26:55.24#ibcon#about to read 5, iclass 24, count 0 2006.201.11:26:55.24#ibcon#read 5, iclass 24, count 0 2006.201.11:26:55.24#ibcon#about to read 6, iclass 24, count 0 2006.201.11:26:55.24#ibcon#read 6, iclass 24, count 0 2006.201.11:26:55.24#ibcon#end of sib2, iclass 24, count 0 2006.201.11:26:55.24#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:26:55.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:26:55.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:26:55.24#ibcon#*before write, iclass 24, count 0 2006.201.11:26:55.24#ibcon#enter sib2, iclass 24, count 0 2006.201.11:26:55.24#ibcon#flushed, iclass 24, count 0 2006.201.11:26:55.24#ibcon#about to write, iclass 24, count 0 2006.201.11:26:55.24#ibcon#wrote, iclass 24, count 0 2006.201.11:26:55.24#ibcon#about to read 3, iclass 24, count 0 2006.201.11:26:55.28#ibcon#read 3, iclass 24, count 0 2006.201.11:26:55.28#ibcon#about to read 4, iclass 24, count 0 2006.201.11:26:55.28#ibcon#read 4, iclass 24, count 0 2006.201.11:26:55.28#ibcon#about to read 5, iclass 24, count 0 2006.201.11:26:55.28#ibcon#read 5, iclass 24, count 0 2006.201.11:26:55.28#ibcon#about to read 6, iclass 24, count 0 2006.201.11:26:55.28#ibcon#read 6, iclass 24, count 0 2006.201.11:26:55.28#ibcon#end of sib2, iclass 24, count 0 2006.201.11:26:55.28#ibcon#*after write, iclass 24, count 0 2006.201.11:26:55.28#ibcon#*before return 0, iclass 24, count 0 2006.201.11:26:55.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:55.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:55.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:26:55.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:26:55.28$vck44/va=2,7 2006.201.11:26:55.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.11:26:55.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.11:26:55.28#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:55.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:55.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:55.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:55.34#ibcon#enter wrdev, iclass 26, count 2 2006.201.11:26:55.34#ibcon#first serial, iclass 26, count 2 2006.201.11:26:55.34#ibcon#enter sib2, iclass 26, count 2 2006.201.11:26:55.34#ibcon#flushed, iclass 26, count 2 2006.201.11:26:55.34#ibcon#about to write, iclass 26, count 2 2006.201.11:26:55.34#ibcon#wrote, iclass 26, count 2 2006.201.11:26:55.34#ibcon#about to read 3, iclass 26, count 2 2006.201.11:26:55.36#ibcon#read 3, iclass 26, count 2 2006.201.11:26:55.36#ibcon#about to read 4, iclass 26, count 2 2006.201.11:26:55.36#ibcon#read 4, iclass 26, count 2 2006.201.11:26:55.36#ibcon#about to read 5, iclass 26, count 2 2006.201.11:26:55.36#ibcon#read 5, iclass 26, count 2 2006.201.11:26:55.36#ibcon#about to read 6, iclass 26, count 2 2006.201.11:26:55.36#ibcon#read 6, iclass 26, count 2 2006.201.11:26:55.36#ibcon#end of sib2, iclass 26, count 2 2006.201.11:26:55.36#ibcon#*mode == 0, iclass 26, count 2 2006.201.11:26:55.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.11:26:55.36#ibcon#[25=AT02-07\r\n] 2006.201.11:26:55.36#ibcon#*before write, iclass 26, count 2 2006.201.11:26:55.36#ibcon#enter sib2, iclass 26, count 2 2006.201.11:26:55.36#ibcon#flushed, iclass 26, count 2 2006.201.11:26:55.36#ibcon#about to write, iclass 26, count 2 2006.201.11:26:55.36#ibcon#wrote, iclass 26, count 2 2006.201.11:26:55.36#ibcon#about to read 3, iclass 26, count 2 2006.201.11:26:55.39#ibcon#read 3, iclass 26, count 2 2006.201.11:26:55.39#ibcon#about to read 4, iclass 26, count 2 2006.201.11:26:55.39#ibcon#read 4, iclass 26, count 2 2006.201.11:26:55.39#ibcon#about to read 5, iclass 26, count 2 2006.201.11:26:55.39#ibcon#read 5, iclass 26, count 2 2006.201.11:26:55.39#ibcon#about to read 6, iclass 26, count 2 2006.201.11:26:55.39#ibcon#read 6, iclass 26, count 2 2006.201.11:26:55.39#ibcon#end of sib2, iclass 26, count 2 2006.201.11:26:55.39#ibcon#*after write, iclass 26, count 2 2006.201.11:26:55.39#ibcon#*before return 0, iclass 26, count 2 2006.201.11:26:55.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:55.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:55.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.11:26:55.39#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:55.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:55.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:55.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:55.51#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:26:55.51#ibcon#first serial, iclass 26, count 0 2006.201.11:26:55.51#ibcon#enter sib2, iclass 26, count 0 2006.201.11:26:55.51#ibcon#flushed, iclass 26, count 0 2006.201.11:26:55.51#ibcon#about to write, iclass 26, count 0 2006.201.11:26:55.51#ibcon#wrote, iclass 26, count 0 2006.201.11:26:55.51#ibcon#about to read 3, iclass 26, count 0 2006.201.11:26:55.53#ibcon#read 3, iclass 26, count 0 2006.201.11:26:55.53#ibcon#about to read 4, iclass 26, count 0 2006.201.11:26:55.53#ibcon#read 4, iclass 26, count 0 2006.201.11:26:55.53#ibcon#about to read 5, iclass 26, count 0 2006.201.11:26:55.53#ibcon#read 5, iclass 26, count 0 2006.201.11:26:55.53#ibcon#about to read 6, iclass 26, count 0 2006.201.11:26:55.53#ibcon#read 6, iclass 26, count 0 2006.201.11:26:55.53#ibcon#end of sib2, iclass 26, count 0 2006.201.11:26:55.53#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:26:55.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:26:55.53#ibcon#[25=USB\r\n] 2006.201.11:26:55.53#ibcon#*before write, iclass 26, count 0 2006.201.11:26:55.53#ibcon#enter sib2, iclass 26, count 0 2006.201.11:26:55.53#ibcon#flushed, iclass 26, count 0 2006.201.11:26:55.53#ibcon#about to write, iclass 26, count 0 2006.201.11:26:55.53#ibcon#wrote, iclass 26, count 0 2006.201.11:26:55.53#ibcon#about to read 3, iclass 26, count 0 2006.201.11:26:55.56#ibcon#read 3, iclass 26, count 0 2006.201.11:26:55.56#ibcon#about to read 4, iclass 26, count 0 2006.201.11:26:55.56#ibcon#read 4, iclass 26, count 0 2006.201.11:26:55.56#ibcon#about to read 5, iclass 26, count 0 2006.201.11:26:55.56#ibcon#read 5, iclass 26, count 0 2006.201.11:26:55.56#ibcon#about to read 6, iclass 26, count 0 2006.201.11:26:55.56#ibcon#read 6, iclass 26, count 0 2006.201.11:26:55.56#ibcon#end of sib2, iclass 26, count 0 2006.201.11:26:55.56#ibcon#*after write, iclass 26, count 0 2006.201.11:26:55.56#ibcon#*before return 0, iclass 26, count 0 2006.201.11:26:55.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:55.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:55.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:26:55.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:26:55.56$vck44/valo=3,564.99 2006.201.11:26:55.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.11:26:55.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.11:26:55.56#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:55.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:55.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:55.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:55.56#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:26:55.56#ibcon#first serial, iclass 28, count 0 2006.201.11:26:55.56#ibcon#enter sib2, iclass 28, count 0 2006.201.11:26:55.56#ibcon#flushed, iclass 28, count 0 2006.201.11:26:55.56#ibcon#about to write, iclass 28, count 0 2006.201.11:26:55.56#ibcon#wrote, iclass 28, count 0 2006.201.11:26:55.56#ibcon#about to read 3, iclass 28, count 0 2006.201.11:26:55.58#ibcon#read 3, iclass 28, count 0 2006.201.11:26:55.58#ibcon#about to read 4, iclass 28, count 0 2006.201.11:26:55.58#ibcon#read 4, iclass 28, count 0 2006.201.11:26:55.58#ibcon#about to read 5, iclass 28, count 0 2006.201.11:26:55.58#ibcon#read 5, iclass 28, count 0 2006.201.11:26:55.58#ibcon#about to read 6, iclass 28, count 0 2006.201.11:26:55.58#ibcon#read 6, iclass 28, count 0 2006.201.11:26:55.58#ibcon#end of sib2, iclass 28, count 0 2006.201.11:26:55.58#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:26:55.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:26:55.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:26:55.58#ibcon#*before write, iclass 28, count 0 2006.201.11:26:55.58#ibcon#enter sib2, iclass 28, count 0 2006.201.11:26:55.58#ibcon#flushed, iclass 28, count 0 2006.201.11:26:55.58#ibcon#about to write, iclass 28, count 0 2006.201.11:26:55.58#ibcon#wrote, iclass 28, count 0 2006.201.11:26:55.58#ibcon#about to read 3, iclass 28, count 0 2006.201.11:26:55.63#ibcon#read 3, iclass 28, count 0 2006.201.11:26:55.63#ibcon#about to read 4, iclass 28, count 0 2006.201.11:26:55.63#ibcon#read 4, iclass 28, count 0 2006.201.11:26:55.63#ibcon#about to read 5, iclass 28, count 0 2006.201.11:26:55.63#ibcon#read 5, iclass 28, count 0 2006.201.11:26:55.63#ibcon#about to read 6, iclass 28, count 0 2006.201.11:26:55.63#ibcon#read 6, iclass 28, count 0 2006.201.11:26:55.63#ibcon#end of sib2, iclass 28, count 0 2006.201.11:26:55.63#ibcon#*after write, iclass 28, count 0 2006.201.11:26:55.63#ibcon#*before return 0, iclass 28, count 0 2006.201.11:26:55.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:55.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:55.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:26:55.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:26:55.63$vck44/va=3,8 2006.201.11:26:55.63#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.11:26:55.63#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.11:26:55.63#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:55.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:55.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:55.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:55.68#ibcon#enter wrdev, iclass 30, count 2 2006.201.11:26:55.68#ibcon#first serial, iclass 30, count 2 2006.201.11:26:55.68#ibcon#enter sib2, iclass 30, count 2 2006.201.11:26:55.68#ibcon#flushed, iclass 30, count 2 2006.201.11:26:55.68#ibcon#about to write, iclass 30, count 2 2006.201.11:26:55.68#ibcon#wrote, iclass 30, count 2 2006.201.11:26:55.68#ibcon#about to read 3, iclass 30, count 2 2006.201.11:26:55.70#ibcon#read 3, iclass 30, count 2 2006.201.11:26:55.70#ibcon#about to read 4, iclass 30, count 2 2006.201.11:26:55.70#ibcon#read 4, iclass 30, count 2 2006.201.11:26:55.70#ibcon#about to read 5, iclass 30, count 2 2006.201.11:26:55.70#ibcon#read 5, iclass 30, count 2 2006.201.11:26:55.70#ibcon#about to read 6, iclass 30, count 2 2006.201.11:26:55.70#ibcon#read 6, iclass 30, count 2 2006.201.11:26:55.70#ibcon#end of sib2, iclass 30, count 2 2006.201.11:26:55.70#ibcon#*mode == 0, iclass 30, count 2 2006.201.11:26:55.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.11:26:55.70#ibcon#[25=AT03-08\r\n] 2006.201.11:26:55.70#ibcon#*before write, iclass 30, count 2 2006.201.11:26:55.70#ibcon#enter sib2, iclass 30, count 2 2006.201.11:26:55.70#ibcon#flushed, iclass 30, count 2 2006.201.11:26:55.70#ibcon#about to write, iclass 30, count 2 2006.201.11:26:55.70#ibcon#wrote, iclass 30, count 2 2006.201.11:26:55.70#ibcon#about to read 3, iclass 30, count 2 2006.201.11:26:55.73#ibcon#read 3, iclass 30, count 2 2006.201.11:26:55.73#ibcon#about to read 4, iclass 30, count 2 2006.201.11:26:55.73#ibcon#read 4, iclass 30, count 2 2006.201.11:26:55.73#ibcon#about to read 5, iclass 30, count 2 2006.201.11:26:55.73#ibcon#read 5, iclass 30, count 2 2006.201.11:26:55.73#ibcon#about to read 6, iclass 30, count 2 2006.201.11:26:55.73#ibcon#read 6, iclass 30, count 2 2006.201.11:26:55.73#ibcon#end of sib2, iclass 30, count 2 2006.201.11:26:55.73#ibcon#*after write, iclass 30, count 2 2006.201.11:26:55.73#ibcon#*before return 0, iclass 30, count 2 2006.201.11:26:55.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:55.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:55.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.11:26:55.73#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:55.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:55.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:55.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:55.85#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:26:55.85#ibcon#first serial, iclass 30, count 0 2006.201.11:26:55.85#ibcon#enter sib2, iclass 30, count 0 2006.201.11:26:55.85#ibcon#flushed, iclass 30, count 0 2006.201.11:26:55.85#ibcon#about to write, iclass 30, count 0 2006.201.11:26:55.85#ibcon#wrote, iclass 30, count 0 2006.201.11:26:55.85#ibcon#about to read 3, iclass 30, count 0 2006.201.11:26:55.87#ibcon#read 3, iclass 30, count 0 2006.201.11:26:55.87#ibcon#about to read 4, iclass 30, count 0 2006.201.11:26:55.87#ibcon#read 4, iclass 30, count 0 2006.201.11:26:55.87#ibcon#about to read 5, iclass 30, count 0 2006.201.11:26:55.87#ibcon#read 5, iclass 30, count 0 2006.201.11:26:55.87#ibcon#about to read 6, iclass 30, count 0 2006.201.11:26:55.87#ibcon#read 6, iclass 30, count 0 2006.201.11:26:55.87#ibcon#end of sib2, iclass 30, count 0 2006.201.11:26:55.87#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:26:55.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:26:55.87#ibcon#[25=USB\r\n] 2006.201.11:26:55.87#ibcon#*before write, iclass 30, count 0 2006.201.11:26:55.87#ibcon#enter sib2, iclass 30, count 0 2006.201.11:26:55.87#ibcon#flushed, iclass 30, count 0 2006.201.11:26:55.87#ibcon#about to write, iclass 30, count 0 2006.201.11:26:55.87#ibcon#wrote, iclass 30, count 0 2006.201.11:26:55.87#ibcon#about to read 3, iclass 30, count 0 2006.201.11:26:55.90#ibcon#read 3, iclass 30, count 0 2006.201.11:26:55.90#ibcon#about to read 4, iclass 30, count 0 2006.201.11:26:55.90#ibcon#read 4, iclass 30, count 0 2006.201.11:26:55.90#ibcon#about to read 5, iclass 30, count 0 2006.201.11:26:55.90#ibcon#read 5, iclass 30, count 0 2006.201.11:26:55.90#ibcon#about to read 6, iclass 30, count 0 2006.201.11:26:55.90#ibcon#read 6, iclass 30, count 0 2006.201.11:26:55.90#ibcon#end of sib2, iclass 30, count 0 2006.201.11:26:55.90#ibcon#*after write, iclass 30, count 0 2006.201.11:26:55.90#ibcon#*before return 0, iclass 30, count 0 2006.201.11:26:55.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:55.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:55.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:26:55.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:26:55.90$vck44/valo=4,624.99 2006.201.11:26:55.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.11:26:55.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.11:26:55.90#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:55.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:55.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:55.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:55.90#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:26:55.90#ibcon#first serial, iclass 32, count 0 2006.201.11:26:55.90#ibcon#enter sib2, iclass 32, count 0 2006.201.11:26:55.90#ibcon#flushed, iclass 32, count 0 2006.201.11:26:55.90#ibcon#about to write, iclass 32, count 0 2006.201.11:26:55.90#ibcon#wrote, iclass 32, count 0 2006.201.11:26:55.90#ibcon#about to read 3, iclass 32, count 0 2006.201.11:26:55.92#ibcon#read 3, iclass 32, count 0 2006.201.11:26:55.92#ibcon#about to read 4, iclass 32, count 0 2006.201.11:26:55.92#ibcon#read 4, iclass 32, count 0 2006.201.11:26:55.92#ibcon#about to read 5, iclass 32, count 0 2006.201.11:26:55.92#ibcon#read 5, iclass 32, count 0 2006.201.11:26:55.92#ibcon#about to read 6, iclass 32, count 0 2006.201.11:26:55.92#ibcon#read 6, iclass 32, count 0 2006.201.11:26:55.92#ibcon#end of sib2, iclass 32, count 0 2006.201.11:26:55.92#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:26:55.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:26:55.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:26:55.92#ibcon#*before write, iclass 32, count 0 2006.201.11:26:55.92#ibcon#enter sib2, iclass 32, count 0 2006.201.11:26:55.92#ibcon#flushed, iclass 32, count 0 2006.201.11:26:55.92#ibcon#about to write, iclass 32, count 0 2006.201.11:26:55.92#ibcon#wrote, iclass 32, count 0 2006.201.11:26:55.92#ibcon#about to read 3, iclass 32, count 0 2006.201.11:26:55.96#ibcon#read 3, iclass 32, count 0 2006.201.11:26:55.96#ibcon#about to read 4, iclass 32, count 0 2006.201.11:26:55.96#ibcon#read 4, iclass 32, count 0 2006.201.11:26:55.96#ibcon#about to read 5, iclass 32, count 0 2006.201.11:26:55.96#ibcon#read 5, iclass 32, count 0 2006.201.11:26:55.96#ibcon#about to read 6, iclass 32, count 0 2006.201.11:26:55.96#ibcon#read 6, iclass 32, count 0 2006.201.11:26:55.96#ibcon#end of sib2, iclass 32, count 0 2006.201.11:26:55.96#ibcon#*after write, iclass 32, count 0 2006.201.11:26:55.96#ibcon#*before return 0, iclass 32, count 0 2006.201.11:26:55.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:55.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:55.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:26:55.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:26:55.96$vck44/va=4,7 2006.201.11:26:55.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.11:26:55.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.11:26:55.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:55.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:56.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:56.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:56.02#ibcon#enter wrdev, iclass 34, count 2 2006.201.11:26:56.02#ibcon#first serial, iclass 34, count 2 2006.201.11:26:56.02#ibcon#enter sib2, iclass 34, count 2 2006.201.11:26:56.02#ibcon#flushed, iclass 34, count 2 2006.201.11:26:56.02#ibcon#about to write, iclass 34, count 2 2006.201.11:26:56.02#ibcon#wrote, iclass 34, count 2 2006.201.11:26:56.02#ibcon#about to read 3, iclass 34, count 2 2006.201.11:26:56.04#ibcon#read 3, iclass 34, count 2 2006.201.11:26:56.04#ibcon#about to read 4, iclass 34, count 2 2006.201.11:26:56.04#ibcon#read 4, iclass 34, count 2 2006.201.11:26:56.04#ibcon#about to read 5, iclass 34, count 2 2006.201.11:26:56.04#ibcon#read 5, iclass 34, count 2 2006.201.11:26:56.04#ibcon#about to read 6, iclass 34, count 2 2006.201.11:26:56.04#ibcon#read 6, iclass 34, count 2 2006.201.11:26:56.04#ibcon#end of sib2, iclass 34, count 2 2006.201.11:26:56.04#ibcon#*mode == 0, iclass 34, count 2 2006.201.11:26:56.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.11:26:56.04#ibcon#[25=AT04-07\r\n] 2006.201.11:26:56.04#ibcon#*before write, iclass 34, count 2 2006.201.11:26:56.04#ibcon#enter sib2, iclass 34, count 2 2006.201.11:26:56.04#ibcon#flushed, iclass 34, count 2 2006.201.11:26:56.04#ibcon#about to write, iclass 34, count 2 2006.201.11:26:56.04#ibcon#wrote, iclass 34, count 2 2006.201.11:26:56.04#ibcon#about to read 3, iclass 34, count 2 2006.201.11:26:56.07#ibcon#read 3, iclass 34, count 2 2006.201.11:26:56.07#ibcon#about to read 4, iclass 34, count 2 2006.201.11:26:56.07#ibcon#read 4, iclass 34, count 2 2006.201.11:26:56.07#ibcon#about to read 5, iclass 34, count 2 2006.201.11:26:56.07#ibcon#read 5, iclass 34, count 2 2006.201.11:26:56.07#ibcon#about to read 6, iclass 34, count 2 2006.201.11:26:56.07#ibcon#read 6, iclass 34, count 2 2006.201.11:26:56.07#ibcon#end of sib2, iclass 34, count 2 2006.201.11:26:56.07#ibcon#*after write, iclass 34, count 2 2006.201.11:26:56.07#ibcon#*before return 0, iclass 34, count 2 2006.201.11:26:56.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:56.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:56.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.11:26:56.07#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:56.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:56.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:56.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:56.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:26:56.19#ibcon#first serial, iclass 34, count 0 2006.201.11:26:56.19#ibcon#enter sib2, iclass 34, count 0 2006.201.11:26:56.19#ibcon#flushed, iclass 34, count 0 2006.201.11:26:56.19#ibcon#about to write, iclass 34, count 0 2006.201.11:26:56.19#ibcon#wrote, iclass 34, count 0 2006.201.11:26:56.19#ibcon#about to read 3, iclass 34, count 0 2006.201.11:26:56.21#ibcon#read 3, iclass 34, count 0 2006.201.11:26:56.21#ibcon#about to read 4, iclass 34, count 0 2006.201.11:26:56.21#ibcon#read 4, iclass 34, count 0 2006.201.11:26:56.21#ibcon#about to read 5, iclass 34, count 0 2006.201.11:26:56.21#ibcon#read 5, iclass 34, count 0 2006.201.11:26:56.21#ibcon#about to read 6, iclass 34, count 0 2006.201.11:26:56.21#ibcon#read 6, iclass 34, count 0 2006.201.11:26:56.21#ibcon#end of sib2, iclass 34, count 0 2006.201.11:26:56.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:26:56.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:26:56.21#ibcon#[25=USB\r\n] 2006.201.11:26:56.21#ibcon#*before write, iclass 34, count 0 2006.201.11:26:56.21#ibcon#enter sib2, iclass 34, count 0 2006.201.11:26:56.21#ibcon#flushed, iclass 34, count 0 2006.201.11:26:56.21#ibcon#about to write, iclass 34, count 0 2006.201.11:26:56.21#ibcon#wrote, iclass 34, count 0 2006.201.11:26:56.21#ibcon#about to read 3, iclass 34, count 0 2006.201.11:26:56.24#ibcon#read 3, iclass 34, count 0 2006.201.11:26:56.24#ibcon#about to read 4, iclass 34, count 0 2006.201.11:26:56.24#ibcon#read 4, iclass 34, count 0 2006.201.11:26:56.24#ibcon#about to read 5, iclass 34, count 0 2006.201.11:26:56.24#ibcon#read 5, iclass 34, count 0 2006.201.11:26:56.24#ibcon#about to read 6, iclass 34, count 0 2006.201.11:26:56.24#ibcon#read 6, iclass 34, count 0 2006.201.11:26:56.24#ibcon#end of sib2, iclass 34, count 0 2006.201.11:26:56.24#ibcon#*after write, iclass 34, count 0 2006.201.11:26:56.24#ibcon#*before return 0, iclass 34, count 0 2006.201.11:26:56.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:56.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:56.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:26:56.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:26:56.24$vck44/valo=5,734.99 2006.201.11:26:56.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.11:26:56.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.11:26:56.24#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:56.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:56.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:56.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:56.24#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:26:56.24#ibcon#first serial, iclass 36, count 0 2006.201.11:26:56.24#ibcon#enter sib2, iclass 36, count 0 2006.201.11:26:56.24#ibcon#flushed, iclass 36, count 0 2006.201.11:26:56.24#ibcon#about to write, iclass 36, count 0 2006.201.11:26:56.24#ibcon#wrote, iclass 36, count 0 2006.201.11:26:56.24#ibcon#about to read 3, iclass 36, count 0 2006.201.11:26:56.26#ibcon#read 3, iclass 36, count 0 2006.201.11:26:56.26#ibcon#about to read 4, iclass 36, count 0 2006.201.11:26:56.26#ibcon#read 4, iclass 36, count 0 2006.201.11:26:56.26#ibcon#about to read 5, iclass 36, count 0 2006.201.11:26:56.26#ibcon#read 5, iclass 36, count 0 2006.201.11:26:56.26#ibcon#about to read 6, iclass 36, count 0 2006.201.11:26:56.26#ibcon#read 6, iclass 36, count 0 2006.201.11:26:56.26#ibcon#end of sib2, iclass 36, count 0 2006.201.11:26:56.26#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:26:56.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:26:56.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:26:56.26#ibcon#*before write, iclass 36, count 0 2006.201.11:26:56.26#ibcon#enter sib2, iclass 36, count 0 2006.201.11:26:56.26#ibcon#flushed, iclass 36, count 0 2006.201.11:26:56.26#ibcon#about to write, iclass 36, count 0 2006.201.11:26:56.26#ibcon#wrote, iclass 36, count 0 2006.201.11:26:56.26#ibcon#about to read 3, iclass 36, count 0 2006.201.11:26:56.30#ibcon#read 3, iclass 36, count 0 2006.201.11:26:56.30#ibcon#about to read 4, iclass 36, count 0 2006.201.11:26:56.30#ibcon#read 4, iclass 36, count 0 2006.201.11:26:56.30#ibcon#about to read 5, iclass 36, count 0 2006.201.11:26:56.30#ibcon#read 5, iclass 36, count 0 2006.201.11:26:56.30#ibcon#about to read 6, iclass 36, count 0 2006.201.11:26:56.30#ibcon#read 6, iclass 36, count 0 2006.201.11:26:56.30#ibcon#end of sib2, iclass 36, count 0 2006.201.11:26:56.30#ibcon#*after write, iclass 36, count 0 2006.201.11:26:56.30#ibcon#*before return 0, iclass 36, count 0 2006.201.11:26:56.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:56.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:56.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:26:56.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:26:56.30$vck44/va=5,4 2006.201.11:26:56.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.11:26:56.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.11:26:56.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:56.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:56.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:56.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:56.36#ibcon#enter wrdev, iclass 38, count 2 2006.201.11:26:56.36#ibcon#first serial, iclass 38, count 2 2006.201.11:26:56.36#ibcon#enter sib2, iclass 38, count 2 2006.201.11:26:56.36#ibcon#flushed, iclass 38, count 2 2006.201.11:26:56.36#ibcon#about to write, iclass 38, count 2 2006.201.11:26:56.36#ibcon#wrote, iclass 38, count 2 2006.201.11:26:56.36#ibcon#about to read 3, iclass 38, count 2 2006.201.11:26:56.38#ibcon#read 3, iclass 38, count 2 2006.201.11:26:56.38#ibcon#about to read 4, iclass 38, count 2 2006.201.11:26:56.38#ibcon#read 4, iclass 38, count 2 2006.201.11:26:56.38#ibcon#about to read 5, iclass 38, count 2 2006.201.11:26:56.38#ibcon#read 5, iclass 38, count 2 2006.201.11:26:56.38#ibcon#about to read 6, iclass 38, count 2 2006.201.11:26:56.38#ibcon#read 6, iclass 38, count 2 2006.201.11:26:56.38#ibcon#end of sib2, iclass 38, count 2 2006.201.11:26:56.38#ibcon#*mode == 0, iclass 38, count 2 2006.201.11:26:56.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.11:26:56.38#ibcon#[25=AT05-04\r\n] 2006.201.11:26:56.38#ibcon#*before write, iclass 38, count 2 2006.201.11:26:56.38#ibcon#enter sib2, iclass 38, count 2 2006.201.11:26:56.38#ibcon#flushed, iclass 38, count 2 2006.201.11:26:56.38#ibcon#about to write, iclass 38, count 2 2006.201.11:26:56.38#ibcon#wrote, iclass 38, count 2 2006.201.11:26:56.38#ibcon#about to read 3, iclass 38, count 2 2006.201.11:26:56.41#ibcon#read 3, iclass 38, count 2 2006.201.11:26:56.41#ibcon#about to read 4, iclass 38, count 2 2006.201.11:26:56.41#ibcon#read 4, iclass 38, count 2 2006.201.11:26:56.41#ibcon#about to read 5, iclass 38, count 2 2006.201.11:26:56.41#ibcon#read 5, iclass 38, count 2 2006.201.11:26:56.41#ibcon#about to read 6, iclass 38, count 2 2006.201.11:26:56.41#ibcon#read 6, iclass 38, count 2 2006.201.11:26:56.41#ibcon#end of sib2, iclass 38, count 2 2006.201.11:26:56.41#ibcon#*after write, iclass 38, count 2 2006.201.11:26:56.41#ibcon#*before return 0, iclass 38, count 2 2006.201.11:26:56.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:56.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:56.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.11:26:56.41#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:56.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:56.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:56.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:56.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:26:56.53#ibcon#first serial, iclass 38, count 0 2006.201.11:26:56.53#ibcon#enter sib2, iclass 38, count 0 2006.201.11:26:56.53#ibcon#flushed, iclass 38, count 0 2006.201.11:26:56.53#ibcon#about to write, iclass 38, count 0 2006.201.11:26:56.53#ibcon#wrote, iclass 38, count 0 2006.201.11:26:56.53#ibcon#about to read 3, iclass 38, count 0 2006.201.11:26:56.55#ibcon#read 3, iclass 38, count 0 2006.201.11:26:56.55#ibcon#about to read 4, iclass 38, count 0 2006.201.11:26:56.55#ibcon#read 4, iclass 38, count 0 2006.201.11:26:56.55#ibcon#about to read 5, iclass 38, count 0 2006.201.11:26:56.55#ibcon#read 5, iclass 38, count 0 2006.201.11:26:56.55#ibcon#about to read 6, iclass 38, count 0 2006.201.11:26:56.55#ibcon#read 6, iclass 38, count 0 2006.201.11:26:56.55#ibcon#end of sib2, iclass 38, count 0 2006.201.11:26:56.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:26:56.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:26:56.55#ibcon#[25=USB\r\n] 2006.201.11:26:56.55#ibcon#*before write, iclass 38, count 0 2006.201.11:26:56.55#ibcon#enter sib2, iclass 38, count 0 2006.201.11:26:56.55#ibcon#flushed, iclass 38, count 0 2006.201.11:26:56.55#ibcon#about to write, iclass 38, count 0 2006.201.11:26:56.55#ibcon#wrote, iclass 38, count 0 2006.201.11:26:56.55#ibcon#about to read 3, iclass 38, count 0 2006.201.11:26:56.58#ibcon#read 3, iclass 38, count 0 2006.201.11:26:56.58#ibcon#about to read 4, iclass 38, count 0 2006.201.11:26:56.58#ibcon#read 4, iclass 38, count 0 2006.201.11:26:56.58#ibcon#about to read 5, iclass 38, count 0 2006.201.11:26:56.58#ibcon#read 5, iclass 38, count 0 2006.201.11:26:56.58#ibcon#about to read 6, iclass 38, count 0 2006.201.11:26:56.58#ibcon#read 6, iclass 38, count 0 2006.201.11:26:56.58#ibcon#end of sib2, iclass 38, count 0 2006.201.11:26:56.58#ibcon#*after write, iclass 38, count 0 2006.201.11:26:56.58#ibcon#*before return 0, iclass 38, count 0 2006.201.11:26:56.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:56.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:56.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:26:56.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:26:56.58$vck44/valo=6,814.99 2006.201.11:26:56.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.11:26:56.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.11:26:56.58#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:56.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:56.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:56.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:56.58#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:26:56.58#ibcon#first serial, iclass 40, count 0 2006.201.11:26:56.58#ibcon#enter sib2, iclass 40, count 0 2006.201.11:26:56.58#ibcon#flushed, iclass 40, count 0 2006.201.11:26:56.58#ibcon#about to write, iclass 40, count 0 2006.201.11:26:56.58#ibcon#wrote, iclass 40, count 0 2006.201.11:26:56.58#ibcon#about to read 3, iclass 40, count 0 2006.201.11:26:56.60#ibcon#read 3, iclass 40, count 0 2006.201.11:26:56.60#ibcon#about to read 4, iclass 40, count 0 2006.201.11:26:56.60#ibcon#read 4, iclass 40, count 0 2006.201.11:26:56.60#ibcon#about to read 5, iclass 40, count 0 2006.201.11:26:56.60#ibcon#read 5, iclass 40, count 0 2006.201.11:26:56.60#ibcon#about to read 6, iclass 40, count 0 2006.201.11:26:56.60#ibcon#read 6, iclass 40, count 0 2006.201.11:26:56.60#ibcon#end of sib2, iclass 40, count 0 2006.201.11:26:56.60#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:26:56.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:26:56.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:26:56.60#ibcon#*before write, iclass 40, count 0 2006.201.11:26:56.60#ibcon#enter sib2, iclass 40, count 0 2006.201.11:26:56.60#ibcon#flushed, iclass 40, count 0 2006.201.11:26:56.60#ibcon#about to write, iclass 40, count 0 2006.201.11:26:56.60#ibcon#wrote, iclass 40, count 0 2006.201.11:26:56.60#ibcon#about to read 3, iclass 40, count 0 2006.201.11:26:56.65#ibcon#read 3, iclass 40, count 0 2006.201.11:26:56.65#ibcon#about to read 4, iclass 40, count 0 2006.201.11:26:56.65#ibcon#read 4, iclass 40, count 0 2006.201.11:26:56.65#ibcon#about to read 5, iclass 40, count 0 2006.201.11:26:56.65#ibcon#read 5, iclass 40, count 0 2006.201.11:26:56.65#ibcon#about to read 6, iclass 40, count 0 2006.201.11:26:56.65#ibcon#read 6, iclass 40, count 0 2006.201.11:26:56.65#ibcon#end of sib2, iclass 40, count 0 2006.201.11:26:56.65#ibcon#*after write, iclass 40, count 0 2006.201.11:26:56.65#ibcon#*before return 0, iclass 40, count 0 2006.201.11:26:56.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:56.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:56.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:26:56.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:26:56.65$vck44/va=6,5 2006.201.11:26:56.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.11:26:56.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.11:26:56.65#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:56.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:56.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:56.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:56.70#ibcon#enter wrdev, iclass 4, count 2 2006.201.11:26:56.70#ibcon#first serial, iclass 4, count 2 2006.201.11:26:56.70#ibcon#enter sib2, iclass 4, count 2 2006.201.11:26:56.70#ibcon#flushed, iclass 4, count 2 2006.201.11:26:56.70#ibcon#about to write, iclass 4, count 2 2006.201.11:26:56.70#ibcon#wrote, iclass 4, count 2 2006.201.11:26:56.70#ibcon#about to read 3, iclass 4, count 2 2006.201.11:26:56.72#ibcon#read 3, iclass 4, count 2 2006.201.11:26:56.72#ibcon#about to read 4, iclass 4, count 2 2006.201.11:26:56.72#ibcon#read 4, iclass 4, count 2 2006.201.11:26:56.72#ibcon#about to read 5, iclass 4, count 2 2006.201.11:26:56.72#ibcon#read 5, iclass 4, count 2 2006.201.11:26:56.72#ibcon#about to read 6, iclass 4, count 2 2006.201.11:26:56.72#ibcon#read 6, iclass 4, count 2 2006.201.11:26:56.72#ibcon#end of sib2, iclass 4, count 2 2006.201.11:26:56.72#ibcon#*mode == 0, iclass 4, count 2 2006.201.11:26:56.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.11:26:56.72#ibcon#[25=AT06-05\r\n] 2006.201.11:26:56.72#ibcon#*before write, iclass 4, count 2 2006.201.11:26:56.72#ibcon#enter sib2, iclass 4, count 2 2006.201.11:26:56.72#ibcon#flushed, iclass 4, count 2 2006.201.11:26:56.72#ibcon#about to write, iclass 4, count 2 2006.201.11:26:56.72#ibcon#wrote, iclass 4, count 2 2006.201.11:26:56.72#ibcon#about to read 3, iclass 4, count 2 2006.201.11:26:56.75#ibcon#read 3, iclass 4, count 2 2006.201.11:26:56.75#ibcon#about to read 4, iclass 4, count 2 2006.201.11:26:56.75#ibcon#read 4, iclass 4, count 2 2006.201.11:26:56.75#ibcon#about to read 5, iclass 4, count 2 2006.201.11:26:56.75#ibcon#read 5, iclass 4, count 2 2006.201.11:26:56.75#ibcon#about to read 6, iclass 4, count 2 2006.201.11:26:56.75#ibcon#read 6, iclass 4, count 2 2006.201.11:26:56.75#ibcon#end of sib2, iclass 4, count 2 2006.201.11:26:56.75#ibcon#*after write, iclass 4, count 2 2006.201.11:26:56.75#ibcon#*before return 0, iclass 4, count 2 2006.201.11:26:56.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:56.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:56.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.11:26:56.75#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:56.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:56.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:56.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:56.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:26:56.87#ibcon#first serial, iclass 4, count 0 2006.201.11:26:56.87#ibcon#enter sib2, iclass 4, count 0 2006.201.11:26:56.87#ibcon#flushed, iclass 4, count 0 2006.201.11:26:56.87#ibcon#about to write, iclass 4, count 0 2006.201.11:26:56.87#ibcon#wrote, iclass 4, count 0 2006.201.11:26:56.87#ibcon#about to read 3, iclass 4, count 0 2006.201.11:26:56.89#ibcon#read 3, iclass 4, count 0 2006.201.11:26:56.89#ibcon#about to read 4, iclass 4, count 0 2006.201.11:26:56.89#ibcon#read 4, iclass 4, count 0 2006.201.11:26:56.89#ibcon#about to read 5, iclass 4, count 0 2006.201.11:26:56.89#ibcon#read 5, iclass 4, count 0 2006.201.11:26:56.89#ibcon#about to read 6, iclass 4, count 0 2006.201.11:26:56.89#ibcon#read 6, iclass 4, count 0 2006.201.11:26:56.89#ibcon#end of sib2, iclass 4, count 0 2006.201.11:26:56.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:26:56.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:26:56.89#ibcon#[25=USB\r\n] 2006.201.11:26:56.89#ibcon#*before write, iclass 4, count 0 2006.201.11:26:56.89#ibcon#enter sib2, iclass 4, count 0 2006.201.11:26:56.89#ibcon#flushed, iclass 4, count 0 2006.201.11:26:56.89#ibcon#about to write, iclass 4, count 0 2006.201.11:26:56.89#ibcon#wrote, iclass 4, count 0 2006.201.11:26:56.89#ibcon#about to read 3, iclass 4, count 0 2006.201.11:26:56.92#ibcon#read 3, iclass 4, count 0 2006.201.11:26:56.92#ibcon#about to read 4, iclass 4, count 0 2006.201.11:26:56.92#ibcon#read 4, iclass 4, count 0 2006.201.11:26:56.92#ibcon#about to read 5, iclass 4, count 0 2006.201.11:26:56.92#ibcon#read 5, iclass 4, count 0 2006.201.11:26:56.92#ibcon#about to read 6, iclass 4, count 0 2006.201.11:26:56.92#ibcon#read 6, iclass 4, count 0 2006.201.11:26:56.92#ibcon#end of sib2, iclass 4, count 0 2006.201.11:26:56.92#ibcon#*after write, iclass 4, count 0 2006.201.11:26:56.92#ibcon#*before return 0, iclass 4, count 0 2006.201.11:26:56.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:56.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:56.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:26:56.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:26:56.92$vck44/valo=7,864.99 2006.201.11:26:56.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.11:26:56.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.11:26:56.92#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:56.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:26:56.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:26:56.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:26:56.92#ibcon#enter wrdev, iclass 6, count 0 2006.201.11:26:56.92#ibcon#first serial, iclass 6, count 0 2006.201.11:26:56.92#ibcon#enter sib2, iclass 6, count 0 2006.201.11:26:56.92#ibcon#flushed, iclass 6, count 0 2006.201.11:26:56.92#ibcon#about to write, iclass 6, count 0 2006.201.11:26:56.92#ibcon#wrote, iclass 6, count 0 2006.201.11:26:56.92#ibcon#about to read 3, iclass 6, count 0 2006.201.11:26:56.94#ibcon#read 3, iclass 6, count 0 2006.201.11:26:56.94#ibcon#about to read 4, iclass 6, count 0 2006.201.11:26:56.94#ibcon#read 4, iclass 6, count 0 2006.201.11:26:56.94#ibcon#about to read 5, iclass 6, count 0 2006.201.11:26:56.94#ibcon#read 5, iclass 6, count 0 2006.201.11:26:56.94#ibcon#about to read 6, iclass 6, count 0 2006.201.11:26:56.94#ibcon#read 6, iclass 6, count 0 2006.201.11:26:56.94#ibcon#end of sib2, iclass 6, count 0 2006.201.11:26:56.94#ibcon#*mode == 0, iclass 6, count 0 2006.201.11:26:56.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.11:26:56.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:26:56.94#ibcon#*before write, iclass 6, count 0 2006.201.11:26:56.94#ibcon#enter sib2, iclass 6, count 0 2006.201.11:26:56.94#ibcon#flushed, iclass 6, count 0 2006.201.11:26:56.94#ibcon#about to write, iclass 6, count 0 2006.201.11:26:56.94#ibcon#wrote, iclass 6, count 0 2006.201.11:26:56.94#ibcon#about to read 3, iclass 6, count 0 2006.201.11:26:56.98#ibcon#read 3, iclass 6, count 0 2006.201.11:26:56.98#ibcon#about to read 4, iclass 6, count 0 2006.201.11:26:56.98#ibcon#read 4, iclass 6, count 0 2006.201.11:26:56.98#ibcon#about to read 5, iclass 6, count 0 2006.201.11:26:56.98#ibcon#read 5, iclass 6, count 0 2006.201.11:26:56.98#ibcon#about to read 6, iclass 6, count 0 2006.201.11:26:56.98#ibcon#read 6, iclass 6, count 0 2006.201.11:26:56.98#ibcon#end of sib2, iclass 6, count 0 2006.201.11:26:56.98#ibcon#*after write, iclass 6, count 0 2006.201.11:26:56.98#ibcon#*before return 0, iclass 6, count 0 2006.201.11:26:56.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:26:56.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:26:56.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.11:26:56.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.11:26:56.98$vck44/va=7,5 2006.201.11:26:56.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.11:26:56.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.11:26:56.98#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:56.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:26:57.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:26:57.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:26:57.04#ibcon#enter wrdev, iclass 10, count 2 2006.201.11:26:57.04#ibcon#first serial, iclass 10, count 2 2006.201.11:26:57.04#ibcon#enter sib2, iclass 10, count 2 2006.201.11:26:57.04#ibcon#flushed, iclass 10, count 2 2006.201.11:26:57.04#ibcon#about to write, iclass 10, count 2 2006.201.11:26:57.04#ibcon#wrote, iclass 10, count 2 2006.201.11:26:57.04#ibcon#about to read 3, iclass 10, count 2 2006.201.11:26:57.06#ibcon#read 3, iclass 10, count 2 2006.201.11:26:57.06#ibcon#about to read 4, iclass 10, count 2 2006.201.11:26:57.06#ibcon#read 4, iclass 10, count 2 2006.201.11:26:57.06#ibcon#about to read 5, iclass 10, count 2 2006.201.11:26:57.06#ibcon#read 5, iclass 10, count 2 2006.201.11:26:57.06#ibcon#about to read 6, iclass 10, count 2 2006.201.11:26:57.06#ibcon#read 6, iclass 10, count 2 2006.201.11:26:57.06#ibcon#end of sib2, iclass 10, count 2 2006.201.11:26:57.06#ibcon#*mode == 0, iclass 10, count 2 2006.201.11:26:57.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.11:26:57.06#ibcon#[25=AT07-05\r\n] 2006.201.11:26:57.06#ibcon#*before write, iclass 10, count 2 2006.201.11:26:57.06#ibcon#enter sib2, iclass 10, count 2 2006.201.11:26:57.06#ibcon#flushed, iclass 10, count 2 2006.201.11:26:57.06#ibcon#about to write, iclass 10, count 2 2006.201.11:26:57.06#ibcon#wrote, iclass 10, count 2 2006.201.11:26:57.06#ibcon#about to read 3, iclass 10, count 2 2006.201.11:26:57.09#ibcon#read 3, iclass 10, count 2 2006.201.11:26:57.09#ibcon#about to read 4, iclass 10, count 2 2006.201.11:26:57.09#ibcon#read 4, iclass 10, count 2 2006.201.11:26:57.09#ibcon#about to read 5, iclass 10, count 2 2006.201.11:26:57.09#ibcon#read 5, iclass 10, count 2 2006.201.11:26:57.09#ibcon#about to read 6, iclass 10, count 2 2006.201.11:26:57.09#ibcon#read 6, iclass 10, count 2 2006.201.11:26:57.09#ibcon#end of sib2, iclass 10, count 2 2006.201.11:26:57.09#ibcon#*after write, iclass 10, count 2 2006.201.11:26:57.09#ibcon#*before return 0, iclass 10, count 2 2006.201.11:26:57.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:26:57.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:26:57.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.11:26:57.09#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:57.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:26:57.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:26:57.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:26:57.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.11:26:57.21#ibcon#first serial, iclass 10, count 0 2006.201.11:26:57.21#ibcon#enter sib2, iclass 10, count 0 2006.201.11:26:57.21#ibcon#flushed, iclass 10, count 0 2006.201.11:26:57.21#ibcon#about to write, iclass 10, count 0 2006.201.11:26:57.21#ibcon#wrote, iclass 10, count 0 2006.201.11:26:57.21#ibcon#about to read 3, iclass 10, count 0 2006.201.11:26:57.23#ibcon#read 3, iclass 10, count 0 2006.201.11:26:57.23#ibcon#about to read 4, iclass 10, count 0 2006.201.11:26:57.23#ibcon#read 4, iclass 10, count 0 2006.201.11:26:57.23#ibcon#about to read 5, iclass 10, count 0 2006.201.11:26:57.23#ibcon#read 5, iclass 10, count 0 2006.201.11:26:57.23#ibcon#about to read 6, iclass 10, count 0 2006.201.11:26:57.23#ibcon#read 6, iclass 10, count 0 2006.201.11:26:57.23#ibcon#end of sib2, iclass 10, count 0 2006.201.11:26:57.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.11:26:57.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.11:26:57.23#ibcon#[25=USB\r\n] 2006.201.11:26:57.23#ibcon#*before write, iclass 10, count 0 2006.201.11:26:57.23#ibcon#enter sib2, iclass 10, count 0 2006.201.11:26:57.23#ibcon#flushed, iclass 10, count 0 2006.201.11:26:57.23#ibcon#about to write, iclass 10, count 0 2006.201.11:26:57.23#ibcon#wrote, iclass 10, count 0 2006.201.11:26:57.23#ibcon#about to read 3, iclass 10, count 0 2006.201.11:26:57.26#ibcon#read 3, iclass 10, count 0 2006.201.11:26:57.26#ibcon#about to read 4, iclass 10, count 0 2006.201.11:26:57.26#ibcon#read 4, iclass 10, count 0 2006.201.11:26:57.26#ibcon#about to read 5, iclass 10, count 0 2006.201.11:26:57.26#ibcon#read 5, iclass 10, count 0 2006.201.11:26:57.26#ibcon#about to read 6, iclass 10, count 0 2006.201.11:26:57.26#ibcon#read 6, iclass 10, count 0 2006.201.11:26:57.26#ibcon#end of sib2, iclass 10, count 0 2006.201.11:26:57.26#ibcon#*after write, iclass 10, count 0 2006.201.11:26:57.26#ibcon#*before return 0, iclass 10, count 0 2006.201.11:26:57.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:26:57.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:26:57.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.11:26:57.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.11:26:57.26$vck44/valo=8,884.99 2006.201.11:26:57.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.11:26:57.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.11:26:57.26#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:57.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:26:57.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:26:57.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:26:57.26#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:26:57.26#ibcon#first serial, iclass 12, count 0 2006.201.11:26:57.26#ibcon#enter sib2, iclass 12, count 0 2006.201.11:26:57.26#ibcon#flushed, iclass 12, count 0 2006.201.11:26:57.26#ibcon#about to write, iclass 12, count 0 2006.201.11:26:57.26#ibcon#wrote, iclass 12, count 0 2006.201.11:26:57.26#ibcon#about to read 3, iclass 12, count 0 2006.201.11:26:57.28#ibcon#read 3, iclass 12, count 0 2006.201.11:26:57.28#ibcon#about to read 4, iclass 12, count 0 2006.201.11:26:57.28#ibcon#read 4, iclass 12, count 0 2006.201.11:26:57.28#ibcon#about to read 5, iclass 12, count 0 2006.201.11:26:57.28#ibcon#read 5, iclass 12, count 0 2006.201.11:26:57.28#ibcon#about to read 6, iclass 12, count 0 2006.201.11:26:57.28#ibcon#read 6, iclass 12, count 0 2006.201.11:26:57.28#ibcon#end of sib2, iclass 12, count 0 2006.201.11:26:57.28#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:26:57.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:26:57.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:26:57.28#ibcon#*before write, iclass 12, count 0 2006.201.11:26:57.28#ibcon#enter sib2, iclass 12, count 0 2006.201.11:26:57.28#ibcon#flushed, iclass 12, count 0 2006.201.11:26:57.28#ibcon#about to write, iclass 12, count 0 2006.201.11:26:57.28#ibcon#wrote, iclass 12, count 0 2006.201.11:26:57.28#ibcon#about to read 3, iclass 12, count 0 2006.201.11:26:57.32#ibcon#read 3, iclass 12, count 0 2006.201.11:26:57.32#ibcon#about to read 4, iclass 12, count 0 2006.201.11:26:57.32#ibcon#read 4, iclass 12, count 0 2006.201.11:26:57.32#ibcon#about to read 5, iclass 12, count 0 2006.201.11:26:57.32#ibcon#read 5, iclass 12, count 0 2006.201.11:26:57.32#ibcon#about to read 6, iclass 12, count 0 2006.201.11:26:57.32#ibcon#read 6, iclass 12, count 0 2006.201.11:26:57.32#ibcon#end of sib2, iclass 12, count 0 2006.201.11:26:57.32#ibcon#*after write, iclass 12, count 0 2006.201.11:26:57.32#ibcon#*before return 0, iclass 12, count 0 2006.201.11:26:57.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:26:57.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:26:57.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:26:57.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:26:57.32$vck44/va=8,4 2006.201.11:26:57.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.11:26:57.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.11:26:57.32#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:57.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:26:57.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:26:57.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:26:57.38#ibcon#enter wrdev, iclass 14, count 2 2006.201.11:26:57.38#ibcon#first serial, iclass 14, count 2 2006.201.11:26:57.38#ibcon#enter sib2, iclass 14, count 2 2006.201.11:26:57.38#ibcon#flushed, iclass 14, count 2 2006.201.11:26:57.38#ibcon#about to write, iclass 14, count 2 2006.201.11:26:57.38#ibcon#wrote, iclass 14, count 2 2006.201.11:26:57.38#ibcon#about to read 3, iclass 14, count 2 2006.201.11:26:57.40#ibcon#read 3, iclass 14, count 2 2006.201.11:26:57.40#ibcon#about to read 4, iclass 14, count 2 2006.201.11:26:57.40#ibcon#read 4, iclass 14, count 2 2006.201.11:26:57.40#ibcon#about to read 5, iclass 14, count 2 2006.201.11:26:57.40#ibcon#read 5, iclass 14, count 2 2006.201.11:26:57.40#ibcon#about to read 6, iclass 14, count 2 2006.201.11:26:57.40#ibcon#read 6, iclass 14, count 2 2006.201.11:26:57.40#ibcon#end of sib2, iclass 14, count 2 2006.201.11:26:57.40#ibcon#*mode == 0, iclass 14, count 2 2006.201.11:26:57.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.11:26:57.40#ibcon#[25=AT08-04\r\n] 2006.201.11:26:57.40#ibcon#*before write, iclass 14, count 2 2006.201.11:26:57.40#ibcon#enter sib2, iclass 14, count 2 2006.201.11:26:57.40#ibcon#flushed, iclass 14, count 2 2006.201.11:26:57.40#ibcon#about to write, iclass 14, count 2 2006.201.11:26:57.40#ibcon#wrote, iclass 14, count 2 2006.201.11:26:57.40#ibcon#about to read 3, iclass 14, count 2 2006.201.11:26:57.43#ibcon#read 3, iclass 14, count 2 2006.201.11:26:57.43#ibcon#about to read 4, iclass 14, count 2 2006.201.11:26:57.43#ibcon#read 4, iclass 14, count 2 2006.201.11:26:57.43#ibcon#about to read 5, iclass 14, count 2 2006.201.11:26:57.43#ibcon#read 5, iclass 14, count 2 2006.201.11:26:57.43#ibcon#about to read 6, iclass 14, count 2 2006.201.11:26:57.43#ibcon#read 6, iclass 14, count 2 2006.201.11:26:57.43#ibcon#end of sib2, iclass 14, count 2 2006.201.11:26:57.43#ibcon#*after write, iclass 14, count 2 2006.201.11:26:57.43#ibcon#*before return 0, iclass 14, count 2 2006.201.11:26:57.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:26:57.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:26:57.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.11:26:57.43#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:57.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:26:57.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:26:57.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:26:57.55#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:26:57.55#ibcon#first serial, iclass 14, count 0 2006.201.11:26:57.55#ibcon#enter sib2, iclass 14, count 0 2006.201.11:26:57.55#ibcon#flushed, iclass 14, count 0 2006.201.11:26:57.55#ibcon#about to write, iclass 14, count 0 2006.201.11:26:57.55#ibcon#wrote, iclass 14, count 0 2006.201.11:26:57.55#ibcon#about to read 3, iclass 14, count 0 2006.201.11:26:57.57#ibcon#read 3, iclass 14, count 0 2006.201.11:26:57.57#ibcon#about to read 4, iclass 14, count 0 2006.201.11:26:57.57#ibcon#read 4, iclass 14, count 0 2006.201.11:26:57.57#ibcon#about to read 5, iclass 14, count 0 2006.201.11:26:57.57#ibcon#read 5, iclass 14, count 0 2006.201.11:26:57.57#ibcon#about to read 6, iclass 14, count 0 2006.201.11:26:57.57#ibcon#read 6, iclass 14, count 0 2006.201.11:26:57.57#ibcon#end of sib2, iclass 14, count 0 2006.201.11:26:57.57#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:26:57.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:26:57.57#ibcon#[25=USB\r\n] 2006.201.11:26:57.57#ibcon#*before write, iclass 14, count 0 2006.201.11:26:57.57#ibcon#enter sib2, iclass 14, count 0 2006.201.11:26:57.57#ibcon#flushed, iclass 14, count 0 2006.201.11:26:57.57#ibcon#about to write, iclass 14, count 0 2006.201.11:26:57.57#ibcon#wrote, iclass 14, count 0 2006.201.11:26:57.57#ibcon#about to read 3, iclass 14, count 0 2006.201.11:26:57.60#ibcon#read 3, iclass 14, count 0 2006.201.11:26:57.60#ibcon#about to read 4, iclass 14, count 0 2006.201.11:26:57.60#ibcon#read 4, iclass 14, count 0 2006.201.11:26:57.60#ibcon#about to read 5, iclass 14, count 0 2006.201.11:26:57.60#ibcon#read 5, iclass 14, count 0 2006.201.11:26:57.60#ibcon#about to read 6, iclass 14, count 0 2006.201.11:26:57.60#ibcon#read 6, iclass 14, count 0 2006.201.11:26:57.60#ibcon#end of sib2, iclass 14, count 0 2006.201.11:26:57.60#ibcon#*after write, iclass 14, count 0 2006.201.11:26:57.60#ibcon#*before return 0, iclass 14, count 0 2006.201.11:26:57.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:26:57.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:26:57.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:26:57.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:26:57.60$vck44/vblo=1,629.99 2006.201.11:26:57.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.11:26:57.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.11:26:57.60#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:57.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:26:57.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:26:57.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:26:57.60#ibcon#enter wrdev, iclass 16, count 0 2006.201.11:26:57.60#ibcon#first serial, iclass 16, count 0 2006.201.11:26:57.60#ibcon#enter sib2, iclass 16, count 0 2006.201.11:26:57.60#ibcon#flushed, iclass 16, count 0 2006.201.11:26:57.60#ibcon#about to write, iclass 16, count 0 2006.201.11:26:57.60#ibcon#wrote, iclass 16, count 0 2006.201.11:26:57.60#ibcon#about to read 3, iclass 16, count 0 2006.201.11:26:57.62#ibcon#read 3, iclass 16, count 0 2006.201.11:26:57.62#ibcon#about to read 4, iclass 16, count 0 2006.201.11:26:57.62#ibcon#read 4, iclass 16, count 0 2006.201.11:26:57.62#ibcon#about to read 5, iclass 16, count 0 2006.201.11:26:57.62#ibcon#read 5, iclass 16, count 0 2006.201.11:26:57.62#ibcon#about to read 6, iclass 16, count 0 2006.201.11:26:57.62#ibcon#read 6, iclass 16, count 0 2006.201.11:26:57.62#ibcon#end of sib2, iclass 16, count 0 2006.201.11:26:57.62#ibcon#*mode == 0, iclass 16, count 0 2006.201.11:26:57.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.11:26:57.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:26:57.62#ibcon#*before write, iclass 16, count 0 2006.201.11:26:57.62#ibcon#enter sib2, iclass 16, count 0 2006.201.11:26:57.62#ibcon#flushed, iclass 16, count 0 2006.201.11:26:57.62#ibcon#about to write, iclass 16, count 0 2006.201.11:26:57.62#ibcon#wrote, iclass 16, count 0 2006.201.11:26:57.62#ibcon#about to read 3, iclass 16, count 0 2006.201.11:26:57.67#ibcon#read 3, iclass 16, count 0 2006.201.11:26:57.67#ibcon#about to read 4, iclass 16, count 0 2006.201.11:26:57.67#ibcon#read 4, iclass 16, count 0 2006.201.11:26:57.67#ibcon#about to read 5, iclass 16, count 0 2006.201.11:26:57.67#ibcon#read 5, iclass 16, count 0 2006.201.11:26:57.67#ibcon#about to read 6, iclass 16, count 0 2006.201.11:26:57.67#ibcon#read 6, iclass 16, count 0 2006.201.11:26:57.67#ibcon#end of sib2, iclass 16, count 0 2006.201.11:26:57.67#ibcon#*after write, iclass 16, count 0 2006.201.11:26:57.67#ibcon#*before return 0, iclass 16, count 0 2006.201.11:26:57.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:26:57.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:26:57.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.11:26:57.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.11:26:57.67$vck44/vb=1,4 2006.201.11:26:57.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.11:26:57.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.11:26:57.67#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:57.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:26:57.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:26:57.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:26:57.67#ibcon#enter wrdev, iclass 18, count 2 2006.201.11:26:57.67#ibcon#first serial, iclass 18, count 2 2006.201.11:26:57.67#ibcon#enter sib2, iclass 18, count 2 2006.201.11:26:57.67#ibcon#flushed, iclass 18, count 2 2006.201.11:26:57.67#ibcon#about to write, iclass 18, count 2 2006.201.11:26:57.67#ibcon#wrote, iclass 18, count 2 2006.201.11:26:57.67#ibcon#about to read 3, iclass 18, count 2 2006.201.11:26:57.69#ibcon#read 3, iclass 18, count 2 2006.201.11:26:57.69#ibcon#about to read 4, iclass 18, count 2 2006.201.11:26:57.69#ibcon#read 4, iclass 18, count 2 2006.201.11:26:57.69#ibcon#about to read 5, iclass 18, count 2 2006.201.11:26:57.69#ibcon#read 5, iclass 18, count 2 2006.201.11:26:57.69#ibcon#about to read 6, iclass 18, count 2 2006.201.11:26:57.69#ibcon#read 6, iclass 18, count 2 2006.201.11:26:57.69#ibcon#end of sib2, iclass 18, count 2 2006.201.11:26:57.69#ibcon#*mode == 0, iclass 18, count 2 2006.201.11:26:57.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.11:26:57.69#ibcon#[27=AT01-04\r\n] 2006.201.11:26:57.69#ibcon#*before write, iclass 18, count 2 2006.201.11:26:57.69#ibcon#enter sib2, iclass 18, count 2 2006.201.11:26:57.69#ibcon#flushed, iclass 18, count 2 2006.201.11:26:57.69#ibcon#about to write, iclass 18, count 2 2006.201.11:26:57.69#ibcon#wrote, iclass 18, count 2 2006.201.11:26:57.69#ibcon#about to read 3, iclass 18, count 2 2006.201.11:26:57.72#ibcon#read 3, iclass 18, count 2 2006.201.11:26:57.72#ibcon#about to read 4, iclass 18, count 2 2006.201.11:26:57.72#ibcon#read 4, iclass 18, count 2 2006.201.11:26:57.72#ibcon#about to read 5, iclass 18, count 2 2006.201.11:26:57.72#ibcon#read 5, iclass 18, count 2 2006.201.11:26:57.72#ibcon#about to read 6, iclass 18, count 2 2006.201.11:26:57.72#ibcon#read 6, iclass 18, count 2 2006.201.11:26:57.72#ibcon#end of sib2, iclass 18, count 2 2006.201.11:26:57.72#ibcon#*after write, iclass 18, count 2 2006.201.11:26:57.72#ibcon#*before return 0, iclass 18, count 2 2006.201.11:26:57.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:26:57.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:26:57.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.11:26:57.72#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:57.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:26:57.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:26:57.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:26:57.84#ibcon#enter wrdev, iclass 18, count 0 2006.201.11:26:57.84#ibcon#first serial, iclass 18, count 0 2006.201.11:26:57.84#ibcon#enter sib2, iclass 18, count 0 2006.201.11:26:57.84#ibcon#flushed, iclass 18, count 0 2006.201.11:26:57.84#ibcon#about to write, iclass 18, count 0 2006.201.11:26:57.84#ibcon#wrote, iclass 18, count 0 2006.201.11:26:57.84#ibcon#about to read 3, iclass 18, count 0 2006.201.11:26:57.86#ibcon#read 3, iclass 18, count 0 2006.201.11:26:57.86#ibcon#about to read 4, iclass 18, count 0 2006.201.11:26:57.86#ibcon#read 4, iclass 18, count 0 2006.201.11:26:57.86#ibcon#about to read 5, iclass 18, count 0 2006.201.11:26:57.86#ibcon#read 5, iclass 18, count 0 2006.201.11:26:57.86#ibcon#about to read 6, iclass 18, count 0 2006.201.11:26:57.86#ibcon#read 6, iclass 18, count 0 2006.201.11:26:57.86#ibcon#end of sib2, iclass 18, count 0 2006.201.11:26:57.86#ibcon#*mode == 0, iclass 18, count 0 2006.201.11:26:57.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.11:26:57.86#ibcon#[27=USB\r\n] 2006.201.11:26:57.86#ibcon#*before write, iclass 18, count 0 2006.201.11:26:57.86#ibcon#enter sib2, iclass 18, count 0 2006.201.11:26:57.86#ibcon#flushed, iclass 18, count 0 2006.201.11:26:57.86#ibcon#about to write, iclass 18, count 0 2006.201.11:26:57.86#ibcon#wrote, iclass 18, count 0 2006.201.11:26:57.86#ibcon#about to read 3, iclass 18, count 0 2006.201.11:26:57.89#ibcon#read 3, iclass 18, count 0 2006.201.11:26:57.89#ibcon#about to read 4, iclass 18, count 0 2006.201.11:26:57.89#ibcon#read 4, iclass 18, count 0 2006.201.11:26:57.89#ibcon#about to read 5, iclass 18, count 0 2006.201.11:26:57.89#ibcon#read 5, iclass 18, count 0 2006.201.11:26:57.89#ibcon#about to read 6, iclass 18, count 0 2006.201.11:26:57.89#ibcon#read 6, iclass 18, count 0 2006.201.11:26:57.89#ibcon#end of sib2, iclass 18, count 0 2006.201.11:26:57.89#ibcon#*after write, iclass 18, count 0 2006.201.11:26:57.89#ibcon#*before return 0, iclass 18, count 0 2006.201.11:26:57.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:26:57.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:26:57.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.11:26:57.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.11:26:57.89$vck44/vblo=2,634.99 2006.201.11:26:57.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.11:26:57.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.11:26:57.89#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:57.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:57.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:57.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:57.89#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:26:57.89#ibcon#first serial, iclass 20, count 0 2006.201.11:26:57.89#ibcon#enter sib2, iclass 20, count 0 2006.201.11:26:57.89#ibcon#flushed, iclass 20, count 0 2006.201.11:26:57.89#ibcon#about to write, iclass 20, count 0 2006.201.11:26:57.89#ibcon#wrote, iclass 20, count 0 2006.201.11:26:57.89#ibcon#about to read 3, iclass 20, count 0 2006.201.11:26:57.91#ibcon#read 3, iclass 20, count 0 2006.201.11:26:57.91#ibcon#about to read 4, iclass 20, count 0 2006.201.11:26:57.91#ibcon#read 4, iclass 20, count 0 2006.201.11:26:57.91#ibcon#about to read 5, iclass 20, count 0 2006.201.11:26:57.91#ibcon#read 5, iclass 20, count 0 2006.201.11:26:57.91#ibcon#about to read 6, iclass 20, count 0 2006.201.11:26:57.91#ibcon#read 6, iclass 20, count 0 2006.201.11:26:57.91#ibcon#end of sib2, iclass 20, count 0 2006.201.11:26:57.91#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:26:57.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:26:57.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:26:57.91#ibcon#*before write, iclass 20, count 0 2006.201.11:26:57.91#ibcon#enter sib2, iclass 20, count 0 2006.201.11:26:57.91#ibcon#flushed, iclass 20, count 0 2006.201.11:26:57.91#ibcon#about to write, iclass 20, count 0 2006.201.11:26:57.91#ibcon#wrote, iclass 20, count 0 2006.201.11:26:57.91#ibcon#about to read 3, iclass 20, count 0 2006.201.11:26:57.95#ibcon#read 3, iclass 20, count 0 2006.201.11:26:57.95#ibcon#about to read 4, iclass 20, count 0 2006.201.11:26:57.95#ibcon#read 4, iclass 20, count 0 2006.201.11:26:57.95#ibcon#about to read 5, iclass 20, count 0 2006.201.11:26:57.95#ibcon#read 5, iclass 20, count 0 2006.201.11:26:57.95#ibcon#about to read 6, iclass 20, count 0 2006.201.11:26:57.95#ibcon#read 6, iclass 20, count 0 2006.201.11:26:57.95#ibcon#end of sib2, iclass 20, count 0 2006.201.11:26:57.95#ibcon#*after write, iclass 20, count 0 2006.201.11:26:57.95#ibcon#*before return 0, iclass 20, count 0 2006.201.11:26:57.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:57.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:26:57.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:26:57.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:26:57.95$vck44/vb=2,5 2006.201.11:26:57.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.11:26:57.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.11:26:57.95#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:57.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:58.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:58.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:58.01#ibcon#enter wrdev, iclass 22, count 2 2006.201.11:26:58.01#ibcon#first serial, iclass 22, count 2 2006.201.11:26:58.01#ibcon#enter sib2, iclass 22, count 2 2006.201.11:26:58.01#ibcon#flushed, iclass 22, count 2 2006.201.11:26:58.01#ibcon#about to write, iclass 22, count 2 2006.201.11:26:58.01#ibcon#wrote, iclass 22, count 2 2006.201.11:26:58.01#ibcon#about to read 3, iclass 22, count 2 2006.201.11:26:58.03#ibcon#read 3, iclass 22, count 2 2006.201.11:26:58.03#ibcon#about to read 4, iclass 22, count 2 2006.201.11:26:58.03#ibcon#read 4, iclass 22, count 2 2006.201.11:26:58.03#ibcon#about to read 5, iclass 22, count 2 2006.201.11:26:58.03#ibcon#read 5, iclass 22, count 2 2006.201.11:26:58.03#ibcon#about to read 6, iclass 22, count 2 2006.201.11:26:58.03#ibcon#read 6, iclass 22, count 2 2006.201.11:26:58.03#ibcon#end of sib2, iclass 22, count 2 2006.201.11:26:58.03#ibcon#*mode == 0, iclass 22, count 2 2006.201.11:26:58.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.11:26:58.03#ibcon#[27=AT02-05\r\n] 2006.201.11:26:58.03#ibcon#*before write, iclass 22, count 2 2006.201.11:26:58.03#ibcon#enter sib2, iclass 22, count 2 2006.201.11:26:58.03#ibcon#flushed, iclass 22, count 2 2006.201.11:26:58.03#ibcon#about to write, iclass 22, count 2 2006.201.11:26:58.03#ibcon#wrote, iclass 22, count 2 2006.201.11:26:58.03#ibcon#about to read 3, iclass 22, count 2 2006.201.11:26:58.06#ibcon#read 3, iclass 22, count 2 2006.201.11:26:58.06#ibcon#about to read 4, iclass 22, count 2 2006.201.11:26:58.06#ibcon#read 4, iclass 22, count 2 2006.201.11:26:58.06#ibcon#about to read 5, iclass 22, count 2 2006.201.11:26:58.06#ibcon#read 5, iclass 22, count 2 2006.201.11:26:58.06#ibcon#about to read 6, iclass 22, count 2 2006.201.11:26:58.06#ibcon#read 6, iclass 22, count 2 2006.201.11:26:58.06#ibcon#end of sib2, iclass 22, count 2 2006.201.11:26:58.06#ibcon#*after write, iclass 22, count 2 2006.201.11:26:58.06#ibcon#*before return 0, iclass 22, count 2 2006.201.11:26:58.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:58.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:26:58.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.11:26:58.06#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:58.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:58.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:58.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:58.18#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:26:58.18#ibcon#first serial, iclass 22, count 0 2006.201.11:26:58.18#ibcon#enter sib2, iclass 22, count 0 2006.201.11:26:58.18#ibcon#flushed, iclass 22, count 0 2006.201.11:26:58.18#ibcon#about to write, iclass 22, count 0 2006.201.11:26:58.18#ibcon#wrote, iclass 22, count 0 2006.201.11:26:58.18#ibcon#about to read 3, iclass 22, count 0 2006.201.11:26:58.21#ibcon#read 3, iclass 22, count 0 2006.201.11:26:58.21#ibcon#about to read 4, iclass 22, count 0 2006.201.11:26:58.21#ibcon#read 4, iclass 22, count 0 2006.201.11:26:58.21#ibcon#about to read 5, iclass 22, count 0 2006.201.11:26:58.21#ibcon#read 5, iclass 22, count 0 2006.201.11:26:58.21#ibcon#about to read 6, iclass 22, count 0 2006.201.11:26:58.21#ibcon#read 6, iclass 22, count 0 2006.201.11:26:58.21#ibcon#end of sib2, iclass 22, count 0 2006.201.11:26:58.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:26:58.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:26:58.21#ibcon#[27=USB\r\n] 2006.201.11:26:58.21#ibcon#*before write, iclass 22, count 0 2006.201.11:26:58.21#ibcon#enter sib2, iclass 22, count 0 2006.201.11:26:58.21#ibcon#flushed, iclass 22, count 0 2006.201.11:26:58.21#ibcon#about to write, iclass 22, count 0 2006.201.11:26:58.21#ibcon#wrote, iclass 22, count 0 2006.201.11:26:58.21#ibcon#about to read 3, iclass 22, count 0 2006.201.11:26:58.24#ibcon#read 3, iclass 22, count 0 2006.201.11:26:58.24#ibcon#about to read 4, iclass 22, count 0 2006.201.11:26:58.24#ibcon#read 4, iclass 22, count 0 2006.201.11:26:58.24#ibcon#about to read 5, iclass 22, count 0 2006.201.11:26:58.24#ibcon#read 5, iclass 22, count 0 2006.201.11:26:58.24#ibcon#about to read 6, iclass 22, count 0 2006.201.11:26:58.24#ibcon#read 6, iclass 22, count 0 2006.201.11:26:58.24#ibcon#end of sib2, iclass 22, count 0 2006.201.11:26:58.24#ibcon#*after write, iclass 22, count 0 2006.201.11:26:58.24#ibcon#*before return 0, iclass 22, count 0 2006.201.11:26:58.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:58.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:26:58.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:26:58.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:26:58.24$vck44/vblo=3,649.99 2006.201.11:26:58.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.11:26:58.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.11:26:58.24#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:58.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:58.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:58.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:58.24#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:26:58.24#ibcon#first serial, iclass 24, count 0 2006.201.11:26:58.24#ibcon#enter sib2, iclass 24, count 0 2006.201.11:26:58.24#ibcon#flushed, iclass 24, count 0 2006.201.11:26:58.24#ibcon#about to write, iclass 24, count 0 2006.201.11:26:58.24#ibcon#wrote, iclass 24, count 0 2006.201.11:26:58.24#ibcon#about to read 3, iclass 24, count 0 2006.201.11:26:58.26#ibcon#read 3, iclass 24, count 0 2006.201.11:26:58.26#ibcon#about to read 4, iclass 24, count 0 2006.201.11:26:58.26#ibcon#read 4, iclass 24, count 0 2006.201.11:26:58.26#ibcon#about to read 5, iclass 24, count 0 2006.201.11:26:58.26#ibcon#read 5, iclass 24, count 0 2006.201.11:26:58.26#ibcon#about to read 6, iclass 24, count 0 2006.201.11:26:58.26#ibcon#read 6, iclass 24, count 0 2006.201.11:26:58.26#ibcon#end of sib2, iclass 24, count 0 2006.201.11:26:58.26#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:26:58.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:26:58.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:26:58.26#ibcon#*before write, iclass 24, count 0 2006.201.11:26:58.26#ibcon#enter sib2, iclass 24, count 0 2006.201.11:26:58.26#ibcon#flushed, iclass 24, count 0 2006.201.11:26:58.26#ibcon#about to write, iclass 24, count 0 2006.201.11:26:58.26#ibcon#wrote, iclass 24, count 0 2006.201.11:26:58.26#ibcon#about to read 3, iclass 24, count 0 2006.201.11:26:58.30#ibcon#read 3, iclass 24, count 0 2006.201.11:26:58.30#ibcon#about to read 4, iclass 24, count 0 2006.201.11:26:58.30#ibcon#read 4, iclass 24, count 0 2006.201.11:26:58.30#ibcon#about to read 5, iclass 24, count 0 2006.201.11:26:58.30#ibcon#read 5, iclass 24, count 0 2006.201.11:26:58.30#ibcon#about to read 6, iclass 24, count 0 2006.201.11:26:58.30#ibcon#read 6, iclass 24, count 0 2006.201.11:26:58.30#ibcon#end of sib2, iclass 24, count 0 2006.201.11:26:58.30#ibcon#*after write, iclass 24, count 0 2006.201.11:26:58.30#ibcon#*before return 0, iclass 24, count 0 2006.201.11:26:58.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:58.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:26:58.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:26:58.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:26:58.30$vck44/vb=3,4 2006.201.11:26:58.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.11:26:58.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.11:26:58.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:58.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:58.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:58.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:58.36#ibcon#enter wrdev, iclass 26, count 2 2006.201.11:26:58.36#ibcon#first serial, iclass 26, count 2 2006.201.11:26:58.36#ibcon#enter sib2, iclass 26, count 2 2006.201.11:26:58.36#ibcon#flushed, iclass 26, count 2 2006.201.11:26:58.36#ibcon#about to write, iclass 26, count 2 2006.201.11:26:58.36#ibcon#wrote, iclass 26, count 2 2006.201.11:26:58.36#ibcon#about to read 3, iclass 26, count 2 2006.201.11:26:58.38#ibcon#read 3, iclass 26, count 2 2006.201.11:26:58.38#ibcon#about to read 4, iclass 26, count 2 2006.201.11:26:58.38#ibcon#read 4, iclass 26, count 2 2006.201.11:26:58.38#ibcon#about to read 5, iclass 26, count 2 2006.201.11:26:58.38#ibcon#read 5, iclass 26, count 2 2006.201.11:26:58.38#ibcon#about to read 6, iclass 26, count 2 2006.201.11:26:58.38#ibcon#read 6, iclass 26, count 2 2006.201.11:26:58.38#ibcon#end of sib2, iclass 26, count 2 2006.201.11:26:58.38#ibcon#*mode == 0, iclass 26, count 2 2006.201.11:26:58.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.11:26:58.38#ibcon#[27=AT03-04\r\n] 2006.201.11:26:58.38#ibcon#*before write, iclass 26, count 2 2006.201.11:26:58.38#ibcon#enter sib2, iclass 26, count 2 2006.201.11:26:58.38#ibcon#flushed, iclass 26, count 2 2006.201.11:26:58.38#ibcon#about to write, iclass 26, count 2 2006.201.11:26:58.38#ibcon#wrote, iclass 26, count 2 2006.201.11:26:58.38#ibcon#about to read 3, iclass 26, count 2 2006.201.11:26:58.41#ibcon#read 3, iclass 26, count 2 2006.201.11:26:58.41#ibcon#about to read 4, iclass 26, count 2 2006.201.11:26:58.41#ibcon#read 4, iclass 26, count 2 2006.201.11:26:58.41#ibcon#about to read 5, iclass 26, count 2 2006.201.11:26:58.41#ibcon#read 5, iclass 26, count 2 2006.201.11:26:58.41#ibcon#about to read 6, iclass 26, count 2 2006.201.11:26:58.41#ibcon#read 6, iclass 26, count 2 2006.201.11:26:58.41#ibcon#end of sib2, iclass 26, count 2 2006.201.11:26:58.41#ibcon#*after write, iclass 26, count 2 2006.201.11:26:58.41#ibcon#*before return 0, iclass 26, count 2 2006.201.11:26:58.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:58.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:26:58.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.11:26:58.41#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:58.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:58.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:58.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:58.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:26:58.53#ibcon#first serial, iclass 26, count 0 2006.201.11:26:58.53#ibcon#enter sib2, iclass 26, count 0 2006.201.11:26:58.53#ibcon#flushed, iclass 26, count 0 2006.201.11:26:58.53#ibcon#about to write, iclass 26, count 0 2006.201.11:26:58.53#ibcon#wrote, iclass 26, count 0 2006.201.11:26:58.53#ibcon#about to read 3, iclass 26, count 0 2006.201.11:26:58.55#ibcon#read 3, iclass 26, count 0 2006.201.11:26:58.55#ibcon#about to read 4, iclass 26, count 0 2006.201.11:26:58.55#ibcon#read 4, iclass 26, count 0 2006.201.11:26:58.55#ibcon#about to read 5, iclass 26, count 0 2006.201.11:26:58.55#ibcon#read 5, iclass 26, count 0 2006.201.11:26:58.55#ibcon#about to read 6, iclass 26, count 0 2006.201.11:26:58.55#ibcon#read 6, iclass 26, count 0 2006.201.11:26:58.55#ibcon#end of sib2, iclass 26, count 0 2006.201.11:26:58.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:26:58.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:26:58.55#ibcon#[27=USB\r\n] 2006.201.11:26:58.55#ibcon#*before write, iclass 26, count 0 2006.201.11:26:58.55#ibcon#enter sib2, iclass 26, count 0 2006.201.11:26:58.55#ibcon#flushed, iclass 26, count 0 2006.201.11:26:58.55#ibcon#about to write, iclass 26, count 0 2006.201.11:26:58.55#ibcon#wrote, iclass 26, count 0 2006.201.11:26:58.55#ibcon#about to read 3, iclass 26, count 0 2006.201.11:26:58.58#ibcon#read 3, iclass 26, count 0 2006.201.11:26:58.58#ibcon#about to read 4, iclass 26, count 0 2006.201.11:26:58.58#ibcon#read 4, iclass 26, count 0 2006.201.11:26:58.58#ibcon#about to read 5, iclass 26, count 0 2006.201.11:26:58.58#ibcon#read 5, iclass 26, count 0 2006.201.11:26:58.58#ibcon#about to read 6, iclass 26, count 0 2006.201.11:26:58.58#ibcon#read 6, iclass 26, count 0 2006.201.11:26:58.58#ibcon#end of sib2, iclass 26, count 0 2006.201.11:26:58.58#ibcon#*after write, iclass 26, count 0 2006.201.11:26:58.58#ibcon#*before return 0, iclass 26, count 0 2006.201.11:26:58.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:58.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:26:58.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:26:58.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:26:58.58$vck44/vblo=4,679.99 2006.201.11:26:58.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.11:26:58.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.11:26:58.58#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:58.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:58.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:58.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:58.58#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:26:58.58#ibcon#first serial, iclass 28, count 0 2006.201.11:26:58.58#ibcon#enter sib2, iclass 28, count 0 2006.201.11:26:58.58#ibcon#flushed, iclass 28, count 0 2006.201.11:26:58.58#ibcon#about to write, iclass 28, count 0 2006.201.11:26:58.58#ibcon#wrote, iclass 28, count 0 2006.201.11:26:58.58#ibcon#about to read 3, iclass 28, count 0 2006.201.11:26:58.60#ibcon#read 3, iclass 28, count 0 2006.201.11:26:58.60#ibcon#about to read 4, iclass 28, count 0 2006.201.11:26:58.60#ibcon#read 4, iclass 28, count 0 2006.201.11:26:58.60#ibcon#about to read 5, iclass 28, count 0 2006.201.11:26:58.60#ibcon#read 5, iclass 28, count 0 2006.201.11:26:58.60#ibcon#about to read 6, iclass 28, count 0 2006.201.11:26:58.60#ibcon#read 6, iclass 28, count 0 2006.201.11:26:58.60#ibcon#end of sib2, iclass 28, count 0 2006.201.11:26:58.60#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:26:58.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:26:58.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:26:58.60#ibcon#*before write, iclass 28, count 0 2006.201.11:26:58.60#ibcon#enter sib2, iclass 28, count 0 2006.201.11:26:58.60#ibcon#flushed, iclass 28, count 0 2006.201.11:26:58.60#ibcon#about to write, iclass 28, count 0 2006.201.11:26:58.60#ibcon#wrote, iclass 28, count 0 2006.201.11:26:58.60#ibcon#about to read 3, iclass 28, count 0 2006.201.11:26:58.64#ibcon#read 3, iclass 28, count 0 2006.201.11:26:58.64#ibcon#about to read 4, iclass 28, count 0 2006.201.11:26:58.64#ibcon#read 4, iclass 28, count 0 2006.201.11:26:58.64#ibcon#about to read 5, iclass 28, count 0 2006.201.11:26:58.64#ibcon#read 5, iclass 28, count 0 2006.201.11:26:58.64#ibcon#about to read 6, iclass 28, count 0 2006.201.11:26:58.64#ibcon#read 6, iclass 28, count 0 2006.201.11:26:58.64#ibcon#end of sib2, iclass 28, count 0 2006.201.11:26:58.64#ibcon#*after write, iclass 28, count 0 2006.201.11:26:58.64#ibcon#*before return 0, iclass 28, count 0 2006.201.11:26:58.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:58.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:26:58.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:26:58.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:26:58.64$vck44/vb=4,5 2006.201.11:26:58.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.11:26:58.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.11:26:58.64#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:58.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:58.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:58.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:58.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.11:26:58.70#ibcon#first serial, iclass 30, count 2 2006.201.11:26:58.70#ibcon#enter sib2, iclass 30, count 2 2006.201.11:26:58.70#ibcon#flushed, iclass 30, count 2 2006.201.11:26:58.70#ibcon#about to write, iclass 30, count 2 2006.201.11:26:58.70#ibcon#wrote, iclass 30, count 2 2006.201.11:26:58.70#ibcon#about to read 3, iclass 30, count 2 2006.201.11:26:58.72#ibcon#read 3, iclass 30, count 2 2006.201.11:26:58.72#ibcon#about to read 4, iclass 30, count 2 2006.201.11:26:58.72#ibcon#read 4, iclass 30, count 2 2006.201.11:26:58.72#ibcon#about to read 5, iclass 30, count 2 2006.201.11:26:58.72#ibcon#read 5, iclass 30, count 2 2006.201.11:26:58.72#ibcon#about to read 6, iclass 30, count 2 2006.201.11:26:58.72#ibcon#read 6, iclass 30, count 2 2006.201.11:26:58.72#ibcon#end of sib2, iclass 30, count 2 2006.201.11:26:58.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.11:26:58.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.11:26:58.72#ibcon#[27=AT04-05\r\n] 2006.201.11:26:58.72#ibcon#*before write, iclass 30, count 2 2006.201.11:26:58.72#ibcon#enter sib2, iclass 30, count 2 2006.201.11:26:58.72#ibcon#flushed, iclass 30, count 2 2006.201.11:26:58.72#ibcon#about to write, iclass 30, count 2 2006.201.11:26:58.72#ibcon#wrote, iclass 30, count 2 2006.201.11:26:58.72#ibcon#about to read 3, iclass 30, count 2 2006.201.11:26:58.75#ibcon#read 3, iclass 30, count 2 2006.201.11:26:58.75#ibcon#about to read 4, iclass 30, count 2 2006.201.11:26:58.75#ibcon#read 4, iclass 30, count 2 2006.201.11:26:58.75#ibcon#about to read 5, iclass 30, count 2 2006.201.11:26:58.75#ibcon#read 5, iclass 30, count 2 2006.201.11:26:58.75#ibcon#about to read 6, iclass 30, count 2 2006.201.11:26:58.75#ibcon#read 6, iclass 30, count 2 2006.201.11:26:58.75#ibcon#end of sib2, iclass 30, count 2 2006.201.11:26:58.75#ibcon#*after write, iclass 30, count 2 2006.201.11:26:58.75#ibcon#*before return 0, iclass 30, count 2 2006.201.11:26:58.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:58.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:26:58.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.11:26:58.75#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:58.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:58.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:58.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:58.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:26:58.87#ibcon#first serial, iclass 30, count 0 2006.201.11:26:58.87#ibcon#enter sib2, iclass 30, count 0 2006.201.11:26:58.87#ibcon#flushed, iclass 30, count 0 2006.201.11:26:58.87#ibcon#about to write, iclass 30, count 0 2006.201.11:26:58.87#ibcon#wrote, iclass 30, count 0 2006.201.11:26:58.87#ibcon#about to read 3, iclass 30, count 0 2006.201.11:26:58.89#ibcon#read 3, iclass 30, count 0 2006.201.11:26:58.89#ibcon#about to read 4, iclass 30, count 0 2006.201.11:26:58.89#ibcon#read 4, iclass 30, count 0 2006.201.11:26:58.89#ibcon#about to read 5, iclass 30, count 0 2006.201.11:26:58.89#ibcon#read 5, iclass 30, count 0 2006.201.11:26:58.89#ibcon#about to read 6, iclass 30, count 0 2006.201.11:26:58.89#ibcon#read 6, iclass 30, count 0 2006.201.11:26:58.89#ibcon#end of sib2, iclass 30, count 0 2006.201.11:26:58.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:26:58.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:26:58.89#ibcon#[27=USB\r\n] 2006.201.11:26:58.89#ibcon#*before write, iclass 30, count 0 2006.201.11:26:58.89#ibcon#enter sib2, iclass 30, count 0 2006.201.11:26:58.89#ibcon#flushed, iclass 30, count 0 2006.201.11:26:58.89#ibcon#about to write, iclass 30, count 0 2006.201.11:26:58.89#ibcon#wrote, iclass 30, count 0 2006.201.11:26:58.89#ibcon#about to read 3, iclass 30, count 0 2006.201.11:26:58.92#ibcon#read 3, iclass 30, count 0 2006.201.11:26:58.92#ibcon#about to read 4, iclass 30, count 0 2006.201.11:26:58.92#ibcon#read 4, iclass 30, count 0 2006.201.11:26:58.92#ibcon#about to read 5, iclass 30, count 0 2006.201.11:26:58.92#ibcon#read 5, iclass 30, count 0 2006.201.11:26:58.92#ibcon#about to read 6, iclass 30, count 0 2006.201.11:26:58.92#ibcon#read 6, iclass 30, count 0 2006.201.11:26:58.92#ibcon#end of sib2, iclass 30, count 0 2006.201.11:26:58.92#ibcon#*after write, iclass 30, count 0 2006.201.11:26:58.92#ibcon#*before return 0, iclass 30, count 0 2006.201.11:26:58.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:58.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:26:58.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:26:58.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:26:58.92$vck44/vblo=5,709.99 2006.201.11:26:58.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.11:26:58.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.11:26:58.92#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:58.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:58.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:58.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:58.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:26:58.92#ibcon#first serial, iclass 32, count 0 2006.201.11:26:58.92#ibcon#enter sib2, iclass 32, count 0 2006.201.11:26:58.92#ibcon#flushed, iclass 32, count 0 2006.201.11:26:58.92#ibcon#about to write, iclass 32, count 0 2006.201.11:26:58.92#ibcon#wrote, iclass 32, count 0 2006.201.11:26:58.92#ibcon#about to read 3, iclass 32, count 0 2006.201.11:26:58.94#ibcon#read 3, iclass 32, count 0 2006.201.11:26:58.94#ibcon#about to read 4, iclass 32, count 0 2006.201.11:26:58.94#ibcon#read 4, iclass 32, count 0 2006.201.11:26:58.94#ibcon#about to read 5, iclass 32, count 0 2006.201.11:26:58.94#ibcon#read 5, iclass 32, count 0 2006.201.11:26:58.94#ibcon#about to read 6, iclass 32, count 0 2006.201.11:26:58.94#ibcon#read 6, iclass 32, count 0 2006.201.11:26:58.94#ibcon#end of sib2, iclass 32, count 0 2006.201.11:26:58.94#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:26:58.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:26:58.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:26:58.94#ibcon#*before write, iclass 32, count 0 2006.201.11:26:58.94#ibcon#enter sib2, iclass 32, count 0 2006.201.11:26:58.94#ibcon#flushed, iclass 32, count 0 2006.201.11:26:58.94#ibcon#about to write, iclass 32, count 0 2006.201.11:26:58.94#ibcon#wrote, iclass 32, count 0 2006.201.11:26:58.94#ibcon#about to read 3, iclass 32, count 0 2006.201.11:26:58.98#ibcon#read 3, iclass 32, count 0 2006.201.11:26:58.98#ibcon#about to read 4, iclass 32, count 0 2006.201.11:26:58.98#ibcon#read 4, iclass 32, count 0 2006.201.11:26:58.98#ibcon#about to read 5, iclass 32, count 0 2006.201.11:26:58.98#ibcon#read 5, iclass 32, count 0 2006.201.11:26:58.98#ibcon#about to read 6, iclass 32, count 0 2006.201.11:26:58.98#ibcon#read 6, iclass 32, count 0 2006.201.11:26:58.98#ibcon#end of sib2, iclass 32, count 0 2006.201.11:26:58.98#ibcon#*after write, iclass 32, count 0 2006.201.11:26:58.98#ibcon#*before return 0, iclass 32, count 0 2006.201.11:26:58.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:58.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:26:58.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:26:58.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:26:58.98$vck44/vb=5,4 2006.201.11:26:58.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.11:26:58.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.11:26:58.98#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:58.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:59.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:59.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:59.04#ibcon#enter wrdev, iclass 34, count 2 2006.201.11:26:59.04#ibcon#first serial, iclass 34, count 2 2006.201.11:26:59.04#ibcon#enter sib2, iclass 34, count 2 2006.201.11:26:59.04#ibcon#flushed, iclass 34, count 2 2006.201.11:26:59.04#ibcon#about to write, iclass 34, count 2 2006.201.11:26:59.04#ibcon#wrote, iclass 34, count 2 2006.201.11:26:59.04#ibcon#about to read 3, iclass 34, count 2 2006.201.11:26:59.06#ibcon#read 3, iclass 34, count 2 2006.201.11:26:59.06#ibcon#about to read 4, iclass 34, count 2 2006.201.11:26:59.06#ibcon#read 4, iclass 34, count 2 2006.201.11:26:59.06#ibcon#about to read 5, iclass 34, count 2 2006.201.11:26:59.06#ibcon#read 5, iclass 34, count 2 2006.201.11:26:59.06#ibcon#about to read 6, iclass 34, count 2 2006.201.11:26:59.06#ibcon#read 6, iclass 34, count 2 2006.201.11:26:59.06#ibcon#end of sib2, iclass 34, count 2 2006.201.11:26:59.06#ibcon#*mode == 0, iclass 34, count 2 2006.201.11:26:59.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.11:26:59.06#ibcon#[27=AT05-04\r\n] 2006.201.11:26:59.06#ibcon#*before write, iclass 34, count 2 2006.201.11:26:59.06#ibcon#enter sib2, iclass 34, count 2 2006.201.11:26:59.06#ibcon#flushed, iclass 34, count 2 2006.201.11:26:59.06#ibcon#about to write, iclass 34, count 2 2006.201.11:26:59.06#ibcon#wrote, iclass 34, count 2 2006.201.11:26:59.06#ibcon#about to read 3, iclass 34, count 2 2006.201.11:26:59.09#ibcon#read 3, iclass 34, count 2 2006.201.11:26:59.09#ibcon#about to read 4, iclass 34, count 2 2006.201.11:26:59.09#ibcon#read 4, iclass 34, count 2 2006.201.11:26:59.09#ibcon#about to read 5, iclass 34, count 2 2006.201.11:26:59.09#ibcon#read 5, iclass 34, count 2 2006.201.11:26:59.09#ibcon#about to read 6, iclass 34, count 2 2006.201.11:26:59.09#ibcon#read 6, iclass 34, count 2 2006.201.11:26:59.09#ibcon#end of sib2, iclass 34, count 2 2006.201.11:26:59.09#ibcon#*after write, iclass 34, count 2 2006.201.11:26:59.09#ibcon#*before return 0, iclass 34, count 2 2006.201.11:26:59.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:59.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:26:59.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.11:26:59.09#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:59.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:59.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:59.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:59.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:26:59.21#ibcon#first serial, iclass 34, count 0 2006.201.11:26:59.21#ibcon#enter sib2, iclass 34, count 0 2006.201.11:26:59.21#ibcon#flushed, iclass 34, count 0 2006.201.11:26:59.21#ibcon#about to write, iclass 34, count 0 2006.201.11:26:59.21#ibcon#wrote, iclass 34, count 0 2006.201.11:26:59.21#ibcon#about to read 3, iclass 34, count 0 2006.201.11:26:59.23#ibcon#read 3, iclass 34, count 0 2006.201.11:26:59.23#ibcon#about to read 4, iclass 34, count 0 2006.201.11:26:59.23#ibcon#read 4, iclass 34, count 0 2006.201.11:26:59.23#ibcon#about to read 5, iclass 34, count 0 2006.201.11:26:59.23#ibcon#read 5, iclass 34, count 0 2006.201.11:26:59.23#ibcon#about to read 6, iclass 34, count 0 2006.201.11:26:59.23#ibcon#read 6, iclass 34, count 0 2006.201.11:26:59.23#ibcon#end of sib2, iclass 34, count 0 2006.201.11:26:59.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:26:59.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:26:59.23#ibcon#[27=USB\r\n] 2006.201.11:26:59.23#ibcon#*before write, iclass 34, count 0 2006.201.11:26:59.23#ibcon#enter sib2, iclass 34, count 0 2006.201.11:26:59.23#ibcon#flushed, iclass 34, count 0 2006.201.11:26:59.23#ibcon#about to write, iclass 34, count 0 2006.201.11:26:59.23#ibcon#wrote, iclass 34, count 0 2006.201.11:26:59.23#ibcon#about to read 3, iclass 34, count 0 2006.201.11:26:59.26#ibcon#read 3, iclass 34, count 0 2006.201.11:26:59.26#ibcon#about to read 4, iclass 34, count 0 2006.201.11:26:59.26#ibcon#read 4, iclass 34, count 0 2006.201.11:26:59.26#ibcon#about to read 5, iclass 34, count 0 2006.201.11:26:59.26#ibcon#read 5, iclass 34, count 0 2006.201.11:26:59.26#ibcon#about to read 6, iclass 34, count 0 2006.201.11:26:59.26#ibcon#read 6, iclass 34, count 0 2006.201.11:26:59.26#ibcon#end of sib2, iclass 34, count 0 2006.201.11:26:59.26#ibcon#*after write, iclass 34, count 0 2006.201.11:26:59.26#ibcon#*before return 0, iclass 34, count 0 2006.201.11:26:59.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:59.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:26:59.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:26:59.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:26:59.26$vck44/vblo=6,719.99 2006.201.11:26:59.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.11:26:59.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.11:26:59.26#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:59.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:59.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:59.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:59.26#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:26:59.26#ibcon#first serial, iclass 36, count 0 2006.201.11:26:59.26#ibcon#enter sib2, iclass 36, count 0 2006.201.11:26:59.26#ibcon#flushed, iclass 36, count 0 2006.201.11:26:59.26#ibcon#about to write, iclass 36, count 0 2006.201.11:26:59.26#ibcon#wrote, iclass 36, count 0 2006.201.11:26:59.26#ibcon#about to read 3, iclass 36, count 0 2006.201.11:26:59.28#ibcon#read 3, iclass 36, count 0 2006.201.11:26:59.28#ibcon#about to read 4, iclass 36, count 0 2006.201.11:26:59.28#ibcon#read 4, iclass 36, count 0 2006.201.11:26:59.28#ibcon#about to read 5, iclass 36, count 0 2006.201.11:26:59.28#ibcon#read 5, iclass 36, count 0 2006.201.11:26:59.28#ibcon#about to read 6, iclass 36, count 0 2006.201.11:26:59.28#ibcon#read 6, iclass 36, count 0 2006.201.11:26:59.28#ibcon#end of sib2, iclass 36, count 0 2006.201.11:26:59.28#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:26:59.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:26:59.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:26:59.28#ibcon#*before write, iclass 36, count 0 2006.201.11:26:59.28#ibcon#enter sib2, iclass 36, count 0 2006.201.11:26:59.28#ibcon#flushed, iclass 36, count 0 2006.201.11:26:59.28#ibcon#about to write, iclass 36, count 0 2006.201.11:26:59.28#ibcon#wrote, iclass 36, count 0 2006.201.11:26:59.28#ibcon#about to read 3, iclass 36, count 0 2006.201.11:26:59.33#ibcon#read 3, iclass 36, count 0 2006.201.11:26:59.33#ibcon#about to read 4, iclass 36, count 0 2006.201.11:26:59.33#ibcon#read 4, iclass 36, count 0 2006.201.11:26:59.33#ibcon#about to read 5, iclass 36, count 0 2006.201.11:26:59.33#ibcon#read 5, iclass 36, count 0 2006.201.11:26:59.33#ibcon#about to read 6, iclass 36, count 0 2006.201.11:26:59.33#ibcon#read 6, iclass 36, count 0 2006.201.11:26:59.33#ibcon#end of sib2, iclass 36, count 0 2006.201.11:26:59.33#ibcon#*after write, iclass 36, count 0 2006.201.11:26:59.33#ibcon#*before return 0, iclass 36, count 0 2006.201.11:26:59.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:59.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:26:59.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:26:59.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:26:59.33$vck44/vb=6,4 2006.201.11:26:59.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.11:26:59.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.11:26:59.33#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:59.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:59.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:59.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:59.38#ibcon#enter wrdev, iclass 38, count 2 2006.201.11:26:59.38#ibcon#first serial, iclass 38, count 2 2006.201.11:26:59.38#ibcon#enter sib2, iclass 38, count 2 2006.201.11:26:59.38#ibcon#flushed, iclass 38, count 2 2006.201.11:26:59.38#ibcon#about to write, iclass 38, count 2 2006.201.11:26:59.38#ibcon#wrote, iclass 38, count 2 2006.201.11:26:59.38#ibcon#about to read 3, iclass 38, count 2 2006.201.11:26:59.40#ibcon#read 3, iclass 38, count 2 2006.201.11:26:59.40#ibcon#about to read 4, iclass 38, count 2 2006.201.11:26:59.40#ibcon#read 4, iclass 38, count 2 2006.201.11:26:59.40#ibcon#about to read 5, iclass 38, count 2 2006.201.11:26:59.40#ibcon#read 5, iclass 38, count 2 2006.201.11:26:59.40#ibcon#about to read 6, iclass 38, count 2 2006.201.11:26:59.40#ibcon#read 6, iclass 38, count 2 2006.201.11:26:59.40#ibcon#end of sib2, iclass 38, count 2 2006.201.11:26:59.40#ibcon#*mode == 0, iclass 38, count 2 2006.201.11:26:59.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.11:26:59.40#ibcon#[27=AT06-04\r\n] 2006.201.11:26:59.40#ibcon#*before write, iclass 38, count 2 2006.201.11:26:59.40#ibcon#enter sib2, iclass 38, count 2 2006.201.11:26:59.40#ibcon#flushed, iclass 38, count 2 2006.201.11:26:59.40#ibcon#about to write, iclass 38, count 2 2006.201.11:26:59.40#ibcon#wrote, iclass 38, count 2 2006.201.11:26:59.40#ibcon#about to read 3, iclass 38, count 2 2006.201.11:26:59.43#ibcon#read 3, iclass 38, count 2 2006.201.11:26:59.43#ibcon#about to read 4, iclass 38, count 2 2006.201.11:26:59.43#ibcon#read 4, iclass 38, count 2 2006.201.11:26:59.43#ibcon#about to read 5, iclass 38, count 2 2006.201.11:26:59.43#ibcon#read 5, iclass 38, count 2 2006.201.11:26:59.43#ibcon#about to read 6, iclass 38, count 2 2006.201.11:26:59.43#ibcon#read 6, iclass 38, count 2 2006.201.11:26:59.43#ibcon#end of sib2, iclass 38, count 2 2006.201.11:26:59.43#ibcon#*after write, iclass 38, count 2 2006.201.11:26:59.43#ibcon#*before return 0, iclass 38, count 2 2006.201.11:26:59.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:59.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:26:59.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.11:26:59.43#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:59.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:59.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:59.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:59.55#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:26:59.55#ibcon#first serial, iclass 38, count 0 2006.201.11:26:59.55#ibcon#enter sib2, iclass 38, count 0 2006.201.11:26:59.55#ibcon#flushed, iclass 38, count 0 2006.201.11:26:59.55#ibcon#about to write, iclass 38, count 0 2006.201.11:26:59.55#ibcon#wrote, iclass 38, count 0 2006.201.11:26:59.55#ibcon#about to read 3, iclass 38, count 0 2006.201.11:26:59.57#ibcon#read 3, iclass 38, count 0 2006.201.11:26:59.57#ibcon#about to read 4, iclass 38, count 0 2006.201.11:26:59.57#ibcon#read 4, iclass 38, count 0 2006.201.11:26:59.57#ibcon#about to read 5, iclass 38, count 0 2006.201.11:26:59.57#ibcon#read 5, iclass 38, count 0 2006.201.11:26:59.57#ibcon#about to read 6, iclass 38, count 0 2006.201.11:26:59.57#ibcon#read 6, iclass 38, count 0 2006.201.11:26:59.57#ibcon#end of sib2, iclass 38, count 0 2006.201.11:26:59.57#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:26:59.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:26:59.57#ibcon#[27=USB\r\n] 2006.201.11:26:59.57#ibcon#*before write, iclass 38, count 0 2006.201.11:26:59.57#ibcon#enter sib2, iclass 38, count 0 2006.201.11:26:59.57#ibcon#flushed, iclass 38, count 0 2006.201.11:26:59.57#ibcon#about to write, iclass 38, count 0 2006.201.11:26:59.57#ibcon#wrote, iclass 38, count 0 2006.201.11:26:59.57#ibcon#about to read 3, iclass 38, count 0 2006.201.11:26:59.60#ibcon#read 3, iclass 38, count 0 2006.201.11:26:59.60#ibcon#about to read 4, iclass 38, count 0 2006.201.11:26:59.60#ibcon#read 4, iclass 38, count 0 2006.201.11:26:59.60#ibcon#about to read 5, iclass 38, count 0 2006.201.11:26:59.60#ibcon#read 5, iclass 38, count 0 2006.201.11:26:59.60#ibcon#about to read 6, iclass 38, count 0 2006.201.11:26:59.60#ibcon#read 6, iclass 38, count 0 2006.201.11:26:59.60#ibcon#end of sib2, iclass 38, count 0 2006.201.11:26:59.60#ibcon#*after write, iclass 38, count 0 2006.201.11:26:59.60#ibcon#*before return 0, iclass 38, count 0 2006.201.11:26:59.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:59.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:26:59.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:26:59.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:26:59.60$vck44/vblo=7,734.99 2006.201.11:26:59.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.11:26:59.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.11:26:59.60#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:59.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:59.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:59.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:59.60#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:26:59.60#ibcon#first serial, iclass 40, count 0 2006.201.11:26:59.60#ibcon#enter sib2, iclass 40, count 0 2006.201.11:26:59.60#ibcon#flushed, iclass 40, count 0 2006.201.11:26:59.60#ibcon#about to write, iclass 40, count 0 2006.201.11:26:59.60#ibcon#wrote, iclass 40, count 0 2006.201.11:26:59.60#ibcon#about to read 3, iclass 40, count 0 2006.201.11:26:59.62#ibcon#read 3, iclass 40, count 0 2006.201.11:26:59.62#ibcon#about to read 4, iclass 40, count 0 2006.201.11:26:59.62#ibcon#read 4, iclass 40, count 0 2006.201.11:26:59.62#ibcon#about to read 5, iclass 40, count 0 2006.201.11:26:59.62#ibcon#read 5, iclass 40, count 0 2006.201.11:26:59.62#ibcon#about to read 6, iclass 40, count 0 2006.201.11:26:59.62#ibcon#read 6, iclass 40, count 0 2006.201.11:26:59.62#ibcon#end of sib2, iclass 40, count 0 2006.201.11:26:59.62#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:26:59.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:26:59.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:26:59.62#ibcon#*before write, iclass 40, count 0 2006.201.11:26:59.62#ibcon#enter sib2, iclass 40, count 0 2006.201.11:26:59.62#ibcon#flushed, iclass 40, count 0 2006.201.11:26:59.62#ibcon#about to write, iclass 40, count 0 2006.201.11:26:59.62#ibcon#wrote, iclass 40, count 0 2006.201.11:26:59.62#ibcon#about to read 3, iclass 40, count 0 2006.201.11:26:59.66#ibcon#read 3, iclass 40, count 0 2006.201.11:26:59.66#ibcon#about to read 4, iclass 40, count 0 2006.201.11:26:59.66#ibcon#read 4, iclass 40, count 0 2006.201.11:26:59.66#ibcon#about to read 5, iclass 40, count 0 2006.201.11:26:59.66#ibcon#read 5, iclass 40, count 0 2006.201.11:26:59.66#ibcon#about to read 6, iclass 40, count 0 2006.201.11:26:59.66#ibcon#read 6, iclass 40, count 0 2006.201.11:26:59.66#ibcon#end of sib2, iclass 40, count 0 2006.201.11:26:59.66#ibcon#*after write, iclass 40, count 0 2006.201.11:26:59.66#ibcon#*before return 0, iclass 40, count 0 2006.201.11:26:59.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:59.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:26:59.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:26:59.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:26:59.66$vck44/vb=7,4 2006.201.11:26:59.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.11:26:59.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.11:26:59.66#ibcon#ireg 11 cls_cnt 2 2006.201.11:26:59.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:59.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:59.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:59.72#ibcon#enter wrdev, iclass 4, count 2 2006.201.11:26:59.72#ibcon#first serial, iclass 4, count 2 2006.201.11:26:59.72#ibcon#enter sib2, iclass 4, count 2 2006.201.11:26:59.72#ibcon#flushed, iclass 4, count 2 2006.201.11:26:59.72#ibcon#about to write, iclass 4, count 2 2006.201.11:26:59.72#ibcon#wrote, iclass 4, count 2 2006.201.11:26:59.72#ibcon#about to read 3, iclass 4, count 2 2006.201.11:26:59.74#ibcon#read 3, iclass 4, count 2 2006.201.11:26:59.74#ibcon#about to read 4, iclass 4, count 2 2006.201.11:26:59.74#ibcon#read 4, iclass 4, count 2 2006.201.11:26:59.74#ibcon#about to read 5, iclass 4, count 2 2006.201.11:26:59.74#ibcon#read 5, iclass 4, count 2 2006.201.11:26:59.74#ibcon#about to read 6, iclass 4, count 2 2006.201.11:26:59.74#ibcon#read 6, iclass 4, count 2 2006.201.11:26:59.74#ibcon#end of sib2, iclass 4, count 2 2006.201.11:26:59.74#ibcon#*mode == 0, iclass 4, count 2 2006.201.11:26:59.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.11:26:59.74#ibcon#[27=AT07-04\r\n] 2006.201.11:26:59.74#ibcon#*before write, iclass 4, count 2 2006.201.11:26:59.74#ibcon#enter sib2, iclass 4, count 2 2006.201.11:26:59.74#ibcon#flushed, iclass 4, count 2 2006.201.11:26:59.74#ibcon#about to write, iclass 4, count 2 2006.201.11:26:59.74#ibcon#wrote, iclass 4, count 2 2006.201.11:26:59.74#ibcon#about to read 3, iclass 4, count 2 2006.201.11:26:59.77#ibcon#read 3, iclass 4, count 2 2006.201.11:26:59.77#ibcon#about to read 4, iclass 4, count 2 2006.201.11:26:59.77#ibcon#read 4, iclass 4, count 2 2006.201.11:26:59.77#ibcon#about to read 5, iclass 4, count 2 2006.201.11:26:59.77#ibcon#read 5, iclass 4, count 2 2006.201.11:26:59.77#ibcon#about to read 6, iclass 4, count 2 2006.201.11:26:59.77#ibcon#read 6, iclass 4, count 2 2006.201.11:26:59.77#ibcon#end of sib2, iclass 4, count 2 2006.201.11:26:59.77#ibcon#*after write, iclass 4, count 2 2006.201.11:26:59.77#ibcon#*before return 0, iclass 4, count 2 2006.201.11:26:59.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:59.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:26:59.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.11:26:59.77#ibcon#ireg 7 cls_cnt 0 2006.201.11:26:59.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:59.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:59.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:59.89#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:26:59.89#ibcon#first serial, iclass 4, count 0 2006.201.11:26:59.89#ibcon#enter sib2, iclass 4, count 0 2006.201.11:26:59.89#ibcon#flushed, iclass 4, count 0 2006.201.11:26:59.89#ibcon#about to write, iclass 4, count 0 2006.201.11:26:59.89#ibcon#wrote, iclass 4, count 0 2006.201.11:26:59.89#ibcon#about to read 3, iclass 4, count 0 2006.201.11:26:59.91#ibcon#read 3, iclass 4, count 0 2006.201.11:26:59.91#ibcon#about to read 4, iclass 4, count 0 2006.201.11:26:59.91#ibcon#read 4, iclass 4, count 0 2006.201.11:26:59.91#ibcon#about to read 5, iclass 4, count 0 2006.201.11:26:59.91#ibcon#read 5, iclass 4, count 0 2006.201.11:26:59.91#ibcon#about to read 6, iclass 4, count 0 2006.201.11:26:59.91#ibcon#read 6, iclass 4, count 0 2006.201.11:26:59.91#ibcon#end of sib2, iclass 4, count 0 2006.201.11:26:59.91#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:26:59.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:26:59.91#ibcon#[27=USB\r\n] 2006.201.11:26:59.91#ibcon#*before write, iclass 4, count 0 2006.201.11:26:59.91#ibcon#enter sib2, iclass 4, count 0 2006.201.11:26:59.91#ibcon#flushed, iclass 4, count 0 2006.201.11:26:59.91#ibcon#about to write, iclass 4, count 0 2006.201.11:26:59.91#ibcon#wrote, iclass 4, count 0 2006.201.11:26:59.91#ibcon#about to read 3, iclass 4, count 0 2006.201.11:26:59.94#ibcon#read 3, iclass 4, count 0 2006.201.11:26:59.94#ibcon#about to read 4, iclass 4, count 0 2006.201.11:26:59.94#ibcon#read 4, iclass 4, count 0 2006.201.11:26:59.94#ibcon#about to read 5, iclass 4, count 0 2006.201.11:26:59.94#ibcon#read 5, iclass 4, count 0 2006.201.11:26:59.94#ibcon#about to read 6, iclass 4, count 0 2006.201.11:26:59.94#ibcon#read 6, iclass 4, count 0 2006.201.11:26:59.94#ibcon#end of sib2, iclass 4, count 0 2006.201.11:26:59.94#ibcon#*after write, iclass 4, count 0 2006.201.11:26:59.94#ibcon#*before return 0, iclass 4, count 0 2006.201.11:26:59.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:59.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:26:59.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:26:59.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:26:59.94$vck44/vblo=8,744.99 2006.201.11:26:59.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.11:26:59.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.11:26:59.94#ibcon#ireg 17 cls_cnt 0 2006.201.11:26:59.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:26:59.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:26:59.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:26:59.94#ibcon#enter wrdev, iclass 6, count 0 2006.201.11:26:59.94#ibcon#first serial, iclass 6, count 0 2006.201.11:26:59.94#ibcon#enter sib2, iclass 6, count 0 2006.201.11:26:59.94#ibcon#flushed, iclass 6, count 0 2006.201.11:26:59.94#ibcon#about to write, iclass 6, count 0 2006.201.11:26:59.94#ibcon#wrote, iclass 6, count 0 2006.201.11:26:59.94#ibcon#about to read 3, iclass 6, count 0 2006.201.11:26:59.96#ibcon#read 3, iclass 6, count 0 2006.201.11:26:59.96#ibcon#about to read 4, iclass 6, count 0 2006.201.11:26:59.96#ibcon#read 4, iclass 6, count 0 2006.201.11:26:59.96#ibcon#about to read 5, iclass 6, count 0 2006.201.11:26:59.96#ibcon#read 5, iclass 6, count 0 2006.201.11:26:59.96#ibcon#about to read 6, iclass 6, count 0 2006.201.11:26:59.96#ibcon#read 6, iclass 6, count 0 2006.201.11:26:59.96#ibcon#end of sib2, iclass 6, count 0 2006.201.11:26:59.96#ibcon#*mode == 0, iclass 6, count 0 2006.201.11:26:59.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.11:26:59.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:26:59.96#ibcon#*before write, iclass 6, count 0 2006.201.11:26:59.96#ibcon#enter sib2, iclass 6, count 0 2006.201.11:26:59.96#ibcon#flushed, iclass 6, count 0 2006.201.11:26:59.96#ibcon#about to write, iclass 6, count 0 2006.201.11:26:59.96#ibcon#wrote, iclass 6, count 0 2006.201.11:26:59.96#ibcon#about to read 3, iclass 6, count 0 2006.201.11:27:00.00#ibcon#read 3, iclass 6, count 0 2006.201.11:27:00.00#ibcon#about to read 4, iclass 6, count 0 2006.201.11:27:00.00#ibcon#read 4, iclass 6, count 0 2006.201.11:27:00.00#ibcon#about to read 5, iclass 6, count 0 2006.201.11:27:00.00#ibcon#read 5, iclass 6, count 0 2006.201.11:27:00.00#ibcon#about to read 6, iclass 6, count 0 2006.201.11:27:00.00#ibcon#read 6, iclass 6, count 0 2006.201.11:27:00.00#ibcon#end of sib2, iclass 6, count 0 2006.201.11:27:00.00#ibcon#*after write, iclass 6, count 0 2006.201.11:27:00.00#ibcon#*before return 0, iclass 6, count 0 2006.201.11:27:00.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:27:00.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:27:00.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.11:27:00.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.11:27:00.00$vck44/vb=8,4 2006.201.11:27:00.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.11:27:00.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.11:27:00.00#ibcon#ireg 11 cls_cnt 2 2006.201.11:27:00.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:27:00.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:27:00.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:27:00.06#ibcon#enter wrdev, iclass 10, count 2 2006.201.11:27:00.06#ibcon#first serial, iclass 10, count 2 2006.201.11:27:00.06#ibcon#enter sib2, iclass 10, count 2 2006.201.11:27:00.06#ibcon#flushed, iclass 10, count 2 2006.201.11:27:00.06#ibcon#about to write, iclass 10, count 2 2006.201.11:27:00.06#ibcon#wrote, iclass 10, count 2 2006.201.11:27:00.06#ibcon#about to read 3, iclass 10, count 2 2006.201.11:27:00.08#ibcon#read 3, iclass 10, count 2 2006.201.11:27:00.08#ibcon#about to read 4, iclass 10, count 2 2006.201.11:27:00.08#ibcon#read 4, iclass 10, count 2 2006.201.11:27:00.08#ibcon#about to read 5, iclass 10, count 2 2006.201.11:27:00.08#ibcon#read 5, iclass 10, count 2 2006.201.11:27:00.08#ibcon#about to read 6, iclass 10, count 2 2006.201.11:27:00.08#ibcon#read 6, iclass 10, count 2 2006.201.11:27:00.08#ibcon#end of sib2, iclass 10, count 2 2006.201.11:27:00.08#ibcon#*mode == 0, iclass 10, count 2 2006.201.11:27:00.08#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.11:27:00.08#ibcon#[27=AT08-04\r\n] 2006.201.11:27:00.08#ibcon#*before write, iclass 10, count 2 2006.201.11:27:00.08#ibcon#enter sib2, iclass 10, count 2 2006.201.11:27:00.08#ibcon#flushed, iclass 10, count 2 2006.201.11:27:00.08#ibcon#about to write, iclass 10, count 2 2006.201.11:27:00.08#ibcon#wrote, iclass 10, count 2 2006.201.11:27:00.08#ibcon#about to read 3, iclass 10, count 2 2006.201.11:27:00.11#ibcon#read 3, iclass 10, count 2 2006.201.11:27:00.11#ibcon#about to read 4, iclass 10, count 2 2006.201.11:27:00.11#ibcon#read 4, iclass 10, count 2 2006.201.11:27:00.11#ibcon#about to read 5, iclass 10, count 2 2006.201.11:27:00.11#ibcon#read 5, iclass 10, count 2 2006.201.11:27:00.11#ibcon#about to read 6, iclass 10, count 2 2006.201.11:27:00.11#ibcon#read 6, iclass 10, count 2 2006.201.11:27:00.11#ibcon#end of sib2, iclass 10, count 2 2006.201.11:27:00.11#ibcon#*after write, iclass 10, count 2 2006.201.11:27:00.11#ibcon#*before return 0, iclass 10, count 2 2006.201.11:27:00.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:27:00.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:27:00.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.11:27:00.11#ibcon#ireg 7 cls_cnt 0 2006.201.11:27:00.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:27:00.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:27:00.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:27:00.23#ibcon#enter wrdev, iclass 10, count 0 2006.201.11:27:00.23#ibcon#first serial, iclass 10, count 0 2006.201.11:27:00.23#ibcon#enter sib2, iclass 10, count 0 2006.201.11:27:00.23#ibcon#flushed, iclass 10, count 0 2006.201.11:27:00.23#ibcon#about to write, iclass 10, count 0 2006.201.11:27:00.23#ibcon#wrote, iclass 10, count 0 2006.201.11:27:00.23#ibcon#about to read 3, iclass 10, count 0 2006.201.11:27:00.25#ibcon#read 3, iclass 10, count 0 2006.201.11:27:00.25#ibcon#about to read 4, iclass 10, count 0 2006.201.11:27:00.25#ibcon#read 4, iclass 10, count 0 2006.201.11:27:00.25#ibcon#about to read 5, iclass 10, count 0 2006.201.11:27:00.25#ibcon#read 5, iclass 10, count 0 2006.201.11:27:00.25#ibcon#about to read 6, iclass 10, count 0 2006.201.11:27:00.25#ibcon#read 6, iclass 10, count 0 2006.201.11:27:00.25#ibcon#end of sib2, iclass 10, count 0 2006.201.11:27:00.25#ibcon#*mode == 0, iclass 10, count 0 2006.201.11:27:00.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.11:27:00.25#ibcon#[27=USB\r\n] 2006.201.11:27:00.25#ibcon#*before write, iclass 10, count 0 2006.201.11:27:00.25#ibcon#enter sib2, iclass 10, count 0 2006.201.11:27:00.25#ibcon#flushed, iclass 10, count 0 2006.201.11:27:00.25#ibcon#about to write, iclass 10, count 0 2006.201.11:27:00.25#ibcon#wrote, iclass 10, count 0 2006.201.11:27:00.25#ibcon#about to read 3, iclass 10, count 0 2006.201.11:27:00.28#ibcon#read 3, iclass 10, count 0 2006.201.11:27:00.28#ibcon#about to read 4, iclass 10, count 0 2006.201.11:27:00.28#ibcon#read 4, iclass 10, count 0 2006.201.11:27:00.28#ibcon#about to read 5, iclass 10, count 0 2006.201.11:27:00.28#ibcon#read 5, iclass 10, count 0 2006.201.11:27:00.28#ibcon#about to read 6, iclass 10, count 0 2006.201.11:27:00.28#ibcon#read 6, iclass 10, count 0 2006.201.11:27:00.28#ibcon#end of sib2, iclass 10, count 0 2006.201.11:27:00.28#ibcon#*after write, iclass 10, count 0 2006.201.11:27:00.28#ibcon#*before return 0, iclass 10, count 0 2006.201.11:27:00.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:27:00.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:27:00.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.11:27:00.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.11:27:00.28$vck44/vabw=wide 2006.201.11:27:00.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.11:27:00.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.11:27:00.28#ibcon#ireg 8 cls_cnt 0 2006.201.11:27:00.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:27:00.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:27:00.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:27:00.28#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:27:00.28#ibcon#first serial, iclass 12, count 0 2006.201.11:27:00.28#ibcon#enter sib2, iclass 12, count 0 2006.201.11:27:00.28#ibcon#flushed, iclass 12, count 0 2006.201.11:27:00.28#ibcon#about to write, iclass 12, count 0 2006.201.11:27:00.28#ibcon#wrote, iclass 12, count 0 2006.201.11:27:00.28#ibcon#about to read 3, iclass 12, count 0 2006.201.11:27:00.30#ibcon#read 3, iclass 12, count 0 2006.201.11:27:00.30#ibcon#about to read 4, iclass 12, count 0 2006.201.11:27:00.30#ibcon#read 4, iclass 12, count 0 2006.201.11:27:00.30#ibcon#about to read 5, iclass 12, count 0 2006.201.11:27:00.30#ibcon#read 5, iclass 12, count 0 2006.201.11:27:00.30#ibcon#about to read 6, iclass 12, count 0 2006.201.11:27:00.30#ibcon#read 6, iclass 12, count 0 2006.201.11:27:00.30#ibcon#end of sib2, iclass 12, count 0 2006.201.11:27:00.30#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:27:00.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:27:00.30#ibcon#[25=BW32\r\n] 2006.201.11:27:00.30#ibcon#*before write, iclass 12, count 0 2006.201.11:27:00.30#ibcon#enter sib2, iclass 12, count 0 2006.201.11:27:00.30#ibcon#flushed, iclass 12, count 0 2006.201.11:27:00.30#ibcon#about to write, iclass 12, count 0 2006.201.11:27:00.30#ibcon#wrote, iclass 12, count 0 2006.201.11:27:00.30#ibcon#about to read 3, iclass 12, count 0 2006.201.11:27:00.34#ibcon#read 3, iclass 12, count 0 2006.201.11:27:00.34#ibcon#about to read 4, iclass 12, count 0 2006.201.11:27:00.34#ibcon#read 4, iclass 12, count 0 2006.201.11:27:00.34#ibcon#about to read 5, iclass 12, count 0 2006.201.11:27:00.34#ibcon#read 5, iclass 12, count 0 2006.201.11:27:00.34#ibcon#about to read 6, iclass 12, count 0 2006.201.11:27:00.34#ibcon#read 6, iclass 12, count 0 2006.201.11:27:00.34#ibcon#end of sib2, iclass 12, count 0 2006.201.11:27:00.34#ibcon#*after write, iclass 12, count 0 2006.201.11:27:00.34#ibcon#*before return 0, iclass 12, count 0 2006.201.11:27:00.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:27:00.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:27:00.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:27:00.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:27:00.34$vck44/vbbw=wide 2006.201.11:27:00.34#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.11:27:00.34#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.11:27:00.34#ibcon#ireg 8 cls_cnt 0 2006.201.11:27:00.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:27:00.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:27:00.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:27:00.40#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:27:00.40#ibcon#first serial, iclass 14, count 0 2006.201.11:27:00.40#ibcon#enter sib2, iclass 14, count 0 2006.201.11:27:00.40#ibcon#flushed, iclass 14, count 0 2006.201.11:27:00.40#ibcon#about to write, iclass 14, count 0 2006.201.11:27:00.40#ibcon#wrote, iclass 14, count 0 2006.201.11:27:00.40#ibcon#about to read 3, iclass 14, count 0 2006.201.11:27:00.42#ibcon#read 3, iclass 14, count 0 2006.201.11:27:00.42#ibcon#about to read 4, iclass 14, count 0 2006.201.11:27:00.42#ibcon#read 4, iclass 14, count 0 2006.201.11:27:00.42#ibcon#about to read 5, iclass 14, count 0 2006.201.11:27:00.42#ibcon#read 5, iclass 14, count 0 2006.201.11:27:00.42#ibcon#about to read 6, iclass 14, count 0 2006.201.11:27:00.42#ibcon#read 6, iclass 14, count 0 2006.201.11:27:00.42#ibcon#end of sib2, iclass 14, count 0 2006.201.11:27:00.42#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:27:00.42#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:27:00.42#ibcon#[27=BW32\r\n] 2006.201.11:27:00.42#ibcon#*before write, iclass 14, count 0 2006.201.11:27:00.42#ibcon#enter sib2, iclass 14, count 0 2006.201.11:27:00.42#ibcon#flushed, iclass 14, count 0 2006.201.11:27:00.42#ibcon#about to write, iclass 14, count 0 2006.201.11:27:00.42#ibcon#wrote, iclass 14, count 0 2006.201.11:27:00.42#ibcon#about to read 3, iclass 14, count 0 2006.201.11:27:00.45#ibcon#read 3, iclass 14, count 0 2006.201.11:27:00.45#ibcon#about to read 4, iclass 14, count 0 2006.201.11:27:00.45#ibcon#read 4, iclass 14, count 0 2006.201.11:27:00.45#ibcon#about to read 5, iclass 14, count 0 2006.201.11:27:00.45#ibcon#read 5, iclass 14, count 0 2006.201.11:27:00.45#ibcon#about to read 6, iclass 14, count 0 2006.201.11:27:00.45#ibcon#read 6, iclass 14, count 0 2006.201.11:27:00.45#ibcon#end of sib2, iclass 14, count 0 2006.201.11:27:00.45#ibcon#*after write, iclass 14, count 0 2006.201.11:27:00.45#ibcon#*before return 0, iclass 14, count 0 2006.201.11:27:00.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:27:00.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:27:00.45#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:27:00.45#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:27:00.45$setupk4/ifdk4 2006.201.11:27:00.45$ifdk4/lo= 2006.201.11:27:00.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:27:00.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:27:00.45$ifdk4/patch= 2006.201.11:27:00.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:27:00.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:27:00.45$setupk4/!*+20s 2006.201.11:27:01.99#abcon#<5=/04 1.9 3.7 21.411001004.0\r\n> 2006.201.11:27:02.01#abcon#{5=INTERFACE CLEAR} 2006.201.11:27:02.07#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:27:12.16#abcon#<5=/04 1.9 3.7 21.411001004.0\r\n> 2006.201.11:27:12.18#abcon#{5=INTERFACE CLEAR} 2006.201.11:27:12.24#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:27:14.90$setupk4/"tpicd 2006.201.11:27:14.90$setupk4/echo=off 2006.201.11:27:14.90$setupk4/xlog=off 2006.201.11:27:14.90:!2006.201.11:29:08 2006.201.11:27:39.14#trakl#Source acquired 2006.201.11:27:41.14#flagr#flagr/antenna,acquired 2006.201.11:29:08.00:preob 2006.201.11:29:09.14/onsource/TRACKING 2006.201.11:29:09.14:!2006.201.11:29:18 2006.201.11:29:18.00:"tape 2006.201.11:29:18.00:"st=record 2006.201.11:29:18.00:data_valid=on 2006.201.11:29:18.00:midob 2006.201.11:29:18.14/onsource/TRACKING 2006.201.11:29:18.14/wx/21.41,1004.0,100 2006.201.11:29:18.36/cable/+6.4720E-03 2006.201.11:29:19.45/va/01,08,usb,yes,30,32 2006.201.11:29:19.45/va/02,07,usb,yes,32,33 2006.201.11:29:19.45/va/03,08,usb,yes,29,30 2006.201.11:29:19.45/va/04,07,usb,yes,33,35 2006.201.11:29:19.45/va/05,04,usb,yes,29,30 2006.201.11:29:19.45/va/06,05,usb,yes,29,29 2006.201.11:29:19.45/va/07,05,usb,yes,28,29 2006.201.11:29:19.45/va/08,04,usb,yes,28,34 2006.201.11:29:19.68/valo/01,524.99,yes,locked 2006.201.11:29:19.68/valo/02,534.99,yes,locked 2006.201.11:29:19.68/valo/03,564.99,yes,locked 2006.201.11:29:19.68/valo/04,624.99,yes,locked 2006.201.11:29:19.68/valo/05,734.99,yes,locked 2006.201.11:29:19.68/valo/06,814.99,yes,locked 2006.201.11:29:19.68/valo/07,864.99,yes,locked 2006.201.11:29:19.68/valo/08,884.99,yes,locked 2006.201.11:29:20.77/vb/01,04,usb,yes,29,27 2006.201.11:29:20.77/vb/02,05,usb,yes,27,27 2006.201.11:29:20.77/vb/03,04,usb,yes,28,31 2006.201.11:29:20.77/vb/04,05,usb,yes,29,28 2006.201.11:29:20.77/vb/05,04,usb,yes,25,28 2006.201.11:29:20.77/vb/06,04,usb,yes,29,26 2006.201.11:29:20.77/vb/07,04,usb,yes,29,29 2006.201.11:29:20.77/vb/08,04,usb,yes,27,30 2006.201.11:29:21.01/vblo/01,629.99,yes,locked 2006.201.11:29:21.01/vblo/02,634.99,yes,locked 2006.201.11:29:21.01/vblo/03,649.99,yes,locked 2006.201.11:29:21.01/vblo/04,679.99,yes,locked 2006.201.11:29:21.01/vblo/05,709.99,yes,locked 2006.201.11:29:21.01/vblo/06,719.99,yes,locked 2006.201.11:29:21.01/vblo/07,734.99,yes,locked 2006.201.11:29:21.01/vblo/08,744.99,yes,locked 2006.201.11:29:21.16/vabw/8 2006.201.11:29:21.31/vbbw/8 2006.201.11:29:21.40/xfe/off,on,15.5 2006.201.11:29:21.77/ifatt/23,28,28,28 2006.201.11:29:22.05/fmout-gps/S +4.56E-07 2006.201.11:29:22.12:!2006.201.11:31:08 2006.201.11:31:08.00:data_valid=off 2006.201.11:31:08.00:"et 2006.201.11:31:08.00:!+3s 2006.201.11:31:11.02:"tape 2006.201.11:31:11.02:postob 2006.201.11:31:11.20/cable/+6.4728E-03 2006.201.11:31:11.20/wx/21.40,1004.0,100 2006.201.11:31:11.28/fmout-gps/S +4.56E-07 2006.201.11:31:11.28:scan_name=201-1133,jd0607,710 2006.201.11:31:11.28:source=1749+096,175132.82,093900.7,2000.0,ccw 2006.201.11:31:12.14#flagr#flagr/antenna,new-source 2006.201.11:31:12.14:checkk5 2006.201.11:31:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:31:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:31:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:31:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:31:14.00/chk_obsdata//k5ts1/T2011129??a.dat file size is correct (nominal:440MB, actual:440MB). 2006.201.11:31:14.37/chk_obsdata//k5ts2/T2011129??b.dat file size is correct (nominal:440MB, actual:440MB). 2006.201.11:31:14.74/chk_obsdata//k5ts3/T2011129??c.dat file size is correct (nominal:440MB, actual:440MB). 2006.201.11:31:15.10/chk_obsdata//k5ts4/T2011129??d.dat file size is correct (nominal:440MB, actual:440MB). 2006.201.11:31:15.79/k5log//k5ts1_log_newline 2006.201.11:31:16.48/k5log//k5ts2_log_newline 2006.201.11:31:17.17/k5log//k5ts3_log_newline 2006.201.11:31:17.85/k5log//k5ts4_log_newline 2006.201.11:31:17.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:31:17.88:setupk4=1 2006.201.11:31:17.88$setupk4/echo=on 2006.201.11:31:17.88$setupk4/pcalon 2006.201.11:31:17.88$pcalon/"no phase cal control is implemented here 2006.201.11:31:17.88$setupk4/"tpicd=stop 2006.201.11:31:17.88$setupk4/"rec=synch_on 2006.201.11:31:17.88$setupk4/"rec_mode=128 2006.201.11:31:17.88$setupk4/!* 2006.201.11:31:17.88$setupk4/recpk4 2006.201.11:31:17.88$recpk4/recpatch= 2006.201.11:31:17.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:31:17.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:31:17.88$setupk4/vck44 2006.201.11:31:17.88$vck44/valo=1,524.99 2006.201.11:31:17.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.11:31:17.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.11:31:17.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:17.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:17.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:17.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:17.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.11:31:17.88#ibcon#first serial, iclass 15, count 0 2006.201.11:31:17.88#ibcon#enter sib2, iclass 15, count 0 2006.201.11:31:17.88#ibcon#flushed, iclass 15, count 0 2006.201.11:31:17.88#ibcon#about to write, iclass 15, count 0 2006.201.11:31:17.88#ibcon#wrote, iclass 15, count 0 2006.201.11:31:17.88#ibcon#about to read 3, iclass 15, count 0 2006.201.11:31:17.92#ibcon#read 3, iclass 15, count 0 2006.201.11:31:17.92#ibcon#about to read 4, iclass 15, count 0 2006.201.11:31:17.92#ibcon#read 4, iclass 15, count 0 2006.201.11:31:17.92#ibcon#about to read 5, iclass 15, count 0 2006.201.11:31:17.92#ibcon#read 5, iclass 15, count 0 2006.201.11:31:17.92#ibcon#about to read 6, iclass 15, count 0 2006.201.11:31:17.92#ibcon#read 6, iclass 15, count 0 2006.201.11:31:17.92#ibcon#end of sib2, iclass 15, count 0 2006.201.11:31:17.92#ibcon#*mode == 0, iclass 15, count 0 2006.201.11:31:17.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.11:31:17.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:31:17.92#ibcon#*before write, iclass 15, count 0 2006.201.11:31:17.92#ibcon#enter sib2, iclass 15, count 0 2006.201.11:31:17.92#ibcon#flushed, iclass 15, count 0 2006.201.11:31:17.92#ibcon#about to write, iclass 15, count 0 2006.201.11:31:17.92#ibcon#wrote, iclass 15, count 0 2006.201.11:31:17.92#ibcon#about to read 3, iclass 15, count 0 2006.201.11:31:17.97#ibcon#read 3, iclass 15, count 0 2006.201.11:31:17.97#ibcon#about to read 4, iclass 15, count 0 2006.201.11:31:17.97#ibcon#read 4, iclass 15, count 0 2006.201.11:31:17.97#ibcon#about to read 5, iclass 15, count 0 2006.201.11:31:17.97#ibcon#read 5, iclass 15, count 0 2006.201.11:31:17.97#ibcon#about to read 6, iclass 15, count 0 2006.201.11:31:17.97#ibcon#read 6, iclass 15, count 0 2006.201.11:31:17.97#ibcon#end of sib2, iclass 15, count 0 2006.201.11:31:17.97#ibcon#*after write, iclass 15, count 0 2006.201.11:31:17.97#ibcon#*before return 0, iclass 15, count 0 2006.201.11:31:17.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:17.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:17.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.11:31:17.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.11:31:17.97$vck44/va=1,8 2006.201.11:31:17.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.11:31:17.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.11:31:17.97#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:17.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:17.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:17.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:17.97#ibcon#enter wrdev, iclass 17, count 2 2006.201.11:31:17.97#ibcon#first serial, iclass 17, count 2 2006.201.11:31:17.97#ibcon#enter sib2, iclass 17, count 2 2006.201.11:31:17.97#ibcon#flushed, iclass 17, count 2 2006.201.11:31:17.97#ibcon#about to write, iclass 17, count 2 2006.201.11:31:17.97#ibcon#wrote, iclass 17, count 2 2006.201.11:31:17.97#ibcon#about to read 3, iclass 17, count 2 2006.201.11:31:17.99#ibcon#read 3, iclass 17, count 2 2006.201.11:31:17.99#ibcon#about to read 4, iclass 17, count 2 2006.201.11:31:17.99#ibcon#read 4, iclass 17, count 2 2006.201.11:31:17.99#ibcon#about to read 5, iclass 17, count 2 2006.201.11:31:17.99#ibcon#read 5, iclass 17, count 2 2006.201.11:31:17.99#ibcon#about to read 6, iclass 17, count 2 2006.201.11:31:17.99#ibcon#read 6, iclass 17, count 2 2006.201.11:31:17.99#ibcon#end of sib2, iclass 17, count 2 2006.201.11:31:17.99#ibcon#*mode == 0, iclass 17, count 2 2006.201.11:31:17.99#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.11:31:17.99#ibcon#[25=AT01-08\r\n] 2006.201.11:31:17.99#ibcon#*before write, iclass 17, count 2 2006.201.11:31:17.99#ibcon#enter sib2, iclass 17, count 2 2006.201.11:31:17.99#ibcon#flushed, iclass 17, count 2 2006.201.11:31:17.99#ibcon#about to write, iclass 17, count 2 2006.201.11:31:17.99#ibcon#wrote, iclass 17, count 2 2006.201.11:31:17.99#ibcon#about to read 3, iclass 17, count 2 2006.201.11:31:18.03#ibcon#read 3, iclass 17, count 2 2006.201.11:31:18.03#ibcon#about to read 4, iclass 17, count 2 2006.201.11:31:18.03#ibcon#read 4, iclass 17, count 2 2006.201.11:31:18.03#ibcon#about to read 5, iclass 17, count 2 2006.201.11:31:18.03#ibcon#read 5, iclass 17, count 2 2006.201.11:31:18.03#ibcon#about to read 6, iclass 17, count 2 2006.201.11:31:18.03#ibcon#read 6, iclass 17, count 2 2006.201.11:31:18.03#ibcon#end of sib2, iclass 17, count 2 2006.201.11:31:18.03#ibcon#*after write, iclass 17, count 2 2006.201.11:31:18.03#ibcon#*before return 0, iclass 17, count 2 2006.201.11:31:18.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:18.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:18.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.11:31:18.03#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:18.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:18.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:18.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:18.15#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:31:18.15#ibcon#first serial, iclass 17, count 0 2006.201.11:31:18.15#ibcon#enter sib2, iclass 17, count 0 2006.201.11:31:18.15#ibcon#flushed, iclass 17, count 0 2006.201.11:31:18.15#ibcon#about to write, iclass 17, count 0 2006.201.11:31:18.15#ibcon#wrote, iclass 17, count 0 2006.201.11:31:18.15#ibcon#about to read 3, iclass 17, count 0 2006.201.11:31:18.17#ibcon#read 3, iclass 17, count 0 2006.201.11:31:18.17#ibcon#about to read 4, iclass 17, count 0 2006.201.11:31:18.17#ibcon#read 4, iclass 17, count 0 2006.201.11:31:18.17#ibcon#about to read 5, iclass 17, count 0 2006.201.11:31:18.17#ibcon#read 5, iclass 17, count 0 2006.201.11:31:18.17#ibcon#about to read 6, iclass 17, count 0 2006.201.11:31:18.17#ibcon#read 6, iclass 17, count 0 2006.201.11:31:18.17#ibcon#end of sib2, iclass 17, count 0 2006.201.11:31:18.17#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:31:18.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:31:18.17#ibcon#[25=USB\r\n] 2006.201.11:31:18.17#ibcon#*before write, iclass 17, count 0 2006.201.11:31:18.17#ibcon#enter sib2, iclass 17, count 0 2006.201.11:31:18.17#ibcon#flushed, iclass 17, count 0 2006.201.11:31:18.17#ibcon#about to write, iclass 17, count 0 2006.201.11:31:18.17#ibcon#wrote, iclass 17, count 0 2006.201.11:31:18.17#ibcon#about to read 3, iclass 17, count 0 2006.201.11:31:18.20#ibcon#read 3, iclass 17, count 0 2006.201.11:31:18.20#ibcon#about to read 4, iclass 17, count 0 2006.201.11:31:18.20#ibcon#read 4, iclass 17, count 0 2006.201.11:31:18.20#ibcon#about to read 5, iclass 17, count 0 2006.201.11:31:18.20#ibcon#read 5, iclass 17, count 0 2006.201.11:31:18.20#ibcon#about to read 6, iclass 17, count 0 2006.201.11:31:18.20#ibcon#read 6, iclass 17, count 0 2006.201.11:31:18.20#ibcon#end of sib2, iclass 17, count 0 2006.201.11:31:18.20#ibcon#*after write, iclass 17, count 0 2006.201.11:31:18.20#ibcon#*before return 0, iclass 17, count 0 2006.201.11:31:18.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:18.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:18.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:31:18.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:31:18.20$vck44/valo=2,534.99 2006.201.11:31:18.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.11:31:18.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.11:31:18.20#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:18.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:18.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:18.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:18.20#ibcon#enter wrdev, iclass 19, count 0 2006.201.11:31:18.20#ibcon#first serial, iclass 19, count 0 2006.201.11:31:18.20#ibcon#enter sib2, iclass 19, count 0 2006.201.11:31:18.20#ibcon#flushed, iclass 19, count 0 2006.201.11:31:18.20#ibcon#about to write, iclass 19, count 0 2006.201.11:31:18.20#ibcon#wrote, iclass 19, count 0 2006.201.11:31:18.20#ibcon#about to read 3, iclass 19, count 0 2006.201.11:31:18.22#ibcon#read 3, iclass 19, count 0 2006.201.11:31:18.22#ibcon#about to read 4, iclass 19, count 0 2006.201.11:31:18.22#ibcon#read 4, iclass 19, count 0 2006.201.11:31:18.22#ibcon#about to read 5, iclass 19, count 0 2006.201.11:31:18.22#ibcon#read 5, iclass 19, count 0 2006.201.11:31:18.22#ibcon#about to read 6, iclass 19, count 0 2006.201.11:31:18.22#ibcon#read 6, iclass 19, count 0 2006.201.11:31:18.22#ibcon#end of sib2, iclass 19, count 0 2006.201.11:31:18.22#ibcon#*mode == 0, iclass 19, count 0 2006.201.11:31:18.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.11:31:18.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:31:18.22#ibcon#*before write, iclass 19, count 0 2006.201.11:31:18.22#ibcon#enter sib2, iclass 19, count 0 2006.201.11:31:18.22#ibcon#flushed, iclass 19, count 0 2006.201.11:31:18.22#ibcon#about to write, iclass 19, count 0 2006.201.11:31:18.22#ibcon#wrote, iclass 19, count 0 2006.201.11:31:18.22#ibcon#about to read 3, iclass 19, count 0 2006.201.11:31:18.27#ibcon#read 3, iclass 19, count 0 2006.201.11:31:18.27#ibcon#about to read 4, iclass 19, count 0 2006.201.11:31:18.27#ibcon#read 4, iclass 19, count 0 2006.201.11:31:18.27#ibcon#about to read 5, iclass 19, count 0 2006.201.11:31:18.27#ibcon#read 5, iclass 19, count 0 2006.201.11:31:18.27#ibcon#about to read 6, iclass 19, count 0 2006.201.11:31:18.27#ibcon#read 6, iclass 19, count 0 2006.201.11:31:18.27#ibcon#end of sib2, iclass 19, count 0 2006.201.11:31:18.27#ibcon#*after write, iclass 19, count 0 2006.201.11:31:18.27#ibcon#*before return 0, iclass 19, count 0 2006.201.11:31:18.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:18.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:18.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.11:31:18.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.11:31:18.27$vck44/va=2,7 2006.201.11:31:18.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.11:31:18.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.11:31:18.27#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:18.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:18.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:18.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:18.32#ibcon#enter wrdev, iclass 21, count 2 2006.201.11:31:18.32#ibcon#first serial, iclass 21, count 2 2006.201.11:31:18.32#ibcon#enter sib2, iclass 21, count 2 2006.201.11:31:18.32#ibcon#flushed, iclass 21, count 2 2006.201.11:31:18.32#ibcon#about to write, iclass 21, count 2 2006.201.11:31:18.32#ibcon#wrote, iclass 21, count 2 2006.201.11:31:18.32#ibcon#about to read 3, iclass 21, count 2 2006.201.11:31:18.34#ibcon#read 3, iclass 21, count 2 2006.201.11:31:18.34#ibcon#about to read 4, iclass 21, count 2 2006.201.11:31:18.34#ibcon#read 4, iclass 21, count 2 2006.201.11:31:18.34#ibcon#about to read 5, iclass 21, count 2 2006.201.11:31:18.34#ibcon#read 5, iclass 21, count 2 2006.201.11:31:18.34#ibcon#about to read 6, iclass 21, count 2 2006.201.11:31:18.34#ibcon#read 6, iclass 21, count 2 2006.201.11:31:18.34#ibcon#end of sib2, iclass 21, count 2 2006.201.11:31:18.34#ibcon#*mode == 0, iclass 21, count 2 2006.201.11:31:18.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.11:31:18.34#ibcon#[25=AT02-07\r\n] 2006.201.11:31:18.34#ibcon#*before write, iclass 21, count 2 2006.201.11:31:18.34#ibcon#enter sib2, iclass 21, count 2 2006.201.11:31:18.34#ibcon#flushed, iclass 21, count 2 2006.201.11:31:18.34#ibcon#about to write, iclass 21, count 2 2006.201.11:31:18.34#ibcon#wrote, iclass 21, count 2 2006.201.11:31:18.34#ibcon#about to read 3, iclass 21, count 2 2006.201.11:31:18.37#ibcon#read 3, iclass 21, count 2 2006.201.11:31:18.37#ibcon#about to read 4, iclass 21, count 2 2006.201.11:31:18.37#ibcon#read 4, iclass 21, count 2 2006.201.11:31:18.37#ibcon#about to read 5, iclass 21, count 2 2006.201.11:31:18.37#ibcon#read 5, iclass 21, count 2 2006.201.11:31:18.37#ibcon#about to read 6, iclass 21, count 2 2006.201.11:31:18.37#ibcon#read 6, iclass 21, count 2 2006.201.11:31:18.37#ibcon#end of sib2, iclass 21, count 2 2006.201.11:31:18.37#ibcon#*after write, iclass 21, count 2 2006.201.11:31:18.37#ibcon#*before return 0, iclass 21, count 2 2006.201.11:31:18.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:18.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:18.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.11:31:18.37#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:18.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:18.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:18.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:18.49#ibcon#enter wrdev, iclass 21, count 0 2006.201.11:31:18.49#ibcon#first serial, iclass 21, count 0 2006.201.11:31:18.49#ibcon#enter sib2, iclass 21, count 0 2006.201.11:31:18.49#ibcon#flushed, iclass 21, count 0 2006.201.11:31:18.49#ibcon#about to write, iclass 21, count 0 2006.201.11:31:18.49#ibcon#wrote, iclass 21, count 0 2006.201.11:31:18.49#ibcon#about to read 3, iclass 21, count 0 2006.201.11:31:18.51#ibcon#read 3, iclass 21, count 0 2006.201.11:31:18.51#ibcon#about to read 4, iclass 21, count 0 2006.201.11:31:18.51#ibcon#read 4, iclass 21, count 0 2006.201.11:31:18.51#ibcon#about to read 5, iclass 21, count 0 2006.201.11:31:18.51#ibcon#read 5, iclass 21, count 0 2006.201.11:31:18.51#ibcon#about to read 6, iclass 21, count 0 2006.201.11:31:18.51#ibcon#read 6, iclass 21, count 0 2006.201.11:31:18.51#ibcon#end of sib2, iclass 21, count 0 2006.201.11:31:18.51#ibcon#*mode == 0, iclass 21, count 0 2006.201.11:31:18.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.11:31:18.51#ibcon#[25=USB\r\n] 2006.201.11:31:18.51#ibcon#*before write, iclass 21, count 0 2006.201.11:31:18.51#ibcon#enter sib2, iclass 21, count 0 2006.201.11:31:18.51#ibcon#flushed, iclass 21, count 0 2006.201.11:31:18.51#ibcon#about to write, iclass 21, count 0 2006.201.11:31:18.51#ibcon#wrote, iclass 21, count 0 2006.201.11:31:18.51#ibcon#about to read 3, iclass 21, count 0 2006.201.11:31:18.54#ibcon#read 3, iclass 21, count 0 2006.201.11:31:18.54#ibcon#about to read 4, iclass 21, count 0 2006.201.11:31:18.54#ibcon#read 4, iclass 21, count 0 2006.201.11:31:18.54#ibcon#about to read 5, iclass 21, count 0 2006.201.11:31:18.54#ibcon#read 5, iclass 21, count 0 2006.201.11:31:18.54#ibcon#about to read 6, iclass 21, count 0 2006.201.11:31:18.54#ibcon#read 6, iclass 21, count 0 2006.201.11:31:18.54#ibcon#end of sib2, iclass 21, count 0 2006.201.11:31:18.54#ibcon#*after write, iclass 21, count 0 2006.201.11:31:18.54#ibcon#*before return 0, iclass 21, count 0 2006.201.11:31:18.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:18.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:18.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.11:31:18.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.11:31:18.54$vck44/valo=3,564.99 2006.201.11:31:18.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.11:31:18.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.11:31:18.54#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:18.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:18.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:18.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:18.54#ibcon#enter wrdev, iclass 23, count 0 2006.201.11:31:18.54#ibcon#first serial, iclass 23, count 0 2006.201.11:31:18.54#ibcon#enter sib2, iclass 23, count 0 2006.201.11:31:18.54#ibcon#flushed, iclass 23, count 0 2006.201.11:31:18.54#ibcon#about to write, iclass 23, count 0 2006.201.11:31:18.54#ibcon#wrote, iclass 23, count 0 2006.201.11:31:18.54#ibcon#about to read 3, iclass 23, count 0 2006.201.11:31:18.56#ibcon#read 3, iclass 23, count 0 2006.201.11:31:18.56#ibcon#about to read 4, iclass 23, count 0 2006.201.11:31:18.56#ibcon#read 4, iclass 23, count 0 2006.201.11:31:18.56#ibcon#about to read 5, iclass 23, count 0 2006.201.11:31:18.56#ibcon#read 5, iclass 23, count 0 2006.201.11:31:18.56#ibcon#about to read 6, iclass 23, count 0 2006.201.11:31:18.56#ibcon#read 6, iclass 23, count 0 2006.201.11:31:18.56#ibcon#end of sib2, iclass 23, count 0 2006.201.11:31:18.56#ibcon#*mode == 0, iclass 23, count 0 2006.201.11:31:18.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.11:31:18.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:31:18.56#ibcon#*before write, iclass 23, count 0 2006.201.11:31:18.56#ibcon#enter sib2, iclass 23, count 0 2006.201.11:31:18.56#ibcon#flushed, iclass 23, count 0 2006.201.11:31:18.56#ibcon#about to write, iclass 23, count 0 2006.201.11:31:18.56#ibcon#wrote, iclass 23, count 0 2006.201.11:31:18.56#ibcon#about to read 3, iclass 23, count 0 2006.201.11:31:18.60#ibcon#read 3, iclass 23, count 0 2006.201.11:31:18.60#ibcon#about to read 4, iclass 23, count 0 2006.201.11:31:18.60#ibcon#read 4, iclass 23, count 0 2006.201.11:31:18.60#ibcon#about to read 5, iclass 23, count 0 2006.201.11:31:18.60#ibcon#read 5, iclass 23, count 0 2006.201.11:31:18.60#ibcon#about to read 6, iclass 23, count 0 2006.201.11:31:18.60#ibcon#read 6, iclass 23, count 0 2006.201.11:31:18.60#ibcon#end of sib2, iclass 23, count 0 2006.201.11:31:18.60#ibcon#*after write, iclass 23, count 0 2006.201.11:31:18.60#ibcon#*before return 0, iclass 23, count 0 2006.201.11:31:18.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:18.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:18.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.11:31:18.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.11:31:18.60$vck44/va=3,8 2006.201.11:31:18.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.11:31:18.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.11:31:18.60#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:18.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:18.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:18.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:18.66#ibcon#enter wrdev, iclass 25, count 2 2006.201.11:31:18.66#ibcon#first serial, iclass 25, count 2 2006.201.11:31:18.66#ibcon#enter sib2, iclass 25, count 2 2006.201.11:31:18.66#ibcon#flushed, iclass 25, count 2 2006.201.11:31:18.66#ibcon#about to write, iclass 25, count 2 2006.201.11:31:18.66#ibcon#wrote, iclass 25, count 2 2006.201.11:31:18.66#ibcon#about to read 3, iclass 25, count 2 2006.201.11:31:18.68#ibcon#read 3, iclass 25, count 2 2006.201.11:31:18.68#ibcon#about to read 4, iclass 25, count 2 2006.201.11:31:18.68#ibcon#read 4, iclass 25, count 2 2006.201.11:31:18.68#ibcon#about to read 5, iclass 25, count 2 2006.201.11:31:18.68#ibcon#read 5, iclass 25, count 2 2006.201.11:31:18.68#ibcon#about to read 6, iclass 25, count 2 2006.201.11:31:18.68#ibcon#read 6, iclass 25, count 2 2006.201.11:31:18.68#ibcon#end of sib2, iclass 25, count 2 2006.201.11:31:18.68#ibcon#*mode == 0, iclass 25, count 2 2006.201.11:31:18.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.11:31:18.68#ibcon#[25=AT03-08\r\n] 2006.201.11:31:18.68#ibcon#*before write, iclass 25, count 2 2006.201.11:31:18.68#ibcon#enter sib2, iclass 25, count 2 2006.201.11:31:18.68#ibcon#flushed, iclass 25, count 2 2006.201.11:31:18.68#ibcon#about to write, iclass 25, count 2 2006.201.11:31:18.68#ibcon#wrote, iclass 25, count 2 2006.201.11:31:18.68#ibcon#about to read 3, iclass 25, count 2 2006.201.11:31:18.71#ibcon#read 3, iclass 25, count 2 2006.201.11:31:18.71#ibcon#about to read 4, iclass 25, count 2 2006.201.11:31:18.71#ibcon#read 4, iclass 25, count 2 2006.201.11:31:18.71#ibcon#about to read 5, iclass 25, count 2 2006.201.11:31:18.71#ibcon#read 5, iclass 25, count 2 2006.201.11:31:18.71#ibcon#about to read 6, iclass 25, count 2 2006.201.11:31:18.71#ibcon#read 6, iclass 25, count 2 2006.201.11:31:18.71#ibcon#end of sib2, iclass 25, count 2 2006.201.11:31:18.71#ibcon#*after write, iclass 25, count 2 2006.201.11:31:18.71#ibcon#*before return 0, iclass 25, count 2 2006.201.11:31:18.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:18.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:18.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.11:31:18.71#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:18.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:18.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:18.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:18.83#ibcon#enter wrdev, iclass 25, count 0 2006.201.11:31:18.83#ibcon#first serial, iclass 25, count 0 2006.201.11:31:18.83#ibcon#enter sib2, iclass 25, count 0 2006.201.11:31:18.83#ibcon#flushed, iclass 25, count 0 2006.201.11:31:18.83#ibcon#about to write, iclass 25, count 0 2006.201.11:31:18.83#ibcon#wrote, iclass 25, count 0 2006.201.11:31:18.83#ibcon#about to read 3, iclass 25, count 0 2006.201.11:31:18.85#ibcon#read 3, iclass 25, count 0 2006.201.11:31:18.85#ibcon#about to read 4, iclass 25, count 0 2006.201.11:31:18.85#ibcon#read 4, iclass 25, count 0 2006.201.11:31:18.85#ibcon#about to read 5, iclass 25, count 0 2006.201.11:31:18.85#ibcon#read 5, iclass 25, count 0 2006.201.11:31:18.85#ibcon#about to read 6, iclass 25, count 0 2006.201.11:31:18.85#ibcon#read 6, iclass 25, count 0 2006.201.11:31:18.85#ibcon#end of sib2, iclass 25, count 0 2006.201.11:31:18.85#ibcon#*mode == 0, iclass 25, count 0 2006.201.11:31:18.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.11:31:18.85#ibcon#[25=USB\r\n] 2006.201.11:31:18.85#ibcon#*before write, iclass 25, count 0 2006.201.11:31:18.85#ibcon#enter sib2, iclass 25, count 0 2006.201.11:31:18.85#ibcon#flushed, iclass 25, count 0 2006.201.11:31:18.85#ibcon#about to write, iclass 25, count 0 2006.201.11:31:18.85#ibcon#wrote, iclass 25, count 0 2006.201.11:31:18.85#ibcon#about to read 3, iclass 25, count 0 2006.201.11:31:18.88#ibcon#read 3, iclass 25, count 0 2006.201.11:31:18.88#ibcon#about to read 4, iclass 25, count 0 2006.201.11:31:18.88#ibcon#read 4, iclass 25, count 0 2006.201.11:31:18.88#ibcon#about to read 5, iclass 25, count 0 2006.201.11:31:18.88#ibcon#read 5, iclass 25, count 0 2006.201.11:31:18.88#ibcon#about to read 6, iclass 25, count 0 2006.201.11:31:18.88#ibcon#read 6, iclass 25, count 0 2006.201.11:31:18.88#ibcon#end of sib2, iclass 25, count 0 2006.201.11:31:18.88#ibcon#*after write, iclass 25, count 0 2006.201.11:31:18.88#ibcon#*before return 0, iclass 25, count 0 2006.201.11:31:18.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:18.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:18.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.11:31:18.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.11:31:18.88$vck44/valo=4,624.99 2006.201.11:31:18.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.11:31:18.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.11:31:18.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:18.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:18.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:18.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:18.88#ibcon#enter wrdev, iclass 27, count 0 2006.201.11:31:18.88#ibcon#first serial, iclass 27, count 0 2006.201.11:31:18.88#ibcon#enter sib2, iclass 27, count 0 2006.201.11:31:18.88#ibcon#flushed, iclass 27, count 0 2006.201.11:31:18.88#ibcon#about to write, iclass 27, count 0 2006.201.11:31:18.88#ibcon#wrote, iclass 27, count 0 2006.201.11:31:18.88#ibcon#about to read 3, iclass 27, count 0 2006.201.11:31:18.90#ibcon#read 3, iclass 27, count 0 2006.201.11:31:18.90#ibcon#about to read 4, iclass 27, count 0 2006.201.11:31:18.90#ibcon#read 4, iclass 27, count 0 2006.201.11:31:18.90#ibcon#about to read 5, iclass 27, count 0 2006.201.11:31:18.90#ibcon#read 5, iclass 27, count 0 2006.201.11:31:18.90#ibcon#about to read 6, iclass 27, count 0 2006.201.11:31:18.90#ibcon#read 6, iclass 27, count 0 2006.201.11:31:18.90#ibcon#end of sib2, iclass 27, count 0 2006.201.11:31:18.90#ibcon#*mode == 0, iclass 27, count 0 2006.201.11:31:18.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.11:31:18.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:31:18.90#ibcon#*before write, iclass 27, count 0 2006.201.11:31:18.90#ibcon#enter sib2, iclass 27, count 0 2006.201.11:31:18.90#ibcon#flushed, iclass 27, count 0 2006.201.11:31:18.90#ibcon#about to write, iclass 27, count 0 2006.201.11:31:18.90#ibcon#wrote, iclass 27, count 0 2006.201.11:31:18.90#ibcon#about to read 3, iclass 27, count 0 2006.201.11:31:18.94#ibcon#read 3, iclass 27, count 0 2006.201.11:31:18.94#ibcon#about to read 4, iclass 27, count 0 2006.201.11:31:18.94#ibcon#read 4, iclass 27, count 0 2006.201.11:31:18.94#ibcon#about to read 5, iclass 27, count 0 2006.201.11:31:18.94#ibcon#read 5, iclass 27, count 0 2006.201.11:31:18.94#ibcon#about to read 6, iclass 27, count 0 2006.201.11:31:18.94#ibcon#read 6, iclass 27, count 0 2006.201.11:31:18.94#ibcon#end of sib2, iclass 27, count 0 2006.201.11:31:18.94#ibcon#*after write, iclass 27, count 0 2006.201.11:31:18.94#ibcon#*before return 0, iclass 27, count 0 2006.201.11:31:18.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:18.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:18.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.11:31:18.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.11:31:18.94$vck44/va=4,7 2006.201.11:31:18.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.11:31:18.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.11:31:18.94#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:18.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:19.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:19.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:19.00#ibcon#enter wrdev, iclass 29, count 2 2006.201.11:31:19.00#ibcon#first serial, iclass 29, count 2 2006.201.11:31:19.00#ibcon#enter sib2, iclass 29, count 2 2006.201.11:31:19.00#ibcon#flushed, iclass 29, count 2 2006.201.11:31:19.00#ibcon#about to write, iclass 29, count 2 2006.201.11:31:19.00#ibcon#wrote, iclass 29, count 2 2006.201.11:31:19.00#ibcon#about to read 3, iclass 29, count 2 2006.201.11:31:19.02#ibcon#read 3, iclass 29, count 2 2006.201.11:31:19.02#ibcon#about to read 4, iclass 29, count 2 2006.201.11:31:19.02#ibcon#read 4, iclass 29, count 2 2006.201.11:31:19.02#ibcon#about to read 5, iclass 29, count 2 2006.201.11:31:19.02#ibcon#read 5, iclass 29, count 2 2006.201.11:31:19.02#ibcon#about to read 6, iclass 29, count 2 2006.201.11:31:19.02#ibcon#read 6, iclass 29, count 2 2006.201.11:31:19.02#ibcon#end of sib2, iclass 29, count 2 2006.201.11:31:19.02#ibcon#*mode == 0, iclass 29, count 2 2006.201.11:31:19.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.11:31:19.02#ibcon#[25=AT04-07\r\n] 2006.201.11:31:19.02#ibcon#*before write, iclass 29, count 2 2006.201.11:31:19.02#ibcon#enter sib2, iclass 29, count 2 2006.201.11:31:19.02#ibcon#flushed, iclass 29, count 2 2006.201.11:31:19.02#ibcon#about to write, iclass 29, count 2 2006.201.11:31:19.02#ibcon#wrote, iclass 29, count 2 2006.201.11:31:19.02#ibcon#about to read 3, iclass 29, count 2 2006.201.11:31:19.05#ibcon#read 3, iclass 29, count 2 2006.201.11:31:19.05#ibcon#about to read 4, iclass 29, count 2 2006.201.11:31:19.05#ibcon#read 4, iclass 29, count 2 2006.201.11:31:19.05#ibcon#about to read 5, iclass 29, count 2 2006.201.11:31:19.05#ibcon#read 5, iclass 29, count 2 2006.201.11:31:19.05#ibcon#about to read 6, iclass 29, count 2 2006.201.11:31:19.05#ibcon#read 6, iclass 29, count 2 2006.201.11:31:19.05#ibcon#end of sib2, iclass 29, count 2 2006.201.11:31:19.05#ibcon#*after write, iclass 29, count 2 2006.201.11:31:19.05#ibcon#*before return 0, iclass 29, count 2 2006.201.11:31:19.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:19.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:19.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.11:31:19.05#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:19.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:19.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:19.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:19.17#ibcon#enter wrdev, iclass 29, count 0 2006.201.11:31:19.17#ibcon#first serial, iclass 29, count 0 2006.201.11:31:19.17#ibcon#enter sib2, iclass 29, count 0 2006.201.11:31:19.17#ibcon#flushed, iclass 29, count 0 2006.201.11:31:19.17#ibcon#about to write, iclass 29, count 0 2006.201.11:31:19.17#ibcon#wrote, iclass 29, count 0 2006.201.11:31:19.17#ibcon#about to read 3, iclass 29, count 0 2006.201.11:31:19.19#ibcon#read 3, iclass 29, count 0 2006.201.11:31:19.19#ibcon#about to read 4, iclass 29, count 0 2006.201.11:31:19.19#ibcon#read 4, iclass 29, count 0 2006.201.11:31:19.19#ibcon#about to read 5, iclass 29, count 0 2006.201.11:31:19.19#ibcon#read 5, iclass 29, count 0 2006.201.11:31:19.19#ibcon#about to read 6, iclass 29, count 0 2006.201.11:31:19.19#ibcon#read 6, iclass 29, count 0 2006.201.11:31:19.19#ibcon#end of sib2, iclass 29, count 0 2006.201.11:31:19.19#ibcon#*mode == 0, iclass 29, count 0 2006.201.11:31:19.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.11:31:19.19#ibcon#[25=USB\r\n] 2006.201.11:31:19.19#ibcon#*before write, iclass 29, count 0 2006.201.11:31:19.19#ibcon#enter sib2, iclass 29, count 0 2006.201.11:31:19.19#ibcon#flushed, iclass 29, count 0 2006.201.11:31:19.19#ibcon#about to write, iclass 29, count 0 2006.201.11:31:19.19#ibcon#wrote, iclass 29, count 0 2006.201.11:31:19.19#ibcon#about to read 3, iclass 29, count 0 2006.201.11:31:19.22#ibcon#read 3, iclass 29, count 0 2006.201.11:31:19.22#ibcon#about to read 4, iclass 29, count 0 2006.201.11:31:19.22#ibcon#read 4, iclass 29, count 0 2006.201.11:31:19.22#ibcon#about to read 5, iclass 29, count 0 2006.201.11:31:19.22#ibcon#read 5, iclass 29, count 0 2006.201.11:31:19.22#ibcon#about to read 6, iclass 29, count 0 2006.201.11:31:19.22#ibcon#read 6, iclass 29, count 0 2006.201.11:31:19.22#ibcon#end of sib2, iclass 29, count 0 2006.201.11:31:19.22#ibcon#*after write, iclass 29, count 0 2006.201.11:31:19.22#ibcon#*before return 0, iclass 29, count 0 2006.201.11:31:19.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:19.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:19.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.11:31:19.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.11:31:19.22$vck44/valo=5,734.99 2006.201.11:31:19.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.11:31:19.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.11:31:19.22#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:19.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:19.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:19.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:19.22#ibcon#enter wrdev, iclass 31, count 0 2006.201.11:31:19.22#ibcon#first serial, iclass 31, count 0 2006.201.11:31:19.22#ibcon#enter sib2, iclass 31, count 0 2006.201.11:31:19.22#ibcon#flushed, iclass 31, count 0 2006.201.11:31:19.22#ibcon#about to write, iclass 31, count 0 2006.201.11:31:19.22#ibcon#wrote, iclass 31, count 0 2006.201.11:31:19.22#ibcon#about to read 3, iclass 31, count 0 2006.201.11:31:19.24#ibcon#read 3, iclass 31, count 0 2006.201.11:31:19.24#ibcon#about to read 4, iclass 31, count 0 2006.201.11:31:19.24#ibcon#read 4, iclass 31, count 0 2006.201.11:31:19.24#ibcon#about to read 5, iclass 31, count 0 2006.201.11:31:19.24#ibcon#read 5, iclass 31, count 0 2006.201.11:31:19.24#ibcon#about to read 6, iclass 31, count 0 2006.201.11:31:19.24#ibcon#read 6, iclass 31, count 0 2006.201.11:31:19.24#ibcon#end of sib2, iclass 31, count 0 2006.201.11:31:19.24#ibcon#*mode == 0, iclass 31, count 0 2006.201.11:31:19.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.11:31:19.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:31:19.24#ibcon#*before write, iclass 31, count 0 2006.201.11:31:19.24#ibcon#enter sib2, iclass 31, count 0 2006.201.11:31:19.24#ibcon#flushed, iclass 31, count 0 2006.201.11:31:19.24#ibcon#about to write, iclass 31, count 0 2006.201.11:31:19.24#ibcon#wrote, iclass 31, count 0 2006.201.11:31:19.24#ibcon#about to read 3, iclass 31, count 0 2006.201.11:31:19.28#ibcon#read 3, iclass 31, count 0 2006.201.11:31:19.28#ibcon#about to read 4, iclass 31, count 0 2006.201.11:31:19.28#ibcon#read 4, iclass 31, count 0 2006.201.11:31:19.28#ibcon#about to read 5, iclass 31, count 0 2006.201.11:31:19.28#ibcon#read 5, iclass 31, count 0 2006.201.11:31:19.28#ibcon#about to read 6, iclass 31, count 0 2006.201.11:31:19.28#ibcon#read 6, iclass 31, count 0 2006.201.11:31:19.28#ibcon#end of sib2, iclass 31, count 0 2006.201.11:31:19.28#ibcon#*after write, iclass 31, count 0 2006.201.11:31:19.28#ibcon#*before return 0, iclass 31, count 0 2006.201.11:31:19.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:19.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:19.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.11:31:19.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.11:31:19.28$vck44/va=5,4 2006.201.11:31:19.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.11:31:19.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.11:31:19.28#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:19.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:19.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:19.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:19.34#ibcon#enter wrdev, iclass 33, count 2 2006.201.11:31:19.34#ibcon#first serial, iclass 33, count 2 2006.201.11:31:19.34#ibcon#enter sib2, iclass 33, count 2 2006.201.11:31:19.34#ibcon#flushed, iclass 33, count 2 2006.201.11:31:19.34#ibcon#about to write, iclass 33, count 2 2006.201.11:31:19.34#ibcon#wrote, iclass 33, count 2 2006.201.11:31:19.34#ibcon#about to read 3, iclass 33, count 2 2006.201.11:31:19.36#ibcon#read 3, iclass 33, count 2 2006.201.11:31:19.36#ibcon#about to read 4, iclass 33, count 2 2006.201.11:31:19.36#ibcon#read 4, iclass 33, count 2 2006.201.11:31:19.36#ibcon#about to read 5, iclass 33, count 2 2006.201.11:31:19.36#ibcon#read 5, iclass 33, count 2 2006.201.11:31:19.36#ibcon#about to read 6, iclass 33, count 2 2006.201.11:31:19.36#ibcon#read 6, iclass 33, count 2 2006.201.11:31:19.36#ibcon#end of sib2, iclass 33, count 2 2006.201.11:31:19.36#ibcon#*mode == 0, iclass 33, count 2 2006.201.11:31:19.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.11:31:19.36#ibcon#[25=AT05-04\r\n] 2006.201.11:31:19.36#ibcon#*before write, iclass 33, count 2 2006.201.11:31:19.36#ibcon#enter sib2, iclass 33, count 2 2006.201.11:31:19.36#ibcon#flushed, iclass 33, count 2 2006.201.11:31:19.36#ibcon#about to write, iclass 33, count 2 2006.201.11:31:19.36#ibcon#wrote, iclass 33, count 2 2006.201.11:31:19.36#ibcon#about to read 3, iclass 33, count 2 2006.201.11:31:19.39#ibcon#read 3, iclass 33, count 2 2006.201.11:31:19.39#ibcon#about to read 4, iclass 33, count 2 2006.201.11:31:19.39#ibcon#read 4, iclass 33, count 2 2006.201.11:31:19.39#ibcon#about to read 5, iclass 33, count 2 2006.201.11:31:19.39#ibcon#read 5, iclass 33, count 2 2006.201.11:31:19.39#ibcon#about to read 6, iclass 33, count 2 2006.201.11:31:19.39#ibcon#read 6, iclass 33, count 2 2006.201.11:31:19.39#ibcon#end of sib2, iclass 33, count 2 2006.201.11:31:19.39#ibcon#*after write, iclass 33, count 2 2006.201.11:31:19.39#ibcon#*before return 0, iclass 33, count 2 2006.201.11:31:19.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:19.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:19.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.11:31:19.39#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:19.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:19.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:19.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:19.51#ibcon#enter wrdev, iclass 33, count 0 2006.201.11:31:19.51#ibcon#first serial, iclass 33, count 0 2006.201.11:31:19.51#ibcon#enter sib2, iclass 33, count 0 2006.201.11:31:19.51#ibcon#flushed, iclass 33, count 0 2006.201.11:31:19.51#ibcon#about to write, iclass 33, count 0 2006.201.11:31:19.51#ibcon#wrote, iclass 33, count 0 2006.201.11:31:19.51#ibcon#about to read 3, iclass 33, count 0 2006.201.11:31:19.53#ibcon#read 3, iclass 33, count 0 2006.201.11:31:19.53#ibcon#about to read 4, iclass 33, count 0 2006.201.11:31:19.53#ibcon#read 4, iclass 33, count 0 2006.201.11:31:19.53#ibcon#about to read 5, iclass 33, count 0 2006.201.11:31:19.53#ibcon#read 5, iclass 33, count 0 2006.201.11:31:19.53#ibcon#about to read 6, iclass 33, count 0 2006.201.11:31:19.53#ibcon#read 6, iclass 33, count 0 2006.201.11:31:19.53#ibcon#end of sib2, iclass 33, count 0 2006.201.11:31:19.53#ibcon#*mode == 0, iclass 33, count 0 2006.201.11:31:19.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.11:31:19.53#ibcon#[25=USB\r\n] 2006.201.11:31:19.53#ibcon#*before write, iclass 33, count 0 2006.201.11:31:19.53#ibcon#enter sib2, iclass 33, count 0 2006.201.11:31:19.53#ibcon#flushed, iclass 33, count 0 2006.201.11:31:19.53#ibcon#about to write, iclass 33, count 0 2006.201.11:31:19.53#ibcon#wrote, iclass 33, count 0 2006.201.11:31:19.53#ibcon#about to read 3, iclass 33, count 0 2006.201.11:31:19.56#ibcon#read 3, iclass 33, count 0 2006.201.11:31:19.56#ibcon#about to read 4, iclass 33, count 0 2006.201.11:31:19.56#ibcon#read 4, iclass 33, count 0 2006.201.11:31:19.56#ibcon#about to read 5, iclass 33, count 0 2006.201.11:31:19.56#ibcon#read 5, iclass 33, count 0 2006.201.11:31:19.56#ibcon#about to read 6, iclass 33, count 0 2006.201.11:31:19.56#ibcon#read 6, iclass 33, count 0 2006.201.11:31:19.56#ibcon#end of sib2, iclass 33, count 0 2006.201.11:31:19.56#ibcon#*after write, iclass 33, count 0 2006.201.11:31:19.56#ibcon#*before return 0, iclass 33, count 0 2006.201.11:31:19.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:19.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:19.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.11:31:19.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.11:31:19.56$vck44/valo=6,814.99 2006.201.11:31:19.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.11:31:19.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.11:31:19.56#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:19.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:19.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:19.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:19.56#ibcon#enter wrdev, iclass 35, count 0 2006.201.11:31:19.56#ibcon#first serial, iclass 35, count 0 2006.201.11:31:19.56#ibcon#enter sib2, iclass 35, count 0 2006.201.11:31:19.56#ibcon#flushed, iclass 35, count 0 2006.201.11:31:19.56#ibcon#about to write, iclass 35, count 0 2006.201.11:31:19.56#ibcon#wrote, iclass 35, count 0 2006.201.11:31:19.56#ibcon#about to read 3, iclass 35, count 0 2006.201.11:31:19.58#ibcon#read 3, iclass 35, count 0 2006.201.11:31:19.58#ibcon#about to read 4, iclass 35, count 0 2006.201.11:31:19.58#ibcon#read 4, iclass 35, count 0 2006.201.11:31:19.58#ibcon#about to read 5, iclass 35, count 0 2006.201.11:31:19.58#ibcon#read 5, iclass 35, count 0 2006.201.11:31:19.58#ibcon#about to read 6, iclass 35, count 0 2006.201.11:31:19.58#ibcon#read 6, iclass 35, count 0 2006.201.11:31:19.58#ibcon#end of sib2, iclass 35, count 0 2006.201.11:31:19.58#ibcon#*mode == 0, iclass 35, count 0 2006.201.11:31:19.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.11:31:19.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:31:19.58#ibcon#*before write, iclass 35, count 0 2006.201.11:31:19.58#ibcon#enter sib2, iclass 35, count 0 2006.201.11:31:19.58#ibcon#flushed, iclass 35, count 0 2006.201.11:31:19.58#ibcon#about to write, iclass 35, count 0 2006.201.11:31:19.58#ibcon#wrote, iclass 35, count 0 2006.201.11:31:19.58#ibcon#about to read 3, iclass 35, count 0 2006.201.11:31:19.62#ibcon#read 3, iclass 35, count 0 2006.201.11:31:19.62#ibcon#about to read 4, iclass 35, count 0 2006.201.11:31:19.62#ibcon#read 4, iclass 35, count 0 2006.201.11:31:19.62#ibcon#about to read 5, iclass 35, count 0 2006.201.11:31:19.62#ibcon#read 5, iclass 35, count 0 2006.201.11:31:19.62#ibcon#about to read 6, iclass 35, count 0 2006.201.11:31:19.62#ibcon#read 6, iclass 35, count 0 2006.201.11:31:19.62#ibcon#end of sib2, iclass 35, count 0 2006.201.11:31:19.62#ibcon#*after write, iclass 35, count 0 2006.201.11:31:19.62#ibcon#*before return 0, iclass 35, count 0 2006.201.11:31:19.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:19.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:19.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.11:31:19.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.11:31:19.62$vck44/va=6,5 2006.201.11:31:19.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.11:31:19.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.11:31:19.62#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:19.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:19.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:19.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:19.68#ibcon#enter wrdev, iclass 37, count 2 2006.201.11:31:19.68#ibcon#first serial, iclass 37, count 2 2006.201.11:31:19.68#ibcon#enter sib2, iclass 37, count 2 2006.201.11:31:19.68#ibcon#flushed, iclass 37, count 2 2006.201.11:31:19.68#ibcon#about to write, iclass 37, count 2 2006.201.11:31:19.68#ibcon#wrote, iclass 37, count 2 2006.201.11:31:19.68#ibcon#about to read 3, iclass 37, count 2 2006.201.11:31:19.70#ibcon#read 3, iclass 37, count 2 2006.201.11:31:19.70#ibcon#about to read 4, iclass 37, count 2 2006.201.11:31:19.70#ibcon#read 4, iclass 37, count 2 2006.201.11:31:19.70#ibcon#about to read 5, iclass 37, count 2 2006.201.11:31:19.70#ibcon#read 5, iclass 37, count 2 2006.201.11:31:19.70#ibcon#about to read 6, iclass 37, count 2 2006.201.11:31:19.70#ibcon#read 6, iclass 37, count 2 2006.201.11:31:19.70#ibcon#end of sib2, iclass 37, count 2 2006.201.11:31:19.70#ibcon#*mode == 0, iclass 37, count 2 2006.201.11:31:19.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.11:31:19.70#ibcon#[25=AT06-05\r\n] 2006.201.11:31:19.70#ibcon#*before write, iclass 37, count 2 2006.201.11:31:19.70#ibcon#enter sib2, iclass 37, count 2 2006.201.11:31:19.70#ibcon#flushed, iclass 37, count 2 2006.201.11:31:19.70#ibcon#about to write, iclass 37, count 2 2006.201.11:31:19.70#ibcon#wrote, iclass 37, count 2 2006.201.11:31:19.70#ibcon#about to read 3, iclass 37, count 2 2006.201.11:31:19.73#ibcon#read 3, iclass 37, count 2 2006.201.11:31:19.73#ibcon#about to read 4, iclass 37, count 2 2006.201.11:31:19.73#ibcon#read 4, iclass 37, count 2 2006.201.11:31:19.73#ibcon#about to read 5, iclass 37, count 2 2006.201.11:31:19.73#ibcon#read 5, iclass 37, count 2 2006.201.11:31:19.73#ibcon#about to read 6, iclass 37, count 2 2006.201.11:31:19.73#ibcon#read 6, iclass 37, count 2 2006.201.11:31:19.73#ibcon#end of sib2, iclass 37, count 2 2006.201.11:31:19.73#ibcon#*after write, iclass 37, count 2 2006.201.11:31:19.73#ibcon#*before return 0, iclass 37, count 2 2006.201.11:31:19.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:19.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:19.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.11:31:19.73#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:19.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:19.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:19.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:19.85#ibcon#enter wrdev, iclass 37, count 0 2006.201.11:31:19.85#ibcon#first serial, iclass 37, count 0 2006.201.11:31:19.85#ibcon#enter sib2, iclass 37, count 0 2006.201.11:31:19.85#ibcon#flushed, iclass 37, count 0 2006.201.11:31:19.85#ibcon#about to write, iclass 37, count 0 2006.201.11:31:19.85#ibcon#wrote, iclass 37, count 0 2006.201.11:31:19.85#ibcon#about to read 3, iclass 37, count 0 2006.201.11:31:19.87#ibcon#read 3, iclass 37, count 0 2006.201.11:31:19.87#ibcon#about to read 4, iclass 37, count 0 2006.201.11:31:19.87#ibcon#read 4, iclass 37, count 0 2006.201.11:31:19.87#ibcon#about to read 5, iclass 37, count 0 2006.201.11:31:19.87#ibcon#read 5, iclass 37, count 0 2006.201.11:31:19.87#ibcon#about to read 6, iclass 37, count 0 2006.201.11:31:19.87#ibcon#read 6, iclass 37, count 0 2006.201.11:31:19.87#ibcon#end of sib2, iclass 37, count 0 2006.201.11:31:19.87#ibcon#*mode == 0, iclass 37, count 0 2006.201.11:31:19.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.11:31:19.87#ibcon#[25=USB\r\n] 2006.201.11:31:19.87#ibcon#*before write, iclass 37, count 0 2006.201.11:31:19.87#ibcon#enter sib2, iclass 37, count 0 2006.201.11:31:19.87#ibcon#flushed, iclass 37, count 0 2006.201.11:31:19.87#ibcon#about to write, iclass 37, count 0 2006.201.11:31:19.87#ibcon#wrote, iclass 37, count 0 2006.201.11:31:19.87#ibcon#about to read 3, iclass 37, count 0 2006.201.11:31:19.90#ibcon#read 3, iclass 37, count 0 2006.201.11:31:19.90#ibcon#about to read 4, iclass 37, count 0 2006.201.11:31:19.90#ibcon#read 4, iclass 37, count 0 2006.201.11:31:19.90#ibcon#about to read 5, iclass 37, count 0 2006.201.11:31:19.90#ibcon#read 5, iclass 37, count 0 2006.201.11:31:19.90#ibcon#about to read 6, iclass 37, count 0 2006.201.11:31:19.90#ibcon#read 6, iclass 37, count 0 2006.201.11:31:19.90#ibcon#end of sib2, iclass 37, count 0 2006.201.11:31:19.90#ibcon#*after write, iclass 37, count 0 2006.201.11:31:19.90#ibcon#*before return 0, iclass 37, count 0 2006.201.11:31:19.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:19.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:19.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.11:31:19.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.11:31:19.90$vck44/valo=7,864.99 2006.201.11:31:19.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.11:31:19.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.11:31:19.90#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:19.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:19.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:19.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:19.90#ibcon#enter wrdev, iclass 39, count 0 2006.201.11:31:19.90#ibcon#first serial, iclass 39, count 0 2006.201.11:31:19.90#ibcon#enter sib2, iclass 39, count 0 2006.201.11:31:19.90#ibcon#flushed, iclass 39, count 0 2006.201.11:31:19.90#ibcon#about to write, iclass 39, count 0 2006.201.11:31:19.90#ibcon#wrote, iclass 39, count 0 2006.201.11:31:19.90#ibcon#about to read 3, iclass 39, count 0 2006.201.11:31:19.92#ibcon#read 3, iclass 39, count 0 2006.201.11:31:19.92#ibcon#about to read 4, iclass 39, count 0 2006.201.11:31:19.92#ibcon#read 4, iclass 39, count 0 2006.201.11:31:19.92#ibcon#about to read 5, iclass 39, count 0 2006.201.11:31:19.92#ibcon#read 5, iclass 39, count 0 2006.201.11:31:19.92#ibcon#about to read 6, iclass 39, count 0 2006.201.11:31:19.92#ibcon#read 6, iclass 39, count 0 2006.201.11:31:19.92#ibcon#end of sib2, iclass 39, count 0 2006.201.11:31:19.92#ibcon#*mode == 0, iclass 39, count 0 2006.201.11:31:19.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.11:31:19.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:31:19.92#ibcon#*before write, iclass 39, count 0 2006.201.11:31:19.92#ibcon#enter sib2, iclass 39, count 0 2006.201.11:31:19.92#ibcon#flushed, iclass 39, count 0 2006.201.11:31:19.92#ibcon#about to write, iclass 39, count 0 2006.201.11:31:19.92#ibcon#wrote, iclass 39, count 0 2006.201.11:31:19.92#ibcon#about to read 3, iclass 39, count 0 2006.201.11:31:19.96#ibcon#read 3, iclass 39, count 0 2006.201.11:31:19.96#ibcon#about to read 4, iclass 39, count 0 2006.201.11:31:19.96#ibcon#read 4, iclass 39, count 0 2006.201.11:31:19.96#ibcon#about to read 5, iclass 39, count 0 2006.201.11:31:19.96#ibcon#read 5, iclass 39, count 0 2006.201.11:31:19.96#ibcon#about to read 6, iclass 39, count 0 2006.201.11:31:19.96#ibcon#read 6, iclass 39, count 0 2006.201.11:31:19.96#ibcon#end of sib2, iclass 39, count 0 2006.201.11:31:19.96#ibcon#*after write, iclass 39, count 0 2006.201.11:31:19.96#ibcon#*before return 0, iclass 39, count 0 2006.201.11:31:19.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:19.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:19.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.11:31:19.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.11:31:19.96$vck44/va=7,5 2006.201.11:31:19.96#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.11:31:19.96#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.11:31:19.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:19.96#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:20.02#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:20.02#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:20.02#ibcon#enter wrdev, iclass 2, count 2 2006.201.11:31:20.02#ibcon#first serial, iclass 2, count 2 2006.201.11:31:20.02#ibcon#enter sib2, iclass 2, count 2 2006.201.11:31:20.02#ibcon#flushed, iclass 2, count 2 2006.201.11:31:20.02#ibcon#about to write, iclass 2, count 2 2006.201.11:31:20.02#ibcon#wrote, iclass 2, count 2 2006.201.11:31:20.02#ibcon#about to read 3, iclass 2, count 2 2006.201.11:31:20.04#ibcon#read 3, iclass 2, count 2 2006.201.11:31:20.04#ibcon#about to read 4, iclass 2, count 2 2006.201.11:31:20.04#ibcon#read 4, iclass 2, count 2 2006.201.11:31:20.04#ibcon#about to read 5, iclass 2, count 2 2006.201.11:31:20.04#ibcon#read 5, iclass 2, count 2 2006.201.11:31:20.04#ibcon#about to read 6, iclass 2, count 2 2006.201.11:31:20.04#ibcon#read 6, iclass 2, count 2 2006.201.11:31:20.04#ibcon#end of sib2, iclass 2, count 2 2006.201.11:31:20.04#ibcon#*mode == 0, iclass 2, count 2 2006.201.11:31:20.04#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.11:31:20.04#ibcon#[25=AT07-05\r\n] 2006.201.11:31:20.04#ibcon#*before write, iclass 2, count 2 2006.201.11:31:20.04#ibcon#enter sib2, iclass 2, count 2 2006.201.11:31:20.04#ibcon#flushed, iclass 2, count 2 2006.201.11:31:20.04#ibcon#about to write, iclass 2, count 2 2006.201.11:31:20.04#ibcon#wrote, iclass 2, count 2 2006.201.11:31:20.04#ibcon#about to read 3, iclass 2, count 2 2006.201.11:31:20.07#ibcon#read 3, iclass 2, count 2 2006.201.11:31:20.07#ibcon#about to read 4, iclass 2, count 2 2006.201.11:31:20.07#ibcon#read 4, iclass 2, count 2 2006.201.11:31:20.07#ibcon#about to read 5, iclass 2, count 2 2006.201.11:31:20.07#ibcon#read 5, iclass 2, count 2 2006.201.11:31:20.07#ibcon#about to read 6, iclass 2, count 2 2006.201.11:31:20.07#ibcon#read 6, iclass 2, count 2 2006.201.11:31:20.07#ibcon#end of sib2, iclass 2, count 2 2006.201.11:31:20.07#ibcon#*after write, iclass 2, count 2 2006.201.11:31:20.07#ibcon#*before return 0, iclass 2, count 2 2006.201.11:31:20.07#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:20.07#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:20.07#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.11:31:20.07#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:20.07#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:20.19#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:20.19#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:20.19#ibcon#enter wrdev, iclass 2, count 0 2006.201.11:31:20.19#ibcon#first serial, iclass 2, count 0 2006.201.11:31:20.19#ibcon#enter sib2, iclass 2, count 0 2006.201.11:31:20.19#ibcon#flushed, iclass 2, count 0 2006.201.11:31:20.19#ibcon#about to write, iclass 2, count 0 2006.201.11:31:20.19#ibcon#wrote, iclass 2, count 0 2006.201.11:31:20.19#ibcon#about to read 3, iclass 2, count 0 2006.201.11:31:20.21#ibcon#read 3, iclass 2, count 0 2006.201.11:31:20.21#ibcon#about to read 4, iclass 2, count 0 2006.201.11:31:20.21#ibcon#read 4, iclass 2, count 0 2006.201.11:31:20.21#ibcon#about to read 5, iclass 2, count 0 2006.201.11:31:20.21#ibcon#read 5, iclass 2, count 0 2006.201.11:31:20.21#ibcon#about to read 6, iclass 2, count 0 2006.201.11:31:20.21#ibcon#read 6, iclass 2, count 0 2006.201.11:31:20.21#ibcon#end of sib2, iclass 2, count 0 2006.201.11:31:20.21#ibcon#*mode == 0, iclass 2, count 0 2006.201.11:31:20.21#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.11:31:20.21#ibcon#[25=USB\r\n] 2006.201.11:31:20.21#ibcon#*before write, iclass 2, count 0 2006.201.11:31:20.21#ibcon#enter sib2, iclass 2, count 0 2006.201.11:31:20.21#ibcon#flushed, iclass 2, count 0 2006.201.11:31:20.21#ibcon#about to write, iclass 2, count 0 2006.201.11:31:20.21#ibcon#wrote, iclass 2, count 0 2006.201.11:31:20.21#ibcon#about to read 3, iclass 2, count 0 2006.201.11:31:20.24#ibcon#read 3, iclass 2, count 0 2006.201.11:31:20.24#ibcon#about to read 4, iclass 2, count 0 2006.201.11:31:20.24#ibcon#read 4, iclass 2, count 0 2006.201.11:31:20.24#ibcon#about to read 5, iclass 2, count 0 2006.201.11:31:20.24#ibcon#read 5, iclass 2, count 0 2006.201.11:31:20.24#ibcon#about to read 6, iclass 2, count 0 2006.201.11:31:20.24#ibcon#read 6, iclass 2, count 0 2006.201.11:31:20.24#ibcon#end of sib2, iclass 2, count 0 2006.201.11:31:20.24#ibcon#*after write, iclass 2, count 0 2006.201.11:31:20.24#ibcon#*before return 0, iclass 2, count 0 2006.201.11:31:20.24#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:20.24#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:20.24#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.11:31:20.24#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.11:31:20.24$vck44/valo=8,884.99 2006.201.11:31:20.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.11:31:20.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.11:31:20.24#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:20.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:20.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:20.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:20.24#ibcon#enter wrdev, iclass 5, count 0 2006.201.11:31:20.24#ibcon#first serial, iclass 5, count 0 2006.201.11:31:20.24#ibcon#enter sib2, iclass 5, count 0 2006.201.11:31:20.24#ibcon#flushed, iclass 5, count 0 2006.201.11:31:20.24#ibcon#about to write, iclass 5, count 0 2006.201.11:31:20.24#ibcon#wrote, iclass 5, count 0 2006.201.11:31:20.24#ibcon#about to read 3, iclass 5, count 0 2006.201.11:31:20.26#ibcon#read 3, iclass 5, count 0 2006.201.11:31:20.26#ibcon#about to read 4, iclass 5, count 0 2006.201.11:31:20.26#ibcon#read 4, iclass 5, count 0 2006.201.11:31:20.26#ibcon#about to read 5, iclass 5, count 0 2006.201.11:31:20.26#ibcon#read 5, iclass 5, count 0 2006.201.11:31:20.26#ibcon#about to read 6, iclass 5, count 0 2006.201.11:31:20.26#ibcon#read 6, iclass 5, count 0 2006.201.11:31:20.26#ibcon#end of sib2, iclass 5, count 0 2006.201.11:31:20.26#ibcon#*mode == 0, iclass 5, count 0 2006.201.11:31:20.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.11:31:20.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:31:20.26#ibcon#*before write, iclass 5, count 0 2006.201.11:31:20.26#ibcon#enter sib2, iclass 5, count 0 2006.201.11:31:20.26#ibcon#flushed, iclass 5, count 0 2006.201.11:31:20.26#ibcon#about to write, iclass 5, count 0 2006.201.11:31:20.26#ibcon#wrote, iclass 5, count 0 2006.201.11:31:20.26#ibcon#about to read 3, iclass 5, count 0 2006.201.11:31:20.30#ibcon#read 3, iclass 5, count 0 2006.201.11:31:20.30#ibcon#about to read 4, iclass 5, count 0 2006.201.11:31:20.30#ibcon#read 4, iclass 5, count 0 2006.201.11:31:20.30#ibcon#about to read 5, iclass 5, count 0 2006.201.11:31:20.30#ibcon#read 5, iclass 5, count 0 2006.201.11:31:20.30#ibcon#about to read 6, iclass 5, count 0 2006.201.11:31:20.30#ibcon#read 6, iclass 5, count 0 2006.201.11:31:20.30#ibcon#end of sib2, iclass 5, count 0 2006.201.11:31:20.30#ibcon#*after write, iclass 5, count 0 2006.201.11:31:20.30#ibcon#*before return 0, iclass 5, count 0 2006.201.11:31:20.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:20.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:20.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.11:31:20.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.11:31:20.30$vck44/va=8,4 2006.201.11:31:20.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.11:31:20.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.11:31:20.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:20.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:31:20.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:31:20.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:31:20.36#ibcon#enter wrdev, iclass 7, count 2 2006.201.11:31:20.36#ibcon#first serial, iclass 7, count 2 2006.201.11:31:20.36#ibcon#enter sib2, iclass 7, count 2 2006.201.11:31:20.36#ibcon#flushed, iclass 7, count 2 2006.201.11:31:20.36#ibcon#about to write, iclass 7, count 2 2006.201.11:31:20.36#ibcon#wrote, iclass 7, count 2 2006.201.11:31:20.36#ibcon#about to read 3, iclass 7, count 2 2006.201.11:31:20.38#ibcon#read 3, iclass 7, count 2 2006.201.11:31:20.38#ibcon#about to read 4, iclass 7, count 2 2006.201.11:31:20.38#ibcon#read 4, iclass 7, count 2 2006.201.11:31:20.38#ibcon#about to read 5, iclass 7, count 2 2006.201.11:31:20.38#ibcon#read 5, iclass 7, count 2 2006.201.11:31:20.38#ibcon#about to read 6, iclass 7, count 2 2006.201.11:31:20.38#ibcon#read 6, iclass 7, count 2 2006.201.11:31:20.38#ibcon#end of sib2, iclass 7, count 2 2006.201.11:31:20.38#ibcon#*mode == 0, iclass 7, count 2 2006.201.11:31:20.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.11:31:20.38#ibcon#[25=AT08-04\r\n] 2006.201.11:31:20.38#ibcon#*before write, iclass 7, count 2 2006.201.11:31:20.38#ibcon#enter sib2, iclass 7, count 2 2006.201.11:31:20.38#ibcon#flushed, iclass 7, count 2 2006.201.11:31:20.38#ibcon#about to write, iclass 7, count 2 2006.201.11:31:20.38#ibcon#wrote, iclass 7, count 2 2006.201.11:31:20.38#ibcon#about to read 3, iclass 7, count 2 2006.201.11:31:20.41#ibcon#read 3, iclass 7, count 2 2006.201.11:31:20.41#ibcon#about to read 4, iclass 7, count 2 2006.201.11:31:20.41#ibcon#read 4, iclass 7, count 2 2006.201.11:31:20.41#ibcon#about to read 5, iclass 7, count 2 2006.201.11:31:20.41#ibcon#read 5, iclass 7, count 2 2006.201.11:31:20.41#ibcon#about to read 6, iclass 7, count 2 2006.201.11:31:20.41#ibcon#read 6, iclass 7, count 2 2006.201.11:31:20.41#ibcon#end of sib2, iclass 7, count 2 2006.201.11:31:20.41#ibcon#*after write, iclass 7, count 2 2006.201.11:31:20.41#ibcon#*before return 0, iclass 7, count 2 2006.201.11:31:20.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:31:20.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.11:31:20.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.11:31:20.41#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:20.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:31:20.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:31:20.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:31:20.53#ibcon#enter wrdev, iclass 7, count 0 2006.201.11:31:20.53#ibcon#first serial, iclass 7, count 0 2006.201.11:31:20.53#ibcon#enter sib2, iclass 7, count 0 2006.201.11:31:20.53#ibcon#flushed, iclass 7, count 0 2006.201.11:31:20.53#ibcon#about to write, iclass 7, count 0 2006.201.11:31:20.53#ibcon#wrote, iclass 7, count 0 2006.201.11:31:20.53#ibcon#about to read 3, iclass 7, count 0 2006.201.11:31:20.55#ibcon#read 3, iclass 7, count 0 2006.201.11:31:20.55#ibcon#about to read 4, iclass 7, count 0 2006.201.11:31:20.55#ibcon#read 4, iclass 7, count 0 2006.201.11:31:20.55#ibcon#about to read 5, iclass 7, count 0 2006.201.11:31:20.55#ibcon#read 5, iclass 7, count 0 2006.201.11:31:20.55#ibcon#about to read 6, iclass 7, count 0 2006.201.11:31:20.55#ibcon#read 6, iclass 7, count 0 2006.201.11:31:20.55#ibcon#end of sib2, iclass 7, count 0 2006.201.11:31:20.55#ibcon#*mode == 0, iclass 7, count 0 2006.201.11:31:20.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.11:31:20.55#ibcon#[25=USB\r\n] 2006.201.11:31:20.55#ibcon#*before write, iclass 7, count 0 2006.201.11:31:20.55#ibcon#enter sib2, iclass 7, count 0 2006.201.11:31:20.55#ibcon#flushed, iclass 7, count 0 2006.201.11:31:20.55#ibcon#about to write, iclass 7, count 0 2006.201.11:31:20.55#ibcon#wrote, iclass 7, count 0 2006.201.11:31:20.55#ibcon#about to read 3, iclass 7, count 0 2006.201.11:31:20.58#ibcon#read 3, iclass 7, count 0 2006.201.11:31:20.58#ibcon#about to read 4, iclass 7, count 0 2006.201.11:31:20.58#ibcon#read 4, iclass 7, count 0 2006.201.11:31:20.58#ibcon#about to read 5, iclass 7, count 0 2006.201.11:31:20.58#ibcon#read 5, iclass 7, count 0 2006.201.11:31:20.58#ibcon#about to read 6, iclass 7, count 0 2006.201.11:31:20.58#ibcon#read 6, iclass 7, count 0 2006.201.11:31:20.58#ibcon#end of sib2, iclass 7, count 0 2006.201.11:31:20.58#ibcon#*after write, iclass 7, count 0 2006.201.11:31:20.58#ibcon#*before return 0, iclass 7, count 0 2006.201.11:31:20.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:31:20.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.11:31:20.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.11:31:20.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.11:31:20.58$vck44/vblo=1,629.99 2006.201.11:31:20.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.11:31:20.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.11:31:20.58#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:20.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:31:20.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:31:20.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:31:20.58#ibcon#enter wrdev, iclass 11, count 0 2006.201.11:31:20.58#ibcon#first serial, iclass 11, count 0 2006.201.11:31:20.58#ibcon#enter sib2, iclass 11, count 0 2006.201.11:31:20.58#ibcon#flushed, iclass 11, count 0 2006.201.11:31:20.58#ibcon#about to write, iclass 11, count 0 2006.201.11:31:20.58#ibcon#wrote, iclass 11, count 0 2006.201.11:31:20.58#ibcon#about to read 3, iclass 11, count 0 2006.201.11:31:20.60#ibcon#read 3, iclass 11, count 0 2006.201.11:31:20.60#ibcon#about to read 4, iclass 11, count 0 2006.201.11:31:20.60#ibcon#read 4, iclass 11, count 0 2006.201.11:31:20.60#ibcon#about to read 5, iclass 11, count 0 2006.201.11:31:20.60#ibcon#read 5, iclass 11, count 0 2006.201.11:31:20.60#ibcon#about to read 6, iclass 11, count 0 2006.201.11:31:20.60#ibcon#read 6, iclass 11, count 0 2006.201.11:31:20.60#ibcon#end of sib2, iclass 11, count 0 2006.201.11:31:20.60#ibcon#*mode == 0, iclass 11, count 0 2006.201.11:31:20.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.11:31:20.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:31:20.60#ibcon#*before write, iclass 11, count 0 2006.201.11:31:20.60#ibcon#enter sib2, iclass 11, count 0 2006.201.11:31:20.60#ibcon#flushed, iclass 11, count 0 2006.201.11:31:20.60#ibcon#about to write, iclass 11, count 0 2006.201.11:31:20.60#ibcon#wrote, iclass 11, count 0 2006.201.11:31:20.60#ibcon#about to read 3, iclass 11, count 0 2006.201.11:31:20.65#ibcon#read 3, iclass 11, count 0 2006.201.11:31:20.65#ibcon#about to read 4, iclass 11, count 0 2006.201.11:31:20.65#ibcon#read 4, iclass 11, count 0 2006.201.11:31:20.65#ibcon#about to read 5, iclass 11, count 0 2006.201.11:31:20.65#ibcon#read 5, iclass 11, count 0 2006.201.11:31:20.65#ibcon#about to read 6, iclass 11, count 0 2006.201.11:31:20.65#ibcon#read 6, iclass 11, count 0 2006.201.11:31:20.65#ibcon#end of sib2, iclass 11, count 0 2006.201.11:31:20.65#ibcon#*after write, iclass 11, count 0 2006.201.11:31:20.65#ibcon#*before return 0, iclass 11, count 0 2006.201.11:31:20.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:31:20.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.11:31:20.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.11:31:20.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.11:31:20.65$vck44/vb=1,4 2006.201.11:31:20.65#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.11:31:20.65#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.11:31:20.65#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:20.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:31:20.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:31:20.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:31:20.65#ibcon#enter wrdev, iclass 13, count 2 2006.201.11:31:20.65#ibcon#first serial, iclass 13, count 2 2006.201.11:31:20.65#ibcon#enter sib2, iclass 13, count 2 2006.201.11:31:20.65#ibcon#flushed, iclass 13, count 2 2006.201.11:31:20.65#ibcon#about to write, iclass 13, count 2 2006.201.11:31:20.65#ibcon#wrote, iclass 13, count 2 2006.201.11:31:20.65#ibcon#about to read 3, iclass 13, count 2 2006.201.11:31:20.67#ibcon#read 3, iclass 13, count 2 2006.201.11:31:20.67#ibcon#about to read 4, iclass 13, count 2 2006.201.11:31:20.67#ibcon#read 4, iclass 13, count 2 2006.201.11:31:20.67#ibcon#about to read 5, iclass 13, count 2 2006.201.11:31:20.67#ibcon#read 5, iclass 13, count 2 2006.201.11:31:20.67#ibcon#about to read 6, iclass 13, count 2 2006.201.11:31:20.67#ibcon#read 6, iclass 13, count 2 2006.201.11:31:20.67#ibcon#end of sib2, iclass 13, count 2 2006.201.11:31:20.67#ibcon#*mode == 0, iclass 13, count 2 2006.201.11:31:20.67#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.11:31:20.67#ibcon#[27=AT01-04\r\n] 2006.201.11:31:20.67#ibcon#*before write, iclass 13, count 2 2006.201.11:31:20.67#ibcon#enter sib2, iclass 13, count 2 2006.201.11:31:20.67#ibcon#flushed, iclass 13, count 2 2006.201.11:31:20.67#ibcon#about to write, iclass 13, count 2 2006.201.11:31:20.67#ibcon#wrote, iclass 13, count 2 2006.201.11:31:20.67#ibcon#about to read 3, iclass 13, count 2 2006.201.11:31:20.70#ibcon#read 3, iclass 13, count 2 2006.201.11:31:20.70#ibcon#about to read 4, iclass 13, count 2 2006.201.11:31:20.70#ibcon#read 4, iclass 13, count 2 2006.201.11:31:20.70#ibcon#about to read 5, iclass 13, count 2 2006.201.11:31:20.70#ibcon#read 5, iclass 13, count 2 2006.201.11:31:20.70#ibcon#about to read 6, iclass 13, count 2 2006.201.11:31:20.70#ibcon#read 6, iclass 13, count 2 2006.201.11:31:20.70#ibcon#end of sib2, iclass 13, count 2 2006.201.11:31:20.70#ibcon#*after write, iclass 13, count 2 2006.201.11:31:20.70#ibcon#*before return 0, iclass 13, count 2 2006.201.11:31:20.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:31:20.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.11:31:20.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.11:31:20.70#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:20.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:31:20.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:31:20.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:31:20.82#ibcon#enter wrdev, iclass 13, count 0 2006.201.11:31:20.82#ibcon#first serial, iclass 13, count 0 2006.201.11:31:20.82#ibcon#enter sib2, iclass 13, count 0 2006.201.11:31:20.82#ibcon#flushed, iclass 13, count 0 2006.201.11:31:20.82#ibcon#about to write, iclass 13, count 0 2006.201.11:31:20.82#ibcon#wrote, iclass 13, count 0 2006.201.11:31:20.82#ibcon#about to read 3, iclass 13, count 0 2006.201.11:31:20.84#ibcon#read 3, iclass 13, count 0 2006.201.11:31:20.84#ibcon#about to read 4, iclass 13, count 0 2006.201.11:31:20.84#ibcon#read 4, iclass 13, count 0 2006.201.11:31:20.84#ibcon#about to read 5, iclass 13, count 0 2006.201.11:31:20.84#ibcon#read 5, iclass 13, count 0 2006.201.11:31:20.84#ibcon#about to read 6, iclass 13, count 0 2006.201.11:31:20.84#ibcon#read 6, iclass 13, count 0 2006.201.11:31:20.84#ibcon#end of sib2, iclass 13, count 0 2006.201.11:31:20.84#ibcon#*mode == 0, iclass 13, count 0 2006.201.11:31:20.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.11:31:20.84#ibcon#[27=USB\r\n] 2006.201.11:31:20.84#ibcon#*before write, iclass 13, count 0 2006.201.11:31:20.84#ibcon#enter sib2, iclass 13, count 0 2006.201.11:31:20.84#ibcon#flushed, iclass 13, count 0 2006.201.11:31:20.84#ibcon#about to write, iclass 13, count 0 2006.201.11:31:20.84#ibcon#wrote, iclass 13, count 0 2006.201.11:31:20.84#ibcon#about to read 3, iclass 13, count 0 2006.201.11:31:20.87#ibcon#read 3, iclass 13, count 0 2006.201.11:31:20.87#ibcon#about to read 4, iclass 13, count 0 2006.201.11:31:20.87#ibcon#read 4, iclass 13, count 0 2006.201.11:31:20.87#ibcon#about to read 5, iclass 13, count 0 2006.201.11:31:20.87#ibcon#read 5, iclass 13, count 0 2006.201.11:31:20.87#ibcon#about to read 6, iclass 13, count 0 2006.201.11:31:20.87#ibcon#read 6, iclass 13, count 0 2006.201.11:31:20.87#ibcon#end of sib2, iclass 13, count 0 2006.201.11:31:20.87#ibcon#*after write, iclass 13, count 0 2006.201.11:31:20.87#ibcon#*before return 0, iclass 13, count 0 2006.201.11:31:20.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:31:20.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.11:31:20.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.11:31:20.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.11:31:20.87$vck44/vblo=2,634.99 2006.201.11:31:20.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.11:31:20.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.11:31:20.87#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:20.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:20.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:20.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:20.87#ibcon#enter wrdev, iclass 15, count 0 2006.201.11:31:20.87#ibcon#first serial, iclass 15, count 0 2006.201.11:31:20.87#ibcon#enter sib2, iclass 15, count 0 2006.201.11:31:20.87#ibcon#flushed, iclass 15, count 0 2006.201.11:31:20.87#ibcon#about to write, iclass 15, count 0 2006.201.11:31:20.87#ibcon#wrote, iclass 15, count 0 2006.201.11:31:20.87#ibcon#about to read 3, iclass 15, count 0 2006.201.11:31:20.89#ibcon#read 3, iclass 15, count 0 2006.201.11:31:20.89#ibcon#about to read 4, iclass 15, count 0 2006.201.11:31:20.89#ibcon#read 4, iclass 15, count 0 2006.201.11:31:20.89#ibcon#about to read 5, iclass 15, count 0 2006.201.11:31:20.89#ibcon#read 5, iclass 15, count 0 2006.201.11:31:20.89#ibcon#about to read 6, iclass 15, count 0 2006.201.11:31:20.89#ibcon#read 6, iclass 15, count 0 2006.201.11:31:20.89#ibcon#end of sib2, iclass 15, count 0 2006.201.11:31:20.89#ibcon#*mode == 0, iclass 15, count 0 2006.201.11:31:20.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.11:31:20.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:31:20.89#ibcon#*before write, iclass 15, count 0 2006.201.11:31:20.89#ibcon#enter sib2, iclass 15, count 0 2006.201.11:31:20.89#ibcon#flushed, iclass 15, count 0 2006.201.11:31:20.89#ibcon#about to write, iclass 15, count 0 2006.201.11:31:20.89#ibcon#wrote, iclass 15, count 0 2006.201.11:31:20.89#ibcon#about to read 3, iclass 15, count 0 2006.201.11:31:20.93#ibcon#read 3, iclass 15, count 0 2006.201.11:31:20.93#ibcon#about to read 4, iclass 15, count 0 2006.201.11:31:20.93#ibcon#read 4, iclass 15, count 0 2006.201.11:31:20.93#ibcon#about to read 5, iclass 15, count 0 2006.201.11:31:20.93#ibcon#read 5, iclass 15, count 0 2006.201.11:31:20.93#ibcon#about to read 6, iclass 15, count 0 2006.201.11:31:20.93#ibcon#read 6, iclass 15, count 0 2006.201.11:31:20.93#ibcon#end of sib2, iclass 15, count 0 2006.201.11:31:20.93#ibcon#*after write, iclass 15, count 0 2006.201.11:31:20.93#ibcon#*before return 0, iclass 15, count 0 2006.201.11:31:20.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:20.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.11:31:20.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.11:31:20.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.11:31:20.93$vck44/vb=2,5 2006.201.11:31:20.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.11:31:20.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.11:31:20.93#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:20.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:20.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:20.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:20.99#ibcon#enter wrdev, iclass 17, count 2 2006.201.11:31:20.99#ibcon#first serial, iclass 17, count 2 2006.201.11:31:20.99#ibcon#enter sib2, iclass 17, count 2 2006.201.11:31:20.99#ibcon#flushed, iclass 17, count 2 2006.201.11:31:20.99#ibcon#about to write, iclass 17, count 2 2006.201.11:31:20.99#ibcon#wrote, iclass 17, count 2 2006.201.11:31:20.99#ibcon#about to read 3, iclass 17, count 2 2006.201.11:31:21.01#ibcon#read 3, iclass 17, count 2 2006.201.11:31:21.01#ibcon#about to read 4, iclass 17, count 2 2006.201.11:31:21.01#ibcon#read 4, iclass 17, count 2 2006.201.11:31:21.01#ibcon#about to read 5, iclass 17, count 2 2006.201.11:31:21.01#ibcon#read 5, iclass 17, count 2 2006.201.11:31:21.01#ibcon#about to read 6, iclass 17, count 2 2006.201.11:31:21.01#ibcon#read 6, iclass 17, count 2 2006.201.11:31:21.01#ibcon#end of sib2, iclass 17, count 2 2006.201.11:31:21.01#ibcon#*mode == 0, iclass 17, count 2 2006.201.11:31:21.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.11:31:21.01#ibcon#[27=AT02-05\r\n] 2006.201.11:31:21.01#ibcon#*before write, iclass 17, count 2 2006.201.11:31:21.01#ibcon#enter sib2, iclass 17, count 2 2006.201.11:31:21.01#ibcon#flushed, iclass 17, count 2 2006.201.11:31:21.01#ibcon#about to write, iclass 17, count 2 2006.201.11:31:21.01#ibcon#wrote, iclass 17, count 2 2006.201.11:31:21.01#ibcon#about to read 3, iclass 17, count 2 2006.201.11:31:21.04#ibcon#read 3, iclass 17, count 2 2006.201.11:31:21.04#ibcon#about to read 4, iclass 17, count 2 2006.201.11:31:21.04#ibcon#read 4, iclass 17, count 2 2006.201.11:31:21.04#ibcon#about to read 5, iclass 17, count 2 2006.201.11:31:21.04#ibcon#read 5, iclass 17, count 2 2006.201.11:31:21.04#ibcon#about to read 6, iclass 17, count 2 2006.201.11:31:21.04#ibcon#read 6, iclass 17, count 2 2006.201.11:31:21.04#ibcon#end of sib2, iclass 17, count 2 2006.201.11:31:21.04#ibcon#*after write, iclass 17, count 2 2006.201.11:31:21.04#ibcon#*before return 0, iclass 17, count 2 2006.201.11:31:21.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:21.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.11:31:21.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.11:31:21.04#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:21.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:21.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:21.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:21.16#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:31:21.16#ibcon#first serial, iclass 17, count 0 2006.201.11:31:21.16#ibcon#enter sib2, iclass 17, count 0 2006.201.11:31:21.16#ibcon#flushed, iclass 17, count 0 2006.201.11:31:21.16#ibcon#about to write, iclass 17, count 0 2006.201.11:31:21.16#ibcon#wrote, iclass 17, count 0 2006.201.11:31:21.16#ibcon#about to read 3, iclass 17, count 0 2006.201.11:31:21.18#ibcon#read 3, iclass 17, count 0 2006.201.11:31:21.18#ibcon#about to read 4, iclass 17, count 0 2006.201.11:31:21.18#ibcon#read 4, iclass 17, count 0 2006.201.11:31:21.18#ibcon#about to read 5, iclass 17, count 0 2006.201.11:31:21.18#ibcon#read 5, iclass 17, count 0 2006.201.11:31:21.18#ibcon#about to read 6, iclass 17, count 0 2006.201.11:31:21.18#ibcon#read 6, iclass 17, count 0 2006.201.11:31:21.18#ibcon#end of sib2, iclass 17, count 0 2006.201.11:31:21.18#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:31:21.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:31:21.18#ibcon#[27=USB\r\n] 2006.201.11:31:21.18#ibcon#*before write, iclass 17, count 0 2006.201.11:31:21.18#ibcon#enter sib2, iclass 17, count 0 2006.201.11:31:21.18#ibcon#flushed, iclass 17, count 0 2006.201.11:31:21.18#ibcon#about to write, iclass 17, count 0 2006.201.11:31:21.18#ibcon#wrote, iclass 17, count 0 2006.201.11:31:21.18#ibcon#about to read 3, iclass 17, count 0 2006.201.11:31:21.21#ibcon#read 3, iclass 17, count 0 2006.201.11:31:21.21#ibcon#about to read 4, iclass 17, count 0 2006.201.11:31:21.21#ibcon#read 4, iclass 17, count 0 2006.201.11:31:21.21#ibcon#about to read 5, iclass 17, count 0 2006.201.11:31:21.21#ibcon#read 5, iclass 17, count 0 2006.201.11:31:21.21#ibcon#about to read 6, iclass 17, count 0 2006.201.11:31:21.21#ibcon#read 6, iclass 17, count 0 2006.201.11:31:21.21#ibcon#end of sib2, iclass 17, count 0 2006.201.11:31:21.21#ibcon#*after write, iclass 17, count 0 2006.201.11:31:21.21#ibcon#*before return 0, iclass 17, count 0 2006.201.11:31:21.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:21.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.11:31:21.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:31:21.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:31:21.21$vck44/vblo=3,649.99 2006.201.11:31:21.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.11:31:21.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.11:31:21.21#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:21.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:21.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:21.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:21.21#ibcon#enter wrdev, iclass 19, count 0 2006.201.11:31:21.21#ibcon#first serial, iclass 19, count 0 2006.201.11:31:21.21#ibcon#enter sib2, iclass 19, count 0 2006.201.11:31:21.21#ibcon#flushed, iclass 19, count 0 2006.201.11:31:21.21#ibcon#about to write, iclass 19, count 0 2006.201.11:31:21.21#ibcon#wrote, iclass 19, count 0 2006.201.11:31:21.21#ibcon#about to read 3, iclass 19, count 0 2006.201.11:31:21.23#ibcon#read 3, iclass 19, count 0 2006.201.11:31:21.23#ibcon#about to read 4, iclass 19, count 0 2006.201.11:31:21.23#ibcon#read 4, iclass 19, count 0 2006.201.11:31:21.23#ibcon#about to read 5, iclass 19, count 0 2006.201.11:31:21.23#ibcon#read 5, iclass 19, count 0 2006.201.11:31:21.23#ibcon#about to read 6, iclass 19, count 0 2006.201.11:31:21.23#ibcon#read 6, iclass 19, count 0 2006.201.11:31:21.23#ibcon#end of sib2, iclass 19, count 0 2006.201.11:31:21.23#ibcon#*mode == 0, iclass 19, count 0 2006.201.11:31:21.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.11:31:21.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:31:21.23#ibcon#*before write, iclass 19, count 0 2006.201.11:31:21.23#ibcon#enter sib2, iclass 19, count 0 2006.201.11:31:21.23#ibcon#flushed, iclass 19, count 0 2006.201.11:31:21.23#ibcon#about to write, iclass 19, count 0 2006.201.11:31:21.23#ibcon#wrote, iclass 19, count 0 2006.201.11:31:21.23#ibcon#about to read 3, iclass 19, count 0 2006.201.11:31:21.27#ibcon#read 3, iclass 19, count 0 2006.201.11:31:21.27#ibcon#about to read 4, iclass 19, count 0 2006.201.11:31:21.27#ibcon#read 4, iclass 19, count 0 2006.201.11:31:21.27#ibcon#about to read 5, iclass 19, count 0 2006.201.11:31:21.27#ibcon#read 5, iclass 19, count 0 2006.201.11:31:21.27#ibcon#about to read 6, iclass 19, count 0 2006.201.11:31:21.27#ibcon#read 6, iclass 19, count 0 2006.201.11:31:21.27#ibcon#end of sib2, iclass 19, count 0 2006.201.11:31:21.27#ibcon#*after write, iclass 19, count 0 2006.201.11:31:21.27#ibcon#*before return 0, iclass 19, count 0 2006.201.11:31:21.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:21.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.11:31:21.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.11:31:21.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.11:31:21.27$vck44/vb=3,4 2006.201.11:31:21.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.11:31:21.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.11:31:21.27#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:21.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:21.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:21.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:21.33#ibcon#enter wrdev, iclass 21, count 2 2006.201.11:31:21.33#ibcon#first serial, iclass 21, count 2 2006.201.11:31:21.33#ibcon#enter sib2, iclass 21, count 2 2006.201.11:31:21.33#ibcon#flushed, iclass 21, count 2 2006.201.11:31:21.33#ibcon#about to write, iclass 21, count 2 2006.201.11:31:21.33#ibcon#wrote, iclass 21, count 2 2006.201.11:31:21.33#ibcon#about to read 3, iclass 21, count 2 2006.201.11:31:21.35#ibcon#read 3, iclass 21, count 2 2006.201.11:31:21.35#ibcon#about to read 4, iclass 21, count 2 2006.201.11:31:21.35#ibcon#read 4, iclass 21, count 2 2006.201.11:31:21.35#ibcon#about to read 5, iclass 21, count 2 2006.201.11:31:21.35#ibcon#read 5, iclass 21, count 2 2006.201.11:31:21.35#ibcon#about to read 6, iclass 21, count 2 2006.201.11:31:21.35#ibcon#read 6, iclass 21, count 2 2006.201.11:31:21.35#ibcon#end of sib2, iclass 21, count 2 2006.201.11:31:21.35#ibcon#*mode == 0, iclass 21, count 2 2006.201.11:31:21.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.11:31:21.35#ibcon#[27=AT03-04\r\n] 2006.201.11:31:21.35#ibcon#*before write, iclass 21, count 2 2006.201.11:31:21.35#ibcon#enter sib2, iclass 21, count 2 2006.201.11:31:21.35#ibcon#flushed, iclass 21, count 2 2006.201.11:31:21.35#ibcon#about to write, iclass 21, count 2 2006.201.11:31:21.35#ibcon#wrote, iclass 21, count 2 2006.201.11:31:21.35#ibcon#about to read 3, iclass 21, count 2 2006.201.11:31:21.38#ibcon#read 3, iclass 21, count 2 2006.201.11:31:21.38#ibcon#about to read 4, iclass 21, count 2 2006.201.11:31:21.38#ibcon#read 4, iclass 21, count 2 2006.201.11:31:21.38#ibcon#about to read 5, iclass 21, count 2 2006.201.11:31:21.38#ibcon#read 5, iclass 21, count 2 2006.201.11:31:21.38#ibcon#about to read 6, iclass 21, count 2 2006.201.11:31:21.38#ibcon#read 6, iclass 21, count 2 2006.201.11:31:21.38#ibcon#end of sib2, iclass 21, count 2 2006.201.11:31:21.38#ibcon#*after write, iclass 21, count 2 2006.201.11:31:21.38#ibcon#*before return 0, iclass 21, count 2 2006.201.11:31:21.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:21.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.11:31:21.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.11:31:21.38#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:21.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:21.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:21.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:21.50#ibcon#enter wrdev, iclass 21, count 0 2006.201.11:31:21.50#ibcon#first serial, iclass 21, count 0 2006.201.11:31:21.50#ibcon#enter sib2, iclass 21, count 0 2006.201.11:31:21.50#ibcon#flushed, iclass 21, count 0 2006.201.11:31:21.50#ibcon#about to write, iclass 21, count 0 2006.201.11:31:21.50#ibcon#wrote, iclass 21, count 0 2006.201.11:31:21.50#ibcon#about to read 3, iclass 21, count 0 2006.201.11:31:21.52#ibcon#read 3, iclass 21, count 0 2006.201.11:31:21.52#ibcon#about to read 4, iclass 21, count 0 2006.201.11:31:21.52#ibcon#read 4, iclass 21, count 0 2006.201.11:31:21.52#ibcon#about to read 5, iclass 21, count 0 2006.201.11:31:21.52#ibcon#read 5, iclass 21, count 0 2006.201.11:31:21.52#ibcon#about to read 6, iclass 21, count 0 2006.201.11:31:21.52#ibcon#read 6, iclass 21, count 0 2006.201.11:31:21.52#ibcon#end of sib2, iclass 21, count 0 2006.201.11:31:21.52#ibcon#*mode == 0, iclass 21, count 0 2006.201.11:31:21.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.11:31:21.52#ibcon#[27=USB\r\n] 2006.201.11:31:21.52#ibcon#*before write, iclass 21, count 0 2006.201.11:31:21.52#ibcon#enter sib2, iclass 21, count 0 2006.201.11:31:21.52#ibcon#flushed, iclass 21, count 0 2006.201.11:31:21.52#ibcon#about to write, iclass 21, count 0 2006.201.11:31:21.52#ibcon#wrote, iclass 21, count 0 2006.201.11:31:21.52#ibcon#about to read 3, iclass 21, count 0 2006.201.11:31:21.55#ibcon#read 3, iclass 21, count 0 2006.201.11:31:21.55#ibcon#about to read 4, iclass 21, count 0 2006.201.11:31:21.55#ibcon#read 4, iclass 21, count 0 2006.201.11:31:21.55#ibcon#about to read 5, iclass 21, count 0 2006.201.11:31:21.55#ibcon#read 5, iclass 21, count 0 2006.201.11:31:21.55#ibcon#about to read 6, iclass 21, count 0 2006.201.11:31:21.55#ibcon#read 6, iclass 21, count 0 2006.201.11:31:21.55#ibcon#end of sib2, iclass 21, count 0 2006.201.11:31:21.55#ibcon#*after write, iclass 21, count 0 2006.201.11:31:21.55#ibcon#*before return 0, iclass 21, count 0 2006.201.11:31:21.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:21.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.11:31:21.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.11:31:21.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.11:31:21.55$vck44/vblo=4,679.99 2006.201.11:31:21.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.11:31:21.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.11:31:21.55#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:21.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:21.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:21.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:21.55#ibcon#enter wrdev, iclass 23, count 0 2006.201.11:31:21.55#ibcon#first serial, iclass 23, count 0 2006.201.11:31:21.55#ibcon#enter sib2, iclass 23, count 0 2006.201.11:31:21.55#ibcon#flushed, iclass 23, count 0 2006.201.11:31:21.55#ibcon#about to write, iclass 23, count 0 2006.201.11:31:21.55#ibcon#wrote, iclass 23, count 0 2006.201.11:31:21.55#ibcon#about to read 3, iclass 23, count 0 2006.201.11:31:21.57#ibcon#read 3, iclass 23, count 0 2006.201.11:31:21.57#ibcon#about to read 4, iclass 23, count 0 2006.201.11:31:21.57#ibcon#read 4, iclass 23, count 0 2006.201.11:31:21.57#ibcon#about to read 5, iclass 23, count 0 2006.201.11:31:21.57#ibcon#read 5, iclass 23, count 0 2006.201.11:31:21.57#ibcon#about to read 6, iclass 23, count 0 2006.201.11:31:21.57#ibcon#read 6, iclass 23, count 0 2006.201.11:31:21.57#ibcon#end of sib2, iclass 23, count 0 2006.201.11:31:21.57#ibcon#*mode == 0, iclass 23, count 0 2006.201.11:31:21.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.11:31:21.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:31:21.57#ibcon#*before write, iclass 23, count 0 2006.201.11:31:21.57#ibcon#enter sib2, iclass 23, count 0 2006.201.11:31:21.57#ibcon#flushed, iclass 23, count 0 2006.201.11:31:21.57#ibcon#about to write, iclass 23, count 0 2006.201.11:31:21.57#ibcon#wrote, iclass 23, count 0 2006.201.11:31:21.57#ibcon#about to read 3, iclass 23, count 0 2006.201.11:31:21.62#ibcon#read 3, iclass 23, count 0 2006.201.11:31:21.62#ibcon#about to read 4, iclass 23, count 0 2006.201.11:31:21.62#ibcon#read 4, iclass 23, count 0 2006.201.11:31:21.62#ibcon#about to read 5, iclass 23, count 0 2006.201.11:31:21.62#ibcon#read 5, iclass 23, count 0 2006.201.11:31:21.62#ibcon#about to read 6, iclass 23, count 0 2006.201.11:31:21.62#ibcon#read 6, iclass 23, count 0 2006.201.11:31:21.62#ibcon#end of sib2, iclass 23, count 0 2006.201.11:31:21.62#ibcon#*after write, iclass 23, count 0 2006.201.11:31:21.62#ibcon#*before return 0, iclass 23, count 0 2006.201.11:31:21.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:21.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.11:31:21.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.11:31:21.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.11:31:21.62$vck44/vb=4,5 2006.201.11:31:21.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.11:31:21.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.11:31:21.62#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:21.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:21.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:21.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:21.67#ibcon#enter wrdev, iclass 25, count 2 2006.201.11:31:21.67#ibcon#first serial, iclass 25, count 2 2006.201.11:31:21.67#ibcon#enter sib2, iclass 25, count 2 2006.201.11:31:21.67#ibcon#flushed, iclass 25, count 2 2006.201.11:31:21.67#ibcon#about to write, iclass 25, count 2 2006.201.11:31:21.67#ibcon#wrote, iclass 25, count 2 2006.201.11:31:21.67#ibcon#about to read 3, iclass 25, count 2 2006.201.11:31:21.69#ibcon#read 3, iclass 25, count 2 2006.201.11:31:21.69#ibcon#about to read 4, iclass 25, count 2 2006.201.11:31:21.69#ibcon#read 4, iclass 25, count 2 2006.201.11:31:21.69#ibcon#about to read 5, iclass 25, count 2 2006.201.11:31:21.69#ibcon#read 5, iclass 25, count 2 2006.201.11:31:21.69#ibcon#about to read 6, iclass 25, count 2 2006.201.11:31:21.69#ibcon#read 6, iclass 25, count 2 2006.201.11:31:21.69#ibcon#end of sib2, iclass 25, count 2 2006.201.11:31:21.69#ibcon#*mode == 0, iclass 25, count 2 2006.201.11:31:21.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.11:31:21.69#ibcon#[27=AT04-05\r\n] 2006.201.11:31:21.69#ibcon#*before write, iclass 25, count 2 2006.201.11:31:21.69#ibcon#enter sib2, iclass 25, count 2 2006.201.11:31:21.69#ibcon#flushed, iclass 25, count 2 2006.201.11:31:21.69#ibcon#about to write, iclass 25, count 2 2006.201.11:31:21.69#ibcon#wrote, iclass 25, count 2 2006.201.11:31:21.69#ibcon#about to read 3, iclass 25, count 2 2006.201.11:31:21.72#ibcon#read 3, iclass 25, count 2 2006.201.11:31:21.72#ibcon#about to read 4, iclass 25, count 2 2006.201.11:31:21.72#ibcon#read 4, iclass 25, count 2 2006.201.11:31:21.72#ibcon#about to read 5, iclass 25, count 2 2006.201.11:31:21.72#ibcon#read 5, iclass 25, count 2 2006.201.11:31:21.72#ibcon#about to read 6, iclass 25, count 2 2006.201.11:31:21.72#ibcon#read 6, iclass 25, count 2 2006.201.11:31:21.72#ibcon#end of sib2, iclass 25, count 2 2006.201.11:31:21.72#ibcon#*after write, iclass 25, count 2 2006.201.11:31:21.72#ibcon#*before return 0, iclass 25, count 2 2006.201.11:31:21.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:21.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.11:31:21.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.11:31:21.72#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:21.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:21.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:21.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:21.84#ibcon#enter wrdev, iclass 25, count 0 2006.201.11:31:21.84#ibcon#first serial, iclass 25, count 0 2006.201.11:31:21.84#ibcon#enter sib2, iclass 25, count 0 2006.201.11:31:21.84#ibcon#flushed, iclass 25, count 0 2006.201.11:31:21.84#ibcon#about to write, iclass 25, count 0 2006.201.11:31:21.84#ibcon#wrote, iclass 25, count 0 2006.201.11:31:21.84#ibcon#about to read 3, iclass 25, count 0 2006.201.11:31:21.86#ibcon#read 3, iclass 25, count 0 2006.201.11:31:21.86#ibcon#about to read 4, iclass 25, count 0 2006.201.11:31:21.86#ibcon#read 4, iclass 25, count 0 2006.201.11:31:21.86#ibcon#about to read 5, iclass 25, count 0 2006.201.11:31:21.86#ibcon#read 5, iclass 25, count 0 2006.201.11:31:21.86#ibcon#about to read 6, iclass 25, count 0 2006.201.11:31:21.86#ibcon#read 6, iclass 25, count 0 2006.201.11:31:21.86#ibcon#end of sib2, iclass 25, count 0 2006.201.11:31:21.86#ibcon#*mode == 0, iclass 25, count 0 2006.201.11:31:21.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.11:31:21.86#ibcon#[27=USB\r\n] 2006.201.11:31:21.86#ibcon#*before write, iclass 25, count 0 2006.201.11:31:21.86#ibcon#enter sib2, iclass 25, count 0 2006.201.11:31:21.86#ibcon#flushed, iclass 25, count 0 2006.201.11:31:21.86#ibcon#about to write, iclass 25, count 0 2006.201.11:31:21.86#ibcon#wrote, iclass 25, count 0 2006.201.11:31:21.86#ibcon#about to read 3, iclass 25, count 0 2006.201.11:31:21.89#ibcon#read 3, iclass 25, count 0 2006.201.11:31:21.89#ibcon#about to read 4, iclass 25, count 0 2006.201.11:31:21.89#ibcon#read 4, iclass 25, count 0 2006.201.11:31:21.89#ibcon#about to read 5, iclass 25, count 0 2006.201.11:31:21.89#ibcon#read 5, iclass 25, count 0 2006.201.11:31:21.89#ibcon#about to read 6, iclass 25, count 0 2006.201.11:31:21.89#ibcon#read 6, iclass 25, count 0 2006.201.11:31:21.89#ibcon#end of sib2, iclass 25, count 0 2006.201.11:31:21.89#ibcon#*after write, iclass 25, count 0 2006.201.11:31:21.89#ibcon#*before return 0, iclass 25, count 0 2006.201.11:31:21.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:21.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.11:31:21.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.11:31:21.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.11:31:21.89$vck44/vblo=5,709.99 2006.201.11:31:21.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.11:31:21.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.11:31:21.89#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:21.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:21.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:21.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:21.89#ibcon#enter wrdev, iclass 27, count 0 2006.201.11:31:21.89#ibcon#first serial, iclass 27, count 0 2006.201.11:31:21.89#ibcon#enter sib2, iclass 27, count 0 2006.201.11:31:21.89#ibcon#flushed, iclass 27, count 0 2006.201.11:31:21.89#ibcon#about to write, iclass 27, count 0 2006.201.11:31:21.89#ibcon#wrote, iclass 27, count 0 2006.201.11:31:21.89#ibcon#about to read 3, iclass 27, count 0 2006.201.11:31:21.91#ibcon#read 3, iclass 27, count 0 2006.201.11:31:21.91#ibcon#about to read 4, iclass 27, count 0 2006.201.11:31:21.91#ibcon#read 4, iclass 27, count 0 2006.201.11:31:21.91#ibcon#about to read 5, iclass 27, count 0 2006.201.11:31:21.91#ibcon#read 5, iclass 27, count 0 2006.201.11:31:21.91#ibcon#about to read 6, iclass 27, count 0 2006.201.11:31:21.91#ibcon#read 6, iclass 27, count 0 2006.201.11:31:21.91#ibcon#end of sib2, iclass 27, count 0 2006.201.11:31:21.91#ibcon#*mode == 0, iclass 27, count 0 2006.201.11:31:21.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.11:31:21.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:31:21.91#ibcon#*before write, iclass 27, count 0 2006.201.11:31:21.91#ibcon#enter sib2, iclass 27, count 0 2006.201.11:31:21.91#ibcon#flushed, iclass 27, count 0 2006.201.11:31:21.91#ibcon#about to write, iclass 27, count 0 2006.201.11:31:21.91#ibcon#wrote, iclass 27, count 0 2006.201.11:31:21.91#ibcon#about to read 3, iclass 27, count 0 2006.201.11:31:21.95#ibcon#read 3, iclass 27, count 0 2006.201.11:31:21.95#ibcon#about to read 4, iclass 27, count 0 2006.201.11:31:21.95#ibcon#read 4, iclass 27, count 0 2006.201.11:31:21.95#ibcon#about to read 5, iclass 27, count 0 2006.201.11:31:21.95#ibcon#read 5, iclass 27, count 0 2006.201.11:31:21.95#ibcon#about to read 6, iclass 27, count 0 2006.201.11:31:21.95#ibcon#read 6, iclass 27, count 0 2006.201.11:31:21.95#ibcon#end of sib2, iclass 27, count 0 2006.201.11:31:21.95#ibcon#*after write, iclass 27, count 0 2006.201.11:31:21.95#ibcon#*before return 0, iclass 27, count 0 2006.201.11:31:21.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:21.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.11:31:21.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.11:31:21.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.11:31:21.95$vck44/vb=5,4 2006.201.11:31:21.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.11:31:21.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.11:31:21.95#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:21.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:22.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:22.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:22.01#ibcon#enter wrdev, iclass 29, count 2 2006.201.11:31:22.01#ibcon#first serial, iclass 29, count 2 2006.201.11:31:22.01#ibcon#enter sib2, iclass 29, count 2 2006.201.11:31:22.01#ibcon#flushed, iclass 29, count 2 2006.201.11:31:22.01#ibcon#about to write, iclass 29, count 2 2006.201.11:31:22.01#ibcon#wrote, iclass 29, count 2 2006.201.11:31:22.01#ibcon#about to read 3, iclass 29, count 2 2006.201.11:31:22.03#ibcon#read 3, iclass 29, count 2 2006.201.11:31:22.03#ibcon#about to read 4, iclass 29, count 2 2006.201.11:31:22.03#ibcon#read 4, iclass 29, count 2 2006.201.11:31:22.03#ibcon#about to read 5, iclass 29, count 2 2006.201.11:31:22.03#ibcon#read 5, iclass 29, count 2 2006.201.11:31:22.03#ibcon#about to read 6, iclass 29, count 2 2006.201.11:31:22.03#ibcon#read 6, iclass 29, count 2 2006.201.11:31:22.03#ibcon#end of sib2, iclass 29, count 2 2006.201.11:31:22.03#ibcon#*mode == 0, iclass 29, count 2 2006.201.11:31:22.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.11:31:22.03#ibcon#[27=AT05-04\r\n] 2006.201.11:31:22.03#ibcon#*before write, iclass 29, count 2 2006.201.11:31:22.03#ibcon#enter sib2, iclass 29, count 2 2006.201.11:31:22.03#ibcon#flushed, iclass 29, count 2 2006.201.11:31:22.03#ibcon#about to write, iclass 29, count 2 2006.201.11:31:22.03#ibcon#wrote, iclass 29, count 2 2006.201.11:31:22.03#ibcon#about to read 3, iclass 29, count 2 2006.201.11:31:22.06#ibcon#read 3, iclass 29, count 2 2006.201.11:31:22.06#ibcon#about to read 4, iclass 29, count 2 2006.201.11:31:22.06#ibcon#read 4, iclass 29, count 2 2006.201.11:31:22.06#ibcon#about to read 5, iclass 29, count 2 2006.201.11:31:22.06#ibcon#read 5, iclass 29, count 2 2006.201.11:31:22.06#ibcon#about to read 6, iclass 29, count 2 2006.201.11:31:22.06#ibcon#read 6, iclass 29, count 2 2006.201.11:31:22.06#ibcon#end of sib2, iclass 29, count 2 2006.201.11:31:22.06#ibcon#*after write, iclass 29, count 2 2006.201.11:31:22.06#ibcon#*before return 0, iclass 29, count 2 2006.201.11:31:22.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:22.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.11:31:22.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.11:31:22.06#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:22.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:22.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:22.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:22.18#ibcon#enter wrdev, iclass 29, count 0 2006.201.11:31:22.18#ibcon#first serial, iclass 29, count 0 2006.201.11:31:22.18#ibcon#enter sib2, iclass 29, count 0 2006.201.11:31:22.18#ibcon#flushed, iclass 29, count 0 2006.201.11:31:22.18#ibcon#about to write, iclass 29, count 0 2006.201.11:31:22.18#ibcon#wrote, iclass 29, count 0 2006.201.11:31:22.18#ibcon#about to read 3, iclass 29, count 0 2006.201.11:31:22.20#ibcon#read 3, iclass 29, count 0 2006.201.11:31:22.20#ibcon#about to read 4, iclass 29, count 0 2006.201.11:31:22.20#ibcon#read 4, iclass 29, count 0 2006.201.11:31:22.20#ibcon#about to read 5, iclass 29, count 0 2006.201.11:31:22.20#ibcon#read 5, iclass 29, count 0 2006.201.11:31:22.20#ibcon#about to read 6, iclass 29, count 0 2006.201.11:31:22.20#ibcon#read 6, iclass 29, count 0 2006.201.11:31:22.20#ibcon#end of sib2, iclass 29, count 0 2006.201.11:31:22.20#ibcon#*mode == 0, iclass 29, count 0 2006.201.11:31:22.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.11:31:22.20#ibcon#[27=USB\r\n] 2006.201.11:31:22.20#ibcon#*before write, iclass 29, count 0 2006.201.11:31:22.20#ibcon#enter sib2, iclass 29, count 0 2006.201.11:31:22.20#ibcon#flushed, iclass 29, count 0 2006.201.11:31:22.20#ibcon#about to write, iclass 29, count 0 2006.201.11:31:22.20#ibcon#wrote, iclass 29, count 0 2006.201.11:31:22.20#ibcon#about to read 3, iclass 29, count 0 2006.201.11:31:22.23#ibcon#read 3, iclass 29, count 0 2006.201.11:31:22.23#ibcon#about to read 4, iclass 29, count 0 2006.201.11:31:22.23#ibcon#read 4, iclass 29, count 0 2006.201.11:31:22.23#ibcon#about to read 5, iclass 29, count 0 2006.201.11:31:22.23#ibcon#read 5, iclass 29, count 0 2006.201.11:31:22.23#ibcon#about to read 6, iclass 29, count 0 2006.201.11:31:22.23#ibcon#read 6, iclass 29, count 0 2006.201.11:31:22.23#ibcon#end of sib2, iclass 29, count 0 2006.201.11:31:22.23#ibcon#*after write, iclass 29, count 0 2006.201.11:31:22.23#ibcon#*before return 0, iclass 29, count 0 2006.201.11:31:22.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:22.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.11:31:22.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.11:31:22.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.11:31:22.23$vck44/vblo=6,719.99 2006.201.11:31:22.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.11:31:22.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.11:31:22.23#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:22.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:22.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:22.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:22.23#ibcon#enter wrdev, iclass 31, count 0 2006.201.11:31:22.23#ibcon#first serial, iclass 31, count 0 2006.201.11:31:22.23#ibcon#enter sib2, iclass 31, count 0 2006.201.11:31:22.23#ibcon#flushed, iclass 31, count 0 2006.201.11:31:22.23#ibcon#about to write, iclass 31, count 0 2006.201.11:31:22.23#ibcon#wrote, iclass 31, count 0 2006.201.11:31:22.23#ibcon#about to read 3, iclass 31, count 0 2006.201.11:31:22.25#ibcon#read 3, iclass 31, count 0 2006.201.11:31:22.25#ibcon#about to read 4, iclass 31, count 0 2006.201.11:31:22.25#ibcon#read 4, iclass 31, count 0 2006.201.11:31:22.25#ibcon#about to read 5, iclass 31, count 0 2006.201.11:31:22.25#ibcon#read 5, iclass 31, count 0 2006.201.11:31:22.25#ibcon#about to read 6, iclass 31, count 0 2006.201.11:31:22.25#ibcon#read 6, iclass 31, count 0 2006.201.11:31:22.25#ibcon#end of sib2, iclass 31, count 0 2006.201.11:31:22.25#ibcon#*mode == 0, iclass 31, count 0 2006.201.11:31:22.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.11:31:22.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:31:22.25#ibcon#*before write, iclass 31, count 0 2006.201.11:31:22.25#ibcon#enter sib2, iclass 31, count 0 2006.201.11:31:22.25#ibcon#flushed, iclass 31, count 0 2006.201.11:31:22.25#ibcon#about to write, iclass 31, count 0 2006.201.11:31:22.25#ibcon#wrote, iclass 31, count 0 2006.201.11:31:22.25#ibcon#about to read 3, iclass 31, count 0 2006.201.11:31:22.30#ibcon#read 3, iclass 31, count 0 2006.201.11:31:22.30#ibcon#about to read 4, iclass 31, count 0 2006.201.11:31:22.30#ibcon#read 4, iclass 31, count 0 2006.201.11:31:22.30#ibcon#about to read 5, iclass 31, count 0 2006.201.11:31:22.30#ibcon#read 5, iclass 31, count 0 2006.201.11:31:22.30#ibcon#about to read 6, iclass 31, count 0 2006.201.11:31:22.30#ibcon#read 6, iclass 31, count 0 2006.201.11:31:22.30#ibcon#end of sib2, iclass 31, count 0 2006.201.11:31:22.30#ibcon#*after write, iclass 31, count 0 2006.201.11:31:22.30#ibcon#*before return 0, iclass 31, count 0 2006.201.11:31:22.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:22.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.11:31:22.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.11:31:22.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.11:31:22.30$vck44/vb=6,4 2006.201.11:31:22.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.11:31:22.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.11:31:22.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:22.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:22.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:22.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:22.35#ibcon#enter wrdev, iclass 33, count 2 2006.201.11:31:22.35#ibcon#first serial, iclass 33, count 2 2006.201.11:31:22.35#ibcon#enter sib2, iclass 33, count 2 2006.201.11:31:22.35#ibcon#flushed, iclass 33, count 2 2006.201.11:31:22.35#ibcon#about to write, iclass 33, count 2 2006.201.11:31:22.35#ibcon#wrote, iclass 33, count 2 2006.201.11:31:22.35#ibcon#about to read 3, iclass 33, count 2 2006.201.11:31:22.37#ibcon#read 3, iclass 33, count 2 2006.201.11:31:22.37#ibcon#about to read 4, iclass 33, count 2 2006.201.11:31:22.37#ibcon#read 4, iclass 33, count 2 2006.201.11:31:22.37#ibcon#about to read 5, iclass 33, count 2 2006.201.11:31:22.37#ibcon#read 5, iclass 33, count 2 2006.201.11:31:22.37#ibcon#about to read 6, iclass 33, count 2 2006.201.11:31:22.37#ibcon#read 6, iclass 33, count 2 2006.201.11:31:22.37#ibcon#end of sib2, iclass 33, count 2 2006.201.11:31:22.37#ibcon#*mode == 0, iclass 33, count 2 2006.201.11:31:22.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.11:31:22.37#ibcon#[27=AT06-04\r\n] 2006.201.11:31:22.37#ibcon#*before write, iclass 33, count 2 2006.201.11:31:22.37#ibcon#enter sib2, iclass 33, count 2 2006.201.11:31:22.37#ibcon#flushed, iclass 33, count 2 2006.201.11:31:22.37#ibcon#about to write, iclass 33, count 2 2006.201.11:31:22.37#ibcon#wrote, iclass 33, count 2 2006.201.11:31:22.37#ibcon#about to read 3, iclass 33, count 2 2006.201.11:31:22.40#ibcon#read 3, iclass 33, count 2 2006.201.11:31:22.40#ibcon#about to read 4, iclass 33, count 2 2006.201.11:31:22.40#ibcon#read 4, iclass 33, count 2 2006.201.11:31:22.40#ibcon#about to read 5, iclass 33, count 2 2006.201.11:31:22.40#ibcon#read 5, iclass 33, count 2 2006.201.11:31:22.40#ibcon#about to read 6, iclass 33, count 2 2006.201.11:31:22.40#ibcon#read 6, iclass 33, count 2 2006.201.11:31:22.40#ibcon#end of sib2, iclass 33, count 2 2006.201.11:31:22.40#ibcon#*after write, iclass 33, count 2 2006.201.11:31:22.40#ibcon#*before return 0, iclass 33, count 2 2006.201.11:31:22.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:22.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.11:31:22.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.11:31:22.40#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:22.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:22.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:22.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:22.52#ibcon#enter wrdev, iclass 33, count 0 2006.201.11:31:22.52#ibcon#first serial, iclass 33, count 0 2006.201.11:31:22.52#ibcon#enter sib2, iclass 33, count 0 2006.201.11:31:22.52#ibcon#flushed, iclass 33, count 0 2006.201.11:31:22.52#ibcon#about to write, iclass 33, count 0 2006.201.11:31:22.52#ibcon#wrote, iclass 33, count 0 2006.201.11:31:22.52#ibcon#about to read 3, iclass 33, count 0 2006.201.11:31:22.54#ibcon#read 3, iclass 33, count 0 2006.201.11:31:22.54#ibcon#about to read 4, iclass 33, count 0 2006.201.11:31:22.54#ibcon#read 4, iclass 33, count 0 2006.201.11:31:22.54#ibcon#about to read 5, iclass 33, count 0 2006.201.11:31:22.54#ibcon#read 5, iclass 33, count 0 2006.201.11:31:22.54#ibcon#about to read 6, iclass 33, count 0 2006.201.11:31:22.54#ibcon#read 6, iclass 33, count 0 2006.201.11:31:22.54#ibcon#end of sib2, iclass 33, count 0 2006.201.11:31:22.54#ibcon#*mode == 0, iclass 33, count 0 2006.201.11:31:22.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.11:31:22.54#ibcon#[27=USB\r\n] 2006.201.11:31:22.54#ibcon#*before write, iclass 33, count 0 2006.201.11:31:22.54#ibcon#enter sib2, iclass 33, count 0 2006.201.11:31:22.54#ibcon#flushed, iclass 33, count 0 2006.201.11:31:22.54#ibcon#about to write, iclass 33, count 0 2006.201.11:31:22.54#ibcon#wrote, iclass 33, count 0 2006.201.11:31:22.54#ibcon#about to read 3, iclass 33, count 0 2006.201.11:31:22.57#ibcon#read 3, iclass 33, count 0 2006.201.11:31:22.57#ibcon#about to read 4, iclass 33, count 0 2006.201.11:31:22.57#ibcon#read 4, iclass 33, count 0 2006.201.11:31:22.57#ibcon#about to read 5, iclass 33, count 0 2006.201.11:31:22.57#ibcon#read 5, iclass 33, count 0 2006.201.11:31:22.57#ibcon#about to read 6, iclass 33, count 0 2006.201.11:31:22.57#ibcon#read 6, iclass 33, count 0 2006.201.11:31:22.57#ibcon#end of sib2, iclass 33, count 0 2006.201.11:31:22.57#ibcon#*after write, iclass 33, count 0 2006.201.11:31:22.57#ibcon#*before return 0, iclass 33, count 0 2006.201.11:31:22.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:22.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.11:31:22.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.11:31:22.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.11:31:22.57$vck44/vblo=7,734.99 2006.201.11:31:22.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.11:31:22.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.11:31:22.57#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:22.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:22.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:22.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:22.57#ibcon#enter wrdev, iclass 35, count 0 2006.201.11:31:22.57#ibcon#first serial, iclass 35, count 0 2006.201.11:31:22.57#ibcon#enter sib2, iclass 35, count 0 2006.201.11:31:22.57#ibcon#flushed, iclass 35, count 0 2006.201.11:31:22.57#ibcon#about to write, iclass 35, count 0 2006.201.11:31:22.57#ibcon#wrote, iclass 35, count 0 2006.201.11:31:22.57#ibcon#about to read 3, iclass 35, count 0 2006.201.11:31:22.59#ibcon#read 3, iclass 35, count 0 2006.201.11:31:22.59#ibcon#about to read 4, iclass 35, count 0 2006.201.11:31:22.59#ibcon#read 4, iclass 35, count 0 2006.201.11:31:22.59#ibcon#about to read 5, iclass 35, count 0 2006.201.11:31:22.59#ibcon#read 5, iclass 35, count 0 2006.201.11:31:22.59#ibcon#about to read 6, iclass 35, count 0 2006.201.11:31:22.59#ibcon#read 6, iclass 35, count 0 2006.201.11:31:22.59#ibcon#end of sib2, iclass 35, count 0 2006.201.11:31:22.59#ibcon#*mode == 0, iclass 35, count 0 2006.201.11:31:22.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.11:31:22.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:31:22.59#ibcon#*before write, iclass 35, count 0 2006.201.11:31:22.59#ibcon#enter sib2, iclass 35, count 0 2006.201.11:31:22.59#ibcon#flushed, iclass 35, count 0 2006.201.11:31:22.59#ibcon#about to write, iclass 35, count 0 2006.201.11:31:22.59#ibcon#wrote, iclass 35, count 0 2006.201.11:31:22.59#ibcon#about to read 3, iclass 35, count 0 2006.201.11:31:22.63#ibcon#read 3, iclass 35, count 0 2006.201.11:31:22.63#ibcon#about to read 4, iclass 35, count 0 2006.201.11:31:22.63#ibcon#read 4, iclass 35, count 0 2006.201.11:31:22.63#ibcon#about to read 5, iclass 35, count 0 2006.201.11:31:22.63#ibcon#read 5, iclass 35, count 0 2006.201.11:31:22.63#ibcon#about to read 6, iclass 35, count 0 2006.201.11:31:22.63#ibcon#read 6, iclass 35, count 0 2006.201.11:31:22.63#ibcon#end of sib2, iclass 35, count 0 2006.201.11:31:22.63#ibcon#*after write, iclass 35, count 0 2006.201.11:31:22.63#ibcon#*before return 0, iclass 35, count 0 2006.201.11:31:22.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:22.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.11:31:22.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.11:31:22.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.11:31:22.63$vck44/vb=7,4 2006.201.11:31:22.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.11:31:22.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.11:31:22.63#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:22.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:22.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:22.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:22.69#ibcon#enter wrdev, iclass 37, count 2 2006.201.11:31:22.69#ibcon#first serial, iclass 37, count 2 2006.201.11:31:22.69#ibcon#enter sib2, iclass 37, count 2 2006.201.11:31:22.69#ibcon#flushed, iclass 37, count 2 2006.201.11:31:22.69#ibcon#about to write, iclass 37, count 2 2006.201.11:31:22.69#ibcon#wrote, iclass 37, count 2 2006.201.11:31:22.69#ibcon#about to read 3, iclass 37, count 2 2006.201.11:31:22.71#ibcon#read 3, iclass 37, count 2 2006.201.11:31:22.71#ibcon#about to read 4, iclass 37, count 2 2006.201.11:31:22.71#ibcon#read 4, iclass 37, count 2 2006.201.11:31:22.71#ibcon#about to read 5, iclass 37, count 2 2006.201.11:31:22.71#ibcon#read 5, iclass 37, count 2 2006.201.11:31:22.71#ibcon#about to read 6, iclass 37, count 2 2006.201.11:31:22.71#ibcon#read 6, iclass 37, count 2 2006.201.11:31:22.71#ibcon#end of sib2, iclass 37, count 2 2006.201.11:31:22.71#ibcon#*mode == 0, iclass 37, count 2 2006.201.11:31:22.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.11:31:22.71#ibcon#[27=AT07-04\r\n] 2006.201.11:31:22.71#ibcon#*before write, iclass 37, count 2 2006.201.11:31:22.71#ibcon#enter sib2, iclass 37, count 2 2006.201.11:31:22.71#ibcon#flushed, iclass 37, count 2 2006.201.11:31:22.71#ibcon#about to write, iclass 37, count 2 2006.201.11:31:22.71#ibcon#wrote, iclass 37, count 2 2006.201.11:31:22.71#ibcon#about to read 3, iclass 37, count 2 2006.201.11:31:22.74#ibcon#read 3, iclass 37, count 2 2006.201.11:31:22.74#ibcon#about to read 4, iclass 37, count 2 2006.201.11:31:22.74#ibcon#read 4, iclass 37, count 2 2006.201.11:31:22.74#ibcon#about to read 5, iclass 37, count 2 2006.201.11:31:22.74#ibcon#read 5, iclass 37, count 2 2006.201.11:31:22.74#ibcon#about to read 6, iclass 37, count 2 2006.201.11:31:22.74#ibcon#read 6, iclass 37, count 2 2006.201.11:31:22.74#ibcon#end of sib2, iclass 37, count 2 2006.201.11:31:22.74#ibcon#*after write, iclass 37, count 2 2006.201.11:31:22.74#ibcon#*before return 0, iclass 37, count 2 2006.201.11:31:22.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:22.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.11:31:22.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.11:31:22.74#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:22.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:22.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:22.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:22.86#ibcon#enter wrdev, iclass 37, count 0 2006.201.11:31:22.86#ibcon#first serial, iclass 37, count 0 2006.201.11:31:22.86#ibcon#enter sib2, iclass 37, count 0 2006.201.11:31:22.86#ibcon#flushed, iclass 37, count 0 2006.201.11:31:22.86#ibcon#about to write, iclass 37, count 0 2006.201.11:31:22.86#ibcon#wrote, iclass 37, count 0 2006.201.11:31:22.86#ibcon#about to read 3, iclass 37, count 0 2006.201.11:31:22.88#ibcon#read 3, iclass 37, count 0 2006.201.11:31:22.88#ibcon#about to read 4, iclass 37, count 0 2006.201.11:31:22.88#ibcon#read 4, iclass 37, count 0 2006.201.11:31:22.88#ibcon#about to read 5, iclass 37, count 0 2006.201.11:31:22.88#ibcon#read 5, iclass 37, count 0 2006.201.11:31:22.88#ibcon#about to read 6, iclass 37, count 0 2006.201.11:31:22.88#ibcon#read 6, iclass 37, count 0 2006.201.11:31:22.88#ibcon#end of sib2, iclass 37, count 0 2006.201.11:31:22.88#ibcon#*mode == 0, iclass 37, count 0 2006.201.11:31:22.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.11:31:22.88#ibcon#[27=USB\r\n] 2006.201.11:31:22.88#ibcon#*before write, iclass 37, count 0 2006.201.11:31:22.88#ibcon#enter sib2, iclass 37, count 0 2006.201.11:31:22.88#ibcon#flushed, iclass 37, count 0 2006.201.11:31:22.88#ibcon#about to write, iclass 37, count 0 2006.201.11:31:22.88#ibcon#wrote, iclass 37, count 0 2006.201.11:31:22.88#ibcon#about to read 3, iclass 37, count 0 2006.201.11:31:22.91#ibcon#read 3, iclass 37, count 0 2006.201.11:31:22.91#ibcon#about to read 4, iclass 37, count 0 2006.201.11:31:22.91#ibcon#read 4, iclass 37, count 0 2006.201.11:31:22.91#ibcon#about to read 5, iclass 37, count 0 2006.201.11:31:22.91#ibcon#read 5, iclass 37, count 0 2006.201.11:31:22.91#ibcon#about to read 6, iclass 37, count 0 2006.201.11:31:22.91#ibcon#read 6, iclass 37, count 0 2006.201.11:31:22.91#ibcon#end of sib2, iclass 37, count 0 2006.201.11:31:22.91#ibcon#*after write, iclass 37, count 0 2006.201.11:31:22.91#ibcon#*before return 0, iclass 37, count 0 2006.201.11:31:22.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:22.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.11:31:22.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.11:31:22.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.11:31:22.91$vck44/vblo=8,744.99 2006.201.11:31:22.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.11:31:22.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.11:31:22.91#ibcon#ireg 17 cls_cnt 0 2006.201.11:31:22.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:22.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:22.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:22.91#ibcon#enter wrdev, iclass 39, count 0 2006.201.11:31:22.91#ibcon#first serial, iclass 39, count 0 2006.201.11:31:22.91#ibcon#enter sib2, iclass 39, count 0 2006.201.11:31:22.91#ibcon#flushed, iclass 39, count 0 2006.201.11:31:22.91#ibcon#about to write, iclass 39, count 0 2006.201.11:31:22.91#ibcon#wrote, iclass 39, count 0 2006.201.11:31:22.91#ibcon#about to read 3, iclass 39, count 0 2006.201.11:31:22.93#ibcon#read 3, iclass 39, count 0 2006.201.11:31:22.93#ibcon#about to read 4, iclass 39, count 0 2006.201.11:31:22.93#ibcon#read 4, iclass 39, count 0 2006.201.11:31:22.93#ibcon#about to read 5, iclass 39, count 0 2006.201.11:31:22.93#ibcon#read 5, iclass 39, count 0 2006.201.11:31:22.93#ibcon#about to read 6, iclass 39, count 0 2006.201.11:31:22.93#ibcon#read 6, iclass 39, count 0 2006.201.11:31:22.93#ibcon#end of sib2, iclass 39, count 0 2006.201.11:31:22.93#ibcon#*mode == 0, iclass 39, count 0 2006.201.11:31:22.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.11:31:22.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:31:22.93#ibcon#*before write, iclass 39, count 0 2006.201.11:31:22.93#ibcon#enter sib2, iclass 39, count 0 2006.201.11:31:22.93#ibcon#flushed, iclass 39, count 0 2006.201.11:31:22.93#ibcon#about to write, iclass 39, count 0 2006.201.11:31:22.93#ibcon#wrote, iclass 39, count 0 2006.201.11:31:22.93#ibcon#about to read 3, iclass 39, count 0 2006.201.11:31:22.97#ibcon#read 3, iclass 39, count 0 2006.201.11:31:22.97#ibcon#about to read 4, iclass 39, count 0 2006.201.11:31:22.97#ibcon#read 4, iclass 39, count 0 2006.201.11:31:22.97#ibcon#about to read 5, iclass 39, count 0 2006.201.11:31:22.97#ibcon#read 5, iclass 39, count 0 2006.201.11:31:22.97#ibcon#about to read 6, iclass 39, count 0 2006.201.11:31:22.97#ibcon#read 6, iclass 39, count 0 2006.201.11:31:22.97#ibcon#end of sib2, iclass 39, count 0 2006.201.11:31:22.97#ibcon#*after write, iclass 39, count 0 2006.201.11:31:22.97#ibcon#*before return 0, iclass 39, count 0 2006.201.11:31:22.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:22.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:31:22.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.11:31:22.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.11:31:22.97$vck44/vb=8,4 2006.201.11:31:22.97#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.11:31:22.97#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.11:31:22.97#ibcon#ireg 11 cls_cnt 2 2006.201.11:31:22.97#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:23.03#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:23.03#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:23.03#ibcon#enter wrdev, iclass 2, count 2 2006.201.11:31:23.03#ibcon#first serial, iclass 2, count 2 2006.201.11:31:23.03#ibcon#enter sib2, iclass 2, count 2 2006.201.11:31:23.03#ibcon#flushed, iclass 2, count 2 2006.201.11:31:23.03#ibcon#about to write, iclass 2, count 2 2006.201.11:31:23.03#ibcon#wrote, iclass 2, count 2 2006.201.11:31:23.03#ibcon#about to read 3, iclass 2, count 2 2006.201.11:31:23.05#ibcon#read 3, iclass 2, count 2 2006.201.11:31:23.05#ibcon#about to read 4, iclass 2, count 2 2006.201.11:31:23.05#ibcon#read 4, iclass 2, count 2 2006.201.11:31:23.05#ibcon#about to read 5, iclass 2, count 2 2006.201.11:31:23.05#ibcon#read 5, iclass 2, count 2 2006.201.11:31:23.05#ibcon#about to read 6, iclass 2, count 2 2006.201.11:31:23.05#ibcon#read 6, iclass 2, count 2 2006.201.11:31:23.05#ibcon#end of sib2, iclass 2, count 2 2006.201.11:31:23.05#ibcon#*mode == 0, iclass 2, count 2 2006.201.11:31:23.05#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.11:31:23.05#ibcon#[27=AT08-04\r\n] 2006.201.11:31:23.05#ibcon#*before write, iclass 2, count 2 2006.201.11:31:23.05#ibcon#enter sib2, iclass 2, count 2 2006.201.11:31:23.05#ibcon#flushed, iclass 2, count 2 2006.201.11:31:23.05#ibcon#about to write, iclass 2, count 2 2006.201.11:31:23.05#ibcon#wrote, iclass 2, count 2 2006.201.11:31:23.05#ibcon#about to read 3, iclass 2, count 2 2006.201.11:31:23.08#ibcon#read 3, iclass 2, count 2 2006.201.11:31:23.08#ibcon#about to read 4, iclass 2, count 2 2006.201.11:31:23.08#ibcon#read 4, iclass 2, count 2 2006.201.11:31:23.08#ibcon#about to read 5, iclass 2, count 2 2006.201.11:31:23.08#ibcon#read 5, iclass 2, count 2 2006.201.11:31:23.08#ibcon#about to read 6, iclass 2, count 2 2006.201.11:31:23.08#ibcon#read 6, iclass 2, count 2 2006.201.11:31:23.08#ibcon#end of sib2, iclass 2, count 2 2006.201.11:31:23.08#ibcon#*after write, iclass 2, count 2 2006.201.11:31:23.08#ibcon#*before return 0, iclass 2, count 2 2006.201.11:31:23.08#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:23.08#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.11:31:23.08#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.11:31:23.08#ibcon#ireg 7 cls_cnt 0 2006.201.11:31:23.08#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:23.20#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:23.20#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:23.20#ibcon#enter wrdev, iclass 2, count 0 2006.201.11:31:23.20#ibcon#first serial, iclass 2, count 0 2006.201.11:31:23.20#ibcon#enter sib2, iclass 2, count 0 2006.201.11:31:23.20#ibcon#flushed, iclass 2, count 0 2006.201.11:31:23.20#ibcon#about to write, iclass 2, count 0 2006.201.11:31:23.20#ibcon#wrote, iclass 2, count 0 2006.201.11:31:23.20#ibcon#about to read 3, iclass 2, count 0 2006.201.11:31:23.23#ibcon#read 3, iclass 2, count 0 2006.201.11:31:23.23#ibcon#about to read 4, iclass 2, count 0 2006.201.11:31:23.23#ibcon#read 4, iclass 2, count 0 2006.201.11:31:23.23#ibcon#about to read 5, iclass 2, count 0 2006.201.11:31:23.23#ibcon#read 5, iclass 2, count 0 2006.201.11:31:23.23#ibcon#about to read 6, iclass 2, count 0 2006.201.11:31:23.23#ibcon#read 6, iclass 2, count 0 2006.201.11:31:23.23#ibcon#end of sib2, iclass 2, count 0 2006.201.11:31:23.23#ibcon#*mode == 0, iclass 2, count 0 2006.201.11:31:23.23#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.11:31:23.23#ibcon#[27=USB\r\n] 2006.201.11:31:23.23#ibcon#*before write, iclass 2, count 0 2006.201.11:31:23.23#ibcon#enter sib2, iclass 2, count 0 2006.201.11:31:23.23#ibcon#flushed, iclass 2, count 0 2006.201.11:31:23.23#ibcon#about to write, iclass 2, count 0 2006.201.11:31:23.23#ibcon#wrote, iclass 2, count 0 2006.201.11:31:23.23#ibcon#about to read 3, iclass 2, count 0 2006.201.11:31:23.26#ibcon#read 3, iclass 2, count 0 2006.201.11:31:23.26#ibcon#about to read 4, iclass 2, count 0 2006.201.11:31:23.26#ibcon#read 4, iclass 2, count 0 2006.201.11:31:23.26#ibcon#about to read 5, iclass 2, count 0 2006.201.11:31:23.26#ibcon#read 5, iclass 2, count 0 2006.201.11:31:23.26#ibcon#about to read 6, iclass 2, count 0 2006.201.11:31:23.26#ibcon#read 6, iclass 2, count 0 2006.201.11:31:23.26#ibcon#end of sib2, iclass 2, count 0 2006.201.11:31:23.26#ibcon#*after write, iclass 2, count 0 2006.201.11:31:23.26#ibcon#*before return 0, iclass 2, count 0 2006.201.11:31:23.26#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:23.26#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.11:31:23.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.11:31:23.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.11:31:23.26$vck44/vabw=wide 2006.201.11:31:23.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.11:31:23.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.11:31:23.26#ibcon#ireg 8 cls_cnt 0 2006.201.11:31:23.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:23.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:23.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:23.26#ibcon#enter wrdev, iclass 5, count 0 2006.201.11:31:23.26#ibcon#first serial, iclass 5, count 0 2006.201.11:31:23.26#ibcon#enter sib2, iclass 5, count 0 2006.201.11:31:23.26#ibcon#flushed, iclass 5, count 0 2006.201.11:31:23.26#ibcon#about to write, iclass 5, count 0 2006.201.11:31:23.26#ibcon#wrote, iclass 5, count 0 2006.201.11:31:23.26#ibcon#about to read 3, iclass 5, count 0 2006.201.11:31:23.28#ibcon#read 3, iclass 5, count 0 2006.201.11:31:23.28#ibcon#about to read 4, iclass 5, count 0 2006.201.11:31:23.28#ibcon#read 4, iclass 5, count 0 2006.201.11:31:23.28#ibcon#about to read 5, iclass 5, count 0 2006.201.11:31:23.28#ibcon#read 5, iclass 5, count 0 2006.201.11:31:23.28#ibcon#about to read 6, iclass 5, count 0 2006.201.11:31:23.28#ibcon#read 6, iclass 5, count 0 2006.201.11:31:23.28#ibcon#end of sib2, iclass 5, count 0 2006.201.11:31:23.28#ibcon#*mode == 0, iclass 5, count 0 2006.201.11:31:23.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.11:31:23.28#ibcon#[25=BW32\r\n] 2006.201.11:31:23.28#ibcon#*before write, iclass 5, count 0 2006.201.11:31:23.28#ibcon#enter sib2, iclass 5, count 0 2006.201.11:31:23.28#ibcon#flushed, iclass 5, count 0 2006.201.11:31:23.28#ibcon#about to write, iclass 5, count 0 2006.201.11:31:23.28#ibcon#wrote, iclass 5, count 0 2006.201.11:31:23.28#ibcon#about to read 3, iclass 5, count 0 2006.201.11:31:23.31#ibcon#read 3, iclass 5, count 0 2006.201.11:31:23.31#ibcon#about to read 4, iclass 5, count 0 2006.201.11:31:23.31#ibcon#read 4, iclass 5, count 0 2006.201.11:31:23.31#ibcon#about to read 5, iclass 5, count 0 2006.201.11:31:23.31#ibcon#read 5, iclass 5, count 0 2006.201.11:31:23.31#ibcon#about to read 6, iclass 5, count 0 2006.201.11:31:23.31#ibcon#read 6, iclass 5, count 0 2006.201.11:31:23.31#ibcon#end of sib2, iclass 5, count 0 2006.201.11:31:23.31#ibcon#*after write, iclass 5, count 0 2006.201.11:31:23.31#ibcon#*before return 0, iclass 5, count 0 2006.201.11:31:23.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:23.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.11:31:23.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.11:31:23.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.11:31:23.31$vck44/vbbw=wide 2006.201.11:31:23.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.11:31:23.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.11:31:23.31#ibcon#ireg 8 cls_cnt 0 2006.201.11:31:23.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:31:23.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:31:23.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:31:23.38#ibcon#enter wrdev, iclass 7, count 0 2006.201.11:31:23.38#ibcon#first serial, iclass 7, count 0 2006.201.11:31:23.38#ibcon#enter sib2, iclass 7, count 0 2006.201.11:31:23.38#ibcon#flushed, iclass 7, count 0 2006.201.11:31:23.38#ibcon#about to write, iclass 7, count 0 2006.201.11:31:23.38#ibcon#wrote, iclass 7, count 0 2006.201.11:31:23.38#ibcon#about to read 3, iclass 7, count 0 2006.201.11:31:23.40#ibcon#read 3, iclass 7, count 0 2006.201.11:31:23.40#ibcon#about to read 4, iclass 7, count 0 2006.201.11:31:23.40#ibcon#read 4, iclass 7, count 0 2006.201.11:31:23.40#ibcon#about to read 5, iclass 7, count 0 2006.201.11:31:23.40#ibcon#read 5, iclass 7, count 0 2006.201.11:31:23.40#ibcon#about to read 6, iclass 7, count 0 2006.201.11:31:23.40#ibcon#read 6, iclass 7, count 0 2006.201.11:31:23.40#ibcon#end of sib2, iclass 7, count 0 2006.201.11:31:23.40#ibcon#*mode == 0, iclass 7, count 0 2006.201.11:31:23.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.11:31:23.40#ibcon#[27=BW32\r\n] 2006.201.11:31:23.40#ibcon#*before write, iclass 7, count 0 2006.201.11:31:23.40#ibcon#enter sib2, iclass 7, count 0 2006.201.11:31:23.40#ibcon#flushed, iclass 7, count 0 2006.201.11:31:23.40#ibcon#about to write, iclass 7, count 0 2006.201.11:31:23.40#ibcon#wrote, iclass 7, count 0 2006.201.11:31:23.40#ibcon#about to read 3, iclass 7, count 0 2006.201.11:31:23.43#ibcon#read 3, iclass 7, count 0 2006.201.11:31:23.43#ibcon#about to read 4, iclass 7, count 0 2006.201.11:31:23.43#ibcon#read 4, iclass 7, count 0 2006.201.11:31:23.43#ibcon#about to read 5, iclass 7, count 0 2006.201.11:31:23.43#ibcon#read 5, iclass 7, count 0 2006.201.11:31:23.43#ibcon#about to read 6, iclass 7, count 0 2006.201.11:31:23.43#ibcon#read 6, iclass 7, count 0 2006.201.11:31:23.43#ibcon#end of sib2, iclass 7, count 0 2006.201.11:31:23.43#ibcon#*after write, iclass 7, count 0 2006.201.11:31:23.43#ibcon#*before return 0, iclass 7, count 0 2006.201.11:31:23.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:31:23.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:31:23.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.11:31:23.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.11:31:23.43$setupk4/ifdk4 2006.201.11:31:23.43$ifdk4/lo= 2006.201.11:31:23.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:31:23.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:31:23.43$ifdk4/patch= 2006.201.11:31:23.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:31:23.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:31:23.43$setupk4/!*+20s 2006.201.11:31:26.57#abcon#<5=/04 1.6 3.4 21.401001004.0\r\n> 2006.201.11:31:26.59#abcon#{5=INTERFACE CLEAR} 2006.201.11:31:26.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:31:36.74#abcon#<5=/04 1.6 3.3 21.401001004.0\r\n> 2006.201.11:31:36.76#abcon#{5=INTERFACE CLEAR} 2006.201.11:31:36.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:31:37.89$setupk4/"tpicd 2006.201.11:31:37.89$setupk4/echo=off 2006.201.11:31:37.89$setupk4/xlog=off 2006.201.11:31:37.89:!2006.201.11:32:57 2006.201.11:31:48.13#trakl#Source acquired 2006.201.11:31:49.13#flagr#flagr/antenna,acquired 2006.201.11:32:57.00:preob 2006.201.11:32:57.13/onsource/TRACKING 2006.201.11:32:57.13:!2006.201.11:33:07 2006.201.11:33:07.00:"tape 2006.201.11:33:07.00:"st=record 2006.201.11:33:07.00:data_valid=on 2006.201.11:33:07.00:midob 2006.201.11:33:07.13/onsource/TRACKING 2006.201.11:33:07.13/wx/21.40,1004.0,100 2006.201.11:33:07.19/cable/+6.4711E-03 2006.201.11:33:08.28/va/01,08,usb,yes,28,30 2006.201.11:33:08.28/va/02,07,usb,yes,30,31 2006.201.11:33:08.28/va/03,08,usb,yes,27,28 2006.201.11:33:08.28/va/04,07,usb,yes,31,32 2006.201.11:33:08.28/va/05,04,usb,yes,27,28 2006.201.11:33:08.28/va/06,05,usb,yes,27,27 2006.201.11:33:08.28/va/07,05,usb,yes,26,28 2006.201.11:33:08.28/va/08,04,usb,yes,26,32 2006.201.11:33:08.51/valo/01,524.99,yes,locked 2006.201.11:33:08.51/valo/02,534.99,yes,locked 2006.201.11:33:08.51/valo/03,564.99,yes,locked 2006.201.11:33:08.51/valo/04,624.99,yes,locked 2006.201.11:33:08.51/valo/05,734.99,yes,locked 2006.201.11:33:08.51/valo/06,814.99,yes,locked 2006.201.11:33:08.51/valo/07,864.99,yes,locked 2006.201.11:33:08.51/valo/08,884.99,yes,locked 2006.201.11:33:09.60/vb/01,04,usb,yes,28,26 2006.201.11:33:09.60/vb/02,05,usb,yes,26,26 2006.201.11:33:09.60/vb/03,04,usb,yes,27,30 2006.201.11:33:09.60/vb/04,05,usb,yes,28,27 2006.201.11:33:09.60/vb/05,04,usb,yes,24,27 2006.201.11:33:09.60/vb/06,04,usb,yes,28,25 2006.201.11:33:09.60/vb/07,04,usb,yes,28,28 2006.201.11:33:09.60/vb/08,04,usb,yes,26,29 2006.201.11:33:09.84/vblo/01,629.99,yes,locked 2006.201.11:33:09.84/vblo/02,634.99,yes,locked 2006.201.11:33:09.84/vblo/03,649.99,yes,locked 2006.201.11:33:09.84/vblo/04,679.99,yes,locked 2006.201.11:33:09.84/vblo/05,709.99,yes,locked 2006.201.11:33:09.84/vblo/06,719.99,yes,locked 2006.201.11:33:09.84/vblo/07,734.99,yes,locked 2006.201.11:33:09.84/vblo/08,744.99,yes,locked 2006.201.11:33:09.99/vabw/8 2006.201.11:33:10.14/vbbw/8 2006.201.11:33:10.23/xfe/off,on,15.5 2006.201.11:33:10.60/ifatt/23,28,28,28 2006.201.11:33:11.06/fmout-gps/S +4.56E-07 2006.201.11:33:11.13:!2006.201.11:44:57 2006.201.11:44:57.00:data_valid=off 2006.201.11:44:57.00:"et 2006.201.11:44:57.00:!+3s 2006.201.11:45:00.02:"tape 2006.201.11:45:00.02:postob 2006.201.11:45:00.21/cable/+6.4705E-03 2006.201.11:45:00.21/wx/21.38,1003.9,100 2006.201.11:45:00.29/fmout-gps/S +4.51E-07 2006.201.11:45:00.29:scan_name=201-1147,jd0607,40 2006.201.11:45:00.30:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.201.11:45:01.14#flagr#flagr/antenna,new-source 2006.201.11:45:01.14:checkk5 2006.201.11:45:01.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:45:01.94/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:45:02.33/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:45:02.70/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:45:03.38/chk_obsdata//k5ts1/T2011133??a.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.201.11:45:04.06/chk_obsdata//k5ts2/T2011133??b.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.201.11:45:04.74/chk_obsdata//k5ts3/T2011133??c.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.201.11:45:05.41/chk_obsdata//k5ts4/T2011133??d.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.201.11:45:06.09/k5log//k5ts1_log_newline 2006.201.11:45:06.78/k5log//k5ts2_log_newline 2006.201.11:45:07.46/k5log//k5ts3_log_newline 2006.201.11:45:08.14/k5log//k5ts4_log_newline 2006.201.11:45:08.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:45:08.16:setupk4=1 2006.201.11:45:08.16$setupk4/echo=on 2006.201.11:45:08.16$setupk4/pcalon 2006.201.11:45:08.16$pcalon/"no phase cal control is implemented here 2006.201.11:45:08.16$setupk4/"tpicd=stop 2006.201.11:45:08.16$setupk4/"rec=synch_on 2006.201.11:45:08.16$setupk4/"rec_mode=128 2006.201.11:45:08.16$setupk4/!* 2006.201.11:45:08.16$setupk4/recpk4 2006.201.11:45:08.16$recpk4/recpatch= 2006.201.11:45:08.17$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:45:08.17$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:45:08.17$setupk4/vck44 2006.201.11:45:08.17$vck44/valo=1,524.99 2006.201.11:45:08.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.11:45:08.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.11:45:08.17#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:08.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:08.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:08.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:08.17#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:45:08.17#ibcon#first serial, iclass 14, count 0 2006.201.11:45:08.17#ibcon#enter sib2, iclass 14, count 0 2006.201.11:45:08.17#ibcon#flushed, iclass 14, count 0 2006.201.11:45:08.17#ibcon#about to write, iclass 14, count 0 2006.201.11:45:08.17#ibcon#wrote, iclass 14, count 0 2006.201.11:45:08.17#ibcon#about to read 3, iclass 14, count 0 2006.201.11:45:08.20#ibcon#read 3, iclass 14, count 0 2006.201.11:45:08.20#ibcon#about to read 4, iclass 14, count 0 2006.201.11:45:08.20#ibcon#read 4, iclass 14, count 0 2006.201.11:45:08.20#ibcon#about to read 5, iclass 14, count 0 2006.201.11:45:08.20#ibcon#read 5, iclass 14, count 0 2006.201.11:45:08.20#ibcon#about to read 6, iclass 14, count 0 2006.201.11:45:08.20#ibcon#read 6, iclass 14, count 0 2006.201.11:45:08.20#ibcon#end of sib2, iclass 14, count 0 2006.201.11:45:08.20#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:45:08.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:45:08.20#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:45:08.20#ibcon#*before write, iclass 14, count 0 2006.201.11:45:08.20#ibcon#enter sib2, iclass 14, count 0 2006.201.11:45:08.20#ibcon#flushed, iclass 14, count 0 2006.201.11:45:08.20#ibcon#about to write, iclass 14, count 0 2006.201.11:45:08.20#ibcon#wrote, iclass 14, count 0 2006.201.11:45:08.20#ibcon#about to read 3, iclass 14, count 0 2006.201.11:45:08.25#ibcon#read 3, iclass 14, count 0 2006.201.11:45:08.25#ibcon#about to read 4, iclass 14, count 0 2006.201.11:45:08.25#ibcon#read 4, iclass 14, count 0 2006.201.11:45:08.25#ibcon#about to read 5, iclass 14, count 0 2006.201.11:45:08.25#ibcon#read 5, iclass 14, count 0 2006.201.11:45:08.25#ibcon#about to read 6, iclass 14, count 0 2006.201.11:45:08.25#ibcon#read 6, iclass 14, count 0 2006.201.11:45:08.25#ibcon#end of sib2, iclass 14, count 0 2006.201.11:45:08.25#ibcon#*after write, iclass 14, count 0 2006.201.11:45:08.25#ibcon#*before return 0, iclass 14, count 0 2006.201.11:45:08.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:08.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:08.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:45:08.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:45:08.25$vck44/va=1,8 2006.201.11:45:08.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.11:45:08.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.11:45:08.25#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:08.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:08.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:08.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:08.25#ibcon#enter wrdev, iclass 16, count 2 2006.201.11:45:08.25#ibcon#first serial, iclass 16, count 2 2006.201.11:45:08.25#ibcon#enter sib2, iclass 16, count 2 2006.201.11:45:08.25#ibcon#flushed, iclass 16, count 2 2006.201.11:45:08.25#ibcon#about to write, iclass 16, count 2 2006.201.11:45:08.25#ibcon#wrote, iclass 16, count 2 2006.201.11:45:08.25#ibcon#about to read 3, iclass 16, count 2 2006.201.11:45:08.27#ibcon#read 3, iclass 16, count 2 2006.201.11:45:08.27#ibcon#about to read 4, iclass 16, count 2 2006.201.11:45:08.27#ibcon#read 4, iclass 16, count 2 2006.201.11:45:08.27#ibcon#about to read 5, iclass 16, count 2 2006.201.11:45:08.27#ibcon#read 5, iclass 16, count 2 2006.201.11:45:08.27#ibcon#about to read 6, iclass 16, count 2 2006.201.11:45:08.27#ibcon#read 6, iclass 16, count 2 2006.201.11:45:08.27#ibcon#end of sib2, iclass 16, count 2 2006.201.11:45:08.27#ibcon#*mode == 0, iclass 16, count 2 2006.201.11:45:08.27#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.11:45:08.27#ibcon#[25=AT01-08\r\n] 2006.201.11:45:08.27#ibcon#*before write, iclass 16, count 2 2006.201.11:45:08.27#ibcon#enter sib2, iclass 16, count 2 2006.201.11:45:08.27#ibcon#flushed, iclass 16, count 2 2006.201.11:45:08.27#ibcon#about to write, iclass 16, count 2 2006.201.11:45:08.27#ibcon#wrote, iclass 16, count 2 2006.201.11:45:08.27#ibcon#about to read 3, iclass 16, count 2 2006.201.11:45:08.30#ibcon#read 3, iclass 16, count 2 2006.201.11:45:08.30#ibcon#about to read 4, iclass 16, count 2 2006.201.11:45:08.30#ibcon#read 4, iclass 16, count 2 2006.201.11:45:08.30#ibcon#about to read 5, iclass 16, count 2 2006.201.11:45:08.30#ibcon#read 5, iclass 16, count 2 2006.201.11:45:08.30#ibcon#about to read 6, iclass 16, count 2 2006.201.11:45:08.30#ibcon#read 6, iclass 16, count 2 2006.201.11:45:08.30#ibcon#end of sib2, iclass 16, count 2 2006.201.11:45:08.30#ibcon#*after write, iclass 16, count 2 2006.201.11:45:08.30#ibcon#*before return 0, iclass 16, count 2 2006.201.11:45:08.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:08.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:08.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.11:45:08.30#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:08.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:08.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:08.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:08.42#ibcon#enter wrdev, iclass 16, count 0 2006.201.11:45:08.42#ibcon#first serial, iclass 16, count 0 2006.201.11:45:08.42#ibcon#enter sib2, iclass 16, count 0 2006.201.11:45:08.42#ibcon#flushed, iclass 16, count 0 2006.201.11:45:08.42#ibcon#about to write, iclass 16, count 0 2006.201.11:45:08.42#ibcon#wrote, iclass 16, count 0 2006.201.11:45:08.42#ibcon#about to read 3, iclass 16, count 0 2006.201.11:45:08.44#ibcon#read 3, iclass 16, count 0 2006.201.11:45:08.44#ibcon#about to read 4, iclass 16, count 0 2006.201.11:45:08.44#ibcon#read 4, iclass 16, count 0 2006.201.11:45:08.44#ibcon#about to read 5, iclass 16, count 0 2006.201.11:45:08.44#ibcon#read 5, iclass 16, count 0 2006.201.11:45:08.44#ibcon#about to read 6, iclass 16, count 0 2006.201.11:45:08.44#ibcon#read 6, iclass 16, count 0 2006.201.11:45:08.44#ibcon#end of sib2, iclass 16, count 0 2006.201.11:45:08.44#ibcon#*mode == 0, iclass 16, count 0 2006.201.11:45:08.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.11:45:08.44#ibcon#[25=USB\r\n] 2006.201.11:45:08.44#ibcon#*before write, iclass 16, count 0 2006.201.11:45:08.44#ibcon#enter sib2, iclass 16, count 0 2006.201.11:45:08.44#ibcon#flushed, iclass 16, count 0 2006.201.11:45:08.44#ibcon#about to write, iclass 16, count 0 2006.201.11:45:08.44#ibcon#wrote, iclass 16, count 0 2006.201.11:45:08.44#ibcon#about to read 3, iclass 16, count 0 2006.201.11:45:08.47#ibcon#read 3, iclass 16, count 0 2006.201.11:45:08.47#ibcon#about to read 4, iclass 16, count 0 2006.201.11:45:08.47#ibcon#read 4, iclass 16, count 0 2006.201.11:45:08.47#ibcon#about to read 5, iclass 16, count 0 2006.201.11:45:08.47#ibcon#read 5, iclass 16, count 0 2006.201.11:45:08.47#ibcon#about to read 6, iclass 16, count 0 2006.201.11:45:08.47#ibcon#read 6, iclass 16, count 0 2006.201.11:45:08.47#ibcon#end of sib2, iclass 16, count 0 2006.201.11:45:08.47#ibcon#*after write, iclass 16, count 0 2006.201.11:45:08.47#ibcon#*before return 0, iclass 16, count 0 2006.201.11:45:08.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:08.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:08.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.11:45:08.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.11:45:08.47$vck44/valo=2,534.99 2006.201.11:45:08.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.11:45:08.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.11:45:08.47#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:08.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:08.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:08.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:08.47#ibcon#enter wrdev, iclass 18, count 0 2006.201.11:45:08.47#ibcon#first serial, iclass 18, count 0 2006.201.11:45:08.47#ibcon#enter sib2, iclass 18, count 0 2006.201.11:45:08.47#ibcon#flushed, iclass 18, count 0 2006.201.11:45:08.47#ibcon#about to write, iclass 18, count 0 2006.201.11:45:08.47#ibcon#wrote, iclass 18, count 0 2006.201.11:45:08.47#ibcon#about to read 3, iclass 18, count 0 2006.201.11:45:08.49#ibcon#read 3, iclass 18, count 0 2006.201.11:45:08.49#ibcon#about to read 4, iclass 18, count 0 2006.201.11:45:08.49#ibcon#read 4, iclass 18, count 0 2006.201.11:45:08.49#ibcon#about to read 5, iclass 18, count 0 2006.201.11:45:08.49#ibcon#read 5, iclass 18, count 0 2006.201.11:45:08.49#ibcon#about to read 6, iclass 18, count 0 2006.201.11:45:08.49#ibcon#read 6, iclass 18, count 0 2006.201.11:45:08.49#ibcon#end of sib2, iclass 18, count 0 2006.201.11:45:08.49#ibcon#*mode == 0, iclass 18, count 0 2006.201.11:45:08.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.11:45:08.49#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:45:08.49#ibcon#*before write, iclass 18, count 0 2006.201.11:45:08.49#ibcon#enter sib2, iclass 18, count 0 2006.201.11:45:08.49#ibcon#flushed, iclass 18, count 0 2006.201.11:45:08.49#ibcon#about to write, iclass 18, count 0 2006.201.11:45:08.49#ibcon#wrote, iclass 18, count 0 2006.201.11:45:08.49#ibcon#about to read 3, iclass 18, count 0 2006.201.11:45:08.54#ibcon#read 3, iclass 18, count 0 2006.201.11:45:08.54#ibcon#about to read 4, iclass 18, count 0 2006.201.11:45:08.54#ibcon#read 4, iclass 18, count 0 2006.201.11:45:08.54#ibcon#about to read 5, iclass 18, count 0 2006.201.11:45:08.54#ibcon#read 5, iclass 18, count 0 2006.201.11:45:08.54#ibcon#about to read 6, iclass 18, count 0 2006.201.11:45:08.54#ibcon#read 6, iclass 18, count 0 2006.201.11:45:08.54#ibcon#end of sib2, iclass 18, count 0 2006.201.11:45:08.54#ibcon#*after write, iclass 18, count 0 2006.201.11:45:08.54#ibcon#*before return 0, iclass 18, count 0 2006.201.11:45:08.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:08.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:08.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.11:45:08.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.11:45:08.54$vck44/va=2,7 2006.201.11:45:08.54#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.11:45:08.54#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.11:45:08.54#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:08.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:08.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:08.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:08.59#ibcon#enter wrdev, iclass 20, count 2 2006.201.11:45:08.59#ibcon#first serial, iclass 20, count 2 2006.201.11:45:08.59#ibcon#enter sib2, iclass 20, count 2 2006.201.11:45:08.59#ibcon#flushed, iclass 20, count 2 2006.201.11:45:08.59#ibcon#about to write, iclass 20, count 2 2006.201.11:45:08.59#ibcon#wrote, iclass 20, count 2 2006.201.11:45:08.59#ibcon#about to read 3, iclass 20, count 2 2006.201.11:45:08.61#ibcon#read 3, iclass 20, count 2 2006.201.11:45:08.61#ibcon#about to read 4, iclass 20, count 2 2006.201.11:45:08.61#ibcon#read 4, iclass 20, count 2 2006.201.11:45:08.61#ibcon#about to read 5, iclass 20, count 2 2006.201.11:45:08.61#ibcon#read 5, iclass 20, count 2 2006.201.11:45:08.61#ibcon#about to read 6, iclass 20, count 2 2006.201.11:45:08.61#ibcon#read 6, iclass 20, count 2 2006.201.11:45:08.61#ibcon#end of sib2, iclass 20, count 2 2006.201.11:45:08.61#ibcon#*mode == 0, iclass 20, count 2 2006.201.11:45:08.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.11:45:08.61#ibcon#[25=AT02-07\r\n] 2006.201.11:45:08.61#ibcon#*before write, iclass 20, count 2 2006.201.11:45:08.61#ibcon#enter sib2, iclass 20, count 2 2006.201.11:45:08.61#ibcon#flushed, iclass 20, count 2 2006.201.11:45:08.61#ibcon#about to write, iclass 20, count 2 2006.201.11:45:08.61#ibcon#wrote, iclass 20, count 2 2006.201.11:45:08.61#ibcon#about to read 3, iclass 20, count 2 2006.201.11:45:08.64#ibcon#read 3, iclass 20, count 2 2006.201.11:45:08.64#ibcon#about to read 4, iclass 20, count 2 2006.201.11:45:08.64#ibcon#read 4, iclass 20, count 2 2006.201.11:45:08.64#ibcon#about to read 5, iclass 20, count 2 2006.201.11:45:08.64#ibcon#read 5, iclass 20, count 2 2006.201.11:45:08.64#ibcon#about to read 6, iclass 20, count 2 2006.201.11:45:08.64#ibcon#read 6, iclass 20, count 2 2006.201.11:45:08.64#ibcon#end of sib2, iclass 20, count 2 2006.201.11:45:08.64#ibcon#*after write, iclass 20, count 2 2006.201.11:45:08.64#ibcon#*before return 0, iclass 20, count 2 2006.201.11:45:08.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:08.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:08.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.11:45:08.64#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:08.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:08.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:08.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:08.76#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:45:08.76#ibcon#first serial, iclass 20, count 0 2006.201.11:45:08.76#ibcon#enter sib2, iclass 20, count 0 2006.201.11:45:08.76#ibcon#flushed, iclass 20, count 0 2006.201.11:45:08.76#ibcon#about to write, iclass 20, count 0 2006.201.11:45:08.76#ibcon#wrote, iclass 20, count 0 2006.201.11:45:08.76#ibcon#about to read 3, iclass 20, count 0 2006.201.11:45:08.78#ibcon#read 3, iclass 20, count 0 2006.201.11:45:08.78#ibcon#about to read 4, iclass 20, count 0 2006.201.11:45:08.78#ibcon#read 4, iclass 20, count 0 2006.201.11:45:08.78#ibcon#about to read 5, iclass 20, count 0 2006.201.11:45:08.78#ibcon#read 5, iclass 20, count 0 2006.201.11:45:08.78#ibcon#about to read 6, iclass 20, count 0 2006.201.11:45:08.78#ibcon#read 6, iclass 20, count 0 2006.201.11:45:08.78#ibcon#end of sib2, iclass 20, count 0 2006.201.11:45:08.78#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:45:08.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:45:08.78#ibcon#[25=USB\r\n] 2006.201.11:45:08.78#ibcon#*before write, iclass 20, count 0 2006.201.11:45:08.78#ibcon#enter sib2, iclass 20, count 0 2006.201.11:45:08.78#ibcon#flushed, iclass 20, count 0 2006.201.11:45:08.78#ibcon#about to write, iclass 20, count 0 2006.201.11:45:08.78#ibcon#wrote, iclass 20, count 0 2006.201.11:45:08.78#ibcon#about to read 3, iclass 20, count 0 2006.201.11:45:08.81#ibcon#read 3, iclass 20, count 0 2006.201.11:45:08.81#ibcon#about to read 4, iclass 20, count 0 2006.201.11:45:08.81#ibcon#read 4, iclass 20, count 0 2006.201.11:45:08.81#ibcon#about to read 5, iclass 20, count 0 2006.201.11:45:08.81#ibcon#read 5, iclass 20, count 0 2006.201.11:45:08.81#ibcon#about to read 6, iclass 20, count 0 2006.201.11:45:08.81#ibcon#read 6, iclass 20, count 0 2006.201.11:45:08.81#ibcon#end of sib2, iclass 20, count 0 2006.201.11:45:08.81#ibcon#*after write, iclass 20, count 0 2006.201.11:45:08.81#ibcon#*before return 0, iclass 20, count 0 2006.201.11:45:08.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:08.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:08.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:45:08.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:45:08.81$vck44/valo=3,564.99 2006.201.11:45:08.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.11:45:08.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.11:45:08.81#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:08.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:08.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:08.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:08.81#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:45:08.81#ibcon#first serial, iclass 22, count 0 2006.201.11:45:08.81#ibcon#enter sib2, iclass 22, count 0 2006.201.11:45:08.81#ibcon#flushed, iclass 22, count 0 2006.201.11:45:08.81#ibcon#about to write, iclass 22, count 0 2006.201.11:45:08.81#ibcon#wrote, iclass 22, count 0 2006.201.11:45:08.81#ibcon#about to read 3, iclass 22, count 0 2006.201.11:45:08.83#ibcon#read 3, iclass 22, count 0 2006.201.11:45:08.83#ibcon#about to read 4, iclass 22, count 0 2006.201.11:45:08.83#ibcon#read 4, iclass 22, count 0 2006.201.11:45:08.83#ibcon#about to read 5, iclass 22, count 0 2006.201.11:45:08.83#ibcon#read 5, iclass 22, count 0 2006.201.11:45:08.83#ibcon#about to read 6, iclass 22, count 0 2006.201.11:45:08.83#ibcon#read 6, iclass 22, count 0 2006.201.11:45:08.83#ibcon#end of sib2, iclass 22, count 0 2006.201.11:45:08.83#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:45:08.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:45:08.83#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:45:08.83#ibcon#*before write, iclass 22, count 0 2006.201.11:45:08.83#ibcon#enter sib2, iclass 22, count 0 2006.201.11:45:08.83#ibcon#flushed, iclass 22, count 0 2006.201.11:45:08.83#ibcon#about to write, iclass 22, count 0 2006.201.11:45:08.83#ibcon#wrote, iclass 22, count 0 2006.201.11:45:08.83#ibcon#about to read 3, iclass 22, count 0 2006.201.11:45:08.88#ibcon#read 3, iclass 22, count 0 2006.201.11:45:08.88#ibcon#about to read 4, iclass 22, count 0 2006.201.11:45:08.88#ibcon#read 4, iclass 22, count 0 2006.201.11:45:08.88#ibcon#about to read 5, iclass 22, count 0 2006.201.11:45:08.88#ibcon#read 5, iclass 22, count 0 2006.201.11:45:08.88#ibcon#about to read 6, iclass 22, count 0 2006.201.11:45:08.88#ibcon#read 6, iclass 22, count 0 2006.201.11:45:08.88#ibcon#end of sib2, iclass 22, count 0 2006.201.11:45:08.88#ibcon#*after write, iclass 22, count 0 2006.201.11:45:08.88#ibcon#*before return 0, iclass 22, count 0 2006.201.11:45:08.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:08.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:08.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:45:08.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:45:08.88$vck44/va=3,8 2006.201.11:45:08.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.11:45:08.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.11:45:08.88#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:08.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:08.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:08.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:08.93#ibcon#enter wrdev, iclass 24, count 2 2006.201.11:45:08.93#ibcon#first serial, iclass 24, count 2 2006.201.11:45:08.93#ibcon#enter sib2, iclass 24, count 2 2006.201.11:45:08.93#ibcon#flushed, iclass 24, count 2 2006.201.11:45:08.93#ibcon#about to write, iclass 24, count 2 2006.201.11:45:08.93#ibcon#wrote, iclass 24, count 2 2006.201.11:45:08.93#ibcon#about to read 3, iclass 24, count 2 2006.201.11:45:08.95#ibcon#read 3, iclass 24, count 2 2006.201.11:45:08.95#ibcon#about to read 4, iclass 24, count 2 2006.201.11:45:08.95#ibcon#read 4, iclass 24, count 2 2006.201.11:45:08.95#ibcon#about to read 5, iclass 24, count 2 2006.201.11:45:08.95#ibcon#read 5, iclass 24, count 2 2006.201.11:45:08.95#ibcon#about to read 6, iclass 24, count 2 2006.201.11:45:08.95#ibcon#read 6, iclass 24, count 2 2006.201.11:45:08.95#ibcon#end of sib2, iclass 24, count 2 2006.201.11:45:08.95#ibcon#*mode == 0, iclass 24, count 2 2006.201.11:45:08.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.11:45:08.95#ibcon#[25=AT03-08\r\n] 2006.201.11:45:08.95#ibcon#*before write, iclass 24, count 2 2006.201.11:45:08.95#ibcon#enter sib2, iclass 24, count 2 2006.201.11:45:08.95#ibcon#flushed, iclass 24, count 2 2006.201.11:45:08.95#ibcon#about to write, iclass 24, count 2 2006.201.11:45:08.95#ibcon#wrote, iclass 24, count 2 2006.201.11:45:08.95#ibcon#about to read 3, iclass 24, count 2 2006.201.11:45:08.98#ibcon#read 3, iclass 24, count 2 2006.201.11:45:08.98#ibcon#about to read 4, iclass 24, count 2 2006.201.11:45:08.98#ibcon#read 4, iclass 24, count 2 2006.201.11:45:08.98#ibcon#about to read 5, iclass 24, count 2 2006.201.11:45:08.98#ibcon#read 5, iclass 24, count 2 2006.201.11:45:08.98#ibcon#about to read 6, iclass 24, count 2 2006.201.11:45:08.98#ibcon#read 6, iclass 24, count 2 2006.201.11:45:08.98#ibcon#end of sib2, iclass 24, count 2 2006.201.11:45:08.98#ibcon#*after write, iclass 24, count 2 2006.201.11:45:08.98#ibcon#*before return 0, iclass 24, count 2 2006.201.11:45:08.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:08.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:08.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.11:45:08.98#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:08.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:09.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:09.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:09.10#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:45:09.10#ibcon#first serial, iclass 24, count 0 2006.201.11:45:09.10#ibcon#enter sib2, iclass 24, count 0 2006.201.11:45:09.10#ibcon#flushed, iclass 24, count 0 2006.201.11:45:09.10#ibcon#about to write, iclass 24, count 0 2006.201.11:45:09.10#ibcon#wrote, iclass 24, count 0 2006.201.11:45:09.10#ibcon#about to read 3, iclass 24, count 0 2006.201.11:45:09.12#ibcon#read 3, iclass 24, count 0 2006.201.11:45:09.12#ibcon#about to read 4, iclass 24, count 0 2006.201.11:45:09.12#ibcon#read 4, iclass 24, count 0 2006.201.11:45:09.12#ibcon#about to read 5, iclass 24, count 0 2006.201.11:45:09.12#ibcon#read 5, iclass 24, count 0 2006.201.11:45:09.12#ibcon#about to read 6, iclass 24, count 0 2006.201.11:45:09.12#ibcon#read 6, iclass 24, count 0 2006.201.11:45:09.12#ibcon#end of sib2, iclass 24, count 0 2006.201.11:45:09.12#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:45:09.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:45:09.12#ibcon#[25=USB\r\n] 2006.201.11:45:09.12#ibcon#*before write, iclass 24, count 0 2006.201.11:45:09.12#ibcon#enter sib2, iclass 24, count 0 2006.201.11:45:09.12#ibcon#flushed, iclass 24, count 0 2006.201.11:45:09.12#ibcon#about to write, iclass 24, count 0 2006.201.11:45:09.12#ibcon#wrote, iclass 24, count 0 2006.201.11:45:09.12#ibcon#about to read 3, iclass 24, count 0 2006.201.11:45:09.15#ibcon#read 3, iclass 24, count 0 2006.201.11:45:09.15#ibcon#about to read 4, iclass 24, count 0 2006.201.11:45:09.15#ibcon#read 4, iclass 24, count 0 2006.201.11:45:09.15#ibcon#about to read 5, iclass 24, count 0 2006.201.11:45:09.15#ibcon#read 5, iclass 24, count 0 2006.201.11:45:09.15#ibcon#about to read 6, iclass 24, count 0 2006.201.11:45:09.15#ibcon#read 6, iclass 24, count 0 2006.201.11:45:09.15#ibcon#end of sib2, iclass 24, count 0 2006.201.11:45:09.15#ibcon#*after write, iclass 24, count 0 2006.201.11:45:09.15#ibcon#*before return 0, iclass 24, count 0 2006.201.11:45:09.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:09.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:09.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:45:09.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:45:09.15$vck44/valo=4,624.99 2006.201.11:45:09.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.11:45:09.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.11:45:09.15#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:09.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:09.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:09.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:09.15#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:45:09.15#ibcon#first serial, iclass 26, count 0 2006.201.11:45:09.15#ibcon#enter sib2, iclass 26, count 0 2006.201.11:45:09.15#ibcon#flushed, iclass 26, count 0 2006.201.11:45:09.15#ibcon#about to write, iclass 26, count 0 2006.201.11:45:09.15#ibcon#wrote, iclass 26, count 0 2006.201.11:45:09.15#ibcon#about to read 3, iclass 26, count 0 2006.201.11:45:09.17#ibcon#read 3, iclass 26, count 0 2006.201.11:45:09.17#ibcon#about to read 4, iclass 26, count 0 2006.201.11:45:09.17#ibcon#read 4, iclass 26, count 0 2006.201.11:45:09.17#ibcon#about to read 5, iclass 26, count 0 2006.201.11:45:09.17#ibcon#read 5, iclass 26, count 0 2006.201.11:45:09.17#ibcon#about to read 6, iclass 26, count 0 2006.201.11:45:09.17#ibcon#read 6, iclass 26, count 0 2006.201.11:45:09.17#ibcon#end of sib2, iclass 26, count 0 2006.201.11:45:09.17#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:45:09.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:45:09.17#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:45:09.17#ibcon#*before write, iclass 26, count 0 2006.201.11:45:09.17#ibcon#enter sib2, iclass 26, count 0 2006.201.11:45:09.17#ibcon#flushed, iclass 26, count 0 2006.201.11:45:09.17#ibcon#about to write, iclass 26, count 0 2006.201.11:45:09.17#ibcon#wrote, iclass 26, count 0 2006.201.11:45:09.17#ibcon#about to read 3, iclass 26, count 0 2006.201.11:45:09.21#ibcon#read 3, iclass 26, count 0 2006.201.11:45:09.21#ibcon#about to read 4, iclass 26, count 0 2006.201.11:45:09.21#ibcon#read 4, iclass 26, count 0 2006.201.11:45:09.21#ibcon#about to read 5, iclass 26, count 0 2006.201.11:45:09.21#ibcon#read 5, iclass 26, count 0 2006.201.11:45:09.21#ibcon#about to read 6, iclass 26, count 0 2006.201.11:45:09.21#ibcon#read 6, iclass 26, count 0 2006.201.11:45:09.21#ibcon#end of sib2, iclass 26, count 0 2006.201.11:45:09.21#ibcon#*after write, iclass 26, count 0 2006.201.11:45:09.21#ibcon#*before return 0, iclass 26, count 0 2006.201.11:45:09.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:09.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:09.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:45:09.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:45:09.21$vck44/va=4,7 2006.201.11:45:09.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.11:45:09.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.11:45:09.21#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:09.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:09.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:09.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:09.27#ibcon#enter wrdev, iclass 28, count 2 2006.201.11:45:09.27#ibcon#first serial, iclass 28, count 2 2006.201.11:45:09.27#ibcon#enter sib2, iclass 28, count 2 2006.201.11:45:09.27#ibcon#flushed, iclass 28, count 2 2006.201.11:45:09.27#ibcon#about to write, iclass 28, count 2 2006.201.11:45:09.27#ibcon#wrote, iclass 28, count 2 2006.201.11:45:09.27#ibcon#about to read 3, iclass 28, count 2 2006.201.11:45:09.29#ibcon#read 3, iclass 28, count 2 2006.201.11:45:09.29#ibcon#about to read 4, iclass 28, count 2 2006.201.11:45:09.29#ibcon#read 4, iclass 28, count 2 2006.201.11:45:09.29#ibcon#about to read 5, iclass 28, count 2 2006.201.11:45:09.29#ibcon#read 5, iclass 28, count 2 2006.201.11:45:09.29#ibcon#about to read 6, iclass 28, count 2 2006.201.11:45:09.29#ibcon#read 6, iclass 28, count 2 2006.201.11:45:09.29#ibcon#end of sib2, iclass 28, count 2 2006.201.11:45:09.29#ibcon#*mode == 0, iclass 28, count 2 2006.201.11:45:09.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.11:45:09.29#ibcon#[25=AT04-07\r\n] 2006.201.11:45:09.29#ibcon#*before write, iclass 28, count 2 2006.201.11:45:09.29#ibcon#enter sib2, iclass 28, count 2 2006.201.11:45:09.29#ibcon#flushed, iclass 28, count 2 2006.201.11:45:09.29#ibcon#about to write, iclass 28, count 2 2006.201.11:45:09.29#ibcon#wrote, iclass 28, count 2 2006.201.11:45:09.29#ibcon#about to read 3, iclass 28, count 2 2006.201.11:45:09.32#ibcon#read 3, iclass 28, count 2 2006.201.11:45:09.32#ibcon#about to read 4, iclass 28, count 2 2006.201.11:45:09.32#ibcon#read 4, iclass 28, count 2 2006.201.11:45:09.32#ibcon#about to read 5, iclass 28, count 2 2006.201.11:45:09.32#ibcon#read 5, iclass 28, count 2 2006.201.11:45:09.32#ibcon#about to read 6, iclass 28, count 2 2006.201.11:45:09.32#ibcon#read 6, iclass 28, count 2 2006.201.11:45:09.32#ibcon#end of sib2, iclass 28, count 2 2006.201.11:45:09.32#ibcon#*after write, iclass 28, count 2 2006.201.11:45:09.32#ibcon#*before return 0, iclass 28, count 2 2006.201.11:45:09.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:09.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:09.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.11:45:09.32#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:09.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:09.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:09.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:09.44#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:45:09.44#ibcon#first serial, iclass 28, count 0 2006.201.11:45:09.44#ibcon#enter sib2, iclass 28, count 0 2006.201.11:45:09.44#ibcon#flushed, iclass 28, count 0 2006.201.11:45:09.44#ibcon#about to write, iclass 28, count 0 2006.201.11:45:09.44#ibcon#wrote, iclass 28, count 0 2006.201.11:45:09.44#ibcon#about to read 3, iclass 28, count 0 2006.201.11:45:09.46#ibcon#read 3, iclass 28, count 0 2006.201.11:45:09.46#ibcon#about to read 4, iclass 28, count 0 2006.201.11:45:09.46#ibcon#read 4, iclass 28, count 0 2006.201.11:45:09.46#ibcon#about to read 5, iclass 28, count 0 2006.201.11:45:09.46#ibcon#read 5, iclass 28, count 0 2006.201.11:45:09.46#ibcon#about to read 6, iclass 28, count 0 2006.201.11:45:09.46#ibcon#read 6, iclass 28, count 0 2006.201.11:45:09.46#ibcon#end of sib2, iclass 28, count 0 2006.201.11:45:09.46#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:45:09.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:45:09.46#ibcon#[25=USB\r\n] 2006.201.11:45:09.46#ibcon#*before write, iclass 28, count 0 2006.201.11:45:09.46#ibcon#enter sib2, iclass 28, count 0 2006.201.11:45:09.46#ibcon#flushed, iclass 28, count 0 2006.201.11:45:09.46#ibcon#about to write, iclass 28, count 0 2006.201.11:45:09.46#ibcon#wrote, iclass 28, count 0 2006.201.11:45:09.46#ibcon#about to read 3, iclass 28, count 0 2006.201.11:45:09.49#ibcon#read 3, iclass 28, count 0 2006.201.11:45:09.49#ibcon#about to read 4, iclass 28, count 0 2006.201.11:45:09.49#ibcon#read 4, iclass 28, count 0 2006.201.11:45:09.49#ibcon#about to read 5, iclass 28, count 0 2006.201.11:45:09.49#ibcon#read 5, iclass 28, count 0 2006.201.11:45:09.49#ibcon#about to read 6, iclass 28, count 0 2006.201.11:45:09.49#ibcon#read 6, iclass 28, count 0 2006.201.11:45:09.49#ibcon#end of sib2, iclass 28, count 0 2006.201.11:45:09.49#ibcon#*after write, iclass 28, count 0 2006.201.11:45:09.49#ibcon#*before return 0, iclass 28, count 0 2006.201.11:45:09.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:09.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:09.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:45:09.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:45:09.49$vck44/valo=5,734.99 2006.201.11:45:09.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.11:45:09.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.11:45:09.49#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:09.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:09.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:09.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:09.49#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:45:09.49#ibcon#first serial, iclass 30, count 0 2006.201.11:45:09.49#ibcon#enter sib2, iclass 30, count 0 2006.201.11:45:09.49#ibcon#flushed, iclass 30, count 0 2006.201.11:45:09.49#ibcon#about to write, iclass 30, count 0 2006.201.11:45:09.49#ibcon#wrote, iclass 30, count 0 2006.201.11:45:09.49#ibcon#about to read 3, iclass 30, count 0 2006.201.11:45:09.51#ibcon#read 3, iclass 30, count 0 2006.201.11:45:09.51#ibcon#about to read 4, iclass 30, count 0 2006.201.11:45:09.51#ibcon#read 4, iclass 30, count 0 2006.201.11:45:09.51#ibcon#about to read 5, iclass 30, count 0 2006.201.11:45:09.51#ibcon#read 5, iclass 30, count 0 2006.201.11:45:09.51#ibcon#about to read 6, iclass 30, count 0 2006.201.11:45:09.51#ibcon#read 6, iclass 30, count 0 2006.201.11:45:09.51#ibcon#end of sib2, iclass 30, count 0 2006.201.11:45:09.51#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:45:09.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:45:09.51#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:45:09.51#ibcon#*before write, iclass 30, count 0 2006.201.11:45:09.51#ibcon#enter sib2, iclass 30, count 0 2006.201.11:45:09.51#ibcon#flushed, iclass 30, count 0 2006.201.11:45:09.51#ibcon#about to write, iclass 30, count 0 2006.201.11:45:09.51#ibcon#wrote, iclass 30, count 0 2006.201.11:45:09.51#ibcon#about to read 3, iclass 30, count 0 2006.201.11:45:09.56#ibcon#read 3, iclass 30, count 0 2006.201.11:45:09.56#ibcon#about to read 4, iclass 30, count 0 2006.201.11:45:09.56#ibcon#read 4, iclass 30, count 0 2006.201.11:45:09.56#ibcon#about to read 5, iclass 30, count 0 2006.201.11:45:09.56#ibcon#read 5, iclass 30, count 0 2006.201.11:45:09.56#ibcon#about to read 6, iclass 30, count 0 2006.201.11:45:09.56#ibcon#read 6, iclass 30, count 0 2006.201.11:45:09.56#ibcon#end of sib2, iclass 30, count 0 2006.201.11:45:09.56#ibcon#*after write, iclass 30, count 0 2006.201.11:45:09.56#ibcon#*before return 0, iclass 30, count 0 2006.201.11:45:09.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:09.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:09.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:45:09.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:45:09.56$vck44/va=5,4 2006.201.11:45:09.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.11:45:09.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.11:45:09.56#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:09.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:09.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:09.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:09.61#ibcon#enter wrdev, iclass 32, count 2 2006.201.11:45:09.61#ibcon#first serial, iclass 32, count 2 2006.201.11:45:09.61#ibcon#enter sib2, iclass 32, count 2 2006.201.11:45:09.61#ibcon#flushed, iclass 32, count 2 2006.201.11:45:09.61#ibcon#about to write, iclass 32, count 2 2006.201.11:45:09.61#ibcon#wrote, iclass 32, count 2 2006.201.11:45:09.61#ibcon#about to read 3, iclass 32, count 2 2006.201.11:45:09.63#ibcon#read 3, iclass 32, count 2 2006.201.11:45:09.63#ibcon#about to read 4, iclass 32, count 2 2006.201.11:45:09.63#ibcon#read 4, iclass 32, count 2 2006.201.11:45:09.63#ibcon#about to read 5, iclass 32, count 2 2006.201.11:45:09.63#ibcon#read 5, iclass 32, count 2 2006.201.11:45:09.63#ibcon#about to read 6, iclass 32, count 2 2006.201.11:45:09.63#ibcon#read 6, iclass 32, count 2 2006.201.11:45:09.63#ibcon#end of sib2, iclass 32, count 2 2006.201.11:45:09.63#ibcon#*mode == 0, iclass 32, count 2 2006.201.11:45:09.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.11:45:09.63#ibcon#[25=AT05-04\r\n] 2006.201.11:45:09.63#ibcon#*before write, iclass 32, count 2 2006.201.11:45:09.63#ibcon#enter sib2, iclass 32, count 2 2006.201.11:45:09.63#ibcon#flushed, iclass 32, count 2 2006.201.11:45:09.63#ibcon#about to write, iclass 32, count 2 2006.201.11:45:09.63#ibcon#wrote, iclass 32, count 2 2006.201.11:45:09.63#ibcon#about to read 3, iclass 32, count 2 2006.201.11:45:09.66#ibcon#read 3, iclass 32, count 2 2006.201.11:45:09.66#ibcon#about to read 4, iclass 32, count 2 2006.201.11:45:09.66#ibcon#read 4, iclass 32, count 2 2006.201.11:45:09.66#ibcon#about to read 5, iclass 32, count 2 2006.201.11:45:09.66#ibcon#read 5, iclass 32, count 2 2006.201.11:45:09.66#ibcon#about to read 6, iclass 32, count 2 2006.201.11:45:09.66#ibcon#read 6, iclass 32, count 2 2006.201.11:45:09.66#ibcon#end of sib2, iclass 32, count 2 2006.201.11:45:09.66#ibcon#*after write, iclass 32, count 2 2006.201.11:45:09.66#ibcon#*before return 0, iclass 32, count 2 2006.201.11:45:09.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:09.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:09.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.11:45:09.66#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:09.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:09.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:09.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:09.78#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:45:09.78#ibcon#first serial, iclass 32, count 0 2006.201.11:45:09.78#ibcon#enter sib2, iclass 32, count 0 2006.201.11:45:09.78#ibcon#flushed, iclass 32, count 0 2006.201.11:45:09.78#ibcon#about to write, iclass 32, count 0 2006.201.11:45:09.78#ibcon#wrote, iclass 32, count 0 2006.201.11:45:09.78#ibcon#about to read 3, iclass 32, count 0 2006.201.11:45:09.80#ibcon#read 3, iclass 32, count 0 2006.201.11:45:09.80#ibcon#about to read 4, iclass 32, count 0 2006.201.11:45:09.80#ibcon#read 4, iclass 32, count 0 2006.201.11:45:09.80#ibcon#about to read 5, iclass 32, count 0 2006.201.11:45:09.80#ibcon#read 5, iclass 32, count 0 2006.201.11:45:09.80#ibcon#about to read 6, iclass 32, count 0 2006.201.11:45:09.80#ibcon#read 6, iclass 32, count 0 2006.201.11:45:09.80#ibcon#end of sib2, iclass 32, count 0 2006.201.11:45:09.80#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:45:09.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:45:09.80#ibcon#[25=USB\r\n] 2006.201.11:45:09.80#ibcon#*before write, iclass 32, count 0 2006.201.11:45:09.80#ibcon#enter sib2, iclass 32, count 0 2006.201.11:45:09.80#ibcon#flushed, iclass 32, count 0 2006.201.11:45:09.80#ibcon#about to write, iclass 32, count 0 2006.201.11:45:09.80#ibcon#wrote, iclass 32, count 0 2006.201.11:45:09.80#ibcon#about to read 3, iclass 32, count 0 2006.201.11:45:09.83#ibcon#read 3, iclass 32, count 0 2006.201.11:45:09.83#ibcon#about to read 4, iclass 32, count 0 2006.201.11:45:09.83#ibcon#read 4, iclass 32, count 0 2006.201.11:45:09.83#ibcon#about to read 5, iclass 32, count 0 2006.201.11:45:09.83#ibcon#read 5, iclass 32, count 0 2006.201.11:45:09.83#ibcon#about to read 6, iclass 32, count 0 2006.201.11:45:09.83#ibcon#read 6, iclass 32, count 0 2006.201.11:45:09.83#ibcon#end of sib2, iclass 32, count 0 2006.201.11:45:09.83#ibcon#*after write, iclass 32, count 0 2006.201.11:45:09.83#ibcon#*before return 0, iclass 32, count 0 2006.201.11:45:09.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:09.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:09.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:45:09.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:45:09.83$vck44/valo=6,814.99 2006.201.11:45:09.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.11:45:09.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.11:45:09.83#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:09.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:09.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:09.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:09.83#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:45:09.83#ibcon#first serial, iclass 34, count 0 2006.201.11:45:09.83#ibcon#enter sib2, iclass 34, count 0 2006.201.11:45:09.83#ibcon#flushed, iclass 34, count 0 2006.201.11:45:09.83#ibcon#about to write, iclass 34, count 0 2006.201.11:45:09.83#ibcon#wrote, iclass 34, count 0 2006.201.11:45:09.83#ibcon#about to read 3, iclass 34, count 0 2006.201.11:45:09.85#ibcon#read 3, iclass 34, count 0 2006.201.11:45:09.85#ibcon#about to read 4, iclass 34, count 0 2006.201.11:45:09.85#ibcon#read 4, iclass 34, count 0 2006.201.11:45:09.85#ibcon#about to read 5, iclass 34, count 0 2006.201.11:45:09.85#ibcon#read 5, iclass 34, count 0 2006.201.11:45:09.85#ibcon#about to read 6, iclass 34, count 0 2006.201.11:45:09.85#ibcon#read 6, iclass 34, count 0 2006.201.11:45:09.85#ibcon#end of sib2, iclass 34, count 0 2006.201.11:45:09.85#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:45:09.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:45:09.85#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:45:09.85#ibcon#*before write, iclass 34, count 0 2006.201.11:45:09.85#ibcon#enter sib2, iclass 34, count 0 2006.201.11:45:09.85#ibcon#flushed, iclass 34, count 0 2006.201.11:45:09.85#ibcon#about to write, iclass 34, count 0 2006.201.11:45:09.85#ibcon#wrote, iclass 34, count 0 2006.201.11:45:09.85#ibcon#about to read 3, iclass 34, count 0 2006.201.11:45:09.90#ibcon#read 3, iclass 34, count 0 2006.201.11:45:09.90#ibcon#about to read 4, iclass 34, count 0 2006.201.11:45:09.90#ibcon#read 4, iclass 34, count 0 2006.201.11:45:09.90#ibcon#about to read 5, iclass 34, count 0 2006.201.11:45:09.90#ibcon#read 5, iclass 34, count 0 2006.201.11:45:09.90#ibcon#about to read 6, iclass 34, count 0 2006.201.11:45:09.90#ibcon#read 6, iclass 34, count 0 2006.201.11:45:09.90#ibcon#end of sib2, iclass 34, count 0 2006.201.11:45:09.90#ibcon#*after write, iclass 34, count 0 2006.201.11:45:09.90#ibcon#*before return 0, iclass 34, count 0 2006.201.11:45:09.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:09.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:09.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:45:09.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:45:09.90$vck44/va=6,5 2006.201.11:45:09.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.11:45:09.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.11:45:09.90#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:09.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:09.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:09.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:09.95#ibcon#enter wrdev, iclass 36, count 2 2006.201.11:45:09.95#ibcon#first serial, iclass 36, count 2 2006.201.11:45:09.95#ibcon#enter sib2, iclass 36, count 2 2006.201.11:45:09.95#ibcon#flushed, iclass 36, count 2 2006.201.11:45:09.95#ibcon#about to write, iclass 36, count 2 2006.201.11:45:09.95#ibcon#wrote, iclass 36, count 2 2006.201.11:45:09.95#ibcon#about to read 3, iclass 36, count 2 2006.201.11:45:09.97#ibcon#read 3, iclass 36, count 2 2006.201.11:45:09.97#ibcon#about to read 4, iclass 36, count 2 2006.201.11:45:09.97#ibcon#read 4, iclass 36, count 2 2006.201.11:45:09.97#ibcon#about to read 5, iclass 36, count 2 2006.201.11:45:09.97#ibcon#read 5, iclass 36, count 2 2006.201.11:45:09.97#ibcon#about to read 6, iclass 36, count 2 2006.201.11:45:09.97#ibcon#read 6, iclass 36, count 2 2006.201.11:45:09.97#ibcon#end of sib2, iclass 36, count 2 2006.201.11:45:09.97#ibcon#*mode == 0, iclass 36, count 2 2006.201.11:45:09.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.11:45:09.97#ibcon#[25=AT06-05\r\n] 2006.201.11:45:09.97#ibcon#*before write, iclass 36, count 2 2006.201.11:45:09.97#ibcon#enter sib2, iclass 36, count 2 2006.201.11:45:09.97#ibcon#flushed, iclass 36, count 2 2006.201.11:45:09.97#ibcon#about to write, iclass 36, count 2 2006.201.11:45:09.97#ibcon#wrote, iclass 36, count 2 2006.201.11:45:09.97#ibcon#about to read 3, iclass 36, count 2 2006.201.11:45:10.00#ibcon#read 3, iclass 36, count 2 2006.201.11:45:10.00#ibcon#about to read 4, iclass 36, count 2 2006.201.11:45:10.00#ibcon#read 4, iclass 36, count 2 2006.201.11:45:10.00#ibcon#about to read 5, iclass 36, count 2 2006.201.11:45:10.00#ibcon#read 5, iclass 36, count 2 2006.201.11:45:10.00#ibcon#about to read 6, iclass 36, count 2 2006.201.11:45:10.00#ibcon#read 6, iclass 36, count 2 2006.201.11:45:10.00#ibcon#end of sib2, iclass 36, count 2 2006.201.11:45:10.00#ibcon#*after write, iclass 36, count 2 2006.201.11:45:10.00#ibcon#*before return 0, iclass 36, count 2 2006.201.11:45:10.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:10.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:10.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.11:45:10.00#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:10.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:10.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:10.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:10.12#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:45:10.12#ibcon#first serial, iclass 36, count 0 2006.201.11:45:10.12#ibcon#enter sib2, iclass 36, count 0 2006.201.11:45:10.12#ibcon#flushed, iclass 36, count 0 2006.201.11:45:10.12#ibcon#about to write, iclass 36, count 0 2006.201.11:45:10.12#ibcon#wrote, iclass 36, count 0 2006.201.11:45:10.12#ibcon#about to read 3, iclass 36, count 0 2006.201.11:45:10.14#ibcon#read 3, iclass 36, count 0 2006.201.11:45:10.14#ibcon#about to read 4, iclass 36, count 0 2006.201.11:45:10.14#ibcon#read 4, iclass 36, count 0 2006.201.11:45:10.14#ibcon#about to read 5, iclass 36, count 0 2006.201.11:45:10.14#ibcon#read 5, iclass 36, count 0 2006.201.11:45:10.14#ibcon#about to read 6, iclass 36, count 0 2006.201.11:45:10.14#ibcon#read 6, iclass 36, count 0 2006.201.11:45:10.14#ibcon#end of sib2, iclass 36, count 0 2006.201.11:45:10.14#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:45:10.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:45:10.14#ibcon#[25=USB\r\n] 2006.201.11:45:10.14#ibcon#*before write, iclass 36, count 0 2006.201.11:45:10.14#ibcon#enter sib2, iclass 36, count 0 2006.201.11:45:10.14#ibcon#flushed, iclass 36, count 0 2006.201.11:45:10.14#ibcon#about to write, iclass 36, count 0 2006.201.11:45:10.14#ibcon#wrote, iclass 36, count 0 2006.201.11:45:10.14#ibcon#about to read 3, iclass 36, count 0 2006.201.11:45:10.17#ibcon#read 3, iclass 36, count 0 2006.201.11:45:10.17#ibcon#about to read 4, iclass 36, count 0 2006.201.11:45:10.17#ibcon#read 4, iclass 36, count 0 2006.201.11:45:10.17#ibcon#about to read 5, iclass 36, count 0 2006.201.11:45:10.17#ibcon#read 5, iclass 36, count 0 2006.201.11:45:10.17#ibcon#about to read 6, iclass 36, count 0 2006.201.11:45:10.17#ibcon#read 6, iclass 36, count 0 2006.201.11:45:10.17#ibcon#end of sib2, iclass 36, count 0 2006.201.11:45:10.17#ibcon#*after write, iclass 36, count 0 2006.201.11:45:10.17#ibcon#*before return 0, iclass 36, count 0 2006.201.11:45:10.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:10.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:10.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:45:10.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:45:10.17$vck44/valo=7,864.99 2006.201.11:45:10.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.11:45:10.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.11:45:10.17#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:10.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:10.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:10.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:10.17#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:45:10.17#ibcon#first serial, iclass 38, count 0 2006.201.11:45:10.17#ibcon#enter sib2, iclass 38, count 0 2006.201.11:45:10.17#ibcon#flushed, iclass 38, count 0 2006.201.11:45:10.17#ibcon#about to write, iclass 38, count 0 2006.201.11:45:10.17#ibcon#wrote, iclass 38, count 0 2006.201.11:45:10.17#ibcon#about to read 3, iclass 38, count 0 2006.201.11:45:10.19#ibcon#read 3, iclass 38, count 0 2006.201.11:45:10.19#ibcon#about to read 4, iclass 38, count 0 2006.201.11:45:10.19#ibcon#read 4, iclass 38, count 0 2006.201.11:45:10.19#ibcon#about to read 5, iclass 38, count 0 2006.201.11:45:10.19#ibcon#read 5, iclass 38, count 0 2006.201.11:45:10.19#ibcon#about to read 6, iclass 38, count 0 2006.201.11:45:10.19#ibcon#read 6, iclass 38, count 0 2006.201.11:45:10.19#ibcon#end of sib2, iclass 38, count 0 2006.201.11:45:10.19#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:45:10.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:45:10.19#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:45:10.19#ibcon#*before write, iclass 38, count 0 2006.201.11:45:10.19#ibcon#enter sib2, iclass 38, count 0 2006.201.11:45:10.19#ibcon#flushed, iclass 38, count 0 2006.201.11:45:10.19#ibcon#about to write, iclass 38, count 0 2006.201.11:45:10.19#ibcon#wrote, iclass 38, count 0 2006.201.11:45:10.19#ibcon#about to read 3, iclass 38, count 0 2006.201.11:45:10.24#ibcon#read 3, iclass 38, count 0 2006.201.11:45:10.24#ibcon#about to read 4, iclass 38, count 0 2006.201.11:45:10.24#ibcon#read 4, iclass 38, count 0 2006.201.11:45:10.24#ibcon#about to read 5, iclass 38, count 0 2006.201.11:45:10.24#ibcon#read 5, iclass 38, count 0 2006.201.11:45:10.24#ibcon#about to read 6, iclass 38, count 0 2006.201.11:45:10.24#ibcon#read 6, iclass 38, count 0 2006.201.11:45:10.24#ibcon#end of sib2, iclass 38, count 0 2006.201.11:45:10.24#ibcon#*after write, iclass 38, count 0 2006.201.11:45:10.24#ibcon#*before return 0, iclass 38, count 0 2006.201.11:45:10.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:10.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:10.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:45:10.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:45:10.24$vck44/va=7,5 2006.201.11:45:10.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.11:45:10.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.11:45:10.24#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:10.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:10.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:10.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:10.29#ibcon#enter wrdev, iclass 40, count 2 2006.201.11:45:10.29#ibcon#first serial, iclass 40, count 2 2006.201.11:45:10.29#ibcon#enter sib2, iclass 40, count 2 2006.201.11:45:10.29#ibcon#flushed, iclass 40, count 2 2006.201.11:45:10.29#ibcon#about to write, iclass 40, count 2 2006.201.11:45:10.29#ibcon#wrote, iclass 40, count 2 2006.201.11:45:10.29#ibcon#about to read 3, iclass 40, count 2 2006.201.11:45:10.31#ibcon#read 3, iclass 40, count 2 2006.201.11:45:10.31#ibcon#about to read 4, iclass 40, count 2 2006.201.11:45:10.31#ibcon#read 4, iclass 40, count 2 2006.201.11:45:10.31#ibcon#about to read 5, iclass 40, count 2 2006.201.11:45:10.31#ibcon#read 5, iclass 40, count 2 2006.201.11:45:10.31#ibcon#about to read 6, iclass 40, count 2 2006.201.11:45:10.31#ibcon#read 6, iclass 40, count 2 2006.201.11:45:10.31#ibcon#end of sib2, iclass 40, count 2 2006.201.11:45:10.31#ibcon#*mode == 0, iclass 40, count 2 2006.201.11:45:10.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.11:45:10.31#ibcon#[25=AT07-05\r\n] 2006.201.11:45:10.31#ibcon#*before write, iclass 40, count 2 2006.201.11:45:10.31#ibcon#enter sib2, iclass 40, count 2 2006.201.11:45:10.31#ibcon#flushed, iclass 40, count 2 2006.201.11:45:10.31#ibcon#about to write, iclass 40, count 2 2006.201.11:45:10.31#ibcon#wrote, iclass 40, count 2 2006.201.11:45:10.31#ibcon#about to read 3, iclass 40, count 2 2006.201.11:45:10.34#ibcon#read 3, iclass 40, count 2 2006.201.11:45:10.34#ibcon#about to read 4, iclass 40, count 2 2006.201.11:45:10.34#ibcon#read 4, iclass 40, count 2 2006.201.11:45:10.34#ibcon#about to read 5, iclass 40, count 2 2006.201.11:45:10.34#ibcon#read 5, iclass 40, count 2 2006.201.11:45:10.34#ibcon#about to read 6, iclass 40, count 2 2006.201.11:45:10.34#ibcon#read 6, iclass 40, count 2 2006.201.11:45:10.34#ibcon#end of sib2, iclass 40, count 2 2006.201.11:45:10.34#ibcon#*after write, iclass 40, count 2 2006.201.11:45:10.34#ibcon#*before return 0, iclass 40, count 2 2006.201.11:45:10.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:10.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:10.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.11:45:10.34#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:10.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:10.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:10.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:10.46#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:45:10.46#ibcon#first serial, iclass 40, count 0 2006.201.11:45:10.46#ibcon#enter sib2, iclass 40, count 0 2006.201.11:45:10.46#ibcon#flushed, iclass 40, count 0 2006.201.11:45:10.46#ibcon#about to write, iclass 40, count 0 2006.201.11:45:10.46#ibcon#wrote, iclass 40, count 0 2006.201.11:45:10.46#ibcon#about to read 3, iclass 40, count 0 2006.201.11:45:10.47#abcon#<5=/04 1.7 3.2 21.381001003.9\r\n> 2006.201.11:45:10.48#ibcon#read 3, iclass 40, count 0 2006.201.11:45:10.48#ibcon#about to read 4, iclass 40, count 0 2006.201.11:45:10.48#ibcon#read 4, iclass 40, count 0 2006.201.11:45:10.48#ibcon#about to read 5, iclass 40, count 0 2006.201.11:45:10.48#ibcon#read 5, iclass 40, count 0 2006.201.11:45:10.48#ibcon#about to read 6, iclass 40, count 0 2006.201.11:45:10.48#ibcon#read 6, iclass 40, count 0 2006.201.11:45:10.48#ibcon#end of sib2, iclass 40, count 0 2006.201.11:45:10.48#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:45:10.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:45:10.48#ibcon#[25=USB\r\n] 2006.201.11:45:10.48#ibcon#*before write, iclass 40, count 0 2006.201.11:45:10.48#ibcon#enter sib2, iclass 40, count 0 2006.201.11:45:10.48#ibcon#flushed, iclass 40, count 0 2006.201.11:45:10.48#ibcon#about to write, iclass 40, count 0 2006.201.11:45:10.48#ibcon#wrote, iclass 40, count 0 2006.201.11:45:10.48#ibcon#about to read 3, iclass 40, count 0 2006.201.11:45:10.49#abcon#{5=INTERFACE CLEAR} 2006.201.11:45:10.51#ibcon#read 3, iclass 40, count 0 2006.201.11:45:10.51#ibcon#about to read 4, iclass 40, count 0 2006.201.11:45:10.51#ibcon#read 4, iclass 40, count 0 2006.201.11:45:10.51#ibcon#about to read 5, iclass 40, count 0 2006.201.11:45:10.51#ibcon#read 5, iclass 40, count 0 2006.201.11:45:10.51#ibcon#about to read 6, iclass 40, count 0 2006.201.11:45:10.51#ibcon#read 6, iclass 40, count 0 2006.201.11:45:10.51#ibcon#end of sib2, iclass 40, count 0 2006.201.11:45:10.51#ibcon#*after write, iclass 40, count 0 2006.201.11:45:10.51#ibcon#*before return 0, iclass 40, count 0 2006.201.11:45:10.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:10.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:10.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:45:10.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:45:10.51$vck44/valo=8,884.99 2006.201.11:45:10.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.11:45:10.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.11:45:10.51#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:10.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:45:10.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:45:10.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:45:10.51#ibcon#enter wrdev, iclass 7, count 0 2006.201.11:45:10.51#ibcon#first serial, iclass 7, count 0 2006.201.11:45:10.51#ibcon#enter sib2, iclass 7, count 0 2006.201.11:45:10.51#ibcon#flushed, iclass 7, count 0 2006.201.11:45:10.51#ibcon#about to write, iclass 7, count 0 2006.201.11:45:10.51#ibcon#wrote, iclass 7, count 0 2006.201.11:45:10.51#ibcon#about to read 3, iclass 7, count 0 2006.201.11:45:10.53#ibcon#read 3, iclass 7, count 0 2006.201.11:45:10.53#ibcon#about to read 4, iclass 7, count 0 2006.201.11:45:10.53#ibcon#read 4, iclass 7, count 0 2006.201.11:45:10.53#ibcon#about to read 5, iclass 7, count 0 2006.201.11:45:10.53#ibcon#read 5, iclass 7, count 0 2006.201.11:45:10.53#ibcon#about to read 6, iclass 7, count 0 2006.201.11:45:10.53#ibcon#read 6, iclass 7, count 0 2006.201.11:45:10.53#ibcon#end of sib2, iclass 7, count 0 2006.201.11:45:10.53#ibcon#*mode == 0, iclass 7, count 0 2006.201.11:45:10.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.11:45:10.53#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:45:10.53#ibcon#*before write, iclass 7, count 0 2006.201.11:45:10.53#ibcon#enter sib2, iclass 7, count 0 2006.201.11:45:10.53#ibcon#flushed, iclass 7, count 0 2006.201.11:45:10.53#ibcon#about to write, iclass 7, count 0 2006.201.11:45:10.53#ibcon#wrote, iclass 7, count 0 2006.201.11:45:10.53#ibcon#about to read 3, iclass 7, count 0 2006.201.11:45:10.55#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:45:10.58#ibcon#read 3, iclass 7, count 0 2006.201.11:45:10.58#ibcon#about to read 4, iclass 7, count 0 2006.201.11:45:10.58#ibcon#read 4, iclass 7, count 0 2006.201.11:45:10.58#ibcon#about to read 5, iclass 7, count 0 2006.201.11:45:10.58#ibcon#read 5, iclass 7, count 0 2006.201.11:45:10.58#ibcon#about to read 6, iclass 7, count 0 2006.201.11:45:10.58#ibcon#read 6, iclass 7, count 0 2006.201.11:45:10.58#ibcon#end of sib2, iclass 7, count 0 2006.201.11:45:10.58#ibcon#*after write, iclass 7, count 0 2006.201.11:45:10.58#ibcon#*before return 0, iclass 7, count 0 2006.201.11:45:10.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:45:10.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:45:10.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.11:45:10.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.11:45:10.58$vck44/va=8,4 2006.201.11:45:10.58#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.11:45:10.58#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.11:45:10.58#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:10.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:45:10.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:45:10.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:45:10.63#ibcon#enter wrdev, iclass 12, count 2 2006.201.11:45:10.63#ibcon#first serial, iclass 12, count 2 2006.201.11:45:10.63#ibcon#enter sib2, iclass 12, count 2 2006.201.11:45:10.63#ibcon#flushed, iclass 12, count 2 2006.201.11:45:10.63#ibcon#about to write, iclass 12, count 2 2006.201.11:45:10.63#ibcon#wrote, iclass 12, count 2 2006.201.11:45:10.63#ibcon#about to read 3, iclass 12, count 2 2006.201.11:45:10.65#ibcon#read 3, iclass 12, count 2 2006.201.11:45:10.65#ibcon#about to read 4, iclass 12, count 2 2006.201.11:45:10.65#ibcon#read 4, iclass 12, count 2 2006.201.11:45:10.65#ibcon#about to read 5, iclass 12, count 2 2006.201.11:45:10.65#ibcon#read 5, iclass 12, count 2 2006.201.11:45:10.65#ibcon#about to read 6, iclass 12, count 2 2006.201.11:45:10.65#ibcon#read 6, iclass 12, count 2 2006.201.11:45:10.65#ibcon#end of sib2, iclass 12, count 2 2006.201.11:45:10.65#ibcon#*mode == 0, iclass 12, count 2 2006.201.11:45:10.65#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.11:45:10.65#ibcon#[25=AT08-04\r\n] 2006.201.11:45:10.65#ibcon#*before write, iclass 12, count 2 2006.201.11:45:10.65#ibcon#enter sib2, iclass 12, count 2 2006.201.11:45:10.65#ibcon#flushed, iclass 12, count 2 2006.201.11:45:10.65#ibcon#about to write, iclass 12, count 2 2006.201.11:45:10.65#ibcon#wrote, iclass 12, count 2 2006.201.11:45:10.65#ibcon#about to read 3, iclass 12, count 2 2006.201.11:45:10.68#ibcon#read 3, iclass 12, count 2 2006.201.11:45:10.68#ibcon#about to read 4, iclass 12, count 2 2006.201.11:45:10.68#ibcon#read 4, iclass 12, count 2 2006.201.11:45:10.68#ibcon#about to read 5, iclass 12, count 2 2006.201.11:45:10.68#ibcon#read 5, iclass 12, count 2 2006.201.11:45:10.68#ibcon#about to read 6, iclass 12, count 2 2006.201.11:45:10.68#ibcon#read 6, iclass 12, count 2 2006.201.11:45:10.68#ibcon#end of sib2, iclass 12, count 2 2006.201.11:45:10.68#ibcon#*after write, iclass 12, count 2 2006.201.11:45:10.68#ibcon#*before return 0, iclass 12, count 2 2006.201.11:45:10.68#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:45:10.68#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.11:45:10.68#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.11:45:10.68#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:10.68#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:45:10.80#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:45:10.80#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:45:10.80#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:45:10.80#ibcon#first serial, iclass 12, count 0 2006.201.11:45:10.80#ibcon#enter sib2, iclass 12, count 0 2006.201.11:45:10.80#ibcon#flushed, iclass 12, count 0 2006.201.11:45:10.80#ibcon#about to write, iclass 12, count 0 2006.201.11:45:10.80#ibcon#wrote, iclass 12, count 0 2006.201.11:45:10.80#ibcon#about to read 3, iclass 12, count 0 2006.201.11:45:10.82#ibcon#read 3, iclass 12, count 0 2006.201.11:45:10.82#ibcon#about to read 4, iclass 12, count 0 2006.201.11:45:10.82#ibcon#read 4, iclass 12, count 0 2006.201.11:45:10.82#ibcon#about to read 5, iclass 12, count 0 2006.201.11:45:10.82#ibcon#read 5, iclass 12, count 0 2006.201.11:45:10.82#ibcon#about to read 6, iclass 12, count 0 2006.201.11:45:10.82#ibcon#read 6, iclass 12, count 0 2006.201.11:45:10.82#ibcon#end of sib2, iclass 12, count 0 2006.201.11:45:10.82#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:45:10.82#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:45:10.82#ibcon#[25=USB\r\n] 2006.201.11:45:10.82#ibcon#*before write, iclass 12, count 0 2006.201.11:45:10.82#ibcon#enter sib2, iclass 12, count 0 2006.201.11:45:10.82#ibcon#flushed, iclass 12, count 0 2006.201.11:45:10.82#ibcon#about to write, iclass 12, count 0 2006.201.11:45:10.82#ibcon#wrote, iclass 12, count 0 2006.201.11:45:10.82#ibcon#about to read 3, iclass 12, count 0 2006.201.11:45:10.85#ibcon#read 3, iclass 12, count 0 2006.201.11:45:10.85#ibcon#about to read 4, iclass 12, count 0 2006.201.11:45:10.85#ibcon#read 4, iclass 12, count 0 2006.201.11:45:10.85#ibcon#about to read 5, iclass 12, count 0 2006.201.11:45:10.85#ibcon#read 5, iclass 12, count 0 2006.201.11:45:10.85#ibcon#about to read 6, iclass 12, count 0 2006.201.11:45:10.85#ibcon#read 6, iclass 12, count 0 2006.201.11:45:10.85#ibcon#end of sib2, iclass 12, count 0 2006.201.11:45:10.85#ibcon#*after write, iclass 12, count 0 2006.201.11:45:10.85#ibcon#*before return 0, iclass 12, count 0 2006.201.11:45:10.85#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:45:10.85#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.11:45:10.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:45:10.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:45:10.85$vck44/vblo=1,629.99 2006.201.11:45:10.85#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.11:45:10.85#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.11:45:10.85#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:10.85#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:10.85#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:10.85#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:10.85#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:45:10.85#ibcon#first serial, iclass 14, count 0 2006.201.11:45:10.85#ibcon#enter sib2, iclass 14, count 0 2006.201.11:45:10.85#ibcon#flushed, iclass 14, count 0 2006.201.11:45:10.85#ibcon#about to write, iclass 14, count 0 2006.201.11:45:10.85#ibcon#wrote, iclass 14, count 0 2006.201.11:45:10.85#ibcon#about to read 3, iclass 14, count 0 2006.201.11:45:10.87#ibcon#read 3, iclass 14, count 0 2006.201.11:45:10.87#ibcon#about to read 4, iclass 14, count 0 2006.201.11:45:10.87#ibcon#read 4, iclass 14, count 0 2006.201.11:45:10.87#ibcon#about to read 5, iclass 14, count 0 2006.201.11:45:10.87#ibcon#read 5, iclass 14, count 0 2006.201.11:45:10.87#ibcon#about to read 6, iclass 14, count 0 2006.201.11:45:10.87#ibcon#read 6, iclass 14, count 0 2006.201.11:45:10.87#ibcon#end of sib2, iclass 14, count 0 2006.201.11:45:10.87#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:45:10.87#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:45:10.87#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:45:10.87#ibcon#*before write, iclass 14, count 0 2006.201.11:45:10.87#ibcon#enter sib2, iclass 14, count 0 2006.201.11:45:10.87#ibcon#flushed, iclass 14, count 0 2006.201.11:45:10.87#ibcon#about to write, iclass 14, count 0 2006.201.11:45:10.87#ibcon#wrote, iclass 14, count 0 2006.201.11:45:10.87#ibcon#about to read 3, iclass 14, count 0 2006.201.11:45:10.92#ibcon#read 3, iclass 14, count 0 2006.201.11:45:10.92#ibcon#about to read 4, iclass 14, count 0 2006.201.11:45:10.92#ibcon#read 4, iclass 14, count 0 2006.201.11:45:10.92#ibcon#about to read 5, iclass 14, count 0 2006.201.11:45:10.92#ibcon#read 5, iclass 14, count 0 2006.201.11:45:10.92#ibcon#about to read 6, iclass 14, count 0 2006.201.11:45:10.92#ibcon#read 6, iclass 14, count 0 2006.201.11:45:10.92#ibcon#end of sib2, iclass 14, count 0 2006.201.11:45:10.92#ibcon#*after write, iclass 14, count 0 2006.201.11:45:10.92#ibcon#*before return 0, iclass 14, count 0 2006.201.11:45:10.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:10.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.11:45:10.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:45:10.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:45:10.92$vck44/vb=1,4 2006.201.11:45:10.92#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.11:45:10.92#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.11:45:10.92#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:10.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:10.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:10.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:10.92#ibcon#enter wrdev, iclass 16, count 2 2006.201.11:45:10.92#ibcon#first serial, iclass 16, count 2 2006.201.11:45:10.92#ibcon#enter sib2, iclass 16, count 2 2006.201.11:45:10.92#ibcon#flushed, iclass 16, count 2 2006.201.11:45:10.92#ibcon#about to write, iclass 16, count 2 2006.201.11:45:10.92#ibcon#wrote, iclass 16, count 2 2006.201.11:45:10.92#ibcon#about to read 3, iclass 16, count 2 2006.201.11:45:10.94#ibcon#read 3, iclass 16, count 2 2006.201.11:45:10.94#ibcon#about to read 4, iclass 16, count 2 2006.201.11:45:10.94#ibcon#read 4, iclass 16, count 2 2006.201.11:45:10.94#ibcon#about to read 5, iclass 16, count 2 2006.201.11:45:10.94#ibcon#read 5, iclass 16, count 2 2006.201.11:45:10.94#ibcon#about to read 6, iclass 16, count 2 2006.201.11:45:10.94#ibcon#read 6, iclass 16, count 2 2006.201.11:45:10.94#ibcon#end of sib2, iclass 16, count 2 2006.201.11:45:10.94#ibcon#*mode == 0, iclass 16, count 2 2006.201.11:45:10.94#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.11:45:10.94#ibcon#[27=AT01-04\r\n] 2006.201.11:45:10.94#ibcon#*before write, iclass 16, count 2 2006.201.11:45:10.94#ibcon#enter sib2, iclass 16, count 2 2006.201.11:45:10.94#ibcon#flushed, iclass 16, count 2 2006.201.11:45:10.94#ibcon#about to write, iclass 16, count 2 2006.201.11:45:10.94#ibcon#wrote, iclass 16, count 2 2006.201.11:45:10.94#ibcon#about to read 3, iclass 16, count 2 2006.201.11:45:10.97#ibcon#read 3, iclass 16, count 2 2006.201.11:45:10.97#ibcon#about to read 4, iclass 16, count 2 2006.201.11:45:10.97#ibcon#read 4, iclass 16, count 2 2006.201.11:45:10.97#ibcon#about to read 5, iclass 16, count 2 2006.201.11:45:10.97#ibcon#read 5, iclass 16, count 2 2006.201.11:45:10.97#ibcon#about to read 6, iclass 16, count 2 2006.201.11:45:10.97#ibcon#read 6, iclass 16, count 2 2006.201.11:45:10.97#ibcon#end of sib2, iclass 16, count 2 2006.201.11:45:10.97#ibcon#*after write, iclass 16, count 2 2006.201.11:45:10.97#ibcon#*before return 0, iclass 16, count 2 2006.201.11:45:10.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:10.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.11:45:10.97#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.11:45:10.97#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:10.97#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:11.09#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:11.09#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:11.09#ibcon#enter wrdev, iclass 16, count 0 2006.201.11:45:11.09#ibcon#first serial, iclass 16, count 0 2006.201.11:45:11.09#ibcon#enter sib2, iclass 16, count 0 2006.201.11:45:11.09#ibcon#flushed, iclass 16, count 0 2006.201.11:45:11.09#ibcon#about to write, iclass 16, count 0 2006.201.11:45:11.09#ibcon#wrote, iclass 16, count 0 2006.201.11:45:11.09#ibcon#about to read 3, iclass 16, count 0 2006.201.11:45:11.11#ibcon#read 3, iclass 16, count 0 2006.201.11:45:11.11#ibcon#about to read 4, iclass 16, count 0 2006.201.11:45:11.11#ibcon#read 4, iclass 16, count 0 2006.201.11:45:11.11#ibcon#about to read 5, iclass 16, count 0 2006.201.11:45:11.11#ibcon#read 5, iclass 16, count 0 2006.201.11:45:11.11#ibcon#about to read 6, iclass 16, count 0 2006.201.11:45:11.11#ibcon#read 6, iclass 16, count 0 2006.201.11:45:11.11#ibcon#end of sib2, iclass 16, count 0 2006.201.11:45:11.11#ibcon#*mode == 0, iclass 16, count 0 2006.201.11:45:11.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.11:45:11.11#ibcon#[27=USB\r\n] 2006.201.11:45:11.11#ibcon#*before write, iclass 16, count 0 2006.201.11:45:11.11#ibcon#enter sib2, iclass 16, count 0 2006.201.11:45:11.11#ibcon#flushed, iclass 16, count 0 2006.201.11:45:11.11#ibcon#about to write, iclass 16, count 0 2006.201.11:45:11.11#ibcon#wrote, iclass 16, count 0 2006.201.11:45:11.11#ibcon#about to read 3, iclass 16, count 0 2006.201.11:45:11.14#ibcon#read 3, iclass 16, count 0 2006.201.11:45:11.14#ibcon#about to read 4, iclass 16, count 0 2006.201.11:45:11.14#ibcon#read 4, iclass 16, count 0 2006.201.11:45:11.14#ibcon#about to read 5, iclass 16, count 0 2006.201.11:45:11.14#ibcon#read 5, iclass 16, count 0 2006.201.11:45:11.14#ibcon#about to read 6, iclass 16, count 0 2006.201.11:45:11.14#ibcon#read 6, iclass 16, count 0 2006.201.11:45:11.14#ibcon#end of sib2, iclass 16, count 0 2006.201.11:45:11.14#ibcon#*after write, iclass 16, count 0 2006.201.11:45:11.14#ibcon#*before return 0, iclass 16, count 0 2006.201.11:45:11.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:11.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.11:45:11.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.11:45:11.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.11:45:11.14$vck44/vblo=2,634.99 2006.201.11:45:11.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.11:45:11.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.11:45:11.14#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:11.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:11.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:11.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:11.14#ibcon#enter wrdev, iclass 18, count 0 2006.201.11:45:11.14#ibcon#first serial, iclass 18, count 0 2006.201.11:45:11.14#ibcon#enter sib2, iclass 18, count 0 2006.201.11:45:11.14#ibcon#flushed, iclass 18, count 0 2006.201.11:45:11.14#ibcon#about to write, iclass 18, count 0 2006.201.11:45:11.14#ibcon#wrote, iclass 18, count 0 2006.201.11:45:11.14#ibcon#about to read 3, iclass 18, count 0 2006.201.11:45:11.16#ibcon#read 3, iclass 18, count 0 2006.201.11:45:11.16#ibcon#about to read 4, iclass 18, count 0 2006.201.11:45:11.16#ibcon#read 4, iclass 18, count 0 2006.201.11:45:11.16#ibcon#about to read 5, iclass 18, count 0 2006.201.11:45:11.16#ibcon#read 5, iclass 18, count 0 2006.201.11:45:11.16#ibcon#about to read 6, iclass 18, count 0 2006.201.11:45:11.16#ibcon#read 6, iclass 18, count 0 2006.201.11:45:11.16#ibcon#end of sib2, iclass 18, count 0 2006.201.11:45:11.16#ibcon#*mode == 0, iclass 18, count 0 2006.201.11:45:11.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.11:45:11.16#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:45:11.16#ibcon#*before write, iclass 18, count 0 2006.201.11:45:11.16#ibcon#enter sib2, iclass 18, count 0 2006.201.11:45:11.16#ibcon#flushed, iclass 18, count 0 2006.201.11:45:11.16#ibcon#about to write, iclass 18, count 0 2006.201.11:45:11.16#ibcon#wrote, iclass 18, count 0 2006.201.11:45:11.16#ibcon#about to read 3, iclass 18, count 0 2006.201.11:45:11.20#ibcon#read 3, iclass 18, count 0 2006.201.11:45:11.20#ibcon#about to read 4, iclass 18, count 0 2006.201.11:45:11.20#ibcon#read 4, iclass 18, count 0 2006.201.11:45:11.20#ibcon#about to read 5, iclass 18, count 0 2006.201.11:45:11.20#ibcon#read 5, iclass 18, count 0 2006.201.11:45:11.20#ibcon#about to read 6, iclass 18, count 0 2006.201.11:45:11.20#ibcon#read 6, iclass 18, count 0 2006.201.11:45:11.20#ibcon#end of sib2, iclass 18, count 0 2006.201.11:45:11.20#ibcon#*after write, iclass 18, count 0 2006.201.11:45:11.20#ibcon#*before return 0, iclass 18, count 0 2006.201.11:45:11.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:11.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.11:45:11.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.11:45:11.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.11:45:11.20$vck44/vb=2,5 2006.201.11:45:11.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.11:45:11.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.11:45:11.20#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:11.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:11.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:11.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:11.26#ibcon#enter wrdev, iclass 20, count 2 2006.201.11:45:11.26#ibcon#first serial, iclass 20, count 2 2006.201.11:45:11.26#ibcon#enter sib2, iclass 20, count 2 2006.201.11:45:11.26#ibcon#flushed, iclass 20, count 2 2006.201.11:45:11.26#ibcon#about to write, iclass 20, count 2 2006.201.11:45:11.26#ibcon#wrote, iclass 20, count 2 2006.201.11:45:11.26#ibcon#about to read 3, iclass 20, count 2 2006.201.11:45:11.28#ibcon#read 3, iclass 20, count 2 2006.201.11:45:11.28#ibcon#about to read 4, iclass 20, count 2 2006.201.11:45:11.28#ibcon#read 4, iclass 20, count 2 2006.201.11:45:11.28#ibcon#about to read 5, iclass 20, count 2 2006.201.11:45:11.28#ibcon#read 5, iclass 20, count 2 2006.201.11:45:11.28#ibcon#about to read 6, iclass 20, count 2 2006.201.11:45:11.28#ibcon#read 6, iclass 20, count 2 2006.201.11:45:11.28#ibcon#end of sib2, iclass 20, count 2 2006.201.11:45:11.28#ibcon#*mode == 0, iclass 20, count 2 2006.201.11:45:11.28#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.11:45:11.28#ibcon#[27=AT02-05\r\n] 2006.201.11:45:11.28#ibcon#*before write, iclass 20, count 2 2006.201.11:45:11.28#ibcon#enter sib2, iclass 20, count 2 2006.201.11:45:11.28#ibcon#flushed, iclass 20, count 2 2006.201.11:45:11.28#ibcon#about to write, iclass 20, count 2 2006.201.11:45:11.28#ibcon#wrote, iclass 20, count 2 2006.201.11:45:11.28#ibcon#about to read 3, iclass 20, count 2 2006.201.11:45:11.31#ibcon#read 3, iclass 20, count 2 2006.201.11:45:11.31#ibcon#about to read 4, iclass 20, count 2 2006.201.11:45:11.31#ibcon#read 4, iclass 20, count 2 2006.201.11:45:11.31#ibcon#about to read 5, iclass 20, count 2 2006.201.11:45:11.31#ibcon#read 5, iclass 20, count 2 2006.201.11:45:11.31#ibcon#about to read 6, iclass 20, count 2 2006.201.11:45:11.31#ibcon#read 6, iclass 20, count 2 2006.201.11:45:11.31#ibcon#end of sib2, iclass 20, count 2 2006.201.11:45:11.31#ibcon#*after write, iclass 20, count 2 2006.201.11:45:11.31#ibcon#*before return 0, iclass 20, count 2 2006.201.11:45:11.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:11.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.11:45:11.31#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.11:45:11.31#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:11.31#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:11.43#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:11.43#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:11.43#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:45:11.43#ibcon#first serial, iclass 20, count 0 2006.201.11:45:11.43#ibcon#enter sib2, iclass 20, count 0 2006.201.11:45:11.43#ibcon#flushed, iclass 20, count 0 2006.201.11:45:11.43#ibcon#about to write, iclass 20, count 0 2006.201.11:45:11.43#ibcon#wrote, iclass 20, count 0 2006.201.11:45:11.43#ibcon#about to read 3, iclass 20, count 0 2006.201.11:45:11.45#ibcon#read 3, iclass 20, count 0 2006.201.11:45:11.45#ibcon#about to read 4, iclass 20, count 0 2006.201.11:45:11.45#ibcon#read 4, iclass 20, count 0 2006.201.11:45:11.45#ibcon#about to read 5, iclass 20, count 0 2006.201.11:45:11.45#ibcon#read 5, iclass 20, count 0 2006.201.11:45:11.45#ibcon#about to read 6, iclass 20, count 0 2006.201.11:45:11.45#ibcon#read 6, iclass 20, count 0 2006.201.11:45:11.45#ibcon#end of sib2, iclass 20, count 0 2006.201.11:45:11.45#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:45:11.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:45:11.45#ibcon#[27=USB\r\n] 2006.201.11:45:11.45#ibcon#*before write, iclass 20, count 0 2006.201.11:45:11.45#ibcon#enter sib2, iclass 20, count 0 2006.201.11:45:11.45#ibcon#flushed, iclass 20, count 0 2006.201.11:45:11.45#ibcon#about to write, iclass 20, count 0 2006.201.11:45:11.45#ibcon#wrote, iclass 20, count 0 2006.201.11:45:11.45#ibcon#about to read 3, iclass 20, count 0 2006.201.11:45:11.48#ibcon#read 3, iclass 20, count 0 2006.201.11:45:11.48#ibcon#about to read 4, iclass 20, count 0 2006.201.11:45:11.48#ibcon#read 4, iclass 20, count 0 2006.201.11:45:11.48#ibcon#about to read 5, iclass 20, count 0 2006.201.11:45:11.48#ibcon#read 5, iclass 20, count 0 2006.201.11:45:11.48#ibcon#about to read 6, iclass 20, count 0 2006.201.11:45:11.48#ibcon#read 6, iclass 20, count 0 2006.201.11:45:11.48#ibcon#end of sib2, iclass 20, count 0 2006.201.11:45:11.48#ibcon#*after write, iclass 20, count 0 2006.201.11:45:11.48#ibcon#*before return 0, iclass 20, count 0 2006.201.11:45:11.48#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:11.48#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.11:45:11.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:45:11.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:45:11.48$vck44/vblo=3,649.99 2006.201.11:45:11.48#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.11:45:11.48#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.11:45:11.48#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:11.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:11.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:11.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:11.48#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:45:11.48#ibcon#first serial, iclass 22, count 0 2006.201.11:45:11.48#ibcon#enter sib2, iclass 22, count 0 2006.201.11:45:11.48#ibcon#flushed, iclass 22, count 0 2006.201.11:45:11.48#ibcon#about to write, iclass 22, count 0 2006.201.11:45:11.48#ibcon#wrote, iclass 22, count 0 2006.201.11:45:11.48#ibcon#about to read 3, iclass 22, count 0 2006.201.11:45:11.50#ibcon#read 3, iclass 22, count 0 2006.201.11:45:11.50#ibcon#about to read 4, iclass 22, count 0 2006.201.11:45:11.50#ibcon#read 4, iclass 22, count 0 2006.201.11:45:11.50#ibcon#about to read 5, iclass 22, count 0 2006.201.11:45:11.50#ibcon#read 5, iclass 22, count 0 2006.201.11:45:11.50#ibcon#about to read 6, iclass 22, count 0 2006.201.11:45:11.50#ibcon#read 6, iclass 22, count 0 2006.201.11:45:11.50#ibcon#end of sib2, iclass 22, count 0 2006.201.11:45:11.50#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:45:11.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:45:11.50#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:45:11.50#ibcon#*before write, iclass 22, count 0 2006.201.11:45:11.50#ibcon#enter sib2, iclass 22, count 0 2006.201.11:45:11.50#ibcon#flushed, iclass 22, count 0 2006.201.11:45:11.50#ibcon#about to write, iclass 22, count 0 2006.201.11:45:11.50#ibcon#wrote, iclass 22, count 0 2006.201.11:45:11.50#ibcon#about to read 3, iclass 22, count 0 2006.201.11:45:11.55#ibcon#read 3, iclass 22, count 0 2006.201.11:45:11.55#ibcon#about to read 4, iclass 22, count 0 2006.201.11:45:11.55#ibcon#read 4, iclass 22, count 0 2006.201.11:45:11.55#ibcon#about to read 5, iclass 22, count 0 2006.201.11:45:11.55#ibcon#read 5, iclass 22, count 0 2006.201.11:45:11.55#ibcon#about to read 6, iclass 22, count 0 2006.201.11:45:11.55#ibcon#read 6, iclass 22, count 0 2006.201.11:45:11.55#ibcon#end of sib2, iclass 22, count 0 2006.201.11:45:11.55#ibcon#*after write, iclass 22, count 0 2006.201.11:45:11.55#ibcon#*before return 0, iclass 22, count 0 2006.201.11:45:11.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:11.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.11:45:11.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:45:11.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:45:11.55$vck44/vb=3,4 2006.201.11:45:11.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.11:45:11.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.11:45:11.55#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:11.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:11.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:11.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:11.60#ibcon#enter wrdev, iclass 24, count 2 2006.201.11:45:11.60#ibcon#first serial, iclass 24, count 2 2006.201.11:45:11.60#ibcon#enter sib2, iclass 24, count 2 2006.201.11:45:11.60#ibcon#flushed, iclass 24, count 2 2006.201.11:45:11.60#ibcon#about to write, iclass 24, count 2 2006.201.11:45:11.60#ibcon#wrote, iclass 24, count 2 2006.201.11:45:11.60#ibcon#about to read 3, iclass 24, count 2 2006.201.11:45:11.62#ibcon#read 3, iclass 24, count 2 2006.201.11:45:11.62#ibcon#about to read 4, iclass 24, count 2 2006.201.11:45:11.62#ibcon#read 4, iclass 24, count 2 2006.201.11:45:11.62#ibcon#about to read 5, iclass 24, count 2 2006.201.11:45:11.62#ibcon#read 5, iclass 24, count 2 2006.201.11:45:11.62#ibcon#about to read 6, iclass 24, count 2 2006.201.11:45:11.62#ibcon#read 6, iclass 24, count 2 2006.201.11:45:11.62#ibcon#end of sib2, iclass 24, count 2 2006.201.11:45:11.62#ibcon#*mode == 0, iclass 24, count 2 2006.201.11:45:11.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.11:45:11.62#ibcon#[27=AT03-04\r\n] 2006.201.11:45:11.62#ibcon#*before write, iclass 24, count 2 2006.201.11:45:11.62#ibcon#enter sib2, iclass 24, count 2 2006.201.11:45:11.62#ibcon#flushed, iclass 24, count 2 2006.201.11:45:11.62#ibcon#about to write, iclass 24, count 2 2006.201.11:45:11.62#ibcon#wrote, iclass 24, count 2 2006.201.11:45:11.62#ibcon#about to read 3, iclass 24, count 2 2006.201.11:45:11.65#ibcon#read 3, iclass 24, count 2 2006.201.11:45:11.65#ibcon#about to read 4, iclass 24, count 2 2006.201.11:45:11.65#ibcon#read 4, iclass 24, count 2 2006.201.11:45:11.65#ibcon#about to read 5, iclass 24, count 2 2006.201.11:45:11.65#ibcon#read 5, iclass 24, count 2 2006.201.11:45:11.65#ibcon#about to read 6, iclass 24, count 2 2006.201.11:45:11.65#ibcon#read 6, iclass 24, count 2 2006.201.11:45:11.65#ibcon#end of sib2, iclass 24, count 2 2006.201.11:45:11.65#ibcon#*after write, iclass 24, count 2 2006.201.11:45:11.65#ibcon#*before return 0, iclass 24, count 2 2006.201.11:45:11.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:11.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.11:45:11.65#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.11:45:11.65#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:11.65#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:11.77#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:11.77#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:11.77#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:45:11.77#ibcon#first serial, iclass 24, count 0 2006.201.11:45:11.77#ibcon#enter sib2, iclass 24, count 0 2006.201.11:45:11.77#ibcon#flushed, iclass 24, count 0 2006.201.11:45:11.77#ibcon#about to write, iclass 24, count 0 2006.201.11:45:11.77#ibcon#wrote, iclass 24, count 0 2006.201.11:45:11.77#ibcon#about to read 3, iclass 24, count 0 2006.201.11:45:11.79#ibcon#read 3, iclass 24, count 0 2006.201.11:45:11.79#ibcon#about to read 4, iclass 24, count 0 2006.201.11:45:11.79#ibcon#read 4, iclass 24, count 0 2006.201.11:45:11.79#ibcon#about to read 5, iclass 24, count 0 2006.201.11:45:11.79#ibcon#read 5, iclass 24, count 0 2006.201.11:45:11.79#ibcon#about to read 6, iclass 24, count 0 2006.201.11:45:11.79#ibcon#read 6, iclass 24, count 0 2006.201.11:45:11.79#ibcon#end of sib2, iclass 24, count 0 2006.201.11:45:11.79#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:45:11.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:45:11.79#ibcon#[27=USB\r\n] 2006.201.11:45:11.79#ibcon#*before write, iclass 24, count 0 2006.201.11:45:11.79#ibcon#enter sib2, iclass 24, count 0 2006.201.11:45:11.79#ibcon#flushed, iclass 24, count 0 2006.201.11:45:11.79#ibcon#about to write, iclass 24, count 0 2006.201.11:45:11.79#ibcon#wrote, iclass 24, count 0 2006.201.11:45:11.79#ibcon#about to read 3, iclass 24, count 0 2006.201.11:45:11.82#ibcon#read 3, iclass 24, count 0 2006.201.11:45:11.82#ibcon#about to read 4, iclass 24, count 0 2006.201.11:45:11.82#ibcon#read 4, iclass 24, count 0 2006.201.11:45:11.82#ibcon#about to read 5, iclass 24, count 0 2006.201.11:45:11.82#ibcon#read 5, iclass 24, count 0 2006.201.11:45:11.82#ibcon#about to read 6, iclass 24, count 0 2006.201.11:45:11.82#ibcon#read 6, iclass 24, count 0 2006.201.11:45:11.82#ibcon#end of sib2, iclass 24, count 0 2006.201.11:45:11.82#ibcon#*after write, iclass 24, count 0 2006.201.11:45:11.82#ibcon#*before return 0, iclass 24, count 0 2006.201.11:45:11.82#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:11.82#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.11:45:11.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:45:11.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:45:11.82$vck44/vblo=4,679.99 2006.201.11:45:11.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.11:45:11.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.11:45:11.82#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:11.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:11.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:11.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:11.82#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:45:11.82#ibcon#first serial, iclass 26, count 0 2006.201.11:45:11.82#ibcon#enter sib2, iclass 26, count 0 2006.201.11:45:11.82#ibcon#flushed, iclass 26, count 0 2006.201.11:45:11.82#ibcon#about to write, iclass 26, count 0 2006.201.11:45:11.82#ibcon#wrote, iclass 26, count 0 2006.201.11:45:11.82#ibcon#about to read 3, iclass 26, count 0 2006.201.11:45:11.84#ibcon#read 3, iclass 26, count 0 2006.201.11:45:11.84#ibcon#about to read 4, iclass 26, count 0 2006.201.11:45:11.84#ibcon#read 4, iclass 26, count 0 2006.201.11:45:11.84#ibcon#about to read 5, iclass 26, count 0 2006.201.11:45:11.84#ibcon#read 5, iclass 26, count 0 2006.201.11:45:11.84#ibcon#about to read 6, iclass 26, count 0 2006.201.11:45:11.84#ibcon#read 6, iclass 26, count 0 2006.201.11:45:11.84#ibcon#end of sib2, iclass 26, count 0 2006.201.11:45:11.84#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:45:11.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:45:11.84#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:45:11.84#ibcon#*before write, iclass 26, count 0 2006.201.11:45:11.84#ibcon#enter sib2, iclass 26, count 0 2006.201.11:45:11.84#ibcon#flushed, iclass 26, count 0 2006.201.11:45:11.84#ibcon#about to write, iclass 26, count 0 2006.201.11:45:11.84#ibcon#wrote, iclass 26, count 0 2006.201.11:45:11.84#ibcon#about to read 3, iclass 26, count 0 2006.201.11:45:11.88#ibcon#read 3, iclass 26, count 0 2006.201.11:45:11.88#ibcon#about to read 4, iclass 26, count 0 2006.201.11:45:11.88#ibcon#read 4, iclass 26, count 0 2006.201.11:45:11.88#ibcon#about to read 5, iclass 26, count 0 2006.201.11:45:11.88#ibcon#read 5, iclass 26, count 0 2006.201.11:45:11.88#ibcon#about to read 6, iclass 26, count 0 2006.201.11:45:11.88#ibcon#read 6, iclass 26, count 0 2006.201.11:45:11.88#ibcon#end of sib2, iclass 26, count 0 2006.201.11:45:11.88#ibcon#*after write, iclass 26, count 0 2006.201.11:45:11.88#ibcon#*before return 0, iclass 26, count 0 2006.201.11:45:11.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:11.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.11:45:11.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:45:11.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:45:11.88$vck44/vb=4,5 2006.201.11:45:11.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.11:45:11.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.11:45:11.88#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:11.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:11.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:11.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:11.94#ibcon#enter wrdev, iclass 28, count 2 2006.201.11:45:11.94#ibcon#first serial, iclass 28, count 2 2006.201.11:45:11.94#ibcon#enter sib2, iclass 28, count 2 2006.201.11:45:11.94#ibcon#flushed, iclass 28, count 2 2006.201.11:45:11.94#ibcon#about to write, iclass 28, count 2 2006.201.11:45:11.94#ibcon#wrote, iclass 28, count 2 2006.201.11:45:11.94#ibcon#about to read 3, iclass 28, count 2 2006.201.11:45:11.96#ibcon#read 3, iclass 28, count 2 2006.201.11:45:11.96#ibcon#about to read 4, iclass 28, count 2 2006.201.11:45:11.96#ibcon#read 4, iclass 28, count 2 2006.201.11:45:11.96#ibcon#about to read 5, iclass 28, count 2 2006.201.11:45:11.96#ibcon#read 5, iclass 28, count 2 2006.201.11:45:11.96#ibcon#about to read 6, iclass 28, count 2 2006.201.11:45:11.96#ibcon#read 6, iclass 28, count 2 2006.201.11:45:11.96#ibcon#end of sib2, iclass 28, count 2 2006.201.11:45:11.96#ibcon#*mode == 0, iclass 28, count 2 2006.201.11:45:11.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.11:45:11.96#ibcon#[27=AT04-05\r\n] 2006.201.11:45:11.96#ibcon#*before write, iclass 28, count 2 2006.201.11:45:11.96#ibcon#enter sib2, iclass 28, count 2 2006.201.11:45:11.96#ibcon#flushed, iclass 28, count 2 2006.201.11:45:11.96#ibcon#about to write, iclass 28, count 2 2006.201.11:45:11.96#ibcon#wrote, iclass 28, count 2 2006.201.11:45:11.96#ibcon#about to read 3, iclass 28, count 2 2006.201.11:45:11.99#ibcon#read 3, iclass 28, count 2 2006.201.11:45:11.99#ibcon#about to read 4, iclass 28, count 2 2006.201.11:45:11.99#ibcon#read 4, iclass 28, count 2 2006.201.11:45:11.99#ibcon#about to read 5, iclass 28, count 2 2006.201.11:45:11.99#ibcon#read 5, iclass 28, count 2 2006.201.11:45:11.99#ibcon#about to read 6, iclass 28, count 2 2006.201.11:45:11.99#ibcon#read 6, iclass 28, count 2 2006.201.11:45:11.99#ibcon#end of sib2, iclass 28, count 2 2006.201.11:45:11.99#ibcon#*after write, iclass 28, count 2 2006.201.11:45:11.99#ibcon#*before return 0, iclass 28, count 2 2006.201.11:45:11.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:11.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.11:45:11.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.11:45:11.99#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:11.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:12.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:12.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:12.11#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:45:12.11#ibcon#first serial, iclass 28, count 0 2006.201.11:45:12.11#ibcon#enter sib2, iclass 28, count 0 2006.201.11:45:12.11#ibcon#flushed, iclass 28, count 0 2006.201.11:45:12.11#ibcon#about to write, iclass 28, count 0 2006.201.11:45:12.11#ibcon#wrote, iclass 28, count 0 2006.201.11:45:12.11#ibcon#about to read 3, iclass 28, count 0 2006.201.11:45:12.13#ibcon#read 3, iclass 28, count 0 2006.201.11:45:12.13#ibcon#about to read 4, iclass 28, count 0 2006.201.11:45:12.13#ibcon#read 4, iclass 28, count 0 2006.201.11:45:12.13#ibcon#about to read 5, iclass 28, count 0 2006.201.11:45:12.13#ibcon#read 5, iclass 28, count 0 2006.201.11:45:12.13#ibcon#about to read 6, iclass 28, count 0 2006.201.11:45:12.13#ibcon#read 6, iclass 28, count 0 2006.201.11:45:12.13#ibcon#end of sib2, iclass 28, count 0 2006.201.11:45:12.13#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:45:12.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:45:12.13#ibcon#[27=USB\r\n] 2006.201.11:45:12.13#ibcon#*before write, iclass 28, count 0 2006.201.11:45:12.13#ibcon#enter sib2, iclass 28, count 0 2006.201.11:45:12.13#ibcon#flushed, iclass 28, count 0 2006.201.11:45:12.13#ibcon#about to write, iclass 28, count 0 2006.201.11:45:12.13#ibcon#wrote, iclass 28, count 0 2006.201.11:45:12.13#ibcon#about to read 3, iclass 28, count 0 2006.201.11:45:12.16#ibcon#read 3, iclass 28, count 0 2006.201.11:45:12.16#ibcon#about to read 4, iclass 28, count 0 2006.201.11:45:12.16#ibcon#read 4, iclass 28, count 0 2006.201.11:45:12.16#ibcon#about to read 5, iclass 28, count 0 2006.201.11:45:12.16#ibcon#read 5, iclass 28, count 0 2006.201.11:45:12.16#ibcon#about to read 6, iclass 28, count 0 2006.201.11:45:12.16#ibcon#read 6, iclass 28, count 0 2006.201.11:45:12.16#ibcon#end of sib2, iclass 28, count 0 2006.201.11:45:12.16#ibcon#*after write, iclass 28, count 0 2006.201.11:45:12.16#ibcon#*before return 0, iclass 28, count 0 2006.201.11:45:12.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:12.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.11:45:12.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:45:12.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:45:12.16$vck44/vblo=5,709.99 2006.201.11:45:12.16#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.11:45:12.16#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.11:45:12.16#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:12.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:12.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:12.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:12.16#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:45:12.16#ibcon#first serial, iclass 30, count 0 2006.201.11:45:12.16#ibcon#enter sib2, iclass 30, count 0 2006.201.11:45:12.16#ibcon#flushed, iclass 30, count 0 2006.201.11:45:12.16#ibcon#about to write, iclass 30, count 0 2006.201.11:45:12.16#ibcon#wrote, iclass 30, count 0 2006.201.11:45:12.16#ibcon#about to read 3, iclass 30, count 0 2006.201.11:45:12.18#ibcon#read 3, iclass 30, count 0 2006.201.11:45:12.18#ibcon#about to read 4, iclass 30, count 0 2006.201.11:45:12.18#ibcon#read 4, iclass 30, count 0 2006.201.11:45:12.18#ibcon#about to read 5, iclass 30, count 0 2006.201.11:45:12.18#ibcon#read 5, iclass 30, count 0 2006.201.11:45:12.18#ibcon#about to read 6, iclass 30, count 0 2006.201.11:45:12.18#ibcon#read 6, iclass 30, count 0 2006.201.11:45:12.18#ibcon#end of sib2, iclass 30, count 0 2006.201.11:45:12.18#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:45:12.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:45:12.18#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:45:12.18#ibcon#*before write, iclass 30, count 0 2006.201.11:45:12.18#ibcon#enter sib2, iclass 30, count 0 2006.201.11:45:12.18#ibcon#flushed, iclass 30, count 0 2006.201.11:45:12.18#ibcon#about to write, iclass 30, count 0 2006.201.11:45:12.18#ibcon#wrote, iclass 30, count 0 2006.201.11:45:12.18#ibcon#about to read 3, iclass 30, count 0 2006.201.11:45:12.23#ibcon#read 3, iclass 30, count 0 2006.201.11:45:12.23#ibcon#about to read 4, iclass 30, count 0 2006.201.11:45:12.23#ibcon#read 4, iclass 30, count 0 2006.201.11:45:12.23#ibcon#about to read 5, iclass 30, count 0 2006.201.11:45:12.23#ibcon#read 5, iclass 30, count 0 2006.201.11:45:12.23#ibcon#about to read 6, iclass 30, count 0 2006.201.11:45:12.23#ibcon#read 6, iclass 30, count 0 2006.201.11:45:12.23#ibcon#end of sib2, iclass 30, count 0 2006.201.11:45:12.23#ibcon#*after write, iclass 30, count 0 2006.201.11:45:12.23#ibcon#*before return 0, iclass 30, count 0 2006.201.11:45:12.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:12.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.11:45:12.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:45:12.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:45:12.23$vck44/vb=5,4 2006.201.11:45:12.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.11:45:12.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.11:45:12.23#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:12.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:12.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:12.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:12.28#ibcon#enter wrdev, iclass 32, count 2 2006.201.11:45:12.28#ibcon#first serial, iclass 32, count 2 2006.201.11:45:12.28#ibcon#enter sib2, iclass 32, count 2 2006.201.11:45:12.28#ibcon#flushed, iclass 32, count 2 2006.201.11:45:12.28#ibcon#about to write, iclass 32, count 2 2006.201.11:45:12.28#ibcon#wrote, iclass 32, count 2 2006.201.11:45:12.28#ibcon#about to read 3, iclass 32, count 2 2006.201.11:45:12.30#ibcon#read 3, iclass 32, count 2 2006.201.11:45:12.30#ibcon#about to read 4, iclass 32, count 2 2006.201.11:45:12.30#ibcon#read 4, iclass 32, count 2 2006.201.11:45:12.30#ibcon#about to read 5, iclass 32, count 2 2006.201.11:45:12.30#ibcon#read 5, iclass 32, count 2 2006.201.11:45:12.30#ibcon#about to read 6, iclass 32, count 2 2006.201.11:45:12.30#ibcon#read 6, iclass 32, count 2 2006.201.11:45:12.30#ibcon#end of sib2, iclass 32, count 2 2006.201.11:45:12.30#ibcon#*mode == 0, iclass 32, count 2 2006.201.11:45:12.30#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.11:45:12.30#ibcon#[27=AT05-04\r\n] 2006.201.11:45:12.30#ibcon#*before write, iclass 32, count 2 2006.201.11:45:12.30#ibcon#enter sib2, iclass 32, count 2 2006.201.11:45:12.30#ibcon#flushed, iclass 32, count 2 2006.201.11:45:12.30#ibcon#about to write, iclass 32, count 2 2006.201.11:45:12.30#ibcon#wrote, iclass 32, count 2 2006.201.11:45:12.30#ibcon#about to read 3, iclass 32, count 2 2006.201.11:45:12.33#ibcon#read 3, iclass 32, count 2 2006.201.11:45:12.33#ibcon#about to read 4, iclass 32, count 2 2006.201.11:45:12.33#ibcon#read 4, iclass 32, count 2 2006.201.11:45:12.33#ibcon#about to read 5, iclass 32, count 2 2006.201.11:45:12.33#ibcon#read 5, iclass 32, count 2 2006.201.11:45:12.33#ibcon#about to read 6, iclass 32, count 2 2006.201.11:45:12.33#ibcon#read 6, iclass 32, count 2 2006.201.11:45:12.33#ibcon#end of sib2, iclass 32, count 2 2006.201.11:45:12.33#ibcon#*after write, iclass 32, count 2 2006.201.11:45:12.33#ibcon#*before return 0, iclass 32, count 2 2006.201.11:45:12.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:12.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.11:45:12.33#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.11:45:12.33#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:12.33#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:12.45#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:12.45#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:12.45#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:45:12.45#ibcon#first serial, iclass 32, count 0 2006.201.11:45:12.45#ibcon#enter sib2, iclass 32, count 0 2006.201.11:45:12.45#ibcon#flushed, iclass 32, count 0 2006.201.11:45:12.45#ibcon#about to write, iclass 32, count 0 2006.201.11:45:12.45#ibcon#wrote, iclass 32, count 0 2006.201.11:45:12.45#ibcon#about to read 3, iclass 32, count 0 2006.201.11:45:12.47#ibcon#read 3, iclass 32, count 0 2006.201.11:45:12.47#ibcon#about to read 4, iclass 32, count 0 2006.201.11:45:12.47#ibcon#read 4, iclass 32, count 0 2006.201.11:45:12.47#ibcon#about to read 5, iclass 32, count 0 2006.201.11:45:12.47#ibcon#read 5, iclass 32, count 0 2006.201.11:45:12.47#ibcon#about to read 6, iclass 32, count 0 2006.201.11:45:12.47#ibcon#read 6, iclass 32, count 0 2006.201.11:45:12.47#ibcon#end of sib2, iclass 32, count 0 2006.201.11:45:12.47#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:45:12.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:45:12.47#ibcon#[27=USB\r\n] 2006.201.11:45:12.47#ibcon#*before write, iclass 32, count 0 2006.201.11:45:12.47#ibcon#enter sib2, iclass 32, count 0 2006.201.11:45:12.47#ibcon#flushed, iclass 32, count 0 2006.201.11:45:12.47#ibcon#about to write, iclass 32, count 0 2006.201.11:45:12.47#ibcon#wrote, iclass 32, count 0 2006.201.11:45:12.47#ibcon#about to read 3, iclass 32, count 0 2006.201.11:45:12.50#ibcon#read 3, iclass 32, count 0 2006.201.11:45:12.50#ibcon#about to read 4, iclass 32, count 0 2006.201.11:45:12.50#ibcon#read 4, iclass 32, count 0 2006.201.11:45:12.50#ibcon#about to read 5, iclass 32, count 0 2006.201.11:45:12.50#ibcon#read 5, iclass 32, count 0 2006.201.11:45:12.50#ibcon#about to read 6, iclass 32, count 0 2006.201.11:45:12.50#ibcon#read 6, iclass 32, count 0 2006.201.11:45:12.50#ibcon#end of sib2, iclass 32, count 0 2006.201.11:45:12.50#ibcon#*after write, iclass 32, count 0 2006.201.11:45:12.50#ibcon#*before return 0, iclass 32, count 0 2006.201.11:45:12.50#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:12.50#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.11:45:12.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:45:12.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:45:12.50$vck44/vblo=6,719.99 2006.201.11:45:12.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.11:45:12.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.11:45:12.50#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:12.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:12.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:12.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:12.50#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:45:12.50#ibcon#first serial, iclass 34, count 0 2006.201.11:45:12.50#ibcon#enter sib2, iclass 34, count 0 2006.201.11:45:12.50#ibcon#flushed, iclass 34, count 0 2006.201.11:45:12.50#ibcon#about to write, iclass 34, count 0 2006.201.11:45:12.50#ibcon#wrote, iclass 34, count 0 2006.201.11:45:12.50#ibcon#about to read 3, iclass 34, count 0 2006.201.11:45:12.52#ibcon#read 3, iclass 34, count 0 2006.201.11:45:12.52#ibcon#about to read 4, iclass 34, count 0 2006.201.11:45:12.52#ibcon#read 4, iclass 34, count 0 2006.201.11:45:12.52#ibcon#about to read 5, iclass 34, count 0 2006.201.11:45:12.52#ibcon#read 5, iclass 34, count 0 2006.201.11:45:12.52#ibcon#about to read 6, iclass 34, count 0 2006.201.11:45:12.52#ibcon#read 6, iclass 34, count 0 2006.201.11:45:12.52#ibcon#end of sib2, iclass 34, count 0 2006.201.11:45:12.52#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:45:12.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:45:12.52#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:45:12.52#ibcon#*before write, iclass 34, count 0 2006.201.11:45:12.52#ibcon#enter sib2, iclass 34, count 0 2006.201.11:45:12.52#ibcon#flushed, iclass 34, count 0 2006.201.11:45:12.52#ibcon#about to write, iclass 34, count 0 2006.201.11:45:12.52#ibcon#wrote, iclass 34, count 0 2006.201.11:45:12.52#ibcon#about to read 3, iclass 34, count 0 2006.201.11:45:12.57#ibcon#read 3, iclass 34, count 0 2006.201.11:45:12.57#ibcon#about to read 4, iclass 34, count 0 2006.201.11:45:12.57#ibcon#read 4, iclass 34, count 0 2006.201.11:45:12.57#ibcon#about to read 5, iclass 34, count 0 2006.201.11:45:12.57#ibcon#read 5, iclass 34, count 0 2006.201.11:45:12.57#ibcon#about to read 6, iclass 34, count 0 2006.201.11:45:12.57#ibcon#read 6, iclass 34, count 0 2006.201.11:45:12.57#ibcon#end of sib2, iclass 34, count 0 2006.201.11:45:12.57#ibcon#*after write, iclass 34, count 0 2006.201.11:45:12.57#ibcon#*before return 0, iclass 34, count 0 2006.201.11:45:12.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:12.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.11:45:12.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:45:12.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:45:12.57$vck44/vb=6,4 2006.201.11:45:12.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.11:45:12.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.11:45:12.57#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:12.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:12.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:12.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:12.62#ibcon#enter wrdev, iclass 36, count 2 2006.201.11:45:12.62#ibcon#first serial, iclass 36, count 2 2006.201.11:45:12.62#ibcon#enter sib2, iclass 36, count 2 2006.201.11:45:12.62#ibcon#flushed, iclass 36, count 2 2006.201.11:45:12.62#ibcon#about to write, iclass 36, count 2 2006.201.11:45:12.62#ibcon#wrote, iclass 36, count 2 2006.201.11:45:12.62#ibcon#about to read 3, iclass 36, count 2 2006.201.11:45:12.64#ibcon#read 3, iclass 36, count 2 2006.201.11:45:12.64#ibcon#about to read 4, iclass 36, count 2 2006.201.11:45:12.64#ibcon#read 4, iclass 36, count 2 2006.201.11:45:12.64#ibcon#about to read 5, iclass 36, count 2 2006.201.11:45:12.64#ibcon#read 5, iclass 36, count 2 2006.201.11:45:12.64#ibcon#about to read 6, iclass 36, count 2 2006.201.11:45:12.64#ibcon#read 6, iclass 36, count 2 2006.201.11:45:12.64#ibcon#end of sib2, iclass 36, count 2 2006.201.11:45:12.64#ibcon#*mode == 0, iclass 36, count 2 2006.201.11:45:12.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.11:45:12.64#ibcon#[27=AT06-04\r\n] 2006.201.11:45:12.64#ibcon#*before write, iclass 36, count 2 2006.201.11:45:12.64#ibcon#enter sib2, iclass 36, count 2 2006.201.11:45:12.64#ibcon#flushed, iclass 36, count 2 2006.201.11:45:12.64#ibcon#about to write, iclass 36, count 2 2006.201.11:45:12.64#ibcon#wrote, iclass 36, count 2 2006.201.11:45:12.64#ibcon#about to read 3, iclass 36, count 2 2006.201.11:45:12.67#ibcon#read 3, iclass 36, count 2 2006.201.11:45:12.67#ibcon#about to read 4, iclass 36, count 2 2006.201.11:45:12.67#ibcon#read 4, iclass 36, count 2 2006.201.11:45:12.67#ibcon#about to read 5, iclass 36, count 2 2006.201.11:45:12.67#ibcon#read 5, iclass 36, count 2 2006.201.11:45:12.67#ibcon#about to read 6, iclass 36, count 2 2006.201.11:45:12.67#ibcon#read 6, iclass 36, count 2 2006.201.11:45:12.67#ibcon#end of sib2, iclass 36, count 2 2006.201.11:45:12.67#ibcon#*after write, iclass 36, count 2 2006.201.11:45:12.67#ibcon#*before return 0, iclass 36, count 2 2006.201.11:45:12.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:12.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.11:45:12.67#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.11:45:12.67#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:12.67#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:12.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:12.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:12.79#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:45:12.79#ibcon#first serial, iclass 36, count 0 2006.201.11:45:12.79#ibcon#enter sib2, iclass 36, count 0 2006.201.11:45:12.79#ibcon#flushed, iclass 36, count 0 2006.201.11:45:12.79#ibcon#about to write, iclass 36, count 0 2006.201.11:45:12.79#ibcon#wrote, iclass 36, count 0 2006.201.11:45:12.79#ibcon#about to read 3, iclass 36, count 0 2006.201.11:45:12.81#ibcon#read 3, iclass 36, count 0 2006.201.11:45:12.81#ibcon#about to read 4, iclass 36, count 0 2006.201.11:45:12.81#ibcon#read 4, iclass 36, count 0 2006.201.11:45:12.81#ibcon#about to read 5, iclass 36, count 0 2006.201.11:45:12.81#ibcon#read 5, iclass 36, count 0 2006.201.11:45:12.81#ibcon#about to read 6, iclass 36, count 0 2006.201.11:45:12.81#ibcon#read 6, iclass 36, count 0 2006.201.11:45:12.81#ibcon#end of sib2, iclass 36, count 0 2006.201.11:45:12.81#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:45:12.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:45:12.81#ibcon#[27=USB\r\n] 2006.201.11:45:12.81#ibcon#*before write, iclass 36, count 0 2006.201.11:45:12.81#ibcon#enter sib2, iclass 36, count 0 2006.201.11:45:12.81#ibcon#flushed, iclass 36, count 0 2006.201.11:45:12.81#ibcon#about to write, iclass 36, count 0 2006.201.11:45:12.81#ibcon#wrote, iclass 36, count 0 2006.201.11:45:12.81#ibcon#about to read 3, iclass 36, count 0 2006.201.11:45:12.84#ibcon#read 3, iclass 36, count 0 2006.201.11:45:12.84#ibcon#about to read 4, iclass 36, count 0 2006.201.11:45:12.84#ibcon#read 4, iclass 36, count 0 2006.201.11:45:12.84#ibcon#about to read 5, iclass 36, count 0 2006.201.11:45:12.84#ibcon#read 5, iclass 36, count 0 2006.201.11:45:12.84#ibcon#about to read 6, iclass 36, count 0 2006.201.11:45:12.84#ibcon#read 6, iclass 36, count 0 2006.201.11:45:12.84#ibcon#end of sib2, iclass 36, count 0 2006.201.11:45:12.84#ibcon#*after write, iclass 36, count 0 2006.201.11:45:12.84#ibcon#*before return 0, iclass 36, count 0 2006.201.11:45:12.84#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:12.84#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.11:45:12.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:45:12.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:45:12.84$vck44/vblo=7,734.99 2006.201.11:45:12.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.11:45:12.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.11:45:12.84#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:12.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:12.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:12.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:12.84#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:45:12.84#ibcon#first serial, iclass 38, count 0 2006.201.11:45:12.84#ibcon#enter sib2, iclass 38, count 0 2006.201.11:45:12.84#ibcon#flushed, iclass 38, count 0 2006.201.11:45:12.84#ibcon#about to write, iclass 38, count 0 2006.201.11:45:12.84#ibcon#wrote, iclass 38, count 0 2006.201.11:45:12.84#ibcon#about to read 3, iclass 38, count 0 2006.201.11:45:12.86#ibcon#read 3, iclass 38, count 0 2006.201.11:45:12.86#ibcon#about to read 4, iclass 38, count 0 2006.201.11:45:12.86#ibcon#read 4, iclass 38, count 0 2006.201.11:45:12.86#ibcon#about to read 5, iclass 38, count 0 2006.201.11:45:12.86#ibcon#read 5, iclass 38, count 0 2006.201.11:45:12.86#ibcon#about to read 6, iclass 38, count 0 2006.201.11:45:12.86#ibcon#read 6, iclass 38, count 0 2006.201.11:45:12.86#ibcon#end of sib2, iclass 38, count 0 2006.201.11:45:12.86#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:45:12.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:45:12.86#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:45:12.86#ibcon#*before write, iclass 38, count 0 2006.201.11:45:12.86#ibcon#enter sib2, iclass 38, count 0 2006.201.11:45:12.86#ibcon#flushed, iclass 38, count 0 2006.201.11:45:12.86#ibcon#about to write, iclass 38, count 0 2006.201.11:45:12.86#ibcon#wrote, iclass 38, count 0 2006.201.11:45:12.86#ibcon#about to read 3, iclass 38, count 0 2006.201.11:45:12.91#ibcon#read 3, iclass 38, count 0 2006.201.11:45:12.91#ibcon#about to read 4, iclass 38, count 0 2006.201.11:45:12.91#ibcon#read 4, iclass 38, count 0 2006.201.11:45:12.91#ibcon#about to read 5, iclass 38, count 0 2006.201.11:45:12.91#ibcon#read 5, iclass 38, count 0 2006.201.11:45:12.91#ibcon#about to read 6, iclass 38, count 0 2006.201.11:45:12.91#ibcon#read 6, iclass 38, count 0 2006.201.11:45:12.91#ibcon#end of sib2, iclass 38, count 0 2006.201.11:45:12.91#ibcon#*after write, iclass 38, count 0 2006.201.11:45:12.91#ibcon#*before return 0, iclass 38, count 0 2006.201.11:45:12.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:12.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.11:45:12.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:45:12.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:45:12.91$vck44/vb=7,4 2006.201.11:45:12.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.11:45:12.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.11:45:12.91#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:12.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:12.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:12.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:12.96#ibcon#enter wrdev, iclass 40, count 2 2006.201.11:45:12.96#ibcon#first serial, iclass 40, count 2 2006.201.11:45:12.96#ibcon#enter sib2, iclass 40, count 2 2006.201.11:45:12.96#ibcon#flushed, iclass 40, count 2 2006.201.11:45:12.96#ibcon#about to write, iclass 40, count 2 2006.201.11:45:12.96#ibcon#wrote, iclass 40, count 2 2006.201.11:45:12.96#ibcon#about to read 3, iclass 40, count 2 2006.201.11:45:12.98#ibcon#read 3, iclass 40, count 2 2006.201.11:45:12.98#ibcon#about to read 4, iclass 40, count 2 2006.201.11:45:12.98#ibcon#read 4, iclass 40, count 2 2006.201.11:45:12.98#ibcon#about to read 5, iclass 40, count 2 2006.201.11:45:12.98#ibcon#read 5, iclass 40, count 2 2006.201.11:45:12.98#ibcon#about to read 6, iclass 40, count 2 2006.201.11:45:12.98#ibcon#read 6, iclass 40, count 2 2006.201.11:45:12.98#ibcon#end of sib2, iclass 40, count 2 2006.201.11:45:12.98#ibcon#*mode == 0, iclass 40, count 2 2006.201.11:45:12.98#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.11:45:12.98#ibcon#[27=AT07-04\r\n] 2006.201.11:45:12.98#ibcon#*before write, iclass 40, count 2 2006.201.11:45:12.98#ibcon#enter sib2, iclass 40, count 2 2006.201.11:45:12.98#ibcon#flushed, iclass 40, count 2 2006.201.11:45:12.98#ibcon#about to write, iclass 40, count 2 2006.201.11:45:12.98#ibcon#wrote, iclass 40, count 2 2006.201.11:45:12.98#ibcon#about to read 3, iclass 40, count 2 2006.201.11:45:13.01#ibcon#read 3, iclass 40, count 2 2006.201.11:45:13.01#ibcon#about to read 4, iclass 40, count 2 2006.201.11:45:13.01#ibcon#read 4, iclass 40, count 2 2006.201.11:45:13.01#ibcon#about to read 5, iclass 40, count 2 2006.201.11:45:13.01#ibcon#read 5, iclass 40, count 2 2006.201.11:45:13.01#ibcon#about to read 6, iclass 40, count 2 2006.201.11:45:13.01#ibcon#read 6, iclass 40, count 2 2006.201.11:45:13.01#ibcon#end of sib2, iclass 40, count 2 2006.201.11:45:13.01#ibcon#*after write, iclass 40, count 2 2006.201.11:45:13.01#ibcon#*before return 0, iclass 40, count 2 2006.201.11:45:13.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:13.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.11:45:13.01#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.11:45:13.01#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:13.01#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:13.13#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:13.13#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:13.13#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:45:13.13#ibcon#first serial, iclass 40, count 0 2006.201.11:45:13.13#ibcon#enter sib2, iclass 40, count 0 2006.201.11:45:13.13#ibcon#flushed, iclass 40, count 0 2006.201.11:45:13.13#ibcon#about to write, iclass 40, count 0 2006.201.11:45:13.13#ibcon#wrote, iclass 40, count 0 2006.201.11:45:13.13#ibcon#about to read 3, iclass 40, count 0 2006.201.11:45:13.15#ibcon#read 3, iclass 40, count 0 2006.201.11:45:13.15#ibcon#about to read 4, iclass 40, count 0 2006.201.11:45:13.15#ibcon#read 4, iclass 40, count 0 2006.201.11:45:13.15#ibcon#about to read 5, iclass 40, count 0 2006.201.11:45:13.15#ibcon#read 5, iclass 40, count 0 2006.201.11:45:13.15#ibcon#about to read 6, iclass 40, count 0 2006.201.11:45:13.15#ibcon#read 6, iclass 40, count 0 2006.201.11:45:13.15#ibcon#end of sib2, iclass 40, count 0 2006.201.11:45:13.15#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:45:13.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:45:13.15#ibcon#[27=USB\r\n] 2006.201.11:45:13.15#ibcon#*before write, iclass 40, count 0 2006.201.11:45:13.15#ibcon#enter sib2, iclass 40, count 0 2006.201.11:45:13.15#ibcon#flushed, iclass 40, count 0 2006.201.11:45:13.15#ibcon#about to write, iclass 40, count 0 2006.201.11:45:13.15#ibcon#wrote, iclass 40, count 0 2006.201.11:45:13.15#ibcon#about to read 3, iclass 40, count 0 2006.201.11:45:13.18#ibcon#read 3, iclass 40, count 0 2006.201.11:45:13.18#ibcon#about to read 4, iclass 40, count 0 2006.201.11:45:13.18#ibcon#read 4, iclass 40, count 0 2006.201.11:45:13.18#ibcon#about to read 5, iclass 40, count 0 2006.201.11:45:13.18#ibcon#read 5, iclass 40, count 0 2006.201.11:45:13.18#ibcon#about to read 6, iclass 40, count 0 2006.201.11:45:13.18#ibcon#read 6, iclass 40, count 0 2006.201.11:45:13.18#ibcon#end of sib2, iclass 40, count 0 2006.201.11:45:13.18#ibcon#*after write, iclass 40, count 0 2006.201.11:45:13.18#ibcon#*before return 0, iclass 40, count 0 2006.201.11:45:13.18#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:13.18#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.11:45:13.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:45:13.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:45:13.18$vck44/vblo=8,744.99 2006.201.11:45:13.18#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.11:45:13.18#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.11:45:13.18#ibcon#ireg 17 cls_cnt 0 2006.201.11:45:13.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:45:13.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:45:13.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:45:13.18#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:45:13.18#ibcon#first serial, iclass 4, count 0 2006.201.11:45:13.18#ibcon#enter sib2, iclass 4, count 0 2006.201.11:45:13.18#ibcon#flushed, iclass 4, count 0 2006.201.11:45:13.18#ibcon#about to write, iclass 4, count 0 2006.201.11:45:13.18#ibcon#wrote, iclass 4, count 0 2006.201.11:45:13.18#ibcon#about to read 3, iclass 4, count 0 2006.201.11:45:13.20#ibcon#read 3, iclass 4, count 0 2006.201.11:45:13.20#ibcon#about to read 4, iclass 4, count 0 2006.201.11:45:13.20#ibcon#read 4, iclass 4, count 0 2006.201.11:45:13.20#ibcon#about to read 5, iclass 4, count 0 2006.201.11:45:13.20#ibcon#read 5, iclass 4, count 0 2006.201.11:45:13.20#ibcon#about to read 6, iclass 4, count 0 2006.201.11:45:13.20#ibcon#read 6, iclass 4, count 0 2006.201.11:45:13.20#ibcon#end of sib2, iclass 4, count 0 2006.201.11:45:13.20#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:45:13.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:45:13.20#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:45:13.20#ibcon#*before write, iclass 4, count 0 2006.201.11:45:13.20#ibcon#enter sib2, iclass 4, count 0 2006.201.11:45:13.20#ibcon#flushed, iclass 4, count 0 2006.201.11:45:13.20#ibcon#about to write, iclass 4, count 0 2006.201.11:45:13.20#ibcon#wrote, iclass 4, count 0 2006.201.11:45:13.20#ibcon#about to read 3, iclass 4, count 0 2006.201.11:45:13.25#ibcon#read 3, iclass 4, count 0 2006.201.11:45:13.25#ibcon#about to read 4, iclass 4, count 0 2006.201.11:45:13.25#ibcon#read 4, iclass 4, count 0 2006.201.11:45:13.25#ibcon#about to read 5, iclass 4, count 0 2006.201.11:45:13.25#ibcon#read 5, iclass 4, count 0 2006.201.11:45:13.25#ibcon#about to read 6, iclass 4, count 0 2006.201.11:45:13.25#ibcon#read 6, iclass 4, count 0 2006.201.11:45:13.25#ibcon#end of sib2, iclass 4, count 0 2006.201.11:45:13.25#ibcon#*after write, iclass 4, count 0 2006.201.11:45:13.25#ibcon#*before return 0, iclass 4, count 0 2006.201.11:45:13.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:45:13.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:45:13.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:45:13.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:45:13.25$vck44/vb=8,4 2006.201.11:45:13.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.11:45:13.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.11:45:13.25#ibcon#ireg 11 cls_cnt 2 2006.201.11:45:13.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:45:13.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:45:13.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:45:13.30#ibcon#enter wrdev, iclass 6, count 2 2006.201.11:45:13.30#ibcon#first serial, iclass 6, count 2 2006.201.11:45:13.30#ibcon#enter sib2, iclass 6, count 2 2006.201.11:45:13.30#ibcon#flushed, iclass 6, count 2 2006.201.11:45:13.30#ibcon#about to write, iclass 6, count 2 2006.201.11:45:13.30#ibcon#wrote, iclass 6, count 2 2006.201.11:45:13.30#ibcon#about to read 3, iclass 6, count 2 2006.201.11:45:13.32#ibcon#read 3, iclass 6, count 2 2006.201.11:45:13.32#ibcon#about to read 4, iclass 6, count 2 2006.201.11:45:13.32#ibcon#read 4, iclass 6, count 2 2006.201.11:45:13.32#ibcon#about to read 5, iclass 6, count 2 2006.201.11:45:13.32#ibcon#read 5, iclass 6, count 2 2006.201.11:45:13.32#ibcon#about to read 6, iclass 6, count 2 2006.201.11:45:13.32#ibcon#read 6, iclass 6, count 2 2006.201.11:45:13.32#ibcon#end of sib2, iclass 6, count 2 2006.201.11:45:13.32#ibcon#*mode == 0, iclass 6, count 2 2006.201.11:45:13.32#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.11:45:13.32#ibcon#[27=AT08-04\r\n] 2006.201.11:45:13.32#ibcon#*before write, iclass 6, count 2 2006.201.11:45:13.32#ibcon#enter sib2, iclass 6, count 2 2006.201.11:45:13.32#ibcon#flushed, iclass 6, count 2 2006.201.11:45:13.32#ibcon#about to write, iclass 6, count 2 2006.201.11:45:13.32#ibcon#wrote, iclass 6, count 2 2006.201.11:45:13.32#ibcon#about to read 3, iclass 6, count 2 2006.201.11:45:13.35#ibcon#read 3, iclass 6, count 2 2006.201.11:45:13.35#ibcon#about to read 4, iclass 6, count 2 2006.201.11:45:13.35#ibcon#read 4, iclass 6, count 2 2006.201.11:45:13.35#ibcon#about to read 5, iclass 6, count 2 2006.201.11:45:13.35#ibcon#read 5, iclass 6, count 2 2006.201.11:45:13.35#ibcon#about to read 6, iclass 6, count 2 2006.201.11:45:13.35#ibcon#read 6, iclass 6, count 2 2006.201.11:45:13.35#ibcon#end of sib2, iclass 6, count 2 2006.201.11:45:13.35#ibcon#*after write, iclass 6, count 2 2006.201.11:45:13.35#ibcon#*before return 0, iclass 6, count 2 2006.201.11:45:13.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:45:13.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.11:45:13.35#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.11:45:13.35#ibcon#ireg 7 cls_cnt 0 2006.201.11:45:13.35#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:45:13.47#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:45:13.47#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:45:13.47#ibcon#enter wrdev, iclass 6, count 0 2006.201.11:45:13.47#ibcon#first serial, iclass 6, count 0 2006.201.11:45:13.47#ibcon#enter sib2, iclass 6, count 0 2006.201.11:45:13.47#ibcon#flushed, iclass 6, count 0 2006.201.11:45:13.47#ibcon#about to write, iclass 6, count 0 2006.201.11:45:13.47#ibcon#wrote, iclass 6, count 0 2006.201.11:45:13.47#ibcon#about to read 3, iclass 6, count 0 2006.201.11:45:13.49#ibcon#read 3, iclass 6, count 0 2006.201.11:45:13.49#ibcon#about to read 4, iclass 6, count 0 2006.201.11:45:13.49#ibcon#read 4, iclass 6, count 0 2006.201.11:45:13.49#ibcon#about to read 5, iclass 6, count 0 2006.201.11:45:13.49#ibcon#read 5, iclass 6, count 0 2006.201.11:45:13.49#ibcon#about to read 6, iclass 6, count 0 2006.201.11:45:13.49#ibcon#read 6, iclass 6, count 0 2006.201.11:45:13.49#ibcon#end of sib2, iclass 6, count 0 2006.201.11:45:13.49#ibcon#*mode == 0, iclass 6, count 0 2006.201.11:45:13.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.11:45:13.49#ibcon#[27=USB\r\n] 2006.201.11:45:13.49#ibcon#*before write, iclass 6, count 0 2006.201.11:45:13.49#ibcon#enter sib2, iclass 6, count 0 2006.201.11:45:13.49#ibcon#flushed, iclass 6, count 0 2006.201.11:45:13.49#ibcon#about to write, iclass 6, count 0 2006.201.11:45:13.49#ibcon#wrote, iclass 6, count 0 2006.201.11:45:13.49#ibcon#about to read 3, iclass 6, count 0 2006.201.11:45:13.52#ibcon#read 3, iclass 6, count 0 2006.201.11:45:13.52#ibcon#about to read 4, iclass 6, count 0 2006.201.11:45:13.52#ibcon#read 4, iclass 6, count 0 2006.201.11:45:13.52#ibcon#about to read 5, iclass 6, count 0 2006.201.11:45:13.52#ibcon#read 5, iclass 6, count 0 2006.201.11:45:13.52#ibcon#about to read 6, iclass 6, count 0 2006.201.11:45:13.52#ibcon#read 6, iclass 6, count 0 2006.201.11:45:13.52#ibcon#end of sib2, iclass 6, count 0 2006.201.11:45:13.52#ibcon#*after write, iclass 6, count 0 2006.201.11:45:13.52#ibcon#*before return 0, iclass 6, count 0 2006.201.11:45:13.52#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:45:13.52#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.11:45:13.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.11:45:13.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.11:45:13.52$vck44/vabw=wide 2006.201.11:45:13.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.11:45:13.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.11:45:13.52#ibcon#ireg 8 cls_cnt 0 2006.201.11:45:13.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:45:13.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:45:13.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:45:13.52#ibcon#enter wrdev, iclass 10, count 0 2006.201.11:45:13.52#ibcon#first serial, iclass 10, count 0 2006.201.11:45:13.52#ibcon#enter sib2, iclass 10, count 0 2006.201.11:45:13.52#ibcon#flushed, iclass 10, count 0 2006.201.11:45:13.52#ibcon#about to write, iclass 10, count 0 2006.201.11:45:13.52#ibcon#wrote, iclass 10, count 0 2006.201.11:45:13.52#ibcon#about to read 3, iclass 10, count 0 2006.201.11:45:13.54#ibcon#read 3, iclass 10, count 0 2006.201.11:45:13.54#ibcon#about to read 4, iclass 10, count 0 2006.201.11:45:13.54#ibcon#read 4, iclass 10, count 0 2006.201.11:45:13.54#ibcon#about to read 5, iclass 10, count 0 2006.201.11:45:13.54#ibcon#read 5, iclass 10, count 0 2006.201.11:45:13.54#ibcon#about to read 6, iclass 10, count 0 2006.201.11:45:13.54#ibcon#read 6, iclass 10, count 0 2006.201.11:45:13.54#ibcon#end of sib2, iclass 10, count 0 2006.201.11:45:13.54#ibcon#*mode == 0, iclass 10, count 0 2006.201.11:45:13.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.11:45:13.54#ibcon#[25=BW32\r\n] 2006.201.11:45:13.54#ibcon#*before write, iclass 10, count 0 2006.201.11:45:13.54#ibcon#enter sib2, iclass 10, count 0 2006.201.11:45:13.54#ibcon#flushed, iclass 10, count 0 2006.201.11:45:13.54#ibcon#about to write, iclass 10, count 0 2006.201.11:45:13.54#ibcon#wrote, iclass 10, count 0 2006.201.11:45:13.54#ibcon#about to read 3, iclass 10, count 0 2006.201.11:45:13.58#ibcon#read 3, iclass 10, count 0 2006.201.11:45:13.58#ibcon#about to read 4, iclass 10, count 0 2006.201.11:45:13.58#ibcon#read 4, iclass 10, count 0 2006.201.11:45:13.58#ibcon#about to read 5, iclass 10, count 0 2006.201.11:45:13.58#ibcon#read 5, iclass 10, count 0 2006.201.11:45:13.58#ibcon#about to read 6, iclass 10, count 0 2006.201.11:45:13.58#ibcon#read 6, iclass 10, count 0 2006.201.11:45:13.58#ibcon#end of sib2, iclass 10, count 0 2006.201.11:45:13.58#ibcon#*after write, iclass 10, count 0 2006.201.11:45:13.58#ibcon#*before return 0, iclass 10, count 0 2006.201.11:45:13.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:45:13.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.11:45:13.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.11:45:13.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.11:45:13.58$vck44/vbbw=wide 2006.201.11:45:13.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.11:45:13.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.11:45:13.58#ibcon#ireg 8 cls_cnt 0 2006.201.11:45:13.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:45:13.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:45:13.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:45:13.64#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:45:13.64#ibcon#first serial, iclass 12, count 0 2006.201.11:45:13.64#ibcon#enter sib2, iclass 12, count 0 2006.201.11:45:13.64#ibcon#flushed, iclass 12, count 0 2006.201.11:45:13.64#ibcon#about to write, iclass 12, count 0 2006.201.11:45:13.64#ibcon#wrote, iclass 12, count 0 2006.201.11:45:13.64#ibcon#about to read 3, iclass 12, count 0 2006.201.11:45:13.66#ibcon#read 3, iclass 12, count 0 2006.201.11:45:13.66#ibcon#about to read 4, iclass 12, count 0 2006.201.11:45:13.66#ibcon#read 4, iclass 12, count 0 2006.201.11:45:13.66#ibcon#about to read 5, iclass 12, count 0 2006.201.11:45:13.66#ibcon#read 5, iclass 12, count 0 2006.201.11:45:13.66#ibcon#about to read 6, iclass 12, count 0 2006.201.11:45:13.66#ibcon#read 6, iclass 12, count 0 2006.201.11:45:13.66#ibcon#end of sib2, iclass 12, count 0 2006.201.11:45:13.66#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:45:13.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:45:13.66#ibcon#[27=BW32\r\n] 2006.201.11:45:13.66#ibcon#*before write, iclass 12, count 0 2006.201.11:45:13.66#ibcon#enter sib2, iclass 12, count 0 2006.201.11:45:13.66#ibcon#flushed, iclass 12, count 0 2006.201.11:45:13.66#ibcon#about to write, iclass 12, count 0 2006.201.11:45:13.66#ibcon#wrote, iclass 12, count 0 2006.201.11:45:13.66#ibcon#about to read 3, iclass 12, count 0 2006.201.11:45:13.69#ibcon#read 3, iclass 12, count 0 2006.201.11:45:13.69#ibcon#about to read 4, iclass 12, count 0 2006.201.11:45:13.69#ibcon#read 4, iclass 12, count 0 2006.201.11:45:13.69#ibcon#about to read 5, iclass 12, count 0 2006.201.11:45:13.69#ibcon#read 5, iclass 12, count 0 2006.201.11:45:13.69#ibcon#about to read 6, iclass 12, count 0 2006.201.11:45:13.69#ibcon#read 6, iclass 12, count 0 2006.201.11:45:13.69#ibcon#end of sib2, iclass 12, count 0 2006.201.11:45:13.69#ibcon#*after write, iclass 12, count 0 2006.201.11:45:13.69#ibcon#*before return 0, iclass 12, count 0 2006.201.11:45:13.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:45:13.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:45:13.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:45:13.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:45:13.69$setupk4/ifdk4 2006.201.11:45:13.69$ifdk4/lo= 2006.201.11:45:13.69$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:45:13.69$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:45:13.69$ifdk4/patch= 2006.201.11:45:13.69$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:45:13.69$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:45:13.69$setupk4/!*+20s 2006.201.11:45:20.65#abcon#<5=/04 1.7 3.2 21.371001003.9\r\n> 2006.201.11:45:20.67#abcon#{5=INTERFACE CLEAR} 2006.201.11:45:20.73#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:45:28.17$setupk4/"tpicd 2006.201.11:45:28.17$setupk4/echo=off 2006.201.11:45:28.17$setupk4/xlog=off 2006.201.11:45:28.17:!2006.201.11:46:51 2006.201.11:45:34.14#trakl#Source acquired 2006.201.11:45:35.14#flagr#flagr/antenna,acquired 2006.201.11:46:51.00:preob 2006.201.11:46:51.14/onsource/TRACKING 2006.201.11:46:51.14:!2006.201.11:47:01 2006.201.11:47:01.00:"tape 2006.201.11:47:01.00:"st=record 2006.201.11:47:01.00:data_valid=on 2006.201.11:47:01.00:midob 2006.201.11:47:02.14/onsource/TRACKING 2006.201.11:47:02.14/wx/21.37,1003.9,100 2006.201.11:47:02.23/cable/+6.4706E-03 2006.201.11:47:03.32/va/01,08,usb,yes,34,36 2006.201.11:47:03.32/va/02,07,usb,yes,36,37 2006.201.11:47:03.32/va/03,08,usb,yes,33,34 2006.201.11:47:03.32/va/04,07,usb,yes,37,39 2006.201.11:47:03.32/va/05,04,usb,yes,33,34 2006.201.11:47:03.32/va/06,05,usb,yes,33,33 2006.201.11:47:03.32/va/07,05,usb,yes,32,34 2006.201.11:47:03.32/va/08,04,usb,yes,32,38 2006.201.11:47:03.55/valo/01,524.99,yes,locked 2006.201.11:47:03.55/valo/02,534.99,yes,locked 2006.201.11:47:03.55/valo/03,564.99,yes,locked 2006.201.11:47:03.55/valo/04,624.99,yes,locked 2006.201.11:47:03.55/valo/05,734.99,yes,locked 2006.201.11:47:03.55/valo/06,814.99,yes,locked 2006.201.11:47:03.55/valo/07,864.99,yes,locked 2006.201.11:47:03.55/valo/08,884.99,yes,locked 2006.201.11:47:04.64/vb/01,04,usb,yes,31,31 2006.201.11:47:04.64/vb/02,05,usb,yes,30,31 2006.201.11:47:04.64/vb/03,04,usb,yes,31,34 2006.201.11:47:04.64/vb/04,05,usb,yes,31,30 2006.201.11:47:04.64/vb/05,04,usb,yes,28,30 2006.201.11:47:04.64/vb/06,04,usb,yes,33,29 2006.201.11:47:04.64/vb/07,04,usb,yes,32,32 2006.201.11:47:04.64/vb/08,04,usb,yes,30,33 2006.201.11:47:04.88/vblo/01,629.99,yes,locked 2006.201.11:47:04.88/vblo/02,634.99,yes,locked 2006.201.11:47:04.88/vblo/03,649.99,yes,locked 2006.201.11:47:04.88/vblo/04,679.99,yes,locked 2006.201.11:47:04.88/vblo/05,709.99,yes,locked 2006.201.11:47:04.88/vblo/06,719.99,yes,locked 2006.201.11:47:04.88/vblo/07,734.99,yes,locked 2006.201.11:47:04.88/vblo/08,744.99,yes,locked 2006.201.11:47:05.03/vabw/8 2006.201.11:47:05.18/vbbw/8 2006.201.11:47:05.27/xfe/off,on,15.2 2006.201.11:47:05.64/ifatt/23,28,28,28 2006.201.11:47:06.05/fmout-gps/S +4.53E-07 2006.201.11:47:06.12:!2006.201.11:47:41 2006.201.11:47:41.00:data_valid=off 2006.201.11:47:41.00:"et 2006.201.11:47:41.00:!+3s 2006.201.11:47:44.02:"tape 2006.201.11:47:44.02:postob 2006.201.11:47:44.11/cable/+6.4698E-03 2006.201.11:47:44.11/wx/21.37,1003.9,100 2006.201.11:47:44.19/fmout-gps/S +4.53E-07 2006.201.11:47:44.19:scan_name=201-1148,jd0607,150 2006.201.11:47:44.20:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.201.11:47:46.14#flagr#flagr/antenna,new-source 2006.201.11:47:46.14:checkk5 2006.201.11:47:46.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:47:46.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:47:47.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:47:47.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:47:48.01/chk_obsdata//k5ts1/T2011147??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:47:48.38/chk_obsdata//k5ts2/T2011147??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:47:48.74/chk_obsdata//k5ts3/T2011147??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:47:49.10/chk_obsdata//k5ts4/T2011147??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.11:47:49.80/k5log//k5ts1_log_newline 2006.201.11:47:50.48/k5log//k5ts2_log_newline 2006.201.11:47:51.16/k5log//k5ts3_log_newline 2006.201.11:47:51.86/k5log//k5ts4_log_newline 2006.201.11:47:51.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:47:51.88:setupk4=1 2006.201.11:47:51.88$setupk4/echo=on 2006.201.11:47:51.88$setupk4/pcalon 2006.201.11:47:51.88$pcalon/"no phase cal control is implemented here 2006.201.11:47:51.88$setupk4/"tpicd=stop 2006.201.11:47:51.88$setupk4/"rec=synch_on 2006.201.11:47:51.88$setupk4/"rec_mode=128 2006.201.11:47:51.88$setupk4/!* 2006.201.11:47:51.88$setupk4/recpk4 2006.201.11:47:51.88$recpk4/recpatch= 2006.201.11:47:51.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:47:51.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:47:51.89$setupk4/vck44 2006.201.11:47:51.89$vck44/valo=1,524.99 2006.201.11:47:51.89#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.11:47:51.89#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.11:47:51.89#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:51.89#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:51.89#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:51.89#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:51.89#ibcon#enter wrdev, iclass 2, count 0 2006.201.11:47:51.89#ibcon#first serial, iclass 2, count 0 2006.201.11:47:51.89#ibcon#enter sib2, iclass 2, count 0 2006.201.11:47:51.89#ibcon#flushed, iclass 2, count 0 2006.201.11:47:51.89#ibcon#about to write, iclass 2, count 0 2006.201.11:47:51.89#ibcon#wrote, iclass 2, count 0 2006.201.11:47:51.89#ibcon#about to read 3, iclass 2, count 0 2006.201.11:47:51.92#ibcon#read 3, iclass 2, count 0 2006.201.11:47:51.92#ibcon#about to read 4, iclass 2, count 0 2006.201.11:47:51.92#ibcon#read 4, iclass 2, count 0 2006.201.11:47:51.92#ibcon#about to read 5, iclass 2, count 0 2006.201.11:47:51.92#ibcon#read 5, iclass 2, count 0 2006.201.11:47:51.92#ibcon#about to read 6, iclass 2, count 0 2006.201.11:47:51.92#ibcon#read 6, iclass 2, count 0 2006.201.11:47:51.92#ibcon#end of sib2, iclass 2, count 0 2006.201.11:47:51.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.11:47:51.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.11:47:51.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:47:51.92#ibcon#*before write, iclass 2, count 0 2006.201.11:47:51.92#ibcon#enter sib2, iclass 2, count 0 2006.201.11:47:51.92#ibcon#flushed, iclass 2, count 0 2006.201.11:47:51.92#ibcon#about to write, iclass 2, count 0 2006.201.11:47:51.92#ibcon#wrote, iclass 2, count 0 2006.201.11:47:51.92#ibcon#about to read 3, iclass 2, count 0 2006.201.11:47:51.97#ibcon#read 3, iclass 2, count 0 2006.201.11:47:51.97#ibcon#about to read 4, iclass 2, count 0 2006.201.11:47:51.97#ibcon#read 4, iclass 2, count 0 2006.201.11:47:51.97#ibcon#about to read 5, iclass 2, count 0 2006.201.11:47:51.97#ibcon#read 5, iclass 2, count 0 2006.201.11:47:51.97#ibcon#about to read 6, iclass 2, count 0 2006.201.11:47:51.97#ibcon#read 6, iclass 2, count 0 2006.201.11:47:51.97#ibcon#end of sib2, iclass 2, count 0 2006.201.11:47:51.97#ibcon#*after write, iclass 2, count 0 2006.201.11:47:51.97#ibcon#*before return 0, iclass 2, count 0 2006.201.11:47:51.97#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:51.97#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:51.97#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.11:47:51.97#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.11:47:51.97$vck44/va=1,8 2006.201.11:47:51.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.11:47:51.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.11:47:51.97#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:51.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:51.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:51.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:51.97#ibcon#enter wrdev, iclass 5, count 2 2006.201.11:47:51.97#ibcon#first serial, iclass 5, count 2 2006.201.11:47:51.97#ibcon#enter sib2, iclass 5, count 2 2006.201.11:47:51.97#ibcon#flushed, iclass 5, count 2 2006.201.11:47:51.97#ibcon#about to write, iclass 5, count 2 2006.201.11:47:51.97#ibcon#wrote, iclass 5, count 2 2006.201.11:47:51.97#ibcon#about to read 3, iclass 5, count 2 2006.201.11:47:51.99#ibcon#read 3, iclass 5, count 2 2006.201.11:47:51.99#ibcon#about to read 4, iclass 5, count 2 2006.201.11:47:51.99#ibcon#read 4, iclass 5, count 2 2006.201.11:47:51.99#ibcon#about to read 5, iclass 5, count 2 2006.201.11:47:51.99#ibcon#read 5, iclass 5, count 2 2006.201.11:47:51.99#ibcon#about to read 6, iclass 5, count 2 2006.201.11:47:51.99#ibcon#read 6, iclass 5, count 2 2006.201.11:47:51.99#ibcon#end of sib2, iclass 5, count 2 2006.201.11:47:51.99#ibcon#*mode == 0, iclass 5, count 2 2006.201.11:47:51.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.11:47:51.99#ibcon#[25=AT01-08\r\n] 2006.201.11:47:51.99#ibcon#*before write, iclass 5, count 2 2006.201.11:47:51.99#ibcon#enter sib2, iclass 5, count 2 2006.201.11:47:51.99#ibcon#flushed, iclass 5, count 2 2006.201.11:47:51.99#ibcon#about to write, iclass 5, count 2 2006.201.11:47:51.99#ibcon#wrote, iclass 5, count 2 2006.201.11:47:51.99#ibcon#about to read 3, iclass 5, count 2 2006.201.11:47:52.02#ibcon#read 3, iclass 5, count 2 2006.201.11:47:52.02#ibcon#about to read 4, iclass 5, count 2 2006.201.11:47:52.02#ibcon#read 4, iclass 5, count 2 2006.201.11:47:52.02#ibcon#about to read 5, iclass 5, count 2 2006.201.11:47:52.02#ibcon#read 5, iclass 5, count 2 2006.201.11:47:52.02#ibcon#about to read 6, iclass 5, count 2 2006.201.11:47:52.02#ibcon#read 6, iclass 5, count 2 2006.201.11:47:52.02#ibcon#end of sib2, iclass 5, count 2 2006.201.11:47:52.02#ibcon#*after write, iclass 5, count 2 2006.201.11:47:52.02#ibcon#*before return 0, iclass 5, count 2 2006.201.11:47:52.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:52.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:52.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.11:47:52.02#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:52.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:52.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:52.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:52.14#ibcon#enter wrdev, iclass 5, count 0 2006.201.11:47:52.14#ibcon#first serial, iclass 5, count 0 2006.201.11:47:52.14#ibcon#enter sib2, iclass 5, count 0 2006.201.11:47:52.14#ibcon#flushed, iclass 5, count 0 2006.201.11:47:52.14#ibcon#about to write, iclass 5, count 0 2006.201.11:47:52.14#ibcon#wrote, iclass 5, count 0 2006.201.11:47:52.14#ibcon#about to read 3, iclass 5, count 0 2006.201.11:47:52.16#ibcon#read 3, iclass 5, count 0 2006.201.11:47:52.16#ibcon#about to read 4, iclass 5, count 0 2006.201.11:47:52.16#ibcon#read 4, iclass 5, count 0 2006.201.11:47:52.16#ibcon#about to read 5, iclass 5, count 0 2006.201.11:47:52.16#ibcon#read 5, iclass 5, count 0 2006.201.11:47:52.16#ibcon#about to read 6, iclass 5, count 0 2006.201.11:47:52.16#ibcon#read 6, iclass 5, count 0 2006.201.11:47:52.16#ibcon#end of sib2, iclass 5, count 0 2006.201.11:47:52.16#ibcon#*mode == 0, iclass 5, count 0 2006.201.11:47:52.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.11:47:52.16#ibcon#[25=USB\r\n] 2006.201.11:47:52.16#ibcon#*before write, iclass 5, count 0 2006.201.11:47:52.16#ibcon#enter sib2, iclass 5, count 0 2006.201.11:47:52.16#ibcon#flushed, iclass 5, count 0 2006.201.11:47:52.16#ibcon#about to write, iclass 5, count 0 2006.201.11:47:52.16#ibcon#wrote, iclass 5, count 0 2006.201.11:47:52.16#ibcon#about to read 3, iclass 5, count 0 2006.201.11:47:52.19#ibcon#read 3, iclass 5, count 0 2006.201.11:47:52.19#ibcon#about to read 4, iclass 5, count 0 2006.201.11:47:52.19#ibcon#read 4, iclass 5, count 0 2006.201.11:47:52.19#ibcon#about to read 5, iclass 5, count 0 2006.201.11:47:52.19#ibcon#read 5, iclass 5, count 0 2006.201.11:47:52.19#ibcon#about to read 6, iclass 5, count 0 2006.201.11:47:52.19#ibcon#read 6, iclass 5, count 0 2006.201.11:47:52.19#ibcon#end of sib2, iclass 5, count 0 2006.201.11:47:52.19#ibcon#*after write, iclass 5, count 0 2006.201.11:47:52.19#ibcon#*before return 0, iclass 5, count 0 2006.201.11:47:52.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:52.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:52.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.11:47:52.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.11:47:52.19$vck44/valo=2,534.99 2006.201.11:47:52.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.11:47:52.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.11:47:52.19#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:52.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:52.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:52.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:52.19#ibcon#enter wrdev, iclass 7, count 0 2006.201.11:47:52.19#ibcon#first serial, iclass 7, count 0 2006.201.11:47:52.19#ibcon#enter sib2, iclass 7, count 0 2006.201.11:47:52.19#ibcon#flushed, iclass 7, count 0 2006.201.11:47:52.19#ibcon#about to write, iclass 7, count 0 2006.201.11:47:52.19#ibcon#wrote, iclass 7, count 0 2006.201.11:47:52.19#ibcon#about to read 3, iclass 7, count 0 2006.201.11:47:52.21#ibcon#read 3, iclass 7, count 0 2006.201.11:47:52.21#ibcon#about to read 4, iclass 7, count 0 2006.201.11:47:52.21#ibcon#read 4, iclass 7, count 0 2006.201.11:47:52.21#ibcon#about to read 5, iclass 7, count 0 2006.201.11:47:52.21#ibcon#read 5, iclass 7, count 0 2006.201.11:47:52.21#ibcon#about to read 6, iclass 7, count 0 2006.201.11:47:52.21#ibcon#read 6, iclass 7, count 0 2006.201.11:47:52.21#ibcon#end of sib2, iclass 7, count 0 2006.201.11:47:52.21#ibcon#*mode == 0, iclass 7, count 0 2006.201.11:47:52.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.11:47:52.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:47:52.21#ibcon#*before write, iclass 7, count 0 2006.201.11:47:52.21#ibcon#enter sib2, iclass 7, count 0 2006.201.11:47:52.21#ibcon#flushed, iclass 7, count 0 2006.201.11:47:52.21#ibcon#about to write, iclass 7, count 0 2006.201.11:47:52.21#ibcon#wrote, iclass 7, count 0 2006.201.11:47:52.21#ibcon#about to read 3, iclass 7, count 0 2006.201.11:47:52.26#ibcon#read 3, iclass 7, count 0 2006.201.11:47:52.26#ibcon#about to read 4, iclass 7, count 0 2006.201.11:47:52.26#ibcon#read 4, iclass 7, count 0 2006.201.11:47:52.26#ibcon#about to read 5, iclass 7, count 0 2006.201.11:47:52.26#ibcon#read 5, iclass 7, count 0 2006.201.11:47:52.26#ibcon#about to read 6, iclass 7, count 0 2006.201.11:47:52.26#ibcon#read 6, iclass 7, count 0 2006.201.11:47:52.26#ibcon#end of sib2, iclass 7, count 0 2006.201.11:47:52.26#ibcon#*after write, iclass 7, count 0 2006.201.11:47:52.26#ibcon#*before return 0, iclass 7, count 0 2006.201.11:47:52.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:52.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:52.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.11:47:52.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.11:47:52.26$vck44/va=2,7 2006.201.11:47:52.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.11:47:52.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.11:47:52.26#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:52.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:52.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:52.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:52.31#ibcon#enter wrdev, iclass 11, count 2 2006.201.11:47:52.31#ibcon#first serial, iclass 11, count 2 2006.201.11:47:52.31#ibcon#enter sib2, iclass 11, count 2 2006.201.11:47:52.31#ibcon#flushed, iclass 11, count 2 2006.201.11:47:52.31#ibcon#about to write, iclass 11, count 2 2006.201.11:47:52.31#ibcon#wrote, iclass 11, count 2 2006.201.11:47:52.31#ibcon#about to read 3, iclass 11, count 2 2006.201.11:47:52.33#ibcon#read 3, iclass 11, count 2 2006.201.11:47:52.33#ibcon#about to read 4, iclass 11, count 2 2006.201.11:47:52.33#ibcon#read 4, iclass 11, count 2 2006.201.11:47:52.33#ibcon#about to read 5, iclass 11, count 2 2006.201.11:47:52.33#ibcon#read 5, iclass 11, count 2 2006.201.11:47:52.33#ibcon#about to read 6, iclass 11, count 2 2006.201.11:47:52.33#ibcon#read 6, iclass 11, count 2 2006.201.11:47:52.33#ibcon#end of sib2, iclass 11, count 2 2006.201.11:47:52.33#ibcon#*mode == 0, iclass 11, count 2 2006.201.11:47:52.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.11:47:52.33#ibcon#[25=AT02-07\r\n] 2006.201.11:47:52.33#ibcon#*before write, iclass 11, count 2 2006.201.11:47:52.33#ibcon#enter sib2, iclass 11, count 2 2006.201.11:47:52.33#ibcon#flushed, iclass 11, count 2 2006.201.11:47:52.33#ibcon#about to write, iclass 11, count 2 2006.201.11:47:52.33#ibcon#wrote, iclass 11, count 2 2006.201.11:47:52.33#ibcon#about to read 3, iclass 11, count 2 2006.201.11:47:52.36#ibcon#read 3, iclass 11, count 2 2006.201.11:47:52.36#ibcon#about to read 4, iclass 11, count 2 2006.201.11:47:52.36#ibcon#read 4, iclass 11, count 2 2006.201.11:47:52.36#ibcon#about to read 5, iclass 11, count 2 2006.201.11:47:52.36#ibcon#read 5, iclass 11, count 2 2006.201.11:47:52.36#ibcon#about to read 6, iclass 11, count 2 2006.201.11:47:52.36#ibcon#read 6, iclass 11, count 2 2006.201.11:47:52.36#ibcon#end of sib2, iclass 11, count 2 2006.201.11:47:52.36#ibcon#*after write, iclass 11, count 2 2006.201.11:47:52.36#ibcon#*before return 0, iclass 11, count 2 2006.201.11:47:52.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:52.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:52.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.11:47:52.36#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:52.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:52.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:52.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:52.48#ibcon#enter wrdev, iclass 11, count 0 2006.201.11:47:52.48#ibcon#first serial, iclass 11, count 0 2006.201.11:47:52.48#ibcon#enter sib2, iclass 11, count 0 2006.201.11:47:52.48#ibcon#flushed, iclass 11, count 0 2006.201.11:47:52.48#ibcon#about to write, iclass 11, count 0 2006.201.11:47:52.48#ibcon#wrote, iclass 11, count 0 2006.201.11:47:52.48#ibcon#about to read 3, iclass 11, count 0 2006.201.11:47:52.50#ibcon#read 3, iclass 11, count 0 2006.201.11:47:52.50#ibcon#about to read 4, iclass 11, count 0 2006.201.11:47:52.50#ibcon#read 4, iclass 11, count 0 2006.201.11:47:52.50#ibcon#about to read 5, iclass 11, count 0 2006.201.11:47:52.50#ibcon#read 5, iclass 11, count 0 2006.201.11:47:52.50#ibcon#about to read 6, iclass 11, count 0 2006.201.11:47:52.50#ibcon#read 6, iclass 11, count 0 2006.201.11:47:52.50#ibcon#end of sib2, iclass 11, count 0 2006.201.11:47:52.50#ibcon#*mode == 0, iclass 11, count 0 2006.201.11:47:52.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.11:47:52.50#ibcon#[25=USB\r\n] 2006.201.11:47:52.50#ibcon#*before write, iclass 11, count 0 2006.201.11:47:52.50#ibcon#enter sib2, iclass 11, count 0 2006.201.11:47:52.50#ibcon#flushed, iclass 11, count 0 2006.201.11:47:52.50#ibcon#about to write, iclass 11, count 0 2006.201.11:47:52.50#ibcon#wrote, iclass 11, count 0 2006.201.11:47:52.50#ibcon#about to read 3, iclass 11, count 0 2006.201.11:47:52.53#ibcon#read 3, iclass 11, count 0 2006.201.11:47:52.53#ibcon#about to read 4, iclass 11, count 0 2006.201.11:47:52.53#ibcon#read 4, iclass 11, count 0 2006.201.11:47:52.53#ibcon#about to read 5, iclass 11, count 0 2006.201.11:47:52.53#ibcon#read 5, iclass 11, count 0 2006.201.11:47:52.53#ibcon#about to read 6, iclass 11, count 0 2006.201.11:47:52.53#ibcon#read 6, iclass 11, count 0 2006.201.11:47:52.53#ibcon#end of sib2, iclass 11, count 0 2006.201.11:47:52.53#ibcon#*after write, iclass 11, count 0 2006.201.11:47:52.53#ibcon#*before return 0, iclass 11, count 0 2006.201.11:47:52.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:52.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:52.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.11:47:52.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.11:47:52.53$vck44/valo=3,564.99 2006.201.11:47:52.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.11:47:52.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.11:47:52.53#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:52.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:52.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:52.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:52.53#ibcon#enter wrdev, iclass 13, count 0 2006.201.11:47:52.53#ibcon#first serial, iclass 13, count 0 2006.201.11:47:52.53#ibcon#enter sib2, iclass 13, count 0 2006.201.11:47:52.53#ibcon#flushed, iclass 13, count 0 2006.201.11:47:52.53#ibcon#about to write, iclass 13, count 0 2006.201.11:47:52.53#ibcon#wrote, iclass 13, count 0 2006.201.11:47:52.53#ibcon#about to read 3, iclass 13, count 0 2006.201.11:47:52.55#ibcon#read 3, iclass 13, count 0 2006.201.11:47:52.55#ibcon#about to read 4, iclass 13, count 0 2006.201.11:47:52.55#ibcon#read 4, iclass 13, count 0 2006.201.11:47:52.55#ibcon#about to read 5, iclass 13, count 0 2006.201.11:47:52.55#ibcon#read 5, iclass 13, count 0 2006.201.11:47:52.55#ibcon#about to read 6, iclass 13, count 0 2006.201.11:47:52.55#ibcon#read 6, iclass 13, count 0 2006.201.11:47:52.55#ibcon#end of sib2, iclass 13, count 0 2006.201.11:47:52.55#ibcon#*mode == 0, iclass 13, count 0 2006.201.11:47:52.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.11:47:52.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:47:52.55#ibcon#*before write, iclass 13, count 0 2006.201.11:47:52.55#ibcon#enter sib2, iclass 13, count 0 2006.201.11:47:52.55#ibcon#flushed, iclass 13, count 0 2006.201.11:47:52.55#ibcon#about to write, iclass 13, count 0 2006.201.11:47:52.55#ibcon#wrote, iclass 13, count 0 2006.201.11:47:52.55#ibcon#about to read 3, iclass 13, count 0 2006.201.11:47:52.60#ibcon#read 3, iclass 13, count 0 2006.201.11:47:52.60#ibcon#about to read 4, iclass 13, count 0 2006.201.11:47:52.60#ibcon#read 4, iclass 13, count 0 2006.201.11:47:52.60#ibcon#about to read 5, iclass 13, count 0 2006.201.11:47:52.60#ibcon#read 5, iclass 13, count 0 2006.201.11:47:52.60#ibcon#about to read 6, iclass 13, count 0 2006.201.11:47:52.60#ibcon#read 6, iclass 13, count 0 2006.201.11:47:52.60#ibcon#end of sib2, iclass 13, count 0 2006.201.11:47:52.60#ibcon#*after write, iclass 13, count 0 2006.201.11:47:52.60#ibcon#*before return 0, iclass 13, count 0 2006.201.11:47:52.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:52.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:52.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.11:47:52.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.11:47:52.60$vck44/va=3,8 2006.201.11:47:52.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.11:47:52.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.11:47:52.60#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:52.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:52.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:52.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:52.65#ibcon#enter wrdev, iclass 15, count 2 2006.201.11:47:52.65#ibcon#first serial, iclass 15, count 2 2006.201.11:47:52.65#ibcon#enter sib2, iclass 15, count 2 2006.201.11:47:52.65#ibcon#flushed, iclass 15, count 2 2006.201.11:47:52.65#ibcon#about to write, iclass 15, count 2 2006.201.11:47:52.65#ibcon#wrote, iclass 15, count 2 2006.201.11:47:52.65#ibcon#about to read 3, iclass 15, count 2 2006.201.11:47:52.67#ibcon#read 3, iclass 15, count 2 2006.201.11:47:52.67#ibcon#about to read 4, iclass 15, count 2 2006.201.11:47:52.67#ibcon#read 4, iclass 15, count 2 2006.201.11:47:52.67#ibcon#about to read 5, iclass 15, count 2 2006.201.11:47:52.67#ibcon#read 5, iclass 15, count 2 2006.201.11:47:52.67#ibcon#about to read 6, iclass 15, count 2 2006.201.11:47:52.67#ibcon#read 6, iclass 15, count 2 2006.201.11:47:52.67#ibcon#end of sib2, iclass 15, count 2 2006.201.11:47:52.67#ibcon#*mode == 0, iclass 15, count 2 2006.201.11:47:52.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.11:47:52.67#ibcon#[25=AT03-08\r\n] 2006.201.11:47:52.67#ibcon#*before write, iclass 15, count 2 2006.201.11:47:52.67#ibcon#enter sib2, iclass 15, count 2 2006.201.11:47:52.67#ibcon#flushed, iclass 15, count 2 2006.201.11:47:52.67#ibcon#about to write, iclass 15, count 2 2006.201.11:47:52.67#ibcon#wrote, iclass 15, count 2 2006.201.11:47:52.67#ibcon#about to read 3, iclass 15, count 2 2006.201.11:47:52.70#ibcon#read 3, iclass 15, count 2 2006.201.11:47:52.70#ibcon#about to read 4, iclass 15, count 2 2006.201.11:47:52.70#ibcon#read 4, iclass 15, count 2 2006.201.11:47:52.70#ibcon#about to read 5, iclass 15, count 2 2006.201.11:47:52.70#ibcon#read 5, iclass 15, count 2 2006.201.11:47:52.70#ibcon#about to read 6, iclass 15, count 2 2006.201.11:47:52.70#ibcon#read 6, iclass 15, count 2 2006.201.11:47:52.70#ibcon#end of sib2, iclass 15, count 2 2006.201.11:47:52.70#ibcon#*after write, iclass 15, count 2 2006.201.11:47:52.70#ibcon#*before return 0, iclass 15, count 2 2006.201.11:47:52.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:52.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:52.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.11:47:52.70#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:52.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:52.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:52.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:52.82#ibcon#enter wrdev, iclass 15, count 0 2006.201.11:47:52.82#ibcon#first serial, iclass 15, count 0 2006.201.11:47:52.82#ibcon#enter sib2, iclass 15, count 0 2006.201.11:47:52.82#ibcon#flushed, iclass 15, count 0 2006.201.11:47:52.82#ibcon#about to write, iclass 15, count 0 2006.201.11:47:52.82#ibcon#wrote, iclass 15, count 0 2006.201.11:47:52.82#ibcon#about to read 3, iclass 15, count 0 2006.201.11:47:52.84#ibcon#read 3, iclass 15, count 0 2006.201.11:47:52.84#ibcon#about to read 4, iclass 15, count 0 2006.201.11:47:52.84#ibcon#read 4, iclass 15, count 0 2006.201.11:47:52.84#ibcon#about to read 5, iclass 15, count 0 2006.201.11:47:52.84#ibcon#read 5, iclass 15, count 0 2006.201.11:47:52.84#ibcon#about to read 6, iclass 15, count 0 2006.201.11:47:52.84#ibcon#read 6, iclass 15, count 0 2006.201.11:47:52.84#ibcon#end of sib2, iclass 15, count 0 2006.201.11:47:52.84#ibcon#*mode == 0, iclass 15, count 0 2006.201.11:47:52.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.11:47:52.84#ibcon#[25=USB\r\n] 2006.201.11:47:52.84#ibcon#*before write, iclass 15, count 0 2006.201.11:47:52.84#ibcon#enter sib2, iclass 15, count 0 2006.201.11:47:52.84#ibcon#flushed, iclass 15, count 0 2006.201.11:47:52.84#ibcon#about to write, iclass 15, count 0 2006.201.11:47:52.84#ibcon#wrote, iclass 15, count 0 2006.201.11:47:52.84#ibcon#about to read 3, iclass 15, count 0 2006.201.11:47:52.87#ibcon#read 3, iclass 15, count 0 2006.201.11:47:52.87#ibcon#about to read 4, iclass 15, count 0 2006.201.11:47:52.87#ibcon#read 4, iclass 15, count 0 2006.201.11:47:52.87#ibcon#about to read 5, iclass 15, count 0 2006.201.11:47:52.87#ibcon#read 5, iclass 15, count 0 2006.201.11:47:52.87#ibcon#about to read 6, iclass 15, count 0 2006.201.11:47:52.87#ibcon#read 6, iclass 15, count 0 2006.201.11:47:52.87#ibcon#end of sib2, iclass 15, count 0 2006.201.11:47:52.87#ibcon#*after write, iclass 15, count 0 2006.201.11:47:52.87#ibcon#*before return 0, iclass 15, count 0 2006.201.11:47:52.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:52.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:52.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.11:47:52.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.11:47:52.87$vck44/valo=4,624.99 2006.201.11:47:52.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.11:47:52.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.11:47:52.87#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:52.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:52.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:52.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:52.87#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:47:52.87#ibcon#first serial, iclass 17, count 0 2006.201.11:47:52.87#ibcon#enter sib2, iclass 17, count 0 2006.201.11:47:52.87#ibcon#flushed, iclass 17, count 0 2006.201.11:47:52.87#ibcon#about to write, iclass 17, count 0 2006.201.11:47:52.87#ibcon#wrote, iclass 17, count 0 2006.201.11:47:52.87#ibcon#about to read 3, iclass 17, count 0 2006.201.11:47:52.89#ibcon#read 3, iclass 17, count 0 2006.201.11:47:52.89#ibcon#about to read 4, iclass 17, count 0 2006.201.11:47:52.89#ibcon#read 4, iclass 17, count 0 2006.201.11:47:52.89#ibcon#about to read 5, iclass 17, count 0 2006.201.11:47:52.89#ibcon#read 5, iclass 17, count 0 2006.201.11:47:52.89#ibcon#about to read 6, iclass 17, count 0 2006.201.11:47:52.89#ibcon#read 6, iclass 17, count 0 2006.201.11:47:52.89#ibcon#end of sib2, iclass 17, count 0 2006.201.11:47:52.89#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:47:52.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:47:52.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:47:52.89#ibcon#*before write, iclass 17, count 0 2006.201.11:47:52.89#ibcon#enter sib2, iclass 17, count 0 2006.201.11:47:52.89#ibcon#flushed, iclass 17, count 0 2006.201.11:47:52.89#ibcon#about to write, iclass 17, count 0 2006.201.11:47:52.89#ibcon#wrote, iclass 17, count 0 2006.201.11:47:52.89#ibcon#about to read 3, iclass 17, count 0 2006.201.11:47:52.94#ibcon#read 3, iclass 17, count 0 2006.201.11:47:52.94#ibcon#about to read 4, iclass 17, count 0 2006.201.11:47:52.94#ibcon#read 4, iclass 17, count 0 2006.201.11:47:52.94#ibcon#about to read 5, iclass 17, count 0 2006.201.11:47:52.94#ibcon#read 5, iclass 17, count 0 2006.201.11:47:52.94#ibcon#about to read 6, iclass 17, count 0 2006.201.11:47:52.94#ibcon#read 6, iclass 17, count 0 2006.201.11:47:52.94#ibcon#end of sib2, iclass 17, count 0 2006.201.11:47:52.94#ibcon#*after write, iclass 17, count 0 2006.201.11:47:52.94#ibcon#*before return 0, iclass 17, count 0 2006.201.11:47:52.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:52.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:52.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:47:52.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:47:52.94$vck44/va=4,7 2006.201.11:47:52.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.11:47:52.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.11:47:52.94#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:52.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:52.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:52.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:52.99#ibcon#enter wrdev, iclass 19, count 2 2006.201.11:47:52.99#ibcon#first serial, iclass 19, count 2 2006.201.11:47:52.99#ibcon#enter sib2, iclass 19, count 2 2006.201.11:47:52.99#ibcon#flushed, iclass 19, count 2 2006.201.11:47:52.99#ibcon#about to write, iclass 19, count 2 2006.201.11:47:52.99#ibcon#wrote, iclass 19, count 2 2006.201.11:47:52.99#ibcon#about to read 3, iclass 19, count 2 2006.201.11:47:53.01#ibcon#read 3, iclass 19, count 2 2006.201.11:47:53.01#ibcon#about to read 4, iclass 19, count 2 2006.201.11:47:53.01#ibcon#read 4, iclass 19, count 2 2006.201.11:47:53.01#ibcon#about to read 5, iclass 19, count 2 2006.201.11:47:53.01#ibcon#read 5, iclass 19, count 2 2006.201.11:47:53.01#ibcon#about to read 6, iclass 19, count 2 2006.201.11:47:53.01#ibcon#read 6, iclass 19, count 2 2006.201.11:47:53.01#ibcon#end of sib2, iclass 19, count 2 2006.201.11:47:53.01#ibcon#*mode == 0, iclass 19, count 2 2006.201.11:47:53.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.11:47:53.01#ibcon#[25=AT04-07\r\n] 2006.201.11:47:53.01#ibcon#*before write, iclass 19, count 2 2006.201.11:47:53.01#ibcon#enter sib2, iclass 19, count 2 2006.201.11:47:53.01#ibcon#flushed, iclass 19, count 2 2006.201.11:47:53.01#ibcon#about to write, iclass 19, count 2 2006.201.11:47:53.01#ibcon#wrote, iclass 19, count 2 2006.201.11:47:53.01#ibcon#about to read 3, iclass 19, count 2 2006.201.11:47:53.04#ibcon#read 3, iclass 19, count 2 2006.201.11:47:53.04#ibcon#about to read 4, iclass 19, count 2 2006.201.11:47:53.04#ibcon#read 4, iclass 19, count 2 2006.201.11:47:53.04#ibcon#about to read 5, iclass 19, count 2 2006.201.11:47:53.04#ibcon#read 5, iclass 19, count 2 2006.201.11:47:53.04#ibcon#about to read 6, iclass 19, count 2 2006.201.11:47:53.04#ibcon#read 6, iclass 19, count 2 2006.201.11:47:53.04#ibcon#end of sib2, iclass 19, count 2 2006.201.11:47:53.04#ibcon#*after write, iclass 19, count 2 2006.201.11:47:53.04#ibcon#*before return 0, iclass 19, count 2 2006.201.11:47:53.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:53.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:53.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.11:47:53.04#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:53.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:53.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:53.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:53.16#ibcon#enter wrdev, iclass 19, count 0 2006.201.11:47:53.16#ibcon#first serial, iclass 19, count 0 2006.201.11:47:53.16#ibcon#enter sib2, iclass 19, count 0 2006.201.11:47:53.16#ibcon#flushed, iclass 19, count 0 2006.201.11:47:53.16#ibcon#about to write, iclass 19, count 0 2006.201.11:47:53.16#ibcon#wrote, iclass 19, count 0 2006.201.11:47:53.16#ibcon#about to read 3, iclass 19, count 0 2006.201.11:47:53.18#ibcon#read 3, iclass 19, count 0 2006.201.11:47:53.18#ibcon#about to read 4, iclass 19, count 0 2006.201.11:47:53.18#ibcon#read 4, iclass 19, count 0 2006.201.11:47:53.18#ibcon#about to read 5, iclass 19, count 0 2006.201.11:47:53.18#ibcon#read 5, iclass 19, count 0 2006.201.11:47:53.18#ibcon#about to read 6, iclass 19, count 0 2006.201.11:47:53.18#ibcon#read 6, iclass 19, count 0 2006.201.11:47:53.18#ibcon#end of sib2, iclass 19, count 0 2006.201.11:47:53.18#ibcon#*mode == 0, iclass 19, count 0 2006.201.11:47:53.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.11:47:53.18#ibcon#[25=USB\r\n] 2006.201.11:47:53.18#ibcon#*before write, iclass 19, count 0 2006.201.11:47:53.18#ibcon#enter sib2, iclass 19, count 0 2006.201.11:47:53.18#ibcon#flushed, iclass 19, count 0 2006.201.11:47:53.18#ibcon#about to write, iclass 19, count 0 2006.201.11:47:53.18#ibcon#wrote, iclass 19, count 0 2006.201.11:47:53.18#ibcon#about to read 3, iclass 19, count 0 2006.201.11:47:53.19#abcon#<5=/04 1.7 3.2 21.371001004.0\r\n> 2006.201.11:47:53.21#abcon#{5=INTERFACE CLEAR} 2006.201.11:47:53.21#ibcon#read 3, iclass 19, count 0 2006.201.11:47:53.21#ibcon#about to read 4, iclass 19, count 0 2006.201.11:47:53.21#ibcon#read 4, iclass 19, count 0 2006.201.11:47:53.21#ibcon#about to read 5, iclass 19, count 0 2006.201.11:47:53.21#ibcon#read 5, iclass 19, count 0 2006.201.11:47:53.21#ibcon#about to read 6, iclass 19, count 0 2006.201.11:47:53.21#ibcon#read 6, iclass 19, count 0 2006.201.11:47:53.21#ibcon#end of sib2, iclass 19, count 0 2006.201.11:47:53.21#ibcon#*after write, iclass 19, count 0 2006.201.11:47:53.21#ibcon#*before return 0, iclass 19, count 0 2006.201.11:47:53.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:53.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:53.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.11:47:53.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.11:47:53.21$vck44/valo=5,734.99 2006.201.11:47:53.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.11:47:53.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.11:47:53.21#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:53.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:47:53.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:47:53.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:47:53.21#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:47:53.21#ibcon#first serial, iclass 24, count 0 2006.201.11:47:53.21#ibcon#enter sib2, iclass 24, count 0 2006.201.11:47:53.21#ibcon#flushed, iclass 24, count 0 2006.201.11:47:53.21#ibcon#about to write, iclass 24, count 0 2006.201.11:47:53.21#ibcon#wrote, iclass 24, count 0 2006.201.11:47:53.21#ibcon#about to read 3, iclass 24, count 0 2006.201.11:47:53.23#ibcon#read 3, iclass 24, count 0 2006.201.11:47:53.23#ibcon#about to read 4, iclass 24, count 0 2006.201.11:47:53.23#ibcon#read 4, iclass 24, count 0 2006.201.11:47:53.23#ibcon#about to read 5, iclass 24, count 0 2006.201.11:47:53.23#ibcon#read 5, iclass 24, count 0 2006.201.11:47:53.23#ibcon#about to read 6, iclass 24, count 0 2006.201.11:47:53.23#ibcon#read 6, iclass 24, count 0 2006.201.11:47:53.23#ibcon#end of sib2, iclass 24, count 0 2006.201.11:47:53.23#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:47:53.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:47:53.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:47:53.23#ibcon#*before write, iclass 24, count 0 2006.201.11:47:53.23#ibcon#enter sib2, iclass 24, count 0 2006.201.11:47:53.23#ibcon#flushed, iclass 24, count 0 2006.201.11:47:53.23#ibcon#about to write, iclass 24, count 0 2006.201.11:47:53.23#ibcon#wrote, iclass 24, count 0 2006.201.11:47:53.23#ibcon#about to read 3, iclass 24, count 0 2006.201.11:47:53.27#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:47:53.27#ibcon#read 3, iclass 24, count 0 2006.201.11:47:53.27#ibcon#about to read 4, iclass 24, count 0 2006.201.11:47:53.27#ibcon#read 4, iclass 24, count 0 2006.201.11:47:53.27#ibcon#about to read 5, iclass 24, count 0 2006.201.11:47:53.27#ibcon#read 5, iclass 24, count 0 2006.201.11:47:53.27#ibcon#about to read 6, iclass 24, count 0 2006.201.11:47:53.27#ibcon#read 6, iclass 24, count 0 2006.201.11:47:53.27#ibcon#end of sib2, iclass 24, count 0 2006.201.11:47:53.27#ibcon#*after write, iclass 24, count 0 2006.201.11:47:53.27#ibcon#*before return 0, iclass 24, count 0 2006.201.11:47:53.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:47:53.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:47:53.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:47:53.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:47:53.27$vck44/va=5,4 2006.201.11:47:53.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.11:47:53.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.11:47:53.27#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:53.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:53.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:53.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:53.33#ibcon#enter wrdev, iclass 27, count 2 2006.201.11:47:53.33#ibcon#first serial, iclass 27, count 2 2006.201.11:47:53.33#ibcon#enter sib2, iclass 27, count 2 2006.201.11:47:53.33#ibcon#flushed, iclass 27, count 2 2006.201.11:47:53.33#ibcon#about to write, iclass 27, count 2 2006.201.11:47:53.33#ibcon#wrote, iclass 27, count 2 2006.201.11:47:53.33#ibcon#about to read 3, iclass 27, count 2 2006.201.11:47:53.35#ibcon#read 3, iclass 27, count 2 2006.201.11:47:53.35#ibcon#about to read 4, iclass 27, count 2 2006.201.11:47:53.35#ibcon#read 4, iclass 27, count 2 2006.201.11:47:53.35#ibcon#about to read 5, iclass 27, count 2 2006.201.11:47:53.35#ibcon#read 5, iclass 27, count 2 2006.201.11:47:53.35#ibcon#about to read 6, iclass 27, count 2 2006.201.11:47:53.35#ibcon#read 6, iclass 27, count 2 2006.201.11:47:53.35#ibcon#end of sib2, iclass 27, count 2 2006.201.11:47:53.35#ibcon#*mode == 0, iclass 27, count 2 2006.201.11:47:53.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.11:47:53.35#ibcon#[25=AT05-04\r\n] 2006.201.11:47:53.35#ibcon#*before write, iclass 27, count 2 2006.201.11:47:53.35#ibcon#enter sib2, iclass 27, count 2 2006.201.11:47:53.35#ibcon#flushed, iclass 27, count 2 2006.201.11:47:53.35#ibcon#about to write, iclass 27, count 2 2006.201.11:47:53.35#ibcon#wrote, iclass 27, count 2 2006.201.11:47:53.35#ibcon#about to read 3, iclass 27, count 2 2006.201.11:47:53.38#ibcon#read 3, iclass 27, count 2 2006.201.11:47:53.38#ibcon#about to read 4, iclass 27, count 2 2006.201.11:47:53.38#ibcon#read 4, iclass 27, count 2 2006.201.11:47:53.38#ibcon#about to read 5, iclass 27, count 2 2006.201.11:47:53.38#ibcon#read 5, iclass 27, count 2 2006.201.11:47:53.38#ibcon#about to read 6, iclass 27, count 2 2006.201.11:47:53.38#ibcon#read 6, iclass 27, count 2 2006.201.11:47:53.38#ibcon#end of sib2, iclass 27, count 2 2006.201.11:47:53.38#ibcon#*after write, iclass 27, count 2 2006.201.11:47:53.38#ibcon#*before return 0, iclass 27, count 2 2006.201.11:47:53.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:53.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:53.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.11:47:53.38#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:53.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:53.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:53.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:53.50#ibcon#enter wrdev, iclass 27, count 0 2006.201.11:47:53.50#ibcon#first serial, iclass 27, count 0 2006.201.11:47:53.50#ibcon#enter sib2, iclass 27, count 0 2006.201.11:47:53.50#ibcon#flushed, iclass 27, count 0 2006.201.11:47:53.50#ibcon#about to write, iclass 27, count 0 2006.201.11:47:53.50#ibcon#wrote, iclass 27, count 0 2006.201.11:47:53.50#ibcon#about to read 3, iclass 27, count 0 2006.201.11:47:53.52#ibcon#read 3, iclass 27, count 0 2006.201.11:47:53.52#ibcon#about to read 4, iclass 27, count 0 2006.201.11:47:53.52#ibcon#read 4, iclass 27, count 0 2006.201.11:47:53.52#ibcon#about to read 5, iclass 27, count 0 2006.201.11:47:53.52#ibcon#read 5, iclass 27, count 0 2006.201.11:47:53.52#ibcon#about to read 6, iclass 27, count 0 2006.201.11:47:53.52#ibcon#read 6, iclass 27, count 0 2006.201.11:47:53.52#ibcon#end of sib2, iclass 27, count 0 2006.201.11:47:53.52#ibcon#*mode == 0, iclass 27, count 0 2006.201.11:47:53.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.11:47:53.52#ibcon#[25=USB\r\n] 2006.201.11:47:53.52#ibcon#*before write, iclass 27, count 0 2006.201.11:47:53.52#ibcon#enter sib2, iclass 27, count 0 2006.201.11:47:53.52#ibcon#flushed, iclass 27, count 0 2006.201.11:47:53.52#ibcon#about to write, iclass 27, count 0 2006.201.11:47:53.52#ibcon#wrote, iclass 27, count 0 2006.201.11:47:53.52#ibcon#about to read 3, iclass 27, count 0 2006.201.11:47:53.55#ibcon#read 3, iclass 27, count 0 2006.201.11:47:53.55#ibcon#about to read 4, iclass 27, count 0 2006.201.11:47:53.55#ibcon#read 4, iclass 27, count 0 2006.201.11:47:53.55#ibcon#about to read 5, iclass 27, count 0 2006.201.11:47:53.55#ibcon#read 5, iclass 27, count 0 2006.201.11:47:53.55#ibcon#about to read 6, iclass 27, count 0 2006.201.11:47:53.55#ibcon#read 6, iclass 27, count 0 2006.201.11:47:53.55#ibcon#end of sib2, iclass 27, count 0 2006.201.11:47:53.55#ibcon#*after write, iclass 27, count 0 2006.201.11:47:53.55#ibcon#*before return 0, iclass 27, count 0 2006.201.11:47:53.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:53.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:53.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.11:47:53.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.11:47:53.55$vck44/valo=6,814.99 2006.201.11:47:53.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.11:47:53.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.11:47:53.55#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:53.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:53.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:53.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:53.55#ibcon#enter wrdev, iclass 29, count 0 2006.201.11:47:53.55#ibcon#first serial, iclass 29, count 0 2006.201.11:47:53.55#ibcon#enter sib2, iclass 29, count 0 2006.201.11:47:53.55#ibcon#flushed, iclass 29, count 0 2006.201.11:47:53.55#ibcon#about to write, iclass 29, count 0 2006.201.11:47:53.55#ibcon#wrote, iclass 29, count 0 2006.201.11:47:53.55#ibcon#about to read 3, iclass 29, count 0 2006.201.11:47:53.57#ibcon#read 3, iclass 29, count 0 2006.201.11:47:53.57#ibcon#about to read 4, iclass 29, count 0 2006.201.11:47:53.57#ibcon#read 4, iclass 29, count 0 2006.201.11:47:53.57#ibcon#about to read 5, iclass 29, count 0 2006.201.11:47:53.57#ibcon#read 5, iclass 29, count 0 2006.201.11:47:53.57#ibcon#about to read 6, iclass 29, count 0 2006.201.11:47:53.57#ibcon#read 6, iclass 29, count 0 2006.201.11:47:53.57#ibcon#end of sib2, iclass 29, count 0 2006.201.11:47:53.57#ibcon#*mode == 0, iclass 29, count 0 2006.201.11:47:53.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.11:47:53.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:47:53.57#ibcon#*before write, iclass 29, count 0 2006.201.11:47:53.57#ibcon#enter sib2, iclass 29, count 0 2006.201.11:47:53.57#ibcon#flushed, iclass 29, count 0 2006.201.11:47:53.57#ibcon#about to write, iclass 29, count 0 2006.201.11:47:53.57#ibcon#wrote, iclass 29, count 0 2006.201.11:47:53.57#ibcon#about to read 3, iclass 29, count 0 2006.201.11:47:53.61#ibcon#read 3, iclass 29, count 0 2006.201.11:47:53.61#ibcon#about to read 4, iclass 29, count 0 2006.201.11:47:53.61#ibcon#read 4, iclass 29, count 0 2006.201.11:47:53.61#ibcon#about to read 5, iclass 29, count 0 2006.201.11:47:53.61#ibcon#read 5, iclass 29, count 0 2006.201.11:47:53.61#ibcon#about to read 6, iclass 29, count 0 2006.201.11:47:53.61#ibcon#read 6, iclass 29, count 0 2006.201.11:47:53.61#ibcon#end of sib2, iclass 29, count 0 2006.201.11:47:53.61#ibcon#*after write, iclass 29, count 0 2006.201.11:47:53.61#ibcon#*before return 0, iclass 29, count 0 2006.201.11:47:53.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:53.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:53.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.11:47:53.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.11:47:53.61$vck44/va=6,5 2006.201.11:47:53.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.11:47:53.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.11:47:53.61#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:53.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:53.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:53.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:53.67#ibcon#enter wrdev, iclass 31, count 2 2006.201.11:47:53.67#ibcon#first serial, iclass 31, count 2 2006.201.11:47:53.67#ibcon#enter sib2, iclass 31, count 2 2006.201.11:47:53.67#ibcon#flushed, iclass 31, count 2 2006.201.11:47:53.67#ibcon#about to write, iclass 31, count 2 2006.201.11:47:53.67#ibcon#wrote, iclass 31, count 2 2006.201.11:47:53.67#ibcon#about to read 3, iclass 31, count 2 2006.201.11:47:53.69#ibcon#read 3, iclass 31, count 2 2006.201.11:47:53.69#ibcon#about to read 4, iclass 31, count 2 2006.201.11:47:53.69#ibcon#read 4, iclass 31, count 2 2006.201.11:47:53.69#ibcon#about to read 5, iclass 31, count 2 2006.201.11:47:53.69#ibcon#read 5, iclass 31, count 2 2006.201.11:47:53.69#ibcon#about to read 6, iclass 31, count 2 2006.201.11:47:53.69#ibcon#read 6, iclass 31, count 2 2006.201.11:47:53.69#ibcon#end of sib2, iclass 31, count 2 2006.201.11:47:53.69#ibcon#*mode == 0, iclass 31, count 2 2006.201.11:47:53.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.11:47:53.69#ibcon#[25=AT06-05\r\n] 2006.201.11:47:53.69#ibcon#*before write, iclass 31, count 2 2006.201.11:47:53.69#ibcon#enter sib2, iclass 31, count 2 2006.201.11:47:53.69#ibcon#flushed, iclass 31, count 2 2006.201.11:47:53.69#ibcon#about to write, iclass 31, count 2 2006.201.11:47:53.69#ibcon#wrote, iclass 31, count 2 2006.201.11:47:53.69#ibcon#about to read 3, iclass 31, count 2 2006.201.11:47:53.72#ibcon#read 3, iclass 31, count 2 2006.201.11:47:53.72#ibcon#about to read 4, iclass 31, count 2 2006.201.11:47:53.72#ibcon#read 4, iclass 31, count 2 2006.201.11:47:53.72#ibcon#about to read 5, iclass 31, count 2 2006.201.11:47:53.72#ibcon#read 5, iclass 31, count 2 2006.201.11:47:53.72#ibcon#about to read 6, iclass 31, count 2 2006.201.11:47:53.72#ibcon#read 6, iclass 31, count 2 2006.201.11:47:53.72#ibcon#end of sib2, iclass 31, count 2 2006.201.11:47:53.72#ibcon#*after write, iclass 31, count 2 2006.201.11:47:53.72#ibcon#*before return 0, iclass 31, count 2 2006.201.11:47:53.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:53.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:53.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.11:47:53.72#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:53.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:53.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:53.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:53.84#ibcon#enter wrdev, iclass 31, count 0 2006.201.11:47:53.84#ibcon#first serial, iclass 31, count 0 2006.201.11:47:53.84#ibcon#enter sib2, iclass 31, count 0 2006.201.11:47:53.84#ibcon#flushed, iclass 31, count 0 2006.201.11:47:53.84#ibcon#about to write, iclass 31, count 0 2006.201.11:47:53.84#ibcon#wrote, iclass 31, count 0 2006.201.11:47:53.84#ibcon#about to read 3, iclass 31, count 0 2006.201.11:47:53.86#ibcon#read 3, iclass 31, count 0 2006.201.11:47:53.86#ibcon#about to read 4, iclass 31, count 0 2006.201.11:47:53.86#ibcon#read 4, iclass 31, count 0 2006.201.11:47:53.86#ibcon#about to read 5, iclass 31, count 0 2006.201.11:47:53.86#ibcon#read 5, iclass 31, count 0 2006.201.11:47:53.86#ibcon#about to read 6, iclass 31, count 0 2006.201.11:47:53.86#ibcon#read 6, iclass 31, count 0 2006.201.11:47:53.86#ibcon#end of sib2, iclass 31, count 0 2006.201.11:47:53.86#ibcon#*mode == 0, iclass 31, count 0 2006.201.11:47:53.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.11:47:53.86#ibcon#[25=USB\r\n] 2006.201.11:47:53.86#ibcon#*before write, iclass 31, count 0 2006.201.11:47:53.86#ibcon#enter sib2, iclass 31, count 0 2006.201.11:47:53.86#ibcon#flushed, iclass 31, count 0 2006.201.11:47:53.86#ibcon#about to write, iclass 31, count 0 2006.201.11:47:53.86#ibcon#wrote, iclass 31, count 0 2006.201.11:47:53.86#ibcon#about to read 3, iclass 31, count 0 2006.201.11:47:53.89#ibcon#read 3, iclass 31, count 0 2006.201.11:47:53.89#ibcon#about to read 4, iclass 31, count 0 2006.201.11:47:53.89#ibcon#read 4, iclass 31, count 0 2006.201.11:47:53.89#ibcon#about to read 5, iclass 31, count 0 2006.201.11:47:53.89#ibcon#read 5, iclass 31, count 0 2006.201.11:47:53.89#ibcon#about to read 6, iclass 31, count 0 2006.201.11:47:53.89#ibcon#read 6, iclass 31, count 0 2006.201.11:47:53.89#ibcon#end of sib2, iclass 31, count 0 2006.201.11:47:53.89#ibcon#*after write, iclass 31, count 0 2006.201.11:47:53.89#ibcon#*before return 0, iclass 31, count 0 2006.201.11:47:53.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:53.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:53.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.11:47:53.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.11:47:53.89$vck44/valo=7,864.99 2006.201.11:47:53.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.11:47:53.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.11:47:53.89#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:53.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:53.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:53.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:53.89#ibcon#enter wrdev, iclass 33, count 0 2006.201.11:47:53.89#ibcon#first serial, iclass 33, count 0 2006.201.11:47:53.89#ibcon#enter sib2, iclass 33, count 0 2006.201.11:47:53.89#ibcon#flushed, iclass 33, count 0 2006.201.11:47:53.89#ibcon#about to write, iclass 33, count 0 2006.201.11:47:53.89#ibcon#wrote, iclass 33, count 0 2006.201.11:47:53.89#ibcon#about to read 3, iclass 33, count 0 2006.201.11:47:53.91#ibcon#read 3, iclass 33, count 0 2006.201.11:47:53.91#ibcon#about to read 4, iclass 33, count 0 2006.201.11:47:53.91#ibcon#read 4, iclass 33, count 0 2006.201.11:47:53.91#ibcon#about to read 5, iclass 33, count 0 2006.201.11:47:53.91#ibcon#read 5, iclass 33, count 0 2006.201.11:47:53.91#ibcon#about to read 6, iclass 33, count 0 2006.201.11:47:53.91#ibcon#read 6, iclass 33, count 0 2006.201.11:47:53.91#ibcon#end of sib2, iclass 33, count 0 2006.201.11:47:53.91#ibcon#*mode == 0, iclass 33, count 0 2006.201.11:47:53.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.11:47:53.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:47:53.91#ibcon#*before write, iclass 33, count 0 2006.201.11:47:53.91#ibcon#enter sib2, iclass 33, count 0 2006.201.11:47:53.91#ibcon#flushed, iclass 33, count 0 2006.201.11:47:53.91#ibcon#about to write, iclass 33, count 0 2006.201.11:47:53.91#ibcon#wrote, iclass 33, count 0 2006.201.11:47:53.91#ibcon#about to read 3, iclass 33, count 0 2006.201.11:47:53.96#ibcon#read 3, iclass 33, count 0 2006.201.11:47:53.96#ibcon#about to read 4, iclass 33, count 0 2006.201.11:47:53.96#ibcon#read 4, iclass 33, count 0 2006.201.11:47:53.96#ibcon#about to read 5, iclass 33, count 0 2006.201.11:47:53.96#ibcon#read 5, iclass 33, count 0 2006.201.11:47:53.96#ibcon#about to read 6, iclass 33, count 0 2006.201.11:47:53.96#ibcon#read 6, iclass 33, count 0 2006.201.11:47:53.96#ibcon#end of sib2, iclass 33, count 0 2006.201.11:47:53.96#ibcon#*after write, iclass 33, count 0 2006.201.11:47:53.96#ibcon#*before return 0, iclass 33, count 0 2006.201.11:47:53.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:53.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:53.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.11:47:53.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.11:47:53.96$vck44/va=7,5 2006.201.11:47:53.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.11:47:53.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.11:47:53.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:53.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:54.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:54.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:54.01#ibcon#enter wrdev, iclass 35, count 2 2006.201.11:47:54.01#ibcon#first serial, iclass 35, count 2 2006.201.11:47:54.01#ibcon#enter sib2, iclass 35, count 2 2006.201.11:47:54.01#ibcon#flushed, iclass 35, count 2 2006.201.11:47:54.01#ibcon#about to write, iclass 35, count 2 2006.201.11:47:54.01#ibcon#wrote, iclass 35, count 2 2006.201.11:47:54.01#ibcon#about to read 3, iclass 35, count 2 2006.201.11:47:54.03#ibcon#read 3, iclass 35, count 2 2006.201.11:47:54.03#ibcon#about to read 4, iclass 35, count 2 2006.201.11:47:54.03#ibcon#read 4, iclass 35, count 2 2006.201.11:47:54.03#ibcon#about to read 5, iclass 35, count 2 2006.201.11:47:54.03#ibcon#read 5, iclass 35, count 2 2006.201.11:47:54.03#ibcon#about to read 6, iclass 35, count 2 2006.201.11:47:54.03#ibcon#read 6, iclass 35, count 2 2006.201.11:47:54.03#ibcon#end of sib2, iclass 35, count 2 2006.201.11:47:54.03#ibcon#*mode == 0, iclass 35, count 2 2006.201.11:47:54.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.11:47:54.03#ibcon#[25=AT07-05\r\n] 2006.201.11:47:54.03#ibcon#*before write, iclass 35, count 2 2006.201.11:47:54.03#ibcon#enter sib2, iclass 35, count 2 2006.201.11:47:54.03#ibcon#flushed, iclass 35, count 2 2006.201.11:47:54.03#ibcon#about to write, iclass 35, count 2 2006.201.11:47:54.03#ibcon#wrote, iclass 35, count 2 2006.201.11:47:54.03#ibcon#about to read 3, iclass 35, count 2 2006.201.11:47:54.06#ibcon#read 3, iclass 35, count 2 2006.201.11:47:54.06#ibcon#about to read 4, iclass 35, count 2 2006.201.11:47:54.06#ibcon#read 4, iclass 35, count 2 2006.201.11:47:54.06#ibcon#about to read 5, iclass 35, count 2 2006.201.11:47:54.06#ibcon#read 5, iclass 35, count 2 2006.201.11:47:54.06#ibcon#about to read 6, iclass 35, count 2 2006.201.11:47:54.06#ibcon#read 6, iclass 35, count 2 2006.201.11:47:54.06#ibcon#end of sib2, iclass 35, count 2 2006.201.11:47:54.06#ibcon#*after write, iclass 35, count 2 2006.201.11:47:54.06#ibcon#*before return 0, iclass 35, count 2 2006.201.11:47:54.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:54.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:54.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.11:47:54.06#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:54.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:54.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:54.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:54.18#ibcon#enter wrdev, iclass 35, count 0 2006.201.11:47:54.18#ibcon#first serial, iclass 35, count 0 2006.201.11:47:54.18#ibcon#enter sib2, iclass 35, count 0 2006.201.11:47:54.18#ibcon#flushed, iclass 35, count 0 2006.201.11:47:54.18#ibcon#about to write, iclass 35, count 0 2006.201.11:47:54.18#ibcon#wrote, iclass 35, count 0 2006.201.11:47:54.18#ibcon#about to read 3, iclass 35, count 0 2006.201.11:47:54.20#ibcon#read 3, iclass 35, count 0 2006.201.11:47:54.20#ibcon#about to read 4, iclass 35, count 0 2006.201.11:47:54.20#ibcon#read 4, iclass 35, count 0 2006.201.11:47:54.20#ibcon#about to read 5, iclass 35, count 0 2006.201.11:47:54.20#ibcon#read 5, iclass 35, count 0 2006.201.11:47:54.20#ibcon#about to read 6, iclass 35, count 0 2006.201.11:47:54.20#ibcon#read 6, iclass 35, count 0 2006.201.11:47:54.20#ibcon#end of sib2, iclass 35, count 0 2006.201.11:47:54.20#ibcon#*mode == 0, iclass 35, count 0 2006.201.11:47:54.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.11:47:54.20#ibcon#[25=USB\r\n] 2006.201.11:47:54.20#ibcon#*before write, iclass 35, count 0 2006.201.11:47:54.20#ibcon#enter sib2, iclass 35, count 0 2006.201.11:47:54.20#ibcon#flushed, iclass 35, count 0 2006.201.11:47:54.20#ibcon#about to write, iclass 35, count 0 2006.201.11:47:54.20#ibcon#wrote, iclass 35, count 0 2006.201.11:47:54.20#ibcon#about to read 3, iclass 35, count 0 2006.201.11:47:54.23#ibcon#read 3, iclass 35, count 0 2006.201.11:47:54.23#ibcon#about to read 4, iclass 35, count 0 2006.201.11:47:54.23#ibcon#read 4, iclass 35, count 0 2006.201.11:47:54.23#ibcon#about to read 5, iclass 35, count 0 2006.201.11:47:54.23#ibcon#read 5, iclass 35, count 0 2006.201.11:47:54.23#ibcon#about to read 6, iclass 35, count 0 2006.201.11:47:54.23#ibcon#read 6, iclass 35, count 0 2006.201.11:47:54.23#ibcon#end of sib2, iclass 35, count 0 2006.201.11:47:54.23#ibcon#*after write, iclass 35, count 0 2006.201.11:47:54.23#ibcon#*before return 0, iclass 35, count 0 2006.201.11:47:54.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:54.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:54.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.11:47:54.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.11:47:54.23$vck44/valo=8,884.99 2006.201.11:47:54.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.11:47:54.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.11:47:54.23#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:54.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:54.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:54.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:54.23#ibcon#enter wrdev, iclass 37, count 0 2006.201.11:47:54.23#ibcon#first serial, iclass 37, count 0 2006.201.11:47:54.23#ibcon#enter sib2, iclass 37, count 0 2006.201.11:47:54.23#ibcon#flushed, iclass 37, count 0 2006.201.11:47:54.23#ibcon#about to write, iclass 37, count 0 2006.201.11:47:54.23#ibcon#wrote, iclass 37, count 0 2006.201.11:47:54.23#ibcon#about to read 3, iclass 37, count 0 2006.201.11:47:54.25#ibcon#read 3, iclass 37, count 0 2006.201.11:47:54.25#ibcon#about to read 4, iclass 37, count 0 2006.201.11:47:54.25#ibcon#read 4, iclass 37, count 0 2006.201.11:47:54.25#ibcon#about to read 5, iclass 37, count 0 2006.201.11:47:54.25#ibcon#read 5, iclass 37, count 0 2006.201.11:47:54.25#ibcon#about to read 6, iclass 37, count 0 2006.201.11:47:54.25#ibcon#read 6, iclass 37, count 0 2006.201.11:47:54.25#ibcon#end of sib2, iclass 37, count 0 2006.201.11:47:54.25#ibcon#*mode == 0, iclass 37, count 0 2006.201.11:47:54.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.11:47:54.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:47:54.25#ibcon#*before write, iclass 37, count 0 2006.201.11:47:54.25#ibcon#enter sib2, iclass 37, count 0 2006.201.11:47:54.25#ibcon#flushed, iclass 37, count 0 2006.201.11:47:54.25#ibcon#about to write, iclass 37, count 0 2006.201.11:47:54.25#ibcon#wrote, iclass 37, count 0 2006.201.11:47:54.25#ibcon#about to read 3, iclass 37, count 0 2006.201.11:47:54.29#ibcon#read 3, iclass 37, count 0 2006.201.11:47:54.29#ibcon#about to read 4, iclass 37, count 0 2006.201.11:47:54.29#ibcon#read 4, iclass 37, count 0 2006.201.11:47:54.29#ibcon#about to read 5, iclass 37, count 0 2006.201.11:47:54.29#ibcon#read 5, iclass 37, count 0 2006.201.11:47:54.29#ibcon#about to read 6, iclass 37, count 0 2006.201.11:47:54.29#ibcon#read 6, iclass 37, count 0 2006.201.11:47:54.29#ibcon#end of sib2, iclass 37, count 0 2006.201.11:47:54.29#ibcon#*after write, iclass 37, count 0 2006.201.11:47:54.29#ibcon#*before return 0, iclass 37, count 0 2006.201.11:47:54.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:54.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:54.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.11:47:54.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.11:47:54.29$vck44/va=8,4 2006.201.11:47:54.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.11:47:54.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.11:47:54.29#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:54.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:47:54.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:47:54.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:47:54.35#ibcon#enter wrdev, iclass 39, count 2 2006.201.11:47:54.35#ibcon#first serial, iclass 39, count 2 2006.201.11:47:54.35#ibcon#enter sib2, iclass 39, count 2 2006.201.11:47:54.35#ibcon#flushed, iclass 39, count 2 2006.201.11:47:54.35#ibcon#about to write, iclass 39, count 2 2006.201.11:47:54.35#ibcon#wrote, iclass 39, count 2 2006.201.11:47:54.35#ibcon#about to read 3, iclass 39, count 2 2006.201.11:47:54.37#ibcon#read 3, iclass 39, count 2 2006.201.11:47:54.37#ibcon#about to read 4, iclass 39, count 2 2006.201.11:47:54.37#ibcon#read 4, iclass 39, count 2 2006.201.11:47:54.37#ibcon#about to read 5, iclass 39, count 2 2006.201.11:47:54.37#ibcon#read 5, iclass 39, count 2 2006.201.11:47:54.37#ibcon#about to read 6, iclass 39, count 2 2006.201.11:47:54.37#ibcon#read 6, iclass 39, count 2 2006.201.11:47:54.37#ibcon#end of sib2, iclass 39, count 2 2006.201.11:47:54.37#ibcon#*mode == 0, iclass 39, count 2 2006.201.11:47:54.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.11:47:54.37#ibcon#[25=AT08-04\r\n] 2006.201.11:47:54.37#ibcon#*before write, iclass 39, count 2 2006.201.11:47:54.37#ibcon#enter sib2, iclass 39, count 2 2006.201.11:47:54.37#ibcon#flushed, iclass 39, count 2 2006.201.11:47:54.37#ibcon#about to write, iclass 39, count 2 2006.201.11:47:54.37#ibcon#wrote, iclass 39, count 2 2006.201.11:47:54.37#ibcon#about to read 3, iclass 39, count 2 2006.201.11:47:54.40#ibcon#read 3, iclass 39, count 2 2006.201.11:47:54.40#ibcon#about to read 4, iclass 39, count 2 2006.201.11:47:54.40#ibcon#read 4, iclass 39, count 2 2006.201.11:47:54.40#ibcon#about to read 5, iclass 39, count 2 2006.201.11:47:54.40#ibcon#read 5, iclass 39, count 2 2006.201.11:47:54.40#ibcon#about to read 6, iclass 39, count 2 2006.201.11:47:54.40#ibcon#read 6, iclass 39, count 2 2006.201.11:47:54.40#ibcon#end of sib2, iclass 39, count 2 2006.201.11:47:54.40#ibcon#*after write, iclass 39, count 2 2006.201.11:47:54.40#ibcon#*before return 0, iclass 39, count 2 2006.201.11:47:54.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:47:54.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.11:47:54.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.11:47:54.40#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:54.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:47:54.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:47:54.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:47:54.52#ibcon#enter wrdev, iclass 39, count 0 2006.201.11:47:54.52#ibcon#first serial, iclass 39, count 0 2006.201.11:47:54.52#ibcon#enter sib2, iclass 39, count 0 2006.201.11:47:54.52#ibcon#flushed, iclass 39, count 0 2006.201.11:47:54.52#ibcon#about to write, iclass 39, count 0 2006.201.11:47:54.52#ibcon#wrote, iclass 39, count 0 2006.201.11:47:54.52#ibcon#about to read 3, iclass 39, count 0 2006.201.11:47:54.54#ibcon#read 3, iclass 39, count 0 2006.201.11:47:54.54#ibcon#about to read 4, iclass 39, count 0 2006.201.11:47:54.54#ibcon#read 4, iclass 39, count 0 2006.201.11:47:54.54#ibcon#about to read 5, iclass 39, count 0 2006.201.11:47:54.54#ibcon#read 5, iclass 39, count 0 2006.201.11:47:54.54#ibcon#about to read 6, iclass 39, count 0 2006.201.11:47:54.54#ibcon#read 6, iclass 39, count 0 2006.201.11:47:54.54#ibcon#end of sib2, iclass 39, count 0 2006.201.11:47:54.54#ibcon#*mode == 0, iclass 39, count 0 2006.201.11:47:54.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.11:47:54.54#ibcon#[25=USB\r\n] 2006.201.11:47:54.54#ibcon#*before write, iclass 39, count 0 2006.201.11:47:54.54#ibcon#enter sib2, iclass 39, count 0 2006.201.11:47:54.54#ibcon#flushed, iclass 39, count 0 2006.201.11:47:54.54#ibcon#about to write, iclass 39, count 0 2006.201.11:47:54.54#ibcon#wrote, iclass 39, count 0 2006.201.11:47:54.54#ibcon#about to read 3, iclass 39, count 0 2006.201.11:47:54.57#ibcon#read 3, iclass 39, count 0 2006.201.11:47:54.57#ibcon#about to read 4, iclass 39, count 0 2006.201.11:47:54.57#ibcon#read 4, iclass 39, count 0 2006.201.11:47:54.57#ibcon#about to read 5, iclass 39, count 0 2006.201.11:47:54.57#ibcon#read 5, iclass 39, count 0 2006.201.11:47:54.57#ibcon#about to read 6, iclass 39, count 0 2006.201.11:47:54.57#ibcon#read 6, iclass 39, count 0 2006.201.11:47:54.57#ibcon#end of sib2, iclass 39, count 0 2006.201.11:47:54.57#ibcon#*after write, iclass 39, count 0 2006.201.11:47:54.57#ibcon#*before return 0, iclass 39, count 0 2006.201.11:47:54.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:47:54.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.11:47:54.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.11:47:54.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.11:47:54.57$vck44/vblo=1,629.99 2006.201.11:47:54.57#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.11:47:54.57#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.11:47:54.57#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:54.57#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:54.57#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:54.57#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:54.57#ibcon#enter wrdev, iclass 2, count 0 2006.201.11:47:54.57#ibcon#first serial, iclass 2, count 0 2006.201.11:47:54.57#ibcon#enter sib2, iclass 2, count 0 2006.201.11:47:54.57#ibcon#flushed, iclass 2, count 0 2006.201.11:47:54.57#ibcon#about to write, iclass 2, count 0 2006.201.11:47:54.57#ibcon#wrote, iclass 2, count 0 2006.201.11:47:54.57#ibcon#about to read 3, iclass 2, count 0 2006.201.11:47:54.59#ibcon#read 3, iclass 2, count 0 2006.201.11:47:54.59#ibcon#about to read 4, iclass 2, count 0 2006.201.11:47:54.59#ibcon#read 4, iclass 2, count 0 2006.201.11:47:54.59#ibcon#about to read 5, iclass 2, count 0 2006.201.11:47:54.59#ibcon#read 5, iclass 2, count 0 2006.201.11:47:54.59#ibcon#about to read 6, iclass 2, count 0 2006.201.11:47:54.59#ibcon#read 6, iclass 2, count 0 2006.201.11:47:54.59#ibcon#end of sib2, iclass 2, count 0 2006.201.11:47:54.59#ibcon#*mode == 0, iclass 2, count 0 2006.201.11:47:54.59#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.11:47:54.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:47:54.59#ibcon#*before write, iclass 2, count 0 2006.201.11:47:54.59#ibcon#enter sib2, iclass 2, count 0 2006.201.11:47:54.59#ibcon#flushed, iclass 2, count 0 2006.201.11:47:54.59#ibcon#about to write, iclass 2, count 0 2006.201.11:47:54.59#ibcon#wrote, iclass 2, count 0 2006.201.11:47:54.59#ibcon#about to read 3, iclass 2, count 0 2006.201.11:47:54.64#ibcon#read 3, iclass 2, count 0 2006.201.11:47:54.64#ibcon#about to read 4, iclass 2, count 0 2006.201.11:47:54.64#ibcon#read 4, iclass 2, count 0 2006.201.11:47:54.64#ibcon#about to read 5, iclass 2, count 0 2006.201.11:47:54.64#ibcon#read 5, iclass 2, count 0 2006.201.11:47:54.64#ibcon#about to read 6, iclass 2, count 0 2006.201.11:47:54.64#ibcon#read 6, iclass 2, count 0 2006.201.11:47:54.64#ibcon#end of sib2, iclass 2, count 0 2006.201.11:47:54.64#ibcon#*after write, iclass 2, count 0 2006.201.11:47:54.64#ibcon#*before return 0, iclass 2, count 0 2006.201.11:47:54.64#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:54.64#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.11:47:54.64#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.11:47:54.64#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.11:47:54.64$vck44/vb=1,4 2006.201.11:47:54.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.11:47:54.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.11:47:54.64#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:54.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:54.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:54.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:54.64#ibcon#enter wrdev, iclass 5, count 2 2006.201.11:47:54.64#ibcon#first serial, iclass 5, count 2 2006.201.11:47:54.64#ibcon#enter sib2, iclass 5, count 2 2006.201.11:47:54.64#ibcon#flushed, iclass 5, count 2 2006.201.11:47:54.64#ibcon#about to write, iclass 5, count 2 2006.201.11:47:54.64#ibcon#wrote, iclass 5, count 2 2006.201.11:47:54.64#ibcon#about to read 3, iclass 5, count 2 2006.201.11:47:54.66#ibcon#read 3, iclass 5, count 2 2006.201.11:47:54.66#ibcon#about to read 4, iclass 5, count 2 2006.201.11:47:54.66#ibcon#read 4, iclass 5, count 2 2006.201.11:47:54.66#ibcon#about to read 5, iclass 5, count 2 2006.201.11:47:54.66#ibcon#read 5, iclass 5, count 2 2006.201.11:47:54.66#ibcon#about to read 6, iclass 5, count 2 2006.201.11:47:54.66#ibcon#read 6, iclass 5, count 2 2006.201.11:47:54.66#ibcon#end of sib2, iclass 5, count 2 2006.201.11:47:54.66#ibcon#*mode == 0, iclass 5, count 2 2006.201.11:47:54.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.11:47:54.66#ibcon#[27=AT01-04\r\n] 2006.201.11:47:54.66#ibcon#*before write, iclass 5, count 2 2006.201.11:47:54.66#ibcon#enter sib2, iclass 5, count 2 2006.201.11:47:54.66#ibcon#flushed, iclass 5, count 2 2006.201.11:47:54.66#ibcon#about to write, iclass 5, count 2 2006.201.11:47:54.66#ibcon#wrote, iclass 5, count 2 2006.201.11:47:54.66#ibcon#about to read 3, iclass 5, count 2 2006.201.11:47:54.69#ibcon#read 3, iclass 5, count 2 2006.201.11:47:54.69#ibcon#about to read 4, iclass 5, count 2 2006.201.11:47:54.69#ibcon#read 4, iclass 5, count 2 2006.201.11:47:54.69#ibcon#about to read 5, iclass 5, count 2 2006.201.11:47:54.69#ibcon#read 5, iclass 5, count 2 2006.201.11:47:54.69#ibcon#about to read 6, iclass 5, count 2 2006.201.11:47:54.69#ibcon#read 6, iclass 5, count 2 2006.201.11:47:54.69#ibcon#end of sib2, iclass 5, count 2 2006.201.11:47:54.69#ibcon#*after write, iclass 5, count 2 2006.201.11:47:54.69#ibcon#*before return 0, iclass 5, count 2 2006.201.11:47:54.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:54.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.11:47:54.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.11:47:54.69#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:54.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:54.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:54.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:54.81#ibcon#enter wrdev, iclass 5, count 0 2006.201.11:47:54.81#ibcon#first serial, iclass 5, count 0 2006.201.11:47:54.81#ibcon#enter sib2, iclass 5, count 0 2006.201.11:47:54.81#ibcon#flushed, iclass 5, count 0 2006.201.11:47:54.81#ibcon#about to write, iclass 5, count 0 2006.201.11:47:54.81#ibcon#wrote, iclass 5, count 0 2006.201.11:47:54.81#ibcon#about to read 3, iclass 5, count 0 2006.201.11:47:54.83#ibcon#read 3, iclass 5, count 0 2006.201.11:47:54.83#ibcon#about to read 4, iclass 5, count 0 2006.201.11:47:54.83#ibcon#read 4, iclass 5, count 0 2006.201.11:47:54.83#ibcon#about to read 5, iclass 5, count 0 2006.201.11:47:54.83#ibcon#read 5, iclass 5, count 0 2006.201.11:47:54.83#ibcon#about to read 6, iclass 5, count 0 2006.201.11:47:54.83#ibcon#read 6, iclass 5, count 0 2006.201.11:47:54.83#ibcon#end of sib2, iclass 5, count 0 2006.201.11:47:54.83#ibcon#*mode == 0, iclass 5, count 0 2006.201.11:47:54.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.11:47:54.83#ibcon#[27=USB\r\n] 2006.201.11:47:54.83#ibcon#*before write, iclass 5, count 0 2006.201.11:47:54.83#ibcon#enter sib2, iclass 5, count 0 2006.201.11:47:54.83#ibcon#flushed, iclass 5, count 0 2006.201.11:47:54.83#ibcon#about to write, iclass 5, count 0 2006.201.11:47:54.83#ibcon#wrote, iclass 5, count 0 2006.201.11:47:54.83#ibcon#about to read 3, iclass 5, count 0 2006.201.11:47:54.86#ibcon#read 3, iclass 5, count 0 2006.201.11:47:54.86#ibcon#about to read 4, iclass 5, count 0 2006.201.11:47:54.86#ibcon#read 4, iclass 5, count 0 2006.201.11:47:54.86#ibcon#about to read 5, iclass 5, count 0 2006.201.11:47:54.86#ibcon#read 5, iclass 5, count 0 2006.201.11:47:54.86#ibcon#about to read 6, iclass 5, count 0 2006.201.11:47:54.86#ibcon#read 6, iclass 5, count 0 2006.201.11:47:54.86#ibcon#end of sib2, iclass 5, count 0 2006.201.11:47:54.86#ibcon#*after write, iclass 5, count 0 2006.201.11:47:54.86#ibcon#*before return 0, iclass 5, count 0 2006.201.11:47:54.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:54.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.11:47:54.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.11:47:54.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.11:47:54.86$vck44/vblo=2,634.99 2006.201.11:47:54.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.11:47:54.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.11:47:54.86#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:54.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:54.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:54.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:54.86#ibcon#enter wrdev, iclass 7, count 0 2006.201.11:47:54.86#ibcon#first serial, iclass 7, count 0 2006.201.11:47:54.86#ibcon#enter sib2, iclass 7, count 0 2006.201.11:47:54.86#ibcon#flushed, iclass 7, count 0 2006.201.11:47:54.86#ibcon#about to write, iclass 7, count 0 2006.201.11:47:54.86#ibcon#wrote, iclass 7, count 0 2006.201.11:47:54.86#ibcon#about to read 3, iclass 7, count 0 2006.201.11:47:54.88#ibcon#read 3, iclass 7, count 0 2006.201.11:47:54.88#ibcon#about to read 4, iclass 7, count 0 2006.201.11:47:54.88#ibcon#read 4, iclass 7, count 0 2006.201.11:47:54.88#ibcon#about to read 5, iclass 7, count 0 2006.201.11:47:54.88#ibcon#read 5, iclass 7, count 0 2006.201.11:47:54.88#ibcon#about to read 6, iclass 7, count 0 2006.201.11:47:54.88#ibcon#read 6, iclass 7, count 0 2006.201.11:47:54.88#ibcon#end of sib2, iclass 7, count 0 2006.201.11:47:54.88#ibcon#*mode == 0, iclass 7, count 0 2006.201.11:47:54.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.11:47:54.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:47:54.88#ibcon#*before write, iclass 7, count 0 2006.201.11:47:54.88#ibcon#enter sib2, iclass 7, count 0 2006.201.11:47:54.88#ibcon#flushed, iclass 7, count 0 2006.201.11:47:54.88#ibcon#about to write, iclass 7, count 0 2006.201.11:47:54.88#ibcon#wrote, iclass 7, count 0 2006.201.11:47:54.88#ibcon#about to read 3, iclass 7, count 0 2006.201.11:47:54.92#ibcon#read 3, iclass 7, count 0 2006.201.11:47:54.92#ibcon#about to read 4, iclass 7, count 0 2006.201.11:47:54.92#ibcon#read 4, iclass 7, count 0 2006.201.11:47:54.92#ibcon#about to read 5, iclass 7, count 0 2006.201.11:47:54.92#ibcon#read 5, iclass 7, count 0 2006.201.11:47:54.92#ibcon#about to read 6, iclass 7, count 0 2006.201.11:47:54.92#ibcon#read 6, iclass 7, count 0 2006.201.11:47:54.92#ibcon#end of sib2, iclass 7, count 0 2006.201.11:47:54.92#ibcon#*after write, iclass 7, count 0 2006.201.11:47:54.92#ibcon#*before return 0, iclass 7, count 0 2006.201.11:47:54.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:54.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.11:47:54.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.11:47:54.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.11:47:54.92$vck44/vb=2,5 2006.201.11:47:54.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.11:47:54.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.11:47:54.92#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:54.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:54.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:54.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:54.98#ibcon#enter wrdev, iclass 11, count 2 2006.201.11:47:54.98#ibcon#first serial, iclass 11, count 2 2006.201.11:47:54.98#ibcon#enter sib2, iclass 11, count 2 2006.201.11:47:54.98#ibcon#flushed, iclass 11, count 2 2006.201.11:47:54.98#ibcon#about to write, iclass 11, count 2 2006.201.11:47:54.98#ibcon#wrote, iclass 11, count 2 2006.201.11:47:54.98#ibcon#about to read 3, iclass 11, count 2 2006.201.11:47:55.00#ibcon#read 3, iclass 11, count 2 2006.201.11:47:55.00#ibcon#about to read 4, iclass 11, count 2 2006.201.11:47:55.00#ibcon#read 4, iclass 11, count 2 2006.201.11:47:55.00#ibcon#about to read 5, iclass 11, count 2 2006.201.11:47:55.00#ibcon#read 5, iclass 11, count 2 2006.201.11:47:55.00#ibcon#about to read 6, iclass 11, count 2 2006.201.11:47:55.00#ibcon#read 6, iclass 11, count 2 2006.201.11:47:55.00#ibcon#end of sib2, iclass 11, count 2 2006.201.11:47:55.00#ibcon#*mode == 0, iclass 11, count 2 2006.201.11:47:55.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.11:47:55.00#ibcon#[27=AT02-05\r\n] 2006.201.11:47:55.00#ibcon#*before write, iclass 11, count 2 2006.201.11:47:55.00#ibcon#enter sib2, iclass 11, count 2 2006.201.11:47:55.00#ibcon#flushed, iclass 11, count 2 2006.201.11:47:55.00#ibcon#about to write, iclass 11, count 2 2006.201.11:47:55.00#ibcon#wrote, iclass 11, count 2 2006.201.11:47:55.00#ibcon#about to read 3, iclass 11, count 2 2006.201.11:47:55.03#ibcon#read 3, iclass 11, count 2 2006.201.11:47:55.03#ibcon#about to read 4, iclass 11, count 2 2006.201.11:47:55.03#ibcon#read 4, iclass 11, count 2 2006.201.11:47:55.03#ibcon#about to read 5, iclass 11, count 2 2006.201.11:47:55.03#ibcon#read 5, iclass 11, count 2 2006.201.11:47:55.03#ibcon#about to read 6, iclass 11, count 2 2006.201.11:47:55.03#ibcon#read 6, iclass 11, count 2 2006.201.11:47:55.03#ibcon#end of sib2, iclass 11, count 2 2006.201.11:47:55.03#ibcon#*after write, iclass 11, count 2 2006.201.11:47:55.03#ibcon#*before return 0, iclass 11, count 2 2006.201.11:47:55.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:55.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.11:47:55.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.11:47:55.03#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:55.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:55.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:55.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:55.15#ibcon#enter wrdev, iclass 11, count 0 2006.201.11:47:55.15#ibcon#first serial, iclass 11, count 0 2006.201.11:47:55.15#ibcon#enter sib2, iclass 11, count 0 2006.201.11:47:55.15#ibcon#flushed, iclass 11, count 0 2006.201.11:47:55.15#ibcon#about to write, iclass 11, count 0 2006.201.11:47:55.15#ibcon#wrote, iclass 11, count 0 2006.201.11:47:55.15#ibcon#about to read 3, iclass 11, count 0 2006.201.11:47:55.17#ibcon#read 3, iclass 11, count 0 2006.201.11:47:55.17#ibcon#about to read 4, iclass 11, count 0 2006.201.11:47:55.17#ibcon#read 4, iclass 11, count 0 2006.201.11:47:55.17#ibcon#about to read 5, iclass 11, count 0 2006.201.11:47:55.17#ibcon#read 5, iclass 11, count 0 2006.201.11:47:55.17#ibcon#about to read 6, iclass 11, count 0 2006.201.11:47:55.17#ibcon#read 6, iclass 11, count 0 2006.201.11:47:55.17#ibcon#end of sib2, iclass 11, count 0 2006.201.11:47:55.17#ibcon#*mode == 0, iclass 11, count 0 2006.201.11:47:55.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.11:47:55.17#ibcon#[27=USB\r\n] 2006.201.11:47:55.17#ibcon#*before write, iclass 11, count 0 2006.201.11:47:55.17#ibcon#enter sib2, iclass 11, count 0 2006.201.11:47:55.17#ibcon#flushed, iclass 11, count 0 2006.201.11:47:55.17#ibcon#about to write, iclass 11, count 0 2006.201.11:47:55.17#ibcon#wrote, iclass 11, count 0 2006.201.11:47:55.17#ibcon#about to read 3, iclass 11, count 0 2006.201.11:47:55.20#ibcon#read 3, iclass 11, count 0 2006.201.11:47:55.20#ibcon#about to read 4, iclass 11, count 0 2006.201.11:47:55.20#ibcon#read 4, iclass 11, count 0 2006.201.11:47:55.20#ibcon#about to read 5, iclass 11, count 0 2006.201.11:47:55.20#ibcon#read 5, iclass 11, count 0 2006.201.11:47:55.20#ibcon#about to read 6, iclass 11, count 0 2006.201.11:47:55.20#ibcon#read 6, iclass 11, count 0 2006.201.11:47:55.20#ibcon#end of sib2, iclass 11, count 0 2006.201.11:47:55.20#ibcon#*after write, iclass 11, count 0 2006.201.11:47:55.20#ibcon#*before return 0, iclass 11, count 0 2006.201.11:47:55.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:55.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.11:47:55.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.11:47:55.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.11:47:55.20$vck44/vblo=3,649.99 2006.201.11:47:55.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.11:47:55.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.11:47:55.20#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:55.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:55.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:55.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:55.20#ibcon#enter wrdev, iclass 13, count 0 2006.201.11:47:55.20#ibcon#first serial, iclass 13, count 0 2006.201.11:47:55.20#ibcon#enter sib2, iclass 13, count 0 2006.201.11:47:55.20#ibcon#flushed, iclass 13, count 0 2006.201.11:47:55.20#ibcon#about to write, iclass 13, count 0 2006.201.11:47:55.20#ibcon#wrote, iclass 13, count 0 2006.201.11:47:55.20#ibcon#about to read 3, iclass 13, count 0 2006.201.11:47:55.22#ibcon#read 3, iclass 13, count 0 2006.201.11:47:55.22#ibcon#about to read 4, iclass 13, count 0 2006.201.11:47:55.22#ibcon#read 4, iclass 13, count 0 2006.201.11:47:55.22#ibcon#about to read 5, iclass 13, count 0 2006.201.11:47:55.22#ibcon#read 5, iclass 13, count 0 2006.201.11:47:55.22#ibcon#about to read 6, iclass 13, count 0 2006.201.11:47:55.22#ibcon#read 6, iclass 13, count 0 2006.201.11:47:55.22#ibcon#end of sib2, iclass 13, count 0 2006.201.11:47:55.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.11:47:55.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.11:47:55.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:47:55.22#ibcon#*before write, iclass 13, count 0 2006.201.11:47:55.22#ibcon#enter sib2, iclass 13, count 0 2006.201.11:47:55.22#ibcon#flushed, iclass 13, count 0 2006.201.11:47:55.22#ibcon#about to write, iclass 13, count 0 2006.201.11:47:55.22#ibcon#wrote, iclass 13, count 0 2006.201.11:47:55.22#ibcon#about to read 3, iclass 13, count 0 2006.201.11:47:55.26#ibcon#read 3, iclass 13, count 0 2006.201.11:47:55.26#ibcon#about to read 4, iclass 13, count 0 2006.201.11:47:55.26#ibcon#read 4, iclass 13, count 0 2006.201.11:47:55.26#ibcon#about to read 5, iclass 13, count 0 2006.201.11:47:55.26#ibcon#read 5, iclass 13, count 0 2006.201.11:47:55.26#ibcon#about to read 6, iclass 13, count 0 2006.201.11:47:55.26#ibcon#read 6, iclass 13, count 0 2006.201.11:47:55.26#ibcon#end of sib2, iclass 13, count 0 2006.201.11:47:55.26#ibcon#*after write, iclass 13, count 0 2006.201.11:47:55.26#ibcon#*before return 0, iclass 13, count 0 2006.201.11:47:55.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:55.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.11:47:55.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.11:47:55.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.11:47:55.26$vck44/vb=3,4 2006.201.11:47:55.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.11:47:55.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.11:47:55.26#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:55.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:55.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:55.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:55.32#ibcon#enter wrdev, iclass 15, count 2 2006.201.11:47:55.32#ibcon#first serial, iclass 15, count 2 2006.201.11:47:55.32#ibcon#enter sib2, iclass 15, count 2 2006.201.11:47:55.32#ibcon#flushed, iclass 15, count 2 2006.201.11:47:55.32#ibcon#about to write, iclass 15, count 2 2006.201.11:47:55.32#ibcon#wrote, iclass 15, count 2 2006.201.11:47:55.32#ibcon#about to read 3, iclass 15, count 2 2006.201.11:47:55.34#ibcon#read 3, iclass 15, count 2 2006.201.11:47:55.34#ibcon#about to read 4, iclass 15, count 2 2006.201.11:47:55.34#ibcon#read 4, iclass 15, count 2 2006.201.11:47:55.34#ibcon#about to read 5, iclass 15, count 2 2006.201.11:47:55.34#ibcon#read 5, iclass 15, count 2 2006.201.11:47:55.34#ibcon#about to read 6, iclass 15, count 2 2006.201.11:47:55.34#ibcon#read 6, iclass 15, count 2 2006.201.11:47:55.34#ibcon#end of sib2, iclass 15, count 2 2006.201.11:47:55.34#ibcon#*mode == 0, iclass 15, count 2 2006.201.11:47:55.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.11:47:55.34#ibcon#[27=AT03-04\r\n] 2006.201.11:47:55.34#ibcon#*before write, iclass 15, count 2 2006.201.11:47:55.34#ibcon#enter sib2, iclass 15, count 2 2006.201.11:47:55.34#ibcon#flushed, iclass 15, count 2 2006.201.11:47:55.34#ibcon#about to write, iclass 15, count 2 2006.201.11:47:55.34#ibcon#wrote, iclass 15, count 2 2006.201.11:47:55.34#ibcon#about to read 3, iclass 15, count 2 2006.201.11:47:55.37#ibcon#read 3, iclass 15, count 2 2006.201.11:47:55.37#ibcon#about to read 4, iclass 15, count 2 2006.201.11:47:55.37#ibcon#read 4, iclass 15, count 2 2006.201.11:47:55.37#ibcon#about to read 5, iclass 15, count 2 2006.201.11:47:55.37#ibcon#read 5, iclass 15, count 2 2006.201.11:47:55.37#ibcon#about to read 6, iclass 15, count 2 2006.201.11:47:55.37#ibcon#read 6, iclass 15, count 2 2006.201.11:47:55.37#ibcon#end of sib2, iclass 15, count 2 2006.201.11:47:55.37#ibcon#*after write, iclass 15, count 2 2006.201.11:47:55.37#ibcon#*before return 0, iclass 15, count 2 2006.201.11:47:55.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:55.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.11:47:55.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.11:47:55.37#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:55.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:55.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:55.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:55.49#ibcon#enter wrdev, iclass 15, count 0 2006.201.11:47:55.49#ibcon#first serial, iclass 15, count 0 2006.201.11:47:55.49#ibcon#enter sib2, iclass 15, count 0 2006.201.11:47:55.49#ibcon#flushed, iclass 15, count 0 2006.201.11:47:55.49#ibcon#about to write, iclass 15, count 0 2006.201.11:47:55.49#ibcon#wrote, iclass 15, count 0 2006.201.11:47:55.49#ibcon#about to read 3, iclass 15, count 0 2006.201.11:47:55.51#ibcon#read 3, iclass 15, count 0 2006.201.11:47:55.51#ibcon#about to read 4, iclass 15, count 0 2006.201.11:47:55.51#ibcon#read 4, iclass 15, count 0 2006.201.11:47:55.51#ibcon#about to read 5, iclass 15, count 0 2006.201.11:47:55.51#ibcon#read 5, iclass 15, count 0 2006.201.11:47:55.51#ibcon#about to read 6, iclass 15, count 0 2006.201.11:47:55.51#ibcon#read 6, iclass 15, count 0 2006.201.11:47:55.51#ibcon#end of sib2, iclass 15, count 0 2006.201.11:47:55.51#ibcon#*mode == 0, iclass 15, count 0 2006.201.11:47:55.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.11:47:55.51#ibcon#[27=USB\r\n] 2006.201.11:47:55.51#ibcon#*before write, iclass 15, count 0 2006.201.11:47:55.51#ibcon#enter sib2, iclass 15, count 0 2006.201.11:47:55.51#ibcon#flushed, iclass 15, count 0 2006.201.11:47:55.51#ibcon#about to write, iclass 15, count 0 2006.201.11:47:55.51#ibcon#wrote, iclass 15, count 0 2006.201.11:47:55.51#ibcon#about to read 3, iclass 15, count 0 2006.201.11:47:55.54#ibcon#read 3, iclass 15, count 0 2006.201.11:47:55.54#ibcon#about to read 4, iclass 15, count 0 2006.201.11:47:55.54#ibcon#read 4, iclass 15, count 0 2006.201.11:47:55.54#ibcon#about to read 5, iclass 15, count 0 2006.201.11:47:55.54#ibcon#read 5, iclass 15, count 0 2006.201.11:47:55.54#ibcon#about to read 6, iclass 15, count 0 2006.201.11:47:55.54#ibcon#read 6, iclass 15, count 0 2006.201.11:47:55.54#ibcon#end of sib2, iclass 15, count 0 2006.201.11:47:55.54#ibcon#*after write, iclass 15, count 0 2006.201.11:47:55.54#ibcon#*before return 0, iclass 15, count 0 2006.201.11:47:55.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:55.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.11:47:55.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.11:47:55.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.11:47:55.54$vck44/vblo=4,679.99 2006.201.11:47:55.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.11:47:55.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.11:47:55.54#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:55.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:55.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:55.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:55.54#ibcon#enter wrdev, iclass 17, count 0 2006.201.11:47:55.54#ibcon#first serial, iclass 17, count 0 2006.201.11:47:55.54#ibcon#enter sib2, iclass 17, count 0 2006.201.11:47:55.54#ibcon#flushed, iclass 17, count 0 2006.201.11:47:55.54#ibcon#about to write, iclass 17, count 0 2006.201.11:47:55.54#ibcon#wrote, iclass 17, count 0 2006.201.11:47:55.54#ibcon#about to read 3, iclass 17, count 0 2006.201.11:47:55.56#ibcon#read 3, iclass 17, count 0 2006.201.11:47:55.56#ibcon#about to read 4, iclass 17, count 0 2006.201.11:47:55.56#ibcon#read 4, iclass 17, count 0 2006.201.11:47:55.56#ibcon#about to read 5, iclass 17, count 0 2006.201.11:47:55.56#ibcon#read 5, iclass 17, count 0 2006.201.11:47:55.56#ibcon#about to read 6, iclass 17, count 0 2006.201.11:47:55.56#ibcon#read 6, iclass 17, count 0 2006.201.11:47:55.56#ibcon#end of sib2, iclass 17, count 0 2006.201.11:47:55.56#ibcon#*mode == 0, iclass 17, count 0 2006.201.11:47:55.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.11:47:55.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:47:55.56#ibcon#*before write, iclass 17, count 0 2006.201.11:47:55.56#ibcon#enter sib2, iclass 17, count 0 2006.201.11:47:55.56#ibcon#flushed, iclass 17, count 0 2006.201.11:47:55.56#ibcon#about to write, iclass 17, count 0 2006.201.11:47:55.56#ibcon#wrote, iclass 17, count 0 2006.201.11:47:55.56#ibcon#about to read 3, iclass 17, count 0 2006.201.11:47:55.61#ibcon#read 3, iclass 17, count 0 2006.201.11:47:55.61#ibcon#about to read 4, iclass 17, count 0 2006.201.11:47:55.61#ibcon#read 4, iclass 17, count 0 2006.201.11:47:55.61#ibcon#about to read 5, iclass 17, count 0 2006.201.11:47:55.61#ibcon#read 5, iclass 17, count 0 2006.201.11:47:55.61#ibcon#about to read 6, iclass 17, count 0 2006.201.11:47:55.61#ibcon#read 6, iclass 17, count 0 2006.201.11:47:55.61#ibcon#end of sib2, iclass 17, count 0 2006.201.11:47:55.61#ibcon#*after write, iclass 17, count 0 2006.201.11:47:55.61#ibcon#*before return 0, iclass 17, count 0 2006.201.11:47:55.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:55.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.11:47:55.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.11:47:55.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.11:47:55.61$vck44/vb=4,5 2006.201.11:47:55.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.11:47:55.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.11:47:55.61#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:55.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:55.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:55.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:55.66#ibcon#enter wrdev, iclass 19, count 2 2006.201.11:47:55.66#ibcon#first serial, iclass 19, count 2 2006.201.11:47:55.66#ibcon#enter sib2, iclass 19, count 2 2006.201.11:47:55.66#ibcon#flushed, iclass 19, count 2 2006.201.11:47:55.66#ibcon#about to write, iclass 19, count 2 2006.201.11:47:55.66#ibcon#wrote, iclass 19, count 2 2006.201.11:47:55.66#ibcon#about to read 3, iclass 19, count 2 2006.201.11:47:55.68#ibcon#read 3, iclass 19, count 2 2006.201.11:47:55.68#ibcon#about to read 4, iclass 19, count 2 2006.201.11:47:55.68#ibcon#read 4, iclass 19, count 2 2006.201.11:47:55.68#ibcon#about to read 5, iclass 19, count 2 2006.201.11:47:55.68#ibcon#read 5, iclass 19, count 2 2006.201.11:47:55.68#ibcon#about to read 6, iclass 19, count 2 2006.201.11:47:55.68#ibcon#read 6, iclass 19, count 2 2006.201.11:47:55.68#ibcon#end of sib2, iclass 19, count 2 2006.201.11:47:55.68#ibcon#*mode == 0, iclass 19, count 2 2006.201.11:47:55.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.11:47:55.68#ibcon#[27=AT04-05\r\n] 2006.201.11:47:55.68#ibcon#*before write, iclass 19, count 2 2006.201.11:47:55.68#ibcon#enter sib2, iclass 19, count 2 2006.201.11:47:55.68#ibcon#flushed, iclass 19, count 2 2006.201.11:47:55.68#ibcon#about to write, iclass 19, count 2 2006.201.11:47:55.68#ibcon#wrote, iclass 19, count 2 2006.201.11:47:55.68#ibcon#about to read 3, iclass 19, count 2 2006.201.11:47:55.71#ibcon#read 3, iclass 19, count 2 2006.201.11:47:55.71#ibcon#about to read 4, iclass 19, count 2 2006.201.11:47:55.71#ibcon#read 4, iclass 19, count 2 2006.201.11:47:55.71#ibcon#about to read 5, iclass 19, count 2 2006.201.11:47:55.71#ibcon#read 5, iclass 19, count 2 2006.201.11:47:55.71#ibcon#about to read 6, iclass 19, count 2 2006.201.11:47:55.71#ibcon#read 6, iclass 19, count 2 2006.201.11:47:55.71#ibcon#end of sib2, iclass 19, count 2 2006.201.11:47:55.71#ibcon#*after write, iclass 19, count 2 2006.201.11:47:55.71#ibcon#*before return 0, iclass 19, count 2 2006.201.11:47:55.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:55.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.11:47:55.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.11:47:55.71#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:55.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:55.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:55.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:55.83#ibcon#enter wrdev, iclass 19, count 0 2006.201.11:47:55.83#ibcon#first serial, iclass 19, count 0 2006.201.11:47:55.83#ibcon#enter sib2, iclass 19, count 0 2006.201.11:47:55.83#ibcon#flushed, iclass 19, count 0 2006.201.11:47:55.83#ibcon#about to write, iclass 19, count 0 2006.201.11:47:55.83#ibcon#wrote, iclass 19, count 0 2006.201.11:47:55.83#ibcon#about to read 3, iclass 19, count 0 2006.201.11:47:55.85#ibcon#read 3, iclass 19, count 0 2006.201.11:47:55.85#ibcon#about to read 4, iclass 19, count 0 2006.201.11:47:55.85#ibcon#read 4, iclass 19, count 0 2006.201.11:47:55.85#ibcon#about to read 5, iclass 19, count 0 2006.201.11:47:55.85#ibcon#read 5, iclass 19, count 0 2006.201.11:47:55.85#ibcon#about to read 6, iclass 19, count 0 2006.201.11:47:55.85#ibcon#read 6, iclass 19, count 0 2006.201.11:47:55.85#ibcon#end of sib2, iclass 19, count 0 2006.201.11:47:55.85#ibcon#*mode == 0, iclass 19, count 0 2006.201.11:47:55.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.11:47:55.85#ibcon#[27=USB\r\n] 2006.201.11:47:55.85#ibcon#*before write, iclass 19, count 0 2006.201.11:47:55.85#ibcon#enter sib2, iclass 19, count 0 2006.201.11:47:55.85#ibcon#flushed, iclass 19, count 0 2006.201.11:47:55.85#ibcon#about to write, iclass 19, count 0 2006.201.11:47:55.85#ibcon#wrote, iclass 19, count 0 2006.201.11:47:55.85#ibcon#about to read 3, iclass 19, count 0 2006.201.11:47:55.88#ibcon#read 3, iclass 19, count 0 2006.201.11:47:55.88#ibcon#about to read 4, iclass 19, count 0 2006.201.11:47:55.88#ibcon#read 4, iclass 19, count 0 2006.201.11:47:55.88#ibcon#about to read 5, iclass 19, count 0 2006.201.11:47:55.88#ibcon#read 5, iclass 19, count 0 2006.201.11:47:55.88#ibcon#about to read 6, iclass 19, count 0 2006.201.11:47:55.88#ibcon#read 6, iclass 19, count 0 2006.201.11:47:55.88#ibcon#end of sib2, iclass 19, count 0 2006.201.11:47:55.88#ibcon#*after write, iclass 19, count 0 2006.201.11:47:55.88#ibcon#*before return 0, iclass 19, count 0 2006.201.11:47:55.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:55.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.11:47:55.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.11:47:55.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.11:47:55.88$vck44/vblo=5,709.99 2006.201.11:47:55.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.11:47:55.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.11:47:55.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:55.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:47:55.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:47:55.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:47:55.88#ibcon#enter wrdev, iclass 21, count 0 2006.201.11:47:55.88#ibcon#first serial, iclass 21, count 0 2006.201.11:47:55.88#ibcon#enter sib2, iclass 21, count 0 2006.201.11:47:55.88#ibcon#flushed, iclass 21, count 0 2006.201.11:47:55.88#ibcon#about to write, iclass 21, count 0 2006.201.11:47:55.88#ibcon#wrote, iclass 21, count 0 2006.201.11:47:55.88#ibcon#about to read 3, iclass 21, count 0 2006.201.11:47:55.90#ibcon#read 3, iclass 21, count 0 2006.201.11:47:55.90#ibcon#about to read 4, iclass 21, count 0 2006.201.11:47:55.90#ibcon#read 4, iclass 21, count 0 2006.201.11:47:55.90#ibcon#about to read 5, iclass 21, count 0 2006.201.11:47:55.90#ibcon#read 5, iclass 21, count 0 2006.201.11:47:55.90#ibcon#about to read 6, iclass 21, count 0 2006.201.11:47:55.90#ibcon#read 6, iclass 21, count 0 2006.201.11:47:55.90#ibcon#end of sib2, iclass 21, count 0 2006.201.11:47:55.90#ibcon#*mode == 0, iclass 21, count 0 2006.201.11:47:55.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.11:47:55.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:47:55.90#ibcon#*before write, iclass 21, count 0 2006.201.11:47:55.90#ibcon#enter sib2, iclass 21, count 0 2006.201.11:47:55.90#ibcon#flushed, iclass 21, count 0 2006.201.11:47:55.90#ibcon#about to write, iclass 21, count 0 2006.201.11:47:55.90#ibcon#wrote, iclass 21, count 0 2006.201.11:47:55.90#ibcon#about to read 3, iclass 21, count 0 2006.201.11:47:55.94#ibcon#read 3, iclass 21, count 0 2006.201.11:47:55.94#ibcon#about to read 4, iclass 21, count 0 2006.201.11:47:55.94#ibcon#read 4, iclass 21, count 0 2006.201.11:47:55.94#ibcon#about to read 5, iclass 21, count 0 2006.201.11:47:55.94#ibcon#read 5, iclass 21, count 0 2006.201.11:47:55.94#ibcon#about to read 6, iclass 21, count 0 2006.201.11:47:55.94#ibcon#read 6, iclass 21, count 0 2006.201.11:47:55.94#ibcon#end of sib2, iclass 21, count 0 2006.201.11:47:55.94#ibcon#*after write, iclass 21, count 0 2006.201.11:47:55.94#ibcon#*before return 0, iclass 21, count 0 2006.201.11:47:55.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:47:55.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.11:47:55.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.11:47:55.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.11:47:55.94$vck44/vb=5,4 2006.201.11:47:55.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.11:47:55.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.11:47:55.94#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:55.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:47:56.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:47:56.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:47:56.00#ibcon#enter wrdev, iclass 23, count 2 2006.201.11:47:56.00#ibcon#first serial, iclass 23, count 2 2006.201.11:47:56.00#ibcon#enter sib2, iclass 23, count 2 2006.201.11:47:56.00#ibcon#flushed, iclass 23, count 2 2006.201.11:47:56.00#ibcon#about to write, iclass 23, count 2 2006.201.11:47:56.00#ibcon#wrote, iclass 23, count 2 2006.201.11:47:56.00#ibcon#about to read 3, iclass 23, count 2 2006.201.11:47:56.02#ibcon#read 3, iclass 23, count 2 2006.201.11:47:56.02#ibcon#about to read 4, iclass 23, count 2 2006.201.11:47:56.02#ibcon#read 4, iclass 23, count 2 2006.201.11:47:56.02#ibcon#about to read 5, iclass 23, count 2 2006.201.11:47:56.02#ibcon#read 5, iclass 23, count 2 2006.201.11:47:56.02#ibcon#about to read 6, iclass 23, count 2 2006.201.11:47:56.02#ibcon#read 6, iclass 23, count 2 2006.201.11:47:56.02#ibcon#end of sib2, iclass 23, count 2 2006.201.11:47:56.02#ibcon#*mode == 0, iclass 23, count 2 2006.201.11:47:56.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.11:47:56.02#ibcon#[27=AT05-04\r\n] 2006.201.11:47:56.02#ibcon#*before write, iclass 23, count 2 2006.201.11:47:56.02#ibcon#enter sib2, iclass 23, count 2 2006.201.11:47:56.02#ibcon#flushed, iclass 23, count 2 2006.201.11:47:56.02#ibcon#about to write, iclass 23, count 2 2006.201.11:47:56.02#ibcon#wrote, iclass 23, count 2 2006.201.11:47:56.02#ibcon#about to read 3, iclass 23, count 2 2006.201.11:47:56.05#ibcon#read 3, iclass 23, count 2 2006.201.11:47:56.05#ibcon#about to read 4, iclass 23, count 2 2006.201.11:47:56.05#ibcon#read 4, iclass 23, count 2 2006.201.11:47:56.05#ibcon#about to read 5, iclass 23, count 2 2006.201.11:47:56.05#ibcon#read 5, iclass 23, count 2 2006.201.11:47:56.05#ibcon#about to read 6, iclass 23, count 2 2006.201.11:47:56.05#ibcon#read 6, iclass 23, count 2 2006.201.11:47:56.05#ibcon#end of sib2, iclass 23, count 2 2006.201.11:47:56.05#ibcon#*after write, iclass 23, count 2 2006.201.11:47:56.05#ibcon#*before return 0, iclass 23, count 2 2006.201.11:47:56.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:47:56.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.11:47:56.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.11:47:56.05#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:56.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:47:56.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:47:56.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:47:56.17#ibcon#enter wrdev, iclass 23, count 0 2006.201.11:47:56.17#ibcon#first serial, iclass 23, count 0 2006.201.11:47:56.17#ibcon#enter sib2, iclass 23, count 0 2006.201.11:47:56.17#ibcon#flushed, iclass 23, count 0 2006.201.11:47:56.17#ibcon#about to write, iclass 23, count 0 2006.201.11:47:56.17#ibcon#wrote, iclass 23, count 0 2006.201.11:47:56.17#ibcon#about to read 3, iclass 23, count 0 2006.201.11:47:56.20#ibcon#read 3, iclass 23, count 0 2006.201.11:47:56.20#ibcon#about to read 4, iclass 23, count 0 2006.201.11:47:56.20#ibcon#read 4, iclass 23, count 0 2006.201.11:47:56.20#ibcon#about to read 5, iclass 23, count 0 2006.201.11:47:56.20#ibcon#read 5, iclass 23, count 0 2006.201.11:47:56.20#ibcon#about to read 6, iclass 23, count 0 2006.201.11:47:56.20#ibcon#read 6, iclass 23, count 0 2006.201.11:47:56.20#ibcon#end of sib2, iclass 23, count 0 2006.201.11:47:56.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.11:47:56.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.11:47:56.20#ibcon#[27=USB\r\n] 2006.201.11:47:56.20#ibcon#*before write, iclass 23, count 0 2006.201.11:47:56.20#ibcon#enter sib2, iclass 23, count 0 2006.201.11:47:56.20#ibcon#flushed, iclass 23, count 0 2006.201.11:47:56.20#ibcon#about to write, iclass 23, count 0 2006.201.11:47:56.20#ibcon#wrote, iclass 23, count 0 2006.201.11:47:56.20#ibcon#about to read 3, iclass 23, count 0 2006.201.11:47:56.23#ibcon#read 3, iclass 23, count 0 2006.201.11:47:56.23#ibcon#about to read 4, iclass 23, count 0 2006.201.11:47:56.23#ibcon#read 4, iclass 23, count 0 2006.201.11:47:56.23#ibcon#about to read 5, iclass 23, count 0 2006.201.11:47:56.23#ibcon#read 5, iclass 23, count 0 2006.201.11:47:56.23#ibcon#about to read 6, iclass 23, count 0 2006.201.11:47:56.23#ibcon#read 6, iclass 23, count 0 2006.201.11:47:56.23#ibcon#end of sib2, iclass 23, count 0 2006.201.11:47:56.23#ibcon#*after write, iclass 23, count 0 2006.201.11:47:56.23#ibcon#*before return 0, iclass 23, count 0 2006.201.11:47:56.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:47:56.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.11:47:56.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.11:47:56.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.11:47:56.23$vck44/vblo=6,719.99 2006.201.11:47:56.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.11:47:56.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.11:47:56.23#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:56.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:47:56.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:47:56.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:47:56.23#ibcon#enter wrdev, iclass 25, count 0 2006.201.11:47:56.23#ibcon#first serial, iclass 25, count 0 2006.201.11:47:56.23#ibcon#enter sib2, iclass 25, count 0 2006.201.11:47:56.23#ibcon#flushed, iclass 25, count 0 2006.201.11:47:56.23#ibcon#about to write, iclass 25, count 0 2006.201.11:47:56.23#ibcon#wrote, iclass 25, count 0 2006.201.11:47:56.23#ibcon#about to read 3, iclass 25, count 0 2006.201.11:47:56.25#ibcon#read 3, iclass 25, count 0 2006.201.11:47:56.25#ibcon#about to read 4, iclass 25, count 0 2006.201.11:47:56.25#ibcon#read 4, iclass 25, count 0 2006.201.11:47:56.25#ibcon#about to read 5, iclass 25, count 0 2006.201.11:47:56.25#ibcon#read 5, iclass 25, count 0 2006.201.11:47:56.25#ibcon#about to read 6, iclass 25, count 0 2006.201.11:47:56.25#ibcon#read 6, iclass 25, count 0 2006.201.11:47:56.25#ibcon#end of sib2, iclass 25, count 0 2006.201.11:47:56.25#ibcon#*mode == 0, iclass 25, count 0 2006.201.11:47:56.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.11:47:56.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:47:56.25#ibcon#*before write, iclass 25, count 0 2006.201.11:47:56.25#ibcon#enter sib2, iclass 25, count 0 2006.201.11:47:56.25#ibcon#flushed, iclass 25, count 0 2006.201.11:47:56.25#ibcon#about to write, iclass 25, count 0 2006.201.11:47:56.25#ibcon#wrote, iclass 25, count 0 2006.201.11:47:56.25#ibcon#about to read 3, iclass 25, count 0 2006.201.11:47:56.29#ibcon#read 3, iclass 25, count 0 2006.201.11:47:56.29#ibcon#about to read 4, iclass 25, count 0 2006.201.11:47:56.29#ibcon#read 4, iclass 25, count 0 2006.201.11:47:56.29#ibcon#about to read 5, iclass 25, count 0 2006.201.11:47:56.29#ibcon#read 5, iclass 25, count 0 2006.201.11:47:56.29#ibcon#about to read 6, iclass 25, count 0 2006.201.11:47:56.29#ibcon#read 6, iclass 25, count 0 2006.201.11:47:56.29#ibcon#end of sib2, iclass 25, count 0 2006.201.11:47:56.29#ibcon#*after write, iclass 25, count 0 2006.201.11:47:56.29#ibcon#*before return 0, iclass 25, count 0 2006.201.11:47:56.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:47:56.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.11:47:56.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.11:47:56.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.11:47:56.29$vck44/vb=6,4 2006.201.11:47:56.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.11:47:56.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.11:47:56.29#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:56.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:56.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:56.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:56.35#ibcon#enter wrdev, iclass 27, count 2 2006.201.11:47:56.35#ibcon#first serial, iclass 27, count 2 2006.201.11:47:56.35#ibcon#enter sib2, iclass 27, count 2 2006.201.11:47:56.35#ibcon#flushed, iclass 27, count 2 2006.201.11:47:56.35#ibcon#about to write, iclass 27, count 2 2006.201.11:47:56.35#ibcon#wrote, iclass 27, count 2 2006.201.11:47:56.35#ibcon#about to read 3, iclass 27, count 2 2006.201.11:47:56.37#ibcon#read 3, iclass 27, count 2 2006.201.11:47:56.37#ibcon#about to read 4, iclass 27, count 2 2006.201.11:47:56.37#ibcon#read 4, iclass 27, count 2 2006.201.11:47:56.37#ibcon#about to read 5, iclass 27, count 2 2006.201.11:47:56.37#ibcon#read 5, iclass 27, count 2 2006.201.11:47:56.37#ibcon#about to read 6, iclass 27, count 2 2006.201.11:47:56.37#ibcon#read 6, iclass 27, count 2 2006.201.11:47:56.37#ibcon#end of sib2, iclass 27, count 2 2006.201.11:47:56.37#ibcon#*mode == 0, iclass 27, count 2 2006.201.11:47:56.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.11:47:56.37#ibcon#[27=AT06-04\r\n] 2006.201.11:47:56.37#ibcon#*before write, iclass 27, count 2 2006.201.11:47:56.37#ibcon#enter sib2, iclass 27, count 2 2006.201.11:47:56.37#ibcon#flushed, iclass 27, count 2 2006.201.11:47:56.37#ibcon#about to write, iclass 27, count 2 2006.201.11:47:56.37#ibcon#wrote, iclass 27, count 2 2006.201.11:47:56.37#ibcon#about to read 3, iclass 27, count 2 2006.201.11:47:56.40#ibcon#read 3, iclass 27, count 2 2006.201.11:47:56.40#ibcon#about to read 4, iclass 27, count 2 2006.201.11:47:56.40#ibcon#read 4, iclass 27, count 2 2006.201.11:47:56.40#ibcon#about to read 5, iclass 27, count 2 2006.201.11:47:56.40#ibcon#read 5, iclass 27, count 2 2006.201.11:47:56.40#ibcon#about to read 6, iclass 27, count 2 2006.201.11:47:56.40#ibcon#read 6, iclass 27, count 2 2006.201.11:47:56.40#ibcon#end of sib2, iclass 27, count 2 2006.201.11:47:56.40#ibcon#*after write, iclass 27, count 2 2006.201.11:47:56.40#ibcon#*before return 0, iclass 27, count 2 2006.201.11:47:56.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:56.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.11:47:56.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.11:47:56.40#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:56.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:56.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:56.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:56.52#ibcon#enter wrdev, iclass 27, count 0 2006.201.11:47:56.52#ibcon#first serial, iclass 27, count 0 2006.201.11:47:56.52#ibcon#enter sib2, iclass 27, count 0 2006.201.11:47:56.52#ibcon#flushed, iclass 27, count 0 2006.201.11:47:56.52#ibcon#about to write, iclass 27, count 0 2006.201.11:47:56.52#ibcon#wrote, iclass 27, count 0 2006.201.11:47:56.52#ibcon#about to read 3, iclass 27, count 0 2006.201.11:47:56.54#ibcon#read 3, iclass 27, count 0 2006.201.11:47:56.54#ibcon#about to read 4, iclass 27, count 0 2006.201.11:47:56.54#ibcon#read 4, iclass 27, count 0 2006.201.11:47:56.54#ibcon#about to read 5, iclass 27, count 0 2006.201.11:47:56.54#ibcon#read 5, iclass 27, count 0 2006.201.11:47:56.54#ibcon#about to read 6, iclass 27, count 0 2006.201.11:47:56.54#ibcon#read 6, iclass 27, count 0 2006.201.11:47:56.54#ibcon#end of sib2, iclass 27, count 0 2006.201.11:47:56.54#ibcon#*mode == 0, iclass 27, count 0 2006.201.11:47:56.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.11:47:56.54#ibcon#[27=USB\r\n] 2006.201.11:47:56.54#ibcon#*before write, iclass 27, count 0 2006.201.11:47:56.54#ibcon#enter sib2, iclass 27, count 0 2006.201.11:47:56.54#ibcon#flushed, iclass 27, count 0 2006.201.11:47:56.54#ibcon#about to write, iclass 27, count 0 2006.201.11:47:56.54#ibcon#wrote, iclass 27, count 0 2006.201.11:47:56.54#ibcon#about to read 3, iclass 27, count 0 2006.201.11:47:56.57#ibcon#read 3, iclass 27, count 0 2006.201.11:47:56.57#ibcon#about to read 4, iclass 27, count 0 2006.201.11:47:56.57#ibcon#read 4, iclass 27, count 0 2006.201.11:47:56.57#ibcon#about to read 5, iclass 27, count 0 2006.201.11:47:56.57#ibcon#read 5, iclass 27, count 0 2006.201.11:47:56.57#ibcon#about to read 6, iclass 27, count 0 2006.201.11:47:56.57#ibcon#read 6, iclass 27, count 0 2006.201.11:47:56.57#ibcon#end of sib2, iclass 27, count 0 2006.201.11:47:56.57#ibcon#*after write, iclass 27, count 0 2006.201.11:47:56.57#ibcon#*before return 0, iclass 27, count 0 2006.201.11:47:56.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:56.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.11:47:56.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.11:47:56.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.11:47:56.57$vck44/vblo=7,734.99 2006.201.11:47:56.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.11:47:56.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.11:47:56.57#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:56.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:56.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:56.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:56.57#ibcon#enter wrdev, iclass 29, count 0 2006.201.11:47:56.57#ibcon#first serial, iclass 29, count 0 2006.201.11:47:56.57#ibcon#enter sib2, iclass 29, count 0 2006.201.11:47:56.57#ibcon#flushed, iclass 29, count 0 2006.201.11:47:56.57#ibcon#about to write, iclass 29, count 0 2006.201.11:47:56.57#ibcon#wrote, iclass 29, count 0 2006.201.11:47:56.57#ibcon#about to read 3, iclass 29, count 0 2006.201.11:47:56.59#ibcon#read 3, iclass 29, count 0 2006.201.11:47:56.59#ibcon#about to read 4, iclass 29, count 0 2006.201.11:47:56.59#ibcon#read 4, iclass 29, count 0 2006.201.11:47:56.59#ibcon#about to read 5, iclass 29, count 0 2006.201.11:47:56.59#ibcon#read 5, iclass 29, count 0 2006.201.11:47:56.59#ibcon#about to read 6, iclass 29, count 0 2006.201.11:47:56.59#ibcon#read 6, iclass 29, count 0 2006.201.11:47:56.59#ibcon#end of sib2, iclass 29, count 0 2006.201.11:47:56.59#ibcon#*mode == 0, iclass 29, count 0 2006.201.11:47:56.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.11:47:56.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:47:56.59#ibcon#*before write, iclass 29, count 0 2006.201.11:47:56.59#ibcon#enter sib2, iclass 29, count 0 2006.201.11:47:56.59#ibcon#flushed, iclass 29, count 0 2006.201.11:47:56.59#ibcon#about to write, iclass 29, count 0 2006.201.11:47:56.59#ibcon#wrote, iclass 29, count 0 2006.201.11:47:56.59#ibcon#about to read 3, iclass 29, count 0 2006.201.11:47:56.63#ibcon#read 3, iclass 29, count 0 2006.201.11:47:56.63#ibcon#about to read 4, iclass 29, count 0 2006.201.11:47:56.63#ibcon#read 4, iclass 29, count 0 2006.201.11:47:56.63#ibcon#about to read 5, iclass 29, count 0 2006.201.11:47:56.63#ibcon#read 5, iclass 29, count 0 2006.201.11:47:56.63#ibcon#about to read 6, iclass 29, count 0 2006.201.11:47:56.63#ibcon#read 6, iclass 29, count 0 2006.201.11:47:56.63#ibcon#end of sib2, iclass 29, count 0 2006.201.11:47:56.63#ibcon#*after write, iclass 29, count 0 2006.201.11:47:56.63#ibcon#*before return 0, iclass 29, count 0 2006.201.11:47:56.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:56.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.11:47:56.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.11:47:56.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.11:47:56.63$vck44/vb=7,4 2006.201.11:47:56.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.11:47:56.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.11:47:56.63#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:56.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:56.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:56.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:56.69#ibcon#enter wrdev, iclass 31, count 2 2006.201.11:47:56.69#ibcon#first serial, iclass 31, count 2 2006.201.11:47:56.69#ibcon#enter sib2, iclass 31, count 2 2006.201.11:47:56.69#ibcon#flushed, iclass 31, count 2 2006.201.11:47:56.69#ibcon#about to write, iclass 31, count 2 2006.201.11:47:56.69#ibcon#wrote, iclass 31, count 2 2006.201.11:47:56.69#ibcon#about to read 3, iclass 31, count 2 2006.201.11:47:56.71#ibcon#read 3, iclass 31, count 2 2006.201.11:47:56.71#ibcon#about to read 4, iclass 31, count 2 2006.201.11:47:56.71#ibcon#read 4, iclass 31, count 2 2006.201.11:47:56.71#ibcon#about to read 5, iclass 31, count 2 2006.201.11:47:56.71#ibcon#read 5, iclass 31, count 2 2006.201.11:47:56.71#ibcon#about to read 6, iclass 31, count 2 2006.201.11:47:56.71#ibcon#read 6, iclass 31, count 2 2006.201.11:47:56.71#ibcon#end of sib2, iclass 31, count 2 2006.201.11:47:56.71#ibcon#*mode == 0, iclass 31, count 2 2006.201.11:47:56.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.11:47:56.71#ibcon#[27=AT07-04\r\n] 2006.201.11:47:56.71#ibcon#*before write, iclass 31, count 2 2006.201.11:47:56.71#ibcon#enter sib2, iclass 31, count 2 2006.201.11:47:56.71#ibcon#flushed, iclass 31, count 2 2006.201.11:47:56.71#ibcon#about to write, iclass 31, count 2 2006.201.11:47:56.71#ibcon#wrote, iclass 31, count 2 2006.201.11:47:56.71#ibcon#about to read 3, iclass 31, count 2 2006.201.11:47:56.74#ibcon#read 3, iclass 31, count 2 2006.201.11:47:56.74#ibcon#about to read 4, iclass 31, count 2 2006.201.11:47:56.74#ibcon#read 4, iclass 31, count 2 2006.201.11:47:56.74#ibcon#about to read 5, iclass 31, count 2 2006.201.11:47:56.74#ibcon#read 5, iclass 31, count 2 2006.201.11:47:56.74#ibcon#about to read 6, iclass 31, count 2 2006.201.11:47:56.74#ibcon#read 6, iclass 31, count 2 2006.201.11:47:56.74#ibcon#end of sib2, iclass 31, count 2 2006.201.11:47:56.74#ibcon#*after write, iclass 31, count 2 2006.201.11:47:56.74#ibcon#*before return 0, iclass 31, count 2 2006.201.11:47:56.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:56.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.11:47:56.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.11:47:56.74#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:56.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:56.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:56.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:56.86#ibcon#enter wrdev, iclass 31, count 0 2006.201.11:47:56.86#ibcon#first serial, iclass 31, count 0 2006.201.11:47:56.86#ibcon#enter sib2, iclass 31, count 0 2006.201.11:47:56.86#ibcon#flushed, iclass 31, count 0 2006.201.11:47:56.86#ibcon#about to write, iclass 31, count 0 2006.201.11:47:56.86#ibcon#wrote, iclass 31, count 0 2006.201.11:47:56.86#ibcon#about to read 3, iclass 31, count 0 2006.201.11:47:56.88#ibcon#read 3, iclass 31, count 0 2006.201.11:47:56.88#ibcon#about to read 4, iclass 31, count 0 2006.201.11:47:56.88#ibcon#read 4, iclass 31, count 0 2006.201.11:47:56.88#ibcon#about to read 5, iclass 31, count 0 2006.201.11:47:56.88#ibcon#read 5, iclass 31, count 0 2006.201.11:47:56.88#ibcon#about to read 6, iclass 31, count 0 2006.201.11:47:56.88#ibcon#read 6, iclass 31, count 0 2006.201.11:47:56.88#ibcon#end of sib2, iclass 31, count 0 2006.201.11:47:56.88#ibcon#*mode == 0, iclass 31, count 0 2006.201.11:47:56.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.11:47:56.88#ibcon#[27=USB\r\n] 2006.201.11:47:56.88#ibcon#*before write, iclass 31, count 0 2006.201.11:47:56.88#ibcon#enter sib2, iclass 31, count 0 2006.201.11:47:56.88#ibcon#flushed, iclass 31, count 0 2006.201.11:47:56.88#ibcon#about to write, iclass 31, count 0 2006.201.11:47:56.88#ibcon#wrote, iclass 31, count 0 2006.201.11:47:56.88#ibcon#about to read 3, iclass 31, count 0 2006.201.11:47:56.91#ibcon#read 3, iclass 31, count 0 2006.201.11:47:56.91#ibcon#about to read 4, iclass 31, count 0 2006.201.11:47:56.91#ibcon#read 4, iclass 31, count 0 2006.201.11:47:56.91#ibcon#about to read 5, iclass 31, count 0 2006.201.11:47:56.91#ibcon#read 5, iclass 31, count 0 2006.201.11:47:56.91#ibcon#about to read 6, iclass 31, count 0 2006.201.11:47:56.91#ibcon#read 6, iclass 31, count 0 2006.201.11:47:56.91#ibcon#end of sib2, iclass 31, count 0 2006.201.11:47:56.91#ibcon#*after write, iclass 31, count 0 2006.201.11:47:56.91#ibcon#*before return 0, iclass 31, count 0 2006.201.11:47:56.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:56.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.11:47:56.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.11:47:56.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.11:47:56.91$vck44/vblo=8,744.99 2006.201.11:47:56.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.11:47:56.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.11:47:56.91#ibcon#ireg 17 cls_cnt 0 2006.201.11:47:56.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:56.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:56.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:56.91#ibcon#enter wrdev, iclass 33, count 0 2006.201.11:47:56.91#ibcon#first serial, iclass 33, count 0 2006.201.11:47:56.91#ibcon#enter sib2, iclass 33, count 0 2006.201.11:47:56.91#ibcon#flushed, iclass 33, count 0 2006.201.11:47:56.91#ibcon#about to write, iclass 33, count 0 2006.201.11:47:56.91#ibcon#wrote, iclass 33, count 0 2006.201.11:47:56.91#ibcon#about to read 3, iclass 33, count 0 2006.201.11:47:56.93#ibcon#read 3, iclass 33, count 0 2006.201.11:47:56.93#ibcon#about to read 4, iclass 33, count 0 2006.201.11:47:56.93#ibcon#read 4, iclass 33, count 0 2006.201.11:47:56.93#ibcon#about to read 5, iclass 33, count 0 2006.201.11:47:56.93#ibcon#read 5, iclass 33, count 0 2006.201.11:47:56.93#ibcon#about to read 6, iclass 33, count 0 2006.201.11:47:56.93#ibcon#read 6, iclass 33, count 0 2006.201.11:47:56.93#ibcon#end of sib2, iclass 33, count 0 2006.201.11:47:56.93#ibcon#*mode == 0, iclass 33, count 0 2006.201.11:47:56.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.11:47:56.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:47:56.93#ibcon#*before write, iclass 33, count 0 2006.201.11:47:56.93#ibcon#enter sib2, iclass 33, count 0 2006.201.11:47:56.93#ibcon#flushed, iclass 33, count 0 2006.201.11:47:56.93#ibcon#about to write, iclass 33, count 0 2006.201.11:47:56.93#ibcon#wrote, iclass 33, count 0 2006.201.11:47:56.93#ibcon#about to read 3, iclass 33, count 0 2006.201.11:47:56.97#ibcon#read 3, iclass 33, count 0 2006.201.11:47:56.97#ibcon#about to read 4, iclass 33, count 0 2006.201.11:47:56.97#ibcon#read 4, iclass 33, count 0 2006.201.11:47:56.97#ibcon#about to read 5, iclass 33, count 0 2006.201.11:47:56.97#ibcon#read 5, iclass 33, count 0 2006.201.11:47:56.97#ibcon#about to read 6, iclass 33, count 0 2006.201.11:47:56.97#ibcon#read 6, iclass 33, count 0 2006.201.11:47:56.97#ibcon#end of sib2, iclass 33, count 0 2006.201.11:47:56.97#ibcon#*after write, iclass 33, count 0 2006.201.11:47:56.97#ibcon#*before return 0, iclass 33, count 0 2006.201.11:47:56.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:56.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.11:47:56.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.11:47:56.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.11:47:56.97$vck44/vb=8,4 2006.201.11:47:56.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.11:47:56.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.11:47:56.97#ibcon#ireg 11 cls_cnt 2 2006.201.11:47:56.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:57.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:57.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:57.03#ibcon#enter wrdev, iclass 35, count 2 2006.201.11:47:57.03#ibcon#first serial, iclass 35, count 2 2006.201.11:47:57.03#ibcon#enter sib2, iclass 35, count 2 2006.201.11:47:57.03#ibcon#flushed, iclass 35, count 2 2006.201.11:47:57.03#ibcon#about to write, iclass 35, count 2 2006.201.11:47:57.03#ibcon#wrote, iclass 35, count 2 2006.201.11:47:57.03#ibcon#about to read 3, iclass 35, count 2 2006.201.11:47:57.05#ibcon#read 3, iclass 35, count 2 2006.201.11:47:57.05#ibcon#about to read 4, iclass 35, count 2 2006.201.11:47:57.05#ibcon#read 4, iclass 35, count 2 2006.201.11:47:57.05#ibcon#about to read 5, iclass 35, count 2 2006.201.11:47:57.05#ibcon#read 5, iclass 35, count 2 2006.201.11:47:57.05#ibcon#about to read 6, iclass 35, count 2 2006.201.11:47:57.05#ibcon#read 6, iclass 35, count 2 2006.201.11:47:57.05#ibcon#end of sib2, iclass 35, count 2 2006.201.11:47:57.05#ibcon#*mode == 0, iclass 35, count 2 2006.201.11:47:57.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.11:47:57.05#ibcon#[27=AT08-04\r\n] 2006.201.11:47:57.05#ibcon#*before write, iclass 35, count 2 2006.201.11:47:57.05#ibcon#enter sib2, iclass 35, count 2 2006.201.11:47:57.05#ibcon#flushed, iclass 35, count 2 2006.201.11:47:57.05#ibcon#about to write, iclass 35, count 2 2006.201.11:47:57.05#ibcon#wrote, iclass 35, count 2 2006.201.11:47:57.05#ibcon#about to read 3, iclass 35, count 2 2006.201.11:47:57.08#ibcon#read 3, iclass 35, count 2 2006.201.11:47:57.08#ibcon#about to read 4, iclass 35, count 2 2006.201.11:47:57.08#ibcon#read 4, iclass 35, count 2 2006.201.11:47:57.08#ibcon#about to read 5, iclass 35, count 2 2006.201.11:47:57.08#ibcon#read 5, iclass 35, count 2 2006.201.11:47:57.08#ibcon#about to read 6, iclass 35, count 2 2006.201.11:47:57.08#ibcon#read 6, iclass 35, count 2 2006.201.11:47:57.08#ibcon#end of sib2, iclass 35, count 2 2006.201.11:47:57.08#ibcon#*after write, iclass 35, count 2 2006.201.11:47:57.08#ibcon#*before return 0, iclass 35, count 2 2006.201.11:47:57.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:57.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.11:47:57.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.11:47:57.08#ibcon#ireg 7 cls_cnt 0 2006.201.11:47:57.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:57.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:57.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:57.20#ibcon#enter wrdev, iclass 35, count 0 2006.201.11:47:57.20#ibcon#first serial, iclass 35, count 0 2006.201.11:47:57.20#ibcon#enter sib2, iclass 35, count 0 2006.201.11:47:57.20#ibcon#flushed, iclass 35, count 0 2006.201.11:47:57.20#ibcon#about to write, iclass 35, count 0 2006.201.11:47:57.20#ibcon#wrote, iclass 35, count 0 2006.201.11:47:57.20#ibcon#about to read 3, iclass 35, count 0 2006.201.11:47:57.23#ibcon#read 3, iclass 35, count 0 2006.201.11:47:57.23#ibcon#about to read 4, iclass 35, count 0 2006.201.11:47:57.23#ibcon#read 4, iclass 35, count 0 2006.201.11:47:57.23#ibcon#about to read 5, iclass 35, count 0 2006.201.11:47:57.23#ibcon#read 5, iclass 35, count 0 2006.201.11:47:57.23#ibcon#about to read 6, iclass 35, count 0 2006.201.11:47:57.23#ibcon#read 6, iclass 35, count 0 2006.201.11:47:57.23#ibcon#end of sib2, iclass 35, count 0 2006.201.11:47:57.23#ibcon#*mode == 0, iclass 35, count 0 2006.201.11:47:57.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.11:47:57.23#ibcon#[27=USB\r\n] 2006.201.11:47:57.23#ibcon#*before write, iclass 35, count 0 2006.201.11:47:57.23#ibcon#enter sib2, iclass 35, count 0 2006.201.11:47:57.23#ibcon#flushed, iclass 35, count 0 2006.201.11:47:57.23#ibcon#about to write, iclass 35, count 0 2006.201.11:47:57.23#ibcon#wrote, iclass 35, count 0 2006.201.11:47:57.23#ibcon#about to read 3, iclass 35, count 0 2006.201.11:47:57.26#ibcon#read 3, iclass 35, count 0 2006.201.11:47:57.26#ibcon#about to read 4, iclass 35, count 0 2006.201.11:47:57.26#ibcon#read 4, iclass 35, count 0 2006.201.11:47:57.26#ibcon#about to read 5, iclass 35, count 0 2006.201.11:47:57.26#ibcon#read 5, iclass 35, count 0 2006.201.11:47:57.26#ibcon#about to read 6, iclass 35, count 0 2006.201.11:47:57.26#ibcon#read 6, iclass 35, count 0 2006.201.11:47:57.26#ibcon#end of sib2, iclass 35, count 0 2006.201.11:47:57.26#ibcon#*after write, iclass 35, count 0 2006.201.11:47:57.26#ibcon#*before return 0, iclass 35, count 0 2006.201.11:47:57.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:57.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.11:47:57.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.11:47:57.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.11:47:57.26$vck44/vabw=wide 2006.201.11:47:57.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.11:47:57.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.11:47:57.26#ibcon#ireg 8 cls_cnt 0 2006.201.11:47:57.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:57.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:57.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:57.26#ibcon#enter wrdev, iclass 37, count 0 2006.201.11:47:57.26#ibcon#first serial, iclass 37, count 0 2006.201.11:47:57.26#ibcon#enter sib2, iclass 37, count 0 2006.201.11:47:57.26#ibcon#flushed, iclass 37, count 0 2006.201.11:47:57.26#ibcon#about to write, iclass 37, count 0 2006.201.11:47:57.26#ibcon#wrote, iclass 37, count 0 2006.201.11:47:57.26#ibcon#about to read 3, iclass 37, count 0 2006.201.11:47:57.28#ibcon#read 3, iclass 37, count 0 2006.201.11:47:57.28#ibcon#about to read 4, iclass 37, count 0 2006.201.11:47:57.28#ibcon#read 4, iclass 37, count 0 2006.201.11:47:57.28#ibcon#about to read 5, iclass 37, count 0 2006.201.11:47:57.28#ibcon#read 5, iclass 37, count 0 2006.201.11:47:57.28#ibcon#about to read 6, iclass 37, count 0 2006.201.11:47:57.28#ibcon#read 6, iclass 37, count 0 2006.201.11:47:57.28#ibcon#end of sib2, iclass 37, count 0 2006.201.11:47:57.28#ibcon#*mode == 0, iclass 37, count 0 2006.201.11:47:57.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.11:47:57.28#ibcon#[25=BW32\r\n] 2006.201.11:47:57.28#ibcon#*before write, iclass 37, count 0 2006.201.11:47:57.28#ibcon#enter sib2, iclass 37, count 0 2006.201.11:47:57.28#ibcon#flushed, iclass 37, count 0 2006.201.11:47:57.28#ibcon#about to write, iclass 37, count 0 2006.201.11:47:57.28#ibcon#wrote, iclass 37, count 0 2006.201.11:47:57.28#ibcon#about to read 3, iclass 37, count 0 2006.201.11:47:57.31#ibcon#read 3, iclass 37, count 0 2006.201.11:47:57.31#ibcon#about to read 4, iclass 37, count 0 2006.201.11:47:57.31#ibcon#read 4, iclass 37, count 0 2006.201.11:47:57.31#ibcon#about to read 5, iclass 37, count 0 2006.201.11:47:57.31#ibcon#read 5, iclass 37, count 0 2006.201.11:47:57.31#ibcon#about to read 6, iclass 37, count 0 2006.201.11:47:57.31#ibcon#read 6, iclass 37, count 0 2006.201.11:47:57.31#ibcon#end of sib2, iclass 37, count 0 2006.201.11:47:57.31#ibcon#*after write, iclass 37, count 0 2006.201.11:47:57.31#ibcon#*before return 0, iclass 37, count 0 2006.201.11:47:57.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:57.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.11:47:57.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.11:47:57.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.11:47:57.31$vck44/vbbw=wide 2006.201.11:47:57.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.11:47:57.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.11:47:57.31#ibcon#ireg 8 cls_cnt 0 2006.201.11:47:57.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:47:57.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:47:57.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:47:57.38#ibcon#enter wrdev, iclass 39, count 0 2006.201.11:47:57.38#ibcon#first serial, iclass 39, count 0 2006.201.11:47:57.38#ibcon#enter sib2, iclass 39, count 0 2006.201.11:47:57.38#ibcon#flushed, iclass 39, count 0 2006.201.11:47:57.38#ibcon#about to write, iclass 39, count 0 2006.201.11:47:57.38#ibcon#wrote, iclass 39, count 0 2006.201.11:47:57.38#ibcon#about to read 3, iclass 39, count 0 2006.201.11:47:57.40#ibcon#read 3, iclass 39, count 0 2006.201.11:47:57.40#ibcon#about to read 4, iclass 39, count 0 2006.201.11:47:57.40#ibcon#read 4, iclass 39, count 0 2006.201.11:47:57.40#ibcon#about to read 5, iclass 39, count 0 2006.201.11:47:57.40#ibcon#read 5, iclass 39, count 0 2006.201.11:47:57.40#ibcon#about to read 6, iclass 39, count 0 2006.201.11:47:57.40#ibcon#read 6, iclass 39, count 0 2006.201.11:47:57.40#ibcon#end of sib2, iclass 39, count 0 2006.201.11:47:57.40#ibcon#*mode == 0, iclass 39, count 0 2006.201.11:47:57.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.11:47:57.40#ibcon#[27=BW32\r\n] 2006.201.11:47:57.40#ibcon#*before write, iclass 39, count 0 2006.201.11:47:57.40#ibcon#enter sib2, iclass 39, count 0 2006.201.11:47:57.40#ibcon#flushed, iclass 39, count 0 2006.201.11:47:57.40#ibcon#about to write, iclass 39, count 0 2006.201.11:47:57.40#ibcon#wrote, iclass 39, count 0 2006.201.11:47:57.40#ibcon#about to read 3, iclass 39, count 0 2006.201.11:47:57.43#ibcon#read 3, iclass 39, count 0 2006.201.11:47:57.43#ibcon#about to read 4, iclass 39, count 0 2006.201.11:47:57.43#ibcon#read 4, iclass 39, count 0 2006.201.11:47:57.43#ibcon#about to read 5, iclass 39, count 0 2006.201.11:47:57.43#ibcon#read 5, iclass 39, count 0 2006.201.11:47:57.43#ibcon#about to read 6, iclass 39, count 0 2006.201.11:47:57.43#ibcon#read 6, iclass 39, count 0 2006.201.11:47:57.43#ibcon#end of sib2, iclass 39, count 0 2006.201.11:47:57.43#ibcon#*after write, iclass 39, count 0 2006.201.11:47:57.43#ibcon#*before return 0, iclass 39, count 0 2006.201.11:47:57.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:47:57.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.11:47:57.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.11:47:57.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.11:47:57.43$setupk4/ifdk4 2006.201.11:47:57.43$ifdk4/lo= 2006.201.11:47:57.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:47:57.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:47:57.43$ifdk4/patch= 2006.201.11:47:57.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:47:57.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:47:57.43$setupk4/!*+20s 2006.201.11:48:03.36#abcon#<5=/04 1.7 3.2 21.361001004.0\r\n> 2006.201.11:48:03.38#abcon#{5=INTERFACE CLEAR} 2006.201.11:48:03.44#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:48:04.14#trakl#Source acquired 2006.201.11:48:05.14#flagr#flagr/antenna,acquired 2006.201.11:48:11.89$setupk4/"tpicd 2006.201.11:48:11.89$setupk4/echo=off 2006.201.11:48:11.89$setupk4/xlog=off 2006.201.11:48:11.89:!2006.201.11:48:18 2006.201.11:48:18.00:preob 2006.201.11:48:18.14/onsource/TRACKING 2006.201.11:48:18.14:!2006.201.11:48:28 2006.201.11:48:28.00:"tape 2006.201.11:48:28.00:"st=record 2006.201.11:48:28.00:data_valid=on 2006.201.11:48:28.00:midob 2006.201.11:48:29.14/onsource/TRACKING 2006.201.11:48:29.14/wx/21.36,1004.0,100 2006.201.11:48:29.31/cable/+6.4719E-03 2006.201.11:48:30.40/va/01,08,usb,yes,29,31 2006.201.11:48:30.40/va/02,07,usb,yes,31,32 2006.201.11:48:30.40/va/03,08,usb,yes,28,29 2006.201.11:48:30.40/va/04,07,usb,yes,32,34 2006.201.11:48:30.40/va/05,04,usb,yes,28,29 2006.201.11:48:30.40/va/06,05,usb,yes,28,28 2006.201.11:48:30.40/va/07,05,usb,yes,28,29 2006.201.11:48:30.40/va/08,04,usb,yes,27,33 2006.201.11:48:30.63/valo/01,524.99,yes,locked 2006.201.11:48:30.63/valo/02,534.99,yes,locked 2006.201.11:48:30.63/valo/03,564.99,yes,locked 2006.201.11:48:30.63/valo/04,624.99,yes,locked 2006.201.11:48:30.63/valo/05,734.99,yes,locked 2006.201.11:48:30.63/valo/06,814.99,yes,locked 2006.201.11:48:30.63/valo/07,864.99,yes,locked 2006.201.11:48:30.63/valo/08,884.99,yes,locked 2006.201.11:48:31.72/vb/01,04,usb,yes,29,27 2006.201.11:48:31.72/vb/02,05,usb,yes,27,27 2006.201.11:48:31.72/vb/03,04,usb,yes,28,31 2006.201.11:48:31.72/vb/04,05,usb,yes,29,28 2006.201.11:48:31.72/vb/05,04,usb,yes,25,28 2006.201.11:48:31.72/vb/06,04,usb,yes,30,26 2006.201.11:48:31.72/vb/07,04,usb,yes,29,29 2006.201.11:48:31.72/vb/08,04,usb,yes,27,30 2006.201.11:48:31.95/vblo/01,629.99,yes,locked 2006.201.11:48:31.95/vblo/02,634.99,yes,locked 2006.201.11:48:31.95/vblo/03,649.99,yes,locked 2006.201.11:48:31.95/vblo/04,679.99,yes,locked 2006.201.11:48:31.95/vblo/05,709.99,yes,locked 2006.201.11:48:31.95/vblo/06,719.99,yes,locked 2006.201.11:48:31.95/vblo/07,734.99,yes,locked 2006.201.11:48:31.95/vblo/08,744.99,yes,locked 2006.201.11:48:32.10/vabw/8 2006.201.11:48:32.25/vbbw/8 2006.201.11:48:32.34/xfe/off,on,15.2 2006.201.11:48:32.72/ifatt/23,28,28,28 2006.201.11:48:33.05/fmout-gps/S +4.54E-07 2006.201.11:48:33.12:!2006.201.11:50:58 2006.201.11:50:58.00:data_valid=off 2006.201.11:50:58.00:"et 2006.201.11:50:58.00:!+3s 2006.201.11:51:01.02:"tape 2006.201.11:51:01.02:postob 2006.201.11:51:01.19/cable/+6.4696E-03 2006.201.11:51:01.19/wx/21.35,1003.9,100 2006.201.11:51:01.27/fmout-gps/S +4.55E-07 2006.201.11:51:01.27:scan_name=201-1159,jd0607,260 2006.201.11:51:01.27:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.201.11:51:02.14#flagr#flagr/antenna,new-source 2006.201.11:51:02.14:checkk5 2006.201.11:51:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.11:51:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.11:51:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.11:51:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.11:51:04.02/chk_obsdata//k5ts1/T2011148??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.201.11:51:04.38/chk_obsdata//k5ts2/T2011148??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.201.11:51:04.74/chk_obsdata//k5ts3/T2011148??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.201.11:51:05.11/chk_obsdata//k5ts4/T2011148??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.201.11:51:05.80/k5log//k5ts1_log_newline 2006.201.11:51:06.48/k5log//k5ts2_log_newline 2006.201.11:51:07.16/k5log//k5ts3_log_newline 2006.201.11:51:07.85/k5log//k5ts4_log_newline 2006.201.11:51:07.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.11:51:07.87:setupk4=1 2006.201.11:51:07.88$setupk4/echo=on 2006.201.11:51:07.88$setupk4/pcalon 2006.201.11:51:07.88$pcalon/"no phase cal control is implemented here 2006.201.11:51:07.88$setupk4/"tpicd=stop 2006.201.11:51:07.88$setupk4/"rec=synch_on 2006.201.11:51:07.88$setupk4/"rec_mode=128 2006.201.11:51:07.88$setupk4/!* 2006.201.11:51:07.88$setupk4/recpk4 2006.201.11:51:07.88$recpk4/recpatch= 2006.201.11:51:07.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.11:51:07.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.11:51:07.88$setupk4/vck44 2006.201.11:51:07.88$vck44/valo=1,524.99 2006.201.11:51:07.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.11:51:07.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.11:51:07.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:07.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:07.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:07.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:07.88#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:51:07.88#ibcon#first serial, iclass 12, count 0 2006.201.11:51:07.88#ibcon#enter sib2, iclass 12, count 0 2006.201.11:51:07.88#ibcon#flushed, iclass 12, count 0 2006.201.11:51:07.88#ibcon#about to write, iclass 12, count 0 2006.201.11:51:07.88#ibcon#wrote, iclass 12, count 0 2006.201.11:51:07.88#ibcon#about to read 3, iclass 12, count 0 2006.201.11:51:07.92#ibcon#read 3, iclass 12, count 0 2006.201.11:51:07.92#ibcon#about to read 4, iclass 12, count 0 2006.201.11:51:07.92#ibcon#read 4, iclass 12, count 0 2006.201.11:51:07.92#ibcon#about to read 5, iclass 12, count 0 2006.201.11:51:07.92#ibcon#read 5, iclass 12, count 0 2006.201.11:51:07.92#ibcon#about to read 6, iclass 12, count 0 2006.201.11:51:07.92#ibcon#read 6, iclass 12, count 0 2006.201.11:51:07.92#ibcon#end of sib2, iclass 12, count 0 2006.201.11:51:07.92#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:51:07.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:51:07.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.11:51:07.92#ibcon#*before write, iclass 12, count 0 2006.201.11:51:07.92#ibcon#enter sib2, iclass 12, count 0 2006.201.11:51:07.92#ibcon#flushed, iclass 12, count 0 2006.201.11:51:07.92#ibcon#about to write, iclass 12, count 0 2006.201.11:51:07.92#ibcon#wrote, iclass 12, count 0 2006.201.11:51:07.92#ibcon#about to read 3, iclass 12, count 0 2006.201.11:51:07.97#ibcon#read 3, iclass 12, count 0 2006.201.11:51:07.97#ibcon#about to read 4, iclass 12, count 0 2006.201.11:51:07.97#ibcon#read 4, iclass 12, count 0 2006.201.11:51:07.97#ibcon#about to read 5, iclass 12, count 0 2006.201.11:51:07.97#ibcon#read 5, iclass 12, count 0 2006.201.11:51:07.97#ibcon#about to read 6, iclass 12, count 0 2006.201.11:51:07.97#ibcon#read 6, iclass 12, count 0 2006.201.11:51:07.97#ibcon#end of sib2, iclass 12, count 0 2006.201.11:51:07.97#ibcon#*after write, iclass 12, count 0 2006.201.11:51:07.97#ibcon#*before return 0, iclass 12, count 0 2006.201.11:51:07.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:07.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:07.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:51:07.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:51:07.97$vck44/va=1,8 2006.201.11:51:07.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.11:51:07.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.11:51:07.97#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:07.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:07.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:07.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:07.97#ibcon#enter wrdev, iclass 14, count 2 2006.201.11:51:07.97#ibcon#first serial, iclass 14, count 2 2006.201.11:51:07.97#ibcon#enter sib2, iclass 14, count 2 2006.201.11:51:07.97#ibcon#flushed, iclass 14, count 2 2006.201.11:51:07.97#ibcon#about to write, iclass 14, count 2 2006.201.11:51:07.97#ibcon#wrote, iclass 14, count 2 2006.201.11:51:07.97#ibcon#about to read 3, iclass 14, count 2 2006.201.11:51:07.99#ibcon#read 3, iclass 14, count 2 2006.201.11:51:07.99#ibcon#about to read 4, iclass 14, count 2 2006.201.11:51:07.99#ibcon#read 4, iclass 14, count 2 2006.201.11:51:07.99#ibcon#about to read 5, iclass 14, count 2 2006.201.11:51:07.99#ibcon#read 5, iclass 14, count 2 2006.201.11:51:07.99#ibcon#about to read 6, iclass 14, count 2 2006.201.11:51:07.99#ibcon#read 6, iclass 14, count 2 2006.201.11:51:07.99#ibcon#end of sib2, iclass 14, count 2 2006.201.11:51:07.99#ibcon#*mode == 0, iclass 14, count 2 2006.201.11:51:07.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.11:51:07.99#ibcon#[25=AT01-08\r\n] 2006.201.11:51:07.99#ibcon#*before write, iclass 14, count 2 2006.201.11:51:07.99#ibcon#enter sib2, iclass 14, count 2 2006.201.11:51:07.99#ibcon#flushed, iclass 14, count 2 2006.201.11:51:07.99#ibcon#about to write, iclass 14, count 2 2006.201.11:51:07.99#ibcon#wrote, iclass 14, count 2 2006.201.11:51:07.99#ibcon#about to read 3, iclass 14, count 2 2006.201.11:51:08.03#ibcon#read 3, iclass 14, count 2 2006.201.11:51:08.03#ibcon#about to read 4, iclass 14, count 2 2006.201.11:51:08.03#ibcon#read 4, iclass 14, count 2 2006.201.11:51:08.03#ibcon#about to read 5, iclass 14, count 2 2006.201.11:51:08.03#ibcon#read 5, iclass 14, count 2 2006.201.11:51:08.03#ibcon#about to read 6, iclass 14, count 2 2006.201.11:51:08.03#ibcon#read 6, iclass 14, count 2 2006.201.11:51:08.03#ibcon#end of sib2, iclass 14, count 2 2006.201.11:51:08.03#ibcon#*after write, iclass 14, count 2 2006.201.11:51:08.03#ibcon#*before return 0, iclass 14, count 2 2006.201.11:51:08.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:08.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:08.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.11:51:08.03#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:08.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:08.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:08.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:08.15#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:51:08.15#ibcon#first serial, iclass 14, count 0 2006.201.11:51:08.15#ibcon#enter sib2, iclass 14, count 0 2006.201.11:51:08.15#ibcon#flushed, iclass 14, count 0 2006.201.11:51:08.15#ibcon#about to write, iclass 14, count 0 2006.201.11:51:08.15#ibcon#wrote, iclass 14, count 0 2006.201.11:51:08.15#ibcon#about to read 3, iclass 14, count 0 2006.201.11:51:08.17#ibcon#read 3, iclass 14, count 0 2006.201.11:51:08.17#ibcon#about to read 4, iclass 14, count 0 2006.201.11:51:08.17#ibcon#read 4, iclass 14, count 0 2006.201.11:51:08.17#ibcon#about to read 5, iclass 14, count 0 2006.201.11:51:08.17#ibcon#read 5, iclass 14, count 0 2006.201.11:51:08.17#ibcon#about to read 6, iclass 14, count 0 2006.201.11:51:08.17#ibcon#read 6, iclass 14, count 0 2006.201.11:51:08.17#ibcon#end of sib2, iclass 14, count 0 2006.201.11:51:08.17#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:51:08.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:51:08.17#ibcon#[25=USB\r\n] 2006.201.11:51:08.17#ibcon#*before write, iclass 14, count 0 2006.201.11:51:08.17#ibcon#enter sib2, iclass 14, count 0 2006.201.11:51:08.17#ibcon#flushed, iclass 14, count 0 2006.201.11:51:08.17#ibcon#about to write, iclass 14, count 0 2006.201.11:51:08.17#ibcon#wrote, iclass 14, count 0 2006.201.11:51:08.17#ibcon#about to read 3, iclass 14, count 0 2006.201.11:51:08.20#ibcon#read 3, iclass 14, count 0 2006.201.11:51:08.20#ibcon#about to read 4, iclass 14, count 0 2006.201.11:51:08.20#ibcon#read 4, iclass 14, count 0 2006.201.11:51:08.20#ibcon#about to read 5, iclass 14, count 0 2006.201.11:51:08.20#ibcon#read 5, iclass 14, count 0 2006.201.11:51:08.20#ibcon#about to read 6, iclass 14, count 0 2006.201.11:51:08.20#ibcon#read 6, iclass 14, count 0 2006.201.11:51:08.20#ibcon#end of sib2, iclass 14, count 0 2006.201.11:51:08.20#ibcon#*after write, iclass 14, count 0 2006.201.11:51:08.20#ibcon#*before return 0, iclass 14, count 0 2006.201.11:51:08.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:08.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:08.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:51:08.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:51:08.20$vck44/valo=2,534.99 2006.201.11:51:08.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.11:51:08.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.11:51:08.20#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:08.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:08.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:08.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:08.20#ibcon#enter wrdev, iclass 16, count 0 2006.201.11:51:08.20#ibcon#first serial, iclass 16, count 0 2006.201.11:51:08.20#ibcon#enter sib2, iclass 16, count 0 2006.201.11:51:08.20#ibcon#flushed, iclass 16, count 0 2006.201.11:51:08.20#ibcon#about to write, iclass 16, count 0 2006.201.11:51:08.20#ibcon#wrote, iclass 16, count 0 2006.201.11:51:08.20#ibcon#about to read 3, iclass 16, count 0 2006.201.11:51:08.22#ibcon#read 3, iclass 16, count 0 2006.201.11:51:08.22#ibcon#about to read 4, iclass 16, count 0 2006.201.11:51:08.22#ibcon#read 4, iclass 16, count 0 2006.201.11:51:08.22#ibcon#about to read 5, iclass 16, count 0 2006.201.11:51:08.22#ibcon#read 5, iclass 16, count 0 2006.201.11:51:08.22#ibcon#about to read 6, iclass 16, count 0 2006.201.11:51:08.22#ibcon#read 6, iclass 16, count 0 2006.201.11:51:08.22#ibcon#end of sib2, iclass 16, count 0 2006.201.11:51:08.22#ibcon#*mode == 0, iclass 16, count 0 2006.201.11:51:08.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.11:51:08.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.11:51:08.22#ibcon#*before write, iclass 16, count 0 2006.201.11:51:08.22#ibcon#enter sib2, iclass 16, count 0 2006.201.11:51:08.22#ibcon#flushed, iclass 16, count 0 2006.201.11:51:08.22#ibcon#about to write, iclass 16, count 0 2006.201.11:51:08.22#ibcon#wrote, iclass 16, count 0 2006.201.11:51:08.22#ibcon#about to read 3, iclass 16, count 0 2006.201.11:51:08.26#ibcon#read 3, iclass 16, count 0 2006.201.11:51:08.26#ibcon#about to read 4, iclass 16, count 0 2006.201.11:51:08.26#ibcon#read 4, iclass 16, count 0 2006.201.11:51:08.26#ibcon#about to read 5, iclass 16, count 0 2006.201.11:51:08.26#ibcon#read 5, iclass 16, count 0 2006.201.11:51:08.26#ibcon#about to read 6, iclass 16, count 0 2006.201.11:51:08.26#ibcon#read 6, iclass 16, count 0 2006.201.11:51:08.26#ibcon#end of sib2, iclass 16, count 0 2006.201.11:51:08.26#ibcon#*after write, iclass 16, count 0 2006.201.11:51:08.26#ibcon#*before return 0, iclass 16, count 0 2006.201.11:51:08.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:08.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:08.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.11:51:08.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.11:51:08.26$vck44/va=2,7 2006.201.11:51:08.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.11:51:08.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.11:51:08.26#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:08.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:08.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:08.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:08.32#ibcon#enter wrdev, iclass 18, count 2 2006.201.11:51:08.32#ibcon#first serial, iclass 18, count 2 2006.201.11:51:08.32#ibcon#enter sib2, iclass 18, count 2 2006.201.11:51:08.32#ibcon#flushed, iclass 18, count 2 2006.201.11:51:08.32#ibcon#about to write, iclass 18, count 2 2006.201.11:51:08.32#ibcon#wrote, iclass 18, count 2 2006.201.11:51:08.32#ibcon#about to read 3, iclass 18, count 2 2006.201.11:51:08.34#ibcon#read 3, iclass 18, count 2 2006.201.11:51:08.34#ibcon#about to read 4, iclass 18, count 2 2006.201.11:51:08.34#ibcon#read 4, iclass 18, count 2 2006.201.11:51:08.34#ibcon#about to read 5, iclass 18, count 2 2006.201.11:51:08.34#ibcon#read 5, iclass 18, count 2 2006.201.11:51:08.34#ibcon#about to read 6, iclass 18, count 2 2006.201.11:51:08.34#ibcon#read 6, iclass 18, count 2 2006.201.11:51:08.34#ibcon#end of sib2, iclass 18, count 2 2006.201.11:51:08.34#ibcon#*mode == 0, iclass 18, count 2 2006.201.11:51:08.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.11:51:08.34#ibcon#[25=AT02-07\r\n] 2006.201.11:51:08.34#ibcon#*before write, iclass 18, count 2 2006.201.11:51:08.34#ibcon#enter sib2, iclass 18, count 2 2006.201.11:51:08.34#ibcon#flushed, iclass 18, count 2 2006.201.11:51:08.34#ibcon#about to write, iclass 18, count 2 2006.201.11:51:08.34#ibcon#wrote, iclass 18, count 2 2006.201.11:51:08.34#ibcon#about to read 3, iclass 18, count 2 2006.201.11:51:08.37#ibcon#read 3, iclass 18, count 2 2006.201.11:51:08.37#ibcon#about to read 4, iclass 18, count 2 2006.201.11:51:08.37#ibcon#read 4, iclass 18, count 2 2006.201.11:51:08.37#ibcon#about to read 5, iclass 18, count 2 2006.201.11:51:08.37#ibcon#read 5, iclass 18, count 2 2006.201.11:51:08.37#ibcon#about to read 6, iclass 18, count 2 2006.201.11:51:08.37#ibcon#read 6, iclass 18, count 2 2006.201.11:51:08.37#ibcon#end of sib2, iclass 18, count 2 2006.201.11:51:08.37#ibcon#*after write, iclass 18, count 2 2006.201.11:51:08.37#ibcon#*before return 0, iclass 18, count 2 2006.201.11:51:08.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:08.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:08.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.11:51:08.37#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:08.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:08.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:08.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:08.49#ibcon#enter wrdev, iclass 18, count 0 2006.201.11:51:08.49#ibcon#first serial, iclass 18, count 0 2006.201.11:51:08.49#ibcon#enter sib2, iclass 18, count 0 2006.201.11:51:08.49#ibcon#flushed, iclass 18, count 0 2006.201.11:51:08.49#ibcon#about to write, iclass 18, count 0 2006.201.11:51:08.49#ibcon#wrote, iclass 18, count 0 2006.201.11:51:08.49#ibcon#about to read 3, iclass 18, count 0 2006.201.11:51:08.51#ibcon#read 3, iclass 18, count 0 2006.201.11:51:08.51#ibcon#about to read 4, iclass 18, count 0 2006.201.11:51:08.51#ibcon#read 4, iclass 18, count 0 2006.201.11:51:08.51#ibcon#about to read 5, iclass 18, count 0 2006.201.11:51:08.51#ibcon#read 5, iclass 18, count 0 2006.201.11:51:08.51#ibcon#about to read 6, iclass 18, count 0 2006.201.11:51:08.51#ibcon#read 6, iclass 18, count 0 2006.201.11:51:08.51#ibcon#end of sib2, iclass 18, count 0 2006.201.11:51:08.51#ibcon#*mode == 0, iclass 18, count 0 2006.201.11:51:08.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.11:51:08.51#ibcon#[25=USB\r\n] 2006.201.11:51:08.51#ibcon#*before write, iclass 18, count 0 2006.201.11:51:08.51#ibcon#enter sib2, iclass 18, count 0 2006.201.11:51:08.51#ibcon#flushed, iclass 18, count 0 2006.201.11:51:08.51#ibcon#about to write, iclass 18, count 0 2006.201.11:51:08.51#ibcon#wrote, iclass 18, count 0 2006.201.11:51:08.51#ibcon#about to read 3, iclass 18, count 0 2006.201.11:51:08.54#ibcon#read 3, iclass 18, count 0 2006.201.11:51:08.54#ibcon#about to read 4, iclass 18, count 0 2006.201.11:51:08.54#ibcon#read 4, iclass 18, count 0 2006.201.11:51:08.54#ibcon#about to read 5, iclass 18, count 0 2006.201.11:51:08.54#ibcon#read 5, iclass 18, count 0 2006.201.11:51:08.54#ibcon#about to read 6, iclass 18, count 0 2006.201.11:51:08.54#ibcon#read 6, iclass 18, count 0 2006.201.11:51:08.54#ibcon#end of sib2, iclass 18, count 0 2006.201.11:51:08.54#ibcon#*after write, iclass 18, count 0 2006.201.11:51:08.54#ibcon#*before return 0, iclass 18, count 0 2006.201.11:51:08.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:08.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:08.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.11:51:08.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.11:51:08.54$vck44/valo=3,564.99 2006.201.11:51:08.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.11:51:08.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.11:51:08.54#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:08.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:08.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:08.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:08.54#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:51:08.54#ibcon#first serial, iclass 20, count 0 2006.201.11:51:08.54#ibcon#enter sib2, iclass 20, count 0 2006.201.11:51:08.54#ibcon#flushed, iclass 20, count 0 2006.201.11:51:08.54#ibcon#about to write, iclass 20, count 0 2006.201.11:51:08.54#ibcon#wrote, iclass 20, count 0 2006.201.11:51:08.54#ibcon#about to read 3, iclass 20, count 0 2006.201.11:51:08.56#ibcon#read 3, iclass 20, count 0 2006.201.11:51:08.56#ibcon#about to read 4, iclass 20, count 0 2006.201.11:51:08.56#ibcon#read 4, iclass 20, count 0 2006.201.11:51:08.56#ibcon#about to read 5, iclass 20, count 0 2006.201.11:51:08.56#ibcon#read 5, iclass 20, count 0 2006.201.11:51:08.56#ibcon#about to read 6, iclass 20, count 0 2006.201.11:51:08.56#ibcon#read 6, iclass 20, count 0 2006.201.11:51:08.56#ibcon#end of sib2, iclass 20, count 0 2006.201.11:51:08.56#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:51:08.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:51:08.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.11:51:08.56#ibcon#*before write, iclass 20, count 0 2006.201.11:51:08.56#ibcon#enter sib2, iclass 20, count 0 2006.201.11:51:08.56#ibcon#flushed, iclass 20, count 0 2006.201.11:51:08.56#ibcon#about to write, iclass 20, count 0 2006.201.11:51:08.56#ibcon#wrote, iclass 20, count 0 2006.201.11:51:08.56#ibcon#about to read 3, iclass 20, count 0 2006.201.11:51:08.61#ibcon#read 3, iclass 20, count 0 2006.201.11:51:08.61#ibcon#about to read 4, iclass 20, count 0 2006.201.11:51:08.61#ibcon#read 4, iclass 20, count 0 2006.201.11:51:08.61#ibcon#about to read 5, iclass 20, count 0 2006.201.11:51:08.61#ibcon#read 5, iclass 20, count 0 2006.201.11:51:08.61#ibcon#about to read 6, iclass 20, count 0 2006.201.11:51:08.61#ibcon#read 6, iclass 20, count 0 2006.201.11:51:08.61#ibcon#end of sib2, iclass 20, count 0 2006.201.11:51:08.61#ibcon#*after write, iclass 20, count 0 2006.201.11:51:08.61#ibcon#*before return 0, iclass 20, count 0 2006.201.11:51:08.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:08.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:08.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:51:08.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:51:08.61$vck44/va=3,8 2006.201.11:51:08.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.11:51:08.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.11:51:08.61#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:08.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:08.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:08.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:08.66#ibcon#enter wrdev, iclass 22, count 2 2006.201.11:51:08.66#ibcon#first serial, iclass 22, count 2 2006.201.11:51:08.66#ibcon#enter sib2, iclass 22, count 2 2006.201.11:51:08.66#ibcon#flushed, iclass 22, count 2 2006.201.11:51:08.66#ibcon#about to write, iclass 22, count 2 2006.201.11:51:08.66#ibcon#wrote, iclass 22, count 2 2006.201.11:51:08.66#ibcon#about to read 3, iclass 22, count 2 2006.201.11:51:08.68#ibcon#read 3, iclass 22, count 2 2006.201.11:51:08.68#ibcon#about to read 4, iclass 22, count 2 2006.201.11:51:08.68#ibcon#read 4, iclass 22, count 2 2006.201.11:51:08.68#ibcon#about to read 5, iclass 22, count 2 2006.201.11:51:08.68#ibcon#read 5, iclass 22, count 2 2006.201.11:51:08.68#ibcon#about to read 6, iclass 22, count 2 2006.201.11:51:08.68#ibcon#read 6, iclass 22, count 2 2006.201.11:51:08.68#ibcon#end of sib2, iclass 22, count 2 2006.201.11:51:08.68#ibcon#*mode == 0, iclass 22, count 2 2006.201.11:51:08.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.11:51:08.68#ibcon#[25=AT03-08\r\n] 2006.201.11:51:08.68#ibcon#*before write, iclass 22, count 2 2006.201.11:51:08.68#ibcon#enter sib2, iclass 22, count 2 2006.201.11:51:08.68#ibcon#flushed, iclass 22, count 2 2006.201.11:51:08.68#ibcon#about to write, iclass 22, count 2 2006.201.11:51:08.68#ibcon#wrote, iclass 22, count 2 2006.201.11:51:08.68#ibcon#about to read 3, iclass 22, count 2 2006.201.11:51:08.71#ibcon#read 3, iclass 22, count 2 2006.201.11:51:08.71#ibcon#about to read 4, iclass 22, count 2 2006.201.11:51:08.71#ibcon#read 4, iclass 22, count 2 2006.201.11:51:08.71#ibcon#about to read 5, iclass 22, count 2 2006.201.11:51:08.71#ibcon#read 5, iclass 22, count 2 2006.201.11:51:08.71#ibcon#about to read 6, iclass 22, count 2 2006.201.11:51:08.71#ibcon#read 6, iclass 22, count 2 2006.201.11:51:08.71#ibcon#end of sib2, iclass 22, count 2 2006.201.11:51:08.71#ibcon#*after write, iclass 22, count 2 2006.201.11:51:08.71#ibcon#*before return 0, iclass 22, count 2 2006.201.11:51:08.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:08.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:08.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.11:51:08.71#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:08.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:08.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:08.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:08.83#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:51:08.83#ibcon#first serial, iclass 22, count 0 2006.201.11:51:08.83#ibcon#enter sib2, iclass 22, count 0 2006.201.11:51:08.83#ibcon#flushed, iclass 22, count 0 2006.201.11:51:08.83#ibcon#about to write, iclass 22, count 0 2006.201.11:51:08.83#ibcon#wrote, iclass 22, count 0 2006.201.11:51:08.83#ibcon#about to read 3, iclass 22, count 0 2006.201.11:51:08.85#ibcon#read 3, iclass 22, count 0 2006.201.11:51:08.85#ibcon#about to read 4, iclass 22, count 0 2006.201.11:51:08.85#ibcon#read 4, iclass 22, count 0 2006.201.11:51:08.85#ibcon#about to read 5, iclass 22, count 0 2006.201.11:51:08.85#ibcon#read 5, iclass 22, count 0 2006.201.11:51:08.85#ibcon#about to read 6, iclass 22, count 0 2006.201.11:51:08.85#ibcon#read 6, iclass 22, count 0 2006.201.11:51:08.85#ibcon#end of sib2, iclass 22, count 0 2006.201.11:51:08.85#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:51:08.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:51:08.85#ibcon#[25=USB\r\n] 2006.201.11:51:08.85#ibcon#*before write, iclass 22, count 0 2006.201.11:51:08.85#ibcon#enter sib2, iclass 22, count 0 2006.201.11:51:08.85#ibcon#flushed, iclass 22, count 0 2006.201.11:51:08.85#ibcon#about to write, iclass 22, count 0 2006.201.11:51:08.85#ibcon#wrote, iclass 22, count 0 2006.201.11:51:08.85#ibcon#about to read 3, iclass 22, count 0 2006.201.11:51:08.88#ibcon#read 3, iclass 22, count 0 2006.201.11:51:08.88#ibcon#about to read 4, iclass 22, count 0 2006.201.11:51:08.88#ibcon#read 4, iclass 22, count 0 2006.201.11:51:08.88#ibcon#about to read 5, iclass 22, count 0 2006.201.11:51:08.88#ibcon#read 5, iclass 22, count 0 2006.201.11:51:08.88#ibcon#about to read 6, iclass 22, count 0 2006.201.11:51:08.88#ibcon#read 6, iclass 22, count 0 2006.201.11:51:08.88#ibcon#end of sib2, iclass 22, count 0 2006.201.11:51:08.88#ibcon#*after write, iclass 22, count 0 2006.201.11:51:08.88#ibcon#*before return 0, iclass 22, count 0 2006.201.11:51:08.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:08.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:08.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:51:08.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:51:08.88$vck44/valo=4,624.99 2006.201.11:51:08.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.11:51:08.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.11:51:08.88#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:08.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:08.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:08.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:08.88#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:51:08.88#ibcon#first serial, iclass 24, count 0 2006.201.11:51:08.88#ibcon#enter sib2, iclass 24, count 0 2006.201.11:51:08.88#ibcon#flushed, iclass 24, count 0 2006.201.11:51:08.88#ibcon#about to write, iclass 24, count 0 2006.201.11:51:08.88#ibcon#wrote, iclass 24, count 0 2006.201.11:51:08.88#ibcon#about to read 3, iclass 24, count 0 2006.201.11:51:08.90#ibcon#read 3, iclass 24, count 0 2006.201.11:51:08.90#ibcon#about to read 4, iclass 24, count 0 2006.201.11:51:08.90#ibcon#read 4, iclass 24, count 0 2006.201.11:51:08.90#ibcon#about to read 5, iclass 24, count 0 2006.201.11:51:08.90#ibcon#read 5, iclass 24, count 0 2006.201.11:51:08.90#ibcon#about to read 6, iclass 24, count 0 2006.201.11:51:08.90#ibcon#read 6, iclass 24, count 0 2006.201.11:51:08.90#ibcon#end of sib2, iclass 24, count 0 2006.201.11:51:08.90#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:51:08.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:51:08.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.11:51:08.90#ibcon#*before write, iclass 24, count 0 2006.201.11:51:08.90#ibcon#enter sib2, iclass 24, count 0 2006.201.11:51:08.90#ibcon#flushed, iclass 24, count 0 2006.201.11:51:08.90#ibcon#about to write, iclass 24, count 0 2006.201.11:51:08.90#ibcon#wrote, iclass 24, count 0 2006.201.11:51:08.90#ibcon#about to read 3, iclass 24, count 0 2006.201.11:51:08.94#ibcon#read 3, iclass 24, count 0 2006.201.11:51:08.94#ibcon#about to read 4, iclass 24, count 0 2006.201.11:51:08.94#ibcon#read 4, iclass 24, count 0 2006.201.11:51:08.94#ibcon#about to read 5, iclass 24, count 0 2006.201.11:51:08.94#ibcon#read 5, iclass 24, count 0 2006.201.11:51:08.94#ibcon#about to read 6, iclass 24, count 0 2006.201.11:51:08.94#ibcon#read 6, iclass 24, count 0 2006.201.11:51:08.94#ibcon#end of sib2, iclass 24, count 0 2006.201.11:51:08.94#ibcon#*after write, iclass 24, count 0 2006.201.11:51:08.94#ibcon#*before return 0, iclass 24, count 0 2006.201.11:51:08.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:08.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:08.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:51:08.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:51:08.94$vck44/va=4,7 2006.201.11:51:08.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.11:51:08.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.11:51:08.94#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:08.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:09.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:09.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:09.00#ibcon#enter wrdev, iclass 26, count 2 2006.201.11:51:09.00#ibcon#first serial, iclass 26, count 2 2006.201.11:51:09.00#ibcon#enter sib2, iclass 26, count 2 2006.201.11:51:09.00#ibcon#flushed, iclass 26, count 2 2006.201.11:51:09.00#ibcon#about to write, iclass 26, count 2 2006.201.11:51:09.00#ibcon#wrote, iclass 26, count 2 2006.201.11:51:09.00#ibcon#about to read 3, iclass 26, count 2 2006.201.11:51:09.02#ibcon#read 3, iclass 26, count 2 2006.201.11:51:09.02#ibcon#about to read 4, iclass 26, count 2 2006.201.11:51:09.02#ibcon#read 4, iclass 26, count 2 2006.201.11:51:09.02#ibcon#about to read 5, iclass 26, count 2 2006.201.11:51:09.02#ibcon#read 5, iclass 26, count 2 2006.201.11:51:09.02#ibcon#about to read 6, iclass 26, count 2 2006.201.11:51:09.02#ibcon#read 6, iclass 26, count 2 2006.201.11:51:09.02#ibcon#end of sib2, iclass 26, count 2 2006.201.11:51:09.02#ibcon#*mode == 0, iclass 26, count 2 2006.201.11:51:09.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.11:51:09.02#ibcon#[25=AT04-07\r\n] 2006.201.11:51:09.02#ibcon#*before write, iclass 26, count 2 2006.201.11:51:09.02#ibcon#enter sib2, iclass 26, count 2 2006.201.11:51:09.02#ibcon#flushed, iclass 26, count 2 2006.201.11:51:09.02#ibcon#about to write, iclass 26, count 2 2006.201.11:51:09.02#ibcon#wrote, iclass 26, count 2 2006.201.11:51:09.02#ibcon#about to read 3, iclass 26, count 2 2006.201.11:51:09.05#ibcon#read 3, iclass 26, count 2 2006.201.11:51:09.05#ibcon#about to read 4, iclass 26, count 2 2006.201.11:51:09.05#ibcon#read 4, iclass 26, count 2 2006.201.11:51:09.05#ibcon#about to read 5, iclass 26, count 2 2006.201.11:51:09.05#ibcon#read 5, iclass 26, count 2 2006.201.11:51:09.05#ibcon#about to read 6, iclass 26, count 2 2006.201.11:51:09.05#ibcon#read 6, iclass 26, count 2 2006.201.11:51:09.05#ibcon#end of sib2, iclass 26, count 2 2006.201.11:51:09.05#ibcon#*after write, iclass 26, count 2 2006.201.11:51:09.05#ibcon#*before return 0, iclass 26, count 2 2006.201.11:51:09.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:09.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:09.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.11:51:09.05#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:09.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:09.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:09.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:09.17#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:51:09.17#ibcon#first serial, iclass 26, count 0 2006.201.11:51:09.17#ibcon#enter sib2, iclass 26, count 0 2006.201.11:51:09.17#ibcon#flushed, iclass 26, count 0 2006.201.11:51:09.17#ibcon#about to write, iclass 26, count 0 2006.201.11:51:09.17#ibcon#wrote, iclass 26, count 0 2006.201.11:51:09.17#ibcon#about to read 3, iclass 26, count 0 2006.201.11:51:09.19#ibcon#read 3, iclass 26, count 0 2006.201.11:51:09.19#ibcon#about to read 4, iclass 26, count 0 2006.201.11:51:09.19#ibcon#read 4, iclass 26, count 0 2006.201.11:51:09.19#ibcon#about to read 5, iclass 26, count 0 2006.201.11:51:09.19#ibcon#read 5, iclass 26, count 0 2006.201.11:51:09.19#ibcon#about to read 6, iclass 26, count 0 2006.201.11:51:09.19#ibcon#read 6, iclass 26, count 0 2006.201.11:51:09.19#ibcon#end of sib2, iclass 26, count 0 2006.201.11:51:09.19#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:51:09.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:51:09.19#ibcon#[25=USB\r\n] 2006.201.11:51:09.19#ibcon#*before write, iclass 26, count 0 2006.201.11:51:09.19#ibcon#enter sib2, iclass 26, count 0 2006.201.11:51:09.19#ibcon#flushed, iclass 26, count 0 2006.201.11:51:09.19#ibcon#about to write, iclass 26, count 0 2006.201.11:51:09.19#ibcon#wrote, iclass 26, count 0 2006.201.11:51:09.19#ibcon#about to read 3, iclass 26, count 0 2006.201.11:51:09.22#ibcon#read 3, iclass 26, count 0 2006.201.11:51:09.22#ibcon#about to read 4, iclass 26, count 0 2006.201.11:51:09.22#ibcon#read 4, iclass 26, count 0 2006.201.11:51:09.22#ibcon#about to read 5, iclass 26, count 0 2006.201.11:51:09.22#ibcon#read 5, iclass 26, count 0 2006.201.11:51:09.22#ibcon#about to read 6, iclass 26, count 0 2006.201.11:51:09.22#ibcon#read 6, iclass 26, count 0 2006.201.11:51:09.22#ibcon#end of sib2, iclass 26, count 0 2006.201.11:51:09.22#ibcon#*after write, iclass 26, count 0 2006.201.11:51:09.22#ibcon#*before return 0, iclass 26, count 0 2006.201.11:51:09.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:09.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:09.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:51:09.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:51:09.22$vck44/valo=5,734.99 2006.201.11:51:09.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.11:51:09.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.11:51:09.22#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:09.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:09.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:09.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:09.22#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:51:09.22#ibcon#first serial, iclass 28, count 0 2006.201.11:51:09.22#ibcon#enter sib2, iclass 28, count 0 2006.201.11:51:09.22#ibcon#flushed, iclass 28, count 0 2006.201.11:51:09.22#ibcon#about to write, iclass 28, count 0 2006.201.11:51:09.22#ibcon#wrote, iclass 28, count 0 2006.201.11:51:09.22#ibcon#about to read 3, iclass 28, count 0 2006.201.11:51:09.24#ibcon#read 3, iclass 28, count 0 2006.201.11:51:09.24#ibcon#about to read 4, iclass 28, count 0 2006.201.11:51:09.24#ibcon#read 4, iclass 28, count 0 2006.201.11:51:09.24#ibcon#about to read 5, iclass 28, count 0 2006.201.11:51:09.24#ibcon#read 5, iclass 28, count 0 2006.201.11:51:09.24#ibcon#about to read 6, iclass 28, count 0 2006.201.11:51:09.24#ibcon#read 6, iclass 28, count 0 2006.201.11:51:09.24#ibcon#end of sib2, iclass 28, count 0 2006.201.11:51:09.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:51:09.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:51:09.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.11:51:09.24#ibcon#*before write, iclass 28, count 0 2006.201.11:51:09.24#ibcon#enter sib2, iclass 28, count 0 2006.201.11:51:09.24#ibcon#flushed, iclass 28, count 0 2006.201.11:51:09.24#ibcon#about to write, iclass 28, count 0 2006.201.11:51:09.24#ibcon#wrote, iclass 28, count 0 2006.201.11:51:09.24#ibcon#about to read 3, iclass 28, count 0 2006.201.11:51:09.28#ibcon#read 3, iclass 28, count 0 2006.201.11:51:09.28#ibcon#about to read 4, iclass 28, count 0 2006.201.11:51:09.28#ibcon#read 4, iclass 28, count 0 2006.201.11:51:09.28#ibcon#about to read 5, iclass 28, count 0 2006.201.11:51:09.28#ibcon#read 5, iclass 28, count 0 2006.201.11:51:09.28#ibcon#about to read 6, iclass 28, count 0 2006.201.11:51:09.28#ibcon#read 6, iclass 28, count 0 2006.201.11:51:09.28#ibcon#end of sib2, iclass 28, count 0 2006.201.11:51:09.28#ibcon#*after write, iclass 28, count 0 2006.201.11:51:09.28#ibcon#*before return 0, iclass 28, count 0 2006.201.11:51:09.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:09.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:09.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:51:09.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:51:09.28$vck44/va=5,4 2006.201.11:51:09.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.11:51:09.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.11:51:09.28#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:09.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:09.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:09.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:09.34#ibcon#enter wrdev, iclass 30, count 2 2006.201.11:51:09.34#ibcon#first serial, iclass 30, count 2 2006.201.11:51:09.34#ibcon#enter sib2, iclass 30, count 2 2006.201.11:51:09.34#ibcon#flushed, iclass 30, count 2 2006.201.11:51:09.34#ibcon#about to write, iclass 30, count 2 2006.201.11:51:09.34#ibcon#wrote, iclass 30, count 2 2006.201.11:51:09.34#ibcon#about to read 3, iclass 30, count 2 2006.201.11:51:09.36#ibcon#read 3, iclass 30, count 2 2006.201.11:51:09.36#ibcon#about to read 4, iclass 30, count 2 2006.201.11:51:09.36#ibcon#read 4, iclass 30, count 2 2006.201.11:51:09.36#ibcon#about to read 5, iclass 30, count 2 2006.201.11:51:09.36#ibcon#read 5, iclass 30, count 2 2006.201.11:51:09.36#ibcon#about to read 6, iclass 30, count 2 2006.201.11:51:09.36#ibcon#read 6, iclass 30, count 2 2006.201.11:51:09.36#ibcon#end of sib2, iclass 30, count 2 2006.201.11:51:09.36#ibcon#*mode == 0, iclass 30, count 2 2006.201.11:51:09.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.11:51:09.36#ibcon#[25=AT05-04\r\n] 2006.201.11:51:09.36#ibcon#*before write, iclass 30, count 2 2006.201.11:51:09.36#ibcon#enter sib2, iclass 30, count 2 2006.201.11:51:09.36#ibcon#flushed, iclass 30, count 2 2006.201.11:51:09.36#ibcon#about to write, iclass 30, count 2 2006.201.11:51:09.36#ibcon#wrote, iclass 30, count 2 2006.201.11:51:09.36#ibcon#about to read 3, iclass 30, count 2 2006.201.11:51:09.39#ibcon#read 3, iclass 30, count 2 2006.201.11:51:09.39#ibcon#about to read 4, iclass 30, count 2 2006.201.11:51:09.39#ibcon#read 4, iclass 30, count 2 2006.201.11:51:09.39#ibcon#about to read 5, iclass 30, count 2 2006.201.11:51:09.39#ibcon#read 5, iclass 30, count 2 2006.201.11:51:09.39#ibcon#about to read 6, iclass 30, count 2 2006.201.11:51:09.39#ibcon#read 6, iclass 30, count 2 2006.201.11:51:09.39#ibcon#end of sib2, iclass 30, count 2 2006.201.11:51:09.39#ibcon#*after write, iclass 30, count 2 2006.201.11:51:09.39#ibcon#*before return 0, iclass 30, count 2 2006.201.11:51:09.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:09.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:09.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.11:51:09.39#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:09.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:09.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:09.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:09.51#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:51:09.51#ibcon#first serial, iclass 30, count 0 2006.201.11:51:09.51#ibcon#enter sib2, iclass 30, count 0 2006.201.11:51:09.51#ibcon#flushed, iclass 30, count 0 2006.201.11:51:09.51#ibcon#about to write, iclass 30, count 0 2006.201.11:51:09.51#ibcon#wrote, iclass 30, count 0 2006.201.11:51:09.51#ibcon#about to read 3, iclass 30, count 0 2006.201.11:51:09.53#ibcon#read 3, iclass 30, count 0 2006.201.11:51:09.53#ibcon#about to read 4, iclass 30, count 0 2006.201.11:51:09.53#ibcon#read 4, iclass 30, count 0 2006.201.11:51:09.53#ibcon#about to read 5, iclass 30, count 0 2006.201.11:51:09.53#ibcon#read 5, iclass 30, count 0 2006.201.11:51:09.53#ibcon#about to read 6, iclass 30, count 0 2006.201.11:51:09.53#ibcon#read 6, iclass 30, count 0 2006.201.11:51:09.53#ibcon#end of sib2, iclass 30, count 0 2006.201.11:51:09.53#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:51:09.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:51:09.53#ibcon#[25=USB\r\n] 2006.201.11:51:09.53#ibcon#*before write, iclass 30, count 0 2006.201.11:51:09.53#ibcon#enter sib2, iclass 30, count 0 2006.201.11:51:09.53#ibcon#flushed, iclass 30, count 0 2006.201.11:51:09.53#ibcon#about to write, iclass 30, count 0 2006.201.11:51:09.53#ibcon#wrote, iclass 30, count 0 2006.201.11:51:09.53#ibcon#about to read 3, iclass 30, count 0 2006.201.11:51:09.56#ibcon#read 3, iclass 30, count 0 2006.201.11:51:09.56#ibcon#about to read 4, iclass 30, count 0 2006.201.11:51:09.56#ibcon#read 4, iclass 30, count 0 2006.201.11:51:09.56#ibcon#about to read 5, iclass 30, count 0 2006.201.11:51:09.56#ibcon#read 5, iclass 30, count 0 2006.201.11:51:09.56#ibcon#about to read 6, iclass 30, count 0 2006.201.11:51:09.56#ibcon#read 6, iclass 30, count 0 2006.201.11:51:09.56#ibcon#end of sib2, iclass 30, count 0 2006.201.11:51:09.56#ibcon#*after write, iclass 30, count 0 2006.201.11:51:09.56#ibcon#*before return 0, iclass 30, count 0 2006.201.11:51:09.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:09.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:09.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:51:09.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:51:09.56$vck44/valo=6,814.99 2006.201.11:51:09.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.11:51:09.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.11:51:09.56#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:09.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:09.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:09.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:09.56#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:51:09.56#ibcon#first serial, iclass 32, count 0 2006.201.11:51:09.56#ibcon#enter sib2, iclass 32, count 0 2006.201.11:51:09.56#ibcon#flushed, iclass 32, count 0 2006.201.11:51:09.56#ibcon#about to write, iclass 32, count 0 2006.201.11:51:09.56#ibcon#wrote, iclass 32, count 0 2006.201.11:51:09.56#ibcon#about to read 3, iclass 32, count 0 2006.201.11:51:09.58#ibcon#read 3, iclass 32, count 0 2006.201.11:51:09.58#ibcon#about to read 4, iclass 32, count 0 2006.201.11:51:09.58#ibcon#read 4, iclass 32, count 0 2006.201.11:51:09.58#ibcon#about to read 5, iclass 32, count 0 2006.201.11:51:09.58#ibcon#read 5, iclass 32, count 0 2006.201.11:51:09.58#ibcon#about to read 6, iclass 32, count 0 2006.201.11:51:09.58#ibcon#read 6, iclass 32, count 0 2006.201.11:51:09.58#ibcon#end of sib2, iclass 32, count 0 2006.201.11:51:09.58#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:51:09.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:51:09.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.11:51:09.58#ibcon#*before write, iclass 32, count 0 2006.201.11:51:09.58#ibcon#enter sib2, iclass 32, count 0 2006.201.11:51:09.58#ibcon#flushed, iclass 32, count 0 2006.201.11:51:09.58#ibcon#about to write, iclass 32, count 0 2006.201.11:51:09.58#ibcon#wrote, iclass 32, count 0 2006.201.11:51:09.58#ibcon#about to read 3, iclass 32, count 0 2006.201.11:51:09.63#ibcon#read 3, iclass 32, count 0 2006.201.11:51:09.63#ibcon#about to read 4, iclass 32, count 0 2006.201.11:51:09.63#ibcon#read 4, iclass 32, count 0 2006.201.11:51:09.63#ibcon#about to read 5, iclass 32, count 0 2006.201.11:51:09.63#ibcon#read 5, iclass 32, count 0 2006.201.11:51:09.63#ibcon#about to read 6, iclass 32, count 0 2006.201.11:51:09.63#ibcon#read 6, iclass 32, count 0 2006.201.11:51:09.63#ibcon#end of sib2, iclass 32, count 0 2006.201.11:51:09.63#ibcon#*after write, iclass 32, count 0 2006.201.11:51:09.63#ibcon#*before return 0, iclass 32, count 0 2006.201.11:51:09.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:09.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:09.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:51:09.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:51:09.63$vck44/va=6,5 2006.201.11:51:09.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.11:51:09.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.11:51:09.63#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:09.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:09.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:09.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:09.68#ibcon#enter wrdev, iclass 34, count 2 2006.201.11:51:09.68#ibcon#first serial, iclass 34, count 2 2006.201.11:51:09.68#ibcon#enter sib2, iclass 34, count 2 2006.201.11:51:09.68#ibcon#flushed, iclass 34, count 2 2006.201.11:51:09.68#ibcon#about to write, iclass 34, count 2 2006.201.11:51:09.68#ibcon#wrote, iclass 34, count 2 2006.201.11:51:09.68#ibcon#about to read 3, iclass 34, count 2 2006.201.11:51:09.70#ibcon#read 3, iclass 34, count 2 2006.201.11:51:09.70#ibcon#about to read 4, iclass 34, count 2 2006.201.11:51:09.70#ibcon#read 4, iclass 34, count 2 2006.201.11:51:09.70#ibcon#about to read 5, iclass 34, count 2 2006.201.11:51:09.70#ibcon#read 5, iclass 34, count 2 2006.201.11:51:09.70#ibcon#about to read 6, iclass 34, count 2 2006.201.11:51:09.70#ibcon#read 6, iclass 34, count 2 2006.201.11:51:09.70#ibcon#end of sib2, iclass 34, count 2 2006.201.11:51:09.70#ibcon#*mode == 0, iclass 34, count 2 2006.201.11:51:09.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.11:51:09.70#ibcon#[25=AT06-05\r\n] 2006.201.11:51:09.70#ibcon#*before write, iclass 34, count 2 2006.201.11:51:09.70#ibcon#enter sib2, iclass 34, count 2 2006.201.11:51:09.70#ibcon#flushed, iclass 34, count 2 2006.201.11:51:09.70#ibcon#about to write, iclass 34, count 2 2006.201.11:51:09.70#ibcon#wrote, iclass 34, count 2 2006.201.11:51:09.70#ibcon#about to read 3, iclass 34, count 2 2006.201.11:51:09.73#ibcon#read 3, iclass 34, count 2 2006.201.11:51:09.73#ibcon#about to read 4, iclass 34, count 2 2006.201.11:51:09.73#ibcon#read 4, iclass 34, count 2 2006.201.11:51:09.73#ibcon#about to read 5, iclass 34, count 2 2006.201.11:51:09.73#ibcon#read 5, iclass 34, count 2 2006.201.11:51:09.73#ibcon#about to read 6, iclass 34, count 2 2006.201.11:51:09.73#ibcon#read 6, iclass 34, count 2 2006.201.11:51:09.73#ibcon#end of sib2, iclass 34, count 2 2006.201.11:51:09.73#ibcon#*after write, iclass 34, count 2 2006.201.11:51:09.73#ibcon#*before return 0, iclass 34, count 2 2006.201.11:51:09.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:09.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:09.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.11:51:09.73#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:09.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:09.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:09.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:09.85#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:51:09.85#ibcon#first serial, iclass 34, count 0 2006.201.11:51:09.85#ibcon#enter sib2, iclass 34, count 0 2006.201.11:51:09.85#ibcon#flushed, iclass 34, count 0 2006.201.11:51:09.85#ibcon#about to write, iclass 34, count 0 2006.201.11:51:09.85#ibcon#wrote, iclass 34, count 0 2006.201.11:51:09.85#ibcon#about to read 3, iclass 34, count 0 2006.201.11:51:09.87#ibcon#read 3, iclass 34, count 0 2006.201.11:51:09.87#ibcon#about to read 4, iclass 34, count 0 2006.201.11:51:09.87#ibcon#read 4, iclass 34, count 0 2006.201.11:51:09.87#ibcon#about to read 5, iclass 34, count 0 2006.201.11:51:09.87#ibcon#read 5, iclass 34, count 0 2006.201.11:51:09.87#ibcon#about to read 6, iclass 34, count 0 2006.201.11:51:09.87#ibcon#read 6, iclass 34, count 0 2006.201.11:51:09.87#ibcon#end of sib2, iclass 34, count 0 2006.201.11:51:09.87#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:51:09.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:51:09.87#ibcon#[25=USB\r\n] 2006.201.11:51:09.87#ibcon#*before write, iclass 34, count 0 2006.201.11:51:09.87#ibcon#enter sib2, iclass 34, count 0 2006.201.11:51:09.87#ibcon#flushed, iclass 34, count 0 2006.201.11:51:09.87#ibcon#about to write, iclass 34, count 0 2006.201.11:51:09.87#ibcon#wrote, iclass 34, count 0 2006.201.11:51:09.87#ibcon#about to read 3, iclass 34, count 0 2006.201.11:51:09.90#ibcon#read 3, iclass 34, count 0 2006.201.11:51:09.90#ibcon#about to read 4, iclass 34, count 0 2006.201.11:51:09.90#ibcon#read 4, iclass 34, count 0 2006.201.11:51:09.90#ibcon#about to read 5, iclass 34, count 0 2006.201.11:51:09.90#ibcon#read 5, iclass 34, count 0 2006.201.11:51:09.90#ibcon#about to read 6, iclass 34, count 0 2006.201.11:51:09.90#ibcon#read 6, iclass 34, count 0 2006.201.11:51:09.90#ibcon#end of sib2, iclass 34, count 0 2006.201.11:51:09.90#ibcon#*after write, iclass 34, count 0 2006.201.11:51:09.90#ibcon#*before return 0, iclass 34, count 0 2006.201.11:51:09.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:09.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:09.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:51:09.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:51:09.90$vck44/valo=7,864.99 2006.201.11:51:09.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.11:51:09.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.11:51:09.90#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:09.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:09.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:09.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:09.90#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:51:09.90#ibcon#first serial, iclass 36, count 0 2006.201.11:51:09.90#ibcon#enter sib2, iclass 36, count 0 2006.201.11:51:09.90#ibcon#flushed, iclass 36, count 0 2006.201.11:51:09.90#ibcon#about to write, iclass 36, count 0 2006.201.11:51:09.90#ibcon#wrote, iclass 36, count 0 2006.201.11:51:09.90#ibcon#about to read 3, iclass 36, count 0 2006.201.11:51:09.92#ibcon#read 3, iclass 36, count 0 2006.201.11:51:09.92#ibcon#about to read 4, iclass 36, count 0 2006.201.11:51:09.92#ibcon#read 4, iclass 36, count 0 2006.201.11:51:09.92#ibcon#about to read 5, iclass 36, count 0 2006.201.11:51:09.92#ibcon#read 5, iclass 36, count 0 2006.201.11:51:09.92#ibcon#about to read 6, iclass 36, count 0 2006.201.11:51:09.92#ibcon#read 6, iclass 36, count 0 2006.201.11:51:09.92#ibcon#end of sib2, iclass 36, count 0 2006.201.11:51:09.92#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:51:09.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:51:09.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.11:51:09.92#ibcon#*before write, iclass 36, count 0 2006.201.11:51:09.92#ibcon#enter sib2, iclass 36, count 0 2006.201.11:51:09.92#ibcon#flushed, iclass 36, count 0 2006.201.11:51:09.92#ibcon#about to write, iclass 36, count 0 2006.201.11:51:09.92#ibcon#wrote, iclass 36, count 0 2006.201.11:51:09.92#ibcon#about to read 3, iclass 36, count 0 2006.201.11:51:09.96#ibcon#read 3, iclass 36, count 0 2006.201.11:51:09.96#ibcon#about to read 4, iclass 36, count 0 2006.201.11:51:09.96#ibcon#read 4, iclass 36, count 0 2006.201.11:51:09.96#ibcon#about to read 5, iclass 36, count 0 2006.201.11:51:09.96#ibcon#read 5, iclass 36, count 0 2006.201.11:51:09.96#ibcon#about to read 6, iclass 36, count 0 2006.201.11:51:09.96#ibcon#read 6, iclass 36, count 0 2006.201.11:51:09.96#ibcon#end of sib2, iclass 36, count 0 2006.201.11:51:09.96#ibcon#*after write, iclass 36, count 0 2006.201.11:51:09.96#ibcon#*before return 0, iclass 36, count 0 2006.201.11:51:09.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:09.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:09.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:51:09.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:51:09.96$vck44/va=7,5 2006.201.11:51:09.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.11:51:09.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.11:51:09.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:09.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:10.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:10.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:10.02#ibcon#enter wrdev, iclass 38, count 2 2006.201.11:51:10.02#ibcon#first serial, iclass 38, count 2 2006.201.11:51:10.02#ibcon#enter sib2, iclass 38, count 2 2006.201.11:51:10.02#ibcon#flushed, iclass 38, count 2 2006.201.11:51:10.02#ibcon#about to write, iclass 38, count 2 2006.201.11:51:10.02#ibcon#wrote, iclass 38, count 2 2006.201.11:51:10.02#ibcon#about to read 3, iclass 38, count 2 2006.201.11:51:10.04#ibcon#read 3, iclass 38, count 2 2006.201.11:51:10.04#ibcon#about to read 4, iclass 38, count 2 2006.201.11:51:10.04#ibcon#read 4, iclass 38, count 2 2006.201.11:51:10.04#ibcon#about to read 5, iclass 38, count 2 2006.201.11:51:10.04#ibcon#read 5, iclass 38, count 2 2006.201.11:51:10.04#ibcon#about to read 6, iclass 38, count 2 2006.201.11:51:10.04#ibcon#read 6, iclass 38, count 2 2006.201.11:51:10.04#ibcon#end of sib2, iclass 38, count 2 2006.201.11:51:10.04#ibcon#*mode == 0, iclass 38, count 2 2006.201.11:51:10.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.11:51:10.04#ibcon#[25=AT07-05\r\n] 2006.201.11:51:10.04#ibcon#*before write, iclass 38, count 2 2006.201.11:51:10.04#ibcon#enter sib2, iclass 38, count 2 2006.201.11:51:10.04#ibcon#flushed, iclass 38, count 2 2006.201.11:51:10.04#ibcon#about to write, iclass 38, count 2 2006.201.11:51:10.04#ibcon#wrote, iclass 38, count 2 2006.201.11:51:10.04#ibcon#about to read 3, iclass 38, count 2 2006.201.11:51:10.07#ibcon#read 3, iclass 38, count 2 2006.201.11:51:10.07#ibcon#about to read 4, iclass 38, count 2 2006.201.11:51:10.07#ibcon#read 4, iclass 38, count 2 2006.201.11:51:10.07#ibcon#about to read 5, iclass 38, count 2 2006.201.11:51:10.07#ibcon#read 5, iclass 38, count 2 2006.201.11:51:10.07#ibcon#about to read 6, iclass 38, count 2 2006.201.11:51:10.07#ibcon#read 6, iclass 38, count 2 2006.201.11:51:10.07#ibcon#end of sib2, iclass 38, count 2 2006.201.11:51:10.07#ibcon#*after write, iclass 38, count 2 2006.201.11:51:10.07#ibcon#*before return 0, iclass 38, count 2 2006.201.11:51:10.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:10.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:10.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.11:51:10.07#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:10.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:10.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:10.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:10.19#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:51:10.19#ibcon#first serial, iclass 38, count 0 2006.201.11:51:10.19#ibcon#enter sib2, iclass 38, count 0 2006.201.11:51:10.19#ibcon#flushed, iclass 38, count 0 2006.201.11:51:10.19#ibcon#about to write, iclass 38, count 0 2006.201.11:51:10.19#ibcon#wrote, iclass 38, count 0 2006.201.11:51:10.19#ibcon#about to read 3, iclass 38, count 0 2006.201.11:51:10.21#ibcon#read 3, iclass 38, count 0 2006.201.11:51:10.21#ibcon#about to read 4, iclass 38, count 0 2006.201.11:51:10.21#ibcon#read 4, iclass 38, count 0 2006.201.11:51:10.21#ibcon#about to read 5, iclass 38, count 0 2006.201.11:51:10.21#ibcon#read 5, iclass 38, count 0 2006.201.11:51:10.21#ibcon#about to read 6, iclass 38, count 0 2006.201.11:51:10.21#ibcon#read 6, iclass 38, count 0 2006.201.11:51:10.21#ibcon#end of sib2, iclass 38, count 0 2006.201.11:51:10.21#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:51:10.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:51:10.21#ibcon#[25=USB\r\n] 2006.201.11:51:10.21#ibcon#*before write, iclass 38, count 0 2006.201.11:51:10.21#ibcon#enter sib2, iclass 38, count 0 2006.201.11:51:10.21#ibcon#flushed, iclass 38, count 0 2006.201.11:51:10.21#ibcon#about to write, iclass 38, count 0 2006.201.11:51:10.21#ibcon#wrote, iclass 38, count 0 2006.201.11:51:10.21#ibcon#about to read 3, iclass 38, count 0 2006.201.11:51:10.24#ibcon#read 3, iclass 38, count 0 2006.201.11:51:10.24#ibcon#about to read 4, iclass 38, count 0 2006.201.11:51:10.24#ibcon#read 4, iclass 38, count 0 2006.201.11:51:10.24#ibcon#about to read 5, iclass 38, count 0 2006.201.11:51:10.24#ibcon#read 5, iclass 38, count 0 2006.201.11:51:10.24#ibcon#about to read 6, iclass 38, count 0 2006.201.11:51:10.24#ibcon#read 6, iclass 38, count 0 2006.201.11:51:10.24#ibcon#end of sib2, iclass 38, count 0 2006.201.11:51:10.24#ibcon#*after write, iclass 38, count 0 2006.201.11:51:10.24#ibcon#*before return 0, iclass 38, count 0 2006.201.11:51:10.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:10.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:10.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:51:10.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:51:10.24$vck44/valo=8,884.99 2006.201.11:51:10.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.11:51:10.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.11:51:10.24#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:10.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:10.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:10.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:10.24#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:51:10.24#ibcon#first serial, iclass 40, count 0 2006.201.11:51:10.24#ibcon#enter sib2, iclass 40, count 0 2006.201.11:51:10.24#ibcon#flushed, iclass 40, count 0 2006.201.11:51:10.24#ibcon#about to write, iclass 40, count 0 2006.201.11:51:10.24#ibcon#wrote, iclass 40, count 0 2006.201.11:51:10.24#ibcon#about to read 3, iclass 40, count 0 2006.201.11:51:10.26#ibcon#read 3, iclass 40, count 0 2006.201.11:51:10.26#ibcon#about to read 4, iclass 40, count 0 2006.201.11:51:10.26#ibcon#read 4, iclass 40, count 0 2006.201.11:51:10.26#ibcon#about to read 5, iclass 40, count 0 2006.201.11:51:10.26#ibcon#read 5, iclass 40, count 0 2006.201.11:51:10.26#ibcon#about to read 6, iclass 40, count 0 2006.201.11:51:10.26#ibcon#read 6, iclass 40, count 0 2006.201.11:51:10.26#ibcon#end of sib2, iclass 40, count 0 2006.201.11:51:10.26#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:51:10.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:51:10.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.11:51:10.26#ibcon#*before write, iclass 40, count 0 2006.201.11:51:10.26#ibcon#enter sib2, iclass 40, count 0 2006.201.11:51:10.26#ibcon#flushed, iclass 40, count 0 2006.201.11:51:10.26#ibcon#about to write, iclass 40, count 0 2006.201.11:51:10.26#ibcon#wrote, iclass 40, count 0 2006.201.11:51:10.26#ibcon#about to read 3, iclass 40, count 0 2006.201.11:51:10.30#ibcon#read 3, iclass 40, count 0 2006.201.11:51:10.30#ibcon#about to read 4, iclass 40, count 0 2006.201.11:51:10.30#ibcon#read 4, iclass 40, count 0 2006.201.11:51:10.30#ibcon#about to read 5, iclass 40, count 0 2006.201.11:51:10.30#ibcon#read 5, iclass 40, count 0 2006.201.11:51:10.30#ibcon#about to read 6, iclass 40, count 0 2006.201.11:51:10.30#ibcon#read 6, iclass 40, count 0 2006.201.11:51:10.30#ibcon#end of sib2, iclass 40, count 0 2006.201.11:51:10.30#ibcon#*after write, iclass 40, count 0 2006.201.11:51:10.30#ibcon#*before return 0, iclass 40, count 0 2006.201.11:51:10.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:10.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:10.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:51:10.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:51:10.30$vck44/va=8,4 2006.201.11:51:10.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.11:51:10.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.11:51:10.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:10.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:51:10.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:51:10.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:51:10.36#ibcon#enter wrdev, iclass 4, count 2 2006.201.11:51:10.36#ibcon#first serial, iclass 4, count 2 2006.201.11:51:10.36#ibcon#enter sib2, iclass 4, count 2 2006.201.11:51:10.36#ibcon#flushed, iclass 4, count 2 2006.201.11:51:10.36#ibcon#about to write, iclass 4, count 2 2006.201.11:51:10.36#ibcon#wrote, iclass 4, count 2 2006.201.11:51:10.36#ibcon#about to read 3, iclass 4, count 2 2006.201.11:51:10.38#ibcon#read 3, iclass 4, count 2 2006.201.11:51:10.38#ibcon#about to read 4, iclass 4, count 2 2006.201.11:51:10.38#ibcon#read 4, iclass 4, count 2 2006.201.11:51:10.38#ibcon#about to read 5, iclass 4, count 2 2006.201.11:51:10.38#ibcon#read 5, iclass 4, count 2 2006.201.11:51:10.38#ibcon#about to read 6, iclass 4, count 2 2006.201.11:51:10.38#ibcon#read 6, iclass 4, count 2 2006.201.11:51:10.38#ibcon#end of sib2, iclass 4, count 2 2006.201.11:51:10.38#ibcon#*mode == 0, iclass 4, count 2 2006.201.11:51:10.38#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.11:51:10.38#ibcon#[25=AT08-04\r\n] 2006.201.11:51:10.38#ibcon#*before write, iclass 4, count 2 2006.201.11:51:10.38#ibcon#enter sib2, iclass 4, count 2 2006.201.11:51:10.38#ibcon#flushed, iclass 4, count 2 2006.201.11:51:10.38#ibcon#about to write, iclass 4, count 2 2006.201.11:51:10.38#ibcon#wrote, iclass 4, count 2 2006.201.11:51:10.38#ibcon#about to read 3, iclass 4, count 2 2006.201.11:51:10.42#ibcon#read 3, iclass 4, count 2 2006.201.11:51:10.42#ibcon#about to read 4, iclass 4, count 2 2006.201.11:51:10.42#ibcon#read 4, iclass 4, count 2 2006.201.11:51:10.42#ibcon#about to read 5, iclass 4, count 2 2006.201.11:51:10.42#ibcon#read 5, iclass 4, count 2 2006.201.11:51:10.42#ibcon#about to read 6, iclass 4, count 2 2006.201.11:51:10.42#ibcon#read 6, iclass 4, count 2 2006.201.11:51:10.42#ibcon#end of sib2, iclass 4, count 2 2006.201.11:51:10.42#ibcon#*after write, iclass 4, count 2 2006.201.11:51:10.42#ibcon#*before return 0, iclass 4, count 2 2006.201.11:51:10.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:51:10.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.11:51:10.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.11:51:10.42#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:10.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:51:10.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:51:10.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:51:10.54#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:51:10.54#ibcon#first serial, iclass 4, count 0 2006.201.11:51:10.54#ibcon#enter sib2, iclass 4, count 0 2006.201.11:51:10.54#ibcon#flushed, iclass 4, count 0 2006.201.11:51:10.54#ibcon#about to write, iclass 4, count 0 2006.201.11:51:10.54#ibcon#wrote, iclass 4, count 0 2006.201.11:51:10.54#ibcon#about to read 3, iclass 4, count 0 2006.201.11:51:10.56#ibcon#read 3, iclass 4, count 0 2006.201.11:51:10.56#ibcon#about to read 4, iclass 4, count 0 2006.201.11:51:10.56#ibcon#read 4, iclass 4, count 0 2006.201.11:51:10.56#ibcon#about to read 5, iclass 4, count 0 2006.201.11:51:10.56#ibcon#read 5, iclass 4, count 0 2006.201.11:51:10.56#ibcon#about to read 6, iclass 4, count 0 2006.201.11:51:10.56#ibcon#read 6, iclass 4, count 0 2006.201.11:51:10.56#ibcon#end of sib2, iclass 4, count 0 2006.201.11:51:10.56#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:51:10.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:51:10.56#ibcon#[25=USB\r\n] 2006.201.11:51:10.56#ibcon#*before write, iclass 4, count 0 2006.201.11:51:10.56#ibcon#enter sib2, iclass 4, count 0 2006.201.11:51:10.56#ibcon#flushed, iclass 4, count 0 2006.201.11:51:10.56#ibcon#about to write, iclass 4, count 0 2006.201.11:51:10.56#ibcon#wrote, iclass 4, count 0 2006.201.11:51:10.56#ibcon#about to read 3, iclass 4, count 0 2006.201.11:51:10.59#ibcon#read 3, iclass 4, count 0 2006.201.11:51:10.59#ibcon#about to read 4, iclass 4, count 0 2006.201.11:51:10.59#ibcon#read 4, iclass 4, count 0 2006.201.11:51:10.59#ibcon#about to read 5, iclass 4, count 0 2006.201.11:51:10.59#ibcon#read 5, iclass 4, count 0 2006.201.11:51:10.59#ibcon#about to read 6, iclass 4, count 0 2006.201.11:51:10.59#ibcon#read 6, iclass 4, count 0 2006.201.11:51:10.59#ibcon#end of sib2, iclass 4, count 0 2006.201.11:51:10.59#ibcon#*after write, iclass 4, count 0 2006.201.11:51:10.59#ibcon#*before return 0, iclass 4, count 0 2006.201.11:51:10.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:51:10.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.11:51:10.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:51:10.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:51:10.59$vck44/vblo=1,629.99 2006.201.11:51:10.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.11:51:10.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.11:51:10.59#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:10.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:51:10.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:51:10.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:51:10.59#ibcon#enter wrdev, iclass 6, count 0 2006.201.11:51:10.59#ibcon#first serial, iclass 6, count 0 2006.201.11:51:10.59#ibcon#enter sib2, iclass 6, count 0 2006.201.11:51:10.59#ibcon#flushed, iclass 6, count 0 2006.201.11:51:10.59#ibcon#about to write, iclass 6, count 0 2006.201.11:51:10.59#ibcon#wrote, iclass 6, count 0 2006.201.11:51:10.59#ibcon#about to read 3, iclass 6, count 0 2006.201.11:51:10.61#ibcon#read 3, iclass 6, count 0 2006.201.11:51:10.61#ibcon#about to read 4, iclass 6, count 0 2006.201.11:51:10.61#ibcon#read 4, iclass 6, count 0 2006.201.11:51:10.61#ibcon#about to read 5, iclass 6, count 0 2006.201.11:51:10.61#ibcon#read 5, iclass 6, count 0 2006.201.11:51:10.61#ibcon#about to read 6, iclass 6, count 0 2006.201.11:51:10.61#ibcon#read 6, iclass 6, count 0 2006.201.11:51:10.61#ibcon#end of sib2, iclass 6, count 0 2006.201.11:51:10.61#ibcon#*mode == 0, iclass 6, count 0 2006.201.11:51:10.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.11:51:10.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.11:51:10.61#ibcon#*before write, iclass 6, count 0 2006.201.11:51:10.61#ibcon#enter sib2, iclass 6, count 0 2006.201.11:51:10.61#ibcon#flushed, iclass 6, count 0 2006.201.11:51:10.61#ibcon#about to write, iclass 6, count 0 2006.201.11:51:10.61#ibcon#wrote, iclass 6, count 0 2006.201.11:51:10.61#ibcon#about to read 3, iclass 6, count 0 2006.201.11:51:10.65#ibcon#read 3, iclass 6, count 0 2006.201.11:51:10.65#ibcon#about to read 4, iclass 6, count 0 2006.201.11:51:10.65#ibcon#read 4, iclass 6, count 0 2006.201.11:51:10.65#ibcon#about to read 5, iclass 6, count 0 2006.201.11:51:10.65#ibcon#read 5, iclass 6, count 0 2006.201.11:51:10.65#ibcon#about to read 6, iclass 6, count 0 2006.201.11:51:10.65#ibcon#read 6, iclass 6, count 0 2006.201.11:51:10.65#ibcon#end of sib2, iclass 6, count 0 2006.201.11:51:10.65#ibcon#*after write, iclass 6, count 0 2006.201.11:51:10.65#ibcon#*before return 0, iclass 6, count 0 2006.201.11:51:10.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:51:10.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.11:51:10.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.11:51:10.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.11:51:10.65$vck44/vb=1,4 2006.201.11:51:10.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.11:51:10.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.11:51:10.65#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:10.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:51:10.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:51:10.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:51:10.65#ibcon#enter wrdev, iclass 10, count 2 2006.201.11:51:10.65#ibcon#first serial, iclass 10, count 2 2006.201.11:51:10.65#ibcon#enter sib2, iclass 10, count 2 2006.201.11:51:10.65#ibcon#flushed, iclass 10, count 2 2006.201.11:51:10.65#ibcon#about to write, iclass 10, count 2 2006.201.11:51:10.65#ibcon#wrote, iclass 10, count 2 2006.201.11:51:10.65#ibcon#about to read 3, iclass 10, count 2 2006.201.11:51:10.67#ibcon#read 3, iclass 10, count 2 2006.201.11:51:10.67#ibcon#about to read 4, iclass 10, count 2 2006.201.11:51:10.67#ibcon#read 4, iclass 10, count 2 2006.201.11:51:10.67#ibcon#about to read 5, iclass 10, count 2 2006.201.11:51:10.67#ibcon#read 5, iclass 10, count 2 2006.201.11:51:10.67#ibcon#about to read 6, iclass 10, count 2 2006.201.11:51:10.67#ibcon#read 6, iclass 10, count 2 2006.201.11:51:10.67#ibcon#end of sib2, iclass 10, count 2 2006.201.11:51:10.67#ibcon#*mode == 0, iclass 10, count 2 2006.201.11:51:10.67#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.11:51:10.67#ibcon#[27=AT01-04\r\n] 2006.201.11:51:10.67#ibcon#*before write, iclass 10, count 2 2006.201.11:51:10.67#ibcon#enter sib2, iclass 10, count 2 2006.201.11:51:10.67#ibcon#flushed, iclass 10, count 2 2006.201.11:51:10.67#ibcon#about to write, iclass 10, count 2 2006.201.11:51:10.67#ibcon#wrote, iclass 10, count 2 2006.201.11:51:10.67#ibcon#about to read 3, iclass 10, count 2 2006.201.11:51:10.70#ibcon#read 3, iclass 10, count 2 2006.201.11:51:10.70#ibcon#about to read 4, iclass 10, count 2 2006.201.11:51:10.70#ibcon#read 4, iclass 10, count 2 2006.201.11:51:10.70#ibcon#about to read 5, iclass 10, count 2 2006.201.11:51:10.70#ibcon#read 5, iclass 10, count 2 2006.201.11:51:10.70#ibcon#about to read 6, iclass 10, count 2 2006.201.11:51:10.70#ibcon#read 6, iclass 10, count 2 2006.201.11:51:10.70#ibcon#end of sib2, iclass 10, count 2 2006.201.11:51:10.70#ibcon#*after write, iclass 10, count 2 2006.201.11:51:10.70#ibcon#*before return 0, iclass 10, count 2 2006.201.11:51:10.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:51:10.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.11:51:10.70#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.11:51:10.70#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:10.70#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:51:10.82#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:51:10.82#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:51:10.82#ibcon#enter wrdev, iclass 10, count 0 2006.201.11:51:10.82#ibcon#first serial, iclass 10, count 0 2006.201.11:51:10.82#ibcon#enter sib2, iclass 10, count 0 2006.201.11:51:10.82#ibcon#flushed, iclass 10, count 0 2006.201.11:51:10.82#ibcon#about to write, iclass 10, count 0 2006.201.11:51:10.82#ibcon#wrote, iclass 10, count 0 2006.201.11:51:10.82#ibcon#about to read 3, iclass 10, count 0 2006.201.11:51:10.84#ibcon#read 3, iclass 10, count 0 2006.201.11:51:10.84#ibcon#about to read 4, iclass 10, count 0 2006.201.11:51:10.84#ibcon#read 4, iclass 10, count 0 2006.201.11:51:10.84#ibcon#about to read 5, iclass 10, count 0 2006.201.11:51:10.84#ibcon#read 5, iclass 10, count 0 2006.201.11:51:10.84#ibcon#about to read 6, iclass 10, count 0 2006.201.11:51:10.84#ibcon#read 6, iclass 10, count 0 2006.201.11:51:10.84#ibcon#end of sib2, iclass 10, count 0 2006.201.11:51:10.84#ibcon#*mode == 0, iclass 10, count 0 2006.201.11:51:10.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.11:51:10.84#ibcon#[27=USB\r\n] 2006.201.11:51:10.84#ibcon#*before write, iclass 10, count 0 2006.201.11:51:10.84#ibcon#enter sib2, iclass 10, count 0 2006.201.11:51:10.84#ibcon#flushed, iclass 10, count 0 2006.201.11:51:10.84#ibcon#about to write, iclass 10, count 0 2006.201.11:51:10.84#ibcon#wrote, iclass 10, count 0 2006.201.11:51:10.84#ibcon#about to read 3, iclass 10, count 0 2006.201.11:51:10.87#ibcon#read 3, iclass 10, count 0 2006.201.11:51:10.87#ibcon#about to read 4, iclass 10, count 0 2006.201.11:51:10.87#ibcon#read 4, iclass 10, count 0 2006.201.11:51:10.87#ibcon#about to read 5, iclass 10, count 0 2006.201.11:51:10.87#ibcon#read 5, iclass 10, count 0 2006.201.11:51:10.87#ibcon#about to read 6, iclass 10, count 0 2006.201.11:51:10.87#ibcon#read 6, iclass 10, count 0 2006.201.11:51:10.87#ibcon#end of sib2, iclass 10, count 0 2006.201.11:51:10.87#ibcon#*after write, iclass 10, count 0 2006.201.11:51:10.87#ibcon#*before return 0, iclass 10, count 0 2006.201.11:51:10.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:51:10.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.11:51:10.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.11:51:10.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.11:51:10.87$vck44/vblo=2,634.99 2006.201.11:51:10.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.11:51:10.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.11:51:10.87#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:10.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:10.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:10.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:10.87#ibcon#enter wrdev, iclass 12, count 0 2006.201.11:51:10.87#ibcon#first serial, iclass 12, count 0 2006.201.11:51:10.87#ibcon#enter sib2, iclass 12, count 0 2006.201.11:51:10.87#ibcon#flushed, iclass 12, count 0 2006.201.11:51:10.87#ibcon#about to write, iclass 12, count 0 2006.201.11:51:10.87#ibcon#wrote, iclass 12, count 0 2006.201.11:51:10.87#ibcon#about to read 3, iclass 12, count 0 2006.201.11:51:10.89#ibcon#read 3, iclass 12, count 0 2006.201.11:51:10.89#ibcon#about to read 4, iclass 12, count 0 2006.201.11:51:10.89#ibcon#read 4, iclass 12, count 0 2006.201.11:51:10.89#ibcon#about to read 5, iclass 12, count 0 2006.201.11:51:10.89#ibcon#read 5, iclass 12, count 0 2006.201.11:51:10.89#ibcon#about to read 6, iclass 12, count 0 2006.201.11:51:10.89#ibcon#read 6, iclass 12, count 0 2006.201.11:51:10.89#ibcon#end of sib2, iclass 12, count 0 2006.201.11:51:10.89#ibcon#*mode == 0, iclass 12, count 0 2006.201.11:51:10.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.11:51:10.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.11:51:10.89#ibcon#*before write, iclass 12, count 0 2006.201.11:51:10.89#ibcon#enter sib2, iclass 12, count 0 2006.201.11:51:10.89#ibcon#flushed, iclass 12, count 0 2006.201.11:51:10.89#ibcon#about to write, iclass 12, count 0 2006.201.11:51:10.89#ibcon#wrote, iclass 12, count 0 2006.201.11:51:10.89#ibcon#about to read 3, iclass 12, count 0 2006.201.11:51:10.93#ibcon#read 3, iclass 12, count 0 2006.201.11:51:10.93#ibcon#about to read 4, iclass 12, count 0 2006.201.11:51:10.93#ibcon#read 4, iclass 12, count 0 2006.201.11:51:10.93#ibcon#about to read 5, iclass 12, count 0 2006.201.11:51:10.93#ibcon#read 5, iclass 12, count 0 2006.201.11:51:10.93#ibcon#about to read 6, iclass 12, count 0 2006.201.11:51:10.93#ibcon#read 6, iclass 12, count 0 2006.201.11:51:10.93#ibcon#end of sib2, iclass 12, count 0 2006.201.11:51:10.93#ibcon#*after write, iclass 12, count 0 2006.201.11:51:10.93#ibcon#*before return 0, iclass 12, count 0 2006.201.11:51:10.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:10.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.11:51:10.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.11:51:10.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.11:51:10.93$vck44/vb=2,5 2006.201.11:51:10.93#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.11:51:10.93#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.11:51:10.93#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:10.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:10.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:10.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:10.99#ibcon#enter wrdev, iclass 14, count 2 2006.201.11:51:10.99#ibcon#first serial, iclass 14, count 2 2006.201.11:51:10.99#ibcon#enter sib2, iclass 14, count 2 2006.201.11:51:10.99#ibcon#flushed, iclass 14, count 2 2006.201.11:51:10.99#ibcon#about to write, iclass 14, count 2 2006.201.11:51:10.99#ibcon#wrote, iclass 14, count 2 2006.201.11:51:10.99#ibcon#about to read 3, iclass 14, count 2 2006.201.11:51:11.01#ibcon#read 3, iclass 14, count 2 2006.201.11:51:11.01#ibcon#about to read 4, iclass 14, count 2 2006.201.11:51:11.01#ibcon#read 4, iclass 14, count 2 2006.201.11:51:11.01#ibcon#about to read 5, iclass 14, count 2 2006.201.11:51:11.01#ibcon#read 5, iclass 14, count 2 2006.201.11:51:11.01#ibcon#about to read 6, iclass 14, count 2 2006.201.11:51:11.01#ibcon#read 6, iclass 14, count 2 2006.201.11:51:11.01#ibcon#end of sib2, iclass 14, count 2 2006.201.11:51:11.01#ibcon#*mode == 0, iclass 14, count 2 2006.201.11:51:11.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.11:51:11.01#ibcon#[27=AT02-05\r\n] 2006.201.11:51:11.01#ibcon#*before write, iclass 14, count 2 2006.201.11:51:11.01#ibcon#enter sib2, iclass 14, count 2 2006.201.11:51:11.01#ibcon#flushed, iclass 14, count 2 2006.201.11:51:11.01#ibcon#about to write, iclass 14, count 2 2006.201.11:51:11.01#ibcon#wrote, iclass 14, count 2 2006.201.11:51:11.01#ibcon#about to read 3, iclass 14, count 2 2006.201.11:51:11.04#ibcon#read 3, iclass 14, count 2 2006.201.11:51:11.04#ibcon#about to read 4, iclass 14, count 2 2006.201.11:51:11.04#ibcon#read 4, iclass 14, count 2 2006.201.11:51:11.04#ibcon#about to read 5, iclass 14, count 2 2006.201.11:51:11.04#ibcon#read 5, iclass 14, count 2 2006.201.11:51:11.04#ibcon#about to read 6, iclass 14, count 2 2006.201.11:51:11.04#ibcon#read 6, iclass 14, count 2 2006.201.11:51:11.04#ibcon#end of sib2, iclass 14, count 2 2006.201.11:51:11.04#ibcon#*after write, iclass 14, count 2 2006.201.11:51:11.04#ibcon#*before return 0, iclass 14, count 2 2006.201.11:51:11.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:11.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.11:51:11.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.11:51:11.04#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:11.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:11.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:11.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:11.16#ibcon#enter wrdev, iclass 14, count 0 2006.201.11:51:11.16#ibcon#first serial, iclass 14, count 0 2006.201.11:51:11.16#ibcon#enter sib2, iclass 14, count 0 2006.201.11:51:11.16#ibcon#flushed, iclass 14, count 0 2006.201.11:51:11.16#ibcon#about to write, iclass 14, count 0 2006.201.11:51:11.16#ibcon#wrote, iclass 14, count 0 2006.201.11:51:11.16#ibcon#about to read 3, iclass 14, count 0 2006.201.11:51:11.18#ibcon#read 3, iclass 14, count 0 2006.201.11:51:11.18#ibcon#about to read 4, iclass 14, count 0 2006.201.11:51:11.18#ibcon#read 4, iclass 14, count 0 2006.201.11:51:11.18#ibcon#about to read 5, iclass 14, count 0 2006.201.11:51:11.18#ibcon#read 5, iclass 14, count 0 2006.201.11:51:11.18#ibcon#about to read 6, iclass 14, count 0 2006.201.11:51:11.18#ibcon#read 6, iclass 14, count 0 2006.201.11:51:11.18#ibcon#end of sib2, iclass 14, count 0 2006.201.11:51:11.18#ibcon#*mode == 0, iclass 14, count 0 2006.201.11:51:11.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.11:51:11.18#ibcon#[27=USB\r\n] 2006.201.11:51:11.18#ibcon#*before write, iclass 14, count 0 2006.201.11:51:11.18#ibcon#enter sib2, iclass 14, count 0 2006.201.11:51:11.18#ibcon#flushed, iclass 14, count 0 2006.201.11:51:11.18#ibcon#about to write, iclass 14, count 0 2006.201.11:51:11.18#ibcon#wrote, iclass 14, count 0 2006.201.11:51:11.18#ibcon#about to read 3, iclass 14, count 0 2006.201.11:51:11.21#ibcon#read 3, iclass 14, count 0 2006.201.11:51:11.21#ibcon#about to read 4, iclass 14, count 0 2006.201.11:51:11.21#ibcon#read 4, iclass 14, count 0 2006.201.11:51:11.21#ibcon#about to read 5, iclass 14, count 0 2006.201.11:51:11.21#ibcon#read 5, iclass 14, count 0 2006.201.11:51:11.21#ibcon#about to read 6, iclass 14, count 0 2006.201.11:51:11.21#ibcon#read 6, iclass 14, count 0 2006.201.11:51:11.21#ibcon#end of sib2, iclass 14, count 0 2006.201.11:51:11.21#ibcon#*after write, iclass 14, count 0 2006.201.11:51:11.21#ibcon#*before return 0, iclass 14, count 0 2006.201.11:51:11.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:11.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.11:51:11.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.11:51:11.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.11:51:11.21$vck44/vblo=3,649.99 2006.201.11:51:11.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.11:51:11.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.11:51:11.21#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:11.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:11.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:11.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:11.21#ibcon#enter wrdev, iclass 16, count 0 2006.201.11:51:11.21#ibcon#first serial, iclass 16, count 0 2006.201.11:51:11.21#ibcon#enter sib2, iclass 16, count 0 2006.201.11:51:11.21#ibcon#flushed, iclass 16, count 0 2006.201.11:51:11.21#ibcon#about to write, iclass 16, count 0 2006.201.11:51:11.21#ibcon#wrote, iclass 16, count 0 2006.201.11:51:11.21#ibcon#about to read 3, iclass 16, count 0 2006.201.11:51:11.23#ibcon#read 3, iclass 16, count 0 2006.201.11:51:11.23#ibcon#about to read 4, iclass 16, count 0 2006.201.11:51:11.23#ibcon#read 4, iclass 16, count 0 2006.201.11:51:11.23#ibcon#about to read 5, iclass 16, count 0 2006.201.11:51:11.23#ibcon#read 5, iclass 16, count 0 2006.201.11:51:11.23#ibcon#about to read 6, iclass 16, count 0 2006.201.11:51:11.23#ibcon#read 6, iclass 16, count 0 2006.201.11:51:11.23#ibcon#end of sib2, iclass 16, count 0 2006.201.11:51:11.23#ibcon#*mode == 0, iclass 16, count 0 2006.201.11:51:11.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.11:51:11.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.11:51:11.23#ibcon#*before write, iclass 16, count 0 2006.201.11:51:11.23#ibcon#enter sib2, iclass 16, count 0 2006.201.11:51:11.23#ibcon#flushed, iclass 16, count 0 2006.201.11:51:11.23#ibcon#about to write, iclass 16, count 0 2006.201.11:51:11.23#ibcon#wrote, iclass 16, count 0 2006.201.11:51:11.23#ibcon#about to read 3, iclass 16, count 0 2006.201.11:51:11.27#ibcon#read 3, iclass 16, count 0 2006.201.11:51:11.27#ibcon#about to read 4, iclass 16, count 0 2006.201.11:51:11.27#ibcon#read 4, iclass 16, count 0 2006.201.11:51:11.27#ibcon#about to read 5, iclass 16, count 0 2006.201.11:51:11.27#ibcon#read 5, iclass 16, count 0 2006.201.11:51:11.27#ibcon#about to read 6, iclass 16, count 0 2006.201.11:51:11.27#ibcon#read 6, iclass 16, count 0 2006.201.11:51:11.27#ibcon#end of sib2, iclass 16, count 0 2006.201.11:51:11.27#ibcon#*after write, iclass 16, count 0 2006.201.11:51:11.27#ibcon#*before return 0, iclass 16, count 0 2006.201.11:51:11.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:11.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.11:51:11.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.11:51:11.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.11:51:11.27$vck44/vb=3,4 2006.201.11:51:11.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.11:51:11.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.11:51:11.27#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:11.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:11.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:11.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:11.33#ibcon#enter wrdev, iclass 18, count 2 2006.201.11:51:11.33#ibcon#first serial, iclass 18, count 2 2006.201.11:51:11.33#ibcon#enter sib2, iclass 18, count 2 2006.201.11:51:11.33#ibcon#flushed, iclass 18, count 2 2006.201.11:51:11.33#ibcon#about to write, iclass 18, count 2 2006.201.11:51:11.33#ibcon#wrote, iclass 18, count 2 2006.201.11:51:11.33#ibcon#about to read 3, iclass 18, count 2 2006.201.11:51:11.35#ibcon#read 3, iclass 18, count 2 2006.201.11:51:11.35#ibcon#about to read 4, iclass 18, count 2 2006.201.11:51:11.35#ibcon#read 4, iclass 18, count 2 2006.201.11:51:11.35#ibcon#about to read 5, iclass 18, count 2 2006.201.11:51:11.35#ibcon#read 5, iclass 18, count 2 2006.201.11:51:11.35#ibcon#about to read 6, iclass 18, count 2 2006.201.11:51:11.35#ibcon#read 6, iclass 18, count 2 2006.201.11:51:11.35#ibcon#end of sib2, iclass 18, count 2 2006.201.11:51:11.35#ibcon#*mode == 0, iclass 18, count 2 2006.201.11:51:11.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.11:51:11.35#ibcon#[27=AT03-04\r\n] 2006.201.11:51:11.35#ibcon#*before write, iclass 18, count 2 2006.201.11:51:11.35#ibcon#enter sib2, iclass 18, count 2 2006.201.11:51:11.35#ibcon#flushed, iclass 18, count 2 2006.201.11:51:11.35#ibcon#about to write, iclass 18, count 2 2006.201.11:51:11.35#ibcon#wrote, iclass 18, count 2 2006.201.11:51:11.35#ibcon#about to read 3, iclass 18, count 2 2006.201.11:51:11.38#ibcon#read 3, iclass 18, count 2 2006.201.11:51:11.38#ibcon#about to read 4, iclass 18, count 2 2006.201.11:51:11.38#ibcon#read 4, iclass 18, count 2 2006.201.11:51:11.38#ibcon#about to read 5, iclass 18, count 2 2006.201.11:51:11.38#ibcon#read 5, iclass 18, count 2 2006.201.11:51:11.38#ibcon#about to read 6, iclass 18, count 2 2006.201.11:51:11.38#ibcon#read 6, iclass 18, count 2 2006.201.11:51:11.38#ibcon#end of sib2, iclass 18, count 2 2006.201.11:51:11.38#ibcon#*after write, iclass 18, count 2 2006.201.11:51:11.38#ibcon#*before return 0, iclass 18, count 2 2006.201.11:51:11.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:11.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.11:51:11.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.11:51:11.38#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:11.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:11.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:11.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:11.50#ibcon#enter wrdev, iclass 18, count 0 2006.201.11:51:11.50#ibcon#first serial, iclass 18, count 0 2006.201.11:51:11.50#ibcon#enter sib2, iclass 18, count 0 2006.201.11:51:11.50#ibcon#flushed, iclass 18, count 0 2006.201.11:51:11.50#ibcon#about to write, iclass 18, count 0 2006.201.11:51:11.50#ibcon#wrote, iclass 18, count 0 2006.201.11:51:11.50#ibcon#about to read 3, iclass 18, count 0 2006.201.11:51:11.52#ibcon#read 3, iclass 18, count 0 2006.201.11:51:11.52#ibcon#about to read 4, iclass 18, count 0 2006.201.11:51:11.52#ibcon#read 4, iclass 18, count 0 2006.201.11:51:11.52#ibcon#about to read 5, iclass 18, count 0 2006.201.11:51:11.52#ibcon#read 5, iclass 18, count 0 2006.201.11:51:11.52#ibcon#about to read 6, iclass 18, count 0 2006.201.11:51:11.52#ibcon#read 6, iclass 18, count 0 2006.201.11:51:11.52#ibcon#end of sib2, iclass 18, count 0 2006.201.11:51:11.52#ibcon#*mode == 0, iclass 18, count 0 2006.201.11:51:11.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.11:51:11.52#ibcon#[27=USB\r\n] 2006.201.11:51:11.52#ibcon#*before write, iclass 18, count 0 2006.201.11:51:11.52#ibcon#enter sib2, iclass 18, count 0 2006.201.11:51:11.52#ibcon#flushed, iclass 18, count 0 2006.201.11:51:11.52#ibcon#about to write, iclass 18, count 0 2006.201.11:51:11.52#ibcon#wrote, iclass 18, count 0 2006.201.11:51:11.52#ibcon#about to read 3, iclass 18, count 0 2006.201.11:51:11.55#ibcon#read 3, iclass 18, count 0 2006.201.11:51:11.55#ibcon#about to read 4, iclass 18, count 0 2006.201.11:51:11.55#ibcon#read 4, iclass 18, count 0 2006.201.11:51:11.55#ibcon#about to read 5, iclass 18, count 0 2006.201.11:51:11.55#ibcon#read 5, iclass 18, count 0 2006.201.11:51:11.55#ibcon#about to read 6, iclass 18, count 0 2006.201.11:51:11.55#ibcon#read 6, iclass 18, count 0 2006.201.11:51:11.55#ibcon#end of sib2, iclass 18, count 0 2006.201.11:51:11.55#ibcon#*after write, iclass 18, count 0 2006.201.11:51:11.55#ibcon#*before return 0, iclass 18, count 0 2006.201.11:51:11.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:11.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.11:51:11.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.11:51:11.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.11:51:11.55$vck44/vblo=4,679.99 2006.201.11:51:11.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.11:51:11.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.11:51:11.55#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:11.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:11.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:11.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:11.55#ibcon#enter wrdev, iclass 20, count 0 2006.201.11:51:11.55#ibcon#first serial, iclass 20, count 0 2006.201.11:51:11.55#ibcon#enter sib2, iclass 20, count 0 2006.201.11:51:11.55#ibcon#flushed, iclass 20, count 0 2006.201.11:51:11.55#ibcon#about to write, iclass 20, count 0 2006.201.11:51:11.55#ibcon#wrote, iclass 20, count 0 2006.201.11:51:11.55#ibcon#about to read 3, iclass 20, count 0 2006.201.11:51:11.57#ibcon#read 3, iclass 20, count 0 2006.201.11:51:11.57#ibcon#about to read 4, iclass 20, count 0 2006.201.11:51:11.57#ibcon#read 4, iclass 20, count 0 2006.201.11:51:11.57#ibcon#about to read 5, iclass 20, count 0 2006.201.11:51:11.57#ibcon#read 5, iclass 20, count 0 2006.201.11:51:11.57#ibcon#about to read 6, iclass 20, count 0 2006.201.11:51:11.57#ibcon#read 6, iclass 20, count 0 2006.201.11:51:11.57#ibcon#end of sib2, iclass 20, count 0 2006.201.11:51:11.57#ibcon#*mode == 0, iclass 20, count 0 2006.201.11:51:11.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.11:51:11.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.11:51:11.57#ibcon#*before write, iclass 20, count 0 2006.201.11:51:11.57#ibcon#enter sib2, iclass 20, count 0 2006.201.11:51:11.57#ibcon#flushed, iclass 20, count 0 2006.201.11:51:11.57#ibcon#about to write, iclass 20, count 0 2006.201.11:51:11.57#ibcon#wrote, iclass 20, count 0 2006.201.11:51:11.57#ibcon#about to read 3, iclass 20, count 0 2006.201.11:51:11.61#ibcon#read 3, iclass 20, count 0 2006.201.11:51:11.61#ibcon#about to read 4, iclass 20, count 0 2006.201.11:51:11.61#ibcon#read 4, iclass 20, count 0 2006.201.11:51:11.61#ibcon#about to read 5, iclass 20, count 0 2006.201.11:51:11.61#ibcon#read 5, iclass 20, count 0 2006.201.11:51:11.61#ibcon#about to read 6, iclass 20, count 0 2006.201.11:51:11.61#ibcon#read 6, iclass 20, count 0 2006.201.11:51:11.61#ibcon#end of sib2, iclass 20, count 0 2006.201.11:51:11.61#ibcon#*after write, iclass 20, count 0 2006.201.11:51:11.61#ibcon#*before return 0, iclass 20, count 0 2006.201.11:51:11.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:11.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.11:51:11.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.11:51:11.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.11:51:11.61$vck44/vb=4,5 2006.201.11:51:11.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.11:51:11.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.11:51:11.61#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:11.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:11.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:11.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:11.67#ibcon#enter wrdev, iclass 22, count 2 2006.201.11:51:11.67#ibcon#first serial, iclass 22, count 2 2006.201.11:51:11.67#ibcon#enter sib2, iclass 22, count 2 2006.201.11:51:11.67#ibcon#flushed, iclass 22, count 2 2006.201.11:51:11.67#ibcon#about to write, iclass 22, count 2 2006.201.11:51:11.67#ibcon#wrote, iclass 22, count 2 2006.201.11:51:11.67#ibcon#about to read 3, iclass 22, count 2 2006.201.11:51:11.69#ibcon#read 3, iclass 22, count 2 2006.201.11:51:11.69#ibcon#about to read 4, iclass 22, count 2 2006.201.11:51:11.69#ibcon#read 4, iclass 22, count 2 2006.201.11:51:11.69#ibcon#about to read 5, iclass 22, count 2 2006.201.11:51:11.69#ibcon#read 5, iclass 22, count 2 2006.201.11:51:11.69#ibcon#about to read 6, iclass 22, count 2 2006.201.11:51:11.69#ibcon#read 6, iclass 22, count 2 2006.201.11:51:11.69#ibcon#end of sib2, iclass 22, count 2 2006.201.11:51:11.69#ibcon#*mode == 0, iclass 22, count 2 2006.201.11:51:11.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.11:51:11.69#ibcon#[27=AT04-05\r\n] 2006.201.11:51:11.69#ibcon#*before write, iclass 22, count 2 2006.201.11:51:11.69#ibcon#enter sib2, iclass 22, count 2 2006.201.11:51:11.69#ibcon#flushed, iclass 22, count 2 2006.201.11:51:11.69#ibcon#about to write, iclass 22, count 2 2006.201.11:51:11.69#ibcon#wrote, iclass 22, count 2 2006.201.11:51:11.69#ibcon#about to read 3, iclass 22, count 2 2006.201.11:51:11.72#ibcon#read 3, iclass 22, count 2 2006.201.11:51:11.72#ibcon#about to read 4, iclass 22, count 2 2006.201.11:51:11.72#ibcon#read 4, iclass 22, count 2 2006.201.11:51:11.72#ibcon#about to read 5, iclass 22, count 2 2006.201.11:51:11.72#ibcon#read 5, iclass 22, count 2 2006.201.11:51:11.72#ibcon#about to read 6, iclass 22, count 2 2006.201.11:51:11.72#ibcon#read 6, iclass 22, count 2 2006.201.11:51:11.72#ibcon#end of sib2, iclass 22, count 2 2006.201.11:51:11.72#ibcon#*after write, iclass 22, count 2 2006.201.11:51:11.72#ibcon#*before return 0, iclass 22, count 2 2006.201.11:51:11.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:11.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.11:51:11.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.11:51:11.72#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:11.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:11.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:11.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:11.84#ibcon#enter wrdev, iclass 22, count 0 2006.201.11:51:11.84#ibcon#first serial, iclass 22, count 0 2006.201.11:51:11.84#ibcon#enter sib2, iclass 22, count 0 2006.201.11:51:11.84#ibcon#flushed, iclass 22, count 0 2006.201.11:51:11.84#ibcon#about to write, iclass 22, count 0 2006.201.11:51:11.84#ibcon#wrote, iclass 22, count 0 2006.201.11:51:11.84#ibcon#about to read 3, iclass 22, count 0 2006.201.11:51:11.86#ibcon#read 3, iclass 22, count 0 2006.201.11:51:11.86#ibcon#about to read 4, iclass 22, count 0 2006.201.11:51:11.86#ibcon#read 4, iclass 22, count 0 2006.201.11:51:11.86#ibcon#about to read 5, iclass 22, count 0 2006.201.11:51:11.86#ibcon#read 5, iclass 22, count 0 2006.201.11:51:11.86#ibcon#about to read 6, iclass 22, count 0 2006.201.11:51:11.86#ibcon#read 6, iclass 22, count 0 2006.201.11:51:11.86#ibcon#end of sib2, iclass 22, count 0 2006.201.11:51:11.86#ibcon#*mode == 0, iclass 22, count 0 2006.201.11:51:11.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.11:51:11.86#ibcon#[27=USB\r\n] 2006.201.11:51:11.86#ibcon#*before write, iclass 22, count 0 2006.201.11:51:11.86#ibcon#enter sib2, iclass 22, count 0 2006.201.11:51:11.86#ibcon#flushed, iclass 22, count 0 2006.201.11:51:11.86#ibcon#about to write, iclass 22, count 0 2006.201.11:51:11.86#ibcon#wrote, iclass 22, count 0 2006.201.11:51:11.86#ibcon#about to read 3, iclass 22, count 0 2006.201.11:51:11.89#ibcon#read 3, iclass 22, count 0 2006.201.11:51:11.89#ibcon#about to read 4, iclass 22, count 0 2006.201.11:51:11.89#ibcon#read 4, iclass 22, count 0 2006.201.11:51:11.89#ibcon#about to read 5, iclass 22, count 0 2006.201.11:51:11.89#ibcon#read 5, iclass 22, count 0 2006.201.11:51:11.89#ibcon#about to read 6, iclass 22, count 0 2006.201.11:51:11.89#ibcon#read 6, iclass 22, count 0 2006.201.11:51:11.89#ibcon#end of sib2, iclass 22, count 0 2006.201.11:51:11.89#ibcon#*after write, iclass 22, count 0 2006.201.11:51:11.89#ibcon#*before return 0, iclass 22, count 0 2006.201.11:51:11.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:11.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.11:51:11.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.11:51:11.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.11:51:11.89$vck44/vblo=5,709.99 2006.201.11:51:11.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.11:51:11.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.11:51:11.89#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:11.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:11.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:11.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:11.89#ibcon#enter wrdev, iclass 24, count 0 2006.201.11:51:11.89#ibcon#first serial, iclass 24, count 0 2006.201.11:51:11.89#ibcon#enter sib2, iclass 24, count 0 2006.201.11:51:11.89#ibcon#flushed, iclass 24, count 0 2006.201.11:51:11.89#ibcon#about to write, iclass 24, count 0 2006.201.11:51:11.89#ibcon#wrote, iclass 24, count 0 2006.201.11:51:11.89#ibcon#about to read 3, iclass 24, count 0 2006.201.11:51:11.91#ibcon#read 3, iclass 24, count 0 2006.201.11:51:11.91#ibcon#about to read 4, iclass 24, count 0 2006.201.11:51:11.91#ibcon#read 4, iclass 24, count 0 2006.201.11:51:11.91#ibcon#about to read 5, iclass 24, count 0 2006.201.11:51:11.91#ibcon#read 5, iclass 24, count 0 2006.201.11:51:11.91#ibcon#about to read 6, iclass 24, count 0 2006.201.11:51:11.91#ibcon#read 6, iclass 24, count 0 2006.201.11:51:11.91#ibcon#end of sib2, iclass 24, count 0 2006.201.11:51:11.91#ibcon#*mode == 0, iclass 24, count 0 2006.201.11:51:11.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.11:51:11.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.11:51:11.91#ibcon#*before write, iclass 24, count 0 2006.201.11:51:11.91#ibcon#enter sib2, iclass 24, count 0 2006.201.11:51:11.91#ibcon#flushed, iclass 24, count 0 2006.201.11:51:11.91#ibcon#about to write, iclass 24, count 0 2006.201.11:51:11.91#ibcon#wrote, iclass 24, count 0 2006.201.11:51:11.91#ibcon#about to read 3, iclass 24, count 0 2006.201.11:51:11.96#ibcon#read 3, iclass 24, count 0 2006.201.11:51:11.96#ibcon#about to read 4, iclass 24, count 0 2006.201.11:51:11.96#ibcon#read 4, iclass 24, count 0 2006.201.11:51:11.96#ibcon#about to read 5, iclass 24, count 0 2006.201.11:51:11.96#ibcon#read 5, iclass 24, count 0 2006.201.11:51:11.96#ibcon#about to read 6, iclass 24, count 0 2006.201.11:51:11.96#ibcon#read 6, iclass 24, count 0 2006.201.11:51:11.96#ibcon#end of sib2, iclass 24, count 0 2006.201.11:51:11.96#ibcon#*after write, iclass 24, count 0 2006.201.11:51:11.96#ibcon#*before return 0, iclass 24, count 0 2006.201.11:51:11.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:11.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.11:51:11.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.11:51:11.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.11:51:11.96$vck44/vb=5,4 2006.201.11:51:11.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.11:51:11.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.11:51:11.96#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:11.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:12.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:12.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:12.01#ibcon#enter wrdev, iclass 26, count 2 2006.201.11:51:12.01#ibcon#first serial, iclass 26, count 2 2006.201.11:51:12.01#ibcon#enter sib2, iclass 26, count 2 2006.201.11:51:12.01#ibcon#flushed, iclass 26, count 2 2006.201.11:51:12.01#ibcon#about to write, iclass 26, count 2 2006.201.11:51:12.01#ibcon#wrote, iclass 26, count 2 2006.201.11:51:12.01#ibcon#about to read 3, iclass 26, count 2 2006.201.11:51:12.03#ibcon#read 3, iclass 26, count 2 2006.201.11:51:12.03#ibcon#about to read 4, iclass 26, count 2 2006.201.11:51:12.03#ibcon#read 4, iclass 26, count 2 2006.201.11:51:12.03#ibcon#about to read 5, iclass 26, count 2 2006.201.11:51:12.03#ibcon#read 5, iclass 26, count 2 2006.201.11:51:12.03#ibcon#about to read 6, iclass 26, count 2 2006.201.11:51:12.03#ibcon#read 6, iclass 26, count 2 2006.201.11:51:12.03#ibcon#end of sib2, iclass 26, count 2 2006.201.11:51:12.03#ibcon#*mode == 0, iclass 26, count 2 2006.201.11:51:12.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.11:51:12.03#ibcon#[27=AT05-04\r\n] 2006.201.11:51:12.03#ibcon#*before write, iclass 26, count 2 2006.201.11:51:12.03#ibcon#enter sib2, iclass 26, count 2 2006.201.11:51:12.03#ibcon#flushed, iclass 26, count 2 2006.201.11:51:12.03#ibcon#about to write, iclass 26, count 2 2006.201.11:51:12.03#ibcon#wrote, iclass 26, count 2 2006.201.11:51:12.03#ibcon#about to read 3, iclass 26, count 2 2006.201.11:51:12.06#ibcon#read 3, iclass 26, count 2 2006.201.11:51:12.06#ibcon#about to read 4, iclass 26, count 2 2006.201.11:51:12.06#ibcon#read 4, iclass 26, count 2 2006.201.11:51:12.06#ibcon#about to read 5, iclass 26, count 2 2006.201.11:51:12.06#ibcon#read 5, iclass 26, count 2 2006.201.11:51:12.06#ibcon#about to read 6, iclass 26, count 2 2006.201.11:51:12.06#ibcon#read 6, iclass 26, count 2 2006.201.11:51:12.06#ibcon#end of sib2, iclass 26, count 2 2006.201.11:51:12.06#ibcon#*after write, iclass 26, count 2 2006.201.11:51:12.06#ibcon#*before return 0, iclass 26, count 2 2006.201.11:51:12.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:12.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.11:51:12.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.11:51:12.06#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:12.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:12.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:12.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:12.18#ibcon#enter wrdev, iclass 26, count 0 2006.201.11:51:12.18#ibcon#first serial, iclass 26, count 0 2006.201.11:51:12.18#ibcon#enter sib2, iclass 26, count 0 2006.201.11:51:12.18#ibcon#flushed, iclass 26, count 0 2006.201.11:51:12.18#ibcon#about to write, iclass 26, count 0 2006.201.11:51:12.18#ibcon#wrote, iclass 26, count 0 2006.201.11:51:12.18#ibcon#about to read 3, iclass 26, count 0 2006.201.11:51:12.21#ibcon#read 3, iclass 26, count 0 2006.201.11:51:12.21#ibcon#about to read 4, iclass 26, count 0 2006.201.11:51:12.21#ibcon#read 4, iclass 26, count 0 2006.201.11:51:12.21#ibcon#about to read 5, iclass 26, count 0 2006.201.11:51:12.21#ibcon#read 5, iclass 26, count 0 2006.201.11:51:12.21#ibcon#about to read 6, iclass 26, count 0 2006.201.11:51:12.21#ibcon#read 6, iclass 26, count 0 2006.201.11:51:12.21#ibcon#end of sib2, iclass 26, count 0 2006.201.11:51:12.21#ibcon#*mode == 0, iclass 26, count 0 2006.201.11:51:12.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.11:51:12.21#ibcon#[27=USB\r\n] 2006.201.11:51:12.21#ibcon#*before write, iclass 26, count 0 2006.201.11:51:12.21#ibcon#enter sib2, iclass 26, count 0 2006.201.11:51:12.21#ibcon#flushed, iclass 26, count 0 2006.201.11:51:12.21#ibcon#about to write, iclass 26, count 0 2006.201.11:51:12.21#ibcon#wrote, iclass 26, count 0 2006.201.11:51:12.21#ibcon#about to read 3, iclass 26, count 0 2006.201.11:51:12.24#ibcon#read 3, iclass 26, count 0 2006.201.11:51:12.24#ibcon#about to read 4, iclass 26, count 0 2006.201.11:51:12.24#ibcon#read 4, iclass 26, count 0 2006.201.11:51:12.24#ibcon#about to read 5, iclass 26, count 0 2006.201.11:51:12.24#ibcon#read 5, iclass 26, count 0 2006.201.11:51:12.24#ibcon#about to read 6, iclass 26, count 0 2006.201.11:51:12.24#ibcon#read 6, iclass 26, count 0 2006.201.11:51:12.24#ibcon#end of sib2, iclass 26, count 0 2006.201.11:51:12.24#ibcon#*after write, iclass 26, count 0 2006.201.11:51:12.24#ibcon#*before return 0, iclass 26, count 0 2006.201.11:51:12.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:12.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.11:51:12.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.11:51:12.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.11:51:12.24$vck44/vblo=6,719.99 2006.201.11:51:12.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.11:51:12.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.11:51:12.24#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:12.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:12.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:12.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:12.24#ibcon#enter wrdev, iclass 28, count 0 2006.201.11:51:12.24#ibcon#first serial, iclass 28, count 0 2006.201.11:51:12.24#ibcon#enter sib2, iclass 28, count 0 2006.201.11:51:12.24#ibcon#flushed, iclass 28, count 0 2006.201.11:51:12.24#ibcon#about to write, iclass 28, count 0 2006.201.11:51:12.24#ibcon#wrote, iclass 28, count 0 2006.201.11:51:12.24#ibcon#about to read 3, iclass 28, count 0 2006.201.11:51:12.26#ibcon#read 3, iclass 28, count 0 2006.201.11:51:12.26#ibcon#about to read 4, iclass 28, count 0 2006.201.11:51:12.26#ibcon#read 4, iclass 28, count 0 2006.201.11:51:12.26#ibcon#about to read 5, iclass 28, count 0 2006.201.11:51:12.26#ibcon#read 5, iclass 28, count 0 2006.201.11:51:12.26#ibcon#about to read 6, iclass 28, count 0 2006.201.11:51:12.26#ibcon#read 6, iclass 28, count 0 2006.201.11:51:12.26#ibcon#end of sib2, iclass 28, count 0 2006.201.11:51:12.26#ibcon#*mode == 0, iclass 28, count 0 2006.201.11:51:12.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.11:51:12.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.11:51:12.26#ibcon#*before write, iclass 28, count 0 2006.201.11:51:12.26#ibcon#enter sib2, iclass 28, count 0 2006.201.11:51:12.26#ibcon#flushed, iclass 28, count 0 2006.201.11:51:12.26#ibcon#about to write, iclass 28, count 0 2006.201.11:51:12.26#ibcon#wrote, iclass 28, count 0 2006.201.11:51:12.26#ibcon#about to read 3, iclass 28, count 0 2006.201.11:51:12.30#ibcon#read 3, iclass 28, count 0 2006.201.11:51:12.30#ibcon#about to read 4, iclass 28, count 0 2006.201.11:51:12.30#ibcon#read 4, iclass 28, count 0 2006.201.11:51:12.30#ibcon#about to read 5, iclass 28, count 0 2006.201.11:51:12.30#ibcon#read 5, iclass 28, count 0 2006.201.11:51:12.30#ibcon#about to read 6, iclass 28, count 0 2006.201.11:51:12.30#ibcon#read 6, iclass 28, count 0 2006.201.11:51:12.30#ibcon#end of sib2, iclass 28, count 0 2006.201.11:51:12.30#ibcon#*after write, iclass 28, count 0 2006.201.11:51:12.30#ibcon#*before return 0, iclass 28, count 0 2006.201.11:51:12.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:12.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.11:51:12.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.11:51:12.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.11:51:12.30$vck44/vb=6,4 2006.201.11:51:12.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.11:51:12.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.11:51:12.30#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:12.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:12.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:12.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:12.36#ibcon#enter wrdev, iclass 30, count 2 2006.201.11:51:12.36#ibcon#first serial, iclass 30, count 2 2006.201.11:51:12.36#ibcon#enter sib2, iclass 30, count 2 2006.201.11:51:12.36#ibcon#flushed, iclass 30, count 2 2006.201.11:51:12.36#ibcon#about to write, iclass 30, count 2 2006.201.11:51:12.36#ibcon#wrote, iclass 30, count 2 2006.201.11:51:12.36#ibcon#about to read 3, iclass 30, count 2 2006.201.11:51:12.38#ibcon#read 3, iclass 30, count 2 2006.201.11:51:12.38#ibcon#about to read 4, iclass 30, count 2 2006.201.11:51:12.38#ibcon#read 4, iclass 30, count 2 2006.201.11:51:12.38#ibcon#about to read 5, iclass 30, count 2 2006.201.11:51:12.38#ibcon#read 5, iclass 30, count 2 2006.201.11:51:12.38#ibcon#about to read 6, iclass 30, count 2 2006.201.11:51:12.38#ibcon#read 6, iclass 30, count 2 2006.201.11:51:12.38#ibcon#end of sib2, iclass 30, count 2 2006.201.11:51:12.38#ibcon#*mode == 0, iclass 30, count 2 2006.201.11:51:12.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.11:51:12.38#ibcon#[27=AT06-04\r\n] 2006.201.11:51:12.38#ibcon#*before write, iclass 30, count 2 2006.201.11:51:12.38#ibcon#enter sib2, iclass 30, count 2 2006.201.11:51:12.38#ibcon#flushed, iclass 30, count 2 2006.201.11:51:12.38#ibcon#about to write, iclass 30, count 2 2006.201.11:51:12.38#ibcon#wrote, iclass 30, count 2 2006.201.11:51:12.38#ibcon#about to read 3, iclass 30, count 2 2006.201.11:51:12.41#ibcon#read 3, iclass 30, count 2 2006.201.11:51:12.41#ibcon#about to read 4, iclass 30, count 2 2006.201.11:51:12.41#ibcon#read 4, iclass 30, count 2 2006.201.11:51:12.41#ibcon#about to read 5, iclass 30, count 2 2006.201.11:51:12.41#ibcon#read 5, iclass 30, count 2 2006.201.11:51:12.41#ibcon#about to read 6, iclass 30, count 2 2006.201.11:51:12.41#ibcon#read 6, iclass 30, count 2 2006.201.11:51:12.41#ibcon#end of sib2, iclass 30, count 2 2006.201.11:51:12.41#ibcon#*after write, iclass 30, count 2 2006.201.11:51:12.41#ibcon#*before return 0, iclass 30, count 2 2006.201.11:51:12.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:12.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.11:51:12.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.11:51:12.41#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:12.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:12.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:12.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:12.53#ibcon#enter wrdev, iclass 30, count 0 2006.201.11:51:12.53#ibcon#first serial, iclass 30, count 0 2006.201.11:51:12.53#ibcon#enter sib2, iclass 30, count 0 2006.201.11:51:12.53#ibcon#flushed, iclass 30, count 0 2006.201.11:51:12.53#ibcon#about to write, iclass 30, count 0 2006.201.11:51:12.53#ibcon#wrote, iclass 30, count 0 2006.201.11:51:12.53#ibcon#about to read 3, iclass 30, count 0 2006.201.11:51:12.55#ibcon#read 3, iclass 30, count 0 2006.201.11:51:12.55#ibcon#about to read 4, iclass 30, count 0 2006.201.11:51:12.55#ibcon#read 4, iclass 30, count 0 2006.201.11:51:12.55#ibcon#about to read 5, iclass 30, count 0 2006.201.11:51:12.55#ibcon#read 5, iclass 30, count 0 2006.201.11:51:12.55#ibcon#about to read 6, iclass 30, count 0 2006.201.11:51:12.55#ibcon#read 6, iclass 30, count 0 2006.201.11:51:12.55#ibcon#end of sib2, iclass 30, count 0 2006.201.11:51:12.55#ibcon#*mode == 0, iclass 30, count 0 2006.201.11:51:12.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.11:51:12.55#ibcon#[27=USB\r\n] 2006.201.11:51:12.55#ibcon#*before write, iclass 30, count 0 2006.201.11:51:12.55#ibcon#enter sib2, iclass 30, count 0 2006.201.11:51:12.55#ibcon#flushed, iclass 30, count 0 2006.201.11:51:12.55#ibcon#about to write, iclass 30, count 0 2006.201.11:51:12.55#ibcon#wrote, iclass 30, count 0 2006.201.11:51:12.55#ibcon#about to read 3, iclass 30, count 0 2006.201.11:51:12.58#ibcon#read 3, iclass 30, count 0 2006.201.11:51:12.58#ibcon#about to read 4, iclass 30, count 0 2006.201.11:51:12.58#ibcon#read 4, iclass 30, count 0 2006.201.11:51:12.58#ibcon#about to read 5, iclass 30, count 0 2006.201.11:51:12.58#ibcon#read 5, iclass 30, count 0 2006.201.11:51:12.58#ibcon#about to read 6, iclass 30, count 0 2006.201.11:51:12.58#ibcon#read 6, iclass 30, count 0 2006.201.11:51:12.58#ibcon#end of sib2, iclass 30, count 0 2006.201.11:51:12.58#ibcon#*after write, iclass 30, count 0 2006.201.11:51:12.58#ibcon#*before return 0, iclass 30, count 0 2006.201.11:51:12.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:12.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.11:51:12.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.11:51:12.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.11:51:12.58$vck44/vblo=7,734.99 2006.201.11:51:12.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.11:51:12.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.11:51:12.58#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:12.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:12.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:12.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:12.58#ibcon#enter wrdev, iclass 32, count 0 2006.201.11:51:12.58#ibcon#first serial, iclass 32, count 0 2006.201.11:51:12.58#ibcon#enter sib2, iclass 32, count 0 2006.201.11:51:12.58#ibcon#flushed, iclass 32, count 0 2006.201.11:51:12.58#ibcon#about to write, iclass 32, count 0 2006.201.11:51:12.58#ibcon#wrote, iclass 32, count 0 2006.201.11:51:12.58#ibcon#about to read 3, iclass 32, count 0 2006.201.11:51:12.60#ibcon#read 3, iclass 32, count 0 2006.201.11:51:12.60#ibcon#about to read 4, iclass 32, count 0 2006.201.11:51:12.60#ibcon#read 4, iclass 32, count 0 2006.201.11:51:12.60#ibcon#about to read 5, iclass 32, count 0 2006.201.11:51:12.60#ibcon#read 5, iclass 32, count 0 2006.201.11:51:12.60#ibcon#about to read 6, iclass 32, count 0 2006.201.11:51:12.60#ibcon#read 6, iclass 32, count 0 2006.201.11:51:12.60#ibcon#end of sib2, iclass 32, count 0 2006.201.11:51:12.60#ibcon#*mode == 0, iclass 32, count 0 2006.201.11:51:12.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.11:51:12.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.11:51:12.60#ibcon#*before write, iclass 32, count 0 2006.201.11:51:12.60#ibcon#enter sib2, iclass 32, count 0 2006.201.11:51:12.60#ibcon#flushed, iclass 32, count 0 2006.201.11:51:12.60#ibcon#about to write, iclass 32, count 0 2006.201.11:51:12.60#ibcon#wrote, iclass 32, count 0 2006.201.11:51:12.60#ibcon#about to read 3, iclass 32, count 0 2006.201.11:51:12.64#ibcon#read 3, iclass 32, count 0 2006.201.11:51:12.64#ibcon#about to read 4, iclass 32, count 0 2006.201.11:51:12.64#ibcon#read 4, iclass 32, count 0 2006.201.11:51:12.64#ibcon#about to read 5, iclass 32, count 0 2006.201.11:51:12.64#ibcon#read 5, iclass 32, count 0 2006.201.11:51:12.64#ibcon#about to read 6, iclass 32, count 0 2006.201.11:51:12.64#ibcon#read 6, iclass 32, count 0 2006.201.11:51:12.64#ibcon#end of sib2, iclass 32, count 0 2006.201.11:51:12.64#ibcon#*after write, iclass 32, count 0 2006.201.11:51:12.64#ibcon#*before return 0, iclass 32, count 0 2006.201.11:51:12.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:12.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.11:51:12.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.11:51:12.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.11:51:12.64$vck44/vb=7,4 2006.201.11:51:12.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.11:51:12.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.11:51:12.64#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:12.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:12.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:12.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:12.70#ibcon#enter wrdev, iclass 34, count 2 2006.201.11:51:12.70#ibcon#first serial, iclass 34, count 2 2006.201.11:51:12.70#ibcon#enter sib2, iclass 34, count 2 2006.201.11:51:12.70#ibcon#flushed, iclass 34, count 2 2006.201.11:51:12.70#ibcon#about to write, iclass 34, count 2 2006.201.11:51:12.70#ibcon#wrote, iclass 34, count 2 2006.201.11:51:12.70#ibcon#about to read 3, iclass 34, count 2 2006.201.11:51:12.72#ibcon#read 3, iclass 34, count 2 2006.201.11:51:12.72#ibcon#about to read 4, iclass 34, count 2 2006.201.11:51:12.72#ibcon#read 4, iclass 34, count 2 2006.201.11:51:12.72#ibcon#about to read 5, iclass 34, count 2 2006.201.11:51:12.72#ibcon#read 5, iclass 34, count 2 2006.201.11:51:12.72#ibcon#about to read 6, iclass 34, count 2 2006.201.11:51:12.72#ibcon#read 6, iclass 34, count 2 2006.201.11:51:12.72#ibcon#end of sib2, iclass 34, count 2 2006.201.11:51:12.72#ibcon#*mode == 0, iclass 34, count 2 2006.201.11:51:12.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.11:51:12.72#ibcon#[27=AT07-04\r\n] 2006.201.11:51:12.72#ibcon#*before write, iclass 34, count 2 2006.201.11:51:12.72#ibcon#enter sib2, iclass 34, count 2 2006.201.11:51:12.72#ibcon#flushed, iclass 34, count 2 2006.201.11:51:12.72#ibcon#about to write, iclass 34, count 2 2006.201.11:51:12.72#ibcon#wrote, iclass 34, count 2 2006.201.11:51:12.72#ibcon#about to read 3, iclass 34, count 2 2006.201.11:51:12.75#ibcon#read 3, iclass 34, count 2 2006.201.11:51:12.75#ibcon#about to read 4, iclass 34, count 2 2006.201.11:51:12.75#ibcon#read 4, iclass 34, count 2 2006.201.11:51:12.75#ibcon#about to read 5, iclass 34, count 2 2006.201.11:51:12.75#ibcon#read 5, iclass 34, count 2 2006.201.11:51:12.75#ibcon#about to read 6, iclass 34, count 2 2006.201.11:51:12.75#ibcon#read 6, iclass 34, count 2 2006.201.11:51:12.75#ibcon#end of sib2, iclass 34, count 2 2006.201.11:51:12.75#ibcon#*after write, iclass 34, count 2 2006.201.11:51:12.75#ibcon#*before return 0, iclass 34, count 2 2006.201.11:51:12.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:12.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.11:51:12.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.11:51:12.75#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:12.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:12.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:12.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:12.87#ibcon#enter wrdev, iclass 34, count 0 2006.201.11:51:12.87#ibcon#first serial, iclass 34, count 0 2006.201.11:51:12.87#ibcon#enter sib2, iclass 34, count 0 2006.201.11:51:12.87#ibcon#flushed, iclass 34, count 0 2006.201.11:51:12.87#ibcon#about to write, iclass 34, count 0 2006.201.11:51:12.87#ibcon#wrote, iclass 34, count 0 2006.201.11:51:12.87#ibcon#about to read 3, iclass 34, count 0 2006.201.11:51:12.89#ibcon#read 3, iclass 34, count 0 2006.201.11:51:12.89#ibcon#about to read 4, iclass 34, count 0 2006.201.11:51:12.89#ibcon#read 4, iclass 34, count 0 2006.201.11:51:12.89#ibcon#about to read 5, iclass 34, count 0 2006.201.11:51:12.89#ibcon#read 5, iclass 34, count 0 2006.201.11:51:12.89#ibcon#about to read 6, iclass 34, count 0 2006.201.11:51:12.89#ibcon#read 6, iclass 34, count 0 2006.201.11:51:12.89#ibcon#end of sib2, iclass 34, count 0 2006.201.11:51:12.89#ibcon#*mode == 0, iclass 34, count 0 2006.201.11:51:12.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.11:51:12.89#ibcon#[27=USB\r\n] 2006.201.11:51:12.89#ibcon#*before write, iclass 34, count 0 2006.201.11:51:12.89#ibcon#enter sib2, iclass 34, count 0 2006.201.11:51:12.89#ibcon#flushed, iclass 34, count 0 2006.201.11:51:12.89#ibcon#about to write, iclass 34, count 0 2006.201.11:51:12.89#ibcon#wrote, iclass 34, count 0 2006.201.11:51:12.89#ibcon#about to read 3, iclass 34, count 0 2006.201.11:51:12.92#ibcon#read 3, iclass 34, count 0 2006.201.11:51:12.92#ibcon#about to read 4, iclass 34, count 0 2006.201.11:51:12.92#ibcon#read 4, iclass 34, count 0 2006.201.11:51:12.92#ibcon#about to read 5, iclass 34, count 0 2006.201.11:51:12.92#ibcon#read 5, iclass 34, count 0 2006.201.11:51:12.92#ibcon#about to read 6, iclass 34, count 0 2006.201.11:51:12.92#ibcon#read 6, iclass 34, count 0 2006.201.11:51:12.92#ibcon#end of sib2, iclass 34, count 0 2006.201.11:51:12.92#ibcon#*after write, iclass 34, count 0 2006.201.11:51:12.92#ibcon#*before return 0, iclass 34, count 0 2006.201.11:51:12.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:12.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.11:51:12.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.11:51:12.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.11:51:12.92$vck44/vblo=8,744.99 2006.201.11:51:12.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.11:51:12.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.11:51:12.92#ibcon#ireg 17 cls_cnt 0 2006.201.11:51:12.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:12.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:12.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:12.92#ibcon#enter wrdev, iclass 36, count 0 2006.201.11:51:12.92#ibcon#first serial, iclass 36, count 0 2006.201.11:51:12.92#ibcon#enter sib2, iclass 36, count 0 2006.201.11:51:12.92#ibcon#flushed, iclass 36, count 0 2006.201.11:51:12.92#ibcon#about to write, iclass 36, count 0 2006.201.11:51:12.92#ibcon#wrote, iclass 36, count 0 2006.201.11:51:12.92#ibcon#about to read 3, iclass 36, count 0 2006.201.11:51:12.94#ibcon#read 3, iclass 36, count 0 2006.201.11:51:12.94#ibcon#about to read 4, iclass 36, count 0 2006.201.11:51:12.94#ibcon#read 4, iclass 36, count 0 2006.201.11:51:12.94#ibcon#about to read 5, iclass 36, count 0 2006.201.11:51:12.94#ibcon#read 5, iclass 36, count 0 2006.201.11:51:12.94#ibcon#about to read 6, iclass 36, count 0 2006.201.11:51:12.94#ibcon#read 6, iclass 36, count 0 2006.201.11:51:12.94#ibcon#end of sib2, iclass 36, count 0 2006.201.11:51:12.94#ibcon#*mode == 0, iclass 36, count 0 2006.201.11:51:12.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.11:51:12.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.11:51:12.94#ibcon#*before write, iclass 36, count 0 2006.201.11:51:12.94#ibcon#enter sib2, iclass 36, count 0 2006.201.11:51:12.94#ibcon#flushed, iclass 36, count 0 2006.201.11:51:12.94#ibcon#about to write, iclass 36, count 0 2006.201.11:51:12.94#ibcon#wrote, iclass 36, count 0 2006.201.11:51:12.94#ibcon#about to read 3, iclass 36, count 0 2006.201.11:51:12.99#ibcon#read 3, iclass 36, count 0 2006.201.11:51:12.99#ibcon#about to read 4, iclass 36, count 0 2006.201.11:51:12.99#ibcon#read 4, iclass 36, count 0 2006.201.11:51:12.99#ibcon#about to read 5, iclass 36, count 0 2006.201.11:51:12.99#ibcon#read 5, iclass 36, count 0 2006.201.11:51:12.99#ibcon#about to read 6, iclass 36, count 0 2006.201.11:51:12.99#ibcon#read 6, iclass 36, count 0 2006.201.11:51:12.99#ibcon#end of sib2, iclass 36, count 0 2006.201.11:51:12.99#ibcon#*after write, iclass 36, count 0 2006.201.11:51:12.99#ibcon#*before return 0, iclass 36, count 0 2006.201.11:51:12.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:12.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.11:51:12.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.11:51:12.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.11:51:12.99$vck44/vb=8,4 2006.201.11:51:12.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.11:51:12.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.11:51:12.99#ibcon#ireg 11 cls_cnt 2 2006.201.11:51:12.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:13.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:13.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:13.04#ibcon#enter wrdev, iclass 38, count 2 2006.201.11:51:13.04#ibcon#first serial, iclass 38, count 2 2006.201.11:51:13.04#ibcon#enter sib2, iclass 38, count 2 2006.201.11:51:13.04#ibcon#flushed, iclass 38, count 2 2006.201.11:51:13.04#ibcon#about to write, iclass 38, count 2 2006.201.11:51:13.04#ibcon#wrote, iclass 38, count 2 2006.201.11:51:13.04#ibcon#about to read 3, iclass 38, count 2 2006.201.11:51:13.06#ibcon#read 3, iclass 38, count 2 2006.201.11:51:13.06#ibcon#about to read 4, iclass 38, count 2 2006.201.11:51:13.06#ibcon#read 4, iclass 38, count 2 2006.201.11:51:13.06#ibcon#about to read 5, iclass 38, count 2 2006.201.11:51:13.06#ibcon#read 5, iclass 38, count 2 2006.201.11:51:13.06#ibcon#about to read 6, iclass 38, count 2 2006.201.11:51:13.06#ibcon#read 6, iclass 38, count 2 2006.201.11:51:13.06#ibcon#end of sib2, iclass 38, count 2 2006.201.11:51:13.06#ibcon#*mode == 0, iclass 38, count 2 2006.201.11:51:13.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.11:51:13.06#ibcon#[27=AT08-04\r\n] 2006.201.11:51:13.06#ibcon#*before write, iclass 38, count 2 2006.201.11:51:13.06#ibcon#enter sib2, iclass 38, count 2 2006.201.11:51:13.06#ibcon#flushed, iclass 38, count 2 2006.201.11:51:13.06#ibcon#about to write, iclass 38, count 2 2006.201.11:51:13.06#ibcon#wrote, iclass 38, count 2 2006.201.11:51:13.06#ibcon#about to read 3, iclass 38, count 2 2006.201.11:51:13.09#ibcon#read 3, iclass 38, count 2 2006.201.11:51:13.09#ibcon#about to read 4, iclass 38, count 2 2006.201.11:51:13.09#ibcon#read 4, iclass 38, count 2 2006.201.11:51:13.09#ibcon#about to read 5, iclass 38, count 2 2006.201.11:51:13.09#ibcon#read 5, iclass 38, count 2 2006.201.11:51:13.09#ibcon#about to read 6, iclass 38, count 2 2006.201.11:51:13.09#ibcon#read 6, iclass 38, count 2 2006.201.11:51:13.09#ibcon#end of sib2, iclass 38, count 2 2006.201.11:51:13.09#ibcon#*after write, iclass 38, count 2 2006.201.11:51:13.09#ibcon#*before return 0, iclass 38, count 2 2006.201.11:51:13.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:13.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.11:51:13.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.11:51:13.09#ibcon#ireg 7 cls_cnt 0 2006.201.11:51:13.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:13.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:13.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:13.21#ibcon#enter wrdev, iclass 38, count 0 2006.201.11:51:13.21#ibcon#first serial, iclass 38, count 0 2006.201.11:51:13.21#ibcon#enter sib2, iclass 38, count 0 2006.201.11:51:13.21#ibcon#flushed, iclass 38, count 0 2006.201.11:51:13.21#ibcon#about to write, iclass 38, count 0 2006.201.11:51:13.21#ibcon#wrote, iclass 38, count 0 2006.201.11:51:13.21#ibcon#about to read 3, iclass 38, count 0 2006.201.11:51:13.23#ibcon#read 3, iclass 38, count 0 2006.201.11:51:13.23#ibcon#about to read 4, iclass 38, count 0 2006.201.11:51:13.23#ibcon#read 4, iclass 38, count 0 2006.201.11:51:13.23#ibcon#about to read 5, iclass 38, count 0 2006.201.11:51:13.23#ibcon#read 5, iclass 38, count 0 2006.201.11:51:13.23#ibcon#about to read 6, iclass 38, count 0 2006.201.11:51:13.23#ibcon#read 6, iclass 38, count 0 2006.201.11:51:13.23#ibcon#end of sib2, iclass 38, count 0 2006.201.11:51:13.23#ibcon#*mode == 0, iclass 38, count 0 2006.201.11:51:13.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.11:51:13.23#ibcon#[27=USB\r\n] 2006.201.11:51:13.23#ibcon#*before write, iclass 38, count 0 2006.201.11:51:13.23#ibcon#enter sib2, iclass 38, count 0 2006.201.11:51:13.23#ibcon#flushed, iclass 38, count 0 2006.201.11:51:13.23#ibcon#about to write, iclass 38, count 0 2006.201.11:51:13.23#ibcon#wrote, iclass 38, count 0 2006.201.11:51:13.23#ibcon#about to read 3, iclass 38, count 0 2006.201.11:51:13.26#ibcon#read 3, iclass 38, count 0 2006.201.11:51:13.26#ibcon#about to read 4, iclass 38, count 0 2006.201.11:51:13.26#ibcon#read 4, iclass 38, count 0 2006.201.11:51:13.26#ibcon#about to read 5, iclass 38, count 0 2006.201.11:51:13.26#ibcon#read 5, iclass 38, count 0 2006.201.11:51:13.26#ibcon#about to read 6, iclass 38, count 0 2006.201.11:51:13.26#ibcon#read 6, iclass 38, count 0 2006.201.11:51:13.26#ibcon#end of sib2, iclass 38, count 0 2006.201.11:51:13.26#ibcon#*after write, iclass 38, count 0 2006.201.11:51:13.26#ibcon#*before return 0, iclass 38, count 0 2006.201.11:51:13.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:13.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.11:51:13.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.11:51:13.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.11:51:13.26$vck44/vabw=wide 2006.201.11:51:13.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.11:51:13.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.11:51:13.26#ibcon#ireg 8 cls_cnt 0 2006.201.11:51:13.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:13.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:13.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:13.26#ibcon#enter wrdev, iclass 40, count 0 2006.201.11:51:13.26#ibcon#first serial, iclass 40, count 0 2006.201.11:51:13.26#ibcon#enter sib2, iclass 40, count 0 2006.201.11:51:13.26#ibcon#flushed, iclass 40, count 0 2006.201.11:51:13.26#ibcon#about to write, iclass 40, count 0 2006.201.11:51:13.26#ibcon#wrote, iclass 40, count 0 2006.201.11:51:13.26#ibcon#about to read 3, iclass 40, count 0 2006.201.11:51:13.28#ibcon#read 3, iclass 40, count 0 2006.201.11:51:13.28#ibcon#about to read 4, iclass 40, count 0 2006.201.11:51:13.28#ibcon#read 4, iclass 40, count 0 2006.201.11:51:13.28#ibcon#about to read 5, iclass 40, count 0 2006.201.11:51:13.28#ibcon#read 5, iclass 40, count 0 2006.201.11:51:13.28#ibcon#about to read 6, iclass 40, count 0 2006.201.11:51:13.28#ibcon#read 6, iclass 40, count 0 2006.201.11:51:13.28#ibcon#end of sib2, iclass 40, count 0 2006.201.11:51:13.28#ibcon#*mode == 0, iclass 40, count 0 2006.201.11:51:13.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.11:51:13.28#ibcon#[25=BW32\r\n] 2006.201.11:51:13.28#ibcon#*before write, iclass 40, count 0 2006.201.11:51:13.28#ibcon#enter sib2, iclass 40, count 0 2006.201.11:51:13.28#ibcon#flushed, iclass 40, count 0 2006.201.11:51:13.28#ibcon#about to write, iclass 40, count 0 2006.201.11:51:13.28#ibcon#wrote, iclass 40, count 0 2006.201.11:51:13.28#ibcon#about to read 3, iclass 40, count 0 2006.201.11:51:13.31#ibcon#read 3, iclass 40, count 0 2006.201.11:51:13.31#ibcon#about to read 4, iclass 40, count 0 2006.201.11:51:13.31#ibcon#read 4, iclass 40, count 0 2006.201.11:51:13.31#ibcon#about to read 5, iclass 40, count 0 2006.201.11:51:13.31#ibcon#read 5, iclass 40, count 0 2006.201.11:51:13.31#ibcon#about to read 6, iclass 40, count 0 2006.201.11:51:13.31#ibcon#read 6, iclass 40, count 0 2006.201.11:51:13.31#ibcon#end of sib2, iclass 40, count 0 2006.201.11:51:13.31#ibcon#*after write, iclass 40, count 0 2006.201.11:51:13.31#ibcon#*before return 0, iclass 40, count 0 2006.201.11:51:13.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:13.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.11:51:13.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.11:51:13.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.11:51:13.31$vck44/vbbw=wide 2006.201.11:51:13.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.11:51:13.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.11:51:13.31#ibcon#ireg 8 cls_cnt 0 2006.201.11:51:13.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:51:13.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:51:13.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:51:13.38#ibcon#enter wrdev, iclass 4, count 0 2006.201.11:51:13.38#ibcon#first serial, iclass 4, count 0 2006.201.11:51:13.38#ibcon#enter sib2, iclass 4, count 0 2006.201.11:51:13.38#ibcon#flushed, iclass 4, count 0 2006.201.11:51:13.38#ibcon#about to write, iclass 4, count 0 2006.201.11:51:13.38#ibcon#wrote, iclass 4, count 0 2006.201.11:51:13.38#ibcon#about to read 3, iclass 4, count 0 2006.201.11:51:13.40#ibcon#read 3, iclass 4, count 0 2006.201.11:51:13.40#ibcon#about to read 4, iclass 4, count 0 2006.201.11:51:13.40#ibcon#read 4, iclass 4, count 0 2006.201.11:51:13.40#ibcon#about to read 5, iclass 4, count 0 2006.201.11:51:13.40#ibcon#read 5, iclass 4, count 0 2006.201.11:51:13.40#ibcon#about to read 6, iclass 4, count 0 2006.201.11:51:13.40#ibcon#read 6, iclass 4, count 0 2006.201.11:51:13.40#ibcon#end of sib2, iclass 4, count 0 2006.201.11:51:13.40#ibcon#*mode == 0, iclass 4, count 0 2006.201.11:51:13.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.11:51:13.40#ibcon#[27=BW32\r\n] 2006.201.11:51:13.40#ibcon#*before write, iclass 4, count 0 2006.201.11:51:13.40#ibcon#enter sib2, iclass 4, count 0 2006.201.11:51:13.40#ibcon#flushed, iclass 4, count 0 2006.201.11:51:13.40#ibcon#about to write, iclass 4, count 0 2006.201.11:51:13.40#ibcon#wrote, iclass 4, count 0 2006.201.11:51:13.40#ibcon#about to read 3, iclass 4, count 0 2006.201.11:51:13.43#ibcon#read 3, iclass 4, count 0 2006.201.11:51:13.43#ibcon#about to read 4, iclass 4, count 0 2006.201.11:51:13.43#ibcon#read 4, iclass 4, count 0 2006.201.11:51:13.43#ibcon#about to read 5, iclass 4, count 0 2006.201.11:51:13.43#ibcon#read 5, iclass 4, count 0 2006.201.11:51:13.43#ibcon#about to read 6, iclass 4, count 0 2006.201.11:51:13.43#ibcon#read 6, iclass 4, count 0 2006.201.11:51:13.43#ibcon#end of sib2, iclass 4, count 0 2006.201.11:51:13.43#ibcon#*after write, iclass 4, count 0 2006.201.11:51:13.43#ibcon#*before return 0, iclass 4, count 0 2006.201.11:51:13.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:51:13.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.11:51:13.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.11:51:13.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.11:51:13.43$setupk4/ifdk4 2006.201.11:51:13.43$ifdk4/lo= 2006.201.11:51:13.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.11:51:13.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.11:51:13.43$ifdk4/patch= 2006.201.11:51:13.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.11:51:13.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.11:51:13.43$setupk4/!*+20s 2006.201.11:51:16.73#abcon#<5=/04 1.6 3.2 21.351001003.9\r\n> 2006.201.11:51:16.75#abcon#{5=INTERFACE CLEAR} 2006.201.11:51:16.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:51:25.14#trakl#Source acquired 2006.201.11:51:25.14#flagr#flagr/antenna,acquired 2006.201.11:51:27.00#abcon#<5=/04 1.7 3.2 21.351001003.9\r\n> 2006.201.11:51:27.02#abcon#{5=INTERFACE CLEAR} 2006.201.11:51:27.08#abcon#[5=S1D000X0/0*\r\n] 2006.201.11:51:27.89$setupk4/"tpicd 2006.201.11:51:27.89$setupk4/echo=off 2006.201.11:51:27.89$setupk4/xlog=off 2006.201.11:51:27.89:!2006.201.11:59:35 2006.201.11:59:35.00:preob 2006.201.11:59:35.14/onsource/TRACKING 2006.201.11:59:35.14:!2006.201.11:59:45 2006.201.11:59:45.00:"tape 2006.201.11:59:45.00:"st=record 2006.201.11:59:45.00:data_valid=on 2006.201.11:59:45.00:midob 2006.201.11:59:46.14/onsource/TRACKING 2006.201.11:59:46.14/wx/21.30,1003.9,100 2006.201.11:59:46.28/cable/+6.4697E-03 2006.201.11:59:47.37/va/01,08,usb,yes,30,33 2006.201.11:59:47.37/va/02,07,usb,yes,33,34 2006.201.11:59:47.37/va/03,08,usb,yes,30,31 2006.201.11:59:47.37/va/04,07,usb,yes,34,36 2006.201.11:59:47.37/va/05,04,usb,yes,30,30 2006.201.11:59:47.37/va/06,05,usb,yes,30,30 2006.201.11:59:47.37/va/07,05,usb,yes,29,30 2006.201.11:59:47.37/va/08,04,usb,yes,29,35 2006.201.11:59:47.60/valo/01,524.99,yes,locked 2006.201.11:59:47.60/valo/02,534.99,yes,locked 2006.201.11:59:47.60/valo/03,564.99,yes,locked 2006.201.11:59:47.60/valo/04,624.99,yes,locked 2006.201.11:59:47.60/valo/05,734.99,yes,locked 2006.201.11:59:47.60/valo/06,814.99,yes,locked 2006.201.11:59:47.60/valo/07,864.99,yes,locked 2006.201.11:59:47.60/valo/08,884.99,yes,locked 2006.201.11:59:48.69/vb/01,04,usb,yes,30,28 2006.201.11:59:48.69/vb/02,05,usb,yes,28,28 2006.201.11:59:48.69/vb/03,04,usb,yes,29,32 2006.201.11:59:48.69/vb/04,05,usb,yes,30,29 2006.201.11:59:48.69/vb/05,04,usb,yes,26,29 2006.201.11:59:48.69/vb/06,04,usb,yes,31,27 2006.201.11:59:48.69/vb/07,04,usb,yes,31,30 2006.201.11:59:48.69/vb/08,04,usb,yes,28,31 2006.201.11:59:48.93/vblo/01,629.99,yes,locked 2006.201.11:59:48.93/vblo/02,634.99,yes,locked 2006.201.11:59:48.93/vblo/03,649.99,yes,locked 2006.201.11:59:48.93/vblo/04,679.99,yes,locked 2006.201.11:59:48.93/vblo/05,709.99,yes,locked 2006.201.11:59:48.93/vblo/06,719.99,yes,locked 2006.201.11:59:48.93/vblo/07,734.99,yes,locked 2006.201.11:59:48.93/vblo/08,744.99,yes,locked 2006.201.11:59:49.08/vabw/8 2006.201.11:59:49.23/vbbw/8 2006.201.11:59:49.39/xfe/off,on,15.2 2006.201.11:59:49.76/ifatt/23,28,28,28 2006.201.11:59:50.05/fmout-gps/S +4.59E-07 2006.201.11:59:50.10:!2006.201.12:04:05 2006.201.12:04:05.00:data_valid=off 2006.201.12:04:05.00:"et 2006.201.12:04:05.00:!+3s 2006.201.12:04:08.02:"tape 2006.201.12:04:08.02:postob 2006.201.12:04:08.24/cable/+6.4719E-03 2006.201.12:04:08.24/wx/21.27,1004.0,100 2006.201.12:04:08.30/fmout-gps/S +4.58E-07 2006.201.12:04:08.30:scan_name=201-1205,jd0607,80 2006.201.12:04:08.30:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.201.12:04:09.14#flagr#flagr/antenna,new-source 2006.201.12:04:09.14:checkk5 2006.201.12:04:09.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:04:09.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:04:10.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:04:10.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:04:11.04/chk_obsdata//k5ts1/T2011159??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.201.12:04:11.41/chk_obsdata//k5ts2/T2011159??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.201.12:04:11.78/chk_obsdata//k5ts3/T2011159??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.201.12:04:12.15/chk_obsdata//k5ts4/T2011159??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.201.12:04:12.83/k5log//k5ts1_log_newline 2006.201.12:04:13.53/k5log//k5ts2_log_newline 2006.201.12:04:14.22/k5log//k5ts3_log_newline 2006.201.12:04:14.91/k5log//k5ts4_log_newline 2006.201.12:04:14.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:04:14.93:setupk4=1 2006.201.12:04:14.93$setupk4/echo=on 2006.201.12:04:14.93$setupk4/pcalon 2006.201.12:04:14.93$pcalon/"no phase cal control is implemented here 2006.201.12:04:14.93$setupk4/"tpicd=stop 2006.201.12:04:14.93$setupk4/"rec=synch_on 2006.201.12:04:14.93$setupk4/"rec_mode=128 2006.201.12:04:14.93$setupk4/!* 2006.201.12:04:14.93$setupk4/recpk4 2006.201.12:04:14.93$recpk4/recpatch= 2006.201.12:04:14.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:04:14.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:04:14.94$setupk4/vck44 2006.201.12:04:14.94$vck44/valo=1,524.99 2006.201.12:04:14.94#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.12:04:14.94#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.12:04:14.94#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:14.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:14.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:14.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:14.94#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:04:14.94#ibcon#first serial, iclass 31, count 0 2006.201.12:04:14.94#ibcon#enter sib2, iclass 31, count 0 2006.201.12:04:14.94#ibcon#flushed, iclass 31, count 0 2006.201.12:04:14.94#ibcon#about to write, iclass 31, count 0 2006.201.12:04:14.94#ibcon#wrote, iclass 31, count 0 2006.201.12:04:14.94#ibcon#about to read 3, iclass 31, count 0 2006.201.12:04:14.97#ibcon#read 3, iclass 31, count 0 2006.201.12:04:14.97#ibcon#about to read 4, iclass 31, count 0 2006.201.12:04:14.97#ibcon#read 4, iclass 31, count 0 2006.201.12:04:14.97#ibcon#about to read 5, iclass 31, count 0 2006.201.12:04:14.97#ibcon#read 5, iclass 31, count 0 2006.201.12:04:14.97#ibcon#about to read 6, iclass 31, count 0 2006.201.12:04:14.97#ibcon#read 6, iclass 31, count 0 2006.201.12:04:14.97#ibcon#end of sib2, iclass 31, count 0 2006.201.12:04:14.97#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:04:14.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:04:14.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:04:14.97#ibcon#*before write, iclass 31, count 0 2006.201.12:04:14.97#ibcon#enter sib2, iclass 31, count 0 2006.201.12:04:14.97#ibcon#flushed, iclass 31, count 0 2006.201.12:04:14.97#ibcon#about to write, iclass 31, count 0 2006.201.12:04:14.97#ibcon#wrote, iclass 31, count 0 2006.201.12:04:14.97#ibcon#about to read 3, iclass 31, count 0 2006.201.12:04:15.02#ibcon#read 3, iclass 31, count 0 2006.201.12:04:15.02#ibcon#about to read 4, iclass 31, count 0 2006.201.12:04:15.02#ibcon#read 4, iclass 31, count 0 2006.201.12:04:15.02#ibcon#about to read 5, iclass 31, count 0 2006.201.12:04:15.02#ibcon#read 5, iclass 31, count 0 2006.201.12:04:15.02#ibcon#about to read 6, iclass 31, count 0 2006.201.12:04:15.02#ibcon#read 6, iclass 31, count 0 2006.201.12:04:15.02#ibcon#end of sib2, iclass 31, count 0 2006.201.12:04:15.02#ibcon#*after write, iclass 31, count 0 2006.201.12:04:15.02#ibcon#*before return 0, iclass 31, count 0 2006.201.12:04:15.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:15.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:15.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:04:15.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:04:15.02$vck44/va=1,8 2006.201.12:04:15.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.12:04:15.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.12:04:15.02#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:15.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:15.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:15.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:15.02#ibcon#enter wrdev, iclass 33, count 2 2006.201.12:04:15.02#ibcon#first serial, iclass 33, count 2 2006.201.12:04:15.02#ibcon#enter sib2, iclass 33, count 2 2006.201.12:04:15.02#ibcon#flushed, iclass 33, count 2 2006.201.12:04:15.02#ibcon#about to write, iclass 33, count 2 2006.201.12:04:15.02#ibcon#wrote, iclass 33, count 2 2006.201.12:04:15.02#ibcon#about to read 3, iclass 33, count 2 2006.201.12:04:15.04#ibcon#read 3, iclass 33, count 2 2006.201.12:04:15.04#ibcon#about to read 4, iclass 33, count 2 2006.201.12:04:15.04#ibcon#read 4, iclass 33, count 2 2006.201.12:04:15.04#ibcon#about to read 5, iclass 33, count 2 2006.201.12:04:15.04#ibcon#read 5, iclass 33, count 2 2006.201.12:04:15.04#ibcon#about to read 6, iclass 33, count 2 2006.201.12:04:15.04#ibcon#read 6, iclass 33, count 2 2006.201.12:04:15.04#ibcon#end of sib2, iclass 33, count 2 2006.201.12:04:15.04#ibcon#*mode == 0, iclass 33, count 2 2006.201.12:04:15.04#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.12:04:15.04#ibcon#[25=AT01-08\r\n] 2006.201.12:04:15.04#ibcon#*before write, iclass 33, count 2 2006.201.12:04:15.04#ibcon#enter sib2, iclass 33, count 2 2006.201.12:04:15.04#ibcon#flushed, iclass 33, count 2 2006.201.12:04:15.04#ibcon#about to write, iclass 33, count 2 2006.201.12:04:15.04#ibcon#wrote, iclass 33, count 2 2006.201.12:04:15.04#ibcon#about to read 3, iclass 33, count 2 2006.201.12:04:15.07#ibcon#read 3, iclass 33, count 2 2006.201.12:04:15.07#ibcon#about to read 4, iclass 33, count 2 2006.201.12:04:15.07#ibcon#read 4, iclass 33, count 2 2006.201.12:04:15.07#ibcon#about to read 5, iclass 33, count 2 2006.201.12:04:15.07#ibcon#read 5, iclass 33, count 2 2006.201.12:04:15.07#ibcon#about to read 6, iclass 33, count 2 2006.201.12:04:15.07#ibcon#read 6, iclass 33, count 2 2006.201.12:04:15.07#ibcon#end of sib2, iclass 33, count 2 2006.201.12:04:15.07#ibcon#*after write, iclass 33, count 2 2006.201.12:04:15.07#ibcon#*before return 0, iclass 33, count 2 2006.201.12:04:15.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:15.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:15.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.12:04:15.07#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:15.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:15.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:15.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:15.19#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:04:15.19#ibcon#first serial, iclass 33, count 0 2006.201.12:04:15.19#ibcon#enter sib2, iclass 33, count 0 2006.201.12:04:15.19#ibcon#flushed, iclass 33, count 0 2006.201.12:04:15.19#ibcon#about to write, iclass 33, count 0 2006.201.12:04:15.19#ibcon#wrote, iclass 33, count 0 2006.201.12:04:15.19#ibcon#about to read 3, iclass 33, count 0 2006.201.12:04:15.21#ibcon#read 3, iclass 33, count 0 2006.201.12:04:15.21#ibcon#about to read 4, iclass 33, count 0 2006.201.12:04:15.21#ibcon#read 4, iclass 33, count 0 2006.201.12:04:15.21#ibcon#about to read 5, iclass 33, count 0 2006.201.12:04:15.21#ibcon#read 5, iclass 33, count 0 2006.201.12:04:15.21#ibcon#about to read 6, iclass 33, count 0 2006.201.12:04:15.21#ibcon#read 6, iclass 33, count 0 2006.201.12:04:15.21#ibcon#end of sib2, iclass 33, count 0 2006.201.12:04:15.21#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:04:15.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:04:15.21#ibcon#[25=USB\r\n] 2006.201.12:04:15.21#ibcon#*before write, iclass 33, count 0 2006.201.12:04:15.21#ibcon#enter sib2, iclass 33, count 0 2006.201.12:04:15.21#ibcon#flushed, iclass 33, count 0 2006.201.12:04:15.21#ibcon#about to write, iclass 33, count 0 2006.201.12:04:15.21#ibcon#wrote, iclass 33, count 0 2006.201.12:04:15.21#ibcon#about to read 3, iclass 33, count 0 2006.201.12:04:15.24#ibcon#read 3, iclass 33, count 0 2006.201.12:04:15.24#ibcon#about to read 4, iclass 33, count 0 2006.201.12:04:15.24#ibcon#read 4, iclass 33, count 0 2006.201.12:04:15.24#ibcon#about to read 5, iclass 33, count 0 2006.201.12:04:15.24#ibcon#read 5, iclass 33, count 0 2006.201.12:04:15.24#ibcon#about to read 6, iclass 33, count 0 2006.201.12:04:15.24#ibcon#read 6, iclass 33, count 0 2006.201.12:04:15.24#ibcon#end of sib2, iclass 33, count 0 2006.201.12:04:15.24#ibcon#*after write, iclass 33, count 0 2006.201.12:04:15.24#ibcon#*before return 0, iclass 33, count 0 2006.201.12:04:15.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:15.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:15.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:04:15.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:04:15.24$vck44/valo=2,534.99 2006.201.12:04:15.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.12:04:15.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.12:04:15.24#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:15.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:15.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:15.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:15.24#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:04:15.24#ibcon#first serial, iclass 35, count 0 2006.201.12:04:15.24#ibcon#enter sib2, iclass 35, count 0 2006.201.12:04:15.24#ibcon#flushed, iclass 35, count 0 2006.201.12:04:15.24#ibcon#about to write, iclass 35, count 0 2006.201.12:04:15.24#ibcon#wrote, iclass 35, count 0 2006.201.12:04:15.24#ibcon#about to read 3, iclass 35, count 0 2006.201.12:04:15.26#ibcon#read 3, iclass 35, count 0 2006.201.12:04:15.26#ibcon#about to read 4, iclass 35, count 0 2006.201.12:04:15.26#ibcon#read 4, iclass 35, count 0 2006.201.12:04:15.26#ibcon#about to read 5, iclass 35, count 0 2006.201.12:04:15.26#ibcon#read 5, iclass 35, count 0 2006.201.12:04:15.26#ibcon#about to read 6, iclass 35, count 0 2006.201.12:04:15.26#ibcon#read 6, iclass 35, count 0 2006.201.12:04:15.26#ibcon#end of sib2, iclass 35, count 0 2006.201.12:04:15.26#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:04:15.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:04:15.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:04:15.26#ibcon#*before write, iclass 35, count 0 2006.201.12:04:15.26#ibcon#enter sib2, iclass 35, count 0 2006.201.12:04:15.26#ibcon#flushed, iclass 35, count 0 2006.201.12:04:15.26#ibcon#about to write, iclass 35, count 0 2006.201.12:04:15.26#ibcon#wrote, iclass 35, count 0 2006.201.12:04:15.26#ibcon#about to read 3, iclass 35, count 0 2006.201.12:04:15.30#ibcon#read 3, iclass 35, count 0 2006.201.12:04:15.30#ibcon#about to read 4, iclass 35, count 0 2006.201.12:04:15.30#ibcon#read 4, iclass 35, count 0 2006.201.12:04:15.30#ibcon#about to read 5, iclass 35, count 0 2006.201.12:04:15.30#ibcon#read 5, iclass 35, count 0 2006.201.12:04:15.30#ibcon#about to read 6, iclass 35, count 0 2006.201.12:04:15.30#ibcon#read 6, iclass 35, count 0 2006.201.12:04:15.30#ibcon#end of sib2, iclass 35, count 0 2006.201.12:04:15.30#ibcon#*after write, iclass 35, count 0 2006.201.12:04:15.30#ibcon#*before return 0, iclass 35, count 0 2006.201.12:04:15.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:15.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:15.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:04:15.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:04:15.30$vck44/va=2,7 2006.201.12:04:15.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.12:04:15.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.12:04:15.30#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:15.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:15.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:15.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:15.36#ibcon#enter wrdev, iclass 37, count 2 2006.201.12:04:15.36#ibcon#first serial, iclass 37, count 2 2006.201.12:04:15.36#ibcon#enter sib2, iclass 37, count 2 2006.201.12:04:15.36#ibcon#flushed, iclass 37, count 2 2006.201.12:04:15.36#ibcon#about to write, iclass 37, count 2 2006.201.12:04:15.36#ibcon#wrote, iclass 37, count 2 2006.201.12:04:15.36#ibcon#about to read 3, iclass 37, count 2 2006.201.12:04:15.38#ibcon#read 3, iclass 37, count 2 2006.201.12:04:15.38#ibcon#about to read 4, iclass 37, count 2 2006.201.12:04:15.38#ibcon#read 4, iclass 37, count 2 2006.201.12:04:15.38#ibcon#about to read 5, iclass 37, count 2 2006.201.12:04:15.38#ibcon#read 5, iclass 37, count 2 2006.201.12:04:15.38#ibcon#about to read 6, iclass 37, count 2 2006.201.12:04:15.38#ibcon#read 6, iclass 37, count 2 2006.201.12:04:15.38#ibcon#end of sib2, iclass 37, count 2 2006.201.12:04:15.38#ibcon#*mode == 0, iclass 37, count 2 2006.201.12:04:15.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.12:04:15.38#ibcon#[25=AT02-07\r\n] 2006.201.12:04:15.38#ibcon#*before write, iclass 37, count 2 2006.201.12:04:15.38#ibcon#enter sib2, iclass 37, count 2 2006.201.12:04:15.38#ibcon#flushed, iclass 37, count 2 2006.201.12:04:15.38#ibcon#about to write, iclass 37, count 2 2006.201.12:04:15.38#ibcon#wrote, iclass 37, count 2 2006.201.12:04:15.38#ibcon#about to read 3, iclass 37, count 2 2006.201.12:04:15.41#ibcon#read 3, iclass 37, count 2 2006.201.12:04:15.41#ibcon#about to read 4, iclass 37, count 2 2006.201.12:04:15.41#ibcon#read 4, iclass 37, count 2 2006.201.12:04:15.41#ibcon#about to read 5, iclass 37, count 2 2006.201.12:04:15.41#ibcon#read 5, iclass 37, count 2 2006.201.12:04:15.41#ibcon#about to read 6, iclass 37, count 2 2006.201.12:04:15.41#ibcon#read 6, iclass 37, count 2 2006.201.12:04:15.41#ibcon#end of sib2, iclass 37, count 2 2006.201.12:04:15.41#ibcon#*after write, iclass 37, count 2 2006.201.12:04:15.41#ibcon#*before return 0, iclass 37, count 2 2006.201.12:04:15.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:15.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:15.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.12:04:15.41#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:15.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:15.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:15.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:15.53#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:04:15.53#ibcon#first serial, iclass 37, count 0 2006.201.12:04:15.53#ibcon#enter sib2, iclass 37, count 0 2006.201.12:04:15.53#ibcon#flushed, iclass 37, count 0 2006.201.12:04:15.53#ibcon#about to write, iclass 37, count 0 2006.201.12:04:15.53#ibcon#wrote, iclass 37, count 0 2006.201.12:04:15.53#ibcon#about to read 3, iclass 37, count 0 2006.201.12:04:15.55#ibcon#read 3, iclass 37, count 0 2006.201.12:04:15.55#ibcon#about to read 4, iclass 37, count 0 2006.201.12:04:15.55#ibcon#read 4, iclass 37, count 0 2006.201.12:04:15.55#ibcon#about to read 5, iclass 37, count 0 2006.201.12:04:15.55#ibcon#read 5, iclass 37, count 0 2006.201.12:04:15.55#ibcon#about to read 6, iclass 37, count 0 2006.201.12:04:15.55#ibcon#read 6, iclass 37, count 0 2006.201.12:04:15.55#ibcon#end of sib2, iclass 37, count 0 2006.201.12:04:15.55#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:04:15.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:04:15.55#ibcon#[25=USB\r\n] 2006.201.12:04:15.55#ibcon#*before write, iclass 37, count 0 2006.201.12:04:15.55#ibcon#enter sib2, iclass 37, count 0 2006.201.12:04:15.55#ibcon#flushed, iclass 37, count 0 2006.201.12:04:15.55#ibcon#about to write, iclass 37, count 0 2006.201.12:04:15.55#ibcon#wrote, iclass 37, count 0 2006.201.12:04:15.55#ibcon#about to read 3, iclass 37, count 0 2006.201.12:04:15.58#ibcon#read 3, iclass 37, count 0 2006.201.12:04:15.58#ibcon#about to read 4, iclass 37, count 0 2006.201.12:04:15.58#ibcon#read 4, iclass 37, count 0 2006.201.12:04:15.58#ibcon#about to read 5, iclass 37, count 0 2006.201.12:04:15.58#ibcon#read 5, iclass 37, count 0 2006.201.12:04:15.58#ibcon#about to read 6, iclass 37, count 0 2006.201.12:04:15.58#ibcon#read 6, iclass 37, count 0 2006.201.12:04:15.58#ibcon#end of sib2, iclass 37, count 0 2006.201.12:04:15.58#ibcon#*after write, iclass 37, count 0 2006.201.12:04:15.58#ibcon#*before return 0, iclass 37, count 0 2006.201.12:04:15.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:15.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:15.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:04:15.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:04:15.58$vck44/valo=3,564.99 2006.201.12:04:15.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.12:04:15.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.12:04:15.58#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:15.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:15.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:15.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:15.58#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:04:15.58#ibcon#first serial, iclass 39, count 0 2006.201.12:04:15.58#ibcon#enter sib2, iclass 39, count 0 2006.201.12:04:15.58#ibcon#flushed, iclass 39, count 0 2006.201.12:04:15.58#ibcon#about to write, iclass 39, count 0 2006.201.12:04:15.58#ibcon#wrote, iclass 39, count 0 2006.201.12:04:15.58#ibcon#about to read 3, iclass 39, count 0 2006.201.12:04:15.60#ibcon#read 3, iclass 39, count 0 2006.201.12:04:15.60#ibcon#about to read 4, iclass 39, count 0 2006.201.12:04:15.60#ibcon#read 4, iclass 39, count 0 2006.201.12:04:15.60#ibcon#about to read 5, iclass 39, count 0 2006.201.12:04:15.60#ibcon#read 5, iclass 39, count 0 2006.201.12:04:15.60#ibcon#about to read 6, iclass 39, count 0 2006.201.12:04:15.60#ibcon#read 6, iclass 39, count 0 2006.201.12:04:15.60#ibcon#end of sib2, iclass 39, count 0 2006.201.12:04:15.60#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:04:15.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:04:15.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:04:15.60#ibcon#*before write, iclass 39, count 0 2006.201.12:04:15.60#ibcon#enter sib2, iclass 39, count 0 2006.201.12:04:15.60#ibcon#flushed, iclass 39, count 0 2006.201.12:04:15.60#ibcon#about to write, iclass 39, count 0 2006.201.12:04:15.60#ibcon#wrote, iclass 39, count 0 2006.201.12:04:15.60#ibcon#about to read 3, iclass 39, count 0 2006.201.12:04:15.65#ibcon#read 3, iclass 39, count 0 2006.201.12:04:15.65#ibcon#about to read 4, iclass 39, count 0 2006.201.12:04:15.65#ibcon#read 4, iclass 39, count 0 2006.201.12:04:15.65#ibcon#about to read 5, iclass 39, count 0 2006.201.12:04:15.65#ibcon#read 5, iclass 39, count 0 2006.201.12:04:15.65#ibcon#about to read 6, iclass 39, count 0 2006.201.12:04:15.65#ibcon#read 6, iclass 39, count 0 2006.201.12:04:15.65#ibcon#end of sib2, iclass 39, count 0 2006.201.12:04:15.65#ibcon#*after write, iclass 39, count 0 2006.201.12:04:15.65#ibcon#*before return 0, iclass 39, count 0 2006.201.12:04:15.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:15.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:15.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:04:15.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:04:15.65$vck44/va=3,8 2006.201.12:04:15.65#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.12:04:15.65#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.12:04:15.65#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:15.65#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:15.70#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:15.70#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:15.70#ibcon#enter wrdev, iclass 2, count 2 2006.201.12:04:15.70#ibcon#first serial, iclass 2, count 2 2006.201.12:04:15.70#ibcon#enter sib2, iclass 2, count 2 2006.201.12:04:15.70#ibcon#flushed, iclass 2, count 2 2006.201.12:04:15.70#ibcon#about to write, iclass 2, count 2 2006.201.12:04:15.70#ibcon#wrote, iclass 2, count 2 2006.201.12:04:15.70#ibcon#about to read 3, iclass 2, count 2 2006.201.12:04:15.72#ibcon#read 3, iclass 2, count 2 2006.201.12:04:15.72#ibcon#about to read 4, iclass 2, count 2 2006.201.12:04:15.72#ibcon#read 4, iclass 2, count 2 2006.201.12:04:15.72#ibcon#about to read 5, iclass 2, count 2 2006.201.12:04:15.72#ibcon#read 5, iclass 2, count 2 2006.201.12:04:15.72#ibcon#about to read 6, iclass 2, count 2 2006.201.12:04:15.72#ibcon#read 6, iclass 2, count 2 2006.201.12:04:15.72#ibcon#end of sib2, iclass 2, count 2 2006.201.12:04:15.72#ibcon#*mode == 0, iclass 2, count 2 2006.201.12:04:15.72#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.12:04:15.72#ibcon#[25=AT03-08\r\n] 2006.201.12:04:15.72#ibcon#*before write, iclass 2, count 2 2006.201.12:04:15.72#ibcon#enter sib2, iclass 2, count 2 2006.201.12:04:15.72#ibcon#flushed, iclass 2, count 2 2006.201.12:04:15.72#ibcon#about to write, iclass 2, count 2 2006.201.12:04:15.72#ibcon#wrote, iclass 2, count 2 2006.201.12:04:15.72#ibcon#about to read 3, iclass 2, count 2 2006.201.12:04:15.75#ibcon#read 3, iclass 2, count 2 2006.201.12:04:15.75#ibcon#about to read 4, iclass 2, count 2 2006.201.12:04:15.75#ibcon#read 4, iclass 2, count 2 2006.201.12:04:15.75#ibcon#about to read 5, iclass 2, count 2 2006.201.12:04:15.75#ibcon#read 5, iclass 2, count 2 2006.201.12:04:15.75#ibcon#about to read 6, iclass 2, count 2 2006.201.12:04:15.75#ibcon#read 6, iclass 2, count 2 2006.201.12:04:15.75#ibcon#end of sib2, iclass 2, count 2 2006.201.12:04:15.75#ibcon#*after write, iclass 2, count 2 2006.201.12:04:15.75#ibcon#*before return 0, iclass 2, count 2 2006.201.12:04:15.75#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:15.75#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:15.75#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.12:04:15.75#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:15.75#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:15.87#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:15.87#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:15.87#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:04:15.87#ibcon#first serial, iclass 2, count 0 2006.201.12:04:15.87#ibcon#enter sib2, iclass 2, count 0 2006.201.12:04:15.87#ibcon#flushed, iclass 2, count 0 2006.201.12:04:15.87#ibcon#about to write, iclass 2, count 0 2006.201.12:04:15.87#ibcon#wrote, iclass 2, count 0 2006.201.12:04:15.87#ibcon#about to read 3, iclass 2, count 0 2006.201.12:04:15.89#ibcon#read 3, iclass 2, count 0 2006.201.12:04:15.89#ibcon#about to read 4, iclass 2, count 0 2006.201.12:04:15.89#ibcon#read 4, iclass 2, count 0 2006.201.12:04:15.89#ibcon#about to read 5, iclass 2, count 0 2006.201.12:04:15.89#ibcon#read 5, iclass 2, count 0 2006.201.12:04:15.89#ibcon#about to read 6, iclass 2, count 0 2006.201.12:04:15.89#ibcon#read 6, iclass 2, count 0 2006.201.12:04:15.89#ibcon#end of sib2, iclass 2, count 0 2006.201.12:04:15.89#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:04:15.89#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:04:15.89#ibcon#[25=USB\r\n] 2006.201.12:04:15.89#ibcon#*before write, iclass 2, count 0 2006.201.12:04:15.89#ibcon#enter sib2, iclass 2, count 0 2006.201.12:04:15.89#ibcon#flushed, iclass 2, count 0 2006.201.12:04:15.89#ibcon#about to write, iclass 2, count 0 2006.201.12:04:15.89#ibcon#wrote, iclass 2, count 0 2006.201.12:04:15.89#ibcon#about to read 3, iclass 2, count 0 2006.201.12:04:15.92#ibcon#read 3, iclass 2, count 0 2006.201.12:04:15.92#ibcon#about to read 4, iclass 2, count 0 2006.201.12:04:15.92#ibcon#read 4, iclass 2, count 0 2006.201.12:04:15.92#ibcon#about to read 5, iclass 2, count 0 2006.201.12:04:15.92#ibcon#read 5, iclass 2, count 0 2006.201.12:04:15.92#ibcon#about to read 6, iclass 2, count 0 2006.201.12:04:15.92#ibcon#read 6, iclass 2, count 0 2006.201.12:04:15.92#ibcon#end of sib2, iclass 2, count 0 2006.201.12:04:15.92#ibcon#*after write, iclass 2, count 0 2006.201.12:04:15.92#ibcon#*before return 0, iclass 2, count 0 2006.201.12:04:15.92#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:15.92#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:15.92#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:04:15.92#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:04:15.92$vck44/valo=4,624.99 2006.201.12:04:15.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.12:04:15.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.12:04:15.92#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:15.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:15.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:15.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:15.92#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:04:15.92#ibcon#first serial, iclass 5, count 0 2006.201.12:04:15.92#ibcon#enter sib2, iclass 5, count 0 2006.201.12:04:15.92#ibcon#flushed, iclass 5, count 0 2006.201.12:04:15.92#ibcon#about to write, iclass 5, count 0 2006.201.12:04:15.92#ibcon#wrote, iclass 5, count 0 2006.201.12:04:15.92#ibcon#about to read 3, iclass 5, count 0 2006.201.12:04:15.94#ibcon#read 3, iclass 5, count 0 2006.201.12:04:15.94#ibcon#about to read 4, iclass 5, count 0 2006.201.12:04:15.94#ibcon#read 4, iclass 5, count 0 2006.201.12:04:15.94#ibcon#about to read 5, iclass 5, count 0 2006.201.12:04:15.94#ibcon#read 5, iclass 5, count 0 2006.201.12:04:15.94#ibcon#about to read 6, iclass 5, count 0 2006.201.12:04:15.94#ibcon#read 6, iclass 5, count 0 2006.201.12:04:15.94#ibcon#end of sib2, iclass 5, count 0 2006.201.12:04:15.94#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:04:15.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:04:15.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:04:15.94#ibcon#*before write, iclass 5, count 0 2006.201.12:04:15.94#ibcon#enter sib2, iclass 5, count 0 2006.201.12:04:15.94#ibcon#flushed, iclass 5, count 0 2006.201.12:04:15.94#ibcon#about to write, iclass 5, count 0 2006.201.12:04:15.94#ibcon#wrote, iclass 5, count 0 2006.201.12:04:15.94#ibcon#about to read 3, iclass 5, count 0 2006.201.12:04:15.98#ibcon#read 3, iclass 5, count 0 2006.201.12:04:15.98#ibcon#about to read 4, iclass 5, count 0 2006.201.12:04:15.98#ibcon#read 4, iclass 5, count 0 2006.201.12:04:15.98#ibcon#about to read 5, iclass 5, count 0 2006.201.12:04:15.98#ibcon#read 5, iclass 5, count 0 2006.201.12:04:15.98#ibcon#about to read 6, iclass 5, count 0 2006.201.12:04:15.98#ibcon#read 6, iclass 5, count 0 2006.201.12:04:15.98#ibcon#end of sib2, iclass 5, count 0 2006.201.12:04:15.98#ibcon#*after write, iclass 5, count 0 2006.201.12:04:15.98#ibcon#*before return 0, iclass 5, count 0 2006.201.12:04:15.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:15.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:15.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:04:15.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:04:15.98$vck44/va=4,7 2006.201.12:04:15.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.12:04:15.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.12:04:15.98#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:15.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:16.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:16.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:16.04#ibcon#enter wrdev, iclass 7, count 2 2006.201.12:04:16.04#ibcon#first serial, iclass 7, count 2 2006.201.12:04:16.04#ibcon#enter sib2, iclass 7, count 2 2006.201.12:04:16.04#ibcon#flushed, iclass 7, count 2 2006.201.12:04:16.04#ibcon#about to write, iclass 7, count 2 2006.201.12:04:16.04#ibcon#wrote, iclass 7, count 2 2006.201.12:04:16.04#ibcon#about to read 3, iclass 7, count 2 2006.201.12:04:16.06#ibcon#read 3, iclass 7, count 2 2006.201.12:04:16.06#ibcon#about to read 4, iclass 7, count 2 2006.201.12:04:16.06#ibcon#read 4, iclass 7, count 2 2006.201.12:04:16.06#ibcon#about to read 5, iclass 7, count 2 2006.201.12:04:16.06#ibcon#read 5, iclass 7, count 2 2006.201.12:04:16.06#ibcon#about to read 6, iclass 7, count 2 2006.201.12:04:16.06#ibcon#read 6, iclass 7, count 2 2006.201.12:04:16.06#ibcon#end of sib2, iclass 7, count 2 2006.201.12:04:16.06#ibcon#*mode == 0, iclass 7, count 2 2006.201.12:04:16.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.12:04:16.06#ibcon#[25=AT04-07\r\n] 2006.201.12:04:16.06#ibcon#*before write, iclass 7, count 2 2006.201.12:04:16.06#ibcon#enter sib2, iclass 7, count 2 2006.201.12:04:16.06#ibcon#flushed, iclass 7, count 2 2006.201.12:04:16.06#ibcon#about to write, iclass 7, count 2 2006.201.12:04:16.06#ibcon#wrote, iclass 7, count 2 2006.201.12:04:16.06#ibcon#about to read 3, iclass 7, count 2 2006.201.12:04:16.09#ibcon#read 3, iclass 7, count 2 2006.201.12:04:16.09#ibcon#about to read 4, iclass 7, count 2 2006.201.12:04:16.09#ibcon#read 4, iclass 7, count 2 2006.201.12:04:16.09#ibcon#about to read 5, iclass 7, count 2 2006.201.12:04:16.09#ibcon#read 5, iclass 7, count 2 2006.201.12:04:16.09#ibcon#about to read 6, iclass 7, count 2 2006.201.12:04:16.09#ibcon#read 6, iclass 7, count 2 2006.201.12:04:16.09#ibcon#end of sib2, iclass 7, count 2 2006.201.12:04:16.09#ibcon#*after write, iclass 7, count 2 2006.201.12:04:16.09#ibcon#*before return 0, iclass 7, count 2 2006.201.12:04:16.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:16.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:16.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.12:04:16.09#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:16.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:16.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:16.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:16.21#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:04:16.21#ibcon#first serial, iclass 7, count 0 2006.201.12:04:16.21#ibcon#enter sib2, iclass 7, count 0 2006.201.12:04:16.21#ibcon#flushed, iclass 7, count 0 2006.201.12:04:16.21#ibcon#about to write, iclass 7, count 0 2006.201.12:04:16.21#ibcon#wrote, iclass 7, count 0 2006.201.12:04:16.21#ibcon#about to read 3, iclass 7, count 0 2006.201.12:04:16.23#ibcon#read 3, iclass 7, count 0 2006.201.12:04:16.23#ibcon#about to read 4, iclass 7, count 0 2006.201.12:04:16.23#ibcon#read 4, iclass 7, count 0 2006.201.12:04:16.23#ibcon#about to read 5, iclass 7, count 0 2006.201.12:04:16.23#ibcon#read 5, iclass 7, count 0 2006.201.12:04:16.23#ibcon#about to read 6, iclass 7, count 0 2006.201.12:04:16.23#ibcon#read 6, iclass 7, count 0 2006.201.12:04:16.23#ibcon#end of sib2, iclass 7, count 0 2006.201.12:04:16.23#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:04:16.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:04:16.23#ibcon#[25=USB\r\n] 2006.201.12:04:16.23#ibcon#*before write, iclass 7, count 0 2006.201.12:04:16.23#ibcon#enter sib2, iclass 7, count 0 2006.201.12:04:16.23#ibcon#flushed, iclass 7, count 0 2006.201.12:04:16.23#ibcon#about to write, iclass 7, count 0 2006.201.12:04:16.23#ibcon#wrote, iclass 7, count 0 2006.201.12:04:16.23#ibcon#about to read 3, iclass 7, count 0 2006.201.12:04:16.26#ibcon#read 3, iclass 7, count 0 2006.201.12:04:16.26#ibcon#about to read 4, iclass 7, count 0 2006.201.12:04:16.26#ibcon#read 4, iclass 7, count 0 2006.201.12:04:16.26#ibcon#about to read 5, iclass 7, count 0 2006.201.12:04:16.26#ibcon#read 5, iclass 7, count 0 2006.201.12:04:16.26#ibcon#about to read 6, iclass 7, count 0 2006.201.12:04:16.26#ibcon#read 6, iclass 7, count 0 2006.201.12:04:16.26#ibcon#end of sib2, iclass 7, count 0 2006.201.12:04:16.26#ibcon#*after write, iclass 7, count 0 2006.201.12:04:16.26#ibcon#*before return 0, iclass 7, count 0 2006.201.12:04:16.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:16.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:16.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:04:16.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:04:16.26$vck44/valo=5,734.99 2006.201.12:04:16.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.12:04:16.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.12:04:16.26#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:16.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:16.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:16.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:16.26#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:04:16.26#ibcon#first serial, iclass 11, count 0 2006.201.12:04:16.26#ibcon#enter sib2, iclass 11, count 0 2006.201.12:04:16.26#ibcon#flushed, iclass 11, count 0 2006.201.12:04:16.26#ibcon#about to write, iclass 11, count 0 2006.201.12:04:16.26#ibcon#wrote, iclass 11, count 0 2006.201.12:04:16.26#ibcon#about to read 3, iclass 11, count 0 2006.201.12:04:16.28#ibcon#read 3, iclass 11, count 0 2006.201.12:04:16.28#ibcon#about to read 4, iclass 11, count 0 2006.201.12:04:16.28#ibcon#read 4, iclass 11, count 0 2006.201.12:04:16.28#ibcon#about to read 5, iclass 11, count 0 2006.201.12:04:16.28#ibcon#read 5, iclass 11, count 0 2006.201.12:04:16.28#ibcon#about to read 6, iclass 11, count 0 2006.201.12:04:16.28#ibcon#read 6, iclass 11, count 0 2006.201.12:04:16.28#ibcon#end of sib2, iclass 11, count 0 2006.201.12:04:16.28#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:04:16.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:04:16.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:04:16.28#ibcon#*before write, iclass 11, count 0 2006.201.12:04:16.28#ibcon#enter sib2, iclass 11, count 0 2006.201.12:04:16.28#ibcon#flushed, iclass 11, count 0 2006.201.12:04:16.28#ibcon#about to write, iclass 11, count 0 2006.201.12:04:16.28#ibcon#wrote, iclass 11, count 0 2006.201.12:04:16.28#ibcon#about to read 3, iclass 11, count 0 2006.201.12:04:16.32#ibcon#read 3, iclass 11, count 0 2006.201.12:04:16.32#ibcon#about to read 4, iclass 11, count 0 2006.201.12:04:16.32#ibcon#read 4, iclass 11, count 0 2006.201.12:04:16.32#ibcon#about to read 5, iclass 11, count 0 2006.201.12:04:16.32#ibcon#read 5, iclass 11, count 0 2006.201.12:04:16.32#ibcon#about to read 6, iclass 11, count 0 2006.201.12:04:16.32#ibcon#read 6, iclass 11, count 0 2006.201.12:04:16.32#ibcon#end of sib2, iclass 11, count 0 2006.201.12:04:16.32#ibcon#*after write, iclass 11, count 0 2006.201.12:04:16.32#ibcon#*before return 0, iclass 11, count 0 2006.201.12:04:16.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:16.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:16.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:04:16.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:04:16.32$vck44/va=5,4 2006.201.12:04:16.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.12:04:16.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.12:04:16.32#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:16.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:16.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:16.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:16.38#ibcon#enter wrdev, iclass 13, count 2 2006.201.12:04:16.38#ibcon#first serial, iclass 13, count 2 2006.201.12:04:16.38#ibcon#enter sib2, iclass 13, count 2 2006.201.12:04:16.38#ibcon#flushed, iclass 13, count 2 2006.201.12:04:16.38#ibcon#about to write, iclass 13, count 2 2006.201.12:04:16.38#ibcon#wrote, iclass 13, count 2 2006.201.12:04:16.38#ibcon#about to read 3, iclass 13, count 2 2006.201.12:04:16.40#ibcon#read 3, iclass 13, count 2 2006.201.12:04:16.40#ibcon#about to read 4, iclass 13, count 2 2006.201.12:04:16.40#ibcon#read 4, iclass 13, count 2 2006.201.12:04:16.40#ibcon#about to read 5, iclass 13, count 2 2006.201.12:04:16.40#ibcon#read 5, iclass 13, count 2 2006.201.12:04:16.40#ibcon#about to read 6, iclass 13, count 2 2006.201.12:04:16.40#ibcon#read 6, iclass 13, count 2 2006.201.12:04:16.40#ibcon#end of sib2, iclass 13, count 2 2006.201.12:04:16.40#ibcon#*mode == 0, iclass 13, count 2 2006.201.12:04:16.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.12:04:16.40#ibcon#[25=AT05-04\r\n] 2006.201.12:04:16.40#ibcon#*before write, iclass 13, count 2 2006.201.12:04:16.40#ibcon#enter sib2, iclass 13, count 2 2006.201.12:04:16.40#ibcon#flushed, iclass 13, count 2 2006.201.12:04:16.40#ibcon#about to write, iclass 13, count 2 2006.201.12:04:16.40#ibcon#wrote, iclass 13, count 2 2006.201.12:04:16.40#ibcon#about to read 3, iclass 13, count 2 2006.201.12:04:16.43#ibcon#read 3, iclass 13, count 2 2006.201.12:04:16.43#ibcon#about to read 4, iclass 13, count 2 2006.201.12:04:16.43#ibcon#read 4, iclass 13, count 2 2006.201.12:04:16.43#ibcon#about to read 5, iclass 13, count 2 2006.201.12:04:16.43#ibcon#read 5, iclass 13, count 2 2006.201.12:04:16.43#ibcon#about to read 6, iclass 13, count 2 2006.201.12:04:16.43#ibcon#read 6, iclass 13, count 2 2006.201.12:04:16.43#ibcon#end of sib2, iclass 13, count 2 2006.201.12:04:16.43#ibcon#*after write, iclass 13, count 2 2006.201.12:04:16.43#ibcon#*before return 0, iclass 13, count 2 2006.201.12:04:16.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:16.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:16.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.12:04:16.43#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:16.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:16.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:16.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:16.55#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:04:16.55#ibcon#first serial, iclass 13, count 0 2006.201.12:04:16.55#ibcon#enter sib2, iclass 13, count 0 2006.201.12:04:16.55#ibcon#flushed, iclass 13, count 0 2006.201.12:04:16.55#ibcon#about to write, iclass 13, count 0 2006.201.12:04:16.55#ibcon#wrote, iclass 13, count 0 2006.201.12:04:16.55#ibcon#about to read 3, iclass 13, count 0 2006.201.12:04:16.57#ibcon#read 3, iclass 13, count 0 2006.201.12:04:16.57#ibcon#about to read 4, iclass 13, count 0 2006.201.12:04:16.57#ibcon#read 4, iclass 13, count 0 2006.201.12:04:16.57#ibcon#about to read 5, iclass 13, count 0 2006.201.12:04:16.57#ibcon#read 5, iclass 13, count 0 2006.201.12:04:16.57#ibcon#about to read 6, iclass 13, count 0 2006.201.12:04:16.57#ibcon#read 6, iclass 13, count 0 2006.201.12:04:16.57#ibcon#end of sib2, iclass 13, count 0 2006.201.12:04:16.57#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:04:16.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:04:16.57#ibcon#[25=USB\r\n] 2006.201.12:04:16.57#ibcon#*before write, iclass 13, count 0 2006.201.12:04:16.57#ibcon#enter sib2, iclass 13, count 0 2006.201.12:04:16.57#ibcon#flushed, iclass 13, count 0 2006.201.12:04:16.57#ibcon#about to write, iclass 13, count 0 2006.201.12:04:16.57#ibcon#wrote, iclass 13, count 0 2006.201.12:04:16.57#ibcon#about to read 3, iclass 13, count 0 2006.201.12:04:16.60#ibcon#read 3, iclass 13, count 0 2006.201.12:04:16.60#ibcon#about to read 4, iclass 13, count 0 2006.201.12:04:16.60#ibcon#read 4, iclass 13, count 0 2006.201.12:04:16.60#ibcon#about to read 5, iclass 13, count 0 2006.201.12:04:16.60#ibcon#read 5, iclass 13, count 0 2006.201.12:04:16.60#ibcon#about to read 6, iclass 13, count 0 2006.201.12:04:16.60#ibcon#read 6, iclass 13, count 0 2006.201.12:04:16.60#ibcon#end of sib2, iclass 13, count 0 2006.201.12:04:16.60#ibcon#*after write, iclass 13, count 0 2006.201.12:04:16.60#ibcon#*before return 0, iclass 13, count 0 2006.201.12:04:16.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:16.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:16.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:04:16.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:04:16.60$vck44/valo=6,814.99 2006.201.12:04:16.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.12:04:16.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.12:04:16.60#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:16.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:16.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:16.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:16.60#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:04:16.60#ibcon#first serial, iclass 15, count 0 2006.201.12:04:16.60#ibcon#enter sib2, iclass 15, count 0 2006.201.12:04:16.60#ibcon#flushed, iclass 15, count 0 2006.201.12:04:16.60#ibcon#about to write, iclass 15, count 0 2006.201.12:04:16.60#ibcon#wrote, iclass 15, count 0 2006.201.12:04:16.60#ibcon#about to read 3, iclass 15, count 0 2006.201.12:04:16.62#ibcon#read 3, iclass 15, count 0 2006.201.12:04:16.62#ibcon#about to read 4, iclass 15, count 0 2006.201.12:04:16.62#ibcon#read 4, iclass 15, count 0 2006.201.12:04:16.62#ibcon#about to read 5, iclass 15, count 0 2006.201.12:04:16.62#ibcon#read 5, iclass 15, count 0 2006.201.12:04:16.62#ibcon#about to read 6, iclass 15, count 0 2006.201.12:04:16.62#ibcon#read 6, iclass 15, count 0 2006.201.12:04:16.62#ibcon#end of sib2, iclass 15, count 0 2006.201.12:04:16.62#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:04:16.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:04:16.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:04:16.62#ibcon#*before write, iclass 15, count 0 2006.201.12:04:16.62#ibcon#enter sib2, iclass 15, count 0 2006.201.12:04:16.62#ibcon#flushed, iclass 15, count 0 2006.201.12:04:16.62#ibcon#about to write, iclass 15, count 0 2006.201.12:04:16.62#ibcon#wrote, iclass 15, count 0 2006.201.12:04:16.62#ibcon#about to read 3, iclass 15, count 0 2006.201.12:04:16.66#ibcon#read 3, iclass 15, count 0 2006.201.12:04:16.66#ibcon#about to read 4, iclass 15, count 0 2006.201.12:04:16.66#ibcon#read 4, iclass 15, count 0 2006.201.12:04:16.66#ibcon#about to read 5, iclass 15, count 0 2006.201.12:04:16.66#ibcon#read 5, iclass 15, count 0 2006.201.12:04:16.66#ibcon#about to read 6, iclass 15, count 0 2006.201.12:04:16.66#ibcon#read 6, iclass 15, count 0 2006.201.12:04:16.66#ibcon#end of sib2, iclass 15, count 0 2006.201.12:04:16.66#ibcon#*after write, iclass 15, count 0 2006.201.12:04:16.66#ibcon#*before return 0, iclass 15, count 0 2006.201.12:04:16.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:16.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:16.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:04:16.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:04:16.66$vck44/va=6,5 2006.201.12:04:16.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.12:04:16.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.12:04:16.66#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:16.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:16.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:16.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:16.72#ibcon#enter wrdev, iclass 17, count 2 2006.201.12:04:16.72#ibcon#first serial, iclass 17, count 2 2006.201.12:04:16.72#ibcon#enter sib2, iclass 17, count 2 2006.201.12:04:16.72#ibcon#flushed, iclass 17, count 2 2006.201.12:04:16.72#ibcon#about to write, iclass 17, count 2 2006.201.12:04:16.72#ibcon#wrote, iclass 17, count 2 2006.201.12:04:16.72#ibcon#about to read 3, iclass 17, count 2 2006.201.12:04:16.74#ibcon#read 3, iclass 17, count 2 2006.201.12:04:16.74#ibcon#about to read 4, iclass 17, count 2 2006.201.12:04:16.74#ibcon#read 4, iclass 17, count 2 2006.201.12:04:16.74#ibcon#about to read 5, iclass 17, count 2 2006.201.12:04:16.74#ibcon#read 5, iclass 17, count 2 2006.201.12:04:16.74#ibcon#about to read 6, iclass 17, count 2 2006.201.12:04:16.74#ibcon#read 6, iclass 17, count 2 2006.201.12:04:16.74#ibcon#end of sib2, iclass 17, count 2 2006.201.12:04:16.74#ibcon#*mode == 0, iclass 17, count 2 2006.201.12:04:16.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.12:04:16.74#ibcon#[25=AT06-05\r\n] 2006.201.12:04:16.74#ibcon#*before write, iclass 17, count 2 2006.201.12:04:16.74#ibcon#enter sib2, iclass 17, count 2 2006.201.12:04:16.74#ibcon#flushed, iclass 17, count 2 2006.201.12:04:16.74#ibcon#about to write, iclass 17, count 2 2006.201.12:04:16.74#ibcon#wrote, iclass 17, count 2 2006.201.12:04:16.74#ibcon#about to read 3, iclass 17, count 2 2006.201.12:04:16.77#ibcon#read 3, iclass 17, count 2 2006.201.12:04:16.77#ibcon#about to read 4, iclass 17, count 2 2006.201.12:04:16.77#ibcon#read 4, iclass 17, count 2 2006.201.12:04:16.77#ibcon#about to read 5, iclass 17, count 2 2006.201.12:04:16.77#ibcon#read 5, iclass 17, count 2 2006.201.12:04:16.77#ibcon#about to read 6, iclass 17, count 2 2006.201.12:04:16.77#ibcon#read 6, iclass 17, count 2 2006.201.12:04:16.77#ibcon#end of sib2, iclass 17, count 2 2006.201.12:04:16.77#ibcon#*after write, iclass 17, count 2 2006.201.12:04:16.77#ibcon#*before return 0, iclass 17, count 2 2006.201.12:04:16.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:16.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:16.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.12:04:16.77#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:16.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:16.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:16.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:16.89#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:04:16.89#ibcon#first serial, iclass 17, count 0 2006.201.12:04:16.89#ibcon#enter sib2, iclass 17, count 0 2006.201.12:04:16.89#ibcon#flushed, iclass 17, count 0 2006.201.12:04:16.89#ibcon#about to write, iclass 17, count 0 2006.201.12:04:16.89#ibcon#wrote, iclass 17, count 0 2006.201.12:04:16.89#ibcon#about to read 3, iclass 17, count 0 2006.201.12:04:16.91#ibcon#read 3, iclass 17, count 0 2006.201.12:04:16.91#ibcon#about to read 4, iclass 17, count 0 2006.201.12:04:16.91#ibcon#read 4, iclass 17, count 0 2006.201.12:04:16.91#ibcon#about to read 5, iclass 17, count 0 2006.201.12:04:16.91#ibcon#read 5, iclass 17, count 0 2006.201.12:04:16.91#ibcon#about to read 6, iclass 17, count 0 2006.201.12:04:16.91#ibcon#read 6, iclass 17, count 0 2006.201.12:04:16.91#ibcon#end of sib2, iclass 17, count 0 2006.201.12:04:16.91#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:04:16.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:04:16.91#ibcon#[25=USB\r\n] 2006.201.12:04:16.91#ibcon#*before write, iclass 17, count 0 2006.201.12:04:16.91#ibcon#enter sib2, iclass 17, count 0 2006.201.12:04:16.91#ibcon#flushed, iclass 17, count 0 2006.201.12:04:16.91#ibcon#about to write, iclass 17, count 0 2006.201.12:04:16.91#ibcon#wrote, iclass 17, count 0 2006.201.12:04:16.91#ibcon#about to read 3, iclass 17, count 0 2006.201.12:04:16.94#ibcon#read 3, iclass 17, count 0 2006.201.12:04:16.94#ibcon#about to read 4, iclass 17, count 0 2006.201.12:04:16.94#ibcon#read 4, iclass 17, count 0 2006.201.12:04:16.94#ibcon#about to read 5, iclass 17, count 0 2006.201.12:04:16.94#ibcon#read 5, iclass 17, count 0 2006.201.12:04:16.94#ibcon#about to read 6, iclass 17, count 0 2006.201.12:04:16.94#ibcon#read 6, iclass 17, count 0 2006.201.12:04:16.94#ibcon#end of sib2, iclass 17, count 0 2006.201.12:04:16.94#ibcon#*after write, iclass 17, count 0 2006.201.12:04:16.94#ibcon#*before return 0, iclass 17, count 0 2006.201.12:04:16.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:16.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:16.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:04:16.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:04:16.94$vck44/valo=7,864.99 2006.201.12:04:16.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.12:04:16.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.12:04:16.94#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:16.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:16.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:16.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:16.94#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:04:16.94#ibcon#first serial, iclass 19, count 0 2006.201.12:04:16.94#ibcon#enter sib2, iclass 19, count 0 2006.201.12:04:16.94#ibcon#flushed, iclass 19, count 0 2006.201.12:04:16.94#ibcon#about to write, iclass 19, count 0 2006.201.12:04:16.94#ibcon#wrote, iclass 19, count 0 2006.201.12:04:16.94#ibcon#about to read 3, iclass 19, count 0 2006.201.12:04:16.96#ibcon#read 3, iclass 19, count 0 2006.201.12:04:16.96#ibcon#about to read 4, iclass 19, count 0 2006.201.12:04:16.96#ibcon#read 4, iclass 19, count 0 2006.201.12:04:16.96#ibcon#about to read 5, iclass 19, count 0 2006.201.12:04:16.96#ibcon#read 5, iclass 19, count 0 2006.201.12:04:16.96#ibcon#about to read 6, iclass 19, count 0 2006.201.12:04:16.96#ibcon#read 6, iclass 19, count 0 2006.201.12:04:16.96#ibcon#end of sib2, iclass 19, count 0 2006.201.12:04:16.96#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:04:16.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:04:16.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:04:16.96#ibcon#*before write, iclass 19, count 0 2006.201.12:04:16.96#ibcon#enter sib2, iclass 19, count 0 2006.201.12:04:16.96#ibcon#flushed, iclass 19, count 0 2006.201.12:04:16.96#ibcon#about to write, iclass 19, count 0 2006.201.12:04:16.96#ibcon#wrote, iclass 19, count 0 2006.201.12:04:16.96#ibcon#about to read 3, iclass 19, count 0 2006.201.12:04:17.00#ibcon#read 3, iclass 19, count 0 2006.201.12:04:17.00#ibcon#about to read 4, iclass 19, count 0 2006.201.12:04:17.00#ibcon#read 4, iclass 19, count 0 2006.201.12:04:17.00#ibcon#about to read 5, iclass 19, count 0 2006.201.12:04:17.00#ibcon#read 5, iclass 19, count 0 2006.201.12:04:17.00#ibcon#about to read 6, iclass 19, count 0 2006.201.12:04:17.00#ibcon#read 6, iclass 19, count 0 2006.201.12:04:17.00#ibcon#end of sib2, iclass 19, count 0 2006.201.12:04:17.00#ibcon#*after write, iclass 19, count 0 2006.201.12:04:17.00#ibcon#*before return 0, iclass 19, count 0 2006.201.12:04:17.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:17.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:17.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:04:17.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:04:17.00$vck44/va=7,5 2006.201.12:04:17.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.12:04:17.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.12:04:17.00#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:17.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:17.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:17.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:17.06#ibcon#enter wrdev, iclass 21, count 2 2006.201.12:04:17.06#ibcon#first serial, iclass 21, count 2 2006.201.12:04:17.06#ibcon#enter sib2, iclass 21, count 2 2006.201.12:04:17.06#ibcon#flushed, iclass 21, count 2 2006.201.12:04:17.06#ibcon#about to write, iclass 21, count 2 2006.201.12:04:17.06#ibcon#wrote, iclass 21, count 2 2006.201.12:04:17.06#ibcon#about to read 3, iclass 21, count 2 2006.201.12:04:17.08#ibcon#read 3, iclass 21, count 2 2006.201.12:04:17.08#ibcon#about to read 4, iclass 21, count 2 2006.201.12:04:17.08#ibcon#read 4, iclass 21, count 2 2006.201.12:04:17.08#ibcon#about to read 5, iclass 21, count 2 2006.201.12:04:17.08#ibcon#read 5, iclass 21, count 2 2006.201.12:04:17.08#ibcon#about to read 6, iclass 21, count 2 2006.201.12:04:17.08#ibcon#read 6, iclass 21, count 2 2006.201.12:04:17.08#ibcon#end of sib2, iclass 21, count 2 2006.201.12:04:17.08#ibcon#*mode == 0, iclass 21, count 2 2006.201.12:04:17.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.12:04:17.08#ibcon#[25=AT07-05\r\n] 2006.201.12:04:17.08#ibcon#*before write, iclass 21, count 2 2006.201.12:04:17.08#ibcon#enter sib2, iclass 21, count 2 2006.201.12:04:17.08#ibcon#flushed, iclass 21, count 2 2006.201.12:04:17.08#ibcon#about to write, iclass 21, count 2 2006.201.12:04:17.08#ibcon#wrote, iclass 21, count 2 2006.201.12:04:17.08#ibcon#about to read 3, iclass 21, count 2 2006.201.12:04:17.11#ibcon#read 3, iclass 21, count 2 2006.201.12:04:17.11#ibcon#about to read 4, iclass 21, count 2 2006.201.12:04:17.11#ibcon#read 4, iclass 21, count 2 2006.201.12:04:17.11#ibcon#about to read 5, iclass 21, count 2 2006.201.12:04:17.11#ibcon#read 5, iclass 21, count 2 2006.201.12:04:17.11#ibcon#about to read 6, iclass 21, count 2 2006.201.12:04:17.11#ibcon#read 6, iclass 21, count 2 2006.201.12:04:17.11#ibcon#end of sib2, iclass 21, count 2 2006.201.12:04:17.11#ibcon#*after write, iclass 21, count 2 2006.201.12:04:17.11#ibcon#*before return 0, iclass 21, count 2 2006.201.12:04:17.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:17.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:17.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.12:04:17.11#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:17.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:17.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:17.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:17.23#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:04:17.23#ibcon#first serial, iclass 21, count 0 2006.201.12:04:17.23#ibcon#enter sib2, iclass 21, count 0 2006.201.12:04:17.23#ibcon#flushed, iclass 21, count 0 2006.201.12:04:17.23#ibcon#about to write, iclass 21, count 0 2006.201.12:04:17.23#ibcon#wrote, iclass 21, count 0 2006.201.12:04:17.23#ibcon#about to read 3, iclass 21, count 0 2006.201.12:04:17.25#ibcon#read 3, iclass 21, count 0 2006.201.12:04:17.25#ibcon#about to read 4, iclass 21, count 0 2006.201.12:04:17.25#ibcon#read 4, iclass 21, count 0 2006.201.12:04:17.25#ibcon#about to read 5, iclass 21, count 0 2006.201.12:04:17.25#ibcon#read 5, iclass 21, count 0 2006.201.12:04:17.25#ibcon#about to read 6, iclass 21, count 0 2006.201.12:04:17.25#ibcon#read 6, iclass 21, count 0 2006.201.12:04:17.25#ibcon#end of sib2, iclass 21, count 0 2006.201.12:04:17.25#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:04:17.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:04:17.25#ibcon#[25=USB\r\n] 2006.201.12:04:17.25#ibcon#*before write, iclass 21, count 0 2006.201.12:04:17.25#ibcon#enter sib2, iclass 21, count 0 2006.201.12:04:17.25#ibcon#flushed, iclass 21, count 0 2006.201.12:04:17.25#ibcon#about to write, iclass 21, count 0 2006.201.12:04:17.25#ibcon#wrote, iclass 21, count 0 2006.201.12:04:17.25#ibcon#about to read 3, iclass 21, count 0 2006.201.12:04:17.28#ibcon#read 3, iclass 21, count 0 2006.201.12:04:17.28#ibcon#about to read 4, iclass 21, count 0 2006.201.12:04:17.28#ibcon#read 4, iclass 21, count 0 2006.201.12:04:17.28#ibcon#about to read 5, iclass 21, count 0 2006.201.12:04:17.28#ibcon#read 5, iclass 21, count 0 2006.201.12:04:17.28#ibcon#about to read 6, iclass 21, count 0 2006.201.12:04:17.28#ibcon#read 6, iclass 21, count 0 2006.201.12:04:17.28#ibcon#end of sib2, iclass 21, count 0 2006.201.12:04:17.28#ibcon#*after write, iclass 21, count 0 2006.201.12:04:17.28#ibcon#*before return 0, iclass 21, count 0 2006.201.12:04:17.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:17.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:17.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:04:17.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:04:17.28$vck44/valo=8,884.99 2006.201.12:04:17.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.12:04:17.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.12:04:17.28#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:17.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:04:17.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:04:17.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:04:17.28#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:04:17.28#ibcon#first serial, iclass 23, count 0 2006.201.12:04:17.28#ibcon#enter sib2, iclass 23, count 0 2006.201.12:04:17.28#ibcon#flushed, iclass 23, count 0 2006.201.12:04:17.28#ibcon#about to write, iclass 23, count 0 2006.201.12:04:17.28#ibcon#wrote, iclass 23, count 0 2006.201.12:04:17.28#ibcon#about to read 3, iclass 23, count 0 2006.201.12:04:17.30#ibcon#read 3, iclass 23, count 0 2006.201.12:04:17.30#ibcon#about to read 4, iclass 23, count 0 2006.201.12:04:17.30#ibcon#read 4, iclass 23, count 0 2006.201.12:04:17.30#ibcon#about to read 5, iclass 23, count 0 2006.201.12:04:17.30#ibcon#read 5, iclass 23, count 0 2006.201.12:04:17.30#ibcon#about to read 6, iclass 23, count 0 2006.201.12:04:17.30#ibcon#read 6, iclass 23, count 0 2006.201.12:04:17.30#ibcon#end of sib2, iclass 23, count 0 2006.201.12:04:17.30#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:04:17.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:04:17.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:04:17.30#ibcon#*before write, iclass 23, count 0 2006.201.12:04:17.30#ibcon#enter sib2, iclass 23, count 0 2006.201.12:04:17.30#ibcon#flushed, iclass 23, count 0 2006.201.12:04:17.30#ibcon#about to write, iclass 23, count 0 2006.201.12:04:17.30#ibcon#wrote, iclass 23, count 0 2006.201.12:04:17.30#ibcon#about to read 3, iclass 23, count 0 2006.201.12:04:17.34#ibcon#read 3, iclass 23, count 0 2006.201.12:04:17.34#ibcon#about to read 4, iclass 23, count 0 2006.201.12:04:17.34#ibcon#read 4, iclass 23, count 0 2006.201.12:04:17.34#ibcon#about to read 5, iclass 23, count 0 2006.201.12:04:17.34#ibcon#read 5, iclass 23, count 0 2006.201.12:04:17.34#ibcon#about to read 6, iclass 23, count 0 2006.201.12:04:17.34#ibcon#read 6, iclass 23, count 0 2006.201.12:04:17.34#ibcon#end of sib2, iclass 23, count 0 2006.201.12:04:17.34#ibcon#*after write, iclass 23, count 0 2006.201.12:04:17.34#ibcon#*before return 0, iclass 23, count 0 2006.201.12:04:17.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:04:17.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:04:17.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:04:17.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:04:17.34$vck44/va=8,4 2006.201.12:04:17.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.12:04:17.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.12:04:17.34#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:17.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:04:17.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:04:17.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:04:17.40#ibcon#enter wrdev, iclass 25, count 2 2006.201.12:04:17.40#ibcon#first serial, iclass 25, count 2 2006.201.12:04:17.40#ibcon#enter sib2, iclass 25, count 2 2006.201.12:04:17.40#ibcon#flushed, iclass 25, count 2 2006.201.12:04:17.40#ibcon#about to write, iclass 25, count 2 2006.201.12:04:17.40#ibcon#wrote, iclass 25, count 2 2006.201.12:04:17.40#ibcon#about to read 3, iclass 25, count 2 2006.201.12:04:17.42#ibcon#read 3, iclass 25, count 2 2006.201.12:04:17.42#ibcon#about to read 4, iclass 25, count 2 2006.201.12:04:17.42#ibcon#read 4, iclass 25, count 2 2006.201.12:04:17.42#ibcon#about to read 5, iclass 25, count 2 2006.201.12:04:17.42#ibcon#read 5, iclass 25, count 2 2006.201.12:04:17.42#ibcon#about to read 6, iclass 25, count 2 2006.201.12:04:17.42#ibcon#read 6, iclass 25, count 2 2006.201.12:04:17.42#ibcon#end of sib2, iclass 25, count 2 2006.201.12:04:17.42#ibcon#*mode == 0, iclass 25, count 2 2006.201.12:04:17.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.12:04:17.42#ibcon#[25=AT08-04\r\n] 2006.201.12:04:17.42#ibcon#*before write, iclass 25, count 2 2006.201.12:04:17.42#ibcon#enter sib2, iclass 25, count 2 2006.201.12:04:17.42#ibcon#flushed, iclass 25, count 2 2006.201.12:04:17.42#ibcon#about to write, iclass 25, count 2 2006.201.12:04:17.42#ibcon#wrote, iclass 25, count 2 2006.201.12:04:17.42#ibcon#about to read 3, iclass 25, count 2 2006.201.12:04:17.45#ibcon#read 3, iclass 25, count 2 2006.201.12:04:17.45#ibcon#about to read 4, iclass 25, count 2 2006.201.12:04:17.45#ibcon#read 4, iclass 25, count 2 2006.201.12:04:17.45#ibcon#about to read 5, iclass 25, count 2 2006.201.12:04:17.45#ibcon#read 5, iclass 25, count 2 2006.201.12:04:17.45#ibcon#about to read 6, iclass 25, count 2 2006.201.12:04:17.45#ibcon#read 6, iclass 25, count 2 2006.201.12:04:17.45#ibcon#end of sib2, iclass 25, count 2 2006.201.12:04:17.45#ibcon#*after write, iclass 25, count 2 2006.201.12:04:17.45#ibcon#*before return 0, iclass 25, count 2 2006.201.12:04:17.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:04:17.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:04:17.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.12:04:17.45#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:17.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:04:17.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:04:17.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:04:17.57#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:04:17.57#ibcon#first serial, iclass 25, count 0 2006.201.12:04:17.57#ibcon#enter sib2, iclass 25, count 0 2006.201.12:04:17.57#ibcon#flushed, iclass 25, count 0 2006.201.12:04:17.57#ibcon#about to write, iclass 25, count 0 2006.201.12:04:17.57#ibcon#wrote, iclass 25, count 0 2006.201.12:04:17.57#ibcon#about to read 3, iclass 25, count 0 2006.201.12:04:17.59#ibcon#read 3, iclass 25, count 0 2006.201.12:04:17.59#ibcon#about to read 4, iclass 25, count 0 2006.201.12:04:17.59#ibcon#read 4, iclass 25, count 0 2006.201.12:04:17.59#ibcon#about to read 5, iclass 25, count 0 2006.201.12:04:17.59#ibcon#read 5, iclass 25, count 0 2006.201.12:04:17.59#ibcon#about to read 6, iclass 25, count 0 2006.201.12:04:17.59#ibcon#read 6, iclass 25, count 0 2006.201.12:04:17.59#ibcon#end of sib2, iclass 25, count 0 2006.201.12:04:17.59#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:04:17.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:04:17.59#ibcon#[25=USB\r\n] 2006.201.12:04:17.59#ibcon#*before write, iclass 25, count 0 2006.201.12:04:17.59#ibcon#enter sib2, iclass 25, count 0 2006.201.12:04:17.59#ibcon#flushed, iclass 25, count 0 2006.201.12:04:17.59#ibcon#about to write, iclass 25, count 0 2006.201.12:04:17.59#ibcon#wrote, iclass 25, count 0 2006.201.12:04:17.59#ibcon#about to read 3, iclass 25, count 0 2006.201.12:04:17.62#ibcon#read 3, iclass 25, count 0 2006.201.12:04:17.62#ibcon#about to read 4, iclass 25, count 0 2006.201.12:04:17.62#ibcon#read 4, iclass 25, count 0 2006.201.12:04:17.62#ibcon#about to read 5, iclass 25, count 0 2006.201.12:04:17.62#ibcon#read 5, iclass 25, count 0 2006.201.12:04:17.62#ibcon#about to read 6, iclass 25, count 0 2006.201.12:04:17.62#ibcon#read 6, iclass 25, count 0 2006.201.12:04:17.62#ibcon#end of sib2, iclass 25, count 0 2006.201.12:04:17.62#ibcon#*after write, iclass 25, count 0 2006.201.12:04:17.62#ibcon#*before return 0, iclass 25, count 0 2006.201.12:04:17.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:04:17.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:04:17.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:04:17.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:04:17.62$vck44/vblo=1,629.99 2006.201.12:04:17.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.12:04:17.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.12:04:17.62#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:17.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:17.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:17.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:17.62#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:04:17.62#ibcon#first serial, iclass 27, count 0 2006.201.12:04:17.62#ibcon#enter sib2, iclass 27, count 0 2006.201.12:04:17.62#ibcon#flushed, iclass 27, count 0 2006.201.12:04:17.62#ibcon#about to write, iclass 27, count 0 2006.201.12:04:17.62#ibcon#wrote, iclass 27, count 0 2006.201.12:04:17.62#ibcon#about to read 3, iclass 27, count 0 2006.201.12:04:17.64#ibcon#read 3, iclass 27, count 0 2006.201.12:04:17.64#ibcon#about to read 4, iclass 27, count 0 2006.201.12:04:17.64#ibcon#read 4, iclass 27, count 0 2006.201.12:04:17.64#ibcon#about to read 5, iclass 27, count 0 2006.201.12:04:17.64#ibcon#read 5, iclass 27, count 0 2006.201.12:04:17.64#ibcon#about to read 6, iclass 27, count 0 2006.201.12:04:17.64#ibcon#read 6, iclass 27, count 0 2006.201.12:04:17.64#ibcon#end of sib2, iclass 27, count 0 2006.201.12:04:17.64#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:04:17.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:04:17.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:04:17.64#ibcon#*before write, iclass 27, count 0 2006.201.12:04:17.64#ibcon#enter sib2, iclass 27, count 0 2006.201.12:04:17.64#ibcon#flushed, iclass 27, count 0 2006.201.12:04:17.64#ibcon#about to write, iclass 27, count 0 2006.201.12:04:17.64#ibcon#wrote, iclass 27, count 0 2006.201.12:04:17.64#ibcon#about to read 3, iclass 27, count 0 2006.201.12:04:17.69#ibcon#read 3, iclass 27, count 0 2006.201.12:04:17.69#ibcon#about to read 4, iclass 27, count 0 2006.201.12:04:17.69#ibcon#read 4, iclass 27, count 0 2006.201.12:04:17.69#ibcon#about to read 5, iclass 27, count 0 2006.201.12:04:17.69#ibcon#read 5, iclass 27, count 0 2006.201.12:04:17.69#ibcon#about to read 6, iclass 27, count 0 2006.201.12:04:17.69#ibcon#read 6, iclass 27, count 0 2006.201.12:04:17.69#ibcon#end of sib2, iclass 27, count 0 2006.201.12:04:17.69#ibcon#*after write, iclass 27, count 0 2006.201.12:04:17.69#ibcon#*before return 0, iclass 27, count 0 2006.201.12:04:17.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:17.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:17.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:04:17.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:04:17.69$vck44/vb=1,4 2006.201.12:04:17.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.12:04:17.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.12:04:17.69#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:17.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:04:17.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:04:17.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:04:17.69#ibcon#enter wrdev, iclass 29, count 2 2006.201.12:04:17.69#ibcon#first serial, iclass 29, count 2 2006.201.12:04:17.69#ibcon#enter sib2, iclass 29, count 2 2006.201.12:04:17.69#ibcon#flushed, iclass 29, count 2 2006.201.12:04:17.69#ibcon#about to write, iclass 29, count 2 2006.201.12:04:17.69#ibcon#wrote, iclass 29, count 2 2006.201.12:04:17.69#ibcon#about to read 3, iclass 29, count 2 2006.201.12:04:17.71#ibcon#read 3, iclass 29, count 2 2006.201.12:04:17.71#ibcon#about to read 4, iclass 29, count 2 2006.201.12:04:17.71#ibcon#read 4, iclass 29, count 2 2006.201.12:04:17.71#ibcon#about to read 5, iclass 29, count 2 2006.201.12:04:17.71#ibcon#read 5, iclass 29, count 2 2006.201.12:04:17.71#ibcon#about to read 6, iclass 29, count 2 2006.201.12:04:17.71#ibcon#read 6, iclass 29, count 2 2006.201.12:04:17.71#ibcon#end of sib2, iclass 29, count 2 2006.201.12:04:17.71#ibcon#*mode == 0, iclass 29, count 2 2006.201.12:04:17.71#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.12:04:17.71#ibcon#[27=AT01-04\r\n] 2006.201.12:04:17.71#ibcon#*before write, iclass 29, count 2 2006.201.12:04:17.71#ibcon#enter sib2, iclass 29, count 2 2006.201.12:04:17.71#ibcon#flushed, iclass 29, count 2 2006.201.12:04:17.71#ibcon#about to write, iclass 29, count 2 2006.201.12:04:17.71#ibcon#wrote, iclass 29, count 2 2006.201.12:04:17.71#ibcon#about to read 3, iclass 29, count 2 2006.201.12:04:17.74#ibcon#read 3, iclass 29, count 2 2006.201.12:04:17.74#ibcon#about to read 4, iclass 29, count 2 2006.201.12:04:17.74#ibcon#read 4, iclass 29, count 2 2006.201.12:04:17.74#ibcon#about to read 5, iclass 29, count 2 2006.201.12:04:17.74#ibcon#read 5, iclass 29, count 2 2006.201.12:04:17.74#ibcon#about to read 6, iclass 29, count 2 2006.201.12:04:17.74#ibcon#read 6, iclass 29, count 2 2006.201.12:04:17.74#ibcon#end of sib2, iclass 29, count 2 2006.201.12:04:17.74#ibcon#*after write, iclass 29, count 2 2006.201.12:04:17.74#ibcon#*before return 0, iclass 29, count 2 2006.201.12:04:17.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:04:17.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:04:17.74#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.12:04:17.74#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:17.74#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:04:17.86#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:04:17.86#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:04:17.86#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:04:17.86#ibcon#first serial, iclass 29, count 0 2006.201.12:04:17.86#ibcon#enter sib2, iclass 29, count 0 2006.201.12:04:17.86#ibcon#flushed, iclass 29, count 0 2006.201.12:04:17.86#ibcon#about to write, iclass 29, count 0 2006.201.12:04:17.86#ibcon#wrote, iclass 29, count 0 2006.201.12:04:17.86#ibcon#about to read 3, iclass 29, count 0 2006.201.12:04:17.88#ibcon#read 3, iclass 29, count 0 2006.201.12:04:17.88#ibcon#about to read 4, iclass 29, count 0 2006.201.12:04:17.88#ibcon#read 4, iclass 29, count 0 2006.201.12:04:17.88#ibcon#about to read 5, iclass 29, count 0 2006.201.12:04:17.88#ibcon#read 5, iclass 29, count 0 2006.201.12:04:17.88#ibcon#about to read 6, iclass 29, count 0 2006.201.12:04:17.88#ibcon#read 6, iclass 29, count 0 2006.201.12:04:17.88#ibcon#end of sib2, iclass 29, count 0 2006.201.12:04:17.88#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:04:17.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:04:17.88#ibcon#[27=USB\r\n] 2006.201.12:04:17.88#ibcon#*before write, iclass 29, count 0 2006.201.12:04:17.88#ibcon#enter sib2, iclass 29, count 0 2006.201.12:04:17.88#ibcon#flushed, iclass 29, count 0 2006.201.12:04:17.88#ibcon#about to write, iclass 29, count 0 2006.201.12:04:17.88#ibcon#wrote, iclass 29, count 0 2006.201.12:04:17.88#ibcon#about to read 3, iclass 29, count 0 2006.201.12:04:17.91#ibcon#read 3, iclass 29, count 0 2006.201.12:04:17.91#ibcon#about to read 4, iclass 29, count 0 2006.201.12:04:17.91#ibcon#read 4, iclass 29, count 0 2006.201.12:04:17.91#ibcon#about to read 5, iclass 29, count 0 2006.201.12:04:17.91#ibcon#read 5, iclass 29, count 0 2006.201.12:04:17.91#ibcon#about to read 6, iclass 29, count 0 2006.201.12:04:17.91#ibcon#read 6, iclass 29, count 0 2006.201.12:04:17.91#ibcon#end of sib2, iclass 29, count 0 2006.201.12:04:17.91#ibcon#*after write, iclass 29, count 0 2006.201.12:04:17.91#ibcon#*before return 0, iclass 29, count 0 2006.201.12:04:17.91#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:04:17.91#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:04:17.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:04:17.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:04:17.91$vck44/vblo=2,634.99 2006.201.12:04:17.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.12:04:17.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.12:04:17.91#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:17.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:17.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:17.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:17.91#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:04:17.91#ibcon#first serial, iclass 31, count 0 2006.201.12:04:17.91#ibcon#enter sib2, iclass 31, count 0 2006.201.12:04:17.91#ibcon#flushed, iclass 31, count 0 2006.201.12:04:17.91#ibcon#about to write, iclass 31, count 0 2006.201.12:04:17.91#ibcon#wrote, iclass 31, count 0 2006.201.12:04:17.91#ibcon#about to read 3, iclass 31, count 0 2006.201.12:04:17.93#ibcon#read 3, iclass 31, count 0 2006.201.12:04:17.93#ibcon#about to read 4, iclass 31, count 0 2006.201.12:04:17.93#ibcon#read 4, iclass 31, count 0 2006.201.12:04:17.93#ibcon#about to read 5, iclass 31, count 0 2006.201.12:04:17.93#ibcon#read 5, iclass 31, count 0 2006.201.12:04:17.93#ibcon#about to read 6, iclass 31, count 0 2006.201.12:04:17.93#ibcon#read 6, iclass 31, count 0 2006.201.12:04:17.93#ibcon#end of sib2, iclass 31, count 0 2006.201.12:04:17.93#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:04:17.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:04:17.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:04:17.93#ibcon#*before write, iclass 31, count 0 2006.201.12:04:17.93#ibcon#enter sib2, iclass 31, count 0 2006.201.12:04:17.93#ibcon#flushed, iclass 31, count 0 2006.201.12:04:17.93#ibcon#about to write, iclass 31, count 0 2006.201.12:04:17.93#ibcon#wrote, iclass 31, count 0 2006.201.12:04:17.93#ibcon#about to read 3, iclass 31, count 0 2006.201.12:04:17.97#ibcon#read 3, iclass 31, count 0 2006.201.12:04:17.97#ibcon#about to read 4, iclass 31, count 0 2006.201.12:04:17.97#ibcon#read 4, iclass 31, count 0 2006.201.12:04:17.97#ibcon#about to read 5, iclass 31, count 0 2006.201.12:04:17.97#ibcon#read 5, iclass 31, count 0 2006.201.12:04:17.97#ibcon#about to read 6, iclass 31, count 0 2006.201.12:04:17.97#ibcon#read 6, iclass 31, count 0 2006.201.12:04:17.97#ibcon#end of sib2, iclass 31, count 0 2006.201.12:04:17.97#ibcon#*after write, iclass 31, count 0 2006.201.12:04:17.97#ibcon#*before return 0, iclass 31, count 0 2006.201.12:04:17.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:17.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:04:17.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:04:17.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:04:17.97$vck44/vb=2,5 2006.201.12:04:17.97#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.12:04:17.97#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.12:04:17.97#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:17.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:18.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:18.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:18.03#ibcon#enter wrdev, iclass 33, count 2 2006.201.12:04:18.03#ibcon#first serial, iclass 33, count 2 2006.201.12:04:18.03#ibcon#enter sib2, iclass 33, count 2 2006.201.12:04:18.03#ibcon#flushed, iclass 33, count 2 2006.201.12:04:18.03#ibcon#about to write, iclass 33, count 2 2006.201.12:04:18.03#ibcon#wrote, iclass 33, count 2 2006.201.12:04:18.03#ibcon#about to read 3, iclass 33, count 2 2006.201.12:04:18.05#ibcon#read 3, iclass 33, count 2 2006.201.12:04:18.05#ibcon#about to read 4, iclass 33, count 2 2006.201.12:04:18.05#ibcon#read 4, iclass 33, count 2 2006.201.12:04:18.05#ibcon#about to read 5, iclass 33, count 2 2006.201.12:04:18.05#ibcon#read 5, iclass 33, count 2 2006.201.12:04:18.05#ibcon#about to read 6, iclass 33, count 2 2006.201.12:04:18.05#ibcon#read 6, iclass 33, count 2 2006.201.12:04:18.05#ibcon#end of sib2, iclass 33, count 2 2006.201.12:04:18.05#ibcon#*mode == 0, iclass 33, count 2 2006.201.12:04:18.05#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.12:04:18.05#ibcon#[27=AT02-05\r\n] 2006.201.12:04:18.05#ibcon#*before write, iclass 33, count 2 2006.201.12:04:18.05#ibcon#enter sib2, iclass 33, count 2 2006.201.12:04:18.05#ibcon#flushed, iclass 33, count 2 2006.201.12:04:18.05#ibcon#about to write, iclass 33, count 2 2006.201.12:04:18.05#ibcon#wrote, iclass 33, count 2 2006.201.12:04:18.05#ibcon#about to read 3, iclass 33, count 2 2006.201.12:04:18.08#ibcon#read 3, iclass 33, count 2 2006.201.12:04:18.08#ibcon#about to read 4, iclass 33, count 2 2006.201.12:04:18.08#ibcon#read 4, iclass 33, count 2 2006.201.12:04:18.08#ibcon#about to read 5, iclass 33, count 2 2006.201.12:04:18.08#ibcon#read 5, iclass 33, count 2 2006.201.12:04:18.08#ibcon#about to read 6, iclass 33, count 2 2006.201.12:04:18.08#ibcon#read 6, iclass 33, count 2 2006.201.12:04:18.08#ibcon#end of sib2, iclass 33, count 2 2006.201.12:04:18.08#ibcon#*after write, iclass 33, count 2 2006.201.12:04:18.08#ibcon#*before return 0, iclass 33, count 2 2006.201.12:04:18.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:18.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:04:18.08#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.12:04:18.08#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:18.08#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:18.20#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:18.20#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:18.20#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:04:18.20#ibcon#first serial, iclass 33, count 0 2006.201.12:04:18.20#ibcon#enter sib2, iclass 33, count 0 2006.201.12:04:18.20#ibcon#flushed, iclass 33, count 0 2006.201.12:04:18.20#ibcon#about to write, iclass 33, count 0 2006.201.12:04:18.20#ibcon#wrote, iclass 33, count 0 2006.201.12:04:18.20#ibcon#about to read 3, iclass 33, count 0 2006.201.12:04:18.22#ibcon#read 3, iclass 33, count 0 2006.201.12:04:18.22#ibcon#about to read 4, iclass 33, count 0 2006.201.12:04:18.22#ibcon#read 4, iclass 33, count 0 2006.201.12:04:18.22#ibcon#about to read 5, iclass 33, count 0 2006.201.12:04:18.22#ibcon#read 5, iclass 33, count 0 2006.201.12:04:18.22#ibcon#about to read 6, iclass 33, count 0 2006.201.12:04:18.22#ibcon#read 6, iclass 33, count 0 2006.201.12:04:18.22#ibcon#end of sib2, iclass 33, count 0 2006.201.12:04:18.22#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:04:18.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:04:18.22#ibcon#[27=USB\r\n] 2006.201.12:04:18.22#ibcon#*before write, iclass 33, count 0 2006.201.12:04:18.22#ibcon#enter sib2, iclass 33, count 0 2006.201.12:04:18.22#ibcon#flushed, iclass 33, count 0 2006.201.12:04:18.22#ibcon#about to write, iclass 33, count 0 2006.201.12:04:18.22#ibcon#wrote, iclass 33, count 0 2006.201.12:04:18.22#ibcon#about to read 3, iclass 33, count 0 2006.201.12:04:18.25#ibcon#read 3, iclass 33, count 0 2006.201.12:04:18.25#ibcon#about to read 4, iclass 33, count 0 2006.201.12:04:18.25#ibcon#read 4, iclass 33, count 0 2006.201.12:04:18.25#ibcon#about to read 5, iclass 33, count 0 2006.201.12:04:18.25#ibcon#read 5, iclass 33, count 0 2006.201.12:04:18.25#ibcon#about to read 6, iclass 33, count 0 2006.201.12:04:18.25#ibcon#read 6, iclass 33, count 0 2006.201.12:04:18.25#ibcon#end of sib2, iclass 33, count 0 2006.201.12:04:18.25#ibcon#*after write, iclass 33, count 0 2006.201.12:04:18.25#ibcon#*before return 0, iclass 33, count 0 2006.201.12:04:18.25#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:18.25#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:04:18.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:04:18.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:04:18.25$vck44/vblo=3,649.99 2006.201.12:04:18.25#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.12:04:18.25#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.12:04:18.25#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:18.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:18.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:18.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:18.25#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:04:18.25#ibcon#first serial, iclass 35, count 0 2006.201.12:04:18.25#ibcon#enter sib2, iclass 35, count 0 2006.201.12:04:18.25#ibcon#flushed, iclass 35, count 0 2006.201.12:04:18.25#ibcon#about to write, iclass 35, count 0 2006.201.12:04:18.25#ibcon#wrote, iclass 35, count 0 2006.201.12:04:18.25#ibcon#about to read 3, iclass 35, count 0 2006.201.12:04:18.27#ibcon#read 3, iclass 35, count 0 2006.201.12:04:18.27#ibcon#about to read 4, iclass 35, count 0 2006.201.12:04:18.27#ibcon#read 4, iclass 35, count 0 2006.201.12:04:18.27#ibcon#about to read 5, iclass 35, count 0 2006.201.12:04:18.27#ibcon#read 5, iclass 35, count 0 2006.201.12:04:18.27#ibcon#about to read 6, iclass 35, count 0 2006.201.12:04:18.27#ibcon#read 6, iclass 35, count 0 2006.201.12:04:18.27#ibcon#end of sib2, iclass 35, count 0 2006.201.12:04:18.27#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:04:18.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:04:18.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:04:18.27#ibcon#*before write, iclass 35, count 0 2006.201.12:04:18.27#ibcon#enter sib2, iclass 35, count 0 2006.201.12:04:18.27#ibcon#flushed, iclass 35, count 0 2006.201.12:04:18.27#ibcon#about to write, iclass 35, count 0 2006.201.12:04:18.27#ibcon#wrote, iclass 35, count 0 2006.201.12:04:18.27#ibcon#about to read 3, iclass 35, count 0 2006.201.12:04:18.31#ibcon#read 3, iclass 35, count 0 2006.201.12:04:18.31#ibcon#about to read 4, iclass 35, count 0 2006.201.12:04:18.31#ibcon#read 4, iclass 35, count 0 2006.201.12:04:18.31#ibcon#about to read 5, iclass 35, count 0 2006.201.12:04:18.31#ibcon#read 5, iclass 35, count 0 2006.201.12:04:18.31#ibcon#about to read 6, iclass 35, count 0 2006.201.12:04:18.31#ibcon#read 6, iclass 35, count 0 2006.201.12:04:18.31#ibcon#end of sib2, iclass 35, count 0 2006.201.12:04:18.31#ibcon#*after write, iclass 35, count 0 2006.201.12:04:18.31#ibcon#*before return 0, iclass 35, count 0 2006.201.12:04:18.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:18.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:04:18.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:04:18.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:04:18.31$vck44/vb=3,4 2006.201.12:04:18.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.12:04:18.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.12:04:18.31#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:18.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:18.37#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:18.37#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:18.37#ibcon#enter wrdev, iclass 37, count 2 2006.201.12:04:18.37#ibcon#first serial, iclass 37, count 2 2006.201.12:04:18.37#ibcon#enter sib2, iclass 37, count 2 2006.201.12:04:18.37#ibcon#flushed, iclass 37, count 2 2006.201.12:04:18.37#ibcon#about to write, iclass 37, count 2 2006.201.12:04:18.37#ibcon#wrote, iclass 37, count 2 2006.201.12:04:18.37#ibcon#about to read 3, iclass 37, count 2 2006.201.12:04:18.39#ibcon#read 3, iclass 37, count 2 2006.201.12:04:18.39#ibcon#about to read 4, iclass 37, count 2 2006.201.12:04:18.39#ibcon#read 4, iclass 37, count 2 2006.201.12:04:18.39#ibcon#about to read 5, iclass 37, count 2 2006.201.12:04:18.39#ibcon#read 5, iclass 37, count 2 2006.201.12:04:18.39#ibcon#about to read 6, iclass 37, count 2 2006.201.12:04:18.39#ibcon#read 6, iclass 37, count 2 2006.201.12:04:18.39#ibcon#end of sib2, iclass 37, count 2 2006.201.12:04:18.39#ibcon#*mode == 0, iclass 37, count 2 2006.201.12:04:18.39#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.12:04:18.39#ibcon#[27=AT03-04\r\n] 2006.201.12:04:18.39#ibcon#*before write, iclass 37, count 2 2006.201.12:04:18.39#ibcon#enter sib2, iclass 37, count 2 2006.201.12:04:18.39#ibcon#flushed, iclass 37, count 2 2006.201.12:04:18.39#ibcon#about to write, iclass 37, count 2 2006.201.12:04:18.39#ibcon#wrote, iclass 37, count 2 2006.201.12:04:18.39#ibcon#about to read 3, iclass 37, count 2 2006.201.12:04:18.42#ibcon#read 3, iclass 37, count 2 2006.201.12:04:18.42#ibcon#about to read 4, iclass 37, count 2 2006.201.12:04:18.42#ibcon#read 4, iclass 37, count 2 2006.201.12:04:18.42#ibcon#about to read 5, iclass 37, count 2 2006.201.12:04:18.42#ibcon#read 5, iclass 37, count 2 2006.201.12:04:18.42#ibcon#about to read 6, iclass 37, count 2 2006.201.12:04:18.42#ibcon#read 6, iclass 37, count 2 2006.201.12:04:18.42#ibcon#end of sib2, iclass 37, count 2 2006.201.12:04:18.42#ibcon#*after write, iclass 37, count 2 2006.201.12:04:18.42#ibcon#*before return 0, iclass 37, count 2 2006.201.12:04:18.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:18.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:04:18.42#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.12:04:18.42#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:18.42#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:18.54#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:18.54#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:18.54#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:04:18.54#ibcon#first serial, iclass 37, count 0 2006.201.12:04:18.54#ibcon#enter sib2, iclass 37, count 0 2006.201.12:04:18.54#ibcon#flushed, iclass 37, count 0 2006.201.12:04:18.54#ibcon#about to write, iclass 37, count 0 2006.201.12:04:18.54#ibcon#wrote, iclass 37, count 0 2006.201.12:04:18.54#ibcon#about to read 3, iclass 37, count 0 2006.201.12:04:18.56#ibcon#read 3, iclass 37, count 0 2006.201.12:04:18.56#ibcon#about to read 4, iclass 37, count 0 2006.201.12:04:18.56#ibcon#read 4, iclass 37, count 0 2006.201.12:04:18.56#ibcon#about to read 5, iclass 37, count 0 2006.201.12:04:18.56#ibcon#read 5, iclass 37, count 0 2006.201.12:04:18.56#ibcon#about to read 6, iclass 37, count 0 2006.201.12:04:18.56#ibcon#read 6, iclass 37, count 0 2006.201.12:04:18.56#ibcon#end of sib2, iclass 37, count 0 2006.201.12:04:18.56#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:04:18.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:04:18.56#ibcon#[27=USB\r\n] 2006.201.12:04:18.56#ibcon#*before write, iclass 37, count 0 2006.201.12:04:18.56#ibcon#enter sib2, iclass 37, count 0 2006.201.12:04:18.56#ibcon#flushed, iclass 37, count 0 2006.201.12:04:18.56#ibcon#about to write, iclass 37, count 0 2006.201.12:04:18.56#ibcon#wrote, iclass 37, count 0 2006.201.12:04:18.56#ibcon#about to read 3, iclass 37, count 0 2006.201.12:04:18.59#ibcon#read 3, iclass 37, count 0 2006.201.12:04:18.59#ibcon#about to read 4, iclass 37, count 0 2006.201.12:04:18.59#ibcon#read 4, iclass 37, count 0 2006.201.12:04:18.59#ibcon#about to read 5, iclass 37, count 0 2006.201.12:04:18.59#ibcon#read 5, iclass 37, count 0 2006.201.12:04:18.59#ibcon#about to read 6, iclass 37, count 0 2006.201.12:04:18.59#ibcon#read 6, iclass 37, count 0 2006.201.12:04:18.59#ibcon#end of sib2, iclass 37, count 0 2006.201.12:04:18.59#ibcon#*after write, iclass 37, count 0 2006.201.12:04:18.59#ibcon#*before return 0, iclass 37, count 0 2006.201.12:04:18.59#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:18.59#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:04:18.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:04:18.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:04:18.59$vck44/vblo=4,679.99 2006.201.12:04:18.59#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.12:04:18.59#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.12:04:18.59#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:18.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:18.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:18.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:18.59#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:04:18.59#ibcon#first serial, iclass 39, count 0 2006.201.12:04:18.59#ibcon#enter sib2, iclass 39, count 0 2006.201.12:04:18.59#ibcon#flushed, iclass 39, count 0 2006.201.12:04:18.59#ibcon#about to write, iclass 39, count 0 2006.201.12:04:18.59#ibcon#wrote, iclass 39, count 0 2006.201.12:04:18.59#ibcon#about to read 3, iclass 39, count 0 2006.201.12:04:18.61#ibcon#read 3, iclass 39, count 0 2006.201.12:04:18.61#ibcon#about to read 4, iclass 39, count 0 2006.201.12:04:18.61#ibcon#read 4, iclass 39, count 0 2006.201.12:04:18.61#ibcon#about to read 5, iclass 39, count 0 2006.201.12:04:18.61#ibcon#read 5, iclass 39, count 0 2006.201.12:04:18.61#ibcon#about to read 6, iclass 39, count 0 2006.201.12:04:18.61#ibcon#read 6, iclass 39, count 0 2006.201.12:04:18.61#ibcon#end of sib2, iclass 39, count 0 2006.201.12:04:18.61#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:04:18.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:04:18.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:04:18.61#ibcon#*before write, iclass 39, count 0 2006.201.12:04:18.61#ibcon#enter sib2, iclass 39, count 0 2006.201.12:04:18.61#ibcon#flushed, iclass 39, count 0 2006.201.12:04:18.61#ibcon#about to write, iclass 39, count 0 2006.201.12:04:18.61#ibcon#wrote, iclass 39, count 0 2006.201.12:04:18.61#ibcon#about to read 3, iclass 39, count 0 2006.201.12:04:18.65#ibcon#read 3, iclass 39, count 0 2006.201.12:04:18.65#ibcon#about to read 4, iclass 39, count 0 2006.201.12:04:18.65#ibcon#read 4, iclass 39, count 0 2006.201.12:04:18.65#ibcon#about to read 5, iclass 39, count 0 2006.201.12:04:18.65#ibcon#read 5, iclass 39, count 0 2006.201.12:04:18.65#ibcon#about to read 6, iclass 39, count 0 2006.201.12:04:18.65#ibcon#read 6, iclass 39, count 0 2006.201.12:04:18.65#ibcon#end of sib2, iclass 39, count 0 2006.201.12:04:18.65#ibcon#*after write, iclass 39, count 0 2006.201.12:04:18.65#ibcon#*before return 0, iclass 39, count 0 2006.201.12:04:18.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:18.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:04:18.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:04:18.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:04:18.65$vck44/vb=4,5 2006.201.12:04:18.65#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.12:04:18.65#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.12:04:18.65#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:18.65#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:18.71#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:18.71#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:18.71#ibcon#enter wrdev, iclass 2, count 2 2006.201.12:04:18.71#ibcon#first serial, iclass 2, count 2 2006.201.12:04:18.71#ibcon#enter sib2, iclass 2, count 2 2006.201.12:04:18.71#ibcon#flushed, iclass 2, count 2 2006.201.12:04:18.71#ibcon#about to write, iclass 2, count 2 2006.201.12:04:18.71#ibcon#wrote, iclass 2, count 2 2006.201.12:04:18.71#ibcon#about to read 3, iclass 2, count 2 2006.201.12:04:18.73#ibcon#read 3, iclass 2, count 2 2006.201.12:04:18.73#ibcon#about to read 4, iclass 2, count 2 2006.201.12:04:18.73#ibcon#read 4, iclass 2, count 2 2006.201.12:04:18.73#ibcon#about to read 5, iclass 2, count 2 2006.201.12:04:18.73#ibcon#read 5, iclass 2, count 2 2006.201.12:04:18.73#ibcon#about to read 6, iclass 2, count 2 2006.201.12:04:18.73#ibcon#read 6, iclass 2, count 2 2006.201.12:04:18.73#ibcon#end of sib2, iclass 2, count 2 2006.201.12:04:18.73#ibcon#*mode == 0, iclass 2, count 2 2006.201.12:04:18.73#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.12:04:18.73#ibcon#[27=AT04-05\r\n] 2006.201.12:04:18.73#ibcon#*before write, iclass 2, count 2 2006.201.12:04:18.73#ibcon#enter sib2, iclass 2, count 2 2006.201.12:04:18.73#ibcon#flushed, iclass 2, count 2 2006.201.12:04:18.73#ibcon#about to write, iclass 2, count 2 2006.201.12:04:18.73#ibcon#wrote, iclass 2, count 2 2006.201.12:04:18.73#ibcon#about to read 3, iclass 2, count 2 2006.201.12:04:18.76#ibcon#read 3, iclass 2, count 2 2006.201.12:04:18.76#ibcon#about to read 4, iclass 2, count 2 2006.201.12:04:18.76#ibcon#read 4, iclass 2, count 2 2006.201.12:04:18.76#ibcon#about to read 5, iclass 2, count 2 2006.201.12:04:18.76#ibcon#read 5, iclass 2, count 2 2006.201.12:04:18.76#ibcon#about to read 6, iclass 2, count 2 2006.201.12:04:18.76#ibcon#read 6, iclass 2, count 2 2006.201.12:04:18.76#ibcon#end of sib2, iclass 2, count 2 2006.201.12:04:18.76#ibcon#*after write, iclass 2, count 2 2006.201.12:04:18.76#ibcon#*before return 0, iclass 2, count 2 2006.201.12:04:18.76#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:18.76#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:04:18.76#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.12:04:18.76#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:18.76#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:18.88#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:18.88#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:18.88#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:04:18.88#ibcon#first serial, iclass 2, count 0 2006.201.12:04:18.88#ibcon#enter sib2, iclass 2, count 0 2006.201.12:04:18.88#ibcon#flushed, iclass 2, count 0 2006.201.12:04:18.88#ibcon#about to write, iclass 2, count 0 2006.201.12:04:18.88#ibcon#wrote, iclass 2, count 0 2006.201.12:04:18.88#ibcon#about to read 3, iclass 2, count 0 2006.201.12:04:18.90#ibcon#read 3, iclass 2, count 0 2006.201.12:04:18.90#ibcon#about to read 4, iclass 2, count 0 2006.201.12:04:18.90#ibcon#read 4, iclass 2, count 0 2006.201.12:04:18.90#ibcon#about to read 5, iclass 2, count 0 2006.201.12:04:18.90#ibcon#read 5, iclass 2, count 0 2006.201.12:04:18.90#ibcon#about to read 6, iclass 2, count 0 2006.201.12:04:18.90#ibcon#read 6, iclass 2, count 0 2006.201.12:04:18.90#ibcon#end of sib2, iclass 2, count 0 2006.201.12:04:18.90#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:04:18.90#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:04:18.90#ibcon#[27=USB\r\n] 2006.201.12:04:18.90#ibcon#*before write, iclass 2, count 0 2006.201.12:04:18.90#ibcon#enter sib2, iclass 2, count 0 2006.201.12:04:18.90#ibcon#flushed, iclass 2, count 0 2006.201.12:04:18.90#ibcon#about to write, iclass 2, count 0 2006.201.12:04:18.90#ibcon#wrote, iclass 2, count 0 2006.201.12:04:18.90#ibcon#about to read 3, iclass 2, count 0 2006.201.12:04:18.93#ibcon#read 3, iclass 2, count 0 2006.201.12:04:18.93#ibcon#about to read 4, iclass 2, count 0 2006.201.12:04:18.93#ibcon#read 4, iclass 2, count 0 2006.201.12:04:18.93#ibcon#about to read 5, iclass 2, count 0 2006.201.12:04:18.93#ibcon#read 5, iclass 2, count 0 2006.201.12:04:18.93#ibcon#about to read 6, iclass 2, count 0 2006.201.12:04:18.93#ibcon#read 6, iclass 2, count 0 2006.201.12:04:18.93#ibcon#end of sib2, iclass 2, count 0 2006.201.12:04:18.93#ibcon#*after write, iclass 2, count 0 2006.201.12:04:18.93#ibcon#*before return 0, iclass 2, count 0 2006.201.12:04:18.93#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:18.93#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:04:18.93#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:04:18.93#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:04:18.93$vck44/vblo=5,709.99 2006.201.12:04:18.93#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.12:04:18.93#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.12:04:18.93#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:18.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:18.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:18.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:18.93#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:04:18.93#ibcon#first serial, iclass 5, count 0 2006.201.12:04:18.93#ibcon#enter sib2, iclass 5, count 0 2006.201.12:04:18.93#ibcon#flushed, iclass 5, count 0 2006.201.12:04:18.93#ibcon#about to write, iclass 5, count 0 2006.201.12:04:18.93#ibcon#wrote, iclass 5, count 0 2006.201.12:04:18.93#ibcon#about to read 3, iclass 5, count 0 2006.201.12:04:18.95#ibcon#read 3, iclass 5, count 0 2006.201.12:04:18.95#ibcon#about to read 4, iclass 5, count 0 2006.201.12:04:18.95#ibcon#read 4, iclass 5, count 0 2006.201.12:04:18.95#ibcon#about to read 5, iclass 5, count 0 2006.201.12:04:18.95#ibcon#read 5, iclass 5, count 0 2006.201.12:04:18.95#ibcon#about to read 6, iclass 5, count 0 2006.201.12:04:18.95#ibcon#read 6, iclass 5, count 0 2006.201.12:04:18.95#ibcon#end of sib2, iclass 5, count 0 2006.201.12:04:18.95#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:04:18.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:04:18.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:04:18.95#ibcon#*before write, iclass 5, count 0 2006.201.12:04:18.95#ibcon#enter sib2, iclass 5, count 0 2006.201.12:04:18.95#ibcon#flushed, iclass 5, count 0 2006.201.12:04:18.95#ibcon#about to write, iclass 5, count 0 2006.201.12:04:18.95#ibcon#wrote, iclass 5, count 0 2006.201.12:04:18.95#ibcon#about to read 3, iclass 5, count 0 2006.201.12:04:18.99#ibcon#read 3, iclass 5, count 0 2006.201.12:04:18.99#ibcon#about to read 4, iclass 5, count 0 2006.201.12:04:18.99#ibcon#read 4, iclass 5, count 0 2006.201.12:04:18.99#ibcon#about to read 5, iclass 5, count 0 2006.201.12:04:18.99#ibcon#read 5, iclass 5, count 0 2006.201.12:04:18.99#ibcon#about to read 6, iclass 5, count 0 2006.201.12:04:18.99#ibcon#read 6, iclass 5, count 0 2006.201.12:04:18.99#ibcon#end of sib2, iclass 5, count 0 2006.201.12:04:18.99#ibcon#*after write, iclass 5, count 0 2006.201.12:04:18.99#ibcon#*before return 0, iclass 5, count 0 2006.201.12:04:18.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:18.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:04:18.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:04:18.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:04:18.99$vck44/vb=5,4 2006.201.12:04:18.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.12:04:18.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.12:04:18.99#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:18.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:19.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:19.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:19.05#ibcon#enter wrdev, iclass 7, count 2 2006.201.12:04:19.05#ibcon#first serial, iclass 7, count 2 2006.201.12:04:19.05#ibcon#enter sib2, iclass 7, count 2 2006.201.12:04:19.05#ibcon#flushed, iclass 7, count 2 2006.201.12:04:19.05#ibcon#about to write, iclass 7, count 2 2006.201.12:04:19.05#ibcon#wrote, iclass 7, count 2 2006.201.12:04:19.05#ibcon#about to read 3, iclass 7, count 2 2006.201.12:04:19.07#ibcon#read 3, iclass 7, count 2 2006.201.12:04:19.07#ibcon#about to read 4, iclass 7, count 2 2006.201.12:04:19.07#ibcon#read 4, iclass 7, count 2 2006.201.12:04:19.07#ibcon#about to read 5, iclass 7, count 2 2006.201.12:04:19.07#ibcon#read 5, iclass 7, count 2 2006.201.12:04:19.07#ibcon#about to read 6, iclass 7, count 2 2006.201.12:04:19.07#ibcon#read 6, iclass 7, count 2 2006.201.12:04:19.07#ibcon#end of sib2, iclass 7, count 2 2006.201.12:04:19.07#ibcon#*mode == 0, iclass 7, count 2 2006.201.12:04:19.07#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.12:04:19.07#ibcon#[27=AT05-04\r\n] 2006.201.12:04:19.07#ibcon#*before write, iclass 7, count 2 2006.201.12:04:19.07#ibcon#enter sib2, iclass 7, count 2 2006.201.12:04:19.07#ibcon#flushed, iclass 7, count 2 2006.201.12:04:19.07#ibcon#about to write, iclass 7, count 2 2006.201.12:04:19.07#ibcon#wrote, iclass 7, count 2 2006.201.12:04:19.07#ibcon#about to read 3, iclass 7, count 2 2006.201.12:04:19.10#ibcon#read 3, iclass 7, count 2 2006.201.12:04:19.10#ibcon#about to read 4, iclass 7, count 2 2006.201.12:04:19.10#ibcon#read 4, iclass 7, count 2 2006.201.12:04:19.10#ibcon#about to read 5, iclass 7, count 2 2006.201.12:04:19.10#ibcon#read 5, iclass 7, count 2 2006.201.12:04:19.10#ibcon#about to read 6, iclass 7, count 2 2006.201.12:04:19.10#ibcon#read 6, iclass 7, count 2 2006.201.12:04:19.10#ibcon#end of sib2, iclass 7, count 2 2006.201.12:04:19.10#ibcon#*after write, iclass 7, count 2 2006.201.12:04:19.10#ibcon#*before return 0, iclass 7, count 2 2006.201.12:04:19.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:19.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:04:19.10#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.12:04:19.10#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:19.10#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:19.22#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:19.22#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:19.22#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:04:19.22#ibcon#first serial, iclass 7, count 0 2006.201.12:04:19.22#ibcon#enter sib2, iclass 7, count 0 2006.201.12:04:19.22#ibcon#flushed, iclass 7, count 0 2006.201.12:04:19.22#ibcon#about to write, iclass 7, count 0 2006.201.12:04:19.22#ibcon#wrote, iclass 7, count 0 2006.201.12:04:19.22#ibcon#about to read 3, iclass 7, count 0 2006.201.12:04:19.24#ibcon#read 3, iclass 7, count 0 2006.201.12:04:19.24#ibcon#about to read 4, iclass 7, count 0 2006.201.12:04:19.24#ibcon#read 4, iclass 7, count 0 2006.201.12:04:19.24#ibcon#about to read 5, iclass 7, count 0 2006.201.12:04:19.24#ibcon#read 5, iclass 7, count 0 2006.201.12:04:19.24#ibcon#about to read 6, iclass 7, count 0 2006.201.12:04:19.24#ibcon#read 6, iclass 7, count 0 2006.201.12:04:19.24#ibcon#end of sib2, iclass 7, count 0 2006.201.12:04:19.24#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:04:19.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:04:19.24#ibcon#[27=USB\r\n] 2006.201.12:04:19.24#ibcon#*before write, iclass 7, count 0 2006.201.12:04:19.24#ibcon#enter sib2, iclass 7, count 0 2006.201.12:04:19.24#ibcon#flushed, iclass 7, count 0 2006.201.12:04:19.24#ibcon#about to write, iclass 7, count 0 2006.201.12:04:19.24#ibcon#wrote, iclass 7, count 0 2006.201.12:04:19.24#ibcon#about to read 3, iclass 7, count 0 2006.201.12:04:19.27#ibcon#read 3, iclass 7, count 0 2006.201.12:04:19.27#ibcon#about to read 4, iclass 7, count 0 2006.201.12:04:19.27#ibcon#read 4, iclass 7, count 0 2006.201.12:04:19.27#ibcon#about to read 5, iclass 7, count 0 2006.201.12:04:19.27#ibcon#read 5, iclass 7, count 0 2006.201.12:04:19.27#ibcon#about to read 6, iclass 7, count 0 2006.201.12:04:19.27#ibcon#read 6, iclass 7, count 0 2006.201.12:04:19.27#ibcon#end of sib2, iclass 7, count 0 2006.201.12:04:19.27#ibcon#*after write, iclass 7, count 0 2006.201.12:04:19.27#ibcon#*before return 0, iclass 7, count 0 2006.201.12:04:19.27#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:19.27#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:04:19.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:04:19.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:04:19.27$vck44/vblo=6,719.99 2006.201.12:04:19.27#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.12:04:19.27#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.12:04:19.27#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:19.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:19.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:19.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:19.27#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:04:19.27#ibcon#first serial, iclass 11, count 0 2006.201.12:04:19.27#ibcon#enter sib2, iclass 11, count 0 2006.201.12:04:19.27#ibcon#flushed, iclass 11, count 0 2006.201.12:04:19.27#ibcon#about to write, iclass 11, count 0 2006.201.12:04:19.27#ibcon#wrote, iclass 11, count 0 2006.201.12:04:19.27#ibcon#about to read 3, iclass 11, count 0 2006.201.12:04:19.29#ibcon#read 3, iclass 11, count 0 2006.201.12:04:19.29#ibcon#about to read 4, iclass 11, count 0 2006.201.12:04:19.29#ibcon#read 4, iclass 11, count 0 2006.201.12:04:19.29#ibcon#about to read 5, iclass 11, count 0 2006.201.12:04:19.29#ibcon#read 5, iclass 11, count 0 2006.201.12:04:19.29#ibcon#about to read 6, iclass 11, count 0 2006.201.12:04:19.29#ibcon#read 6, iclass 11, count 0 2006.201.12:04:19.29#ibcon#end of sib2, iclass 11, count 0 2006.201.12:04:19.29#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:04:19.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:04:19.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:04:19.29#ibcon#*before write, iclass 11, count 0 2006.201.12:04:19.29#ibcon#enter sib2, iclass 11, count 0 2006.201.12:04:19.29#ibcon#flushed, iclass 11, count 0 2006.201.12:04:19.29#ibcon#about to write, iclass 11, count 0 2006.201.12:04:19.29#ibcon#wrote, iclass 11, count 0 2006.201.12:04:19.29#ibcon#about to read 3, iclass 11, count 0 2006.201.12:04:19.33#ibcon#read 3, iclass 11, count 0 2006.201.12:04:19.33#ibcon#about to read 4, iclass 11, count 0 2006.201.12:04:19.33#ibcon#read 4, iclass 11, count 0 2006.201.12:04:19.33#ibcon#about to read 5, iclass 11, count 0 2006.201.12:04:19.33#ibcon#read 5, iclass 11, count 0 2006.201.12:04:19.33#ibcon#about to read 6, iclass 11, count 0 2006.201.12:04:19.33#ibcon#read 6, iclass 11, count 0 2006.201.12:04:19.33#ibcon#end of sib2, iclass 11, count 0 2006.201.12:04:19.33#ibcon#*after write, iclass 11, count 0 2006.201.12:04:19.33#ibcon#*before return 0, iclass 11, count 0 2006.201.12:04:19.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:19.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:04:19.33#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:04:19.33#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:04:19.33$vck44/vb=6,4 2006.201.12:04:19.33#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.12:04:19.33#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.12:04:19.33#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:19.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:19.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:19.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:19.39#ibcon#enter wrdev, iclass 13, count 2 2006.201.12:04:19.39#ibcon#first serial, iclass 13, count 2 2006.201.12:04:19.39#ibcon#enter sib2, iclass 13, count 2 2006.201.12:04:19.39#ibcon#flushed, iclass 13, count 2 2006.201.12:04:19.39#ibcon#about to write, iclass 13, count 2 2006.201.12:04:19.39#ibcon#wrote, iclass 13, count 2 2006.201.12:04:19.39#ibcon#about to read 3, iclass 13, count 2 2006.201.12:04:19.41#ibcon#read 3, iclass 13, count 2 2006.201.12:04:19.41#ibcon#about to read 4, iclass 13, count 2 2006.201.12:04:19.41#ibcon#read 4, iclass 13, count 2 2006.201.12:04:19.41#ibcon#about to read 5, iclass 13, count 2 2006.201.12:04:19.41#ibcon#read 5, iclass 13, count 2 2006.201.12:04:19.41#ibcon#about to read 6, iclass 13, count 2 2006.201.12:04:19.41#ibcon#read 6, iclass 13, count 2 2006.201.12:04:19.41#ibcon#end of sib2, iclass 13, count 2 2006.201.12:04:19.41#ibcon#*mode == 0, iclass 13, count 2 2006.201.12:04:19.41#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.12:04:19.41#ibcon#[27=AT06-04\r\n] 2006.201.12:04:19.41#ibcon#*before write, iclass 13, count 2 2006.201.12:04:19.41#ibcon#enter sib2, iclass 13, count 2 2006.201.12:04:19.41#ibcon#flushed, iclass 13, count 2 2006.201.12:04:19.41#ibcon#about to write, iclass 13, count 2 2006.201.12:04:19.41#ibcon#wrote, iclass 13, count 2 2006.201.12:04:19.41#ibcon#about to read 3, iclass 13, count 2 2006.201.12:04:19.44#ibcon#read 3, iclass 13, count 2 2006.201.12:04:19.44#ibcon#about to read 4, iclass 13, count 2 2006.201.12:04:19.44#ibcon#read 4, iclass 13, count 2 2006.201.12:04:19.44#ibcon#about to read 5, iclass 13, count 2 2006.201.12:04:19.44#ibcon#read 5, iclass 13, count 2 2006.201.12:04:19.44#ibcon#about to read 6, iclass 13, count 2 2006.201.12:04:19.44#ibcon#read 6, iclass 13, count 2 2006.201.12:04:19.44#ibcon#end of sib2, iclass 13, count 2 2006.201.12:04:19.44#ibcon#*after write, iclass 13, count 2 2006.201.12:04:19.44#ibcon#*before return 0, iclass 13, count 2 2006.201.12:04:19.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:19.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:04:19.44#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.12:04:19.44#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:19.44#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:19.56#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:19.56#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:19.56#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:04:19.56#ibcon#first serial, iclass 13, count 0 2006.201.12:04:19.56#ibcon#enter sib2, iclass 13, count 0 2006.201.12:04:19.56#ibcon#flushed, iclass 13, count 0 2006.201.12:04:19.56#ibcon#about to write, iclass 13, count 0 2006.201.12:04:19.56#ibcon#wrote, iclass 13, count 0 2006.201.12:04:19.56#ibcon#about to read 3, iclass 13, count 0 2006.201.12:04:19.58#ibcon#read 3, iclass 13, count 0 2006.201.12:04:19.58#ibcon#about to read 4, iclass 13, count 0 2006.201.12:04:19.58#ibcon#read 4, iclass 13, count 0 2006.201.12:04:19.58#ibcon#about to read 5, iclass 13, count 0 2006.201.12:04:19.58#ibcon#read 5, iclass 13, count 0 2006.201.12:04:19.58#ibcon#about to read 6, iclass 13, count 0 2006.201.12:04:19.58#ibcon#read 6, iclass 13, count 0 2006.201.12:04:19.58#ibcon#end of sib2, iclass 13, count 0 2006.201.12:04:19.58#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:04:19.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:04:19.58#ibcon#[27=USB\r\n] 2006.201.12:04:19.58#ibcon#*before write, iclass 13, count 0 2006.201.12:04:19.58#ibcon#enter sib2, iclass 13, count 0 2006.201.12:04:19.58#ibcon#flushed, iclass 13, count 0 2006.201.12:04:19.58#ibcon#about to write, iclass 13, count 0 2006.201.12:04:19.58#ibcon#wrote, iclass 13, count 0 2006.201.12:04:19.58#ibcon#about to read 3, iclass 13, count 0 2006.201.12:04:19.61#ibcon#read 3, iclass 13, count 0 2006.201.12:04:19.61#ibcon#about to read 4, iclass 13, count 0 2006.201.12:04:19.61#ibcon#read 4, iclass 13, count 0 2006.201.12:04:19.61#ibcon#about to read 5, iclass 13, count 0 2006.201.12:04:19.61#ibcon#read 5, iclass 13, count 0 2006.201.12:04:19.61#ibcon#about to read 6, iclass 13, count 0 2006.201.12:04:19.61#ibcon#read 6, iclass 13, count 0 2006.201.12:04:19.61#ibcon#end of sib2, iclass 13, count 0 2006.201.12:04:19.61#ibcon#*after write, iclass 13, count 0 2006.201.12:04:19.61#ibcon#*before return 0, iclass 13, count 0 2006.201.12:04:19.61#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:19.61#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:04:19.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:04:19.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:04:19.61$vck44/vblo=7,734.99 2006.201.12:04:19.61#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.12:04:19.61#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.12:04:19.61#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:19.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:19.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:19.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:19.61#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:04:19.61#ibcon#first serial, iclass 15, count 0 2006.201.12:04:19.61#ibcon#enter sib2, iclass 15, count 0 2006.201.12:04:19.61#ibcon#flushed, iclass 15, count 0 2006.201.12:04:19.61#ibcon#about to write, iclass 15, count 0 2006.201.12:04:19.61#ibcon#wrote, iclass 15, count 0 2006.201.12:04:19.61#ibcon#about to read 3, iclass 15, count 0 2006.201.12:04:19.63#ibcon#read 3, iclass 15, count 0 2006.201.12:04:19.63#ibcon#about to read 4, iclass 15, count 0 2006.201.12:04:19.63#ibcon#read 4, iclass 15, count 0 2006.201.12:04:19.63#ibcon#about to read 5, iclass 15, count 0 2006.201.12:04:19.63#ibcon#read 5, iclass 15, count 0 2006.201.12:04:19.63#ibcon#about to read 6, iclass 15, count 0 2006.201.12:04:19.63#ibcon#read 6, iclass 15, count 0 2006.201.12:04:19.63#ibcon#end of sib2, iclass 15, count 0 2006.201.12:04:19.63#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:04:19.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:04:19.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:04:19.63#ibcon#*before write, iclass 15, count 0 2006.201.12:04:19.63#ibcon#enter sib2, iclass 15, count 0 2006.201.12:04:19.63#ibcon#flushed, iclass 15, count 0 2006.201.12:04:19.63#ibcon#about to write, iclass 15, count 0 2006.201.12:04:19.63#ibcon#wrote, iclass 15, count 0 2006.201.12:04:19.63#ibcon#about to read 3, iclass 15, count 0 2006.201.12:04:19.67#ibcon#read 3, iclass 15, count 0 2006.201.12:04:19.67#ibcon#about to read 4, iclass 15, count 0 2006.201.12:04:19.67#ibcon#read 4, iclass 15, count 0 2006.201.12:04:19.67#ibcon#about to read 5, iclass 15, count 0 2006.201.12:04:19.67#ibcon#read 5, iclass 15, count 0 2006.201.12:04:19.67#ibcon#about to read 6, iclass 15, count 0 2006.201.12:04:19.67#ibcon#read 6, iclass 15, count 0 2006.201.12:04:19.67#ibcon#end of sib2, iclass 15, count 0 2006.201.12:04:19.67#ibcon#*after write, iclass 15, count 0 2006.201.12:04:19.67#ibcon#*before return 0, iclass 15, count 0 2006.201.12:04:19.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:19.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:04:19.67#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:04:19.67#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:04:19.67$vck44/vb=7,4 2006.201.12:04:19.67#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.12:04:19.67#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.12:04:19.67#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:19.67#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:19.73#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:19.73#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:19.73#ibcon#enter wrdev, iclass 17, count 2 2006.201.12:04:19.73#ibcon#first serial, iclass 17, count 2 2006.201.12:04:19.73#ibcon#enter sib2, iclass 17, count 2 2006.201.12:04:19.73#ibcon#flushed, iclass 17, count 2 2006.201.12:04:19.73#ibcon#about to write, iclass 17, count 2 2006.201.12:04:19.73#ibcon#wrote, iclass 17, count 2 2006.201.12:04:19.73#ibcon#about to read 3, iclass 17, count 2 2006.201.12:04:19.75#ibcon#read 3, iclass 17, count 2 2006.201.12:04:19.75#ibcon#about to read 4, iclass 17, count 2 2006.201.12:04:19.75#ibcon#read 4, iclass 17, count 2 2006.201.12:04:19.75#ibcon#about to read 5, iclass 17, count 2 2006.201.12:04:19.75#ibcon#read 5, iclass 17, count 2 2006.201.12:04:19.75#ibcon#about to read 6, iclass 17, count 2 2006.201.12:04:19.75#ibcon#read 6, iclass 17, count 2 2006.201.12:04:19.75#ibcon#end of sib2, iclass 17, count 2 2006.201.12:04:19.75#ibcon#*mode == 0, iclass 17, count 2 2006.201.12:04:19.75#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.12:04:19.75#ibcon#[27=AT07-04\r\n] 2006.201.12:04:19.75#ibcon#*before write, iclass 17, count 2 2006.201.12:04:19.75#ibcon#enter sib2, iclass 17, count 2 2006.201.12:04:19.75#ibcon#flushed, iclass 17, count 2 2006.201.12:04:19.75#ibcon#about to write, iclass 17, count 2 2006.201.12:04:19.75#ibcon#wrote, iclass 17, count 2 2006.201.12:04:19.75#ibcon#about to read 3, iclass 17, count 2 2006.201.12:04:19.78#ibcon#read 3, iclass 17, count 2 2006.201.12:04:19.78#ibcon#about to read 4, iclass 17, count 2 2006.201.12:04:19.78#ibcon#read 4, iclass 17, count 2 2006.201.12:04:19.78#ibcon#about to read 5, iclass 17, count 2 2006.201.12:04:19.78#ibcon#read 5, iclass 17, count 2 2006.201.12:04:19.78#ibcon#about to read 6, iclass 17, count 2 2006.201.12:04:19.78#ibcon#read 6, iclass 17, count 2 2006.201.12:04:19.78#ibcon#end of sib2, iclass 17, count 2 2006.201.12:04:19.78#ibcon#*after write, iclass 17, count 2 2006.201.12:04:19.78#ibcon#*before return 0, iclass 17, count 2 2006.201.12:04:19.78#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:19.78#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:04:19.78#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.12:04:19.78#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:19.78#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:19.90#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:19.90#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:19.90#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:04:19.90#ibcon#first serial, iclass 17, count 0 2006.201.12:04:19.90#ibcon#enter sib2, iclass 17, count 0 2006.201.12:04:19.90#ibcon#flushed, iclass 17, count 0 2006.201.12:04:19.90#ibcon#about to write, iclass 17, count 0 2006.201.12:04:19.90#ibcon#wrote, iclass 17, count 0 2006.201.12:04:19.90#ibcon#about to read 3, iclass 17, count 0 2006.201.12:04:19.92#ibcon#read 3, iclass 17, count 0 2006.201.12:04:19.92#ibcon#about to read 4, iclass 17, count 0 2006.201.12:04:19.92#ibcon#read 4, iclass 17, count 0 2006.201.12:04:19.92#ibcon#about to read 5, iclass 17, count 0 2006.201.12:04:19.92#ibcon#read 5, iclass 17, count 0 2006.201.12:04:19.92#ibcon#about to read 6, iclass 17, count 0 2006.201.12:04:19.92#ibcon#read 6, iclass 17, count 0 2006.201.12:04:19.92#ibcon#end of sib2, iclass 17, count 0 2006.201.12:04:19.92#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:04:19.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:04:19.92#ibcon#[27=USB\r\n] 2006.201.12:04:19.92#ibcon#*before write, iclass 17, count 0 2006.201.12:04:19.92#ibcon#enter sib2, iclass 17, count 0 2006.201.12:04:19.92#ibcon#flushed, iclass 17, count 0 2006.201.12:04:19.92#ibcon#about to write, iclass 17, count 0 2006.201.12:04:19.92#ibcon#wrote, iclass 17, count 0 2006.201.12:04:19.92#ibcon#about to read 3, iclass 17, count 0 2006.201.12:04:19.95#ibcon#read 3, iclass 17, count 0 2006.201.12:04:19.95#ibcon#about to read 4, iclass 17, count 0 2006.201.12:04:19.95#ibcon#read 4, iclass 17, count 0 2006.201.12:04:19.95#ibcon#about to read 5, iclass 17, count 0 2006.201.12:04:19.95#ibcon#read 5, iclass 17, count 0 2006.201.12:04:19.95#ibcon#about to read 6, iclass 17, count 0 2006.201.12:04:19.95#ibcon#read 6, iclass 17, count 0 2006.201.12:04:19.95#ibcon#end of sib2, iclass 17, count 0 2006.201.12:04:19.95#ibcon#*after write, iclass 17, count 0 2006.201.12:04:19.95#ibcon#*before return 0, iclass 17, count 0 2006.201.12:04:19.95#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:19.95#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:04:19.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:04:19.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:04:19.95$vck44/vblo=8,744.99 2006.201.12:04:19.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.12:04:19.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.12:04:19.95#ibcon#ireg 17 cls_cnt 0 2006.201.12:04:19.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:19.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:19.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:19.95#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:04:19.95#ibcon#first serial, iclass 19, count 0 2006.201.12:04:19.95#ibcon#enter sib2, iclass 19, count 0 2006.201.12:04:19.95#ibcon#flushed, iclass 19, count 0 2006.201.12:04:19.95#ibcon#about to write, iclass 19, count 0 2006.201.12:04:19.95#ibcon#wrote, iclass 19, count 0 2006.201.12:04:19.95#ibcon#about to read 3, iclass 19, count 0 2006.201.12:04:19.97#ibcon#read 3, iclass 19, count 0 2006.201.12:04:19.97#ibcon#about to read 4, iclass 19, count 0 2006.201.12:04:19.97#ibcon#read 4, iclass 19, count 0 2006.201.12:04:19.97#ibcon#about to read 5, iclass 19, count 0 2006.201.12:04:19.97#ibcon#read 5, iclass 19, count 0 2006.201.12:04:19.97#ibcon#about to read 6, iclass 19, count 0 2006.201.12:04:19.97#ibcon#read 6, iclass 19, count 0 2006.201.12:04:19.97#ibcon#end of sib2, iclass 19, count 0 2006.201.12:04:19.97#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:04:19.97#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:04:19.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:04:19.97#ibcon#*before write, iclass 19, count 0 2006.201.12:04:19.97#ibcon#enter sib2, iclass 19, count 0 2006.201.12:04:19.97#ibcon#flushed, iclass 19, count 0 2006.201.12:04:19.97#ibcon#about to write, iclass 19, count 0 2006.201.12:04:19.97#ibcon#wrote, iclass 19, count 0 2006.201.12:04:19.97#ibcon#about to read 3, iclass 19, count 0 2006.201.12:04:20.01#ibcon#read 3, iclass 19, count 0 2006.201.12:04:20.01#ibcon#about to read 4, iclass 19, count 0 2006.201.12:04:20.01#ibcon#read 4, iclass 19, count 0 2006.201.12:04:20.01#ibcon#about to read 5, iclass 19, count 0 2006.201.12:04:20.01#ibcon#read 5, iclass 19, count 0 2006.201.12:04:20.01#ibcon#about to read 6, iclass 19, count 0 2006.201.12:04:20.01#ibcon#read 6, iclass 19, count 0 2006.201.12:04:20.01#ibcon#end of sib2, iclass 19, count 0 2006.201.12:04:20.01#ibcon#*after write, iclass 19, count 0 2006.201.12:04:20.01#ibcon#*before return 0, iclass 19, count 0 2006.201.12:04:20.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:20.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:04:20.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:04:20.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:04:20.01$vck44/vb=8,4 2006.201.12:04:20.01#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.12:04:20.01#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.12:04:20.01#ibcon#ireg 11 cls_cnt 2 2006.201.12:04:20.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:20.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:20.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:20.07#ibcon#enter wrdev, iclass 21, count 2 2006.201.12:04:20.07#ibcon#first serial, iclass 21, count 2 2006.201.12:04:20.07#ibcon#enter sib2, iclass 21, count 2 2006.201.12:04:20.07#ibcon#flushed, iclass 21, count 2 2006.201.12:04:20.07#ibcon#about to write, iclass 21, count 2 2006.201.12:04:20.07#ibcon#wrote, iclass 21, count 2 2006.201.12:04:20.07#ibcon#about to read 3, iclass 21, count 2 2006.201.12:04:20.09#ibcon#read 3, iclass 21, count 2 2006.201.12:04:20.09#ibcon#about to read 4, iclass 21, count 2 2006.201.12:04:20.09#ibcon#read 4, iclass 21, count 2 2006.201.12:04:20.09#ibcon#about to read 5, iclass 21, count 2 2006.201.12:04:20.09#ibcon#read 5, iclass 21, count 2 2006.201.12:04:20.09#ibcon#about to read 6, iclass 21, count 2 2006.201.12:04:20.09#ibcon#read 6, iclass 21, count 2 2006.201.12:04:20.09#ibcon#end of sib2, iclass 21, count 2 2006.201.12:04:20.09#ibcon#*mode == 0, iclass 21, count 2 2006.201.12:04:20.09#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.12:04:20.09#ibcon#[27=AT08-04\r\n] 2006.201.12:04:20.09#ibcon#*before write, iclass 21, count 2 2006.201.12:04:20.09#ibcon#enter sib2, iclass 21, count 2 2006.201.12:04:20.09#ibcon#flushed, iclass 21, count 2 2006.201.12:04:20.09#ibcon#about to write, iclass 21, count 2 2006.201.12:04:20.09#ibcon#wrote, iclass 21, count 2 2006.201.12:04:20.09#ibcon#about to read 3, iclass 21, count 2 2006.201.12:04:20.12#ibcon#read 3, iclass 21, count 2 2006.201.12:04:20.12#ibcon#about to read 4, iclass 21, count 2 2006.201.12:04:20.12#ibcon#read 4, iclass 21, count 2 2006.201.12:04:20.12#ibcon#about to read 5, iclass 21, count 2 2006.201.12:04:20.12#ibcon#read 5, iclass 21, count 2 2006.201.12:04:20.12#ibcon#about to read 6, iclass 21, count 2 2006.201.12:04:20.12#ibcon#read 6, iclass 21, count 2 2006.201.12:04:20.12#ibcon#end of sib2, iclass 21, count 2 2006.201.12:04:20.12#ibcon#*after write, iclass 21, count 2 2006.201.12:04:20.12#ibcon#*before return 0, iclass 21, count 2 2006.201.12:04:20.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:20.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:04:20.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.12:04:20.12#ibcon#ireg 7 cls_cnt 0 2006.201.12:04:20.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:20.14#abcon#<5=/04 1.9 4.2 21.271001004.0\r\n> 2006.201.12:04:20.16#abcon#{5=INTERFACE CLEAR} 2006.201.12:04:20.22#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:04:20.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:20.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:20.24#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:04:20.24#ibcon#first serial, iclass 21, count 0 2006.201.12:04:20.24#ibcon#enter sib2, iclass 21, count 0 2006.201.12:04:20.24#ibcon#flushed, iclass 21, count 0 2006.201.12:04:20.24#ibcon#about to write, iclass 21, count 0 2006.201.12:04:20.24#ibcon#wrote, iclass 21, count 0 2006.201.12:04:20.24#ibcon#about to read 3, iclass 21, count 0 2006.201.12:04:20.26#ibcon#read 3, iclass 21, count 0 2006.201.12:04:20.26#ibcon#about to read 4, iclass 21, count 0 2006.201.12:04:20.26#ibcon#read 4, iclass 21, count 0 2006.201.12:04:20.26#ibcon#about to read 5, iclass 21, count 0 2006.201.12:04:20.26#ibcon#read 5, iclass 21, count 0 2006.201.12:04:20.26#ibcon#about to read 6, iclass 21, count 0 2006.201.12:04:20.26#ibcon#read 6, iclass 21, count 0 2006.201.12:04:20.26#ibcon#end of sib2, iclass 21, count 0 2006.201.12:04:20.26#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:04:20.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:04:20.26#ibcon#[27=USB\r\n] 2006.201.12:04:20.26#ibcon#*before write, iclass 21, count 0 2006.201.12:04:20.26#ibcon#enter sib2, iclass 21, count 0 2006.201.12:04:20.26#ibcon#flushed, iclass 21, count 0 2006.201.12:04:20.26#ibcon#about to write, iclass 21, count 0 2006.201.12:04:20.26#ibcon#wrote, iclass 21, count 0 2006.201.12:04:20.26#ibcon#about to read 3, iclass 21, count 0 2006.201.12:04:20.29#ibcon#read 3, iclass 21, count 0 2006.201.12:04:20.29#ibcon#about to read 4, iclass 21, count 0 2006.201.12:04:20.29#ibcon#read 4, iclass 21, count 0 2006.201.12:04:20.29#ibcon#about to read 5, iclass 21, count 0 2006.201.12:04:20.29#ibcon#read 5, iclass 21, count 0 2006.201.12:04:20.29#ibcon#about to read 6, iclass 21, count 0 2006.201.12:04:20.29#ibcon#read 6, iclass 21, count 0 2006.201.12:04:20.29#ibcon#end of sib2, iclass 21, count 0 2006.201.12:04:20.29#ibcon#*after write, iclass 21, count 0 2006.201.12:04:20.29#ibcon#*before return 0, iclass 21, count 0 2006.201.12:04:20.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:20.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:04:20.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:04:20.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:04:20.29$vck44/vabw=wide 2006.201.12:04:20.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.12:04:20.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.12:04:20.29#ibcon#ireg 8 cls_cnt 0 2006.201.12:04:20.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:20.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:20.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:20.29#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:04:20.29#ibcon#first serial, iclass 27, count 0 2006.201.12:04:20.29#ibcon#enter sib2, iclass 27, count 0 2006.201.12:04:20.29#ibcon#flushed, iclass 27, count 0 2006.201.12:04:20.29#ibcon#about to write, iclass 27, count 0 2006.201.12:04:20.29#ibcon#wrote, iclass 27, count 0 2006.201.12:04:20.29#ibcon#about to read 3, iclass 27, count 0 2006.201.12:04:20.31#ibcon#read 3, iclass 27, count 0 2006.201.12:04:20.31#ibcon#about to read 4, iclass 27, count 0 2006.201.12:04:20.31#ibcon#read 4, iclass 27, count 0 2006.201.12:04:20.31#ibcon#about to read 5, iclass 27, count 0 2006.201.12:04:20.31#ibcon#read 5, iclass 27, count 0 2006.201.12:04:20.31#ibcon#about to read 6, iclass 27, count 0 2006.201.12:04:20.31#ibcon#read 6, iclass 27, count 0 2006.201.12:04:20.31#ibcon#end of sib2, iclass 27, count 0 2006.201.12:04:20.31#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:04:20.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:04:20.31#ibcon#[25=BW32\r\n] 2006.201.12:04:20.31#ibcon#*before write, iclass 27, count 0 2006.201.12:04:20.31#ibcon#enter sib2, iclass 27, count 0 2006.201.12:04:20.31#ibcon#flushed, iclass 27, count 0 2006.201.12:04:20.31#ibcon#about to write, iclass 27, count 0 2006.201.12:04:20.31#ibcon#wrote, iclass 27, count 0 2006.201.12:04:20.31#ibcon#about to read 3, iclass 27, count 0 2006.201.12:04:20.34#ibcon#read 3, iclass 27, count 0 2006.201.12:04:20.34#ibcon#about to read 4, iclass 27, count 0 2006.201.12:04:20.34#ibcon#read 4, iclass 27, count 0 2006.201.12:04:20.34#ibcon#about to read 5, iclass 27, count 0 2006.201.12:04:20.34#ibcon#read 5, iclass 27, count 0 2006.201.12:04:20.34#ibcon#about to read 6, iclass 27, count 0 2006.201.12:04:20.34#ibcon#read 6, iclass 27, count 0 2006.201.12:04:20.34#ibcon#end of sib2, iclass 27, count 0 2006.201.12:04:20.34#ibcon#*after write, iclass 27, count 0 2006.201.12:04:20.34#ibcon#*before return 0, iclass 27, count 0 2006.201.12:04:20.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:20.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:04:20.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:04:20.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:04:20.34$vck44/vbbw=wide 2006.201.12:04:20.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.12:04:20.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.12:04:20.34#ibcon#ireg 8 cls_cnt 0 2006.201.12:04:20.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:04:20.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:04:20.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:04:20.41#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:04:20.41#ibcon#first serial, iclass 29, count 0 2006.201.12:04:20.41#ibcon#enter sib2, iclass 29, count 0 2006.201.12:04:20.41#ibcon#flushed, iclass 29, count 0 2006.201.12:04:20.41#ibcon#about to write, iclass 29, count 0 2006.201.12:04:20.41#ibcon#wrote, iclass 29, count 0 2006.201.12:04:20.41#ibcon#about to read 3, iclass 29, count 0 2006.201.12:04:20.43#ibcon#read 3, iclass 29, count 0 2006.201.12:04:20.43#ibcon#about to read 4, iclass 29, count 0 2006.201.12:04:20.43#ibcon#read 4, iclass 29, count 0 2006.201.12:04:20.43#ibcon#about to read 5, iclass 29, count 0 2006.201.12:04:20.43#ibcon#read 5, iclass 29, count 0 2006.201.12:04:20.43#ibcon#about to read 6, iclass 29, count 0 2006.201.12:04:20.43#ibcon#read 6, iclass 29, count 0 2006.201.12:04:20.43#ibcon#end of sib2, iclass 29, count 0 2006.201.12:04:20.43#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:04:20.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:04:20.43#ibcon#[27=BW32\r\n] 2006.201.12:04:20.43#ibcon#*before write, iclass 29, count 0 2006.201.12:04:20.43#ibcon#enter sib2, iclass 29, count 0 2006.201.12:04:20.43#ibcon#flushed, iclass 29, count 0 2006.201.12:04:20.43#ibcon#about to write, iclass 29, count 0 2006.201.12:04:20.43#ibcon#wrote, iclass 29, count 0 2006.201.12:04:20.43#ibcon#about to read 3, iclass 29, count 0 2006.201.12:04:20.46#ibcon#read 3, iclass 29, count 0 2006.201.12:04:20.46#ibcon#about to read 4, iclass 29, count 0 2006.201.12:04:20.46#ibcon#read 4, iclass 29, count 0 2006.201.12:04:20.46#ibcon#about to read 5, iclass 29, count 0 2006.201.12:04:20.46#ibcon#read 5, iclass 29, count 0 2006.201.12:04:20.46#ibcon#about to read 6, iclass 29, count 0 2006.201.12:04:20.46#ibcon#read 6, iclass 29, count 0 2006.201.12:04:20.46#ibcon#end of sib2, iclass 29, count 0 2006.201.12:04:20.46#ibcon#*after write, iclass 29, count 0 2006.201.12:04:20.46#ibcon#*before return 0, iclass 29, count 0 2006.201.12:04:20.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:04:20.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:04:20.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:04:20.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:04:20.46$setupk4/ifdk4 2006.201.12:04:20.46$ifdk4/lo= 2006.201.12:04:20.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:04:20.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:04:20.46$ifdk4/patch= 2006.201.12:04:20.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:04:20.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:04:20.46$setupk4/!*+20s 2006.201.12:04:30.31#abcon#<5=/04 1.9 4.2 21.271001004.0\r\n> 2006.201.12:04:30.33#abcon#{5=INTERFACE CLEAR} 2006.201.12:04:30.39#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:04:34.94$setupk4/"tpicd 2006.201.12:04:34.94$setupk4/echo=off 2006.201.12:04:34.94$setupk4/xlog=off 2006.201.12:04:34.94:!2006.201.12:05:38 2006.201.12:04:41.14#trakl#Source acquired 2006.201.12:04:43.14#flagr#flagr/antenna,acquired 2006.201.12:05:38.00:preob 2006.201.12:05:38.13/onsource/TRACKING 2006.201.12:05:38.13:!2006.201.12:05:48 2006.201.12:05:48.00:"tape 2006.201.12:05:48.00:"st=record 2006.201.12:05:48.00:data_valid=on 2006.201.12:05:48.00:midob 2006.201.12:05:49.13/onsource/TRACKING 2006.201.12:05:49.13/wx/21.26,1004.0,100 2006.201.12:05:49.33/cable/+6.4716E-03 2006.201.12:05:50.42/va/01,08,usb,yes,29,31 2006.201.12:05:50.42/va/02,07,usb,yes,32,32 2006.201.12:05:50.42/va/03,08,usb,yes,28,30 2006.201.12:05:50.42/va/04,07,usb,yes,32,34 2006.201.12:05:50.42/va/05,04,usb,yes,29,29 2006.201.12:05:50.42/va/06,05,usb,yes,29,29 2006.201.12:05:50.42/va/07,05,usb,yes,28,29 2006.201.12:05:50.42/va/08,04,usb,yes,28,33 2006.201.12:05:50.65/valo/01,524.99,yes,locked 2006.201.12:05:50.65/valo/02,534.99,yes,locked 2006.201.12:05:50.65/valo/03,564.99,yes,locked 2006.201.12:05:50.65/valo/04,624.99,yes,locked 2006.201.12:05:50.65/valo/05,734.99,yes,locked 2006.201.12:05:50.65/valo/06,814.99,yes,locked 2006.201.12:05:50.65/valo/07,864.99,yes,locked 2006.201.12:05:50.65/valo/08,884.99,yes,locked 2006.201.12:05:51.74/vb/01,04,usb,yes,29,27 2006.201.12:05:51.74/vb/02,05,usb,yes,27,27 2006.201.12:05:51.74/vb/03,04,usb,yes,28,31 2006.201.12:05:51.74/vb/04,05,usb,yes,28,28 2006.201.12:05:51.74/vb/05,04,usb,yes,25,28 2006.201.12:05:51.74/vb/06,04,usb,yes,29,26 2006.201.12:05:51.74/vb/07,04,usb,yes,29,29 2006.201.12:05:51.74/vb/08,04,usb,yes,27,30 2006.201.12:05:51.97/vblo/01,629.99,yes,locked 2006.201.12:05:51.97/vblo/02,634.99,yes,locked 2006.201.12:05:51.97/vblo/03,649.99,yes,locked 2006.201.12:05:51.97/vblo/04,679.99,yes,locked 2006.201.12:05:51.97/vblo/05,709.99,yes,locked 2006.201.12:05:51.97/vblo/06,719.99,yes,locked 2006.201.12:05:51.97/vblo/07,734.99,yes,locked 2006.201.12:05:51.97/vblo/08,744.99,yes,locked 2006.201.12:05:52.12/vabw/8 2006.201.12:05:52.27/vbbw/8 2006.201.12:05:52.36/xfe/off,on,15.2 2006.201.12:05:52.75/ifatt/23,28,28,28 2006.201.12:05:53.06/fmout-gps/S +4.59E-07 2006.201.12:05:53.13:!2006.201.12:07:08 2006.201.12:07:08.00:data_valid=off 2006.201.12:07:08.00:"et 2006.201.12:07:08.00:!+3s 2006.201.12:07:11.02:"tape 2006.201.12:07:11.02:postob 2006.201.12:07:11.20/cable/+6.4730E-03 2006.201.12:07:11.20/wx/21.26,1004.0,100 2006.201.12:07:11.28/fmout-gps/S +4.60E-07 2006.201.12:07:11.28:scan_name=201-1210,jd0607,40 2006.201.12:07:11.28:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.201.12:07:12.13#flagr#flagr/antenna,new-source 2006.201.12:07:12.13:checkk5 2006.201.12:07:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:07:12.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:07:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:07:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:07:13.99/chk_obsdata//k5ts1/T2011205??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.12:07:14.35/chk_obsdata//k5ts2/T2011205??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.12:07:14.72/chk_obsdata//k5ts3/T2011205??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.12:07:15.09/chk_obsdata//k5ts4/T2011205??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.12:07:15.78/k5log//k5ts1_log_newline 2006.201.12:07:16.47/k5log//k5ts2_log_newline 2006.201.12:07:17.16/k5log//k5ts3_log_newline 2006.201.12:07:17.85/k5log//k5ts4_log_newline 2006.201.12:07:17.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:07:17.87:setupk4=1 2006.201.12:07:17.87$setupk4/echo=on 2006.201.12:07:17.87$setupk4/pcalon 2006.201.12:07:17.87$pcalon/"no phase cal control is implemented here 2006.201.12:07:17.87$setupk4/"tpicd=stop 2006.201.12:07:17.87$setupk4/"rec=synch_on 2006.201.12:07:17.87$setupk4/"rec_mode=128 2006.201.12:07:17.87$setupk4/!* 2006.201.12:07:17.87$setupk4/recpk4 2006.201.12:07:17.87$recpk4/recpatch= 2006.201.12:07:17.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:07:17.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:07:17.88$setupk4/vck44 2006.201.12:07:17.88$vck44/valo=1,524.99 2006.201.12:07:17.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.12:07:17.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.12:07:17.88#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:17.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:17.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:17.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:17.88#ibcon#enter wrdev, iclass 30, count 0 2006.201.12:07:17.88#ibcon#first serial, iclass 30, count 0 2006.201.12:07:17.88#ibcon#enter sib2, iclass 30, count 0 2006.201.12:07:17.88#ibcon#flushed, iclass 30, count 0 2006.201.12:07:17.88#ibcon#about to write, iclass 30, count 0 2006.201.12:07:17.88#ibcon#wrote, iclass 30, count 0 2006.201.12:07:17.88#ibcon#about to read 3, iclass 30, count 0 2006.201.12:07:17.92#ibcon#read 3, iclass 30, count 0 2006.201.12:07:17.92#ibcon#about to read 4, iclass 30, count 0 2006.201.12:07:17.92#ibcon#read 4, iclass 30, count 0 2006.201.12:07:17.92#ibcon#about to read 5, iclass 30, count 0 2006.201.12:07:17.92#ibcon#read 5, iclass 30, count 0 2006.201.12:07:17.92#ibcon#about to read 6, iclass 30, count 0 2006.201.12:07:17.92#ibcon#read 6, iclass 30, count 0 2006.201.12:07:17.92#ibcon#end of sib2, iclass 30, count 0 2006.201.12:07:17.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.12:07:17.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.12:07:17.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:07:17.92#ibcon#*before write, iclass 30, count 0 2006.201.12:07:17.92#ibcon#enter sib2, iclass 30, count 0 2006.201.12:07:17.92#ibcon#flushed, iclass 30, count 0 2006.201.12:07:17.92#ibcon#about to write, iclass 30, count 0 2006.201.12:07:17.92#ibcon#wrote, iclass 30, count 0 2006.201.12:07:17.92#ibcon#about to read 3, iclass 30, count 0 2006.201.12:07:17.97#ibcon#read 3, iclass 30, count 0 2006.201.12:07:17.97#ibcon#about to read 4, iclass 30, count 0 2006.201.12:07:17.97#ibcon#read 4, iclass 30, count 0 2006.201.12:07:17.97#ibcon#about to read 5, iclass 30, count 0 2006.201.12:07:17.97#ibcon#read 5, iclass 30, count 0 2006.201.12:07:17.97#ibcon#about to read 6, iclass 30, count 0 2006.201.12:07:17.97#ibcon#read 6, iclass 30, count 0 2006.201.12:07:17.97#ibcon#end of sib2, iclass 30, count 0 2006.201.12:07:17.97#ibcon#*after write, iclass 30, count 0 2006.201.12:07:17.97#ibcon#*before return 0, iclass 30, count 0 2006.201.12:07:17.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:17.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:17.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.12:07:17.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.12:07:17.97$vck44/va=1,8 2006.201.12:07:17.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.12:07:17.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.12:07:17.97#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:17.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:17.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:17.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:17.97#ibcon#enter wrdev, iclass 32, count 2 2006.201.12:07:17.97#ibcon#first serial, iclass 32, count 2 2006.201.12:07:17.97#ibcon#enter sib2, iclass 32, count 2 2006.201.12:07:17.97#ibcon#flushed, iclass 32, count 2 2006.201.12:07:17.97#ibcon#about to write, iclass 32, count 2 2006.201.12:07:17.97#ibcon#wrote, iclass 32, count 2 2006.201.12:07:17.97#ibcon#about to read 3, iclass 32, count 2 2006.201.12:07:17.99#ibcon#read 3, iclass 32, count 2 2006.201.12:07:17.99#ibcon#about to read 4, iclass 32, count 2 2006.201.12:07:17.99#ibcon#read 4, iclass 32, count 2 2006.201.12:07:17.99#ibcon#about to read 5, iclass 32, count 2 2006.201.12:07:17.99#ibcon#read 5, iclass 32, count 2 2006.201.12:07:17.99#ibcon#about to read 6, iclass 32, count 2 2006.201.12:07:17.99#ibcon#read 6, iclass 32, count 2 2006.201.12:07:17.99#ibcon#end of sib2, iclass 32, count 2 2006.201.12:07:17.99#ibcon#*mode == 0, iclass 32, count 2 2006.201.12:07:17.99#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.12:07:17.99#ibcon#[25=AT01-08\r\n] 2006.201.12:07:17.99#ibcon#*before write, iclass 32, count 2 2006.201.12:07:17.99#ibcon#enter sib2, iclass 32, count 2 2006.201.12:07:17.99#ibcon#flushed, iclass 32, count 2 2006.201.12:07:17.99#ibcon#about to write, iclass 32, count 2 2006.201.12:07:17.99#ibcon#wrote, iclass 32, count 2 2006.201.12:07:17.99#ibcon#about to read 3, iclass 32, count 2 2006.201.12:07:18.03#ibcon#read 3, iclass 32, count 2 2006.201.12:07:18.03#ibcon#about to read 4, iclass 32, count 2 2006.201.12:07:18.03#ibcon#read 4, iclass 32, count 2 2006.201.12:07:18.03#ibcon#about to read 5, iclass 32, count 2 2006.201.12:07:18.03#ibcon#read 5, iclass 32, count 2 2006.201.12:07:18.03#ibcon#about to read 6, iclass 32, count 2 2006.201.12:07:18.03#ibcon#read 6, iclass 32, count 2 2006.201.12:07:18.03#ibcon#end of sib2, iclass 32, count 2 2006.201.12:07:18.03#ibcon#*after write, iclass 32, count 2 2006.201.12:07:18.03#ibcon#*before return 0, iclass 32, count 2 2006.201.12:07:18.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:18.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:18.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.12:07:18.03#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:18.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:18.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:18.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:18.15#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:07:18.15#ibcon#first serial, iclass 32, count 0 2006.201.12:07:18.15#ibcon#enter sib2, iclass 32, count 0 2006.201.12:07:18.15#ibcon#flushed, iclass 32, count 0 2006.201.12:07:18.15#ibcon#about to write, iclass 32, count 0 2006.201.12:07:18.15#ibcon#wrote, iclass 32, count 0 2006.201.12:07:18.15#ibcon#about to read 3, iclass 32, count 0 2006.201.12:07:18.17#ibcon#read 3, iclass 32, count 0 2006.201.12:07:18.17#ibcon#about to read 4, iclass 32, count 0 2006.201.12:07:18.17#ibcon#read 4, iclass 32, count 0 2006.201.12:07:18.17#ibcon#about to read 5, iclass 32, count 0 2006.201.12:07:18.17#ibcon#read 5, iclass 32, count 0 2006.201.12:07:18.17#ibcon#about to read 6, iclass 32, count 0 2006.201.12:07:18.17#ibcon#read 6, iclass 32, count 0 2006.201.12:07:18.17#ibcon#end of sib2, iclass 32, count 0 2006.201.12:07:18.17#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:07:18.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:07:18.17#ibcon#[25=USB\r\n] 2006.201.12:07:18.17#ibcon#*before write, iclass 32, count 0 2006.201.12:07:18.17#ibcon#enter sib2, iclass 32, count 0 2006.201.12:07:18.17#ibcon#flushed, iclass 32, count 0 2006.201.12:07:18.17#ibcon#about to write, iclass 32, count 0 2006.201.12:07:18.17#ibcon#wrote, iclass 32, count 0 2006.201.12:07:18.17#ibcon#about to read 3, iclass 32, count 0 2006.201.12:07:18.20#ibcon#read 3, iclass 32, count 0 2006.201.12:07:18.20#ibcon#about to read 4, iclass 32, count 0 2006.201.12:07:18.20#ibcon#read 4, iclass 32, count 0 2006.201.12:07:18.20#ibcon#about to read 5, iclass 32, count 0 2006.201.12:07:18.20#ibcon#read 5, iclass 32, count 0 2006.201.12:07:18.20#ibcon#about to read 6, iclass 32, count 0 2006.201.12:07:18.20#ibcon#read 6, iclass 32, count 0 2006.201.12:07:18.20#ibcon#end of sib2, iclass 32, count 0 2006.201.12:07:18.20#ibcon#*after write, iclass 32, count 0 2006.201.12:07:18.20#ibcon#*before return 0, iclass 32, count 0 2006.201.12:07:18.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:18.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:18.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:07:18.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:07:18.20$vck44/valo=2,534.99 2006.201.12:07:18.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.12:07:18.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.12:07:18.20#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:18.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:18.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:18.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:18.20#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:07:18.20#ibcon#first serial, iclass 34, count 0 2006.201.12:07:18.20#ibcon#enter sib2, iclass 34, count 0 2006.201.12:07:18.20#ibcon#flushed, iclass 34, count 0 2006.201.12:07:18.20#ibcon#about to write, iclass 34, count 0 2006.201.12:07:18.20#ibcon#wrote, iclass 34, count 0 2006.201.12:07:18.20#ibcon#about to read 3, iclass 34, count 0 2006.201.12:07:18.22#ibcon#read 3, iclass 34, count 0 2006.201.12:07:18.22#ibcon#about to read 4, iclass 34, count 0 2006.201.12:07:18.22#ibcon#read 4, iclass 34, count 0 2006.201.12:07:18.22#ibcon#about to read 5, iclass 34, count 0 2006.201.12:07:18.22#ibcon#read 5, iclass 34, count 0 2006.201.12:07:18.22#ibcon#about to read 6, iclass 34, count 0 2006.201.12:07:18.22#ibcon#read 6, iclass 34, count 0 2006.201.12:07:18.22#ibcon#end of sib2, iclass 34, count 0 2006.201.12:07:18.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:07:18.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:07:18.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:07:18.22#ibcon#*before write, iclass 34, count 0 2006.201.12:07:18.22#ibcon#enter sib2, iclass 34, count 0 2006.201.12:07:18.22#ibcon#flushed, iclass 34, count 0 2006.201.12:07:18.22#ibcon#about to write, iclass 34, count 0 2006.201.12:07:18.22#ibcon#wrote, iclass 34, count 0 2006.201.12:07:18.22#ibcon#about to read 3, iclass 34, count 0 2006.201.12:07:18.27#ibcon#read 3, iclass 34, count 0 2006.201.12:07:18.27#ibcon#about to read 4, iclass 34, count 0 2006.201.12:07:18.27#ibcon#read 4, iclass 34, count 0 2006.201.12:07:18.27#ibcon#about to read 5, iclass 34, count 0 2006.201.12:07:18.27#ibcon#read 5, iclass 34, count 0 2006.201.12:07:18.27#ibcon#about to read 6, iclass 34, count 0 2006.201.12:07:18.27#ibcon#read 6, iclass 34, count 0 2006.201.12:07:18.27#ibcon#end of sib2, iclass 34, count 0 2006.201.12:07:18.27#ibcon#*after write, iclass 34, count 0 2006.201.12:07:18.27#ibcon#*before return 0, iclass 34, count 0 2006.201.12:07:18.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:18.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:18.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:07:18.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:07:18.27$vck44/va=2,7 2006.201.12:07:18.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.12:07:18.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.12:07:18.27#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:18.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:18.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:18.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:18.32#ibcon#enter wrdev, iclass 36, count 2 2006.201.12:07:18.32#ibcon#first serial, iclass 36, count 2 2006.201.12:07:18.32#ibcon#enter sib2, iclass 36, count 2 2006.201.12:07:18.32#ibcon#flushed, iclass 36, count 2 2006.201.12:07:18.32#ibcon#about to write, iclass 36, count 2 2006.201.12:07:18.32#ibcon#wrote, iclass 36, count 2 2006.201.12:07:18.32#ibcon#about to read 3, iclass 36, count 2 2006.201.12:07:18.34#ibcon#read 3, iclass 36, count 2 2006.201.12:07:18.34#ibcon#about to read 4, iclass 36, count 2 2006.201.12:07:18.34#ibcon#read 4, iclass 36, count 2 2006.201.12:07:18.34#ibcon#about to read 5, iclass 36, count 2 2006.201.12:07:18.34#ibcon#read 5, iclass 36, count 2 2006.201.12:07:18.34#ibcon#about to read 6, iclass 36, count 2 2006.201.12:07:18.34#ibcon#read 6, iclass 36, count 2 2006.201.12:07:18.34#ibcon#end of sib2, iclass 36, count 2 2006.201.12:07:18.34#ibcon#*mode == 0, iclass 36, count 2 2006.201.12:07:18.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.12:07:18.34#ibcon#[25=AT02-07\r\n] 2006.201.12:07:18.34#ibcon#*before write, iclass 36, count 2 2006.201.12:07:18.34#ibcon#enter sib2, iclass 36, count 2 2006.201.12:07:18.34#ibcon#flushed, iclass 36, count 2 2006.201.12:07:18.34#ibcon#about to write, iclass 36, count 2 2006.201.12:07:18.34#ibcon#wrote, iclass 36, count 2 2006.201.12:07:18.34#ibcon#about to read 3, iclass 36, count 2 2006.201.12:07:18.37#ibcon#read 3, iclass 36, count 2 2006.201.12:07:18.37#ibcon#about to read 4, iclass 36, count 2 2006.201.12:07:18.37#ibcon#read 4, iclass 36, count 2 2006.201.12:07:18.37#ibcon#about to read 5, iclass 36, count 2 2006.201.12:07:18.37#ibcon#read 5, iclass 36, count 2 2006.201.12:07:18.37#ibcon#about to read 6, iclass 36, count 2 2006.201.12:07:18.37#ibcon#read 6, iclass 36, count 2 2006.201.12:07:18.37#ibcon#end of sib2, iclass 36, count 2 2006.201.12:07:18.37#ibcon#*after write, iclass 36, count 2 2006.201.12:07:18.37#ibcon#*before return 0, iclass 36, count 2 2006.201.12:07:18.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:18.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:18.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.12:07:18.37#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:18.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:18.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:18.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:18.49#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:07:18.49#ibcon#first serial, iclass 36, count 0 2006.201.12:07:18.49#ibcon#enter sib2, iclass 36, count 0 2006.201.12:07:18.49#ibcon#flushed, iclass 36, count 0 2006.201.12:07:18.49#ibcon#about to write, iclass 36, count 0 2006.201.12:07:18.49#ibcon#wrote, iclass 36, count 0 2006.201.12:07:18.49#ibcon#about to read 3, iclass 36, count 0 2006.201.12:07:18.51#ibcon#read 3, iclass 36, count 0 2006.201.12:07:18.51#ibcon#about to read 4, iclass 36, count 0 2006.201.12:07:18.51#ibcon#read 4, iclass 36, count 0 2006.201.12:07:18.51#ibcon#about to read 5, iclass 36, count 0 2006.201.12:07:18.51#ibcon#read 5, iclass 36, count 0 2006.201.12:07:18.51#ibcon#about to read 6, iclass 36, count 0 2006.201.12:07:18.51#ibcon#read 6, iclass 36, count 0 2006.201.12:07:18.51#ibcon#end of sib2, iclass 36, count 0 2006.201.12:07:18.51#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:07:18.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:07:18.51#ibcon#[25=USB\r\n] 2006.201.12:07:18.51#ibcon#*before write, iclass 36, count 0 2006.201.12:07:18.51#ibcon#enter sib2, iclass 36, count 0 2006.201.12:07:18.51#ibcon#flushed, iclass 36, count 0 2006.201.12:07:18.51#ibcon#about to write, iclass 36, count 0 2006.201.12:07:18.51#ibcon#wrote, iclass 36, count 0 2006.201.12:07:18.51#ibcon#about to read 3, iclass 36, count 0 2006.201.12:07:18.54#ibcon#read 3, iclass 36, count 0 2006.201.12:07:18.54#ibcon#about to read 4, iclass 36, count 0 2006.201.12:07:18.54#ibcon#read 4, iclass 36, count 0 2006.201.12:07:18.54#ibcon#about to read 5, iclass 36, count 0 2006.201.12:07:18.54#ibcon#read 5, iclass 36, count 0 2006.201.12:07:18.54#ibcon#about to read 6, iclass 36, count 0 2006.201.12:07:18.54#ibcon#read 6, iclass 36, count 0 2006.201.12:07:18.54#ibcon#end of sib2, iclass 36, count 0 2006.201.12:07:18.54#ibcon#*after write, iclass 36, count 0 2006.201.12:07:18.54#ibcon#*before return 0, iclass 36, count 0 2006.201.12:07:18.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:18.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:18.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:07:18.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:07:18.54$vck44/valo=3,564.99 2006.201.12:07:18.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.12:07:18.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.12:07:18.54#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:18.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:18.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:18.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:18.54#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:07:18.54#ibcon#first serial, iclass 38, count 0 2006.201.12:07:18.54#ibcon#enter sib2, iclass 38, count 0 2006.201.12:07:18.54#ibcon#flushed, iclass 38, count 0 2006.201.12:07:18.54#ibcon#about to write, iclass 38, count 0 2006.201.12:07:18.54#ibcon#wrote, iclass 38, count 0 2006.201.12:07:18.54#ibcon#about to read 3, iclass 38, count 0 2006.201.12:07:18.56#ibcon#read 3, iclass 38, count 0 2006.201.12:07:18.56#ibcon#about to read 4, iclass 38, count 0 2006.201.12:07:18.56#ibcon#read 4, iclass 38, count 0 2006.201.12:07:18.56#ibcon#about to read 5, iclass 38, count 0 2006.201.12:07:18.56#ibcon#read 5, iclass 38, count 0 2006.201.12:07:18.56#ibcon#about to read 6, iclass 38, count 0 2006.201.12:07:18.56#ibcon#read 6, iclass 38, count 0 2006.201.12:07:18.56#ibcon#end of sib2, iclass 38, count 0 2006.201.12:07:18.56#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:07:18.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:07:18.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:07:18.56#ibcon#*before write, iclass 38, count 0 2006.201.12:07:18.56#ibcon#enter sib2, iclass 38, count 0 2006.201.12:07:18.56#ibcon#flushed, iclass 38, count 0 2006.201.12:07:18.56#ibcon#about to write, iclass 38, count 0 2006.201.12:07:18.56#ibcon#wrote, iclass 38, count 0 2006.201.12:07:18.56#ibcon#about to read 3, iclass 38, count 0 2006.201.12:07:18.60#ibcon#read 3, iclass 38, count 0 2006.201.12:07:18.60#ibcon#about to read 4, iclass 38, count 0 2006.201.12:07:18.60#ibcon#read 4, iclass 38, count 0 2006.201.12:07:18.60#ibcon#about to read 5, iclass 38, count 0 2006.201.12:07:18.60#ibcon#read 5, iclass 38, count 0 2006.201.12:07:18.60#ibcon#about to read 6, iclass 38, count 0 2006.201.12:07:18.60#ibcon#read 6, iclass 38, count 0 2006.201.12:07:18.60#ibcon#end of sib2, iclass 38, count 0 2006.201.12:07:18.60#ibcon#*after write, iclass 38, count 0 2006.201.12:07:18.60#ibcon#*before return 0, iclass 38, count 0 2006.201.12:07:18.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:18.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:18.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:07:18.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:07:18.60$vck44/va=3,8 2006.201.12:07:18.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.12:07:18.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.12:07:18.60#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:18.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:18.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:18.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:18.66#ibcon#enter wrdev, iclass 40, count 2 2006.201.12:07:18.66#ibcon#first serial, iclass 40, count 2 2006.201.12:07:18.66#ibcon#enter sib2, iclass 40, count 2 2006.201.12:07:18.66#ibcon#flushed, iclass 40, count 2 2006.201.12:07:18.66#ibcon#about to write, iclass 40, count 2 2006.201.12:07:18.66#ibcon#wrote, iclass 40, count 2 2006.201.12:07:18.66#ibcon#about to read 3, iclass 40, count 2 2006.201.12:07:18.68#ibcon#read 3, iclass 40, count 2 2006.201.12:07:18.68#ibcon#about to read 4, iclass 40, count 2 2006.201.12:07:18.68#ibcon#read 4, iclass 40, count 2 2006.201.12:07:18.68#ibcon#about to read 5, iclass 40, count 2 2006.201.12:07:18.68#ibcon#read 5, iclass 40, count 2 2006.201.12:07:18.68#ibcon#about to read 6, iclass 40, count 2 2006.201.12:07:18.68#ibcon#read 6, iclass 40, count 2 2006.201.12:07:18.68#ibcon#end of sib2, iclass 40, count 2 2006.201.12:07:18.68#ibcon#*mode == 0, iclass 40, count 2 2006.201.12:07:18.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.12:07:18.68#ibcon#[25=AT03-08\r\n] 2006.201.12:07:18.68#ibcon#*before write, iclass 40, count 2 2006.201.12:07:18.68#ibcon#enter sib2, iclass 40, count 2 2006.201.12:07:18.68#ibcon#flushed, iclass 40, count 2 2006.201.12:07:18.68#ibcon#about to write, iclass 40, count 2 2006.201.12:07:18.68#ibcon#wrote, iclass 40, count 2 2006.201.12:07:18.68#ibcon#about to read 3, iclass 40, count 2 2006.201.12:07:18.71#ibcon#read 3, iclass 40, count 2 2006.201.12:07:18.71#ibcon#about to read 4, iclass 40, count 2 2006.201.12:07:18.71#ibcon#read 4, iclass 40, count 2 2006.201.12:07:18.71#ibcon#about to read 5, iclass 40, count 2 2006.201.12:07:18.71#ibcon#read 5, iclass 40, count 2 2006.201.12:07:18.71#ibcon#about to read 6, iclass 40, count 2 2006.201.12:07:18.71#ibcon#read 6, iclass 40, count 2 2006.201.12:07:18.71#ibcon#end of sib2, iclass 40, count 2 2006.201.12:07:18.71#ibcon#*after write, iclass 40, count 2 2006.201.12:07:18.71#ibcon#*before return 0, iclass 40, count 2 2006.201.12:07:18.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:18.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:18.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.12:07:18.71#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:18.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:18.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:18.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:18.83#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:07:18.83#ibcon#first serial, iclass 40, count 0 2006.201.12:07:18.83#ibcon#enter sib2, iclass 40, count 0 2006.201.12:07:18.83#ibcon#flushed, iclass 40, count 0 2006.201.12:07:18.83#ibcon#about to write, iclass 40, count 0 2006.201.12:07:18.83#ibcon#wrote, iclass 40, count 0 2006.201.12:07:18.83#ibcon#about to read 3, iclass 40, count 0 2006.201.12:07:18.85#ibcon#read 3, iclass 40, count 0 2006.201.12:07:18.85#ibcon#about to read 4, iclass 40, count 0 2006.201.12:07:18.85#ibcon#read 4, iclass 40, count 0 2006.201.12:07:18.85#ibcon#about to read 5, iclass 40, count 0 2006.201.12:07:18.85#ibcon#read 5, iclass 40, count 0 2006.201.12:07:18.85#ibcon#about to read 6, iclass 40, count 0 2006.201.12:07:18.85#ibcon#read 6, iclass 40, count 0 2006.201.12:07:18.85#ibcon#end of sib2, iclass 40, count 0 2006.201.12:07:18.85#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:07:18.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:07:18.85#ibcon#[25=USB\r\n] 2006.201.12:07:18.85#ibcon#*before write, iclass 40, count 0 2006.201.12:07:18.85#ibcon#enter sib2, iclass 40, count 0 2006.201.12:07:18.85#ibcon#flushed, iclass 40, count 0 2006.201.12:07:18.85#ibcon#about to write, iclass 40, count 0 2006.201.12:07:18.85#ibcon#wrote, iclass 40, count 0 2006.201.12:07:18.85#ibcon#about to read 3, iclass 40, count 0 2006.201.12:07:18.88#ibcon#read 3, iclass 40, count 0 2006.201.12:07:18.88#ibcon#about to read 4, iclass 40, count 0 2006.201.12:07:18.88#ibcon#read 4, iclass 40, count 0 2006.201.12:07:18.88#ibcon#about to read 5, iclass 40, count 0 2006.201.12:07:18.88#ibcon#read 5, iclass 40, count 0 2006.201.12:07:18.88#ibcon#about to read 6, iclass 40, count 0 2006.201.12:07:18.88#ibcon#read 6, iclass 40, count 0 2006.201.12:07:18.88#ibcon#end of sib2, iclass 40, count 0 2006.201.12:07:18.88#ibcon#*after write, iclass 40, count 0 2006.201.12:07:18.88#ibcon#*before return 0, iclass 40, count 0 2006.201.12:07:18.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:18.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:18.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:07:18.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:07:18.88$vck44/valo=4,624.99 2006.201.12:07:18.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.12:07:18.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.12:07:18.88#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:18.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:18.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:18.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:18.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:07:18.88#ibcon#first serial, iclass 4, count 0 2006.201.12:07:18.88#ibcon#enter sib2, iclass 4, count 0 2006.201.12:07:18.88#ibcon#flushed, iclass 4, count 0 2006.201.12:07:18.88#ibcon#about to write, iclass 4, count 0 2006.201.12:07:18.88#ibcon#wrote, iclass 4, count 0 2006.201.12:07:18.88#ibcon#about to read 3, iclass 4, count 0 2006.201.12:07:18.90#ibcon#read 3, iclass 4, count 0 2006.201.12:07:18.90#ibcon#about to read 4, iclass 4, count 0 2006.201.12:07:18.90#ibcon#read 4, iclass 4, count 0 2006.201.12:07:18.90#ibcon#about to read 5, iclass 4, count 0 2006.201.12:07:18.90#ibcon#read 5, iclass 4, count 0 2006.201.12:07:18.90#ibcon#about to read 6, iclass 4, count 0 2006.201.12:07:18.90#ibcon#read 6, iclass 4, count 0 2006.201.12:07:18.90#ibcon#end of sib2, iclass 4, count 0 2006.201.12:07:18.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:07:18.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:07:18.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:07:18.90#ibcon#*before write, iclass 4, count 0 2006.201.12:07:18.90#ibcon#enter sib2, iclass 4, count 0 2006.201.12:07:18.90#ibcon#flushed, iclass 4, count 0 2006.201.12:07:18.90#ibcon#about to write, iclass 4, count 0 2006.201.12:07:18.90#ibcon#wrote, iclass 4, count 0 2006.201.12:07:18.90#ibcon#about to read 3, iclass 4, count 0 2006.201.12:07:18.94#ibcon#read 3, iclass 4, count 0 2006.201.12:07:18.94#ibcon#about to read 4, iclass 4, count 0 2006.201.12:07:18.94#ibcon#read 4, iclass 4, count 0 2006.201.12:07:18.94#ibcon#about to read 5, iclass 4, count 0 2006.201.12:07:18.94#ibcon#read 5, iclass 4, count 0 2006.201.12:07:18.94#ibcon#about to read 6, iclass 4, count 0 2006.201.12:07:18.94#ibcon#read 6, iclass 4, count 0 2006.201.12:07:18.94#ibcon#end of sib2, iclass 4, count 0 2006.201.12:07:18.94#ibcon#*after write, iclass 4, count 0 2006.201.12:07:18.94#ibcon#*before return 0, iclass 4, count 0 2006.201.12:07:18.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:18.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:18.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:07:18.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:07:18.94$vck44/va=4,7 2006.201.12:07:18.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.12:07:18.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.12:07:18.94#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:18.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:19.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:19.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:19.00#ibcon#enter wrdev, iclass 6, count 2 2006.201.12:07:19.00#ibcon#first serial, iclass 6, count 2 2006.201.12:07:19.00#ibcon#enter sib2, iclass 6, count 2 2006.201.12:07:19.00#ibcon#flushed, iclass 6, count 2 2006.201.12:07:19.00#ibcon#about to write, iclass 6, count 2 2006.201.12:07:19.00#ibcon#wrote, iclass 6, count 2 2006.201.12:07:19.00#ibcon#about to read 3, iclass 6, count 2 2006.201.12:07:19.02#ibcon#read 3, iclass 6, count 2 2006.201.12:07:19.02#ibcon#about to read 4, iclass 6, count 2 2006.201.12:07:19.02#ibcon#read 4, iclass 6, count 2 2006.201.12:07:19.02#ibcon#about to read 5, iclass 6, count 2 2006.201.12:07:19.02#ibcon#read 5, iclass 6, count 2 2006.201.12:07:19.02#ibcon#about to read 6, iclass 6, count 2 2006.201.12:07:19.02#ibcon#read 6, iclass 6, count 2 2006.201.12:07:19.02#ibcon#end of sib2, iclass 6, count 2 2006.201.12:07:19.02#ibcon#*mode == 0, iclass 6, count 2 2006.201.12:07:19.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.12:07:19.02#ibcon#[25=AT04-07\r\n] 2006.201.12:07:19.02#ibcon#*before write, iclass 6, count 2 2006.201.12:07:19.02#ibcon#enter sib2, iclass 6, count 2 2006.201.12:07:19.02#ibcon#flushed, iclass 6, count 2 2006.201.12:07:19.02#ibcon#about to write, iclass 6, count 2 2006.201.12:07:19.02#ibcon#wrote, iclass 6, count 2 2006.201.12:07:19.02#ibcon#about to read 3, iclass 6, count 2 2006.201.12:07:19.05#ibcon#read 3, iclass 6, count 2 2006.201.12:07:19.05#ibcon#about to read 4, iclass 6, count 2 2006.201.12:07:19.05#ibcon#read 4, iclass 6, count 2 2006.201.12:07:19.05#ibcon#about to read 5, iclass 6, count 2 2006.201.12:07:19.05#ibcon#read 5, iclass 6, count 2 2006.201.12:07:19.05#ibcon#about to read 6, iclass 6, count 2 2006.201.12:07:19.05#ibcon#read 6, iclass 6, count 2 2006.201.12:07:19.05#ibcon#end of sib2, iclass 6, count 2 2006.201.12:07:19.05#ibcon#*after write, iclass 6, count 2 2006.201.12:07:19.05#ibcon#*before return 0, iclass 6, count 2 2006.201.12:07:19.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:19.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:19.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.12:07:19.05#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:19.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:19.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:19.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:19.17#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:07:19.17#ibcon#first serial, iclass 6, count 0 2006.201.12:07:19.17#ibcon#enter sib2, iclass 6, count 0 2006.201.12:07:19.17#ibcon#flushed, iclass 6, count 0 2006.201.12:07:19.17#ibcon#about to write, iclass 6, count 0 2006.201.12:07:19.17#ibcon#wrote, iclass 6, count 0 2006.201.12:07:19.17#ibcon#about to read 3, iclass 6, count 0 2006.201.12:07:19.19#ibcon#read 3, iclass 6, count 0 2006.201.12:07:19.19#ibcon#about to read 4, iclass 6, count 0 2006.201.12:07:19.19#ibcon#read 4, iclass 6, count 0 2006.201.12:07:19.19#ibcon#about to read 5, iclass 6, count 0 2006.201.12:07:19.19#ibcon#read 5, iclass 6, count 0 2006.201.12:07:19.19#ibcon#about to read 6, iclass 6, count 0 2006.201.12:07:19.19#ibcon#read 6, iclass 6, count 0 2006.201.12:07:19.19#ibcon#end of sib2, iclass 6, count 0 2006.201.12:07:19.19#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:07:19.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:07:19.19#ibcon#[25=USB\r\n] 2006.201.12:07:19.19#ibcon#*before write, iclass 6, count 0 2006.201.12:07:19.19#ibcon#enter sib2, iclass 6, count 0 2006.201.12:07:19.19#ibcon#flushed, iclass 6, count 0 2006.201.12:07:19.19#ibcon#about to write, iclass 6, count 0 2006.201.12:07:19.19#ibcon#wrote, iclass 6, count 0 2006.201.12:07:19.19#ibcon#about to read 3, iclass 6, count 0 2006.201.12:07:19.22#ibcon#read 3, iclass 6, count 0 2006.201.12:07:19.22#ibcon#about to read 4, iclass 6, count 0 2006.201.12:07:19.22#ibcon#read 4, iclass 6, count 0 2006.201.12:07:19.22#ibcon#about to read 5, iclass 6, count 0 2006.201.12:07:19.22#ibcon#read 5, iclass 6, count 0 2006.201.12:07:19.22#ibcon#about to read 6, iclass 6, count 0 2006.201.12:07:19.22#ibcon#read 6, iclass 6, count 0 2006.201.12:07:19.22#ibcon#end of sib2, iclass 6, count 0 2006.201.12:07:19.22#ibcon#*after write, iclass 6, count 0 2006.201.12:07:19.22#ibcon#*before return 0, iclass 6, count 0 2006.201.12:07:19.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:19.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:19.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:07:19.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:07:19.22$vck44/valo=5,734.99 2006.201.12:07:19.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.12:07:19.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.12:07:19.22#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:19.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:19.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:19.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:19.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.12:07:19.22#ibcon#first serial, iclass 10, count 0 2006.201.12:07:19.22#ibcon#enter sib2, iclass 10, count 0 2006.201.12:07:19.22#ibcon#flushed, iclass 10, count 0 2006.201.12:07:19.22#ibcon#about to write, iclass 10, count 0 2006.201.12:07:19.22#ibcon#wrote, iclass 10, count 0 2006.201.12:07:19.22#ibcon#about to read 3, iclass 10, count 0 2006.201.12:07:19.24#ibcon#read 3, iclass 10, count 0 2006.201.12:07:19.24#ibcon#about to read 4, iclass 10, count 0 2006.201.12:07:19.24#ibcon#read 4, iclass 10, count 0 2006.201.12:07:19.24#ibcon#about to read 5, iclass 10, count 0 2006.201.12:07:19.24#ibcon#read 5, iclass 10, count 0 2006.201.12:07:19.24#ibcon#about to read 6, iclass 10, count 0 2006.201.12:07:19.24#ibcon#read 6, iclass 10, count 0 2006.201.12:07:19.24#ibcon#end of sib2, iclass 10, count 0 2006.201.12:07:19.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.12:07:19.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.12:07:19.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:07:19.24#ibcon#*before write, iclass 10, count 0 2006.201.12:07:19.24#ibcon#enter sib2, iclass 10, count 0 2006.201.12:07:19.24#ibcon#flushed, iclass 10, count 0 2006.201.12:07:19.24#ibcon#about to write, iclass 10, count 0 2006.201.12:07:19.24#ibcon#wrote, iclass 10, count 0 2006.201.12:07:19.24#ibcon#about to read 3, iclass 10, count 0 2006.201.12:07:19.28#ibcon#read 3, iclass 10, count 0 2006.201.12:07:19.28#ibcon#about to read 4, iclass 10, count 0 2006.201.12:07:19.28#ibcon#read 4, iclass 10, count 0 2006.201.12:07:19.28#ibcon#about to read 5, iclass 10, count 0 2006.201.12:07:19.28#ibcon#read 5, iclass 10, count 0 2006.201.12:07:19.28#ibcon#about to read 6, iclass 10, count 0 2006.201.12:07:19.28#ibcon#read 6, iclass 10, count 0 2006.201.12:07:19.28#ibcon#end of sib2, iclass 10, count 0 2006.201.12:07:19.28#ibcon#*after write, iclass 10, count 0 2006.201.12:07:19.28#ibcon#*before return 0, iclass 10, count 0 2006.201.12:07:19.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:19.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:19.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.12:07:19.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.12:07:19.28$vck44/va=5,4 2006.201.12:07:19.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.12:07:19.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.12:07:19.28#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:19.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:19.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:19.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:19.34#ibcon#enter wrdev, iclass 12, count 2 2006.201.12:07:19.34#ibcon#first serial, iclass 12, count 2 2006.201.12:07:19.34#ibcon#enter sib2, iclass 12, count 2 2006.201.12:07:19.34#ibcon#flushed, iclass 12, count 2 2006.201.12:07:19.34#ibcon#about to write, iclass 12, count 2 2006.201.12:07:19.34#ibcon#wrote, iclass 12, count 2 2006.201.12:07:19.34#ibcon#about to read 3, iclass 12, count 2 2006.201.12:07:19.36#ibcon#read 3, iclass 12, count 2 2006.201.12:07:19.36#ibcon#about to read 4, iclass 12, count 2 2006.201.12:07:19.36#ibcon#read 4, iclass 12, count 2 2006.201.12:07:19.36#ibcon#about to read 5, iclass 12, count 2 2006.201.12:07:19.36#ibcon#read 5, iclass 12, count 2 2006.201.12:07:19.36#ibcon#about to read 6, iclass 12, count 2 2006.201.12:07:19.36#ibcon#read 6, iclass 12, count 2 2006.201.12:07:19.36#ibcon#end of sib2, iclass 12, count 2 2006.201.12:07:19.36#ibcon#*mode == 0, iclass 12, count 2 2006.201.12:07:19.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.12:07:19.36#ibcon#[25=AT05-04\r\n] 2006.201.12:07:19.36#ibcon#*before write, iclass 12, count 2 2006.201.12:07:19.36#ibcon#enter sib2, iclass 12, count 2 2006.201.12:07:19.36#ibcon#flushed, iclass 12, count 2 2006.201.12:07:19.36#ibcon#about to write, iclass 12, count 2 2006.201.12:07:19.36#ibcon#wrote, iclass 12, count 2 2006.201.12:07:19.36#ibcon#about to read 3, iclass 12, count 2 2006.201.12:07:19.39#ibcon#read 3, iclass 12, count 2 2006.201.12:07:19.39#ibcon#about to read 4, iclass 12, count 2 2006.201.12:07:19.39#ibcon#read 4, iclass 12, count 2 2006.201.12:07:19.39#ibcon#about to read 5, iclass 12, count 2 2006.201.12:07:19.39#ibcon#read 5, iclass 12, count 2 2006.201.12:07:19.39#ibcon#about to read 6, iclass 12, count 2 2006.201.12:07:19.39#ibcon#read 6, iclass 12, count 2 2006.201.12:07:19.39#ibcon#end of sib2, iclass 12, count 2 2006.201.12:07:19.39#ibcon#*after write, iclass 12, count 2 2006.201.12:07:19.39#ibcon#*before return 0, iclass 12, count 2 2006.201.12:07:19.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:19.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:19.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.12:07:19.39#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:19.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:19.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:19.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:19.51#ibcon#enter wrdev, iclass 12, count 0 2006.201.12:07:19.51#ibcon#first serial, iclass 12, count 0 2006.201.12:07:19.51#ibcon#enter sib2, iclass 12, count 0 2006.201.12:07:19.51#ibcon#flushed, iclass 12, count 0 2006.201.12:07:19.51#ibcon#about to write, iclass 12, count 0 2006.201.12:07:19.51#ibcon#wrote, iclass 12, count 0 2006.201.12:07:19.51#ibcon#about to read 3, iclass 12, count 0 2006.201.12:07:19.53#ibcon#read 3, iclass 12, count 0 2006.201.12:07:19.53#ibcon#about to read 4, iclass 12, count 0 2006.201.12:07:19.53#ibcon#read 4, iclass 12, count 0 2006.201.12:07:19.53#ibcon#about to read 5, iclass 12, count 0 2006.201.12:07:19.53#ibcon#read 5, iclass 12, count 0 2006.201.12:07:19.53#ibcon#about to read 6, iclass 12, count 0 2006.201.12:07:19.53#ibcon#read 6, iclass 12, count 0 2006.201.12:07:19.53#ibcon#end of sib2, iclass 12, count 0 2006.201.12:07:19.53#ibcon#*mode == 0, iclass 12, count 0 2006.201.12:07:19.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.12:07:19.53#ibcon#[25=USB\r\n] 2006.201.12:07:19.53#ibcon#*before write, iclass 12, count 0 2006.201.12:07:19.53#ibcon#enter sib2, iclass 12, count 0 2006.201.12:07:19.53#ibcon#flushed, iclass 12, count 0 2006.201.12:07:19.53#ibcon#about to write, iclass 12, count 0 2006.201.12:07:19.53#ibcon#wrote, iclass 12, count 0 2006.201.12:07:19.53#ibcon#about to read 3, iclass 12, count 0 2006.201.12:07:19.56#ibcon#read 3, iclass 12, count 0 2006.201.12:07:19.56#ibcon#about to read 4, iclass 12, count 0 2006.201.12:07:19.56#ibcon#read 4, iclass 12, count 0 2006.201.12:07:19.56#ibcon#about to read 5, iclass 12, count 0 2006.201.12:07:19.56#ibcon#read 5, iclass 12, count 0 2006.201.12:07:19.56#ibcon#about to read 6, iclass 12, count 0 2006.201.12:07:19.56#ibcon#read 6, iclass 12, count 0 2006.201.12:07:19.56#ibcon#end of sib2, iclass 12, count 0 2006.201.12:07:19.56#ibcon#*after write, iclass 12, count 0 2006.201.12:07:19.56#ibcon#*before return 0, iclass 12, count 0 2006.201.12:07:19.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:19.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:19.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.12:07:19.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.12:07:19.56$vck44/valo=6,814.99 2006.201.12:07:19.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.12:07:19.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.12:07:19.56#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:19.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:19.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:19.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:19.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.12:07:19.56#ibcon#first serial, iclass 14, count 0 2006.201.12:07:19.56#ibcon#enter sib2, iclass 14, count 0 2006.201.12:07:19.56#ibcon#flushed, iclass 14, count 0 2006.201.12:07:19.56#ibcon#about to write, iclass 14, count 0 2006.201.12:07:19.56#ibcon#wrote, iclass 14, count 0 2006.201.12:07:19.56#ibcon#about to read 3, iclass 14, count 0 2006.201.12:07:19.58#ibcon#read 3, iclass 14, count 0 2006.201.12:07:19.58#ibcon#about to read 4, iclass 14, count 0 2006.201.12:07:19.58#ibcon#read 4, iclass 14, count 0 2006.201.12:07:19.58#ibcon#about to read 5, iclass 14, count 0 2006.201.12:07:19.58#ibcon#read 5, iclass 14, count 0 2006.201.12:07:19.58#ibcon#about to read 6, iclass 14, count 0 2006.201.12:07:19.58#ibcon#read 6, iclass 14, count 0 2006.201.12:07:19.58#ibcon#end of sib2, iclass 14, count 0 2006.201.12:07:19.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.12:07:19.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.12:07:19.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:07:19.58#ibcon#*before write, iclass 14, count 0 2006.201.12:07:19.58#ibcon#enter sib2, iclass 14, count 0 2006.201.12:07:19.58#ibcon#flushed, iclass 14, count 0 2006.201.12:07:19.58#ibcon#about to write, iclass 14, count 0 2006.201.12:07:19.58#ibcon#wrote, iclass 14, count 0 2006.201.12:07:19.58#ibcon#about to read 3, iclass 14, count 0 2006.201.12:07:19.62#ibcon#read 3, iclass 14, count 0 2006.201.12:07:19.62#ibcon#about to read 4, iclass 14, count 0 2006.201.12:07:19.62#ibcon#read 4, iclass 14, count 0 2006.201.12:07:19.62#ibcon#about to read 5, iclass 14, count 0 2006.201.12:07:19.62#ibcon#read 5, iclass 14, count 0 2006.201.12:07:19.62#ibcon#about to read 6, iclass 14, count 0 2006.201.12:07:19.62#ibcon#read 6, iclass 14, count 0 2006.201.12:07:19.62#ibcon#end of sib2, iclass 14, count 0 2006.201.12:07:19.62#ibcon#*after write, iclass 14, count 0 2006.201.12:07:19.62#ibcon#*before return 0, iclass 14, count 0 2006.201.12:07:19.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:19.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:19.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.12:07:19.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.12:07:19.62$vck44/va=6,5 2006.201.12:07:19.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.12:07:19.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.12:07:19.62#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:19.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:19.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:19.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:19.68#ibcon#enter wrdev, iclass 16, count 2 2006.201.12:07:19.68#ibcon#first serial, iclass 16, count 2 2006.201.12:07:19.68#ibcon#enter sib2, iclass 16, count 2 2006.201.12:07:19.68#ibcon#flushed, iclass 16, count 2 2006.201.12:07:19.68#ibcon#about to write, iclass 16, count 2 2006.201.12:07:19.68#ibcon#wrote, iclass 16, count 2 2006.201.12:07:19.68#ibcon#about to read 3, iclass 16, count 2 2006.201.12:07:19.70#ibcon#read 3, iclass 16, count 2 2006.201.12:07:19.70#ibcon#about to read 4, iclass 16, count 2 2006.201.12:07:19.70#ibcon#read 4, iclass 16, count 2 2006.201.12:07:19.70#ibcon#about to read 5, iclass 16, count 2 2006.201.12:07:19.70#ibcon#read 5, iclass 16, count 2 2006.201.12:07:19.70#ibcon#about to read 6, iclass 16, count 2 2006.201.12:07:19.70#ibcon#read 6, iclass 16, count 2 2006.201.12:07:19.70#ibcon#end of sib2, iclass 16, count 2 2006.201.12:07:19.70#ibcon#*mode == 0, iclass 16, count 2 2006.201.12:07:19.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.12:07:19.70#ibcon#[25=AT06-05\r\n] 2006.201.12:07:19.70#ibcon#*before write, iclass 16, count 2 2006.201.12:07:19.70#ibcon#enter sib2, iclass 16, count 2 2006.201.12:07:19.70#ibcon#flushed, iclass 16, count 2 2006.201.12:07:19.70#ibcon#about to write, iclass 16, count 2 2006.201.12:07:19.70#ibcon#wrote, iclass 16, count 2 2006.201.12:07:19.70#ibcon#about to read 3, iclass 16, count 2 2006.201.12:07:19.73#ibcon#read 3, iclass 16, count 2 2006.201.12:07:19.73#ibcon#about to read 4, iclass 16, count 2 2006.201.12:07:19.73#ibcon#read 4, iclass 16, count 2 2006.201.12:07:19.73#ibcon#about to read 5, iclass 16, count 2 2006.201.12:07:19.73#ibcon#read 5, iclass 16, count 2 2006.201.12:07:19.73#ibcon#about to read 6, iclass 16, count 2 2006.201.12:07:19.73#ibcon#read 6, iclass 16, count 2 2006.201.12:07:19.73#ibcon#end of sib2, iclass 16, count 2 2006.201.12:07:19.73#ibcon#*after write, iclass 16, count 2 2006.201.12:07:19.73#ibcon#*before return 0, iclass 16, count 2 2006.201.12:07:19.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:19.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:19.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.12:07:19.73#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:19.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:19.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:19.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:19.85#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:07:19.85#ibcon#first serial, iclass 16, count 0 2006.201.12:07:19.85#ibcon#enter sib2, iclass 16, count 0 2006.201.12:07:19.85#ibcon#flushed, iclass 16, count 0 2006.201.12:07:19.85#ibcon#about to write, iclass 16, count 0 2006.201.12:07:19.85#ibcon#wrote, iclass 16, count 0 2006.201.12:07:19.85#ibcon#about to read 3, iclass 16, count 0 2006.201.12:07:19.87#ibcon#read 3, iclass 16, count 0 2006.201.12:07:19.87#ibcon#about to read 4, iclass 16, count 0 2006.201.12:07:19.87#ibcon#read 4, iclass 16, count 0 2006.201.12:07:19.87#ibcon#about to read 5, iclass 16, count 0 2006.201.12:07:19.87#ibcon#read 5, iclass 16, count 0 2006.201.12:07:19.87#ibcon#about to read 6, iclass 16, count 0 2006.201.12:07:19.87#ibcon#read 6, iclass 16, count 0 2006.201.12:07:19.87#ibcon#end of sib2, iclass 16, count 0 2006.201.12:07:19.87#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:07:19.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:07:19.87#ibcon#[25=USB\r\n] 2006.201.12:07:19.87#ibcon#*before write, iclass 16, count 0 2006.201.12:07:19.87#ibcon#enter sib2, iclass 16, count 0 2006.201.12:07:19.87#ibcon#flushed, iclass 16, count 0 2006.201.12:07:19.87#ibcon#about to write, iclass 16, count 0 2006.201.12:07:19.87#ibcon#wrote, iclass 16, count 0 2006.201.12:07:19.87#ibcon#about to read 3, iclass 16, count 0 2006.201.12:07:19.90#ibcon#read 3, iclass 16, count 0 2006.201.12:07:19.90#ibcon#about to read 4, iclass 16, count 0 2006.201.12:07:19.90#ibcon#read 4, iclass 16, count 0 2006.201.12:07:19.90#ibcon#about to read 5, iclass 16, count 0 2006.201.12:07:19.90#ibcon#read 5, iclass 16, count 0 2006.201.12:07:19.90#ibcon#about to read 6, iclass 16, count 0 2006.201.12:07:19.90#ibcon#read 6, iclass 16, count 0 2006.201.12:07:19.90#ibcon#end of sib2, iclass 16, count 0 2006.201.12:07:19.90#ibcon#*after write, iclass 16, count 0 2006.201.12:07:19.90#ibcon#*before return 0, iclass 16, count 0 2006.201.12:07:19.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:19.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:19.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:07:19.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:07:19.90$vck44/valo=7,864.99 2006.201.12:07:19.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.12:07:19.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.12:07:19.90#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:19.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:19.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:19.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:19.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:07:19.90#ibcon#first serial, iclass 18, count 0 2006.201.12:07:19.90#ibcon#enter sib2, iclass 18, count 0 2006.201.12:07:19.90#ibcon#flushed, iclass 18, count 0 2006.201.12:07:19.90#ibcon#about to write, iclass 18, count 0 2006.201.12:07:19.90#ibcon#wrote, iclass 18, count 0 2006.201.12:07:19.90#ibcon#about to read 3, iclass 18, count 0 2006.201.12:07:19.92#ibcon#read 3, iclass 18, count 0 2006.201.12:07:19.92#ibcon#about to read 4, iclass 18, count 0 2006.201.12:07:19.92#ibcon#read 4, iclass 18, count 0 2006.201.12:07:19.92#ibcon#about to read 5, iclass 18, count 0 2006.201.12:07:19.92#ibcon#read 5, iclass 18, count 0 2006.201.12:07:19.92#ibcon#about to read 6, iclass 18, count 0 2006.201.12:07:19.92#ibcon#read 6, iclass 18, count 0 2006.201.12:07:19.92#ibcon#end of sib2, iclass 18, count 0 2006.201.12:07:19.92#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:07:19.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:07:19.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:07:19.92#ibcon#*before write, iclass 18, count 0 2006.201.12:07:19.92#ibcon#enter sib2, iclass 18, count 0 2006.201.12:07:19.92#ibcon#flushed, iclass 18, count 0 2006.201.12:07:19.92#ibcon#about to write, iclass 18, count 0 2006.201.12:07:19.92#ibcon#wrote, iclass 18, count 0 2006.201.12:07:19.92#ibcon#about to read 3, iclass 18, count 0 2006.201.12:07:19.96#ibcon#read 3, iclass 18, count 0 2006.201.12:07:19.96#ibcon#about to read 4, iclass 18, count 0 2006.201.12:07:19.96#ibcon#read 4, iclass 18, count 0 2006.201.12:07:19.96#ibcon#about to read 5, iclass 18, count 0 2006.201.12:07:19.96#ibcon#read 5, iclass 18, count 0 2006.201.12:07:19.96#ibcon#about to read 6, iclass 18, count 0 2006.201.12:07:19.96#ibcon#read 6, iclass 18, count 0 2006.201.12:07:19.96#ibcon#end of sib2, iclass 18, count 0 2006.201.12:07:19.96#ibcon#*after write, iclass 18, count 0 2006.201.12:07:19.96#ibcon#*before return 0, iclass 18, count 0 2006.201.12:07:19.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:19.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:19.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:07:19.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:07:19.96$vck44/va=7,5 2006.201.12:07:19.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.12:07:19.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.12:07:19.96#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:19.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:20.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:20.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:20.02#ibcon#enter wrdev, iclass 20, count 2 2006.201.12:07:20.02#ibcon#first serial, iclass 20, count 2 2006.201.12:07:20.02#ibcon#enter sib2, iclass 20, count 2 2006.201.12:07:20.02#ibcon#flushed, iclass 20, count 2 2006.201.12:07:20.02#ibcon#about to write, iclass 20, count 2 2006.201.12:07:20.02#ibcon#wrote, iclass 20, count 2 2006.201.12:07:20.02#ibcon#about to read 3, iclass 20, count 2 2006.201.12:07:20.04#ibcon#read 3, iclass 20, count 2 2006.201.12:07:20.04#ibcon#about to read 4, iclass 20, count 2 2006.201.12:07:20.04#ibcon#read 4, iclass 20, count 2 2006.201.12:07:20.04#ibcon#about to read 5, iclass 20, count 2 2006.201.12:07:20.04#ibcon#read 5, iclass 20, count 2 2006.201.12:07:20.04#ibcon#about to read 6, iclass 20, count 2 2006.201.12:07:20.04#ibcon#read 6, iclass 20, count 2 2006.201.12:07:20.04#ibcon#end of sib2, iclass 20, count 2 2006.201.12:07:20.04#ibcon#*mode == 0, iclass 20, count 2 2006.201.12:07:20.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.12:07:20.04#ibcon#[25=AT07-05\r\n] 2006.201.12:07:20.04#ibcon#*before write, iclass 20, count 2 2006.201.12:07:20.04#ibcon#enter sib2, iclass 20, count 2 2006.201.12:07:20.04#ibcon#flushed, iclass 20, count 2 2006.201.12:07:20.04#ibcon#about to write, iclass 20, count 2 2006.201.12:07:20.04#ibcon#wrote, iclass 20, count 2 2006.201.12:07:20.04#ibcon#about to read 3, iclass 20, count 2 2006.201.12:07:20.07#ibcon#read 3, iclass 20, count 2 2006.201.12:07:20.07#ibcon#about to read 4, iclass 20, count 2 2006.201.12:07:20.07#ibcon#read 4, iclass 20, count 2 2006.201.12:07:20.07#ibcon#about to read 5, iclass 20, count 2 2006.201.12:07:20.07#ibcon#read 5, iclass 20, count 2 2006.201.12:07:20.07#ibcon#about to read 6, iclass 20, count 2 2006.201.12:07:20.07#ibcon#read 6, iclass 20, count 2 2006.201.12:07:20.07#ibcon#end of sib2, iclass 20, count 2 2006.201.12:07:20.07#ibcon#*after write, iclass 20, count 2 2006.201.12:07:20.07#ibcon#*before return 0, iclass 20, count 2 2006.201.12:07:20.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:20.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:20.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.12:07:20.07#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:20.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:20.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:20.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:20.19#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:07:20.19#ibcon#first serial, iclass 20, count 0 2006.201.12:07:20.19#ibcon#enter sib2, iclass 20, count 0 2006.201.12:07:20.19#ibcon#flushed, iclass 20, count 0 2006.201.12:07:20.19#ibcon#about to write, iclass 20, count 0 2006.201.12:07:20.19#ibcon#wrote, iclass 20, count 0 2006.201.12:07:20.19#ibcon#about to read 3, iclass 20, count 0 2006.201.12:07:20.21#ibcon#read 3, iclass 20, count 0 2006.201.12:07:20.21#ibcon#about to read 4, iclass 20, count 0 2006.201.12:07:20.21#ibcon#read 4, iclass 20, count 0 2006.201.12:07:20.21#ibcon#about to read 5, iclass 20, count 0 2006.201.12:07:20.21#ibcon#read 5, iclass 20, count 0 2006.201.12:07:20.21#ibcon#about to read 6, iclass 20, count 0 2006.201.12:07:20.21#ibcon#read 6, iclass 20, count 0 2006.201.12:07:20.21#ibcon#end of sib2, iclass 20, count 0 2006.201.12:07:20.21#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:07:20.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:07:20.21#ibcon#[25=USB\r\n] 2006.201.12:07:20.21#ibcon#*before write, iclass 20, count 0 2006.201.12:07:20.21#ibcon#enter sib2, iclass 20, count 0 2006.201.12:07:20.21#ibcon#flushed, iclass 20, count 0 2006.201.12:07:20.21#ibcon#about to write, iclass 20, count 0 2006.201.12:07:20.21#ibcon#wrote, iclass 20, count 0 2006.201.12:07:20.21#ibcon#about to read 3, iclass 20, count 0 2006.201.12:07:20.24#ibcon#read 3, iclass 20, count 0 2006.201.12:07:20.24#ibcon#about to read 4, iclass 20, count 0 2006.201.12:07:20.24#ibcon#read 4, iclass 20, count 0 2006.201.12:07:20.24#ibcon#about to read 5, iclass 20, count 0 2006.201.12:07:20.24#ibcon#read 5, iclass 20, count 0 2006.201.12:07:20.24#ibcon#about to read 6, iclass 20, count 0 2006.201.12:07:20.24#ibcon#read 6, iclass 20, count 0 2006.201.12:07:20.24#ibcon#end of sib2, iclass 20, count 0 2006.201.12:07:20.24#ibcon#*after write, iclass 20, count 0 2006.201.12:07:20.24#ibcon#*before return 0, iclass 20, count 0 2006.201.12:07:20.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:20.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:20.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:07:20.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:07:20.24$vck44/valo=8,884.99 2006.201.12:07:20.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.12:07:20.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.12:07:20.24#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:20.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:07:20.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:07:20.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:07:20.24#ibcon#enter wrdev, iclass 22, count 0 2006.201.12:07:20.24#ibcon#first serial, iclass 22, count 0 2006.201.12:07:20.24#ibcon#enter sib2, iclass 22, count 0 2006.201.12:07:20.24#ibcon#flushed, iclass 22, count 0 2006.201.12:07:20.24#ibcon#about to write, iclass 22, count 0 2006.201.12:07:20.24#ibcon#wrote, iclass 22, count 0 2006.201.12:07:20.24#ibcon#about to read 3, iclass 22, count 0 2006.201.12:07:20.26#ibcon#read 3, iclass 22, count 0 2006.201.12:07:20.26#ibcon#about to read 4, iclass 22, count 0 2006.201.12:07:20.26#ibcon#read 4, iclass 22, count 0 2006.201.12:07:20.26#ibcon#about to read 5, iclass 22, count 0 2006.201.12:07:20.26#ibcon#read 5, iclass 22, count 0 2006.201.12:07:20.26#ibcon#about to read 6, iclass 22, count 0 2006.201.12:07:20.26#ibcon#read 6, iclass 22, count 0 2006.201.12:07:20.26#ibcon#end of sib2, iclass 22, count 0 2006.201.12:07:20.26#ibcon#*mode == 0, iclass 22, count 0 2006.201.12:07:20.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.12:07:20.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:07:20.26#ibcon#*before write, iclass 22, count 0 2006.201.12:07:20.26#ibcon#enter sib2, iclass 22, count 0 2006.201.12:07:20.26#ibcon#flushed, iclass 22, count 0 2006.201.12:07:20.26#ibcon#about to write, iclass 22, count 0 2006.201.12:07:20.26#ibcon#wrote, iclass 22, count 0 2006.201.12:07:20.26#ibcon#about to read 3, iclass 22, count 0 2006.201.12:07:20.30#ibcon#read 3, iclass 22, count 0 2006.201.12:07:20.30#ibcon#about to read 4, iclass 22, count 0 2006.201.12:07:20.30#ibcon#read 4, iclass 22, count 0 2006.201.12:07:20.30#ibcon#about to read 5, iclass 22, count 0 2006.201.12:07:20.30#ibcon#read 5, iclass 22, count 0 2006.201.12:07:20.30#ibcon#about to read 6, iclass 22, count 0 2006.201.12:07:20.30#ibcon#read 6, iclass 22, count 0 2006.201.12:07:20.30#ibcon#end of sib2, iclass 22, count 0 2006.201.12:07:20.30#ibcon#*after write, iclass 22, count 0 2006.201.12:07:20.30#ibcon#*before return 0, iclass 22, count 0 2006.201.12:07:20.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:07:20.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:07:20.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.12:07:20.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.12:07:20.30$vck44/va=8,4 2006.201.12:07:20.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.12:07:20.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.12:07:20.30#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:20.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:07:20.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:07:20.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:07:20.36#ibcon#enter wrdev, iclass 24, count 2 2006.201.12:07:20.36#ibcon#first serial, iclass 24, count 2 2006.201.12:07:20.36#ibcon#enter sib2, iclass 24, count 2 2006.201.12:07:20.36#ibcon#flushed, iclass 24, count 2 2006.201.12:07:20.36#ibcon#about to write, iclass 24, count 2 2006.201.12:07:20.36#ibcon#wrote, iclass 24, count 2 2006.201.12:07:20.36#ibcon#about to read 3, iclass 24, count 2 2006.201.12:07:20.38#ibcon#read 3, iclass 24, count 2 2006.201.12:07:20.38#ibcon#about to read 4, iclass 24, count 2 2006.201.12:07:20.38#ibcon#read 4, iclass 24, count 2 2006.201.12:07:20.38#ibcon#about to read 5, iclass 24, count 2 2006.201.12:07:20.38#ibcon#read 5, iclass 24, count 2 2006.201.12:07:20.38#ibcon#about to read 6, iclass 24, count 2 2006.201.12:07:20.38#ibcon#read 6, iclass 24, count 2 2006.201.12:07:20.38#ibcon#end of sib2, iclass 24, count 2 2006.201.12:07:20.38#ibcon#*mode == 0, iclass 24, count 2 2006.201.12:07:20.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.12:07:20.38#ibcon#[25=AT08-04\r\n] 2006.201.12:07:20.38#ibcon#*before write, iclass 24, count 2 2006.201.12:07:20.38#ibcon#enter sib2, iclass 24, count 2 2006.201.12:07:20.38#ibcon#flushed, iclass 24, count 2 2006.201.12:07:20.38#ibcon#about to write, iclass 24, count 2 2006.201.12:07:20.38#ibcon#wrote, iclass 24, count 2 2006.201.12:07:20.38#ibcon#about to read 3, iclass 24, count 2 2006.201.12:07:20.41#ibcon#read 3, iclass 24, count 2 2006.201.12:07:20.41#ibcon#about to read 4, iclass 24, count 2 2006.201.12:07:20.41#ibcon#read 4, iclass 24, count 2 2006.201.12:07:20.41#ibcon#about to read 5, iclass 24, count 2 2006.201.12:07:20.41#ibcon#read 5, iclass 24, count 2 2006.201.12:07:20.41#ibcon#about to read 6, iclass 24, count 2 2006.201.12:07:20.41#ibcon#read 6, iclass 24, count 2 2006.201.12:07:20.41#ibcon#end of sib2, iclass 24, count 2 2006.201.12:07:20.41#ibcon#*after write, iclass 24, count 2 2006.201.12:07:20.41#ibcon#*before return 0, iclass 24, count 2 2006.201.12:07:20.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:07:20.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:07:20.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.12:07:20.41#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:20.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:07:20.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:07:20.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:07:20.53#ibcon#enter wrdev, iclass 24, count 0 2006.201.12:07:20.53#ibcon#first serial, iclass 24, count 0 2006.201.12:07:20.53#ibcon#enter sib2, iclass 24, count 0 2006.201.12:07:20.53#ibcon#flushed, iclass 24, count 0 2006.201.12:07:20.53#ibcon#about to write, iclass 24, count 0 2006.201.12:07:20.53#ibcon#wrote, iclass 24, count 0 2006.201.12:07:20.53#ibcon#about to read 3, iclass 24, count 0 2006.201.12:07:20.55#ibcon#read 3, iclass 24, count 0 2006.201.12:07:20.55#ibcon#about to read 4, iclass 24, count 0 2006.201.12:07:20.55#ibcon#read 4, iclass 24, count 0 2006.201.12:07:20.55#ibcon#about to read 5, iclass 24, count 0 2006.201.12:07:20.55#ibcon#read 5, iclass 24, count 0 2006.201.12:07:20.55#ibcon#about to read 6, iclass 24, count 0 2006.201.12:07:20.55#ibcon#read 6, iclass 24, count 0 2006.201.12:07:20.55#ibcon#end of sib2, iclass 24, count 0 2006.201.12:07:20.55#ibcon#*mode == 0, iclass 24, count 0 2006.201.12:07:20.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.12:07:20.55#ibcon#[25=USB\r\n] 2006.201.12:07:20.55#ibcon#*before write, iclass 24, count 0 2006.201.12:07:20.55#ibcon#enter sib2, iclass 24, count 0 2006.201.12:07:20.55#ibcon#flushed, iclass 24, count 0 2006.201.12:07:20.55#ibcon#about to write, iclass 24, count 0 2006.201.12:07:20.55#ibcon#wrote, iclass 24, count 0 2006.201.12:07:20.55#ibcon#about to read 3, iclass 24, count 0 2006.201.12:07:20.58#ibcon#read 3, iclass 24, count 0 2006.201.12:07:20.58#ibcon#about to read 4, iclass 24, count 0 2006.201.12:07:20.58#ibcon#read 4, iclass 24, count 0 2006.201.12:07:20.58#ibcon#about to read 5, iclass 24, count 0 2006.201.12:07:20.58#ibcon#read 5, iclass 24, count 0 2006.201.12:07:20.58#ibcon#about to read 6, iclass 24, count 0 2006.201.12:07:20.58#ibcon#read 6, iclass 24, count 0 2006.201.12:07:20.58#ibcon#end of sib2, iclass 24, count 0 2006.201.12:07:20.58#ibcon#*after write, iclass 24, count 0 2006.201.12:07:20.58#ibcon#*before return 0, iclass 24, count 0 2006.201.12:07:20.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:07:20.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:07:20.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.12:07:20.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.12:07:20.58$vck44/vblo=1,629.99 2006.201.12:07:20.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.12:07:20.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.12:07:20.58#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:20.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:07:20.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:07:20.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:07:20.58#ibcon#enter wrdev, iclass 26, count 0 2006.201.12:07:20.58#ibcon#first serial, iclass 26, count 0 2006.201.12:07:20.58#ibcon#enter sib2, iclass 26, count 0 2006.201.12:07:20.58#ibcon#flushed, iclass 26, count 0 2006.201.12:07:20.58#ibcon#about to write, iclass 26, count 0 2006.201.12:07:20.58#ibcon#wrote, iclass 26, count 0 2006.201.12:07:20.58#ibcon#about to read 3, iclass 26, count 0 2006.201.12:07:20.60#ibcon#read 3, iclass 26, count 0 2006.201.12:07:20.60#ibcon#about to read 4, iclass 26, count 0 2006.201.12:07:20.60#ibcon#read 4, iclass 26, count 0 2006.201.12:07:20.60#ibcon#about to read 5, iclass 26, count 0 2006.201.12:07:20.60#ibcon#read 5, iclass 26, count 0 2006.201.12:07:20.60#ibcon#about to read 6, iclass 26, count 0 2006.201.12:07:20.60#ibcon#read 6, iclass 26, count 0 2006.201.12:07:20.60#ibcon#end of sib2, iclass 26, count 0 2006.201.12:07:20.60#ibcon#*mode == 0, iclass 26, count 0 2006.201.12:07:20.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.12:07:20.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:07:20.60#ibcon#*before write, iclass 26, count 0 2006.201.12:07:20.60#ibcon#enter sib2, iclass 26, count 0 2006.201.12:07:20.60#ibcon#flushed, iclass 26, count 0 2006.201.12:07:20.60#ibcon#about to write, iclass 26, count 0 2006.201.12:07:20.60#ibcon#wrote, iclass 26, count 0 2006.201.12:07:20.60#ibcon#about to read 3, iclass 26, count 0 2006.201.12:07:20.64#ibcon#read 3, iclass 26, count 0 2006.201.12:07:20.64#ibcon#about to read 4, iclass 26, count 0 2006.201.12:07:20.64#ibcon#read 4, iclass 26, count 0 2006.201.12:07:20.64#ibcon#about to read 5, iclass 26, count 0 2006.201.12:07:20.64#ibcon#read 5, iclass 26, count 0 2006.201.12:07:20.64#ibcon#about to read 6, iclass 26, count 0 2006.201.12:07:20.64#ibcon#read 6, iclass 26, count 0 2006.201.12:07:20.64#ibcon#end of sib2, iclass 26, count 0 2006.201.12:07:20.64#ibcon#*after write, iclass 26, count 0 2006.201.12:07:20.64#ibcon#*before return 0, iclass 26, count 0 2006.201.12:07:20.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:07:20.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:07:20.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.12:07:20.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.12:07:20.64$vck44/vb=1,4 2006.201.12:07:20.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.12:07:20.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.12:07:20.64#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:20.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:07:20.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:07:20.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:07:20.64#ibcon#enter wrdev, iclass 28, count 2 2006.201.12:07:20.64#ibcon#first serial, iclass 28, count 2 2006.201.12:07:20.64#ibcon#enter sib2, iclass 28, count 2 2006.201.12:07:20.64#ibcon#flushed, iclass 28, count 2 2006.201.12:07:20.64#ibcon#about to write, iclass 28, count 2 2006.201.12:07:20.64#ibcon#wrote, iclass 28, count 2 2006.201.12:07:20.64#ibcon#about to read 3, iclass 28, count 2 2006.201.12:07:20.66#ibcon#read 3, iclass 28, count 2 2006.201.12:07:20.66#ibcon#about to read 4, iclass 28, count 2 2006.201.12:07:20.66#ibcon#read 4, iclass 28, count 2 2006.201.12:07:20.66#ibcon#about to read 5, iclass 28, count 2 2006.201.12:07:20.66#ibcon#read 5, iclass 28, count 2 2006.201.12:07:20.66#ibcon#about to read 6, iclass 28, count 2 2006.201.12:07:20.66#ibcon#read 6, iclass 28, count 2 2006.201.12:07:20.66#ibcon#end of sib2, iclass 28, count 2 2006.201.12:07:20.66#ibcon#*mode == 0, iclass 28, count 2 2006.201.12:07:20.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.12:07:20.66#ibcon#[27=AT01-04\r\n] 2006.201.12:07:20.66#ibcon#*before write, iclass 28, count 2 2006.201.12:07:20.66#ibcon#enter sib2, iclass 28, count 2 2006.201.12:07:20.66#ibcon#flushed, iclass 28, count 2 2006.201.12:07:20.66#ibcon#about to write, iclass 28, count 2 2006.201.12:07:20.66#ibcon#wrote, iclass 28, count 2 2006.201.12:07:20.66#ibcon#about to read 3, iclass 28, count 2 2006.201.12:07:20.69#ibcon#read 3, iclass 28, count 2 2006.201.12:07:20.69#ibcon#about to read 4, iclass 28, count 2 2006.201.12:07:20.69#ibcon#read 4, iclass 28, count 2 2006.201.12:07:20.69#ibcon#about to read 5, iclass 28, count 2 2006.201.12:07:20.69#ibcon#read 5, iclass 28, count 2 2006.201.12:07:20.69#ibcon#about to read 6, iclass 28, count 2 2006.201.12:07:20.69#ibcon#read 6, iclass 28, count 2 2006.201.12:07:20.69#ibcon#end of sib2, iclass 28, count 2 2006.201.12:07:20.69#ibcon#*after write, iclass 28, count 2 2006.201.12:07:20.69#ibcon#*before return 0, iclass 28, count 2 2006.201.12:07:20.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:07:20.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:07:20.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.12:07:20.69#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:20.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:07:20.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:07:20.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:07:20.81#ibcon#enter wrdev, iclass 28, count 0 2006.201.12:07:20.81#ibcon#first serial, iclass 28, count 0 2006.201.12:07:20.81#ibcon#enter sib2, iclass 28, count 0 2006.201.12:07:20.81#ibcon#flushed, iclass 28, count 0 2006.201.12:07:20.81#ibcon#about to write, iclass 28, count 0 2006.201.12:07:20.81#ibcon#wrote, iclass 28, count 0 2006.201.12:07:20.81#ibcon#about to read 3, iclass 28, count 0 2006.201.12:07:20.83#ibcon#read 3, iclass 28, count 0 2006.201.12:07:20.83#ibcon#about to read 4, iclass 28, count 0 2006.201.12:07:20.83#ibcon#read 4, iclass 28, count 0 2006.201.12:07:20.83#ibcon#about to read 5, iclass 28, count 0 2006.201.12:07:20.83#ibcon#read 5, iclass 28, count 0 2006.201.12:07:20.83#ibcon#about to read 6, iclass 28, count 0 2006.201.12:07:20.83#ibcon#read 6, iclass 28, count 0 2006.201.12:07:20.83#ibcon#end of sib2, iclass 28, count 0 2006.201.12:07:20.83#ibcon#*mode == 0, iclass 28, count 0 2006.201.12:07:20.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.12:07:20.83#ibcon#[27=USB\r\n] 2006.201.12:07:20.83#ibcon#*before write, iclass 28, count 0 2006.201.12:07:20.83#ibcon#enter sib2, iclass 28, count 0 2006.201.12:07:20.83#ibcon#flushed, iclass 28, count 0 2006.201.12:07:20.83#ibcon#about to write, iclass 28, count 0 2006.201.12:07:20.83#ibcon#wrote, iclass 28, count 0 2006.201.12:07:20.83#ibcon#about to read 3, iclass 28, count 0 2006.201.12:07:20.86#ibcon#read 3, iclass 28, count 0 2006.201.12:07:20.86#ibcon#about to read 4, iclass 28, count 0 2006.201.12:07:20.86#ibcon#read 4, iclass 28, count 0 2006.201.12:07:20.86#ibcon#about to read 5, iclass 28, count 0 2006.201.12:07:20.86#ibcon#read 5, iclass 28, count 0 2006.201.12:07:20.86#ibcon#about to read 6, iclass 28, count 0 2006.201.12:07:20.86#ibcon#read 6, iclass 28, count 0 2006.201.12:07:20.86#ibcon#end of sib2, iclass 28, count 0 2006.201.12:07:20.86#ibcon#*after write, iclass 28, count 0 2006.201.12:07:20.86#ibcon#*before return 0, iclass 28, count 0 2006.201.12:07:20.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:07:20.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:07:20.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.12:07:20.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.12:07:20.86$vck44/vblo=2,634.99 2006.201.12:07:20.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.12:07:20.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.12:07:20.86#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:20.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:20.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:20.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:20.86#ibcon#enter wrdev, iclass 30, count 0 2006.201.12:07:20.86#ibcon#first serial, iclass 30, count 0 2006.201.12:07:20.86#ibcon#enter sib2, iclass 30, count 0 2006.201.12:07:20.86#ibcon#flushed, iclass 30, count 0 2006.201.12:07:20.86#ibcon#about to write, iclass 30, count 0 2006.201.12:07:20.86#ibcon#wrote, iclass 30, count 0 2006.201.12:07:20.86#ibcon#about to read 3, iclass 30, count 0 2006.201.12:07:20.88#ibcon#read 3, iclass 30, count 0 2006.201.12:07:20.88#ibcon#about to read 4, iclass 30, count 0 2006.201.12:07:20.88#ibcon#read 4, iclass 30, count 0 2006.201.12:07:20.88#ibcon#about to read 5, iclass 30, count 0 2006.201.12:07:20.88#ibcon#read 5, iclass 30, count 0 2006.201.12:07:20.88#ibcon#about to read 6, iclass 30, count 0 2006.201.12:07:20.88#ibcon#read 6, iclass 30, count 0 2006.201.12:07:20.88#ibcon#end of sib2, iclass 30, count 0 2006.201.12:07:20.88#ibcon#*mode == 0, iclass 30, count 0 2006.201.12:07:20.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.12:07:20.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:07:20.88#ibcon#*before write, iclass 30, count 0 2006.201.12:07:20.88#ibcon#enter sib2, iclass 30, count 0 2006.201.12:07:20.88#ibcon#flushed, iclass 30, count 0 2006.201.12:07:20.88#ibcon#about to write, iclass 30, count 0 2006.201.12:07:20.88#ibcon#wrote, iclass 30, count 0 2006.201.12:07:20.88#ibcon#about to read 3, iclass 30, count 0 2006.201.12:07:20.92#ibcon#read 3, iclass 30, count 0 2006.201.12:07:20.92#ibcon#about to read 4, iclass 30, count 0 2006.201.12:07:20.92#ibcon#read 4, iclass 30, count 0 2006.201.12:07:20.92#ibcon#about to read 5, iclass 30, count 0 2006.201.12:07:20.92#ibcon#read 5, iclass 30, count 0 2006.201.12:07:20.92#ibcon#about to read 6, iclass 30, count 0 2006.201.12:07:20.92#ibcon#read 6, iclass 30, count 0 2006.201.12:07:20.92#ibcon#end of sib2, iclass 30, count 0 2006.201.12:07:20.92#ibcon#*after write, iclass 30, count 0 2006.201.12:07:20.92#ibcon#*before return 0, iclass 30, count 0 2006.201.12:07:20.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:20.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:07:20.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.12:07:20.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.12:07:20.92$vck44/vb=2,5 2006.201.12:07:20.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.12:07:20.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.12:07:20.92#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:20.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:20.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:20.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:20.98#ibcon#enter wrdev, iclass 32, count 2 2006.201.12:07:20.98#ibcon#first serial, iclass 32, count 2 2006.201.12:07:20.98#ibcon#enter sib2, iclass 32, count 2 2006.201.12:07:20.98#ibcon#flushed, iclass 32, count 2 2006.201.12:07:20.98#ibcon#about to write, iclass 32, count 2 2006.201.12:07:20.98#ibcon#wrote, iclass 32, count 2 2006.201.12:07:20.98#ibcon#about to read 3, iclass 32, count 2 2006.201.12:07:21.00#ibcon#read 3, iclass 32, count 2 2006.201.12:07:21.00#ibcon#about to read 4, iclass 32, count 2 2006.201.12:07:21.00#ibcon#read 4, iclass 32, count 2 2006.201.12:07:21.00#ibcon#about to read 5, iclass 32, count 2 2006.201.12:07:21.00#ibcon#read 5, iclass 32, count 2 2006.201.12:07:21.00#ibcon#about to read 6, iclass 32, count 2 2006.201.12:07:21.00#ibcon#read 6, iclass 32, count 2 2006.201.12:07:21.00#ibcon#end of sib2, iclass 32, count 2 2006.201.12:07:21.00#ibcon#*mode == 0, iclass 32, count 2 2006.201.12:07:21.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.12:07:21.00#ibcon#[27=AT02-05\r\n] 2006.201.12:07:21.00#ibcon#*before write, iclass 32, count 2 2006.201.12:07:21.00#ibcon#enter sib2, iclass 32, count 2 2006.201.12:07:21.00#ibcon#flushed, iclass 32, count 2 2006.201.12:07:21.00#ibcon#about to write, iclass 32, count 2 2006.201.12:07:21.00#ibcon#wrote, iclass 32, count 2 2006.201.12:07:21.00#ibcon#about to read 3, iclass 32, count 2 2006.201.12:07:21.03#ibcon#read 3, iclass 32, count 2 2006.201.12:07:21.03#ibcon#about to read 4, iclass 32, count 2 2006.201.12:07:21.03#ibcon#read 4, iclass 32, count 2 2006.201.12:07:21.03#ibcon#about to read 5, iclass 32, count 2 2006.201.12:07:21.03#ibcon#read 5, iclass 32, count 2 2006.201.12:07:21.03#ibcon#about to read 6, iclass 32, count 2 2006.201.12:07:21.03#ibcon#read 6, iclass 32, count 2 2006.201.12:07:21.03#ibcon#end of sib2, iclass 32, count 2 2006.201.12:07:21.03#ibcon#*after write, iclass 32, count 2 2006.201.12:07:21.03#ibcon#*before return 0, iclass 32, count 2 2006.201.12:07:21.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:21.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:07:21.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.12:07:21.03#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:21.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:21.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:21.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:21.15#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:07:21.15#ibcon#first serial, iclass 32, count 0 2006.201.12:07:21.15#ibcon#enter sib2, iclass 32, count 0 2006.201.12:07:21.15#ibcon#flushed, iclass 32, count 0 2006.201.12:07:21.15#ibcon#about to write, iclass 32, count 0 2006.201.12:07:21.15#ibcon#wrote, iclass 32, count 0 2006.201.12:07:21.15#ibcon#about to read 3, iclass 32, count 0 2006.201.12:07:21.17#ibcon#read 3, iclass 32, count 0 2006.201.12:07:21.17#ibcon#about to read 4, iclass 32, count 0 2006.201.12:07:21.17#ibcon#read 4, iclass 32, count 0 2006.201.12:07:21.17#ibcon#about to read 5, iclass 32, count 0 2006.201.12:07:21.17#ibcon#read 5, iclass 32, count 0 2006.201.12:07:21.17#ibcon#about to read 6, iclass 32, count 0 2006.201.12:07:21.17#ibcon#read 6, iclass 32, count 0 2006.201.12:07:21.17#ibcon#end of sib2, iclass 32, count 0 2006.201.12:07:21.17#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:07:21.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:07:21.17#ibcon#[27=USB\r\n] 2006.201.12:07:21.17#ibcon#*before write, iclass 32, count 0 2006.201.12:07:21.17#ibcon#enter sib2, iclass 32, count 0 2006.201.12:07:21.17#ibcon#flushed, iclass 32, count 0 2006.201.12:07:21.17#ibcon#about to write, iclass 32, count 0 2006.201.12:07:21.17#ibcon#wrote, iclass 32, count 0 2006.201.12:07:21.17#ibcon#about to read 3, iclass 32, count 0 2006.201.12:07:21.20#ibcon#read 3, iclass 32, count 0 2006.201.12:07:21.20#ibcon#about to read 4, iclass 32, count 0 2006.201.12:07:21.20#ibcon#read 4, iclass 32, count 0 2006.201.12:07:21.20#ibcon#about to read 5, iclass 32, count 0 2006.201.12:07:21.20#ibcon#read 5, iclass 32, count 0 2006.201.12:07:21.20#ibcon#about to read 6, iclass 32, count 0 2006.201.12:07:21.20#ibcon#read 6, iclass 32, count 0 2006.201.12:07:21.20#ibcon#end of sib2, iclass 32, count 0 2006.201.12:07:21.20#ibcon#*after write, iclass 32, count 0 2006.201.12:07:21.20#ibcon#*before return 0, iclass 32, count 0 2006.201.12:07:21.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:21.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:07:21.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:07:21.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:07:21.20$vck44/vblo=3,649.99 2006.201.12:07:21.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.12:07:21.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.12:07:21.20#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:21.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:21.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:21.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:21.20#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:07:21.20#ibcon#first serial, iclass 34, count 0 2006.201.12:07:21.20#ibcon#enter sib2, iclass 34, count 0 2006.201.12:07:21.20#ibcon#flushed, iclass 34, count 0 2006.201.12:07:21.20#ibcon#about to write, iclass 34, count 0 2006.201.12:07:21.20#ibcon#wrote, iclass 34, count 0 2006.201.12:07:21.20#ibcon#about to read 3, iclass 34, count 0 2006.201.12:07:21.22#ibcon#read 3, iclass 34, count 0 2006.201.12:07:21.22#ibcon#about to read 4, iclass 34, count 0 2006.201.12:07:21.22#ibcon#read 4, iclass 34, count 0 2006.201.12:07:21.22#ibcon#about to read 5, iclass 34, count 0 2006.201.12:07:21.22#ibcon#read 5, iclass 34, count 0 2006.201.12:07:21.22#ibcon#about to read 6, iclass 34, count 0 2006.201.12:07:21.22#ibcon#read 6, iclass 34, count 0 2006.201.12:07:21.22#ibcon#end of sib2, iclass 34, count 0 2006.201.12:07:21.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:07:21.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:07:21.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:07:21.22#ibcon#*before write, iclass 34, count 0 2006.201.12:07:21.22#ibcon#enter sib2, iclass 34, count 0 2006.201.12:07:21.22#ibcon#flushed, iclass 34, count 0 2006.201.12:07:21.22#ibcon#about to write, iclass 34, count 0 2006.201.12:07:21.22#ibcon#wrote, iclass 34, count 0 2006.201.12:07:21.22#ibcon#about to read 3, iclass 34, count 0 2006.201.12:07:21.26#ibcon#read 3, iclass 34, count 0 2006.201.12:07:21.26#ibcon#about to read 4, iclass 34, count 0 2006.201.12:07:21.26#ibcon#read 4, iclass 34, count 0 2006.201.12:07:21.26#ibcon#about to read 5, iclass 34, count 0 2006.201.12:07:21.26#ibcon#read 5, iclass 34, count 0 2006.201.12:07:21.26#ibcon#about to read 6, iclass 34, count 0 2006.201.12:07:21.26#ibcon#read 6, iclass 34, count 0 2006.201.12:07:21.26#ibcon#end of sib2, iclass 34, count 0 2006.201.12:07:21.26#ibcon#*after write, iclass 34, count 0 2006.201.12:07:21.26#ibcon#*before return 0, iclass 34, count 0 2006.201.12:07:21.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:21.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:07:21.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:07:21.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:07:21.26$vck44/vb=3,4 2006.201.12:07:21.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.12:07:21.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.12:07:21.26#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:21.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:21.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:21.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:21.32#ibcon#enter wrdev, iclass 36, count 2 2006.201.12:07:21.32#ibcon#first serial, iclass 36, count 2 2006.201.12:07:21.32#ibcon#enter sib2, iclass 36, count 2 2006.201.12:07:21.32#ibcon#flushed, iclass 36, count 2 2006.201.12:07:21.32#ibcon#about to write, iclass 36, count 2 2006.201.12:07:21.32#ibcon#wrote, iclass 36, count 2 2006.201.12:07:21.32#ibcon#about to read 3, iclass 36, count 2 2006.201.12:07:21.34#ibcon#read 3, iclass 36, count 2 2006.201.12:07:21.34#ibcon#about to read 4, iclass 36, count 2 2006.201.12:07:21.34#ibcon#read 4, iclass 36, count 2 2006.201.12:07:21.34#ibcon#about to read 5, iclass 36, count 2 2006.201.12:07:21.34#ibcon#read 5, iclass 36, count 2 2006.201.12:07:21.34#ibcon#about to read 6, iclass 36, count 2 2006.201.12:07:21.34#ibcon#read 6, iclass 36, count 2 2006.201.12:07:21.34#ibcon#end of sib2, iclass 36, count 2 2006.201.12:07:21.34#ibcon#*mode == 0, iclass 36, count 2 2006.201.12:07:21.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.12:07:21.34#ibcon#[27=AT03-04\r\n] 2006.201.12:07:21.34#ibcon#*before write, iclass 36, count 2 2006.201.12:07:21.34#ibcon#enter sib2, iclass 36, count 2 2006.201.12:07:21.34#ibcon#flushed, iclass 36, count 2 2006.201.12:07:21.34#ibcon#about to write, iclass 36, count 2 2006.201.12:07:21.34#ibcon#wrote, iclass 36, count 2 2006.201.12:07:21.34#ibcon#about to read 3, iclass 36, count 2 2006.201.12:07:21.37#ibcon#read 3, iclass 36, count 2 2006.201.12:07:21.37#ibcon#about to read 4, iclass 36, count 2 2006.201.12:07:21.37#ibcon#read 4, iclass 36, count 2 2006.201.12:07:21.37#ibcon#about to read 5, iclass 36, count 2 2006.201.12:07:21.37#ibcon#read 5, iclass 36, count 2 2006.201.12:07:21.37#ibcon#about to read 6, iclass 36, count 2 2006.201.12:07:21.37#ibcon#read 6, iclass 36, count 2 2006.201.12:07:21.37#ibcon#end of sib2, iclass 36, count 2 2006.201.12:07:21.37#ibcon#*after write, iclass 36, count 2 2006.201.12:07:21.37#ibcon#*before return 0, iclass 36, count 2 2006.201.12:07:21.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:21.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:07:21.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.12:07:21.37#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:21.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:21.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:21.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:21.49#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:07:21.49#ibcon#first serial, iclass 36, count 0 2006.201.12:07:21.49#ibcon#enter sib2, iclass 36, count 0 2006.201.12:07:21.49#ibcon#flushed, iclass 36, count 0 2006.201.12:07:21.49#ibcon#about to write, iclass 36, count 0 2006.201.12:07:21.49#ibcon#wrote, iclass 36, count 0 2006.201.12:07:21.49#ibcon#about to read 3, iclass 36, count 0 2006.201.12:07:21.51#ibcon#read 3, iclass 36, count 0 2006.201.12:07:21.51#ibcon#about to read 4, iclass 36, count 0 2006.201.12:07:21.51#ibcon#read 4, iclass 36, count 0 2006.201.12:07:21.51#ibcon#about to read 5, iclass 36, count 0 2006.201.12:07:21.51#ibcon#read 5, iclass 36, count 0 2006.201.12:07:21.51#ibcon#about to read 6, iclass 36, count 0 2006.201.12:07:21.51#ibcon#read 6, iclass 36, count 0 2006.201.12:07:21.51#ibcon#end of sib2, iclass 36, count 0 2006.201.12:07:21.51#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:07:21.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:07:21.51#ibcon#[27=USB\r\n] 2006.201.12:07:21.51#ibcon#*before write, iclass 36, count 0 2006.201.12:07:21.51#ibcon#enter sib2, iclass 36, count 0 2006.201.12:07:21.51#ibcon#flushed, iclass 36, count 0 2006.201.12:07:21.51#ibcon#about to write, iclass 36, count 0 2006.201.12:07:21.51#ibcon#wrote, iclass 36, count 0 2006.201.12:07:21.51#ibcon#about to read 3, iclass 36, count 0 2006.201.12:07:21.54#ibcon#read 3, iclass 36, count 0 2006.201.12:07:21.54#ibcon#about to read 4, iclass 36, count 0 2006.201.12:07:21.54#ibcon#read 4, iclass 36, count 0 2006.201.12:07:21.54#ibcon#about to read 5, iclass 36, count 0 2006.201.12:07:21.54#ibcon#read 5, iclass 36, count 0 2006.201.12:07:21.54#ibcon#about to read 6, iclass 36, count 0 2006.201.12:07:21.54#ibcon#read 6, iclass 36, count 0 2006.201.12:07:21.54#ibcon#end of sib2, iclass 36, count 0 2006.201.12:07:21.54#ibcon#*after write, iclass 36, count 0 2006.201.12:07:21.54#ibcon#*before return 0, iclass 36, count 0 2006.201.12:07:21.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:21.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:07:21.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:07:21.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:07:21.54$vck44/vblo=4,679.99 2006.201.12:07:21.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.12:07:21.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.12:07:21.54#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:21.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:21.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:21.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:21.54#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:07:21.54#ibcon#first serial, iclass 38, count 0 2006.201.12:07:21.54#ibcon#enter sib2, iclass 38, count 0 2006.201.12:07:21.54#ibcon#flushed, iclass 38, count 0 2006.201.12:07:21.54#ibcon#about to write, iclass 38, count 0 2006.201.12:07:21.54#ibcon#wrote, iclass 38, count 0 2006.201.12:07:21.54#ibcon#about to read 3, iclass 38, count 0 2006.201.12:07:21.56#ibcon#read 3, iclass 38, count 0 2006.201.12:07:21.56#ibcon#about to read 4, iclass 38, count 0 2006.201.12:07:21.56#ibcon#read 4, iclass 38, count 0 2006.201.12:07:21.56#ibcon#about to read 5, iclass 38, count 0 2006.201.12:07:21.56#ibcon#read 5, iclass 38, count 0 2006.201.12:07:21.56#ibcon#about to read 6, iclass 38, count 0 2006.201.12:07:21.56#ibcon#read 6, iclass 38, count 0 2006.201.12:07:21.56#ibcon#end of sib2, iclass 38, count 0 2006.201.12:07:21.56#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:07:21.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:07:21.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:07:21.56#ibcon#*before write, iclass 38, count 0 2006.201.12:07:21.56#ibcon#enter sib2, iclass 38, count 0 2006.201.12:07:21.56#ibcon#flushed, iclass 38, count 0 2006.201.12:07:21.56#ibcon#about to write, iclass 38, count 0 2006.201.12:07:21.56#ibcon#wrote, iclass 38, count 0 2006.201.12:07:21.56#ibcon#about to read 3, iclass 38, count 0 2006.201.12:07:21.60#ibcon#read 3, iclass 38, count 0 2006.201.12:07:21.60#ibcon#about to read 4, iclass 38, count 0 2006.201.12:07:21.60#ibcon#read 4, iclass 38, count 0 2006.201.12:07:21.60#ibcon#about to read 5, iclass 38, count 0 2006.201.12:07:21.60#ibcon#read 5, iclass 38, count 0 2006.201.12:07:21.60#ibcon#about to read 6, iclass 38, count 0 2006.201.12:07:21.60#ibcon#read 6, iclass 38, count 0 2006.201.12:07:21.60#ibcon#end of sib2, iclass 38, count 0 2006.201.12:07:21.60#ibcon#*after write, iclass 38, count 0 2006.201.12:07:21.60#ibcon#*before return 0, iclass 38, count 0 2006.201.12:07:21.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:21.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:07:21.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:07:21.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:07:21.60$vck44/vb=4,5 2006.201.12:07:21.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.12:07:21.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.12:07:21.60#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:21.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:21.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:21.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:21.66#ibcon#enter wrdev, iclass 40, count 2 2006.201.12:07:21.66#ibcon#first serial, iclass 40, count 2 2006.201.12:07:21.66#ibcon#enter sib2, iclass 40, count 2 2006.201.12:07:21.66#ibcon#flushed, iclass 40, count 2 2006.201.12:07:21.66#ibcon#about to write, iclass 40, count 2 2006.201.12:07:21.66#ibcon#wrote, iclass 40, count 2 2006.201.12:07:21.66#ibcon#about to read 3, iclass 40, count 2 2006.201.12:07:21.68#ibcon#read 3, iclass 40, count 2 2006.201.12:07:21.68#ibcon#about to read 4, iclass 40, count 2 2006.201.12:07:21.68#ibcon#read 4, iclass 40, count 2 2006.201.12:07:21.68#ibcon#about to read 5, iclass 40, count 2 2006.201.12:07:21.68#ibcon#read 5, iclass 40, count 2 2006.201.12:07:21.68#ibcon#about to read 6, iclass 40, count 2 2006.201.12:07:21.68#ibcon#read 6, iclass 40, count 2 2006.201.12:07:21.68#ibcon#end of sib2, iclass 40, count 2 2006.201.12:07:21.68#ibcon#*mode == 0, iclass 40, count 2 2006.201.12:07:21.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.12:07:21.68#ibcon#[27=AT04-05\r\n] 2006.201.12:07:21.68#ibcon#*before write, iclass 40, count 2 2006.201.12:07:21.68#ibcon#enter sib2, iclass 40, count 2 2006.201.12:07:21.68#ibcon#flushed, iclass 40, count 2 2006.201.12:07:21.68#ibcon#about to write, iclass 40, count 2 2006.201.12:07:21.68#ibcon#wrote, iclass 40, count 2 2006.201.12:07:21.68#ibcon#about to read 3, iclass 40, count 2 2006.201.12:07:21.71#ibcon#read 3, iclass 40, count 2 2006.201.12:07:21.71#ibcon#about to read 4, iclass 40, count 2 2006.201.12:07:21.71#ibcon#read 4, iclass 40, count 2 2006.201.12:07:21.71#ibcon#about to read 5, iclass 40, count 2 2006.201.12:07:21.71#ibcon#read 5, iclass 40, count 2 2006.201.12:07:21.71#ibcon#about to read 6, iclass 40, count 2 2006.201.12:07:21.71#ibcon#read 6, iclass 40, count 2 2006.201.12:07:21.71#ibcon#end of sib2, iclass 40, count 2 2006.201.12:07:21.71#ibcon#*after write, iclass 40, count 2 2006.201.12:07:21.71#ibcon#*before return 0, iclass 40, count 2 2006.201.12:07:21.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:21.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:07:21.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.12:07:21.71#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:21.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:21.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:21.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:21.83#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:07:21.83#ibcon#first serial, iclass 40, count 0 2006.201.12:07:21.83#ibcon#enter sib2, iclass 40, count 0 2006.201.12:07:21.83#ibcon#flushed, iclass 40, count 0 2006.201.12:07:21.83#ibcon#about to write, iclass 40, count 0 2006.201.12:07:21.83#ibcon#wrote, iclass 40, count 0 2006.201.12:07:21.83#ibcon#about to read 3, iclass 40, count 0 2006.201.12:07:21.85#ibcon#read 3, iclass 40, count 0 2006.201.12:07:21.85#ibcon#about to read 4, iclass 40, count 0 2006.201.12:07:21.85#ibcon#read 4, iclass 40, count 0 2006.201.12:07:21.85#ibcon#about to read 5, iclass 40, count 0 2006.201.12:07:21.85#ibcon#read 5, iclass 40, count 0 2006.201.12:07:21.85#ibcon#about to read 6, iclass 40, count 0 2006.201.12:07:21.85#ibcon#read 6, iclass 40, count 0 2006.201.12:07:21.85#ibcon#end of sib2, iclass 40, count 0 2006.201.12:07:21.85#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:07:21.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:07:21.85#ibcon#[27=USB\r\n] 2006.201.12:07:21.85#ibcon#*before write, iclass 40, count 0 2006.201.12:07:21.85#ibcon#enter sib2, iclass 40, count 0 2006.201.12:07:21.85#ibcon#flushed, iclass 40, count 0 2006.201.12:07:21.85#ibcon#about to write, iclass 40, count 0 2006.201.12:07:21.85#ibcon#wrote, iclass 40, count 0 2006.201.12:07:21.85#ibcon#about to read 3, iclass 40, count 0 2006.201.12:07:21.88#ibcon#read 3, iclass 40, count 0 2006.201.12:07:21.88#ibcon#about to read 4, iclass 40, count 0 2006.201.12:07:21.88#ibcon#read 4, iclass 40, count 0 2006.201.12:07:21.88#ibcon#about to read 5, iclass 40, count 0 2006.201.12:07:21.88#ibcon#read 5, iclass 40, count 0 2006.201.12:07:21.88#ibcon#about to read 6, iclass 40, count 0 2006.201.12:07:21.88#ibcon#read 6, iclass 40, count 0 2006.201.12:07:21.88#ibcon#end of sib2, iclass 40, count 0 2006.201.12:07:21.88#ibcon#*after write, iclass 40, count 0 2006.201.12:07:21.88#ibcon#*before return 0, iclass 40, count 0 2006.201.12:07:21.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:21.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:07:21.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:07:21.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:07:21.88$vck44/vblo=5,709.99 2006.201.12:07:21.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.12:07:21.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.12:07:21.88#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:21.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:21.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:21.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:21.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:07:21.88#ibcon#first serial, iclass 4, count 0 2006.201.12:07:21.88#ibcon#enter sib2, iclass 4, count 0 2006.201.12:07:21.88#ibcon#flushed, iclass 4, count 0 2006.201.12:07:21.88#ibcon#about to write, iclass 4, count 0 2006.201.12:07:21.88#ibcon#wrote, iclass 4, count 0 2006.201.12:07:21.88#ibcon#about to read 3, iclass 4, count 0 2006.201.12:07:21.90#ibcon#read 3, iclass 4, count 0 2006.201.12:07:21.90#ibcon#about to read 4, iclass 4, count 0 2006.201.12:07:21.90#ibcon#read 4, iclass 4, count 0 2006.201.12:07:21.90#ibcon#about to read 5, iclass 4, count 0 2006.201.12:07:21.90#ibcon#read 5, iclass 4, count 0 2006.201.12:07:21.90#ibcon#about to read 6, iclass 4, count 0 2006.201.12:07:21.90#ibcon#read 6, iclass 4, count 0 2006.201.12:07:21.90#ibcon#end of sib2, iclass 4, count 0 2006.201.12:07:21.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:07:21.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:07:21.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:07:21.90#ibcon#*before write, iclass 4, count 0 2006.201.12:07:21.90#ibcon#enter sib2, iclass 4, count 0 2006.201.12:07:21.90#ibcon#flushed, iclass 4, count 0 2006.201.12:07:21.90#ibcon#about to write, iclass 4, count 0 2006.201.12:07:21.90#ibcon#wrote, iclass 4, count 0 2006.201.12:07:21.90#ibcon#about to read 3, iclass 4, count 0 2006.201.12:07:21.94#ibcon#read 3, iclass 4, count 0 2006.201.12:07:21.94#ibcon#about to read 4, iclass 4, count 0 2006.201.12:07:21.94#ibcon#read 4, iclass 4, count 0 2006.201.12:07:21.94#ibcon#about to read 5, iclass 4, count 0 2006.201.12:07:21.94#ibcon#read 5, iclass 4, count 0 2006.201.12:07:21.94#ibcon#about to read 6, iclass 4, count 0 2006.201.12:07:21.94#ibcon#read 6, iclass 4, count 0 2006.201.12:07:21.94#ibcon#end of sib2, iclass 4, count 0 2006.201.12:07:21.94#ibcon#*after write, iclass 4, count 0 2006.201.12:07:21.94#ibcon#*before return 0, iclass 4, count 0 2006.201.12:07:21.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:21.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:07:21.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:07:21.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:07:21.94$vck44/vb=5,4 2006.201.12:07:21.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.12:07:21.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.12:07:21.94#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:21.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:22.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:22.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:22.00#ibcon#enter wrdev, iclass 6, count 2 2006.201.12:07:22.00#ibcon#first serial, iclass 6, count 2 2006.201.12:07:22.00#ibcon#enter sib2, iclass 6, count 2 2006.201.12:07:22.00#ibcon#flushed, iclass 6, count 2 2006.201.12:07:22.00#ibcon#about to write, iclass 6, count 2 2006.201.12:07:22.00#ibcon#wrote, iclass 6, count 2 2006.201.12:07:22.00#ibcon#about to read 3, iclass 6, count 2 2006.201.12:07:22.02#ibcon#read 3, iclass 6, count 2 2006.201.12:07:22.02#ibcon#about to read 4, iclass 6, count 2 2006.201.12:07:22.02#ibcon#read 4, iclass 6, count 2 2006.201.12:07:22.02#ibcon#about to read 5, iclass 6, count 2 2006.201.12:07:22.02#ibcon#read 5, iclass 6, count 2 2006.201.12:07:22.02#ibcon#about to read 6, iclass 6, count 2 2006.201.12:07:22.02#ibcon#read 6, iclass 6, count 2 2006.201.12:07:22.02#ibcon#end of sib2, iclass 6, count 2 2006.201.12:07:22.02#ibcon#*mode == 0, iclass 6, count 2 2006.201.12:07:22.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.12:07:22.02#ibcon#[27=AT05-04\r\n] 2006.201.12:07:22.02#ibcon#*before write, iclass 6, count 2 2006.201.12:07:22.02#ibcon#enter sib2, iclass 6, count 2 2006.201.12:07:22.02#ibcon#flushed, iclass 6, count 2 2006.201.12:07:22.02#ibcon#about to write, iclass 6, count 2 2006.201.12:07:22.02#ibcon#wrote, iclass 6, count 2 2006.201.12:07:22.02#ibcon#about to read 3, iclass 6, count 2 2006.201.12:07:22.05#ibcon#read 3, iclass 6, count 2 2006.201.12:07:22.05#ibcon#about to read 4, iclass 6, count 2 2006.201.12:07:22.05#ibcon#read 4, iclass 6, count 2 2006.201.12:07:22.05#ibcon#about to read 5, iclass 6, count 2 2006.201.12:07:22.05#ibcon#read 5, iclass 6, count 2 2006.201.12:07:22.05#ibcon#about to read 6, iclass 6, count 2 2006.201.12:07:22.05#ibcon#read 6, iclass 6, count 2 2006.201.12:07:22.05#ibcon#end of sib2, iclass 6, count 2 2006.201.12:07:22.05#ibcon#*after write, iclass 6, count 2 2006.201.12:07:22.05#ibcon#*before return 0, iclass 6, count 2 2006.201.12:07:22.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:22.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:07:22.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.12:07:22.05#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:22.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:22.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:22.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:22.17#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:07:22.17#ibcon#first serial, iclass 6, count 0 2006.201.12:07:22.17#ibcon#enter sib2, iclass 6, count 0 2006.201.12:07:22.17#ibcon#flushed, iclass 6, count 0 2006.201.12:07:22.17#ibcon#about to write, iclass 6, count 0 2006.201.12:07:22.17#ibcon#wrote, iclass 6, count 0 2006.201.12:07:22.17#ibcon#about to read 3, iclass 6, count 0 2006.201.12:07:22.19#ibcon#read 3, iclass 6, count 0 2006.201.12:07:22.19#ibcon#about to read 4, iclass 6, count 0 2006.201.12:07:22.19#ibcon#read 4, iclass 6, count 0 2006.201.12:07:22.19#ibcon#about to read 5, iclass 6, count 0 2006.201.12:07:22.19#ibcon#read 5, iclass 6, count 0 2006.201.12:07:22.19#ibcon#about to read 6, iclass 6, count 0 2006.201.12:07:22.19#ibcon#read 6, iclass 6, count 0 2006.201.12:07:22.19#ibcon#end of sib2, iclass 6, count 0 2006.201.12:07:22.19#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:07:22.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:07:22.19#ibcon#[27=USB\r\n] 2006.201.12:07:22.19#ibcon#*before write, iclass 6, count 0 2006.201.12:07:22.19#ibcon#enter sib2, iclass 6, count 0 2006.201.12:07:22.19#ibcon#flushed, iclass 6, count 0 2006.201.12:07:22.19#ibcon#about to write, iclass 6, count 0 2006.201.12:07:22.19#ibcon#wrote, iclass 6, count 0 2006.201.12:07:22.19#ibcon#about to read 3, iclass 6, count 0 2006.201.12:07:22.22#ibcon#read 3, iclass 6, count 0 2006.201.12:07:22.22#ibcon#about to read 4, iclass 6, count 0 2006.201.12:07:22.22#ibcon#read 4, iclass 6, count 0 2006.201.12:07:22.22#ibcon#about to read 5, iclass 6, count 0 2006.201.12:07:22.22#ibcon#read 5, iclass 6, count 0 2006.201.12:07:22.22#ibcon#about to read 6, iclass 6, count 0 2006.201.12:07:22.22#ibcon#read 6, iclass 6, count 0 2006.201.12:07:22.22#ibcon#end of sib2, iclass 6, count 0 2006.201.12:07:22.22#ibcon#*after write, iclass 6, count 0 2006.201.12:07:22.22#ibcon#*before return 0, iclass 6, count 0 2006.201.12:07:22.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:22.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:07:22.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:07:22.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:07:22.22$vck44/vblo=6,719.99 2006.201.12:07:22.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.12:07:22.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.12:07:22.22#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:22.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:22.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:22.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:22.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.12:07:22.22#ibcon#first serial, iclass 10, count 0 2006.201.12:07:22.22#ibcon#enter sib2, iclass 10, count 0 2006.201.12:07:22.22#ibcon#flushed, iclass 10, count 0 2006.201.12:07:22.22#ibcon#about to write, iclass 10, count 0 2006.201.12:07:22.22#ibcon#wrote, iclass 10, count 0 2006.201.12:07:22.22#ibcon#about to read 3, iclass 10, count 0 2006.201.12:07:22.24#ibcon#read 3, iclass 10, count 0 2006.201.12:07:22.24#ibcon#about to read 4, iclass 10, count 0 2006.201.12:07:22.24#ibcon#read 4, iclass 10, count 0 2006.201.12:07:22.24#ibcon#about to read 5, iclass 10, count 0 2006.201.12:07:22.24#ibcon#read 5, iclass 10, count 0 2006.201.12:07:22.24#ibcon#about to read 6, iclass 10, count 0 2006.201.12:07:22.24#ibcon#read 6, iclass 10, count 0 2006.201.12:07:22.24#ibcon#end of sib2, iclass 10, count 0 2006.201.12:07:22.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.12:07:22.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.12:07:22.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:07:22.24#ibcon#*before write, iclass 10, count 0 2006.201.12:07:22.24#ibcon#enter sib2, iclass 10, count 0 2006.201.12:07:22.24#ibcon#flushed, iclass 10, count 0 2006.201.12:07:22.24#ibcon#about to write, iclass 10, count 0 2006.201.12:07:22.24#ibcon#wrote, iclass 10, count 0 2006.201.12:07:22.24#ibcon#about to read 3, iclass 10, count 0 2006.201.12:07:22.28#ibcon#read 3, iclass 10, count 0 2006.201.12:07:22.28#ibcon#about to read 4, iclass 10, count 0 2006.201.12:07:22.28#ibcon#read 4, iclass 10, count 0 2006.201.12:07:22.28#ibcon#about to read 5, iclass 10, count 0 2006.201.12:07:22.28#ibcon#read 5, iclass 10, count 0 2006.201.12:07:22.28#ibcon#about to read 6, iclass 10, count 0 2006.201.12:07:22.28#ibcon#read 6, iclass 10, count 0 2006.201.12:07:22.28#ibcon#end of sib2, iclass 10, count 0 2006.201.12:07:22.28#ibcon#*after write, iclass 10, count 0 2006.201.12:07:22.28#ibcon#*before return 0, iclass 10, count 0 2006.201.12:07:22.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:22.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:07:22.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.12:07:22.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.12:07:22.28$vck44/vb=6,4 2006.201.12:07:22.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.12:07:22.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.12:07:22.28#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:22.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:22.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:22.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:22.34#ibcon#enter wrdev, iclass 12, count 2 2006.201.12:07:22.34#ibcon#first serial, iclass 12, count 2 2006.201.12:07:22.34#ibcon#enter sib2, iclass 12, count 2 2006.201.12:07:22.34#ibcon#flushed, iclass 12, count 2 2006.201.12:07:22.34#ibcon#about to write, iclass 12, count 2 2006.201.12:07:22.34#ibcon#wrote, iclass 12, count 2 2006.201.12:07:22.34#ibcon#about to read 3, iclass 12, count 2 2006.201.12:07:22.36#ibcon#read 3, iclass 12, count 2 2006.201.12:07:22.36#ibcon#about to read 4, iclass 12, count 2 2006.201.12:07:22.36#ibcon#read 4, iclass 12, count 2 2006.201.12:07:22.36#ibcon#about to read 5, iclass 12, count 2 2006.201.12:07:22.36#ibcon#read 5, iclass 12, count 2 2006.201.12:07:22.36#ibcon#about to read 6, iclass 12, count 2 2006.201.12:07:22.36#ibcon#read 6, iclass 12, count 2 2006.201.12:07:22.36#ibcon#end of sib2, iclass 12, count 2 2006.201.12:07:22.36#ibcon#*mode == 0, iclass 12, count 2 2006.201.12:07:22.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.12:07:22.36#ibcon#[27=AT06-04\r\n] 2006.201.12:07:22.36#ibcon#*before write, iclass 12, count 2 2006.201.12:07:22.36#ibcon#enter sib2, iclass 12, count 2 2006.201.12:07:22.36#ibcon#flushed, iclass 12, count 2 2006.201.12:07:22.36#ibcon#about to write, iclass 12, count 2 2006.201.12:07:22.36#ibcon#wrote, iclass 12, count 2 2006.201.12:07:22.36#ibcon#about to read 3, iclass 12, count 2 2006.201.12:07:22.39#ibcon#read 3, iclass 12, count 2 2006.201.12:07:22.39#ibcon#about to read 4, iclass 12, count 2 2006.201.12:07:22.39#ibcon#read 4, iclass 12, count 2 2006.201.12:07:22.39#ibcon#about to read 5, iclass 12, count 2 2006.201.12:07:22.39#ibcon#read 5, iclass 12, count 2 2006.201.12:07:22.39#ibcon#about to read 6, iclass 12, count 2 2006.201.12:07:22.39#ibcon#read 6, iclass 12, count 2 2006.201.12:07:22.39#ibcon#end of sib2, iclass 12, count 2 2006.201.12:07:22.39#ibcon#*after write, iclass 12, count 2 2006.201.12:07:22.39#ibcon#*before return 0, iclass 12, count 2 2006.201.12:07:22.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:22.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:07:22.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.12:07:22.39#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:22.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:22.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:22.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:22.51#ibcon#enter wrdev, iclass 12, count 0 2006.201.12:07:22.51#ibcon#first serial, iclass 12, count 0 2006.201.12:07:22.51#ibcon#enter sib2, iclass 12, count 0 2006.201.12:07:22.51#ibcon#flushed, iclass 12, count 0 2006.201.12:07:22.51#ibcon#about to write, iclass 12, count 0 2006.201.12:07:22.51#ibcon#wrote, iclass 12, count 0 2006.201.12:07:22.51#ibcon#about to read 3, iclass 12, count 0 2006.201.12:07:22.53#ibcon#read 3, iclass 12, count 0 2006.201.12:07:22.53#ibcon#about to read 4, iclass 12, count 0 2006.201.12:07:22.53#ibcon#read 4, iclass 12, count 0 2006.201.12:07:22.53#ibcon#about to read 5, iclass 12, count 0 2006.201.12:07:22.53#ibcon#read 5, iclass 12, count 0 2006.201.12:07:22.53#ibcon#about to read 6, iclass 12, count 0 2006.201.12:07:22.53#ibcon#read 6, iclass 12, count 0 2006.201.12:07:22.53#ibcon#end of sib2, iclass 12, count 0 2006.201.12:07:22.53#ibcon#*mode == 0, iclass 12, count 0 2006.201.12:07:22.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.12:07:22.53#ibcon#[27=USB\r\n] 2006.201.12:07:22.53#ibcon#*before write, iclass 12, count 0 2006.201.12:07:22.53#ibcon#enter sib2, iclass 12, count 0 2006.201.12:07:22.53#ibcon#flushed, iclass 12, count 0 2006.201.12:07:22.53#ibcon#about to write, iclass 12, count 0 2006.201.12:07:22.53#ibcon#wrote, iclass 12, count 0 2006.201.12:07:22.53#ibcon#about to read 3, iclass 12, count 0 2006.201.12:07:22.56#ibcon#read 3, iclass 12, count 0 2006.201.12:07:22.56#ibcon#about to read 4, iclass 12, count 0 2006.201.12:07:22.56#ibcon#read 4, iclass 12, count 0 2006.201.12:07:22.56#ibcon#about to read 5, iclass 12, count 0 2006.201.12:07:22.56#ibcon#read 5, iclass 12, count 0 2006.201.12:07:22.56#ibcon#about to read 6, iclass 12, count 0 2006.201.12:07:22.56#ibcon#read 6, iclass 12, count 0 2006.201.12:07:22.56#ibcon#end of sib2, iclass 12, count 0 2006.201.12:07:22.56#ibcon#*after write, iclass 12, count 0 2006.201.12:07:22.56#ibcon#*before return 0, iclass 12, count 0 2006.201.12:07:22.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:22.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:07:22.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.12:07:22.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.12:07:22.56$vck44/vblo=7,734.99 2006.201.12:07:22.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.12:07:22.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.12:07:22.56#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:22.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:22.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:22.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:22.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.12:07:22.56#ibcon#first serial, iclass 14, count 0 2006.201.12:07:22.56#ibcon#enter sib2, iclass 14, count 0 2006.201.12:07:22.56#ibcon#flushed, iclass 14, count 0 2006.201.12:07:22.56#ibcon#about to write, iclass 14, count 0 2006.201.12:07:22.56#ibcon#wrote, iclass 14, count 0 2006.201.12:07:22.56#ibcon#about to read 3, iclass 14, count 0 2006.201.12:07:22.58#ibcon#read 3, iclass 14, count 0 2006.201.12:07:22.58#ibcon#about to read 4, iclass 14, count 0 2006.201.12:07:22.58#ibcon#read 4, iclass 14, count 0 2006.201.12:07:22.58#ibcon#about to read 5, iclass 14, count 0 2006.201.12:07:22.58#ibcon#read 5, iclass 14, count 0 2006.201.12:07:22.58#ibcon#about to read 6, iclass 14, count 0 2006.201.12:07:22.58#ibcon#read 6, iclass 14, count 0 2006.201.12:07:22.58#ibcon#end of sib2, iclass 14, count 0 2006.201.12:07:22.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.12:07:22.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.12:07:22.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:07:22.58#ibcon#*before write, iclass 14, count 0 2006.201.12:07:22.58#ibcon#enter sib2, iclass 14, count 0 2006.201.12:07:22.58#ibcon#flushed, iclass 14, count 0 2006.201.12:07:22.58#ibcon#about to write, iclass 14, count 0 2006.201.12:07:22.58#ibcon#wrote, iclass 14, count 0 2006.201.12:07:22.58#ibcon#about to read 3, iclass 14, count 0 2006.201.12:07:22.62#ibcon#read 3, iclass 14, count 0 2006.201.12:07:22.62#ibcon#about to read 4, iclass 14, count 0 2006.201.12:07:22.62#ibcon#read 4, iclass 14, count 0 2006.201.12:07:22.62#ibcon#about to read 5, iclass 14, count 0 2006.201.12:07:22.62#ibcon#read 5, iclass 14, count 0 2006.201.12:07:22.62#ibcon#about to read 6, iclass 14, count 0 2006.201.12:07:22.62#ibcon#read 6, iclass 14, count 0 2006.201.12:07:22.62#ibcon#end of sib2, iclass 14, count 0 2006.201.12:07:22.62#ibcon#*after write, iclass 14, count 0 2006.201.12:07:22.62#ibcon#*before return 0, iclass 14, count 0 2006.201.12:07:22.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:22.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:07:22.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.12:07:22.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.12:07:22.62$vck44/vb=7,4 2006.201.12:07:22.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.12:07:22.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.12:07:22.62#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:22.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:22.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:22.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:22.68#ibcon#enter wrdev, iclass 16, count 2 2006.201.12:07:22.68#ibcon#first serial, iclass 16, count 2 2006.201.12:07:22.68#ibcon#enter sib2, iclass 16, count 2 2006.201.12:07:22.68#ibcon#flushed, iclass 16, count 2 2006.201.12:07:22.68#ibcon#about to write, iclass 16, count 2 2006.201.12:07:22.68#ibcon#wrote, iclass 16, count 2 2006.201.12:07:22.68#ibcon#about to read 3, iclass 16, count 2 2006.201.12:07:22.70#ibcon#read 3, iclass 16, count 2 2006.201.12:07:22.70#ibcon#about to read 4, iclass 16, count 2 2006.201.12:07:22.70#ibcon#read 4, iclass 16, count 2 2006.201.12:07:22.70#ibcon#about to read 5, iclass 16, count 2 2006.201.12:07:22.70#ibcon#read 5, iclass 16, count 2 2006.201.12:07:22.70#ibcon#about to read 6, iclass 16, count 2 2006.201.12:07:22.70#ibcon#read 6, iclass 16, count 2 2006.201.12:07:22.70#ibcon#end of sib2, iclass 16, count 2 2006.201.12:07:22.70#ibcon#*mode == 0, iclass 16, count 2 2006.201.12:07:22.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.12:07:22.70#ibcon#[27=AT07-04\r\n] 2006.201.12:07:22.70#ibcon#*before write, iclass 16, count 2 2006.201.12:07:22.70#ibcon#enter sib2, iclass 16, count 2 2006.201.12:07:22.70#ibcon#flushed, iclass 16, count 2 2006.201.12:07:22.70#ibcon#about to write, iclass 16, count 2 2006.201.12:07:22.70#ibcon#wrote, iclass 16, count 2 2006.201.12:07:22.70#ibcon#about to read 3, iclass 16, count 2 2006.201.12:07:22.73#ibcon#read 3, iclass 16, count 2 2006.201.12:07:22.73#ibcon#about to read 4, iclass 16, count 2 2006.201.12:07:22.73#ibcon#read 4, iclass 16, count 2 2006.201.12:07:22.73#ibcon#about to read 5, iclass 16, count 2 2006.201.12:07:22.73#ibcon#read 5, iclass 16, count 2 2006.201.12:07:22.73#ibcon#about to read 6, iclass 16, count 2 2006.201.12:07:22.73#ibcon#read 6, iclass 16, count 2 2006.201.12:07:22.73#ibcon#end of sib2, iclass 16, count 2 2006.201.12:07:22.73#ibcon#*after write, iclass 16, count 2 2006.201.12:07:22.73#ibcon#*before return 0, iclass 16, count 2 2006.201.12:07:22.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:22.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:07:22.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.12:07:22.73#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:22.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:22.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:22.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:22.85#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:07:22.85#ibcon#first serial, iclass 16, count 0 2006.201.12:07:22.85#ibcon#enter sib2, iclass 16, count 0 2006.201.12:07:22.85#ibcon#flushed, iclass 16, count 0 2006.201.12:07:22.85#ibcon#about to write, iclass 16, count 0 2006.201.12:07:22.85#ibcon#wrote, iclass 16, count 0 2006.201.12:07:22.85#ibcon#about to read 3, iclass 16, count 0 2006.201.12:07:22.87#ibcon#read 3, iclass 16, count 0 2006.201.12:07:22.87#ibcon#about to read 4, iclass 16, count 0 2006.201.12:07:22.87#ibcon#read 4, iclass 16, count 0 2006.201.12:07:22.87#ibcon#about to read 5, iclass 16, count 0 2006.201.12:07:22.87#ibcon#read 5, iclass 16, count 0 2006.201.12:07:22.87#ibcon#about to read 6, iclass 16, count 0 2006.201.12:07:22.87#ibcon#read 6, iclass 16, count 0 2006.201.12:07:22.87#ibcon#end of sib2, iclass 16, count 0 2006.201.12:07:22.87#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:07:22.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:07:22.87#ibcon#[27=USB\r\n] 2006.201.12:07:22.87#ibcon#*before write, iclass 16, count 0 2006.201.12:07:22.87#ibcon#enter sib2, iclass 16, count 0 2006.201.12:07:22.87#ibcon#flushed, iclass 16, count 0 2006.201.12:07:22.87#ibcon#about to write, iclass 16, count 0 2006.201.12:07:22.87#ibcon#wrote, iclass 16, count 0 2006.201.12:07:22.87#ibcon#about to read 3, iclass 16, count 0 2006.201.12:07:22.90#ibcon#read 3, iclass 16, count 0 2006.201.12:07:22.90#ibcon#about to read 4, iclass 16, count 0 2006.201.12:07:22.90#ibcon#read 4, iclass 16, count 0 2006.201.12:07:22.90#ibcon#about to read 5, iclass 16, count 0 2006.201.12:07:22.90#ibcon#read 5, iclass 16, count 0 2006.201.12:07:22.90#ibcon#about to read 6, iclass 16, count 0 2006.201.12:07:22.90#ibcon#read 6, iclass 16, count 0 2006.201.12:07:22.90#ibcon#end of sib2, iclass 16, count 0 2006.201.12:07:22.90#ibcon#*after write, iclass 16, count 0 2006.201.12:07:22.90#ibcon#*before return 0, iclass 16, count 0 2006.201.12:07:22.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:22.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:07:22.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:07:22.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:07:22.90$vck44/vblo=8,744.99 2006.201.12:07:22.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.12:07:22.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.12:07:22.90#ibcon#ireg 17 cls_cnt 0 2006.201.12:07:22.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:22.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:22.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:22.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:07:22.90#ibcon#first serial, iclass 18, count 0 2006.201.12:07:22.90#ibcon#enter sib2, iclass 18, count 0 2006.201.12:07:22.90#ibcon#flushed, iclass 18, count 0 2006.201.12:07:22.90#ibcon#about to write, iclass 18, count 0 2006.201.12:07:22.90#ibcon#wrote, iclass 18, count 0 2006.201.12:07:22.90#ibcon#about to read 3, iclass 18, count 0 2006.201.12:07:22.92#ibcon#read 3, iclass 18, count 0 2006.201.12:07:22.92#ibcon#about to read 4, iclass 18, count 0 2006.201.12:07:22.92#ibcon#read 4, iclass 18, count 0 2006.201.12:07:22.92#ibcon#about to read 5, iclass 18, count 0 2006.201.12:07:22.92#ibcon#read 5, iclass 18, count 0 2006.201.12:07:22.92#ibcon#about to read 6, iclass 18, count 0 2006.201.12:07:22.92#ibcon#read 6, iclass 18, count 0 2006.201.12:07:22.92#ibcon#end of sib2, iclass 18, count 0 2006.201.12:07:22.92#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:07:22.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:07:22.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:07:22.92#ibcon#*before write, iclass 18, count 0 2006.201.12:07:22.92#ibcon#enter sib2, iclass 18, count 0 2006.201.12:07:22.92#ibcon#flushed, iclass 18, count 0 2006.201.12:07:22.92#ibcon#about to write, iclass 18, count 0 2006.201.12:07:22.92#ibcon#wrote, iclass 18, count 0 2006.201.12:07:22.92#ibcon#about to read 3, iclass 18, count 0 2006.201.12:07:22.97#ibcon#read 3, iclass 18, count 0 2006.201.12:07:22.97#ibcon#about to read 4, iclass 18, count 0 2006.201.12:07:22.97#ibcon#read 4, iclass 18, count 0 2006.201.12:07:22.97#ibcon#about to read 5, iclass 18, count 0 2006.201.12:07:22.97#ibcon#read 5, iclass 18, count 0 2006.201.12:07:22.97#ibcon#about to read 6, iclass 18, count 0 2006.201.12:07:22.97#ibcon#read 6, iclass 18, count 0 2006.201.12:07:22.97#ibcon#end of sib2, iclass 18, count 0 2006.201.12:07:22.97#ibcon#*after write, iclass 18, count 0 2006.201.12:07:22.97#ibcon#*before return 0, iclass 18, count 0 2006.201.12:07:22.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:22.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:07:22.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:07:22.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:07:22.97$vck44/vb=8,4 2006.201.12:07:22.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.12:07:22.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.12:07:22.97#ibcon#ireg 11 cls_cnt 2 2006.201.12:07:22.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:23.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:23.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:23.02#ibcon#enter wrdev, iclass 20, count 2 2006.201.12:07:23.02#ibcon#first serial, iclass 20, count 2 2006.201.12:07:23.02#ibcon#enter sib2, iclass 20, count 2 2006.201.12:07:23.02#ibcon#flushed, iclass 20, count 2 2006.201.12:07:23.02#ibcon#about to write, iclass 20, count 2 2006.201.12:07:23.02#ibcon#wrote, iclass 20, count 2 2006.201.12:07:23.02#ibcon#about to read 3, iclass 20, count 2 2006.201.12:07:23.04#ibcon#read 3, iclass 20, count 2 2006.201.12:07:23.04#ibcon#about to read 4, iclass 20, count 2 2006.201.12:07:23.04#ibcon#read 4, iclass 20, count 2 2006.201.12:07:23.04#ibcon#about to read 5, iclass 20, count 2 2006.201.12:07:23.04#ibcon#read 5, iclass 20, count 2 2006.201.12:07:23.04#ibcon#about to read 6, iclass 20, count 2 2006.201.12:07:23.04#ibcon#read 6, iclass 20, count 2 2006.201.12:07:23.04#ibcon#end of sib2, iclass 20, count 2 2006.201.12:07:23.04#ibcon#*mode == 0, iclass 20, count 2 2006.201.12:07:23.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.12:07:23.04#ibcon#[27=AT08-04\r\n] 2006.201.12:07:23.04#ibcon#*before write, iclass 20, count 2 2006.201.12:07:23.04#ibcon#enter sib2, iclass 20, count 2 2006.201.12:07:23.04#ibcon#flushed, iclass 20, count 2 2006.201.12:07:23.04#ibcon#about to write, iclass 20, count 2 2006.201.12:07:23.04#ibcon#wrote, iclass 20, count 2 2006.201.12:07:23.04#ibcon#about to read 3, iclass 20, count 2 2006.201.12:07:23.07#ibcon#read 3, iclass 20, count 2 2006.201.12:07:23.07#ibcon#about to read 4, iclass 20, count 2 2006.201.12:07:23.07#ibcon#read 4, iclass 20, count 2 2006.201.12:07:23.07#ibcon#about to read 5, iclass 20, count 2 2006.201.12:07:23.07#ibcon#read 5, iclass 20, count 2 2006.201.12:07:23.07#ibcon#about to read 6, iclass 20, count 2 2006.201.12:07:23.07#ibcon#read 6, iclass 20, count 2 2006.201.12:07:23.07#ibcon#end of sib2, iclass 20, count 2 2006.201.12:07:23.07#ibcon#*after write, iclass 20, count 2 2006.201.12:07:23.07#ibcon#*before return 0, iclass 20, count 2 2006.201.12:07:23.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:23.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:07:23.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.12:07:23.07#ibcon#ireg 7 cls_cnt 0 2006.201.12:07:23.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:23.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:23.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:23.19#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:07:23.19#ibcon#first serial, iclass 20, count 0 2006.201.12:07:23.19#ibcon#enter sib2, iclass 20, count 0 2006.201.12:07:23.19#ibcon#flushed, iclass 20, count 0 2006.201.12:07:23.19#ibcon#about to write, iclass 20, count 0 2006.201.12:07:23.19#ibcon#wrote, iclass 20, count 0 2006.201.12:07:23.19#ibcon#about to read 3, iclass 20, count 0 2006.201.12:07:23.20#abcon#<5=/04 1.7 3.1 21.251001004.0\r\n> 2006.201.12:07:23.21#ibcon#read 3, iclass 20, count 0 2006.201.12:07:23.21#ibcon#about to read 4, iclass 20, count 0 2006.201.12:07:23.21#ibcon#read 4, iclass 20, count 0 2006.201.12:07:23.21#ibcon#about to read 5, iclass 20, count 0 2006.201.12:07:23.21#ibcon#read 5, iclass 20, count 0 2006.201.12:07:23.21#ibcon#about to read 6, iclass 20, count 0 2006.201.12:07:23.21#ibcon#read 6, iclass 20, count 0 2006.201.12:07:23.21#ibcon#end of sib2, iclass 20, count 0 2006.201.12:07:23.21#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:07:23.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:07:23.21#ibcon#[27=USB\r\n] 2006.201.12:07:23.21#ibcon#*before write, iclass 20, count 0 2006.201.12:07:23.21#ibcon#enter sib2, iclass 20, count 0 2006.201.12:07:23.21#ibcon#flushed, iclass 20, count 0 2006.201.12:07:23.21#ibcon#about to write, iclass 20, count 0 2006.201.12:07:23.21#ibcon#wrote, iclass 20, count 0 2006.201.12:07:23.21#ibcon#about to read 3, iclass 20, count 0 2006.201.12:07:23.22#abcon#{5=INTERFACE CLEAR} 2006.201.12:07:23.24#ibcon#read 3, iclass 20, count 0 2006.201.12:07:23.24#ibcon#about to read 4, iclass 20, count 0 2006.201.12:07:23.24#ibcon#read 4, iclass 20, count 0 2006.201.12:07:23.24#ibcon#about to read 5, iclass 20, count 0 2006.201.12:07:23.24#ibcon#read 5, iclass 20, count 0 2006.201.12:07:23.24#ibcon#about to read 6, iclass 20, count 0 2006.201.12:07:23.24#ibcon#read 6, iclass 20, count 0 2006.201.12:07:23.24#ibcon#end of sib2, iclass 20, count 0 2006.201.12:07:23.24#ibcon#*after write, iclass 20, count 0 2006.201.12:07:23.24#ibcon#*before return 0, iclass 20, count 0 2006.201.12:07:23.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:23.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:07:23.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:07:23.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:07:23.24$vck44/vabw=wide 2006.201.12:07:23.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.12:07:23.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.12:07:23.24#ibcon#ireg 8 cls_cnt 0 2006.201.12:07:23.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:07:23.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:07:23.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:07:23.24#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:07:23.24#ibcon#first serial, iclass 25, count 0 2006.201.12:07:23.24#ibcon#enter sib2, iclass 25, count 0 2006.201.12:07:23.24#ibcon#flushed, iclass 25, count 0 2006.201.12:07:23.24#ibcon#about to write, iclass 25, count 0 2006.201.12:07:23.24#ibcon#wrote, iclass 25, count 0 2006.201.12:07:23.24#ibcon#about to read 3, iclass 25, count 0 2006.201.12:07:23.26#ibcon#read 3, iclass 25, count 0 2006.201.12:07:23.26#ibcon#about to read 4, iclass 25, count 0 2006.201.12:07:23.26#ibcon#read 4, iclass 25, count 0 2006.201.12:07:23.26#ibcon#about to read 5, iclass 25, count 0 2006.201.12:07:23.26#ibcon#read 5, iclass 25, count 0 2006.201.12:07:23.26#ibcon#about to read 6, iclass 25, count 0 2006.201.12:07:23.26#ibcon#read 6, iclass 25, count 0 2006.201.12:07:23.26#ibcon#end of sib2, iclass 25, count 0 2006.201.12:07:23.26#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:07:23.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:07:23.26#ibcon#[25=BW32\r\n] 2006.201.12:07:23.26#ibcon#*before write, iclass 25, count 0 2006.201.12:07:23.26#ibcon#enter sib2, iclass 25, count 0 2006.201.12:07:23.26#ibcon#flushed, iclass 25, count 0 2006.201.12:07:23.26#ibcon#about to write, iclass 25, count 0 2006.201.12:07:23.26#ibcon#wrote, iclass 25, count 0 2006.201.12:07:23.26#ibcon#about to read 3, iclass 25, count 0 2006.201.12:07:23.28#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:07:23.29#ibcon#read 3, iclass 25, count 0 2006.201.12:07:23.29#ibcon#about to read 4, iclass 25, count 0 2006.201.12:07:23.29#ibcon#read 4, iclass 25, count 0 2006.201.12:07:23.29#ibcon#about to read 5, iclass 25, count 0 2006.201.12:07:23.29#ibcon#read 5, iclass 25, count 0 2006.201.12:07:23.29#ibcon#about to read 6, iclass 25, count 0 2006.201.12:07:23.29#ibcon#read 6, iclass 25, count 0 2006.201.12:07:23.29#ibcon#end of sib2, iclass 25, count 0 2006.201.12:07:23.29#ibcon#*after write, iclass 25, count 0 2006.201.12:07:23.29#ibcon#*before return 0, iclass 25, count 0 2006.201.12:07:23.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:07:23.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:07:23.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:07:23.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:07:23.29$vck44/vbbw=wide 2006.201.12:07:23.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.12:07:23.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.12:07:23.29#ibcon#ireg 8 cls_cnt 0 2006.201.12:07:23.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:07:23.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:07:23.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:07:23.36#ibcon#enter wrdev, iclass 28, count 0 2006.201.12:07:23.36#ibcon#first serial, iclass 28, count 0 2006.201.12:07:23.36#ibcon#enter sib2, iclass 28, count 0 2006.201.12:07:23.36#ibcon#flushed, iclass 28, count 0 2006.201.12:07:23.36#ibcon#about to write, iclass 28, count 0 2006.201.12:07:23.36#ibcon#wrote, iclass 28, count 0 2006.201.12:07:23.36#ibcon#about to read 3, iclass 28, count 0 2006.201.12:07:23.38#ibcon#read 3, iclass 28, count 0 2006.201.12:07:23.38#ibcon#about to read 4, iclass 28, count 0 2006.201.12:07:23.38#ibcon#read 4, iclass 28, count 0 2006.201.12:07:23.38#ibcon#about to read 5, iclass 28, count 0 2006.201.12:07:23.38#ibcon#read 5, iclass 28, count 0 2006.201.12:07:23.38#ibcon#about to read 6, iclass 28, count 0 2006.201.12:07:23.38#ibcon#read 6, iclass 28, count 0 2006.201.12:07:23.38#ibcon#end of sib2, iclass 28, count 0 2006.201.12:07:23.38#ibcon#*mode == 0, iclass 28, count 0 2006.201.12:07:23.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.12:07:23.38#ibcon#[27=BW32\r\n] 2006.201.12:07:23.38#ibcon#*before write, iclass 28, count 0 2006.201.12:07:23.38#ibcon#enter sib2, iclass 28, count 0 2006.201.12:07:23.38#ibcon#flushed, iclass 28, count 0 2006.201.12:07:23.38#ibcon#about to write, iclass 28, count 0 2006.201.12:07:23.38#ibcon#wrote, iclass 28, count 0 2006.201.12:07:23.38#ibcon#about to read 3, iclass 28, count 0 2006.201.12:07:23.41#ibcon#read 3, iclass 28, count 0 2006.201.12:07:23.41#ibcon#about to read 4, iclass 28, count 0 2006.201.12:07:23.41#ibcon#read 4, iclass 28, count 0 2006.201.12:07:23.41#ibcon#about to read 5, iclass 28, count 0 2006.201.12:07:23.41#ibcon#read 5, iclass 28, count 0 2006.201.12:07:23.41#ibcon#about to read 6, iclass 28, count 0 2006.201.12:07:23.41#ibcon#read 6, iclass 28, count 0 2006.201.12:07:23.41#ibcon#end of sib2, iclass 28, count 0 2006.201.12:07:23.41#ibcon#*after write, iclass 28, count 0 2006.201.12:07:23.41#ibcon#*before return 0, iclass 28, count 0 2006.201.12:07:23.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:07:23.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:07:23.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.12:07:23.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.12:07:23.41$setupk4/ifdk4 2006.201.12:07:23.41$ifdk4/lo= 2006.201.12:07:23.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:07:23.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:07:23.41$ifdk4/patch= 2006.201.12:07:23.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:07:23.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:07:23.41$setupk4/!*+20s 2006.201.12:07:33.37#abcon#<5=/04 1.7 3.1 21.251001004.0\r\n> 2006.201.12:07:33.39#abcon#{5=INTERFACE CLEAR} 2006.201.12:07:33.45#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:07:37.13#trakl#Source acquired 2006.201.12:07:37.13#flagr#flagr/antenna,acquired 2006.201.12:07:37.88$setupk4/"tpicd 2006.201.12:07:37.88$setupk4/echo=off 2006.201.12:07:37.88$setupk4/xlog=off 2006.201.12:07:37.88:!2006.201.12:09:55 2006.201.12:09:55.00:preob 2006.201.12:09:56.14/onsource/TRACKING 2006.201.12:09:56.14:!2006.201.12:10:05 2006.201.12:10:05.00:"tape 2006.201.12:10:05.00:"st=record 2006.201.12:10:05.00:data_valid=on 2006.201.12:10:05.00:midob 2006.201.12:10:05.14/onsource/TRACKING 2006.201.12:10:05.14/wx/21.24,1003.9,100 2006.201.12:10:05.29/cable/+6.4726E-03 2006.201.12:10:06.38/va/01,08,usb,yes,31,33 2006.201.12:10:06.38/va/02,07,usb,yes,33,34 2006.201.12:10:06.38/va/03,08,usb,yes,30,31 2006.201.12:10:06.38/va/04,07,usb,yes,34,36 2006.201.12:10:06.38/va/05,04,usb,yes,30,31 2006.201.12:10:06.38/va/06,05,usb,yes,30,30 2006.201.12:10:06.38/va/07,05,usb,yes,29,31 2006.201.12:10:06.38/va/08,04,usb,yes,29,35 2006.201.12:10:06.61/valo/01,524.99,yes,locked 2006.201.12:10:06.61/valo/02,534.99,yes,locked 2006.201.12:10:06.61/valo/03,564.99,yes,locked 2006.201.12:10:06.61/valo/04,624.99,yes,locked 2006.201.12:10:06.61/valo/05,734.99,yes,locked 2006.201.12:10:06.61/valo/06,814.99,yes,locked 2006.201.12:10:06.61/valo/07,864.99,yes,locked 2006.201.12:10:06.61/valo/08,884.99,yes,locked 2006.201.12:10:07.70/vb/01,04,usb,yes,30,28 2006.201.12:10:07.70/vb/02,05,usb,yes,28,28 2006.201.12:10:07.70/vb/03,04,usb,yes,29,32 2006.201.12:10:07.70/vb/04,05,usb,yes,29,28 2006.201.12:10:07.70/vb/05,04,usb,yes,26,28 2006.201.12:10:07.70/vb/06,04,usb,yes,30,27 2006.201.12:10:07.70/vb/07,04,usb,yes,30,30 2006.201.12:10:07.70/vb/08,04,usb,yes,28,31 2006.201.12:10:07.94/vblo/01,629.99,yes,locked 2006.201.12:10:07.94/vblo/02,634.99,yes,locked 2006.201.12:10:07.94/vblo/03,649.99,yes,locked 2006.201.12:10:07.94/vblo/04,679.99,yes,locked 2006.201.12:10:07.94/vblo/05,709.99,yes,locked 2006.201.12:10:07.94/vblo/06,719.99,yes,locked 2006.201.12:10:07.94/vblo/07,734.99,yes,locked 2006.201.12:10:07.94/vblo/08,744.99,yes,locked 2006.201.12:10:08.09/vabw/8 2006.201.12:10:08.24/vbbw/8 2006.201.12:10:08.42/xfe/off,on,15.0 2006.201.12:10:08.79/ifatt/23,28,28,28 2006.201.12:10:09.06/fmout-gps/S +4.59E-07 2006.201.12:10:09.11:!2006.201.12:10:45 2006.201.12:10:45.00:data_valid=off 2006.201.12:10:45.00:"et 2006.201.12:10:45.00:!+3s 2006.201.12:10:48.02:"tape 2006.201.12:10:48.02:postob 2006.201.12:10:48.20/cable/+6.4727E-03 2006.201.12:10:48.20/wx/21.23,1003.9,100 2006.201.12:10:48.27/fmout-gps/S +4.59E-07 2006.201.12:10:48.28:scan_name=201-1211,jd0607,40 2006.201.12:10:48.28:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.201.12:10:50.14#flagr#flagr/antenna,new-source 2006.201.12:10:50.14:checkk5 2006.201.12:10:50.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:10:50.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:10:51.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:10:51.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:10:52.03/chk_obsdata//k5ts1/T2011210??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:10:52.40/chk_obsdata//k5ts2/T2011210??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:10:52.76/chk_obsdata//k5ts3/T2011210??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:10:53.13/chk_obsdata//k5ts4/T2011210??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:10:53.83/k5log//k5ts1_log_newline 2006.201.12:10:54.53/k5log//k5ts2_log_newline 2006.201.12:10:55.21/k5log//k5ts3_log_newline 2006.201.12:10:55.90/k5log//k5ts4_log_newline 2006.201.12:10:55.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:10:55.92:setupk4=1 2006.201.12:10:55.92$setupk4/echo=on 2006.201.12:10:55.92$setupk4/pcalon 2006.201.12:10:55.92$pcalon/"no phase cal control is implemented here 2006.201.12:10:55.92$setupk4/"tpicd=stop 2006.201.12:10:55.92$setupk4/"rec=synch_on 2006.201.12:10:55.92$setupk4/"rec_mode=128 2006.201.12:10:55.92$setupk4/!* 2006.201.12:10:55.92$setupk4/recpk4 2006.201.12:10:55.92$recpk4/recpatch= 2006.201.12:10:55.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:10:55.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:10:55.93$setupk4/vck44 2006.201.12:10:55.93$vck44/valo=1,524.99 2006.201.12:10:55.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.12:10:55.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.12:10:55.93#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:55.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:55.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:55.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:55.93#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:10:55.93#ibcon#first serial, iclass 36, count 0 2006.201.12:10:55.93#ibcon#enter sib2, iclass 36, count 0 2006.201.12:10:55.93#ibcon#flushed, iclass 36, count 0 2006.201.12:10:55.93#ibcon#about to write, iclass 36, count 0 2006.201.12:10:55.93#ibcon#wrote, iclass 36, count 0 2006.201.12:10:55.93#ibcon#about to read 3, iclass 36, count 0 2006.201.12:10:55.97#ibcon#read 3, iclass 36, count 0 2006.201.12:10:55.97#ibcon#about to read 4, iclass 36, count 0 2006.201.12:10:55.97#ibcon#read 4, iclass 36, count 0 2006.201.12:10:55.97#ibcon#about to read 5, iclass 36, count 0 2006.201.12:10:55.97#ibcon#read 5, iclass 36, count 0 2006.201.12:10:55.97#ibcon#about to read 6, iclass 36, count 0 2006.201.12:10:55.97#ibcon#read 6, iclass 36, count 0 2006.201.12:10:55.97#ibcon#end of sib2, iclass 36, count 0 2006.201.12:10:55.97#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:10:55.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:10:55.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:10:55.97#ibcon#*before write, iclass 36, count 0 2006.201.12:10:55.97#ibcon#enter sib2, iclass 36, count 0 2006.201.12:10:55.97#ibcon#flushed, iclass 36, count 0 2006.201.12:10:55.97#ibcon#about to write, iclass 36, count 0 2006.201.12:10:55.97#ibcon#wrote, iclass 36, count 0 2006.201.12:10:55.97#ibcon#about to read 3, iclass 36, count 0 2006.201.12:10:56.02#ibcon#read 3, iclass 36, count 0 2006.201.12:10:56.02#ibcon#about to read 4, iclass 36, count 0 2006.201.12:10:56.02#ibcon#read 4, iclass 36, count 0 2006.201.12:10:56.02#ibcon#about to read 5, iclass 36, count 0 2006.201.12:10:56.02#ibcon#read 5, iclass 36, count 0 2006.201.12:10:56.02#ibcon#about to read 6, iclass 36, count 0 2006.201.12:10:56.02#ibcon#read 6, iclass 36, count 0 2006.201.12:10:56.02#ibcon#end of sib2, iclass 36, count 0 2006.201.12:10:56.02#ibcon#*after write, iclass 36, count 0 2006.201.12:10:56.02#ibcon#*before return 0, iclass 36, count 0 2006.201.12:10:56.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:56.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:56.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:10:56.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:10:56.02$vck44/va=1,8 2006.201.12:10:56.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.12:10:56.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.12:10:56.02#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:56.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:56.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:56.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:56.02#ibcon#enter wrdev, iclass 38, count 2 2006.201.12:10:56.02#ibcon#first serial, iclass 38, count 2 2006.201.12:10:56.02#ibcon#enter sib2, iclass 38, count 2 2006.201.12:10:56.02#ibcon#flushed, iclass 38, count 2 2006.201.12:10:56.02#ibcon#about to write, iclass 38, count 2 2006.201.12:10:56.02#ibcon#wrote, iclass 38, count 2 2006.201.12:10:56.02#ibcon#about to read 3, iclass 38, count 2 2006.201.12:10:56.04#ibcon#read 3, iclass 38, count 2 2006.201.12:10:56.04#ibcon#about to read 4, iclass 38, count 2 2006.201.12:10:56.04#ibcon#read 4, iclass 38, count 2 2006.201.12:10:56.04#ibcon#about to read 5, iclass 38, count 2 2006.201.12:10:56.04#ibcon#read 5, iclass 38, count 2 2006.201.12:10:56.04#ibcon#about to read 6, iclass 38, count 2 2006.201.12:10:56.04#ibcon#read 6, iclass 38, count 2 2006.201.12:10:56.04#ibcon#end of sib2, iclass 38, count 2 2006.201.12:10:56.04#ibcon#*mode == 0, iclass 38, count 2 2006.201.12:10:56.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.12:10:56.04#ibcon#[25=AT01-08\r\n] 2006.201.12:10:56.04#ibcon#*before write, iclass 38, count 2 2006.201.12:10:56.04#ibcon#enter sib2, iclass 38, count 2 2006.201.12:10:56.04#ibcon#flushed, iclass 38, count 2 2006.201.12:10:56.04#ibcon#about to write, iclass 38, count 2 2006.201.12:10:56.04#ibcon#wrote, iclass 38, count 2 2006.201.12:10:56.04#ibcon#about to read 3, iclass 38, count 2 2006.201.12:10:56.08#ibcon#read 3, iclass 38, count 2 2006.201.12:10:56.08#ibcon#about to read 4, iclass 38, count 2 2006.201.12:10:56.08#ibcon#read 4, iclass 38, count 2 2006.201.12:10:56.08#ibcon#about to read 5, iclass 38, count 2 2006.201.12:10:56.08#ibcon#read 5, iclass 38, count 2 2006.201.12:10:56.08#ibcon#about to read 6, iclass 38, count 2 2006.201.12:10:56.08#ibcon#read 6, iclass 38, count 2 2006.201.12:10:56.08#ibcon#end of sib2, iclass 38, count 2 2006.201.12:10:56.08#ibcon#*after write, iclass 38, count 2 2006.201.12:10:56.08#ibcon#*before return 0, iclass 38, count 2 2006.201.12:10:56.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:56.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:56.08#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.12:10:56.08#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:56.08#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:56.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:56.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:56.20#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:10:56.20#ibcon#first serial, iclass 38, count 0 2006.201.12:10:56.20#ibcon#enter sib2, iclass 38, count 0 2006.201.12:10:56.20#ibcon#flushed, iclass 38, count 0 2006.201.12:10:56.20#ibcon#about to write, iclass 38, count 0 2006.201.12:10:56.20#ibcon#wrote, iclass 38, count 0 2006.201.12:10:56.20#ibcon#about to read 3, iclass 38, count 0 2006.201.12:10:56.23#ibcon#read 3, iclass 38, count 0 2006.201.12:10:56.23#ibcon#about to read 4, iclass 38, count 0 2006.201.12:10:56.23#ibcon#read 4, iclass 38, count 0 2006.201.12:10:56.23#ibcon#about to read 5, iclass 38, count 0 2006.201.12:10:56.23#ibcon#read 5, iclass 38, count 0 2006.201.12:10:56.23#ibcon#about to read 6, iclass 38, count 0 2006.201.12:10:56.23#ibcon#read 6, iclass 38, count 0 2006.201.12:10:56.23#ibcon#end of sib2, iclass 38, count 0 2006.201.12:10:56.23#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:10:56.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:10:56.23#ibcon#[25=USB\r\n] 2006.201.12:10:56.23#ibcon#*before write, iclass 38, count 0 2006.201.12:10:56.23#ibcon#enter sib2, iclass 38, count 0 2006.201.12:10:56.23#ibcon#flushed, iclass 38, count 0 2006.201.12:10:56.23#ibcon#about to write, iclass 38, count 0 2006.201.12:10:56.23#ibcon#wrote, iclass 38, count 0 2006.201.12:10:56.23#ibcon#about to read 3, iclass 38, count 0 2006.201.12:10:56.26#ibcon#read 3, iclass 38, count 0 2006.201.12:10:56.26#ibcon#about to read 4, iclass 38, count 0 2006.201.12:10:56.26#ibcon#read 4, iclass 38, count 0 2006.201.12:10:56.26#ibcon#about to read 5, iclass 38, count 0 2006.201.12:10:56.26#ibcon#read 5, iclass 38, count 0 2006.201.12:10:56.26#ibcon#about to read 6, iclass 38, count 0 2006.201.12:10:56.26#ibcon#read 6, iclass 38, count 0 2006.201.12:10:56.26#ibcon#end of sib2, iclass 38, count 0 2006.201.12:10:56.26#ibcon#*after write, iclass 38, count 0 2006.201.12:10:56.26#ibcon#*before return 0, iclass 38, count 0 2006.201.12:10:56.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:56.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:56.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:10:56.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:10:56.26$vck44/valo=2,534.99 2006.201.12:10:56.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.12:10:56.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.12:10:56.26#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:56.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:56.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:56.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:56.26#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:10:56.26#ibcon#first serial, iclass 40, count 0 2006.201.12:10:56.26#ibcon#enter sib2, iclass 40, count 0 2006.201.12:10:56.26#ibcon#flushed, iclass 40, count 0 2006.201.12:10:56.26#ibcon#about to write, iclass 40, count 0 2006.201.12:10:56.26#ibcon#wrote, iclass 40, count 0 2006.201.12:10:56.26#ibcon#about to read 3, iclass 40, count 0 2006.201.12:10:56.28#ibcon#read 3, iclass 40, count 0 2006.201.12:10:56.28#ibcon#about to read 4, iclass 40, count 0 2006.201.12:10:56.28#ibcon#read 4, iclass 40, count 0 2006.201.12:10:56.28#ibcon#about to read 5, iclass 40, count 0 2006.201.12:10:56.28#ibcon#read 5, iclass 40, count 0 2006.201.12:10:56.28#ibcon#about to read 6, iclass 40, count 0 2006.201.12:10:56.28#ibcon#read 6, iclass 40, count 0 2006.201.12:10:56.28#ibcon#end of sib2, iclass 40, count 0 2006.201.12:10:56.28#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:10:56.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:10:56.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:10:56.28#ibcon#*before write, iclass 40, count 0 2006.201.12:10:56.28#ibcon#enter sib2, iclass 40, count 0 2006.201.12:10:56.28#ibcon#flushed, iclass 40, count 0 2006.201.12:10:56.28#ibcon#about to write, iclass 40, count 0 2006.201.12:10:56.28#ibcon#wrote, iclass 40, count 0 2006.201.12:10:56.28#ibcon#about to read 3, iclass 40, count 0 2006.201.12:10:56.32#ibcon#read 3, iclass 40, count 0 2006.201.12:10:56.32#ibcon#about to read 4, iclass 40, count 0 2006.201.12:10:56.32#ibcon#read 4, iclass 40, count 0 2006.201.12:10:56.32#ibcon#about to read 5, iclass 40, count 0 2006.201.12:10:56.32#ibcon#read 5, iclass 40, count 0 2006.201.12:10:56.32#ibcon#about to read 6, iclass 40, count 0 2006.201.12:10:56.32#ibcon#read 6, iclass 40, count 0 2006.201.12:10:56.32#ibcon#end of sib2, iclass 40, count 0 2006.201.12:10:56.32#ibcon#*after write, iclass 40, count 0 2006.201.12:10:56.32#ibcon#*before return 0, iclass 40, count 0 2006.201.12:10:56.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:56.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:56.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:10:56.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:10:56.32$vck44/va=2,7 2006.201.12:10:56.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.12:10:56.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.12:10:56.32#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:56.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:56.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:56.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:56.38#ibcon#enter wrdev, iclass 4, count 2 2006.201.12:10:56.38#ibcon#first serial, iclass 4, count 2 2006.201.12:10:56.38#ibcon#enter sib2, iclass 4, count 2 2006.201.12:10:56.38#ibcon#flushed, iclass 4, count 2 2006.201.12:10:56.38#ibcon#about to write, iclass 4, count 2 2006.201.12:10:56.38#ibcon#wrote, iclass 4, count 2 2006.201.12:10:56.38#ibcon#about to read 3, iclass 4, count 2 2006.201.12:10:56.40#ibcon#read 3, iclass 4, count 2 2006.201.12:10:56.40#ibcon#about to read 4, iclass 4, count 2 2006.201.12:10:56.40#ibcon#read 4, iclass 4, count 2 2006.201.12:10:56.40#ibcon#about to read 5, iclass 4, count 2 2006.201.12:10:56.40#ibcon#read 5, iclass 4, count 2 2006.201.12:10:56.40#ibcon#about to read 6, iclass 4, count 2 2006.201.12:10:56.40#ibcon#read 6, iclass 4, count 2 2006.201.12:10:56.40#ibcon#end of sib2, iclass 4, count 2 2006.201.12:10:56.40#ibcon#*mode == 0, iclass 4, count 2 2006.201.12:10:56.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.12:10:56.40#ibcon#[25=AT02-07\r\n] 2006.201.12:10:56.40#ibcon#*before write, iclass 4, count 2 2006.201.12:10:56.40#ibcon#enter sib2, iclass 4, count 2 2006.201.12:10:56.40#ibcon#flushed, iclass 4, count 2 2006.201.12:10:56.40#ibcon#about to write, iclass 4, count 2 2006.201.12:10:56.40#ibcon#wrote, iclass 4, count 2 2006.201.12:10:56.40#ibcon#about to read 3, iclass 4, count 2 2006.201.12:10:56.43#ibcon#read 3, iclass 4, count 2 2006.201.12:10:56.43#ibcon#about to read 4, iclass 4, count 2 2006.201.12:10:56.43#ibcon#read 4, iclass 4, count 2 2006.201.12:10:56.43#ibcon#about to read 5, iclass 4, count 2 2006.201.12:10:56.43#ibcon#read 5, iclass 4, count 2 2006.201.12:10:56.43#ibcon#about to read 6, iclass 4, count 2 2006.201.12:10:56.43#ibcon#read 6, iclass 4, count 2 2006.201.12:10:56.43#ibcon#end of sib2, iclass 4, count 2 2006.201.12:10:56.43#ibcon#*after write, iclass 4, count 2 2006.201.12:10:56.43#ibcon#*before return 0, iclass 4, count 2 2006.201.12:10:56.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:56.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:56.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.12:10:56.43#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:56.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:56.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:56.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:56.55#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:10:56.55#ibcon#first serial, iclass 4, count 0 2006.201.12:10:56.55#ibcon#enter sib2, iclass 4, count 0 2006.201.12:10:56.55#ibcon#flushed, iclass 4, count 0 2006.201.12:10:56.55#ibcon#about to write, iclass 4, count 0 2006.201.12:10:56.55#ibcon#wrote, iclass 4, count 0 2006.201.12:10:56.55#ibcon#about to read 3, iclass 4, count 0 2006.201.12:10:56.57#ibcon#read 3, iclass 4, count 0 2006.201.12:10:56.57#ibcon#about to read 4, iclass 4, count 0 2006.201.12:10:56.57#ibcon#read 4, iclass 4, count 0 2006.201.12:10:56.57#ibcon#about to read 5, iclass 4, count 0 2006.201.12:10:56.57#ibcon#read 5, iclass 4, count 0 2006.201.12:10:56.57#ibcon#about to read 6, iclass 4, count 0 2006.201.12:10:56.57#ibcon#read 6, iclass 4, count 0 2006.201.12:10:56.57#ibcon#end of sib2, iclass 4, count 0 2006.201.12:10:56.57#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:10:56.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:10:56.57#ibcon#[25=USB\r\n] 2006.201.12:10:56.57#ibcon#*before write, iclass 4, count 0 2006.201.12:10:56.57#ibcon#enter sib2, iclass 4, count 0 2006.201.12:10:56.57#ibcon#flushed, iclass 4, count 0 2006.201.12:10:56.57#ibcon#about to write, iclass 4, count 0 2006.201.12:10:56.57#ibcon#wrote, iclass 4, count 0 2006.201.12:10:56.57#ibcon#about to read 3, iclass 4, count 0 2006.201.12:10:56.60#ibcon#read 3, iclass 4, count 0 2006.201.12:10:56.60#ibcon#about to read 4, iclass 4, count 0 2006.201.12:10:56.60#ibcon#read 4, iclass 4, count 0 2006.201.12:10:56.60#ibcon#about to read 5, iclass 4, count 0 2006.201.12:10:56.60#ibcon#read 5, iclass 4, count 0 2006.201.12:10:56.60#ibcon#about to read 6, iclass 4, count 0 2006.201.12:10:56.60#ibcon#read 6, iclass 4, count 0 2006.201.12:10:56.60#ibcon#end of sib2, iclass 4, count 0 2006.201.12:10:56.60#ibcon#*after write, iclass 4, count 0 2006.201.12:10:56.60#ibcon#*before return 0, iclass 4, count 0 2006.201.12:10:56.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:56.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:56.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:10:56.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:10:56.60$vck44/valo=3,564.99 2006.201.12:10:56.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.12:10:56.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.12:10:56.60#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:56.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:56.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:56.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:56.60#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:10:56.60#ibcon#first serial, iclass 6, count 0 2006.201.12:10:56.60#ibcon#enter sib2, iclass 6, count 0 2006.201.12:10:56.60#ibcon#flushed, iclass 6, count 0 2006.201.12:10:56.60#ibcon#about to write, iclass 6, count 0 2006.201.12:10:56.60#ibcon#wrote, iclass 6, count 0 2006.201.12:10:56.60#ibcon#about to read 3, iclass 6, count 0 2006.201.12:10:56.62#ibcon#read 3, iclass 6, count 0 2006.201.12:10:56.62#ibcon#about to read 4, iclass 6, count 0 2006.201.12:10:56.62#ibcon#read 4, iclass 6, count 0 2006.201.12:10:56.62#ibcon#about to read 5, iclass 6, count 0 2006.201.12:10:56.62#ibcon#read 5, iclass 6, count 0 2006.201.12:10:56.62#ibcon#about to read 6, iclass 6, count 0 2006.201.12:10:56.62#ibcon#read 6, iclass 6, count 0 2006.201.12:10:56.62#ibcon#end of sib2, iclass 6, count 0 2006.201.12:10:56.62#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:10:56.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:10:56.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:10:56.62#ibcon#*before write, iclass 6, count 0 2006.201.12:10:56.62#ibcon#enter sib2, iclass 6, count 0 2006.201.12:10:56.62#ibcon#flushed, iclass 6, count 0 2006.201.12:10:56.62#ibcon#about to write, iclass 6, count 0 2006.201.12:10:56.62#ibcon#wrote, iclass 6, count 0 2006.201.12:10:56.62#ibcon#about to read 3, iclass 6, count 0 2006.201.12:10:56.66#ibcon#read 3, iclass 6, count 0 2006.201.12:10:56.66#ibcon#about to read 4, iclass 6, count 0 2006.201.12:10:56.66#ibcon#read 4, iclass 6, count 0 2006.201.12:10:56.66#ibcon#about to read 5, iclass 6, count 0 2006.201.12:10:56.66#ibcon#read 5, iclass 6, count 0 2006.201.12:10:56.66#ibcon#about to read 6, iclass 6, count 0 2006.201.12:10:56.66#ibcon#read 6, iclass 6, count 0 2006.201.12:10:56.66#ibcon#end of sib2, iclass 6, count 0 2006.201.12:10:56.66#ibcon#*after write, iclass 6, count 0 2006.201.12:10:56.66#ibcon#*before return 0, iclass 6, count 0 2006.201.12:10:56.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:56.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:56.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:10:56.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:10:56.66$vck44/va=3,8 2006.201.12:10:56.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.12:10:56.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.12:10:56.66#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:56.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:10:56.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:10:56.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:10:56.72#ibcon#enter wrdev, iclass 10, count 2 2006.201.12:10:56.72#ibcon#first serial, iclass 10, count 2 2006.201.12:10:56.72#ibcon#enter sib2, iclass 10, count 2 2006.201.12:10:56.72#ibcon#flushed, iclass 10, count 2 2006.201.12:10:56.72#ibcon#about to write, iclass 10, count 2 2006.201.12:10:56.72#ibcon#wrote, iclass 10, count 2 2006.201.12:10:56.72#ibcon#about to read 3, iclass 10, count 2 2006.201.12:10:56.74#ibcon#read 3, iclass 10, count 2 2006.201.12:10:56.74#ibcon#about to read 4, iclass 10, count 2 2006.201.12:10:56.74#ibcon#read 4, iclass 10, count 2 2006.201.12:10:56.74#ibcon#about to read 5, iclass 10, count 2 2006.201.12:10:56.74#ibcon#read 5, iclass 10, count 2 2006.201.12:10:56.74#ibcon#about to read 6, iclass 10, count 2 2006.201.12:10:56.74#ibcon#read 6, iclass 10, count 2 2006.201.12:10:56.74#ibcon#end of sib2, iclass 10, count 2 2006.201.12:10:56.74#ibcon#*mode == 0, iclass 10, count 2 2006.201.12:10:56.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.12:10:56.74#ibcon#[25=AT03-08\r\n] 2006.201.12:10:56.74#ibcon#*before write, iclass 10, count 2 2006.201.12:10:56.74#ibcon#enter sib2, iclass 10, count 2 2006.201.12:10:56.74#ibcon#flushed, iclass 10, count 2 2006.201.12:10:56.74#ibcon#about to write, iclass 10, count 2 2006.201.12:10:56.74#ibcon#wrote, iclass 10, count 2 2006.201.12:10:56.74#ibcon#about to read 3, iclass 10, count 2 2006.201.12:10:56.77#ibcon#read 3, iclass 10, count 2 2006.201.12:10:56.77#ibcon#about to read 4, iclass 10, count 2 2006.201.12:10:56.77#ibcon#read 4, iclass 10, count 2 2006.201.12:10:56.77#ibcon#about to read 5, iclass 10, count 2 2006.201.12:10:56.77#ibcon#read 5, iclass 10, count 2 2006.201.12:10:56.77#ibcon#about to read 6, iclass 10, count 2 2006.201.12:10:56.77#ibcon#read 6, iclass 10, count 2 2006.201.12:10:56.77#ibcon#end of sib2, iclass 10, count 2 2006.201.12:10:56.77#ibcon#*after write, iclass 10, count 2 2006.201.12:10:56.77#ibcon#*before return 0, iclass 10, count 2 2006.201.12:10:56.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:10:56.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:10:56.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.12:10:56.77#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:56.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:10:56.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:10:56.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:10:56.89#ibcon#enter wrdev, iclass 10, count 0 2006.201.12:10:56.89#ibcon#first serial, iclass 10, count 0 2006.201.12:10:56.89#ibcon#enter sib2, iclass 10, count 0 2006.201.12:10:56.89#ibcon#flushed, iclass 10, count 0 2006.201.12:10:56.89#ibcon#about to write, iclass 10, count 0 2006.201.12:10:56.89#ibcon#wrote, iclass 10, count 0 2006.201.12:10:56.89#ibcon#about to read 3, iclass 10, count 0 2006.201.12:10:56.91#ibcon#read 3, iclass 10, count 0 2006.201.12:10:56.91#ibcon#about to read 4, iclass 10, count 0 2006.201.12:10:56.91#ibcon#read 4, iclass 10, count 0 2006.201.12:10:56.91#ibcon#about to read 5, iclass 10, count 0 2006.201.12:10:56.91#ibcon#read 5, iclass 10, count 0 2006.201.12:10:56.91#ibcon#about to read 6, iclass 10, count 0 2006.201.12:10:56.91#ibcon#read 6, iclass 10, count 0 2006.201.12:10:56.91#ibcon#end of sib2, iclass 10, count 0 2006.201.12:10:56.91#ibcon#*mode == 0, iclass 10, count 0 2006.201.12:10:56.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.12:10:56.91#ibcon#[25=USB\r\n] 2006.201.12:10:56.91#ibcon#*before write, iclass 10, count 0 2006.201.12:10:56.91#ibcon#enter sib2, iclass 10, count 0 2006.201.12:10:56.91#ibcon#flushed, iclass 10, count 0 2006.201.12:10:56.91#ibcon#about to write, iclass 10, count 0 2006.201.12:10:56.91#ibcon#wrote, iclass 10, count 0 2006.201.12:10:56.91#ibcon#about to read 3, iclass 10, count 0 2006.201.12:10:56.94#ibcon#read 3, iclass 10, count 0 2006.201.12:10:56.94#ibcon#about to read 4, iclass 10, count 0 2006.201.12:10:56.94#ibcon#read 4, iclass 10, count 0 2006.201.12:10:56.94#ibcon#about to read 5, iclass 10, count 0 2006.201.12:10:56.94#ibcon#read 5, iclass 10, count 0 2006.201.12:10:56.94#ibcon#about to read 6, iclass 10, count 0 2006.201.12:10:56.94#ibcon#read 6, iclass 10, count 0 2006.201.12:10:56.94#ibcon#end of sib2, iclass 10, count 0 2006.201.12:10:56.94#ibcon#*after write, iclass 10, count 0 2006.201.12:10:56.94#ibcon#*before return 0, iclass 10, count 0 2006.201.12:10:56.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:10:56.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:10:56.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.12:10:56.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.12:10:56.94$vck44/valo=4,624.99 2006.201.12:10:56.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.12:10:56.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.12:10:56.94#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:56.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:10:56.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:10:56.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:10:56.94#ibcon#enter wrdev, iclass 12, count 0 2006.201.12:10:56.94#ibcon#first serial, iclass 12, count 0 2006.201.12:10:56.94#ibcon#enter sib2, iclass 12, count 0 2006.201.12:10:56.94#ibcon#flushed, iclass 12, count 0 2006.201.12:10:56.94#ibcon#about to write, iclass 12, count 0 2006.201.12:10:56.94#ibcon#wrote, iclass 12, count 0 2006.201.12:10:56.94#ibcon#about to read 3, iclass 12, count 0 2006.201.12:10:56.96#ibcon#read 3, iclass 12, count 0 2006.201.12:10:56.96#ibcon#about to read 4, iclass 12, count 0 2006.201.12:10:56.96#ibcon#read 4, iclass 12, count 0 2006.201.12:10:56.96#ibcon#about to read 5, iclass 12, count 0 2006.201.12:10:56.96#ibcon#read 5, iclass 12, count 0 2006.201.12:10:56.96#ibcon#about to read 6, iclass 12, count 0 2006.201.12:10:56.96#ibcon#read 6, iclass 12, count 0 2006.201.12:10:56.96#ibcon#end of sib2, iclass 12, count 0 2006.201.12:10:56.96#ibcon#*mode == 0, iclass 12, count 0 2006.201.12:10:56.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.12:10:56.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:10:56.96#ibcon#*before write, iclass 12, count 0 2006.201.12:10:56.96#ibcon#enter sib2, iclass 12, count 0 2006.201.12:10:56.96#ibcon#flushed, iclass 12, count 0 2006.201.12:10:56.96#ibcon#about to write, iclass 12, count 0 2006.201.12:10:56.96#ibcon#wrote, iclass 12, count 0 2006.201.12:10:56.96#ibcon#about to read 3, iclass 12, count 0 2006.201.12:10:57.01#ibcon#read 3, iclass 12, count 0 2006.201.12:10:57.01#ibcon#about to read 4, iclass 12, count 0 2006.201.12:10:57.01#ibcon#read 4, iclass 12, count 0 2006.201.12:10:57.01#ibcon#about to read 5, iclass 12, count 0 2006.201.12:10:57.01#ibcon#read 5, iclass 12, count 0 2006.201.12:10:57.01#ibcon#about to read 6, iclass 12, count 0 2006.201.12:10:57.01#ibcon#read 6, iclass 12, count 0 2006.201.12:10:57.01#ibcon#end of sib2, iclass 12, count 0 2006.201.12:10:57.01#ibcon#*after write, iclass 12, count 0 2006.201.12:10:57.01#ibcon#*before return 0, iclass 12, count 0 2006.201.12:10:57.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:10:57.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:10:57.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.12:10:57.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.12:10:57.01$vck44/va=4,7 2006.201.12:10:57.01#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.12:10:57.01#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.12:10:57.01#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:57.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:10:57.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:10:57.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:10:57.06#ibcon#enter wrdev, iclass 14, count 2 2006.201.12:10:57.06#ibcon#first serial, iclass 14, count 2 2006.201.12:10:57.06#ibcon#enter sib2, iclass 14, count 2 2006.201.12:10:57.06#ibcon#flushed, iclass 14, count 2 2006.201.12:10:57.06#ibcon#about to write, iclass 14, count 2 2006.201.12:10:57.06#ibcon#wrote, iclass 14, count 2 2006.201.12:10:57.06#ibcon#about to read 3, iclass 14, count 2 2006.201.12:10:57.08#ibcon#read 3, iclass 14, count 2 2006.201.12:10:57.08#ibcon#about to read 4, iclass 14, count 2 2006.201.12:10:57.08#ibcon#read 4, iclass 14, count 2 2006.201.12:10:57.08#ibcon#about to read 5, iclass 14, count 2 2006.201.12:10:57.08#ibcon#read 5, iclass 14, count 2 2006.201.12:10:57.08#ibcon#about to read 6, iclass 14, count 2 2006.201.12:10:57.08#ibcon#read 6, iclass 14, count 2 2006.201.12:10:57.08#ibcon#end of sib2, iclass 14, count 2 2006.201.12:10:57.08#ibcon#*mode == 0, iclass 14, count 2 2006.201.12:10:57.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.12:10:57.08#ibcon#[25=AT04-07\r\n] 2006.201.12:10:57.08#ibcon#*before write, iclass 14, count 2 2006.201.12:10:57.08#ibcon#enter sib2, iclass 14, count 2 2006.201.12:10:57.08#ibcon#flushed, iclass 14, count 2 2006.201.12:10:57.08#ibcon#about to write, iclass 14, count 2 2006.201.12:10:57.08#ibcon#wrote, iclass 14, count 2 2006.201.12:10:57.08#ibcon#about to read 3, iclass 14, count 2 2006.201.12:10:57.11#ibcon#read 3, iclass 14, count 2 2006.201.12:10:57.11#ibcon#about to read 4, iclass 14, count 2 2006.201.12:10:57.11#ibcon#read 4, iclass 14, count 2 2006.201.12:10:57.11#ibcon#about to read 5, iclass 14, count 2 2006.201.12:10:57.11#ibcon#read 5, iclass 14, count 2 2006.201.12:10:57.11#ibcon#about to read 6, iclass 14, count 2 2006.201.12:10:57.11#ibcon#read 6, iclass 14, count 2 2006.201.12:10:57.11#ibcon#end of sib2, iclass 14, count 2 2006.201.12:10:57.11#ibcon#*after write, iclass 14, count 2 2006.201.12:10:57.11#ibcon#*before return 0, iclass 14, count 2 2006.201.12:10:57.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:10:57.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:10:57.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.12:10:57.11#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:57.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:10:57.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:10:57.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:10:57.23#ibcon#enter wrdev, iclass 14, count 0 2006.201.12:10:57.23#ibcon#first serial, iclass 14, count 0 2006.201.12:10:57.23#ibcon#enter sib2, iclass 14, count 0 2006.201.12:10:57.23#ibcon#flushed, iclass 14, count 0 2006.201.12:10:57.23#ibcon#about to write, iclass 14, count 0 2006.201.12:10:57.23#ibcon#wrote, iclass 14, count 0 2006.201.12:10:57.23#ibcon#about to read 3, iclass 14, count 0 2006.201.12:10:57.25#ibcon#read 3, iclass 14, count 0 2006.201.12:10:57.25#ibcon#about to read 4, iclass 14, count 0 2006.201.12:10:57.25#ibcon#read 4, iclass 14, count 0 2006.201.12:10:57.25#ibcon#about to read 5, iclass 14, count 0 2006.201.12:10:57.25#ibcon#read 5, iclass 14, count 0 2006.201.12:10:57.25#ibcon#about to read 6, iclass 14, count 0 2006.201.12:10:57.25#ibcon#read 6, iclass 14, count 0 2006.201.12:10:57.25#ibcon#end of sib2, iclass 14, count 0 2006.201.12:10:57.25#ibcon#*mode == 0, iclass 14, count 0 2006.201.12:10:57.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.12:10:57.25#ibcon#[25=USB\r\n] 2006.201.12:10:57.25#ibcon#*before write, iclass 14, count 0 2006.201.12:10:57.25#ibcon#enter sib2, iclass 14, count 0 2006.201.12:10:57.25#ibcon#flushed, iclass 14, count 0 2006.201.12:10:57.25#ibcon#about to write, iclass 14, count 0 2006.201.12:10:57.25#ibcon#wrote, iclass 14, count 0 2006.201.12:10:57.25#ibcon#about to read 3, iclass 14, count 0 2006.201.12:10:57.28#ibcon#read 3, iclass 14, count 0 2006.201.12:10:57.28#ibcon#about to read 4, iclass 14, count 0 2006.201.12:10:57.28#ibcon#read 4, iclass 14, count 0 2006.201.12:10:57.28#ibcon#about to read 5, iclass 14, count 0 2006.201.12:10:57.28#ibcon#read 5, iclass 14, count 0 2006.201.12:10:57.28#ibcon#about to read 6, iclass 14, count 0 2006.201.12:10:57.28#ibcon#read 6, iclass 14, count 0 2006.201.12:10:57.28#ibcon#end of sib2, iclass 14, count 0 2006.201.12:10:57.28#ibcon#*after write, iclass 14, count 0 2006.201.12:10:57.28#ibcon#*before return 0, iclass 14, count 0 2006.201.12:10:57.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:10:57.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:10:57.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.12:10:57.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.12:10:57.28$vck44/valo=5,734.99 2006.201.12:10:57.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.12:10:57.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.12:10:57.28#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:57.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:10:57.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:10:57.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:10:57.28#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:10:57.28#ibcon#first serial, iclass 16, count 0 2006.201.12:10:57.28#ibcon#enter sib2, iclass 16, count 0 2006.201.12:10:57.28#ibcon#flushed, iclass 16, count 0 2006.201.12:10:57.28#ibcon#about to write, iclass 16, count 0 2006.201.12:10:57.28#ibcon#wrote, iclass 16, count 0 2006.201.12:10:57.28#ibcon#about to read 3, iclass 16, count 0 2006.201.12:10:57.30#ibcon#read 3, iclass 16, count 0 2006.201.12:10:57.30#ibcon#about to read 4, iclass 16, count 0 2006.201.12:10:57.30#ibcon#read 4, iclass 16, count 0 2006.201.12:10:57.30#ibcon#about to read 5, iclass 16, count 0 2006.201.12:10:57.30#ibcon#read 5, iclass 16, count 0 2006.201.12:10:57.30#ibcon#about to read 6, iclass 16, count 0 2006.201.12:10:57.30#ibcon#read 6, iclass 16, count 0 2006.201.12:10:57.30#ibcon#end of sib2, iclass 16, count 0 2006.201.12:10:57.30#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:10:57.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:10:57.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:10:57.30#ibcon#*before write, iclass 16, count 0 2006.201.12:10:57.30#ibcon#enter sib2, iclass 16, count 0 2006.201.12:10:57.30#ibcon#flushed, iclass 16, count 0 2006.201.12:10:57.30#ibcon#about to write, iclass 16, count 0 2006.201.12:10:57.30#ibcon#wrote, iclass 16, count 0 2006.201.12:10:57.30#ibcon#about to read 3, iclass 16, count 0 2006.201.12:10:57.34#ibcon#read 3, iclass 16, count 0 2006.201.12:10:57.34#ibcon#about to read 4, iclass 16, count 0 2006.201.12:10:57.34#ibcon#read 4, iclass 16, count 0 2006.201.12:10:57.34#ibcon#about to read 5, iclass 16, count 0 2006.201.12:10:57.34#ibcon#read 5, iclass 16, count 0 2006.201.12:10:57.34#ibcon#about to read 6, iclass 16, count 0 2006.201.12:10:57.34#ibcon#read 6, iclass 16, count 0 2006.201.12:10:57.34#ibcon#end of sib2, iclass 16, count 0 2006.201.12:10:57.34#ibcon#*after write, iclass 16, count 0 2006.201.12:10:57.34#ibcon#*before return 0, iclass 16, count 0 2006.201.12:10:57.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:10:57.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:10:57.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:10:57.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:10:57.34$vck44/va=5,4 2006.201.12:10:57.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.12:10:57.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.12:10:57.34#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:57.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:10:57.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:10:57.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:10:57.40#ibcon#enter wrdev, iclass 18, count 2 2006.201.12:10:57.40#ibcon#first serial, iclass 18, count 2 2006.201.12:10:57.40#ibcon#enter sib2, iclass 18, count 2 2006.201.12:10:57.40#ibcon#flushed, iclass 18, count 2 2006.201.12:10:57.40#ibcon#about to write, iclass 18, count 2 2006.201.12:10:57.40#ibcon#wrote, iclass 18, count 2 2006.201.12:10:57.40#ibcon#about to read 3, iclass 18, count 2 2006.201.12:10:57.42#ibcon#read 3, iclass 18, count 2 2006.201.12:10:57.42#ibcon#about to read 4, iclass 18, count 2 2006.201.12:10:57.42#ibcon#read 4, iclass 18, count 2 2006.201.12:10:57.42#ibcon#about to read 5, iclass 18, count 2 2006.201.12:10:57.42#ibcon#read 5, iclass 18, count 2 2006.201.12:10:57.42#ibcon#about to read 6, iclass 18, count 2 2006.201.12:10:57.42#ibcon#read 6, iclass 18, count 2 2006.201.12:10:57.42#ibcon#end of sib2, iclass 18, count 2 2006.201.12:10:57.42#ibcon#*mode == 0, iclass 18, count 2 2006.201.12:10:57.42#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.12:10:57.42#ibcon#[25=AT05-04\r\n] 2006.201.12:10:57.42#ibcon#*before write, iclass 18, count 2 2006.201.12:10:57.42#ibcon#enter sib2, iclass 18, count 2 2006.201.12:10:57.42#ibcon#flushed, iclass 18, count 2 2006.201.12:10:57.42#ibcon#about to write, iclass 18, count 2 2006.201.12:10:57.42#ibcon#wrote, iclass 18, count 2 2006.201.12:10:57.42#ibcon#about to read 3, iclass 18, count 2 2006.201.12:10:57.45#ibcon#read 3, iclass 18, count 2 2006.201.12:10:57.45#ibcon#about to read 4, iclass 18, count 2 2006.201.12:10:57.45#ibcon#read 4, iclass 18, count 2 2006.201.12:10:57.45#ibcon#about to read 5, iclass 18, count 2 2006.201.12:10:57.45#ibcon#read 5, iclass 18, count 2 2006.201.12:10:57.45#ibcon#about to read 6, iclass 18, count 2 2006.201.12:10:57.45#ibcon#read 6, iclass 18, count 2 2006.201.12:10:57.45#ibcon#end of sib2, iclass 18, count 2 2006.201.12:10:57.45#ibcon#*after write, iclass 18, count 2 2006.201.12:10:57.45#ibcon#*before return 0, iclass 18, count 2 2006.201.12:10:57.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:10:57.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:10:57.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.12:10:57.45#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:57.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:10:57.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:10:57.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:10:57.57#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:10:57.57#ibcon#first serial, iclass 18, count 0 2006.201.12:10:57.57#ibcon#enter sib2, iclass 18, count 0 2006.201.12:10:57.57#ibcon#flushed, iclass 18, count 0 2006.201.12:10:57.57#ibcon#about to write, iclass 18, count 0 2006.201.12:10:57.57#ibcon#wrote, iclass 18, count 0 2006.201.12:10:57.57#ibcon#about to read 3, iclass 18, count 0 2006.201.12:10:57.59#ibcon#read 3, iclass 18, count 0 2006.201.12:10:57.59#ibcon#about to read 4, iclass 18, count 0 2006.201.12:10:57.59#ibcon#read 4, iclass 18, count 0 2006.201.12:10:57.59#ibcon#about to read 5, iclass 18, count 0 2006.201.12:10:57.59#ibcon#read 5, iclass 18, count 0 2006.201.12:10:57.59#ibcon#about to read 6, iclass 18, count 0 2006.201.12:10:57.59#ibcon#read 6, iclass 18, count 0 2006.201.12:10:57.59#ibcon#end of sib2, iclass 18, count 0 2006.201.12:10:57.59#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:10:57.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:10:57.59#ibcon#[25=USB\r\n] 2006.201.12:10:57.59#ibcon#*before write, iclass 18, count 0 2006.201.12:10:57.59#ibcon#enter sib2, iclass 18, count 0 2006.201.12:10:57.59#ibcon#flushed, iclass 18, count 0 2006.201.12:10:57.59#ibcon#about to write, iclass 18, count 0 2006.201.12:10:57.59#ibcon#wrote, iclass 18, count 0 2006.201.12:10:57.59#ibcon#about to read 3, iclass 18, count 0 2006.201.12:10:57.62#ibcon#read 3, iclass 18, count 0 2006.201.12:10:57.62#ibcon#about to read 4, iclass 18, count 0 2006.201.12:10:57.62#ibcon#read 4, iclass 18, count 0 2006.201.12:10:57.62#ibcon#about to read 5, iclass 18, count 0 2006.201.12:10:57.62#ibcon#read 5, iclass 18, count 0 2006.201.12:10:57.62#ibcon#about to read 6, iclass 18, count 0 2006.201.12:10:57.62#ibcon#read 6, iclass 18, count 0 2006.201.12:10:57.62#ibcon#end of sib2, iclass 18, count 0 2006.201.12:10:57.62#ibcon#*after write, iclass 18, count 0 2006.201.12:10:57.62#ibcon#*before return 0, iclass 18, count 0 2006.201.12:10:57.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:10:57.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:10:57.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:10:57.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:10:57.62$vck44/valo=6,814.99 2006.201.12:10:57.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.12:10:57.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.12:10:57.62#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:57.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:10:57.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:10:57.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:10:57.62#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:10:57.62#ibcon#first serial, iclass 20, count 0 2006.201.12:10:57.62#ibcon#enter sib2, iclass 20, count 0 2006.201.12:10:57.62#ibcon#flushed, iclass 20, count 0 2006.201.12:10:57.62#ibcon#about to write, iclass 20, count 0 2006.201.12:10:57.62#ibcon#wrote, iclass 20, count 0 2006.201.12:10:57.62#ibcon#about to read 3, iclass 20, count 0 2006.201.12:10:57.64#ibcon#read 3, iclass 20, count 0 2006.201.12:10:57.64#ibcon#about to read 4, iclass 20, count 0 2006.201.12:10:57.64#ibcon#read 4, iclass 20, count 0 2006.201.12:10:57.64#ibcon#about to read 5, iclass 20, count 0 2006.201.12:10:57.64#ibcon#read 5, iclass 20, count 0 2006.201.12:10:57.64#ibcon#about to read 6, iclass 20, count 0 2006.201.12:10:57.64#ibcon#read 6, iclass 20, count 0 2006.201.12:10:57.64#ibcon#end of sib2, iclass 20, count 0 2006.201.12:10:57.64#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:10:57.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:10:57.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:10:57.64#ibcon#*before write, iclass 20, count 0 2006.201.12:10:57.64#ibcon#enter sib2, iclass 20, count 0 2006.201.12:10:57.64#ibcon#flushed, iclass 20, count 0 2006.201.12:10:57.64#ibcon#about to write, iclass 20, count 0 2006.201.12:10:57.64#ibcon#wrote, iclass 20, count 0 2006.201.12:10:57.64#ibcon#about to read 3, iclass 20, count 0 2006.201.12:10:57.69#ibcon#read 3, iclass 20, count 0 2006.201.12:10:57.69#ibcon#about to read 4, iclass 20, count 0 2006.201.12:10:57.69#ibcon#read 4, iclass 20, count 0 2006.201.12:10:57.69#ibcon#about to read 5, iclass 20, count 0 2006.201.12:10:57.69#ibcon#read 5, iclass 20, count 0 2006.201.12:10:57.69#ibcon#about to read 6, iclass 20, count 0 2006.201.12:10:57.69#ibcon#read 6, iclass 20, count 0 2006.201.12:10:57.69#ibcon#end of sib2, iclass 20, count 0 2006.201.12:10:57.69#ibcon#*after write, iclass 20, count 0 2006.201.12:10:57.69#ibcon#*before return 0, iclass 20, count 0 2006.201.12:10:57.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:10:57.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:10:57.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:10:57.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:10:57.69$vck44/va=6,5 2006.201.12:10:57.69#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.12:10:57.69#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.12:10:57.69#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:57.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:10:57.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:10:57.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:10:57.74#ibcon#enter wrdev, iclass 22, count 2 2006.201.12:10:57.74#ibcon#first serial, iclass 22, count 2 2006.201.12:10:57.74#ibcon#enter sib2, iclass 22, count 2 2006.201.12:10:57.74#ibcon#flushed, iclass 22, count 2 2006.201.12:10:57.74#ibcon#about to write, iclass 22, count 2 2006.201.12:10:57.74#ibcon#wrote, iclass 22, count 2 2006.201.12:10:57.74#ibcon#about to read 3, iclass 22, count 2 2006.201.12:10:57.76#ibcon#read 3, iclass 22, count 2 2006.201.12:10:57.76#ibcon#about to read 4, iclass 22, count 2 2006.201.12:10:57.76#ibcon#read 4, iclass 22, count 2 2006.201.12:10:57.76#ibcon#about to read 5, iclass 22, count 2 2006.201.12:10:57.76#ibcon#read 5, iclass 22, count 2 2006.201.12:10:57.76#ibcon#about to read 6, iclass 22, count 2 2006.201.12:10:57.76#ibcon#read 6, iclass 22, count 2 2006.201.12:10:57.76#ibcon#end of sib2, iclass 22, count 2 2006.201.12:10:57.76#ibcon#*mode == 0, iclass 22, count 2 2006.201.12:10:57.76#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.12:10:57.76#ibcon#[25=AT06-05\r\n] 2006.201.12:10:57.76#ibcon#*before write, iclass 22, count 2 2006.201.12:10:57.76#ibcon#enter sib2, iclass 22, count 2 2006.201.12:10:57.76#ibcon#flushed, iclass 22, count 2 2006.201.12:10:57.76#ibcon#about to write, iclass 22, count 2 2006.201.12:10:57.76#ibcon#wrote, iclass 22, count 2 2006.201.12:10:57.76#ibcon#about to read 3, iclass 22, count 2 2006.201.12:10:57.79#ibcon#read 3, iclass 22, count 2 2006.201.12:10:57.79#ibcon#about to read 4, iclass 22, count 2 2006.201.12:10:57.79#ibcon#read 4, iclass 22, count 2 2006.201.12:10:57.79#ibcon#about to read 5, iclass 22, count 2 2006.201.12:10:57.79#ibcon#read 5, iclass 22, count 2 2006.201.12:10:57.79#ibcon#about to read 6, iclass 22, count 2 2006.201.12:10:57.79#ibcon#read 6, iclass 22, count 2 2006.201.12:10:57.79#ibcon#end of sib2, iclass 22, count 2 2006.201.12:10:57.79#ibcon#*after write, iclass 22, count 2 2006.201.12:10:57.79#ibcon#*before return 0, iclass 22, count 2 2006.201.12:10:57.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:10:57.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:10:57.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.12:10:57.79#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:57.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:10:57.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:10:57.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:10:57.91#ibcon#enter wrdev, iclass 22, count 0 2006.201.12:10:57.91#ibcon#first serial, iclass 22, count 0 2006.201.12:10:57.91#ibcon#enter sib2, iclass 22, count 0 2006.201.12:10:57.91#ibcon#flushed, iclass 22, count 0 2006.201.12:10:57.91#ibcon#about to write, iclass 22, count 0 2006.201.12:10:57.91#ibcon#wrote, iclass 22, count 0 2006.201.12:10:57.91#ibcon#about to read 3, iclass 22, count 0 2006.201.12:10:57.93#ibcon#read 3, iclass 22, count 0 2006.201.12:10:57.93#ibcon#about to read 4, iclass 22, count 0 2006.201.12:10:57.93#ibcon#read 4, iclass 22, count 0 2006.201.12:10:57.93#ibcon#about to read 5, iclass 22, count 0 2006.201.12:10:57.93#ibcon#read 5, iclass 22, count 0 2006.201.12:10:57.93#ibcon#about to read 6, iclass 22, count 0 2006.201.12:10:57.93#ibcon#read 6, iclass 22, count 0 2006.201.12:10:57.93#ibcon#end of sib2, iclass 22, count 0 2006.201.12:10:57.93#ibcon#*mode == 0, iclass 22, count 0 2006.201.12:10:57.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.12:10:57.93#ibcon#[25=USB\r\n] 2006.201.12:10:57.93#ibcon#*before write, iclass 22, count 0 2006.201.12:10:57.93#ibcon#enter sib2, iclass 22, count 0 2006.201.12:10:57.93#ibcon#flushed, iclass 22, count 0 2006.201.12:10:57.93#ibcon#about to write, iclass 22, count 0 2006.201.12:10:57.93#ibcon#wrote, iclass 22, count 0 2006.201.12:10:57.93#ibcon#about to read 3, iclass 22, count 0 2006.201.12:10:57.96#ibcon#read 3, iclass 22, count 0 2006.201.12:10:57.96#ibcon#about to read 4, iclass 22, count 0 2006.201.12:10:57.96#ibcon#read 4, iclass 22, count 0 2006.201.12:10:57.96#ibcon#about to read 5, iclass 22, count 0 2006.201.12:10:57.96#ibcon#read 5, iclass 22, count 0 2006.201.12:10:57.96#ibcon#about to read 6, iclass 22, count 0 2006.201.12:10:57.96#ibcon#read 6, iclass 22, count 0 2006.201.12:10:57.96#ibcon#end of sib2, iclass 22, count 0 2006.201.12:10:57.96#ibcon#*after write, iclass 22, count 0 2006.201.12:10:57.96#ibcon#*before return 0, iclass 22, count 0 2006.201.12:10:57.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:10:57.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:10:57.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.12:10:57.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.12:10:57.96$vck44/valo=7,864.99 2006.201.12:10:57.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.12:10:57.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.12:10:57.96#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:57.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:10:57.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:10:57.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:10:57.96#ibcon#enter wrdev, iclass 24, count 0 2006.201.12:10:57.96#ibcon#first serial, iclass 24, count 0 2006.201.12:10:57.96#ibcon#enter sib2, iclass 24, count 0 2006.201.12:10:57.96#ibcon#flushed, iclass 24, count 0 2006.201.12:10:57.96#ibcon#about to write, iclass 24, count 0 2006.201.12:10:57.96#ibcon#wrote, iclass 24, count 0 2006.201.12:10:57.96#ibcon#about to read 3, iclass 24, count 0 2006.201.12:10:57.98#ibcon#read 3, iclass 24, count 0 2006.201.12:10:57.98#ibcon#about to read 4, iclass 24, count 0 2006.201.12:10:57.98#ibcon#read 4, iclass 24, count 0 2006.201.12:10:57.98#ibcon#about to read 5, iclass 24, count 0 2006.201.12:10:57.98#ibcon#read 5, iclass 24, count 0 2006.201.12:10:57.98#ibcon#about to read 6, iclass 24, count 0 2006.201.12:10:57.98#ibcon#read 6, iclass 24, count 0 2006.201.12:10:57.98#ibcon#end of sib2, iclass 24, count 0 2006.201.12:10:57.98#ibcon#*mode == 0, iclass 24, count 0 2006.201.12:10:57.98#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.12:10:57.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:10:57.98#ibcon#*before write, iclass 24, count 0 2006.201.12:10:57.98#ibcon#enter sib2, iclass 24, count 0 2006.201.12:10:57.98#ibcon#flushed, iclass 24, count 0 2006.201.12:10:57.98#ibcon#about to write, iclass 24, count 0 2006.201.12:10:57.98#ibcon#wrote, iclass 24, count 0 2006.201.12:10:57.98#ibcon#about to read 3, iclass 24, count 0 2006.201.12:10:58.02#ibcon#read 3, iclass 24, count 0 2006.201.12:10:58.02#ibcon#about to read 4, iclass 24, count 0 2006.201.12:10:58.02#ibcon#read 4, iclass 24, count 0 2006.201.12:10:58.02#ibcon#about to read 5, iclass 24, count 0 2006.201.12:10:58.02#ibcon#read 5, iclass 24, count 0 2006.201.12:10:58.02#ibcon#about to read 6, iclass 24, count 0 2006.201.12:10:58.02#ibcon#read 6, iclass 24, count 0 2006.201.12:10:58.02#ibcon#end of sib2, iclass 24, count 0 2006.201.12:10:58.02#ibcon#*after write, iclass 24, count 0 2006.201.12:10:58.02#ibcon#*before return 0, iclass 24, count 0 2006.201.12:10:58.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:10:58.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:10:58.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.12:10:58.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.12:10:58.02$vck44/va=7,5 2006.201.12:10:58.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.12:10:58.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.12:10:58.02#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:58.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:10:58.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:10:58.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:10:58.08#ibcon#enter wrdev, iclass 26, count 2 2006.201.12:10:58.08#ibcon#first serial, iclass 26, count 2 2006.201.12:10:58.08#ibcon#enter sib2, iclass 26, count 2 2006.201.12:10:58.08#ibcon#flushed, iclass 26, count 2 2006.201.12:10:58.08#ibcon#about to write, iclass 26, count 2 2006.201.12:10:58.08#ibcon#wrote, iclass 26, count 2 2006.201.12:10:58.08#ibcon#about to read 3, iclass 26, count 2 2006.201.12:10:58.10#ibcon#read 3, iclass 26, count 2 2006.201.12:10:58.10#ibcon#about to read 4, iclass 26, count 2 2006.201.12:10:58.10#ibcon#read 4, iclass 26, count 2 2006.201.12:10:58.10#ibcon#about to read 5, iclass 26, count 2 2006.201.12:10:58.10#ibcon#read 5, iclass 26, count 2 2006.201.12:10:58.10#ibcon#about to read 6, iclass 26, count 2 2006.201.12:10:58.10#ibcon#read 6, iclass 26, count 2 2006.201.12:10:58.10#ibcon#end of sib2, iclass 26, count 2 2006.201.12:10:58.10#ibcon#*mode == 0, iclass 26, count 2 2006.201.12:10:58.10#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.12:10:58.10#ibcon#[25=AT07-05\r\n] 2006.201.12:10:58.10#ibcon#*before write, iclass 26, count 2 2006.201.12:10:58.10#ibcon#enter sib2, iclass 26, count 2 2006.201.12:10:58.10#ibcon#flushed, iclass 26, count 2 2006.201.12:10:58.10#ibcon#about to write, iclass 26, count 2 2006.201.12:10:58.10#ibcon#wrote, iclass 26, count 2 2006.201.12:10:58.10#ibcon#about to read 3, iclass 26, count 2 2006.201.12:10:58.13#ibcon#read 3, iclass 26, count 2 2006.201.12:10:58.13#ibcon#about to read 4, iclass 26, count 2 2006.201.12:10:58.13#ibcon#read 4, iclass 26, count 2 2006.201.12:10:58.13#ibcon#about to read 5, iclass 26, count 2 2006.201.12:10:58.13#ibcon#read 5, iclass 26, count 2 2006.201.12:10:58.13#ibcon#about to read 6, iclass 26, count 2 2006.201.12:10:58.13#ibcon#read 6, iclass 26, count 2 2006.201.12:10:58.13#ibcon#end of sib2, iclass 26, count 2 2006.201.12:10:58.13#ibcon#*after write, iclass 26, count 2 2006.201.12:10:58.13#ibcon#*before return 0, iclass 26, count 2 2006.201.12:10:58.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:10:58.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:10:58.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.12:10:58.13#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:58.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:10:58.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:10:58.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:10:58.25#ibcon#enter wrdev, iclass 26, count 0 2006.201.12:10:58.25#ibcon#first serial, iclass 26, count 0 2006.201.12:10:58.25#ibcon#enter sib2, iclass 26, count 0 2006.201.12:10:58.25#ibcon#flushed, iclass 26, count 0 2006.201.12:10:58.25#ibcon#about to write, iclass 26, count 0 2006.201.12:10:58.25#ibcon#wrote, iclass 26, count 0 2006.201.12:10:58.25#ibcon#about to read 3, iclass 26, count 0 2006.201.12:10:58.27#ibcon#read 3, iclass 26, count 0 2006.201.12:10:58.27#ibcon#about to read 4, iclass 26, count 0 2006.201.12:10:58.27#ibcon#read 4, iclass 26, count 0 2006.201.12:10:58.27#ibcon#about to read 5, iclass 26, count 0 2006.201.12:10:58.27#ibcon#read 5, iclass 26, count 0 2006.201.12:10:58.27#ibcon#about to read 6, iclass 26, count 0 2006.201.12:10:58.27#ibcon#read 6, iclass 26, count 0 2006.201.12:10:58.27#ibcon#end of sib2, iclass 26, count 0 2006.201.12:10:58.27#ibcon#*mode == 0, iclass 26, count 0 2006.201.12:10:58.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.12:10:58.27#ibcon#[25=USB\r\n] 2006.201.12:10:58.27#ibcon#*before write, iclass 26, count 0 2006.201.12:10:58.27#ibcon#enter sib2, iclass 26, count 0 2006.201.12:10:58.27#ibcon#flushed, iclass 26, count 0 2006.201.12:10:58.27#ibcon#about to write, iclass 26, count 0 2006.201.12:10:58.27#ibcon#wrote, iclass 26, count 0 2006.201.12:10:58.27#ibcon#about to read 3, iclass 26, count 0 2006.201.12:10:58.30#ibcon#read 3, iclass 26, count 0 2006.201.12:10:58.30#ibcon#about to read 4, iclass 26, count 0 2006.201.12:10:58.30#ibcon#read 4, iclass 26, count 0 2006.201.12:10:58.30#ibcon#about to read 5, iclass 26, count 0 2006.201.12:10:58.30#ibcon#read 5, iclass 26, count 0 2006.201.12:10:58.30#ibcon#about to read 6, iclass 26, count 0 2006.201.12:10:58.30#ibcon#read 6, iclass 26, count 0 2006.201.12:10:58.30#ibcon#end of sib2, iclass 26, count 0 2006.201.12:10:58.30#ibcon#*after write, iclass 26, count 0 2006.201.12:10:58.30#ibcon#*before return 0, iclass 26, count 0 2006.201.12:10:58.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:10:58.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:10:58.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.12:10:58.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.12:10:58.30$vck44/valo=8,884.99 2006.201.12:10:58.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.12:10:58.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.12:10:58.30#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:58.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:10:58.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:10:58.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:10:58.30#ibcon#enter wrdev, iclass 28, count 0 2006.201.12:10:58.30#ibcon#first serial, iclass 28, count 0 2006.201.12:10:58.30#ibcon#enter sib2, iclass 28, count 0 2006.201.12:10:58.30#ibcon#flushed, iclass 28, count 0 2006.201.12:10:58.30#ibcon#about to write, iclass 28, count 0 2006.201.12:10:58.30#ibcon#wrote, iclass 28, count 0 2006.201.12:10:58.30#ibcon#about to read 3, iclass 28, count 0 2006.201.12:10:58.32#ibcon#read 3, iclass 28, count 0 2006.201.12:10:58.32#ibcon#about to read 4, iclass 28, count 0 2006.201.12:10:58.32#ibcon#read 4, iclass 28, count 0 2006.201.12:10:58.32#ibcon#about to read 5, iclass 28, count 0 2006.201.12:10:58.32#ibcon#read 5, iclass 28, count 0 2006.201.12:10:58.32#ibcon#about to read 6, iclass 28, count 0 2006.201.12:10:58.32#ibcon#read 6, iclass 28, count 0 2006.201.12:10:58.32#ibcon#end of sib2, iclass 28, count 0 2006.201.12:10:58.32#ibcon#*mode == 0, iclass 28, count 0 2006.201.12:10:58.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.12:10:58.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:10:58.32#ibcon#*before write, iclass 28, count 0 2006.201.12:10:58.32#ibcon#enter sib2, iclass 28, count 0 2006.201.12:10:58.32#ibcon#flushed, iclass 28, count 0 2006.201.12:10:58.32#ibcon#about to write, iclass 28, count 0 2006.201.12:10:58.32#ibcon#wrote, iclass 28, count 0 2006.201.12:10:58.32#ibcon#about to read 3, iclass 28, count 0 2006.201.12:10:58.36#ibcon#read 3, iclass 28, count 0 2006.201.12:10:58.36#ibcon#about to read 4, iclass 28, count 0 2006.201.12:10:58.36#ibcon#read 4, iclass 28, count 0 2006.201.12:10:58.36#ibcon#about to read 5, iclass 28, count 0 2006.201.12:10:58.36#ibcon#read 5, iclass 28, count 0 2006.201.12:10:58.36#ibcon#about to read 6, iclass 28, count 0 2006.201.12:10:58.36#ibcon#read 6, iclass 28, count 0 2006.201.12:10:58.36#ibcon#end of sib2, iclass 28, count 0 2006.201.12:10:58.36#ibcon#*after write, iclass 28, count 0 2006.201.12:10:58.36#ibcon#*before return 0, iclass 28, count 0 2006.201.12:10:58.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:10:58.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:10:58.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.12:10:58.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.12:10:58.36$vck44/va=8,4 2006.201.12:10:58.36#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.12:10:58.36#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.12:10:58.36#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:58.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:10:58.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:10:58.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:10:58.42#ibcon#enter wrdev, iclass 30, count 2 2006.201.12:10:58.42#ibcon#first serial, iclass 30, count 2 2006.201.12:10:58.42#ibcon#enter sib2, iclass 30, count 2 2006.201.12:10:58.42#ibcon#flushed, iclass 30, count 2 2006.201.12:10:58.42#ibcon#about to write, iclass 30, count 2 2006.201.12:10:58.42#ibcon#wrote, iclass 30, count 2 2006.201.12:10:58.42#ibcon#about to read 3, iclass 30, count 2 2006.201.12:10:58.44#ibcon#read 3, iclass 30, count 2 2006.201.12:10:58.44#ibcon#about to read 4, iclass 30, count 2 2006.201.12:10:58.44#ibcon#read 4, iclass 30, count 2 2006.201.12:10:58.44#ibcon#about to read 5, iclass 30, count 2 2006.201.12:10:58.44#ibcon#read 5, iclass 30, count 2 2006.201.12:10:58.44#ibcon#about to read 6, iclass 30, count 2 2006.201.12:10:58.44#ibcon#read 6, iclass 30, count 2 2006.201.12:10:58.44#ibcon#end of sib2, iclass 30, count 2 2006.201.12:10:58.44#ibcon#*mode == 0, iclass 30, count 2 2006.201.12:10:58.44#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.12:10:58.44#ibcon#[25=AT08-04\r\n] 2006.201.12:10:58.44#ibcon#*before write, iclass 30, count 2 2006.201.12:10:58.44#ibcon#enter sib2, iclass 30, count 2 2006.201.12:10:58.44#ibcon#flushed, iclass 30, count 2 2006.201.12:10:58.44#ibcon#about to write, iclass 30, count 2 2006.201.12:10:58.44#ibcon#wrote, iclass 30, count 2 2006.201.12:10:58.44#ibcon#about to read 3, iclass 30, count 2 2006.201.12:10:58.47#ibcon#read 3, iclass 30, count 2 2006.201.12:10:58.47#ibcon#about to read 4, iclass 30, count 2 2006.201.12:10:58.47#ibcon#read 4, iclass 30, count 2 2006.201.12:10:58.47#ibcon#about to read 5, iclass 30, count 2 2006.201.12:10:58.47#ibcon#read 5, iclass 30, count 2 2006.201.12:10:58.47#ibcon#about to read 6, iclass 30, count 2 2006.201.12:10:58.47#ibcon#read 6, iclass 30, count 2 2006.201.12:10:58.47#ibcon#end of sib2, iclass 30, count 2 2006.201.12:10:58.47#ibcon#*after write, iclass 30, count 2 2006.201.12:10:58.47#ibcon#*before return 0, iclass 30, count 2 2006.201.12:10:58.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:10:58.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:10:58.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.12:10:58.47#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:58.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:10:58.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:10:58.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:10:58.59#ibcon#enter wrdev, iclass 30, count 0 2006.201.12:10:58.59#ibcon#first serial, iclass 30, count 0 2006.201.12:10:58.59#ibcon#enter sib2, iclass 30, count 0 2006.201.12:10:58.59#ibcon#flushed, iclass 30, count 0 2006.201.12:10:58.59#ibcon#about to write, iclass 30, count 0 2006.201.12:10:58.59#ibcon#wrote, iclass 30, count 0 2006.201.12:10:58.59#ibcon#about to read 3, iclass 30, count 0 2006.201.12:10:58.61#ibcon#read 3, iclass 30, count 0 2006.201.12:10:58.61#ibcon#about to read 4, iclass 30, count 0 2006.201.12:10:58.61#ibcon#read 4, iclass 30, count 0 2006.201.12:10:58.61#ibcon#about to read 5, iclass 30, count 0 2006.201.12:10:58.61#ibcon#read 5, iclass 30, count 0 2006.201.12:10:58.61#ibcon#about to read 6, iclass 30, count 0 2006.201.12:10:58.61#ibcon#read 6, iclass 30, count 0 2006.201.12:10:58.61#ibcon#end of sib2, iclass 30, count 0 2006.201.12:10:58.61#ibcon#*mode == 0, iclass 30, count 0 2006.201.12:10:58.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.12:10:58.61#ibcon#[25=USB\r\n] 2006.201.12:10:58.61#ibcon#*before write, iclass 30, count 0 2006.201.12:10:58.61#ibcon#enter sib2, iclass 30, count 0 2006.201.12:10:58.61#ibcon#flushed, iclass 30, count 0 2006.201.12:10:58.61#ibcon#about to write, iclass 30, count 0 2006.201.12:10:58.61#ibcon#wrote, iclass 30, count 0 2006.201.12:10:58.61#ibcon#about to read 3, iclass 30, count 0 2006.201.12:10:58.64#ibcon#read 3, iclass 30, count 0 2006.201.12:10:58.64#ibcon#about to read 4, iclass 30, count 0 2006.201.12:10:58.64#ibcon#read 4, iclass 30, count 0 2006.201.12:10:58.64#ibcon#about to read 5, iclass 30, count 0 2006.201.12:10:58.64#ibcon#read 5, iclass 30, count 0 2006.201.12:10:58.64#ibcon#about to read 6, iclass 30, count 0 2006.201.12:10:58.64#ibcon#read 6, iclass 30, count 0 2006.201.12:10:58.64#ibcon#end of sib2, iclass 30, count 0 2006.201.12:10:58.64#ibcon#*after write, iclass 30, count 0 2006.201.12:10:58.64#ibcon#*before return 0, iclass 30, count 0 2006.201.12:10:58.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:10:58.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:10:58.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.12:10:58.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.12:10:58.64$vck44/vblo=1,629.99 2006.201.12:10:58.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.12:10:58.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.12:10:58.64#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:58.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:10:58.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:10:58.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:10:58.64#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:10:58.64#ibcon#first serial, iclass 32, count 0 2006.201.12:10:58.64#ibcon#enter sib2, iclass 32, count 0 2006.201.12:10:58.64#ibcon#flushed, iclass 32, count 0 2006.201.12:10:58.64#ibcon#about to write, iclass 32, count 0 2006.201.12:10:58.64#ibcon#wrote, iclass 32, count 0 2006.201.12:10:58.64#ibcon#about to read 3, iclass 32, count 0 2006.201.12:10:58.66#ibcon#read 3, iclass 32, count 0 2006.201.12:10:58.66#ibcon#about to read 4, iclass 32, count 0 2006.201.12:10:58.66#ibcon#read 4, iclass 32, count 0 2006.201.12:10:58.66#ibcon#about to read 5, iclass 32, count 0 2006.201.12:10:58.66#ibcon#read 5, iclass 32, count 0 2006.201.12:10:58.66#ibcon#about to read 6, iclass 32, count 0 2006.201.12:10:58.66#ibcon#read 6, iclass 32, count 0 2006.201.12:10:58.66#ibcon#end of sib2, iclass 32, count 0 2006.201.12:10:58.66#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:10:58.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:10:58.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:10:58.66#ibcon#*before write, iclass 32, count 0 2006.201.12:10:58.66#ibcon#enter sib2, iclass 32, count 0 2006.201.12:10:58.66#ibcon#flushed, iclass 32, count 0 2006.201.12:10:58.66#ibcon#about to write, iclass 32, count 0 2006.201.12:10:58.66#ibcon#wrote, iclass 32, count 0 2006.201.12:10:58.66#ibcon#about to read 3, iclass 32, count 0 2006.201.12:10:58.70#ibcon#read 3, iclass 32, count 0 2006.201.12:10:58.70#ibcon#about to read 4, iclass 32, count 0 2006.201.12:10:58.70#ibcon#read 4, iclass 32, count 0 2006.201.12:10:58.70#ibcon#about to read 5, iclass 32, count 0 2006.201.12:10:58.70#ibcon#read 5, iclass 32, count 0 2006.201.12:10:58.70#ibcon#about to read 6, iclass 32, count 0 2006.201.12:10:58.70#ibcon#read 6, iclass 32, count 0 2006.201.12:10:58.70#ibcon#end of sib2, iclass 32, count 0 2006.201.12:10:58.70#ibcon#*after write, iclass 32, count 0 2006.201.12:10:58.70#ibcon#*before return 0, iclass 32, count 0 2006.201.12:10:58.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:10:58.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:10:58.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:10:58.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:10:58.70$vck44/vb=1,4 2006.201.12:10:58.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.12:10:58.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.12:10:58.70#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:58.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:10:58.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:10:58.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:10:58.70#ibcon#enter wrdev, iclass 34, count 2 2006.201.12:10:58.70#ibcon#first serial, iclass 34, count 2 2006.201.12:10:58.70#ibcon#enter sib2, iclass 34, count 2 2006.201.12:10:58.70#ibcon#flushed, iclass 34, count 2 2006.201.12:10:58.70#ibcon#about to write, iclass 34, count 2 2006.201.12:10:58.70#ibcon#wrote, iclass 34, count 2 2006.201.12:10:58.70#ibcon#about to read 3, iclass 34, count 2 2006.201.12:10:58.72#ibcon#read 3, iclass 34, count 2 2006.201.12:10:58.72#ibcon#about to read 4, iclass 34, count 2 2006.201.12:10:58.72#ibcon#read 4, iclass 34, count 2 2006.201.12:10:58.72#ibcon#about to read 5, iclass 34, count 2 2006.201.12:10:58.72#ibcon#read 5, iclass 34, count 2 2006.201.12:10:58.72#ibcon#about to read 6, iclass 34, count 2 2006.201.12:10:58.72#ibcon#read 6, iclass 34, count 2 2006.201.12:10:58.72#ibcon#end of sib2, iclass 34, count 2 2006.201.12:10:58.72#ibcon#*mode == 0, iclass 34, count 2 2006.201.12:10:58.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.12:10:58.72#ibcon#[27=AT01-04\r\n] 2006.201.12:10:58.72#ibcon#*before write, iclass 34, count 2 2006.201.12:10:58.72#ibcon#enter sib2, iclass 34, count 2 2006.201.12:10:58.72#ibcon#flushed, iclass 34, count 2 2006.201.12:10:58.72#ibcon#about to write, iclass 34, count 2 2006.201.12:10:58.72#ibcon#wrote, iclass 34, count 2 2006.201.12:10:58.72#ibcon#about to read 3, iclass 34, count 2 2006.201.12:10:58.75#ibcon#read 3, iclass 34, count 2 2006.201.12:10:58.75#ibcon#about to read 4, iclass 34, count 2 2006.201.12:10:58.75#ibcon#read 4, iclass 34, count 2 2006.201.12:10:58.75#ibcon#about to read 5, iclass 34, count 2 2006.201.12:10:58.75#ibcon#read 5, iclass 34, count 2 2006.201.12:10:58.75#ibcon#about to read 6, iclass 34, count 2 2006.201.12:10:58.75#ibcon#read 6, iclass 34, count 2 2006.201.12:10:58.75#ibcon#end of sib2, iclass 34, count 2 2006.201.12:10:58.75#ibcon#*after write, iclass 34, count 2 2006.201.12:10:58.75#ibcon#*before return 0, iclass 34, count 2 2006.201.12:10:58.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:10:58.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:10:58.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.12:10:58.75#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:58.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:10:58.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:10:58.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:10:58.87#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:10:58.87#ibcon#first serial, iclass 34, count 0 2006.201.12:10:58.87#ibcon#enter sib2, iclass 34, count 0 2006.201.12:10:58.87#ibcon#flushed, iclass 34, count 0 2006.201.12:10:58.87#ibcon#about to write, iclass 34, count 0 2006.201.12:10:58.87#ibcon#wrote, iclass 34, count 0 2006.201.12:10:58.87#ibcon#about to read 3, iclass 34, count 0 2006.201.12:10:58.89#ibcon#read 3, iclass 34, count 0 2006.201.12:10:58.89#ibcon#about to read 4, iclass 34, count 0 2006.201.12:10:58.89#ibcon#read 4, iclass 34, count 0 2006.201.12:10:58.89#ibcon#about to read 5, iclass 34, count 0 2006.201.12:10:58.89#ibcon#read 5, iclass 34, count 0 2006.201.12:10:58.89#ibcon#about to read 6, iclass 34, count 0 2006.201.12:10:58.89#ibcon#read 6, iclass 34, count 0 2006.201.12:10:58.89#ibcon#end of sib2, iclass 34, count 0 2006.201.12:10:58.89#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:10:58.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:10:58.89#ibcon#[27=USB\r\n] 2006.201.12:10:58.89#ibcon#*before write, iclass 34, count 0 2006.201.12:10:58.89#ibcon#enter sib2, iclass 34, count 0 2006.201.12:10:58.89#ibcon#flushed, iclass 34, count 0 2006.201.12:10:58.89#ibcon#about to write, iclass 34, count 0 2006.201.12:10:58.89#ibcon#wrote, iclass 34, count 0 2006.201.12:10:58.89#ibcon#about to read 3, iclass 34, count 0 2006.201.12:10:58.92#ibcon#read 3, iclass 34, count 0 2006.201.12:10:58.92#ibcon#about to read 4, iclass 34, count 0 2006.201.12:10:58.92#ibcon#read 4, iclass 34, count 0 2006.201.12:10:58.92#ibcon#about to read 5, iclass 34, count 0 2006.201.12:10:58.92#ibcon#read 5, iclass 34, count 0 2006.201.12:10:58.92#ibcon#about to read 6, iclass 34, count 0 2006.201.12:10:58.92#ibcon#read 6, iclass 34, count 0 2006.201.12:10:58.92#ibcon#end of sib2, iclass 34, count 0 2006.201.12:10:58.92#ibcon#*after write, iclass 34, count 0 2006.201.12:10:58.92#ibcon#*before return 0, iclass 34, count 0 2006.201.12:10:58.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:10:58.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:10:58.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:10:58.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:10:58.92$vck44/vblo=2,634.99 2006.201.12:10:58.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.12:10:58.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.12:10:58.92#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:58.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:58.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:58.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:58.92#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:10:58.92#ibcon#first serial, iclass 36, count 0 2006.201.12:10:58.92#ibcon#enter sib2, iclass 36, count 0 2006.201.12:10:58.92#ibcon#flushed, iclass 36, count 0 2006.201.12:10:58.92#ibcon#about to write, iclass 36, count 0 2006.201.12:10:58.92#ibcon#wrote, iclass 36, count 0 2006.201.12:10:58.92#ibcon#about to read 3, iclass 36, count 0 2006.201.12:10:58.94#ibcon#read 3, iclass 36, count 0 2006.201.12:10:58.94#ibcon#about to read 4, iclass 36, count 0 2006.201.12:10:58.94#ibcon#read 4, iclass 36, count 0 2006.201.12:10:58.94#ibcon#about to read 5, iclass 36, count 0 2006.201.12:10:58.94#ibcon#read 5, iclass 36, count 0 2006.201.12:10:58.94#ibcon#about to read 6, iclass 36, count 0 2006.201.12:10:58.94#ibcon#read 6, iclass 36, count 0 2006.201.12:10:58.94#ibcon#end of sib2, iclass 36, count 0 2006.201.12:10:58.94#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:10:58.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:10:58.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:10:58.94#ibcon#*before write, iclass 36, count 0 2006.201.12:10:58.94#ibcon#enter sib2, iclass 36, count 0 2006.201.12:10:58.94#ibcon#flushed, iclass 36, count 0 2006.201.12:10:58.94#ibcon#about to write, iclass 36, count 0 2006.201.12:10:58.94#ibcon#wrote, iclass 36, count 0 2006.201.12:10:58.94#ibcon#about to read 3, iclass 36, count 0 2006.201.12:10:58.98#ibcon#read 3, iclass 36, count 0 2006.201.12:10:58.98#ibcon#about to read 4, iclass 36, count 0 2006.201.12:10:58.98#ibcon#read 4, iclass 36, count 0 2006.201.12:10:58.98#ibcon#about to read 5, iclass 36, count 0 2006.201.12:10:58.98#ibcon#read 5, iclass 36, count 0 2006.201.12:10:58.98#ibcon#about to read 6, iclass 36, count 0 2006.201.12:10:58.98#ibcon#read 6, iclass 36, count 0 2006.201.12:10:58.98#ibcon#end of sib2, iclass 36, count 0 2006.201.12:10:58.98#ibcon#*after write, iclass 36, count 0 2006.201.12:10:58.98#ibcon#*before return 0, iclass 36, count 0 2006.201.12:10:58.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:58.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:10:58.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:10:58.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:10:58.98$vck44/vb=2,5 2006.201.12:10:58.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.12:10:58.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.12:10:58.98#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:58.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:59.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:59.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:59.04#ibcon#enter wrdev, iclass 38, count 2 2006.201.12:10:59.04#ibcon#first serial, iclass 38, count 2 2006.201.12:10:59.04#ibcon#enter sib2, iclass 38, count 2 2006.201.12:10:59.04#ibcon#flushed, iclass 38, count 2 2006.201.12:10:59.04#ibcon#about to write, iclass 38, count 2 2006.201.12:10:59.04#ibcon#wrote, iclass 38, count 2 2006.201.12:10:59.04#ibcon#about to read 3, iclass 38, count 2 2006.201.12:10:59.06#ibcon#read 3, iclass 38, count 2 2006.201.12:10:59.06#ibcon#about to read 4, iclass 38, count 2 2006.201.12:10:59.06#ibcon#read 4, iclass 38, count 2 2006.201.12:10:59.06#ibcon#about to read 5, iclass 38, count 2 2006.201.12:10:59.06#ibcon#read 5, iclass 38, count 2 2006.201.12:10:59.06#ibcon#about to read 6, iclass 38, count 2 2006.201.12:10:59.06#ibcon#read 6, iclass 38, count 2 2006.201.12:10:59.06#ibcon#end of sib2, iclass 38, count 2 2006.201.12:10:59.06#ibcon#*mode == 0, iclass 38, count 2 2006.201.12:10:59.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.12:10:59.06#ibcon#[27=AT02-05\r\n] 2006.201.12:10:59.06#ibcon#*before write, iclass 38, count 2 2006.201.12:10:59.06#ibcon#enter sib2, iclass 38, count 2 2006.201.12:10:59.06#ibcon#flushed, iclass 38, count 2 2006.201.12:10:59.06#ibcon#about to write, iclass 38, count 2 2006.201.12:10:59.06#ibcon#wrote, iclass 38, count 2 2006.201.12:10:59.06#ibcon#about to read 3, iclass 38, count 2 2006.201.12:10:59.09#ibcon#read 3, iclass 38, count 2 2006.201.12:10:59.09#ibcon#about to read 4, iclass 38, count 2 2006.201.12:10:59.09#ibcon#read 4, iclass 38, count 2 2006.201.12:10:59.09#ibcon#about to read 5, iclass 38, count 2 2006.201.12:10:59.09#ibcon#read 5, iclass 38, count 2 2006.201.12:10:59.09#ibcon#about to read 6, iclass 38, count 2 2006.201.12:10:59.09#ibcon#read 6, iclass 38, count 2 2006.201.12:10:59.09#ibcon#end of sib2, iclass 38, count 2 2006.201.12:10:59.09#ibcon#*after write, iclass 38, count 2 2006.201.12:10:59.09#ibcon#*before return 0, iclass 38, count 2 2006.201.12:10:59.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:59.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:10:59.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.12:10:59.09#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:59.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:59.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:59.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:59.21#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:10:59.21#ibcon#first serial, iclass 38, count 0 2006.201.12:10:59.21#ibcon#enter sib2, iclass 38, count 0 2006.201.12:10:59.21#ibcon#flushed, iclass 38, count 0 2006.201.12:10:59.21#ibcon#about to write, iclass 38, count 0 2006.201.12:10:59.21#ibcon#wrote, iclass 38, count 0 2006.201.12:10:59.21#ibcon#about to read 3, iclass 38, count 0 2006.201.12:10:59.23#ibcon#read 3, iclass 38, count 0 2006.201.12:10:59.23#ibcon#about to read 4, iclass 38, count 0 2006.201.12:10:59.23#ibcon#read 4, iclass 38, count 0 2006.201.12:10:59.23#ibcon#about to read 5, iclass 38, count 0 2006.201.12:10:59.23#ibcon#read 5, iclass 38, count 0 2006.201.12:10:59.23#ibcon#about to read 6, iclass 38, count 0 2006.201.12:10:59.23#ibcon#read 6, iclass 38, count 0 2006.201.12:10:59.23#ibcon#end of sib2, iclass 38, count 0 2006.201.12:10:59.23#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:10:59.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:10:59.23#ibcon#[27=USB\r\n] 2006.201.12:10:59.23#ibcon#*before write, iclass 38, count 0 2006.201.12:10:59.23#ibcon#enter sib2, iclass 38, count 0 2006.201.12:10:59.23#ibcon#flushed, iclass 38, count 0 2006.201.12:10:59.23#ibcon#about to write, iclass 38, count 0 2006.201.12:10:59.23#ibcon#wrote, iclass 38, count 0 2006.201.12:10:59.23#ibcon#about to read 3, iclass 38, count 0 2006.201.12:10:59.26#ibcon#read 3, iclass 38, count 0 2006.201.12:10:59.26#ibcon#about to read 4, iclass 38, count 0 2006.201.12:10:59.26#ibcon#read 4, iclass 38, count 0 2006.201.12:10:59.26#ibcon#about to read 5, iclass 38, count 0 2006.201.12:10:59.26#ibcon#read 5, iclass 38, count 0 2006.201.12:10:59.26#ibcon#about to read 6, iclass 38, count 0 2006.201.12:10:59.26#ibcon#read 6, iclass 38, count 0 2006.201.12:10:59.26#ibcon#end of sib2, iclass 38, count 0 2006.201.12:10:59.26#ibcon#*after write, iclass 38, count 0 2006.201.12:10:59.26#ibcon#*before return 0, iclass 38, count 0 2006.201.12:10:59.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:59.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:10:59.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:10:59.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:10:59.26$vck44/vblo=3,649.99 2006.201.12:10:59.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.12:10:59.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.12:10:59.26#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:59.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:59.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:59.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:59.26#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:10:59.26#ibcon#first serial, iclass 40, count 0 2006.201.12:10:59.26#ibcon#enter sib2, iclass 40, count 0 2006.201.12:10:59.26#ibcon#flushed, iclass 40, count 0 2006.201.12:10:59.26#ibcon#about to write, iclass 40, count 0 2006.201.12:10:59.26#ibcon#wrote, iclass 40, count 0 2006.201.12:10:59.26#ibcon#about to read 3, iclass 40, count 0 2006.201.12:10:59.28#ibcon#read 3, iclass 40, count 0 2006.201.12:10:59.28#ibcon#about to read 4, iclass 40, count 0 2006.201.12:10:59.28#ibcon#read 4, iclass 40, count 0 2006.201.12:10:59.28#ibcon#about to read 5, iclass 40, count 0 2006.201.12:10:59.28#ibcon#read 5, iclass 40, count 0 2006.201.12:10:59.28#ibcon#about to read 6, iclass 40, count 0 2006.201.12:10:59.28#ibcon#read 6, iclass 40, count 0 2006.201.12:10:59.28#ibcon#end of sib2, iclass 40, count 0 2006.201.12:10:59.28#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:10:59.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:10:59.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:10:59.28#ibcon#*before write, iclass 40, count 0 2006.201.12:10:59.28#ibcon#enter sib2, iclass 40, count 0 2006.201.12:10:59.28#ibcon#flushed, iclass 40, count 0 2006.201.12:10:59.28#ibcon#about to write, iclass 40, count 0 2006.201.12:10:59.28#ibcon#wrote, iclass 40, count 0 2006.201.12:10:59.28#ibcon#about to read 3, iclass 40, count 0 2006.201.12:10:59.33#ibcon#read 3, iclass 40, count 0 2006.201.12:10:59.33#ibcon#about to read 4, iclass 40, count 0 2006.201.12:10:59.33#ibcon#read 4, iclass 40, count 0 2006.201.12:10:59.33#ibcon#about to read 5, iclass 40, count 0 2006.201.12:10:59.33#ibcon#read 5, iclass 40, count 0 2006.201.12:10:59.33#ibcon#about to read 6, iclass 40, count 0 2006.201.12:10:59.33#ibcon#read 6, iclass 40, count 0 2006.201.12:10:59.33#ibcon#end of sib2, iclass 40, count 0 2006.201.12:10:59.33#ibcon#*after write, iclass 40, count 0 2006.201.12:10:59.33#ibcon#*before return 0, iclass 40, count 0 2006.201.12:10:59.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:59.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:10:59.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:10:59.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:10:59.33$vck44/vb=3,4 2006.201.12:10:59.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.12:10:59.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.12:10:59.33#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:59.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:59.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:59.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:59.38#ibcon#enter wrdev, iclass 4, count 2 2006.201.12:10:59.38#ibcon#first serial, iclass 4, count 2 2006.201.12:10:59.38#ibcon#enter sib2, iclass 4, count 2 2006.201.12:10:59.38#ibcon#flushed, iclass 4, count 2 2006.201.12:10:59.38#ibcon#about to write, iclass 4, count 2 2006.201.12:10:59.38#ibcon#wrote, iclass 4, count 2 2006.201.12:10:59.38#ibcon#about to read 3, iclass 4, count 2 2006.201.12:10:59.40#ibcon#read 3, iclass 4, count 2 2006.201.12:10:59.40#ibcon#about to read 4, iclass 4, count 2 2006.201.12:10:59.40#ibcon#read 4, iclass 4, count 2 2006.201.12:10:59.40#ibcon#about to read 5, iclass 4, count 2 2006.201.12:10:59.40#ibcon#read 5, iclass 4, count 2 2006.201.12:10:59.40#ibcon#about to read 6, iclass 4, count 2 2006.201.12:10:59.40#ibcon#read 6, iclass 4, count 2 2006.201.12:10:59.40#ibcon#end of sib2, iclass 4, count 2 2006.201.12:10:59.40#ibcon#*mode == 0, iclass 4, count 2 2006.201.12:10:59.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.12:10:59.40#ibcon#[27=AT03-04\r\n] 2006.201.12:10:59.40#ibcon#*before write, iclass 4, count 2 2006.201.12:10:59.40#ibcon#enter sib2, iclass 4, count 2 2006.201.12:10:59.40#ibcon#flushed, iclass 4, count 2 2006.201.12:10:59.40#ibcon#about to write, iclass 4, count 2 2006.201.12:10:59.40#ibcon#wrote, iclass 4, count 2 2006.201.12:10:59.40#ibcon#about to read 3, iclass 4, count 2 2006.201.12:10:59.43#ibcon#read 3, iclass 4, count 2 2006.201.12:10:59.43#ibcon#about to read 4, iclass 4, count 2 2006.201.12:10:59.43#ibcon#read 4, iclass 4, count 2 2006.201.12:10:59.43#ibcon#about to read 5, iclass 4, count 2 2006.201.12:10:59.43#ibcon#read 5, iclass 4, count 2 2006.201.12:10:59.43#ibcon#about to read 6, iclass 4, count 2 2006.201.12:10:59.43#ibcon#read 6, iclass 4, count 2 2006.201.12:10:59.43#ibcon#end of sib2, iclass 4, count 2 2006.201.12:10:59.43#ibcon#*after write, iclass 4, count 2 2006.201.12:10:59.43#ibcon#*before return 0, iclass 4, count 2 2006.201.12:10:59.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:59.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:10:59.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.12:10:59.43#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:59.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:59.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:59.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:59.55#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:10:59.55#ibcon#first serial, iclass 4, count 0 2006.201.12:10:59.55#ibcon#enter sib2, iclass 4, count 0 2006.201.12:10:59.55#ibcon#flushed, iclass 4, count 0 2006.201.12:10:59.55#ibcon#about to write, iclass 4, count 0 2006.201.12:10:59.55#ibcon#wrote, iclass 4, count 0 2006.201.12:10:59.55#ibcon#about to read 3, iclass 4, count 0 2006.201.12:10:59.57#ibcon#read 3, iclass 4, count 0 2006.201.12:10:59.57#ibcon#about to read 4, iclass 4, count 0 2006.201.12:10:59.57#ibcon#read 4, iclass 4, count 0 2006.201.12:10:59.57#ibcon#about to read 5, iclass 4, count 0 2006.201.12:10:59.57#ibcon#read 5, iclass 4, count 0 2006.201.12:10:59.57#ibcon#about to read 6, iclass 4, count 0 2006.201.12:10:59.57#ibcon#read 6, iclass 4, count 0 2006.201.12:10:59.57#ibcon#end of sib2, iclass 4, count 0 2006.201.12:10:59.57#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:10:59.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:10:59.57#ibcon#[27=USB\r\n] 2006.201.12:10:59.57#ibcon#*before write, iclass 4, count 0 2006.201.12:10:59.57#ibcon#enter sib2, iclass 4, count 0 2006.201.12:10:59.57#ibcon#flushed, iclass 4, count 0 2006.201.12:10:59.57#ibcon#about to write, iclass 4, count 0 2006.201.12:10:59.57#ibcon#wrote, iclass 4, count 0 2006.201.12:10:59.57#ibcon#about to read 3, iclass 4, count 0 2006.201.12:10:59.60#ibcon#read 3, iclass 4, count 0 2006.201.12:10:59.60#ibcon#about to read 4, iclass 4, count 0 2006.201.12:10:59.60#ibcon#read 4, iclass 4, count 0 2006.201.12:10:59.60#ibcon#about to read 5, iclass 4, count 0 2006.201.12:10:59.60#ibcon#read 5, iclass 4, count 0 2006.201.12:10:59.60#ibcon#about to read 6, iclass 4, count 0 2006.201.12:10:59.60#ibcon#read 6, iclass 4, count 0 2006.201.12:10:59.60#ibcon#end of sib2, iclass 4, count 0 2006.201.12:10:59.60#ibcon#*after write, iclass 4, count 0 2006.201.12:10:59.60#ibcon#*before return 0, iclass 4, count 0 2006.201.12:10:59.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:59.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:10:59.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:10:59.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:10:59.60$vck44/vblo=4,679.99 2006.201.12:10:59.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.12:10:59.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.12:10:59.60#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:59.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:59.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:59.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:59.60#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:10:59.60#ibcon#first serial, iclass 6, count 0 2006.201.12:10:59.60#ibcon#enter sib2, iclass 6, count 0 2006.201.12:10:59.60#ibcon#flushed, iclass 6, count 0 2006.201.12:10:59.60#ibcon#about to write, iclass 6, count 0 2006.201.12:10:59.60#ibcon#wrote, iclass 6, count 0 2006.201.12:10:59.60#ibcon#about to read 3, iclass 6, count 0 2006.201.12:10:59.62#ibcon#read 3, iclass 6, count 0 2006.201.12:10:59.62#ibcon#about to read 4, iclass 6, count 0 2006.201.12:10:59.62#ibcon#read 4, iclass 6, count 0 2006.201.12:10:59.62#ibcon#about to read 5, iclass 6, count 0 2006.201.12:10:59.62#ibcon#read 5, iclass 6, count 0 2006.201.12:10:59.62#ibcon#about to read 6, iclass 6, count 0 2006.201.12:10:59.62#ibcon#read 6, iclass 6, count 0 2006.201.12:10:59.62#ibcon#end of sib2, iclass 6, count 0 2006.201.12:10:59.62#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:10:59.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:10:59.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:10:59.62#ibcon#*before write, iclass 6, count 0 2006.201.12:10:59.62#ibcon#enter sib2, iclass 6, count 0 2006.201.12:10:59.62#ibcon#flushed, iclass 6, count 0 2006.201.12:10:59.62#ibcon#about to write, iclass 6, count 0 2006.201.12:10:59.62#ibcon#wrote, iclass 6, count 0 2006.201.12:10:59.62#ibcon#about to read 3, iclass 6, count 0 2006.201.12:10:59.66#ibcon#read 3, iclass 6, count 0 2006.201.12:10:59.66#ibcon#about to read 4, iclass 6, count 0 2006.201.12:10:59.66#ibcon#read 4, iclass 6, count 0 2006.201.12:10:59.66#ibcon#about to read 5, iclass 6, count 0 2006.201.12:10:59.66#ibcon#read 5, iclass 6, count 0 2006.201.12:10:59.66#ibcon#about to read 6, iclass 6, count 0 2006.201.12:10:59.66#ibcon#read 6, iclass 6, count 0 2006.201.12:10:59.66#ibcon#end of sib2, iclass 6, count 0 2006.201.12:10:59.66#ibcon#*after write, iclass 6, count 0 2006.201.12:10:59.66#ibcon#*before return 0, iclass 6, count 0 2006.201.12:10:59.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:59.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:10:59.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:10:59.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:10:59.66$vck44/vb=4,5 2006.201.12:10:59.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.12:10:59.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.12:10:59.66#ibcon#ireg 11 cls_cnt 2 2006.201.12:10:59.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:10:59.69#abcon#<5=/04 1.9 3.8 21.231001003.9\r\n> 2006.201.12:10:59.71#abcon#{5=INTERFACE CLEAR} 2006.201.12:10:59.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:10:59.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:10:59.72#ibcon#enter wrdev, iclass 11, count 2 2006.201.12:10:59.72#ibcon#first serial, iclass 11, count 2 2006.201.12:10:59.72#ibcon#enter sib2, iclass 11, count 2 2006.201.12:10:59.72#ibcon#flushed, iclass 11, count 2 2006.201.12:10:59.72#ibcon#about to write, iclass 11, count 2 2006.201.12:10:59.72#ibcon#wrote, iclass 11, count 2 2006.201.12:10:59.72#ibcon#about to read 3, iclass 11, count 2 2006.201.12:10:59.74#ibcon#read 3, iclass 11, count 2 2006.201.12:10:59.74#ibcon#about to read 4, iclass 11, count 2 2006.201.12:10:59.74#ibcon#read 4, iclass 11, count 2 2006.201.12:10:59.74#ibcon#about to read 5, iclass 11, count 2 2006.201.12:10:59.74#ibcon#read 5, iclass 11, count 2 2006.201.12:10:59.74#ibcon#about to read 6, iclass 11, count 2 2006.201.12:10:59.74#ibcon#read 6, iclass 11, count 2 2006.201.12:10:59.74#ibcon#end of sib2, iclass 11, count 2 2006.201.12:10:59.74#ibcon#*mode == 0, iclass 11, count 2 2006.201.12:10:59.74#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.12:10:59.74#ibcon#[27=AT04-05\r\n] 2006.201.12:10:59.74#ibcon#*before write, iclass 11, count 2 2006.201.12:10:59.74#ibcon#enter sib2, iclass 11, count 2 2006.201.12:10:59.74#ibcon#flushed, iclass 11, count 2 2006.201.12:10:59.74#ibcon#about to write, iclass 11, count 2 2006.201.12:10:59.74#ibcon#wrote, iclass 11, count 2 2006.201.12:10:59.74#ibcon#about to read 3, iclass 11, count 2 2006.201.12:10:59.77#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:10:59.77#ibcon#read 3, iclass 11, count 2 2006.201.12:10:59.77#ibcon#about to read 4, iclass 11, count 2 2006.201.12:10:59.77#ibcon#read 4, iclass 11, count 2 2006.201.12:10:59.77#ibcon#about to read 5, iclass 11, count 2 2006.201.12:10:59.77#ibcon#read 5, iclass 11, count 2 2006.201.12:10:59.77#ibcon#about to read 6, iclass 11, count 2 2006.201.12:10:59.77#ibcon#read 6, iclass 11, count 2 2006.201.12:10:59.77#ibcon#end of sib2, iclass 11, count 2 2006.201.12:10:59.77#ibcon#*after write, iclass 11, count 2 2006.201.12:10:59.77#ibcon#*before return 0, iclass 11, count 2 2006.201.12:10:59.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:10:59.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:10:59.77#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.12:10:59.77#ibcon#ireg 7 cls_cnt 0 2006.201.12:10:59.77#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:10:59.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:10:59.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:10:59.89#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:10:59.89#ibcon#first serial, iclass 11, count 0 2006.201.12:10:59.89#ibcon#enter sib2, iclass 11, count 0 2006.201.12:10:59.89#ibcon#flushed, iclass 11, count 0 2006.201.12:10:59.89#ibcon#about to write, iclass 11, count 0 2006.201.12:10:59.89#ibcon#wrote, iclass 11, count 0 2006.201.12:10:59.89#ibcon#about to read 3, iclass 11, count 0 2006.201.12:10:59.91#ibcon#read 3, iclass 11, count 0 2006.201.12:10:59.91#ibcon#about to read 4, iclass 11, count 0 2006.201.12:10:59.91#ibcon#read 4, iclass 11, count 0 2006.201.12:10:59.91#ibcon#about to read 5, iclass 11, count 0 2006.201.12:10:59.91#ibcon#read 5, iclass 11, count 0 2006.201.12:10:59.91#ibcon#about to read 6, iclass 11, count 0 2006.201.12:10:59.91#ibcon#read 6, iclass 11, count 0 2006.201.12:10:59.91#ibcon#end of sib2, iclass 11, count 0 2006.201.12:10:59.91#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:10:59.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:10:59.91#ibcon#[27=USB\r\n] 2006.201.12:10:59.91#ibcon#*before write, iclass 11, count 0 2006.201.12:10:59.91#ibcon#enter sib2, iclass 11, count 0 2006.201.12:10:59.91#ibcon#flushed, iclass 11, count 0 2006.201.12:10:59.91#ibcon#about to write, iclass 11, count 0 2006.201.12:10:59.91#ibcon#wrote, iclass 11, count 0 2006.201.12:10:59.91#ibcon#about to read 3, iclass 11, count 0 2006.201.12:10:59.94#ibcon#read 3, iclass 11, count 0 2006.201.12:10:59.94#ibcon#about to read 4, iclass 11, count 0 2006.201.12:10:59.94#ibcon#read 4, iclass 11, count 0 2006.201.12:10:59.94#ibcon#about to read 5, iclass 11, count 0 2006.201.12:10:59.94#ibcon#read 5, iclass 11, count 0 2006.201.12:10:59.94#ibcon#about to read 6, iclass 11, count 0 2006.201.12:10:59.94#ibcon#read 6, iclass 11, count 0 2006.201.12:10:59.94#ibcon#end of sib2, iclass 11, count 0 2006.201.12:10:59.94#ibcon#*after write, iclass 11, count 0 2006.201.12:10:59.94#ibcon#*before return 0, iclass 11, count 0 2006.201.12:10:59.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:10:59.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:10:59.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:10:59.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:10:59.94$vck44/vblo=5,709.99 2006.201.12:10:59.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.12:10:59.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.12:10:59.94#ibcon#ireg 17 cls_cnt 0 2006.201.12:10:59.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:10:59.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:10:59.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:10:59.94#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:10:59.94#ibcon#first serial, iclass 16, count 0 2006.201.12:10:59.94#ibcon#enter sib2, iclass 16, count 0 2006.201.12:10:59.94#ibcon#flushed, iclass 16, count 0 2006.201.12:10:59.94#ibcon#about to write, iclass 16, count 0 2006.201.12:10:59.94#ibcon#wrote, iclass 16, count 0 2006.201.12:10:59.94#ibcon#about to read 3, iclass 16, count 0 2006.201.12:10:59.96#ibcon#read 3, iclass 16, count 0 2006.201.12:10:59.96#ibcon#about to read 4, iclass 16, count 0 2006.201.12:10:59.96#ibcon#read 4, iclass 16, count 0 2006.201.12:10:59.96#ibcon#about to read 5, iclass 16, count 0 2006.201.12:10:59.96#ibcon#read 5, iclass 16, count 0 2006.201.12:10:59.96#ibcon#about to read 6, iclass 16, count 0 2006.201.12:10:59.96#ibcon#read 6, iclass 16, count 0 2006.201.12:10:59.96#ibcon#end of sib2, iclass 16, count 0 2006.201.12:10:59.96#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:10:59.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:10:59.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:10:59.96#ibcon#*before write, iclass 16, count 0 2006.201.12:10:59.96#ibcon#enter sib2, iclass 16, count 0 2006.201.12:10:59.96#ibcon#flushed, iclass 16, count 0 2006.201.12:10:59.96#ibcon#about to write, iclass 16, count 0 2006.201.12:10:59.96#ibcon#wrote, iclass 16, count 0 2006.201.12:10:59.96#ibcon#about to read 3, iclass 16, count 0 2006.201.12:11:00.00#ibcon#read 3, iclass 16, count 0 2006.201.12:11:00.00#ibcon#about to read 4, iclass 16, count 0 2006.201.12:11:00.00#ibcon#read 4, iclass 16, count 0 2006.201.12:11:00.00#ibcon#about to read 5, iclass 16, count 0 2006.201.12:11:00.00#ibcon#read 5, iclass 16, count 0 2006.201.12:11:00.00#ibcon#about to read 6, iclass 16, count 0 2006.201.12:11:00.00#ibcon#read 6, iclass 16, count 0 2006.201.12:11:00.00#ibcon#end of sib2, iclass 16, count 0 2006.201.12:11:00.00#ibcon#*after write, iclass 16, count 0 2006.201.12:11:00.00#ibcon#*before return 0, iclass 16, count 0 2006.201.12:11:00.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:11:00.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:11:00.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:11:00.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:11:00.00$vck44/vb=5,4 2006.201.12:11:00.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.12:11:00.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.12:11:00.00#ibcon#ireg 11 cls_cnt 2 2006.201.12:11:00.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:11:00.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:11:00.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:11:00.06#ibcon#enter wrdev, iclass 18, count 2 2006.201.12:11:00.06#ibcon#first serial, iclass 18, count 2 2006.201.12:11:00.06#ibcon#enter sib2, iclass 18, count 2 2006.201.12:11:00.06#ibcon#flushed, iclass 18, count 2 2006.201.12:11:00.06#ibcon#about to write, iclass 18, count 2 2006.201.12:11:00.06#ibcon#wrote, iclass 18, count 2 2006.201.12:11:00.06#ibcon#about to read 3, iclass 18, count 2 2006.201.12:11:00.08#ibcon#read 3, iclass 18, count 2 2006.201.12:11:00.08#ibcon#about to read 4, iclass 18, count 2 2006.201.12:11:00.08#ibcon#read 4, iclass 18, count 2 2006.201.12:11:00.08#ibcon#about to read 5, iclass 18, count 2 2006.201.12:11:00.08#ibcon#read 5, iclass 18, count 2 2006.201.12:11:00.08#ibcon#about to read 6, iclass 18, count 2 2006.201.12:11:00.08#ibcon#read 6, iclass 18, count 2 2006.201.12:11:00.08#ibcon#end of sib2, iclass 18, count 2 2006.201.12:11:00.08#ibcon#*mode == 0, iclass 18, count 2 2006.201.12:11:00.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.12:11:00.08#ibcon#[27=AT05-04\r\n] 2006.201.12:11:00.08#ibcon#*before write, iclass 18, count 2 2006.201.12:11:00.08#ibcon#enter sib2, iclass 18, count 2 2006.201.12:11:00.08#ibcon#flushed, iclass 18, count 2 2006.201.12:11:00.08#ibcon#about to write, iclass 18, count 2 2006.201.12:11:00.08#ibcon#wrote, iclass 18, count 2 2006.201.12:11:00.08#ibcon#about to read 3, iclass 18, count 2 2006.201.12:11:00.11#ibcon#read 3, iclass 18, count 2 2006.201.12:11:00.11#ibcon#about to read 4, iclass 18, count 2 2006.201.12:11:00.11#ibcon#read 4, iclass 18, count 2 2006.201.12:11:00.11#ibcon#about to read 5, iclass 18, count 2 2006.201.12:11:00.11#ibcon#read 5, iclass 18, count 2 2006.201.12:11:00.11#ibcon#about to read 6, iclass 18, count 2 2006.201.12:11:00.11#ibcon#read 6, iclass 18, count 2 2006.201.12:11:00.11#ibcon#end of sib2, iclass 18, count 2 2006.201.12:11:00.11#ibcon#*after write, iclass 18, count 2 2006.201.12:11:00.11#ibcon#*before return 0, iclass 18, count 2 2006.201.12:11:00.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:11:00.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:11:00.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.12:11:00.11#ibcon#ireg 7 cls_cnt 0 2006.201.12:11:00.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:11:00.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:11:00.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:11:00.23#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:11:00.23#ibcon#first serial, iclass 18, count 0 2006.201.12:11:00.23#ibcon#enter sib2, iclass 18, count 0 2006.201.12:11:00.23#ibcon#flushed, iclass 18, count 0 2006.201.12:11:00.23#ibcon#about to write, iclass 18, count 0 2006.201.12:11:00.23#ibcon#wrote, iclass 18, count 0 2006.201.12:11:00.23#ibcon#about to read 3, iclass 18, count 0 2006.201.12:11:00.25#ibcon#read 3, iclass 18, count 0 2006.201.12:11:00.25#ibcon#about to read 4, iclass 18, count 0 2006.201.12:11:00.25#ibcon#read 4, iclass 18, count 0 2006.201.12:11:00.25#ibcon#about to read 5, iclass 18, count 0 2006.201.12:11:00.25#ibcon#read 5, iclass 18, count 0 2006.201.12:11:00.25#ibcon#about to read 6, iclass 18, count 0 2006.201.12:11:00.25#ibcon#read 6, iclass 18, count 0 2006.201.12:11:00.25#ibcon#end of sib2, iclass 18, count 0 2006.201.12:11:00.25#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:11:00.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:11:00.25#ibcon#[27=USB\r\n] 2006.201.12:11:00.25#ibcon#*before write, iclass 18, count 0 2006.201.12:11:00.25#ibcon#enter sib2, iclass 18, count 0 2006.201.12:11:00.25#ibcon#flushed, iclass 18, count 0 2006.201.12:11:00.25#ibcon#about to write, iclass 18, count 0 2006.201.12:11:00.25#ibcon#wrote, iclass 18, count 0 2006.201.12:11:00.25#ibcon#about to read 3, iclass 18, count 0 2006.201.12:11:00.28#ibcon#read 3, iclass 18, count 0 2006.201.12:11:00.28#ibcon#about to read 4, iclass 18, count 0 2006.201.12:11:00.28#ibcon#read 4, iclass 18, count 0 2006.201.12:11:00.28#ibcon#about to read 5, iclass 18, count 0 2006.201.12:11:00.28#ibcon#read 5, iclass 18, count 0 2006.201.12:11:00.28#ibcon#about to read 6, iclass 18, count 0 2006.201.12:11:00.28#ibcon#read 6, iclass 18, count 0 2006.201.12:11:00.28#ibcon#end of sib2, iclass 18, count 0 2006.201.12:11:00.28#ibcon#*after write, iclass 18, count 0 2006.201.12:11:00.28#ibcon#*before return 0, iclass 18, count 0 2006.201.12:11:00.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:11:00.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:11:00.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:11:00.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:11:00.28$vck44/vblo=6,719.99 2006.201.12:11:00.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.12:11:00.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.12:11:00.28#ibcon#ireg 17 cls_cnt 0 2006.201.12:11:00.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:11:00.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:11:00.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:11:00.28#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:11:00.28#ibcon#first serial, iclass 20, count 0 2006.201.12:11:00.28#ibcon#enter sib2, iclass 20, count 0 2006.201.12:11:00.28#ibcon#flushed, iclass 20, count 0 2006.201.12:11:00.28#ibcon#about to write, iclass 20, count 0 2006.201.12:11:00.28#ibcon#wrote, iclass 20, count 0 2006.201.12:11:00.28#ibcon#about to read 3, iclass 20, count 0 2006.201.12:11:00.30#ibcon#read 3, iclass 20, count 0 2006.201.12:11:00.30#ibcon#about to read 4, iclass 20, count 0 2006.201.12:11:00.30#ibcon#read 4, iclass 20, count 0 2006.201.12:11:00.30#ibcon#about to read 5, iclass 20, count 0 2006.201.12:11:00.30#ibcon#read 5, iclass 20, count 0 2006.201.12:11:00.30#ibcon#about to read 6, iclass 20, count 0 2006.201.12:11:00.30#ibcon#read 6, iclass 20, count 0 2006.201.12:11:00.30#ibcon#end of sib2, iclass 20, count 0 2006.201.12:11:00.30#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:11:00.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:11:00.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:11:00.30#ibcon#*before write, iclass 20, count 0 2006.201.12:11:00.30#ibcon#enter sib2, iclass 20, count 0 2006.201.12:11:00.30#ibcon#flushed, iclass 20, count 0 2006.201.12:11:00.30#ibcon#about to write, iclass 20, count 0 2006.201.12:11:00.30#ibcon#wrote, iclass 20, count 0 2006.201.12:11:00.30#ibcon#about to read 3, iclass 20, count 0 2006.201.12:11:00.34#ibcon#read 3, iclass 20, count 0 2006.201.12:11:00.34#ibcon#about to read 4, iclass 20, count 0 2006.201.12:11:00.34#ibcon#read 4, iclass 20, count 0 2006.201.12:11:00.34#ibcon#about to read 5, iclass 20, count 0 2006.201.12:11:00.34#ibcon#read 5, iclass 20, count 0 2006.201.12:11:00.34#ibcon#about to read 6, iclass 20, count 0 2006.201.12:11:00.34#ibcon#read 6, iclass 20, count 0 2006.201.12:11:00.34#ibcon#end of sib2, iclass 20, count 0 2006.201.12:11:00.34#ibcon#*after write, iclass 20, count 0 2006.201.12:11:00.34#ibcon#*before return 0, iclass 20, count 0 2006.201.12:11:00.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:11:00.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:11:00.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:11:00.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:11:00.34$vck44/vb=6,4 2006.201.12:11:00.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.12:11:00.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.12:11:00.34#ibcon#ireg 11 cls_cnt 2 2006.201.12:11:00.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:11:00.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:11:00.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:11:00.40#ibcon#enter wrdev, iclass 22, count 2 2006.201.12:11:00.40#ibcon#first serial, iclass 22, count 2 2006.201.12:11:00.40#ibcon#enter sib2, iclass 22, count 2 2006.201.12:11:00.40#ibcon#flushed, iclass 22, count 2 2006.201.12:11:00.40#ibcon#about to write, iclass 22, count 2 2006.201.12:11:00.40#ibcon#wrote, iclass 22, count 2 2006.201.12:11:00.40#ibcon#about to read 3, iclass 22, count 2 2006.201.12:11:00.42#ibcon#read 3, iclass 22, count 2 2006.201.12:11:00.42#ibcon#about to read 4, iclass 22, count 2 2006.201.12:11:00.42#ibcon#read 4, iclass 22, count 2 2006.201.12:11:00.42#ibcon#about to read 5, iclass 22, count 2 2006.201.12:11:00.42#ibcon#read 5, iclass 22, count 2 2006.201.12:11:00.42#ibcon#about to read 6, iclass 22, count 2 2006.201.12:11:00.42#ibcon#read 6, iclass 22, count 2 2006.201.12:11:00.42#ibcon#end of sib2, iclass 22, count 2 2006.201.12:11:00.42#ibcon#*mode == 0, iclass 22, count 2 2006.201.12:11:00.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.12:11:00.42#ibcon#[27=AT06-04\r\n] 2006.201.12:11:00.42#ibcon#*before write, iclass 22, count 2 2006.201.12:11:00.42#ibcon#enter sib2, iclass 22, count 2 2006.201.12:11:00.42#ibcon#flushed, iclass 22, count 2 2006.201.12:11:00.42#ibcon#about to write, iclass 22, count 2 2006.201.12:11:00.42#ibcon#wrote, iclass 22, count 2 2006.201.12:11:00.42#ibcon#about to read 3, iclass 22, count 2 2006.201.12:11:00.45#ibcon#read 3, iclass 22, count 2 2006.201.12:11:00.45#ibcon#about to read 4, iclass 22, count 2 2006.201.12:11:00.45#ibcon#read 4, iclass 22, count 2 2006.201.12:11:00.45#ibcon#about to read 5, iclass 22, count 2 2006.201.12:11:00.45#ibcon#read 5, iclass 22, count 2 2006.201.12:11:00.45#ibcon#about to read 6, iclass 22, count 2 2006.201.12:11:00.45#ibcon#read 6, iclass 22, count 2 2006.201.12:11:00.45#ibcon#end of sib2, iclass 22, count 2 2006.201.12:11:00.45#ibcon#*after write, iclass 22, count 2 2006.201.12:11:00.45#ibcon#*before return 0, iclass 22, count 2 2006.201.12:11:00.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:11:00.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:11:00.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.12:11:00.45#ibcon#ireg 7 cls_cnt 0 2006.201.12:11:00.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:11:00.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:11:00.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:11:00.57#ibcon#enter wrdev, iclass 22, count 0 2006.201.12:11:00.57#ibcon#first serial, iclass 22, count 0 2006.201.12:11:00.57#ibcon#enter sib2, iclass 22, count 0 2006.201.12:11:00.57#ibcon#flushed, iclass 22, count 0 2006.201.12:11:00.57#ibcon#about to write, iclass 22, count 0 2006.201.12:11:00.57#ibcon#wrote, iclass 22, count 0 2006.201.12:11:00.57#ibcon#about to read 3, iclass 22, count 0 2006.201.12:11:00.59#ibcon#read 3, iclass 22, count 0 2006.201.12:11:00.59#ibcon#about to read 4, iclass 22, count 0 2006.201.12:11:00.59#ibcon#read 4, iclass 22, count 0 2006.201.12:11:00.59#ibcon#about to read 5, iclass 22, count 0 2006.201.12:11:00.59#ibcon#read 5, iclass 22, count 0 2006.201.12:11:00.59#ibcon#about to read 6, iclass 22, count 0 2006.201.12:11:00.59#ibcon#read 6, iclass 22, count 0 2006.201.12:11:00.59#ibcon#end of sib2, iclass 22, count 0 2006.201.12:11:00.59#ibcon#*mode == 0, iclass 22, count 0 2006.201.12:11:00.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.12:11:00.59#ibcon#[27=USB\r\n] 2006.201.12:11:00.59#ibcon#*before write, iclass 22, count 0 2006.201.12:11:00.59#ibcon#enter sib2, iclass 22, count 0 2006.201.12:11:00.59#ibcon#flushed, iclass 22, count 0 2006.201.12:11:00.59#ibcon#about to write, iclass 22, count 0 2006.201.12:11:00.59#ibcon#wrote, iclass 22, count 0 2006.201.12:11:00.59#ibcon#about to read 3, iclass 22, count 0 2006.201.12:11:00.62#ibcon#read 3, iclass 22, count 0 2006.201.12:11:00.62#ibcon#about to read 4, iclass 22, count 0 2006.201.12:11:00.62#ibcon#read 4, iclass 22, count 0 2006.201.12:11:00.62#ibcon#about to read 5, iclass 22, count 0 2006.201.12:11:00.62#ibcon#read 5, iclass 22, count 0 2006.201.12:11:00.62#ibcon#about to read 6, iclass 22, count 0 2006.201.12:11:00.62#ibcon#read 6, iclass 22, count 0 2006.201.12:11:00.62#ibcon#end of sib2, iclass 22, count 0 2006.201.12:11:00.62#ibcon#*after write, iclass 22, count 0 2006.201.12:11:00.62#ibcon#*before return 0, iclass 22, count 0 2006.201.12:11:00.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:11:00.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:11:00.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.12:11:00.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.12:11:00.62$vck44/vblo=7,734.99 2006.201.12:11:00.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.12:11:00.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.12:11:00.62#ibcon#ireg 17 cls_cnt 0 2006.201.12:11:00.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:11:00.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:11:00.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:11:00.62#ibcon#enter wrdev, iclass 24, count 0 2006.201.12:11:00.62#ibcon#first serial, iclass 24, count 0 2006.201.12:11:00.62#ibcon#enter sib2, iclass 24, count 0 2006.201.12:11:00.62#ibcon#flushed, iclass 24, count 0 2006.201.12:11:00.62#ibcon#about to write, iclass 24, count 0 2006.201.12:11:00.62#ibcon#wrote, iclass 24, count 0 2006.201.12:11:00.62#ibcon#about to read 3, iclass 24, count 0 2006.201.12:11:00.64#ibcon#read 3, iclass 24, count 0 2006.201.12:11:00.64#ibcon#about to read 4, iclass 24, count 0 2006.201.12:11:00.64#ibcon#read 4, iclass 24, count 0 2006.201.12:11:00.64#ibcon#about to read 5, iclass 24, count 0 2006.201.12:11:00.64#ibcon#read 5, iclass 24, count 0 2006.201.12:11:00.64#ibcon#about to read 6, iclass 24, count 0 2006.201.12:11:00.64#ibcon#read 6, iclass 24, count 0 2006.201.12:11:00.64#ibcon#end of sib2, iclass 24, count 0 2006.201.12:11:00.64#ibcon#*mode == 0, iclass 24, count 0 2006.201.12:11:00.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.12:11:00.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:11:00.64#ibcon#*before write, iclass 24, count 0 2006.201.12:11:00.64#ibcon#enter sib2, iclass 24, count 0 2006.201.12:11:00.64#ibcon#flushed, iclass 24, count 0 2006.201.12:11:00.64#ibcon#about to write, iclass 24, count 0 2006.201.12:11:00.64#ibcon#wrote, iclass 24, count 0 2006.201.12:11:00.64#ibcon#about to read 3, iclass 24, count 0 2006.201.12:11:00.68#ibcon#read 3, iclass 24, count 0 2006.201.12:11:00.68#ibcon#about to read 4, iclass 24, count 0 2006.201.12:11:00.68#ibcon#read 4, iclass 24, count 0 2006.201.12:11:00.68#ibcon#about to read 5, iclass 24, count 0 2006.201.12:11:00.68#ibcon#read 5, iclass 24, count 0 2006.201.12:11:00.68#ibcon#about to read 6, iclass 24, count 0 2006.201.12:11:00.68#ibcon#read 6, iclass 24, count 0 2006.201.12:11:00.68#ibcon#end of sib2, iclass 24, count 0 2006.201.12:11:00.68#ibcon#*after write, iclass 24, count 0 2006.201.12:11:00.68#ibcon#*before return 0, iclass 24, count 0 2006.201.12:11:00.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:11:00.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:11:00.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.12:11:00.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.12:11:00.68$vck44/vb=7,4 2006.201.12:11:00.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.12:11:00.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.12:11:00.68#ibcon#ireg 11 cls_cnt 2 2006.201.12:11:00.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:11:00.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:11:00.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:11:00.74#ibcon#enter wrdev, iclass 26, count 2 2006.201.12:11:00.74#ibcon#first serial, iclass 26, count 2 2006.201.12:11:00.74#ibcon#enter sib2, iclass 26, count 2 2006.201.12:11:00.74#ibcon#flushed, iclass 26, count 2 2006.201.12:11:00.74#ibcon#about to write, iclass 26, count 2 2006.201.12:11:00.74#ibcon#wrote, iclass 26, count 2 2006.201.12:11:00.74#ibcon#about to read 3, iclass 26, count 2 2006.201.12:11:00.76#ibcon#read 3, iclass 26, count 2 2006.201.12:11:00.76#ibcon#about to read 4, iclass 26, count 2 2006.201.12:11:00.76#ibcon#read 4, iclass 26, count 2 2006.201.12:11:00.76#ibcon#about to read 5, iclass 26, count 2 2006.201.12:11:00.76#ibcon#read 5, iclass 26, count 2 2006.201.12:11:00.76#ibcon#about to read 6, iclass 26, count 2 2006.201.12:11:00.76#ibcon#read 6, iclass 26, count 2 2006.201.12:11:00.76#ibcon#end of sib2, iclass 26, count 2 2006.201.12:11:00.76#ibcon#*mode == 0, iclass 26, count 2 2006.201.12:11:00.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.12:11:00.76#ibcon#[27=AT07-04\r\n] 2006.201.12:11:00.76#ibcon#*before write, iclass 26, count 2 2006.201.12:11:00.76#ibcon#enter sib2, iclass 26, count 2 2006.201.12:11:00.76#ibcon#flushed, iclass 26, count 2 2006.201.12:11:00.76#ibcon#about to write, iclass 26, count 2 2006.201.12:11:00.76#ibcon#wrote, iclass 26, count 2 2006.201.12:11:00.76#ibcon#about to read 3, iclass 26, count 2 2006.201.12:11:00.79#ibcon#read 3, iclass 26, count 2 2006.201.12:11:00.79#ibcon#about to read 4, iclass 26, count 2 2006.201.12:11:00.79#ibcon#read 4, iclass 26, count 2 2006.201.12:11:00.79#ibcon#about to read 5, iclass 26, count 2 2006.201.12:11:00.79#ibcon#read 5, iclass 26, count 2 2006.201.12:11:00.79#ibcon#about to read 6, iclass 26, count 2 2006.201.12:11:00.79#ibcon#read 6, iclass 26, count 2 2006.201.12:11:00.79#ibcon#end of sib2, iclass 26, count 2 2006.201.12:11:00.79#ibcon#*after write, iclass 26, count 2 2006.201.12:11:00.79#ibcon#*before return 0, iclass 26, count 2 2006.201.12:11:00.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:11:00.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:11:00.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.12:11:00.79#ibcon#ireg 7 cls_cnt 0 2006.201.12:11:00.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:11:00.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:11:00.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:11:00.91#ibcon#enter wrdev, iclass 26, count 0 2006.201.12:11:00.91#ibcon#first serial, iclass 26, count 0 2006.201.12:11:00.91#ibcon#enter sib2, iclass 26, count 0 2006.201.12:11:00.91#ibcon#flushed, iclass 26, count 0 2006.201.12:11:00.91#ibcon#about to write, iclass 26, count 0 2006.201.12:11:00.91#ibcon#wrote, iclass 26, count 0 2006.201.12:11:00.91#ibcon#about to read 3, iclass 26, count 0 2006.201.12:11:00.93#ibcon#read 3, iclass 26, count 0 2006.201.12:11:00.93#ibcon#about to read 4, iclass 26, count 0 2006.201.12:11:00.93#ibcon#read 4, iclass 26, count 0 2006.201.12:11:00.93#ibcon#about to read 5, iclass 26, count 0 2006.201.12:11:00.93#ibcon#read 5, iclass 26, count 0 2006.201.12:11:00.93#ibcon#about to read 6, iclass 26, count 0 2006.201.12:11:00.93#ibcon#read 6, iclass 26, count 0 2006.201.12:11:00.93#ibcon#end of sib2, iclass 26, count 0 2006.201.12:11:00.93#ibcon#*mode == 0, iclass 26, count 0 2006.201.12:11:00.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.12:11:00.93#ibcon#[27=USB\r\n] 2006.201.12:11:00.93#ibcon#*before write, iclass 26, count 0 2006.201.12:11:00.93#ibcon#enter sib2, iclass 26, count 0 2006.201.12:11:00.93#ibcon#flushed, iclass 26, count 0 2006.201.12:11:00.93#ibcon#about to write, iclass 26, count 0 2006.201.12:11:00.93#ibcon#wrote, iclass 26, count 0 2006.201.12:11:00.93#ibcon#about to read 3, iclass 26, count 0 2006.201.12:11:00.96#ibcon#read 3, iclass 26, count 0 2006.201.12:11:00.96#ibcon#about to read 4, iclass 26, count 0 2006.201.12:11:00.96#ibcon#read 4, iclass 26, count 0 2006.201.12:11:00.96#ibcon#about to read 5, iclass 26, count 0 2006.201.12:11:00.96#ibcon#read 5, iclass 26, count 0 2006.201.12:11:00.96#ibcon#about to read 6, iclass 26, count 0 2006.201.12:11:00.96#ibcon#read 6, iclass 26, count 0 2006.201.12:11:00.96#ibcon#end of sib2, iclass 26, count 0 2006.201.12:11:00.96#ibcon#*after write, iclass 26, count 0 2006.201.12:11:00.96#ibcon#*before return 0, iclass 26, count 0 2006.201.12:11:00.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:11:00.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:11:00.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.12:11:00.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.12:11:00.96$vck44/vblo=8,744.99 2006.201.12:11:00.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.12:11:00.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.12:11:00.96#ibcon#ireg 17 cls_cnt 0 2006.201.12:11:00.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:11:00.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:11:00.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:11:00.96#ibcon#enter wrdev, iclass 28, count 0 2006.201.12:11:00.96#ibcon#first serial, iclass 28, count 0 2006.201.12:11:00.96#ibcon#enter sib2, iclass 28, count 0 2006.201.12:11:00.96#ibcon#flushed, iclass 28, count 0 2006.201.12:11:00.96#ibcon#about to write, iclass 28, count 0 2006.201.12:11:00.96#ibcon#wrote, iclass 28, count 0 2006.201.12:11:00.96#ibcon#about to read 3, iclass 28, count 0 2006.201.12:11:00.98#ibcon#read 3, iclass 28, count 0 2006.201.12:11:00.98#ibcon#about to read 4, iclass 28, count 0 2006.201.12:11:00.98#ibcon#read 4, iclass 28, count 0 2006.201.12:11:00.98#ibcon#about to read 5, iclass 28, count 0 2006.201.12:11:00.98#ibcon#read 5, iclass 28, count 0 2006.201.12:11:00.98#ibcon#about to read 6, iclass 28, count 0 2006.201.12:11:00.98#ibcon#read 6, iclass 28, count 0 2006.201.12:11:00.98#ibcon#end of sib2, iclass 28, count 0 2006.201.12:11:00.98#ibcon#*mode == 0, iclass 28, count 0 2006.201.12:11:00.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.12:11:00.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:11:00.98#ibcon#*before write, iclass 28, count 0 2006.201.12:11:00.98#ibcon#enter sib2, iclass 28, count 0 2006.201.12:11:00.98#ibcon#flushed, iclass 28, count 0 2006.201.12:11:00.98#ibcon#about to write, iclass 28, count 0 2006.201.12:11:00.98#ibcon#wrote, iclass 28, count 0 2006.201.12:11:00.98#ibcon#about to read 3, iclass 28, count 0 2006.201.12:11:01.02#ibcon#read 3, iclass 28, count 0 2006.201.12:11:01.02#ibcon#about to read 4, iclass 28, count 0 2006.201.12:11:01.02#ibcon#read 4, iclass 28, count 0 2006.201.12:11:01.02#ibcon#about to read 5, iclass 28, count 0 2006.201.12:11:01.02#ibcon#read 5, iclass 28, count 0 2006.201.12:11:01.02#ibcon#about to read 6, iclass 28, count 0 2006.201.12:11:01.02#ibcon#read 6, iclass 28, count 0 2006.201.12:11:01.02#ibcon#end of sib2, iclass 28, count 0 2006.201.12:11:01.02#ibcon#*after write, iclass 28, count 0 2006.201.12:11:01.02#ibcon#*before return 0, iclass 28, count 0 2006.201.12:11:01.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:11:01.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:11:01.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.12:11:01.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.12:11:01.02$vck44/vb=8,4 2006.201.12:11:01.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.12:11:01.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.12:11:01.02#ibcon#ireg 11 cls_cnt 2 2006.201.12:11:01.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:11:01.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:11:01.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:11:01.08#ibcon#enter wrdev, iclass 30, count 2 2006.201.12:11:01.08#ibcon#first serial, iclass 30, count 2 2006.201.12:11:01.08#ibcon#enter sib2, iclass 30, count 2 2006.201.12:11:01.08#ibcon#flushed, iclass 30, count 2 2006.201.12:11:01.08#ibcon#about to write, iclass 30, count 2 2006.201.12:11:01.08#ibcon#wrote, iclass 30, count 2 2006.201.12:11:01.08#ibcon#about to read 3, iclass 30, count 2 2006.201.12:11:01.10#ibcon#read 3, iclass 30, count 2 2006.201.12:11:01.10#ibcon#about to read 4, iclass 30, count 2 2006.201.12:11:01.10#ibcon#read 4, iclass 30, count 2 2006.201.12:11:01.10#ibcon#about to read 5, iclass 30, count 2 2006.201.12:11:01.10#ibcon#read 5, iclass 30, count 2 2006.201.12:11:01.10#ibcon#about to read 6, iclass 30, count 2 2006.201.12:11:01.10#ibcon#read 6, iclass 30, count 2 2006.201.12:11:01.10#ibcon#end of sib2, iclass 30, count 2 2006.201.12:11:01.10#ibcon#*mode == 0, iclass 30, count 2 2006.201.12:11:01.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.12:11:01.10#ibcon#[27=AT08-04\r\n] 2006.201.12:11:01.10#ibcon#*before write, iclass 30, count 2 2006.201.12:11:01.10#ibcon#enter sib2, iclass 30, count 2 2006.201.12:11:01.10#ibcon#flushed, iclass 30, count 2 2006.201.12:11:01.10#ibcon#about to write, iclass 30, count 2 2006.201.12:11:01.10#ibcon#wrote, iclass 30, count 2 2006.201.12:11:01.10#ibcon#about to read 3, iclass 30, count 2 2006.201.12:11:01.13#ibcon#read 3, iclass 30, count 2 2006.201.12:11:01.13#ibcon#about to read 4, iclass 30, count 2 2006.201.12:11:01.13#ibcon#read 4, iclass 30, count 2 2006.201.12:11:01.13#ibcon#about to read 5, iclass 30, count 2 2006.201.12:11:01.13#ibcon#read 5, iclass 30, count 2 2006.201.12:11:01.13#ibcon#about to read 6, iclass 30, count 2 2006.201.12:11:01.13#ibcon#read 6, iclass 30, count 2 2006.201.12:11:01.13#ibcon#end of sib2, iclass 30, count 2 2006.201.12:11:01.13#ibcon#*after write, iclass 30, count 2 2006.201.12:11:01.13#ibcon#*before return 0, iclass 30, count 2 2006.201.12:11:01.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:11:01.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:11:01.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.12:11:01.13#ibcon#ireg 7 cls_cnt 0 2006.201.12:11:01.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:11:01.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:11:01.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:11:01.25#ibcon#enter wrdev, iclass 30, count 0 2006.201.12:11:01.25#ibcon#first serial, iclass 30, count 0 2006.201.12:11:01.25#ibcon#enter sib2, iclass 30, count 0 2006.201.12:11:01.25#ibcon#flushed, iclass 30, count 0 2006.201.12:11:01.25#ibcon#about to write, iclass 30, count 0 2006.201.12:11:01.25#ibcon#wrote, iclass 30, count 0 2006.201.12:11:01.25#ibcon#about to read 3, iclass 30, count 0 2006.201.12:11:01.27#ibcon#read 3, iclass 30, count 0 2006.201.12:11:01.27#ibcon#about to read 4, iclass 30, count 0 2006.201.12:11:01.27#ibcon#read 4, iclass 30, count 0 2006.201.12:11:01.27#ibcon#about to read 5, iclass 30, count 0 2006.201.12:11:01.27#ibcon#read 5, iclass 30, count 0 2006.201.12:11:01.27#ibcon#about to read 6, iclass 30, count 0 2006.201.12:11:01.27#ibcon#read 6, iclass 30, count 0 2006.201.12:11:01.27#ibcon#end of sib2, iclass 30, count 0 2006.201.12:11:01.27#ibcon#*mode == 0, iclass 30, count 0 2006.201.12:11:01.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.12:11:01.27#ibcon#[27=USB\r\n] 2006.201.12:11:01.27#ibcon#*before write, iclass 30, count 0 2006.201.12:11:01.27#ibcon#enter sib2, iclass 30, count 0 2006.201.12:11:01.27#ibcon#flushed, iclass 30, count 0 2006.201.12:11:01.27#ibcon#about to write, iclass 30, count 0 2006.201.12:11:01.27#ibcon#wrote, iclass 30, count 0 2006.201.12:11:01.27#ibcon#about to read 3, iclass 30, count 0 2006.201.12:11:01.30#ibcon#read 3, iclass 30, count 0 2006.201.12:11:01.30#ibcon#about to read 4, iclass 30, count 0 2006.201.12:11:01.30#ibcon#read 4, iclass 30, count 0 2006.201.12:11:01.30#ibcon#about to read 5, iclass 30, count 0 2006.201.12:11:01.30#ibcon#read 5, iclass 30, count 0 2006.201.12:11:01.30#ibcon#about to read 6, iclass 30, count 0 2006.201.12:11:01.30#ibcon#read 6, iclass 30, count 0 2006.201.12:11:01.30#ibcon#end of sib2, iclass 30, count 0 2006.201.12:11:01.30#ibcon#*after write, iclass 30, count 0 2006.201.12:11:01.30#ibcon#*before return 0, iclass 30, count 0 2006.201.12:11:01.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:11:01.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:11:01.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.12:11:01.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.12:11:01.30$vck44/vabw=wide 2006.201.12:11:01.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.12:11:01.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.12:11:01.30#ibcon#ireg 8 cls_cnt 0 2006.201.12:11:01.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:11:01.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:11:01.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:11:01.30#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:11:01.30#ibcon#first serial, iclass 32, count 0 2006.201.12:11:01.30#ibcon#enter sib2, iclass 32, count 0 2006.201.12:11:01.30#ibcon#flushed, iclass 32, count 0 2006.201.12:11:01.30#ibcon#about to write, iclass 32, count 0 2006.201.12:11:01.30#ibcon#wrote, iclass 32, count 0 2006.201.12:11:01.30#ibcon#about to read 3, iclass 32, count 0 2006.201.12:11:01.32#ibcon#read 3, iclass 32, count 0 2006.201.12:11:01.32#ibcon#about to read 4, iclass 32, count 0 2006.201.12:11:01.32#ibcon#read 4, iclass 32, count 0 2006.201.12:11:01.32#ibcon#about to read 5, iclass 32, count 0 2006.201.12:11:01.32#ibcon#read 5, iclass 32, count 0 2006.201.12:11:01.32#ibcon#about to read 6, iclass 32, count 0 2006.201.12:11:01.32#ibcon#read 6, iclass 32, count 0 2006.201.12:11:01.32#ibcon#end of sib2, iclass 32, count 0 2006.201.12:11:01.32#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:11:01.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:11:01.32#ibcon#[25=BW32\r\n] 2006.201.12:11:01.32#ibcon#*before write, iclass 32, count 0 2006.201.12:11:01.32#ibcon#enter sib2, iclass 32, count 0 2006.201.12:11:01.32#ibcon#flushed, iclass 32, count 0 2006.201.12:11:01.32#ibcon#about to write, iclass 32, count 0 2006.201.12:11:01.32#ibcon#wrote, iclass 32, count 0 2006.201.12:11:01.32#ibcon#about to read 3, iclass 32, count 0 2006.201.12:11:01.35#ibcon#read 3, iclass 32, count 0 2006.201.12:11:01.35#ibcon#about to read 4, iclass 32, count 0 2006.201.12:11:01.35#ibcon#read 4, iclass 32, count 0 2006.201.12:11:01.35#ibcon#about to read 5, iclass 32, count 0 2006.201.12:11:01.35#ibcon#read 5, iclass 32, count 0 2006.201.12:11:01.35#ibcon#about to read 6, iclass 32, count 0 2006.201.12:11:01.35#ibcon#read 6, iclass 32, count 0 2006.201.12:11:01.35#ibcon#end of sib2, iclass 32, count 0 2006.201.12:11:01.35#ibcon#*after write, iclass 32, count 0 2006.201.12:11:01.35#ibcon#*before return 0, iclass 32, count 0 2006.201.12:11:01.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:11:01.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:11:01.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:11:01.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:11:01.35$vck44/vbbw=wide 2006.201.12:11:01.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.12:11:01.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.12:11:01.35#ibcon#ireg 8 cls_cnt 0 2006.201.12:11:01.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:11:01.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:11:01.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:11:01.42#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:11:01.42#ibcon#first serial, iclass 34, count 0 2006.201.12:11:01.42#ibcon#enter sib2, iclass 34, count 0 2006.201.12:11:01.42#ibcon#flushed, iclass 34, count 0 2006.201.12:11:01.42#ibcon#about to write, iclass 34, count 0 2006.201.12:11:01.42#ibcon#wrote, iclass 34, count 0 2006.201.12:11:01.42#ibcon#about to read 3, iclass 34, count 0 2006.201.12:11:01.44#ibcon#read 3, iclass 34, count 0 2006.201.12:11:01.44#ibcon#about to read 4, iclass 34, count 0 2006.201.12:11:01.44#ibcon#read 4, iclass 34, count 0 2006.201.12:11:01.44#ibcon#about to read 5, iclass 34, count 0 2006.201.12:11:01.44#ibcon#read 5, iclass 34, count 0 2006.201.12:11:01.44#ibcon#about to read 6, iclass 34, count 0 2006.201.12:11:01.44#ibcon#read 6, iclass 34, count 0 2006.201.12:11:01.44#ibcon#end of sib2, iclass 34, count 0 2006.201.12:11:01.44#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:11:01.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:11:01.44#ibcon#[27=BW32\r\n] 2006.201.12:11:01.44#ibcon#*before write, iclass 34, count 0 2006.201.12:11:01.44#ibcon#enter sib2, iclass 34, count 0 2006.201.12:11:01.44#ibcon#flushed, iclass 34, count 0 2006.201.12:11:01.44#ibcon#about to write, iclass 34, count 0 2006.201.12:11:01.44#ibcon#wrote, iclass 34, count 0 2006.201.12:11:01.44#ibcon#about to read 3, iclass 34, count 0 2006.201.12:11:01.47#ibcon#read 3, iclass 34, count 0 2006.201.12:11:01.47#ibcon#about to read 4, iclass 34, count 0 2006.201.12:11:01.47#ibcon#read 4, iclass 34, count 0 2006.201.12:11:01.47#ibcon#about to read 5, iclass 34, count 0 2006.201.12:11:01.47#ibcon#read 5, iclass 34, count 0 2006.201.12:11:01.47#ibcon#about to read 6, iclass 34, count 0 2006.201.12:11:01.47#ibcon#read 6, iclass 34, count 0 2006.201.12:11:01.47#ibcon#end of sib2, iclass 34, count 0 2006.201.12:11:01.47#ibcon#*after write, iclass 34, count 0 2006.201.12:11:01.47#ibcon#*before return 0, iclass 34, count 0 2006.201.12:11:01.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:11:01.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:11:01.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:11:01.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:11:01.47$setupk4/ifdk4 2006.201.12:11:01.47$ifdk4/lo= 2006.201.12:11:01.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:11:01.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:11:01.47$ifdk4/patch= 2006.201.12:11:01.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:11:01.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:11:01.47$setupk4/!*+20s 2006.201.12:11:06.14#trakl#Source acquired 2006.201.12:11:06.14#flagr#flagr/antenna,acquired 2006.201.12:11:09.86#abcon#<5=/04 1.9 3.8 21.231001003.9\r\n> 2006.201.12:11:09.88#abcon#{5=INTERFACE CLEAR} 2006.201.12:11:09.94#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:11:15.93$setupk4/"tpicd 2006.201.12:11:15.93$setupk4/echo=off 2006.201.12:11:15.93$setupk4/xlog=off 2006.201.12:11:15.93:!2006.201.12:11:22 2006.201.12:11:22.00:preob 2006.201.12:11:22.14/onsource/TRACKING 2006.201.12:11:22.14:!2006.201.12:11:32 2006.201.12:11:32.00:"tape 2006.201.12:11:32.00:"st=record 2006.201.12:11:32.00:data_valid=on 2006.201.12:11:32.00:midob 2006.201.12:11:33.14/onsource/TRACKING 2006.201.12:11:33.14/wx/21.23,1003.9,100 2006.201.12:11:33.33/cable/+6.4725E-03 2006.201.12:11:34.42/va/01,08,usb,yes,36,39 2006.201.12:11:34.42/va/02,07,usb,yes,39,40 2006.201.12:11:34.42/va/03,08,usb,yes,35,37 2006.201.12:11:34.42/va/04,07,usb,yes,40,42 2006.201.12:11:34.42/va/05,04,usb,yes,36,36 2006.201.12:11:34.42/va/06,05,usb,yes,36,36 2006.201.12:11:34.42/va/07,05,usb,yes,35,36 2006.201.12:11:34.42/va/08,04,usb,yes,35,41 2006.201.12:11:34.65/valo/01,524.99,yes,locked 2006.201.12:11:34.65/valo/02,534.99,yes,locked 2006.201.12:11:34.65/valo/03,564.99,yes,locked 2006.201.12:11:34.65/valo/04,624.99,yes,locked 2006.201.12:11:34.65/valo/05,734.99,yes,locked 2006.201.12:11:34.65/valo/06,814.99,yes,locked 2006.201.12:11:34.65/valo/07,864.99,yes,locked 2006.201.12:11:34.65/valo/08,884.99,yes,locked 2006.201.12:11:35.74/vb/01,04,usb,yes,31,35 2006.201.12:11:35.74/vb/02,05,usb,yes,30,36 2006.201.12:11:35.74/vb/03,04,usb,yes,31,35 2006.201.12:11:35.74/vb/04,05,usb,yes,31,30 2006.201.12:11:35.74/vb/05,04,usb,yes,28,30 2006.201.12:11:35.74/vb/06,04,usb,yes,32,28 2006.201.12:11:35.74/vb/07,04,usb,yes,32,32 2006.201.12:11:35.74/vb/08,04,usb,yes,30,33 2006.201.12:11:35.97/vblo/01,629.99,yes,locked 2006.201.12:11:35.97/vblo/02,634.99,yes,locked 2006.201.12:11:35.97/vblo/03,649.99,yes,locked 2006.201.12:11:35.97/vblo/04,679.99,yes,locked 2006.201.12:11:35.97/vblo/05,709.99,yes,locked 2006.201.12:11:35.97/vblo/06,719.99,yes,locked 2006.201.12:11:35.97/vblo/07,734.99,yes,locked 2006.201.12:11:35.97/vblo/08,744.99,yes,locked 2006.201.12:11:36.12/vabw/8 2006.201.12:11:36.27/vbbw/8 2006.201.12:11:36.36/xfe/off,on,14.7 2006.201.12:11:36.74/ifatt/23,28,28,28 2006.201.12:11:37.06/fmout-gps/S +4.59E-07 2006.201.12:11:37.10:!2006.201.12:12:12 2006.201.12:12:12.00:data_valid=off 2006.201.12:12:12.00:"et 2006.201.12:12:12.00:!+3s 2006.201.12:12:15.02:"tape 2006.201.12:12:15.02:postob 2006.201.12:12:15.13/cable/+6.4723E-03 2006.201.12:12:15.13/wx/21.23,1003.9,100 2006.201.12:12:15.21/fmout-gps/S +4.58E-07 2006.201.12:12:15.21:scan_name=201-1220,jd0607,40 2006.201.12:12:15.22:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.201.12:12:17.14#flagr#flagr/antenna,new-source 2006.201.12:12:17.14:checkk5 2006.201.12:12:17.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:12:17.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:12:18.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:12:18.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:12:18.99/chk_obsdata//k5ts1/T2011211??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:12:19.36/chk_obsdata//k5ts2/T2011211??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:12:19.72/chk_obsdata//k5ts3/T2011211??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:12:20.09/chk_obsdata//k5ts4/T2011211??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:12:20.78/k5log//k5ts1_log_newline 2006.201.12:12:21.48/k5log//k5ts2_log_newline 2006.201.12:12:22.16/k5log//k5ts3_log_newline 2006.201.12:12:22.86/k5log//k5ts4_log_newline 2006.201.12:12:22.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:12:22.88:setupk4=1 2006.201.12:12:22.88$setupk4/echo=on 2006.201.12:12:22.88$setupk4/pcalon 2006.201.12:12:22.88$pcalon/"no phase cal control is implemented here 2006.201.12:12:22.88$setupk4/"tpicd=stop 2006.201.12:12:22.88$setupk4/"rec=synch_on 2006.201.12:12:22.88$setupk4/"rec_mode=128 2006.201.12:12:22.88$setupk4/!* 2006.201.12:12:22.88$setupk4/recpk4 2006.201.12:12:22.88$recpk4/recpatch= 2006.201.12:12:22.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:12:22.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:12:22.89$setupk4/vck44 2006.201.12:12:22.89$vck44/valo=1,524.99 2006.201.12:12:22.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.12:12:22.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.12:12:22.89#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:22.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:22.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:22.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:22.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:12:22.89#ibcon#first serial, iclass 35, count 0 2006.201.12:12:22.89#ibcon#enter sib2, iclass 35, count 0 2006.201.12:12:22.89#ibcon#flushed, iclass 35, count 0 2006.201.12:12:22.89#ibcon#about to write, iclass 35, count 0 2006.201.12:12:22.89#ibcon#wrote, iclass 35, count 0 2006.201.12:12:22.89#ibcon#about to read 3, iclass 35, count 0 2006.201.12:12:22.93#ibcon#read 3, iclass 35, count 0 2006.201.12:12:22.93#ibcon#about to read 4, iclass 35, count 0 2006.201.12:12:22.93#ibcon#read 4, iclass 35, count 0 2006.201.12:12:22.93#ibcon#about to read 5, iclass 35, count 0 2006.201.12:12:22.93#ibcon#read 5, iclass 35, count 0 2006.201.12:12:22.93#ibcon#about to read 6, iclass 35, count 0 2006.201.12:12:22.93#ibcon#read 6, iclass 35, count 0 2006.201.12:12:22.93#ibcon#end of sib2, iclass 35, count 0 2006.201.12:12:22.93#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:12:22.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:12:22.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:12:22.93#ibcon#*before write, iclass 35, count 0 2006.201.12:12:22.93#ibcon#enter sib2, iclass 35, count 0 2006.201.12:12:22.93#ibcon#flushed, iclass 35, count 0 2006.201.12:12:22.93#ibcon#about to write, iclass 35, count 0 2006.201.12:12:22.93#ibcon#wrote, iclass 35, count 0 2006.201.12:12:22.93#ibcon#about to read 3, iclass 35, count 0 2006.201.12:12:22.98#ibcon#read 3, iclass 35, count 0 2006.201.12:12:22.98#ibcon#about to read 4, iclass 35, count 0 2006.201.12:12:22.98#ibcon#read 4, iclass 35, count 0 2006.201.12:12:22.98#ibcon#about to read 5, iclass 35, count 0 2006.201.12:12:22.98#ibcon#read 5, iclass 35, count 0 2006.201.12:12:22.98#ibcon#about to read 6, iclass 35, count 0 2006.201.12:12:22.98#ibcon#read 6, iclass 35, count 0 2006.201.12:12:22.98#ibcon#end of sib2, iclass 35, count 0 2006.201.12:12:22.98#ibcon#*after write, iclass 35, count 0 2006.201.12:12:22.98#ibcon#*before return 0, iclass 35, count 0 2006.201.12:12:22.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:22.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:22.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:12:22.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:12:22.98$vck44/va=1,8 2006.201.12:12:22.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.12:12:22.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.12:12:22.98#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:22.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:22.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:22.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:22.98#ibcon#enter wrdev, iclass 37, count 2 2006.201.12:12:22.98#ibcon#first serial, iclass 37, count 2 2006.201.12:12:22.98#ibcon#enter sib2, iclass 37, count 2 2006.201.12:12:22.98#ibcon#flushed, iclass 37, count 2 2006.201.12:12:22.98#ibcon#about to write, iclass 37, count 2 2006.201.12:12:22.98#ibcon#wrote, iclass 37, count 2 2006.201.12:12:22.98#ibcon#about to read 3, iclass 37, count 2 2006.201.12:12:23.00#ibcon#read 3, iclass 37, count 2 2006.201.12:12:23.00#ibcon#about to read 4, iclass 37, count 2 2006.201.12:12:23.00#ibcon#read 4, iclass 37, count 2 2006.201.12:12:23.00#ibcon#about to read 5, iclass 37, count 2 2006.201.12:12:23.00#ibcon#read 5, iclass 37, count 2 2006.201.12:12:23.00#ibcon#about to read 6, iclass 37, count 2 2006.201.12:12:23.00#ibcon#read 6, iclass 37, count 2 2006.201.12:12:23.00#ibcon#end of sib2, iclass 37, count 2 2006.201.12:12:23.00#ibcon#*mode == 0, iclass 37, count 2 2006.201.12:12:23.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.12:12:23.00#ibcon#[25=AT01-08\r\n] 2006.201.12:12:23.00#ibcon#*before write, iclass 37, count 2 2006.201.12:12:23.00#ibcon#enter sib2, iclass 37, count 2 2006.201.12:12:23.00#ibcon#flushed, iclass 37, count 2 2006.201.12:12:23.00#ibcon#about to write, iclass 37, count 2 2006.201.12:12:23.00#ibcon#wrote, iclass 37, count 2 2006.201.12:12:23.00#ibcon#about to read 3, iclass 37, count 2 2006.201.12:12:23.04#ibcon#read 3, iclass 37, count 2 2006.201.12:12:23.04#ibcon#about to read 4, iclass 37, count 2 2006.201.12:12:23.04#ibcon#read 4, iclass 37, count 2 2006.201.12:12:23.04#ibcon#about to read 5, iclass 37, count 2 2006.201.12:12:23.04#ibcon#read 5, iclass 37, count 2 2006.201.12:12:23.04#ibcon#about to read 6, iclass 37, count 2 2006.201.12:12:23.04#ibcon#read 6, iclass 37, count 2 2006.201.12:12:23.04#ibcon#end of sib2, iclass 37, count 2 2006.201.12:12:23.04#ibcon#*after write, iclass 37, count 2 2006.201.12:12:23.04#ibcon#*before return 0, iclass 37, count 2 2006.201.12:12:23.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:23.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:23.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.12:12:23.04#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:23.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:23.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:23.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:23.16#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:12:23.16#ibcon#first serial, iclass 37, count 0 2006.201.12:12:23.16#ibcon#enter sib2, iclass 37, count 0 2006.201.12:12:23.16#ibcon#flushed, iclass 37, count 0 2006.201.12:12:23.16#ibcon#about to write, iclass 37, count 0 2006.201.12:12:23.16#ibcon#wrote, iclass 37, count 0 2006.201.12:12:23.16#ibcon#about to read 3, iclass 37, count 0 2006.201.12:12:23.18#ibcon#read 3, iclass 37, count 0 2006.201.12:12:23.18#ibcon#about to read 4, iclass 37, count 0 2006.201.12:12:23.18#ibcon#read 4, iclass 37, count 0 2006.201.12:12:23.18#ibcon#about to read 5, iclass 37, count 0 2006.201.12:12:23.18#ibcon#read 5, iclass 37, count 0 2006.201.12:12:23.18#ibcon#about to read 6, iclass 37, count 0 2006.201.12:12:23.18#ibcon#read 6, iclass 37, count 0 2006.201.12:12:23.18#ibcon#end of sib2, iclass 37, count 0 2006.201.12:12:23.18#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:12:23.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:12:23.18#ibcon#[25=USB\r\n] 2006.201.12:12:23.18#ibcon#*before write, iclass 37, count 0 2006.201.12:12:23.18#ibcon#enter sib2, iclass 37, count 0 2006.201.12:12:23.18#ibcon#flushed, iclass 37, count 0 2006.201.12:12:23.18#ibcon#about to write, iclass 37, count 0 2006.201.12:12:23.18#ibcon#wrote, iclass 37, count 0 2006.201.12:12:23.18#ibcon#about to read 3, iclass 37, count 0 2006.201.12:12:23.21#ibcon#read 3, iclass 37, count 0 2006.201.12:12:23.21#ibcon#about to read 4, iclass 37, count 0 2006.201.12:12:23.21#ibcon#read 4, iclass 37, count 0 2006.201.12:12:23.21#ibcon#about to read 5, iclass 37, count 0 2006.201.12:12:23.21#ibcon#read 5, iclass 37, count 0 2006.201.12:12:23.21#ibcon#about to read 6, iclass 37, count 0 2006.201.12:12:23.21#ibcon#read 6, iclass 37, count 0 2006.201.12:12:23.21#ibcon#end of sib2, iclass 37, count 0 2006.201.12:12:23.21#ibcon#*after write, iclass 37, count 0 2006.201.12:12:23.21#ibcon#*before return 0, iclass 37, count 0 2006.201.12:12:23.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:23.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:23.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:12:23.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:12:23.21$vck44/valo=2,534.99 2006.201.12:12:23.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.12:12:23.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.12:12:23.21#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:23.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:23.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:23.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:23.21#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:12:23.21#ibcon#first serial, iclass 39, count 0 2006.201.12:12:23.21#ibcon#enter sib2, iclass 39, count 0 2006.201.12:12:23.21#ibcon#flushed, iclass 39, count 0 2006.201.12:12:23.21#ibcon#about to write, iclass 39, count 0 2006.201.12:12:23.21#ibcon#wrote, iclass 39, count 0 2006.201.12:12:23.21#ibcon#about to read 3, iclass 39, count 0 2006.201.12:12:23.23#ibcon#read 3, iclass 39, count 0 2006.201.12:12:23.23#ibcon#about to read 4, iclass 39, count 0 2006.201.12:12:23.23#ibcon#read 4, iclass 39, count 0 2006.201.12:12:23.23#ibcon#about to read 5, iclass 39, count 0 2006.201.12:12:23.23#ibcon#read 5, iclass 39, count 0 2006.201.12:12:23.23#ibcon#about to read 6, iclass 39, count 0 2006.201.12:12:23.23#ibcon#read 6, iclass 39, count 0 2006.201.12:12:23.23#ibcon#end of sib2, iclass 39, count 0 2006.201.12:12:23.23#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:12:23.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:12:23.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:12:23.23#ibcon#*before write, iclass 39, count 0 2006.201.12:12:23.23#ibcon#enter sib2, iclass 39, count 0 2006.201.12:12:23.23#ibcon#flushed, iclass 39, count 0 2006.201.12:12:23.23#ibcon#about to write, iclass 39, count 0 2006.201.12:12:23.23#ibcon#wrote, iclass 39, count 0 2006.201.12:12:23.23#ibcon#about to read 3, iclass 39, count 0 2006.201.12:12:23.27#ibcon#read 3, iclass 39, count 0 2006.201.12:12:23.27#ibcon#about to read 4, iclass 39, count 0 2006.201.12:12:23.27#ibcon#read 4, iclass 39, count 0 2006.201.12:12:23.27#ibcon#about to read 5, iclass 39, count 0 2006.201.12:12:23.27#ibcon#read 5, iclass 39, count 0 2006.201.12:12:23.27#ibcon#about to read 6, iclass 39, count 0 2006.201.12:12:23.27#ibcon#read 6, iclass 39, count 0 2006.201.12:12:23.27#ibcon#end of sib2, iclass 39, count 0 2006.201.12:12:23.27#ibcon#*after write, iclass 39, count 0 2006.201.12:12:23.27#ibcon#*before return 0, iclass 39, count 0 2006.201.12:12:23.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:23.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:23.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:12:23.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:12:23.27$vck44/va=2,7 2006.201.12:12:23.27#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.12:12:23.27#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.12:12:23.27#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:23.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:23.33#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:23.33#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:23.33#ibcon#enter wrdev, iclass 2, count 2 2006.201.12:12:23.33#ibcon#first serial, iclass 2, count 2 2006.201.12:12:23.33#ibcon#enter sib2, iclass 2, count 2 2006.201.12:12:23.33#ibcon#flushed, iclass 2, count 2 2006.201.12:12:23.33#ibcon#about to write, iclass 2, count 2 2006.201.12:12:23.33#ibcon#wrote, iclass 2, count 2 2006.201.12:12:23.33#ibcon#about to read 3, iclass 2, count 2 2006.201.12:12:23.35#ibcon#read 3, iclass 2, count 2 2006.201.12:12:23.35#ibcon#about to read 4, iclass 2, count 2 2006.201.12:12:23.35#ibcon#read 4, iclass 2, count 2 2006.201.12:12:23.35#ibcon#about to read 5, iclass 2, count 2 2006.201.12:12:23.35#ibcon#read 5, iclass 2, count 2 2006.201.12:12:23.35#ibcon#about to read 6, iclass 2, count 2 2006.201.12:12:23.35#ibcon#read 6, iclass 2, count 2 2006.201.12:12:23.35#ibcon#end of sib2, iclass 2, count 2 2006.201.12:12:23.35#ibcon#*mode == 0, iclass 2, count 2 2006.201.12:12:23.35#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.12:12:23.35#ibcon#[25=AT02-07\r\n] 2006.201.12:12:23.35#ibcon#*before write, iclass 2, count 2 2006.201.12:12:23.35#ibcon#enter sib2, iclass 2, count 2 2006.201.12:12:23.35#ibcon#flushed, iclass 2, count 2 2006.201.12:12:23.35#ibcon#about to write, iclass 2, count 2 2006.201.12:12:23.35#ibcon#wrote, iclass 2, count 2 2006.201.12:12:23.35#ibcon#about to read 3, iclass 2, count 2 2006.201.12:12:23.38#ibcon#read 3, iclass 2, count 2 2006.201.12:12:23.38#ibcon#about to read 4, iclass 2, count 2 2006.201.12:12:23.38#ibcon#read 4, iclass 2, count 2 2006.201.12:12:23.38#ibcon#about to read 5, iclass 2, count 2 2006.201.12:12:23.38#ibcon#read 5, iclass 2, count 2 2006.201.12:12:23.38#ibcon#about to read 6, iclass 2, count 2 2006.201.12:12:23.38#ibcon#read 6, iclass 2, count 2 2006.201.12:12:23.38#ibcon#end of sib2, iclass 2, count 2 2006.201.12:12:23.38#ibcon#*after write, iclass 2, count 2 2006.201.12:12:23.38#ibcon#*before return 0, iclass 2, count 2 2006.201.12:12:23.38#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:23.38#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:23.38#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.12:12:23.38#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:23.38#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:23.50#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:23.50#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:23.50#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:12:23.50#ibcon#first serial, iclass 2, count 0 2006.201.12:12:23.50#ibcon#enter sib2, iclass 2, count 0 2006.201.12:12:23.50#ibcon#flushed, iclass 2, count 0 2006.201.12:12:23.50#ibcon#about to write, iclass 2, count 0 2006.201.12:12:23.50#ibcon#wrote, iclass 2, count 0 2006.201.12:12:23.50#ibcon#about to read 3, iclass 2, count 0 2006.201.12:12:23.52#ibcon#read 3, iclass 2, count 0 2006.201.12:12:23.52#ibcon#about to read 4, iclass 2, count 0 2006.201.12:12:23.52#ibcon#read 4, iclass 2, count 0 2006.201.12:12:23.52#ibcon#about to read 5, iclass 2, count 0 2006.201.12:12:23.52#ibcon#read 5, iclass 2, count 0 2006.201.12:12:23.52#ibcon#about to read 6, iclass 2, count 0 2006.201.12:12:23.52#ibcon#read 6, iclass 2, count 0 2006.201.12:12:23.52#ibcon#end of sib2, iclass 2, count 0 2006.201.12:12:23.52#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:12:23.52#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:12:23.52#ibcon#[25=USB\r\n] 2006.201.12:12:23.52#ibcon#*before write, iclass 2, count 0 2006.201.12:12:23.52#ibcon#enter sib2, iclass 2, count 0 2006.201.12:12:23.52#ibcon#flushed, iclass 2, count 0 2006.201.12:12:23.52#ibcon#about to write, iclass 2, count 0 2006.201.12:12:23.52#ibcon#wrote, iclass 2, count 0 2006.201.12:12:23.52#ibcon#about to read 3, iclass 2, count 0 2006.201.12:12:23.55#ibcon#read 3, iclass 2, count 0 2006.201.12:12:23.55#ibcon#about to read 4, iclass 2, count 0 2006.201.12:12:23.55#ibcon#read 4, iclass 2, count 0 2006.201.12:12:23.55#ibcon#about to read 5, iclass 2, count 0 2006.201.12:12:23.55#ibcon#read 5, iclass 2, count 0 2006.201.12:12:23.55#ibcon#about to read 6, iclass 2, count 0 2006.201.12:12:23.55#ibcon#read 6, iclass 2, count 0 2006.201.12:12:23.55#ibcon#end of sib2, iclass 2, count 0 2006.201.12:12:23.55#ibcon#*after write, iclass 2, count 0 2006.201.12:12:23.55#ibcon#*before return 0, iclass 2, count 0 2006.201.12:12:23.55#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:23.55#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:23.55#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:12:23.55#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:12:23.55$vck44/valo=3,564.99 2006.201.12:12:23.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.12:12:23.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.12:12:23.55#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:23.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:23.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:23.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:23.55#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:12:23.55#ibcon#first serial, iclass 5, count 0 2006.201.12:12:23.55#ibcon#enter sib2, iclass 5, count 0 2006.201.12:12:23.55#ibcon#flushed, iclass 5, count 0 2006.201.12:12:23.55#ibcon#about to write, iclass 5, count 0 2006.201.12:12:23.55#ibcon#wrote, iclass 5, count 0 2006.201.12:12:23.55#ibcon#about to read 3, iclass 5, count 0 2006.201.12:12:23.57#ibcon#read 3, iclass 5, count 0 2006.201.12:12:23.57#ibcon#about to read 4, iclass 5, count 0 2006.201.12:12:23.57#ibcon#read 4, iclass 5, count 0 2006.201.12:12:23.57#ibcon#about to read 5, iclass 5, count 0 2006.201.12:12:23.57#ibcon#read 5, iclass 5, count 0 2006.201.12:12:23.57#ibcon#about to read 6, iclass 5, count 0 2006.201.12:12:23.57#ibcon#read 6, iclass 5, count 0 2006.201.12:12:23.57#ibcon#end of sib2, iclass 5, count 0 2006.201.12:12:23.57#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:12:23.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:12:23.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:12:23.57#ibcon#*before write, iclass 5, count 0 2006.201.12:12:23.57#ibcon#enter sib2, iclass 5, count 0 2006.201.12:12:23.57#ibcon#flushed, iclass 5, count 0 2006.201.12:12:23.57#ibcon#about to write, iclass 5, count 0 2006.201.12:12:23.57#ibcon#wrote, iclass 5, count 0 2006.201.12:12:23.57#ibcon#about to read 3, iclass 5, count 0 2006.201.12:12:23.62#ibcon#read 3, iclass 5, count 0 2006.201.12:12:23.62#ibcon#about to read 4, iclass 5, count 0 2006.201.12:12:23.62#ibcon#read 4, iclass 5, count 0 2006.201.12:12:23.62#ibcon#about to read 5, iclass 5, count 0 2006.201.12:12:23.62#ibcon#read 5, iclass 5, count 0 2006.201.12:12:23.62#ibcon#about to read 6, iclass 5, count 0 2006.201.12:12:23.62#ibcon#read 6, iclass 5, count 0 2006.201.12:12:23.62#ibcon#end of sib2, iclass 5, count 0 2006.201.12:12:23.62#ibcon#*after write, iclass 5, count 0 2006.201.12:12:23.62#ibcon#*before return 0, iclass 5, count 0 2006.201.12:12:23.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:23.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:23.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:12:23.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:12:23.62$vck44/va=3,8 2006.201.12:12:23.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.12:12:23.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.12:12:23.62#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:23.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:23.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:23.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:23.67#ibcon#enter wrdev, iclass 7, count 2 2006.201.12:12:23.67#ibcon#first serial, iclass 7, count 2 2006.201.12:12:23.67#ibcon#enter sib2, iclass 7, count 2 2006.201.12:12:23.67#ibcon#flushed, iclass 7, count 2 2006.201.12:12:23.67#ibcon#about to write, iclass 7, count 2 2006.201.12:12:23.67#ibcon#wrote, iclass 7, count 2 2006.201.12:12:23.67#ibcon#about to read 3, iclass 7, count 2 2006.201.12:12:23.69#ibcon#read 3, iclass 7, count 2 2006.201.12:12:23.69#ibcon#about to read 4, iclass 7, count 2 2006.201.12:12:23.69#ibcon#read 4, iclass 7, count 2 2006.201.12:12:23.69#ibcon#about to read 5, iclass 7, count 2 2006.201.12:12:23.69#ibcon#read 5, iclass 7, count 2 2006.201.12:12:23.69#ibcon#about to read 6, iclass 7, count 2 2006.201.12:12:23.69#ibcon#read 6, iclass 7, count 2 2006.201.12:12:23.69#ibcon#end of sib2, iclass 7, count 2 2006.201.12:12:23.69#ibcon#*mode == 0, iclass 7, count 2 2006.201.12:12:23.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.12:12:23.69#ibcon#[25=AT03-08\r\n] 2006.201.12:12:23.69#ibcon#*before write, iclass 7, count 2 2006.201.12:12:23.69#ibcon#enter sib2, iclass 7, count 2 2006.201.12:12:23.69#ibcon#flushed, iclass 7, count 2 2006.201.12:12:23.69#ibcon#about to write, iclass 7, count 2 2006.201.12:12:23.69#ibcon#wrote, iclass 7, count 2 2006.201.12:12:23.69#ibcon#about to read 3, iclass 7, count 2 2006.201.12:12:23.72#ibcon#read 3, iclass 7, count 2 2006.201.12:12:23.72#ibcon#about to read 4, iclass 7, count 2 2006.201.12:12:23.72#ibcon#read 4, iclass 7, count 2 2006.201.12:12:23.72#ibcon#about to read 5, iclass 7, count 2 2006.201.12:12:23.72#ibcon#read 5, iclass 7, count 2 2006.201.12:12:23.72#ibcon#about to read 6, iclass 7, count 2 2006.201.12:12:23.72#ibcon#read 6, iclass 7, count 2 2006.201.12:12:23.72#ibcon#end of sib2, iclass 7, count 2 2006.201.12:12:23.72#ibcon#*after write, iclass 7, count 2 2006.201.12:12:23.72#ibcon#*before return 0, iclass 7, count 2 2006.201.12:12:23.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:23.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:23.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.12:12:23.72#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:23.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:23.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:23.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:23.84#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:12:23.84#ibcon#first serial, iclass 7, count 0 2006.201.12:12:23.84#ibcon#enter sib2, iclass 7, count 0 2006.201.12:12:23.84#ibcon#flushed, iclass 7, count 0 2006.201.12:12:23.84#ibcon#about to write, iclass 7, count 0 2006.201.12:12:23.84#ibcon#wrote, iclass 7, count 0 2006.201.12:12:23.84#ibcon#about to read 3, iclass 7, count 0 2006.201.12:12:23.86#ibcon#read 3, iclass 7, count 0 2006.201.12:12:23.86#ibcon#about to read 4, iclass 7, count 0 2006.201.12:12:23.86#ibcon#read 4, iclass 7, count 0 2006.201.12:12:23.86#ibcon#about to read 5, iclass 7, count 0 2006.201.12:12:23.86#ibcon#read 5, iclass 7, count 0 2006.201.12:12:23.86#ibcon#about to read 6, iclass 7, count 0 2006.201.12:12:23.86#ibcon#read 6, iclass 7, count 0 2006.201.12:12:23.86#ibcon#end of sib2, iclass 7, count 0 2006.201.12:12:23.86#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:12:23.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:12:23.86#ibcon#[25=USB\r\n] 2006.201.12:12:23.86#ibcon#*before write, iclass 7, count 0 2006.201.12:12:23.86#ibcon#enter sib2, iclass 7, count 0 2006.201.12:12:23.86#ibcon#flushed, iclass 7, count 0 2006.201.12:12:23.86#ibcon#about to write, iclass 7, count 0 2006.201.12:12:23.86#ibcon#wrote, iclass 7, count 0 2006.201.12:12:23.86#ibcon#about to read 3, iclass 7, count 0 2006.201.12:12:23.89#ibcon#read 3, iclass 7, count 0 2006.201.12:12:23.89#ibcon#about to read 4, iclass 7, count 0 2006.201.12:12:23.89#ibcon#read 4, iclass 7, count 0 2006.201.12:12:23.89#ibcon#about to read 5, iclass 7, count 0 2006.201.12:12:23.89#ibcon#read 5, iclass 7, count 0 2006.201.12:12:23.89#ibcon#about to read 6, iclass 7, count 0 2006.201.12:12:23.89#ibcon#read 6, iclass 7, count 0 2006.201.12:12:23.89#ibcon#end of sib2, iclass 7, count 0 2006.201.12:12:23.89#ibcon#*after write, iclass 7, count 0 2006.201.12:12:23.89#ibcon#*before return 0, iclass 7, count 0 2006.201.12:12:23.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:23.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:23.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:12:23.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:12:23.89$vck44/valo=4,624.99 2006.201.12:12:23.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.12:12:23.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.12:12:23.89#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:23.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:23.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:23.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:23.89#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:12:23.89#ibcon#first serial, iclass 11, count 0 2006.201.12:12:23.89#ibcon#enter sib2, iclass 11, count 0 2006.201.12:12:23.89#ibcon#flushed, iclass 11, count 0 2006.201.12:12:23.89#ibcon#about to write, iclass 11, count 0 2006.201.12:12:23.89#ibcon#wrote, iclass 11, count 0 2006.201.12:12:23.89#ibcon#about to read 3, iclass 11, count 0 2006.201.12:12:23.91#ibcon#read 3, iclass 11, count 0 2006.201.12:12:23.91#ibcon#about to read 4, iclass 11, count 0 2006.201.12:12:23.91#ibcon#read 4, iclass 11, count 0 2006.201.12:12:23.91#ibcon#about to read 5, iclass 11, count 0 2006.201.12:12:23.91#ibcon#read 5, iclass 11, count 0 2006.201.12:12:23.91#ibcon#about to read 6, iclass 11, count 0 2006.201.12:12:23.91#ibcon#read 6, iclass 11, count 0 2006.201.12:12:23.91#ibcon#end of sib2, iclass 11, count 0 2006.201.12:12:23.91#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:12:23.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:12:23.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:12:23.91#ibcon#*before write, iclass 11, count 0 2006.201.12:12:23.91#ibcon#enter sib2, iclass 11, count 0 2006.201.12:12:23.91#ibcon#flushed, iclass 11, count 0 2006.201.12:12:23.91#ibcon#about to write, iclass 11, count 0 2006.201.12:12:23.91#ibcon#wrote, iclass 11, count 0 2006.201.12:12:23.91#ibcon#about to read 3, iclass 11, count 0 2006.201.12:12:23.95#ibcon#read 3, iclass 11, count 0 2006.201.12:12:23.95#ibcon#about to read 4, iclass 11, count 0 2006.201.12:12:23.95#ibcon#read 4, iclass 11, count 0 2006.201.12:12:23.95#ibcon#about to read 5, iclass 11, count 0 2006.201.12:12:23.95#ibcon#read 5, iclass 11, count 0 2006.201.12:12:23.95#ibcon#about to read 6, iclass 11, count 0 2006.201.12:12:23.95#ibcon#read 6, iclass 11, count 0 2006.201.12:12:23.95#ibcon#end of sib2, iclass 11, count 0 2006.201.12:12:23.95#ibcon#*after write, iclass 11, count 0 2006.201.12:12:23.95#ibcon#*before return 0, iclass 11, count 0 2006.201.12:12:23.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:23.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:23.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:12:23.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:12:23.95$vck44/va=4,7 2006.201.12:12:23.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.12:12:23.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.12:12:23.95#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:23.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:24.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:24.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:24.01#ibcon#enter wrdev, iclass 13, count 2 2006.201.12:12:24.01#ibcon#first serial, iclass 13, count 2 2006.201.12:12:24.01#ibcon#enter sib2, iclass 13, count 2 2006.201.12:12:24.01#ibcon#flushed, iclass 13, count 2 2006.201.12:12:24.01#ibcon#about to write, iclass 13, count 2 2006.201.12:12:24.01#ibcon#wrote, iclass 13, count 2 2006.201.12:12:24.01#ibcon#about to read 3, iclass 13, count 2 2006.201.12:12:24.03#ibcon#read 3, iclass 13, count 2 2006.201.12:12:24.03#ibcon#about to read 4, iclass 13, count 2 2006.201.12:12:24.03#ibcon#read 4, iclass 13, count 2 2006.201.12:12:24.03#ibcon#about to read 5, iclass 13, count 2 2006.201.12:12:24.03#ibcon#read 5, iclass 13, count 2 2006.201.12:12:24.03#ibcon#about to read 6, iclass 13, count 2 2006.201.12:12:24.03#ibcon#read 6, iclass 13, count 2 2006.201.12:12:24.03#ibcon#end of sib2, iclass 13, count 2 2006.201.12:12:24.03#ibcon#*mode == 0, iclass 13, count 2 2006.201.12:12:24.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.12:12:24.03#ibcon#[25=AT04-07\r\n] 2006.201.12:12:24.03#ibcon#*before write, iclass 13, count 2 2006.201.12:12:24.03#ibcon#enter sib2, iclass 13, count 2 2006.201.12:12:24.03#ibcon#flushed, iclass 13, count 2 2006.201.12:12:24.03#ibcon#about to write, iclass 13, count 2 2006.201.12:12:24.03#ibcon#wrote, iclass 13, count 2 2006.201.12:12:24.03#ibcon#about to read 3, iclass 13, count 2 2006.201.12:12:24.06#ibcon#read 3, iclass 13, count 2 2006.201.12:12:24.06#ibcon#about to read 4, iclass 13, count 2 2006.201.12:12:24.06#ibcon#read 4, iclass 13, count 2 2006.201.12:12:24.06#ibcon#about to read 5, iclass 13, count 2 2006.201.12:12:24.06#ibcon#read 5, iclass 13, count 2 2006.201.12:12:24.06#ibcon#about to read 6, iclass 13, count 2 2006.201.12:12:24.06#ibcon#read 6, iclass 13, count 2 2006.201.12:12:24.06#ibcon#end of sib2, iclass 13, count 2 2006.201.12:12:24.06#ibcon#*after write, iclass 13, count 2 2006.201.12:12:24.06#ibcon#*before return 0, iclass 13, count 2 2006.201.12:12:24.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:24.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:24.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.12:12:24.06#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:24.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:24.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:24.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:24.18#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:12:24.18#ibcon#first serial, iclass 13, count 0 2006.201.12:12:24.18#ibcon#enter sib2, iclass 13, count 0 2006.201.12:12:24.18#ibcon#flushed, iclass 13, count 0 2006.201.12:12:24.18#ibcon#about to write, iclass 13, count 0 2006.201.12:12:24.18#ibcon#wrote, iclass 13, count 0 2006.201.12:12:24.18#ibcon#about to read 3, iclass 13, count 0 2006.201.12:12:24.20#ibcon#read 3, iclass 13, count 0 2006.201.12:12:24.20#ibcon#about to read 4, iclass 13, count 0 2006.201.12:12:24.20#ibcon#read 4, iclass 13, count 0 2006.201.12:12:24.20#ibcon#about to read 5, iclass 13, count 0 2006.201.12:12:24.20#ibcon#read 5, iclass 13, count 0 2006.201.12:12:24.20#ibcon#about to read 6, iclass 13, count 0 2006.201.12:12:24.20#ibcon#read 6, iclass 13, count 0 2006.201.12:12:24.20#ibcon#end of sib2, iclass 13, count 0 2006.201.12:12:24.20#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:12:24.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:12:24.20#ibcon#[25=USB\r\n] 2006.201.12:12:24.20#ibcon#*before write, iclass 13, count 0 2006.201.12:12:24.20#ibcon#enter sib2, iclass 13, count 0 2006.201.12:12:24.20#ibcon#flushed, iclass 13, count 0 2006.201.12:12:24.20#ibcon#about to write, iclass 13, count 0 2006.201.12:12:24.20#ibcon#wrote, iclass 13, count 0 2006.201.12:12:24.20#ibcon#about to read 3, iclass 13, count 0 2006.201.12:12:24.23#ibcon#read 3, iclass 13, count 0 2006.201.12:12:24.23#ibcon#about to read 4, iclass 13, count 0 2006.201.12:12:24.23#ibcon#read 4, iclass 13, count 0 2006.201.12:12:24.23#ibcon#about to read 5, iclass 13, count 0 2006.201.12:12:24.23#ibcon#read 5, iclass 13, count 0 2006.201.12:12:24.23#ibcon#about to read 6, iclass 13, count 0 2006.201.12:12:24.23#ibcon#read 6, iclass 13, count 0 2006.201.12:12:24.23#ibcon#end of sib2, iclass 13, count 0 2006.201.12:12:24.23#ibcon#*after write, iclass 13, count 0 2006.201.12:12:24.23#ibcon#*before return 0, iclass 13, count 0 2006.201.12:12:24.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:24.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:24.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:12:24.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:12:24.23$vck44/valo=5,734.99 2006.201.12:12:24.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.12:12:24.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.12:12:24.23#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:24.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:24.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:24.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:24.23#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:12:24.23#ibcon#first serial, iclass 15, count 0 2006.201.12:12:24.23#ibcon#enter sib2, iclass 15, count 0 2006.201.12:12:24.23#ibcon#flushed, iclass 15, count 0 2006.201.12:12:24.23#ibcon#about to write, iclass 15, count 0 2006.201.12:12:24.23#ibcon#wrote, iclass 15, count 0 2006.201.12:12:24.23#ibcon#about to read 3, iclass 15, count 0 2006.201.12:12:24.25#ibcon#read 3, iclass 15, count 0 2006.201.12:12:24.25#ibcon#about to read 4, iclass 15, count 0 2006.201.12:12:24.25#ibcon#read 4, iclass 15, count 0 2006.201.12:12:24.25#ibcon#about to read 5, iclass 15, count 0 2006.201.12:12:24.25#ibcon#read 5, iclass 15, count 0 2006.201.12:12:24.25#ibcon#about to read 6, iclass 15, count 0 2006.201.12:12:24.25#ibcon#read 6, iclass 15, count 0 2006.201.12:12:24.25#ibcon#end of sib2, iclass 15, count 0 2006.201.12:12:24.25#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:12:24.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:12:24.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:12:24.25#ibcon#*before write, iclass 15, count 0 2006.201.12:12:24.25#ibcon#enter sib2, iclass 15, count 0 2006.201.12:12:24.25#ibcon#flushed, iclass 15, count 0 2006.201.12:12:24.25#ibcon#about to write, iclass 15, count 0 2006.201.12:12:24.25#ibcon#wrote, iclass 15, count 0 2006.201.12:12:24.25#ibcon#about to read 3, iclass 15, count 0 2006.201.12:12:24.29#ibcon#read 3, iclass 15, count 0 2006.201.12:12:24.29#ibcon#about to read 4, iclass 15, count 0 2006.201.12:12:24.29#ibcon#read 4, iclass 15, count 0 2006.201.12:12:24.29#ibcon#about to read 5, iclass 15, count 0 2006.201.12:12:24.29#ibcon#read 5, iclass 15, count 0 2006.201.12:12:24.29#ibcon#about to read 6, iclass 15, count 0 2006.201.12:12:24.29#ibcon#read 6, iclass 15, count 0 2006.201.12:12:24.29#ibcon#end of sib2, iclass 15, count 0 2006.201.12:12:24.29#ibcon#*after write, iclass 15, count 0 2006.201.12:12:24.29#ibcon#*before return 0, iclass 15, count 0 2006.201.12:12:24.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:24.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:24.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:12:24.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:12:24.29$vck44/va=5,4 2006.201.12:12:24.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.12:12:24.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.12:12:24.29#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:24.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:24.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:24.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:24.35#ibcon#enter wrdev, iclass 17, count 2 2006.201.12:12:24.35#ibcon#first serial, iclass 17, count 2 2006.201.12:12:24.35#ibcon#enter sib2, iclass 17, count 2 2006.201.12:12:24.35#ibcon#flushed, iclass 17, count 2 2006.201.12:12:24.35#ibcon#about to write, iclass 17, count 2 2006.201.12:12:24.35#ibcon#wrote, iclass 17, count 2 2006.201.12:12:24.35#ibcon#about to read 3, iclass 17, count 2 2006.201.12:12:24.37#ibcon#read 3, iclass 17, count 2 2006.201.12:12:24.37#ibcon#about to read 4, iclass 17, count 2 2006.201.12:12:24.37#ibcon#read 4, iclass 17, count 2 2006.201.12:12:24.37#ibcon#about to read 5, iclass 17, count 2 2006.201.12:12:24.37#ibcon#read 5, iclass 17, count 2 2006.201.12:12:24.37#ibcon#about to read 6, iclass 17, count 2 2006.201.12:12:24.37#ibcon#read 6, iclass 17, count 2 2006.201.12:12:24.37#ibcon#end of sib2, iclass 17, count 2 2006.201.12:12:24.37#ibcon#*mode == 0, iclass 17, count 2 2006.201.12:12:24.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.12:12:24.37#ibcon#[25=AT05-04\r\n] 2006.201.12:12:24.37#ibcon#*before write, iclass 17, count 2 2006.201.12:12:24.37#ibcon#enter sib2, iclass 17, count 2 2006.201.12:12:24.37#ibcon#flushed, iclass 17, count 2 2006.201.12:12:24.37#ibcon#about to write, iclass 17, count 2 2006.201.12:12:24.37#ibcon#wrote, iclass 17, count 2 2006.201.12:12:24.37#ibcon#about to read 3, iclass 17, count 2 2006.201.12:12:24.40#ibcon#read 3, iclass 17, count 2 2006.201.12:12:24.40#ibcon#about to read 4, iclass 17, count 2 2006.201.12:12:24.40#ibcon#read 4, iclass 17, count 2 2006.201.12:12:24.40#ibcon#about to read 5, iclass 17, count 2 2006.201.12:12:24.40#ibcon#read 5, iclass 17, count 2 2006.201.12:12:24.40#ibcon#about to read 6, iclass 17, count 2 2006.201.12:12:24.40#ibcon#read 6, iclass 17, count 2 2006.201.12:12:24.40#ibcon#end of sib2, iclass 17, count 2 2006.201.12:12:24.40#ibcon#*after write, iclass 17, count 2 2006.201.12:12:24.40#ibcon#*before return 0, iclass 17, count 2 2006.201.12:12:24.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:24.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:24.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.12:12:24.40#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:24.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:24.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:24.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:24.52#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:12:24.52#ibcon#first serial, iclass 17, count 0 2006.201.12:12:24.52#ibcon#enter sib2, iclass 17, count 0 2006.201.12:12:24.52#ibcon#flushed, iclass 17, count 0 2006.201.12:12:24.52#ibcon#about to write, iclass 17, count 0 2006.201.12:12:24.52#ibcon#wrote, iclass 17, count 0 2006.201.12:12:24.52#ibcon#about to read 3, iclass 17, count 0 2006.201.12:12:24.54#ibcon#read 3, iclass 17, count 0 2006.201.12:12:24.54#ibcon#about to read 4, iclass 17, count 0 2006.201.12:12:24.54#ibcon#read 4, iclass 17, count 0 2006.201.12:12:24.54#ibcon#about to read 5, iclass 17, count 0 2006.201.12:12:24.54#ibcon#read 5, iclass 17, count 0 2006.201.12:12:24.54#ibcon#about to read 6, iclass 17, count 0 2006.201.12:12:24.54#ibcon#read 6, iclass 17, count 0 2006.201.12:12:24.54#ibcon#end of sib2, iclass 17, count 0 2006.201.12:12:24.54#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:12:24.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:12:24.54#ibcon#[25=USB\r\n] 2006.201.12:12:24.54#ibcon#*before write, iclass 17, count 0 2006.201.12:12:24.54#ibcon#enter sib2, iclass 17, count 0 2006.201.12:12:24.54#ibcon#flushed, iclass 17, count 0 2006.201.12:12:24.54#ibcon#about to write, iclass 17, count 0 2006.201.12:12:24.54#ibcon#wrote, iclass 17, count 0 2006.201.12:12:24.54#ibcon#about to read 3, iclass 17, count 0 2006.201.12:12:24.57#ibcon#read 3, iclass 17, count 0 2006.201.12:12:24.57#ibcon#about to read 4, iclass 17, count 0 2006.201.12:12:24.57#ibcon#read 4, iclass 17, count 0 2006.201.12:12:24.57#ibcon#about to read 5, iclass 17, count 0 2006.201.12:12:24.57#ibcon#read 5, iclass 17, count 0 2006.201.12:12:24.57#ibcon#about to read 6, iclass 17, count 0 2006.201.12:12:24.57#ibcon#read 6, iclass 17, count 0 2006.201.12:12:24.57#ibcon#end of sib2, iclass 17, count 0 2006.201.12:12:24.57#ibcon#*after write, iclass 17, count 0 2006.201.12:12:24.57#ibcon#*before return 0, iclass 17, count 0 2006.201.12:12:24.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:24.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:24.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:12:24.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:12:24.57$vck44/valo=6,814.99 2006.201.12:12:24.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.12:12:24.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.12:12:24.57#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:24.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:24.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:24.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:24.57#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:12:24.57#ibcon#first serial, iclass 19, count 0 2006.201.12:12:24.57#ibcon#enter sib2, iclass 19, count 0 2006.201.12:12:24.57#ibcon#flushed, iclass 19, count 0 2006.201.12:12:24.57#ibcon#about to write, iclass 19, count 0 2006.201.12:12:24.57#ibcon#wrote, iclass 19, count 0 2006.201.12:12:24.57#ibcon#about to read 3, iclass 19, count 0 2006.201.12:12:24.59#ibcon#read 3, iclass 19, count 0 2006.201.12:12:24.59#ibcon#about to read 4, iclass 19, count 0 2006.201.12:12:24.59#ibcon#read 4, iclass 19, count 0 2006.201.12:12:24.59#ibcon#about to read 5, iclass 19, count 0 2006.201.12:12:24.59#ibcon#read 5, iclass 19, count 0 2006.201.12:12:24.59#ibcon#about to read 6, iclass 19, count 0 2006.201.12:12:24.59#ibcon#read 6, iclass 19, count 0 2006.201.12:12:24.59#ibcon#end of sib2, iclass 19, count 0 2006.201.12:12:24.59#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:12:24.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:12:24.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:12:24.59#ibcon#*before write, iclass 19, count 0 2006.201.12:12:24.59#ibcon#enter sib2, iclass 19, count 0 2006.201.12:12:24.59#ibcon#flushed, iclass 19, count 0 2006.201.12:12:24.59#ibcon#about to write, iclass 19, count 0 2006.201.12:12:24.59#ibcon#wrote, iclass 19, count 0 2006.201.12:12:24.59#ibcon#about to read 3, iclass 19, count 0 2006.201.12:12:24.64#ibcon#read 3, iclass 19, count 0 2006.201.12:12:24.64#ibcon#about to read 4, iclass 19, count 0 2006.201.12:12:24.64#ibcon#read 4, iclass 19, count 0 2006.201.12:12:24.64#ibcon#about to read 5, iclass 19, count 0 2006.201.12:12:24.64#ibcon#read 5, iclass 19, count 0 2006.201.12:12:24.64#ibcon#about to read 6, iclass 19, count 0 2006.201.12:12:24.64#ibcon#read 6, iclass 19, count 0 2006.201.12:12:24.64#ibcon#end of sib2, iclass 19, count 0 2006.201.12:12:24.64#ibcon#*after write, iclass 19, count 0 2006.201.12:12:24.64#ibcon#*before return 0, iclass 19, count 0 2006.201.12:12:24.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:24.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:24.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:12:24.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:12:24.64$vck44/va=6,5 2006.201.12:12:24.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.12:12:24.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.12:12:24.64#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:24.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:24.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:24.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:24.69#ibcon#enter wrdev, iclass 21, count 2 2006.201.12:12:24.69#ibcon#first serial, iclass 21, count 2 2006.201.12:12:24.69#ibcon#enter sib2, iclass 21, count 2 2006.201.12:12:24.69#ibcon#flushed, iclass 21, count 2 2006.201.12:12:24.69#ibcon#about to write, iclass 21, count 2 2006.201.12:12:24.69#ibcon#wrote, iclass 21, count 2 2006.201.12:12:24.69#ibcon#about to read 3, iclass 21, count 2 2006.201.12:12:24.71#ibcon#read 3, iclass 21, count 2 2006.201.12:12:24.71#ibcon#about to read 4, iclass 21, count 2 2006.201.12:12:24.71#ibcon#read 4, iclass 21, count 2 2006.201.12:12:24.71#ibcon#about to read 5, iclass 21, count 2 2006.201.12:12:24.71#ibcon#read 5, iclass 21, count 2 2006.201.12:12:24.71#ibcon#about to read 6, iclass 21, count 2 2006.201.12:12:24.71#ibcon#read 6, iclass 21, count 2 2006.201.12:12:24.71#ibcon#end of sib2, iclass 21, count 2 2006.201.12:12:24.71#ibcon#*mode == 0, iclass 21, count 2 2006.201.12:12:24.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.12:12:24.71#ibcon#[25=AT06-05\r\n] 2006.201.12:12:24.71#ibcon#*before write, iclass 21, count 2 2006.201.12:12:24.71#ibcon#enter sib2, iclass 21, count 2 2006.201.12:12:24.71#ibcon#flushed, iclass 21, count 2 2006.201.12:12:24.71#ibcon#about to write, iclass 21, count 2 2006.201.12:12:24.71#ibcon#wrote, iclass 21, count 2 2006.201.12:12:24.71#ibcon#about to read 3, iclass 21, count 2 2006.201.12:12:24.74#ibcon#read 3, iclass 21, count 2 2006.201.12:12:24.74#ibcon#about to read 4, iclass 21, count 2 2006.201.12:12:24.74#ibcon#read 4, iclass 21, count 2 2006.201.12:12:24.74#ibcon#about to read 5, iclass 21, count 2 2006.201.12:12:24.74#ibcon#read 5, iclass 21, count 2 2006.201.12:12:24.74#ibcon#about to read 6, iclass 21, count 2 2006.201.12:12:24.74#ibcon#read 6, iclass 21, count 2 2006.201.12:12:24.74#ibcon#end of sib2, iclass 21, count 2 2006.201.12:12:24.74#ibcon#*after write, iclass 21, count 2 2006.201.12:12:24.74#ibcon#*before return 0, iclass 21, count 2 2006.201.12:12:24.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:24.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:24.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.12:12:24.74#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:24.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:24.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:24.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:24.86#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:12:24.86#ibcon#first serial, iclass 21, count 0 2006.201.12:12:24.86#ibcon#enter sib2, iclass 21, count 0 2006.201.12:12:24.86#ibcon#flushed, iclass 21, count 0 2006.201.12:12:24.86#ibcon#about to write, iclass 21, count 0 2006.201.12:12:24.86#ibcon#wrote, iclass 21, count 0 2006.201.12:12:24.86#ibcon#about to read 3, iclass 21, count 0 2006.201.12:12:24.88#ibcon#read 3, iclass 21, count 0 2006.201.12:12:24.88#ibcon#about to read 4, iclass 21, count 0 2006.201.12:12:24.88#ibcon#read 4, iclass 21, count 0 2006.201.12:12:24.88#ibcon#about to read 5, iclass 21, count 0 2006.201.12:12:24.88#ibcon#read 5, iclass 21, count 0 2006.201.12:12:24.88#ibcon#about to read 6, iclass 21, count 0 2006.201.12:12:24.88#ibcon#read 6, iclass 21, count 0 2006.201.12:12:24.88#ibcon#end of sib2, iclass 21, count 0 2006.201.12:12:24.88#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:12:24.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:12:24.88#ibcon#[25=USB\r\n] 2006.201.12:12:24.88#ibcon#*before write, iclass 21, count 0 2006.201.12:12:24.88#ibcon#enter sib2, iclass 21, count 0 2006.201.12:12:24.88#ibcon#flushed, iclass 21, count 0 2006.201.12:12:24.88#ibcon#about to write, iclass 21, count 0 2006.201.12:12:24.88#ibcon#wrote, iclass 21, count 0 2006.201.12:12:24.88#ibcon#about to read 3, iclass 21, count 0 2006.201.12:12:24.91#ibcon#read 3, iclass 21, count 0 2006.201.12:12:24.91#ibcon#about to read 4, iclass 21, count 0 2006.201.12:12:24.91#ibcon#read 4, iclass 21, count 0 2006.201.12:12:24.91#ibcon#about to read 5, iclass 21, count 0 2006.201.12:12:24.91#ibcon#read 5, iclass 21, count 0 2006.201.12:12:24.91#ibcon#about to read 6, iclass 21, count 0 2006.201.12:12:24.91#ibcon#read 6, iclass 21, count 0 2006.201.12:12:24.91#ibcon#end of sib2, iclass 21, count 0 2006.201.12:12:24.91#ibcon#*after write, iclass 21, count 0 2006.201.12:12:24.91#ibcon#*before return 0, iclass 21, count 0 2006.201.12:12:24.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:24.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:24.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:12:24.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:12:24.91$vck44/valo=7,864.99 2006.201.12:12:24.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.12:12:24.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.12:12:24.91#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:24.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:24.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:24.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:24.91#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:12:24.91#ibcon#first serial, iclass 23, count 0 2006.201.12:12:24.91#ibcon#enter sib2, iclass 23, count 0 2006.201.12:12:24.91#ibcon#flushed, iclass 23, count 0 2006.201.12:12:24.91#ibcon#about to write, iclass 23, count 0 2006.201.12:12:24.91#ibcon#wrote, iclass 23, count 0 2006.201.12:12:24.91#ibcon#about to read 3, iclass 23, count 0 2006.201.12:12:24.93#ibcon#read 3, iclass 23, count 0 2006.201.12:12:24.93#ibcon#about to read 4, iclass 23, count 0 2006.201.12:12:24.93#ibcon#read 4, iclass 23, count 0 2006.201.12:12:24.93#ibcon#about to read 5, iclass 23, count 0 2006.201.12:12:24.93#ibcon#read 5, iclass 23, count 0 2006.201.12:12:24.93#ibcon#about to read 6, iclass 23, count 0 2006.201.12:12:24.93#ibcon#read 6, iclass 23, count 0 2006.201.12:12:24.93#ibcon#end of sib2, iclass 23, count 0 2006.201.12:12:24.93#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:12:24.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:12:24.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:12:24.93#ibcon#*before write, iclass 23, count 0 2006.201.12:12:24.93#ibcon#enter sib2, iclass 23, count 0 2006.201.12:12:24.93#ibcon#flushed, iclass 23, count 0 2006.201.12:12:24.93#ibcon#about to write, iclass 23, count 0 2006.201.12:12:24.93#ibcon#wrote, iclass 23, count 0 2006.201.12:12:24.93#ibcon#about to read 3, iclass 23, count 0 2006.201.12:12:24.97#ibcon#read 3, iclass 23, count 0 2006.201.12:12:24.97#ibcon#about to read 4, iclass 23, count 0 2006.201.12:12:24.97#ibcon#read 4, iclass 23, count 0 2006.201.12:12:24.97#ibcon#about to read 5, iclass 23, count 0 2006.201.12:12:24.97#ibcon#read 5, iclass 23, count 0 2006.201.12:12:24.97#ibcon#about to read 6, iclass 23, count 0 2006.201.12:12:24.97#ibcon#read 6, iclass 23, count 0 2006.201.12:12:24.97#ibcon#end of sib2, iclass 23, count 0 2006.201.12:12:24.97#ibcon#*after write, iclass 23, count 0 2006.201.12:12:24.97#ibcon#*before return 0, iclass 23, count 0 2006.201.12:12:24.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:24.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:24.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:12:24.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:12:24.97$vck44/va=7,5 2006.201.12:12:24.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.12:12:24.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.12:12:24.97#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:24.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:25.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:25.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:25.03#ibcon#enter wrdev, iclass 25, count 2 2006.201.12:12:25.03#ibcon#first serial, iclass 25, count 2 2006.201.12:12:25.03#ibcon#enter sib2, iclass 25, count 2 2006.201.12:12:25.03#ibcon#flushed, iclass 25, count 2 2006.201.12:12:25.03#ibcon#about to write, iclass 25, count 2 2006.201.12:12:25.03#ibcon#wrote, iclass 25, count 2 2006.201.12:12:25.03#ibcon#about to read 3, iclass 25, count 2 2006.201.12:12:25.05#ibcon#read 3, iclass 25, count 2 2006.201.12:12:25.05#ibcon#about to read 4, iclass 25, count 2 2006.201.12:12:25.05#ibcon#read 4, iclass 25, count 2 2006.201.12:12:25.05#ibcon#about to read 5, iclass 25, count 2 2006.201.12:12:25.05#ibcon#read 5, iclass 25, count 2 2006.201.12:12:25.05#ibcon#about to read 6, iclass 25, count 2 2006.201.12:12:25.05#ibcon#read 6, iclass 25, count 2 2006.201.12:12:25.05#ibcon#end of sib2, iclass 25, count 2 2006.201.12:12:25.05#ibcon#*mode == 0, iclass 25, count 2 2006.201.12:12:25.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.12:12:25.05#ibcon#[25=AT07-05\r\n] 2006.201.12:12:25.05#ibcon#*before write, iclass 25, count 2 2006.201.12:12:25.05#ibcon#enter sib2, iclass 25, count 2 2006.201.12:12:25.05#ibcon#flushed, iclass 25, count 2 2006.201.12:12:25.05#ibcon#about to write, iclass 25, count 2 2006.201.12:12:25.05#ibcon#wrote, iclass 25, count 2 2006.201.12:12:25.05#ibcon#about to read 3, iclass 25, count 2 2006.201.12:12:25.08#ibcon#read 3, iclass 25, count 2 2006.201.12:12:25.08#ibcon#about to read 4, iclass 25, count 2 2006.201.12:12:25.08#ibcon#read 4, iclass 25, count 2 2006.201.12:12:25.08#ibcon#about to read 5, iclass 25, count 2 2006.201.12:12:25.08#ibcon#read 5, iclass 25, count 2 2006.201.12:12:25.08#ibcon#about to read 6, iclass 25, count 2 2006.201.12:12:25.08#ibcon#read 6, iclass 25, count 2 2006.201.12:12:25.08#ibcon#end of sib2, iclass 25, count 2 2006.201.12:12:25.08#ibcon#*after write, iclass 25, count 2 2006.201.12:12:25.08#ibcon#*before return 0, iclass 25, count 2 2006.201.12:12:25.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:25.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:25.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.12:12:25.08#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:25.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:25.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:25.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:25.20#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:12:25.20#ibcon#first serial, iclass 25, count 0 2006.201.12:12:25.20#ibcon#enter sib2, iclass 25, count 0 2006.201.12:12:25.20#ibcon#flushed, iclass 25, count 0 2006.201.12:12:25.20#ibcon#about to write, iclass 25, count 0 2006.201.12:12:25.20#ibcon#wrote, iclass 25, count 0 2006.201.12:12:25.20#ibcon#about to read 3, iclass 25, count 0 2006.201.12:12:25.22#ibcon#read 3, iclass 25, count 0 2006.201.12:12:25.22#ibcon#about to read 4, iclass 25, count 0 2006.201.12:12:25.22#ibcon#read 4, iclass 25, count 0 2006.201.12:12:25.22#ibcon#about to read 5, iclass 25, count 0 2006.201.12:12:25.22#ibcon#read 5, iclass 25, count 0 2006.201.12:12:25.22#ibcon#about to read 6, iclass 25, count 0 2006.201.12:12:25.22#ibcon#read 6, iclass 25, count 0 2006.201.12:12:25.22#ibcon#end of sib2, iclass 25, count 0 2006.201.12:12:25.22#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:12:25.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:12:25.22#ibcon#[25=USB\r\n] 2006.201.12:12:25.22#ibcon#*before write, iclass 25, count 0 2006.201.12:12:25.22#ibcon#enter sib2, iclass 25, count 0 2006.201.12:12:25.22#ibcon#flushed, iclass 25, count 0 2006.201.12:12:25.22#ibcon#about to write, iclass 25, count 0 2006.201.12:12:25.22#ibcon#wrote, iclass 25, count 0 2006.201.12:12:25.22#ibcon#about to read 3, iclass 25, count 0 2006.201.12:12:25.25#ibcon#read 3, iclass 25, count 0 2006.201.12:12:25.25#ibcon#about to read 4, iclass 25, count 0 2006.201.12:12:25.25#ibcon#read 4, iclass 25, count 0 2006.201.12:12:25.25#ibcon#about to read 5, iclass 25, count 0 2006.201.12:12:25.25#ibcon#read 5, iclass 25, count 0 2006.201.12:12:25.25#ibcon#about to read 6, iclass 25, count 0 2006.201.12:12:25.25#ibcon#read 6, iclass 25, count 0 2006.201.12:12:25.25#ibcon#end of sib2, iclass 25, count 0 2006.201.12:12:25.25#ibcon#*after write, iclass 25, count 0 2006.201.12:12:25.25#ibcon#*before return 0, iclass 25, count 0 2006.201.12:12:25.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:25.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:25.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:12:25.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:12:25.25$vck44/valo=8,884.99 2006.201.12:12:25.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.12:12:25.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.12:12:25.25#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:25.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:25.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:25.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:25.25#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:12:25.25#ibcon#first serial, iclass 27, count 0 2006.201.12:12:25.25#ibcon#enter sib2, iclass 27, count 0 2006.201.12:12:25.25#ibcon#flushed, iclass 27, count 0 2006.201.12:12:25.25#ibcon#about to write, iclass 27, count 0 2006.201.12:12:25.25#ibcon#wrote, iclass 27, count 0 2006.201.12:12:25.25#ibcon#about to read 3, iclass 27, count 0 2006.201.12:12:25.27#ibcon#read 3, iclass 27, count 0 2006.201.12:12:25.27#ibcon#about to read 4, iclass 27, count 0 2006.201.12:12:25.27#ibcon#read 4, iclass 27, count 0 2006.201.12:12:25.27#ibcon#about to read 5, iclass 27, count 0 2006.201.12:12:25.27#ibcon#read 5, iclass 27, count 0 2006.201.12:12:25.27#ibcon#about to read 6, iclass 27, count 0 2006.201.12:12:25.27#ibcon#read 6, iclass 27, count 0 2006.201.12:12:25.27#ibcon#end of sib2, iclass 27, count 0 2006.201.12:12:25.27#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:12:25.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:12:25.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:12:25.27#ibcon#*before write, iclass 27, count 0 2006.201.12:12:25.27#ibcon#enter sib2, iclass 27, count 0 2006.201.12:12:25.27#ibcon#flushed, iclass 27, count 0 2006.201.12:12:25.27#ibcon#about to write, iclass 27, count 0 2006.201.12:12:25.27#ibcon#wrote, iclass 27, count 0 2006.201.12:12:25.27#ibcon#about to read 3, iclass 27, count 0 2006.201.12:12:25.31#ibcon#read 3, iclass 27, count 0 2006.201.12:12:25.31#ibcon#about to read 4, iclass 27, count 0 2006.201.12:12:25.31#ibcon#read 4, iclass 27, count 0 2006.201.12:12:25.31#ibcon#about to read 5, iclass 27, count 0 2006.201.12:12:25.31#ibcon#read 5, iclass 27, count 0 2006.201.12:12:25.31#ibcon#about to read 6, iclass 27, count 0 2006.201.12:12:25.31#ibcon#read 6, iclass 27, count 0 2006.201.12:12:25.31#ibcon#end of sib2, iclass 27, count 0 2006.201.12:12:25.31#ibcon#*after write, iclass 27, count 0 2006.201.12:12:25.31#ibcon#*before return 0, iclass 27, count 0 2006.201.12:12:25.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:25.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:25.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:12:25.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:12:25.31$vck44/va=8,4 2006.201.12:12:25.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.12:12:25.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.12:12:25.31#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:25.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:12:25.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:12:25.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:12:25.37#ibcon#enter wrdev, iclass 29, count 2 2006.201.12:12:25.37#ibcon#first serial, iclass 29, count 2 2006.201.12:12:25.37#ibcon#enter sib2, iclass 29, count 2 2006.201.12:12:25.37#ibcon#flushed, iclass 29, count 2 2006.201.12:12:25.37#ibcon#about to write, iclass 29, count 2 2006.201.12:12:25.37#ibcon#wrote, iclass 29, count 2 2006.201.12:12:25.37#ibcon#about to read 3, iclass 29, count 2 2006.201.12:12:25.39#ibcon#read 3, iclass 29, count 2 2006.201.12:12:25.39#ibcon#about to read 4, iclass 29, count 2 2006.201.12:12:25.39#ibcon#read 4, iclass 29, count 2 2006.201.12:12:25.39#ibcon#about to read 5, iclass 29, count 2 2006.201.12:12:25.39#ibcon#read 5, iclass 29, count 2 2006.201.12:12:25.39#ibcon#about to read 6, iclass 29, count 2 2006.201.12:12:25.39#ibcon#read 6, iclass 29, count 2 2006.201.12:12:25.39#ibcon#end of sib2, iclass 29, count 2 2006.201.12:12:25.39#ibcon#*mode == 0, iclass 29, count 2 2006.201.12:12:25.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.12:12:25.39#ibcon#[25=AT08-04\r\n] 2006.201.12:12:25.39#ibcon#*before write, iclass 29, count 2 2006.201.12:12:25.39#ibcon#enter sib2, iclass 29, count 2 2006.201.12:12:25.39#ibcon#flushed, iclass 29, count 2 2006.201.12:12:25.39#ibcon#about to write, iclass 29, count 2 2006.201.12:12:25.39#ibcon#wrote, iclass 29, count 2 2006.201.12:12:25.39#ibcon#about to read 3, iclass 29, count 2 2006.201.12:12:25.42#ibcon#read 3, iclass 29, count 2 2006.201.12:12:25.42#ibcon#about to read 4, iclass 29, count 2 2006.201.12:12:25.42#ibcon#read 4, iclass 29, count 2 2006.201.12:12:25.42#ibcon#about to read 5, iclass 29, count 2 2006.201.12:12:25.42#ibcon#read 5, iclass 29, count 2 2006.201.12:12:25.42#ibcon#about to read 6, iclass 29, count 2 2006.201.12:12:25.42#ibcon#read 6, iclass 29, count 2 2006.201.12:12:25.42#ibcon#end of sib2, iclass 29, count 2 2006.201.12:12:25.42#ibcon#*after write, iclass 29, count 2 2006.201.12:12:25.42#ibcon#*before return 0, iclass 29, count 2 2006.201.12:12:25.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:12:25.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:12:25.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.12:12:25.42#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:25.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:12:25.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:12:25.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:12:25.54#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:12:25.54#ibcon#first serial, iclass 29, count 0 2006.201.12:12:25.54#ibcon#enter sib2, iclass 29, count 0 2006.201.12:12:25.54#ibcon#flushed, iclass 29, count 0 2006.201.12:12:25.54#ibcon#about to write, iclass 29, count 0 2006.201.12:12:25.54#ibcon#wrote, iclass 29, count 0 2006.201.12:12:25.54#ibcon#about to read 3, iclass 29, count 0 2006.201.12:12:25.56#ibcon#read 3, iclass 29, count 0 2006.201.12:12:25.56#ibcon#about to read 4, iclass 29, count 0 2006.201.12:12:25.56#ibcon#read 4, iclass 29, count 0 2006.201.12:12:25.56#ibcon#about to read 5, iclass 29, count 0 2006.201.12:12:25.56#ibcon#read 5, iclass 29, count 0 2006.201.12:12:25.56#ibcon#about to read 6, iclass 29, count 0 2006.201.12:12:25.56#ibcon#read 6, iclass 29, count 0 2006.201.12:12:25.56#ibcon#end of sib2, iclass 29, count 0 2006.201.12:12:25.56#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:12:25.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:12:25.56#ibcon#[25=USB\r\n] 2006.201.12:12:25.56#ibcon#*before write, iclass 29, count 0 2006.201.12:12:25.56#ibcon#enter sib2, iclass 29, count 0 2006.201.12:12:25.56#ibcon#flushed, iclass 29, count 0 2006.201.12:12:25.56#ibcon#about to write, iclass 29, count 0 2006.201.12:12:25.56#ibcon#wrote, iclass 29, count 0 2006.201.12:12:25.56#ibcon#about to read 3, iclass 29, count 0 2006.201.12:12:25.59#ibcon#read 3, iclass 29, count 0 2006.201.12:12:25.59#ibcon#about to read 4, iclass 29, count 0 2006.201.12:12:25.59#ibcon#read 4, iclass 29, count 0 2006.201.12:12:25.59#ibcon#about to read 5, iclass 29, count 0 2006.201.12:12:25.59#ibcon#read 5, iclass 29, count 0 2006.201.12:12:25.59#ibcon#about to read 6, iclass 29, count 0 2006.201.12:12:25.59#ibcon#read 6, iclass 29, count 0 2006.201.12:12:25.59#ibcon#end of sib2, iclass 29, count 0 2006.201.12:12:25.59#ibcon#*after write, iclass 29, count 0 2006.201.12:12:25.59#ibcon#*before return 0, iclass 29, count 0 2006.201.12:12:25.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:12:25.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:12:25.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:12:25.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:12:25.59$vck44/vblo=1,629.99 2006.201.12:12:25.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.12:12:25.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.12:12:25.59#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:25.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:12:25.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:12:25.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:12:25.59#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:12:25.59#ibcon#first serial, iclass 31, count 0 2006.201.12:12:25.59#ibcon#enter sib2, iclass 31, count 0 2006.201.12:12:25.59#ibcon#flushed, iclass 31, count 0 2006.201.12:12:25.59#ibcon#about to write, iclass 31, count 0 2006.201.12:12:25.59#ibcon#wrote, iclass 31, count 0 2006.201.12:12:25.59#ibcon#about to read 3, iclass 31, count 0 2006.201.12:12:25.61#ibcon#read 3, iclass 31, count 0 2006.201.12:12:25.61#ibcon#about to read 4, iclass 31, count 0 2006.201.12:12:25.61#ibcon#read 4, iclass 31, count 0 2006.201.12:12:25.61#ibcon#about to read 5, iclass 31, count 0 2006.201.12:12:25.61#ibcon#read 5, iclass 31, count 0 2006.201.12:12:25.61#ibcon#about to read 6, iclass 31, count 0 2006.201.12:12:25.61#ibcon#read 6, iclass 31, count 0 2006.201.12:12:25.61#ibcon#end of sib2, iclass 31, count 0 2006.201.12:12:25.61#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:12:25.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:12:25.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:12:25.61#ibcon#*before write, iclass 31, count 0 2006.201.12:12:25.61#ibcon#enter sib2, iclass 31, count 0 2006.201.12:12:25.61#ibcon#flushed, iclass 31, count 0 2006.201.12:12:25.61#ibcon#about to write, iclass 31, count 0 2006.201.12:12:25.61#ibcon#wrote, iclass 31, count 0 2006.201.12:12:25.61#ibcon#about to read 3, iclass 31, count 0 2006.201.12:12:25.66#ibcon#read 3, iclass 31, count 0 2006.201.12:12:25.66#ibcon#about to read 4, iclass 31, count 0 2006.201.12:12:25.66#ibcon#read 4, iclass 31, count 0 2006.201.12:12:25.66#ibcon#about to read 5, iclass 31, count 0 2006.201.12:12:25.66#ibcon#read 5, iclass 31, count 0 2006.201.12:12:25.66#ibcon#about to read 6, iclass 31, count 0 2006.201.12:12:25.66#ibcon#read 6, iclass 31, count 0 2006.201.12:12:25.66#ibcon#end of sib2, iclass 31, count 0 2006.201.12:12:25.66#ibcon#*after write, iclass 31, count 0 2006.201.12:12:25.66#ibcon#*before return 0, iclass 31, count 0 2006.201.12:12:25.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:12:25.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:12:25.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:12:25.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:12:25.66$vck44/vb=1,4 2006.201.12:12:25.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.12:12:25.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.12:12:25.66#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:25.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:12:25.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:12:25.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:12:25.66#ibcon#enter wrdev, iclass 33, count 2 2006.201.12:12:25.66#ibcon#first serial, iclass 33, count 2 2006.201.12:12:25.66#ibcon#enter sib2, iclass 33, count 2 2006.201.12:12:25.66#ibcon#flushed, iclass 33, count 2 2006.201.12:12:25.66#ibcon#about to write, iclass 33, count 2 2006.201.12:12:25.66#ibcon#wrote, iclass 33, count 2 2006.201.12:12:25.66#ibcon#about to read 3, iclass 33, count 2 2006.201.12:12:25.68#ibcon#read 3, iclass 33, count 2 2006.201.12:12:25.68#ibcon#about to read 4, iclass 33, count 2 2006.201.12:12:25.68#ibcon#read 4, iclass 33, count 2 2006.201.12:12:25.68#ibcon#about to read 5, iclass 33, count 2 2006.201.12:12:25.68#ibcon#read 5, iclass 33, count 2 2006.201.12:12:25.68#ibcon#about to read 6, iclass 33, count 2 2006.201.12:12:25.68#ibcon#read 6, iclass 33, count 2 2006.201.12:12:25.68#ibcon#end of sib2, iclass 33, count 2 2006.201.12:12:25.68#ibcon#*mode == 0, iclass 33, count 2 2006.201.12:12:25.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.12:12:25.68#ibcon#[27=AT01-04\r\n] 2006.201.12:12:25.68#ibcon#*before write, iclass 33, count 2 2006.201.12:12:25.68#ibcon#enter sib2, iclass 33, count 2 2006.201.12:12:25.68#ibcon#flushed, iclass 33, count 2 2006.201.12:12:25.68#ibcon#about to write, iclass 33, count 2 2006.201.12:12:25.68#ibcon#wrote, iclass 33, count 2 2006.201.12:12:25.68#ibcon#about to read 3, iclass 33, count 2 2006.201.12:12:25.71#ibcon#read 3, iclass 33, count 2 2006.201.12:12:25.71#ibcon#about to read 4, iclass 33, count 2 2006.201.12:12:25.71#ibcon#read 4, iclass 33, count 2 2006.201.12:12:25.71#ibcon#about to read 5, iclass 33, count 2 2006.201.12:12:25.71#ibcon#read 5, iclass 33, count 2 2006.201.12:12:25.71#ibcon#about to read 6, iclass 33, count 2 2006.201.12:12:25.71#ibcon#read 6, iclass 33, count 2 2006.201.12:12:25.71#ibcon#end of sib2, iclass 33, count 2 2006.201.12:12:25.71#ibcon#*after write, iclass 33, count 2 2006.201.12:12:25.71#ibcon#*before return 0, iclass 33, count 2 2006.201.12:12:25.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:12:25.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:12:25.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.12:12:25.71#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:25.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:12:25.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:12:25.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:12:25.83#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:12:25.83#ibcon#first serial, iclass 33, count 0 2006.201.12:12:25.83#ibcon#enter sib2, iclass 33, count 0 2006.201.12:12:25.83#ibcon#flushed, iclass 33, count 0 2006.201.12:12:25.83#ibcon#about to write, iclass 33, count 0 2006.201.12:12:25.83#ibcon#wrote, iclass 33, count 0 2006.201.12:12:25.83#ibcon#about to read 3, iclass 33, count 0 2006.201.12:12:25.85#ibcon#read 3, iclass 33, count 0 2006.201.12:12:25.85#ibcon#about to read 4, iclass 33, count 0 2006.201.12:12:25.85#ibcon#read 4, iclass 33, count 0 2006.201.12:12:25.85#ibcon#about to read 5, iclass 33, count 0 2006.201.12:12:25.85#ibcon#read 5, iclass 33, count 0 2006.201.12:12:25.85#ibcon#about to read 6, iclass 33, count 0 2006.201.12:12:25.85#ibcon#read 6, iclass 33, count 0 2006.201.12:12:25.85#ibcon#end of sib2, iclass 33, count 0 2006.201.12:12:25.85#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:12:25.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:12:25.85#ibcon#[27=USB\r\n] 2006.201.12:12:25.85#ibcon#*before write, iclass 33, count 0 2006.201.12:12:25.85#ibcon#enter sib2, iclass 33, count 0 2006.201.12:12:25.85#ibcon#flushed, iclass 33, count 0 2006.201.12:12:25.85#ibcon#about to write, iclass 33, count 0 2006.201.12:12:25.85#ibcon#wrote, iclass 33, count 0 2006.201.12:12:25.85#ibcon#about to read 3, iclass 33, count 0 2006.201.12:12:25.88#ibcon#read 3, iclass 33, count 0 2006.201.12:12:25.88#ibcon#about to read 4, iclass 33, count 0 2006.201.12:12:25.88#ibcon#read 4, iclass 33, count 0 2006.201.12:12:25.88#ibcon#about to read 5, iclass 33, count 0 2006.201.12:12:25.88#ibcon#read 5, iclass 33, count 0 2006.201.12:12:25.88#ibcon#about to read 6, iclass 33, count 0 2006.201.12:12:25.88#ibcon#read 6, iclass 33, count 0 2006.201.12:12:25.88#ibcon#end of sib2, iclass 33, count 0 2006.201.12:12:25.88#ibcon#*after write, iclass 33, count 0 2006.201.12:12:25.88#ibcon#*before return 0, iclass 33, count 0 2006.201.12:12:25.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:12:25.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:12:25.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:12:25.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:12:25.88$vck44/vblo=2,634.99 2006.201.12:12:25.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.12:12:25.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.12:12:25.88#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:25.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:25.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:25.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:25.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:12:25.88#ibcon#first serial, iclass 35, count 0 2006.201.12:12:25.88#ibcon#enter sib2, iclass 35, count 0 2006.201.12:12:25.88#ibcon#flushed, iclass 35, count 0 2006.201.12:12:25.88#ibcon#about to write, iclass 35, count 0 2006.201.12:12:25.88#ibcon#wrote, iclass 35, count 0 2006.201.12:12:25.88#ibcon#about to read 3, iclass 35, count 0 2006.201.12:12:25.90#ibcon#read 3, iclass 35, count 0 2006.201.12:12:25.90#ibcon#about to read 4, iclass 35, count 0 2006.201.12:12:25.90#ibcon#read 4, iclass 35, count 0 2006.201.12:12:25.90#ibcon#about to read 5, iclass 35, count 0 2006.201.12:12:25.90#ibcon#read 5, iclass 35, count 0 2006.201.12:12:25.90#ibcon#about to read 6, iclass 35, count 0 2006.201.12:12:25.90#ibcon#read 6, iclass 35, count 0 2006.201.12:12:25.90#ibcon#end of sib2, iclass 35, count 0 2006.201.12:12:25.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:12:25.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:12:25.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:12:25.90#ibcon#*before write, iclass 35, count 0 2006.201.12:12:25.90#ibcon#enter sib2, iclass 35, count 0 2006.201.12:12:25.90#ibcon#flushed, iclass 35, count 0 2006.201.12:12:25.90#ibcon#about to write, iclass 35, count 0 2006.201.12:12:25.90#ibcon#wrote, iclass 35, count 0 2006.201.12:12:25.90#ibcon#about to read 3, iclass 35, count 0 2006.201.12:12:25.94#ibcon#read 3, iclass 35, count 0 2006.201.12:12:25.94#ibcon#about to read 4, iclass 35, count 0 2006.201.12:12:25.94#ibcon#read 4, iclass 35, count 0 2006.201.12:12:25.94#ibcon#about to read 5, iclass 35, count 0 2006.201.12:12:25.94#ibcon#read 5, iclass 35, count 0 2006.201.12:12:25.94#ibcon#about to read 6, iclass 35, count 0 2006.201.12:12:25.94#ibcon#read 6, iclass 35, count 0 2006.201.12:12:25.94#ibcon#end of sib2, iclass 35, count 0 2006.201.12:12:25.94#ibcon#*after write, iclass 35, count 0 2006.201.12:12:25.94#ibcon#*before return 0, iclass 35, count 0 2006.201.12:12:25.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:25.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:12:25.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:12:25.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:12:25.94$vck44/vb=2,5 2006.201.12:12:25.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.12:12:25.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.12:12:25.94#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:25.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:26.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:26.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:26.00#ibcon#enter wrdev, iclass 37, count 2 2006.201.12:12:26.00#ibcon#first serial, iclass 37, count 2 2006.201.12:12:26.00#ibcon#enter sib2, iclass 37, count 2 2006.201.12:12:26.00#ibcon#flushed, iclass 37, count 2 2006.201.12:12:26.00#ibcon#about to write, iclass 37, count 2 2006.201.12:12:26.00#ibcon#wrote, iclass 37, count 2 2006.201.12:12:26.00#ibcon#about to read 3, iclass 37, count 2 2006.201.12:12:26.02#ibcon#read 3, iclass 37, count 2 2006.201.12:12:26.02#ibcon#about to read 4, iclass 37, count 2 2006.201.12:12:26.02#ibcon#read 4, iclass 37, count 2 2006.201.12:12:26.02#ibcon#about to read 5, iclass 37, count 2 2006.201.12:12:26.02#ibcon#read 5, iclass 37, count 2 2006.201.12:12:26.02#ibcon#about to read 6, iclass 37, count 2 2006.201.12:12:26.02#ibcon#read 6, iclass 37, count 2 2006.201.12:12:26.02#ibcon#end of sib2, iclass 37, count 2 2006.201.12:12:26.02#ibcon#*mode == 0, iclass 37, count 2 2006.201.12:12:26.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.12:12:26.02#ibcon#[27=AT02-05\r\n] 2006.201.12:12:26.02#ibcon#*before write, iclass 37, count 2 2006.201.12:12:26.02#ibcon#enter sib2, iclass 37, count 2 2006.201.12:12:26.02#ibcon#flushed, iclass 37, count 2 2006.201.12:12:26.02#ibcon#about to write, iclass 37, count 2 2006.201.12:12:26.02#ibcon#wrote, iclass 37, count 2 2006.201.12:12:26.02#ibcon#about to read 3, iclass 37, count 2 2006.201.12:12:26.05#ibcon#read 3, iclass 37, count 2 2006.201.12:12:26.05#ibcon#about to read 4, iclass 37, count 2 2006.201.12:12:26.05#ibcon#read 4, iclass 37, count 2 2006.201.12:12:26.05#ibcon#about to read 5, iclass 37, count 2 2006.201.12:12:26.05#ibcon#read 5, iclass 37, count 2 2006.201.12:12:26.05#ibcon#about to read 6, iclass 37, count 2 2006.201.12:12:26.05#ibcon#read 6, iclass 37, count 2 2006.201.12:12:26.05#ibcon#end of sib2, iclass 37, count 2 2006.201.12:12:26.05#ibcon#*after write, iclass 37, count 2 2006.201.12:12:26.05#ibcon#*before return 0, iclass 37, count 2 2006.201.12:12:26.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:26.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:12:26.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.12:12:26.05#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:26.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:26.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:26.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:26.17#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:12:26.17#ibcon#first serial, iclass 37, count 0 2006.201.12:12:26.17#ibcon#enter sib2, iclass 37, count 0 2006.201.12:12:26.17#ibcon#flushed, iclass 37, count 0 2006.201.12:12:26.17#ibcon#about to write, iclass 37, count 0 2006.201.12:12:26.17#ibcon#wrote, iclass 37, count 0 2006.201.12:12:26.17#ibcon#about to read 3, iclass 37, count 0 2006.201.12:12:26.19#ibcon#read 3, iclass 37, count 0 2006.201.12:12:26.19#ibcon#about to read 4, iclass 37, count 0 2006.201.12:12:26.19#ibcon#read 4, iclass 37, count 0 2006.201.12:12:26.19#ibcon#about to read 5, iclass 37, count 0 2006.201.12:12:26.19#ibcon#read 5, iclass 37, count 0 2006.201.12:12:26.19#ibcon#about to read 6, iclass 37, count 0 2006.201.12:12:26.19#ibcon#read 6, iclass 37, count 0 2006.201.12:12:26.19#ibcon#end of sib2, iclass 37, count 0 2006.201.12:12:26.19#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:12:26.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:12:26.19#ibcon#[27=USB\r\n] 2006.201.12:12:26.19#ibcon#*before write, iclass 37, count 0 2006.201.12:12:26.19#ibcon#enter sib2, iclass 37, count 0 2006.201.12:12:26.19#ibcon#flushed, iclass 37, count 0 2006.201.12:12:26.19#ibcon#about to write, iclass 37, count 0 2006.201.12:12:26.19#ibcon#wrote, iclass 37, count 0 2006.201.12:12:26.19#ibcon#about to read 3, iclass 37, count 0 2006.201.12:12:26.22#ibcon#read 3, iclass 37, count 0 2006.201.12:12:26.22#ibcon#about to read 4, iclass 37, count 0 2006.201.12:12:26.22#ibcon#read 4, iclass 37, count 0 2006.201.12:12:26.22#ibcon#about to read 5, iclass 37, count 0 2006.201.12:12:26.22#ibcon#read 5, iclass 37, count 0 2006.201.12:12:26.22#ibcon#about to read 6, iclass 37, count 0 2006.201.12:12:26.22#ibcon#read 6, iclass 37, count 0 2006.201.12:12:26.22#ibcon#end of sib2, iclass 37, count 0 2006.201.12:12:26.22#ibcon#*after write, iclass 37, count 0 2006.201.12:12:26.22#ibcon#*before return 0, iclass 37, count 0 2006.201.12:12:26.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:26.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:12:26.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:12:26.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:12:26.22$vck44/vblo=3,649.99 2006.201.12:12:26.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.12:12:26.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.12:12:26.22#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:26.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:26.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:26.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:26.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:12:26.22#ibcon#first serial, iclass 39, count 0 2006.201.12:12:26.22#ibcon#enter sib2, iclass 39, count 0 2006.201.12:12:26.22#ibcon#flushed, iclass 39, count 0 2006.201.12:12:26.22#ibcon#about to write, iclass 39, count 0 2006.201.12:12:26.22#ibcon#wrote, iclass 39, count 0 2006.201.12:12:26.22#ibcon#about to read 3, iclass 39, count 0 2006.201.12:12:26.24#ibcon#read 3, iclass 39, count 0 2006.201.12:12:26.24#ibcon#about to read 4, iclass 39, count 0 2006.201.12:12:26.24#ibcon#read 4, iclass 39, count 0 2006.201.12:12:26.24#ibcon#about to read 5, iclass 39, count 0 2006.201.12:12:26.24#ibcon#read 5, iclass 39, count 0 2006.201.12:12:26.24#ibcon#about to read 6, iclass 39, count 0 2006.201.12:12:26.24#ibcon#read 6, iclass 39, count 0 2006.201.12:12:26.24#ibcon#end of sib2, iclass 39, count 0 2006.201.12:12:26.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:12:26.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:12:26.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:12:26.24#ibcon#*before write, iclass 39, count 0 2006.201.12:12:26.24#ibcon#enter sib2, iclass 39, count 0 2006.201.12:12:26.24#ibcon#flushed, iclass 39, count 0 2006.201.12:12:26.24#ibcon#about to write, iclass 39, count 0 2006.201.12:12:26.24#ibcon#wrote, iclass 39, count 0 2006.201.12:12:26.24#ibcon#about to read 3, iclass 39, count 0 2006.201.12:12:26.28#ibcon#read 3, iclass 39, count 0 2006.201.12:12:26.28#ibcon#about to read 4, iclass 39, count 0 2006.201.12:12:26.28#ibcon#read 4, iclass 39, count 0 2006.201.12:12:26.28#ibcon#about to read 5, iclass 39, count 0 2006.201.12:12:26.28#ibcon#read 5, iclass 39, count 0 2006.201.12:12:26.28#ibcon#about to read 6, iclass 39, count 0 2006.201.12:12:26.28#ibcon#read 6, iclass 39, count 0 2006.201.12:12:26.28#ibcon#end of sib2, iclass 39, count 0 2006.201.12:12:26.28#ibcon#*after write, iclass 39, count 0 2006.201.12:12:26.28#ibcon#*before return 0, iclass 39, count 0 2006.201.12:12:26.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:26.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:12:26.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:12:26.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:12:26.28$vck44/vb=3,4 2006.201.12:12:26.28#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.12:12:26.28#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.12:12:26.28#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:26.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:26.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:26.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:26.34#ibcon#enter wrdev, iclass 2, count 2 2006.201.12:12:26.34#ibcon#first serial, iclass 2, count 2 2006.201.12:12:26.34#ibcon#enter sib2, iclass 2, count 2 2006.201.12:12:26.34#ibcon#flushed, iclass 2, count 2 2006.201.12:12:26.34#ibcon#about to write, iclass 2, count 2 2006.201.12:12:26.34#ibcon#wrote, iclass 2, count 2 2006.201.12:12:26.34#ibcon#about to read 3, iclass 2, count 2 2006.201.12:12:26.36#ibcon#read 3, iclass 2, count 2 2006.201.12:12:26.36#ibcon#about to read 4, iclass 2, count 2 2006.201.12:12:26.36#ibcon#read 4, iclass 2, count 2 2006.201.12:12:26.36#ibcon#about to read 5, iclass 2, count 2 2006.201.12:12:26.36#ibcon#read 5, iclass 2, count 2 2006.201.12:12:26.36#ibcon#about to read 6, iclass 2, count 2 2006.201.12:12:26.36#ibcon#read 6, iclass 2, count 2 2006.201.12:12:26.36#ibcon#end of sib2, iclass 2, count 2 2006.201.12:12:26.36#ibcon#*mode == 0, iclass 2, count 2 2006.201.12:12:26.36#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.12:12:26.36#ibcon#[27=AT03-04\r\n] 2006.201.12:12:26.36#ibcon#*before write, iclass 2, count 2 2006.201.12:12:26.36#ibcon#enter sib2, iclass 2, count 2 2006.201.12:12:26.36#ibcon#flushed, iclass 2, count 2 2006.201.12:12:26.36#ibcon#about to write, iclass 2, count 2 2006.201.12:12:26.36#ibcon#wrote, iclass 2, count 2 2006.201.12:12:26.36#ibcon#about to read 3, iclass 2, count 2 2006.201.12:12:26.39#ibcon#read 3, iclass 2, count 2 2006.201.12:12:26.39#ibcon#about to read 4, iclass 2, count 2 2006.201.12:12:26.39#ibcon#read 4, iclass 2, count 2 2006.201.12:12:26.39#ibcon#about to read 5, iclass 2, count 2 2006.201.12:12:26.39#ibcon#read 5, iclass 2, count 2 2006.201.12:12:26.39#ibcon#about to read 6, iclass 2, count 2 2006.201.12:12:26.39#ibcon#read 6, iclass 2, count 2 2006.201.12:12:26.39#ibcon#end of sib2, iclass 2, count 2 2006.201.12:12:26.39#ibcon#*after write, iclass 2, count 2 2006.201.12:12:26.39#ibcon#*before return 0, iclass 2, count 2 2006.201.12:12:26.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:26.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:12:26.39#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.12:12:26.39#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:26.39#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:26.51#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:26.51#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:26.51#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:12:26.51#ibcon#first serial, iclass 2, count 0 2006.201.12:12:26.51#ibcon#enter sib2, iclass 2, count 0 2006.201.12:12:26.51#ibcon#flushed, iclass 2, count 0 2006.201.12:12:26.51#ibcon#about to write, iclass 2, count 0 2006.201.12:12:26.51#ibcon#wrote, iclass 2, count 0 2006.201.12:12:26.51#ibcon#about to read 3, iclass 2, count 0 2006.201.12:12:26.53#ibcon#read 3, iclass 2, count 0 2006.201.12:12:26.53#ibcon#about to read 4, iclass 2, count 0 2006.201.12:12:26.53#ibcon#read 4, iclass 2, count 0 2006.201.12:12:26.53#ibcon#about to read 5, iclass 2, count 0 2006.201.12:12:26.53#ibcon#read 5, iclass 2, count 0 2006.201.12:12:26.53#ibcon#about to read 6, iclass 2, count 0 2006.201.12:12:26.53#ibcon#read 6, iclass 2, count 0 2006.201.12:12:26.53#ibcon#end of sib2, iclass 2, count 0 2006.201.12:12:26.53#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:12:26.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:12:26.53#ibcon#[27=USB\r\n] 2006.201.12:12:26.53#ibcon#*before write, iclass 2, count 0 2006.201.12:12:26.53#ibcon#enter sib2, iclass 2, count 0 2006.201.12:12:26.53#ibcon#flushed, iclass 2, count 0 2006.201.12:12:26.53#ibcon#about to write, iclass 2, count 0 2006.201.12:12:26.53#ibcon#wrote, iclass 2, count 0 2006.201.12:12:26.53#ibcon#about to read 3, iclass 2, count 0 2006.201.12:12:26.56#ibcon#read 3, iclass 2, count 0 2006.201.12:12:26.56#ibcon#about to read 4, iclass 2, count 0 2006.201.12:12:26.56#ibcon#read 4, iclass 2, count 0 2006.201.12:12:26.56#ibcon#about to read 5, iclass 2, count 0 2006.201.12:12:26.56#ibcon#read 5, iclass 2, count 0 2006.201.12:12:26.56#ibcon#about to read 6, iclass 2, count 0 2006.201.12:12:26.56#ibcon#read 6, iclass 2, count 0 2006.201.12:12:26.56#ibcon#end of sib2, iclass 2, count 0 2006.201.12:12:26.56#ibcon#*after write, iclass 2, count 0 2006.201.12:12:26.56#ibcon#*before return 0, iclass 2, count 0 2006.201.12:12:26.56#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:26.56#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:12:26.56#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:12:26.56#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:12:26.56$vck44/vblo=4,679.99 2006.201.12:12:26.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.12:12:26.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.12:12:26.56#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:26.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:26.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:26.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:26.56#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:12:26.56#ibcon#first serial, iclass 5, count 0 2006.201.12:12:26.56#ibcon#enter sib2, iclass 5, count 0 2006.201.12:12:26.56#ibcon#flushed, iclass 5, count 0 2006.201.12:12:26.56#ibcon#about to write, iclass 5, count 0 2006.201.12:12:26.56#ibcon#wrote, iclass 5, count 0 2006.201.12:12:26.56#ibcon#about to read 3, iclass 5, count 0 2006.201.12:12:26.58#ibcon#read 3, iclass 5, count 0 2006.201.12:12:26.58#ibcon#about to read 4, iclass 5, count 0 2006.201.12:12:26.58#ibcon#read 4, iclass 5, count 0 2006.201.12:12:26.58#ibcon#about to read 5, iclass 5, count 0 2006.201.12:12:26.58#ibcon#read 5, iclass 5, count 0 2006.201.12:12:26.58#ibcon#about to read 6, iclass 5, count 0 2006.201.12:12:26.58#ibcon#read 6, iclass 5, count 0 2006.201.12:12:26.58#ibcon#end of sib2, iclass 5, count 0 2006.201.12:12:26.58#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:12:26.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:12:26.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:12:26.58#ibcon#*before write, iclass 5, count 0 2006.201.12:12:26.58#ibcon#enter sib2, iclass 5, count 0 2006.201.12:12:26.58#ibcon#flushed, iclass 5, count 0 2006.201.12:12:26.58#ibcon#about to write, iclass 5, count 0 2006.201.12:12:26.58#ibcon#wrote, iclass 5, count 0 2006.201.12:12:26.58#ibcon#about to read 3, iclass 5, count 0 2006.201.12:12:26.63#ibcon#read 3, iclass 5, count 0 2006.201.12:12:26.63#ibcon#about to read 4, iclass 5, count 0 2006.201.12:12:26.63#ibcon#read 4, iclass 5, count 0 2006.201.12:12:26.63#ibcon#about to read 5, iclass 5, count 0 2006.201.12:12:26.63#ibcon#read 5, iclass 5, count 0 2006.201.12:12:26.63#ibcon#about to read 6, iclass 5, count 0 2006.201.12:12:26.63#ibcon#read 6, iclass 5, count 0 2006.201.12:12:26.63#ibcon#end of sib2, iclass 5, count 0 2006.201.12:12:26.63#ibcon#*after write, iclass 5, count 0 2006.201.12:12:26.63#ibcon#*before return 0, iclass 5, count 0 2006.201.12:12:26.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:26.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:12:26.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:12:26.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:12:26.63$vck44/vb=4,5 2006.201.12:12:26.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.12:12:26.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.12:12:26.63#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:26.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:26.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:26.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:26.68#ibcon#enter wrdev, iclass 7, count 2 2006.201.12:12:26.68#ibcon#first serial, iclass 7, count 2 2006.201.12:12:26.68#ibcon#enter sib2, iclass 7, count 2 2006.201.12:12:26.68#ibcon#flushed, iclass 7, count 2 2006.201.12:12:26.68#ibcon#about to write, iclass 7, count 2 2006.201.12:12:26.68#ibcon#wrote, iclass 7, count 2 2006.201.12:12:26.68#ibcon#about to read 3, iclass 7, count 2 2006.201.12:12:26.70#ibcon#read 3, iclass 7, count 2 2006.201.12:12:26.70#ibcon#about to read 4, iclass 7, count 2 2006.201.12:12:26.70#ibcon#read 4, iclass 7, count 2 2006.201.12:12:26.70#ibcon#about to read 5, iclass 7, count 2 2006.201.12:12:26.70#ibcon#read 5, iclass 7, count 2 2006.201.12:12:26.70#ibcon#about to read 6, iclass 7, count 2 2006.201.12:12:26.70#ibcon#read 6, iclass 7, count 2 2006.201.12:12:26.70#ibcon#end of sib2, iclass 7, count 2 2006.201.12:12:26.70#ibcon#*mode == 0, iclass 7, count 2 2006.201.12:12:26.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.12:12:26.70#ibcon#[27=AT04-05\r\n] 2006.201.12:12:26.70#ibcon#*before write, iclass 7, count 2 2006.201.12:12:26.70#ibcon#enter sib2, iclass 7, count 2 2006.201.12:12:26.70#ibcon#flushed, iclass 7, count 2 2006.201.12:12:26.70#ibcon#about to write, iclass 7, count 2 2006.201.12:12:26.70#ibcon#wrote, iclass 7, count 2 2006.201.12:12:26.70#ibcon#about to read 3, iclass 7, count 2 2006.201.12:12:26.73#ibcon#read 3, iclass 7, count 2 2006.201.12:12:26.73#ibcon#about to read 4, iclass 7, count 2 2006.201.12:12:26.73#ibcon#read 4, iclass 7, count 2 2006.201.12:12:26.73#ibcon#about to read 5, iclass 7, count 2 2006.201.12:12:26.73#ibcon#read 5, iclass 7, count 2 2006.201.12:12:26.73#ibcon#about to read 6, iclass 7, count 2 2006.201.12:12:26.73#ibcon#read 6, iclass 7, count 2 2006.201.12:12:26.73#ibcon#end of sib2, iclass 7, count 2 2006.201.12:12:26.73#ibcon#*after write, iclass 7, count 2 2006.201.12:12:26.73#ibcon#*before return 0, iclass 7, count 2 2006.201.12:12:26.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:26.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:12:26.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.12:12:26.73#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:26.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:26.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:26.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:26.85#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:12:26.85#ibcon#first serial, iclass 7, count 0 2006.201.12:12:26.85#ibcon#enter sib2, iclass 7, count 0 2006.201.12:12:26.85#ibcon#flushed, iclass 7, count 0 2006.201.12:12:26.85#ibcon#about to write, iclass 7, count 0 2006.201.12:12:26.85#ibcon#wrote, iclass 7, count 0 2006.201.12:12:26.85#ibcon#about to read 3, iclass 7, count 0 2006.201.12:12:26.87#ibcon#read 3, iclass 7, count 0 2006.201.12:12:26.87#ibcon#about to read 4, iclass 7, count 0 2006.201.12:12:26.87#ibcon#read 4, iclass 7, count 0 2006.201.12:12:26.87#ibcon#about to read 5, iclass 7, count 0 2006.201.12:12:26.87#ibcon#read 5, iclass 7, count 0 2006.201.12:12:26.87#ibcon#about to read 6, iclass 7, count 0 2006.201.12:12:26.87#ibcon#read 6, iclass 7, count 0 2006.201.12:12:26.87#ibcon#end of sib2, iclass 7, count 0 2006.201.12:12:26.87#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:12:26.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:12:26.87#ibcon#[27=USB\r\n] 2006.201.12:12:26.87#ibcon#*before write, iclass 7, count 0 2006.201.12:12:26.87#ibcon#enter sib2, iclass 7, count 0 2006.201.12:12:26.87#ibcon#flushed, iclass 7, count 0 2006.201.12:12:26.87#ibcon#about to write, iclass 7, count 0 2006.201.12:12:26.87#ibcon#wrote, iclass 7, count 0 2006.201.12:12:26.87#ibcon#about to read 3, iclass 7, count 0 2006.201.12:12:26.90#ibcon#read 3, iclass 7, count 0 2006.201.12:12:26.90#ibcon#about to read 4, iclass 7, count 0 2006.201.12:12:26.90#ibcon#read 4, iclass 7, count 0 2006.201.12:12:26.90#ibcon#about to read 5, iclass 7, count 0 2006.201.12:12:26.90#ibcon#read 5, iclass 7, count 0 2006.201.12:12:26.90#ibcon#about to read 6, iclass 7, count 0 2006.201.12:12:26.90#ibcon#read 6, iclass 7, count 0 2006.201.12:12:26.90#ibcon#end of sib2, iclass 7, count 0 2006.201.12:12:26.90#ibcon#*after write, iclass 7, count 0 2006.201.12:12:26.90#ibcon#*before return 0, iclass 7, count 0 2006.201.12:12:26.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:26.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:12:26.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:12:26.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:12:26.90$vck44/vblo=5,709.99 2006.201.12:12:26.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.12:12:26.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.12:12:26.90#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:26.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:26.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:26.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:26.90#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:12:26.90#ibcon#first serial, iclass 11, count 0 2006.201.12:12:26.90#ibcon#enter sib2, iclass 11, count 0 2006.201.12:12:26.90#ibcon#flushed, iclass 11, count 0 2006.201.12:12:26.90#ibcon#about to write, iclass 11, count 0 2006.201.12:12:26.90#ibcon#wrote, iclass 11, count 0 2006.201.12:12:26.90#ibcon#about to read 3, iclass 11, count 0 2006.201.12:12:26.92#ibcon#read 3, iclass 11, count 0 2006.201.12:12:26.92#ibcon#about to read 4, iclass 11, count 0 2006.201.12:12:26.92#ibcon#read 4, iclass 11, count 0 2006.201.12:12:26.92#ibcon#about to read 5, iclass 11, count 0 2006.201.12:12:26.92#ibcon#read 5, iclass 11, count 0 2006.201.12:12:26.92#ibcon#about to read 6, iclass 11, count 0 2006.201.12:12:26.92#ibcon#read 6, iclass 11, count 0 2006.201.12:12:26.92#ibcon#end of sib2, iclass 11, count 0 2006.201.12:12:26.92#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:12:26.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:12:26.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:12:26.92#ibcon#*before write, iclass 11, count 0 2006.201.12:12:26.92#ibcon#enter sib2, iclass 11, count 0 2006.201.12:12:26.92#ibcon#flushed, iclass 11, count 0 2006.201.12:12:26.92#ibcon#about to write, iclass 11, count 0 2006.201.12:12:26.92#ibcon#wrote, iclass 11, count 0 2006.201.12:12:26.92#ibcon#about to read 3, iclass 11, count 0 2006.201.12:12:26.96#ibcon#read 3, iclass 11, count 0 2006.201.12:12:26.96#ibcon#about to read 4, iclass 11, count 0 2006.201.12:12:26.96#ibcon#read 4, iclass 11, count 0 2006.201.12:12:26.96#ibcon#about to read 5, iclass 11, count 0 2006.201.12:12:26.96#ibcon#read 5, iclass 11, count 0 2006.201.12:12:26.96#ibcon#about to read 6, iclass 11, count 0 2006.201.12:12:26.96#ibcon#read 6, iclass 11, count 0 2006.201.12:12:26.96#ibcon#end of sib2, iclass 11, count 0 2006.201.12:12:26.96#ibcon#*after write, iclass 11, count 0 2006.201.12:12:26.96#ibcon#*before return 0, iclass 11, count 0 2006.201.12:12:26.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:26.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:12:26.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:12:26.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:12:26.96$vck44/vb=5,4 2006.201.12:12:26.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.12:12:26.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.12:12:26.96#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:26.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:27.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:27.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:27.02#ibcon#enter wrdev, iclass 13, count 2 2006.201.12:12:27.02#ibcon#first serial, iclass 13, count 2 2006.201.12:12:27.02#ibcon#enter sib2, iclass 13, count 2 2006.201.12:12:27.02#ibcon#flushed, iclass 13, count 2 2006.201.12:12:27.02#ibcon#about to write, iclass 13, count 2 2006.201.12:12:27.02#ibcon#wrote, iclass 13, count 2 2006.201.12:12:27.02#ibcon#about to read 3, iclass 13, count 2 2006.201.12:12:27.04#ibcon#read 3, iclass 13, count 2 2006.201.12:12:27.04#ibcon#about to read 4, iclass 13, count 2 2006.201.12:12:27.04#ibcon#read 4, iclass 13, count 2 2006.201.12:12:27.04#ibcon#about to read 5, iclass 13, count 2 2006.201.12:12:27.04#ibcon#read 5, iclass 13, count 2 2006.201.12:12:27.04#ibcon#about to read 6, iclass 13, count 2 2006.201.12:12:27.04#ibcon#read 6, iclass 13, count 2 2006.201.12:12:27.04#ibcon#end of sib2, iclass 13, count 2 2006.201.12:12:27.04#ibcon#*mode == 0, iclass 13, count 2 2006.201.12:12:27.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.12:12:27.04#ibcon#[27=AT05-04\r\n] 2006.201.12:12:27.04#ibcon#*before write, iclass 13, count 2 2006.201.12:12:27.04#ibcon#enter sib2, iclass 13, count 2 2006.201.12:12:27.04#ibcon#flushed, iclass 13, count 2 2006.201.12:12:27.04#ibcon#about to write, iclass 13, count 2 2006.201.12:12:27.04#ibcon#wrote, iclass 13, count 2 2006.201.12:12:27.04#ibcon#about to read 3, iclass 13, count 2 2006.201.12:12:27.07#ibcon#read 3, iclass 13, count 2 2006.201.12:12:27.07#ibcon#about to read 4, iclass 13, count 2 2006.201.12:12:27.07#ibcon#read 4, iclass 13, count 2 2006.201.12:12:27.07#ibcon#about to read 5, iclass 13, count 2 2006.201.12:12:27.07#ibcon#read 5, iclass 13, count 2 2006.201.12:12:27.07#ibcon#about to read 6, iclass 13, count 2 2006.201.12:12:27.07#ibcon#read 6, iclass 13, count 2 2006.201.12:12:27.07#ibcon#end of sib2, iclass 13, count 2 2006.201.12:12:27.07#ibcon#*after write, iclass 13, count 2 2006.201.12:12:27.07#ibcon#*before return 0, iclass 13, count 2 2006.201.12:12:27.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:27.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:12:27.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.12:12:27.07#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:27.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:27.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:27.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:27.19#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:12:27.19#ibcon#first serial, iclass 13, count 0 2006.201.12:12:27.19#ibcon#enter sib2, iclass 13, count 0 2006.201.12:12:27.19#ibcon#flushed, iclass 13, count 0 2006.201.12:12:27.19#ibcon#about to write, iclass 13, count 0 2006.201.12:12:27.19#ibcon#wrote, iclass 13, count 0 2006.201.12:12:27.19#ibcon#about to read 3, iclass 13, count 0 2006.201.12:12:27.22#ibcon#read 3, iclass 13, count 0 2006.201.12:12:27.22#ibcon#about to read 4, iclass 13, count 0 2006.201.12:12:27.22#ibcon#read 4, iclass 13, count 0 2006.201.12:12:27.22#ibcon#about to read 5, iclass 13, count 0 2006.201.12:12:27.22#ibcon#read 5, iclass 13, count 0 2006.201.12:12:27.22#ibcon#about to read 6, iclass 13, count 0 2006.201.12:12:27.22#ibcon#read 6, iclass 13, count 0 2006.201.12:12:27.22#ibcon#end of sib2, iclass 13, count 0 2006.201.12:12:27.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:12:27.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:12:27.22#ibcon#[27=USB\r\n] 2006.201.12:12:27.22#ibcon#*before write, iclass 13, count 0 2006.201.12:12:27.22#ibcon#enter sib2, iclass 13, count 0 2006.201.12:12:27.22#ibcon#flushed, iclass 13, count 0 2006.201.12:12:27.22#ibcon#about to write, iclass 13, count 0 2006.201.12:12:27.22#ibcon#wrote, iclass 13, count 0 2006.201.12:12:27.22#ibcon#about to read 3, iclass 13, count 0 2006.201.12:12:27.25#ibcon#read 3, iclass 13, count 0 2006.201.12:12:27.25#ibcon#about to read 4, iclass 13, count 0 2006.201.12:12:27.25#ibcon#read 4, iclass 13, count 0 2006.201.12:12:27.25#ibcon#about to read 5, iclass 13, count 0 2006.201.12:12:27.25#ibcon#read 5, iclass 13, count 0 2006.201.12:12:27.25#ibcon#about to read 6, iclass 13, count 0 2006.201.12:12:27.25#ibcon#read 6, iclass 13, count 0 2006.201.12:12:27.25#ibcon#end of sib2, iclass 13, count 0 2006.201.12:12:27.25#ibcon#*after write, iclass 13, count 0 2006.201.12:12:27.25#ibcon#*before return 0, iclass 13, count 0 2006.201.12:12:27.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:27.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:12:27.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:12:27.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:12:27.25$vck44/vblo=6,719.99 2006.201.12:12:27.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.12:12:27.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.12:12:27.25#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:27.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:27.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:27.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:27.25#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:12:27.25#ibcon#first serial, iclass 15, count 0 2006.201.12:12:27.25#ibcon#enter sib2, iclass 15, count 0 2006.201.12:12:27.25#ibcon#flushed, iclass 15, count 0 2006.201.12:12:27.25#ibcon#about to write, iclass 15, count 0 2006.201.12:12:27.25#ibcon#wrote, iclass 15, count 0 2006.201.12:12:27.25#ibcon#about to read 3, iclass 15, count 0 2006.201.12:12:27.27#ibcon#read 3, iclass 15, count 0 2006.201.12:12:27.27#ibcon#about to read 4, iclass 15, count 0 2006.201.12:12:27.27#ibcon#read 4, iclass 15, count 0 2006.201.12:12:27.27#ibcon#about to read 5, iclass 15, count 0 2006.201.12:12:27.27#ibcon#read 5, iclass 15, count 0 2006.201.12:12:27.27#ibcon#about to read 6, iclass 15, count 0 2006.201.12:12:27.27#ibcon#read 6, iclass 15, count 0 2006.201.12:12:27.27#ibcon#end of sib2, iclass 15, count 0 2006.201.12:12:27.27#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:12:27.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:12:27.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:12:27.27#ibcon#*before write, iclass 15, count 0 2006.201.12:12:27.27#ibcon#enter sib2, iclass 15, count 0 2006.201.12:12:27.27#ibcon#flushed, iclass 15, count 0 2006.201.12:12:27.27#ibcon#about to write, iclass 15, count 0 2006.201.12:12:27.27#ibcon#wrote, iclass 15, count 0 2006.201.12:12:27.27#ibcon#about to read 3, iclass 15, count 0 2006.201.12:12:27.31#ibcon#read 3, iclass 15, count 0 2006.201.12:12:27.31#ibcon#about to read 4, iclass 15, count 0 2006.201.12:12:27.31#ibcon#read 4, iclass 15, count 0 2006.201.12:12:27.31#ibcon#about to read 5, iclass 15, count 0 2006.201.12:12:27.31#ibcon#read 5, iclass 15, count 0 2006.201.12:12:27.31#ibcon#about to read 6, iclass 15, count 0 2006.201.12:12:27.31#ibcon#read 6, iclass 15, count 0 2006.201.12:12:27.31#ibcon#end of sib2, iclass 15, count 0 2006.201.12:12:27.31#ibcon#*after write, iclass 15, count 0 2006.201.12:12:27.31#ibcon#*before return 0, iclass 15, count 0 2006.201.12:12:27.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:27.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:12:27.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:12:27.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:12:27.31$vck44/vb=6,4 2006.201.12:12:27.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.12:12:27.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.12:12:27.31#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:27.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:27.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:27.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:27.37#ibcon#enter wrdev, iclass 17, count 2 2006.201.12:12:27.37#ibcon#first serial, iclass 17, count 2 2006.201.12:12:27.37#ibcon#enter sib2, iclass 17, count 2 2006.201.12:12:27.37#ibcon#flushed, iclass 17, count 2 2006.201.12:12:27.37#ibcon#about to write, iclass 17, count 2 2006.201.12:12:27.37#ibcon#wrote, iclass 17, count 2 2006.201.12:12:27.37#ibcon#about to read 3, iclass 17, count 2 2006.201.12:12:27.39#ibcon#read 3, iclass 17, count 2 2006.201.12:12:27.39#ibcon#about to read 4, iclass 17, count 2 2006.201.12:12:27.39#ibcon#read 4, iclass 17, count 2 2006.201.12:12:27.39#ibcon#about to read 5, iclass 17, count 2 2006.201.12:12:27.39#ibcon#read 5, iclass 17, count 2 2006.201.12:12:27.39#ibcon#about to read 6, iclass 17, count 2 2006.201.12:12:27.39#ibcon#read 6, iclass 17, count 2 2006.201.12:12:27.39#ibcon#end of sib2, iclass 17, count 2 2006.201.12:12:27.39#ibcon#*mode == 0, iclass 17, count 2 2006.201.12:12:27.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.12:12:27.39#ibcon#[27=AT06-04\r\n] 2006.201.12:12:27.39#ibcon#*before write, iclass 17, count 2 2006.201.12:12:27.39#ibcon#enter sib2, iclass 17, count 2 2006.201.12:12:27.39#ibcon#flushed, iclass 17, count 2 2006.201.12:12:27.39#ibcon#about to write, iclass 17, count 2 2006.201.12:12:27.39#ibcon#wrote, iclass 17, count 2 2006.201.12:12:27.39#ibcon#about to read 3, iclass 17, count 2 2006.201.12:12:27.42#ibcon#read 3, iclass 17, count 2 2006.201.12:12:27.42#ibcon#about to read 4, iclass 17, count 2 2006.201.12:12:27.42#ibcon#read 4, iclass 17, count 2 2006.201.12:12:27.42#ibcon#about to read 5, iclass 17, count 2 2006.201.12:12:27.42#ibcon#read 5, iclass 17, count 2 2006.201.12:12:27.42#ibcon#about to read 6, iclass 17, count 2 2006.201.12:12:27.42#ibcon#read 6, iclass 17, count 2 2006.201.12:12:27.42#ibcon#end of sib2, iclass 17, count 2 2006.201.12:12:27.42#ibcon#*after write, iclass 17, count 2 2006.201.12:12:27.42#ibcon#*before return 0, iclass 17, count 2 2006.201.12:12:27.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:27.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:12:27.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.12:12:27.42#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:27.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:27.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:27.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:27.54#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:12:27.54#ibcon#first serial, iclass 17, count 0 2006.201.12:12:27.54#ibcon#enter sib2, iclass 17, count 0 2006.201.12:12:27.54#ibcon#flushed, iclass 17, count 0 2006.201.12:12:27.54#ibcon#about to write, iclass 17, count 0 2006.201.12:12:27.54#ibcon#wrote, iclass 17, count 0 2006.201.12:12:27.54#ibcon#about to read 3, iclass 17, count 0 2006.201.12:12:27.56#ibcon#read 3, iclass 17, count 0 2006.201.12:12:27.56#ibcon#about to read 4, iclass 17, count 0 2006.201.12:12:27.56#ibcon#read 4, iclass 17, count 0 2006.201.12:12:27.56#ibcon#about to read 5, iclass 17, count 0 2006.201.12:12:27.56#ibcon#read 5, iclass 17, count 0 2006.201.12:12:27.56#ibcon#about to read 6, iclass 17, count 0 2006.201.12:12:27.56#ibcon#read 6, iclass 17, count 0 2006.201.12:12:27.56#ibcon#end of sib2, iclass 17, count 0 2006.201.12:12:27.56#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:12:27.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:12:27.56#ibcon#[27=USB\r\n] 2006.201.12:12:27.56#ibcon#*before write, iclass 17, count 0 2006.201.12:12:27.56#ibcon#enter sib2, iclass 17, count 0 2006.201.12:12:27.56#ibcon#flushed, iclass 17, count 0 2006.201.12:12:27.56#ibcon#about to write, iclass 17, count 0 2006.201.12:12:27.56#ibcon#wrote, iclass 17, count 0 2006.201.12:12:27.56#ibcon#about to read 3, iclass 17, count 0 2006.201.12:12:27.59#ibcon#read 3, iclass 17, count 0 2006.201.12:12:27.59#ibcon#about to read 4, iclass 17, count 0 2006.201.12:12:27.59#ibcon#read 4, iclass 17, count 0 2006.201.12:12:27.59#ibcon#about to read 5, iclass 17, count 0 2006.201.12:12:27.59#ibcon#read 5, iclass 17, count 0 2006.201.12:12:27.59#ibcon#about to read 6, iclass 17, count 0 2006.201.12:12:27.59#ibcon#read 6, iclass 17, count 0 2006.201.12:12:27.59#ibcon#end of sib2, iclass 17, count 0 2006.201.12:12:27.59#ibcon#*after write, iclass 17, count 0 2006.201.12:12:27.59#ibcon#*before return 0, iclass 17, count 0 2006.201.12:12:27.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:27.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:12:27.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:12:27.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:12:27.59$vck44/vblo=7,734.99 2006.201.12:12:27.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.12:12:27.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.12:12:27.59#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:27.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:27.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:27.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:27.59#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:12:27.59#ibcon#first serial, iclass 19, count 0 2006.201.12:12:27.59#ibcon#enter sib2, iclass 19, count 0 2006.201.12:12:27.59#ibcon#flushed, iclass 19, count 0 2006.201.12:12:27.59#ibcon#about to write, iclass 19, count 0 2006.201.12:12:27.59#ibcon#wrote, iclass 19, count 0 2006.201.12:12:27.59#ibcon#about to read 3, iclass 19, count 0 2006.201.12:12:27.61#ibcon#read 3, iclass 19, count 0 2006.201.12:12:27.61#ibcon#about to read 4, iclass 19, count 0 2006.201.12:12:27.61#ibcon#read 4, iclass 19, count 0 2006.201.12:12:27.61#ibcon#about to read 5, iclass 19, count 0 2006.201.12:12:27.61#ibcon#read 5, iclass 19, count 0 2006.201.12:12:27.61#ibcon#about to read 6, iclass 19, count 0 2006.201.12:12:27.61#ibcon#read 6, iclass 19, count 0 2006.201.12:12:27.61#ibcon#end of sib2, iclass 19, count 0 2006.201.12:12:27.61#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:12:27.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:12:27.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:12:27.61#ibcon#*before write, iclass 19, count 0 2006.201.12:12:27.61#ibcon#enter sib2, iclass 19, count 0 2006.201.12:12:27.61#ibcon#flushed, iclass 19, count 0 2006.201.12:12:27.61#ibcon#about to write, iclass 19, count 0 2006.201.12:12:27.61#ibcon#wrote, iclass 19, count 0 2006.201.12:12:27.61#ibcon#about to read 3, iclass 19, count 0 2006.201.12:12:27.65#ibcon#read 3, iclass 19, count 0 2006.201.12:12:27.65#ibcon#about to read 4, iclass 19, count 0 2006.201.12:12:27.65#ibcon#read 4, iclass 19, count 0 2006.201.12:12:27.65#ibcon#about to read 5, iclass 19, count 0 2006.201.12:12:27.65#ibcon#read 5, iclass 19, count 0 2006.201.12:12:27.65#ibcon#about to read 6, iclass 19, count 0 2006.201.12:12:27.65#ibcon#read 6, iclass 19, count 0 2006.201.12:12:27.65#ibcon#end of sib2, iclass 19, count 0 2006.201.12:12:27.65#ibcon#*after write, iclass 19, count 0 2006.201.12:12:27.65#ibcon#*before return 0, iclass 19, count 0 2006.201.12:12:27.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:27.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:12:27.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:12:27.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:12:27.65$vck44/vb=7,4 2006.201.12:12:27.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.12:12:27.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.12:12:27.65#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:27.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:27.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:27.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:27.71#ibcon#enter wrdev, iclass 21, count 2 2006.201.12:12:27.71#ibcon#first serial, iclass 21, count 2 2006.201.12:12:27.71#ibcon#enter sib2, iclass 21, count 2 2006.201.12:12:27.71#ibcon#flushed, iclass 21, count 2 2006.201.12:12:27.71#ibcon#about to write, iclass 21, count 2 2006.201.12:12:27.71#ibcon#wrote, iclass 21, count 2 2006.201.12:12:27.71#ibcon#about to read 3, iclass 21, count 2 2006.201.12:12:27.73#ibcon#read 3, iclass 21, count 2 2006.201.12:12:27.73#ibcon#about to read 4, iclass 21, count 2 2006.201.12:12:27.73#ibcon#read 4, iclass 21, count 2 2006.201.12:12:27.73#ibcon#about to read 5, iclass 21, count 2 2006.201.12:12:27.73#ibcon#read 5, iclass 21, count 2 2006.201.12:12:27.73#ibcon#about to read 6, iclass 21, count 2 2006.201.12:12:27.73#ibcon#read 6, iclass 21, count 2 2006.201.12:12:27.73#ibcon#end of sib2, iclass 21, count 2 2006.201.12:12:27.73#ibcon#*mode == 0, iclass 21, count 2 2006.201.12:12:27.73#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.12:12:27.73#ibcon#[27=AT07-04\r\n] 2006.201.12:12:27.73#ibcon#*before write, iclass 21, count 2 2006.201.12:12:27.73#ibcon#enter sib2, iclass 21, count 2 2006.201.12:12:27.73#ibcon#flushed, iclass 21, count 2 2006.201.12:12:27.73#ibcon#about to write, iclass 21, count 2 2006.201.12:12:27.73#ibcon#wrote, iclass 21, count 2 2006.201.12:12:27.73#ibcon#about to read 3, iclass 21, count 2 2006.201.12:12:27.76#ibcon#read 3, iclass 21, count 2 2006.201.12:12:27.76#ibcon#about to read 4, iclass 21, count 2 2006.201.12:12:27.76#ibcon#read 4, iclass 21, count 2 2006.201.12:12:27.76#ibcon#about to read 5, iclass 21, count 2 2006.201.12:12:27.76#ibcon#read 5, iclass 21, count 2 2006.201.12:12:27.76#ibcon#about to read 6, iclass 21, count 2 2006.201.12:12:27.76#ibcon#read 6, iclass 21, count 2 2006.201.12:12:27.76#ibcon#end of sib2, iclass 21, count 2 2006.201.12:12:27.76#ibcon#*after write, iclass 21, count 2 2006.201.12:12:27.76#ibcon#*before return 0, iclass 21, count 2 2006.201.12:12:27.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:27.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:12:27.76#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.12:12:27.76#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:27.76#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:27.88#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:27.88#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:27.88#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:12:27.88#ibcon#first serial, iclass 21, count 0 2006.201.12:12:27.88#ibcon#enter sib2, iclass 21, count 0 2006.201.12:12:27.88#ibcon#flushed, iclass 21, count 0 2006.201.12:12:27.88#ibcon#about to write, iclass 21, count 0 2006.201.12:12:27.88#ibcon#wrote, iclass 21, count 0 2006.201.12:12:27.88#ibcon#about to read 3, iclass 21, count 0 2006.201.12:12:27.90#ibcon#read 3, iclass 21, count 0 2006.201.12:12:27.90#ibcon#about to read 4, iclass 21, count 0 2006.201.12:12:27.90#ibcon#read 4, iclass 21, count 0 2006.201.12:12:27.90#ibcon#about to read 5, iclass 21, count 0 2006.201.12:12:27.90#ibcon#read 5, iclass 21, count 0 2006.201.12:12:27.90#ibcon#about to read 6, iclass 21, count 0 2006.201.12:12:27.90#ibcon#read 6, iclass 21, count 0 2006.201.12:12:27.90#ibcon#end of sib2, iclass 21, count 0 2006.201.12:12:27.90#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:12:27.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:12:27.90#ibcon#[27=USB\r\n] 2006.201.12:12:27.90#ibcon#*before write, iclass 21, count 0 2006.201.12:12:27.90#ibcon#enter sib2, iclass 21, count 0 2006.201.12:12:27.90#ibcon#flushed, iclass 21, count 0 2006.201.12:12:27.90#ibcon#about to write, iclass 21, count 0 2006.201.12:12:27.90#ibcon#wrote, iclass 21, count 0 2006.201.12:12:27.90#ibcon#about to read 3, iclass 21, count 0 2006.201.12:12:27.93#ibcon#read 3, iclass 21, count 0 2006.201.12:12:27.93#ibcon#about to read 4, iclass 21, count 0 2006.201.12:12:27.93#ibcon#read 4, iclass 21, count 0 2006.201.12:12:27.93#ibcon#about to read 5, iclass 21, count 0 2006.201.12:12:27.93#ibcon#read 5, iclass 21, count 0 2006.201.12:12:27.93#ibcon#about to read 6, iclass 21, count 0 2006.201.12:12:27.93#ibcon#read 6, iclass 21, count 0 2006.201.12:12:27.93#ibcon#end of sib2, iclass 21, count 0 2006.201.12:12:27.93#ibcon#*after write, iclass 21, count 0 2006.201.12:12:27.93#ibcon#*before return 0, iclass 21, count 0 2006.201.12:12:27.93#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:27.93#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:12:27.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:12:27.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:12:27.93$vck44/vblo=8,744.99 2006.201.12:12:27.93#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.12:12:27.93#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.12:12:27.93#ibcon#ireg 17 cls_cnt 0 2006.201.12:12:27.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:27.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:27.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:27.93#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:12:27.93#ibcon#first serial, iclass 23, count 0 2006.201.12:12:27.93#ibcon#enter sib2, iclass 23, count 0 2006.201.12:12:27.93#ibcon#flushed, iclass 23, count 0 2006.201.12:12:27.93#ibcon#about to write, iclass 23, count 0 2006.201.12:12:27.93#ibcon#wrote, iclass 23, count 0 2006.201.12:12:27.93#ibcon#about to read 3, iclass 23, count 0 2006.201.12:12:27.95#ibcon#read 3, iclass 23, count 0 2006.201.12:12:27.95#ibcon#about to read 4, iclass 23, count 0 2006.201.12:12:27.95#ibcon#read 4, iclass 23, count 0 2006.201.12:12:27.95#ibcon#about to read 5, iclass 23, count 0 2006.201.12:12:27.95#ibcon#read 5, iclass 23, count 0 2006.201.12:12:27.95#ibcon#about to read 6, iclass 23, count 0 2006.201.12:12:27.95#ibcon#read 6, iclass 23, count 0 2006.201.12:12:27.95#ibcon#end of sib2, iclass 23, count 0 2006.201.12:12:27.95#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:12:27.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:12:27.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:12:27.95#ibcon#*before write, iclass 23, count 0 2006.201.12:12:27.95#ibcon#enter sib2, iclass 23, count 0 2006.201.12:12:27.95#ibcon#flushed, iclass 23, count 0 2006.201.12:12:27.95#ibcon#about to write, iclass 23, count 0 2006.201.12:12:27.95#ibcon#wrote, iclass 23, count 0 2006.201.12:12:27.95#ibcon#about to read 3, iclass 23, count 0 2006.201.12:12:28.00#ibcon#read 3, iclass 23, count 0 2006.201.12:12:28.00#ibcon#about to read 4, iclass 23, count 0 2006.201.12:12:28.00#ibcon#read 4, iclass 23, count 0 2006.201.12:12:28.00#ibcon#about to read 5, iclass 23, count 0 2006.201.12:12:28.00#ibcon#read 5, iclass 23, count 0 2006.201.12:12:28.00#ibcon#about to read 6, iclass 23, count 0 2006.201.12:12:28.00#ibcon#read 6, iclass 23, count 0 2006.201.12:12:28.00#ibcon#end of sib2, iclass 23, count 0 2006.201.12:12:28.00#ibcon#*after write, iclass 23, count 0 2006.201.12:12:28.00#ibcon#*before return 0, iclass 23, count 0 2006.201.12:12:28.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:28.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:12:28.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:12:28.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:12:28.00$vck44/vb=8,4 2006.201.12:12:28.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.12:12:28.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.12:12:28.00#ibcon#ireg 11 cls_cnt 2 2006.201.12:12:28.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:28.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:28.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:28.05#ibcon#enter wrdev, iclass 25, count 2 2006.201.12:12:28.05#ibcon#first serial, iclass 25, count 2 2006.201.12:12:28.05#ibcon#enter sib2, iclass 25, count 2 2006.201.12:12:28.05#ibcon#flushed, iclass 25, count 2 2006.201.12:12:28.05#ibcon#about to write, iclass 25, count 2 2006.201.12:12:28.05#ibcon#wrote, iclass 25, count 2 2006.201.12:12:28.05#ibcon#about to read 3, iclass 25, count 2 2006.201.12:12:28.07#ibcon#read 3, iclass 25, count 2 2006.201.12:12:28.07#ibcon#about to read 4, iclass 25, count 2 2006.201.12:12:28.07#ibcon#read 4, iclass 25, count 2 2006.201.12:12:28.07#ibcon#about to read 5, iclass 25, count 2 2006.201.12:12:28.07#ibcon#read 5, iclass 25, count 2 2006.201.12:12:28.07#ibcon#about to read 6, iclass 25, count 2 2006.201.12:12:28.07#ibcon#read 6, iclass 25, count 2 2006.201.12:12:28.07#ibcon#end of sib2, iclass 25, count 2 2006.201.12:12:28.07#ibcon#*mode == 0, iclass 25, count 2 2006.201.12:12:28.07#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.12:12:28.07#ibcon#[27=AT08-04\r\n] 2006.201.12:12:28.07#ibcon#*before write, iclass 25, count 2 2006.201.12:12:28.07#ibcon#enter sib2, iclass 25, count 2 2006.201.12:12:28.07#ibcon#flushed, iclass 25, count 2 2006.201.12:12:28.07#ibcon#about to write, iclass 25, count 2 2006.201.12:12:28.07#ibcon#wrote, iclass 25, count 2 2006.201.12:12:28.07#ibcon#about to read 3, iclass 25, count 2 2006.201.12:12:28.10#ibcon#read 3, iclass 25, count 2 2006.201.12:12:28.10#ibcon#about to read 4, iclass 25, count 2 2006.201.12:12:28.10#ibcon#read 4, iclass 25, count 2 2006.201.12:12:28.10#ibcon#about to read 5, iclass 25, count 2 2006.201.12:12:28.10#ibcon#read 5, iclass 25, count 2 2006.201.12:12:28.10#ibcon#about to read 6, iclass 25, count 2 2006.201.12:12:28.10#ibcon#read 6, iclass 25, count 2 2006.201.12:12:28.10#ibcon#end of sib2, iclass 25, count 2 2006.201.12:12:28.10#ibcon#*after write, iclass 25, count 2 2006.201.12:12:28.10#ibcon#*before return 0, iclass 25, count 2 2006.201.12:12:28.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:28.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:12:28.10#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.12:12:28.10#ibcon#ireg 7 cls_cnt 0 2006.201.12:12:28.10#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:28.22#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:28.22#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:28.22#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:12:28.22#ibcon#first serial, iclass 25, count 0 2006.201.12:12:28.22#ibcon#enter sib2, iclass 25, count 0 2006.201.12:12:28.22#ibcon#flushed, iclass 25, count 0 2006.201.12:12:28.22#ibcon#about to write, iclass 25, count 0 2006.201.12:12:28.22#ibcon#wrote, iclass 25, count 0 2006.201.12:12:28.22#ibcon#about to read 3, iclass 25, count 0 2006.201.12:12:28.25#ibcon#read 3, iclass 25, count 0 2006.201.12:12:28.25#ibcon#about to read 4, iclass 25, count 0 2006.201.12:12:28.25#ibcon#read 4, iclass 25, count 0 2006.201.12:12:28.25#ibcon#about to read 5, iclass 25, count 0 2006.201.12:12:28.25#ibcon#read 5, iclass 25, count 0 2006.201.12:12:28.25#ibcon#about to read 6, iclass 25, count 0 2006.201.12:12:28.25#ibcon#read 6, iclass 25, count 0 2006.201.12:12:28.25#ibcon#end of sib2, iclass 25, count 0 2006.201.12:12:28.25#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:12:28.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:12:28.25#ibcon#[27=USB\r\n] 2006.201.12:12:28.25#ibcon#*before write, iclass 25, count 0 2006.201.12:12:28.25#ibcon#enter sib2, iclass 25, count 0 2006.201.12:12:28.25#ibcon#flushed, iclass 25, count 0 2006.201.12:12:28.25#ibcon#about to write, iclass 25, count 0 2006.201.12:12:28.25#ibcon#wrote, iclass 25, count 0 2006.201.12:12:28.25#ibcon#about to read 3, iclass 25, count 0 2006.201.12:12:28.28#ibcon#read 3, iclass 25, count 0 2006.201.12:12:28.28#ibcon#about to read 4, iclass 25, count 0 2006.201.12:12:28.28#ibcon#read 4, iclass 25, count 0 2006.201.12:12:28.28#ibcon#about to read 5, iclass 25, count 0 2006.201.12:12:28.28#ibcon#read 5, iclass 25, count 0 2006.201.12:12:28.28#ibcon#about to read 6, iclass 25, count 0 2006.201.12:12:28.28#ibcon#read 6, iclass 25, count 0 2006.201.12:12:28.28#ibcon#end of sib2, iclass 25, count 0 2006.201.12:12:28.28#ibcon#*after write, iclass 25, count 0 2006.201.12:12:28.28#ibcon#*before return 0, iclass 25, count 0 2006.201.12:12:28.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:28.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:12:28.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:12:28.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:12:28.28$vck44/vabw=wide 2006.201.12:12:28.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.12:12:28.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.12:12:28.28#ibcon#ireg 8 cls_cnt 0 2006.201.12:12:28.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:28.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:28.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:28.28#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:12:28.28#ibcon#first serial, iclass 27, count 0 2006.201.12:12:28.28#ibcon#enter sib2, iclass 27, count 0 2006.201.12:12:28.28#ibcon#flushed, iclass 27, count 0 2006.201.12:12:28.28#ibcon#about to write, iclass 27, count 0 2006.201.12:12:28.28#ibcon#wrote, iclass 27, count 0 2006.201.12:12:28.28#ibcon#about to read 3, iclass 27, count 0 2006.201.12:12:28.30#ibcon#read 3, iclass 27, count 0 2006.201.12:12:28.30#ibcon#about to read 4, iclass 27, count 0 2006.201.12:12:28.30#ibcon#read 4, iclass 27, count 0 2006.201.12:12:28.30#ibcon#about to read 5, iclass 27, count 0 2006.201.12:12:28.30#ibcon#read 5, iclass 27, count 0 2006.201.12:12:28.30#ibcon#about to read 6, iclass 27, count 0 2006.201.12:12:28.30#ibcon#read 6, iclass 27, count 0 2006.201.12:12:28.30#ibcon#end of sib2, iclass 27, count 0 2006.201.12:12:28.30#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:12:28.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:12:28.30#ibcon#[25=BW32\r\n] 2006.201.12:12:28.30#ibcon#*before write, iclass 27, count 0 2006.201.12:12:28.30#ibcon#enter sib2, iclass 27, count 0 2006.201.12:12:28.30#ibcon#flushed, iclass 27, count 0 2006.201.12:12:28.30#ibcon#about to write, iclass 27, count 0 2006.201.12:12:28.30#ibcon#wrote, iclass 27, count 0 2006.201.12:12:28.30#ibcon#about to read 3, iclass 27, count 0 2006.201.12:12:28.33#ibcon#read 3, iclass 27, count 0 2006.201.12:12:28.33#ibcon#about to read 4, iclass 27, count 0 2006.201.12:12:28.33#ibcon#read 4, iclass 27, count 0 2006.201.12:12:28.33#ibcon#about to read 5, iclass 27, count 0 2006.201.12:12:28.33#ibcon#read 5, iclass 27, count 0 2006.201.12:12:28.33#ibcon#about to read 6, iclass 27, count 0 2006.201.12:12:28.33#ibcon#read 6, iclass 27, count 0 2006.201.12:12:28.33#ibcon#end of sib2, iclass 27, count 0 2006.201.12:12:28.33#ibcon#*after write, iclass 27, count 0 2006.201.12:12:28.33#ibcon#*before return 0, iclass 27, count 0 2006.201.12:12:28.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:28.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:12:28.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:12:28.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:12:28.33$vck44/vbbw=wide 2006.201.12:12:28.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.12:12:28.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.12:12:28.33#ibcon#ireg 8 cls_cnt 0 2006.201.12:12:28.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:12:28.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:12:28.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:12:28.40#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:12:28.40#ibcon#first serial, iclass 29, count 0 2006.201.12:12:28.40#ibcon#enter sib2, iclass 29, count 0 2006.201.12:12:28.40#ibcon#flushed, iclass 29, count 0 2006.201.12:12:28.40#ibcon#about to write, iclass 29, count 0 2006.201.12:12:28.40#ibcon#wrote, iclass 29, count 0 2006.201.12:12:28.40#ibcon#about to read 3, iclass 29, count 0 2006.201.12:12:28.42#ibcon#read 3, iclass 29, count 0 2006.201.12:12:28.42#ibcon#about to read 4, iclass 29, count 0 2006.201.12:12:28.42#ibcon#read 4, iclass 29, count 0 2006.201.12:12:28.42#ibcon#about to read 5, iclass 29, count 0 2006.201.12:12:28.42#ibcon#read 5, iclass 29, count 0 2006.201.12:12:28.42#ibcon#about to read 6, iclass 29, count 0 2006.201.12:12:28.42#ibcon#read 6, iclass 29, count 0 2006.201.12:12:28.42#ibcon#end of sib2, iclass 29, count 0 2006.201.12:12:28.42#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:12:28.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:12:28.42#ibcon#[27=BW32\r\n] 2006.201.12:12:28.42#ibcon#*before write, iclass 29, count 0 2006.201.12:12:28.42#ibcon#enter sib2, iclass 29, count 0 2006.201.12:12:28.42#ibcon#flushed, iclass 29, count 0 2006.201.12:12:28.42#ibcon#about to write, iclass 29, count 0 2006.201.12:12:28.42#ibcon#wrote, iclass 29, count 0 2006.201.12:12:28.42#ibcon#about to read 3, iclass 29, count 0 2006.201.12:12:28.45#ibcon#read 3, iclass 29, count 0 2006.201.12:12:28.45#ibcon#about to read 4, iclass 29, count 0 2006.201.12:12:28.45#ibcon#read 4, iclass 29, count 0 2006.201.12:12:28.45#ibcon#about to read 5, iclass 29, count 0 2006.201.12:12:28.45#ibcon#read 5, iclass 29, count 0 2006.201.12:12:28.45#ibcon#about to read 6, iclass 29, count 0 2006.201.12:12:28.45#ibcon#read 6, iclass 29, count 0 2006.201.12:12:28.45#ibcon#end of sib2, iclass 29, count 0 2006.201.12:12:28.45#ibcon#*after write, iclass 29, count 0 2006.201.12:12:28.45#ibcon#*before return 0, iclass 29, count 0 2006.201.12:12:28.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:12:28.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:12:28.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:12:28.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:12:28.45$setupk4/ifdk4 2006.201.12:12:28.45$ifdk4/lo= 2006.201.12:12:28.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:12:28.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:12:28.45$ifdk4/patch= 2006.201.12:12:28.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:12:28.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:12:28.45$setupk4/!*+20s 2006.201.12:12:31.22#abcon#<5=/04 2.0 3.8 21.221001003.9\r\n> 2006.201.12:12:31.24#abcon#{5=INTERFACE CLEAR} 2006.201.12:12:31.30#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:12:41.39#abcon#<5=/04 2.0 3.8 21.231001003.9\r\n> 2006.201.12:12:41.41#abcon#{5=INTERFACE CLEAR} 2006.201.12:12:41.47#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:12:42.14#trakl#Source acquired 2006.201.12:12:42.14#flagr#flagr/antenna,acquired 2006.201.12:12:42.89$setupk4/"tpicd 2006.201.12:12:42.89$setupk4/echo=off 2006.201.12:12:42.89$setupk4/xlog=off 2006.201.12:12:42.89:!2006.201.12:20:09 2006.201.12:20:09.00:preob 2006.201.12:20:10.14/onsource/TRACKING 2006.201.12:20:10.14:!2006.201.12:20:19 2006.201.12:20:19.00:"tape 2006.201.12:20:19.00:"st=record 2006.201.12:20:19.00:data_valid=on 2006.201.12:20:19.00:midob 2006.201.12:20:19.14/onsource/TRACKING 2006.201.12:20:19.14/wx/21.18,1004.0,100 2006.201.12:20:19.32/cable/+6.4743E-03 2006.201.12:20:20.41/va/01,08,usb,yes,28,30 2006.201.12:20:20.41/va/02,07,usb,yes,30,31 2006.201.12:20:20.41/va/03,08,usb,yes,27,28 2006.201.12:20:20.41/va/04,07,usb,yes,31,33 2006.201.12:20:20.41/va/05,04,usb,yes,27,28 2006.201.12:20:20.41/va/06,05,usb,yes,27,27 2006.201.12:20:20.41/va/07,05,usb,yes,27,28 2006.201.12:20:20.41/va/08,04,usb,yes,27,32 2006.201.12:20:20.64/valo/01,524.99,yes,locked 2006.201.12:20:20.64/valo/02,534.99,yes,locked 2006.201.12:20:20.64/valo/03,564.99,yes,locked 2006.201.12:20:20.64/valo/04,624.99,yes,locked 2006.201.12:20:20.64/valo/05,734.99,yes,locked 2006.201.12:20:20.64/valo/06,814.99,yes,locked 2006.201.12:20:20.64/valo/07,864.99,yes,locked 2006.201.12:20:20.64/valo/08,884.99,yes,locked 2006.201.12:20:21.73/vb/01,04,usb,yes,30,26 2006.201.12:20:21.73/vb/02,05,usb,yes,27,28 2006.201.12:20:21.73/vb/03,04,usb,yes,28,31 2006.201.12:20:21.73/vb/04,05,usb,yes,28,27 2006.201.12:20:21.73/vb/05,04,usb,yes,25,27 2006.201.12:20:21.73/vb/06,04,usb,yes,29,25 2006.201.12:20:21.73/vb/07,04,usb,yes,29,28 2006.201.12:20:21.73/vb/08,04,usb,yes,26,30 2006.201.12:20:21.97/vblo/01,629.99,yes,locked 2006.201.12:20:21.97/vblo/02,634.99,yes,locked 2006.201.12:20:21.97/vblo/03,649.99,yes,locked 2006.201.12:20:21.97/vblo/04,679.99,yes,locked 2006.201.12:20:21.97/vblo/05,709.99,yes,locked 2006.201.12:20:21.97/vblo/06,719.99,yes,locked 2006.201.12:20:21.97/vblo/07,734.99,yes,locked 2006.201.12:20:21.97/vblo/08,744.99,yes,locked 2006.201.12:20:22.12/vabw/8 2006.201.12:20:22.27/vbbw/8 2006.201.12:20:22.36/xfe/off,on,15.5 2006.201.12:20:22.74/ifatt/23,28,28,28 2006.201.12:20:23.06/fmout-gps/S +4.60E-07 2006.201.12:20:23.13:!2006.201.12:20:59 2006.201.12:20:59.00:data_valid=off 2006.201.12:20:59.00:"et 2006.201.12:20:59.00:!+3s 2006.201.12:21:02.02:"tape 2006.201.12:21:02.02:postob 2006.201.12:21:02.21/cable/+6.4725E-03 2006.201.12:21:02.21/wx/21.18,1004.1,100 2006.201.12:21:02.29/fmout-gps/S +4.60E-07 2006.201.12:21:02.29:scan_name=201-1222,jd0607,140 2006.201.12:21:02.29:source=1334-127,133739.78,-125724.7,2000.0,ccw 2006.201.12:21:04.14#flagr#flagr/antenna,new-source 2006.201.12:21:04.14:checkk5 2006.201.12:21:04.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:21:04.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:21:05.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:21:05.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:21:05.99/chk_obsdata//k5ts1/T2011220??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.12:21:06.36/chk_obsdata//k5ts2/T2011220??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.12:21:06.73/chk_obsdata//k5ts3/T2011220??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.12:21:07.10/chk_obsdata//k5ts4/T2011220??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.12:21:07.78/k5log//k5ts1_log_newline 2006.201.12:21:08.47/k5log//k5ts2_log_newline 2006.201.12:21:09.16/k5log//k5ts3_log_newline 2006.201.12:21:09.84/k5log//k5ts4_log_newline 2006.201.12:21:09.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:21:09.87:setupk4=1 2006.201.12:21:09.87$setupk4/echo=on 2006.201.12:21:09.87$setupk4/pcalon 2006.201.12:21:09.87$pcalon/"no phase cal control is implemented here 2006.201.12:21:09.87$setupk4/"tpicd=stop 2006.201.12:21:09.87$setupk4/"rec=synch_on 2006.201.12:21:09.87$setupk4/"rec_mode=128 2006.201.12:21:09.87$setupk4/!* 2006.201.12:21:09.87$setupk4/recpk4 2006.201.12:21:09.87$recpk4/recpatch= 2006.201.12:21:09.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:21:09.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:21:09.87$setupk4/vck44 2006.201.12:21:09.87$vck44/valo=1,524.99 2006.201.12:21:09.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.12:21:09.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.12:21:09.87#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:09.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:09.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:09.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:09.87#ibcon#enter wrdev, iclass 22, count 0 2006.201.12:21:09.87#ibcon#first serial, iclass 22, count 0 2006.201.12:21:09.87#ibcon#enter sib2, iclass 22, count 0 2006.201.12:21:09.87#ibcon#flushed, iclass 22, count 0 2006.201.12:21:09.87#ibcon#about to write, iclass 22, count 0 2006.201.12:21:09.87#ibcon#wrote, iclass 22, count 0 2006.201.12:21:09.87#ibcon#about to read 3, iclass 22, count 0 2006.201.12:21:09.89#ibcon#read 3, iclass 22, count 0 2006.201.12:21:09.89#ibcon#about to read 4, iclass 22, count 0 2006.201.12:21:09.89#ibcon#read 4, iclass 22, count 0 2006.201.12:21:09.89#ibcon#about to read 5, iclass 22, count 0 2006.201.12:21:09.89#ibcon#read 5, iclass 22, count 0 2006.201.12:21:09.89#ibcon#about to read 6, iclass 22, count 0 2006.201.12:21:09.89#ibcon#read 6, iclass 22, count 0 2006.201.12:21:09.89#ibcon#end of sib2, iclass 22, count 0 2006.201.12:21:09.89#ibcon#*mode == 0, iclass 22, count 0 2006.201.12:21:09.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.12:21:09.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:21:09.89#ibcon#*before write, iclass 22, count 0 2006.201.12:21:09.89#ibcon#enter sib2, iclass 22, count 0 2006.201.12:21:09.89#ibcon#flushed, iclass 22, count 0 2006.201.12:21:09.89#ibcon#about to write, iclass 22, count 0 2006.201.12:21:09.89#ibcon#wrote, iclass 22, count 0 2006.201.12:21:09.89#ibcon#about to read 3, iclass 22, count 0 2006.201.12:21:09.94#ibcon#read 3, iclass 22, count 0 2006.201.12:21:09.94#ibcon#about to read 4, iclass 22, count 0 2006.201.12:21:09.94#ibcon#read 4, iclass 22, count 0 2006.201.12:21:09.94#ibcon#about to read 5, iclass 22, count 0 2006.201.12:21:09.94#ibcon#read 5, iclass 22, count 0 2006.201.12:21:09.94#ibcon#about to read 6, iclass 22, count 0 2006.201.12:21:09.94#ibcon#read 6, iclass 22, count 0 2006.201.12:21:09.94#ibcon#end of sib2, iclass 22, count 0 2006.201.12:21:09.94#ibcon#*after write, iclass 22, count 0 2006.201.12:21:09.94#ibcon#*before return 0, iclass 22, count 0 2006.201.12:21:09.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:09.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:09.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.12:21:09.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.12:21:09.94$vck44/va=1,8 2006.201.12:21:09.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.12:21:09.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.12:21:09.94#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:09.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:21:09.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:21:09.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:21:09.94#ibcon#enter wrdev, iclass 25, count 2 2006.201.12:21:09.94#ibcon#first serial, iclass 25, count 2 2006.201.12:21:09.94#ibcon#enter sib2, iclass 25, count 2 2006.201.12:21:09.94#ibcon#flushed, iclass 25, count 2 2006.201.12:21:09.94#ibcon#about to write, iclass 25, count 2 2006.201.12:21:09.94#ibcon#wrote, iclass 25, count 2 2006.201.12:21:09.94#ibcon#about to read 3, iclass 25, count 2 2006.201.12:21:09.96#ibcon#read 3, iclass 25, count 2 2006.201.12:21:09.96#ibcon#about to read 4, iclass 25, count 2 2006.201.12:21:09.96#ibcon#read 4, iclass 25, count 2 2006.201.12:21:09.96#ibcon#about to read 5, iclass 25, count 2 2006.201.12:21:09.96#ibcon#read 5, iclass 25, count 2 2006.201.12:21:09.96#ibcon#about to read 6, iclass 25, count 2 2006.201.12:21:09.96#ibcon#read 6, iclass 25, count 2 2006.201.12:21:09.96#ibcon#end of sib2, iclass 25, count 2 2006.201.12:21:09.96#ibcon#*mode == 0, iclass 25, count 2 2006.201.12:21:09.96#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.12:21:09.96#ibcon#[25=AT01-08\r\n] 2006.201.12:21:09.96#ibcon#*before write, iclass 25, count 2 2006.201.12:21:09.96#ibcon#enter sib2, iclass 25, count 2 2006.201.12:21:09.96#ibcon#flushed, iclass 25, count 2 2006.201.12:21:09.96#ibcon#about to write, iclass 25, count 2 2006.201.12:21:09.96#ibcon#wrote, iclass 25, count 2 2006.201.12:21:09.96#ibcon#about to read 3, iclass 25, count 2 2006.201.12:21:09.96#abcon#<5=/04 2.1 3.7 21.171001004.1\r\n> 2006.201.12:21:09.98#abcon#{5=INTERFACE CLEAR} 2006.201.12:21:09.99#ibcon#read 3, iclass 25, count 2 2006.201.12:21:09.99#ibcon#about to read 4, iclass 25, count 2 2006.201.12:21:09.99#ibcon#read 4, iclass 25, count 2 2006.201.12:21:09.99#ibcon#about to read 5, iclass 25, count 2 2006.201.12:21:09.99#ibcon#read 5, iclass 25, count 2 2006.201.12:21:09.99#ibcon#about to read 6, iclass 25, count 2 2006.201.12:21:09.99#ibcon#read 6, iclass 25, count 2 2006.201.12:21:09.99#ibcon#end of sib2, iclass 25, count 2 2006.201.12:21:09.99#ibcon#*after write, iclass 25, count 2 2006.201.12:21:09.99#ibcon#*before return 0, iclass 25, count 2 2006.201.12:21:09.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:21:09.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:21:09.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.12:21:09.99#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:09.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:21:10.04#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:21:10.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:21:10.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:21:10.11#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:21:10.11#ibcon#first serial, iclass 25, count 0 2006.201.12:21:10.11#ibcon#enter sib2, iclass 25, count 0 2006.201.12:21:10.11#ibcon#flushed, iclass 25, count 0 2006.201.12:21:10.11#ibcon#about to write, iclass 25, count 0 2006.201.12:21:10.11#ibcon#wrote, iclass 25, count 0 2006.201.12:21:10.11#ibcon#about to read 3, iclass 25, count 0 2006.201.12:21:10.13#ibcon#read 3, iclass 25, count 0 2006.201.12:21:10.13#ibcon#about to read 4, iclass 25, count 0 2006.201.12:21:10.13#ibcon#read 4, iclass 25, count 0 2006.201.12:21:10.13#ibcon#about to read 5, iclass 25, count 0 2006.201.12:21:10.13#ibcon#read 5, iclass 25, count 0 2006.201.12:21:10.13#ibcon#about to read 6, iclass 25, count 0 2006.201.12:21:10.13#ibcon#read 6, iclass 25, count 0 2006.201.12:21:10.13#ibcon#end of sib2, iclass 25, count 0 2006.201.12:21:10.13#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:21:10.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:21:10.13#ibcon#[25=USB\r\n] 2006.201.12:21:10.13#ibcon#*before write, iclass 25, count 0 2006.201.12:21:10.13#ibcon#enter sib2, iclass 25, count 0 2006.201.12:21:10.13#ibcon#flushed, iclass 25, count 0 2006.201.12:21:10.13#ibcon#about to write, iclass 25, count 0 2006.201.12:21:10.13#ibcon#wrote, iclass 25, count 0 2006.201.12:21:10.13#ibcon#about to read 3, iclass 25, count 0 2006.201.12:21:10.16#ibcon#read 3, iclass 25, count 0 2006.201.12:21:10.16#ibcon#about to read 4, iclass 25, count 0 2006.201.12:21:10.16#ibcon#read 4, iclass 25, count 0 2006.201.12:21:10.16#ibcon#about to read 5, iclass 25, count 0 2006.201.12:21:10.16#ibcon#read 5, iclass 25, count 0 2006.201.12:21:10.16#ibcon#about to read 6, iclass 25, count 0 2006.201.12:21:10.16#ibcon#read 6, iclass 25, count 0 2006.201.12:21:10.16#ibcon#end of sib2, iclass 25, count 0 2006.201.12:21:10.16#ibcon#*after write, iclass 25, count 0 2006.201.12:21:10.16#ibcon#*before return 0, iclass 25, count 0 2006.201.12:21:10.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:21:10.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:21:10.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:21:10.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:21:10.16$vck44/valo=2,534.99 2006.201.12:21:10.16#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.12:21:10.16#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.12:21:10.16#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:10.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:10.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:10.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:10.16#ibcon#enter wrdev, iclass 30, count 0 2006.201.12:21:10.16#ibcon#first serial, iclass 30, count 0 2006.201.12:21:10.16#ibcon#enter sib2, iclass 30, count 0 2006.201.12:21:10.16#ibcon#flushed, iclass 30, count 0 2006.201.12:21:10.16#ibcon#about to write, iclass 30, count 0 2006.201.12:21:10.16#ibcon#wrote, iclass 30, count 0 2006.201.12:21:10.16#ibcon#about to read 3, iclass 30, count 0 2006.201.12:21:10.18#ibcon#read 3, iclass 30, count 0 2006.201.12:21:10.18#ibcon#about to read 4, iclass 30, count 0 2006.201.12:21:10.18#ibcon#read 4, iclass 30, count 0 2006.201.12:21:10.18#ibcon#about to read 5, iclass 30, count 0 2006.201.12:21:10.18#ibcon#read 5, iclass 30, count 0 2006.201.12:21:10.18#ibcon#about to read 6, iclass 30, count 0 2006.201.12:21:10.18#ibcon#read 6, iclass 30, count 0 2006.201.12:21:10.18#ibcon#end of sib2, iclass 30, count 0 2006.201.12:21:10.18#ibcon#*mode == 0, iclass 30, count 0 2006.201.12:21:10.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.12:21:10.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:21:10.18#ibcon#*before write, iclass 30, count 0 2006.201.12:21:10.18#ibcon#enter sib2, iclass 30, count 0 2006.201.12:21:10.18#ibcon#flushed, iclass 30, count 0 2006.201.12:21:10.18#ibcon#about to write, iclass 30, count 0 2006.201.12:21:10.18#ibcon#wrote, iclass 30, count 0 2006.201.12:21:10.18#ibcon#about to read 3, iclass 30, count 0 2006.201.12:21:10.23#ibcon#read 3, iclass 30, count 0 2006.201.12:21:10.23#ibcon#about to read 4, iclass 30, count 0 2006.201.12:21:10.23#ibcon#read 4, iclass 30, count 0 2006.201.12:21:10.23#ibcon#about to read 5, iclass 30, count 0 2006.201.12:21:10.23#ibcon#read 5, iclass 30, count 0 2006.201.12:21:10.23#ibcon#about to read 6, iclass 30, count 0 2006.201.12:21:10.23#ibcon#read 6, iclass 30, count 0 2006.201.12:21:10.23#ibcon#end of sib2, iclass 30, count 0 2006.201.12:21:10.23#ibcon#*after write, iclass 30, count 0 2006.201.12:21:10.23#ibcon#*before return 0, iclass 30, count 0 2006.201.12:21:10.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:10.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:10.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.12:21:10.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.12:21:10.23$vck44/va=2,7 2006.201.12:21:10.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.12:21:10.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.12:21:10.23#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:10.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:10.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:10.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:10.28#ibcon#enter wrdev, iclass 32, count 2 2006.201.12:21:10.28#ibcon#first serial, iclass 32, count 2 2006.201.12:21:10.28#ibcon#enter sib2, iclass 32, count 2 2006.201.12:21:10.28#ibcon#flushed, iclass 32, count 2 2006.201.12:21:10.28#ibcon#about to write, iclass 32, count 2 2006.201.12:21:10.28#ibcon#wrote, iclass 32, count 2 2006.201.12:21:10.28#ibcon#about to read 3, iclass 32, count 2 2006.201.12:21:10.30#ibcon#read 3, iclass 32, count 2 2006.201.12:21:10.30#ibcon#about to read 4, iclass 32, count 2 2006.201.12:21:10.30#ibcon#read 4, iclass 32, count 2 2006.201.12:21:10.30#ibcon#about to read 5, iclass 32, count 2 2006.201.12:21:10.30#ibcon#read 5, iclass 32, count 2 2006.201.12:21:10.30#ibcon#about to read 6, iclass 32, count 2 2006.201.12:21:10.30#ibcon#read 6, iclass 32, count 2 2006.201.12:21:10.30#ibcon#end of sib2, iclass 32, count 2 2006.201.12:21:10.30#ibcon#*mode == 0, iclass 32, count 2 2006.201.12:21:10.30#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.12:21:10.30#ibcon#[25=AT02-07\r\n] 2006.201.12:21:10.30#ibcon#*before write, iclass 32, count 2 2006.201.12:21:10.30#ibcon#enter sib2, iclass 32, count 2 2006.201.12:21:10.30#ibcon#flushed, iclass 32, count 2 2006.201.12:21:10.30#ibcon#about to write, iclass 32, count 2 2006.201.12:21:10.30#ibcon#wrote, iclass 32, count 2 2006.201.12:21:10.30#ibcon#about to read 3, iclass 32, count 2 2006.201.12:21:10.33#ibcon#read 3, iclass 32, count 2 2006.201.12:21:10.33#ibcon#about to read 4, iclass 32, count 2 2006.201.12:21:10.33#ibcon#read 4, iclass 32, count 2 2006.201.12:21:10.33#ibcon#about to read 5, iclass 32, count 2 2006.201.12:21:10.33#ibcon#read 5, iclass 32, count 2 2006.201.12:21:10.33#ibcon#about to read 6, iclass 32, count 2 2006.201.12:21:10.33#ibcon#read 6, iclass 32, count 2 2006.201.12:21:10.33#ibcon#end of sib2, iclass 32, count 2 2006.201.12:21:10.33#ibcon#*after write, iclass 32, count 2 2006.201.12:21:10.33#ibcon#*before return 0, iclass 32, count 2 2006.201.12:21:10.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:10.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:10.33#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.12:21:10.33#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:10.33#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:10.45#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:10.45#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:10.45#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:21:10.45#ibcon#first serial, iclass 32, count 0 2006.201.12:21:10.45#ibcon#enter sib2, iclass 32, count 0 2006.201.12:21:10.45#ibcon#flushed, iclass 32, count 0 2006.201.12:21:10.45#ibcon#about to write, iclass 32, count 0 2006.201.12:21:10.45#ibcon#wrote, iclass 32, count 0 2006.201.12:21:10.45#ibcon#about to read 3, iclass 32, count 0 2006.201.12:21:10.47#ibcon#read 3, iclass 32, count 0 2006.201.12:21:10.47#ibcon#about to read 4, iclass 32, count 0 2006.201.12:21:10.47#ibcon#read 4, iclass 32, count 0 2006.201.12:21:10.47#ibcon#about to read 5, iclass 32, count 0 2006.201.12:21:10.47#ibcon#read 5, iclass 32, count 0 2006.201.12:21:10.47#ibcon#about to read 6, iclass 32, count 0 2006.201.12:21:10.47#ibcon#read 6, iclass 32, count 0 2006.201.12:21:10.47#ibcon#end of sib2, iclass 32, count 0 2006.201.12:21:10.47#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:21:10.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:21:10.47#ibcon#[25=USB\r\n] 2006.201.12:21:10.47#ibcon#*before write, iclass 32, count 0 2006.201.12:21:10.47#ibcon#enter sib2, iclass 32, count 0 2006.201.12:21:10.47#ibcon#flushed, iclass 32, count 0 2006.201.12:21:10.47#ibcon#about to write, iclass 32, count 0 2006.201.12:21:10.47#ibcon#wrote, iclass 32, count 0 2006.201.12:21:10.47#ibcon#about to read 3, iclass 32, count 0 2006.201.12:21:10.50#ibcon#read 3, iclass 32, count 0 2006.201.12:21:10.50#ibcon#about to read 4, iclass 32, count 0 2006.201.12:21:10.50#ibcon#read 4, iclass 32, count 0 2006.201.12:21:10.50#ibcon#about to read 5, iclass 32, count 0 2006.201.12:21:10.50#ibcon#read 5, iclass 32, count 0 2006.201.12:21:10.50#ibcon#about to read 6, iclass 32, count 0 2006.201.12:21:10.50#ibcon#read 6, iclass 32, count 0 2006.201.12:21:10.50#ibcon#end of sib2, iclass 32, count 0 2006.201.12:21:10.50#ibcon#*after write, iclass 32, count 0 2006.201.12:21:10.50#ibcon#*before return 0, iclass 32, count 0 2006.201.12:21:10.50#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:10.50#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:10.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:21:10.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:21:10.50$vck44/valo=3,564.99 2006.201.12:21:10.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.12:21:10.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.12:21:10.50#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:10.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:10.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:10.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:10.50#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:21:10.50#ibcon#first serial, iclass 34, count 0 2006.201.12:21:10.50#ibcon#enter sib2, iclass 34, count 0 2006.201.12:21:10.50#ibcon#flushed, iclass 34, count 0 2006.201.12:21:10.50#ibcon#about to write, iclass 34, count 0 2006.201.12:21:10.50#ibcon#wrote, iclass 34, count 0 2006.201.12:21:10.50#ibcon#about to read 3, iclass 34, count 0 2006.201.12:21:10.52#ibcon#read 3, iclass 34, count 0 2006.201.12:21:10.52#ibcon#about to read 4, iclass 34, count 0 2006.201.12:21:10.52#ibcon#read 4, iclass 34, count 0 2006.201.12:21:10.52#ibcon#about to read 5, iclass 34, count 0 2006.201.12:21:10.52#ibcon#read 5, iclass 34, count 0 2006.201.12:21:10.52#ibcon#about to read 6, iclass 34, count 0 2006.201.12:21:10.52#ibcon#read 6, iclass 34, count 0 2006.201.12:21:10.52#ibcon#end of sib2, iclass 34, count 0 2006.201.12:21:10.52#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:21:10.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:21:10.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:21:10.52#ibcon#*before write, iclass 34, count 0 2006.201.12:21:10.52#ibcon#enter sib2, iclass 34, count 0 2006.201.12:21:10.52#ibcon#flushed, iclass 34, count 0 2006.201.12:21:10.52#ibcon#about to write, iclass 34, count 0 2006.201.12:21:10.52#ibcon#wrote, iclass 34, count 0 2006.201.12:21:10.52#ibcon#about to read 3, iclass 34, count 0 2006.201.12:21:10.57#ibcon#read 3, iclass 34, count 0 2006.201.12:21:10.57#ibcon#about to read 4, iclass 34, count 0 2006.201.12:21:10.57#ibcon#read 4, iclass 34, count 0 2006.201.12:21:10.57#ibcon#about to read 5, iclass 34, count 0 2006.201.12:21:10.57#ibcon#read 5, iclass 34, count 0 2006.201.12:21:10.57#ibcon#about to read 6, iclass 34, count 0 2006.201.12:21:10.57#ibcon#read 6, iclass 34, count 0 2006.201.12:21:10.57#ibcon#end of sib2, iclass 34, count 0 2006.201.12:21:10.57#ibcon#*after write, iclass 34, count 0 2006.201.12:21:10.57#ibcon#*before return 0, iclass 34, count 0 2006.201.12:21:10.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:10.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:10.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:21:10.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:21:10.57$vck44/va=3,8 2006.201.12:21:10.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.12:21:10.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.12:21:10.57#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:10.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:10.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:10.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:10.62#ibcon#enter wrdev, iclass 36, count 2 2006.201.12:21:10.62#ibcon#first serial, iclass 36, count 2 2006.201.12:21:10.62#ibcon#enter sib2, iclass 36, count 2 2006.201.12:21:10.62#ibcon#flushed, iclass 36, count 2 2006.201.12:21:10.62#ibcon#about to write, iclass 36, count 2 2006.201.12:21:10.62#ibcon#wrote, iclass 36, count 2 2006.201.12:21:10.62#ibcon#about to read 3, iclass 36, count 2 2006.201.12:21:10.64#ibcon#read 3, iclass 36, count 2 2006.201.12:21:10.64#ibcon#about to read 4, iclass 36, count 2 2006.201.12:21:10.64#ibcon#read 4, iclass 36, count 2 2006.201.12:21:10.64#ibcon#about to read 5, iclass 36, count 2 2006.201.12:21:10.64#ibcon#read 5, iclass 36, count 2 2006.201.12:21:10.64#ibcon#about to read 6, iclass 36, count 2 2006.201.12:21:10.64#ibcon#read 6, iclass 36, count 2 2006.201.12:21:10.64#ibcon#end of sib2, iclass 36, count 2 2006.201.12:21:10.64#ibcon#*mode == 0, iclass 36, count 2 2006.201.12:21:10.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.12:21:10.64#ibcon#[25=AT03-08\r\n] 2006.201.12:21:10.64#ibcon#*before write, iclass 36, count 2 2006.201.12:21:10.64#ibcon#enter sib2, iclass 36, count 2 2006.201.12:21:10.64#ibcon#flushed, iclass 36, count 2 2006.201.12:21:10.64#ibcon#about to write, iclass 36, count 2 2006.201.12:21:10.64#ibcon#wrote, iclass 36, count 2 2006.201.12:21:10.64#ibcon#about to read 3, iclass 36, count 2 2006.201.12:21:10.67#ibcon#read 3, iclass 36, count 2 2006.201.12:21:10.67#ibcon#about to read 4, iclass 36, count 2 2006.201.12:21:10.67#ibcon#read 4, iclass 36, count 2 2006.201.12:21:10.67#ibcon#about to read 5, iclass 36, count 2 2006.201.12:21:10.67#ibcon#read 5, iclass 36, count 2 2006.201.12:21:10.67#ibcon#about to read 6, iclass 36, count 2 2006.201.12:21:10.67#ibcon#read 6, iclass 36, count 2 2006.201.12:21:10.67#ibcon#end of sib2, iclass 36, count 2 2006.201.12:21:10.67#ibcon#*after write, iclass 36, count 2 2006.201.12:21:10.67#ibcon#*before return 0, iclass 36, count 2 2006.201.12:21:10.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:10.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:10.67#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.12:21:10.67#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:10.67#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:10.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:10.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:10.79#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:21:10.79#ibcon#first serial, iclass 36, count 0 2006.201.12:21:10.79#ibcon#enter sib2, iclass 36, count 0 2006.201.12:21:10.79#ibcon#flushed, iclass 36, count 0 2006.201.12:21:10.79#ibcon#about to write, iclass 36, count 0 2006.201.12:21:10.79#ibcon#wrote, iclass 36, count 0 2006.201.12:21:10.79#ibcon#about to read 3, iclass 36, count 0 2006.201.12:21:10.81#ibcon#read 3, iclass 36, count 0 2006.201.12:21:10.81#ibcon#about to read 4, iclass 36, count 0 2006.201.12:21:10.81#ibcon#read 4, iclass 36, count 0 2006.201.12:21:10.81#ibcon#about to read 5, iclass 36, count 0 2006.201.12:21:10.81#ibcon#read 5, iclass 36, count 0 2006.201.12:21:10.81#ibcon#about to read 6, iclass 36, count 0 2006.201.12:21:10.81#ibcon#read 6, iclass 36, count 0 2006.201.12:21:10.81#ibcon#end of sib2, iclass 36, count 0 2006.201.12:21:10.81#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:21:10.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:21:10.81#ibcon#[25=USB\r\n] 2006.201.12:21:10.81#ibcon#*before write, iclass 36, count 0 2006.201.12:21:10.81#ibcon#enter sib2, iclass 36, count 0 2006.201.12:21:10.81#ibcon#flushed, iclass 36, count 0 2006.201.12:21:10.81#ibcon#about to write, iclass 36, count 0 2006.201.12:21:10.81#ibcon#wrote, iclass 36, count 0 2006.201.12:21:10.81#ibcon#about to read 3, iclass 36, count 0 2006.201.12:21:10.84#ibcon#read 3, iclass 36, count 0 2006.201.12:21:10.84#ibcon#about to read 4, iclass 36, count 0 2006.201.12:21:10.84#ibcon#read 4, iclass 36, count 0 2006.201.12:21:10.84#ibcon#about to read 5, iclass 36, count 0 2006.201.12:21:10.84#ibcon#read 5, iclass 36, count 0 2006.201.12:21:10.84#ibcon#about to read 6, iclass 36, count 0 2006.201.12:21:10.84#ibcon#read 6, iclass 36, count 0 2006.201.12:21:10.84#ibcon#end of sib2, iclass 36, count 0 2006.201.12:21:10.84#ibcon#*after write, iclass 36, count 0 2006.201.12:21:10.84#ibcon#*before return 0, iclass 36, count 0 2006.201.12:21:10.84#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:10.84#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:10.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:21:10.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:21:10.84$vck44/valo=4,624.99 2006.201.12:21:10.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.12:21:10.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.12:21:10.84#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:10.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:10.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:10.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:10.84#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:21:10.84#ibcon#first serial, iclass 38, count 0 2006.201.12:21:10.84#ibcon#enter sib2, iclass 38, count 0 2006.201.12:21:10.84#ibcon#flushed, iclass 38, count 0 2006.201.12:21:10.84#ibcon#about to write, iclass 38, count 0 2006.201.12:21:10.84#ibcon#wrote, iclass 38, count 0 2006.201.12:21:10.84#ibcon#about to read 3, iclass 38, count 0 2006.201.12:21:10.86#ibcon#read 3, iclass 38, count 0 2006.201.12:21:10.86#ibcon#about to read 4, iclass 38, count 0 2006.201.12:21:10.86#ibcon#read 4, iclass 38, count 0 2006.201.12:21:10.86#ibcon#about to read 5, iclass 38, count 0 2006.201.12:21:10.86#ibcon#read 5, iclass 38, count 0 2006.201.12:21:10.86#ibcon#about to read 6, iclass 38, count 0 2006.201.12:21:10.86#ibcon#read 6, iclass 38, count 0 2006.201.12:21:10.86#ibcon#end of sib2, iclass 38, count 0 2006.201.12:21:10.86#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:21:10.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:21:10.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:21:10.86#ibcon#*before write, iclass 38, count 0 2006.201.12:21:10.86#ibcon#enter sib2, iclass 38, count 0 2006.201.12:21:10.86#ibcon#flushed, iclass 38, count 0 2006.201.12:21:10.86#ibcon#about to write, iclass 38, count 0 2006.201.12:21:10.86#ibcon#wrote, iclass 38, count 0 2006.201.12:21:10.86#ibcon#about to read 3, iclass 38, count 0 2006.201.12:21:10.91#ibcon#read 3, iclass 38, count 0 2006.201.12:21:10.91#ibcon#about to read 4, iclass 38, count 0 2006.201.12:21:10.91#ibcon#read 4, iclass 38, count 0 2006.201.12:21:10.91#ibcon#about to read 5, iclass 38, count 0 2006.201.12:21:10.91#ibcon#read 5, iclass 38, count 0 2006.201.12:21:10.91#ibcon#about to read 6, iclass 38, count 0 2006.201.12:21:10.91#ibcon#read 6, iclass 38, count 0 2006.201.12:21:10.91#ibcon#end of sib2, iclass 38, count 0 2006.201.12:21:10.91#ibcon#*after write, iclass 38, count 0 2006.201.12:21:10.91#ibcon#*before return 0, iclass 38, count 0 2006.201.12:21:10.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:10.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:10.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:21:10.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:21:10.91$vck44/va=4,7 2006.201.12:21:10.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.12:21:10.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.12:21:10.91#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:10.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:10.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:10.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:10.96#ibcon#enter wrdev, iclass 40, count 2 2006.201.12:21:10.96#ibcon#first serial, iclass 40, count 2 2006.201.12:21:10.96#ibcon#enter sib2, iclass 40, count 2 2006.201.12:21:10.96#ibcon#flushed, iclass 40, count 2 2006.201.12:21:10.96#ibcon#about to write, iclass 40, count 2 2006.201.12:21:10.96#ibcon#wrote, iclass 40, count 2 2006.201.12:21:10.96#ibcon#about to read 3, iclass 40, count 2 2006.201.12:21:10.98#ibcon#read 3, iclass 40, count 2 2006.201.12:21:10.98#ibcon#about to read 4, iclass 40, count 2 2006.201.12:21:10.98#ibcon#read 4, iclass 40, count 2 2006.201.12:21:10.98#ibcon#about to read 5, iclass 40, count 2 2006.201.12:21:10.98#ibcon#read 5, iclass 40, count 2 2006.201.12:21:10.98#ibcon#about to read 6, iclass 40, count 2 2006.201.12:21:10.98#ibcon#read 6, iclass 40, count 2 2006.201.12:21:10.98#ibcon#end of sib2, iclass 40, count 2 2006.201.12:21:10.98#ibcon#*mode == 0, iclass 40, count 2 2006.201.12:21:10.98#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.12:21:10.98#ibcon#[25=AT04-07\r\n] 2006.201.12:21:10.98#ibcon#*before write, iclass 40, count 2 2006.201.12:21:10.98#ibcon#enter sib2, iclass 40, count 2 2006.201.12:21:10.98#ibcon#flushed, iclass 40, count 2 2006.201.12:21:10.98#ibcon#about to write, iclass 40, count 2 2006.201.12:21:10.98#ibcon#wrote, iclass 40, count 2 2006.201.12:21:10.98#ibcon#about to read 3, iclass 40, count 2 2006.201.12:21:11.01#ibcon#read 3, iclass 40, count 2 2006.201.12:21:11.01#ibcon#about to read 4, iclass 40, count 2 2006.201.12:21:11.01#ibcon#read 4, iclass 40, count 2 2006.201.12:21:11.01#ibcon#about to read 5, iclass 40, count 2 2006.201.12:21:11.01#ibcon#read 5, iclass 40, count 2 2006.201.12:21:11.01#ibcon#about to read 6, iclass 40, count 2 2006.201.12:21:11.01#ibcon#read 6, iclass 40, count 2 2006.201.12:21:11.01#ibcon#end of sib2, iclass 40, count 2 2006.201.12:21:11.01#ibcon#*after write, iclass 40, count 2 2006.201.12:21:11.01#ibcon#*before return 0, iclass 40, count 2 2006.201.12:21:11.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:11.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:11.01#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.12:21:11.01#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:11.01#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:11.13#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:11.13#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:11.13#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:21:11.13#ibcon#first serial, iclass 40, count 0 2006.201.12:21:11.13#ibcon#enter sib2, iclass 40, count 0 2006.201.12:21:11.13#ibcon#flushed, iclass 40, count 0 2006.201.12:21:11.13#ibcon#about to write, iclass 40, count 0 2006.201.12:21:11.13#ibcon#wrote, iclass 40, count 0 2006.201.12:21:11.13#ibcon#about to read 3, iclass 40, count 0 2006.201.12:21:11.15#ibcon#read 3, iclass 40, count 0 2006.201.12:21:11.15#ibcon#about to read 4, iclass 40, count 0 2006.201.12:21:11.15#ibcon#read 4, iclass 40, count 0 2006.201.12:21:11.15#ibcon#about to read 5, iclass 40, count 0 2006.201.12:21:11.15#ibcon#read 5, iclass 40, count 0 2006.201.12:21:11.15#ibcon#about to read 6, iclass 40, count 0 2006.201.12:21:11.15#ibcon#read 6, iclass 40, count 0 2006.201.12:21:11.15#ibcon#end of sib2, iclass 40, count 0 2006.201.12:21:11.15#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:21:11.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:21:11.15#ibcon#[25=USB\r\n] 2006.201.12:21:11.15#ibcon#*before write, iclass 40, count 0 2006.201.12:21:11.15#ibcon#enter sib2, iclass 40, count 0 2006.201.12:21:11.15#ibcon#flushed, iclass 40, count 0 2006.201.12:21:11.15#ibcon#about to write, iclass 40, count 0 2006.201.12:21:11.15#ibcon#wrote, iclass 40, count 0 2006.201.12:21:11.15#ibcon#about to read 3, iclass 40, count 0 2006.201.12:21:11.18#ibcon#read 3, iclass 40, count 0 2006.201.12:21:11.18#ibcon#about to read 4, iclass 40, count 0 2006.201.12:21:11.18#ibcon#read 4, iclass 40, count 0 2006.201.12:21:11.18#ibcon#about to read 5, iclass 40, count 0 2006.201.12:21:11.18#ibcon#read 5, iclass 40, count 0 2006.201.12:21:11.18#ibcon#about to read 6, iclass 40, count 0 2006.201.12:21:11.18#ibcon#read 6, iclass 40, count 0 2006.201.12:21:11.18#ibcon#end of sib2, iclass 40, count 0 2006.201.12:21:11.18#ibcon#*after write, iclass 40, count 0 2006.201.12:21:11.18#ibcon#*before return 0, iclass 40, count 0 2006.201.12:21:11.18#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:11.18#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:11.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:21:11.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:21:11.18$vck44/valo=5,734.99 2006.201.12:21:11.18#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.12:21:11.18#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.12:21:11.18#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:11.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:11.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:11.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:11.18#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:21:11.18#ibcon#first serial, iclass 4, count 0 2006.201.12:21:11.18#ibcon#enter sib2, iclass 4, count 0 2006.201.12:21:11.18#ibcon#flushed, iclass 4, count 0 2006.201.12:21:11.18#ibcon#about to write, iclass 4, count 0 2006.201.12:21:11.18#ibcon#wrote, iclass 4, count 0 2006.201.12:21:11.18#ibcon#about to read 3, iclass 4, count 0 2006.201.12:21:11.20#ibcon#read 3, iclass 4, count 0 2006.201.12:21:11.20#ibcon#about to read 4, iclass 4, count 0 2006.201.12:21:11.20#ibcon#read 4, iclass 4, count 0 2006.201.12:21:11.20#ibcon#about to read 5, iclass 4, count 0 2006.201.12:21:11.20#ibcon#read 5, iclass 4, count 0 2006.201.12:21:11.20#ibcon#about to read 6, iclass 4, count 0 2006.201.12:21:11.20#ibcon#read 6, iclass 4, count 0 2006.201.12:21:11.20#ibcon#end of sib2, iclass 4, count 0 2006.201.12:21:11.20#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:21:11.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:21:11.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:21:11.20#ibcon#*before write, iclass 4, count 0 2006.201.12:21:11.20#ibcon#enter sib2, iclass 4, count 0 2006.201.12:21:11.20#ibcon#flushed, iclass 4, count 0 2006.201.12:21:11.20#ibcon#about to write, iclass 4, count 0 2006.201.12:21:11.20#ibcon#wrote, iclass 4, count 0 2006.201.12:21:11.20#ibcon#about to read 3, iclass 4, count 0 2006.201.12:21:11.25#ibcon#read 3, iclass 4, count 0 2006.201.12:21:11.25#ibcon#about to read 4, iclass 4, count 0 2006.201.12:21:11.25#ibcon#read 4, iclass 4, count 0 2006.201.12:21:11.25#ibcon#about to read 5, iclass 4, count 0 2006.201.12:21:11.25#ibcon#read 5, iclass 4, count 0 2006.201.12:21:11.25#ibcon#about to read 6, iclass 4, count 0 2006.201.12:21:11.25#ibcon#read 6, iclass 4, count 0 2006.201.12:21:11.25#ibcon#end of sib2, iclass 4, count 0 2006.201.12:21:11.25#ibcon#*after write, iclass 4, count 0 2006.201.12:21:11.25#ibcon#*before return 0, iclass 4, count 0 2006.201.12:21:11.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:11.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:11.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:21:11.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:21:11.25$vck44/va=5,4 2006.201.12:21:11.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.12:21:11.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.12:21:11.25#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:11.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:11.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:11.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:11.30#ibcon#enter wrdev, iclass 6, count 2 2006.201.12:21:11.30#ibcon#first serial, iclass 6, count 2 2006.201.12:21:11.30#ibcon#enter sib2, iclass 6, count 2 2006.201.12:21:11.30#ibcon#flushed, iclass 6, count 2 2006.201.12:21:11.30#ibcon#about to write, iclass 6, count 2 2006.201.12:21:11.30#ibcon#wrote, iclass 6, count 2 2006.201.12:21:11.30#ibcon#about to read 3, iclass 6, count 2 2006.201.12:21:11.32#ibcon#read 3, iclass 6, count 2 2006.201.12:21:11.32#ibcon#about to read 4, iclass 6, count 2 2006.201.12:21:11.32#ibcon#read 4, iclass 6, count 2 2006.201.12:21:11.32#ibcon#about to read 5, iclass 6, count 2 2006.201.12:21:11.32#ibcon#read 5, iclass 6, count 2 2006.201.12:21:11.32#ibcon#about to read 6, iclass 6, count 2 2006.201.12:21:11.32#ibcon#read 6, iclass 6, count 2 2006.201.12:21:11.32#ibcon#end of sib2, iclass 6, count 2 2006.201.12:21:11.32#ibcon#*mode == 0, iclass 6, count 2 2006.201.12:21:11.32#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.12:21:11.32#ibcon#[25=AT05-04\r\n] 2006.201.12:21:11.32#ibcon#*before write, iclass 6, count 2 2006.201.12:21:11.32#ibcon#enter sib2, iclass 6, count 2 2006.201.12:21:11.32#ibcon#flushed, iclass 6, count 2 2006.201.12:21:11.32#ibcon#about to write, iclass 6, count 2 2006.201.12:21:11.32#ibcon#wrote, iclass 6, count 2 2006.201.12:21:11.32#ibcon#about to read 3, iclass 6, count 2 2006.201.12:21:11.35#ibcon#read 3, iclass 6, count 2 2006.201.12:21:11.35#ibcon#about to read 4, iclass 6, count 2 2006.201.12:21:11.35#ibcon#read 4, iclass 6, count 2 2006.201.12:21:11.35#ibcon#about to read 5, iclass 6, count 2 2006.201.12:21:11.35#ibcon#read 5, iclass 6, count 2 2006.201.12:21:11.35#ibcon#about to read 6, iclass 6, count 2 2006.201.12:21:11.35#ibcon#read 6, iclass 6, count 2 2006.201.12:21:11.35#ibcon#end of sib2, iclass 6, count 2 2006.201.12:21:11.35#ibcon#*after write, iclass 6, count 2 2006.201.12:21:11.35#ibcon#*before return 0, iclass 6, count 2 2006.201.12:21:11.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:11.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:11.35#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.12:21:11.35#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:11.35#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:11.47#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:11.47#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:11.47#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:21:11.47#ibcon#first serial, iclass 6, count 0 2006.201.12:21:11.47#ibcon#enter sib2, iclass 6, count 0 2006.201.12:21:11.47#ibcon#flushed, iclass 6, count 0 2006.201.12:21:11.47#ibcon#about to write, iclass 6, count 0 2006.201.12:21:11.47#ibcon#wrote, iclass 6, count 0 2006.201.12:21:11.47#ibcon#about to read 3, iclass 6, count 0 2006.201.12:21:11.49#ibcon#read 3, iclass 6, count 0 2006.201.12:21:11.49#ibcon#about to read 4, iclass 6, count 0 2006.201.12:21:11.49#ibcon#read 4, iclass 6, count 0 2006.201.12:21:11.49#ibcon#about to read 5, iclass 6, count 0 2006.201.12:21:11.49#ibcon#read 5, iclass 6, count 0 2006.201.12:21:11.49#ibcon#about to read 6, iclass 6, count 0 2006.201.12:21:11.49#ibcon#read 6, iclass 6, count 0 2006.201.12:21:11.49#ibcon#end of sib2, iclass 6, count 0 2006.201.12:21:11.49#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:21:11.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:21:11.49#ibcon#[25=USB\r\n] 2006.201.12:21:11.49#ibcon#*before write, iclass 6, count 0 2006.201.12:21:11.49#ibcon#enter sib2, iclass 6, count 0 2006.201.12:21:11.49#ibcon#flushed, iclass 6, count 0 2006.201.12:21:11.49#ibcon#about to write, iclass 6, count 0 2006.201.12:21:11.49#ibcon#wrote, iclass 6, count 0 2006.201.12:21:11.49#ibcon#about to read 3, iclass 6, count 0 2006.201.12:21:11.52#ibcon#read 3, iclass 6, count 0 2006.201.12:21:11.52#ibcon#about to read 4, iclass 6, count 0 2006.201.12:21:11.52#ibcon#read 4, iclass 6, count 0 2006.201.12:21:11.52#ibcon#about to read 5, iclass 6, count 0 2006.201.12:21:11.52#ibcon#read 5, iclass 6, count 0 2006.201.12:21:11.52#ibcon#about to read 6, iclass 6, count 0 2006.201.12:21:11.52#ibcon#read 6, iclass 6, count 0 2006.201.12:21:11.52#ibcon#end of sib2, iclass 6, count 0 2006.201.12:21:11.52#ibcon#*after write, iclass 6, count 0 2006.201.12:21:11.52#ibcon#*before return 0, iclass 6, count 0 2006.201.12:21:11.52#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:11.52#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:11.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:21:11.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:21:11.52$vck44/valo=6,814.99 2006.201.12:21:11.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.12:21:11.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.12:21:11.52#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:11.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:11.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:11.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:11.52#ibcon#enter wrdev, iclass 10, count 0 2006.201.12:21:11.52#ibcon#first serial, iclass 10, count 0 2006.201.12:21:11.52#ibcon#enter sib2, iclass 10, count 0 2006.201.12:21:11.52#ibcon#flushed, iclass 10, count 0 2006.201.12:21:11.52#ibcon#about to write, iclass 10, count 0 2006.201.12:21:11.52#ibcon#wrote, iclass 10, count 0 2006.201.12:21:11.52#ibcon#about to read 3, iclass 10, count 0 2006.201.12:21:11.54#ibcon#read 3, iclass 10, count 0 2006.201.12:21:11.54#ibcon#about to read 4, iclass 10, count 0 2006.201.12:21:11.54#ibcon#read 4, iclass 10, count 0 2006.201.12:21:11.54#ibcon#about to read 5, iclass 10, count 0 2006.201.12:21:11.54#ibcon#read 5, iclass 10, count 0 2006.201.12:21:11.54#ibcon#about to read 6, iclass 10, count 0 2006.201.12:21:11.54#ibcon#read 6, iclass 10, count 0 2006.201.12:21:11.54#ibcon#end of sib2, iclass 10, count 0 2006.201.12:21:11.54#ibcon#*mode == 0, iclass 10, count 0 2006.201.12:21:11.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.12:21:11.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:21:11.54#ibcon#*before write, iclass 10, count 0 2006.201.12:21:11.54#ibcon#enter sib2, iclass 10, count 0 2006.201.12:21:11.54#ibcon#flushed, iclass 10, count 0 2006.201.12:21:11.54#ibcon#about to write, iclass 10, count 0 2006.201.12:21:11.54#ibcon#wrote, iclass 10, count 0 2006.201.12:21:11.54#ibcon#about to read 3, iclass 10, count 0 2006.201.12:21:11.59#ibcon#read 3, iclass 10, count 0 2006.201.12:21:11.59#ibcon#about to read 4, iclass 10, count 0 2006.201.12:21:11.59#ibcon#read 4, iclass 10, count 0 2006.201.12:21:11.59#ibcon#about to read 5, iclass 10, count 0 2006.201.12:21:11.59#ibcon#read 5, iclass 10, count 0 2006.201.12:21:11.59#ibcon#about to read 6, iclass 10, count 0 2006.201.12:21:11.59#ibcon#read 6, iclass 10, count 0 2006.201.12:21:11.59#ibcon#end of sib2, iclass 10, count 0 2006.201.12:21:11.59#ibcon#*after write, iclass 10, count 0 2006.201.12:21:11.59#ibcon#*before return 0, iclass 10, count 0 2006.201.12:21:11.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:11.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:11.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.12:21:11.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.12:21:11.59$vck44/va=6,5 2006.201.12:21:11.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.12:21:11.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.12:21:11.59#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:11.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:11.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:11.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:11.64#ibcon#enter wrdev, iclass 12, count 2 2006.201.12:21:11.64#ibcon#first serial, iclass 12, count 2 2006.201.12:21:11.64#ibcon#enter sib2, iclass 12, count 2 2006.201.12:21:11.64#ibcon#flushed, iclass 12, count 2 2006.201.12:21:11.64#ibcon#about to write, iclass 12, count 2 2006.201.12:21:11.64#ibcon#wrote, iclass 12, count 2 2006.201.12:21:11.64#ibcon#about to read 3, iclass 12, count 2 2006.201.12:21:11.66#ibcon#read 3, iclass 12, count 2 2006.201.12:21:11.66#ibcon#about to read 4, iclass 12, count 2 2006.201.12:21:11.66#ibcon#read 4, iclass 12, count 2 2006.201.12:21:11.66#ibcon#about to read 5, iclass 12, count 2 2006.201.12:21:11.66#ibcon#read 5, iclass 12, count 2 2006.201.12:21:11.66#ibcon#about to read 6, iclass 12, count 2 2006.201.12:21:11.66#ibcon#read 6, iclass 12, count 2 2006.201.12:21:11.66#ibcon#end of sib2, iclass 12, count 2 2006.201.12:21:11.66#ibcon#*mode == 0, iclass 12, count 2 2006.201.12:21:11.66#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.12:21:11.66#ibcon#[25=AT06-05\r\n] 2006.201.12:21:11.66#ibcon#*before write, iclass 12, count 2 2006.201.12:21:11.66#ibcon#enter sib2, iclass 12, count 2 2006.201.12:21:11.66#ibcon#flushed, iclass 12, count 2 2006.201.12:21:11.66#ibcon#about to write, iclass 12, count 2 2006.201.12:21:11.66#ibcon#wrote, iclass 12, count 2 2006.201.12:21:11.66#ibcon#about to read 3, iclass 12, count 2 2006.201.12:21:11.69#ibcon#read 3, iclass 12, count 2 2006.201.12:21:11.69#ibcon#about to read 4, iclass 12, count 2 2006.201.12:21:11.69#ibcon#read 4, iclass 12, count 2 2006.201.12:21:11.69#ibcon#about to read 5, iclass 12, count 2 2006.201.12:21:11.69#ibcon#read 5, iclass 12, count 2 2006.201.12:21:11.69#ibcon#about to read 6, iclass 12, count 2 2006.201.12:21:11.69#ibcon#read 6, iclass 12, count 2 2006.201.12:21:11.69#ibcon#end of sib2, iclass 12, count 2 2006.201.12:21:11.69#ibcon#*after write, iclass 12, count 2 2006.201.12:21:11.69#ibcon#*before return 0, iclass 12, count 2 2006.201.12:21:11.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:11.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:11.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.12:21:11.69#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:11.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:11.81#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:11.81#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:11.81#ibcon#enter wrdev, iclass 12, count 0 2006.201.12:21:11.81#ibcon#first serial, iclass 12, count 0 2006.201.12:21:11.81#ibcon#enter sib2, iclass 12, count 0 2006.201.12:21:11.81#ibcon#flushed, iclass 12, count 0 2006.201.12:21:11.81#ibcon#about to write, iclass 12, count 0 2006.201.12:21:11.81#ibcon#wrote, iclass 12, count 0 2006.201.12:21:11.81#ibcon#about to read 3, iclass 12, count 0 2006.201.12:21:11.83#ibcon#read 3, iclass 12, count 0 2006.201.12:21:11.83#ibcon#about to read 4, iclass 12, count 0 2006.201.12:21:11.83#ibcon#read 4, iclass 12, count 0 2006.201.12:21:11.83#ibcon#about to read 5, iclass 12, count 0 2006.201.12:21:11.83#ibcon#read 5, iclass 12, count 0 2006.201.12:21:11.83#ibcon#about to read 6, iclass 12, count 0 2006.201.12:21:11.83#ibcon#read 6, iclass 12, count 0 2006.201.12:21:11.83#ibcon#end of sib2, iclass 12, count 0 2006.201.12:21:11.83#ibcon#*mode == 0, iclass 12, count 0 2006.201.12:21:11.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.12:21:11.83#ibcon#[25=USB\r\n] 2006.201.12:21:11.83#ibcon#*before write, iclass 12, count 0 2006.201.12:21:11.83#ibcon#enter sib2, iclass 12, count 0 2006.201.12:21:11.83#ibcon#flushed, iclass 12, count 0 2006.201.12:21:11.83#ibcon#about to write, iclass 12, count 0 2006.201.12:21:11.83#ibcon#wrote, iclass 12, count 0 2006.201.12:21:11.83#ibcon#about to read 3, iclass 12, count 0 2006.201.12:21:11.86#ibcon#read 3, iclass 12, count 0 2006.201.12:21:11.86#ibcon#about to read 4, iclass 12, count 0 2006.201.12:21:11.86#ibcon#read 4, iclass 12, count 0 2006.201.12:21:11.86#ibcon#about to read 5, iclass 12, count 0 2006.201.12:21:11.86#ibcon#read 5, iclass 12, count 0 2006.201.12:21:11.86#ibcon#about to read 6, iclass 12, count 0 2006.201.12:21:11.86#ibcon#read 6, iclass 12, count 0 2006.201.12:21:11.86#ibcon#end of sib2, iclass 12, count 0 2006.201.12:21:11.86#ibcon#*after write, iclass 12, count 0 2006.201.12:21:11.86#ibcon#*before return 0, iclass 12, count 0 2006.201.12:21:11.86#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:11.86#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:11.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.12:21:11.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.12:21:11.86$vck44/valo=7,864.99 2006.201.12:21:11.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.12:21:11.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.12:21:11.86#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:11.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:11.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:11.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:11.86#ibcon#enter wrdev, iclass 14, count 0 2006.201.12:21:11.86#ibcon#first serial, iclass 14, count 0 2006.201.12:21:11.86#ibcon#enter sib2, iclass 14, count 0 2006.201.12:21:11.86#ibcon#flushed, iclass 14, count 0 2006.201.12:21:11.86#ibcon#about to write, iclass 14, count 0 2006.201.12:21:11.86#ibcon#wrote, iclass 14, count 0 2006.201.12:21:11.86#ibcon#about to read 3, iclass 14, count 0 2006.201.12:21:11.88#ibcon#read 3, iclass 14, count 0 2006.201.12:21:11.88#ibcon#about to read 4, iclass 14, count 0 2006.201.12:21:11.88#ibcon#read 4, iclass 14, count 0 2006.201.12:21:11.88#ibcon#about to read 5, iclass 14, count 0 2006.201.12:21:11.88#ibcon#read 5, iclass 14, count 0 2006.201.12:21:11.88#ibcon#about to read 6, iclass 14, count 0 2006.201.12:21:11.88#ibcon#read 6, iclass 14, count 0 2006.201.12:21:11.88#ibcon#end of sib2, iclass 14, count 0 2006.201.12:21:11.88#ibcon#*mode == 0, iclass 14, count 0 2006.201.12:21:11.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.12:21:11.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:21:11.88#ibcon#*before write, iclass 14, count 0 2006.201.12:21:11.88#ibcon#enter sib2, iclass 14, count 0 2006.201.12:21:11.88#ibcon#flushed, iclass 14, count 0 2006.201.12:21:11.88#ibcon#about to write, iclass 14, count 0 2006.201.12:21:11.88#ibcon#wrote, iclass 14, count 0 2006.201.12:21:11.88#ibcon#about to read 3, iclass 14, count 0 2006.201.12:21:11.93#ibcon#read 3, iclass 14, count 0 2006.201.12:21:11.93#ibcon#about to read 4, iclass 14, count 0 2006.201.12:21:11.93#ibcon#read 4, iclass 14, count 0 2006.201.12:21:11.93#ibcon#about to read 5, iclass 14, count 0 2006.201.12:21:11.93#ibcon#read 5, iclass 14, count 0 2006.201.12:21:11.93#ibcon#about to read 6, iclass 14, count 0 2006.201.12:21:11.93#ibcon#read 6, iclass 14, count 0 2006.201.12:21:11.93#ibcon#end of sib2, iclass 14, count 0 2006.201.12:21:11.93#ibcon#*after write, iclass 14, count 0 2006.201.12:21:11.93#ibcon#*before return 0, iclass 14, count 0 2006.201.12:21:11.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:11.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:11.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.12:21:11.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.12:21:11.93$vck44/va=7,5 2006.201.12:21:11.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.12:21:11.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.12:21:11.93#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:11.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:11.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:11.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:11.98#ibcon#enter wrdev, iclass 16, count 2 2006.201.12:21:11.98#ibcon#first serial, iclass 16, count 2 2006.201.12:21:11.98#ibcon#enter sib2, iclass 16, count 2 2006.201.12:21:11.98#ibcon#flushed, iclass 16, count 2 2006.201.12:21:11.98#ibcon#about to write, iclass 16, count 2 2006.201.12:21:11.98#ibcon#wrote, iclass 16, count 2 2006.201.12:21:11.98#ibcon#about to read 3, iclass 16, count 2 2006.201.12:21:12.00#ibcon#read 3, iclass 16, count 2 2006.201.12:21:12.00#ibcon#about to read 4, iclass 16, count 2 2006.201.12:21:12.00#ibcon#read 4, iclass 16, count 2 2006.201.12:21:12.00#ibcon#about to read 5, iclass 16, count 2 2006.201.12:21:12.00#ibcon#read 5, iclass 16, count 2 2006.201.12:21:12.00#ibcon#about to read 6, iclass 16, count 2 2006.201.12:21:12.00#ibcon#read 6, iclass 16, count 2 2006.201.12:21:12.00#ibcon#end of sib2, iclass 16, count 2 2006.201.12:21:12.00#ibcon#*mode == 0, iclass 16, count 2 2006.201.12:21:12.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.12:21:12.00#ibcon#[25=AT07-05\r\n] 2006.201.12:21:12.00#ibcon#*before write, iclass 16, count 2 2006.201.12:21:12.00#ibcon#enter sib2, iclass 16, count 2 2006.201.12:21:12.00#ibcon#flushed, iclass 16, count 2 2006.201.12:21:12.00#ibcon#about to write, iclass 16, count 2 2006.201.12:21:12.00#ibcon#wrote, iclass 16, count 2 2006.201.12:21:12.00#ibcon#about to read 3, iclass 16, count 2 2006.201.12:21:12.03#ibcon#read 3, iclass 16, count 2 2006.201.12:21:12.03#ibcon#about to read 4, iclass 16, count 2 2006.201.12:21:12.03#ibcon#read 4, iclass 16, count 2 2006.201.12:21:12.03#ibcon#about to read 5, iclass 16, count 2 2006.201.12:21:12.03#ibcon#read 5, iclass 16, count 2 2006.201.12:21:12.03#ibcon#about to read 6, iclass 16, count 2 2006.201.12:21:12.03#ibcon#read 6, iclass 16, count 2 2006.201.12:21:12.03#ibcon#end of sib2, iclass 16, count 2 2006.201.12:21:12.03#ibcon#*after write, iclass 16, count 2 2006.201.12:21:12.03#ibcon#*before return 0, iclass 16, count 2 2006.201.12:21:12.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:12.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:12.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.12:21:12.03#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:12.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:12.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:12.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:12.15#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:21:12.15#ibcon#first serial, iclass 16, count 0 2006.201.12:21:12.15#ibcon#enter sib2, iclass 16, count 0 2006.201.12:21:12.15#ibcon#flushed, iclass 16, count 0 2006.201.12:21:12.15#ibcon#about to write, iclass 16, count 0 2006.201.12:21:12.15#ibcon#wrote, iclass 16, count 0 2006.201.12:21:12.15#ibcon#about to read 3, iclass 16, count 0 2006.201.12:21:12.17#ibcon#read 3, iclass 16, count 0 2006.201.12:21:12.17#ibcon#about to read 4, iclass 16, count 0 2006.201.12:21:12.17#ibcon#read 4, iclass 16, count 0 2006.201.12:21:12.17#ibcon#about to read 5, iclass 16, count 0 2006.201.12:21:12.17#ibcon#read 5, iclass 16, count 0 2006.201.12:21:12.17#ibcon#about to read 6, iclass 16, count 0 2006.201.12:21:12.17#ibcon#read 6, iclass 16, count 0 2006.201.12:21:12.17#ibcon#end of sib2, iclass 16, count 0 2006.201.12:21:12.17#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:21:12.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:21:12.17#ibcon#[25=USB\r\n] 2006.201.12:21:12.17#ibcon#*before write, iclass 16, count 0 2006.201.12:21:12.17#ibcon#enter sib2, iclass 16, count 0 2006.201.12:21:12.17#ibcon#flushed, iclass 16, count 0 2006.201.12:21:12.17#ibcon#about to write, iclass 16, count 0 2006.201.12:21:12.17#ibcon#wrote, iclass 16, count 0 2006.201.12:21:12.17#ibcon#about to read 3, iclass 16, count 0 2006.201.12:21:12.20#ibcon#read 3, iclass 16, count 0 2006.201.12:21:12.20#ibcon#about to read 4, iclass 16, count 0 2006.201.12:21:12.20#ibcon#read 4, iclass 16, count 0 2006.201.12:21:12.20#ibcon#about to read 5, iclass 16, count 0 2006.201.12:21:12.20#ibcon#read 5, iclass 16, count 0 2006.201.12:21:12.20#ibcon#about to read 6, iclass 16, count 0 2006.201.12:21:12.20#ibcon#read 6, iclass 16, count 0 2006.201.12:21:12.20#ibcon#end of sib2, iclass 16, count 0 2006.201.12:21:12.20#ibcon#*after write, iclass 16, count 0 2006.201.12:21:12.20#ibcon#*before return 0, iclass 16, count 0 2006.201.12:21:12.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:12.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:12.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:21:12.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:21:12.20$vck44/valo=8,884.99 2006.201.12:21:12.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.12:21:12.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.12:21:12.20#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:12.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:12.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:12.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:12.20#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:21:12.20#ibcon#first serial, iclass 18, count 0 2006.201.12:21:12.20#ibcon#enter sib2, iclass 18, count 0 2006.201.12:21:12.20#ibcon#flushed, iclass 18, count 0 2006.201.12:21:12.20#ibcon#about to write, iclass 18, count 0 2006.201.12:21:12.20#ibcon#wrote, iclass 18, count 0 2006.201.12:21:12.20#ibcon#about to read 3, iclass 18, count 0 2006.201.12:21:12.22#ibcon#read 3, iclass 18, count 0 2006.201.12:21:12.22#ibcon#about to read 4, iclass 18, count 0 2006.201.12:21:12.22#ibcon#read 4, iclass 18, count 0 2006.201.12:21:12.22#ibcon#about to read 5, iclass 18, count 0 2006.201.12:21:12.22#ibcon#read 5, iclass 18, count 0 2006.201.12:21:12.22#ibcon#about to read 6, iclass 18, count 0 2006.201.12:21:12.22#ibcon#read 6, iclass 18, count 0 2006.201.12:21:12.22#ibcon#end of sib2, iclass 18, count 0 2006.201.12:21:12.22#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:21:12.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:21:12.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:21:12.22#ibcon#*before write, iclass 18, count 0 2006.201.12:21:12.22#ibcon#enter sib2, iclass 18, count 0 2006.201.12:21:12.22#ibcon#flushed, iclass 18, count 0 2006.201.12:21:12.22#ibcon#about to write, iclass 18, count 0 2006.201.12:21:12.22#ibcon#wrote, iclass 18, count 0 2006.201.12:21:12.22#ibcon#about to read 3, iclass 18, count 0 2006.201.12:21:12.26#ibcon#read 3, iclass 18, count 0 2006.201.12:21:12.26#ibcon#about to read 4, iclass 18, count 0 2006.201.12:21:12.26#ibcon#read 4, iclass 18, count 0 2006.201.12:21:12.26#ibcon#about to read 5, iclass 18, count 0 2006.201.12:21:12.26#ibcon#read 5, iclass 18, count 0 2006.201.12:21:12.26#ibcon#about to read 6, iclass 18, count 0 2006.201.12:21:12.26#ibcon#read 6, iclass 18, count 0 2006.201.12:21:12.26#ibcon#end of sib2, iclass 18, count 0 2006.201.12:21:12.26#ibcon#*after write, iclass 18, count 0 2006.201.12:21:12.26#ibcon#*before return 0, iclass 18, count 0 2006.201.12:21:12.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:12.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:12.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:21:12.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:21:12.26$vck44/va=8,4 2006.201.12:21:12.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.12:21:12.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.12:21:12.26#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:12.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:21:12.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:21:12.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:21:12.32#ibcon#enter wrdev, iclass 20, count 2 2006.201.12:21:12.32#ibcon#first serial, iclass 20, count 2 2006.201.12:21:12.32#ibcon#enter sib2, iclass 20, count 2 2006.201.12:21:12.32#ibcon#flushed, iclass 20, count 2 2006.201.12:21:12.32#ibcon#about to write, iclass 20, count 2 2006.201.12:21:12.32#ibcon#wrote, iclass 20, count 2 2006.201.12:21:12.32#ibcon#about to read 3, iclass 20, count 2 2006.201.12:21:12.34#ibcon#read 3, iclass 20, count 2 2006.201.12:21:12.34#ibcon#about to read 4, iclass 20, count 2 2006.201.12:21:12.34#ibcon#read 4, iclass 20, count 2 2006.201.12:21:12.34#ibcon#about to read 5, iclass 20, count 2 2006.201.12:21:12.34#ibcon#read 5, iclass 20, count 2 2006.201.12:21:12.34#ibcon#about to read 6, iclass 20, count 2 2006.201.12:21:12.34#ibcon#read 6, iclass 20, count 2 2006.201.12:21:12.34#ibcon#end of sib2, iclass 20, count 2 2006.201.12:21:12.34#ibcon#*mode == 0, iclass 20, count 2 2006.201.12:21:12.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.12:21:12.34#ibcon#[25=AT08-04\r\n] 2006.201.12:21:12.34#ibcon#*before write, iclass 20, count 2 2006.201.12:21:12.34#ibcon#enter sib2, iclass 20, count 2 2006.201.12:21:12.34#ibcon#flushed, iclass 20, count 2 2006.201.12:21:12.34#ibcon#about to write, iclass 20, count 2 2006.201.12:21:12.34#ibcon#wrote, iclass 20, count 2 2006.201.12:21:12.34#ibcon#about to read 3, iclass 20, count 2 2006.201.12:21:12.37#ibcon#read 3, iclass 20, count 2 2006.201.12:21:12.37#ibcon#about to read 4, iclass 20, count 2 2006.201.12:21:12.37#ibcon#read 4, iclass 20, count 2 2006.201.12:21:12.37#ibcon#about to read 5, iclass 20, count 2 2006.201.12:21:12.37#ibcon#read 5, iclass 20, count 2 2006.201.12:21:12.37#ibcon#about to read 6, iclass 20, count 2 2006.201.12:21:12.37#ibcon#read 6, iclass 20, count 2 2006.201.12:21:12.37#ibcon#end of sib2, iclass 20, count 2 2006.201.12:21:12.37#ibcon#*after write, iclass 20, count 2 2006.201.12:21:12.37#ibcon#*before return 0, iclass 20, count 2 2006.201.12:21:12.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:21:12.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.12:21:12.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.12:21:12.37#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:12.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:21:12.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:21:12.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:21:12.49#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:21:12.49#ibcon#first serial, iclass 20, count 0 2006.201.12:21:12.49#ibcon#enter sib2, iclass 20, count 0 2006.201.12:21:12.49#ibcon#flushed, iclass 20, count 0 2006.201.12:21:12.49#ibcon#about to write, iclass 20, count 0 2006.201.12:21:12.49#ibcon#wrote, iclass 20, count 0 2006.201.12:21:12.49#ibcon#about to read 3, iclass 20, count 0 2006.201.12:21:12.51#ibcon#read 3, iclass 20, count 0 2006.201.12:21:12.51#ibcon#about to read 4, iclass 20, count 0 2006.201.12:21:12.51#ibcon#read 4, iclass 20, count 0 2006.201.12:21:12.51#ibcon#about to read 5, iclass 20, count 0 2006.201.12:21:12.51#ibcon#read 5, iclass 20, count 0 2006.201.12:21:12.51#ibcon#about to read 6, iclass 20, count 0 2006.201.12:21:12.51#ibcon#read 6, iclass 20, count 0 2006.201.12:21:12.51#ibcon#end of sib2, iclass 20, count 0 2006.201.12:21:12.51#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:21:12.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:21:12.51#ibcon#[25=USB\r\n] 2006.201.12:21:12.51#ibcon#*before write, iclass 20, count 0 2006.201.12:21:12.51#ibcon#enter sib2, iclass 20, count 0 2006.201.12:21:12.51#ibcon#flushed, iclass 20, count 0 2006.201.12:21:12.51#ibcon#about to write, iclass 20, count 0 2006.201.12:21:12.51#ibcon#wrote, iclass 20, count 0 2006.201.12:21:12.51#ibcon#about to read 3, iclass 20, count 0 2006.201.12:21:12.54#ibcon#read 3, iclass 20, count 0 2006.201.12:21:12.54#ibcon#about to read 4, iclass 20, count 0 2006.201.12:21:12.54#ibcon#read 4, iclass 20, count 0 2006.201.12:21:12.54#ibcon#about to read 5, iclass 20, count 0 2006.201.12:21:12.54#ibcon#read 5, iclass 20, count 0 2006.201.12:21:12.54#ibcon#about to read 6, iclass 20, count 0 2006.201.12:21:12.54#ibcon#read 6, iclass 20, count 0 2006.201.12:21:12.54#ibcon#end of sib2, iclass 20, count 0 2006.201.12:21:12.54#ibcon#*after write, iclass 20, count 0 2006.201.12:21:12.54#ibcon#*before return 0, iclass 20, count 0 2006.201.12:21:12.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:21:12.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.12:21:12.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:21:12.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:21:12.54$vck44/vblo=1,629.99 2006.201.12:21:12.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.12:21:12.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.12:21:12.54#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:12.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:12.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:12.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:12.54#ibcon#enter wrdev, iclass 22, count 0 2006.201.12:21:12.54#ibcon#first serial, iclass 22, count 0 2006.201.12:21:12.54#ibcon#enter sib2, iclass 22, count 0 2006.201.12:21:12.54#ibcon#flushed, iclass 22, count 0 2006.201.12:21:12.54#ibcon#about to write, iclass 22, count 0 2006.201.12:21:12.54#ibcon#wrote, iclass 22, count 0 2006.201.12:21:12.54#ibcon#about to read 3, iclass 22, count 0 2006.201.12:21:12.56#ibcon#read 3, iclass 22, count 0 2006.201.12:21:12.56#ibcon#about to read 4, iclass 22, count 0 2006.201.12:21:12.56#ibcon#read 4, iclass 22, count 0 2006.201.12:21:12.56#ibcon#about to read 5, iclass 22, count 0 2006.201.12:21:12.56#ibcon#read 5, iclass 22, count 0 2006.201.12:21:12.56#ibcon#about to read 6, iclass 22, count 0 2006.201.12:21:12.56#ibcon#read 6, iclass 22, count 0 2006.201.12:21:12.56#ibcon#end of sib2, iclass 22, count 0 2006.201.12:21:12.56#ibcon#*mode == 0, iclass 22, count 0 2006.201.12:21:12.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.12:21:12.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:21:12.56#ibcon#*before write, iclass 22, count 0 2006.201.12:21:12.56#ibcon#enter sib2, iclass 22, count 0 2006.201.12:21:12.56#ibcon#flushed, iclass 22, count 0 2006.201.12:21:12.56#ibcon#about to write, iclass 22, count 0 2006.201.12:21:12.56#ibcon#wrote, iclass 22, count 0 2006.201.12:21:12.56#ibcon#about to read 3, iclass 22, count 0 2006.201.12:21:12.61#ibcon#read 3, iclass 22, count 0 2006.201.12:21:12.61#ibcon#about to read 4, iclass 22, count 0 2006.201.12:21:12.61#ibcon#read 4, iclass 22, count 0 2006.201.12:21:12.61#ibcon#about to read 5, iclass 22, count 0 2006.201.12:21:12.61#ibcon#read 5, iclass 22, count 0 2006.201.12:21:12.61#ibcon#about to read 6, iclass 22, count 0 2006.201.12:21:12.61#ibcon#read 6, iclass 22, count 0 2006.201.12:21:12.61#ibcon#end of sib2, iclass 22, count 0 2006.201.12:21:12.61#ibcon#*after write, iclass 22, count 0 2006.201.12:21:12.61#ibcon#*before return 0, iclass 22, count 0 2006.201.12:21:12.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:12.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.12:21:12.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.12:21:12.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.12:21:12.61$vck44/vb=1,4 2006.201.12:21:12.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.12:21:12.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.12:21:12.61#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:12.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:21:12.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:21:12.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:21:12.61#ibcon#enter wrdev, iclass 24, count 2 2006.201.12:21:12.61#ibcon#first serial, iclass 24, count 2 2006.201.12:21:12.61#ibcon#enter sib2, iclass 24, count 2 2006.201.12:21:12.61#ibcon#flushed, iclass 24, count 2 2006.201.12:21:12.61#ibcon#about to write, iclass 24, count 2 2006.201.12:21:12.61#ibcon#wrote, iclass 24, count 2 2006.201.12:21:12.61#ibcon#about to read 3, iclass 24, count 2 2006.201.12:21:12.63#ibcon#read 3, iclass 24, count 2 2006.201.12:21:12.63#ibcon#about to read 4, iclass 24, count 2 2006.201.12:21:12.63#ibcon#read 4, iclass 24, count 2 2006.201.12:21:12.63#ibcon#about to read 5, iclass 24, count 2 2006.201.12:21:12.63#ibcon#read 5, iclass 24, count 2 2006.201.12:21:12.63#ibcon#about to read 6, iclass 24, count 2 2006.201.12:21:12.63#ibcon#read 6, iclass 24, count 2 2006.201.12:21:12.63#ibcon#end of sib2, iclass 24, count 2 2006.201.12:21:12.63#ibcon#*mode == 0, iclass 24, count 2 2006.201.12:21:12.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.12:21:12.63#ibcon#[27=AT01-04\r\n] 2006.201.12:21:12.63#ibcon#*before write, iclass 24, count 2 2006.201.12:21:12.63#ibcon#enter sib2, iclass 24, count 2 2006.201.12:21:12.63#ibcon#flushed, iclass 24, count 2 2006.201.12:21:12.63#ibcon#about to write, iclass 24, count 2 2006.201.12:21:12.63#ibcon#wrote, iclass 24, count 2 2006.201.12:21:12.63#ibcon#about to read 3, iclass 24, count 2 2006.201.12:21:12.66#ibcon#read 3, iclass 24, count 2 2006.201.12:21:12.66#ibcon#about to read 4, iclass 24, count 2 2006.201.12:21:12.66#ibcon#read 4, iclass 24, count 2 2006.201.12:21:12.66#ibcon#about to read 5, iclass 24, count 2 2006.201.12:21:12.66#ibcon#read 5, iclass 24, count 2 2006.201.12:21:12.66#ibcon#about to read 6, iclass 24, count 2 2006.201.12:21:12.66#ibcon#read 6, iclass 24, count 2 2006.201.12:21:12.66#ibcon#end of sib2, iclass 24, count 2 2006.201.12:21:12.66#ibcon#*after write, iclass 24, count 2 2006.201.12:21:12.66#ibcon#*before return 0, iclass 24, count 2 2006.201.12:21:12.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:21:12.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.12:21:12.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.12:21:12.66#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:12.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:21:12.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:21:12.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:21:12.78#ibcon#enter wrdev, iclass 24, count 0 2006.201.12:21:12.78#ibcon#first serial, iclass 24, count 0 2006.201.12:21:12.78#ibcon#enter sib2, iclass 24, count 0 2006.201.12:21:12.78#ibcon#flushed, iclass 24, count 0 2006.201.12:21:12.78#ibcon#about to write, iclass 24, count 0 2006.201.12:21:12.78#ibcon#wrote, iclass 24, count 0 2006.201.12:21:12.78#ibcon#about to read 3, iclass 24, count 0 2006.201.12:21:12.80#ibcon#read 3, iclass 24, count 0 2006.201.12:21:12.80#ibcon#about to read 4, iclass 24, count 0 2006.201.12:21:12.80#ibcon#read 4, iclass 24, count 0 2006.201.12:21:12.80#ibcon#about to read 5, iclass 24, count 0 2006.201.12:21:12.80#ibcon#read 5, iclass 24, count 0 2006.201.12:21:12.80#ibcon#about to read 6, iclass 24, count 0 2006.201.12:21:12.80#ibcon#read 6, iclass 24, count 0 2006.201.12:21:12.80#ibcon#end of sib2, iclass 24, count 0 2006.201.12:21:12.80#ibcon#*mode == 0, iclass 24, count 0 2006.201.12:21:12.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.12:21:12.80#ibcon#[27=USB\r\n] 2006.201.12:21:12.80#ibcon#*before write, iclass 24, count 0 2006.201.12:21:12.80#ibcon#enter sib2, iclass 24, count 0 2006.201.12:21:12.80#ibcon#flushed, iclass 24, count 0 2006.201.12:21:12.80#ibcon#about to write, iclass 24, count 0 2006.201.12:21:12.80#ibcon#wrote, iclass 24, count 0 2006.201.12:21:12.80#ibcon#about to read 3, iclass 24, count 0 2006.201.12:21:12.83#ibcon#read 3, iclass 24, count 0 2006.201.12:21:12.83#ibcon#about to read 4, iclass 24, count 0 2006.201.12:21:12.83#ibcon#read 4, iclass 24, count 0 2006.201.12:21:12.83#ibcon#about to read 5, iclass 24, count 0 2006.201.12:21:12.83#ibcon#read 5, iclass 24, count 0 2006.201.12:21:12.83#ibcon#about to read 6, iclass 24, count 0 2006.201.12:21:12.83#ibcon#read 6, iclass 24, count 0 2006.201.12:21:12.83#ibcon#end of sib2, iclass 24, count 0 2006.201.12:21:12.83#ibcon#*after write, iclass 24, count 0 2006.201.12:21:12.83#ibcon#*before return 0, iclass 24, count 0 2006.201.12:21:12.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:21:12.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.12:21:12.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.12:21:12.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.12:21:12.83$vck44/vblo=2,634.99 2006.201.12:21:12.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.12:21:12.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.12:21:12.83#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:12.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:21:12.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:21:12.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:21:12.83#ibcon#enter wrdev, iclass 26, count 0 2006.201.12:21:12.83#ibcon#first serial, iclass 26, count 0 2006.201.12:21:12.83#ibcon#enter sib2, iclass 26, count 0 2006.201.12:21:12.83#ibcon#flushed, iclass 26, count 0 2006.201.12:21:12.83#ibcon#about to write, iclass 26, count 0 2006.201.12:21:12.83#ibcon#wrote, iclass 26, count 0 2006.201.12:21:12.83#ibcon#about to read 3, iclass 26, count 0 2006.201.12:21:12.85#ibcon#read 3, iclass 26, count 0 2006.201.12:21:12.85#ibcon#about to read 4, iclass 26, count 0 2006.201.12:21:12.85#ibcon#read 4, iclass 26, count 0 2006.201.12:21:12.85#ibcon#about to read 5, iclass 26, count 0 2006.201.12:21:12.85#ibcon#read 5, iclass 26, count 0 2006.201.12:21:12.85#ibcon#about to read 6, iclass 26, count 0 2006.201.12:21:12.85#ibcon#read 6, iclass 26, count 0 2006.201.12:21:12.85#ibcon#end of sib2, iclass 26, count 0 2006.201.12:21:12.85#ibcon#*mode == 0, iclass 26, count 0 2006.201.12:21:12.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.12:21:12.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:21:12.85#ibcon#*before write, iclass 26, count 0 2006.201.12:21:12.85#ibcon#enter sib2, iclass 26, count 0 2006.201.12:21:12.85#ibcon#flushed, iclass 26, count 0 2006.201.12:21:12.85#ibcon#about to write, iclass 26, count 0 2006.201.12:21:12.85#ibcon#wrote, iclass 26, count 0 2006.201.12:21:12.85#ibcon#about to read 3, iclass 26, count 0 2006.201.12:21:12.89#ibcon#read 3, iclass 26, count 0 2006.201.12:21:12.89#ibcon#about to read 4, iclass 26, count 0 2006.201.12:21:12.89#ibcon#read 4, iclass 26, count 0 2006.201.12:21:12.89#ibcon#about to read 5, iclass 26, count 0 2006.201.12:21:12.89#ibcon#read 5, iclass 26, count 0 2006.201.12:21:12.89#ibcon#about to read 6, iclass 26, count 0 2006.201.12:21:12.89#ibcon#read 6, iclass 26, count 0 2006.201.12:21:12.89#ibcon#end of sib2, iclass 26, count 0 2006.201.12:21:12.89#ibcon#*after write, iclass 26, count 0 2006.201.12:21:12.89#ibcon#*before return 0, iclass 26, count 0 2006.201.12:21:12.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:21:12.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.12:21:12.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.12:21:12.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.12:21:12.89$vck44/vb=2,5 2006.201.12:21:12.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.12:21:12.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.12:21:12.89#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:12.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:21:12.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:21:12.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:21:12.95#ibcon#enter wrdev, iclass 28, count 2 2006.201.12:21:12.95#ibcon#first serial, iclass 28, count 2 2006.201.12:21:12.95#ibcon#enter sib2, iclass 28, count 2 2006.201.12:21:12.95#ibcon#flushed, iclass 28, count 2 2006.201.12:21:12.95#ibcon#about to write, iclass 28, count 2 2006.201.12:21:12.95#ibcon#wrote, iclass 28, count 2 2006.201.12:21:12.95#ibcon#about to read 3, iclass 28, count 2 2006.201.12:21:12.97#ibcon#read 3, iclass 28, count 2 2006.201.12:21:12.97#ibcon#about to read 4, iclass 28, count 2 2006.201.12:21:12.97#ibcon#read 4, iclass 28, count 2 2006.201.12:21:12.97#ibcon#about to read 5, iclass 28, count 2 2006.201.12:21:12.97#ibcon#read 5, iclass 28, count 2 2006.201.12:21:12.97#ibcon#about to read 6, iclass 28, count 2 2006.201.12:21:12.97#ibcon#read 6, iclass 28, count 2 2006.201.12:21:12.97#ibcon#end of sib2, iclass 28, count 2 2006.201.12:21:12.97#ibcon#*mode == 0, iclass 28, count 2 2006.201.12:21:12.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.12:21:12.97#ibcon#[27=AT02-05\r\n] 2006.201.12:21:12.97#ibcon#*before write, iclass 28, count 2 2006.201.12:21:12.97#ibcon#enter sib2, iclass 28, count 2 2006.201.12:21:12.97#ibcon#flushed, iclass 28, count 2 2006.201.12:21:12.97#ibcon#about to write, iclass 28, count 2 2006.201.12:21:12.97#ibcon#wrote, iclass 28, count 2 2006.201.12:21:12.97#ibcon#about to read 3, iclass 28, count 2 2006.201.12:21:13.00#ibcon#read 3, iclass 28, count 2 2006.201.12:21:13.00#ibcon#about to read 4, iclass 28, count 2 2006.201.12:21:13.00#ibcon#read 4, iclass 28, count 2 2006.201.12:21:13.00#ibcon#about to read 5, iclass 28, count 2 2006.201.12:21:13.00#ibcon#read 5, iclass 28, count 2 2006.201.12:21:13.00#ibcon#about to read 6, iclass 28, count 2 2006.201.12:21:13.00#ibcon#read 6, iclass 28, count 2 2006.201.12:21:13.00#ibcon#end of sib2, iclass 28, count 2 2006.201.12:21:13.00#ibcon#*after write, iclass 28, count 2 2006.201.12:21:13.00#ibcon#*before return 0, iclass 28, count 2 2006.201.12:21:13.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:21:13.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.12:21:13.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.12:21:13.00#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:13.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:21:13.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:21:13.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:21:13.12#ibcon#enter wrdev, iclass 28, count 0 2006.201.12:21:13.12#ibcon#first serial, iclass 28, count 0 2006.201.12:21:13.12#ibcon#enter sib2, iclass 28, count 0 2006.201.12:21:13.12#ibcon#flushed, iclass 28, count 0 2006.201.12:21:13.12#ibcon#about to write, iclass 28, count 0 2006.201.12:21:13.12#ibcon#wrote, iclass 28, count 0 2006.201.12:21:13.12#ibcon#about to read 3, iclass 28, count 0 2006.201.12:21:13.14#ibcon#read 3, iclass 28, count 0 2006.201.12:21:13.14#ibcon#about to read 4, iclass 28, count 0 2006.201.12:21:13.14#ibcon#read 4, iclass 28, count 0 2006.201.12:21:13.14#ibcon#about to read 5, iclass 28, count 0 2006.201.12:21:13.14#ibcon#read 5, iclass 28, count 0 2006.201.12:21:13.14#ibcon#about to read 6, iclass 28, count 0 2006.201.12:21:13.14#ibcon#read 6, iclass 28, count 0 2006.201.12:21:13.14#ibcon#end of sib2, iclass 28, count 0 2006.201.12:21:13.14#ibcon#*mode == 0, iclass 28, count 0 2006.201.12:21:13.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.12:21:13.14#ibcon#[27=USB\r\n] 2006.201.12:21:13.14#ibcon#*before write, iclass 28, count 0 2006.201.12:21:13.14#ibcon#enter sib2, iclass 28, count 0 2006.201.12:21:13.14#ibcon#flushed, iclass 28, count 0 2006.201.12:21:13.14#ibcon#about to write, iclass 28, count 0 2006.201.12:21:13.14#ibcon#wrote, iclass 28, count 0 2006.201.12:21:13.14#ibcon#about to read 3, iclass 28, count 0 2006.201.12:21:13.17#ibcon#read 3, iclass 28, count 0 2006.201.12:21:13.17#ibcon#about to read 4, iclass 28, count 0 2006.201.12:21:13.17#ibcon#read 4, iclass 28, count 0 2006.201.12:21:13.17#ibcon#about to read 5, iclass 28, count 0 2006.201.12:21:13.17#ibcon#read 5, iclass 28, count 0 2006.201.12:21:13.17#ibcon#about to read 6, iclass 28, count 0 2006.201.12:21:13.17#ibcon#read 6, iclass 28, count 0 2006.201.12:21:13.17#ibcon#end of sib2, iclass 28, count 0 2006.201.12:21:13.17#ibcon#*after write, iclass 28, count 0 2006.201.12:21:13.17#ibcon#*before return 0, iclass 28, count 0 2006.201.12:21:13.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:21:13.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.12:21:13.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.12:21:13.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.12:21:13.17$vck44/vblo=3,649.99 2006.201.12:21:13.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.12:21:13.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.12:21:13.17#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:13.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:13.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:13.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:13.17#ibcon#enter wrdev, iclass 30, count 0 2006.201.12:21:13.17#ibcon#first serial, iclass 30, count 0 2006.201.12:21:13.17#ibcon#enter sib2, iclass 30, count 0 2006.201.12:21:13.17#ibcon#flushed, iclass 30, count 0 2006.201.12:21:13.17#ibcon#about to write, iclass 30, count 0 2006.201.12:21:13.17#ibcon#wrote, iclass 30, count 0 2006.201.12:21:13.17#ibcon#about to read 3, iclass 30, count 0 2006.201.12:21:13.19#ibcon#read 3, iclass 30, count 0 2006.201.12:21:13.19#ibcon#about to read 4, iclass 30, count 0 2006.201.12:21:13.19#ibcon#read 4, iclass 30, count 0 2006.201.12:21:13.19#ibcon#about to read 5, iclass 30, count 0 2006.201.12:21:13.19#ibcon#read 5, iclass 30, count 0 2006.201.12:21:13.19#ibcon#about to read 6, iclass 30, count 0 2006.201.12:21:13.19#ibcon#read 6, iclass 30, count 0 2006.201.12:21:13.19#ibcon#end of sib2, iclass 30, count 0 2006.201.12:21:13.19#ibcon#*mode == 0, iclass 30, count 0 2006.201.12:21:13.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.12:21:13.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:21:13.19#ibcon#*before write, iclass 30, count 0 2006.201.12:21:13.19#ibcon#enter sib2, iclass 30, count 0 2006.201.12:21:13.19#ibcon#flushed, iclass 30, count 0 2006.201.12:21:13.19#ibcon#about to write, iclass 30, count 0 2006.201.12:21:13.19#ibcon#wrote, iclass 30, count 0 2006.201.12:21:13.19#ibcon#about to read 3, iclass 30, count 0 2006.201.12:21:13.24#ibcon#read 3, iclass 30, count 0 2006.201.12:21:13.24#ibcon#about to read 4, iclass 30, count 0 2006.201.12:21:13.24#ibcon#read 4, iclass 30, count 0 2006.201.12:21:13.24#ibcon#about to read 5, iclass 30, count 0 2006.201.12:21:13.24#ibcon#read 5, iclass 30, count 0 2006.201.12:21:13.24#ibcon#about to read 6, iclass 30, count 0 2006.201.12:21:13.24#ibcon#read 6, iclass 30, count 0 2006.201.12:21:13.24#ibcon#end of sib2, iclass 30, count 0 2006.201.12:21:13.24#ibcon#*after write, iclass 30, count 0 2006.201.12:21:13.24#ibcon#*before return 0, iclass 30, count 0 2006.201.12:21:13.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:13.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.12:21:13.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.12:21:13.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.12:21:13.24$vck44/vb=3,4 2006.201.12:21:13.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.12:21:13.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.12:21:13.24#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:13.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:13.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:13.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:13.29#ibcon#enter wrdev, iclass 32, count 2 2006.201.12:21:13.29#ibcon#first serial, iclass 32, count 2 2006.201.12:21:13.29#ibcon#enter sib2, iclass 32, count 2 2006.201.12:21:13.29#ibcon#flushed, iclass 32, count 2 2006.201.12:21:13.29#ibcon#about to write, iclass 32, count 2 2006.201.12:21:13.29#ibcon#wrote, iclass 32, count 2 2006.201.12:21:13.29#ibcon#about to read 3, iclass 32, count 2 2006.201.12:21:13.31#ibcon#read 3, iclass 32, count 2 2006.201.12:21:13.31#ibcon#about to read 4, iclass 32, count 2 2006.201.12:21:13.31#ibcon#read 4, iclass 32, count 2 2006.201.12:21:13.31#ibcon#about to read 5, iclass 32, count 2 2006.201.12:21:13.31#ibcon#read 5, iclass 32, count 2 2006.201.12:21:13.31#ibcon#about to read 6, iclass 32, count 2 2006.201.12:21:13.31#ibcon#read 6, iclass 32, count 2 2006.201.12:21:13.31#ibcon#end of sib2, iclass 32, count 2 2006.201.12:21:13.31#ibcon#*mode == 0, iclass 32, count 2 2006.201.12:21:13.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.12:21:13.31#ibcon#[27=AT03-04\r\n] 2006.201.12:21:13.31#ibcon#*before write, iclass 32, count 2 2006.201.12:21:13.31#ibcon#enter sib2, iclass 32, count 2 2006.201.12:21:13.31#ibcon#flushed, iclass 32, count 2 2006.201.12:21:13.31#ibcon#about to write, iclass 32, count 2 2006.201.12:21:13.31#ibcon#wrote, iclass 32, count 2 2006.201.12:21:13.31#ibcon#about to read 3, iclass 32, count 2 2006.201.12:21:13.34#ibcon#read 3, iclass 32, count 2 2006.201.12:21:13.34#ibcon#about to read 4, iclass 32, count 2 2006.201.12:21:13.34#ibcon#read 4, iclass 32, count 2 2006.201.12:21:13.34#ibcon#about to read 5, iclass 32, count 2 2006.201.12:21:13.34#ibcon#read 5, iclass 32, count 2 2006.201.12:21:13.34#ibcon#about to read 6, iclass 32, count 2 2006.201.12:21:13.34#ibcon#read 6, iclass 32, count 2 2006.201.12:21:13.34#ibcon#end of sib2, iclass 32, count 2 2006.201.12:21:13.34#ibcon#*after write, iclass 32, count 2 2006.201.12:21:13.34#ibcon#*before return 0, iclass 32, count 2 2006.201.12:21:13.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:13.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.12:21:13.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.12:21:13.34#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:13.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:13.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:13.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:13.46#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:21:13.46#ibcon#first serial, iclass 32, count 0 2006.201.12:21:13.46#ibcon#enter sib2, iclass 32, count 0 2006.201.12:21:13.46#ibcon#flushed, iclass 32, count 0 2006.201.12:21:13.46#ibcon#about to write, iclass 32, count 0 2006.201.12:21:13.46#ibcon#wrote, iclass 32, count 0 2006.201.12:21:13.46#ibcon#about to read 3, iclass 32, count 0 2006.201.12:21:13.48#ibcon#read 3, iclass 32, count 0 2006.201.12:21:13.48#ibcon#about to read 4, iclass 32, count 0 2006.201.12:21:13.48#ibcon#read 4, iclass 32, count 0 2006.201.12:21:13.48#ibcon#about to read 5, iclass 32, count 0 2006.201.12:21:13.48#ibcon#read 5, iclass 32, count 0 2006.201.12:21:13.48#ibcon#about to read 6, iclass 32, count 0 2006.201.12:21:13.48#ibcon#read 6, iclass 32, count 0 2006.201.12:21:13.48#ibcon#end of sib2, iclass 32, count 0 2006.201.12:21:13.48#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:21:13.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:21:13.48#ibcon#[27=USB\r\n] 2006.201.12:21:13.48#ibcon#*before write, iclass 32, count 0 2006.201.12:21:13.48#ibcon#enter sib2, iclass 32, count 0 2006.201.12:21:13.48#ibcon#flushed, iclass 32, count 0 2006.201.12:21:13.48#ibcon#about to write, iclass 32, count 0 2006.201.12:21:13.48#ibcon#wrote, iclass 32, count 0 2006.201.12:21:13.48#ibcon#about to read 3, iclass 32, count 0 2006.201.12:21:13.51#ibcon#read 3, iclass 32, count 0 2006.201.12:21:13.51#ibcon#about to read 4, iclass 32, count 0 2006.201.12:21:13.51#ibcon#read 4, iclass 32, count 0 2006.201.12:21:13.51#ibcon#about to read 5, iclass 32, count 0 2006.201.12:21:13.51#ibcon#read 5, iclass 32, count 0 2006.201.12:21:13.51#ibcon#about to read 6, iclass 32, count 0 2006.201.12:21:13.51#ibcon#read 6, iclass 32, count 0 2006.201.12:21:13.51#ibcon#end of sib2, iclass 32, count 0 2006.201.12:21:13.51#ibcon#*after write, iclass 32, count 0 2006.201.12:21:13.51#ibcon#*before return 0, iclass 32, count 0 2006.201.12:21:13.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:13.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.12:21:13.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:21:13.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:21:13.51$vck44/vblo=4,679.99 2006.201.12:21:13.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.12:21:13.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.12:21:13.51#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:13.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:13.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:13.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:13.51#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:21:13.51#ibcon#first serial, iclass 34, count 0 2006.201.12:21:13.51#ibcon#enter sib2, iclass 34, count 0 2006.201.12:21:13.51#ibcon#flushed, iclass 34, count 0 2006.201.12:21:13.51#ibcon#about to write, iclass 34, count 0 2006.201.12:21:13.51#ibcon#wrote, iclass 34, count 0 2006.201.12:21:13.51#ibcon#about to read 3, iclass 34, count 0 2006.201.12:21:13.53#ibcon#read 3, iclass 34, count 0 2006.201.12:21:13.53#ibcon#about to read 4, iclass 34, count 0 2006.201.12:21:13.53#ibcon#read 4, iclass 34, count 0 2006.201.12:21:13.53#ibcon#about to read 5, iclass 34, count 0 2006.201.12:21:13.53#ibcon#read 5, iclass 34, count 0 2006.201.12:21:13.53#ibcon#about to read 6, iclass 34, count 0 2006.201.12:21:13.53#ibcon#read 6, iclass 34, count 0 2006.201.12:21:13.53#ibcon#end of sib2, iclass 34, count 0 2006.201.12:21:13.53#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:21:13.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:21:13.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:21:13.53#ibcon#*before write, iclass 34, count 0 2006.201.12:21:13.53#ibcon#enter sib2, iclass 34, count 0 2006.201.12:21:13.53#ibcon#flushed, iclass 34, count 0 2006.201.12:21:13.53#ibcon#about to write, iclass 34, count 0 2006.201.12:21:13.53#ibcon#wrote, iclass 34, count 0 2006.201.12:21:13.53#ibcon#about to read 3, iclass 34, count 0 2006.201.12:21:13.58#ibcon#read 3, iclass 34, count 0 2006.201.12:21:13.58#ibcon#about to read 4, iclass 34, count 0 2006.201.12:21:13.58#ibcon#read 4, iclass 34, count 0 2006.201.12:21:13.58#ibcon#about to read 5, iclass 34, count 0 2006.201.12:21:13.58#ibcon#read 5, iclass 34, count 0 2006.201.12:21:13.58#ibcon#about to read 6, iclass 34, count 0 2006.201.12:21:13.58#ibcon#read 6, iclass 34, count 0 2006.201.12:21:13.58#ibcon#end of sib2, iclass 34, count 0 2006.201.12:21:13.58#ibcon#*after write, iclass 34, count 0 2006.201.12:21:13.58#ibcon#*before return 0, iclass 34, count 0 2006.201.12:21:13.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:13.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.12:21:13.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:21:13.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:21:13.58$vck44/vb=4,5 2006.201.12:21:13.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.12:21:13.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.12:21:13.58#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:13.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:13.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:13.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:13.63#ibcon#enter wrdev, iclass 36, count 2 2006.201.12:21:13.63#ibcon#first serial, iclass 36, count 2 2006.201.12:21:13.63#ibcon#enter sib2, iclass 36, count 2 2006.201.12:21:13.63#ibcon#flushed, iclass 36, count 2 2006.201.12:21:13.63#ibcon#about to write, iclass 36, count 2 2006.201.12:21:13.63#ibcon#wrote, iclass 36, count 2 2006.201.12:21:13.63#ibcon#about to read 3, iclass 36, count 2 2006.201.12:21:13.65#ibcon#read 3, iclass 36, count 2 2006.201.12:21:13.65#ibcon#about to read 4, iclass 36, count 2 2006.201.12:21:13.65#ibcon#read 4, iclass 36, count 2 2006.201.12:21:13.65#ibcon#about to read 5, iclass 36, count 2 2006.201.12:21:13.65#ibcon#read 5, iclass 36, count 2 2006.201.12:21:13.65#ibcon#about to read 6, iclass 36, count 2 2006.201.12:21:13.65#ibcon#read 6, iclass 36, count 2 2006.201.12:21:13.65#ibcon#end of sib2, iclass 36, count 2 2006.201.12:21:13.65#ibcon#*mode == 0, iclass 36, count 2 2006.201.12:21:13.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.12:21:13.65#ibcon#[27=AT04-05\r\n] 2006.201.12:21:13.65#ibcon#*before write, iclass 36, count 2 2006.201.12:21:13.65#ibcon#enter sib2, iclass 36, count 2 2006.201.12:21:13.65#ibcon#flushed, iclass 36, count 2 2006.201.12:21:13.65#ibcon#about to write, iclass 36, count 2 2006.201.12:21:13.65#ibcon#wrote, iclass 36, count 2 2006.201.12:21:13.65#ibcon#about to read 3, iclass 36, count 2 2006.201.12:21:13.68#ibcon#read 3, iclass 36, count 2 2006.201.12:21:13.68#ibcon#about to read 4, iclass 36, count 2 2006.201.12:21:13.68#ibcon#read 4, iclass 36, count 2 2006.201.12:21:13.68#ibcon#about to read 5, iclass 36, count 2 2006.201.12:21:13.68#ibcon#read 5, iclass 36, count 2 2006.201.12:21:13.68#ibcon#about to read 6, iclass 36, count 2 2006.201.12:21:13.68#ibcon#read 6, iclass 36, count 2 2006.201.12:21:13.68#ibcon#end of sib2, iclass 36, count 2 2006.201.12:21:13.68#ibcon#*after write, iclass 36, count 2 2006.201.12:21:13.68#ibcon#*before return 0, iclass 36, count 2 2006.201.12:21:13.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:13.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.12:21:13.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.12:21:13.68#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:13.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:13.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:13.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:13.80#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:21:13.80#ibcon#first serial, iclass 36, count 0 2006.201.12:21:13.80#ibcon#enter sib2, iclass 36, count 0 2006.201.12:21:13.80#ibcon#flushed, iclass 36, count 0 2006.201.12:21:13.80#ibcon#about to write, iclass 36, count 0 2006.201.12:21:13.80#ibcon#wrote, iclass 36, count 0 2006.201.12:21:13.80#ibcon#about to read 3, iclass 36, count 0 2006.201.12:21:13.82#ibcon#read 3, iclass 36, count 0 2006.201.12:21:13.82#ibcon#about to read 4, iclass 36, count 0 2006.201.12:21:13.82#ibcon#read 4, iclass 36, count 0 2006.201.12:21:13.82#ibcon#about to read 5, iclass 36, count 0 2006.201.12:21:13.82#ibcon#read 5, iclass 36, count 0 2006.201.12:21:13.82#ibcon#about to read 6, iclass 36, count 0 2006.201.12:21:13.82#ibcon#read 6, iclass 36, count 0 2006.201.12:21:13.82#ibcon#end of sib2, iclass 36, count 0 2006.201.12:21:13.82#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:21:13.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:21:13.82#ibcon#[27=USB\r\n] 2006.201.12:21:13.82#ibcon#*before write, iclass 36, count 0 2006.201.12:21:13.82#ibcon#enter sib2, iclass 36, count 0 2006.201.12:21:13.82#ibcon#flushed, iclass 36, count 0 2006.201.12:21:13.82#ibcon#about to write, iclass 36, count 0 2006.201.12:21:13.82#ibcon#wrote, iclass 36, count 0 2006.201.12:21:13.82#ibcon#about to read 3, iclass 36, count 0 2006.201.12:21:13.85#ibcon#read 3, iclass 36, count 0 2006.201.12:21:13.85#ibcon#about to read 4, iclass 36, count 0 2006.201.12:21:13.85#ibcon#read 4, iclass 36, count 0 2006.201.12:21:13.85#ibcon#about to read 5, iclass 36, count 0 2006.201.12:21:13.85#ibcon#read 5, iclass 36, count 0 2006.201.12:21:13.85#ibcon#about to read 6, iclass 36, count 0 2006.201.12:21:13.85#ibcon#read 6, iclass 36, count 0 2006.201.12:21:13.85#ibcon#end of sib2, iclass 36, count 0 2006.201.12:21:13.85#ibcon#*after write, iclass 36, count 0 2006.201.12:21:13.85#ibcon#*before return 0, iclass 36, count 0 2006.201.12:21:13.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:13.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.12:21:13.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:21:13.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:21:13.85$vck44/vblo=5,709.99 2006.201.12:21:13.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.12:21:13.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.12:21:13.85#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:13.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:13.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:13.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:13.85#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:21:13.85#ibcon#first serial, iclass 38, count 0 2006.201.12:21:13.85#ibcon#enter sib2, iclass 38, count 0 2006.201.12:21:13.85#ibcon#flushed, iclass 38, count 0 2006.201.12:21:13.85#ibcon#about to write, iclass 38, count 0 2006.201.12:21:13.85#ibcon#wrote, iclass 38, count 0 2006.201.12:21:13.85#ibcon#about to read 3, iclass 38, count 0 2006.201.12:21:13.87#ibcon#read 3, iclass 38, count 0 2006.201.12:21:13.87#ibcon#about to read 4, iclass 38, count 0 2006.201.12:21:13.87#ibcon#read 4, iclass 38, count 0 2006.201.12:21:13.87#ibcon#about to read 5, iclass 38, count 0 2006.201.12:21:13.87#ibcon#read 5, iclass 38, count 0 2006.201.12:21:13.87#ibcon#about to read 6, iclass 38, count 0 2006.201.12:21:13.87#ibcon#read 6, iclass 38, count 0 2006.201.12:21:13.87#ibcon#end of sib2, iclass 38, count 0 2006.201.12:21:13.87#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:21:13.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:21:13.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:21:13.87#ibcon#*before write, iclass 38, count 0 2006.201.12:21:13.87#ibcon#enter sib2, iclass 38, count 0 2006.201.12:21:13.87#ibcon#flushed, iclass 38, count 0 2006.201.12:21:13.87#ibcon#about to write, iclass 38, count 0 2006.201.12:21:13.87#ibcon#wrote, iclass 38, count 0 2006.201.12:21:13.87#ibcon#about to read 3, iclass 38, count 0 2006.201.12:21:13.92#ibcon#read 3, iclass 38, count 0 2006.201.12:21:13.92#ibcon#about to read 4, iclass 38, count 0 2006.201.12:21:13.92#ibcon#read 4, iclass 38, count 0 2006.201.12:21:13.92#ibcon#about to read 5, iclass 38, count 0 2006.201.12:21:13.92#ibcon#read 5, iclass 38, count 0 2006.201.12:21:13.92#ibcon#about to read 6, iclass 38, count 0 2006.201.12:21:13.92#ibcon#read 6, iclass 38, count 0 2006.201.12:21:13.92#ibcon#end of sib2, iclass 38, count 0 2006.201.12:21:13.92#ibcon#*after write, iclass 38, count 0 2006.201.12:21:13.92#ibcon#*before return 0, iclass 38, count 0 2006.201.12:21:13.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:13.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:21:13.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:21:13.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:21:13.92$vck44/vb=5,4 2006.201.12:21:13.92#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.12:21:13.92#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.12:21:13.92#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:13.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:13.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:13.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:13.97#ibcon#enter wrdev, iclass 40, count 2 2006.201.12:21:13.97#ibcon#first serial, iclass 40, count 2 2006.201.12:21:13.97#ibcon#enter sib2, iclass 40, count 2 2006.201.12:21:13.97#ibcon#flushed, iclass 40, count 2 2006.201.12:21:13.97#ibcon#about to write, iclass 40, count 2 2006.201.12:21:13.97#ibcon#wrote, iclass 40, count 2 2006.201.12:21:13.97#ibcon#about to read 3, iclass 40, count 2 2006.201.12:21:13.99#ibcon#read 3, iclass 40, count 2 2006.201.12:21:13.99#ibcon#about to read 4, iclass 40, count 2 2006.201.12:21:13.99#ibcon#read 4, iclass 40, count 2 2006.201.12:21:13.99#ibcon#about to read 5, iclass 40, count 2 2006.201.12:21:13.99#ibcon#read 5, iclass 40, count 2 2006.201.12:21:13.99#ibcon#about to read 6, iclass 40, count 2 2006.201.12:21:13.99#ibcon#read 6, iclass 40, count 2 2006.201.12:21:13.99#ibcon#end of sib2, iclass 40, count 2 2006.201.12:21:13.99#ibcon#*mode == 0, iclass 40, count 2 2006.201.12:21:13.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.12:21:13.99#ibcon#[27=AT05-04\r\n] 2006.201.12:21:13.99#ibcon#*before write, iclass 40, count 2 2006.201.12:21:13.99#ibcon#enter sib2, iclass 40, count 2 2006.201.12:21:13.99#ibcon#flushed, iclass 40, count 2 2006.201.12:21:13.99#ibcon#about to write, iclass 40, count 2 2006.201.12:21:13.99#ibcon#wrote, iclass 40, count 2 2006.201.12:21:13.99#ibcon#about to read 3, iclass 40, count 2 2006.201.12:21:14.02#ibcon#read 3, iclass 40, count 2 2006.201.12:21:14.02#ibcon#about to read 4, iclass 40, count 2 2006.201.12:21:14.02#ibcon#read 4, iclass 40, count 2 2006.201.12:21:14.02#ibcon#about to read 5, iclass 40, count 2 2006.201.12:21:14.02#ibcon#read 5, iclass 40, count 2 2006.201.12:21:14.02#ibcon#about to read 6, iclass 40, count 2 2006.201.12:21:14.02#ibcon#read 6, iclass 40, count 2 2006.201.12:21:14.02#ibcon#end of sib2, iclass 40, count 2 2006.201.12:21:14.02#ibcon#*after write, iclass 40, count 2 2006.201.12:21:14.02#ibcon#*before return 0, iclass 40, count 2 2006.201.12:21:14.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:14.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.12:21:14.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.12:21:14.02#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:14.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:14.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:14.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:14.14#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:21:14.14#ibcon#first serial, iclass 40, count 0 2006.201.12:21:14.14#ibcon#enter sib2, iclass 40, count 0 2006.201.12:21:14.14#ibcon#flushed, iclass 40, count 0 2006.201.12:21:14.14#ibcon#about to write, iclass 40, count 0 2006.201.12:21:14.14#ibcon#wrote, iclass 40, count 0 2006.201.12:21:14.14#ibcon#about to read 3, iclass 40, count 0 2006.201.12:21:14.16#ibcon#read 3, iclass 40, count 0 2006.201.12:21:14.16#ibcon#about to read 4, iclass 40, count 0 2006.201.12:21:14.16#ibcon#read 4, iclass 40, count 0 2006.201.12:21:14.16#ibcon#about to read 5, iclass 40, count 0 2006.201.12:21:14.16#ibcon#read 5, iclass 40, count 0 2006.201.12:21:14.16#ibcon#about to read 6, iclass 40, count 0 2006.201.12:21:14.16#ibcon#read 6, iclass 40, count 0 2006.201.12:21:14.16#ibcon#end of sib2, iclass 40, count 0 2006.201.12:21:14.16#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:21:14.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:21:14.16#ibcon#[27=USB\r\n] 2006.201.12:21:14.16#ibcon#*before write, iclass 40, count 0 2006.201.12:21:14.16#ibcon#enter sib2, iclass 40, count 0 2006.201.12:21:14.16#ibcon#flushed, iclass 40, count 0 2006.201.12:21:14.16#ibcon#about to write, iclass 40, count 0 2006.201.12:21:14.16#ibcon#wrote, iclass 40, count 0 2006.201.12:21:14.16#ibcon#about to read 3, iclass 40, count 0 2006.201.12:21:14.19#ibcon#read 3, iclass 40, count 0 2006.201.12:21:14.19#ibcon#about to read 4, iclass 40, count 0 2006.201.12:21:14.19#ibcon#read 4, iclass 40, count 0 2006.201.12:21:14.19#ibcon#about to read 5, iclass 40, count 0 2006.201.12:21:14.19#ibcon#read 5, iclass 40, count 0 2006.201.12:21:14.19#ibcon#about to read 6, iclass 40, count 0 2006.201.12:21:14.19#ibcon#read 6, iclass 40, count 0 2006.201.12:21:14.19#ibcon#end of sib2, iclass 40, count 0 2006.201.12:21:14.19#ibcon#*after write, iclass 40, count 0 2006.201.12:21:14.19#ibcon#*before return 0, iclass 40, count 0 2006.201.12:21:14.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:14.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.12:21:14.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:21:14.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:21:14.19$vck44/vblo=6,719.99 2006.201.12:21:14.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.12:21:14.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.12:21:14.19#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:14.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:14.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:14.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:14.19#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:21:14.19#ibcon#first serial, iclass 4, count 0 2006.201.12:21:14.19#ibcon#enter sib2, iclass 4, count 0 2006.201.12:21:14.19#ibcon#flushed, iclass 4, count 0 2006.201.12:21:14.19#ibcon#about to write, iclass 4, count 0 2006.201.12:21:14.19#ibcon#wrote, iclass 4, count 0 2006.201.12:21:14.19#ibcon#about to read 3, iclass 4, count 0 2006.201.12:21:14.21#ibcon#read 3, iclass 4, count 0 2006.201.12:21:14.21#ibcon#about to read 4, iclass 4, count 0 2006.201.12:21:14.21#ibcon#read 4, iclass 4, count 0 2006.201.12:21:14.21#ibcon#about to read 5, iclass 4, count 0 2006.201.12:21:14.21#ibcon#read 5, iclass 4, count 0 2006.201.12:21:14.21#ibcon#about to read 6, iclass 4, count 0 2006.201.12:21:14.21#ibcon#read 6, iclass 4, count 0 2006.201.12:21:14.21#ibcon#end of sib2, iclass 4, count 0 2006.201.12:21:14.21#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:21:14.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:21:14.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:21:14.21#ibcon#*before write, iclass 4, count 0 2006.201.12:21:14.21#ibcon#enter sib2, iclass 4, count 0 2006.201.12:21:14.21#ibcon#flushed, iclass 4, count 0 2006.201.12:21:14.21#ibcon#about to write, iclass 4, count 0 2006.201.12:21:14.21#ibcon#wrote, iclass 4, count 0 2006.201.12:21:14.21#ibcon#about to read 3, iclass 4, count 0 2006.201.12:21:14.26#ibcon#read 3, iclass 4, count 0 2006.201.12:21:14.26#ibcon#about to read 4, iclass 4, count 0 2006.201.12:21:14.26#ibcon#read 4, iclass 4, count 0 2006.201.12:21:14.26#ibcon#about to read 5, iclass 4, count 0 2006.201.12:21:14.26#ibcon#read 5, iclass 4, count 0 2006.201.12:21:14.26#ibcon#about to read 6, iclass 4, count 0 2006.201.12:21:14.26#ibcon#read 6, iclass 4, count 0 2006.201.12:21:14.26#ibcon#end of sib2, iclass 4, count 0 2006.201.12:21:14.26#ibcon#*after write, iclass 4, count 0 2006.201.12:21:14.26#ibcon#*before return 0, iclass 4, count 0 2006.201.12:21:14.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:14.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.12:21:14.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:21:14.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:21:14.26$vck44/vb=6,4 2006.201.12:21:14.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.12:21:14.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.12:21:14.26#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:14.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:14.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:14.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:14.31#ibcon#enter wrdev, iclass 6, count 2 2006.201.12:21:14.31#ibcon#first serial, iclass 6, count 2 2006.201.12:21:14.31#ibcon#enter sib2, iclass 6, count 2 2006.201.12:21:14.31#ibcon#flushed, iclass 6, count 2 2006.201.12:21:14.31#ibcon#about to write, iclass 6, count 2 2006.201.12:21:14.31#ibcon#wrote, iclass 6, count 2 2006.201.12:21:14.31#ibcon#about to read 3, iclass 6, count 2 2006.201.12:21:14.33#ibcon#read 3, iclass 6, count 2 2006.201.12:21:14.33#ibcon#about to read 4, iclass 6, count 2 2006.201.12:21:14.33#ibcon#read 4, iclass 6, count 2 2006.201.12:21:14.33#ibcon#about to read 5, iclass 6, count 2 2006.201.12:21:14.33#ibcon#read 5, iclass 6, count 2 2006.201.12:21:14.33#ibcon#about to read 6, iclass 6, count 2 2006.201.12:21:14.33#ibcon#read 6, iclass 6, count 2 2006.201.12:21:14.33#ibcon#end of sib2, iclass 6, count 2 2006.201.12:21:14.33#ibcon#*mode == 0, iclass 6, count 2 2006.201.12:21:14.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.12:21:14.33#ibcon#[27=AT06-04\r\n] 2006.201.12:21:14.33#ibcon#*before write, iclass 6, count 2 2006.201.12:21:14.33#ibcon#enter sib2, iclass 6, count 2 2006.201.12:21:14.33#ibcon#flushed, iclass 6, count 2 2006.201.12:21:14.33#ibcon#about to write, iclass 6, count 2 2006.201.12:21:14.33#ibcon#wrote, iclass 6, count 2 2006.201.12:21:14.33#ibcon#about to read 3, iclass 6, count 2 2006.201.12:21:14.36#ibcon#read 3, iclass 6, count 2 2006.201.12:21:14.36#ibcon#about to read 4, iclass 6, count 2 2006.201.12:21:14.36#ibcon#read 4, iclass 6, count 2 2006.201.12:21:14.36#ibcon#about to read 5, iclass 6, count 2 2006.201.12:21:14.36#ibcon#read 5, iclass 6, count 2 2006.201.12:21:14.36#ibcon#about to read 6, iclass 6, count 2 2006.201.12:21:14.36#ibcon#read 6, iclass 6, count 2 2006.201.12:21:14.36#ibcon#end of sib2, iclass 6, count 2 2006.201.12:21:14.36#ibcon#*after write, iclass 6, count 2 2006.201.12:21:14.36#ibcon#*before return 0, iclass 6, count 2 2006.201.12:21:14.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:14.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.12:21:14.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.12:21:14.36#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:14.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:14.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:14.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:14.48#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:21:14.48#ibcon#first serial, iclass 6, count 0 2006.201.12:21:14.48#ibcon#enter sib2, iclass 6, count 0 2006.201.12:21:14.48#ibcon#flushed, iclass 6, count 0 2006.201.12:21:14.48#ibcon#about to write, iclass 6, count 0 2006.201.12:21:14.48#ibcon#wrote, iclass 6, count 0 2006.201.12:21:14.48#ibcon#about to read 3, iclass 6, count 0 2006.201.12:21:14.50#ibcon#read 3, iclass 6, count 0 2006.201.12:21:14.50#ibcon#about to read 4, iclass 6, count 0 2006.201.12:21:14.50#ibcon#read 4, iclass 6, count 0 2006.201.12:21:14.50#ibcon#about to read 5, iclass 6, count 0 2006.201.12:21:14.50#ibcon#read 5, iclass 6, count 0 2006.201.12:21:14.50#ibcon#about to read 6, iclass 6, count 0 2006.201.12:21:14.50#ibcon#read 6, iclass 6, count 0 2006.201.12:21:14.50#ibcon#end of sib2, iclass 6, count 0 2006.201.12:21:14.50#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:21:14.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:21:14.50#ibcon#[27=USB\r\n] 2006.201.12:21:14.50#ibcon#*before write, iclass 6, count 0 2006.201.12:21:14.50#ibcon#enter sib2, iclass 6, count 0 2006.201.12:21:14.50#ibcon#flushed, iclass 6, count 0 2006.201.12:21:14.50#ibcon#about to write, iclass 6, count 0 2006.201.12:21:14.50#ibcon#wrote, iclass 6, count 0 2006.201.12:21:14.50#ibcon#about to read 3, iclass 6, count 0 2006.201.12:21:14.53#ibcon#read 3, iclass 6, count 0 2006.201.12:21:14.53#ibcon#about to read 4, iclass 6, count 0 2006.201.12:21:14.53#ibcon#read 4, iclass 6, count 0 2006.201.12:21:14.53#ibcon#about to read 5, iclass 6, count 0 2006.201.12:21:14.53#ibcon#read 5, iclass 6, count 0 2006.201.12:21:14.53#ibcon#about to read 6, iclass 6, count 0 2006.201.12:21:14.53#ibcon#read 6, iclass 6, count 0 2006.201.12:21:14.53#ibcon#end of sib2, iclass 6, count 0 2006.201.12:21:14.53#ibcon#*after write, iclass 6, count 0 2006.201.12:21:14.53#ibcon#*before return 0, iclass 6, count 0 2006.201.12:21:14.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:14.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.12:21:14.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:21:14.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:21:14.53$vck44/vblo=7,734.99 2006.201.12:21:14.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.12:21:14.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.12:21:14.53#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:14.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:14.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:14.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:14.53#ibcon#enter wrdev, iclass 10, count 0 2006.201.12:21:14.53#ibcon#first serial, iclass 10, count 0 2006.201.12:21:14.53#ibcon#enter sib2, iclass 10, count 0 2006.201.12:21:14.53#ibcon#flushed, iclass 10, count 0 2006.201.12:21:14.53#ibcon#about to write, iclass 10, count 0 2006.201.12:21:14.53#ibcon#wrote, iclass 10, count 0 2006.201.12:21:14.53#ibcon#about to read 3, iclass 10, count 0 2006.201.12:21:14.55#ibcon#read 3, iclass 10, count 0 2006.201.12:21:14.55#ibcon#about to read 4, iclass 10, count 0 2006.201.12:21:14.55#ibcon#read 4, iclass 10, count 0 2006.201.12:21:14.55#ibcon#about to read 5, iclass 10, count 0 2006.201.12:21:14.55#ibcon#read 5, iclass 10, count 0 2006.201.12:21:14.55#ibcon#about to read 6, iclass 10, count 0 2006.201.12:21:14.55#ibcon#read 6, iclass 10, count 0 2006.201.12:21:14.55#ibcon#end of sib2, iclass 10, count 0 2006.201.12:21:14.55#ibcon#*mode == 0, iclass 10, count 0 2006.201.12:21:14.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.12:21:14.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:21:14.55#ibcon#*before write, iclass 10, count 0 2006.201.12:21:14.55#ibcon#enter sib2, iclass 10, count 0 2006.201.12:21:14.55#ibcon#flushed, iclass 10, count 0 2006.201.12:21:14.55#ibcon#about to write, iclass 10, count 0 2006.201.12:21:14.55#ibcon#wrote, iclass 10, count 0 2006.201.12:21:14.55#ibcon#about to read 3, iclass 10, count 0 2006.201.12:21:14.60#ibcon#read 3, iclass 10, count 0 2006.201.12:21:14.60#ibcon#about to read 4, iclass 10, count 0 2006.201.12:21:14.60#ibcon#read 4, iclass 10, count 0 2006.201.12:21:14.60#ibcon#about to read 5, iclass 10, count 0 2006.201.12:21:14.60#ibcon#read 5, iclass 10, count 0 2006.201.12:21:14.60#ibcon#about to read 6, iclass 10, count 0 2006.201.12:21:14.60#ibcon#read 6, iclass 10, count 0 2006.201.12:21:14.60#ibcon#end of sib2, iclass 10, count 0 2006.201.12:21:14.60#ibcon#*after write, iclass 10, count 0 2006.201.12:21:14.60#ibcon#*before return 0, iclass 10, count 0 2006.201.12:21:14.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:14.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.12:21:14.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.12:21:14.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.12:21:14.60$vck44/vb=7,4 2006.201.12:21:14.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.12:21:14.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.12:21:14.60#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:14.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:14.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:14.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:14.65#ibcon#enter wrdev, iclass 12, count 2 2006.201.12:21:14.65#ibcon#first serial, iclass 12, count 2 2006.201.12:21:14.65#ibcon#enter sib2, iclass 12, count 2 2006.201.12:21:14.65#ibcon#flushed, iclass 12, count 2 2006.201.12:21:14.65#ibcon#about to write, iclass 12, count 2 2006.201.12:21:14.65#ibcon#wrote, iclass 12, count 2 2006.201.12:21:14.65#ibcon#about to read 3, iclass 12, count 2 2006.201.12:21:14.67#ibcon#read 3, iclass 12, count 2 2006.201.12:21:14.67#ibcon#about to read 4, iclass 12, count 2 2006.201.12:21:14.67#ibcon#read 4, iclass 12, count 2 2006.201.12:21:14.67#ibcon#about to read 5, iclass 12, count 2 2006.201.12:21:14.67#ibcon#read 5, iclass 12, count 2 2006.201.12:21:14.67#ibcon#about to read 6, iclass 12, count 2 2006.201.12:21:14.67#ibcon#read 6, iclass 12, count 2 2006.201.12:21:14.67#ibcon#end of sib2, iclass 12, count 2 2006.201.12:21:14.67#ibcon#*mode == 0, iclass 12, count 2 2006.201.12:21:14.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.12:21:14.67#ibcon#[27=AT07-04\r\n] 2006.201.12:21:14.67#ibcon#*before write, iclass 12, count 2 2006.201.12:21:14.67#ibcon#enter sib2, iclass 12, count 2 2006.201.12:21:14.67#ibcon#flushed, iclass 12, count 2 2006.201.12:21:14.67#ibcon#about to write, iclass 12, count 2 2006.201.12:21:14.67#ibcon#wrote, iclass 12, count 2 2006.201.12:21:14.67#ibcon#about to read 3, iclass 12, count 2 2006.201.12:21:14.70#ibcon#read 3, iclass 12, count 2 2006.201.12:21:14.70#ibcon#about to read 4, iclass 12, count 2 2006.201.12:21:14.70#ibcon#read 4, iclass 12, count 2 2006.201.12:21:14.70#ibcon#about to read 5, iclass 12, count 2 2006.201.12:21:14.70#ibcon#read 5, iclass 12, count 2 2006.201.12:21:14.70#ibcon#about to read 6, iclass 12, count 2 2006.201.12:21:14.70#ibcon#read 6, iclass 12, count 2 2006.201.12:21:14.70#ibcon#end of sib2, iclass 12, count 2 2006.201.12:21:14.70#ibcon#*after write, iclass 12, count 2 2006.201.12:21:14.70#ibcon#*before return 0, iclass 12, count 2 2006.201.12:21:14.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:14.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.12:21:14.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.12:21:14.70#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:14.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:14.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:14.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:14.82#ibcon#enter wrdev, iclass 12, count 0 2006.201.12:21:14.82#ibcon#first serial, iclass 12, count 0 2006.201.12:21:14.82#ibcon#enter sib2, iclass 12, count 0 2006.201.12:21:14.82#ibcon#flushed, iclass 12, count 0 2006.201.12:21:14.82#ibcon#about to write, iclass 12, count 0 2006.201.12:21:14.82#ibcon#wrote, iclass 12, count 0 2006.201.12:21:14.82#ibcon#about to read 3, iclass 12, count 0 2006.201.12:21:14.84#ibcon#read 3, iclass 12, count 0 2006.201.12:21:14.84#ibcon#about to read 4, iclass 12, count 0 2006.201.12:21:14.84#ibcon#read 4, iclass 12, count 0 2006.201.12:21:14.84#ibcon#about to read 5, iclass 12, count 0 2006.201.12:21:14.84#ibcon#read 5, iclass 12, count 0 2006.201.12:21:14.84#ibcon#about to read 6, iclass 12, count 0 2006.201.12:21:14.84#ibcon#read 6, iclass 12, count 0 2006.201.12:21:14.84#ibcon#end of sib2, iclass 12, count 0 2006.201.12:21:14.84#ibcon#*mode == 0, iclass 12, count 0 2006.201.12:21:14.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.12:21:14.84#ibcon#[27=USB\r\n] 2006.201.12:21:14.84#ibcon#*before write, iclass 12, count 0 2006.201.12:21:14.84#ibcon#enter sib2, iclass 12, count 0 2006.201.12:21:14.84#ibcon#flushed, iclass 12, count 0 2006.201.12:21:14.84#ibcon#about to write, iclass 12, count 0 2006.201.12:21:14.84#ibcon#wrote, iclass 12, count 0 2006.201.12:21:14.84#ibcon#about to read 3, iclass 12, count 0 2006.201.12:21:14.87#ibcon#read 3, iclass 12, count 0 2006.201.12:21:14.87#ibcon#about to read 4, iclass 12, count 0 2006.201.12:21:14.87#ibcon#read 4, iclass 12, count 0 2006.201.12:21:14.87#ibcon#about to read 5, iclass 12, count 0 2006.201.12:21:14.87#ibcon#read 5, iclass 12, count 0 2006.201.12:21:14.87#ibcon#about to read 6, iclass 12, count 0 2006.201.12:21:14.87#ibcon#read 6, iclass 12, count 0 2006.201.12:21:14.87#ibcon#end of sib2, iclass 12, count 0 2006.201.12:21:14.87#ibcon#*after write, iclass 12, count 0 2006.201.12:21:14.87#ibcon#*before return 0, iclass 12, count 0 2006.201.12:21:14.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:14.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.12:21:14.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.12:21:14.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.12:21:14.87$vck44/vblo=8,744.99 2006.201.12:21:14.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.12:21:14.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.12:21:14.87#ibcon#ireg 17 cls_cnt 0 2006.201.12:21:14.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:14.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:14.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:14.87#ibcon#enter wrdev, iclass 14, count 0 2006.201.12:21:14.87#ibcon#first serial, iclass 14, count 0 2006.201.12:21:14.87#ibcon#enter sib2, iclass 14, count 0 2006.201.12:21:14.87#ibcon#flushed, iclass 14, count 0 2006.201.12:21:14.87#ibcon#about to write, iclass 14, count 0 2006.201.12:21:14.87#ibcon#wrote, iclass 14, count 0 2006.201.12:21:14.87#ibcon#about to read 3, iclass 14, count 0 2006.201.12:21:14.89#ibcon#read 3, iclass 14, count 0 2006.201.12:21:14.89#ibcon#about to read 4, iclass 14, count 0 2006.201.12:21:14.89#ibcon#read 4, iclass 14, count 0 2006.201.12:21:14.89#ibcon#about to read 5, iclass 14, count 0 2006.201.12:21:14.89#ibcon#read 5, iclass 14, count 0 2006.201.12:21:14.89#ibcon#about to read 6, iclass 14, count 0 2006.201.12:21:14.89#ibcon#read 6, iclass 14, count 0 2006.201.12:21:14.89#ibcon#end of sib2, iclass 14, count 0 2006.201.12:21:14.89#ibcon#*mode == 0, iclass 14, count 0 2006.201.12:21:14.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.12:21:14.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:21:14.89#ibcon#*before write, iclass 14, count 0 2006.201.12:21:14.89#ibcon#enter sib2, iclass 14, count 0 2006.201.12:21:14.89#ibcon#flushed, iclass 14, count 0 2006.201.12:21:14.89#ibcon#about to write, iclass 14, count 0 2006.201.12:21:14.89#ibcon#wrote, iclass 14, count 0 2006.201.12:21:14.89#ibcon#about to read 3, iclass 14, count 0 2006.201.12:21:14.94#ibcon#read 3, iclass 14, count 0 2006.201.12:21:14.94#ibcon#about to read 4, iclass 14, count 0 2006.201.12:21:14.94#ibcon#read 4, iclass 14, count 0 2006.201.12:21:14.94#ibcon#about to read 5, iclass 14, count 0 2006.201.12:21:14.94#ibcon#read 5, iclass 14, count 0 2006.201.12:21:14.94#ibcon#about to read 6, iclass 14, count 0 2006.201.12:21:14.94#ibcon#read 6, iclass 14, count 0 2006.201.12:21:14.94#ibcon#end of sib2, iclass 14, count 0 2006.201.12:21:14.94#ibcon#*after write, iclass 14, count 0 2006.201.12:21:14.94#ibcon#*before return 0, iclass 14, count 0 2006.201.12:21:14.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:14.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:21:14.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.12:21:14.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.12:21:14.94$vck44/vb=8,4 2006.201.12:21:14.94#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.12:21:14.94#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.12:21:14.94#ibcon#ireg 11 cls_cnt 2 2006.201.12:21:14.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:14.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:14.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:14.99#ibcon#enter wrdev, iclass 16, count 2 2006.201.12:21:14.99#ibcon#first serial, iclass 16, count 2 2006.201.12:21:14.99#ibcon#enter sib2, iclass 16, count 2 2006.201.12:21:14.99#ibcon#flushed, iclass 16, count 2 2006.201.12:21:14.99#ibcon#about to write, iclass 16, count 2 2006.201.12:21:14.99#ibcon#wrote, iclass 16, count 2 2006.201.12:21:14.99#ibcon#about to read 3, iclass 16, count 2 2006.201.12:21:15.01#ibcon#read 3, iclass 16, count 2 2006.201.12:21:15.01#ibcon#about to read 4, iclass 16, count 2 2006.201.12:21:15.01#ibcon#read 4, iclass 16, count 2 2006.201.12:21:15.01#ibcon#about to read 5, iclass 16, count 2 2006.201.12:21:15.01#ibcon#read 5, iclass 16, count 2 2006.201.12:21:15.01#ibcon#about to read 6, iclass 16, count 2 2006.201.12:21:15.01#ibcon#read 6, iclass 16, count 2 2006.201.12:21:15.01#ibcon#end of sib2, iclass 16, count 2 2006.201.12:21:15.01#ibcon#*mode == 0, iclass 16, count 2 2006.201.12:21:15.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.12:21:15.01#ibcon#[27=AT08-04\r\n] 2006.201.12:21:15.01#ibcon#*before write, iclass 16, count 2 2006.201.12:21:15.01#ibcon#enter sib2, iclass 16, count 2 2006.201.12:21:15.01#ibcon#flushed, iclass 16, count 2 2006.201.12:21:15.01#ibcon#about to write, iclass 16, count 2 2006.201.12:21:15.01#ibcon#wrote, iclass 16, count 2 2006.201.12:21:15.01#ibcon#about to read 3, iclass 16, count 2 2006.201.12:21:15.04#ibcon#read 3, iclass 16, count 2 2006.201.12:21:15.04#ibcon#about to read 4, iclass 16, count 2 2006.201.12:21:15.04#ibcon#read 4, iclass 16, count 2 2006.201.12:21:15.04#ibcon#about to read 5, iclass 16, count 2 2006.201.12:21:15.04#ibcon#read 5, iclass 16, count 2 2006.201.12:21:15.04#ibcon#about to read 6, iclass 16, count 2 2006.201.12:21:15.04#ibcon#read 6, iclass 16, count 2 2006.201.12:21:15.04#ibcon#end of sib2, iclass 16, count 2 2006.201.12:21:15.04#ibcon#*after write, iclass 16, count 2 2006.201.12:21:15.04#ibcon#*before return 0, iclass 16, count 2 2006.201.12:21:15.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:15.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.12:21:15.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.12:21:15.04#ibcon#ireg 7 cls_cnt 0 2006.201.12:21:15.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:15.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:15.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:15.16#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:21:15.16#ibcon#first serial, iclass 16, count 0 2006.201.12:21:15.16#ibcon#enter sib2, iclass 16, count 0 2006.201.12:21:15.16#ibcon#flushed, iclass 16, count 0 2006.201.12:21:15.16#ibcon#about to write, iclass 16, count 0 2006.201.12:21:15.16#ibcon#wrote, iclass 16, count 0 2006.201.12:21:15.16#ibcon#about to read 3, iclass 16, count 0 2006.201.12:21:15.18#ibcon#read 3, iclass 16, count 0 2006.201.12:21:15.18#ibcon#about to read 4, iclass 16, count 0 2006.201.12:21:15.18#ibcon#read 4, iclass 16, count 0 2006.201.12:21:15.18#ibcon#about to read 5, iclass 16, count 0 2006.201.12:21:15.18#ibcon#read 5, iclass 16, count 0 2006.201.12:21:15.18#ibcon#about to read 6, iclass 16, count 0 2006.201.12:21:15.18#ibcon#read 6, iclass 16, count 0 2006.201.12:21:15.18#ibcon#end of sib2, iclass 16, count 0 2006.201.12:21:15.18#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:21:15.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:21:15.18#ibcon#[27=USB\r\n] 2006.201.12:21:15.18#ibcon#*before write, iclass 16, count 0 2006.201.12:21:15.18#ibcon#enter sib2, iclass 16, count 0 2006.201.12:21:15.18#ibcon#flushed, iclass 16, count 0 2006.201.12:21:15.18#ibcon#about to write, iclass 16, count 0 2006.201.12:21:15.18#ibcon#wrote, iclass 16, count 0 2006.201.12:21:15.18#ibcon#about to read 3, iclass 16, count 0 2006.201.12:21:15.21#ibcon#read 3, iclass 16, count 0 2006.201.12:21:15.21#ibcon#about to read 4, iclass 16, count 0 2006.201.12:21:15.21#ibcon#read 4, iclass 16, count 0 2006.201.12:21:15.21#ibcon#about to read 5, iclass 16, count 0 2006.201.12:21:15.21#ibcon#read 5, iclass 16, count 0 2006.201.12:21:15.21#ibcon#about to read 6, iclass 16, count 0 2006.201.12:21:15.21#ibcon#read 6, iclass 16, count 0 2006.201.12:21:15.21#ibcon#end of sib2, iclass 16, count 0 2006.201.12:21:15.21#ibcon#*after write, iclass 16, count 0 2006.201.12:21:15.21#ibcon#*before return 0, iclass 16, count 0 2006.201.12:21:15.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:15.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.12:21:15.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:21:15.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:21:15.21$vck44/vabw=wide 2006.201.12:21:15.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.12:21:15.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.12:21:15.21#ibcon#ireg 8 cls_cnt 0 2006.201.12:21:15.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:15.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:15.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:15.21#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:21:15.21#ibcon#first serial, iclass 18, count 0 2006.201.12:21:15.21#ibcon#enter sib2, iclass 18, count 0 2006.201.12:21:15.21#ibcon#flushed, iclass 18, count 0 2006.201.12:21:15.21#ibcon#about to write, iclass 18, count 0 2006.201.12:21:15.21#ibcon#wrote, iclass 18, count 0 2006.201.12:21:15.21#ibcon#about to read 3, iclass 18, count 0 2006.201.12:21:15.23#ibcon#read 3, iclass 18, count 0 2006.201.12:21:15.23#ibcon#about to read 4, iclass 18, count 0 2006.201.12:21:15.23#ibcon#read 4, iclass 18, count 0 2006.201.12:21:15.23#ibcon#about to read 5, iclass 18, count 0 2006.201.12:21:15.23#ibcon#read 5, iclass 18, count 0 2006.201.12:21:15.23#ibcon#about to read 6, iclass 18, count 0 2006.201.12:21:15.23#ibcon#read 6, iclass 18, count 0 2006.201.12:21:15.23#ibcon#end of sib2, iclass 18, count 0 2006.201.12:21:15.23#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:21:15.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:21:15.23#ibcon#[25=BW32\r\n] 2006.201.12:21:15.23#ibcon#*before write, iclass 18, count 0 2006.201.12:21:15.23#ibcon#enter sib2, iclass 18, count 0 2006.201.12:21:15.23#ibcon#flushed, iclass 18, count 0 2006.201.12:21:15.23#ibcon#about to write, iclass 18, count 0 2006.201.12:21:15.23#ibcon#wrote, iclass 18, count 0 2006.201.12:21:15.23#ibcon#about to read 3, iclass 18, count 0 2006.201.12:21:15.26#ibcon#read 3, iclass 18, count 0 2006.201.12:21:15.26#ibcon#about to read 4, iclass 18, count 0 2006.201.12:21:15.26#ibcon#read 4, iclass 18, count 0 2006.201.12:21:15.26#ibcon#about to read 5, iclass 18, count 0 2006.201.12:21:15.26#ibcon#read 5, iclass 18, count 0 2006.201.12:21:15.26#ibcon#about to read 6, iclass 18, count 0 2006.201.12:21:15.26#ibcon#read 6, iclass 18, count 0 2006.201.12:21:15.26#ibcon#end of sib2, iclass 18, count 0 2006.201.12:21:15.26#ibcon#*after write, iclass 18, count 0 2006.201.12:21:15.26#ibcon#*before return 0, iclass 18, count 0 2006.201.12:21:15.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:15.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.12:21:15.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:21:15.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:21:15.26$vck44/vbbw=wide 2006.201.12:21:15.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.12:21:15.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.12:21:15.26#ibcon#ireg 8 cls_cnt 0 2006.201.12:21:15.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:21:15.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:21:15.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:21:15.33#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:21:15.33#ibcon#first serial, iclass 20, count 0 2006.201.12:21:15.33#ibcon#enter sib2, iclass 20, count 0 2006.201.12:21:15.33#ibcon#flushed, iclass 20, count 0 2006.201.12:21:15.33#ibcon#about to write, iclass 20, count 0 2006.201.12:21:15.33#ibcon#wrote, iclass 20, count 0 2006.201.12:21:15.33#ibcon#about to read 3, iclass 20, count 0 2006.201.12:21:15.35#ibcon#read 3, iclass 20, count 0 2006.201.12:21:15.35#ibcon#about to read 4, iclass 20, count 0 2006.201.12:21:15.35#ibcon#read 4, iclass 20, count 0 2006.201.12:21:15.35#ibcon#about to read 5, iclass 20, count 0 2006.201.12:21:15.35#ibcon#read 5, iclass 20, count 0 2006.201.12:21:15.35#ibcon#about to read 6, iclass 20, count 0 2006.201.12:21:15.35#ibcon#read 6, iclass 20, count 0 2006.201.12:21:15.35#ibcon#end of sib2, iclass 20, count 0 2006.201.12:21:15.35#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:21:15.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:21:15.35#ibcon#[27=BW32\r\n] 2006.201.12:21:15.35#ibcon#*before write, iclass 20, count 0 2006.201.12:21:15.35#ibcon#enter sib2, iclass 20, count 0 2006.201.12:21:15.35#ibcon#flushed, iclass 20, count 0 2006.201.12:21:15.35#ibcon#about to write, iclass 20, count 0 2006.201.12:21:15.35#ibcon#wrote, iclass 20, count 0 2006.201.12:21:15.35#ibcon#about to read 3, iclass 20, count 0 2006.201.12:21:15.38#ibcon#read 3, iclass 20, count 0 2006.201.12:21:15.38#ibcon#about to read 4, iclass 20, count 0 2006.201.12:21:15.38#ibcon#read 4, iclass 20, count 0 2006.201.12:21:15.38#ibcon#about to read 5, iclass 20, count 0 2006.201.12:21:15.38#ibcon#read 5, iclass 20, count 0 2006.201.12:21:15.38#ibcon#about to read 6, iclass 20, count 0 2006.201.12:21:15.38#ibcon#read 6, iclass 20, count 0 2006.201.12:21:15.38#ibcon#end of sib2, iclass 20, count 0 2006.201.12:21:15.38#ibcon#*after write, iclass 20, count 0 2006.201.12:21:15.38#ibcon#*before return 0, iclass 20, count 0 2006.201.12:21:15.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:21:15.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:21:15.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:21:15.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:21:15.38$setupk4/ifdk4 2006.201.12:21:15.38$ifdk4/lo= 2006.201.12:21:15.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:21:15.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:21:15.38$ifdk4/patch= 2006.201.12:21:15.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:21:15.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:21:15.38$setupk4/!*+20s 2006.201.12:21:20.13#abcon#<5=/04 2.1 3.7 21.171001004.1\r\n> 2006.201.12:21:20.15#abcon#{5=INTERFACE CLEAR} 2006.201.12:21:20.22#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:21:29.88$setupk4/"tpicd 2006.201.12:21:29.88$setupk4/echo=off 2006.201.12:21:29.88$setupk4/xlog=off 2006.201.12:21:29.88:!2006.201.12:22:17 2006.201.12:21:33.14#trakl#Source acquired 2006.201.12:21:35.14#flagr#flagr/antenna,acquired 2006.201.12:22:17.00:preob 2006.201.12:22:18.14/onsource/TRACKING 2006.201.12:22:18.14:!2006.201.12:22:27 2006.201.12:22:27.00:"tape 2006.201.12:22:27.00:"st=record 2006.201.12:22:27.00:data_valid=on 2006.201.12:22:27.00:midob 2006.201.12:22:27.14/onsource/TRACKING 2006.201.12:22:27.14/wx/21.17,1004.1,100 2006.201.12:22:27.32/cable/+6.4734E-03 2006.201.12:22:28.41/va/01,08,usb,yes,31,34 2006.201.12:22:28.41/va/02,07,usb,yes,34,35 2006.201.12:22:28.41/va/03,08,usb,yes,30,32 2006.201.12:22:28.41/va/04,07,usb,yes,35,37 2006.201.12:22:28.41/va/05,04,usb,yes,31,31 2006.201.12:22:28.41/va/06,05,usb,yes,31,31 2006.201.12:22:28.41/va/07,05,usb,yes,30,31 2006.201.12:22:28.41/va/08,04,usb,yes,30,36 2006.201.12:22:28.64/valo/01,524.99,yes,locked 2006.201.12:22:28.64/valo/02,534.99,yes,locked 2006.201.12:22:28.64/valo/03,564.99,yes,locked 2006.201.12:22:28.64/valo/04,624.99,yes,locked 2006.201.12:22:28.64/valo/05,734.99,yes,locked 2006.201.12:22:28.64/valo/06,814.99,yes,locked 2006.201.12:22:28.64/valo/07,864.99,yes,locked 2006.201.12:22:28.64/valo/08,884.99,yes,locked 2006.201.12:22:29.73/vb/01,04,usb,yes,30,28 2006.201.12:22:29.73/vb/02,05,usb,yes,28,28 2006.201.12:22:29.73/vb/03,04,usb,yes,29,32 2006.201.12:22:29.73/vb/04,05,usb,yes,30,29 2006.201.12:22:29.73/vb/05,04,usb,yes,26,29 2006.201.12:22:29.73/vb/06,04,usb,yes,31,27 2006.201.12:22:29.73/vb/07,04,usb,yes,31,30 2006.201.12:22:29.73/vb/08,04,usb,yes,28,31 2006.201.12:22:29.97/vblo/01,629.99,yes,locked 2006.201.12:22:29.97/vblo/02,634.99,yes,locked 2006.201.12:22:29.97/vblo/03,649.99,yes,locked 2006.201.12:22:29.97/vblo/04,679.99,yes,locked 2006.201.12:22:29.97/vblo/05,709.99,yes,locked 2006.201.12:22:29.97/vblo/06,719.99,yes,locked 2006.201.12:22:29.97/vblo/07,734.99,yes,locked 2006.201.12:22:29.97/vblo/08,744.99,yes,locked 2006.201.12:22:30.12/vabw/8 2006.201.12:22:30.27/vbbw/8 2006.201.12:22:30.36/xfe/off,on,15.0 2006.201.12:22:30.75/ifatt/23,28,28,28 2006.201.12:22:31.06/fmout-gps/S +4.58E-07 2006.201.12:22:31.13:!2006.201.12:24:47 2006.201.12:24:47.00:data_valid=off 2006.201.12:24:47.00:"et 2006.201.12:24:47.00:!+3s 2006.201.12:24:50.02:"tape 2006.201.12:24:50.02:postob 2006.201.12:24:50.16/cable/+6.4739E-03 2006.201.12:24:50.16/wx/21.16,1004.1,100 2006.201.12:24:50.22/fmout-gps/S +4.60E-07 2006.201.12:24:50.22:scan_name=201-1226,jd0607,120 2006.201.12:24:50.23:source=3c274,123049.42,122328.0,2000.0,ccw 2006.201.12:24:51.14#flagr#flagr/antenna,new-source 2006.201.12:24:51.14:checkk5 2006.201.12:24:51.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:24:51.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:24:52.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:24:52.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:24:52.99/chk_obsdata//k5ts1/T2011222??a.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.12:24:53.35/chk_obsdata//k5ts2/T2011222??b.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.12:24:53.73/chk_obsdata//k5ts3/T2011222??c.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.12:24:54.10/chk_obsdata//k5ts4/T2011222??d.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.12:24:54.79/k5log//k5ts1_log_newline 2006.201.12:24:55.47/k5log//k5ts2_log_newline 2006.201.12:24:56.15/k5log//k5ts3_log_newline 2006.201.12:24:56.84/k5log//k5ts4_log_newline 2006.201.12:24:56.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:24:56.86:setupk4=1 2006.201.12:24:56.86$setupk4/echo=on 2006.201.12:24:56.86$setupk4/pcalon 2006.201.12:24:56.86$pcalon/"no phase cal control is implemented here 2006.201.12:24:56.86$setupk4/"tpicd=stop 2006.201.12:24:56.86$setupk4/"rec=synch_on 2006.201.12:24:56.86$setupk4/"rec_mode=128 2006.201.12:24:56.86$setupk4/!* 2006.201.12:24:56.86$setupk4/recpk4 2006.201.12:24:56.86$recpk4/recpatch= 2006.201.12:24:56.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:24:56.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:24:56.87$setupk4/vck44 2006.201.12:24:56.87$vck44/valo=1,524.99 2006.201.12:24:56.87#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.12:24:56.87#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.12:24:56.87#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:56.87#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:56.87#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:56.87#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:56.87#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:24:56.87#ibcon#first serial, iclass 2, count 0 2006.201.12:24:56.87#ibcon#enter sib2, iclass 2, count 0 2006.201.12:24:56.87#ibcon#flushed, iclass 2, count 0 2006.201.12:24:56.87#ibcon#about to write, iclass 2, count 0 2006.201.12:24:56.87#ibcon#wrote, iclass 2, count 0 2006.201.12:24:56.87#ibcon#about to read 3, iclass 2, count 0 2006.201.12:24:56.90#ibcon#read 3, iclass 2, count 0 2006.201.12:24:56.90#ibcon#about to read 4, iclass 2, count 0 2006.201.12:24:56.90#ibcon#read 4, iclass 2, count 0 2006.201.12:24:56.90#ibcon#about to read 5, iclass 2, count 0 2006.201.12:24:56.90#ibcon#read 5, iclass 2, count 0 2006.201.12:24:56.90#ibcon#about to read 6, iclass 2, count 0 2006.201.12:24:56.90#ibcon#read 6, iclass 2, count 0 2006.201.12:24:56.90#ibcon#end of sib2, iclass 2, count 0 2006.201.12:24:56.90#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:24:56.90#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:24:56.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:24:56.90#ibcon#*before write, iclass 2, count 0 2006.201.12:24:56.90#ibcon#enter sib2, iclass 2, count 0 2006.201.12:24:56.90#ibcon#flushed, iclass 2, count 0 2006.201.12:24:56.90#ibcon#about to write, iclass 2, count 0 2006.201.12:24:56.90#ibcon#wrote, iclass 2, count 0 2006.201.12:24:56.90#ibcon#about to read 3, iclass 2, count 0 2006.201.12:24:56.95#ibcon#read 3, iclass 2, count 0 2006.201.12:24:56.95#ibcon#about to read 4, iclass 2, count 0 2006.201.12:24:56.95#ibcon#read 4, iclass 2, count 0 2006.201.12:24:56.95#ibcon#about to read 5, iclass 2, count 0 2006.201.12:24:56.95#ibcon#read 5, iclass 2, count 0 2006.201.12:24:56.95#ibcon#about to read 6, iclass 2, count 0 2006.201.12:24:56.95#ibcon#read 6, iclass 2, count 0 2006.201.12:24:56.95#ibcon#end of sib2, iclass 2, count 0 2006.201.12:24:56.95#ibcon#*after write, iclass 2, count 0 2006.201.12:24:56.95#ibcon#*before return 0, iclass 2, count 0 2006.201.12:24:56.95#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:56.95#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:56.95#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:24:56.95#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:24:56.95$vck44/va=1,8 2006.201.12:24:56.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.12:24:56.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.12:24:56.95#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:56.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:24:56.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:24:56.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:24:56.95#ibcon#enter wrdev, iclass 5, count 2 2006.201.12:24:56.95#ibcon#first serial, iclass 5, count 2 2006.201.12:24:56.95#ibcon#enter sib2, iclass 5, count 2 2006.201.12:24:56.95#ibcon#flushed, iclass 5, count 2 2006.201.12:24:56.95#ibcon#about to write, iclass 5, count 2 2006.201.12:24:56.95#ibcon#wrote, iclass 5, count 2 2006.201.12:24:56.95#ibcon#about to read 3, iclass 5, count 2 2006.201.12:24:56.97#ibcon#read 3, iclass 5, count 2 2006.201.12:24:56.97#ibcon#about to read 4, iclass 5, count 2 2006.201.12:24:56.97#ibcon#read 4, iclass 5, count 2 2006.201.12:24:56.97#ibcon#about to read 5, iclass 5, count 2 2006.201.12:24:56.97#ibcon#read 5, iclass 5, count 2 2006.201.12:24:56.97#ibcon#about to read 6, iclass 5, count 2 2006.201.12:24:56.97#ibcon#read 6, iclass 5, count 2 2006.201.12:24:56.97#ibcon#end of sib2, iclass 5, count 2 2006.201.12:24:56.97#ibcon#*mode == 0, iclass 5, count 2 2006.201.12:24:56.97#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.12:24:56.97#ibcon#[25=AT01-08\r\n] 2006.201.12:24:56.97#ibcon#*before write, iclass 5, count 2 2006.201.12:24:56.97#ibcon#enter sib2, iclass 5, count 2 2006.201.12:24:56.97#ibcon#flushed, iclass 5, count 2 2006.201.12:24:56.97#ibcon#about to write, iclass 5, count 2 2006.201.12:24:56.97#ibcon#wrote, iclass 5, count 2 2006.201.12:24:56.97#ibcon#about to read 3, iclass 5, count 2 2006.201.12:24:57.00#ibcon#read 3, iclass 5, count 2 2006.201.12:24:57.00#ibcon#about to read 4, iclass 5, count 2 2006.201.12:24:57.00#ibcon#read 4, iclass 5, count 2 2006.201.12:24:57.00#ibcon#about to read 5, iclass 5, count 2 2006.201.12:24:57.00#ibcon#read 5, iclass 5, count 2 2006.201.12:24:57.00#ibcon#about to read 6, iclass 5, count 2 2006.201.12:24:57.00#ibcon#read 6, iclass 5, count 2 2006.201.12:24:57.00#ibcon#end of sib2, iclass 5, count 2 2006.201.12:24:57.00#ibcon#*after write, iclass 5, count 2 2006.201.12:24:57.00#ibcon#*before return 0, iclass 5, count 2 2006.201.12:24:57.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:24:57.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:24:57.00#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.12:24:57.00#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:57.00#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:24:57.12#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:24:57.12#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:24:57.12#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:24:57.12#ibcon#first serial, iclass 5, count 0 2006.201.12:24:57.12#ibcon#enter sib2, iclass 5, count 0 2006.201.12:24:57.12#ibcon#flushed, iclass 5, count 0 2006.201.12:24:57.12#ibcon#about to write, iclass 5, count 0 2006.201.12:24:57.12#ibcon#wrote, iclass 5, count 0 2006.201.12:24:57.12#ibcon#about to read 3, iclass 5, count 0 2006.201.12:24:57.14#ibcon#read 3, iclass 5, count 0 2006.201.12:24:57.14#ibcon#about to read 4, iclass 5, count 0 2006.201.12:24:57.14#ibcon#read 4, iclass 5, count 0 2006.201.12:24:57.14#ibcon#about to read 5, iclass 5, count 0 2006.201.12:24:57.14#ibcon#read 5, iclass 5, count 0 2006.201.12:24:57.14#ibcon#about to read 6, iclass 5, count 0 2006.201.12:24:57.14#ibcon#read 6, iclass 5, count 0 2006.201.12:24:57.14#ibcon#end of sib2, iclass 5, count 0 2006.201.12:24:57.14#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:24:57.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:24:57.14#ibcon#[25=USB\r\n] 2006.201.12:24:57.14#ibcon#*before write, iclass 5, count 0 2006.201.12:24:57.14#ibcon#enter sib2, iclass 5, count 0 2006.201.12:24:57.14#ibcon#flushed, iclass 5, count 0 2006.201.12:24:57.14#ibcon#about to write, iclass 5, count 0 2006.201.12:24:57.14#ibcon#wrote, iclass 5, count 0 2006.201.12:24:57.14#ibcon#about to read 3, iclass 5, count 0 2006.201.12:24:57.17#ibcon#read 3, iclass 5, count 0 2006.201.12:24:57.17#ibcon#about to read 4, iclass 5, count 0 2006.201.12:24:57.17#ibcon#read 4, iclass 5, count 0 2006.201.12:24:57.17#ibcon#about to read 5, iclass 5, count 0 2006.201.12:24:57.17#ibcon#read 5, iclass 5, count 0 2006.201.12:24:57.17#ibcon#about to read 6, iclass 5, count 0 2006.201.12:24:57.17#ibcon#read 6, iclass 5, count 0 2006.201.12:24:57.17#ibcon#end of sib2, iclass 5, count 0 2006.201.12:24:57.17#ibcon#*after write, iclass 5, count 0 2006.201.12:24:57.17#ibcon#*before return 0, iclass 5, count 0 2006.201.12:24:57.17#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:24:57.17#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:24:57.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:24:57.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:24:57.17$vck44/valo=2,534.99 2006.201.12:24:57.17#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.12:24:57.17#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.12:24:57.17#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:57.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:24:57.17#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:24:57.17#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:24:57.17#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:24:57.17#ibcon#first serial, iclass 7, count 0 2006.201.12:24:57.17#ibcon#enter sib2, iclass 7, count 0 2006.201.12:24:57.17#ibcon#flushed, iclass 7, count 0 2006.201.12:24:57.17#ibcon#about to write, iclass 7, count 0 2006.201.12:24:57.17#ibcon#wrote, iclass 7, count 0 2006.201.12:24:57.17#ibcon#about to read 3, iclass 7, count 0 2006.201.12:24:57.19#ibcon#read 3, iclass 7, count 0 2006.201.12:24:57.19#ibcon#about to read 4, iclass 7, count 0 2006.201.12:24:57.19#ibcon#read 4, iclass 7, count 0 2006.201.12:24:57.19#ibcon#about to read 5, iclass 7, count 0 2006.201.12:24:57.19#ibcon#read 5, iclass 7, count 0 2006.201.12:24:57.19#ibcon#about to read 6, iclass 7, count 0 2006.201.12:24:57.19#ibcon#read 6, iclass 7, count 0 2006.201.12:24:57.19#ibcon#end of sib2, iclass 7, count 0 2006.201.12:24:57.19#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:24:57.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:24:57.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:24:57.19#ibcon#*before write, iclass 7, count 0 2006.201.12:24:57.19#ibcon#enter sib2, iclass 7, count 0 2006.201.12:24:57.19#ibcon#flushed, iclass 7, count 0 2006.201.12:24:57.19#ibcon#about to write, iclass 7, count 0 2006.201.12:24:57.19#ibcon#wrote, iclass 7, count 0 2006.201.12:24:57.19#ibcon#about to read 3, iclass 7, count 0 2006.201.12:24:57.24#ibcon#read 3, iclass 7, count 0 2006.201.12:24:57.24#ibcon#about to read 4, iclass 7, count 0 2006.201.12:24:57.24#ibcon#read 4, iclass 7, count 0 2006.201.12:24:57.24#ibcon#about to read 5, iclass 7, count 0 2006.201.12:24:57.24#ibcon#read 5, iclass 7, count 0 2006.201.12:24:57.24#ibcon#about to read 6, iclass 7, count 0 2006.201.12:24:57.24#ibcon#read 6, iclass 7, count 0 2006.201.12:24:57.24#ibcon#end of sib2, iclass 7, count 0 2006.201.12:24:57.24#ibcon#*after write, iclass 7, count 0 2006.201.12:24:57.24#ibcon#*before return 0, iclass 7, count 0 2006.201.12:24:57.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:24:57.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:24:57.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:24:57.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:24:57.24$vck44/va=2,7 2006.201.12:24:57.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.12:24:57.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.12:24:57.24#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:57.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:24:57.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:24:57.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:24:57.29#ibcon#enter wrdev, iclass 11, count 2 2006.201.12:24:57.29#ibcon#first serial, iclass 11, count 2 2006.201.12:24:57.29#ibcon#enter sib2, iclass 11, count 2 2006.201.12:24:57.29#ibcon#flushed, iclass 11, count 2 2006.201.12:24:57.29#ibcon#about to write, iclass 11, count 2 2006.201.12:24:57.29#ibcon#wrote, iclass 11, count 2 2006.201.12:24:57.29#ibcon#about to read 3, iclass 11, count 2 2006.201.12:24:57.31#ibcon#read 3, iclass 11, count 2 2006.201.12:24:57.31#ibcon#about to read 4, iclass 11, count 2 2006.201.12:24:57.31#ibcon#read 4, iclass 11, count 2 2006.201.12:24:57.31#ibcon#about to read 5, iclass 11, count 2 2006.201.12:24:57.31#ibcon#read 5, iclass 11, count 2 2006.201.12:24:57.31#ibcon#about to read 6, iclass 11, count 2 2006.201.12:24:57.31#ibcon#read 6, iclass 11, count 2 2006.201.12:24:57.31#ibcon#end of sib2, iclass 11, count 2 2006.201.12:24:57.31#ibcon#*mode == 0, iclass 11, count 2 2006.201.12:24:57.31#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.12:24:57.31#ibcon#[25=AT02-07\r\n] 2006.201.12:24:57.31#ibcon#*before write, iclass 11, count 2 2006.201.12:24:57.31#ibcon#enter sib2, iclass 11, count 2 2006.201.12:24:57.31#ibcon#flushed, iclass 11, count 2 2006.201.12:24:57.31#ibcon#about to write, iclass 11, count 2 2006.201.12:24:57.31#ibcon#wrote, iclass 11, count 2 2006.201.12:24:57.31#ibcon#about to read 3, iclass 11, count 2 2006.201.12:24:57.34#ibcon#read 3, iclass 11, count 2 2006.201.12:24:57.34#ibcon#about to read 4, iclass 11, count 2 2006.201.12:24:57.34#ibcon#read 4, iclass 11, count 2 2006.201.12:24:57.34#ibcon#about to read 5, iclass 11, count 2 2006.201.12:24:57.34#ibcon#read 5, iclass 11, count 2 2006.201.12:24:57.34#ibcon#about to read 6, iclass 11, count 2 2006.201.12:24:57.34#ibcon#read 6, iclass 11, count 2 2006.201.12:24:57.34#ibcon#end of sib2, iclass 11, count 2 2006.201.12:24:57.34#ibcon#*after write, iclass 11, count 2 2006.201.12:24:57.34#ibcon#*before return 0, iclass 11, count 2 2006.201.12:24:57.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:24:57.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:24:57.34#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.12:24:57.34#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:57.34#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:24:57.46#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:24:57.46#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:24:57.46#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:24:57.46#ibcon#first serial, iclass 11, count 0 2006.201.12:24:57.46#ibcon#enter sib2, iclass 11, count 0 2006.201.12:24:57.46#ibcon#flushed, iclass 11, count 0 2006.201.12:24:57.46#ibcon#about to write, iclass 11, count 0 2006.201.12:24:57.46#ibcon#wrote, iclass 11, count 0 2006.201.12:24:57.46#ibcon#about to read 3, iclass 11, count 0 2006.201.12:24:57.48#ibcon#read 3, iclass 11, count 0 2006.201.12:24:57.48#ibcon#about to read 4, iclass 11, count 0 2006.201.12:24:57.48#ibcon#read 4, iclass 11, count 0 2006.201.12:24:57.48#ibcon#about to read 5, iclass 11, count 0 2006.201.12:24:57.48#ibcon#read 5, iclass 11, count 0 2006.201.12:24:57.48#ibcon#about to read 6, iclass 11, count 0 2006.201.12:24:57.48#ibcon#read 6, iclass 11, count 0 2006.201.12:24:57.48#ibcon#end of sib2, iclass 11, count 0 2006.201.12:24:57.48#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:24:57.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:24:57.48#ibcon#[25=USB\r\n] 2006.201.12:24:57.48#ibcon#*before write, iclass 11, count 0 2006.201.12:24:57.48#ibcon#enter sib2, iclass 11, count 0 2006.201.12:24:57.48#ibcon#flushed, iclass 11, count 0 2006.201.12:24:57.48#ibcon#about to write, iclass 11, count 0 2006.201.12:24:57.48#ibcon#wrote, iclass 11, count 0 2006.201.12:24:57.48#ibcon#about to read 3, iclass 11, count 0 2006.201.12:24:57.51#ibcon#read 3, iclass 11, count 0 2006.201.12:24:57.51#ibcon#about to read 4, iclass 11, count 0 2006.201.12:24:57.51#ibcon#read 4, iclass 11, count 0 2006.201.12:24:57.51#ibcon#about to read 5, iclass 11, count 0 2006.201.12:24:57.51#ibcon#read 5, iclass 11, count 0 2006.201.12:24:57.51#ibcon#about to read 6, iclass 11, count 0 2006.201.12:24:57.51#ibcon#read 6, iclass 11, count 0 2006.201.12:24:57.51#ibcon#end of sib2, iclass 11, count 0 2006.201.12:24:57.51#ibcon#*after write, iclass 11, count 0 2006.201.12:24:57.51#ibcon#*before return 0, iclass 11, count 0 2006.201.12:24:57.51#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:24:57.51#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:24:57.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:24:57.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:24:57.51$vck44/valo=3,564.99 2006.201.12:24:57.51#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.12:24:57.51#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.12:24:57.51#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:57.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:24:57.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:24:57.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:24:57.51#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:24:57.51#ibcon#first serial, iclass 13, count 0 2006.201.12:24:57.51#ibcon#enter sib2, iclass 13, count 0 2006.201.12:24:57.51#ibcon#flushed, iclass 13, count 0 2006.201.12:24:57.51#ibcon#about to write, iclass 13, count 0 2006.201.12:24:57.51#ibcon#wrote, iclass 13, count 0 2006.201.12:24:57.51#ibcon#about to read 3, iclass 13, count 0 2006.201.12:24:57.53#ibcon#read 3, iclass 13, count 0 2006.201.12:24:57.53#ibcon#about to read 4, iclass 13, count 0 2006.201.12:24:57.53#ibcon#read 4, iclass 13, count 0 2006.201.12:24:57.53#ibcon#about to read 5, iclass 13, count 0 2006.201.12:24:57.53#ibcon#read 5, iclass 13, count 0 2006.201.12:24:57.53#ibcon#about to read 6, iclass 13, count 0 2006.201.12:24:57.53#ibcon#read 6, iclass 13, count 0 2006.201.12:24:57.53#ibcon#end of sib2, iclass 13, count 0 2006.201.12:24:57.53#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:24:57.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:24:57.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:24:57.53#ibcon#*before write, iclass 13, count 0 2006.201.12:24:57.53#ibcon#enter sib2, iclass 13, count 0 2006.201.12:24:57.53#ibcon#flushed, iclass 13, count 0 2006.201.12:24:57.53#ibcon#about to write, iclass 13, count 0 2006.201.12:24:57.53#ibcon#wrote, iclass 13, count 0 2006.201.12:24:57.53#ibcon#about to read 3, iclass 13, count 0 2006.201.12:24:57.58#ibcon#read 3, iclass 13, count 0 2006.201.12:24:57.58#ibcon#about to read 4, iclass 13, count 0 2006.201.12:24:57.58#ibcon#read 4, iclass 13, count 0 2006.201.12:24:57.58#ibcon#about to read 5, iclass 13, count 0 2006.201.12:24:57.58#ibcon#read 5, iclass 13, count 0 2006.201.12:24:57.58#ibcon#about to read 6, iclass 13, count 0 2006.201.12:24:57.58#ibcon#read 6, iclass 13, count 0 2006.201.12:24:57.58#ibcon#end of sib2, iclass 13, count 0 2006.201.12:24:57.58#ibcon#*after write, iclass 13, count 0 2006.201.12:24:57.58#ibcon#*before return 0, iclass 13, count 0 2006.201.12:24:57.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:24:57.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:24:57.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:24:57.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:24:57.58$vck44/va=3,8 2006.201.12:24:57.58#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.12:24:57.58#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.12:24:57.58#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:57.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:24:57.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:24:57.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:24:57.63#ibcon#enter wrdev, iclass 15, count 2 2006.201.12:24:57.63#ibcon#first serial, iclass 15, count 2 2006.201.12:24:57.63#ibcon#enter sib2, iclass 15, count 2 2006.201.12:24:57.63#ibcon#flushed, iclass 15, count 2 2006.201.12:24:57.63#ibcon#about to write, iclass 15, count 2 2006.201.12:24:57.63#ibcon#wrote, iclass 15, count 2 2006.201.12:24:57.63#ibcon#about to read 3, iclass 15, count 2 2006.201.12:24:57.65#ibcon#read 3, iclass 15, count 2 2006.201.12:24:57.65#ibcon#about to read 4, iclass 15, count 2 2006.201.12:24:57.65#ibcon#read 4, iclass 15, count 2 2006.201.12:24:57.65#ibcon#about to read 5, iclass 15, count 2 2006.201.12:24:57.65#ibcon#read 5, iclass 15, count 2 2006.201.12:24:57.65#ibcon#about to read 6, iclass 15, count 2 2006.201.12:24:57.65#ibcon#read 6, iclass 15, count 2 2006.201.12:24:57.65#ibcon#end of sib2, iclass 15, count 2 2006.201.12:24:57.65#ibcon#*mode == 0, iclass 15, count 2 2006.201.12:24:57.65#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.12:24:57.65#ibcon#[25=AT03-08\r\n] 2006.201.12:24:57.65#ibcon#*before write, iclass 15, count 2 2006.201.12:24:57.65#ibcon#enter sib2, iclass 15, count 2 2006.201.12:24:57.65#ibcon#flushed, iclass 15, count 2 2006.201.12:24:57.65#ibcon#about to write, iclass 15, count 2 2006.201.12:24:57.65#ibcon#wrote, iclass 15, count 2 2006.201.12:24:57.65#ibcon#about to read 3, iclass 15, count 2 2006.201.12:24:57.68#ibcon#read 3, iclass 15, count 2 2006.201.12:24:57.68#ibcon#about to read 4, iclass 15, count 2 2006.201.12:24:57.68#ibcon#read 4, iclass 15, count 2 2006.201.12:24:57.68#ibcon#about to read 5, iclass 15, count 2 2006.201.12:24:57.68#ibcon#read 5, iclass 15, count 2 2006.201.12:24:57.68#ibcon#about to read 6, iclass 15, count 2 2006.201.12:24:57.68#ibcon#read 6, iclass 15, count 2 2006.201.12:24:57.68#ibcon#end of sib2, iclass 15, count 2 2006.201.12:24:57.68#ibcon#*after write, iclass 15, count 2 2006.201.12:24:57.68#ibcon#*before return 0, iclass 15, count 2 2006.201.12:24:57.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:24:57.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:24:57.68#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.12:24:57.68#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:57.68#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:24:57.80#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:24:57.80#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:24:57.80#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:24:57.80#ibcon#first serial, iclass 15, count 0 2006.201.12:24:57.80#ibcon#enter sib2, iclass 15, count 0 2006.201.12:24:57.80#ibcon#flushed, iclass 15, count 0 2006.201.12:24:57.80#ibcon#about to write, iclass 15, count 0 2006.201.12:24:57.80#ibcon#wrote, iclass 15, count 0 2006.201.12:24:57.80#ibcon#about to read 3, iclass 15, count 0 2006.201.12:24:57.82#ibcon#read 3, iclass 15, count 0 2006.201.12:24:57.82#ibcon#about to read 4, iclass 15, count 0 2006.201.12:24:57.82#ibcon#read 4, iclass 15, count 0 2006.201.12:24:57.82#ibcon#about to read 5, iclass 15, count 0 2006.201.12:24:57.82#ibcon#read 5, iclass 15, count 0 2006.201.12:24:57.82#ibcon#about to read 6, iclass 15, count 0 2006.201.12:24:57.82#ibcon#read 6, iclass 15, count 0 2006.201.12:24:57.82#ibcon#end of sib2, iclass 15, count 0 2006.201.12:24:57.82#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:24:57.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:24:57.82#ibcon#[25=USB\r\n] 2006.201.12:24:57.82#ibcon#*before write, iclass 15, count 0 2006.201.12:24:57.82#ibcon#enter sib2, iclass 15, count 0 2006.201.12:24:57.82#ibcon#flushed, iclass 15, count 0 2006.201.12:24:57.82#ibcon#about to write, iclass 15, count 0 2006.201.12:24:57.82#ibcon#wrote, iclass 15, count 0 2006.201.12:24:57.82#ibcon#about to read 3, iclass 15, count 0 2006.201.12:24:57.85#ibcon#read 3, iclass 15, count 0 2006.201.12:24:57.85#ibcon#about to read 4, iclass 15, count 0 2006.201.12:24:57.85#ibcon#read 4, iclass 15, count 0 2006.201.12:24:57.85#ibcon#about to read 5, iclass 15, count 0 2006.201.12:24:57.85#ibcon#read 5, iclass 15, count 0 2006.201.12:24:57.85#ibcon#about to read 6, iclass 15, count 0 2006.201.12:24:57.85#ibcon#read 6, iclass 15, count 0 2006.201.12:24:57.85#ibcon#end of sib2, iclass 15, count 0 2006.201.12:24:57.85#ibcon#*after write, iclass 15, count 0 2006.201.12:24:57.85#ibcon#*before return 0, iclass 15, count 0 2006.201.12:24:57.85#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:24:57.85#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:24:57.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:24:57.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:24:57.85$vck44/valo=4,624.99 2006.201.12:24:57.85#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.12:24:57.85#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.12:24:57.85#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:57.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:24:57.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:24:57.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:24:57.85#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:24:57.85#ibcon#first serial, iclass 17, count 0 2006.201.12:24:57.85#ibcon#enter sib2, iclass 17, count 0 2006.201.12:24:57.85#ibcon#flushed, iclass 17, count 0 2006.201.12:24:57.85#ibcon#about to write, iclass 17, count 0 2006.201.12:24:57.85#ibcon#wrote, iclass 17, count 0 2006.201.12:24:57.85#ibcon#about to read 3, iclass 17, count 0 2006.201.12:24:57.87#ibcon#read 3, iclass 17, count 0 2006.201.12:24:57.87#ibcon#about to read 4, iclass 17, count 0 2006.201.12:24:57.87#ibcon#read 4, iclass 17, count 0 2006.201.12:24:57.87#ibcon#about to read 5, iclass 17, count 0 2006.201.12:24:57.87#ibcon#read 5, iclass 17, count 0 2006.201.12:24:57.87#ibcon#about to read 6, iclass 17, count 0 2006.201.12:24:57.87#ibcon#read 6, iclass 17, count 0 2006.201.12:24:57.87#ibcon#end of sib2, iclass 17, count 0 2006.201.12:24:57.87#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:24:57.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:24:57.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:24:57.87#ibcon#*before write, iclass 17, count 0 2006.201.12:24:57.87#ibcon#enter sib2, iclass 17, count 0 2006.201.12:24:57.87#ibcon#flushed, iclass 17, count 0 2006.201.12:24:57.87#ibcon#about to write, iclass 17, count 0 2006.201.12:24:57.87#ibcon#wrote, iclass 17, count 0 2006.201.12:24:57.87#ibcon#about to read 3, iclass 17, count 0 2006.201.12:24:57.92#ibcon#read 3, iclass 17, count 0 2006.201.12:24:57.92#ibcon#about to read 4, iclass 17, count 0 2006.201.12:24:57.92#ibcon#read 4, iclass 17, count 0 2006.201.12:24:57.92#ibcon#about to read 5, iclass 17, count 0 2006.201.12:24:57.92#ibcon#read 5, iclass 17, count 0 2006.201.12:24:57.92#ibcon#about to read 6, iclass 17, count 0 2006.201.12:24:57.92#ibcon#read 6, iclass 17, count 0 2006.201.12:24:57.92#ibcon#end of sib2, iclass 17, count 0 2006.201.12:24:57.92#ibcon#*after write, iclass 17, count 0 2006.201.12:24:57.92#ibcon#*before return 0, iclass 17, count 0 2006.201.12:24:57.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:24:57.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:24:57.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:24:57.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:24:57.92$vck44/va=4,7 2006.201.12:24:57.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.12:24:57.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.12:24:57.92#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:57.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:24:57.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:24:57.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:24:57.97#ibcon#enter wrdev, iclass 19, count 2 2006.201.12:24:57.97#ibcon#first serial, iclass 19, count 2 2006.201.12:24:57.97#ibcon#enter sib2, iclass 19, count 2 2006.201.12:24:57.97#ibcon#flushed, iclass 19, count 2 2006.201.12:24:57.97#ibcon#about to write, iclass 19, count 2 2006.201.12:24:57.97#ibcon#wrote, iclass 19, count 2 2006.201.12:24:57.97#ibcon#about to read 3, iclass 19, count 2 2006.201.12:24:57.99#ibcon#read 3, iclass 19, count 2 2006.201.12:24:57.99#ibcon#about to read 4, iclass 19, count 2 2006.201.12:24:57.99#ibcon#read 4, iclass 19, count 2 2006.201.12:24:57.99#ibcon#about to read 5, iclass 19, count 2 2006.201.12:24:57.99#ibcon#read 5, iclass 19, count 2 2006.201.12:24:57.99#ibcon#about to read 6, iclass 19, count 2 2006.201.12:24:57.99#ibcon#read 6, iclass 19, count 2 2006.201.12:24:57.99#ibcon#end of sib2, iclass 19, count 2 2006.201.12:24:57.99#ibcon#*mode == 0, iclass 19, count 2 2006.201.12:24:57.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.12:24:57.99#ibcon#[25=AT04-07\r\n] 2006.201.12:24:57.99#ibcon#*before write, iclass 19, count 2 2006.201.12:24:57.99#ibcon#enter sib2, iclass 19, count 2 2006.201.12:24:57.99#ibcon#flushed, iclass 19, count 2 2006.201.12:24:57.99#ibcon#about to write, iclass 19, count 2 2006.201.12:24:57.99#ibcon#wrote, iclass 19, count 2 2006.201.12:24:57.99#ibcon#about to read 3, iclass 19, count 2 2006.201.12:24:58.02#ibcon#read 3, iclass 19, count 2 2006.201.12:24:58.02#ibcon#about to read 4, iclass 19, count 2 2006.201.12:24:58.02#ibcon#read 4, iclass 19, count 2 2006.201.12:24:58.02#ibcon#about to read 5, iclass 19, count 2 2006.201.12:24:58.02#ibcon#read 5, iclass 19, count 2 2006.201.12:24:58.02#ibcon#about to read 6, iclass 19, count 2 2006.201.12:24:58.02#ibcon#read 6, iclass 19, count 2 2006.201.12:24:58.02#ibcon#end of sib2, iclass 19, count 2 2006.201.12:24:58.02#ibcon#*after write, iclass 19, count 2 2006.201.12:24:58.02#ibcon#*before return 0, iclass 19, count 2 2006.201.12:24:58.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:24:58.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:24:58.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.12:24:58.02#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:58.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:24:58.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:24:58.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:24:58.14#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:24:58.14#ibcon#first serial, iclass 19, count 0 2006.201.12:24:58.14#ibcon#enter sib2, iclass 19, count 0 2006.201.12:24:58.14#ibcon#flushed, iclass 19, count 0 2006.201.12:24:58.14#ibcon#about to write, iclass 19, count 0 2006.201.12:24:58.14#ibcon#wrote, iclass 19, count 0 2006.201.12:24:58.14#ibcon#about to read 3, iclass 19, count 0 2006.201.12:24:58.16#ibcon#read 3, iclass 19, count 0 2006.201.12:24:58.16#ibcon#about to read 4, iclass 19, count 0 2006.201.12:24:58.16#ibcon#read 4, iclass 19, count 0 2006.201.12:24:58.16#ibcon#about to read 5, iclass 19, count 0 2006.201.12:24:58.16#ibcon#read 5, iclass 19, count 0 2006.201.12:24:58.16#ibcon#about to read 6, iclass 19, count 0 2006.201.12:24:58.16#ibcon#read 6, iclass 19, count 0 2006.201.12:24:58.16#ibcon#end of sib2, iclass 19, count 0 2006.201.12:24:58.16#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:24:58.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:24:58.16#ibcon#[25=USB\r\n] 2006.201.12:24:58.16#ibcon#*before write, iclass 19, count 0 2006.201.12:24:58.16#ibcon#enter sib2, iclass 19, count 0 2006.201.12:24:58.16#ibcon#flushed, iclass 19, count 0 2006.201.12:24:58.16#ibcon#about to write, iclass 19, count 0 2006.201.12:24:58.16#ibcon#wrote, iclass 19, count 0 2006.201.12:24:58.16#ibcon#about to read 3, iclass 19, count 0 2006.201.12:24:58.19#ibcon#read 3, iclass 19, count 0 2006.201.12:24:58.19#ibcon#about to read 4, iclass 19, count 0 2006.201.12:24:58.19#ibcon#read 4, iclass 19, count 0 2006.201.12:24:58.19#ibcon#about to read 5, iclass 19, count 0 2006.201.12:24:58.19#ibcon#read 5, iclass 19, count 0 2006.201.12:24:58.19#ibcon#about to read 6, iclass 19, count 0 2006.201.12:24:58.19#ibcon#read 6, iclass 19, count 0 2006.201.12:24:58.19#ibcon#end of sib2, iclass 19, count 0 2006.201.12:24:58.19#ibcon#*after write, iclass 19, count 0 2006.201.12:24:58.19#ibcon#*before return 0, iclass 19, count 0 2006.201.12:24:58.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:24:58.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:24:58.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:24:58.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:24:58.19$vck44/valo=5,734.99 2006.201.12:24:58.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.12:24:58.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.12:24:58.19#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:58.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:24:58.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:24:58.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:24:58.19#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:24:58.19#ibcon#first serial, iclass 21, count 0 2006.201.12:24:58.19#ibcon#enter sib2, iclass 21, count 0 2006.201.12:24:58.19#ibcon#flushed, iclass 21, count 0 2006.201.12:24:58.19#ibcon#about to write, iclass 21, count 0 2006.201.12:24:58.19#ibcon#wrote, iclass 21, count 0 2006.201.12:24:58.19#ibcon#about to read 3, iclass 21, count 0 2006.201.12:24:58.21#ibcon#read 3, iclass 21, count 0 2006.201.12:24:58.21#ibcon#about to read 4, iclass 21, count 0 2006.201.12:24:58.21#ibcon#read 4, iclass 21, count 0 2006.201.12:24:58.21#ibcon#about to read 5, iclass 21, count 0 2006.201.12:24:58.21#ibcon#read 5, iclass 21, count 0 2006.201.12:24:58.21#ibcon#about to read 6, iclass 21, count 0 2006.201.12:24:58.21#ibcon#read 6, iclass 21, count 0 2006.201.12:24:58.21#ibcon#end of sib2, iclass 21, count 0 2006.201.12:24:58.21#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:24:58.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:24:58.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:24:58.21#ibcon#*before write, iclass 21, count 0 2006.201.12:24:58.21#ibcon#enter sib2, iclass 21, count 0 2006.201.12:24:58.21#ibcon#flushed, iclass 21, count 0 2006.201.12:24:58.21#ibcon#about to write, iclass 21, count 0 2006.201.12:24:58.21#ibcon#wrote, iclass 21, count 0 2006.201.12:24:58.21#ibcon#about to read 3, iclass 21, count 0 2006.201.12:24:58.25#ibcon#read 3, iclass 21, count 0 2006.201.12:24:58.25#ibcon#about to read 4, iclass 21, count 0 2006.201.12:24:58.25#ibcon#read 4, iclass 21, count 0 2006.201.12:24:58.25#ibcon#about to read 5, iclass 21, count 0 2006.201.12:24:58.25#ibcon#read 5, iclass 21, count 0 2006.201.12:24:58.25#ibcon#about to read 6, iclass 21, count 0 2006.201.12:24:58.25#ibcon#read 6, iclass 21, count 0 2006.201.12:24:58.25#ibcon#end of sib2, iclass 21, count 0 2006.201.12:24:58.25#ibcon#*after write, iclass 21, count 0 2006.201.12:24:58.25#ibcon#*before return 0, iclass 21, count 0 2006.201.12:24:58.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:24:58.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:24:58.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:24:58.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:24:58.25$vck44/va=5,4 2006.201.12:24:58.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.12:24:58.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.12:24:58.25#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:58.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:24:58.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:24:58.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:24:58.31#ibcon#enter wrdev, iclass 23, count 2 2006.201.12:24:58.31#ibcon#first serial, iclass 23, count 2 2006.201.12:24:58.31#ibcon#enter sib2, iclass 23, count 2 2006.201.12:24:58.31#ibcon#flushed, iclass 23, count 2 2006.201.12:24:58.31#ibcon#about to write, iclass 23, count 2 2006.201.12:24:58.31#ibcon#wrote, iclass 23, count 2 2006.201.12:24:58.31#ibcon#about to read 3, iclass 23, count 2 2006.201.12:24:58.33#ibcon#read 3, iclass 23, count 2 2006.201.12:24:58.33#ibcon#about to read 4, iclass 23, count 2 2006.201.12:24:58.33#ibcon#read 4, iclass 23, count 2 2006.201.12:24:58.33#ibcon#about to read 5, iclass 23, count 2 2006.201.12:24:58.33#ibcon#read 5, iclass 23, count 2 2006.201.12:24:58.33#ibcon#about to read 6, iclass 23, count 2 2006.201.12:24:58.33#ibcon#read 6, iclass 23, count 2 2006.201.12:24:58.33#ibcon#end of sib2, iclass 23, count 2 2006.201.12:24:58.33#ibcon#*mode == 0, iclass 23, count 2 2006.201.12:24:58.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.12:24:58.33#ibcon#[25=AT05-04\r\n] 2006.201.12:24:58.33#ibcon#*before write, iclass 23, count 2 2006.201.12:24:58.33#ibcon#enter sib2, iclass 23, count 2 2006.201.12:24:58.33#ibcon#flushed, iclass 23, count 2 2006.201.12:24:58.33#ibcon#about to write, iclass 23, count 2 2006.201.12:24:58.33#ibcon#wrote, iclass 23, count 2 2006.201.12:24:58.33#ibcon#about to read 3, iclass 23, count 2 2006.201.12:24:58.36#ibcon#read 3, iclass 23, count 2 2006.201.12:24:58.36#ibcon#about to read 4, iclass 23, count 2 2006.201.12:24:58.36#ibcon#read 4, iclass 23, count 2 2006.201.12:24:58.36#ibcon#about to read 5, iclass 23, count 2 2006.201.12:24:58.36#ibcon#read 5, iclass 23, count 2 2006.201.12:24:58.36#ibcon#about to read 6, iclass 23, count 2 2006.201.12:24:58.36#ibcon#read 6, iclass 23, count 2 2006.201.12:24:58.36#ibcon#end of sib2, iclass 23, count 2 2006.201.12:24:58.36#ibcon#*after write, iclass 23, count 2 2006.201.12:24:58.36#ibcon#*before return 0, iclass 23, count 2 2006.201.12:24:58.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:24:58.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:24:58.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.12:24:58.36#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:58.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:24:58.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:24:58.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:24:58.48#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:24:58.48#ibcon#first serial, iclass 23, count 0 2006.201.12:24:58.48#ibcon#enter sib2, iclass 23, count 0 2006.201.12:24:58.48#ibcon#flushed, iclass 23, count 0 2006.201.12:24:58.48#ibcon#about to write, iclass 23, count 0 2006.201.12:24:58.48#ibcon#wrote, iclass 23, count 0 2006.201.12:24:58.48#ibcon#about to read 3, iclass 23, count 0 2006.201.12:24:58.50#ibcon#read 3, iclass 23, count 0 2006.201.12:24:58.50#ibcon#about to read 4, iclass 23, count 0 2006.201.12:24:58.50#ibcon#read 4, iclass 23, count 0 2006.201.12:24:58.50#ibcon#about to read 5, iclass 23, count 0 2006.201.12:24:58.50#ibcon#read 5, iclass 23, count 0 2006.201.12:24:58.50#ibcon#about to read 6, iclass 23, count 0 2006.201.12:24:58.50#ibcon#read 6, iclass 23, count 0 2006.201.12:24:58.50#ibcon#end of sib2, iclass 23, count 0 2006.201.12:24:58.50#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:24:58.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:24:58.50#ibcon#[25=USB\r\n] 2006.201.12:24:58.50#ibcon#*before write, iclass 23, count 0 2006.201.12:24:58.50#ibcon#enter sib2, iclass 23, count 0 2006.201.12:24:58.50#ibcon#flushed, iclass 23, count 0 2006.201.12:24:58.50#ibcon#about to write, iclass 23, count 0 2006.201.12:24:58.50#ibcon#wrote, iclass 23, count 0 2006.201.12:24:58.50#ibcon#about to read 3, iclass 23, count 0 2006.201.12:24:58.53#ibcon#read 3, iclass 23, count 0 2006.201.12:24:58.53#ibcon#about to read 4, iclass 23, count 0 2006.201.12:24:58.53#ibcon#read 4, iclass 23, count 0 2006.201.12:24:58.53#ibcon#about to read 5, iclass 23, count 0 2006.201.12:24:58.53#ibcon#read 5, iclass 23, count 0 2006.201.12:24:58.53#ibcon#about to read 6, iclass 23, count 0 2006.201.12:24:58.53#ibcon#read 6, iclass 23, count 0 2006.201.12:24:58.53#ibcon#end of sib2, iclass 23, count 0 2006.201.12:24:58.53#ibcon#*after write, iclass 23, count 0 2006.201.12:24:58.53#ibcon#*before return 0, iclass 23, count 0 2006.201.12:24:58.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:24:58.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:24:58.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:24:58.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:24:58.53$vck44/valo=6,814.99 2006.201.12:24:58.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.12:24:58.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.12:24:58.53#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:58.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:24:58.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:24:58.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:24:58.53#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:24:58.53#ibcon#first serial, iclass 25, count 0 2006.201.12:24:58.53#ibcon#enter sib2, iclass 25, count 0 2006.201.12:24:58.53#ibcon#flushed, iclass 25, count 0 2006.201.12:24:58.53#ibcon#about to write, iclass 25, count 0 2006.201.12:24:58.53#ibcon#wrote, iclass 25, count 0 2006.201.12:24:58.53#ibcon#about to read 3, iclass 25, count 0 2006.201.12:24:58.55#ibcon#read 3, iclass 25, count 0 2006.201.12:24:58.55#ibcon#about to read 4, iclass 25, count 0 2006.201.12:24:58.55#ibcon#read 4, iclass 25, count 0 2006.201.12:24:58.55#ibcon#about to read 5, iclass 25, count 0 2006.201.12:24:58.55#ibcon#read 5, iclass 25, count 0 2006.201.12:24:58.55#ibcon#about to read 6, iclass 25, count 0 2006.201.12:24:58.55#ibcon#read 6, iclass 25, count 0 2006.201.12:24:58.55#ibcon#end of sib2, iclass 25, count 0 2006.201.12:24:58.55#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:24:58.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:24:58.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:24:58.55#ibcon#*before write, iclass 25, count 0 2006.201.12:24:58.55#ibcon#enter sib2, iclass 25, count 0 2006.201.12:24:58.55#ibcon#flushed, iclass 25, count 0 2006.201.12:24:58.55#ibcon#about to write, iclass 25, count 0 2006.201.12:24:58.55#ibcon#wrote, iclass 25, count 0 2006.201.12:24:58.55#ibcon#about to read 3, iclass 25, count 0 2006.201.12:24:58.60#ibcon#read 3, iclass 25, count 0 2006.201.12:24:58.60#ibcon#about to read 4, iclass 25, count 0 2006.201.12:24:58.60#ibcon#read 4, iclass 25, count 0 2006.201.12:24:58.60#ibcon#about to read 5, iclass 25, count 0 2006.201.12:24:58.60#ibcon#read 5, iclass 25, count 0 2006.201.12:24:58.60#ibcon#about to read 6, iclass 25, count 0 2006.201.12:24:58.60#ibcon#read 6, iclass 25, count 0 2006.201.12:24:58.60#ibcon#end of sib2, iclass 25, count 0 2006.201.12:24:58.60#ibcon#*after write, iclass 25, count 0 2006.201.12:24:58.60#ibcon#*before return 0, iclass 25, count 0 2006.201.12:24:58.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:24:58.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:24:58.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:24:58.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:24:58.60$vck44/va=6,5 2006.201.12:24:58.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.12:24:58.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.12:24:58.60#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:58.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:24:58.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:24:58.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:24:58.65#ibcon#enter wrdev, iclass 27, count 2 2006.201.12:24:58.65#ibcon#first serial, iclass 27, count 2 2006.201.12:24:58.65#ibcon#enter sib2, iclass 27, count 2 2006.201.12:24:58.65#ibcon#flushed, iclass 27, count 2 2006.201.12:24:58.65#ibcon#about to write, iclass 27, count 2 2006.201.12:24:58.65#ibcon#wrote, iclass 27, count 2 2006.201.12:24:58.65#ibcon#about to read 3, iclass 27, count 2 2006.201.12:24:58.67#ibcon#read 3, iclass 27, count 2 2006.201.12:24:58.67#ibcon#about to read 4, iclass 27, count 2 2006.201.12:24:58.67#ibcon#read 4, iclass 27, count 2 2006.201.12:24:58.67#ibcon#about to read 5, iclass 27, count 2 2006.201.12:24:58.67#ibcon#read 5, iclass 27, count 2 2006.201.12:24:58.67#ibcon#about to read 6, iclass 27, count 2 2006.201.12:24:58.67#ibcon#read 6, iclass 27, count 2 2006.201.12:24:58.67#ibcon#end of sib2, iclass 27, count 2 2006.201.12:24:58.67#ibcon#*mode == 0, iclass 27, count 2 2006.201.12:24:58.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.12:24:58.67#ibcon#[25=AT06-05\r\n] 2006.201.12:24:58.67#ibcon#*before write, iclass 27, count 2 2006.201.12:24:58.67#ibcon#enter sib2, iclass 27, count 2 2006.201.12:24:58.67#ibcon#flushed, iclass 27, count 2 2006.201.12:24:58.67#ibcon#about to write, iclass 27, count 2 2006.201.12:24:58.67#ibcon#wrote, iclass 27, count 2 2006.201.12:24:58.67#ibcon#about to read 3, iclass 27, count 2 2006.201.12:24:58.70#ibcon#read 3, iclass 27, count 2 2006.201.12:24:58.70#ibcon#about to read 4, iclass 27, count 2 2006.201.12:24:58.70#ibcon#read 4, iclass 27, count 2 2006.201.12:24:58.70#ibcon#about to read 5, iclass 27, count 2 2006.201.12:24:58.70#ibcon#read 5, iclass 27, count 2 2006.201.12:24:58.70#ibcon#about to read 6, iclass 27, count 2 2006.201.12:24:58.70#ibcon#read 6, iclass 27, count 2 2006.201.12:24:58.70#ibcon#end of sib2, iclass 27, count 2 2006.201.12:24:58.70#ibcon#*after write, iclass 27, count 2 2006.201.12:24:58.70#ibcon#*before return 0, iclass 27, count 2 2006.201.12:24:58.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:24:58.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:24:58.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.12:24:58.70#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:58.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:24:58.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:24:58.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:24:58.82#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:24:58.82#ibcon#first serial, iclass 27, count 0 2006.201.12:24:58.82#ibcon#enter sib2, iclass 27, count 0 2006.201.12:24:58.82#ibcon#flushed, iclass 27, count 0 2006.201.12:24:58.82#ibcon#about to write, iclass 27, count 0 2006.201.12:24:58.82#ibcon#wrote, iclass 27, count 0 2006.201.12:24:58.82#ibcon#about to read 3, iclass 27, count 0 2006.201.12:24:58.84#ibcon#read 3, iclass 27, count 0 2006.201.12:24:58.84#ibcon#about to read 4, iclass 27, count 0 2006.201.12:24:58.84#ibcon#read 4, iclass 27, count 0 2006.201.12:24:58.84#ibcon#about to read 5, iclass 27, count 0 2006.201.12:24:58.84#ibcon#read 5, iclass 27, count 0 2006.201.12:24:58.84#ibcon#about to read 6, iclass 27, count 0 2006.201.12:24:58.84#ibcon#read 6, iclass 27, count 0 2006.201.12:24:58.84#ibcon#end of sib2, iclass 27, count 0 2006.201.12:24:58.84#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:24:58.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:24:58.84#ibcon#[25=USB\r\n] 2006.201.12:24:58.84#ibcon#*before write, iclass 27, count 0 2006.201.12:24:58.84#ibcon#enter sib2, iclass 27, count 0 2006.201.12:24:58.84#ibcon#flushed, iclass 27, count 0 2006.201.12:24:58.84#ibcon#about to write, iclass 27, count 0 2006.201.12:24:58.84#ibcon#wrote, iclass 27, count 0 2006.201.12:24:58.84#ibcon#about to read 3, iclass 27, count 0 2006.201.12:24:58.87#ibcon#read 3, iclass 27, count 0 2006.201.12:24:58.87#ibcon#about to read 4, iclass 27, count 0 2006.201.12:24:58.87#ibcon#read 4, iclass 27, count 0 2006.201.12:24:58.87#ibcon#about to read 5, iclass 27, count 0 2006.201.12:24:58.87#ibcon#read 5, iclass 27, count 0 2006.201.12:24:58.87#ibcon#about to read 6, iclass 27, count 0 2006.201.12:24:58.87#ibcon#read 6, iclass 27, count 0 2006.201.12:24:58.87#ibcon#end of sib2, iclass 27, count 0 2006.201.12:24:58.87#ibcon#*after write, iclass 27, count 0 2006.201.12:24:58.87#ibcon#*before return 0, iclass 27, count 0 2006.201.12:24:58.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:24:58.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:24:58.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:24:58.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:24:58.87$vck44/valo=7,864.99 2006.201.12:24:58.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.12:24:58.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.12:24:58.87#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:58.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:24:58.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:24:58.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:24:58.87#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:24:58.87#ibcon#first serial, iclass 29, count 0 2006.201.12:24:58.87#ibcon#enter sib2, iclass 29, count 0 2006.201.12:24:58.87#ibcon#flushed, iclass 29, count 0 2006.201.12:24:58.87#ibcon#about to write, iclass 29, count 0 2006.201.12:24:58.87#ibcon#wrote, iclass 29, count 0 2006.201.12:24:58.87#ibcon#about to read 3, iclass 29, count 0 2006.201.12:24:58.89#ibcon#read 3, iclass 29, count 0 2006.201.12:24:58.89#ibcon#about to read 4, iclass 29, count 0 2006.201.12:24:58.89#ibcon#read 4, iclass 29, count 0 2006.201.12:24:58.89#ibcon#about to read 5, iclass 29, count 0 2006.201.12:24:58.89#ibcon#read 5, iclass 29, count 0 2006.201.12:24:58.89#ibcon#about to read 6, iclass 29, count 0 2006.201.12:24:58.89#ibcon#read 6, iclass 29, count 0 2006.201.12:24:58.89#ibcon#end of sib2, iclass 29, count 0 2006.201.12:24:58.89#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:24:58.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:24:58.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:24:58.89#ibcon#*before write, iclass 29, count 0 2006.201.12:24:58.89#ibcon#enter sib2, iclass 29, count 0 2006.201.12:24:58.89#ibcon#flushed, iclass 29, count 0 2006.201.12:24:58.89#ibcon#about to write, iclass 29, count 0 2006.201.12:24:58.89#ibcon#wrote, iclass 29, count 0 2006.201.12:24:58.89#ibcon#about to read 3, iclass 29, count 0 2006.201.12:24:58.94#ibcon#read 3, iclass 29, count 0 2006.201.12:24:58.94#ibcon#about to read 4, iclass 29, count 0 2006.201.12:24:58.94#ibcon#read 4, iclass 29, count 0 2006.201.12:24:58.94#ibcon#about to read 5, iclass 29, count 0 2006.201.12:24:58.94#ibcon#read 5, iclass 29, count 0 2006.201.12:24:58.94#ibcon#about to read 6, iclass 29, count 0 2006.201.12:24:58.94#ibcon#read 6, iclass 29, count 0 2006.201.12:24:58.94#ibcon#end of sib2, iclass 29, count 0 2006.201.12:24:58.94#ibcon#*after write, iclass 29, count 0 2006.201.12:24:58.94#ibcon#*before return 0, iclass 29, count 0 2006.201.12:24:58.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:24:58.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:24:58.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:24:58.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:24:58.94$vck44/va=7,5 2006.201.12:24:58.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.12:24:58.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.12:24:58.94#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:58.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:24:58.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:24:58.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:24:58.99#ibcon#enter wrdev, iclass 31, count 2 2006.201.12:24:58.99#ibcon#first serial, iclass 31, count 2 2006.201.12:24:58.99#ibcon#enter sib2, iclass 31, count 2 2006.201.12:24:58.99#ibcon#flushed, iclass 31, count 2 2006.201.12:24:58.99#ibcon#about to write, iclass 31, count 2 2006.201.12:24:58.99#ibcon#wrote, iclass 31, count 2 2006.201.12:24:58.99#ibcon#about to read 3, iclass 31, count 2 2006.201.12:24:59.01#ibcon#read 3, iclass 31, count 2 2006.201.12:24:59.01#ibcon#about to read 4, iclass 31, count 2 2006.201.12:24:59.01#ibcon#read 4, iclass 31, count 2 2006.201.12:24:59.01#ibcon#about to read 5, iclass 31, count 2 2006.201.12:24:59.01#ibcon#read 5, iclass 31, count 2 2006.201.12:24:59.01#ibcon#about to read 6, iclass 31, count 2 2006.201.12:24:59.01#ibcon#read 6, iclass 31, count 2 2006.201.12:24:59.01#ibcon#end of sib2, iclass 31, count 2 2006.201.12:24:59.01#ibcon#*mode == 0, iclass 31, count 2 2006.201.12:24:59.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.12:24:59.01#ibcon#[25=AT07-05\r\n] 2006.201.12:24:59.01#ibcon#*before write, iclass 31, count 2 2006.201.12:24:59.01#ibcon#enter sib2, iclass 31, count 2 2006.201.12:24:59.01#ibcon#flushed, iclass 31, count 2 2006.201.12:24:59.01#ibcon#about to write, iclass 31, count 2 2006.201.12:24:59.01#ibcon#wrote, iclass 31, count 2 2006.201.12:24:59.01#ibcon#about to read 3, iclass 31, count 2 2006.201.12:24:59.04#ibcon#read 3, iclass 31, count 2 2006.201.12:24:59.04#ibcon#about to read 4, iclass 31, count 2 2006.201.12:24:59.04#ibcon#read 4, iclass 31, count 2 2006.201.12:24:59.04#ibcon#about to read 5, iclass 31, count 2 2006.201.12:24:59.04#ibcon#read 5, iclass 31, count 2 2006.201.12:24:59.04#ibcon#about to read 6, iclass 31, count 2 2006.201.12:24:59.04#ibcon#read 6, iclass 31, count 2 2006.201.12:24:59.04#ibcon#end of sib2, iclass 31, count 2 2006.201.12:24:59.04#ibcon#*after write, iclass 31, count 2 2006.201.12:24:59.04#ibcon#*before return 0, iclass 31, count 2 2006.201.12:24:59.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:24:59.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:24:59.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.12:24:59.04#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:59.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:24:59.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:24:59.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:24:59.16#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:24:59.16#ibcon#first serial, iclass 31, count 0 2006.201.12:24:59.16#ibcon#enter sib2, iclass 31, count 0 2006.201.12:24:59.16#ibcon#flushed, iclass 31, count 0 2006.201.12:24:59.16#ibcon#about to write, iclass 31, count 0 2006.201.12:24:59.16#ibcon#wrote, iclass 31, count 0 2006.201.12:24:59.16#ibcon#about to read 3, iclass 31, count 0 2006.201.12:24:59.18#ibcon#read 3, iclass 31, count 0 2006.201.12:24:59.18#ibcon#about to read 4, iclass 31, count 0 2006.201.12:24:59.18#ibcon#read 4, iclass 31, count 0 2006.201.12:24:59.18#ibcon#about to read 5, iclass 31, count 0 2006.201.12:24:59.18#ibcon#read 5, iclass 31, count 0 2006.201.12:24:59.18#ibcon#about to read 6, iclass 31, count 0 2006.201.12:24:59.18#ibcon#read 6, iclass 31, count 0 2006.201.12:24:59.18#ibcon#end of sib2, iclass 31, count 0 2006.201.12:24:59.18#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:24:59.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:24:59.18#ibcon#[25=USB\r\n] 2006.201.12:24:59.18#ibcon#*before write, iclass 31, count 0 2006.201.12:24:59.18#ibcon#enter sib2, iclass 31, count 0 2006.201.12:24:59.18#ibcon#flushed, iclass 31, count 0 2006.201.12:24:59.18#ibcon#about to write, iclass 31, count 0 2006.201.12:24:59.18#ibcon#wrote, iclass 31, count 0 2006.201.12:24:59.18#ibcon#about to read 3, iclass 31, count 0 2006.201.12:24:59.21#ibcon#read 3, iclass 31, count 0 2006.201.12:24:59.21#ibcon#about to read 4, iclass 31, count 0 2006.201.12:24:59.21#ibcon#read 4, iclass 31, count 0 2006.201.12:24:59.21#ibcon#about to read 5, iclass 31, count 0 2006.201.12:24:59.21#ibcon#read 5, iclass 31, count 0 2006.201.12:24:59.21#ibcon#about to read 6, iclass 31, count 0 2006.201.12:24:59.21#ibcon#read 6, iclass 31, count 0 2006.201.12:24:59.21#ibcon#end of sib2, iclass 31, count 0 2006.201.12:24:59.21#ibcon#*after write, iclass 31, count 0 2006.201.12:24:59.21#ibcon#*before return 0, iclass 31, count 0 2006.201.12:24:59.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:24:59.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:24:59.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:24:59.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:24:59.21$vck44/valo=8,884.99 2006.201.12:24:59.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.12:24:59.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.12:24:59.21#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:59.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:24:59.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:24:59.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:24:59.21#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:24:59.21#ibcon#first serial, iclass 33, count 0 2006.201.12:24:59.21#ibcon#enter sib2, iclass 33, count 0 2006.201.12:24:59.21#ibcon#flushed, iclass 33, count 0 2006.201.12:24:59.21#ibcon#about to write, iclass 33, count 0 2006.201.12:24:59.21#ibcon#wrote, iclass 33, count 0 2006.201.12:24:59.21#ibcon#about to read 3, iclass 33, count 0 2006.201.12:24:59.23#ibcon#read 3, iclass 33, count 0 2006.201.12:24:59.23#ibcon#about to read 4, iclass 33, count 0 2006.201.12:24:59.23#ibcon#read 4, iclass 33, count 0 2006.201.12:24:59.23#ibcon#about to read 5, iclass 33, count 0 2006.201.12:24:59.23#ibcon#read 5, iclass 33, count 0 2006.201.12:24:59.23#ibcon#about to read 6, iclass 33, count 0 2006.201.12:24:59.23#ibcon#read 6, iclass 33, count 0 2006.201.12:24:59.23#ibcon#end of sib2, iclass 33, count 0 2006.201.12:24:59.23#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:24:59.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:24:59.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:24:59.23#ibcon#*before write, iclass 33, count 0 2006.201.12:24:59.23#ibcon#enter sib2, iclass 33, count 0 2006.201.12:24:59.23#ibcon#flushed, iclass 33, count 0 2006.201.12:24:59.23#ibcon#about to write, iclass 33, count 0 2006.201.12:24:59.23#ibcon#wrote, iclass 33, count 0 2006.201.12:24:59.23#ibcon#about to read 3, iclass 33, count 0 2006.201.12:24:59.27#ibcon#read 3, iclass 33, count 0 2006.201.12:24:59.27#ibcon#about to read 4, iclass 33, count 0 2006.201.12:24:59.27#ibcon#read 4, iclass 33, count 0 2006.201.12:24:59.27#ibcon#about to read 5, iclass 33, count 0 2006.201.12:24:59.27#ibcon#read 5, iclass 33, count 0 2006.201.12:24:59.27#ibcon#about to read 6, iclass 33, count 0 2006.201.12:24:59.27#ibcon#read 6, iclass 33, count 0 2006.201.12:24:59.27#ibcon#end of sib2, iclass 33, count 0 2006.201.12:24:59.27#ibcon#*after write, iclass 33, count 0 2006.201.12:24:59.27#ibcon#*before return 0, iclass 33, count 0 2006.201.12:24:59.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:24:59.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:24:59.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:24:59.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:24:59.27$vck44/va=8,4 2006.201.12:24:59.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.12:24:59.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.12:24:59.27#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:59.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:24:59.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:24:59.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:24:59.33#ibcon#enter wrdev, iclass 35, count 2 2006.201.12:24:59.33#ibcon#first serial, iclass 35, count 2 2006.201.12:24:59.33#ibcon#enter sib2, iclass 35, count 2 2006.201.12:24:59.33#ibcon#flushed, iclass 35, count 2 2006.201.12:24:59.33#ibcon#about to write, iclass 35, count 2 2006.201.12:24:59.33#ibcon#wrote, iclass 35, count 2 2006.201.12:24:59.33#ibcon#about to read 3, iclass 35, count 2 2006.201.12:24:59.35#ibcon#read 3, iclass 35, count 2 2006.201.12:24:59.35#ibcon#about to read 4, iclass 35, count 2 2006.201.12:24:59.35#ibcon#read 4, iclass 35, count 2 2006.201.12:24:59.35#ibcon#about to read 5, iclass 35, count 2 2006.201.12:24:59.35#ibcon#read 5, iclass 35, count 2 2006.201.12:24:59.35#ibcon#about to read 6, iclass 35, count 2 2006.201.12:24:59.35#ibcon#read 6, iclass 35, count 2 2006.201.12:24:59.35#ibcon#end of sib2, iclass 35, count 2 2006.201.12:24:59.35#ibcon#*mode == 0, iclass 35, count 2 2006.201.12:24:59.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.12:24:59.35#ibcon#[25=AT08-04\r\n] 2006.201.12:24:59.35#ibcon#*before write, iclass 35, count 2 2006.201.12:24:59.35#ibcon#enter sib2, iclass 35, count 2 2006.201.12:24:59.35#ibcon#flushed, iclass 35, count 2 2006.201.12:24:59.35#ibcon#about to write, iclass 35, count 2 2006.201.12:24:59.35#ibcon#wrote, iclass 35, count 2 2006.201.12:24:59.35#ibcon#about to read 3, iclass 35, count 2 2006.201.12:24:59.38#ibcon#read 3, iclass 35, count 2 2006.201.12:24:59.38#ibcon#about to read 4, iclass 35, count 2 2006.201.12:24:59.38#ibcon#read 4, iclass 35, count 2 2006.201.12:24:59.38#ibcon#about to read 5, iclass 35, count 2 2006.201.12:24:59.38#ibcon#read 5, iclass 35, count 2 2006.201.12:24:59.38#ibcon#about to read 6, iclass 35, count 2 2006.201.12:24:59.38#ibcon#read 6, iclass 35, count 2 2006.201.12:24:59.38#ibcon#end of sib2, iclass 35, count 2 2006.201.12:24:59.38#ibcon#*after write, iclass 35, count 2 2006.201.12:24:59.38#ibcon#*before return 0, iclass 35, count 2 2006.201.12:24:59.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:24:59.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:24:59.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.12:24:59.38#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:59.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:24:59.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:24:59.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:24:59.50#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:24:59.50#ibcon#first serial, iclass 35, count 0 2006.201.12:24:59.50#ibcon#enter sib2, iclass 35, count 0 2006.201.12:24:59.50#ibcon#flushed, iclass 35, count 0 2006.201.12:24:59.50#ibcon#about to write, iclass 35, count 0 2006.201.12:24:59.50#ibcon#wrote, iclass 35, count 0 2006.201.12:24:59.50#ibcon#about to read 3, iclass 35, count 0 2006.201.12:24:59.52#ibcon#read 3, iclass 35, count 0 2006.201.12:24:59.52#ibcon#about to read 4, iclass 35, count 0 2006.201.12:24:59.52#ibcon#read 4, iclass 35, count 0 2006.201.12:24:59.52#ibcon#about to read 5, iclass 35, count 0 2006.201.12:24:59.52#ibcon#read 5, iclass 35, count 0 2006.201.12:24:59.52#ibcon#about to read 6, iclass 35, count 0 2006.201.12:24:59.52#ibcon#read 6, iclass 35, count 0 2006.201.12:24:59.52#ibcon#end of sib2, iclass 35, count 0 2006.201.12:24:59.52#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:24:59.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:24:59.52#ibcon#[25=USB\r\n] 2006.201.12:24:59.52#ibcon#*before write, iclass 35, count 0 2006.201.12:24:59.52#ibcon#enter sib2, iclass 35, count 0 2006.201.12:24:59.52#ibcon#flushed, iclass 35, count 0 2006.201.12:24:59.52#ibcon#about to write, iclass 35, count 0 2006.201.12:24:59.52#ibcon#wrote, iclass 35, count 0 2006.201.12:24:59.52#ibcon#about to read 3, iclass 35, count 0 2006.201.12:24:59.55#ibcon#read 3, iclass 35, count 0 2006.201.12:24:59.55#ibcon#about to read 4, iclass 35, count 0 2006.201.12:24:59.55#ibcon#read 4, iclass 35, count 0 2006.201.12:24:59.55#ibcon#about to read 5, iclass 35, count 0 2006.201.12:24:59.55#ibcon#read 5, iclass 35, count 0 2006.201.12:24:59.55#ibcon#about to read 6, iclass 35, count 0 2006.201.12:24:59.55#ibcon#read 6, iclass 35, count 0 2006.201.12:24:59.55#ibcon#end of sib2, iclass 35, count 0 2006.201.12:24:59.55#ibcon#*after write, iclass 35, count 0 2006.201.12:24:59.55#ibcon#*before return 0, iclass 35, count 0 2006.201.12:24:59.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:24:59.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:24:59.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:24:59.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:24:59.55$vck44/vblo=1,629.99 2006.201.12:24:59.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.12:24:59.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.12:24:59.55#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:59.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:24:59.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:24:59.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:24:59.55#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:24:59.55#ibcon#first serial, iclass 37, count 0 2006.201.12:24:59.55#ibcon#enter sib2, iclass 37, count 0 2006.201.12:24:59.55#ibcon#flushed, iclass 37, count 0 2006.201.12:24:59.55#ibcon#about to write, iclass 37, count 0 2006.201.12:24:59.55#ibcon#wrote, iclass 37, count 0 2006.201.12:24:59.55#ibcon#about to read 3, iclass 37, count 0 2006.201.12:24:59.57#ibcon#read 3, iclass 37, count 0 2006.201.12:24:59.57#ibcon#about to read 4, iclass 37, count 0 2006.201.12:24:59.57#ibcon#read 4, iclass 37, count 0 2006.201.12:24:59.57#ibcon#about to read 5, iclass 37, count 0 2006.201.12:24:59.57#ibcon#read 5, iclass 37, count 0 2006.201.12:24:59.57#ibcon#about to read 6, iclass 37, count 0 2006.201.12:24:59.57#ibcon#read 6, iclass 37, count 0 2006.201.12:24:59.57#ibcon#end of sib2, iclass 37, count 0 2006.201.12:24:59.57#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:24:59.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:24:59.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:24:59.57#ibcon#*before write, iclass 37, count 0 2006.201.12:24:59.57#ibcon#enter sib2, iclass 37, count 0 2006.201.12:24:59.57#ibcon#flushed, iclass 37, count 0 2006.201.12:24:59.57#ibcon#about to write, iclass 37, count 0 2006.201.12:24:59.57#ibcon#wrote, iclass 37, count 0 2006.201.12:24:59.57#ibcon#about to read 3, iclass 37, count 0 2006.201.12:24:59.62#ibcon#read 3, iclass 37, count 0 2006.201.12:24:59.62#ibcon#about to read 4, iclass 37, count 0 2006.201.12:24:59.62#ibcon#read 4, iclass 37, count 0 2006.201.12:24:59.62#ibcon#about to read 5, iclass 37, count 0 2006.201.12:24:59.62#ibcon#read 5, iclass 37, count 0 2006.201.12:24:59.62#ibcon#about to read 6, iclass 37, count 0 2006.201.12:24:59.62#ibcon#read 6, iclass 37, count 0 2006.201.12:24:59.62#ibcon#end of sib2, iclass 37, count 0 2006.201.12:24:59.62#ibcon#*after write, iclass 37, count 0 2006.201.12:24:59.62#ibcon#*before return 0, iclass 37, count 0 2006.201.12:24:59.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:24:59.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:24:59.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:24:59.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:24:59.62$vck44/vb=1,4 2006.201.12:24:59.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.12:24:59.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.12:24:59.62#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:59.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:24:59.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:24:59.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:24:59.62#ibcon#enter wrdev, iclass 39, count 2 2006.201.12:24:59.62#ibcon#first serial, iclass 39, count 2 2006.201.12:24:59.62#ibcon#enter sib2, iclass 39, count 2 2006.201.12:24:59.62#ibcon#flushed, iclass 39, count 2 2006.201.12:24:59.62#ibcon#about to write, iclass 39, count 2 2006.201.12:24:59.62#ibcon#wrote, iclass 39, count 2 2006.201.12:24:59.62#ibcon#about to read 3, iclass 39, count 2 2006.201.12:24:59.64#ibcon#read 3, iclass 39, count 2 2006.201.12:24:59.64#ibcon#about to read 4, iclass 39, count 2 2006.201.12:24:59.64#ibcon#read 4, iclass 39, count 2 2006.201.12:24:59.64#ibcon#about to read 5, iclass 39, count 2 2006.201.12:24:59.64#ibcon#read 5, iclass 39, count 2 2006.201.12:24:59.64#ibcon#about to read 6, iclass 39, count 2 2006.201.12:24:59.64#ibcon#read 6, iclass 39, count 2 2006.201.12:24:59.64#ibcon#end of sib2, iclass 39, count 2 2006.201.12:24:59.64#ibcon#*mode == 0, iclass 39, count 2 2006.201.12:24:59.64#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.12:24:59.64#ibcon#[27=AT01-04\r\n] 2006.201.12:24:59.64#ibcon#*before write, iclass 39, count 2 2006.201.12:24:59.64#ibcon#enter sib2, iclass 39, count 2 2006.201.12:24:59.64#ibcon#flushed, iclass 39, count 2 2006.201.12:24:59.64#ibcon#about to write, iclass 39, count 2 2006.201.12:24:59.64#ibcon#wrote, iclass 39, count 2 2006.201.12:24:59.64#ibcon#about to read 3, iclass 39, count 2 2006.201.12:24:59.67#ibcon#read 3, iclass 39, count 2 2006.201.12:24:59.67#ibcon#about to read 4, iclass 39, count 2 2006.201.12:24:59.67#ibcon#read 4, iclass 39, count 2 2006.201.12:24:59.67#ibcon#about to read 5, iclass 39, count 2 2006.201.12:24:59.67#ibcon#read 5, iclass 39, count 2 2006.201.12:24:59.67#ibcon#about to read 6, iclass 39, count 2 2006.201.12:24:59.67#ibcon#read 6, iclass 39, count 2 2006.201.12:24:59.67#ibcon#end of sib2, iclass 39, count 2 2006.201.12:24:59.67#ibcon#*after write, iclass 39, count 2 2006.201.12:24:59.67#ibcon#*before return 0, iclass 39, count 2 2006.201.12:24:59.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:24:59.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:24:59.67#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.12:24:59.67#ibcon#ireg 7 cls_cnt 0 2006.201.12:24:59.67#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:24:59.79#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:24:59.79#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:24:59.79#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:24:59.79#ibcon#first serial, iclass 39, count 0 2006.201.12:24:59.79#ibcon#enter sib2, iclass 39, count 0 2006.201.12:24:59.79#ibcon#flushed, iclass 39, count 0 2006.201.12:24:59.79#ibcon#about to write, iclass 39, count 0 2006.201.12:24:59.79#ibcon#wrote, iclass 39, count 0 2006.201.12:24:59.79#ibcon#about to read 3, iclass 39, count 0 2006.201.12:24:59.81#ibcon#read 3, iclass 39, count 0 2006.201.12:24:59.81#ibcon#about to read 4, iclass 39, count 0 2006.201.12:24:59.81#ibcon#read 4, iclass 39, count 0 2006.201.12:24:59.81#ibcon#about to read 5, iclass 39, count 0 2006.201.12:24:59.81#ibcon#read 5, iclass 39, count 0 2006.201.12:24:59.81#ibcon#about to read 6, iclass 39, count 0 2006.201.12:24:59.81#ibcon#read 6, iclass 39, count 0 2006.201.12:24:59.81#ibcon#end of sib2, iclass 39, count 0 2006.201.12:24:59.81#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:24:59.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:24:59.81#ibcon#[27=USB\r\n] 2006.201.12:24:59.81#ibcon#*before write, iclass 39, count 0 2006.201.12:24:59.81#ibcon#enter sib2, iclass 39, count 0 2006.201.12:24:59.81#ibcon#flushed, iclass 39, count 0 2006.201.12:24:59.81#ibcon#about to write, iclass 39, count 0 2006.201.12:24:59.81#ibcon#wrote, iclass 39, count 0 2006.201.12:24:59.81#ibcon#about to read 3, iclass 39, count 0 2006.201.12:24:59.84#ibcon#read 3, iclass 39, count 0 2006.201.12:24:59.84#ibcon#about to read 4, iclass 39, count 0 2006.201.12:24:59.84#ibcon#read 4, iclass 39, count 0 2006.201.12:24:59.84#ibcon#about to read 5, iclass 39, count 0 2006.201.12:24:59.84#ibcon#read 5, iclass 39, count 0 2006.201.12:24:59.84#ibcon#about to read 6, iclass 39, count 0 2006.201.12:24:59.84#ibcon#read 6, iclass 39, count 0 2006.201.12:24:59.84#ibcon#end of sib2, iclass 39, count 0 2006.201.12:24:59.84#ibcon#*after write, iclass 39, count 0 2006.201.12:24:59.84#ibcon#*before return 0, iclass 39, count 0 2006.201.12:24:59.84#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:24:59.84#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:24:59.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:24:59.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:24:59.84$vck44/vblo=2,634.99 2006.201.12:24:59.84#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.12:24:59.84#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.12:24:59.84#ibcon#ireg 17 cls_cnt 0 2006.201.12:24:59.84#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:59.84#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:59.84#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:59.84#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:24:59.84#ibcon#first serial, iclass 2, count 0 2006.201.12:24:59.84#ibcon#enter sib2, iclass 2, count 0 2006.201.12:24:59.84#ibcon#flushed, iclass 2, count 0 2006.201.12:24:59.84#ibcon#about to write, iclass 2, count 0 2006.201.12:24:59.84#ibcon#wrote, iclass 2, count 0 2006.201.12:24:59.84#ibcon#about to read 3, iclass 2, count 0 2006.201.12:24:59.86#ibcon#read 3, iclass 2, count 0 2006.201.12:24:59.86#ibcon#about to read 4, iclass 2, count 0 2006.201.12:24:59.86#ibcon#read 4, iclass 2, count 0 2006.201.12:24:59.86#ibcon#about to read 5, iclass 2, count 0 2006.201.12:24:59.86#ibcon#read 5, iclass 2, count 0 2006.201.12:24:59.86#ibcon#about to read 6, iclass 2, count 0 2006.201.12:24:59.86#ibcon#read 6, iclass 2, count 0 2006.201.12:24:59.86#ibcon#end of sib2, iclass 2, count 0 2006.201.12:24:59.86#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:24:59.86#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:24:59.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:24:59.86#ibcon#*before write, iclass 2, count 0 2006.201.12:24:59.86#ibcon#enter sib2, iclass 2, count 0 2006.201.12:24:59.86#ibcon#flushed, iclass 2, count 0 2006.201.12:24:59.86#ibcon#about to write, iclass 2, count 0 2006.201.12:24:59.86#ibcon#wrote, iclass 2, count 0 2006.201.12:24:59.86#ibcon#about to read 3, iclass 2, count 0 2006.201.12:24:59.90#ibcon#read 3, iclass 2, count 0 2006.201.12:24:59.90#ibcon#about to read 4, iclass 2, count 0 2006.201.12:24:59.90#ibcon#read 4, iclass 2, count 0 2006.201.12:24:59.90#ibcon#about to read 5, iclass 2, count 0 2006.201.12:24:59.90#ibcon#read 5, iclass 2, count 0 2006.201.12:24:59.90#ibcon#about to read 6, iclass 2, count 0 2006.201.12:24:59.90#ibcon#read 6, iclass 2, count 0 2006.201.12:24:59.90#ibcon#end of sib2, iclass 2, count 0 2006.201.12:24:59.90#ibcon#*after write, iclass 2, count 0 2006.201.12:24:59.90#ibcon#*before return 0, iclass 2, count 0 2006.201.12:24:59.90#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:59.90#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:24:59.90#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:24:59.90#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:24:59.90$vck44/vb=2,5 2006.201.12:24:59.90#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.12:24:59.90#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.12:24:59.90#ibcon#ireg 11 cls_cnt 2 2006.201.12:24:59.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:24:59.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:24:59.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:24:59.96#ibcon#enter wrdev, iclass 5, count 2 2006.201.12:24:59.96#ibcon#first serial, iclass 5, count 2 2006.201.12:24:59.96#ibcon#enter sib2, iclass 5, count 2 2006.201.12:24:59.96#ibcon#flushed, iclass 5, count 2 2006.201.12:24:59.96#ibcon#about to write, iclass 5, count 2 2006.201.12:24:59.96#ibcon#wrote, iclass 5, count 2 2006.201.12:24:59.96#ibcon#about to read 3, iclass 5, count 2 2006.201.12:24:59.98#ibcon#read 3, iclass 5, count 2 2006.201.12:24:59.98#ibcon#about to read 4, iclass 5, count 2 2006.201.12:24:59.98#ibcon#read 4, iclass 5, count 2 2006.201.12:24:59.98#ibcon#about to read 5, iclass 5, count 2 2006.201.12:24:59.98#ibcon#read 5, iclass 5, count 2 2006.201.12:24:59.98#ibcon#about to read 6, iclass 5, count 2 2006.201.12:24:59.98#ibcon#read 6, iclass 5, count 2 2006.201.12:24:59.98#ibcon#end of sib2, iclass 5, count 2 2006.201.12:24:59.98#ibcon#*mode == 0, iclass 5, count 2 2006.201.12:24:59.98#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.12:24:59.98#ibcon#[27=AT02-05\r\n] 2006.201.12:24:59.98#ibcon#*before write, iclass 5, count 2 2006.201.12:24:59.98#ibcon#enter sib2, iclass 5, count 2 2006.201.12:24:59.98#ibcon#flushed, iclass 5, count 2 2006.201.12:24:59.98#ibcon#about to write, iclass 5, count 2 2006.201.12:24:59.98#ibcon#wrote, iclass 5, count 2 2006.201.12:24:59.98#ibcon#about to read 3, iclass 5, count 2 2006.201.12:25:00.01#ibcon#read 3, iclass 5, count 2 2006.201.12:25:00.01#ibcon#about to read 4, iclass 5, count 2 2006.201.12:25:00.01#ibcon#read 4, iclass 5, count 2 2006.201.12:25:00.01#ibcon#about to read 5, iclass 5, count 2 2006.201.12:25:00.01#ibcon#read 5, iclass 5, count 2 2006.201.12:25:00.01#ibcon#about to read 6, iclass 5, count 2 2006.201.12:25:00.01#ibcon#read 6, iclass 5, count 2 2006.201.12:25:00.01#ibcon#end of sib2, iclass 5, count 2 2006.201.12:25:00.01#ibcon#*after write, iclass 5, count 2 2006.201.12:25:00.01#ibcon#*before return 0, iclass 5, count 2 2006.201.12:25:00.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:25:00.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:25:00.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.12:25:00.01#ibcon#ireg 7 cls_cnt 0 2006.201.12:25:00.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:25:00.13#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:25:00.13#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:25:00.13#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:25:00.13#ibcon#first serial, iclass 5, count 0 2006.201.12:25:00.13#ibcon#enter sib2, iclass 5, count 0 2006.201.12:25:00.13#ibcon#flushed, iclass 5, count 0 2006.201.12:25:00.13#ibcon#about to write, iclass 5, count 0 2006.201.12:25:00.13#ibcon#wrote, iclass 5, count 0 2006.201.12:25:00.13#ibcon#about to read 3, iclass 5, count 0 2006.201.12:25:00.15#ibcon#read 3, iclass 5, count 0 2006.201.12:25:00.15#ibcon#about to read 4, iclass 5, count 0 2006.201.12:25:00.15#ibcon#read 4, iclass 5, count 0 2006.201.12:25:00.15#ibcon#about to read 5, iclass 5, count 0 2006.201.12:25:00.15#ibcon#read 5, iclass 5, count 0 2006.201.12:25:00.15#ibcon#about to read 6, iclass 5, count 0 2006.201.12:25:00.15#ibcon#read 6, iclass 5, count 0 2006.201.12:25:00.15#ibcon#end of sib2, iclass 5, count 0 2006.201.12:25:00.15#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:25:00.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:25:00.15#ibcon#[27=USB\r\n] 2006.201.12:25:00.15#ibcon#*before write, iclass 5, count 0 2006.201.12:25:00.15#ibcon#enter sib2, iclass 5, count 0 2006.201.12:25:00.15#ibcon#flushed, iclass 5, count 0 2006.201.12:25:00.15#ibcon#about to write, iclass 5, count 0 2006.201.12:25:00.15#ibcon#wrote, iclass 5, count 0 2006.201.12:25:00.15#ibcon#about to read 3, iclass 5, count 0 2006.201.12:25:00.18#ibcon#read 3, iclass 5, count 0 2006.201.12:25:00.18#ibcon#about to read 4, iclass 5, count 0 2006.201.12:25:00.18#ibcon#read 4, iclass 5, count 0 2006.201.12:25:00.18#ibcon#about to read 5, iclass 5, count 0 2006.201.12:25:00.18#ibcon#read 5, iclass 5, count 0 2006.201.12:25:00.18#ibcon#about to read 6, iclass 5, count 0 2006.201.12:25:00.18#ibcon#read 6, iclass 5, count 0 2006.201.12:25:00.18#ibcon#end of sib2, iclass 5, count 0 2006.201.12:25:00.18#ibcon#*after write, iclass 5, count 0 2006.201.12:25:00.18#ibcon#*before return 0, iclass 5, count 0 2006.201.12:25:00.18#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:25:00.18#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:25:00.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:25:00.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:25:00.18$vck44/vblo=3,649.99 2006.201.12:25:00.18#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.12:25:00.18#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.12:25:00.18#ibcon#ireg 17 cls_cnt 0 2006.201.12:25:00.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:25:00.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:25:00.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:25:00.18#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:25:00.18#ibcon#first serial, iclass 7, count 0 2006.201.12:25:00.18#ibcon#enter sib2, iclass 7, count 0 2006.201.12:25:00.18#ibcon#flushed, iclass 7, count 0 2006.201.12:25:00.18#ibcon#about to write, iclass 7, count 0 2006.201.12:25:00.18#ibcon#wrote, iclass 7, count 0 2006.201.12:25:00.18#ibcon#about to read 3, iclass 7, count 0 2006.201.12:25:00.20#ibcon#read 3, iclass 7, count 0 2006.201.12:25:00.20#ibcon#about to read 4, iclass 7, count 0 2006.201.12:25:00.20#ibcon#read 4, iclass 7, count 0 2006.201.12:25:00.20#ibcon#about to read 5, iclass 7, count 0 2006.201.12:25:00.20#ibcon#read 5, iclass 7, count 0 2006.201.12:25:00.20#ibcon#about to read 6, iclass 7, count 0 2006.201.12:25:00.20#ibcon#read 6, iclass 7, count 0 2006.201.12:25:00.20#ibcon#end of sib2, iclass 7, count 0 2006.201.12:25:00.20#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:25:00.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:25:00.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:25:00.20#ibcon#*before write, iclass 7, count 0 2006.201.12:25:00.20#ibcon#enter sib2, iclass 7, count 0 2006.201.12:25:00.20#ibcon#flushed, iclass 7, count 0 2006.201.12:25:00.20#ibcon#about to write, iclass 7, count 0 2006.201.12:25:00.20#ibcon#wrote, iclass 7, count 0 2006.201.12:25:00.20#ibcon#about to read 3, iclass 7, count 0 2006.201.12:25:00.24#ibcon#read 3, iclass 7, count 0 2006.201.12:25:00.24#ibcon#about to read 4, iclass 7, count 0 2006.201.12:25:00.24#ibcon#read 4, iclass 7, count 0 2006.201.12:25:00.24#ibcon#about to read 5, iclass 7, count 0 2006.201.12:25:00.24#ibcon#read 5, iclass 7, count 0 2006.201.12:25:00.24#ibcon#about to read 6, iclass 7, count 0 2006.201.12:25:00.24#ibcon#read 6, iclass 7, count 0 2006.201.12:25:00.24#ibcon#end of sib2, iclass 7, count 0 2006.201.12:25:00.24#ibcon#*after write, iclass 7, count 0 2006.201.12:25:00.24#ibcon#*before return 0, iclass 7, count 0 2006.201.12:25:00.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:25:00.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:25:00.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:25:00.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:25:00.24$vck44/vb=3,4 2006.201.12:25:00.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.12:25:00.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.12:25:00.24#ibcon#ireg 11 cls_cnt 2 2006.201.12:25:00.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:25:00.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:25:00.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:25:00.30#ibcon#enter wrdev, iclass 11, count 2 2006.201.12:25:00.30#ibcon#first serial, iclass 11, count 2 2006.201.12:25:00.30#ibcon#enter sib2, iclass 11, count 2 2006.201.12:25:00.30#ibcon#flushed, iclass 11, count 2 2006.201.12:25:00.30#ibcon#about to write, iclass 11, count 2 2006.201.12:25:00.30#ibcon#wrote, iclass 11, count 2 2006.201.12:25:00.30#ibcon#about to read 3, iclass 11, count 2 2006.201.12:25:00.32#ibcon#read 3, iclass 11, count 2 2006.201.12:25:00.32#ibcon#about to read 4, iclass 11, count 2 2006.201.12:25:00.32#ibcon#read 4, iclass 11, count 2 2006.201.12:25:00.32#ibcon#about to read 5, iclass 11, count 2 2006.201.12:25:00.32#ibcon#read 5, iclass 11, count 2 2006.201.12:25:00.32#ibcon#about to read 6, iclass 11, count 2 2006.201.12:25:00.32#ibcon#read 6, iclass 11, count 2 2006.201.12:25:00.32#ibcon#end of sib2, iclass 11, count 2 2006.201.12:25:00.32#ibcon#*mode == 0, iclass 11, count 2 2006.201.12:25:00.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.12:25:00.32#ibcon#[27=AT03-04\r\n] 2006.201.12:25:00.32#ibcon#*before write, iclass 11, count 2 2006.201.12:25:00.32#ibcon#enter sib2, iclass 11, count 2 2006.201.12:25:00.32#ibcon#flushed, iclass 11, count 2 2006.201.12:25:00.32#ibcon#about to write, iclass 11, count 2 2006.201.12:25:00.32#ibcon#wrote, iclass 11, count 2 2006.201.12:25:00.32#ibcon#about to read 3, iclass 11, count 2 2006.201.12:25:00.35#ibcon#read 3, iclass 11, count 2 2006.201.12:25:00.35#ibcon#about to read 4, iclass 11, count 2 2006.201.12:25:00.35#ibcon#read 4, iclass 11, count 2 2006.201.12:25:00.35#ibcon#about to read 5, iclass 11, count 2 2006.201.12:25:00.35#ibcon#read 5, iclass 11, count 2 2006.201.12:25:00.35#ibcon#about to read 6, iclass 11, count 2 2006.201.12:25:00.35#ibcon#read 6, iclass 11, count 2 2006.201.12:25:00.35#ibcon#end of sib2, iclass 11, count 2 2006.201.12:25:00.35#ibcon#*after write, iclass 11, count 2 2006.201.12:25:00.35#ibcon#*before return 0, iclass 11, count 2 2006.201.12:25:00.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:25:00.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:25:00.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.12:25:00.35#ibcon#ireg 7 cls_cnt 0 2006.201.12:25:00.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:25:00.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:25:00.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:25:00.47#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:25:00.47#ibcon#first serial, iclass 11, count 0 2006.201.12:25:00.47#ibcon#enter sib2, iclass 11, count 0 2006.201.12:25:00.47#ibcon#flushed, iclass 11, count 0 2006.201.12:25:00.47#ibcon#about to write, iclass 11, count 0 2006.201.12:25:00.47#ibcon#wrote, iclass 11, count 0 2006.201.12:25:00.47#ibcon#about to read 3, iclass 11, count 0 2006.201.12:25:00.49#ibcon#read 3, iclass 11, count 0 2006.201.12:25:00.49#ibcon#about to read 4, iclass 11, count 0 2006.201.12:25:00.49#ibcon#read 4, iclass 11, count 0 2006.201.12:25:00.49#ibcon#about to read 5, iclass 11, count 0 2006.201.12:25:00.49#ibcon#read 5, iclass 11, count 0 2006.201.12:25:00.49#ibcon#about to read 6, iclass 11, count 0 2006.201.12:25:00.49#ibcon#read 6, iclass 11, count 0 2006.201.12:25:00.49#ibcon#end of sib2, iclass 11, count 0 2006.201.12:25:00.49#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:25:00.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:25:00.49#ibcon#[27=USB\r\n] 2006.201.12:25:00.49#ibcon#*before write, iclass 11, count 0 2006.201.12:25:00.49#ibcon#enter sib2, iclass 11, count 0 2006.201.12:25:00.49#ibcon#flushed, iclass 11, count 0 2006.201.12:25:00.49#ibcon#about to write, iclass 11, count 0 2006.201.12:25:00.49#ibcon#wrote, iclass 11, count 0 2006.201.12:25:00.49#ibcon#about to read 3, iclass 11, count 0 2006.201.12:25:00.52#ibcon#read 3, iclass 11, count 0 2006.201.12:25:00.52#ibcon#about to read 4, iclass 11, count 0 2006.201.12:25:00.52#ibcon#read 4, iclass 11, count 0 2006.201.12:25:00.52#ibcon#about to read 5, iclass 11, count 0 2006.201.12:25:00.52#ibcon#read 5, iclass 11, count 0 2006.201.12:25:00.52#ibcon#about to read 6, iclass 11, count 0 2006.201.12:25:00.52#ibcon#read 6, iclass 11, count 0 2006.201.12:25:00.52#ibcon#end of sib2, iclass 11, count 0 2006.201.12:25:00.52#ibcon#*after write, iclass 11, count 0 2006.201.12:25:00.52#ibcon#*before return 0, iclass 11, count 0 2006.201.12:25:00.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:25:00.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:25:00.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:25:00.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:25:00.52$vck44/vblo=4,679.99 2006.201.12:25:00.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.12:25:00.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.12:25:00.52#ibcon#ireg 17 cls_cnt 0 2006.201.12:25:00.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:25:00.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:25:00.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:25:00.52#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:25:00.52#ibcon#first serial, iclass 13, count 0 2006.201.12:25:00.52#ibcon#enter sib2, iclass 13, count 0 2006.201.12:25:00.52#ibcon#flushed, iclass 13, count 0 2006.201.12:25:00.52#ibcon#about to write, iclass 13, count 0 2006.201.12:25:00.52#ibcon#wrote, iclass 13, count 0 2006.201.12:25:00.52#ibcon#about to read 3, iclass 13, count 0 2006.201.12:25:00.54#ibcon#read 3, iclass 13, count 0 2006.201.12:25:00.54#ibcon#about to read 4, iclass 13, count 0 2006.201.12:25:00.54#ibcon#read 4, iclass 13, count 0 2006.201.12:25:00.54#ibcon#about to read 5, iclass 13, count 0 2006.201.12:25:00.54#ibcon#read 5, iclass 13, count 0 2006.201.12:25:00.54#ibcon#about to read 6, iclass 13, count 0 2006.201.12:25:00.54#ibcon#read 6, iclass 13, count 0 2006.201.12:25:00.54#ibcon#end of sib2, iclass 13, count 0 2006.201.12:25:00.54#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:25:00.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:25:00.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:25:00.54#ibcon#*before write, iclass 13, count 0 2006.201.12:25:00.54#ibcon#enter sib2, iclass 13, count 0 2006.201.12:25:00.54#ibcon#flushed, iclass 13, count 0 2006.201.12:25:00.54#ibcon#about to write, iclass 13, count 0 2006.201.12:25:00.54#ibcon#wrote, iclass 13, count 0 2006.201.12:25:00.54#ibcon#about to read 3, iclass 13, count 0 2006.201.12:25:00.59#ibcon#read 3, iclass 13, count 0 2006.201.12:25:00.59#ibcon#about to read 4, iclass 13, count 0 2006.201.12:25:00.59#ibcon#read 4, iclass 13, count 0 2006.201.12:25:00.59#ibcon#about to read 5, iclass 13, count 0 2006.201.12:25:00.59#ibcon#read 5, iclass 13, count 0 2006.201.12:25:00.59#ibcon#about to read 6, iclass 13, count 0 2006.201.12:25:00.59#ibcon#read 6, iclass 13, count 0 2006.201.12:25:00.59#ibcon#end of sib2, iclass 13, count 0 2006.201.12:25:00.59#ibcon#*after write, iclass 13, count 0 2006.201.12:25:00.59#ibcon#*before return 0, iclass 13, count 0 2006.201.12:25:00.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:25:00.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:25:00.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:25:00.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:25:00.59$vck44/vb=4,5 2006.201.12:25:00.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.12:25:00.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.12:25:00.59#ibcon#ireg 11 cls_cnt 2 2006.201.12:25:00.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:25:00.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:25:00.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:25:00.64#ibcon#enter wrdev, iclass 15, count 2 2006.201.12:25:00.64#ibcon#first serial, iclass 15, count 2 2006.201.12:25:00.64#ibcon#enter sib2, iclass 15, count 2 2006.201.12:25:00.64#ibcon#flushed, iclass 15, count 2 2006.201.12:25:00.64#ibcon#about to write, iclass 15, count 2 2006.201.12:25:00.64#ibcon#wrote, iclass 15, count 2 2006.201.12:25:00.64#ibcon#about to read 3, iclass 15, count 2 2006.201.12:25:00.66#ibcon#read 3, iclass 15, count 2 2006.201.12:25:00.66#ibcon#about to read 4, iclass 15, count 2 2006.201.12:25:00.66#ibcon#read 4, iclass 15, count 2 2006.201.12:25:00.66#ibcon#about to read 5, iclass 15, count 2 2006.201.12:25:00.66#ibcon#read 5, iclass 15, count 2 2006.201.12:25:00.66#ibcon#about to read 6, iclass 15, count 2 2006.201.12:25:00.66#ibcon#read 6, iclass 15, count 2 2006.201.12:25:00.66#ibcon#end of sib2, iclass 15, count 2 2006.201.12:25:00.66#ibcon#*mode == 0, iclass 15, count 2 2006.201.12:25:00.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.12:25:00.66#ibcon#[27=AT04-05\r\n] 2006.201.12:25:00.66#ibcon#*before write, iclass 15, count 2 2006.201.12:25:00.66#ibcon#enter sib2, iclass 15, count 2 2006.201.12:25:00.66#ibcon#flushed, iclass 15, count 2 2006.201.12:25:00.66#ibcon#about to write, iclass 15, count 2 2006.201.12:25:00.66#ibcon#wrote, iclass 15, count 2 2006.201.12:25:00.66#ibcon#about to read 3, iclass 15, count 2 2006.201.12:25:00.69#ibcon#read 3, iclass 15, count 2 2006.201.12:25:00.69#ibcon#about to read 4, iclass 15, count 2 2006.201.12:25:00.69#ibcon#read 4, iclass 15, count 2 2006.201.12:25:00.69#ibcon#about to read 5, iclass 15, count 2 2006.201.12:25:00.69#ibcon#read 5, iclass 15, count 2 2006.201.12:25:00.69#ibcon#about to read 6, iclass 15, count 2 2006.201.12:25:00.69#ibcon#read 6, iclass 15, count 2 2006.201.12:25:00.69#ibcon#end of sib2, iclass 15, count 2 2006.201.12:25:00.69#ibcon#*after write, iclass 15, count 2 2006.201.12:25:00.69#ibcon#*before return 0, iclass 15, count 2 2006.201.12:25:00.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:25:00.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:25:00.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.12:25:00.69#ibcon#ireg 7 cls_cnt 0 2006.201.12:25:00.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:25:00.81#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:25:00.81#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:25:00.81#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:25:00.81#ibcon#first serial, iclass 15, count 0 2006.201.12:25:00.81#ibcon#enter sib2, iclass 15, count 0 2006.201.12:25:00.81#ibcon#flushed, iclass 15, count 0 2006.201.12:25:00.81#ibcon#about to write, iclass 15, count 0 2006.201.12:25:00.81#ibcon#wrote, iclass 15, count 0 2006.201.12:25:00.81#ibcon#about to read 3, iclass 15, count 0 2006.201.12:25:00.83#ibcon#read 3, iclass 15, count 0 2006.201.12:25:00.83#ibcon#about to read 4, iclass 15, count 0 2006.201.12:25:00.83#ibcon#read 4, iclass 15, count 0 2006.201.12:25:00.83#ibcon#about to read 5, iclass 15, count 0 2006.201.12:25:00.83#ibcon#read 5, iclass 15, count 0 2006.201.12:25:00.83#ibcon#about to read 6, iclass 15, count 0 2006.201.12:25:00.83#ibcon#read 6, iclass 15, count 0 2006.201.12:25:00.83#ibcon#end of sib2, iclass 15, count 0 2006.201.12:25:00.83#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:25:00.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:25:00.83#ibcon#[27=USB\r\n] 2006.201.12:25:00.83#ibcon#*before write, iclass 15, count 0 2006.201.12:25:00.83#ibcon#enter sib2, iclass 15, count 0 2006.201.12:25:00.83#ibcon#flushed, iclass 15, count 0 2006.201.12:25:00.83#ibcon#about to write, iclass 15, count 0 2006.201.12:25:00.83#ibcon#wrote, iclass 15, count 0 2006.201.12:25:00.83#ibcon#about to read 3, iclass 15, count 0 2006.201.12:25:00.86#ibcon#read 3, iclass 15, count 0 2006.201.12:25:00.86#ibcon#about to read 4, iclass 15, count 0 2006.201.12:25:00.86#ibcon#read 4, iclass 15, count 0 2006.201.12:25:00.86#ibcon#about to read 5, iclass 15, count 0 2006.201.12:25:00.86#ibcon#read 5, iclass 15, count 0 2006.201.12:25:00.86#ibcon#about to read 6, iclass 15, count 0 2006.201.12:25:00.86#ibcon#read 6, iclass 15, count 0 2006.201.12:25:00.86#ibcon#end of sib2, iclass 15, count 0 2006.201.12:25:00.86#ibcon#*after write, iclass 15, count 0 2006.201.12:25:00.86#ibcon#*before return 0, iclass 15, count 0 2006.201.12:25:00.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:25:00.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:25:00.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:25:00.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:25:00.86$vck44/vblo=5,709.99 2006.201.12:25:00.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.12:25:00.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.12:25:00.86#ibcon#ireg 17 cls_cnt 0 2006.201.12:25:00.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:25:00.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:25:00.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:25:00.86#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:25:00.86#ibcon#first serial, iclass 17, count 0 2006.201.12:25:00.86#ibcon#enter sib2, iclass 17, count 0 2006.201.12:25:00.86#ibcon#flushed, iclass 17, count 0 2006.201.12:25:00.86#ibcon#about to write, iclass 17, count 0 2006.201.12:25:00.86#ibcon#wrote, iclass 17, count 0 2006.201.12:25:00.86#ibcon#about to read 3, iclass 17, count 0 2006.201.12:25:00.88#ibcon#read 3, iclass 17, count 0 2006.201.12:25:00.88#ibcon#about to read 4, iclass 17, count 0 2006.201.12:25:00.88#ibcon#read 4, iclass 17, count 0 2006.201.12:25:00.88#ibcon#about to read 5, iclass 17, count 0 2006.201.12:25:00.88#ibcon#read 5, iclass 17, count 0 2006.201.12:25:00.88#ibcon#about to read 6, iclass 17, count 0 2006.201.12:25:00.88#ibcon#read 6, iclass 17, count 0 2006.201.12:25:00.88#ibcon#end of sib2, iclass 17, count 0 2006.201.12:25:00.88#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:25:00.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:25:00.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:25:00.88#ibcon#*before write, iclass 17, count 0 2006.201.12:25:00.88#ibcon#enter sib2, iclass 17, count 0 2006.201.12:25:00.88#ibcon#flushed, iclass 17, count 0 2006.201.12:25:00.88#ibcon#about to write, iclass 17, count 0 2006.201.12:25:00.88#ibcon#wrote, iclass 17, count 0 2006.201.12:25:00.88#ibcon#about to read 3, iclass 17, count 0 2006.201.12:25:00.92#ibcon#read 3, iclass 17, count 0 2006.201.12:25:00.92#ibcon#about to read 4, iclass 17, count 0 2006.201.12:25:00.92#ibcon#read 4, iclass 17, count 0 2006.201.12:25:00.92#ibcon#about to read 5, iclass 17, count 0 2006.201.12:25:00.92#ibcon#read 5, iclass 17, count 0 2006.201.12:25:00.92#ibcon#about to read 6, iclass 17, count 0 2006.201.12:25:00.92#ibcon#read 6, iclass 17, count 0 2006.201.12:25:00.92#ibcon#end of sib2, iclass 17, count 0 2006.201.12:25:00.92#ibcon#*after write, iclass 17, count 0 2006.201.12:25:00.92#ibcon#*before return 0, iclass 17, count 0 2006.201.12:25:00.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:25:00.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:25:00.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:25:00.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:25:00.92$vck44/vb=5,4 2006.201.12:25:00.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.12:25:00.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.12:25:00.92#ibcon#ireg 11 cls_cnt 2 2006.201.12:25:00.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:25:00.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:25:00.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:25:00.98#ibcon#enter wrdev, iclass 19, count 2 2006.201.12:25:00.98#ibcon#first serial, iclass 19, count 2 2006.201.12:25:00.98#ibcon#enter sib2, iclass 19, count 2 2006.201.12:25:00.98#ibcon#flushed, iclass 19, count 2 2006.201.12:25:00.98#ibcon#about to write, iclass 19, count 2 2006.201.12:25:00.98#ibcon#wrote, iclass 19, count 2 2006.201.12:25:00.98#ibcon#about to read 3, iclass 19, count 2 2006.201.12:25:01.00#ibcon#read 3, iclass 19, count 2 2006.201.12:25:01.00#ibcon#about to read 4, iclass 19, count 2 2006.201.12:25:01.00#ibcon#read 4, iclass 19, count 2 2006.201.12:25:01.00#ibcon#about to read 5, iclass 19, count 2 2006.201.12:25:01.00#ibcon#read 5, iclass 19, count 2 2006.201.12:25:01.00#ibcon#about to read 6, iclass 19, count 2 2006.201.12:25:01.00#ibcon#read 6, iclass 19, count 2 2006.201.12:25:01.00#ibcon#end of sib2, iclass 19, count 2 2006.201.12:25:01.00#ibcon#*mode == 0, iclass 19, count 2 2006.201.12:25:01.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.12:25:01.00#ibcon#[27=AT05-04\r\n] 2006.201.12:25:01.00#ibcon#*before write, iclass 19, count 2 2006.201.12:25:01.00#ibcon#enter sib2, iclass 19, count 2 2006.201.12:25:01.00#ibcon#flushed, iclass 19, count 2 2006.201.12:25:01.00#ibcon#about to write, iclass 19, count 2 2006.201.12:25:01.00#ibcon#wrote, iclass 19, count 2 2006.201.12:25:01.00#ibcon#about to read 3, iclass 19, count 2 2006.201.12:25:01.03#ibcon#read 3, iclass 19, count 2 2006.201.12:25:01.03#ibcon#about to read 4, iclass 19, count 2 2006.201.12:25:01.03#ibcon#read 4, iclass 19, count 2 2006.201.12:25:01.03#ibcon#about to read 5, iclass 19, count 2 2006.201.12:25:01.03#ibcon#read 5, iclass 19, count 2 2006.201.12:25:01.03#ibcon#about to read 6, iclass 19, count 2 2006.201.12:25:01.03#ibcon#read 6, iclass 19, count 2 2006.201.12:25:01.03#ibcon#end of sib2, iclass 19, count 2 2006.201.12:25:01.03#ibcon#*after write, iclass 19, count 2 2006.201.12:25:01.03#ibcon#*before return 0, iclass 19, count 2 2006.201.12:25:01.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:25:01.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:25:01.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.12:25:01.03#ibcon#ireg 7 cls_cnt 0 2006.201.12:25:01.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:25:01.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:25:01.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:25:01.15#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:25:01.15#ibcon#first serial, iclass 19, count 0 2006.201.12:25:01.15#ibcon#enter sib2, iclass 19, count 0 2006.201.12:25:01.15#ibcon#flushed, iclass 19, count 0 2006.201.12:25:01.15#ibcon#about to write, iclass 19, count 0 2006.201.12:25:01.15#ibcon#wrote, iclass 19, count 0 2006.201.12:25:01.15#ibcon#about to read 3, iclass 19, count 0 2006.201.12:25:01.17#ibcon#read 3, iclass 19, count 0 2006.201.12:25:01.17#ibcon#about to read 4, iclass 19, count 0 2006.201.12:25:01.17#ibcon#read 4, iclass 19, count 0 2006.201.12:25:01.17#ibcon#about to read 5, iclass 19, count 0 2006.201.12:25:01.17#ibcon#read 5, iclass 19, count 0 2006.201.12:25:01.17#ibcon#about to read 6, iclass 19, count 0 2006.201.12:25:01.17#ibcon#read 6, iclass 19, count 0 2006.201.12:25:01.17#ibcon#end of sib2, iclass 19, count 0 2006.201.12:25:01.17#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:25:01.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:25:01.17#ibcon#[27=USB\r\n] 2006.201.12:25:01.17#ibcon#*before write, iclass 19, count 0 2006.201.12:25:01.17#ibcon#enter sib2, iclass 19, count 0 2006.201.12:25:01.17#ibcon#flushed, iclass 19, count 0 2006.201.12:25:01.17#ibcon#about to write, iclass 19, count 0 2006.201.12:25:01.17#ibcon#wrote, iclass 19, count 0 2006.201.12:25:01.17#ibcon#about to read 3, iclass 19, count 0 2006.201.12:25:01.20#ibcon#read 3, iclass 19, count 0 2006.201.12:25:01.20#ibcon#about to read 4, iclass 19, count 0 2006.201.12:25:01.20#ibcon#read 4, iclass 19, count 0 2006.201.12:25:01.20#ibcon#about to read 5, iclass 19, count 0 2006.201.12:25:01.20#ibcon#read 5, iclass 19, count 0 2006.201.12:25:01.20#ibcon#about to read 6, iclass 19, count 0 2006.201.12:25:01.20#ibcon#read 6, iclass 19, count 0 2006.201.12:25:01.20#ibcon#end of sib2, iclass 19, count 0 2006.201.12:25:01.20#ibcon#*after write, iclass 19, count 0 2006.201.12:25:01.20#ibcon#*before return 0, iclass 19, count 0 2006.201.12:25:01.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:25:01.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:25:01.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:25:01.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:25:01.20$vck44/vblo=6,719.99 2006.201.12:25:01.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.12:25:01.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.12:25:01.20#ibcon#ireg 17 cls_cnt 0 2006.201.12:25:01.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:25:01.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:25:01.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:25:01.20#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:25:01.20#ibcon#first serial, iclass 21, count 0 2006.201.12:25:01.20#ibcon#enter sib2, iclass 21, count 0 2006.201.12:25:01.20#ibcon#flushed, iclass 21, count 0 2006.201.12:25:01.20#ibcon#about to write, iclass 21, count 0 2006.201.12:25:01.20#ibcon#wrote, iclass 21, count 0 2006.201.12:25:01.20#ibcon#about to read 3, iclass 21, count 0 2006.201.12:25:01.22#ibcon#read 3, iclass 21, count 0 2006.201.12:25:01.22#ibcon#about to read 4, iclass 21, count 0 2006.201.12:25:01.22#ibcon#read 4, iclass 21, count 0 2006.201.12:25:01.22#ibcon#about to read 5, iclass 21, count 0 2006.201.12:25:01.22#ibcon#read 5, iclass 21, count 0 2006.201.12:25:01.22#ibcon#about to read 6, iclass 21, count 0 2006.201.12:25:01.22#ibcon#read 6, iclass 21, count 0 2006.201.12:25:01.22#ibcon#end of sib2, iclass 21, count 0 2006.201.12:25:01.22#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:25:01.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:25:01.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:25:01.22#ibcon#*before write, iclass 21, count 0 2006.201.12:25:01.22#ibcon#enter sib2, iclass 21, count 0 2006.201.12:25:01.22#ibcon#flushed, iclass 21, count 0 2006.201.12:25:01.22#ibcon#about to write, iclass 21, count 0 2006.201.12:25:01.22#ibcon#wrote, iclass 21, count 0 2006.201.12:25:01.22#ibcon#about to read 3, iclass 21, count 0 2006.201.12:25:01.26#ibcon#read 3, iclass 21, count 0 2006.201.12:25:01.26#ibcon#about to read 4, iclass 21, count 0 2006.201.12:25:01.26#ibcon#read 4, iclass 21, count 0 2006.201.12:25:01.26#ibcon#about to read 5, iclass 21, count 0 2006.201.12:25:01.26#ibcon#read 5, iclass 21, count 0 2006.201.12:25:01.26#ibcon#about to read 6, iclass 21, count 0 2006.201.12:25:01.26#ibcon#read 6, iclass 21, count 0 2006.201.12:25:01.26#ibcon#end of sib2, iclass 21, count 0 2006.201.12:25:01.26#ibcon#*after write, iclass 21, count 0 2006.201.12:25:01.26#ibcon#*before return 0, iclass 21, count 0 2006.201.12:25:01.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:25:01.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:25:01.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:25:01.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:25:01.26$vck44/vb=6,4 2006.201.12:25:01.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.12:25:01.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.12:25:01.26#ibcon#ireg 11 cls_cnt 2 2006.201.12:25:01.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:25:01.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:25:01.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:25:01.32#ibcon#enter wrdev, iclass 23, count 2 2006.201.12:25:01.32#ibcon#first serial, iclass 23, count 2 2006.201.12:25:01.32#ibcon#enter sib2, iclass 23, count 2 2006.201.12:25:01.32#ibcon#flushed, iclass 23, count 2 2006.201.12:25:01.32#ibcon#about to write, iclass 23, count 2 2006.201.12:25:01.32#ibcon#wrote, iclass 23, count 2 2006.201.12:25:01.32#ibcon#about to read 3, iclass 23, count 2 2006.201.12:25:01.34#ibcon#read 3, iclass 23, count 2 2006.201.12:25:01.34#ibcon#about to read 4, iclass 23, count 2 2006.201.12:25:01.34#ibcon#read 4, iclass 23, count 2 2006.201.12:25:01.34#ibcon#about to read 5, iclass 23, count 2 2006.201.12:25:01.34#ibcon#read 5, iclass 23, count 2 2006.201.12:25:01.34#ibcon#about to read 6, iclass 23, count 2 2006.201.12:25:01.34#ibcon#read 6, iclass 23, count 2 2006.201.12:25:01.34#ibcon#end of sib2, iclass 23, count 2 2006.201.12:25:01.34#ibcon#*mode == 0, iclass 23, count 2 2006.201.12:25:01.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.12:25:01.34#ibcon#[27=AT06-04\r\n] 2006.201.12:25:01.34#ibcon#*before write, iclass 23, count 2 2006.201.12:25:01.34#ibcon#enter sib2, iclass 23, count 2 2006.201.12:25:01.34#ibcon#flushed, iclass 23, count 2 2006.201.12:25:01.34#ibcon#about to write, iclass 23, count 2 2006.201.12:25:01.34#ibcon#wrote, iclass 23, count 2 2006.201.12:25:01.34#ibcon#about to read 3, iclass 23, count 2 2006.201.12:25:01.37#ibcon#read 3, iclass 23, count 2 2006.201.12:25:01.37#ibcon#about to read 4, iclass 23, count 2 2006.201.12:25:01.37#ibcon#read 4, iclass 23, count 2 2006.201.12:25:01.37#ibcon#about to read 5, iclass 23, count 2 2006.201.12:25:01.37#ibcon#read 5, iclass 23, count 2 2006.201.12:25:01.37#ibcon#about to read 6, iclass 23, count 2 2006.201.12:25:01.37#ibcon#read 6, iclass 23, count 2 2006.201.12:25:01.37#ibcon#end of sib2, iclass 23, count 2 2006.201.12:25:01.37#ibcon#*after write, iclass 23, count 2 2006.201.12:25:01.37#ibcon#*before return 0, iclass 23, count 2 2006.201.12:25:01.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:25:01.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:25:01.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.12:25:01.37#ibcon#ireg 7 cls_cnt 0 2006.201.12:25:01.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:25:01.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:25:01.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:25:01.49#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:25:01.49#ibcon#first serial, iclass 23, count 0 2006.201.12:25:01.49#ibcon#enter sib2, iclass 23, count 0 2006.201.12:25:01.49#ibcon#flushed, iclass 23, count 0 2006.201.12:25:01.49#ibcon#about to write, iclass 23, count 0 2006.201.12:25:01.49#ibcon#wrote, iclass 23, count 0 2006.201.12:25:01.49#ibcon#about to read 3, iclass 23, count 0 2006.201.12:25:01.51#ibcon#read 3, iclass 23, count 0 2006.201.12:25:01.51#ibcon#about to read 4, iclass 23, count 0 2006.201.12:25:01.51#ibcon#read 4, iclass 23, count 0 2006.201.12:25:01.51#ibcon#about to read 5, iclass 23, count 0 2006.201.12:25:01.51#ibcon#read 5, iclass 23, count 0 2006.201.12:25:01.51#ibcon#about to read 6, iclass 23, count 0 2006.201.12:25:01.51#ibcon#read 6, iclass 23, count 0 2006.201.12:25:01.51#ibcon#end of sib2, iclass 23, count 0 2006.201.12:25:01.51#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:25:01.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:25:01.51#ibcon#[27=USB\r\n] 2006.201.12:25:01.51#ibcon#*before write, iclass 23, count 0 2006.201.12:25:01.51#ibcon#enter sib2, iclass 23, count 0 2006.201.12:25:01.51#ibcon#flushed, iclass 23, count 0 2006.201.12:25:01.51#ibcon#about to write, iclass 23, count 0 2006.201.12:25:01.51#ibcon#wrote, iclass 23, count 0 2006.201.12:25:01.51#ibcon#about to read 3, iclass 23, count 0 2006.201.12:25:01.54#ibcon#read 3, iclass 23, count 0 2006.201.12:25:01.54#ibcon#about to read 4, iclass 23, count 0 2006.201.12:25:01.54#ibcon#read 4, iclass 23, count 0 2006.201.12:25:01.54#ibcon#about to read 5, iclass 23, count 0 2006.201.12:25:01.54#ibcon#read 5, iclass 23, count 0 2006.201.12:25:01.54#ibcon#about to read 6, iclass 23, count 0 2006.201.12:25:01.54#ibcon#read 6, iclass 23, count 0 2006.201.12:25:01.54#ibcon#end of sib2, iclass 23, count 0 2006.201.12:25:01.54#ibcon#*after write, iclass 23, count 0 2006.201.12:25:01.54#ibcon#*before return 0, iclass 23, count 0 2006.201.12:25:01.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:25:01.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:25:01.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:25:01.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:25:01.54$vck44/vblo=7,734.99 2006.201.12:25:01.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.12:25:01.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.12:25:01.54#ibcon#ireg 17 cls_cnt 0 2006.201.12:25:01.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:25:01.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:25:01.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:25:01.54#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:25:01.54#ibcon#first serial, iclass 25, count 0 2006.201.12:25:01.54#ibcon#enter sib2, iclass 25, count 0 2006.201.12:25:01.54#ibcon#flushed, iclass 25, count 0 2006.201.12:25:01.54#ibcon#about to write, iclass 25, count 0 2006.201.12:25:01.54#ibcon#wrote, iclass 25, count 0 2006.201.12:25:01.54#ibcon#about to read 3, iclass 25, count 0 2006.201.12:25:01.56#ibcon#read 3, iclass 25, count 0 2006.201.12:25:01.56#ibcon#about to read 4, iclass 25, count 0 2006.201.12:25:01.56#ibcon#read 4, iclass 25, count 0 2006.201.12:25:01.56#ibcon#about to read 5, iclass 25, count 0 2006.201.12:25:01.56#ibcon#read 5, iclass 25, count 0 2006.201.12:25:01.56#ibcon#about to read 6, iclass 25, count 0 2006.201.12:25:01.56#ibcon#read 6, iclass 25, count 0 2006.201.12:25:01.56#ibcon#end of sib2, iclass 25, count 0 2006.201.12:25:01.56#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:25:01.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:25:01.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:25:01.56#ibcon#*before write, iclass 25, count 0 2006.201.12:25:01.56#ibcon#enter sib2, iclass 25, count 0 2006.201.12:25:01.56#ibcon#flushed, iclass 25, count 0 2006.201.12:25:01.56#ibcon#about to write, iclass 25, count 0 2006.201.12:25:01.56#ibcon#wrote, iclass 25, count 0 2006.201.12:25:01.56#ibcon#about to read 3, iclass 25, count 0 2006.201.12:25:01.60#ibcon#read 3, iclass 25, count 0 2006.201.12:25:01.60#ibcon#about to read 4, iclass 25, count 0 2006.201.12:25:01.60#ibcon#read 4, iclass 25, count 0 2006.201.12:25:01.60#ibcon#about to read 5, iclass 25, count 0 2006.201.12:25:01.60#ibcon#read 5, iclass 25, count 0 2006.201.12:25:01.60#ibcon#about to read 6, iclass 25, count 0 2006.201.12:25:01.60#ibcon#read 6, iclass 25, count 0 2006.201.12:25:01.60#ibcon#end of sib2, iclass 25, count 0 2006.201.12:25:01.60#ibcon#*after write, iclass 25, count 0 2006.201.12:25:01.60#ibcon#*before return 0, iclass 25, count 0 2006.201.12:25:01.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:25:01.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:25:01.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:25:01.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:25:01.60$vck44/vb=7,4 2006.201.12:25:01.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.12:25:01.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.12:25:01.60#ibcon#ireg 11 cls_cnt 2 2006.201.12:25:01.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:25:01.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:25:01.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:25:01.66#ibcon#enter wrdev, iclass 27, count 2 2006.201.12:25:01.66#ibcon#first serial, iclass 27, count 2 2006.201.12:25:01.66#ibcon#enter sib2, iclass 27, count 2 2006.201.12:25:01.66#ibcon#flushed, iclass 27, count 2 2006.201.12:25:01.66#ibcon#about to write, iclass 27, count 2 2006.201.12:25:01.66#ibcon#wrote, iclass 27, count 2 2006.201.12:25:01.66#ibcon#about to read 3, iclass 27, count 2 2006.201.12:25:01.68#ibcon#read 3, iclass 27, count 2 2006.201.12:25:01.68#ibcon#about to read 4, iclass 27, count 2 2006.201.12:25:01.68#ibcon#read 4, iclass 27, count 2 2006.201.12:25:01.68#ibcon#about to read 5, iclass 27, count 2 2006.201.12:25:01.68#ibcon#read 5, iclass 27, count 2 2006.201.12:25:01.68#ibcon#about to read 6, iclass 27, count 2 2006.201.12:25:01.68#ibcon#read 6, iclass 27, count 2 2006.201.12:25:01.68#ibcon#end of sib2, iclass 27, count 2 2006.201.12:25:01.68#ibcon#*mode == 0, iclass 27, count 2 2006.201.12:25:01.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.12:25:01.68#ibcon#[27=AT07-04\r\n] 2006.201.12:25:01.68#ibcon#*before write, iclass 27, count 2 2006.201.12:25:01.68#ibcon#enter sib2, iclass 27, count 2 2006.201.12:25:01.68#ibcon#flushed, iclass 27, count 2 2006.201.12:25:01.68#ibcon#about to write, iclass 27, count 2 2006.201.12:25:01.68#ibcon#wrote, iclass 27, count 2 2006.201.12:25:01.68#ibcon#about to read 3, iclass 27, count 2 2006.201.12:25:01.71#ibcon#read 3, iclass 27, count 2 2006.201.12:25:01.71#ibcon#about to read 4, iclass 27, count 2 2006.201.12:25:01.71#ibcon#read 4, iclass 27, count 2 2006.201.12:25:01.71#ibcon#about to read 5, iclass 27, count 2 2006.201.12:25:01.71#ibcon#read 5, iclass 27, count 2 2006.201.12:25:01.71#ibcon#about to read 6, iclass 27, count 2 2006.201.12:25:01.71#ibcon#read 6, iclass 27, count 2 2006.201.12:25:01.71#ibcon#end of sib2, iclass 27, count 2 2006.201.12:25:01.71#ibcon#*after write, iclass 27, count 2 2006.201.12:25:01.71#ibcon#*before return 0, iclass 27, count 2 2006.201.12:25:01.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:25:01.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:25:01.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.12:25:01.71#ibcon#ireg 7 cls_cnt 0 2006.201.12:25:01.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:25:01.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:25:01.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:25:01.83#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:25:01.83#ibcon#first serial, iclass 27, count 0 2006.201.12:25:01.83#ibcon#enter sib2, iclass 27, count 0 2006.201.12:25:01.83#ibcon#flushed, iclass 27, count 0 2006.201.12:25:01.83#ibcon#about to write, iclass 27, count 0 2006.201.12:25:01.83#ibcon#wrote, iclass 27, count 0 2006.201.12:25:01.83#ibcon#about to read 3, iclass 27, count 0 2006.201.12:25:01.85#ibcon#read 3, iclass 27, count 0 2006.201.12:25:01.85#ibcon#about to read 4, iclass 27, count 0 2006.201.12:25:01.85#ibcon#read 4, iclass 27, count 0 2006.201.12:25:01.85#ibcon#about to read 5, iclass 27, count 0 2006.201.12:25:01.85#ibcon#read 5, iclass 27, count 0 2006.201.12:25:01.85#ibcon#about to read 6, iclass 27, count 0 2006.201.12:25:01.85#ibcon#read 6, iclass 27, count 0 2006.201.12:25:01.85#ibcon#end of sib2, iclass 27, count 0 2006.201.12:25:01.85#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:25:01.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:25:01.85#ibcon#[27=USB\r\n] 2006.201.12:25:01.85#ibcon#*before write, iclass 27, count 0 2006.201.12:25:01.85#ibcon#enter sib2, iclass 27, count 0 2006.201.12:25:01.85#ibcon#flushed, iclass 27, count 0 2006.201.12:25:01.85#ibcon#about to write, iclass 27, count 0 2006.201.12:25:01.85#ibcon#wrote, iclass 27, count 0 2006.201.12:25:01.85#ibcon#about to read 3, iclass 27, count 0 2006.201.12:25:01.88#ibcon#read 3, iclass 27, count 0 2006.201.12:25:01.88#ibcon#about to read 4, iclass 27, count 0 2006.201.12:25:01.88#ibcon#read 4, iclass 27, count 0 2006.201.12:25:01.88#ibcon#about to read 5, iclass 27, count 0 2006.201.12:25:01.88#ibcon#read 5, iclass 27, count 0 2006.201.12:25:01.88#ibcon#about to read 6, iclass 27, count 0 2006.201.12:25:01.88#ibcon#read 6, iclass 27, count 0 2006.201.12:25:01.88#ibcon#end of sib2, iclass 27, count 0 2006.201.12:25:01.88#ibcon#*after write, iclass 27, count 0 2006.201.12:25:01.88#ibcon#*before return 0, iclass 27, count 0 2006.201.12:25:01.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:25:01.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:25:01.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:25:01.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:25:01.88$vck44/vblo=8,744.99 2006.201.12:25:01.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.12:25:01.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.12:25:01.88#ibcon#ireg 17 cls_cnt 0 2006.201.12:25:01.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:25:01.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:25:01.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:25:01.88#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:25:01.88#ibcon#first serial, iclass 29, count 0 2006.201.12:25:01.88#ibcon#enter sib2, iclass 29, count 0 2006.201.12:25:01.88#ibcon#flushed, iclass 29, count 0 2006.201.12:25:01.88#ibcon#about to write, iclass 29, count 0 2006.201.12:25:01.88#ibcon#wrote, iclass 29, count 0 2006.201.12:25:01.88#ibcon#about to read 3, iclass 29, count 0 2006.201.12:25:01.90#ibcon#read 3, iclass 29, count 0 2006.201.12:25:01.90#ibcon#about to read 4, iclass 29, count 0 2006.201.12:25:01.90#ibcon#read 4, iclass 29, count 0 2006.201.12:25:01.90#ibcon#about to read 5, iclass 29, count 0 2006.201.12:25:01.90#ibcon#read 5, iclass 29, count 0 2006.201.12:25:01.90#ibcon#about to read 6, iclass 29, count 0 2006.201.12:25:01.90#ibcon#read 6, iclass 29, count 0 2006.201.12:25:01.90#ibcon#end of sib2, iclass 29, count 0 2006.201.12:25:01.90#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:25:01.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:25:01.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:25:01.90#ibcon#*before write, iclass 29, count 0 2006.201.12:25:01.90#ibcon#enter sib2, iclass 29, count 0 2006.201.12:25:01.90#ibcon#flushed, iclass 29, count 0 2006.201.12:25:01.90#ibcon#about to write, iclass 29, count 0 2006.201.12:25:01.90#ibcon#wrote, iclass 29, count 0 2006.201.12:25:01.90#ibcon#about to read 3, iclass 29, count 0 2006.201.12:25:01.94#ibcon#read 3, iclass 29, count 0 2006.201.12:25:01.94#ibcon#about to read 4, iclass 29, count 0 2006.201.12:25:01.94#ibcon#read 4, iclass 29, count 0 2006.201.12:25:01.94#ibcon#about to read 5, iclass 29, count 0 2006.201.12:25:01.94#ibcon#read 5, iclass 29, count 0 2006.201.12:25:01.94#ibcon#about to read 6, iclass 29, count 0 2006.201.12:25:01.94#ibcon#read 6, iclass 29, count 0 2006.201.12:25:01.94#ibcon#end of sib2, iclass 29, count 0 2006.201.12:25:01.94#ibcon#*after write, iclass 29, count 0 2006.201.12:25:01.94#ibcon#*before return 0, iclass 29, count 0 2006.201.12:25:01.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:25:01.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:25:01.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:25:01.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:25:01.94$vck44/vb=8,4 2006.201.12:25:01.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.12:25:01.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.12:25:01.94#ibcon#ireg 11 cls_cnt 2 2006.201.12:25:01.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:25:02.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:25:02.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:25:02.00#ibcon#enter wrdev, iclass 31, count 2 2006.201.12:25:02.00#ibcon#first serial, iclass 31, count 2 2006.201.12:25:02.00#ibcon#enter sib2, iclass 31, count 2 2006.201.12:25:02.00#ibcon#flushed, iclass 31, count 2 2006.201.12:25:02.00#ibcon#about to write, iclass 31, count 2 2006.201.12:25:02.00#ibcon#wrote, iclass 31, count 2 2006.201.12:25:02.00#ibcon#about to read 3, iclass 31, count 2 2006.201.12:25:02.02#ibcon#read 3, iclass 31, count 2 2006.201.12:25:02.02#ibcon#about to read 4, iclass 31, count 2 2006.201.12:25:02.02#ibcon#read 4, iclass 31, count 2 2006.201.12:25:02.02#ibcon#about to read 5, iclass 31, count 2 2006.201.12:25:02.02#ibcon#read 5, iclass 31, count 2 2006.201.12:25:02.02#ibcon#about to read 6, iclass 31, count 2 2006.201.12:25:02.02#ibcon#read 6, iclass 31, count 2 2006.201.12:25:02.02#ibcon#end of sib2, iclass 31, count 2 2006.201.12:25:02.02#ibcon#*mode == 0, iclass 31, count 2 2006.201.12:25:02.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.12:25:02.02#ibcon#[27=AT08-04\r\n] 2006.201.12:25:02.02#ibcon#*before write, iclass 31, count 2 2006.201.12:25:02.02#ibcon#enter sib2, iclass 31, count 2 2006.201.12:25:02.02#ibcon#flushed, iclass 31, count 2 2006.201.12:25:02.02#ibcon#about to write, iclass 31, count 2 2006.201.12:25:02.02#ibcon#wrote, iclass 31, count 2 2006.201.12:25:02.02#ibcon#about to read 3, iclass 31, count 2 2006.201.12:25:02.05#ibcon#read 3, iclass 31, count 2 2006.201.12:25:02.05#ibcon#about to read 4, iclass 31, count 2 2006.201.12:25:02.05#ibcon#read 4, iclass 31, count 2 2006.201.12:25:02.05#ibcon#about to read 5, iclass 31, count 2 2006.201.12:25:02.05#ibcon#read 5, iclass 31, count 2 2006.201.12:25:02.05#ibcon#about to read 6, iclass 31, count 2 2006.201.12:25:02.05#ibcon#read 6, iclass 31, count 2 2006.201.12:25:02.05#ibcon#end of sib2, iclass 31, count 2 2006.201.12:25:02.05#ibcon#*after write, iclass 31, count 2 2006.201.12:25:02.05#ibcon#*before return 0, iclass 31, count 2 2006.201.12:25:02.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:25:02.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:25:02.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.12:25:02.05#ibcon#ireg 7 cls_cnt 0 2006.201.12:25:02.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:25:02.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:25:02.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:25:02.17#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:25:02.17#ibcon#first serial, iclass 31, count 0 2006.201.12:25:02.17#ibcon#enter sib2, iclass 31, count 0 2006.201.12:25:02.17#ibcon#flushed, iclass 31, count 0 2006.201.12:25:02.17#ibcon#about to write, iclass 31, count 0 2006.201.12:25:02.17#ibcon#wrote, iclass 31, count 0 2006.201.12:25:02.17#ibcon#about to read 3, iclass 31, count 0 2006.201.12:25:02.20#ibcon#read 3, iclass 31, count 0 2006.201.12:25:02.20#ibcon#about to read 4, iclass 31, count 0 2006.201.12:25:02.20#ibcon#read 4, iclass 31, count 0 2006.201.12:25:02.20#ibcon#about to read 5, iclass 31, count 0 2006.201.12:25:02.20#ibcon#read 5, iclass 31, count 0 2006.201.12:25:02.20#ibcon#about to read 6, iclass 31, count 0 2006.201.12:25:02.20#ibcon#read 6, iclass 31, count 0 2006.201.12:25:02.20#ibcon#end of sib2, iclass 31, count 0 2006.201.12:25:02.20#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:25:02.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:25:02.20#ibcon#[27=USB\r\n] 2006.201.12:25:02.20#ibcon#*before write, iclass 31, count 0 2006.201.12:25:02.20#ibcon#enter sib2, iclass 31, count 0 2006.201.12:25:02.20#ibcon#flushed, iclass 31, count 0 2006.201.12:25:02.20#ibcon#about to write, iclass 31, count 0 2006.201.12:25:02.20#ibcon#wrote, iclass 31, count 0 2006.201.12:25:02.20#ibcon#about to read 3, iclass 31, count 0 2006.201.12:25:02.23#ibcon#read 3, iclass 31, count 0 2006.201.12:25:02.23#ibcon#about to read 4, iclass 31, count 0 2006.201.12:25:02.23#ibcon#read 4, iclass 31, count 0 2006.201.12:25:02.23#ibcon#about to read 5, iclass 31, count 0 2006.201.12:25:02.23#ibcon#read 5, iclass 31, count 0 2006.201.12:25:02.23#ibcon#about to read 6, iclass 31, count 0 2006.201.12:25:02.23#ibcon#read 6, iclass 31, count 0 2006.201.12:25:02.23#ibcon#end of sib2, iclass 31, count 0 2006.201.12:25:02.23#ibcon#*after write, iclass 31, count 0 2006.201.12:25:02.23#ibcon#*before return 0, iclass 31, count 0 2006.201.12:25:02.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:25:02.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:25:02.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:25:02.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:25:02.23$vck44/vabw=wide 2006.201.12:25:02.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.12:25:02.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.12:25:02.23#ibcon#ireg 8 cls_cnt 0 2006.201.12:25:02.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:25:02.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:25:02.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:25:02.23#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:25:02.23#ibcon#first serial, iclass 33, count 0 2006.201.12:25:02.23#ibcon#enter sib2, iclass 33, count 0 2006.201.12:25:02.23#ibcon#flushed, iclass 33, count 0 2006.201.12:25:02.23#ibcon#about to write, iclass 33, count 0 2006.201.12:25:02.23#ibcon#wrote, iclass 33, count 0 2006.201.12:25:02.23#ibcon#about to read 3, iclass 33, count 0 2006.201.12:25:02.25#ibcon#read 3, iclass 33, count 0 2006.201.12:25:02.25#ibcon#about to read 4, iclass 33, count 0 2006.201.12:25:02.25#ibcon#read 4, iclass 33, count 0 2006.201.12:25:02.25#ibcon#about to read 5, iclass 33, count 0 2006.201.12:25:02.25#ibcon#read 5, iclass 33, count 0 2006.201.12:25:02.25#ibcon#about to read 6, iclass 33, count 0 2006.201.12:25:02.25#ibcon#read 6, iclass 33, count 0 2006.201.12:25:02.25#ibcon#end of sib2, iclass 33, count 0 2006.201.12:25:02.25#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:25:02.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:25:02.25#ibcon#[25=BW32\r\n] 2006.201.12:25:02.25#ibcon#*before write, iclass 33, count 0 2006.201.12:25:02.25#ibcon#enter sib2, iclass 33, count 0 2006.201.12:25:02.25#ibcon#flushed, iclass 33, count 0 2006.201.12:25:02.25#ibcon#about to write, iclass 33, count 0 2006.201.12:25:02.25#ibcon#wrote, iclass 33, count 0 2006.201.12:25:02.25#ibcon#about to read 3, iclass 33, count 0 2006.201.12:25:02.28#ibcon#read 3, iclass 33, count 0 2006.201.12:25:02.28#ibcon#about to read 4, iclass 33, count 0 2006.201.12:25:02.28#ibcon#read 4, iclass 33, count 0 2006.201.12:25:02.28#ibcon#about to read 5, iclass 33, count 0 2006.201.12:25:02.28#ibcon#read 5, iclass 33, count 0 2006.201.12:25:02.28#ibcon#about to read 6, iclass 33, count 0 2006.201.12:25:02.28#ibcon#read 6, iclass 33, count 0 2006.201.12:25:02.28#ibcon#end of sib2, iclass 33, count 0 2006.201.12:25:02.28#ibcon#*after write, iclass 33, count 0 2006.201.12:25:02.28#ibcon#*before return 0, iclass 33, count 0 2006.201.12:25:02.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:25:02.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:25:02.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:25:02.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:25:02.28$vck44/vbbw=wide 2006.201.12:25:02.28#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.12:25:02.28#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.12:25:02.28#ibcon#ireg 8 cls_cnt 0 2006.201.12:25:02.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:25:02.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:25:02.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:25:02.35#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:25:02.35#ibcon#first serial, iclass 35, count 0 2006.201.12:25:02.35#ibcon#enter sib2, iclass 35, count 0 2006.201.12:25:02.35#ibcon#flushed, iclass 35, count 0 2006.201.12:25:02.35#ibcon#about to write, iclass 35, count 0 2006.201.12:25:02.35#ibcon#wrote, iclass 35, count 0 2006.201.12:25:02.35#ibcon#about to read 3, iclass 35, count 0 2006.201.12:25:02.37#ibcon#read 3, iclass 35, count 0 2006.201.12:25:02.37#ibcon#about to read 4, iclass 35, count 0 2006.201.12:25:02.37#ibcon#read 4, iclass 35, count 0 2006.201.12:25:02.37#ibcon#about to read 5, iclass 35, count 0 2006.201.12:25:02.37#ibcon#read 5, iclass 35, count 0 2006.201.12:25:02.37#ibcon#about to read 6, iclass 35, count 0 2006.201.12:25:02.37#ibcon#read 6, iclass 35, count 0 2006.201.12:25:02.37#ibcon#end of sib2, iclass 35, count 0 2006.201.12:25:02.37#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:25:02.37#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:25:02.37#ibcon#[27=BW32\r\n] 2006.201.12:25:02.37#ibcon#*before write, iclass 35, count 0 2006.201.12:25:02.37#ibcon#enter sib2, iclass 35, count 0 2006.201.12:25:02.37#ibcon#flushed, iclass 35, count 0 2006.201.12:25:02.37#ibcon#about to write, iclass 35, count 0 2006.201.12:25:02.37#ibcon#wrote, iclass 35, count 0 2006.201.12:25:02.37#ibcon#about to read 3, iclass 35, count 0 2006.201.12:25:02.40#ibcon#read 3, iclass 35, count 0 2006.201.12:25:02.40#ibcon#about to read 4, iclass 35, count 0 2006.201.12:25:02.40#ibcon#read 4, iclass 35, count 0 2006.201.12:25:02.40#ibcon#about to read 5, iclass 35, count 0 2006.201.12:25:02.40#ibcon#read 5, iclass 35, count 0 2006.201.12:25:02.40#ibcon#about to read 6, iclass 35, count 0 2006.201.12:25:02.40#ibcon#read 6, iclass 35, count 0 2006.201.12:25:02.40#ibcon#end of sib2, iclass 35, count 0 2006.201.12:25:02.40#ibcon#*after write, iclass 35, count 0 2006.201.12:25:02.40#ibcon#*before return 0, iclass 35, count 0 2006.201.12:25:02.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:25:02.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:25:02.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:25:02.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:25:02.40$setupk4/ifdk4 2006.201.12:25:02.40$ifdk4/lo= 2006.201.12:25:02.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:25:02.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:25:02.40$ifdk4/patch= 2006.201.12:25:02.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:25:02.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:25:02.40$setupk4/!*+20s 2006.201.12:25:03.89#abcon#<5=/04 1.9 3.7 21.161001004.1\r\n> 2006.201.12:25:03.91#abcon#{5=INTERFACE CLEAR} 2006.201.12:25:03.97#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:25:10.14#trakl#Source acquired 2006.201.12:25:10.14#flagr#flagr/antenna,acquired 2006.201.12:25:14.06#abcon#<5=/04 1.9 3.7 21.151001004.1\r\n> 2006.201.12:25:14.08#abcon#{5=INTERFACE CLEAR} 2006.201.12:25:14.14#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:25:16.87$setupk4/"tpicd 2006.201.12:25:16.87$setupk4/echo=off 2006.201.12:25:16.87$setupk4/xlog=off 2006.201.12:25:16.87:!2006.201.12:26:14 2006.201.12:26:14.00:preob 2006.201.12:26:14.14/onsource/TRACKING 2006.201.12:26:14.14:!2006.201.12:26:24 2006.201.12:26:24.00:"tape 2006.201.12:26:24.00:"st=record 2006.201.12:26:24.00:data_valid=on 2006.201.12:26:24.00:midob 2006.201.12:26:25.14/onsource/TRACKING 2006.201.12:26:25.14/wx/21.15,1004.1,100 2006.201.12:26:25.31/cable/+6.4745E-03 2006.201.12:26:26.40/va/01,08,usb,yes,33,35 2006.201.12:26:26.40/va/02,07,usb,yes,35,36 2006.201.12:26:26.40/va/03,08,usb,yes,32,33 2006.201.12:26:26.40/va/04,07,usb,yes,36,38 2006.201.12:26:26.40/va/05,04,usb,yes,32,33 2006.201.12:26:26.40/va/06,05,usb,yes,32,32 2006.201.12:26:26.40/va/07,05,usb,yes,31,32 2006.201.12:26:26.40/va/08,04,usb,yes,31,37 2006.201.12:26:26.63/valo/01,524.99,yes,locked 2006.201.12:26:26.63/valo/02,534.99,yes,locked 2006.201.12:26:26.63/valo/03,564.99,yes,locked 2006.201.12:26:26.63/valo/04,624.99,yes,locked 2006.201.12:26:26.63/valo/05,734.99,yes,locked 2006.201.12:26:26.63/valo/06,814.99,yes,locked 2006.201.12:26:26.63/valo/07,864.99,yes,locked 2006.201.12:26:26.63/valo/08,884.99,yes,locked 2006.201.12:26:27.72/vb/01,04,usb,yes,36,33 2006.201.12:26:27.72/vb/02,05,usb,yes,34,33 2006.201.12:26:27.72/vb/03,04,usb,yes,35,38 2006.201.12:26:27.72/vb/04,05,usb,yes,35,34 2006.201.12:26:27.72/vb/05,04,usb,yes,31,34 2006.201.12:26:27.72/vb/06,04,usb,yes,36,32 2006.201.12:26:27.72/vb/07,04,usb,yes,36,36 2006.201.12:26:27.72/vb/08,04,usb,yes,33,37 2006.201.12:26:27.95/vblo/01,629.99,yes,locked 2006.201.12:26:27.95/vblo/02,634.99,yes,locked 2006.201.12:26:27.95/vblo/03,649.99,yes,locked 2006.201.12:26:27.95/vblo/04,679.99,yes,locked 2006.201.12:26:27.95/vblo/05,709.99,yes,locked 2006.201.12:26:27.95/vblo/06,719.99,yes,locked 2006.201.12:26:27.95/vblo/07,734.99,yes,locked 2006.201.12:26:27.95/vblo/08,744.99,yes,locked 2006.201.12:26:28.10/vabw/8 2006.201.12:26:28.25/vbbw/8 2006.201.12:26:28.34/xfe/off,on,15.0 2006.201.12:26:28.72/ifatt/23,28,28,28 2006.201.12:26:29.05/fmout-gps/S +4.59E-07 2006.201.12:26:29.12:!2006.201.12:28:24 2006.201.12:28:24.00:data_valid=off 2006.201.12:28:24.00:"et 2006.201.12:28:24.00:!+3s 2006.201.12:28:27.02:"tape 2006.201.12:28:27.02:postob 2006.201.12:28:27.11/cable/+6.4760E-03 2006.201.12:28:27.11/wx/21.14,1004.2,100 2006.201.12:28:27.19/fmout-gps/S +4.60E-07 2006.201.12:28:27.19:scan_name=201-1234,jd0607,70 2006.201.12:28:27.19:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.201.12:28:28.14#flagr#flagr/antenna,new-source 2006.201.12:28:28.14:checkk5 2006.201.12:28:28.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:28:28.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:28:29.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:28:29.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:28:30.00/chk_obsdata//k5ts1/T2011226??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.12:28:30.37/chk_obsdata//k5ts2/T2011226??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.12:28:30.74/chk_obsdata//k5ts3/T2011226??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.12:28:31.11/chk_obsdata//k5ts4/T2011226??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.12:28:31.81/k5log//k5ts1_log_newline 2006.201.12:28:32.50/k5log//k5ts2_log_newline 2006.201.12:28:33.18/k5log//k5ts3_log_newline 2006.201.12:28:33.87/k5log//k5ts4_log_newline 2006.201.12:28:33.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:28:33.89:setupk4=1 2006.201.12:28:33.89$setupk4/echo=on 2006.201.12:28:33.89$setupk4/pcalon 2006.201.12:28:33.89$pcalon/"no phase cal control is implemented here 2006.201.12:28:33.89$setupk4/"tpicd=stop 2006.201.12:28:33.89$setupk4/"rec=synch_on 2006.201.12:28:33.89$setupk4/"rec_mode=128 2006.201.12:28:33.89$setupk4/!* 2006.201.12:28:33.89$setupk4/recpk4 2006.201.12:28:33.89$recpk4/recpatch= 2006.201.12:28:33.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:28:33.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:28:33.90$setupk4/vck44 2006.201.12:28:33.90$vck44/valo=1,524.99 2006.201.12:28:33.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.12:28:33.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.12:28:33.90#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:33.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:33.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:33.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:33.90#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:28:33.90#ibcon#first serial, iclass 16, count 0 2006.201.12:28:33.90#ibcon#enter sib2, iclass 16, count 0 2006.201.12:28:33.90#ibcon#flushed, iclass 16, count 0 2006.201.12:28:33.90#ibcon#about to write, iclass 16, count 0 2006.201.12:28:33.90#ibcon#wrote, iclass 16, count 0 2006.201.12:28:33.90#ibcon#about to read 3, iclass 16, count 0 2006.201.12:28:33.93#ibcon#read 3, iclass 16, count 0 2006.201.12:28:33.93#ibcon#about to read 4, iclass 16, count 0 2006.201.12:28:33.93#ibcon#read 4, iclass 16, count 0 2006.201.12:28:33.93#ibcon#about to read 5, iclass 16, count 0 2006.201.12:28:33.93#ibcon#read 5, iclass 16, count 0 2006.201.12:28:33.93#ibcon#about to read 6, iclass 16, count 0 2006.201.12:28:33.93#ibcon#read 6, iclass 16, count 0 2006.201.12:28:33.93#ibcon#end of sib2, iclass 16, count 0 2006.201.12:28:33.93#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:28:33.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:28:33.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:28:33.93#ibcon#*before write, iclass 16, count 0 2006.201.12:28:33.93#ibcon#enter sib2, iclass 16, count 0 2006.201.12:28:33.93#ibcon#flushed, iclass 16, count 0 2006.201.12:28:33.93#ibcon#about to write, iclass 16, count 0 2006.201.12:28:33.93#ibcon#wrote, iclass 16, count 0 2006.201.12:28:33.93#ibcon#about to read 3, iclass 16, count 0 2006.201.12:28:33.98#ibcon#read 3, iclass 16, count 0 2006.201.12:28:33.98#ibcon#about to read 4, iclass 16, count 0 2006.201.12:28:33.98#ibcon#read 4, iclass 16, count 0 2006.201.12:28:33.98#ibcon#about to read 5, iclass 16, count 0 2006.201.12:28:33.98#ibcon#read 5, iclass 16, count 0 2006.201.12:28:33.98#ibcon#about to read 6, iclass 16, count 0 2006.201.12:28:33.98#ibcon#read 6, iclass 16, count 0 2006.201.12:28:33.98#ibcon#end of sib2, iclass 16, count 0 2006.201.12:28:33.98#ibcon#*after write, iclass 16, count 0 2006.201.12:28:33.98#ibcon#*before return 0, iclass 16, count 0 2006.201.12:28:33.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:33.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:33.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:28:33.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:28:33.98$vck44/va=1,8 2006.201.12:28:33.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.12:28:33.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.12:28:33.98#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:33.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:33.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:33.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:33.98#ibcon#enter wrdev, iclass 18, count 2 2006.201.12:28:33.98#ibcon#first serial, iclass 18, count 2 2006.201.12:28:33.98#ibcon#enter sib2, iclass 18, count 2 2006.201.12:28:33.98#ibcon#flushed, iclass 18, count 2 2006.201.12:28:33.98#ibcon#about to write, iclass 18, count 2 2006.201.12:28:33.98#ibcon#wrote, iclass 18, count 2 2006.201.12:28:33.98#ibcon#about to read 3, iclass 18, count 2 2006.201.12:28:34.00#ibcon#read 3, iclass 18, count 2 2006.201.12:28:34.00#ibcon#about to read 4, iclass 18, count 2 2006.201.12:28:34.00#ibcon#read 4, iclass 18, count 2 2006.201.12:28:34.00#ibcon#about to read 5, iclass 18, count 2 2006.201.12:28:34.00#ibcon#read 5, iclass 18, count 2 2006.201.12:28:34.00#ibcon#about to read 6, iclass 18, count 2 2006.201.12:28:34.00#ibcon#read 6, iclass 18, count 2 2006.201.12:28:34.00#ibcon#end of sib2, iclass 18, count 2 2006.201.12:28:34.00#ibcon#*mode == 0, iclass 18, count 2 2006.201.12:28:34.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.12:28:34.00#ibcon#[25=AT01-08\r\n] 2006.201.12:28:34.00#ibcon#*before write, iclass 18, count 2 2006.201.12:28:34.00#ibcon#enter sib2, iclass 18, count 2 2006.201.12:28:34.00#ibcon#flushed, iclass 18, count 2 2006.201.12:28:34.00#ibcon#about to write, iclass 18, count 2 2006.201.12:28:34.00#ibcon#wrote, iclass 18, count 2 2006.201.12:28:34.00#ibcon#about to read 3, iclass 18, count 2 2006.201.12:28:34.03#ibcon#read 3, iclass 18, count 2 2006.201.12:28:34.03#ibcon#about to read 4, iclass 18, count 2 2006.201.12:28:34.03#ibcon#read 4, iclass 18, count 2 2006.201.12:28:34.03#ibcon#about to read 5, iclass 18, count 2 2006.201.12:28:34.03#ibcon#read 5, iclass 18, count 2 2006.201.12:28:34.03#ibcon#about to read 6, iclass 18, count 2 2006.201.12:28:34.03#ibcon#read 6, iclass 18, count 2 2006.201.12:28:34.03#ibcon#end of sib2, iclass 18, count 2 2006.201.12:28:34.03#ibcon#*after write, iclass 18, count 2 2006.201.12:28:34.03#ibcon#*before return 0, iclass 18, count 2 2006.201.12:28:34.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:34.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:34.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.12:28:34.03#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:34.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:34.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:34.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:34.15#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:28:34.15#ibcon#first serial, iclass 18, count 0 2006.201.12:28:34.15#ibcon#enter sib2, iclass 18, count 0 2006.201.12:28:34.15#ibcon#flushed, iclass 18, count 0 2006.201.12:28:34.15#ibcon#about to write, iclass 18, count 0 2006.201.12:28:34.15#ibcon#wrote, iclass 18, count 0 2006.201.12:28:34.15#ibcon#about to read 3, iclass 18, count 0 2006.201.12:28:34.17#ibcon#read 3, iclass 18, count 0 2006.201.12:28:34.17#ibcon#about to read 4, iclass 18, count 0 2006.201.12:28:34.17#ibcon#read 4, iclass 18, count 0 2006.201.12:28:34.17#ibcon#about to read 5, iclass 18, count 0 2006.201.12:28:34.17#ibcon#read 5, iclass 18, count 0 2006.201.12:28:34.17#ibcon#about to read 6, iclass 18, count 0 2006.201.12:28:34.17#ibcon#read 6, iclass 18, count 0 2006.201.12:28:34.17#ibcon#end of sib2, iclass 18, count 0 2006.201.12:28:34.17#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:28:34.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:28:34.17#ibcon#[25=USB\r\n] 2006.201.12:28:34.17#ibcon#*before write, iclass 18, count 0 2006.201.12:28:34.17#ibcon#enter sib2, iclass 18, count 0 2006.201.12:28:34.17#ibcon#flushed, iclass 18, count 0 2006.201.12:28:34.17#ibcon#about to write, iclass 18, count 0 2006.201.12:28:34.17#ibcon#wrote, iclass 18, count 0 2006.201.12:28:34.17#ibcon#about to read 3, iclass 18, count 0 2006.201.12:28:34.20#ibcon#read 3, iclass 18, count 0 2006.201.12:28:34.20#ibcon#about to read 4, iclass 18, count 0 2006.201.12:28:34.20#ibcon#read 4, iclass 18, count 0 2006.201.12:28:34.20#ibcon#about to read 5, iclass 18, count 0 2006.201.12:28:34.20#ibcon#read 5, iclass 18, count 0 2006.201.12:28:34.20#ibcon#about to read 6, iclass 18, count 0 2006.201.12:28:34.20#ibcon#read 6, iclass 18, count 0 2006.201.12:28:34.20#ibcon#end of sib2, iclass 18, count 0 2006.201.12:28:34.20#ibcon#*after write, iclass 18, count 0 2006.201.12:28:34.20#ibcon#*before return 0, iclass 18, count 0 2006.201.12:28:34.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:34.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:34.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:28:34.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:28:34.20$vck44/valo=2,534.99 2006.201.12:28:34.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.12:28:34.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.12:28:34.20#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:34.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:34.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:34.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:34.20#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:28:34.20#ibcon#first serial, iclass 20, count 0 2006.201.12:28:34.20#ibcon#enter sib2, iclass 20, count 0 2006.201.12:28:34.20#ibcon#flushed, iclass 20, count 0 2006.201.12:28:34.20#ibcon#about to write, iclass 20, count 0 2006.201.12:28:34.20#ibcon#wrote, iclass 20, count 0 2006.201.12:28:34.20#ibcon#about to read 3, iclass 20, count 0 2006.201.12:28:34.22#ibcon#read 3, iclass 20, count 0 2006.201.12:28:34.22#ibcon#about to read 4, iclass 20, count 0 2006.201.12:28:34.22#ibcon#read 4, iclass 20, count 0 2006.201.12:28:34.22#ibcon#about to read 5, iclass 20, count 0 2006.201.12:28:34.22#ibcon#read 5, iclass 20, count 0 2006.201.12:28:34.22#ibcon#about to read 6, iclass 20, count 0 2006.201.12:28:34.22#ibcon#read 6, iclass 20, count 0 2006.201.12:28:34.22#ibcon#end of sib2, iclass 20, count 0 2006.201.12:28:34.22#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:28:34.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:28:34.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:28:34.22#ibcon#*before write, iclass 20, count 0 2006.201.12:28:34.22#ibcon#enter sib2, iclass 20, count 0 2006.201.12:28:34.22#ibcon#flushed, iclass 20, count 0 2006.201.12:28:34.22#ibcon#about to write, iclass 20, count 0 2006.201.12:28:34.22#ibcon#wrote, iclass 20, count 0 2006.201.12:28:34.22#ibcon#about to read 3, iclass 20, count 0 2006.201.12:28:34.26#ibcon#read 3, iclass 20, count 0 2006.201.12:28:34.26#ibcon#about to read 4, iclass 20, count 0 2006.201.12:28:34.26#ibcon#read 4, iclass 20, count 0 2006.201.12:28:34.26#ibcon#about to read 5, iclass 20, count 0 2006.201.12:28:34.26#ibcon#read 5, iclass 20, count 0 2006.201.12:28:34.26#ibcon#about to read 6, iclass 20, count 0 2006.201.12:28:34.26#ibcon#read 6, iclass 20, count 0 2006.201.12:28:34.26#ibcon#end of sib2, iclass 20, count 0 2006.201.12:28:34.26#ibcon#*after write, iclass 20, count 0 2006.201.12:28:34.26#ibcon#*before return 0, iclass 20, count 0 2006.201.12:28:34.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:34.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:34.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:28:34.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:28:34.26$vck44/va=2,7 2006.201.12:28:34.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.12:28:34.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.12:28:34.26#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:34.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:34.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:34.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:34.32#ibcon#enter wrdev, iclass 22, count 2 2006.201.12:28:34.32#ibcon#first serial, iclass 22, count 2 2006.201.12:28:34.32#ibcon#enter sib2, iclass 22, count 2 2006.201.12:28:34.32#ibcon#flushed, iclass 22, count 2 2006.201.12:28:34.32#ibcon#about to write, iclass 22, count 2 2006.201.12:28:34.32#ibcon#wrote, iclass 22, count 2 2006.201.12:28:34.32#ibcon#about to read 3, iclass 22, count 2 2006.201.12:28:34.34#ibcon#read 3, iclass 22, count 2 2006.201.12:28:34.34#ibcon#about to read 4, iclass 22, count 2 2006.201.12:28:34.34#ibcon#read 4, iclass 22, count 2 2006.201.12:28:34.34#ibcon#about to read 5, iclass 22, count 2 2006.201.12:28:34.34#ibcon#read 5, iclass 22, count 2 2006.201.12:28:34.34#ibcon#about to read 6, iclass 22, count 2 2006.201.12:28:34.34#ibcon#read 6, iclass 22, count 2 2006.201.12:28:34.34#ibcon#end of sib2, iclass 22, count 2 2006.201.12:28:34.34#ibcon#*mode == 0, iclass 22, count 2 2006.201.12:28:34.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.12:28:34.34#ibcon#[25=AT02-07\r\n] 2006.201.12:28:34.34#ibcon#*before write, iclass 22, count 2 2006.201.12:28:34.34#ibcon#enter sib2, iclass 22, count 2 2006.201.12:28:34.34#ibcon#flushed, iclass 22, count 2 2006.201.12:28:34.34#ibcon#about to write, iclass 22, count 2 2006.201.12:28:34.34#ibcon#wrote, iclass 22, count 2 2006.201.12:28:34.34#ibcon#about to read 3, iclass 22, count 2 2006.201.12:28:34.37#ibcon#read 3, iclass 22, count 2 2006.201.12:28:34.37#ibcon#about to read 4, iclass 22, count 2 2006.201.12:28:34.37#ibcon#read 4, iclass 22, count 2 2006.201.12:28:34.37#ibcon#about to read 5, iclass 22, count 2 2006.201.12:28:34.37#ibcon#read 5, iclass 22, count 2 2006.201.12:28:34.37#ibcon#about to read 6, iclass 22, count 2 2006.201.12:28:34.37#ibcon#read 6, iclass 22, count 2 2006.201.12:28:34.37#ibcon#end of sib2, iclass 22, count 2 2006.201.12:28:34.37#ibcon#*after write, iclass 22, count 2 2006.201.12:28:34.37#ibcon#*before return 0, iclass 22, count 2 2006.201.12:28:34.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:34.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:34.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.12:28:34.37#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:34.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:34.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:34.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:34.49#ibcon#enter wrdev, iclass 22, count 0 2006.201.12:28:34.49#ibcon#first serial, iclass 22, count 0 2006.201.12:28:34.49#ibcon#enter sib2, iclass 22, count 0 2006.201.12:28:34.49#ibcon#flushed, iclass 22, count 0 2006.201.12:28:34.49#ibcon#about to write, iclass 22, count 0 2006.201.12:28:34.49#ibcon#wrote, iclass 22, count 0 2006.201.12:28:34.49#ibcon#about to read 3, iclass 22, count 0 2006.201.12:28:34.51#ibcon#read 3, iclass 22, count 0 2006.201.12:28:34.51#ibcon#about to read 4, iclass 22, count 0 2006.201.12:28:34.51#ibcon#read 4, iclass 22, count 0 2006.201.12:28:34.51#ibcon#about to read 5, iclass 22, count 0 2006.201.12:28:34.51#ibcon#read 5, iclass 22, count 0 2006.201.12:28:34.51#ibcon#about to read 6, iclass 22, count 0 2006.201.12:28:34.51#ibcon#read 6, iclass 22, count 0 2006.201.12:28:34.51#ibcon#end of sib2, iclass 22, count 0 2006.201.12:28:34.51#ibcon#*mode == 0, iclass 22, count 0 2006.201.12:28:34.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.12:28:34.51#ibcon#[25=USB\r\n] 2006.201.12:28:34.51#ibcon#*before write, iclass 22, count 0 2006.201.12:28:34.51#ibcon#enter sib2, iclass 22, count 0 2006.201.12:28:34.51#ibcon#flushed, iclass 22, count 0 2006.201.12:28:34.51#ibcon#about to write, iclass 22, count 0 2006.201.12:28:34.51#ibcon#wrote, iclass 22, count 0 2006.201.12:28:34.51#ibcon#about to read 3, iclass 22, count 0 2006.201.12:28:34.54#ibcon#read 3, iclass 22, count 0 2006.201.12:28:34.54#ibcon#about to read 4, iclass 22, count 0 2006.201.12:28:34.54#ibcon#read 4, iclass 22, count 0 2006.201.12:28:34.54#ibcon#about to read 5, iclass 22, count 0 2006.201.12:28:34.54#ibcon#read 5, iclass 22, count 0 2006.201.12:28:34.54#ibcon#about to read 6, iclass 22, count 0 2006.201.12:28:34.54#ibcon#read 6, iclass 22, count 0 2006.201.12:28:34.54#ibcon#end of sib2, iclass 22, count 0 2006.201.12:28:34.54#ibcon#*after write, iclass 22, count 0 2006.201.12:28:34.54#ibcon#*before return 0, iclass 22, count 0 2006.201.12:28:34.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:34.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:34.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.12:28:34.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.12:28:34.54$vck44/valo=3,564.99 2006.201.12:28:34.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.12:28:34.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.12:28:34.54#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:34.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:28:34.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:28:34.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:28:34.54#ibcon#enter wrdev, iclass 24, count 0 2006.201.12:28:34.54#ibcon#first serial, iclass 24, count 0 2006.201.12:28:34.54#ibcon#enter sib2, iclass 24, count 0 2006.201.12:28:34.54#ibcon#flushed, iclass 24, count 0 2006.201.12:28:34.54#ibcon#about to write, iclass 24, count 0 2006.201.12:28:34.54#ibcon#wrote, iclass 24, count 0 2006.201.12:28:34.54#ibcon#about to read 3, iclass 24, count 0 2006.201.12:28:34.56#ibcon#read 3, iclass 24, count 0 2006.201.12:28:34.56#ibcon#about to read 4, iclass 24, count 0 2006.201.12:28:34.56#ibcon#read 4, iclass 24, count 0 2006.201.12:28:34.56#ibcon#about to read 5, iclass 24, count 0 2006.201.12:28:34.56#ibcon#read 5, iclass 24, count 0 2006.201.12:28:34.56#ibcon#about to read 6, iclass 24, count 0 2006.201.12:28:34.56#ibcon#read 6, iclass 24, count 0 2006.201.12:28:34.56#ibcon#end of sib2, iclass 24, count 0 2006.201.12:28:34.56#ibcon#*mode == 0, iclass 24, count 0 2006.201.12:28:34.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.12:28:34.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:28:34.56#ibcon#*before write, iclass 24, count 0 2006.201.12:28:34.56#ibcon#enter sib2, iclass 24, count 0 2006.201.12:28:34.56#ibcon#flushed, iclass 24, count 0 2006.201.12:28:34.56#ibcon#about to write, iclass 24, count 0 2006.201.12:28:34.56#ibcon#wrote, iclass 24, count 0 2006.201.12:28:34.56#ibcon#about to read 3, iclass 24, count 0 2006.201.12:28:34.61#ibcon#read 3, iclass 24, count 0 2006.201.12:28:34.61#ibcon#about to read 4, iclass 24, count 0 2006.201.12:28:34.61#ibcon#read 4, iclass 24, count 0 2006.201.12:28:34.61#ibcon#about to read 5, iclass 24, count 0 2006.201.12:28:34.61#ibcon#read 5, iclass 24, count 0 2006.201.12:28:34.61#ibcon#about to read 6, iclass 24, count 0 2006.201.12:28:34.61#ibcon#read 6, iclass 24, count 0 2006.201.12:28:34.61#ibcon#end of sib2, iclass 24, count 0 2006.201.12:28:34.61#ibcon#*after write, iclass 24, count 0 2006.201.12:28:34.61#ibcon#*before return 0, iclass 24, count 0 2006.201.12:28:34.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:28:34.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:28:34.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.12:28:34.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.12:28:34.61$vck44/va=3,8 2006.201.12:28:34.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.12:28:34.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.12:28:34.61#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:34.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:28:34.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:28:34.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:28:34.66#ibcon#enter wrdev, iclass 26, count 2 2006.201.12:28:34.66#ibcon#first serial, iclass 26, count 2 2006.201.12:28:34.66#ibcon#enter sib2, iclass 26, count 2 2006.201.12:28:34.66#ibcon#flushed, iclass 26, count 2 2006.201.12:28:34.66#ibcon#about to write, iclass 26, count 2 2006.201.12:28:34.66#ibcon#wrote, iclass 26, count 2 2006.201.12:28:34.66#ibcon#about to read 3, iclass 26, count 2 2006.201.12:28:34.68#ibcon#read 3, iclass 26, count 2 2006.201.12:28:34.68#ibcon#about to read 4, iclass 26, count 2 2006.201.12:28:34.68#ibcon#read 4, iclass 26, count 2 2006.201.12:28:34.68#ibcon#about to read 5, iclass 26, count 2 2006.201.12:28:34.68#ibcon#read 5, iclass 26, count 2 2006.201.12:28:34.68#ibcon#about to read 6, iclass 26, count 2 2006.201.12:28:34.68#ibcon#read 6, iclass 26, count 2 2006.201.12:28:34.68#ibcon#end of sib2, iclass 26, count 2 2006.201.12:28:34.68#ibcon#*mode == 0, iclass 26, count 2 2006.201.12:28:34.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.12:28:34.68#ibcon#[25=AT03-08\r\n] 2006.201.12:28:34.68#ibcon#*before write, iclass 26, count 2 2006.201.12:28:34.68#ibcon#enter sib2, iclass 26, count 2 2006.201.12:28:34.68#ibcon#flushed, iclass 26, count 2 2006.201.12:28:34.68#ibcon#about to write, iclass 26, count 2 2006.201.12:28:34.68#ibcon#wrote, iclass 26, count 2 2006.201.12:28:34.68#ibcon#about to read 3, iclass 26, count 2 2006.201.12:28:34.71#ibcon#read 3, iclass 26, count 2 2006.201.12:28:34.71#ibcon#about to read 4, iclass 26, count 2 2006.201.12:28:34.71#ibcon#read 4, iclass 26, count 2 2006.201.12:28:34.71#ibcon#about to read 5, iclass 26, count 2 2006.201.12:28:34.71#ibcon#read 5, iclass 26, count 2 2006.201.12:28:34.71#ibcon#about to read 6, iclass 26, count 2 2006.201.12:28:34.71#ibcon#read 6, iclass 26, count 2 2006.201.12:28:34.71#ibcon#end of sib2, iclass 26, count 2 2006.201.12:28:34.71#ibcon#*after write, iclass 26, count 2 2006.201.12:28:34.71#ibcon#*before return 0, iclass 26, count 2 2006.201.12:28:34.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:28:34.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:28:34.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.12:28:34.71#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:34.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:28:34.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:28:34.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:28:34.83#ibcon#enter wrdev, iclass 26, count 0 2006.201.12:28:34.83#ibcon#first serial, iclass 26, count 0 2006.201.12:28:34.83#ibcon#enter sib2, iclass 26, count 0 2006.201.12:28:34.83#ibcon#flushed, iclass 26, count 0 2006.201.12:28:34.83#ibcon#about to write, iclass 26, count 0 2006.201.12:28:34.83#ibcon#wrote, iclass 26, count 0 2006.201.12:28:34.83#ibcon#about to read 3, iclass 26, count 0 2006.201.12:28:34.85#ibcon#read 3, iclass 26, count 0 2006.201.12:28:34.85#ibcon#about to read 4, iclass 26, count 0 2006.201.12:28:34.85#ibcon#read 4, iclass 26, count 0 2006.201.12:28:34.85#ibcon#about to read 5, iclass 26, count 0 2006.201.12:28:34.85#ibcon#read 5, iclass 26, count 0 2006.201.12:28:34.85#ibcon#about to read 6, iclass 26, count 0 2006.201.12:28:34.85#ibcon#read 6, iclass 26, count 0 2006.201.12:28:34.85#ibcon#end of sib2, iclass 26, count 0 2006.201.12:28:34.85#ibcon#*mode == 0, iclass 26, count 0 2006.201.12:28:34.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.12:28:34.85#ibcon#[25=USB\r\n] 2006.201.12:28:34.85#ibcon#*before write, iclass 26, count 0 2006.201.12:28:34.85#ibcon#enter sib2, iclass 26, count 0 2006.201.12:28:34.85#ibcon#flushed, iclass 26, count 0 2006.201.12:28:34.85#ibcon#about to write, iclass 26, count 0 2006.201.12:28:34.85#ibcon#wrote, iclass 26, count 0 2006.201.12:28:34.85#ibcon#about to read 3, iclass 26, count 0 2006.201.12:28:34.88#ibcon#read 3, iclass 26, count 0 2006.201.12:28:34.88#ibcon#about to read 4, iclass 26, count 0 2006.201.12:28:34.88#ibcon#read 4, iclass 26, count 0 2006.201.12:28:34.88#ibcon#about to read 5, iclass 26, count 0 2006.201.12:28:34.88#ibcon#read 5, iclass 26, count 0 2006.201.12:28:34.88#ibcon#about to read 6, iclass 26, count 0 2006.201.12:28:34.88#ibcon#read 6, iclass 26, count 0 2006.201.12:28:34.88#ibcon#end of sib2, iclass 26, count 0 2006.201.12:28:34.88#ibcon#*after write, iclass 26, count 0 2006.201.12:28:34.88#ibcon#*before return 0, iclass 26, count 0 2006.201.12:28:34.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:28:34.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:28:34.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.12:28:34.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.12:28:34.88$vck44/valo=4,624.99 2006.201.12:28:34.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.12:28:34.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.12:28:34.88#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:34.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:28:34.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:28:34.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:28:34.88#ibcon#enter wrdev, iclass 28, count 0 2006.201.12:28:34.88#ibcon#first serial, iclass 28, count 0 2006.201.12:28:34.88#ibcon#enter sib2, iclass 28, count 0 2006.201.12:28:34.88#ibcon#flushed, iclass 28, count 0 2006.201.12:28:34.88#ibcon#about to write, iclass 28, count 0 2006.201.12:28:34.88#ibcon#wrote, iclass 28, count 0 2006.201.12:28:34.88#ibcon#about to read 3, iclass 28, count 0 2006.201.12:28:34.90#ibcon#read 3, iclass 28, count 0 2006.201.12:28:34.90#ibcon#about to read 4, iclass 28, count 0 2006.201.12:28:34.90#ibcon#read 4, iclass 28, count 0 2006.201.12:28:34.90#ibcon#about to read 5, iclass 28, count 0 2006.201.12:28:34.90#ibcon#read 5, iclass 28, count 0 2006.201.12:28:34.90#ibcon#about to read 6, iclass 28, count 0 2006.201.12:28:34.90#ibcon#read 6, iclass 28, count 0 2006.201.12:28:34.90#ibcon#end of sib2, iclass 28, count 0 2006.201.12:28:34.90#ibcon#*mode == 0, iclass 28, count 0 2006.201.12:28:34.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.12:28:34.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:28:34.90#ibcon#*before write, iclass 28, count 0 2006.201.12:28:34.90#ibcon#enter sib2, iclass 28, count 0 2006.201.12:28:34.90#ibcon#flushed, iclass 28, count 0 2006.201.12:28:34.90#ibcon#about to write, iclass 28, count 0 2006.201.12:28:34.90#ibcon#wrote, iclass 28, count 0 2006.201.12:28:34.90#ibcon#about to read 3, iclass 28, count 0 2006.201.12:28:34.95#ibcon#read 3, iclass 28, count 0 2006.201.12:28:34.95#ibcon#about to read 4, iclass 28, count 0 2006.201.12:28:34.95#ibcon#read 4, iclass 28, count 0 2006.201.12:28:34.95#ibcon#about to read 5, iclass 28, count 0 2006.201.12:28:34.95#ibcon#read 5, iclass 28, count 0 2006.201.12:28:34.95#ibcon#about to read 6, iclass 28, count 0 2006.201.12:28:34.95#ibcon#read 6, iclass 28, count 0 2006.201.12:28:34.95#ibcon#end of sib2, iclass 28, count 0 2006.201.12:28:34.95#ibcon#*after write, iclass 28, count 0 2006.201.12:28:34.95#ibcon#*before return 0, iclass 28, count 0 2006.201.12:28:34.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:28:34.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:28:34.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.12:28:34.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.12:28:34.95$vck44/va=4,7 2006.201.12:28:34.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.12:28:34.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.12:28:34.95#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:34.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:28:35.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:28:35.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:28:35.00#ibcon#enter wrdev, iclass 30, count 2 2006.201.12:28:35.00#ibcon#first serial, iclass 30, count 2 2006.201.12:28:35.00#ibcon#enter sib2, iclass 30, count 2 2006.201.12:28:35.00#ibcon#flushed, iclass 30, count 2 2006.201.12:28:35.00#ibcon#about to write, iclass 30, count 2 2006.201.12:28:35.00#ibcon#wrote, iclass 30, count 2 2006.201.12:28:35.00#ibcon#about to read 3, iclass 30, count 2 2006.201.12:28:35.02#ibcon#read 3, iclass 30, count 2 2006.201.12:28:35.02#ibcon#about to read 4, iclass 30, count 2 2006.201.12:28:35.02#ibcon#read 4, iclass 30, count 2 2006.201.12:28:35.02#ibcon#about to read 5, iclass 30, count 2 2006.201.12:28:35.02#ibcon#read 5, iclass 30, count 2 2006.201.12:28:35.02#ibcon#about to read 6, iclass 30, count 2 2006.201.12:28:35.02#ibcon#read 6, iclass 30, count 2 2006.201.12:28:35.02#ibcon#end of sib2, iclass 30, count 2 2006.201.12:28:35.02#ibcon#*mode == 0, iclass 30, count 2 2006.201.12:28:35.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.12:28:35.02#ibcon#[25=AT04-07\r\n] 2006.201.12:28:35.02#ibcon#*before write, iclass 30, count 2 2006.201.12:28:35.02#ibcon#enter sib2, iclass 30, count 2 2006.201.12:28:35.02#ibcon#flushed, iclass 30, count 2 2006.201.12:28:35.02#ibcon#about to write, iclass 30, count 2 2006.201.12:28:35.02#ibcon#wrote, iclass 30, count 2 2006.201.12:28:35.02#ibcon#about to read 3, iclass 30, count 2 2006.201.12:28:35.05#ibcon#read 3, iclass 30, count 2 2006.201.12:28:35.05#ibcon#about to read 4, iclass 30, count 2 2006.201.12:28:35.05#ibcon#read 4, iclass 30, count 2 2006.201.12:28:35.05#ibcon#about to read 5, iclass 30, count 2 2006.201.12:28:35.05#ibcon#read 5, iclass 30, count 2 2006.201.12:28:35.05#ibcon#about to read 6, iclass 30, count 2 2006.201.12:28:35.05#ibcon#read 6, iclass 30, count 2 2006.201.12:28:35.05#ibcon#end of sib2, iclass 30, count 2 2006.201.12:28:35.05#ibcon#*after write, iclass 30, count 2 2006.201.12:28:35.05#ibcon#*before return 0, iclass 30, count 2 2006.201.12:28:35.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:28:35.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:28:35.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.12:28:35.05#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:35.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:28:35.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:28:35.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:28:35.17#ibcon#enter wrdev, iclass 30, count 0 2006.201.12:28:35.17#ibcon#first serial, iclass 30, count 0 2006.201.12:28:35.17#ibcon#enter sib2, iclass 30, count 0 2006.201.12:28:35.17#ibcon#flushed, iclass 30, count 0 2006.201.12:28:35.17#ibcon#about to write, iclass 30, count 0 2006.201.12:28:35.17#ibcon#wrote, iclass 30, count 0 2006.201.12:28:35.17#ibcon#about to read 3, iclass 30, count 0 2006.201.12:28:35.19#ibcon#read 3, iclass 30, count 0 2006.201.12:28:35.19#ibcon#about to read 4, iclass 30, count 0 2006.201.12:28:35.19#ibcon#read 4, iclass 30, count 0 2006.201.12:28:35.19#ibcon#about to read 5, iclass 30, count 0 2006.201.12:28:35.19#ibcon#read 5, iclass 30, count 0 2006.201.12:28:35.19#ibcon#about to read 6, iclass 30, count 0 2006.201.12:28:35.19#ibcon#read 6, iclass 30, count 0 2006.201.12:28:35.19#ibcon#end of sib2, iclass 30, count 0 2006.201.12:28:35.19#ibcon#*mode == 0, iclass 30, count 0 2006.201.12:28:35.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.12:28:35.19#ibcon#[25=USB\r\n] 2006.201.12:28:35.19#ibcon#*before write, iclass 30, count 0 2006.201.12:28:35.19#ibcon#enter sib2, iclass 30, count 0 2006.201.12:28:35.19#ibcon#flushed, iclass 30, count 0 2006.201.12:28:35.19#ibcon#about to write, iclass 30, count 0 2006.201.12:28:35.19#ibcon#wrote, iclass 30, count 0 2006.201.12:28:35.19#ibcon#about to read 3, iclass 30, count 0 2006.201.12:28:35.22#ibcon#read 3, iclass 30, count 0 2006.201.12:28:35.22#ibcon#about to read 4, iclass 30, count 0 2006.201.12:28:35.22#ibcon#read 4, iclass 30, count 0 2006.201.12:28:35.22#ibcon#about to read 5, iclass 30, count 0 2006.201.12:28:35.22#ibcon#read 5, iclass 30, count 0 2006.201.12:28:35.22#ibcon#about to read 6, iclass 30, count 0 2006.201.12:28:35.22#ibcon#read 6, iclass 30, count 0 2006.201.12:28:35.22#ibcon#end of sib2, iclass 30, count 0 2006.201.12:28:35.22#ibcon#*after write, iclass 30, count 0 2006.201.12:28:35.22#ibcon#*before return 0, iclass 30, count 0 2006.201.12:28:35.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:28:35.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:28:35.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.12:28:35.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.12:28:35.22$vck44/valo=5,734.99 2006.201.12:28:35.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.12:28:35.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.12:28:35.22#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:35.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:35.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:35.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:35.22#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:28:35.22#ibcon#first serial, iclass 32, count 0 2006.201.12:28:35.22#ibcon#enter sib2, iclass 32, count 0 2006.201.12:28:35.22#ibcon#flushed, iclass 32, count 0 2006.201.12:28:35.22#ibcon#about to write, iclass 32, count 0 2006.201.12:28:35.22#ibcon#wrote, iclass 32, count 0 2006.201.12:28:35.22#ibcon#about to read 3, iclass 32, count 0 2006.201.12:28:35.24#ibcon#read 3, iclass 32, count 0 2006.201.12:28:35.24#ibcon#about to read 4, iclass 32, count 0 2006.201.12:28:35.24#ibcon#read 4, iclass 32, count 0 2006.201.12:28:35.24#ibcon#about to read 5, iclass 32, count 0 2006.201.12:28:35.24#ibcon#read 5, iclass 32, count 0 2006.201.12:28:35.24#ibcon#about to read 6, iclass 32, count 0 2006.201.12:28:35.24#ibcon#read 6, iclass 32, count 0 2006.201.12:28:35.24#ibcon#end of sib2, iclass 32, count 0 2006.201.12:28:35.24#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:28:35.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:28:35.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:28:35.24#ibcon#*before write, iclass 32, count 0 2006.201.12:28:35.24#ibcon#enter sib2, iclass 32, count 0 2006.201.12:28:35.24#ibcon#flushed, iclass 32, count 0 2006.201.12:28:35.24#ibcon#about to write, iclass 32, count 0 2006.201.12:28:35.24#ibcon#wrote, iclass 32, count 0 2006.201.12:28:35.24#ibcon#about to read 3, iclass 32, count 0 2006.201.12:28:35.28#ibcon#read 3, iclass 32, count 0 2006.201.12:28:35.28#ibcon#about to read 4, iclass 32, count 0 2006.201.12:28:35.28#ibcon#read 4, iclass 32, count 0 2006.201.12:28:35.28#ibcon#about to read 5, iclass 32, count 0 2006.201.12:28:35.28#ibcon#read 5, iclass 32, count 0 2006.201.12:28:35.28#ibcon#about to read 6, iclass 32, count 0 2006.201.12:28:35.28#ibcon#read 6, iclass 32, count 0 2006.201.12:28:35.28#ibcon#end of sib2, iclass 32, count 0 2006.201.12:28:35.28#ibcon#*after write, iclass 32, count 0 2006.201.12:28:35.28#ibcon#*before return 0, iclass 32, count 0 2006.201.12:28:35.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:35.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:35.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:28:35.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:28:35.28$vck44/va=5,4 2006.201.12:28:35.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.12:28:35.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.12:28:35.28#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:35.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:35.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:35.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:35.34#ibcon#enter wrdev, iclass 34, count 2 2006.201.12:28:35.34#ibcon#first serial, iclass 34, count 2 2006.201.12:28:35.34#ibcon#enter sib2, iclass 34, count 2 2006.201.12:28:35.34#ibcon#flushed, iclass 34, count 2 2006.201.12:28:35.34#ibcon#about to write, iclass 34, count 2 2006.201.12:28:35.34#ibcon#wrote, iclass 34, count 2 2006.201.12:28:35.34#ibcon#about to read 3, iclass 34, count 2 2006.201.12:28:35.36#ibcon#read 3, iclass 34, count 2 2006.201.12:28:35.36#ibcon#about to read 4, iclass 34, count 2 2006.201.12:28:35.36#ibcon#read 4, iclass 34, count 2 2006.201.12:28:35.36#ibcon#about to read 5, iclass 34, count 2 2006.201.12:28:35.36#ibcon#read 5, iclass 34, count 2 2006.201.12:28:35.36#ibcon#about to read 6, iclass 34, count 2 2006.201.12:28:35.36#ibcon#read 6, iclass 34, count 2 2006.201.12:28:35.36#ibcon#end of sib2, iclass 34, count 2 2006.201.12:28:35.36#ibcon#*mode == 0, iclass 34, count 2 2006.201.12:28:35.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.12:28:35.36#ibcon#[25=AT05-04\r\n] 2006.201.12:28:35.36#ibcon#*before write, iclass 34, count 2 2006.201.12:28:35.36#ibcon#enter sib2, iclass 34, count 2 2006.201.12:28:35.36#ibcon#flushed, iclass 34, count 2 2006.201.12:28:35.36#ibcon#about to write, iclass 34, count 2 2006.201.12:28:35.36#ibcon#wrote, iclass 34, count 2 2006.201.12:28:35.36#ibcon#about to read 3, iclass 34, count 2 2006.201.12:28:35.39#ibcon#read 3, iclass 34, count 2 2006.201.12:28:35.39#ibcon#about to read 4, iclass 34, count 2 2006.201.12:28:35.39#ibcon#read 4, iclass 34, count 2 2006.201.12:28:35.39#ibcon#about to read 5, iclass 34, count 2 2006.201.12:28:35.39#ibcon#read 5, iclass 34, count 2 2006.201.12:28:35.39#ibcon#about to read 6, iclass 34, count 2 2006.201.12:28:35.39#ibcon#read 6, iclass 34, count 2 2006.201.12:28:35.39#ibcon#end of sib2, iclass 34, count 2 2006.201.12:28:35.39#ibcon#*after write, iclass 34, count 2 2006.201.12:28:35.39#ibcon#*before return 0, iclass 34, count 2 2006.201.12:28:35.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:35.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:35.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.12:28:35.39#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:35.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:35.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:35.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:35.51#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:28:35.51#ibcon#first serial, iclass 34, count 0 2006.201.12:28:35.51#ibcon#enter sib2, iclass 34, count 0 2006.201.12:28:35.51#ibcon#flushed, iclass 34, count 0 2006.201.12:28:35.51#ibcon#about to write, iclass 34, count 0 2006.201.12:28:35.51#ibcon#wrote, iclass 34, count 0 2006.201.12:28:35.51#ibcon#about to read 3, iclass 34, count 0 2006.201.12:28:35.53#ibcon#read 3, iclass 34, count 0 2006.201.12:28:35.53#ibcon#about to read 4, iclass 34, count 0 2006.201.12:28:35.53#ibcon#read 4, iclass 34, count 0 2006.201.12:28:35.53#ibcon#about to read 5, iclass 34, count 0 2006.201.12:28:35.53#ibcon#read 5, iclass 34, count 0 2006.201.12:28:35.53#ibcon#about to read 6, iclass 34, count 0 2006.201.12:28:35.53#ibcon#read 6, iclass 34, count 0 2006.201.12:28:35.53#ibcon#end of sib2, iclass 34, count 0 2006.201.12:28:35.53#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:28:35.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:28:35.53#ibcon#[25=USB\r\n] 2006.201.12:28:35.53#ibcon#*before write, iclass 34, count 0 2006.201.12:28:35.53#ibcon#enter sib2, iclass 34, count 0 2006.201.12:28:35.53#ibcon#flushed, iclass 34, count 0 2006.201.12:28:35.53#ibcon#about to write, iclass 34, count 0 2006.201.12:28:35.53#ibcon#wrote, iclass 34, count 0 2006.201.12:28:35.53#ibcon#about to read 3, iclass 34, count 0 2006.201.12:28:35.56#ibcon#read 3, iclass 34, count 0 2006.201.12:28:35.56#ibcon#about to read 4, iclass 34, count 0 2006.201.12:28:35.56#ibcon#read 4, iclass 34, count 0 2006.201.12:28:35.56#ibcon#about to read 5, iclass 34, count 0 2006.201.12:28:35.56#ibcon#read 5, iclass 34, count 0 2006.201.12:28:35.56#ibcon#about to read 6, iclass 34, count 0 2006.201.12:28:35.56#ibcon#read 6, iclass 34, count 0 2006.201.12:28:35.56#ibcon#end of sib2, iclass 34, count 0 2006.201.12:28:35.56#ibcon#*after write, iclass 34, count 0 2006.201.12:28:35.56#ibcon#*before return 0, iclass 34, count 0 2006.201.12:28:35.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:35.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:35.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:28:35.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:28:35.56$vck44/valo=6,814.99 2006.201.12:28:35.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.12:28:35.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.12:28:35.56#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:35.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:35.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:35.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:35.56#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:28:35.56#ibcon#first serial, iclass 36, count 0 2006.201.12:28:35.56#ibcon#enter sib2, iclass 36, count 0 2006.201.12:28:35.56#ibcon#flushed, iclass 36, count 0 2006.201.12:28:35.56#ibcon#about to write, iclass 36, count 0 2006.201.12:28:35.56#ibcon#wrote, iclass 36, count 0 2006.201.12:28:35.56#ibcon#about to read 3, iclass 36, count 0 2006.201.12:28:35.58#ibcon#read 3, iclass 36, count 0 2006.201.12:28:35.58#ibcon#about to read 4, iclass 36, count 0 2006.201.12:28:35.58#ibcon#read 4, iclass 36, count 0 2006.201.12:28:35.58#ibcon#about to read 5, iclass 36, count 0 2006.201.12:28:35.58#ibcon#read 5, iclass 36, count 0 2006.201.12:28:35.58#ibcon#about to read 6, iclass 36, count 0 2006.201.12:28:35.58#ibcon#read 6, iclass 36, count 0 2006.201.12:28:35.58#ibcon#end of sib2, iclass 36, count 0 2006.201.12:28:35.58#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:28:35.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:28:35.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:28:35.58#ibcon#*before write, iclass 36, count 0 2006.201.12:28:35.58#ibcon#enter sib2, iclass 36, count 0 2006.201.12:28:35.58#ibcon#flushed, iclass 36, count 0 2006.201.12:28:35.58#ibcon#about to write, iclass 36, count 0 2006.201.12:28:35.58#ibcon#wrote, iclass 36, count 0 2006.201.12:28:35.58#ibcon#about to read 3, iclass 36, count 0 2006.201.12:28:35.62#ibcon#read 3, iclass 36, count 0 2006.201.12:28:35.62#ibcon#about to read 4, iclass 36, count 0 2006.201.12:28:35.62#ibcon#read 4, iclass 36, count 0 2006.201.12:28:35.62#ibcon#about to read 5, iclass 36, count 0 2006.201.12:28:35.62#ibcon#read 5, iclass 36, count 0 2006.201.12:28:35.62#ibcon#about to read 6, iclass 36, count 0 2006.201.12:28:35.62#ibcon#read 6, iclass 36, count 0 2006.201.12:28:35.62#ibcon#end of sib2, iclass 36, count 0 2006.201.12:28:35.62#ibcon#*after write, iclass 36, count 0 2006.201.12:28:35.62#ibcon#*before return 0, iclass 36, count 0 2006.201.12:28:35.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:35.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:35.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:28:35.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:28:35.62$vck44/va=6,5 2006.201.12:28:35.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.12:28:35.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.12:28:35.62#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:35.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:35.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:35.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:35.68#ibcon#enter wrdev, iclass 38, count 2 2006.201.12:28:35.68#ibcon#first serial, iclass 38, count 2 2006.201.12:28:35.68#ibcon#enter sib2, iclass 38, count 2 2006.201.12:28:35.68#ibcon#flushed, iclass 38, count 2 2006.201.12:28:35.68#ibcon#about to write, iclass 38, count 2 2006.201.12:28:35.68#ibcon#wrote, iclass 38, count 2 2006.201.12:28:35.68#ibcon#about to read 3, iclass 38, count 2 2006.201.12:28:35.70#ibcon#read 3, iclass 38, count 2 2006.201.12:28:35.70#ibcon#about to read 4, iclass 38, count 2 2006.201.12:28:35.70#ibcon#read 4, iclass 38, count 2 2006.201.12:28:35.70#ibcon#about to read 5, iclass 38, count 2 2006.201.12:28:35.70#ibcon#read 5, iclass 38, count 2 2006.201.12:28:35.70#ibcon#about to read 6, iclass 38, count 2 2006.201.12:28:35.70#ibcon#read 6, iclass 38, count 2 2006.201.12:28:35.70#ibcon#end of sib2, iclass 38, count 2 2006.201.12:28:35.70#ibcon#*mode == 0, iclass 38, count 2 2006.201.12:28:35.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.12:28:35.70#ibcon#[25=AT06-05\r\n] 2006.201.12:28:35.70#ibcon#*before write, iclass 38, count 2 2006.201.12:28:35.70#ibcon#enter sib2, iclass 38, count 2 2006.201.12:28:35.70#ibcon#flushed, iclass 38, count 2 2006.201.12:28:35.70#ibcon#about to write, iclass 38, count 2 2006.201.12:28:35.70#ibcon#wrote, iclass 38, count 2 2006.201.12:28:35.70#ibcon#about to read 3, iclass 38, count 2 2006.201.12:28:35.73#ibcon#read 3, iclass 38, count 2 2006.201.12:28:35.73#ibcon#about to read 4, iclass 38, count 2 2006.201.12:28:35.73#ibcon#read 4, iclass 38, count 2 2006.201.12:28:35.73#ibcon#about to read 5, iclass 38, count 2 2006.201.12:28:35.73#ibcon#read 5, iclass 38, count 2 2006.201.12:28:35.73#ibcon#about to read 6, iclass 38, count 2 2006.201.12:28:35.73#ibcon#read 6, iclass 38, count 2 2006.201.12:28:35.73#ibcon#end of sib2, iclass 38, count 2 2006.201.12:28:35.73#ibcon#*after write, iclass 38, count 2 2006.201.12:28:35.73#ibcon#*before return 0, iclass 38, count 2 2006.201.12:28:35.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:35.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:35.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.12:28:35.73#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:35.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:35.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:35.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:35.85#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:28:35.85#ibcon#first serial, iclass 38, count 0 2006.201.12:28:35.85#ibcon#enter sib2, iclass 38, count 0 2006.201.12:28:35.85#ibcon#flushed, iclass 38, count 0 2006.201.12:28:35.85#ibcon#about to write, iclass 38, count 0 2006.201.12:28:35.85#ibcon#wrote, iclass 38, count 0 2006.201.12:28:35.85#ibcon#about to read 3, iclass 38, count 0 2006.201.12:28:35.87#ibcon#read 3, iclass 38, count 0 2006.201.12:28:35.87#ibcon#about to read 4, iclass 38, count 0 2006.201.12:28:35.87#ibcon#read 4, iclass 38, count 0 2006.201.12:28:35.87#ibcon#about to read 5, iclass 38, count 0 2006.201.12:28:35.87#ibcon#read 5, iclass 38, count 0 2006.201.12:28:35.87#ibcon#about to read 6, iclass 38, count 0 2006.201.12:28:35.87#ibcon#read 6, iclass 38, count 0 2006.201.12:28:35.87#ibcon#end of sib2, iclass 38, count 0 2006.201.12:28:35.87#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:28:35.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:28:35.87#ibcon#[25=USB\r\n] 2006.201.12:28:35.87#ibcon#*before write, iclass 38, count 0 2006.201.12:28:35.87#ibcon#enter sib2, iclass 38, count 0 2006.201.12:28:35.87#ibcon#flushed, iclass 38, count 0 2006.201.12:28:35.87#ibcon#about to write, iclass 38, count 0 2006.201.12:28:35.87#ibcon#wrote, iclass 38, count 0 2006.201.12:28:35.87#ibcon#about to read 3, iclass 38, count 0 2006.201.12:28:35.90#ibcon#read 3, iclass 38, count 0 2006.201.12:28:35.90#ibcon#about to read 4, iclass 38, count 0 2006.201.12:28:35.90#ibcon#read 4, iclass 38, count 0 2006.201.12:28:35.90#ibcon#about to read 5, iclass 38, count 0 2006.201.12:28:35.90#ibcon#read 5, iclass 38, count 0 2006.201.12:28:35.90#ibcon#about to read 6, iclass 38, count 0 2006.201.12:28:35.90#ibcon#read 6, iclass 38, count 0 2006.201.12:28:35.90#ibcon#end of sib2, iclass 38, count 0 2006.201.12:28:35.90#ibcon#*after write, iclass 38, count 0 2006.201.12:28:35.90#ibcon#*before return 0, iclass 38, count 0 2006.201.12:28:35.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:35.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:35.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:28:35.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:28:35.90$vck44/valo=7,864.99 2006.201.12:28:35.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.12:28:35.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.12:28:35.90#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:35.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:35.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:35.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:35.90#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:28:35.90#ibcon#first serial, iclass 40, count 0 2006.201.12:28:35.90#ibcon#enter sib2, iclass 40, count 0 2006.201.12:28:35.90#ibcon#flushed, iclass 40, count 0 2006.201.12:28:35.90#ibcon#about to write, iclass 40, count 0 2006.201.12:28:35.90#ibcon#wrote, iclass 40, count 0 2006.201.12:28:35.90#ibcon#about to read 3, iclass 40, count 0 2006.201.12:28:35.92#ibcon#read 3, iclass 40, count 0 2006.201.12:28:35.92#ibcon#about to read 4, iclass 40, count 0 2006.201.12:28:35.92#ibcon#read 4, iclass 40, count 0 2006.201.12:28:35.92#ibcon#about to read 5, iclass 40, count 0 2006.201.12:28:35.92#ibcon#read 5, iclass 40, count 0 2006.201.12:28:35.92#ibcon#about to read 6, iclass 40, count 0 2006.201.12:28:35.92#ibcon#read 6, iclass 40, count 0 2006.201.12:28:35.92#ibcon#end of sib2, iclass 40, count 0 2006.201.12:28:35.92#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:28:35.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:28:35.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:28:35.92#ibcon#*before write, iclass 40, count 0 2006.201.12:28:35.92#ibcon#enter sib2, iclass 40, count 0 2006.201.12:28:35.92#ibcon#flushed, iclass 40, count 0 2006.201.12:28:35.92#ibcon#about to write, iclass 40, count 0 2006.201.12:28:35.92#ibcon#wrote, iclass 40, count 0 2006.201.12:28:35.92#ibcon#about to read 3, iclass 40, count 0 2006.201.12:28:35.97#ibcon#read 3, iclass 40, count 0 2006.201.12:28:35.97#ibcon#about to read 4, iclass 40, count 0 2006.201.12:28:35.97#ibcon#read 4, iclass 40, count 0 2006.201.12:28:35.97#ibcon#about to read 5, iclass 40, count 0 2006.201.12:28:35.97#ibcon#read 5, iclass 40, count 0 2006.201.12:28:35.97#ibcon#about to read 6, iclass 40, count 0 2006.201.12:28:35.97#ibcon#read 6, iclass 40, count 0 2006.201.12:28:35.97#ibcon#end of sib2, iclass 40, count 0 2006.201.12:28:35.97#ibcon#*after write, iclass 40, count 0 2006.201.12:28:35.97#ibcon#*before return 0, iclass 40, count 0 2006.201.12:28:35.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:35.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:35.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:28:35.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:28:35.97$vck44/va=7,5 2006.201.12:28:35.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.12:28:35.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.12:28:35.97#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:35.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:36.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:36.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:36.02#ibcon#enter wrdev, iclass 4, count 2 2006.201.12:28:36.02#ibcon#first serial, iclass 4, count 2 2006.201.12:28:36.02#ibcon#enter sib2, iclass 4, count 2 2006.201.12:28:36.02#ibcon#flushed, iclass 4, count 2 2006.201.12:28:36.02#ibcon#about to write, iclass 4, count 2 2006.201.12:28:36.02#ibcon#wrote, iclass 4, count 2 2006.201.12:28:36.02#ibcon#about to read 3, iclass 4, count 2 2006.201.12:28:36.04#ibcon#read 3, iclass 4, count 2 2006.201.12:28:36.04#ibcon#about to read 4, iclass 4, count 2 2006.201.12:28:36.04#ibcon#read 4, iclass 4, count 2 2006.201.12:28:36.04#ibcon#about to read 5, iclass 4, count 2 2006.201.12:28:36.04#ibcon#read 5, iclass 4, count 2 2006.201.12:28:36.04#ibcon#about to read 6, iclass 4, count 2 2006.201.12:28:36.04#ibcon#read 6, iclass 4, count 2 2006.201.12:28:36.04#ibcon#end of sib2, iclass 4, count 2 2006.201.12:28:36.04#ibcon#*mode == 0, iclass 4, count 2 2006.201.12:28:36.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.12:28:36.04#ibcon#[25=AT07-05\r\n] 2006.201.12:28:36.04#ibcon#*before write, iclass 4, count 2 2006.201.12:28:36.04#ibcon#enter sib2, iclass 4, count 2 2006.201.12:28:36.04#ibcon#flushed, iclass 4, count 2 2006.201.12:28:36.04#ibcon#about to write, iclass 4, count 2 2006.201.12:28:36.04#ibcon#wrote, iclass 4, count 2 2006.201.12:28:36.04#ibcon#about to read 3, iclass 4, count 2 2006.201.12:28:36.07#ibcon#read 3, iclass 4, count 2 2006.201.12:28:36.07#ibcon#about to read 4, iclass 4, count 2 2006.201.12:28:36.07#ibcon#read 4, iclass 4, count 2 2006.201.12:28:36.07#ibcon#about to read 5, iclass 4, count 2 2006.201.12:28:36.07#ibcon#read 5, iclass 4, count 2 2006.201.12:28:36.07#ibcon#about to read 6, iclass 4, count 2 2006.201.12:28:36.07#ibcon#read 6, iclass 4, count 2 2006.201.12:28:36.07#ibcon#end of sib2, iclass 4, count 2 2006.201.12:28:36.07#ibcon#*after write, iclass 4, count 2 2006.201.12:28:36.07#ibcon#*before return 0, iclass 4, count 2 2006.201.12:28:36.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:36.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:36.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.12:28:36.07#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:36.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:36.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:36.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:36.19#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:28:36.19#ibcon#first serial, iclass 4, count 0 2006.201.12:28:36.19#ibcon#enter sib2, iclass 4, count 0 2006.201.12:28:36.19#ibcon#flushed, iclass 4, count 0 2006.201.12:28:36.19#ibcon#about to write, iclass 4, count 0 2006.201.12:28:36.19#ibcon#wrote, iclass 4, count 0 2006.201.12:28:36.19#ibcon#about to read 3, iclass 4, count 0 2006.201.12:28:36.21#ibcon#read 3, iclass 4, count 0 2006.201.12:28:36.21#ibcon#about to read 4, iclass 4, count 0 2006.201.12:28:36.21#ibcon#read 4, iclass 4, count 0 2006.201.12:28:36.21#ibcon#about to read 5, iclass 4, count 0 2006.201.12:28:36.21#ibcon#read 5, iclass 4, count 0 2006.201.12:28:36.21#ibcon#about to read 6, iclass 4, count 0 2006.201.12:28:36.21#ibcon#read 6, iclass 4, count 0 2006.201.12:28:36.21#ibcon#end of sib2, iclass 4, count 0 2006.201.12:28:36.21#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:28:36.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:28:36.21#ibcon#[25=USB\r\n] 2006.201.12:28:36.21#ibcon#*before write, iclass 4, count 0 2006.201.12:28:36.21#ibcon#enter sib2, iclass 4, count 0 2006.201.12:28:36.21#ibcon#flushed, iclass 4, count 0 2006.201.12:28:36.21#ibcon#about to write, iclass 4, count 0 2006.201.12:28:36.21#ibcon#wrote, iclass 4, count 0 2006.201.12:28:36.21#ibcon#about to read 3, iclass 4, count 0 2006.201.12:28:36.24#ibcon#read 3, iclass 4, count 0 2006.201.12:28:36.24#ibcon#about to read 4, iclass 4, count 0 2006.201.12:28:36.24#ibcon#read 4, iclass 4, count 0 2006.201.12:28:36.24#ibcon#about to read 5, iclass 4, count 0 2006.201.12:28:36.24#ibcon#read 5, iclass 4, count 0 2006.201.12:28:36.24#ibcon#about to read 6, iclass 4, count 0 2006.201.12:28:36.24#ibcon#read 6, iclass 4, count 0 2006.201.12:28:36.24#ibcon#end of sib2, iclass 4, count 0 2006.201.12:28:36.24#ibcon#*after write, iclass 4, count 0 2006.201.12:28:36.24#ibcon#*before return 0, iclass 4, count 0 2006.201.12:28:36.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:36.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:36.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:28:36.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:28:36.24$vck44/valo=8,884.99 2006.201.12:28:36.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.12:28:36.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.12:28:36.24#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:36.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:36.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:36.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:36.24#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:28:36.24#ibcon#first serial, iclass 6, count 0 2006.201.12:28:36.24#ibcon#enter sib2, iclass 6, count 0 2006.201.12:28:36.24#ibcon#flushed, iclass 6, count 0 2006.201.12:28:36.24#ibcon#about to write, iclass 6, count 0 2006.201.12:28:36.24#ibcon#wrote, iclass 6, count 0 2006.201.12:28:36.24#ibcon#about to read 3, iclass 6, count 0 2006.201.12:28:36.26#ibcon#read 3, iclass 6, count 0 2006.201.12:28:36.26#ibcon#about to read 4, iclass 6, count 0 2006.201.12:28:36.26#ibcon#read 4, iclass 6, count 0 2006.201.12:28:36.26#ibcon#about to read 5, iclass 6, count 0 2006.201.12:28:36.26#ibcon#read 5, iclass 6, count 0 2006.201.12:28:36.26#ibcon#about to read 6, iclass 6, count 0 2006.201.12:28:36.26#ibcon#read 6, iclass 6, count 0 2006.201.12:28:36.26#ibcon#end of sib2, iclass 6, count 0 2006.201.12:28:36.26#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:28:36.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:28:36.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:28:36.26#ibcon#*before write, iclass 6, count 0 2006.201.12:28:36.26#ibcon#enter sib2, iclass 6, count 0 2006.201.12:28:36.26#ibcon#flushed, iclass 6, count 0 2006.201.12:28:36.26#ibcon#about to write, iclass 6, count 0 2006.201.12:28:36.26#ibcon#wrote, iclass 6, count 0 2006.201.12:28:36.26#ibcon#about to read 3, iclass 6, count 0 2006.201.12:28:36.30#ibcon#read 3, iclass 6, count 0 2006.201.12:28:36.30#ibcon#about to read 4, iclass 6, count 0 2006.201.12:28:36.30#ibcon#read 4, iclass 6, count 0 2006.201.12:28:36.30#ibcon#about to read 5, iclass 6, count 0 2006.201.12:28:36.30#ibcon#read 5, iclass 6, count 0 2006.201.12:28:36.30#ibcon#about to read 6, iclass 6, count 0 2006.201.12:28:36.30#ibcon#read 6, iclass 6, count 0 2006.201.12:28:36.30#ibcon#end of sib2, iclass 6, count 0 2006.201.12:28:36.30#ibcon#*after write, iclass 6, count 0 2006.201.12:28:36.30#ibcon#*before return 0, iclass 6, count 0 2006.201.12:28:36.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:36.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:36.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:28:36.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:28:36.30$vck44/va=8,4 2006.201.12:28:36.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.12:28:36.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.12:28:36.30#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:36.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:36.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:36.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:36.36#ibcon#enter wrdev, iclass 10, count 2 2006.201.12:28:36.36#ibcon#first serial, iclass 10, count 2 2006.201.12:28:36.36#ibcon#enter sib2, iclass 10, count 2 2006.201.12:28:36.36#ibcon#flushed, iclass 10, count 2 2006.201.12:28:36.36#ibcon#about to write, iclass 10, count 2 2006.201.12:28:36.36#ibcon#wrote, iclass 10, count 2 2006.201.12:28:36.36#ibcon#about to read 3, iclass 10, count 2 2006.201.12:28:36.38#ibcon#read 3, iclass 10, count 2 2006.201.12:28:36.38#ibcon#about to read 4, iclass 10, count 2 2006.201.12:28:36.38#ibcon#read 4, iclass 10, count 2 2006.201.12:28:36.38#ibcon#about to read 5, iclass 10, count 2 2006.201.12:28:36.38#ibcon#read 5, iclass 10, count 2 2006.201.12:28:36.38#ibcon#about to read 6, iclass 10, count 2 2006.201.12:28:36.38#ibcon#read 6, iclass 10, count 2 2006.201.12:28:36.38#ibcon#end of sib2, iclass 10, count 2 2006.201.12:28:36.38#ibcon#*mode == 0, iclass 10, count 2 2006.201.12:28:36.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.12:28:36.38#ibcon#[25=AT08-04\r\n] 2006.201.12:28:36.38#ibcon#*before write, iclass 10, count 2 2006.201.12:28:36.38#ibcon#enter sib2, iclass 10, count 2 2006.201.12:28:36.38#ibcon#flushed, iclass 10, count 2 2006.201.12:28:36.38#ibcon#about to write, iclass 10, count 2 2006.201.12:28:36.38#ibcon#wrote, iclass 10, count 2 2006.201.12:28:36.38#ibcon#about to read 3, iclass 10, count 2 2006.201.12:28:36.41#ibcon#read 3, iclass 10, count 2 2006.201.12:28:36.41#ibcon#about to read 4, iclass 10, count 2 2006.201.12:28:36.41#ibcon#read 4, iclass 10, count 2 2006.201.12:28:36.41#ibcon#about to read 5, iclass 10, count 2 2006.201.12:28:36.41#ibcon#read 5, iclass 10, count 2 2006.201.12:28:36.41#ibcon#about to read 6, iclass 10, count 2 2006.201.12:28:36.41#ibcon#read 6, iclass 10, count 2 2006.201.12:28:36.41#ibcon#end of sib2, iclass 10, count 2 2006.201.12:28:36.41#ibcon#*after write, iclass 10, count 2 2006.201.12:28:36.41#ibcon#*before return 0, iclass 10, count 2 2006.201.12:28:36.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:36.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:36.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.12:28:36.41#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:36.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:36.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:36.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:36.53#ibcon#enter wrdev, iclass 10, count 0 2006.201.12:28:36.53#ibcon#first serial, iclass 10, count 0 2006.201.12:28:36.53#ibcon#enter sib2, iclass 10, count 0 2006.201.12:28:36.53#ibcon#flushed, iclass 10, count 0 2006.201.12:28:36.53#ibcon#about to write, iclass 10, count 0 2006.201.12:28:36.53#ibcon#wrote, iclass 10, count 0 2006.201.12:28:36.53#ibcon#about to read 3, iclass 10, count 0 2006.201.12:28:36.55#ibcon#read 3, iclass 10, count 0 2006.201.12:28:36.55#ibcon#about to read 4, iclass 10, count 0 2006.201.12:28:36.55#ibcon#read 4, iclass 10, count 0 2006.201.12:28:36.55#ibcon#about to read 5, iclass 10, count 0 2006.201.12:28:36.55#ibcon#read 5, iclass 10, count 0 2006.201.12:28:36.55#ibcon#about to read 6, iclass 10, count 0 2006.201.12:28:36.55#ibcon#read 6, iclass 10, count 0 2006.201.12:28:36.55#ibcon#end of sib2, iclass 10, count 0 2006.201.12:28:36.55#ibcon#*mode == 0, iclass 10, count 0 2006.201.12:28:36.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.12:28:36.55#ibcon#[25=USB\r\n] 2006.201.12:28:36.55#ibcon#*before write, iclass 10, count 0 2006.201.12:28:36.55#ibcon#enter sib2, iclass 10, count 0 2006.201.12:28:36.55#ibcon#flushed, iclass 10, count 0 2006.201.12:28:36.55#ibcon#about to write, iclass 10, count 0 2006.201.12:28:36.55#ibcon#wrote, iclass 10, count 0 2006.201.12:28:36.55#ibcon#about to read 3, iclass 10, count 0 2006.201.12:28:36.58#ibcon#read 3, iclass 10, count 0 2006.201.12:28:36.58#ibcon#about to read 4, iclass 10, count 0 2006.201.12:28:36.58#ibcon#read 4, iclass 10, count 0 2006.201.12:28:36.58#ibcon#about to read 5, iclass 10, count 0 2006.201.12:28:36.58#ibcon#read 5, iclass 10, count 0 2006.201.12:28:36.58#ibcon#about to read 6, iclass 10, count 0 2006.201.12:28:36.58#ibcon#read 6, iclass 10, count 0 2006.201.12:28:36.58#ibcon#end of sib2, iclass 10, count 0 2006.201.12:28:36.58#ibcon#*after write, iclass 10, count 0 2006.201.12:28:36.58#ibcon#*before return 0, iclass 10, count 0 2006.201.12:28:36.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:36.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:36.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.12:28:36.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.12:28:36.58$vck44/vblo=1,629.99 2006.201.12:28:36.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.12:28:36.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.12:28:36.58#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:36.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:36.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:36.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:36.58#ibcon#enter wrdev, iclass 12, count 0 2006.201.12:28:36.58#ibcon#first serial, iclass 12, count 0 2006.201.12:28:36.58#ibcon#enter sib2, iclass 12, count 0 2006.201.12:28:36.58#ibcon#flushed, iclass 12, count 0 2006.201.12:28:36.58#ibcon#about to write, iclass 12, count 0 2006.201.12:28:36.58#ibcon#wrote, iclass 12, count 0 2006.201.12:28:36.58#ibcon#about to read 3, iclass 12, count 0 2006.201.12:28:36.60#ibcon#read 3, iclass 12, count 0 2006.201.12:28:36.60#ibcon#about to read 4, iclass 12, count 0 2006.201.12:28:36.60#ibcon#read 4, iclass 12, count 0 2006.201.12:28:36.60#ibcon#about to read 5, iclass 12, count 0 2006.201.12:28:36.60#ibcon#read 5, iclass 12, count 0 2006.201.12:28:36.60#ibcon#about to read 6, iclass 12, count 0 2006.201.12:28:36.60#ibcon#read 6, iclass 12, count 0 2006.201.12:28:36.60#ibcon#end of sib2, iclass 12, count 0 2006.201.12:28:36.60#ibcon#*mode == 0, iclass 12, count 0 2006.201.12:28:36.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.12:28:36.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:28:36.60#ibcon#*before write, iclass 12, count 0 2006.201.12:28:36.60#ibcon#enter sib2, iclass 12, count 0 2006.201.12:28:36.60#ibcon#flushed, iclass 12, count 0 2006.201.12:28:36.60#ibcon#about to write, iclass 12, count 0 2006.201.12:28:36.60#ibcon#wrote, iclass 12, count 0 2006.201.12:28:36.60#ibcon#about to read 3, iclass 12, count 0 2006.201.12:28:36.65#ibcon#read 3, iclass 12, count 0 2006.201.12:28:36.65#ibcon#about to read 4, iclass 12, count 0 2006.201.12:28:36.65#ibcon#read 4, iclass 12, count 0 2006.201.12:28:36.65#ibcon#about to read 5, iclass 12, count 0 2006.201.12:28:36.65#ibcon#read 5, iclass 12, count 0 2006.201.12:28:36.65#ibcon#about to read 6, iclass 12, count 0 2006.201.12:28:36.65#ibcon#read 6, iclass 12, count 0 2006.201.12:28:36.65#ibcon#end of sib2, iclass 12, count 0 2006.201.12:28:36.65#ibcon#*after write, iclass 12, count 0 2006.201.12:28:36.65#ibcon#*before return 0, iclass 12, count 0 2006.201.12:28:36.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:36.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:36.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.12:28:36.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.12:28:36.65$vck44/vb=1,4 2006.201.12:28:36.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.12:28:36.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.12:28:36.65#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:36.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:28:36.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:28:36.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:28:36.65#ibcon#enter wrdev, iclass 14, count 2 2006.201.12:28:36.65#ibcon#first serial, iclass 14, count 2 2006.201.12:28:36.65#ibcon#enter sib2, iclass 14, count 2 2006.201.12:28:36.65#ibcon#flushed, iclass 14, count 2 2006.201.12:28:36.65#ibcon#about to write, iclass 14, count 2 2006.201.12:28:36.65#ibcon#wrote, iclass 14, count 2 2006.201.12:28:36.65#ibcon#about to read 3, iclass 14, count 2 2006.201.12:28:36.67#ibcon#read 3, iclass 14, count 2 2006.201.12:28:36.67#ibcon#about to read 4, iclass 14, count 2 2006.201.12:28:36.67#ibcon#read 4, iclass 14, count 2 2006.201.12:28:36.67#ibcon#about to read 5, iclass 14, count 2 2006.201.12:28:36.67#ibcon#read 5, iclass 14, count 2 2006.201.12:28:36.67#ibcon#about to read 6, iclass 14, count 2 2006.201.12:28:36.67#ibcon#read 6, iclass 14, count 2 2006.201.12:28:36.67#ibcon#end of sib2, iclass 14, count 2 2006.201.12:28:36.67#ibcon#*mode == 0, iclass 14, count 2 2006.201.12:28:36.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.12:28:36.67#ibcon#[27=AT01-04\r\n] 2006.201.12:28:36.67#ibcon#*before write, iclass 14, count 2 2006.201.12:28:36.67#ibcon#enter sib2, iclass 14, count 2 2006.201.12:28:36.67#ibcon#flushed, iclass 14, count 2 2006.201.12:28:36.67#ibcon#about to write, iclass 14, count 2 2006.201.12:28:36.67#ibcon#wrote, iclass 14, count 2 2006.201.12:28:36.67#ibcon#about to read 3, iclass 14, count 2 2006.201.12:28:36.70#ibcon#read 3, iclass 14, count 2 2006.201.12:28:36.70#ibcon#about to read 4, iclass 14, count 2 2006.201.12:28:36.70#ibcon#read 4, iclass 14, count 2 2006.201.12:28:36.70#ibcon#about to read 5, iclass 14, count 2 2006.201.12:28:36.70#ibcon#read 5, iclass 14, count 2 2006.201.12:28:36.70#ibcon#about to read 6, iclass 14, count 2 2006.201.12:28:36.70#ibcon#read 6, iclass 14, count 2 2006.201.12:28:36.70#ibcon#end of sib2, iclass 14, count 2 2006.201.12:28:36.70#ibcon#*after write, iclass 14, count 2 2006.201.12:28:36.70#ibcon#*before return 0, iclass 14, count 2 2006.201.12:28:36.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:28:36.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:28:36.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.12:28:36.70#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:36.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:28:36.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:28:36.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:28:36.82#ibcon#enter wrdev, iclass 14, count 0 2006.201.12:28:36.82#ibcon#first serial, iclass 14, count 0 2006.201.12:28:36.82#ibcon#enter sib2, iclass 14, count 0 2006.201.12:28:36.82#ibcon#flushed, iclass 14, count 0 2006.201.12:28:36.82#ibcon#about to write, iclass 14, count 0 2006.201.12:28:36.82#ibcon#wrote, iclass 14, count 0 2006.201.12:28:36.82#ibcon#about to read 3, iclass 14, count 0 2006.201.12:28:36.84#ibcon#read 3, iclass 14, count 0 2006.201.12:28:36.84#ibcon#about to read 4, iclass 14, count 0 2006.201.12:28:36.84#ibcon#read 4, iclass 14, count 0 2006.201.12:28:36.84#ibcon#about to read 5, iclass 14, count 0 2006.201.12:28:36.84#ibcon#read 5, iclass 14, count 0 2006.201.12:28:36.84#ibcon#about to read 6, iclass 14, count 0 2006.201.12:28:36.84#ibcon#read 6, iclass 14, count 0 2006.201.12:28:36.84#ibcon#end of sib2, iclass 14, count 0 2006.201.12:28:36.84#ibcon#*mode == 0, iclass 14, count 0 2006.201.12:28:36.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.12:28:36.84#ibcon#[27=USB\r\n] 2006.201.12:28:36.84#ibcon#*before write, iclass 14, count 0 2006.201.12:28:36.84#ibcon#enter sib2, iclass 14, count 0 2006.201.12:28:36.84#ibcon#flushed, iclass 14, count 0 2006.201.12:28:36.84#ibcon#about to write, iclass 14, count 0 2006.201.12:28:36.84#ibcon#wrote, iclass 14, count 0 2006.201.12:28:36.84#ibcon#about to read 3, iclass 14, count 0 2006.201.12:28:36.87#ibcon#read 3, iclass 14, count 0 2006.201.12:28:36.87#ibcon#about to read 4, iclass 14, count 0 2006.201.12:28:36.87#ibcon#read 4, iclass 14, count 0 2006.201.12:28:36.87#ibcon#about to read 5, iclass 14, count 0 2006.201.12:28:36.87#ibcon#read 5, iclass 14, count 0 2006.201.12:28:36.87#ibcon#about to read 6, iclass 14, count 0 2006.201.12:28:36.87#ibcon#read 6, iclass 14, count 0 2006.201.12:28:36.87#ibcon#end of sib2, iclass 14, count 0 2006.201.12:28:36.87#ibcon#*after write, iclass 14, count 0 2006.201.12:28:36.87#ibcon#*before return 0, iclass 14, count 0 2006.201.12:28:36.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:28:36.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:28:36.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.12:28:36.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.12:28:36.87$vck44/vblo=2,634.99 2006.201.12:28:36.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.12:28:36.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.12:28:36.87#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:36.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:36.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:36.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:36.87#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:28:36.87#ibcon#first serial, iclass 16, count 0 2006.201.12:28:36.87#ibcon#enter sib2, iclass 16, count 0 2006.201.12:28:36.87#ibcon#flushed, iclass 16, count 0 2006.201.12:28:36.87#ibcon#about to write, iclass 16, count 0 2006.201.12:28:36.87#ibcon#wrote, iclass 16, count 0 2006.201.12:28:36.87#ibcon#about to read 3, iclass 16, count 0 2006.201.12:28:36.89#ibcon#read 3, iclass 16, count 0 2006.201.12:28:36.89#ibcon#about to read 4, iclass 16, count 0 2006.201.12:28:36.89#ibcon#read 4, iclass 16, count 0 2006.201.12:28:36.89#ibcon#about to read 5, iclass 16, count 0 2006.201.12:28:36.89#ibcon#read 5, iclass 16, count 0 2006.201.12:28:36.89#ibcon#about to read 6, iclass 16, count 0 2006.201.12:28:36.89#ibcon#read 6, iclass 16, count 0 2006.201.12:28:36.89#ibcon#end of sib2, iclass 16, count 0 2006.201.12:28:36.89#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:28:36.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:28:36.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:28:36.89#ibcon#*before write, iclass 16, count 0 2006.201.12:28:36.89#ibcon#enter sib2, iclass 16, count 0 2006.201.12:28:36.89#ibcon#flushed, iclass 16, count 0 2006.201.12:28:36.89#ibcon#about to write, iclass 16, count 0 2006.201.12:28:36.89#ibcon#wrote, iclass 16, count 0 2006.201.12:28:36.89#ibcon#about to read 3, iclass 16, count 0 2006.201.12:28:36.93#ibcon#read 3, iclass 16, count 0 2006.201.12:28:36.93#ibcon#about to read 4, iclass 16, count 0 2006.201.12:28:36.93#ibcon#read 4, iclass 16, count 0 2006.201.12:28:36.93#ibcon#about to read 5, iclass 16, count 0 2006.201.12:28:36.93#ibcon#read 5, iclass 16, count 0 2006.201.12:28:36.93#ibcon#about to read 6, iclass 16, count 0 2006.201.12:28:36.93#ibcon#read 6, iclass 16, count 0 2006.201.12:28:36.93#ibcon#end of sib2, iclass 16, count 0 2006.201.12:28:36.93#ibcon#*after write, iclass 16, count 0 2006.201.12:28:36.93#ibcon#*before return 0, iclass 16, count 0 2006.201.12:28:36.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:36.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:28:36.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:28:36.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:28:36.93$vck44/vb=2,5 2006.201.12:28:36.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.12:28:36.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.12:28:36.93#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:36.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:36.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:36.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:36.99#ibcon#enter wrdev, iclass 18, count 2 2006.201.12:28:36.99#ibcon#first serial, iclass 18, count 2 2006.201.12:28:36.99#ibcon#enter sib2, iclass 18, count 2 2006.201.12:28:36.99#ibcon#flushed, iclass 18, count 2 2006.201.12:28:36.99#ibcon#about to write, iclass 18, count 2 2006.201.12:28:36.99#ibcon#wrote, iclass 18, count 2 2006.201.12:28:36.99#ibcon#about to read 3, iclass 18, count 2 2006.201.12:28:37.01#ibcon#read 3, iclass 18, count 2 2006.201.12:28:37.01#ibcon#about to read 4, iclass 18, count 2 2006.201.12:28:37.01#ibcon#read 4, iclass 18, count 2 2006.201.12:28:37.01#ibcon#about to read 5, iclass 18, count 2 2006.201.12:28:37.01#ibcon#read 5, iclass 18, count 2 2006.201.12:28:37.01#ibcon#about to read 6, iclass 18, count 2 2006.201.12:28:37.01#ibcon#read 6, iclass 18, count 2 2006.201.12:28:37.01#ibcon#end of sib2, iclass 18, count 2 2006.201.12:28:37.01#ibcon#*mode == 0, iclass 18, count 2 2006.201.12:28:37.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.12:28:37.01#ibcon#[27=AT02-05\r\n] 2006.201.12:28:37.01#ibcon#*before write, iclass 18, count 2 2006.201.12:28:37.01#ibcon#enter sib2, iclass 18, count 2 2006.201.12:28:37.01#ibcon#flushed, iclass 18, count 2 2006.201.12:28:37.01#ibcon#about to write, iclass 18, count 2 2006.201.12:28:37.01#ibcon#wrote, iclass 18, count 2 2006.201.12:28:37.01#ibcon#about to read 3, iclass 18, count 2 2006.201.12:28:37.04#ibcon#read 3, iclass 18, count 2 2006.201.12:28:37.04#ibcon#about to read 4, iclass 18, count 2 2006.201.12:28:37.04#ibcon#read 4, iclass 18, count 2 2006.201.12:28:37.04#ibcon#about to read 5, iclass 18, count 2 2006.201.12:28:37.04#ibcon#read 5, iclass 18, count 2 2006.201.12:28:37.04#ibcon#about to read 6, iclass 18, count 2 2006.201.12:28:37.04#ibcon#read 6, iclass 18, count 2 2006.201.12:28:37.04#ibcon#end of sib2, iclass 18, count 2 2006.201.12:28:37.04#ibcon#*after write, iclass 18, count 2 2006.201.12:28:37.04#ibcon#*before return 0, iclass 18, count 2 2006.201.12:28:37.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:37.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:28:37.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.12:28:37.04#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:37.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:37.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:37.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:37.16#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:28:37.16#ibcon#first serial, iclass 18, count 0 2006.201.12:28:37.16#ibcon#enter sib2, iclass 18, count 0 2006.201.12:28:37.16#ibcon#flushed, iclass 18, count 0 2006.201.12:28:37.16#ibcon#about to write, iclass 18, count 0 2006.201.12:28:37.16#ibcon#wrote, iclass 18, count 0 2006.201.12:28:37.16#ibcon#about to read 3, iclass 18, count 0 2006.201.12:28:37.18#ibcon#read 3, iclass 18, count 0 2006.201.12:28:37.18#ibcon#about to read 4, iclass 18, count 0 2006.201.12:28:37.18#ibcon#read 4, iclass 18, count 0 2006.201.12:28:37.18#ibcon#about to read 5, iclass 18, count 0 2006.201.12:28:37.18#ibcon#read 5, iclass 18, count 0 2006.201.12:28:37.18#ibcon#about to read 6, iclass 18, count 0 2006.201.12:28:37.18#ibcon#read 6, iclass 18, count 0 2006.201.12:28:37.18#ibcon#end of sib2, iclass 18, count 0 2006.201.12:28:37.18#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:28:37.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:28:37.18#ibcon#[27=USB\r\n] 2006.201.12:28:37.18#ibcon#*before write, iclass 18, count 0 2006.201.12:28:37.18#ibcon#enter sib2, iclass 18, count 0 2006.201.12:28:37.18#ibcon#flushed, iclass 18, count 0 2006.201.12:28:37.18#ibcon#about to write, iclass 18, count 0 2006.201.12:28:37.18#ibcon#wrote, iclass 18, count 0 2006.201.12:28:37.18#ibcon#about to read 3, iclass 18, count 0 2006.201.12:28:37.21#ibcon#read 3, iclass 18, count 0 2006.201.12:28:37.21#ibcon#about to read 4, iclass 18, count 0 2006.201.12:28:37.21#ibcon#read 4, iclass 18, count 0 2006.201.12:28:37.21#ibcon#about to read 5, iclass 18, count 0 2006.201.12:28:37.21#ibcon#read 5, iclass 18, count 0 2006.201.12:28:37.21#ibcon#about to read 6, iclass 18, count 0 2006.201.12:28:37.21#ibcon#read 6, iclass 18, count 0 2006.201.12:28:37.21#ibcon#end of sib2, iclass 18, count 0 2006.201.12:28:37.21#ibcon#*after write, iclass 18, count 0 2006.201.12:28:37.21#ibcon#*before return 0, iclass 18, count 0 2006.201.12:28:37.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:37.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:28:37.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:28:37.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:28:37.21$vck44/vblo=3,649.99 2006.201.12:28:37.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.12:28:37.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.12:28:37.21#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:37.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:37.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:37.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:37.21#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:28:37.21#ibcon#first serial, iclass 20, count 0 2006.201.12:28:37.21#ibcon#enter sib2, iclass 20, count 0 2006.201.12:28:37.21#ibcon#flushed, iclass 20, count 0 2006.201.12:28:37.21#ibcon#about to write, iclass 20, count 0 2006.201.12:28:37.21#ibcon#wrote, iclass 20, count 0 2006.201.12:28:37.21#ibcon#about to read 3, iclass 20, count 0 2006.201.12:28:37.23#ibcon#read 3, iclass 20, count 0 2006.201.12:28:37.23#ibcon#about to read 4, iclass 20, count 0 2006.201.12:28:37.23#ibcon#read 4, iclass 20, count 0 2006.201.12:28:37.23#ibcon#about to read 5, iclass 20, count 0 2006.201.12:28:37.23#ibcon#read 5, iclass 20, count 0 2006.201.12:28:37.23#ibcon#about to read 6, iclass 20, count 0 2006.201.12:28:37.23#ibcon#read 6, iclass 20, count 0 2006.201.12:28:37.23#ibcon#end of sib2, iclass 20, count 0 2006.201.12:28:37.23#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:28:37.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:28:37.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:28:37.23#ibcon#*before write, iclass 20, count 0 2006.201.12:28:37.23#ibcon#enter sib2, iclass 20, count 0 2006.201.12:28:37.23#ibcon#flushed, iclass 20, count 0 2006.201.12:28:37.23#ibcon#about to write, iclass 20, count 0 2006.201.12:28:37.23#ibcon#wrote, iclass 20, count 0 2006.201.12:28:37.23#ibcon#about to read 3, iclass 20, count 0 2006.201.12:28:37.27#ibcon#read 3, iclass 20, count 0 2006.201.12:28:37.27#ibcon#about to read 4, iclass 20, count 0 2006.201.12:28:37.27#ibcon#read 4, iclass 20, count 0 2006.201.12:28:37.27#ibcon#about to read 5, iclass 20, count 0 2006.201.12:28:37.27#ibcon#read 5, iclass 20, count 0 2006.201.12:28:37.27#ibcon#about to read 6, iclass 20, count 0 2006.201.12:28:37.27#ibcon#read 6, iclass 20, count 0 2006.201.12:28:37.27#ibcon#end of sib2, iclass 20, count 0 2006.201.12:28:37.27#ibcon#*after write, iclass 20, count 0 2006.201.12:28:37.27#ibcon#*before return 0, iclass 20, count 0 2006.201.12:28:37.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:37.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:28:37.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:28:37.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:28:37.27$vck44/vb=3,4 2006.201.12:28:37.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.12:28:37.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.12:28:37.27#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:37.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:37.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:37.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:37.33#ibcon#enter wrdev, iclass 22, count 2 2006.201.12:28:37.33#ibcon#first serial, iclass 22, count 2 2006.201.12:28:37.33#ibcon#enter sib2, iclass 22, count 2 2006.201.12:28:37.33#ibcon#flushed, iclass 22, count 2 2006.201.12:28:37.33#ibcon#about to write, iclass 22, count 2 2006.201.12:28:37.33#ibcon#wrote, iclass 22, count 2 2006.201.12:28:37.33#ibcon#about to read 3, iclass 22, count 2 2006.201.12:28:37.35#ibcon#read 3, iclass 22, count 2 2006.201.12:28:37.35#ibcon#about to read 4, iclass 22, count 2 2006.201.12:28:37.35#ibcon#read 4, iclass 22, count 2 2006.201.12:28:37.35#ibcon#about to read 5, iclass 22, count 2 2006.201.12:28:37.35#ibcon#read 5, iclass 22, count 2 2006.201.12:28:37.35#ibcon#about to read 6, iclass 22, count 2 2006.201.12:28:37.35#ibcon#read 6, iclass 22, count 2 2006.201.12:28:37.35#ibcon#end of sib2, iclass 22, count 2 2006.201.12:28:37.35#ibcon#*mode == 0, iclass 22, count 2 2006.201.12:28:37.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.12:28:37.35#ibcon#[27=AT03-04\r\n] 2006.201.12:28:37.35#ibcon#*before write, iclass 22, count 2 2006.201.12:28:37.35#ibcon#enter sib2, iclass 22, count 2 2006.201.12:28:37.35#ibcon#flushed, iclass 22, count 2 2006.201.12:28:37.35#ibcon#about to write, iclass 22, count 2 2006.201.12:28:37.35#ibcon#wrote, iclass 22, count 2 2006.201.12:28:37.35#ibcon#about to read 3, iclass 22, count 2 2006.201.12:28:37.38#ibcon#read 3, iclass 22, count 2 2006.201.12:28:37.38#ibcon#about to read 4, iclass 22, count 2 2006.201.12:28:37.38#ibcon#read 4, iclass 22, count 2 2006.201.12:28:37.38#ibcon#about to read 5, iclass 22, count 2 2006.201.12:28:37.38#ibcon#read 5, iclass 22, count 2 2006.201.12:28:37.38#ibcon#about to read 6, iclass 22, count 2 2006.201.12:28:37.38#ibcon#read 6, iclass 22, count 2 2006.201.12:28:37.38#ibcon#end of sib2, iclass 22, count 2 2006.201.12:28:37.38#ibcon#*after write, iclass 22, count 2 2006.201.12:28:37.38#ibcon#*before return 0, iclass 22, count 2 2006.201.12:28:37.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:37.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:28:37.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.12:28:37.38#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:37.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:37.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:37.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:37.50#ibcon#enter wrdev, iclass 22, count 0 2006.201.12:28:37.50#ibcon#first serial, iclass 22, count 0 2006.201.12:28:37.50#ibcon#enter sib2, iclass 22, count 0 2006.201.12:28:37.50#ibcon#flushed, iclass 22, count 0 2006.201.12:28:37.50#ibcon#about to write, iclass 22, count 0 2006.201.12:28:37.50#ibcon#wrote, iclass 22, count 0 2006.201.12:28:37.50#ibcon#about to read 3, iclass 22, count 0 2006.201.12:28:37.52#ibcon#read 3, iclass 22, count 0 2006.201.12:28:37.52#ibcon#about to read 4, iclass 22, count 0 2006.201.12:28:37.52#ibcon#read 4, iclass 22, count 0 2006.201.12:28:37.52#ibcon#about to read 5, iclass 22, count 0 2006.201.12:28:37.52#ibcon#read 5, iclass 22, count 0 2006.201.12:28:37.52#ibcon#about to read 6, iclass 22, count 0 2006.201.12:28:37.52#ibcon#read 6, iclass 22, count 0 2006.201.12:28:37.52#ibcon#end of sib2, iclass 22, count 0 2006.201.12:28:37.52#ibcon#*mode == 0, iclass 22, count 0 2006.201.12:28:37.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.12:28:37.52#ibcon#[27=USB\r\n] 2006.201.12:28:37.52#ibcon#*before write, iclass 22, count 0 2006.201.12:28:37.52#ibcon#enter sib2, iclass 22, count 0 2006.201.12:28:37.52#ibcon#flushed, iclass 22, count 0 2006.201.12:28:37.52#ibcon#about to write, iclass 22, count 0 2006.201.12:28:37.52#ibcon#wrote, iclass 22, count 0 2006.201.12:28:37.52#ibcon#about to read 3, iclass 22, count 0 2006.201.12:28:37.55#ibcon#read 3, iclass 22, count 0 2006.201.12:28:37.55#ibcon#about to read 4, iclass 22, count 0 2006.201.12:28:37.55#ibcon#read 4, iclass 22, count 0 2006.201.12:28:37.55#ibcon#about to read 5, iclass 22, count 0 2006.201.12:28:37.55#ibcon#read 5, iclass 22, count 0 2006.201.12:28:37.55#ibcon#about to read 6, iclass 22, count 0 2006.201.12:28:37.55#ibcon#read 6, iclass 22, count 0 2006.201.12:28:37.55#ibcon#end of sib2, iclass 22, count 0 2006.201.12:28:37.55#ibcon#*after write, iclass 22, count 0 2006.201.12:28:37.55#ibcon#*before return 0, iclass 22, count 0 2006.201.12:28:37.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:37.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:28:37.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.12:28:37.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.12:28:37.55$vck44/vblo=4,679.99 2006.201.12:28:37.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.12:28:37.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.12:28:37.55#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:37.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:28:37.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:28:37.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:28:37.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:28:37.55#ibcon#first serial, iclass 25, count 0 2006.201.12:28:37.55#ibcon#enter sib2, iclass 25, count 0 2006.201.12:28:37.55#ibcon#flushed, iclass 25, count 0 2006.201.12:28:37.55#ibcon#about to write, iclass 25, count 0 2006.201.12:28:37.55#ibcon#wrote, iclass 25, count 0 2006.201.12:28:37.55#ibcon#about to read 3, iclass 25, count 0 2006.201.12:28:37.56#abcon#<5=/04 1.7 3.7 21.141001004.2\r\n> 2006.201.12:28:37.57#ibcon#read 3, iclass 25, count 0 2006.201.12:28:37.57#ibcon#about to read 4, iclass 25, count 0 2006.201.12:28:37.57#ibcon#read 4, iclass 25, count 0 2006.201.12:28:37.57#ibcon#about to read 5, iclass 25, count 0 2006.201.12:28:37.57#ibcon#read 5, iclass 25, count 0 2006.201.12:28:37.57#ibcon#about to read 6, iclass 25, count 0 2006.201.12:28:37.57#ibcon#read 6, iclass 25, count 0 2006.201.12:28:37.57#ibcon#end of sib2, iclass 25, count 0 2006.201.12:28:37.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:28:37.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:28:37.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:28:37.57#ibcon#*before write, iclass 25, count 0 2006.201.12:28:37.57#ibcon#enter sib2, iclass 25, count 0 2006.201.12:28:37.57#ibcon#flushed, iclass 25, count 0 2006.201.12:28:37.57#ibcon#about to write, iclass 25, count 0 2006.201.12:28:37.57#ibcon#wrote, iclass 25, count 0 2006.201.12:28:37.57#ibcon#about to read 3, iclass 25, count 0 2006.201.12:28:37.58#abcon#{5=INTERFACE CLEAR} 2006.201.12:28:37.62#ibcon#read 3, iclass 25, count 0 2006.201.12:28:37.62#ibcon#about to read 4, iclass 25, count 0 2006.201.12:28:37.62#ibcon#read 4, iclass 25, count 0 2006.201.12:28:37.62#ibcon#about to read 5, iclass 25, count 0 2006.201.12:28:37.62#ibcon#read 5, iclass 25, count 0 2006.201.12:28:37.62#ibcon#about to read 6, iclass 25, count 0 2006.201.12:28:37.62#ibcon#read 6, iclass 25, count 0 2006.201.12:28:37.62#ibcon#end of sib2, iclass 25, count 0 2006.201.12:28:37.62#ibcon#*after write, iclass 25, count 0 2006.201.12:28:37.62#ibcon#*before return 0, iclass 25, count 0 2006.201.12:28:37.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:28:37.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:28:37.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:28:37.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:28:37.62$vck44/vb=4,5 2006.201.12:28:37.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.12:28:37.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.12:28:37.62#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:37.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:28:37.64#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:28:37.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:28:37.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:28:37.67#ibcon#enter wrdev, iclass 29, count 2 2006.201.12:28:37.67#ibcon#first serial, iclass 29, count 2 2006.201.12:28:37.67#ibcon#enter sib2, iclass 29, count 2 2006.201.12:28:37.67#ibcon#flushed, iclass 29, count 2 2006.201.12:28:37.67#ibcon#about to write, iclass 29, count 2 2006.201.12:28:37.67#ibcon#wrote, iclass 29, count 2 2006.201.12:28:37.67#ibcon#about to read 3, iclass 29, count 2 2006.201.12:28:37.69#ibcon#read 3, iclass 29, count 2 2006.201.12:28:37.69#ibcon#about to read 4, iclass 29, count 2 2006.201.12:28:37.69#ibcon#read 4, iclass 29, count 2 2006.201.12:28:37.69#ibcon#about to read 5, iclass 29, count 2 2006.201.12:28:37.69#ibcon#read 5, iclass 29, count 2 2006.201.12:28:37.69#ibcon#about to read 6, iclass 29, count 2 2006.201.12:28:37.69#ibcon#read 6, iclass 29, count 2 2006.201.12:28:37.69#ibcon#end of sib2, iclass 29, count 2 2006.201.12:28:37.69#ibcon#*mode == 0, iclass 29, count 2 2006.201.12:28:37.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.12:28:37.69#ibcon#[27=AT04-05\r\n] 2006.201.12:28:37.69#ibcon#*before write, iclass 29, count 2 2006.201.12:28:37.69#ibcon#enter sib2, iclass 29, count 2 2006.201.12:28:37.69#ibcon#flushed, iclass 29, count 2 2006.201.12:28:37.69#ibcon#about to write, iclass 29, count 2 2006.201.12:28:37.69#ibcon#wrote, iclass 29, count 2 2006.201.12:28:37.69#ibcon#about to read 3, iclass 29, count 2 2006.201.12:28:37.72#ibcon#read 3, iclass 29, count 2 2006.201.12:28:37.72#ibcon#about to read 4, iclass 29, count 2 2006.201.12:28:37.72#ibcon#read 4, iclass 29, count 2 2006.201.12:28:37.72#ibcon#about to read 5, iclass 29, count 2 2006.201.12:28:37.72#ibcon#read 5, iclass 29, count 2 2006.201.12:28:37.72#ibcon#about to read 6, iclass 29, count 2 2006.201.12:28:37.72#ibcon#read 6, iclass 29, count 2 2006.201.12:28:37.72#ibcon#end of sib2, iclass 29, count 2 2006.201.12:28:37.72#ibcon#*after write, iclass 29, count 2 2006.201.12:28:37.72#ibcon#*before return 0, iclass 29, count 2 2006.201.12:28:37.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:28:37.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:28:37.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.12:28:37.72#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:37.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:28:37.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:28:37.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:28:37.84#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:28:37.84#ibcon#first serial, iclass 29, count 0 2006.201.12:28:37.84#ibcon#enter sib2, iclass 29, count 0 2006.201.12:28:37.84#ibcon#flushed, iclass 29, count 0 2006.201.12:28:37.84#ibcon#about to write, iclass 29, count 0 2006.201.12:28:37.84#ibcon#wrote, iclass 29, count 0 2006.201.12:28:37.84#ibcon#about to read 3, iclass 29, count 0 2006.201.12:28:37.86#ibcon#read 3, iclass 29, count 0 2006.201.12:28:37.86#ibcon#about to read 4, iclass 29, count 0 2006.201.12:28:37.86#ibcon#read 4, iclass 29, count 0 2006.201.12:28:37.86#ibcon#about to read 5, iclass 29, count 0 2006.201.12:28:37.86#ibcon#read 5, iclass 29, count 0 2006.201.12:28:37.86#ibcon#about to read 6, iclass 29, count 0 2006.201.12:28:37.86#ibcon#read 6, iclass 29, count 0 2006.201.12:28:37.86#ibcon#end of sib2, iclass 29, count 0 2006.201.12:28:37.86#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:28:37.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:28:37.86#ibcon#[27=USB\r\n] 2006.201.12:28:37.86#ibcon#*before write, iclass 29, count 0 2006.201.12:28:37.86#ibcon#enter sib2, iclass 29, count 0 2006.201.12:28:37.86#ibcon#flushed, iclass 29, count 0 2006.201.12:28:37.86#ibcon#about to write, iclass 29, count 0 2006.201.12:28:37.86#ibcon#wrote, iclass 29, count 0 2006.201.12:28:37.86#ibcon#about to read 3, iclass 29, count 0 2006.201.12:28:37.89#ibcon#read 3, iclass 29, count 0 2006.201.12:28:37.89#ibcon#about to read 4, iclass 29, count 0 2006.201.12:28:37.89#ibcon#read 4, iclass 29, count 0 2006.201.12:28:37.89#ibcon#about to read 5, iclass 29, count 0 2006.201.12:28:37.89#ibcon#read 5, iclass 29, count 0 2006.201.12:28:37.89#ibcon#about to read 6, iclass 29, count 0 2006.201.12:28:37.89#ibcon#read 6, iclass 29, count 0 2006.201.12:28:37.89#ibcon#end of sib2, iclass 29, count 0 2006.201.12:28:37.89#ibcon#*after write, iclass 29, count 0 2006.201.12:28:37.89#ibcon#*before return 0, iclass 29, count 0 2006.201.12:28:37.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:28:37.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:28:37.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:28:37.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:28:37.89$vck44/vblo=5,709.99 2006.201.12:28:37.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.12:28:37.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.12:28:37.89#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:37.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:37.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:37.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:37.89#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:28:37.89#ibcon#first serial, iclass 32, count 0 2006.201.12:28:37.89#ibcon#enter sib2, iclass 32, count 0 2006.201.12:28:37.89#ibcon#flushed, iclass 32, count 0 2006.201.12:28:37.89#ibcon#about to write, iclass 32, count 0 2006.201.12:28:37.89#ibcon#wrote, iclass 32, count 0 2006.201.12:28:37.89#ibcon#about to read 3, iclass 32, count 0 2006.201.12:28:37.91#ibcon#read 3, iclass 32, count 0 2006.201.12:28:37.91#ibcon#about to read 4, iclass 32, count 0 2006.201.12:28:37.91#ibcon#read 4, iclass 32, count 0 2006.201.12:28:37.91#ibcon#about to read 5, iclass 32, count 0 2006.201.12:28:37.91#ibcon#read 5, iclass 32, count 0 2006.201.12:28:37.91#ibcon#about to read 6, iclass 32, count 0 2006.201.12:28:37.91#ibcon#read 6, iclass 32, count 0 2006.201.12:28:37.91#ibcon#end of sib2, iclass 32, count 0 2006.201.12:28:37.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:28:37.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:28:37.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:28:37.91#ibcon#*before write, iclass 32, count 0 2006.201.12:28:37.91#ibcon#enter sib2, iclass 32, count 0 2006.201.12:28:37.91#ibcon#flushed, iclass 32, count 0 2006.201.12:28:37.91#ibcon#about to write, iclass 32, count 0 2006.201.12:28:37.91#ibcon#wrote, iclass 32, count 0 2006.201.12:28:37.91#ibcon#about to read 3, iclass 32, count 0 2006.201.12:28:37.95#ibcon#read 3, iclass 32, count 0 2006.201.12:28:37.95#ibcon#about to read 4, iclass 32, count 0 2006.201.12:28:37.95#ibcon#read 4, iclass 32, count 0 2006.201.12:28:37.95#ibcon#about to read 5, iclass 32, count 0 2006.201.12:28:37.95#ibcon#read 5, iclass 32, count 0 2006.201.12:28:37.95#ibcon#about to read 6, iclass 32, count 0 2006.201.12:28:37.95#ibcon#read 6, iclass 32, count 0 2006.201.12:28:37.95#ibcon#end of sib2, iclass 32, count 0 2006.201.12:28:37.95#ibcon#*after write, iclass 32, count 0 2006.201.12:28:37.95#ibcon#*before return 0, iclass 32, count 0 2006.201.12:28:37.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:37.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:28:37.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:28:37.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:28:37.95$vck44/vb=5,4 2006.201.12:28:37.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.12:28:37.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.12:28:37.95#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:37.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:38.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:38.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:38.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.12:28:38.01#ibcon#first serial, iclass 34, count 2 2006.201.12:28:38.01#ibcon#enter sib2, iclass 34, count 2 2006.201.12:28:38.01#ibcon#flushed, iclass 34, count 2 2006.201.12:28:38.01#ibcon#about to write, iclass 34, count 2 2006.201.12:28:38.01#ibcon#wrote, iclass 34, count 2 2006.201.12:28:38.01#ibcon#about to read 3, iclass 34, count 2 2006.201.12:28:38.03#ibcon#read 3, iclass 34, count 2 2006.201.12:28:38.03#ibcon#about to read 4, iclass 34, count 2 2006.201.12:28:38.03#ibcon#read 4, iclass 34, count 2 2006.201.12:28:38.03#ibcon#about to read 5, iclass 34, count 2 2006.201.12:28:38.03#ibcon#read 5, iclass 34, count 2 2006.201.12:28:38.03#ibcon#about to read 6, iclass 34, count 2 2006.201.12:28:38.03#ibcon#read 6, iclass 34, count 2 2006.201.12:28:38.03#ibcon#end of sib2, iclass 34, count 2 2006.201.12:28:38.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.12:28:38.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.12:28:38.03#ibcon#[27=AT05-04\r\n] 2006.201.12:28:38.03#ibcon#*before write, iclass 34, count 2 2006.201.12:28:38.03#ibcon#enter sib2, iclass 34, count 2 2006.201.12:28:38.03#ibcon#flushed, iclass 34, count 2 2006.201.12:28:38.03#ibcon#about to write, iclass 34, count 2 2006.201.12:28:38.03#ibcon#wrote, iclass 34, count 2 2006.201.12:28:38.03#ibcon#about to read 3, iclass 34, count 2 2006.201.12:28:38.06#ibcon#read 3, iclass 34, count 2 2006.201.12:28:38.06#ibcon#about to read 4, iclass 34, count 2 2006.201.12:28:38.06#ibcon#read 4, iclass 34, count 2 2006.201.12:28:38.06#ibcon#about to read 5, iclass 34, count 2 2006.201.12:28:38.06#ibcon#read 5, iclass 34, count 2 2006.201.12:28:38.06#ibcon#about to read 6, iclass 34, count 2 2006.201.12:28:38.06#ibcon#read 6, iclass 34, count 2 2006.201.12:28:38.06#ibcon#end of sib2, iclass 34, count 2 2006.201.12:28:38.06#ibcon#*after write, iclass 34, count 2 2006.201.12:28:38.06#ibcon#*before return 0, iclass 34, count 2 2006.201.12:28:38.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:38.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:28:38.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.12:28:38.06#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:38.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:38.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:38.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:38.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:28:38.18#ibcon#first serial, iclass 34, count 0 2006.201.12:28:38.18#ibcon#enter sib2, iclass 34, count 0 2006.201.12:28:38.18#ibcon#flushed, iclass 34, count 0 2006.201.12:28:38.18#ibcon#about to write, iclass 34, count 0 2006.201.12:28:38.18#ibcon#wrote, iclass 34, count 0 2006.201.12:28:38.18#ibcon#about to read 3, iclass 34, count 0 2006.201.12:28:38.21#ibcon#read 3, iclass 34, count 0 2006.201.12:28:38.21#ibcon#about to read 4, iclass 34, count 0 2006.201.12:28:38.21#ibcon#read 4, iclass 34, count 0 2006.201.12:28:38.21#ibcon#about to read 5, iclass 34, count 0 2006.201.12:28:38.21#ibcon#read 5, iclass 34, count 0 2006.201.12:28:38.21#ibcon#about to read 6, iclass 34, count 0 2006.201.12:28:38.21#ibcon#read 6, iclass 34, count 0 2006.201.12:28:38.21#ibcon#end of sib2, iclass 34, count 0 2006.201.12:28:38.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:28:38.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:28:38.21#ibcon#[27=USB\r\n] 2006.201.12:28:38.21#ibcon#*before write, iclass 34, count 0 2006.201.12:28:38.21#ibcon#enter sib2, iclass 34, count 0 2006.201.12:28:38.21#ibcon#flushed, iclass 34, count 0 2006.201.12:28:38.21#ibcon#about to write, iclass 34, count 0 2006.201.12:28:38.21#ibcon#wrote, iclass 34, count 0 2006.201.12:28:38.21#ibcon#about to read 3, iclass 34, count 0 2006.201.12:28:38.24#ibcon#read 3, iclass 34, count 0 2006.201.12:28:38.24#ibcon#about to read 4, iclass 34, count 0 2006.201.12:28:38.24#ibcon#read 4, iclass 34, count 0 2006.201.12:28:38.24#ibcon#about to read 5, iclass 34, count 0 2006.201.12:28:38.24#ibcon#read 5, iclass 34, count 0 2006.201.12:28:38.24#ibcon#about to read 6, iclass 34, count 0 2006.201.12:28:38.24#ibcon#read 6, iclass 34, count 0 2006.201.12:28:38.24#ibcon#end of sib2, iclass 34, count 0 2006.201.12:28:38.24#ibcon#*after write, iclass 34, count 0 2006.201.12:28:38.24#ibcon#*before return 0, iclass 34, count 0 2006.201.12:28:38.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:38.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:28:38.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:28:38.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:28:38.24$vck44/vblo=6,719.99 2006.201.12:28:38.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.12:28:38.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.12:28:38.24#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:38.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:38.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:38.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:38.24#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:28:38.24#ibcon#first serial, iclass 36, count 0 2006.201.12:28:38.24#ibcon#enter sib2, iclass 36, count 0 2006.201.12:28:38.24#ibcon#flushed, iclass 36, count 0 2006.201.12:28:38.24#ibcon#about to write, iclass 36, count 0 2006.201.12:28:38.24#ibcon#wrote, iclass 36, count 0 2006.201.12:28:38.24#ibcon#about to read 3, iclass 36, count 0 2006.201.12:28:38.26#ibcon#read 3, iclass 36, count 0 2006.201.12:28:38.26#ibcon#about to read 4, iclass 36, count 0 2006.201.12:28:38.26#ibcon#read 4, iclass 36, count 0 2006.201.12:28:38.26#ibcon#about to read 5, iclass 36, count 0 2006.201.12:28:38.26#ibcon#read 5, iclass 36, count 0 2006.201.12:28:38.26#ibcon#about to read 6, iclass 36, count 0 2006.201.12:28:38.26#ibcon#read 6, iclass 36, count 0 2006.201.12:28:38.26#ibcon#end of sib2, iclass 36, count 0 2006.201.12:28:38.26#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:28:38.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:28:38.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:28:38.26#ibcon#*before write, iclass 36, count 0 2006.201.12:28:38.26#ibcon#enter sib2, iclass 36, count 0 2006.201.12:28:38.26#ibcon#flushed, iclass 36, count 0 2006.201.12:28:38.26#ibcon#about to write, iclass 36, count 0 2006.201.12:28:38.26#ibcon#wrote, iclass 36, count 0 2006.201.12:28:38.26#ibcon#about to read 3, iclass 36, count 0 2006.201.12:28:38.30#ibcon#read 3, iclass 36, count 0 2006.201.12:28:38.30#ibcon#about to read 4, iclass 36, count 0 2006.201.12:28:38.30#ibcon#read 4, iclass 36, count 0 2006.201.12:28:38.30#ibcon#about to read 5, iclass 36, count 0 2006.201.12:28:38.30#ibcon#read 5, iclass 36, count 0 2006.201.12:28:38.30#ibcon#about to read 6, iclass 36, count 0 2006.201.12:28:38.30#ibcon#read 6, iclass 36, count 0 2006.201.12:28:38.30#ibcon#end of sib2, iclass 36, count 0 2006.201.12:28:38.30#ibcon#*after write, iclass 36, count 0 2006.201.12:28:38.30#ibcon#*before return 0, iclass 36, count 0 2006.201.12:28:38.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:38.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:28:38.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:28:38.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:28:38.30$vck44/vb=6,4 2006.201.12:28:38.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.12:28:38.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.12:28:38.30#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:38.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:38.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:38.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:38.36#ibcon#enter wrdev, iclass 38, count 2 2006.201.12:28:38.36#ibcon#first serial, iclass 38, count 2 2006.201.12:28:38.36#ibcon#enter sib2, iclass 38, count 2 2006.201.12:28:38.36#ibcon#flushed, iclass 38, count 2 2006.201.12:28:38.36#ibcon#about to write, iclass 38, count 2 2006.201.12:28:38.36#ibcon#wrote, iclass 38, count 2 2006.201.12:28:38.36#ibcon#about to read 3, iclass 38, count 2 2006.201.12:28:38.38#ibcon#read 3, iclass 38, count 2 2006.201.12:28:38.38#ibcon#about to read 4, iclass 38, count 2 2006.201.12:28:38.38#ibcon#read 4, iclass 38, count 2 2006.201.12:28:38.38#ibcon#about to read 5, iclass 38, count 2 2006.201.12:28:38.38#ibcon#read 5, iclass 38, count 2 2006.201.12:28:38.38#ibcon#about to read 6, iclass 38, count 2 2006.201.12:28:38.38#ibcon#read 6, iclass 38, count 2 2006.201.12:28:38.38#ibcon#end of sib2, iclass 38, count 2 2006.201.12:28:38.38#ibcon#*mode == 0, iclass 38, count 2 2006.201.12:28:38.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.12:28:38.38#ibcon#[27=AT06-04\r\n] 2006.201.12:28:38.38#ibcon#*before write, iclass 38, count 2 2006.201.12:28:38.38#ibcon#enter sib2, iclass 38, count 2 2006.201.12:28:38.38#ibcon#flushed, iclass 38, count 2 2006.201.12:28:38.38#ibcon#about to write, iclass 38, count 2 2006.201.12:28:38.38#ibcon#wrote, iclass 38, count 2 2006.201.12:28:38.38#ibcon#about to read 3, iclass 38, count 2 2006.201.12:28:38.41#ibcon#read 3, iclass 38, count 2 2006.201.12:28:38.41#ibcon#about to read 4, iclass 38, count 2 2006.201.12:28:38.41#ibcon#read 4, iclass 38, count 2 2006.201.12:28:38.41#ibcon#about to read 5, iclass 38, count 2 2006.201.12:28:38.41#ibcon#read 5, iclass 38, count 2 2006.201.12:28:38.41#ibcon#about to read 6, iclass 38, count 2 2006.201.12:28:38.41#ibcon#read 6, iclass 38, count 2 2006.201.12:28:38.41#ibcon#end of sib2, iclass 38, count 2 2006.201.12:28:38.41#ibcon#*after write, iclass 38, count 2 2006.201.12:28:38.41#ibcon#*before return 0, iclass 38, count 2 2006.201.12:28:38.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:38.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:28:38.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.12:28:38.41#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:38.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:38.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:38.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:38.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:28:38.53#ibcon#first serial, iclass 38, count 0 2006.201.12:28:38.53#ibcon#enter sib2, iclass 38, count 0 2006.201.12:28:38.53#ibcon#flushed, iclass 38, count 0 2006.201.12:28:38.53#ibcon#about to write, iclass 38, count 0 2006.201.12:28:38.53#ibcon#wrote, iclass 38, count 0 2006.201.12:28:38.53#ibcon#about to read 3, iclass 38, count 0 2006.201.12:28:38.55#ibcon#read 3, iclass 38, count 0 2006.201.12:28:38.55#ibcon#about to read 4, iclass 38, count 0 2006.201.12:28:38.55#ibcon#read 4, iclass 38, count 0 2006.201.12:28:38.55#ibcon#about to read 5, iclass 38, count 0 2006.201.12:28:38.55#ibcon#read 5, iclass 38, count 0 2006.201.12:28:38.55#ibcon#about to read 6, iclass 38, count 0 2006.201.12:28:38.55#ibcon#read 6, iclass 38, count 0 2006.201.12:28:38.55#ibcon#end of sib2, iclass 38, count 0 2006.201.12:28:38.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:28:38.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:28:38.55#ibcon#[27=USB\r\n] 2006.201.12:28:38.55#ibcon#*before write, iclass 38, count 0 2006.201.12:28:38.55#ibcon#enter sib2, iclass 38, count 0 2006.201.12:28:38.55#ibcon#flushed, iclass 38, count 0 2006.201.12:28:38.55#ibcon#about to write, iclass 38, count 0 2006.201.12:28:38.55#ibcon#wrote, iclass 38, count 0 2006.201.12:28:38.55#ibcon#about to read 3, iclass 38, count 0 2006.201.12:28:38.58#ibcon#read 3, iclass 38, count 0 2006.201.12:28:38.58#ibcon#about to read 4, iclass 38, count 0 2006.201.12:28:38.58#ibcon#read 4, iclass 38, count 0 2006.201.12:28:38.58#ibcon#about to read 5, iclass 38, count 0 2006.201.12:28:38.58#ibcon#read 5, iclass 38, count 0 2006.201.12:28:38.58#ibcon#about to read 6, iclass 38, count 0 2006.201.12:28:38.58#ibcon#read 6, iclass 38, count 0 2006.201.12:28:38.58#ibcon#end of sib2, iclass 38, count 0 2006.201.12:28:38.58#ibcon#*after write, iclass 38, count 0 2006.201.12:28:38.58#ibcon#*before return 0, iclass 38, count 0 2006.201.12:28:38.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:38.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:28:38.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:28:38.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:28:38.58$vck44/vblo=7,734.99 2006.201.12:28:38.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.12:28:38.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.12:28:38.58#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:38.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:38.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:38.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:38.58#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:28:38.58#ibcon#first serial, iclass 40, count 0 2006.201.12:28:38.58#ibcon#enter sib2, iclass 40, count 0 2006.201.12:28:38.58#ibcon#flushed, iclass 40, count 0 2006.201.12:28:38.58#ibcon#about to write, iclass 40, count 0 2006.201.12:28:38.58#ibcon#wrote, iclass 40, count 0 2006.201.12:28:38.58#ibcon#about to read 3, iclass 40, count 0 2006.201.12:28:38.60#ibcon#read 3, iclass 40, count 0 2006.201.12:28:38.60#ibcon#about to read 4, iclass 40, count 0 2006.201.12:28:38.60#ibcon#read 4, iclass 40, count 0 2006.201.12:28:38.60#ibcon#about to read 5, iclass 40, count 0 2006.201.12:28:38.60#ibcon#read 5, iclass 40, count 0 2006.201.12:28:38.60#ibcon#about to read 6, iclass 40, count 0 2006.201.12:28:38.60#ibcon#read 6, iclass 40, count 0 2006.201.12:28:38.60#ibcon#end of sib2, iclass 40, count 0 2006.201.12:28:38.60#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:28:38.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:28:38.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:28:38.60#ibcon#*before write, iclass 40, count 0 2006.201.12:28:38.60#ibcon#enter sib2, iclass 40, count 0 2006.201.12:28:38.60#ibcon#flushed, iclass 40, count 0 2006.201.12:28:38.60#ibcon#about to write, iclass 40, count 0 2006.201.12:28:38.60#ibcon#wrote, iclass 40, count 0 2006.201.12:28:38.60#ibcon#about to read 3, iclass 40, count 0 2006.201.12:28:38.64#ibcon#read 3, iclass 40, count 0 2006.201.12:28:38.64#ibcon#about to read 4, iclass 40, count 0 2006.201.12:28:38.64#ibcon#read 4, iclass 40, count 0 2006.201.12:28:38.64#ibcon#about to read 5, iclass 40, count 0 2006.201.12:28:38.64#ibcon#read 5, iclass 40, count 0 2006.201.12:28:38.64#ibcon#about to read 6, iclass 40, count 0 2006.201.12:28:38.64#ibcon#read 6, iclass 40, count 0 2006.201.12:28:38.64#ibcon#end of sib2, iclass 40, count 0 2006.201.12:28:38.64#ibcon#*after write, iclass 40, count 0 2006.201.12:28:38.64#ibcon#*before return 0, iclass 40, count 0 2006.201.12:28:38.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:38.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:28:38.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:28:38.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:28:38.64$vck44/vb=7,4 2006.201.12:28:38.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.12:28:38.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.12:28:38.64#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:38.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:38.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:38.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:38.70#ibcon#enter wrdev, iclass 4, count 2 2006.201.12:28:38.70#ibcon#first serial, iclass 4, count 2 2006.201.12:28:38.70#ibcon#enter sib2, iclass 4, count 2 2006.201.12:28:38.70#ibcon#flushed, iclass 4, count 2 2006.201.12:28:38.70#ibcon#about to write, iclass 4, count 2 2006.201.12:28:38.70#ibcon#wrote, iclass 4, count 2 2006.201.12:28:38.70#ibcon#about to read 3, iclass 4, count 2 2006.201.12:28:38.72#ibcon#read 3, iclass 4, count 2 2006.201.12:28:38.72#ibcon#about to read 4, iclass 4, count 2 2006.201.12:28:38.72#ibcon#read 4, iclass 4, count 2 2006.201.12:28:38.72#ibcon#about to read 5, iclass 4, count 2 2006.201.12:28:38.72#ibcon#read 5, iclass 4, count 2 2006.201.12:28:38.72#ibcon#about to read 6, iclass 4, count 2 2006.201.12:28:38.72#ibcon#read 6, iclass 4, count 2 2006.201.12:28:38.72#ibcon#end of sib2, iclass 4, count 2 2006.201.12:28:38.72#ibcon#*mode == 0, iclass 4, count 2 2006.201.12:28:38.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.12:28:38.72#ibcon#[27=AT07-04\r\n] 2006.201.12:28:38.72#ibcon#*before write, iclass 4, count 2 2006.201.12:28:38.72#ibcon#enter sib2, iclass 4, count 2 2006.201.12:28:38.72#ibcon#flushed, iclass 4, count 2 2006.201.12:28:38.72#ibcon#about to write, iclass 4, count 2 2006.201.12:28:38.72#ibcon#wrote, iclass 4, count 2 2006.201.12:28:38.72#ibcon#about to read 3, iclass 4, count 2 2006.201.12:28:38.75#ibcon#read 3, iclass 4, count 2 2006.201.12:28:38.75#ibcon#about to read 4, iclass 4, count 2 2006.201.12:28:38.75#ibcon#read 4, iclass 4, count 2 2006.201.12:28:38.75#ibcon#about to read 5, iclass 4, count 2 2006.201.12:28:38.75#ibcon#read 5, iclass 4, count 2 2006.201.12:28:38.75#ibcon#about to read 6, iclass 4, count 2 2006.201.12:28:38.75#ibcon#read 6, iclass 4, count 2 2006.201.12:28:38.75#ibcon#end of sib2, iclass 4, count 2 2006.201.12:28:38.75#ibcon#*after write, iclass 4, count 2 2006.201.12:28:38.75#ibcon#*before return 0, iclass 4, count 2 2006.201.12:28:38.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:38.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:28:38.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.12:28:38.75#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:38.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:38.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:38.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:38.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:28:38.87#ibcon#first serial, iclass 4, count 0 2006.201.12:28:38.87#ibcon#enter sib2, iclass 4, count 0 2006.201.12:28:38.87#ibcon#flushed, iclass 4, count 0 2006.201.12:28:38.87#ibcon#about to write, iclass 4, count 0 2006.201.12:28:38.87#ibcon#wrote, iclass 4, count 0 2006.201.12:28:38.87#ibcon#about to read 3, iclass 4, count 0 2006.201.12:28:38.89#ibcon#read 3, iclass 4, count 0 2006.201.12:28:38.89#ibcon#about to read 4, iclass 4, count 0 2006.201.12:28:38.89#ibcon#read 4, iclass 4, count 0 2006.201.12:28:38.89#ibcon#about to read 5, iclass 4, count 0 2006.201.12:28:38.89#ibcon#read 5, iclass 4, count 0 2006.201.12:28:38.89#ibcon#about to read 6, iclass 4, count 0 2006.201.12:28:38.89#ibcon#read 6, iclass 4, count 0 2006.201.12:28:38.89#ibcon#end of sib2, iclass 4, count 0 2006.201.12:28:38.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:28:38.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:28:38.89#ibcon#[27=USB\r\n] 2006.201.12:28:38.89#ibcon#*before write, iclass 4, count 0 2006.201.12:28:38.89#ibcon#enter sib2, iclass 4, count 0 2006.201.12:28:38.89#ibcon#flushed, iclass 4, count 0 2006.201.12:28:38.89#ibcon#about to write, iclass 4, count 0 2006.201.12:28:38.89#ibcon#wrote, iclass 4, count 0 2006.201.12:28:38.89#ibcon#about to read 3, iclass 4, count 0 2006.201.12:28:38.92#ibcon#read 3, iclass 4, count 0 2006.201.12:28:38.92#ibcon#about to read 4, iclass 4, count 0 2006.201.12:28:38.92#ibcon#read 4, iclass 4, count 0 2006.201.12:28:38.92#ibcon#about to read 5, iclass 4, count 0 2006.201.12:28:38.92#ibcon#read 5, iclass 4, count 0 2006.201.12:28:38.92#ibcon#about to read 6, iclass 4, count 0 2006.201.12:28:38.92#ibcon#read 6, iclass 4, count 0 2006.201.12:28:38.92#ibcon#end of sib2, iclass 4, count 0 2006.201.12:28:38.92#ibcon#*after write, iclass 4, count 0 2006.201.12:28:38.92#ibcon#*before return 0, iclass 4, count 0 2006.201.12:28:38.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:38.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:28:38.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:28:38.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:28:38.92$vck44/vblo=8,744.99 2006.201.12:28:38.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.12:28:38.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.12:28:38.92#ibcon#ireg 17 cls_cnt 0 2006.201.12:28:38.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:38.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:38.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:38.92#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:28:38.92#ibcon#first serial, iclass 6, count 0 2006.201.12:28:38.92#ibcon#enter sib2, iclass 6, count 0 2006.201.12:28:38.92#ibcon#flushed, iclass 6, count 0 2006.201.12:28:38.92#ibcon#about to write, iclass 6, count 0 2006.201.12:28:38.92#ibcon#wrote, iclass 6, count 0 2006.201.12:28:38.92#ibcon#about to read 3, iclass 6, count 0 2006.201.12:28:38.94#ibcon#read 3, iclass 6, count 0 2006.201.12:28:38.94#ibcon#about to read 4, iclass 6, count 0 2006.201.12:28:38.94#ibcon#read 4, iclass 6, count 0 2006.201.12:28:38.94#ibcon#about to read 5, iclass 6, count 0 2006.201.12:28:38.94#ibcon#read 5, iclass 6, count 0 2006.201.12:28:38.94#ibcon#about to read 6, iclass 6, count 0 2006.201.12:28:38.94#ibcon#read 6, iclass 6, count 0 2006.201.12:28:38.94#ibcon#end of sib2, iclass 6, count 0 2006.201.12:28:38.94#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:28:38.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:28:38.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:28:38.94#ibcon#*before write, iclass 6, count 0 2006.201.12:28:38.94#ibcon#enter sib2, iclass 6, count 0 2006.201.12:28:38.94#ibcon#flushed, iclass 6, count 0 2006.201.12:28:38.94#ibcon#about to write, iclass 6, count 0 2006.201.12:28:38.94#ibcon#wrote, iclass 6, count 0 2006.201.12:28:38.94#ibcon#about to read 3, iclass 6, count 0 2006.201.12:28:38.98#ibcon#read 3, iclass 6, count 0 2006.201.12:28:38.98#ibcon#about to read 4, iclass 6, count 0 2006.201.12:28:38.98#ibcon#read 4, iclass 6, count 0 2006.201.12:28:38.98#ibcon#about to read 5, iclass 6, count 0 2006.201.12:28:38.98#ibcon#read 5, iclass 6, count 0 2006.201.12:28:38.98#ibcon#about to read 6, iclass 6, count 0 2006.201.12:28:38.98#ibcon#read 6, iclass 6, count 0 2006.201.12:28:38.98#ibcon#end of sib2, iclass 6, count 0 2006.201.12:28:38.98#ibcon#*after write, iclass 6, count 0 2006.201.12:28:38.98#ibcon#*before return 0, iclass 6, count 0 2006.201.12:28:38.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:38.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:28:38.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:28:38.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:28:38.98$vck44/vb=8,4 2006.201.12:28:38.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.12:28:38.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.12:28:38.98#ibcon#ireg 11 cls_cnt 2 2006.201.12:28:38.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:39.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:39.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:39.04#ibcon#enter wrdev, iclass 10, count 2 2006.201.12:28:39.04#ibcon#first serial, iclass 10, count 2 2006.201.12:28:39.04#ibcon#enter sib2, iclass 10, count 2 2006.201.12:28:39.04#ibcon#flushed, iclass 10, count 2 2006.201.12:28:39.04#ibcon#about to write, iclass 10, count 2 2006.201.12:28:39.04#ibcon#wrote, iclass 10, count 2 2006.201.12:28:39.04#ibcon#about to read 3, iclass 10, count 2 2006.201.12:28:39.06#ibcon#read 3, iclass 10, count 2 2006.201.12:28:39.06#ibcon#about to read 4, iclass 10, count 2 2006.201.12:28:39.06#ibcon#read 4, iclass 10, count 2 2006.201.12:28:39.06#ibcon#about to read 5, iclass 10, count 2 2006.201.12:28:39.06#ibcon#read 5, iclass 10, count 2 2006.201.12:28:39.06#ibcon#about to read 6, iclass 10, count 2 2006.201.12:28:39.06#ibcon#read 6, iclass 10, count 2 2006.201.12:28:39.06#ibcon#end of sib2, iclass 10, count 2 2006.201.12:28:39.06#ibcon#*mode == 0, iclass 10, count 2 2006.201.12:28:39.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.12:28:39.06#ibcon#[27=AT08-04\r\n] 2006.201.12:28:39.06#ibcon#*before write, iclass 10, count 2 2006.201.12:28:39.06#ibcon#enter sib2, iclass 10, count 2 2006.201.12:28:39.06#ibcon#flushed, iclass 10, count 2 2006.201.12:28:39.06#ibcon#about to write, iclass 10, count 2 2006.201.12:28:39.06#ibcon#wrote, iclass 10, count 2 2006.201.12:28:39.06#ibcon#about to read 3, iclass 10, count 2 2006.201.12:28:39.09#ibcon#read 3, iclass 10, count 2 2006.201.12:28:39.09#ibcon#about to read 4, iclass 10, count 2 2006.201.12:28:39.09#ibcon#read 4, iclass 10, count 2 2006.201.12:28:39.09#ibcon#about to read 5, iclass 10, count 2 2006.201.12:28:39.09#ibcon#read 5, iclass 10, count 2 2006.201.12:28:39.09#ibcon#about to read 6, iclass 10, count 2 2006.201.12:28:39.09#ibcon#read 6, iclass 10, count 2 2006.201.12:28:39.09#ibcon#end of sib2, iclass 10, count 2 2006.201.12:28:39.09#ibcon#*after write, iclass 10, count 2 2006.201.12:28:39.09#ibcon#*before return 0, iclass 10, count 2 2006.201.12:28:39.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:39.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:28:39.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.12:28:39.09#ibcon#ireg 7 cls_cnt 0 2006.201.12:28:39.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:39.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:39.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:39.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.12:28:39.21#ibcon#first serial, iclass 10, count 0 2006.201.12:28:39.21#ibcon#enter sib2, iclass 10, count 0 2006.201.12:28:39.21#ibcon#flushed, iclass 10, count 0 2006.201.12:28:39.21#ibcon#about to write, iclass 10, count 0 2006.201.12:28:39.21#ibcon#wrote, iclass 10, count 0 2006.201.12:28:39.21#ibcon#about to read 3, iclass 10, count 0 2006.201.12:28:39.23#ibcon#read 3, iclass 10, count 0 2006.201.12:28:39.23#ibcon#about to read 4, iclass 10, count 0 2006.201.12:28:39.23#ibcon#read 4, iclass 10, count 0 2006.201.12:28:39.23#ibcon#about to read 5, iclass 10, count 0 2006.201.12:28:39.23#ibcon#read 5, iclass 10, count 0 2006.201.12:28:39.23#ibcon#about to read 6, iclass 10, count 0 2006.201.12:28:39.23#ibcon#read 6, iclass 10, count 0 2006.201.12:28:39.23#ibcon#end of sib2, iclass 10, count 0 2006.201.12:28:39.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.12:28:39.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.12:28:39.23#ibcon#[27=USB\r\n] 2006.201.12:28:39.23#ibcon#*before write, iclass 10, count 0 2006.201.12:28:39.23#ibcon#enter sib2, iclass 10, count 0 2006.201.12:28:39.23#ibcon#flushed, iclass 10, count 0 2006.201.12:28:39.23#ibcon#about to write, iclass 10, count 0 2006.201.12:28:39.23#ibcon#wrote, iclass 10, count 0 2006.201.12:28:39.23#ibcon#about to read 3, iclass 10, count 0 2006.201.12:28:39.26#ibcon#read 3, iclass 10, count 0 2006.201.12:28:39.26#ibcon#about to read 4, iclass 10, count 0 2006.201.12:28:39.26#ibcon#read 4, iclass 10, count 0 2006.201.12:28:39.26#ibcon#about to read 5, iclass 10, count 0 2006.201.12:28:39.26#ibcon#read 5, iclass 10, count 0 2006.201.12:28:39.26#ibcon#about to read 6, iclass 10, count 0 2006.201.12:28:39.26#ibcon#read 6, iclass 10, count 0 2006.201.12:28:39.26#ibcon#end of sib2, iclass 10, count 0 2006.201.12:28:39.26#ibcon#*after write, iclass 10, count 0 2006.201.12:28:39.26#ibcon#*before return 0, iclass 10, count 0 2006.201.12:28:39.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:39.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:28:39.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.12:28:39.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.12:28:39.26$vck44/vabw=wide 2006.201.12:28:39.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.12:28:39.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.12:28:39.26#ibcon#ireg 8 cls_cnt 0 2006.201.12:28:39.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:39.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:39.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:39.26#ibcon#enter wrdev, iclass 12, count 0 2006.201.12:28:39.26#ibcon#first serial, iclass 12, count 0 2006.201.12:28:39.26#ibcon#enter sib2, iclass 12, count 0 2006.201.12:28:39.26#ibcon#flushed, iclass 12, count 0 2006.201.12:28:39.26#ibcon#about to write, iclass 12, count 0 2006.201.12:28:39.26#ibcon#wrote, iclass 12, count 0 2006.201.12:28:39.26#ibcon#about to read 3, iclass 12, count 0 2006.201.12:28:39.28#ibcon#read 3, iclass 12, count 0 2006.201.12:28:39.28#ibcon#about to read 4, iclass 12, count 0 2006.201.12:28:39.28#ibcon#read 4, iclass 12, count 0 2006.201.12:28:39.28#ibcon#about to read 5, iclass 12, count 0 2006.201.12:28:39.28#ibcon#read 5, iclass 12, count 0 2006.201.12:28:39.28#ibcon#about to read 6, iclass 12, count 0 2006.201.12:28:39.28#ibcon#read 6, iclass 12, count 0 2006.201.12:28:39.28#ibcon#end of sib2, iclass 12, count 0 2006.201.12:28:39.28#ibcon#*mode == 0, iclass 12, count 0 2006.201.12:28:39.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.12:28:39.28#ibcon#[25=BW32\r\n] 2006.201.12:28:39.28#ibcon#*before write, iclass 12, count 0 2006.201.12:28:39.28#ibcon#enter sib2, iclass 12, count 0 2006.201.12:28:39.28#ibcon#flushed, iclass 12, count 0 2006.201.12:28:39.28#ibcon#about to write, iclass 12, count 0 2006.201.12:28:39.28#ibcon#wrote, iclass 12, count 0 2006.201.12:28:39.28#ibcon#about to read 3, iclass 12, count 0 2006.201.12:28:39.32#ibcon#read 3, iclass 12, count 0 2006.201.12:28:39.32#ibcon#about to read 4, iclass 12, count 0 2006.201.12:28:39.32#ibcon#read 4, iclass 12, count 0 2006.201.12:28:39.32#ibcon#about to read 5, iclass 12, count 0 2006.201.12:28:39.32#ibcon#read 5, iclass 12, count 0 2006.201.12:28:39.32#ibcon#about to read 6, iclass 12, count 0 2006.201.12:28:39.32#ibcon#read 6, iclass 12, count 0 2006.201.12:28:39.32#ibcon#end of sib2, iclass 12, count 0 2006.201.12:28:39.32#ibcon#*after write, iclass 12, count 0 2006.201.12:28:39.32#ibcon#*before return 0, iclass 12, count 0 2006.201.12:28:39.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:39.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:28:39.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.12:28:39.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.12:28:39.32$vck44/vbbw=wide 2006.201.12:28:39.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.12:28:39.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.12:28:39.32#ibcon#ireg 8 cls_cnt 0 2006.201.12:28:39.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:28:39.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:28:39.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:28:39.38#ibcon#enter wrdev, iclass 14, count 0 2006.201.12:28:39.38#ibcon#first serial, iclass 14, count 0 2006.201.12:28:39.38#ibcon#enter sib2, iclass 14, count 0 2006.201.12:28:39.38#ibcon#flushed, iclass 14, count 0 2006.201.12:28:39.38#ibcon#about to write, iclass 14, count 0 2006.201.12:28:39.38#ibcon#wrote, iclass 14, count 0 2006.201.12:28:39.38#ibcon#about to read 3, iclass 14, count 0 2006.201.12:28:39.40#ibcon#read 3, iclass 14, count 0 2006.201.12:28:39.40#ibcon#about to read 4, iclass 14, count 0 2006.201.12:28:39.40#ibcon#read 4, iclass 14, count 0 2006.201.12:28:39.40#ibcon#about to read 5, iclass 14, count 0 2006.201.12:28:39.40#ibcon#read 5, iclass 14, count 0 2006.201.12:28:39.40#ibcon#about to read 6, iclass 14, count 0 2006.201.12:28:39.40#ibcon#read 6, iclass 14, count 0 2006.201.12:28:39.40#ibcon#end of sib2, iclass 14, count 0 2006.201.12:28:39.40#ibcon#*mode == 0, iclass 14, count 0 2006.201.12:28:39.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.12:28:39.40#ibcon#[27=BW32\r\n] 2006.201.12:28:39.40#ibcon#*before write, iclass 14, count 0 2006.201.12:28:39.40#ibcon#enter sib2, iclass 14, count 0 2006.201.12:28:39.40#ibcon#flushed, iclass 14, count 0 2006.201.12:28:39.40#ibcon#about to write, iclass 14, count 0 2006.201.12:28:39.40#ibcon#wrote, iclass 14, count 0 2006.201.12:28:39.40#ibcon#about to read 3, iclass 14, count 0 2006.201.12:28:39.43#ibcon#read 3, iclass 14, count 0 2006.201.12:28:39.43#ibcon#about to read 4, iclass 14, count 0 2006.201.12:28:39.43#ibcon#read 4, iclass 14, count 0 2006.201.12:28:39.43#ibcon#about to read 5, iclass 14, count 0 2006.201.12:28:39.43#ibcon#read 5, iclass 14, count 0 2006.201.12:28:39.43#ibcon#about to read 6, iclass 14, count 0 2006.201.12:28:39.43#ibcon#read 6, iclass 14, count 0 2006.201.12:28:39.43#ibcon#end of sib2, iclass 14, count 0 2006.201.12:28:39.43#ibcon#*after write, iclass 14, count 0 2006.201.12:28:39.43#ibcon#*before return 0, iclass 14, count 0 2006.201.12:28:39.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:28:39.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.12:28:39.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.12:28:39.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.12:28:39.43$setupk4/ifdk4 2006.201.12:28:39.43$ifdk4/lo= 2006.201.12:28:39.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:28:39.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:28:39.43$ifdk4/patch= 2006.201.12:28:39.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:28:39.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:28:39.43$setupk4/!*+20s 2006.201.12:28:47.73#abcon#<5=/04 1.7 3.7 21.141001004.2\r\n> 2006.201.12:28:47.75#abcon#{5=INTERFACE CLEAR} 2006.201.12:28:47.81#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:28:53.90$setupk4/"tpicd 2006.201.12:28:53.90$setupk4/echo=off 2006.201.12:28:53.90$setupk4/xlog=off 2006.201.12:28:53.90:!2006.201.12:34:22 2006.201.12:29:14.14#trakl#Source acquired 2006.201.12:29:15.14#flagr#flagr/antenna,acquired 2006.201.12:34:22.00:preob 2006.201.12:34:22.14/onsource/TRACKING 2006.201.12:34:22.14:!2006.201.12:34:32 2006.201.12:34:32.00:"tape 2006.201.12:34:32.00:"st=record 2006.201.12:34:32.00:data_valid=on 2006.201.12:34:32.00:midob 2006.201.12:34:33.14/onsource/TRACKING 2006.201.12:34:33.14/wx/21.10,1004.0,100 2006.201.12:34:33.32/cable/+6.4716E-03 2006.201.12:34:34.41/va/01,08,usb,yes,29,31 2006.201.12:34:34.41/va/02,07,usb,yes,31,32 2006.201.12:34:34.41/va/03,08,usb,yes,28,29 2006.201.12:34:34.41/va/04,07,usb,yes,32,33 2006.201.12:34:34.41/va/05,04,usb,yes,28,29 2006.201.12:34:34.41/va/06,05,usb,yes,28,28 2006.201.12:34:34.41/va/07,05,usb,yes,27,29 2006.201.12:34:34.41/va/08,04,usb,yes,27,33 2006.201.12:34:34.64/valo/01,524.99,yes,locked 2006.201.12:34:34.64/valo/02,534.99,yes,locked 2006.201.12:34:34.64/valo/03,564.99,yes,locked 2006.201.12:34:34.64/valo/04,624.99,yes,locked 2006.201.12:34:34.64/valo/05,734.99,yes,locked 2006.201.12:34:34.64/valo/06,814.99,yes,locked 2006.201.12:34:34.64/valo/07,864.99,yes,locked 2006.201.12:34:34.64/valo/08,884.99,yes,locked 2006.201.12:34:35.73/vb/01,04,usb,yes,29,27 2006.201.12:34:35.73/vb/02,05,usb,yes,27,27 2006.201.12:34:35.73/vb/03,04,usb,yes,28,31 2006.201.12:34:35.73/vb/04,05,usb,yes,28,27 2006.201.12:34:35.73/vb/05,04,usb,yes,25,27 2006.201.12:34:35.73/vb/06,04,usb,yes,29,25 2006.201.12:34:35.73/vb/07,04,usb,yes,29,29 2006.201.12:34:35.73/vb/08,04,usb,yes,27,30 2006.201.12:34:35.96/vblo/01,629.99,yes,locked 2006.201.12:34:35.96/vblo/02,634.99,yes,locked 2006.201.12:34:35.96/vblo/03,649.99,yes,locked 2006.201.12:34:35.96/vblo/04,679.99,yes,locked 2006.201.12:34:35.96/vblo/05,709.99,yes,locked 2006.201.12:34:35.96/vblo/06,719.99,yes,locked 2006.201.12:34:35.96/vblo/07,734.99,yes,locked 2006.201.12:34:35.96/vblo/08,744.99,yes,locked 2006.201.12:34:36.11/vabw/8 2006.201.12:34:36.26/vbbw/8 2006.201.12:34:36.35/xfe/off,on,14.7 2006.201.12:34:36.74/ifatt/23,28,28,28 2006.201.12:34:37.05/fmout-gps/S +4.62E-07 2006.201.12:34:37.10:!2006.201.12:35:42 2006.201.12:35:42.00:data_valid=off 2006.201.12:35:42.00:"et 2006.201.12:35:42.00:!+3s 2006.201.12:35:45.02:"tape 2006.201.12:35:45.02:postob 2006.201.12:35:45.24/cable/+6.4716E-03 2006.201.12:35:45.24/wx/21.09,1004.1,100 2006.201.12:35:45.31/fmout-gps/S +4.60E-07 2006.201.12:35:45.31:scan_name=201-1239,jd0607,40 2006.201.12:35:45.31:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.201.12:35:47.14#flagr#flagr/antenna,new-source 2006.201.12:35:47.14:checkk5 2006.201.12:35:47.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:35:47.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:35:48.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:35:48.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:35:49.02/chk_obsdata//k5ts1/T2011234??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.12:35:49.40/chk_obsdata//k5ts2/T2011234??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.12:35:49.77/chk_obsdata//k5ts3/T2011234??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.12:35:50.14/chk_obsdata//k5ts4/T2011234??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.12:35:50.84/k5log//k5ts1_log_newline 2006.201.12:35:51.53/k5log//k5ts2_log_newline 2006.201.12:35:52.22/k5log//k5ts3_log_newline 2006.201.12:35:52.90/k5log//k5ts4_log_newline 2006.201.12:35:52.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:35:52.92:setupk4=1 2006.201.12:35:52.92$setupk4/echo=on 2006.201.12:35:52.92$setupk4/pcalon 2006.201.12:35:52.92$pcalon/"no phase cal control is implemented here 2006.201.12:35:52.92$setupk4/"tpicd=stop 2006.201.12:35:52.92$setupk4/"rec=synch_on 2006.201.12:35:52.92$setupk4/"rec_mode=128 2006.201.12:35:52.92$setupk4/!* 2006.201.12:35:52.92$setupk4/recpk4 2006.201.12:35:52.92$recpk4/recpatch= 2006.201.12:35:52.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:35:52.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:35:52.93$setupk4/vck44 2006.201.12:35:52.93$vck44/valo=1,524.99 2006.201.12:35:52.93#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.12:35:52.93#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.12:35:52.93#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:52.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:35:52.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:35:52.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:35:52.93#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:35:52.93#ibcon#first serial, iclass 5, count 0 2006.201.12:35:52.93#ibcon#enter sib2, iclass 5, count 0 2006.201.12:35:52.93#ibcon#flushed, iclass 5, count 0 2006.201.12:35:52.93#ibcon#about to write, iclass 5, count 0 2006.201.12:35:52.93#ibcon#wrote, iclass 5, count 0 2006.201.12:35:52.93#ibcon#about to read 3, iclass 5, count 0 2006.201.12:35:52.96#ibcon#read 3, iclass 5, count 0 2006.201.12:35:52.96#ibcon#about to read 4, iclass 5, count 0 2006.201.12:35:52.96#ibcon#read 4, iclass 5, count 0 2006.201.12:35:52.96#ibcon#about to read 5, iclass 5, count 0 2006.201.12:35:52.96#ibcon#read 5, iclass 5, count 0 2006.201.12:35:52.96#ibcon#about to read 6, iclass 5, count 0 2006.201.12:35:52.96#ibcon#read 6, iclass 5, count 0 2006.201.12:35:52.96#ibcon#end of sib2, iclass 5, count 0 2006.201.12:35:52.96#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:35:52.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:35:52.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:35:52.96#ibcon#*before write, iclass 5, count 0 2006.201.12:35:52.96#ibcon#enter sib2, iclass 5, count 0 2006.201.12:35:52.96#ibcon#flushed, iclass 5, count 0 2006.201.12:35:52.96#ibcon#about to write, iclass 5, count 0 2006.201.12:35:52.97#ibcon#wrote, iclass 5, count 0 2006.201.12:35:52.97#ibcon#about to read 3, iclass 5, count 0 2006.201.12:35:53.02#ibcon#read 3, iclass 5, count 0 2006.201.12:35:53.02#ibcon#about to read 4, iclass 5, count 0 2006.201.12:35:53.02#ibcon#read 4, iclass 5, count 0 2006.201.12:35:53.02#ibcon#about to read 5, iclass 5, count 0 2006.201.12:35:53.02#ibcon#read 5, iclass 5, count 0 2006.201.12:35:53.02#ibcon#about to read 6, iclass 5, count 0 2006.201.12:35:53.02#ibcon#read 6, iclass 5, count 0 2006.201.12:35:53.02#ibcon#end of sib2, iclass 5, count 0 2006.201.12:35:53.02#ibcon#*after write, iclass 5, count 0 2006.201.12:35:53.02#ibcon#*before return 0, iclass 5, count 0 2006.201.12:35:53.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:35:53.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:35:53.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:35:53.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:35:53.02$vck44/va=1,8 2006.201.12:35:53.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.12:35:53.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.12:35:53.02#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:53.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:35:53.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:35:53.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:35:53.02#ibcon#enter wrdev, iclass 7, count 2 2006.201.12:35:53.02#ibcon#first serial, iclass 7, count 2 2006.201.12:35:53.02#ibcon#enter sib2, iclass 7, count 2 2006.201.12:35:53.02#ibcon#flushed, iclass 7, count 2 2006.201.12:35:53.02#ibcon#about to write, iclass 7, count 2 2006.201.12:35:53.02#ibcon#wrote, iclass 7, count 2 2006.201.12:35:53.02#ibcon#about to read 3, iclass 7, count 2 2006.201.12:35:53.04#ibcon#read 3, iclass 7, count 2 2006.201.12:35:53.04#ibcon#about to read 4, iclass 7, count 2 2006.201.12:35:53.04#ibcon#read 4, iclass 7, count 2 2006.201.12:35:53.04#ibcon#about to read 5, iclass 7, count 2 2006.201.12:35:53.04#ibcon#read 5, iclass 7, count 2 2006.201.12:35:53.04#ibcon#about to read 6, iclass 7, count 2 2006.201.12:35:53.04#ibcon#read 6, iclass 7, count 2 2006.201.12:35:53.04#ibcon#end of sib2, iclass 7, count 2 2006.201.12:35:53.04#ibcon#*mode == 0, iclass 7, count 2 2006.201.12:35:53.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.12:35:53.04#ibcon#[25=AT01-08\r\n] 2006.201.12:35:53.04#ibcon#*before write, iclass 7, count 2 2006.201.12:35:53.04#ibcon#enter sib2, iclass 7, count 2 2006.201.12:35:53.04#ibcon#flushed, iclass 7, count 2 2006.201.12:35:53.04#ibcon#about to write, iclass 7, count 2 2006.201.12:35:53.04#ibcon#wrote, iclass 7, count 2 2006.201.12:35:53.04#ibcon#about to read 3, iclass 7, count 2 2006.201.12:35:53.08#ibcon#read 3, iclass 7, count 2 2006.201.12:35:53.08#ibcon#about to read 4, iclass 7, count 2 2006.201.12:35:53.08#ibcon#read 4, iclass 7, count 2 2006.201.12:35:53.08#ibcon#about to read 5, iclass 7, count 2 2006.201.12:35:53.08#ibcon#read 5, iclass 7, count 2 2006.201.12:35:53.08#ibcon#about to read 6, iclass 7, count 2 2006.201.12:35:53.08#ibcon#read 6, iclass 7, count 2 2006.201.12:35:53.08#ibcon#end of sib2, iclass 7, count 2 2006.201.12:35:53.08#ibcon#*after write, iclass 7, count 2 2006.201.12:35:53.08#ibcon#*before return 0, iclass 7, count 2 2006.201.12:35:53.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:35:53.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:35:53.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.12:35:53.08#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:53.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:35:53.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:35:53.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:35:53.20#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:35:53.20#ibcon#first serial, iclass 7, count 0 2006.201.12:35:53.20#ibcon#enter sib2, iclass 7, count 0 2006.201.12:35:53.20#ibcon#flushed, iclass 7, count 0 2006.201.12:35:53.20#ibcon#about to write, iclass 7, count 0 2006.201.12:35:53.20#ibcon#wrote, iclass 7, count 0 2006.201.12:35:53.20#ibcon#about to read 3, iclass 7, count 0 2006.201.12:35:53.23#ibcon#read 3, iclass 7, count 0 2006.201.12:35:53.23#ibcon#about to read 4, iclass 7, count 0 2006.201.12:35:53.23#ibcon#read 4, iclass 7, count 0 2006.201.12:35:53.23#ibcon#about to read 5, iclass 7, count 0 2006.201.12:35:53.23#ibcon#read 5, iclass 7, count 0 2006.201.12:35:53.23#ibcon#about to read 6, iclass 7, count 0 2006.201.12:35:53.23#ibcon#read 6, iclass 7, count 0 2006.201.12:35:53.23#ibcon#end of sib2, iclass 7, count 0 2006.201.12:35:53.23#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:35:53.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:35:53.23#ibcon#[25=USB\r\n] 2006.201.12:35:53.23#ibcon#*before write, iclass 7, count 0 2006.201.12:35:53.23#ibcon#enter sib2, iclass 7, count 0 2006.201.12:35:53.23#ibcon#flushed, iclass 7, count 0 2006.201.12:35:53.23#ibcon#about to write, iclass 7, count 0 2006.201.12:35:53.23#ibcon#wrote, iclass 7, count 0 2006.201.12:35:53.23#ibcon#about to read 3, iclass 7, count 0 2006.201.12:35:53.26#ibcon#read 3, iclass 7, count 0 2006.201.12:35:53.26#ibcon#about to read 4, iclass 7, count 0 2006.201.12:35:53.26#ibcon#read 4, iclass 7, count 0 2006.201.12:35:53.26#ibcon#about to read 5, iclass 7, count 0 2006.201.12:35:53.26#ibcon#read 5, iclass 7, count 0 2006.201.12:35:53.26#ibcon#about to read 6, iclass 7, count 0 2006.201.12:35:53.26#ibcon#read 6, iclass 7, count 0 2006.201.12:35:53.26#ibcon#end of sib2, iclass 7, count 0 2006.201.12:35:53.26#ibcon#*after write, iclass 7, count 0 2006.201.12:35:53.26#ibcon#*before return 0, iclass 7, count 0 2006.201.12:35:53.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:35:53.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:35:53.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:35:53.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:35:53.26$vck44/valo=2,534.99 2006.201.12:35:53.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.12:35:53.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.12:35:53.26#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:53.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:35:53.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:35:53.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:35:53.26#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:35:53.26#ibcon#first serial, iclass 11, count 0 2006.201.12:35:53.26#ibcon#enter sib2, iclass 11, count 0 2006.201.12:35:53.26#ibcon#flushed, iclass 11, count 0 2006.201.12:35:53.26#ibcon#about to write, iclass 11, count 0 2006.201.12:35:53.26#ibcon#wrote, iclass 11, count 0 2006.201.12:35:53.26#ibcon#about to read 3, iclass 11, count 0 2006.201.12:35:53.28#ibcon#read 3, iclass 11, count 0 2006.201.12:35:53.28#ibcon#about to read 4, iclass 11, count 0 2006.201.12:35:53.28#ibcon#read 4, iclass 11, count 0 2006.201.12:35:53.28#ibcon#about to read 5, iclass 11, count 0 2006.201.12:35:53.28#ibcon#read 5, iclass 11, count 0 2006.201.12:35:53.28#ibcon#about to read 6, iclass 11, count 0 2006.201.12:35:53.28#ibcon#read 6, iclass 11, count 0 2006.201.12:35:53.28#ibcon#end of sib2, iclass 11, count 0 2006.201.12:35:53.28#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:35:53.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:35:53.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:35:53.28#ibcon#*before write, iclass 11, count 0 2006.201.12:35:53.28#ibcon#enter sib2, iclass 11, count 0 2006.201.12:35:53.28#ibcon#flushed, iclass 11, count 0 2006.201.12:35:53.28#ibcon#about to write, iclass 11, count 0 2006.201.12:35:53.28#ibcon#wrote, iclass 11, count 0 2006.201.12:35:53.28#ibcon#about to read 3, iclass 11, count 0 2006.201.12:35:53.32#ibcon#read 3, iclass 11, count 0 2006.201.12:35:53.32#ibcon#about to read 4, iclass 11, count 0 2006.201.12:35:53.32#ibcon#read 4, iclass 11, count 0 2006.201.12:35:53.32#ibcon#about to read 5, iclass 11, count 0 2006.201.12:35:53.32#ibcon#read 5, iclass 11, count 0 2006.201.12:35:53.32#ibcon#about to read 6, iclass 11, count 0 2006.201.12:35:53.32#ibcon#read 6, iclass 11, count 0 2006.201.12:35:53.32#ibcon#end of sib2, iclass 11, count 0 2006.201.12:35:53.32#ibcon#*after write, iclass 11, count 0 2006.201.12:35:53.32#ibcon#*before return 0, iclass 11, count 0 2006.201.12:35:53.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:35:53.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:35:53.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:35:53.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:35:53.32$vck44/va=2,7 2006.201.12:35:53.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.12:35:53.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.12:35:53.32#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:53.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:35:53.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:35:53.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:35:53.38#ibcon#enter wrdev, iclass 13, count 2 2006.201.12:35:53.38#ibcon#first serial, iclass 13, count 2 2006.201.12:35:53.38#ibcon#enter sib2, iclass 13, count 2 2006.201.12:35:53.38#ibcon#flushed, iclass 13, count 2 2006.201.12:35:53.38#ibcon#about to write, iclass 13, count 2 2006.201.12:35:53.38#ibcon#wrote, iclass 13, count 2 2006.201.12:35:53.38#ibcon#about to read 3, iclass 13, count 2 2006.201.12:35:53.40#ibcon#read 3, iclass 13, count 2 2006.201.12:35:53.40#ibcon#about to read 4, iclass 13, count 2 2006.201.12:35:53.40#ibcon#read 4, iclass 13, count 2 2006.201.12:35:53.40#ibcon#about to read 5, iclass 13, count 2 2006.201.12:35:53.40#ibcon#read 5, iclass 13, count 2 2006.201.12:35:53.40#ibcon#about to read 6, iclass 13, count 2 2006.201.12:35:53.40#ibcon#read 6, iclass 13, count 2 2006.201.12:35:53.40#ibcon#end of sib2, iclass 13, count 2 2006.201.12:35:53.40#ibcon#*mode == 0, iclass 13, count 2 2006.201.12:35:53.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.12:35:53.40#ibcon#[25=AT02-07\r\n] 2006.201.12:35:53.40#ibcon#*before write, iclass 13, count 2 2006.201.12:35:53.40#ibcon#enter sib2, iclass 13, count 2 2006.201.12:35:53.40#ibcon#flushed, iclass 13, count 2 2006.201.12:35:53.40#ibcon#about to write, iclass 13, count 2 2006.201.12:35:53.40#ibcon#wrote, iclass 13, count 2 2006.201.12:35:53.40#ibcon#about to read 3, iclass 13, count 2 2006.201.12:35:53.43#ibcon#read 3, iclass 13, count 2 2006.201.12:35:53.43#ibcon#about to read 4, iclass 13, count 2 2006.201.12:35:53.43#ibcon#read 4, iclass 13, count 2 2006.201.12:35:53.43#ibcon#about to read 5, iclass 13, count 2 2006.201.12:35:53.43#ibcon#read 5, iclass 13, count 2 2006.201.12:35:53.43#ibcon#about to read 6, iclass 13, count 2 2006.201.12:35:53.43#ibcon#read 6, iclass 13, count 2 2006.201.12:35:53.43#ibcon#end of sib2, iclass 13, count 2 2006.201.12:35:53.43#ibcon#*after write, iclass 13, count 2 2006.201.12:35:53.43#ibcon#*before return 0, iclass 13, count 2 2006.201.12:35:53.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:35:53.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:35:53.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.12:35:53.43#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:53.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:35:53.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:35:53.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:35:53.55#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:35:53.55#ibcon#first serial, iclass 13, count 0 2006.201.12:35:53.55#ibcon#enter sib2, iclass 13, count 0 2006.201.12:35:53.55#ibcon#flushed, iclass 13, count 0 2006.201.12:35:53.55#ibcon#about to write, iclass 13, count 0 2006.201.12:35:53.55#ibcon#wrote, iclass 13, count 0 2006.201.12:35:53.55#ibcon#about to read 3, iclass 13, count 0 2006.201.12:35:53.57#ibcon#read 3, iclass 13, count 0 2006.201.12:35:53.57#ibcon#about to read 4, iclass 13, count 0 2006.201.12:35:53.57#ibcon#read 4, iclass 13, count 0 2006.201.12:35:53.57#ibcon#about to read 5, iclass 13, count 0 2006.201.12:35:53.57#ibcon#read 5, iclass 13, count 0 2006.201.12:35:53.57#ibcon#about to read 6, iclass 13, count 0 2006.201.12:35:53.57#ibcon#read 6, iclass 13, count 0 2006.201.12:35:53.57#ibcon#end of sib2, iclass 13, count 0 2006.201.12:35:53.57#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:35:53.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:35:53.57#ibcon#[25=USB\r\n] 2006.201.12:35:53.57#ibcon#*before write, iclass 13, count 0 2006.201.12:35:53.57#ibcon#enter sib2, iclass 13, count 0 2006.201.12:35:53.57#ibcon#flushed, iclass 13, count 0 2006.201.12:35:53.57#ibcon#about to write, iclass 13, count 0 2006.201.12:35:53.57#ibcon#wrote, iclass 13, count 0 2006.201.12:35:53.57#ibcon#about to read 3, iclass 13, count 0 2006.201.12:35:53.60#ibcon#read 3, iclass 13, count 0 2006.201.12:35:53.60#ibcon#about to read 4, iclass 13, count 0 2006.201.12:35:53.60#ibcon#read 4, iclass 13, count 0 2006.201.12:35:53.60#ibcon#about to read 5, iclass 13, count 0 2006.201.12:35:53.60#ibcon#read 5, iclass 13, count 0 2006.201.12:35:53.60#ibcon#about to read 6, iclass 13, count 0 2006.201.12:35:53.60#ibcon#read 6, iclass 13, count 0 2006.201.12:35:53.60#ibcon#end of sib2, iclass 13, count 0 2006.201.12:35:53.60#ibcon#*after write, iclass 13, count 0 2006.201.12:35:53.60#ibcon#*before return 0, iclass 13, count 0 2006.201.12:35:53.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:35:53.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:35:53.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:35:53.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:35:53.60$vck44/valo=3,564.99 2006.201.12:35:53.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.12:35:53.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.12:35:53.60#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:53.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:35:53.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:35:53.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:35:53.60#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:35:53.60#ibcon#first serial, iclass 15, count 0 2006.201.12:35:53.60#ibcon#enter sib2, iclass 15, count 0 2006.201.12:35:53.60#ibcon#flushed, iclass 15, count 0 2006.201.12:35:53.60#ibcon#about to write, iclass 15, count 0 2006.201.12:35:53.60#ibcon#wrote, iclass 15, count 0 2006.201.12:35:53.60#ibcon#about to read 3, iclass 15, count 0 2006.201.12:35:53.62#ibcon#read 3, iclass 15, count 0 2006.201.12:35:53.62#ibcon#about to read 4, iclass 15, count 0 2006.201.12:35:53.62#ibcon#read 4, iclass 15, count 0 2006.201.12:35:53.62#ibcon#about to read 5, iclass 15, count 0 2006.201.12:35:53.62#ibcon#read 5, iclass 15, count 0 2006.201.12:35:53.62#ibcon#about to read 6, iclass 15, count 0 2006.201.12:35:53.62#ibcon#read 6, iclass 15, count 0 2006.201.12:35:53.62#ibcon#end of sib2, iclass 15, count 0 2006.201.12:35:53.62#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:35:53.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:35:53.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:35:53.62#ibcon#*before write, iclass 15, count 0 2006.201.12:35:53.62#ibcon#enter sib2, iclass 15, count 0 2006.201.12:35:53.62#ibcon#flushed, iclass 15, count 0 2006.201.12:35:53.62#ibcon#about to write, iclass 15, count 0 2006.201.12:35:53.62#ibcon#wrote, iclass 15, count 0 2006.201.12:35:53.62#ibcon#about to read 3, iclass 15, count 0 2006.201.12:35:53.67#ibcon#read 3, iclass 15, count 0 2006.201.12:35:53.67#ibcon#about to read 4, iclass 15, count 0 2006.201.12:35:53.67#ibcon#read 4, iclass 15, count 0 2006.201.12:35:53.67#ibcon#about to read 5, iclass 15, count 0 2006.201.12:35:53.67#ibcon#read 5, iclass 15, count 0 2006.201.12:35:53.67#ibcon#about to read 6, iclass 15, count 0 2006.201.12:35:53.67#ibcon#read 6, iclass 15, count 0 2006.201.12:35:53.67#ibcon#end of sib2, iclass 15, count 0 2006.201.12:35:53.67#ibcon#*after write, iclass 15, count 0 2006.201.12:35:53.67#ibcon#*before return 0, iclass 15, count 0 2006.201.12:35:53.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:35:53.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:35:53.67#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:35:53.67#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:35:53.67$vck44/va=3,8 2006.201.12:35:53.67#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.12:35:53.67#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.12:35:53.67#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:53.67#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:35:53.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:35:53.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:35:53.72#ibcon#enter wrdev, iclass 17, count 2 2006.201.12:35:53.72#ibcon#first serial, iclass 17, count 2 2006.201.12:35:53.72#ibcon#enter sib2, iclass 17, count 2 2006.201.12:35:53.72#ibcon#flushed, iclass 17, count 2 2006.201.12:35:53.72#ibcon#about to write, iclass 17, count 2 2006.201.12:35:53.72#ibcon#wrote, iclass 17, count 2 2006.201.12:35:53.72#ibcon#about to read 3, iclass 17, count 2 2006.201.12:35:53.74#ibcon#read 3, iclass 17, count 2 2006.201.12:35:53.74#ibcon#about to read 4, iclass 17, count 2 2006.201.12:35:53.74#ibcon#read 4, iclass 17, count 2 2006.201.12:35:53.74#ibcon#about to read 5, iclass 17, count 2 2006.201.12:35:53.74#ibcon#read 5, iclass 17, count 2 2006.201.12:35:53.74#ibcon#about to read 6, iclass 17, count 2 2006.201.12:35:53.74#ibcon#read 6, iclass 17, count 2 2006.201.12:35:53.74#ibcon#end of sib2, iclass 17, count 2 2006.201.12:35:53.74#ibcon#*mode == 0, iclass 17, count 2 2006.201.12:35:53.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.12:35:53.74#ibcon#[25=AT03-08\r\n] 2006.201.12:35:53.74#ibcon#*before write, iclass 17, count 2 2006.201.12:35:53.74#ibcon#enter sib2, iclass 17, count 2 2006.201.12:35:53.74#ibcon#flushed, iclass 17, count 2 2006.201.12:35:53.74#ibcon#about to write, iclass 17, count 2 2006.201.12:35:53.74#ibcon#wrote, iclass 17, count 2 2006.201.12:35:53.74#ibcon#about to read 3, iclass 17, count 2 2006.201.12:35:53.77#ibcon#read 3, iclass 17, count 2 2006.201.12:35:53.77#ibcon#about to read 4, iclass 17, count 2 2006.201.12:35:53.77#ibcon#read 4, iclass 17, count 2 2006.201.12:35:53.77#ibcon#about to read 5, iclass 17, count 2 2006.201.12:35:53.77#ibcon#read 5, iclass 17, count 2 2006.201.12:35:53.77#ibcon#about to read 6, iclass 17, count 2 2006.201.12:35:53.77#ibcon#read 6, iclass 17, count 2 2006.201.12:35:53.77#ibcon#end of sib2, iclass 17, count 2 2006.201.12:35:53.77#ibcon#*after write, iclass 17, count 2 2006.201.12:35:53.77#ibcon#*before return 0, iclass 17, count 2 2006.201.12:35:53.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:35:53.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:35:53.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.12:35:53.77#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:53.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:35:53.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:35:53.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:35:53.89#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:35:53.89#ibcon#first serial, iclass 17, count 0 2006.201.12:35:53.89#ibcon#enter sib2, iclass 17, count 0 2006.201.12:35:53.89#ibcon#flushed, iclass 17, count 0 2006.201.12:35:53.89#ibcon#about to write, iclass 17, count 0 2006.201.12:35:53.89#ibcon#wrote, iclass 17, count 0 2006.201.12:35:53.89#ibcon#about to read 3, iclass 17, count 0 2006.201.12:35:53.91#ibcon#read 3, iclass 17, count 0 2006.201.12:35:53.91#ibcon#about to read 4, iclass 17, count 0 2006.201.12:35:53.91#ibcon#read 4, iclass 17, count 0 2006.201.12:35:53.91#ibcon#about to read 5, iclass 17, count 0 2006.201.12:35:53.91#ibcon#read 5, iclass 17, count 0 2006.201.12:35:53.91#ibcon#about to read 6, iclass 17, count 0 2006.201.12:35:53.91#ibcon#read 6, iclass 17, count 0 2006.201.12:35:53.91#ibcon#end of sib2, iclass 17, count 0 2006.201.12:35:53.91#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:35:53.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:35:53.91#ibcon#[25=USB\r\n] 2006.201.12:35:53.91#ibcon#*before write, iclass 17, count 0 2006.201.12:35:53.91#ibcon#enter sib2, iclass 17, count 0 2006.201.12:35:53.91#ibcon#flushed, iclass 17, count 0 2006.201.12:35:53.91#ibcon#about to write, iclass 17, count 0 2006.201.12:35:53.91#ibcon#wrote, iclass 17, count 0 2006.201.12:35:53.91#ibcon#about to read 3, iclass 17, count 0 2006.201.12:35:53.94#ibcon#read 3, iclass 17, count 0 2006.201.12:35:53.94#ibcon#about to read 4, iclass 17, count 0 2006.201.12:35:53.94#ibcon#read 4, iclass 17, count 0 2006.201.12:35:53.94#ibcon#about to read 5, iclass 17, count 0 2006.201.12:35:53.94#ibcon#read 5, iclass 17, count 0 2006.201.12:35:53.94#ibcon#about to read 6, iclass 17, count 0 2006.201.12:35:53.94#ibcon#read 6, iclass 17, count 0 2006.201.12:35:53.94#ibcon#end of sib2, iclass 17, count 0 2006.201.12:35:53.94#ibcon#*after write, iclass 17, count 0 2006.201.12:35:53.94#ibcon#*before return 0, iclass 17, count 0 2006.201.12:35:53.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:35:53.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:35:53.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:35:53.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:35:53.94$vck44/valo=4,624.99 2006.201.12:35:53.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.12:35:53.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.12:35:53.94#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:53.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:35:53.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:35:53.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:35:53.94#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:35:53.94#ibcon#first serial, iclass 19, count 0 2006.201.12:35:53.94#ibcon#enter sib2, iclass 19, count 0 2006.201.12:35:53.94#ibcon#flushed, iclass 19, count 0 2006.201.12:35:53.94#ibcon#about to write, iclass 19, count 0 2006.201.12:35:53.94#ibcon#wrote, iclass 19, count 0 2006.201.12:35:53.94#ibcon#about to read 3, iclass 19, count 0 2006.201.12:35:53.96#ibcon#read 3, iclass 19, count 0 2006.201.12:35:53.96#ibcon#about to read 4, iclass 19, count 0 2006.201.12:35:53.96#ibcon#read 4, iclass 19, count 0 2006.201.12:35:53.96#ibcon#about to read 5, iclass 19, count 0 2006.201.12:35:53.96#ibcon#read 5, iclass 19, count 0 2006.201.12:35:53.96#ibcon#about to read 6, iclass 19, count 0 2006.201.12:35:53.96#ibcon#read 6, iclass 19, count 0 2006.201.12:35:53.96#ibcon#end of sib2, iclass 19, count 0 2006.201.12:35:53.96#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:35:53.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:35:53.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:35:53.96#ibcon#*before write, iclass 19, count 0 2006.201.12:35:53.96#ibcon#enter sib2, iclass 19, count 0 2006.201.12:35:53.96#ibcon#flushed, iclass 19, count 0 2006.201.12:35:53.96#ibcon#about to write, iclass 19, count 0 2006.201.12:35:53.96#ibcon#wrote, iclass 19, count 0 2006.201.12:35:53.96#ibcon#about to read 3, iclass 19, count 0 2006.201.12:35:54.01#ibcon#read 3, iclass 19, count 0 2006.201.12:35:54.01#ibcon#about to read 4, iclass 19, count 0 2006.201.12:35:54.01#ibcon#read 4, iclass 19, count 0 2006.201.12:35:54.01#ibcon#about to read 5, iclass 19, count 0 2006.201.12:35:54.01#ibcon#read 5, iclass 19, count 0 2006.201.12:35:54.01#ibcon#about to read 6, iclass 19, count 0 2006.201.12:35:54.01#ibcon#read 6, iclass 19, count 0 2006.201.12:35:54.01#ibcon#end of sib2, iclass 19, count 0 2006.201.12:35:54.01#ibcon#*after write, iclass 19, count 0 2006.201.12:35:54.01#ibcon#*before return 0, iclass 19, count 0 2006.201.12:35:54.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:35:54.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:35:54.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:35:54.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:35:54.01$vck44/va=4,7 2006.201.12:35:54.01#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.12:35:54.01#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.12:35:54.01#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:54.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:35:54.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:35:54.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:35:54.06#ibcon#enter wrdev, iclass 21, count 2 2006.201.12:35:54.06#ibcon#first serial, iclass 21, count 2 2006.201.12:35:54.06#ibcon#enter sib2, iclass 21, count 2 2006.201.12:35:54.06#ibcon#flushed, iclass 21, count 2 2006.201.12:35:54.06#ibcon#about to write, iclass 21, count 2 2006.201.12:35:54.06#ibcon#wrote, iclass 21, count 2 2006.201.12:35:54.06#ibcon#about to read 3, iclass 21, count 2 2006.201.12:35:54.08#ibcon#read 3, iclass 21, count 2 2006.201.12:35:54.08#ibcon#about to read 4, iclass 21, count 2 2006.201.12:35:54.08#ibcon#read 4, iclass 21, count 2 2006.201.12:35:54.08#ibcon#about to read 5, iclass 21, count 2 2006.201.12:35:54.08#ibcon#read 5, iclass 21, count 2 2006.201.12:35:54.08#ibcon#about to read 6, iclass 21, count 2 2006.201.12:35:54.08#ibcon#read 6, iclass 21, count 2 2006.201.12:35:54.08#ibcon#end of sib2, iclass 21, count 2 2006.201.12:35:54.08#ibcon#*mode == 0, iclass 21, count 2 2006.201.12:35:54.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.12:35:54.08#ibcon#[25=AT04-07\r\n] 2006.201.12:35:54.08#ibcon#*before write, iclass 21, count 2 2006.201.12:35:54.08#ibcon#enter sib2, iclass 21, count 2 2006.201.12:35:54.08#ibcon#flushed, iclass 21, count 2 2006.201.12:35:54.08#ibcon#about to write, iclass 21, count 2 2006.201.12:35:54.08#ibcon#wrote, iclass 21, count 2 2006.201.12:35:54.08#ibcon#about to read 3, iclass 21, count 2 2006.201.12:35:54.11#ibcon#read 3, iclass 21, count 2 2006.201.12:35:54.11#ibcon#about to read 4, iclass 21, count 2 2006.201.12:35:54.11#ibcon#read 4, iclass 21, count 2 2006.201.12:35:54.11#ibcon#about to read 5, iclass 21, count 2 2006.201.12:35:54.11#ibcon#read 5, iclass 21, count 2 2006.201.12:35:54.11#ibcon#about to read 6, iclass 21, count 2 2006.201.12:35:54.11#ibcon#read 6, iclass 21, count 2 2006.201.12:35:54.11#ibcon#end of sib2, iclass 21, count 2 2006.201.12:35:54.11#ibcon#*after write, iclass 21, count 2 2006.201.12:35:54.11#ibcon#*before return 0, iclass 21, count 2 2006.201.12:35:54.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:35:54.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:35:54.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.12:35:54.11#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:54.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:35:54.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:35:54.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:35:54.23#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:35:54.23#ibcon#first serial, iclass 21, count 0 2006.201.12:35:54.23#ibcon#enter sib2, iclass 21, count 0 2006.201.12:35:54.23#ibcon#flushed, iclass 21, count 0 2006.201.12:35:54.23#ibcon#about to write, iclass 21, count 0 2006.201.12:35:54.23#ibcon#wrote, iclass 21, count 0 2006.201.12:35:54.23#ibcon#about to read 3, iclass 21, count 0 2006.201.12:35:54.25#ibcon#read 3, iclass 21, count 0 2006.201.12:35:54.25#ibcon#about to read 4, iclass 21, count 0 2006.201.12:35:54.25#ibcon#read 4, iclass 21, count 0 2006.201.12:35:54.25#ibcon#about to read 5, iclass 21, count 0 2006.201.12:35:54.25#ibcon#read 5, iclass 21, count 0 2006.201.12:35:54.25#ibcon#about to read 6, iclass 21, count 0 2006.201.12:35:54.25#ibcon#read 6, iclass 21, count 0 2006.201.12:35:54.25#ibcon#end of sib2, iclass 21, count 0 2006.201.12:35:54.25#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:35:54.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:35:54.25#ibcon#[25=USB\r\n] 2006.201.12:35:54.25#ibcon#*before write, iclass 21, count 0 2006.201.12:35:54.25#ibcon#enter sib2, iclass 21, count 0 2006.201.12:35:54.25#ibcon#flushed, iclass 21, count 0 2006.201.12:35:54.25#ibcon#about to write, iclass 21, count 0 2006.201.12:35:54.25#ibcon#wrote, iclass 21, count 0 2006.201.12:35:54.25#ibcon#about to read 3, iclass 21, count 0 2006.201.12:35:54.28#ibcon#read 3, iclass 21, count 0 2006.201.12:35:54.28#ibcon#about to read 4, iclass 21, count 0 2006.201.12:35:54.28#ibcon#read 4, iclass 21, count 0 2006.201.12:35:54.28#ibcon#about to read 5, iclass 21, count 0 2006.201.12:35:54.28#ibcon#read 5, iclass 21, count 0 2006.201.12:35:54.28#ibcon#about to read 6, iclass 21, count 0 2006.201.12:35:54.28#ibcon#read 6, iclass 21, count 0 2006.201.12:35:54.28#ibcon#end of sib2, iclass 21, count 0 2006.201.12:35:54.28#ibcon#*after write, iclass 21, count 0 2006.201.12:35:54.28#ibcon#*before return 0, iclass 21, count 0 2006.201.12:35:54.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:35:54.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:35:54.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:35:54.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:35:54.28$vck44/valo=5,734.99 2006.201.12:35:54.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.12:35:54.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.12:35:54.28#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:54.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:35:54.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:35:54.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:35:54.28#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:35:54.28#ibcon#first serial, iclass 23, count 0 2006.201.12:35:54.28#ibcon#enter sib2, iclass 23, count 0 2006.201.12:35:54.28#ibcon#flushed, iclass 23, count 0 2006.201.12:35:54.28#ibcon#about to write, iclass 23, count 0 2006.201.12:35:54.28#ibcon#wrote, iclass 23, count 0 2006.201.12:35:54.28#ibcon#about to read 3, iclass 23, count 0 2006.201.12:35:54.30#ibcon#read 3, iclass 23, count 0 2006.201.12:35:54.30#ibcon#about to read 4, iclass 23, count 0 2006.201.12:35:54.30#ibcon#read 4, iclass 23, count 0 2006.201.12:35:54.30#ibcon#about to read 5, iclass 23, count 0 2006.201.12:35:54.30#ibcon#read 5, iclass 23, count 0 2006.201.12:35:54.30#ibcon#about to read 6, iclass 23, count 0 2006.201.12:35:54.30#ibcon#read 6, iclass 23, count 0 2006.201.12:35:54.30#ibcon#end of sib2, iclass 23, count 0 2006.201.12:35:54.30#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:35:54.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:35:54.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:35:54.30#ibcon#*before write, iclass 23, count 0 2006.201.12:35:54.30#ibcon#enter sib2, iclass 23, count 0 2006.201.12:35:54.30#ibcon#flushed, iclass 23, count 0 2006.201.12:35:54.30#ibcon#about to write, iclass 23, count 0 2006.201.12:35:54.30#ibcon#wrote, iclass 23, count 0 2006.201.12:35:54.30#ibcon#about to read 3, iclass 23, count 0 2006.201.12:35:54.34#ibcon#read 3, iclass 23, count 0 2006.201.12:35:54.34#ibcon#about to read 4, iclass 23, count 0 2006.201.12:35:54.34#ibcon#read 4, iclass 23, count 0 2006.201.12:35:54.34#ibcon#about to read 5, iclass 23, count 0 2006.201.12:35:54.34#ibcon#read 5, iclass 23, count 0 2006.201.12:35:54.34#ibcon#about to read 6, iclass 23, count 0 2006.201.12:35:54.34#ibcon#read 6, iclass 23, count 0 2006.201.12:35:54.34#ibcon#end of sib2, iclass 23, count 0 2006.201.12:35:54.34#ibcon#*after write, iclass 23, count 0 2006.201.12:35:54.34#ibcon#*before return 0, iclass 23, count 0 2006.201.12:35:54.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:35:54.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:35:54.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:35:54.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:35:54.34$vck44/va=5,4 2006.201.12:35:54.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.12:35:54.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.12:35:54.34#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:54.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:35:54.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:35:54.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:35:54.40#ibcon#enter wrdev, iclass 25, count 2 2006.201.12:35:54.40#ibcon#first serial, iclass 25, count 2 2006.201.12:35:54.40#ibcon#enter sib2, iclass 25, count 2 2006.201.12:35:54.40#ibcon#flushed, iclass 25, count 2 2006.201.12:35:54.40#ibcon#about to write, iclass 25, count 2 2006.201.12:35:54.40#ibcon#wrote, iclass 25, count 2 2006.201.12:35:54.40#ibcon#about to read 3, iclass 25, count 2 2006.201.12:35:54.42#ibcon#read 3, iclass 25, count 2 2006.201.12:35:54.42#ibcon#about to read 4, iclass 25, count 2 2006.201.12:35:54.42#ibcon#read 4, iclass 25, count 2 2006.201.12:35:54.42#ibcon#about to read 5, iclass 25, count 2 2006.201.12:35:54.42#ibcon#read 5, iclass 25, count 2 2006.201.12:35:54.42#ibcon#about to read 6, iclass 25, count 2 2006.201.12:35:54.42#ibcon#read 6, iclass 25, count 2 2006.201.12:35:54.42#ibcon#end of sib2, iclass 25, count 2 2006.201.12:35:54.42#ibcon#*mode == 0, iclass 25, count 2 2006.201.12:35:54.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.12:35:54.42#ibcon#[25=AT05-04\r\n] 2006.201.12:35:54.42#ibcon#*before write, iclass 25, count 2 2006.201.12:35:54.42#ibcon#enter sib2, iclass 25, count 2 2006.201.12:35:54.42#ibcon#flushed, iclass 25, count 2 2006.201.12:35:54.42#ibcon#about to write, iclass 25, count 2 2006.201.12:35:54.42#ibcon#wrote, iclass 25, count 2 2006.201.12:35:54.42#ibcon#about to read 3, iclass 25, count 2 2006.201.12:35:54.45#ibcon#read 3, iclass 25, count 2 2006.201.12:35:54.45#ibcon#about to read 4, iclass 25, count 2 2006.201.12:35:54.45#ibcon#read 4, iclass 25, count 2 2006.201.12:35:54.45#ibcon#about to read 5, iclass 25, count 2 2006.201.12:35:54.45#ibcon#read 5, iclass 25, count 2 2006.201.12:35:54.45#ibcon#about to read 6, iclass 25, count 2 2006.201.12:35:54.45#ibcon#read 6, iclass 25, count 2 2006.201.12:35:54.45#ibcon#end of sib2, iclass 25, count 2 2006.201.12:35:54.45#ibcon#*after write, iclass 25, count 2 2006.201.12:35:54.45#ibcon#*before return 0, iclass 25, count 2 2006.201.12:35:54.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:35:54.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:35:54.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.12:35:54.45#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:54.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:35:54.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:35:54.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:35:54.57#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:35:54.57#ibcon#first serial, iclass 25, count 0 2006.201.12:35:54.57#ibcon#enter sib2, iclass 25, count 0 2006.201.12:35:54.57#ibcon#flushed, iclass 25, count 0 2006.201.12:35:54.57#ibcon#about to write, iclass 25, count 0 2006.201.12:35:54.57#ibcon#wrote, iclass 25, count 0 2006.201.12:35:54.57#ibcon#about to read 3, iclass 25, count 0 2006.201.12:35:54.59#ibcon#read 3, iclass 25, count 0 2006.201.12:35:54.59#ibcon#about to read 4, iclass 25, count 0 2006.201.12:35:54.59#ibcon#read 4, iclass 25, count 0 2006.201.12:35:54.59#ibcon#about to read 5, iclass 25, count 0 2006.201.12:35:54.59#ibcon#read 5, iclass 25, count 0 2006.201.12:35:54.59#ibcon#about to read 6, iclass 25, count 0 2006.201.12:35:54.59#ibcon#read 6, iclass 25, count 0 2006.201.12:35:54.59#ibcon#end of sib2, iclass 25, count 0 2006.201.12:35:54.59#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:35:54.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:35:54.59#ibcon#[25=USB\r\n] 2006.201.12:35:54.59#ibcon#*before write, iclass 25, count 0 2006.201.12:35:54.59#ibcon#enter sib2, iclass 25, count 0 2006.201.12:35:54.59#ibcon#flushed, iclass 25, count 0 2006.201.12:35:54.59#ibcon#about to write, iclass 25, count 0 2006.201.12:35:54.59#ibcon#wrote, iclass 25, count 0 2006.201.12:35:54.59#ibcon#about to read 3, iclass 25, count 0 2006.201.12:35:54.62#ibcon#read 3, iclass 25, count 0 2006.201.12:35:54.62#ibcon#about to read 4, iclass 25, count 0 2006.201.12:35:54.62#ibcon#read 4, iclass 25, count 0 2006.201.12:35:54.62#ibcon#about to read 5, iclass 25, count 0 2006.201.12:35:54.62#ibcon#read 5, iclass 25, count 0 2006.201.12:35:54.62#ibcon#about to read 6, iclass 25, count 0 2006.201.12:35:54.62#ibcon#read 6, iclass 25, count 0 2006.201.12:35:54.62#ibcon#end of sib2, iclass 25, count 0 2006.201.12:35:54.62#ibcon#*after write, iclass 25, count 0 2006.201.12:35:54.62#ibcon#*before return 0, iclass 25, count 0 2006.201.12:35:54.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:35:54.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:35:54.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:35:54.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:35:54.62$vck44/valo=6,814.99 2006.201.12:35:54.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.12:35:54.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.12:35:54.62#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:54.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:35:54.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:35:54.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:35:54.62#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:35:54.62#ibcon#first serial, iclass 27, count 0 2006.201.12:35:54.62#ibcon#enter sib2, iclass 27, count 0 2006.201.12:35:54.62#ibcon#flushed, iclass 27, count 0 2006.201.12:35:54.62#ibcon#about to write, iclass 27, count 0 2006.201.12:35:54.62#ibcon#wrote, iclass 27, count 0 2006.201.12:35:54.62#ibcon#about to read 3, iclass 27, count 0 2006.201.12:35:54.64#ibcon#read 3, iclass 27, count 0 2006.201.12:35:54.64#ibcon#about to read 4, iclass 27, count 0 2006.201.12:35:54.64#ibcon#read 4, iclass 27, count 0 2006.201.12:35:54.64#ibcon#about to read 5, iclass 27, count 0 2006.201.12:35:54.64#ibcon#read 5, iclass 27, count 0 2006.201.12:35:54.64#ibcon#about to read 6, iclass 27, count 0 2006.201.12:35:54.64#ibcon#read 6, iclass 27, count 0 2006.201.12:35:54.64#ibcon#end of sib2, iclass 27, count 0 2006.201.12:35:54.64#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:35:54.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:35:54.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:35:54.64#ibcon#*before write, iclass 27, count 0 2006.201.12:35:54.64#ibcon#enter sib2, iclass 27, count 0 2006.201.12:35:54.64#ibcon#flushed, iclass 27, count 0 2006.201.12:35:54.64#ibcon#about to write, iclass 27, count 0 2006.201.12:35:54.64#ibcon#wrote, iclass 27, count 0 2006.201.12:35:54.64#ibcon#about to read 3, iclass 27, count 0 2006.201.12:35:54.69#ibcon#read 3, iclass 27, count 0 2006.201.12:35:54.69#ibcon#about to read 4, iclass 27, count 0 2006.201.12:35:54.69#ibcon#read 4, iclass 27, count 0 2006.201.12:35:54.69#ibcon#about to read 5, iclass 27, count 0 2006.201.12:35:54.69#ibcon#read 5, iclass 27, count 0 2006.201.12:35:54.69#ibcon#about to read 6, iclass 27, count 0 2006.201.12:35:54.69#ibcon#read 6, iclass 27, count 0 2006.201.12:35:54.69#ibcon#end of sib2, iclass 27, count 0 2006.201.12:35:54.69#ibcon#*after write, iclass 27, count 0 2006.201.12:35:54.69#ibcon#*before return 0, iclass 27, count 0 2006.201.12:35:54.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:35:54.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:35:54.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:35:54.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:35:54.69$vck44/va=6,5 2006.201.12:35:54.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.12:35:54.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.12:35:54.69#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:54.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:35:54.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:35:54.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:35:54.74#ibcon#enter wrdev, iclass 29, count 2 2006.201.12:35:54.74#ibcon#first serial, iclass 29, count 2 2006.201.12:35:54.74#ibcon#enter sib2, iclass 29, count 2 2006.201.12:35:54.74#ibcon#flushed, iclass 29, count 2 2006.201.12:35:54.74#ibcon#about to write, iclass 29, count 2 2006.201.12:35:54.74#ibcon#wrote, iclass 29, count 2 2006.201.12:35:54.74#ibcon#about to read 3, iclass 29, count 2 2006.201.12:35:54.76#ibcon#read 3, iclass 29, count 2 2006.201.12:35:54.76#ibcon#about to read 4, iclass 29, count 2 2006.201.12:35:54.76#ibcon#read 4, iclass 29, count 2 2006.201.12:35:54.76#ibcon#about to read 5, iclass 29, count 2 2006.201.12:35:54.76#ibcon#read 5, iclass 29, count 2 2006.201.12:35:54.76#ibcon#about to read 6, iclass 29, count 2 2006.201.12:35:54.76#ibcon#read 6, iclass 29, count 2 2006.201.12:35:54.76#ibcon#end of sib2, iclass 29, count 2 2006.201.12:35:54.76#ibcon#*mode == 0, iclass 29, count 2 2006.201.12:35:54.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.12:35:54.76#ibcon#[25=AT06-05\r\n] 2006.201.12:35:54.76#ibcon#*before write, iclass 29, count 2 2006.201.12:35:54.76#ibcon#enter sib2, iclass 29, count 2 2006.201.12:35:54.76#ibcon#flushed, iclass 29, count 2 2006.201.12:35:54.76#ibcon#about to write, iclass 29, count 2 2006.201.12:35:54.76#ibcon#wrote, iclass 29, count 2 2006.201.12:35:54.76#ibcon#about to read 3, iclass 29, count 2 2006.201.12:35:54.79#ibcon#read 3, iclass 29, count 2 2006.201.12:35:54.79#ibcon#about to read 4, iclass 29, count 2 2006.201.12:35:54.79#ibcon#read 4, iclass 29, count 2 2006.201.12:35:54.79#ibcon#about to read 5, iclass 29, count 2 2006.201.12:35:54.79#ibcon#read 5, iclass 29, count 2 2006.201.12:35:54.79#ibcon#about to read 6, iclass 29, count 2 2006.201.12:35:54.79#ibcon#read 6, iclass 29, count 2 2006.201.12:35:54.79#ibcon#end of sib2, iclass 29, count 2 2006.201.12:35:54.79#ibcon#*after write, iclass 29, count 2 2006.201.12:35:54.79#ibcon#*before return 0, iclass 29, count 2 2006.201.12:35:54.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:35:54.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:35:54.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.12:35:54.79#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:54.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:35:54.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:35:54.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:35:54.91#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:35:54.91#ibcon#first serial, iclass 29, count 0 2006.201.12:35:54.91#ibcon#enter sib2, iclass 29, count 0 2006.201.12:35:54.91#ibcon#flushed, iclass 29, count 0 2006.201.12:35:54.91#ibcon#about to write, iclass 29, count 0 2006.201.12:35:54.91#ibcon#wrote, iclass 29, count 0 2006.201.12:35:54.91#ibcon#about to read 3, iclass 29, count 0 2006.201.12:35:54.93#ibcon#read 3, iclass 29, count 0 2006.201.12:35:54.93#ibcon#about to read 4, iclass 29, count 0 2006.201.12:35:54.93#ibcon#read 4, iclass 29, count 0 2006.201.12:35:54.93#ibcon#about to read 5, iclass 29, count 0 2006.201.12:35:54.93#ibcon#read 5, iclass 29, count 0 2006.201.12:35:54.93#ibcon#about to read 6, iclass 29, count 0 2006.201.12:35:54.93#ibcon#read 6, iclass 29, count 0 2006.201.12:35:54.93#ibcon#end of sib2, iclass 29, count 0 2006.201.12:35:54.93#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:35:54.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:35:54.93#ibcon#[25=USB\r\n] 2006.201.12:35:54.93#ibcon#*before write, iclass 29, count 0 2006.201.12:35:54.93#ibcon#enter sib2, iclass 29, count 0 2006.201.12:35:54.93#ibcon#flushed, iclass 29, count 0 2006.201.12:35:54.93#ibcon#about to write, iclass 29, count 0 2006.201.12:35:54.93#ibcon#wrote, iclass 29, count 0 2006.201.12:35:54.93#ibcon#about to read 3, iclass 29, count 0 2006.201.12:35:54.96#ibcon#read 3, iclass 29, count 0 2006.201.12:35:54.96#ibcon#about to read 4, iclass 29, count 0 2006.201.12:35:54.96#ibcon#read 4, iclass 29, count 0 2006.201.12:35:54.96#ibcon#about to read 5, iclass 29, count 0 2006.201.12:35:54.96#ibcon#read 5, iclass 29, count 0 2006.201.12:35:54.96#ibcon#about to read 6, iclass 29, count 0 2006.201.12:35:54.96#ibcon#read 6, iclass 29, count 0 2006.201.12:35:54.96#ibcon#end of sib2, iclass 29, count 0 2006.201.12:35:54.96#ibcon#*after write, iclass 29, count 0 2006.201.12:35:54.96#ibcon#*before return 0, iclass 29, count 0 2006.201.12:35:54.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:35:54.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:35:54.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:35:54.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:35:54.96$vck44/valo=7,864.99 2006.201.12:35:54.96#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.12:35:54.96#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.12:35:54.96#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:54.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:54.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:54.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:54.96#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:35:54.96#ibcon#first serial, iclass 32, count 0 2006.201.12:35:54.96#ibcon#enter sib2, iclass 32, count 0 2006.201.12:35:54.96#ibcon#flushed, iclass 32, count 0 2006.201.12:35:54.96#ibcon#about to write, iclass 32, count 0 2006.201.12:35:54.96#ibcon#wrote, iclass 32, count 0 2006.201.12:35:54.96#ibcon#about to read 3, iclass 32, count 0 2006.201.12:35:54.98#ibcon#read 3, iclass 32, count 0 2006.201.12:35:54.98#ibcon#about to read 4, iclass 32, count 0 2006.201.12:35:54.98#ibcon#read 4, iclass 32, count 0 2006.201.12:35:54.98#ibcon#about to read 5, iclass 32, count 0 2006.201.12:35:54.98#ibcon#read 5, iclass 32, count 0 2006.201.12:35:54.98#ibcon#about to read 6, iclass 32, count 0 2006.201.12:35:54.98#ibcon#read 6, iclass 32, count 0 2006.201.12:35:54.98#ibcon#end of sib2, iclass 32, count 0 2006.201.12:35:54.98#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:35:54.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:35:54.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:35:54.98#ibcon#*before write, iclass 32, count 0 2006.201.12:35:54.98#ibcon#enter sib2, iclass 32, count 0 2006.201.12:35:54.98#ibcon#flushed, iclass 32, count 0 2006.201.12:35:54.98#ibcon#about to write, iclass 32, count 0 2006.201.12:35:54.98#ibcon#wrote, iclass 32, count 0 2006.201.12:35:54.98#ibcon#about to read 3, iclass 32, count 0 2006.201.12:35:55.03#ibcon#read 3, iclass 32, count 0 2006.201.12:35:55.03#ibcon#about to read 4, iclass 32, count 0 2006.201.12:35:55.03#ibcon#read 4, iclass 32, count 0 2006.201.12:35:55.03#ibcon#about to read 5, iclass 32, count 0 2006.201.12:35:55.03#ibcon#read 5, iclass 32, count 0 2006.201.12:35:55.03#ibcon#about to read 6, iclass 32, count 0 2006.201.12:35:55.03#ibcon#read 6, iclass 32, count 0 2006.201.12:35:55.03#ibcon#end of sib2, iclass 32, count 0 2006.201.12:35:55.03#ibcon#*after write, iclass 32, count 0 2006.201.12:35:55.03#ibcon#*before return 0, iclass 32, count 0 2006.201.12:35:55.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:55.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:55.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:35:55.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:35:55.03$vck44/va=7,5 2006.201.12:35:55.03#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.12:35:55.03#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.12:35:55.03#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:55.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:55.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:55.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:55.08#ibcon#enter wrdev, iclass 34, count 2 2006.201.12:35:55.08#ibcon#first serial, iclass 34, count 2 2006.201.12:35:55.08#ibcon#enter sib2, iclass 34, count 2 2006.201.12:35:55.08#ibcon#flushed, iclass 34, count 2 2006.201.12:35:55.08#ibcon#about to write, iclass 34, count 2 2006.201.12:35:55.08#ibcon#wrote, iclass 34, count 2 2006.201.12:35:55.08#ibcon#about to read 3, iclass 34, count 2 2006.201.12:35:55.10#ibcon#read 3, iclass 34, count 2 2006.201.12:35:55.10#ibcon#about to read 4, iclass 34, count 2 2006.201.12:35:55.10#ibcon#read 4, iclass 34, count 2 2006.201.12:35:55.10#ibcon#about to read 5, iclass 34, count 2 2006.201.12:35:55.10#ibcon#read 5, iclass 34, count 2 2006.201.12:35:55.10#ibcon#about to read 6, iclass 34, count 2 2006.201.12:35:55.10#ibcon#read 6, iclass 34, count 2 2006.201.12:35:55.10#ibcon#end of sib2, iclass 34, count 2 2006.201.12:35:55.10#ibcon#*mode == 0, iclass 34, count 2 2006.201.12:35:55.10#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.12:35:55.10#ibcon#[25=AT07-05\r\n] 2006.201.12:35:55.10#ibcon#*before write, iclass 34, count 2 2006.201.12:35:55.10#ibcon#enter sib2, iclass 34, count 2 2006.201.12:35:55.10#ibcon#flushed, iclass 34, count 2 2006.201.12:35:55.10#ibcon#about to write, iclass 34, count 2 2006.201.12:35:55.10#ibcon#wrote, iclass 34, count 2 2006.201.12:35:55.10#ibcon#about to read 3, iclass 34, count 2 2006.201.12:35:55.13#ibcon#read 3, iclass 34, count 2 2006.201.12:35:55.13#ibcon#about to read 4, iclass 34, count 2 2006.201.12:35:55.13#ibcon#read 4, iclass 34, count 2 2006.201.12:35:55.13#ibcon#about to read 5, iclass 34, count 2 2006.201.12:35:55.13#ibcon#read 5, iclass 34, count 2 2006.201.12:35:55.13#ibcon#about to read 6, iclass 34, count 2 2006.201.12:35:55.13#ibcon#read 6, iclass 34, count 2 2006.201.12:35:55.13#ibcon#end of sib2, iclass 34, count 2 2006.201.12:35:55.13#ibcon#*after write, iclass 34, count 2 2006.201.12:35:55.13#ibcon#*before return 0, iclass 34, count 2 2006.201.12:35:55.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:55.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:55.13#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.12:35:55.13#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:55.13#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:55.25#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:55.25#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:55.25#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:35:55.25#ibcon#first serial, iclass 34, count 0 2006.201.12:35:55.25#ibcon#enter sib2, iclass 34, count 0 2006.201.12:35:55.25#ibcon#flushed, iclass 34, count 0 2006.201.12:35:55.25#ibcon#about to write, iclass 34, count 0 2006.201.12:35:55.25#ibcon#wrote, iclass 34, count 0 2006.201.12:35:55.25#ibcon#about to read 3, iclass 34, count 0 2006.201.12:35:55.27#ibcon#read 3, iclass 34, count 0 2006.201.12:35:55.27#ibcon#about to read 4, iclass 34, count 0 2006.201.12:35:55.27#ibcon#read 4, iclass 34, count 0 2006.201.12:35:55.27#ibcon#about to read 5, iclass 34, count 0 2006.201.12:35:55.27#ibcon#read 5, iclass 34, count 0 2006.201.12:35:55.27#ibcon#about to read 6, iclass 34, count 0 2006.201.12:35:55.27#ibcon#read 6, iclass 34, count 0 2006.201.12:35:55.27#ibcon#end of sib2, iclass 34, count 0 2006.201.12:35:55.27#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:35:55.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:35:55.27#ibcon#[25=USB\r\n] 2006.201.12:35:55.27#ibcon#*before write, iclass 34, count 0 2006.201.12:35:55.27#ibcon#enter sib2, iclass 34, count 0 2006.201.12:35:55.27#ibcon#flushed, iclass 34, count 0 2006.201.12:35:55.27#ibcon#about to write, iclass 34, count 0 2006.201.12:35:55.27#ibcon#wrote, iclass 34, count 0 2006.201.12:35:55.27#ibcon#about to read 3, iclass 34, count 0 2006.201.12:35:55.30#ibcon#read 3, iclass 34, count 0 2006.201.12:35:55.30#ibcon#about to read 4, iclass 34, count 0 2006.201.12:35:55.30#ibcon#read 4, iclass 34, count 0 2006.201.12:35:55.30#ibcon#about to read 5, iclass 34, count 0 2006.201.12:35:55.30#ibcon#read 5, iclass 34, count 0 2006.201.12:35:55.30#ibcon#about to read 6, iclass 34, count 0 2006.201.12:35:55.30#ibcon#read 6, iclass 34, count 0 2006.201.12:35:55.30#ibcon#end of sib2, iclass 34, count 0 2006.201.12:35:55.30#ibcon#*after write, iclass 34, count 0 2006.201.12:35:55.30#ibcon#*before return 0, iclass 34, count 0 2006.201.12:35:55.30#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:55.30#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:55.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:35:55.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:35:55.30$vck44/valo=8,884.99 2006.201.12:35:55.30#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.12:35:55.30#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.12:35:55.30#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:55.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:55.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:55.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:55.30#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:35:55.30#ibcon#first serial, iclass 36, count 0 2006.201.12:35:55.30#ibcon#enter sib2, iclass 36, count 0 2006.201.12:35:55.30#ibcon#flushed, iclass 36, count 0 2006.201.12:35:55.30#ibcon#about to write, iclass 36, count 0 2006.201.12:35:55.30#ibcon#wrote, iclass 36, count 0 2006.201.12:35:55.30#ibcon#about to read 3, iclass 36, count 0 2006.201.12:35:55.32#ibcon#read 3, iclass 36, count 0 2006.201.12:35:55.32#ibcon#about to read 4, iclass 36, count 0 2006.201.12:35:55.32#ibcon#read 4, iclass 36, count 0 2006.201.12:35:55.32#ibcon#about to read 5, iclass 36, count 0 2006.201.12:35:55.32#ibcon#read 5, iclass 36, count 0 2006.201.12:35:55.32#ibcon#about to read 6, iclass 36, count 0 2006.201.12:35:55.32#ibcon#read 6, iclass 36, count 0 2006.201.12:35:55.32#ibcon#end of sib2, iclass 36, count 0 2006.201.12:35:55.32#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:35:55.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:35:55.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:35:55.32#ibcon#*before write, iclass 36, count 0 2006.201.12:35:55.32#ibcon#enter sib2, iclass 36, count 0 2006.201.12:35:55.32#ibcon#flushed, iclass 36, count 0 2006.201.12:35:55.32#ibcon#about to write, iclass 36, count 0 2006.201.12:35:55.32#ibcon#wrote, iclass 36, count 0 2006.201.12:35:55.32#ibcon#about to read 3, iclass 36, count 0 2006.201.12:35:55.36#ibcon#read 3, iclass 36, count 0 2006.201.12:35:55.36#ibcon#about to read 4, iclass 36, count 0 2006.201.12:35:55.36#ibcon#read 4, iclass 36, count 0 2006.201.12:35:55.36#ibcon#about to read 5, iclass 36, count 0 2006.201.12:35:55.36#ibcon#read 5, iclass 36, count 0 2006.201.12:35:55.36#ibcon#about to read 6, iclass 36, count 0 2006.201.12:35:55.36#ibcon#read 6, iclass 36, count 0 2006.201.12:35:55.36#ibcon#end of sib2, iclass 36, count 0 2006.201.12:35:55.36#ibcon#*after write, iclass 36, count 0 2006.201.12:35:55.36#ibcon#*before return 0, iclass 36, count 0 2006.201.12:35:55.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:55.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:55.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:35:55.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:35:55.36$vck44/va=8,4 2006.201.12:35:55.36#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.12:35:55.36#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.12:35:55.36#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:55.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:35:55.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:35:55.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:35:55.42#ibcon#enter wrdev, iclass 38, count 2 2006.201.12:35:55.42#ibcon#first serial, iclass 38, count 2 2006.201.12:35:55.42#ibcon#enter sib2, iclass 38, count 2 2006.201.12:35:55.42#ibcon#flushed, iclass 38, count 2 2006.201.12:35:55.42#ibcon#about to write, iclass 38, count 2 2006.201.12:35:55.42#ibcon#wrote, iclass 38, count 2 2006.201.12:35:55.42#ibcon#about to read 3, iclass 38, count 2 2006.201.12:35:55.44#ibcon#read 3, iclass 38, count 2 2006.201.12:35:55.44#ibcon#about to read 4, iclass 38, count 2 2006.201.12:35:55.44#ibcon#read 4, iclass 38, count 2 2006.201.12:35:55.44#ibcon#about to read 5, iclass 38, count 2 2006.201.12:35:55.44#ibcon#read 5, iclass 38, count 2 2006.201.12:35:55.44#ibcon#about to read 6, iclass 38, count 2 2006.201.12:35:55.44#ibcon#read 6, iclass 38, count 2 2006.201.12:35:55.44#ibcon#end of sib2, iclass 38, count 2 2006.201.12:35:55.44#ibcon#*mode == 0, iclass 38, count 2 2006.201.12:35:55.44#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.12:35:55.44#ibcon#[25=AT08-04\r\n] 2006.201.12:35:55.44#ibcon#*before write, iclass 38, count 2 2006.201.12:35:55.44#ibcon#enter sib2, iclass 38, count 2 2006.201.12:35:55.44#ibcon#flushed, iclass 38, count 2 2006.201.12:35:55.44#ibcon#about to write, iclass 38, count 2 2006.201.12:35:55.44#ibcon#wrote, iclass 38, count 2 2006.201.12:35:55.44#ibcon#about to read 3, iclass 38, count 2 2006.201.12:35:55.47#ibcon#read 3, iclass 38, count 2 2006.201.12:35:55.47#ibcon#about to read 4, iclass 38, count 2 2006.201.12:35:55.47#ibcon#read 4, iclass 38, count 2 2006.201.12:35:55.47#ibcon#about to read 5, iclass 38, count 2 2006.201.12:35:55.47#ibcon#read 5, iclass 38, count 2 2006.201.12:35:55.47#ibcon#about to read 6, iclass 38, count 2 2006.201.12:35:55.47#ibcon#read 6, iclass 38, count 2 2006.201.12:35:55.47#ibcon#end of sib2, iclass 38, count 2 2006.201.12:35:55.47#ibcon#*after write, iclass 38, count 2 2006.201.12:35:55.47#ibcon#*before return 0, iclass 38, count 2 2006.201.12:35:55.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:35:55.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.12:35:55.47#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.12:35:55.47#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:55.47#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:35:55.59#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:35:55.59#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:35:55.59#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:35:55.59#ibcon#first serial, iclass 38, count 0 2006.201.12:35:55.59#ibcon#enter sib2, iclass 38, count 0 2006.201.12:35:55.59#ibcon#flushed, iclass 38, count 0 2006.201.12:35:55.59#ibcon#about to write, iclass 38, count 0 2006.201.12:35:55.59#ibcon#wrote, iclass 38, count 0 2006.201.12:35:55.59#ibcon#about to read 3, iclass 38, count 0 2006.201.12:35:55.61#ibcon#read 3, iclass 38, count 0 2006.201.12:35:55.61#ibcon#about to read 4, iclass 38, count 0 2006.201.12:35:55.61#ibcon#read 4, iclass 38, count 0 2006.201.12:35:55.61#ibcon#about to read 5, iclass 38, count 0 2006.201.12:35:55.61#ibcon#read 5, iclass 38, count 0 2006.201.12:35:55.61#ibcon#about to read 6, iclass 38, count 0 2006.201.12:35:55.61#ibcon#read 6, iclass 38, count 0 2006.201.12:35:55.61#ibcon#end of sib2, iclass 38, count 0 2006.201.12:35:55.61#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:35:55.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:35:55.61#ibcon#[25=USB\r\n] 2006.201.12:35:55.61#ibcon#*before write, iclass 38, count 0 2006.201.12:35:55.61#ibcon#enter sib2, iclass 38, count 0 2006.201.12:35:55.61#ibcon#flushed, iclass 38, count 0 2006.201.12:35:55.61#ibcon#about to write, iclass 38, count 0 2006.201.12:35:55.61#ibcon#wrote, iclass 38, count 0 2006.201.12:35:55.61#ibcon#about to read 3, iclass 38, count 0 2006.201.12:35:55.64#ibcon#read 3, iclass 38, count 0 2006.201.12:35:55.64#ibcon#about to read 4, iclass 38, count 0 2006.201.12:35:55.64#ibcon#read 4, iclass 38, count 0 2006.201.12:35:55.64#ibcon#about to read 5, iclass 38, count 0 2006.201.12:35:55.64#ibcon#read 5, iclass 38, count 0 2006.201.12:35:55.64#ibcon#about to read 6, iclass 38, count 0 2006.201.12:35:55.64#ibcon#read 6, iclass 38, count 0 2006.201.12:35:55.64#ibcon#end of sib2, iclass 38, count 0 2006.201.12:35:55.64#ibcon#*after write, iclass 38, count 0 2006.201.12:35:55.64#ibcon#*before return 0, iclass 38, count 0 2006.201.12:35:55.64#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:35:55.64#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.12:35:55.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:35:55.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:35:55.64$vck44/vblo=1,629.99 2006.201.12:35:55.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.12:35:55.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.12:35:55.64#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:55.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:35:55.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:35:55.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:35:55.64#ibcon#enter wrdev, iclass 40, count 0 2006.201.12:35:55.64#ibcon#first serial, iclass 40, count 0 2006.201.12:35:55.64#ibcon#enter sib2, iclass 40, count 0 2006.201.12:35:55.64#ibcon#flushed, iclass 40, count 0 2006.201.12:35:55.64#ibcon#about to write, iclass 40, count 0 2006.201.12:35:55.64#ibcon#wrote, iclass 40, count 0 2006.201.12:35:55.64#ibcon#about to read 3, iclass 40, count 0 2006.201.12:35:55.66#ibcon#read 3, iclass 40, count 0 2006.201.12:35:55.66#ibcon#about to read 4, iclass 40, count 0 2006.201.12:35:55.66#ibcon#read 4, iclass 40, count 0 2006.201.12:35:55.66#ibcon#about to read 5, iclass 40, count 0 2006.201.12:35:55.66#ibcon#read 5, iclass 40, count 0 2006.201.12:35:55.66#ibcon#about to read 6, iclass 40, count 0 2006.201.12:35:55.66#ibcon#read 6, iclass 40, count 0 2006.201.12:35:55.66#ibcon#end of sib2, iclass 40, count 0 2006.201.12:35:55.66#ibcon#*mode == 0, iclass 40, count 0 2006.201.12:35:55.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.12:35:55.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:35:55.66#ibcon#*before write, iclass 40, count 0 2006.201.12:35:55.66#ibcon#enter sib2, iclass 40, count 0 2006.201.12:35:55.66#ibcon#flushed, iclass 40, count 0 2006.201.12:35:55.66#ibcon#about to write, iclass 40, count 0 2006.201.12:35:55.66#ibcon#wrote, iclass 40, count 0 2006.201.12:35:55.66#ibcon#about to read 3, iclass 40, count 0 2006.201.12:35:55.71#ibcon#read 3, iclass 40, count 0 2006.201.12:35:55.71#ibcon#about to read 4, iclass 40, count 0 2006.201.12:35:55.71#ibcon#read 4, iclass 40, count 0 2006.201.12:35:55.71#ibcon#about to read 5, iclass 40, count 0 2006.201.12:35:55.71#ibcon#read 5, iclass 40, count 0 2006.201.12:35:55.71#ibcon#about to read 6, iclass 40, count 0 2006.201.12:35:55.71#ibcon#read 6, iclass 40, count 0 2006.201.12:35:55.71#ibcon#end of sib2, iclass 40, count 0 2006.201.12:35:55.71#ibcon#*after write, iclass 40, count 0 2006.201.12:35:55.71#ibcon#*before return 0, iclass 40, count 0 2006.201.12:35:55.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:35:55.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.12:35:55.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.12:35:55.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.12:35:55.71$vck44/vb=1,4 2006.201.12:35:55.71#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.12:35:55.71#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.12:35:55.71#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:55.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:35:55.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:35:55.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:35:55.71#ibcon#enter wrdev, iclass 4, count 2 2006.201.12:35:55.71#ibcon#first serial, iclass 4, count 2 2006.201.12:35:55.71#ibcon#enter sib2, iclass 4, count 2 2006.201.12:35:55.71#ibcon#flushed, iclass 4, count 2 2006.201.12:35:55.71#ibcon#about to write, iclass 4, count 2 2006.201.12:35:55.71#ibcon#wrote, iclass 4, count 2 2006.201.12:35:55.71#ibcon#about to read 3, iclass 4, count 2 2006.201.12:35:55.73#ibcon#read 3, iclass 4, count 2 2006.201.12:35:55.73#ibcon#about to read 4, iclass 4, count 2 2006.201.12:35:55.73#ibcon#read 4, iclass 4, count 2 2006.201.12:35:55.73#ibcon#about to read 5, iclass 4, count 2 2006.201.12:35:55.73#ibcon#read 5, iclass 4, count 2 2006.201.12:35:55.73#ibcon#about to read 6, iclass 4, count 2 2006.201.12:35:55.73#ibcon#read 6, iclass 4, count 2 2006.201.12:35:55.73#ibcon#end of sib2, iclass 4, count 2 2006.201.12:35:55.73#ibcon#*mode == 0, iclass 4, count 2 2006.201.12:35:55.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.12:35:55.73#ibcon#[27=AT01-04\r\n] 2006.201.12:35:55.73#ibcon#*before write, iclass 4, count 2 2006.201.12:35:55.73#ibcon#enter sib2, iclass 4, count 2 2006.201.12:35:55.73#ibcon#flushed, iclass 4, count 2 2006.201.12:35:55.73#ibcon#about to write, iclass 4, count 2 2006.201.12:35:55.73#ibcon#wrote, iclass 4, count 2 2006.201.12:35:55.73#ibcon#about to read 3, iclass 4, count 2 2006.201.12:35:55.76#ibcon#read 3, iclass 4, count 2 2006.201.12:35:55.76#ibcon#about to read 4, iclass 4, count 2 2006.201.12:35:55.76#ibcon#read 4, iclass 4, count 2 2006.201.12:35:55.76#ibcon#about to read 5, iclass 4, count 2 2006.201.12:35:55.76#ibcon#read 5, iclass 4, count 2 2006.201.12:35:55.76#ibcon#about to read 6, iclass 4, count 2 2006.201.12:35:55.76#ibcon#read 6, iclass 4, count 2 2006.201.12:35:55.76#ibcon#end of sib2, iclass 4, count 2 2006.201.12:35:55.76#ibcon#*after write, iclass 4, count 2 2006.201.12:35:55.76#ibcon#*before return 0, iclass 4, count 2 2006.201.12:35:55.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:35:55.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.12:35:55.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.12:35:55.76#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:55.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:35:55.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:35:55.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:35:55.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.12:35:55.88#ibcon#first serial, iclass 4, count 0 2006.201.12:35:55.88#ibcon#enter sib2, iclass 4, count 0 2006.201.12:35:55.88#ibcon#flushed, iclass 4, count 0 2006.201.12:35:55.88#ibcon#about to write, iclass 4, count 0 2006.201.12:35:55.88#ibcon#wrote, iclass 4, count 0 2006.201.12:35:55.88#ibcon#about to read 3, iclass 4, count 0 2006.201.12:35:55.90#ibcon#read 3, iclass 4, count 0 2006.201.12:35:55.90#ibcon#about to read 4, iclass 4, count 0 2006.201.12:35:55.90#ibcon#read 4, iclass 4, count 0 2006.201.12:35:55.90#ibcon#about to read 5, iclass 4, count 0 2006.201.12:35:55.90#ibcon#read 5, iclass 4, count 0 2006.201.12:35:55.90#ibcon#about to read 6, iclass 4, count 0 2006.201.12:35:55.90#ibcon#read 6, iclass 4, count 0 2006.201.12:35:55.90#ibcon#end of sib2, iclass 4, count 0 2006.201.12:35:55.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.12:35:55.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.12:35:55.90#ibcon#[27=USB\r\n] 2006.201.12:35:55.90#ibcon#*before write, iclass 4, count 0 2006.201.12:35:55.90#ibcon#enter sib2, iclass 4, count 0 2006.201.12:35:55.90#ibcon#flushed, iclass 4, count 0 2006.201.12:35:55.90#ibcon#about to write, iclass 4, count 0 2006.201.12:35:55.90#ibcon#wrote, iclass 4, count 0 2006.201.12:35:55.90#ibcon#about to read 3, iclass 4, count 0 2006.201.12:35:55.93#ibcon#read 3, iclass 4, count 0 2006.201.12:35:55.93#ibcon#about to read 4, iclass 4, count 0 2006.201.12:35:55.93#ibcon#read 4, iclass 4, count 0 2006.201.12:35:55.93#ibcon#about to read 5, iclass 4, count 0 2006.201.12:35:55.93#ibcon#read 5, iclass 4, count 0 2006.201.12:35:55.93#ibcon#about to read 6, iclass 4, count 0 2006.201.12:35:55.93#ibcon#read 6, iclass 4, count 0 2006.201.12:35:55.93#ibcon#end of sib2, iclass 4, count 0 2006.201.12:35:55.93#ibcon#*after write, iclass 4, count 0 2006.201.12:35:55.93#ibcon#*before return 0, iclass 4, count 0 2006.201.12:35:55.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:35:55.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.12:35:55.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.12:35:55.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.12:35:55.93$vck44/vblo=2,634.99 2006.201.12:35:55.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.12:35:55.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.12:35:55.93#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:55.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:35:55.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:35:55.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:35:55.93#ibcon#enter wrdev, iclass 6, count 0 2006.201.12:35:55.93#ibcon#first serial, iclass 6, count 0 2006.201.12:35:55.93#ibcon#enter sib2, iclass 6, count 0 2006.201.12:35:55.93#ibcon#flushed, iclass 6, count 0 2006.201.12:35:55.93#ibcon#about to write, iclass 6, count 0 2006.201.12:35:55.93#ibcon#wrote, iclass 6, count 0 2006.201.12:35:55.93#ibcon#about to read 3, iclass 6, count 0 2006.201.12:35:55.95#ibcon#read 3, iclass 6, count 0 2006.201.12:35:55.95#ibcon#about to read 4, iclass 6, count 0 2006.201.12:35:55.95#ibcon#read 4, iclass 6, count 0 2006.201.12:35:55.95#ibcon#about to read 5, iclass 6, count 0 2006.201.12:35:55.95#ibcon#read 5, iclass 6, count 0 2006.201.12:35:55.95#ibcon#about to read 6, iclass 6, count 0 2006.201.12:35:55.95#ibcon#read 6, iclass 6, count 0 2006.201.12:35:55.95#ibcon#end of sib2, iclass 6, count 0 2006.201.12:35:55.95#ibcon#*mode == 0, iclass 6, count 0 2006.201.12:35:55.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.12:35:55.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:35:55.95#ibcon#*before write, iclass 6, count 0 2006.201.12:35:55.95#ibcon#enter sib2, iclass 6, count 0 2006.201.12:35:55.95#ibcon#flushed, iclass 6, count 0 2006.201.12:35:55.95#ibcon#about to write, iclass 6, count 0 2006.201.12:35:55.95#ibcon#wrote, iclass 6, count 0 2006.201.12:35:55.95#ibcon#about to read 3, iclass 6, count 0 2006.201.12:35:55.99#ibcon#read 3, iclass 6, count 0 2006.201.12:35:55.99#ibcon#about to read 4, iclass 6, count 0 2006.201.12:35:55.99#ibcon#read 4, iclass 6, count 0 2006.201.12:35:55.99#ibcon#about to read 5, iclass 6, count 0 2006.201.12:35:55.99#ibcon#read 5, iclass 6, count 0 2006.201.12:35:55.99#ibcon#about to read 6, iclass 6, count 0 2006.201.12:35:55.99#ibcon#read 6, iclass 6, count 0 2006.201.12:35:55.99#ibcon#end of sib2, iclass 6, count 0 2006.201.12:35:55.99#ibcon#*after write, iclass 6, count 0 2006.201.12:35:55.99#ibcon#*before return 0, iclass 6, count 0 2006.201.12:35:55.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:35:55.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.12:35:55.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.12:35:55.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.12:35:55.99$vck44/vb=2,5 2006.201.12:35:55.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.12:35:55.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.12:35:55.99#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:55.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:35:56.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:35:56.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:35:56.05#ibcon#enter wrdev, iclass 10, count 2 2006.201.12:35:56.05#ibcon#first serial, iclass 10, count 2 2006.201.12:35:56.05#ibcon#enter sib2, iclass 10, count 2 2006.201.12:35:56.05#ibcon#flushed, iclass 10, count 2 2006.201.12:35:56.05#ibcon#about to write, iclass 10, count 2 2006.201.12:35:56.05#ibcon#wrote, iclass 10, count 2 2006.201.12:35:56.05#ibcon#about to read 3, iclass 10, count 2 2006.201.12:35:56.07#ibcon#read 3, iclass 10, count 2 2006.201.12:35:56.07#ibcon#about to read 4, iclass 10, count 2 2006.201.12:35:56.07#ibcon#read 4, iclass 10, count 2 2006.201.12:35:56.07#ibcon#about to read 5, iclass 10, count 2 2006.201.12:35:56.07#ibcon#read 5, iclass 10, count 2 2006.201.12:35:56.07#ibcon#about to read 6, iclass 10, count 2 2006.201.12:35:56.07#ibcon#read 6, iclass 10, count 2 2006.201.12:35:56.07#ibcon#end of sib2, iclass 10, count 2 2006.201.12:35:56.07#ibcon#*mode == 0, iclass 10, count 2 2006.201.12:35:56.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.12:35:56.07#ibcon#[27=AT02-05\r\n] 2006.201.12:35:56.07#ibcon#*before write, iclass 10, count 2 2006.201.12:35:56.07#ibcon#enter sib2, iclass 10, count 2 2006.201.12:35:56.07#ibcon#flushed, iclass 10, count 2 2006.201.12:35:56.07#ibcon#about to write, iclass 10, count 2 2006.201.12:35:56.07#ibcon#wrote, iclass 10, count 2 2006.201.12:35:56.07#ibcon#about to read 3, iclass 10, count 2 2006.201.12:35:56.10#ibcon#read 3, iclass 10, count 2 2006.201.12:35:56.10#ibcon#about to read 4, iclass 10, count 2 2006.201.12:35:56.10#ibcon#read 4, iclass 10, count 2 2006.201.12:35:56.10#ibcon#about to read 5, iclass 10, count 2 2006.201.12:35:56.10#ibcon#read 5, iclass 10, count 2 2006.201.12:35:56.10#ibcon#about to read 6, iclass 10, count 2 2006.201.12:35:56.10#ibcon#read 6, iclass 10, count 2 2006.201.12:35:56.10#ibcon#end of sib2, iclass 10, count 2 2006.201.12:35:56.10#ibcon#*after write, iclass 10, count 2 2006.201.12:35:56.10#ibcon#*before return 0, iclass 10, count 2 2006.201.12:35:56.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:35:56.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.12:35:56.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.12:35:56.10#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:56.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:35:56.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:35:56.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:35:56.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.12:35:56.22#ibcon#first serial, iclass 10, count 0 2006.201.12:35:56.22#ibcon#enter sib2, iclass 10, count 0 2006.201.12:35:56.22#ibcon#flushed, iclass 10, count 0 2006.201.12:35:56.22#ibcon#about to write, iclass 10, count 0 2006.201.12:35:56.22#ibcon#wrote, iclass 10, count 0 2006.201.12:35:56.22#ibcon#about to read 3, iclass 10, count 0 2006.201.12:35:56.24#ibcon#read 3, iclass 10, count 0 2006.201.12:35:56.24#ibcon#about to read 4, iclass 10, count 0 2006.201.12:35:56.24#ibcon#read 4, iclass 10, count 0 2006.201.12:35:56.24#ibcon#about to read 5, iclass 10, count 0 2006.201.12:35:56.24#ibcon#read 5, iclass 10, count 0 2006.201.12:35:56.24#ibcon#about to read 6, iclass 10, count 0 2006.201.12:35:56.24#ibcon#read 6, iclass 10, count 0 2006.201.12:35:56.24#ibcon#end of sib2, iclass 10, count 0 2006.201.12:35:56.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.12:35:56.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.12:35:56.24#ibcon#[27=USB\r\n] 2006.201.12:35:56.24#ibcon#*before write, iclass 10, count 0 2006.201.12:35:56.24#ibcon#enter sib2, iclass 10, count 0 2006.201.12:35:56.24#ibcon#flushed, iclass 10, count 0 2006.201.12:35:56.24#ibcon#about to write, iclass 10, count 0 2006.201.12:35:56.24#ibcon#wrote, iclass 10, count 0 2006.201.12:35:56.24#ibcon#about to read 3, iclass 10, count 0 2006.201.12:35:56.27#ibcon#read 3, iclass 10, count 0 2006.201.12:35:56.27#ibcon#about to read 4, iclass 10, count 0 2006.201.12:35:56.27#ibcon#read 4, iclass 10, count 0 2006.201.12:35:56.27#ibcon#about to read 5, iclass 10, count 0 2006.201.12:35:56.27#ibcon#read 5, iclass 10, count 0 2006.201.12:35:56.27#ibcon#about to read 6, iclass 10, count 0 2006.201.12:35:56.27#ibcon#read 6, iclass 10, count 0 2006.201.12:35:56.27#ibcon#end of sib2, iclass 10, count 0 2006.201.12:35:56.27#ibcon#*after write, iclass 10, count 0 2006.201.12:35:56.27#ibcon#*before return 0, iclass 10, count 0 2006.201.12:35:56.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:35:56.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.12:35:56.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.12:35:56.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.12:35:56.27$vck44/vblo=3,649.99 2006.201.12:35:56.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.12:35:56.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.12:35:56.27#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:56.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:35:56.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:35:56.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:35:56.27#ibcon#enter wrdev, iclass 12, count 0 2006.201.12:35:56.27#ibcon#first serial, iclass 12, count 0 2006.201.12:35:56.27#ibcon#enter sib2, iclass 12, count 0 2006.201.12:35:56.27#ibcon#flushed, iclass 12, count 0 2006.201.12:35:56.27#ibcon#about to write, iclass 12, count 0 2006.201.12:35:56.27#ibcon#wrote, iclass 12, count 0 2006.201.12:35:56.27#ibcon#about to read 3, iclass 12, count 0 2006.201.12:35:56.29#ibcon#read 3, iclass 12, count 0 2006.201.12:35:56.29#ibcon#about to read 4, iclass 12, count 0 2006.201.12:35:56.29#ibcon#read 4, iclass 12, count 0 2006.201.12:35:56.29#ibcon#about to read 5, iclass 12, count 0 2006.201.12:35:56.29#ibcon#read 5, iclass 12, count 0 2006.201.12:35:56.29#ibcon#about to read 6, iclass 12, count 0 2006.201.12:35:56.29#ibcon#read 6, iclass 12, count 0 2006.201.12:35:56.29#ibcon#end of sib2, iclass 12, count 0 2006.201.12:35:56.29#ibcon#*mode == 0, iclass 12, count 0 2006.201.12:35:56.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.12:35:56.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:35:56.29#ibcon#*before write, iclass 12, count 0 2006.201.12:35:56.29#ibcon#enter sib2, iclass 12, count 0 2006.201.12:35:56.29#ibcon#flushed, iclass 12, count 0 2006.201.12:35:56.29#ibcon#about to write, iclass 12, count 0 2006.201.12:35:56.29#ibcon#wrote, iclass 12, count 0 2006.201.12:35:56.29#ibcon#about to read 3, iclass 12, count 0 2006.201.12:35:56.33#ibcon#read 3, iclass 12, count 0 2006.201.12:35:56.33#ibcon#about to read 4, iclass 12, count 0 2006.201.12:35:56.33#ibcon#read 4, iclass 12, count 0 2006.201.12:35:56.33#ibcon#about to read 5, iclass 12, count 0 2006.201.12:35:56.33#ibcon#read 5, iclass 12, count 0 2006.201.12:35:56.33#ibcon#about to read 6, iclass 12, count 0 2006.201.12:35:56.33#ibcon#read 6, iclass 12, count 0 2006.201.12:35:56.33#ibcon#end of sib2, iclass 12, count 0 2006.201.12:35:56.33#ibcon#*after write, iclass 12, count 0 2006.201.12:35:56.33#ibcon#*before return 0, iclass 12, count 0 2006.201.12:35:56.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:35:56.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.12:35:56.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.12:35:56.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.12:35:56.33$vck44/vb=3,4 2006.201.12:35:56.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.12:35:56.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.12:35:56.33#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:56.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:35:56.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:35:56.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:35:56.39#ibcon#enter wrdev, iclass 14, count 2 2006.201.12:35:56.39#ibcon#first serial, iclass 14, count 2 2006.201.12:35:56.39#ibcon#enter sib2, iclass 14, count 2 2006.201.12:35:56.39#ibcon#flushed, iclass 14, count 2 2006.201.12:35:56.39#ibcon#about to write, iclass 14, count 2 2006.201.12:35:56.39#ibcon#wrote, iclass 14, count 2 2006.201.12:35:56.39#ibcon#about to read 3, iclass 14, count 2 2006.201.12:35:56.41#ibcon#read 3, iclass 14, count 2 2006.201.12:35:56.41#ibcon#about to read 4, iclass 14, count 2 2006.201.12:35:56.41#ibcon#read 4, iclass 14, count 2 2006.201.12:35:56.41#ibcon#about to read 5, iclass 14, count 2 2006.201.12:35:56.41#ibcon#read 5, iclass 14, count 2 2006.201.12:35:56.41#ibcon#about to read 6, iclass 14, count 2 2006.201.12:35:56.41#ibcon#read 6, iclass 14, count 2 2006.201.12:35:56.41#ibcon#end of sib2, iclass 14, count 2 2006.201.12:35:56.41#ibcon#*mode == 0, iclass 14, count 2 2006.201.12:35:56.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.12:35:56.41#ibcon#[27=AT03-04\r\n] 2006.201.12:35:56.41#ibcon#*before write, iclass 14, count 2 2006.201.12:35:56.41#ibcon#enter sib2, iclass 14, count 2 2006.201.12:35:56.41#ibcon#flushed, iclass 14, count 2 2006.201.12:35:56.41#ibcon#about to write, iclass 14, count 2 2006.201.12:35:56.41#ibcon#wrote, iclass 14, count 2 2006.201.12:35:56.41#ibcon#about to read 3, iclass 14, count 2 2006.201.12:35:56.44#ibcon#read 3, iclass 14, count 2 2006.201.12:35:56.44#ibcon#about to read 4, iclass 14, count 2 2006.201.12:35:56.44#ibcon#read 4, iclass 14, count 2 2006.201.12:35:56.44#ibcon#about to read 5, iclass 14, count 2 2006.201.12:35:56.44#ibcon#read 5, iclass 14, count 2 2006.201.12:35:56.44#ibcon#about to read 6, iclass 14, count 2 2006.201.12:35:56.44#ibcon#read 6, iclass 14, count 2 2006.201.12:35:56.44#ibcon#end of sib2, iclass 14, count 2 2006.201.12:35:56.44#ibcon#*after write, iclass 14, count 2 2006.201.12:35:56.44#ibcon#*before return 0, iclass 14, count 2 2006.201.12:35:56.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:35:56.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.12:35:56.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.12:35:56.44#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:56.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:35:56.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:35:56.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:35:56.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.12:35:56.56#ibcon#first serial, iclass 14, count 0 2006.201.12:35:56.56#ibcon#enter sib2, iclass 14, count 0 2006.201.12:35:56.56#ibcon#flushed, iclass 14, count 0 2006.201.12:35:56.56#ibcon#about to write, iclass 14, count 0 2006.201.12:35:56.56#ibcon#wrote, iclass 14, count 0 2006.201.12:35:56.56#ibcon#about to read 3, iclass 14, count 0 2006.201.12:35:56.58#ibcon#read 3, iclass 14, count 0 2006.201.12:35:56.58#ibcon#about to read 4, iclass 14, count 0 2006.201.12:35:56.58#ibcon#read 4, iclass 14, count 0 2006.201.12:35:56.58#ibcon#about to read 5, iclass 14, count 0 2006.201.12:35:56.58#ibcon#read 5, iclass 14, count 0 2006.201.12:35:56.58#ibcon#about to read 6, iclass 14, count 0 2006.201.12:35:56.58#ibcon#read 6, iclass 14, count 0 2006.201.12:35:56.58#ibcon#end of sib2, iclass 14, count 0 2006.201.12:35:56.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.12:35:56.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.12:35:56.58#ibcon#[27=USB\r\n] 2006.201.12:35:56.58#ibcon#*before write, iclass 14, count 0 2006.201.12:35:56.58#ibcon#enter sib2, iclass 14, count 0 2006.201.12:35:56.58#ibcon#flushed, iclass 14, count 0 2006.201.12:35:56.58#ibcon#about to write, iclass 14, count 0 2006.201.12:35:56.58#ibcon#wrote, iclass 14, count 0 2006.201.12:35:56.58#ibcon#about to read 3, iclass 14, count 0 2006.201.12:35:56.61#ibcon#read 3, iclass 14, count 0 2006.201.12:35:56.61#ibcon#about to read 4, iclass 14, count 0 2006.201.12:35:56.61#ibcon#read 4, iclass 14, count 0 2006.201.12:35:56.61#ibcon#about to read 5, iclass 14, count 0 2006.201.12:35:56.61#ibcon#read 5, iclass 14, count 0 2006.201.12:35:56.61#ibcon#about to read 6, iclass 14, count 0 2006.201.12:35:56.61#ibcon#read 6, iclass 14, count 0 2006.201.12:35:56.61#ibcon#end of sib2, iclass 14, count 0 2006.201.12:35:56.61#ibcon#*after write, iclass 14, count 0 2006.201.12:35:56.61#ibcon#*before return 0, iclass 14, count 0 2006.201.12:35:56.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:35:56.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.12:35:56.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.12:35:56.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.12:35:56.61$vck44/vblo=4,679.99 2006.201.12:35:56.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.12:35:56.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.12:35:56.61#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:56.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:35:56.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:35:56.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:35:56.61#ibcon#enter wrdev, iclass 16, count 0 2006.201.12:35:56.61#ibcon#first serial, iclass 16, count 0 2006.201.12:35:56.61#ibcon#enter sib2, iclass 16, count 0 2006.201.12:35:56.61#ibcon#flushed, iclass 16, count 0 2006.201.12:35:56.61#ibcon#about to write, iclass 16, count 0 2006.201.12:35:56.61#ibcon#wrote, iclass 16, count 0 2006.201.12:35:56.61#ibcon#about to read 3, iclass 16, count 0 2006.201.12:35:56.63#ibcon#read 3, iclass 16, count 0 2006.201.12:35:56.63#ibcon#about to read 4, iclass 16, count 0 2006.201.12:35:56.63#ibcon#read 4, iclass 16, count 0 2006.201.12:35:56.63#ibcon#about to read 5, iclass 16, count 0 2006.201.12:35:56.63#ibcon#read 5, iclass 16, count 0 2006.201.12:35:56.63#ibcon#about to read 6, iclass 16, count 0 2006.201.12:35:56.63#ibcon#read 6, iclass 16, count 0 2006.201.12:35:56.63#ibcon#end of sib2, iclass 16, count 0 2006.201.12:35:56.63#ibcon#*mode == 0, iclass 16, count 0 2006.201.12:35:56.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.12:35:56.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:35:56.63#ibcon#*before write, iclass 16, count 0 2006.201.12:35:56.63#ibcon#enter sib2, iclass 16, count 0 2006.201.12:35:56.63#ibcon#flushed, iclass 16, count 0 2006.201.12:35:56.63#ibcon#about to write, iclass 16, count 0 2006.201.12:35:56.63#ibcon#wrote, iclass 16, count 0 2006.201.12:35:56.63#ibcon#about to read 3, iclass 16, count 0 2006.201.12:35:56.68#ibcon#read 3, iclass 16, count 0 2006.201.12:35:56.68#ibcon#about to read 4, iclass 16, count 0 2006.201.12:35:56.68#ibcon#read 4, iclass 16, count 0 2006.201.12:35:56.68#ibcon#about to read 5, iclass 16, count 0 2006.201.12:35:56.68#ibcon#read 5, iclass 16, count 0 2006.201.12:35:56.68#ibcon#about to read 6, iclass 16, count 0 2006.201.12:35:56.68#ibcon#read 6, iclass 16, count 0 2006.201.12:35:56.68#ibcon#end of sib2, iclass 16, count 0 2006.201.12:35:56.68#ibcon#*after write, iclass 16, count 0 2006.201.12:35:56.68#ibcon#*before return 0, iclass 16, count 0 2006.201.12:35:56.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:35:56.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.12:35:56.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.12:35:56.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.12:35:56.68$vck44/vb=4,5 2006.201.12:35:56.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.12:35:56.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.12:35:56.68#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:56.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:35:56.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:35:56.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:35:56.73#ibcon#enter wrdev, iclass 18, count 2 2006.201.12:35:56.73#ibcon#first serial, iclass 18, count 2 2006.201.12:35:56.73#ibcon#enter sib2, iclass 18, count 2 2006.201.12:35:56.73#ibcon#flushed, iclass 18, count 2 2006.201.12:35:56.73#ibcon#about to write, iclass 18, count 2 2006.201.12:35:56.73#ibcon#wrote, iclass 18, count 2 2006.201.12:35:56.73#ibcon#about to read 3, iclass 18, count 2 2006.201.12:35:56.75#ibcon#read 3, iclass 18, count 2 2006.201.12:35:56.75#ibcon#about to read 4, iclass 18, count 2 2006.201.12:35:56.75#ibcon#read 4, iclass 18, count 2 2006.201.12:35:56.75#ibcon#about to read 5, iclass 18, count 2 2006.201.12:35:56.75#ibcon#read 5, iclass 18, count 2 2006.201.12:35:56.75#ibcon#about to read 6, iclass 18, count 2 2006.201.12:35:56.75#ibcon#read 6, iclass 18, count 2 2006.201.12:35:56.75#ibcon#end of sib2, iclass 18, count 2 2006.201.12:35:56.75#ibcon#*mode == 0, iclass 18, count 2 2006.201.12:35:56.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.12:35:56.75#ibcon#[27=AT04-05\r\n] 2006.201.12:35:56.75#ibcon#*before write, iclass 18, count 2 2006.201.12:35:56.75#ibcon#enter sib2, iclass 18, count 2 2006.201.12:35:56.75#ibcon#flushed, iclass 18, count 2 2006.201.12:35:56.75#ibcon#about to write, iclass 18, count 2 2006.201.12:35:56.75#ibcon#wrote, iclass 18, count 2 2006.201.12:35:56.75#ibcon#about to read 3, iclass 18, count 2 2006.201.12:35:56.78#ibcon#read 3, iclass 18, count 2 2006.201.12:35:56.78#ibcon#about to read 4, iclass 18, count 2 2006.201.12:35:56.78#ibcon#read 4, iclass 18, count 2 2006.201.12:35:56.78#ibcon#about to read 5, iclass 18, count 2 2006.201.12:35:56.78#ibcon#read 5, iclass 18, count 2 2006.201.12:35:56.78#ibcon#about to read 6, iclass 18, count 2 2006.201.12:35:56.78#ibcon#read 6, iclass 18, count 2 2006.201.12:35:56.78#ibcon#end of sib2, iclass 18, count 2 2006.201.12:35:56.78#ibcon#*after write, iclass 18, count 2 2006.201.12:35:56.78#ibcon#*before return 0, iclass 18, count 2 2006.201.12:35:56.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:35:56.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.12:35:56.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.12:35:56.78#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:56.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:35:56.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:35:56.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:35:56.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.12:35:56.90#ibcon#first serial, iclass 18, count 0 2006.201.12:35:56.90#ibcon#enter sib2, iclass 18, count 0 2006.201.12:35:56.90#ibcon#flushed, iclass 18, count 0 2006.201.12:35:56.90#ibcon#about to write, iclass 18, count 0 2006.201.12:35:56.90#ibcon#wrote, iclass 18, count 0 2006.201.12:35:56.90#ibcon#about to read 3, iclass 18, count 0 2006.201.12:35:56.92#ibcon#read 3, iclass 18, count 0 2006.201.12:35:56.92#ibcon#about to read 4, iclass 18, count 0 2006.201.12:35:56.92#ibcon#read 4, iclass 18, count 0 2006.201.12:35:56.92#ibcon#about to read 5, iclass 18, count 0 2006.201.12:35:56.92#ibcon#read 5, iclass 18, count 0 2006.201.12:35:56.92#ibcon#about to read 6, iclass 18, count 0 2006.201.12:35:56.92#ibcon#read 6, iclass 18, count 0 2006.201.12:35:56.92#ibcon#end of sib2, iclass 18, count 0 2006.201.12:35:56.92#ibcon#*mode == 0, iclass 18, count 0 2006.201.12:35:56.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.12:35:56.92#ibcon#[27=USB\r\n] 2006.201.12:35:56.92#ibcon#*before write, iclass 18, count 0 2006.201.12:35:56.92#ibcon#enter sib2, iclass 18, count 0 2006.201.12:35:56.92#ibcon#flushed, iclass 18, count 0 2006.201.12:35:56.92#ibcon#about to write, iclass 18, count 0 2006.201.12:35:56.92#ibcon#wrote, iclass 18, count 0 2006.201.12:35:56.92#ibcon#about to read 3, iclass 18, count 0 2006.201.12:35:56.95#ibcon#read 3, iclass 18, count 0 2006.201.12:35:56.95#ibcon#about to read 4, iclass 18, count 0 2006.201.12:35:56.95#ibcon#read 4, iclass 18, count 0 2006.201.12:35:56.95#ibcon#about to read 5, iclass 18, count 0 2006.201.12:35:56.95#ibcon#read 5, iclass 18, count 0 2006.201.12:35:56.95#ibcon#about to read 6, iclass 18, count 0 2006.201.12:35:56.95#ibcon#read 6, iclass 18, count 0 2006.201.12:35:56.95#ibcon#end of sib2, iclass 18, count 0 2006.201.12:35:56.95#ibcon#*after write, iclass 18, count 0 2006.201.12:35:56.95#ibcon#*before return 0, iclass 18, count 0 2006.201.12:35:56.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:35:56.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.12:35:56.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.12:35:56.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.12:35:56.95$vck44/vblo=5,709.99 2006.201.12:35:56.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.12:35:56.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.12:35:56.95#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:56.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:35:56.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:35:56.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:35:56.95#ibcon#enter wrdev, iclass 20, count 0 2006.201.12:35:56.95#ibcon#first serial, iclass 20, count 0 2006.201.12:35:56.95#ibcon#enter sib2, iclass 20, count 0 2006.201.12:35:56.95#ibcon#flushed, iclass 20, count 0 2006.201.12:35:56.95#ibcon#about to write, iclass 20, count 0 2006.201.12:35:56.95#ibcon#wrote, iclass 20, count 0 2006.201.12:35:56.95#ibcon#about to read 3, iclass 20, count 0 2006.201.12:35:56.97#ibcon#read 3, iclass 20, count 0 2006.201.12:35:56.97#ibcon#about to read 4, iclass 20, count 0 2006.201.12:35:56.97#ibcon#read 4, iclass 20, count 0 2006.201.12:35:56.97#ibcon#about to read 5, iclass 20, count 0 2006.201.12:35:56.97#ibcon#read 5, iclass 20, count 0 2006.201.12:35:56.97#ibcon#about to read 6, iclass 20, count 0 2006.201.12:35:56.97#ibcon#read 6, iclass 20, count 0 2006.201.12:35:56.97#ibcon#end of sib2, iclass 20, count 0 2006.201.12:35:56.97#ibcon#*mode == 0, iclass 20, count 0 2006.201.12:35:56.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.12:35:56.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:35:56.97#ibcon#*before write, iclass 20, count 0 2006.201.12:35:56.97#ibcon#enter sib2, iclass 20, count 0 2006.201.12:35:56.97#ibcon#flushed, iclass 20, count 0 2006.201.12:35:56.97#ibcon#about to write, iclass 20, count 0 2006.201.12:35:56.97#ibcon#wrote, iclass 20, count 0 2006.201.12:35:56.97#ibcon#about to read 3, iclass 20, count 0 2006.201.12:35:57.01#ibcon#read 3, iclass 20, count 0 2006.201.12:35:57.01#ibcon#about to read 4, iclass 20, count 0 2006.201.12:35:57.01#ibcon#read 4, iclass 20, count 0 2006.201.12:35:57.01#ibcon#about to read 5, iclass 20, count 0 2006.201.12:35:57.01#ibcon#read 5, iclass 20, count 0 2006.201.12:35:57.01#ibcon#about to read 6, iclass 20, count 0 2006.201.12:35:57.01#ibcon#read 6, iclass 20, count 0 2006.201.12:35:57.01#ibcon#end of sib2, iclass 20, count 0 2006.201.12:35:57.01#ibcon#*after write, iclass 20, count 0 2006.201.12:35:57.01#ibcon#*before return 0, iclass 20, count 0 2006.201.12:35:57.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:35:57.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.12:35:57.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.12:35:57.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.12:35:57.01$vck44/vb=5,4 2006.201.12:35:57.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.12:35:57.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.12:35:57.01#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:57.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:35:57.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:35:57.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:35:57.07#ibcon#enter wrdev, iclass 22, count 2 2006.201.12:35:57.07#ibcon#first serial, iclass 22, count 2 2006.201.12:35:57.07#ibcon#enter sib2, iclass 22, count 2 2006.201.12:35:57.07#ibcon#flushed, iclass 22, count 2 2006.201.12:35:57.07#ibcon#about to write, iclass 22, count 2 2006.201.12:35:57.07#ibcon#wrote, iclass 22, count 2 2006.201.12:35:57.07#ibcon#about to read 3, iclass 22, count 2 2006.201.12:35:57.09#ibcon#read 3, iclass 22, count 2 2006.201.12:35:57.09#ibcon#about to read 4, iclass 22, count 2 2006.201.12:35:57.09#ibcon#read 4, iclass 22, count 2 2006.201.12:35:57.09#ibcon#about to read 5, iclass 22, count 2 2006.201.12:35:57.09#ibcon#read 5, iclass 22, count 2 2006.201.12:35:57.09#ibcon#about to read 6, iclass 22, count 2 2006.201.12:35:57.09#ibcon#read 6, iclass 22, count 2 2006.201.12:35:57.09#ibcon#end of sib2, iclass 22, count 2 2006.201.12:35:57.09#ibcon#*mode == 0, iclass 22, count 2 2006.201.12:35:57.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.12:35:57.09#ibcon#[27=AT05-04\r\n] 2006.201.12:35:57.09#ibcon#*before write, iclass 22, count 2 2006.201.12:35:57.09#ibcon#enter sib2, iclass 22, count 2 2006.201.12:35:57.09#ibcon#flushed, iclass 22, count 2 2006.201.12:35:57.09#ibcon#about to write, iclass 22, count 2 2006.201.12:35:57.09#ibcon#wrote, iclass 22, count 2 2006.201.12:35:57.09#ibcon#about to read 3, iclass 22, count 2 2006.201.12:35:57.12#ibcon#read 3, iclass 22, count 2 2006.201.12:35:57.12#ibcon#about to read 4, iclass 22, count 2 2006.201.12:35:57.12#ibcon#read 4, iclass 22, count 2 2006.201.12:35:57.12#ibcon#about to read 5, iclass 22, count 2 2006.201.12:35:57.12#ibcon#read 5, iclass 22, count 2 2006.201.12:35:57.12#ibcon#about to read 6, iclass 22, count 2 2006.201.12:35:57.12#ibcon#read 6, iclass 22, count 2 2006.201.12:35:57.12#ibcon#end of sib2, iclass 22, count 2 2006.201.12:35:57.12#ibcon#*after write, iclass 22, count 2 2006.201.12:35:57.12#ibcon#*before return 0, iclass 22, count 2 2006.201.12:35:57.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:35:57.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.12:35:57.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.12:35:57.12#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:57.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:35:57.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:35:57.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:35:57.24#ibcon#enter wrdev, iclass 22, count 0 2006.201.12:35:57.24#ibcon#first serial, iclass 22, count 0 2006.201.12:35:57.24#ibcon#enter sib2, iclass 22, count 0 2006.201.12:35:57.24#ibcon#flushed, iclass 22, count 0 2006.201.12:35:57.24#ibcon#about to write, iclass 22, count 0 2006.201.12:35:57.24#ibcon#wrote, iclass 22, count 0 2006.201.12:35:57.24#ibcon#about to read 3, iclass 22, count 0 2006.201.12:35:57.26#ibcon#read 3, iclass 22, count 0 2006.201.12:35:57.26#ibcon#about to read 4, iclass 22, count 0 2006.201.12:35:57.26#ibcon#read 4, iclass 22, count 0 2006.201.12:35:57.26#ibcon#about to read 5, iclass 22, count 0 2006.201.12:35:57.26#ibcon#read 5, iclass 22, count 0 2006.201.12:35:57.26#ibcon#about to read 6, iclass 22, count 0 2006.201.12:35:57.26#ibcon#read 6, iclass 22, count 0 2006.201.12:35:57.26#ibcon#end of sib2, iclass 22, count 0 2006.201.12:35:57.26#ibcon#*mode == 0, iclass 22, count 0 2006.201.12:35:57.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.12:35:57.26#ibcon#[27=USB\r\n] 2006.201.12:35:57.26#ibcon#*before write, iclass 22, count 0 2006.201.12:35:57.26#ibcon#enter sib2, iclass 22, count 0 2006.201.12:35:57.26#ibcon#flushed, iclass 22, count 0 2006.201.12:35:57.26#ibcon#about to write, iclass 22, count 0 2006.201.12:35:57.26#ibcon#wrote, iclass 22, count 0 2006.201.12:35:57.26#ibcon#about to read 3, iclass 22, count 0 2006.201.12:35:57.29#ibcon#read 3, iclass 22, count 0 2006.201.12:35:57.29#ibcon#about to read 4, iclass 22, count 0 2006.201.12:35:57.29#ibcon#read 4, iclass 22, count 0 2006.201.12:35:57.29#ibcon#about to read 5, iclass 22, count 0 2006.201.12:35:57.29#ibcon#read 5, iclass 22, count 0 2006.201.12:35:57.29#ibcon#about to read 6, iclass 22, count 0 2006.201.12:35:57.29#ibcon#read 6, iclass 22, count 0 2006.201.12:35:57.29#ibcon#end of sib2, iclass 22, count 0 2006.201.12:35:57.29#ibcon#*after write, iclass 22, count 0 2006.201.12:35:57.29#ibcon#*before return 0, iclass 22, count 0 2006.201.12:35:57.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:35:57.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.12:35:57.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.12:35:57.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.12:35:57.29$vck44/vblo=6,719.99 2006.201.12:35:57.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.12:35:57.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.12:35:57.29#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:57.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:35:57.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:35:57.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:35:57.29#ibcon#enter wrdev, iclass 24, count 0 2006.201.12:35:57.29#ibcon#first serial, iclass 24, count 0 2006.201.12:35:57.29#ibcon#enter sib2, iclass 24, count 0 2006.201.12:35:57.29#ibcon#flushed, iclass 24, count 0 2006.201.12:35:57.29#ibcon#about to write, iclass 24, count 0 2006.201.12:35:57.29#ibcon#wrote, iclass 24, count 0 2006.201.12:35:57.29#ibcon#about to read 3, iclass 24, count 0 2006.201.12:35:57.31#ibcon#read 3, iclass 24, count 0 2006.201.12:35:57.31#ibcon#about to read 4, iclass 24, count 0 2006.201.12:35:57.31#ibcon#read 4, iclass 24, count 0 2006.201.12:35:57.31#ibcon#about to read 5, iclass 24, count 0 2006.201.12:35:57.31#ibcon#read 5, iclass 24, count 0 2006.201.12:35:57.31#ibcon#about to read 6, iclass 24, count 0 2006.201.12:35:57.31#ibcon#read 6, iclass 24, count 0 2006.201.12:35:57.31#ibcon#end of sib2, iclass 24, count 0 2006.201.12:35:57.31#ibcon#*mode == 0, iclass 24, count 0 2006.201.12:35:57.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.12:35:57.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:35:57.31#ibcon#*before write, iclass 24, count 0 2006.201.12:35:57.31#ibcon#enter sib2, iclass 24, count 0 2006.201.12:35:57.31#ibcon#flushed, iclass 24, count 0 2006.201.12:35:57.31#ibcon#about to write, iclass 24, count 0 2006.201.12:35:57.31#ibcon#wrote, iclass 24, count 0 2006.201.12:35:57.31#ibcon#about to read 3, iclass 24, count 0 2006.201.12:35:57.36#ibcon#read 3, iclass 24, count 0 2006.201.12:35:57.36#ibcon#about to read 4, iclass 24, count 0 2006.201.12:35:57.36#ibcon#read 4, iclass 24, count 0 2006.201.12:35:57.36#ibcon#about to read 5, iclass 24, count 0 2006.201.12:35:57.36#ibcon#read 5, iclass 24, count 0 2006.201.12:35:57.36#ibcon#about to read 6, iclass 24, count 0 2006.201.12:35:57.36#ibcon#read 6, iclass 24, count 0 2006.201.12:35:57.36#ibcon#end of sib2, iclass 24, count 0 2006.201.12:35:57.36#ibcon#*after write, iclass 24, count 0 2006.201.12:35:57.36#ibcon#*before return 0, iclass 24, count 0 2006.201.12:35:57.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:35:57.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.12:35:57.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.12:35:57.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.12:35:57.36$vck44/vb=6,4 2006.201.12:35:57.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.12:35:57.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.12:35:57.36#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:57.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:35:57.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:35:57.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:35:57.41#ibcon#enter wrdev, iclass 26, count 2 2006.201.12:35:57.41#ibcon#first serial, iclass 26, count 2 2006.201.12:35:57.41#ibcon#enter sib2, iclass 26, count 2 2006.201.12:35:57.41#ibcon#flushed, iclass 26, count 2 2006.201.12:35:57.41#ibcon#about to write, iclass 26, count 2 2006.201.12:35:57.41#ibcon#wrote, iclass 26, count 2 2006.201.12:35:57.41#ibcon#about to read 3, iclass 26, count 2 2006.201.12:35:57.43#ibcon#read 3, iclass 26, count 2 2006.201.12:35:57.43#ibcon#about to read 4, iclass 26, count 2 2006.201.12:35:57.43#ibcon#read 4, iclass 26, count 2 2006.201.12:35:57.43#ibcon#about to read 5, iclass 26, count 2 2006.201.12:35:57.43#ibcon#read 5, iclass 26, count 2 2006.201.12:35:57.43#ibcon#about to read 6, iclass 26, count 2 2006.201.12:35:57.43#ibcon#read 6, iclass 26, count 2 2006.201.12:35:57.43#ibcon#end of sib2, iclass 26, count 2 2006.201.12:35:57.43#ibcon#*mode == 0, iclass 26, count 2 2006.201.12:35:57.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.12:35:57.43#ibcon#[27=AT06-04\r\n] 2006.201.12:35:57.43#ibcon#*before write, iclass 26, count 2 2006.201.12:35:57.43#ibcon#enter sib2, iclass 26, count 2 2006.201.12:35:57.43#ibcon#flushed, iclass 26, count 2 2006.201.12:35:57.43#ibcon#about to write, iclass 26, count 2 2006.201.12:35:57.43#ibcon#wrote, iclass 26, count 2 2006.201.12:35:57.43#ibcon#about to read 3, iclass 26, count 2 2006.201.12:35:57.46#ibcon#read 3, iclass 26, count 2 2006.201.12:35:57.46#ibcon#about to read 4, iclass 26, count 2 2006.201.12:35:57.46#ibcon#read 4, iclass 26, count 2 2006.201.12:35:57.46#ibcon#about to read 5, iclass 26, count 2 2006.201.12:35:57.46#ibcon#read 5, iclass 26, count 2 2006.201.12:35:57.46#ibcon#about to read 6, iclass 26, count 2 2006.201.12:35:57.46#ibcon#read 6, iclass 26, count 2 2006.201.12:35:57.46#ibcon#end of sib2, iclass 26, count 2 2006.201.12:35:57.46#ibcon#*after write, iclass 26, count 2 2006.201.12:35:57.46#ibcon#*before return 0, iclass 26, count 2 2006.201.12:35:57.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:35:57.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.12:35:57.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.12:35:57.46#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:57.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:35:57.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:35:57.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:35:57.58#ibcon#enter wrdev, iclass 26, count 0 2006.201.12:35:57.58#ibcon#first serial, iclass 26, count 0 2006.201.12:35:57.58#ibcon#enter sib2, iclass 26, count 0 2006.201.12:35:57.58#ibcon#flushed, iclass 26, count 0 2006.201.12:35:57.58#ibcon#about to write, iclass 26, count 0 2006.201.12:35:57.58#ibcon#wrote, iclass 26, count 0 2006.201.12:35:57.58#ibcon#about to read 3, iclass 26, count 0 2006.201.12:35:57.60#ibcon#read 3, iclass 26, count 0 2006.201.12:35:57.60#ibcon#about to read 4, iclass 26, count 0 2006.201.12:35:57.60#ibcon#read 4, iclass 26, count 0 2006.201.12:35:57.60#ibcon#about to read 5, iclass 26, count 0 2006.201.12:35:57.60#ibcon#read 5, iclass 26, count 0 2006.201.12:35:57.60#ibcon#about to read 6, iclass 26, count 0 2006.201.12:35:57.60#ibcon#read 6, iclass 26, count 0 2006.201.12:35:57.60#ibcon#end of sib2, iclass 26, count 0 2006.201.12:35:57.60#ibcon#*mode == 0, iclass 26, count 0 2006.201.12:35:57.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.12:35:57.60#ibcon#[27=USB\r\n] 2006.201.12:35:57.60#ibcon#*before write, iclass 26, count 0 2006.201.12:35:57.60#ibcon#enter sib2, iclass 26, count 0 2006.201.12:35:57.60#ibcon#flushed, iclass 26, count 0 2006.201.12:35:57.60#ibcon#about to write, iclass 26, count 0 2006.201.12:35:57.60#ibcon#wrote, iclass 26, count 0 2006.201.12:35:57.60#ibcon#about to read 3, iclass 26, count 0 2006.201.12:35:57.63#ibcon#read 3, iclass 26, count 0 2006.201.12:35:57.63#ibcon#about to read 4, iclass 26, count 0 2006.201.12:35:57.63#ibcon#read 4, iclass 26, count 0 2006.201.12:35:57.63#ibcon#about to read 5, iclass 26, count 0 2006.201.12:35:57.63#ibcon#read 5, iclass 26, count 0 2006.201.12:35:57.63#ibcon#about to read 6, iclass 26, count 0 2006.201.12:35:57.63#ibcon#read 6, iclass 26, count 0 2006.201.12:35:57.63#ibcon#end of sib2, iclass 26, count 0 2006.201.12:35:57.63#ibcon#*after write, iclass 26, count 0 2006.201.12:35:57.63#ibcon#*before return 0, iclass 26, count 0 2006.201.12:35:57.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:35:57.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.12:35:57.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.12:35:57.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.12:35:57.63$vck44/vblo=7,734.99 2006.201.12:35:57.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.12:35:57.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.12:35:57.63#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:57.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:35:57.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:35:57.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:35:57.63#ibcon#enter wrdev, iclass 28, count 0 2006.201.12:35:57.63#ibcon#first serial, iclass 28, count 0 2006.201.12:35:57.63#ibcon#enter sib2, iclass 28, count 0 2006.201.12:35:57.63#ibcon#flushed, iclass 28, count 0 2006.201.12:35:57.63#ibcon#about to write, iclass 28, count 0 2006.201.12:35:57.63#ibcon#wrote, iclass 28, count 0 2006.201.12:35:57.63#ibcon#about to read 3, iclass 28, count 0 2006.201.12:35:57.65#ibcon#read 3, iclass 28, count 0 2006.201.12:35:57.65#ibcon#about to read 4, iclass 28, count 0 2006.201.12:35:57.65#ibcon#read 4, iclass 28, count 0 2006.201.12:35:57.65#ibcon#about to read 5, iclass 28, count 0 2006.201.12:35:57.65#ibcon#read 5, iclass 28, count 0 2006.201.12:35:57.65#ibcon#about to read 6, iclass 28, count 0 2006.201.12:35:57.65#ibcon#read 6, iclass 28, count 0 2006.201.12:35:57.65#ibcon#end of sib2, iclass 28, count 0 2006.201.12:35:57.65#ibcon#*mode == 0, iclass 28, count 0 2006.201.12:35:57.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.12:35:57.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:35:57.65#ibcon#*before write, iclass 28, count 0 2006.201.12:35:57.65#ibcon#enter sib2, iclass 28, count 0 2006.201.12:35:57.65#ibcon#flushed, iclass 28, count 0 2006.201.12:35:57.65#ibcon#about to write, iclass 28, count 0 2006.201.12:35:57.65#ibcon#wrote, iclass 28, count 0 2006.201.12:35:57.65#ibcon#about to read 3, iclass 28, count 0 2006.201.12:35:57.70#ibcon#read 3, iclass 28, count 0 2006.201.12:35:57.70#ibcon#about to read 4, iclass 28, count 0 2006.201.12:35:57.70#ibcon#read 4, iclass 28, count 0 2006.201.12:35:57.70#ibcon#about to read 5, iclass 28, count 0 2006.201.12:35:57.70#ibcon#read 5, iclass 28, count 0 2006.201.12:35:57.70#ibcon#about to read 6, iclass 28, count 0 2006.201.12:35:57.70#ibcon#read 6, iclass 28, count 0 2006.201.12:35:57.70#ibcon#end of sib2, iclass 28, count 0 2006.201.12:35:57.70#ibcon#*after write, iclass 28, count 0 2006.201.12:35:57.70#ibcon#*before return 0, iclass 28, count 0 2006.201.12:35:57.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:35:57.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.12:35:57.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.12:35:57.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.12:35:57.70$vck44/vb=7,4 2006.201.12:35:57.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.12:35:57.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.12:35:57.70#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:57.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:35:57.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:35:57.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:35:57.75#ibcon#enter wrdev, iclass 30, count 2 2006.201.12:35:57.75#ibcon#first serial, iclass 30, count 2 2006.201.12:35:57.75#ibcon#enter sib2, iclass 30, count 2 2006.201.12:35:57.75#ibcon#flushed, iclass 30, count 2 2006.201.12:35:57.75#ibcon#about to write, iclass 30, count 2 2006.201.12:35:57.75#ibcon#wrote, iclass 30, count 2 2006.201.12:35:57.75#ibcon#about to read 3, iclass 30, count 2 2006.201.12:35:57.77#ibcon#read 3, iclass 30, count 2 2006.201.12:35:57.77#ibcon#about to read 4, iclass 30, count 2 2006.201.12:35:57.77#ibcon#read 4, iclass 30, count 2 2006.201.12:35:57.77#ibcon#about to read 5, iclass 30, count 2 2006.201.12:35:57.77#ibcon#read 5, iclass 30, count 2 2006.201.12:35:57.77#ibcon#about to read 6, iclass 30, count 2 2006.201.12:35:57.77#ibcon#read 6, iclass 30, count 2 2006.201.12:35:57.77#ibcon#end of sib2, iclass 30, count 2 2006.201.12:35:57.77#ibcon#*mode == 0, iclass 30, count 2 2006.201.12:35:57.77#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.12:35:57.77#ibcon#[27=AT07-04\r\n] 2006.201.12:35:57.77#ibcon#*before write, iclass 30, count 2 2006.201.12:35:57.77#ibcon#enter sib2, iclass 30, count 2 2006.201.12:35:57.77#ibcon#flushed, iclass 30, count 2 2006.201.12:35:57.77#ibcon#about to write, iclass 30, count 2 2006.201.12:35:57.77#ibcon#wrote, iclass 30, count 2 2006.201.12:35:57.77#ibcon#about to read 3, iclass 30, count 2 2006.201.12:35:57.80#ibcon#read 3, iclass 30, count 2 2006.201.12:35:57.80#ibcon#about to read 4, iclass 30, count 2 2006.201.12:35:57.80#ibcon#read 4, iclass 30, count 2 2006.201.12:35:57.80#ibcon#about to read 5, iclass 30, count 2 2006.201.12:35:57.80#ibcon#read 5, iclass 30, count 2 2006.201.12:35:57.80#ibcon#about to read 6, iclass 30, count 2 2006.201.12:35:57.80#ibcon#read 6, iclass 30, count 2 2006.201.12:35:57.80#ibcon#end of sib2, iclass 30, count 2 2006.201.12:35:57.80#ibcon#*after write, iclass 30, count 2 2006.201.12:35:57.80#ibcon#*before return 0, iclass 30, count 2 2006.201.12:35:57.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:35:57.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.12:35:57.80#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.12:35:57.80#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:57.80#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:35:57.92#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:35:57.92#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:35:57.92#ibcon#enter wrdev, iclass 30, count 0 2006.201.12:35:57.92#ibcon#first serial, iclass 30, count 0 2006.201.12:35:57.92#ibcon#enter sib2, iclass 30, count 0 2006.201.12:35:57.92#ibcon#flushed, iclass 30, count 0 2006.201.12:35:57.92#ibcon#about to write, iclass 30, count 0 2006.201.12:35:57.92#ibcon#wrote, iclass 30, count 0 2006.201.12:35:57.92#ibcon#about to read 3, iclass 30, count 0 2006.201.12:35:57.94#ibcon#read 3, iclass 30, count 0 2006.201.12:35:57.94#ibcon#about to read 4, iclass 30, count 0 2006.201.12:35:57.94#ibcon#read 4, iclass 30, count 0 2006.201.12:35:57.94#ibcon#about to read 5, iclass 30, count 0 2006.201.12:35:57.94#ibcon#read 5, iclass 30, count 0 2006.201.12:35:57.94#ibcon#about to read 6, iclass 30, count 0 2006.201.12:35:57.94#ibcon#read 6, iclass 30, count 0 2006.201.12:35:57.94#ibcon#end of sib2, iclass 30, count 0 2006.201.12:35:57.94#ibcon#*mode == 0, iclass 30, count 0 2006.201.12:35:57.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.12:35:57.94#ibcon#[27=USB\r\n] 2006.201.12:35:57.94#ibcon#*before write, iclass 30, count 0 2006.201.12:35:57.94#ibcon#enter sib2, iclass 30, count 0 2006.201.12:35:57.94#ibcon#flushed, iclass 30, count 0 2006.201.12:35:57.94#ibcon#about to write, iclass 30, count 0 2006.201.12:35:57.94#ibcon#wrote, iclass 30, count 0 2006.201.12:35:57.94#ibcon#about to read 3, iclass 30, count 0 2006.201.12:35:57.97#ibcon#read 3, iclass 30, count 0 2006.201.12:35:57.97#ibcon#about to read 4, iclass 30, count 0 2006.201.12:35:57.97#ibcon#read 4, iclass 30, count 0 2006.201.12:35:57.97#ibcon#about to read 5, iclass 30, count 0 2006.201.12:35:57.97#ibcon#read 5, iclass 30, count 0 2006.201.12:35:57.97#ibcon#about to read 6, iclass 30, count 0 2006.201.12:35:57.97#ibcon#read 6, iclass 30, count 0 2006.201.12:35:57.97#ibcon#end of sib2, iclass 30, count 0 2006.201.12:35:57.97#ibcon#*after write, iclass 30, count 0 2006.201.12:35:57.97#ibcon#*before return 0, iclass 30, count 0 2006.201.12:35:57.97#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:35:57.97#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.12:35:57.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.12:35:57.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.12:35:57.97$vck44/vblo=8,744.99 2006.201.12:35:57.97#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.12:35:57.97#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.12:35:57.97#ibcon#ireg 17 cls_cnt 0 2006.201.12:35:57.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:57.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:57.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:57.97#ibcon#enter wrdev, iclass 32, count 0 2006.201.12:35:57.97#ibcon#first serial, iclass 32, count 0 2006.201.12:35:57.97#ibcon#enter sib2, iclass 32, count 0 2006.201.12:35:57.97#ibcon#flushed, iclass 32, count 0 2006.201.12:35:57.97#ibcon#about to write, iclass 32, count 0 2006.201.12:35:57.97#ibcon#wrote, iclass 32, count 0 2006.201.12:35:57.97#ibcon#about to read 3, iclass 32, count 0 2006.201.12:35:57.99#ibcon#read 3, iclass 32, count 0 2006.201.12:35:57.99#ibcon#about to read 4, iclass 32, count 0 2006.201.12:35:57.99#ibcon#read 4, iclass 32, count 0 2006.201.12:35:57.99#ibcon#about to read 5, iclass 32, count 0 2006.201.12:35:57.99#ibcon#read 5, iclass 32, count 0 2006.201.12:35:57.99#ibcon#about to read 6, iclass 32, count 0 2006.201.12:35:57.99#ibcon#read 6, iclass 32, count 0 2006.201.12:35:57.99#ibcon#end of sib2, iclass 32, count 0 2006.201.12:35:57.99#ibcon#*mode == 0, iclass 32, count 0 2006.201.12:35:57.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.12:35:57.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:35:57.99#ibcon#*before write, iclass 32, count 0 2006.201.12:35:57.99#ibcon#enter sib2, iclass 32, count 0 2006.201.12:35:57.99#ibcon#flushed, iclass 32, count 0 2006.201.12:35:57.99#ibcon#about to write, iclass 32, count 0 2006.201.12:35:57.99#ibcon#wrote, iclass 32, count 0 2006.201.12:35:57.99#ibcon#about to read 3, iclass 32, count 0 2006.201.12:35:58.03#ibcon#read 3, iclass 32, count 0 2006.201.12:35:58.03#ibcon#about to read 4, iclass 32, count 0 2006.201.12:35:58.03#ibcon#read 4, iclass 32, count 0 2006.201.12:35:58.03#ibcon#about to read 5, iclass 32, count 0 2006.201.12:35:58.03#ibcon#read 5, iclass 32, count 0 2006.201.12:35:58.03#ibcon#about to read 6, iclass 32, count 0 2006.201.12:35:58.03#ibcon#read 6, iclass 32, count 0 2006.201.12:35:58.03#ibcon#end of sib2, iclass 32, count 0 2006.201.12:35:58.03#ibcon#*after write, iclass 32, count 0 2006.201.12:35:58.03#ibcon#*before return 0, iclass 32, count 0 2006.201.12:35:58.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:58.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.12:35:58.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.12:35:58.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.12:35:58.03$vck44/vb=8,4 2006.201.12:35:58.03#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.12:35:58.03#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.12:35:58.03#ibcon#ireg 11 cls_cnt 2 2006.201.12:35:58.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:58.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:58.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:58.09#ibcon#enter wrdev, iclass 34, count 2 2006.201.12:35:58.09#ibcon#first serial, iclass 34, count 2 2006.201.12:35:58.09#ibcon#enter sib2, iclass 34, count 2 2006.201.12:35:58.09#ibcon#flushed, iclass 34, count 2 2006.201.12:35:58.09#ibcon#about to write, iclass 34, count 2 2006.201.12:35:58.09#ibcon#wrote, iclass 34, count 2 2006.201.12:35:58.09#ibcon#about to read 3, iclass 34, count 2 2006.201.12:35:58.11#ibcon#read 3, iclass 34, count 2 2006.201.12:35:58.11#ibcon#about to read 4, iclass 34, count 2 2006.201.12:35:58.11#ibcon#read 4, iclass 34, count 2 2006.201.12:35:58.11#ibcon#about to read 5, iclass 34, count 2 2006.201.12:35:58.11#ibcon#read 5, iclass 34, count 2 2006.201.12:35:58.11#ibcon#about to read 6, iclass 34, count 2 2006.201.12:35:58.11#ibcon#read 6, iclass 34, count 2 2006.201.12:35:58.11#ibcon#end of sib2, iclass 34, count 2 2006.201.12:35:58.11#ibcon#*mode == 0, iclass 34, count 2 2006.201.12:35:58.11#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.12:35:58.11#ibcon#[27=AT08-04\r\n] 2006.201.12:35:58.11#ibcon#*before write, iclass 34, count 2 2006.201.12:35:58.11#ibcon#enter sib2, iclass 34, count 2 2006.201.12:35:58.11#ibcon#flushed, iclass 34, count 2 2006.201.12:35:58.11#ibcon#about to write, iclass 34, count 2 2006.201.12:35:58.11#ibcon#wrote, iclass 34, count 2 2006.201.12:35:58.11#ibcon#about to read 3, iclass 34, count 2 2006.201.12:35:58.14#ibcon#read 3, iclass 34, count 2 2006.201.12:35:58.14#ibcon#about to read 4, iclass 34, count 2 2006.201.12:35:58.14#ibcon#read 4, iclass 34, count 2 2006.201.12:35:58.14#ibcon#about to read 5, iclass 34, count 2 2006.201.12:35:58.14#ibcon#read 5, iclass 34, count 2 2006.201.12:35:58.14#ibcon#about to read 6, iclass 34, count 2 2006.201.12:35:58.14#ibcon#read 6, iclass 34, count 2 2006.201.12:35:58.14#ibcon#end of sib2, iclass 34, count 2 2006.201.12:35:58.14#ibcon#*after write, iclass 34, count 2 2006.201.12:35:58.14#ibcon#*before return 0, iclass 34, count 2 2006.201.12:35:58.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:58.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.12:35:58.14#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.12:35:58.14#ibcon#ireg 7 cls_cnt 0 2006.201.12:35:58.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:58.26#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:58.26#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:58.26#ibcon#enter wrdev, iclass 34, count 0 2006.201.12:35:58.26#ibcon#first serial, iclass 34, count 0 2006.201.12:35:58.26#ibcon#enter sib2, iclass 34, count 0 2006.201.12:35:58.26#ibcon#flushed, iclass 34, count 0 2006.201.12:35:58.26#ibcon#about to write, iclass 34, count 0 2006.201.12:35:58.26#ibcon#wrote, iclass 34, count 0 2006.201.12:35:58.26#ibcon#about to read 3, iclass 34, count 0 2006.201.12:35:58.28#ibcon#read 3, iclass 34, count 0 2006.201.12:35:58.28#ibcon#about to read 4, iclass 34, count 0 2006.201.12:35:58.28#ibcon#read 4, iclass 34, count 0 2006.201.12:35:58.28#ibcon#about to read 5, iclass 34, count 0 2006.201.12:35:58.28#ibcon#read 5, iclass 34, count 0 2006.201.12:35:58.28#ibcon#about to read 6, iclass 34, count 0 2006.201.12:35:58.28#ibcon#read 6, iclass 34, count 0 2006.201.12:35:58.28#ibcon#end of sib2, iclass 34, count 0 2006.201.12:35:58.28#ibcon#*mode == 0, iclass 34, count 0 2006.201.12:35:58.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.12:35:58.28#ibcon#[27=USB\r\n] 2006.201.12:35:58.28#ibcon#*before write, iclass 34, count 0 2006.201.12:35:58.28#ibcon#enter sib2, iclass 34, count 0 2006.201.12:35:58.28#ibcon#flushed, iclass 34, count 0 2006.201.12:35:58.28#ibcon#about to write, iclass 34, count 0 2006.201.12:35:58.28#ibcon#wrote, iclass 34, count 0 2006.201.12:35:58.28#ibcon#about to read 3, iclass 34, count 0 2006.201.12:35:58.31#ibcon#read 3, iclass 34, count 0 2006.201.12:35:58.31#ibcon#about to read 4, iclass 34, count 0 2006.201.12:35:58.31#ibcon#read 4, iclass 34, count 0 2006.201.12:35:58.31#ibcon#about to read 5, iclass 34, count 0 2006.201.12:35:58.31#ibcon#read 5, iclass 34, count 0 2006.201.12:35:58.31#ibcon#about to read 6, iclass 34, count 0 2006.201.12:35:58.31#ibcon#read 6, iclass 34, count 0 2006.201.12:35:58.31#ibcon#end of sib2, iclass 34, count 0 2006.201.12:35:58.31#ibcon#*after write, iclass 34, count 0 2006.201.12:35:58.31#ibcon#*before return 0, iclass 34, count 0 2006.201.12:35:58.31#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:58.31#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.12:35:58.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.12:35:58.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.12:35:58.31$vck44/vabw=wide 2006.201.12:35:58.31#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.12:35:58.31#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.12:35:58.31#ibcon#ireg 8 cls_cnt 0 2006.201.12:35:58.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:58.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:58.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:58.31#ibcon#enter wrdev, iclass 36, count 0 2006.201.12:35:58.31#ibcon#first serial, iclass 36, count 0 2006.201.12:35:58.31#ibcon#enter sib2, iclass 36, count 0 2006.201.12:35:58.31#ibcon#flushed, iclass 36, count 0 2006.201.12:35:58.31#ibcon#about to write, iclass 36, count 0 2006.201.12:35:58.31#ibcon#wrote, iclass 36, count 0 2006.201.12:35:58.31#ibcon#about to read 3, iclass 36, count 0 2006.201.12:35:58.33#ibcon#read 3, iclass 36, count 0 2006.201.12:35:58.33#ibcon#about to read 4, iclass 36, count 0 2006.201.12:35:58.33#ibcon#read 4, iclass 36, count 0 2006.201.12:35:58.33#ibcon#about to read 5, iclass 36, count 0 2006.201.12:35:58.33#ibcon#read 5, iclass 36, count 0 2006.201.12:35:58.33#ibcon#about to read 6, iclass 36, count 0 2006.201.12:35:58.33#ibcon#read 6, iclass 36, count 0 2006.201.12:35:58.33#ibcon#end of sib2, iclass 36, count 0 2006.201.12:35:58.33#ibcon#*mode == 0, iclass 36, count 0 2006.201.12:35:58.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.12:35:58.33#ibcon#[25=BW32\r\n] 2006.201.12:35:58.33#ibcon#*before write, iclass 36, count 0 2006.201.12:35:58.33#ibcon#enter sib2, iclass 36, count 0 2006.201.12:35:58.33#ibcon#flushed, iclass 36, count 0 2006.201.12:35:58.33#ibcon#about to write, iclass 36, count 0 2006.201.12:35:58.33#ibcon#wrote, iclass 36, count 0 2006.201.12:35:58.33#ibcon#about to read 3, iclass 36, count 0 2006.201.12:35:58.37#ibcon#read 3, iclass 36, count 0 2006.201.12:35:58.37#ibcon#about to read 4, iclass 36, count 0 2006.201.12:35:58.37#ibcon#read 4, iclass 36, count 0 2006.201.12:35:58.37#ibcon#about to read 5, iclass 36, count 0 2006.201.12:35:58.37#ibcon#read 5, iclass 36, count 0 2006.201.12:35:58.37#ibcon#about to read 6, iclass 36, count 0 2006.201.12:35:58.37#ibcon#read 6, iclass 36, count 0 2006.201.12:35:58.37#ibcon#end of sib2, iclass 36, count 0 2006.201.12:35:58.37#ibcon#*after write, iclass 36, count 0 2006.201.12:35:58.37#ibcon#*before return 0, iclass 36, count 0 2006.201.12:35:58.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:58.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.12:35:58.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.12:35:58.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.12:35:58.37$vck44/vbbw=wide 2006.201.12:35:58.37#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.12:35:58.37#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.12:35:58.37#ibcon#ireg 8 cls_cnt 0 2006.201.12:35:58.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:35:58.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:35:58.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:35:58.43#ibcon#enter wrdev, iclass 38, count 0 2006.201.12:35:58.43#ibcon#first serial, iclass 38, count 0 2006.201.12:35:58.43#ibcon#enter sib2, iclass 38, count 0 2006.201.12:35:58.43#ibcon#flushed, iclass 38, count 0 2006.201.12:35:58.43#ibcon#about to write, iclass 38, count 0 2006.201.12:35:58.43#ibcon#wrote, iclass 38, count 0 2006.201.12:35:58.43#ibcon#about to read 3, iclass 38, count 0 2006.201.12:35:58.45#ibcon#read 3, iclass 38, count 0 2006.201.12:35:58.45#ibcon#about to read 4, iclass 38, count 0 2006.201.12:35:58.45#ibcon#read 4, iclass 38, count 0 2006.201.12:35:58.45#ibcon#about to read 5, iclass 38, count 0 2006.201.12:35:58.45#ibcon#read 5, iclass 38, count 0 2006.201.12:35:58.45#ibcon#about to read 6, iclass 38, count 0 2006.201.12:35:58.45#ibcon#read 6, iclass 38, count 0 2006.201.12:35:58.45#ibcon#end of sib2, iclass 38, count 0 2006.201.12:35:58.45#ibcon#*mode == 0, iclass 38, count 0 2006.201.12:35:58.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.12:35:58.45#ibcon#[27=BW32\r\n] 2006.201.12:35:58.45#ibcon#*before write, iclass 38, count 0 2006.201.12:35:58.45#ibcon#enter sib2, iclass 38, count 0 2006.201.12:35:58.45#ibcon#flushed, iclass 38, count 0 2006.201.12:35:58.45#ibcon#about to write, iclass 38, count 0 2006.201.12:35:58.45#ibcon#wrote, iclass 38, count 0 2006.201.12:35:58.45#ibcon#about to read 3, iclass 38, count 0 2006.201.12:35:58.48#ibcon#read 3, iclass 38, count 0 2006.201.12:35:58.48#ibcon#about to read 4, iclass 38, count 0 2006.201.12:35:58.48#ibcon#read 4, iclass 38, count 0 2006.201.12:35:58.48#ibcon#about to read 5, iclass 38, count 0 2006.201.12:35:58.48#ibcon#read 5, iclass 38, count 0 2006.201.12:35:58.48#ibcon#about to read 6, iclass 38, count 0 2006.201.12:35:58.48#ibcon#read 6, iclass 38, count 0 2006.201.12:35:58.48#ibcon#end of sib2, iclass 38, count 0 2006.201.12:35:58.48#ibcon#*after write, iclass 38, count 0 2006.201.12:35:58.48#ibcon#*before return 0, iclass 38, count 0 2006.201.12:35:58.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:35:58.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.12:35:58.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.12:35:58.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.12:35:58.48$setupk4/ifdk4 2006.201.12:35:58.48$ifdk4/lo= 2006.201.12:35:58.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:35:58.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:35:58.48$ifdk4/patch= 2006.201.12:35:58.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:35:58.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:35:58.48$setupk4/!*+20s 2006.201.12:36:07.98#abcon#{5=INTERFACE CLEAR} 2006.201.12:36:08.04#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:36:12.93$setupk4/"tpicd 2006.201.12:36:12.93$setupk4/echo=off 2006.201.12:36:12.93$setupk4/xlog=off 2006.201.12:36:12.93:!2006.201.12:39:04 2006.201.12:36:19.14#trakl#Source acquired 2006.201.12:36:21.14#flagr#flagr/antenna,acquired 2006.201.12:39:04.00:preob 2006.201.12:39:04.14/onsource/TRACKING 2006.201.12:39:04.14:!2006.201.12:39:14 2006.201.12:39:14.00:"tape 2006.201.12:39:14.00:"st=record 2006.201.12:39:14.00:data_valid=on 2006.201.12:39:14.00:midob 2006.201.12:39:15.14/onsource/TRACKING 2006.201.12:39:15.14/wx/21.07,1004.2,100 2006.201.12:39:15.28/cable/+6.4738E-03 2006.201.12:39:16.37/va/01,08,usb,yes,30,33 2006.201.12:39:16.37/va/02,07,usb,yes,33,34 2006.201.12:39:16.37/va/03,08,usb,yes,30,31 2006.201.12:39:16.37/va/04,07,usb,yes,34,36 2006.201.12:39:16.37/va/05,04,usb,yes,30,30 2006.201.12:39:16.37/va/06,05,usb,yes,30,30 2006.201.12:39:16.37/va/07,05,usb,yes,29,30 2006.201.12:39:16.37/va/08,04,usb,yes,29,35 2006.201.12:39:16.60/valo/01,524.99,yes,locked 2006.201.12:39:16.60/valo/02,534.99,yes,locked 2006.201.12:39:16.60/valo/03,564.99,yes,locked 2006.201.12:39:16.60/valo/04,624.99,yes,locked 2006.201.12:39:16.60/valo/05,734.99,yes,locked 2006.201.12:39:16.60/valo/06,814.99,yes,locked 2006.201.12:39:16.60/valo/07,864.99,yes,locked 2006.201.12:39:16.60/valo/08,884.99,yes,locked 2006.201.12:39:17.69/vb/01,04,usb,yes,30,28 2006.201.12:39:17.69/vb/02,05,usb,yes,28,28 2006.201.12:39:17.69/vb/03,04,usb,yes,29,32 2006.201.12:39:17.69/vb/04,05,usb,yes,30,29 2006.201.12:39:17.69/vb/05,04,usb,yes,26,29 2006.201.12:39:17.69/vb/06,04,usb,yes,31,27 2006.201.12:39:17.69/vb/07,04,usb,yes,30,30 2006.201.12:39:17.69/vb/08,04,usb,yes,28,31 2006.201.12:39:17.93/vblo/01,629.99,yes,locked 2006.201.12:39:17.93/vblo/02,634.99,yes,locked 2006.201.12:39:17.93/vblo/03,649.99,yes,locked 2006.201.12:39:17.93/vblo/04,679.99,yes,locked 2006.201.12:39:17.93/vblo/05,709.99,yes,locked 2006.201.12:39:17.93/vblo/06,719.99,yes,locked 2006.201.12:39:17.93/vblo/07,734.99,yes,locked 2006.201.12:39:17.93/vblo/08,744.99,yes,locked 2006.201.12:39:18.08/vabw/8 2006.201.12:39:18.23/vbbw/8 2006.201.12:39:18.32/xfe/off,on,15.0 2006.201.12:39:18.70/ifatt/23,28,28,28 2006.201.12:39:19.06/fmout-gps/S +4.61E-07 2006.201.12:39:19.13:!2006.201.12:39:54 2006.201.12:39:54.00:data_valid=off 2006.201.12:39:54.00:"et 2006.201.12:39:54.00:!+3s 2006.201.12:39:57.02:"tape 2006.201.12:39:57.02:postob 2006.201.12:39:57.09/cable/+6.4708E-03 2006.201.12:39:57.09/wx/21.06,1004.2,100 2006.201.12:39:57.17/fmout-gps/S +4.62E-07 2006.201.12:39:57.17:scan_name=201-1243,jd0607,40 2006.201.12:39:57.17:source=3c345,164258.81,394837.0,2000.0,ccw 2006.201.12:39:59.13#flagr#flagr/antenna,new-source 2006.201.12:39:59.13:checkk5 2006.201.12:39:59.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:39:59.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:40:00.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:40:00.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:40:00.98/chk_obsdata//k5ts1/T2011239??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:40:01.35/chk_obsdata//k5ts2/T2011239??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:40:01.71/chk_obsdata//k5ts3/T2011239??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:40:02.07/chk_obsdata//k5ts4/T2011239??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:40:02.76/k5log//k5ts1_log_newline 2006.201.12:40:03.44/k5log//k5ts2_log_newline 2006.201.12:40:04.13/k5log//k5ts3_log_newline 2006.201.12:40:04.81/k5log//k5ts4_log_newline 2006.201.12:40:04.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:40:04.83:setupk4=1 2006.201.12:40:04.84$setupk4/echo=on 2006.201.12:40:04.84$setupk4/pcalon 2006.201.12:40:04.84$pcalon/"no phase cal control is implemented here 2006.201.12:40:04.84$setupk4/"tpicd=stop 2006.201.12:40:04.84$setupk4/"rec=synch_on 2006.201.12:40:04.84$setupk4/"rec_mode=128 2006.201.12:40:04.84$setupk4/!* 2006.201.12:40:04.84$setupk4/recpk4 2006.201.12:40:04.84$recpk4/recpatch= 2006.201.12:40:04.84$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:40:04.84$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:40:04.84$setupk4/vck44 2006.201.12:40:04.84$vck44/valo=1,524.99 2006.201.12:40:04.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.12:40:04.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.12:40:04.84#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:04.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:04.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:04.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:04.84#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:40:04.84#ibcon#first serial, iclass 29, count 0 2006.201.12:40:04.84#ibcon#enter sib2, iclass 29, count 0 2006.201.12:40:04.84#ibcon#flushed, iclass 29, count 0 2006.201.12:40:04.84#ibcon#about to write, iclass 29, count 0 2006.201.12:40:04.84#ibcon#wrote, iclass 29, count 0 2006.201.12:40:04.84#ibcon#about to read 3, iclass 29, count 0 2006.201.12:40:04.88#ibcon#read 3, iclass 29, count 0 2006.201.12:40:04.88#ibcon#about to read 4, iclass 29, count 0 2006.201.12:40:04.88#ibcon#read 4, iclass 29, count 0 2006.201.12:40:04.88#ibcon#about to read 5, iclass 29, count 0 2006.201.12:40:04.88#ibcon#read 5, iclass 29, count 0 2006.201.12:40:04.88#ibcon#about to read 6, iclass 29, count 0 2006.201.12:40:04.88#ibcon#read 6, iclass 29, count 0 2006.201.12:40:04.88#ibcon#end of sib2, iclass 29, count 0 2006.201.12:40:04.88#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:40:04.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:40:04.88#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:40:04.88#ibcon#*before write, iclass 29, count 0 2006.201.12:40:04.88#ibcon#enter sib2, iclass 29, count 0 2006.201.12:40:04.88#ibcon#flushed, iclass 29, count 0 2006.201.12:40:04.88#ibcon#about to write, iclass 29, count 0 2006.201.12:40:04.88#ibcon#wrote, iclass 29, count 0 2006.201.12:40:04.88#ibcon#about to read 3, iclass 29, count 0 2006.201.12:40:04.93#ibcon#read 3, iclass 29, count 0 2006.201.12:40:04.93#ibcon#about to read 4, iclass 29, count 0 2006.201.12:40:04.93#ibcon#read 4, iclass 29, count 0 2006.201.12:40:04.93#ibcon#about to read 5, iclass 29, count 0 2006.201.12:40:04.93#ibcon#read 5, iclass 29, count 0 2006.201.12:40:04.93#ibcon#about to read 6, iclass 29, count 0 2006.201.12:40:04.93#ibcon#read 6, iclass 29, count 0 2006.201.12:40:04.93#ibcon#end of sib2, iclass 29, count 0 2006.201.12:40:04.93#ibcon#*after write, iclass 29, count 0 2006.201.12:40:04.93#ibcon#*before return 0, iclass 29, count 0 2006.201.12:40:04.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:04.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:04.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:40:04.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:40:04.93$vck44/va=1,8 2006.201.12:40:04.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.12:40:04.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.12:40:04.93#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:04.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:04.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:04.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:04.93#ibcon#enter wrdev, iclass 31, count 2 2006.201.12:40:04.93#ibcon#first serial, iclass 31, count 2 2006.201.12:40:04.93#ibcon#enter sib2, iclass 31, count 2 2006.201.12:40:04.93#ibcon#flushed, iclass 31, count 2 2006.201.12:40:04.93#ibcon#about to write, iclass 31, count 2 2006.201.12:40:04.93#ibcon#wrote, iclass 31, count 2 2006.201.12:40:04.93#ibcon#about to read 3, iclass 31, count 2 2006.201.12:40:04.95#ibcon#read 3, iclass 31, count 2 2006.201.12:40:04.95#ibcon#about to read 4, iclass 31, count 2 2006.201.12:40:04.95#ibcon#read 4, iclass 31, count 2 2006.201.12:40:04.95#ibcon#about to read 5, iclass 31, count 2 2006.201.12:40:04.95#ibcon#read 5, iclass 31, count 2 2006.201.12:40:04.95#ibcon#about to read 6, iclass 31, count 2 2006.201.12:40:04.95#ibcon#read 6, iclass 31, count 2 2006.201.12:40:04.95#ibcon#end of sib2, iclass 31, count 2 2006.201.12:40:04.95#ibcon#*mode == 0, iclass 31, count 2 2006.201.12:40:04.95#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.12:40:04.95#ibcon#[25=AT01-08\r\n] 2006.201.12:40:04.95#ibcon#*before write, iclass 31, count 2 2006.201.12:40:04.95#ibcon#enter sib2, iclass 31, count 2 2006.201.12:40:04.95#ibcon#flushed, iclass 31, count 2 2006.201.12:40:04.95#ibcon#about to write, iclass 31, count 2 2006.201.12:40:04.95#ibcon#wrote, iclass 31, count 2 2006.201.12:40:04.95#ibcon#about to read 3, iclass 31, count 2 2006.201.12:40:04.99#ibcon#read 3, iclass 31, count 2 2006.201.12:40:04.99#ibcon#about to read 4, iclass 31, count 2 2006.201.12:40:04.99#ibcon#read 4, iclass 31, count 2 2006.201.12:40:04.99#ibcon#about to read 5, iclass 31, count 2 2006.201.12:40:04.99#ibcon#read 5, iclass 31, count 2 2006.201.12:40:04.99#ibcon#about to read 6, iclass 31, count 2 2006.201.12:40:04.99#ibcon#read 6, iclass 31, count 2 2006.201.12:40:04.99#ibcon#end of sib2, iclass 31, count 2 2006.201.12:40:04.99#ibcon#*after write, iclass 31, count 2 2006.201.12:40:04.99#ibcon#*before return 0, iclass 31, count 2 2006.201.12:40:04.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:04.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:04.99#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.12:40:04.99#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:04.99#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:05.11#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:05.11#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:05.11#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:40:05.11#ibcon#first serial, iclass 31, count 0 2006.201.12:40:05.11#ibcon#enter sib2, iclass 31, count 0 2006.201.12:40:05.11#ibcon#flushed, iclass 31, count 0 2006.201.12:40:05.11#ibcon#about to write, iclass 31, count 0 2006.201.12:40:05.11#ibcon#wrote, iclass 31, count 0 2006.201.12:40:05.11#ibcon#about to read 3, iclass 31, count 0 2006.201.12:40:05.13#ibcon#read 3, iclass 31, count 0 2006.201.12:40:05.13#ibcon#about to read 4, iclass 31, count 0 2006.201.12:40:05.13#ibcon#read 4, iclass 31, count 0 2006.201.12:40:05.13#ibcon#about to read 5, iclass 31, count 0 2006.201.12:40:05.13#ibcon#read 5, iclass 31, count 0 2006.201.12:40:05.13#ibcon#about to read 6, iclass 31, count 0 2006.201.12:40:05.13#ibcon#read 6, iclass 31, count 0 2006.201.12:40:05.13#ibcon#end of sib2, iclass 31, count 0 2006.201.12:40:05.13#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:40:05.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:40:05.13#ibcon#[25=USB\r\n] 2006.201.12:40:05.13#ibcon#*before write, iclass 31, count 0 2006.201.12:40:05.13#ibcon#enter sib2, iclass 31, count 0 2006.201.12:40:05.13#ibcon#flushed, iclass 31, count 0 2006.201.12:40:05.13#ibcon#about to write, iclass 31, count 0 2006.201.12:40:05.13#ibcon#wrote, iclass 31, count 0 2006.201.12:40:05.13#ibcon#about to read 3, iclass 31, count 0 2006.201.12:40:05.16#ibcon#read 3, iclass 31, count 0 2006.201.12:40:05.16#ibcon#about to read 4, iclass 31, count 0 2006.201.12:40:05.16#ibcon#read 4, iclass 31, count 0 2006.201.12:40:05.16#ibcon#about to read 5, iclass 31, count 0 2006.201.12:40:05.16#ibcon#read 5, iclass 31, count 0 2006.201.12:40:05.16#ibcon#about to read 6, iclass 31, count 0 2006.201.12:40:05.16#ibcon#read 6, iclass 31, count 0 2006.201.12:40:05.16#ibcon#end of sib2, iclass 31, count 0 2006.201.12:40:05.16#ibcon#*after write, iclass 31, count 0 2006.201.12:40:05.16#ibcon#*before return 0, iclass 31, count 0 2006.201.12:40:05.16#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:05.16#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:05.16#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:40:05.16#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:40:05.16$vck44/valo=2,534.99 2006.201.12:40:05.16#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.12:40:05.16#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.12:40:05.16#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:05.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:05.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:05.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:05.16#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:40:05.16#ibcon#first serial, iclass 33, count 0 2006.201.12:40:05.16#ibcon#enter sib2, iclass 33, count 0 2006.201.12:40:05.16#ibcon#flushed, iclass 33, count 0 2006.201.12:40:05.16#ibcon#about to write, iclass 33, count 0 2006.201.12:40:05.16#ibcon#wrote, iclass 33, count 0 2006.201.12:40:05.16#ibcon#about to read 3, iclass 33, count 0 2006.201.12:40:05.18#ibcon#read 3, iclass 33, count 0 2006.201.12:40:05.18#ibcon#about to read 4, iclass 33, count 0 2006.201.12:40:05.18#ibcon#read 4, iclass 33, count 0 2006.201.12:40:05.18#ibcon#about to read 5, iclass 33, count 0 2006.201.12:40:05.18#ibcon#read 5, iclass 33, count 0 2006.201.12:40:05.18#ibcon#about to read 6, iclass 33, count 0 2006.201.12:40:05.18#ibcon#read 6, iclass 33, count 0 2006.201.12:40:05.18#ibcon#end of sib2, iclass 33, count 0 2006.201.12:40:05.18#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:40:05.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:40:05.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:40:05.18#ibcon#*before write, iclass 33, count 0 2006.201.12:40:05.18#ibcon#enter sib2, iclass 33, count 0 2006.201.12:40:05.18#ibcon#flushed, iclass 33, count 0 2006.201.12:40:05.18#ibcon#about to write, iclass 33, count 0 2006.201.12:40:05.18#ibcon#wrote, iclass 33, count 0 2006.201.12:40:05.18#ibcon#about to read 3, iclass 33, count 0 2006.201.12:40:05.23#ibcon#read 3, iclass 33, count 0 2006.201.12:40:05.23#ibcon#about to read 4, iclass 33, count 0 2006.201.12:40:05.23#ibcon#read 4, iclass 33, count 0 2006.201.12:40:05.23#ibcon#about to read 5, iclass 33, count 0 2006.201.12:40:05.23#ibcon#read 5, iclass 33, count 0 2006.201.12:40:05.23#ibcon#about to read 6, iclass 33, count 0 2006.201.12:40:05.23#ibcon#read 6, iclass 33, count 0 2006.201.12:40:05.23#ibcon#end of sib2, iclass 33, count 0 2006.201.12:40:05.23#ibcon#*after write, iclass 33, count 0 2006.201.12:40:05.23#ibcon#*before return 0, iclass 33, count 0 2006.201.12:40:05.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:05.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:05.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:40:05.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:40:05.23$vck44/va=2,7 2006.201.12:40:05.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.12:40:05.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.12:40:05.23#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:05.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:05.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:05.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:05.28#ibcon#enter wrdev, iclass 35, count 2 2006.201.12:40:05.28#ibcon#first serial, iclass 35, count 2 2006.201.12:40:05.28#ibcon#enter sib2, iclass 35, count 2 2006.201.12:40:05.28#ibcon#flushed, iclass 35, count 2 2006.201.12:40:05.28#ibcon#about to write, iclass 35, count 2 2006.201.12:40:05.28#ibcon#wrote, iclass 35, count 2 2006.201.12:40:05.28#ibcon#about to read 3, iclass 35, count 2 2006.201.12:40:05.30#ibcon#read 3, iclass 35, count 2 2006.201.12:40:05.30#ibcon#about to read 4, iclass 35, count 2 2006.201.12:40:05.30#ibcon#read 4, iclass 35, count 2 2006.201.12:40:05.30#ibcon#about to read 5, iclass 35, count 2 2006.201.12:40:05.30#ibcon#read 5, iclass 35, count 2 2006.201.12:40:05.30#ibcon#about to read 6, iclass 35, count 2 2006.201.12:40:05.30#ibcon#read 6, iclass 35, count 2 2006.201.12:40:05.30#ibcon#end of sib2, iclass 35, count 2 2006.201.12:40:05.30#ibcon#*mode == 0, iclass 35, count 2 2006.201.12:40:05.30#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.12:40:05.30#ibcon#[25=AT02-07\r\n] 2006.201.12:40:05.30#ibcon#*before write, iclass 35, count 2 2006.201.12:40:05.30#ibcon#enter sib2, iclass 35, count 2 2006.201.12:40:05.30#ibcon#flushed, iclass 35, count 2 2006.201.12:40:05.30#ibcon#about to write, iclass 35, count 2 2006.201.12:40:05.30#ibcon#wrote, iclass 35, count 2 2006.201.12:40:05.30#ibcon#about to read 3, iclass 35, count 2 2006.201.12:40:05.33#ibcon#read 3, iclass 35, count 2 2006.201.12:40:05.33#ibcon#about to read 4, iclass 35, count 2 2006.201.12:40:05.33#ibcon#read 4, iclass 35, count 2 2006.201.12:40:05.33#ibcon#about to read 5, iclass 35, count 2 2006.201.12:40:05.33#ibcon#read 5, iclass 35, count 2 2006.201.12:40:05.33#ibcon#about to read 6, iclass 35, count 2 2006.201.12:40:05.33#ibcon#read 6, iclass 35, count 2 2006.201.12:40:05.33#ibcon#end of sib2, iclass 35, count 2 2006.201.12:40:05.33#ibcon#*after write, iclass 35, count 2 2006.201.12:40:05.33#ibcon#*before return 0, iclass 35, count 2 2006.201.12:40:05.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:05.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:05.33#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.12:40:05.33#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:05.33#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:05.45#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:05.45#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:05.45#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:40:05.45#ibcon#first serial, iclass 35, count 0 2006.201.12:40:05.45#ibcon#enter sib2, iclass 35, count 0 2006.201.12:40:05.45#ibcon#flushed, iclass 35, count 0 2006.201.12:40:05.45#ibcon#about to write, iclass 35, count 0 2006.201.12:40:05.45#ibcon#wrote, iclass 35, count 0 2006.201.12:40:05.45#ibcon#about to read 3, iclass 35, count 0 2006.201.12:40:05.47#ibcon#read 3, iclass 35, count 0 2006.201.12:40:05.47#ibcon#about to read 4, iclass 35, count 0 2006.201.12:40:05.47#ibcon#read 4, iclass 35, count 0 2006.201.12:40:05.47#ibcon#about to read 5, iclass 35, count 0 2006.201.12:40:05.47#ibcon#read 5, iclass 35, count 0 2006.201.12:40:05.47#ibcon#about to read 6, iclass 35, count 0 2006.201.12:40:05.47#ibcon#read 6, iclass 35, count 0 2006.201.12:40:05.47#ibcon#end of sib2, iclass 35, count 0 2006.201.12:40:05.47#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:40:05.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:40:05.47#ibcon#[25=USB\r\n] 2006.201.12:40:05.47#ibcon#*before write, iclass 35, count 0 2006.201.12:40:05.47#ibcon#enter sib2, iclass 35, count 0 2006.201.12:40:05.47#ibcon#flushed, iclass 35, count 0 2006.201.12:40:05.47#ibcon#about to write, iclass 35, count 0 2006.201.12:40:05.47#ibcon#wrote, iclass 35, count 0 2006.201.12:40:05.47#ibcon#about to read 3, iclass 35, count 0 2006.201.12:40:05.50#ibcon#read 3, iclass 35, count 0 2006.201.12:40:05.50#ibcon#about to read 4, iclass 35, count 0 2006.201.12:40:05.50#ibcon#read 4, iclass 35, count 0 2006.201.12:40:05.50#ibcon#about to read 5, iclass 35, count 0 2006.201.12:40:05.50#ibcon#read 5, iclass 35, count 0 2006.201.12:40:05.50#ibcon#about to read 6, iclass 35, count 0 2006.201.12:40:05.50#ibcon#read 6, iclass 35, count 0 2006.201.12:40:05.50#ibcon#end of sib2, iclass 35, count 0 2006.201.12:40:05.50#ibcon#*after write, iclass 35, count 0 2006.201.12:40:05.50#ibcon#*before return 0, iclass 35, count 0 2006.201.12:40:05.50#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:05.50#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:05.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:40:05.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:40:05.50$vck44/valo=3,564.99 2006.201.12:40:05.50#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.12:40:05.50#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.12:40:05.50#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:05.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:05.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:05.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:05.50#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:40:05.50#ibcon#first serial, iclass 37, count 0 2006.201.12:40:05.50#ibcon#enter sib2, iclass 37, count 0 2006.201.12:40:05.50#ibcon#flushed, iclass 37, count 0 2006.201.12:40:05.50#ibcon#about to write, iclass 37, count 0 2006.201.12:40:05.50#ibcon#wrote, iclass 37, count 0 2006.201.12:40:05.50#ibcon#about to read 3, iclass 37, count 0 2006.201.12:40:05.52#ibcon#read 3, iclass 37, count 0 2006.201.12:40:05.52#ibcon#about to read 4, iclass 37, count 0 2006.201.12:40:05.52#ibcon#read 4, iclass 37, count 0 2006.201.12:40:05.52#ibcon#about to read 5, iclass 37, count 0 2006.201.12:40:05.52#ibcon#read 5, iclass 37, count 0 2006.201.12:40:05.52#ibcon#about to read 6, iclass 37, count 0 2006.201.12:40:05.52#ibcon#read 6, iclass 37, count 0 2006.201.12:40:05.52#ibcon#end of sib2, iclass 37, count 0 2006.201.12:40:05.52#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:40:05.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:40:05.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:40:05.52#ibcon#*before write, iclass 37, count 0 2006.201.12:40:05.52#ibcon#enter sib2, iclass 37, count 0 2006.201.12:40:05.52#ibcon#flushed, iclass 37, count 0 2006.201.12:40:05.52#ibcon#about to write, iclass 37, count 0 2006.201.12:40:05.52#ibcon#wrote, iclass 37, count 0 2006.201.12:40:05.52#ibcon#about to read 3, iclass 37, count 0 2006.201.12:40:05.57#ibcon#read 3, iclass 37, count 0 2006.201.12:40:05.57#ibcon#about to read 4, iclass 37, count 0 2006.201.12:40:05.57#ibcon#read 4, iclass 37, count 0 2006.201.12:40:05.57#ibcon#about to read 5, iclass 37, count 0 2006.201.12:40:05.57#ibcon#read 5, iclass 37, count 0 2006.201.12:40:05.57#ibcon#about to read 6, iclass 37, count 0 2006.201.12:40:05.57#ibcon#read 6, iclass 37, count 0 2006.201.12:40:05.57#ibcon#end of sib2, iclass 37, count 0 2006.201.12:40:05.57#ibcon#*after write, iclass 37, count 0 2006.201.12:40:05.57#ibcon#*before return 0, iclass 37, count 0 2006.201.12:40:05.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:05.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:05.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:40:05.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:40:05.57$vck44/va=3,8 2006.201.12:40:05.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.12:40:05.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.12:40:05.57#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:05.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:05.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:05.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:05.62#ibcon#enter wrdev, iclass 39, count 2 2006.201.12:40:05.62#ibcon#first serial, iclass 39, count 2 2006.201.12:40:05.62#ibcon#enter sib2, iclass 39, count 2 2006.201.12:40:05.62#ibcon#flushed, iclass 39, count 2 2006.201.12:40:05.62#ibcon#about to write, iclass 39, count 2 2006.201.12:40:05.62#ibcon#wrote, iclass 39, count 2 2006.201.12:40:05.62#ibcon#about to read 3, iclass 39, count 2 2006.201.12:40:05.64#ibcon#read 3, iclass 39, count 2 2006.201.12:40:05.64#ibcon#about to read 4, iclass 39, count 2 2006.201.12:40:05.64#ibcon#read 4, iclass 39, count 2 2006.201.12:40:05.64#ibcon#about to read 5, iclass 39, count 2 2006.201.12:40:05.64#ibcon#read 5, iclass 39, count 2 2006.201.12:40:05.64#ibcon#about to read 6, iclass 39, count 2 2006.201.12:40:05.64#ibcon#read 6, iclass 39, count 2 2006.201.12:40:05.64#ibcon#end of sib2, iclass 39, count 2 2006.201.12:40:05.64#ibcon#*mode == 0, iclass 39, count 2 2006.201.12:40:05.64#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.12:40:05.64#ibcon#[25=AT03-08\r\n] 2006.201.12:40:05.64#ibcon#*before write, iclass 39, count 2 2006.201.12:40:05.64#ibcon#enter sib2, iclass 39, count 2 2006.201.12:40:05.64#ibcon#flushed, iclass 39, count 2 2006.201.12:40:05.64#ibcon#about to write, iclass 39, count 2 2006.201.12:40:05.64#ibcon#wrote, iclass 39, count 2 2006.201.12:40:05.64#ibcon#about to read 3, iclass 39, count 2 2006.201.12:40:05.67#ibcon#read 3, iclass 39, count 2 2006.201.12:40:05.67#ibcon#about to read 4, iclass 39, count 2 2006.201.12:40:05.67#ibcon#read 4, iclass 39, count 2 2006.201.12:40:05.67#ibcon#about to read 5, iclass 39, count 2 2006.201.12:40:05.67#ibcon#read 5, iclass 39, count 2 2006.201.12:40:05.67#ibcon#about to read 6, iclass 39, count 2 2006.201.12:40:05.67#ibcon#read 6, iclass 39, count 2 2006.201.12:40:05.67#ibcon#end of sib2, iclass 39, count 2 2006.201.12:40:05.67#ibcon#*after write, iclass 39, count 2 2006.201.12:40:05.67#ibcon#*before return 0, iclass 39, count 2 2006.201.12:40:05.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:05.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:05.67#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.12:40:05.67#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:05.67#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:05.79#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:05.79#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:05.79#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:40:05.79#ibcon#first serial, iclass 39, count 0 2006.201.12:40:05.79#ibcon#enter sib2, iclass 39, count 0 2006.201.12:40:05.79#ibcon#flushed, iclass 39, count 0 2006.201.12:40:05.79#ibcon#about to write, iclass 39, count 0 2006.201.12:40:05.79#ibcon#wrote, iclass 39, count 0 2006.201.12:40:05.79#ibcon#about to read 3, iclass 39, count 0 2006.201.12:40:05.81#ibcon#read 3, iclass 39, count 0 2006.201.12:40:05.81#ibcon#about to read 4, iclass 39, count 0 2006.201.12:40:05.81#ibcon#read 4, iclass 39, count 0 2006.201.12:40:05.81#ibcon#about to read 5, iclass 39, count 0 2006.201.12:40:05.81#ibcon#read 5, iclass 39, count 0 2006.201.12:40:05.81#ibcon#about to read 6, iclass 39, count 0 2006.201.12:40:05.81#ibcon#read 6, iclass 39, count 0 2006.201.12:40:05.81#ibcon#end of sib2, iclass 39, count 0 2006.201.12:40:05.81#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:40:05.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:40:05.81#ibcon#[25=USB\r\n] 2006.201.12:40:05.81#ibcon#*before write, iclass 39, count 0 2006.201.12:40:05.81#ibcon#enter sib2, iclass 39, count 0 2006.201.12:40:05.81#ibcon#flushed, iclass 39, count 0 2006.201.12:40:05.81#ibcon#about to write, iclass 39, count 0 2006.201.12:40:05.81#ibcon#wrote, iclass 39, count 0 2006.201.12:40:05.81#ibcon#about to read 3, iclass 39, count 0 2006.201.12:40:05.84#ibcon#read 3, iclass 39, count 0 2006.201.12:40:05.84#ibcon#about to read 4, iclass 39, count 0 2006.201.12:40:05.84#ibcon#read 4, iclass 39, count 0 2006.201.12:40:05.84#ibcon#about to read 5, iclass 39, count 0 2006.201.12:40:05.84#ibcon#read 5, iclass 39, count 0 2006.201.12:40:05.84#ibcon#about to read 6, iclass 39, count 0 2006.201.12:40:05.84#ibcon#read 6, iclass 39, count 0 2006.201.12:40:05.84#ibcon#end of sib2, iclass 39, count 0 2006.201.12:40:05.84#ibcon#*after write, iclass 39, count 0 2006.201.12:40:05.84#ibcon#*before return 0, iclass 39, count 0 2006.201.12:40:05.84#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:05.84#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:05.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:40:05.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:40:05.84$vck44/valo=4,624.99 2006.201.12:40:05.84#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.12:40:05.84#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.12:40:05.84#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:05.84#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:05.84#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:05.84#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:05.84#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:40:05.84#ibcon#first serial, iclass 2, count 0 2006.201.12:40:05.84#ibcon#enter sib2, iclass 2, count 0 2006.201.12:40:05.84#ibcon#flushed, iclass 2, count 0 2006.201.12:40:05.84#ibcon#about to write, iclass 2, count 0 2006.201.12:40:05.84#ibcon#wrote, iclass 2, count 0 2006.201.12:40:05.84#ibcon#about to read 3, iclass 2, count 0 2006.201.12:40:05.86#ibcon#read 3, iclass 2, count 0 2006.201.12:40:05.86#ibcon#about to read 4, iclass 2, count 0 2006.201.12:40:05.86#ibcon#read 4, iclass 2, count 0 2006.201.12:40:05.86#ibcon#about to read 5, iclass 2, count 0 2006.201.12:40:05.86#ibcon#read 5, iclass 2, count 0 2006.201.12:40:05.86#ibcon#about to read 6, iclass 2, count 0 2006.201.12:40:05.86#ibcon#read 6, iclass 2, count 0 2006.201.12:40:05.86#ibcon#end of sib2, iclass 2, count 0 2006.201.12:40:05.86#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:40:05.86#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:40:05.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:40:05.86#ibcon#*before write, iclass 2, count 0 2006.201.12:40:05.86#ibcon#enter sib2, iclass 2, count 0 2006.201.12:40:05.86#ibcon#flushed, iclass 2, count 0 2006.201.12:40:05.86#ibcon#about to write, iclass 2, count 0 2006.201.12:40:05.86#ibcon#wrote, iclass 2, count 0 2006.201.12:40:05.86#ibcon#about to read 3, iclass 2, count 0 2006.201.12:40:05.91#ibcon#read 3, iclass 2, count 0 2006.201.12:40:05.91#ibcon#about to read 4, iclass 2, count 0 2006.201.12:40:05.91#ibcon#read 4, iclass 2, count 0 2006.201.12:40:05.91#ibcon#about to read 5, iclass 2, count 0 2006.201.12:40:05.91#ibcon#read 5, iclass 2, count 0 2006.201.12:40:05.91#ibcon#about to read 6, iclass 2, count 0 2006.201.12:40:05.91#ibcon#read 6, iclass 2, count 0 2006.201.12:40:05.91#ibcon#end of sib2, iclass 2, count 0 2006.201.12:40:05.91#ibcon#*after write, iclass 2, count 0 2006.201.12:40:05.91#ibcon#*before return 0, iclass 2, count 0 2006.201.12:40:05.91#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:05.91#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:05.91#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:40:05.91#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:40:05.91$vck44/va=4,7 2006.201.12:40:05.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.12:40:05.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.12:40:05.91#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:05.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:05.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:05.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:05.96#ibcon#enter wrdev, iclass 5, count 2 2006.201.12:40:05.96#ibcon#first serial, iclass 5, count 2 2006.201.12:40:05.96#ibcon#enter sib2, iclass 5, count 2 2006.201.12:40:05.96#ibcon#flushed, iclass 5, count 2 2006.201.12:40:05.96#ibcon#about to write, iclass 5, count 2 2006.201.12:40:05.96#ibcon#wrote, iclass 5, count 2 2006.201.12:40:05.96#ibcon#about to read 3, iclass 5, count 2 2006.201.12:40:05.98#ibcon#read 3, iclass 5, count 2 2006.201.12:40:05.98#ibcon#about to read 4, iclass 5, count 2 2006.201.12:40:05.98#ibcon#read 4, iclass 5, count 2 2006.201.12:40:05.98#ibcon#about to read 5, iclass 5, count 2 2006.201.12:40:05.98#ibcon#read 5, iclass 5, count 2 2006.201.12:40:05.98#ibcon#about to read 6, iclass 5, count 2 2006.201.12:40:05.98#ibcon#read 6, iclass 5, count 2 2006.201.12:40:05.98#ibcon#end of sib2, iclass 5, count 2 2006.201.12:40:05.98#ibcon#*mode == 0, iclass 5, count 2 2006.201.12:40:05.98#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.12:40:05.98#ibcon#[25=AT04-07\r\n] 2006.201.12:40:05.98#ibcon#*before write, iclass 5, count 2 2006.201.12:40:05.98#ibcon#enter sib2, iclass 5, count 2 2006.201.12:40:05.98#ibcon#flushed, iclass 5, count 2 2006.201.12:40:05.98#ibcon#about to write, iclass 5, count 2 2006.201.12:40:05.98#ibcon#wrote, iclass 5, count 2 2006.201.12:40:05.98#ibcon#about to read 3, iclass 5, count 2 2006.201.12:40:06.01#ibcon#read 3, iclass 5, count 2 2006.201.12:40:06.01#ibcon#about to read 4, iclass 5, count 2 2006.201.12:40:06.01#ibcon#read 4, iclass 5, count 2 2006.201.12:40:06.01#ibcon#about to read 5, iclass 5, count 2 2006.201.12:40:06.01#ibcon#read 5, iclass 5, count 2 2006.201.12:40:06.01#ibcon#about to read 6, iclass 5, count 2 2006.201.12:40:06.01#ibcon#read 6, iclass 5, count 2 2006.201.12:40:06.01#ibcon#end of sib2, iclass 5, count 2 2006.201.12:40:06.01#ibcon#*after write, iclass 5, count 2 2006.201.12:40:06.01#ibcon#*before return 0, iclass 5, count 2 2006.201.12:40:06.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:06.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:06.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.12:40:06.01#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:06.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:06.13#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:06.13#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:06.13#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:40:06.13#ibcon#first serial, iclass 5, count 0 2006.201.12:40:06.13#ibcon#enter sib2, iclass 5, count 0 2006.201.12:40:06.13#ibcon#flushed, iclass 5, count 0 2006.201.12:40:06.13#ibcon#about to write, iclass 5, count 0 2006.201.12:40:06.13#ibcon#wrote, iclass 5, count 0 2006.201.12:40:06.13#ibcon#about to read 3, iclass 5, count 0 2006.201.12:40:06.15#ibcon#read 3, iclass 5, count 0 2006.201.12:40:06.15#ibcon#about to read 4, iclass 5, count 0 2006.201.12:40:06.15#ibcon#read 4, iclass 5, count 0 2006.201.12:40:06.15#ibcon#about to read 5, iclass 5, count 0 2006.201.12:40:06.15#ibcon#read 5, iclass 5, count 0 2006.201.12:40:06.15#ibcon#about to read 6, iclass 5, count 0 2006.201.12:40:06.15#ibcon#read 6, iclass 5, count 0 2006.201.12:40:06.15#ibcon#end of sib2, iclass 5, count 0 2006.201.12:40:06.15#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:40:06.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:40:06.15#ibcon#[25=USB\r\n] 2006.201.12:40:06.15#ibcon#*before write, iclass 5, count 0 2006.201.12:40:06.15#ibcon#enter sib2, iclass 5, count 0 2006.201.12:40:06.15#ibcon#flushed, iclass 5, count 0 2006.201.12:40:06.15#ibcon#about to write, iclass 5, count 0 2006.201.12:40:06.15#ibcon#wrote, iclass 5, count 0 2006.201.12:40:06.15#ibcon#about to read 3, iclass 5, count 0 2006.201.12:40:06.18#ibcon#read 3, iclass 5, count 0 2006.201.12:40:06.18#ibcon#about to read 4, iclass 5, count 0 2006.201.12:40:06.18#ibcon#read 4, iclass 5, count 0 2006.201.12:40:06.18#ibcon#about to read 5, iclass 5, count 0 2006.201.12:40:06.18#ibcon#read 5, iclass 5, count 0 2006.201.12:40:06.18#ibcon#about to read 6, iclass 5, count 0 2006.201.12:40:06.18#ibcon#read 6, iclass 5, count 0 2006.201.12:40:06.18#ibcon#end of sib2, iclass 5, count 0 2006.201.12:40:06.18#ibcon#*after write, iclass 5, count 0 2006.201.12:40:06.18#ibcon#*before return 0, iclass 5, count 0 2006.201.12:40:06.18#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:06.18#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:06.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:40:06.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:40:06.18$vck44/valo=5,734.99 2006.201.12:40:06.18#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.12:40:06.18#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.12:40:06.18#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:06.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:06.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:06.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:06.18#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:40:06.18#ibcon#first serial, iclass 7, count 0 2006.201.12:40:06.18#ibcon#enter sib2, iclass 7, count 0 2006.201.12:40:06.18#ibcon#flushed, iclass 7, count 0 2006.201.12:40:06.18#ibcon#about to write, iclass 7, count 0 2006.201.12:40:06.18#ibcon#wrote, iclass 7, count 0 2006.201.12:40:06.18#ibcon#about to read 3, iclass 7, count 0 2006.201.12:40:06.20#ibcon#read 3, iclass 7, count 0 2006.201.12:40:06.20#ibcon#about to read 4, iclass 7, count 0 2006.201.12:40:06.20#ibcon#read 4, iclass 7, count 0 2006.201.12:40:06.20#ibcon#about to read 5, iclass 7, count 0 2006.201.12:40:06.20#ibcon#read 5, iclass 7, count 0 2006.201.12:40:06.20#ibcon#about to read 6, iclass 7, count 0 2006.201.12:40:06.20#ibcon#read 6, iclass 7, count 0 2006.201.12:40:06.20#ibcon#end of sib2, iclass 7, count 0 2006.201.12:40:06.20#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:40:06.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:40:06.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:40:06.20#ibcon#*before write, iclass 7, count 0 2006.201.12:40:06.20#ibcon#enter sib2, iclass 7, count 0 2006.201.12:40:06.20#ibcon#flushed, iclass 7, count 0 2006.201.12:40:06.20#ibcon#about to write, iclass 7, count 0 2006.201.12:40:06.20#ibcon#wrote, iclass 7, count 0 2006.201.12:40:06.20#ibcon#about to read 3, iclass 7, count 0 2006.201.12:40:06.24#ibcon#read 3, iclass 7, count 0 2006.201.12:40:06.24#ibcon#about to read 4, iclass 7, count 0 2006.201.12:40:06.24#ibcon#read 4, iclass 7, count 0 2006.201.12:40:06.24#ibcon#about to read 5, iclass 7, count 0 2006.201.12:40:06.24#ibcon#read 5, iclass 7, count 0 2006.201.12:40:06.24#ibcon#about to read 6, iclass 7, count 0 2006.201.12:40:06.24#ibcon#read 6, iclass 7, count 0 2006.201.12:40:06.24#ibcon#end of sib2, iclass 7, count 0 2006.201.12:40:06.24#ibcon#*after write, iclass 7, count 0 2006.201.12:40:06.24#ibcon#*before return 0, iclass 7, count 0 2006.201.12:40:06.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:06.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:06.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:40:06.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:40:06.24$vck44/va=5,4 2006.201.12:40:06.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.12:40:06.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.12:40:06.24#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:06.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:06.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:06.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:06.30#ibcon#enter wrdev, iclass 11, count 2 2006.201.12:40:06.30#ibcon#first serial, iclass 11, count 2 2006.201.12:40:06.30#ibcon#enter sib2, iclass 11, count 2 2006.201.12:40:06.30#ibcon#flushed, iclass 11, count 2 2006.201.12:40:06.30#ibcon#about to write, iclass 11, count 2 2006.201.12:40:06.30#ibcon#wrote, iclass 11, count 2 2006.201.12:40:06.30#ibcon#about to read 3, iclass 11, count 2 2006.201.12:40:06.32#ibcon#read 3, iclass 11, count 2 2006.201.12:40:06.32#ibcon#about to read 4, iclass 11, count 2 2006.201.12:40:06.32#ibcon#read 4, iclass 11, count 2 2006.201.12:40:06.32#ibcon#about to read 5, iclass 11, count 2 2006.201.12:40:06.32#ibcon#read 5, iclass 11, count 2 2006.201.12:40:06.32#ibcon#about to read 6, iclass 11, count 2 2006.201.12:40:06.32#ibcon#read 6, iclass 11, count 2 2006.201.12:40:06.32#ibcon#end of sib2, iclass 11, count 2 2006.201.12:40:06.32#ibcon#*mode == 0, iclass 11, count 2 2006.201.12:40:06.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.12:40:06.32#ibcon#[25=AT05-04\r\n] 2006.201.12:40:06.32#ibcon#*before write, iclass 11, count 2 2006.201.12:40:06.32#ibcon#enter sib2, iclass 11, count 2 2006.201.12:40:06.32#ibcon#flushed, iclass 11, count 2 2006.201.12:40:06.32#ibcon#about to write, iclass 11, count 2 2006.201.12:40:06.32#ibcon#wrote, iclass 11, count 2 2006.201.12:40:06.32#ibcon#about to read 3, iclass 11, count 2 2006.201.12:40:06.35#ibcon#read 3, iclass 11, count 2 2006.201.12:40:06.35#ibcon#about to read 4, iclass 11, count 2 2006.201.12:40:06.35#ibcon#read 4, iclass 11, count 2 2006.201.12:40:06.35#ibcon#about to read 5, iclass 11, count 2 2006.201.12:40:06.35#ibcon#read 5, iclass 11, count 2 2006.201.12:40:06.35#ibcon#about to read 6, iclass 11, count 2 2006.201.12:40:06.35#ibcon#read 6, iclass 11, count 2 2006.201.12:40:06.35#ibcon#end of sib2, iclass 11, count 2 2006.201.12:40:06.35#ibcon#*after write, iclass 11, count 2 2006.201.12:40:06.35#ibcon#*before return 0, iclass 11, count 2 2006.201.12:40:06.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:06.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:06.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.12:40:06.35#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:06.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:06.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:06.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:06.47#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:40:06.47#ibcon#first serial, iclass 11, count 0 2006.201.12:40:06.47#ibcon#enter sib2, iclass 11, count 0 2006.201.12:40:06.47#ibcon#flushed, iclass 11, count 0 2006.201.12:40:06.47#ibcon#about to write, iclass 11, count 0 2006.201.12:40:06.47#ibcon#wrote, iclass 11, count 0 2006.201.12:40:06.47#ibcon#about to read 3, iclass 11, count 0 2006.201.12:40:06.49#ibcon#read 3, iclass 11, count 0 2006.201.12:40:06.49#ibcon#about to read 4, iclass 11, count 0 2006.201.12:40:06.49#ibcon#read 4, iclass 11, count 0 2006.201.12:40:06.49#ibcon#about to read 5, iclass 11, count 0 2006.201.12:40:06.49#ibcon#read 5, iclass 11, count 0 2006.201.12:40:06.49#ibcon#about to read 6, iclass 11, count 0 2006.201.12:40:06.49#ibcon#read 6, iclass 11, count 0 2006.201.12:40:06.49#ibcon#end of sib2, iclass 11, count 0 2006.201.12:40:06.49#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:40:06.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:40:06.49#ibcon#[25=USB\r\n] 2006.201.12:40:06.49#ibcon#*before write, iclass 11, count 0 2006.201.12:40:06.49#ibcon#enter sib2, iclass 11, count 0 2006.201.12:40:06.49#ibcon#flushed, iclass 11, count 0 2006.201.12:40:06.49#ibcon#about to write, iclass 11, count 0 2006.201.12:40:06.49#ibcon#wrote, iclass 11, count 0 2006.201.12:40:06.49#ibcon#about to read 3, iclass 11, count 0 2006.201.12:40:06.52#ibcon#read 3, iclass 11, count 0 2006.201.12:40:06.52#ibcon#about to read 4, iclass 11, count 0 2006.201.12:40:06.52#ibcon#read 4, iclass 11, count 0 2006.201.12:40:06.52#ibcon#about to read 5, iclass 11, count 0 2006.201.12:40:06.52#ibcon#read 5, iclass 11, count 0 2006.201.12:40:06.52#ibcon#about to read 6, iclass 11, count 0 2006.201.12:40:06.52#ibcon#read 6, iclass 11, count 0 2006.201.12:40:06.52#ibcon#end of sib2, iclass 11, count 0 2006.201.12:40:06.52#ibcon#*after write, iclass 11, count 0 2006.201.12:40:06.52#ibcon#*before return 0, iclass 11, count 0 2006.201.12:40:06.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:06.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:06.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:40:06.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:40:06.52$vck44/valo=6,814.99 2006.201.12:40:06.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.12:40:06.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.12:40:06.52#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:06.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:06.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:06.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:06.52#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:40:06.52#ibcon#first serial, iclass 13, count 0 2006.201.12:40:06.52#ibcon#enter sib2, iclass 13, count 0 2006.201.12:40:06.52#ibcon#flushed, iclass 13, count 0 2006.201.12:40:06.52#ibcon#about to write, iclass 13, count 0 2006.201.12:40:06.52#ibcon#wrote, iclass 13, count 0 2006.201.12:40:06.52#ibcon#about to read 3, iclass 13, count 0 2006.201.12:40:06.54#ibcon#read 3, iclass 13, count 0 2006.201.12:40:06.54#ibcon#about to read 4, iclass 13, count 0 2006.201.12:40:06.54#ibcon#read 4, iclass 13, count 0 2006.201.12:40:06.54#ibcon#about to read 5, iclass 13, count 0 2006.201.12:40:06.54#ibcon#read 5, iclass 13, count 0 2006.201.12:40:06.54#ibcon#about to read 6, iclass 13, count 0 2006.201.12:40:06.54#ibcon#read 6, iclass 13, count 0 2006.201.12:40:06.54#ibcon#end of sib2, iclass 13, count 0 2006.201.12:40:06.54#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:40:06.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:40:06.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:40:06.54#ibcon#*before write, iclass 13, count 0 2006.201.12:40:06.54#ibcon#enter sib2, iclass 13, count 0 2006.201.12:40:06.54#ibcon#flushed, iclass 13, count 0 2006.201.12:40:06.54#ibcon#about to write, iclass 13, count 0 2006.201.12:40:06.54#ibcon#wrote, iclass 13, count 0 2006.201.12:40:06.54#ibcon#about to read 3, iclass 13, count 0 2006.201.12:40:06.59#ibcon#read 3, iclass 13, count 0 2006.201.12:40:06.59#ibcon#about to read 4, iclass 13, count 0 2006.201.12:40:06.59#ibcon#read 4, iclass 13, count 0 2006.201.12:40:06.59#ibcon#about to read 5, iclass 13, count 0 2006.201.12:40:06.59#ibcon#read 5, iclass 13, count 0 2006.201.12:40:06.59#ibcon#about to read 6, iclass 13, count 0 2006.201.12:40:06.59#ibcon#read 6, iclass 13, count 0 2006.201.12:40:06.59#ibcon#end of sib2, iclass 13, count 0 2006.201.12:40:06.59#ibcon#*after write, iclass 13, count 0 2006.201.12:40:06.59#ibcon#*before return 0, iclass 13, count 0 2006.201.12:40:06.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:06.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:06.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:40:06.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:40:06.59$vck44/va=6,5 2006.201.12:40:06.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.12:40:06.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.12:40:06.59#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:06.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:06.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:06.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:06.64#ibcon#enter wrdev, iclass 15, count 2 2006.201.12:40:06.64#ibcon#first serial, iclass 15, count 2 2006.201.12:40:06.64#ibcon#enter sib2, iclass 15, count 2 2006.201.12:40:06.64#ibcon#flushed, iclass 15, count 2 2006.201.12:40:06.64#ibcon#about to write, iclass 15, count 2 2006.201.12:40:06.64#ibcon#wrote, iclass 15, count 2 2006.201.12:40:06.64#ibcon#about to read 3, iclass 15, count 2 2006.201.12:40:06.66#ibcon#read 3, iclass 15, count 2 2006.201.12:40:06.66#ibcon#about to read 4, iclass 15, count 2 2006.201.12:40:06.66#ibcon#read 4, iclass 15, count 2 2006.201.12:40:06.66#ibcon#about to read 5, iclass 15, count 2 2006.201.12:40:06.66#ibcon#read 5, iclass 15, count 2 2006.201.12:40:06.66#ibcon#about to read 6, iclass 15, count 2 2006.201.12:40:06.66#ibcon#read 6, iclass 15, count 2 2006.201.12:40:06.66#ibcon#end of sib2, iclass 15, count 2 2006.201.12:40:06.66#ibcon#*mode == 0, iclass 15, count 2 2006.201.12:40:06.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.12:40:06.66#ibcon#[25=AT06-05\r\n] 2006.201.12:40:06.66#ibcon#*before write, iclass 15, count 2 2006.201.12:40:06.66#ibcon#enter sib2, iclass 15, count 2 2006.201.12:40:06.66#ibcon#flushed, iclass 15, count 2 2006.201.12:40:06.66#ibcon#about to write, iclass 15, count 2 2006.201.12:40:06.66#ibcon#wrote, iclass 15, count 2 2006.201.12:40:06.66#ibcon#about to read 3, iclass 15, count 2 2006.201.12:40:06.69#ibcon#read 3, iclass 15, count 2 2006.201.12:40:06.69#ibcon#about to read 4, iclass 15, count 2 2006.201.12:40:06.69#ibcon#read 4, iclass 15, count 2 2006.201.12:40:06.69#ibcon#about to read 5, iclass 15, count 2 2006.201.12:40:06.69#ibcon#read 5, iclass 15, count 2 2006.201.12:40:06.69#ibcon#about to read 6, iclass 15, count 2 2006.201.12:40:06.69#ibcon#read 6, iclass 15, count 2 2006.201.12:40:06.69#ibcon#end of sib2, iclass 15, count 2 2006.201.12:40:06.69#ibcon#*after write, iclass 15, count 2 2006.201.12:40:06.69#ibcon#*before return 0, iclass 15, count 2 2006.201.12:40:06.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:06.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:06.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.12:40:06.69#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:06.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:06.81#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:06.81#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:06.81#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:40:06.81#ibcon#first serial, iclass 15, count 0 2006.201.12:40:06.81#ibcon#enter sib2, iclass 15, count 0 2006.201.12:40:06.81#ibcon#flushed, iclass 15, count 0 2006.201.12:40:06.81#ibcon#about to write, iclass 15, count 0 2006.201.12:40:06.81#ibcon#wrote, iclass 15, count 0 2006.201.12:40:06.81#ibcon#about to read 3, iclass 15, count 0 2006.201.12:40:06.83#ibcon#read 3, iclass 15, count 0 2006.201.12:40:06.83#ibcon#about to read 4, iclass 15, count 0 2006.201.12:40:06.83#ibcon#read 4, iclass 15, count 0 2006.201.12:40:06.83#ibcon#about to read 5, iclass 15, count 0 2006.201.12:40:06.83#ibcon#read 5, iclass 15, count 0 2006.201.12:40:06.83#ibcon#about to read 6, iclass 15, count 0 2006.201.12:40:06.83#ibcon#read 6, iclass 15, count 0 2006.201.12:40:06.83#ibcon#end of sib2, iclass 15, count 0 2006.201.12:40:06.83#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:40:06.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:40:06.83#ibcon#[25=USB\r\n] 2006.201.12:40:06.83#ibcon#*before write, iclass 15, count 0 2006.201.12:40:06.83#ibcon#enter sib2, iclass 15, count 0 2006.201.12:40:06.83#ibcon#flushed, iclass 15, count 0 2006.201.12:40:06.83#ibcon#about to write, iclass 15, count 0 2006.201.12:40:06.83#ibcon#wrote, iclass 15, count 0 2006.201.12:40:06.83#ibcon#about to read 3, iclass 15, count 0 2006.201.12:40:06.86#ibcon#read 3, iclass 15, count 0 2006.201.12:40:06.86#ibcon#about to read 4, iclass 15, count 0 2006.201.12:40:06.86#ibcon#read 4, iclass 15, count 0 2006.201.12:40:06.86#ibcon#about to read 5, iclass 15, count 0 2006.201.12:40:06.86#ibcon#read 5, iclass 15, count 0 2006.201.12:40:06.86#ibcon#about to read 6, iclass 15, count 0 2006.201.12:40:06.86#ibcon#read 6, iclass 15, count 0 2006.201.12:40:06.86#ibcon#end of sib2, iclass 15, count 0 2006.201.12:40:06.86#ibcon#*after write, iclass 15, count 0 2006.201.12:40:06.86#ibcon#*before return 0, iclass 15, count 0 2006.201.12:40:06.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:06.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:06.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:40:06.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:40:06.86$vck44/valo=7,864.99 2006.201.12:40:06.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.12:40:06.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.12:40:06.86#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:06.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:06.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:06.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:06.86#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:40:06.86#ibcon#first serial, iclass 17, count 0 2006.201.12:40:06.86#ibcon#enter sib2, iclass 17, count 0 2006.201.12:40:06.86#ibcon#flushed, iclass 17, count 0 2006.201.12:40:06.86#ibcon#about to write, iclass 17, count 0 2006.201.12:40:06.86#ibcon#wrote, iclass 17, count 0 2006.201.12:40:06.86#ibcon#about to read 3, iclass 17, count 0 2006.201.12:40:06.88#ibcon#read 3, iclass 17, count 0 2006.201.12:40:06.88#ibcon#about to read 4, iclass 17, count 0 2006.201.12:40:06.88#ibcon#read 4, iclass 17, count 0 2006.201.12:40:06.88#ibcon#about to read 5, iclass 17, count 0 2006.201.12:40:06.88#ibcon#read 5, iclass 17, count 0 2006.201.12:40:06.88#ibcon#about to read 6, iclass 17, count 0 2006.201.12:40:06.88#ibcon#read 6, iclass 17, count 0 2006.201.12:40:06.88#ibcon#end of sib2, iclass 17, count 0 2006.201.12:40:06.88#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:40:06.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:40:06.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:40:06.88#ibcon#*before write, iclass 17, count 0 2006.201.12:40:06.88#ibcon#enter sib2, iclass 17, count 0 2006.201.12:40:06.88#ibcon#flushed, iclass 17, count 0 2006.201.12:40:06.88#ibcon#about to write, iclass 17, count 0 2006.201.12:40:06.88#ibcon#wrote, iclass 17, count 0 2006.201.12:40:06.88#ibcon#about to read 3, iclass 17, count 0 2006.201.12:40:06.92#ibcon#read 3, iclass 17, count 0 2006.201.12:40:06.92#ibcon#about to read 4, iclass 17, count 0 2006.201.12:40:06.92#ibcon#read 4, iclass 17, count 0 2006.201.12:40:06.92#ibcon#about to read 5, iclass 17, count 0 2006.201.12:40:06.92#ibcon#read 5, iclass 17, count 0 2006.201.12:40:06.92#ibcon#about to read 6, iclass 17, count 0 2006.201.12:40:06.92#ibcon#read 6, iclass 17, count 0 2006.201.12:40:06.92#ibcon#end of sib2, iclass 17, count 0 2006.201.12:40:06.92#ibcon#*after write, iclass 17, count 0 2006.201.12:40:06.92#ibcon#*before return 0, iclass 17, count 0 2006.201.12:40:06.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:06.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:06.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:40:06.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:40:06.92$vck44/va=7,5 2006.201.12:40:06.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.12:40:06.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.12:40:06.92#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:06.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:06.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:06.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:06.98#ibcon#enter wrdev, iclass 19, count 2 2006.201.12:40:06.98#ibcon#first serial, iclass 19, count 2 2006.201.12:40:06.98#ibcon#enter sib2, iclass 19, count 2 2006.201.12:40:06.98#ibcon#flushed, iclass 19, count 2 2006.201.12:40:06.98#ibcon#about to write, iclass 19, count 2 2006.201.12:40:06.98#ibcon#wrote, iclass 19, count 2 2006.201.12:40:06.98#ibcon#about to read 3, iclass 19, count 2 2006.201.12:40:07.00#ibcon#read 3, iclass 19, count 2 2006.201.12:40:07.00#ibcon#about to read 4, iclass 19, count 2 2006.201.12:40:07.00#ibcon#read 4, iclass 19, count 2 2006.201.12:40:07.00#ibcon#about to read 5, iclass 19, count 2 2006.201.12:40:07.00#ibcon#read 5, iclass 19, count 2 2006.201.12:40:07.00#ibcon#about to read 6, iclass 19, count 2 2006.201.12:40:07.00#ibcon#read 6, iclass 19, count 2 2006.201.12:40:07.00#ibcon#end of sib2, iclass 19, count 2 2006.201.12:40:07.00#ibcon#*mode == 0, iclass 19, count 2 2006.201.12:40:07.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.12:40:07.00#ibcon#[25=AT07-05\r\n] 2006.201.12:40:07.00#ibcon#*before write, iclass 19, count 2 2006.201.12:40:07.00#ibcon#enter sib2, iclass 19, count 2 2006.201.12:40:07.00#ibcon#flushed, iclass 19, count 2 2006.201.12:40:07.00#ibcon#about to write, iclass 19, count 2 2006.201.12:40:07.00#ibcon#wrote, iclass 19, count 2 2006.201.12:40:07.00#ibcon#about to read 3, iclass 19, count 2 2006.201.12:40:07.03#ibcon#read 3, iclass 19, count 2 2006.201.12:40:07.03#ibcon#about to read 4, iclass 19, count 2 2006.201.12:40:07.03#ibcon#read 4, iclass 19, count 2 2006.201.12:40:07.03#ibcon#about to read 5, iclass 19, count 2 2006.201.12:40:07.03#ibcon#read 5, iclass 19, count 2 2006.201.12:40:07.03#ibcon#about to read 6, iclass 19, count 2 2006.201.12:40:07.03#ibcon#read 6, iclass 19, count 2 2006.201.12:40:07.03#ibcon#end of sib2, iclass 19, count 2 2006.201.12:40:07.03#ibcon#*after write, iclass 19, count 2 2006.201.12:40:07.03#ibcon#*before return 0, iclass 19, count 2 2006.201.12:40:07.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:07.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:07.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.12:40:07.03#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:07.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:07.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:07.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:07.15#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:40:07.15#ibcon#first serial, iclass 19, count 0 2006.201.12:40:07.15#ibcon#enter sib2, iclass 19, count 0 2006.201.12:40:07.15#ibcon#flushed, iclass 19, count 0 2006.201.12:40:07.15#ibcon#about to write, iclass 19, count 0 2006.201.12:40:07.15#ibcon#wrote, iclass 19, count 0 2006.201.12:40:07.15#ibcon#about to read 3, iclass 19, count 0 2006.201.12:40:07.17#ibcon#read 3, iclass 19, count 0 2006.201.12:40:07.17#ibcon#about to read 4, iclass 19, count 0 2006.201.12:40:07.17#ibcon#read 4, iclass 19, count 0 2006.201.12:40:07.17#ibcon#about to read 5, iclass 19, count 0 2006.201.12:40:07.17#ibcon#read 5, iclass 19, count 0 2006.201.12:40:07.17#ibcon#about to read 6, iclass 19, count 0 2006.201.12:40:07.17#ibcon#read 6, iclass 19, count 0 2006.201.12:40:07.17#ibcon#end of sib2, iclass 19, count 0 2006.201.12:40:07.17#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:40:07.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:40:07.17#ibcon#[25=USB\r\n] 2006.201.12:40:07.17#ibcon#*before write, iclass 19, count 0 2006.201.12:40:07.17#ibcon#enter sib2, iclass 19, count 0 2006.201.12:40:07.17#ibcon#flushed, iclass 19, count 0 2006.201.12:40:07.17#ibcon#about to write, iclass 19, count 0 2006.201.12:40:07.17#ibcon#wrote, iclass 19, count 0 2006.201.12:40:07.17#ibcon#about to read 3, iclass 19, count 0 2006.201.12:40:07.20#ibcon#read 3, iclass 19, count 0 2006.201.12:40:07.20#ibcon#about to read 4, iclass 19, count 0 2006.201.12:40:07.20#ibcon#read 4, iclass 19, count 0 2006.201.12:40:07.20#ibcon#about to read 5, iclass 19, count 0 2006.201.12:40:07.20#ibcon#read 5, iclass 19, count 0 2006.201.12:40:07.20#ibcon#about to read 6, iclass 19, count 0 2006.201.12:40:07.20#ibcon#read 6, iclass 19, count 0 2006.201.12:40:07.20#ibcon#end of sib2, iclass 19, count 0 2006.201.12:40:07.20#ibcon#*after write, iclass 19, count 0 2006.201.12:40:07.20#ibcon#*before return 0, iclass 19, count 0 2006.201.12:40:07.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:07.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:07.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:40:07.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:40:07.20$vck44/valo=8,884.99 2006.201.12:40:07.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.12:40:07.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.12:40:07.20#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:07.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:07.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:07.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:07.20#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:40:07.20#ibcon#first serial, iclass 21, count 0 2006.201.12:40:07.20#ibcon#enter sib2, iclass 21, count 0 2006.201.12:40:07.20#ibcon#flushed, iclass 21, count 0 2006.201.12:40:07.20#ibcon#about to write, iclass 21, count 0 2006.201.12:40:07.20#ibcon#wrote, iclass 21, count 0 2006.201.12:40:07.20#ibcon#about to read 3, iclass 21, count 0 2006.201.12:40:07.22#ibcon#read 3, iclass 21, count 0 2006.201.12:40:07.22#ibcon#about to read 4, iclass 21, count 0 2006.201.12:40:07.22#ibcon#read 4, iclass 21, count 0 2006.201.12:40:07.22#ibcon#about to read 5, iclass 21, count 0 2006.201.12:40:07.22#ibcon#read 5, iclass 21, count 0 2006.201.12:40:07.22#ibcon#about to read 6, iclass 21, count 0 2006.201.12:40:07.22#ibcon#read 6, iclass 21, count 0 2006.201.12:40:07.22#ibcon#end of sib2, iclass 21, count 0 2006.201.12:40:07.22#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:40:07.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:40:07.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:40:07.22#ibcon#*before write, iclass 21, count 0 2006.201.12:40:07.22#ibcon#enter sib2, iclass 21, count 0 2006.201.12:40:07.22#ibcon#flushed, iclass 21, count 0 2006.201.12:40:07.22#ibcon#about to write, iclass 21, count 0 2006.201.12:40:07.22#ibcon#wrote, iclass 21, count 0 2006.201.12:40:07.22#ibcon#about to read 3, iclass 21, count 0 2006.201.12:40:07.26#ibcon#read 3, iclass 21, count 0 2006.201.12:40:07.26#ibcon#about to read 4, iclass 21, count 0 2006.201.12:40:07.26#ibcon#read 4, iclass 21, count 0 2006.201.12:40:07.26#ibcon#about to read 5, iclass 21, count 0 2006.201.12:40:07.26#ibcon#read 5, iclass 21, count 0 2006.201.12:40:07.26#ibcon#about to read 6, iclass 21, count 0 2006.201.12:40:07.26#ibcon#read 6, iclass 21, count 0 2006.201.12:40:07.26#ibcon#end of sib2, iclass 21, count 0 2006.201.12:40:07.26#ibcon#*after write, iclass 21, count 0 2006.201.12:40:07.26#ibcon#*before return 0, iclass 21, count 0 2006.201.12:40:07.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:07.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:07.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:40:07.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:40:07.26$vck44/va=8,4 2006.201.12:40:07.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.12:40:07.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.12:40:07.26#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:07.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:40:07.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:40:07.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:40:07.32#ibcon#enter wrdev, iclass 23, count 2 2006.201.12:40:07.32#ibcon#first serial, iclass 23, count 2 2006.201.12:40:07.32#ibcon#enter sib2, iclass 23, count 2 2006.201.12:40:07.32#ibcon#flushed, iclass 23, count 2 2006.201.12:40:07.32#ibcon#about to write, iclass 23, count 2 2006.201.12:40:07.32#ibcon#wrote, iclass 23, count 2 2006.201.12:40:07.32#ibcon#about to read 3, iclass 23, count 2 2006.201.12:40:07.34#ibcon#read 3, iclass 23, count 2 2006.201.12:40:07.34#ibcon#about to read 4, iclass 23, count 2 2006.201.12:40:07.34#ibcon#read 4, iclass 23, count 2 2006.201.12:40:07.34#ibcon#about to read 5, iclass 23, count 2 2006.201.12:40:07.34#ibcon#read 5, iclass 23, count 2 2006.201.12:40:07.34#ibcon#about to read 6, iclass 23, count 2 2006.201.12:40:07.34#ibcon#read 6, iclass 23, count 2 2006.201.12:40:07.34#ibcon#end of sib2, iclass 23, count 2 2006.201.12:40:07.34#ibcon#*mode == 0, iclass 23, count 2 2006.201.12:40:07.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.12:40:07.34#ibcon#[25=AT08-04\r\n] 2006.201.12:40:07.34#ibcon#*before write, iclass 23, count 2 2006.201.12:40:07.34#ibcon#enter sib2, iclass 23, count 2 2006.201.12:40:07.34#ibcon#flushed, iclass 23, count 2 2006.201.12:40:07.34#ibcon#about to write, iclass 23, count 2 2006.201.12:40:07.34#ibcon#wrote, iclass 23, count 2 2006.201.12:40:07.34#ibcon#about to read 3, iclass 23, count 2 2006.201.12:40:07.37#ibcon#read 3, iclass 23, count 2 2006.201.12:40:07.37#ibcon#about to read 4, iclass 23, count 2 2006.201.12:40:07.37#ibcon#read 4, iclass 23, count 2 2006.201.12:40:07.37#ibcon#about to read 5, iclass 23, count 2 2006.201.12:40:07.37#ibcon#read 5, iclass 23, count 2 2006.201.12:40:07.37#ibcon#about to read 6, iclass 23, count 2 2006.201.12:40:07.37#ibcon#read 6, iclass 23, count 2 2006.201.12:40:07.37#ibcon#end of sib2, iclass 23, count 2 2006.201.12:40:07.37#ibcon#*after write, iclass 23, count 2 2006.201.12:40:07.37#ibcon#*before return 0, iclass 23, count 2 2006.201.12:40:07.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:40:07.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:40:07.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.12:40:07.37#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:07.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:40:07.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:40:07.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:40:07.49#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:40:07.49#ibcon#first serial, iclass 23, count 0 2006.201.12:40:07.49#ibcon#enter sib2, iclass 23, count 0 2006.201.12:40:07.49#ibcon#flushed, iclass 23, count 0 2006.201.12:40:07.49#ibcon#about to write, iclass 23, count 0 2006.201.12:40:07.49#ibcon#wrote, iclass 23, count 0 2006.201.12:40:07.49#ibcon#about to read 3, iclass 23, count 0 2006.201.12:40:07.51#ibcon#read 3, iclass 23, count 0 2006.201.12:40:07.51#ibcon#about to read 4, iclass 23, count 0 2006.201.12:40:07.51#ibcon#read 4, iclass 23, count 0 2006.201.12:40:07.51#ibcon#about to read 5, iclass 23, count 0 2006.201.12:40:07.51#ibcon#read 5, iclass 23, count 0 2006.201.12:40:07.51#ibcon#about to read 6, iclass 23, count 0 2006.201.12:40:07.51#ibcon#read 6, iclass 23, count 0 2006.201.12:40:07.51#ibcon#end of sib2, iclass 23, count 0 2006.201.12:40:07.51#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:40:07.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:40:07.51#ibcon#[25=USB\r\n] 2006.201.12:40:07.51#ibcon#*before write, iclass 23, count 0 2006.201.12:40:07.51#ibcon#enter sib2, iclass 23, count 0 2006.201.12:40:07.51#ibcon#flushed, iclass 23, count 0 2006.201.12:40:07.51#ibcon#about to write, iclass 23, count 0 2006.201.12:40:07.51#ibcon#wrote, iclass 23, count 0 2006.201.12:40:07.51#ibcon#about to read 3, iclass 23, count 0 2006.201.12:40:07.54#ibcon#read 3, iclass 23, count 0 2006.201.12:40:07.54#ibcon#about to read 4, iclass 23, count 0 2006.201.12:40:07.54#ibcon#read 4, iclass 23, count 0 2006.201.12:40:07.54#ibcon#about to read 5, iclass 23, count 0 2006.201.12:40:07.54#ibcon#read 5, iclass 23, count 0 2006.201.12:40:07.54#ibcon#about to read 6, iclass 23, count 0 2006.201.12:40:07.54#ibcon#read 6, iclass 23, count 0 2006.201.12:40:07.54#ibcon#end of sib2, iclass 23, count 0 2006.201.12:40:07.54#ibcon#*after write, iclass 23, count 0 2006.201.12:40:07.54#ibcon#*before return 0, iclass 23, count 0 2006.201.12:40:07.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:40:07.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:40:07.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:40:07.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:40:07.54$vck44/vblo=1,629.99 2006.201.12:40:07.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.12:40:07.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.12:40:07.54#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:07.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:40:07.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:40:07.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:40:07.54#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:40:07.54#ibcon#first serial, iclass 25, count 0 2006.201.12:40:07.54#ibcon#enter sib2, iclass 25, count 0 2006.201.12:40:07.54#ibcon#flushed, iclass 25, count 0 2006.201.12:40:07.54#ibcon#about to write, iclass 25, count 0 2006.201.12:40:07.54#ibcon#wrote, iclass 25, count 0 2006.201.12:40:07.54#ibcon#about to read 3, iclass 25, count 0 2006.201.12:40:07.56#ibcon#read 3, iclass 25, count 0 2006.201.12:40:07.56#ibcon#about to read 4, iclass 25, count 0 2006.201.12:40:07.56#ibcon#read 4, iclass 25, count 0 2006.201.12:40:07.56#ibcon#about to read 5, iclass 25, count 0 2006.201.12:40:07.56#ibcon#read 5, iclass 25, count 0 2006.201.12:40:07.56#ibcon#about to read 6, iclass 25, count 0 2006.201.12:40:07.56#ibcon#read 6, iclass 25, count 0 2006.201.12:40:07.56#ibcon#end of sib2, iclass 25, count 0 2006.201.12:40:07.56#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:40:07.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:40:07.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:40:07.56#ibcon#*before write, iclass 25, count 0 2006.201.12:40:07.56#ibcon#enter sib2, iclass 25, count 0 2006.201.12:40:07.56#ibcon#flushed, iclass 25, count 0 2006.201.12:40:07.56#ibcon#about to write, iclass 25, count 0 2006.201.12:40:07.56#ibcon#wrote, iclass 25, count 0 2006.201.12:40:07.56#ibcon#about to read 3, iclass 25, count 0 2006.201.12:40:07.61#ibcon#read 3, iclass 25, count 0 2006.201.12:40:07.61#ibcon#about to read 4, iclass 25, count 0 2006.201.12:40:07.61#ibcon#read 4, iclass 25, count 0 2006.201.12:40:07.61#ibcon#about to read 5, iclass 25, count 0 2006.201.12:40:07.61#ibcon#read 5, iclass 25, count 0 2006.201.12:40:07.61#ibcon#about to read 6, iclass 25, count 0 2006.201.12:40:07.61#ibcon#read 6, iclass 25, count 0 2006.201.12:40:07.61#ibcon#end of sib2, iclass 25, count 0 2006.201.12:40:07.61#ibcon#*after write, iclass 25, count 0 2006.201.12:40:07.61#ibcon#*before return 0, iclass 25, count 0 2006.201.12:40:07.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:40:07.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:40:07.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:40:07.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:40:07.61$vck44/vb=1,4 2006.201.12:40:07.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.12:40:07.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.12:40:07.61#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:07.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:40:07.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:40:07.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:40:07.61#ibcon#enter wrdev, iclass 27, count 2 2006.201.12:40:07.61#ibcon#first serial, iclass 27, count 2 2006.201.12:40:07.61#ibcon#enter sib2, iclass 27, count 2 2006.201.12:40:07.61#ibcon#flushed, iclass 27, count 2 2006.201.12:40:07.61#ibcon#about to write, iclass 27, count 2 2006.201.12:40:07.61#ibcon#wrote, iclass 27, count 2 2006.201.12:40:07.61#ibcon#about to read 3, iclass 27, count 2 2006.201.12:40:07.63#ibcon#read 3, iclass 27, count 2 2006.201.12:40:07.63#ibcon#about to read 4, iclass 27, count 2 2006.201.12:40:07.63#ibcon#read 4, iclass 27, count 2 2006.201.12:40:07.63#ibcon#about to read 5, iclass 27, count 2 2006.201.12:40:07.63#ibcon#read 5, iclass 27, count 2 2006.201.12:40:07.63#ibcon#about to read 6, iclass 27, count 2 2006.201.12:40:07.63#ibcon#read 6, iclass 27, count 2 2006.201.12:40:07.63#ibcon#end of sib2, iclass 27, count 2 2006.201.12:40:07.63#ibcon#*mode == 0, iclass 27, count 2 2006.201.12:40:07.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.12:40:07.63#ibcon#[27=AT01-04\r\n] 2006.201.12:40:07.63#ibcon#*before write, iclass 27, count 2 2006.201.12:40:07.63#ibcon#enter sib2, iclass 27, count 2 2006.201.12:40:07.63#ibcon#flushed, iclass 27, count 2 2006.201.12:40:07.63#ibcon#about to write, iclass 27, count 2 2006.201.12:40:07.63#ibcon#wrote, iclass 27, count 2 2006.201.12:40:07.63#ibcon#about to read 3, iclass 27, count 2 2006.201.12:40:07.66#ibcon#read 3, iclass 27, count 2 2006.201.12:40:07.66#ibcon#about to read 4, iclass 27, count 2 2006.201.12:40:07.66#ibcon#read 4, iclass 27, count 2 2006.201.12:40:07.66#ibcon#about to read 5, iclass 27, count 2 2006.201.12:40:07.66#ibcon#read 5, iclass 27, count 2 2006.201.12:40:07.66#ibcon#about to read 6, iclass 27, count 2 2006.201.12:40:07.66#ibcon#read 6, iclass 27, count 2 2006.201.12:40:07.66#ibcon#end of sib2, iclass 27, count 2 2006.201.12:40:07.66#ibcon#*after write, iclass 27, count 2 2006.201.12:40:07.66#ibcon#*before return 0, iclass 27, count 2 2006.201.12:40:07.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:40:07.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:40:07.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.12:40:07.66#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:07.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:40:07.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:40:07.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:40:07.78#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:40:07.78#ibcon#first serial, iclass 27, count 0 2006.201.12:40:07.78#ibcon#enter sib2, iclass 27, count 0 2006.201.12:40:07.78#ibcon#flushed, iclass 27, count 0 2006.201.12:40:07.78#ibcon#about to write, iclass 27, count 0 2006.201.12:40:07.78#ibcon#wrote, iclass 27, count 0 2006.201.12:40:07.78#ibcon#about to read 3, iclass 27, count 0 2006.201.12:40:07.80#ibcon#read 3, iclass 27, count 0 2006.201.12:40:07.80#ibcon#about to read 4, iclass 27, count 0 2006.201.12:40:07.80#ibcon#read 4, iclass 27, count 0 2006.201.12:40:07.80#ibcon#about to read 5, iclass 27, count 0 2006.201.12:40:07.80#ibcon#read 5, iclass 27, count 0 2006.201.12:40:07.80#ibcon#about to read 6, iclass 27, count 0 2006.201.12:40:07.80#ibcon#read 6, iclass 27, count 0 2006.201.12:40:07.80#ibcon#end of sib2, iclass 27, count 0 2006.201.12:40:07.80#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:40:07.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:40:07.80#ibcon#[27=USB\r\n] 2006.201.12:40:07.80#ibcon#*before write, iclass 27, count 0 2006.201.12:40:07.80#ibcon#enter sib2, iclass 27, count 0 2006.201.12:40:07.80#ibcon#flushed, iclass 27, count 0 2006.201.12:40:07.80#ibcon#about to write, iclass 27, count 0 2006.201.12:40:07.80#ibcon#wrote, iclass 27, count 0 2006.201.12:40:07.80#ibcon#about to read 3, iclass 27, count 0 2006.201.12:40:07.83#ibcon#read 3, iclass 27, count 0 2006.201.12:40:07.83#ibcon#about to read 4, iclass 27, count 0 2006.201.12:40:07.83#ibcon#read 4, iclass 27, count 0 2006.201.12:40:07.83#ibcon#about to read 5, iclass 27, count 0 2006.201.12:40:07.83#ibcon#read 5, iclass 27, count 0 2006.201.12:40:07.83#ibcon#about to read 6, iclass 27, count 0 2006.201.12:40:07.83#ibcon#read 6, iclass 27, count 0 2006.201.12:40:07.83#ibcon#end of sib2, iclass 27, count 0 2006.201.12:40:07.83#ibcon#*after write, iclass 27, count 0 2006.201.12:40:07.83#ibcon#*before return 0, iclass 27, count 0 2006.201.12:40:07.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:40:07.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:40:07.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:40:07.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:40:07.83$vck44/vblo=2,634.99 2006.201.12:40:07.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.12:40:07.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.12:40:07.83#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:07.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:07.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:07.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:07.83#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:40:07.83#ibcon#first serial, iclass 29, count 0 2006.201.12:40:07.83#ibcon#enter sib2, iclass 29, count 0 2006.201.12:40:07.83#ibcon#flushed, iclass 29, count 0 2006.201.12:40:07.83#ibcon#about to write, iclass 29, count 0 2006.201.12:40:07.83#ibcon#wrote, iclass 29, count 0 2006.201.12:40:07.83#ibcon#about to read 3, iclass 29, count 0 2006.201.12:40:07.85#ibcon#read 3, iclass 29, count 0 2006.201.12:40:07.85#ibcon#about to read 4, iclass 29, count 0 2006.201.12:40:07.85#ibcon#read 4, iclass 29, count 0 2006.201.12:40:07.85#ibcon#about to read 5, iclass 29, count 0 2006.201.12:40:07.85#ibcon#read 5, iclass 29, count 0 2006.201.12:40:07.85#ibcon#about to read 6, iclass 29, count 0 2006.201.12:40:07.85#ibcon#read 6, iclass 29, count 0 2006.201.12:40:07.85#ibcon#end of sib2, iclass 29, count 0 2006.201.12:40:07.85#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:40:07.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:40:07.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:40:07.85#ibcon#*before write, iclass 29, count 0 2006.201.12:40:07.85#ibcon#enter sib2, iclass 29, count 0 2006.201.12:40:07.85#ibcon#flushed, iclass 29, count 0 2006.201.12:40:07.85#ibcon#about to write, iclass 29, count 0 2006.201.12:40:07.85#ibcon#wrote, iclass 29, count 0 2006.201.12:40:07.85#ibcon#about to read 3, iclass 29, count 0 2006.201.12:40:07.89#ibcon#read 3, iclass 29, count 0 2006.201.12:40:07.89#ibcon#about to read 4, iclass 29, count 0 2006.201.12:40:07.89#ibcon#read 4, iclass 29, count 0 2006.201.12:40:07.89#ibcon#about to read 5, iclass 29, count 0 2006.201.12:40:07.89#ibcon#read 5, iclass 29, count 0 2006.201.12:40:07.89#ibcon#about to read 6, iclass 29, count 0 2006.201.12:40:07.89#ibcon#read 6, iclass 29, count 0 2006.201.12:40:07.89#ibcon#end of sib2, iclass 29, count 0 2006.201.12:40:07.89#ibcon#*after write, iclass 29, count 0 2006.201.12:40:07.89#ibcon#*before return 0, iclass 29, count 0 2006.201.12:40:07.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:07.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:40:07.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:40:07.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:40:07.89$vck44/vb=2,5 2006.201.12:40:07.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.12:40:07.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.12:40:07.89#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:07.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:07.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:07.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:07.95#ibcon#enter wrdev, iclass 31, count 2 2006.201.12:40:07.95#ibcon#first serial, iclass 31, count 2 2006.201.12:40:07.95#ibcon#enter sib2, iclass 31, count 2 2006.201.12:40:07.95#ibcon#flushed, iclass 31, count 2 2006.201.12:40:07.95#ibcon#about to write, iclass 31, count 2 2006.201.12:40:07.95#ibcon#wrote, iclass 31, count 2 2006.201.12:40:07.95#ibcon#about to read 3, iclass 31, count 2 2006.201.12:40:07.97#ibcon#read 3, iclass 31, count 2 2006.201.12:40:07.97#ibcon#about to read 4, iclass 31, count 2 2006.201.12:40:07.97#ibcon#read 4, iclass 31, count 2 2006.201.12:40:07.97#ibcon#about to read 5, iclass 31, count 2 2006.201.12:40:07.97#ibcon#read 5, iclass 31, count 2 2006.201.12:40:07.97#ibcon#about to read 6, iclass 31, count 2 2006.201.12:40:07.97#ibcon#read 6, iclass 31, count 2 2006.201.12:40:07.97#ibcon#end of sib2, iclass 31, count 2 2006.201.12:40:07.97#ibcon#*mode == 0, iclass 31, count 2 2006.201.12:40:07.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.12:40:07.97#ibcon#[27=AT02-05\r\n] 2006.201.12:40:07.97#ibcon#*before write, iclass 31, count 2 2006.201.12:40:07.97#ibcon#enter sib2, iclass 31, count 2 2006.201.12:40:07.97#ibcon#flushed, iclass 31, count 2 2006.201.12:40:07.97#ibcon#about to write, iclass 31, count 2 2006.201.12:40:07.97#ibcon#wrote, iclass 31, count 2 2006.201.12:40:07.97#ibcon#about to read 3, iclass 31, count 2 2006.201.12:40:08.00#ibcon#read 3, iclass 31, count 2 2006.201.12:40:08.00#ibcon#about to read 4, iclass 31, count 2 2006.201.12:40:08.00#ibcon#read 4, iclass 31, count 2 2006.201.12:40:08.00#ibcon#about to read 5, iclass 31, count 2 2006.201.12:40:08.00#ibcon#read 5, iclass 31, count 2 2006.201.12:40:08.00#ibcon#about to read 6, iclass 31, count 2 2006.201.12:40:08.00#ibcon#read 6, iclass 31, count 2 2006.201.12:40:08.00#ibcon#end of sib2, iclass 31, count 2 2006.201.12:40:08.00#ibcon#*after write, iclass 31, count 2 2006.201.12:40:08.00#ibcon#*before return 0, iclass 31, count 2 2006.201.12:40:08.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:08.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:40:08.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.12:40:08.00#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:08.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:08.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:08.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:08.12#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:40:08.12#ibcon#first serial, iclass 31, count 0 2006.201.12:40:08.12#ibcon#enter sib2, iclass 31, count 0 2006.201.12:40:08.12#ibcon#flushed, iclass 31, count 0 2006.201.12:40:08.12#ibcon#about to write, iclass 31, count 0 2006.201.12:40:08.12#ibcon#wrote, iclass 31, count 0 2006.201.12:40:08.12#ibcon#about to read 3, iclass 31, count 0 2006.201.12:40:08.14#ibcon#read 3, iclass 31, count 0 2006.201.12:40:08.14#ibcon#about to read 4, iclass 31, count 0 2006.201.12:40:08.14#ibcon#read 4, iclass 31, count 0 2006.201.12:40:08.14#ibcon#about to read 5, iclass 31, count 0 2006.201.12:40:08.14#ibcon#read 5, iclass 31, count 0 2006.201.12:40:08.14#ibcon#about to read 6, iclass 31, count 0 2006.201.12:40:08.14#ibcon#read 6, iclass 31, count 0 2006.201.12:40:08.14#ibcon#end of sib2, iclass 31, count 0 2006.201.12:40:08.14#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:40:08.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:40:08.14#ibcon#[27=USB\r\n] 2006.201.12:40:08.14#ibcon#*before write, iclass 31, count 0 2006.201.12:40:08.14#ibcon#enter sib2, iclass 31, count 0 2006.201.12:40:08.14#ibcon#flushed, iclass 31, count 0 2006.201.12:40:08.14#ibcon#about to write, iclass 31, count 0 2006.201.12:40:08.14#ibcon#wrote, iclass 31, count 0 2006.201.12:40:08.14#ibcon#about to read 3, iclass 31, count 0 2006.201.12:40:08.17#ibcon#read 3, iclass 31, count 0 2006.201.12:40:08.17#ibcon#about to read 4, iclass 31, count 0 2006.201.12:40:08.17#ibcon#read 4, iclass 31, count 0 2006.201.12:40:08.17#ibcon#about to read 5, iclass 31, count 0 2006.201.12:40:08.17#ibcon#read 5, iclass 31, count 0 2006.201.12:40:08.17#ibcon#about to read 6, iclass 31, count 0 2006.201.12:40:08.17#ibcon#read 6, iclass 31, count 0 2006.201.12:40:08.17#ibcon#end of sib2, iclass 31, count 0 2006.201.12:40:08.17#ibcon#*after write, iclass 31, count 0 2006.201.12:40:08.17#ibcon#*before return 0, iclass 31, count 0 2006.201.12:40:08.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:08.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:40:08.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:40:08.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:40:08.17$vck44/vblo=3,649.99 2006.201.12:40:08.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.12:40:08.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.12:40:08.17#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:08.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:08.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:08.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:08.17#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:40:08.17#ibcon#first serial, iclass 33, count 0 2006.201.12:40:08.17#ibcon#enter sib2, iclass 33, count 0 2006.201.12:40:08.17#ibcon#flushed, iclass 33, count 0 2006.201.12:40:08.17#ibcon#about to write, iclass 33, count 0 2006.201.12:40:08.17#ibcon#wrote, iclass 33, count 0 2006.201.12:40:08.17#ibcon#about to read 3, iclass 33, count 0 2006.201.12:40:08.19#ibcon#read 3, iclass 33, count 0 2006.201.12:40:08.19#ibcon#about to read 4, iclass 33, count 0 2006.201.12:40:08.19#ibcon#read 4, iclass 33, count 0 2006.201.12:40:08.19#ibcon#about to read 5, iclass 33, count 0 2006.201.12:40:08.19#ibcon#read 5, iclass 33, count 0 2006.201.12:40:08.19#ibcon#about to read 6, iclass 33, count 0 2006.201.12:40:08.19#ibcon#read 6, iclass 33, count 0 2006.201.12:40:08.19#ibcon#end of sib2, iclass 33, count 0 2006.201.12:40:08.19#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:40:08.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:40:08.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:40:08.19#ibcon#*before write, iclass 33, count 0 2006.201.12:40:08.19#ibcon#enter sib2, iclass 33, count 0 2006.201.12:40:08.19#ibcon#flushed, iclass 33, count 0 2006.201.12:40:08.19#ibcon#about to write, iclass 33, count 0 2006.201.12:40:08.19#ibcon#wrote, iclass 33, count 0 2006.201.12:40:08.19#ibcon#about to read 3, iclass 33, count 0 2006.201.12:40:08.23#ibcon#read 3, iclass 33, count 0 2006.201.12:40:08.23#ibcon#about to read 4, iclass 33, count 0 2006.201.12:40:08.23#ibcon#read 4, iclass 33, count 0 2006.201.12:40:08.23#ibcon#about to read 5, iclass 33, count 0 2006.201.12:40:08.23#ibcon#read 5, iclass 33, count 0 2006.201.12:40:08.23#ibcon#about to read 6, iclass 33, count 0 2006.201.12:40:08.23#ibcon#read 6, iclass 33, count 0 2006.201.12:40:08.23#ibcon#end of sib2, iclass 33, count 0 2006.201.12:40:08.23#ibcon#*after write, iclass 33, count 0 2006.201.12:40:08.23#ibcon#*before return 0, iclass 33, count 0 2006.201.12:40:08.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:08.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:40:08.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:40:08.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:40:08.23$vck44/vb=3,4 2006.201.12:40:08.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.12:40:08.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.12:40:08.23#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:08.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:08.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:08.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:08.29#ibcon#enter wrdev, iclass 35, count 2 2006.201.12:40:08.29#ibcon#first serial, iclass 35, count 2 2006.201.12:40:08.29#ibcon#enter sib2, iclass 35, count 2 2006.201.12:40:08.29#ibcon#flushed, iclass 35, count 2 2006.201.12:40:08.29#ibcon#about to write, iclass 35, count 2 2006.201.12:40:08.29#ibcon#wrote, iclass 35, count 2 2006.201.12:40:08.29#ibcon#about to read 3, iclass 35, count 2 2006.201.12:40:08.31#ibcon#read 3, iclass 35, count 2 2006.201.12:40:08.31#ibcon#about to read 4, iclass 35, count 2 2006.201.12:40:08.31#ibcon#read 4, iclass 35, count 2 2006.201.12:40:08.31#ibcon#about to read 5, iclass 35, count 2 2006.201.12:40:08.31#ibcon#read 5, iclass 35, count 2 2006.201.12:40:08.31#ibcon#about to read 6, iclass 35, count 2 2006.201.12:40:08.31#ibcon#read 6, iclass 35, count 2 2006.201.12:40:08.31#ibcon#end of sib2, iclass 35, count 2 2006.201.12:40:08.31#ibcon#*mode == 0, iclass 35, count 2 2006.201.12:40:08.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.12:40:08.31#ibcon#[27=AT03-04\r\n] 2006.201.12:40:08.31#ibcon#*before write, iclass 35, count 2 2006.201.12:40:08.31#ibcon#enter sib2, iclass 35, count 2 2006.201.12:40:08.31#ibcon#flushed, iclass 35, count 2 2006.201.12:40:08.31#ibcon#about to write, iclass 35, count 2 2006.201.12:40:08.31#ibcon#wrote, iclass 35, count 2 2006.201.12:40:08.31#ibcon#about to read 3, iclass 35, count 2 2006.201.12:40:08.34#ibcon#read 3, iclass 35, count 2 2006.201.12:40:08.34#ibcon#about to read 4, iclass 35, count 2 2006.201.12:40:08.34#ibcon#read 4, iclass 35, count 2 2006.201.12:40:08.34#ibcon#about to read 5, iclass 35, count 2 2006.201.12:40:08.34#ibcon#read 5, iclass 35, count 2 2006.201.12:40:08.34#ibcon#about to read 6, iclass 35, count 2 2006.201.12:40:08.34#ibcon#read 6, iclass 35, count 2 2006.201.12:40:08.34#ibcon#end of sib2, iclass 35, count 2 2006.201.12:40:08.34#ibcon#*after write, iclass 35, count 2 2006.201.12:40:08.34#ibcon#*before return 0, iclass 35, count 2 2006.201.12:40:08.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:08.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:40:08.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.12:40:08.34#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:08.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:08.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:08.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:08.46#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:40:08.46#ibcon#first serial, iclass 35, count 0 2006.201.12:40:08.46#ibcon#enter sib2, iclass 35, count 0 2006.201.12:40:08.46#ibcon#flushed, iclass 35, count 0 2006.201.12:40:08.46#ibcon#about to write, iclass 35, count 0 2006.201.12:40:08.46#ibcon#wrote, iclass 35, count 0 2006.201.12:40:08.46#ibcon#about to read 3, iclass 35, count 0 2006.201.12:40:08.48#ibcon#read 3, iclass 35, count 0 2006.201.12:40:08.48#ibcon#about to read 4, iclass 35, count 0 2006.201.12:40:08.48#ibcon#read 4, iclass 35, count 0 2006.201.12:40:08.48#ibcon#about to read 5, iclass 35, count 0 2006.201.12:40:08.48#ibcon#read 5, iclass 35, count 0 2006.201.12:40:08.48#ibcon#about to read 6, iclass 35, count 0 2006.201.12:40:08.48#ibcon#read 6, iclass 35, count 0 2006.201.12:40:08.48#ibcon#end of sib2, iclass 35, count 0 2006.201.12:40:08.48#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:40:08.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:40:08.48#ibcon#[27=USB\r\n] 2006.201.12:40:08.48#ibcon#*before write, iclass 35, count 0 2006.201.12:40:08.48#ibcon#enter sib2, iclass 35, count 0 2006.201.12:40:08.48#ibcon#flushed, iclass 35, count 0 2006.201.12:40:08.48#ibcon#about to write, iclass 35, count 0 2006.201.12:40:08.48#ibcon#wrote, iclass 35, count 0 2006.201.12:40:08.48#ibcon#about to read 3, iclass 35, count 0 2006.201.12:40:08.51#ibcon#read 3, iclass 35, count 0 2006.201.12:40:08.51#ibcon#about to read 4, iclass 35, count 0 2006.201.12:40:08.51#ibcon#read 4, iclass 35, count 0 2006.201.12:40:08.51#ibcon#about to read 5, iclass 35, count 0 2006.201.12:40:08.51#ibcon#read 5, iclass 35, count 0 2006.201.12:40:08.51#ibcon#about to read 6, iclass 35, count 0 2006.201.12:40:08.51#ibcon#read 6, iclass 35, count 0 2006.201.12:40:08.51#ibcon#end of sib2, iclass 35, count 0 2006.201.12:40:08.51#ibcon#*after write, iclass 35, count 0 2006.201.12:40:08.51#ibcon#*before return 0, iclass 35, count 0 2006.201.12:40:08.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:08.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:40:08.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:40:08.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:40:08.51$vck44/vblo=4,679.99 2006.201.12:40:08.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.12:40:08.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.12:40:08.51#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:08.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:08.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:08.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:08.51#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:40:08.51#ibcon#first serial, iclass 37, count 0 2006.201.12:40:08.51#ibcon#enter sib2, iclass 37, count 0 2006.201.12:40:08.51#ibcon#flushed, iclass 37, count 0 2006.201.12:40:08.51#ibcon#about to write, iclass 37, count 0 2006.201.12:40:08.51#ibcon#wrote, iclass 37, count 0 2006.201.12:40:08.51#ibcon#about to read 3, iclass 37, count 0 2006.201.12:40:08.53#ibcon#read 3, iclass 37, count 0 2006.201.12:40:08.53#ibcon#about to read 4, iclass 37, count 0 2006.201.12:40:08.53#ibcon#read 4, iclass 37, count 0 2006.201.12:40:08.53#ibcon#about to read 5, iclass 37, count 0 2006.201.12:40:08.53#ibcon#read 5, iclass 37, count 0 2006.201.12:40:08.53#ibcon#about to read 6, iclass 37, count 0 2006.201.12:40:08.53#ibcon#read 6, iclass 37, count 0 2006.201.12:40:08.53#ibcon#end of sib2, iclass 37, count 0 2006.201.12:40:08.53#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:40:08.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:40:08.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:40:08.53#ibcon#*before write, iclass 37, count 0 2006.201.12:40:08.53#ibcon#enter sib2, iclass 37, count 0 2006.201.12:40:08.53#ibcon#flushed, iclass 37, count 0 2006.201.12:40:08.53#ibcon#about to write, iclass 37, count 0 2006.201.12:40:08.53#ibcon#wrote, iclass 37, count 0 2006.201.12:40:08.53#ibcon#about to read 3, iclass 37, count 0 2006.201.12:40:08.57#ibcon#read 3, iclass 37, count 0 2006.201.12:40:08.57#ibcon#about to read 4, iclass 37, count 0 2006.201.12:40:08.57#ibcon#read 4, iclass 37, count 0 2006.201.12:40:08.57#ibcon#about to read 5, iclass 37, count 0 2006.201.12:40:08.57#ibcon#read 5, iclass 37, count 0 2006.201.12:40:08.57#ibcon#about to read 6, iclass 37, count 0 2006.201.12:40:08.57#ibcon#read 6, iclass 37, count 0 2006.201.12:40:08.57#ibcon#end of sib2, iclass 37, count 0 2006.201.12:40:08.57#ibcon#*after write, iclass 37, count 0 2006.201.12:40:08.57#ibcon#*before return 0, iclass 37, count 0 2006.201.12:40:08.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:08.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:40:08.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:40:08.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:40:08.57$vck44/vb=4,5 2006.201.12:40:08.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.12:40:08.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.12:40:08.57#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:08.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:08.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:08.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:08.63#ibcon#enter wrdev, iclass 39, count 2 2006.201.12:40:08.63#ibcon#first serial, iclass 39, count 2 2006.201.12:40:08.63#ibcon#enter sib2, iclass 39, count 2 2006.201.12:40:08.63#ibcon#flushed, iclass 39, count 2 2006.201.12:40:08.63#ibcon#about to write, iclass 39, count 2 2006.201.12:40:08.63#ibcon#wrote, iclass 39, count 2 2006.201.12:40:08.63#ibcon#about to read 3, iclass 39, count 2 2006.201.12:40:08.65#ibcon#read 3, iclass 39, count 2 2006.201.12:40:08.65#ibcon#about to read 4, iclass 39, count 2 2006.201.12:40:08.65#ibcon#read 4, iclass 39, count 2 2006.201.12:40:08.65#ibcon#about to read 5, iclass 39, count 2 2006.201.12:40:08.65#ibcon#read 5, iclass 39, count 2 2006.201.12:40:08.65#ibcon#about to read 6, iclass 39, count 2 2006.201.12:40:08.65#ibcon#read 6, iclass 39, count 2 2006.201.12:40:08.65#ibcon#end of sib2, iclass 39, count 2 2006.201.12:40:08.65#ibcon#*mode == 0, iclass 39, count 2 2006.201.12:40:08.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.12:40:08.65#ibcon#[27=AT04-05\r\n] 2006.201.12:40:08.65#ibcon#*before write, iclass 39, count 2 2006.201.12:40:08.65#ibcon#enter sib2, iclass 39, count 2 2006.201.12:40:08.65#ibcon#flushed, iclass 39, count 2 2006.201.12:40:08.65#ibcon#about to write, iclass 39, count 2 2006.201.12:40:08.65#ibcon#wrote, iclass 39, count 2 2006.201.12:40:08.65#ibcon#about to read 3, iclass 39, count 2 2006.201.12:40:08.68#ibcon#read 3, iclass 39, count 2 2006.201.12:40:08.68#ibcon#about to read 4, iclass 39, count 2 2006.201.12:40:08.68#ibcon#read 4, iclass 39, count 2 2006.201.12:40:08.68#ibcon#about to read 5, iclass 39, count 2 2006.201.12:40:08.68#ibcon#read 5, iclass 39, count 2 2006.201.12:40:08.68#ibcon#about to read 6, iclass 39, count 2 2006.201.12:40:08.68#ibcon#read 6, iclass 39, count 2 2006.201.12:40:08.68#ibcon#end of sib2, iclass 39, count 2 2006.201.12:40:08.68#ibcon#*after write, iclass 39, count 2 2006.201.12:40:08.68#ibcon#*before return 0, iclass 39, count 2 2006.201.12:40:08.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:08.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:40:08.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.12:40:08.68#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:08.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:08.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:08.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:08.80#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:40:08.80#ibcon#first serial, iclass 39, count 0 2006.201.12:40:08.80#ibcon#enter sib2, iclass 39, count 0 2006.201.12:40:08.80#ibcon#flushed, iclass 39, count 0 2006.201.12:40:08.80#ibcon#about to write, iclass 39, count 0 2006.201.12:40:08.80#ibcon#wrote, iclass 39, count 0 2006.201.12:40:08.80#ibcon#about to read 3, iclass 39, count 0 2006.201.12:40:08.82#ibcon#read 3, iclass 39, count 0 2006.201.12:40:08.82#ibcon#about to read 4, iclass 39, count 0 2006.201.12:40:08.82#ibcon#read 4, iclass 39, count 0 2006.201.12:40:08.82#ibcon#about to read 5, iclass 39, count 0 2006.201.12:40:08.82#ibcon#read 5, iclass 39, count 0 2006.201.12:40:08.82#ibcon#about to read 6, iclass 39, count 0 2006.201.12:40:08.82#ibcon#read 6, iclass 39, count 0 2006.201.12:40:08.82#ibcon#end of sib2, iclass 39, count 0 2006.201.12:40:08.82#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:40:08.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:40:08.82#ibcon#[27=USB\r\n] 2006.201.12:40:08.82#ibcon#*before write, iclass 39, count 0 2006.201.12:40:08.82#ibcon#enter sib2, iclass 39, count 0 2006.201.12:40:08.82#ibcon#flushed, iclass 39, count 0 2006.201.12:40:08.82#ibcon#about to write, iclass 39, count 0 2006.201.12:40:08.82#ibcon#wrote, iclass 39, count 0 2006.201.12:40:08.82#ibcon#about to read 3, iclass 39, count 0 2006.201.12:40:08.85#ibcon#read 3, iclass 39, count 0 2006.201.12:40:08.85#ibcon#about to read 4, iclass 39, count 0 2006.201.12:40:08.85#ibcon#read 4, iclass 39, count 0 2006.201.12:40:08.85#ibcon#about to read 5, iclass 39, count 0 2006.201.12:40:08.85#ibcon#read 5, iclass 39, count 0 2006.201.12:40:08.85#ibcon#about to read 6, iclass 39, count 0 2006.201.12:40:08.85#ibcon#read 6, iclass 39, count 0 2006.201.12:40:08.85#ibcon#end of sib2, iclass 39, count 0 2006.201.12:40:08.85#ibcon#*after write, iclass 39, count 0 2006.201.12:40:08.85#ibcon#*before return 0, iclass 39, count 0 2006.201.12:40:08.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:08.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:40:08.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:40:08.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:40:08.85$vck44/vblo=5,709.99 2006.201.12:40:08.85#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.12:40:08.85#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.12:40:08.85#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:08.85#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:08.85#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:08.85#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:08.85#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:40:08.85#ibcon#first serial, iclass 2, count 0 2006.201.12:40:08.85#ibcon#enter sib2, iclass 2, count 0 2006.201.12:40:08.85#ibcon#flushed, iclass 2, count 0 2006.201.12:40:08.85#ibcon#about to write, iclass 2, count 0 2006.201.12:40:08.85#ibcon#wrote, iclass 2, count 0 2006.201.12:40:08.85#ibcon#about to read 3, iclass 2, count 0 2006.201.12:40:08.87#ibcon#read 3, iclass 2, count 0 2006.201.12:40:08.87#ibcon#about to read 4, iclass 2, count 0 2006.201.12:40:08.87#ibcon#read 4, iclass 2, count 0 2006.201.12:40:08.87#ibcon#about to read 5, iclass 2, count 0 2006.201.12:40:08.87#ibcon#read 5, iclass 2, count 0 2006.201.12:40:08.87#ibcon#about to read 6, iclass 2, count 0 2006.201.12:40:08.87#ibcon#read 6, iclass 2, count 0 2006.201.12:40:08.87#ibcon#end of sib2, iclass 2, count 0 2006.201.12:40:08.87#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:40:08.87#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:40:08.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:40:08.87#ibcon#*before write, iclass 2, count 0 2006.201.12:40:08.87#ibcon#enter sib2, iclass 2, count 0 2006.201.12:40:08.87#ibcon#flushed, iclass 2, count 0 2006.201.12:40:08.87#ibcon#about to write, iclass 2, count 0 2006.201.12:40:08.87#ibcon#wrote, iclass 2, count 0 2006.201.12:40:08.87#ibcon#about to read 3, iclass 2, count 0 2006.201.12:40:08.91#ibcon#read 3, iclass 2, count 0 2006.201.12:40:08.91#ibcon#about to read 4, iclass 2, count 0 2006.201.12:40:08.91#ibcon#read 4, iclass 2, count 0 2006.201.12:40:08.91#ibcon#about to read 5, iclass 2, count 0 2006.201.12:40:08.91#ibcon#read 5, iclass 2, count 0 2006.201.12:40:08.91#ibcon#about to read 6, iclass 2, count 0 2006.201.12:40:08.91#ibcon#read 6, iclass 2, count 0 2006.201.12:40:08.91#ibcon#end of sib2, iclass 2, count 0 2006.201.12:40:08.91#ibcon#*after write, iclass 2, count 0 2006.201.12:40:08.91#ibcon#*before return 0, iclass 2, count 0 2006.201.12:40:08.91#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:08.91#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:40:08.91#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:40:08.91#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:40:08.91$vck44/vb=5,4 2006.201.12:40:08.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.12:40:08.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.12:40:08.91#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:08.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:08.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:08.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:08.97#ibcon#enter wrdev, iclass 5, count 2 2006.201.12:40:08.97#ibcon#first serial, iclass 5, count 2 2006.201.12:40:08.97#ibcon#enter sib2, iclass 5, count 2 2006.201.12:40:08.97#ibcon#flushed, iclass 5, count 2 2006.201.12:40:08.97#ibcon#about to write, iclass 5, count 2 2006.201.12:40:08.97#ibcon#wrote, iclass 5, count 2 2006.201.12:40:08.97#ibcon#about to read 3, iclass 5, count 2 2006.201.12:40:08.99#ibcon#read 3, iclass 5, count 2 2006.201.12:40:08.99#ibcon#about to read 4, iclass 5, count 2 2006.201.12:40:08.99#ibcon#read 4, iclass 5, count 2 2006.201.12:40:08.99#ibcon#about to read 5, iclass 5, count 2 2006.201.12:40:08.99#ibcon#read 5, iclass 5, count 2 2006.201.12:40:08.99#ibcon#about to read 6, iclass 5, count 2 2006.201.12:40:08.99#ibcon#read 6, iclass 5, count 2 2006.201.12:40:08.99#ibcon#end of sib2, iclass 5, count 2 2006.201.12:40:08.99#ibcon#*mode == 0, iclass 5, count 2 2006.201.12:40:08.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.12:40:08.99#ibcon#[27=AT05-04\r\n] 2006.201.12:40:08.99#ibcon#*before write, iclass 5, count 2 2006.201.12:40:08.99#ibcon#enter sib2, iclass 5, count 2 2006.201.12:40:08.99#ibcon#flushed, iclass 5, count 2 2006.201.12:40:08.99#ibcon#about to write, iclass 5, count 2 2006.201.12:40:08.99#ibcon#wrote, iclass 5, count 2 2006.201.12:40:08.99#ibcon#about to read 3, iclass 5, count 2 2006.201.12:40:09.02#ibcon#read 3, iclass 5, count 2 2006.201.12:40:09.02#ibcon#about to read 4, iclass 5, count 2 2006.201.12:40:09.02#ibcon#read 4, iclass 5, count 2 2006.201.12:40:09.02#ibcon#about to read 5, iclass 5, count 2 2006.201.12:40:09.02#ibcon#read 5, iclass 5, count 2 2006.201.12:40:09.02#ibcon#about to read 6, iclass 5, count 2 2006.201.12:40:09.02#ibcon#read 6, iclass 5, count 2 2006.201.12:40:09.02#ibcon#end of sib2, iclass 5, count 2 2006.201.12:40:09.02#ibcon#*after write, iclass 5, count 2 2006.201.12:40:09.02#ibcon#*before return 0, iclass 5, count 2 2006.201.12:40:09.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:09.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:40:09.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.12:40:09.02#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:09.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:09.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:09.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:09.14#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:40:09.14#ibcon#first serial, iclass 5, count 0 2006.201.12:40:09.14#ibcon#enter sib2, iclass 5, count 0 2006.201.12:40:09.14#ibcon#flushed, iclass 5, count 0 2006.201.12:40:09.14#ibcon#about to write, iclass 5, count 0 2006.201.12:40:09.14#ibcon#wrote, iclass 5, count 0 2006.201.12:40:09.14#ibcon#about to read 3, iclass 5, count 0 2006.201.12:40:09.16#ibcon#read 3, iclass 5, count 0 2006.201.12:40:09.16#ibcon#about to read 4, iclass 5, count 0 2006.201.12:40:09.16#ibcon#read 4, iclass 5, count 0 2006.201.12:40:09.16#ibcon#about to read 5, iclass 5, count 0 2006.201.12:40:09.16#ibcon#read 5, iclass 5, count 0 2006.201.12:40:09.16#ibcon#about to read 6, iclass 5, count 0 2006.201.12:40:09.16#ibcon#read 6, iclass 5, count 0 2006.201.12:40:09.16#ibcon#end of sib2, iclass 5, count 0 2006.201.12:40:09.16#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:40:09.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:40:09.16#ibcon#[27=USB\r\n] 2006.201.12:40:09.16#ibcon#*before write, iclass 5, count 0 2006.201.12:40:09.16#ibcon#enter sib2, iclass 5, count 0 2006.201.12:40:09.16#ibcon#flushed, iclass 5, count 0 2006.201.12:40:09.16#ibcon#about to write, iclass 5, count 0 2006.201.12:40:09.16#ibcon#wrote, iclass 5, count 0 2006.201.12:40:09.16#ibcon#about to read 3, iclass 5, count 0 2006.201.12:40:09.19#ibcon#read 3, iclass 5, count 0 2006.201.12:40:09.19#ibcon#about to read 4, iclass 5, count 0 2006.201.12:40:09.19#ibcon#read 4, iclass 5, count 0 2006.201.12:40:09.19#ibcon#about to read 5, iclass 5, count 0 2006.201.12:40:09.19#ibcon#read 5, iclass 5, count 0 2006.201.12:40:09.19#ibcon#about to read 6, iclass 5, count 0 2006.201.12:40:09.19#ibcon#read 6, iclass 5, count 0 2006.201.12:40:09.19#ibcon#end of sib2, iclass 5, count 0 2006.201.12:40:09.19#ibcon#*after write, iclass 5, count 0 2006.201.12:40:09.19#ibcon#*before return 0, iclass 5, count 0 2006.201.12:40:09.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:09.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:40:09.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:40:09.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:40:09.19$vck44/vblo=6,719.99 2006.201.12:40:09.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.12:40:09.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.12:40:09.19#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:09.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:09.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:09.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:09.19#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:40:09.19#ibcon#first serial, iclass 7, count 0 2006.201.12:40:09.19#ibcon#enter sib2, iclass 7, count 0 2006.201.12:40:09.19#ibcon#flushed, iclass 7, count 0 2006.201.12:40:09.19#ibcon#about to write, iclass 7, count 0 2006.201.12:40:09.19#ibcon#wrote, iclass 7, count 0 2006.201.12:40:09.19#ibcon#about to read 3, iclass 7, count 0 2006.201.12:40:09.21#ibcon#read 3, iclass 7, count 0 2006.201.12:40:09.21#ibcon#about to read 4, iclass 7, count 0 2006.201.12:40:09.21#ibcon#read 4, iclass 7, count 0 2006.201.12:40:09.21#ibcon#about to read 5, iclass 7, count 0 2006.201.12:40:09.21#ibcon#read 5, iclass 7, count 0 2006.201.12:40:09.21#ibcon#about to read 6, iclass 7, count 0 2006.201.12:40:09.21#ibcon#read 6, iclass 7, count 0 2006.201.12:40:09.21#ibcon#end of sib2, iclass 7, count 0 2006.201.12:40:09.21#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:40:09.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:40:09.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:40:09.21#ibcon#*before write, iclass 7, count 0 2006.201.12:40:09.21#ibcon#enter sib2, iclass 7, count 0 2006.201.12:40:09.21#ibcon#flushed, iclass 7, count 0 2006.201.12:40:09.21#ibcon#about to write, iclass 7, count 0 2006.201.12:40:09.21#ibcon#wrote, iclass 7, count 0 2006.201.12:40:09.21#ibcon#about to read 3, iclass 7, count 0 2006.201.12:40:09.25#ibcon#read 3, iclass 7, count 0 2006.201.12:40:09.25#ibcon#about to read 4, iclass 7, count 0 2006.201.12:40:09.25#ibcon#read 4, iclass 7, count 0 2006.201.12:40:09.25#ibcon#about to read 5, iclass 7, count 0 2006.201.12:40:09.25#ibcon#read 5, iclass 7, count 0 2006.201.12:40:09.25#ibcon#about to read 6, iclass 7, count 0 2006.201.12:40:09.25#ibcon#read 6, iclass 7, count 0 2006.201.12:40:09.25#ibcon#end of sib2, iclass 7, count 0 2006.201.12:40:09.25#ibcon#*after write, iclass 7, count 0 2006.201.12:40:09.25#ibcon#*before return 0, iclass 7, count 0 2006.201.12:40:09.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:09.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:40:09.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:40:09.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:40:09.25$vck44/vb=6,4 2006.201.12:40:09.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.12:40:09.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.12:40:09.25#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:09.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:09.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:09.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:09.31#ibcon#enter wrdev, iclass 11, count 2 2006.201.12:40:09.31#ibcon#first serial, iclass 11, count 2 2006.201.12:40:09.31#ibcon#enter sib2, iclass 11, count 2 2006.201.12:40:09.31#ibcon#flushed, iclass 11, count 2 2006.201.12:40:09.31#ibcon#about to write, iclass 11, count 2 2006.201.12:40:09.31#ibcon#wrote, iclass 11, count 2 2006.201.12:40:09.31#ibcon#about to read 3, iclass 11, count 2 2006.201.12:40:09.33#ibcon#read 3, iclass 11, count 2 2006.201.12:40:09.33#ibcon#about to read 4, iclass 11, count 2 2006.201.12:40:09.33#ibcon#read 4, iclass 11, count 2 2006.201.12:40:09.33#ibcon#about to read 5, iclass 11, count 2 2006.201.12:40:09.33#ibcon#read 5, iclass 11, count 2 2006.201.12:40:09.33#ibcon#about to read 6, iclass 11, count 2 2006.201.12:40:09.33#ibcon#read 6, iclass 11, count 2 2006.201.12:40:09.33#ibcon#end of sib2, iclass 11, count 2 2006.201.12:40:09.33#ibcon#*mode == 0, iclass 11, count 2 2006.201.12:40:09.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.12:40:09.33#ibcon#[27=AT06-04\r\n] 2006.201.12:40:09.33#ibcon#*before write, iclass 11, count 2 2006.201.12:40:09.33#ibcon#enter sib2, iclass 11, count 2 2006.201.12:40:09.33#ibcon#flushed, iclass 11, count 2 2006.201.12:40:09.33#ibcon#about to write, iclass 11, count 2 2006.201.12:40:09.33#ibcon#wrote, iclass 11, count 2 2006.201.12:40:09.33#ibcon#about to read 3, iclass 11, count 2 2006.201.12:40:09.36#ibcon#read 3, iclass 11, count 2 2006.201.12:40:09.36#ibcon#about to read 4, iclass 11, count 2 2006.201.12:40:09.36#ibcon#read 4, iclass 11, count 2 2006.201.12:40:09.36#ibcon#about to read 5, iclass 11, count 2 2006.201.12:40:09.36#ibcon#read 5, iclass 11, count 2 2006.201.12:40:09.36#ibcon#about to read 6, iclass 11, count 2 2006.201.12:40:09.36#ibcon#read 6, iclass 11, count 2 2006.201.12:40:09.36#ibcon#end of sib2, iclass 11, count 2 2006.201.12:40:09.36#ibcon#*after write, iclass 11, count 2 2006.201.12:40:09.36#ibcon#*before return 0, iclass 11, count 2 2006.201.12:40:09.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:09.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:40:09.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.12:40:09.36#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:09.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:09.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:09.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:09.48#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:40:09.48#ibcon#first serial, iclass 11, count 0 2006.201.12:40:09.48#ibcon#enter sib2, iclass 11, count 0 2006.201.12:40:09.48#ibcon#flushed, iclass 11, count 0 2006.201.12:40:09.48#ibcon#about to write, iclass 11, count 0 2006.201.12:40:09.48#ibcon#wrote, iclass 11, count 0 2006.201.12:40:09.48#ibcon#about to read 3, iclass 11, count 0 2006.201.12:40:09.50#ibcon#read 3, iclass 11, count 0 2006.201.12:40:09.50#ibcon#about to read 4, iclass 11, count 0 2006.201.12:40:09.50#ibcon#read 4, iclass 11, count 0 2006.201.12:40:09.50#ibcon#about to read 5, iclass 11, count 0 2006.201.12:40:09.50#ibcon#read 5, iclass 11, count 0 2006.201.12:40:09.50#ibcon#about to read 6, iclass 11, count 0 2006.201.12:40:09.50#ibcon#read 6, iclass 11, count 0 2006.201.12:40:09.50#ibcon#end of sib2, iclass 11, count 0 2006.201.12:40:09.50#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:40:09.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:40:09.50#ibcon#[27=USB\r\n] 2006.201.12:40:09.50#ibcon#*before write, iclass 11, count 0 2006.201.12:40:09.50#ibcon#enter sib2, iclass 11, count 0 2006.201.12:40:09.50#ibcon#flushed, iclass 11, count 0 2006.201.12:40:09.50#ibcon#about to write, iclass 11, count 0 2006.201.12:40:09.50#ibcon#wrote, iclass 11, count 0 2006.201.12:40:09.50#ibcon#about to read 3, iclass 11, count 0 2006.201.12:40:09.53#ibcon#read 3, iclass 11, count 0 2006.201.12:40:09.53#ibcon#about to read 4, iclass 11, count 0 2006.201.12:40:09.53#ibcon#read 4, iclass 11, count 0 2006.201.12:40:09.53#ibcon#about to read 5, iclass 11, count 0 2006.201.12:40:09.53#ibcon#read 5, iclass 11, count 0 2006.201.12:40:09.53#ibcon#about to read 6, iclass 11, count 0 2006.201.12:40:09.53#ibcon#read 6, iclass 11, count 0 2006.201.12:40:09.53#ibcon#end of sib2, iclass 11, count 0 2006.201.12:40:09.53#ibcon#*after write, iclass 11, count 0 2006.201.12:40:09.53#ibcon#*before return 0, iclass 11, count 0 2006.201.12:40:09.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:09.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:40:09.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:40:09.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:40:09.53$vck44/vblo=7,734.99 2006.201.12:40:09.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.12:40:09.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.12:40:09.53#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:09.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:09.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:09.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:09.53#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:40:09.53#ibcon#first serial, iclass 13, count 0 2006.201.12:40:09.53#ibcon#enter sib2, iclass 13, count 0 2006.201.12:40:09.53#ibcon#flushed, iclass 13, count 0 2006.201.12:40:09.53#ibcon#about to write, iclass 13, count 0 2006.201.12:40:09.53#ibcon#wrote, iclass 13, count 0 2006.201.12:40:09.53#ibcon#about to read 3, iclass 13, count 0 2006.201.12:40:09.55#ibcon#read 3, iclass 13, count 0 2006.201.12:40:09.55#ibcon#about to read 4, iclass 13, count 0 2006.201.12:40:09.55#ibcon#read 4, iclass 13, count 0 2006.201.12:40:09.55#ibcon#about to read 5, iclass 13, count 0 2006.201.12:40:09.55#ibcon#read 5, iclass 13, count 0 2006.201.12:40:09.55#ibcon#about to read 6, iclass 13, count 0 2006.201.12:40:09.55#ibcon#read 6, iclass 13, count 0 2006.201.12:40:09.55#ibcon#end of sib2, iclass 13, count 0 2006.201.12:40:09.55#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:40:09.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:40:09.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:40:09.55#ibcon#*before write, iclass 13, count 0 2006.201.12:40:09.55#ibcon#enter sib2, iclass 13, count 0 2006.201.12:40:09.55#ibcon#flushed, iclass 13, count 0 2006.201.12:40:09.55#ibcon#about to write, iclass 13, count 0 2006.201.12:40:09.55#ibcon#wrote, iclass 13, count 0 2006.201.12:40:09.55#ibcon#about to read 3, iclass 13, count 0 2006.201.12:40:09.59#ibcon#read 3, iclass 13, count 0 2006.201.12:40:09.59#ibcon#about to read 4, iclass 13, count 0 2006.201.12:40:09.59#ibcon#read 4, iclass 13, count 0 2006.201.12:40:09.59#ibcon#about to read 5, iclass 13, count 0 2006.201.12:40:09.59#ibcon#read 5, iclass 13, count 0 2006.201.12:40:09.59#ibcon#about to read 6, iclass 13, count 0 2006.201.12:40:09.59#ibcon#read 6, iclass 13, count 0 2006.201.12:40:09.59#ibcon#end of sib2, iclass 13, count 0 2006.201.12:40:09.59#ibcon#*after write, iclass 13, count 0 2006.201.12:40:09.59#ibcon#*before return 0, iclass 13, count 0 2006.201.12:40:09.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:09.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:40:09.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:40:09.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:40:09.59$vck44/vb=7,4 2006.201.12:40:09.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.12:40:09.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.12:40:09.59#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:09.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:09.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:09.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:09.65#ibcon#enter wrdev, iclass 15, count 2 2006.201.12:40:09.65#ibcon#first serial, iclass 15, count 2 2006.201.12:40:09.65#ibcon#enter sib2, iclass 15, count 2 2006.201.12:40:09.65#ibcon#flushed, iclass 15, count 2 2006.201.12:40:09.65#ibcon#about to write, iclass 15, count 2 2006.201.12:40:09.65#ibcon#wrote, iclass 15, count 2 2006.201.12:40:09.65#ibcon#about to read 3, iclass 15, count 2 2006.201.12:40:09.67#ibcon#read 3, iclass 15, count 2 2006.201.12:40:09.67#ibcon#about to read 4, iclass 15, count 2 2006.201.12:40:09.67#ibcon#read 4, iclass 15, count 2 2006.201.12:40:09.67#ibcon#about to read 5, iclass 15, count 2 2006.201.12:40:09.67#ibcon#read 5, iclass 15, count 2 2006.201.12:40:09.67#ibcon#about to read 6, iclass 15, count 2 2006.201.12:40:09.67#ibcon#read 6, iclass 15, count 2 2006.201.12:40:09.67#ibcon#end of sib2, iclass 15, count 2 2006.201.12:40:09.67#ibcon#*mode == 0, iclass 15, count 2 2006.201.12:40:09.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.12:40:09.67#ibcon#[27=AT07-04\r\n] 2006.201.12:40:09.67#ibcon#*before write, iclass 15, count 2 2006.201.12:40:09.67#ibcon#enter sib2, iclass 15, count 2 2006.201.12:40:09.67#ibcon#flushed, iclass 15, count 2 2006.201.12:40:09.67#ibcon#about to write, iclass 15, count 2 2006.201.12:40:09.67#ibcon#wrote, iclass 15, count 2 2006.201.12:40:09.67#ibcon#about to read 3, iclass 15, count 2 2006.201.12:40:09.70#ibcon#read 3, iclass 15, count 2 2006.201.12:40:09.70#ibcon#about to read 4, iclass 15, count 2 2006.201.12:40:09.70#ibcon#read 4, iclass 15, count 2 2006.201.12:40:09.70#ibcon#about to read 5, iclass 15, count 2 2006.201.12:40:09.70#ibcon#read 5, iclass 15, count 2 2006.201.12:40:09.70#ibcon#about to read 6, iclass 15, count 2 2006.201.12:40:09.70#ibcon#read 6, iclass 15, count 2 2006.201.12:40:09.70#ibcon#end of sib2, iclass 15, count 2 2006.201.12:40:09.70#ibcon#*after write, iclass 15, count 2 2006.201.12:40:09.70#ibcon#*before return 0, iclass 15, count 2 2006.201.12:40:09.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:09.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:40:09.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.12:40:09.70#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:09.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:09.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:09.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:09.82#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:40:09.82#ibcon#first serial, iclass 15, count 0 2006.201.12:40:09.82#ibcon#enter sib2, iclass 15, count 0 2006.201.12:40:09.82#ibcon#flushed, iclass 15, count 0 2006.201.12:40:09.82#ibcon#about to write, iclass 15, count 0 2006.201.12:40:09.82#ibcon#wrote, iclass 15, count 0 2006.201.12:40:09.82#ibcon#about to read 3, iclass 15, count 0 2006.201.12:40:09.84#ibcon#read 3, iclass 15, count 0 2006.201.12:40:09.84#ibcon#about to read 4, iclass 15, count 0 2006.201.12:40:09.84#ibcon#read 4, iclass 15, count 0 2006.201.12:40:09.84#ibcon#about to read 5, iclass 15, count 0 2006.201.12:40:09.84#ibcon#read 5, iclass 15, count 0 2006.201.12:40:09.84#ibcon#about to read 6, iclass 15, count 0 2006.201.12:40:09.84#ibcon#read 6, iclass 15, count 0 2006.201.12:40:09.84#ibcon#end of sib2, iclass 15, count 0 2006.201.12:40:09.84#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:40:09.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:40:09.84#ibcon#[27=USB\r\n] 2006.201.12:40:09.84#ibcon#*before write, iclass 15, count 0 2006.201.12:40:09.84#ibcon#enter sib2, iclass 15, count 0 2006.201.12:40:09.84#ibcon#flushed, iclass 15, count 0 2006.201.12:40:09.84#ibcon#about to write, iclass 15, count 0 2006.201.12:40:09.84#ibcon#wrote, iclass 15, count 0 2006.201.12:40:09.84#ibcon#about to read 3, iclass 15, count 0 2006.201.12:40:09.87#ibcon#read 3, iclass 15, count 0 2006.201.12:40:09.87#ibcon#about to read 4, iclass 15, count 0 2006.201.12:40:09.87#ibcon#read 4, iclass 15, count 0 2006.201.12:40:09.87#ibcon#about to read 5, iclass 15, count 0 2006.201.12:40:09.87#ibcon#read 5, iclass 15, count 0 2006.201.12:40:09.87#ibcon#about to read 6, iclass 15, count 0 2006.201.12:40:09.87#ibcon#read 6, iclass 15, count 0 2006.201.12:40:09.87#ibcon#end of sib2, iclass 15, count 0 2006.201.12:40:09.87#ibcon#*after write, iclass 15, count 0 2006.201.12:40:09.87#ibcon#*before return 0, iclass 15, count 0 2006.201.12:40:09.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:09.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:40:09.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:40:09.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:40:09.87$vck44/vblo=8,744.99 2006.201.12:40:09.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.12:40:09.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.12:40:09.87#ibcon#ireg 17 cls_cnt 0 2006.201.12:40:09.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:09.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:09.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:09.87#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:40:09.87#ibcon#first serial, iclass 17, count 0 2006.201.12:40:09.87#ibcon#enter sib2, iclass 17, count 0 2006.201.12:40:09.87#ibcon#flushed, iclass 17, count 0 2006.201.12:40:09.87#ibcon#about to write, iclass 17, count 0 2006.201.12:40:09.87#ibcon#wrote, iclass 17, count 0 2006.201.12:40:09.87#ibcon#about to read 3, iclass 17, count 0 2006.201.12:40:09.89#ibcon#read 3, iclass 17, count 0 2006.201.12:40:09.89#ibcon#about to read 4, iclass 17, count 0 2006.201.12:40:09.89#ibcon#read 4, iclass 17, count 0 2006.201.12:40:09.89#ibcon#about to read 5, iclass 17, count 0 2006.201.12:40:09.89#ibcon#read 5, iclass 17, count 0 2006.201.12:40:09.89#ibcon#about to read 6, iclass 17, count 0 2006.201.12:40:09.89#ibcon#read 6, iclass 17, count 0 2006.201.12:40:09.89#ibcon#end of sib2, iclass 17, count 0 2006.201.12:40:09.89#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:40:09.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:40:09.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:40:09.89#ibcon#*before write, iclass 17, count 0 2006.201.12:40:09.89#ibcon#enter sib2, iclass 17, count 0 2006.201.12:40:09.89#ibcon#flushed, iclass 17, count 0 2006.201.12:40:09.89#ibcon#about to write, iclass 17, count 0 2006.201.12:40:09.89#ibcon#wrote, iclass 17, count 0 2006.201.12:40:09.89#ibcon#about to read 3, iclass 17, count 0 2006.201.12:40:09.93#ibcon#read 3, iclass 17, count 0 2006.201.12:40:09.93#ibcon#about to read 4, iclass 17, count 0 2006.201.12:40:09.93#ibcon#read 4, iclass 17, count 0 2006.201.12:40:09.93#ibcon#about to read 5, iclass 17, count 0 2006.201.12:40:09.93#ibcon#read 5, iclass 17, count 0 2006.201.12:40:09.93#ibcon#about to read 6, iclass 17, count 0 2006.201.12:40:09.93#ibcon#read 6, iclass 17, count 0 2006.201.12:40:09.93#ibcon#end of sib2, iclass 17, count 0 2006.201.12:40:09.93#ibcon#*after write, iclass 17, count 0 2006.201.12:40:09.93#ibcon#*before return 0, iclass 17, count 0 2006.201.12:40:09.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:09.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:40:09.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:40:09.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:40:09.93$vck44/vb=8,4 2006.201.12:40:09.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.12:40:09.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.12:40:09.93#ibcon#ireg 11 cls_cnt 2 2006.201.12:40:09.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:09.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:09.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:09.99#ibcon#enter wrdev, iclass 19, count 2 2006.201.12:40:09.99#ibcon#first serial, iclass 19, count 2 2006.201.12:40:09.99#ibcon#enter sib2, iclass 19, count 2 2006.201.12:40:09.99#ibcon#flushed, iclass 19, count 2 2006.201.12:40:09.99#ibcon#about to write, iclass 19, count 2 2006.201.12:40:09.99#ibcon#wrote, iclass 19, count 2 2006.201.12:40:09.99#ibcon#about to read 3, iclass 19, count 2 2006.201.12:40:10.01#ibcon#read 3, iclass 19, count 2 2006.201.12:40:10.01#ibcon#about to read 4, iclass 19, count 2 2006.201.12:40:10.01#ibcon#read 4, iclass 19, count 2 2006.201.12:40:10.01#ibcon#about to read 5, iclass 19, count 2 2006.201.12:40:10.01#ibcon#read 5, iclass 19, count 2 2006.201.12:40:10.01#ibcon#about to read 6, iclass 19, count 2 2006.201.12:40:10.01#ibcon#read 6, iclass 19, count 2 2006.201.12:40:10.01#ibcon#end of sib2, iclass 19, count 2 2006.201.12:40:10.01#ibcon#*mode == 0, iclass 19, count 2 2006.201.12:40:10.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.12:40:10.01#ibcon#[27=AT08-04\r\n] 2006.201.12:40:10.01#ibcon#*before write, iclass 19, count 2 2006.201.12:40:10.01#ibcon#enter sib2, iclass 19, count 2 2006.201.12:40:10.01#ibcon#flushed, iclass 19, count 2 2006.201.12:40:10.01#ibcon#about to write, iclass 19, count 2 2006.201.12:40:10.01#ibcon#wrote, iclass 19, count 2 2006.201.12:40:10.01#ibcon#about to read 3, iclass 19, count 2 2006.201.12:40:10.04#ibcon#read 3, iclass 19, count 2 2006.201.12:40:10.04#ibcon#about to read 4, iclass 19, count 2 2006.201.12:40:10.04#ibcon#read 4, iclass 19, count 2 2006.201.12:40:10.04#ibcon#about to read 5, iclass 19, count 2 2006.201.12:40:10.04#ibcon#read 5, iclass 19, count 2 2006.201.12:40:10.04#ibcon#about to read 6, iclass 19, count 2 2006.201.12:40:10.04#ibcon#read 6, iclass 19, count 2 2006.201.12:40:10.04#ibcon#end of sib2, iclass 19, count 2 2006.201.12:40:10.04#ibcon#*after write, iclass 19, count 2 2006.201.12:40:10.04#ibcon#*before return 0, iclass 19, count 2 2006.201.12:40:10.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:10.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:40:10.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.12:40:10.04#ibcon#ireg 7 cls_cnt 0 2006.201.12:40:10.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:10.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:10.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:10.16#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:40:10.16#ibcon#first serial, iclass 19, count 0 2006.201.12:40:10.16#ibcon#enter sib2, iclass 19, count 0 2006.201.12:40:10.16#ibcon#flushed, iclass 19, count 0 2006.201.12:40:10.16#ibcon#about to write, iclass 19, count 0 2006.201.12:40:10.16#ibcon#wrote, iclass 19, count 0 2006.201.12:40:10.16#ibcon#about to read 3, iclass 19, count 0 2006.201.12:40:10.18#ibcon#read 3, iclass 19, count 0 2006.201.12:40:10.18#ibcon#about to read 4, iclass 19, count 0 2006.201.12:40:10.18#ibcon#read 4, iclass 19, count 0 2006.201.12:40:10.18#ibcon#about to read 5, iclass 19, count 0 2006.201.12:40:10.18#ibcon#read 5, iclass 19, count 0 2006.201.12:40:10.18#ibcon#about to read 6, iclass 19, count 0 2006.201.12:40:10.18#ibcon#read 6, iclass 19, count 0 2006.201.12:40:10.18#ibcon#end of sib2, iclass 19, count 0 2006.201.12:40:10.18#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:40:10.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:40:10.18#ibcon#[27=USB\r\n] 2006.201.12:40:10.18#ibcon#*before write, iclass 19, count 0 2006.201.12:40:10.18#ibcon#enter sib2, iclass 19, count 0 2006.201.12:40:10.18#ibcon#flushed, iclass 19, count 0 2006.201.12:40:10.18#ibcon#about to write, iclass 19, count 0 2006.201.12:40:10.18#ibcon#wrote, iclass 19, count 0 2006.201.12:40:10.18#ibcon#about to read 3, iclass 19, count 0 2006.201.12:40:10.21#ibcon#read 3, iclass 19, count 0 2006.201.12:40:10.21#ibcon#about to read 4, iclass 19, count 0 2006.201.12:40:10.21#ibcon#read 4, iclass 19, count 0 2006.201.12:40:10.21#ibcon#about to read 5, iclass 19, count 0 2006.201.12:40:10.21#ibcon#read 5, iclass 19, count 0 2006.201.12:40:10.21#ibcon#about to read 6, iclass 19, count 0 2006.201.12:40:10.21#ibcon#read 6, iclass 19, count 0 2006.201.12:40:10.21#ibcon#end of sib2, iclass 19, count 0 2006.201.12:40:10.21#ibcon#*after write, iclass 19, count 0 2006.201.12:40:10.21#ibcon#*before return 0, iclass 19, count 0 2006.201.12:40:10.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:10.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:40:10.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:40:10.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:40:10.21$vck44/vabw=wide 2006.201.12:40:10.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.12:40:10.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.12:40:10.21#ibcon#ireg 8 cls_cnt 0 2006.201.12:40:10.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:10.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:10.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:10.21#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:40:10.21#ibcon#first serial, iclass 21, count 0 2006.201.12:40:10.21#ibcon#enter sib2, iclass 21, count 0 2006.201.12:40:10.21#ibcon#flushed, iclass 21, count 0 2006.201.12:40:10.21#ibcon#about to write, iclass 21, count 0 2006.201.12:40:10.21#ibcon#wrote, iclass 21, count 0 2006.201.12:40:10.21#ibcon#about to read 3, iclass 21, count 0 2006.201.12:40:10.23#ibcon#read 3, iclass 21, count 0 2006.201.12:40:10.23#ibcon#about to read 4, iclass 21, count 0 2006.201.12:40:10.23#ibcon#read 4, iclass 21, count 0 2006.201.12:40:10.23#ibcon#about to read 5, iclass 21, count 0 2006.201.12:40:10.23#ibcon#read 5, iclass 21, count 0 2006.201.12:40:10.23#ibcon#about to read 6, iclass 21, count 0 2006.201.12:40:10.23#ibcon#read 6, iclass 21, count 0 2006.201.12:40:10.23#ibcon#end of sib2, iclass 21, count 0 2006.201.12:40:10.23#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:40:10.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:40:10.23#ibcon#[25=BW32\r\n] 2006.201.12:40:10.23#ibcon#*before write, iclass 21, count 0 2006.201.12:40:10.23#ibcon#enter sib2, iclass 21, count 0 2006.201.12:40:10.23#ibcon#flushed, iclass 21, count 0 2006.201.12:40:10.23#ibcon#about to write, iclass 21, count 0 2006.201.12:40:10.23#ibcon#wrote, iclass 21, count 0 2006.201.12:40:10.23#ibcon#about to read 3, iclass 21, count 0 2006.201.12:40:10.26#ibcon#read 3, iclass 21, count 0 2006.201.12:40:10.26#ibcon#about to read 4, iclass 21, count 0 2006.201.12:40:10.26#ibcon#read 4, iclass 21, count 0 2006.201.12:40:10.26#ibcon#about to read 5, iclass 21, count 0 2006.201.12:40:10.26#ibcon#read 5, iclass 21, count 0 2006.201.12:40:10.26#ibcon#about to read 6, iclass 21, count 0 2006.201.12:40:10.26#ibcon#read 6, iclass 21, count 0 2006.201.12:40:10.26#ibcon#end of sib2, iclass 21, count 0 2006.201.12:40:10.26#ibcon#*after write, iclass 21, count 0 2006.201.12:40:10.26#ibcon#*before return 0, iclass 21, count 0 2006.201.12:40:10.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:10.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:40:10.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:40:10.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:40:10.26$vck44/vbbw=wide 2006.201.12:40:10.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.12:40:10.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.12:40:10.26#ibcon#ireg 8 cls_cnt 0 2006.201.12:40:10.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:40:10.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:40:10.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:40:10.33#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:40:10.33#ibcon#first serial, iclass 23, count 0 2006.201.12:40:10.33#ibcon#enter sib2, iclass 23, count 0 2006.201.12:40:10.33#ibcon#flushed, iclass 23, count 0 2006.201.12:40:10.33#ibcon#about to write, iclass 23, count 0 2006.201.12:40:10.33#ibcon#wrote, iclass 23, count 0 2006.201.12:40:10.33#ibcon#about to read 3, iclass 23, count 0 2006.201.12:40:10.35#ibcon#read 3, iclass 23, count 0 2006.201.12:40:10.35#ibcon#about to read 4, iclass 23, count 0 2006.201.12:40:10.35#ibcon#read 4, iclass 23, count 0 2006.201.12:40:10.35#ibcon#about to read 5, iclass 23, count 0 2006.201.12:40:10.35#ibcon#read 5, iclass 23, count 0 2006.201.12:40:10.35#ibcon#about to read 6, iclass 23, count 0 2006.201.12:40:10.35#ibcon#read 6, iclass 23, count 0 2006.201.12:40:10.35#ibcon#end of sib2, iclass 23, count 0 2006.201.12:40:10.35#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:40:10.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:40:10.35#ibcon#[27=BW32\r\n] 2006.201.12:40:10.35#ibcon#*before write, iclass 23, count 0 2006.201.12:40:10.35#ibcon#enter sib2, iclass 23, count 0 2006.201.12:40:10.35#ibcon#flushed, iclass 23, count 0 2006.201.12:40:10.35#ibcon#about to write, iclass 23, count 0 2006.201.12:40:10.35#ibcon#wrote, iclass 23, count 0 2006.201.12:40:10.35#ibcon#about to read 3, iclass 23, count 0 2006.201.12:40:10.38#ibcon#read 3, iclass 23, count 0 2006.201.12:40:10.38#ibcon#about to read 4, iclass 23, count 0 2006.201.12:40:10.38#ibcon#read 4, iclass 23, count 0 2006.201.12:40:10.38#ibcon#about to read 5, iclass 23, count 0 2006.201.12:40:10.38#ibcon#read 5, iclass 23, count 0 2006.201.12:40:10.38#ibcon#about to read 6, iclass 23, count 0 2006.201.12:40:10.38#ibcon#read 6, iclass 23, count 0 2006.201.12:40:10.38#ibcon#end of sib2, iclass 23, count 0 2006.201.12:40:10.38#ibcon#*after write, iclass 23, count 0 2006.201.12:40:10.38#ibcon#*before return 0, iclass 23, count 0 2006.201.12:40:10.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:40:10.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:40:10.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:40:10.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:40:10.38$setupk4/ifdk4 2006.201.12:40:10.38$ifdk4/lo= 2006.201.12:40:10.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:40:10.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:40:10.38$ifdk4/patch= 2006.201.12:40:10.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:40:10.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:40:10.38$setupk4/!*+20s 2006.201.12:40:12.24#abcon#<5=/04 2.2 4.3 21.061001004.2\r\n> 2006.201.12:40:12.26#abcon#{5=INTERFACE CLEAR} 2006.201.12:40:12.32#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:40:22.41#abcon#<5=/04 2.2 4.3 21.061001004.2\r\n> 2006.201.12:40:22.43#abcon#{5=INTERFACE CLEAR} 2006.201.12:40:22.49#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:40:24.85$setupk4/"tpicd 2006.201.12:40:24.85$setupk4/echo=off 2006.201.12:40:24.85$setupk4/xlog=off 2006.201.12:40:24.85:!2006.201.12:43:04 2006.201.12:41:11.13#trakl#Source acquired 2006.201.12:41:12.13#flagr#flagr/antenna,acquired 2006.201.12:43:04.00:preob 2006.201.12:43:04.14/onsource/TRACKING 2006.201.12:43:04.14:!2006.201.12:43:14 2006.201.12:43:14.00:"tape 2006.201.12:43:14.00:"st=record 2006.201.12:43:14.00:data_valid=on 2006.201.12:43:14.00:midob 2006.201.12:43:15.14/onsource/TRACKING 2006.201.12:43:15.14/wx/21.05,1004.2,100 2006.201.12:43:15.33/cable/+6.4754E-03 2006.201.12:43:16.42/va/01,08,usb,yes,28,30 2006.201.12:43:16.42/va/02,07,usb,yes,30,31 2006.201.12:43:16.42/va/03,08,usb,yes,27,28 2006.201.12:43:16.42/va/04,07,usb,yes,31,32 2006.201.12:43:16.42/va/05,04,usb,yes,27,28 2006.201.12:43:16.42/va/06,05,usb,yes,27,27 2006.201.12:43:16.42/va/07,05,usb,yes,26,28 2006.201.12:43:16.42/va/08,04,usb,yes,26,32 2006.201.12:43:16.65/valo/01,524.99,yes,locked 2006.201.12:43:16.65/valo/02,534.99,yes,locked 2006.201.12:43:16.65/valo/03,564.99,yes,locked 2006.201.12:43:16.65/valo/04,624.99,yes,locked 2006.201.12:43:16.65/valo/05,734.99,yes,locked 2006.201.12:43:16.65/valo/06,814.99,yes,locked 2006.201.12:43:16.65/valo/07,864.99,yes,locked 2006.201.12:43:16.65/valo/08,884.99,yes,locked 2006.201.12:43:17.74/vb/01,04,usb,yes,28,26 2006.201.12:43:17.74/vb/02,05,usb,yes,27,27 2006.201.12:43:17.74/vb/03,04,usb,yes,28,31 2006.201.12:43:17.74/vb/04,05,usb,yes,28,27 2006.201.12:43:17.74/vb/05,04,usb,yes,25,27 2006.201.12:43:17.74/vb/06,04,usb,yes,29,25 2006.201.12:43:17.74/vb/07,04,usb,yes,29,29 2006.201.12:43:17.74/vb/08,04,usb,yes,27,30 2006.201.12:43:17.98/vblo/01,629.99,yes,locked 2006.201.12:43:17.98/vblo/02,634.99,yes,locked 2006.201.12:43:17.98/vblo/03,649.99,yes,locked 2006.201.12:43:17.98/vblo/04,679.99,yes,locked 2006.201.12:43:17.98/vblo/05,709.99,yes,locked 2006.201.12:43:17.98/vblo/06,719.99,yes,locked 2006.201.12:43:17.98/vblo/07,734.99,yes,locked 2006.201.12:43:17.98/vblo/08,744.99,yes,locked 2006.201.12:43:18.13/vabw/8 2006.201.12:43:18.28/vbbw/8 2006.201.12:43:18.37/xfe/off,on,15.0 2006.201.12:43:18.75/ifatt/23,28,28,28 2006.201.12:43:19.06/fmout-gps/S +4.61E-07 2006.201.12:43:19.13:!2006.201.12:43:54 2006.201.12:43:54.00:data_valid=off 2006.201.12:43:54.00:"et 2006.201.12:43:54.00:!+3s 2006.201.12:43:57.02:"tape 2006.201.12:43:57.02:postob 2006.201.12:43:57.21/cable/+6.4724E-03 2006.201.12:43:57.21/wx/21.05,1004.1,100 2006.201.12:43:57.29/fmout-gps/S +4.61E-07 2006.201.12:43:57.29:scan_name=201-1245,jd0607,400 2006.201.12:43:57.29:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.201.12:43:59.14#flagr#flagr/antenna,new-source 2006.201.12:43:59.14:checkk5 2006.201.12:43:59.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:43:59.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:44:00.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:44:00.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:44:01.00/chk_obsdata//k5ts1/T2011243??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:44:01.37/chk_obsdata//k5ts2/T2011243??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:44:01.73/chk_obsdata//k5ts3/T2011243??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:44:02.09/chk_obsdata//k5ts4/T2011243??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.12:44:02.78/k5log//k5ts1_log_newline 2006.201.12:44:03.48/k5log//k5ts2_log_newline 2006.201.12:44:04.16/k5log//k5ts3_log_newline 2006.201.12:44:04.84/k5log//k5ts4_log_newline 2006.201.12:44:04.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:44:04.87:setupk4=1 2006.201.12:44:04.87$setupk4/echo=on 2006.201.12:44:04.87$setupk4/pcalon 2006.201.12:44:04.87$pcalon/"no phase cal control is implemented here 2006.201.12:44:04.87$setupk4/"tpicd=stop 2006.201.12:44:04.87$setupk4/"rec=synch_on 2006.201.12:44:04.87$setupk4/"rec_mode=128 2006.201.12:44:04.87$setupk4/!* 2006.201.12:44:04.87$setupk4/recpk4 2006.201.12:44:04.87$recpk4/recpatch= 2006.201.12:44:04.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:44:04.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:44:04.87$setupk4/vck44 2006.201.12:44:04.87$vck44/valo=1,524.99 2006.201.12:44:04.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.12:44:04.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.12:44:04.87#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:04.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:04.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:04.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:04.87#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:44:04.87#ibcon#first serial, iclass 5, count 0 2006.201.12:44:04.87#ibcon#enter sib2, iclass 5, count 0 2006.201.12:44:04.87#ibcon#flushed, iclass 5, count 0 2006.201.12:44:04.87#ibcon#about to write, iclass 5, count 0 2006.201.12:44:04.87#ibcon#wrote, iclass 5, count 0 2006.201.12:44:04.87#ibcon#about to read 3, iclass 5, count 0 2006.201.12:44:04.91#ibcon#read 3, iclass 5, count 0 2006.201.12:44:04.91#ibcon#about to read 4, iclass 5, count 0 2006.201.12:44:04.91#ibcon#read 4, iclass 5, count 0 2006.201.12:44:04.91#ibcon#about to read 5, iclass 5, count 0 2006.201.12:44:04.91#ibcon#read 5, iclass 5, count 0 2006.201.12:44:04.91#ibcon#about to read 6, iclass 5, count 0 2006.201.12:44:04.91#ibcon#read 6, iclass 5, count 0 2006.201.12:44:04.91#ibcon#end of sib2, iclass 5, count 0 2006.201.12:44:04.91#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:44:04.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:44:04.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:44:04.91#ibcon#*before write, iclass 5, count 0 2006.201.12:44:04.91#ibcon#enter sib2, iclass 5, count 0 2006.201.12:44:04.91#ibcon#flushed, iclass 5, count 0 2006.201.12:44:04.91#ibcon#about to write, iclass 5, count 0 2006.201.12:44:04.91#ibcon#wrote, iclass 5, count 0 2006.201.12:44:04.91#ibcon#about to read 3, iclass 5, count 0 2006.201.12:44:04.96#ibcon#read 3, iclass 5, count 0 2006.201.12:44:04.96#ibcon#about to read 4, iclass 5, count 0 2006.201.12:44:04.96#ibcon#read 4, iclass 5, count 0 2006.201.12:44:04.96#ibcon#about to read 5, iclass 5, count 0 2006.201.12:44:04.96#ibcon#read 5, iclass 5, count 0 2006.201.12:44:04.96#ibcon#about to read 6, iclass 5, count 0 2006.201.12:44:04.96#ibcon#read 6, iclass 5, count 0 2006.201.12:44:04.96#ibcon#end of sib2, iclass 5, count 0 2006.201.12:44:04.96#ibcon#*after write, iclass 5, count 0 2006.201.12:44:04.96#ibcon#*before return 0, iclass 5, count 0 2006.201.12:44:04.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:04.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:04.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:44:04.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:44:04.96$vck44/va=1,8 2006.201.12:44:04.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.12:44:04.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.12:44:04.96#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:04.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:04.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:04.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:04.96#ibcon#enter wrdev, iclass 7, count 2 2006.201.12:44:04.96#ibcon#first serial, iclass 7, count 2 2006.201.12:44:04.96#ibcon#enter sib2, iclass 7, count 2 2006.201.12:44:04.96#ibcon#flushed, iclass 7, count 2 2006.201.12:44:04.96#ibcon#about to write, iclass 7, count 2 2006.201.12:44:04.96#ibcon#wrote, iclass 7, count 2 2006.201.12:44:04.96#ibcon#about to read 3, iclass 7, count 2 2006.201.12:44:04.98#ibcon#read 3, iclass 7, count 2 2006.201.12:44:04.98#ibcon#about to read 4, iclass 7, count 2 2006.201.12:44:04.98#ibcon#read 4, iclass 7, count 2 2006.201.12:44:04.98#ibcon#about to read 5, iclass 7, count 2 2006.201.12:44:04.98#ibcon#read 5, iclass 7, count 2 2006.201.12:44:04.98#ibcon#about to read 6, iclass 7, count 2 2006.201.12:44:04.98#ibcon#read 6, iclass 7, count 2 2006.201.12:44:04.98#ibcon#end of sib2, iclass 7, count 2 2006.201.12:44:04.98#ibcon#*mode == 0, iclass 7, count 2 2006.201.12:44:04.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.12:44:04.98#ibcon#[25=AT01-08\r\n] 2006.201.12:44:04.98#ibcon#*before write, iclass 7, count 2 2006.201.12:44:04.98#ibcon#enter sib2, iclass 7, count 2 2006.201.12:44:04.98#ibcon#flushed, iclass 7, count 2 2006.201.12:44:04.98#ibcon#about to write, iclass 7, count 2 2006.201.12:44:04.98#ibcon#wrote, iclass 7, count 2 2006.201.12:44:04.98#ibcon#about to read 3, iclass 7, count 2 2006.201.12:44:05.01#ibcon#read 3, iclass 7, count 2 2006.201.12:44:05.01#ibcon#about to read 4, iclass 7, count 2 2006.201.12:44:05.01#ibcon#read 4, iclass 7, count 2 2006.201.12:44:05.01#ibcon#about to read 5, iclass 7, count 2 2006.201.12:44:05.01#ibcon#read 5, iclass 7, count 2 2006.201.12:44:05.01#ibcon#about to read 6, iclass 7, count 2 2006.201.12:44:05.01#ibcon#read 6, iclass 7, count 2 2006.201.12:44:05.01#ibcon#end of sib2, iclass 7, count 2 2006.201.12:44:05.01#ibcon#*after write, iclass 7, count 2 2006.201.12:44:05.01#ibcon#*before return 0, iclass 7, count 2 2006.201.12:44:05.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:05.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:05.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.12:44:05.01#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:05.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:05.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:05.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:05.13#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:44:05.13#ibcon#first serial, iclass 7, count 0 2006.201.12:44:05.13#ibcon#enter sib2, iclass 7, count 0 2006.201.12:44:05.13#ibcon#flushed, iclass 7, count 0 2006.201.12:44:05.13#ibcon#about to write, iclass 7, count 0 2006.201.12:44:05.13#ibcon#wrote, iclass 7, count 0 2006.201.12:44:05.13#ibcon#about to read 3, iclass 7, count 0 2006.201.12:44:05.15#ibcon#read 3, iclass 7, count 0 2006.201.12:44:05.15#ibcon#about to read 4, iclass 7, count 0 2006.201.12:44:05.15#ibcon#read 4, iclass 7, count 0 2006.201.12:44:05.15#ibcon#about to read 5, iclass 7, count 0 2006.201.12:44:05.15#ibcon#read 5, iclass 7, count 0 2006.201.12:44:05.15#ibcon#about to read 6, iclass 7, count 0 2006.201.12:44:05.15#ibcon#read 6, iclass 7, count 0 2006.201.12:44:05.15#ibcon#end of sib2, iclass 7, count 0 2006.201.12:44:05.15#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:44:05.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:44:05.15#ibcon#[25=USB\r\n] 2006.201.12:44:05.15#ibcon#*before write, iclass 7, count 0 2006.201.12:44:05.15#ibcon#enter sib2, iclass 7, count 0 2006.201.12:44:05.15#ibcon#flushed, iclass 7, count 0 2006.201.12:44:05.15#ibcon#about to write, iclass 7, count 0 2006.201.12:44:05.15#ibcon#wrote, iclass 7, count 0 2006.201.12:44:05.15#ibcon#about to read 3, iclass 7, count 0 2006.201.12:44:05.18#ibcon#read 3, iclass 7, count 0 2006.201.12:44:05.18#ibcon#about to read 4, iclass 7, count 0 2006.201.12:44:05.18#ibcon#read 4, iclass 7, count 0 2006.201.12:44:05.18#ibcon#about to read 5, iclass 7, count 0 2006.201.12:44:05.18#ibcon#read 5, iclass 7, count 0 2006.201.12:44:05.18#ibcon#about to read 6, iclass 7, count 0 2006.201.12:44:05.18#ibcon#read 6, iclass 7, count 0 2006.201.12:44:05.18#ibcon#end of sib2, iclass 7, count 0 2006.201.12:44:05.18#ibcon#*after write, iclass 7, count 0 2006.201.12:44:05.18#ibcon#*before return 0, iclass 7, count 0 2006.201.12:44:05.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:05.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:05.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:44:05.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:44:05.18$vck44/valo=2,534.99 2006.201.12:44:05.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.12:44:05.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.12:44:05.18#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:05.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:05.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:05.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:05.18#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:44:05.18#ibcon#first serial, iclass 11, count 0 2006.201.12:44:05.18#ibcon#enter sib2, iclass 11, count 0 2006.201.12:44:05.18#ibcon#flushed, iclass 11, count 0 2006.201.12:44:05.18#ibcon#about to write, iclass 11, count 0 2006.201.12:44:05.18#ibcon#wrote, iclass 11, count 0 2006.201.12:44:05.18#ibcon#about to read 3, iclass 11, count 0 2006.201.12:44:05.20#ibcon#read 3, iclass 11, count 0 2006.201.12:44:05.20#ibcon#about to read 4, iclass 11, count 0 2006.201.12:44:05.20#ibcon#read 4, iclass 11, count 0 2006.201.12:44:05.20#ibcon#about to read 5, iclass 11, count 0 2006.201.12:44:05.20#ibcon#read 5, iclass 11, count 0 2006.201.12:44:05.20#ibcon#about to read 6, iclass 11, count 0 2006.201.12:44:05.20#ibcon#read 6, iclass 11, count 0 2006.201.12:44:05.20#ibcon#end of sib2, iclass 11, count 0 2006.201.12:44:05.20#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:44:05.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:44:05.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:44:05.20#ibcon#*before write, iclass 11, count 0 2006.201.12:44:05.20#ibcon#enter sib2, iclass 11, count 0 2006.201.12:44:05.20#ibcon#flushed, iclass 11, count 0 2006.201.12:44:05.20#ibcon#about to write, iclass 11, count 0 2006.201.12:44:05.20#ibcon#wrote, iclass 11, count 0 2006.201.12:44:05.20#ibcon#about to read 3, iclass 11, count 0 2006.201.12:44:05.25#ibcon#read 3, iclass 11, count 0 2006.201.12:44:05.25#ibcon#about to read 4, iclass 11, count 0 2006.201.12:44:05.25#ibcon#read 4, iclass 11, count 0 2006.201.12:44:05.25#ibcon#about to read 5, iclass 11, count 0 2006.201.12:44:05.25#ibcon#read 5, iclass 11, count 0 2006.201.12:44:05.25#ibcon#about to read 6, iclass 11, count 0 2006.201.12:44:05.25#ibcon#read 6, iclass 11, count 0 2006.201.12:44:05.25#ibcon#end of sib2, iclass 11, count 0 2006.201.12:44:05.25#ibcon#*after write, iclass 11, count 0 2006.201.12:44:05.25#ibcon#*before return 0, iclass 11, count 0 2006.201.12:44:05.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:05.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:05.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:44:05.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:44:05.25$vck44/va=2,7 2006.201.12:44:05.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.12:44:05.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.12:44:05.25#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:05.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:05.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:05.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:05.30#ibcon#enter wrdev, iclass 13, count 2 2006.201.12:44:05.30#ibcon#first serial, iclass 13, count 2 2006.201.12:44:05.30#ibcon#enter sib2, iclass 13, count 2 2006.201.12:44:05.30#ibcon#flushed, iclass 13, count 2 2006.201.12:44:05.30#ibcon#about to write, iclass 13, count 2 2006.201.12:44:05.30#ibcon#wrote, iclass 13, count 2 2006.201.12:44:05.30#ibcon#about to read 3, iclass 13, count 2 2006.201.12:44:05.32#ibcon#read 3, iclass 13, count 2 2006.201.12:44:05.32#ibcon#about to read 4, iclass 13, count 2 2006.201.12:44:05.32#ibcon#read 4, iclass 13, count 2 2006.201.12:44:05.32#ibcon#about to read 5, iclass 13, count 2 2006.201.12:44:05.32#ibcon#read 5, iclass 13, count 2 2006.201.12:44:05.32#ibcon#about to read 6, iclass 13, count 2 2006.201.12:44:05.32#ibcon#read 6, iclass 13, count 2 2006.201.12:44:05.32#ibcon#end of sib2, iclass 13, count 2 2006.201.12:44:05.32#ibcon#*mode == 0, iclass 13, count 2 2006.201.12:44:05.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.12:44:05.32#ibcon#[25=AT02-07\r\n] 2006.201.12:44:05.32#ibcon#*before write, iclass 13, count 2 2006.201.12:44:05.32#ibcon#enter sib2, iclass 13, count 2 2006.201.12:44:05.32#ibcon#flushed, iclass 13, count 2 2006.201.12:44:05.32#ibcon#about to write, iclass 13, count 2 2006.201.12:44:05.32#ibcon#wrote, iclass 13, count 2 2006.201.12:44:05.32#ibcon#about to read 3, iclass 13, count 2 2006.201.12:44:05.35#ibcon#read 3, iclass 13, count 2 2006.201.12:44:05.35#ibcon#about to read 4, iclass 13, count 2 2006.201.12:44:05.35#ibcon#read 4, iclass 13, count 2 2006.201.12:44:05.35#ibcon#about to read 5, iclass 13, count 2 2006.201.12:44:05.35#ibcon#read 5, iclass 13, count 2 2006.201.12:44:05.35#ibcon#about to read 6, iclass 13, count 2 2006.201.12:44:05.35#ibcon#read 6, iclass 13, count 2 2006.201.12:44:05.35#ibcon#end of sib2, iclass 13, count 2 2006.201.12:44:05.35#ibcon#*after write, iclass 13, count 2 2006.201.12:44:05.35#ibcon#*before return 0, iclass 13, count 2 2006.201.12:44:05.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:05.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:05.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.12:44:05.35#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:05.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:05.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:05.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:05.47#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:44:05.47#ibcon#first serial, iclass 13, count 0 2006.201.12:44:05.47#ibcon#enter sib2, iclass 13, count 0 2006.201.12:44:05.47#ibcon#flushed, iclass 13, count 0 2006.201.12:44:05.47#ibcon#about to write, iclass 13, count 0 2006.201.12:44:05.47#ibcon#wrote, iclass 13, count 0 2006.201.12:44:05.47#ibcon#about to read 3, iclass 13, count 0 2006.201.12:44:05.49#ibcon#read 3, iclass 13, count 0 2006.201.12:44:05.49#ibcon#about to read 4, iclass 13, count 0 2006.201.12:44:05.49#ibcon#read 4, iclass 13, count 0 2006.201.12:44:05.49#ibcon#about to read 5, iclass 13, count 0 2006.201.12:44:05.49#ibcon#read 5, iclass 13, count 0 2006.201.12:44:05.49#ibcon#about to read 6, iclass 13, count 0 2006.201.12:44:05.49#ibcon#read 6, iclass 13, count 0 2006.201.12:44:05.49#ibcon#end of sib2, iclass 13, count 0 2006.201.12:44:05.49#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:44:05.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:44:05.49#ibcon#[25=USB\r\n] 2006.201.12:44:05.49#ibcon#*before write, iclass 13, count 0 2006.201.12:44:05.49#ibcon#enter sib2, iclass 13, count 0 2006.201.12:44:05.49#ibcon#flushed, iclass 13, count 0 2006.201.12:44:05.49#ibcon#about to write, iclass 13, count 0 2006.201.12:44:05.49#ibcon#wrote, iclass 13, count 0 2006.201.12:44:05.49#ibcon#about to read 3, iclass 13, count 0 2006.201.12:44:05.52#ibcon#read 3, iclass 13, count 0 2006.201.12:44:05.52#ibcon#about to read 4, iclass 13, count 0 2006.201.12:44:05.52#ibcon#read 4, iclass 13, count 0 2006.201.12:44:05.52#ibcon#about to read 5, iclass 13, count 0 2006.201.12:44:05.52#ibcon#read 5, iclass 13, count 0 2006.201.12:44:05.52#ibcon#about to read 6, iclass 13, count 0 2006.201.12:44:05.52#ibcon#read 6, iclass 13, count 0 2006.201.12:44:05.52#ibcon#end of sib2, iclass 13, count 0 2006.201.12:44:05.52#ibcon#*after write, iclass 13, count 0 2006.201.12:44:05.52#ibcon#*before return 0, iclass 13, count 0 2006.201.12:44:05.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:05.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:05.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:44:05.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:44:05.52$vck44/valo=3,564.99 2006.201.12:44:05.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.12:44:05.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.12:44:05.52#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:05.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:05.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:05.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:05.52#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:44:05.52#ibcon#first serial, iclass 15, count 0 2006.201.12:44:05.52#ibcon#enter sib2, iclass 15, count 0 2006.201.12:44:05.52#ibcon#flushed, iclass 15, count 0 2006.201.12:44:05.52#ibcon#about to write, iclass 15, count 0 2006.201.12:44:05.52#ibcon#wrote, iclass 15, count 0 2006.201.12:44:05.52#ibcon#about to read 3, iclass 15, count 0 2006.201.12:44:05.54#ibcon#read 3, iclass 15, count 0 2006.201.12:44:05.54#ibcon#about to read 4, iclass 15, count 0 2006.201.12:44:05.54#ibcon#read 4, iclass 15, count 0 2006.201.12:44:05.54#ibcon#about to read 5, iclass 15, count 0 2006.201.12:44:05.54#ibcon#read 5, iclass 15, count 0 2006.201.12:44:05.54#ibcon#about to read 6, iclass 15, count 0 2006.201.12:44:05.54#ibcon#read 6, iclass 15, count 0 2006.201.12:44:05.54#ibcon#end of sib2, iclass 15, count 0 2006.201.12:44:05.54#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:44:05.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:44:05.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:44:05.54#ibcon#*before write, iclass 15, count 0 2006.201.12:44:05.54#ibcon#enter sib2, iclass 15, count 0 2006.201.12:44:05.54#ibcon#flushed, iclass 15, count 0 2006.201.12:44:05.54#ibcon#about to write, iclass 15, count 0 2006.201.12:44:05.54#ibcon#wrote, iclass 15, count 0 2006.201.12:44:05.54#ibcon#about to read 3, iclass 15, count 0 2006.201.12:44:05.59#ibcon#read 3, iclass 15, count 0 2006.201.12:44:05.59#ibcon#about to read 4, iclass 15, count 0 2006.201.12:44:05.59#ibcon#read 4, iclass 15, count 0 2006.201.12:44:05.59#ibcon#about to read 5, iclass 15, count 0 2006.201.12:44:05.59#ibcon#read 5, iclass 15, count 0 2006.201.12:44:05.59#ibcon#about to read 6, iclass 15, count 0 2006.201.12:44:05.59#ibcon#read 6, iclass 15, count 0 2006.201.12:44:05.59#ibcon#end of sib2, iclass 15, count 0 2006.201.12:44:05.59#ibcon#*after write, iclass 15, count 0 2006.201.12:44:05.59#ibcon#*before return 0, iclass 15, count 0 2006.201.12:44:05.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:05.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:05.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:44:05.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:44:05.59$vck44/va=3,8 2006.201.12:44:05.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.12:44:05.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.12:44:05.59#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:05.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:05.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:05.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:05.64#ibcon#enter wrdev, iclass 17, count 2 2006.201.12:44:05.64#ibcon#first serial, iclass 17, count 2 2006.201.12:44:05.64#ibcon#enter sib2, iclass 17, count 2 2006.201.12:44:05.64#ibcon#flushed, iclass 17, count 2 2006.201.12:44:05.64#ibcon#about to write, iclass 17, count 2 2006.201.12:44:05.64#ibcon#wrote, iclass 17, count 2 2006.201.12:44:05.64#ibcon#about to read 3, iclass 17, count 2 2006.201.12:44:05.66#ibcon#read 3, iclass 17, count 2 2006.201.12:44:05.66#ibcon#about to read 4, iclass 17, count 2 2006.201.12:44:05.66#ibcon#read 4, iclass 17, count 2 2006.201.12:44:05.66#ibcon#about to read 5, iclass 17, count 2 2006.201.12:44:05.66#ibcon#read 5, iclass 17, count 2 2006.201.12:44:05.66#ibcon#about to read 6, iclass 17, count 2 2006.201.12:44:05.66#ibcon#read 6, iclass 17, count 2 2006.201.12:44:05.66#ibcon#end of sib2, iclass 17, count 2 2006.201.12:44:05.66#ibcon#*mode == 0, iclass 17, count 2 2006.201.12:44:05.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.12:44:05.66#ibcon#[25=AT03-08\r\n] 2006.201.12:44:05.66#ibcon#*before write, iclass 17, count 2 2006.201.12:44:05.66#ibcon#enter sib2, iclass 17, count 2 2006.201.12:44:05.66#ibcon#flushed, iclass 17, count 2 2006.201.12:44:05.66#ibcon#about to write, iclass 17, count 2 2006.201.12:44:05.66#ibcon#wrote, iclass 17, count 2 2006.201.12:44:05.66#ibcon#about to read 3, iclass 17, count 2 2006.201.12:44:05.69#ibcon#read 3, iclass 17, count 2 2006.201.12:44:05.69#ibcon#about to read 4, iclass 17, count 2 2006.201.12:44:05.69#ibcon#read 4, iclass 17, count 2 2006.201.12:44:05.69#ibcon#about to read 5, iclass 17, count 2 2006.201.12:44:05.69#ibcon#read 5, iclass 17, count 2 2006.201.12:44:05.69#ibcon#about to read 6, iclass 17, count 2 2006.201.12:44:05.69#ibcon#read 6, iclass 17, count 2 2006.201.12:44:05.69#ibcon#end of sib2, iclass 17, count 2 2006.201.12:44:05.69#ibcon#*after write, iclass 17, count 2 2006.201.12:44:05.69#ibcon#*before return 0, iclass 17, count 2 2006.201.12:44:05.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:05.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:05.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.12:44:05.69#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:05.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:05.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:05.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:05.81#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:44:05.81#ibcon#first serial, iclass 17, count 0 2006.201.12:44:05.81#ibcon#enter sib2, iclass 17, count 0 2006.201.12:44:05.81#ibcon#flushed, iclass 17, count 0 2006.201.12:44:05.81#ibcon#about to write, iclass 17, count 0 2006.201.12:44:05.81#ibcon#wrote, iclass 17, count 0 2006.201.12:44:05.81#ibcon#about to read 3, iclass 17, count 0 2006.201.12:44:05.83#ibcon#read 3, iclass 17, count 0 2006.201.12:44:05.83#ibcon#about to read 4, iclass 17, count 0 2006.201.12:44:05.83#ibcon#read 4, iclass 17, count 0 2006.201.12:44:05.83#ibcon#about to read 5, iclass 17, count 0 2006.201.12:44:05.83#ibcon#read 5, iclass 17, count 0 2006.201.12:44:05.83#ibcon#about to read 6, iclass 17, count 0 2006.201.12:44:05.83#ibcon#read 6, iclass 17, count 0 2006.201.12:44:05.83#ibcon#end of sib2, iclass 17, count 0 2006.201.12:44:05.83#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:44:05.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:44:05.83#ibcon#[25=USB\r\n] 2006.201.12:44:05.83#ibcon#*before write, iclass 17, count 0 2006.201.12:44:05.83#ibcon#enter sib2, iclass 17, count 0 2006.201.12:44:05.83#ibcon#flushed, iclass 17, count 0 2006.201.12:44:05.83#ibcon#about to write, iclass 17, count 0 2006.201.12:44:05.83#ibcon#wrote, iclass 17, count 0 2006.201.12:44:05.83#ibcon#about to read 3, iclass 17, count 0 2006.201.12:44:05.86#ibcon#read 3, iclass 17, count 0 2006.201.12:44:05.86#ibcon#about to read 4, iclass 17, count 0 2006.201.12:44:05.86#ibcon#read 4, iclass 17, count 0 2006.201.12:44:05.86#ibcon#about to read 5, iclass 17, count 0 2006.201.12:44:05.86#ibcon#read 5, iclass 17, count 0 2006.201.12:44:05.86#ibcon#about to read 6, iclass 17, count 0 2006.201.12:44:05.86#ibcon#read 6, iclass 17, count 0 2006.201.12:44:05.86#ibcon#end of sib2, iclass 17, count 0 2006.201.12:44:05.86#ibcon#*after write, iclass 17, count 0 2006.201.12:44:05.86#ibcon#*before return 0, iclass 17, count 0 2006.201.12:44:05.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:05.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:05.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:44:05.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:44:05.86$vck44/valo=4,624.99 2006.201.12:44:05.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.12:44:05.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.12:44:05.86#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:05.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:05.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:05.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:05.86#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:44:05.86#ibcon#first serial, iclass 19, count 0 2006.201.12:44:05.86#ibcon#enter sib2, iclass 19, count 0 2006.201.12:44:05.86#ibcon#flushed, iclass 19, count 0 2006.201.12:44:05.86#ibcon#about to write, iclass 19, count 0 2006.201.12:44:05.86#ibcon#wrote, iclass 19, count 0 2006.201.12:44:05.86#ibcon#about to read 3, iclass 19, count 0 2006.201.12:44:05.88#ibcon#read 3, iclass 19, count 0 2006.201.12:44:05.88#ibcon#about to read 4, iclass 19, count 0 2006.201.12:44:05.88#ibcon#read 4, iclass 19, count 0 2006.201.12:44:05.88#ibcon#about to read 5, iclass 19, count 0 2006.201.12:44:05.88#ibcon#read 5, iclass 19, count 0 2006.201.12:44:05.88#ibcon#about to read 6, iclass 19, count 0 2006.201.12:44:05.88#ibcon#read 6, iclass 19, count 0 2006.201.12:44:05.88#ibcon#end of sib2, iclass 19, count 0 2006.201.12:44:05.88#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:44:05.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:44:05.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:44:05.88#ibcon#*before write, iclass 19, count 0 2006.201.12:44:05.88#ibcon#enter sib2, iclass 19, count 0 2006.201.12:44:05.88#ibcon#flushed, iclass 19, count 0 2006.201.12:44:05.88#ibcon#about to write, iclass 19, count 0 2006.201.12:44:05.88#ibcon#wrote, iclass 19, count 0 2006.201.12:44:05.88#ibcon#about to read 3, iclass 19, count 0 2006.201.12:44:05.93#ibcon#read 3, iclass 19, count 0 2006.201.12:44:05.93#ibcon#about to read 4, iclass 19, count 0 2006.201.12:44:05.93#ibcon#read 4, iclass 19, count 0 2006.201.12:44:05.93#ibcon#about to read 5, iclass 19, count 0 2006.201.12:44:05.93#ibcon#read 5, iclass 19, count 0 2006.201.12:44:05.93#ibcon#about to read 6, iclass 19, count 0 2006.201.12:44:05.93#ibcon#read 6, iclass 19, count 0 2006.201.12:44:05.93#ibcon#end of sib2, iclass 19, count 0 2006.201.12:44:05.93#ibcon#*after write, iclass 19, count 0 2006.201.12:44:05.93#ibcon#*before return 0, iclass 19, count 0 2006.201.12:44:05.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:05.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:05.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:44:05.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:44:05.93$vck44/va=4,7 2006.201.12:44:05.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.12:44:05.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.12:44:05.93#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:05.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:05.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:05.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:05.98#ibcon#enter wrdev, iclass 21, count 2 2006.201.12:44:05.98#ibcon#first serial, iclass 21, count 2 2006.201.12:44:05.98#ibcon#enter sib2, iclass 21, count 2 2006.201.12:44:05.98#ibcon#flushed, iclass 21, count 2 2006.201.12:44:05.98#ibcon#about to write, iclass 21, count 2 2006.201.12:44:05.98#ibcon#wrote, iclass 21, count 2 2006.201.12:44:05.98#ibcon#about to read 3, iclass 21, count 2 2006.201.12:44:06.00#ibcon#read 3, iclass 21, count 2 2006.201.12:44:06.00#ibcon#about to read 4, iclass 21, count 2 2006.201.12:44:06.00#ibcon#read 4, iclass 21, count 2 2006.201.12:44:06.00#ibcon#about to read 5, iclass 21, count 2 2006.201.12:44:06.00#ibcon#read 5, iclass 21, count 2 2006.201.12:44:06.00#ibcon#about to read 6, iclass 21, count 2 2006.201.12:44:06.00#ibcon#read 6, iclass 21, count 2 2006.201.12:44:06.00#ibcon#end of sib2, iclass 21, count 2 2006.201.12:44:06.00#ibcon#*mode == 0, iclass 21, count 2 2006.201.12:44:06.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.12:44:06.00#ibcon#[25=AT04-07\r\n] 2006.201.12:44:06.00#ibcon#*before write, iclass 21, count 2 2006.201.12:44:06.00#ibcon#enter sib2, iclass 21, count 2 2006.201.12:44:06.00#ibcon#flushed, iclass 21, count 2 2006.201.12:44:06.00#ibcon#about to write, iclass 21, count 2 2006.201.12:44:06.00#ibcon#wrote, iclass 21, count 2 2006.201.12:44:06.00#ibcon#about to read 3, iclass 21, count 2 2006.201.12:44:06.03#ibcon#read 3, iclass 21, count 2 2006.201.12:44:06.03#ibcon#about to read 4, iclass 21, count 2 2006.201.12:44:06.03#ibcon#read 4, iclass 21, count 2 2006.201.12:44:06.03#ibcon#about to read 5, iclass 21, count 2 2006.201.12:44:06.03#ibcon#read 5, iclass 21, count 2 2006.201.12:44:06.03#ibcon#about to read 6, iclass 21, count 2 2006.201.12:44:06.03#ibcon#read 6, iclass 21, count 2 2006.201.12:44:06.03#ibcon#end of sib2, iclass 21, count 2 2006.201.12:44:06.03#ibcon#*after write, iclass 21, count 2 2006.201.12:44:06.03#ibcon#*before return 0, iclass 21, count 2 2006.201.12:44:06.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:06.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:06.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.12:44:06.03#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:06.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:06.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:06.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:06.15#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:44:06.15#ibcon#first serial, iclass 21, count 0 2006.201.12:44:06.15#ibcon#enter sib2, iclass 21, count 0 2006.201.12:44:06.15#ibcon#flushed, iclass 21, count 0 2006.201.12:44:06.15#ibcon#about to write, iclass 21, count 0 2006.201.12:44:06.15#ibcon#wrote, iclass 21, count 0 2006.201.12:44:06.15#ibcon#about to read 3, iclass 21, count 0 2006.201.12:44:06.17#ibcon#read 3, iclass 21, count 0 2006.201.12:44:06.17#ibcon#about to read 4, iclass 21, count 0 2006.201.12:44:06.17#ibcon#read 4, iclass 21, count 0 2006.201.12:44:06.17#ibcon#about to read 5, iclass 21, count 0 2006.201.12:44:06.17#ibcon#read 5, iclass 21, count 0 2006.201.12:44:06.17#ibcon#about to read 6, iclass 21, count 0 2006.201.12:44:06.17#ibcon#read 6, iclass 21, count 0 2006.201.12:44:06.17#ibcon#end of sib2, iclass 21, count 0 2006.201.12:44:06.17#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:44:06.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:44:06.17#ibcon#[25=USB\r\n] 2006.201.12:44:06.17#ibcon#*before write, iclass 21, count 0 2006.201.12:44:06.17#ibcon#enter sib2, iclass 21, count 0 2006.201.12:44:06.17#ibcon#flushed, iclass 21, count 0 2006.201.12:44:06.17#ibcon#about to write, iclass 21, count 0 2006.201.12:44:06.17#ibcon#wrote, iclass 21, count 0 2006.201.12:44:06.17#ibcon#about to read 3, iclass 21, count 0 2006.201.12:44:06.20#ibcon#read 3, iclass 21, count 0 2006.201.12:44:06.20#ibcon#about to read 4, iclass 21, count 0 2006.201.12:44:06.20#ibcon#read 4, iclass 21, count 0 2006.201.12:44:06.20#ibcon#about to read 5, iclass 21, count 0 2006.201.12:44:06.20#ibcon#read 5, iclass 21, count 0 2006.201.12:44:06.20#ibcon#about to read 6, iclass 21, count 0 2006.201.12:44:06.20#ibcon#read 6, iclass 21, count 0 2006.201.12:44:06.20#ibcon#end of sib2, iclass 21, count 0 2006.201.12:44:06.20#ibcon#*after write, iclass 21, count 0 2006.201.12:44:06.20#ibcon#*before return 0, iclass 21, count 0 2006.201.12:44:06.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:06.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:06.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:44:06.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:44:06.20$vck44/valo=5,734.99 2006.201.12:44:06.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.12:44:06.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.12:44:06.20#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:06.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:44:06.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:44:06.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:44:06.20#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:44:06.20#ibcon#first serial, iclass 23, count 0 2006.201.12:44:06.20#ibcon#enter sib2, iclass 23, count 0 2006.201.12:44:06.20#ibcon#flushed, iclass 23, count 0 2006.201.12:44:06.20#ibcon#about to write, iclass 23, count 0 2006.201.12:44:06.20#ibcon#wrote, iclass 23, count 0 2006.201.12:44:06.20#ibcon#about to read 3, iclass 23, count 0 2006.201.12:44:06.22#ibcon#read 3, iclass 23, count 0 2006.201.12:44:06.22#ibcon#about to read 4, iclass 23, count 0 2006.201.12:44:06.22#ibcon#read 4, iclass 23, count 0 2006.201.12:44:06.22#ibcon#about to read 5, iclass 23, count 0 2006.201.12:44:06.22#ibcon#read 5, iclass 23, count 0 2006.201.12:44:06.22#ibcon#about to read 6, iclass 23, count 0 2006.201.12:44:06.22#ibcon#read 6, iclass 23, count 0 2006.201.12:44:06.22#ibcon#end of sib2, iclass 23, count 0 2006.201.12:44:06.22#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:44:06.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:44:06.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:44:06.22#ibcon#*before write, iclass 23, count 0 2006.201.12:44:06.22#ibcon#enter sib2, iclass 23, count 0 2006.201.12:44:06.22#ibcon#flushed, iclass 23, count 0 2006.201.12:44:06.22#ibcon#about to write, iclass 23, count 0 2006.201.12:44:06.22#ibcon#wrote, iclass 23, count 0 2006.201.12:44:06.22#ibcon#about to read 3, iclass 23, count 0 2006.201.12:44:06.26#ibcon#read 3, iclass 23, count 0 2006.201.12:44:06.26#ibcon#about to read 4, iclass 23, count 0 2006.201.12:44:06.26#ibcon#read 4, iclass 23, count 0 2006.201.12:44:06.26#ibcon#about to read 5, iclass 23, count 0 2006.201.12:44:06.26#ibcon#read 5, iclass 23, count 0 2006.201.12:44:06.26#ibcon#about to read 6, iclass 23, count 0 2006.201.12:44:06.26#ibcon#read 6, iclass 23, count 0 2006.201.12:44:06.26#ibcon#end of sib2, iclass 23, count 0 2006.201.12:44:06.26#ibcon#*after write, iclass 23, count 0 2006.201.12:44:06.26#ibcon#*before return 0, iclass 23, count 0 2006.201.12:44:06.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:44:06.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.12:44:06.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:44:06.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:44:06.26$vck44/va=5,4 2006.201.12:44:06.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.12:44:06.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.12:44:06.26#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:06.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:44:06.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:44:06.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:44:06.32#ibcon#enter wrdev, iclass 25, count 2 2006.201.12:44:06.32#ibcon#first serial, iclass 25, count 2 2006.201.12:44:06.32#ibcon#enter sib2, iclass 25, count 2 2006.201.12:44:06.32#ibcon#flushed, iclass 25, count 2 2006.201.12:44:06.32#ibcon#about to write, iclass 25, count 2 2006.201.12:44:06.32#ibcon#wrote, iclass 25, count 2 2006.201.12:44:06.32#ibcon#about to read 3, iclass 25, count 2 2006.201.12:44:06.34#ibcon#read 3, iclass 25, count 2 2006.201.12:44:06.34#ibcon#about to read 4, iclass 25, count 2 2006.201.12:44:06.34#ibcon#read 4, iclass 25, count 2 2006.201.12:44:06.34#ibcon#about to read 5, iclass 25, count 2 2006.201.12:44:06.34#ibcon#read 5, iclass 25, count 2 2006.201.12:44:06.34#ibcon#about to read 6, iclass 25, count 2 2006.201.12:44:06.34#ibcon#read 6, iclass 25, count 2 2006.201.12:44:06.34#ibcon#end of sib2, iclass 25, count 2 2006.201.12:44:06.34#ibcon#*mode == 0, iclass 25, count 2 2006.201.12:44:06.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.12:44:06.34#ibcon#[25=AT05-04\r\n] 2006.201.12:44:06.34#ibcon#*before write, iclass 25, count 2 2006.201.12:44:06.34#ibcon#enter sib2, iclass 25, count 2 2006.201.12:44:06.34#ibcon#flushed, iclass 25, count 2 2006.201.12:44:06.34#ibcon#about to write, iclass 25, count 2 2006.201.12:44:06.34#ibcon#wrote, iclass 25, count 2 2006.201.12:44:06.34#ibcon#about to read 3, iclass 25, count 2 2006.201.12:44:06.37#ibcon#read 3, iclass 25, count 2 2006.201.12:44:06.37#ibcon#about to read 4, iclass 25, count 2 2006.201.12:44:06.37#ibcon#read 4, iclass 25, count 2 2006.201.12:44:06.37#ibcon#about to read 5, iclass 25, count 2 2006.201.12:44:06.37#ibcon#read 5, iclass 25, count 2 2006.201.12:44:06.37#ibcon#about to read 6, iclass 25, count 2 2006.201.12:44:06.37#ibcon#read 6, iclass 25, count 2 2006.201.12:44:06.37#ibcon#end of sib2, iclass 25, count 2 2006.201.12:44:06.37#ibcon#*after write, iclass 25, count 2 2006.201.12:44:06.37#ibcon#*before return 0, iclass 25, count 2 2006.201.12:44:06.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:44:06.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.12:44:06.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.12:44:06.37#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:06.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:44:06.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:44:06.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:44:06.49#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:44:06.49#ibcon#first serial, iclass 25, count 0 2006.201.12:44:06.49#ibcon#enter sib2, iclass 25, count 0 2006.201.12:44:06.49#ibcon#flushed, iclass 25, count 0 2006.201.12:44:06.49#ibcon#about to write, iclass 25, count 0 2006.201.12:44:06.49#ibcon#wrote, iclass 25, count 0 2006.201.12:44:06.49#ibcon#about to read 3, iclass 25, count 0 2006.201.12:44:06.51#ibcon#read 3, iclass 25, count 0 2006.201.12:44:06.51#ibcon#about to read 4, iclass 25, count 0 2006.201.12:44:06.51#ibcon#read 4, iclass 25, count 0 2006.201.12:44:06.51#ibcon#about to read 5, iclass 25, count 0 2006.201.12:44:06.51#ibcon#read 5, iclass 25, count 0 2006.201.12:44:06.51#ibcon#about to read 6, iclass 25, count 0 2006.201.12:44:06.51#ibcon#read 6, iclass 25, count 0 2006.201.12:44:06.51#ibcon#end of sib2, iclass 25, count 0 2006.201.12:44:06.51#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:44:06.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:44:06.51#ibcon#[25=USB\r\n] 2006.201.12:44:06.51#ibcon#*before write, iclass 25, count 0 2006.201.12:44:06.51#ibcon#enter sib2, iclass 25, count 0 2006.201.12:44:06.51#ibcon#flushed, iclass 25, count 0 2006.201.12:44:06.51#ibcon#about to write, iclass 25, count 0 2006.201.12:44:06.51#ibcon#wrote, iclass 25, count 0 2006.201.12:44:06.51#ibcon#about to read 3, iclass 25, count 0 2006.201.12:44:06.54#ibcon#read 3, iclass 25, count 0 2006.201.12:44:06.54#ibcon#about to read 4, iclass 25, count 0 2006.201.12:44:06.54#ibcon#read 4, iclass 25, count 0 2006.201.12:44:06.54#ibcon#about to read 5, iclass 25, count 0 2006.201.12:44:06.54#ibcon#read 5, iclass 25, count 0 2006.201.12:44:06.54#ibcon#about to read 6, iclass 25, count 0 2006.201.12:44:06.54#ibcon#read 6, iclass 25, count 0 2006.201.12:44:06.54#ibcon#end of sib2, iclass 25, count 0 2006.201.12:44:06.54#ibcon#*after write, iclass 25, count 0 2006.201.12:44:06.54#ibcon#*before return 0, iclass 25, count 0 2006.201.12:44:06.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:44:06.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.12:44:06.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:44:06.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:44:06.54$vck44/valo=6,814.99 2006.201.12:44:06.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.12:44:06.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.12:44:06.54#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:06.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:06.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:06.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:06.54#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:44:06.54#ibcon#first serial, iclass 27, count 0 2006.201.12:44:06.54#ibcon#enter sib2, iclass 27, count 0 2006.201.12:44:06.54#ibcon#flushed, iclass 27, count 0 2006.201.12:44:06.54#ibcon#about to write, iclass 27, count 0 2006.201.12:44:06.54#ibcon#wrote, iclass 27, count 0 2006.201.12:44:06.54#ibcon#about to read 3, iclass 27, count 0 2006.201.12:44:06.56#ibcon#read 3, iclass 27, count 0 2006.201.12:44:06.56#ibcon#about to read 4, iclass 27, count 0 2006.201.12:44:06.56#ibcon#read 4, iclass 27, count 0 2006.201.12:44:06.56#ibcon#about to read 5, iclass 27, count 0 2006.201.12:44:06.56#ibcon#read 5, iclass 27, count 0 2006.201.12:44:06.56#ibcon#about to read 6, iclass 27, count 0 2006.201.12:44:06.56#ibcon#read 6, iclass 27, count 0 2006.201.12:44:06.56#ibcon#end of sib2, iclass 27, count 0 2006.201.12:44:06.56#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:44:06.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:44:06.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:44:06.56#ibcon#*before write, iclass 27, count 0 2006.201.12:44:06.56#ibcon#enter sib2, iclass 27, count 0 2006.201.12:44:06.56#ibcon#flushed, iclass 27, count 0 2006.201.12:44:06.56#ibcon#about to write, iclass 27, count 0 2006.201.12:44:06.56#ibcon#wrote, iclass 27, count 0 2006.201.12:44:06.56#ibcon#about to read 3, iclass 27, count 0 2006.201.12:44:06.61#ibcon#read 3, iclass 27, count 0 2006.201.12:44:06.61#ibcon#about to read 4, iclass 27, count 0 2006.201.12:44:06.61#ibcon#read 4, iclass 27, count 0 2006.201.12:44:06.61#ibcon#about to read 5, iclass 27, count 0 2006.201.12:44:06.61#ibcon#read 5, iclass 27, count 0 2006.201.12:44:06.61#ibcon#about to read 6, iclass 27, count 0 2006.201.12:44:06.61#ibcon#read 6, iclass 27, count 0 2006.201.12:44:06.61#ibcon#end of sib2, iclass 27, count 0 2006.201.12:44:06.61#ibcon#*after write, iclass 27, count 0 2006.201.12:44:06.61#ibcon#*before return 0, iclass 27, count 0 2006.201.12:44:06.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:06.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:06.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:44:06.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:44:06.61$vck44/va=6,5 2006.201.12:44:06.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.12:44:06.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.12:44:06.61#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:06.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:06.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:06.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:06.66#ibcon#enter wrdev, iclass 29, count 2 2006.201.12:44:06.66#ibcon#first serial, iclass 29, count 2 2006.201.12:44:06.66#ibcon#enter sib2, iclass 29, count 2 2006.201.12:44:06.66#ibcon#flushed, iclass 29, count 2 2006.201.12:44:06.66#ibcon#about to write, iclass 29, count 2 2006.201.12:44:06.66#ibcon#wrote, iclass 29, count 2 2006.201.12:44:06.66#ibcon#about to read 3, iclass 29, count 2 2006.201.12:44:06.68#ibcon#read 3, iclass 29, count 2 2006.201.12:44:06.68#ibcon#about to read 4, iclass 29, count 2 2006.201.12:44:06.68#ibcon#read 4, iclass 29, count 2 2006.201.12:44:06.68#ibcon#about to read 5, iclass 29, count 2 2006.201.12:44:06.68#ibcon#read 5, iclass 29, count 2 2006.201.12:44:06.68#ibcon#about to read 6, iclass 29, count 2 2006.201.12:44:06.68#ibcon#read 6, iclass 29, count 2 2006.201.12:44:06.68#ibcon#end of sib2, iclass 29, count 2 2006.201.12:44:06.68#ibcon#*mode == 0, iclass 29, count 2 2006.201.12:44:06.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.12:44:06.68#ibcon#[25=AT06-05\r\n] 2006.201.12:44:06.68#ibcon#*before write, iclass 29, count 2 2006.201.12:44:06.68#ibcon#enter sib2, iclass 29, count 2 2006.201.12:44:06.68#ibcon#flushed, iclass 29, count 2 2006.201.12:44:06.68#ibcon#about to write, iclass 29, count 2 2006.201.12:44:06.68#ibcon#wrote, iclass 29, count 2 2006.201.12:44:06.68#ibcon#about to read 3, iclass 29, count 2 2006.201.12:44:06.71#ibcon#read 3, iclass 29, count 2 2006.201.12:44:06.71#ibcon#about to read 4, iclass 29, count 2 2006.201.12:44:06.71#ibcon#read 4, iclass 29, count 2 2006.201.12:44:06.71#ibcon#about to read 5, iclass 29, count 2 2006.201.12:44:06.71#ibcon#read 5, iclass 29, count 2 2006.201.12:44:06.71#ibcon#about to read 6, iclass 29, count 2 2006.201.12:44:06.71#ibcon#read 6, iclass 29, count 2 2006.201.12:44:06.71#ibcon#end of sib2, iclass 29, count 2 2006.201.12:44:06.71#ibcon#*after write, iclass 29, count 2 2006.201.12:44:06.71#ibcon#*before return 0, iclass 29, count 2 2006.201.12:44:06.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:06.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:06.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.12:44:06.71#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:06.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:06.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:06.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:06.83#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:44:06.83#ibcon#first serial, iclass 29, count 0 2006.201.12:44:06.83#ibcon#enter sib2, iclass 29, count 0 2006.201.12:44:06.83#ibcon#flushed, iclass 29, count 0 2006.201.12:44:06.83#ibcon#about to write, iclass 29, count 0 2006.201.12:44:06.83#ibcon#wrote, iclass 29, count 0 2006.201.12:44:06.83#ibcon#about to read 3, iclass 29, count 0 2006.201.12:44:06.85#ibcon#read 3, iclass 29, count 0 2006.201.12:44:06.85#ibcon#about to read 4, iclass 29, count 0 2006.201.12:44:06.85#ibcon#read 4, iclass 29, count 0 2006.201.12:44:06.85#ibcon#about to read 5, iclass 29, count 0 2006.201.12:44:06.85#ibcon#read 5, iclass 29, count 0 2006.201.12:44:06.85#ibcon#about to read 6, iclass 29, count 0 2006.201.12:44:06.85#ibcon#read 6, iclass 29, count 0 2006.201.12:44:06.85#ibcon#end of sib2, iclass 29, count 0 2006.201.12:44:06.85#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:44:06.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:44:06.85#ibcon#[25=USB\r\n] 2006.201.12:44:06.85#ibcon#*before write, iclass 29, count 0 2006.201.12:44:06.85#ibcon#enter sib2, iclass 29, count 0 2006.201.12:44:06.85#ibcon#flushed, iclass 29, count 0 2006.201.12:44:06.85#ibcon#about to write, iclass 29, count 0 2006.201.12:44:06.85#ibcon#wrote, iclass 29, count 0 2006.201.12:44:06.85#ibcon#about to read 3, iclass 29, count 0 2006.201.12:44:06.88#ibcon#read 3, iclass 29, count 0 2006.201.12:44:06.88#ibcon#about to read 4, iclass 29, count 0 2006.201.12:44:06.88#ibcon#read 4, iclass 29, count 0 2006.201.12:44:06.88#ibcon#about to read 5, iclass 29, count 0 2006.201.12:44:06.88#ibcon#read 5, iclass 29, count 0 2006.201.12:44:06.88#ibcon#about to read 6, iclass 29, count 0 2006.201.12:44:06.88#ibcon#read 6, iclass 29, count 0 2006.201.12:44:06.88#ibcon#end of sib2, iclass 29, count 0 2006.201.12:44:06.88#ibcon#*after write, iclass 29, count 0 2006.201.12:44:06.88#ibcon#*before return 0, iclass 29, count 0 2006.201.12:44:06.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:06.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:06.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:44:06.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:44:06.88$vck44/valo=7,864.99 2006.201.12:44:06.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.12:44:06.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.12:44:06.88#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:06.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:06.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:06.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:06.88#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:44:06.88#ibcon#first serial, iclass 31, count 0 2006.201.12:44:06.88#ibcon#enter sib2, iclass 31, count 0 2006.201.12:44:06.88#ibcon#flushed, iclass 31, count 0 2006.201.12:44:06.88#ibcon#about to write, iclass 31, count 0 2006.201.12:44:06.88#ibcon#wrote, iclass 31, count 0 2006.201.12:44:06.88#ibcon#about to read 3, iclass 31, count 0 2006.201.12:44:06.90#ibcon#read 3, iclass 31, count 0 2006.201.12:44:06.90#ibcon#about to read 4, iclass 31, count 0 2006.201.12:44:06.90#ibcon#read 4, iclass 31, count 0 2006.201.12:44:06.90#ibcon#about to read 5, iclass 31, count 0 2006.201.12:44:06.90#ibcon#read 5, iclass 31, count 0 2006.201.12:44:06.90#ibcon#about to read 6, iclass 31, count 0 2006.201.12:44:06.90#ibcon#read 6, iclass 31, count 0 2006.201.12:44:06.90#ibcon#end of sib2, iclass 31, count 0 2006.201.12:44:06.90#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:44:06.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:44:06.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:44:06.90#ibcon#*before write, iclass 31, count 0 2006.201.12:44:06.90#ibcon#enter sib2, iclass 31, count 0 2006.201.12:44:06.90#ibcon#flushed, iclass 31, count 0 2006.201.12:44:06.90#ibcon#about to write, iclass 31, count 0 2006.201.12:44:06.90#ibcon#wrote, iclass 31, count 0 2006.201.12:44:06.90#ibcon#about to read 3, iclass 31, count 0 2006.201.12:44:06.94#ibcon#read 3, iclass 31, count 0 2006.201.12:44:06.94#ibcon#about to read 4, iclass 31, count 0 2006.201.12:44:06.94#ibcon#read 4, iclass 31, count 0 2006.201.12:44:06.94#ibcon#about to read 5, iclass 31, count 0 2006.201.12:44:06.94#ibcon#read 5, iclass 31, count 0 2006.201.12:44:06.94#ibcon#about to read 6, iclass 31, count 0 2006.201.12:44:06.94#ibcon#read 6, iclass 31, count 0 2006.201.12:44:06.94#ibcon#end of sib2, iclass 31, count 0 2006.201.12:44:06.94#ibcon#*after write, iclass 31, count 0 2006.201.12:44:06.94#ibcon#*before return 0, iclass 31, count 0 2006.201.12:44:06.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:06.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:06.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:44:06.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:44:06.94$vck44/va=7,5 2006.201.12:44:06.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.12:44:06.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.12:44:06.94#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:06.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:07.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:07.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:07.00#ibcon#enter wrdev, iclass 33, count 2 2006.201.12:44:07.00#ibcon#first serial, iclass 33, count 2 2006.201.12:44:07.00#ibcon#enter sib2, iclass 33, count 2 2006.201.12:44:07.00#ibcon#flushed, iclass 33, count 2 2006.201.12:44:07.00#ibcon#about to write, iclass 33, count 2 2006.201.12:44:07.00#ibcon#wrote, iclass 33, count 2 2006.201.12:44:07.00#ibcon#about to read 3, iclass 33, count 2 2006.201.12:44:07.02#ibcon#read 3, iclass 33, count 2 2006.201.12:44:07.02#ibcon#about to read 4, iclass 33, count 2 2006.201.12:44:07.02#ibcon#read 4, iclass 33, count 2 2006.201.12:44:07.02#ibcon#about to read 5, iclass 33, count 2 2006.201.12:44:07.02#ibcon#read 5, iclass 33, count 2 2006.201.12:44:07.02#ibcon#about to read 6, iclass 33, count 2 2006.201.12:44:07.02#ibcon#read 6, iclass 33, count 2 2006.201.12:44:07.02#ibcon#end of sib2, iclass 33, count 2 2006.201.12:44:07.02#ibcon#*mode == 0, iclass 33, count 2 2006.201.12:44:07.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.12:44:07.02#ibcon#[25=AT07-05\r\n] 2006.201.12:44:07.02#ibcon#*before write, iclass 33, count 2 2006.201.12:44:07.02#ibcon#enter sib2, iclass 33, count 2 2006.201.12:44:07.02#ibcon#flushed, iclass 33, count 2 2006.201.12:44:07.02#ibcon#about to write, iclass 33, count 2 2006.201.12:44:07.02#ibcon#wrote, iclass 33, count 2 2006.201.12:44:07.02#ibcon#about to read 3, iclass 33, count 2 2006.201.12:44:07.05#ibcon#read 3, iclass 33, count 2 2006.201.12:44:07.05#ibcon#about to read 4, iclass 33, count 2 2006.201.12:44:07.05#ibcon#read 4, iclass 33, count 2 2006.201.12:44:07.05#ibcon#about to read 5, iclass 33, count 2 2006.201.12:44:07.05#ibcon#read 5, iclass 33, count 2 2006.201.12:44:07.05#ibcon#about to read 6, iclass 33, count 2 2006.201.12:44:07.05#ibcon#read 6, iclass 33, count 2 2006.201.12:44:07.05#ibcon#end of sib2, iclass 33, count 2 2006.201.12:44:07.05#ibcon#*after write, iclass 33, count 2 2006.201.12:44:07.05#ibcon#*before return 0, iclass 33, count 2 2006.201.12:44:07.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:07.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:07.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.12:44:07.05#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:07.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:07.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:07.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:07.17#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:44:07.17#ibcon#first serial, iclass 33, count 0 2006.201.12:44:07.17#ibcon#enter sib2, iclass 33, count 0 2006.201.12:44:07.17#ibcon#flushed, iclass 33, count 0 2006.201.12:44:07.17#ibcon#about to write, iclass 33, count 0 2006.201.12:44:07.17#ibcon#wrote, iclass 33, count 0 2006.201.12:44:07.17#ibcon#about to read 3, iclass 33, count 0 2006.201.12:44:07.19#ibcon#read 3, iclass 33, count 0 2006.201.12:44:07.19#ibcon#about to read 4, iclass 33, count 0 2006.201.12:44:07.19#ibcon#read 4, iclass 33, count 0 2006.201.12:44:07.19#ibcon#about to read 5, iclass 33, count 0 2006.201.12:44:07.19#ibcon#read 5, iclass 33, count 0 2006.201.12:44:07.19#ibcon#about to read 6, iclass 33, count 0 2006.201.12:44:07.19#ibcon#read 6, iclass 33, count 0 2006.201.12:44:07.19#ibcon#end of sib2, iclass 33, count 0 2006.201.12:44:07.19#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:44:07.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:44:07.19#ibcon#[25=USB\r\n] 2006.201.12:44:07.19#ibcon#*before write, iclass 33, count 0 2006.201.12:44:07.19#ibcon#enter sib2, iclass 33, count 0 2006.201.12:44:07.19#ibcon#flushed, iclass 33, count 0 2006.201.12:44:07.19#ibcon#about to write, iclass 33, count 0 2006.201.12:44:07.19#ibcon#wrote, iclass 33, count 0 2006.201.12:44:07.19#ibcon#about to read 3, iclass 33, count 0 2006.201.12:44:07.22#ibcon#read 3, iclass 33, count 0 2006.201.12:44:07.22#ibcon#about to read 4, iclass 33, count 0 2006.201.12:44:07.22#ibcon#read 4, iclass 33, count 0 2006.201.12:44:07.22#ibcon#about to read 5, iclass 33, count 0 2006.201.12:44:07.22#ibcon#read 5, iclass 33, count 0 2006.201.12:44:07.22#ibcon#about to read 6, iclass 33, count 0 2006.201.12:44:07.22#ibcon#read 6, iclass 33, count 0 2006.201.12:44:07.22#ibcon#end of sib2, iclass 33, count 0 2006.201.12:44:07.22#ibcon#*after write, iclass 33, count 0 2006.201.12:44:07.22#ibcon#*before return 0, iclass 33, count 0 2006.201.12:44:07.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:07.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:07.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:44:07.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:44:07.22$vck44/valo=8,884.99 2006.201.12:44:07.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.12:44:07.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.12:44:07.22#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:07.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:07.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:07.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:07.22#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:44:07.22#ibcon#first serial, iclass 35, count 0 2006.201.12:44:07.22#ibcon#enter sib2, iclass 35, count 0 2006.201.12:44:07.22#ibcon#flushed, iclass 35, count 0 2006.201.12:44:07.22#ibcon#about to write, iclass 35, count 0 2006.201.12:44:07.22#ibcon#wrote, iclass 35, count 0 2006.201.12:44:07.22#ibcon#about to read 3, iclass 35, count 0 2006.201.12:44:07.24#ibcon#read 3, iclass 35, count 0 2006.201.12:44:07.24#ibcon#about to read 4, iclass 35, count 0 2006.201.12:44:07.24#ibcon#read 4, iclass 35, count 0 2006.201.12:44:07.24#ibcon#about to read 5, iclass 35, count 0 2006.201.12:44:07.24#ibcon#read 5, iclass 35, count 0 2006.201.12:44:07.24#ibcon#about to read 6, iclass 35, count 0 2006.201.12:44:07.24#ibcon#read 6, iclass 35, count 0 2006.201.12:44:07.24#ibcon#end of sib2, iclass 35, count 0 2006.201.12:44:07.24#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:44:07.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:44:07.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:44:07.24#ibcon#*before write, iclass 35, count 0 2006.201.12:44:07.24#ibcon#enter sib2, iclass 35, count 0 2006.201.12:44:07.24#ibcon#flushed, iclass 35, count 0 2006.201.12:44:07.24#ibcon#about to write, iclass 35, count 0 2006.201.12:44:07.24#ibcon#wrote, iclass 35, count 0 2006.201.12:44:07.24#ibcon#about to read 3, iclass 35, count 0 2006.201.12:44:07.28#ibcon#read 3, iclass 35, count 0 2006.201.12:44:07.28#ibcon#about to read 4, iclass 35, count 0 2006.201.12:44:07.28#ibcon#read 4, iclass 35, count 0 2006.201.12:44:07.28#ibcon#about to read 5, iclass 35, count 0 2006.201.12:44:07.28#ibcon#read 5, iclass 35, count 0 2006.201.12:44:07.28#ibcon#about to read 6, iclass 35, count 0 2006.201.12:44:07.28#ibcon#read 6, iclass 35, count 0 2006.201.12:44:07.28#ibcon#end of sib2, iclass 35, count 0 2006.201.12:44:07.28#ibcon#*after write, iclass 35, count 0 2006.201.12:44:07.28#ibcon#*before return 0, iclass 35, count 0 2006.201.12:44:07.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:07.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:07.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:44:07.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:44:07.28$vck44/va=8,4 2006.201.12:44:07.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.12:44:07.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.12:44:07.28#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:07.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:07.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:07.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:07.34#ibcon#enter wrdev, iclass 37, count 2 2006.201.12:44:07.34#ibcon#first serial, iclass 37, count 2 2006.201.12:44:07.34#ibcon#enter sib2, iclass 37, count 2 2006.201.12:44:07.34#ibcon#flushed, iclass 37, count 2 2006.201.12:44:07.34#ibcon#about to write, iclass 37, count 2 2006.201.12:44:07.34#ibcon#wrote, iclass 37, count 2 2006.201.12:44:07.34#ibcon#about to read 3, iclass 37, count 2 2006.201.12:44:07.36#ibcon#read 3, iclass 37, count 2 2006.201.12:44:07.36#ibcon#about to read 4, iclass 37, count 2 2006.201.12:44:07.36#ibcon#read 4, iclass 37, count 2 2006.201.12:44:07.36#ibcon#about to read 5, iclass 37, count 2 2006.201.12:44:07.36#ibcon#read 5, iclass 37, count 2 2006.201.12:44:07.36#ibcon#about to read 6, iclass 37, count 2 2006.201.12:44:07.36#ibcon#read 6, iclass 37, count 2 2006.201.12:44:07.36#ibcon#end of sib2, iclass 37, count 2 2006.201.12:44:07.36#ibcon#*mode == 0, iclass 37, count 2 2006.201.12:44:07.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.12:44:07.36#ibcon#[25=AT08-04\r\n] 2006.201.12:44:07.36#ibcon#*before write, iclass 37, count 2 2006.201.12:44:07.36#ibcon#enter sib2, iclass 37, count 2 2006.201.12:44:07.36#ibcon#flushed, iclass 37, count 2 2006.201.12:44:07.36#ibcon#about to write, iclass 37, count 2 2006.201.12:44:07.36#ibcon#wrote, iclass 37, count 2 2006.201.12:44:07.36#ibcon#about to read 3, iclass 37, count 2 2006.201.12:44:07.39#ibcon#read 3, iclass 37, count 2 2006.201.12:44:07.39#ibcon#about to read 4, iclass 37, count 2 2006.201.12:44:07.39#ibcon#read 4, iclass 37, count 2 2006.201.12:44:07.39#ibcon#about to read 5, iclass 37, count 2 2006.201.12:44:07.39#ibcon#read 5, iclass 37, count 2 2006.201.12:44:07.39#ibcon#about to read 6, iclass 37, count 2 2006.201.12:44:07.39#ibcon#read 6, iclass 37, count 2 2006.201.12:44:07.39#ibcon#end of sib2, iclass 37, count 2 2006.201.12:44:07.39#ibcon#*after write, iclass 37, count 2 2006.201.12:44:07.39#ibcon#*before return 0, iclass 37, count 2 2006.201.12:44:07.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:07.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:07.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.12:44:07.39#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:07.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:07.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:07.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:07.51#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:44:07.51#ibcon#first serial, iclass 37, count 0 2006.201.12:44:07.51#ibcon#enter sib2, iclass 37, count 0 2006.201.12:44:07.51#ibcon#flushed, iclass 37, count 0 2006.201.12:44:07.51#ibcon#about to write, iclass 37, count 0 2006.201.12:44:07.51#ibcon#wrote, iclass 37, count 0 2006.201.12:44:07.51#ibcon#about to read 3, iclass 37, count 0 2006.201.12:44:07.53#ibcon#read 3, iclass 37, count 0 2006.201.12:44:07.53#ibcon#about to read 4, iclass 37, count 0 2006.201.12:44:07.53#ibcon#read 4, iclass 37, count 0 2006.201.12:44:07.53#ibcon#about to read 5, iclass 37, count 0 2006.201.12:44:07.53#ibcon#read 5, iclass 37, count 0 2006.201.12:44:07.53#ibcon#about to read 6, iclass 37, count 0 2006.201.12:44:07.53#ibcon#read 6, iclass 37, count 0 2006.201.12:44:07.53#ibcon#end of sib2, iclass 37, count 0 2006.201.12:44:07.53#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:44:07.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:44:07.53#ibcon#[25=USB\r\n] 2006.201.12:44:07.53#ibcon#*before write, iclass 37, count 0 2006.201.12:44:07.53#ibcon#enter sib2, iclass 37, count 0 2006.201.12:44:07.53#ibcon#flushed, iclass 37, count 0 2006.201.12:44:07.53#ibcon#about to write, iclass 37, count 0 2006.201.12:44:07.53#ibcon#wrote, iclass 37, count 0 2006.201.12:44:07.53#ibcon#about to read 3, iclass 37, count 0 2006.201.12:44:07.56#ibcon#read 3, iclass 37, count 0 2006.201.12:44:07.56#ibcon#about to read 4, iclass 37, count 0 2006.201.12:44:07.56#ibcon#read 4, iclass 37, count 0 2006.201.12:44:07.56#ibcon#about to read 5, iclass 37, count 0 2006.201.12:44:07.56#ibcon#read 5, iclass 37, count 0 2006.201.12:44:07.56#ibcon#about to read 6, iclass 37, count 0 2006.201.12:44:07.56#ibcon#read 6, iclass 37, count 0 2006.201.12:44:07.56#ibcon#end of sib2, iclass 37, count 0 2006.201.12:44:07.56#ibcon#*after write, iclass 37, count 0 2006.201.12:44:07.56#ibcon#*before return 0, iclass 37, count 0 2006.201.12:44:07.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:07.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:07.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:44:07.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:44:07.56$vck44/vblo=1,629.99 2006.201.12:44:07.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.12:44:07.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.12:44:07.56#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:07.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:07.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:07.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:07.56#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:44:07.56#ibcon#first serial, iclass 39, count 0 2006.201.12:44:07.56#ibcon#enter sib2, iclass 39, count 0 2006.201.12:44:07.56#ibcon#flushed, iclass 39, count 0 2006.201.12:44:07.56#ibcon#about to write, iclass 39, count 0 2006.201.12:44:07.56#ibcon#wrote, iclass 39, count 0 2006.201.12:44:07.56#ibcon#about to read 3, iclass 39, count 0 2006.201.12:44:07.58#ibcon#read 3, iclass 39, count 0 2006.201.12:44:07.58#ibcon#about to read 4, iclass 39, count 0 2006.201.12:44:07.58#ibcon#read 4, iclass 39, count 0 2006.201.12:44:07.58#ibcon#about to read 5, iclass 39, count 0 2006.201.12:44:07.58#ibcon#read 5, iclass 39, count 0 2006.201.12:44:07.58#ibcon#about to read 6, iclass 39, count 0 2006.201.12:44:07.58#ibcon#read 6, iclass 39, count 0 2006.201.12:44:07.58#ibcon#end of sib2, iclass 39, count 0 2006.201.12:44:07.58#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:44:07.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:44:07.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:44:07.58#ibcon#*before write, iclass 39, count 0 2006.201.12:44:07.58#ibcon#enter sib2, iclass 39, count 0 2006.201.12:44:07.58#ibcon#flushed, iclass 39, count 0 2006.201.12:44:07.58#ibcon#about to write, iclass 39, count 0 2006.201.12:44:07.58#ibcon#wrote, iclass 39, count 0 2006.201.12:44:07.58#ibcon#about to read 3, iclass 39, count 0 2006.201.12:44:07.62#ibcon#read 3, iclass 39, count 0 2006.201.12:44:07.62#ibcon#about to read 4, iclass 39, count 0 2006.201.12:44:07.62#ibcon#read 4, iclass 39, count 0 2006.201.12:44:07.62#ibcon#about to read 5, iclass 39, count 0 2006.201.12:44:07.62#ibcon#read 5, iclass 39, count 0 2006.201.12:44:07.62#ibcon#about to read 6, iclass 39, count 0 2006.201.12:44:07.62#ibcon#read 6, iclass 39, count 0 2006.201.12:44:07.62#ibcon#end of sib2, iclass 39, count 0 2006.201.12:44:07.62#ibcon#*after write, iclass 39, count 0 2006.201.12:44:07.62#ibcon#*before return 0, iclass 39, count 0 2006.201.12:44:07.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:07.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:07.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:44:07.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:44:07.62$vck44/vb=1,4 2006.201.12:44:07.62#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.12:44:07.62#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.12:44:07.62#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:07.62#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:44:07.62#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:44:07.62#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:44:07.62#ibcon#enter wrdev, iclass 2, count 2 2006.201.12:44:07.62#ibcon#first serial, iclass 2, count 2 2006.201.12:44:07.62#ibcon#enter sib2, iclass 2, count 2 2006.201.12:44:07.62#ibcon#flushed, iclass 2, count 2 2006.201.12:44:07.62#ibcon#about to write, iclass 2, count 2 2006.201.12:44:07.62#ibcon#wrote, iclass 2, count 2 2006.201.12:44:07.62#ibcon#about to read 3, iclass 2, count 2 2006.201.12:44:07.64#ibcon#read 3, iclass 2, count 2 2006.201.12:44:07.64#ibcon#about to read 4, iclass 2, count 2 2006.201.12:44:07.64#ibcon#read 4, iclass 2, count 2 2006.201.12:44:07.64#ibcon#about to read 5, iclass 2, count 2 2006.201.12:44:07.64#ibcon#read 5, iclass 2, count 2 2006.201.12:44:07.64#ibcon#about to read 6, iclass 2, count 2 2006.201.12:44:07.64#ibcon#read 6, iclass 2, count 2 2006.201.12:44:07.64#ibcon#end of sib2, iclass 2, count 2 2006.201.12:44:07.64#ibcon#*mode == 0, iclass 2, count 2 2006.201.12:44:07.64#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.12:44:07.64#ibcon#[27=AT01-04\r\n] 2006.201.12:44:07.64#ibcon#*before write, iclass 2, count 2 2006.201.12:44:07.64#ibcon#enter sib2, iclass 2, count 2 2006.201.12:44:07.64#ibcon#flushed, iclass 2, count 2 2006.201.12:44:07.64#ibcon#about to write, iclass 2, count 2 2006.201.12:44:07.64#ibcon#wrote, iclass 2, count 2 2006.201.12:44:07.64#ibcon#about to read 3, iclass 2, count 2 2006.201.12:44:07.67#ibcon#read 3, iclass 2, count 2 2006.201.12:44:07.67#ibcon#about to read 4, iclass 2, count 2 2006.201.12:44:07.67#ibcon#read 4, iclass 2, count 2 2006.201.12:44:07.67#ibcon#about to read 5, iclass 2, count 2 2006.201.12:44:07.67#ibcon#read 5, iclass 2, count 2 2006.201.12:44:07.67#ibcon#about to read 6, iclass 2, count 2 2006.201.12:44:07.67#ibcon#read 6, iclass 2, count 2 2006.201.12:44:07.67#ibcon#end of sib2, iclass 2, count 2 2006.201.12:44:07.67#ibcon#*after write, iclass 2, count 2 2006.201.12:44:07.67#ibcon#*before return 0, iclass 2, count 2 2006.201.12:44:07.67#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:44:07.67#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.12:44:07.67#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.12:44:07.67#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:07.67#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:44:07.79#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:44:07.79#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:44:07.79#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:44:07.79#ibcon#first serial, iclass 2, count 0 2006.201.12:44:07.79#ibcon#enter sib2, iclass 2, count 0 2006.201.12:44:07.79#ibcon#flushed, iclass 2, count 0 2006.201.12:44:07.79#ibcon#about to write, iclass 2, count 0 2006.201.12:44:07.79#ibcon#wrote, iclass 2, count 0 2006.201.12:44:07.79#ibcon#about to read 3, iclass 2, count 0 2006.201.12:44:07.81#ibcon#read 3, iclass 2, count 0 2006.201.12:44:07.81#ibcon#about to read 4, iclass 2, count 0 2006.201.12:44:07.81#ibcon#read 4, iclass 2, count 0 2006.201.12:44:07.81#ibcon#about to read 5, iclass 2, count 0 2006.201.12:44:07.81#ibcon#read 5, iclass 2, count 0 2006.201.12:44:07.81#ibcon#about to read 6, iclass 2, count 0 2006.201.12:44:07.81#ibcon#read 6, iclass 2, count 0 2006.201.12:44:07.81#ibcon#end of sib2, iclass 2, count 0 2006.201.12:44:07.81#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:44:07.81#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:44:07.81#ibcon#[27=USB\r\n] 2006.201.12:44:07.81#ibcon#*before write, iclass 2, count 0 2006.201.12:44:07.81#ibcon#enter sib2, iclass 2, count 0 2006.201.12:44:07.81#ibcon#flushed, iclass 2, count 0 2006.201.12:44:07.81#ibcon#about to write, iclass 2, count 0 2006.201.12:44:07.81#ibcon#wrote, iclass 2, count 0 2006.201.12:44:07.81#ibcon#about to read 3, iclass 2, count 0 2006.201.12:44:07.84#ibcon#read 3, iclass 2, count 0 2006.201.12:44:07.84#ibcon#about to read 4, iclass 2, count 0 2006.201.12:44:07.84#ibcon#read 4, iclass 2, count 0 2006.201.12:44:07.84#ibcon#about to read 5, iclass 2, count 0 2006.201.12:44:07.84#ibcon#read 5, iclass 2, count 0 2006.201.12:44:07.84#ibcon#about to read 6, iclass 2, count 0 2006.201.12:44:07.84#ibcon#read 6, iclass 2, count 0 2006.201.12:44:07.84#ibcon#end of sib2, iclass 2, count 0 2006.201.12:44:07.84#ibcon#*after write, iclass 2, count 0 2006.201.12:44:07.84#ibcon#*before return 0, iclass 2, count 0 2006.201.12:44:07.84#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:44:07.84#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.12:44:07.84#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:44:07.84#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:44:07.84$vck44/vblo=2,634.99 2006.201.12:44:07.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.12:44:07.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.12:44:07.84#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:07.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:07.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:07.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:07.84#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:44:07.84#ibcon#first serial, iclass 5, count 0 2006.201.12:44:07.84#ibcon#enter sib2, iclass 5, count 0 2006.201.12:44:07.84#ibcon#flushed, iclass 5, count 0 2006.201.12:44:07.84#ibcon#about to write, iclass 5, count 0 2006.201.12:44:07.84#ibcon#wrote, iclass 5, count 0 2006.201.12:44:07.84#ibcon#about to read 3, iclass 5, count 0 2006.201.12:44:07.86#ibcon#read 3, iclass 5, count 0 2006.201.12:44:07.86#ibcon#about to read 4, iclass 5, count 0 2006.201.12:44:07.86#ibcon#read 4, iclass 5, count 0 2006.201.12:44:07.86#ibcon#about to read 5, iclass 5, count 0 2006.201.12:44:07.86#ibcon#read 5, iclass 5, count 0 2006.201.12:44:07.86#ibcon#about to read 6, iclass 5, count 0 2006.201.12:44:07.86#ibcon#read 6, iclass 5, count 0 2006.201.12:44:07.86#ibcon#end of sib2, iclass 5, count 0 2006.201.12:44:07.86#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:44:07.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:44:07.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:44:07.86#ibcon#*before write, iclass 5, count 0 2006.201.12:44:07.86#ibcon#enter sib2, iclass 5, count 0 2006.201.12:44:07.86#ibcon#flushed, iclass 5, count 0 2006.201.12:44:07.86#ibcon#about to write, iclass 5, count 0 2006.201.12:44:07.86#ibcon#wrote, iclass 5, count 0 2006.201.12:44:07.86#ibcon#about to read 3, iclass 5, count 0 2006.201.12:44:07.90#ibcon#read 3, iclass 5, count 0 2006.201.12:44:07.90#ibcon#about to read 4, iclass 5, count 0 2006.201.12:44:07.90#ibcon#read 4, iclass 5, count 0 2006.201.12:44:07.90#ibcon#about to read 5, iclass 5, count 0 2006.201.12:44:07.90#ibcon#read 5, iclass 5, count 0 2006.201.12:44:07.90#ibcon#about to read 6, iclass 5, count 0 2006.201.12:44:07.90#ibcon#read 6, iclass 5, count 0 2006.201.12:44:07.90#ibcon#end of sib2, iclass 5, count 0 2006.201.12:44:07.90#ibcon#*after write, iclass 5, count 0 2006.201.12:44:07.90#ibcon#*before return 0, iclass 5, count 0 2006.201.12:44:07.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:07.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.12:44:07.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:44:07.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:44:07.90$vck44/vb=2,5 2006.201.12:44:07.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.12:44:07.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.12:44:07.90#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:07.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:07.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:07.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:07.96#ibcon#enter wrdev, iclass 7, count 2 2006.201.12:44:07.96#ibcon#first serial, iclass 7, count 2 2006.201.12:44:07.96#ibcon#enter sib2, iclass 7, count 2 2006.201.12:44:07.96#ibcon#flushed, iclass 7, count 2 2006.201.12:44:07.96#ibcon#about to write, iclass 7, count 2 2006.201.12:44:07.96#ibcon#wrote, iclass 7, count 2 2006.201.12:44:07.96#ibcon#about to read 3, iclass 7, count 2 2006.201.12:44:07.98#ibcon#read 3, iclass 7, count 2 2006.201.12:44:07.98#ibcon#about to read 4, iclass 7, count 2 2006.201.12:44:07.98#ibcon#read 4, iclass 7, count 2 2006.201.12:44:07.98#ibcon#about to read 5, iclass 7, count 2 2006.201.12:44:07.98#ibcon#read 5, iclass 7, count 2 2006.201.12:44:07.98#ibcon#about to read 6, iclass 7, count 2 2006.201.12:44:07.98#ibcon#read 6, iclass 7, count 2 2006.201.12:44:07.98#ibcon#end of sib2, iclass 7, count 2 2006.201.12:44:07.98#ibcon#*mode == 0, iclass 7, count 2 2006.201.12:44:07.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.12:44:07.98#ibcon#[27=AT02-05\r\n] 2006.201.12:44:07.98#ibcon#*before write, iclass 7, count 2 2006.201.12:44:07.98#ibcon#enter sib2, iclass 7, count 2 2006.201.12:44:07.98#ibcon#flushed, iclass 7, count 2 2006.201.12:44:07.98#ibcon#about to write, iclass 7, count 2 2006.201.12:44:07.98#ibcon#wrote, iclass 7, count 2 2006.201.12:44:07.98#ibcon#about to read 3, iclass 7, count 2 2006.201.12:44:08.01#ibcon#read 3, iclass 7, count 2 2006.201.12:44:08.01#ibcon#about to read 4, iclass 7, count 2 2006.201.12:44:08.01#ibcon#read 4, iclass 7, count 2 2006.201.12:44:08.01#ibcon#about to read 5, iclass 7, count 2 2006.201.12:44:08.01#ibcon#read 5, iclass 7, count 2 2006.201.12:44:08.01#ibcon#about to read 6, iclass 7, count 2 2006.201.12:44:08.01#ibcon#read 6, iclass 7, count 2 2006.201.12:44:08.01#ibcon#end of sib2, iclass 7, count 2 2006.201.12:44:08.01#ibcon#*after write, iclass 7, count 2 2006.201.12:44:08.01#ibcon#*before return 0, iclass 7, count 2 2006.201.12:44:08.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:08.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.12:44:08.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.12:44:08.01#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:08.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:08.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:08.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:08.13#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:44:08.13#ibcon#first serial, iclass 7, count 0 2006.201.12:44:08.13#ibcon#enter sib2, iclass 7, count 0 2006.201.12:44:08.13#ibcon#flushed, iclass 7, count 0 2006.201.12:44:08.13#ibcon#about to write, iclass 7, count 0 2006.201.12:44:08.13#ibcon#wrote, iclass 7, count 0 2006.201.12:44:08.13#ibcon#about to read 3, iclass 7, count 0 2006.201.12:44:08.15#ibcon#read 3, iclass 7, count 0 2006.201.12:44:08.15#ibcon#about to read 4, iclass 7, count 0 2006.201.12:44:08.15#ibcon#read 4, iclass 7, count 0 2006.201.12:44:08.15#ibcon#about to read 5, iclass 7, count 0 2006.201.12:44:08.15#ibcon#read 5, iclass 7, count 0 2006.201.12:44:08.15#ibcon#about to read 6, iclass 7, count 0 2006.201.12:44:08.15#ibcon#read 6, iclass 7, count 0 2006.201.12:44:08.15#ibcon#end of sib2, iclass 7, count 0 2006.201.12:44:08.15#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:44:08.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:44:08.15#ibcon#[27=USB\r\n] 2006.201.12:44:08.15#ibcon#*before write, iclass 7, count 0 2006.201.12:44:08.15#ibcon#enter sib2, iclass 7, count 0 2006.201.12:44:08.15#ibcon#flushed, iclass 7, count 0 2006.201.12:44:08.15#ibcon#about to write, iclass 7, count 0 2006.201.12:44:08.15#ibcon#wrote, iclass 7, count 0 2006.201.12:44:08.15#ibcon#about to read 3, iclass 7, count 0 2006.201.12:44:08.18#ibcon#read 3, iclass 7, count 0 2006.201.12:44:08.18#ibcon#about to read 4, iclass 7, count 0 2006.201.12:44:08.18#ibcon#read 4, iclass 7, count 0 2006.201.12:44:08.18#ibcon#about to read 5, iclass 7, count 0 2006.201.12:44:08.18#ibcon#read 5, iclass 7, count 0 2006.201.12:44:08.18#ibcon#about to read 6, iclass 7, count 0 2006.201.12:44:08.18#ibcon#read 6, iclass 7, count 0 2006.201.12:44:08.18#ibcon#end of sib2, iclass 7, count 0 2006.201.12:44:08.18#ibcon#*after write, iclass 7, count 0 2006.201.12:44:08.18#ibcon#*before return 0, iclass 7, count 0 2006.201.12:44:08.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:08.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.12:44:08.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:44:08.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:44:08.18$vck44/vblo=3,649.99 2006.201.12:44:08.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.12:44:08.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.12:44:08.18#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:08.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:08.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:08.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:08.18#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:44:08.18#ibcon#first serial, iclass 11, count 0 2006.201.12:44:08.18#ibcon#enter sib2, iclass 11, count 0 2006.201.12:44:08.18#ibcon#flushed, iclass 11, count 0 2006.201.12:44:08.18#ibcon#about to write, iclass 11, count 0 2006.201.12:44:08.18#ibcon#wrote, iclass 11, count 0 2006.201.12:44:08.18#ibcon#about to read 3, iclass 11, count 0 2006.201.12:44:08.20#ibcon#read 3, iclass 11, count 0 2006.201.12:44:08.20#ibcon#about to read 4, iclass 11, count 0 2006.201.12:44:08.20#ibcon#read 4, iclass 11, count 0 2006.201.12:44:08.20#ibcon#about to read 5, iclass 11, count 0 2006.201.12:44:08.20#ibcon#read 5, iclass 11, count 0 2006.201.12:44:08.20#ibcon#about to read 6, iclass 11, count 0 2006.201.12:44:08.20#ibcon#read 6, iclass 11, count 0 2006.201.12:44:08.20#ibcon#end of sib2, iclass 11, count 0 2006.201.12:44:08.20#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:44:08.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:44:08.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:44:08.20#ibcon#*before write, iclass 11, count 0 2006.201.12:44:08.20#ibcon#enter sib2, iclass 11, count 0 2006.201.12:44:08.20#ibcon#flushed, iclass 11, count 0 2006.201.12:44:08.20#ibcon#about to write, iclass 11, count 0 2006.201.12:44:08.20#ibcon#wrote, iclass 11, count 0 2006.201.12:44:08.20#ibcon#about to read 3, iclass 11, count 0 2006.201.12:44:08.25#ibcon#read 3, iclass 11, count 0 2006.201.12:44:08.25#ibcon#about to read 4, iclass 11, count 0 2006.201.12:44:08.25#ibcon#read 4, iclass 11, count 0 2006.201.12:44:08.25#ibcon#about to read 5, iclass 11, count 0 2006.201.12:44:08.25#ibcon#read 5, iclass 11, count 0 2006.201.12:44:08.25#ibcon#about to read 6, iclass 11, count 0 2006.201.12:44:08.25#ibcon#read 6, iclass 11, count 0 2006.201.12:44:08.25#ibcon#end of sib2, iclass 11, count 0 2006.201.12:44:08.25#ibcon#*after write, iclass 11, count 0 2006.201.12:44:08.25#ibcon#*before return 0, iclass 11, count 0 2006.201.12:44:08.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:08.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.12:44:08.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:44:08.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:44:08.25$vck44/vb=3,4 2006.201.12:44:08.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.12:44:08.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.12:44:08.25#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:08.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:08.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:08.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:08.30#ibcon#enter wrdev, iclass 13, count 2 2006.201.12:44:08.30#ibcon#first serial, iclass 13, count 2 2006.201.12:44:08.30#ibcon#enter sib2, iclass 13, count 2 2006.201.12:44:08.30#ibcon#flushed, iclass 13, count 2 2006.201.12:44:08.30#ibcon#about to write, iclass 13, count 2 2006.201.12:44:08.30#ibcon#wrote, iclass 13, count 2 2006.201.12:44:08.30#ibcon#about to read 3, iclass 13, count 2 2006.201.12:44:08.32#ibcon#read 3, iclass 13, count 2 2006.201.12:44:08.32#ibcon#about to read 4, iclass 13, count 2 2006.201.12:44:08.32#ibcon#read 4, iclass 13, count 2 2006.201.12:44:08.32#ibcon#about to read 5, iclass 13, count 2 2006.201.12:44:08.32#ibcon#read 5, iclass 13, count 2 2006.201.12:44:08.32#ibcon#about to read 6, iclass 13, count 2 2006.201.12:44:08.32#ibcon#read 6, iclass 13, count 2 2006.201.12:44:08.32#ibcon#end of sib2, iclass 13, count 2 2006.201.12:44:08.32#ibcon#*mode == 0, iclass 13, count 2 2006.201.12:44:08.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.12:44:08.32#ibcon#[27=AT03-04\r\n] 2006.201.12:44:08.32#ibcon#*before write, iclass 13, count 2 2006.201.12:44:08.32#ibcon#enter sib2, iclass 13, count 2 2006.201.12:44:08.32#ibcon#flushed, iclass 13, count 2 2006.201.12:44:08.32#ibcon#about to write, iclass 13, count 2 2006.201.12:44:08.32#ibcon#wrote, iclass 13, count 2 2006.201.12:44:08.32#ibcon#about to read 3, iclass 13, count 2 2006.201.12:44:08.35#ibcon#read 3, iclass 13, count 2 2006.201.12:44:08.35#ibcon#about to read 4, iclass 13, count 2 2006.201.12:44:08.35#ibcon#read 4, iclass 13, count 2 2006.201.12:44:08.35#ibcon#about to read 5, iclass 13, count 2 2006.201.12:44:08.35#ibcon#read 5, iclass 13, count 2 2006.201.12:44:08.35#ibcon#about to read 6, iclass 13, count 2 2006.201.12:44:08.35#ibcon#read 6, iclass 13, count 2 2006.201.12:44:08.35#ibcon#end of sib2, iclass 13, count 2 2006.201.12:44:08.35#ibcon#*after write, iclass 13, count 2 2006.201.12:44:08.35#ibcon#*before return 0, iclass 13, count 2 2006.201.12:44:08.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:08.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.12:44:08.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.12:44:08.35#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:08.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:08.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:08.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:08.47#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:44:08.47#ibcon#first serial, iclass 13, count 0 2006.201.12:44:08.47#ibcon#enter sib2, iclass 13, count 0 2006.201.12:44:08.47#ibcon#flushed, iclass 13, count 0 2006.201.12:44:08.47#ibcon#about to write, iclass 13, count 0 2006.201.12:44:08.47#ibcon#wrote, iclass 13, count 0 2006.201.12:44:08.47#ibcon#about to read 3, iclass 13, count 0 2006.201.12:44:08.49#ibcon#read 3, iclass 13, count 0 2006.201.12:44:08.49#ibcon#about to read 4, iclass 13, count 0 2006.201.12:44:08.49#ibcon#read 4, iclass 13, count 0 2006.201.12:44:08.49#ibcon#about to read 5, iclass 13, count 0 2006.201.12:44:08.49#ibcon#read 5, iclass 13, count 0 2006.201.12:44:08.49#ibcon#about to read 6, iclass 13, count 0 2006.201.12:44:08.49#ibcon#read 6, iclass 13, count 0 2006.201.12:44:08.49#ibcon#end of sib2, iclass 13, count 0 2006.201.12:44:08.49#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:44:08.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:44:08.49#ibcon#[27=USB\r\n] 2006.201.12:44:08.49#ibcon#*before write, iclass 13, count 0 2006.201.12:44:08.49#ibcon#enter sib2, iclass 13, count 0 2006.201.12:44:08.49#ibcon#flushed, iclass 13, count 0 2006.201.12:44:08.49#ibcon#about to write, iclass 13, count 0 2006.201.12:44:08.49#ibcon#wrote, iclass 13, count 0 2006.201.12:44:08.49#ibcon#about to read 3, iclass 13, count 0 2006.201.12:44:08.52#ibcon#read 3, iclass 13, count 0 2006.201.12:44:08.52#ibcon#about to read 4, iclass 13, count 0 2006.201.12:44:08.52#ibcon#read 4, iclass 13, count 0 2006.201.12:44:08.52#ibcon#about to read 5, iclass 13, count 0 2006.201.12:44:08.52#ibcon#read 5, iclass 13, count 0 2006.201.12:44:08.52#ibcon#about to read 6, iclass 13, count 0 2006.201.12:44:08.52#ibcon#read 6, iclass 13, count 0 2006.201.12:44:08.52#ibcon#end of sib2, iclass 13, count 0 2006.201.12:44:08.52#ibcon#*after write, iclass 13, count 0 2006.201.12:44:08.52#ibcon#*before return 0, iclass 13, count 0 2006.201.12:44:08.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:08.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.12:44:08.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:44:08.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:44:08.52$vck44/vblo=4,679.99 2006.201.12:44:08.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.12:44:08.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.12:44:08.52#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:08.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:08.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:08.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:08.52#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:44:08.52#ibcon#first serial, iclass 15, count 0 2006.201.12:44:08.52#ibcon#enter sib2, iclass 15, count 0 2006.201.12:44:08.52#ibcon#flushed, iclass 15, count 0 2006.201.12:44:08.52#ibcon#about to write, iclass 15, count 0 2006.201.12:44:08.52#ibcon#wrote, iclass 15, count 0 2006.201.12:44:08.52#ibcon#about to read 3, iclass 15, count 0 2006.201.12:44:08.54#ibcon#read 3, iclass 15, count 0 2006.201.12:44:08.54#ibcon#about to read 4, iclass 15, count 0 2006.201.12:44:08.54#ibcon#read 4, iclass 15, count 0 2006.201.12:44:08.54#ibcon#about to read 5, iclass 15, count 0 2006.201.12:44:08.54#ibcon#read 5, iclass 15, count 0 2006.201.12:44:08.54#ibcon#about to read 6, iclass 15, count 0 2006.201.12:44:08.54#ibcon#read 6, iclass 15, count 0 2006.201.12:44:08.54#ibcon#end of sib2, iclass 15, count 0 2006.201.12:44:08.54#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:44:08.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:44:08.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:44:08.54#ibcon#*before write, iclass 15, count 0 2006.201.12:44:08.54#ibcon#enter sib2, iclass 15, count 0 2006.201.12:44:08.54#ibcon#flushed, iclass 15, count 0 2006.201.12:44:08.54#ibcon#about to write, iclass 15, count 0 2006.201.12:44:08.54#ibcon#wrote, iclass 15, count 0 2006.201.12:44:08.54#ibcon#about to read 3, iclass 15, count 0 2006.201.12:44:08.58#ibcon#read 3, iclass 15, count 0 2006.201.12:44:08.58#ibcon#about to read 4, iclass 15, count 0 2006.201.12:44:08.58#ibcon#read 4, iclass 15, count 0 2006.201.12:44:08.58#ibcon#about to read 5, iclass 15, count 0 2006.201.12:44:08.58#ibcon#read 5, iclass 15, count 0 2006.201.12:44:08.58#ibcon#about to read 6, iclass 15, count 0 2006.201.12:44:08.58#ibcon#read 6, iclass 15, count 0 2006.201.12:44:08.58#ibcon#end of sib2, iclass 15, count 0 2006.201.12:44:08.58#ibcon#*after write, iclass 15, count 0 2006.201.12:44:08.58#ibcon#*before return 0, iclass 15, count 0 2006.201.12:44:08.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:08.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.12:44:08.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:44:08.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:44:08.58$vck44/vb=4,5 2006.201.12:44:08.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.12:44:08.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.12:44:08.58#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:08.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:08.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:08.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:08.64#ibcon#enter wrdev, iclass 17, count 2 2006.201.12:44:08.64#ibcon#first serial, iclass 17, count 2 2006.201.12:44:08.64#ibcon#enter sib2, iclass 17, count 2 2006.201.12:44:08.64#ibcon#flushed, iclass 17, count 2 2006.201.12:44:08.64#ibcon#about to write, iclass 17, count 2 2006.201.12:44:08.64#ibcon#wrote, iclass 17, count 2 2006.201.12:44:08.64#ibcon#about to read 3, iclass 17, count 2 2006.201.12:44:08.66#ibcon#read 3, iclass 17, count 2 2006.201.12:44:08.66#ibcon#about to read 4, iclass 17, count 2 2006.201.12:44:08.66#ibcon#read 4, iclass 17, count 2 2006.201.12:44:08.66#ibcon#about to read 5, iclass 17, count 2 2006.201.12:44:08.66#ibcon#read 5, iclass 17, count 2 2006.201.12:44:08.66#ibcon#about to read 6, iclass 17, count 2 2006.201.12:44:08.66#ibcon#read 6, iclass 17, count 2 2006.201.12:44:08.66#ibcon#end of sib2, iclass 17, count 2 2006.201.12:44:08.66#ibcon#*mode == 0, iclass 17, count 2 2006.201.12:44:08.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.12:44:08.66#ibcon#[27=AT04-05\r\n] 2006.201.12:44:08.66#ibcon#*before write, iclass 17, count 2 2006.201.12:44:08.66#ibcon#enter sib2, iclass 17, count 2 2006.201.12:44:08.66#ibcon#flushed, iclass 17, count 2 2006.201.12:44:08.66#ibcon#about to write, iclass 17, count 2 2006.201.12:44:08.66#ibcon#wrote, iclass 17, count 2 2006.201.12:44:08.66#ibcon#about to read 3, iclass 17, count 2 2006.201.12:44:08.69#ibcon#read 3, iclass 17, count 2 2006.201.12:44:08.69#ibcon#about to read 4, iclass 17, count 2 2006.201.12:44:08.69#ibcon#read 4, iclass 17, count 2 2006.201.12:44:08.69#ibcon#about to read 5, iclass 17, count 2 2006.201.12:44:08.69#ibcon#read 5, iclass 17, count 2 2006.201.12:44:08.69#ibcon#about to read 6, iclass 17, count 2 2006.201.12:44:08.69#ibcon#read 6, iclass 17, count 2 2006.201.12:44:08.69#ibcon#end of sib2, iclass 17, count 2 2006.201.12:44:08.69#ibcon#*after write, iclass 17, count 2 2006.201.12:44:08.69#ibcon#*before return 0, iclass 17, count 2 2006.201.12:44:08.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:08.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.12:44:08.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.12:44:08.69#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:08.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:08.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:08.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:08.81#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:44:08.81#ibcon#first serial, iclass 17, count 0 2006.201.12:44:08.81#ibcon#enter sib2, iclass 17, count 0 2006.201.12:44:08.81#ibcon#flushed, iclass 17, count 0 2006.201.12:44:08.81#ibcon#about to write, iclass 17, count 0 2006.201.12:44:08.81#ibcon#wrote, iclass 17, count 0 2006.201.12:44:08.81#ibcon#about to read 3, iclass 17, count 0 2006.201.12:44:08.83#ibcon#read 3, iclass 17, count 0 2006.201.12:44:08.83#ibcon#about to read 4, iclass 17, count 0 2006.201.12:44:08.83#ibcon#read 4, iclass 17, count 0 2006.201.12:44:08.83#ibcon#about to read 5, iclass 17, count 0 2006.201.12:44:08.83#ibcon#read 5, iclass 17, count 0 2006.201.12:44:08.83#ibcon#about to read 6, iclass 17, count 0 2006.201.12:44:08.83#ibcon#read 6, iclass 17, count 0 2006.201.12:44:08.83#ibcon#end of sib2, iclass 17, count 0 2006.201.12:44:08.83#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:44:08.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:44:08.83#ibcon#[27=USB\r\n] 2006.201.12:44:08.83#ibcon#*before write, iclass 17, count 0 2006.201.12:44:08.83#ibcon#enter sib2, iclass 17, count 0 2006.201.12:44:08.83#ibcon#flushed, iclass 17, count 0 2006.201.12:44:08.83#ibcon#about to write, iclass 17, count 0 2006.201.12:44:08.83#ibcon#wrote, iclass 17, count 0 2006.201.12:44:08.83#ibcon#about to read 3, iclass 17, count 0 2006.201.12:44:08.86#ibcon#read 3, iclass 17, count 0 2006.201.12:44:08.86#ibcon#about to read 4, iclass 17, count 0 2006.201.12:44:08.86#ibcon#read 4, iclass 17, count 0 2006.201.12:44:08.86#ibcon#about to read 5, iclass 17, count 0 2006.201.12:44:08.86#ibcon#read 5, iclass 17, count 0 2006.201.12:44:08.86#ibcon#about to read 6, iclass 17, count 0 2006.201.12:44:08.86#ibcon#read 6, iclass 17, count 0 2006.201.12:44:08.86#ibcon#end of sib2, iclass 17, count 0 2006.201.12:44:08.86#ibcon#*after write, iclass 17, count 0 2006.201.12:44:08.86#ibcon#*before return 0, iclass 17, count 0 2006.201.12:44:08.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:08.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.12:44:08.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:44:08.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:44:08.86$vck44/vblo=5,709.99 2006.201.12:44:08.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.12:44:08.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.12:44:08.86#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:08.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:08.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:08.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:08.86#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:44:08.86#ibcon#first serial, iclass 19, count 0 2006.201.12:44:08.86#ibcon#enter sib2, iclass 19, count 0 2006.201.12:44:08.86#ibcon#flushed, iclass 19, count 0 2006.201.12:44:08.86#ibcon#about to write, iclass 19, count 0 2006.201.12:44:08.86#ibcon#wrote, iclass 19, count 0 2006.201.12:44:08.86#ibcon#about to read 3, iclass 19, count 0 2006.201.12:44:08.88#ibcon#read 3, iclass 19, count 0 2006.201.12:44:08.88#ibcon#about to read 4, iclass 19, count 0 2006.201.12:44:08.88#ibcon#read 4, iclass 19, count 0 2006.201.12:44:08.88#ibcon#about to read 5, iclass 19, count 0 2006.201.12:44:08.88#ibcon#read 5, iclass 19, count 0 2006.201.12:44:08.88#ibcon#about to read 6, iclass 19, count 0 2006.201.12:44:08.88#ibcon#read 6, iclass 19, count 0 2006.201.12:44:08.88#ibcon#end of sib2, iclass 19, count 0 2006.201.12:44:08.88#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:44:08.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:44:08.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:44:08.88#ibcon#*before write, iclass 19, count 0 2006.201.12:44:08.88#ibcon#enter sib2, iclass 19, count 0 2006.201.12:44:08.88#ibcon#flushed, iclass 19, count 0 2006.201.12:44:08.88#ibcon#about to write, iclass 19, count 0 2006.201.12:44:08.88#ibcon#wrote, iclass 19, count 0 2006.201.12:44:08.88#ibcon#about to read 3, iclass 19, count 0 2006.201.12:44:08.93#ibcon#read 3, iclass 19, count 0 2006.201.12:44:08.93#ibcon#about to read 4, iclass 19, count 0 2006.201.12:44:08.93#ibcon#read 4, iclass 19, count 0 2006.201.12:44:08.93#ibcon#about to read 5, iclass 19, count 0 2006.201.12:44:08.93#ibcon#read 5, iclass 19, count 0 2006.201.12:44:08.93#ibcon#about to read 6, iclass 19, count 0 2006.201.12:44:08.93#ibcon#read 6, iclass 19, count 0 2006.201.12:44:08.93#ibcon#end of sib2, iclass 19, count 0 2006.201.12:44:08.93#ibcon#*after write, iclass 19, count 0 2006.201.12:44:08.93#ibcon#*before return 0, iclass 19, count 0 2006.201.12:44:08.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:08.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.12:44:08.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:44:08.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:44:08.93$vck44/vb=5,4 2006.201.12:44:08.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.12:44:08.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.12:44:08.93#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:08.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:08.98#abcon#<5=/04 2.0 3.5 21.051001004.1\r\n> 2006.201.12:44:08.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:08.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:08.98#ibcon#enter wrdev, iclass 21, count 2 2006.201.12:44:08.98#ibcon#first serial, iclass 21, count 2 2006.201.12:44:08.98#ibcon#enter sib2, iclass 21, count 2 2006.201.12:44:08.98#ibcon#flushed, iclass 21, count 2 2006.201.12:44:08.98#ibcon#about to write, iclass 21, count 2 2006.201.12:44:08.98#ibcon#wrote, iclass 21, count 2 2006.201.12:44:08.98#ibcon#about to read 3, iclass 21, count 2 2006.201.12:44:09.00#ibcon#read 3, iclass 21, count 2 2006.201.12:44:09.00#ibcon#about to read 4, iclass 21, count 2 2006.201.12:44:09.00#ibcon#read 4, iclass 21, count 2 2006.201.12:44:09.00#ibcon#about to read 5, iclass 21, count 2 2006.201.12:44:09.00#ibcon#read 5, iclass 21, count 2 2006.201.12:44:09.00#ibcon#about to read 6, iclass 21, count 2 2006.201.12:44:09.00#ibcon#read 6, iclass 21, count 2 2006.201.12:44:09.00#ibcon#end of sib2, iclass 21, count 2 2006.201.12:44:09.00#ibcon#*mode == 0, iclass 21, count 2 2006.201.12:44:09.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.12:44:09.00#ibcon#[27=AT05-04\r\n] 2006.201.12:44:09.00#ibcon#*before write, iclass 21, count 2 2006.201.12:44:09.00#ibcon#enter sib2, iclass 21, count 2 2006.201.12:44:09.00#ibcon#flushed, iclass 21, count 2 2006.201.12:44:09.00#ibcon#about to write, iclass 21, count 2 2006.201.12:44:09.00#ibcon#wrote, iclass 21, count 2 2006.201.12:44:09.00#ibcon#about to read 3, iclass 21, count 2 2006.201.12:44:09.00#abcon#{5=INTERFACE CLEAR} 2006.201.12:44:09.03#ibcon#read 3, iclass 21, count 2 2006.201.12:44:09.03#ibcon#about to read 4, iclass 21, count 2 2006.201.12:44:09.03#ibcon#read 4, iclass 21, count 2 2006.201.12:44:09.03#ibcon#about to read 5, iclass 21, count 2 2006.201.12:44:09.03#ibcon#read 5, iclass 21, count 2 2006.201.12:44:09.03#ibcon#about to read 6, iclass 21, count 2 2006.201.12:44:09.03#ibcon#read 6, iclass 21, count 2 2006.201.12:44:09.03#ibcon#end of sib2, iclass 21, count 2 2006.201.12:44:09.03#ibcon#*after write, iclass 21, count 2 2006.201.12:44:09.03#ibcon#*before return 0, iclass 21, count 2 2006.201.12:44:09.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:09.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.12:44:09.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.12:44:09.03#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:09.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:09.06#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:44:09.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:09.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:09.15#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:44:09.15#ibcon#first serial, iclass 21, count 0 2006.201.12:44:09.15#ibcon#enter sib2, iclass 21, count 0 2006.201.12:44:09.15#ibcon#flushed, iclass 21, count 0 2006.201.12:44:09.15#ibcon#about to write, iclass 21, count 0 2006.201.12:44:09.15#ibcon#wrote, iclass 21, count 0 2006.201.12:44:09.15#ibcon#about to read 3, iclass 21, count 0 2006.201.12:44:09.17#ibcon#read 3, iclass 21, count 0 2006.201.12:44:09.17#ibcon#about to read 4, iclass 21, count 0 2006.201.12:44:09.17#ibcon#read 4, iclass 21, count 0 2006.201.12:44:09.17#ibcon#about to read 5, iclass 21, count 0 2006.201.12:44:09.17#ibcon#read 5, iclass 21, count 0 2006.201.12:44:09.17#ibcon#about to read 6, iclass 21, count 0 2006.201.12:44:09.17#ibcon#read 6, iclass 21, count 0 2006.201.12:44:09.17#ibcon#end of sib2, iclass 21, count 0 2006.201.12:44:09.17#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:44:09.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:44:09.17#ibcon#[27=USB\r\n] 2006.201.12:44:09.17#ibcon#*before write, iclass 21, count 0 2006.201.12:44:09.17#ibcon#enter sib2, iclass 21, count 0 2006.201.12:44:09.17#ibcon#flushed, iclass 21, count 0 2006.201.12:44:09.17#ibcon#about to write, iclass 21, count 0 2006.201.12:44:09.17#ibcon#wrote, iclass 21, count 0 2006.201.12:44:09.17#ibcon#about to read 3, iclass 21, count 0 2006.201.12:44:09.20#ibcon#read 3, iclass 21, count 0 2006.201.12:44:09.20#ibcon#about to read 4, iclass 21, count 0 2006.201.12:44:09.20#ibcon#read 4, iclass 21, count 0 2006.201.12:44:09.20#ibcon#about to read 5, iclass 21, count 0 2006.201.12:44:09.20#ibcon#read 5, iclass 21, count 0 2006.201.12:44:09.20#ibcon#about to read 6, iclass 21, count 0 2006.201.12:44:09.20#ibcon#read 6, iclass 21, count 0 2006.201.12:44:09.20#ibcon#end of sib2, iclass 21, count 0 2006.201.12:44:09.20#ibcon#*after write, iclass 21, count 0 2006.201.12:44:09.20#ibcon#*before return 0, iclass 21, count 0 2006.201.12:44:09.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:09.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.12:44:09.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:44:09.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:44:09.20$vck44/vblo=6,719.99 2006.201.12:44:09.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.12:44:09.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.12:44:09.20#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:09.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:09.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:09.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:09.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:44:09.20#ibcon#first serial, iclass 27, count 0 2006.201.12:44:09.20#ibcon#enter sib2, iclass 27, count 0 2006.201.12:44:09.20#ibcon#flushed, iclass 27, count 0 2006.201.12:44:09.20#ibcon#about to write, iclass 27, count 0 2006.201.12:44:09.20#ibcon#wrote, iclass 27, count 0 2006.201.12:44:09.20#ibcon#about to read 3, iclass 27, count 0 2006.201.12:44:09.22#ibcon#read 3, iclass 27, count 0 2006.201.12:44:09.22#ibcon#about to read 4, iclass 27, count 0 2006.201.12:44:09.22#ibcon#read 4, iclass 27, count 0 2006.201.12:44:09.22#ibcon#about to read 5, iclass 27, count 0 2006.201.12:44:09.22#ibcon#read 5, iclass 27, count 0 2006.201.12:44:09.22#ibcon#about to read 6, iclass 27, count 0 2006.201.12:44:09.22#ibcon#read 6, iclass 27, count 0 2006.201.12:44:09.22#ibcon#end of sib2, iclass 27, count 0 2006.201.12:44:09.22#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:44:09.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:44:09.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:44:09.22#ibcon#*before write, iclass 27, count 0 2006.201.12:44:09.22#ibcon#enter sib2, iclass 27, count 0 2006.201.12:44:09.22#ibcon#flushed, iclass 27, count 0 2006.201.12:44:09.22#ibcon#about to write, iclass 27, count 0 2006.201.12:44:09.22#ibcon#wrote, iclass 27, count 0 2006.201.12:44:09.22#ibcon#about to read 3, iclass 27, count 0 2006.201.12:44:09.26#ibcon#read 3, iclass 27, count 0 2006.201.12:44:09.26#ibcon#about to read 4, iclass 27, count 0 2006.201.12:44:09.26#ibcon#read 4, iclass 27, count 0 2006.201.12:44:09.26#ibcon#about to read 5, iclass 27, count 0 2006.201.12:44:09.26#ibcon#read 5, iclass 27, count 0 2006.201.12:44:09.26#ibcon#about to read 6, iclass 27, count 0 2006.201.12:44:09.26#ibcon#read 6, iclass 27, count 0 2006.201.12:44:09.26#ibcon#end of sib2, iclass 27, count 0 2006.201.12:44:09.26#ibcon#*after write, iclass 27, count 0 2006.201.12:44:09.26#ibcon#*before return 0, iclass 27, count 0 2006.201.12:44:09.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:09.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.12:44:09.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:44:09.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:44:09.26$vck44/vb=6,4 2006.201.12:44:09.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.12:44:09.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.12:44:09.26#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:09.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:09.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:09.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:09.32#ibcon#enter wrdev, iclass 29, count 2 2006.201.12:44:09.32#ibcon#first serial, iclass 29, count 2 2006.201.12:44:09.32#ibcon#enter sib2, iclass 29, count 2 2006.201.12:44:09.32#ibcon#flushed, iclass 29, count 2 2006.201.12:44:09.32#ibcon#about to write, iclass 29, count 2 2006.201.12:44:09.32#ibcon#wrote, iclass 29, count 2 2006.201.12:44:09.32#ibcon#about to read 3, iclass 29, count 2 2006.201.12:44:09.34#ibcon#read 3, iclass 29, count 2 2006.201.12:44:09.34#ibcon#about to read 4, iclass 29, count 2 2006.201.12:44:09.34#ibcon#read 4, iclass 29, count 2 2006.201.12:44:09.34#ibcon#about to read 5, iclass 29, count 2 2006.201.12:44:09.34#ibcon#read 5, iclass 29, count 2 2006.201.12:44:09.34#ibcon#about to read 6, iclass 29, count 2 2006.201.12:44:09.34#ibcon#read 6, iclass 29, count 2 2006.201.12:44:09.34#ibcon#end of sib2, iclass 29, count 2 2006.201.12:44:09.34#ibcon#*mode == 0, iclass 29, count 2 2006.201.12:44:09.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.12:44:09.34#ibcon#[27=AT06-04\r\n] 2006.201.12:44:09.34#ibcon#*before write, iclass 29, count 2 2006.201.12:44:09.34#ibcon#enter sib2, iclass 29, count 2 2006.201.12:44:09.34#ibcon#flushed, iclass 29, count 2 2006.201.12:44:09.34#ibcon#about to write, iclass 29, count 2 2006.201.12:44:09.34#ibcon#wrote, iclass 29, count 2 2006.201.12:44:09.34#ibcon#about to read 3, iclass 29, count 2 2006.201.12:44:09.37#ibcon#read 3, iclass 29, count 2 2006.201.12:44:09.37#ibcon#about to read 4, iclass 29, count 2 2006.201.12:44:09.37#ibcon#read 4, iclass 29, count 2 2006.201.12:44:09.37#ibcon#about to read 5, iclass 29, count 2 2006.201.12:44:09.37#ibcon#read 5, iclass 29, count 2 2006.201.12:44:09.37#ibcon#about to read 6, iclass 29, count 2 2006.201.12:44:09.37#ibcon#read 6, iclass 29, count 2 2006.201.12:44:09.37#ibcon#end of sib2, iclass 29, count 2 2006.201.12:44:09.37#ibcon#*after write, iclass 29, count 2 2006.201.12:44:09.37#ibcon#*before return 0, iclass 29, count 2 2006.201.12:44:09.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:09.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.12:44:09.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.12:44:09.37#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:09.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:09.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:09.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:09.49#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:44:09.49#ibcon#first serial, iclass 29, count 0 2006.201.12:44:09.49#ibcon#enter sib2, iclass 29, count 0 2006.201.12:44:09.49#ibcon#flushed, iclass 29, count 0 2006.201.12:44:09.49#ibcon#about to write, iclass 29, count 0 2006.201.12:44:09.49#ibcon#wrote, iclass 29, count 0 2006.201.12:44:09.49#ibcon#about to read 3, iclass 29, count 0 2006.201.12:44:09.51#ibcon#read 3, iclass 29, count 0 2006.201.12:44:09.51#ibcon#about to read 4, iclass 29, count 0 2006.201.12:44:09.51#ibcon#read 4, iclass 29, count 0 2006.201.12:44:09.51#ibcon#about to read 5, iclass 29, count 0 2006.201.12:44:09.51#ibcon#read 5, iclass 29, count 0 2006.201.12:44:09.51#ibcon#about to read 6, iclass 29, count 0 2006.201.12:44:09.51#ibcon#read 6, iclass 29, count 0 2006.201.12:44:09.51#ibcon#end of sib2, iclass 29, count 0 2006.201.12:44:09.51#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:44:09.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:44:09.51#ibcon#[27=USB\r\n] 2006.201.12:44:09.51#ibcon#*before write, iclass 29, count 0 2006.201.12:44:09.51#ibcon#enter sib2, iclass 29, count 0 2006.201.12:44:09.51#ibcon#flushed, iclass 29, count 0 2006.201.12:44:09.51#ibcon#about to write, iclass 29, count 0 2006.201.12:44:09.51#ibcon#wrote, iclass 29, count 0 2006.201.12:44:09.51#ibcon#about to read 3, iclass 29, count 0 2006.201.12:44:09.54#ibcon#read 3, iclass 29, count 0 2006.201.12:44:09.54#ibcon#about to read 4, iclass 29, count 0 2006.201.12:44:09.54#ibcon#read 4, iclass 29, count 0 2006.201.12:44:09.54#ibcon#about to read 5, iclass 29, count 0 2006.201.12:44:09.54#ibcon#read 5, iclass 29, count 0 2006.201.12:44:09.54#ibcon#about to read 6, iclass 29, count 0 2006.201.12:44:09.54#ibcon#read 6, iclass 29, count 0 2006.201.12:44:09.54#ibcon#end of sib2, iclass 29, count 0 2006.201.12:44:09.54#ibcon#*after write, iclass 29, count 0 2006.201.12:44:09.54#ibcon#*before return 0, iclass 29, count 0 2006.201.12:44:09.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:09.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.12:44:09.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:44:09.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:44:09.54$vck44/vblo=7,734.99 2006.201.12:44:09.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.12:44:09.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.12:44:09.54#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:09.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:09.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:09.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:09.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:44:09.54#ibcon#first serial, iclass 31, count 0 2006.201.12:44:09.54#ibcon#enter sib2, iclass 31, count 0 2006.201.12:44:09.54#ibcon#flushed, iclass 31, count 0 2006.201.12:44:09.54#ibcon#about to write, iclass 31, count 0 2006.201.12:44:09.54#ibcon#wrote, iclass 31, count 0 2006.201.12:44:09.54#ibcon#about to read 3, iclass 31, count 0 2006.201.12:44:09.56#ibcon#read 3, iclass 31, count 0 2006.201.12:44:09.56#ibcon#about to read 4, iclass 31, count 0 2006.201.12:44:09.56#ibcon#read 4, iclass 31, count 0 2006.201.12:44:09.56#ibcon#about to read 5, iclass 31, count 0 2006.201.12:44:09.56#ibcon#read 5, iclass 31, count 0 2006.201.12:44:09.56#ibcon#about to read 6, iclass 31, count 0 2006.201.12:44:09.56#ibcon#read 6, iclass 31, count 0 2006.201.12:44:09.56#ibcon#end of sib2, iclass 31, count 0 2006.201.12:44:09.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:44:09.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:44:09.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:44:09.56#ibcon#*before write, iclass 31, count 0 2006.201.12:44:09.56#ibcon#enter sib2, iclass 31, count 0 2006.201.12:44:09.56#ibcon#flushed, iclass 31, count 0 2006.201.12:44:09.56#ibcon#about to write, iclass 31, count 0 2006.201.12:44:09.56#ibcon#wrote, iclass 31, count 0 2006.201.12:44:09.56#ibcon#about to read 3, iclass 31, count 0 2006.201.12:44:09.60#ibcon#read 3, iclass 31, count 0 2006.201.12:44:09.60#ibcon#about to read 4, iclass 31, count 0 2006.201.12:44:09.60#ibcon#read 4, iclass 31, count 0 2006.201.12:44:09.60#ibcon#about to read 5, iclass 31, count 0 2006.201.12:44:09.60#ibcon#read 5, iclass 31, count 0 2006.201.12:44:09.60#ibcon#about to read 6, iclass 31, count 0 2006.201.12:44:09.60#ibcon#read 6, iclass 31, count 0 2006.201.12:44:09.60#ibcon#end of sib2, iclass 31, count 0 2006.201.12:44:09.60#ibcon#*after write, iclass 31, count 0 2006.201.12:44:09.60#ibcon#*before return 0, iclass 31, count 0 2006.201.12:44:09.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:09.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.12:44:09.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:44:09.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:44:09.60$vck44/vb=7,4 2006.201.12:44:09.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.12:44:09.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.12:44:09.60#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:09.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:09.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:09.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:09.66#ibcon#enter wrdev, iclass 33, count 2 2006.201.12:44:09.66#ibcon#first serial, iclass 33, count 2 2006.201.12:44:09.66#ibcon#enter sib2, iclass 33, count 2 2006.201.12:44:09.66#ibcon#flushed, iclass 33, count 2 2006.201.12:44:09.66#ibcon#about to write, iclass 33, count 2 2006.201.12:44:09.66#ibcon#wrote, iclass 33, count 2 2006.201.12:44:09.66#ibcon#about to read 3, iclass 33, count 2 2006.201.12:44:09.68#ibcon#read 3, iclass 33, count 2 2006.201.12:44:09.68#ibcon#about to read 4, iclass 33, count 2 2006.201.12:44:09.68#ibcon#read 4, iclass 33, count 2 2006.201.12:44:09.68#ibcon#about to read 5, iclass 33, count 2 2006.201.12:44:09.68#ibcon#read 5, iclass 33, count 2 2006.201.12:44:09.68#ibcon#about to read 6, iclass 33, count 2 2006.201.12:44:09.68#ibcon#read 6, iclass 33, count 2 2006.201.12:44:09.68#ibcon#end of sib2, iclass 33, count 2 2006.201.12:44:09.68#ibcon#*mode == 0, iclass 33, count 2 2006.201.12:44:09.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.12:44:09.68#ibcon#[27=AT07-04\r\n] 2006.201.12:44:09.68#ibcon#*before write, iclass 33, count 2 2006.201.12:44:09.68#ibcon#enter sib2, iclass 33, count 2 2006.201.12:44:09.68#ibcon#flushed, iclass 33, count 2 2006.201.12:44:09.68#ibcon#about to write, iclass 33, count 2 2006.201.12:44:09.68#ibcon#wrote, iclass 33, count 2 2006.201.12:44:09.68#ibcon#about to read 3, iclass 33, count 2 2006.201.12:44:09.71#ibcon#read 3, iclass 33, count 2 2006.201.12:44:09.71#ibcon#about to read 4, iclass 33, count 2 2006.201.12:44:09.71#ibcon#read 4, iclass 33, count 2 2006.201.12:44:09.71#ibcon#about to read 5, iclass 33, count 2 2006.201.12:44:09.71#ibcon#read 5, iclass 33, count 2 2006.201.12:44:09.71#ibcon#about to read 6, iclass 33, count 2 2006.201.12:44:09.71#ibcon#read 6, iclass 33, count 2 2006.201.12:44:09.71#ibcon#end of sib2, iclass 33, count 2 2006.201.12:44:09.71#ibcon#*after write, iclass 33, count 2 2006.201.12:44:09.71#ibcon#*before return 0, iclass 33, count 2 2006.201.12:44:09.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:09.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.12:44:09.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.12:44:09.71#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:09.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:09.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:09.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:09.83#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:44:09.83#ibcon#first serial, iclass 33, count 0 2006.201.12:44:09.83#ibcon#enter sib2, iclass 33, count 0 2006.201.12:44:09.83#ibcon#flushed, iclass 33, count 0 2006.201.12:44:09.83#ibcon#about to write, iclass 33, count 0 2006.201.12:44:09.83#ibcon#wrote, iclass 33, count 0 2006.201.12:44:09.83#ibcon#about to read 3, iclass 33, count 0 2006.201.12:44:09.85#ibcon#read 3, iclass 33, count 0 2006.201.12:44:09.85#ibcon#about to read 4, iclass 33, count 0 2006.201.12:44:09.85#ibcon#read 4, iclass 33, count 0 2006.201.12:44:09.85#ibcon#about to read 5, iclass 33, count 0 2006.201.12:44:09.85#ibcon#read 5, iclass 33, count 0 2006.201.12:44:09.85#ibcon#about to read 6, iclass 33, count 0 2006.201.12:44:09.85#ibcon#read 6, iclass 33, count 0 2006.201.12:44:09.85#ibcon#end of sib2, iclass 33, count 0 2006.201.12:44:09.85#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:44:09.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:44:09.85#ibcon#[27=USB\r\n] 2006.201.12:44:09.85#ibcon#*before write, iclass 33, count 0 2006.201.12:44:09.85#ibcon#enter sib2, iclass 33, count 0 2006.201.12:44:09.85#ibcon#flushed, iclass 33, count 0 2006.201.12:44:09.85#ibcon#about to write, iclass 33, count 0 2006.201.12:44:09.85#ibcon#wrote, iclass 33, count 0 2006.201.12:44:09.85#ibcon#about to read 3, iclass 33, count 0 2006.201.12:44:09.88#ibcon#read 3, iclass 33, count 0 2006.201.12:44:09.88#ibcon#about to read 4, iclass 33, count 0 2006.201.12:44:09.88#ibcon#read 4, iclass 33, count 0 2006.201.12:44:09.88#ibcon#about to read 5, iclass 33, count 0 2006.201.12:44:09.88#ibcon#read 5, iclass 33, count 0 2006.201.12:44:09.88#ibcon#about to read 6, iclass 33, count 0 2006.201.12:44:09.88#ibcon#read 6, iclass 33, count 0 2006.201.12:44:09.88#ibcon#end of sib2, iclass 33, count 0 2006.201.12:44:09.88#ibcon#*after write, iclass 33, count 0 2006.201.12:44:09.88#ibcon#*before return 0, iclass 33, count 0 2006.201.12:44:09.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:09.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.12:44:09.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:44:09.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:44:09.88$vck44/vblo=8,744.99 2006.201.12:44:09.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.12:44:09.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.12:44:09.88#ibcon#ireg 17 cls_cnt 0 2006.201.12:44:09.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:09.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:09.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:09.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:44:09.88#ibcon#first serial, iclass 35, count 0 2006.201.12:44:09.88#ibcon#enter sib2, iclass 35, count 0 2006.201.12:44:09.88#ibcon#flushed, iclass 35, count 0 2006.201.12:44:09.88#ibcon#about to write, iclass 35, count 0 2006.201.12:44:09.88#ibcon#wrote, iclass 35, count 0 2006.201.12:44:09.88#ibcon#about to read 3, iclass 35, count 0 2006.201.12:44:09.90#ibcon#read 3, iclass 35, count 0 2006.201.12:44:09.90#ibcon#about to read 4, iclass 35, count 0 2006.201.12:44:09.90#ibcon#read 4, iclass 35, count 0 2006.201.12:44:09.90#ibcon#about to read 5, iclass 35, count 0 2006.201.12:44:09.90#ibcon#read 5, iclass 35, count 0 2006.201.12:44:09.90#ibcon#about to read 6, iclass 35, count 0 2006.201.12:44:09.90#ibcon#read 6, iclass 35, count 0 2006.201.12:44:09.90#ibcon#end of sib2, iclass 35, count 0 2006.201.12:44:09.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:44:09.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:44:09.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:44:09.90#ibcon#*before write, iclass 35, count 0 2006.201.12:44:09.90#ibcon#enter sib2, iclass 35, count 0 2006.201.12:44:09.90#ibcon#flushed, iclass 35, count 0 2006.201.12:44:09.90#ibcon#about to write, iclass 35, count 0 2006.201.12:44:09.90#ibcon#wrote, iclass 35, count 0 2006.201.12:44:09.90#ibcon#about to read 3, iclass 35, count 0 2006.201.12:44:09.95#ibcon#read 3, iclass 35, count 0 2006.201.12:44:09.95#ibcon#about to read 4, iclass 35, count 0 2006.201.12:44:09.95#ibcon#read 4, iclass 35, count 0 2006.201.12:44:09.95#ibcon#about to read 5, iclass 35, count 0 2006.201.12:44:09.95#ibcon#read 5, iclass 35, count 0 2006.201.12:44:09.95#ibcon#about to read 6, iclass 35, count 0 2006.201.12:44:09.95#ibcon#read 6, iclass 35, count 0 2006.201.12:44:09.95#ibcon#end of sib2, iclass 35, count 0 2006.201.12:44:09.95#ibcon#*after write, iclass 35, count 0 2006.201.12:44:09.95#ibcon#*before return 0, iclass 35, count 0 2006.201.12:44:09.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:09.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:44:09.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:44:09.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:44:09.95$vck44/vb=8,4 2006.201.12:44:09.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.12:44:09.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.12:44:09.95#ibcon#ireg 11 cls_cnt 2 2006.201.12:44:09.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:10.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:10.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:10.00#ibcon#enter wrdev, iclass 37, count 2 2006.201.12:44:10.00#ibcon#first serial, iclass 37, count 2 2006.201.12:44:10.00#ibcon#enter sib2, iclass 37, count 2 2006.201.12:44:10.00#ibcon#flushed, iclass 37, count 2 2006.201.12:44:10.00#ibcon#about to write, iclass 37, count 2 2006.201.12:44:10.00#ibcon#wrote, iclass 37, count 2 2006.201.12:44:10.00#ibcon#about to read 3, iclass 37, count 2 2006.201.12:44:10.02#ibcon#read 3, iclass 37, count 2 2006.201.12:44:10.02#ibcon#about to read 4, iclass 37, count 2 2006.201.12:44:10.02#ibcon#read 4, iclass 37, count 2 2006.201.12:44:10.02#ibcon#about to read 5, iclass 37, count 2 2006.201.12:44:10.02#ibcon#read 5, iclass 37, count 2 2006.201.12:44:10.02#ibcon#about to read 6, iclass 37, count 2 2006.201.12:44:10.02#ibcon#read 6, iclass 37, count 2 2006.201.12:44:10.02#ibcon#end of sib2, iclass 37, count 2 2006.201.12:44:10.02#ibcon#*mode == 0, iclass 37, count 2 2006.201.12:44:10.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.12:44:10.02#ibcon#[27=AT08-04\r\n] 2006.201.12:44:10.02#ibcon#*before write, iclass 37, count 2 2006.201.12:44:10.02#ibcon#enter sib2, iclass 37, count 2 2006.201.12:44:10.02#ibcon#flushed, iclass 37, count 2 2006.201.12:44:10.02#ibcon#about to write, iclass 37, count 2 2006.201.12:44:10.02#ibcon#wrote, iclass 37, count 2 2006.201.12:44:10.02#ibcon#about to read 3, iclass 37, count 2 2006.201.12:44:10.05#ibcon#read 3, iclass 37, count 2 2006.201.12:44:10.05#ibcon#about to read 4, iclass 37, count 2 2006.201.12:44:10.05#ibcon#read 4, iclass 37, count 2 2006.201.12:44:10.05#ibcon#about to read 5, iclass 37, count 2 2006.201.12:44:10.05#ibcon#read 5, iclass 37, count 2 2006.201.12:44:10.05#ibcon#about to read 6, iclass 37, count 2 2006.201.12:44:10.05#ibcon#read 6, iclass 37, count 2 2006.201.12:44:10.05#ibcon#end of sib2, iclass 37, count 2 2006.201.12:44:10.05#ibcon#*after write, iclass 37, count 2 2006.201.12:44:10.05#ibcon#*before return 0, iclass 37, count 2 2006.201.12:44:10.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:10.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.12:44:10.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.12:44:10.05#ibcon#ireg 7 cls_cnt 0 2006.201.12:44:10.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:10.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:10.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:10.17#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:44:10.17#ibcon#first serial, iclass 37, count 0 2006.201.12:44:10.17#ibcon#enter sib2, iclass 37, count 0 2006.201.12:44:10.17#ibcon#flushed, iclass 37, count 0 2006.201.12:44:10.17#ibcon#about to write, iclass 37, count 0 2006.201.12:44:10.17#ibcon#wrote, iclass 37, count 0 2006.201.12:44:10.17#ibcon#about to read 3, iclass 37, count 0 2006.201.12:44:10.19#ibcon#read 3, iclass 37, count 0 2006.201.12:44:10.19#ibcon#about to read 4, iclass 37, count 0 2006.201.12:44:10.19#ibcon#read 4, iclass 37, count 0 2006.201.12:44:10.19#ibcon#about to read 5, iclass 37, count 0 2006.201.12:44:10.19#ibcon#read 5, iclass 37, count 0 2006.201.12:44:10.19#ibcon#about to read 6, iclass 37, count 0 2006.201.12:44:10.19#ibcon#read 6, iclass 37, count 0 2006.201.12:44:10.19#ibcon#end of sib2, iclass 37, count 0 2006.201.12:44:10.19#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:44:10.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:44:10.19#ibcon#[27=USB\r\n] 2006.201.12:44:10.19#ibcon#*before write, iclass 37, count 0 2006.201.12:44:10.19#ibcon#enter sib2, iclass 37, count 0 2006.201.12:44:10.19#ibcon#flushed, iclass 37, count 0 2006.201.12:44:10.19#ibcon#about to write, iclass 37, count 0 2006.201.12:44:10.19#ibcon#wrote, iclass 37, count 0 2006.201.12:44:10.19#ibcon#about to read 3, iclass 37, count 0 2006.201.12:44:10.22#ibcon#read 3, iclass 37, count 0 2006.201.12:44:10.22#ibcon#about to read 4, iclass 37, count 0 2006.201.12:44:10.22#ibcon#read 4, iclass 37, count 0 2006.201.12:44:10.22#ibcon#about to read 5, iclass 37, count 0 2006.201.12:44:10.22#ibcon#read 5, iclass 37, count 0 2006.201.12:44:10.22#ibcon#about to read 6, iclass 37, count 0 2006.201.12:44:10.22#ibcon#read 6, iclass 37, count 0 2006.201.12:44:10.22#ibcon#end of sib2, iclass 37, count 0 2006.201.12:44:10.22#ibcon#*after write, iclass 37, count 0 2006.201.12:44:10.22#ibcon#*before return 0, iclass 37, count 0 2006.201.12:44:10.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:10.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.12:44:10.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:44:10.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:44:10.22$vck44/vabw=wide 2006.201.12:44:10.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.12:44:10.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.12:44:10.22#ibcon#ireg 8 cls_cnt 0 2006.201.12:44:10.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:10.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:10.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:10.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:44:10.22#ibcon#first serial, iclass 39, count 0 2006.201.12:44:10.22#ibcon#enter sib2, iclass 39, count 0 2006.201.12:44:10.22#ibcon#flushed, iclass 39, count 0 2006.201.12:44:10.22#ibcon#about to write, iclass 39, count 0 2006.201.12:44:10.22#ibcon#wrote, iclass 39, count 0 2006.201.12:44:10.22#ibcon#about to read 3, iclass 39, count 0 2006.201.12:44:10.24#ibcon#read 3, iclass 39, count 0 2006.201.12:44:10.24#ibcon#about to read 4, iclass 39, count 0 2006.201.12:44:10.24#ibcon#read 4, iclass 39, count 0 2006.201.12:44:10.24#ibcon#about to read 5, iclass 39, count 0 2006.201.12:44:10.24#ibcon#read 5, iclass 39, count 0 2006.201.12:44:10.24#ibcon#about to read 6, iclass 39, count 0 2006.201.12:44:10.24#ibcon#read 6, iclass 39, count 0 2006.201.12:44:10.24#ibcon#end of sib2, iclass 39, count 0 2006.201.12:44:10.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:44:10.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:44:10.24#ibcon#[25=BW32\r\n] 2006.201.12:44:10.24#ibcon#*before write, iclass 39, count 0 2006.201.12:44:10.24#ibcon#enter sib2, iclass 39, count 0 2006.201.12:44:10.24#ibcon#flushed, iclass 39, count 0 2006.201.12:44:10.24#ibcon#about to write, iclass 39, count 0 2006.201.12:44:10.24#ibcon#wrote, iclass 39, count 0 2006.201.12:44:10.24#ibcon#about to read 3, iclass 39, count 0 2006.201.12:44:10.27#ibcon#read 3, iclass 39, count 0 2006.201.12:44:10.27#ibcon#about to read 4, iclass 39, count 0 2006.201.12:44:10.27#ibcon#read 4, iclass 39, count 0 2006.201.12:44:10.27#ibcon#about to read 5, iclass 39, count 0 2006.201.12:44:10.27#ibcon#read 5, iclass 39, count 0 2006.201.12:44:10.27#ibcon#about to read 6, iclass 39, count 0 2006.201.12:44:10.27#ibcon#read 6, iclass 39, count 0 2006.201.12:44:10.27#ibcon#end of sib2, iclass 39, count 0 2006.201.12:44:10.27#ibcon#*after write, iclass 39, count 0 2006.201.12:44:10.27#ibcon#*before return 0, iclass 39, count 0 2006.201.12:44:10.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:10.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.12:44:10.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:44:10.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:44:10.27$vck44/vbbw=wide 2006.201.12:44:10.27#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.12:44:10.27#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.12:44:10.27#ibcon#ireg 8 cls_cnt 0 2006.201.12:44:10.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:44:10.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:44:10.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:44:10.34#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:44:10.34#ibcon#first serial, iclass 2, count 0 2006.201.12:44:10.34#ibcon#enter sib2, iclass 2, count 0 2006.201.12:44:10.34#ibcon#flushed, iclass 2, count 0 2006.201.12:44:10.34#ibcon#about to write, iclass 2, count 0 2006.201.12:44:10.34#ibcon#wrote, iclass 2, count 0 2006.201.12:44:10.34#ibcon#about to read 3, iclass 2, count 0 2006.201.12:44:10.36#ibcon#read 3, iclass 2, count 0 2006.201.12:44:10.36#ibcon#about to read 4, iclass 2, count 0 2006.201.12:44:10.36#ibcon#read 4, iclass 2, count 0 2006.201.12:44:10.36#ibcon#about to read 5, iclass 2, count 0 2006.201.12:44:10.36#ibcon#read 5, iclass 2, count 0 2006.201.12:44:10.36#ibcon#about to read 6, iclass 2, count 0 2006.201.12:44:10.36#ibcon#read 6, iclass 2, count 0 2006.201.12:44:10.36#ibcon#end of sib2, iclass 2, count 0 2006.201.12:44:10.36#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:44:10.36#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:44:10.36#ibcon#[27=BW32\r\n] 2006.201.12:44:10.36#ibcon#*before write, iclass 2, count 0 2006.201.12:44:10.36#ibcon#enter sib2, iclass 2, count 0 2006.201.12:44:10.36#ibcon#flushed, iclass 2, count 0 2006.201.12:44:10.36#ibcon#about to write, iclass 2, count 0 2006.201.12:44:10.36#ibcon#wrote, iclass 2, count 0 2006.201.12:44:10.36#ibcon#about to read 3, iclass 2, count 0 2006.201.12:44:10.39#ibcon#read 3, iclass 2, count 0 2006.201.12:44:10.39#ibcon#about to read 4, iclass 2, count 0 2006.201.12:44:10.39#ibcon#read 4, iclass 2, count 0 2006.201.12:44:10.39#ibcon#about to read 5, iclass 2, count 0 2006.201.12:44:10.39#ibcon#read 5, iclass 2, count 0 2006.201.12:44:10.39#ibcon#about to read 6, iclass 2, count 0 2006.201.12:44:10.39#ibcon#read 6, iclass 2, count 0 2006.201.12:44:10.39#ibcon#end of sib2, iclass 2, count 0 2006.201.12:44:10.39#ibcon#*after write, iclass 2, count 0 2006.201.12:44:10.39#ibcon#*before return 0, iclass 2, count 0 2006.201.12:44:10.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:44:10.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:44:10.39#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:44:10.39#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:44:10.39$setupk4/ifdk4 2006.201.12:44:10.39$ifdk4/lo= 2006.201.12:44:10.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:44:10.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:44:10.39$ifdk4/patch= 2006.201.12:44:10.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:44:10.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:44:10.39$setupk4/!*+20s 2006.201.12:44:19.15#abcon#<5=/04 2.0 3.5 21.051001004.1\r\n> 2006.201.12:44:19.17#abcon#{5=INTERFACE CLEAR} 2006.201.12:44:19.23#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:44:24.88$setupk4/"tpicd 2006.201.12:44:24.88$setupk4/echo=off 2006.201.12:44:24.88$setupk4/xlog=off 2006.201.12:44:24.88:!2006.201.12:44:52 2006.201.12:44:25.14#trakl#Source acquired 2006.201.12:44:27.14#flagr#flagr/antenna,acquired 2006.201.12:44:52.00:preob 2006.201.12:44:52.14/onsource/TRACKING 2006.201.12:44:52.14:!2006.201.12:45:02 2006.201.12:45:02.00:"tape 2006.201.12:45:02.00:"st=record 2006.201.12:45:02.00:data_valid=on 2006.201.12:45:02.00:midob 2006.201.12:45:03.14/onsource/TRACKING 2006.201.12:45:03.14/wx/21.05,1004.1,100 2006.201.12:45:03.36/cable/+6.4743E-03 2006.201.12:45:04.45/va/01,08,usb,yes,29,31 2006.201.12:45:04.45/va/02,07,usb,yes,31,32 2006.201.12:45:04.45/va/03,08,usb,yes,28,29 2006.201.12:45:04.45/va/04,07,usb,yes,32,33 2006.201.12:45:04.45/va/05,04,usb,yes,28,28 2006.201.12:45:04.45/va/06,05,usb,yes,28,28 2006.201.12:45:04.45/va/07,05,usb,yes,27,28 2006.201.12:45:04.45/va/08,04,usb,yes,27,33 2006.201.12:45:04.68/valo/01,524.99,yes,locked 2006.201.12:45:04.68/valo/02,534.99,yes,locked 2006.201.12:45:04.68/valo/03,564.99,yes,locked 2006.201.12:45:04.68/valo/04,624.99,yes,locked 2006.201.12:45:04.68/valo/05,734.99,yes,locked 2006.201.12:45:04.68/valo/06,814.99,yes,locked 2006.201.12:45:04.68/valo/07,864.99,yes,locked 2006.201.12:45:04.68/valo/08,884.99,yes,locked 2006.201.12:45:05.77/vb/01,04,usb,yes,29,27 2006.201.12:45:05.77/vb/02,05,usb,yes,27,27 2006.201.12:45:05.77/vb/03,04,usb,yes,28,31 2006.201.12:45:05.77/vb/04,05,usb,yes,29,28 2006.201.12:45:05.77/vb/05,04,usb,yes,25,27 2006.201.12:45:05.77/vb/06,04,usb,yes,29,26 2006.201.12:45:05.77/vb/07,04,usb,yes,29,29 2006.201.12:45:05.77/vb/08,04,usb,yes,27,30 2006.201.12:45:06.00/vblo/01,629.99,yes,locked 2006.201.12:45:06.00/vblo/02,634.99,yes,locked 2006.201.12:45:06.00/vblo/03,649.99,yes,locked 2006.201.12:45:06.00/vblo/04,679.99,yes,locked 2006.201.12:45:06.00/vblo/05,709.99,yes,locked 2006.201.12:45:06.00/vblo/06,719.99,yes,locked 2006.201.12:45:06.00/vblo/07,734.99,yes,locked 2006.201.12:45:06.00/vblo/08,744.99,yes,locked 2006.201.12:45:06.15/vabw/8 2006.201.12:45:06.30/vbbw/8 2006.201.12:45:06.51/xfe/off,on,15.5 2006.201.12:45:06.90/ifatt/23,28,28,28 2006.201.12:45:07.06/fmout-gps/S +4.60E-07 2006.201.12:45:07.10:!2006.201.12:51:42 2006.201.12:51:42.00:data_valid=off 2006.201.12:51:42.00:"et 2006.201.12:51:42.00:!+3s 2006.201.12:51:45.02:"tape 2006.201.12:51:45.02:postob 2006.201.12:51:45.08/cable/+6.4729E-03 2006.201.12:51:45.08/wx/21.02,1004.1,100 2006.201.12:51:45.16/fmout-gps/S +4.59E-07 2006.201.12:51:45.16:scan_name=201-1257,jd0607,240 2006.201.12:51:45.17:source=0059+581,010245.76,582411.1,2000.0,cw 2006.201.12:51:47.14#flagr#flagr/antenna,new-source 2006.201.12:51:47.14:checkk5 2006.201.12:51:47.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.12:51:47.93/chk_autoobs//k5ts2/ autoobs is running! 2006.201.12:51:48.31/chk_autoobs//k5ts3/ autoobs is running! 2006.201.12:51:48.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.12:51:49.04/chk_obsdata//k5ts1/T2011245??a.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.201.12:51:49.40/chk_obsdata//k5ts2/T2011245??b.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.201.12:51:49.77/chk_obsdata//k5ts3/T2011245??c.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.201.12:51:50.14/chk_obsdata//k5ts4/T2011245??d.dat file size is correct (nominal:1600MB, actual:1596MB). 2006.201.12:51:50.82/k5log//k5ts1_log_newline 2006.201.12:51:51.52/k5log//k5ts2_log_newline 2006.201.12:51:52.21/k5log//k5ts3_log_newline 2006.201.12:51:52.90/k5log//k5ts4_log_newline 2006.201.12:51:52.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.12:51:52.92:setupk4=1 2006.201.12:51:52.92$setupk4/echo=on 2006.201.12:51:52.92$setupk4/pcalon 2006.201.12:51:52.92$pcalon/"no phase cal control is implemented here 2006.201.12:51:52.92$setupk4/"tpicd=stop 2006.201.12:51:52.92$setupk4/"rec=synch_on 2006.201.12:51:52.92$setupk4/"rec_mode=128 2006.201.12:51:52.92$setupk4/!* 2006.201.12:51:52.92$setupk4/recpk4 2006.201.12:51:52.92$recpk4/recpatch= 2006.201.12:51:52.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.12:51:52.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.12:51:52.93$setupk4/vck44 2006.201.12:51:52.93$vck44/valo=1,524.99 2006.201.12:51:52.93#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.12:51:52.93#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.12:51:52.93#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:52.93#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:52.93#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:52.93#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:52.93#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:51:52.93#ibcon#first serial, iclass 2, count 0 2006.201.12:51:52.93#ibcon#enter sib2, iclass 2, count 0 2006.201.12:51:52.93#ibcon#flushed, iclass 2, count 0 2006.201.12:51:52.93#ibcon#about to write, iclass 2, count 0 2006.201.12:51:52.93#ibcon#wrote, iclass 2, count 0 2006.201.12:51:52.93#ibcon#about to read 3, iclass 2, count 0 2006.201.12:51:52.96#ibcon#read 3, iclass 2, count 0 2006.201.12:51:52.96#ibcon#about to read 4, iclass 2, count 0 2006.201.12:51:52.96#ibcon#read 4, iclass 2, count 0 2006.201.12:51:52.96#ibcon#about to read 5, iclass 2, count 0 2006.201.12:51:52.96#ibcon#read 5, iclass 2, count 0 2006.201.12:51:52.96#ibcon#about to read 6, iclass 2, count 0 2006.201.12:51:52.96#ibcon#read 6, iclass 2, count 0 2006.201.12:51:52.96#ibcon#end of sib2, iclass 2, count 0 2006.201.12:51:52.96#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:51:52.96#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:51:52.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.12:51:52.96#ibcon#*before write, iclass 2, count 0 2006.201.12:51:52.96#ibcon#enter sib2, iclass 2, count 0 2006.201.12:51:52.96#ibcon#flushed, iclass 2, count 0 2006.201.12:51:52.96#ibcon#about to write, iclass 2, count 0 2006.201.12:51:52.96#ibcon#wrote, iclass 2, count 0 2006.201.12:51:52.96#ibcon#about to read 3, iclass 2, count 0 2006.201.12:51:53.01#ibcon#read 3, iclass 2, count 0 2006.201.12:51:53.01#ibcon#about to read 4, iclass 2, count 0 2006.201.12:51:53.01#ibcon#read 4, iclass 2, count 0 2006.201.12:51:53.01#ibcon#about to read 5, iclass 2, count 0 2006.201.12:51:53.01#ibcon#read 5, iclass 2, count 0 2006.201.12:51:53.01#ibcon#about to read 6, iclass 2, count 0 2006.201.12:51:53.01#ibcon#read 6, iclass 2, count 0 2006.201.12:51:53.01#ibcon#end of sib2, iclass 2, count 0 2006.201.12:51:53.01#ibcon#*after write, iclass 2, count 0 2006.201.12:51:53.01#ibcon#*before return 0, iclass 2, count 0 2006.201.12:51:53.01#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:53.01#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:53.01#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:51:53.01#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:51:53.01$vck44/va=1,8 2006.201.12:51:53.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.12:51:53.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.12:51:53.01#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:53.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:53.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:53.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:53.01#ibcon#enter wrdev, iclass 5, count 2 2006.201.12:51:53.01#ibcon#first serial, iclass 5, count 2 2006.201.12:51:53.01#ibcon#enter sib2, iclass 5, count 2 2006.201.12:51:53.01#ibcon#flushed, iclass 5, count 2 2006.201.12:51:53.01#ibcon#about to write, iclass 5, count 2 2006.201.12:51:53.01#ibcon#wrote, iclass 5, count 2 2006.201.12:51:53.01#ibcon#about to read 3, iclass 5, count 2 2006.201.12:51:53.03#ibcon#read 3, iclass 5, count 2 2006.201.12:51:53.03#ibcon#about to read 4, iclass 5, count 2 2006.201.12:51:53.03#ibcon#read 4, iclass 5, count 2 2006.201.12:51:53.03#ibcon#about to read 5, iclass 5, count 2 2006.201.12:51:53.03#ibcon#read 5, iclass 5, count 2 2006.201.12:51:53.03#ibcon#about to read 6, iclass 5, count 2 2006.201.12:51:53.03#ibcon#read 6, iclass 5, count 2 2006.201.12:51:53.03#ibcon#end of sib2, iclass 5, count 2 2006.201.12:51:53.03#ibcon#*mode == 0, iclass 5, count 2 2006.201.12:51:53.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.12:51:53.03#ibcon#[25=AT01-08\r\n] 2006.201.12:51:53.03#ibcon#*before write, iclass 5, count 2 2006.201.12:51:53.03#ibcon#enter sib2, iclass 5, count 2 2006.201.12:51:53.03#ibcon#flushed, iclass 5, count 2 2006.201.12:51:53.03#ibcon#about to write, iclass 5, count 2 2006.201.12:51:53.03#ibcon#wrote, iclass 5, count 2 2006.201.12:51:53.03#ibcon#about to read 3, iclass 5, count 2 2006.201.12:51:53.06#ibcon#read 3, iclass 5, count 2 2006.201.12:51:53.06#ibcon#about to read 4, iclass 5, count 2 2006.201.12:51:53.06#ibcon#read 4, iclass 5, count 2 2006.201.12:51:53.06#ibcon#about to read 5, iclass 5, count 2 2006.201.12:51:53.06#ibcon#read 5, iclass 5, count 2 2006.201.12:51:53.06#ibcon#about to read 6, iclass 5, count 2 2006.201.12:51:53.06#ibcon#read 6, iclass 5, count 2 2006.201.12:51:53.06#ibcon#end of sib2, iclass 5, count 2 2006.201.12:51:53.06#ibcon#*after write, iclass 5, count 2 2006.201.12:51:53.06#ibcon#*before return 0, iclass 5, count 2 2006.201.12:51:53.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:53.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:53.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.12:51:53.06#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:53.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:53.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:53.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:53.18#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:51:53.18#ibcon#first serial, iclass 5, count 0 2006.201.12:51:53.18#ibcon#enter sib2, iclass 5, count 0 2006.201.12:51:53.18#ibcon#flushed, iclass 5, count 0 2006.201.12:51:53.18#ibcon#about to write, iclass 5, count 0 2006.201.12:51:53.18#ibcon#wrote, iclass 5, count 0 2006.201.12:51:53.18#ibcon#about to read 3, iclass 5, count 0 2006.201.12:51:53.20#ibcon#read 3, iclass 5, count 0 2006.201.12:51:53.20#ibcon#about to read 4, iclass 5, count 0 2006.201.12:51:53.20#ibcon#read 4, iclass 5, count 0 2006.201.12:51:53.20#ibcon#about to read 5, iclass 5, count 0 2006.201.12:51:53.20#ibcon#read 5, iclass 5, count 0 2006.201.12:51:53.20#ibcon#about to read 6, iclass 5, count 0 2006.201.12:51:53.20#ibcon#read 6, iclass 5, count 0 2006.201.12:51:53.20#ibcon#end of sib2, iclass 5, count 0 2006.201.12:51:53.20#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:51:53.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:51:53.20#ibcon#[25=USB\r\n] 2006.201.12:51:53.20#ibcon#*before write, iclass 5, count 0 2006.201.12:51:53.20#ibcon#enter sib2, iclass 5, count 0 2006.201.12:51:53.20#ibcon#flushed, iclass 5, count 0 2006.201.12:51:53.20#ibcon#about to write, iclass 5, count 0 2006.201.12:51:53.20#ibcon#wrote, iclass 5, count 0 2006.201.12:51:53.20#ibcon#about to read 3, iclass 5, count 0 2006.201.12:51:53.23#ibcon#read 3, iclass 5, count 0 2006.201.12:51:53.23#ibcon#about to read 4, iclass 5, count 0 2006.201.12:51:53.23#ibcon#read 4, iclass 5, count 0 2006.201.12:51:53.23#ibcon#about to read 5, iclass 5, count 0 2006.201.12:51:53.23#ibcon#read 5, iclass 5, count 0 2006.201.12:51:53.23#ibcon#about to read 6, iclass 5, count 0 2006.201.12:51:53.23#ibcon#read 6, iclass 5, count 0 2006.201.12:51:53.23#ibcon#end of sib2, iclass 5, count 0 2006.201.12:51:53.23#ibcon#*after write, iclass 5, count 0 2006.201.12:51:53.23#ibcon#*before return 0, iclass 5, count 0 2006.201.12:51:53.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:53.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:53.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:51:53.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:51:53.23$vck44/valo=2,534.99 2006.201.12:51:53.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.12:51:53.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.12:51:53.23#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:53.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:53.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:53.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:53.23#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:51:53.23#ibcon#first serial, iclass 7, count 0 2006.201.12:51:53.23#ibcon#enter sib2, iclass 7, count 0 2006.201.12:51:53.23#ibcon#flushed, iclass 7, count 0 2006.201.12:51:53.23#ibcon#about to write, iclass 7, count 0 2006.201.12:51:53.23#ibcon#wrote, iclass 7, count 0 2006.201.12:51:53.23#ibcon#about to read 3, iclass 7, count 0 2006.201.12:51:53.25#ibcon#read 3, iclass 7, count 0 2006.201.12:51:53.25#ibcon#about to read 4, iclass 7, count 0 2006.201.12:51:53.25#ibcon#read 4, iclass 7, count 0 2006.201.12:51:53.25#ibcon#about to read 5, iclass 7, count 0 2006.201.12:51:53.25#ibcon#read 5, iclass 7, count 0 2006.201.12:51:53.25#ibcon#about to read 6, iclass 7, count 0 2006.201.12:51:53.25#ibcon#read 6, iclass 7, count 0 2006.201.12:51:53.25#ibcon#end of sib2, iclass 7, count 0 2006.201.12:51:53.25#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:51:53.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:51:53.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.12:51:53.25#ibcon#*before write, iclass 7, count 0 2006.201.12:51:53.25#ibcon#enter sib2, iclass 7, count 0 2006.201.12:51:53.25#ibcon#flushed, iclass 7, count 0 2006.201.12:51:53.25#ibcon#about to write, iclass 7, count 0 2006.201.12:51:53.25#ibcon#wrote, iclass 7, count 0 2006.201.12:51:53.25#ibcon#about to read 3, iclass 7, count 0 2006.201.12:51:53.29#ibcon#read 3, iclass 7, count 0 2006.201.12:51:53.29#ibcon#about to read 4, iclass 7, count 0 2006.201.12:51:53.29#ibcon#read 4, iclass 7, count 0 2006.201.12:51:53.29#ibcon#about to read 5, iclass 7, count 0 2006.201.12:51:53.29#ibcon#read 5, iclass 7, count 0 2006.201.12:51:53.29#ibcon#about to read 6, iclass 7, count 0 2006.201.12:51:53.29#ibcon#read 6, iclass 7, count 0 2006.201.12:51:53.29#ibcon#end of sib2, iclass 7, count 0 2006.201.12:51:53.29#ibcon#*after write, iclass 7, count 0 2006.201.12:51:53.29#ibcon#*before return 0, iclass 7, count 0 2006.201.12:51:53.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:53.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:53.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:51:53.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:51:53.29$vck44/va=2,7 2006.201.12:51:53.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.12:51:53.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.12:51:53.29#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:53.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:53.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:53.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:53.35#ibcon#enter wrdev, iclass 11, count 2 2006.201.12:51:53.35#ibcon#first serial, iclass 11, count 2 2006.201.12:51:53.35#ibcon#enter sib2, iclass 11, count 2 2006.201.12:51:53.35#ibcon#flushed, iclass 11, count 2 2006.201.12:51:53.35#ibcon#about to write, iclass 11, count 2 2006.201.12:51:53.35#ibcon#wrote, iclass 11, count 2 2006.201.12:51:53.35#ibcon#about to read 3, iclass 11, count 2 2006.201.12:51:53.37#ibcon#read 3, iclass 11, count 2 2006.201.12:51:53.37#ibcon#about to read 4, iclass 11, count 2 2006.201.12:51:53.37#ibcon#read 4, iclass 11, count 2 2006.201.12:51:53.37#ibcon#about to read 5, iclass 11, count 2 2006.201.12:51:53.37#ibcon#read 5, iclass 11, count 2 2006.201.12:51:53.37#ibcon#about to read 6, iclass 11, count 2 2006.201.12:51:53.37#ibcon#read 6, iclass 11, count 2 2006.201.12:51:53.37#ibcon#end of sib2, iclass 11, count 2 2006.201.12:51:53.37#ibcon#*mode == 0, iclass 11, count 2 2006.201.12:51:53.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.12:51:53.37#ibcon#[25=AT02-07\r\n] 2006.201.12:51:53.37#ibcon#*before write, iclass 11, count 2 2006.201.12:51:53.37#ibcon#enter sib2, iclass 11, count 2 2006.201.12:51:53.37#ibcon#flushed, iclass 11, count 2 2006.201.12:51:53.37#ibcon#about to write, iclass 11, count 2 2006.201.12:51:53.37#ibcon#wrote, iclass 11, count 2 2006.201.12:51:53.37#ibcon#about to read 3, iclass 11, count 2 2006.201.12:51:53.40#ibcon#read 3, iclass 11, count 2 2006.201.12:51:53.40#ibcon#about to read 4, iclass 11, count 2 2006.201.12:51:53.40#ibcon#read 4, iclass 11, count 2 2006.201.12:51:53.40#ibcon#about to read 5, iclass 11, count 2 2006.201.12:51:53.40#ibcon#read 5, iclass 11, count 2 2006.201.12:51:53.40#ibcon#about to read 6, iclass 11, count 2 2006.201.12:51:53.40#ibcon#read 6, iclass 11, count 2 2006.201.12:51:53.40#ibcon#end of sib2, iclass 11, count 2 2006.201.12:51:53.40#ibcon#*after write, iclass 11, count 2 2006.201.12:51:53.40#ibcon#*before return 0, iclass 11, count 2 2006.201.12:51:53.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:53.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:53.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.12:51:53.40#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:53.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:53.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:53.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:53.52#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:51:53.52#ibcon#first serial, iclass 11, count 0 2006.201.12:51:53.52#ibcon#enter sib2, iclass 11, count 0 2006.201.12:51:53.52#ibcon#flushed, iclass 11, count 0 2006.201.12:51:53.52#ibcon#about to write, iclass 11, count 0 2006.201.12:51:53.52#ibcon#wrote, iclass 11, count 0 2006.201.12:51:53.52#ibcon#about to read 3, iclass 11, count 0 2006.201.12:51:53.54#ibcon#read 3, iclass 11, count 0 2006.201.12:51:53.54#ibcon#about to read 4, iclass 11, count 0 2006.201.12:51:53.54#ibcon#read 4, iclass 11, count 0 2006.201.12:51:53.54#ibcon#about to read 5, iclass 11, count 0 2006.201.12:51:53.54#ibcon#read 5, iclass 11, count 0 2006.201.12:51:53.54#ibcon#about to read 6, iclass 11, count 0 2006.201.12:51:53.54#ibcon#read 6, iclass 11, count 0 2006.201.12:51:53.54#ibcon#end of sib2, iclass 11, count 0 2006.201.12:51:53.54#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:51:53.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:51:53.54#ibcon#[25=USB\r\n] 2006.201.12:51:53.54#ibcon#*before write, iclass 11, count 0 2006.201.12:51:53.54#ibcon#enter sib2, iclass 11, count 0 2006.201.12:51:53.54#ibcon#flushed, iclass 11, count 0 2006.201.12:51:53.54#ibcon#about to write, iclass 11, count 0 2006.201.12:51:53.54#ibcon#wrote, iclass 11, count 0 2006.201.12:51:53.54#ibcon#about to read 3, iclass 11, count 0 2006.201.12:51:53.57#ibcon#read 3, iclass 11, count 0 2006.201.12:51:53.57#ibcon#about to read 4, iclass 11, count 0 2006.201.12:51:53.57#ibcon#read 4, iclass 11, count 0 2006.201.12:51:53.57#ibcon#about to read 5, iclass 11, count 0 2006.201.12:51:53.57#ibcon#read 5, iclass 11, count 0 2006.201.12:51:53.57#ibcon#about to read 6, iclass 11, count 0 2006.201.12:51:53.57#ibcon#read 6, iclass 11, count 0 2006.201.12:51:53.57#ibcon#end of sib2, iclass 11, count 0 2006.201.12:51:53.57#ibcon#*after write, iclass 11, count 0 2006.201.12:51:53.57#ibcon#*before return 0, iclass 11, count 0 2006.201.12:51:53.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:53.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:53.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:51:53.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:51:53.57$vck44/valo=3,564.99 2006.201.12:51:53.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.12:51:53.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.12:51:53.57#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:53.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:53.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:53.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:53.57#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:51:53.57#ibcon#first serial, iclass 13, count 0 2006.201.12:51:53.57#ibcon#enter sib2, iclass 13, count 0 2006.201.12:51:53.57#ibcon#flushed, iclass 13, count 0 2006.201.12:51:53.57#ibcon#about to write, iclass 13, count 0 2006.201.12:51:53.57#ibcon#wrote, iclass 13, count 0 2006.201.12:51:53.57#ibcon#about to read 3, iclass 13, count 0 2006.201.12:51:53.59#ibcon#read 3, iclass 13, count 0 2006.201.12:51:53.59#ibcon#about to read 4, iclass 13, count 0 2006.201.12:51:53.59#ibcon#read 4, iclass 13, count 0 2006.201.12:51:53.59#ibcon#about to read 5, iclass 13, count 0 2006.201.12:51:53.59#ibcon#read 5, iclass 13, count 0 2006.201.12:51:53.59#ibcon#about to read 6, iclass 13, count 0 2006.201.12:51:53.59#ibcon#read 6, iclass 13, count 0 2006.201.12:51:53.59#ibcon#end of sib2, iclass 13, count 0 2006.201.12:51:53.59#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:51:53.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:51:53.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.12:51:53.59#ibcon#*before write, iclass 13, count 0 2006.201.12:51:53.59#ibcon#enter sib2, iclass 13, count 0 2006.201.12:51:53.59#ibcon#flushed, iclass 13, count 0 2006.201.12:51:53.59#ibcon#about to write, iclass 13, count 0 2006.201.12:51:53.59#ibcon#wrote, iclass 13, count 0 2006.201.12:51:53.59#ibcon#about to read 3, iclass 13, count 0 2006.201.12:51:53.64#ibcon#read 3, iclass 13, count 0 2006.201.12:51:53.64#ibcon#about to read 4, iclass 13, count 0 2006.201.12:51:53.64#ibcon#read 4, iclass 13, count 0 2006.201.12:51:53.64#ibcon#about to read 5, iclass 13, count 0 2006.201.12:51:53.64#ibcon#read 5, iclass 13, count 0 2006.201.12:51:53.64#ibcon#about to read 6, iclass 13, count 0 2006.201.12:51:53.64#ibcon#read 6, iclass 13, count 0 2006.201.12:51:53.64#ibcon#end of sib2, iclass 13, count 0 2006.201.12:51:53.64#ibcon#*after write, iclass 13, count 0 2006.201.12:51:53.64#ibcon#*before return 0, iclass 13, count 0 2006.201.12:51:53.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:53.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:53.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:51:53.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:51:53.64$vck44/va=3,8 2006.201.12:51:53.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.12:51:53.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.12:51:53.64#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:53.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:53.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:53.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:53.69#ibcon#enter wrdev, iclass 15, count 2 2006.201.12:51:53.69#ibcon#first serial, iclass 15, count 2 2006.201.12:51:53.69#ibcon#enter sib2, iclass 15, count 2 2006.201.12:51:53.69#ibcon#flushed, iclass 15, count 2 2006.201.12:51:53.69#ibcon#about to write, iclass 15, count 2 2006.201.12:51:53.69#ibcon#wrote, iclass 15, count 2 2006.201.12:51:53.69#ibcon#about to read 3, iclass 15, count 2 2006.201.12:51:53.71#ibcon#read 3, iclass 15, count 2 2006.201.12:51:53.71#ibcon#about to read 4, iclass 15, count 2 2006.201.12:51:53.71#ibcon#read 4, iclass 15, count 2 2006.201.12:51:53.71#ibcon#about to read 5, iclass 15, count 2 2006.201.12:51:53.71#ibcon#read 5, iclass 15, count 2 2006.201.12:51:53.71#ibcon#about to read 6, iclass 15, count 2 2006.201.12:51:53.71#ibcon#read 6, iclass 15, count 2 2006.201.12:51:53.71#ibcon#end of sib2, iclass 15, count 2 2006.201.12:51:53.71#ibcon#*mode == 0, iclass 15, count 2 2006.201.12:51:53.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.12:51:53.71#ibcon#[25=AT03-08\r\n] 2006.201.12:51:53.71#ibcon#*before write, iclass 15, count 2 2006.201.12:51:53.71#ibcon#enter sib2, iclass 15, count 2 2006.201.12:51:53.71#ibcon#flushed, iclass 15, count 2 2006.201.12:51:53.71#ibcon#about to write, iclass 15, count 2 2006.201.12:51:53.71#ibcon#wrote, iclass 15, count 2 2006.201.12:51:53.71#ibcon#about to read 3, iclass 15, count 2 2006.201.12:51:53.74#ibcon#read 3, iclass 15, count 2 2006.201.12:51:53.74#ibcon#about to read 4, iclass 15, count 2 2006.201.12:51:53.74#ibcon#read 4, iclass 15, count 2 2006.201.12:51:53.74#ibcon#about to read 5, iclass 15, count 2 2006.201.12:51:53.74#ibcon#read 5, iclass 15, count 2 2006.201.12:51:53.74#ibcon#about to read 6, iclass 15, count 2 2006.201.12:51:53.74#ibcon#read 6, iclass 15, count 2 2006.201.12:51:53.74#ibcon#end of sib2, iclass 15, count 2 2006.201.12:51:53.74#ibcon#*after write, iclass 15, count 2 2006.201.12:51:53.74#ibcon#*before return 0, iclass 15, count 2 2006.201.12:51:53.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:53.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:53.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.12:51:53.74#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:53.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:53.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:53.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:53.86#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:51:53.86#ibcon#first serial, iclass 15, count 0 2006.201.12:51:53.86#ibcon#enter sib2, iclass 15, count 0 2006.201.12:51:53.86#ibcon#flushed, iclass 15, count 0 2006.201.12:51:53.86#ibcon#about to write, iclass 15, count 0 2006.201.12:51:53.86#ibcon#wrote, iclass 15, count 0 2006.201.12:51:53.86#ibcon#about to read 3, iclass 15, count 0 2006.201.12:51:53.88#ibcon#read 3, iclass 15, count 0 2006.201.12:51:53.88#ibcon#about to read 4, iclass 15, count 0 2006.201.12:51:53.88#ibcon#read 4, iclass 15, count 0 2006.201.12:51:53.88#ibcon#about to read 5, iclass 15, count 0 2006.201.12:51:53.88#ibcon#read 5, iclass 15, count 0 2006.201.12:51:53.88#ibcon#about to read 6, iclass 15, count 0 2006.201.12:51:53.88#ibcon#read 6, iclass 15, count 0 2006.201.12:51:53.88#ibcon#end of sib2, iclass 15, count 0 2006.201.12:51:53.88#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:51:53.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:51:53.88#ibcon#[25=USB\r\n] 2006.201.12:51:53.88#ibcon#*before write, iclass 15, count 0 2006.201.12:51:53.88#ibcon#enter sib2, iclass 15, count 0 2006.201.12:51:53.88#ibcon#flushed, iclass 15, count 0 2006.201.12:51:53.88#ibcon#about to write, iclass 15, count 0 2006.201.12:51:53.88#ibcon#wrote, iclass 15, count 0 2006.201.12:51:53.88#ibcon#about to read 3, iclass 15, count 0 2006.201.12:51:53.91#ibcon#read 3, iclass 15, count 0 2006.201.12:51:53.91#ibcon#about to read 4, iclass 15, count 0 2006.201.12:51:53.91#ibcon#read 4, iclass 15, count 0 2006.201.12:51:53.91#ibcon#about to read 5, iclass 15, count 0 2006.201.12:51:53.91#ibcon#read 5, iclass 15, count 0 2006.201.12:51:53.91#ibcon#about to read 6, iclass 15, count 0 2006.201.12:51:53.91#ibcon#read 6, iclass 15, count 0 2006.201.12:51:53.91#ibcon#end of sib2, iclass 15, count 0 2006.201.12:51:53.91#ibcon#*after write, iclass 15, count 0 2006.201.12:51:53.91#ibcon#*before return 0, iclass 15, count 0 2006.201.12:51:53.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:53.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:53.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:51:53.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:51:53.91$vck44/valo=4,624.99 2006.201.12:51:53.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.12:51:53.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.12:51:53.91#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:53.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:53.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:53.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:53.91#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:51:53.91#ibcon#first serial, iclass 17, count 0 2006.201.12:51:53.91#ibcon#enter sib2, iclass 17, count 0 2006.201.12:51:53.91#ibcon#flushed, iclass 17, count 0 2006.201.12:51:53.91#ibcon#about to write, iclass 17, count 0 2006.201.12:51:53.91#ibcon#wrote, iclass 17, count 0 2006.201.12:51:53.91#ibcon#about to read 3, iclass 17, count 0 2006.201.12:51:53.93#ibcon#read 3, iclass 17, count 0 2006.201.12:51:53.93#ibcon#about to read 4, iclass 17, count 0 2006.201.12:51:53.93#ibcon#read 4, iclass 17, count 0 2006.201.12:51:53.93#ibcon#about to read 5, iclass 17, count 0 2006.201.12:51:53.93#ibcon#read 5, iclass 17, count 0 2006.201.12:51:53.93#ibcon#about to read 6, iclass 17, count 0 2006.201.12:51:53.93#ibcon#read 6, iclass 17, count 0 2006.201.12:51:53.93#ibcon#end of sib2, iclass 17, count 0 2006.201.12:51:53.93#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:51:53.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:51:53.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.12:51:53.93#ibcon#*before write, iclass 17, count 0 2006.201.12:51:53.93#ibcon#enter sib2, iclass 17, count 0 2006.201.12:51:53.93#ibcon#flushed, iclass 17, count 0 2006.201.12:51:53.93#ibcon#about to write, iclass 17, count 0 2006.201.12:51:53.93#ibcon#wrote, iclass 17, count 0 2006.201.12:51:53.93#ibcon#about to read 3, iclass 17, count 0 2006.201.12:51:53.98#ibcon#read 3, iclass 17, count 0 2006.201.12:51:53.98#ibcon#about to read 4, iclass 17, count 0 2006.201.12:51:53.98#ibcon#read 4, iclass 17, count 0 2006.201.12:51:53.98#ibcon#about to read 5, iclass 17, count 0 2006.201.12:51:53.98#ibcon#read 5, iclass 17, count 0 2006.201.12:51:53.98#ibcon#about to read 6, iclass 17, count 0 2006.201.12:51:53.98#ibcon#read 6, iclass 17, count 0 2006.201.12:51:53.98#ibcon#end of sib2, iclass 17, count 0 2006.201.12:51:53.98#ibcon#*after write, iclass 17, count 0 2006.201.12:51:53.98#ibcon#*before return 0, iclass 17, count 0 2006.201.12:51:53.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:53.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:53.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:51:53.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:51:53.98$vck44/va=4,7 2006.201.12:51:53.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.12:51:53.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.12:51:53.98#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:53.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:54.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:54.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:54.03#ibcon#enter wrdev, iclass 19, count 2 2006.201.12:51:54.03#ibcon#first serial, iclass 19, count 2 2006.201.12:51:54.03#ibcon#enter sib2, iclass 19, count 2 2006.201.12:51:54.03#ibcon#flushed, iclass 19, count 2 2006.201.12:51:54.03#ibcon#about to write, iclass 19, count 2 2006.201.12:51:54.03#ibcon#wrote, iclass 19, count 2 2006.201.12:51:54.03#ibcon#about to read 3, iclass 19, count 2 2006.201.12:51:54.05#ibcon#read 3, iclass 19, count 2 2006.201.12:51:54.05#ibcon#about to read 4, iclass 19, count 2 2006.201.12:51:54.05#ibcon#read 4, iclass 19, count 2 2006.201.12:51:54.05#ibcon#about to read 5, iclass 19, count 2 2006.201.12:51:54.05#ibcon#read 5, iclass 19, count 2 2006.201.12:51:54.05#ibcon#about to read 6, iclass 19, count 2 2006.201.12:51:54.05#ibcon#read 6, iclass 19, count 2 2006.201.12:51:54.05#ibcon#end of sib2, iclass 19, count 2 2006.201.12:51:54.05#ibcon#*mode == 0, iclass 19, count 2 2006.201.12:51:54.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.12:51:54.05#ibcon#[25=AT04-07\r\n] 2006.201.12:51:54.05#ibcon#*before write, iclass 19, count 2 2006.201.12:51:54.05#ibcon#enter sib2, iclass 19, count 2 2006.201.12:51:54.05#ibcon#flushed, iclass 19, count 2 2006.201.12:51:54.05#ibcon#about to write, iclass 19, count 2 2006.201.12:51:54.05#ibcon#wrote, iclass 19, count 2 2006.201.12:51:54.05#ibcon#about to read 3, iclass 19, count 2 2006.201.12:51:54.08#ibcon#read 3, iclass 19, count 2 2006.201.12:51:54.08#ibcon#about to read 4, iclass 19, count 2 2006.201.12:51:54.08#ibcon#read 4, iclass 19, count 2 2006.201.12:51:54.08#ibcon#about to read 5, iclass 19, count 2 2006.201.12:51:54.08#ibcon#read 5, iclass 19, count 2 2006.201.12:51:54.08#ibcon#about to read 6, iclass 19, count 2 2006.201.12:51:54.08#ibcon#read 6, iclass 19, count 2 2006.201.12:51:54.08#ibcon#end of sib2, iclass 19, count 2 2006.201.12:51:54.08#ibcon#*after write, iclass 19, count 2 2006.201.12:51:54.08#ibcon#*before return 0, iclass 19, count 2 2006.201.12:51:54.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:54.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:54.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.12:51:54.08#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:54.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:54.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:54.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:54.20#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:51:54.20#ibcon#first serial, iclass 19, count 0 2006.201.12:51:54.20#ibcon#enter sib2, iclass 19, count 0 2006.201.12:51:54.20#ibcon#flushed, iclass 19, count 0 2006.201.12:51:54.20#ibcon#about to write, iclass 19, count 0 2006.201.12:51:54.20#ibcon#wrote, iclass 19, count 0 2006.201.12:51:54.20#ibcon#about to read 3, iclass 19, count 0 2006.201.12:51:54.22#ibcon#read 3, iclass 19, count 0 2006.201.12:51:54.22#ibcon#about to read 4, iclass 19, count 0 2006.201.12:51:54.22#ibcon#read 4, iclass 19, count 0 2006.201.12:51:54.22#ibcon#about to read 5, iclass 19, count 0 2006.201.12:51:54.22#ibcon#read 5, iclass 19, count 0 2006.201.12:51:54.22#ibcon#about to read 6, iclass 19, count 0 2006.201.12:51:54.22#ibcon#read 6, iclass 19, count 0 2006.201.12:51:54.22#ibcon#end of sib2, iclass 19, count 0 2006.201.12:51:54.22#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:51:54.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:51:54.22#ibcon#[25=USB\r\n] 2006.201.12:51:54.22#ibcon#*before write, iclass 19, count 0 2006.201.12:51:54.22#ibcon#enter sib2, iclass 19, count 0 2006.201.12:51:54.22#ibcon#flushed, iclass 19, count 0 2006.201.12:51:54.22#ibcon#about to write, iclass 19, count 0 2006.201.12:51:54.22#ibcon#wrote, iclass 19, count 0 2006.201.12:51:54.22#ibcon#about to read 3, iclass 19, count 0 2006.201.12:51:54.25#ibcon#read 3, iclass 19, count 0 2006.201.12:51:54.25#ibcon#about to read 4, iclass 19, count 0 2006.201.12:51:54.25#ibcon#read 4, iclass 19, count 0 2006.201.12:51:54.25#ibcon#about to read 5, iclass 19, count 0 2006.201.12:51:54.25#ibcon#read 5, iclass 19, count 0 2006.201.12:51:54.25#ibcon#about to read 6, iclass 19, count 0 2006.201.12:51:54.25#ibcon#read 6, iclass 19, count 0 2006.201.12:51:54.25#ibcon#end of sib2, iclass 19, count 0 2006.201.12:51:54.25#ibcon#*after write, iclass 19, count 0 2006.201.12:51:54.25#ibcon#*before return 0, iclass 19, count 0 2006.201.12:51:54.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:54.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:54.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:51:54.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:51:54.25$vck44/valo=5,734.99 2006.201.12:51:54.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.12:51:54.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.12:51:54.25#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:54.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:54.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:54.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:54.25#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:51:54.25#ibcon#first serial, iclass 21, count 0 2006.201.12:51:54.25#ibcon#enter sib2, iclass 21, count 0 2006.201.12:51:54.25#ibcon#flushed, iclass 21, count 0 2006.201.12:51:54.25#ibcon#about to write, iclass 21, count 0 2006.201.12:51:54.25#ibcon#wrote, iclass 21, count 0 2006.201.12:51:54.25#ibcon#about to read 3, iclass 21, count 0 2006.201.12:51:54.27#ibcon#read 3, iclass 21, count 0 2006.201.12:51:54.27#ibcon#about to read 4, iclass 21, count 0 2006.201.12:51:54.27#ibcon#read 4, iclass 21, count 0 2006.201.12:51:54.27#ibcon#about to read 5, iclass 21, count 0 2006.201.12:51:54.27#ibcon#read 5, iclass 21, count 0 2006.201.12:51:54.27#ibcon#about to read 6, iclass 21, count 0 2006.201.12:51:54.27#ibcon#read 6, iclass 21, count 0 2006.201.12:51:54.27#ibcon#end of sib2, iclass 21, count 0 2006.201.12:51:54.27#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:51:54.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:51:54.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.12:51:54.27#ibcon#*before write, iclass 21, count 0 2006.201.12:51:54.27#ibcon#enter sib2, iclass 21, count 0 2006.201.12:51:54.27#ibcon#flushed, iclass 21, count 0 2006.201.12:51:54.27#ibcon#about to write, iclass 21, count 0 2006.201.12:51:54.27#ibcon#wrote, iclass 21, count 0 2006.201.12:51:54.27#ibcon#about to read 3, iclass 21, count 0 2006.201.12:51:54.31#ibcon#read 3, iclass 21, count 0 2006.201.12:51:54.31#ibcon#about to read 4, iclass 21, count 0 2006.201.12:51:54.31#ibcon#read 4, iclass 21, count 0 2006.201.12:51:54.31#ibcon#about to read 5, iclass 21, count 0 2006.201.12:51:54.31#ibcon#read 5, iclass 21, count 0 2006.201.12:51:54.31#ibcon#about to read 6, iclass 21, count 0 2006.201.12:51:54.31#ibcon#read 6, iclass 21, count 0 2006.201.12:51:54.31#ibcon#end of sib2, iclass 21, count 0 2006.201.12:51:54.31#ibcon#*after write, iclass 21, count 0 2006.201.12:51:54.31#ibcon#*before return 0, iclass 21, count 0 2006.201.12:51:54.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:54.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:54.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:51:54.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:51:54.31$vck44/va=5,4 2006.201.12:51:54.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.12:51:54.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.12:51:54.31#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:54.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:54.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:54.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:54.37#ibcon#enter wrdev, iclass 23, count 2 2006.201.12:51:54.37#ibcon#first serial, iclass 23, count 2 2006.201.12:51:54.37#ibcon#enter sib2, iclass 23, count 2 2006.201.12:51:54.37#ibcon#flushed, iclass 23, count 2 2006.201.12:51:54.37#ibcon#about to write, iclass 23, count 2 2006.201.12:51:54.37#ibcon#wrote, iclass 23, count 2 2006.201.12:51:54.37#ibcon#about to read 3, iclass 23, count 2 2006.201.12:51:54.39#ibcon#read 3, iclass 23, count 2 2006.201.12:51:54.39#ibcon#about to read 4, iclass 23, count 2 2006.201.12:51:54.39#ibcon#read 4, iclass 23, count 2 2006.201.12:51:54.39#ibcon#about to read 5, iclass 23, count 2 2006.201.12:51:54.39#ibcon#read 5, iclass 23, count 2 2006.201.12:51:54.39#ibcon#about to read 6, iclass 23, count 2 2006.201.12:51:54.39#ibcon#read 6, iclass 23, count 2 2006.201.12:51:54.39#ibcon#end of sib2, iclass 23, count 2 2006.201.12:51:54.39#ibcon#*mode == 0, iclass 23, count 2 2006.201.12:51:54.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.12:51:54.39#ibcon#[25=AT05-04\r\n] 2006.201.12:51:54.39#ibcon#*before write, iclass 23, count 2 2006.201.12:51:54.39#ibcon#enter sib2, iclass 23, count 2 2006.201.12:51:54.39#ibcon#flushed, iclass 23, count 2 2006.201.12:51:54.39#ibcon#about to write, iclass 23, count 2 2006.201.12:51:54.39#ibcon#wrote, iclass 23, count 2 2006.201.12:51:54.39#ibcon#about to read 3, iclass 23, count 2 2006.201.12:51:54.42#ibcon#read 3, iclass 23, count 2 2006.201.12:51:54.42#ibcon#about to read 4, iclass 23, count 2 2006.201.12:51:54.42#ibcon#read 4, iclass 23, count 2 2006.201.12:51:54.42#ibcon#about to read 5, iclass 23, count 2 2006.201.12:51:54.42#ibcon#read 5, iclass 23, count 2 2006.201.12:51:54.42#ibcon#about to read 6, iclass 23, count 2 2006.201.12:51:54.42#ibcon#read 6, iclass 23, count 2 2006.201.12:51:54.42#ibcon#end of sib2, iclass 23, count 2 2006.201.12:51:54.42#ibcon#*after write, iclass 23, count 2 2006.201.12:51:54.42#ibcon#*before return 0, iclass 23, count 2 2006.201.12:51:54.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:54.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:54.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.12:51:54.42#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:54.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:54.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:54.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:54.54#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:51:54.54#ibcon#first serial, iclass 23, count 0 2006.201.12:51:54.54#ibcon#enter sib2, iclass 23, count 0 2006.201.12:51:54.54#ibcon#flushed, iclass 23, count 0 2006.201.12:51:54.54#ibcon#about to write, iclass 23, count 0 2006.201.12:51:54.54#ibcon#wrote, iclass 23, count 0 2006.201.12:51:54.54#ibcon#about to read 3, iclass 23, count 0 2006.201.12:51:54.56#ibcon#read 3, iclass 23, count 0 2006.201.12:51:54.56#ibcon#about to read 4, iclass 23, count 0 2006.201.12:51:54.56#ibcon#read 4, iclass 23, count 0 2006.201.12:51:54.56#ibcon#about to read 5, iclass 23, count 0 2006.201.12:51:54.56#ibcon#read 5, iclass 23, count 0 2006.201.12:51:54.56#ibcon#about to read 6, iclass 23, count 0 2006.201.12:51:54.56#ibcon#read 6, iclass 23, count 0 2006.201.12:51:54.56#ibcon#end of sib2, iclass 23, count 0 2006.201.12:51:54.56#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:51:54.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:51:54.56#ibcon#[25=USB\r\n] 2006.201.12:51:54.56#ibcon#*before write, iclass 23, count 0 2006.201.12:51:54.56#ibcon#enter sib2, iclass 23, count 0 2006.201.12:51:54.56#ibcon#flushed, iclass 23, count 0 2006.201.12:51:54.56#ibcon#about to write, iclass 23, count 0 2006.201.12:51:54.56#ibcon#wrote, iclass 23, count 0 2006.201.12:51:54.56#ibcon#about to read 3, iclass 23, count 0 2006.201.12:51:54.59#ibcon#read 3, iclass 23, count 0 2006.201.12:51:54.59#ibcon#about to read 4, iclass 23, count 0 2006.201.12:51:54.59#ibcon#read 4, iclass 23, count 0 2006.201.12:51:54.59#ibcon#about to read 5, iclass 23, count 0 2006.201.12:51:54.59#ibcon#read 5, iclass 23, count 0 2006.201.12:51:54.59#ibcon#about to read 6, iclass 23, count 0 2006.201.12:51:54.59#ibcon#read 6, iclass 23, count 0 2006.201.12:51:54.59#ibcon#end of sib2, iclass 23, count 0 2006.201.12:51:54.59#ibcon#*after write, iclass 23, count 0 2006.201.12:51:54.59#ibcon#*before return 0, iclass 23, count 0 2006.201.12:51:54.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:54.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:54.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:51:54.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:51:54.59$vck44/valo=6,814.99 2006.201.12:51:54.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.12:51:54.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.12:51:54.59#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:54.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:54.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:54.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:54.59#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:51:54.59#ibcon#first serial, iclass 25, count 0 2006.201.12:51:54.59#ibcon#enter sib2, iclass 25, count 0 2006.201.12:51:54.59#ibcon#flushed, iclass 25, count 0 2006.201.12:51:54.59#ibcon#about to write, iclass 25, count 0 2006.201.12:51:54.59#ibcon#wrote, iclass 25, count 0 2006.201.12:51:54.59#ibcon#about to read 3, iclass 25, count 0 2006.201.12:51:54.61#ibcon#read 3, iclass 25, count 0 2006.201.12:51:54.61#ibcon#about to read 4, iclass 25, count 0 2006.201.12:51:54.61#ibcon#read 4, iclass 25, count 0 2006.201.12:51:54.61#ibcon#about to read 5, iclass 25, count 0 2006.201.12:51:54.61#ibcon#read 5, iclass 25, count 0 2006.201.12:51:54.61#ibcon#about to read 6, iclass 25, count 0 2006.201.12:51:54.61#ibcon#read 6, iclass 25, count 0 2006.201.12:51:54.61#ibcon#end of sib2, iclass 25, count 0 2006.201.12:51:54.61#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:51:54.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:51:54.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.12:51:54.61#ibcon#*before write, iclass 25, count 0 2006.201.12:51:54.61#ibcon#enter sib2, iclass 25, count 0 2006.201.12:51:54.61#ibcon#flushed, iclass 25, count 0 2006.201.12:51:54.61#ibcon#about to write, iclass 25, count 0 2006.201.12:51:54.61#ibcon#wrote, iclass 25, count 0 2006.201.12:51:54.61#ibcon#about to read 3, iclass 25, count 0 2006.201.12:51:54.65#ibcon#read 3, iclass 25, count 0 2006.201.12:51:54.65#ibcon#about to read 4, iclass 25, count 0 2006.201.12:51:54.65#ibcon#read 4, iclass 25, count 0 2006.201.12:51:54.65#ibcon#about to read 5, iclass 25, count 0 2006.201.12:51:54.65#ibcon#read 5, iclass 25, count 0 2006.201.12:51:54.65#ibcon#about to read 6, iclass 25, count 0 2006.201.12:51:54.65#ibcon#read 6, iclass 25, count 0 2006.201.12:51:54.65#ibcon#end of sib2, iclass 25, count 0 2006.201.12:51:54.65#ibcon#*after write, iclass 25, count 0 2006.201.12:51:54.65#ibcon#*before return 0, iclass 25, count 0 2006.201.12:51:54.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:54.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:54.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:51:54.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:51:54.65$vck44/va=6,5 2006.201.12:51:54.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.12:51:54.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.12:51:54.65#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:54.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:54.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:54.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:54.71#ibcon#enter wrdev, iclass 27, count 2 2006.201.12:51:54.71#ibcon#first serial, iclass 27, count 2 2006.201.12:51:54.71#ibcon#enter sib2, iclass 27, count 2 2006.201.12:51:54.71#ibcon#flushed, iclass 27, count 2 2006.201.12:51:54.71#ibcon#about to write, iclass 27, count 2 2006.201.12:51:54.71#ibcon#wrote, iclass 27, count 2 2006.201.12:51:54.71#ibcon#about to read 3, iclass 27, count 2 2006.201.12:51:54.73#ibcon#read 3, iclass 27, count 2 2006.201.12:51:54.73#ibcon#about to read 4, iclass 27, count 2 2006.201.12:51:54.73#ibcon#read 4, iclass 27, count 2 2006.201.12:51:54.73#ibcon#about to read 5, iclass 27, count 2 2006.201.12:51:54.73#ibcon#read 5, iclass 27, count 2 2006.201.12:51:54.73#ibcon#about to read 6, iclass 27, count 2 2006.201.12:51:54.73#ibcon#read 6, iclass 27, count 2 2006.201.12:51:54.73#ibcon#end of sib2, iclass 27, count 2 2006.201.12:51:54.73#ibcon#*mode == 0, iclass 27, count 2 2006.201.12:51:54.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.12:51:54.73#ibcon#[25=AT06-05\r\n] 2006.201.12:51:54.73#ibcon#*before write, iclass 27, count 2 2006.201.12:51:54.73#ibcon#enter sib2, iclass 27, count 2 2006.201.12:51:54.73#ibcon#flushed, iclass 27, count 2 2006.201.12:51:54.73#ibcon#about to write, iclass 27, count 2 2006.201.12:51:54.73#ibcon#wrote, iclass 27, count 2 2006.201.12:51:54.73#ibcon#about to read 3, iclass 27, count 2 2006.201.12:51:54.76#ibcon#read 3, iclass 27, count 2 2006.201.12:51:54.76#ibcon#about to read 4, iclass 27, count 2 2006.201.12:51:54.76#ibcon#read 4, iclass 27, count 2 2006.201.12:51:54.76#ibcon#about to read 5, iclass 27, count 2 2006.201.12:51:54.76#ibcon#read 5, iclass 27, count 2 2006.201.12:51:54.76#ibcon#about to read 6, iclass 27, count 2 2006.201.12:51:54.76#ibcon#read 6, iclass 27, count 2 2006.201.12:51:54.76#ibcon#end of sib2, iclass 27, count 2 2006.201.12:51:54.76#ibcon#*after write, iclass 27, count 2 2006.201.12:51:54.76#ibcon#*before return 0, iclass 27, count 2 2006.201.12:51:54.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:54.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:54.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.12:51:54.76#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:54.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:54.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:54.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:54.88#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:51:54.88#ibcon#first serial, iclass 27, count 0 2006.201.12:51:54.88#ibcon#enter sib2, iclass 27, count 0 2006.201.12:51:54.88#ibcon#flushed, iclass 27, count 0 2006.201.12:51:54.88#ibcon#about to write, iclass 27, count 0 2006.201.12:51:54.88#ibcon#wrote, iclass 27, count 0 2006.201.12:51:54.88#ibcon#about to read 3, iclass 27, count 0 2006.201.12:51:54.90#ibcon#read 3, iclass 27, count 0 2006.201.12:51:54.90#ibcon#about to read 4, iclass 27, count 0 2006.201.12:51:54.90#ibcon#read 4, iclass 27, count 0 2006.201.12:51:54.90#ibcon#about to read 5, iclass 27, count 0 2006.201.12:51:54.90#ibcon#read 5, iclass 27, count 0 2006.201.12:51:54.90#ibcon#about to read 6, iclass 27, count 0 2006.201.12:51:54.90#ibcon#read 6, iclass 27, count 0 2006.201.12:51:54.90#ibcon#end of sib2, iclass 27, count 0 2006.201.12:51:54.90#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:51:54.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:51:54.90#ibcon#[25=USB\r\n] 2006.201.12:51:54.90#ibcon#*before write, iclass 27, count 0 2006.201.12:51:54.90#ibcon#enter sib2, iclass 27, count 0 2006.201.12:51:54.90#ibcon#flushed, iclass 27, count 0 2006.201.12:51:54.90#ibcon#about to write, iclass 27, count 0 2006.201.12:51:54.90#ibcon#wrote, iclass 27, count 0 2006.201.12:51:54.90#ibcon#about to read 3, iclass 27, count 0 2006.201.12:51:54.93#ibcon#read 3, iclass 27, count 0 2006.201.12:51:54.93#ibcon#about to read 4, iclass 27, count 0 2006.201.12:51:54.93#ibcon#read 4, iclass 27, count 0 2006.201.12:51:54.93#ibcon#about to read 5, iclass 27, count 0 2006.201.12:51:54.93#ibcon#read 5, iclass 27, count 0 2006.201.12:51:54.93#ibcon#about to read 6, iclass 27, count 0 2006.201.12:51:54.93#ibcon#read 6, iclass 27, count 0 2006.201.12:51:54.93#ibcon#end of sib2, iclass 27, count 0 2006.201.12:51:54.93#ibcon#*after write, iclass 27, count 0 2006.201.12:51:54.93#ibcon#*before return 0, iclass 27, count 0 2006.201.12:51:54.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:54.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:54.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:51:54.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:51:54.93$vck44/valo=7,864.99 2006.201.12:51:54.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.12:51:54.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.12:51:54.93#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:54.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:54.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:54.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:54.93#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:51:54.93#ibcon#first serial, iclass 29, count 0 2006.201.12:51:54.93#ibcon#enter sib2, iclass 29, count 0 2006.201.12:51:54.93#ibcon#flushed, iclass 29, count 0 2006.201.12:51:54.93#ibcon#about to write, iclass 29, count 0 2006.201.12:51:54.93#ibcon#wrote, iclass 29, count 0 2006.201.12:51:54.93#ibcon#about to read 3, iclass 29, count 0 2006.201.12:51:54.95#ibcon#read 3, iclass 29, count 0 2006.201.12:51:54.95#ibcon#about to read 4, iclass 29, count 0 2006.201.12:51:54.95#ibcon#read 4, iclass 29, count 0 2006.201.12:51:54.95#ibcon#about to read 5, iclass 29, count 0 2006.201.12:51:54.95#ibcon#read 5, iclass 29, count 0 2006.201.12:51:54.95#ibcon#about to read 6, iclass 29, count 0 2006.201.12:51:54.95#ibcon#read 6, iclass 29, count 0 2006.201.12:51:54.95#ibcon#end of sib2, iclass 29, count 0 2006.201.12:51:54.95#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:51:54.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:51:54.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.12:51:54.95#ibcon#*before write, iclass 29, count 0 2006.201.12:51:54.95#ibcon#enter sib2, iclass 29, count 0 2006.201.12:51:54.95#ibcon#flushed, iclass 29, count 0 2006.201.12:51:54.95#ibcon#about to write, iclass 29, count 0 2006.201.12:51:54.95#ibcon#wrote, iclass 29, count 0 2006.201.12:51:54.95#ibcon#about to read 3, iclass 29, count 0 2006.201.12:51:54.99#ibcon#read 3, iclass 29, count 0 2006.201.12:51:54.99#ibcon#about to read 4, iclass 29, count 0 2006.201.12:51:54.99#ibcon#read 4, iclass 29, count 0 2006.201.12:51:54.99#ibcon#about to read 5, iclass 29, count 0 2006.201.12:51:54.99#ibcon#read 5, iclass 29, count 0 2006.201.12:51:54.99#ibcon#about to read 6, iclass 29, count 0 2006.201.12:51:54.99#ibcon#read 6, iclass 29, count 0 2006.201.12:51:54.99#ibcon#end of sib2, iclass 29, count 0 2006.201.12:51:54.99#ibcon#*after write, iclass 29, count 0 2006.201.12:51:54.99#ibcon#*before return 0, iclass 29, count 0 2006.201.12:51:54.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:54.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:54.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:51:54.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:51:54.99$vck44/va=7,5 2006.201.12:51:54.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.12:51:54.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.12:51:54.99#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:54.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:55.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:55.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:55.05#ibcon#enter wrdev, iclass 31, count 2 2006.201.12:51:55.05#ibcon#first serial, iclass 31, count 2 2006.201.12:51:55.05#ibcon#enter sib2, iclass 31, count 2 2006.201.12:51:55.05#ibcon#flushed, iclass 31, count 2 2006.201.12:51:55.05#ibcon#about to write, iclass 31, count 2 2006.201.12:51:55.05#ibcon#wrote, iclass 31, count 2 2006.201.12:51:55.05#ibcon#about to read 3, iclass 31, count 2 2006.201.12:51:55.07#ibcon#read 3, iclass 31, count 2 2006.201.12:51:55.07#ibcon#about to read 4, iclass 31, count 2 2006.201.12:51:55.07#ibcon#read 4, iclass 31, count 2 2006.201.12:51:55.07#ibcon#about to read 5, iclass 31, count 2 2006.201.12:51:55.07#ibcon#read 5, iclass 31, count 2 2006.201.12:51:55.07#ibcon#about to read 6, iclass 31, count 2 2006.201.12:51:55.07#ibcon#read 6, iclass 31, count 2 2006.201.12:51:55.07#ibcon#end of sib2, iclass 31, count 2 2006.201.12:51:55.07#ibcon#*mode == 0, iclass 31, count 2 2006.201.12:51:55.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.12:51:55.07#ibcon#[25=AT07-05\r\n] 2006.201.12:51:55.07#ibcon#*before write, iclass 31, count 2 2006.201.12:51:55.07#ibcon#enter sib2, iclass 31, count 2 2006.201.12:51:55.07#ibcon#flushed, iclass 31, count 2 2006.201.12:51:55.07#ibcon#about to write, iclass 31, count 2 2006.201.12:51:55.07#ibcon#wrote, iclass 31, count 2 2006.201.12:51:55.07#ibcon#about to read 3, iclass 31, count 2 2006.201.12:51:55.10#ibcon#read 3, iclass 31, count 2 2006.201.12:51:55.10#ibcon#about to read 4, iclass 31, count 2 2006.201.12:51:55.10#ibcon#read 4, iclass 31, count 2 2006.201.12:51:55.10#ibcon#about to read 5, iclass 31, count 2 2006.201.12:51:55.10#ibcon#read 5, iclass 31, count 2 2006.201.12:51:55.10#ibcon#about to read 6, iclass 31, count 2 2006.201.12:51:55.10#ibcon#read 6, iclass 31, count 2 2006.201.12:51:55.10#ibcon#end of sib2, iclass 31, count 2 2006.201.12:51:55.10#ibcon#*after write, iclass 31, count 2 2006.201.12:51:55.10#ibcon#*before return 0, iclass 31, count 2 2006.201.12:51:55.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:55.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:55.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.12:51:55.10#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:55.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:55.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:55.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:55.22#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:51:55.22#ibcon#first serial, iclass 31, count 0 2006.201.12:51:55.22#ibcon#enter sib2, iclass 31, count 0 2006.201.12:51:55.22#ibcon#flushed, iclass 31, count 0 2006.201.12:51:55.22#ibcon#about to write, iclass 31, count 0 2006.201.12:51:55.22#ibcon#wrote, iclass 31, count 0 2006.201.12:51:55.22#ibcon#about to read 3, iclass 31, count 0 2006.201.12:51:55.24#ibcon#read 3, iclass 31, count 0 2006.201.12:51:55.24#ibcon#about to read 4, iclass 31, count 0 2006.201.12:51:55.24#ibcon#read 4, iclass 31, count 0 2006.201.12:51:55.24#ibcon#about to read 5, iclass 31, count 0 2006.201.12:51:55.24#ibcon#read 5, iclass 31, count 0 2006.201.12:51:55.24#ibcon#about to read 6, iclass 31, count 0 2006.201.12:51:55.24#ibcon#read 6, iclass 31, count 0 2006.201.12:51:55.24#ibcon#end of sib2, iclass 31, count 0 2006.201.12:51:55.24#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:51:55.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:51:55.24#ibcon#[25=USB\r\n] 2006.201.12:51:55.24#ibcon#*before write, iclass 31, count 0 2006.201.12:51:55.24#ibcon#enter sib2, iclass 31, count 0 2006.201.12:51:55.24#ibcon#flushed, iclass 31, count 0 2006.201.12:51:55.24#ibcon#about to write, iclass 31, count 0 2006.201.12:51:55.24#ibcon#wrote, iclass 31, count 0 2006.201.12:51:55.24#ibcon#about to read 3, iclass 31, count 0 2006.201.12:51:55.27#ibcon#read 3, iclass 31, count 0 2006.201.12:51:55.27#ibcon#about to read 4, iclass 31, count 0 2006.201.12:51:55.27#ibcon#read 4, iclass 31, count 0 2006.201.12:51:55.27#ibcon#about to read 5, iclass 31, count 0 2006.201.12:51:55.27#ibcon#read 5, iclass 31, count 0 2006.201.12:51:55.27#ibcon#about to read 6, iclass 31, count 0 2006.201.12:51:55.27#ibcon#read 6, iclass 31, count 0 2006.201.12:51:55.27#ibcon#end of sib2, iclass 31, count 0 2006.201.12:51:55.27#ibcon#*after write, iclass 31, count 0 2006.201.12:51:55.27#ibcon#*before return 0, iclass 31, count 0 2006.201.12:51:55.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:55.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:55.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:51:55.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:51:55.27$vck44/valo=8,884.99 2006.201.12:51:55.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.12:51:55.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.12:51:55.27#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:55.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:55.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:55.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:55.27#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:51:55.27#ibcon#first serial, iclass 33, count 0 2006.201.12:51:55.27#ibcon#enter sib2, iclass 33, count 0 2006.201.12:51:55.27#ibcon#flushed, iclass 33, count 0 2006.201.12:51:55.27#ibcon#about to write, iclass 33, count 0 2006.201.12:51:55.27#ibcon#wrote, iclass 33, count 0 2006.201.12:51:55.27#ibcon#about to read 3, iclass 33, count 0 2006.201.12:51:55.29#ibcon#read 3, iclass 33, count 0 2006.201.12:51:55.29#ibcon#about to read 4, iclass 33, count 0 2006.201.12:51:55.29#ibcon#read 4, iclass 33, count 0 2006.201.12:51:55.29#ibcon#about to read 5, iclass 33, count 0 2006.201.12:51:55.29#ibcon#read 5, iclass 33, count 0 2006.201.12:51:55.29#ibcon#about to read 6, iclass 33, count 0 2006.201.12:51:55.29#ibcon#read 6, iclass 33, count 0 2006.201.12:51:55.29#ibcon#end of sib2, iclass 33, count 0 2006.201.12:51:55.29#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:51:55.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:51:55.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.12:51:55.29#ibcon#*before write, iclass 33, count 0 2006.201.12:51:55.29#ibcon#enter sib2, iclass 33, count 0 2006.201.12:51:55.29#ibcon#flushed, iclass 33, count 0 2006.201.12:51:55.29#ibcon#about to write, iclass 33, count 0 2006.201.12:51:55.29#ibcon#wrote, iclass 33, count 0 2006.201.12:51:55.29#ibcon#about to read 3, iclass 33, count 0 2006.201.12:51:55.33#ibcon#read 3, iclass 33, count 0 2006.201.12:51:55.33#ibcon#about to read 4, iclass 33, count 0 2006.201.12:51:55.33#ibcon#read 4, iclass 33, count 0 2006.201.12:51:55.33#ibcon#about to read 5, iclass 33, count 0 2006.201.12:51:55.33#ibcon#read 5, iclass 33, count 0 2006.201.12:51:55.33#ibcon#about to read 6, iclass 33, count 0 2006.201.12:51:55.33#ibcon#read 6, iclass 33, count 0 2006.201.12:51:55.33#ibcon#end of sib2, iclass 33, count 0 2006.201.12:51:55.33#ibcon#*after write, iclass 33, count 0 2006.201.12:51:55.33#ibcon#*before return 0, iclass 33, count 0 2006.201.12:51:55.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:55.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:55.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:51:55.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:51:55.33$vck44/va=8,4 2006.201.12:51:55.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.12:51:55.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.12:51:55.33#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:55.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:51:55.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:51:55.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:51:55.39#ibcon#enter wrdev, iclass 35, count 2 2006.201.12:51:55.39#ibcon#first serial, iclass 35, count 2 2006.201.12:51:55.39#ibcon#enter sib2, iclass 35, count 2 2006.201.12:51:55.39#ibcon#flushed, iclass 35, count 2 2006.201.12:51:55.39#ibcon#about to write, iclass 35, count 2 2006.201.12:51:55.39#ibcon#wrote, iclass 35, count 2 2006.201.12:51:55.39#ibcon#about to read 3, iclass 35, count 2 2006.201.12:51:55.41#ibcon#read 3, iclass 35, count 2 2006.201.12:51:55.41#ibcon#about to read 4, iclass 35, count 2 2006.201.12:51:55.41#ibcon#read 4, iclass 35, count 2 2006.201.12:51:55.41#ibcon#about to read 5, iclass 35, count 2 2006.201.12:51:55.41#ibcon#read 5, iclass 35, count 2 2006.201.12:51:55.41#ibcon#about to read 6, iclass 35, count 2 2006.201.12:51:55.41#ibcon#read 6, iclass 35, count 2 2006.201.12:51:55.41#ibcon#end of sib2, iclass 35, count 2 2006.201.12:51:55.41#ibcon#*mode == 0, iclass 35, count 2 2006.201.12:51:55.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.12:51:55.41#ibcon#[25=AT08-04\r\n] 2006.201.12:51:55.41#ibcon#*before write, iclass 35, count 2 2006.201.12:51:55.41#ibcon#enter sib2, iclass 35, count 2 2006.201.12:51:55.41#ibcon#flushed, iclass 35, count 2 2006.201.12:51:55.41#ibcon#about to write, iclass 35, count 2 2006.201.12:51:55.41#ibcon#wrote, iclass 35, count 2 2006.201.12:51:55.41#ibcon#about to read 3, iclass 35, count 2 2006.201.12:51:55.44#ibcon#read 3, iclass 35, count 2 2006.201.12:51:55.44#ibcon#about to read 4, iclass 35, count 2 2006.201.12:51:55.44#ibcon#read 4, iclass 35, count 2 2006.201.12:51:55.44#ibcon#about to read 5, iclass 35, count 2 2006.201.12:51:55.44#ibcon#read 5, iclass 35, count 2 2006.201.12:51:55.44#ibcon#about to read 6, iclass 35, count 2 2006.201.12:51:55.44#ibcon#read 6, iclass 35, count 2 2006.201.12:51:55.44#ibcon#end of sib2, iclass 35, count 2 2006.201.12:51:55.44#ibcon#*after write, iclass 35, count 2 2006.201.12:51:55.44#ibcon#*before return 0, iclass 35, count 2 2006.201.12:51:55.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:51:55.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.12:51:55.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.12:51:55.44#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:55.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:51:55.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:51:55.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:51:55.56#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:51:55.56#ibcon#first serial, iclass 35, count 0 2006.201.12:51:55.56#ibcon#enter sib2, iclass 35, count 0 2006.201.12:51:55.56#ibcon#flushed, iclass 35, count 0 2006.201.12:51:55.56#ibcon#about to write, iclass 35, count 0 2006.201.12:51:55.56#ibcon#wrote, iclass 35, count 0 2006.201.12:51:55.56#ibcon#about to read 3, iclass 35, count 0 2006.201.12:51:55.58#ibcon#read 3, iclass 35, count 0 2006.201.12:51:55.58#ibcon#about to read 4, iclass 35, count 0 2006.201.12:51:55.58#ibcon#read 4, iclass 35, count 0 2006.201.12:51:55.58#ibcon#about to read 5, iclass 35, count 0 2006.201.12:51:55.58#ibcon#read 5, iclass 35, count 0 2006.201.12:51:55.58#ibcon#about to read 6, iclass 35, count 0 2006.201.12:51:55.58#ibcon#read 6, iclass 35, count 0 2006.201.12:51:55.58#ibcon#end of sib2, iclass 35, count 0 2006.201.12:51:55.58#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:51:55.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:51:55.58#ibcon#[25=USB\r\n] 2006.201.12:51:55.58#ibcon#*before write, iclass 35, count 0 2006.201.12:51:55.58#ibcon#enter sib2, iclass 35, count 0 2006.201.12:51:55.58#ibcon#flushed, iclass 35, count 0 2006.201.12:51:55.58#ibcon#about to write, iclass 35, count 0 2006.201.12:51:55.58#ibcon#wrote, iclass 35, count 0 2006.201.12:51:55.58#ibcon#about to read 3, iclass 35, count 0 2006.201.12:51:55.61#ibcon#read 3, iclass 35, count 0 2006.201.12:51:55.61#ibcon#about to read 4, iclass 35, count 0 2006.201.12:51:55.61#ibcon#read 4, iclass 35, count 0 2006.201.12:51:55.61#ibcon#about to read 5, iclass 35, count 0 2006.201.12:51:55.61#ibcon#read 5, iclass 35, count 0 2006.201.12:51:55.61#ibcon#about to read 6, iclass 35, count 0 2006.201.12:51:55.61#ibcon#read 6, iclass 35, count 0 2006.201.12:51:55.61#ibcon#end of sib2, iclass 35, count 0 2006.201.12:51:55.61#ibcon#*after write, iclass 35, count 0 2006.201.12:51:55.61#ibcon#*before return 0, iclass 35, count 0 2006.201.12:51:55.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:51:55.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.12:51:55.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:51:55.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:51:55.61$vck44/vblo=1,629.99 2006.201.12:51:55.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.12:51:55.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.12:51:55.61#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:55.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:51:55.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:51:55.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:51:55.61#ibcon#enter wrdev, iclass 37, count 0 2006.201.12:51:55.61#ibcon#first serial, iclass 37, count 0 2006.201.12:51:55.61#ibcon#enter sib2, iclass 37, count 0 2006.201.12:51:55.61#ibcon#flushed, iclass 37, count 0 2006.201.12:51:55.61#ibcon#about to write, iclass 37, count 0 2006.201.12:51:55.61#ibcon#wrote, iclass 37, count 0 2006.201.12:51:55.61#ibcon#about to read 3, iclass 37, count 0 2006.201.12:51:55.63#ibcon#read 3, iclass 37, count 0 2006.201.12:51:55.63#ibcon#about to read 4, iclass 37, count 0 2006.201.12:51:55.63#ibcon#read 4, iclass 37, count 0 2006.201.12:51:55.63#ibcon#about to read 5, iclass 37, count 0 2006.201.12:51:55.63#ibcon#read 5, iclass 37, count 0 2006.201.12:51:55.63#ibcon#about to read 6, iclass 37, count 0 2006.201.12:51:55.63#ibcon#read 6, iclass 37, count 0 2006.201.12:51:55.63#ibcon#end of sib2, iclass 37, count 0 2006.201.12:51:55.63#ibcon#*mode == 0, iclass 37, count 0 2006.201.12:51:55.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.12:51:55.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.12:51:55.63#ibcon#*before write, iclass 37, count 0 2006.201.12:51:55.63#ibcon#enter sib2, iclass 37, count 0 2006.201.12:51:55.63#ibcon#flushed, iclass 37, count 0 2006.201.12:51:55.63#ibcon#about to write, iclass 37, count 0 2006.201.12:51:55.63#ibcon#wrote, iclass 37, count 0 2006.201.12:51:55.63#ibcon#about to read 3, iclass 37, count 0 2006.201.12:51:55.67#ibcon#read 3, iclass 37, count 0 2006.201.12:51:55.67#ibcon#about to read 4, iclass 37, count 0 2006.201.12:51:55.67#ibcon#read 4, iclass 37, count 0 2006.201.12:51:55.67#ibcon#about to read 5, iclass 37, count 0 2006.201.12:51:55.67#ibcon#read 5, iclass 37, count 0 2006.201.12:51:55.67#ibcon#about to read 6, iclass 37, count 0 2006.201.12:51:55.67#ibcon#read 6, iclass 37, count 0 2006.201.12:51:55.67#ibcon#end of sib2, iclass 37, count 0 2006.201.12:51:55.67#ibcon#*after write, iclass 37, count 0 2006.201.12:51:55.67#ibcon#*before return 0, iclass 37, count 0 2006.201.12:51:55.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:51:55.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.12:51:55.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.12:51:55.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.12:51:55.67$vck44/vb=1,4 2006.201.12:51:55.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.12:51:55.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.12:51:55.67#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:55.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:51:55.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:51:55.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:51:55.67#ibcon#enter wrdev, iclass 39, count 2 2006.201.12:51:55.67#ibcon#first serial, iclass 39, count 2 2006.201.12:51:55.67#ibcon#enter sib2, iclass 39, count 2 2006.201.12:51:55.67#ibcon#flushed, iclass 39, count 2 2006.201.12:51:55.67#ibcon#about to write, iclass 39, count 2 2006.201.12:51:55.67#ibcon#wrote, iclass 39, count 2 2006.201.12:51:55.67#ibcon#about to read 3, iclass 39, count 2 2006.201.12:51:55.69#ibcon#read 3, iclass 39, count 2 2006.201.12:51:55.69#ibcon#about to read 4, iclass 39, count 2 2006.201.12:51:55.69#ibcon#read 4, iclass 39, count 2 2006.201.12:51:55.69#ibcon#about to read 5, iclass 39, count 2 2006.201.12:51:55.69#ibcon#read 5, iclass 39, count 2 2006.201.12:51:55.69#ibcon#about to read 6, iclass 39, count 2 2006.201.12:51:55.69#ibcon#read 6, iclass 39, count 2 2006.201.12:51:55.69#ibcon#end of sib2, iclass 39, count 2 2006.201.12:51:55.69#ibcon#*mode == 0, iclass 39, count 2 2006.201.12:51:55.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.12:51:55.69#ibcon#[27=AT01-04\r\n] 2006.201.12:51:55.69#ibcon#*before write, iclass 39, count 2 2006.201.12:51:55.69#ibcon#enter sib2, iclass 39, count 2 2006.201.12:51:55.69#ibcon#flushed, iclass 39, count 2 2006.201.12:51:55.69#ibcon#about to write, iclass 39, count 2 2006.201.12:51:55.69#ibcon#wrote, iclass 39, count 2 2006.201.12:51:55.69#ibcon#about to read 3, iclass 39, count 2 2006.201.12:51:55.72#ibcon#read 3, iclass 39, count 2 2006.201.12:51:55.72#ibcon#about to read 4, iclass 39, count 2 2006.201.12:51:55.72#ibcon#read 4, iclass 39, count 2 2006.201.12:51:55.72#ibcon#about to read 5, iclass 39, count 2 2006.201.12:51:55.72#ibcon#read 5, iclass 39, count 2 2006.201.12:51:55.72#ibcon#about to read 6, iclass 39, count 2 2006.201.12:51:55.72#ibcon#read 6, iclass 39, count 2 2006.201.12:51:55.72#ibcon#end of sib2, iclass 39, count 2 2006.201.12:51:55.72#ibcon#*after write, iclass 39, count 2 2006.201.12:51:55.72#ibcon#*before return 0, iclass 39, count 2 2006.201.12:51:55.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:51:55.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.12:51:55.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.12:51:55.72#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:55.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:51:55.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:51:55.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:51:55.84#ibcon#enter wrdev, iclass 39, count 0 2006.201.12:51:55.84#ibcon#first serial, iclass 39, count 0 2006.201.12:51:55.84#ibcon#enter sib2, iclass 39, count 0 2006.201.12:51:55.84#ibcon#flushed, iclass 39, count 0 2006.201.12:51:55.84#ibcon#about to write, iclass 39, count 0 2006.201.12:51:55.84#ibcon#wrote, iclass 39, count 0 2006.201.12:51:55.84#ibcon#about to read 3, iclass 39, count 0 2006.201.12:51:55.86#ibcon#read 3, iclass 39, count 0 2006.201.12:51:55.86#ibcon#about to read 4, iclass 39, count 0 2006.201.12:51:55.86#ibcon#read 4, iclass 39, count 0 2006.201.12:51:55.86#ibcon#about to read 5, iclass 39, count 0 2006.201.12:51:55.86#ibcon#read 5, iclass 39, count 0 2006.201.12:51:55.86#ibcon#about to read 6, iclass 39, count 0 2006.201.12:51:55.86#ibcon#read 6, iclass 39, count 0 2006.201.12:51:55.86#ibcon#end of sib2, iclass 39, count 0 2006.201.12:51:55.86#ibcon#*mode == 0, iclass 39, count 0 2006.201.12:51:55.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.12:51:55.86#ibcon#[27=USB\r\n] 2006.201.12:51:55.86#ibcon#*before write, iclass 39, count 0 2006.201.12:51:55.86#ibcon#enter sib2, iclass 39, count 0 2006.201.12:51:55.86#ibcon#flushed, iclass 39, count 0 2006.201.12:51:55.86#ibcon#about to write, iclass 39, count 0 2006.201.12:51:55.86#ibcon#wrote, iclass 39, count 0 2006.201.12:51:55.86#ibcon#about to read 3, iclass 39, count 0 2006.201.12:51:55.89#ibcon#read 3, iclass 39, count 0 2006.201.12:51:55.89#ibcon#about to read 4, iclass 39, count 0 2006.201.12:51:55.89#ibcon#read 4, iclass 39, count 0 2006.201.12:51:55.89#ibcon#about to read 5, iclass 39, count 0 2006.201.12:51:55.89#ibcon#read 5, iclass 39, count 0 2006.201.12:51:55.89#ibcon#about to read 6, iclass 39, count 0 2006.201.12:51:55.89#ibcon#read 6, iclass 39, count 0 2006.201.12:51:55.89#ibcon#end of sib2, iclass 39, count 0 2006.201.12:51:55.89#ibcon#*after write, iclass 39, count 0 2006.201.12:51:55.89#ibcon#*before return 0, iclass 39, count 0 2006.201.12:51:55.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:51:55.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.12:51:55.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.12:51:55.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.12:51:55.89$vck44/vblo=2,634.99 2006.201.12:51:55.89#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.12:51:55.89#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.12:51:55.89#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:55.89#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:55.89#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:55.89#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:55.89#ibcon#enter wrdev, iclass 2, count 0 2006.201.12:51:55.89#ibcon#first serial, iclass 2, count 0 2006.201.12:51:55.89#ibcon#enter sib2, iclass 2, count 0 2006.201.12:51:55.89#ibcon#flushed, iclass 2, count 0 2006.201.12:51:55.89#ibcon#about to write, iclass 2, count 0 2006.201.12:51:55.89#ibcon#wrote, iclass 2, count 0 2006.201.12:51:55.89#ibcon#about to read 3, iclass 2, count 0 2006.201.12:51:55.91#ibcon#read 3, iclass 2, count 0 2006.201.12:51:55.91#ibcon#about to read 4, iclass 2, count 0 2006.201.12:51:55.91#ibcon#read 4, iclass 2, count 0 2006.201.12:51:55.91#ibcon#about to read 5, iclass 2, count 0 2006.201.12:51:55.91#ibcon#read 5, iclass 2, count 0 2006.201.12:51:55.91#ibcon#about to read 6, iclass 2, count 0 2006.201.12:51:55.91#ibcon#read 6, iclass 2, count 0 2006.201.12:51:55.91#ibcon#end of sib2, iclass 2, count 0 2006.201.12:51:55.91#ibcon#*mode == 0, iclass 2, count 0 2006.201.12:51:55.91#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.12:51:55.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.12:51:55.91#ibcon#*before write, iclass 2, count 0 2006.201.12:51:55.91#ibcon#enter sib2, iclass 2, count 0 2006.201.12:51:55.91#ibcon#flushed, iclass 2, count 0 2006.201.12:51:55.91#ibcon#about to write, iclass 2, count 0 2006.201.12:51:55.91#ibcon#wrote, iclass 2, count 0 2006.201.12:51:55.91#ibcon#about to read 3, iclass 2, count 0 2006.201.12:51:55.95#ibcon#read 3, iclass 2, count 0 2006.201.12:51:55.95#ibcon#about to read 4, iclass 2, count 0 2006.201.12:51:55.95#ibcon#read 4, iclass 2, count 0 2006.201.12:51:55.95#ibcon#about to read 5, iclass 2, count 0 2006.201.12:51:55.95#ibcon#read 5, iclass 2, count 0 2006.201.12:51:55.95#ibcon#about to read 6, iclass 2, count 0 2006.201.12:51:55.95#ibcon#read 6, iclass 2, count 0 2006.201.12:51:55.95#ibcon#end of sib2, iclass 2, count 0 2006.201.12:51:55.95#ibcon#*after write, iclass 2, count 0 2006.201.12:51:55.95#ibcon#*before return 0, iclass 2, count 0 2006.201.12:51:55.95#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:55.95#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.12:51:55.95#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.12:51:55.95#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.12:51:55.95$vck44/vb=2,5 2006.201.12:51:55.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.12:51:55.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.12:51:55.95#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:55.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:56.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:56.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:56.01#ibcon#enter wrdev, iclass 5, count 2 2006.201.12:51:56.01#ibcon#first serial, iclass 5, count 2 2006.201.12:51:56.01#ibcon#enter sib2, iclass 5, count 2 2006.201.12:51:56.01#ibcon#flushed, iclass 5, count 2 2006.201.12:51:56.01#ibcon#about to write, iclass 5, count 2 2006.201.12:51:56.01#ibcon#wrote, iclass 5, count 2 2006.201.12:51:56.01#ibcon#about to read 3, iclass 5, count 2 2006.201.12:51:56.03#ibcon#read 3, iclass 5, count 2 2006.201.12:51:56.03#ibcon#about to read 4, iclass 5, count 2 2006.201.12:51:56.03#ibcon#read 4, iclass 5, count 2 2006.201.12:51:56.03#ibcon#about to read 5, iclass 5, count 2 2006.201.12:51:56.03#ibcon#read 5, iclass 5, count 2 2006.201.12:51:56.03#ibcon#about to read 6, iclass 5, count 2 2006.201.12:51:56.03#ibcon#read 6, iclass 5, count 2 2006.201.12:51:56.03#ibcon#end of sib2, iclass 5, count 2 2006.201.12:51:56.03#ibcon#*mode == 0, iclass 5, count 2 2006.201.12:51:56.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.12:51:56.03#ibcon#[27=AT02-05\r\n] 2006.201.12:51:56.03#ibcon#*before write, iclass 5, count 2 2006.201.12:51:56.03#ibcon#enter sib2, iclass 5, count 2 2006.201.12:51:56.03#ibcon#flushed, iclass 5, count 2 2006.201.12:51:56.03#ibcon#about to write, iclass 5, count 2 2006.201.12:51:56.03#ibcon#wrote, iclass 5, count 2 2006.201.12:51:56.03#ibcon#about to read 3, iclass 5, count 2 2006.201.12:51:56.06#ibcon#read 3, iclass 5, count 2 2006.201.12:51:56.06#ibcon#about to read 4, iclass 5, count 2 2006.201.12:51:56.06#ibcon#read 4, iclass 5, count 2 2006.201.12:51:56.06#ibcon#about to read 5, iclass 5, count 2 2006.201.12:51:56.06#ibcon#read 5, iclass 5, count 2 2006.201.12:51:56.06#ibcon#about to read 6, iclass 5, count 2 2006.201.12:51:56.06#ibcon#read 6, iclass 5, count 2 2006.201.12:51:56.06#ibcon#end of sib2, iclass 5, count 2 2006.201.12:51:56.06#ibcon#*after write, iclass 5, count 2 2006.201.12:51:56.06#ibcon#*before return 0, iclass 5, count 2 2006.201.12:51:56.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:56.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.12:51:56.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.12:51:56.06#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:56.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:56.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:56.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:56.18#ibcon#enter wrdev, iclass 5, count 0 2006.201.12:51:56.18#ibcon#first serial, iclass 5, count 0 2006.201.12:51:56.18#ibcon#enter sib2, iclass 5, count 0 2006.201.12:51:56.18#ibcon#flushed, iclass 5, count 0 2006.201.12:51:56.18#ibcon#about to write, iclass 5, count 0 2006.201.12:51:56.18#ibcon#wrote, iclass 5, count 0 2006.201.12:51:56.18#ibcon#about to read 3, iclass 5, count 0 2006.201.12:51:56.21#ibcon#read 3, iclass 5, count 0 2006.201.12:51:56.21#ibcon#about to read 4, iclass 5, count 0 2006.201.12:51:56.21#ibcon#read 4, iclass 5, count 0 2006.201.12:51:56.21#ibcon#about to read 5, iclass 5, count 0 2006.201.12:51:56.21#ibcon#read 5, iclass 5, count 0 2006.201.12:51:56.21#ibcon#about to read 6, iclass 5, count 0 2006.201.12:51:56.21#ibcon#read 6, iclass 5, count 0 2006.201.12:51:56.21#ibcon#end of sib2, iclass 5, count 0 2006.201.12:51:56.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.12:51:56.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.12:51:56.21#ibcon#[27=USB\r\n] 2006.201.12:51:56.21#ibcon#*before write, iclass 5, count 0 2006.201.12:51:56.21#ibcon#enter sib2, iclass 5, count 0 2006.201.12:51:56.21#ibcon#flushed, iclass 5, count 0 2006.201.12:51:56.21#ibcon#about to write, iclass 5, count 0 2006.201.12:51:56.21#ibcon#wrote, iclass 5, count 0 2006.201.12:51:56.21#ibcon#about to read 3, iclass 5, count 0 2006.201.12:51:56.24#ibcon#read 3, iclass 5, count 0 2006.201.12:51:56.24#ibcon#about to read 4, iclass 5, count 0 2006.201.12:51:56.24#ibcon#read 4, iclass 5, count 0 2006.201.12:51:56.24#ibcon#about to read 5, iclass 5, count 0 2006.201.12:51:56.24#ibcon#read 5, iclass 5, count 0 2006.201.12:51:56.24#ibcon#about to read 6, iclass 5, count 0 2006.201.12:51:56.24#ibcon#read 6, iclass 5, count 0 2006.201.12:51:56.24#ibcon#end of sib2, iclass 5, count 0 2006.201.12:51:56.24#ibcon#*after write, iclass 5, count 0 2006.201.12:51:56.24#ibcon#*before return 0, iclass 5, count 0 2006.201.12:51:56.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:56.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.12:51:56.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.12:51:56.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.12:51:56.24$vck44/vblo=3,649.99 2006.201.12:51:56.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.12:51:56.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.12:51:56.24#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:56.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:56.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:56.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:56.24#ibcon#enter wrdev, iclass 7, count 0 2006.201.12:51:56.24#ibcon#first serial, iclass 7, count 0 2006.201.12:51:56.24#ibcon#enter sib2, iclass 7, count 0 2006.201.12:51:56.24#ibcon#flushed, iclass 7, count 0 2006.201.12:51:56.24#ibcon#about to write, iclass 7, count 0 2006.201.12:51:56.24#ibcon#wrote, iclass 7, count 0 2006.201.12:51:56.24#ibcon#about to read 3, iclass 7, count 0 2006.201.12:51:56.26#ibcon#read 3, iclass 7, count 0 2006.201.12:51:56.26#ibcon#about to read 4, iclass 7, count 0 2006.201.12:51:56.26#ibcon#read 4, iclass 7, count 0 2006.201.12:51:56.26#ibcon#about to read 5, iclass 7, count 0 2006.201.12:51:56.26#ibcon#read 5, iclass 7, count 0 2006.201.12:51:56.26#ibcon#about to read 6, iclass 7, count 0 2006.201.12:51:56.26#ibcon#read 6, iclass 7, count 0 2006.201.12:51:56.26#ibcon#end of sib2, iclass 7, count 0 2006.201.12:51:56.26#ibcon#*mode == 0, iclass 7, count 0 2006.201.12:51:56.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.12:51:56.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.12:51:56.26#ibcon#*before write, iclass 7, count 0 2006.201.12:51:56.26#ibcon#enter sib2, iclass 7, count 0 2006.201.12:51:56.26#ibcon#flushed, iclass 7, count 0 2006.201.12:51:56.26#ibcon#about to write, iclass 7, count 0 2006.201.12:51:56.26#ibcon#wrote, iclass 7, count 0 2006.201.12:51:56.26#ibcon#about to read 3, iclass 7, count 0 2006.201.12:51:56.30#ibcon#read 3, iclass 7, count 0 2006.201.12:51:56.30#ibcon#about to read 4, iclass 7, count 0 2006.201.12:51:56.30#ibcon#read 4, iclass 7, count 0 2006.201.12:51:56.30#ibcon#about to read 5, iclass 7, count 0 2006.201.12:51:56.30#ibcon#read 5, iclass 7, count 0 2006.201.12:51:56.30#ibcon#about to read 6, iclass 7, count 0 2006.201.12:51:56.30#ibcon#read 6, iclass 7, count 0 2006.201.12:51:56.30#ibcon#end of sib2, iclass 7, count 0 2006.201.12:51:56.30#ibcon#*after write, iclass 7, count 0 2006.201.12:51:56.30#ibcon#*before return 0, iclass 7, count 0 2006.201.12:51:56.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:56.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.12:51:56.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.12:51:56.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.12:51:56.30$vck44/vb=3,4 2006.201.12:51:56.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.12:51:56.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.12:51:56.30#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:56.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:56.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:56.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:56.36#ibcon#enter wrdev, iclass 11, count 2 2006.201.12:51:56.36#ibcon#first serial, iclass 11, count 2 2006.201.12:51:56.36#ibcon#enter sib2, iclass 11, count 2 2006.201.12:51:56.36#ibcon#flushed, iclass 11, count 2 2006.201.12:51:56.36#ibcon#about to write, iclass 11, count 2 2006.201.12:51:56.36#ibcon#wrote, iclass 11, count 2 2006.201.12:51:56.36#ibcon#about to read 3, iclass 11, count 2 2006.201.12:51:56.38#ibcon#read 3, iclass 11, count 2 2006.201.12:51:56.38#ibcon#about to read 4, iclass 11, count 2 2006.201.12:51:56.38#ibcon#read 4, iclass 11, count 2 2006.201.12:51:56.38#ibcon#about to read 5, iclass 11, count 2 2006.201.12:51:56.38#ibcon#read 5, iclass 11, count 2 2006.201.12:51:56.38#ibcon#about to read 6, iclass 11, count 2 2006.201.12:51:56.38#ibcon#read 6, iclass 11, count 2 2006.201.12:51:56.38#ibcon#end of sib2, iclass 11, count 2 2006.201.12:51:56.38#ibcon#*mode == 0, iclass 11, count 2 2006.201.12:51:56.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.12:51:56.38#ibcon#[27=AT03-04\r\n] 2006.201.12:51:56.38#ibcon#*before write, iclass 11, count 2 2006.201.12:51:56.38#ibcon#enter sib2, iclass 11, count 2 2006.201.12:51:56.38#ibcon#flushed, iclass 11, count 2 2006.201.12:51:56.38#ibcon#about to write, iclass 11, count 2 2006.201.12:51:56.38#ibcon#wrote, iclass 11, count 2 2006.201.12:51:56.38#ibcon#about to read 3, iclass 11, count 2 2006.201.12:51:56.41#ibcon#read 3, iclass 11, count 2 2006.201.12:51:56.41#ibcon#about to read 4, iclass 11, count 2 2006.201.12:51:56.41#ibcon#read 4, iclass 11, count 2 2006.201.12:51:56.41#ibcon#about to read 5, iclass 11, count 2 2006.201.12:51:56.41#ibcon#read 5, iclass 11, count 2 2006.201.12:51:56.41#ibcon#about to read 6, iclass 11, count 2 2006.201.12:51:56.41#ibcon#read 6, iclass 11, count 2 2006.201.12:51:56.41#ibcon#end of sib2, iclass 11, count 2 2006.201.12:51:56.41#ibcon#*after write, iclass 11, count 2 2006.201.12:51:56.41#ibcon#*before return 0, iclass 11, count 2 2006.201.12:51:56.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:56.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.12:51:56.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.12:51:56.41#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:56.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:56.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:56.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:56.53#ibcon#enter wrdev, iclass 11, count 0 2006.201.12:51:56.53#ibcon#first serial, iclass 11, count 0 2006.201.12:51:56.53#ibcon#enter sib2, iclass 11, count 0 2006.201.12:51:56.53#ibcon#flushed, iclass 11, count 0 2006.201.12:51:56.53#ibcon#about to write, iclass 11, count 0 2006.201.12:51:56.53#ibcon#wrote, iclass 11, count 0 2006.201.12:51:56.53#ibcon#about to read 3, iclass 11, count 0 2006.201.12:51:56.55#ibcon#read 3, iclass 11, count 0 2006.201.12:51:56.55#ibcon#about to read 4, iclass 11, count 0 2006.201.12:51:56.55#ibcon#read 4, iclass 11, count 0 2006.201.12:51:56.55#ibcon#about to read 5, iclass 11, count 0 2006.201.12:51:56.55#ibcon#read 5, iclass 11, count 0 2006.201.12:51:56.55#ibcon#about to read 6, iclass 11, count 0 2006.201.12:51:56.55#ibcon#read 6, iclass 11, count 0 2006.201.12:51:56.55#ibcon#end of sib2, iclass 11, count 0 2006.201.12:51:56.55#ibcon#*mode == 0, iclass 11, count 0 2006.201.12:51:56.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.12:51:56.55#ibcon#[27=USB\r\n] 2006.201.12:51:56.55#ibcon#*before write, iclass 11, count 0 2006.201.12:51:56.55#ibcon#enter sib2, iclass 11, count 0 2006.201.12:51:56.55#ibcon#flushed, iclass 11, count 0 2006.201.12:51:56.55#ibcon#about to write, iclass 11, count 0 2006.201.12:51:56.55#ibcon#wrote, iclass 11, count 0 2006.201.12:51:56.55#ibcon#about to read 3, iclass 11, count 0 2006.201.12:51:56.58#ibcon#read 3, iclass 11, count 0 2006.201.12:51:56.58#ibcon#about to read 4, iclass 11, count 0 2006.201.12:51:56.58#ibcon#read 4, iclass 11, count 0 2006.201.12:51:56.58#ibcon#about to read 5, iclass 11, count 0 2006.201.12:51:56.58#ibcon#read 5, iclass 11, count 0 2006.201.12:51:56.58#ibcon#about to read 6, iclass 11, count 0 2006.201.12:51:56.58#ibcon#read 6, iclass 11, count 0 2006.201.12:51:56.58#ibcon#end of sib2, iclass 11, count 0 2006.201.12:51:56.58#ibcon#*after write, iclass 11, count 0 2006.201.12:51:56.58#ibcon#*before return 0, iclass 11, count 0 2006.201.12:51:56.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:56.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.12:51:56.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.12:51:56.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.12:51:56.58$vck44/vblo=4,679.99 2006.201.12:51:56.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.12:51:56.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.12:51:56.58#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:56.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:56.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:56.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:56.58#ibcon#enter wrdev, iclass 13, count 0 2006.201.12:51:56.58#ibcon#first serial, iclass 13, count 0 2006.201.12:51:56.58#ibcon#enter sib2, iclass 13, count 0 2006.201.12:51:56.58#ibcon#flushed, iclass 13, count 0 2006.201.12:51:56.58#ibcon#about to write, iclass 13, count 0 2006.201.12:51:56.58#ibcon#wrote, iclass 13, count 0 2006.201.12:51:56.58#ibcon#about to read 3, iclass 13, count 0 2006.201.12:51:56.60#ibcon#read 3, iclass 13, count 0 2006.201.12:51:56.60#ibcon#about to read 4, iclass 13, count 0 2006.201.12:51:56.60#ibcon#read 4, iclass 13, count 0 2006.201.12:51:56.60#ibcon#about to read 5, iclass 13, count 0 2006.201.12:51:56.60#ibcon#read 5, iclass 13, count 0 2006.201.12:51:56.60#ibcon#about to read 6, iclass 13, count 0 2006.201.12:51:56.60#ibcon#read 6, iclass 13, count 0 2006.201.12:51:56.60#ibcon#end of sib2, iclass 13, count 0 2006.201.12:51:56.60#ibcon#*mode == 0, iclass 13, count 0 2006.201.12:51:56.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.12:51:56.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.12:51:56.60#ibcon#*before write, iclass 13, count 0 2006.201.12:51:56.60#ibcon#enter sib2, iclass 13, count 0 2006.201.12:51:56.60#ibcon#flushed, iclass 13, count 0 2006.201.12:51:56.60#ibcon#about to write, iclass 13, count 0 2006.201.12:51:56.60#ibcon#wrote, iclass 13, count 0 2006.201.12:51:56.60#ibcon#about to read 3, iclass 13, count 0 2006.201.12:51:56.64#ibcon#read 3, iclass 13, count 0 2006.201.12:51:56.64#ibcon#about to read 4, iclass 13, count 0 2006.201.12:51:56.64#ibcon#read 4, iclass 13, count 0 2006.201.12:51:56.64#ibcon#about to read 5, iclass 13, count 0 2006.201.12:51:56.64#ibcon#read 5, iclass 13, count 0 2006.201.12:51:56.64#ibcon#about to read 6, iclass 13, count 0 2006.201.12:51:56.64#ibcon#read 6, iclass 13, count 0 2006.201.12:51:56.64#ibcon#end of sib2, iclass 13, count 0 2006.201.12:51:56.64#ibcon#*after write, iclass 13, count 0 2006.201.12:51:56.64#ibcon#*before return 0, iclass 13, count 0 2006.201.12:51:56.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:56.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.12:51:56.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.12:51:56.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.12:51:56.64$vck44/vb=4,5 2006.201.12:51:56.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.12:51:56.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.12:51:56.64#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:56.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:56.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:56.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:56.70#ibcon#enter wrdev, iclass 15, count 2 2006.201.12:51:56.70#ibcon#first serial, iclass 15, count 2 2006.201.12:51:56.70#ibcon#enter sib2, iclass 15, count 2 2006.201.12:51:56.70#ibcon#flushed, iclass 15, count 2 2006.201.12:51:56.70#ibcon#about to write, iclass 15, count 2 2006.201.12:51:56.70#ibcon#wrote, iclass 15, count 2 2006.201.12:51:56.70#ibcon#about to read 3, iclass 15, count 2 2006.201.12:51:56.72#ibcon#read 3, iclass 15, count 2 2006.201.12:51:56.72#ibcon#about to read 4, iclass 15, count 2 2006.201.12:51:56.72#ibcon#read 4, iclass 15, count 2 2006.201.12:51:56.72#ibcon#about to read 5, iclass 15, count 2 2006.201.12:51:56.72#ibcon#read 5, iclass 15, count 2 2006.201.12:51:56.72#ibcon#about to read 6, iclass 15, count 2 2006.201.12:51:56.72#ibcon#read 6, iclass 15, count 2 2006.201.12:51:56.72#ibcon#end of sib2, iclass 15, count 2 2006.201.12:51:56.72#ibcon#*mode == 0, iclass 15, count 2 2006.201.12:51:56.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.12:51:56.72#ibcon#[27=AT04-05\r\n] 2006.201.12:51:56.72#ibcon#*before write, iclass 15, count 2 2006.201.12:51:56.72#ibcon#enter sib2, iclass 15, count 2 2006.201.12:51:56.72#ibcon#flushed, iclass 15, count 2 2006.201.12:51:56.72#ibcon#about to write, iclass 15, count 2 2006.201.12:51:56.72#ibcon#wrote, iclass 15, count 2 2006.201.12:51:56.72#ibcon#about to read 3, iclass 15, count 2 2006.201.12:51:56.75#ibcon#read 3, iclass 15, count 2 2006.201.12:51:56.75#ibcon#about to read 4, iclass 15, count 2 2006.201.12:51:56.75#ibcon#read 4, iclass 15, count 2 2006.201.12:51:56.75#ibcon#about to read 5, iclass 15, count 2 2006.201.12:51:56.75#ibcon#read 5, iclass 15, count 2 2006.201.12:51:56.75#ibcon#about to read 6, iclass 15, count 2 2006.201.12:51:56.75#ibcon#read 6, iclass 15, count 2 2006.201.12:51:56.75#ibcon#end of sib2, iclass 15, count 2 2006.201.12:51:56.75#ibcon#*after write, iclass 15, count 2 2006.201.12:51:56.75#ibcon#*before return 0, iclass 15, count 2 2006.201.12:51:56.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:56.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.12:51:56.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.12:51:56.75#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:56.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:56.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:56.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:56.87#ibcon#enter wrdev, iclass 15, count 0 2006.201.12:51:56.87#ibcon#first serial, iclass 15, count 0 2006.201.12:51:56.87#ibcon#enter sib2, iclass 15, count 0 2006.201.12:51:56.87#ibcon#flushed, iclass 15, count 0 2006.201.12:51:56.87#ibcon#about to write, iclass 15, count 0 2006.201.12:51:56.87#ibcon#wrote, iclass 15, count 0 2006.201.12:51:56.87#ibcon#about to read 3, iclass 15, count 0 2006.201.12:51:56.89#ibcon#read 3, iclass 15, count 0 2006.201.12:51:56.89#ibcon#about to read 4, iclass 15, count 0 2006.201.12:51:56.89#ibcon#read 4, iclass 15, count 0 2006.201.12:51:56.89#ibcon#about to read 5, iclass 15, count 0 2006.201.12:51:56.89#ibcon#read 5, iclass 15, count 0 2006.201.12:51:56.89#ibcon#about to read 6, iclass 15, count 0 2006.201.12:51:56.89#ibcon#read 6, iclass 15, count 0 2006.201.12:51:56.89#ibcon#end of sib2, iclass 15, count 0 2006.201.12:51:56.89#ibcon#*mode == 0, iclass 15, count 0 2006.201.12:51:56.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.12:51:56.89#ibcon#[27=USB\r\n] 2006.201.12:51:56.89#ibcon#*before write, iclass 15, count 0 2006.201.12:51:56.89#ibcon#enter sib2, iclass 15, count 0 2006.201.12:51:56.89#ibcon#flushed, iclass 15, count 0 2006.201.12:51:56.89#ibcon#about to write, iclass 15, count 0 2006.201.12:51:56.89#ibcon#wrote, iclass 15, count 0 2006.201.12:51:56.89#ibcon#about to read 3, iclass 15, count 0 2006.201.12:51:56.92#ibcon#read 3, iclass 15, count 0 2006.201.12:51:56.92#ibcon#about to read 4, iclass 15, count 0 2006.201.12:51:56.92#ibcon#read 4, iclass 15, count 0 2006.201.12:51:56.92#ibcon#about to read 5, iclass 15, count 0 2006.201.12:51:56.92#ibcon#read 5, iclass 15, count 0 2006.201.12:51:56.92#ibcon#about to read 6, iclass 15, count 0 2006.201.12:51:56.92#ibcon#read 6, iclass 15, count 0 2006.201.12:51:56.92#ibcon#end of sib2, iclass 15, count 0 2006.201.12:51:56.92#ibcon#*after write, iclass 15, count 0 2006.201.12:51:56.92#ibcon#*before return 0, iclass 15, count 0 2006.201.12:51:56.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:56.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.12:51:56.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.12:51:56.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.12:51:56.92$vck44/vblo=5,709.99 2006.201.12:51:56.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.12:51:56.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.12:51:56.92#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:56.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:56.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:56.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:56.92#ibcon#enter wrdev, iclass 17, count 0 2006.201.12:51:56.92#ibcon#first serial, iclass 17, count 0 2006.201.12:51:56.92#ibcon#enter sib2, iclass 17, count 0 2006.201.12:51:56.92#ibcon#flushed, iclass 17, count 0 2006.201.12:51:56.92#ibcon#about to write, iclass 17, count 0 2006.201.12:51:56.92#ibcon#wrote, iclass 17, count 0 2006.201.12:51:56.92#ibcon#about to read 3, iclass 17, count 0 2006.201.12:51:56.94#ibcon#read 3, iclass 17, count 0 2006.201.12:51:56.94#ibcon#about to read 4, iclass 17, count 0 2006.201.12:51:56.94#ibcon#read 4, iclass 17, count 0 2006.201.12:51:56.94#ibcon#about to read 5, iclass 17, count 0 2006.201.12:51:56.94#ibcon#read 5, iclass 17, count 0 2006.201.12:51:56.94#ibcon#about to read 6, iclass 17, count 0 2006.201.12:51:56.94#ibcon#read 6, iclass 17, count 0 2006.201.12:51:56.94#ibcon#end of sib2, iclass 17, count 0 2006.201.12:51:56.94#ibcon#*mode == 0, iclass 17, count 0 2006.201.12:51:56.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.12:51:56.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.12:51:56.94#ibcon#*before write, iclass 17, count 0 2006.201.12:51:56.94#ibcon#enter sib2, iclass 17, count 0 2006.201.12:51:56.94#ibcon#flushed, iclass 17, count 0 2006.201.12:51:56.94#ibcon#about to write, iclass 17, count 0 2006.201.12:51:56.94#ibcon#wrote, iclass 17, count 0 2006.201.12:51:56.94#ibcon#about to read 3, iclass 17, count 0 2006.201.12:51:56.99#ibcon#read 3, iclass 17, count 0 2006.201.12:51:56.99#ibcon#about to read 4, iclass 17, count 0 2006.201.12:51:56.99#ibcon#read 4, iclass 17, count 0 2006.201.12:51:56.99#ibcon#about to read 5, iclass 17, count 0 2006.201.12:51:56.99#ibcon#read 5, iclass 17, count 0 2006.201.12:51:56.99#ibcon#about to read 6, iclass 17, count 0 2006.201.12:51:56.99#ibcon#read 6, iclass 17, count 0 2006.201.12:51:56.99#ibcon#end of sib2, iclass 17, count 0 2006.201.12:51:56.99#ibcon#*after write, iclass 17, count 0 2006.201.12:51:56.99#ibcon#*before return 0, iclass 17, count 0 2006.201.12:51:56.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:56.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.12:51:56.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.12:51:56.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.12:51:56.99$vck44/vb=5,4 2006.201.12:51:56.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.12:51:56.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.12:51:56.99#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:56.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:57.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:57.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:57.04#ibcon#enter wrdev, iclass 19, count 2 2006.201.12:51:57.04#ibcon#first serial, iclass 19, count 2 2006.201.12:51:57.04#ibcon#enter sib2, iclass 19, count 2 2006.201.12:51:57.04#ibcon#flushed, iclass 19, count 2 2006.201.12:51:57.04#ibcon#about to write, iclass 19, count 2 2006.201.12:51:57.04#ibcon#wrote, iclass 19, count 2 2006.201.12:51:57.04#ibcon#about to read 3, iclass 19, count 2 2006.201.12:51:57.06#ibcon#read 3, iclass 19, count 2 2006.201.12:51:57.06#ibcon#about to read 4, iclass 19, count 2 2006.201.12:51:57.06#ibcon#read 4, iclass 19, count 2 2006.201.12:51:57.06#ibcon#about to read 5, iclass 19, count 2 2006.201.12:51:57.06#ibcon#read 5, iclass 19, count 2 2006.201.12:51:57.06#ibcon#about to read 6, iclass 19, count 2 2006.201.12:51:57.06#ibcon#read 6, iclass 19, count 2 2006.201.12:51:57.06#ibcon#end of sib2, iclass 19, count 2 2006.201.12:51:57.06#ibcon#*mode == 0, iclass 19, count 2 2006.201.12:51:57.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.12:51:57.06#ibcon#[27=AT05-04\r\n] 2006.201.12:51:57.06#ibcon#*before write, iclass 19, count 2 2006.201.12:51:57.06#ibcon#enter sib2, iclass 19, count 2 2006.201.12:51:57.06#ibcon#flushed, iclass 19, count 2 2006.201.12:51:57.06#ibcon#about to write, iclass 19, count 2 2006.201.12:51:57.06#ibcon#wrote, iclass 19, count 2 2006.201.12:51:57.06#ibcon#about to read 3, iclass 19, count 2 2006.201.12:51:57.09#ibcon#read 3, iclass 19, count 2 2006.201.12:51:57.09#ibcon#about to read 4, iclass 19, count 2 2006.201.12:51:57.09#ibcon#read 4, iclass 19, count 2 2006.201.12:51:57.09#ibcon#about to read 5, iclass 19, count 2 2006.201.12:51:57.09#ibcon#read 5, iclass 19, count 2 2006.201.12:51:57.09#ibcon#about to read 6, iclass 19, count 2 2006.201.12:51:57.09#ibcon#read 6, iclass 19, count 2 2006.201.12:51:57.09#ibcon#end of sib2, iclass 19, count 2 2006.201.12:51:57.09#ibcon#*after write, iclass 19, count 2 2006.201.12:51:57.09#ibcon#*before return 0, iclass 19, count 2 2006.201.12:51:57.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:57.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.12:51:57.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.12:51:57.09#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:57.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:57.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:57.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:57.21#ibcon#enter wrdev, iclass 19, count 0 2006.201.12:51:57.21#ibcon#first serial, iclass 19, count 0 2006.201.12:51:57.21#ibcon#enter sib2, iclass 19, count 0 2006.201.12:51:57.21#ibcon#flushed, iclass 19, count 0 2006.201.12:51:57.21#ibcon#about to write, iclass 19, count 0 2006.201.12:51:57.21#ibcon#wrote, iclass 19, count 0 2006.201.12:51:57.21#ibcon#about to read 3, iclass 19, count 0 2006.201.12:51:57.23#ibcon#read 3, iclass 19, count 0 2006.201.12:51:57.23#ibcon#about to read 4, iclass 19, count 0 2006.201.12:51:57.23#ibcon#read 4, iclass 19, count 0 2006.201.12:51:57.23#ibcon#about to read 5, iclass 19, count 0 2006.201.12:51:57.23#ibcon#read 5, iclass 19, count 0 2006.201.12:51:57.23#ibcon#about to read 6, iclass 19, count 0 2006.201.12:51:57.23#ibcon#read 6, iclass 19, count 0 2006.201.12:51:57.23#ibcon#end of sib2, iclass 19, count 0 2006.201.12:51:57.23#ibcon#*mode == 0, iclass 19, count 0 2006.201.12:51:57.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.12:51:57.23#ibcon#[27=USB\r\n] 2006.201.12:51:57.23#ibcon#*before write, iclass 19, count 0 2006.201.12:51:57.23#ibcon#enter sib2, iclass 19, count 0 2006.201.12:51:57.23#ibcon#flushed, iclass 19, count 0 2006.201.12:51:57.23#ibcon#about to write, iclass 19, count 0 2006.201.12:51:57.23#ibcon#wrote, iclass 19, count 0 2006.201.12:51:57.23#ibcon#about to read 3, iclass 19, count 0 2006.201.12:51:57.26#ibcon#read 3, iclass 19, count 0 2006.201.12:51:57.26#ibcon#about to read 4, iclass 19, count 0 2006.201.12:51:57.26#ibcon#read 4, iclass 19, count 0 2006.201.12:51:57.26#ibcon#about to read 5, iclass 19, count 0 2006.201.12:51:57.26#ibcon#read 5, iclass 19, count 0 2006.201.12:51:57.26#ibcon#about to read 6, iclass 19, count 0 2006.201.12:51:57.26#ibcon#read 6, iclass 19, count 0 2006.201.12:51:57.26#ibcon#end of sib2, iclass 19, count 0 2006.201.12:51:57.26#ibcon#*after write, iclass 19, count 0 2006.201.12:51:57.26#ibcon#*before return 0, iclass 19, count 0 2006.201.12:51:57.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:57.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.12:51:57.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.12:51:57.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.12:51:57.26$vck44/vblo=6,719.99 2006.201.12:51:57.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.12:51:57.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.12:51:57.26#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:57.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:57.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:57.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:57.26#ibcon#enter wrdev, iclass 21, count 0 2006.201.12:51:57.26#ibcon#first serial, iclass 21, count 0 2006.201.12:51:57.26#ibcon#enter sib2, iclass 21, count 0 2006.201.12:51:57.26#ibcon#flushed, iclass 21, count 0 2006.201.12:51:57.26#ibcon#about to write, iclass 21, count 0 2006.201.12:51:57.26#ibcon#wrote, iclass 21, count 0 2006.201.12:51:57.26#ibcon#about to read 3, iclass 21, count 0 2006.201.12:51:57.28#ibcon#read 3, iclass 21, count 0 2006.201.12:51:57.28#ibcon#about to read 4, iclass 21, count 0 2006.201.12:51:57.28#ibcon#read 4, iclass 21, count 0 2006.201.12:51:57.28#ibcon#about to read 5, iclass 21, count 0 2006.201.12:51:57.28#ibcon#read 5, iclass 21, count 0 2006.201.12:51:57.28#ibcon#about to read 6, iclass 21, count 0 2006.201.12:51:57.28#ibcon#read 6, iclass 21, count 0 2006.201.12:51:57.28#ibcon#end of sib2, iclass 21, count 0 2006.201.12:51:57.28#ibcon#*mode == 0, iclass 21, count 0 2006.201.12:51:57.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.12:51:57.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.12:51:57.28#ibcon#*before write, iclass 21, count 0 2006.201.12:51:57.28#ibcon#enter sib2, iclass 21, count 0 2006.201.12:51:57.28#ibcon#flushed, iclass 21, count 0 2006.201.12:51:57.28#ibcon#about to write, iclass 21, count 0 2006.201.12:51:57.28#ibcon#wrote, iclass 21, count 0 2006.201.12:51:57.28#ibcon#about to read 3, iclass 21, count 0 2006.201.12:51:57.32#ibcon#read 3, iclass 21, count 0 2006.201.12:51:57.32#ibcon#about to read 4, iclass 21, count 0 2006.201.12:51:57.32#ibcon#read 4, iclass 21, count 0 2006.201.12:51:57.32#ibcon#about to read 5, iclass 21, count 0 2006.201.12:51:57.32#ibcon#read 5, iclass 21, count 0 2006.201.12:51:57.32#ibcon#about to read 6, iclass 21, count 0 2006.201.12:51:57.32#ibcon#read 6, iclass 21, count 0 2006.201.12:51:57.32#ibcon#end of sib2, iclass 21, count 0 2006.201.12:51:57.32#ibcon#*after write, iclass 21, count 0 2006.201.12:51:57.32#ibcon#*before return 0, iclass 21, count 0 2006.201.12:51:57.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:57.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.12:51:57.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.12:51:57.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.12:51:57.32$vck44/vb=6,4 2006.201.12:51:57.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.12:51:57.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.12:51:57.32#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:57.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:57.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:57.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:57.38#ibcon#enter wrdev, iclass 23, count 2 2006.201.12:51:57.38#ibcon#first serial, iclass 23, count 2 2006.201.12:51:57.38#ibcon#enter sib2, iclass 23, count 2 2006.201.12:51:57.38#ibcon#flushed, iclass 23, count 2 2006.201.12:51:57.38#ibcon#about to write, iclass 23, count 2 2006.201.12:51:57.38#ibcon#wrote, iclass 23, count 2 2006.201.12:51:57.38#ibcon#about to read 3, iclass 23, count 2 2006.201.12:51:57.40#ibcon#read 3, iclass 23, count 2 2006.201.12:51:57.40#ibcon#about to read 4, iclass 23, count 2 2006.201.12:51:57.40#ibcon#read 4, iclass 23, count 2 2006.201.12:51:57.40#ibcon#about to read 5, iclass 23, count 2 2006.201.12:51:57.40#ibcon#read 5, iclass 23, count 2 2006.201.12:51:57.40#ibcon#about to read 6, iclass 23, count 2 2006.201.12:51:57.40#ibcon#read 6, iclass 23, count 2 2006.201.12:51:57.40#ibcon#end of sib2, iclass 23, count 2 2006.201.12:51:57.40#ibcon#*mode == 0, iclass 23, count 2 2006.201.12:51:57.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.12:51:57.40#ibcon#[27=AT06-04\r\n] 2006.201.12:51:57.40#ibcon#*before write, iclass 23, count 2 2006.201.12:51:57.40#ibcon#enter sib2, iclass 23, count 2 2006.201.12:51:57.40#ibcon#flushed, iclass 23, count 2 2006.201.12:51:57.40#ibcon#about to write, iclass 23, count 2 2006.201.12:51:57.40#ibcon#wrote, iclass 23, count 2 2006.201.12:51:57.40#ibcon#about to read 3, iclass 23, count 2 2006.201.12:51:57.43#ibcon#read 3, iclass 23, count 2 2006.201.12:51:57.43#ibcon#about to read 4, iclass 23, count 2 2006.201.12:51:57.43#ibcon#read 4, iclass 23, count 2 2006.201.12:51:57.43#ibcon#about to read 5, iclass 23, count 2 2006.201.12:51:57.43#ibcon#read 5, iclass 23, count 2 2006.201.12:51:57.43#ibcon#about to read 6, iclass 23, count 2 2006.201.12:51:57.43#ibcon#read 6, iclass 23, count 2 2006.201.12:51:57.43#ibcon#end of sib2, iclass 23, count 2 2006.201.12:51:57.43#ibcon#*after write, iclass 23, count 2 2006.201.12:51:57.43#ibcon#*before return 0, iclass 23, count 2 2006.201.12:51:57.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:57.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.12:51:57.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.12:51:57.43#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:57.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:57.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:57.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:57.55#ibcon#enter wrdev, iclass 23, count 0 2006.201.12:51:57.55#ibcon#first serial, iclass 23, count 0 2006.201.12:51:57.55#ibcon#enter sib2, iclass 23, count 0 2006.201.12:51:57.55#ibcon#flushed, iclass 23, count 0 2006.201.12:51:57.55#ibcon#about to write, iclass 23, count 0 2006.201.12:51:57.55#ibcon#wrote, iclass 23, count 0 2006.201.12:51:57.55#ibcon#about to read 3, iclass 23, count 0 2006.201.12:51:57.57#ibcon#read 3, iclass 23, count 0 2006.201.12:51:57.57#ibcon#about to read 4, iclass 23, count 0 2006.201.12:51:57.57#ibcon#read 4, iclass 23, count 0 2006.201.12:51:57.57#ibcon#about to read 5, iclass 23, count 0 2006.201.12:51:57.57#ibcon#read 5, iclass 23, count 0 2006.201.12:51:57.57#ibcon#about to read 6, iclass 23, count 0 2006.201.12:51:57.57#ibcon#read 6, iclass 23, count 0 2006.201.12:51:57.57#ibcon#end of sib2, iclass 23, count 0 2006.201.12:51:57.57#ibcon#*mode == 0, iclass 23, count 0 2006.201.12:51:57.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.12:51:57.57#ibcon#[27=USB\r\n] 2006.201.12:51:57.57#ibcon#*before write, iclass 23, count 0 2006.201.12:51:57.57#ibcon#enter sib2, iclass 23, count 0 2006.201.12:51:57.57#ibcon#flushed, iclass 23, count 0 2006.201.12:51:57.57#ibcon#about to write, iclass 23, count 0 2006.201.12:51:57.57#ibcon#wrote, iclass 23, count 0 2006.201.12:51:57.57#ibcon#about to read 3, iclass 23, count 0 2006.201.12:51:57.60#ibcon#read 3, iclass 23, count 0 2006.201.12:51:57.60#ibcon#about to read 4, iclass 23, count 0 2006.201.12:51:57.60#ibcon#read 4, iclass 23, count 0 2006.201.12:51:57.60#ibcon#about to read 5, iclass 23, count 0 2006.201.12:51:57.60#ibcon#read 5, iclass 23, count 0 2006.201.12:51:57.60#ibcon#about to read 6, iclass 23, count 0 2006.201.12:51:57.60#ibcon#read 6, iclass 23, count 0 2006.201.12:51:57.60#ibcon#end of sib2, iclass 23, count 0 2006.201.12:51:57.60#ibcon#*after write, iclass 23, count 0 2006.201.12:51:57.60#ibcon#*before return 0, iclass 23, count 0 2006.201.12:51:57.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:57.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.12:51:57.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.12:51:57.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.12:51:57.60$vck44/vblo=7,734.99 2006.201.12:51:57.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.12:51:57.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.12:51:57.60#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:57.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:57.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:57.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:57.60#ibcon#enter wrdev, iclass 25, count 0 2006.201.12:51:57.60#ibcon#first serial, iclass 25, count 0 2006.201.12:51:57.60#ibcon#enter sib2, iclass 25, count 0 2006.201.12:51:57.60#ibcon#flushed, iclass 25, count 0 2006.201.12:51:57.60#ibcon#about to write, iclass 25, count 0 2006.201.12:51:57.60#ibcon#wrote, iclass 25, count 0 2006.201.12:51:57.60#ibcon#about to read 3, iclass 25, count 0 2006.201.12:51:57.62#ibcon#read 3, iclass 25, count 0 2006.201.12:51:57.62#ibcon#about to read 4, iclass 25, count 0 2006.201.12:51:57.62#ibcon#read 4, iclass 25, count 0 2006.201.12:51:57.62#ibcon#about to read 5, iclass 25, count 0 2006.201.12:51:57.62#ibcon#read 5, iclass 25, count 0 2006.201.12:51:57.62#ibcon#about to read 6, iclass 25, count 0 2006.201.12:51:57.62#ibcon#read 6, iclass 25, count 0 2006.201.12:51:57.62#ibcon#end of sib2, iclass 25, count 0 2006.201.12:51:57.62#ibcon#*mode == 0, iclass 25, count 0 2006.201.12:51:57.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.12:51:57.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.12:51:57.62#ibcon#*before write, iclass 25, count 0 2006.201.12:51:57.62#ibcon#enter sib2, iclass 25, count 0 2006.201.12:51:57.62#ibcon#flushed, iclass 25, count 0 2006.201.12:51:57.62#ibcon#about to write, iclass 25, count 0 2006.201.12:51:57.62#ibcon#wrote, iclass 25, count 0 2006.201.12:51:57.62#ibcon#about to read 3, iclass 25, count 0 2006.201.12:51:57.67#ibcon#read 3, iclass 25, count 0 2006.201.12:51:57.67#ibcon#about to read 4, iclass 25, count 0 2006.201.12:51:57.67#ibcon#read 4, iclass 25, count 0 2006.201.12:51:57.67#ibcon#about to read 5, iclass 25, count 0 2006.201.12:51:57.67#ibcon#read 5, iclass 25, count 0 2006.201.12:51:57.67#ibcon#about to read 6, iclass 25, count 0 2006.201.12:51:57.67#ibcon#read 6, iclass 25, count 0 2006.201.12:51:57.67#ibcon#end of sib2, iclass 25, count 0 2006.201.12:51:57.67#ibcon#*after write, iclass 25, count 0 2006.201.12:51:57.67#ibcon#*before return 0, iclass 25, count 0 2006.201.12:51:57.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:57.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.12:51:57.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.12:51:57.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.12:51:57.67$vck44/vb=7,4 2006.201.12:51:57.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.12:51:57.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.12:51:57.67#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:57.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:57.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:57.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:57.72#ibcon#enter wrdev, iclass 27, count 2 2006.201.12:51:57.72#ibcon#first serial, iclass 27, count 2 2006.201.12:51:57.72#ibcon#enter sib2, iclass 27, count 2 2006.201.12:51:57.72#ibcon#flushed, iclass 27, count 2 2006.201.12:51:57.72#ibcon#about to write, iclass 27, count 2 2006.201.12:51:57.72#ibcon#wrote, iclass 27, count 2 2006.201.12:51:57.72#ibcon#about to read 3, iclass 27, count 2 2006.201.12:51:57.74#ibcon#read 3, iclass 27, count 2 2006.201.12:51:57.74#ibcon#about to read 4, iclass 27, count 2 2006.201.12:51:57.74#ibcon#read 4, iclass 27, count 2 2006.201.12:51:57.74#ibcon#about to read 5, iclass 27, count 2 2006.201.12:51:57.74#ibcon#read 5, iclass 27, count 2 2006.201.12:51:57.74#ibcon#about to read 6, iclass 27, count 2 2006.201.12:51:57.74#ibcon#read 6, iclass 27, count 2 2006.201.12:51:57.74#ibcon#end of sib2, iclass 27, count 2 2006.201.12:51:57.74#ibcon#*mode == 0, iclass 27, count 2 2006.201.12:51:57.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.12:51:57.74#ibcon#[27=AT07-04\r\n] 2006.201.12:51:57.74#ibcon#*before write, iclass 27, count 2 2006.201.12:51:57.74#ibcon#enter sib2, iclass 27, count 2 2006.201.12:51:57.74#ibcon#flushed, iclass 27, count 2 2006.201.12:51:57.74#ibcon#about to write, iclass 27, count 2 2006.201.12:51:57.74#ibcon#wrote, iclass 27, count 2 2006.201.12:51:57.74#ibcon#about to read 3, iclass 27, count 2 2006.201.12:51:57.77#ibcon#read 3, iclass 27, count 2 2006.201.12:51:57.77#ibcon#about to read 4, iclass 27, count 2 2006.201.12:51:57.77#ibcon#read 4, iclass 27, count 2 2006.201.12:51:57.77#ibcon#about to read 5, iclass 27, count 2 2006.201.12:51:57.77#ibcon#read 5, iclass 27, count 2 2006.201.12:51:57.77#ibcon#about to read 6, iclass 27, count 2 2006.201.12:51:57.77#ibcon#read 6, iclass 27, count 2 2006.201.12:51:57.77#ibcon#end of sib2, iclass 27, count 2 2006.201.12:51:57.77#ibcon#*after write, iclass 27, count 2 2006.201.12:51:57.77#ibcon#*before return 0, iclass 27, count 2 2006.201.12:51:57.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:57.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.12:51:57.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.12:51:57.77#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:57.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:57.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:57.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:57.89#ibcon#enter wrdev, iclass 27, count 0 2006.201.12:51:57.89#ibcon#first serial, iclass 27, count 0 2006.201.12:51:57.89#ibcon#enter sib2, iclass 27, count 0 2006.201.12:51:57.89#ibcon#flushed, iclass 27, count 0 2006.201.12:51:57.89#ibcon#about to write, iclass 27, count 0 2006.201.12:51:57.89#ibcon#wrote, iclass 27, count 0 2006.201.12:51:57.89#ibcon#about to read 3, iclass 27, count 0 2006.201.12:51:57.91#ibcon#read 3, iclass 27, count 0 2006.201.12:51:57.91#ibcon#about to read 4, iclass 27, count 0 2006.201.12:51:57.91#ibcon#read 4, iclass 27, count 0 2006.201.12:51:57.91#ibcon#about to read 5, iclass 27, count 0 2006.201.12:51:57.91#ibcon#read 5, iclass 27, count 0 2006.201.12:51:57.91#ibcon#about to read 6, iclass 27, count 0 2006.201.12:51:57.91#ibcon#read 6, iclass 27, count 0 2006.201.12:51:57.91#ibcon#end of sib2, iclass 27, count 0 2006.201.12:51:57.91#ibcon#*mode == 0, iclass 27, count 0 2006.201.12:51:57.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.12:51:57.91#ibcon#[27=USB\r\n] 2006.201.12:51:57.91#ibcon#*before write, iclass 27, count 0 2006.201.12:51:57.91#ibcon#enter sib2, iclass 27, count 0 2006.201.12:51:57.91#ibcon#flushed, iclass 27, count 0 2006.201.12:51:57.91#ibcon#about to write, iclass 27, count 0 2006.201.12:51:57.91#ibcon#wrote, iclass 27, count 0 2006.201.12:51:57.91#ibcon#about to read 3, iclass 27, count 0 2006.201.12:51:57.94#ibcon#read 3, iclass 27, count 0 2006.201.12:51:57.94#ibcon#about to read 4, iclass 27, count 0 2006.201.12:51:57.94#ibcon#read 4, iclass 27, count 0 2006.201.12:51:57.94#ibcon#about to read 5, iclass 27, count 0 2006.201.12:51:57.94#ibcon#read 5, iclass 27, count 0 2006.201.12:51:57.94#ibcon#about to read 6, iclass 27, count 0 2006.201.12:51:57.94#ibcon#read 6, iclass 27, count 0 2006.201.12:51:57.94#ibcon#end of sib2, iclass 27, count 0 2006.201.12:51:57.94#ibcon#*after write, iclass 27, count 0 2006.201.12:51:57.94#ibcon#*before return 0, iclass 27, count 0 2006.201.12:51:57.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:57.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.12:51:57.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.12:51:57.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.12:51:57.94$vck44/vblo=8,744.99 2006.201.12:51:57.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.12:51:57.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.12:51:57.94#ibcon#ireg 17 cls_cnt 0 2006.201.12:51:57.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:57.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:57.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:57.94#ibcon#enter wrdev, iclass 29, count 0 2006.201.12:51:57.94#ibcon#first serial, iclass 29, count 0 2006.201.12:51:57.94#ibcon#enter sib2, iclass 29, count 0 2006.201.12:51:57.94#ibcon#flushed, iclass 29, count 0 2006.201.12:51:57.94#ibcon#about to write, iclass 29, count 0 2006.201.12:51:57.94#ibcon#wrote, iclass 29, count 0 2006.201.12:51:57.94#ibcon#about to read 3, iclass 29, count 0 2006.201.12:51:57.96#ibcon#read 3, iclass 29, count 0 2006.201.12:51:57.96#ibcon#about to read 4, iclass 29, count 0 2006.201.12:51:57.96#ibcon#read 4, iclass 29, count 0 2006.201.12:51:57.96#ibcon#about to read 5, iclass 29, count 0 2006.201.12:51:57.96#ibcon#read 5, iclass 29, count 0 2006.201.12:51:57.96#ibcon#about to read 6, iclass 29, count 0 2006.201.12:51:57.96#ibcon#read 6, iclass 29, count 0 2006.201.12:51:57.96#ibcon#end of sib2, iclass 29, count 0 2006.201.12:51:57.96#ibcon#*mode == 0, iclass 29, count 0 2006.201.12:51:57.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.12:51:57.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.12:51:57.96#ibcon#*before write, iclass 29, count 0 2006.201.12:51:57.96#ibcon#enter sib2, iclass 29, count 0 2006.201.12:51:57.96#ibcon#flushed, iclass 29, count 0 2006.201.12:51:57.96#ibcon#about to write, iclass 29, count 0 2006.201.12:51:57.96#ibcon#wrote, iclass 29, count 0 2006.201.12:51:57.96#ibcon#about to read 3, iclass 29, count 0 2006.201.12:51:58.00#ibcon#read 3, iclass 29, count 0 2006.201.12:51:58.00#ibcon#about to read 4, iclass 29, count 0 2006.201.12:51:58.00#ibcon#read 4, iclass 29, count 0 2006.201.12:51:58.00#ibcon#about to read 5, iclass 29, count 0 2006.201.12:51:58.00#ibcon#read 5, iclass 29, count 0 2006.201.12:51:58.00#ibcon#about to read 6, iclass 29, count 0 2006.201.12:51:58.00#ibcon#read 6, iclass 29, count 0 2006.201.12:51:58.00#ibcon#end of sib2, iclass 29, count 0 2006.201.12:51:58.00#ibcon#*after write, iclass 29, count 0 2006.201.12:51:58.00#ibcon#*before return 0, iclass 29, count 0 2006.201.12:51:58.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:58.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.12:51:58.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.12:51:58.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.12:51:58.00$vck44/vb=8,4 2006.201.12:51:58.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.12:51:58.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.12:51:58.00#ibcon#ireg 11 cls_cnt 2 2006.201.12:51:58.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:58.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:58.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:58.06#ibcon#enter wrdev, iclass 31, count 2 2006.201.12:51:58.06#ibcon#first serial, iclass 31, count 2 2006.201.12:51:58.06#ibcon#enter sib2, iclass 31, count 2 2006.201.12:51:58.06#ibcon#flushed, iclass 31, count 2 2006.201.12:51:58.06#ibcon#about to write, iclass 31, count 2 2006.201.12:51:58.06#ibcon#wrote, iclass 31, count 2 2006.201.12:51:58.06#ibcon#about to read 3, iclass 31, count 2 2006.201.12:51:58.08#ibcon#read 3, iclass 31, count 2 2006.201.12:51:58.08#ibcon#about to read 4, iclass 31, count 2 2006.201.12:51:58.08#ibcon#read 4, iclass 31, count 2 2006.201.12:51:58.08#ibcon#about to read 5, iclass 31, count 2 2006.201.12:51:58.08#ibcon#read 5, iclass 31, count 2 2006.201.12:51:58.08#ibcon#about to read 6, iclass 31, count 2 2006.201.12:51:58.08#ibcon#read 6, iclass 31, count 2 2006.201.12:51:58.08#ibcon#end of sib2, iclass 31, count 2 2006.201.12:51:58.08#ibcon#*mode == 0, iclass 31, count 2 2006.201.12:51:58.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.12:51:58.08#ibcon#[27=AT08-04\r\n] 2006.201.12:51:58.08#ibcon#*before write, iclass 31, count 2 2006.201.12:51:58.08#ibcon#enter sib2, iclass 31, count 2 2006.201.12:51:58.08#ibcon#flushed, iclass 31, count 2 2006.201.12:51:58.08#ibcon#about to write, iclass 31, count 2 2006.201.12:51:58.08#ibcon#wrote, iclass 31, count 2 2006.201.12:51:58.08#ibcon#about to read 3, iclass 31, count 2 2006.201.12:51:58.11#ibcon#read 3, iclass 31, count 2 2006.201.12:51:58.11#ibcon#about to read 4, iclass 31, count 2 2006.201.12:51:58.11#ibcon#read 4, iclass 31, count 2 2006.201.12:51:58.11#ibcon#about to read 5, iclass 31, count 2 2006.201.12:51:58.11#ibcon#read 5, iclass 31, count 2 2006.201.12:51:58.11#ibcon#about to read 6, iclass 31, count 2 2006.201.12:51:58.11#ibcon#read 6, iclass 31, count 2 2006.201.12:51:58.11#ibcon#end of sib2, iclass 31, count 2 2006.201.12:51:58.11#ibcon#*after write, iclass 31, count 2 2006.201.12:51:58.11#ibcon#*before return 0, iclass 31, count 2 2006.201.12:51:58.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:58.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.12:51:58.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.12:51:58.11#ibcon#ireg 7 cls_cnt 0 2006.201.12:51:58.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:58.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:58.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:58.23#ibcon#enter wrdev, iclass 31, count 0 2006.201.12:51:58.23#ibcon#first serial, iclass 31, count 0 2006.201.12:51:58.23#ibcon#enter sib2, iclass 31, count 0 2006.201.12:51:58.23#ibcon#flushed, iclass 31, count 0 2006.201.12:51:58.23#ibcon#about to write, iclass 31, count 0 2006.201.12:51:58.23#ibcon#wrote, iclass 31, count 0 2006.201.12:51:58.23#ibcon#about to read 3, iclass 31, count 0 2006.201.12:51:58.25#ibcon#read 3, iclass 31, count 0 2006.201.12:51:58.25#ibcon#about to read 4, iclass 31, count 0 2006.201.12:51:58.25#ibcon#read 4, iclass 31, count 0 2006.201.12:51:58.25#ibcon#about to read 5, iclass 31, count 0 2006.201.12:51:58.25#ibcon#read 5, iclass 31, count 0 2006.201.12:51:58.25#ibcon#about to read 6, iclass 31, count 0 2006.201.12:51:58.25#ibcon#read 6, iclass 31, count 0 2006.201.12:51:58.25#ibcon#end of sib2, iclass 31, count 0 2006.201.12:51:58.25#ibcon#*mode == 0, iclass 31, count 0 2006.201.12:51:58.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.12:51:58.25#ibcon#[27=USB\r\n] 2006.201.12:51:58.25#ibcon#*before write, iclass 31, count 0 2006.201.12:51:58.25#ibcon#enter sib2, iclass 31, count 0 2006.201.12:51:58.25#ibcon#flushed, iclass 31, count 0 2006.201.12:51:58.25#ibcon#about to write, iclass 31, count 0 2006.201.12:51:58.25#ibcon#wrote, iclass 31, count 0 2006.201.12:51:58.25#ibcon#about to read 3, iclass 31, count 0 2006.201.12:51:58.28#ibcon#read 3, iclass 31, count 0 2006.201.12:51:58.28#ibcon#about to read 4, iclass 31, count 0 2006.201.12:51:58.28#ibcon#read 4, iclass 31, count 0 2006.201.12:51:58.28#ibcon#about to read 5, iclass 31, count 0 2006.201.12:51:58.28#ibcon#read 5, iclass 31, count 0 2006.201.12:51:58.28#ibcon#about to read 6, iclass 31, count 0 2006.201.12:51:58.28#ibcon#read 6, iclass 31, count 0 2006.201.12:51:58.28#ibcon#end of sib2, iclass 31, count 0 2006.201.12:51:58.28#ibcon#*after write, iclass 31, count 0 2006.201.12:51:58.28#ibcon#*before return 0, iclass 31, count 0 2006.201.12:51:58.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:58.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.12:51:58.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.12:51:58.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.12:51:58.28$vck44/vabw=wide 2006.201.12:51:58.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.12:51:58.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.12:51:58.28#ibcon#ireg 8 cls_cnt 0 2006.201.12:51:58.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:58.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:58.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:58.28#ibcon#enter wrdev, iclass 33, count 0 2006.201.12:51:58.28#ibcon#first serial, iclass 33, count 0 2006.201.12:51:58.28#ibcon#enter sib2, iclass 33, count 0 2006.201.12:51:58.28#ibcon#flushed, iclass 33, count 0 2006.201.12:51:58.28#ibcon#about to write, iclass 33, count 0 2006.201.12:51:58.28#ibcon#wrote, iclass 33, count 0 2006.201.12:51:58.28#ibcon#about to read 3, iclass 33, count 0 2006.201.12:51:58.30#ibcon#read 3, iclass 33, count 0 2006.201.12:51:58.30#ibcon#about to read 4, iclass 33, count 0 2006.201.12:51:58.30#ibcon#read 4, iclass 33, count 0 2006.201.12:51:58.30#ibcon#about to read 5, iclass 33, count 0 2006.201.12:51:58.30#ibcon#read 5, iclass 33, count 0 2006.201.12:51:58.30#ibcon#about to read 6, iclass 33, count 0 2006.201.12:51:58.30#ibcon#read 6, iclass 33, count 0 2006.201.12:51:58.30#ibcon#end of sib2, iclass 33, count 0 2006.201.12:51:58.30#ibcon#*mode == 0, iclass 33, count 0 2006.201.12:51:58.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.12:51:58.30#ibcon#[25=BW32\r\n] 2006.201.12:51:58.30#ibcon#*before write, iclass 33, count 0 2006.201.12:51:58.30#ibcon#enter sib2, iclass 33, count 0 2006.201.12:51:58.30#ibcon#flushed, iclass 33, count 0 2006.201.12:51:58.30#ibcon#about to write, iclass 33, count 0 2006.201.12:51:58.30#ibcon#wrote, iclass 33, count 0 2006.201.12:51:58.30#ibcon#about to read 3, iclass 33, count 0 2006.201.12:51:58.33#ibcon#read 3, iclass 33, count 0 2006.201.12:51:58.33#ibcon#about to read 4, iclass 33, count 0 2006.201.12:51:58.33#ibcon#read 4, iclass 33, count 0 2006.201.12:51:58.33#ibcon#about to read 5, iclass 33, count 0 2006.201.12:51:58.33#ibcon#read 5, iclass 33, count 0 2006.201.12:51:58.33#ibcon#about to read 6, iclass 33, count 0 2006.201.12:51:58.33#ibcon#read 6, iclass 33, count 0 2006.201.12:51:58.33#ibcon#end of sib2, iclass 33, count 0 2006.201.12:51:58.33#ibcon#*after write, iclass 33, count 0 2006.201.12:51:58.33#ibcon#*before return 0, iclass 33, count 0 2006.201.12:51:58.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:58.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.12:51:58.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.12:51:58.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.12:51:58.33$vck44/vbbw=wide 2006.201.12:51:58.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.12:51:58.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.12:51:58.33#ibcon#ireg 8 cls_cnt 0 2006.201.12:51:58.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:51:58.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:51:58.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:51:58.40#ibcon#enter wrdev, iclass 35, count 0 2006.201.12:51:58.40#ibcon#first serial, iclass 35, count 0 2006.201.12:51:58.40#ibcon#enter sib2, iclass 35, count 0 2006.201.12:51:58.40#ibcon#flushed, iclass 35, count 0 2006.201.12:51:58.40#ibcon#about to write, iclass 35, count 0 2006.201.12:51:58.40#ibcon#wrote, iclass 35, count 0 2006.201.12:51:58.40#ibcon#about to read 3, iclass 35, count 0 2006.201.12:51:58.42#ibcon#read 3, iclass 35, count 0 2006.201.12:51:58.42#ibcon#about to read 4, iclass 35, count 0 2006.201.12:51:58.42#ibcon#read 4, iclass 35, count 0 2006.201.12:51:58.42#ibcon#about to read 5, iclass 35, count 0 2006.201.12:51:58.42#ibcon#read 5, iclass 35, count 0 2006.201.12:51:58.42#ibcon#about to read 6, iclass 35, count 0 2006.201.12:51:58.42#ibcon#read 6, iclass 35, count 0 2006.201.12:51:58.42#ibcon#end of sib2, iclass 35, count 0 2006.201.12:51:58.42#ibcon#*mode == 0, iclass 35, count 0 2006.201.12:51:58.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.12:51:58.42#ibcon#[27=BW32\r\n] 2006.201.12:51:58.42#ibcon#*before write, iclass 35, count 0 2006.201.12:51:58.42#ibcon#enter sib2, iclass 35, count 0 2006.201.12:51:58.42#ibcon#flushed, iclass 35, count 0 2006.201.12:51:58.42#ibcon#about to write, iclass 35, count 0 2006.201.12:51:58.42#ibcon#wrote, iclass 35, count 0 2006.201.12:51:58.42#ibcon#about to read 3, iclass 35, count 0 2006.201.12:51:58.45#ibcon#read 3, iclass 35, count 0 2006.201.12:51:58.45#ibcon#about to read 4, iclass 35, count 0 2006.201.12:51:58.45#ibcon#read 4, iclass 35, count 0 2006.201.12:51:58.45#ibcon#about to read 5, iclass 35, count 0 2006.201.12:51:58.45#ibcon#read 5, iclass 35, count 0 2006.201.12:51:58.45#ibcon#about to read 6, iclass 35, count 0 2006.201.12:51:58.45#ibcon#read 6, iclass 35, count 0 2006.201.12:51:58.45#ibcon#end of sib2, iclass 35, count 0 2006.201.12:51:58.45#ibcon#*after write, iclass 35, count 0 2006.201.12:51:58.45#ibcon#*before return 0, iclass 35, count 0 2006.201.12:51:58.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:51:58.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.12:51:58.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.12:51:58.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.12:51:58.45$setupk4/ifdk4 2006.201.12:51:58.45$ifdk4/lo= 2006.201.12:51:58.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.12:51:58.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.12:51:58.45$ifdk4/patch= 2006.201.12:51:58.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.12:51:58.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.12:51:58.45$setupk4/!*+20s 2006.201.12:51:59.65#abcon#<5=/03 1.7 3.5 21.021001004.0\r\n> 2006.201.12:51:59.67#abcon#{5=INTERFACE CLEAR} 2006.201.12:51:59.73#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:52:09.82#abcon#<5=/03 1.7 3.5 21.021001004.0\r\n> 2006.201.12:52:09.84#abcon#{5=INTERFACE CLEAR} 2006.201.12:52:09.90#abcon#[5=S1D000X0/0*\r\n] 2006.201.12:52:12.93$setupk4/"tpicd 2006.201.12:52:12.93$setupk4/echo=off 2006.201.12:52:12.93$setupk4/xlog=off 2006.201.12:52:12.93:!2006.201.12:57:32 2006.201.12:52:29.14#trakl#Source acquired 2006.201.12:52:30.14#flagr#flagr/antenna,acquired 2006.201.12:57:32.00:preob 2006.201.12:57:32.13/onsource/TRACKING 2006.201.12:57:32.13:!2006.201.12:57:42 2006.201.12:57:42.00:"tape 2006.201.12:57:42.00:"st=record 2006.201.12:57:42.00:data_valid=on 2006.201.12:57:42.00:midob 2006.201.12:57:42.13/onsource/TRACKING 2006.201.12:57:42.13/wx/21.02,1004.1,100 2006.201.12:57:42.32/cable/+6.4738E-03 2006.201.12:57:43.41/va/01,08,usb,yes,29,32 2006.201.12:57:43.41/va/02,07,usb,yes,32,33 2006.201.12:57:43.41/va/03,08,usb,yes,29,30 2006.201.12:57:43.41/va/04,07,usb,yes,33,34 2006.201.12:57:43.41/va/05,04,usb,yes,29,29 2006.201.12:57:43.41/va/06,05,usb,yes,29,29 2006.201.12:57:43.41/va/07,05,usb,yes,28,29 2006.201.12:57:43.41/va/08,04,usb,yes,28,34 2006.201.12:57:43.64/valo/01,524.99,yes,locked 2006.201.12:57:43.64/valo/02,534.99,yes,locked 2006.201.12:57:43.64/valo/03,564.99,yes,locked 2006.201.12:57:43.64/valo/04,624.99,yes,locked 2006.201.12:57:43.64/valo/05,734.99,yes,locked 2006.201.12:57:43.64/valo/06,814.99,yes,locked 2006.201.12:57:43.64/valo/07,864.99,yes,locked 2006.201.12:57:43.64/valo/08,884.99,yes,locked 2006.201.12:57:44.73/vb/01,04,usb,yes,29,27 2006.201.12:57:44.73/vb/02,05,usb,yes,27,27 2006.201.12:57:44.73/vb/03,04,usb,yes,28,31 2006.201.12:57:44.73/vb/04,05,usb,yes,29,28 2006.201.12:57:44.73/vb/05,04,usb,yes,25,28 2006.201.12:57:44.73/vb/06,04,usb,yes,30,26 2006.201.12:57:44.73/vb/07,04,usb,yes,30,29 2006.201.12:57:44.73/vb/08,04,usb,yes,27,30 2006.201.12:57:44.96/vblo/01,629.99,yes,locked 2006.201.12:57:44.96/vblo/02,634.99,yes,locked 2006.201.12:57:44.96/vblo/03,649.99,yes,locked 2006.201.12:57:44.96/vblo/04,679.99,yes,locked 2006.201.12:57:44.96/vblo/05,709.99,yes,locked 2006.201.12:57:44.96/vblo/06,719.99,yes,locked 2006.201.12:57:44.96/vblo/07,734.99,yes,locked 2006.201.12:57:44.96/vblo/08,744.99,yes,locked 2006.201.12:57:45.11/vabw/8 2006.201.12:57:45.26/vbbw/8 2006.201.12:57:45.38/xfe/off,on,14.7 2006.201.12:57:45.76/ifatt/23,28,28,28 2006.201.12:57:46.06/fmout-gps/S +4.59E-07 2006.201.12:57:46.13:!2006.201.13:01:42 2006.201.13:01:42.00:data_valid=off 2006.201.13:01:42.00:"et 2006.201.13:01:42.00:!+3s 2006.201.13:01:45.02:"tape 2006.201.13:01:45.02:postob 2006.201.13:01:45.22/cable/+6.4725E-03 2006.201.13:01:45.22/wx/21.02,1003.9,100 2006.201.13:01:45.30/fmout-gps/S +4.62E-07 2006.201.13:01:45.30:scan_name=201-1306,jd0607,240 2006.201.13:01:45.30:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.201.13:01:46.14#flagr#flagr/antenna,new-source 2006.201.13:01:46.14:checkk5 2006.201.13:01:46.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:01:46.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:01:47.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:01:47.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:01:48.01/chk_obsdata//k5ts1/T2011257??a.dat file size is correct (nominal:960MB, actual:956MB). 2006.201.13:01:48.38/chk_obsdata//k5ts2/T2011257??b.dat file size is correct (nominal:960MB, actual:956MB). 2006.201.13:01:48.75/chk_obsdata//k5ts3/T2011257??c.dat file size is correct (nominal:960MB, actual:956MB). 2006.201.13:01:49.11/chk_obsdata//k5ts4/T2011257??d.dat file size is correct (nominal:960MB, actual:956MB). 2006.201.13:01:49.81/k5log//k5ts1_log_newline 2006.201.13:01:50.50/k5log//k5ts2_log_newline 2006.201.13:01:51.19/k5log//k5ts3_log_newline 2006.201.13:01:51.89/k5log//k5ts4_log_newline 2006.201.13:01:51.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:01:51.92:setupk4=1 2006.201.13:01:51.92$setupk4/echo=on 2006.201.13:01:51.92$setupk4/pcalon 2006.201.13:01:51.92$pcalon/"no phase cal control is implemented here 2006.201.13:01:51.92$setupk4/"tpicd=stop 2006.201.13:01:51.92$setupk4/"rec=synch_on 2006.201.13:01:51.92$setupk4/"rec_mode=128 2006.201.13:01:51.92$setupk4/!* 2006.201.13:01:51.92$setupk4/recpk4 2006.201.13:01:51.92$recpk4/recpatch= 2006.201.13:01:51.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:01:51.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:01:51.92$setupk4/vck44 2006.201.13:01:51.92$vck44/valo=1,524.99 2006.201.13:01:51.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.13:01:51.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.13:01:51.92#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:51.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:51.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:51.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:51.92#ibcon#enter wrdev, iclass 24, count 0 2006.201.13:01:51.92#ibcon#first serial, iclass 24, count 0 2006.201.13:01:51.92#ibcon#enter sib2, iclass 24, count 0 2006.201.13:01:51.92#ibcon#flushed, iclass 24, count 0 2006.201.13:01:51.92#ibcon#about to write, iclass 24, count 0 2006.201.13:01:51.92#ibcon#wrote, iclass 24, count 0 2006.201.13:01:51.92#ibcon#about to read 3, iclass 24, count 0 2006.201.13:01:51.96#ibcon#read 3, iclass 24, count 0 2006.201.13:01:51.96#ibcon#about to read 4, iclass 24, count 0 2006.201.13:01:51.96#ibcon#read 4, iclass 24, count 0 2006.201.13:01:51.96#ibcon#about to read 5, iclass 24, count 0 2006.201.13:01:51.96#ibcon#read 5, iclass 24, count 0 2006.201.13:01:51.96#ibcon#about to read 6, iclass 24, count 0 2006.201.13:01:51.96#ibcon#read 6, iclass 24, count 0 2006.201.13:01:51.96#ibcon#end of sib2, iclass 24, count 0 2006.201.13:01:51.96#ibcon#*mode == 0, iclass 24, count 0 2006.201.13:01:51.96#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.13:01:51.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:01:51.96#ibcon#*before write, iclass 24, count 0 2006.201.13:01:51.96#ibcon#enter sib2, iclass 24, count 0 2006.201.13:01:51.96#ibcon#flushed, iclass 24, count 0 2006.201.13:01:51.96#ibcon#about to write, iclass 24, count 0 2006.201.13:01:51.96#ibcon#wrote, iclass 24, count 0 2006.201.13:01:51.96#ibcon#about to read 3, iclass 24, count 0 2006.201.13:01:52.01#ibcon#read 3, iclass 24, count 0 2006.201.13:01:52.01#ibcon#about to read 4, iclass 24, count 0 2006.201.13:01:52.01#ibcon#read 4, iclass 24, count 0 2006.201.13:01:52.01#ibcon#about to read 5, iclass 24, count 0 2006.201.13:01:52.01#ibcon#read 5, iclass 24, count 0 2006.201.13:01:52.01#ibcon#about to read 6, iclass 24, count 0 2006.201.13:01:52.01#ibcon#read 6, iclass 24, count 0 2006.201.13:01:52.01#ibcon#end of sib2, iclass 24, count 0 2006.201.13:01:52.01#ibcon#*after write, iclass 24, count 0 2006.201.13:01:52.01#ibcon#*before return 0, iclass 24, count 0 2006.201.13:01:52.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:52.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:52.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.13:01:52.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.13:01:52.01$vck44/va=1,8 2006.201.13:01:52.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.13:01:52.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.13:01:52.01#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:52.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:52.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:52.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:52.01#ibcon#enter wrdev, iclass 26, count 2 2006.201.13:01:52.01#ibcon#first serial, iclass 26, count 2 2006.201.13:01:52.01#ibcon#enter sib2, iclass 26, count 2 2006.201.13:01:52.01#ibcon#flushed, iclass 26, count 2 2006.201.13:01:52.01#ibcon#about to write, iclass 26, count 2 2006.201.13:01:52.01#ibcon#wrote, iclass 26, count 2 2006.201.13:01:52.01#ibcon#about to read 3, iclass 26, count 2 2006.201.13:01:52.03#ibcon#read 3, iclass 26, count 2 2006.201.13:01:52.03#ibcon#about to read 4, iclass 26, count 2 2006.201.13:01:52.03#ibcon#read 4, iclass 26, count 2 2006.201.13:01:52.03#ibcon#about to read 5, iclass 26, count 2 2006.201.13:01:52.03#ibcon#read 5, iclass 26, count 2 2006.201.13:01:52.03#ibcon#about to read 6, iclass 26, count 2 2006.201.13:01:52.03#ibcon#read 6, iclass 26, count 2 2006.201.13:01:52.03#ibcon#end of sib2, iclass 26, count 2 2006.201.13:01:52.03#ibcon#*mode == 0, iclass 26, count 2 2006.201.13:01:52.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.13:01:52.03#ibcon#[25=AT01-08\r\n] 2006.201.13:01:52.03#ibcon#*before write, iclass 26, count 2 2006.201.13:01:52.03#ibcon#enter sib2, iclass 26, count 2 2006.201.13:01:52.03#ibcon#flushed, iclass 26, count 2 2006.201.13:01:52.03#ibcon#about to write, iclass 26, count 2 2006.201.13:01:52.03#ibcon#wrote, iclass 26, count 2 2006.201.13:01:52.03#ibcon#about to read 3, iclass 26, count 2 2006.201.13:01:52.07#ibcon#read 3, iclass 26, count 2 2006.201.13:01:52.07#ibcon#about to read 4, iclass 26, count 2 2006.201.13:01:52.07#ibcon#read 4, iclass 26, count 2 2006.201.13:01:52.07#ibcon#about to read 5, iclass 26, count 2 2006.201.13:01:52.07#ibcon#read 5, iclass 26, count 2 2006.201.13:01:52.07#ibcon#about to read 6, iclass 26, count 2 2006.201.13:01:52.07#ibcon#read 6, iclass 26, count 2 2006.201.13:01:52.07#ibcon#end of sib2, iclass 26, count 2 2006.201.13:01:52.07#ibcon#*after write, iclass 26, count 2 2006.201.13:01:52.07#ibcon#*before return 0, iclass 26, count 2 2006.201.13:01:52.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:52.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:52.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.13:01:52.07#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:52.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:52.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:52.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:52.19#ibcon#enter wrdev, iclass 26, count 0 2006.201.13:01:52.19#ibcon#first serial, iclass 26, count 0 2006.201.13:01:52.19#ibcon#enter sib2, iclass 26, count 0 2006.201.13:01:52.19#ibcon#flushed, iclass 26, count 0 2006.201.13:01:52.19#ibcon#about to write, iclass 26, count 0 2006.201.13:01:52.19#ibcon#wrote, iclass 26, count 0 2006.201.13:01:52.19#ibcon#about to read 3, iclass 26, count 0 2006.201.13:01:52.22#ibcon#read 3, iclass 26, count 0 2006.201.13:01:52.22#ibcon#about to read 4, iclass 26, count 0 2006.201.13:01:52.22#ibcon#read 4, iclass 26, count 0 2006.201.13:01:52.22#ibcon#about to read 5, iclass 26, count 0 2006.201.13:01:52.22#ibcon#read 5, iclass 26, count 0 2006.201.13:01:52.22#ibcon#about to read 6, iclass 26, count 0 2006.201.13:01:52.22#ibcon#read 6, iclass 26, count 0 2006.201.13:01:52.22#ibcon#end of sib2, iclass 26, count 0 2006.201.13:01:52.22#ibcon#*mode == 0, iclass 26, count 0 2006.201.13:01:52.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.13:01:52.22#ibcon#[25=USB\r\n] 2006.201.13:01:52.22#ibcon#*before write, iclass 26, count 0 2006.201.13:01:52.22#ibcon#enter sib2, iclass 26, count 0 2006.201.13:01:52.22#ibcon#flushed, iclass 26, count 0 2006.201.13:01:52.22#ibcon#about to write, iclass 26, count 0 2006.201.13:01:52.22#ibcon#wrote, iclass 26, count 0 2006.201.13:01:52.22#ibcon#about to read 3, iclass 26, count 0 2006.201.13:01:52.25#ibcon#read 3, iclass 26, count 0 2006.201.13:01:52.25#ibcon#about to read 4, iclass 26, count 0 2006.201.13:01:52.25#ibcon#read 4, iclass 26, count 0 2006.201.13:01:52.25#ibcon#about to read 5, iclass 26, count 0 2006.201.13:01:52.25#ibcon#read 5, iclass 26, count 0 2006.201.13:01:52.25#ibcon#about to read 6, iclass 26, count 0 2006.201.13:01:52.25#ibcon#read 6, iclass 26, count 0 2006.201.13:01:52.25#ibcon#end of sib2, iclass 26, count 0 2006.201.13:01:52.25#ibcon#*after write, iclass 26, count 0 2006.201.13:01:52.25#ibcon#*before return 0, iclass 26, count 0 2006.201.13:01:52.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:52.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:52.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.13:01:52.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.13:01:52.25$vck44/valo=2,534.99 2006.201.13:01:52.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.13:01:52.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.13:01:52.25#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:52.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:52.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:52.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:52.25#ibcon#enter wrdev, iclass 28, count 0 2006.201.13:01:52.25#ibcon#first serial, iclass 28, count 0 2006.201.13:01:52.25#ibcon#enter sib2, iclass 28, count 0 2006.201.13:01:52.25#ibcon#flushed, iclass 28, count 0 2006.201.13:01:52.25#ibcon#about to write, iclass 28, count 0 2006.201.13:01:52.25#ibcon#wrote, iclass 28, count 0 2006.201.13:01:52.25#ibcon#about to read 3, iclass 28, count 0 2006.201.13:01:52.27#ibcon#read 3, iclass 28, count 0 2006.201.13:01:52.27#ibcon#about to read 4, iclass 28, count 0 2006.201.13:01:52.27#ibcon#read 4, iclass 28, count 0 2006.201.13:01:52.27#ibcon#about to read 5, iclass 28, count 0 2006.201.13:01:52.27#ibcon#read 5, iclass 28, count 0 2006.201.13:01:52.27#ibcon#about to read 6, iclass 28, count 0 2006.201.13:01:52.27#ibcon#read 6, iclass 28, count 0 2006.201.13:01:52.27#ibcon#end of sib2, iclass 28, count 0 2006.201.13:01:52.27#ibcon#*mode == 0, iclass 28, count 0 2006.201.13:01:52.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.13:01:52.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:01:52.27#ibcon#*before write, iclass 28, count 0 2006.201.13:01:52.27#ibcon#enter sib2, iclass 28, count 0 2006.201.13:01:52.27#ibcon#flushed, iclass 28, count 0 2006.201.13:01:52.27#ibcon#about to write, iclass 28, count 0 2006.201.13:01:52.27#ibcon#wrote, iclass 28, count 0 2006.201.13:01:52.27#ibcon#about to read 3, iclass 28, count 0 2006.201.13:01:52.31#ibcon#read 3, iclass 28, count 0 2006.201.13:01:52.31#ibcon#about to read 4, iclass 28, count 0 2006.201.13:01:52.31#ibcon#read 4, iclass 28, count 0 2006.201.13:01:52.31#ibcon#about to read 5, iclass 28, count 0 2006.201.13:01:52.31#ibcon#read 5, iclass 28, count 0 2006.201.13:01:52.31#ibcon#about to read 6, iclass 28, count 0 2006.201.13:01:52.31#ibcon#read 6, iclass 28, count 0 2006.201.13:01:52.31#ibcon#end of sib2, iclass 28, count 0 2006.201.13:01:52.31#ibcon#*after write, iclass 28, count 0 2006.201.13:01:52.31#ibcon#*before return 0, iclass 28, count 0 2006.201.13:01:52.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:52.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:52.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.13:01:52.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.13:01:52.31$vck44/va=2,7 2006.201.13:01:52.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.13:01:52.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.13:01:52.31#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:52.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:52.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:52.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:52.37#ibcon#enter wrdev, iclass 30, count 2 2006.201.13:01:52.37#ibcon#first serial, iclass 30, count 2 2006.201.13:01:52.37#ibcon#enter sib2, iclass 30, count 2 2006.201.13:01:52.37#ibcon#flushed, iclass 30, count 2 2006.201.13:01:52.37#ibcon#about to write, iclass 30, count 2 2006.201.13:01:52.37#ibcon#wrote, iclass 30, count 2 2006.201.13:01:52.37#ibcon#about to read 3, iclass 30, count 2 2006.201.13:01:52.39#ibcon#read 3, iclass 30, count 2 2006.201.13:01:52.39#ibcon#about to read 4, iclass 30, count 2 2006.201.13:01:52.39#ibcon#read 4, iclass 30, count 2 2006.201.13:01:52.39#ibcon#about to read 5, iclass 30, count 2 2006.201.13:01:52.39#ibcon#read 5, iclass 30, count 2 2006.201.13:01:52.39#ibcon#about to read 6, iclass 30, count 2 2006.201.13:01:52.39#ibcon#read 6, iclass 30, count 2 2006.201.13:01:52.39#ibcon#end of sib2, iclass 30, count 2 2006.201.13:01:52.39#ibcon#*mode == 0, iclass 30, count 2 2006.201.13:01:52.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.13:01:52.39#ibcon#[25=AT02-07\r\n] 2006.201.13:01:52.39#ibcon#*before write, iclass 30, count 2 2006.201.13:01:52.39#ibcon#enter sib2, iclass 30, count 2 2006.201.13:01:52.39#ibcon#flushed, iclass 30, count 2 2006.201.13:01:52.39#ibcon#about to write, iclass 30, count 2 2006.201.13:01:52.39#ibcon#wrote, iclass 30, count 2 2006.201.13:01:52.39#ibcon#about to read 3, iclass 30, count 2 2006.201.13:01:52.42#ibcon#read 3, iclass 30, count 2 2006.201.13:01:52.42#ibcon#about to read 4, iclass 30, count 2 2006.201.13:01:52.42#ibcon#read 4, iclass 30, count 2 2006.201.13:01:52.42#ibcon#about to read 5, iclass 30, count 2 2006.201.13:01:52.42#ibcon#read 5, iclass 30, count 2 2006.201.13:01:52.42#ibcon#about to read 6, iclass 30, count 2 2006.201.13:01:52.42#ibcon#read 6, iclass 30, count 2 2006.201.13:01:52.42#ibcon#end of sib2, iclass 30, count 2 2006.201.13:01:52.42#ibcon#*after write, iclass 30, count 2 2006.201.13:01:52.42#ibcon#*before return 0, iclass 30, count 2 2006.201.13:01:52.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:52.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:52.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.13:01:52.42#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:52.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:52.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:52.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:52.54#ibcon#enter wrdev, iclass 30, count 0 2006.201.13:01:52.54#ibcon#first serial, iclass 30, count 0 2006.201.13:01:52.54#ibcon#enter sib2, iclass 30, count 0 2006.201.13:01:52.54#ibcon#flushed, iclass 30, count 0 2006.201.13:01:52.54#ibcon#about to write, iclass 30, count 0 2006.201.13:01:52.54#ibcon#wrote, iclass 30, count 0 2006.201.13:01:52.54#ibcon#about to read 3, iclass 30, count 0 2006.201.13:01:52.56#ibcon#read 3, iclass 30, count 0 2006.201.13:01:52.56#ibcon#about to read 4, iclass 30, count 0 2006.201.13:01:52.56#ibcon#read 4, iclass 30, count 0 2006.201.13:01:52.56#ibcon#about to read 5, iclass 30, count 0 2006.201.13:01:52.56#ibcon#read 5, iclass 30, count 0 2006.201.13:01:52.56#ibcon#about to read 6, iclass 30, count 0 2006.201.13:01:52.56#ibcon#read 6, iclass 30, count 0 2006.201.13:01:52.56#ibcon#end of sib2, iclass 30, count 0 2006.201.13:01:52.56#ibcon#*mode == 0, iclass 30, count 0 2006.201.13:01:52.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.13:01:52.56#ibcon#[25=USB\r\n] 2006.201.13:01:52.56#ibcon#*before write, iclass 30, count 0 2006.201.13:01:52.56#ibcon#enter sib2, iclass 30, count 0 2006.201.13:01:52.56#ibcon#flushed, iclass 30, count 0 2006.201.13:01:52.56#ibcon#about to write, iclass 30, count 0 2006.201.13:01:52.56#ibcon#wrote, iclass 30, count 0 2006.201.13:01:52.56#ibcon#about to read 3, iclass 30, count 0 2006.201.13:01:52.59#ibcon#read 3, iclass 30, count 0 2006.201.13:01:52.59#ibcon#about to read 4, iclass 30, count 0 2006.201.13:01:52.59#ibcon#read 4, iclass 30, count 0 2006.201.13:01:52.59#ibcon#about to read 5, iclass 30, count 0 2006.201.13:01:52.59#ibcon#read 5, iclass 30, count 0 2006.201.13:01:52.59#ibcon#about to read 6, iclass 30, count 0 2006.201.13:01:52.59#ibcon#read 6, iclass 30, count 0 2006.201.13:01:52.59#ibcon#end of sib2, iclass 30, count 0 2006.201.13:01:52.59#ibcon#*after write, iclass 30, count 0 2006.201.13:01:52.59#ibcon#*before return 0, iclass 30, count 0 2006.201.13:01:52.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:52.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:52.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.13:01:52.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.13:01:52.59$vck44/valo=3,564.99 2006.201.13:01:52.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.13:01:52.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.13:01:52.59#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:52.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:52.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:52.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:52.59#ibcon#enter wrdev, iclass 32, count 0 2006.201.13:01:52.59#ibcon#first serial, iclass 32, count 0 2006.201.13:01:52.59#ibcon#enter sib2, iclass 32, count 0 2006.201.13:01:52.59#ibcon#flushed, iclass 32, count 0 2006.201.13:01:52.59#ibcon#about to write, iclass 32, count 0 2006.201.13:01:52.59#ibcon#wrote, iclass 32, count 0 2006.201.13:01:52.59#ibcon#about to read 3, iclass 32, count 0 2006.201.13:01:52.61#ibcon#read 3, iclass 32, count 0 2006.201.13:01:52.61#ibcon#about to read 4, iclass 32, count 0 2006.201.13:01:52.61#ibcon#read 4, iclass 32, count 0 2006.201.13:01:52.61#ibcon#about to read 5, iclass 32, count 0 2006.201.13:01:52.61#ibcon#read 5, iclass 32, count 0 2006.201.13:01:52.61#ibcon#about to read 6, iclass 32, count 0 2006.201.13:01:52.61#ibcon#read 6, iclass 32, count 0 2006.201.13:01:52.61#ibcon#end of sib2, iclass 32, count 0 2006.201.13:01:52.61#ibcon#*mode == 0, iclass 32, count 0 2006.201.13:01:52.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.13:01:52.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:01:52.61#ibcon#*before write, iclass 32, count 0 2006.201.13:01:52.61#ibcon#enter sib2, iclass 32, count 0 2006.201.13:01:52.61#ibcon#flushed, iclass 32, count 0 2006.201.13:01:52.61#ibcon#about to write, iclass 32, count 0 2006.201.13:01:52.61#ibcon#wrote, iclass 32, count 0 2006.201.13:01:52.61#ibcon#about to read 3, iclass 32, count 0 2006.201.13:01:52.66#ibcon#read 3, iclass 32, count 0 2006.201.13:01:52.66#ibcon#about to read 4, iclass 32, count 0 2006.201.13:01:52.66#ibcon#read 4, iclass 32, count 0 2006.201.13:01:52.66#ibcon#about to read 5, iclass 32, count 0 2006.201.13:01:52.66#ibcon#read 5, iclass 32, count 0 2006.201.13:01:52.66#ibcon#about to read 6, iclass 32, count 0 2006.201.13:01:52.66#ibcon#read 6, iclass 32, count 0 2006.201.13:01:52.66#ibcon#end of sib2, iclass 32, count 0 2006.201.13:01:52.66#ibcon#*after write, iclass 32, count 0 2006.201.13:01:52.66#ibcon#*before return 0, iclass 32, count 0 2006.201.13:01:52.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:52.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:52.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.13:01:52.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.13:01:52.66$vck44/va=3,8 2006.201.13:01:52.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.13:01:52.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.13:01:52.66#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:52.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:52.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:52.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:52.71#ibcon#enter wrdev, iclass 34, count 2 2006.201.13:01:52.71#ibcon#first serial, iclass 34, count 2 2006.201.13:01:52.71#ibcon#enter sib2, iclass 34, count 2 2006.201.13:01:52.71#ibcon#flushed, iclass 34, count 2 2006.201.13:01:52.71#ibcon#about to write, iclass 34, count 2 2006.201.13:01:52.71#ibcon#wrote, iclass 34, count 2 2006.201.13:01:52.71#ibcon#about to read 3, iclass 34, count 2 2006.201.13:01:52.73#ibcon#read 3, iclass 34, count 2 2006.201.13:01:52.73#ibcon#about to read 4, iclass 34, count 2 2006.201.13:01:52.73#ibcon#read 4, iclass 34, count 2 2006.201.13:01:52.73#ibcon#about to read 5, iclass 34, count 2 2006.201.13:01:52.73#ibcon#read 5, iclass 34, count 2 2006.201.13:01:52.73#ibcon#about to read 6, iclass 34, count 2 2006.201.13:01:52.73#ibcon#read 6, iclass 34, count 2 2006.201.13:01:52.73#ibcon#end of sib2, iclass 34, count 2 2006.201.13:01:52.73#ibcon#*mode == 0, iclass 34, count 2 2006.201.13:01:52.73#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.13:01:52.73#ibcon#[25=AT03-08\r\n] 2006.201.13:01:52.73#ibcon#*before write, iclass 34, count 2 2006.201.13:01:52.73#ibcon#enter sib2, iclass 34, count 2 2006.201.13:01:52.73#ibcon#flushed, iclass 34, count 2 2006.201.13:01:52.73#ibcon#about to write, iclass 34, count 2 2006.201.13:01:52.73#ibcon#wrote, iclass 34, count 2 2006.201.13:01:52.73#ibcon#about to read 3, iclass 34, count 2 2006.201.13:01:52.76#ibcon#read 3, iclass 34, count 2 2006.201.13:01:52.76#ibcon#about to read 4, iclass 34, count 2 2006.201.13:01:52.76#ibcon#read 4, iclass 34, count 2 2006.201.13:01:52.76#ibcon#about to read 5, iclass 34, count 2 2006.201.13:01:52.76#ibcon#read 5, iclass 34, count 2 2006.201.13:01:52.76#ibcon#about to read 6, iclass 34, count 2 2006.201.13:01:52.76#ibcon#read 6, iclass 34, count 2 2006.201.13:01:52.76#ibcon#end of sib2, iclass 34, count 2 2006.201.13:01:52.76#ibcon#*after write, iclass 34, count 2 2006.201.13:01:52.76#ibcon#*before return 0, iclass 34, count 2 2006.201.13:01:52.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:52.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:52.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.13:01:52.76#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:52.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:52.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:52.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:52.88#ibcon#enter wrdev, iclass 34, count 0 2006.201.13:01:52.88#ibcon#first serial, iclass 34, count 0 2006.201.13:01:52.88#ibcon#enter sib2, iclass 34, count 0 2006.201.13:01:52.88#ibcon#flushed, iclass 34, count 0 2006.201.13:01:52.88#ibcon#about to write, iclass 34, count 0 2006.201.13:01:52.88#ibcon#wrote, iclass 34, count 0 2006.201.13:01:52.88#ibcon#about to read 3, iclass 34, count 0 2006.201.13:01:52.90#ibcon#read 3, iclass 34, count 0 2006.201.13:01:52.90#ibcon#about to read 4, iclass 34, count 0 2006.201.13:01:52.90#ibcon#read 4, iclass 34, count 0 2006.201.13:01:52.90#ibcon#about to read 5, iclass 34, count 0 2006.201.13:01:52.90#ibcon#read 5, iclass 34, count 0 2006.201.13:01:52.90#ibcon#about to read 6, iclass 34, count 0 2006.201.13:01:52.90#ibcon#read 6, iclass 34, count 0 2006.201.13:01:52.90#ibcon#end of sib2, iclass 34, count 0 2006.201.13:01:52.90#ibcon#*mode == 0, iclass 34, count 0 2006.201.13:01:52.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.13:01:52.90#ibcon#[25=USB\r\n] 2006.201.13:01:52.90#ibcon#*before write, iclass 34, count 0 2006.201.13:01:52.90#ibcon#enter sib2, iclass 34, count 0 2006.201.13:01:52.90#ibcon#flushed, iclass 34, count 0 2006.201.13:01:52.90#ibcon#about to write, iclass 34, count 0 2006.201.13:01:52.90#ibcon#wrote, iclass 34, count 0 2006.201.13:01:52.90#ibcon#about to read 3, iclass 34, count 0 2006.201.13:01:52.93#ibcon#read 3, iclass 34, count 0 2006.201.13:01:52.93#ibcon#about to read 4, iclass 34, count 0 2006.201.13:01:52.93#ibcon#read 4, iclass 34, count 0 2006.201.13:01:52.93#ibcon#about to read 5, iclass 34, count 0 2006.201.13:01:52.93#ibcon#read 5, iclass 34, count 0 2006.201.13:01:52.93#ibcon#about to read 6, iclass 34, count 0 2006.201.13:01:52.93#ibcon#read 6, iclass 34, count 0 2006.201.13:01:52.93#ibcon#end of sib2, iclass 34, count 0 2006.201.13:01:52.93#ibcon#*after write, iclass 34, count 0 2006.201.13:01:52.93#ibcon#*before return 0, iclass 34, count 0 2006.201.13:01:52.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:52.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:52.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.13:01:52.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.13:01:52.93$vck44/valo=4,624.99 2006.201.13:01:52.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.13:01:52.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.13:01:52.93#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:52.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:52.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:52.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:52.93#ibcon#enter wrdev, iclass 36, count 0 2006.201.13:01:52.93#ibcon#first serial, iclass 36, count 0 2006.201.13:01:52.93#ibcon#enter sib2, iclass 36, count 0 2006.201.13:01:52.93#ibcon#flushed, iclass 36, count 0 2006.201.13:01:52.93#ibcon#about to write, iclass 36, count 0 2006.201.13:01:52.93#ibcon#wrote, iclass 36, count 0 2006.201.13:01:52.93#ibcon#about to read 3, iclass 36, count 0 2006.201.13:01:52.95#ibcon#read 3, iclass 36, count 0 2006.201.13:01:52.95#ibcon#about to read 4, iclass 36, count 0 2006.201.13:01:52.95#ibcon#read 4, iclass 36, count 0 2006.201.13:01:52.95#ibcon#about to read 5, iclass 36, count 0 2006.201.13:01:52.95#ibcon#read 5, iclass 36, count 0 2006.201.13:01:52.95#ibcon#about to read 6, iclass 36, count 0 2006.201.13:01:52.95#ibcon#read 6, iclass 36, count 0 2006.201.13:01:52.95#ibcon#end of sib2, iclass 36, count 0 2006.201.13:01:52.95#ibcon#*mode == 0, iclass 36, count 0 2006.201.13:01:52.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.13:01:52.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:01:52.95#ibcon#*before write, iclass 36, count 0 2006.201.13:01:52.95#ibcon#enter sib2, iclass 36, count 0 2006.201.13:01:52.95#ibcon#flushed, iclass 36, count 0 2006.201.13:01:52.95#ibcon#about to write, iclass 36, count 0 2006.201.13:01:52.95#ibcon#wrote, iclass 36, count 0 2006.201.13:01:52.95#ibcon#about to read 3, iclass 36, count 0 2006.201.13:01:53.00#ibcon#read 3, iclass 36, count 0 2006.201.13:01:53.00#ibcon#about to read 4, iclass 36, count 0 2006.201.13:01:53.00#ibcon#read 4, iclass 36, count 0 2006.201.13:01:53.00#ibcon#about to read 5, iclass 36, count 0 2006.201.13:01:53.00#ibcon#read 5, iclass 36, count 0 2006.201.13:01:53.00#ibcon#about to read 6, iclass 36, count 0 2006.201.13:01:53.00#ibcon#read 6, iclass 36, count 0 2006.201.13:01:53.00#ibcon#end of sib2, iclass 36, count 0 2006.201.13:01:53.00#ibcon#*after write, iclass 36, count 0 2006.201.13:01:53.00#ibcon#*before return 0, iclass 36, count 0 2006.201.13:01:53.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:53.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:53.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.13:01:53.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.13:01:53.00$vck44/va=4,7 2006.201.13:01:53.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.13:01:53.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.13:01:53.00#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:53.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:53.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:53.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:53.05#ibcon#enter wrdev, iclass 38, count 2 2006.201.13:01:53.05#ibcon#first serial, iclass 38, count 2 2006.201.13:01:53.05#ibcon#enter sib2, iclass 38, count 2 2006.201.13:01:53.05#ibcon#flushed, iclass 38, count 2 2006.201.13:01:53.05#ibcon#about to write, iclass 38, count 2 2006.201.13:01:53.05#ibcon#wrote, iclass 38, count 2 2006.201.13:01:53.05#ibcon#about to read 3, iclass 38, count 2 2006.201.13:01:53.07#ibcon#read 3, iclass 38, count 2 2006.201.13:01:53.07#ibcon#about to read 4, iclass 38, count 2 2006.201.13:01:53.07#ibcon#read 4, iclass 38, count 2 2006.201.13:01:53.07#ibcon#about to read 5, iclass 38, count 2 2006.201.13:01:53.07#ibcon#read 5, iclass 38, count 2 2006.201.13:01:53.07#ibcon#about to read 6, iclass 38, count 2 2006.201.13:01:53.07#ibcon#read 6, iclass 38, count 2 2006.201.13:01:53.07#ibcon#end of sib2, iclass 38, count 2 2006.201.13:01:53.07#ibcon#*mode == 0, iclass 38, count 2 2006.201.13:01:53.07#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.13:01:53.07#ibcon#[25=AT04-07\r\n] 2006.201.13:01:53.07#ibcon#*before write, iclass 38, count 2 2006.201.13:01:53.07#ibcon#enter sib2, iclass 38, count 2 2006.201.13:01:53.07#ibcon#flushed, iclass 38, count 2 2006.201.13:01:53.07#ibcon#about to write, iclass 38, count 2 2006.201.13:01:53.07#ibcon#wrote, iclass 38, count 2 2006.201.13:01:53.07#ibcon#about to read 3, iclass 38, count 2 2006.201.13:01:53.10#ibcon#read 3, iclass 38, count 2 2006.201.13:01:53.10#ibcon#about to read 4, iclass 38, count 2 2006.201.13:01:53.10#ibcon#read 4, iclass 38, count 2 2006.201.13:01:53.10#ibcon#about to read 5, iclass 38, count 2 2006.201.13:01:53.10#ibcon#read 5, iclass 38, count 2 2006.201.13:01:53.10#ibcon#about to read 6, iclass 38, count 2 2006.201.13:01:53.10#ibcon#read 6, iclass 38, count 2 2006.201.13:01:53.10#ibcon#end of sib2, iclass 38, count 2 2006.201.13:01:53.10#ibcon#*after write, iclass 38, count 2 2006.201.13:01:53.10#ibcon#*before return 0, iclass 38, count 2 2006.201.13:01:53.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:53.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:53.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.13:01:53.10#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:53.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:53.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:53.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:53.22#ibcon#enter wrdev, iclass 38, count 0 2006.201.13:01:53.22#ibcon#first serial, iclass 38, count 0 2006.201.13:01:53.22#ibcon#enter sib2, iclass 38, count 0 2006.201.13:01:53.22#ibcon#flushed, iclass 38, count 0 2006.201.13:01:53.22#ibcon#about to write, iclass 38, count 0 2006.201.13:01:53.22#ibcon#wrote, iclass 38, count 0 2006.201.13:01:53.22#ibcon#about to read 3, iclass 38, count 0 2006.201.13:01:53.24#ibcon#read 3, iclass 38, count 0 2006.201.13:01:53.24#ibcon#about to read 4, iclass 38, count 0 2006.201.13:01:53.24#ibcon#read 4, iclass 38, count 0 2006.201.13:01:53.24#ibcon#about to read 5, iclass 38, count 0 2006.201.13:01:53.24#ibcon#read 5, iclass 38, count 0 2006.201.13:01:53.24#ibcon#about to read 6, iclass 38, count 0 2006.201.13:01:53.24#ibcon#read 6, iclass 38, count 0 2006.201.13:01:53.24#ibcon#end of sib2, iclass 38, count 0 2006.201.13:01:53.24#ibcon#*mode == 0, iclass 38, count 0 2006.201.13:01:53.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.13:01:53.24#ibcon#[25=USB\r\n] 2006.201.13:01:53.24#ibcon#*before write, iclass 38, count 0 2006.201.13:01:53.24#ibcon#enter sib2, iclass 38, count 0 2006.201.13:01:53.24#ibcon#flushed, iclass 38, count 0 2006.201.13:01:53.24#ibcon#about to write, iclass 38, count 0 2006.201.13:01:53.24#ibcon#wrote, iclass 38, count 0 2006.201.13:01:53.24#ibcon#about to read 3, iclass 38, count 0 2006.201.13:01:53.27#ibcon#read 3, iclass 38, count 0 2006.201.13:01:53.27#ibcon#about to read 4, iclass 38, count 0 2006.201.13:01:53.27#ibcon#read 4, iclass 38, count 0 2006.201.13:01:53.27#ibcon#about to read 5, iclass 38, count 0 2006.201.13:01:53.27#ibcon#read 5, iclass 38, count 0 2006.201.13:01:53.27#ibcon#about to read 6, iclass 38, count 0 2006.201.13:01:53.27#ibcon#read 6, iclass 38, count 0 2006.201.13:01:53.27#ibcon#end of sib2, iclass 38, count 0 2006.201.13:01:53.27#ibcon#*after write, iclass 38, count 0 2006.201.13:01:53.27#ibcon#*before return 0, iclass 38, count 0 2006.201.13:01:53.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:53.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:53.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.13:01:53.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.13:01:53.27$vck44/valo=5,734.99 2006.201.13:01:53.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.13:01:53.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.13:01:53.27#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:53.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:53.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:53.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:53.27#ibcon#enter wrdev, iclass 40, count 0 2006.201.13:01:53.27#ibcon#first serial, iclass 40, count 0 2006.201.13:01:53.27#ibcon#enter sib2, iclass 40, count 0 2006.201.13:01:53.27#ibcon#flushed, iclass 40, count 0 2006.201.13:01:53.27#ibcon#about to write, iclass 40, count 0 2006.201.13:01:53.27#ibcon#wrote, iclass 40, count 0 2006.201.13:01:53.27#ibcon#about to read 3, iclass 40, count 0 2006.201.13:01:53.29#ibcon#read 3, iclass 40, count 0 2006.201.13:01:53.29#ibcon#about to read 4, iclass 40, count 0 2006.201.13:01:53.29#ibcon#read 4, iclass 40, count 0 2006.201.13:01:53.29#ibcon#about to read 5, iclass 40, count 0 2006.201.13:01:53.29#ibcon#read 5, iclass 40, count 0 2006.201.13:01:53.29#ibcon#about to read 6, iclass 40, count 0 2006.201.13:01:53.29#ibcon#read 6, iclass 40, count 0 2006.201.13:01:53.29#ibcon#end of sib2, iclass 40, count 0 2006.201.13:01:53.29#ibcon#*mode == 0, iclass 40, count 0 2006.201.13:01:53.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.13:01:53.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:01:53.29#ibcon#*before write, iclass 40, count 0 2006.201.13:01:53.29#ibcon#enter sib2, iclass 40, count 0 2006.201.13:01:53.29#ibcon#flushed, iclass 40, count 0 2006.201.13:01:53.29#ibcon#about to write, iclass 40, count 0 2006.201.13:01:53.29#ibcon#wrote, iclass 40, count 0 2006.201.13:01:53.29#ibcon#about to read 3, iclass 40, count 0 2006.201.13:01:53.33#ibcon#read 3, iclass 40, count 0 2006.201.13:01:53.33#ibcon#about to read 4, iclass 40, count 0 2006.201.13:01:53.33#ibcon#read 4, iclass 40, count 0 2006.201.13:01:53.33#ibcon#about to read 5, iclass 40, count 0 2006.201.13:01:53.33#ibcon#read 5, iclass 40, count 0 2006.201.13:01:53.33#ibcon#about to read 6, iclass 40, count 0 2006.201.13:01:53.33#ibcon#read 6, iclass 40, count 0 2006.201.13:01:53.33#ibcon#end of sib2, iclass 40, count 0 2006.201.13:01:53.33#ibcon#*after write, iclass 40, count 0 2006.201.13:01:53.33#ibcon#*before return 0, iclass 40, count 0 2006.201.13:01:53.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:53.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:53.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.13:01:53.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.13:01:53.33$vck44/va=5,4 2006.201.13:01:53.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.13:01:53.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.13:01:53.33#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:53.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:53.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:53.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:53.39#ibcon#enter wrdev, iclass 4, count 2 2006.201.13:01:53.39#ibcon#first serial, iclass 4, count 2 2006.201.13:01:53.39#ibcon#enter sib2, iclass 4, count 2 2006.201.13:01:53.39#ibcon#flushed, iclass 4, count 2 2006.201.13:01:53.39#ibcon#about to write, iclass 4, count 2 2006.201.13:01:53.39#ibcon#wrote, iclass 4, count 2 2006.201.13:01:53.39#ibcon#about to read 3, iclass 4, count 2 2006.201.13:01:53.41#ibcon#read 3, iclass 4, count 2 2006.201.13:01:53.41#ibcon#about to read 4, iclass 4, count 2 2006.201.13:01:53.41#ibcon#read 4, iclass 4, count 2 2006.201.13:01:53.41#ibcon#about to read 5, iclass 4, count 2 2006.201.13:01:53.41#ibcon#read 5, iclass 4, count 2 2006.201.13:01:53.41#ibcon#about to read 6, iclass 4, count 2 2006.201.13:01:53.41#ibcon#read 6, iclass 4, count 2 2006.201.13:01:53.41#ibcon#end of sib2, iclass 4, count 2 2006.201.13:01:53.41#ibcon#*mode == 0, iclass 4, count 2 2006.201.13:01:53.41#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.13:01:53.41#ibcon#[25=AT05-04\r\n] 2006.201.13:01:53.41#ibcon#*before write, iclass 4, count 2 2006.201.13:01:53.41#ibcon#enter sib2, iclass 4, count 2 2006.201.13:01:53.41#ibcon#flushed, iclass 4, count 2 2006.201.13:01:53.41#ibcon#about to write, iclass 4, count 2 2006.201.13:01:53.41#ibcon#wrote, iclass 4, count 2 2006.201.13:01:53.41#ibcon#about to read 3, iclass 4, count 2 2006.201.13:01:53.44#ibcon#read 3, iclass 4, count 2 2006.201.13:01:53.44#ibcon#about to read 4, iclass 4, count 2 2006.201.13:01:53.44#ibcon#read 4, iclass 4, count 2 2006.201.13:01:53.44#ibcon#about to read 5, iclass 4, count 2 2006.201.13:01:53.44#ibcon#read 5, iclass 4, count 2 2006.201.13:01:53.44#ibcon#about to read 6, iclass 4, count 2 2006.201.13:01:53.44#ibcon#read 6, iclass 4, count 2 2006.201.13:01:53.44#ibcon#end of sib2, iclass 4, count 2 2006.201.13:01:53.44#ibcon#*after write, iclass 4, count 2 2006.201.13:01:53.44#ibcon#*before return 0, iclass 4, count 2 2006.201.13:01:53.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:53.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:53.44#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.13:01:53.44#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:53.44#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:53.56#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:53.56#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:53.56#ibcon#enter wrdev, iclass 4, count 0 2006.201.13:01:53.56#ibcon#first serial, iclass 4, count 0 2006.201.13:01:53.56#ibcon#enter sib2, iclass 4, count 0 2006.201.13:01:53.56#ibcon#flushed, iclass 4, count 0 2006.201.13:01:53.56#ibcon#about to write, iclass 4, count 0 2006.201.13:01:53.56#ibcon#wrote, iclass 4, count 0 2006.201.13:01:53.56#ibcon#about to read 3, iclass 4, count 0 2006.201.13:01:53.58#ibcon#read 3, iclass 4, count 0 2006.201.13:01:53.58#ibcon#about to read 4, iclass 4, count 0 2006.201.13:01:53.58#ibcon#read 4, iclass 4, count 0 2006.201.13:01:53.58#ibcon#about to read 5, iclass 4, count 0 2006.201.13:01:53.58#ibcon#read 5, iclass 4, count 0 2006.201.13:01:53.58#ibcon#about to read 6, iclass 4, count 0 2006.201.13:01:53.58#ibcon#read 6, iclass 4, count 0 2006.201.13:01:53.58#ibcon#end of sib2, iclass 4, count 0 2006.201.13:01:53.58#ibcon#*mode == 0, iclass 4, count 0 2006.201.13:01:53.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.13:01:53.58#ibcon#[25=USB\r\n] 2006.201.13:01:53.58#ibcon#*before write, iclass 4, count 0 2006.201.13:01:53.58#ibcon#enter sib2, iclass 4, count 0 2006.201.13:01:53.58#ibcon#flushed, iclass 4, count 0 2006.201.13:01:53.58#ibcon#about to write, iclass 4, count 0 2006.201.13:01:53.58#ibcon#wrote, iclass 4, count 0 2006.201.13:01:53.58#ibcon#about to read 3, iclass 4, count 0 2006.201.13:01:53.61#ibcon#read 3, iclass 4, count 0 2006.201.13:01:53.61#ibcon#about to read 4, iclass 4, count 0 2006.201.13:01:53.61#ibcon#read 4, iclass 4, count 0 2006.201.13:01:53.61#ibcon#about to read 5, iclass 4, count 0 2006.201.13:01:53.61#ibcon#read 5, iclass 4, count 0 2006.201.13:01:53.61#ibcon#about to read 6, iclass 4, count 0 2006.201.13:01:53.61#ibcon#read 6, iclass 4, count 0 2006.201.13:01:53.61#ibcon#end of sib2, iclass 4, count 0 2006.201.13:01:53.61#ibcon#*after write, iclass 4, count 0 2006.201.13:01:53.61#ibcon#*before return 0, iclass 4, count 0 2006.201.13:01:53.61#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:53.61#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:53.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.13:01:53.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.13:01:53.61$vck44/valo=6,814.99 2006.201.13:01:53.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.13:01:53.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.13:01:53.61#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:53.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:53.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:53.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:53.61#ibcon#enter wrdev, iclass 6, count 0 2006.201.13:01:53.61#ibcon#first serial, iclass 6, count 0 2006.201.13:01:53.61#ibcon#enter sib2, iclass 6, count 0 2006.201.13:01:53.61#ibcon#flushed, iclass 6, count 0 2006.201.13:01:53.61#ibcon#about to write, iclass 6, count 0 2006.201.13:01:53.61#ibcon#wrote, iclass 6, count 0 2006.201.13:01:53.61#ibcon#about to read 3, iclass 6, count 0 2006.201.13:01:53.63#ibcon#read 3, iclass 6, count 0 2006.201.13:01:53.63#ibcon#about to read 4, iclass 6, count 0 2006.201.13:01:53.63#ibcon#read 4, iclass 6, count 0 2006.201.13:01:53.63#ibcon#about to read 5, iclass 6, count 0 2006.201.13:01:53.63#ibcon#read 5, iclass 6, count 0 2006.201.13:01:53.63#ibcon#about to read 6, iclass 6, count 0 2006.201.13:01:53.63#ibcon#read 6, iclass 6, count 0 2006.201.13:01:53.63#ibcon#end of sib2, iclass 6, count 0 2006.201.13:01:53.63#ibcon#*mode == 0, iclass 6, count 0 2006.201.13:01:53.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.13:01:53.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:01:53.63#ibcon#*before write, iclass 6, count 0 2006.201.13:01:53.63#ibcon#enter sib2, iclass 6, count 0 2006.201.13:01:53.63#ibcon#flushed, iclass 6, count 0 2006.201.13:01:53.63#ibcon#about to write, iclass 6, count 0 2006.201.13:01:53.63#ibcon#wrote, iclass 6, count 0 2006.201.13:01:53.63#ibcon#about to read 3, iclass 6, count 0 2006.201.13:01:53.68#ibcon#read 3, iclass 6, count 0 2006.201.13:01:53.68#ibcon#about to read 4, iclass 6, count 0 2006.201.13:01:53.68#ibcon#read 4, iclass 6, count 0 2006.201.13:01:53.68#ibcon#about to read 5, iclass 6, count 0 2006.201.13:01:53.68#ibcon#read 5, iclass 6, count 0 2006.201.13:01:53.68#ibcon#about to read 6, iclass 6, count 0 2006.201.13:01:53.68#ibcon#read 6, iclass 6, count 0 2006.201.13:01:53.68#ibcon#end of sib2, iclass 6, count 0 2006.201.13:01:53.68#ibcon#*after write, iclass 6, count 0 2006.201.13:01:53.68#ibcon#*before return 0, iclass 6, count 0 2006.201.13:01:53.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:53.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:53.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.13:01:53.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.13:01:53.68$vck44/va=6,5 2006.201.13:01:53.68#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.13:01:53.68#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.13:01:53.68#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:53.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:53.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:53.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:53.73#ibcon#enter wrdev, iclass 10, count 2 2006.201.13:01:53.73#ibcon#first serial, iclass 10, count 2 2006.201.13:01:53.73#ibcon#enter sib2, iclass 10, count 2 2006.201.13:01:53.73#ibcon#flushed, iclass 10, count 2 2006.201.13:01:53.73#ibcon#about to write, iclass 10, count 2 2006.201.13:01:53.73#ibcon#wrote, iclass 10, count 2 2006.201.13:01:53.73#ibcon#about to read 3, iclass 10, count 2 2006.201.13:01:53.75#ibcon#read 3, iclass 10, count 2 2006.201.13:01:53.75#ibcon#about to read 4, iclass 10, count 2 2006.201.13:01:53.75#ibcon#read 4, iclass 10, count 2 2006.201.13:01:53.75#ibcon#about to read 5, iclass 10, count 2 2006.201.13:01:53.75#ibcon#read 5, iclass 10, count 2 2006.201.13:01:53.75#ibcon#about to read 6, iclass 10, count 2 2006.201.13:01:53.75#ibcon#read 6, iclass 10, count 2 2006.201.13:01:53.75#ibcon#end of sib2, iclass 10, count 2 2006.201.13:01:53.75#ibcon#*mode == 0, iclass 10, count 2 2006.201.13:01:53.75#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.13:01:53.75#ibcon#[25=AT06-05\r\n] 2006.201.13:01:53.75#ibcon#*before write, iclass 10, count 2 2006.201.13:01:53.75#ibcon#enter sib2, iclass 10, count 2 2006.201.13:01:53.75#ibcon#flushed, iclass 10, count 2 2006.201.13:01:53.75#ibcon#about to write, iclass 10, count 2 2006.201.13:01:53.75#ibcon#wrote, iclass 10, count 2 2006.201.13:01:53.75#ibcon#about to read 3, iclass 10, count 2 2006.201.13:01:53.78#ibcon#read 3, iclass 10, count 2 2006.201.13:01:53.78#ibcon#about to read 4, iclass 10, count 2 2006.201.13:01:53.78#ibcon#read 4, iclass 10, count 2 2006.201.13:01:53.78#ibcon#about to read 5, iclass 10, count 2 2006.201.13:01:53.78#ibcon#read 5, iclass 10, count 2 2006.201.13:01:53.78#ibcon#about to read 6, iclass 10, count 2 2006.201.13:01:53.78#ibcon#read 6, iclass 10, count 2 2006.201.13:01:53.78#ibcon#end of sib2, iclass 10, count 2 2006.201.13:01:53.78#ibcon#*after write, iclass 10, count 2 2006.201.13:01:53.78#ibcon#*before return 0, iclass 10, count 2 2006.201.13:01:53.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:53.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:53.78#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.13:01:53.78#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:53.78#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:53.90#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:53.90#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:53.90#ibcon#enter wrdev, iclass 10, count 0 2006.201.13:01:53.90#ibcon#first serial, iclass 10, count 0 2006.201.13:01:53.90#ibcon#enter sib2, iclass 10, count 0 2006.201.13:01:53.90#ibcon#flushed, iclass 10, count 0 2006.201.13:01:53.90#ibcon#about to write, iclass 10, count 0 2006.201.13:01:53.90#ibcon#wrote, iclass 10, count 0 2006.201.13:01:53.90#ibcon#about to read 3, iclass 10, count 0 2006.201.13:01:53.92#ibcon#read 3, iclass 10, count 0 2006.201.13:01:53.92#ibcon#about to read 4, iclass 10, count 0 2006.201.13:01:53.92#ibcon#read 4, iclass 10, count 0 2006.201.13:01:53.92#ibcon#about to read 5, iclass 10, count 0 2006.201.13:01:53.92#ibcon#read 5, iclass 10, count 0 2006.201.13:01:53.92#ibcon#about to read 6, iclass 10, count 0 2006.201.13:01:53.92#ibcon#read 6, iclass 10, count 0 2006.201.13:01:53.92#ibcon#end of sib2, iclass 10, count 0 2006.201.13:01:53.92#ibcon#*mode == 0, iclass 10, count 0 2006.201.13:01:53.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.13:01:53.92#ibcon#[25=USB\r\n] 2006.201.13:01:53.92#ibcon#*before write, iclass 10, count 0 2006.201.13:01:53.92#ibcon#enter sib2, iclass 10, count 0 2006.201.13:01:53.92#ibcon#flushed, iclass 10, count 0 2006.201.13:01:53.92#ibcon#about to write, iclass 10, count 0 2006.201.13:01:53.92#ibcon#wrote, iclass 10, count 0 2006.201.13:01:53.92#ibcon#about to read 3, iclass 10, count 0 2006.201.13:01:53.95#ibcon#read 3, iclass 10, count 0 2006.201.13:01:53.95#ibcon#about to read 4, iclass 10, count 0 2006.201.13:01:53.95#ibcon#read 4, iclass 10, count 0 2006.201.13:01:53.95#ibcon#about to read 5, iclass 10, count 0 2006.201.13:01:53.95#ibcon#read 5, iclass 10, count 0 2006.201.13:01:53.95#ibcon#about to read 6, iclass 10, count 0 2006.201.13:01:53.95#ibcon#read 6, iclass 10, count 0 2006.201.13:01:53.95#ibcon#end of sib2, iclass 10, count 0 2006.201.13:01:53.95#ibcon#*after write, iclass 10, count 0 2006.201.13:01:53.95#ibcon#*before return 0, iclass 10, count 0 2006.201.13:01:53.95#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:53.95#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:53.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.13:01:53.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.13:01:53.95$vck44/valo=7,864.99 2006.201.13:01:53.95#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.13:01:53.95#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.13:01:53.95#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:53.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:53.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:53.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:53.95#ibcon#enter wrdev, iclass 12, count 0 2006.201.13:01:53.95#ibcon#first serial, iclass 12, count 0 2006.201.13:01:53.95#ibcon#enter sib2, iclass 12, count 0 2006.201.13:01:53.95#ibcon#flushed, iclass 12, count 0 2006.201.13:01:53.95#ibcon#about to write, iclass 12, count 0 2006.201.13:01:53.95#ibcon#wrote, iclass 12, count 0 2006.201.13:01:53.95#ibcon#about to read 3, iclass 12, count 0 2006.201.13:01:53.97#ibcon#read 3, iclass 12, count 0 2006.201.13:01:53.97#ibcon#about to read 4, iclass 12, count 0 2006.201.13:01:53.97#ibcon#read 4, iclass 12, count 0 2006.201.13:01:53.97#ibcon#about to read 5, iclass 12, count 0 2006.201.13:01:53.97#ibcon#read 5, iclass 12, count 0 2006.201.13:01:53.97#ibcon#about to read 6, iclass 12, count 0 2006.201.13:01:53.97#ibcon#read 6, iclass 12, count 0 2006.201.13:01:53.97#ibcon#end of sib2, iclass 12, count 0 2006.201.13:01:53.97#ibcon#*mode == 0, iclass 12, count 0 2006.201.13:01:53.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.13:01:53.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:01:53.97#ibcon#*before write, iclass 12, count 0 2006.201.13:01:53.97#ibcon#enter sib2, iclass 12, count 0 2006.201.13:01:53.97#ibcon#flushed, iclass 12, count 0 2006.201.13:01:53.97#ibcon#about to write, iclass 12, count 0 2006.201.13:01:53.97#ibcon#wrote, iclass 12, count 0 2006.201.13:01:53.97#ibcon#about to read 3, iclass 12, count 0 2006.201.13:01:54.01#ibcon#read 3, iclass 12, count 0 2006.201.13:01:54.01#ibcon#about to read 4, iclass 12, count 0 2006.201.13:01:54.01#ibcon#read 4, iclass 12, count 0 2006.201.13:01:54.01#ibcon#about to read 5, iclass 12, count 0 2006.201.13:01:54.01#ibcon#read 5, iclass 12, count 0 2006.201.13:01:54.01#ibcon#about to read 6, iclass 12, count 0 2006.201.13:01:54.01#ibcon#read 6, iclass 12, count 0 2006.201.13:01:54.01#ibcon#end of sib2, iclass 12, count 0 2006.201.13:01:54.01#ibcon#*after write, iclass 12, count 0 2006.201.13:01:54.01#ibcon#*before return 0, iclass 12, count 0 2006.201.13:01:54.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:54.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:54.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.13:01:54.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.13:01:54.01$vck44/va=7,5 2006.201.13:01:54.01#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.13:01:54.01#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.13:01:54.01#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:54.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:54.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:54.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:54.07#ibcon#enter wrdev, iclass 14, count 2 2006.201.13:01:54.07#ibcon#first serial, iclass 14, count 2 2006.201.13:01:54.07#ibcon#enter sib2, iclass 14, count 2 2006.201.13:01:54.07#ibcon#flushed, iclass 14, count 2 2006.201.13:01:54.07#ibcon#about to write, iclass 14, count 2 2006.201.13:01:54.07#ibcon#wrote, iclass 14, count 2 2006.201.13:01:54.07#ibcon#about to read 3, iclass 14, count 2 2006.201.13:01:54.09#ibcon#read 3, iclass 14, count 2 2006.201.13:01:54.09#ibcon#about to read 4, iclass 14, count 2 2006.201.13:01:54.09#ibcon#read 4, iclass 14, count 2 2006.201.13:01:54.09#ibcon#about to read 5, iclass 14, count 2 2006.201.13:01:54.09#ibcon#read 5, iclass 14, count 2 2006.201.13:01:54.09#ibcon#about to read 6, iclass 14, count 2 2006.201.13:01:54.09#ibcon#read 6, iclass 14, count 2 2006.201.13:01:54.09#ibcon#end of sib2, iclass 14, count 2 2006.201.13:01:54.09#ibcon#*mode == 0, iclass 14, count 2 2006.201.13:01:54.09#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.13:01:54.09#ibcon#[25=AT07-05\r\n] 2006.201.13:01:54.09#ibcon#*before write, iclass 14, count 2 2006.201.13:01:54.09#ibcon#enter sib2, iclass 14, count 2 2006.201.13:01:54.09#ibcon#flushed, iclass 14, count 2 2006.201.13:01:54.09#ibcon#about to write, iclass 14, count 2 2006.201.13:01:54.09#ibcon#wrote, iclass 14, count 2 2006.201.13:01:54.09#ibcon#about to read 3, iclass 14, count 2 2006.201.13:01:54.12#ibcon#read 3, iclass 14, count 2 2006.201.13:01:54.12#ibcon#about to read 4, iclass 14, count 2 2006.201.13:01:54.12#ibcon#read 4, iclass 14, count 2 2006.201.13:01:54.12#ibcon#about to read 5, iclass 14, count 2 2006.201.13:01:54.12#ibcon#read 5, iclass 14, count 2 2006.201.13:01:54.12#ibcon#about to read 6, iclass 14, count 2 2006.201.13:01:54.12#ibcon#read 6, iclass 14, count 2 2006.201.13:01:54.12#ibcon#end of sib2, iclass 14, count 2 2006.201.13:01:54.12#ibcon#*after write, iclass 14, count 2 2006.201.13:01:54.12#ibcon#*before return 0, iclass 14, count 2 2006.201.13:01:54.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:54.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:54.12#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.13:01:54.12#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:54.12#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:54.24#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:54.24#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:54.24#ibcon#enter wrdev, iclass 14, count 0 2006.201.13:01:54.24#ibcon#first serial, iclass 14, count 0 2006.201.13:01:54.24#ibcon#enter sib2, iclass 14, count 0 2006.201.13:01:54.24#ibcon#flushed, iclass 14, count 0 2006.201.13:01:54.24#ibcon#about to write, iclass 14, count 0 2006.201.13:01:54.24#ibcon#wrote, iclass 14, count 0 2006.201.13:01:54.24#ibcon#about to read 3, iclass 14, count 0 2006.201.13:01:54.26#ibcon#read 3, iclass 14, count 0 2006.201.13:01:54.26#ibcon#about to read 4, iclass 14, count 0 2006.201.13:01:54.26#ibcon#read 4, iclass 14, count 0 2006.201.13:01:54.26#ibcon#about to read 5, iclass 14, count 0 2006.201.13:01:54.26#ibcon#read 5, iclass 14, count 0 2006.201.13:01:54.26#ibcon#about to read 6, iclass 14, count 0 2006.201.13:01:54.26#ibcon#read 6, iclass 14, count 0 2006.201.13:01:54.26#ibcon#end of sib2, iclass 14, count 0 2006.201.13:01:54.26#ibcon#*mode == 0, iclass 14, count 0 2006.201.13:01:54.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.13:01:54.26#ibcon#[25=USB\r\n] 2006.201.13:01:54.26#ibcon#*before write, iclass 14, count 0 2006.201.13:01:54.26#ibcon#enter sib2, iclass 14, count 0 2006.201.13:01:54.26#ibcon#flushed, iclass 14, count 0 2006.201.13:01:54.26#ibcon#about to write, iclass 14, count 0 2006.201.13:01:54.26#ibcon#wrote, iclass 14, count 0 2006.201.13:01:54.26#ibcon#about to read 3, iclass 14, count 0 2006.201.13:01:54.29#ibcon#read 3, iclass 14, count 0 2006.201.13:01:54.29#ibcon#about to read 4, iclass 14, count 0 2006.201.13:01:54.29#ibcon#read 4, iclass 14, count 0 2006.201.13:01:54.29#ibcon#about to read 5, iclass 14, count 0 2006.201.13:01:54.29#ibcon#read 5, iclass 14, count 0 2006.201.13:01:54.29#ibcon#about to read 6, iclass 14, count 0 2006.201.13:01:54.29#ibcon#read 6, iclass 14, count 0 2006.201.13:01:54.29#ibcon#end of sib2, iclass 14, count 0 2006.201.13:01:54.29#ibcon#*after write, iclass 14, count 0 2006.201.13:01:54.29#ibcon#*before return 0, iclass 14, count 0 2006.201.13:01:54.29#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:54.29#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:54.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.13:01:54.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.13:01:54.29$vck44/valo=8,884.99 2006.201.13:01:54.29#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.13:01:54.29#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.13:01:54.29#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:54.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:54.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:54.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:54.29#ibcon#enter wrdev, iclass 16, count 0 2006.201.13:01:54.29#ibcon#first serial, iclass 16, count 0 2006.201.13:01:54.29#ibcon#enter sib2, iclass 16, count 0 2006.201.13:01:54.29#ibcon#flushed, iclass 16, count 0 2006.201.13:01:54.29#ibcon#about to write, iclass 16, count 0 2006.201.13:01:54.29#ibcon#wrote, iclass 16, count 0 2006.201.13:01:54.29#ibcon#about to read 3, iclass 16, count 0 2006.201.13:01:54.31#ibcon#read 3, iclass 16, count 0 2006.201.13:01:54.31#ibcon#about to read 4, iclass 16, count 0 2006.201.13:01:54.31#ibcon#read 4, iclass 16, count 0 2006.201.13:01:54.31#ibcon#about to read 5, iclass 16, count 0 2006.201.13:01:54.31#ibcon#read 5, iclass 16, count 0 2006.201.13:01:54.31#ibcon#about to read 6, iclass 16, count 0 2006.201.13:01:54.31#ibcon#read 6, iclass 16, count 0 2006.201.13:01:54.31#ibcon#end of sib2, iclass 16, count 0 2006.201.13:01:54.31#ibcon#*mode == 0, iclass 16, count 0 2006.201.13:01:54.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.13:01:54.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:01:54.31#ibcon#*before write, iclass 16, count 0 2006.201.13:01:54.31#ibcon#enter sib2, iclass 16, count 0 2006.201.13:01:54.31#ibcon#flushed, iclass 16, count 0 2006.201.13:01:54.31#ibcon#about to write, iclass 16, count 0 2006.201.13:01:54.31#ibcon#wrote, iclass 16, count 0 2006.201.13:01:54.31#ibcon#about to read 3, iclass 16, count 0 2006.201.13:01:54.35#ibcon#read 3, iclass 16, count 0 2006.201.13:01:54.35#ibcon#about to read 4, iclass 16, count 0 2006.201.13:01:54.35#ibcon#read 4, iclass 16, count 0 2006.201.13:01:54.35#ibcon#about to read 5, iclass 16, count 0 2006.201.13:01:54.35#ibcon#read 5, iclass 16, count 0 2006.201.13:01:54.35#ibcon#about to read 6, iclass 16, count 0 2006.201.13:01:54.35#ibcon#read 6, iclass 16, count 0 2006.201.13:01:54.35#ibcon#end of sib2, iclass 16, count 0 2006.201.13:01:54.35#ibcon#*after write, iclass 16, count 0 2006.201.13:01:54.35#ibcon#*before return 0, iclass 16, count 0 2006.201.13:01:54.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:54.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:54.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.13:01:54.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.13:01:54.35$vck44/va=8,4 2006.201.13:01:54.35#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.13:01:54.35#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.13:01:54.35#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:54.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:01:54.41#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:01:54.41#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:01:54.41#ibcon#enter wrdev, iclass 18, count 2 2006.201.13:01:54.41#ibcon#first serial, iclass 18, count 2 2006.201.13:01:54.41#ibcon#enter sib2, iclass 18, count 2 2006.201.13:01:54.41#ibcon#flushed, iclass 18, count 2 2006.201.13:01:54.41#ibcon#about to write, iclass 18, count 2 2006.201.13:01:54.41#ibcon#wrote, iclass 18, count 2 2006.201.13:01:54.41#ibcon#about to read 3, iclass 18, count 2 2006.201.13:01:54.43#ibcon#read 3, iclass 18, count 2 2006.201.13:01:54.43#ibcon#about to read 4, iclass 18, count 2 2006.201.13:01:54.43#ibcon#read 4, iclass 18, count 2 2006.201.13:01:54.43#ibcon#about to read 5, iclass 18, count 2 2006.201.13:01:54.43#ibcon#read 5, iclass 18, count 2 2006.201.13:01:54.43#ibcon#about to read 6, iclass 18, count 2 2006.201.13:01:54.43#ibcon#read 6, iclass 18, count 2 2006.201.13:01:54.43#ibcon#end of sib2, iclass 18, count 2 2006.201.13:01:54.43#ibcon#*mode == 0, iclass 18, count 2 2006.201.13:01:54.43#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.13:01:54.43#ibcon#[25=AT08-04\r\n] 2006.201.13:01:54.43#ibcon#*before write, iclass 18, count 2 2006.201.13:01:54.43#ibcon#enter sib2, iclass 18, count 2 2006.201.13:01:54.43#ibcon#flushed, iclass 18, count 2 2006.201.13:01:54.43#ibcon#about to write, iclass 18, count 2 2006.201.13:01:54.43#ibcon#wrote, iclass 18, count 2 2006.201.13:01:54.43#ibcon#about to read 3, iclass 18, count 2 2006.201.13:01:54.46#ibcon#read 3, iclass 18, count 2 2006.201.13:01:54.46#ibcon#about to read 4, iclass 18, count 2 2006.201.13:01:54.46#ibcon#read 4, iclass 18, count 2 2006.201.13:01:54.46#ibcon#about to read 5, iclass 18, count 2 2006.201.13:01:54.46#ibcon#read 5, iclass 18, count 2 2006.201.13:01:54.46#ibcon#about to read 6, iclass 18, count 2 2006.201.13:01:54.46#ibcon#read 6, iclass 18, count 2 2006.201.13:01:54.46#ibcon#end of sib2, iclass 18, count 2 2006.201.13:01:54.46#ibcon#*after write, iclass 18, count 2 2006.201.13:01:54.46#ibcon#*before return 0, iclass 18, count 2 2006.201.13:01:54.46#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:01:54.46#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:01:54.46#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.13:01:54.46#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:54.46#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:01:54.58#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:01:54.58#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:01:54.58#ibcon#enter wrdev, iclass 18, count 0 2006.201.13:01:54.58#ibcon#first serial, iclass 18, count 0 2006.201.13:01:54.58#ibcon#enter sib2, iclass 18, count 0 2006.201.13:01:54.58#ibcon#flushed, iclass 18, count 0 2006.201.13:01:54.58#ibcon#about to write, iclass 18, count 0 2006.201.13:01:54.58#ibcon#wrote, iclass 18, count 0 2006.201.13:01:54.58#ibcon#about to read 3, iclass 18, count 0 2006.201.13:01:54.60#ibcon#read 3, iclass 18, count 0 2006.201.13:01:54.60#ibcon#about to read 4, iclass 18, count 0 2006.201.13:01:54.60#ibcon#read 4, iclass 18, count 0 2006.201.13:01:54.60#ibcon#about to read 5, iclass 18, count 0 2006.201.13:01:54.60#ibcon#read 5, iclass 18, count 0 2006.201.13:01:54.60#ibcon#about to read 6, iclass 18, count 0 2006.201.13:01:54.60#ibcon#read 6, iclass 18, count 0 2006.201.13:01:54.60#ibcon#end of sib2, iclass 18, count 0 2006.201.13:01:54.60#ibcon#*mode == 0, iclass 18, count 0 2006.201.13:01:54.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.13:01:54.60#ibcon#[25=USB\r\n] 2006.201.13:01:54.60#ibcon#*before write, iclass 18, count 0 2006.201.13:01:54.60#ibcon#enter sib2, iclass 18, count 0 2006.201.13:01:54.60#ibcon#flushed, iclass 18, count 0 2006.201.13:01:54.60#ibcon#about to write, iclass 18, count 0 2006.201.13:01:54.60#ibcon#wrote, iclass 18, count 0 2006.201.13:01:54.60#ibcon#about to read 3, iclass 18, count 0 2006.201.13:01:54.63#ibcon#read 3, iclass 18, count 0 2006.201.13:01:54.63#ibcon#about to read 4, iclass 18, count 0 2006.201.13:01:54.63#ibcon#read 4, iclass 18, count 0 2006.201.13:01:54.63#ibcon#about to read 5, iclass 18, count 0 2006.201.13:01:54.63#ibcon#read 5, iclass 18, count 0 2006.201.13:01:54.63#ibcon#about to read 6, iclass 18, count 0 2006.201.13:01:54.63#ibcon#read 6, iclass 18, count 0 2006.201.13:01:54.63#ibcon#end of sib2, iclass 18, count 0 2006.201.13:01:54.63#ibcon#*after write, iclass 18, count 0 2006.201.13:01:54.63#ibcon#*before return 0, iclass 18, count 0 2006.201.13:01:54.63#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:01:54.63#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:01:54.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.13:01:54.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.13:01:54.63$vck44/vblo=1,629.99 2006.201.13:01:54.63#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.13:01:54.63#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.13:01:54.63#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:54.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:01:54.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:01:54.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:01:54.63#ibcon#enter wrdev, iclass 20, count 0 2006.201.13:01:54.63#ibcon#first serial, iclass 20, count 0 2006.201.13:01:54.63#ibcon#enter sib2, iclass 20, count 0 2006.201.13:01:54.63#ibcon#flushed, iclass 20, count 0 2006.201.13:01:54.63#ibcon#about to write, iclass 20, count 0 2006.201.13:01:54.63#ibcon#wrote, iclass 20, count 0 2006.201.13:01:54.63#ibcon#about to read 3, iclass 20, count 0 2006.201.13:01:54.65#ibcon#read 3, iclass 20, count 0 2006.201.13:01:54.65#ibcon#about to read 4, iclass 20, count 0 2006.201.13:01:54.65#ibcon#read 4, iclass 20, count 0 2006.201.13:01:54.65#ibcon#about to read 5, iclass 20, count 0 2006.201.13:01:54.65#ibcon#read 5, iclass 20, count 0 2006.201.13:01:54.65#ibcon#about to read 6, iclass 20, count 0 2006.201.13:01:54.65#ibcon#read 6, iclass 20, count 0 2006.201.13:01:54.65#ibcon#end of sib2, iclass 20, count 0 2006.201.13:01:54.65#ibcon#*mode == 0, iclass 20, count 0 2006.201.13:01:54.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.13:01:54.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:01:54.65#ibcon#*before write, iclass 20, count 0 2006.201.13:01:54.65#ibcon#enter sib2, iclass 20, count 0 2006.201.13:01:54.65#ibcon#flushed, iclass 20, count 0 2006.201.13:01:54.65#ibcon#about to write, iclass 20, count 0 2006.201.13:01:54.65#ibcon#wrote, iclass 20, count 0 2006.201.13:01:54.65#ibcon#about to read 3, iclass 20, count 0 2006.201.13:01:54.70#ibcon#read 3, iclass 20, count 0 2006.201.13:01:54.70#ibcon#about to read 4, iclass 20, count 0 2006.201.13:01:54.70#ibcon#read 4, iclass 20, count 0 2006.201.13:01:54.70#ibcon#about to read 5, iclass 20, count 0 2006.201.13:01:54.70#ibcon#read 5, iclass 20, count 0 2006.201.13:01:54.70#ibcon#about to read 6, iclass 20, count 0 2006.201.13:01:54.70#ibcon#read 6, iclass 20, count 0 2006.201.13:01:54.70#ibcon#end of sib2, iclass 20, count 0 2006.201.13:01:54.70#ibcon#*after write, iclass 20, count 0 2006.201.13:01:54.70#ibcon#*before return 0, iclass 20, count 0 2006.201.13:01:54.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:01:54.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:01:54.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.13:01:54.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.13:01:54.70$vck44/vb=1,4 2006.201.13:01:54.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.13:01:54.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.13:01:54.70#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:54.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:01:54.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:01:54.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:01:54.70#ibcon#enter wrdev, iclass 22, count 2 2006.201.13:01:54.70#ibcon#first serial, iclass 22, count 2 2006.201.13:01:54.70#ibcon#enter sib2, iclass 22, count 2 2006.201.13:01:54.70#ibcon#flushed, iclass 22, count 2 2006.201.13:01:54.70#ibcon#about to write, iclass 22, count 2 2006.201.13:01:54.70#ibcon#wrote, iclass 22, count 2 2006.201.13:01:54.70#ibcon#about to read 3, iclass 22, count 2 2006.201.13:01:54.72#ibcon#read 3, iclass 22, count 2 2006.201.13:01:54.72#ibcon#about to read 4, iclass 22, count 2 2006.201.13:01:54.72#ibcon#read 4, iclass 22, count 2 2006.201.13:01:54.72#ibcon#about to read 5, iclass 22, count 2 2006.201.13:01:54.72#ibcon#read 5, iclass 22, count 2 2006.201.13:01:54.72#ibcon#about to read 6, iclass 22, count 2 2006.201.13:01:54.72#ibcon#read 6, iclass 22, count 2 2006.201.13:01:54.72#ibcon#end of sib2, iclass 22, count 2 2006.201.13:01:54.72#ibcon#*mode == 0, iclass 22, count 2 2006.201.13:01:54.72#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.13:01:54.72#ibcon#[27=AT01-04\r\n] 2006.201.13:01:54.72#ibcon#*before write, iclass 22, count 2 2006.201.13:01:54.72#ibcon#enter sib2, iclass 22, count 2 2006.201.13:01:54.72#ibcon#flushed, iclass 22, count 2 2006.201.13:01:54.72#ibcon#about to write, iclass 22, count 2 2006.201.13:01:54.72#ibcon#wrote, iclass 22, count 2 2006.201.13:01:54.72#ibcon#about to read 3, iclass 22, count 2 2006.201.13:01:54.75#ibcon#read 3, iclass 22, count 2 2006.201.13:01:54.75#ibcon#about to read 4, iclass 22, count 2 2006.201.13:01:54.75#ibcon#read 4, iclass 22, count 2 2006.201.13:01:54.75#ibcon#about to read 5, iclass 22, count 2 2006.201.13:01:54.75#ibcon#read 5, iclass 22, count 2 2006.201.13:01:54.75#ibcon#about to read 6, iclass 22, count 2 2006.201.13:01:54.75#ibcon#read 6, iclass 22, count 2 2006.201.13:01:54.75#ibcon#end of sib2, iclass 22, count 2 2006.201.13:01:54.75#ibcon#*after write, iclass 22, count 2 2006.201.13:01:54.75#ibcon#*before return 0, iclass 22, count 2 2006.201.13:01:54.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:01:54.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:01:54.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.13:01:54.75#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:54.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:01:54.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:01:54.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:01:54.87#ibcon#enter wrdev, iclass 22, count 0 2006.201.13:01:54.87#ibcon#first serial, iclass 22, count 0 2006.201.13:01:54.87#ibcon#enter sib2, iclass 22, count 0 2006.201.13:01:54.87#ibcon#flushed, iclass 22, count 0 2006.201.13:01:54.87#ibcon#about to write, iclass 22, count 0 2006.201.13:01:54.87#ibcon#wrote, iclass 22, count 0 2006.201.13:01:54.87#ibcon#about to read 3, iclass 22, count 0 2006.201.13:01:54.89#ibcon#read 3, iclass 22, count 0 2006.201.13:01:54.89#ibcon#about to read 4, iclass 22, count 0 2006.201.13:01:54.89#ibcon#read 4, iclass 22, count 0 2006.201.13:01:54.89#ibcon#about to read 5, iclass 22, count 0 2006.201.13:01:54.89#ibcon#read 5, iclass 22, count 0 2006.201.13:01:54.89#ibcon#about to read 6, iclass 22, count 0 2006.201.13:01:54.89#ibcon#read 6, iclass 22, count 0 2006.201.13:01:54.89#ibcon#end of sib2, iclass 22, count 0 2006.201.13:01:54.89#ibcon#*mode == 0, iclass 22, count 0 2006.201.13:01:54.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.13:01:54.89#ibcon#[27=USB\r\n] 2006.201.13:01:54.89#ibcon#*before write, iclass 22, count 0 2006.201.13:01:54.89#ibcon#enter sib2, iclass 22, count 0 2006.201.13:01:54.89#ibcon#flushed, iclass 22, count 0 2006.201.13:01:54.89#ibcon#about to write, iclass 22, count 0 2006.201.13:01:54.89#ibcon#wrote, iclass 22, count 0 2006.201.13:01:54.89#ibcon#about to read 3, iclass 22, count 0 2006.201.13:01:54.92#ibcon#read 3, iclass 22, count 0 2006.201.13:01:54.92#ibcon#about to read 4, iclass 22, count 0 2006.201.13:01:54.92#ibcon#read 4, iclass 22, count 0 2006.201.13:01:54.92#ibcon#about to read 5, iclass 22, count 0 2006.201.13:01:54.92#ibcon#read 5, iclass 22, count 0 2006.201.13:01:54.92#ibcon#about to read 6, iclass 22, count 0 2006.201.13:01:54.92#ibcon#read 6, iclass 22, count 0 2006.201.13:01:54.92#ibcon#end of sib2, iclass 22, count 0 2006.201.13:01:54.92#ibcon#*after write, iclass 22, count 0 2006.201.13:01:54.92#ibcon#*before return 0, iclass 22, count 0 2006.201.13:01:54.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:01:54.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:01:54.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.13:01:54.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.13:01:54.92$vck44/vblo=2,634.99 2006.201.13:01:54.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.13:01:54.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.13:01:54.92#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:54.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:54.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:54.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:54.92#ibcon#enter wrdev, iclass 24, count 0 2006.201.13:01:54.92#ibcon#first serial, iclass 24, count 0 2006.201.13:01:54.92#ibcon#enter sib2, iclass 24, count 0 2006.201.13:01:54.92#ibcon#flushed, iclass 24, count 0 2006.201.13:01:54.92#ibcon#about to write, iclass 24, count 0 2006.201.13:01:54.92#ibcon#wrote, iclass 24, count 0 2006.201.13:01:54.92#ibcon#about to read 3, iclass 24, count 0 2006.201.13:01:54.94#ibcon#read 3, iclass 24, count 0 2006.201.13:01:54.94#ibcon#about to read 4, iclass 24, count 0 2006.201.13:01:54.94#ibcon#read 4, iclass 24, count 0 2006.201.13:01:54.94#ibcon#about to read 5, iclass 24, count 0 2006.201.13:01:54.94#ibcon#read 5, iclass 24, count 0 2006.201.13:01:54.94#ibcon#about to read 6, iclass 24, count 0 2006.201.13:01:54.94#ibcon#read 6, iclass 24, count 0 2006.201.13:01:54.94#ibcon#end of sib2, iclass 24, count 0 2006.201.13:01:54.94#ibcon#*mode == 0, iclass 24, count 0 2006.201.13:01:54.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.13:01:54.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:01:54.94#ibcon#*before write, iclass 24, count 0 2006.201.13:01:54.94#ibcon#enter sib2, iclass 24, count 0 2006.201.13:01:54.94#ibcon#flushed, iclass 24, count 0 2006.201.13:01:54.94#ibcon#about to write, iclass 24, count 0 2006.201.13:01:54.94#ibcon#wrote, iclass 24, count 0 2006.201.13:01:54.94#ibcon#about to read 3, iclass 24, count 0 2006.201.13:01:54.98#ibcon#read 3, iclass 24, count 0 2006.201.13:01:54.98#ibcon#about to read 4, iclass 24, count 0 2006.201.13:01:54.98#ibcon#read 4, iclass 24, count 0 2006.201.13:01:54.98#ibcon#about to read 5, iclass 24, count 0 2006.201.13:01:54.98#ibcon#read 5, iclass 24, count 0 2006.201.13:01:54.98#ibcon#about to read 6, iclass 24, count 0 2006.201.13:01:54.98#ibcon#read 6, iclass 24, count 0 2006.201.13:01:54.98#ibcon#end of sib2, iclass 24, count 0 2006.201.13:01:54.98#ibcon#*after write, iclass 24, count 0 2006.201.13:01:54.98#ibcon#*before return 0, iclass 24, count 0 2006.201.13:01:54.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:54.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:01:54.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.13:01:54.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.13:01:54.98$vck44/vb=2,5 2006.201.13:01:54.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.13:01:54.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.13:01:54.98#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:54.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:55.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:55.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:55.04#ibcon#enter wrdev, iclass 26, count 2 2006.201.13:01:55.04#ibcon#first serial, iclass 26, count 2 2006.201.13:01:55.04#ibcon#enter sib2, iclass 26, count 2 2006.201.13:01:55.04#ibcon#flushed, iclass 26, count 2 2006.201.13:01:55.04#ibcon#about to write, iclass 26, count 2 2006.201.13:01:55.04#ibcon#wrote, iclass 26, count 2 2006.201.13:01:55.04#ibcon#about to read 3, iclass 26, count 2 2006.201.13:01:55.06#ibcon#read 3, iclass 26, count 2 2006.201.13:01:55.06#ibcon#about to read 4, iclass 26, count 2 2006.201.13:01:55.06#ibcon#read 4, iclass 26, count 2 2006.201.13:01:55.06#ibcon#about to read 5, iclass 26, count 2 2006.201.13:01:55.06#ibcon#read 5, iclass 26, count 2 2006.201.13:01:55.06#ibcon#about to read 6, iclass 26, count 2 2006.201.13:01:55.06#ibcon#read 6, iclass 26, count 2 2006.201.13:01:55.06#ibcon#end of sib2, iclass 26, count 2 2006.201.13:01:55.06#ibcon#*mode == 0, iclass 26, count 2 2006.201.13:01:55.06#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.13:01:55.06#ibcon#[27=AT02-05\r\n] 2006.201.13:01:55.06#ibcon#*before write, iclass 26, count 2 2006.201.13:01:55.06#ibcon#enter sib2, iclass 26, count 2 2006.201.13:01:55.06#ibcon#flushed, iclass 26, count 2 2006.201.13:01:55.06#ibcon#about to write, iclass 26, count 2 2006.201.13:01:55.06#ibcon#wrote, iclass 26, count 2 2006.201.13:01:55.06#ibcon#about to read 3, iclass 26, count 2 2006.201.13:01:55.09#ibcon#read 3, iclass 26, count 2 2006.201.13:01:55.09#ibcon#about to read 4, iclass 26, count 2 2006.201.13:01:55.09#ibcon#read 4, iclass 26, count 2 2006.201.13:01:55.09#ibcon#about to read 5, iclass 26, count 2 2006.201.13:01:55.09#ibcon#read 5, iclass 26, count 2 2006.201.13:01:55.09#ibcon#about to read 6, iclass 26, count 2 2006.201.13:01:55.09#ibcon#read 6, iclass 26, count 2 2006.201.13:01:55.09#ibcon#end of sib2, iclass 26, count 2 2006.201.13:01:55.09#ibcon#*after write, iclass 26, count 2 2006.201.13:01:55.09#ibcon#*before return 0, iclass 26, count 2 2006.201.13:01:55.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:55.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:01:55.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.13:01:55.09#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:55.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:55.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:55.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:55.21#ibcon#enter wrdev, iclass 26, count 0 2006.201.13:01:55.21#ibcon#first serial, iclass 26, count 0 2006.201.13:01:55.21#ibcon#enter sib2, iclass 26, count 0 2006.201.13:01:55.21#ibcon#flushed, iclass 26, count 0 2006.201.13:01:55.21#ibcon#about to write, iclass 26, count 0 2006.201.13:01:55.21#ibcon#wrote, iclass 26, count 0 2006.201.13:01:55.21#ibcon#about to read 3, iclass 26, count 0 2006.201.13:01:55.23#ibcon#read 3, iclass 26, count 0 2006.201.13:01:55.23#ibcon#about to read 4, iclass 26, count 0 2006.201.13:01:55.23#ibcon#read 4, iclass 26, count 0 2006.201.13:01:55.23#ibcon#about to read 5, iclass 26, count 0 2006.201.13:01:55.23#ibcon#read 5, iclass 26, count 0 2006.201.13:01:55.23#ibcon#about to read 6, iclass 26, count 0 2006.201.13:01:55.23#ibcon#read 6, iclass 26, count 0 2006.201.13:01:55.23#ibcon#end of sib2, iclass 26, count 0 2006.201.13:01:55.23#ibcon#*mode == 0, iclass 26, count 0 2006.201.13:01:55.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.13:01:55.23#ibcon#[27=USB\r\n] 2006.201.13:01:55.23#ibcon#*before write, iclass 26, count 0 2006.201.13:01:55.23#ibcon#enter sib2, iclass 26, count 0 2006.201.13:01:55.23#ibcon#flushed, iclass 26, count 0 2006.201.13:01:55.23#ibcon#about to write, iclass 26, count 0 2006.201.13:01:55.23#ibcon#wrote, iclass 26, count 0 2006.201.13:01:55.23#ibcon#about to read 3, iclass 26, count 0 2006.201.13:01:55.26#ibcon#read 3, iclass 26, count 0 2006.201.13:01:55.26#ibcon#about to read 4, iclass 26, count 0 2006.201.13:01:55.26#ibcon#read 4, iclass 26, count 0 2006.201.13:01:55.26#ibcon#about to read 5, iclass 26, count 0 2006.201.13:01:55.26#ibcon#read 5, iclass 26, count 0 2006.201.13:01:55.26#ibcon#about to read 6, iclass 26, count 0 2006.201.13:01:55.26#ibcon#read 6, iclass 26, count 0 2006.201.13:01:55.26#ibcon#end of sib2, iclass 26, count 0 2006.201.13:01:55.26#ibcon#*after write, iclass 26, count 0 2006.201.13:01:55.26#ibcon#*before return 0, iclass 26, count 0 2006.201.13:01:55.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:55.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:01:55.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.13:01:55.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.13:01:55.26$vck44/vblo=3,649.99 2006.201.13:01:55.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.13:01:55.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.13:01:55.26#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:55.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:55.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:55.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:55.26#ibcon#enter wrdev, iclass 28, count 0 2006.201.13:01:55.26#ibcon#first serial, iclass 28, count 0 2006.201.13:01:55.26#ibcon#enter sib2, iclass 28, count 0 2006.201.13:01:55.26#ibcon#flushed, iclass 28, count 0 2006.201.13:01:55.26#ibcon#about to write, iclass 28, count 0 2006.201.13:01:55.26#ibcon#wrote, iclass 28, count 0 2006.201.13:01:55.26#ibcon#about to read 3, iclass 28, count 0 2006.201.13:01:55.28#ibcon#read 3, iclass 28, count 0 2006.201.13:01:55.28#ibcon#about to read 4, iclass 28, count 0 2006.201.13:01:55.28#ibcon#read 4, iclass 28, count 0 2006.201.13:01:55.28#ibcon#about to read 5, iclass 28, count 0 2006.201.13:01:55.28#ibcon#read 5, iclass 28, count 0 2006.201.13:01:55.28#ibcon#about to read 6, iclass 28, count 0 2006.201.13:01:55.28#ibcon#read 6, iclass 28, count 0 2006.201.13:01:55.28#ibcon#end of sib2, iclass 28, count 0 2006.201.13:01:55.28#ibcon#*mode == 0, iclass 28, count 0 2006.201.13:01:55.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.13:01:55.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:01:55.28#ibcon#*before write, iclass 28, count 0 2006.201.13:01:55.28#ibcon#enter sib2, iclass 28, count 0 2006.201.13:01:55.28#ibcon#flushed, iclass 28, count 0 2006.201.13:01:55.28#ibcon#about to write, iclass 28, count 0 2006.201.13:01:55.28#ibcon#wrote, iclass 28, count 0 2006.201.13:01:55.28#ibcon#about to read 3, iclass 28, count 0 2006.201.13:01:55.33#ibcon#read 3, iclass 28, count 0 2006.201.13:01:55.33#ibcon#about to read 4, iclass 28, count 0 2006.201.13:01:55.33#ibcon#read 4, iclass 28, count 0 2006.201.13:01:55.33#ibcon#about to read 5, iclass 28, count 0 2006.201.13:01:55.33#ibcon#read 5, iclass 28, count 0 2006.201.13:01:55.33#ibcon#about to read 6, iclass 28, count 0 2006.201.13:01:55.33#ibcon#read 6, iclass 28, count 0 2006.201.13:01:55.33#ibcon#end of sib2, iclass 28, count 0 2006.201.13:01:55.33#ibcon#*after write, iclass 28, count 0 2006.201.13:01:55.33#ibcon#*before return 0, iclass 28, count 0 2006.201.13:01:55.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:55.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:01:55.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.13:01:55.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.13:01:55.33$vck44/vb=3,4 2006.201.13:01:55.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.13:01:55.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.13:01:55.33#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:55.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:55.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:55.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:55.38#ibcon#enter wrdev, iclass 30, count 2 2006.201.13:01:55.38#ibcon#first serial, iclass 30, count 2 2006.201.13:01:55.38#ibcon#enter sib2, iclass 30, count 2 2006.201.13:01:55.38#ibcon#flushed, iclass 30, count 2 2006.201.13:01:55.38#ibcon#about to write, iclass 30, count 2 2006.201.13:01:55.38#ibcon#wrote, iclass 30, count 2 2006.201.13:01:55.38#ibcon#about to read 3, iclass 30, count 2 2006.201.13:01:55.40#ibcon#read 3, iclass 30, count 2 2006.201.13:01:55.40#ibcon#about to read 4, iclass 30, count 2 2006.201.13:01:55.40#ibcon#read 4, iclass 30, count 2 2006.201.13:01:55.40#ibcon#about to read 5, iclass 30, count 2 2006.201.13:01:55.40#ibcon#read 5, iclass 30, count 2 2006.201.13:01:55.40#ibcon#about to read 6, iclass 30, count 2 2006.201.13:01:55.40#ibcon#read 6, iclass 30, count 2 2006.201.13:01:55.40#ibcon#end of sib2, iclass 30, count 2 2006.201.13:01:55.40#ibcon#*mode == 0, iclass 30, count 2 2006.201.13:01:55.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.13:01:55.40#ibcon#[27=AT03-04\r\n] 2006.201.13:01:55.40#ibcon#*before write, iclass 30, count 2 2006.201.13:01:55.40#ibcon#enter sib2, iclass 30, count 2 2006.201.13:01:55.40#ibcon#flushed, iclass 30, count 2 2006.201.13:01:55.40#ibcon#about to write, iclass 30, count 2 2006.201.13:01:55.40#ibcon#wrote, iclass 30, count 2 2006.201.13:01:55.40#ibcon#about to read 3, iclass 30, count 2 2006.201.13:01:55.43#ibcon#read 3, iclass 30, count 2 2006.201.13:01:55.43#ibcon#about to read 4, iclass 30, count 2 2006.201.13:01:55.43#ibcon#read 4, iclass 30, count 2 2006.201.13:01:55.43#ibcon#about to read 5, iclass 30, count 2 2006.201.13:01:55.43#ibcon#read 5, iclass 30, count 2 2006.201.13:01:55.43#ibcon#about to read 6, iclass 30, count 2 2006.201.13:01:55.43#ibcon#read 6, iclass 30, count 2 2006.201.13:01:55.43#ibcon#end of sib2, iclass 30, count 2 2006.201.13:01:55.43#ibcon#*after write, iclass 30, count 2 2006.201.13:01:55.43#ibcon#*before return 0, iclass 30, count 2 2006.201.13:01:55.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:55.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:01:55.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.13:01:55.43#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:55.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:55.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:55.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:55.55#ibcon#enter wrdev, iclass 30, count 0 2006.201.13:01:55.55#ibcon#first serial, iclass 30, count 0 2006.201.13:01:55.55#ibcon#enter sib2, iclass 30, count 0 2006.201.13:01:55.55#ibcon#flushed, iclass 30, count 0 2006.201.13:01:55.55#ibcon#about to write, iclass 30, count 0 2006.201.13:01:55.55#ibcon#wrote, iclass 30, count 0 2006.201.13:01:55.55#ibcon#about to read 3, iclass 30, count 0 2006.201.13:01:55.57#ibcon#read 3, iclass 30, count 0 2006.201.13:01:55.57#ibcon#about to read 4, iclass 30, count 0 2006.201.13:01:55.57#ibcon#read 4, iclass 30, count 0 2006.201.13:01:55.57#ibcon#about to read 5, iclass 30, count 0 2006.201.13:01:55.57#ibcon#read 5, iclass 30, count 0 2006.201.13:01:55.57#ibcon#about to read 6, iclass 30, count 0 2006.201.13:01:55.57#ibcon#read 6, iclass 30, count 0 2006.201.13:01:55.57#ibcon#end of sib2, iclass 30, count 0 2006.201.13:01:55.57#ibcon#*mode == 0, iclass 30, count 0 2006.201.13:01:55.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.13:01:55.57#ibcon#[27=USB\r\n] 2006.201.13:01:55.57#ibcon#*before write, iclass 30, count 0 2006.201.13:01:55.57#ibcon#enter sib2, iclass 30, count 0 2006.201.13:01:55.57#ibcon#flushed, iclass 30, count 0 2006.201.13:01:55.57#ibcon#about to write, iclass 30, count 0 2006.201.13:01:55.57#ibcon#wrote, iclass 30, count 0 2006.201.13:01:55.57#ibcon#about to read 3, iclass 30, count 0 2006.201.13:01:55.60#ibcon#read 3, iclass 30, count 0 2006.201.13:01:55.60#ibcon#about to read 4, iclass 30, count 0 2006.201.13:01:55.60#ibcon#read 4, iclass 30, count 0 2006.201.13:01:55.60#ibcon#about to read 5, iclass 30, count 0 2006.201.13:01:55.60#ibcon#read 5, iclass 30, count 0 2006.201.13:01:55.60#ibcon#about to read 6, iclass 30, count 0 2006.201.13:01:55.60#ibcon#read 6, iclass 30, count 0 2006.201.13:01:55.60#ibcon#end of sib2, iclass 30, count 0 2006.201.13:01:55.60#ibcon#*after write, iclass 30, count 0 2006.201.13:01:55.60#ibcon#*before return 0, iclass 30, count 0 2006.201.13:01:55.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:55.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:01:55.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.13:01:55.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.13:01:55.60$vck44/vblo=4,679.99 2006.201.13:01:55.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.13:01:55.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.13:01:55.60#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:55.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:55.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:55.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:55.60#ibcon#enter wrdev, iclass 32, count 0 2006.201.13:01:55.60#ibcon#first serial, iclass 32, count 0 2006.201.13:01:55.60#ibcon#enter sib2, iclass 32, count 0 2006.201.13:01:55.60#ibcon#flushed, iclass 32, count 0 2006.201.13:01:55.60#ibcon#about to write, iclass 32, count 0 2006.201.13:01:55.60#ibcon#wrote, iclass 32, count 0 2006.201.13:01:55.60#ibcon#about to read 3, iclass 32, count 0 2006.201.13:01:55.62#ibcon#read 3, iclass 32, count 0 2006.201.13:01:55.62#ibcon#about to read 4, iclass 32, count 0 2006.201.13:01:55.62#ibcon#read 4, iclass 32, count 0 2006.201.13:01:55.62#ibcon#about to read 5, iclass 32, count 0 2006.201.13:01:55.62#ibcon#read 5, iclass 32, count 0 2006.201.13:01:55.62#ibcon#about to read 6, iclass 32, count 0 2006.201.13:01:55.62#ibcon#read 6, iclass 32, count 0 2006.201.13:01:55.62#ibcon#end of sib2, iclass 32, count 0 2006.201.13:01:55.62#ibcon#*mode == 0, iclass 32, count 0 2006.201.13:01:55.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.13:01:55.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:01:55.62#ibcon#*before write, iclass 32, count 0 2006.201.13:01:55.62#ibcon#enter sib2, iclass 32, count 0 2006.201.13:01:55.62#ibcon#flushed, iclass 32, count 0 2006.201.13:01:55.62#ibcon#about to write, iclass 32, count 0 2006.201.13:01:55.62#ibcon#wrote, iclass 32, count 0 2006.201.13:01:55.62#ibcon#about to read 3, iclass 32, count 0 2006.201.13:01:55.66#ibcon#read 3, iclass 32, count 0 2006.201.13:01:55.66#ibcon#about to read 4, iclass 32, count 0 2006.201.13:01:55.66#ibcon#read 4, iclass 32, count 0 2006.201.13:01:55.66#ibcon#about to read 5, iclass 32, count 0 2006.201.13:01:55.66#ibcon#read 5, iclass 32, count 0 2006.201.13:01:55.66#ibcon#about to read 6, iclass 32, count 0 2006.201.13:01:55.66#ibcon#read 6, iclass 32, count 0 2006.201.13:01:55.66#ibcon#end of sib2, iclass 32, count 0 2006.201.13:01:55.66#ibcon#*after write, iclass 32, count 0 2006.201.13:01:55.66#ibcon#*before return 0, iclass 32, count 0 2006.201.13:01:55.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:55.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:01:55.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.13:01:55.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.13:01:55.66$vck44/vb=4,5 2006.201.13:01:55.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.13:01:55.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.13:01:55.66#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:55.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:55.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:55.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:55.72#ibcon#enter wrdev, iclass 34, count 2 2006.201.13:01:55.72#ibcon#first serial, iclass 34, count 2 2006.201.13:01:55.72#ibcon#enter sib2, iclass 34, count 2 2006.201.13:01:55.72#ibcon#flushed, iclass 34, count 2 2006.201.13:01:55.72#ibcon#about to write, iclass 34, count 2 2006.201.13:01:55.72#ibcon#wrote, iclass 34, count 2 2006.201.13:01:55.72#ibcon#about to read 3, iclass 34, count 2 2006.201.13:01:55.74#ibcon#read 3, iclass 34, count 2 2006.201.13:01:55.74#ibcon#about to read 4, iclass 34, count 2 2006.201.13:01:55.74#ibcon#read 4, iclass 34, count 2 2006.201.13:01:55.74#ibcon#about to read 5, iclass 34, count 2 2006.201.13:01:55.74#ibcon#read 5, iclass 34, count 2 2006.201.13:01:55.74#ibcon#about to read 6, iclass 34, count 2 2006.201.13:01:55.74#ibcon#read 6, iclass 34, count 2 2006.201.13:01:55.74#ibcon#end of sib2, iclass 34, count 2 2006.201.13:01:55.74#ibcon#*mode == 0, iclass 34, count 2 2006.201.13:01:55.74#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.13:01:55.74#ibcon#[27=AT04-05\r\n] 2006.201.13:01:55.74#ibcon#*before write, iclass 34, count 2 2006.201.13:01:55.74#ibcon#enter sib2, iclass 34, count 2 2006.201.13:01:55.74#ibcon#flushed, iclass 34, count 2 2006.201.13:01:55.74#ibcon#about to write, iclass 34, count 2 2006.201.13:01:55.74#ibcon#wrote, iclass 34, count 2 2006.201.13:01:55.74#ibcon#about to read 3, iclass 34, count 2 2006.201.13:01:55.77#ibcon#read 3, iclass 34, count 2 2006.201.13:01:55.77#ibcon#about to read 4, iclass 34, count 2 2006.201.13:01:55.77#ibcon#read 4, iclass 34, count 2 2006.201.13:01:55.77#ibcon#about to read 5, iclass 34, count 2 2006.201.13:01:55.77#ibcon#read 5, iclass 34, count 2 2006.201.13:01:55.77#ibcon#about to read 6, iclass 34, count 2 2006.201.13:01:55.77#ibcon#read 6, iclass 34, count 2 2006.201.13:01:55.77#ibcon#end of sib2, iclass 34, count 2 2006.201.13:01:55.77#ibcon#*after write, iclass 34, count 2 2006.201.13:01:55.77#ibcon#*before return 0, iclass 34, count 2 2006.201.13:01:55.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:55.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:01:55.77#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.13:01:55.77#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:55.77#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:55.89#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:55.89#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:55.89#ibcon#enter wrdev, iclass 34, count 0 2006.201.13:01:55.89#ibcon#first serial, iclass 34, count 0 2006.201.13:01:55.89#ibcon#enter sib2, iclass 34, count 0 2006.201.13:01:55.89#ibcon#flushed, iclass 34, count 0 2006.201.13:01:55.89#ibcon#about to write, iclass 34, count 0 2006.201.13:01:55.89#ibcon#wrote, iclass 34, count 0 2006.201.13:01:55.89#ibcon#about to read 3, iclass 34, count 0 2006.201.13:01:55.91#ibcon#read 3, iclass 34, count 0 2006.201.13:01:55.91#ibcon#about to read 4, iclass 34, count 0 2006.201.13:01:55.91#ibcon#read 4, iclass 34, count 0 2006.201.13:01:55.91#ibcon#about to read 5, iclass 34, count 0 2006.201.13:01:55.91#ibcon#read 5, iclass 34, count 0 2006.201.13:01:55.91#ibcon#about to read 6, iclass 34, count 0 2006.201.13:01:55.91#ibcon#read 6, iclass 34, count 0 2006.201.13:01:55.91#ibcon#end of sib2, iclass 34, count 0 2006.201.13:01:55.91#ibcon#*mode == 0, iclass 34, count 0 2006.201.13:01:55.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.13:01:55.91#ibcon#[27=USB\r\n] 2006.201.13:01:55.91#ibcon#*before write, iclass 34, count 0 2006.201.13:01:55.91#ibcon#enter sib2, iclass 34, count 0 2006.201.13:01:55.91#ibcon#flushed, iclass 34, count 0 2006.201.13:01:55.91#ibcon#about to write, iclass 34, count 0 2006.201.13:01:55.91#ibcon#wrote, iclass 34, count 0 2006.201.13:01:55.91#ibcon#about to read 3, iclass 34, count 0 2006.201.13:01:55.94#ibcon#read 3, iclass 34, count 0 2006.201.13:01:55.94#ibcon#about to read 4, iclass 34, count 0 2006.201.13:01:55.94#ibcon#read 4, iclass 34, count 0 2006.201.13:01:55.94#ibcon#about to read 5, iclass 34, count 0 2006.201.13:01:55.94#ibcon#read 5, iclass 34, count 0 2006.201.13:01:55.94#ibcon#about to read 6, iclass 34, count 0 2006.201.13:01:55.94#ibcon#read 6, iclass 34, count 0 2006.201.13:01:55.94#ibcon#end of sib2, iclass 34, count 0 2006.201.13:01:55.94#ibcon#*after write, iclass 34, count 0 2006.201.13:01:55.94#ibcon#*before return 0, iclass 34, count 0 2006.201.13:01:55.94#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:55.94#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:01:55.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.13:01:55.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.13:01:55.94$vck44/vblo=5,709.99 2006.201.13:01:55.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.13:01:55.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.13:01:55.94#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:55.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:55.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:55.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:55.94#ibcon#enter wrdev, iclass 36, count 0 2006.201.13:01:55.94#ibcon#first serial, iclass 36, count 0 2006.201.13:01:55.94#ibcon#enter sib2, iclass 36, count 0 2006.201.13:01:55.94#ibcon#flushed, iclass 36, count 0 2006.201.13:01:55.94#ibcon#about to write, iclass 36, count 0 2006.201.13:01:55.94#ibcon#wrote, iclass 36, count 0 2006.201.13:01:55.94#ibcon#about to read 3, iclass 36, count 0 2006.201.13:01:55.96#ibcon#read 3, iclass 36, count 0 2006.201.13:01:55.96#ibcon#about to read 4, iclass 36, count 0 2006.201.13:01:55.96#ibcon#read 4, iclass 36, count 0 2006.201.13:01:55.96#ibcon#about to read 5, iclass 36, count 0 2006.201.13:01:55.96#ibcon#read 5, iclass 36, count 0 2006.201.13:01:55.96#ibcon#about to read 6, iclass 36, count 0 2006.201.13:01:55.96#ibcon#read 6, iclass 36, count 0 2006.201.13:01:55.96#ibcon#end of sib2, iclass 36, count 0 2006.201.13:01:55.96#ibcon#*mode == 0, iclass 36, count 0 2006.201.13:01:55.96#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.13:01:55.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:01:55.96#ibcon#*before write, iclass 36, count 0 2006.201.13:01:55.96#ibcon#enter sib2, iclass 36, count 0 2006.201.13:01:55.96#ibcon#flushed, iclass 36, count 0 2006.201.13:01:55.96#ibcon#about to write, iclass 36, count 0 2006.201.13:01:55.96#ibcon#wrote, iclass 36, count 0 2006.201.13:01:55.96#ibcon#about to read 3, iclass 36, count 0 2006.201.13:01:56.00#ibcon#read 3, iclass 36, count 0 2006.201.13:01:56.00#ibcon#about to read 4, iclass 36, count 0 2006.201.13:01:56.00#ibcon#read 4, iclass 36, count 0 2006.201.13:01:56.00#ibcon#about to read 5, iclass 36, count 0 2006.201.13:01:56.00#ibcon#read 5, iclass 36, count 0 2006.201.13:01:56.00#ibcon#about to read 6, iclass 36, count 0 2006.201.13:01:56.00#ibcon#read 6, iclass 36, count 0 2006.201.13:01:56.00#ibcon#end of sib2, iclass 36, count 0 2006.201.13:01:56.00#ibcon#*after write, iclass 36, count 0 2006.201.13:01:56.00#ibcon#*before return 0, iclass 36, count 0 2006.201.13:01:56.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:56.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:01:56.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.13:01:56.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.13:01:56.00$vck44/vb=5,4 2006.201.13:01:56.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.13:01:56.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.13:01:56.00#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:56.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:56.06#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:56.06#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:56.06#ibcon#enter wrdev, iclass 38, count 2 2006.201.13:01:56.06#ibcon#first serial, iclass 38, count 2 2006.201.13:01:56.06#ibcon#enter sib2, iclass 38, count 2 2006.201.13:01:56.06#ibcon#flushed, iclass 38, count 2 2006.201.13:01:56.06#ibcon#about to write, iclass 38, count 2 2006.201.13:01:56.06#ibcon#wrote, iclass 38, count 2 2006.201.13:01:56.06#ibcon#about to read 3, iclass 38, count 2 2006.201.13:01:56.08#ibcon#read 3, iclass 38, count 2 2006.201.13:01:56.08#ibcon#about to read 4, iclass 38, count 2 2006.201.13:01:56.08#ibcon#read 4, iclass 38, count 2 2006.201.13:01:56.08#ibcon#about to read 5, iclass 38, count 2 2006.201.13:01:56.08#ibcon#read 5, iclass 38, count 2 2006.201.13:01:56.08#ibcon#about to read 6, iclass 38, count 2 2006.201.13:01:56.08#ibcon#read 6, iclass 38, count 2 2006.201.13:01:56.08#ibcon#end of sib2, iclass 38, count 2 2006.201.13:01:56.08#ibcon#*mode == 0, iclass 38, count 2 2006.201.13:01:56.08#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.13:01:56.08#ibcon#[27=AT05-04\r\n] 2006.201.13:01:56.08#ibcon#*before write, iclass 38, count 2 2006.201.13:01:56.08#ibcon#enter sib2, iclass 38, count 2 2006.201.13:01:56.08#ibcon#flushed, iclass 38, count 2 2006.201.13:01:56.08#ibcon#about to write, iclass 38, count 2 2006.201.13:01:56.08#ibcon#wrote, iclass 38, count 2 2006.201.13:01:56.08#ibcon#about to read 3, iclass 38, count 2 2006.201.13:01:56.11#ibcon#read 3, iclass 38, count 2 2006.201.13:01:56.11#ibcon#about to read 4, iclass 38, count 2 2006.201.13:01:56.11#ibcon#read 4, iclass 38, count 2 2006.201.13:01:56.11#ibcon#about to read 5, iclass 38, count 2 2006.201.13:01:56.11#ibcon#read 5, iclass 38, count 2 2006.201.13:01:56.11#ibcon#about to read 6, iclass 38, count 2 2006.201.13:01:56.11#ibcon#read 6, iclass 38, count 2 2006.201.13:01:56.11#ibcon#end of sib2, iclass 38, count 2 2006.201.13:01:56.11#ibcon#*after write, iclass 38, count 2 2006.201.13:01:56.11#ibcon#*before return 0, iclass 38, count 2 2006.201.13:01:56.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:56.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:01:56.11#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.13:01:56.11#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:56.11#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:56.23#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:56.23#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:56.23#ibcon#enter wrdev, iclass 38, count 0 2006.201.13:01:56.23#ibcon#first serial, iclass 38, count 0 2006.201.13:01:56.23#ibcon#enter sib2, iclass 38, count 0 2006.201.13:01:56.23#ibcon#flushed, iclass 38, count 0 2006.201.13:01:56.23#ibcon#about to write, iclass 38, count 0 2006.201.13:01:56.23#ibcon#wrote, iclass 38, count 0 2006.201.13:01:56.23#ibcon#about to read 3, iclass 38, count 0 2006.201.13:01:56.25#ibcon#read 3, iclass 38, count 0 2006.201.13:01:56.25#ibcon#about to read 4, iclass 38, count 0 2006.201.13:01:56.25#ibcon#read 4, iclass 38, count 0 2006.201.13:01:56.25#ibcon#about to read 5, iclass 38, count 0 2006.201.13:01:56.25#ibcon#read 5, iclass 38, count 0 2006.201.13:01:56.25#ibcon#about to read 6, iclass 38, count 0 2006.201.13:01:56.25#ibcon#read 6, iclass 38, count 0 2006.201.13:01:56.25#ibcon#end of sib2, iclass 38, count 0 2006.201.13:01:56.25#ibcon#*mode == 0, iclass 38, count 0 2006.201.13:01:56.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.13:01:56.25#ibcon#[27=USB\r\n] 2006.201.13:01:56.25#ibcon#*before write, iclass 38, count 0 2006.201.13:01:56.25#ibcon#enter sib2, iclass 38, count 0 2006.201.13:01:56.25#ibcon#flushed, iclass 38, count 0 2006.201.13:01:56.25#ibcon#about to write, iclass 38, count 0 2006.201.13:01:56.25#ibcon#wrote, iclass 38, count 0 2006.201.13:01:56.25#ibcon#about to read 3, iclass 38, count 0 2006.201.13:01:56.28#ibcon#read 3, iclass 38, count 0 2006.201.13:01:56.28#ibcon#about to read 4, iclass 38, count 0 2006.201.13:01:56.28#ibcon#read 4, iclass 38, count 0 2006.201.13:01:56.28#ibcon#about to read 5, iclass 38, count 0 2006.201.13:01:56.28#ibcon#read 5, iclass 38, count 0 2006.201.13:01:56.28#ibcon#about to read 6, iclass 38, count 0 2006.201.13:01:56.28#ibcon#read 6, iclass 38, count 0 2006.201.13:01:56.28#ibcon#end of sib2, iclass 38, count 0 2006.201.13:01:56.28#ibcon#*after write, iclass 38, count 0 2006.201.13:01:56.28#ibcon#*before return 0, iclass 38, count 0 2006.201.13:01:56.28#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:56.28#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:01:56.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.13:01:56.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.13:01:56.28$vck44/vblo=6,719.99 2006.201.13:01:56.28#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.13:01:56.28#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.13:01:56.28#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:56.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:56.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:56.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:56.28#ibcon#enter wrdev, iclass 40, count 0 2006.201.13:01:56.28#ibcon#first serial, iclass 40, count 0 2006.201.13:01:56.28#ibcon#enter sib2, iclass 40, count 0 2006.201.13:01:56.28#ibcon#flushed, iclass 40, count 0 2006.201.13:01:56.28#ibcon#about to write, iclass 40, count 0 2006.201.13:01:56.28#ibcon#wrote, iclass 40, count 0 2006.201.13:01:56.28#ibcon#about to read 3, iclass 40, count 0 2006.201.13:01:56.30#ibcon#read 3, iclass 40, count 0 2006.201.13:01:56.30#ibcon#about to read 4, iclass 40, count 0 2006.201.13:01:56.30#ibcon#read 4, iclass 40, count 0 2006.201.13:01:56.30#ibcon#about to read 5, iclass 40, count 0 2006.201.13:01:56.30#ibcon#read 5, iclass 40, count 0 2006.201.13:01:56.30#ibcon#about to read 6, iclass 40, count 0 2006.201.13:01:56.30#ibcon#read 6, iclass 40, count 0 2006.201.13:01:56.30#ibcon#end of sib2, iclass 40, count 0 2006.201.13:01:56.30#ibcon#*mode == 0, iclass 40, count 0 2006.201.13:01:56.30#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.13:01:56.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:01:56.30#ibcon#*before write, iclass 40, count 0 2006.201.13:01:56.30#ibcon#enter sib2, iclass 40, count 0 2006.201.13:01:56.30#ibcon#flushed, iclass 40, count 0 2006.201.13:01:56.30#ibcon#about to write, iclass 40, count 0 2006.201.13:01:56.30#ibcon#wrote, iclass 40, count 0 2006.201.13:01:56.30#ibcon#about to read 3, iclass 40, count 0 2006.201.13:01:56.35#ibcon#read 3, iclass 40, count 0 2006.201.13:01:56.35#ibcon#about to read 4, iclass 40, count 0 2006.201.13:01:56.35#ibcon#read 4, iclass 40, count 0 2006.201.13:01:56.35#ibcon#about to read 5, iclass 40, count 0 2006.201.13:01:56.35#ibcon#read 5, iclass 40, count 0 2006.201.13:01:56.35#ibcon#about to read 6, iclass 40, count 0 2006.201.13:01:56.35#ibcon#read 6, iclass 40, count 0 2006.201.13:01:56.35#ibcon#end of sib2, iclass 40, count 0 2006.201.13:01:56.35#ibcon#*after write, iclass 40, count 0 2006.201.13:01:56.35#ibcon#*before return 0, iclass 40, count 0 2006.201.13:01:56.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:56.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:01:56.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.13:01:56.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.13:01:56.35$vck44/vb=6,4 2006.201.13:01:56.35#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.13:01:56.35#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.13:01:56.35#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:56.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:56.40#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:56.40#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:56.40#ibcon#enter wrdev, iclass 4, count 2 2006.201.13:01:56.40#ibcon#first serial, iclass 4, count 2 2006.201.13:01:56.40#ibcon#enter sib2, iclass 4, count 2 2006.201.13:01:56.40#ibcon#flushed, iclass 4, count 2 2006.201.13:01:56.40#ibcon#about to write, iclass 4, count 2 2006.201.13:01:56.40#ibcon#wrote, iclass 4, count 2 2006.201.13:01:56.40#ibcon#about to read 3, iclass 4, count 2 2006.201.13:01:56.42#ibcon#read 3, iclass 4, count 2 2006.201.13:01:56.42#ibcon#about to read 4, iclass 4, count 2 2006.201.13:01:56.42#ibcon#read 4, iclass 4, count 2 2006.201.13:01:56.42#ibcon#about to read 5, iclass 4, count 2 2006.201.13:01:56.42#ibcon#read 5, iclass 4, count 2 2006.201.13:01:56.42#ibcon#about to read 6, iclass 4, count 2 2006.201.13:01:56.42#ibcon#read 6, iclass 4, count 2 2006.201.13:01:56.42#ibcon#end of sib2, iclass 4, count 2 2006.201.13:01:56.42#ibcon#*mode == 0, iclass 4, count 2 2006.201.13:01:56.42#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.13:01:56.42#ibcon#[27=AT06-04\r\n] 2006.201.13:01:56.42#ibcon#*before write, iclass 4, count 2 2006.201.13:01:56.42#ibcon#enter sib2, iclass 4, count 2 2006.201.13:01:56.42#ibcon#flushed, iclass 4, count 2 2006.201.13:01:56.42#ibcon#about to write, iclass 4, count 2 2006.201.13:01:56.42#ibcon#wrote, iclass 4, count 2 2006.201.13:01:56.42#ibcon#about to read 3, iclass 4, count 2 2006.201.13:01:56.45#ibcon#read 3, iclass 4, count 2 2006.201.13:01:56.45#ibcon#about to read 4, iclass 4, count 2 2006.201.13:01:56.45#ibcon#read 4, iclass 4, count 2 2006.201.13:01:56.45#ibcon#about to read 5, iclass 4, count 2 2006.201.13:01:56.45#ibcon#read 5, iclass 4, count 2 2006.201.13:01:56.45#ibcon#about to read 6, iclass 4, count 2 2006.201.13:01:56.45#ibcon#read 6, iclass 4, count 2 2006.201.13:01:56.45#ibcon#end of sib2, iclass 4, count 2 2006.201.13:01:56.45#ibcon#*after write, iclass 4, count 2 2006.201.13:01:56.45#ibcon#*before return 0, iclass 4, count 2 2006.201.13:01:56.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:56.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:01:56.45#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.13:01:56.45#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:56.45#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:56.57#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:56.57#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:56.57#ibcon#enter wrdev, iclass 4, count 0 2006.201.13:01:56.57#ibcon#first serial, iclass 4, count 0 2006.201.13:01:56.57#ibcon#enter sib2, iclass 4, count 0 2006.201.13:01:56.57#ibcon#flushed, iclass 4, count 0 2006.201.13:01:56.57#ibcon#about to write, iclass 4, count 0 2006.201.13:01:56.57#ibcon#wrote, iclass 4, count 0 2006.201.13:01:56.57#ibcon#about to read 3, iclass 4, count 0 2006.201.13:01:56.59#ibcon#read 3, iclass 4, count 0 2006.201.13:01:56.59#ibcon#about to read 4, iclass 4, count 0 2006.201.13:01:56.59#ibcon#read 4, iclass 4, count 0 2006.201.13:01:56.59#ibcon#about to read 5, iclass 4, count 0 2006.201.13:01:56.59#ibcon#read 5, iclass 4, count 0 2006.201.13:01:56.59#ibcon#about to read 6, iclass 4, count 0 2006.201.13:01:56.59#ibcon#read 6, iclass 4, count 0 2006.201.13:01:56.59#ibcon#end of sib2, iclass 4, count 0 2006.201.13:01:56.59#ibcon#*mode == 0, iclass 4, count 0 2006.201.13:01:56.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.13:01:56.59#ibcon#[27=USB\r\n] 2006.201.13:01:56.59#ibcon#*before write, iclass 4, count 0 2006.201.13:01:56.59#ibcon#enter sib2, iclass 4, count 0 2006.201.13:01:56.59#ibcon#flushed, iclass 4, count 0 2006.201.13:01:56.59#ibcon#about to write, iclass 4, count 0 2006.201.13:01:56.59#ibcon#wrote, iclass 4, count 0 2006.201.13:01:56.59#ibcon#about to read 3, iclass 4, count 0 2006.201.13:01:56.62#ibcon#read 3, iclass 4, count 0 2006.201.13:01:56.62#ibcon#about to read 4, iclass 4, count 0 2006.201.13:01:56.62#ibcon#read 4, iclass 4, count 0 2006.201.13:01:56.62#ibcon#about to read 5, iclass 4, count 0 2006.201.13:01:56.62#ibcon#read 5, iclass 4, count 0 2006.201.13:01:56.62#ibcon#about to read 6, iclass 4, count 0 2006.201.13:01:56.62#ibcon#read 6, iclass 4, count 0 2006.201.13:01:56.62#ibcon#end of sib2, iclass 4, count 0 2006.201.13:01:56.62#ibcon#*after write, iclass 4, count 0 2006.201.13:01:56.62#ibcon#*before return 0, iclass 4, count 0 2006.201.13:01:56.62#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:56.62#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:01:56.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.13:01:56.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.13:01:56.62$vck44/vblo=7,734.99 2006.201.13:01:56.62#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.13:01:56.62#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.13:01:56.62#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:56.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:56.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:56.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:56.62#ibcon#enter wrdev, iclass 6, count 0 2006.201.13:01:56.62#ibcon#first serial, iclass 6, count 0 2006.201.13:01:56.62#ibcon#enter sib2, iclass 6, count 0 2006.201.13:01:56.62#ibcon#flushed, iclass 6, count 0 2006.201.13:01:56.62#ibcon#about to write, iclass 6, count 0 2006.201.13:01:56.62#ibcon#wrote, iclass 6, count 0 2006.201.13:01:56.62#ibcon#about to read 3, iclass 6, count 0 2006.201.13:01:56.64#ibcon#read 3, iclass 6, count 0 2006.201.13:01:56.64#ibcon#about to read 4, iclass 6, count 0 2006.201.13:01:56.64#ibcon#read 4, iclass 6, count 0 2006.201.13:01:56.64#ibcon#about to read 5, iclass 6, count 0 2006.201.13:01:56.64#ibcon#read 5, iclass 6, count 0 2006.201.13:01:56.64#ibcon#about to read 6, iclass 6, count 0 2006.201.13:01:56.64#ibcon#read 6, iclass 6, count 0 2006.201.13:01:56.64#ibcon#end of sib2, iclass 6, count 0 2006.201.13:01:56.64#ibcon#*mode == 0, iclass 6, count 0 2006.201.13:01:56.64#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.13:01:56.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:01:56.64#ibcon#*before write, iclass 6, count 0 2006.201.13:01:56.64#ibcon#enter sib2, iclass 6, count 0 2006.201.13:01:56.64#ibcon#flushed, iclass 6, count 0 2006.201.13:01:56.64#ibcon#about to write, iclass 6, count 0 2006.201.13:01:56.64#ibcon#wrote, iclass 6, count 0 2006.201.13:01:56.64#ibcon#about to read 3, iclass 6, count 0 2006.201.13:01:56.68#ibcon#read 3, iclass 6, count 0 2006.201.13:01:56.68#ibcon#about to read 4, iclass 6, count 0 2006.201.13:01:56.68#ibcon#read 4, iclass 6, count 0 2006.201.13:01:56.68#ibcon#about to read 5, iclass 6, count 0 2006.201.13:01:56.68#ibcon#read 5, iclass 6, count 0 2006.201.13:01:56.68#ibcon#about to read 6, iclass 6, count 0 2006.201.13:01:56.68#ibcon#read 6, iclass 6, count 0 2006.201.13:01:56.68#ibcon#end of sib2, iclass 6, count 0 2006.201.13:01:56.68#ibcon#*after write, iclass 6, count 0 2006.201.13:01:56.68#ibcon#*before return 0, iclass 6, count 0 2006.201.13:01:56.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:56.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:01:56.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.13:01:56.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.13:01:56.68$vck44/vb=7,4 2006.201.13:01:56.68#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.13:01:56.68#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.13:01:56.68#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:56.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:56.74#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:56.74#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:56.74#ibcon#enter wrdev, iclass 10, count 2 2006.201.13:01:56.74#ibcon#first serial, iclass 10, count 2 2006.201.13:01:56.74#ibcon#enter sib2, iclass 10, count 2 2006.201.13:01:56.74#ibcon#flushed, iclass 10, count 2 2006.201.13:01:56.74#ibcon#about to write, iclass 10, count 2 2006.201.13:01:56.74#ibcon#wrote, iclass 10, count 2 2006.201.13:01:56.74#ibcon#about to read 3, iclass 10, count 2 2006.201.13:01:56.76#ibcon#read 3, iclass 10, count 2 2006.201.13:01:56.76#ibcon#about to read 4, iclass 10, count 2 2006.201.13:01:56.76#ibcon#read 4, iclass 10, count 2 2006.201.13:01:56.76#ibcon#about to read 5, iclass 10, count 2 2006.201.13:01:56.76#ibcon#read 5, iclass 10, count 2 2006.201.13:01:56.76#ibcon#about to read 6, iclass 10, count 2 2006.201.13:01:56.76#ibcon#read 6, iclass 10, count 2 2006.201.13:01:56.76#ibcon#end of sib2, iclass 10, count 2 2006.201.13:01:56.76#ibcon#*mode == 0, iclass 10, count 2 2006.201.13:01:56.76#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.13:01:56.76#ibcon#[27=AT07-04\r\n] 2006.201.13:01:56.76#ibcon#*before write, iclass 10, count 2 2006.201.13:01:56.76#ibcon#enter sib2, iclass 10, count 2 2006.201.13:01:56.76#ibcon#flushed, iclass 10, count 2 2006.201.13:01:56.76#ibcon#about to write, iclass 10, count 2 2006.201.13:01:56.76#ibcon#wrote, iclass 10, count 2 2006.201.13:01:56.76#ibcon#about to read 3, iclass 10, count 2 2006.201.13:01:56.79#ibcon#read 3, iclass 10, count 2 2006.201.13:01:56.79#ibcon#about to read 4, iclass 10, count 2 2006.201.13:01:56.79#ibcon#read 4, iclass 10, count 2 2006.201.13:01:56.79#ibcon#about to read 5, iclass 10, count 2 2006.201.13:01:56.79#ibcon#read 5, iclass 10, count 2 2006.201.13:01:56.79#ibcon#about to read 6, iclass 10, count 2 2006.201.13:01:56.79#ibcon#read 6, iclass 10, count 2 2006.201.13:01:56.79#ibcon#end of sib2, iclass 10, count 2 2006.201.13:01:56.79#ibcon#*after write, iclass 10, count 2 2006.201.13:01:56.79#ibcon#*before return 0, iclass 10, count 2 2006.201.13:01:56.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:56.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:01:56.79#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.13:01:56.79#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:56.79#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:56.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:56.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:56.91#ibcon#enter wrdev, iclass 10, count 0 2006.201.13:01:56.91#ibcon#first serial, iclass 10, count 0 2006.201.13:01:56.91#ibcon#enter sib2, iclass 10, count 0 2006.201.13:01:56.91#ibcon#flushed, iclass 10, count 0 2006.201.13:01:56.91#ibcon#about to write, iclass 10, count 0 2006.201.13:01:56.91#ibcon#wrote, iclass 10, count 0 2006.201.13:01:56.91#ibcon#about to read 3, iclass 10, count 0 2006.201.13:01:56.93#ibcon#read 3, iclass 10, count 0 2006.201.13:01:56.93#ibcon#about to read 4, iclass 10, count 0 2006.201.13:01:56.93#ibcon#read 4, iclass 10, count 0 2006.201.13:01:56.93#ibcon#about to read 5, iclass 10, count 0 2006.201.13:01:56.93#ibcon#read 5, iclass 10, count 0 2006.201.13:01:56.93#ibcon#about to read 6, iclass 10, count 0 2006.201.13:01:56.93#ibcon#read 6, iclass 10, count 0 2006.201.13:01:56.93#ibcon#end of sib2, iclass 10, count 0 2006.201.13:01:56.93#ibcon#*mode == 0, iclass 10, count 0 2006.201.13:01:56.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.13:01:56.93#ibcon#[27=USB\r\n] 2006.201.13:01:56.93#ibcon#*before write, iclass 10, count 0 2006.201.13:01:56.93#ibcon#enter sib2, iclass 10, count 0 2006.201.13:01:56.93#ibcon#flushed, iclass 10, count 0 2006.201.13:01:56.93#ibcon#about to write, iclass 10, count 0 2006.201.13:01:56.93#ibcon#wrote, iclass 10, count 0 2006.201.13:01:56.93#ibcon#about to read 3, iclass 10, count 0 2006.201.13:01:56.96#ibcon#read 3, iclass 10, count 0 2006.201.13:01:56.96#ibcon#about to read 4, iclass 10, count 0 2006.201.13:01:56.96#ibcon#read 4, iclass 10, count 0 2006.201.13:01:56.96#ibcon#about to read 5, iclass 10, count 0 2006.201.13:01:56.96#ibcon#read 5, iclass 10, count 0 2006.201.13:01:56.96#ibcon#about to read 6, iclass 10, count 0 2006.201.13:01:56.96#ibcon#read 6, iclass 10, count 0 2006.201.13:01:56.96#ibcon#end of sib2, iclass 10, count 0 2006.201.13:01:56.96#ibcon#*after write, iclass 10, count 0 2006.201.13:01:56.96#ibcon#*before return 0, iclass 10, count 0 2006.201.13:01:56.96#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:56.96#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:01:56.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.13:01:56.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.13:01:56.96$vck44/vblo=8,744.99 2006.201.13:01:56.96#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.13:01:56.96#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.13:01:56.96#ibcon#ireg 17 cls_cnt 0 2006.201.13:01:56.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:56.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:56.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:56.96#ibcon#enter wrdev, iclass 12, count 0 2006.201.13:01:56.96#ibcon#first serial, iclass 12, count 0 2006.201.13:01:56.96#ibcon#enter sib2, iclass 12, count 0 2006.201.13:01:56.96#ibcon#flushed, iclass 12, count 0 2006.201.13:01:56.96#ibcon#about to write, iclass 12, count 0 2006.201.13:01:56.96#ibcon#wrote, iclass 12, count 0 2006.201.13:01:56.96#ibcon#about to read 3, iclass 12, count 0 2006.201.13:01:56.98#ibcon#read 3, iclass 12, count 0 2006.201.13:01:56.98#ibcon#about to read 4, iclass 12, count 0 2006.201.13:01:56.98#ibcon#read 4, iclass 12, count 0 2006.201.13:01:56.98#ibcon#about to read 5, iclass 12, count 0 2006.201.13:01:56.98#ibcon#read 5, iclass 12, count 0 2006.201.13:01:56.98#ibcon#about to read 6, iclass 12, count 0 2006.201.13:01:56.98#ibcon#read 6, iclass 12, count 0 2006.201.13:01:56.98#ibcon#end of sib2, iclass 12, count 0 2006.201.13:01:56.98#ibcon#*mode == 0, iclass 12, count 0 2006.201.13:01:56.98#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.13:01:56.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:01:56.98#ibcon#*before write, iclass 12, count 0 2006.201.13:01:56.98#ibcon#enter sib2, iclass 12, count 0 2006.201.13:01:56.98#ibcon#flushed, iclass 12, count 0 2006.201.13:01:56.98#ibcon#about to write, iclass 12, count 0 2006.201.13:01:56.98#ibcon#wrote, iclass 12, count 0 2006.201.13:01:56.98#ibcon#about to read 3, iclass 12, count 0 2006.201.13:01:57.03#ibcon#read 3, iclass 12, count 0 2006.201.13:01:57.03#ibcon#about to read 4, iclass 12, count 0 2006.201.13:01:57.03#ibcon#read 4, iclass 12, count 0 2006.201.13:01:57.03#ibcon#about to read 5, iclass 12, count 0 2006.201.13:01:57.03#ibcon#read 5, iclass 12, count 0 2006.201.13:01:57.03#ibcon#about to read 6, iclass 12, count 0 2006.201.13:01:57.03#ibcon#read 6, iclass 12, count 0 2006.201.13:01:57.03#ibcon#end of sib2, iclass 12, count 0 2006.201.13:01:57.03#ibcon#*after write, iclass 12, count 0 2006.201.13:01:57.03#ibcon#*before return 0, iclass 12, count 0 2006.201.13:01:57.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:57.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:01:57.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.13:01:57.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.13:01:57.03$vck44/vb=8,4 2006.201.13:01:57.03#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.13:01:57.03#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.13:01:57.03#ibcon#ireg 11 cls_cnt 2 2006.201.13:01:57.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:57.08#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:57.08#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:57.08#ibcon#enter wrdev, iclass 14, count 2 2006.201.13:01:57.08#ibcon#first serial, iclass 14, count 2 2006.201.13:01:57.08#ibcon#enter sib2, iclass 14, count 2 2006.201.13:01:57.08#ibcon#flushed, iclass 14, count 2 2006.201.13:01:57.08#ibcon#about to write, iclass 14, count 2 2006.201.13:01:57.08#ibcon#wrote, iclass 14, count 2 2006.201.13:01:57.08#ibcon#about to read 3, iclass 14, count 2 2006.201.13:01:57.10#ibcon#read 3, iclass 14, count 2 2006.201.13:01:57.10#ibcon#about to read 4, iclass 14, count 2 2006.201.13:01:57.10#ibcon#read 4, iclass 14, count 2 2006.201.13:01:57.10#ibcon#about to read 5, iclass 14, count 2 2006.201.13:01:57.10#ibcon#read 5, iclass 14, count 2 2006.201.13:01:57.10#ibcon#about to read 6, iclass 14, count 2 2006.201.13:01:57.10#ibcon#read 6, iclass 14, count 2 2006.201.13:01:57.10#ibcon#end of sib2, iclass 14, count 2 2006.201.13:01:57.10#ibcon#*mode == 0, iclass 14, count 2 2006.201.13:01:57.10#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.13:01:57.10#ibcon#[27=AT08-04\r\n] 2006.201.13:01:57.10#ibcon#*before write, iclass 14, count 2 2006.201.13:01:57.10#ibcon#enter sib2, iclass 14, count 2 2006.201.13:01:57.10#ibcon#flushed, iclass 14, count 2 2006.201.13:01:57.10#ibcon#about to write, iclass 14, count 2 2006.201.13:01:57.10#ibcon#wrote, iclass 14, count 2 2006.201.13:01:57.10#ibcon#about to read 3, iclass 14, count 2 2006.201.13:01:57.13#ibcon#read 3, iclass 14, count 2 2006.201.13:01:57.13#ibcon#about to read 4, iclass 14, count 2 2006.201.13:01:57.13#ibcon#read 4, iclass 14, count 2 2006.201.13:01:57.13#ibcon#about to read 5, iclass 14, count 2 2006.201.13:01:57.13#ibcon#read 5, iclass 14, count 2 2006.201.13:01:57.13#ibcon#about to read 6, iclass 14, count 2 2006.201.13:01:57.13#ibcon#read 6, iclass 14, count 2 2006.201.13:01:57.13#ibcon#end of sib2, iclass 14, count 2 2006.201.13:01:57.13#ibcon#*after write, iclass 14, count 2 2006.201.13:01:57.13#ibcon#*before return 0, iclass 14, count 2 2006.201.13:01:57.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:57.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:01:57.13#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.13:01:57.13#ibcon#ireg 7 cls_cnt 0 2006.201.13:01:57.13#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:57.25#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:57.25#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:57.25#ibcon#enter wrdev, iclass 14, count 0 2006.201.13:01:57.25#ibcon#first serial, iclass 14, count 0 2006.201.13:01:57.25#ibcon#enter sib2, iclass 14, count 0 2006.201.13:01:57.25#ibcon#flushed, iclass 14, count 0 2006.201.13:01:57.25#ibcon#about to write, iclass 14, count 0 2006.201.13:01:57.25#ibcon#wrote, iclass 14, count 0 2006.201.13:01:57.25#ibcon#about to read 3, iclass 14, count 0 2006.201.13:01:57.27#ibcon#read 3, iclass 14, count 0 2006.201.13:01:57.27#ibcon#about to read 4, iclass 14, count 0 2006.201.13:01:57.27#ibcon#read 4, iclass 14, count 0 2006.201.13:01:57.27#ibcon#about to read 5, iclass 14, count 0 2006.201.13:01:57.27#ibcon#read 5, iclass 14, count 0 2006.201.13:01:57.27#ibcon#about to read 6, iclass 14, count 0 2006.201.13:01:57.27#ibcon#read 6, iclass 14, count 0 2006.201.13:01:57.27#ibcon#end of sib2, iclass 14, count 0 2006.201.13:01:57.27#ibcon#*mode == 0, iclass 14, count 0 2006.201.13:01:57.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.13:01:57.27#ibcon#[27=USB\r\n] 2006.201.13:01:57.27#ibcon#*before write, iclass 14, count 0 2006.201.13:01:57.27#ibcon#enter sib2, iclass 14, count 0 2006.201.13:01:57.27#ibcon#flushed, iclass 14, count 0 2006.201.13:01:57.27#ibcon#about to write, iclass 14, count 0 2006.201.13:01:57.27#ibcon#wrote, iclass 14, count 0 2006.201.13:01:57.27#ibcon#about to read 3, iclass 14, count 0 2006.201.13:01:57.30#ibcon#read 3, iclass 14, count 0 2006.201.13:01:57.30#ibcon#about to read 4, iclass 14, count 0 2006.201.13:01:57.30#ibcon#read 4, iclass 14, count 0 2006.201.13:01:57.30#ibcon#about to read 5, iclass 14, count 0 2006.201.13:01:57.30#ibcon#read 5, iclass 14, count 0 2006.201.13:01:57.30#ibcon#about to read 6, iclass 14, count 0 2006.201.13:01:57.30#ibcon#read 6, iclass 14, count 0 2006.201.13:01:57.30#ibcon#end of sib2, iclass 14, count 0 2006.201.13:01:57.30#ibcon#*after write, iclass 14, count 0 2006.201.13:01:57.30#ibcon#*before return 0, iclass 14, count 0 2006.201.13:01:57.30#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:57.30#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:01:57.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.13:01:57.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.13:01:57.30$vck44/vabw=wide 2006.201.13:01:57.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.13:01:57.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.13:01:57.30#ibcon#ireg 8 cls_cnt 0 2006.201.13:01:57.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:57.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:57.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:57.30#ibcon#enter wrdev, iclass 16, count 0 2006.201.13:01:57.30#ibcon#first serial, iclass 16, count 0 2006.201.13:01:57.30#ibcon#enter sib2, iclass 16, count 0 2006.201.13:01:57.30#ibcon#flushed, iclass 16, count 0 2006.201.13:01:57.30#ibcon#about to write, iclass 16, count 0 2006.201.13:01:57.30#ibcon#wrote, iclass 16, count 0 2006.201.13:01:57.30#ibcon#about to read 3, iclass 16, count 0 2006.201.13:01:57.32#ibcon#read 3, iclass 16, count 0 2006.201.13:01:57.32#ibcon#about to read 4, iclass 16, count 0 2006.201.13:01:57.32#ibcon#read 4, iclass 16, count 0 2006.201.13:01:57.32#ibcon#about to read 5, iclass 16, count 0 2006.201.13:01:57.32#ibcon#read 5, iclass 16, count 0 2006.201.13:01:57.32#ibcon#about to read 6, iclass 16, count 0 2006.201.13:01:57.32#ibcon#read 6, iclass 16, count 0 2006.201.13:01:57.32#ibcon#end of sib2, iclass 16, count 0 2006.201.13:01:57.32#ibcon#*mode == 0, iclass 16, count 0 2006.201.13:01:57.32#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.13:01:57.32#ibcon#[25=BW32\r\n] 2006.201.13:01:57.32#ibcon#*before write, iclass 16, count 0 2006.201.13:01:57.32#ibcon#enter sib2, iclass 16, count 0 2006.201.13:01:57.32#ibcon#flushed, iclass 16, count 0 2006.201.13:01:57.32#ibcon#about to write, iclass 16, count 0 2006.201.13:01:57.32#ibcon#wrote, iclass 16, count 0 2006.201.13:01:57.32#ibcon#about to read 3, iclass 16, count 0 2006.201.13:01:57.35#ibcon#read 3, iclass 16, count 0 2006.201.13:01:57.35#ibcon#about to read 4, iclass 16, count 0 2006.201.13:01:57.35#ibcon#read 4, iclass 16, count 0 2006.201.13:01:57.35#ibcon#about to read 5, iclass 16, count 0 2006.201.13:01:57.35#ibcon#read 5, iclass 16, count 0 2006.201.13:01:57.35#ibcon#about to read 6, iclass 16, count 0 2006.201.13:01:57.35#ibcon#read 6, iclass 16, count 0 2006.201.13:01:57.35#ibcon#end of sib2, iclass 16, count 0 2006.201.13:01:57.35#ibcon#*after write, iclass 16, count 0 2006.201.13:01:57.35#ibcon#*before return 0, iclass 16, count 0 2006.201.13:01:57.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:57.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:01:57.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.13:01:57.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.13:01:57.35$vck44/vbbw=wide 2006.201.13:01:57.35#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.13:01:57.35#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.13:01:57.35#ibcon#ireg 8 cls_cnt 0 2006.201.13:01:57.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:01:57.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:01:57.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:01:57.42#ibcon#enter wrdev, iclass 18, count 0 2006.201.13:01:57.42#ibcon#first serial, iclass 18, count 0 2006.201.13:01:57.42#ibcon#enter sib2, iclass 18, count 0 2006.201.13:01:57.42#ibcon#flushed, iclass 18, count 0 2006.201.13:01:57.42#ibcon#about to write, iclass 18, count 0 2006.201.13:01:57.42#ibcon#wrote, iclass 18, count 0 2006.201.13:01:57.42#ibcon#about to read 3, iclass 18, count 0 2006.201.13:01:57.44#ibcon#read 3, iclass 18, count 0 2006.201.13:01:57.44#ibcon#about to read 4, iclass 18, count 0 2006.201.13:01:57.44#ibcon#read 4, iclass 18, count 0 2006.201.13:01:57.44#ibcon#about to read 5, iclass 18, count 0 2006.201.13:01:57.44#ibcon#read 5, iclass 18, count 0 2006.201.13:01:57.44#ibcon#about to read 6, iclass 18, count 0 2006.201.13:01:57.44#ibcon#read 6, iclass 18, count 0 2006.201.13:01:57.44#ibcon#end of sib2, iclass 18, count 0 2006.201.13:01:57.44#ibcon#*mode == 0, iclass 18, count 0 2006.201.13:01:57.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.13:01:57.44#ibcon#[27=BW32\r\n] 2006.201.13:01:57.44#ibcon#*before write, iclass 18, count 0 2006.201.13:01:57.44#ibcon#enter sib2, iclass 18, count 0 2006.201.13:01:57.44#ibcon#flushed, iclass 18, count 0 2006.201.13:01:57.44#ibcon#about to write, iclass 18, count 0 2006.201.13:01:57.44#ibcon#wrote, iclass 18, count 0 2006.201.13:01:57.44#ibcon#about to read 3, iclass 18, count 0 2006.201.13:01:57.47#ibcon#read 3, iclass 18, count 0 2006.201.13:01:57.47#ibcon#about to read 4, iclass 18, count 0 2006.201.13:01:57.47#ibcon#read 4, iclass 18, count 0 2006.201.13:01:57.47#ibcon#about to read 5, iclass 18, count 0 2006.201.13:01:57.47#ibcon#read 5, iclass 18, count 0 2006.201.13:01:57.47#ibcon#about to read 6, iclass 18, count 0 2006.201.13:01:57.47#ibcon#read 6, iclass 18, count 0 2006.201.13:01:57.47#ibcon#end of sib2, iclass 18, count 0 2006.201.13:01:57.47#ibcon#*after write, iclass 18, count 0 2006.201.13:01:57.47#ibcon#*before return 0, iclass 18, count 0 2006.201.13:01:57.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:01:57.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:01:57.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.13:01:57.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.13:01:57.47$setupk4/ifdk4 2006.201.13:01:57.47$ifdk4/lo= 2006.201.13:01:57.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:01:57.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:01:57.47$ifdk4/patch= 2006.201.13:01:57.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:01:57.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:01:57.47$setupk4/!*+20s 2006.201.13:02:00.08#abcon#<5=/04 1.3 2.6 21.021001003.9\r\n> 2006.201.13:02:00.10#abcon#{5=INTERFACE CLEAR} 2006.201.13:02:00.16#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:02:10.25#abcon#<5=/04 1.3 2.4 21.021001003.9\r\n> 2006.201.13:02:10.27#abcon#{5=INTERFACE CLEAR} 2006.201.13:02:10.33#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:02:11.93$setupk4/"tpicd 2006.201.13:02:11.93$setupk4/echo=off 2006.201.13:02:11.93$setupk4/xlog=off 2006.201.13:02:11.93:!2006.201.13:05:59 2006.201.13:02:12.14#trakl#Source acquired 2006.201.13:02:12.14#flagr#flagr/antenna,acquired 2006.201.13:05:59.00:preob 2006.201.13:05:59.13/onsource/TRACKING 2006.201.13:05:59.13:!2006.201.13:06:09 2006.201.13:06:09.00:"tape 2006.201.13:06:09.00:"st=record 2006.201.13:06:09.00:data_valid=on 2006.201.13:06:09.00:midob 2006.201.13:06:09.13/onsource/TRACKING 2006.201.13:06:09.13/wx/21.00,1003.8,100 2006.201.13:06:09.24/cable/+6.4755E-03 2006.201.13:06:10.33/va/01,08,usb,yes,29,31 2006.201.13:06:10.33/va/02,07,usb,yes,31,32 2006.201.13:06:10.33/va/03,08,usb,yes,28,29 2006.201.13:06:10.33/va/04,07,usb,yes,32,34 2006.201.13:06:10.33/va/05,04,usb,yes,28,29 2006.201.13:06:10.33/va/06,05,usb,yes,28,28 2006.201.13:06:10.33/va/07,05,usb,yes,28,29 2006.201.13:06:10.33/va/08,04,usb,yes,27,33 2006.201.13:06:10.56/valo/01,524.99,yes,locked 2006.201.13:06:10.56/valo/02,534.99,yes,locked 2006.201.13:06:10.56/valo/03,564.99,yes,locked 2006.201.13:06:10.56/valo/04,624.99,yes,locked 2006.201.13:06:10.56/valo/05,734.99,yes,locked 2006.201.13:06:10.56/valo/06,814.99,yes,locked 2006.201.13:06:10.56/valo/07,864.99,yes,locked 2006.201.13:06:10.56/valo/08,884.99,yes,locked 2006.201.13:06:11.65/vb/01,04,usb,yes,29,27 2006.201.13:06:11.65/vb/02,05,usb,yes,28,27 2006.201.13:06:11.65/vb/03,04,usb,yes,29,31 2006.201.13:06:11.65/vb/04,05,usb,yes,29,28 2006.201.13:06:11.65/vb/05,04,usb,yes,25,28 2006.201.13:06:11.65/vb/06,04,usb,yes,30,26 2006.201.13:06:11.65/vb/07,04,usb,yes,30,29 2006.201.13:06:11.65/vb/08,04,usb,yes,27,30 2006.201.13:06:11.89/vblo/01,629.99,yes,locked 2006.201.13:06:11.89/vblo/02,634.99,yes,locked 2006.201.13:06:11.89/vblo/03,649.99,yes,locked 2006.201.13:06:11.89/vblo/04,679.99,yes,locked 2006.201.13:06:11.89/vblo/05,709.99,yes,locked 2006.201.13:06:11.89/vblo/06,719.99,yes,locked 2006.201.13:06:11.89/vblo/07,734.99,yes,locked 2006.201.13:06:11.89/vblo/08,744.99,yes,locked 2006.201.13:06:12.04/vabw/8 2006.201.13:06:12.19/vbbw/8 2006.201.13:06:12.28/xfe/off,on,14.7 2006.201.13:06:12.66/ifatt/23,28,28,28 2006.201.13:06:13.05/fmout-gps/S +4.63E-07 2006.201.13:06:13.12:!2006.201.13:10:09 2006.201.13:10:09.00:data_valid=off 2006.201.13:10:09.00:"et 2006.201.13:10:09.00:!+3s 2006.201.13:10:12.02:"tape 2006.201.13:10:12.02:postob 2006.201.13:10:12.11/cable/+6.4746E-03 2006.201.13:10:12.11/wx/20.99,1003.9,100 2006.201.13:10:12.18/fmout-gps/S +4.57E-07 2006.201.13:10:12.18:scan_name=201-1314,jd0607,130 2006.201.13:10:12.19:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.13:10:13.14#flagr#flagr/antenna,new-source 2006.201.13:10:13.14:checkk5 2006.201.13:10:13.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:10:13.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:10:14.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:10:14.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:10:15.02/chk_obsdata//k5ts1/T2011306??a.dat file size is correct (nominal:960MB, actual:956MB). 2006.201.13:10:15.38/chk_obsdata//k5ts2/T2011306??b.dat file size is correct (nominal:960MB, actual:956MB). 2006.201.13:10:15.75/chk_obsdata//k5ts3/T2011306??c.dat file size is correct (nominal:960MB, actual:956MB). 2006.201.13:10:16.12/chk_obsdata//k5ts4/T2011306??d.dat file size is correct (nominal:960MB, actual:956MB). 2006.201.13:10:16.82/k5log//k5ts1_log_newline 2006.201.13:10:17.52/k5log//k5ts2_log_newline 2006.201.13:10:18.22/k5log//k5ts3_log_newline 2006.201.13:10:18.91/k5log//k5ts4_log_newline 2006.201.13:10:18.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:10:18.94:setupk4=1 2006.201.13:10:18.94$setupk4/echo=on 2006.201.13:10:18.94$setupk4/pcalon 2006.201.13:10:18.94$pcalon/"no phase cal control is implemented here 2006.201.13:10:18.94$setupk4/"tpicd=stop 2006.201.13:10:18.94$setupk4/"rec=synch_on 2006.201.13:10:18.94$setupk4/"rec_mode=128 2006.201.13:10:18.94$setupk4/!* 2006.201.13:10:18.94$setupk4/recpk4 2006.201.13:10:18.94$recpk4/recpatch= 2006.201.13:10:18.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:10:18.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:10:18.94$setupk4/vck44 2006.201.13:10:18.94$vck44/valo=1,524.99 2006.201.13:10:18.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.13:10:18.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.13:10:18.94#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:18.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:18.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:18.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:18.94#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:10:18.94#ibcon#first serial, iclass 5, count 0 2006.201.13:10:18.94#ibcon#enter sib2, iclass 5, count 0 2006.201.13:10:18.94#ibcon#flushed, iclass 5, count 0 2006.201.13:10:18.94#ibcon#about to write, iclass 5, count 0 2006.201.13:10:18.94#ibcon#wrote, iclass 5, count 0 2006.201.13:10:18.94#ibcon#about to read 3, iclass 5, count 0 2006.201.13:10:18.98#ibcon#read 3, iclass 5, count 0 2006.201.13:10:18.98#ibcon#about to read 4, iclass 5, count 0 2006.201.13:10:18.98#ibcon#read 4, iclass 5, count 0 2006.201.13:10:18.98#ibcon#about to read 5, iclass 5, count 0 2006.201.13:10:18.98#ibcon#read 5, iclass 5, count 0 2006.201.13:10:18.98#ibcon#about to read 6, iclass 5, count 0 2006.201.13:10:18.98#ibcon#read 6, iclass 5, count 0 2006.201.13:10:18.98#ibcon#end of sib2, iclass 5, count 0 2006.201.13:10:18.98#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:10:18.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:10:18.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:10:18.98#ibcon#*before write, iclass 5, count 0 2006.201.13:10:18.98#ibcon#enter sib2, iclass 5, count 0 2006.201.13:10:18.98#ibcon#flushed, iclass 5, count 0 2006.201.13:10:18.98#ibcon#about to write, iclass 5, count 0 2006.201.13:10:18.98#ibcon#wrote, iclass 5, count 0 2006.201.13:10:18.98#ibcon#about to read 3, iclass 5, count 0 2006.201.13:10:19.03#ibcon#read 3, iclass 5, count 0 2006.201.13:10:19.03#ibcon#about to read 4, iclass 5, count 0 2006.201.13:10:19.03#ibcon#read 4, iclass 5, count 0 2006.201.13:10:19.03#ibcon#about to read 5, iclass 5, count 0 2006.201.13:10:19.03#ibcon#read 5, iclass 5, count 0 2006.201.13:10:19.03#ibcon#about to read 6, iclass 5, count 0 2006.201.13:10:19.03#ibcon#read 6, iclass 5, count 0 2006.201.13:10:19.03#ibcon#end of sib2, iclass 5, count 0 2006.201.13:10:19.03#ibcon#*after write, iclass 5, count 0 2006.201.13:10:19.03#ibcon#*before return 0, iclass 5, count 0 2006.201.13:10:19.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:19.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:19.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:10:19.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:10:19.03$vck44/va=1,8 2006.201.13:10:19.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.13:10:19.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.13:10:19.03#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:19.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:19.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:19.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:19.03#ibcon#enter wrdev, iclass 7, count 2 2006.201.13:10:19.03#ibcon#first serial, iclass 7, count 2 2006.201.13:10:19.03#ibcon#enter sib2, iclass 7, count 2 2006.201.13:10:19.03#ibcon#flushed, iclass 7, count 2 2006.201.13:10:19.03#ibcon#about to write, iclass 7, count 2 2006.201.13:10:19.03#ibcon#wrote, iclass 7, count 2 2006.201.13:10:19.03#ibcon#about to read 3, iclass 7, count 2 2006.201.13:10:19.05#ibcon#read 3, iclass 7, count 2 2006.201.13:10:19.05#ibcon#about to read 4, iclass 7, count 2 2006.201.13:10:19.05#ibcon#read 4, iclass 7, count 2 2006.201.13:10:19.05#ibcon#about to read 5, iclass 7, count 2 2006.201.13:10:19.05#ibcon#read 5, iclass 7, count 2 2006.201.13:10:19.05#ibcon#about to read 6, iclass 7, count 2 2006.201.13:10:19.05#ibcon#read 6, iclass 7, count 2 2006.201.13:10:19.05#ibcon#end of sib2, iclass 7, count 2 2006.201.13:10:19.05#ibcon#*mode == 0, iclass 7, count 2 2006.201.13:10:19.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.13:10:19.05#ibcon#[25=AT01-08\r\n] 2006.201.13:10:19.05#ibcon#*before write, iclass 7, count 2 2006.201.13:10:19.05#ibcon#enter sib2, iclass 7, count 2 2006.201.13:10:19.05#ibcon#flushed, iclass 7, count 2 2006.201.13:10:19.05#ibcon#about to write, iclass 7, count 2 2006.201.13:10:19.05#ibcon#wrote, iclass 7, count 2 2006.201.13:10:19.05#ibcon#about to read 3, iclass 7, count 2 2006.201.13:10:19.08#ibcon#read 3, iclass 7, count 2 2006.201.13:10:19.08#ibcon#about to read 4, iclass 7, count 2 2006.201.13:10:19.08#ibcon#read 4, iclass 7, count 2 2006.201.13:10:19.08#ibcon#about to read 5, iclass 7, count 2 2006.201.13:10:19.08#ibcon#read 5, iclass 7, count 2 2006.201.13:10:19.08#ibcon#about to read 6, iclass 7, count 2 2006.201.13:10:19.08#ibcon#read 6, iclass 7, count 2 2006.201.13:10:19.08#ibcon#end of sib2, iclass 7, count 2 2006.201.13:10:19.08#ibcon#*after write, iclass 7, count 2 2006.201.13:10:19.08#ibcon#*before return 0, iclass 7, count 2 2006.201.13:10:19.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:19.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:19.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.13:10:19.08#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:19.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:19.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:19.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:19.20#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:10:19.20#ibcon#first serial, iclass 7, count 0 2006.201.13:10:19.20#ibcon#enter sib2, iclass 7, count 0 2006.201.13:10:19.20#ibcon#flushed, iclass 7, count 0 2006.201.13:10:19.20#ibcon#about to write, iclass 7, count 0 2006.201.13:10:19.20#ibcon#wrote, iclass 7, count 0 2006.201.13:10:19.20#ibcon#about to read 3, iclass 7, count 0 2006.201.13:10:19.22#ibcon#read 3, iclass 7, count 0 2006.201.13:10:19.22#ibcon#about to read 4, iclass 7, count 0 2006.201.13:10:19.22#ibcon#read 4, iclass 7, count 0 2006.201.13:10:19.22#ibcon#about to read 5, iclass 7, count 0 2006.201.13:10:19.22#ibcon#read 5, iclass 7, count 0 2006.201.13:10:19.22#ibcon#about to read 6, iclass 7, count 0 2006.201.13:10:19.22#ibcon#read 6, iclass 7, count 0 2006.201.13:10:19.22#ibcon#end of sib2, iclass 7, count 0 2006.201.13:10:19.22#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:10:19.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:10:19.22#ibcon#[25=USB\r\n] 2006.201.13:10:19.22#ibcon#*before write, iclass 7, count 0 2006.201.13:10:19.22#ibcon#enter sib2, iclass 7, count 0 2006.201.13:10:19.22#ibcon#flushed, iclass 7, count 0 2006.201.13:10:19.22#ibcon#about to write, iclass 7, count 0 2006.201.13:10:19.22#ibcon#wrote, iclass 7, count 0 2006.201.13:10:19.22#ibcon#about to read 3, iclass 7, count 0 2006.201.13:10:19.25#ibcon#read 3, iclass 7, count 0 2006.201.13:10:19.25#ibcon#about to read 4, iclass 7, count 0 2006.201.13:10:19.25#ibcon#read 4, iclass 7, count 0 2006.201.13:10:19.25#ibcon#about to read 5, iclass 7, count 0 2006.201.13:10:19.25#ibcon#read 5, iclass 7, count 0 2006.201.13:10:19.25#ibcon#about to read 6, iclass 7, count 0 2006.201.13:10:19.25#ibcon#read 6, iclass 7, count 0 2006.201.13:10:19.25#ibcon#end of sib2, iclass 7, count 0 2006.201.13:10:19.25#ibcon#*after write, iclass 7, count 0 2006.201.13:10:19.25#ibcon#*before return 0, iclass 7, count 0 2006.201.13:10:19.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:19.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:19.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:10:19.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:10:19.25$vck44/valo=2,534.99 2006.201.13:10:19.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.13:10:19.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.13:10:19.25#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:19.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:19.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:19.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:19.25#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:10:19.25#ibcon#first serial, iclass 11, count 0 2006.201.13:10:19.25#ibcon#enter sib2, iclass 11, count 0 2006.201.13:10:19.25#ibcon#flushed, iclass 11, count 0 2006.201.13:10:19.25#ibcon#about to write, iclass 11, count 0 2006.201.13:10:19.25#ibcon#wrote, iclass 11, count 0 2006.201.13:10:19.25#ibcon#about to read 3, iclass 11, count 0 2006.201.13:10:19.27#ibcon#read 3, iclass 11, count 0 2006.201.13:10:19.27#ibcon#about to read 4, iclass 11, count 0 2006.201.13:10:19.27#ibcon#read 4, iclass 11, count 0 2006.201.13:10:19.27#ibcon#about to read 5, iclass 11, count 0 2006.201.13:10:19.27#ibcon#read 5, iclass 11, count 0 2006.201.13:10:19.27#ibcon#about to read 6, iclass 11, count 0 2006.201.13:10:19.27#ibcon#read 6, iclass 11, count 0 2006.201.13:10:19.27#ibcon#end of sib2, iclass 11, count 0 2006.201.13:10:19.27#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:10:19.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:10:19.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:10:19.27#ibcon#*before write, iclass 11, count 0 2006.201.13:10:19.27#ibcon#enter sib2, iclass 11, count 0 2006.201.13:10:19.27#ibcon#flushed, iclass 11, count 0 2006.201.13:10:19.27#ibcon#about to write, iclass 11, count 0 2006.201.13:10:19.27#ibcon#wrote, iclass 11, count 0 2006.201.13:10:19.27#ibcon#about to read 3, iclass 11, count 0 2006.201.13:10:19.31#ibcon#read 3, iclass 11, count 0 2006.201.13:10:19.31#ibcon#about to read 4, iclass 11, count 0 2006.201.13:10:19.31#ibcon#read 4, iclass 11, count 0 2006.201.13:10:19.31#ibcon#about to read 5, iclass 11, count 0 2006.201.13:10:19.31#ibcon#read 5, iclass 11, count 0 2006.201.13:10:19.31#ibcon#about to read 6, iclass 11, count 0 2006.201.13:10:19.31#ibcon#read 6, iclass 11, count 0 2006.201.13:10:19.31#ibcon#end of sib2, iclass 11, count 0 2006.201.13:10:19.31#ibcon#*after write, iclass 11, count 0 2006.201.13:10:19.31#ibcon#*before return 0, iclass 11, count 0 2006.201.13:10:19.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:19.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:19.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:10:19.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:10:19.31$vck44/va=2,7 2006.201.13:10:19.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.13:10:19.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.13:10:19.31#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:19.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:19.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:19.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:19.37#ibcon#enter wrdev, iclass 13, count 2 2006.201.13:10:19.37#ibcon#first serial, iclass 13, count 2 2006.201.13:10:19.37#ibcon#enter sib2, iclass 13, count 2 2006.201.13:10:19.37#ibcon#flushed, iclass 13, count 2 2006.201.13:10:19.37#ibcon#about to write, iclass 13, count 2 2006.201.13:10:19.37#ibcon#wrote, iclass 13, count 2 2006.201.13:10:19.37#ibcon#about to read 3, iclass 13, count 2 2006.201.13:10:19.39#ibcon#read 3, iclass 13, count 2 2006.201.13:10:19.39#ibcon#about to read 4, iclass 13, count 2 2006.201.13:10:19.39#ibcon#read 4, iclass 13, count 2 2006.201.13:10:19.39#ibcon#about to read 5, iclass 13, count 2 2006.201.13:10:19.39#ibcon#read 5, iclass 13, count 2 2006.201.13:10:19.39#ibcon#about to read 6, iclass 13, count 2 2006.201.13:10:19.39#ibcon#read 6, iclass 13, count 2 2006.201.13:10:19.39#ibcon#end of sib2, iclass 13, count 2 2006.201.13:10:19.39#ibcon#*mode == 0, iclass 13, count 2 2006.201.13:10:19.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.13:10:19.39#ibcon#[25=AT02-07\r\n] 2006.201.13:10:19.39#ibcon#*before write, iclass 13, count 2 2006.201.13:10:19.39#ibcon#enter sib2, iclass 13, count 2 2006.201.13:10:19.39#ibcon#flushed, iclass 13, count 2 2006.201.13:10:19.39#ibcon#about to write, iclass 13, count 2 2006.201.13:10:19.39#ibcon#wrote, iclass 13, count 2 2006.201.13:10:19.39#ibcon#about to read 3, iclass 13, count 2 2006.201.13:10:19.42#ibcon#read 3, iclass 13, count 2 2006.201.13:10:19.42#ibcon#about to read 4, iclass 13, count 2 2006.201.13:10:19.42#ibcon#read 4, iclass 13, count 2 2006.201.13:10:19.42#ibcon#about to read 5, iclass 13, count 2 2006.201.13:10:19.42#ibcon#read 5, iclass 13, count 2 2006.201.13:10:19.42#ibcon#about to read 6, iclass 13, count 2 2006.201.13:10:19.42#ibcon#read 6, iclass 13, count 2 2006.201.13:10:19.42#ibcon#end of sib2, iclass 13, count 2 2006.201.13:10:19.42#ibcon#*after write, iclass 13, count 2 2006.201.13:10:19.42#ibcon#*before return 0, iclass 13, count 2 2006.201.13:10:19.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:19.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:19.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.13:10:19.42#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:19.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:19.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:19.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:19.54#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:10:19.54#ibcon#first serial, iclass 13, count 0 2006.201.13:10:19.54#ibcon#enter sib2, iclass 13, count 0 2006.201.13:10:19.54#ibcon#flushed, iclass 13, count 0 2006.201.13:10:19.54#ibcon#about to write, iclass 13, count 0 2006.201.13:10:19.54#ibcon#wrote, iclass 13, count 0 2006.201.13:10:19.54#ibcon#about to read 3, iclass 13, count 0 2006.201.13:10:19.56#ibcon#read 3, iclass 13, count 0 2006.201.13:10:19.56#ibcon#about to read 4, iclass 13, count 0 2006.201.13:10:19.56#ibcon#read 4, iclass 13, count 0 2006.201.13:10:19.56#ibcon#about to read 5, iclass 13, count 0 2006.201.13:10:19.56#ibcon#read 5, iclass 13, count 0 2006.201.13:10:19.56#ibcon#about to read 6, iclass 13, count 0 2006.201.13:10:19.56#ibcon#read 6, iclass 13, count 0 2006.201.13:10:19.56#ibcon#end of sib2, iclass 13, count 0 2006.201.13:10:19.56#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:10:19.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:10:19.56#ibcon#[25=USB\r\n] 2006.201.13:10:19.56#ibcon#*before write, iclass 13, count 0 2006.201.13:10:19.56#ibcon#enter sib2, iclass 13, count 0 2006.201.13:10:19.56#ibcon#flushed, iclass 13, count 0 2006.201.13:10:19.56#ibcon#about to write, iclass 13, count 0 2006.201.13:10:19.56#ibcon#wrote, iclass 13, count 0 2006.201.13:10:19.56#ibcon#about to read 3, iclass 13, count 0 2006.201.13:10:19.59#ibcon#read 3, iclass 13, count 0 2006.201.13:10:19.59#ibcon#about to read 4, iclass 13, count 0 2006.201.13:10:19.59#ibcon#read 4, iclass 13, count 0 2006.201.13:10:19.59#ibcon#about to read 5, iclass 13, count 0 2006.201.13:10:19.59#ibcon#read 5, iclass 13, count 0 2006.201.13:10:19.59#ibcon#about to read 6, iclass 13, count 0 2006.201.13:10:19.59#ibcon#read 6, iclass 13, count 0 2006.201.13:10:19.59#ibcon#end of sib2, iclass 13, count 0 2006.201.13:10:19.59#ibcon#*after write, iclass 13, count 0 2006.201.13:10:19.59#ibcon#*before return 0, iclass 13, count 0 2006.201.13:10:19.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:19.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:19.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:10:19.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:10:19.59$vck44/valo=3,564.99 2006.201.13:10:19.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.13:10:19.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.13:10:19.59#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:19.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:19.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:19.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:19.59#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:10:19.59#ibcon#first serial, iclass 15, count 0 2006.201.13:10:19.59#ibcon#enter sib2, iclass 15, count 0 2006.201.13:10:19.59#ibcon#flushed, iclass 15, count 0 2006.201.13:10:19.59#ibcon#about to write, iclass 15, count 0 2006.201.13:10:19.59#ibcon#wrote, iclass 15, count 0 2006.201.13:10:19.59#ibcon#about to read 3, iclass 15, count 0 2006.201.13:10:19.61#ibcon#read 3, iclass 15, count 0 2006.201.13:10:19.61#ibcon#about to read 4, iclass 15, count 0 2006.201.13:10:19.61#ibcon#read 4, iclass 15, count 0 2006.201.13:10:19.61#ibcon#about to read 5, iclass 15, count 0 2006.201.13:10:19.61#ibcon#read 5, iclass 15, count 0 2006.201.13:10:19.61#ibcon#about to read 6, iclass 15, count 0 2006.201.13:10:19.61#ibcon#read 6, iclass 15, count 0 2006.201.13:10:19.61#ibcon#end of sib2, iclass 15, count 0 2006.201.13:10:19.61#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:10:19.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:10:19.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:10:19.61#ibcon#*before write, iclass 15, count 0 2006.201.13:10:19.61#ibcon#enter sib2, iclass 15, count 0 2006.201.13:10:19.61#ibcon#flushed, iclass 15, count 0 2006.201.13:10:19.61#ibcon#about to write, iclass 15, count 0 2006.201.13:10:19.61#ibcon#wrote, iclass 15, count 0 2006.201.13:10:19.61#ibcon#about to read 3, iclass 15, count 0 2006.201.13:10:19.66#ibcon#read 3, iclass 15, count 0 2006.201.13:10:19.66#ibcon#about to read 4, iclass 15, count 0 2006.201.13:10:19.66#ibcon#read 4, iclass 15, count 0 2006.201.13:10:19.66#ibcon#about to read 5, iclass 15, count 0 2006.201.13:10:19.66#ibcon#read 5, iclass 15, count 0 2006.201.13:10:19.66#ibcon#about to read 6, iclass 15, count 0 2006.201.13:10:19.66#ibcon#read 6, iclass 15, count 0 2006.201.13:10:19.66#ibcon#end of sib2, iclass 15, count 0 2006.201.13:10:19.66#ibcon#*after write, iclass 15, count 0 2006.201.13:10:19.66#ibcon#*before return 0, iclass 15, count 0 2006.201.13:10:19.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:19.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:19.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:10:19.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:10:19.66$vck44/va=3,8 2006.201.13:10:19.66#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.13:10:19.66#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.13:10:19.66#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:19.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:19.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:19.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:19.71#ibcon#enter wrdev, iclass 17, count 2 2006.201.13:10:19.71#ibcon#first serial, iclass 17, count 2 2006.201.13:10:19.71#ibcon#enter sib2, iclass 17, count 2 2006.201.13:10:19.71#ibcon#flushed, iclass 17, count 2 2006.201.13:10:19.71#ibcon#about to write, iclass 17, count 2 2006.201.13:10:19.71#ibcon#wrote, iclass 17, count 2 2006.201.13:10:19.71#ibcon#about to read 3, iclass 17, count 2 2006.201.13:10:19.73#ibcon#read 3, iclass 17, count 2 2006.201.13:10:19.73#ibcon#about to read 4, iclass 17, count 2 2006.201.13:10:19.73#ibcon#read 4, iclass 17, count 2 2006.201.13:10:19.73#ibcon#about to read 5, iclass 17, count 2 2006.201.13:10:19.73#ibcon#read 5, iclass 17, count 2 2006.201.13:10:19.73#ibcon#about to read 6, iclass 17, count 2 2006.201.13:10:19.73#ibcon#read 6, iclass 17, count 2 2006.201.13:10:19.73#ibcon#end of sib2, iclass 17, count 2 2006.201.13:10:19.73#ibcon#*mode == 0, iclass 17, count 2 2006.201.13:10:19.73#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.13:10:19.73#ibcon#[25=AT03-08\r\n] 2006.201.13:10:19.73#ibcon#*before write, iclass 17, count 2 2006.201.13:10:19.73#ibcon#enter sib2, iclass 17, count 2 2006.201.13:10:19.73#ibcon#flushed, iclass 17, count 2 2006.201.13:10:19.73#ibcon#about to write, iclass 17, count 2 2006.201.13:10:19.73#ibcon#wrote, iclass 17, count 2 2006.201.13:10:19.73#ibcon#about to read 3, iclass 17, count 2 2006.201.13:10:19.76#ibcon#read 3, iclass 17, count 2 2006.201.13:10:19.76#ibcon#about to read 4, iclass 17, count 2 2006.201.13:10:19.76#ibcon#read 4, iclass 17, count 2 2006.201.13:10:19.76#ibcon#about to read 5, iclass 17, count 2 2006.201.13:10:19.76#ibcon#read 5, iclass 17, count 2 2006.201.13:10:19.76#ibcon#about to read 6, iclass 17, count 2 2006.201.13:10:19.76#ibcon#read 6, iclass 17, count 2 2006.201.13:10:19.76#ibcon#end of sib2, iclass 17, count 2 2006.201.13:10:19.76#ibcon#*after write, iclass 17, count 2 2006.201.13:10:19.76#ibcon#*before return 0, iclass 17, count 2 2006.201.13:10:19.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:19.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:19.76#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.13:10:19.76#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:19.76#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:19.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:19.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:19.88#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:10:19.88#ibcon#first serial, iclass 17, count 0 2006.201.13:10:19.88#ibcon#enter sib2, iclass 17, count 0 2006.201.13:10:19.88#ibcon#flushed, iclass 17, count 0 2006.201.13:10:19.88#ibcon#about to write, iclass 17, count 0 2006.201.13:10:19.88#ibcon#wrote, iclass 17, count 0 2006.201.13:10:19.88#ibcon#about to read 3, iclass 17, count 0 2006.201.13:10:19.90#ibcon#read 3, iclass 17, count 0 2006.201.13:10:19.90#ibcon#about to read 4, iclass 17, count 0 2006.201.13:10:19.90#ibcon#read 4, iclass 17, count 0 2006.201.13:10:19.90#ibcon#about to read 5, iclass 17, count 0 2006.201.13:10:19.90#ibcon#read 5, iclass 17, count 0 2006.201.13:10:19.90#ibcon#about to read 6, iclass 17, count 0 2006.201.13:10:19.90#ibcon#read 6, iclass 17, count 0 2006.201.13:10:19.90#ibcon#end of sib2, iclass 17, count 0 2006.201.13:10:19.90#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:10:19.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:10:19.90#ibcon#[25=USB\r\n] 2006.201.13:10:19.90#ibcon#*before write, iclass 17, count 0 2006.201.13:10:19.90#ibcon#enter sib2, iclass 17, count 0 2006.201.13:10:19.90#ibcon#flushed, iclass 17, count 0 2006.201.13:10:19.90#ibcon#about to write, iclass 17, count 0 2006.201.13:10:19.90#ibcon#wrote, iclass 17, count 0 2006.201.13:10:19.90#ibcon#about to read 3, iclass 17, count 0 2006.201.13:10:19.93#ibcon#read 3, iclass 17, count 0 2006.201.13:10:19.93#ibcon#about to read 4, iclass 17, count 0 2006.201.13:10:19.93#ibcon#read 4, iclass 17, count 0 2006.201.13:10:19.93#ibcon#about to read 5, iclass 17, count 0 2006.201.13:10:19.93#ibcon#read 5, iclass 17, count 0 2006.201.13:10:19.93#ibcon#about to read 6, iclass 17, count 0 2006.201.13:10:19.93#ibcon#read 6, iclass 17, count 0 2006.201.13:10:19.93#ibcon#end of sib2, iclass 17, count 0 2006.201.13:10:19.93#ibcon#*after write, iclass 17, count 0 2006.201.13:10:19.93#ibcon#*before return 0, iclass 17, count 0 2006.201.13:10:19.93#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:19.93#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:19.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:10:19.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:10:19.93$vck44/valo=4,624.99 2006.201.13:10:19.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.13:10:19.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.13:10:19.93#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:19.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:19.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:19.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:19.93#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:10:19.93#ibcon#first serial, iclass 19, count 0 2006.201.13:10:19.93#ibcon#enter sib2, iclass 19, count 0 2006.201.13:10:19.93#ibcon#flushed, iclass 19, count 0 2006.201.13:10:19.93#ibcon#about to write, iclass 19, count 0 2006.201.13:10:19.93#ibcon#wrote, iclass 19, count 0 2006.201.13:10:19.93#ibcon#about to read 3, iclass 19, count 0 2006.201.13:10:19.95#ibcon#read 3, iclass 19, count 0 2006.201.13:10:19.95#ibcon#about to read 4, iclass 19, count 0 2006.201.13:10:19.95#ibcon#read 4, iclass 19, count 0 2006.201.13:10:19.95#ibcon#about to read 5, iclass 19, count 0 2006.201.13:10:19.95#ibcon#read 5, iclass 19, count 0 2006.201.13:10:19.95#ibcon#about to read 6, iclass 19, count 0 2006.201.13:10:19.95#ibcon#read 6, iclass 19, count 0 2006.201.13:10:19.95#ibcon#end of sib2, iclass 19, count 0 2006.201.13:10:19.95#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:10:19.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:10:19.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:10:19.95#ibcon#*before write, iclass 19, count 0 2006.201.13:10:19.95#ibcon#enter sib2, iclass 19, count 0 2006.201.13:10:19.95#ibcon#flushed, iclass 19, count 0 2006.201.13:10:19.95#ibcon#about to write, iclass 19, count 0 2006.201.13:10:19.95#ibcon#wrote, iclass 19, count 0 2006.201.13:10:19.95#ibcon#about to read 3, iclass 19, count 0 2006.201.13:10:20.00#ibcon#read 3, iclass 19, count 0 2006.201.13:10:20.00#ibcon#about to read 4, iclass 19, count 0 2006.201.13:10:20.00#ibcon#read 4, iclass 19, count 0 2006.201.13:10:20.00#ibcon#about to read 5, iclass 19, count 0 2006.201.13:10:20.00#ibcon#read 5, iclass 19, count 0 2006.201.13:10:20.00#ibcon#about to read 6, iclass 19, count 0 2006.201.13:10:20.00#ibcon#read 6, iclass 19, count 0 2006.201.13:10:20.00#ibcon#end of sib2, iclass 19, count 0 2006.201.13:10:20.00#ibcon#*after write, iclass 19, count 0 2006.201.13:10:20.00#ibcon#*before return 0, iclass 19, count 0 2006.201.13:10:20.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:20.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:20.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:10:20.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:10:20.00$vck44/va=4,7 2006.201.13:10:20.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.13:10:20.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.13:10:20.00#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:20.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:20.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:20.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:20.05#ibcon#enter wrdev, iclass 21, count 2 2006.201.13:10:20.05#ibcon#first serial, iclass 21, count 2 2006.201.13:10:20.05#ibcon#enter sib2, iclass 21, count 2 2006.201.13:10:20.05#ibcon#flushed, iclass 21, count 2 2006.201.13:10:20.05#ibcon#about to write, iclass 21, count 2 2006.201.13:10:20.05#ibcon#wrote, iclass 21, count 2 2006.201.13:10:20.05#ibcon#about to read 3, iclass 21, count 2 2006.201.13:10:20.07#ibcon#read 3, iclass 21, count 2 2006.201.13:10:20.07#ibcon#about to read 4, iclass 21, count 2 2006.201.13:10:20.07#ibcon#read 4, iclass 21, count 2 2006.201.13:10:20.07#ibcon#about to read 5, iclass 21, count 2 2006.201.13:10:20.07#ibcon#read 5, iclass 21, count 2 2006.201.13:10:20.07#ibcon#about to read 6, iclass 21, count 2 2006.201.13:10:20.07#ibcon#read 6, iclass 21, count 2 2006.201.13:10:20.07#ibcon#end of sib2, iclass 21, count 2 2006.201.13:10:20.07#ibcon#*mode == 0, iclass 21, count 2 2006.201.13:10:20.07#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.13:10:20.07#ibcon#[25=AT04-07\r\n] 2006.201.13:10:20.07#ibcon#*before write, iclass 21, count 2 2006.201.13:10:20.07#ibcon#enter sib2, iclass 21, count 2 2006.201.13:10:20.07#ibcon#flushed, iclass 21, count 2 2006.201.13:10:20.07#ibcon#about to write, iclass 21, count 2 2006.201.13:10:20.07#ibcon#wrote, iclass 21, count 2 2006.201.13:10:20.07#ibcon#about to read 3, iclass 21, count 2 2006.201.13:10:20.10#ibcon#read 3, iclass 21, count 2 2006.201.13:10:20.10#ibcon#about to read 4, iclass 21, count 2 2006.201.13:10:20.10#ibcon#read 4, iclass 21, count 2 2006.201.13:10:20.10#ibcon#about to read 5, iclass 21, count 2 2006.201.13:10:20.10#ibcon#read 5, iclass 21, count 2 2006.201.13:10:20.10#ibcon#about to read 6, iclass 21, count 2 2006.201.13:10:20.10#ibcon#read 6, iclass 21, count 2 2006.201.13:10:20.10#ibcon#end of sib2, iclass 21, count 2 2006.201.13:10:20.10#ibcon#*after write, iclass 21, count 2 2006.201.13:10:20.10#ibcon#*before return 0, iclass 21, count 2 2006.201.13:10:20.10#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:20.10#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:20.10#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.13:10:20.10#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:20.10#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:20.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:20.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:20.22#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:10:20.22#ibcon#first serial, iclass 21, count 0 2006.201.13:10:20.22#ibcon#enter sib2, iclass 21, count 0 2006.201.13:10:20.22#ibcon#flushed, iclass 21, count 0 2006.201.13:10:20.22#ibcon#about to write, iclass 21, count 0 2006.201.13:10:20.22#ibcon#wrote, iclass 21, count 0 2006.201.13:10:20.22#ibcon#about to read 3, iclass 21, count 0 2006.201.13:10:20.24#ibcon#read 3, iclass 21, count 0 2006.201.13:10:20.24#ibcon#about to read 4, iclass 21, count 0 2006.201.13:10:20.24#ibcon#read 4, iclass 21, count 0 2006.201.13:10:20.24#ibcon#about to read 5, iclass 21, count 0 2006.201.13:10:20.24#ibcon#read 5, iclass 21, count 0 2006.201.13:10:20.24#ibcon#about to read 6, iclass 21, count 0 2006.201.13:10:20.24#ibcon#read 6, iclass 21, count 0 2006.201.13:10:20.24#ibcon#end of sib2, iclass 21, count 0 2006.201.13:10:20.24#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:10:20.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:10:20.24#ibcon#[25=USB\r\n] 2006.201.13:10:20.24#ibcon#*before write, iclass 21, count 0 2006.201.13:10:20.24#ibcon#enter sib2, iclass 21, count 0 2006.201.13:10:20.24#ibcon#flushed, iclass 21, count 0 2006.201.13:10:20.24#ibcon#about to write, iclass 21, count 0 2006.201.13:10:20.24#ibcon#wrote, iclass 21, count 0 2006.201.13:10:20.24#ibcon#about to read 3, iclass 21, count 0 2006.201.13:10:20.27#ibcon#read 3, iclass 21, count 0 2006.201.13:10:20.27#ibcon#about to read 4, iclass 21, count 0 2006.201.13:10:20.27#ibcon#read 4, iclass 21, count 0 2006.201.13:10:20.27#ibcon#about to read 5, iclass 21, count 0 2006.201.13:10:20.27#ibcon#read 5, iclass 21, count 0 2006.201.13:10:20.27#ibcon#about to read 6, iclass 21, count 0 2006.201.13:10:20.27#ibcon#read 6, iclass 21, count 0 2006.201.13:10:20.27#ibcon#end of sib2, iclass 21, count 0 2006.201.13:10:20.27#ibcon#*after write, iclass 21, count 0 2006.201.13:10:20.27#ibcon#*before return 0, iclass 21, count 0 2006.201.13:10:20.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:20.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:20.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:10:20.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:10:20.27$vck44/valo=5,734.99 2006.201.13:10:20.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.13:10:20.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.13:10:20.27#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:20.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:20.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:20.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:20.27#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:10:20.27#ibcon#first serial, iclass 23, count 0 2006.201.13:10:20.27#ibcon#enter sib2, iclass 23, count 0 2006.201.13:10:20.27#ibcon#flushed, iclass 23, count 0 2006.201.13:10:20.27#ibcon#about to write, iclass 23, count 0 2006.201.13:10:20.27#ibcon#wrote, iclass 23, count 0 2006.201.13:10:20.27#ibcon#about to read 3, iclass 23, count 0 2006.201.13:10:20.29#ibcon#read 3, iclass 23, count 0 2006.201.13:10:20.29#ibcon#about to read 4, iclass 23, count 0 2006.201.13:10:20.29#ibcon#read 4, iclass 23, count 0 2006.201.13:10:20.29#ibcon#about to read 5, iclass 23, count 0 2006.201.13:10:20.29#ibcon#read 5, iclass 23, count 0 2006.201.13:10:20.29#ibcon#about to read 6, iclass 23, count 0 2006.201.13:10:20.29#ibcon#read 6, iclass 23, count 0 2006.201.13:10:20.29#ibcon#end of sib2, iclass 23, count 0 2006.201.13:10:20.29#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:10:20.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:10:20.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:10:20.29#ibcon#*before write, iclass 23, count 0 2006.201.13:10:20.29#ibcon#enter sib2, iclass 23, count 0 2006.201.13:10:20.29#ibcon#flushed, iclass 23, count 0 2006.201.13:10:20.29#ibcon#about to write, iclass 23, count 0 2006.201.13:10:20.29#ibcon#wrote, iclass 23, count 0 2006.201.13:10:20.29#ibcon#about to read 3, iclass 23, count 0 2006.201.13:10:20.33#ibcon#read 3, iclass 23, count 0 2006.201.13:10:20.33#ibcon#about to read 4, iclass 23, count 0 2006.201.13:10:20.33#ibcon#read 4, iclass 23, count 0 2006.201.13:10:20.33#ibcon#about to read 5, iclass 23, count 0 2006.201.13:10:20.33#ibcon#read 5, iclass 23, count 0 2006.201.13:10:20.33#ibcon#about to read 6, iclass 23, count 0 2006.201.13:10:20.33#ibcon#read 6, iclass 23, count 0 2006.201.13:10:20.33#ibcon#end of sib2, iclass 23, count 0 2006.201.13:10:20.33#ibcon#*after write, iclass 23, count 0 2006.201.13:10:20.33#ibcon#*before return 0, iclass 23, count 0 2006.201.13:10:20.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:20.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:20.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:10:20.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:10:20.33$vck44/va=5,4 2006.201.13:10:20.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.13:10:20.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.13:10:20.33#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:20.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:20.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:20.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:20.39#ibcon#enter wrdev, iclass 25, count 2 2006.201.13:10:20.39#ibcon#first serial, iclass 25, count 2 2006.201.13:10:20.39#ibcon#enter sib2, iclass 25, count 2 2006.201.13:10:20.39#ibcon#flushed, iclass 25, count 2 2006.201.13:10:20.39#ibcon#about to write, iclass 25, count 2 2006.201.13:10:20.39#ibcon#wrote, iclass 25, count 2 2006.201.13:10:20.39#ibcon#about to read 3, iclass 25, count 2 2006.201.13:10:20.41#ibcon#read 3, iclass 25, count 2 2006.201.13:10:20.41#ibcon#about to read 4, iclass 25, count 2 2006.201.13:10:20.41#ibcon#read 4, iclass 25, count 2 2006.201.13:10:20.41#ibcon#about to read 5, iclass 25, count 2 2006.201.13:10:20.41#ibcon#read 5, iclass 25, count 2 2006.201.13:10:20.41#ibcon#about to read 6, iclass 25, count 2 2006.201.13:10:20.41#ibcon#read 6, iclass 25, count 2 2006.201.13:10:20.41#ibcon#end of sib2, iclass 25, count 2 2006.201.13:10:20.41#ibcon#*mode == 0, iclass 25, count 2 2006.201.13:10:20.41#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.13:10:20.41#ibcon#[25=AT05-04\r\n] 2006.201.13:10:20.41#ibcon#*before write, iclass 25, count 2 2006.201.13:10:20.41#ibcon#enter sib2, iclass 25, count 2 2006.201.13:10:20.41#ibcon#flushed, iclass 25, count 2 2006.201.13:10:20.41#ibcon#about to write, iclass 25, count 2 2006.201.13:10:20.41#ibcon#wrote, iclass 25, count 2 2006.201.13:10:20.41#ibcon#about to read 3, iclass 25, count 2 2006.201.13:10:20.44#ibcon#read 3, iclass 25, count 2 2006.201.13:10:20.44#ibcon#about to read 4, iclass 25, count 2 2006.201.13:10:20.44#ibcon#read 4, iclass 25, count 2 2006.201.13:10:20.44#ibcon#about to read 5, iclass 25, count 2 2006.201.13:10:20.44#ibcon#read 5, iclass 25, count 2 2006.201.13:10:20.44#ibcon#about to read 6, iclass 25, count 2 2006.201.13:10:20.44#ibcon#read 6, iclass 25, count 2 2006.201.13:10:20.44#ibcon#end of sib2, iclass 25, count 2 2006.201.13:10:20.44#ibcon#*after write, iclass 25, count 2 2006.201.13:10:20.44#ibcon#*before return 0, iclass 25, count 2 2006.201.13:10:20.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:20.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:20.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.13:10:20.44#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:20.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:20.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:20.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:20.56#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:10:20.56#ibcon#first serial, iclass 25, count 0 2006.201.13:10:20.56#ibcon#enter sib2, iclass 25, count 0 2006.201.13:10:20.56#ibcon#flushed, iclass 25, count 0 2006.201.13:10:20.56#ibcon#about to write, iclass 25, count 0 2006.201.13:10:20.56#ibcon#wrote, iclass 25, count 0 2006.201.13:10:20.56#ibcon#about to read 3, iclass 25, count 0 2006.201.13:10:20.58#ibcon#read 3, iclass 25, count 0 2006.201.13:10:20.58#ibcon#about to read 4, iclass 25, count 0 2006.201.13:10:20.58#ibcon#read 4, iclass 25, count 0 2006.201.13:10:20.58#ibcon#about to read 5, iclass 25, count 0 2006.201.13:10:20.58#ibcon#read 5, iclass 25, count 0 2006.201.13:10:20.58#ibcon#about to read 6, iclass 25, count 0 2006.201.13:10:20.58#ibcon#read 6, iclass 25, count 0 2006.201.13:10:20.58#ibcon#end of sib2, iclass 25, count 0 2006.201.13:10:20.58#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:10:20.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:10:20.58#ibcon#[25=USB\r\n] 2006.201.13:10:20.58#ibcon#*before write, iclass 25, count 0 2006.201.13:10:20.58#ibcon#enter sib2, iclass 25, count 0 2006.201.13:10:20.58#ibcon#flushed, iclass 25, count 0 2006.201.13:10:20.58#ibcon#about to write, iclass 25, count 0 2006.201.13:10:20.58#ibcon#wrote, iclass 25, count 0 2006.201.13:10:20.58#ibcon#about to read 3, iclass 25, count 0 2006.201.13:10:20.61#ibcon#read 3, iclass 25, count 0 2006.201.13:10:20.61#ibcon#about to read 4, iclass 25, count 0 2006.201.13:10:20.61#ibcon#read 4, iclass 25, count 0 2006.201.13:10:20.61#ibcon#about to read 5, iclass 25, count 0 2006.201.13:10:20.61#ibcon#read 5, iclass 25, count 0 2006.201.13:10:20.61#ibcon#about to read 6, iclass 25, count 0 2006.201.13:10:20.61#ibcon#read 6, iclass 25, count 0 2006.201.13:10:20.61#ibcon#end of sib2, iclass 25, count 0 2006.201.13:10:20.61#ibcon#*after write, iclass 25, count 0 2006.201.13:10:20.61#ibcon#*before return 0, iclass 25, count 0 2006.201.13:10:20.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:20.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:20.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:10:20.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:10:20.61$vck44/valo=6,814.99 2006.201.13:10:20.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.13:10:20.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.13:10:20.61#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:20.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:20.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:20.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:20.61#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:10:20.61#ibcon#first serial, iclass 27, count 0 2006.201.13:10:20.61#ibcon#enter sib2, iclass 27, count 0 2006.201.13:10:20.61#ibcon#flushed, iclass 27, count 0 2006.201.13:10:20.61#ibcon#about to write, iclass 27, count 0 2006.201.13:10:20.61#ibcon#wrote, iclass 27, count 0 2006.201.13:10:20.61#ibcon#about to read 3, iclass 27, count 0 2006.201.13:10:20.63#ibcon#read 3, iclass 27, count 0 2006.201.13:10:20.63#ibcon#about to read 4, iclass 27, count 0 2006.201.13:10:20.63#ibcon#read 4, iclass 27, count 0 2006.201.13:10:20.63#ibcon#about to read 5, iclass 27, count 0 2006.201.13:10:20.63#ibcon#read 5, iclass 27, count 0 2006.201.13:10:20.63#ibcon#about to read 6, iclass 27, count 0 2006.201.13:10:20.63#ibcon#read 6, iclass 27, count 0 2006.201.13:10:20.63#ibcon#end of sib2, iclass 27, count 0 2006.201.13:10:20.63#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:10:20.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:10:20.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:10:20.63#ibcon#*before write, iclass 27, count 0 2006.201.13:10:20.63#ibcon#enter sib2, iclass 27, count 0 2006.201.13:10:20.63#ibcon#flushed, iclass 27, count 0 2006.201.13:10:20.63#ibcon#about to write, iclass 27, count 0 2006.201.13:10:20.63#ibcon#wrote, iclass 27, count 0 2006.201.13:10:20.63#ibcon#about to read 3, iclass 27, count 0 2006.201.13:10:20.67#ibcon#read 3, iclass 27, count 0 2006.201.13:10:20.67#ibcon#about to read 4, iclass 27, count 0 2006.201.13:10:20.67#ibcon#read 4, iclass 27, count 0 2006.201.13:10:20.67#ibcon#about to read 5, iclass 27, count 0 2006.201.13:10:20.67#ibcon#read 5, iclass 27, count 0 2006.201.13:10:20.67#ibcon#about to read 6, iclass 27, count 0 2006.201.13:10:20.67#ibcon#read 6, iclass 27, count 0 2006.201.13:10:20.67#ibcon#end of sib2, iclass 27, count 0 2006.201.13:10:20.67#ibcon#*after write, iclass 27, count 0 2006.201.13:10:20.67#ibcon#*before return 0, iclass 27, count 0 2006.201.13:10:20.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:20.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:20.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:10:20.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:10:20.67$vck44/va=6,5 2006.201.13:10:20.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.13:10:20.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.13:10:20.67#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:20.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:20.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:20.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:20.73#ibcon#enter wrdev, iclass 29, count 2 2006.201.13:10:20.73#ibcon#first serial, iclass 29, count 2 2006.201.13:10:20.73#ibcon#enter sib2, iclass 29, count 2 2006.201.13:10:20.73#ibcon#flushed, iclass 29, count 2 2006.201.13:10:20.73#ibcon#about to write, iclass 29, count 2 2006.201.13:10:20.73#ibcon#wrote, iclass 29, count 2 2006.201.13:10:20.73#ibcon#about to read 3, iclass 29, count 2 2006.201.13:10:20.75#ibcon#read 3, iclass 29, count 2 2006.201.13:10:20.75#ibcon#about to read 4, iclass 29, count 2 2006.201.13:10:20.75#ibcon#read 4, iclass 29, count 2 2006.201.13:10:20.75#ibcon#about to read 5, iclass 29, count 2 2006.201.13:10:20.75#ibcon#read 5, iclass 29, count 2 2006.201.13:10:20.75#ibcon#about to read 6, iclass 29, count 2 2006.201.13:10:20.75#ibcon#read 6, iclass 29, count 2 2006.201.13:10:20.75#ibcon#end of sib2, iclass 29, count 2 2006.201.13:10:20.75#ibcon#*mode == 0, iclass 29, count 2 2006.201.13:10:20.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.13:10:20.75#ibcon#[25=AT06-05\r\n] 2006.201.13:10:20.75#ibcon#*before write, iclass 29, count 2 2006.201.13:10:20.75#ibcon#enter sib2, iclass 29, count 2 2006.201.13:10:20.75#ibcon#flushed, iclass 29, count 2 2006.201.13:10:20.75#ibcon#about to write, iclass 29, count 2 2006.201.13:10:20.75#ibcon#wrote, iclass 29, count 2 2006.201.13:10:20.75#ibcon#about to read 3, iclass 29, count 2 2006.201.13:10:20.78#ibcon#read 3, iclass 29, count 2 2006.201.13:10:20.78#ibcon#about to read 4, iclass 29, count 2 2006.201.13:10:20.78#ibcon#read 4, iclass 29, count 2 2006.201.13:10:20.78#ibcon#about to read 5, iclass 29, count 2 2006.201.13:10:20.78#ibcon#read 5, iclass 29, count 2 2006.201.13:10:20.78#ibcon#about to read 6, iclass 29, count 2 2006.201.13:10:20.78#ibcon#read 6, iclass 29, count 2 2006.201.13:10:20.78#ibcon#end of sib2, iclass 29, count 2 2006.201.13:10:20.78#ibcon#*after write, iclass 29, count 2 2006.201.13:10:20.78#ibcon#*before return 0, iclass 29, count 2 2006.201.13:10:20.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:20.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:20.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.13:10:20.78#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:20.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:20.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:20.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:20.90#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:10:20.90#ibcon#first serial, iclass 29, count 0 2006.201.13:10:20.90#ibcon#enter sib2, iclass 29, count 0 2006.201.13:10:20.90#ibcon#flushed, iclass 29, count 0 2006.201.13:10:20.90#ibcon#about to write, iclass 29, count 0 2006.201.13:10:20.90#ibcon#wrote, iclass 29, count 0 2006.201.13:10:20.90#ibcon#about to read 3, iclass 29, count 0 2006.201.13:10:20.92#ibcon#read 3, iclass 29, count 0 2006.201.13:10:20.92#ibcon#about to read 4, iclass 29, count 0 2006.201.13:10:20.92#ibcon#read 4, iclass 29, count 0 2006.201.13:10:20.92#ibcon#about to read 5, iclass 29, count 0 2006.201.13:10:20.92#ibcon#read 5, iclass 29, count 0 2006.201.13:10:20.92#ibcon#about to read 6, iclass 29, count 0 2006.201.13:10:20.92#ibcon#read 6, iclass 29, count 0 2006.201.13:10:20.92#ibcon#end of sib2, iclass 29, count 0 2006.201.13:10:20.92#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:10:20.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:10:20.92#ibcon#[25=USB\r\n] 2006.201.13:10:20.92#ibcon#*before write, iclass 29, count 0 2006.201.13:10:20.92#ibcon#enter sib2, iclass 29, count 0 2006.201.13:10:20.92#ibcon#flushed, iclass 29, count 0 2006.201.13:10:20.92#ibcon#about to write, iclass 29, count 0 2006.201.13:10:20.92#ibcon#wrote, iclass 29, count 0 2006.201.13:10:20.92#ibcon#about to read 3, iclass 29, count 0 2006.201.13:10:20.95#ibcon#read 3, iclass 29, count 0 2006.201.13:10:20.95#ibcon#about to read 4, iclass 29, count 0 2006.201.13:10:20.95#ibcon#read 4, iclass 29, count 0 2006.201.13:10:20.95#ibcon#about to read 5, iclass 29, count 0 2006.201.13:10:20.95#ibcon#read 5, iclass 29, count 0 2006.201.13:10:20.95#ibcon#about to read 6, iclass 29, count 0 2006.201.13:10:20.95#ibcon#read 6, iclass 29, count 0 2006.201.13:10:20.95#ibcon#end of sib2, iclass 29, count 0 2006.201.13:10:20.95#ibcon#*after write, iclass 29, count 0 2006.201.13:10:20.95#ibcon#*before return 0, iclass 29, count 0 2006.201.13:10:20.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:20.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:20.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:10:20.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:10:20.95$vck44/valo=7,864.99 2006.201.13:10:20.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.13:10:20.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.13:10:20.95#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:20.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:20.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:20.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:20.95#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:10:20.95#ibcon#first serial, iclass 31, count 0 2006.201.13:10:20.95#ibcon#enter sib2, iclass 31, count 0 2006.201.13:10:20.95#ibcon#flushed, iclass 31, count 0 2006.201.13:10:20.95#ibcon#about to write, iclass 31, count 0 2006.201.13:10:20.95#ibcon#wrote, iclass 31, count 0 2006.201.13:10:20.95#ibcon#about to read 3, iclass 31, count 0 2006.201.13:10:20.97#ibcon#read 3, iclass 31, count 0 2006.201.13:10:20.97#ibcon#about to read 4, iclass 31, count 0 2006.201.13:10:20.97#ibcon#read 4, iclass 31, count 0 2006.201.13:10:20.97#ibcon#about to read 5, iclass 31, count 0 2006.201.13:10:20.97#ibcon#read 5, iclass 31, count 0 2006.201.13:10:20.97#ibcon#about to read 6, iclass 31, count 0 2006.201.13:10:20.97#ibcon#read 6, iclass 31, count 0 2006.201.13:10:20.97#ibcon#end of sib2, iclass 31, count 0 2006.201.13:10:20.97#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:10:20.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:10:20.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:10:20.97#ibcon#*before write, iclass 31, count 0 2006.201.13:10:20.97#ibcon#enter sib2, iclass 31, count 0 2006.201.13:10:20.97#ibcon#flushed, iclass 31, count 0 2006.201.13:10:20.97#ibcon#about to write, iclass 31, count 0 2006.201.13:10:20.97#ibcon#wrote, iclass 31, count 0 2006.201.13:10:20.97#ibcon#about to read 3, iclass 31, count 0 2006.201.13:10:21.01#ibcon#read 3, iclass 31, count 0 2006.201.13:10:21.01#ibcon#about to read 4, iclass 31, count 0 2006.201.13:10:21.01#ibcon#read 4, iclass 31, count 0 2006.201.13:10:21.01#ibcon#about to read 5, iclass 31, count 0 2006.201.13:10:21.01#ibcon#read 5, iclass 31, count 0 2006.201.13:10:21.01#ibcon#about to read 6, iclass 31, count 0 2006.201.13:10:21.01#ibcon#read 6, iclass 31, count 0 2006.201.13:10:21.01#ibcon#end of sib2, iclass 31, count 0 2006.201.13:10:21.01#ibcon#*after write, iclass 31, count 0 2006.201.13:10:21.01#ibcon#*before return 0, iclass 31, count 0 2006.201.13:10:21.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:21.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:21.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:10:21.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:10:21.01$vck44/va=7,5 2006.201.13:10:21.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.13:10:21.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.13:10:21.01#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:21.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:21.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:21.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:21.07#ibcon#enter wrdev, iclass 33, count 2 2006.201.13:10:21.07#ibcon#first serial, iclass 33, count 2 2006.201.13:10:21.07#ibcon#enter sib2, iclass 33, count 2 2006.201.13:10:21.07#ibcon#flushed, iclass 33, count 2 2006.201.13:10:21.07#ibcon#about to write, iclass 33, count 2 2006.201.13:10:21.07#ibcon#wrote, iclass 33, count 2 2006.201.13:10:21.07#ibcon#about to read 3, iclass 33, count 2 2006.201.13:10:21.09#ibcon#read 3, iclass 33, count 2 2006.201.13:10:21.09#ibcon#about to read 4, iclass 33, count 2 2006.201.13:10:21.09#ibcon#read 4, iclass 33, count 2 2006.201.13:10:21.09#ibcon#about to read 5, iclass 33, count 2 2006.201.13:10:21.09#ibcon#read 5, iclass 33, count 2 2006.201.13:10:21.09#ibcon#about to read 6, iclass 33, count 2 2006.201.13:10:21.09#ibcon#read 6, iclass 33, count 2 2006.201.13:10:21.09#ibcon#end of sib2, iclass 33, count 2 2006.201.13:10:21.09#ibcon#*mode == 0, iclass 33, count 2 2006.201.13:10:21.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.13:10:21.09#ibcon#[25=AT07-05\r\n] 2006.201.13:10:21.09#ibcon#*before write, iclass 33, count 2 2006.201.13:10:21.09#ibcon#enter sib2, iclass 33, count 2 2006.201.13:10:21.09#ibcon#flushed, iclass 33, count 2 2006.201.13:10:21.09#ibcon#about to write, iclass 33, count 2 2006.201.13:10:21.09#ibcon#wrote, iclass 33, count 2 2006.201.13:10:21.09#ibcon#about to read 3, iclass 33, count 2 2006.201.13:10:21.12#ibcon#read 3, iclass 33, count 2 2006.201.13:10:21.12#ibcon#about to read 4, iclass 33, count 2 2006.201.13:10:21.12#ibcon#read 4, iclass 33, count 2 2006.201.13:10:21.12#ibcon#about to read 5, iclass 33, count 2 2006.201.13:10:21.12#ibcon#read 5, iclass 33, count 2 2006.201.13:10:21.12#ibcon#about to read 6, iclass 33, count 2 2006.201.13:10:21.12#ibcon#read 6, iclass 33, count 2 2006.201.13:10:21.12#ibcon#end of sib2, iclass 33, count 2 2006.201.13:10:21.12#ibcon#*after write, iclass 33, count 2 2006.201.13:10:21.12#ibcon#*before return 0, iclass 33, count 2 2006.201.13:10:21.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:21.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:21.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.13:10:21.12#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:21.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:21.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:21.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:21.24#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:10:21.24#ibcon#first serial, iclass 33, count 0 2006.201.13:10:21.24#ibcon#enter sib2, iclass 33, count 0 2006.201.13:10:21.24#ibcon#flushed, iclass 33, count 0 2006.201.13:10:21.24#ibcon#about to write, iclass 33, count 0 2006.201.13:10:21.24#ibcon#wrote, iclass 33, count 0 2006.201.13:10:21.24#ibcon#about to read 3, iclass 33, count 0 2006.201.13:10:21.26#ibcon#read 3, iclass 33, count 0 2006.201.13:10:21.26#ibcon#about to read 4, iclass 33, count 0 2006.201.13:10:21.26#ibcon#read 4, iclass 33, count 0 2006.201.13:10:21.26#ibcon#about to read 5, iclass 33, count 0 2006.201.13:10:21.26#ibcon#read 5, iclass 33, count 0 2006.201.13:10:21.26#ibcon#about to read 6, iclass 33, count 0 2006.201.13:10:21.26#ibcon#read 6, iclass 33, count 0 2006.201.13:10:21.26#ibcon#end of sib2, iclass 33, count 0 2006.201.13:10:21.26#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:10:21.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:10:21.26#ibcon#[25=USB\r\n] 2006.201.13:10:21.26#ibcon#*before write, iclass 33, count 0 2006.201.13:10:21.26#ibcon#enter sib2, iclass 33, count 0 2006.201.13:10:21.26#ibcon#flushed, iclass 33, count 0 2006.201.13:10:21.26#ibcon#about to write, iclass 33, count 0 2006.201.13:10:21.26#ibcon#wrote, iclass 33, count 0 2006.201.13:10:21.26#ibcon#about to read 3, iclass 33, count 0 2006.201.13:10:21.29#ibcon#read 3, iclass 33, count 0 2006.201.13:10:21.29#ibcon#about to read 4, iclass 33, count 0 2006.201.13:10:21.29#ibcon#read 4, iclass 33, count 0 2006.201.13:10:21.29#ibcon#about to read 5, iclass 33, count 0 2006.201.13:10:21.29#ibcon#read 5, iclass 33, count 0 2006.201.13:10:21.29#ibcon#about to read 6, iclass 33, count 0 2006.201.13:10:21.29#ibcon#read 6, iclass 33, count 0 2006.201.13:10:21.29#ibcon#end of sib2, iclass 33, count 0 2006.201.13:10:21.29#ibcon#*after write, iclass 33, count 0 2006.201.13:10:21.29#ibcon#*before return 0, iclass 33, count 0 2006.201.13:10:21.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:21.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:21.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:10:21.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:10:21.29$vck44/valo=8,884.99 2006.201.13:10:21.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.13:10:21.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.13:10:21.29#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:21.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:21.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:21.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:21.29#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:10:21.29#ibcon#first serial, iclass 35, count 0 2006.201.13:10:21.29#ibcon#enter sib2, iclass 35, count 0 2006.201.13:10:21.29#ibcon#flushed, iclass 35, count 0 2006.201.13:10:21.29#ibcon#about to write, iclass 35, count 0 2006.201.13:10:21.29#ibcon#wrote, iclass 35, count 0 2006.201.13:10:21.29#ibcon#about to read 3, iclass 35, count 0 2006.201.13:10:21.31#ibcon#read 3, iclass 35, count 0 2006.201.13:10:21.31#ibcon#about to read 4, iclass 35, count 0 2006.201.13:10:21.31#ibcon#read 4, iclass 35, count 0 2006.201.13:10:21.31#ibcon#about to read 5, iclass 35, count 0 2006.201.13:10:21.31#ibcon#read 5, iclass 35, count 0 2006.201.13:10:21.31#ibcon#about to read 6, iclass 35, count 0 2006.201.13:10:21.31#ibcon#read 6, iclass 35, count 0 2006.201.13:10:21.31#ibcon#end of sib2, iclass 35, count 0 2006.201.13:10:21.31#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:10:21.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:10:21.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:10:21.31#ibcon#*before write, iclass 35, count 0 2006.201.13:10:21.31#ibcon#enter sib2, iclass 35, count 0 2006.201.13:10:21.31#ibcon#flushed, iclass 35, count 0 2006.201.13:10:21.31#ibcon#about to write, iclass 35, count 0 2006.201.13:10:21.31#ibcon#wrote, iclass 35, count 0 2006.201.13:10:21.31#ibcon#about to read 3, iclass 35, count 0 2006.201.13:10:21.36#ibcon#read 3, iclass 35, count 0 2006.201.13:10:21.36#ibcon#about to read 4, iclass 35, count 0 2006.201.13:10:21.36#ibcon#read 4, iclass 35, count 0 2006.201.13:10:21.36#ibcon#about to read 5, iclass 35, count 0 2006.201.13:10:21.36#ibcon#read 5, iclass 35, count 0 2006.201.13:10:21.36#ibcon#about to read 6, iclass 35, count 0 2006.201.13:10:21.36#ibcon#read 6, iclass 35, count 0 2006.201.13:10:21.36#ibcon#end of sib2, iclass 35, count 0 2006.201.13:10:21.36#ibcon#*after write, iclass 35, count 0 2006.201.13:10:21.36#ibcon#*before return 0, iclass 35, count 0 2006.201.13:10:21.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:21.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:21.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:10:21.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:10:21.36$vck44/va=8,4 2006.201.13:10:21.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.13:10:21.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.13:10:21.36#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:21.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:10:21.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:10:21.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:10:21.41#ibcon#enter wrdev, iclass 37, count 2 2006.201.13:10:21.41#ibcon#first serial, iclass 37, count 2 2006.201.13:10:21.41#ibcon#enter sib2, iclass 37, count 2 2006.201.13:10:21.41#ibcon#flushed, iclass 37, count 2 2006.201.13:10:21.41#ibcon#about to write, iclass 37, count 2 2006.201.13:10:21.41#ibcon#wrote, iclass 37, count 2 2006.201.13:10:21.41#ibcon#about to read 3, iclass 37, count 2 2006.201.13:10:21.43#ibcon#read 3, iclass 37, count 2 2006.201.13:10:21.43#ibcon#about to read 4, iclass 37, count 2 2006.201.13:10:21.43#ibcon#read 4, iclass 37, count 2 2006.201.13:10:21.43#ibcon#about to read 5, iclass 37, count 2 2006.201.13:10:21.43#ibcon#read 5, iclass 37, count 2 2006.201.13:10:21.43#ibcon#about to read 6, iclass 37, count 2 2006.201.13:10:21.43#ibcon#read 6, iclass 37, count 2 2006.201.13:10:21.43#ibcon#end of sib2, iclass 37, count 2 2006.201.13:10:21.43#ibcon#*mode == 0, iclass 37, count 2 2006.201.13:10:21.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.13:10:21.43#ibcon#[25=AT08-04\r\n] 2006.201.13:10:21.43#ibcon#*before write, iclass 37, count 2 2006.201.13:10:21.43#ibcon#enter sib2, iclass 37, count 2 2006.201.13:10:21.43#ibcon#flushed, iclass 37, count 2 2006.201.13:10:21.43#ibcon#about to write, iclass 37, count 2 2006.201.13:10:21.43#ibcon#wrote, iclass 37, count 2 2006.201.13:10:21.43#ibcon#about to read 3, iclass 37, count 2 2006.201.13:10:21.46#ibcon#read 3, iclass 37, count 2 2006.201.13:10:21.46#ibcon#about to read 4, iclass 37, count 2 2006.201.13:10:21.46#ibcon#read 4, iclass 37, count 2 2006.201.13:10:21.46#ibcon#about to read 5, iclass 37, count 2 2006.201.13:10:21.46#ibcon#read 5, iclass 37, count 2 2006.201.13:10:21.46#ibcon#about to read 6, iclass 37, count 2 2006.201.13:10:21.46#ibcon#read 6, iclass 37, count 2 2006.201.13:10:21.46#ibcon#end of sib2, iclass 37, count 2 2006.201.13:10:21.46#ibcon#*after write, iclass 37, count 2 2006.201.13:10:21.46#ibcon#*before return 0, iclass 37, count 2 2006.201.13:10:21.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:10:21.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:10:21.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.13:10:21.46#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:21.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:10:21.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:10:21.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:10:21.58#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:10:21.58#ibcon#first serial, iclass 37, count 0 2006.201.13:10:21.58#ibcon#enter sib2, iclass 37, count 0 2006.201.13:10:21.58#ibcon#flushed, iclass 37, count 0 2006.201.13:10:21.58#ibcon#about to write, iclass 37, count 0 2006.201.13:10:21.58#ibcon#wrote, iclass 37, count 0 2006.201.13:10:21.58#ibcon#about to read 3, iclass 37, count 0 2006.201.13:10:21.60#ibcon#read 3, iclass 37, count 0 2006.201.13:10:21.60#ibcon#about to read 4, iclass 37, count 0 2006.201.13:10:21.60#ibcon#read 4, iclass 37, count 0 2006.201.13:10:21.60#ibcon#about to read 5, iclass 37, count 0 2006.201.13:10:21.60#ibcon#read 5, iclass 37, count 0 2006.201.13:10:21.60#ibcon#about to read 6, iclass 37, count 0 2006.201.13:10:21.60#ibcon#read 6, iclass 37, count 0 2006.201.13:10:21.60#ibcon#end of sib2, iclass 37, count 0 2006.201.13:10:21.60#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:10:21.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:10:21.60#ibcon#[25=USB\r\n] 2006.201.13:10:21.60#ibcon#*before write, iclass 37, count 0 2006.201.13:10:21.60#ibcon#enter sib2, iclass 37, count 0 2006.201.13:10:21.60#ibcon#flushed, iclass 37, count 0 2006.201.13:10:21.60#ibcon#about to write, iclass 37, count 0 2006.201.13:10:21.60#ibcon#wrote, iclass 37, count 0 2006.201.13:10:21.60#ibcon#about to read 3, iclass 37, count 0 2006.201.13:10:21.63#ibcon#read 3, iclass 37, count 0 2006.201.13:10:21.63#ibcon#about to read 4, iclass 37, count 0 2006.201.13:10:21.63#ibcon#read 4, iclass 37, count 0 2006.201.13:10:21.63#ibcon#about to read 5, iclass 37, count 0 2006.201.13:10:21.63#ibcon#read 5, iclass 37, count 0 2006.201.13:10:21.63#ibcon#about to read 6, iclass 37, count 0 2006.201.13:10:21.63#ibcon#read 6, iclass 37, count 0 2006.201.13:10:21.63#ibcon#end of sib2, iclass 37, count 0 2006.201.13:10:21.63#ibcon#*after write, iclass 37, count 0 2006.201.13:10:21.63#ibcon#*before return 0, iclass 37, count 0 2006.201.13:10:21.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:10:21.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:10:21.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:10:21.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:10:21.63$vck44/vblo=1,629.99 2006.201.13:10:21.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.13:10:21.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.13:10:21.63#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:21.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:10:21.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:10:21.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:10:21.63#ibcon#enter wrdev, iclass 39, count 0 2006.201.13:10:21.63#ibcon#first serial, iclass 39, count 0 2006.201.13:10:21.63#ibcon#enter sib2, iclass 39, count 0 2006.201.13:10:21.63#ibcon#flushed, iclass 39, count 0 2006.201.13:10:21.63#ibcon#about to write, iclass 39, count 0 2006.201.13:10:21.63#ibcon#wrote, iclass 39, count 0 2006.201.13:10:21.63#ibcon#about to read 3, iclass 39, count 0 2006.201.13:10:21.65#ibcon#read 3, iclass 39, count 0 2006.201.13:10:21.65#ibcon#about to read 4, iclass 39, count 0 2006.201.13:10:21.65#ibcon#read 4, iclass 39, count 0 2006.201.13:10:21.65#ibcon#about to read 5, iclass 39, count 0 2006.201.13:10:21.65#ibcon#read 5, iclass 39, count 0 2006.201.13:10:21.65#ibcon#about to read 6, iclass 39, count 0 2006.201.13:10:21.65#ibcon#read 6, iclass 39, count 0 2006.201.13:10:21.65#ibcon#end of sib2, iclass 39, count 0 2006.201.13:10:21.65#ibcon#*mode == 0, iclass 39, count 0 2006.201.13:10:21.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.13:10:21.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:10:21.65#ibcon#*before write, iclass 39, count 0 2006.201.13:10:21.65#ibcon#enter sib2, iclass 39, count 0 2006.201.13:10:21.65#ibcon#flushed, iclass 39, count 0 2006.201.13:10:21.65#ibcon#about to write, iclass 39, count 0 2006.201.13:10:21.65#ibcon#wrote, iclass 39, count 0 2006.201.13:10:21.65#ibcon#about to read 3, iclass 39, count 0 2006.201.13:10:21.69#ibcon#read 3, iclass 39, count 0 2006.201.13:10:21.69#ibcon#about to read 4, iclass 39, count 0 2006.201.13:10:21.69#ibcon#read 4, iclass 39, count 0 2006.201.13:10:21.69#ibcon#about to read 5, iclass 39, count 0 2006.201.13:10:21.69#ibcon#read 5, iclass 39, count 0 2006.201.13:10:21.69#ibcon#about to read 6, iclass 39, count 0 2006.201.13:10:21.69#ibcon#read 6, iclass 39, count 0 2006.201.13:10:21.69#ibcon#end of sib2, iclass 39, count 0 2006.201.13:10:21.69#ibcon#*after write, iclass 39, count 0 2006.201.13:10:21.69#ibcon#*before return 0, iclass 39, count 0 2006.201.13:10:21.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:10:21.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:10:21.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.13:10:21.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.13:10:21.69$vck44/vb=1,4 2006.201.13:10:21.69#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.13:10:21.69#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.13:10:21.69#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:21.69#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:10:21.69#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:10:21.69#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:10:21.69#ibcon#enter wrdev, iclass 2, count 2 2006.201.13:10:21.69#ibcon#first serial, iclass 2, count 2 2006.201.13:10:21.69#ibcon#enter sib2, iclass 2, count 2 2006.201.13:10:21.69#ibcon#flushed, iclass 2, count 2 2006.201.13:10:21.69#ibcon#about to write, iclass 2, count 2 2006.201.13:10:21.69#ibcon#wrote, iclass 2, count 2 2006.201.13:10:21.69#ibcon#about to read 3, iclass 2, count 2 2006.201.13:10:21.71#ibcon#read 3, iclass 2, count 2 2006.201.13:10:21.71#ibcon#about to read 4, iclass 2, count 2 2006.201.13:10:21.71#ibcon#read 4, iclass 2, count 2 2006.201.13:10:21.71#ibcon#about to read 5, iclass 2, count 2 2006.201.13:10:21.71#ibcon#read 5, iclass 2, count 2 2006.201.13:10:21.71#ibcon#about to read 6, iclass 2, count 2 2006.201.13:10:21.71#ibcon#read 6, iclass 2, count 2 2006.201.13:10:21.71#ibcon#end of sib2, iclass 2, count 2 2006.201.13:10:21.71#ibcon#*mode == 0, iclass 2, count 2 2006.201.13:10:21.71#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.13:10:21.71#ibcon#[27=AT01-04\r\n] 2006.201.13:10:21.71#ibcon#*before write, iclass 2, count 2 2006.201.13:10:21.71#ibcon#enter sib2, iclass 2, count 2 2006.201.13:10:21.71#ibcon#flushed, iclass 2, count 2 2006.201.13:10:21.71#ibcon#about to write, iclass 2, count 2 2006.201.13:10:21.71#ibcon#wrote, iclass 2, count 2 2006.201.13:10:21.71#ibcon#about to read 3, iclass 2, count 2 2006.201.13:10:21.74#ibcon#read 3, iclass 2, count 2 2006.201.13:10:21.74#ibcon#about to read 4, iclass 2, count 2 2006.201.13:10:21.74#ibcon#read 4, iclass 2, count 2 2006.201.13:10:21.74#ibcon#about to read 5, iclass 2, count 2 2006.201.13:10:21.74#ibcon#read 5, iclass 2, count 2 2006.201.13:10:21.74#ibcon#about to read 6, iclass 2, count 2 2006.201.13:10:21.74#ibcon#read 6, iclass 2, count 2 2006.201.13:10:21.74#ibcon#end of sib2, iclass 2, count 2 2006.201.13:10:21.74#ibcon#*after write, iclass 2, count 2 2006.201.13:10:21.74#ibcon#*before return 0, iclass 2, count 2 2006.201.13:10:21.74#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:10:21.74#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:10:21.74#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.13:10:21.74#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:21.74#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:10:21.86#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:10:21.86#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:10:21.86#ibcon#enter wrdev, iclass 2, count 0 2006.201.13:10:21.86#ibcon#first serial, iclass 2, count 0 2006.201.13:10:21.86#ibcon#enter sib2, iclass 2, count 0 2006.201.13:10:21.86#ibcon#flushed, iclass 2, count 0 2006.201.13:10:21.86#ibcon#about to write, iclass 2, count 0 2006.201.13:10:21.86#ibcon#wrote, iclass 2, count 0 2006.201.13:10:21.86#ibcon#about to read 3, iclass 2, count 0 2006.201.13:10:21.88#ibcon#read 3, iclass 2, count 0 2006.201.13:10:21.88#ibcon#about to read 4, iclass 2, count 0 2006.201.13:10:21.88#ibcon#read 4, iclass 2, count 0 2006.201.13:10:21.88#ibcon#about to read 5, iclass 2, count 0 2006.201.13:10:21.88#ibcon#read 5, iclass 2, count 0 2006.201.13:10:21.88#ibcon#about to read 6, iclass 2, count 0 2006.201.13:10:21.88#ibcon#read 6, iclass 2, count 0 2006.201.13:10:21.88#ibcon#end of sib2, iclass 2, count 0 2006.201.13:10:21.88#ibcon#*mode == 0, iclass 2, count 0 2006.201.13:10:21.88#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.13:10:21.88#ibcon#[27=USB\r\n] 2006.201.13:10:21.88#ibcon#*before write, iclass 2, count 0 2006.201.13:10:21.88#ibcon#enter sib2, iclass 2, count 0 2006.201.13:10:21.88#ibcon#flushed, iclass 2, count 0 2006.201.13:10:21.88#ibcon#about to write, iclass 2, count 0 2006.201.13:10:21.88#ibcon#wrote, iclass 2, count 0 2006.201.13:10:21.88#ibcon#about to read 3, iclass 2, count 0 2006.201.13:10:21.91#ibcon#read 3, iclass 2, count 0 2006.201.13:10:21.91#ibcon#about to read 4, iclass 2, count 0 2006.201.13:10:21.91#ibcon#read 4, iclass 2, count 0 2006.201.13:10:21.91#ibcon#about to read 5, iclass 2, count 0 2006.201.13:10:21.91#ibcon#read 5, iclass 2, count 0 2006.201.13:10:21.91#ibcon#about to read 6, iclass 2, count 0 2006.201.13:10:21.91#ibcon#read 6, iclass 2, count 0 2006.201.13:10:21.91#ibcon#end of sib2, iclass 2, count 0 2006.201.13:10:21.91#ibcon#*after write, iclass 2, count 0 2006.201.13:10:21.91#ibcon#*before return 0, iclass 2, count 0 2006.201.13:10:21.91#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:10:21.91#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:10:21.91#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.13:10:21.91#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.13:10:21.91$vck44/vblo=2,634.99 2006.201.13:10:21.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.13:10:21.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.13:10:21.91#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:21.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:21.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:21.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:21.91#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:10:21.91#ibcon#first serial, iclass 5, count 0 2006.201.13:10:21.91#ibcon#enter sib2, iclass 5, count 0 2006.201.13:10:21.91#ibcon#flushed, iclass 5, count 0 2006.201.13:10:21.91#ibcon#about to write, iclass 5, count 0 2006.201.13:10:21.91#ibcon#wrote, iclass 5, count 0 2006.201.13:10:21.91#ibcon#about to read 3, iclass 5, count 0 2006.201.13:10:21.93#ibcon#read 3, iclass 5, count 0 2006.201.13:10:21.93#ibcon#about to read 4, iclass 5, count 0 2006.201.13:10:21.93#ibcon#read 4, iclass 5, count 0 2006.201.13:10:21.93#ibcon#about to read 5, iclass 5, count 0 2006.201.13:10:21.93#ibcon#read 5, iclass 5, count 0 2006.201.13:10:21.93#ibcon#about to read 6, iclass 5, count 0 2006.201.13:10:21.93#ibcon#read 6, iclass 5, count 0 2006.201.13:10:21.93#ibcon#end of sib2, iclass 5, count 0 2006.201.13:10:21.93#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:10:21.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:10:21.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:10:21.93#ibcon#*before write, iclass 5, count 0 2006.201.13:10:21.93#ibcon#enter sib2, iclass 5, count 0 2006.201.13:10:21.93#ibcon#flushed, iclass 5, count 0 2006.201.13:10:21.93#ibcon#about to write, iclass 5, count 0 2006.201.13:10:21.93#ibcon#wrote, iclass 5, count 0 2006.201.13:10:21.93#ibcon#about to read 3, iclass 5, count 0 2006.201.13:10:21.98#ibcon#read 3, iclass 5, count 0 2006.201.13:10:21.98#ibcon#about to read 4, iclass 5, count 0 2006.201.13:10:21.98#ibcon#read 4, iclass 5, count 0 2006.201.13:10:21.98#ibcon#about to read 5, iclass 5, count 0 2006.201.13:10:21.98#ibcon#read 5, iclass 5, count 0 2006.201.13:10:21.98#ibcon#about to read 6, iclass 5, count 0 2006.201.13:10:21.98#ibcon#read 6, iclass 5, count 0 2006.201.13:10:21.98#ibcon#end of sib2, iclass 5, count 0 2006.201.13:10:21.98#ibcon#*after write, iclass 5, count 0 2006.201.13:10:21.98#ibcon#*before return 0, iclass 5, count 0 2006.201.13:10:21.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:21.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:10:21.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:10:21.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:10:21.98$vck44/vb=2,5 2006.201.13:10:21.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.13:10:21.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.13:10:21.98#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:21.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:22.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:22.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:22.03#ibcon#enter wrdev, iclass 7, count 2 2006.201.13:10:22.03#ibcon#first serial, iclass 7, count 2 2006.201.13:10:22.03#ibcon#enter sib2, iclass 7, count 2 2006.201.13:10:22.03#ibcon#flushed, iclass 7, count 2 2006.201.13:10:22.03#ibcon#about to write, iclass 7, count 2 2006.201.13:10:22.03#ibcon#wrote, iclass 7, count 2 2006.201.13:10:22.03#ibcon#about to read 3, iclass 7, count 2 2006.201.13:10:22.05#ibcon#read 3, iclass 7, count 2 2006.201.13:10:22.05#ibcon#about to read 4, iclass 7, count 2 2006.201.13:10:22.05#ibcon#read 4, iclass 7, count 2 2006.201.13:10:22.05#ibcon#about to read 5, iclass 7, count 2 2006.201.13:10:22.05#ibcon#read 5, iclass 7, count 2 2006.201.13:10:22.05#ibcon#about to read 6, iclass 7, count 2 2006.201.13:10:22.05#ibcon#read 6, iclass 7, count 2 2006.201.13:10:22.05#ibcon#end of sib2, iclass 7, count 2 2006.201.13:10:22.05#ibcon#*mode == 0, iclass 7, count 2 2006.201.13:10:22.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.13:10:22.05#ibcon#[27=AT02-05\r\n] 2006.201.13:10:22.05#ibcon#*before write, iclass 7, count 2 2006.201.13:10:22.05#ibcon#enter sib2, iclass 7, count 2 2006.201.13:10:22.05#ibcon#flushed, iclass 7, count 2 2006.201.13:10:22.05#ibcon#about to write, iclass 7, count 2 2006.201.13:10:22.05#ibcon#wrote, iclass 7, count 2 2006.201.13:10:22.05#ibcon#about to read 3, iclass 7, count 2 2006.201.13:10:22.08#ibcon#read 3, iclass 7, count 2 2006.201.13:10:22.08#ibcon#about to read 4, iclass 7, count 2 2006.201.13:10:22.08#ibcon#read 4, iclass 7, count 2 2006.201.13:10:22.08#ibcon#about to read 5, iclass 7, count 2 2006.201.13:10:22.08#ibcon#read 5, iclass 7, count 2 2006.201.13:10:22.08#ibcon#about to read 6, iclass 7, count 2 2006.201.13:10:22.08#ibcon#read 6, iclass 7, count 2 2006.201.13:10:22.08#ibcon#end of sib2, iclass 7, count 2 2006.201.13:10:22.08#ibcon#*after write, iclass 7, count 2 2006.201.13:10:22.08#ibcon#*before return 0, iclass 7, count 2 2006.201.13:10:22.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:22.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:10:22.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.13:10:22.08#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:22.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:22.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:22.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:22.20#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:10:22.20#ibcon#first serial, iclass 7, count 0 2006.201.13:10:22.20#ibcon#enter sib2, iclass 7, count 0 2006.201.13:10:22.20#ibcon#flushed, iclass 7, count 0 2006.201.13:10:22.20#ibcon#about to write, iclass 7, count 0 2006.201.13:10:22.20#ibcon#wrote, iclass 7, count 0 2006.201.13:10:22.20#ibcon#about to read 3, iclass 7, count 0 2006.201.13:10:22.22#ibcon#read 3, iclass 7, count 0 2006.201.13:10:22.22#ibcon#about to read 4, iclass 7, count 0 2006.201.13:10:22.22#ibcon#read 4, iclass 7, count 0 2006.201.13:10:22.22#ibcon#about to read 5, iclass 7, count 0 2006.201.13:10:22.22#ibcon#read 5, iclass 7, count 0 2006.201.13:10:22.22#ibcon#about to read 6, iclass 7, count 0 2006.201.13:10:22.22#ibcon#read 6, iclass 7, count 0 2006.201.13:10:22.22#ibcon#end of sib2, iclass 7, count 0 2006.201.13:10:22.22#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:10:22.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:10:22.22#ibcon#[27=USB\r\n] 2006.201.13:10:22.22#ibcon#*before write, iclass 7, count 0 2006.201.13:10:22.22#ibcon#enter sib2, iclass 7, count 0 2006.201.13:10:22.22#ibcon#flushed, iclass 7, count 0 2006.201.13:10:22.22#ibcon#about to write, iclass 7, count 0 2006.201.13:10:22.22#ibcon#wrote, iclass 7, count 0 2006.201.13:10:22.22#ibcon#about to read 3, iclass 7, count 0 2006.201.13:10:22.25#ibcon#read 3, iclass 7, count 0 2006.201.13:10:22.25#ibcon#about to read 4, iclass 7, count 0 2006.201.13:10:22.25#ibcon#read 4, iclass 7, count 0 2006.201.13:10:22.25#ibcon#about to read 5, iclass 7, count 0 2006.201.13:10:22.25#ibcon#read 5, iclass 7, count 0 2006.201.13:10:22.25#ibcon#about to read 6, iclass 7, count 0 2006.201.13:10:22.25#ibcon#read 6, iclass 7, count 0 2006.201.13:10:22.25#ibcon#end of sib2, iclass 7, count 0 2006.201.13:10:22.25#ibcon#*after write, iclass 7, count 0 2006.201.13:10:22.25#ibcon#*before return 0, iclass 7, count 0 2006.201.13:10:22.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:22.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:10:22.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:10:22.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:10:22.25$vck44/vblo=3,649.99 2006.201.13:10:22.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.13:10:22.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.13:10:22.25#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:22.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:22.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:22.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:22.25#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:10:22.25#ibcon#first serial, iclass 11, count 0 2006.201.13:10:22.25#ibcon#enter sib2, iclass 11, count 0 2006.201.13:10:22.25#ibcon#flushed, iclass 11, count 0 2006.201.13:10:22.25#ibcon#about to write, iclass 11, count 0 2006.201.13:10:22.25#ibcon#wrote, iclass 11, count 0 2006.201.13:10:22.25#ibcon#about to read 3, iclass 11, count 0 2006.201.13:10:22.27#ibcon#read 3, iclass 11, count 0 2006.201.13:10:22.27#ibcon#about to read 4, iclass 11, count 0 2006.201.13:10:22.27#ibcon#read 4, iclass 11, count 0 2006.201.13:10:22.27#ibcon#about to read 5, iclass 11, count 0 2006.201.13:10:22.27#ibcon#read 5, iclass 11, count 0 2006.201.13:10:22.27#ibcon#about to read 6, iclass 11, count 0 2006.201.13:10:22.27#ibcon#read 6, iclass 11, count 0 2006.201.13:10:22.27#ibcon#end of sib2, iclass 11, count 0 2006.201.13:10:22.27#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:10:22.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:10:22.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:10:22.27#ibcon#*before write, iclass 11, count 0 2006.201.13:10:22.27#ibcon#enter sib2, iclass 11, count 0 2006.201.13:10:22.27#ibcon#flushed, iclass 11, count 0 2006.201.13:10:22.27#ibcon#about to write, iclass 11, count 0 2006.201.13:10:22.27#ibcon#wrote, iclass 11, count 0 2006.201.13:10:22.27#ibcon#about to read 3, iclass 11, count 0 2006.201.13:10:22.31#ibcon#read 3, iclass 11, count 0 2006.201.13:10:22.31#ibcon#about to read 4, iclass 11, count 0 2006.201.13:10:22.31#ibcon#read 4, iclass 11, count 0 2006.201.13:10:22.31#ibcon#about to read 5, iclass 11, count 0 2006.201.13:10:22.31#ibcon#read 5, iclass 11, count 0 2006.201.13:10:22.31#ibcon#about to read 6, iclass 11, count 0 2006.201.13:10:22.31#ibcon#read 6, iclass 11, count 0 2006.201.13:10:22.31#ibcon#end of sib2, iclass 11, count 0 2006.201.13:10:22.31#ibcon#*after write, iclass 11, count 0 2006.201.13:10:22.31#ibcon#*before return 0, iclass 11, count 0 2006.201.13:10:22.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:22.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:10:22.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:10:22.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:10:22.31$vck44/vb=3,4 2006.201.13:10:22.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.13:10:22.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.13:10:22.31#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:22.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:22.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:22.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:22.37#ibcon#enter wrdev, iclass 13, count 2 2006.201.13:10:22.37#ibcon#first serial, iclass 13, count 2 2006.201.13:10:22.37#ibcon#enter sib2, iclass 13, count 2 2006.201.13:10:22.37#ibcon#flushed, iclass 13, count 2 2006.201.13:10:22.37#ibcon#about to write, iclass 13, count 2 2006.201.13:10:22.37#ibcon#wrote, iclass 13, count 2 2006.201.13:10:22.37#ibcon#about to read 3, iclass 13, count 2 2006.201.13:10:22.39#ibcon#read 3, iclass 13, count 2 2006.201.13:10:22.39#ibcon#about to read 4, iclass 13, count 2 2006.201.13:10:22.39#ibcon#read 4, iclass 13, count 2 2006.201.13:10:22.39#ibcon#about to read 5, iclass 13, count 2 2006.201.13:10:22.39#ibcon#read 5, iclass 13, count 2 2006.201.13:10:22.39#ibcon#about to read 6, iclass 13, count 2 2006.201.13:10:22.39#ibcon#read 6, iclass 13, count 2 2006.201.13:10:22.39#ibcon#end of sib2, iclass 13, count 2 2006.201.13:10:22.39#ibcon#*mode == 0, iclass 13, count 2 2006.201.13:10:22.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.13:10:22.39#ibcon#[27=AT03-04\r\n] 2006.201.13:10:22.39#ibcon#*before write, iclass 13, count 2 2006.201.13:10:22.39#ibcon#enter sib2, iclass 13, count 2 2006.201.13:10:22.39#ibcon#flushed, iclass 13, count 2 2006.201.13:10:22.39#ibcon#about to write, iclass 13, count 2 2006.201.13:10:22.39#ibcon#wrote, iclass 13, count 2 2006.201.13:10:22.39#ibcon#about to read 3, iclass 13, count 2 2006.201.13:10:22.42#ibcon#read 3, iclass 13, count 2 2006.201.13:10:22.42#ibcon#about to read 4, iclass 13, count 2 2006.201.13:10:22.42#ibcon#read 4, iclass 13, count 2 2006.201.13:10:22.42#ibcon#about to read 5, iclass 13, count 2 2006.201.13:10:22.42#ibcon#read 5, iclass 13, count 2 2006.201.13:10:22.42#ibcon#about to read 6, iclass 13, count 2 2006.201.13:10:22.42#ibcon#read 6, iclass 13, count 2 2006.201.13:10:22.42#ibcon#end of sib2, iclass 13, count 2 2006.201.13:10:22.42#ibcon#*after write, iclass 13, count 2 2006.201.13:10:22.42#ibcon#*before return 0, iclass 13, count 2 2006.201.13:10:22.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:22.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:10:22.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.13:10:22.42#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:22.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:22.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:22.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:22.54#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:10:22.54#ibcon#first serial, iclass 13, count 0 2006.201.13:10:22.54#ibcon#enter sib2, iclass 13, count 0 2006.201.13:10:22.54#ibcon#flushed, iclass 13, count 0 2006.201.13:10:22.54#ibcon#about to write, iclass 13, count 0 2006.201.13:10:22.54#ibcon#wrote, iclass 13, count 0 2006.201.13:10:22.54#ibcon#about to read 3, iclass 13, count 0 2006.201.13:10:22.56#ibcon#read 3, iclass 13, count 0 2006.201.13:10:22.56#ibcon#about to read 4, iclass 13, count 0 2006.201.13:10:22.56#ibcon#read 4, iclass 13, count 0 2006.201.13:10:22.56#ibcon#about to read 5, iclass 13, count 0 2006.201.13:10:22.56#ibcon#read 5, iclass 13, count 0 2006.201.13:10:22.56#ibcon#about to read 6, iclass 13, count 0 2006.201.13:10:22.56#ibcon#read 6, iclass 13, count 0 2006.201.13:10:22.56#ibcon#end of sib2, iclass 13, count 0 2006.201.13:10:22.56#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:10:22.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:10:22.56#ibcon#[27=USB\r\n] 2006.201.13:10:22.56#ibcon#*before write, iclass 13, count 0 2006.201.13:10:22.56#ibcon#enter sib2, iclass 13, count 0 2006.201.13:10:22.56#ibcon#flushed, iclass 13, count 0 2006.201.13:10:22.56#ibcon#about to write, iclass 13, count 0 2006.201.13:10:22.56#ibcon#wrote, iclass 13, count 0 2006.201.13:10:22.56#ibcon#about to read 3, iclass 13, count 0 2006.201.13:10:22.59#ibcon#read 3, iclass 13, count 0 2006.201.13:10:22.59#ibcon#about to read 4, iclass 13, count 0 2006.201.13:10:22.59#ibcon#read 4, iclass 13, count 0 2006.201.13:10:22.59#ibcon#about to read 5, iclass 13, count 0 2006.201.13:10:22.59#ibcon#read 5, iclass 13, count 0 2006.201.13:10:22.59#ibcon#about to read 6, iclass 13, count 0 2006.201.13:10:22.59#ibcon#read 6, iclass 13, count 0 2006.201.13:10:22.59#ibcon#end of sib2, iclass 13, count 0 2006.201.13:10:22.59#ibcon#*after write, iclass 13, count 0 2006.201.13:10:22.59#ibcon#*before return 0, iclass 13, count 0 2006.201.13:10:22.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:22.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:10:22.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:10:22.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:10:22.59$vck44/vblo=4,679.99 2006.201.13:10:22.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.13:10:22.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.13:10:22.59#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:22.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:22.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:22.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:22.59#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:10:22.59#ibcon#first serial, iclass 15, count 0 2006.201.13:10:22.59#ibcon#enter sib2, iclass 15, count 0 2006.201.13:10:22.59#ibcon#flushed, iclass 15, count 0 2006.201.13:10:22.59#ibcon#about to write, iclass 15, count 0 2006.201.13:10:22.59#ibcon#wrote, iclass 15, count 0 2006.201.13:10:22.59#ibcon#about to read 3, iclass 15, count 0 2006.201.13:10:22.61#ibcon#read 3, iclass 15, count 0 2006.201.13:10:22.61#ibcon#about to read 4, iclass 15, count 0 2006.201.13:10:22.61#ibcon#read 4, iclass 15, count 0 2006.201.13:10:22.61#ibcon#about to read 5, iclass 15, count 0 2006.201.13:10:22.61#ibcon#read 5, iclass 15, count 0 2006.201.13:10:22.61#ibcon#about to read 6, iclass 15, count 0 2006.201.13:10:22.61#ibcon#read 6, iclass 15, count 0 2006.201.13:10:22.61#ibcon#end of sib2, iclass 15, count 0 2006.201.13:10:22.61#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:10:22.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:10:22.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:10:22.61#ibcon#*before write, iclass 15, count 0 2006.201.13:10:22.61#ibcon#enter sib2, iclass 15, count 0 2006.201.13:10:22.61#ibcon#flushed, iclass 15, count 0 2006.201.13:10:22.61#ibcon#about to write, iclass 15, count 0 2006.201.13:10:22.61#ibcon#wrote, iclass 15, count 0 2006.201.13:10:22.61#ibcon#about to read 3, iclass 15, count 0 2006.201.13:10:22.65#ibcon#read 3, iclass 15, count 0 2006.201.13:10:22.65#ibcon#about to read 4, iclass 15, count 0 2006.201.13:10:22.65#ibcon#read 4, iclass 15, count 0 2006.201.13:10:22.65#ibcon#about to read 5, iclass 15, count 0 2006.201.13:10:22.65#ibcon#read 5, iclass 15, count 0 2006.201.13:10:22.65#ibcon#about to read 6, iclass 15, count 0 2006.201.13:10:22.65#ibcon#read 6, iclass 15, count 0 2006.201.13:10:22.65#ibcon#end of sib2, iclass 15, count 0 2006.201.13:10:22.65#ibcon#*after write, iclass 15, count 0 2006.201.13:10:22.65#ibcon#*before return 0, iclass 15, count 0 2006.201.13:10:22.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:22.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:10:22.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:10:22.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:10:22.65$vck44/vb=4,5 2006.201.13:10:22.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.13:10:22.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.13:10:22.65#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:22.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:22.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:22.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:22.71#ibcon#enter wrdev, iclass 17, count 2 2006.201.13:10:22.71#ibcon#first serial, iclass 17, count 2 2006.201.13:10:22.71#ibcon#enter sib2, iclass 17, count 2 2006.201.13:10:22.71#ibcon#flushed, iclass 17, count 2 2006.201.13:10:22.71#ibcon#about to write, iclass 17, count 2 2006.201.13:10:22.71#ibcon#wrote, iclass 17, count 2 2006.201.13:10:22.71#ibcon#about to read 3, iclass 17, count 2 2006.201.13:10:22.73#ibcon#read 3, iclass 17, count 2 2006.201.13:10:22.73#ibcon#about to read 4, iclass 17, count 2 2006.201.13:10:22.73#ibcon#read 4, iclass 17, count 2 2006.201.13:10:22.73#ibcon#about to read 5, iclass 17, count 2 2006.201.13:10:22.73#ibcon#read 5, iclass 17, count 2 2006.201.13:10:22.73#ibcon#about to read 6, iclass 17, count 2 2006.201.13:10:22.73#ibcon#read 6, iclass 17, count 2 2006.201.13:10:22.73#ibcon#end of sib2, iclass 17, count 2 2006.201.13:10:22.73#ibcon#*mode == 0, iclass 17, count 2 2006.201.13:10:22.73#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.13:10:22.73#ibcon#[27=AT04-05\r\n] 2006.201.13:10:22.73#ibcon#*before write, iclass 17, count 2 2006.201.13:10:22.73#ibcon#enter sib2, iclass 17, count 2 2006.201.13:10:22.73#ibcon#flushed, iclass 17, count 2 2006.201.13:10:22.73#ibcon#about to write, iclass 17, count 2 2006.201.13:10:22.73#ibcon#wrote, iclass 17, count 2 2006.201.13:10:22.73#ibcon#about to read 3, iclass 17, count 2 2006.201.13:10:22.76#ibcon#read 3, iclass 17, count 2 2006.201.13:10:22.76#ibcon#about to read 4, iclass 17, count 2 2006.201.13:10:22.76#ibcon#read 4, iclass 17, count 2 2006.201.13:10:22.76#ibcon#about to read 5, iclass 17, count 2 2006.201.13:10:22.76#ibcon#read 5, iclass 17, count 2 2006.201.13:10:22.76#ibcon#about to read 6, iclass 17, count 2 2006.201.13:10:22.76#ibcon#read 6, iclass 17, count 2 2006.201.13:10:22.76#ibcon#end of sib2, iclass 17, count 2 2006.201.13:10:22.76#ibcon#*after write, iclass 17, count 2 2006.201.13:10:22.76#ibcon#*before return 0, iclass 17, count 2 2006.201.13:10:22.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:22.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:10:22.76#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.13:10:22.76#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:22.76#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:22.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:22.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:22.88#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:10:22.88#ibcon#first serial, iclass 17, count 0 2006.201.13:10:22.88#ibcon#enter sib2, iclass 17, count 0 2006.201.13:10:22.88#ibcon#flushed, iclass 17, count 0 2006.201.13:10:22.88#ibcon#about to write, iclass 17, count 0 2006.201.13:10:22.88#ibcon#wrote, iclass 17, count 0 2006.201.13:10:22.88#ibcon#about to read 3, iclass 17, count 0 2006.201.13:10:22.90#ibcon#read 3, iclass 17, count 0 2006.201.13:10:22.90#ibcon#about to read 4, iclass 17, count 0 2006.201.13:10:22.90#ibcon#read 4, iclass 17, count 0 2006.201.13:10:22.90#ibcon#about to read 5, iclass 17, count 0 2006.201.13:10:22.90#ibcon#read 5, iclass 17, count 0 2006.201.13:10:22.90#ibcon#about to read 6, iclass 17, count 0 2006.201.13:10:22.90#ibcon#read 6, iclass 17, count 0 2006.201.13:10:22.90#ibcon#end of sib2, iclass 17, count 0 2006.201.13:10:22.90#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:10:22.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:10:22.90#ibcon#[27=USB\r\n] 2006.201.13:10:22.90#ibcon#*before write, iclass 17, count 0 2006.201.13:10:22.90#ibcon#enter sib2, iclass 17, count 0 2006.201.13:10:22.90#ibcon#flushed, iclass 17, count 0 2006.201.13:10:22.90#ibcon#about to write, iclass 17, count 0 2006.201.13:10:22.90#ibcon#wrote, iclass 17, count 0 2006.201.13:10:22.90#ibcon#about to read 3, iclass 17, count 0 2006.201.13:10:22.93#ibcon#read 3, iclass 17, count 0 2006.201.13:10:22.93#ibcon#about to read 4, iclass 17, count 0 2006.201.13:10:22.93#ibcon#read 4, iclass 17, count 0 2006.201.13:10:22.93#ibcon#about to read 5, iclass 17, count 0 2006.201.13:10:22.93#ibcon#read 5, iclass 17, count 0 2006.201.13:10:22.93#ibcon#about to read 6, iclass 17, count 0 2006.201.13:10:22.93#ibcon#read 6, iclass 17, count 0 2006.201.13:10:22.93#ibcon#end of sib2, iclass 17, count 0 2006.201.13:10:22.93#ibcon#*after write, iclass 17, count 0 2006.201.13:10:22.93#ibcon#*before return 0, iclass 17, count 0 2006.201.13:10:22.93#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:22.93#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:10:22.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:10:22.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:10:22.93$vck44/vblo=5,709.99 2006.201.13:10:22.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.13:10:22.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.13:10:22.93#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:22.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:22.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:22.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:22.93#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:10:22.93#ibcon#first serial, iclass 19, count 0 2006.201.13:10:22.93#ibcon#enter sib2, iclass 19, count 0 2006.201.13:10:22.93#ibcon#flushed, iclass 19, count 0 2006.201.13:10:22.93#ibcon#about to write, iclass 19, count 0 2006.201.13:10:22.93#ibcon#wrote, iclass 19, count 0 2006.201.13:10:22.93#ibcon#about to read 3, iclass 19, count 0 2006.201.13:10:22.95#ibcon#read 3, iclass 19, count 0 2006.201.13:10:22.95#ibcon#about to read 4, iclass 19, count 0 2006.201.13:10:22.95#ibcon#read 4, iclass 19, count 0 2006.201.13:10:22.95#ibcon#about to read 5, iclass 19, count 0 2006.201.13:10:22.95#ibcon#read 5, iclass 19, count 0 2006.201.13:10:22.95#ibcon#about to read 6, iclass 19, count 0 2006.201.13:10:22.95#ibcon#read 6, iclass 19, count 0 2006.201.13:10:22.95#ibcon#end of sib2, iclass 19, count 0 2006.201.13:10:22.95#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:10:22.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:10:22.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:10:22.95#ibcon#*before write, iclass 19, count 0 2006.201.13:10:22.95#ibcon#enter sib2, iclass 19, count 0 2006.201.13:10:22.95#ibcon#flushed, iclass 19, count 0 2006.201.13:10:22.95#ibcon#about to write, iclass 19, count 0 2006.201.13:10:22.95#ibcon#wrote, iclass 19, count 0 2006.201.13:10:22.95#ibcon#about to read 3, iclass 19, count 0 2006.201.13:10:22.99#ibcon#read 3, iclass 19, count 0 2006.201.13:10:22.99#ibcon#about to read 4, iclass 19, count 0 2006.201.13:10:22.99#ibcon#read 4, iclass 19, count 0 2006.201.13:10:22.99#ibcon#about to read 5, iclass 19, count 0 2006.201.13:10:22.99#ibcon#read 5, iclass 19, count 0 2006.201.13:10:22.99#ibcon#about to read 6, iclass 19, count 0 2006.201.13:10:22.99#ibcon#read 6, iclass 19, count 0 2006.201.13:10:22.99#ibcon#end of sib2, iclass 19, count 0 2006.201.13:10:22.99#ibcon#*after write, iclass 19, count 0 2006.201.13:10:22.99#ibcon#*before return 0, iclass 19, count 0 2006.201.13:10:22.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:22.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:10:22.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:10:22.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:10:22.99$vck44/vb=5,4 2006.201.13:10:22.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.13:10:22.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.13:10:22.99#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:22.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:23.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:23.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:23.05#ibcon#enter wrdev, iclass 21, count 2 2006.201.13:10:23.05#ibcon#first serial, iclass 21, count 2 2006.201.13:10:23.05#ibcon#enter sib2, iclass 21, count 2 2006.201.13:10:23.05#ibcon#flushed, iclass 21, count 2 2006.201.13:10:23.05#ibcon#about to write, iclass 21, count 2 2006.201.13:10:23.05#ibcon#wrote, iclass 21, count 2 2006.201.13:10:23.05#ibcon#about to read 3, iclass 21, count 2 2006.201.13:10:23.07#ibcon#read 3, iclass 21, count 2 2006.201.13:10:23.07#ibcon#about to read 4, iclass 21, count 2 2006.201.13:10:23.07#ibcon#read 4, iclass 21, count 2 2006.201.13:10:23.07#ibcon#about to read 5, iclass 21, count 2 2006.201.13:10:23.07#ibcon#read 5, iclass 21, count 2 2006.201.13:10:23.07#ibcon#about to read 6, iclass 21, count 2 2006.201.13:10:23.07#ibcon#read 6, iclass 21, count 2 2006.201.13:10:23.07#ibcon#end of sib2, iclass 21, count 2 2006.201.13:10:23.07#ibcon#*mode == 0, iclass 21, count 2 2006.201.13:10:23.07#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.13:10:23.07#ibcon#[27=AT05-04\r\n] 2006.201.13:10:23.07#ibcon#*before write, iclass 21, count 2 2006.201.13:10:23.07#ibcon#enter sib2, iclass 21, count 2 2006.201.13:10:23.07#ibcon#flushed, iclass 21, count 2 2006.201.13:10:23.07#ibcon#about to write, iclass 21, count 2 2006.201.13:10:23.07#ibcon#wrote, iclass 21, count 2 2006.201.13:10:23.07#ibcon#about to read 3, iclass 21, count 2 2006.201.13:10:23.10#ibcon#read 3, iclass 21, count 2 2006.201.13:10:23.10#ibcon#about to read 4, iclass 21, count 2 2006.201.13:10:23.10#ibcon#read 4, iclass 21, count 2 2006.201.13:10:23.10#ibcon#about to read 5, iclass 21, count 2 2006.201.13:10:23.10#ibcon#read 5, iclass 21, count 2 2006.201.13:10:23.10#ibcon#about to read 6, iclass 21, count 2 2006.201.13:10:23.10#ibcon#read 6, iclass 21, count 2 2006.201.13:10:23.10#ibcon#end of sib2, iclass 21, count 2 2006.201.13:10:23.10#ibcon#*after write, iclass 21, count 2 2006.201.13:10:23.10#ibcon#*before return 0, iclass 21, count 2 2006.201.13:10:23.10#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:23.10#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:10:23.10#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.13:10:23.10#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:23.10#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:23.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:23.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:23.22#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:10:23.22#ibcon#first serial, iclass 21, count 0 2006.201.13:10:23.22#ibcon#enter sib2, iclass 21, count 0 2006.201.13:10:23.22#ibcon#flushed, iclass 21, count 0 2006.201.13:10:23.22#ibcon#about to write, iclass 21, count 0 2006.201.13:10:23.22#ibcon#wrote, iclass 21, count 0 2006.201.13:10:23.22#ibcon#about to read 3, iclass 21, count 0 2006.201.13:10:23.24#ibcon#read 3, iclass 21, count 0 2006.201.13:10:23.24#ibcon#about to read 4, iclass 21, count 0 2006.201.13:10:23.24#ibcon#read 4, iclass 21, count 0 2006.201.13:10:23.24#ibcon#about to read 5, iclass 21, count 0 2006.201.13:10:23.24#ibcon#read 5, iclass 21, count 0 2006.201.13:10:23.24#ibcon#about to read 6, iclass 21, count 0 2006.201.13:10:23.24#ibcon#read 6, iclass 21, count 0 2006.201.13:10:23.24#ibcon#end of sib2, iclass 21, count 0 2006.201.13:10:23.24#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:10:23.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:10:23.24#ibcon#[27=USB\r\n] 2006.201.13:10:23.24#ibcon#*before write, iclass 21, count 0 2006.201.13:10:23.24#ibcon#enter sib2, iclass 21, count 0 2006.201.13:10:23.24#ibcon#flushed, iclass 21, count 0 2006.201.13:10:23.24#ibcon#about to write, iclass 21, count 0 2006.201.13:10:23.24#ibcon#wrote, iclass 21, count 0 2006.201.13:10:23.24#ibcon#about to read 3, iclass 21, count 0 2006.201.13:10:23.27#ibcon#read 3, iclass 21, count 0 2006.201.13:10:23.27#ibcon#about to read 4, iclass 21, count 0 2006.201.13:10:23.27#ibcon#read 4, iclass 21, count 0 2006.201.13:10:23.27#ibcon#about to read 5, iclass 21, count 0 2006.201.13:10:23.27#ibcon#read 5, iclass 21, count 0 2006.201.13:10:23.27#ibcon#about to read 6, iclass 21, count 0 2006.201.13:10:23.27#ibcon#read 6, iclass 21, count 0 2006.201.13:10:23.27#ibcon#end of sib2, iclass 21, count 0 2006.201.13:10:23.27#ibcon#*after write, iclass 21, count 0 2006.201.13:10:23.27#ibcon#*before return 0, iclass 21, count 0 2006.201.13:10:23.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:23.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:10:23.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:10:23.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:10:23.27$vck44/vblo=6,719.99 2006.201.13:10:23.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.13:10:23.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.13:10:23.27#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:23.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:23.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:23.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:23.27#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:10:23.27#ibcon#first serial, iclass 23, count 0 2006.201.13:10:23.27#ibcon#enter sib2, iclass 23, count 0 2006.201.13:10:23.27#ibcon#flushed, iclass 23, count 0 2006.201.13:10:23.27#ibcon#about to write, iclass 23, count 0 2006.201.13:10:23.27#ibcon#wrote, iclass 23, count 0 2006.201.13:10:23.27#ibcon#about to read 3, iclass 23, count 0 2006.201.13:10:23.29#ibcon#read 3, iclass 23, count 0 2006.201.13:10:23.29#ibcon#about to read 4, iclass 23, count 0 2006.201.13:10:23.29#ibcon#read 4, iclass 23, count 0 2006.201.13:10:23.29#ibcon#about to read 5, iclass 23, count 0 2006.201.13:10:23.29#ibcon#read 5, iclass 23, count 0 2006.201.13:10:23.29#ibcon#about to read 6, iclass 23, count 0 2006.201.13:10:23.29#ibcon#read 6, iclass 23, count 0 2006.201.13:10:23.29#ibcon#end of sib2, iclass 23, count 0 2006.201.13:10:23.29#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:10:23.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:10:23.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:10:23.29#ibcon#*before write, iclass 23, count 0 2006.201.13:10:23.29#ibcon#enter sib2, iclass 23, count 0 2006.201.13:10:23.29#ibcon#flushed, iclass 23, count 0 2006.201.13:10:23.29#ibcon#about to write, iclass 23, count 0 2006.201.13:10:23.29#ibcon#wrote, iclass 23, count 0 2006.201.13:10:23.29#ibcon#about to read 3, iclass 23, count 0 2006.201.13:10:23.33#ibcon#read 3, iclass 23, count 0 2006.201.13:10:23.33#ibcon#about to read 4, iclass 23, count 0 2006.201.13:10:23.33#ibcon#read 4, iclass 23, count 0 2006.201.13:10:23.33#ibcon#about to read 5, iclass 23, count 0 2006.201.13:10:23.33#ibcon#read 5, iclass 23, count 0 2006.201.13:10:23.33#ibcon#about to read 6, iclass 23, count 0 2006.201.13:10:23.33#ibcon#read 6, iclass 23, count 0 2006.201.13:10:23.33#ibcon#end of sib2, iclass 23, count 0 2006.201.13:10:23.33#ibcon#*after write, iclass 23, count 0 2006.201.13:10:23.33#ibcon#*before return 0, iclass 23, count 0 2006.201.13:10:23.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:23.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:10:23.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:10:23.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:10:23.33$vck44/vb=6,4 2006.201.13:10:23.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.13:10:23.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.13:10:23.33#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:23.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:23.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:23.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:23.39#ibcon#enter wrdev, iclass 25, count 2 2006.201.13:10:23.39#ibcon#first serial, iclass 25, count 2 2006.201.13:10:23.39#ibcon#enter sib2, iclass 25, count 2 2006.201.13:10:23.39#ibcon#flushed, iclass 25, count 2 2006.201.13:10:23.39#ibcon#about to write, iclass 25, count 2 2006.201.13:10:23.39#ibcon#wrote, iclass 25, count 2 2006.201.13:10:23.39#ibcon#about to read 3, iclass 25, count 2 2006.201.13:10:23.41#ibcon#read 3, iclass 25, count 2 2006.201.13:10:23.41#ibcon#about to read 4, iclass 25, count 2 2006.201.13:10:23.41#ibcon#read 4, iclass 25, count 2 2006.201.13:10:23.41#ibcon#about to read 5, iclass 25, count 2 2006.201.13:10:23.41#ibcon#read 5, iclass 25, count 2 2006.201.13:10:23.41#ibcon#about to read 6, iclass 25, count 2 2006.201.13:10:23.41#ibcon#read 6, iclass 25, count 2 2006.201.13:10:23.41#ibcon#end of sib2, iclass 25, count 2 2006.201.13:10:23.41#ibcon#*mode == 0, iclass 25, count 2 2006.201.13:10:23.41#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.13:10:23.41#ibcon#[27=AT06-04\r\n] 2006.201.13:10:23.41#ibcon#*before write, iclass 25, count 2 2006.201.13:10:23.41#ibcon#enter sib2, iclass 25, count 2 2006.201.13:10:23.41#ibcon#flushed, iclass 25, count 2 2006.201.13:10:23.41#ibcon#about to write, iclass 25, count 2 2006.201.13:10:23.41#ibcon#wrote, iclass 25, count 2 2006.201.13:10:23.41#ibcon#about to read 3, iclass 25, count 2 2006.201.13:10:23.44#ibcon#read 3, iclass 25, count 2 2006.201.13:10:23.44#ibcon#about to read 4, iclass 25, count 2 2006.201.13:10:23.44#ibcon#read 4, iclass 25, count 2 2006.201.13:10:23.44#ibcon#about to read 5, iclass 25, count 2 2006.201.13:10:23.44#ibcon#read 5, iclass 25, count 2 2006.201.13:10:23.44#ibcon#about to read 6, iclass 25, count 2 2006.201.13:10:23.44#ibcon#read 6, iclass 25, count 2 2006.201.13:10:23.44#ibcon#end of sib2, iclass 25, count 2 2006.201.13:10:23.44#ibcon#*after write, iclass 25, count 2 2006.201.13:10:23.44#ibcon#*before return 0, iclass 25, count 2 2006.201.13:10:23.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:23.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:10:23.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.13:10:23.44#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:23.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:23.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:23.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:23.56#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:10:23.56#ibcon#first serial, iclass 25, count 0 2006.201.13:10:23.56#ibcon#enter sib2, iclass 25, count 0 2006.201.13:10:23.56#ibcon#flushed, iclass 25, count 0 2006.201.13:10:23.56#ibcon#about to write, iclass 25, count 0 2006.201.13:10:23.56#ibcon#wrote, iclass 25, count 0 2006.201.13:10:23.56#ibcon#about to read 3, iclass 25, count 0 2006.201.13:10:23.58#ibcon#read 3, iclass 25, count 0 2006.201.13:10:23.58#ibcon#about to read 4, iclass 25, count 0 2006.201.13:10:23.58#ibcon#read 4, iclass 25, count 0 2006.201.13:10:23.58#ibcon#about to read 5, iclass 25, count 0 2006.201.13:10:23.58#ibcon#read 5, iclass 25, count 0 2006.201.13:10:23.58#ibcon#about to read 6, iclass 25, count 0 2006.201.13:10:23.58#ibcon#read 6, iclass 25, count 0 2006.201.13:10:23.58#ibcon#end of sib2, iclass 25, count 0 2006.201.13:10:23.58#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:10:23.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:10:23.58#ibcon#[27=USB\r\n] 2006.201.13:10:23.58#ibcon#*before write, iclass 25, count 0 2006.201.13:10:23.58#ibcon#enter sib2, iclass 25, count 0 2006.201.13:10:23.58#ibcon#flushed, iclass 25, count 0 2006.201.13:10:23.58#ibcon#about to write, iclass 25, count 0 2006.201.13:10:23.58#ibcon#wrote, iclass 25, count 0 2006.201.13:10:23.58#ibcon#about to read 3, iclass 25, count 0 2006.201.13:10:23.61#ibcon#read 3, iclass 25, count 0 2006.201.13:10:23.61#ibcon#about to read 4, iclass 25, count 0 2006.201.13:10:23.61#ibcon#read 4, iclass 25, count 0 2006.201.13:10:23.61#ibcon#about to read 5, iclass 25, count 0 2006.201.13:10:23.61#ibcon#read 5, iclass 25, count 0 2006.201.13:10:23.61#ibcon#about to read 6, iclass 25, count 0 2006.201.13:10:23.61#ibcon#read 6, iclass 25, count 0 2006.201.13:10:23.61#ibcon#end of sib2, iclass 25, count 0 2006.201.13:10:23.61#ibcon#*after write, iclass 25, count 0 2006.201.13:10:23.61#ibcon#*before return 0, iclass 25, count 0 2006.201.13:10:23.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:23.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:10:23.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:10:23.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:10:23.61$vck44/vblo=7,734.99 2006.201.13:10:23.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.13:10:23.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.13:10:23.61#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:23.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:23.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:23.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:23.61#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:10:23.61#ibcon#first serial, iclass 27, count 0 2006.201.13:10:23.61#ibcon#enter sib2, iclass 27, count 0 2006.201.13:10:23.61#ibcon#flushed, iclass 27, count 0 2006.201.13:10:23.61#ibcon#about to write, iclass 27, count 0 2006.201.13:10:23.61#ibcon#wrote, iclass 27, count 0 2006.201.13:10:23.61#ibcon#about to read 3, iclass 27, count 0 2006.201.13:10:23.63#ibcon#read 3, iclass 27, count 0 2006.201.13:10:23.63#ibcon#about to read 4, iclass 27, count 0 2006.201.13:10:23.63#ibcon#read 4, iclass 27, count 0 2006.201.13:10:23.63#ibcon#about to read 5, iclass 27, count 0 2006.201.13:10:23.63#ibcon#read 5, iclass 27, count 0 2006.201.13:10:23.63#ibcon#about to read 6, iclass 27, count 0 2006.201.13:10:23.63#ibcon#read 6, iclass 27, count 0 2006.201.13:10:23.63#ibcon#end of sib2, iclass 27, count 0 2006.201.13:10:23.63#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:10:23.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:10:23.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:10:23.63#ibcon#*before write, iclass 27, count 0 2006.201.13:10:23.63#ibcon#enter sib2, iclass 27, count 0 2006.201.13:10:23.63#ibcon#flushed, iclass 27, count 0 2006.201.13:10:23.63#ibcon#about to write, iclass 27, count 0 2006.201.13:10:23.63#ibcon#wrote, iclass 27, count 0 2006.201.13:10:23.63#ibcon#about to read 3, iclass 27, count 0 2006.201.13:10:23.68#ibcon#read 3, iclass 27, count 0 2006.201.13:10:23.68#ibcon#about to read 4, iclass 27, count 0 2006.201.13:10:23.68#ibcon#read 4, iclass 27, count 0 2006.201.13:10:23.68#ibcon#about to read 5, iclass 27, count 0 2006.201.13:10:23.68#ibcon#read 5, iclass 27, count 0 2006.201.13:10:23.68#ibcon#about to read 6, iclass 27, count 0 2006.201.13:10:23.68#ibcon#read 6, iclass 27, count 0 2006.201.13:10:23.68#ibcon#end of sib2, iclass 27, count 0 2006.201.13:10:23.68#ibcon#*after write, iclass 27, count 0 2006.201.13:10:23.68#ibcon#*before return 0, iclass 27, count 0 2006.201.13:10:23.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:23.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:10:23.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:10:23.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:10:23.68$vck44/vb=7,4 2006.201.13:10:23.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.13:10:23.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.13:10:23.68#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:23.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:23.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:23.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:23.73#ibcon#enter wrdev, iclass 29, count 2 2006.201.13:10:23.73#ibcon#first serial, iclass 29, count 2 2006.201.13:10:23.73#ibcon#enter sib2, iclass 29, count 2 2006.201.13:10:23.73#ibcon#flushed, iclass 29, count 2 2006.201.13:10:23.73#ibcon#about to write, iclass 29, count 2 2006.201.13:10:23.73#ibcon#wrote, iclass 29, count 2 2006.201.13:10:23.73#ibcon#about to read 3, iclass 29, count 2 2006.201.13:10:23.75#ibcon#read 3, iclass 29, count 2 2006.201.13:10:23.75#ibcon#about to read 4, iclass 29, count 2 2006.201.13:10:23.75#ibcon#read 4, iclass 29, count 2 2006.201.13:10:23.75#ibcon#about to read 5, iclass 29, count 2 2006.201.13:10:23.75#ibcon#read 5, iclass 29, count 2 2006.201.13:10:23.75#ibcon#about to read 6, iclass 29, count 2 2006.201.13:10:23.75#ibcon#read 6, iclass 29, count 2 2006.201.13:10:23.75#ibcon#end of sib2, iclass 29, count 2 2006.201.13:10:23.75#ibcon#*mode == 0, iclass 29, count 2 2006.201.13:10:23.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.13:10:23.75#ibcon#[27=AT07-04\r\n] 2006.201.13:10:23.75#ibcon#*before write, iclass 29, count 2 2006.201.13:10:23.75#ibcon#enter sib2, iclass 29, count 2 2006.201.13:10:23.75#ibcon#flushed, iclass 29, count 2 2006.201.13:10:23.75#ibcon#about to write, iclass 29, count 2 2006.201.13:10:23.75#ibcon#wrote, iclass 29, count 2 2006.201.13:10:23.75#ibcon#about to read 3, iclass 29, count 2 2006.201.13:10:23.78#ibcon#read 3, iclass 29, count 2 2006.201.13:10:23.78#ibcon#about to read 4, iclass 29, count 2 2006.201.13:10:23.78#ibcon#read 4, iclass 29, count 2 2006.201.13:10:23.78#ibcon#about to read 5, iclass 29, count 2 2006.201.13:10:23.78#ibcon#read 5, iclass 29, count 2 2006.201.13:10:23.78#ibcon#about to read 6, iclass 29, count 2 2006.201.13:10:23.78#ibcon#read 6, iclass 29, count 2 2006.201.13:10:23.78#ibcon#end of sib2, iclass 29, count 2 2006.201.13:10:23.78#ibcon#*after write, iclass 29, count 2 2006.201.13:10:23.78#ibcon#*before return 0, iclass 29, count 2 2006.201.13:10:23.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:23.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:10:23.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.13:10:23.78#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:23.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:23.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:23.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:23.90#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:10:23.90#ibcon#first serial, iclass 29, count 0 2006.201.13:10:23.90#ibcon#enter sib2, iclass 29, count 0 2006.201.13:10:23.90#ibcon#flushed, iclass 29, count 0 2006.201.13:10:23.90#ibcon#about to write, iclass 29, count 0 2006.201.13:10:23.90#ibcon#wrote, iclass 29, count 0 2006.201.13:10:23.90#ibcon#about to read 3, iclass 29, count 0 2006.201.13:10:23.92#ibcon#read 3, iclass 29, count 0 2006.201.13:10:23.92#ibcon#about to read 4, iclass 29, count 0 2006.201.13:10:23.92#ibcon#read 4, iclass 29, count 0 2006.201.13:10:23.92#ibcon#about to read 5, iclass 29, count 0 2006.201.13:10:23.92#ibcon#read 5, iclass 29, count 0 2006.201.13:10:23.92#ibcon#about to read 6, iclass 29, count 0 2006.201.13:10:23.92#ibcon#read 6, iclass 29, count 0 2006.201.13:10:23.92#ibcon#end of sib2, iclass 29, count 0 2006.201.13:10:23.92#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:10:23.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:10:23.92#ibcon#[27=USB\r\n] 2006.201.13:10:23.92#ibcon#*before write, iclass 29, count 0 2006.201.13:10:23.92#ibcon#enter sib2, iclass 29, count 0 2006.201.13:10:23.92#ibcon#flushed, iclass 29, count 0 2006.201.13:10:23.92#ibcon#about to write, iclass 29, count 0 2006.201.13:10:23.92#ibcon#wrote, iclass 29, count 0 2006.201.13:10:23.92#ibcon#about to read 3, iclass 29, count 0 2006.201.13:10:23.95#ibcon#read 3, iclass 29, count 0 2006.201.13:10:23.95#ibcon#about to read 4, iclass 29, count 0 2006.201.13:10:23.95#ibcon#read 4, iclass 29, count 0 2006.201.13:10:23.95#ibcon#about to read 5, iclass 29, count 0 2006.201.13:10:23.95#ibcon#read 5, iclass 29, count 0 2006.201.13:10:23.95#ibcon#about to read 6, iclass 29, count 0 2006.201.13:10:23.95#ibcon#read 6, iclass 29, count 0 2006.201.13:10:23.95#ibcon#end of sib2, iclass 29, count 0 2006.201.13:10:23.95#ibcon#*after write, iclass 29, count 0 2006.201.13:10:23.95#ibcon#*before return 0, iclass 29, count 0 2006.201.13:10:23.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:23.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:10:23.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:10:23.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:10:23.95$vck44/vblo=8,744.99 2006.201.13:10:23.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.13:10:23.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.13:10:23.95#ibcon#ireg 17 cls_cnt 0 2006.201.13:10:23.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:23.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:23.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:23.95#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:10:23.95#ibcon#first serial, iclass 31, count 0 2006.201.13:10:23.95#ibcon#enter sib2, iclass 31, count 0 2006.201.13:10:23.95#ibcon#flushed, iclass 31, count 0 2006.201.13:10:23.95#ibcon#about to write, iclass 31, count 0 2006.201.13:10:23.95#ibcon#wrote, iclass 31, count 0 2006.201.13:10:23.95#ibcon#about to read 3, iclass 31, count 0 2006.201.13:10:23.97#ibcon#read 3, iclass 31, count 0 2006.201.13:10:23.97#ibcon#about to read 4, iclass 31, count 0 2006.201.13:10:23.97#ibcon#read 4, iclass 31, count 0 2006.201.13:10:23.97#ibcon#about to read 5, iclass 31, count 0 2006.201.13:10:23.97#ibcon#read 5, iclass 31, count 0 2006.201.13:10:23.97#ibcon#about to read 6, iclass 31, count 0 2006.201.13:10:23.97#ibcon#read 6, iclass 31, count 0 2006.201.13:10:23.97#ibcon#end of sib2, iclass 31, count 0 2006.201.13:10:23.97#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:10:23.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:10:23.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:10:23.97#ibcon#*before write, iclass 31, count 0 2006.201.13:10:23.97#ibcon#enter sib2, iclass 31, count 0 2006.201.13:10:23.97#ibcon#flushed, iclass 31, count 0 2006.201.13:10:23.97#ibcon#about to write, iclass 31, count 0 2006.201.13:10:23.97#ibcon#wrote, iclass 31, count 0 2006.201.13:10:23.97#ibcon#about to read 3, iclass 31, count 0 2006.201.13:10:24.01#ibcon#read 3, iclass 31, count 0 2006.201.13:10:24.01#ibcon#about to read 4, iclass 31, count 0 2006.201.13:10:24.01#ibcon#read 4, iclass 31, count 0 2006.201.13:10:24.01#ibcon#about to read 5, iclass 31, count 0 2006.201.13:10:24.01#ibcon#read 5, iclass 31, count 0 2006.201.13:10:24.01#ibcon#about to read 6, iclass 31, count 0 2006.201.13:10:24.01#ibcon#read 6, iclass 31, count 0 2006.201.13:10:24.01#ibcon#end of sib2, iclass 31, count 0 2006.201.13:10:24.01#ibcon#*after write, iclass 31, count 0 2006.201.13:10:24.01#ibcon#*before return 0, iclass 31, count 0 2006.201.13:10:24.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:24.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:10:24.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:10:24.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:10:24.01$vck44/vb=8,4 2006.201.13:10:24.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.13:10:24.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.13:10:24.01#ibcon#ireg 11 cls_cnt 2 2006.201.13:10:24.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:24.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:24.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:24.07#ibcon#enter wrdev, iclass 33, count 2 2006.201.13:10:24.07#ibcon#first serial, iclass 33, count 2 2006.201.13:10:24.07#ibcon#enter sib2, iclass 33, count 2 2006.201.13:10:24.07#ibcon#flushed, iclass 33, count 2 2006.201.13:10:24.07#ibcon#about to write, iclass 33, count 2 2006.201.13:10:24.07#ibcon#wrote, iclass 33, count 2 2006.201.13:10:24.07#ibcon#about to read 3, iclass 33, count 2 2006.201.13:10:24.09#ibcon#read 3, iclass 33, count 2 2006.201.13:10:24.09#ibcon#about to read 4, iclass 33, count 2 2006.201.13:10:24.09#ibcon#read 4, iclass 33, count 2 2006.201.13:10:24.09#ibcon#about to read 5, iclass 33, count 2 2006.201.13:10:24.09#ibcon#read 5, iclass 33, count 2 2006.201.13:10:24.09#ibcon#about to read 6, iclass 33, count 2 2006.201.13:10:24.09#ibcon#read 6, iclass 33, count 2 2006.201.13:10:24.09#ibcon#end of sib2, iclass 33, count 2 2006.201.13:10:24.09#ibcon#*mode == 0, iclass 33, count 2 2006.201.13:10:24.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.13:10:24.09#ibcon#[27=AT08-04\r\n] 2006.201.13:10:24.09#ibcon#*before write, iclass 33, count 2 2006.201.13:10:24.09#ibcon#enter sib2, iclass 33, count 2 2006.201.13:10:24.09#ibcon#flushed, iclass 33, count 2 2006.201.13:10:24.09#ibcon#about to write, iclass 33, count 2 2006.201.13:10:24.09#ibcon#wrote, iclass 33, count 2 2006.201.13:10:24.09#ibcon#about to read 3, iclass 33, count 2 2006.201.13:10:24.12#ibcon#read 3, iclass 33, count 2 2006.201.13:10:24.12#ibcon#about to read 4, iclass 33, count 2 2006.201.13:10:24.12#ibcon#read 4, iclass 33, count 2 2006.201.13:10:24.12#ibcon#about to read 5, iclass 33, count 2 2006.201.13:10:24.12#ibcon#read 5, iclass 33, count 2 2006.201.13:10:24.12#ibcon#about to read 6, iclass 33, count 2 2006.201.13:10:24.12#ibcon#read 6, iclass 33, count 2 2006.201.13:10:24.12#ibcon#end of sib2, iclass 33, count 2 2006.201.13:10:24.12#ibcon#*after write, iclass 33, count 2 2006.201.13:10:24.12#ibcon#*before return 0, iclass 33, count 2 2006.201.13:10:24.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:24.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:10:24.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.13:10:24.12#ibcon#ireg 7 cls_cnt 0 2006.201.13:10:24.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:24.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:24.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:24.24#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:10:24.24#ibcon#first serial, iclass 33, count 0 2006.201.13:10:24.24#ibcon#enter sib2, iclass 33, count 0 2006.201.13:10:24.24#ibcon#flushed, iclass 33, count 0 2006.201.13:10:24.24#ibcon#about to write, iclass 33, count 0 2006.201.13:10:24.24#ibcon#wrote, iclass 33, count 0 2006.201.13:10:24.24#ibcon#about to read 3, iclass 33, count 0 2006.201.13:10:24.26#ibcon#read 3, iclass 33, count 0 2006.201.13:10:24.26#ibcon#about to read 4, iclass 33, count 0 2006.201.13:10:24.26#ibcon#read 4, iclass 33, count 0 2006.201.13:10:24.26#ibcon#about to read 5, iclass 33, count 0 2006.201.13:10:24.26#ibcon#read 5, iclass 33, count 0 2006.201.13:10:24.26#ibcon#about to read 6, iclass 33, count 0 2006.201.13:10:24.26#ibcon#read 6, iclass 33, count 0 2006.201.13:10:24.26#ibcon#end of sib2, iclass 33, count 0 2006.201.13:10:24.26#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:10:24.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:10:24.26#ibcon#[27=USB\r\n] 2006.201.13:10:24.26#ibcon#*before write, iclass 33, count 0 2006.201.13:10:24.26#ibcon#enter sib2, iclass 33, count 0 2006.201.13:10:24.26#ibcon#flushed, iclass 33, count 0 2006.201.13:10:24.26#ibcon#about to write, iclass 33, count 0 2006.201.13:10:24.26#ibcon#wrote, iclass 33, count 0 2006.201.13:10:24.26#ibcon#about to read 3, iclass 33, count 0 2006.201.13:10:24.29#ibcon#read 3, iclass 33, count 0 2006.201.13:10:24.29#ibcon#about to read 4, iclass 33, count 0 2006.201.13:10:24.29#ibcon#read 4, iclass 33, count 0 2006.201.13:10:24.29#ibcon#about to read 5, iclass 33, count 0 2006.201.13:10:24.29#ibcon#read 5, iclass 33, count 0 2006.201.13:10:24.29#ibcon#about to read 6, iclass 33, count 0 2006.201.13:10:24.29#ibcon#read 6, iclass 33, count 0 2006.201.13:10:24.29#ibcon#end of sib2, iclass 33, count 0 2006.201.13:10:24.29#ibcon#*after write, iclass 33, count 0 2006.201.13:10:24.29#ibcon#*before return 0, iclass 33, count 0 2006.201.13:10:24.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:24.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:10:24.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:10:24.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:10:24.29$vck44/vabw=wide 2006.201.13:10:24.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.13:10:24.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.13:10:24.29#ibcon#ireg 8 cls_cnt 0 2006.201.13:10:24.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:24.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:24.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:24.29#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:10:24.29#ibcon#first serial, iclass 35, count 0 2006.201.13:10:24.29#ibcon#enter sib2, iclass 35, count 0 2006.201.13:10:24.29#ibcon#flushed, iclass 35, count 0 2006.201.13:10:24.29#ibcon#about to write, iclass 35, count 0 2006.201.13:10:24.29#ibcon#wrote, iclass 35, count 0 2006.201.13:10:24.29#ibcon#about to read 3, iclass 35, count 0 2006.201.13:10:24.31#ibcon#read 3, iclass 35, count 0 2006.201.13:10:24.31#ibcon#about to read 4, iclass 35, count 0 2006.201.13:10:24.31#ibcon#read 4, iclass 35, count 0 2006.201.13:10:24.31#ibcon#about to read 5, iclass 35, count 0 2006.201.13:10:24.31#ibcon#read 5, iclass 35, count 0 2006.201.13:10:24.31#ibcon#about to read 6, iclass 35, count 0 2006.201.13:10:24.31#ibcon#read 6, iclass 35, count 0 2006.201.13:10:24.31#ibcon#end of sib2, iclass 35, count 0 2006.201.13:10:24.31#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:10:24.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:10:24.31#ibcon#[25=BW32\r\n] 2006.201.13:10:24.31#ibcon#*before write, iclass 35, count 0 2006.201.13:10:24.31#ibcon#enter sib2, iclass 35, count 0 2006.201.13:10:24.31#ibcon#flushed, iclass 35, count 0 2006.201.13:10:24.31#ibcon#about to write, iclass 35, count 0 2006.201.13:10:24.31#ibcon#wrote, iclass 35, count 0 2006.201.13:10:24.31#ibcon#about to read 3, iclass 35, count 0 2006.201.13:10:24.34#ibcon#read 3, iclass 35, count 0 2006.201.13:10:24.34#ibcon#about to read 4, iclass 35, count 0 2006.201.13:10:24.34#ibcon#read 4, iclass 35, count 0 2006.201.13:10:24.34#ibcon#about to read 5, iclass 35, count 0 2006.201.13:10:24.34#ibcon#read 5, iclass 35, count 0 2006.201.13:10:24.34#ibcon#about to read 6, iclass 35, count 0 2006.201.13:10:24.34#ibcon#read 6, iclass 35, count 0 2006.201.13:10:24.34#ibcon#end of sib2, iclass 35, count 0 2006.201.13:10:24.34#ibcon#*after write, iclass 35, count 0 2006.201.13:10:24.34#ibcon#*before return 0, iclass 35, count 0 2006.201.13:10:24.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:24.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:10:24.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:10:24.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:10:24.34$vck44/vbbw=wide 2006.201.13:10:24.34#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.13:10:24.34#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.13:10:24.34#ibcon#ireg 8 cls_cnt 0 2006.201.13:10:24.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:10:24.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:10:24.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:10:24.41#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:10:24.41#ibcon#first serial, iclass 37, count 0 2006.201.13:10:24.41#ibcon#enter sib2, iclass 37, count 0 2006.201.13:10:24.41#ibcon#flushed, iclass 37, count 0 2006.201.13:10:24.41#ibcon#about to write, iclass 37, count 0 2006.201.13:10:24.41#ibcon#wrote, iclass 37, count 0 2006.201.13:10:24.41#ibcon#about to read 3, iclass 37, count 0 2006.201.13:10:24.43#ibcon#read 3, iclass 37, count 0 2006.201.13:10:24.43#ibcon#about to read 4, iclass 37, count 0 2006.201.13:10:24.43#ibcon#read 4, iclass 37, count 0 2006.201.13:10:24.43#ibcon#about to read 5, iclass 37, count 0 2006.201.13:10:24.43#ibcon#read 5, iclass 37, count 0 2006.201.13:10:24.43#ibcon#about to read 6, iclass 37, count 0 2006.201.13:10:24.43#ibcon#read 6, iclass 37, count 0 2006.201.13:10:24.43#ibcon#end of sib2, iclass 37, count 0 2006.201.13:10:24.43#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:10:24.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:10:24.43#ibcon#[27=BW32\r\n] 2006.201.13:10:24.43#ibcon#*before write, iclass 37, count 0 2006.201.13:10:24.43#ibcon#enter sib2, iclass 37, count 0 2006.201.13:10:24.43#ibcon#flushed, iclass 37, count 0 2006.201.13:10:24.43#ibcon#about to write, iclass 37, count 0 2006.201.13:10:24.43#ibcon#wrote, iclass 37, count 0 2006.201.13:10:24.43#ibcon#about to read 3, iclass 37, count 0 2006.201.13:10:24.46#ibcon#read 3, iclass 37, count 0 2006.201.13:10:24.46#ibcon#about to read 4, iclass 37, count 0 2006.201.13:10:24.46#ibcon#read 4, iclass 37, count 0 2006.201.13:10:24.46#ibcon#about to read 5, iclass 37, count 0 2006.201.13:10:24.46#ibcon#read 5, iclass 37, count 0 2006.201.13:10:24.46#ibcon#about to read 6, iclass 37, count 0 2006.201.13:10:24.46#ibcon#read 6, iclass 37, count 0 2006.201.13:10:24.46#ibcon#end of sib2, iclass 37, count 0 2006.201.13:10:24.46#ibcon#*after write, iclass 37, count 0 2006.201.13:10:24.46#ibcon#*before return 0, iclass 37, count 0 2006.201.13:10:24.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:10:24.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:10:24.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:10:24.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:10:24.46$setupk4/ifdk4 2006.201.13:10:24.46$ifdk4/lo= 2006.201.13:10:24.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:10:24.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:10:24.46$ifdk4/patch= 2006.201.13:10:24.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:10:24.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:10:24.46$setupk4/!*+20s 2006.201.13:10:28.84#abcon#<5=/04 1.3 2.3 20.991001003.9\r\n> 2006.201.13:10:28.86#abcon#{5=INTERFACE CLEAR} 2006.201.13:10:28.92#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:10:38.95$setupk4/"tpicd 2006.201.13:10:38.95$setupk4/echo=off 2006.201.13:10:38.95$setupk4/xlog=off 2006.201.13:10:38.95:!2006.201.13:14:06 2006.201.13:10:53.14#trakl#Source acquired 2006.201.13:10:54.14#flagr#flagr/antenna,acquired 2006.201.13:14:06.00:preob 2006.201.13:14:07.13/onsource/TRACKING 2006.201.13:14:07.13:!2006.201.13:14:16 2006.201.13:14:16.00:"tape 2006.201.13:14:16.00:"st=record 2006.201.13:14:16.00:data_valid=on 2006.201.13:14:16.00:midob 2006.201.13:14:16.13/onsource/TRACKING 2006.201.13:14:16.13/wx/20.97,1004.0,100 2006.201.13:14:16.25/cable/+6.4735E-03 2006.201.13:14:17.34/va/01,08,usb,yes,28,30 2006.201.13:14:17.34/va/02,07,usb,yes,30,31 2006.201.13:14:17.34/va/03,08,usb,yes,27,28 2006.201.13:14:17.34/va/04,07,usb,yes,31,33 2006.201.13:14:17.34/va/05,04,usb,yes,27,28 2006.201.13:14:17.34/va/06,05,usb,yes,27,27 2006.201.13:14:17.34/va/07,05,usb,yes,27,28 2006.201.13:14:17.34/va/08,04,usb,yes,27,32 2006.201.13:14:17.57/valo/01,524.99,yes,locked 2006.201.13:14:17.57/valo/02,534.99,yes,locked 2006.201.13:14:17.57/valo/03,564.99,yes,locked 2006.201.13:14:17.57/valo/04,624.99,yes,locked 2006.201.13:14:17.57/valo/05,734.99,yes,locked 2006.201.13:14:17.57/valo/06,814.99,yes,locked 2006.201.13:14:17.57/valo/07,864.99,yes,locked 2006.201.13:14:17.57/valo/08,884.99,yes,locked 2006.201.13:14:18.66/vb/01,04,usb,yes,28,26 2006.201.13:14:18.66/vb/02,05,usb,yes,27,27 2006.201.13:14:18.66/vb/03,04,usb,yes,28,30 2006.201.13:14:18.66/vb/04,05,usb,yes,28,27 2006.201.13:14:18.66/vb/05,04,usb,yes,24,27 2006.201.13:14:18.66/vb/06,04,usb,yes,29,25 2006.201.13:14:18.66/vb/07,04,usb,yes,29,28 2006.201.13:14:18.66/vb/08,04,usb,yes,26,29 2006.201.13:14:18.89/vblo/01,629.99,yes,locked 2006.201.13:14:18.89/vblo/02,634.99,yes,locked 2006.201.13:14:18.89/vblo/03,649.99,yes,locked 2006.201.13:14:18.89/vblo/04,679.99,yes,locked 2006.201.13:14:18.89/vblo/05,709.99,yes,locked 2006.201.13:14:18.89/vblo/06,719.99,yes,locked 2006.201.13:14:18.89/vblo/07,734.99,yes,locked 2006.201.13:14:18.89/vblo/08,744.99,yes,locked 2006.201.13:14:19.04/vabw/8 2006.201.13:14:19.19/vbbw/8 2006.201.13:14:19.28/xfe/off,on,15.0 2006.201.13:14:19.66/ifatt/23,28,28,28 2006.201.13:14:20.05/fmout-gps/S +4.53E-07 2006.201.13:14:20.12:!2006.201.13:16:26 2006.201.13:16:26.00:data_valid=off 2006.201.13:16:26.00:"et 2006.201.13:16:26.00:!+3s 2006.201.13:16:29.02:"tape 2006.201.13:16:29.02:postob 2006.201.13:16:29.20/cable/+6.4731E-03 2006.201.13:16:29.20/wx/20.96,1004.0,100 2006.201.13:16:29.28/fmout-gps/S +4.52E-07 2006.201.13:16:29.28:scan_name=201-1323,jd0607,220 2006.201.13:16:29.28:source=0014+813,001708.47,813508.1,2000.0,cw 2006.201.13:16:31.14#flagr#flagr/antenna,new-source 2006.201.13:16:31.14:checkk5 2006.201.13:16:31.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:16:31.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:16:32.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:16:32.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:16:33.00/chk_obsdata//k5ts1/T2011314??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.13:16:33.37/chk_obsdata//k5ts2/T2011314??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.13:16:33.73/chk_obsdata//k5ts3/T2011314??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.13:16:34.10/chk_obsdata//k5ts4/T2011314??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.13:16:34.79/k5log//k5ts1_log_newline 2006.201.13:16:35.50/k5log//k5ts2_log_newline 2006.201.13:16:36.19/k5log//k5ts3_log_newline 2006.201.13:16:36.88/k5log//k5ts4_log_newline 2006.201.13:16:36.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:16:36.91:setupk4=1 2006.201.13:16:36.91$setupk4/echo=on 2006.201.13:16:36.91$setupk4/pcalon 2006.201.13:16:36.91$pcalon/"no phase cal control is implemented here 2006.201.13:16:36.91$setupk4/"tpicd=stop 2006.201.13:16:36.91$setupk4/"rec=synch_on 2006.201.13:16:36.91$setupk4/"rec_mode=128 2006.201.13:16:36.91$setupk4/!* 2006.201.13:16:36.91$setupk4/recpk4 2006.201.13:16:36.91$recpk4/recpatch= 2006.201.13:16:36.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:16:36.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:16:36.91$setupk4/vck44 2006.201.13:16:36.91$vck44/valo=1,524.99 2006.201.13:16:36.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.13:16:36.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.13:16:36.91#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:36.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:16:36.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:16:36.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:16:36.91#ibcon#enter wrdev, iclass 39, count 0 2006.201.13:16:36.91#ibcon#first serial, iclass 39, count 0 2006.201.13:16:36.91#ibcon#enter sib2, iclass 39, count 0 2006.201.13:16:36.91#ibcon#flushed, iclass 39, count 0 2006.201.13:16:36.91#ibcon#about to write, iclass 39, count 0 2006.201.13:16:36.91#ibcon#wrote, iclass 39, count 0 2006.201.13:16:36.91#ibcon#about to read 3, iclass 39, count 0 2006.201.13:16:36.93#ibcon#read 3, iclass 39, count 0 2006.201.13:16:36.93#ibcon#about to read 4, iclass 39, count 0 2006.201.13:16:36.93#ibcon#read 4, iclass 39, count 0 2006.201.13:16:36.93#ibcon#about to read 5, iclass 39, count 0 2006.201.13:16:36.93#ibcon#read 5, iclass 39, count 0 2006.201.13:16:36.93#ibcon#about to read 6, iclass 39, count 0 2006.201.13:16:36.93#ibcon#read 6, iclass 39, count 0 2006.201.13:16:36.93#ibcon#end of sib2, iclass 39, count 0 2006.201.13:16:36.93#ibcon#*mode == 0, iclass 39, count 0 2006.201.13:16:36.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.13:16:36.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:16:36.93#ibcon#*before write, iclass 39, count 0 2006.201.13:16:36.93#ibcon#enter sib2, iclass 39, count 0 2006.201.13:16:36.93#ibcon#flushed, iclass 39, count 0 2006.201.13:16:36.93#ibcon#about to write, iclass 39, count 0 2006.201.13:16:36.93#ibcon#wrote, iclass 39, count 0 2006.201.13:16:36.93#ibcon#about to read 3, iclass 39, count 0 2006.201.13:16:36.98#ibcon#read 3, iclass 39, count 0 2006.201.13:16:36.98#ibcon#about to read 4, iclass 39, count 0 2006.201.13:16:36.98#ibcon#read 4, iclass 39, count 0 2006.201.13:16:36.98#ibcon#about to read 5, iclass 39, count 0 2006.201.13:16:36.98#ibcon#read 5, iclass 39, count 0 2006.201.13:16:36.98#ibcon#about to read 6, iclass 39, count 0 2006.201.13:16:36.98#ibcon#read 6, iclass 39, count 0 2006.201.13:16:36.98#ibcon#end of sib2, iclass 39, count 0 2006.201.13:16:36.98#ibcon#*after write, iclass 39, count 0 2006.201.13:16:36.98#ibcon#*before return 0, iclass 39, count 0 2006.201.13:16:36.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:16:36.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:16:36.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.13:16:36.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.13:16:36.98$vck44/va=1,8 2006.201.13:16:36.98#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.13:16:36.98#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.13:16:36.98#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:36.98#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:16:36.98#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:16:36.98#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:16:36.98#ibcon#enter wrdev, iclass 2, count 2 2006.201.13:16:36.98#ibcon#first serial, iclass 2, count 2 2006.201.13:16:36.98#ibcon#enter sib2, iclass 2, count 2 2006.201.13:16:36.98#ibcon#flushed, iclass 2, count 2 2006.201.13:16:36.98#ibcon#about to write, iclass 2, count 2 2006.201.13:16:36.98#ibcon#wrote, iclass 2, count 2 2006.201.13:16:36.98#ibcon#about to read 3, iclass 2, count 2 2006.201.13:16:37.00#ibcon#read 3, iclass 2, count 2 2006.201.13:16:37.00#ibcon#about to read 4, iclass 2, count 2 2006.201.13:16:37.00#ibcon#read 4, iclass 2, count 2 2006.201.13:16:37.00#ibcon#about to read 5, iclass 2, count 2 2006.201.13:16:37.00#ibcon#read 5, iclass 2, count 2 2006.201.13:16:37.00#ibcon#about to read 6, iclass 2, count 2 2006.201.13:16:37.00#ibcon#read 6, iclass 2, count 2 2006.201.13:16:37.00#ibcon#end of sib2, iclass 2, count 2 2006.201.13:16:37.00#ibcon#*mode == 0, iclass 2, count 2 2006.201.13:16:37.00#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.13:16:37.00#ibcon#[25=AT01-08\r\n] 2006.201.13:16:37.00#ibcon#*before write, iclass 2, count 2 2006.201.13:16:37.00#ibcon#enter sib2, iclass 2, count 2 2006.201.13:16:37.00#ibcon#flushed, iclass 2, count 2 2006.201.13:16:37.00#ibcon#about to write, iclass 2, count 2 2006.201.13:16:37.00#ibcon#wrote, iclass 2, count 2 2006.201.13:16:37.00#ibcon#about to read 3, iclass 2, count 2 2006.201.13:16:37.03#ibcon#read 3, iclass 2, count 2 2006.201.13:16:37.03#ibcon#about to read 4, iclass 2, count 2 2006.201.13:16:37.03#ibcon#read 4, iclass 2, count 2 2006.201.13:16:37.03#ibcon#about to read 5, iclass 2, count 2 2006.201.13:16:37.03#ibcon#read 5, iclass 2, count 2 2006.201.13:16:37.03#ibcon#about to read 6, iclass 2, count 2 2006.201.13:16:37.03#ibcon#read 6, iclass 2, count 2 2006.201.13:16:37.03#ibcon#end of sib2, iclass 2, count 2 2006.201.13:16:37.03#ibcon#*after write, iclass 2, count 2 2006.201.13:16:37.03#ibcon#*before return 0, iclass 2, count 2 2006.201.13:16:37.03#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:16:37.03#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:16:37.03#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.13:16:37.03#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:37.03#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:16:37.15#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:16:37.15#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:16:37.15#ibcon#enter wrdev, iclass 2, count 0 2006.201.13:16:37.15#ibcon#first serial, iclass 2, count 0 2006.201.13:16:37.15#ibcon#enter sib2, iclass 2, count 0 2006.201.13:16:37.15#ibcon#flushed, iclass 2, count 0 2006.201.13:16:37.15#ibcon#about to write, iclass 2, count 0 2006.201.13:16:37.15#ibcon#wrote, iclass 2, count 0 2006.201.13:16:37.15#ibcon#about to read 3, iclass 2, count 0 2006.201.13:16:37.17#ibcon#read 3, iclass 2, count 0 2006.201.13:16:37.17#ibcon#about to read 4, iclass 2, count 0 2006.201.13:16:37.17#ibcon#read 4, iclass 2, count 0 2006.201.13:16:37.17#ibcon#about to read 5, iclass 2, count 0 2006.201.13:16:37.17#ibcon#read 5, iclass 2, count 0 2006.201.13:16:37.17#ibcon#about to read 6, iclass 2, count 0 2006.201.13:16:37.17#ibcon#read 6, iclass 2, count 0 2006.201.13:16:37.17#ibcon#end of sib2, iclass 2, count 0 2006.201.13:16:37.17#ibcon#*mode == 0, iclass 2, count 0 2006.201.13:16:37.17#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.13:16:37.17#ibcon#[25=USB\r\n] 2006.201.13:16:37.17#ibcon#*before write, iclass 2, count 0 2006.201.13:16:37.17#ibcon#enter sib2, iclass 2, count 0 2006.201.13:16:37.17#ibcon#flushed, iclass 2, count 0 2006.201.13:16:37.17#ibcon#about to write, iclass 2, count 0 2006.201.13:16:37.17#ibcon#wrote, iclass 2, count 0 2006.201.13:16:37.17#ibcon#about to read 3, iclass 2, count 0 2006.201.13:16:37.20#ibcon#read 3, iclass 2, count 0 2006.201.13:16:37.20#ibcon#about to read 4, iclass 2, count 0 2006.201.13:16:37.20#ibcon#read 4, iclass 2, count 0 2006.201.13:16:37.20#ibcon#about to read 5, iclass 2, count 0 2006.201.13:16:37.20#ibcon#read 5, iclass 2, count 0 2006.201.13:16:37.20#ibcon#about to read 6, iclass 2, count 0 2006.201.13:16:37.20#ibcon#read 6, iclass 2, count 0 2006.201.13:16:37.20#ibcon#end of sib2, iclass 2, count 0 2006.201.13:16:37.20#ibcon#*after write, iclass 2, count 0 2006.201.13:16:37.20#ibcon#*before return 0, iclass 2, count 0 2006.201.13:16:37.20#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:16:37.20#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:16:37.20#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.13:16:37.20#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.13:16:37.20$vck44/valo=2,534.99 2006.201.13:16:37.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.13:16:37.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.13:16:37.20#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:37.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:16:37.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:16:37.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:16:37.20#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:16:37.20#ibcon#first serial, iclass 5, count 0 2006.201.13:16:37.20#ibcon#enter sib2, iclass 5, count 0 2006.201.13:16:37.20#ibcon#flushed, iclass 5, count 0 2006.201.13:16:37.20#ibcon#about to write, iclass 5, count 0 2006.201.13:16:37.20#ibcon#wrote, iclass 5, count 0 2006.201.13:16:37.20#ibcon#about to read 3, iclass 5, count 0 2006.201.13:16:37.22#ibcon#read 3, iclass 5, count 0 2006.201.13:16:37.22#ibcon#about to read 4, iclass 5, count 0 2006.201.13:16:37.22#ibcon#read 4, iclass 5, count 0 2006.201.13:16:37.22#ibcon#about to read 5, iclass 5, count 0 2006.201.13:16:37.22#ibcon#read 5, iclass 5, count 0 2006.201.13:16:37.22#ibcon#about to read 6, iclass 5, count 0 2006.201.13:16:37.22#ibcon#read 6, iclass 5, count 0 2006.201.13:16:37.22#ibcon#end of sib2, iclass 5, count 0 2006.201.13:16:37.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:16:37.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:16:37.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:16:37.22#ibcon#*before write, iclass 5, count 0 2006.201.13:16:37.22#ibcon#enter sib2, iclass 5, count 0 2006.201.13:16:37.22#ibcon#flushed, iclass 5, count 0 2006.201.13:16:37.22#ibcon#about to write, iclass 5, count 0 2006.201.13:16:37.22#ibcon#wrote, iclass 5, count 0 2006.201.13:16:37.22#ibcon#about to read 3, iclass 5, count 0 2006.201.13:16:37.26#ibcon#read 3, iclass 5, count 0 2006.201.13:16:37.26#ibcon#about to read 4, iclass 5, count 0 2006.201.13:16:37.26#ibcon#read 4, iclass 5, count 0 2006.201.13:16:37.26#ibcon#about to read 5, iclass 5, count 0 2006.201.13:16:37.26#ibcon#read 5, iclass 5, count 0 2006.201.13:16:37.26#ibcon#about to read 6, iclass 5, count 0 2006.201.13:16:37.26#ibcon#read 6, iclass 5, count 0 2006.201.13:16:37.26#ibcon#end of sib2, iclass 5, count 0 2006.201.13:16:37.26#ibcon#*after write, iclass 5, count 0 2006.201.13:16:37.26#ibcon#*before return 0, iclass 5, count 0 2006.201.13:16:37.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:16:37.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:16:37.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:16:37.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:16:37.26$vck44/va=2,7 2006.201.13:16:37.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.13:16:37.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.13:16:37.26#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:37.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:16:37.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:16:37.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:16:37.32#ibcon#enter wrdev, iclass 7, count 2 2006.201.13:16:37.32#ibcon#first serial, iclass 7, count 2 2006.201.13:16:37.32#ibcon#enter sib2, iclass 7, count 2 2006.201.13:16:37.32#ibcon#flushed, iclass 7, count 2 2006.201.13:16:37.32#ibcon#about to write, iclass 7, count 2 2006.201.13:16:37.32#ibcon#wrote, iclass 7, count 2 2006.201.13:16:37.32#ibcon#about to read 3, iclass 7, count 2 2006.201.13:16:37.34#ibcon#read 3, iclass 7, count 2 2006.201.13:16:37.34#ibcon#about to read 4, iclass 7, count 2 2006.201.13:16:37.34#ibcon#read 4, iclass 7, count 2 2006.201.13:16:37.34#ibcon#about to read 5, iclass 7, count 2 2006.201.13:16:37.34#ibcon#read 5, iclass 7, count 2 2006.201.13:16:37.34#ibcon#about to read 6, iclass 7, count 2 2006.201.13:16:37.34#ibcon#read 6, iclass 7, count 2 2006.201.13:16:37.34#ibcon#end of sib2, iclass 7, count 2 2006.201.13:16:37.34#ibcon#*mode == 0, iclass 7, count 2 2006.201.13:16:37.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.13:16:37.34#ibcon#[25=AT02-07\r\n] 2006.201.13:16:37.34#ibcon#*before write, iclass 7, count 2 2006.201.13:16:37.34#ibcon#enter sib2, iclass 7, count 2 2006.201.13:16:37.34#ibcon#flushed, iclass 7, count 2 2006.201.13:16:37.34#ibcon#about to write, iclass 7, count 2 2006.201.13:16:37.34#ibcon#wrote, iclass 7, count 2 2006.201.13:16:37.34#ibcon#about to read 3, iclass 7, count 2 2006.201.13:16:37.37#ibcon#read 3, iclass 7, count 2 2006.201.13:16:37.37#ibcon#about to read 4, iclass 7, count 2 2006.201.13:16:37.37#ibcon#read 4, iclass 7, count 2 2006.201.13:16:37.37#ibcon#about to read 5, iclass 7, count 2 2006.201.13:16:37.37#ibcon#read 5, iclass 7, count 2 2006.201.13:16:37.37#ibcon#about to read 6, iclass 7, count 2 2006.201.13:16:37.37#ibcon#read 6, iclass 7, count 2 2006.201.13:16:37.37#ibcon#end of sib2, iclass 7, count 2 2006.201.13:16:37.37#ibcon#*after write, iclass 7, count 2 2006.201.13:16:37.37#ibcon#*before return 0, iclass 7, count 2 2006.201.13:16:37.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:16:37.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:16:37.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.13:16:37.37#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:37.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:16:37.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:16:37.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:16:37.49#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:16:37.49#ibcon#first serial, iclass 7, count 0 2006.201.13:16:37.49#ibcon#enter sib2, iclass 7, count 0 2006.201.13:16:37.49#ibcon#flushed, iclass 7, count 0 2006.201.13:16:37.49#ibcon#about to write, iclass 7, count 0 2006.201.13:16:37.49#ibcon#wrote, iclass 7, count 0 2006.201.13:16:37.49#ibcon#about to read 3, iclass 7, count 0 2006.201.13:16:37.51#ibcon#read 3, iclass 7, count 0 2006.201.13:16:37.51#ibcon#about to read 4, iclass 7, count 0 2006.201.13:16:37.51#ibcon#read 4, iclass 7, count 0 2006.201.13:16:37.51#ibcon#about to read 5, iclass 7, count 0 2006.201.13:16:37.51#ibcon#read 5, iclass 7, count 0 2006.201.13:16:37.51#ibcon#about to read 6, iclass 7, count 0 2006.201.13:16:37.51#ibcon#read 6, iclass 7, count 0 2006.201.13:16:37.51#ibcon#end of sib2, iclass 7, count 0 2006.201.13:16:37.51#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:16:37.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:16:37.51#ibcon#[25=USB\r\n] 2006.201.13:16:37.51#ibcon#*before write, iclass 7, count 0 2006.201.13:16:37.51#ibcon#enter sib2, iclass 7, count 0 2006.201.13:16:37.51#ibcon#flushed, iclass 7, count 0 2006.201.13:16:37.51#ibcon#about to write, iclass 7, count 0 2006.201.13:16:37.51#ibcon#wrote, iclass 7, count 0 2006.201.13:16:37.51#ibcon#about to read 3, iclass 7, count 0 2006.201.13:16:37.54#ibcon#read 3, iclass 7, count 0 2006.201.13:16:37.54#ibcon#about to read 4, iclass 7, count 0 2006.201.13:16:37.54#ibcon#read 4, iclass 7, count 0 2006.201.13:16:37.54#ibcon#about to read 5, iclass 7, count 0 2006.201.13:16:37.54#ibcon#read 5, iclass 7, count 0 2006.201.13:16:37.54#ibcon#about to read 6, iclass 7, count 0 2006.201.13:16:37.54#ibcon#read 6, iclass 7, count 0 2006.201.13:16:37.54#ibcon#end of sib2, iclass 7, count 0 2006.201.13:16:37.54#ibcon#*after write, iclass 7, count 0 2006.201.13:16:37.54#ibcon#*before return 0, iclass 7, count 0 2006.201.13:16:37.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:16:37.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:16:37.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:16:37.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:16:37.54$vck44/valo=3,564.99 2006.201.13:16:37.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.13:16:37.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.13:16:37.54#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:37.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:16:37.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:16:37.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:16:37.54#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:16:37.54#ibcon#first serial, iclass 11, count 0 2006.201.13:16:37.54#ibcon#enter sib2, iclass 11, count 0 2006.201.13:16:37.54#ibcon#flushed, iclass 11, count 0 2006.201.13:16:37.54#ibcon#about to write, iclass 11, count 0 2006.201.13:16:37.54#ibcon#wrote, iclass 11, count 0 2006.201.13:16:37.54#ibcon#about to read 3, iclass 11, count 0 2006.201.13:16:37.56#ibcon#read 3, iclass 11, count 0 2006.201.13:16:37.56#ibcon#about to read 4, iclass 11, count 0 2006.201.13:16:37.56#ibcon#read 4, iclass 11, count 0 2006.201.13:16:37.56#ibcon#about to read 5, iclass 11, count 0 2006.201.13:16:37.56#ibcon#read 5, iclass 11, count 0 2006.201.13:16:37.56#ibcon#about to read 6, iclass 11, count 0 2006.201.13:16:37.56#ibcon#read 6, iclass 11, count 0 2006.201.13:16:37.56#ibcon#end of sib2, iclass 11, count 0 2006.201.13:16:37.56#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:16:37.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:16:37.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:16:37.56#ibcon#*before write, iclass 11, count 0 2006.201.13:16:37.56#ibcon#enter sib2, iclass 11, count 0 2006.201.13:16:37.56#ibcon#flushed, iclass 11, count 0 2006.201.13:16:37.56#ibcon#about to write, iclass 11, count 0 2006.201.13:16:37.56#ibcon#wrote, iclass 11, count 0 2006.201.13:16:37.56#ibcon#about to read 3, iclass 11, count 0 2006.201.13:16:37.61#ibcon#read 3, iclass 11, count 0 2006.201.13:16:37.61#ibcon#about to read 4, iclass 11, count 0 2006.201.13:16:37.61#ibcon#read 4, iclass 11, count 0 2006.201.13:16:37.61#ibcon#about to read 5, iclass 11, count 0 2006.201.13:16:37.61#ibcon#read 5, iclass 11, count 0 2006.201.13:16:37.61#ibcon#about to read 6, iclass 11, count 0 2006.201.13:16:37.61#ibcon#read 6, iclass 11, count 0 2006.201.13:16:37.61#ibcon#end of sib2, iclass 11, count 0 2006.201.13:16:37.61#ibcon#*after write, iclass 11, count 0 2006.201.13:16:37.61#ibcon#*before return 0, iclass 11, count 0 2006.201.13:16:37.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:16:37.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:16:37.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:16:37.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:16:37.61$vck44/va=3,8 2006.201.13:16:37.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.13:16:37.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.13:16:37.61#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:37.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:16:37.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:16:37.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:16:37.66#ibcon#enter wrdev, iclass 13, count 2 2006.201.13:16:37.66#ibcon#first serial, iclass 13, count 2 2006.201.13:16:37.66#ibcon#enter sib2, iclass 13, count 2 2006.201.13:16:37.66#ibcon#flushed, iclass 13, count 2 2006.201.13:16:37.66#ibcon#about to write, iclass 13, count 2 2006.201.13:16:37.66#ibcon#wrote, iclass 13, count 2 2006.201.13:16:37.66#ibcon#about to read 3, iclass 13, count 2 2006.201.13:16:37.68#ibcon#read 3, iclass 13, count 2 2006.201.13:16:37.68#ibcon#about to read 4, iclass 13, count 2 2006.201.13:16:37.68#ibcon#read 4, iclass 13, count 2 2006.201.13:16:37.68#ibcon#about to read 5, iclass 13, count 2 2006.201.13:16:37.68#ibcon#read 5, iclass 13, count 2 2006.201.13:16:37.68#ibcon#about to read 6, iclass 13, count 2 2006.201.13:16:37.68#ibcon#read 6, iclass 13, count 2 2006.201.13:16:37.68#ibcon#end of sib2, iclass 13, count 2 2006.201.13:16:37.68#ibcon#*mode == 0, iclass 13, count 2 2006.201.13:16:37.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.13:16:37.68#ibcon#[25=AT03-08\r\n] 2006.201.13:16:37.68#ibcon#*before write, iclass 13, count 2 2006.201.13:16:37.68#ibcon#enter sib2, iclass 13, count 2 2006.201.13:16:37.68#ibcon#flushed, iclass 13, count 2 2006.201.13:16:37.68#ibcon#about to write, iclass 13, count 2 2006.201.13:16:37.68#ibcon#wrote, iclass 13, count 2 2006.201.13:16:37.68#ibcon#about to read 3, iclass 13, count 2 2006.201.13:16:37.71#ibcon#read 3, iclass 13, count 2 2006.201.13:16:37.71#ibcon#about to read 4, iclass 13, count 2 2006.201.13:16:37.71#ibcon#read 4, iclass 13, count 2 2006.201.13:16:37.71#ibcon#about to read 5, iclass 13, count 2 2006.201.13:16:37.71#ibcon#read 5, iclass 13, count 2 2006.201.13:16:37.71#ibcon#about to read 6, iclass 13, count 2 2006.201.13:16:37.71#ibcon#read 6, iclass 13, count 2 2006.201.13:16:37.71#ibcon#end of sib2, iclass 13, count 2 2006.201.13:16:37.71#ibcon#*after write, iclass 13, count 2 2006.201.13:16:37.71#ibcon#*before return 0, iclass 13, count 2 2006.201.13:16:37.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:16:37.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:16:37.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.13:16:37.71#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:37.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:16:37.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:16:37.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:16:37.83#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:16:37.83#ibcon#first serial, iclass 13, count 0 2006.201.13:16:37.83#ibcon#enter sib2, iclass 13, count 0 2006.201.13:16:37.83#ibcon#flushed, iclass 13, count 0 2006.201.13:16:37.83#ibcon#about to write, iclass 13, count 0 2006.201.13:16:37.83#ibcon#wrote, iclass 13, count 0 2006.201.13:16:37.83#ibcon#about to read 3, iclass 13, count 0 2006.201.13:16:37.85#ibcon#read 3, iclass 13, count 0 2006.201.13:16:37.85#ibcon#about to read 4, iclass 13, count 0 2006.201.13:16:37.85#ibcon#read 4, iclass 13, count 0 2006.201.13:16:37.85#ibcon#about to read 5, iclass 13, count 0 2006.201.13:16:37.85#ibcon#read 5, iclass 13, count 0 2006.201.13:16:37.85#ibcon#about to read 6, iclass 13, count 0 2006.201.13:16:37.85#ibcon#read 6, iclass 13, count 0 2006.201.13:16:37.85#ibcon#end of sib2, iclass 13, count 0 2006.201.13:16:37.85#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:16:37.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:16:37.85#ibcon#[25=USB\r\n] 2006.201.13:16:37.85#ibcon#*before write, iclass 13, count 0 2006.201.13:16:37.85#ibcon#enter sib2, iclass 13, count 0 2006.201.13:16:37.85#ibcon#flushed, iclass 13, count 0 2006.201.13:16:37.85#ibcon#about to write, iclass 13, count 0 2006.201.13:16:37.85#ibcon#wrote, iclass 13, count 0 2006.201.13:16:37.85#ibcon#about to read 3, iclass 13, count 0 2006.201.13:16:37.88#ibcon#read 3, iclass 13, count 0 2006.201.13:16:37.88#ibcon#about to read 4, iclass 13, count 0 2006.201.13:16:37.88#ibcon#read 4, iclass 13, count 0 2006.201.13:16:37.88#ibcon#about to read 5, iclass 13, count 0 2006.201.13:16:37.88#ibcon#read 5, iclass 13, count 0 2006.201.13:16:37.88#ibcon#about to read 6, iclass 13, count 0 2006.201.13:16:37.88#ibcon#read 6, iclass 13, count 0 2006.201.13:16:37.88#ibcon#end of sib2, iclass 13, count 0 2006.201.13:16:37.88#ibcon#*after write, iclass 13, count 0 2006.201.13:16:37.88#ibcon#*before return 0, iclass 13, count 0 2006.201.13:16:37.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:16:37.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:16:37.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:16:37.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:16:37.88$vck44/valo=4,624.99 2006.201.13:16:37.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.13:16:37.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.13:16:37.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:37.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:16:37.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:16:37.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:16:37.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:16:37.88#ibcon#first serial, iclass 15, count 0 2006.201.13:16:37.88#ibcon#enter sib2, iclass 15, count 0 2006.201.13:16:37.88#ibcon#flushed, iclass 15, count 0 2006.201.13:16:37.88#ibcon#about to write, iclass 15, count 0 2006.201.13:16:37.88#ibcon#wrote, iclass 15, count 0 2006.201.13:16:37.88#ibcon#about to read 3, iclass 15, count 0 2006.201.13:16:37.90#ibcon#read 3, iclass 15, count 0 2006.201.13:16:37.90#ibcon#about to read 4, iclass 15, count 0 2006.201.13:16:37.90#ibcon#read 4, iclass 15, count 0 2006.201.13:16:37.90#ibcon#about to read 5, iclass 15, count 0 2006.201.13:16:37.90#ibcon#read 5, iclass 15, count 0 2006.201.13:16:37.90#ibcon#about to read 6, iclass 15, count 0 2006.201.13:16:37.90#ibcon#read 6, iclass 15, count 0 2006.201.13:16:37.90#ibcon#end of sib2, iclass 15, count 0 2006.201.13:16:37.90#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:16:37.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:16:37.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:16:37.90#ibcon#*before write, iclass 15, count 0 2006.201.13:16:37.90#ibcon#enter sib2, iclass 15, count 0 2006.201.13:16:37.90#ibcon#flushed, iclass 15, count 0 2006.201.13:16:37.90#ibcon#about to write, iclass 15, count 0 2006.201.13:16:37.90#ibcon#wrote, iclass 15, count 0 2006.201.13:16:37.90#ibcon#about to read 3, iclass 15, count 0 2006.201.13:16:37.90#abcon#{5=INTERFACE CLEAR} 2006.201.13:16:37.95#ibcon#read 3, iclass 15, count 0 2006.201.13:16:37.95#ibcon#about to read 4, iclass 15, count 0 2006.201.13:16:37.95#ibcon#read 4, iclass 15, count 0 2006.201.13:16:37.95#ibcon#about to read 5, iclass 15, count 0 2006.201.13:16:37.95#ibcon#read 5, iclass 15, count 0 2006.201.13:16:37.95#ibcon#about to read 6, iclass 15, count 0 2006.201.13:16:37.95#ibcon#read 6, iclass 15, count 0 2006.201.13:16:37.95#ibcon#end of sib2, iclass 15, count 0 2006.201.13:16:37.95#ibcon#*after write, iclass 15, count 0 2006.201.13:16:37.95#ibcon#*before return 0, iclass 15, count 0 2006.201.13:16:37.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:16:37.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:16:37.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:16:37.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:16:37.95$vck44/va=4,7 2006.201.13:16:37.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.13:16:37.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.13:16:37.95#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:37.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:37.96#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:16:38.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:38.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:38.00#ibcon#enter wrdev, iclass 19, count 2 2006.201.13:16:38.00#ibcon#first serial, iclass 19, count 2 2006.201.13:16:38.00#ibcon#enter sib2, iclass 19, count 2 2006.201.13:16:38.00#ibcon#flushed, iclass 19, count 2 2006.201.13:16:38.00#ibcon#about to write, iclass 19, count 2 2006.201.13:16:38.00#ibcon#wrote, iclass 19, count 2 2006.201.13:16:38.00#ibcon#about to read 3, iclass 19, count 2 2006.201.13:16:38.02#ibcon#read 3, iclass 19, count 2 2006.201.13:16:38.02#ibcon#about to read 4, iclass 19, count 2 2006.201.13:16:38.02#ibcon#read 4, iclass 19, count 2 2006.201.13:16:38.02#ibcon#about to read 5, iclass 19, count 2 2006.201.13:16:38.02#ibcon#read 5, iclass 19, count 2 2006.201.13:16:38.02#ibcon#about to read 6, iclass 19, count 2 2006.201.13:16:38.02#ibcon#read 6, iclass 19, count 2 2006.201.13:16:38.02#ibcon#end of sib2, iclass 19, count 2 2006.201.13:16:38.02#ibcon#*mode == 0, iclass 19, count 2 2006.201.13:16:38.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.13:16:38.02#ibcon#[25=AT04-07\r\n] 2006.201.13:16:38.02#ibcon#*before write, iclass 19, count 2 2006.201.13:16:38.02#ibcon#enter sib2, iclass 19, count 2 2006.201.13:16:38.02#ibcon#flushed, iclass 19, count 2 2006.201.13:16:38.02#ibcon#about to write, iclass 19, count 2 2006.201.13:16:38.02#ibcon#wrote, iclass 19, count 2 2006.201.13:16:38.02#ibcon#about to read 3, iclass 19, count 2 2006.201.13:16:38.05#ibcon#read 3, iclass 19, count 2 2006.201.13:16:38.05#ibcon#about to read 4, iclass 19, count 2 2006.201.13:16:38.05#ibcon#read 4, iclass 19, count 2 2006.201.13:16:38.05#ibcon#about to read 5, iclass 19, count 2 2006.201.13:16:38.05#ibcon#read 5, iclass 19, count 2 2006.201.13:16:38.05#ibcon#about to read 6, iclass 19, count 2 2006.201.13:16:38.05#ibcon#read 6, iclass 19, count 2 2006.201.13:16:38.05#ibcon#end of sib2, iclass 19, count 2 2006.201.13:16:38.05#ibcon#*after write, iclass 19, count 2 2006.201.13:16:38.05#ibcon#*before return 0, iclass 19, count 2 2006.201.13:16:38.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:38.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:38.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.13:16:38.05#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:38.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:38.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:38.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:38.17#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:16:38.17#ibcon#first serial, iclass 19, count 0 2006.201.13:16:38.17#ibcon#enter sib2, iclass 19, count 0 2006.201.13:16:38.17#ibcon#flushed, iclass 19, count 0 2006.201.13:16:38.17#ibcon#about to write, iclass 19, count 0 2006.201.13:16:38.17#ibcon#wrote, iclass 19, count 0 2006.201.13:16:38.17#ibcon#about to read 3, iclass 19, count 0 2006.201.13:16:38.19#ibcon#read 3, iclass 19, count 0 2006.201.13:16:38.19#ibcon#about to read 4, iclass 19, count 0 2006.201.13:16:38.19#ibcon#read 4, iclass 19, count 0 2006.201.13:16:38.19#ibcon#about to read 5, iclass 19, count 0 2006.201.13:16:38.19#ibcon#read 5, iclass 19, count 0 2006.201.13:16:38.19#ibcon#about to read 6, iclass 19, count 0 2006.201.13:16:38.19#ibcon#read 6, iclass 19, count 0 2006.201.13:16:38.19#ibcon#end of sib2, iclass 19, count 0 2006.201.13:16:38.19#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:16:38.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:16:38.19#ibcon#[25=USB\r\n] 2006.201.13:16:38.19#ibcon#*before write, iclass 19, count 0 2006.201.13:16:38.19#ibcon#enter sib2, iclass 19, count 0 2006.201.13:16:38.19#ibcon#flushed, iclass 19, count 0 2006.201.13:16:38.19#ibcon#about to write, iclass 19, count 0 2006.201.13:16:38.19#ibcon#wrote, iclass 19, count 0 2006.201.13:16:38.19#ibcon#about to read 3, iclass 19, count 0 2006.201.13:16:38.22#ibcon#read 3, iclass 19, count 0 2006.201.13:16:38.22#ibcon#about to read 4, iclass 19, count 0 2006.201.13:16:38.22#ibcon#read 4, iclass 19, count 0 2006.201.13:16:38.22#ibcon#about to read 5, iclass 19, count 0 2006.201.13:16:38.22#ibcon#read 5, iclass 19, count 0 2006.201.13:16:38.22#ibcon#about to read 6, iclass 19, count 0 2006.201.13:16:38.22#ibcon#read 6, iclass 19, count 0 2006.201.13:16:38.22#ibcon#end of sib2, iclass 19, count 0 2006.201.13:16:38.22#ibcon#*after write, iclass 19, count 0 2006.201.13:16:38.22#ibcon#*before return 0, iclass 19, count 0 2006.201.13:16:38.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:38.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:38.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:16:38.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:16:38.22$vck44/valo=5,734.99 2006.201.13:16:38.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.13:16:38.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.13:16:38.22#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:38.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:38.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:38.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:38.22#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:16:38.22#ibcon#first serial, iclass 21, count 0 2006.201.13:16:38.22#ibcon#enter sib2, iclass 21, count 0 2006.201.13:16:38.22#ibcon#flushed, iclass 21, count 0 2006.201.13:16:38.22#ibcon#about to write, iclass 21, count 0 2006.201.13:16:38.22#ibcon#wrote, iclass 21, count 0 2006.201.13:16:38.22#ibcon#about to read 3, iclass 21, count 0 2006.201.13:16:38.24#ibcon#read 3, iclass 21, count 0 2006.201.13:16:38.24#ibcon#about to read 4, iclass 21, count 0 2006.201.13:16:38.24#ibcon#read 4, iclass 21, count 0 2006.201.13:16:38.24#ibcon#about to read 5, iclass 21, count 0 2006.201.13:16:38.24#ibcon#read 5, iclass 21, count 0 2006.201.13:16:38.24#ibcon#about to read 6, iclass 21, count 0 2006.201.13:16:38.24#ibcon#read 6, iclass 21, count 0 2006.201.13:16:38.24#ibcon#end of sib2, iclass 21, count 0 2006.201.13:16:38.24#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:16:38.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:16:38.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:16:38.24#ibcon#*before write, iclass 21, count 0 2006.201.13:16:38.24#ibcon#enter sib2, iclass 21, count 0 2006.201.13:16:38.24#ibcon#flushed, iclass 21, count 0 2006.201.13:16:38.24#ibcon#about to write, iclass 21, count 0 2006.201.13:16:38.24#ibcon#wrote, iclass 21, count 0 2006.201.13:16:38.24#ibcon#about to read 3, iclass 21, count 0 2006.201.13:16:38.28#ibcon#read 3, iclass 21, count 0 2006.201.13:16:38.28#ibcon#about to read 4, iclass 21, count 0 2006.201.13:16:38.28#ibcon#read 4, iclass 21, count 0 2006.201.13:16:38.28#ibcon#about to read 5, iclass 21, count 0 2006.201.13:16:38.28#ibcon#read 5, iclass 21, count 0 2006.201.13:16:38.28#ibcon#about to read 6, iclass 21, count 0 2006.201.13:16:38.28#ibcon#read 6, iclass 21, count 0 2006.201.13:16:38.28#ibcon#end of sib2, iclass 21, count 0 2006.201.13:16:38.28#ibcon#*after write, iclass 21, count 0 2006.201.13:16:38.28#ibcon#*before return 0, iclass 21, count 0 2006.201.13:16:38.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:38.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:38.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:16:38.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:16:38.28$vck44/va=5,4 2006.201.13:16:38.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.13:16:38.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.13:16:38.28#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:38.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:38.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:38.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:38.34#ibcon#enter wrdev, iclass 23, count 2 2006.201.13:16:38.34#ibcon#first serial, iclass 23, count 2 2006.201.13:16:38.34#ibcon#enter sib2, iclass 23, count 2 2006.201.13:16:38.34#ibcon#flushed, iclass 23, count 2 2006.201.13:16:38.34#ibcon#about to write, iclass 23, count 2 2006.201.13:16:38.34#ibcon#wrote, iclass 23, count 2 2006.201.13:16:38.34#ibcon#about to read 3, iclass 23, count 2 2006.201.13:16:38.36#ibcon#read 3, iclass 23, count 2 2006.201.13:16:38.36#ibcon#about to read 4, iclass 23, count 2 2006.201.13:16:38.36#ibcon#read 4, iclass 23, count 2 2006.201.13:16:38.36#ibcon#about to read 5, iclass 23, count 2 2006.201.13:16:38.36#ibcon#read 5, iclass 23, count 2 2006.201.13:16:38.36#ibcon#about to read 6, iclass 23, count 2 2006.201.13:16:38.36#ibcon#read 6, iclass 23, count 2 2006.201.13:16:38.36#ibcon#end of sib2, iclass 23, count 2 2006.201.13:16:38.36#ibcon#*mode == 0, iclass 23, count 2 2006.201.13:16:38.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.13:16:38.36#ibcon#[25=AT05-04\r\n] 2006.201.13:16:38.36#ibcon#*before write, iclass 23, count 2 2006.201.13:16:38.36#ibcon#enter sib2, iclass 23, count 2 2006.201.13:16:38.36#ibcon#flushed, iclass 23, count 2 2006.201.13:16:38.36#ibcon#about to write, iclass 23, count 2 2006.201.13:16:38.36#ibcon#wrote, iclass 23, count 2 2006.201.13:16:38.36#ibcon#about to read 3, iclass 23, count 2 2006.201.13:16:38.39#ibcon#read 3, iclass 23, count 2 2006.201.13:16:38.39#ibcon#about to read 4, iclass 23, count 2 2006.201.13:16:38.39#ibcon#read 4, iclass 23, count 2 2006.201.13:16:38.39#ibcon#about to read 5, iclass 23, count 2 2006.201.13:16:38.39#ibcon#read 5, iclass 23, count 2 2006.201.13:16:38.39#ibcon#about to read 6, iclass 23, count 2 2006.201.13:16:38.39#ibcon#read 6, iclass 23, count 2 2006.201.13:16:38.39#ibcon#end of sib2, iclass 23, count 2 2006.201.13:16:38.39#ibcon#*after write, iclass 23, count 2 2006.201.13:16:38.39#ibcon#*before return 0, iclass 23, count 2 2006.201.13:16:38.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:38.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:38.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.13:16:38.39#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:38.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:38.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:38.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:38.51#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:16:38.51#ibcon#first serial, iclass 23, count 0 2006.201.13:16:38.51#ibcon#enter sib2, iclass 23, count 0 2006.201.13:16:38.51#ibcon#flushed, iclass 23, count 0 2006.201.13:16:38.51#ibcon#about to write, iclass 23, count 0 2006.201.13:16:38.51#ibcon#wrote, iclass 23, count 0 2006.201.13:16:38.51#ibcon#about to read 3, iclass 23, count 0 2006.201.13:16:38.53#ibcon#read 3, iclass 23, count 0 2006.201.13:16:38.53#ibcon#about to read 4, iclass 23, count 0 2006.201.13:16:38.53#ibcon#read 4, iclass 23, count 0 2006.201.13:16:38.53#ibcon#about to read 5, iclass 23, count 0 2006.201.13:16:38.53#ibcon#read 5, iclass 23, count 0 2006.201.13:16:38.53#ibcon#about to read 6, iclass 23, count 0 2006.201.13:16:38.53#ibcon#read 6, iclass 23, count 0 2006.201.13:16:38.53#ibcon#end of sib2, iclass 23, count 0 2006.201.13:16:38.53#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:16:38.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:16:38.53#ibcon#[25=USB\r\n] 2006.201.13:16:38.53#ibcon#*before write, iclass 23, count 0 2006.201.13:16:38.53#ibcon#enter sib2, iclass 23, count 0 2006.201.13:16:38.53#ibcon#flushed, iclass 23, count 0 2006.201.13:16:38.53#ibcon#about to write, iclass 23, count 0 2006.201.13:16:38.53#ibcon#wrote, iclass 23, count 0 2006.201.13:16:38.53#ibcon#about to read 3, iclass 23, count 0 2006.201.13:16:38.56#ibcon#read 3, iclass 23, count 0 2006.201.13:16:38.56#ibcon#about to read 4, iclass 23, count 0 2006.201.13:16:38.56#ibcon#read 4, iclass 23, count 0 2006.201.13:16:38.56#ibcon#about to read 5, iclass 23, count 0 2006.201.13:16:38.56#ibcon#read 5, iclass 23, count 0 2006.201.13:16:38.56#ibcon#about to read 6, iclass 23, count 0 2006.201.13:16:38.56#ibcon#read 6, iclass 23, count 0 2006.201.13:16:38.56#ibcon#end of sib2, iclass 23, count 0 2006.201.13:16:38.56#ibcon#*after write, iclass 23, count 0 2006.201.13:16:38.56#ibcon#*before return 0, iclass 23, count 0 2006.201.13:16:38.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:38.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:38.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:16:38.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:16:38.56$vck44/valo=6,814.99 2006.201.13:16:38.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.13:16:38.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.13:16:38.56#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:38.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:38.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:38.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:38.56#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:16:38.56#ibcon#first serial, iclass 25, count 0 2006.201.13:16:38.56#ibcon#enter sib2, iclass 25, count 0 2006.201.13:16:38.56#ibcon#flushed, iclass 25, count 0 2006.201.13:16:38.56#ibcon#about to write, iclass 25, count 0 2006.201.13:16:38.56#ibcon#wrote, iclass 25, count 0 2006.201.13:16:38.56#ibcon#about to read 3, iclass 25, count 0 2006.201.13:16:38.58#ibcon#read 3, iclass 25, count 0 2006.201.13:16:38.58#ibcon#about to read 4, iclass 25, count 0 2006.201.13:16:38.58#ibcon#read 4, iclass 25, count 0 2006.201.13:16:38.58#ibcon#about to read 5, iclass 25, count 0 2006.201.13:16:38.58#ibcon#read 5, iclass 25, count 0 2006.201.13:16:38.58#ibcon#about to read 6, iclass 25, count 0 2006.201.13:16:38.58#ibcon#read 6, iclass 25, count 0 2006.201.13:16:38.58#ibcon#end of sib2, iclass 25, count 0 2006.201.13:16:38.58#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:16:38.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:16:38.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:16:38.58#ibcon#*before write, iclass 25, count 0 2006.201.13:16:38.58#ibcon#enter sib2, iclass 25, count 0 2006.201.13:16:38.58#ibcon#flushed, iclass 25, count 0 2006.201.13:16:38.58#ibcon#about to write, iclass 25, count 0 2006.201.13:16:38.58#ibcon#wrote, iclass 25, count 0 2006.201.13:16:38.58#ibcon#about to read 3, iclass 25, count 0 2006.201.13:16:38.63#ibcon#read 3, iclass 25, count 0 2006.201.13:16:38.63#ibcon#about to read 4, iclass 25, count 0 2006.201.13:16:38.63#ibcon#read 4, iclass 25, count 0 2006.201.13:16:38.63#ibcon#about to read 5, iclass 25, count 0 2006.201.13:16:38.63#ibcon#read 5, iclass 25, count 0 2006.201.13:16:38.63#ibcon#about to read 6, iclass 25, count 0 2006.201.13:16:38.63#ibcon#read 6, iclass 25, count 0 2006.201.13:16:38.63#ibcon#end of sib2, iclass 25, count 0 2006.201.13:16:38.63#ibcon#*after write, iclass 25, count 0 2006.201.13:16:38.63#ibcon#*before return 0, iclass 25, count 0 2006.201.13:16:38.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:38.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:38.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:16:38.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:16:38.63$vck44/va=6,5 2006.201.13:16:38.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.13:16:38.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.13:16:38.63#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:38.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:38.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:38.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:38.68#ibcon#enter wrdev, iclass 27, count 2 2006.201.13:16:38.68#ibcon#first serial, iclass 27, count 2 2006.201.13:16:38.68#ibcon#enter sib2, iclass 27, count 2 2006.201.13:16:38.68#ibcon#flushed, iclass 27, count 2 2006.201.13:16:38.68#ibcon#about to write, iclass 27, count 2 2006.201.13:16:38.68#ibcon#wrote, iclass 27, count 2 2006.201.13:16:38.68#ibcon#about to read 3, iclass 27, count 2 2006.201.13:16:38.70#ibcon#read 3, iclass 27, count 2 2006.201.13:16:38.70#ibcon#about to read 4, iclass 27, count 2 2006.201.13:16:38.70#ibcon#read 4, iclass 27, count 2 2006.201.13:16:38.70#ibcon#about to read 5, iclass 27, count 2 2006.201.13:16:38.70#ibcon#read 5, iclass 27, count 2 2006.201.13:16:38.70#ibcon#about to read 6, iclass 27, count 2 2006.201.13:16:38.70#ibcon#read 6, iclass 27, count 2 2006.201.13:16:38.70#ibcon#end of sib2, iclass 27, count 2 2006.201.13:16:38.70#ibcon#*mode == 0, iclass 27, count 2 2006.201.13:16:38.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.13:16:38.70#ibcon#[25=AT06-05\r\n] 2006.201.13:16:38.70#ibcon#*before write, iclass 27, count 2 2006.201.13:16:38.70#ibcon#enter sib2, iclass 27, count 2 2006.201.13:16:38.70#ibcon#flushed, iclass 27, count 2 2006.201.13:16:38.70#ibcon#about to write, iclass 27, count 2 2006.201.13:16:38.70#ibcon#wrote, iclass 27, count 2 2006.201.13:16:38.70#ibcon#about to read 3, iclass 27, count 2 2006.201.13:16:38.73#ibcon#read 3, iclass 27, count 2 2006.201.13:16:38.73#ibcon#about to read 4, iclass 27, count 2 2006.201.13:16:38.73#ibcon#read 4, iclass 27, count 2 2006.201.13:16:38.73#ibcon#about to read 5, iclass 27, count 2 2006.201.13:16:38.73#ibcon#read 5, iclass 27, count 2 2006.201.13:16:38.73#ibcon#about to read 6, iclass 27, count 2 2006.201.13:16:38.73#ibcon#read 6, iclass 27, count 2 2006.201.13:16:38.73#ibcon#end of sib2, iclass 27, count 2 2006.201.13:16:38.73#ibcon#*after write, iclass 27, count 2 2006.201.13:16:38.73#ibcon#*before return 0, iclass 27, count 2 2006.201.13:16:38.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:38.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:38.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.13:16:38.73#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:38.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:38.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:38.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:38.85#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:16:38.85#ibcon#first serial, iclass 27, count 0 2006.201.13:16:38.85#ibcon#enter sib2, iclass 27, count 0 2006.201.13:16:38.85#ibcon#flushed, iclass 27, count 0 2006.201.13:16:38.85#ibcon#about to write, iclass 27, count 0 2006.201.13:16:38.85#ibcon#wrote, iclass 27, count 0 2006.201.13:16:38.85#ibcon#about to read 3, iclass 27, count 0 2006.201.13:16:38.87#ibcon#read 3, iclass 27, count 0 2006.201.13:16:38.87#ibcon#about to read 4, iclass 27, count 0 2006.201.13:16:38.87#ibcon#read 4, iclass 27, count 0 2006.201.13:16:38.87#ibcon#about to read 5, iclass 27, count 0 2006.201.13:16:38.87#ibcon#read 5, iclass 27, count 0 2006.201.13:16:38.87#ibcon#about to read 6, iclass 27, count 0 2006.201.13:16:38.87#ibcon#read 6, iclass 27, count 0 2006.201.13:16:38.87#ibcon#end of sib2, iclass 27, count 0 2006.201.13:16:38.87#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:16:38.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:16:38.87#ibcon#[25=USB\r\n] 2006.201.13:16:38.87#ibcon#*before write, iclass 27, count 0 2006.201.13:16:38.87#ibcon#enter sib2, iclass 27, count 0 2006.201.13:16:38.87#ibcon#flushed, iclass 27, count 0 2006.201.13:16:38.87#ibcon#about to write, iclass 27, count 0 2006.201.13:16:38.87#ibcon#wrote, iclass 27, count 0 2006.201.13:16:38.87#ibcon#about to read 3, iclass 27, count 0 2006.201.13:16:38.90#ibcon#read 3, iclass 27, count 0 2006.201.13:16:38.90#ibcon#about to read 4, iclass 27, count 0 2006.201.13:16:38.90#ibcon#read 4, iclass 27, count 0 2006.201.13:16:38.90#ibcon#about to read 5, iclass 27, count 0 2006.201.13:16:38.90#ibcon#read 5, iclass 27, count 0 2006.201.13:16:38.90#ibcon#about to read 6, iclass 27, count 0 2006.201.13:16:38.90#ibcon#read 6, iclass 27, count 0 2006.201.13:16:38.90#ibcon#end of sib2, iclass 27, count 0 2006.201.13:16:38.90#ibcon#*after write, iclass 27, count 0 2006.201.13:16:38.90#ibcon#*before return 0, iclass 27, count 0 2006.201.13:16:38.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:38.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:38.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:16:38.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:16:38.90$vck44/valo=7,864.99 2006.201.13:16:38.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.13:16:38.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.13:16:38.90#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:38.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:38.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:38.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:38.90#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:16:38.90#ibcon#first serial, iclass 29, count 0 2006.201.13:16:38.90#ibcon#enter sib2, iclass 29, count 0 2006.201.13:16:38.90#ibcon#flushed, iclass 29, count 0 2006.201.13:16:38.90#ibcon#about to write, iclass 29, count 0 2006.201.13:16:38.90#ibcon#wrote, iclass 29, count 0 2006.201.13:16:38.90#ibcon#about to read 3, iclass 29, count 0 2006.201.13:16:38.92#ibcon#read 3, iclass 29, count 0 2006.201.13:16:38.92#ibcon#about to read 4, iclass 29, count 0 2006.201.13:16:38.92#ibcon#read 4, iclass 29, count 0 2006.201.13:16:38.92#ibcon#about to read 5, iclass 29, count 0 2006.201.13:16:38.92#ibcon#read 5, iclass 29, count 0 2006.201.13:16:38.92#ibcon#about to read 6, iclass 29, count 0 2006.201.13:16:38.92#ibcon#read 6, iclass 29, count 0 2006.201.13:16:38.92#ibcon#end of sib2, iclass 29, count 0 2006.201.13:16:38.92#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:16:38.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:16:38.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:16:38.92#ibcon#*before write, iclass 29, count 0 2006.201.13:16:38.92#ibcon#enter sib2, iclass 29, count 0 2006.201.13:16:38.92#ibcon#flushed, iclass 29, count 0 2006.201.13:16:38.92#ibcon#about to write, iclass 29, count 0 2006.201.13:16:38.92#ibcon#wrote, iclass 29, count 0 2006.201.13:16:38.92#ibcon#about to read 3, iclass 29, count 0 2006.201.13:16:38.96#ibcon#read 3, iclass 29, count 0 2006.201.13:16:38.96#ibcon#about to read 4, iclass 29, count 0 2006.201.13:16:38.96#ibcon#read 4, iclass 29, count 0 2006.201.13:16:38.96#ibcon#about to read 5, iclass 29, count 0 2006.201.13:16:38.96#ibcon#read 5, iclass 29, count 0 2006.201.13:16:38.96#ibcon#about to read 6, iclass 29, count 0 2006.201.13:16:38.96#ibcon#read 6, iclass 29, count 0 2006.201.13:16:38.96#ibcon#end of sib2, iclass 29, count 0 2006.201.13:16:38.96#ibcon#*after write, iclass 29, count 0 2006.201.13:16:38.96#ibcon#*before return 0, iclass 29, count 0 2006.201.13:16:38.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:38.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:38.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:16:38.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:16:38.96$vck44/va=7,5 2006.201.13:16:38.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.13:16:38.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.13:16:38.96#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:38.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:39.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:39.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:39.02#ibcon#enter wrdev, iclass 31, count 2 2006.201.13:16:39.02#ibcon#first serial, iclass 31, count 2 2006.201.13:16:39.02#ibcon#enter sib2, iclass 31, count 2 2006.201.13:16:39.02#ibcon#flushed, iclass 31, count 2 2006.201.13:16:39.02#ibcon#about to write, iclass 31, count 2 2006.201.13:16:39.02#ibcon#wrote, iclass 31, count 2 2006.201.13:16:39.02#ibcon#about to read 3, iclass 31, count 2 2006.201.13:16:39.04#ibcon#read 3, iclass 31, count 2 2006.201.13:16:39.04#ibcon#about to read 4, iclass 31, count 2 2006.201.13:16:39.04#ibcon#read 4, iclass 31, count 2 2006.201.13:16:39.04#ibcon#about to read 5, iclass 31, count 2 2006.201.13:16:39.04#ibcon#read 5, iclass 31, count 2 2006.201.13:16:39.04#ibcon#about to read 6, iclass 31, count 2 2006.201.13:16:39.04#ibcon#read 6, iclass 31, count 2 2006.201.13:16:39.04#ibcon#end of sib2, iclass 31, count 2 2006.201.13:16:39.04#ibcon#*mode == 0, iclass 31, count 2 2006.201.13:16:39.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.13:16:39.04#ibcon#[25=AT07-05\r\n] 2006.201.13:16:39.04#ibcon#*before write, iclass 31, count 2 2006.201.13:16:39.04#ibcon#enter sib2, iclass 31, count 2 2006.201.13:16:39.04#ibcon#flushed, iclass 31, count 2 2006.201.13:16:39.04#ibcon#about to write, iclass 31, count 2 2006.201.13:16:39.04#ibcon#wrote, iclass 31, count 2 2006.201.13:16:39.04#ibcon#about to read 3, iclass 31, count 2 2006.201.13:16:39.07#ibcon#read 3, iclass 31, count 2 2006.201.13:16:39.07#ibcon#about to read 4, iclass 31, count 2 2006.201.13:16:39.07#ibcon#read 4, iclass 31, count 2 2006.201.13:16:39.07#ibcon#about to read 5, iclass 31, count 2 2006.201.13:16:39.07#ibcon#read 5, iclass 31, count 2 2006.201.13:16:39.07#ibcon#about to read 6, iclass 31, count 2 2006.201.13:16:39.07#ibcon#read 6, iclass 31, count 2 2006.201.13:16:39.07#ibcon#end of sib2, iclass 31, count 2 2006.201.13:16:39.07#ibcon#*after write, iclass 31, count 2 2006.201.13:16:39.07#ibcon#*before return 0, iclass 31, count 2 2006.201.13:16:39.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:39.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:39.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.13:16:39.07#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:39.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:39.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:39.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:39.19#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:16:39.19#ibcon#first serial, iclass 31, count 0 2006.201.13:16:39.19#ibcon#enter sib2, iclass 31, count 0 2006.201.13:16:39.19#ibcon#flushed, iclass 31, count 0 2006.201.13:16:39.19#ibcon#about to write, iclass 31, count 0 2006.201.13:16:39.19#ibcon#wrote, iclass 31, count 0 2006.201.13:16:39.19#ibcon#about to read 3, iclass 31, count 0 2006.201.13:16:39.21#ibcon#read 3, iclass 31, count 0 2006.201.13:16:39.21#ibcon#about to read 4, iclass 31, count 0 2006.201.13:16:39.21#ibcon#read 4, iclass 31, count 0 2006.201.13:16:39.21#ibcon#about to read 5, iclass 31, count 0 2006.201.13:16:39.21#ibcon#read 5, iclass 31, count 0 2006.201.13:16:39.21#ibcon#about to read 6, iclass 31, count 0 2006.201.13:16:39.21#ibcon#read 6, iclass 31, count 0 2006.201.13:16:39.21#ibcon#end of sib2, iclass 31, count 0 2006.201.13:16:39.21#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:16:39.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:16:39.21#ibcon#[25=USB\r\n] 2006.201.13:16:39.21#ibcon#*before write, iclass 31, count 0 2006.201.13:16:39.21#ibcon#enter sib2, iclass 31, count 0 2006.201.13:16:39.21#ibcon#flushed, iclass 31, count 0 2006.201.13:16:39.21#ibcon#about to write, iclass 31, count 0 2006.201.13:16:39.21#ibcon#wrote, iclass 31, count 0 2006.201.13:16:39.21#ibcon#about to read 3, iclass 31, count 0 2006.201.13:16:39.24#ibcon#read 3, iclass 31, count 0 2006.201.13:16:39.24#ibcon#about to read 4, iclass 31, count 0 2006.201.13:16:39.24#ibcon#read 4, iclass 31, count 0 2006.201.13:16:39.24#ibcon#about to read 5, iclass 31, count 0 2006.201.13:16:39.24#ibcon#read 5, iclass 31, count 0 2006.201.13:16:39.24#ibcon#about to read 6, iclass 31, count 0 2006.201.13:16:39.24#ibcon#read 6, iclass 31, count 0 2006.201.13:16:39.24#ibcon#end of sib2, iclass 31, count 0 2006.201.13:16:39.24#ibcon#*after write, iclass 31, count 0 2006.201.13:16:39.24#ibcon#*before return 0, iclass 31, count 0 2006.201.13:16:39.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:39.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:39.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:16:39.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:16:39.24$vck44/valo=8,884.99 2006.201.13:16:39.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.13:16:39.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.13:16:39.24#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:39.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:39.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:39.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:39.24#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:16:39.24#ibcon#first serial, iclass 33, count 0 2006.201.13:16:39.24#ibcon#enter sib2, iclass 33, count 0 2006.201.13:16:39.24#ibcon#flushed, iclass 33, count 0 2006.201.13:16:39.24#ibcon#about to write, iclass 33, count 0 2006.201.13:16:39.24#ibcon#wrote, iclass 33, count 0 2006.201.13:16:39.24#ibcon#about to read 3, iclass 33, count 0 2006.201.13:16:39.26#ibcon#read 3, iclass 33, count 0 2006.201.13:16:39.26#ibcon#about to read 4, iclass 33, count 0 2006.201.13:16:39.26#ibcon#read 4, iclass 33, count 0 2006.201.13:16:39.26#ibcon#about to read 5, iclass 33, count 0 2006.201.13:16:39.26#ibcon#read 5, iclass 33, count 0 2006.201.13:16:39.26#ibcon#about to read 6, iclass 33, count 0 2006.201.13:16:39.26#ibcon#read 6, iclass 33, count 0 2006.201.13:16:39.26#ibcon#end of sib2, iclass 33, count 0 2006.201.13:16:39.26#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:16:39.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:16:39.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:16:39.26#ibcon#*before write, iclass 33, count 0 2006.201.13:16:39.26#ibcon#enter sib2, iclass 33, count 0 2006.201.13:16:39.26#ibcon#flushed, iclass 33, count 0 2006.201.13:16:39.26#ibcon#about to write, iclass 33, count 0 2006.201.13:16:39.26#ibcon#wrote, iclass 33, count 0 2006.201.13:16:39.26#ibcon#about to read 3, iclass 33, count 0 2006.201.13:16:39.30#ibcon#read 3, iclass 33, count 0 2006.201.13:16:39.30#ibcon#about to read 4, iclass 33, count 0 2006.201.13:16:39.30#ibcon#read 4, iclass 33, count 0 2006.201.13:16:39.30#ibcon#about to read 5, iclass 33, count 0 2006.201.13:16:39.30#ibcon#read 5, iclass 33, count 0 2006.201.13:16:39.30#ibcon#about to read 6, iclass 33, count 0 2006.201.13:16:39.30#ibcon#read 6, iclass 33, count 0 2006.201.13:16:39.30#ibcon#end of sib2, iclass 33, count 0 2006.201.13:16:39.30#ibcon#*after write, iclass 33, count 0 2006.201.13:16:39.30#ibcon#*before return 0, iclass 33, count 0 2006.201.13:16:39.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:39.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:39.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:16:39.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:16:39.30$vck44/va=8,4 2006.201.13:16:39.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.13:16:39.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.13:16:39.30#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:39.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:16:39.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:16:39.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:16:39.36#ibcon#enter wrdev, iclass 35, count 2 2006.201.13:16:39.36#ibcon#first serial, iclass 35, count 2 2006.201.13:16:39.36#ibcon#enter sib2, iclass 35, count 2 2006.201.13:16:39.36#ibcon#flushed, iclass 35, count 2 2006.201.13:16:39.36#ibcon#about to write, iclass 35, count 2 2006.201.13:16:39.36#ibcon#wrote, iclass 35, count 2 2006.201.13:16:39.36#ibcon#about to read 3, iclass 35, count 2 2006.201.13:16:39.38#ibcon#read 3, iclass 35, count 2 2006.201.13:16:39.38#ibcon#about to read 4, iclass 35, count 2 2006.201.13:16:39.38#ibcon#read 4, iclass 35, count 2 2006.201.13:16:39.38#ibcon#about to read 5, iclass 35, count 2 2006.201.13:16:39.38#ibcon#read 5, iclass 35, count 2 2006.201.13:16:39.38#ibcon#about to read 6, iclass 35, count 2 2006.201.13:16:39.38#ibcon#read 6, iclass 35, count 2 2006.201.13:16:39.38#ibcon#end of sib2, iclass 35, count 2 2006.201.13:16:39.38#ibcon#*mode == 0, iclass 35, count 2 2006.201.13:16:39.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.13:16:39.38#ibcon#[25=AT08-04\r\n] 2006.201.13:16:39.38#ibcon#*before write, iclass 35, count 2 2006.201.13:16:39.38#ibcon#enter sib2, iclass 35, count 2 2006.201.13:16:39.38#ibcon#flushed, iclass 35, count 2 2006.201.13:16:39.38#ibcon#about to write, iclass 35, count 2 2006.201.13:16:39.38#ibcon#wrote, iclass 35, count 2 2006.201.13:16:39.38#ibcon#about to read 3, iclass 35, count 2 2006.201.13:16:39.42#ibcon#read 3, iclass 35, count 2 2006.201.13:16:39.42#ibcon#about to read 4, iclass 35, count 2 2006.201.13:16:39.42#ibcon#read 4, iclass 35, count 2 2006.201.13:16:39.42#ibcon#about to read 5, iclass 35, count 2 2006.201.13:16:39.42#ibcon#read 5, iclass 35, count 2 2006.201.13:16:39.42#ibcon#about to read 6, iclass 35, count 2 2006.201.13:16:39.42#ibcon#read 6, iclass 35, count 2 2006.201.13:16:39.42#ibcon#end of sib2, iclass 35, count 2 2006.201.13:16:39.42#ibcon#*after write, iclass 35, count 2 2006.201.13:16:39.42#ibcon#*before return 0, iclass 35, count 2 2006.201.13:16:39.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:16:39.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:16:39.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.13:16:39.42#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:39.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:16:39.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:16:39.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:16:39.54#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:16:39.54#ibcon#first serial, iclass 35, count 0 2006.201.13:16:39.54#ibcon#enter sib2, iclass 35, count 0 2006.201.13:16:39.54#ibcon#flushed, iclass 35, count 0 2006.201.13:16:39.54#ibcon#about to write, iclass 35, count 0 2006.201.13:16:39.54#ibcon#wrote, iclass 35, count 0 2006.201.13:16:39.54#ibcon#about to read 3, iclass 35, count 0 2006.201.13:16:39.56#ibcon#read 3, iclass 35, count 0 2006.201.13:16:39.56#ibcon#about to read 4, iclass 35, count 0 2006.201.13:16:39.56#ibcon#read 4, iclass 35, count 0 2006.201.13:16:39.56#ibcon#about to read 5, iclass 35, count 0 2006.201.13:16:39.56#ibcon#read 5, iclass 35, count 0 2006.201.13:16:39.56#ibcon#about to read 6, iclass 35, count 0 2006.201.13:16:39.56#ibcon#read 6, iclass 35, count 0 2006.201.13:16:39.56#ibcon#end of sib2, iclass 35, count 0 2006.201.13:16:39.56#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:16:39.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:16:39.56#ibcon#[25=USB\r\n] 2006.201.13:16:39.56#ibcon#*before write, iclass 35, count 0 2006.201.13:16:39.56#ibcon#enter sib2, iclass 35, count 0 2006.201.13:16:39.56#ibcon#flushed, iclass 35, count 0 2006.201.13:16:39.56#ibcon#about to write, iclass 35, count 0 2006.201.13:16:39.56#ibcon#wrote, iclass 35, count 0 2006.201.13:16:39.56#ibcon#about to read 3, iclass 35, count 0 2006.201.13:16:39.59#ibcon#read 3, iclass 35, count 0 2006.201.13:16:39.59#ibcon#about to read 4, iclass 35, count 0 2006.201.13:16:39.59#ibcon#read 4, iclass 35, count 0 2006.201.13:16:39.59#ibcon#about to read 5, iclass 35, count 0 2006.201.13:16:39.59#ibcon#read 5, iclass 35, count 0 2006.201.13:16:39.59#ibcon#about to read 6, iclass 35, count 0 2006.201.13:16:39.59#ibcon#read 6, iclass 35, count 0 2006.201.13:16:39.59#ibcon#end of sib2, iclass 35, count 0 2006.201.13:16:39.59#ibcon#*after write, iclass 35, count 0 2006.201.13:16:39.59#ibcon#*before return 0, iclass 35, count 0 2006.201.13:16:39.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:16:39.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:16:39.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:16:39.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:16:39.59$vck44/vblo=1,629.99 2006.201.13:16:39.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.13:16:39.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.13:16:39.59#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:39.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:16:39.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:16:39.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:16:39.59#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:16:39.59#ibcon#first serial, iclass 37, count 0 2006.201.13:16:39.59#ibcon#enter sib2, iclass 37, count 0 2006.201.13:16:39.59#ibcon#flushed, iclass 37, count 0 2006.201.13:16:39.59#ibcon#about to write, iclass 37, count 0 2006.201.13:16:39.59#ibcon#wrote, iclass 37, count 0 2006.201.13:16:39.59#ibcon#about to read 3, iclass 37, count 0 2006.201.13:16:39.61#ibcon#read 3, iclass 37, count 0 2006.201.13:16:39.61#ibcon#about to read 4, iclass 37, count 0 2006.201.13:16:39.61#ibcon#read 4, iclass 37, count 0 2006.201.13:16:39.61#ibcon#about to read 5, iclass 37, count 0 2006.201.13:16:39.61#ibcon#read 5, iclass 37, count 0 2006.201.13:16:39.61#ibcon#about to read 6, iclass 37, count 0 2006.201.13:16:39.61#ibcon#read 6, iclass 37, count 0 2006.201.13:16:39.61#ibcon#end of sib2, iclass 37, count 0 2006.201.13:16:39.61#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:16:39.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:16:39.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:16:39.61#ibcon#*before write, iclass 37, count 0 2006.201.13:16:39.61#ibcon#enter sib2, iclass 37, count 0 2006.201.13:16:39.61#ibcon#flushed, iclass 37, count 0 2006.201.13:16:39.61#ibcon#about to write, iclass 37, count 0 2006.201.13:16:39.61#ibcon#wrote, iclass 37, count 0 2006.201.13:16:39.61#ibcon#about to read 3, iclass 37, count 0 2006.201.13:16:39.66#ibcon#read 3, iclass 37, count 0 2006.201.13:16:39.66#ibcon#about to read 4, iclass 37, count 0 2006.201.13:16:39.66#ibcon#read 4, iclass 37, count 0 2006.201.13:16:39.66#ibcon#about to read 5, iclass 37, count 0 2006.201.13:16:39.66#ibcon#read 5, iclass 37, count 0 2006.201.13:16:39.66#ibcon#about to read 6, iclass 37, count 0 2006.201.13:16:39.66#ibcon#read 6, iclass 37, count 0 2006.201.13:16:39.66#ibcon#end of sib2, iclass 37, count 0 2006.201.13:16:39.66#ibcon#*after write, iclass 37, count 0 2006.201.13:16:39.66#ibcon#*before return 0, iclass 37, count 0 2006.201.13:16:39.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:16:39.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:16:39.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:16:39.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:16:39.66$vck44/vb=1,4 2006.201.13:16:39.66#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.13:16:39.66#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.13:16:39.66#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:39.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:16:39.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:16:39.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:16:39.66#ibcon#enter wrdev, iclass 39, count 2 2006.201.13:16:39.66#ibcon#first serial, iclass 39, count 2 2006.201.13:16:39.66#ibcon#enter sib2, iclass 39, count 2 2006.201.13:16:39.66#ibcon#flushed, iclass 39, count 2 2006.201.13:16:39.66#ibcon#about to write, iclass 39, count 2 2006.201.13:16:39.66#ibcon#wrote, iclass 39, count 2 2006.201.13:16:39.66#ibcon#about to read 3, iclass 39, count 2 2006.201.13:16:39.68#ibcon#read 3, iclass 39, count 2 2006.201.13:16:39.68#ibcon#about to read 4, iclass 39, count 2 2006.201.13:16:39.68#ibcon#read 4, iclass 39, count 2 2006.201.13:16:39.68#ibcon#about to read 5, iclass 39, count 2 2006.201.13:16:39.68#ibcon#read 5, iclass 39, count 2 2006.201.13:16:39.68#ibcon#about to read 6, iclass 39, count 2 2006.201.13:16:39.68#ibcon#read 6, iclass 39, count 2 2006.201.13:16:39.68#ibcon#end of sib2, iclass 39, count 2 2006.201.13:16:39.68#ibcon#*mode == 0, iclass 39, count 2 2006.201.13:16:39.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.13:16:39.68#ibcon#[27=AT01-04\r\n] 2006.201.13:16:39.68#ibcon#*before write, iclass 39, count 2 2006.201.13:16:39.68#ibcon#enter sib2, iclass 39, count 2 2006.201.13:16:39.68#ibcon#flushed, iclass 39, count 2 2006.201.13:16:39.68#ibcon#about to write, iclass 39, count 2 2006.201.13:16:39.68#ibcon#wrote, iclass 39, count 2 2006.201.13:16:39.68#ibcon#about to read 3, iclass 39, count 2 2006.201.13:16:39.71#ibcon#read 3, iclass 39, count 2 2006.201.13:16:39.71#ibcon#about to read 4, iclass 39, count 2 2006.201.13:16:39.71#ibcon#read 4, iclass 39, count 2 2006.201.13:16:39.71#ibcon#about to read 5, iclass 39, count 2 2006.201.13:16:39.71#ibcon#read 5, iclass 39, count 2 2006.201.13:16:39.71#ibcon#about to read 6, iclass 39, count 2 2006.201.13:16:39.71#ibcon#read 6, iclass 39, count 2 2006.201.13:16:39.71#ibcon#end of sib2, iclass 39, count 2 2006.201.13:16:39.71#ibcon#*after write, iclass 39, count 2 2006.201.13:16:39.71#ibcon#*before return 0, iclass 39, count 2 2006.201.13:16:39.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:16:39.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:16:39.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.13:16:39.71#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:39.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:16:39.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:16:39.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:16:39.83#ibcon#enter wrdev, iclass 39, count 0 2006.201.13:16:39.83#ibcon#first serial, iclass 39, count 0 2006.201.13:16:39.83#ibcon#enter sib2, iclass 39, count 0 2006.201.13:16:39.83#ibcon#flushed, iclass 39, count 0 2006.201.13:16:39.83#ibcon#about to write, iclass 39, count 0 2006.201.13:16:39.83#ibcon#wrote, iclass 39, count 0 2006.201.13:16:39.83#ibcon#about to read 3, iclass 39, count 0 2006.201.13:16:39.85#ibcon#read 3, iclass 39, count 0 2006.201.13:16:39.85#ibcon#about to read 4, iclass 39, count 0 2006.201.13:16:39.85#ibcon#read 4, iclass 39, count 0 2006.201.13:16:39.85#ibcon#about to read 5, iclass 39, count 0 2006.201.13:16:39.85#ibcon#read 5, iclass 39, count 0 2006.201.13:16:39.85#ibcon#about to read 6, iclass 39, count 0 2006.201.13:16:39.85#ibcon#read 6, iclass 39, count 0 2006.201.13:16:39.85#ibcon#end of sib2, iclass 39, count 0 2006.201.13:16:39.85#ibcon#*mode == 0, iclass 39, count 0 2006.201.13:16:39.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.13:16:39.85#ibcon#[27=USB\r\n] 2006.201.13:16:39.85#ibcon#*before write, iclass 39, count 0 2006.201.13:16:39.85#ibcon#enter sib2, iclass 39, count 0 2006.201.13:16:39.85#ibcon#flushed, iclass 39, count 0 2006.201.13:16:39.85#ibcon#about to write, iclass 39, count 0 2006.201.13:16:39.85#ibcon#wrote, iclass 39, count 0 2006.201.13:16:39.85#ibcon#about to read 3, iclass 39, count 0 2006.201.13:16:39.88#ibcon#read 3, iclass 39, count 0 2006.201.13:16:39.88#ibcon#about to read 4, iclass 39, count 0 2006.201.13:16:39.88#ibcon#read 4, iclass 39, count 0 2006.201.13:16:39.88#ibcon#about to read 5, iclass 39, count 0 2006.201.13:16:39.88#ibcon#read 5, iclass 39, count 0 2006.201.13:16:39.88#ibcon#about to read 6, iclass 39, count 0 2006.201.13:16:39.88#ibcon#read 6, iclass 39, count 0 2006.201.13:16:39.88#ibcon#end of sib2, iclass 39, count 0 2006.201.13:16:39.88#ibcon#*after write, iclass 39, count 0 2006.201.13:16:39.88#ibcon#*before return 0, iclass 39, count 0 2006.201.13:16:39.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:16:39.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:16:39.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.13:16:39.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.13:16:39.88$vck44/vblo=2,634.99 2006.201.13:16:39.88#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.13:16:39.88#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.13:16:39.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:39.88#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:16:39.88#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:16:39.88#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:16:39.88#ibcon#enter wrdev, iclass 2, count 0 2006.201.13:16:39.88#ibcon#first serial, iclass 2, count 0 2006.201.13:16:39.88#ibcon#enter sib2, iclass 2, count 0 2006.201.13:16:39.88#ibcon#flushed, iclass 2, count 0 2006.201.13:16:39.88#ibcon#about to write, iclass 2, count 0 2006.201.13:16:39.88#ibcon#wrote, iclass 2, count 0 2006.201.13:16:39.88#ibcon#about to read 3, iclass 2, count 0 2006.201.13:16:39.90#ibcon#read 3, iclass 2, count 0 2006.201.13:16:39.90#ibcon#about to read 4, iclass 2, count 0 2006.201.13:16:39.90#ibcon#read 4, iclass 2, count 0 2006.201.13:16:39.90#ibcon#about to read 5, iclass 2, count 0 2006.201.13:16:39.90#ibcon#read 5, iclass 2, count 0 2006.201.13:16:39.90#ibcon#about to read 6, iclass 2, count 0 2006.201.13:16:39.90#ibcon#read 6, iclass 2, count 0 2006.201.13:16:39.90#ibcon#end of sib2, iclass 2, count 0 2006.201.13:16:39.90#ibcon#*mode == 0, iclass 2, count 0 2006.201.13:16:39.90#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.13:16:39.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:16:39.90#ibcon#*before write, iclass 2, count 0 2006.201.13:16:39.90#ibcon#enter sib2, iclass 2, count 0 2006.201.13:16:39.90#ibcon#flushed, iclass 2, count 0 2006.201.13:16:39.90#ibcon#about to write, iclass 2, count 0 2006.201.13:16:39.90#ibcon#wrote, iclass 2, count 0 2006.201.13:16:39.90#ibcon#about to read 3, iclass 2, count 0 2006.201.13:16:39.94#ibcon#read 3, iclass 2, count 0 2006.201.13:16:39.94#ibcon#about to read 4, iclass 2, count 0 2006.201.13:16:39.94#ibcon#read 4, iclass 2, count 0 2006.201.13:16:39.94#ibcon#about to read 5, iclass 2, count 0 2006.201.13:16:39.94#ibcon#read 5, iclass 2, count 0 2006.201.13:16:39.94#ibcon#about to read 6, iclass 2, count 0 2006.201.13:16:39.94#ibcon#read 6, iclass 2, count 0 2006.201.13:16:39.94#ibcon#end of sib2, iclass 2, count 0 2006.201.13:16:39.94#ibcon#*after write, iclass 2, count 0 2006.201.13:16:39.94#ibcon#*before return 0, iclass 2, count 0 2006.201.13:16:39.94#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:16:39.94#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:16:39.94#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.13:16:39.94#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.13:16:39.94$vck44/vb=2,5 2006.201.13:16:39.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.13:16:39.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.13:16:39.94#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:39.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:16:40.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:16:40.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:16:40.00#ibcon#enter wrdev, iclass 5, count 2 2006.201.13:16:40.00#ibcon#first serial, iclass 5, count 2 2006.201.13:16:40.00#ibcon#enter sib2, iclass 5, count 2 2006.201.13:16:40.00#ibcon#flushed, iclass 5, count 2 2006.201.13:16:40.00#ibcon#about to write, iclass 5, count 2 2006.201.13:16:40.00#ibcon#wrote, iclass 5, count 2 2006.201.13:16:40.00#ibcon#about to read 3, iclass 5, count 2 2006.201.13:16:40.02#ibcon#read 3, iclass 5, count 2 2006.201.13:16:40.02#ibcon#about to read 4, iclass 5, count 2 2006.201.13:16:40.02#ibcon#read 4, iclass 5, count 2 2006.201.13:16:40.02#ibcon#about to read 5, iclass 5, count 2 2006.201.13:16:40.02#ibcon#read 5, iclass 5, count 2 2006.201.13:16:40.02#ibcon#about to read 6, iclass 5, count 2 2006.201.13:16:40.02#ibcon#read 6, iclass 5, count 2 2006.201.13:16:40.02#ibcon#end of sib2, iclass 5, count 2 2006.201.13:16:40.02#ibcon#*mode == 0, iclass 5, count 2 2006.201.13:16:40.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.13:16:40.02#ibcon#[27=AT02-05\r\n] 2006.201.13:16:40.02#ibcon#*before write, iclass 5, count 2 2006.201.13:16:40.02#ibcon#enter sib2, iclass 5, count 2 2006.201.13:16:40.02#ibcon#flushed, iclass 5, count 2 2006.201.13:16:40.02#ibcon#about to write, iclass 5, count 2 2006.201.13:16:40.02#ibcon#wrote, iclass 5, count 2 2006.201.13:16:40.02#ibcon#about to read 3, iclass 5, count 2 2006.201.13:16:40.05#ibcon#read 3, iclass 5, count 2 2006.201.13:16:40.05#ibcon#about to read 4, iclass 5, count 2 2006.201.13:16:40.05#ibcon#read 4, iclass 5, count 2 2006.201.13:16:40.05#ibcon#about to read 5, iclass 5, count 2 2006.201.13:16:40.05#ibcon#read 5, iclass 5, count 2 2006.201.13:16:40.05#ibcon#about to read 6, iclass 5, count 2 2006.201.13:16:40.05#ibcon#read 6, iclass 5, count 2 2006.201.13:16:40.05#ibcon#end of sib2, iclass 5, count 2 2006.201.13:16:40.05#ibcon#*after write, iclass 5, count 2 2006.201.13:16:40.05#ibcon#*before return 0, iclass 5, count 2 2006.201.13:16:40.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:16:40.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:16:40.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.13:16:40.05#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:40.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:16:40.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:16:40.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:16:40.17#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:16:40.17#ibcon#first serial, iclass 5, count 0 2006.201.13:16:40.17#ibcon#enter sib2, iclass 5, count 0 2006.201.13:16:40.17#ibcon#flushed, iclass 5, count 0 2006.201.13:16:40.17#ibcon#about to write, iclass 5, count 0 2006.201.13:16:40.17#ibcon#wrote, iclass 5, count 0 2006.201.13:16:40.17#ibcon#about to read 3, iclass 5, count 0 2006.201.13:16:40.19#ibcon#read 3, iclass 5, count 0 2006.201.13:16:40.19#ibcon#about to read 4, iclass 5, count 0 2006.201.13:16:40.19#ibcon#read 4, iclass 5, count 0 2006.201.13:16:40.19#ibcon#about to read 5, iclass 5, count 0 2006.201.13:16:40.19#ibcon#read 5, iclass 5, count 0 2006.201.13:16:40.19#ibcon#about to read 6, iclass 5, count 0 2006.201.13:16:40.19#ibcon#read 6, iclass 5, count 0 2006.201.13:16:40.19#ibcon#end of sib2, iclass 5, count 0 2006.201.13:16:40.19#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:16:40.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:16:40.19#ibcon#[27=USB\r\n] 2006.201.13:16:40.19#ibcon#*before write, iclass 5, count 0 2006.201.13:16:40.19#ibcon#enter sib2, iclass 5, count 0 2006.201.13:16:40.19#ibcon#flushed, iclass 5, count 0 2006.201.13:16:40.19#ibcon#about to write, iclass 5, count 0 2006.201.13:16:40.19#ibcon#wrote, iclass 5, count 0 2006.201.13:16:40.19#ibcon#about to read 3, iclass 5, count 0 2006.201.13:16:40.22#ibcon#read 3, iclass 5, count 0 2006.201.13:16:40.22#ibcon#about to read 4, iclass 5, count 0 2006.201.13:16:40.22#ibcon#read 4, iclass 5, count 0 2006.201.13:16:40.22#ibcon#about to read 5, iclass 5, count 0 2006.201.13:16:40.22#ibcon#read 5, iclass 5, count 0 2006.201.13:16:40.22#ibcon#about to read 6, iclass 5, count 0 2006.201.13:16:40.22#ibcon#read 6, iclass 5, count 0 2006.201.13:16:40.22#ibcon#end of sib2, iclass 5, count 0 2006.201.13:16:40.22#ibcon#*after write, iclass 5, count 0 2006.201.13:16:40.22#ibcon#*before return 0, iclass 5, count 0 2006.201.13:16:40.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:16:40.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:16:40.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:16:40.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:16:40.22$vck44/vblo=3,649.99 2006.201.13:16:40.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.13:16:40.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.13:16:40.22#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:40.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:16:40.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:16:40.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:16:40.22#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:16:40.22#ibcon#first serial, iclass 7, count 0 2006.201.13:16:40.22#ibcon#enter sib2, iclass 7, count 0 2006.201.13:16:40.22#ibcon#flushed, iclass 7, count 0 2006.201.13:16:40.22#ibcon#about to write, iclass 7, count 0 2006.201.13:16:40.22#ibcon#wrote, iclass 7, count 0 2006.201.13:16:40.22#ibcon#about to read 3, iclass 7, count 0 2006.201.13:16:40.24#ibcon#read 3, iclass 7, count 0 2006.201.13:16:40.24#ibcon#about to read 4, iclass 7, count 0 2006.201.13:16:40.24#ibcon#read 4, iclass 7, count 0 2006.201.13:16:40.24#ibcon#about to read 5, iclass 7, count 0 2006.201.13:16:40.24#ibcon#read 5, iclass 7, count 0 2006.201.13:16:40.24#ibcon#about to read 6, iclass 7, count 0 2006.201.13:16:40.24#ibcon#read 6, iclass 7, count 0 2006.201.13:16:40.24#ibcon#end of sib2, iclass 7, count 0 2006.201.13:16:40.24#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:16:40.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:16:40.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:16:40.24#ibcon#*before write, iclass 7, count 0 2006.201.13:16:40.24#ibcon#enter sib2, iclass 7, count 0 2006.201.13:16:40.24#ibcon#flushed, iclass 7, count 0 2006.201.13:16:40.24#ibcon#about to write, iclass 7, count 0 2006.201.13:16:40.24#ibcon#wrote, iclass 7, count 0 2006.201.13:16:40.24#ibcon#about to read 3, iclass 7, count 0 2006.201.13:16:40.28#ibcon#read 3, iclass 7, count 0 2006.201.13:16:40.28#ibcon#about to read 4, iclass 7, count 0 2006.201.13:16:40.28#ibcon#read 4, iclass 7, count 0 2006.201.13:16:40.28#ibcon#about to read 5, iclass 7, count 0 2006.201.13:16:40.28#ibcon#read 5, iclass 7, count 0 2006.201.13:16:40.28#ibcon#about to read 6, iclass 7, count 0 2006.201.13:16:40.28#ibcon#read 6, iclass 7, count 0 2006.201.13:16:40.28#ibcon#end of sib2, iclass 7, count 0 2006.201.13:16:40.28#ibcon#*after write, iclass 7, count 0 2006.201.13:16:40.28#ibcon#*before return 0, iclass 7, count 0 2006.201.13:16:40.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:16:40.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:16:40.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:16:40.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:16:40.28$vck44/vb=3,4 2006.201.13:16:40.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.13:16:40.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.13:16:40.28#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:40.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:16:40.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:16:40.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:16:40.34#ibcon#enter wrdev, iclass 11, count 2 2006.201.13:16:40.34#ibcon#first serial, iclass 11, count 2 2006.201.13:16:40.34#ibcon#enter sib2, iclass 11, count 2 2006.201.13:16:40.34#ibcon#flushed, iclass 11, count 2 2006.201.13:16:40.34#ibcon#about to write, iclass 11, count 2 2006.201.13:16:40.34#ibcon#wrote, iclass 11, count 2 2006.201.13:16:40.34#ibcon#about to read 3, iclass 11, count 2 2006.201.13:16:40.36#ibcon#read 3, iclass 11, count 2 2006.201.13:16:40.36#ibcon#about to read 4, iclass 11, count 2 2006.201.13:16:40.36#ibcon#read 4, iclass 11, count 2 2006.201.13:16:40.36#ibcon#about to read 5, iclass 11, count 2 2006.201.13:16:40.36#ibcon#read 5, iclass 11, count 2 2006.201.13:16:40.36#ibcon#about to read 6, iclass 11, count 2 2006.201.13:16:40.36#ibcon#read 6, iclass 11, count 2 2006.201.13:16:40.36#ibcon#end of sib2, iclass 11, count 2 2006.201.13:16:40.36#ibcon#*mode == 0, iclass 11, count 2 2006.201.13:16:40.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.13:16:40.36#ibcon#[27=AT03-04\r\n] 2006.201.13:16:40.36#ibcon#*before write, iclass 11, count 2 2006.201.13:16:40.36#ibcon#enter sib2, iclass 11, count 2 2006.201.13:16:40.36#ibcon#flushed, iclass 11, count 2 2006.201.13:16:40.36#ibcon#about to write, iclass 11, count 2 2006.201.13:16:40.36#ibcon#wrote, iclass 11, count 2 2006.201.13:16:40.36#ibcon#about to read 3, iclass 11, count 2 2006.201.13:16:40.39#ibcon#read 3, iclass 11, count 2 2006.201.13:16:40.39#ibcon#about to read 4, iclass 11, count 2 2006.201.13:16:40.39#ibcon#read 4, iclass 11, count 2 2006.201.13:16:40.39#ibcon#about to read 5, iclass 11, count 2 2006.201.13:16:40.39#ibcon#read 5, iclass 11, count 2 2006.201.13:16:40.39#ibcon#about to read 6, iclass 11, count 2 2006.201.13:16:40.39#ibcon#read 6, iclass 11, count 2 2006.201.13:16:40.39#ibcon#end of sib2, iclass 11, count 2 2006.201.13:16:40.39#ibcon#*after write, iclass 11, count 2 2006.201.13:16:40.39#ibcon#*before return 0, iclass 11, count 2 2006.201.13:16:40.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:16:40.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:16:40.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.13:16:40.39#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:40.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:16:40.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:16:40.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:16:40.51#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:16:40.51#ibcon#first serial, iclass 11, count 0 2006.201.13:16:40.51#ibcon#enter sib2, iclass 11, count 0 2006.201.13:16:40.51#ibcon#flushed, iclass 11, count 0 2006.201.13:16:40.51#ibcon#about to write, iclass 11, count 0 2006.201.13:16:40.51#ibcon#wrote, iclass 11, count 0 2006.201.13:16:40.51#ibcon#about to read 3, iclass 11, count 0 2006.201.13:16:40.53#ibcon#read 3, iclass 11, count 0 2006.201.13:16:40.53#ibcon#about to read 4, iclass 11, count 0 2006.201.13:16:40.53#ibcon#read 4, iclass 11, count 0 2006.201.13:16:40.53#ibcon#about to read 5, iclass 11, count 0 2006.201.13:16:40.53#ibcon#read 5, iclass 11, count 0 2006.201.13:16:40.53#ibcon#about to read 6, iclass 11, count 0 2006.201.13:16:40.53#ibcon#read 6, iclass 11, count 0 2006.201.13:16:40.53#ibcon#end of sib2, iclass 11, count 0 2006.201.13:16:40.53#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:16:40.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:16:40.53#ibcon#[27=USB\r\n] 2006.201.13:16:40.53#ibcon#*before write, iclass 11, count 0 2006.201.13:16:40.53#ibcon#enter sib2, iclass 11, count 0 2006.201.13:16:40.53#ibcon#flushed, iclass 11, count 0 2006.201.13:16:40.53#ibcon#about to write, iclass 11, count 0 2006.201.13:16:40.53#ibcon#wrote, iclass 11, count 0 2006.201.13:16:40.53#ibcon#about to read 3, iclass 11, count 0 2006.201.13:16:40.56#ibcon#read 3, iclass 11, count 0 2006.201.13:16:40.56#ibcon#about to read 4, iclass 11, count 0 2006.201.13:16:40.56#ibcon#read 4, iclass 11, count 0 2006.201.13:16:40.56#ibcon#about to read 5, iclass 11, count 0 2006.201.13:16:40.56#ibcon#read 5, iclass 11, count 0 2006.201.13:16:40.56#ibcon#about to read 6, iclass 11, count 0 2006.201.13:16:40.56#ibcon#read 6, iclass 11, count 0 2006.201.13:16:40.56#ibcon#end of sib2, iclass 11, count 0 2006.201.13:16:40.56#ibcon#*after write, iclass 11, count 0 2006.201.13:16:40.56#ibcon#*before return 0, iclass 11, count 0 2006.201.13:16:40.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:16:40.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:16:40.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:16:40.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:16:40.56$vck44/vblo=4,679.99 2006.201.13:16:40.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.13:16:40.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.13:16:40.56#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:40.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:16:40.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:16:40.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:16:40.56#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:16:40.56#ibcon#first serial, iclass 13, count 0 2006.201.13:16:40.56#ibcon#enter sib2, iclass 13, count 0 2006.201.13:16:40.56#ibcon#flushed, iclass 13, count 0 2006.201.13:16:40.56#ibcon#about to write, iclass 13, count 0 2006.201.13:16:40.56#ibcon#wrote, iclass 13, count 0 2006.201.13:16:40.56#ibcon#about to read 3, iclass 13, count 0 2006.201.13:16:40.58#ibcon#read 3, iclass 13, count 0 2006.201.13:16:40.58#ibcon#about to read 4, iclass 13, count 0 2006.201.13:16:40.58#ibcon#read 4, iclass 13, count 0 2006.201.13:16:40.58#ibcon#about to read 5, iclass 13, count 0 2006.201.13:16:40.58#ibcon#read 5, iclass 13, count 0 2006.201.13:16:40.58#ibcon#about to read 6, iclass 13, count 0 2006.201.13:16:40.58#ibcon#read 6, iclass 13, count 0 2006.201.13:16:40.58#ibcon#end of sib2, iclass 13, count 0 2006.201.13:16:40.58#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:16:40.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:16:40.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:16:40.58#ibcon#*before write, iclass 13, count 0 2006.201.13:16:40.58#ibcon#enter sib2, iclass 13, count 0 2006.201.13:16:40.58#ibcon#flushed, iclass 13, count 0 2006.201.13:16:40.58#ibcon#about to write, iclass 13, count 0 2006.201.13:16:40.58#ibcon#wrote, iclass 13, count 0 2006.201.13:16:40.58#ibcon#about to read 3, iclass 13, count 0 2006.201.13:16:40.62#ibcon#read 3, iclass 13, count 0 2006.201.13:16:40.62#ibcon#about to read 4, iclass 13, count 0 2006.201.13:16:40.62#ibcon#read 4, iclass 13, count 0 2006.201.13:16:40.62#ibcon#about to read 5, iclass 13, count 0 2006.201.13:16:40.62#ibcon#read 5, iclass 13, count 0 2006.201.13:16:40.62#ibcon#about to read 6, iclass 13, count 0 2006.201.13:16:40.62#ibcon#read 6, iclass 13, count 0 2006.201.13:16:40.62#ibcon#end of sib2, iclass 13, count 0 2006.201.13:16:40.62#ibcon#*after write, iclass 13, count 0 2006.201.13:16:40.62#ibcon#*before return 0, iclass 13, count 0 2006.201.13:16:40.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:16:40.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:16:40.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:16:40.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:16:40.62$vck44/vb=4,5 2006.201.13:16:40.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.13:16:40.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.13:16:40.62#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:40.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:16:40.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:16:40.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:16:40.68#ibcon#enter wrdev, iclass 15, count 2 2006.201.13:16:40.68#ibcon#first serial, iclass 15, count 2 2006.201.13:16:40.68#ibcon#enter sib2, iclass 15, count 2 2006.201.13:16:40.68#ibcon#flushed, iclass 15, count 2 2006.201.13:16:40.68#ibcon#about to write, iclass 15, count 2 2006.201.13:16:40.68#ibcon#wrote, iclass 15, count 2 2006.201.13:16:40.68#ibcon#about to read 3, iclass 15, count 2 2006.201.13:16:40.70#ibcon#read 3, iclass 15, count 2 2006.201.13:16:40.70#ibcon#about to read 4, iclass 15, count 2 2006.201.13:16:40.70#ibcon#read 4, iclass 15, count 2 2006.201.13:16:40.70#ibcon#about to read 5, iclass 15, count 2 2006.201.13:16:40.70#ibcon#read 5, iclass 15, count 2 2006.201.13:16:40.70#ibcon#about to read 6, iclass 15, count 2 2006.201.13:16:40.70#ibcon#read 6, iclass 15, count 2 2006.201.13:16:40.70#ibcon#end of sib2, iclass 15, count 2 2006.201.13:16:40.70#ibcon#*mode == 0, iclass 15, count 2 2006.201.13:16:40.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.13:16:40.70#ibcon#[27=AT04-05\r\n] 2006.201.13:16:40.70#ibcon#*before write, iclass 15, count 2 2006.201.13:16:40.70#ibcon#enter sib2, iclass 15, count 2 2006.201.13:16:40.70#ibcon#flushed, iclass 15, count 2 2006.201.13:16:40.70#ibcon#about to write, iclass 15, count 2 2006.201.13:16:40.70#ibcon#wrote, iclass 15, count 2 2006.201.13:16:40.70#ibcon#about to read 3, iclass 15, count 2 2006.201.13:16:40.73#ibcon#read 3, iclass 15, count 2 2006.201.13:16:40.73#ibcon#about to read 4, iclass 15, count 2 2006.201.13:16:40.73#ibcon#read 4, iclass 15, count 2 2006.201.13:16:40.73#ibcon#about to read 5, iclass 15, count 2 2006.201.13:16:40.73#ibcon#read 5, iclass 15, count 2 2006.201.13:16:40.73#ibcon#about to read 6, iclass 15, count 2 2006.201.13:16:40.73#ibcon#read 6, iclass 15, count 2 2006.201.13:16:40.73#ibcon#end of sib2, iclass 15, count 2 2006.201.13:16:40.73#ibcon#*after write, iclass 15, count 2 2006.201.13:16:40.73#ibcon#*before return 0, iclass 15, count 2 2006.201.13:16:40.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:16:40.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:16:40.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.13:16:40.73#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:40.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:16:40.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:16:40.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:16:40.85#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:16:40.85#ibcon#first serial, iclass 15, count 0 2006.201.13:16:40.85#ibcon#enter sib2, iclass 15, count 0 2006.201.13:16:40.85#ibcon#flushed, iclass 15, count 0 2006.201.13:16:40.85#ibcon#about to write, iclass 15, count 0 2006.201.13:16:40.85#ibcon#wrote, iclass 15, count 0 2006.201.13:16:40.85#ibcon#about to read 3, iclass 15, count 0 2006.201.13:16:40.87#ibcon#read 3, iclass 15, count 0 2006.201.13:16:40.87#ibcon#about to read 4, iclass 15, count 0 2006.201.13:16:40.87#ibcon#read 4, iclass 15, count 0 2006.201.13:16:40.87#ibcon#about to read 5, iclass 15, count 0 2006.201.13:16:40.87#ibcon#read 5, iclass 15, count 0 2006.201.13:16:40.87#ibcon#about to read 6, iclass 15, count 0 2006.201.13:16:40.87#ibcon#read 6, iclass 15, count 0 2006.201.13:16:40.87#ibcon#end of sib2, iclass 15, count 0 2006.201.13:16:40.87#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:16:40.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:16:40.87#ibcon#[27=USB\r\n] 2006.201.13:16:40.87#ibcon#*before write, iclass 15, count 0 2006.201.13:16:40.87#ibcon#enter sib2, iclass 15, count 0 2006.201.13:16:40.87#ibcon#flushed, iclass 15, count 0 2006.201.13:16:40.87#ibcon#about to write, iclass 15, count 0 2006.201.13:16:40.87#ibcon#wrote, iclass 15, count 0 2006.201.13:16:40.87#ibcon#about to read 3, iclass 15, count 0 2006.201.13:16:40.90#ibcon#read 3, iclass 15, count 0 2006.201.13:16:40.90#ibcon#about to read 4, iclass 15, count 0 2006.201.13:16:40.90#ibcon#read 4, iclass 15, count 0 2006.201.13:16:40.90#ibcon#about to read 5, iclass 15, count 0 2006.201.13:16:40.90#ibcon#read 5, iclass 15, count 0 2006.201.13:16:40.90#ibcon#about to read 6, iclass 15, count 0 2006.201.13:16:40.90#ibcon#read 6, iclass 15, count 0 2006.201.13:16:40.90#ibcon#end of sib2, iclass 15, count 0 2006.201.13:16:40.90#ibcon#*after write, iclass 15, count 0 2006.201.13:16:40.90#ibcon#*before return 0, iclass 15, count 0 2006.201.13:16:40.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:16:40.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:16:40.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:16:40.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:16:40.90$vck44/vblo=5,709.99 2006.201.13:16:40.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.13:16:40.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.13:16:40.90#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:40.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:16:40.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:16:40.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:16:40.90#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:16:40.90#ibcon#first serial, iclass 17, count 0 2006.201.13:16:40.90#ibcon#enter sib2, iclass 17, count 0 2006.201.13:16:40.90#ibcon#flushed, iclass 17, count 0 2006.201.13:16:40.90#ibcon#about to write, iclass 17, count 0 2006.201.13:16:40.90#ibcon#wrote, iclass 17, count 0 2006.201.13:16:40.90#ibcon#about to read 3, iclass 17, count 0 2006.201.13:16:40.92#ibcon#read 3, iclass 17, count 0 2006.201.13:16:40.92#ibcon#about to read 4, iclass 17, count 0 2006.201.13:16:40.92#ibcon#read 4, iclass 17, count 0 2006.201.13:16:40.92#ibcon#about to read 5, iclass 17, count 0 2006.201.13:16:40.92#ibcon#read 5, iclass 17, count 0 2006.201.13:16:40.92#ibcon#about to read 6, iclass 17, count 0 2006.201.13:16:40.92#ibcon#read 6, iclass 17, count 0 2006.201.13:16:40.92#ibcon#end of sib2, iclass 17, count 0 2006.201.13:16:40.92#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:16:40.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:16:40.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:16:40.92#ibcon#*before write, iclass 17, count 0 2006.201.13:16:40.92#ibcon#enter sib2, iclass 17, count 0 2006.201.13:16:40.92#ibcon#flushed, iclass 17, count 0 2006.201.13:16:40.92#ibcon#about to write, iclass 17, count 0 2006.201.13:16:40.92#ibcon#wrote, iclass 17, count 0 2006.201.13:16:40.92#ibcon#about to read 3, iclass 17, count 0 2006.201.13:16:40.96#ibcon#read 3, iclass 17, count 0 2006.201.13:16:40.96#ibcon#about to read 4, iclass 17, count 0 2006.201.13:16:40.96#ibcon#read 4, iclass 17, count 0 2006.201.13:16:40.96#ibcon#about to read 5, iclass 17, count 0 2006.201.13:16:40.96#ibcon#read 5, iclass 17, count 0 2006.201.13:16:40.96#ibcon#about to read 6, iclass 17, count 0 2006.201.13:16:40.96#ibcon#read 6, iclass 17, count 0 2006.201.13:16:40.96#ibcon#end of sib2, iclass 17, count 0 2006.201.13:16:40.96#ibcon#*after write, iclass 17, count 0 2006.201.13:16:40.96#ibcon#*before return 0, iclass 17, count 0 2006.201.13:16:40.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:16:40.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:16:40.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:16:40.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:16:40.96$vck44/vb=5,4 2006.201.13:16:40.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.13:16:40.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.13:16:40.96#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:40.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:41.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:41.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:41.02#ibcon#enter wrdev, iclass 19, count 2 2006.201.13:16:41.02#ibcon#first serial, iclass 19, count 2 2006.201.13:16:41.02#ibcon#enter sib2, iclass 19, count 2 2006.201.13:16:41.02#ibcon#flushed, iclass 19, count 2 2006.201.13:16:41.02#ibcon#about to write, iclass 19, count 2 2006.201.13:16:41.02#ibcon#wrote, iclass 19, count 2 2006.201.13:16:41.02#ibcon#about to read 3, iclass 19, count 2 2006.201.13:16:41.04#ibcon#read 3, iclass 19, count 2 2006.201.13:16:41.04#ibcon#about to read 4, iclass 19, count 2 2006.201.13:16:41.04#ibcon#read 4, iclass 19, count 2 2006.201.13:16:41.04#ibcon#about to read 5, iclass 19, count 2 2006.201.13:16:41.04#ibcon#read 5, iclass 19, count 2 2006.201.13:16:41.04#ibcon#about to read 6, iclass 19, count 2 2006.201.13:16:41.04#ibcon#read 6, iclass 19, count 2 2006.201.13:16:41.04#ibcon#end of sib2, iclass 19, count 2 2006.201.13:16:41.04#ibcon#*mode == 0, iclass 19, count 2 2006.201.13:16:41.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.13:16:41.04#ibcon#[27=AT05-04\r\n] 2006.201.13:16:41.04#ibcon#*before write, iclass 19, count 2 2006.201.13:16:41.04#ibcon#enter sib2, iclass 19, count 2 2006.201.13:16:41.04#ibcon#flushed, iclass 19, count 2 2006.201.13:16:41.04#ibcon#about to write, iclass 19, count 2 2006.201.13:16:41.04#ibcon#wrote, iclass 19, count 2 2006.201.13:16:41.04#ibcon#about to read 3, iclass 19, count 2 2006.201.13:16:41.07#ibcon#read 3, iclass 19, count 2 2006.201.13:16:41.07#ibcon#about to read 4, iclass 19, count 2 2006.201.13:16:41.07#ibcon#read 4, iclass 19, count 2 2006.201.13:16:41.07#ibcon#about to read 5, iclass 19, count 2 2006.201.13:16:41.07#ibcon#read 5, iclass 19, count 2 2006.201.13:16:41.07#ibcon#about to read 6, iclass 19, count 2 2006.201.13:16:41.07#ibcon#read 6, iclass 19, count 2 2006.201.13:16:41.07#ibcon#end of sib2, iclass 19, count 2 2006.201.13:16:41.07#ibcon#*after write, iclass 19, count 2 2006.201.13:16:41.07#ibcon#*before return 0, iclass 19, count 2 2006.201.13:16:41.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:41.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:16:41.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.13:16:41.07#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:41.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:41.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:41.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:41.19#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:16:41.19#ibcon#first serial, iclass 19, count 0 2006.201.13:16:41.19#ibcon#enter sib2, iclass 19, count 0 2006.201.13:16:41.19#ibcon#flushed, iclass 19, count 0 2006.201.13:16:41.19#ibcon#about to write, iclass 19, count 0 2006.201.13:16:41.19#ibcon#wrote, iclass 19, count 0 2006.201.13:16:41.19#ibcon#about to read 3, iclass 19, count 0 2006.201.13:16:41.22#ibcon#read 3, iclass 19, count 0 2006.201.13:16:41.22#ibcon#about to read 4, iclass 19, count 0 2006.201.13:16:41.22#ibcon#read 4, iclass 19, count 0 2006.201.13:16:41.22#ibcon#about to read 5, iclass 19, count 0 2006.201.13:16:41.22#ibcon#read 5, iclass 19, count 0 2006.201.13:16:41.22#ibcon#about to read 6, iclass 19, count 0 2006.201.13:16:41.22#ibcon#read 6, iclass 19, count 0 2006.201.13:16:41.22#ibcon#end of sib2, iclass 19, count 0 2006.201.13:16:41.22#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:16:41.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:16:41.22#ibcon#[27=USB\r\n] 2006.201.13:16:41.22#ibcon#*before write, iclass 19, count 0 2006.201.13:16:41.22#ibcon#enter sib2, iclass 19, count 0 2006.201.13:16:41.22#ibcon#flushed, iclass 19, count 0 2006.201.13:16:41.22#ibcon#about to write, iclass 19, count 0 2006.201.13:16:41.22#ibcon#wrote, iclass 19, count 0 2006.201.13:16:41.22#ibcon#about to read 3, iclass 19, count 0 2006.201.13:16:41.25#ibcon#read 3, iclass 19, count 0 2006.201.13:16:41.25#ibcon#about to read 4, iclass 19, count 0 2006.201.13:16:41.25#ibcon#read 4, iclass 19, count 0 2006.201.13:16:41.25#ibcon#about to read 5, iclass 19, count 0 2006.201.13:16:41.25#ibcon#read 5, iclass 19, count 0 2006.201.13:16:41.25#ibcon#about to read 6, iclass 19, count 0 2006.201.13:16:41.25#ibcon#read 6, iclass 19, count 0 2006.201.13:16:41.25#ibcon#end of sib2, iclass 19, count 0 2006.201.13:16:41.25#ibcon#*after write, iclass 19, count 0 2006.201.13:16:41.25#ibcon#*before return 0, iclass 19, count 0 2006.201.13:16:41.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:41.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:16:41.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:16:41.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:16:41.25$vck44/vblo=6,719.99 2006.201.13:16:41.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.13:16:41.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.13:16:41.25#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:41.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:41.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:41.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:41.25#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:16:41.25#ibcon#first serial, iclass 21, count 0 2006.201.13:16:41.25#ibcon#enter sib2, iclass 21, count 0 2006.201.13:16:41.25#ibcon#flushed, iclass 21, count 0 2006.201.13:16:41.25#ibcon#about to write, iclass 21, count 0 2006.201.13:16:41.25#ibcon#wrote, iclass 21, count 0 2006.201.13:16:41.25#ibcon#about to read 3, iclass 21, count 0 2006.201.13:16:41.27#ibcon#read 3, iclass 21, count 0 2006.201.13:16:41.27#ibcon#about to read 4, iclass 21, count 0 2006.201.13:16:41.27#ibcon#read 4, iclass 21, count 0 2006.201.13:16:41.27#ibcon#about to read 5, iclass 21, count 0 2006.201.13:16:41.27#ibcon#read 5, iclass 21, count 0 2006.201.13:16:41.27#ibcon#about to read 6, iclass 21, count 0 2006.201.13:16:41.27#ibcon#read 6, iclass 21, count 0 2006.201.13:16:41.27#ibcon#end of sib2, iclass 21, count 0 2006.201.13:16:41.27#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:16:41.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:16:41.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:16:41.27#ibcon#*before write, iclass 21, count 0 2006.201.13:16:41.27#ibcon#enter sib2, iclass 21, count 0 2006.201.13:16:41.27#ibcon#flushed, iclass 21, count 0 2006.201.13:16:41.27#ibcon#about to write, iclass 21, count 0 2006.201.13:16:41.27#ibcon#wrote, iclass 21, count 0 2006.201.13:16:41.27#ibcon#about to read 3, iclass 21, count 0 2006.201.13:16:41.31#ibcon#read 3, iclass 21, count 0 2006.201.13:16:41.31#ibcon#about to read 4, iclass 21, count 0 2006.201.13:16:41.31#ibcon#read 4, iclass 21, count 0 2006.201.13:16:41.31#ibcon#about to read 5, iclass 21, count 0 2006.201.13:16:41.31#ibcon#read 5, iclass 21, count 0 2006.201.13:16:41.31#ibcon#about to read 6, iclass 21, count 0 2006.201.13:16:41.31#ibcon#read 6, iclass 21, count 0 2006.201.13:16:41.31#ibcon#end of sib2, iclass 21, count 0 2006.201.13:16:41.31#ibcon#*after write, iclass 21, count 0 2006.201.13:16:41.31#ibcon#*before return 0, iclass 21, count 0 2006.201.13:16:41.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:41.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:16:41.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:16:41.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:16:41.31$vck44/vb=6,4 2006.201.13:16:41.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.13:16:41.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.13:16:41.31#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:41.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:41.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:41.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:41.37#ibcon#enter wrdev, iclass 23, count 2 2006.201.13:16:41.37#ibcon#first serial, iclass 23, count 2 2006.201.13:16:41.37#ibcon#enter sib2, iclass 23, count 2 2006.201.13:16:41.37#ibcon#flushed, iclass 23, count 2 2006.201.13:16:41.37#ibcon#about to write, iclass 23, count 2 2006.201.13:16:41.37#ibcon#wrote, iclass 23, count 2 2006.201.13:16:41.37#ibcon#about to read 3, iclass 23, count 2 2006.201.13:16:41.39#ibcon#read 3, iclass 23, count 2 2006.201.13:16:41.39#ibcon#about to read 4, iclass 23, count 2 2006.201.13:16:41.39#ibcon#read 4, iclass 23, count 2 2006.201.13:16:41.39#ibcon#about to read 5, iclass 23, count 2 2006.201.13:16:41.39#ibcon#read 5, iclass 23, count 2 2006.201.13:16:41.39#ibcon#about to read 6, iclass 23, count 2 2006.201.13:16:41.39#ibcon#read 6, iclass 23, count 2 2006.201.13:16:41.39#ibcon#end of sib2, iclass 23, count 2 2006.201.13:16:41.39#ibcon#*mode == 0, iclass 23, count 2 2006.201.13:16:41.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.13:16:41.39#ibcon#[27=AT06-04\r\n] 2006.201.13:16:41.39#ibcon#*before write, iclass 23, count 2 2006.201.13:16:41.39#ibcon#enter sib2, iclass 23, count 2 2006.201.13:16:41.39#ibcon#flushed, iclass 23, count 2 2006.201.13:16:41.39#ibcon#about to write, iclass 23, count 2 2006.201.13:16:41.39#ibcon#wrote, iclass 23, count 2 2006.201.13:16:41.39#ibcon#about to read 3, iclass 23, count 2 2006.201.13:16:41.42#ibcon#read 3, iclass 23, count 2 2006.201.13:16:41.42#ibcon#about to read 4, iclass 23, count 2 2006.201.13:16:41.42#ibcon#read 4, iclass 23, count 2 2006.201.13:16:41.42#ibcon#about to read 5, iclass 23, count 2 2006.201.13:16:41.42#ibcon#read 5, iclass 23, count 2 2006.201.13:16:41.42#ibcon#about to read 6, iclass 23, count 2 2006.201.13:16:41.42#ibcon#read 6, iclass 23, count 2 2006.201.13:16:41.42#ibcon#end of sib2, iclass 23, count 2 2006.201.13:16:41.42#ibcon#*after write, iclass 23, count 2 2006.201.13:16:41.42#ibcon#*before return 0, iclass 23, count 2 2006.201.13:16:41.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:41.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:16:41.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.13:16:41.42#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:41.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:41.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:41.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:41.54#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:16:41.54#ibcon#first serial, iclass 23, count 0 2006.201.13:16:41.54#ibcon#enter sib2, iclass 23, count 0 2006.201.13:16:41.54#ibcon#flushed, iclass 23, count 0 2006.201.13:16:41.54#ibcon#about to write, iclass 23, count 0 2006.201.13:16:41.54#ibcon#wrote, iclass 23, count 0 2006.201.13:16:41.54#ibcon#about to read 3, iclass 23, count 0 2006.201.13:16:41.56#ibcon#read 3, iclass 23, count 0 2006.201.13:16:41.56#ibcon#about to read 4, iclass 23, count 0 2006.201.13:16:41.56#ibcon#read 4, iclass 23, count 0 2006.201.13:16:41.56#ibcon#about to read 5, iclass 23, count 0 2006.201.13:16:41.56#ibcon#read 5, iclass 23, count 0 2006.201.13:16:41.56#ibcon#about to read 6, iclass 23, count 0 2006.201.13:16:41.56#ibcon#read 6, iclass 23, count 0 2006.201.13:16:41.56#ibcon#end of sib2, iclass 23, count 0 2006.201.13:16:41.56#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:16:41.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:16:41.56#ibcon#[27=USB\r\n] 2006.201.13:16:41.56#ibcon#*before write, iclass 23, count 0 2006.201.13:16:41.56#ibcon#enter sib2, iclass 23, count 0 2006.201.13:16:41.56#ibcon#flushed, iclass 23, count 0 2006.201.13:16:41.56#ibcon#about to write, iclass 23, count 0 2006.201.13:16:41.56#ibcon#wrote, iclass 23, count 0 2006.201.13:16:41.56#ibcon#about to read 3, iclass 23, count 0 2006.201.13:16:41.59#ibcon#read 3, iclass 23, count 0 2006.201.13:16:41.59#ibcon#about to read 4, iclass 23, count 0 2006.201.13:16:41.59#ibcon#read 4, iclass 23, count 0 2006.201.13:16:41.59#ibcon#about to read 5, iclass 23, count 0 2006.201.13:16:41.59#ibcon#read 5, iclass 23, count 0 2006.201.13:16:41.59#ibcon#about to read 6, iclass 23, count 0 2006.201.13:16:41.59#ibcon#read 6, iclass 23, count 0 2006.201.13:16:41.59#ibcon#end of sib2, iclass 23, count 0 2006.201.13:16:41.59#ibcon#*after write, iclass 23, count 0 2006.201.13:16:41.59#ibcon#*before return 0, iclass 23, count 0 2006.201.13:16:41.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:41.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:16:41.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:16:41.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:16:41.59$vck44/vblo=7,734.99 2006.201.13:16:41.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.13:16:41.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.13:16:41.59#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:41.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:41.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:41.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:41.59#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:16:41.59#ibcon#first serial, iclass 25, count 0 2006.201.13:16:41.59#ibcon#enter sib2, iclass 25, count 0 2006.201.13:16:41.59#ibcon#flushed, iclass 25, count 0 2006.201.13:16:41.59#ibcon#about to write, iclass 25, count 0 2006.201.13:16:41.59#ibcon#wrote, iclass 25, count 0 2006.201.13:16:41.59#ibcon#about to read 3, iclass 25, count 0 2006.201.13:16:41.61#ibcon#read 3, iclass 25, count 0 2006.201.13:16:41.61#ibcon#about to read 4, iclass 25, count 0 2006.201.13:16:41.61#ibcon#read 4, iclass 25, count 0 2006.201.13:16:41.61#ibcon#about to read 5, iclass 25, count 0 2006.201.13:16:41.61#ibcon#read 5, iclass 25, count 0 2006.201.13:16:41.61#ibcon#about to read 6, iclass 25, count 0 2006.201.13:16:41.61#ibcon#read 6, iclass 25, count 0 2006.201.13:16:41.61#ibcon#end of sib2, iclass 25, count 0 2006.201.13:16:41.61#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:16:41.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:16:41.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:16:41.61#ibcon#*before write, iclass 25, count 0 2006.201.13:16:41.61#ibcon#enter sib2, iclass 25, count 0 2006.201.13:16:41.61#ibcon#flushed, iclass 25, count 0 2006.201.13:16:41.61#ibcon#about to write, iclass 25, count 0 2006.201.13:16:41.61#ibcon#wrote, iclass 25, count 0 2006.201.13:16:41.61#ibcon#about to read 3, iclass 25, count 0 2006.201.13:16:41.65#ibcon#read 3, iclass 25, count 0 2006.201.13:16:41.65#ibcon#about to read 4, iclass 25, count 0 2006.201.13:16:41.65#ibcon#read 4, iclass 25, count 0 2006.201.13:16:41.65#ibcon#about to read 5, iclass 25, count 0 2006.201.13:16:41.65#ibcon#read 5, iclass 25, count 0 2006.201.13:16:41.65#ibcon#about to read 6, iclass 25, count 0 2006.201.13:16:41.65#ibcon#read 6, iclass 25, count 0 2006.201.13:16:41.65#ibcon#end of sib2, iclass 25, count 0 2006.201.13:16:41.65#ibcon#*after write, iclass 25, count 0 2006.201.13:16:41.65#ibcon#*before return 0, iclass 25, count 0 2006.201.13:16:41.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:41.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:16:41.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:16:41.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:16:41.65$vck44/vb=7,4 2006.201.13:16:41.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.13:16:41.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.13:16:41.65#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:41.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:41.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:41.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:41.71#ibcon#enter wrdev, iclass 27, count 2 2006.201.13:16:41.71#ibcon#first serial, iclass 27, count 2 2006.201.13:16:41.71#ibcon#enter sib2, iclass 27, count 2 2006.201.13:16:41.71#ibcon#flushed, iclass 27, count 2 2006.201.13:16:41.71#ibcon#about to write, iclass 27, count 2 2006.201.13:16:41.71#ibcon#wrote, iclass 27, count 2 2006.201.13:16:41.71#ibcon#about to read 3, iclass 27, count 2 2006.201.13:16:41.73#ibcon#read 3, iclass 27, count 2 2006.201.13:16:41.73#ibcon#about to read 4, iclass 27, count 2 2006.201.13:16:41.73#ibcon#read 4, iclass 27, count 2 2006.201.13:16:41.73#ibcon#about to read 5, iclass 27, count 2 2006.201.13:16:41.73#ibcon#read 5, iclass 27, count 2 2006.201.13:16:41.73#ibcon#about to read 6, iclass 27, count 2 2006.201.13:16:41.73#ibcon#read 6, iclass 27, count 2 2006.201.13:16:41.73#ibcon#end of sib2, iclass 27, count 2 2006.201.13:16:41.73#ibcon#*mode == 0, iclass 27, count 2 2006.201.13:16:41.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.13:16:41.73#ibcon#[27=AT07-04\r\n] 2006.201.13:16:41.73#ibcon#*before write, iclass 27, count 2 2006.201.13:16:41.73#ibcon#enter sib2, iclass 27, count 2 2006.201.13:16:41.73#ibcon#flushed, iclass 27, count 2 2006.201.13:16:41.73#ibcon#about to write, iclass 27, count 2 2006.201.13:16:41.73#ibcon#wrote, iclass 27, count 2 2006.201.13:16:41.73#ibcon#about to read 3, iclass 27, count 2 2006.201.13:16:41.76#ibcon#read 3, iclass 27, count 2 2006.201.13:16:41.76#ibcon#about to read 4, iclass 27, count 2 2006.201.13:16:41.76#ibcon#read 4, iclass 27, count 2 2006.201.13:16:41.76#ibcon#about to read 5, iclass 27, count 2 2006.201.13:16:41.76#ibcon#read 5, iclass 27, count 2 2006.201.13:16:41.76#ibcon#about to read 6, iclass 27, count 2 2006.201.13:16:41.76#ibcon#read 6, iclass 27, count 2 2006.201.13:16:41.76#ibcon#end of sib2, iclass 27, count 2 2006.201.13:16:41.76#ibcon#*after write, iclass 27, count 2 2006.201.13:16:41.76#ibcon#*before return 0, iclass 27, count 2 2006.201.13:16:41.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:41.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:16:41.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.13:16:41.76#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:41.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:41.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:41.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:41.88#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:16:41.88#ibcon#first serial, iclass 27, count 0 2006.201.13:16:41.88#ibcon#enter sib2, iclass 27, count 0 2006.201.13:16:41.88#ibcon#flushed, iclass 27, count 0 2006.201.13:16:41.88#ibcon#about to write, iclass 27, count 0 2006.201.13:16:41.88#ibcon#wrote, iclass 27, count 0 2006.201.13:16:41.88#ibcon#about to read 3, iclass 27, count 0 2006.201.13:16:41.90#ibcon#read 3, iclass 27, count 0 2006.201.13:16:41.90#ibcon#about to read 4, iclass 27, count 0 2006.201.13:16:41.90#ibcon#read 4, iclass 27, count 0 2006.201.13:16:41.90#ibcon#about to read 5, iclass 27, count 0 2006.201.13:16:41.90#ibcon#read 5, iclass 27, count 0 2006.201.13:16:41.90#ibcon#about to read 6, iclass 27, count 0 2006.201.13:16:41.90#ibcon#read 6, iclass 27, count 0 2006.201.13:16:41.90#ibcon#end of sib2, iclass 27, count 0 2006.201.13:16:41.90#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:16:41.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:16:41.90#ibcon#[27=USB\r\n] 2006.201.13:16:41.90#ibcon#*before write, iclass 27, count 0 2006.201.13:16:41.90#ibcon#enter sib2, iclass 27, count 0 2006.201.13:16:41.90#ibcon#flushed, iclass 27, count 0 2006.201.13:16:41.90#ibcon#about to write, iclass 27, count 0 2006.201.13:16:41.90#ibcon#wrote, iclass 27, count 0 2006.201.13:16:41.90#ibcon#about to read 3, iclass 27, count 0 2006.201.13:16:41.93#ibcon#read 3, iclass 27, count 0 2006.201.13:16:41.93#ibcon#about to read 4, iclass 27, count 0 2006.201.13:16:41.93#ibcon#read 4, iclass 27, count 0 2006.201.13:16:41.93#ibcon#about to read 5, iclass 27, count 0 2006.201.13:16:41.93#ibcon#read 5, iclass 27, count 0 2006.201.13:16:41.93#ibcon#about to read 6, iclass 27, count 0 2006.201.13:16:41.93#ibcon#read 6, iclass 27, count 0 2006.201.13:16:41.93#ibcon#end of sib2, iclass 27, count 0 2006.201.13:16:41.93#ibcon#*after write, iclass 27, count 0 2006.201.13:16:41.93#ibcon#*before return 0, iclass 27, count 0 2006.201.13:16:41.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:41.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:16:41.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:16:41.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:16:41.93$vck44/vblo=8,744.99 2006.201.13:16:41.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.13:16:41.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.13:16:41.93#ibcon#ireg 17 cls_cnt 0 2006.201.13:16:41.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:41.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:41.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:41.93#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:16:41.93#ibcon#first serial, iclass 29, count 0 2006.201.13:16:41.93#ibcon#enter sib2, iclass 29, count 0 2006.201.13:16:41.93#ibcon#flushed, iclass 29, count 0 2006.201.13:16:41.93#ibcon#about to write, iclass 29, count 0 2006.201.13:16:41.93#ibcon#wrote, iclass 29, count 0 2006.201.13:16:41.93#ibcon#about to read 3, iclass 29, count 0 2006.201.13:16:41.95#ibcon#read 3, iclass 29, count 0 2006.201.13:16:41.95#ibcon#about to read 4, iclass 29, count 0 2006.201.13:16:41.95#ibcon#read 4, iclass 29, count 0 2006.201.13:16:41.95#ibcon#about to read 5, iclass 29, count 0 2006.201.13:16:41.95#ibcon#read 5, iclass 29, count 0 2006.201.13:16:41.95#ibcon#about to read 6, iclass 29, count 0 2006.201.13:16:41.95#ibcon#read 6, iclass 29, count 0 2006.201.13:16:41.95#ibcon#end of sib2, iclass 29, count 0 2006.201.13:16:41.95#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:16:41.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:16:41.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:16:41.95#ibcon#*before write, iclass 29, count 0 2006.201.13:16:41.95#ibcon#enter sib2, iclass 29, count 0 2006.201.13:16:41.95#ibcon#flushed, iclass 29, count 0 2006.201.13:16:41.95#ibcon#about to write, iclass 29, count 0 2006.201.13:16:41.95#ibcon#wrote, iclass 29, count 0 2006.201.13:16:41.95#ibcon#about to read 3, iclass 29, count 0 2006.201.13:16:42.00#ibcon#read 3, iclass 29, count 0 2006.201.13:16:42.00#ibcon#about to read 4, iclass 29, count 0 2006.201.13:16:42.00#ibcon#read 4, iclass 29, count 0 2006.201.13:16:42.00#ibcon#about to read 5, iclass 29, count 0 2006.201.13:16:42.00#ibcon#read 5, iclass 29, count 0 2006.201.13:16:42.00#ibcon#about to read 6, iclass 29, count 0 2006.201.13:16:42.00#ibcon#read 6, iclass 29, count 0 2006.201.13:16:42.00#ibcon#end of sib2, iclass 29, count 0 2006.201.13:16:42.00#ibcon#*after write, iclass 29, count 0 2006.201.13:16:42.00#ibcon#*before return 0, iclass 29, count 0 2006.201.13:16:42.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:42.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:16:42.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:16:42.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:16:42.00$vck44/vb=8,4 2006.201.13:16:42.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.13:16:42.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.13:16:42.00#ibcon#ireg 11 cls_cnt 2 2006.201.13:16:42.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:42.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:42.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:42.05#ibcon#enter wrdev, iclass 31, count 2 2006.201.13:16:42.05#ibcon#first serial, iclass 31, count 2 2006.201.13:16:42.05#ibcon#enter sib2, iclass 31, count 2 2006.201.13:16:42.05#ibcon#flushed, iclass 31, count 2 2006.201.13:16:42.05#ibcon#about to write, iclass 31, count 2 2006.201.13:16:42.05#ibcon#wrote, iclass 31, count 2 2006.201.13:16:42.05#ibcon#about to read 3, iclass 31, count 2 2006.201.13:16:42.07#ibcon#read 3, iclass 31, count 2 2006.201.13:16:42.07#ibcon#about to read 4, iclass 31, count 2 2006.201.13:16:42.07#ibcon#read 4, iclass 31, count 2 2006.201.13:16:42.07#ibcon#about to read 5, iclass 31, count 2 2006.201.13:16:42.07#ibcon#read 5, iclass 31, count 2 2006.201.13:16:42.07#ibcon#about to read 6, iclass 31, count 2 2006.201.13:16:42.07#ibcon#read 6, iclass 31, count 2 2006.201.13:16:42.07#ibcon#end of sib2, iclass 31, count 2 2006.201.13:16:42.07#ibcon#*mode == 0, iclass 31, count 2 2006.201.13:16:42.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.13:16:42.07#ibcon#[27=AT08-04\r\n] 2006.201.13:16:42.07#ibcon#*before write, iclass 31, count 2 2006.201.13:16:42.07#ibcon#enter sib2, iclass 31, count 2 2006.201.13:16:42.07#ibcon#flushed, iclass 31, count 2 2006.201.13:16:42.07#ibcon#about to write, iclass 31, count 2 2006.201.13:16:42.07#ibcon#wrote, iclass 31, count 2 2006.201.13:16:42.07#ibcon#about to read 3, iclass 31, count 2 2006.201.13:16:42.10#ibcon#read 3, iclass 31, count 2 2006.201.13:16:42.10#ibcon#about to read 4, iclass 31, count 2 2006.201.13:16:42.10#ibcon#read 4, iclass 31, count 2 2006.201.13:16:42.10#ibcon#about to read 5, iclass 31, count 2 2006.201.13:16:42.10#ibcon#read 5, iclass 31, count 2 2006.201.13:16:42.10#ibcon#about to read 6, iclass 31, count 2 2006.201.13:16:42.10#ibcon#read 6, iclass 31, count 2 2006.201.13:16:42.10#ibcon#end of sib2, iclass 31, count 2 2006.201.13:16:42.10#ibcon#*after write, iclass 31, count 2 2006.201.13:16:42.10#ibcon#*before return 0, iclass 31, count 2 2006.201.13:16:42.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:42.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:16:42.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.13:16:42.10#ibcon#ireg 7 cls_cnt 0 2006.201.13:16:42.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:42.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:42.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:42.22#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:16:42.22#ibcon#first serial, iclass 31, count 0 2006.201.13:16:42.22#ibcon#enter sib2, iclass 31, count 0 2006.201.13:16:42.22#ibcon#flushed, iclass 31, count 0 2006.201.13:16:42.22#ibcon#about to write, iclass 31, count 0 2006.201.13:16:42.22#ibcon#wrote, iclass 31, count 0 2006.201.13:16:42.22#ibcon#about to read 3, iclass 31, count 0 2006.201.13:16:42.24#ibcon#read 3, iclass 31, count 0 2006.201.13:16:42.24#ibcon#about to read 4, iclass 31, count 0 2006.201.13:16:42.24#ibcon#read 4, iclass 31, count 0 2006.201.13:16:42.24#ibcon#about to read 5, iclass 31, count 0 2006.201.13:16:42.24#ibcon#read 5, iclass 31, count 0 2006.201.13:16:42.24#ibcon#about to read 6, iclass 31, count 0 2006.201.13:16:42.24#ibcon#read 6, iclass 31, count 0 2006.201.13:16:42.24#ibcon#end of sib2, iclass 31, count 0 2006.201.13:16:42.24#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:16:42.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:16:42.24#ibcon#[27=USB\r\n] 2006.201.13:16:42.24#ibcon#*before write, iclass 31, count 0 2006.201.13:16:42.24#ibcon#enter sib2, iclass 31, count 0 2006.201.13:16:42.24#ibcon#flushed, iclass 31, count 0 2006.201.13:16:42.24#ibcon#about to write, iclass 31, count 0 2006.201.13:16:42.24#ibcon#wrote, iclass 31, count 0 2006.201.13:16:42.24#ibcon#about to read 3, iclass 31, count 0 2006.201.13:16:42.27#ibcon#read 3, iclass 31, count 0 2006.201.13:16:42.27#ibcon#about to read 4, iclass 31, count 0 2006.201.13:16:42.27#ibcon#read 4, iclass 31, count 0 2006.201.13:16:42.27#ibcon#about to read 5, iclass 31, count 0 2006.201.13:16:42.27#ibcon#read 5, iclass 31, count 0 2006.201.13:16:42.27#ibcon#about to read 6, iclass 31, count 0 2006.201.13:16:42.27#ibcon#read 6, iclass 31, count 0 2006.201.13:16:42.27#ibcon#end of sib2, iclass 31, count 0 2006.201.13:16:42.27#ibcon#*after write, iclass 31, count 0 2006.201.13:16:42.27#ibcon#*before return 0, iclass 31, count 0 2006.201.13:16:42.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:42.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:16:42.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:16:42.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:16:42.27$vck44/vabw=wide 2006.201.13:16:42.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.13:16:42.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.13:16:42.27#ibcon#ireg 8 cls_cnt 0 2006.201.13:16:42.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:42.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:42.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:42.27#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:16:42.27#ibcon#first serial, iclass 33, count 0 2006.201.13:16:42.27#ibcon#enter sib2, iclass 33, count 0 2006.201.13:16:42.27#ibcon#flushed, iclass 33, count 0 2006.201.13:16:42.27#ibcon#about to write, iclass 33, count 0 2006.201.13:16:42.27#ibcon#wrote, iclass 33, count 0 2006.201.13:16:42.27#ibcon#about to read 3, iclass 33, count 0 2006.201.13:16:42.29#ibcon#read 3, iclass 33, count 0 2006.201.13:16:42.29#ibcon#about to read 4, iclass 33, count 0 2006.201.13:16:42.29#ibcon#read 4, iclass 33, count 0 2006.201.13:16:42.29#ibcon#about to read 5, iclass 33, count 0 2006.201.13:16:42.29#ibcon#read 5, iclass 33, count 0 2006.201.13:16:42.29#ibcon#about to read 6, iclass 33, count 0 2006.201.13:16:42.29#ibcon#read 6, iclass 33, count 0 2006.201.13:16:42.29#ibcon#end of sib2, iclass 33, count 0 2006.201.13:16:42.29#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:16:42.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:16:42.29#ibcon#[25=BW32\r\n] 2006.201.13:16:42.29#ibcon#*before write, iclass 33, count 0 2006.201.13:16:42.29#ibcon#enter sib2, iclass 33, count 0 2006.201.13:16:42.29#ibcon#flushed, iclass 33, count 0 2006.201.13:16:42.29#ibcon#about to write, iclass 33, count 0 2006.201.13:16:42.29#ibcon#wrote, iclass 33, count 0 2006.201.13:16:42.29#ibcon#about to read 3, iclass 33, count 0 2006.201.13:16:42.32#ibcon#read 3, iclass 33, count 0 2006.201.13:16:42.32#ibcon#about to read 4, iclass 33, count 0 2006.201.13:16:42.32#ibcon#read 4, iclass 33, count 0 2006.201.13:16:42.32#ibcon#about to read 5, iclass 33, count 0 2006.201.13:16:42.32#ibcon#read 5, iclass 33, count 0 2006.201.13:16:42.32#ibcon#about to read 6, iclass 33, count 0 2006.201.13:16:42.32#ibcon#read 6, iclass 33, count 0 2006.201.13:16:42.32#ibcon#end of sib2, iclass 33, count 0 2006.201.13:16:42.32#ibcon#*after write, iclass 33, count 0 2006.201.13:16:42.32#ibcon#*before return 0, iclass 33, count 0 2006.201.13:16:42.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:42.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:16:42.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:16:42.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:16:42.32$vck44/vbbw=wide 2006.201.13:16:42.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.13:16:42.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.13:16:42.32#ibcon#ireg 8 cls_cnt 0 2006.201.13:16:42.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:16:42.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:16:42.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:16:42.39#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:16:42.39#ibcon#first serial, iclass 35, count 0 2006.201.13:16:42.39#ibcon#enter sib2, iclass 35, count 0 2006.201.13:16:42.39#ibcon#flushed, iclass 35, count 0 2006.201.13:16:42.39#ibcon#about to write, iclass 35, count 0 2006.201.13:16:42.39#ibcon#wrote, iclass 35, count 0 2006.201.13:16:42.39#ibcon#about to read 3, iclass 35, count 0 2006.201.13:16:42.41#ibcon#read 3, iclass 35, count 0 2006.201.13:16:42.41#ibcon#about to read 4, iclass 35, count 0 2006.201.13:16:42.41#ibcon#read 4, iclass 35, count 0 2006.201.13:16:42.41#ibcon#about to read 5, iclass 35, count 0 2006.201.13:16:42.41#ibcon#read 5, iclass 35, count 0 2006.201.13:16:42.41#ibcon#about to read 6, iclass 35, count 0 2006.201.13:16:42.41#ibcon#read 6, iclass 35, count 0 2006.201.13:16:42.41#ibcon#end of sib2, iclass 35, count 0 2006.201.13:16:42.41#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:16:42.41#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:16:42.41#ibcon#[27=BW32\r\n] 2006.201.13:16:42.41#ibcon#*before write, iclass 35, count 0 2006.201.13:16:42.41#ibcon#enter sib2, iclass 35, count 0 2006.201.13:16:42.41#ibcon#flushed, iclass 35, count 0 2006.201.13:16:42.41#ibcon#about to write, iclass 35, count 0 2006.201.13:16:42.41#ibcon#wrote, iclass 35, count 0 2006.201.13:16:42.41#ibcon#about to read 3, iclass 35, count 0 2006.201.13:16:42.44#ibcon#read 3, iclass 35, count 0 2006.201.13:16:42.44#ibcon#about to read 4, iclass 35, count 0 2006.201.13:16:42.44#ibcon#read 4, iclass 35, count 0 2006.201.13:16:42.44#ibcon#about to read 5, iclass 35, count 0 2006.201.13:16:42.44#ibcon#read 5, iclass 35, count 0 2006.201.13:16:42.44#ibcon#about to read 6, iclass 35, count 0 2006.201.13:16:42.44#ibcon#read 6, iclass 35, count 0 2006.201.13:16:42.44#ibcon#end of sib2, iclass 35, count 0 2006.201.13:16:42.44#ibcon#*after write, iclass 35, count 0 2006.201.13:16:42.44#ibcon#*before return 0, iclass 35, count 0 2006.201.13:16:42.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:16:42.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:16:42.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:16:42.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:16:42.44$setupk4/ifdk4 2006.201.13:16:42.44$ifdk4/lo= 2006.201.13:16:42.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:16:42.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:16:42.44$ifdk4/patch= 2006.201.13:16:42.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:16:42.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:16:42.44$setupk4/!*+20s 2006.201.13:16:48.05#abcon#<5=/05 1.3 2.3 20.961001003.9\r\n> 2006.201.13:16:48.07#abcon#{5=INTERFACE CLEAR} 2006.201.13:16:48.13#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:16:56.92$setupk4/"tpicd 2006.201.13:16:56.92$setupk4/echo=off 2006.201.13:16:56.92$setupk4/xlog=off 2006.201.13:16:56.92:!2006.201.13:22:53 2006.201.13:17:02.14#trakl#Source acquired 2006.201.13:17:02.14#flagr#flagr/antenna,acquired 2006.201.13:22:53.00:preob 2006.201.13:22:54.13/onsource/TRACKING 2006.201.13:22:54.13:!2006.201.13:23:03 2006.201.13:23:03.00:"tape 2006.201.13:23:03.00:"st=record 2006.201.13:23:03.00:data_valid=on 2006.201.13:23:03.00:midob 2006.201.13:23:03.13/onsource/TRACKING 2006.201.13:23:03.13/wx/20.95,1003.8,100 2006.201.13:23:03.31/cable/+6.4751E-03 2006.201.13:23:04.40/va/01,08,usb,yes,28,30 2006.201.13:23:04.40/va/02,07,usb,yes,31,31 2006.201.13:23:04.40/va/03,08,usb,yes,27,29 2006.201.13:23:04.40/va/04,07,usb,yes,32,33 2006.201.13:23:04.40/va/05,04,usb,yes,28,28 2006.201.13:23:04.40/va/06,05,usb,yes,28,28 2006.201.13:23:04.40/va/07,05,usb,yes,27,28 2006.201.13:23:04.40/va/08,04,usb,yes,27,32 2006.201.13:23:04.63/valo/01,524.99,yes,locked 2006.201.13:23:04.63/valo/02,534.99,yes,locked 2006.201.13:23:04.63/valo/03,564.99,yes,locked 2006.201.13:23:04.63/valo/04,624.99,yes,locked 2006.201.13:23:04.63/valo/05,734.99,yes,locked 2006.201.13:23:04.63/valo/06,814.99,yes,locked 2006.201.13:23:04.63/valo/07,864.99,yes,locked 2006.201.13:23:04.63/valo/08,884.99,yes,locked 2006.201.13:23:05.72/vb/01,04,usb,yes,28,26 2006.201.13:23:05.72/vb/02,05,usb,yes,27,27 2006.201.13:23:05.72/vb/03,04,usb,yes,28,31 2006.201.13:23:05.72/vb/04,05,usb,yes,28,27 2006.201.13:23:05.72/vb/05,04,usb,yes,25,27 2006.201.13:23:05.72/vb/06,04,usb,yes,29,25 2006.201.13:23:05.72/vb/07,04,usb,yes,29,29 2006.201.13:23:05.72/vb/08,04,usb,yes,27,30 2006.201.13:23:05.96/vblo/01,629.99,yes,locked 2006.201.13:23:05.96/vblo/02,634.99,yes,locked 2006.201.13:23:05.96/vblo/03,649.99,yes,locked 2006.201.13:23:05.96/vblo/04,679.99,yes,locked 2006.201.13:23:05.96/vblo/05,709.99,yes,locked 2006.201.13:23:05.96/vblo/06,719.99,yes,locked 2006.201.13:23:05.96/vblo/07,734.99,yes,locked 2006.201.13:23:05.96/vblo/08,744.99,yes,locked 2006.201.13:23:06.11/vabw/8 2006.201.13:23:06.26/vbbw/8 2006.201.13:23:06.35/xfe/off,on,14.7 2006.201.13:23:06.74/ifatt/23,28,28,28 2006.201.13:23:07.06/fmout-gps/S +4.54E-07 2006.201.13:23:07.13:!2006.201.13:26:43 2006.201.13:26:43.00:data_valid=off 2006.201.13:26:43.00:"et 2006.201.13:26:43.00:!+3s 2006.201.13:26:46.02:"tape 2006.201.13:26:46.02:postob 2006.201.13:26:46.20/cable/+6.4737E-03 2006.201.13:26:46.20/wx/20.94,1003.7,100 2006.201.13:26:46.28/fmout-gps/S +4.55E-07 2006.201.13:26:46.28:scan_name=201-1337,jd0607,70 2006.201.13:26:46.28:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.201.13:26:48.14#flagr#flagr/antenna,new-source 2006.201.13:26:48.14:checkk5 2006.201.13:26:48.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:26:48.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:26:49.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:26:49.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:26:50.05/chk_obsdata//k5ts1/T2011323??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.13:26:50.42/chk_obsdata//k5ts2/T2011323??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.13:26:50.78/chk_obsdata//k5ts3/T2011323??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.13:26:51.14/chk_obsdata//k5ts4/T2011323??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.13:26:51.84/k5log//k5ts1_log_newline 2006.201.13:26:52.52/k5log//k5ts2_log_newline 2006.201.13:26:53.21/k5log//k5ts3_log_newline 2006.201.13:26:53.89/k5log//k5ts4_log_newline 2006.201.13:26:53.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:26:53.92:setupk4=1 2006.201.13:26:53.92$setupk4/echo=on 2006.201.13:26:53.92$setupk4/pcalon 2006.201.13:26:53.92$pcalon/"no phase cal control is implemented here 2006.201.13:26:53.92$setupk4/"tpicd=stop 2006.201.13:26:53.92$setupk4/"rec=synch_on 2006.201.13:26:53.92$setupk4/"rec_mode=128 2006.201.13:26:53.92$setupk4/!* 2006.201.13:26:53.92$setupk4/recpk4 2006.201.13:26:53.92$recpk4/recpatch= 2006.201.13:26:53.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:26:53.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:26:53.92$setupk4/vck44 2006.201.13:26:53.92$vck44/valo=1,524.99 2006.201.13:26:53.92#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.13:26:53.92#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.13:26:53.92#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:53.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:53.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:53.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:53.92#ibcon#enter wrdev, iclass 28, count 0 2006.201.13:26:53.92#ibcon#first serial, iclass 28, count 0 2006.201.13:26:53.92#ibcon#enter sib2, iclass 28, count 0 2006.201.13:26:53.92#ibcon#flushed, iclass 28, count 0 2006.201.13:26:53.92#ibcon#about to write, iclass 28, count 0 2006.201.13:26:53.92#ibcon#wrote, iclass 28, count 0 2006.201.13:26:53.92#ibcon#about to read 3, iclass 28, count 0 2006.201.13:26:53.96#ibcon#read 3, iclass 28, count 0 2006.201.13:26:53.96#ibcon#about to read 4, iclass 28, count 0 2006.201.13:26:53.96#ibcon#read 4, iclass 28, count 0 2006.201.13:26:53.96#ibcon#about to read 5, iclass 28, count 0 2006.201.13:26:53.96#ibcon#read 5, iclass 28, count 0 2006.201.13:26:53.96#ibcon#about to read 6, iclass 28, count 0 2006.201.13:26:53.96#ibcon#read 6, iclass 28, count 0 2006.201.13:26:53.96#ibcon#end of sib2, iclass 28, count 0 2006.201.13:26:53.96#ibcon#*mode == 0, iclass 28, count 0 2006.201.13:26:53.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.13:26:53.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:26:53.96#ibcon#*before write, iclass 28, count 0 2006.201.13:26:53.96#ibcon#enter sib2, iclass 28, count 0 2006.201.13:26:53.96#ibcon#flushed, iclass 28, count 0 2006.201.13:26:53.96#ibcon#about to write, iclass 28, count 0 2006.201.13:26:53.96#ibcon#wrote, iclass 28, count 0 2006.201.13:26:53.96#ibcon#about to read 3, iclass 28, count 0 2006.201.13:26:54.01#ibcon#read 3, iclass 28, count 0 2006.201.13:26:54.01#ibcon#about to read 4, iclass 28, count 0 2006.201.13:26:54.01#ibcon#read 4, iclass 28, count 0 2006.201.13:26:54.01#ibcon#about to read 5, iclass 28, count 0 2006.201.13:26:54.01#ibcon#read 5, iclass 28, count 0 2006.201.13:26:54.01#ibcon#about to read 6, iclass 28, count 0 2006.201.13:26:54.01#ibcon#read 6, iclass 28, count 0 2006.201.13:26:54.01#ibcon#end of sib2, iclass 28, count 0 2006.201.13:26:54.01#ibcon#*after write, iclass 28, count 0 2006.201.13:26:54.01#ibcon#*before return 0, iclass 28, count 0 2006.201.13:26:54.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:54.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:54.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.13:26:54.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.13:26:54.01$vck44/va=1,8 2006.201.13:26:54.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.13:26:54.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.13:26:54.01#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:54.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:54.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:54.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:54.01#ibcon#enter wrdev, iclass 30, count 2 2006.201.13:26:54.01#ibcon#first serial, iclass 30, count 2 2006.201.13:26:54.01#ibcon#enter sib2, iclass 30, count 2 2006.201.13:26:54.01#ibcon#flushed, iclass 30, count 2 2006.201.13:26:54.01#ibcon#about to write, iclass 30, count 2 2006.201.13:26:54.01#ibcon#wrote, iclass 30, count 2 2006.201.13:26:54.01#ibcon#about to read 3, iclass 30, count 2 2006.201.13:26:54.03#ibcon#read 3, iclass 30, count 2 2006.201.13:26:54.03#ibcon#about to read 4, iclass 30, count 2 2006.201.13:26:54.03#ibcon#read 4, iclass 30, count 2 2006.201.13:26:54.03#ibcon#about to read 5, iclass 30, count 2 2006.201.13:26:54.03#ibcon#read 5, iclass 30, count 2 2006.201.13:26:54.03#ibcon#about to read 6, iclass 30, count 2 2006.201.13:26:54.03#ibcon#read 6, iclass 30, count 2 2006.201.13:26:54.03#ibcon#end of sib2, iclass 30, count 2 2006.201.13:26:54.03#ibcon#*mode == 0, iclass 30, count 2 2006.201.13:26:54.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.13:26:54.03#ibcon#[25=AT01-08\r\n] 2006.201.13:26:54.03#ibcon#*before write, iclass 30, count 2 2006.201.13:26:54.03#ibcon#enter sib2, iclass 30, count 2 2006.201.13:26:54.03#ibcon#flushed, iclass 30, count 2 2006.201.13:26:54.03#ibcon#about to write, iclass 30, count 2 2006.201.13:26:54.03#ibcon#wrote, iclass 30, count 2 2006.201.13:26:54.03#ibcon#about to read 3, iclass 30, count 2 2006.201.13:26:54.06#ibcon#read 3, iclass 30, count 2 2006.201.13:26:54.06#ibcon#about to read 4, iclass 30, count 2 2006.201.13:26:54.06#ibcon#read 4, iclass 30, count 2 2006.201.13:26:54.06#ibcon#about to read 5, iclass 30, count 2 2006.201.13:26:54.06#ibcon#read 5, iclass 30, count 2 2006.201.13:26:54.06#ibcon#about to read 6, iclass 30, count 2 2006.201.13:26:54.06#ibcon#read 6, iclass 30, count 2 2006.201.13:26:54.06#ibcon#end of sib2, iclass 30, count 2 2006.201.13:26:54.06#ibcon#*after write, iclass 30, count 2 2006.201.13:26:54.06#ibcon#*before return 0, iclass 30, count 2 2006.201.13:26:54.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:54.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:54.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.13:26:54.06#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:54.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:54.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:54.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:54.18#ibcon#enter wrdev, iclass 30, count 0 2006.201.13:26:54.18#ibcon#first serial, iclass 30, count 0 2006.201.13:26:54.18#ibcon#enter sib2, iclass 30, count 0 2006.201.13:26:54.18#ibcon#flushed, iclass 30, count 0 2006.201.13:26:54.18#ibcon#about to write, iclass 30, count 0 2006.201.13:26:54.18#ibcon#wrote, iclass 30, count 0 2006.201.13:26:54.18#ibcon#about to read 3, iclass 30, count 0 2006.201.13:26:54.20#ibcon#read 3, iclass 30, count 0 2006.201.13:26:54.20#ibcon#about to read 4, iclass 30, count 0 2006.201.13:26:54.20#ibcon#read 4, iclass 30, count 0 2006.201.13:26:54.20#ibcon#about to read 5, iclass 30, count 0 2006.201.13:26:54.20#ibcon#read 5, iclass 30, count 0 2006.201.13:26:54.20#ibcon#about to read 6, iclass 30, count 0 2006.201.13:26:54.20#ibcon#read 6, iclass 30, count 0 2006.201.13:26:54.20#ibcon#end of sib2, iclass 30, count 0 2006.201.13:26:54.20#ibcon#*mode == 0, iclass 30, count 0 2006.201.13:26:54.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.13:26:54.20#ibcon#[25=USB\r\n] 2006.201.13:26:54.20#ibcon#*before write, iclass 30, count 0 2006.201.13:26:54.20#ibcon#enter sib2, iclass 30, count 0 2006.201.13:26:54.20#ibcon#flushed, iclass 30, count 0 2006.201.13:26:54.20#ibcon#about to write, iclass 30, count 0 2006.201.13:26:54.20#ibcon#wrote, iclass 30, count 0 2006.201.13:26:54.20#ibcon#about to read 3, iclass 30, count 0 2006.201.13:26:54.23#ibcon#read 3, iclass 30, count 0 2006.201.13:26:54.23#ibcon#about to read 4, iclass 30, count 0 2006.201.13:26:54.23#ibcon#read 4, iclass 30, count 0 2006.201.13:26:54.23#ibcon#about to read 5, iclass 30, count 0 2006.201.13:26:54.23#ibcon#read 5, iclass 30, count 0 2006.201.13:26:54.23#ibcon#about to read 6, iclass 30, count 0 2006.201.13:26:54.23#ibcon#read 6, iclass 30, count 0 2006.201.13:26:54.23#ibcon#end of sib2, iclass 30, count 0 2006.201.13:26:54.23#ibcon#*after write, iclass 30, count 0 2006.201.13:26:54.23#ibcon#*before return 0, iclass 30, count 0 2006.201.13:26:54.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:54.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:54.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.13:26:54.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.13:26:54.23$vck44/valo=2,534.99 2006.201.13:26:54.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.13:26:54.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.13:26:54.23#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:54.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:54.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:54.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:54.23#ibcon#enter wrdev, iclass 32, count 0 2006.201.13:26:54.23#ibcon#first serial, iclass 32, count 0 2006.201.13:26:54.23#ibcon#enter sib2, iclass 32, count 0 2006.201.13:26:54.23#ibcon#flushed, iclass 32, count 0 2006.201.13:26:54.23#ibcon#about to write, iclass 32, count 0 2006.201.13:26:54.23#ibcon#wrote, iclass 32, count 0 2006.201.13:26:54.23#ibcon#about to read 3, iclass 32, count 0 2006.201.13:26:54.25#ibcon#read 3, iclass 32, count 0 2006.201.13:26:54.25#ibcon#about to read 4, iclass 32, count 0 2006.201.13:26:54.25#ibcon#read 4, iclass 32, count 0 2006.201.13:26:54.25#ibcon#about to read 5, iclass 32, count 0 2006.201.13:26:54.25#ibcon#read 5, iclass 32, count 0 2006.201.13:26:54.25#ibcon#about to read 6, iclass 32, count 0 2006.201.13:26:54.25#ibcon#read 6, iclass 32, count 0 2006.201.13:26:54.25#ibcon#end of sib2, iclass 32, count 0 2006.201.13:26:54.25#ibcon#*mode == 0, iclass 32, count 0 2006.201.13:26:54.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.13:26:54.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:26:54.25#ibcon#*before write, iclass 32, count 0 2006.201.13:26:54.25#ibcon#enter sib2, iclass 32, count 0 2006.201.13:26:54.25#ibcon#flushed, iclass 32, count 0 2006.201.13:26:54.25#ibcon#about to write, iclass 32, count 0 2006.201.13:26:54.25#ibcon#wrote, iclass 32, count 0 2006.201.13:26:54.25#ibcon#about to read 3, iclass 32, count 0 2006.201.13:26:54.29#ibcon#read 3, iclass 32, count 0 2006.201.13:26:54.29#ibcon#about to read 4, iclass 32, count 0 2006.201.13:26:54.29#ibcon#read 4, iclass 32, count 0 2006.201.13:26:54.29#ibcon#about to read 5, iclass 32, count 0 2006.201.13:26:54.29#ibcon#read 5, iclass 32, count 0 2006.201.13:26:54.29#ibcon#about to read 6, iclass 32, count 0 2006.201.13:26:54.29#ibcon#read 6, iclass 32, count 0 2006.201.13:26:54.29#ibcon#end of sib2, iclass 32, count 0 2006.201.13:26:54.29#ibcon#*after write, iclass 32, count 0 2006.201.13:26:54.29#ibcon#*before return 0, iclass 32, count 0 2006.201.13:26:54.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:54.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:54.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.13:26:54.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.13:26:54.29$vck44/va=2,7 2006.201.13:26:54.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.13:26:54.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.13:26:54.29#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:54.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:54.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:54.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:54.35#ibcon#enter wrdev, iclass 34, count 2 2006.201.13:26:54.35#ibcon#first serial, iclass 34, count 2 2006.201.13:26:54.35#ibcon#enter sib2, iclass 34, count 2 2006.201.13:26:54.35#ibcon#flushed, iclass 34, count 2 2006.201.13:26:54.35#ibcon#about to write, iclass 34, count 2 2006.201.13:26:54.35#ibcon#wrote, iclass 34, count 2 2006.201.13:26:54.35#ibcon#about to read 3, iclass 34, count 2 2006.201.13:26:54.37#ibcon#read 3, iclass 34, count 2 2006.201.13:26:54.37#ibcon#about to read 4, iclass 34, count 2 2006.201.13:26:54.37#ibcon#read 4, iclass 34, count 2 2006.201.13:26:54.37#ibcon#about to read 5, iclass 34, count 2 2006.201.13:26:54.37#ibcon#read 5, iclass 34, count 2 2006.201.13:26:54.37#ibcon#about to read 6, iclass 34, count 2 2006.201.13:26:54.37#ibcon#read 6, iclass 34, count 2 2006.201.13:26:54.37#ibcon#end of sib2, iclass 34, count 2 2006.201.13:26:54.37#ibcon#*mode == 0, iclass 34, count 2 2006.201.13:26:54.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.13:26:54.37#ibcon#[25=AT02-07\r\n] 2006.201.13:26:54.37#ibcon#*before write, iclass 34, count 2 2006.201.13:26:54.37#ibcon#enter sib2, iclass 34, count 2 2006.201.13:26:54.37#ibcon#flushed, iclass 34, count 2 2006.201.13:26:54.37#ibcon#about to write, iclass 34, count 2 2006.201.13:26:54.37#ibcon#wrote, iclass 34, count 2 2006.201.13:26:54.37#ibcon#about to read 3, iclass 34, count 2 2006.201.13:26:54.40#ibcon#read 3, iclass 34, count 2 2006.201.13:26:54.40#ibcon#about to read 4, iclass 34, count 2 2006.201.13:26:54.40#ibcon#read 4, iclass 34, count 2 2006.201.13:26:54.40#ibcon#about to read 5, iclass 34, count 2 2006.201.13:26:54.40#ibcon#read 5, iclass 34, count 2 2006.201.13:26:54.40#ibcon#about to read 6, iclass 34, count 2 2006.201.13:26:54.40#ibcon#read 6, iclass 34, count 2 2006.201.13:26:54.40#ibcon#end of sib2, iclass 34, count 2 2006.201.13:26:54.40#ibcon#*after write, iclass 34, count 2 2006.201.13:26:54.40#ibcon#*before return 0, iclass 34, count 2 2006.201.13:26:54.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:54.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:54.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.13:26:54.40#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:54.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:54.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:54.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:54.52#ibcon#enter wrdev, iclass 34, count 0 2006.201.13:26:54.52#ibcon#first serial, iclass 34, count 0 2006.201.13:26:54.52#ibcon#enter sib2, iclass 34, count 0 2006.201.13:26:54.52#ibcon#flushed, iclass 34, count 0 2006.201.13:26:54.52#ibcon#about to write, iclass 34, count 0 2006.201.13:26:54.52#ibcon#wrote, iclass 34, count 0 2006.201.13:26:54.52#ibcon#about to read 3, iclass 34, count 0 2006.201.13:26:54.54#ibcon#read 3, iclass 34, count 0 2006.201.13:26:54.54#ibcon#about to read 4, iclass 34, count 0 2006.201.13:26:54.54#ibcon#read 4, iclass 34, count 0 2006.201.13:26:54.54#ibcon#about to read 5, iclass 34, count 0 2006.201.13:26:54.54#ibcon#read 5, iclass 34, count 0 2006.201.13:26:54.54#ibcon#about to read 6, iclass 34, count 0 2006.201.13:26:54.54#ibcon#read 6, iclass 34, count 0 2006.201.13:26:54.54#ibcon#end of sib2, iclass 34, count 0 2006.201.13:26:54.54#ibcon#*mode == 0, iclass 34, count 0 2006.201.13:26:54.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.13:26:54.54#ibcon#[25=USB\r\n] 2006.201.13:26:54.54#ibcon#*before write, iclass 34, count 0 2006.201.13:26:54.54#ibcon#enter sib2, iclass 34, count 0 2006.201.13:26:54.54#ibcon#flushed, iclass 34, count 0 2006.201.13:26:54.54#ibcon#about to write, iclass 34, count 0 2006.201.13:26:54.54#ibcon#wrote, iclass 34, count 0 2006.201.13:26:54.54#ibcon#about to read 3, iclass 34, count 0 2006.201.13:26:54.57#ibcon#read 3, iclass 34, count 0 2006.201.13:26:54.57#ibcon#about to read 4, iclass 34, count 0 2006.201.13:26:54.57#ibcon#read 4, iclass 34, count 0 2006.201.13:26:54.57#ibcon#about to read 5, iclass 34, count 0 2006.201.13:26:54.57#ibcon#read 5, iclass 34, count 0 2006.201.13:26:54.57#ibcon#about to read 6, iclass 34, count 0 2006.201.13:26:54.57#ibcon#read 6, iclass 34, count 0 2006.201.13:26:54.57#ibcon#end of sib2, iclass 34, count 0 2006.201.13:26:54.57#ibcon#*after write, iclass 34, count 0 2006.201.13:26:54.57#ibcon#*before return 0, iclass 34, count 0 2006.201.13:26:54.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:54.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:54.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.13:26:54.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.13:26:54.57$vck44/valo=3,564.99 2006.201.13:26:54.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.13:26:54.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.13:26:54.57#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:54.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:54.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:54.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:54.57#ibcon#enter wrdev, iclass 36, count 0 2006.201.13:26:54.57#ibcon#first serial, iclass 36, count 0 2006.201.13:26:54.57#ibcon#enter sib2, iclass 36, count 0 2006.201.13:26:54.57#ibcon#flushed, iclass 36, count 0 2006.201.13:26:54.57#ibcon#about to write, iclass 36, count 0 2006.201.13:26:54.57#ibcon#wrote, iclass 36, count 0 2006.201.13:26:54.57#ibcon#about to read 3, iclass 36, count 0 2006.201.13:26:54.59#ibcon#read 3, iclass 36, count 0 2006.201.13:26:54.59#ibcon#about to read 4, iclass 36, count 0 2006.201.13:26:54.59#ibcon#read 4, iclass 36, count 0 2006.201.13:26:54.59#ibcon#about to read 5, iclass 36, count 0 2006.201.13:26:54.59#ibcon#read 5, iclass 36, count 0 2006.201.13:26:54.59#ibcon#about to read 6, iclass 36, count 0 2006.201.13:26:54.59#ibcon#read 6, iclass 36, count 0 2006.201.13:26:54.59#ibcon#end of sib2, iclass 36, count 0 2006.201.13:26:54.59#ibcon#*mode == 0, iclass 36, count 0 2006.201.13:26:54.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.13:26:54.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:26:54.59#ibcon#*before write, iclass 36, count 0 2006.201.13:26:54.59#ibcon#enter sib2, iclass 36, count 0 2006.201.13:26:54.59#ibcon#flushed, iclass 36, count 0 2006.201.13:26:54.59#ibcon#about to write, iclass 36, count 0 2006.201.13:26:54.59#ibcon#wrote, iclass 36, count 0 2006.201.13:26:54.59#ibcon#about to read 3, iclass 36, count 0 2006.201.13:26:54.64#ibcon#read 3, iclass 36, count 0 2006.201.13:26:54.64#ibcon#about to read 4, iclass 36, count 0 2006.201.13:26:54.64#ibcon#read 4, iclass 36, count 0 2006.201.13:26:54.64#ibcon#about to read 5, iclass 36, count 0 2006.201.13:26:54.64#ibcon#read 5, iclass 36, count 0 2006.201.13:26:54.64#ibcon#about to read 6, iclass 36, count 0 2006.201.13:26:54.64#ibcon#read 6, iclass 36, count 0 2006.201.13:26:54.64#ibcon#end of sib2, iclass 36, count 0 2006.201.13:26:54.64#ibcon#*after write, iclass 36, count 0 2006.201.13:26:54.64#ibcon#*before return 0, iclass 36, count 0 2006.201.13:26:54.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:54.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:54.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.13:26:54.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.13:26:54.64$vck44/va=3,8 2006.201.13:26:54.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.13:26:54.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.13:26:54.64#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:54.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:54.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:54.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:54.69#ibcon#enter wrdev, iclass 38, count 2 2006.201.13:26:54.69#ibcon#first serial, iclass 38, count 2 2006.201.13:26:54.69#ibcon#enter sib2, iclass 38, count 2 2006.201.13:26:54.69#ibcon#flushed, iclass 38, count 2 2006.201.13:26:54.69#ibcon#about to write, iclass 38, count 2 2006.201.13:26:54.69#ibcon#wrote, iclass 38, count 2 2006.201.13:26:54.69#ibcon#about to read 3, iclass 38, count 2 2006.201.13:26:54.71#ibcon#read 3, iclass 38, count 2 2006.201.13:26:54.71#ibcon#about to read 4, iclass 38, count 2 2006.201.13:26:54.71#ibcon#read 4, iclass 38, count 2 2006.201.13:26:54.71#ibcon#about to read 5, iclass 38, count 2 2006.201.13:26:54.71#ibcon#read 5, iclass 38, count 2 2006.201.13:26:54.71#ibcon#about to read 6, iclass 38, count 2 2006.201.13:26:54.71#ibcon#read 6, iclass 38, count 2 2006.201.13:26:54.71#ibcon#end of sib2, iclass 38, count 2 2006.201.13:26:54.71#ibcon#*mode == 0, iclass 38, count 2 2006.201.13:26:54.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.13:26:54.71#ibcon#[25=AT03-08\r\n] 2006.201.13:26:54.71#ibcon#*before write, iclass 38, count 2 2006.201.13:26:54.71#ibcon#enter sib2, iclass 38, count 2 2006.201.13:26:54.71#ibcon#flushed, iclass 38, count 2 2006.201.13:26:54.71#ibcon#about to write, iclass 38, count 2 2006.201.13:26:54.71#ibcon#wrote, iclass 38, count 2 2006.201.13:26:54.71#ibcon#about to read 3, iclass 38, count 2 2006.201.13:26:54.74#ibcon#read 3, iclass 38, count 2 2006.201.13:26:54.74#ibcon#about to read 4, iclass 38, count 2 2006.201.13:26:54.74#ibcon#read 4, iclass 38, count 2 2006.201.13:26:54.74#ibcon#about to read 5, iclass 38, count 2 2006.201.13:26:54.74#ibcon#read 5, iclass 38, count 2 2006.201.13:26:54.74#ibcon#about to read 6, iclass 38, count 2 2006.201.13:26:54.74#ibcon#read 6, iclass 38, count 2 2006.201.13:26:54.74#ibcon#end of sib2, iclass 38, count 2 2006.201.13:26:54.74#ibcon#*after write, iclass 38, count 2 2006.201.13:26:54.74#ibcon#*before return 0, iclass 38, count 2 2006.201.13:26:54.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:54.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:54.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.13:26:54.74#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:54.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:54.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:54.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:54.86#ibcon#enter wrdev, iclass 38, count 0 2006.201.13:26:54.86#ibcon#first serial, iclass 38, count 0 2006.201.13:26:54.86#ibcon#enter sib2, iclass 38, count 0 2006.201.13:26:54.86#ibcon#flushed, iclass 38, count 0 2006.201.13:26:54.86#ibcon#about to write, iclass 38, count 0 2006.201.13:26:54.86#ibcon#wrote, iclass 38, count 0 2006.201.13:26:54.86#ibcon#about to read 3, iclass 38, count 0 2006.201.13:26:54.88#ibcon#read 3, iclass 38, count 0 2006.201.13:26:54.88#ibcon#about to read 4, iclass 38, count 0 2006.201.13:26:54.88#ibcon#read 4, iclass 38, count 0 2006.201.13:26:54.88#ibcon#about to read 5, iclass 38, count 0 2006.201.13:26:54.88#ibcon#read 5, iclass 38, count 0 2006.201.13:26:54.88#ibcon#about to read 6, iclass 38, count 0 2006.201.13:26:54.88#ibcon#read 6, iclass 38, count 0 2006.201.13:26:54.88#ibcon#end of sib2, iclass 38, count 0 2006.201.13:26:54.88#ibcon#*mode == 0, iclass 38, count 0 2006.201.13:26:54.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.13:26:54.88#ibcon#[25=USB\r\n] 2006.201.13:26:54.88#ibcon#*before write, iclass 38, count 0 2006.201.13:26:54.88#ibcon#enter sib2, iclass 38, count 0 2006.201.13:26:54.88#ibcon#flushed, iclass 38, count 0 2006.201.13:26:54.88#ibcon#about to write, iclass 38, count 0 2006.201.13:26:54.88#ibcon#wrote, iclass 38, count 0 2006.201.13:26:54.88#ibcon#about to read 3, iclass 38, count 0 2006.201.13:26:54.91#ibcon#read 3, iclass 38, count 0 2006.201.13:26:54.91#ibcon#about to read 4, iclass 38, count 0 2006.201.13:26:54.91#ibcon#read 4, iclass 38, count 0 2006.201.13:26:54.91#ibcon#about to read 5, iclass 38, count 0 2006.201.13:26:54.91#ibcon#read 5, iclass 38, count 0 2006.201.13:26:54.91#ibcon#about to read 6, iclass 38, count 0 2006.201.13:26:54.91#ibcon#read 6, iclass 38, count 0 2006.201.13:26:54.91#ibcon#end of sib2, iclass 38, count 0 2006.201.13:26:54.91#ibcon#*after write, iclass 38, count 0 2006.201.13:26:54.91#ibcon#*before return 0, iclass 38, count 0 2006.201.13:26:54.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:54.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:54.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.13:26:54.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.13:26:54.91$vck44/valo=4,624.99 2006.201.13:26:54.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.13:26:54.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.13:26:54.91#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:54.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:54.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:54.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:54.91#ibcon#enter wrdev, iclass 40, count 0 2006.201.13:26:54.91#ibcon#first serial, iclass 40, count 0 2006.201.13:26:54.91#ibcon#enter sib2, iclass 40, count 0 2006.201.13:26:54.91#ibcon#flushed, iclass 40, count 0 2006.201.13:26:54.91#ibcon#about to write, iclass 40, count 0 2006.201.13:26:54.91#ibcon#wrote, iclass 40, count 0 2006.201.13:26:54.91#ibcon#about to read 3, iclass 40, count 0 2006.201.13:26:54.93#ibcon#read 3, iclass 40, count 0 2006.201.13:26:54.93#ibcon#about to read 4, iclass 40, count 0 2006.201.13:26:54.93#ibcon#read 4, iclass 40, count 0 2006.201.13:26:54.93#ibcon#about to read 5, iclass 40, count 0 2006.201.13:26:54.93#ibcon#read 5, iclass 40, count 0 2006.201.13:26:54.93#ibcon#about to read 6, iclass 40, count 0 2006.201.13:26:54.93#ibcon#read 6, iclass 40, count 0 2006.201.13:26:54.93#ibcon#end of sib2, iclass 40, count 0 2006.201.13:26:54.93#ibcon#*mode == 0, iclass 40, count 0 2006.201.13:26:54.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.13:26:54.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:26:54.93#ibcon#*before write, iclass 40, count 0 2006.201.13:26:54.93#ibcon#enter sib2, iclass 40, count 0 2006.201.13:26:54.93#ibcon#flushed, iclass 40, count 0 2006.201.13:26:54.93#ibcon#about to write, iclass 40, count 0 2006.201.13:26:54.93#ibcon#wrote, iclass 40, count 0 2006.201.13:26:54.93#ibcon#about to read 3, iclass 40, count 0 2006.201.13:26:54.97#ibcon#read 3, iclass 40, count 0 2006.201.13:26:54.97#ibcon#about to read 4, iclass 40, count 0 2006.201.13:26:54.97#ibcon#read 4, iclass 40, count 0 2006.201.13:26:54.97#ibcon#about to read 5, iclass 40, count 0 2006.201.13:26:54.97#ibcon#read 5, iclass 40, count 0 2006.201.13:26:54.97#ibcon#about to read 6, iclass 40, count 0 2006.201.13:26:54.97#ibcon#read 6, iclass 40, count 0 2006.201.13:26:54.97#ibcon#end of sib2, iclass 40, count 0 2006.201.13:26:54.97#ibcon#*after write, iclass 40, count 0 2006.201.13:26:54.97#ibcon#*before return 0, iclass 40, count 0 2006.201.13:26:54.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:54.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:54.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.13:26:54.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.13:26:54.97$vck44/va=4,7 2006.201.13:26:54.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.13:26:54.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.13:26:54.97#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:54.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:55.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:55.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:55.03#ibcon#enter wrdev, iclass 4, count 2 2006.201.13:26:55.03#ibcon#first serial, iclass 4, count 2 2006.201.13:26:55.03#ibcon#enter sib2, iclass 4, count 2 2006.201.13:26:55.03#ibcon#flushed, iclass 4, count 2 2006.201.13:26:55.03#ibcon#about to write, iclass 4, count 2 2006.201.13:26:55.03#ibcon#wrote, iclass 4, count 2 2006.201.13:26:55.03#ibcon#about to read 3, iclass 4, count 2 2006.201.13:26:55.05#ibcon#read 3, iclass 4, count 2 2006.201.13:26:55.05#ibcon#about to read 4, iclass 4, count 2 2006.201.13:26:55.05#ibcon#read 4, iclass 4, count 2 2006.201.13:26:55.05#ibcon#about to read 5, iclass 4, count 2 2006.201.13:26:55.05#ibcon#read 5, iclass 4, count 2 2006.201.13:26:55.05#ibcon#about to read 6, iclass 4, count 2 2006.201.13:26:55.05#ibcon#read 6, iclass 4, count 2 2006.201.13:26:55.05#ibcon#end of sib2, iclass 4, count 2 2006.201.13:26:55.05#ibcon#*mode == 0, iclass 4, count 2 2006.201.13:26:55.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.13:26:55.05#ibcon#[25=AT04-07\r\n] 2006.201.13:26:55.05#ibcon#*before write, iclass 4, count 2 2006.201.13:26:55.05#ibcon#enter sib2, iclass 4, count 2 2006.201.13:26:55.05#ibcon#flushed, iclass 4, count 2 2006.201.13:26:55.05#ibcon#about to write, iclass 4, count 2 2006.201.13:26:55.05#ibcon#wrote, iclass 4, count 2 2006.201.13:26:55.05#ibcon#about to read 3, iclass 4, count 2 2006.201.13:26:55.08#ibcon#read 3, iclass 4, count 2 2006.201.13:26:55.08#ibcon#about to read 4, iclass 4, count 2 2006.201.13:26:55.08#ibcon#read 4, iclass 4, count 2 2006.201.13:26:55.08#ibcon#about to read 5, iclass 4, count 2 2006.201.13:26:55.08#ibcon#read 5, iclass 4, count 2 2006.201.13:26:55.08#ibcon#about to read 6, iclass 4, count 2 2006.201.13:26:55.08#ibcon#read 6, iclass 4, count 2 2006.201.13:26:55.08#ibcon#end of sib2, iclass 4, count 2 2006.201.13:26:55.08#ibcon#*after write, iclass 4, count 2 2006.201.13:26:55.08#ibcon#*before return 0, iclass 4, count 2 2006.201.13:26:55.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:55.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:55.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.13:26:55.08#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:55.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:55.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:55.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:55.20#ibcon#enter wrdev, iclass 4, count 0 2006.201.13:26:55.20#ibcon#first serial, iclass 4, count 0 2006.201.13:26:55.20#ibcon#enter sib2, iclass 4, count 0 2006.201.13:26:55.20#ibcon#flushed, iclass 4, count 0 2006.201.13:26:55.20#ibcon#about to write, iclass 4, count 0 2006.201.13:26:55.20#ibcon#wrote, iclass 4, count 0 2006.201.13:26:55.20#ibcon#about to read 3, iclass 4, count 0 2006.201.13:26:55.22#ibcon#read 3, iclass 4, count 0 2006.201.13:26:55.22#ibcon#about to read 4, iclass 4, count 0 2006.201.13:26:55.22#ibcon#read 4, iclass 4, count 0 2006.201.13:26:55.22#ibcon#about to read 5, iclass 4, count 0 2006.201.13:26:55.22#ibcon#read 5, iclass 4, count 0 2006.201.13:26:55.22#ibcon#about to read 6, iclass 4, count 0 2006.201.13:26:55.22#ibcon#read 6, iclass 4, count 0 2006.201.13:26:55.22#ibcon#end of sib2, iclass 4, count 0 2006.201.13:26:55.22#ibcon#*mode == 0, iclass 4, count 0 2006.201.13:26:55.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.13:26:55.22#ibcon#[25=USB\r\n] 2006.201.13:26:55.22#ibcon#*before write, iclass 4, count 0 2006.201.13:26:55.22#ibcon#enter sib2, iclass 4, count 0 2006.201.13:26:55.22#ibcon#flushed, iclass 4, count 0 2006.201.13:26:55.22#ibcon#about to write, iclass 4, count 0 2006.201.13:26:55.22#ibcon#wrote, iclass 4, count 0 2006.201.13:26:55.22#ibcon#about to read 3, iclass 4, count 0 2006.201.13:26:55.25#ibcon#read 3, iclass 4, count 0 2006.201.13:26:55.25#ibcon#about to read 4, iclass 4, count 0 2006.201.13:26:55.25#ibcon#read 4, iclass 4, count 0 2006.201.13:26:55.25#ibcon#about to read 5, iclass 4, count 0 2006.201.13:26:55.25#ibcon#read 5, iclass 4, count 0 2006.201.13:26:55.25#ibcon#about to read 6, iclass 4, count 0 2006.201.13:26:55.25#ibcon#read 6, iclass 4, count 0 2006.201.13:26:55.25#ibcon#end of sib2, iclass 4, count 0 2006.201.13:26:55.25#ibcon#*after write, iclass 4, count 0 2006.201.13:26:55.25#ibcon#*before return 0, iclass 4, count 0 2006.201.13:26:55.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:55.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:55.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.13:26:55.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.13:26:55.25$vck44/valo=5,734.99 2006.201.13:26:55.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.13:26:55.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.13:26:55.25#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:55.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:55.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:55.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:55.25#ibcon#enter wrdev, iclass 6, count 0 2006.201.13:26:55.25#ibcon#first serial, iclass 6, count 0 2006.201.13:26:55.25#ibcon#enter sib2, iclass 6, count 0 2006.201.13:26:55.25#ibcon#flushed, iclass 6, count 0 2006.201.13:26:55.25#ibcon#about to write, iclass 6, count 0 2006.201.13:26:55.25#ibcon#wrote, iclass 6, count 0 2006.201.13:26:55.25#ibcon#about to read 3, iclass 6, count 0 2006.201.13:26:55.27#ibcon#read 3, iclass 6, count 0 2006.201.13:26:55.27#ibcon#about to read 4, iclass 6, count 0 2006.201.13:26:55.27#ibcon#read 4, iclass 6, count 0 2006.201.13:26:55.27#ibcon#about to read 5, iclass 6, count 0 2006.201.13:26:55.27#ibcon#read 5, iclass 6, count 0 2006.201.13:26:55.27#ibcon#about to read 6, iclass 6, count 0 2006.201.13:26:55.27#ibcon#read 6, iclass 6, count 0 2006.201.13:26:55.27#ibcon#end of sib2, iclass 6, count 0 2006.201.13:26:55.27#ibcon#*mode == 0, iclass 6, count 0 2006.201.13:26:55.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.13:26:55.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:26:55.27#ibcon#*before write, iclass 6, count 0 2006.201.13:26:55.27#ibcon#enter sib2, iclass 6, count 0 2006.201.13:26:55.27#ibcon#flushed, iclass 6, count 0 2006.201.13:26:55.27#ibcon#about to write, iclass 6, count 0 2006.201.13:26:55.27#ibcon#wrote, iclass 6, count 0 2006.201.13:26:55.27#ibcon#about to read 3, iclass 6, count 0 2006.201.13:26:55.31#ibcon#read 3, iclass 6, count 0 2006.201.13:26:55.31#ibcon#about to read 4, iclass 6, count 0 2006.201.13:26:55.31#ibcon#read 4, iclass 6, count 0 2006.201.13:26:55.31#ibcon#about to read 5, iclass 6, count 0 2006.201.13:26:55.31#ibcon#read 5, iclass 6, count 0 2006.201.13:26:55.31#ibcon#about to read 6, iclass 6, count 0 2006.201.13:26:55.31#ibcon#read 6, iclass 6, count 0 2006.201.13:26:55.31#ibcon#end of sib2, iclass 6, count 0 2006.201.13:26:55.31#ibcon#*after write, iclass 6, count 0 2006.201.13:26:55.31#ibcon#*before return 0, iclass 6, count 0 2006.201.13:26:55.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:55.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:55.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.13:26:55.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.13:26:55.31$vck44/va=5,4 2006.201.13:26:55.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.13:26:55.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.13:26:55.31#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:55.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:55.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:55.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:55.37#ibcon#enter wrdev, iclass 10, count 2 2006.201.13:26:55.37#ibcon#first serial, iclass 10, count 2 2006.201.13:26:55.37#ibcon#enter sib2, iclass 10, count 2 2006.201.13:26:55.37#ibcon#flushed, iclass 10, count 2 2006.201.13:26:55.37#ibcon#about to write, iclass 10, count 2 2006.201.13:26:55.37#ibcon#wrote, iclass 10, count 2 2006.201.13:26:55.37#ibcon#about to read 3, iclass 10, count 2 2006.201.13:26:55.39#ibcon#read 3, iclass 10, count 2 2006.201.13:26:55.39#ibcon#about to read 4, iclass 10, count 2 2006.201.13:26:55.39#ibcon#read 4, iclass 10, count 2 2006.201.13:26:55.39#ibcon#about to read 5, iclass 10, count 2 2006.201.13:26:55.39#ibcon#read 5, iclass 10, count 2 2006.201.13:26:55.39#ibcon#about to read 6, iclass 10, count 2 2006.201.13:26:55.39#ibcon#read 6, iclass 10, count 2 2006.201.13:26:55.39#ibcon#end of sib2, iclass 10, count 2 2006.201.13:26:55.39#ibcon#*mode == 0, iclass 10, count 2 2006.201.13:26:55.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.13:26:55.39#ibcon#[25=AT05-04\r\n] 2006.201.13:26:55.39#ibcon#*before write, iclass 10, count 2 2006.201.13:26:55.39#ibcon#enter sib2, iclass 10, count 2 2006.201.13:26:55.39#ibcon#flushed, iclass 10, count 2 2006.201.13:26:55.39#ibcon#about to write, iclass 10, count 2 2006.201.13:26:55.39#ibcon#wrote, iclass 10, count 2 2006.201.13:26:55.39#ibcon#about to read 3, iclass 10, count 2 2006.201.13:26:55.42#ibcon#read 3, iclass 10, count 2 2006.201.13:26:55.42#ibcon#about to read 4, iclass 10, count 2 2006.201.13:26:55.42#ibcon#read 4, iclass 10, count 2 2006.201.13:26:55.42#ibcon#about to read 5, iclass 10, count 2 2006.201.13:26:55.42#ibcon#read 5, iclass 10, count 2 2006.201.13:26:55.42#ibcon#about to read 6, iclass 10, count 2 2006.201.13:26:55.42#ibcon#read 6, iclass 10, count 2 2006.201.13:26:55.42#ibcon#end of sib2, iclass 10, count 2 2006.201.13:26:55.42#ibcon#*after write, iclass 10, count 2 2006.201.13:26:55.42#ibcon#*before return 0, iclass 10, count 2 2006.201.13:26:55.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:55.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:55.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.13:26:55.42#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:55.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:55.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:55.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:55.54#ibcon#enter wrdev, iclass 10, count 0 2006.201.13:26:55.54#ibcon#first serial, iclass 10, count 0 2006.201.13:26:55.54#ibcon#enter sib2, iclass 10, count 0 2006.201.13:26:55.54#ibcon#flushed, iclass 10, count 0 2006.201.13:26:55.54#ibcon#about to write, iclass 10, count 0 2006.201.13:26:55.54#ibcon#wrote, iclass 10, count 0 2006.201.13:26:55.54#ibcon#about to read 3, iclass 10, count 0 2006.201.13:26:55.56#ibcon#read 3, iclass 10, count 0 2006.201.13:26:55.56#ibcon#about to read 4, iclass 10, count 0 2006.201.13:26:55.56#ibcon#read 4, iclass 10, count 0 2006.201.13:26:55.56#ibcon#about to read 5, iclass 10, count 0 2006.201.13:26:55.56#ibcon#read 5, iclass 10, count 0 2006.201.13:26:55.56#ibcon#about to read 6, iclass 10, count 0 2006.201.13:26:55.56#ibcon#read 6, iclass 10, count 0 2006.201.13:26:55.56#ibcon#end of sib2, iclass 10, count 0 2006.201.13:26:55.56#ibcon#*mode == 0, iclass 10, count 0 2006.201.13:26:55.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.13:26:55.56#ibcon#[25=USB\r\n] 2006.201.13:26:55.56#ibcon#*before write, iclass 10, count 0 2006.201.13:26:55.56#ibcon#enter sib2, iclass 10, count 0 2006.201.13:26:55.56#ibcon#flushed, iclass 10, count 0 2006.201.13:26:55.56#ibcon#about to write, iclass 10, count 0 2006.201.13:26:55.56#ibcon#wrote, iclass 10, count 0 2006.201.13:26:55.56#ibcon#about to read 3, iclass 10, count 0 2006.201.13:26:55.59#ibcon#read 3, iclass 10, count 0 2006.201.13:26:55.59#ibcon#about to read 4, iclass 10, count 0 2006.201.13:26:55.59#ibcon#read 4, iclass 10, count 0 2006.201.13:26:55.59#ibcon#about to read 5, iclass 10, count 0 2006.201.13:26:55.59#ibcon#read 5, iclass 10, count 0 2006.201.13:26:55.59#ibcon#about to read 6, iclass 10, count 0 2006.201.13:26:55.59#ibcon#read 6, iclass 10, count 0 2006.201.13:26:55.59#ibcon#end of sib2, iclass 10, count 0 2006.201.13:26:55.59#ibcon#*after write, iclass 10, count 0 2006.201.13:26:55.59#ibcon#*before return 0, iclass 10, count 0 2006.201.13:26:55.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:55.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:55.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.13:26:55.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.13:26:55.59$vck44/valo=6,814.99 2006.201.13:26:55.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.13:26:55.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.13:26:55.59#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:55.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:26:55.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:26:55.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:26:55.59#ibcon#enter wrdev, iclass 12, count 0 2006.201.13:26:55.59#ibcon#first serial, iclass 12, count 0 2006.201.13:26:55.59#ibcon#enter sib2, iclass 12, count 0 2006.201.13:26:55.59#ibcon#flushed, iclass 12, count 0 2006.201.13:26:55.59#ibcon#about to write, iclass 12, count 0 2006.201.13:26:55.59#ibcon#wrote, iclass 12, count 0 2006.201.13:26:55.59#ibcon#about to read 3, iclass 12, count 0 2006.201.13:26:55.61#ibcon#read 3, iclass 12, count 0 2006.201.13:26:55.61#ibcon#about to read 4, iclass 12, count 0 2006.201.13:26:55.61#ibcon#read 4, iclass 12, count 0 2006.201.13:26:55.61#ibcon#about to read 5, iclass 12, count 0 2006.201.13:26:55.61#ibcon#read 5, iclass 12, count 0 2006.201.13:26:55.61#ibcon#about to read 6, iclass 12, count 0 2006.201.13:26:55.61#ibcon#read 6, iclass 12, count 0 2006.201.13:26:55.61#ibcon#end of sib2, iclass 12, count 0 2006.201.13:26:55.61#ibcon#*mode == 0, iclass 12, count 0 2006.201.13:26:55.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.13:26:55.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:26:55.61#ibcon#*before write, iclass 12, count 0 2006.201.13:26:55.61#ibcon#enter sib2, iclass 12, count 0 2006.201.13:26:55.61#ibcon#flushed, iclass 12, count 0 2006.201.13:26:55.61#ibcon#about to write, iclass 12, count 0 2006.201.13:26:55.61#ibcon#wrote, iclass 12, count 0 2006.201.13:26:55.61#ibcon#about to read 3, iclass 12, count 0 2006.201.13:26:55.65#ibcon#read 3, iclass 12, count 0 2006.201.13:26:55.65#ibcon#about to read 4, iclass 12, count 0 2006.201.13:26:55.65#ibcon#read 4, iclass 12, count 0 2006.201.13:26:55.65#ibcon#about to read 5, iclass 12, count 0 2006.201.13:26:55.65#ibcon#read 5, iclass 12, count 0 2006.201.13:26:55.65#ibcon#about to read 6, iclass 12, count 0 2006.201.13:26:55.65#ibcon#read 6, iclass 12, count 0 2006.201.13:26:55.65#ibcon#end of sib2, iclass 12, count 0 2006.201.13:26:55.65#ibcon#*after write, iclass 12, count 0 2006.201.13:26:55.65#ibcon#*before return 0, iclass 12, count 0 2006.201.13:26:55.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:26:55.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:26:55.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.13:26:55.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.13:26:55.65$vck44/va=6,5 2006.201.13:26:55.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.13:26:55.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.13:26:55.65#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:55.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:26:55.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:26:55.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:26:55.71#ibcon#enter wrdev, iclass 14, count 2 2006.201.13:26:55.71#ibcon#first serial, iclass 14, count 2 2006.201.13:26:55.71#ibcon#enter sib2, iclass 14, count 2 2006.201.13:26:55.71#ibcon#flushed, iclass 14, count 2 2006.201.13:26:55.71#ibcon#about to write, iclass 14, count 2 2006.201.13:26:55.71#ibcon#wrote, iclass 14, count 2 2006.201.13:26:55.71#ibcon#about to read 3, iclass 14, count 2 2006.201.13:26:55.73#ibcon#read 3, iclass 14, count 2 2006.201.13:26:55.73#ibcon#about to read 4, iclass 14, count 2 2006.201.13:26:55.73#ibcon#read 4, iclass 14, count 2 2006.201.13:26:55.73#ibcon#about to read 5, iclass 14, count 2 2006.201.13:26:55.73#ibcon#read 5, iclass 14, count 2 2006.201.13:26:55.73#ibcon#about to read 6, iclass 14, count 2 2006.201.13:26:55.73#ibcon#read 6, iclass 14, count 2 2006.201.13:26:55.73#ibcon#end of sib2, iclass 14, count 2 2006.201.13:26:55.73#ibcon#*mode == 0, iclass 14, count 2 2006.201.13:26:55.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.13:26:55.73#ibcon#[25=AT06-05\r\n] 2006.201.13:26:55.73#ibcon#*before write, iclass 14, count 2 2006.201.13:26:55.73#ibcon#enter sib2, iclass 14, count 2 2006.201.13:26:55.73#ibcon#flushed, iclass 14, count 2 2006.201.13:26:55.73#ibcon#about to write, iclass 14, count 2 2006.201.13:26:55.73#ibcon#wrote, iclass 14, count 2 2006.201.13:26:55.73#ibcon#about to read 3, iclass 14, count 2 2006.201.13:26:55.76#ibcon#read 3, iclass 14, count 2 2006.201.13:26:55.76#ibcon#about to read 4, iclass 14, count 2 2006.201.13:26:55.76#ibcon#read 4, iclass 14, count 2 2006.201.13:26:55.76#ibcon#about to read 5, iclass 14, count 2 2006.201.13:26:55.76#ibcon#read 5, iclass 14, count 2 2006.201.13:26:55.76#ibcon#about to read 6, iclass 14, count 2 2006.201.13:26:55.76#ibcon#read 6, iclass 14, count 2 2006.201.13:26:55.76#ibcon#end of sib2, iclass 14, count 2 2006.201.13:26:55.76#ibcon#*after write, iclass 14, count 2 2006.201.13:26:55.76#ibcon#*before return 0, iclass 14, count 2 2006.201.13:26:55.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:26:55.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:26:55.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.13:26:55.76#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:55.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:26:55.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:26:55.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:26:55.88#ibcon#enter wrdev, iclass 14, count 0 2006.201.13:26:55.88#ibcon#first serial, iclass 14, count 0 2006.201.13:26:55.88#ibcon#enter sib2, iclass 14, count 0 2006.201.13:26:55.88#ibcon#flushed, iclass 14, count 0 2006.201.13:26:55.88#ibcon#about to write, iclass 14, count 0 2006.201.13:26:55.88#ibcon#wrote, iclass 14, count 0 2006.201.13:26:55.88#ibcon#about to read 3, iclass 14, count 0 2006.201.13:26:55.90#ibcon#read 3, iclass 14, count 0 2006.201.13:26:55.90#ibcon#about to read 4, iclass 14, count 0 2006.201.13:26:55.90#ibcon#read 4, iclass 14, count 0 2006.201.13:26:55.90#ibcon#about to read 5, iclass 14, count 0 2006.201.13:26:55.90#ibcon#read 5, iclass 14, count 0 2006.201.13:26:55.90#ibcon#about to read 6, iclass 14, count 0 2006.201.13:26:55.90#ibcon#read 6, iclass 14, count 0 2006.201.13:26:55.90#ibcon#end of sib2, iclass 14, count 0 2006.201.13:26:55.90#ibcon#*mode == 0, iclass 14, count 0 2006.201.13:26:55.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.13:26:55.90#ibcon#[25=USB\r\n] 2006.201.13:26:55.90#ibcon#*before write, iclass 14, count 0 2006.201.13:26:55.90#ibcon#enter sib2, iclass 14, count 0 2006.201.13:26:55.90#ibcon#flushed, iclass 14, count 0 2006.201.13:26:55.90#ibcon#about to write, iclass 14, count 0 2006.201.13:26:55.90#ibcon#wrote, iclass 14, count 0 2006.201.13:26:55.90#ibcon#about to read 3, iclass 14, count 0 2006.201.13:26:55.93#ibcon#read 3, iclass 14, count 0 2006.201.13:26:55.93#ibcon#about to read 4, iclass 14, count 0 2006.201.13:26:55.93#ibcon#read 4, iclass 14, count 0 2006.201.13:26:55.93#ibcon#about to read 5, iclass 14, count 0 2006.201.13:26:55.93#ibcon#read 5, iclass 14, count 0 2006.201.13:26:55.93#ibcon#about to read 6, iclass 14, count 0 2006.201.13:26:55.93#ibcon#read 6, iclass 14, count 0 2006.201.13:26:55.93#ibcon#end of sib2, iclass 14, count 0 2006.201.13:26:55.93#ibcon#*after write, iclass 14, count 0 2006.201.13:26:55.93#ibcon#*before return 0, iclass 14, count 0 2006.201.13:26:55.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:26:55.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:26:55.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.13:26:55.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.13:26:55.93$vck44/valo=7,864.99 2006.201.13:26:55.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.13:26:55.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.13:26:55.93#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:55.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:55.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:55.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:55.93#ibcon#enter wrdev, iclass 16, count 0 2006.201.13:26:55.93#ibcon#first serial, iclass 16, count 0 2006.201.13:26:55.93#ibcon#enter sib2, iclass 16, count 0 2006.201.13:26:55.93#ibcon#flushed, iclass 16, count 0 2006.201.13:26:55.93#ibcon#about to write, iclass 16, count 0 2006.201.13:26:55.93#ibcon#wrote, iclass 16, count 0 2006.201.13:26:55.93#ibcon#about to read 3, iclass 16, count 0 2006.201.13:26:55.95#ibcon#read 3, iclass 16, count 0 2006.201.13:26:55.95#ibcon#about to read 4, iclass 16, count 0 2006.201.13:26:55.95#ibcon#read 4, iclass 16, count 0 2006.201.13:26:55.95#ibcon#about to read 5, iclass 16, count 0 2006.201.13:26:55.95#ibcon#read 5, iclass 16, count 0 2006.201.13:26:55.95#ibcon#about to read 6, iclass 16, count 0 2006.201.13:26:55.95#ibcon#read 6, iclass 16, count 0 2006.201.13:26:55.95#ibcon#end of sib2, iclass 16, count 0 2006.201.13:26:55.95#ibcon#*mode == 0, iclass 16, count 0 2006.201.13:26:55.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.13:26:55.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:26:55.95#ibcon#*before write, iclass 16, count 0 2006.201.13:26:55.95#ibcon#enter sib2, iclass 16, count 0 2006.201.13:26:55.95#ibcon#flushed, iclass 16, count 0 2006.201.13:26:55.95#ibcon#about to write, iclass 16, count 0 2006.201.13:26:55.95#ibcon#wrote, iclass 16, count 0 2006.201.13:26:55.95#ibcon#about to read 3, iclass 16, count 0 2006.201.13:26:55.99#ibcon#read 3, iclass 16, count 0 2006.201.13:26:55.99#ibcon#about to read 4, iclass 16, count 0 2006.201.13:26:55.99#ibcon#read 4, iclass 16, count 0 2006.201.13:26:55.99#ibcon#about to read 5, iclass 16, count 0 2006.201.13:26:55.99#ibcon#read 5, iclass 16, count 0 2006.201.13:26:55.99#ibcon#about to read 6, iclass 16, count 0 2006.201.13:26:55.99#ibcon#read 6, iclass 16, count 0 2006.201.13:26:55.99#ibcon#end of sib2, iclass 16, count 0 2006.201.13:26:55.99#ibcon#*after write, iclass 16, count 0 2006.201.13:26:55.99#ibcon#*before return 0, iclass 16, count 0 2006.201.13:26:55.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:55.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:55.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.13:26:55.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.13:26:55.99$vck44/va=7,5 2006.201.13:26:55.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.13:26:55.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.13:26:55.99#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:55.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:56.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:56.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:56.05#ibcon#enter wrdev, iclass 18, count 2 2006.201.13:26:56.05#ibcon#first serial, iclass 18, count 2 2006.201.13:26:56.05#ibcon#enter sib2, iclass 18, count 2 2006.201.13:26:56.05#ibcon#flushed, iclass 18, count 2 2006.201.13:26:56.05#ibcon#about to write, iclass 18, count 2 2006.201.13:26:56.05#ibcon#wrote, iclass 18, count 2 2006.201.13:26:56.05#ibcon#about to read 3, iclass 18, count 2 2006.201.13:26:56.07#ibcon#read 3, iclass 18, count 2 2006.201.13:26:56.07#ibcon#about to read 4, iclass 18, count 2 2006.201.13:26:56.07#ibcon#read 4, iclass 18, count 2 2006.201.13:26:56.07#ibcon#about to read 5, iclass 18, count 2 2006.201.13:26:56.07#ibcon#read 5, iclass 18, count 2 2006.201.13:26:56.07#ibcon#about to read 6, iclass 18, count 2 2006.201.13:26:56.07#ibcon#read 6, iclass 18, count 2 2006.201.13:26:56.07#ibcon#end of sib2, iclass 18, count 2 2006.201.13:26:56.07#ibcon#*mode == 0, iclass 18, count 2 2006.201.13:26:56.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.13:26:56.07#ibcon#[25=AT07-05\r\n] 2006.201.13:26:56.07#ibcon#*before write, iclass 18, count 2 2006.201.13:26:56.07#ibcon#enter sib2, iclass 18, count 2 2006.201.13:26:56.07#ibcon#flushed, iclass 18, count 2 2006.201.13:26:56.07#ibcon#about to write, iclass 18, count 2 2006.201.13:26:56.07#ibcon#wrote, iclass 18, count 2 2006.201.13:26:56.07#ibcon#about to read 3, iclass 18, count 2 2006.201.13:26:56.10#ibcon#read 3, iclass 18, count 2 2006.201.13:26:56.10#ibcon#about to read 4, iclass 18, count 2 2006.201.13:26:56.10#ibcon#read 4, iclass 18, count 2 2006.201.13:26:56.10#ibcon#about to read 5, iclass 18, count 2 2006.201.13:26:56.10#ibcon#read 5, iclass 18, count 2 2006.201.13:26:56.10#ibcon#about to read 6, iclass 18, count 2 2006.201.13:26:56.10#ibcon#read 6, iclass 18, count 2 2006.201.13:26:56.10#ibcon#end of sib2, iclass 18, count 2 2006.201.13:26:56.10#ibcon#*after write, iclass 18, count 2 2006.201.13:26:56.10#ibcon#*before return 0, iclass 18, count 2 2006.201.13:26:56.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:56.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:56.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.13:26:56.10#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:56.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:56.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:56.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:56.22#ibcon#enter wrdev, iclass 18, count 0 2006.201.13:26:56.22#ibcon#first serial, iclass 18, count 0 2006.201.13:26:56.22#ibcon#enter sib2, iclass 18, count 0 2006.201.13:26:56.22#ibcon#flushed, iclass 18, count 0 2006.201.13:26:56.22#ibcon#about to write, iclass 18, count 0 2006.201.13:26:56.22#ibcon#wrote, iclass 18, count 0 2006.201.13:26:56.22#ibcon#about to read 3, iclass 18, count 0 2006.201.13:26:56.24#ibcon#read 3, iclass 18, count 0 2006.201.13:26:56.24#ibcon#about to read 4, iclass 18, count 0 2006.201.13:26:56.24#ibcon#read 4, iclass 18, count 0 2006.201.13:26:56.24#ibcon#about to read 5, iclass 18, count 0 2006.201.13:26:56.24#ibcon#read 5, iclass 18, count 0 2006.201.13:26:56.24#ibcon#about to read 6, iclass 18, count 0 2006.201.13:26:56.24#ibcon#read 6, iclass 18, count 0 2006.201.13:26:56.24#ibcon#end of sib2, iclass 18, count 0 2006.201.13:26:56.24#ibcon#*mode == 0, iclass 18, count 0 2006.201.13:26:56.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.13:26:56.24#ibcon#[25=USB\r\n] 2006.201.13:26:56.24#ibcon#*before write, iclass 18, count 0 2006.201.13:26:56.24#ibcon#enter sib2, iclass 18, count 0 2006.201.13:26:56.24#ibcon#flushed, iclass 18, count 0 2006.201.13:26:56.24#ibcon#about to write, iclass 18, count 0 2006.201.13:26:56.24#ibcon#wrote, iclass 18, count 0 2006.201.13:26:56.24#ibcon#about to read 3, iclass 18, count 0 2006.201.13:26:56.27#ibcon#read 3, iclass 18, count 0 2006.201.13:26:56.27#ibcon#about to read 4, iclass 18, count 0 2006.201.13:26:56.27#ibcon#read 4, iclass 18, count 0 2006.201.13:26:56.27#ibcon#about to read 5, iclass 18, count 0 2006.201.13:26:56.27#ibcon#read 5, iclass 18, count 0 2006.201.13:26:56.27#ibcon#about to read 6, iclass 18, count 0 2006.201.13:26:56.27#ibcon#read 6, iclass 18, count 0 2006.201.13:26:56.27#ibcon#end of sib2, iclass 18, count 0 2006.201.13:26:56.27#ibcon#*after write, iclass 18, count 0 2006.201.13:26:56.27#ibcon#*before return 0, iclass 18, count 0 2006.201.13:26:56.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:56.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:56.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.13:26:56.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.13:26:56.27$vck44/valo=8,884.99 2006.201.13:26:56.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.13:26:56.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.13:26:56.27#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:56.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:56.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:56.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:56.27#ibcon#enter wrdev, iclass 20, count 0 2006.201.13:26:56.27#ibcon#first serial, iclass 20, count 0 2006.201.13:26:56.27#ibcon#enter sib2, iclass 20, count 0 2006.201.13:26:56.27#ibcon#flushed, iclass 20, count 0 2006.201.13:26:56.27#ibcon#about to write, iclass 20, count 0 2006.201.13:26:56.27#ibcon#wrote, iclass 20, count 0 2006.201.13:26:56.27#ibcon#about to read 3, iclass 20, count 0 2006.201.13:26:56.29#ibcon#read 3, iclass 20, count 0 2006.201.13:26:56.29#ibcon#about to read 4, iclass 20, count 0 2006.201.13:26:56.29#ibcon#read 4, iclass 20, count 0 2006.201.13:26:56.29#ibcon#about to read 5, iclass 20, count 0 2006.201.13:26:56.29#ibcon#read 5, iclass 20, count 0 2006.201.13:26:56.29#ibcon#about to read 6, iclass 20, count 0 2006.201.13:26:56.29#ibcon#read 6, iclass 20, count 0 2006.201.13:26:56.29#ibcon#end of sib2, iclass 20, count 0 2006.201.13:26:56.29#ibcon#*mode == 0, iclass 20, count 0 2006.201.13:26:56.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.13:26:56.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:26:56.29#ibcon#*before write, iclass 20, count 0 2006.201.13:26:56.29#ibcon#enter sib2, iclass 20, count 0 2006.201.13:26:56.29#ibcon#flushed, iclass 20, count 0 2006.201.13:26:56.29#ibcon#about to write, iclass 20, count 0 2006.201.13:26:56.29#ibcon#wrote, iclass 20, count 0 2006.201.13:26:56.29#ibcon#about to read 3, iclass 20, count 0 2006.201.13:26:56.33#ibcon#read 3, iclass 20, count 0 2006.201.13:26:56.33#ibcon#about to read 4, iclass 20, count 0 2006.201.13:26:56.33#ibcon#read 4, iclass 20, count 0 2006.201.13:26:56.33#ibcon#about to read 5, iclass 20, count 0 2006.201.13:26:56.33#ibcon#read 5, iclass 20, count 0 2006.201.13:26:56.33#ibcon#about to read 6, iclass 20, count 0 2006.201.13:26:56.33#ibcon#read 6, iclass 20, count 0 2006.201.13:26:56.33#ibcon#end of sib2, iclass 20, count 0 2006.201.13:26:56.33#ibcon#*after write, iclass 20, count 0 2006.201.13:26:56.33#ibcon#*before return 0, iclass 20, count 0 2006.201.13:26:56.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:56.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:56.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.13:26:56.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.13:26:56.33$vck44/va=8,4 2006.201.13:26:56.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.13:26:56.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.13:26:56.33#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:56.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:56.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:56.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:56.39#ibcon#enter wrdev, iclass 22, count 2 2006.201.13:26:56.39#ibcon#first serial, iclass 22, count 2 2006.201.13:26:56.39#ibcon#enter sib2, iclass 22, count 2 2006.201.13:26:56.39#ibcon#flushed, iclass 22, count 2 2006.201.13:26:56.39#ibcon#about to write, iclass 22, count 2 2006.201.13:26:56.39#ibcon#wrote, iclass 22, count 2 2006.201.13:26:56.39#ibcon#about to read 3, iclass 22, count 2 2006.201.13:26:56.41#ibcon#read 3, iclass 22, count 2 2006.201.13:26:56.41#ibcon#about to read 4, iclass 22, count 2 2006.201.13:26:56.41#ibcon#read 4, iclass 22, count 2 2006.201.13:26:56.41#ibcon#about to read 5, iclass 22, count 2 2006.201.13:26:56.41#ibcon#read 5, iclass 22, count 2 2006.201.13:26:56.41#ibcon#about to read 6, iclass 22, count 2 2006.201.13:26:56.41#ibcon#read 6, iclass 22, count 2 2006.201.13:26:56.41#ibcon#end of sib2, iclass 22, count 2 2006.201.13:26:56.41#ibcon#*mode == 0, iclass 22, count 2 2006.201.13:26:56.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.13:26:56.41#ibcon#[25=AT08-04\r\n] 2006.201.13:26:56.41#ibcon#*before write, iclass 22, count 2 2006.201.13:26:56.41#ibcon#enter sib2, iclass 22, count 2 2006.201.13:26:56.41#ibcon#flushed, iclass 22, count 2 2006.201.13:26:56.41#ibcon#about to write, iclass 22, count 2 2006.201.13:26:56.41#ibcon#wrote, iclass 22, count 2 2006.201.13:26:56.41#ibcon#about to read 3, iclass 22, count 2 2006.201.13:26:56.44#ibcon#read 3, iclass 22, count 2 2006.201.13:26:56.44#ibcon#about to read 4, iclass 22, count 2 2006.201.13:26:56.44#ibcon#read 4, iclass 22, count 2 2006.201.13:26:56.44#ibcon#about to read 5, iclass 22, count 2 2006.201.13:26:56.44#ibcon#read 5, iclass 22, count 2 2006.201.13:26:56.44#ibcon#about to read 6, iclass 22, count 2 2006.201.13:26:56.44#ibcon#read 6, iclass 22, count 2 2006.201.13:26:56.44#ibcon#end of sib2, iclass 22, count 2 2006.201.13:26:56.44#ibcon#*after write, iclass 22, count 2 2006.201.13:26:56.44#ibcon#*before return 0, iclass 22, count 2 2006.201.13:26:56.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:56.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:56.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.13:26:56.44#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:56.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:56.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:56.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:56.56#ibcon#enter wrdev, iclass 22, count 0 2006.201.13:26:56.56#ibcon#first serial, iclass 22, count 0 2006.201.13:26:56.56#ibcon#enter sib2, iclass 22, count 0 2006.201.13:26:56.56#ibcon#flushed, iclass 22, count 0 2006.201.13:26:56.56#ibcon#about to write, iclass 22, count 0 2006.201.13:26:56.56#ibcon#wrote, iclass 22, count 0 2006.201.13:26:56.56#ibcon#about to read 3, iclass 22, count 0 2006.201.13:26:56.58#ibcon#read 3, iclass 22, count 0 2006.201.13:26:56.58#ibcon#about to read 4, iclass 22, count 0 2006.201.13:26:56.58#ibcon#read 4, iclass 22, count 0 2006.201.13:26:56.58#ibcon#about to read 5, iclass 22, count 0 2006.201.13:26:56.58#ibcon#read 5, iclass 22, count 0 2006.201.13:26:56.58#ibcon#about to read 6, iclass 22, count 0 2006.201.13:26:56.58#ibcon#read 6, iclass 22, count 0 2006.201.13:26:56.58#ibcon#end of sib2, iclass 22, count 0 2006.201.13:26:56.58#ibcon#*mode == 0, iclass 22, count 0 2006.201.13:26:56.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.13:26:56.58#ibcon#[25=USB\r\n] 2006.201.13:26:56.58#ibcon#*before write, iclass 22, count 0 2006.201.13:26:56.58#ibcon#enter sib2, iclass 22, count 0 2006.201.13:26:56.58#ibcon#flushed, iclass 22, count 0 2006.201.13:26:56.58#ibcon#about to write, iclass 22, count 0 2006.201.13:26:56.58#ibcon#wrote, iclass 22, count 0 2006.201.13:26:56.58#ibcon#about to read 3, iclass 22, count 0 2006.201.13:26:56.61#ibcon#read 3, iclass 22, count 0 2006.201.13:26:56.61#ibcon#about to read 4, iclass 22, count 0 2006.201.13:26:56.61#ibcon#read 4, iclass 22, count 0 2006.201.13:26:56.61#ibcon#about to read 5, iclass 22, count 0 2006.201.13:26:56.61#ibcon#read 5, iclass 22, count 0 2006.201.13:26:56.61#ibcon#about to read 6, iclass 22, count 0 2006.201.13:26:56.61#ibcon#read 6, iclass 22, count 0 2006.201.13:26:56.61#ibcon#end of sib2, iclass 22, count 0 2006.201.13:26:56.61#ibcon#*after write, iclass 22, count 0 2006.201.13:26:56.61#ibcon#*before return 0, iclass 22, count 0 2006.201.13:26:56.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:56.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:56.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.13:26:56.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.13:26:56.61$vck44/vblo=1,629.99 2006.201.13:26:56.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.13:26:56.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.13:26:56.61#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:56.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:56.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:56.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:56.61#ibcon#enter wrdev, iclass 24, count 0 2006.201.13:26:56.61#ibcon#first serial, iclass 24, count 0 2006.201.13:26:56.61#ibcon#enter sib2, iclass 24, count 0 2006.201.13:26:56.61#ibcon#flushed, iclass 24, count 0 2006.201.13:26:56.61#ibcon#about to write, iclass 24, count 0 2006.201.13:26:56.61#ibcon#wrote, iclass 24, count 0 2006.201.13:26:56.61#ibcon#about to read 3, iclass 24, count 0 2006.201.13:26:56.63#ibcon#read 3, iclass 24, count 0 2006.201.13:26:56.63#ibcon#about to read 4, iclass 24, count 0 2006.201.13:26:56.63#ibcon#read 4, iclass 24, count 0 2006.201.13:26:56.63#ibcon#about to read 5, iclass 24, count 0 2006.201.13:26:56.63#ibcon#read 5, iclass 24, count 0 2006.201.13:26:56.63#ibcon#about to read 6, iclass 24, count 0 2006.201.13:26:56.63#ibcon#read 6, iclass 24, count 0 2006.201.13:26:56.63#ibcon#end of sib2, iclass 24, count 0 2006.201.13:26:56.63#ibcon#*mode == 0, iclass 24, count 0 2006.201.13:26:56.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.13:26:56.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:26:56.63#ibcon#*before write, iclass 24, count 0 2006.201.13:26:56.63#ibcon#enter sib2, iclass 24, count 0 2006.201.13:26:56.63#ibcon#flushed, iclass 24, count 0 2006.201.13:26:56.63#ibcon#about to write, iclass 24, count 0 2006.201.13:26:56.63#ibcon#wrote, iclass 24, count 0 2006.201.13:26:56.63#ibcon#about to read 3, iclass 24, count 0 2006.201.13:26:56.67#ibcon#read 3, iclass 24, count 0 2006.201.13:26:56.67#ibcon#about to read 4, iclass 24, count 0 2006.201.13:26:56.67#ibcon#read 4, iclass 24, count 0 2006.201.13:26:56.67#ibcon#about to read 5, iclass 24, count 0 2006.201.13:26:56.67#ibcon#read 5, iclass 24, count 0 2006.201.13:26:56.67#ibcon#about to read 6, iclass 24, count 0 2006.201.13:26:56.67#ibcon#read 6, iclass 24, count 0 2006.201.13:26:56.67#ibcon#end of sib2, iclass 24, count 0 2006.201.13:26:56.67#ibcon#*after write, iclass 24, count 0 2006.201.13:26:56.67#ibcon#*before return 0, iclass 24, count 0 2006.201.13:26:56.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:56.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:56.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.13:26:56.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.13:26:56.67$vck44/vb=1,4 2006.201.13:26:56.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.13:26:56.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.13:26:56.67#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:56.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:26:56.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:26:56.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:26:56.67#ibcon#enter wrdev, iclass 26, count 2 2006.201.13:26:56.67#ibcon#first serial, iclass 26, count 2 2006.201.13:26:56.67#ibcon#enter sib2, iclass 26, count 2 2006.201.13:26:56.67#ibcon#flushed, iclass 26, count 2 2006.201.13:26:56.67#ibcon#about to write, iclass 26, count 2 2006.201.13:26:56.67#ibcon#wrote, iclass 26, count 2 2006.201.13:26:56.67#ibcon#about to read 3, iclass 26, count 2 2006.201.13:26:56.69#ibcon#read 3, iclass 26, count 2 2006.201.13:26:56.69#ibcon#about to read 4, iclass 26, count 2 2006.201.13:26:56.69#ibcon#read 4, iclass 26, count 2 2006.201.13:26:56.69#ibcon#about to read 5, iclass 26, count 2 2006.201.13:26:56.69#ibcon#read 5, iclass 26, count 2 2006.201.13:26:56.69#ibcon#about to read 6, iclass 26, count 2 2006.201.13:26:56.69#ibcon#read 6, iclass 26, count 2 2006.201.13:26:56.69#ibcon#end of sib2, iclass 26, count 2 2006.201.13:26:56.69#ibcon#*mode == 0, iclass 26, count 2 2006.201.13:26:56.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.13:26:56.69#ibcon#[27=AT01-04\r\n] 2006.201.13:26:56.69#ibcon#*before write, iclass 26, count 2 2006.201.13:26:56.69#ibcon#enter sib2, iclass 26, count 2 2006.201.13:26:56.69#ibcon#flushed, iclass 26, count 2 2006.201.13:26:56.69#ibcon#about to write, iclass 26, count 2 2006.201.13:26:56.69#ibcon#wrote, iclass 26, count 2 2006.201.13:26:56.69#ibcon#about to read 3, iclass 26, count 2 2006.201.13:26:56.72#ibcon#read 3, iclass 26, count 2 2006.201.13:26:56.72#ibcon#about to read 4, iclass 26, count 2 2006.201.13:26:56.72#ibcon#read 4, iclass 26, count 2 2006.201.13:26:56.72#ibcon#about to read 5, iclass 26, count 2 2006.201.13:26:56.72#ibcon#read 5, iclass 26, count 2 2006.201.13:26:56.72#ibcon#about to read 6, iclass 26, count 2 2006.201.13:26:56.72#ibcon#read 6, iclass 26, count 2 2006.201.13:26:56.72#ibcon#end of sib2, iclass 26, count 2 2006.201.13:26:56.72#ibcon#*after write, iclass 26, count 2 2006.201.13:26:56.72#ibcon#*before return 0, iclass 26, count 2 2006.201.13:26:56.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:26:56.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:26:56.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.13:26:56.72#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:56.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:26:56.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:26:56.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:26:56.84#ibcon#enter wrdev, iclass 26, count 0 2006.201.13:26:56.84#ibcon#first serial, iclass 26, count 0 2006.201.13:26:56.84#ibcon#enter sib2, iclass 26, count 0 2006.201.13:26:56.84#ibcon#flushed, iclass 26, count 0 2006.201.13:26:56.84#ibcon#about to write, iclass 26, count 0 2006.201.13:26:56.84#ibcon#wrote, iclass 26, count 0 2006.201.13:26:56.84#ibcon#about to read 3, iclass 26, count 0 2006.201.13:26:56.86#ibcon#read 3, iclass 26, count 0 2006.201.13:26:56.86#ibcon#about to read 4, iclass 26, count 0 2006.201.13:26:56.86#ibcon#read 4, iclass 26, count 0 2006.201.13:26:56.86#ibcon#about to read 5, iclass 26, count 0 2006.201.13:26:56.86#ibcon#read 5, iclass 26, count 0 2006.201.13:26:56.86#ibcon#about to read 6, iclass 26, count 0 2006.201.13:26:56.86#ibcon#read 6, iclass 26, count 0 2006.201.13:26:56.86#ibcon#end of sib2, iclass 26, count 0 2006.201.13:26:56.86#ibcon#*mode == 0, iclass 26, count 0 2006.201.13:26:56.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.13:26:56.86#ibcon#[27=USB\r\n] 2006.201.13:26:56.86#ibcon#*before write, iclass 26, count 0 2006.201.13:26:56.86#ibcon#enter sib2, iclass 26, count 0 2006.201.13:26:56.86#ibcon#flushed, iclass 26, count 0 2006.201.13:26:56.86#ibcon#about to write, iclass 26, count 0 2006.201.13:26:56.86#ibcon#wrote, iclass 26, count 0 2006.201.13:26:56.86#ibcon#about to read 3, iclass 26, count 0 2006.201.13:26:56.89#ibcon#read 3, iclass 26, count 0 2006.201.13:26:56.89#ibcon#about to read 4, iclass 26, count 0 2006.201.13:26:56.89#ibcon#read 4, iclass 26, count 0 2006.201.13:26:56.89#ibcon#about to read 5, iclass 26, count 0 2006.201.13:26:56.89#ibcon#read 5, iclass 26, count 0 2006.201.13:26:56.89#ibcon#about to read 6, iclass 26, count 0 2006.201.13:26:56.89#ibcon#read 6, iclass 26, count 0 2006.201.13:26:56.89#ibcon#end of sib2, iclass 26, count 0 2006.201.13:26:56.89#ibcon#*after write, iclass 26, count 0 2006.201.13:26:56.89#ibcon#*before return 0, iclass 26, count 0 2006.201.13:26:56.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:26:56.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:26:56.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.13:26:56.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.13:26:56.89$vck44/vblo=2,634.99 2006.201.13:26:56.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.13:26:56.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.13:26:56.89#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:56.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:56.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:56.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:56.89#ibcon#enter wrdev, iclass 28, count 0 2006.201.13:26:56.89#ibcon#first serial, iclass 28, count 0 2006.201.13:26:56.89#ibcon#enter sib2, iclass 28, count 0 2006.201.13:26:56.89#ibcon#flushed, iclass 28, count 0 2006.201.13:26:56.89#ibcon#about to write, iclass 28, count 0 2006.201.13:26:56.89#ibcon#wrote, iclass 28, count 0 2006.201.13:26:56.89#ibcon#about to read 3, iclass 28, count 0 2006.201.13:26:56.91#ibcon#read 3, iclass 28, count 0 2006.201.13:26:56.91#ibcon#about to read 4, iclass 28, count 0 2006.201.13:26:56.91#ibcon#read 4, iclass 28, count 0 2006.201.13:26:56.91#ibcon#about to read 5, iclass 28, count 0 2006.201.13:26:56.91#ibcon#read 5, iclass 28, count 0 2006.201.13:26:56.91#ibcon#about to read 6, iclass 28, count 0 2006.201.13:26:56.91#ibcon#read 6, iclass 28, count 0 2006.201.13:26:56.91#ibcon#end of sib2, iclass 28, count 0 2006.201.13:26:56.91#ibcon#*mode == 0, iclass 28, count 0 2006.201.13:26:56.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.13:26:56.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:26:56.91#ibcon#*before write, iclass 28, count 0 2006.201.13:26:56.91#ibcon#enter sib2, iclass 28, count 0 2006.201.13:26:56.91#ibcon#flushed, iclass 28, count 0 2006.201.13:26:56.91#ibcon#about to write, iclass 28, count 0 2006.201.13:26:56.91#ibcon#wrote, iclass 28, count 0 2006.201.13:26:56.91#ibcon#about to read 3, iclass 28, count 0 2006.201.13:26:56.95#ibcon#read 3, iclass 28, count 0 2006.201.13:26:56.95#ibcon#about to read 4, iclass 28, count 0 2006.201.13:26:56.95#ibcon#read 4, iclass 28, count 0 2006.201.13:26:56.95#ibcon#about to read 5, iclass 28, count 0 2006.201.13:26:56.95#ibcon#read 5, iclass 28, count 0 2006.201.13:26:56.95#ibcon#about to read 6, iclass 28, count 0 2006.201.13:26:56.95#ibcon#read 6, iclass 28, count 0 2006.201.13:26:56.95#ibcon#end of sib2, iclass 28, count 0 2006.201.13:26:56.95#ibcon#*after write, iclass 28, count 0 2006.201.13:26:56.95#ibcon#*before return 0, iclass 28, count 0 2006.201.13:26:56.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:56.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:26:56.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.13:26:56.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.13:26:56.95$vck44/vb=2,5 2006.201.13:26:56.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.13:26:56.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.13:26:56.95#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:56.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:57.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:57.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:57.01#ibcon#enter wrdev, iclass 30, count 2 2006.201.13:26:57.01#ibcon#first serial, iclass 30, count 2 2006.201.13:26:57.01#ibcon#enter sib2, iclass 30, count 2 2006.201.13:26:57.01#ibcon#flushed, iclass 30, count 2 2006.201.13:26:57.01#ibcon#about to write, iclass 30, count 2 2006.201.13:26:57.01#ibcon#wrote, iclass 30, count 2 2006.201.13:26:57.01#ibcon#about to read 3, iclass 30, count 2 2006.201.13:26:57.03#ibcon#read 3, iclass 30, count 2 2006.201.13:26:57.03#ibcon#about to read 4, iclass 30, count 2 2006.201.13:26:57.03#ibcon#read 4, iclass 30, count 2 2006.201.13:26:57.03#ibcon#about to read 5, iclass 30, count 2 2006.201.13:26:57.03#ibcon#read 5, iclass 30, count 2 2006.201.13:26:57.03#ibcon#about to read 6, iclass 30, count 2 2006.201.13:26:57.03#ibcon#read 6, iclass 30, count 2 2006.201.13:26:57.03#ibcon#end of sib2, iclass 30, count 2 2006.201.13:26:57.03#ibcon#*mode == 0, iclass 30, count 2 2006.201.13:26:57.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.13:26:57.03#ibcon#[27=AT02-05\r\n] 2006.201.13:26:57.03#ibcon#*before write, iclass 30, count 2 2006.201.13:26:57.03#ibcon#enter sib2, iclass 30, count 2 2006.201.13:26:57.03#ibcon#flushed, iclass 30, count 2 2006.201.13:26:57.03#ibcon#about to write, iclass 30, count 2 2006.201.13:26:57.03#ibcon#wrote, iclass 30, count 2 2006.201.13:26:57.03#ibcon#about to read 3, iclass 30, count 2 2006.201.13:26:57.06#ibcon#read 3, iclass 30, count 2 2006.201.13:26:57.06#ibcon#about to read 4, iclass 30, count 2 2006.201.13:26:57.06#ibcon#read 4, iclass 30, count 2 2006.201.13:26:57.06#ibcon#about to read 5, iclass 30, count 2 2006.201.13:26:57.06#ibcon#read 5, iclass 30, count 2 2006.201.13:26:57.06#ibcon#about to read 6, iclass 30, count 2 2006.201.13:26:57.06#ibcon#read 6, iclass 30, count 2 2006.201.13:26:57.06#ibcon#end of sib2, iclass 30, count 2 2006.201.13:26:57.06#ibcon#*after write, iclass 30, count 2 2006.201.13:26:57.06#ibcon#*before return 0, iclass 30, count 2 2006.201.13:26:57.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:57.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:26:57.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.13:26:57.06#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:57.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:57.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:57.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:57.18#ibcon#enter wrdev, iclass 30, count 0 2006.201.13:26:57.18#ibcon#first serial, iclass 30, count 0 2006.201.13:26:57.18#ibcon#enter sib2, iclass 30, count 0 2006.201.13:26:57.18#ibcon#flushed, iclass 30, count 0 2006.201.13:26:57.18#ibcon#about to write, iclass 30, count 0 2006.201.13:26:57.18#ibcon#wrote, iclass 30, count 0 2006.201.13:26:57.18#ibcon#about to read 3, iclass 30, count 0 2006.201.13:26:57.20#ibcon#read 3, iclass 30, count 0 2006.201.13:26:57.20#ibcon#about to read 4, iclass 30, count 0 2006.201.13:26:57.20#ibcon#read 4, iclass 30, count 0 2006.201.13:26:57.20#ibcon#about to read 5, iclass 30, count 0 2006.201.13:26:57.20#ibcon#read 5, iclass 30, count 0 2006.201.13:26:57.20#ibcon#about to read 6, iclass 30, count 0 2006.201.13:26:57.20#ibcon#read 6, iclass 30, count 0 2006.201.13:26:57.20#ibcon#end of sib2, iclass 30, count 0 2006.201.13:26:57.20#ibcon#*mode == 0, iclass 30, count 0 2006.201.13:26:57.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.13:26:57.20#ibcon#[27=USB\r\n] 2006.201.13:26:57.20#ibcon#*before write, iclass 30, count 0 2006.201.13:26:57.20#ibcon#enter sib2, iclass 30, count 0 2006.201.13:26:57.20#ibcon#flushed, iclass 30, count 0 2006.201.13:26:57.20#ibcon#about to write, iclass 30, count 0 2006.201.13:26:57.20#ibcon#wrote, iclass 30, count 0 2006.201.13:26:57.20#ibcon#about to read 3, iclass 30, count 0 2006.201.13:26:57.23#ibcon#read 3, iclass 30, count 0 2006.201.13:26:57.23#ibcon#about to read 4, iclass 30, count 0 2006.201.13:26:57.23#ibcon#read 4, iclass 30, count 0 2006.201.13:26:57.23#ibcon#about to read 5, iclass 30, count 0 2006.201.13:26:57.23#ibcon#read 5, iclass 30, count 0 2006.201.13:26:57.23#ibcon#about to read 6, iclass 30, count 0 2006.201.13:26:57.23#ibcon#read 6, iclass 30, count 0 2006.201.13:26:57.23#ibcon#end of sib2, iclass 30, count 0 2006.201.13:26:57.23#ibcon#*after write, iclass 30, count 0 2006.201.13:26:57.23#ibcon#*before return 0, iclass 30, count 0 2006.201.13:26:57.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:57.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:26:57.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.13:26:57.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.13:26:57.23$vck44/vblo=3,649.99 2006.201.13:26:57.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.13:26:57.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.13:26:57.23#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:57.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:57.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:57.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:57.23#ibcon#enter wrdev, iclass 32, count 0 2006.201.13:26:57.23#ibcon#first serial, iclass 32, count 0 2006.201.13:26:57.23#ibcon#enter sib2, iclass 32, count 0 2006.201.13:26:57.23#ibcon#flushed, iclass 32, count 0 2006.201.13:26:57.23#ibcon#about to write, iclass 32, count 0 2006.201.13:26:57.23#ibcon#wrote, iclass 32, count 0 2006.201.13:26:57.23#ibcon#about to read 3, iclass 32, count 0 2006.201.13:26:57.25#ibcon#read 3, iclass 32, count 0 2006.201.13:26:57.25#ibcon#about to read 4, iclass 32, count 0 2006.201.13:26:57.25#ibcon#read 4, iclass 32, count 0 2006.201.13:26:57.25#ibcon#about to read 5, iclass 32, count 0 2006.201.13:26:57.25#ibcon#read 5, iclass 32, count 0 2006.201.13:26:57.25#ibcon#about to read 6, iclass 32, count 0 2006.201.13:26:57.25#ibcon#read 6, iclass 32, count 0 2006.201.13:26:57.25#ibcon#end of sib2, iclass 32, count 0 2006.201.13:26:57.25#ibcon#*mode == 0, iclass 32, count 0 2006.201.13:26:57.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.13:26:57.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:26:57.25#ibcon#*before write, iclass 32, count 0 2006.201.13:26:57.25#ibcon#enter sib2, iclass 32, count 0 2006.201.13:26:57.25#ibcon#flushed, iclass 32, count 0 2006.201.13:26:57.25#ibcon#about to write, iclass 32, count 0 2006.201.13:26:57.25#ibcon#wrote, iclass 32, count 0 2006.201.13:26:57.25#ibcon#about to read 3, iclass 32, count 0 2006.201.13:26:57.29#ibcon#read 3, iclass 32, count 0 2006.201.13:26:57.29#ibcon#about to read 4, iclass 32, count 0 2006.201.13:26:57.29#ibcon#read 4, iclass 32, count 0 2006.201.13:26:57.29#ibcon#about to read 5, iclass 32, count 0 2006.201.13:26:57.29#ibcon#read 5, iclass 32, count 0 2006.201.13:26:57.29#ibcon#about to read 6, iclass 32, count 0 2006.201.13:26:57.29#ibcon#read 6, iclass 32, count 0 2006.201.13:26:57.29#ibcon#end of sib2, iclass 32, count 0 2006.201.13:26:57.29#ibcon#*after write, iclass 32, count 0 2006.201.13:26:57.29#ibcon#*before return 0, iclass 32, count 0 2006.201.13:26:57.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:57.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:26:57.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.13:26:57.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.13:26:57.29$vck44/vb=3,4 2006.201.13:26:57.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.13:26:57.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.13:26:57.29#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:57.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:57.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:57.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:57.35#ibcon#enter wrdev, iclass 34, count 2 2006.201.13:26:57.35#ibcon#first serial, iclass 34, count 2 2006.201.13:26:57.35#ibcon#enter sib2, iclass 34, count 2 2006.201.13:26:57.35#ibcon#flushed, iclass 34, count 2 2006.201.13:26:57.35#ibcon#about to write, iclass 34, count 2 2006.201.13:26:57.35#ibcon#wrote, iclass 34, count 2 2006.201.13:26:57.35#ibcon#about to read 3, iclass 34, count 2 2006.201.13:26:57.37#ibcon#read 3, iclass 34, count 2 2006.201.13:26:57.37#ibcon#about to read 4, iclass 34, count 2 2006.201.13:26:57.37#ibcon#read 4, iclass 34, count 2 2006.201.13:26:57.37#ibcon#about to read 5, iclass 34, count 2 2006.201.13:26:57.37#ibcon#read 5, iclass 34, count 2 2006.201.13:26:57.37#ibcon#about to read 6, iclass 34, count 2 2006.201.13:26:57.37#ibcon#read 6, iclass 34, count 2 2006.201.13:26:57.37#ibcon#end of sib2, iclass 34, count 2 2006.201.13:26:57.37#ibcon#*mode == 0, iclass 34, count 2 2006.201.13:26:57.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.13:26:57.37#ibcon#[27=AT03-04\r\n] 2006.201.13:26:57.37#ibcon#*before write, iclass 34, count 2 2006.201.13:26:57.37#ibcon#enter sib2, iclass 34, count 2 2006.201.13:26:57.37#ibcon#flushed, iclass 34, count 2 2006.201.13:26:57.37#ibcon#about to write, iclass 34, count 2 2006.201.13:26:57.37#ibcon#wrote, iclass 34, count 2 2006.201.13:26:57.37#ibcon#about to read 3, iclass 34, count 2 2006.201.13:26:57.40#ibcon#read 3, iclass 34, count 2 2006.201.13:26:57.40#ibcon#about to read 4, iclass 34, count 2 2006.201.13:26:57.40#ibcon#read 4, iclass 34, count 2 2006.201.13:26:57.40#ibcon#about to read 5, iclass 34, count 2 2006.201.13:26:57.40#ibcon#read 5, iclass 34, count 2 2006.201.13:26:57.40#ibcon#about to read 6, iclass 34, count 2 2006.201.13:26:57.40#ibcon#read 6, iclass 34, count 2 2006.201.13:26:57.40#ibcon#end of sib2, iclass 34, count 2 2006.201.13:26:57.40#ibcon#*after write, iclass 34, count 2 2006.201.13:26:57.40#ibcon#*before return 0, iclass 34, count 2 2006.201.13:26:57.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:57.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:26:57.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.13:26:57.40#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:57.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:57.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:57.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:57.52#ibcon#enter wrdev, iclass 34, count 0 2006.201.13:26:57.52#ibcon#first serial, iclass 34, count 0 2006.201.13:26:57.52#ibcon#enter sib2, iclass 34, count 0 2006.201.13:26:57.52#ibcon#flushed, iclass 34, count 0 2006.201.13:26:57.52#ibcon#about to write, iclass 34, count 0 2006.201.13:26:57.52#ibcon#wrote, iclass 34, count 0 2006.201.13:26:57.52#ibcon#about to read 3, iclass 34, count 0 2006.201.13:26:57.54#ibcon#read 3, iclass 34, count 0 2006.201.13:26:57.54#ibcon#about to read 4, iclass 34, count 0 2006.201.13:26:57.54#ibcon#read 4, iclass 34, count 0 2006.201.13:26:57.54#ibcon#about to read 5, iclass 34, count 0 2006.201.13:26:57.54#ibcon#read 5, iclass 34, count 0 2006.201.13:26:57.54#ibcon#about to read 6, iclass 34, count 0 2006.201.13:26:57.54#ibcon#read 6, iclass 34, count 0 2006.201.13:26:57.54#ibcon#end of sib2, iclass 34, count 0 2006.201.13:26:57.54#ibcon#*mode == 0, iclass 34, count 0 2006.201.13:26:57.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.13:26:57.54#ibcon#[27=USB\r\n] 2006.201.13:26:57.54#ibcon#*before write, iclass 34, count 0 2006.201.13:26:57.54#ibcon#enter sib2, iclass 34, count 0 2006.201.13:26:57.54#ibcon#flushed, iclass 34, count 0 2006.201.13:26:57.54#ibcon#about to write, iclass 34, count 0 2006.201.13:26:57.54#ibcon#wrote, iclass 34, count 0 2006.201.13:26:57.54#ibcon#about to read 3, iclass 34, count 0 2006.201.13:26:57.57#ibcon#read 3, iclass 34, count 0 2006.201.13:26:57.57#ibcon#about to read 4, iclass 34, count 0 2006.201.13:26:57.57#ibcon#read 4, iclass 34, count 0 2006.201.13:26:57.57#ibcon#about to read 5, iclass 34, count 0 2006.201.13:26:57.57#ibcon#read 5, iclass 34, count 0 2006.201.13:26:57.57#ibcon#about to read 6, iclass 34, count 0 2006.201.13:26:57.57#ibcon#read 6, iclass 34, count 0 2006.201.13:26:57.57#ibcon#end of sib2, iclass 34, count 0 2006.201.13:26:57.57#ibcon#*after write, iclass 34, count 0 2006.201.13:26:57.57#ibcon#*before return 0, iclass 34, count 0 2006.201.13:26:57.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:57.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:26:57.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.13:26:57.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.13:26:57.57$vck44/vblo=4,679.99 2006.201.13:26:57.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.13:26:57.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.13:26:57.57#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:57.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:57.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:57.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:57.57#ibcon#enter wrdev, iclass 36, count 0 2006.201.13:26:57.57#ibcon#first serial, iclass 36, count 0 2006.201.13:26:57.57#ibcon#enter sib2, iclass 36, count 0 2006.201.13:26:57.57#ibcon#flushed, iclass 36, count 0 2006.201.13:26:57.57#ibcon#about to write, iclass 36, count 0 2006.201.13:26:57.57#ibcon#wrote, iclass 36, count 0 2006.201.13:26:57.57#ibcon#about to read 3, iclass 36, count 0 2006.201.13:26:57.59#ibcon#read 3, iclass 36, count 0 2006.201.13:26:57.59#ibcon#about to read 4, iclass 36, count 0 2006.201.13:26:57.59#ibcon#read 4, iclass 36, count 0 2006.201.13:26:57.59#ibcon#about to read 5, iclass 36, count 0 2006.201.13:26:57.59#ibcon#read 5, iclass 36, count 0 2006.201.13:26:57.59#ibcon#about to read 6, iclass 36, count 0 2006.201.13:26:57.59#ibcon#read 6, iclass 36, count 0 2006.201.13:26:57.59#ibcon#end of sib2, iclass 36, count 0 2006.201.13:26:57.59#ibcon#*mode == 0, iclass 36, count 0 2006.201.13:26:57.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.13:26:57.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:26:57.59#ibcon#*before write, iclass 36, count 0 2006.201.13:26:57.59#ibcon#enter sib2, iclass 36, count 0 2006.201.13:26:57.59#ibcon#flushed, iclass 36, count 0 2006.201.13:26:57.59#ibcon#about to write, iclass 36, count 0 2006.201.13:26:57.59#ibcon#wrote, iclass 36, count 0 2006.201.13:26:57.59#ibcon#about to read 3, iclass 36, count 0 2006.201.13:26:57.63#ibcon#read 3, iclass 36, count 0 2006.201.13:26:57.63#ibcon#about to read 4, iclass 36, count 0 2006.201.13:26:57.63#ibcon#read 4, iclass 36, count 0 2006.201.13:26:57.63#ibcon#about to read 5, iclass 36, count 0 2006.201.13:26:57.63#ibcon#read 5, iclass 36, count 0 2006.201.13:26:57.63#ibcon#about to read 6, iclass 36, count 0 2006.201.13:26:57.63#ibcon#read 6, iclass 36, count 0 2006.201.13:26:57.63#ibcon#end of sib2, iclass 36, count 0 2006.201.13:26:57.63#ibcon#*after write, iclass 36, count 0 2006.201.13:26:57.63#ibcon#*before return 0, iclass 36, count 0 2006.201.13:26:57.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:57.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:26:57.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.13:26:57.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.13:26:57.63$vck44/vb=4,5 2006.201.13:26:57.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.13:26:57.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.13:26:57.63#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:57.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:57.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:57.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:57.69#ibcon#enter wrdev, iclass 38, count 2 2006.201.13:26:57.69#ibcon#first serial, iclass 38, count 2 2006.201.13:26:57.69#ibcon#enter sib2, iclass 38, count 2 2006.201.13:26:57.69#ibcon#flushed, iclass 38, count 2 2006.201.13:26:57.69#ibcon#about to write, iclass 38, count 2 2006.201.13:26:57.69#ibcon#wrote, iclass 38, count 2 2006.201.13:26:57.69#ibcon#about to read 3, iclass 38, count 2 2006.201.13:26:57.71#ibcon#read 3, iclass 38, count 2 2006.201.13:26:57.71#ibcon#about to read 4, iclass 38, count 2 2006.201.13:26:57.71#ibcon#read 4, iclass 38, count 2 2006.201.13:26:57.71#ibcon#about to read 5, iclass 38, count 2 2006.201.13:26:57.71#ibcon#read 5, iclass 38, count 2 2006.201.13:26:57.71#ibcon#about to read 6, iclass 38, count 2 2006.201.13:26:57.71#ibcon#read 6, iclass 38, count 2 2006.201.13:26:57.71#ibcon#end of sib2, iclass 38, count 2 2006.201.13:26:57.71#ibcon#*mode == 0, iclass 38, count 2 2006.201.13:26:57.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.13:26:57.71#ibcon#[27=AT04-05\r\n] 2006.201.13:26:57.71#ibcon#*before write, iclass 38, count 2 2006.201.13:26:57.71#ibcon#enter sib2, iclass 38, count 2 2006.201.13:26:57.71#ibcon#flushed, iclass 38, count 2 2006.201.13:26:57.71#ibcon#about to write, iclass 38, count 2 2006.201.13:26:57.71#ibcon#wrote, iclass 38, count 2 2006.201.13:26:57.71#ibcon#about to read 3, iclass 38, count 2 2006.201.13:26:57.74#ibcon#read 3, iclass 38, count 2 2006.201.13:26:57.74#ibcon#about to read 4, iclass 38, count 2 2006.201.13:26:57.74#ibcon#read 4, iclass 38, count 2 2006.201.13:26:57.74#ibcon#about to read 5, iclass 38, count 2 2006.201.13:26:57.74#ibcon#read 5, iclass 38, count 2 2006.201.13:26:57.74#ibcon#about to read 6, iclass 38, count 2 2006.201.13:26:57.74#ibcon#read 6, iclass 38, count 2 2006.201.13:26:57.74#ibcon#end of sib2, iclass 38, count 2 2006.201.13:26:57.74#ibcon#*after write, iclass 38, count 2 2006.201.13:26:57.74#ibcon#*before return 0, iclass 38, count 2 2006.201.13:26:57.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:57.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:26:57.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.13:26:57.74#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:57.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:57.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:57.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:57.86#ibcon#enter wrdev, iclass 38, count 0 2006.201.13:26:57.86#ibcon#first serial, iclass 38, count 0 2006.201.13:26:57.86#ibcon#enter sib2, iclass 38, count 0 2006.201.13:26:57.86#ibcon#flushed, iclass 38, count 0 2006.201.13:26:57.86#ibcon#about to write, iclass 38, count 0 2006.201.13:26:57.86#ibcon#wrote, iclass 38, count 0 2006.201.13:26:57.86#ibcon#about to read 3, iclass 38, count 0 2006.201.13:26:57.88#ibcon#read 3, iclass 38, count 0 2006.201.13:26:57.88#ibcon#about to read 4, iclass 38, count 0 2006.201.13:26:57.88#ibcon#read 4, iclass 38, count 0 2006.201.13:26:57.88#ibcon#about to read 5, iclass 38, count 0 2006.201.13:26:57.88#ibcon#read 5, iclass 38, count 0 2006.201.13:26:57.88#ibcon#about to read 6, iclass 38, count 0 2006.201.13:26:57.88#ibcon#read 6, iclass 38, count 0 2006.201.13:26:57.88#ibcon#end of sib2, iclass 38, count 0 2006.201.13:26:57.88#ibcon#*mode == 0, iclass 38, count 0 2006.201.13:26:57.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.13:26:57.88#ibcon#[27=USB\r\n] 2006.201.13:26:57.88#ibcon#*before write, iclass 38, count 0 2006.201.13:26:57.88#ibcon#enter sib2, iclass 38, count 0 2006.201.13:26:57.88#ibcon#flushed, iclass 38, count 0 2006.201.13:26:57.88#ibcon#about to write, iclass 38, count 0 2006.201.13:26:57.88#ibcon#wrote, iclass 38, count 0 2006.201.13:26:57.88#ibcon#about to read 3, iclass 38, count 0 2006.201.13:26:57.91#ibcon#read 3, iclass 38, count 0 2006.201.13:26:57.91#ibcon#about to read 4, iclass 38, count 0 2006.201.13:26:57.91#ibcon#read 4, iclass 38, count 0 2006.201.13:26:57.91#ibcon#about to read 5, iclass 38, count 0 2006.201.13:26:57.91#ibcon#read 5, iclass 38, count 0 2006.201.13:26:57.91#ibcon#about to read 6, iclass 38, count 0 2006.201.13:26:57.91#ibcon#read 6, iclass 38, count 0 2006.201.13:26:57.91#ibcon#end of sib2, iclass 38, count 0 2006.201.13:26:57.91#ibcon#*after write, iclass 38, count 0 2006.201.13:26:57.91#ibcon#*before return 0, iclass 38, count 0 2006.201.13:26:57.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:57.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:26:57.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.13:26:57.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.13:26:57.91$vck44/vblo=5,709.99 2006.201.13:26:57.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.13:26:57.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.13:26:57.91#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:57.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:57.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:57.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:57.91#ibcon#enter wrdev, iclass 40, count 0 2006.201.13:26:57.91#ibcon#first serial, iclass 40, count 0 2006.201.13:26:57.91#ibcon#enter sib2, iclass 40, count 0 2006.201.13:26:57.91#ibcon#flushed, iclass 40, count 0 2006.201.13:26:57.91#ibcon#about to write, iclass 40, count 0 2006.201.13:26:57.91#ibcon#wrote, iclass 40, count 0 2006.201.13:26:57.91#ibcon#about to read 3, iclass 40, count 0 2006.201.13:26:57.93#ibcon#read 3, iclass 40, count 0 2006.201.13:26:57.93#ibcon#about to read 4, iclass 40, count 0 2006.201.13:26:57.93#ibcon#read 4, iclass 40, count 0 2006.201.13:26:57.93#ibcon#about to read 5, iclass 40, count 0 2006.201.13:26:57.93#ibcon#read 5, iclass 40, count 0 2006.201.13:26:57.93#ibcon#about to read 6, iclass 40, count 0 2006.201.13:26:57.93#ibcon#read 6, iclass 40, count 0 2006.201.13:26:57.93#ibcon#end of sib2, iclass 40, count 0 2006.201.13:26:57.93#ibcon#*mode == 0, iclass 40, count 0 2006.201.13:26:57.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.13:26:57.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:26:57.93#ibcon#*before write, iclass 40, count 0 2006.201.13:26:57.93#ibcon#enter sib2, iclass 40, count 0 2006.201.13:26:57.93#ibcon#flushed, iclass 40, count 0 2006.201.13:26:57.93#ibcon#about to write, iclass 40, count 0 2006.201.13:26:57.93#ibcon#wrote, iclass 40, count 0 2006.201.13:26:57.93#ibcon#about to read 3, iclass 40, count 0 2006.201.13:26:57.97#ibcon#read 3, iclass 40, count 0 2006.201.13:26:57.97#ibcon#about to read 4, iclass 40, count 0 2006.201.13:26:57.97#ibcon#read 4, iclass 40, count 0 2006.201.13:26:57.97#ibcon#about to read 5, iclass 40, count 0 2006.201.13:26:57.97#ibcon#read 5, iclass 40, count 0 2006.201.13:26:57.97#ibcon#about to read 6, iclass 40, count 0 2006.201.13:26:57.97#ibcon#read 6, iclass 40, count 0 2006.201.13:26:57.97#ibcon#end of sib2, iclass 40, count 0 2006.201.13:26:57.97#ibcon#*after write, iclass 40, count 0 2006.201.13:26:57.97#ibcon#*before return 0, iclass 40, count 0 2006.201.13:26:57.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:57.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:26:57.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.13:26:57.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.13:26:57.97$vck44/vb=5,4 2006.201.13:26:57.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.13:26:57.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.13:26:57.97#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:57.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:58.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:58.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:58.03#ibcon#enter wrdev, iclass 4, count 2 2006.201.13:26:58.03#ibcon#first serial, iclass 4, count 2 2006.201.13:26:58.03#ibcon#enter sib2, iclass 4, count 2 2006.201.13:26:58.03#ibcon#flushed, iclass 4, count 2 2006.201.13:26:58.03#ibcon#about to write, iclass 4, count 2 2006.201.13:26:58.03#ibcon#wrote, iclass 4, count 2 2006.201.13:26:58.03#ibcon#about to read 3, iclass 4, count 2 2006.201.13:26:58.05#ibcon#read 3, iclass 4, count 2 2006.201.13:26:58.05#ibcon#about to read 4, iclass 4, count 2 2006.201.13:26:58.05#ibcon#read 4, iclass 4, count 2 2006.201.13:26:58.05#ibcon#about to read 5, iclass 4, count 2 2006.201.13:26:58.05#ibcon#read 5, iclass 4, count 2 2006.201.13:26:58.05#ibcon#about to read 6, iclass 4, count 2 2006.201.13:26:58.05#ibcon#read 6, iclass 4, count 2 2006.201.13:26:58.05#ibcon#end of sib2, iclass 4, count 2 2006.201.13:26:58.05#ibcon#*mode == 0, iclass 4, count 2 2006.201.13:26:58.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.13:26:58.05#ibcon#[27=AT05-04\r\n] 2006.201.13:26:58.05#ibcon#*before write, iclass 4, count 2 2006.201.13:26:58.05#ibcon#enter sib2, iclass 4, count 2 2006.201.13:26:58.05#ibcon#flushed, iclass 4, count 2 2006.201.13:26:58.05#ibcon#about to write, iclass 4, count 2 2006.201.13:26:58.05#ibcon#wrote, iclass 4, count 2 2006.201.13:26:58.05#ibcon#about to read 3, iclass 4, count 2 2006.201.13:26:58.08#ibcon#read 3, iclass 4, count 2 2006.201.13:26:58.08#ibcon#about to read 4, iclass 4, count 2 2006.201.13:26:58.08#ibcon#read 4, iclass 4, count 2 2006.201.13:26:58.08#ibcon#about to read 5, iclass 4, count 2 2006.201.13:26:58.08#ibcon#read 5, iclass 4, count 2 2006.201.13:26:58.08#ibcon#about to read 6, iclass 4, count 2 2006.201.13:26:58.08#ibcon#read 6, iclass 4, count 2 2006.201.13:26:58.08#ibcon#end of sib2, iclass 4, count 2 2006.201.13:26:58.08#ibcon#*after write, iclass 4, count 2 2006.201.13:26:58.08#ibcon#*before return 0, iclass 4, count 2 2006.201.13:26:58.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:58.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:26:58.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.13:26:58.08#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:58.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:58.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:58.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:58.20#ibcon#enter wrdev, iclass 4, count 0 2006.201.13:26:58.20#ibcon#first serial, iclass 4, count 0 2006.201.13:26:58.20#ibcon#enter sib2, iclass 4, count 0 2006.201.13:26:58.20#ibcon#flushed, iclass 4, count 0 2006.201.13:26:58.20#ibcon#about to write, iclass 4, count 0 2006.201.13:26:58.20#ibcon#wrote, iclass 4, count 0 2006.201.13:26:58.20#ibcon#about to read 3, iclass 4, count 0 2006.201.13:26:58.22#ibcon#read 3, iclass 4, count 0 2006.201.13:26:58.22#ibcon#about to read 4, iclass 4, count 0 2006.201.13:26:58.22#ibcon#read 4, iclass 4, count 0 2006.201.13:26:58.22#ibcon#about to read 5, iclass 4, count 0 2006.201.13:26:58.22#ibcon#read 5, iclass 4, count 0 2006.201.13:26:58.22#ibcon#about to read 6, iclass 4, count 0 2006.201.13:26:58.22#ibcon#read 6, iclass 4, count 0 2006.201.13:26:58.22#ibcon#end of sib2, iclass 4, count 0 2006.201.13:26:58.22#ibcon#*mode == 0, iclass 4, count 0 2006.201.13:26:58.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.13:26:58.22#ibcon#[27=USB\r\n] 2006.201.13:26:58.22#ibcon#*before write, iclass 4, count 0 2006.201.13:26:58.22#ibcon#enter sib2, iclass 4, count 0 2006.201.13:26:58.22#ibcon#flushed, iclass 4, count 0 2006.201.13:26:58.22#ibcon#about to write, iclass 4, count 0 2006.201.13:26:58.22#ibcon#wrote, iclass 4, count 0 2006.201.13:26:58.22#ibcon#about to read 3, iclass 4, count 0 2006.201.13:26:58.25#ibcon#read 3, iclass 4, count 0 2006.201.13:26:58.25#ibcon#about to read 4, iclass 4, count 0 2006.201.13:26:58.25#ibcon#read 4, iclass 4, count 0 2006.201.13:26:58.25#ibcon#about to read 5, iclass 4, count 0 2006.201.13:26:58.25#ibcon#read 5, iclass 4, count 0 2006.201.13:26:58.25#ibcon#about to read 6, iclass 4, count 0 2006.201.13:26:58.25#ibcon#read 6, iclass 4, count 0 2006.201.13:26:58.25#ibcon#end of sib2, iclass 4, count 0 2006.201.13:26:58.25#ibcon#*after write, iclass 4, count 0 2006.201.13:26:58.25#ibcon#*before return 0, iclass 4, count 0 2006.201.13:26:58.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:58.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:26:58.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.13:26:58.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.13:26:58.25$vck44/vblo=6,719.99 2006.201.13:26:58.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.13:26:58.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.13:26:58.25#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:58.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:58.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:58.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:58.25#ibcon#enter wrdev, iclass 6, count 0 2006.201.13:26:58.25#ibcon#first serial, iclass 6, count 0 2006.201.13:26:58.25#ibcon#enter sib2, iclass 6, count 0 2006.201.13:26:58.25#ibcon#flushed, iclass 6, count 0 2006.201.13:26:58.25#ibcon#about to write, iclass 6, count 0 2006.201.13:26:58.25#ibcon#wrote, iclass 6, count 0 2006.201.13:26:58.25#ibcon#about to read 3, iclass 6, count 0 2006.201.13:26:58.27#ibcon#read 3, iclass 6, count 0 2006.201.13:26:58.27#ibcon#about to read 4, iclass 6, count 0 2006.201.13:26:58.27#ibcon#read 4, iclass 6, count 0 2006.201.13:26:58.27#ibcon#about to read 5, iclass 6, count 0 2006.201.13:26:58.27#ibcon#read 5, iclass 6, count 0 2006.201.13:26:58.27#ibcon#about to read 6, iclass 6, count 0 2006.201.13:26:58.27#ibcon#read 6, iclass 6, count 0 2006.201.13:26:58.27#ibcon#end of sib2, iclass 6, count 0 2006.201.13:26:58.27#ibcon#*mode == 0, iclass 6, count 0 2006.201.13:26:58.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.13:26:58.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:26:58.27#ibcon#*before write, iclass 6, count 0 2006.201.13:26:58.27#ibcon#enter sib2, iclass 6, count 0 2006.201.13:26:58.27#ibcon#flushed, iclass 6, count 0 2006.201.13:26:58.27#ibcon#about to write, iclass 6, count 0 2006.201.13:26:58.27#ibcon#wrote, iclass 6, count 0 2006.201.13:26:58.27#ibcon#about to read 3, iclass 6, count 0 2006.201.13:26:58.31#ibcon#read 3, iclass 6, count 0 2006.201.13:26:58.31#ibcon#about to read 4, iclass 6, count 0 2006.201.13:26:58.31#ibcon#read 4, iclass 6, count 0 2006.201.13:26:58.31#ibcon#about to read 5, iclass 6, count 0 2006.201.13:26:58.31#ibcon#read 5, iclass 6, count 0 2006.201.13:26:58.31#ibcon#about to read 6, iclass 6, count 0 2006.201.13:26:58.31#ibcon#read 6, iclass 6, count 0 2006.201.13:26:58.31#ibcon#end of sib2, iclass 6, count 0 2006.201.13:26:58.31#ibcon#*after write, iclass 6, count 0 2006.201.13:26:58.31#ibcon#*before return 0, iclass 6, count 0 2006.201.13:26:58.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:58.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:26:58.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.13:26:58.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.13:26:58.31$vck44/vb=6,4 2006.201.13:26:58.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.13:26:58.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.13:26:58.31#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:58.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:58.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:58.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:58.37#ibcon#enter wrdev, iclass 10, count 2 2006.201.13:26:58.37#ibcon#first serial, iclass 10, count 2 2006.201.13:26:58.37#ibcon#enter sib2, iclass 10, count 2 2006.201.13:26:58.37#ibcon#flushed, iclass 10, count 2 2006.201.13:26:58.37#ibcon#about to write, iclass 10, count 2 2006.201.13:26:58.37#ibcon#wrote, iclass 10, count 2 2006.201.13:26:58.37#ibcon#about to read 3, iclass 10, count 2 2006.201.13:26:58.39#ibcon#read 3, iclass 10, count 2 2006.201.13:26:58.39#ibcon#about to read 4, iclass 10, count 2 2006.201.13:26:58.39#ibcon#read 4, iclass 10, count 2 2006.201.13:26:58.39#ibcon#about to read 5, iclass 10, count 2 2006.201.13:26:58.39#ibcon#read 5, iclass 10, count 2 2006.201.13:26:58.39#ibcon#about to read 6, iclass 10, count 2 2006.201.13:26:58.39#ibcon#read 6, iclass 10, count 2 2006.201.13:26:58.39#ibcon#end of sib2, iclass 10, count 2 2006.201.13:26:58.39#ibcon#*mode == 0, iclass 10, count 2 2006.201.13:26:58.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.13:26:58.39#ibcon#[27=AT06-04\r\n] 2006.201.13:26:58.39#ibcon#*before write, iclass 10, count 2 2006.201.13:26:58.39#ibcon#enter sib2, iclass 10, count 2 2006.201.13:26:58.39#ibcon#flushed, iclass 10, count 2 2006.201.13:26:58.39#ibcon#about to write, iclass 10, count 2 2006.201.13:26:58.39#ibcon#wrote, iclass 10, count 2 2006.201.13:26:58.39#ibcon#about to read 3, iclass 10, count 2 2006.201.13:26:58.41#abcon#<5=/04 1.8 3.2 20.931001003.7\r\n> 2006.201.13:26:58.42#ibcon#read 3, iclass 10, count 2 2006.201.13:26:58.42#ibcon#about to read 4, iclass 10, count 2 2006.201.13:26:58.42#ibcon#read 4, iclass 10, count 2 2006.201.13:26:58.42#ibcon#about to read 5, iclass 10, count 2 2006.201.13:26:58.42#ibcon#read 5, iclass 10, count 2 2006.201.13:26:58.42#ibcon#about to read 6, iclass 10, count 2 2006.201.13:26:58.42#ibcon#read 6, iclass 10, count 2 2006.201.13:26:58.42#ibcon#end of sib2, iclass 10, count 2 2006.201.13:26:58.42#ibcon#*after write, iclass 10, count 2 2006.201.13:26:58.42#ibcon#*before return 0, iclass 10, count 2 2006.201.13:26:58.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:58.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:26:58.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.13:26:58.42#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:58.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:58.43#abcon#{5=INTERFACE CLEAR} 2006.201.13:26:58.49#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:26:58.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:58.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:58.54#ibcon#enter wrdev, iclass 10, count 0 2006.201.13:26:58.54#ibcon#first serial, iclass 10, count 0 2006.201.13:26:58.54#ibcon#enter sib2, iclass 10, count 0 2006.201.13:26:58.54#ibcon#flushed, iclass 10, count 0 2006.201.13:26:58.54#ibcon#about to write, iclass 10, count 0 2006.201.13:26:58.54#ibcon#wrote, iclass 10, count 0 2006.201.13:26:58.54#ibcon#about to read 3, iclass 10, count 0 2006.201.13:26:58.56#ibcon#read 3, iclass 10, count 0 2006.201.13:26:58.56#ibcon#about to read 4, iclass 10, count 0 2006.201.13:26:58.56#ibcon#read 4, iclass 10, count 0 2006.201.13:26:58.56#ibcon#about to read 5, iclass 10, count 0 2006.201.13:26:58.56#ibcon#read 5, iclass 10, count 0 2006.201.13:26:58.56#ibcon#about to read 6, iclass 10, count 0 2006.201.13:26:58.56#ibcon#read 6, iclass 10, count 0 2006.201.13:26:58.56#ibcon#end of sib2, iclass 10, count 0 2006.201.13:26:58.56#ibcon#*mode == 0, iclass 10, count 0 2006.201.13:26:58.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.13:26:58.56#ibcon#[27=USB\r\n] 2006.201.13:26:58.56#ibcon#*before write, iclass 10, count 0 2006.201.13:26:58.56#ibcon#enter sib2, iclass 10, count 0 2006.201.13:26:58.56#ibcon#flushed, iclass 10, count 0 2006.201.13:26:58.56#ibcon#about to write, iclass 10, count 0 2006.201.13:26:58.56#ibcon#wrote, iclass 10, count 0 2006.201.13:26:58.56#ibcon#about to read 3, iclass 10, count 0 2006.201.13:26:58.59#ibcon#read 3, iclass 10, count 0 2006.201.13:26:58.59#ibcon#about to read 4, iclass 10, count 0 2006.201.13:26:58.59#ibcon#read 4, iclass 10, count 0 2006.201.13:26:58.59#ibcon#about to read 5, iclass 10, count 0 2006.201.13:26:58.59#ibcon#read 5, iclass 10, count 0 2006.201.13:26:58.59#ibcon#about to read 6, iclass 10, count 0 2006.201.13:26:58.59#ibcon#read 6, iclass 10, count 0 2006.201.13:26:58.59#ibcon#end of sib2, iclass 10, count 0 2006.201.13:26:58.59#ibcon#*after write, iclass 10, count 0 2006.201.13:26:58.59#ibcon#*before return 0, iclass 10, count 0 2006.201.13:26:58.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:58.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:26:58.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.13:26:58.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.13:26:58.59$vck44/vblo=7,734.99 2006.201.13:26:58.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.13:26:58.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.13:26:58.59#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:58.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:58.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:58.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:58.59#ibcon#enter wrdev, iclass 16, count 0 2006.201.13:26:58.59#ibcon#first serial, iclass 16, count 0 2006.201.13:26:58.59#ibcon#enter sib2, iclass 16, count 0 2006.201.13:26:58.59#ibcon#flushed, iclass 16, count 0 2006.201.13:26:58.59#ibcon#about to write, iclass 16, count 0 2006.201.13:26:58.59#ibcon#wrote, iclass 16, count 0 2006.201.13:26:58.59#ibcon#about to read 3, iclass 16, count 0 2006.201.13:26:58.61#ibcon#read 3, iclass 16, count 0 2006.201.13:26:58.61#ibcon#about to read 4, iclass 16, count 0 2006.201.13:26:58.61#ibcon#read 4, iclass 16, count 0 2006.201.13:26:58.61#ibcon#about to read 5, iclass 16, count 0 2006.201.13:26:58.61#ibcon#read 5, iclass 16, count 0 2006.201.13:26:58.61#ibcon#about to read 6, iclass 16, count 0 2006.201.13:26:58.61#ibcon#read 6, iclass 16, count 0 2006.201.13:26:58.61#ibcon#end of sib2, iclass 16, count 0 2006.201.13:26:58.61#ibcon#*mode == 0, iclass 16, count 0 2006.201.13:26:58.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.13:26:58.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:26:58.61#ibcon#*before write, iclass 16, count 0 2006.201.13:26:58.61#ibcon#enter sib2, iclass 16, count 0 2006.201.13:26:58.61#ibcon#flushed, iclass 16, count 0 2006.201.13:26:58.61#ibcon#about to write, iclass 16, count 0 2006.201.13:26:58.61#ibcon#wrote, iclass 16, count 0 2006.201.13:26:58.61#ibcon#about to read 3, iclass 16, count 0 2006.201.13:26:58.65#ibcon#read 3, iclass 16, count 0 2006.201.13:26:58.65#ibcon#about to read 4, iclass 16, count 0 2006.201.13:26:58.65#ibcon#read 4, iclass 16, count 0 2006.201.13:26:58.65#ibcon#about to read 5, iclass 16, count 0 2006.201.13:26:58.65#ibcon#read 5, iclass 16, count 0 2006.201.13:26:58.65#ibcon#about to read 6, iclass 16, count 0 2006.201.13:26:58.65#ibcon#read 6, iclass 16, count 0 2006.201.13:26:58.65#ibcon#end of sib2, iclass 16, count 0 2006.201.13:26:58.65#ibcon#*after write, iclass 16, count 0 2006.201.13:26:58.65#ibcon#*before return 0, iclass 16, count 0 2006.201.13:26:58.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:58.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:26:58.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.13:26:58.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.13:26:58.65$vck44/vb=7,4 2006.201.13:26:58.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.13:26:58.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.13:26:58.65#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:58.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:58.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:58.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:58.71#ibcon#enter wrdev, iclass 18, count 2 2006.201.13:26:58.71#ibcon#first serial, iclass 18, count 2 2006.201.13:26:58.71#ibcon#enter sib2, iclass 18, count 2 2006.201.13:26:58.71#ibcon#flushed, iclass 18, count 2 2006.201.13:26:58.71#ibcon#about to write, iclass 18, count 2 2006.201.13:26:58.71#ibcon#wrote, iclass 18, count 2 2006.201.13:26:58.71#ibcon#about to read 3, iclass 18, count 2 2006.201.13:26:58.73#ibcon#read 3, iclass 18, count 2 2006.201.13:26:58.73#ibcon#about to read 4, iclass 18, count 2 2006.201.13:26:58.73#ibcon#read 4, iclass 18, count 2 2006.201.13:26:58.73#ibcon#about to read 5, iclass 18, count 2 2006.201.13:26:58.73#ibcon#read 5, iclass 18, count 2 2006.201.13:26:58.73#ibcon#about to read 6, iclass 18, count 2 2006.201.13:26:58.73#ibcon#read 6, iclass 18, count 2 2006.201.13:26:58.73#ibcon#end of sib2, iclass 18, count 2 2006.201.13:26:58.73#ibcon#*mode == 0, iclass 18, count 2 2006.201.13:26:58.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.13:26:58.73#ibcon#[27=AT07-04\r\n] 2006.201.13:26:58.73#ibcon#*before write, iclass 18, count 2 2006.201.13:26:58.73#ibcon#enter sib2, iclass 18, count 2 2006.201.13:26:58.73#ibcon#flushed, iclass 18, count 2 2006.201.13:26:58.73#ibcon#about to write, iclass 18, count 2 2006.201.13:26:58.73#ibcon#wrote, iclass 18, count 2 2006.201.13:26:58.73#ibcon#about to read 3, iclass 18, count 2 2006.201.13:26:58.76#ibcon#read 3, iclass 18, count 2 2006.201.13:26:58.76#ibcon#about to read 4, iclass 18, count 2 2006.201.13:26:58.76#ibcon#read 4, iclass 18, count 2 2006.201.13:26:58.76#ibcon#about to read 5, iclass 18, count 2 2006.201.13:26:58.76#ibcon#read 5, iclass 18, count 2 2006.201.13:26:58.76#ibcon#about to read 6, iclass 18, count 2 2006.201.13:26:58.76#ibcon#read 6, iclass 18, count 2 2006.201.13:26:58.76#ibcon#end of sib2, iclass 18, count 2 2006.201.13:26:58.76#ibcon#*after write, iclass 18, count 2 2006.201.13:26:58.76#ibcon#*before return 0, iclass 18, count 2 2006.201.13:26:58.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:58.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:26:58.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.13:26:58.76#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:58.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:58.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:58.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:58.88#ibcon#enter wrdev, iclass 18, count 0 2006.201.13:26:58.88#ibcon#first serial, iclass 18, count 0 2006.201.13:26:58.88#ibcon#enter sib2, iclass 18, count 0 2006.201.13:26:58.88#ibcon#flushed, iclass 18, count 0 2006.201.13:26:58.88#ibcon#about to write, iclass 18, count 0 2006.201.13:26:58.88#ibcon#wrote, iclass 18, count 0 2006.201.13:26:58.88#ibcon#about to read 3, iclass 18, count 0 2006.201.13:26:58.90#ibcon#read 3, iclass 18, count 0 2006.201.13:26:58.90#ibcon#about to read 4, iclass 18, count 0 2006.201.13:26:58.90#ibcon#read 4, iclass 18, count 0 2006.201.13:26:58.90#ibcon#about to read 5, iclass 18, count 0 2006.201.13:26:58.90#ibcon#read 5, iclass 18, count 0 2006.201.13:26:58.90#ibcon#about to read 6, iclass 18, count 0 2006.201.13:26:58.90#ibcon#read 6, iclass 18, count 0 2006.201.13:26:58.90#ibcon#end of sib2, iclass 18, count 0 2006.201.13:26:58.90#ibcon#*mode == 0, iclass 18, count 0 2006.201.13:26:58.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.13:26:58.90#ibcon#[27=USB\r\n] 2006.201.13:26:58.90#ibcon#*before write, iclass 18, count 0 2006.201.13:26:58.90#ibcon#enter sib2, iclass 18, count 0 2006.201.13:26:58.90#ibcon#flushed, iclass 18, count 0 2006.201.13:26:58.90#ibcon#about to write, iclass 18, count 0 2006.201.13:26:58.90#ibcon#wrote, iclass 18, count 0 2006.201.13:26:58.90#ibcon#about to read 3, iclass 18, count 0 2006.201.13:26:58.93#ibcon#read 3, iclass 18, count 0 2006.201.13:26:58.93#ibcon#about to read 4, iclass 18, count 0 2006.201.13:26:58.93#ibcon#read 4, iclass 18, count 0 2006.201.13:26:58.93#ibcon#about to read 5, iclass 18, count 0 2006.201.13:26:58.93#ibcon#read 5, iclass 18, count 0 2006.201.13:26:58.93#ibcon#about to read 6, iclass 18, count 0 2006.201.13:26:58.93#ibcon#read 6, iclass 18, count 0 2006.201.13:26:58.93#ibcon#end of sib2, iclass 18, count 0 2006.201.13:26:58.93#ibcon#*after write, iclass 18, count 0 2006.201.13:26:58.93#ibcon#*before return 0, iclass 18, count 0 2006.201.13:26:58.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:58.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:26:58.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.13:26:58.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.13:26:58.93$vck44/vblo=8,744.99 2006.201.13:26:58.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.13:26:58.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.13:26:58.93#ibcon#ireg 17 cls_cnt 0 2006.201.13:26:58.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:58.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:58.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:58.93#ibcon#enter wrdev, iclass 20, count 0 2006.201.13:26:58.93#ibcon#first serial, iclass 20, count 0 2006.201.13:26:58.93#ibcon#enter sib2, iclass 20, count 0 2006.201.13:26:58.93#ibcon#flushed, iclass 20, count 0 2006.201.13:26:58.93#ibcon#about to write, iclass 20, count 0 2006.201.13:26:58.93#ibcon#wrote, iclass 20, count 0 2006.201.13:26:58.93#ibcon#about to read 3, iclass 20, count 0 2006.201.13:26:58.95#ibcon#read 3, iclass 20, count 0 2006.201.13:26:58.95#ibcon#about to read 4, iclass 20, count 0 2006.201.13:26:58.95#ibcon#read 4, iclass 20, count 0 2006.201.13:26:58.95#ibcon#about to read 5, iclass 20, count 0 2006.201.13:26:58.95#ibcon#read 5, iclass 20, count 0 2006.201.13:26:58.95#ibcon#about to read 6, iclass 20, count 0 2006.201.13:26:58.95#ibcon#read 6, iclass 20, count 0 2006.201.13:26:58.95#ibcon#end of sib2, iclass 20, count 0 2006.201.13:26:58.95#ibcon#*mode == 0, iclass 20, count 0 2006.201.13:26:58.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.13:26:58.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:26:58.95#ibcon#*before write, iclass 20, count 0 2006.201.13:26:58.95#ibcon#enter sib2, iclass 20, count 0 2006.201.13:26:58.95#ibcon#flushed, iclass 20, count 0 2006.201.13:26:58.95#ibcon#about to write, iclass 20, count 0 2006.201.13:26:58.95#ibcon#wrote, iclass 20, count 0 2006.201.13:26:58.95#ibcon#about to read 3, iclass 20, count 0 2006.201.13:26:58.99#ibcon#read 3, iclass 20, count 0 2006.201.13:26:58.99#ibcon#about to read 4, iclass 20, count 0 2006.201.13:26:58.99#ibcon#read 4, iclass 20, count 0 2006.201.13:26:58.99#ibcon#about to read 5, iclass 20, count 0 2006.201.13:26:58.99#ibcon#read 5, iclass 20, count 0 2006.201.13:26:58.99#ibcon#about to read 6, iclass 20, count 0 2006.201.13:26:58.99#ibcon#read 6, iclass 20, count 0 2006.201.13:26:58.99#ibcon#end of sib2, iclass 20, count 0 2006.201.13:26:58.99#ibcon#*after write, iclass 20, count 0 2006.201.13:26:58.99#ibcon#*before return 0, iclass 20, count 0 2006.201.13:26:58.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:58.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:26:58.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.13:26:58.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.13:26:58.99$vck44/vb=8,4 2006.201.13:26:58.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.13:26:58.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.13:26:58.99#ibcon#ireg 11 cls_cnt 2 2006.201.13:26:58.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:59.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:59.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:59.05#ibcon#enter wrdev, iclass 22, count 2 2006.201.13:26:59.05#ibcon#first serial, iclass 22, count 2 2006.201.13:26:59.05#ibcon#enter sib2, iclass 22, count 2 2006.201.13:26:59.05#ibcon#flushed, iclass 22, count 2 2006.201.13:26:59.05#ibcon#about to write, iclass 22, count 2 2006.201.13:26:59.05#ibcon#wrote, iclass 22, count 2 2006.201.13:26:59.05#ibcon#about to read 3, iclass 22, count 2 2006.201.13:26:59.07#ibcon#read 3, iclass 22, count 2 2006.201.13:26:59.07#ibcon#about to read 4, iclass 22, count 2 2006.201.13:26:59.07#ibcon#read 4, iclass 22, count 2 2006.201.13:26:59.07#ibcon#about to read 5, iclass 22, count 2 2006.201.13:26:59.07#ibcon#read 5, iclass 22, count 2 2006.201.13:26:59.07#ibcon#about to read 6, iclass 22, count 2 2006.201.13:26:59.07#ibcon#read 6, iclass 22, count 2 2006.201.13:26:59.07#ibcon#end of sib2, iclass 22, count 2 2006.201.13:26:59.07#ibcon#*mode == 0, iclass 22, count 2 2006.201.13:26:59.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.13:26:59.07#ibcon#[27=AT08-04\r\n] 2006.201.13:26:59.07#ibcon#*before write, iclass 22, count 2 2006.201.13:26:59.07#ibcon#enter sib2, iclass 22, count 2 2006.201.13:26:59.07#ibcon#flushed, iclass 22, count 2 2006.201.13:26:59.07#ibcon#about to write, iclass 22, count 2 2006.201.13:26:59.07#ibcon#wrote, iclass 22, count 2 2006.201.13:26:59.07#ibcon#about to read 3, iclass 22, count 2 2006.201.13:26:59.10#ibcon#read 3, iclass 22, count 2 2006.201.13:26:59.10#ibcon#about to read 4, iclass 22, count 2 2006.201.13:26:59.10#ibcon#read 4, iclass 22, count 2 2006.201.13:26:59.10#ibcon#about to read 5, iclass 22, count 2 2006.201.13:26:59.10#ibcon#read 5, iclass 22, count 2 2006.201.13:26:59.10#ibcon#about to read 6, iclass 22, count 2 2006.201.13:26:59.10#ibcon#read 6, iclass 22, count 2 2006.201.13:26:59.10#ibcon#end of sib2, iclass 22, count 2 2006.201.13:26:59.10#ibcon#*after write, iclass 22, count 2 2006.201.13:26:59.10#ibcon#*before return 0, iclass 22, count 2 2006.201.13:26:59.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:59.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:26:59.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.13:26:59.10#ibcon#ireg 7 cls_cnt 0 2006.201.13:26:59.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:59.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:59.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:59.22#ibcon#enter wrdev, iclass 22, count 0 2006.201.13:26:59.22#ibcon#first serial, iclass 22, count 0 2006.201.13:26:59.22#ibcon#enter sib2, iclass 22, count 0 2006.201.13:26:59.22#ibcon#flushed, iclass 22, count 0 2006.201.13:26:59.22#ibcon#about to write, iclass 22, count 0 2006.201.13:26:59.22#ibcon#wrote, iclass 22, count 0 2006.201.13:26:59.22#ibcon#about to read 3, iclass 22, count 0 2006.201.13:26:59.24#ibcon#read 3, iclass 22, count 0 2006.201.13:26:59.24#ibcon#about to read 4, iclass 22, count 0 2006.201.13:26:59.24#ibcon#read 4, iclass 22, count 0 2006.201.13:26:59.24#ibcon#about to read 5, iclass 22, count 0 2006.201.13:26:59.24#ibcon#read 5, iclass 22, count 0 2006.201.13:26:59.24#ibcon#about to read 6, iclass 22, count 0 2006.201.13:26:59.24#ibcon#read 6, iclass 22, count 0 2006.201.13:26:59.24#ibcon#end of sib2, iclass 22, count 0 2006.201.13:26:59.24#ibcon#*mode == 0, iclass 22, count 0 2006.201.13:26:59.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.13:26:59.24#ibcon#[27=USB\r\n] 2006.201.13:26:59.24#ibcon#*before write, iclass 22, count 0 2006.201.13:26:59.24#ibcon#enter sib2, iclass 22, count 0 2006.201.13:26:59.24#ibcon#flushed, iclass 22, count 0 2006.201.13:26:59.24#ibcon#about to write, iclass 22, count 0 2006.201.13:26:59.24#ibcon#wrote, iclass 22, count 0 2006.201.13:26:59.24#ibcon#about to read 3, iclass 22, count 0 2006.201.13:26:59.27#ibcon#read 3, iclass 22, count 0 2006.201.13:26:59.27#ibcon#about to read 4, iclass 22, count 0 2006.201.13:26:59.27#ibcon#read 4, iclass 22, count 0 2006.201.13:26:59.27#ibcon#about to read 5, iclass 22, count 0 2006.201.13:26:59.27#ibcon#read 5, iclass 22, count 0 2006.201.13:26:59.27#ibcon#about to read 6, iclass 22, count 0 2006.201.13:26:59.27#ibcon#read 6, iclass 22, count 0 2006.201.13:26:59.27#ibcon#end of sib2, iclass 22, count 0 2006.201.13:26:59.27#ibcon#*after write, iclass 22, count 0 2006.201.13:26:59.27#ibcon#*before return 0, iclass 22, count 0 2006.201.13:26:59.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:59.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:26:59.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.13:26:59.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.13:26:59.27$vck44/vabw=wide 2006.201.13:26:59.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.13:26:59.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.13:26:59.27#ibcon#ireg 8 cls_cnt 0 2006.201.13:26:59.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:59.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:59.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:59.27#ibcon#enter wrdev, iclass 24, count 0 2006.201.13:26:59.27#ibcon#first serial, iclass 24, count 0 2006.201.13:26:59.27#ibcon#enter sib2, iclass 24, count 0 2006.201.13:26:59.27#ibcon#flushed, iclass 24, count 0 2006.201.13:26:59.27#ibcon#about to write, iclass 24, count 0 2006.201.13:26:59.27#ibcon#wrote, iclass 24, count 0 2006.201.13:26:59.27#ibcon#about to read 3, iclass 24, count 0 2006.201.13:26:59.29#ibcon#read 3, iclass 24, count 0 2006.201.13:26:59.29#ibcon#about to read 4, iclass 24, count 0 2006.201.13:26:59.29#ibcon#read 4, iclass 24, count 0 2006.201.13:26:59.29#ibcon#about to read 5, iclass 24, count 0 2006.201.13:26:59.29#ibcon#read 5, iclass 24, count 0 2006.201.13:26:59.29#ibcon#about to read 6, iclass 24, count 0 2006.201.13:26:59.29#ibcon#read 6, iclass 24, count 0 2006.201.13:26:59.29#ibcon#end of sib2, iclass 24, count 0 2006.201.13:26:59.29#ibcon#*mode == 0, iclass 24, count 0 2006.201.13:26:59.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.13:26:59.29#ibcon#[25=BW32\r\n] 2006.201.13:26:59.29#ibcon#*before write, iclass 24, count 0 2006.201.13:26:59.29#ibcon#enter sib2, iclass 24, count 0 2006.201.13:26:59.29#ibcon#flushed, iclass 24, count 0 2006.201.13:26:59.29#ibcon#about to write, iclass 24, count 0 2006.201.13:26:59.29#ibcon#wrote, iclass 24, count 0 2006.201.13:26:59.29#ibcon#about to read 3, iclass 24, count 0 2006.201.13:26:59.32#ibcon#read 3, iclass 24, count 0 2006.201.13:26:59.32#ibcon#about to read 4, iclass 24, count 0 2006.201.13:26:59.32#ibcon#read 4, iclass 24, count 0 2006.201.13:26:59.32#ibcon#about to read 5, iclass 24, count 0 2006.201.13:26:59.32#ibcon#read 5, iclass 24, count 0 2006.201.13:26:59.32#ibcon#about to read 6, iclass 24, count 0 2006.201.13:26:59.32#ibcon#read 6, iclass 24, count 0 2006.201.13:26:59.32#ibcon#end of sib2, iclass 24, count 0 2006.201.13:26:59.32#ibcon#*after write, iclass 24, count 0 2006.201.13:26:59.32#ibcon#*before return 0, iclass 24, count 0 2006.201.13:26:59.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:59.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:26:59.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.13:26:59.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.13:26:59.32$vck44/vbbw=wide 2006.201.13:26:59.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.13:26:59.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.13:26:59.32#ibcon#ireg 8 cls_cnt 0 2006.201.13:26:59.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:26:59.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:26:59.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:26:59.39#ibcon#enter wrdev, iclass 26, count 0 2006.201.13:26:59.39#ibcon#first serial, iclass 26, count 0 2006.201.13:26:59.39#ibcon#enter sib2, iclass 26, count 0 2006.201.13:26:59.39#ibcon#flushed, iclass 26, count 0 2006.201.13:26:59.39#ibcon#about to write, iclass 26, count 0 2006.201.13:26:59.39#ibcon#wrote, iclass 26, count 0 2006.201.13:26:59.39#ibcon#about to read 3, iclass 26, count 0 2006.201.13:26:59.41#ibcon#read 3, iclass 26, count 0 2006.201.13:26:59.41#ibcon#about to read 4, iclass 26, count 0 2006.201.13:26:59.41#ibcon#read 4, iclass 26, count 0 2006.201.13:26:59.41#ibcon#about to read 5, iclass 26, count 0 2006.201.13:26:59.41#ibcon#read 5, iclass 26, count 0 2006.201.13:26:59.41#ibcon#about to read 6, iclass 26, count 0 2006.201.13:26:59.41#ibcon#read 6, iclass 26, count 0 2006.201.13:26:59.41#ibcon#end of sib2, iclass 26, count 0 2006.201.13:26:59.41#ibcon#*mode == 0, iclass 26, count 0 2006.201.13:26:59.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.13:26:59.41#ibcon#[27=BW32\r\n] 2006.201.13:26:59.41#ibcon#*before write, iclass 26, count 0 2006.201.13:26:59.41#ibcon#enter sib2, iclass 26, count 0 2006.201.13:26:59.41#ibcon#flushed, iclass 26, count 0 2006.201.13:26:59.41#ibcon#about to write, iclass 26, count 0 2006.201.13:26:59.41#ibcon#wrote, iclass 26, count 0 2006.201.13:26:59.41#ibcon#about to read 3, iclass 26, count 0 2006.201.13:26:59.44#ibcon#read 3, iclass 26, count 0 2006.201.13:26:59.44#ibcon#about to read 4, iclass 26, count 0 2006.201.13:26:59.44#ibcon#read 4, iclass 26, count 0 2006.201.13:26:59.44#ibcon#about to read 5, iclass 26, count 0 2006.201.13:26:59.44#ibcon#read 5, iclass 26, count 0 2006.201.13:26:59.44#ibcon#about to read 6, iclass 26, count 0 2006.201.13:26:59.44#ibcon#read 6, iclass 26, count 0 2006.201.13:26:59.44#ibcon#end of sib2, iclass 26, count 0 2006.201.13:26:59.44#ibcon#*after write, iclass 26, count 0 2006.201.13:26:59.44#ibcon#*before return 0, iclass 26, count 0 2006.201.13:26:59.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:26:59.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:26:59.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.13:26:59.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.13:26:59.44$setupk4/ifdk4 2006.201.13:26:59.44$ifdk4/lo= 2006.201.13:26:59.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:26:59.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:26:59.44$ifdk4/patch= 2006.201.13:26:59.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:26:59.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:26:59.44$setupk4/!*+20s 2006.201.13:27:08.58#abcon#<5=/04 1.8 3.2 20.931001003.7\r\n> 2006.201.13:27:08.60#abcon#{5=INTERFACE CLEAR} 2006.201.13:27:08.66#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:27:13.93$setupk4/"tpicd 2006.201.13:27:13.93$setupk4/echo=off 2006.201.13:27:13.93$setupk4/xlog=off 2006.201.13:27:13.93:!2006.201.13:37:19 2006.201.13:27:47.14#trakl#Source acquired 2006.201.13:27:49.14#flagr#flagr/antenna,acquired 2006.201.13:37:19.00:preob 2006.201.13:37:20.14/onsource/TRACKING 2006.201.13:37:20.14:!2006.201.13:37:29 2006.201.13:37:29.00:"tape 2006.201.13:37:29.00:"st=record 2006.201.13:37:29.00:data_valid=on 2006.201.13:37:29.00:midob 2006.201.13:37:29.14/onsource/TRACKING 2006.201.13:37:29.14/wx/20.90,1003.8,100 2006.201.13:37:29.29/cable/+6.4745E-03 2006.201.13:37:30.38/va/01,08,usb,yes,29,31 2006.201.13:37:30.38/va/02,07,usb,yes,31,32 2006.201.13:37:30.38/va/03,08,usb,yes,28,29 2006.201.13:37:30.38/va/04,07,usb,yes,32,34 2006.201.13:37:30.38/va/05,04,usb,yes,28,29 2006.201.13:37:30.38/va/06,05,usb,yes,28,28 2006.201.13:37:30.38/va/07,05,usb,yes,27,29 2006.201.13:37:30.38/va/08,04,usb,yes,27,33 2006.201.13:37:30.61/valo/01,524.99,yes,locked 2006.201.13:37:30.61/valo/02,534.99,yes,locked 2006.201.13:37:30.61/valo/03,564.99,yes,locked 2006.201.13:37:30.61/valo/04,624.99,yes,locked 2006.201.13:37:30.61/valo/05,734.99,yes,locked 2006.201.13:37:30.61/valo/06,814.99,yes,locked 2006.201.13:37:30.61/valo/07,864.99,yes,locked 2006.201.13:37:30.61/valo/08,884.99,yes,locked 2006.201.13:37:31.70/vb/01,04,usb,yes,29,27 2006.201.13:37:31.70/vb/02,05,usb,yes,27,27 2006.201.13:37:31.70/vb/03,04,usb,yes,28,31 2006.201.13:37:31.70/vb/04,05,usb,yes,28,27 2006.201.13:37:31.70/vb/05,04,usb,yes,25,27 2006.201.13:37:31.70/vb/06,04,usb,yes,29,25 2006.201.13:37:31.70/vb/07,04,usb,yes,29,29 2006.201.13:37:31.70/vb/08,04,usb,yes,27,30 2006.201.13:37:31.94/vblo/01,629.99,yes,locked 2006.201.13:37:31.94/vblo/02,634.99,yes,locked 2006.201.13:37:31.94/vblo/03,649.99,yes,locked 2006.201.13:37:31.94/vblo/04,679.99,yes,locked 2006.201.13:37:31.94/vblo/05,709.99,yes,locked 2006.201.13:37:31.94/vblo/06,719.99,yes,locked 2006.201.13:37:31.94/vblo/07,734.99,yes,locked 2006.201.13:37:31.94/vblo/08,744.99,yes,locked 2006.201.13:37:32.09/vabw/8 2006.201.13:37:32.24/vbbw/8 2006.201.13:37:32.33/xfe/off,on,15.2 2006.201.13:37:32.72/ifatt/23,28,28,28 2006.201.13:37:33.06/fmout-gps/S +4.55E-07 2006.201.13:37:33.13:!2006.201.13:38:39 2006.201.13:38:39.00:data_valid=off 2006.201.13:38:39.00:"et 2006.201.13:38:39.00:!+3s 2006.201.13:38:42.02:"tape 2006.201.13:38:42.02:postob 2006.201.13:38:42.16/cable/+6.4722E-03 2006.201.13:38:42.16/wx/20.90,1003.8,100 2006.201.13:38:42.22/fmout-gps/S +4.55E-07 2006.201.13:38:42.22:scan_name=201-1341,jd0607,190 2006.201.13:38:42.22:source=3c446,222547.26,-045701.4,2000.0,cw 2006.201.13:38:44.13#flagr#flagr/antenna,new-source 2006.201.13:38:44.13:checkk5 2006.201.13:38:44.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:38:44.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:38:45.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:38:45.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:38:46.00/chk_obsdata//k5ts1/T2011337??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.13:38:46.36/chk_obsdata//k5ts2/T2011337??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.13:38:46.73/chk_obsdata//k5ts3/T2011337??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.13:38:47.10/chk_obsdata//k5ts4/T2011337??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.13:38:47.78/k5log//k5ts1_log_newline 2006.201.13:38:48.46/k5log//k5ts2_log_newline 2006.201.13:38:49.15/k5log//k5ts3_log_newline 2006.201.13:38:49.84/k5log//k5ts4_log_newline 2006.201.13:38:49.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:38:49.86:setupk4=1 2006.201.13:38:49.86$setupk4/echo=on 2006.201.13:38:49.86$setupk4/pcalon 2006.201.13:38:49.86$pcalon/"no phase cal control is implemented here 2006.201.13:38:49.86$setupk4/"tpicd=stop 2006.201.13:38:49.86$setupk4/"rec=synch_on 2006.201.13:38:49.86$setupk4/"rec_mode=128 2006.201.13:38:49.86$setupk4/!* 2006.201.13:38:49.86$setupk4/recpk4 2006.201.13:38:49.86$recpk4/recpatch= 2006.201.13:38:49.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:38:49.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:38:49.87$setupk4/vck44 2006.201.13:38:49.87$vck44/valo=1,524.99 2006.201.13:38:49.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.13:38:49.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.13:38:49.87#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:49.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:49.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:49.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:49.87#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:38:49.87#ibcon#first serial, iclass 19, count 0 2006.201.13:38:49.87#ibcon#enter sib2, iclass 19, count 0 2006.201.13:38:49.87#ibcon#flushed, iclass 19, count 0 2006.201.13:38:49.87#ibcon#about to write, iclass 19, count 0 2006.201.13:38:49.87#ibcon#wrote, iclass 19, count 0 2006.201.13:38:49.87#ibcon#about to read 3, iclass 19, count 0 2006.201.13:38:49.90#ibcon#read 3, iclass 19, count 0 2006.201.13:38:49.90#ibcon#about to read 4, iclass 19, count 0 2006.201.13:38:49.90#ibcon#read 4, iclass 19, count 0 2006.201.13:38:49.90#ibcon#about to read 5, iclass 19, count 0 2006.201.13:38:49.90#ibcon#read 5, iclass 19, count 0 2006.201.13:38:49.90#ibcon#about to read 6, iclass 19, count 0 2006.201.13:38:49.90#ibcon#read 6, iclass 19, count 0 2006.201.13:38:49.90#ibcon#end of sib2, iclass 19, count 0 2006.201.13:38:49.90#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:38:49.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:38:49.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:38:49.90#ibcon#*before write, iclass 19, count 0 2006.201.13:38:49.90#ibcon#enter sib2, iclass 19, count 0 2006.201.13:38:49.90#ibcon#flushed, iclass 19, count 0 2006.201.13:38:49.90#ibcon#about to write, iclass 19, count 0 2006.201.13:38:49.90#ibcon#wrote, iclass 19, count 0 2006.201.13:38:49.90#ibcon#about to read 3, iclass 19, count 0 2006.201.13:38:49.96#ibcon#read 3, iclass 19, count 0 2006.201.13:38:49.96#ibcon#about to read 4, iclass 19, count 0 2006.201.13:38:49.96#ibcon#read 4, iclass 19, count 0 2006.201.13:38:49.96#ibcon#about to read 5, iclass 19, count 0 2006.201.13:38:49.96#ibcon#read 5, iclass 19, count 0 2006.201.13:38:49.96#ibcon#about to read 6, iclass 19, count 0 2006.201.13:38:49.96#ibcon#read 6, iclass 19, count 0 2006.201.13:38:49.96#ibcon#end of sib2, iclass 19, count 0 2006.201.13:38:49.96#ibcon#*after write, iclass 19, count 0 2006.201.13:38:49.96#ibcon#*before return 0, iclass 19, count 0 2006.201.13:38:49.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:49.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:49.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:38:49.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:38:49.96$vck44/va=1,8 2006.201.13:38:49.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.13:38:49.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.13:38:49.96#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:49.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:49.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:49.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:49.96#ibcon#enter wrdev, iclass 21, count 2 2006.201.13:38:49.96#ibcon#first serial, iclass 21, count 2 2006.201.13:38:49.96#ibcon#enter sib2, iclass 21, count 2 2006.201.13:38:49.96#ibcon#flushed, iclass 21, count 2 2006.201.13:38:49.96#ibcon#about to write, iclass 21, count 2 2006.201.13:38:49.96#ibcon#wrote, iclass 21, count 2 2006.201.13:38:49.96#ibcon#about to read 3, iclass 21, count 2 2006.201.13:38:49.98#ibcon#read 3, iclass 21, count 2 2006.201.13:38:49.98#ibcon#about to read 4, iclass 21, count 2 2006.201.13:38:49.98#ibcon#read 4, iclass 21, count 2 2006.201.13:38:49.98#ibcon#about to read 5, iclass 21, count 2 2006.201.13:38:49.98#ibcon#read 5, iclass 21, count 2 2006.201.13:38:49.98#ibcon#about to read 6, iclass 21, count 2 2006.201.13:38:49.98#ibcon#read 6, iclass 21, count 2 2006.201.13:38:49.98#ibcon#end of sib2, iclass 21, count 2 2006.201.13:38:49.98#ibcon#*mode == 0, iclass 21, count 2 2006.201.13:38:49.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.13:38:49.98#ibcon#[25=AT01-08\r\n] 2006.201.13:38:49.98#ibcon#*before write, iclass 21, count 2 2006.201.13:38:49.98#ibcon#enter sib2, iclass 21, count 2 2006.201.13:38:49.98#ibcon#flushed, iclass 21, count 2 2006.201.13:38:49.98#ibcon#about to write, iclass 21, count 2 2006.201.13:38:49.98#ibcon#wrote, iclass 21, count 2 2006.201.13:38:49.98#ibcon#about to read 3, iclass 21, count 2 2006.201.13:38:50.02#ibcon#read 3, iclass 21, count 2 2006.201.13:38:50.02#ibcon#about to read 4, iclass 21, count 2 2006.201.13:38:50.02#ibcon#read 4, iclass 21, count 2 2006.201.13:38:50.02#ibcon#about to read 5, iclass 21, count 2 2006.201.13:38:50.02#ibcon#read 5, iclass 21, count 2 2006.201.13:38:50.02#ibcon#about to read 6, iclass 21, count 2 2006.201.13:38:50.02#ibcon#read 6, iclass 21, count 2 2006.201.13:38:50.02#ibcon#end of sib2, iclass 21, count 2 2006.201.13:38:50.02#ibcon#*after write, iclass 21, count 2 2006.201.13:38:50.02#ibcon#*before return 0, iclass 21, count 2 2006.201.13:38:50.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:50.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:50.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.13:38:50.02#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:50.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:50.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:50.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:50.14#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:38:50.14#ibcon#first serial, iclass 21, count 0 2006.201.13:38:50.14#ibcon#enter sib2, iclass 21, count 0 2006.201.13:38:50.14#ibcon#flushed, iclass 21, count 0 2006.201.13:38:50.14#ibcon#about to write, iclass 21, count 0 2006.201.13:38:50.14#ibcon#wrote, iclass 21, count 0 2006.201.13:38:50.14#ibcon#about to read 3, iclass 21, count 0 2006.201.13:38:50.16#ibcon#read 3, iclass 21, count 0 2006.201.13:38:50.16#ibcon#about to read 4, iclass 21, count 0 2006.201.13:38:50.16#ibcon#read 4, iclass 21, count 0 2006.201.13:38:50.16#ibcon#about to read 5, iclass 21, count 0 2006.201.13:38:50.16#ibcon#read 5, iclass 21, count 0 2006.201.13:38:50.16#ibcon#about to read 6, iclass 21, count 0 2006.201.13:38:50.16#ibcon#read 6, iclass 21, count 0 2006.201.13:38:50.16#ibcon#end of sib2, iclass 21, count 0 2006.201.13:38:50.16#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:38:50.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:38:50.16#ibcon#[25=USB\r\n] 2006.201.13:38:50.16#ibcon#*before write, iclass 21, count 0 2006.201.13:38:50.16#ibcon#enter sib2, iclass 21, count 0 2006.201.13:38:50.16#ibcon#flushed, iclass 21, count 0 2006.201.13:38:50.16#ibcon#about to write, iclass 21, count 0 2006.201.13:38:50.16#ibcon#wrote, iclass 21, count 0 2006.201.13:38:50.16#ibcon#about to read 3, iclass 21, count 0 2006.201.13:38:50.19#ibcon#read 3, iclass 21, count 0 2006.201.13:38:50.19#ibcon#about to read 4, iclass 21, count 0 2006.201.13:38:50.19#ibcon#read 4, iclass 21, count 0 2006.201.13:38:50.19#ibcon#about to read 5, iclass 21, count 0 2006.201.13:38:50.19#ibcon#read 5, iclass 21, count 0 2006.201.13:38:50.19#ibcon#about to read 6, iclass 21, count 0 2006.201.13:38:50.19#ibcon#read 6, iclass 21, count 0 2006.201.13:38:50.19#ibcon#end of sib2, iclass 21, count 0 2006.201.13:38:50.19#ibcon#*after write, iclass 21, count 0 2006.201.13:38:50.19#ibcon#*before return 0, iclass 21, count 0 2006.201.13:38:50.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:50.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:50.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:38:50.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:38:50.19$vck44/valo=2,534.99 2006.201.13:38:50.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.13:38:50.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.13:38:50.19#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:50.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:50.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:50.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:50.19#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:38:50.19#ibcon#first serial, iclass 23, count 0 2006.201.13:38:50.19#ibcon#enter sib2, iclass 23, count 0 2006.201.13:38:50.19#ibcon#flushed, iclass 23, count 0 2006.201.13:38:50.19#ibcon#about to write, iclass 23, count 0 2006.201.13:38:50.19#ibcon#wrote, iclass 23, count 0 2006.201.13:38:50.19#ibcon#about to read 3, iclass 23, count 0 2006.201.13:38:50.21#ibcon#read 3, iclass 23, count 0 2006.201.13:38:50.21#ibcon#about to read 4, iclass 23, count 0 2006.201.13:38:50.21#ibcon#read 4, iclass 23, count 0 2006.201.13:38:50.21#ibcon#about to read 5, iclass 23, count 0 2006.201.13:38:50.21#ibcon#read 5, iclass 23, count 0 2006.201.13:38:50.21#ibcon#about to read 6, iclass 23, count 0 2006.201.13:38:50.21#ibcon#read 6, iclass 23, count 0 2006.201.13:38:50.21#ibcon#end of sib2, iclass 23, count 0 2006.201.13:38:50.21#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:38:50.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:38:50.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:38:50.21#ibcon#*before write, iclass 23, count 0 2006.201.13:38:50.21#ibcon#enter sib2, iclass 23, count 0 2006.201.13:38:50.21#ibcon#flushed, iclass 23, count 0 2006.201.13:38:50.21#ibcon#about to write, iclass 23, count 0 2006.201.13:38:50.21#ibcon#wrote, iclass 23, count 0 2006.201.13:38:50.21#ibcon#about to read 3, iclass 23, count 0 2006.201.13:38:50.25#ibcon#read 3, iclass 23, count 0 2006.201.13:38:50.25#ibcon#about to read 4, iclass 23, count 0 2006.201.13:38:50.25#ibcon#read 4, iclass 23, count 0 2006.201.13:38:50.25#ibcon#about to read 5, iclass 23, count 0 2006.201.13:38:50.25#ibcon#read 5, iclass 23, count 0 2006.201.13:38:50.25#ibcon#about to read 6, iclass 23, count 0 2006.201.13:38:50.25#ibcon#read 6, iclass 23, count 0 2006.201.13:38:50.25#ibcon#end of sib2, iclass 23, count 0 2006.201.13:38:50.25#ibcon#*after write, iclass 23, count 0 2006.201.13:38:50.25#ibcon#*before return 0, iclass 23, count 0 2006.201.13:38:50.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:50.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:50.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:38:50.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:38:50.25$vck44/va=2,7 2006.201.13:38:50.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.13:38:50.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.13:38:50.25#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:50.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:50.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:50.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:50.31#ibcon#enter wrdev, iclass 25, count 2 2006.201.13:38:50.31#ibcon#first serial, iclass 25, count 2 2006.201.13:38:50.31#ibcon#enter sib2, iclass 25, count 2 2006.201.13:38:50.31#ibcon#flushed, iclass 25, count 2 2006.201.13:38:50.31#ibcon#about to write, iclass 25, count 2 2006.201.13:38:50.31#ibcon#wrote, iclass 25, count 2 2006.201.13:38:50.31#ibcon#about to read 3, iclass 25, count 2 2006.201.13:38:50.33#ibcon#read 3, iclass 25, count 2 2006.201.13:38:50.33#ibcon#about to read 4, iclass 25, count 2 2006.201.13:38:50.33#ibcon#read 4, iclass 25, count 2 2006.201.13:38:50.33#ibcon#about to read 5, iclass 25, count 2 2006.201.13:38:50.33#ibcon#read 5, iclass 25, count 2 2006.201.13:38:50.33#ibcon#about to read 6, iclass 25, count 2 2006.201.13:38:50.33#ibcon#read 6, iclass 25, count 2 2006.201.13:38:50.33#ibcon#end of sib2, iclass 25, count 2 2006.201.13:38:50.33#ibcon#*mode == 0, iclass 25, count 2 2006.201.13:38:50.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.13:38:50.33#ibcon#[25=AT02-07\r\n] 2006.201.13:38:50.33#ibcon#*before write, iclass 25, count 2 2006.201.13:38:50.33#ibcon#enter sib2, iclass 25, count 2 2006.201.13:38:50.33#ibcon#flushed, iclass 25, count 2 2006.201.13:38:50.33#ibcon#about to write, iclass 25, count 2 2006.201.13:38:50.33#ibcon#wrote, iclass 25, count 2 2006.201.13:38:50.33#ibcon#about to read 3, iclass 25, count 2 2006.201.13:38:50.36#ibcon#read 3, iclass 25, count 2 2006.201.13:38:50.36#ibcon#about to read 4, iclass 25, count 2 2006.201.13:38:50.36#ibcon#read 4, iclass 25, count 2 2006.201.13:38:50.36#ibcon#about to read 5, iclass 25, count 2 2006.201.13:38:50.36#ibcon#read 5, iclass 25, count 2 2006.201.13:38:50.36#ibcon#about to read 6, iclass 25, count 2 2006.201.13:38:50.36#ibcon#read 6, iclass 25, count 2 2006.201.13:38:50.36#ibcon#end of sib2, iclass 25, count 2 2006.201.13:38:50.36#ibcon#*after write, iclass 25, count 2 2006.201.13:38:50.36#ibcon#*before return 0, iclass 25, count 2 2006.201.13:38:50.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:50.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:50.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.13:38:50.36#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:50.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:50.46#abcon#<5=/04 1.4 2.8 20.901001003.8\r\n> 2006.201.13:38:50.48#abcon#{5=INTERFACE CLEAR} 2006.201.13:38:50.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:50.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:50.48#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:38:50.48#ibcon#first serial, iclass 25, count 0 2006.201.13:38:50.48#ibcon#enter sib2, iclass 25, count 0 2006.201.13:38:50.48#ibcon#flushed, iclass 25, count 0 2006.201.13:38:50.48#ibcon#about to write, iclass 25, count 0 2006.201.13:38:50.48#ibcon#wrote, iclass 25, count 0 2006.201.13:38:50.48#ibcon#about to read 3, iclass 25, count 0 2006.201.13:38:50.50#ibcon#read 3, iclass 25, count 0 2006.201.13:38:50.50#ibcon#about to read 4, iclass 25, count 0 2006.201.13:38:50.50#ibcon#read 4, iclass 25, count 0 2006.201.13:38:50.50#ibcon#about to read 5, iclass 25, count 0 2006.201.13:38:50.50#ibcon#read 5, iclass 25, count 0 2006.201.13:38:50.50#ibcon#about to read 6, iclass 25, count 0 2006.201.13:38:50.50#ibcon#read 6, iclass 25, count 0 2006.201.13:38:50.50#ibcon#end of sib2, iclass 25, count 0 2006.201.13:38:50.50#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:38:50.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:38:50.50#ibcon#[25=USB\r\n] 2006.201.13:38:50.50#ibcon#*before write, iclass 25, count 0 2006.201.13:38:50.50#ibcon#enter sib2, iclass 25, count 0 2006.201.13:38:50.50#ibcon#flushed, iclass 25, count 0 2006.201.13:38:50.50#ibcon#about to write, iclass 25, count 0 2006.201.13:38:50.50#ibcon#wrote, iclass 25, count 0 2006.201.13:38:50.50#ibcon#about to read 3, iclass 25, count 0 2006.201.13:38:50.53#ibcon#read 3, iclass 25, count 0 2006.201.13:38:50.53#ibcon#about to read 4, iclass 25, count 0 2006.201.13:38:50.53#ibcon#read 4, iclass 25, count 0 2006.201.13:38:50.53#ibcon#about to read 5, iclass 25, count 0 2006.201.13:38:50.53#ibcon#read 5, iclass 25, count 0 2006.201.13:38:50.53#ibcon#about to read 6, iclass 25, count 0 2006.201.13:38:50.53#ibcon#read 6, iclass 25, count 0 2006.201.13:38:50.53#ibcon#end of sib2, iclass 25, count 0 2006.201.13:38:50.53#ibcon#*after write, iclass 25, count 0 2006.201.13:38:50.53#ibcon#*before return 0, iclass 25, count 0 2006.201.13:38:50.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:50.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:50.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:38:50.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:38:50.53$vck44/valo=3,564.99 2006.201.13:38:50.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.13:38:50.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.13:38:50.53#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:50.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:50.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:50.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:50.53#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:38:50.53#ibcon#first serial, iclass 31, count 0 2006.201.13:38:50.53#ibcon#enter sib2, iclass 31, count 0 2006.201.13:38:50.53#ibcon#flushed, iclass 31, count 0 2006.201.13:38:50.53#ibcon#about to write, iclass 31, count 0 2006.201.13:38:50.53#ibcon#wrote, iclass 31, count 0 2006.201.13:38:50.53#ibcon#about to read 3, iclass 31, count 0 2006.201.13:38:50.54#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:38:50.55#ibcon#read 3, iclass 31, count 0 2006.201.13:38:50.55#ibcon#about to read 4, iclass 31, count 0 2006.201.13:38:50.55#ibcon#read 4, iclass 31, count 0 2006.201.13:38:50.55#ibcon#about to read 5, iclass 31, count 0 2006.201.13:38:50.55#ibcon#read 5, iclass 31, count 0 2006.201.13:38:50.55#ibcon#about to read 6, iclass 31, count 0 2006.201.13:38:50.55#ibcon#read 6, iclass 31, count 0 2006.201.13:38:50.55#ibcon#end of sib2, iclass 31, count 0 2006.201.13:38:50.55#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:38:50.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:38:50.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:38:50.55#ibcon#*before write, iclass 31, count 0 2006.201.13:38:50.55#ibcon#enter sib2, iclass 31, count 0 2006.201.13:38:50.55#ibcon#flushed, iclass 31, count 0 2006.201.13:38:50.55#ibcon#about to write, iclass 31, count 0 2006.201.13:38:50.55#ibcon#wrote, iclass 31, count 0 2006.201.13:38:50.55#ibcon#about to read 3, iclass 31, count 0 2006.201.13:38:50.60#ibcon#read 3, iclass 31, count 0 2006.201.13:38:50.60#ibcon#about to read 4, iclass 31, count 0 2006.201.13:38:50.60#ibcon#read 4, iclass 31, count 0 2006.201.13:38:50.60#ibcon#about to read 5, iclass 31, count 0 2006.201.13:38:50.60#ibcon#read 5, iclass 31, count 0 2006.201.13:38:50.60#ibcon#about to read 6, iclass 31, count 0 2006.201.13:38:50.60#ibcon#read 6, iclass 31, count 0 2006.201.13:38:50.60#ibcon#end of sib2, iclass 31, count 0 2006.201.13:38:50.60#ibcon#*after write, iclass 31, count 0 2006.201.13:38:50.60#ibcon#*before return 0, iclass 31, count 0 2006.201.13:38:50.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:50.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:50.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:38:50.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:38:50.60$vck44/va=3,8 2006.201.13:38:50.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.13:38:50.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.13:38:50.60#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:50.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:50.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:50.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:50.65#ibcon#enter wrdev, iclass 33, count 2 2006.201.13:38:50.65#ibcon#first serial, iclass 33, count 2 2006.201.13:38:50.65#ibcon#enter sib2, iclass 33, count 2 2006.201.13:38:50.65#ibcon#flushed, iclass 33, count 2 2006.201.13:38:50.65#ibcon#about to write, iclass 33, count 2 2006.201.13:38:50.65#ibcon#wrote, iclass 33, count 2 2006.201.13:38:50.65#ibcon#about to read 3, iclass 33, count 2 2006.201.13:38:50.67#ibcon#read 3, iclass 33, count 2 2006.201.13:38:50.67#ibcon#about to read 4, iclass 33, count 2 2006.201.13:38:50.67#ibcon#read 4, iclass 33, count 2 2006.201.13:38:50.67#ibcon#about to read 5, iclass 33, count 2 2006.201.13:38:50.67#ibcon#read 5, iclass 33, count 2 2006.201.13:38:50.67#ibcon#about to read 6, iclass 33, count 2 2006.201.13:38:50.67#ibcon#read 6, iclass 33, count 2 2006.201.13:38:50.67#ibcon#end of sib2, iclass 33, count 2 2006.201.13:38:50.67#ibcon#*mode == 0, iclass 33, count 2 2006.201.13:38:50.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.13:38:50.67#ibcon#[25=AT03-08\r\n] 2006.201.13:38:50.67#ibcon#*before write, iclass 33, count 2 2006.201.13:38:50.67#ibcon#enter sib2, iclass 33, count 2 2006.201.13:38:50.67#ibcon#flushed, iclass 33, count 2 2006.201.13:38:50.67#ibcon#about to write, iclass 33, count 2 2006.201.13:38:50.67#ibcon#wrote, iclass 33, count 2 2006.201.13:38:50.67#ibcon#about to read 3, iclass 33, count 2 2006.201.13:38:50.70#ibcon#read 3, iclass 33, count 2 2006.201.13:38:50.70#ibcon#about to read 4, iclass 33, count 2 2006.201.13:38:50.70#ibcon#read 4, iclass 33, count 2 2006.201.13:38:50.70#ibcon#about to read 5, iclass 33, count 2 2006.201.13:38:50.70#ibcon#read 5, iclass 33, count 2 2006.201.13:38:50.70#ibcon#about to read 6, iclass 33, count 2 2006.201.13:38:50.70#ibcon#read 6, iclass 33, count 2 2006.201.13:38:50.70#ibcon#end of sib2, iclass 33, count 2 2006.201.13:38:50.70#ibcon#*after write, iclass 33, count 2 2006.201.13:38:50.70#ibcon#*before return 0, iclass 33, count 2 2006.201.13:38:50.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:50.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:50.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.13:38:50.70#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:50.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:50.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:50.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:50.82#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:38:50.82#ibcon#first serial, iclass 33, count 0 2006.201.13:38:50.82#ibcon#enter sib2, iclass 33, count 0 2006.201.13:38:50.82#ibcon#flushed, iclass 33, count 0 2006.201.13:38:50.82#ibcon#about to write, iclass 33, count 0 2006.201.13:38:50.82#ibcon#wrote, iclass 33, count 0 2006.201.13:38:50.82#ibcon#about to read 3, iclass 33, count 0 2006.201.13:38:50.84#ibcon#read 3, iclass 33, count 0 2006.201.13:38:50.84#ibcon#about to read 4, iclass 33, count 0 2006.201.13:38:50.84#ibcon#read 4, iclass 33, count 0 2006.201.13:38:50.84#ibcon#about to read 5, iclass 33, count 0 2006.201.13:38:50.84#ibcon#read 5, iclass 33, count 0 2006.201.13:38:50.84#ibcon#about to read 6, iclass 33, count 0 2006.201.13:38:50.84#ibcon#read 6, iclass 33, count 0 2006.201.13:38:50.84#ibcon#end of sib2, iclass 33, count 0 2006.201.13:38:50.84#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:38:50.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:38:50.84#ibcon#[25=USB\r\n] 2006.201.13:38:50.84#ibcon#*before write, iclass 33, count 0 2006.201.13:38:50.84#ibcon#enter sib2, iclass 33, count 0 2006.201.13:38:50.84#ibcon#flushed, iclass 33, count 0 2006.201.13:38:50.84#ibcon#about to write, iclass 33, count 0 2006.201.13:38:50.84#ibcon#wrote, iclass 33, count 0 2006.201.13:38:50.84#ibcon#about to read 3, iclass 33, count 0 2006.201.13:38:50.87#ibcon#read 3, iclass 33, count 0 2006.201.13:38:50.87#ibcon#about to read 4, iclass 33, count 0 2006.201.13:38:50.87#ibcon#read 4, iclass 33, count 0 2006.201.13:38:50.87#ibcon#about to read 5, iclass 33, count 0 2006.201.13:38:50.87#ibcon#read 5, iclass 33, count 0 2006.201.13:38:50.87#ibcon#about to read 6, iclass 33, count 0 2006.201.13:38:50.87#ibcon#read 6, iclass 33, count 0 2006.201.13:38:50.87#ibcon#end of sib2, iclass 33, count 0 2006.201.13:38:50.87#ibcon#*after write, iclass 33, count 0 2006.201.13:38:50.87#ibcon#*before return 0, iclass 33, count 0 2006.201.13:38:50.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:50.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:50.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:38:50.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:38:50.87$vck44/valo=4,624.99 2006.201.13:38:50.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.13:38:50.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.13:38:50.87#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:50.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:50.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:50.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:50.87#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:38:50.87#ibcon#first serial, iclass 35, count 0 2006.201.13:38:50.87#ibcon#enter sib2, iclass 35, count 0 2006.201.13:38:50.87#ibcon#flushed, iclass 35, count 0 2006.201.13:38:50.87#ibcon#about to write, iclass 35, count 0 2006.201.13:38:50.87#ibcon#wrote, iclass 35, count 0 2006.201.13:38:50.87#ibcon#about to read 3, iclass 35, count 0 2006.201.13:38:50.89#ibcon#read 3, iclass 35, count 0 2006.201.13:38:50.89#ibcon#about to read 4, iclass 35, count 0 2006.201.13:38:50.89#ibcon#read 4, iclass 35, count 0 2006.201.13:38:50.89#ibcon#about to read 5, iclass 35, count 0 2006.201.13:38:50.89#ibcon#read 5, iclass 35, count 0 2006.201.13:38:50.89#ibcon#about to read 6, iclass 35, count 0 2006.201.13:38:50.89#ibcon#read 6, iclass 35, count 0 2006.201.13:38:50.89#ibcon#end of sib2, iclass 35, count 0 2006.201.13:38:50.89#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:38:50.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:38:50.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:38:50.89#ibcon#*before write, iclass 35, count 0 2006.201.13:38:50.89#ibcon#enter sib2, iclass 35, count 0 2006.201.13:38:50.89#ibcon#flushed, iclass 35, count 0 2006.201.13:38:50.89#ibcon#about to write, iclass 35, count 0 2006.201.13:38:50.89#ibcon#wrote, iclass 35, count 0 2006.201.13:38:50.89#ibcon#about to read 3, iclass 35, count 0 2006.201.13:38:50.93#ibcon#read 3, iclass 35, count 0 2006.201.13:38:50.93#ibcon#about to read 4, iclass 35, count 0 2006.201.13:38:50.93#ibcon#read 4, iclass 35, count 0 2006.201.13:38:50.93#ibcon#about to read 5, iclass 35, count 0 2006.201.13:38:50.93#ibcon#read 5, iclass 35, count 0 2006.201.13:38:50.93#ibcon#about to read 6, iclass 35, count 0 2006.201.13:38:50.93#ibcon#read 6, iclass 35, count 0 2006.201.13:38:50.93#ibcon#end of sib2, iclass 35, count 0 2006.201.13:38:50.93#ibcon#*after write, iclass 35, count 0 2006.201.13:38:50.93#ibcon#*before return 0, iclass 35, count 0 2006.201.13:38:50.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:50.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:50.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:38:50.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:38:50.93$vck44/va=4,7 2006.201.13:38:50.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.13:38:50.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.13:38:50.93#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:50.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:50.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:50.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:50.99#ibcon#enter wrdev, iclass 37, count 2 2006.201.13:38:50.99#ibcon#first serial, iclass 37, count 2 2006.201.13:38:50.99#ibcon#enter sib2, iclass 37, count 2 2006.201.13:38:50.99#ibcon#flushed, iclass 37, count 2 2006.201.13:38:50.99#ibcon#about to write, iclass 37, count 2 2006.201.13:38:50.99#ibcon#wrote, iclass 37, count 2 2006.201.13:38:50.99#ibcon#about to read 3, iclass 37, count 2 2006.201.13:38:51.01#ibcon#read 3, iclass 37, count 2 2006.201.13:38:51.01#ibcon#about to read 4, iclass 37, count 2 2006.201.13:38:51.01#ibcon#read 4, iclass 37, count 2 2006.201.13:38:51.01#ibcon#about to read 5, iclass 37, count 2 2006.201.13:38:51.01#ibcon#read 5, iclass 37, count 2 2006.201.13:38:51.01#ibcon#about to read 6, iclass 37, count 2 2006.201.13:38:51.01#ibcon#read 6, iclass 37, count 2 2006.201.13:38:51.01#ibcon#end of sib2, iclass 37, count 2 2006.201.13:38:51.01#ibcon#*mode == 0, iclass 37, count 2 2006.201.13:38:51.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.13:38:51.01#ibcon#[25=AT04-07\r\n] 2006.201.13:38:51.01#ibcon#*before write, iclass 37, count 2 2006.201.13:38:51.01#ibcon#enter sib2, iclass 37, count 2 2006.201.13:38:51.01#ibcon#flushed, iclass 37, count 2 2006.201.13:38:51.01#ibcon#about to write, iclass 37, count 2 2006.201.13:38:51.01#ibcon#wrote, iclass 37, count 2 2006.201.13:38:51.01#ibcon#about to read 3, iclass 37, count 2 2006.201.13:38:51.04#ibcon#read 3, iclass 37, count 2 2006.201.13:38:51.04#ibcon#about to read 4, iclass 37, count 2 2006.201.13:38:51.04#ibcon#read 4, iclass 37, count 2 2006.201.13:38:51.04#ibcon#about to read 5, iclass 37, count 2 2006.201.13:38:51.04#ibcon#read 5, iclass 37, count 2 2006.201.13:38:51.04#ibcon#about to read 6, iclass 37, count 2 2006.201.13:38:51.04#ibcon#read 6, iclass 37, count 2 2006.201.13:38:51.04#ibcon#end of sib2, iclass 37, count 2 2006.201.13:38:51.04#ibcon#*after write, iclass 37, count 2 2006.201.13:38:51.04#ibcon#*before return 0, iclass 37, count 2 2006.201.13:38:51.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:51.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:51.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.13:38:51.04#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:51.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:51.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:51.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:51.16#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:38:51.16#ibcon#first serial, iclass 37, count 0 2006.201.13:38:51.16#ibcon#enter sib2, iclass 37, count 0 2006.201.13:38:51.16#ibcon#flushed, iclass 37, count 0 2006.201.13:38:51.16#ibcon#about to write, iclass 37, count 0 2006.201.13:38:51.16#ibcon#wrote, iclass 37, count 0 2006.201.13:38:51.16#ibcon#about to read 3, iclass 37, count 0 2006.201.13:38:51.18#ibcon#read 3, iclass 37, count 0 2006.201.13:38:51.18#ibcon#about to read 4, iclass 37, count 0 2006.201.13:38:51.18#ibcon#read 4, iclass 37, count 0 2006.201.13:38:51.18#ibcon#about to read 5, iclass 37, count 0 2006.201.13:38:51.18#ibcon#read 5, iclass 37, count 0 2006.201.13:38:51.18#ibcon#about to read 6, iclass 37, count 0 2006.201.13:38:51.18#ibcon#read 6, iclass 37, count 0 2006.201.13:38:51.18#ibcon#end of sib2, iclass 37, count 0 2006.201.13:38:51.18#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:38:51.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:38:51.18#ibcon#[25=USB\r\n] 2006.201.13:38:51.18#ibcon#*before write, iclass 37, count 0 2006.201.13:38:51.18#ibcon#enter sib2, iclass 37, count 0 2006.201.13:38:51.18#ibcon#flushed, iclass 37, count 0 2006.201.13:38:51.18#ibcon#about to write, iclass 37, count 0 2006.201.13:38:51.18#ibcon#wrote, iclass 37, count 0 2006.201.13:38:51.18#ibcon#about to read 3, iclass 37, count 0 2006.201.13:38:51.21#ibcon#read 3, iclass 37, count 0 2006.201.13:38:51.21#ibcon#about to read 4, iclass 37, count 0 2006.201.13:38:51.21#ibcon#read 4, iclass 37, count 0 2006.201.13:38:51.21#ibcon#about to read 5, iclass 37, count 0 2006.201.13:38:51.21#ibcon#read 5, iclass 37, count 0 2006.201.13:38:51.21#ibcon#about to read 6, iclass 37, count 0 2006.201.13:38:51.21#ibcon#read 6, iclass 37, count 0 2006.201.13:38:51.21#ibcon#end of sib2, iclass 37, count 0 2006.201.13:38:51.21#ibcon#*after write, iclass 37, count 0 2006.201.13:38:51.21#ibcon#*before return 0, iclass 37, count 0 2006.201.13:38:51.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:51.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:51.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:38:51.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:38:51.21$vck44/valo=5,734.99 2006.201.13:38:51.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.13:38:51.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.13:38:51.21#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:51.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:51.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:51.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:51.21#ibcon#enter wrdev, iclass 39, count 0 2006.201.13:38:51.21#ibcon#first serial, iclass 39, count 0 2006.201.13:38:51.21#ibcon#enter sib2, iclass 39, count 0 2006.201.13:38:51.21#ibcon#flushed, iclass 39, count 0 2006.201.13:38:51.21#ibcon#about to write, iclass 39, count 0 2006.201.13:38:51.21#ibcon#wrote, iclass 39, count 0 2006.201.13:38:51.21#ibcon#about to read 3, iclass 39, count 0 2006.201.13:38:51.23#ibcon#read 3, iclass 39, count 0 2006.201.13:38:51.23#ibcon#about to read 4, iclass 39, count 0 2006.201.13:38:51.23#ibcon#read 4, iclass 39, count 0 2006.201.13:38:51.23#ibcon#about to read 5, iclass 39, count 0 2006.201.13:38:51.23#ibcon#read 5, iclass 39, count 0 2006.201.13:38:51.23#ibcon#about to read 6, iclass 39, count 0 2006.201.13:38:51.23#ibcon#read 6, iclass 39, count 0 2006.201.13:38:51.23#ibcon#end of sib2, iclass 39, count 0 2006.201.13:38:51.23#ibcon#*mode == 0, iclass 39, count 0 2006.201.13:38:51.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.13:38:51.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:38:51.23#ibcon#*before write, iclass 39, count 0 2006.201.13:38:51.23#ibcon#enter sib2, iclass 39, count 0 2006.201.13:38:51.23#ibcon#flushed, iclass 39, count 0 2006.201.13:38:51.23#ibcon#about to write, iclass 39, count 0 2006.201.13:38:51.23#ibcon#wrote, iclass 39, count 0 2006.201.13:38:51.23#ibcon#about to read 3, iclass 39, count 0 2006.201.13:38:51.27#ibcon#read 3, iclass 39, count 0 2006.201.13:38:51.27#ibcon#about to read 4, iclass 39, count 0 2006.201.13:38:51.27#ibcon#read 4, iclass 39, count 0 2006.201.13:38:51.27#ibcon#about to read 5, iclass 39, count 0 2006.201.13:38:51.27#ibcon#read 5, iclass 39, count 0 2006.201.13:38:51.27#ibcon#about to read 6, iclass 39, count 0 2006.201.13:38:51.27#ibcon#read 6, iclass 39, count 0 2006.201.13:38:51.27#ibcon#end of sib2, iclass 39, count 0 2006.201.13:38:51.27#ibcon#*after write, iclass 39, count 0 2006.201.13:38:51.27#ibcon#*before return 0, iclass 39, count 0 2006.201.13:38:51.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:51.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:51.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.13:38:51.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.13:38:51.27$vck44/va=5,4 2006.201.13:38:51.27#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.13:38:51.27#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.13:38:51.27#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:51.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:51.33#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:51.33#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:51.33#ibcon#enter wrdev, iclass 2, count 2 2006.201.13:38:51.33#ibcon#first serial, iclass 2, count 2 2006.201.13:38:51.33#ibcon#enter sib2, iclass 2, count 2 2006.201.13:38:51.33#ibcon#flushed, iclass 2, count 2 2006.201.13:38:51.33#ibcon#about to write, iclass 2, count 2 2006.201.13:38:51.33#ibcon#wrote, iclass 2, count 2 2006.201.13:38:51.33#ibcon#about to read 3, iclass 2, count 2 2006.201.13:38:51.35#ibcon#read 3, iclass 2, count 2 2006.201.13:38:51.35#ibcon#about to read 4, iclass 2, count 2 2006.201.13:38:51.35#ibcon#read 4, iclass 2, count 2 2006.201.13:38:51.35#ibcon#about to read 5, iclass 2, count 2 2006.201.13:38:51.35#ibcon#read 5, iclass 2, count 2 2006.201.13:38:51.35#ibcon#about to read 6, iclass 2, count 2 2006.201.13:38:51.35#ibcon#read 6, iclass 2, count 2 2006.201.13:38:51.35#ibcon#end of sib2, iclass 2, count 2 2006.201.13:38:51.35#ibcon#*mode == 0, iclass 2, count 2 2006.201.13:38:51.35#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.13:38:51.35#ibcon#[25=AT05-04\r\n] 2006.201.13:38:51.35#ibcon#*before write, iclass 2, count 2 2006.201.13:38:51.35#ibcon#enter sib2, iclass 2, count 2 2006.201.13:38:51.35#ibcon#flushed, iclass 2, count 2 2006.201.13:38:51.35#ibcon#about to write, iclass 2, count 2 2006.201.13:38:51.35#ibcon#wrote, iclass 2, count 2 2006.201.13:38:51.35#ibcon#about to read 3, iclass 2, count 2 2006.201.13:38:51.38#ibcon#read 3, iclass 2, count 2 2006.201.13:38:51.38#ibcon#about to read 4, iclass 2, count 2 2006.201.13:38:51.38#ibcon#read 4, iclass 2, count 2 2006.201.13:38:51.38#ibcon#about to read 5, iclass 2, count 2 2006.201.13:38:51.38#ibcon#read 5, iclass 2, count 2 2006.201.13:38:51.38#ibcon#about to read 6, iclass 2, count 2 2006.201.13:38:51.38#ibcon#read 6, iclass 2, count 2 2006.201.13:38:51.38#ibcon#end of sib2, iclass 2, count 2 2006.201.13:38:51.38#ibcon#*after write, iclass 2, count 2 2006.201.13:38:51.38#ibcon#*before return 0, iclass 2, count 2 2006.201.13:38:51.38#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:51.38#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:51.38#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.13:38:51.38#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:51.38#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:51.50#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:51.50#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:51.50#ibcon#enter wrdev, iclass 2, count 0 2006.201.13:38:51.50#ibcon#first serial, iclass 2, count 0 2006.201.13:38:51.50#ibcon#enter sib2, iclass 2, count 0 2006.201.13:38:51.50#ibcon#flushed, iclass 2, count 0 2006.201.13:38:51.50#ibcon#about to write, iclass 2, count 0 2006.201.13:38:51.50#ibcon#wrote, iclass 2, count 0 2006.201.13:38:51.50#ibcon#about to read 3, iclass 2, count 0 2006.201.13:38:51.52#ibcon#read 3, iclass 2, count 0 2006.201.13:38:51.52#ibcon#about to read 4, iclass 2, count 0 2006.201.13:38:51.52#ibcon#read 4, iclass 2, count 0 2006.201.13:38:51.52#ibcon#about to read 5, iclass 2, count 0 2006.201.13:38:51.52#ibcon#read 5, iclass 2, count 0 2006.201.13:38:51.52#ibcon#about to read 6, iclass 2, count 0 2006.201.13:38:51.52#ibcon#read 6, iclass 2, count 0 2006.201.13:38:51.52#ibcon#end of sib2, iclass 2, count 0 2006.201.13:38:51.52#ibcon#*mode == 0, iclass 2, count 0 2006.201.13:38:51.52#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.13:38:51.52#ibcon#[25=USB\r\n] 2006.201.13:38:51.52#ibcon#*before write, iclass 2, count 0 2006.201.13:38:51.52#ibcon#enter sib2, iclass 2, count 0 2006.201.13:38:51.52#ibcon#flushed, iclass 2, count 0 2006.201.13:38:51.52#ibcon#about to write, iclass 2, count 0 2006.201.13:38:51.52#ibcon#wrote, iclass 2, count 0 2006.201.13:38:51.52#ibcon#about to read 3, iclass 2, count 0 2006.201.13:38:51.55#ibcon#read 3, iclass 2, count 0 2006.201.13:38:51.55#ibcon#about to read 4, iclass 2, count 0 2006.201.13:38:51.55#ibcon#read 4, iclass 2, count 0 2006.201.13:38:51.55#ibcon#about to read 5, iclass 2, count 0 2006.201.13:38:51.55#ibcon#read 5, iclass 2, count 0 2006.201.13:38:51.55#ibcon#about to read 6, iclass 2, count 0 2006.201.13:38:51.55#ibcon#read 6, iclass 2, count 0 2006.201.13:38:51.55#ibcon#end of sib2, iclass 2, count 0 2006.201.13:38:51.55#ibcon#*after write, iclass 2, count 0 2006.201.13:38:51.55#ibcon#*before return 0, iclass 2, count 0 2006.201.13:38:51.55#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:51.55#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:51.55#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.13:38:51.55#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.13:38:51.55$vck44/valo=6,814.99 2006.201.13:38:51.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.13:38:51.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.13:38:51.55#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:51.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:51.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:51.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:51.55#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:38:51.55#ibcon#first serial, iclass 5, count 0 2006.201.13:38:51.55#ibcon#enter sib2, iclass 5, count 0 2006.201.13:38:51.55#ibcon#flushed, iclass 5, count 0 2006.201.13:38:51.55#ibcon#about to write, iclass 5, count 0 2006.201.13:38:51.55#ibcon#wrote, iclass 5, count 0 2006.201.13:38:51.55#ibcon#about to read 3, iclass 5, count 0 2006.201.13:38:51.57#ibcon#read 3, iclass 5, count 0 2006.201.13:38:51.57#ibcon#about to read 4, iclass 5, count 0 2006.201.13:38:51.57#ibcon#read 4, iclass 5, count 0 2006.201.13:38:51.57#ibcon#about to read 5, iclass 5, count 0 2006.201.13:38:51.57#ibcon#read 5, iclass 5, count 0 2006.201.13:38:51.57#ibcon#about to read 6, iclass 5, count 0 2006.201.13:38:51.57#ibcon#read 6, iclass 5, count 0 2006.201.13:38:51.57#ibcon#end of sib2, iclass 5, count 0 2006.201.13:38:51.57#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:38:51.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:38:51.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:38:51.57#ibcon#*before write, iclass 5, count 0 2006.201.13:38:51.57#ibcon#enter sib2, iclass 5, count 0 2006.201.13:38:51.57#ibcon#flushed, iclass 5, count 0 2006.201.13:38:51.57#ibcon#about to write, iclass 5, count 0 2006.201.13:38:51.57#ibcon#wrote, iclass 5, count 0 2006.201.13:38:51.57#ibcon#about to read 3, iclass 5, count 0 2006.201.13:38:51.61#ibcon#read 3, iclass 5, count 0 2006.201.13:38:51.61#ibcon#about to read 4, iclass 5, count 0 2006.201.13:38:51.61#ibcon#read 4, iclass 5, count 0 2006.201.13:38:51.61#ibcon#about to read 5, iclass 5, count 0 2006.201.13:38:51.61#ibcon#read 5, iclass 5, count 0 2006.201.13:38:51.61#ibcon#about to read 6, iclass 5, count 0 2006.201.13:38:51.61#ibcon#read 6, iclass 5, count 0 2006.201.13:38:51.61#ibcon#end of sib2, iclass 5, count 0 2006.201.13:38:51.61#ibcon#*after write, iclass 5, count 0 2006.201.13:38:51.61#ibcon#*before return 0, iclass 5, count 0 2006.201.13:38:51.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:51.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:51.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:38:51.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:38:51.61$vck44/va=6,5 2006.201.13:38:51.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.13:38:51.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.13:38:51.61#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:51.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:51.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:51.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:51.67#ibcon#enter wrdev, iclass 7, count 2 2006.201.13:38:51.67#ibcon#first serial, iclass 7, count 2 2006.201.13:38:51.67#ibcon#enter sib2, iclass 7, count 2 2006.201.13:38:51.67#ibcon#flushed, iclass 7, count 2 2006.201.13:38:51.67#ibcon#about to write, iclass 7, count 2 2006.201.13:38:51.67#ibcon#wrote, iclass 7, count 2 2006.201.13:38:51.67#ibcon#about to read 3, iclass 7, count 2 2006.201.13:38:51.69#ibcon#read 3, iclass 7, count 2 2006.201.13:38:51.69#ibcon#about to read 4, iclass 7, count 2 2006.201.13:38:51.69#ibcon#read 4, iclass 7, count 2 2006.201.13:38:51.69#ibcon#about to read 5, iclass 7, count 2 2006.201.13:38:51.69#ibcon#read 5, iclass 7, count 2 2006.201.13:38:51.69#ibcon#about to read 6, iclass 7, count 2 2006.201.13:38:51.69#ibcon#read 6, iclass 7, count 2 2006.201.13:38:51.69#ibcon#end of sib2, iclass 7, count 2 2006.201.13:38:51.69#ibcon#*mode == 0, iclass 7, count 2 2006.201.13:38:51.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.13:38:51.69#ibcon#[25=AT06-05\r\n] 2006.201.13:38:51.69#ibcon#*before write, iclass 7, count 2 2006.201.13:38:51.69#ibcon#enter sib2, iclass 7, count 2 2006.201.13:38:51.69#ibcon#flushed, iclass 7, count 2 2006.201.13:38:51.69#ibcon#about to write, iclass 7, count 2 2006.201.13:38:51.69#ibcon#wrote, iclass 7, count 2 2006.201.13:38:51.69#ibcon#about to read 3, iclass 7, count 2 2006.201.13:38:51.72#ibcon#read 3, iclass 7, count 2 2006.201.13:38:51.72#ibcon#about to read 4, iclass 7, count 2 2006.201.13:38:51.72#ibcon#read 4, iclass 7, count 2 2006.201.13:38:51.72#ibcon#about to read 5, iclass 7, count 2 2006.201.13:38:51.72#ibcon#read 5, iclass 7, count 2 2006.201.13:38:51.72#ibcon#about to read 6, iclass 7, count 2 2006.201.13:38:51.72#ibcon#read 6, iclass 7, count 2 2006.201.13:38:51.72#ibcon#end of sib2, iclass 7, count 2 2006.201.13:38:51.72#ibcon#*after write, iclass 7, count 2 2006.201.13:38:51.72#ibcon#*before return 0, iclass 7, count 2 2006.201.13:38:51.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:51.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:51.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.13:38:51.72#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:51.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:51.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:51.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:51.84#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:38:51.84#ibcon#first serial, iclass 7, count 0 2006.201.13:38:51.84#ibcon#enter sib2, iclass 7, count 0 2006.201.13:38:51.84#ibcon#flushed, iclass 7, count 0 2006.201.13:38:51.84#ibcon#about to write, iclass 7, count 0 2006.201.13:38:51.84#ibcon#wrote, iclass 7, count 0 2006.201.13:38:51.84#ibcon#about to read 3, iclass 7, count 0 2006.201.13:38:51.86#ibcon#read 3, iclass 7, count 0 2006.201.13:38:51.86#ibcon#about to read 4, iclass 7, count 0 2006.201.13:38:51.86#ibcon#read 4, iclass 7, count 0 2006.201.13:38:51.86#ibcon#about to read 5, iclass 7, count 0 2006.201.13:38:51.86#ibcon#read 5, iclass 7, count 0 2006.201.13:38:51.86#ibcon#about to read 6, iclass 7, count 0 2006.201.13:38:51.86#ibcon#read 6, iclass 7, count 0 2006.201.13:38:51.86#ibcon#end of sib2, iclass 7, count 0 2006.201.13:38:51.86#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:38:51.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:38:51.86#ibcon#[25=USB\r\n] 2006.201.13:38:51.86#ibcon#*before write, iclass 7, count 0 2006.201.13:38:51.86#ibcon#enter sib2, iclass 7, count 0 2006.201.13:38:51.86#ibcon#flushed, iclass 7, count 0 2006.201.13:38:51.86#ibcon#about to write, iclass 7, count 0 2006.201.13:38:51.86#ibcon#wrote, iclass 7, count 0 2006.201.13:38:51.86#ibcon#about to read 3, iclass 7, count 0 2006.201.13:38:51.89#ibcon#read 3, iclass 7, count 0 2006.201.13:38:51.89#ibcon#about to read 4, iclass 7, count 0 2006.201.13:38:51.89#ibcon#read 4, iclass 7, count 0 2006.201.13:38:51.89#ibcon#about to read 5, iclass 7, count 0 2006.201.13:38:51.89#ibcon#read 5, iclass 7, count 0 2006.201.13:38:51.89#ibcon#about to read 6, iclass 7, count 0 2006.201.13:38:51.89#ibcon#read 6, iclass 7, count 0 2006.201.13:38:51.89#ibcon#end of sib2, iclass 7, count 0 2006.201.13:38:51.89#ibcon#*after write, iclass 7, count 0 2006.201.13:38:51.89#ibcon#*before return 0, iclass 7, count 0 2006.201.13:38:51.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:51.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:51.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:38:51.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:38:51.89$vck44/valo=7,864.99 2006.201.13:38:51.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.13:38:51.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.13:38:51.89#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:51.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:51.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:51.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:51.89#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:38:51.89#ibcon#first serial, iclass 11, count 0 2006.201.13:38:51.89#ibcon#enter sib2, iclass 11, count 0 2006.201.13:38:51.89#ibcon#flushed, iclass 11, count 0 2006.201.13:38:51.89#ibcon#about to write, iclass 11, count 0 2006.201.13:38:51.89#ibcon#wrote, iclass 11, count 0 2006.201.13:38:51.89#ibcon#about to read 3, iclass 11, count 0 2006.201.13:38:51.91#ibcon#read 3, iclass 11, count 0 2006.201.13:38:51.91#ibcon#about to read 4, iclass 11, count 0 2006.201.13:38:51.91#ibcon#read 4, iclass 11, count 0 2006.201.13:38:51.91#ibcon#about to read 5, iclass 11, count 0 2006.201.13:38:51.91#ibcon#read 5, iclass 11, count 0 2006.201.13:38:51.91#ibcon#about to read 6, iclass 11, count 0 2006.201.13:38:51.91#ibcon#read 6, iclass 11, count 0 2006.201.13:38:51.91#ibcon#end of sib2, iclass 11, count 0 2006.201.13:38:51.91#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:38:51.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:38:51.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:38:51.91#ibcon#*before write, iclass 11, count 0 2006.201.13:38:51.91#ibcon#enter sib2, iclass 11, count 0 2006.201.13:38:51.91#ibcon#flushed, iclass 11, count 0 2006.201.13:38:51.91#ibcon#about to write, iclass 11, count 0 2006.201.13:38:51.91#ibcon#wrote, iclass 11, count 0 2006.201.13:38:51.91#ibcon#about to read 3, iclass 11, count 0 2006.201.13:38:51.95#ibcon#read 3, iclass 11, count 0 2006.201.13:38:51.95#ibcon#about to read 4, iclass 11, count 0 2006.201.13:38:51.95#ibcon#read 4, iclass 11, count 0 2006.201.13:38:51.95#ibcon#about to read 5, iclass 11, count 0 2006.201.13:38:51.95#ibcon#read 5, iclass 11, count 0 2006.201.13:38:51.95#ibcon#about to read 6, iclass 11, count 0 2006.201.13:38:51.95#ibcon#read 6, iclass 11, count 0 2006.201.13:38:51.95#ibcon#end of sib2, iclass 11, count 0 2006.201.13:38:51.95#ibcon#*after write, iclass 11, count 0 2006.201.13:38:51.95#ibcon#*before return 0, iclass 11, count 0 2006.201.13:38:51.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:51.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:51.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:38:51.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:38:51.95$vck44/va=7,5 2006.201.13:38:51.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.13:38:51.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.13:38:51.95#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:51.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:52.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:52.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:52.01#ibcon#enter wrdev, iclass 13, count 2 2006.201.13:38:52.01#ibcon#first serial, iclass 13, count 2 2006.201.13:38:52.01#ibcon#enter sib2, iclass 13, count 2 2006.201.13:38:52.01#ibcon#flushed, iclass 13, count 2 2006.201.13:38:52.01#ibcon#about to write, iclass 13, count 2 2006.201.13:38:52.01#ibcon#wrote, iclass 13, count 2 2006.201.13:38:52.01#ibcon#about to read 3, iclass 13, count 2 2006.201.13:38:52.03#ibcon#read 3, iclass 13, count 2 2006.201.13:38:52.03#ibcon#about to read 4, iclass 13, count 2 2006.201.13:38:52.03#ibcon#read 4, iclass 13, count 2 2006.201.13:38:52.03#ibcon#about to read 5, iclass 13, count 2 2006.201.13:38:52.03#ibcon#read 5, iclass 13, count 2 2006.201.13:38:52.03#ibcon#about to read 6, iclass 13, count 2 2006.201.13:38:52.03#ibcon#read 6, iclass 13, count 2 2006.201.13:38:52.03#ibcon#end of sib2, iclass 13, count 2 2006.201.13:38:52.03#ibcon#*mode == 0, iclass 13, count 2 2006.201.13:38:52.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.13:38:52.03#ibcon#[25=AT07-05\r\n] 2006.201.13:38:52.03#ibcon#*before write, iclass 13, count 2 2006.201.13:38:52.03#ibcon#enter sib2, iclass 13, count 2 2006.201.13:38:52.03#ibcon#flushed, iclass 13, count 2 2006.201.13:38:52.03#ibcon#about to write, iclass 13, count 2 2006.201.13:38:52.03#ibcon#wrote, iclass 13, count 2 2006.201.13:38:52.03#ibcon#about to read 3, iclass 13, count 2 2006.201.13:38:52.06#ibcon#read 3, iclass 13, count 2 2006.201.13:38:52.06#ibcon#about to read 4, iclass 13, count 2 2006.201.13:38:52.06#ibcon#read 4, iclass 13, count 2 2006.201.13:38:52.06#ibcon#about to read 5, iclass 13, count 2 2006.201.13:38:52.06#ibcon#read 5, iclass 13, count 2 2006.201.13:38:52.06#ibcon#about to read 6, iclass 13, count 2 2006.201.13:38:52.06#ibcon#read 6, iclass 13, count 2 2006.201.13:38:52.06#ibcon#end of sib2, iclass 13, count 2 2006.201.13:38:52.06#ibcon#*after write, iclass 13, count 2 2006.201.13:38:52.06#ibcon#*before return 0, iclass 13, count 2 2006.201.13:38:52.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:52.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:52.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.13:38:52.06#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:52.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:52.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:52.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:52.18#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:38:52.18#ibcon#first serial, iclass 13, count 0 2006.201.13:38:52.18#ibcon#enter sib2, iclass 13, count 0 2006.201.13:38:52.18#ibcon#flushed, iclass 13, count 0 2006.201.13:38:52.18#ibcon#about to write, iclass 13, count 0 2006.201.13:38:52.18#ibcon#wrote, iclass 13, count 0 2006.201.13:38:52.18#ibcon#about to read 3, iclass 13, count 0 2006.201.13:38:52.20#ibcon#read 3, iclass 13, count 0 2006.201.13:38:52.20#ibcon#about to read 4, iclass 13, count 0 2006.201.13:38:52.20#ibcon#read 4, iclass 13, count 0 2006.201.13:38:52.20#ibcon#about to read 5, iclass 13, count 0 2006.201.13:38:52.20#ibcon#read 5, iclass 13, count 0 2006.201.13:38:52.20#ibcon#about to read 6, iclass 13, count 0 2006.201.13:38:52.20#ibcon#read 6, iclass 13, count 0 2006.201.13:38:52.20#ibcon#end of sib2, iclass 13, count 0 2006.201.13:38:52.20#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:38:52.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:38:52.20#ibcon#[25=USB\r\n] 2006.201.13:38:52.20#ibcon#*before write, iclass 13, count 0 2006.201.13:38:52.20#ibcon#enter sib2, iclass 13, count 0 2006.201.13:38:52.20#ibcon#flushed, iclass 13, count 0 2006.201.13:38:52.20#ibcon#about to write, iclass 13, count 0 2006.201.13:38:52.20#ibcon#wrote, iclass 13, count 0 2006.201.13:38:52.20#ibcon#about to read 3, iclass 13, count 0 2006.201.13:38:52.23#ibcon#read 3, iclass 13, count 0 2006.201.13:38:52.23#ibcon#about to read 4, iclass 13, count 0 2006.201.13:38:52.23#ibcon#read 4, iclass 13, count 0 2006.201.13:38:52.23#ibcon#about to read 5, iclass 13, count 0 2006.201.13:38:52.23#ibcon#read 5, iclass 13, count 0 2006.201.13:38:52.23#ibcon#about to read 6, iclass 13, count 0 2006.201.13:38:52.23#ibcon#read 6, iclass 13, count 0 2006.201.13:38:52.23#ibcon#end of sib2, iclass 13, count 0 2006.201.13:38:52.23#ibcon#*after write, iclass 13, count 0 2006.201.13:38:52.23#ibcon#*before return 0, iclass 13, count 0 2006.201.13:38:52.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:52.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:52.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:38:52.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:38:52.23$vck44/valo=8,884.99 2006.201.13:38:52.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.13:38:52.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.13:38:52.23#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:52.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:52.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:52.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:52.23#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:38:52.23#ibcon#first serial, iclass 15, count 0 2006.201.13:38:52.23#ibcon#enter sib2, iclass 15, count 0 2006.201.13:38:52.23#ibcon#flushed, iclass 15, count 0 2006.201.13:38:52.23#ibcon#about to write, iclass 15, count 0 2006.201.13:38:52.23#ibcon#wrote, iclass 15, count 0 2006.201.13:38:52.23#ibcon#about to read 3, iclass 15, count 0 2006.201.13:38:52.25#ibcon#read 3, iclass 15, count 0 2006.201.13:38:52.25#ibcon#about to read 4, iclass 15, count 0 2006.201.13:38:52.25#ibcon#read 4, iclass 15, count 0 2006.201.13:38:52.25#ibcon#about to read 5, iclass 15, count 0 2006.201.13:38:52.25#ibcon#read 5, iclass 15, count 0 2006.201.13:38:52.25#ibcon#about to read 6, iclass 15, count 0 2006.201.13:38:52.25#ibcon#read 6, iclass 15, count 0 2006.201.13:38:52.25#ibcon#end of sib2, iclass 15, count 0 2006.201.13:38:52.25#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:38:52.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:38:52.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:38:52.25#ibcon#*before write, iclass 15, count 0 2006.201.13:38:52.25#ibcon#enter sib2, iclass 15, count 0 2006.201.13:38:52.25#ibcon#flushed, iclass 15, count 0 2006.201.13:38:52.25#ibcon#about to write, iclass 15, count 0 2006.201.13:38:52.25#ibcon#wrote, iclass 15, count 0 2006.201.13:38:52.25#ibcon#about to read 3, iclass 15, count 0 2006.201.13:38:52.29#ibcon#read 3, iclass 15, count 0 2006.201.13:38:52.29#ibcon#about to read 4, iclass 15, count 0 2006.201.13:38:52.29#ibcon#read 4, iclass 15, count 0 2006.201.13:38:52.29#ibcon#about to read 5, iclass 15, count 0 2006.201.13:38:52.29#ibcon#read 5, iclass 15, count 0 2006.201.13:38:52.29#ibcon#about to read 6, iclass 15, count 0 2006.201.13:38:52.29#ibcon#read 6, iclass 15, count 0 2006.201.13:38:52.29#ibcon#end of sib2, iclass 15, count 0 2006.201.13:38:52.29#ibcon#*after write, iclass 15, count 0 2006.201.13:38:52.29#ibcon#*before return 0, iclass 15, count 0 2006.201.13:38:52.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:52.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:52.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:38:52.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:38:52.29$vck44/va=8,4 2006.201.13:38:52.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.13:38:52.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.13:38:52.29#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:52.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:38:52.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:38:52.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:38:52.35#ibcon#enter wrdev, iclass 17, count 2 2006.201.13:38:52.35#ibcon#first serial, iclass 17, count 2 2006.201.13:38:52.35#ibcon#enter sib2, iclass 17, count 2 2006.201.13:38:52.35#ibcon#flushed, iclass 17, count 2 2006.201.13:38:52.35#ibcon#about to write, iclass 17, count 2 2006.201.13:38:52.35#ibcon#wrote, iclass 17, count 2 2006.201.13:38:52.35#ibcon#about to read 3, iclass 17, count 2 2006.201.13:38:52.37#ibcon#read 3, iclass 17, count 2 2006.201.13:38:52.37#ibcon#about to read 4, iclass 17, count 2 2006.201.13:38:52.37#ibcon#read 4, iclass 17, count 2 2006.201.13:38:52.37#ibcon#about to read 5, iclass 17, count 2 2006.201.13:38:52.37#ibcon#read 5, iclass 17, count 2 2006.201.13:38:52.37#ibcon#about to read 6, iclass 17, count 2 2006.201.13:38:52.37#ibcon#read 6, iclass 17, count 2 2006.201.13:38:52.37#ibcon#end of sib2, iclass 17, count 2 2006.201.13:38:52.37#ibcon#*mode == 0, iclass 17, count 2 2006.201.13:38:52.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.13:38:52.37#ibcon#[25=AT08-04\r\n] 2006.201.13:38:52.37#ibcon#*before write, iclass 17, count 2 2006.201.13:38:52.37#ibcon#enter sib2, iclass 17, count 2 2006.201.13:38:52.37#ibcon#flushed, iclass 17, count 2 2006.201.13:38:52.37#ibcon#about to write, iclass 17, count 2 2006.201.13:38:52.37#ibcon#wrote, iclass 17, count 2 2006.201.13:38:52.37#ibcon#about to read 3, iclass 17, count 2 2006.201.13:38:52.40#ibcon#read 3, iclass 17, count 2 2006.201.13:38:52.40#ibcon#about to read 4, iclass 17, count 2 2006.201.13:38:52.40#ibcon#read 4, iclass 17, count 2 2006.201.13:38:52.40#ibcon#about to read 5, iclass 17, count 2 2006.201.13:38:52.40#ibcon#read 5, iclass 17, count 2 2006.201.13:38:52.40#ibcon#about to read 6, iclass 17, count 2 2006.201.13:38:52.40#ibcon#read 6, iclass 17, count 2 2006.201.13:38:52.40#ibcon#end of sib2, iclass 17, count 2 2006.201.13:38:52.40#ibcon#*after write, iclass 17, count 2 2006.201.13:38:52.40#ibcon#*before return 0, iclass 17, count 2 2006.201.13:38:52.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:38:52.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:38:52.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.13:38:52.40#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:52.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:38:52.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:38:52.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:38:52.52#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:38:52.52#ibcon#first serial, iclass 17, count 0 2006.201.13:38:52.52#ibcon#enter sib2, iclass 17, count 0 2006.201.13:38:52.52#ibcon#flushed, iclass 17, count 0 2006.201.13:38:52.52#ibcon#about to write, iclass 17, count 0 2006.201.13:38:52.52#ibcon#wrote, iclass 17, count 0 2006.201.13:38:52.52#ibcon#about to read 3, iclass 17, count 0 2006.201.13:38:52.54#ibcon#read 3, iclass 17, count 0 2006.201.13:38:52.54#ibcon#about to read 4, iclass 17, count 0 2006.201.13:38:52.54#ibcon#read 4, iclass 17, count 0 2006.201.13:38:52.54#ibcon#about to read 5, iclass 17, count 0 2006.201.13:38:52.54#ibcon#read 5, iclass 17, count 0 2006.201.13:38:52.54#ibcon#about to read 6, iclass 17, count 0 2006.201.13:38:52.54#ibcon#read 6, iclass 17, count 0 2006.201.13:38:52.54#ibcon#end of sib2, iclass 17, count 0 2006.201.13:38:52.54#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:38:52.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:38:52.54#ibcon#[25=USB\r\n] 2006.201.13:38:52.54#ibcon#*before write, iclass 17, count 0 2006.201.13:38:52.54#ibcon#enter sib2, iclass 17, count 0 2006.201.13:38:52.54#ibcon#flushed, iclass 17, count 0 2006.201.13:38:52.54#ibcon#about to write, iclass 17, count 0 2006.201.13:38:52.54#ibcon#wrote, iclass 17, count 0 2006.201.13:38:52.54#ibcon#about to read 3, iclass 17, count 0 2006.201.13:38:52.57#ibcon#read 3, iclass 17, count 0 2006.201.13:38:52.57#ibcon#about to read 4, iclass 17, count 0 2006.201.13:38:52.57#ibcon#read 4, iclass 17, count 0 2006.201.13:38:52.57#ibcon#about to read 5, iclass 17, count 0 2006.201.13:38:52.57#ibcon#read 5, iclass 17, count 0 2006.201.13:38:52.57#ibcon#about to read 6, iclass 17, count 0 2006.201.13:38:52.57#ibcon#read 6, iclass 17, count 0 2006.201.13:38:52.57#ibcon#end of sib2, iclass 17, count 0 2006.201.13:38:52.57#ibcon#*after write, iclass 17, count 0 2006.201.13:38:52.57#ibcon#*before return 0, iclass 17, count 0 2006.201.13:38:52.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:38:52.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:38:52.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:38:52.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:38:52.57$vck44/vblo=1,629.99 2006.201.13:38:52.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.13:38:52.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.13:38:52.57#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:52.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:52.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:52.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:52.57#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:38:52.57#ibcon#first serial, iclass 19, count 0 2006.201.13:38:52.57#ibcon#enter sib2, iclass 19, count 0 2006.201.13:38:52.57#ibcon#flushed, iclass 19, count 0 2006.201.13:38:52.57#ibcon#about to write, iclass 19, count 0 2006.201.13:38:52.57#ibcon#wrote, iclass 19, count 0 2006.201.13:38:52.57#ibcon#about to read 3, iclass 19, count 0 2006.201.13:38:52.59#ibcon#read 3, iclass 19, count 0 2006.201.13:38:52.59#ibcon#about to read 4, iclass 19, count 0 2006.201.13:38:52.59#ibcon#read 4, iclass 19, count 0 2006.201.13:38:52.59#ibcon#about to read 5, iclass 19, count 0 2006.201.13:38:52.59#ibcon#read 5, iclass 19, count 0 2006.201.13:38:52.59#ibcon#about to read 6, iclass 19, count 0 2006.201.13:38:52.59#ibcon#read 6, iclass 19, count 0 2006.201.13:38:52.59#ibcon#end of sib2, iclass 19, count 0 2006.201.13:38:52.59#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:38:52.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:38:52.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:38:52.59#ibcon#*before write, iclass 19, count 0 2006.201.13:38:52.59#ibcon#enter sib2, iclass 19, count 0 2006.201.13:38:52.59#ibcon#flushed, iclass 19, count 0 2006.201.13:38:52.59#ibcon#about to write, iclass 19, count 0 2006.201.13:38:52.59#ibcon#wrote, iclass 19, count 0 2006.201.13:38:52.59#ibcon#about to read 3, iclass 19, count 0 2006.201.13:38:52.64#ibcon#read 3, iclass 19, count 0 2006.201.13:38:52.64#ibcon#about to read 4, iclass 19, count 0 2006.201.13:38:52.64#ibcon#read 4, iclass 19, count 0 2006.201.13:38:52.64#ibcon#about to read 5, iclass 19, count 0 2006.201.13:38:52.64#ibcon#read 5, iclass 19, count 0 2006.201.13:38:52.64#ibcon#about to read 6, iclass 19, count 0 2006.201.13:38:52.64#ibcon#read 6, iclass 19, count 0 2006.201.13:38:52.64#ibcon#end of sib2, iclass 19, count 0 2006.201.13:38:52.64#ibcon#*after write, iclass 19, count 0 2006.201.13:38:52.64#ibcon#*before return 0, iclass 19, count 0 2006.201.13:38:52.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:52.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:38:52.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:38:52.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:38:52.64$vck44/vb=1,4 2006.201.13:38:52.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.13:38:52.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.13:38:52.64#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:52.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:52.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:52.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:52.64#ibcon#enter wrdev, iclass 21, count 2 2006.201.13:38:52.64#ibcon#first serial, iclass 21, count 2 2006.201.13:38:52.64#ibcon#enter sib2, iclass 21, count 2 2006.201.13:38:52.64#ibcon#flushed, iclass 21, count 2 2006.201.13:38:52.64#ibcon#about to write, iclass 21, count 2 2006.201.13:38:52.64#ibcon#wrote, iclass 21, count 2 2006.201.13:38:52.64#ibcon#about to read 3, iclass 21, count 2 2006.201.13:38:52.66#ibcon#read 3, iclass 21, count 2 2006.201.13:38:52.66#ibcon#about to read 4, iclass 21, count 2 2006.201.13:38:52.66#ibcon#read 4, iclass 21, count 2 2006.201.13:38:52.66#ibcon#about to read 5, iclass 21, count 2 2006.201.13:38:52.66#ibcon#read 5, iclass 21, count 2 2006.201.13:38:52.66#ibcon#about to read 6, iclass 21, count 2 2006.201.13:38:52.66#ibcon#read 6, iclass 21, count 2 2006.201.13:38:52.66#ibcon#end of sib2, iclass 21, count 2 2006.201.13:38:52.66#ibcon#*mode == 0, iclass 21, count 2 2006.201.13:38:52.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.13:38:52.66#ibcon#[27=AT01-04\r\n] 2006.201.13:38:52.66#ibcon#*before write, iclass 21, count 2 2006.201.13:38:52.66#ibcon#enter sib2, iclass 21, count 2 2006.201.13:38:52.66#ibcon#flushed, iclass 21, count 2 2006.201.13:38:52.66#ibcon#about to write, iclass 21, count 2 2006.201.13:38:52.66#ibcon#wrote, iclass 21, count 2 2006.201.13:38:52.66#ibcon#about to read 3, iclass 21, count 2 2006.201.13:38:52.69#ibcon#read 3, iclass 21, count 2 2006.201.13:38:52.69#ibcon#about to read 4, iclass 21, count 2 2006.201.13:38:52.69#ibcon#read 4, iclass 21, count 2 2006.201.13:38:52.69#ibcon#about to read 5, iclass 21, count 2 2006.201.13:38:52.69#ibcon#read 5, iclass 21, count 2 2006.201.13:38:52.69#ibcon#about to read 6, iclass 21, count 2 2006.201.13:38:52.69#ibcon#read 6, iclass 21, count 2 2006.201.13:38:52.69#ibcon#end of sib2, iclass 21, count 2 2006.201.13:38:52.69#ibcon#*after write, iclass 21, count 2 2006.201.13:38:52.69#ibcon#*before return 0, iclass 21, count 2 2006.201.13:38:52.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:52.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:38:52.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.13:38:52.69#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:52.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:52.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:52.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:52.81#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:38:52.81#ibcon#first serial, iclass 21, count 0 2006.201.13:38:52.81#ibcon#enter sib2, iclass 21, count 0 2006.201.13:38:52.81#ibcon#flushed, iclass 21, count 0 2006.201.13:38:52.81#ibcon#about to write, iclass 21, count 0 2006.201.13:38:52.81#ibcon#wrote, iclass 21, count 0 2006.201.13:38:52.81#ibcon#about to read 3, iclass 21, count 0 2006.201.13:38:52.83#ibcon#read 3, iclass 21, count 0 2006.201.13:38:52.83#ibcon#about to read 4, iclass 21, count 0 2006.201.13:38:52.83#ibcon#read 4, iclass 21, count 0 2006.201.13:38:52.83#ibcon#about to read 5, iclass 21, count 0 2006.201.13:38:52.83#ibcon#read 5, iclass 21, count 0 2006.201.13:38:52.83#ibcon#about to read 6, iclass 21, count 0 2006.201.13:38:52.83#ibcon#read 6, iclass 21, count 0 2006.201.13:38:52.83#ibcon#end of sib2, iclass 21, count 0 2006.201.13:38:52.83#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:38:52.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:38:52.83#ibcon#[27=USB\r\n] 2006.201.13:38:52.83#ibcon#*before write, iclass 21, count 0 2006.201.13:38:52.83#ibcon#enter sib2, iclass 21, count 0 2006.201.13:38:52.83#ibcon#flushed, iclass 21, count 0 2006.201.13:38:52.83#ibcon#about to write, iclass 21, count 0 2006.201.13:38:52.83#ibcon#wrote, iclass 21, count 0 2006.201.13:38:52.83#ibcon#about to read 3, iclass 21, count 0 2006.201.13:38:52.86#ibcon#read 3, iclass 21, count 0 2006.201.13:38:52.86#ibcon#about to read 4, iclass 21, count 0 2006.201.13:38:52.86#ibcon#read 4, iclass 21, count 0 2006.201.13:38:52.86#ibcon#about to read 5, iclass 21, count 0 2006.201.13:38:52.86#ibcon#read 5, iclass 21, count 0 2006.201.13:38:52.86#ibcon#about to read 6, iclass 21, count 0 2006.201.13:38:52.86#ibcon#read 6, iclass 21, count 0 2006.201.13:38:52.86#ibcon#end of sib2, iclass 21, count 0 2006.201.13:38:52.86#ibcon#*after write, iclass 21, count 0 2006.201.13:38:52.86#ibcon#*before return 0, iclass 21, count 0 2006.201.13:38:52.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:52.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:38:52.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:38:52.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:38:52.86$vck44/vblo=2,634.99 2006.201.13:38:52.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.13:38:52.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.13:38:52.86#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:52.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:52.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:52.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:52.86#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:38:52.86#ibcon#first serial, iclass 23, count 0 2006.201.13:38:52.86#ibcon#enter sib2, iclass 23, count 0 2006.201.13:38:52.86#ibcon#flushed, iclass 23, count 0 2006.201.13:38:52.86#ibcon#about to write, iclass 23, count 0 2006.201.13:38:52.86#ibcon#wrote, iclass 23, count 0 2006.201.13:38:52.86#ibcon#about to read 3, iclass 23, count 0 2006.201.13:38:52.88#ibcon#read 3, iclass 23, count 0 2006.201.13:38:52.88#ibcon#about to read 4, iclass 23, count 0 2006.201.13:38:52.88#ibcon#read 4, iclass 23, count 0 2006.201.13:38:52.88#ibcon#about to read 5, iclass 23, count 0 2006.201.13:38:52.88#ibcon#read 5, iclass 23, count 0 2006.201.13:38:52.88#ibcon#about to read 6, iclass 23, count 0 2006.201.13:38:52.88#ibcon#read 6, iclass 23, count 0 2006.201.13:38:52.88#ibcon#end of sib2, iclass 23, count 0 2006.201.13:38:52.88#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:38:52.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:38:52.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:38:52.88#ibcon#*before write, iclass 23, count 0 2006.201.13:38:52.88#ibcon#enter sib2, iclass 23, count 0 2006.201.13:38:52.88#ibcon#flushed, iclass 23, count 0 2006.201.13:38:52.88#ibcon#about to write, iclass 23, count 0 2006.201.13:38:52.88#ibcon#wrote, iclass 23, count 0 2006.201.13:38:52.88#ibcon#about to read 3, iclass 23, count 0 2006.201.13:38:52.92#ibcon#read 3, iclass 23, count 0 2006.201.13:38:52.92#ibcon#about to read 4, iclass 23, count 0 2006.201.13:38:52.92#ibcon#read 4, iclass 23, count 0 2006.201.13:38:52.92#ibcon#about to read 5, iclass 23, count 0 2006.201.13:38:52.92#ibcon#read 5, iclass 23, count 0 2006.201.13:38:52.92#ibcon#about to read 6, iclass 23, count 0 2006.201.13:38:52.92#ibcon#read 6, iclass 23, count 0 2006.201.13:38:52.92#ibcon#end of sib2, iclass 23, count 0 2006.201.13:38:52.92#ibcon#*after write, iclass 23, count 0 2006.201.13:38:52.92#ibcon#*before return 0, iclass 23, count 0 2006.201.13:38:52.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:52.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:38:52.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:38:52.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:38:52.92$vck44/vb=2,5 2006.201.13:38:52.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.13:38:52.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.13:38:52.92#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:52.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:52.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:52.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:52.98#ibcon#enter wrdev, iclass 25, count 2 2006.201.13:38:52.98#ibcon#first serial, iclass 25, count 2 2006.201.13:38:52.98#ibcon#enter sib2, iclass 25, count 2 2006.201.13:38:52.98#ibcon#flushed, iclass 25, count 2 2006.201.13:38:52.98#ibcon#about to write, iclass 25, count 2 2006.201.13:38:52.98#ibcon#wrote, iclass 25, count 2 2006.201.13:38:52.98#ibcon#about to read 3, iclass 25, count 2 2006.201.13:38:53.00#ibcon#read 3, iclass 25, count 2 2006.201.13:38:53.00#ibcon#about to read 4, iclass 25, count 2 2006.201.13:38:53.00#ibcon#read 4, iclass 25, count 2 2006.201.13:38:53.00#ibcon#about to read 5, iclass 25, count 2 2006.201.13:38:53.00#ibcon#read 5, iclass 25, count 2 2006.201.13:38:53.00#ibcon#about to read 6, iclass 25, count 2 2006.201.13:38:53.00#ibcon#read 6, iclass 25, count 2 2006.201.13:38:53.00#ibcon#end of sib2, iclass 25, count 2 2006.201.13:38:53.00#ibcon#*mode == 0, iclass 25, count 2 2006.201.13:38:53.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.13:38:53.00#ibcon#[27=AT02-05\r\n] 2006.201.13:38:53.00#ibcon#*before write, iclass 25, count 2 2006.201.13:38:53.00#ibcon#enter sib2, iclass 25, count 2 2006.201.13:38:53.00#ibcon#flushed, iclass 25, count 2 2006.201.13:38:53.00#ibcon#about to write, iclass 25, count 2 2006.201.13:38:53.00#ibcon#wrote, iclass 25, count 2 2006.201.13:38:53.00#ibcon#about to read 3, iclass 25, count 2 2006.201.13:38:53.03#ibcon#read 3, iclass 25, count 2 2006.201.13:38:53.03#ibcon#about to read 4, iclass 25, count 2 2006.201.13:38:53.03#ibcon#read 4, iclass 25, count 2 2006.201.13:38:53.03#ibcon#about to read 5, iclass 25, count 2 2006.201.13:38:53.03#ibcon#read 5, iclass 25, count 2 2006.201.13:38:53.03#ibcon#about to read 6, iclass 25, count 2 2006.201.13:38:53.03#ibcon#read 6, iclass 25, count 2 2006.201.13:38:53.03#ibcon#end of sib2, iclass 25, count 2 2006.201.13:38:53.03#ibcon#*after write, iclass 25, count 2 2006.201.13:38:53.03#ibcon#*before return 0, iclass 25, count 2 2006.201.13:38:53.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:53.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:38:53.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.13:38:53.03#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:53.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:53.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:53.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:53.15#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:38:53.15#ibcon#first serial, iclass 25, count 0 2006.201.13:38:53.15#ibcon#enter sib2, iclass 25, count 0 2006.201.13:38:53.15#ibcon#flushed, iclass 25, count 0 2006.201.13:38:53.15#ibcon#about to write, iclass 25, count 0 2006.201.13:38:53.15#ibcon#wrote, iclass 25, count 0 2006.201.13:38:53.15#ibcon#about to read 3, iclass 25, count 0 2006.201.13:38:53.17#ibcon#read 3, iclass 25, count 0 2006.201.13:38:53.17#ibcon#about to read 4, iclass 25, count 0 2006.201.13:38:53.17#ibcon#read 4, iclass 25, count 0 2006.201.13:38:53.17#ibcon#about to read 5, iclass 25, count 0 2006.201.13:38:53.17#ibcon#read 5, iclass 25, count 0 2006.201.13:38:53.17#ibcon#about to read 6, iclass 25, count 0 2006.201.13:38:53.17#ibcon#read 6, iclass 25, count 0 2006.201.13:38:53.17#ibcon#end of sib2, iclass 25, count 0 2006.201.13:38:53.17#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:38:53.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:38:53.17#ibcon#[27=USB\r\n] 2006.201.13:38:53.17#ibcon#*before write, iclass 25, count 0 2006.201.13:38:53.17#ibcon#enter sib2, iclass 25, count 0 2006.201.13:38:53.17#ibcon#flushed, iclass 25, count 0 2006.201.13:38:53.17#ibcon#about to write, iclass 25, count 0 2006.201.13:38:53.17#ibcon#wrote, iclass 25, count 0 2006.201.13:38:53.17#ibcon#about to read 3, iclass 25, count 0 2006.201.13:38:53.20#ibcon#read 3, iclass 25, count 0 2006.201.13:38:53.20#ibcon#about to read 4, iclass 25, count 0 2006.201.13:38:53.20#ibcon#read 4, iclass 25, count 0 2006.201.13:38:53.20#ibcon#about to read 5, iclass 25, count 0 2006.201.13:38:53.20#ibcon#read 5, iclass 25, count 0 2006.201.13:38:53.20#ibcon#about to read 6, iclass 25, count 0 2006.201.13:38:53.20#ibcon#read 6, iclass 25, count 0 2006.201.13:38:53.20#ibcon#end of sib2, iclass 25, count 0 2006.201.13:38:53.20#ibcon#*after write, iclass 25, count 0 2006.201.13:38:53.20#ibcon#*before return 0, iclass 25, count 0 2006.201.13:38:53.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:53.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:38:53.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:38:53.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:38:53.20$vck44/vblo=3,649.99 2006.201.13:38:53.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.13:38:53.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.13:38:53.20#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:53.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:38:53.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:38:53.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:38:53.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:38:53.20#ibcon#first serial, iclass 27, count 0 2006.201.13:38:53.20#ibcon#enter sib2, iclass 27, count 0 2006.201.13:38:53.20#ibcon#flushed, iclass 27, count 0 2006.201.13:38:53.20#ibcon#about to write, iclass 27, count 0 2006.201.13:38:53.20#ibcon#wrote, iclass 27, count 0 2006.201.13:38:53.20#ibcon#about to read 3, iclass 27, count 0 2006.201.13:38:53.22#ibcon#read 3, iclass 27, count 0 2006.201.13:38:53.22#ibcon#about to read 4, iclass 27, count 0 2006.201.13:38:53.22#ibcon#read 4, iclass 27, count 0 2006.201.13:38:53.22#ibcon#about to read 5, iclass 27, count 0 2006.201.13:38:53.22#ibcon#read 5, iclass 27, count 0 2006.201.13:38:53.22#ibcon#about to read 6, iclass 27, count 0 2006.201.13:38:53.22#ibcon#read 6, iclass 27, count 0 2006.201.13:38:53.22#ibcon#end of sib2, iclass 27, count 0 2006.201.13:38:53.22#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:38:53.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:38:53.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:38:53.22#ibcon#*before write, iclass 27, count 0 2006.201.13:38:53.22#ibcon#enter sib2, iclass 27, count 0 2006.201.13:38:53.22#ibcon#flushed, iclass 27, count 0 2006.201.13:38:53.22#ibcon#about to write, iclass 27, count 0 2006.201.13:38:53.22#ibcon#wrote, iclass 27, count 0 2006.201.13:38:53.22#ibcon#about to read 3, iclass 27, count 0 2006.201.13:38:53.27#ibcon#read 3, iclass 27, count 0 2006.201.13:38:53.27#ibcon#about to read 4, iclass 27, count 0 2006.201.13:38:53.27#ibcon#read 4, iclass 27, count 0 2006.201.13:38:53.27#ibcon#about to read 5, iclass 27, count 0 2006.201.13:38:53.27#ibcon#read 5, iclass 27, count 0 2006.201.13:38:53.27#ibcon#about to read 6, iclass 27, count 0 2006.201.13:38:53.27#ibcon#read 6, iclass 27, count 0 2006.201.13:38:53.27#ibcon#end of sib2, iclass 27, count 0 2006.201.13:38:53.27#ibcon#*after write, iclass 27, count 0 2006.201.13:38:53.27#ibcon#*before return 0, iclass 27, count 0 2006.201.13:38:53.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:38:53.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:38:53.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:38:53.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:38:53.27$vck44/vb=3,4 2006.201.13:38:53.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.13:38:53.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.13:38:53.27#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:53.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:38:53.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:38:53.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:38:53.32#ibcon#enter wrdev, iclass 29, count 2 2006.201.13:38:53.32#ibcon#first serial, iclass 29, count 2 2006.201.13:38:53.32#ibcon#enter sib2, iclass 29, count 2 2006.201.13:38:53.32#ibcon#flushed, iclass 29, count 2 2006.201.13:38:53.32#ibcon#about to write, iclass 29, count 2 2006.201.13:38:53.32#ibcon#wrote, iclass 29, count 2 2006.201.13:38:53.32#ibcon#about to read 3, iclass 29, count 2 2006.201.13:38:53.34#ibcon#read 3, iclass 29, count 2 2006.201.13:38:53.34#ibcon#about to read 4, iclass 29, count 2 2006.201.13:38:53.34#ibcon#read 4, iclass 29, count 2 2006.201.13:38:53.34#ibcon#about to read 5, iclass 29, count 2 2006.201.13:38:53.34#ibcon#read 5, iclass 29, count 2 2006.201.13:38:53.34#ibcon#about to read 6, iclass 29, count 2 2006.201.13:38:53.34#ibcon#read 6, iclass 29, count 2 2006.201.13:38:53.34#ibcon#end of sib2, iclass 29, count 2 2006.201.13:38:53.34#ibcon#*mode == 0, iclass 29, count 2 2006.201.13:38:53.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.13:38:53.34#ibcon#[27=AT03-04\r\n] 2006.201.13:38:53.34#ibcon#*before write, iclass 29, count 2 2006.201.13:38:53.34#ibcon#enter sib2, iclass 29, count 2 2006.201.13:38:53.34#ibcon#flushed, iclass 29, count 2 2006.201.13:38:53.34#ibcon#about to write, iclass 29, count 2 2006.201.13:38:53.34#ibcon#wrote, iclass 29, count 2 2006.201.13:38:53.34#ibcon#about to read 3, iclass 29, count 2 2006.201.13:38:53.37#ibcon#read 3, iclass 29, count 2 2006.201.13:38:53.37#ibcon#about to read 4, iclass 29, count 2 2006.201.13:38:53.37#ibcon#read 4, iclass 29, count 2 2006.201.13:38:53.37#ibcon#about to read 5, iclass 29, count 2 2006.201.13:38:53.37#ibcon#read 5, iclass 29, count 2 2006.201.13:38:53.37#ibcon#about to read 6, iclass 29, count 2 2006.201.13:38:53.37#ibcon#read 6, iclass 29, count 2 2006.201.13:38:53.37#ibcon#end of sib2, iclass 29, count 2 2006.201.13:38:53.37#ibcon#*after write, iclass 29, count 2 2006.201.13:38:53.37#ibcon#*before return 0, iclass 29, count 2 2006.201.13:38:53.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:38:53.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:38:53.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.13:38:53.37#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:53.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:38:53.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:38:53.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:38:53.49#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:38:53.49#ibcon#first serial, iclass 29, count 0 2006.201.13:38:53.49#ibcon#enter sib2, iclass 29, count 0 2006.201.13:38:53.49#ibcon#flushed, iclass 29, count 0 2006.201.13:38:53.49#ibcon#about to write, iclass 29, count 0 2006.201.13:38:53.49#ibcon#wrote, iclass 29, count 0 2006.201.13:38:53.49#ibcon#about to read 3, iclass 29, count 0 2006.201.13:38:53.51#ibcon#read 3, iclass 29, count 0 2006.201.13:38:53.51#ibcon#about to read 4, iclass 29, count 0 2006.201.13:38:53.51#ibcon#read 4, iclass 29, count 0 2006.201.13:38:53.51#ibcon#about to read 5, iclass 29, count 0 2006.201.13:38:53.51#ibcon#read 5, iclass 29, count 0 2006.201.13:38:53.51#ibcon#about to read 6, iclass 29, count 0 2006.201.13:38:53.51#ibcon#read 6, iclass 29, count 0 2006.201.13:38:53.51#ibcon#end of sib2, iclass 29, count 0 2006.201.13:38:53.51#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:38:53.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:38:53.51#ibcon#[27=USB\r\n] 2006.201.13:38:53.51#ibcon#*before write, iclass 29, count 0 2006.201.13:38:53.51#ibcon#enter sib2, iclass 29, count 0 2006.201.13:38:53.51#ibcon#flushed, iclass 29, count 0 2006.201.13:38:53.51#ibcon#about to write, iclass 29, count 0 2006.201.13:38:53.51#ibcon#wrote, iclass 29, count 0 2006.201.13:38:53.51#ibcon#about to read 3, iclass 29, count 0 2006.201.13:38:53.54#ibcon#read 3, iclass 29, count 0 2006.201.13:38:53.54#ibcon#about to read 4, iclass 29, count 0 2006.201.13:38:53.54#ibcon#read 4, iclass 29, count 0 2006.201.13:38:53.54#ibcon#about to read 5, iclass 29, count 0 2006.201.13:38:53.54#ibcon#read 5, iclass 29, count 0 2006.201.13:38:53.54#ibcon#about to read 6, iclass 29, count 0 2006.201.13:38:53.54#ibcon#read 6, iclass 29, count 0 2006.201.13:38:53.54#ibcon#end of sib2, iclass 29, count 0 2006.201.13:38:53.54#ibcon#*after write, iclass 29, count 0 2006.201.13:38:53.54#ibcon#*before return 0, iclass 29, count 0 2006.201.13:38:53.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:38:53.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:38:53.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:38:53.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:38:53.54$vck44/vblo=4,679.99 2006.201.13:38:53.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.13:38:53.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.13:38:53.54#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:53.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:53.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:53.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:53.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:38:53.54#ibcon#first serial, iclass 31, count 0 2006.201.13:38:53.54#ibcon#enter sib2, iclass 31, count 0 2006.201.13:38:53.54#ibcon#flushed, iclass 31, count 0 2006.201.13:38:53.54#ibcon#about to write, iclass 31, count 0 2006.201.13:38:53.54#ibcon#wrote, iclass 31, count 0 2006.201.13:38:53.54#ibcon#about to read 3, iclass 31, count 0 2006.201.13:38:53.56#ibcon#read 3, iclass 31, count 0 2006.201.13:38:53.56#ibcon#about to read 4, iclass 31, count 0 2006.201.13:38:53.56#ibcon#read 4, iclass 31, count 0 2006.201.13:38:53.56#ibcon#about to read 5, iclass 31, count 0 2006.201.13:38:53.56#ibcon#read 5, iclass 31, count 0 2006.201.13:38:53.56#ibcon#about to read 6, iclass 31, count 0 2006.201.13:38:53.56#ibcon#read 6, iclass 31, count 0 2006.201.13:38:53.56#ibcon#end of sib2, iclass 31, count 0 2006.201.13:38:53.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:38:53.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:38:53.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:38:53.56#ibcon#*before write, iclass 31, count 0 2006.201.13:38:53.56#ibcon#enter sib2, iclass 31, count 0 2006.201.13:38:53.56#ibcon#flushed, iclass 31, count 0 2006.201.13:38:53.56#ibcon#about to write, iclass 31, count 0 2006.201.13:38:53.56#ibcon#wrote, iclass 31, count 0 2006.201.13:38:53.56#ibcon#about to read 3, iclass 31, count 0 2006.201.13:38:53.60#ibcon#read 3, iclass 31, count 0 2006.201.13:38:53.60#ibcon#about to read 4, iclass 31, count 0 2006.201.13:38:53.60#ibcon#read 4, iclass 31, count 0 2006.201.13:38:53.60#ibcon#about to read 5, iclass 31, count 0 2006.201.13:38:53.60#ibcon#read 5, iclass 31, count 0 2006.201.13:38:53.60#ibcon#about to read 6, iclass 31, count 0 2006.201.13:38:53.60#ibcon#read 6, iclass 31, count 0 2006.201.13:38:53.60#ibcon#end of sib2, iclass 31, count 0 2006.201.13:38:53.60#ibcon#*after write, iclass 31, count 0 2006.201.13:38:53.60#ibcon#*before return 0, iclass 31, count 0 2006.201.13:38:53.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:53.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:38:53.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:38:53.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:38:53.60$vck44/vb=4,5 2006.201.13:38:53.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.13:38:53.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.13:38:53.60#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:53.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:53.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:53.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:53.66#ibcon#enter wrdev, iclass 33, count 2 2006.201.13:38:53.66#ibcon#first serial, iclass 33, count 2 2006.201.13:38:53.66#ibcon#enter sib2, iclass 33, count 2 2006.201.13:38:53.66#ibcon#flushed, iclass 33, count 2 2006.201.13:38:53.66#ibcon#about to write, iclass 33, count 2 2006.201.13:38:53.66#ibcon#wrote, iclass 33, count 2 2006.201.13:38:53.66#ibcon#about to read 3, iclass 33, count 2 2006.201.13:38:53.68#ibcon#read 3, iclass 33, count 2 2006.201.13:38:53.68#ibcon#about to read 4, iclass 33, count 2 2006.201.13:38:53.68#ibcon#read 4, iclass 33, count 2 2006.201.13:38:53.68#ibcon#about to read 5, iclass 33, count 2 2006.201.13:38:53.68#ibcon#read 5, iclass 33, count 2 2006.201.13:38:53.68#ibcon#about to read 6, iclass 33, count 2 2006.201.13:38:53.68#ibcon#read 6, iclass 33, count 2 2006.201.13:38:53.68#ibcon#end of sib2, iclass 33, count 2 2006.201.13:38:53.68#ibcon#*mode == 0, iclass 33, count 2 2006.201.13:38:53.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.13:38:53.68#ibcon#[27=AT04-05\r\n] 2006.201.13:38:53.68#ibcon#*before write, iclass 33, count 2 2006.201.13:38:53.68#ibcon#enter sib2, iclass 33, count 2 2006.201.13:38:53.68#ibcon#flushed, iclass 33, count 2 2006.201.13:38:53.68#ibcon#about to write, iclass 33, count 2 2006.201.13:38:53.68#ibcon#wrote, iclass 33, count 2 2006.201.13:38:53.68#ibcon#about to read 3, iclass 33, count 2 2006.201.13:38:53.71#ibcon#read 3, iclass 33, count 2 2006.201.13:38:53.71#ibcon#about to read 4, iclass 33, count 2 2006.201.13:38:53.71#ibcon#read 4, iclass 33, count 2 2006.201.13:38:53.71#ibcon#about to read 5, iclass 33, count 2 2006.201.13:38:53.71#ibcon#read 5, iclass 33, count 2 2006.201.13:38:53.71#ibcon#about to read 6, iclass 33, count 2 2006.201.13:38:53.71#ibcon#read 6, iclass 33, count 2 2006.201.13:38:53.71#ibcon#end of sib2, iclass 33, count 2 2006.201.13:38:53.71#ibcon#*after write, iclass 33, count 2 2006.201.13:38:53.71#ibcon#*before return 0, iclass 33, count 2 2006.201.13:38:53.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:53.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:38:53.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.13:38:53.71#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:53.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:53.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:53.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:53.83#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:38:53.83#ibcon#first serial, iclass 33, count 0 2006.201.13:38:53.83#ibcon#enter sib2, iclass 33, count 0 2006.201.13:38:53.83#ibcon#flushed, iclass 33, count 0 2006.201.13:38:53.83#ibcon#about to write, iclass 33, count 0 2006.201.13:38:53.83#ibcon#wrote, iclass 33, count 0 2006.201.13:38:53.83#ibcon#about to read 3, iclass 33, count 0 2006.201.13:38:53.85#ibcon#read 3, iclass 33, count 0 2006.201.13:38:53.85#ibcon#about to read 4, iclass 33, count 0 2006.201.13:38:53.85#ibcon#read 4, iclass 33, count 0 2006.201.13:38:53.85#ibcon#about to read 5, iclass 33, count 0 2006.201.13:38:53.85#ibcon#read 5, iclass 33, count 0 2006.201.13:38:53.85#ibcon#about to read 6, iclass 33, count 0 2006.201.13:38:53.85#ibcon#read 6, iclass 33, count 0 2006.201.13:38:53.85#ibcon#end of sib2, iclass 33, count 0 2006.201.13:38:53.85#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:38:53.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:38:53.85#ibcon#[27=USB\r\n] 2006.201.13:38:53.85#ibcon#*before write, iclass 33, count 0 2006.201.13:38:53.85#ibcon#enter sib2, iclass 33, count 0 2006.201.13:38:53.85#ibcon#flushed, iclass 33, count 0 2006.201.13:38:53.85#ibcon#about to write, iclass 33, count 0 2006.201.13:38:53.85#ibcon#wrote, iclass 33, count 0 2006.201.13:38:53.85#ibcon#about to read 3, iclass 33, count 0 2006.201.13:38:53.88#ibcon#read 3, iclass 33, count 0 2006.201.13:38:53.88#ibcon#about to read 4, iclass 33, count 0 2006.201.13:38:53.88#ibcon#read 4, iclass 33, count 0 2006.201.13:38:53.88#ibcon#about to read 5, iclass 33, count 0 2006.201.13:38:53.88#ibcon#read 5, iclass 33, count 0 2006.201.13:38:53.88#ibcon#about to read 6, iclass 33, count 0 2006.201.13:38:53.88#ibcon#read 6, iclass 33, count 0 2006.201.13:38:53.88#ibcon#end of sib2, iclass 33, count 0 2006.201.13:38:53.88#ibcon#*after write, iclass 33, count 0 2006.201.13:38:53.88#ibcon#*before return 0, iclass 33, count 0 2006.201.13:38:53.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:53.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:38:53.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:38:53.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:38:53.88$vck44/vblo=5,709.99 2006.201.13:38:53.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.13:38:53.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.13:38:53.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:53.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:53.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:53.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:53.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:38:53.88#ibcon#first serial, iclass 35, count 0 2006.201.13:38:53.88#ibcon#enter sib2, iclass 35, count 0 2006.201.13:38:53.88#ibcon#flushed, iclass 35, count 0 2006.201.13:38:53.88#ibcon#about to write, iclass 35, count 0 2006.201.13:38:53.88#ibcon#wrote, iclass 35, count 0 2006.201.13:38:53.88#ibcon#about to read 3, iclass 35, count 0 2006.201.13:38:53.90#ibcon#read 3, iclass 35, count 0 2006.201.13:38:53.90#ibcon#about to read 4, iclass 35, count 0 2006.201.13:38:53.90#ibcon#read 4, iclass 35, count 0 2006.201.13:38:53.90#ibcon#about to read 5, iclass 35, count 0 2006.201.13:38:53.90#ibcon#read 5, iclass 35, count 0 2006.201.13:38:53.90#ibcon#about to read 6, iclass 35, count 0 2006.201.13:38:53.90#ibcon#read 6, iclass 35, count 0 2006.201.13:38:53.90#ibcon#end of sib2, iclass 35, count 0 2006.201.13:38:53.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:38:53.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:38:53.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:38:53.90#ibcon#*before write, iclass 35, count 0 2006.201.13:38:53.90#ibcon#enter sib2, iclass 35, count 0 2006.201.13:38:53.90#ibcon#flushed, iclass 35, count 0 2006.201.13:38:53.90#ibcon#about to write, iclass 35, count 0 2006.201.13:38:53.90#ibcon#wrote, iclass 35, count 0 2006.201.13:38:53.90#ibcon#about to read 3, iclass 35, count 0 2006.201.13:38:53.95#ibcon#read 3, iclass 35, count 0 2006.201.13:38:53.95#ibcon#about to read 4, iclass 35, count 0 2006.201.13:38:53.95#ibcon#read 4, iclass 35, count 0 2006.201.13:38:53.95#ibcon#about to read 5, iclass 35, count 0 2006.201.13:38:53.95#ibcon#read 5, iclass 35, count 0 2006.201.13:38:53.95#ibcon#about to read 6, iclass 35, count 0 2006.201.13:38:53.95#ibcon#read 6, iclass 35, count 0 2006.201.13:38:53.95#ibcon#end of sib2, iclass 35, count 0 2006.201.13:38:53.95#ibcon#*after write, iclass 35, count 0 2006.201.13:38:53.95#ibcon#*before return 0, iclass 35, count 0 2006.201.13:38:53.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:53.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:38:53.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:38:53.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:38:53.95$vck44/vb=5,4 2006.201.13:38:53.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.13:38:53.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.13:38:53.95#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:53.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:54.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:54.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:54.00#ibcon#enter wrdev, iclass 37, count 2 2006.201.13:38:54.00#ibcon#first serial, iclass 37, count 2 2006.201.13:38:54.00#ibcon#enter sib2, iclass 37, count 2 2006.201.13:38:54.00#ibcon#flushed, iclass 37, count 2 2006.201.13:38:54.00#ibcon#about to write, iclass 37, count 2 2006.201.13:38:54.00#ibcon#wrote, iclass 37, count 2 2006.201.13:38:54.00#ibcon#about to read 3, iclass 37, count 2 2006.201.13:38:54.02#ibcon#read 3, iclass 37, count 2 2006.201.13:38:54.02#ibcon#about to read 4, iclass 37, count 2 2006.201.13:38:54.02#ibcon#read 4, iclass 37, count 2 2006.201.13:38:54.02#ibcon#about to read 5, iclass 37, count 2 2006.201.13:38:54.02#ibcon#read 5, iclass 37, count 2 2006.201.13:38:54.02#ibcon#about to read 6, iclass 37, count 2 2006.201.13:38:54.02#ibcon#read 6, iclass 37, count 2 2006.201.13:38:54.02#ibcon#end of sib2, iclass 37, count 2 2006.201.13:38:54.02#ibcon#*mode == 0, iclass 37, count 2 2006.201.13:38:54.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.13:38:54.02#ibcon#[27=AT05-04\r\n] 2006.201.13:38:54.02#ibcon#*before write, iclass 37, count 2 2006.201.13:38:54.02#ibcon#enter sib2, iclass 37, count 2 2006.201.13:38:54.02#ibcon#flushed, iclass 37, count 2 2006.201.13:38:54.02#ibcon#about to write, iclass 37, count 2 2006.201.13:38:54.02#ibcon#wrote, iclass 37, count 2 2006.201.13:38:54.02#ibcon#about to read 3, iclass 37, count 2 2006.201.13:38:54.05#ibcon#read 3, iclass 37, count 2 2006.201.13:38:54.05#ibcon#about to read 4, iclass 37, count 2 2006.201.13:38:54.05#ibcon#read 4, iclass 37, count 2 2006.201.13:38:54.05#ibcon#about to read 5, iclass 37, count 2 2006.201.13:38:54.05#ibcon#read 5, iclass 37, count 2 2006.201.13:38:54.05#ibcon#about to read 6, iclass 37, count 2 2006.201.13:38:54.05#ibcon#read 6, iclass 37, count 2 2006.201.13:38:54.05#ibcon#end of sib2, iclass 37, count 2 2006.201.13:38:54.05#ibcon#*after write, iclass 37, count 2 2006.201.13:38:54.05#ibcon#*before return 0, iclass 37, count 2 2006.201.13:38:54.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:54.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:38:54.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.13:38:54.05#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:54.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:54.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:54.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:54.17#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:38:54.17#ibcon#first serial, iclass 37, count 0 2006.201.13:38:54.17#ibcon#enter sib2, iclass 37, count 0 2006.201.13:38:54.17#ibcon#flushed, iclass 37, count 0 2006.201.13:38:54.17#ibcon#about to write, iclass 37, count 0 2006.201.13:38:54.17#ibcon#wrote, iclass 37, count 0 2006.201.13:38:54.17#ibcon#about to read 3, iclass 37, count 0 2006.201.13:38:54.19#ibcon#read 3, iclass 37, count 0 2006.201.13:38:54.19#ibcon#about to read 4, iclass 37, count 0 2006.201.13:38:54.19#ibcon#read 4, iclass 37, count 0 2006.201.13:38:54.19#ibcon#about to read 5, iclass 37, count 0 2006.201.13:38:54.19#ibcon#read 5, iclass 37, count 0 2006.201.13:38:54.19#ibcon#about to read 6, iclass 37, count 0 2006.201.13:38:54.19#ibcon#read 6, iclass 37, count 0 2006.201.13:38:54.19#ibcon#end of sib2, iclass 37, count 0 2006.201.13:38:54.19#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:38:54.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:38:54.19#ibcon#[27=USB\r\n] 2006.201.13:38:54.19#ibcon#*before write, iclass 37, count 0 2006.201.13:38:54.19#ibcon#enter sib2, iclass 37, count 0 2006.201.13:38:54.19#ibcon#flushed, iclass 37, count 0 2006.201.13:38:54.19#ibcon#about to write, iclass 37, count 0 2006.201.13:38:54.19#ibcon#wrote, iclass 37, count 0 2006.201.13:38:54.19#ibcon#about to read 3, iclass 37, count 0 2006.201.13:38:54.22#ibcon#read 3, iclass 37, count 0 2006.201.13:38:54.22#ibcon#about to read 4, iclass 37, count 0 2006.201.13:38:54.22#ibcon#read 4, iclass 37, count 0 2006.201.13:38:54.22#ibcon#about to read 5, iclass 37, count 0 2006.201.13:38:54.22#ibcon#read 5, iclass 37, count 0 2006.201.13:38:54.22#ibcon#about to read 6, iclass 37, count 0 2006.201.13:38:54.22#ibcon#read 6, iclass 37, count 0 2006.201.13:38:54.22#ibcon#end of sib2, iclass 37, count 0 2006.201.13:38:54.22#ibcon#*after write, iclass 37, count 0 2006.201.13:38:54.22#ibcon#*before return 0, iclass 37, count 0 2006.201.13:38:54.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:54.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:38:54.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:38:54.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:38:54.22$vck44/vblo=6,719.99 2006.201.13:38:54.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.13:38:54.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.13:38:54.22#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:54.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:54.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:54.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:54.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.13:38:54.22#ibcon#first serial, iclass 39, count 0 2006.201.13:38:54.22#ibcon#enter sib2, iclass 39, count 0 2006.201.13:38:54.22#ibcon#flushed, iclass 39, count 0 2006.201.13:38:54.22#ibcon#about to write, iclass 39, count 0 2006.201.13:38:54.22#ibcon#wrote, iclass 39, count 0 2006.201.13:38:54.22#ibcon#about to read 3, iclass 39, count 0 2006.201.13:38:54.24#ibcon#read 3, iclass 39, count 0 2006.201.13:38:54.24#ibcon#about to read 4, iclass 39, count 0 2006.201.13:38:54.24#ibcon#read 4, iclass 39, count 0 2006.201.13:38:54.24#ibcon#about to read 5, iclass 39, count 0 2006.201.13:38:54.24#ibcon#read 5, iclass 39, count 0 2006.201.13:38:54.24#ibcon#about to read 6, iclass 39, count 0 2006.201.13:38:54.24#ibcon#read 6, iclass 39, count 0 2006.201.13:38:54.24#ibcon#end of sib2, iclass 39, count 0 2006.201.13:38:54.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.13:38:54.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.13:38:54.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:38:54.24#ibcon#*before write, iclass 39, count 0 2006.201.13:38:54.24#ibcon#enter sib2, iclass 39, count 0 2006.201.13:38:54.24#ibcon#flushed, iclass 39, count 0 2006.201.13:38:54.24#ibcon#about to write, iclass 39, count 0 2006.201.13:38:54.24#ibcon#wrote, iclass 39, count 0 2006.201.13:38:54.24#ibcon#about to read 3, iclass 39, count 0 2006.201.13:38:54.28#ibcon#read 3, iclass 39, count 0 2006.201.13:38:54.28#ibcon#about to read 4, iclass 39, count 0 2006.201.13:38:54.28#ibcon#read 4, iclass 39, count 0 2006.201.13:38:54.28#ibcon#about to read 5, iclass 39, count 0 2006.201.13:38:54.28#ibcon#read 5, iclass 39, count 0 2006.201.13:38:54.28#ibcon#about to read 6, iclass 39, count 0 2006.201.13:38:54.28#ibcon#read 6, iclass 39, count 0 2006.201.13:38:54.28#ibcon#end of sib2, iclass 39, count 0 2006.201.13:38:54.28#ibcon#*after write, iclass 39, count 0 2006.201.13:38:54.28#ibcon#*before return 0, iclass 39, count 0 2006.201.13:38:54.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:54.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:38:54.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.13:38:54.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.13:38:54.28$vck44/vb=6,4 2006.201.13:38:54.28#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.13:38:54.28#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.13:38:54.28#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:54.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:54.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:54.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:54.34#ibcon#enter wrdev, iclass 2, count 2 2006.201.13:38:54.34#ibcon#first serial, iclass 2, count 2 2006.201.13:38:54.34#ibcon#enter sib2, iclass 2, count 2 2006.201.13:38:54.34#ibcon#flushed, iclass 2, count 2 2006.201.13:38:54.34#ibcon#about to write, iclass 2, count 2 2006.201.13:38:54.34#ibcon#wrote, iclass 2, count 2 2006.201.13:38:54.34#ibcon#about to read 3, iclass 2, count 2 2006.201.13:38:54.36#ibcon#read 3, iclass 2, count 2 2006.201.13:38:54.36#ibcon#about to read 4, iclass 2, count 2 2006.201.13:38:54.36#ibcon#read 4, iclass 2, count 2 2006.201.13:38:54.36#ibcon#about to read 5, iclass 2, count 2 2006.201.13:38:54.36#ibcon#read 5, iclass 2, count 2 2006.201.13:38:54.36#ibcon#about to read 6, iclass 2, count 2 2006.201.13:38:54.36#ibcon#read 6, iclass 2, count 2 2006.201.13:38:54.36#ibcon#end of sib2, iclass 2, count 2 2006.201.13:38:54.36#ibcon#*mode == 0, iclass 2, count 2 2006.201.13:38:54.36#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.13:38:54.36#ibcon#[27=AT06-04\r\n] 2006.201.13:38:54.36#ibcon#*before write, iclass 2, count 2 2006.201.13:38:54.36#ibcon#enter sib2, iclass 2, count 2 2006.201.13:38:54.36#ibcon#flushed, iclass 2, count 2 2006.201.13:38:54.36#ibcon#about to write, iclass 2, count 2 2006.201.13:38:54.36#ibcon#wrote, iclass 2, count 2 2006.201.13:38:54.36#ibcon#about to read 3, iclass 2, count 2 2006.201.13:38:54.39#ibcon#read 3, iclass 2, count 2 2006.201.13:38:54.39#ibcon#about to read 4, iclass 2, count 2 2006.201.13:38:54.39#ibcon#read 4, iclass 2, count 2 2006.201.13:38:54.39#ibcon#about to read 5, iclass 2, count 2 2006.201.13:38:54.39#ibcon#read 5, iclass 2, count 2 2006.201.13:38:54.39#ibcon#about to read 6, iclass 2, count 2 2006.201.13:38:54.39#ibcon#read 6, iclass 2, count 2 2006.201.13:38:54.39#ibcon#end of sib2, iclass 2, count 2 2006.201.13:38:54.39#ibcon#*after write, iclass 2, count 2 2006.201.13:38:54.39#ibcon#*before return 0, iclass 2, count 2 2006.201.13:38:54.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:54.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:38:54.39#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.13:38:54.39#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:54.39#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:54.51#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:54.51#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:54.51#ibcon#enter wrdev, iclass 2, count 0 2006.201.13:38:54.51#ibcon#first serial, iclass 2, count 0 2006.201.13:38:54.51#ibcon#enter sib2, iclass 2, count 0 2006.201.13:38:54.51#ibcon#flushed, iclass 2, count 0 2006.201.13:38:54.51#ibcon#about to write, iclass 2, count 0 2006.201.13:38:54.51#ibcon#wrote, iclass 2, count 0 2006.201.13:38:54.51#ibcon#about to read 3, iclass 2, count 0 2006.201.13:38:54.53#ibcon#read 3, iclass 2, count 0 2006.201.13:38:54.53#ibcon#about to read 4, iclass 2, count 0 2006.201.13:38:54.53#ibcon#read 4, iclass 2, count 0 2006.201.13:38:54.53#ibcon#about to read 5, iclass 2, count 0 2006.201.13:38:54.53#ibcon#read 5, iclass 2, count 0 2006.201.13:38:54.53#ibcon#about to read 6, iclass 2, count 0 2006.201.13:38:54.53#ibcon#read 6, iclass 2, count 0 2006.201.13:38:54.53#ibcon#end of sib2, iclass 2, count 0 2006.201.13:38:54.53#ibcon#*mode == 0, iclass 2, count 0 2006.201.13:38:54.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.13:38:54.53#ibcon#[27=USB\r\n] 2006.201.13:38:54.53#ibcon#*before write, iclass 2, count 0 2006.201.13:38:54.53#ibcon#enter sib2, iclass 2, count 0 2006.201.13:38:54.53#ibcon#flushed, iclass 2, count 0 2006.201.13:38:54.53#ibcon#about to write, iclass 2, count 0 2006.201.13:38:54.53#ibcon#wrote, iclass 2, count 0 2006.201.13:38:54.53#ibcon#about to read 3, iclass 2, count 0 2006.201.13:38:54.56#ibcon#read 3, iclass 2, count 0 2006.201.13:38:54.56#ibcon#about to read 4, iclass 2, count 0 2006.201.13:38:54.56#ibcon#read 4, iclass 2, count 0 2006.201.13:38:54.56#ibcon#about to read 5, iclass 2, count 0 2006.201.13:38:54.56#ibcon#read 5, iclass 2, count 0 2006.201.13:38:54.56#ibcon#about to read 6, iclass 2, count 0 2006.201.13:38:54.56#ibcon#read 6, iclass 2, count 0 2006.201.13:38:54.56#ibcon#end of sib2, iclass 2, count 0 2006.201.13:38:54.56#ibcon#*after write, iclass 2, count 0 2006.201.13:38:54.56#ibcon#*before return 0, iclass 2, count 0 2006.201.13:38:54.56#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:54.56#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:38:54.56#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.13:38:54.56#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.13:38:54.56$vck44/vblo=7,734.99 2006.201.13:38:54.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.13:38:54.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.13:38:54.56#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:54.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:54.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:54.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:54.56#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:38:54.56#ibcon#first serial, iclass 5, count 0 2006.201.13:38:54.56#ibcon#enter sib2, iclass 5, count 0 2006.201.13:38:54.56#ibcon#flushed, iclass 5, count 0 2006.201.13:38:54.56#ibcon#about to write, iclass 5, count 0 2006.201.13:38:54.56#ibcon#wrote, iclass 5, count 0 2006.201.13:38:54.56#ibcon#about to read 3, iclass 5, count 0 2006.201.13:38:54.58#ibcon#read 3, iclass 5, count 0 2006.201.13:38:54.58#ibcon#about to read 4, iclass 5, count 0 2006.201.13:38:54.58#ibcon#read 4, iclass 5, count 0 2006.201.13:38:54.58#ibcon#about to read 5, iclass 5, count 0 2006.201.13:38:54.58#ibcon#read 5, iclass 5, count 0 2006.201.13:38:54.58#ibcon#about to read 6, iclass 5, count 0 2006.201.13:38:54.58#ibcon#read 6, iclass 5, count 0 2006.201.13:38:54.58#ibcon#end of sib2, iclass 5, count 0 2006.201.13:38:54.58#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:38:54.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:38:54.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:38:54.58#ibcon#*before write, iclass 5, count 0 2006.201.13:38:54.58#ibcon#enter sib2, iclass 5, count 0 2006.201.13:38:54.58#ibcon#flushed, iclass 5, count 0 2006.201.13:38:54.58#ibcon#about to write, iclass 5, count 0 2006.201.13:38:54.58#ibcon#wrote, iclass 5, count 0 2006.201.13:38:54.58#ibcon#about to read 3, iclass 5, count 0 2006.201.13:38:54.62#ibcon#read 3, iclass 5, count 0 2006.201.13:38:54.62#ibcon#about to read 4, iclass 5, count 0 2006.201.13:38:54.62#ibcon#read 4, iclass 5, count 0 2006.201.13:38:54.62#ibcon#about to read 5, iclass 5, count 0 2006.201.13:38:54.62#ibcon#read 5, iclass 5, count 0 2006.201.13:38:54.62#ibcon#about to read 6, iclass 5, count 0 2006.201.13:38:54.62#ibcon#read 6, iclass 5, count 0 2006.201.13:38:54.62#ibcon#end of sib2, iclass 5, count 0 2006.201.13:38:54.62#ibcon#*after write, iclass 5, count 0 2006.201.13:38:54.62#ibcon#*before return 0, iclass 5, count 0 2006.201.13:38:54.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:54.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:38:54.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:38:54.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:38:54.62$vck44/vb=7,4 2006.201.13:38:54.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.13:38:54.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.13:38:54.62#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:54.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:54.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:54.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:54.68#ibcon#enter wrdev, iclass 7, count 2 2006.201.13:38:54.68#ibcon#first serial, iclass 7, count 2 2006.201.13:38:54.68#ibcon#enter sib2, iclass 7, count 2 2006.201.13:38:54.68#ibcon#flushed, iclass 7, count 2 2006.201.13:38:54.68#ibcon#about to write, iclass 7, count 2 2006.201.13:38:54.68#ibcon#wrote, iclass 7, count 2 2006.201.13:38:54.68#ibcon#about to read 3, iclass 7, count 2 2006.201.13:38:54.70#ibcon#read 3, iclass 7, count 2 2006.201.13:38:54.70#ibcon#about to read 4, iclass 7, count 2 2006.201.13:38:54.70#ibcon#read 4, iclass 7, count 2 2006.201.13:38:54.70#ibcon#about to read 5, iclass 7, count 2 2006.201.13:38:54.70#ibcon#read 5, iclass 7, count 2 2006.201.13:38:54.70#ibcon#about to read 6, iclass 7, count 2 2006.201.13:38:54.70#ibcon#read 6, iclass 7, count 2 2006.201.13:38:54.70#ibcon#end of sib2, iclass 7, count 2 2006.201.13:38:54.70#ibcon#*mode == 0, iclass 7, count 2 2006.201.13:38:54.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.13:38:54.70#ibcon#[27=AT07-04\r\n] 2006.201.13:38:54.70#ibcon#*before write, iclass 7, count 2 2006.201.13:38:54.70#ibcon#enter sib2, iclass 7, count 2 2006.201.13:38:54.70#ibcon#flushed, iclass 7, count 2 2006.201.13:38:54.70#ibcon#about to write, iclass 7, count 2 2006.201.13:38:54.70#ibcon#wrote, iclass 7, count 2 2006.201.13:38:54.70#ibcon#about to read 3, iclass 7, count 2 2006.201.13:38:54.73#ibcon#read 3, iclass 7, count 2 2006.201.13:38:54.73#ibcon#about to read 4, iclass 7, count 2 2006.201.13:38:54.73#ibcon#read 4, iclass 7, count 2 2006.201.13:38:54.73#ibcon#about to read 5, iclass 7, count 2 2006.201.13:38:54.73#ibcon#read 5, iclass 7, count 2 2006.201.13:38:54.73#ibcon#about to read 6, iclass 7, count 2 2006.201.13:38:54.73#ibcon#read 6, iclass 7, count 2 2006.201.13:38:54.73#ibcon#end of sib2, iclass 7, count 2 2006.201.13:38:54.73#ibcon#*after write, iclass 7, count 2 2006.201.13:38:54.73#ibcon#*before return 0, iclass 7, count 2 2006.201.13:38:54.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:54.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:38:54.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.13:38:54.73#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:54.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:54.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:54.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:54.85#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:38:54.85#ibcon#first serial, iclass 7, count 0 2006.201.13:38:54.85#ibcon#enter sib2, iclass 7, count 0 2006.201.13:38:54.85#ibcon#flushed, iclass 7, count 0 2006.201.13:38:54.85#ibcon#about to write, iclass 7, count 0 2006.201.13:38:54.85#ibcon#wrote, iclass 7, count 0 2006.201.13:38:54.85#ibcon#about to read 3, iclass 7, count 0 2006.201.13:38:54.87#ibcon#read 3, iclass 7, count 0 2006.201.13:38:54.87#ibcon#about to read 4, iclass 7, count 0 2006.201.13:38:54.87#ibcon#read 4, iclass 7, count 0 2006.201.13:38:54.87#ibcon#about to read 5, iclass 7, count 0 2006.201.13:38:54.87#ibcon#read 5, iclass 7, count 0 2006.201.13:38:54.87#ibcon#about to read 6, iclass 7, count 0 2006.201.13:38:54.87#ibcon#read 6, iclass 7, count 0 2006.201.13:38:54.87#ibcon#end of sib2, iclass 7, count 0 2006.201.13:38:54.87#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:38:54.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:38:54.87#ibcon#[27=USB\r\n] 2006.201.13:38:54.87#ibcon#*before write, iclass 7, count 0 2006.201.13:38:54.87#ibcon#enter sib2, iclass 7, count 0 2006.201.13:38:54.87#ibcon#flushed, iclass 7, count 0 2006.201.13:38:54.87#ibcon#about to write, iclass 7, count 0 2006.201.13:38:54.87#ibcon#wrote, iclass 7, count 0 2006.201.13:38:54.87#ibcon#about to read 3, iclass 7, count 0 2006.201.13:38:54.90#ibcon#read 3, iclass 7, count 0 2006.201.13:38:54.90#ibcon#about to read 4, iclass 7, count 0 2006.201.13:38:54.90#ibcon#read 4, iclass 7, count 0 2006.201.13:38:54.90#ibcon#about to read 5, iclass 7, count 0 2006.201.13:38:54.90#ibcon#read 5, iclass 7, count 0 2006.201.13:38:54.90#ibcon#about to read 6, iclass 7, count 0 2006.201.13:38:54.90#ibcon#read 6, iclass 7, count 0 2006.201.13:38:54.90#ibcon#end of sib2, iclass 7, count 0 2006.201.13:38:54.90#ibcon#*after write, iclass 7, count 0 2006.201.13:38:54.90#ibcon#*before return 0, iclass 7, count 0 2006.201.13:38:54.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:54.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:38:54.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:38:54.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:38:54.90$vck44/vblo=8,744.99 2006.201.13:38:54.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.13:38:54.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.13:38:54.90#ibcon#ireg 17 cls_cnt 0 2006.201.13:38:54.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:54.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:54.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:54.90#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:38:54.90#ibcon#first serial, iclass 11, count 0 2006.201.13:38:54.90#ibcon#enter sib2, iclass 11, count 0 2006.201.13:38:54.90#ibcon#flushed, iclass 11, count 0 2006.201.13:38:54.90#ibcon#about to write, iclass 11, count 0 2006.201.13:38:54.90#ibcon#wrote, iclass 11, count 0 2006.201.13:38:54.90#ibcon#about to read 3, iclass 11, count 0 2006.201.13:38:54.92#ibcon#read 3, iclass 11, count 0 2006.201.13:38:54.92#ibcon#about to read 4, iclass 11, count 0 2006.201.13:38:54.92#ibcon#read 4, iclass 11, count 0 2006.201.13:38:54.92#ibcon#about to read 5, iclass 11, count 0 2006.201.13:38:54.92#ibcon#read 5, iclass 11, count 0 2006.201.13:38:54.92#ibcon#about to read 6, iclass 11, count 0 2006.201.13:38:54.92#ibcon#read 6, iclass 11, count 0 2006.201.13:38:54.92#ibcon#end of sib2, iclass 11, count 0 2006.201.13:38:54.92#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:38:54.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:38:54.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:38:54.92#ibcon#*before write, iclass 11, count 0 2006.201.13:38:54.92#ibcon#enter sib2, iclass 11, count 0 2006.201.13:38:54.92#ibcon#flushed, iclass 11, count 0 2006.201.13:38:54.92#ibcon#about to write, iclass 11, count 0 2006.201.13:38:54.92#ibcon#wrote, iclass 11, count 0 2006.201.13:38:54.92#ibcon#about to read 3, iclass 11, count 0 2006.201.13:38:54.97#ibcon#read 3, iclass 11, count 0 2006.201.13:38:54.97#ibcon#about to read 4, iclass 11, count 0 2006.201.13:38:54.97#ibcon#read 4, iclass 11, count 0 2006.201.13:38:54.97#ibcon#about to read 5, iclass 11, count 0 2006.201.13:38:54.97#ibcon#read 5, iclass 11, count 0 2006.201.13:38:54.97#ibcon#about to read 6, iclass 11, count 0 2006.201.13:38:54.97#ibcon#read 6, iclass 11, count 0 2006.201.13:38:54.97#ibcon#end of sib2, iclass 11, count 0 2006.201.13:38:54.97#ibcon#*after write, iclass 11, count 0 2006.201.13:38:54.97#ibcon#*before return 0, iclass 11, count 0 2006.201.13:38:54.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:54.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:38:54.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:38:54.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:38:54.97$vck44/vb=8,4 2006.201.13:38:54.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.13:38:54.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.13:38:54.97#ibcon#ireg 11 cls_cnt 2 2006.201.13:38:54.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:55.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:55.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:55.02#ibcon#enter wrdev, iclass 13, count 2 2006.201.13:38:55.02#ibcon#first serial, iclass 13, count 2 2006.201.13:38:55.02#ibcon#enter sib2, iclass 13, count 2 2006.201.13:38:55.02#ibcon#flushed, iclass 13, count 2 2006.201.13:38:55.02#ibcon#about to write, iclass 13, count 2 2006.201.13:38:55.02#ibcon#wrote, iclass 13, count 2 2006.201.13:38:55.02#ibcon#about to read 3, iclass 13, count 2 2006.201.13:38:55.04#ibcon#read 3, iclass 13, count 2 2006.201.13:38:55.04#ibcon#about to read 4, iclass 13, count 2 2006.201.13:38:55.04#ibcon#read 4, iclass 13, count 2 2006.201.13:38:55.04#ibcon#about to read 5, iclass 13, count 2 2006.201.13:38:55.04#ibcon#read 5, iclass 13, count 2 2006.201.13:38:55.04#ibcon#about to read 6, iclass 13, count 2 2006.201.13:38:55.04#ibcon#read 6, iclass 13, count 2 2006.201.13:38:55.04#ibcon#end of sib2, iclass 13, count 2 2006.201.13:38:55.04#ibcon#*mode == 0, iclass 13, count 2 2006.201.13:38:55.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.13:38:55.04#ibcon#[27=AT08-04\r\n] 2006.201.13:38:55.04#ibcon#*before write, iclass 13, count 2 2006.201.13:38:55.04#ibcon#enter sib2, iclass 13, count 2 2006.201.13:38:55.04#ibcon#flushed, iclass 13, count 2 2006.201.13:38:55.04#ibcon#about to write, iclass 13, count 2 2006.201.13:38:55.04#ibcon#wrote, iclass 13, count 2 2006.201.13:38:55.04#ibcon#about to read 3, iclass 13, count 2 2006.201.13:38:55.07#ibcon#read 3, iclass 13, count 2 2006.201.13:38:55.07#ibcon#about to read 4, iclass 13, count 2 2006.201.13:38:55.07#ibcon#read 4, iclass 13, count 2 2006.201.13:38:55.07#ibcon#about to read 5, iclass 13, count 2 2006.201.13:38:55.07#ibcon#read 5, iclass 13, count 2 2006.201.13:38:55.07#ibcon#about to read 6, iclass 13, count 2 2006.201.13:38:55.07#ibcon#read 6, iclass 13, count 2 2006.201.13:38:55.07#ibcon#end of sib2, iclass 13, count 2 2006.201.13:38:55.07#ibcon#*after write, iclass 13, count 2 2006.201.13:38:55.07#ibcon#*before return 0, iclass 13, count 2 2006.201.13:38:55.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:55.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:38:55.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.13:38:55.07#ibcon#ireg 7 cls_cnt 0 2006.201.13:38:55.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:55.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:55.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:55.19#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:38:55.19#ibcon#first serial, iclass 13, count 0 2006.201.13:38:55.19#ibcon#enter sib2, iclass 13, count 0 2006.201.13:38:55.19#ibcon#flushed, iclass 13, count 0 2006.201.13:38:55.19#ibcon#about to write, iclass 13, count 0 2006.201.13:38:55.19#ibcon#wrote, iclass 13, count 0 2006.201.13:38:55.19#ibcon#about to read 3, iclass 13, count 0 2006.201.13:38:55.21#ibcon#read 3, iclass 13, count 0 2006.201.13:38:55.21#ibcon#about to read 4, iclass 13, count 0 2006.201.13:38:55.21#ibcon#read 4, iclass 13, count 0 2006.201.13:38:55.21#ibcon#about to read 5, iclass 13, count 0 2006.201.13:38:55.21#ibcon#read 5, iclass 13, count 0 2006.201.13:38:55.21#ibcon#about to read 6, iclass 13, count 0 2006.201.13:38:55.21#ibcon#read 6, iclass 13, count 0 2006.201.13:38:55.21#ibcon#end of sib2, iclass 13, count 0 2006.201.13:38:55.21#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:38:55.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:38:55.21#ibcon#[27=USB\r\n] 2006.201.13:38:55.21#ibcon#*before write, iclass 13, count 0 2006.201.13:38:55.21#ibcon#enter sib2, iclass 13, count 0 2006.201.13:38:55.21#ibcon#flushed, iclass 13, count 0 2006.201.13:38:55.21#ibcon#about to write, iclass 13, count 0 2006.201.13:38:55.21#ibcon#wrote, iclass 13, count 0 2006.201.13:38:55.21#ibcon#about to read 3, iclass 13, count 0 2006.201.13:38:55.24#ibcon#read 3, iclass 13, count 0 2006.201.13:38:55.24#ibcon#about to read 4, iclass 13, count 0 2006.201.13:38:55.24#ibcon#read 4, iclass 13, count 0 2006.201.13:38:55.24#ibcon#about to read 5, iclass 13, count 0 2006.201.13:38:55.24#ibcon#read 5, iclass 13, count 0 2006.201.13:38:55.24#ibcon#about to read 6, iclass 13, count 0 2006.201.13:38:55.24#ibcon#read 6, iclass 13, count 0 2006.201.13:38:55.24#ibcon#end of sib2, iclass 13, count 0 2006.201.13:38:55.24#ibcon#*after write, iclass 13, count 0 2006.201.13:38:55.24#ibcon#*before return 0, iclass 13, count 0 2006.201.13:38:55.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:55.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:38:55.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:38:55.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:38:55.24$vck44/vabw=wide 2006.201.13:38:55.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.13:38:55.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.13:38:55.24#ibcon#ireg 8 cls_cnt 0 2006.201.13:38:55.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:55.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:55.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:55.24#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:38:55.24#ibcon#first serial, iclass 15, count 0 2006.201.13:38:55.24#ibcon#enter sib2, iclass 15, count 0 2006.201.13:38:55.24#ibcon#flushed, iclass 15, count 0 2006.201.13:38:55.24#ibcon#about to write, iclass 15, count 0 2006.201.13:38:55.24#ibcon#wrote, iclass 15, count 0 2006.201.13:38:55.24#ibcon#about to read 3, iclass 15, count 0 2006.201.13:38:55.26#ibcon#read 3, iclass 15, count 0 2006.201.13:38:55.26#ibcon#about to read 4, iclass 15, count 0 2006.201.13:38:55.26#ibcon#read 4, iclass 15, count 0 2006.201.13:38:55.26#ibcon#about to read 5, iclass 15, count 0 2006.201.13:38:55.26#ibcon#read 5, iclass 15, count 0 2006.201.13:38:55.26#ibcon#about to read 6, iclass 15, count 0 2006.201.13:38:55.26#ibcon#read 6, iclass 15, count 0 2006.201.13:38:55.26#ibcon#end of sib2, iclass 15, count 0 2006.201.13:38:55.26#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:38:55.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:38:55.26#ibcon#[25=BW32\r\n] 2006.201.13:38:55.26#ibcon#*before write, iclass 15, count 0 2006.201.13:38:55.26#ibcon#enter sib2, iclass 15, count 0 2006.201.13:38:55.26#ibcon#flushed, iclass 15, count 0 2006.201.13:38:55.26#ibcon#about to write, iclass 15, count 0 2006.201.13:38:55.26#ibcon#wrote, iclass 15, count 0 2006.201.13:38:55.26#ibcon#about to read 3, iclass 15, count 0 2006.201.13:38:55.29#ibcon#read 3, iclass 15, count 0 2006.201.13:38:55.29#ibcon#about to read 4, iclass 15, count 0 2006.201.13:38:55.29#ibcon#read 4, iclass 15, count 0 2006.201.13:38:55.29#ibcon#about to read 5, iclass 15, count 0 2006.201.13:38:55.29#ibcon#read 5, iclass 15, count 0 2006.201.13:38:55.29#ibcon#about to read 6, iclass 15, count 0 2006.201.13:38:55.29#ibcon#read 6, iclass 15, count 0 2006.201.13:38:55.29#ibcon#end of sib2, iclass 15, count 0 2006.201.13:38:55.29#ibcon#*after write, iclass 15, count 0 2006.201.13:38:55.29#ibcon#*before return 0, iclass 15, count 0 2006.201.13:38:55.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:55.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:38:55.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:38:55.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:38:55.29$vck44/vbbw=wide 2006.201.13:38:55.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.13:38:55.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.13:38:55.29#ibcon#ireg 8 cls_cnt 0 2006.201.13:38:55.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:38:55.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:38:55.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:38:55.36#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:38:55.36#ibcon#first serial, iclass 17, count 0 2006.201.13:38:55.36#ibcon#enter sib2, iclass 17, count 0 2006.201.13:38:55.36#ibcon#flushed, iclass 17, count 0 2006.201.13:38:55.36#ibcon#about to write, iclass 17, count 0 2006.201.13:38:55.36#ibcon#wrote, iclass 17, count 0 2006.201.13:38:55.36#ibcon#about to read 3, iclass 17, count 0 2006.201.13:38:55.38#ibcon#read 3, iclass 17, count 0 2006.201.13:38:55.38#ibcon#about to read 4, iclass 17, count 0 2006.201.13:38:55.38#ibcon#read 4, iclass 17, count 0 2006.201.13:38:55.38#ibcon#about to read 5, iclass 17, count 0 2006.201.13:38:55.38#ibcon#read 5, iclass 17, count 0 2006.201.13:38:55.38#ibcon#about to read 6, iclass 17, count 0 2006.201.13:38:55.38#ibcon#read 6, iclass 17, count 0 2006.201.13:38:55.38#ibcon#end of sib2, iclass 17, count 0 2006.201.13:38:55.38#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:38:55.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:38:55.38#ibcon#[27=BW32\r\n] 2006.201.13:38:55.38#ibcon#*before write, iclass 17, count 0 2006.201.13:38:55.38#ibcon#enter sib2, iclass 17, count 0 2006.201.13:38:55.38#ibcon#flushed, iclass 17, count 0 2006.201.13:38:55.38#ibcon#about to write, iclass 17, count 0 2006.201.13:38:55.38#ibcon#wrote, iclass 17, count 0 2006.201.13:38:55.38#ibcon#about to read 3, iclass 17, count 0 2006.201.13:38:55.41#ibcon#read 3, iclass 17, count 0 2006.201.13:38:55.41#ibcon#about to read 4, iclass 17, count 0 2006.201.13:38:55.41#ibcon#read 4, iclass 17, count 0 2006.201.13:38:55.41#ibcon#about to read 5, iclass 17, count 0 2006.201.13:38:55.41#ibcon#read 5, iclass 17, count 0 2006.201.13:38:55.41#ibcon#about to read 6, iclass 17, count 0 2006.201.13:38:55.41#ibcon#read 6, iclass 17, count 0 2006.201.13:38:55.41#ibcon#end of sib2, iclass 17, count 0 2006.201.13:38:55.41#ibcon#*after write, iclass 17, count 0 2006.201.13:38:55.41#ibcon#*before return 0, iclass 17, count 0 2006.201.13:38:55.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:38:55.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:38:55.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:38:55.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:38:55.41$setupk4/ifdk4 2006.201.13:38:55.41$ifdk4/lo= 2006.201.13:38:55.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:38:55.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:38:55.41$ifdk4/patch= 2006.201.13:38:55.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:38:55.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:38:55.41$setupk4/!*+20s 2006.201.13:39:00.63#abcon#<5=/04 1.4 2.8 20.901001003.8\r\n> 2006.201.13:39:00.65#abcon#{5=INTERFACE CLEAR} 2006.201.13:39:00.71#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:39:09.87$setupk4/"tpicd 2006.201.13:39:09.87$setupk4/echo=off 2006.201.13:39:09.87$setupk4/xlog=off 2006.201.13:39:09.87:!2006.201.13:41:46 2006.201.13:39:11.13#trakl#Source acquired 2006.201.13:39:12.13#flagr#flagr/antenna,acquired 2006.201.13:41:46.00:preob 2006.201.13:41:46.14/onsource/TRACKING 2006.201.13:41:46.14:!2006.201.13:41:56 2006.201.13:41:56.00:"tape 2006.201.13:41:56.00:"st=record 2006.201.13:41:56.00:data_valid=on 2006.201.13:41:56.00:midob 2006.201.13:41:57.14/onsource/TRACKING 2006.201.13:41:57.14/wx/20.89,1003.8,100 2006.201.13:41:57.21/cable/+6.4756E-03 2006.201.13:41:58.30/va/01,08,usb,yes,29,32 2006.201.13:41:58.30/va/02,07,usb,yes,32,33 2006.201.13:41:58.30/va/03,08,usb,yes,29,30 2006.201.13:41:58.30/va/04,07,usb,yes,33,34 2006.201.13:41:58.30/va/05,04,usb,yes,29,29 2006.201.13:41:58.30/va/06,05,usb,yes,29,29 2006.201.13:41:58.30/va/07,05,usb,yes,28,29 2006.201.13:41:58.30/va/08,04,usb,yes,28,34 2006.201.13:41:58.53/valo/01,524.99,yes,locked 2006.201.13:41:58.53/valo/02,534.99,yes,locked 2006.201.13:41:58.53/valo/03,564.99,yes,locked 2006.201.13:41:58.53/valo/04,624.99,yes,locked 2006.201.13:41:58.53/valo/05,734.99,yes,locked 2006.201.13:41:58.53/valo/06,814.99,yes,locked 2006.201.13:41:58.53/valo/07,864.99,yes,locked 2006.201.13:41:58.53/valo/08,884.99,yes,locked 2006.201.13:41:59.62/vb/01,04,usb,yes,29,27 2006.201.13:41:59.62/vb/02,05,usb,yes,28,28 2006.201.13:41:59.62/vb/03,04,usb,yes,28,31 2006.201.13:41:59.62/vb/04,05,usb,yes,29,28 2006.201.13:41:59.62/vb/05,04,usb,yes,25,28 2006.201.13:41:59.62/vb/06,04,usb,yes,30,26 2006.201.13:41:59.62/vb/07,04,usb,yes,30,29 2006.201.13:41:59.62/vb/08,04,usb,yes,27,30 2006.201.13:41:59.86/vblo/01,629.99,yes,locked 2006.201.13:41:59.86/vblo/02,634.99,yes,locked 2006.201.13:41:59.86/vblo/03,649.99,yes,locked 2006.201.13:41:59.86/vblo/04,679.99,yes,locked 2006.201.13:41:59.86/vblo/05,709.99,yes,locked 2006.201.13:41:59.86/vblo/06,719.99,yes,locked 2006.201.13:41:59.86/vblo/07,734.99,yes,locked 2006.201.13:41:59.86/vblo/08,744.99,yes,locked 2006.201.13:42:00.01/vabw/8 2006.201.13:42:00.16/vbbw/8 2006.201.13:42:00.25/xfe/off,on,14.5 2006.201.13:42:00.62/ifatt/23,28,28,28 2006.201.13:42:01.06/fmout-gps/S +4.55E-07 2006.201.13:42:01.10:!2006.201.13:45:06 2006.201.13:45:06.00:data_valid=off 2006.201.13:45:06.00:"et 2006.201.13:45:06.00:!+3s 2006.201.13:45:09.02:"tape 2006.201.13:45:09.02:postob 2006.201.13:45:09.12/cable/+6.4759E-03 2006.201.13:45:09.12/wx/20.88,1004.0,100 2006.201.13:45:09.20/fmout-gps/S +4.53E-07 2006.201.13:45:09.20:scan_name=201-1347,jd0607,80 2006.201.13:45:09.20:source=2136+141,213901.31,142336.0,2000.0,cw 2006.201.13:45:11.14#flagr#flagr/antenna,new-source 2006.201.13:45:11.14:checkk5 2006.201.13:45:11.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:45:11.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:45:12.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:45:12.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:45:13.02/chk_obsdata//k5ts1/T2011341??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.201.13:45:13.38/chk_obsdata//k5ts2/T2011341??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.201.13:45:13.75/chk_obsdata//k5ts3/T2011341??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.201.13:45:14.11/chk_obsdata//k5ts4/T2011341??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.201.13:45:14.79/k5log//k5ts1_log_newline 2006.201.13:45:15.49/k5log//k5ts2_log_newline 2006.201.13:45:16.18/k5log//k5ts3_log_newline 2006.201.13:45:16.86/k5log//k5ts4_log_newline 2006.201.13:45:16.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:45:16.88:setupk4=1 2006.201.13:45:16.88$setupk4/echo=on 2006.201.13:45:16.88$setupk4/pcalon 2006.201.13:45:16.88$pcalon/"no phase cal control is implemented here 2006.201.13:45:16.88$setupk4/"tpicd=stop 2006.201.13:45:16.88$setupk4/"rec=synch_on 2006.201.13:45:16.88$setupk4/"rec_mode=128 2006.201.13:45:16.88$setupk4/!* 2006.201.13:45:16.88$setupk4/recpk4 2006.201.13:45:16.88$recpk4/recpatch= 2006.201.13:45:16.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:45:16.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:45:16.89$setupk4/vck44 2006.201.13:45:16.89$vck44/valo=1,524.99 2006.201.13:45:16.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.13:45:16.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.13:45:16.89#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:16.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:16.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:16.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:16.89#ibcon#enter wrdev, iclass 26, count 0 2006.201.13:45:16.89#ibcon#first serial, iclass 26, count 0 2006.201.13:45:16.89#ibcon#enter sib2, iclass 26, count 0 2006.201.13:45:16.89#ibcon#flushed, iclass 26, count 0 2006.201.13:45:16.89#ibcon#about to write, iclass 26, count 0 2006.201.13:45:16.89#ibcon#wrote, iclass 26, count 0 2006.201.13:45:16.89#ibcon#about to read 3, iclass 26, count 0 2006.201.13:45:16.92#ibcon#read 3, iclass 26, count 0 2006.201.13:45:16.92#ibcon#about to read 4, iclass 26, count 0 2006.201.13:45:16.92#ibcon#read 4, iclass 26, count 0 2006.201.13:45:16.92#ibcon#about to read 5, iclass 26, count 0 2006.201.13:45:16.92#ibcon#read 5, iclass 26, count 0 2006.201.13:45:16.92#ibcon#about to read 6, iclass 26, count 0 2006.201.13:45:16.92#ibcon#read 6, iclass 26, count 0 2006.201.13:45:16.92#ibcon#end of sib2, iclass 26, count 0 2006.201.13:45:16.92#ibcon#*mode == 0, iclass 26, count 0 2006.201.13:45:16.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.13:45:16.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:45:16.92#ibcon#*before write, iclass 26, count 0 2006.201.13:45:16.92#ibcon#enter sib2, iclass 26, count 0 2006.201.13:45:16.92#ibcon#flushed, iclass 26, count 0 2006.201.13:45:16.92#ibcon#about to write, iclass 26, count 0 2006.201.13:45:16.92#ibcon#wrote, iclass 26, count 0 2006.201.13:45:16.92#ibcon#about to read 3, iclass 26, count 0 2006.201.13:45:16.97#ibcon#read 3, iclass 26, count 0 2006.201.13:45:16.97#ibcon#about to read 4, iclass 26, count 0 2006.201.13:45:16.97#ibcon#read 4, iclass 26, count 0 2006.201.13:45:16.97#ibcon#about to read 5, iclass 26, count 0 2006.201.13:45:16.97#ibcon#read 5, iclass 26, count 0 2006.201.13:45:16.97#ibcon#about to read 6, iclass 26, count 0 2006.201.13:45:16.97#ibcon#read 6, iclass 26, count 0 2006.201.13:45:16.97#ibcon#end of sib2, iclass 26, count 0 2006.201.13:45:16.97#ibcon#*after write, iclass 26, count 0 2006.201.13:45:16.97#ibcon#*before return 0, iclass 26, count 0 2006.201.13:45:16.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:16.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:16.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.13:45:16.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.13:45:16.97$vck44/va=1,8 2006.201.13:45:16.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.13:45:16.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.13:45:16.97#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:16.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:16.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:16.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:16.97#ibcon#enter wrdev, iclass 28, count 2 2006.201.13:45:16.97#ibcon#first serial, iclass 28, count 2 2006.201.13:45:16.97#ibcon#enter sib2, iclass 28, count 2 2006.201.13:45:16.97#ibcon#flushed, iclass 28, count 2 2006.201.13:45:16.97#ibcon#about to write, iclass 28, count 2 2006.201.13:45:16.97#ibcon#wrote, iclass 28, count 2 2006.201.13:45:16.97#ibcon#about to read 3, iclass 28, count 2 2006.201.13:45:16.99#ibcon#read 3, iclass 28, count 2 2006.201.13:45:16.99#ibcon#about to read 4, iclass 28, count 2 2006.201.13:45:16.99#ibcon#read 4, iclass 28, count 2 2006.201.13:45:16.99#ibcon#about to read 5, iclass 28, count 2 2006.201.13:45:16.99#ibcon#read 5, iclass 28, count 2 2006.201.13:45:16.99#ibcon#about to read 6, iclass 28, count 2 2006.201.13:45:16.99#ibcon#read 6, iclass 28, count 2 2006.201.13:45:16.99#ibcon#end of sib2, iclass 28, count 2 2006.201.13:45:16.99#ibcon#*mode == 0, iclass 28, count 2 2006.201.13:45:16.99#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.13:45:16.99#ibcon#[25=AT01-08\r\n] 2006.201.13:45:16.99#ibcon#*before write, iclass 28, count 2 2006.201.13:45:16.99#ibcon#enter sib2, iclass 28, count 2 2006.201.13:45:16.99#ibcon#flushed, iclass 28, count 2 2006.201.13:45:16.99#ibcon#about to write, iclass 28, count 2 2006.201.13:45:16.99#ibcon#wrote, iclass 28, count 2 2006.201.13:45:16.99#ibcon#about to read 3, iclass 28, count 2 2006.201.13:45:17.02#ibcon#read 3, iclass 28, count 2 2006.201.13:45:17.02#ibcon#about to read 4, iclass 28, count 2 2006.201.13:45:17.02#ibcon#read 4, iclass 28, count 2 2006.201.13:45:17.02#ibcon#about to read 5, iclass 28, count 2 2006.201.13:45:17.02#ibcon#read 5, iclass 28, count 2 2006.201.13:45:17.02#ibcon#about to read 6, iclass 28, count 2 2006.201.13:45:17.02#ibcon#read 6, iclass 28, count 2 2006.201.13:45:17.02#ibcon#end of sib2, iclass 28, count 2 2006.201.13:45:17.02#ibcon#*after write, iclass 28, count 2 2006.201.13:45:17.02#ibcon#*before return 0, iclass 28, count 2 2006.201.13:45:17.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:17.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:17.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.13:45:17.02#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:17.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:17.05#abcon#<5=/04 1.2 2.3 20.881001003.9\r\n> 2006.201.13:45:17.07#abcon#{5=INTERFACE CLEAR} 2006.201.13:45:17.13#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:45:17.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:17.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:17.14#ibcon#enter wrdev, iclass 28, count 0 2006.201.13:45:17.14#ibcon#first serial, iclass 28, count 0 2006.201.13:45:17.14#ibcon#enter sib2, iclass 28, count 0 2006.201.13:45:17.14#ibcon#flushed, iclass 28, count 0 2006.201.13:45:17.14#ibcon#about to write, iclass 28, count 0 2006.201.13:45:17.14#ibcon#wrote, iclass 28, count 0 2006.201.13:45:17.14#ibcon#about to read 3, iclass 28, count 0 2006.201.13:45:17.16#ibcon#read 3, iclass 28, count 0 2006.201.13:45:17.16#ibcon#about to read 4, iclass 28, count 0 2006.201.13:45:17.16#ibcon#read 4, iclass 28, count 0 2006.201.13:45:17.16#ibcon#about to read 5, iclass 28, count 0 2006.201.13:45:17.16#ibcon#read 5, iclass 28, count 0 2006.201.13:45:17.16#ibcon#about to read 6, iclass 28, count 0 2006.201.13:45:17.16#ibcon#read 6, iclass 28, count 0 2006.201.13:45:17.16#ibcon#end of sib2, iclass 28, count 0 2006.201.13:45:17.16#ibcon#*mode == 0, iclass 28, count 0 2006.201.13:45:17.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.13:45:17.16#ibcon#[25=USB\r\n] 2006.201.13:45:17.16#ibcon#*before write, iclass 28, count 0 2006.201.13:45:17.16#ibcon#enter sib2, iclass 28, count 0 2006.201.13:45:17.16#ibcon#flushed, iclass 28, count 0 2006.201.13:45:17.16#ibcon#about to write, iclass 28, count 0 2006.201.13:45:17.16#ibcon#wrote, iclass 28, count 0 2006.201.13:45:17.16#ibcon#about to read 3, iclass 28, count 0 2006.201.13:45:17.19#ibcon#read 3, iclass 28, count 0 2006.201.13:45:17.19#ibcon#about to read 4, iclass 28, count 0 2006.201.13:45:17.19#ibcon#read 4, iclass 28, count 0 2006.201.13:45:17.19#ibcon#about to read 5, iclass 28, count 0 2006.201.13:45:17.19#ibcon#read 5, iclass 28, count 0 2006.201.13:45:17.19#ibcon#about to read 6, iclass 28, count 0 2006.201.13:45:17.19#ibcon#read 6, iclass 28, count 0 2006.201.13:45:17.19#ibcon#end of sib2, iclass 28, count 0 2006.201.13:45:17.19#ibcon#*after write, iclass 28, count 0 2006.201.13:45:17.19#ibcon#*before return 0, iclass 28, count 0 2006.201.13:45:17.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:17.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:17.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.13:45:17.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.13:45:17.19$vck44/valo=2,534.99 2006.201.13:45:17.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.13:45:17.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.13:45:17.19#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:17.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:17.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:17.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:17.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.13:45:17.19#ibcon#first serial, iclass 34, count 0 2006.201.13:45:17.19#ibcon#enter sib2, iclass 34, count 0 2006.201.13:45:17.19#ibcon#flushed, iclass 34, count 0 2006.201.13:45:17.19#ibcon#about to write, iclass 34, count 0 2006.201.13:45:17.19#ibcon#wrote, iclass 34, count 0 2006.201.13:45:17.19#ibcon#about to read 3, iclass 34, count 0 2006.201.13:45:17.21#ibcon#read 3, iclass 34, count 0 2006.201.13:45:17.21#ibcon#about to read 4, iclass 34, count 0 2006.201.13:45:17.21#ibcon#read 4, iclass 34, count 0 2006.201.13:45:17.21#ibcon#about to read 5, iclass 34, count 0 2006.201.13:45:17.21#ibcon#read 5, iclass 34, count 0 2006.201.13:45:17.21#ibcon#about to read 6, iclass 34, count 0 2006.201.13:45:17.21#ibcon#read 6, iclass 34, count 0 2006.201.13:45:17.21#ibcon#end of sib2, iclass 34, count 0 2006.201.13:45:17.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.13:45:17.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.13:45:17.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:45:17.21#ibcon#*before write, iclass 34, count 0 2006.201.13:45:17.21#ibcon#enter sib2, iclass 34, count 0 2006.201.13:45:17.21#ibcon#flushed, iclass 34, count 0 2006.201.13:45:17.21#ibcon#about to write, iclass 34, count 0 2006.201.13:45:17.21#ibcon#wrote, iclass 34, count 0 2006.201.13:45:17.21#ibcon#about to read 3, iclass 34, count 0 2006.201.13:45:17.25#ibcon#read 3, iclass 34, count 0 2006.201.13:45:17.25#ibcon#about to read 4, iclass 34, count 0 2006.201.13:45:17.25#ibcon#read 4, iclass 34, count 0 2006.201.13:45:17.25#ibcon#about to read 5, iclass 34, count 0 2006.201.13:45:17.25#ibcon#read 5, iclass 34, count 0 2006.201.13:45:17.25#ibcon#about to read 6, iclass 34, count 0 2006.201.13:45:17.25#ibcon#read 6, iclass 34, count 0 2006.201.13:45:17.25#ibcon#end of sib2, iclass 34, count 0 2006.201.13:45:17.25#ibcon#*after write, iclass 34, count 0 2006.201.13:45:17.25#ibcon#*before return 0, iclass 34, count 0 2006.201.13:45:17.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:17.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:17.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.13:45:17.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.13:45:17.25$vck44/va=2,7 2006.201.13:45:17.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.13:45:17.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.13:45:17.25#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:17.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:17.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:17.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:17.31#ibcon#enter wrdev, iclass 36, count 2 2006.201.13:45:17.31#ibcon#first serial, iclass 36, count 2 2006.201.13:45:17.31#ibcon#enter sib2, iclass 36, count 2 2006.201.13:45:17.31#ibcon#flushed, iclass 36, count 2 2006.201.13:45:17.31#ibcon#about to write, iclass 36, count 2 2006.201.13:45:17.31#ibcon#wrote, iclass 36, count 2 2006.201.13:45:17.31#ibcon#about to read 3, iclass 36, count 2 2006.201.13:45:17.33#ibcon#read 3, iclass 36, count 2 2006.201.13:45:17.33#ibcon#about to read 4, iclass 36, count 2 2006.201.13:45:17.33#ibcon#read 4, iclass 36, count 2 2006.201.13:45:17.33#ibcon#about to read 5, iclass 36, count 2 2006.201.13:45:17.33#ibcon#read 5, iclass 36, count 2 2006.201.13:45:17.33#ibcon#about to read 6, iclass 36, count 2 2006.201.13:45:17.33#ibcon#read 6, iclass 36, count 2 2006.201.13:45:17.33#ibcon#end of sib2, iclass 36, count 2 2006.201.13:45:17.33#ibcon#*mode == 0, iclass 36, count 2 2006.201.13:45:17.33#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.13:45:17.33#ibcon#[25=AT02-07\r\n] 2006.201.13:45:17.33#ibcon#*before write, iclass 36, count 2 2006.201.13:45:17.33#ibcon#enter sib2, iclass 36, count 2 2006.201.13:45:17.33#ibcon#flushed, iclass 36, count 2 2006.201.13:45:17.33#ibcon#about to write, iclass 36, count 2 2006.201.13:45:17.33#ibcon#wrote, iclass 36, count 2 2006.201.13:45:17.33#ibcon#about to read 3, iclass 36, count 2 2006.201.13:45:17.36#ibcon#read 3, iclass 36, count 2 2006.201.13:45:17.36#ibcon#about to read 4, iclass 36, count 2 2006.201.13:45:17.36#ibcon#read 4, iclass 36, count 2 2006.201.13:45:17.36#ibcon#about to read 5, iclass 36, count 2 2006.201.13:45:17.36#ibcon#read 5, iclass 36, count 2 2006.201.13:45:17.36#ibcon#about to read 6, iclass 36, count 2 2006.201.13:45:17.36#ibcon#read 6, iclass 36, count 2 2006.201.13:45:17.36#ibcon#end of sib2, iclass 36, count 2 2006.201.13:45:17.36#ibcon#*after write, iclass 36, count 2 2006.201.13:45:17.36#ibcon#*before return 0, iclass 36, count 2 2006.201.13:45:17.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:17.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:17.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.13:45:17.36#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:17.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:17.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:17.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:17.48#ibcon#enter wrdev, iclass 36, count 0 2006.201.13:45:17.48#ibcon#first serial, iclass 36, count 0 2006.201.13:45:17.48#ibcon#enter sib2, iclass 36, count 0 2006.201.13:45:17.48#ibcon#flushed, iclass 36, count 0 2006.201.13:45:17.48#ibcon#about to write, iclass 36, count 0 2006.201.13:45:17.48#ibcon#wrote, iclass 36, count 0 2006.201.13:45:17.48#ibcon#about to read 3, iclass 36, count 0 2006.201.13:45:17.50#ibcon#read 3, iclass 36, count 0 2006.201.13:45:17.50#ibcon#about to read 4, iclass 36, count 0 2006.201.13:45:17.50#ibcon#read 4, iclass 36, count 0 2006.201.13:45:17.50#ibcon#about to read 5, iclass 36, count 0 2006.201.13:45:17.50#ibcon#read 5, iclass 36, count 0 2006.201.13:45:17.50#ibcon#about to read 6, iclass 36, count 0 2006.201.13:45:17.50#ibcon#read 6, iclass 36, count 0 2006.201.13:45:17.50#ibcon#end of sib2, iclass 36, count 0 2006.201.13:45:17.50#ibcon#*mode == 0, iclass 36, count 0 2006.201.13:45:17.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.13:45:17.50#ibcon#[25=USB\r\n] 2006.201.13:45:17.50#ibcon#*before write, iclass 36, count 0 2006.201.13:45:17.50#ibcon#enter sib2, iclass 36, count 0 2006.201.13:45:17.50#ibcon#flushed, iclass 36, count 0 2006.201.13:45:17.50#ibcon#about to write, iclass 36, count 0 2006.201.13:45:17.50#ibcon#wrote, iclass 36, count 0 2006.201.13:45:17.50#ibcon#about to read 3, iclass 36, count 0 2006.201.13:45:17.53#ibcon#read 3, iclass 36, count 0 2006.201.13:45:17.53#ibcon#about to read 4, iclass 36, count 0 2006.201.13:45:17.53#ibcon#read 4, iclass 36, count 0 2006.201.13:45:17.53#ibcon#about to read 5, iclass 36, count 0 2006.201.13:45:17.53#ibcon#read 5, iclass 36, count 0 2006.201.13:45:17.53#ibcon#about to read 6, iclass 36, count 0 2006.201.13:45:17.53#ibcon#read 6, iclass 36, count 0 2006.201.13:45:17.53#ibcon#end of sib2, iclass 36, count 0 2006.201.13:45:17.53#ibcon#*after write, iclass 36, count 0 2006.201.13:45:17.53#ibcon#*before return 0, iclass 36, count 0 2006.201.13:45:17.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:17.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:17.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.13:45:17.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.13:45:17.53$vck44/valo=3,564.99 2006.201.13:45:17.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.13:45:17.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.13:45:17.53#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:17.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:17.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:17.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:17.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.13:45:17.53#ibcon#first serial, iclass 38, count 0 2006.201.13:45:17.53#ibcon#enter sib2, iclass 38, count 0 2006.201.13:45:17.53#ibcon#flushed, iclass 38, count 0 2006.201.13:45:17.53#ibcon#about to write, iclass 38, count 0 2006.201.13:45:17.53#ibcon#wrote, iclass 38, count 0 2006.201.13:45:17.53#ibcon#about to read 3, iclass 38, count 0 2006.201.13:45:17.55#ibcon#read 3, iclass 38, count 0 2006.201.13:45:17.55#ibcon#about to read 4, iclass 38, count 0 2006.201.13:45:17.55#ibcon#read 4, iclass 38, count 0 2006.201.13:45:17.55#ibcon#about to read 5, iclass 38, count 0 2006.201.13:45:17.55#ibcon#read 5, iclass 38, count 0 2006.201.13:45:17.55#ibcon#about to read 6, iclass 38, count 0 2006.201.13:45:17.55#ibcon#read 6, iclass 38, count 0 2006.201.13:45:17.55#ibcon#end of sib2, iclass 38, count 0 2006.201.13:45:17.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.13:45:17.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.13:45:17.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:45:17.55#ibcon#*before write, iclass 38, count 0 2006.201.13:45:17.55#ibcon#enter sib2, iclass 38, count 0 2006.201.13:45:17.55#ibcon#flushed, iclass 38, count 0 2006.201.13:45:17.55#ibcon#about to write, iclass 38, count 0 2006.201.13:45:17.55#ibcon#wrote, iclass 38, count 0 2006.201.13:45:17.55#ibcon#about to read 3, iclass 38, count 0 2006.201.13:45:17.60#ibcon#read 3, iclass 38, count 0 2006.201.13:45:17.60#ibcon#about to read 4, iclass 38, count 0 2006.201.13:45:17.60#ibcon#read 4, iclass 38, count 0 2006.201.13:45:17.60#ibcon#about to read 5, iclass 38, count 0 2006.201.13:45:17.60#ibcon#read 5, iclass 38, count 0 2006.201.13:45:17.60#ibcon#about to read 6, iclass 38, count 0 2006.201.13:45:17.60#ibcon#read 6, iclass 38, count 0 2006.201.13:45:17.60#ibcon#end of sib2, iclass 38, count 0 2006.201.13:45:17.60#ibcon#*after write, iclass 38, count 0 2006.201.13:45:17.60#ibcon#*before return 0, iclass 38, count 0 2006.201.13:45:17.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:17.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:17.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.13:45:17.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.13:45:17.60$vck44/va=3,8 2006.201.13:45:17.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.13:45:17.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.13:45:17.60#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:17.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:17.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:17.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:17.65#ibcon#enter wrdev, iclass 40, count 2 2006.201.13:45:17.65#ibcon#first serial, iclass 40, count 2 2006.201.13:45:17.65#ibcon#enter sib2, iclass 40, count 2 2006.201.13:45:17.65#ibcon#flushed, iclass 40, count 2 2006.201.13:45:17.65#ibcon#about to write, iclass 40, count 2 2006.201.13:45:17.65#ibcon#wrote, iclass 40, count 2 2006.201.13:45:17.65#ibcon#about to read 3, iclass 40, count 2 2006.201.13:45:17.67#ibcon#read 3, iclass 40, count 2 2006.201.13:45:17.67#ibcon#about to read 4, iclass 40, count 2 2006.201.13:45:17.67#ibcon#read 4, iclass 40, count 2 2006.201.13:45:17.67#ibcon#about to read 5, iclass 40, count 2 2006.201.13:45:17.67#ibcon#read 5, iclass 40, count 2 2006.201.13:45:17.67#ibcon#about to read 6, iclass 40, count 2 2006.201.13:45:17.67#ibcon#read 6, iclass 40, count 2 2006.201.13:45:17.67#ibcon#end of sib2, iclass 40, count 2 2006.201.13:45:17.67#ibcon#*mode == 0, iclass 40, count 2 2006.201.13:45:17.67#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.13:45:17.67#ibcon#[25=AT03-08\r\n] 2006.201.13:45:17.67#ibcon#*before write, iclass 40, count 2 2006.201.13:45:17.67#ibcon#enter sib2, iclass 40, count 2 2006.201.13:45:17.67#ibcon#flushed, iclass 40, count 2 2006.201.13:45:17.67#ibcon#about to write, iclass 40, count 2 2006.201.13:45:17.67#ibcon#wrote, iclass 40, count 2 2006.201.13:45:17.67#ibcon#about to read 3, iclass 40, count 2 2006.201.13:45:17.70#ibcon#read 3, iclass 40, count 2 2006.201.13:45:17.70#ibcon#about to read 4, iclass 40, count 2 2006.201.13:45:17.70#ibcon#read 4, iclass 40, count 2 2006.201.13:45:17.70#ibcon#about to read 5, iclass 40, count 2 2006.201.13:45:17.70#ibcon#read 5, iclass 40, count 2 2006.201.13:45:17.70#ibcon#about to read 6, iclass 40, count 2 2006.201.13:45:17.70#ibcon#read 6, iclass 40, count 2 2006.201.13:45:17.70#ibcon#end of sib2, iclass 40, count 2 2006.201.13:45:17.70#ibcon#*after write, iclass 40, count 2 2006.201.13:45:17.70#ibcon#*before return 0, iclass 40, count 2 2006.201.13:45:17.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:17.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:17.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.13:45:17.70#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:17.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:17.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:17.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:17.82#ibcon#enter wrdev, iclass 40, count 0 2006.201.13:45:17.82#ibcon#first serial, iclass 40, count 0 2006.201.13:45:17.82#ibcon#enter sib2, iclass 40, count 0 2006.201.13:45:17.82#ibcon#flushed, iclass 40, count 0 2006.201.13:45:17.82#ibcon#about to write, iclass 40, count 0 2006.201.13:45:17.82#ibcon#wrote, iclass 40, count 0 2006.201.13:45:17.82#ibcon#about to read 3, iclass 40, count 0 2006.201.13:45:17.84#ibcon#read 3, iclass 40, count 0 2006.201.13:45:17.84#ibcon#about to read 4, iclass 40, count 0 2006.201.13:45:17.84#ibcon#read 4, iclass 40, count 0 2006.201.13:45:17.84#ibcon#about to read 5, iclass 40, count 0 2006.201.13:45:17.84#ibcon#read 5, iclass 40, count 0 2006.201.13:45:17.84#ibcon#about to read 6, iclass 40, count 0 2006.201.13:45:17.84#ibcon#read 6, iclass 40, count 0 2006.201.13:45:17.84#ibcon#end of sib2, iclass 40, count 0 2006.201.13:45:17.84#ibcon#*mode == 0, iclass 40, count 0 2006.201.13:45:17.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.13:45:17.84#ibcon#[25=USB\r\n] 2006.201.13:45:17.84#ibcon#*before write, iclass 40, count 0 2006.201.13:45:17.84#ibcon#enter sib2, iclass 40, count 0 2006.201.13:45:17.84#ibcon#flushed, iclass 40, count 0 2006.201.13:45:17.84#ibcon#about to write, iclass 40, count 0 2006.201.13:45:17.84#ibcon#wrote, iclass 40, count 0 2006.201.13:45:17.84#ibcon#about to read 3, iclass 40, count 0 2006.201.13:45:17.87#ibcon#read 3, iclass 40, count 0 2006.201.13:45:17.87#ibcon#about to read 4, iclass 40, count 0 2006.201.13:45:17.87#ibcon#read 4, iclass 40, count 0 2006.201.13:45:17.87#ibcon#about to read 5, iclass 40, count 0 2006.201.13:45:17.87#ibcon#read 5, iclass 40, count 0 2006.201.13:45:17.87#ibcon#about to read 6, iclass 40, count 0 2006.201.13:45:17.87#ibcon#read 6, iclass 40, count 0 2006.201.13:45:17.87#ibcon#end of sib2, iclass 40, count 0 2006.201.13:45:17.87#ibcon#*after write, iclass 40, count 0 2006.201.13:45:17.87#ibcon#*before return 0, iclass 40, count 0 2006.201.13:45:17.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:17.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:17.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.13:45:17.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.13:45:17.87$vck44/valo=4,624.99 2006.201.13:45:17.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.13:45:17.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.13:45:17.87#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:17.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:17.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:17.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:17.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.13:45:17.87#ibcon#first serial, iclass 4, count 0 2006.201.13:45:17.87#ibcon#enter sib2, iclass 4, count 0 2006.201.13:45:17.87#ibcon#flushed, iclass 4, count 0 2006.201.13:45:17.87#ibcon#about to write, iclass 4, count 0 2006.201.13:45:17.87#ibcon#wrote, iclass 4, count 0 2006.201.13:45:17.87#ibcon#about to read 3, iclass 4, count 0 2006.201.13:45:17.89#ibcon#read 3, iclass 4, count 0 2006.201.13:45:17.89#ibcon#about to read 4, iclass 4, count 0 2006.201.13:45:17.89#ibcon#read 4, iclass 4, count 0 2006.201.13:45:17.89#ibcon#about to read 5, iclass 4, count 0 2006.201.13:45:17.89#ibcon#read 5, iclass 4, count 0 2006.201.13:45:17.89#ibcon#about to read 6, iclass 4, count 0 2006.201.13:45:17.89#ibcon#read 6, iclass 4, count 0 2006.201.13:45:17.89#ibcon#end of sib2, iclass 4, count 0 2006.201.13:45:17.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.13:45:17.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.13:45:17.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:45:17.89#ibcon#*before write, iclass 4, count 0 2006.201.13:45:17.89#ibcon#enter sib2, iclass 4, count 0 2006.201.13:45:17.89#ibcon#flushed, iclass 4, count 0 2006.201.13:45:17.89#ibcon#about to write, iclass 4, count 0 2006.201.13:45:17.89#ibcon#wrote, iclass 4, count 0 2006.201.13:45:17.89#ibcon#about to read 3, iclass 4, count 0 2006.201.13:45:17.94#ibcon#read 3, iclass 4, count 0 2006.201.13:45:17.94#ibcon#about to read 4, iclass 4, count 0 2006.201.13:45:17.94#ibcon#read 4, iclass 4, count 0 2006.201.13:45:17.94#ibcon#about to read 5, iclass 4, count 0 2006.201.13:45:17.94#ibcon#read 5, iclass 4, count 0 2006.201.13:45:17.94#ibcon#about to read 6, iclass 4, count 0 2006.201.13:45:17.94#ibcon#read 6, iclass 4, count 0 2006.201.13:45:17.94#ibcon#end of sib2, iclass 4, count 0 2006.201.13:45:17.94#ibcon#*after write, iclass 4, count 0 2006.201.13:45:17.94#ibcon#*before return 0, iclass 4, count 0 2006.201.13:45:17.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:17.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:17.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.13:45:17.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.13:45:17.94$vck44/va=4,7 2006.201.13:45:17.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.13:45:17.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.13:45:17.94#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:17.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:17.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:17.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:17.99#ibcon#enter wrdev, iclass 6, count 2 2006.201.13:45:17.99#ibcon#first serial, iclass 6, count 2 2006.201.13:45:17.99#ibcon#enter sib2, iclass 6, count 2 2006.201.13:45:17.99#ibcon#flushed, iclass 6, count 2 2006.201.13:45:17.99#ibcon#about to write, iclass 6, count 2 2006.201.13:45:17.99#ibcon#wrote, iclass 6, count 2 2006.201.13:45:17.99#ibcon#about to read 3, iclass 6, count 2 2006.201.13:45:18.01#ibcon#read 3, iclass 6, count 2 2006.201.13:45:18.01#ibcon#about to read 4, iclass 6, count 2 2006.201.13:45:18.01#ibcon#read 4, iclass 6, count 2 2006.201.13:45:18.01#ibcon#about to read 5, iclass 6, count 2 2006.201.13:45:18.01#ibcon#read 5, iclass 6, count 2 2006.201.13:45:18.01#ibcon#about to read 6, iclass 6, count 2 2006.201.13:45:18.01#ibcon#read 6, iclass 6, count 2 2006.201.13:45:18.01#ibcon#end of sib2, iclass 6, count 2 2006.201.13:45:18.01#ibcon#*mode == 0, iclass 6, count 2 2006.201.13:45:18.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.13:45:18.01#ibcon#[25=AT04-07\r\n] 2006.201.13:45:18.01#ibcon#*before write, iclass 6, count 2 2006.201.13:45:18.01#ibcon#enter sib2, iclass 6, count 2 2006.201.13:45:18.01#ibcon#flushed, iclass 6, count 2 2006.201.13:45:18.01#ibcon#about to write, iclass 6, count 2 2006.201.13:45:18.01#ibcon#wrote, iclass 6, count 2 2006.201.13:45:18.01#ibcon#about to read 3, iclass 6, count 2 2006.201.13:45:18.04#ibcon#read 3, iclass 6, count 2 2006.201.13:45:18.04#ibcon#about to read 4, iclass 6, count 2 2006.201.13:45:18.04#ibcon#read 4, iclass 6, count 2 2006.201.13:45:18.04#ibcon#about to read 5, iclass 6, count 2 2006.201.13:45:18.04#ibcon#read 5, iclass 6, count 2 2006.201.13:45:18.04#ibcon#about to read 6, iclass 6, count 2 2006.201.13:45:18.04#ibcon#read 6, iclass 6, count 2 2006.201.13:45:18.04#ibcon#end of sib2, iclass 6, count 2 2006.201.13:45:18.04#ibcon#*after write, iclass 6, count 2 2006.201.13:45:18.04#ibcon#*before return 0, iclass 6, count 2 2006.201.13:45:18.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:18.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:18.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.13:45:18.04#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:18.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:18.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:18.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:18.16#ibcon#enter wrdev, iclass 6, count 0 2006.201.13:45:18.16#ibcon#first serial, iclass 6, count 0 2006.201.13:45:18.16#ibcon#enter sib2, iclass 6, count 0 2006.201.13:45:18.16#ibcon#flushed, iclass 6, count 0 2006.201.13:45:18.16#ibcon#about to write, iclass 6, count 0 2006.201.13:45:18.16#ibcon#wrote, iclass 6, count 0 2006.201.13:45:18.16#ibcon#about to read 3, iclass 6, count 0 2006.201.13:45:18.18#ibcon#read 3, iclass 6, count 0 2006.201.13:45:18.18#ibcon#about to read 4, iclass 6, count 0 2006.201.13:45:18.18#ibcon#read 4, iclass 6, count 0 2006.201.13:45:18.18#ibcon#about to read 5, iclass 6, count 0 2006.201.13:45:18.18#ibcon#read 5, iclass 6, count 0 2006.201.13:45:18.18#ibcon#about to read 6, iclass 6, count 0 2006.201.13:45:18.18#ibcon#read 6, iclass 6, count 0 2006.201.13:45:18.18#ibcon#end of sib2, iclass 6, count 0 2006.201.13:45:18.18#ibcon#*mode == 0, iclass 6, count 0 2006.201.13:45:18.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.13:45:18.18#ibcon#[25=USB\r\n] 2006.201.13:45:18.18#ibcon#*before write, iclass 6, count 0 2006.201.13:45:18.18#ibcon#enter sib2, iclass 6, count 0 2006.201.13:45:18.18#ibcon#flushed, iclass 6, count 0 2006.201.13:45:18.18#ibcon#about to write, iclass 6, count 0 2006.201.13:45:18.18#ibcon#wrote, iclass 6, count 0 2006.201.13:45:18.18#ibcon#about to read 3, iclass 6, count 0 2006.201.13:45:18.21#ibcon#read 3, iclass 6, count 0 2006.201.13:45:18.21#ibcon#about to read 4, iclass 6, count 0 2006.201.13:45:18.21#ibcon#read 4, iclass 6, count 0 2006.201.13:45:18.21#ibcon#about to read 5, iclass 6, count 0 2006.201.13:45:18.21#ibcon#read 5, iclass 6, count 0 2006.201.13:45:18.21#ibcon#about to read 6, iclass 6, count 0 2006.201.13:45:18.21#ibcon#read 6, iclass 6, count 0 2006.201.13:45:18.21#ibcon#end of sib2, iclass 6, count 0 2006.201.13:45:18.21#ibcon#*after write, iclass 6, count 0 2006.201.13:45:18.21#ibcon#*before return 0, iclass 6, count 0 2006.201.13:45:18.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:18.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:18.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.13:45:18.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.13:45:18.21$vck44/valo=5,734.99 2006.201.13:45:18.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.13:45:18.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.13:45:18.21#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:18.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:18.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:18.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:18.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.13:45:18.21#ibcon#first serial, iclass 10, count 0 2006.201.13:45:18.21#ibcon#enter sib2, iclass 10, count 0 2006.201.13:45:18.21#ibcon#flushed, iclass 10, count 0 2006.201.13:45:18.21#ibcon#about to write, iclass 10, count 0 2006.201.13:45:18.21#ibcon#wrote, iclass 10, count 0 2006.201.13:45:18.21#ibcon#about to read 3, iclass 10, count 0 2006.201.13:45:18.23#ibcon#read 3, iclass 10, count 0 2006.201.13:45:18.23#ibcon#about to read 4, iclass 10, count 0 2006.201.13:45:18.23#ibcon#read 4, iclass 10, count 0 2006.201.13:45:18.23#ibcon#about to read 5, iclass 10, count 0 2006.201.13:45:18.23#ibcon#read 5, iclass 10, count 0 2006.201.13:45:18.23#ibcon#about to read 6, iclass 10, count 0 2006.201.13:45:18.23#ibcon#read 6, iclass 10, count 0 2006.201.13:45:18.23#ibcon#end of sib2, iclass 10, count 0 2006.201.13:45:18.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.13:45:18.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.13:45:18.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:45:18.23#ibcon#*before write, iclass 10, count 0 2006.201.13:45:18.23#ibcon#enter sib2, iclass 10, count 0 2006.201.13:45:18.23#ibcon#flushed, iclass 10, count 0 2006.201.13:45:18.23#ibcon#about to write, iclass 10, count 0 2006.201.13:45:18.23#ibcon#wrote, iclass 10, count 0 2006.201.13:45:18.23#ibcon#about to read 3, iclass 10, count 0 2006.201.13:45:18.27#ibcon#read 3, iclass 10, count 0 2006.201.13:45:18.27#ibcon#about to read 4, iclass 10, count 0 2006.201.13:45:18.27#ibcon#read 4, iclass 10, count 0 2006.201.13:45:18.27#ibcon#about to read 5, iclass 10, count 0 2006.201.13:45:18.27#ibcon#read 5, iclass 10, count 0 2006.201.13:45:18.27#ibcon#about to read 6, iclass 10, count 0 2006.201.13:45:18.27#ibcon#read 6, iclass 10, count 0 2006.201.13:45:18.27#ibcon#end of sib2, iclass 10, count 0 2006.201.13:45:18.27#ibcon#*after write, iclass 10, count 0 2006.201.13:45:18.27#ibcon#*before return 0, iclass 10, count 0 2006.201.13:45:18.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:18.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:18.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.13:45:18.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.13:45:18.27$vck44/va=5,4 2006.201.13:45:18.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.13:45:18.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.13:45:18.27#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:18.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:18.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:18.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:18.33#ibcon#enter wrdev, iclass 12, count 2 2006.201.13:45:18.33#ibcon#first serial, iclass 12, count 2 2006.201.13:45:18.33#ibcon#enter sib2, iclass 12, count 2 2006.201.13:45:18.33#ibcon#flushed, iclass 12, count 2 2006.201.13:45:18.33#ibcon#about to write, iclass 12, count 2 2006.201.13:45:18.33#ibcon#wrote, iclass 12, count 2 2006.201.13:45:18.33#ibcon#about to read 3, iclass 12, count 2 2006.201.13:45:18.35#ibcon#read 3, iclass 12, count 2 2006.201.13:45:18.35#ibcon#about to read 4, iclass 12, count 2 2006.201.13:45:18.35#ibcon#read 4, iclass 12, count 2 2006.201.13:45:18.35#ibcon#about to read 5, iclass 12, count 2 2006.201.13:45:18.35#ibcon#read 5, iclass 12, count 2 2006.201.13:45:18.35#ibcon#about to read 6, iclass 12, count 2 2006.201.13:45:18.35#ibcon#read 6, iclass 12, count 2 2006.201.13:45:18.35#ibcon#end of sib2, iclass 12, count 2 2006.201.13:45:18.35#ibcon#*mode == 0, iclass 12, count 2 2006.201.13:45:18.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.13:45:18.35#ibcon#[25=AT05-04\r\n] 2006.201.13:45:18.35#ibcon#*before write, iclass 12, count 2 2006.201.13:45:18.35#ibcon#enter sib2, iclass 12, count 2 2006.201.13:45:18.35#ibcon#flushed, iclass 12, count 2 2006.201.13:45:18.35#ibcon#about to write, iclass 12, count 2 2006.201.13:45:18.35#ibcon#wrote, iclass 12, count 2 2006.201.13:45:18.35#ibcon#about to read 3, iclass 12, count 2 2006.201.13:45:18.38#ibcon#read 3, iclass 12, count 2 2006.201.13:45:18.38#ibcon#about to read 4, iclass 12, count 2 2006.201.13:45:18.38#ibcon#read 4, iclass 12, count 2 2006.201.13:45:18.38#ibcon#about to read 5, iclass 12, count 2 2006.201.13:45:18.38#ibcon#read 5, iclass 12, count 2 2006.201.13:45:18.38#ibcon#about to read 6, iclass 12, count 2 2006.201.13:45:18.38#ibcon#read 6, iclass 12, count 2 2006.201.13:45:18.38#ibcon#end of sib2, iclass 12, count 2 2006.201.13:45:18.38#ibcon#*after write, iclass 12, count 2 2006.201.13:45:18.38#ibcon#*before return 0, iclass 12, count 2 2006.201.13:45:18.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:18.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:18.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.13:45:18.38#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:18.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:18.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:18.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:18.50#ibcon#enter wrdev, iclass 12, count 0 2006.201.13:45:18.50#ibcon#first serial, iclass 12, count 0 2006.201.13:45:18.50#ibcon#enter sib2, iclass 12, count 0 2006.201.13:45:18.50#ibcon#flushed, iclass 12, count 0 2006.201.13:45:18.50#ibcon#about to write, iclass 12, count 0 2006.201.13:45:18.50#ibcon#wrote, iclass 12, count 0 2006.201.13:45:18.50#ibcon#about to read 3, iclass 12, count 0 2006.201.13:45:18.52#ibcon#read 3, iclass 12, count 0 2006.201.13:45:18.52#ibcon#about to read 4, iclass 12, count 0 2006.201.13:45:18.52#ibcon#read 4, iclass 12, count 0 2006.201.13:45:18.52#ibcon#about to read 5, iclass 12, count 0 2006.201.13:45:18.52#ibcon#read 5, iclass 12, count 0 2006.201.13:45:18.52#ibcon#about to read 6, iclass 12, count 0 2006.201.13:45:18.52#ibcon#read 6, iclass 12, count 0 2006.201.13:45:18.52#ibcon#end of sib2, iclass 12, count 0 2006.201.13:45:18.52#ibcon#*mode == 0, iclass 12, count 0 2006.201.13:45:18.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.13:45:18.52#ibcon#[25=USB\r\n] 2006.201.13:45:18.52#ibcon#*before write, iclass 12, count 0 2006.201.13:45:18.52#ibcon#enter sib2, iclass 12, count 0 2006.201.13:45:18.52#ibcon#flushed, iclass 12, count 0 2006.201.13:45:18.52#ibcon#about to write, iclass 12, count 0 2006.201.13:45:18.52#ibcon#wrote, iclass 12, count 0 2006.201.13:45:18.52#ibcon#about to read 3, iclass 12, count 0 2006.201.13:45:18.55#ibcon#read 3, iclass 12, count 0 2006.201.13:45:18.55#ibcon#about to read 4, iclass 12, count 0 2006.201.13:45:18.55#ibcon#read 4, iclass 12, count 0 2006.201.13:45:18.55#ibcon#about to read 5, iclass 12, count 0 2006.201.13:45:18.55#ibcon#read 5, iclass 12, count 0 2006.201.13:45:18.55#ibcon#about to read 6, iclass 12, count 0 2006.201.13:45:18.55#ibcon#read 6, iclass 12, count 0 2006.201.13:45:18.55#ibcon#end of sib2, iclass 12, count 0 2006.201.13:45:18.55#ibcon#*after write, iclass 12, count 0 2006.201.13:45:18.55#ibcon#*before return 0, iclass 12, count 0 2006.201.13:45:18.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:18.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:18.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.13:45:18.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.13:45:18.55$vck44/valo=6,814.99 2006.201.13:45:18.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.13:45:18.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.13:45:18.55#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:18.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:18.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:18.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:18.55#ibcon#enter wrdev, iclass 14, count 0 2006.201.13:45:18.55#ibcon#first serial, iclass 14, count 0 2006.201.13:45:18.55#ibcon#enter sib2, iclass 14, count 0 2006.201.13:45:18.55#ibcon#flushed, iclass 14, count 0 2006.201.13:45:18.55#ibcon#about to write, iclass 14, count 0 2006.201.13:45:18.55#ibcon#wrote, iclass 14, count 0 2006.201.13:45:18.55#ibcon#about to read 3, iclass 14, count 0 2006.201.13:45:18.57#ibcon#read 3, iclass 14, count 0 2006.201.13:45:18.57#ibcon#about to read 4, iclass 14, count 0 2006.201.13:45:18.57#ibcon#read 4, iclass 14, count 0 2006.201.13:45:18.57#ibcon#about to read 5, iclass 14, count 0 2006.201.13:45:18.57#ibcon#read 5, iclass 14, count 0 2006.201.13:45:18.57#ibcon#about to read 6, iclass 14, count 0 2006.201.13:45:18.57#ibcon#read 6, iclass 14, count 0 2006.201.13:45:18.57#ibcon#end of sib2, iclass 14, count 0 2006.201.13:45:18.57#ibcon#*mode == 0, iclass 14, count 0 2006.201.13:45:18.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.13:45:18.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:45:18.57#ibcon#*before write, iclass 14, count 0 2006.201.13:45:18.57#ibcon#enter sib2, iclass 14, count 0 2006.201.13:45:18.57#ibcon#flushed, iclass 14, count 0 2006.201.13:45:18.57#ibcon#about to write, iclass 14, count 0 2006.201.13:45:18.57#ibcon#wrote, iclass 14, count 0 2006.201.13:45:18.57#ibcon#about to read 3, iclass 14, count 0 2006.201.13:45:18.62#ibcon#read 3, iclass 14, count 0 2006.201.13:45:18.62#ibcon#about to read 4, iclass 14, count 0 2006.201.13:45:18.62#ibcon#read 4, iclass 14, count 0 2006.201.13:45:18.62#ibcon#about to read 5, iclass 14, count 0 2006.201.13:45:18.62#ibcon#read 5, iclass 14, count 0 2006.201.13:45:18.62#ibcon#about to read 6, iclass 14, count 0 2006.201.13:45:18.62#ibcon#read 6, iclass 14, count 0 2006.201.13:45:18.62#ibcon#end of sib2, iclass 14, count 0 2006.201.13:45:18.62#ibcon#*after write, iclass 14, count 0 2006.201.13:45:18.62#ibcon#*before return 0, iclass 14, count 0 2006.201.13:45:18.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:18.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:18.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.13:45:18.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.13:45:18.62$vck44/va=6,5 2006.201.13:45:18.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.13:45:18.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.13:45:18.62#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:18.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:18.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:18.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:18.67#ibcon#enter wrdev, iclass 16, count 2 2006.201.13:45:18.67#ibcon#first serial, iclass 16, count 2 2006.201.13:45:18.67#ibcon#enter sib2, iclass 16, count 2 2006.201.13:45:18.67#ibcon#flushed, iclass 16, count 2 2006.201.13:45:18.67#ibcon#about to write, iclass 16, count 2 2006.201.13:45:18.67#ibcon#wrote, iclass 16, count 2 2006.201.13:45:18.67#ibcon#about to read 3, iclass 16, count 2 2006.201.13:45:18.69#ibcon#read 3, iclass 16, count 2 2006.201.13:45:18.69#ibcon#about to read 4, iclass 16, count 2 2006.201.13:45:18.69#ibcon#read 4, iclass 16, count 2 2006.201.13:45:18.69#ibcon#about to read 5, iclass 16, count 2 2006.201.13:45:18.69#ibcon#read 5, iclass 16, count 2 2006.201.13:45:18.69#ibcon#about to read 6, iclass 16, count 2 2006.201.13:45:18.69#ibcon#read 6, iclass 16, count 2 2006.201.13:45:18.69#ibcon#end of sib2, iclass 16, count 2 2006.201.13:45:18.69#ibcon#*mode == 0, iclass 16, count 2 2006.201.13:45:18.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.13:45:18.69#ibcon#[25=AT06-05\r\n] 2006.201.13:45:18.69#ibcon#*before write, iclass 16, count 2 2006.201.13:45:18.69#ibcon#enter sib2, iclass 16, count 2 2006.201.13:45:18.69#ibcon#flushed, iclass 16, count 2 2006.201.13:45:18.69#ibcon#about to write, iclass 16, count 2 2006.201.13:45:18.69#ibcon#wrote, iclass 16, count 2 2006.201.13:45:18.69#ibcon#about to read 3, iclass 16, count 2 2006.201.13:45:18.72#ibcon#read 3, iclass 16, count 2 2006.201.13:45:18.72#ibcon#about to read 4, iclass 16, count 2 2006.201.13:45:18.72#ibcon#read 4, iclass 16, count 2 2006.201.13:45:18.72#ibcon#about to read 5, iclass 16, count 2 2006.201.13:45:18.72#ibcon#read 5, iclass 16, count 2 2006.201.13:45:18.72#ibcon#about to read 6, iclass 16, count 2 2006.201.13:45:18.72#ibcon#read 6, iclass 16, count 2 2006.201.13:45:18.72#ibcon#end of sib2, iclass 16, count 2 2006.201.13:45:18.72#ibcon#*after write, iclass 16, count 2 2006.201.13:45:18.72#ibcon#*before return 0, iclass 16, count 2 2006.201.13:45:18.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:18.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:18.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.13:45:18.72#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:18.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:18.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:18.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:18.84#ibcon#enter wrdev, iclass 16, count 0 2006.201.13:45:18.84#ibcon#first serial, iclass 16, count 0 2006.201.13:45:18.84#ibcon#enter sib2, iclass 16, count 0 2006.201.13:45:18.84#ibcon#flushed, iclass 16, count 0 2006.201.13:45:18.84#ibcon#about to write, iclass 16, count 0 2006.201.13:45:18.84#ibcon#wrote, iclass 16, count 0 2006.201.13:45:18.84#ibcon#about to read 3, iclass 16, count 0 2006.201.13:45:18.86#ibcon#read 3, iclass 16, count 0 2006.201.13:45:18.86#ibcon#about to read 4, iclass 16, count 0 2006.201.13:45:18.86#ibcon#read 4, iclass 16, count 0 2006.201.13:45:18.86#ibcon#about to read 5, iclass 16, count 0 2006.201.13:45:18.86#ibcon#read 5, iclass 16, count 0 2006.201.13:45:18.86#ibcon#about to read 6, iclass 16, count 0 2006.201.13:45:18.86#ibcon#read 6, iclass 16, count 0 2006.201.13:45:18.86#ibcon#end of sib2, iclass 16, count 0 2006.201.13:45:18.86#ibcon#*mode == 0, iclass 16, count 0 2006.201.13:45:18.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.13:45:18.86#ibcon#[25=USB\r\n] 2006.201.13:45:18.86#ibcon#*before write, iclass 16, count 0 2006.201.13:45:18.86#ibcon#enter sib2, iclass 16, count 0 2006.201.13:45:18.86#ibcon#flushed, iclass 16, count 0 2006.201.13:45:18.86#ibcon#about to write, iclass 16, count 0 2006.201.13:45:18.86#ibcon#wrote, iclass 16, count 0 2006.201.13:45:18.86#ibcon#about to read 3, iclass 16, count 0 2006.201.13:45:18.89#ibcon#read 3, iclass 16, count 0 2006.201.13:45:18.89#ibcon#about to read 4, iclass 16, count 0 2006.201.13:45:18.89#ibcon#read 4, iclass 16, count 0 2006.201.13:45:18.89#ibcon#about to read 5, iclass 16, count 0 2006.201.13:45:18.89#ibcon#read 5, iclass 16, count 0 2006.201.13:45:18.89#ibcon#about to read 6, iclass 16, count 0 2006.201.13:45:18.89#ibcon#read 6, iclass 16, count 0 2006.201.13:45:18.89#ibcon#end of sib2, iclass 16, count 0 2006.201.13:45:18.89#ibcon#*after write, iclass 16, count 0 2006.201.13:45:18.89#ibcon#*before return 0, iclass 16, count 0 2006.201.13:45:18.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:18.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:18.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.13:45:18.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.13:45:18.89$vck44/valo=7,864.99 2006.201.13:45:18.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.13:45:18.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.13:45:18.89#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:18.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:18.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:18.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:18.89#ibcon#enter wrdev, iclass 18, count 0 2006.201.13:45:18.89#ibcon#first serial, iclass 18, count 0 2006.201.13:45:18.89#ibcon#enter sib2, iclass 18, count 0 2006.201.13:45:18.89#ibcon#flushed, iclass 18, count 0 2006.201.13:45:18.89#ibcon#about to write, iclass 18, count 0 2006.201.13:45:18.89#ibcon#wrote, iclass 18, count 0 2006.201.13:45:18.89#ibcon#about to read 3, iclass 18, count 0 2006.201.13:45:18.91#ibcon#read 3, iclass 18, count 0 2006.201.13:45:18.91#ibcon#about to read 4, iclass 18, count 0 2006.201.13:45:18.91#ibcon#read 4, iclass 18, count 0 2006.201.13:45:18.91#ibcon#about to read 5, iclass 18, count 0 2006.201.13:45:18.91#ibcon#read 5, iclass 18, count 0 2006.201.13:45:18.91#ibcon#about to read 6, iclass 18, count 0 2006.201.13:45:18.91#ibcon#read 6, iclass 18, count 0 2006.201.13:45:18.91#ibcon#end of sib2, iclass 18, count 0 2006.201.13:45:18.91#ibcon#*mode == 0, iclass 18, count 0 2006.201.13:45:18.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.13:45:18.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:45:18.91#ibcon#*before write, iclass 18, count 0 2006.201.13:45:18.91#ibcon#enter sib2, iclass 18, count 0 2006.201.13:45:18.91#ibcon#flushed, iclass 18, count 0 2006.201.13:45:18.91#ibcon#about to write, iclass 18, count 0 2006.201.13:45:18.91#ibcon#wrote, iclass 18, count 0 2006.201.13:45:18.91#ibcon#about to read 3, iclass 18, count 0 2006.201.13:45:18.95#ibcon#read 3, iclass 18, count 0 2006.201.13:45:18.95#ibcon#about to read 4, iclass 18, count 0 2006.201.13:45:18.95#ibcon#read 4, iclass 18, count 0 2006.201.13:45:18.95#ibcon#about to read 5, iclass 18, count 0 2006.201.13:45:18.95#ibcon#read 5, iclass 18, count 0 2006.201.13:45:18.95#ibcon#about to read 6, iclass 18, count 0 2006.201.13:45:18.95#ibcon#read 6, iclass 18, count 0 2006.201.13:45:18.95#ibcon#end of sib2, iclass 18, count 0 2006.201.13:45:18.95#ibcon#*after write, iclass 18, count 0 2006.201.13:45:18.95#ibcon#*before return 0, iclass 18, count 0 2006.201.13:45:18.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:18.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:18.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.13:45:18.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.13:45:18.95$vck44/va=7,5 2006.201.13:45:18.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.13:45:18.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.13:45:18.95#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:18.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:19.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:19.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:19.01#ibcon#enter wrdev, iclass 20, count 2 2006.201.13:45:19.01#ibcon#first serial, iclass 20, count 2 2006.201.13:45:19.01#ibcon#enter sib2, iclass 20, count 2 2006.201.13:45:19.01#ibcon#flushed, iclass 20, count 2 2006.201.13:45:19.01#ibcon#about to write, iclass 20, count 2 2006.201.13:45:19.01#ibcon#wrote, iclass 20, count 2 2006.201.13:45:19.01#ibcon#about to read 3, iclass 20, count 2 2006.201.13:45:19.03#ibcon#read 3, iclass 20, count 2 2006.201.13:45:19.03#ibcon#about to read 4, iclass 20, count 2 2006.201.13:45:19.03#ibcon#read 4, iclass 20, count 2 2006.201.13:45:19.03#ibcon#about to read 5, iclass 20, count 2 2006.201.13:45:19.03#ibcon#read 5, iclass 20, count 2 2006.201.13:45:19.03#ibcon#about to read 6, iclass 20, count 2 2006.201.13:45:19.03#ibcon#read 6, iclass 20, count 2 2006.201.13:45:19.03#ibcon#end of sib2, iclass 20, count 2 2006.201.13:45:19.03#ibcon#*mode == 0, iclass 20, count 2 2006.201.13:45:19.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.13:45:19.03#ibcon#[25=AT07-05\r\n] 2006.201.13:45:19.03#ibcon#*before write, iclass 20, count 2 2006.201.13:45:19.03#ibcon#enter sib2, iclass 20, count 2 2006.201.13:45:19.03#ibcon#flushed, iclass 20, count 2 2006.201.13:45:19.03#ibcon#about to write, iclass 20, count 2 2006.201.13:45:19.03#ibcon#wrote, iclass 20, count 2 2006.201.13:45:19.03#ibcon#about to read 3, iclass 20, count 2 2006.201.13:45:19.06#ibcon#read 3, iclass 20, count 2 2006.201.13:45:19.06#ibcon#about to read 4, iclass 20, count 2 2006.201.13:45:19.06#ibcon#read 4, iclass 20, count 2 2006.201.13:45:19.06#ibcon#about to read 5, iclass 20, count 2 2006.201.13:45:19.06#ibcon#read 5, iclass 20, count 2 2006.201.13:45:19.06#ibcon#about to read 6, iclass 20, count 2 2006.201.13:45:19.06#ibcon#read 6, iclass 20, count 2 2006.201.13:45:19.06#ibcon#end of sib2, iclass 20, count 2 2006.201.13:45:19.06#ibcon#*after write, iclass 20, count 2 2006.201.13:45:19.06#ibcon#*before return 0, iclass 20, count 2 2006.201.13:45:19.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:19.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:19.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.13:45:19.06#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:19.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:19.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:19.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:19.18#ibcon#enter wrdev, iclass 20, count 0 2006.201.13:45:19.18#ibcon#first serial, iclass 20, count 0 2006.201.13:45:19.18#ibcon#enter sib2, iclass 20, count 0 2006.201.13:45:19.18#ibcon#flushed, iclass 20, count 0 2006.201.13:45:19.18#ibcon#about to write, iclass 20, count 0 2006.201.13:45:19.18#ibcon#wrote, iclass 20, count 0 2006.201.13:45:19.18#ibcon#about to read 3, iclass 20, count 0 2006.201.13:45:19.20#ibcon#read 3, iclass 20, count 0 2006.201.13:45:19.20#ibcon#about to read 4, iclass 20, count 0 2006.201.13:45:19.20#ibcon#read 4, iclass 20, count 0 2006.201.13:45:19.20#ibcon#about to read 5, iclass 20, count 0 2006.201.13:45:19.20#ibcon#read 5, iclass 20, count 0 2006.201.13:45:19.20#ibcon#about to read 6, iclass 20, count 0 2006.201.13:45:19.20#ibcon#read 6, iclass 20, count 0 2006.201.13:45:19.20#ibcon#end of sib2, iclass 20, count 0 2006.201.13:45:19.20#ibcon#*mode == 0, iclass 20, count 0 2006.201.13:45:19.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.13:45:19.20#ibcon#[25=USB\r\n] 2006.201.13:45:19.20#ibcon#*before write, iclass 20, count 0 2006.201.13:45:19.20#ibcon#enter sib2, iclass 20, count 0 2006.201.13:45:19.20#ibcon#flushed, iclass 20, count 0 2006.201.13:45:19.20#ibcon#about to write, iclass 20, count 0 2006.201.13:45:19.20#ibcon#wrote, iclass 20, count 0 2006.201.13:45:19.20#ibcon#about to read 3, iclass 20, count 0 2006.201.13:45:19.23#ibcon#read 3, iclass 20, count 0 2006.201.13:45:19.23#ibcon#about to read 4, iclass 20, count 0 2006.201.13:45:19.23#ibcon#read 4, iclass 20, count 0 2006.201.13:45:19.23#ibcon#about to read 5, iclass 20, count 0 2006.201.13:45:19.23#ibcon#read 5, iclass 20, count 0 2006.201.13:45:19.23#ibcon#about to read 6, iclass 20, count 0 2006.201.13:45:19.23#ibcon#read 6, iclass 20, count 0 2006.201.13:45:19.23#ibcon#end of sib2, iclass 20, count 0 2006.201.13:45:19.23#ibcon#*after write, iclass 20, count 0 2006.201.13:45:19.23#ibcon#*before return 0, iclass 20, count 0 2006.201.13:45:19.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:19.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:19.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.13:45:19.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.13:45:19.23$vck44/valo=8,884.99 2006.201.13:45:19.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.13:45:19.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.13:45:19.23#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:19.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:19.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:19.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:19.23#ibcon#enter wrdev, iclass 22, count 0 2006.201.13:45:19.23#ibcon#first serial, iclass 22, count 0 2006.201.13:45:19.23#ibcon#enter sib2, iclass 22, count 0 2006.201.13:45:19.23#ibcon#flushed, iclass 22, count 0 2006.201.13:45:19.23#ibcon#about to write, iclass 22, count 0 2006.201.13:45:19.23#ibcon#wrote, iclass 22, count 0 2006.201.13:45:19.23#ibcon#about to read 3, iclass 22, count 0 2006.201.13:45:19.25#ibcon#read 3, iclass 22, count 0 2006.201.13:45:19.25#ibcon#about to read 4, iclass 22, count 0 2006.201.13:45:19.25#ibcon#read 4, iclass 22, count 0 2006.201.13:45:19.25#ibcon#about to read 5, iclass 22, count 0 2006.201.13:45:19.25#ibcon#read 5, iclass 22, count 0 2006.201.13:45:19.25#ibcon#about to read 6, iclass 22, count 0 2006.201.13:45:19.25#ibcon#read 6, iclass 22, count 0 2006.201.13:45:19.25#ibcon#end of sib2, iclass 22, count 0 2006.201.13:45:19.25#ibcon#*mode == 0, iclass 22, count 0 2006.201.13:45:19.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.13:45:19.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:45:19.25#ibcon#*before write, iclass 22, count 0 2006.201.13:45:19.25#ibcon#enter sib2, iclass 22, count 0 2006.201.13:45:19.25#ibcon#flushed, iclass 22, count 0 2006.201.13:45:19.25#ibcon#about to write, iclass 22, count 0 2006.201.13:45:19.25#ibcon#wrote, iclass 22, count 0 2006.201.13:45:19.25#ibcon#about to read 3, iclass 22, count 0 2006.201.13:45:19.29#ibcon#read 3, iclass 22, count 0 2006.201.13:45:19.29#ibcon#about to read 4, iclass 22, count 0 2006.201.13:45:19.29#ibcon#read 4, iclass 22, count 0 2006.201.13:45:19.29#ibcon#about to read 5, iclass 22, count 0 2006.201.13:45:19.29#ibcon#read 5, iclass 22, count 0 2006.201.13:45:19.29#ibcon#about to read 6, iclass 22, count 0 2006.201.13:45:19.29#ibcon#read 6, iclass 22, count 0 2006.201.13:45:19.29#ibcon#end of sib2, iclass 22, count 0 2006.201.13:45:19.29#ibcon#*after write, iclass 22, count 0 2006.201.13:45:19.29#ibcon#*before return 0, iclass 22, count 0 2006.201.13:45:19.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:19.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:19.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.13:45:19.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.13:45:19.29$vck44/va=8,4 2006.201.13:45:19.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.13:45:19.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.13:45:19.29#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:19.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.13:45:19.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.13:45:19.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.13:45:19.35#ibcon#enter wrdev, iclass 24, count 2 2006.201.13:45:19.35#ibcon#first serial, iclass 24, count 2 2006.201.13:45:19.35#ibcon#enter sib2, iclass 24, count 2 2006.201.13:45:19.35#ibcon#flushed, iclass 24, count 2 2006.201.13:45:19.35#ibcon#about to write, iclass 24, count 2 2006.201.13:45:19.35#ibcon#wrote, iclass 24, count 2 2006.201.13:45:19.35#ibcon#about to read 3, iclass 24, count 2 2006.201.13:45:19.37#ibcon#read 3, iclass 24, count 2 2006.201.13:45:19.37#ibcon#about to read 4, iclass 24, count 2 2006.201.13:45:19.37#ibcon#read 4, iclass 24, count 2 2006.201.13:45:19.37#ibcon#about to read 5, iclass 24, count 2 2006.201.13:45:19.37#ibcon#read 5, iclass 24, count 2 2006.201.13:45:19.37#ibcon#about to read 6, iclass 24, count 2 2006.201.13:45:19.37#ibcon#read 6, iclass 24, count 2 2006.201.13:45:19.37#ibcon#end of sib2, iclass 24, count 2 2006.201.13:45:19.37#ibcon#*mode == 0, iclass 24, count 2 2006.201.13:45:19.37#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.13:45:19.37#ibcon#[25=AT08-04\r\n] 2006.201.13:45:19.37#ibcon#*before write, iclass 24, count 2 2006.201.13:45:19.37#ibcon#enter sib2, iclass 24, count 2 2006.201.13:45:19.37#ibcon#flushed, iclass 24, count 2 2006.201.13:45:19.37#ibcon#about to write, iclass 24, count 2 2006.201.13:45:19.37#ibcon#wrote, iclass 24, count 2 2006.201.13:45:19.37#ibcon#about to read 3, iclass 24, count 2 2006.201.13:45:19.40#ibcon#read 3, iclass 24, count 2 2006.201.13:45:19.40#ibcon#about to read 4, iclass 24, count 2 2006.201.13:45:19.40#ibcon#read 4, iclass 24, count 2 2006.201.13:45:19.40#ibcon#about to read 5, iclass 24, count 2 2006.201.13:45:19.40#ibcon#read 5, iclass 24, count 2 2006.201.13:45:19.40#ibcon#about to read 6, iclass 24, count 2 2006.201.13:45:19.40#ibcon#read 6, iclass 24, count 2 2006.201.13:45:19.40#ibcon#end of sib2, iclass 24, count 2 2006.201.13:45:19.40#ibcon#*after write, iclass 24, count 2 2006.201.13:45:19.40#ibcon#*before return 0, iclass 24, count 2 2006.201.13:45:19.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.13:45:19.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.13:45:19.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.13:45:19.40#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:19.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.13:45:19.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.13:45:19.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.13:45:19.52#ibcon#enter wrdev, iclass 24, count 0 2006.201.13:45:19.52#ibcon#first serial, iclass 24, count 0 2006.201.13:45:19.52#ibcon#enter sib2, iclass 24, count 0 2006.201.13:45:19.52#ibcon#flushed, iclass 24, count 0 2006.201.13:45:19.52#ibcon#about to write, iclass 24, count 0 2006.201.13:45:19.52#ibcon#wrote, iclass 24, count 0 2006.201.13:45:19.52#ibcon#about to read 3, iclass 24, count 0 2006.201.13:45:19.54#ibcon#read 3, iclass 24, count 0 2006.201.13:45:19.54#ibcon#about to read 4, iclass 24, count 0 2006.201.13:45:19.54#ibcon#read 4, iclass 24, count 0 2006.201.13:45:19.54#ibcon#about to read 5, iclass 24, count 0 2006.201.13:45:19.54#ibcon#read 5, iclass 24, count 0 2006.201.13:45:19.54#ibcon#about to read 6, iclass 24, count 0 2006.201.13:45:19.54#ibcon#read 6, iclass 24, count 0 2006.201.13:45:19.54#ibcon#end of sib2, iclass 24, count 0 2006.201.13:45:19.54#ibcon#*mode == 0, iclass 24, count 0 2006.201.13:45:19.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.13:45:19.54#ibcon#[25=USB\r\n] 2006.201.13:45:19.54#ibcon#*before write, iclass 24, count 0 2006.201.13:45:19.54#ibcon#enter sib2, iclass 24, count 0 2006.201.13:45:19.54#ibcon#flushed, iclass 24, count 0 2006.201.13:45:19.54#ibcon#about to write, iclass 24, count 0 2006.201.13:45:19.54#ibcon#wrote, iclass 24, count 0 2006.201.13:45:19.54#ibcon#about to read 3, iclass 24, count 0 2006.201.13:45:19.57#ibcon#read 3, iclass 24, count 0 2006.201.13:45:19.57#ibcon#about to read 4, iclass 24, count 0 2006.201.13:45:19.57#ibcon#read 4, iclass 24, count 0 2006.201.13:45:19.57#ibcon#about to read 5, iclass 24, count 0 2006.201.13:45:19.57#ibcon#read 5, iclass 24, count 0 2006.201.13:45:19.57#ibcon#about to read 6, iclass 24, count 0 2006.201.13:45:19.57#ibcon#read 6, iclass 24, count 0 2006.201.13:45:19.57#ibcon#end of sib2, iclass 24, count 0 2006.201.13:45:19.57#ibcon#*after write, iclass 24, count 0 2006.201.13:45:19.57#ibcon#*before return 0, iclass 24, count 0 2006.201.13:45:19.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.13:45:19.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.13:45:19.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.13:45:19.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.13:45:19.57$vck44/vblo=1,629.99 2006.201.13:45:19.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.13:45:19.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.13:45:19.57#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:19.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:19.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:19.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:19.57#ibcon#enter wrdev, iclass 26, count 0 2006.201.13:45:19.57#ibcon#first serial, iclass 26, count 0 2006.201.13:45:19.57#ibcon#enter sib2, iclass 26, count 0 2006.201.13:45:19.57#ibcon#flushed, iclass 26, count 0 2006.201.13:45:19.57#ibcon#about to write, iclass 26, count 0 2006.201.13:45:19.57#ibcon#wrote, iclass 26, count 0 2006.201.13:45:19.57#ibcon#about to read 3, iclass 26, count 0 2006.201.13:45:19.59#ibcon#read 3, iclass 26, count 0 2006.201.13:45:19.59#ibcon#about to read 4, iclass 26, count 0 2006.201.13:45:19.59#ibcon#read 4, iclass 26, count 0 2006.201.13:45:19.59#ibcon#about to read 5, iclass 26, count 0 2006.201.13:45:19.59#ibcon#read 5, iclass 26, count 0 2006.201.13:45:19.59#ibcon#about to read 6, iclass 26, count 0 2006.201.13:45:19.59#ibcon#read 6, iclass 26, count 0 2006.201.13:45:19.59#ibcon#end of sib2, iclass 26, count 0 2006.201.13:45:19.59#ibcon#*mode == 0, iclass 26, count 0 2006.201.13:45:19.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.13:45:19.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:45:19.59#ibcon#*before write, iclass 26, count 0 2006.201.13:45:19.59#ibcon#enter sib2, iclass 26, count 0 2006.201.13:45:19.59#ibcon#flushed, iclass 26, count 0 2006.201.13:45:19.59#ibcon#about to write, iclass 26, count 0 2006.201.13:45:19.59#ibcon#wrote, iclass 26, count 0 2006.201.13:45:19.59#ibcon#about to read 3, iclass 26, count 0 2006.201.13:45:19.64#ibcon#read 3, iclass 26, count 0 2006.201.13:45:19.64#ibcon#about to read 4, iclass 26, count 0 2006.201.13:45:19.64#ibcon#read 4, iclass 26, count 0 2006.201.13:45:19.64#ibcon#about to read 5, iclass 26, count 0 2006.201.13:45:19.64#ibcon#read 5, iclass 26, count 0 2006.201.13:45:19.64#ibcon#about to read 6, iclass 26, count 0 2006.201.13:45:19.64#ibcon#read 6, iclass 26, count 0 2006.201.13:45:19.64#ibcon#end of sib2, iclass 26, count 0 2006.201.13:45:19.64#ibcon#*after write, iclass 26, count 0 2006.201.13:45:19.64#ibcon#*before return 0, iclass 26, count 0 2006.201.13:45:19.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:19.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.13:45:19.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.13:45:19.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.13:45:19.64$vck44/vb=1,4 2006.201.13:45:19.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.13:45:19.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.13:45:19.64#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:19.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:19.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:19.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:19.64#ibcon#enter wrdev, iclass 28, count 2 2006.201.13:45:19.64#ibcon#first serial, iclass 28, count 2 2006.201.13:45:19.64#ibcon#enter sib2, iclass 28, count 2 2006.201.13:45:19.64#ibcon#flushed, iclass 28, count 2 2006.201.13:45:19.64#ibcon#about to write, iclass 28, count 2 2006.201.13:45:19.64#ibcon#wrote, iclass 28, count 2 2006.201.13:45:19.64#ibcon#about to read 3, iclass 28, count 2 2006.201.13:45:19.66#ibcon#read 3, iclass 28, count 2 2006.201.13:45:19.66#ibcon#about to read 4, iclass 28, count 2 2006.201.13:45:19.66#ibcon#read 4, iclass 28, count 2 2006.201.13:45:19.66#ibcon#about to read 5, iclass 28, count 2 2006.201.13:45:19.66#ibcon#read 5, iclass 28, count 2 2006.201.13:45:19.66#ibcon#about to read 6, iclass 28, count 2 2006.201.13:45:19.66#ibcon#read 6, iclass 28, count 2 2006.201.13:45:19.66#ibcon#end of sib2, iclass 28, count 2 2006.201.13:45:19.66#ibcon#*mode == 0, iclass 28, count 2 2006.201.13:45:19.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.13:45:19.66#ibcon#[27=AT01-04\r\n] 2006.201.13:45:19.66#ibcon#*before write, iclass 28, count 2 2006.201.13:45:19.66#ibcon#enter sib2, iclass 28, count 2 2006.201.13:45:19.66#ibcon#flushed, iclass 28, count 2 2006.201.13:45:19.66#ibcon#about to write, iclass 28, count 2 2006.201.13:45:19.66#ibcon#wrote, iclass 28, count 2 2006.201.13:45:19.66#ibcon#about to read 3, iclass 28, count 2 2006.201.13:45:19.69#ibcon#read 3, iclass 28, count 2 2006.201.13:45:19.69#ibcon#about to read 4, iclass 28, count 2 2006.201.13:45:19.69#ibcon#read 4, iclass 28, count 2 2006.201.13:45:19.69#ibcon#about to read 5, iclass 28, count 2 2006.201.13:45:19.69#ibcon#read 5, iclass 28, count 2 2006.201.13:45:19.69#ibcon#about to read 6, iclass 28, count 2 2006.201.13:45:19.69#ibcon#read 6, iclass 28, count 2 2006.201.13:45:19.69#ibcon#end of sib2, iclass 28, count 2 2006.201.13:45:19.69#ibcon#*after write, iclass 28, count 2 2006.201.13:45:19.69#ibcon#*before return 0, iclass 28, count 2 2006.201.13:45:19.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:19.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.13:45:19.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.13:45:19.69#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:19.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:19.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:19.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:19.81#ibcon#enter wrdev, iclass 28, count 0 2006.201.13:45:19.81#ibcon#first serial, iclass 28, count 0 2006.201.13:45:19.81#ibcon#enter sib2, iclass 28, count 0 2006.201.13:45:19.81#ibcon#flushed, iclass 28, count 0 2006.201.13:45:19.81#ibcon#about to write, iclass 28, count 0 2006.201.13:45:19.81#ibcon#wrote, iclass 28, count 0 2006.201.13:45:19.81#ibcon#about to read 3, iclass 28, count 0 2006.201.13:45:19.83#ibcon#read 3, iclass 28, count 0 2006.201.13:45:19.83#ibcon#about to read 4, iclass 28, count 0 2006.201.13:45:19.83#ibcon#read 4, iclass 28, count 0 2006.201.13:45:19.83#ibcon#about to read 5, iclass 28, count 0 2006.201.13:45:19.83#ibcon#read 5, iclass 28, count 0 2006.201.13:45:19.83#ibcon#about to read 6, iclass 28, count 0 2006.201.13:45:19.83#ibcon#read 6, iclass 28, count 0 2006.201.13:45:19.83#ibcon#end of sib2, iclass 28, count 0 2006.201.13:45:19.83#ibcon#*mode == 0, iclass 28, count 0 2006.201.13:45:19.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.13:45:19.83#ibcon#[27=USB\r\n] 2006.201.13:45:19.83#ibcon#*before write, iclass 28, count 0 2006.201.13:45:19.83#ibcon#enter sib2, iclass 28, count 0 2006.201.13:45:19.83#ibcon#flushed, iclass 28, count 0 2006.201.13:45:19.83#ibcon#about to write, iclass 28, count 0 2006.201.13:45:19.83#ibcon#wrote, iclass 28, count 0 2006.201.13:45:19.83#ibcon#about to read 3, iclass 28, count 0 2006.201.13:45:19.86#ibcon#read 3, iclass 28, count 0 2006.201.13:45:19.86#ibcon#about to read 4, iclass 28, count 0 2006.201.13:45:19.86#ibcon#read 4, iclass 28, count 0 2006.201.13:45:19.86#ibcon#about to read 5, iclass 28, count 0 2006.201.13:45:19.86#ibcon#read 5, iclass 28, count 0 2006.201.13:45:19.86#ibcon#about to read 6, iclass 28, count 0 2006.201.13:45:19.86#ibcon#read 6, iclass 28, count 0 2006.201.13:45:19.86#ibcon#end of sib2, iclass 28, count 0 2006.201.13:45:19.86#ibcon#*after write, iclass 28, count 0 2006.201.13:45:19.86#ibcon#*before return 0, iclass 28, count 0 2006.201.13:45:19.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:19.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.13:45:19.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.13:45:19.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.13:45:19.86$vck44/vblo=2,634.99 2006.201.13:45:19.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.13:45:19.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.13:45:19.86#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:19.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.13:45:19.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.13:45:19.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.13:45:19.86#ibcon#enter wrdev, iclass 30, count 0 2006.201.13:45:19.86#ibcon#first serial, iclass 30, count 0 2006.201.13:45:19.86#ibcon#enter sib2, iclass 30, count 0 2006.201.13:45:19.86#ibcon#flushed, iclass 30, count 0 2006.201.13:45:19.86#ibcon#about to write, iclass 30, count 0 2006.201.13:45:19.86#ibcon#wrote, iclass 30, count 0 2006.201.13:45:19.86#ibcon#about to read 3, iclass 30, count 0 2006.201.13:45:19.88#ibcon#read 3, iclass 30, count 0 2006.201.13:45:19.88#ibcon#about to read 4, iclass 30, count 0 2006.201.13:45:19.88#ibcon#read 4, iclass 30, count 0 2006.201.13:45:19.88#ibcon#about to read 5, iclass 30, count 0 2006.201.13:45:19.88#ibcon#read 5, iclass 30, count 0 2006.201.13:45:19.88#ibcon#about to read 6, iclass 30, count 0 2006.201.13:45:19.88#ibcon#read 6, iclass 30, count 0 2006.201.13:45:19.88#ibcon#end of sib2, iclass 30, count 0 2006.201.13:45:19.88#ibcon#*mode == 0, iclass 30, count 0 2006.201.13:45:19.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.13:45:19.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:45:19.88#ibcon#*before write, iclass 30, count 0 2006.201.13:45:19.88#ibcon#enter sib2, iclass 30, count 0 2006.201.13:45:19.88#ibcon#flushed, iclass 30, count 0 2006.201.13:45:19.88#ibcon#about to write, iclass 30, count 0 2006.201.13:45:19.88#ibcon#wrote, iclass 30, count 0 2006.201.13:45:19.88#ibcon#about to read 3, iclass 30, count 0 2006.201.13:45:19.92#ibcon#read 3, iclass 30, count 0 2006.201.13:45:19.92#ibcon#about to read 4, iclass 30, count 0 2006.201.13:45:19.92#ibcon#read 4, iclass 30, count 0 2006.201.13:45:19.92#ibcon#about to read 5, iclass 30, count 0 2006.201.13:45:19.92#ibcon#read 5, iclass 30, count 0 2006.201.13:45:19.92#ibcon#about to read 6, iclass 30, count 0 2006.201.13:45:19.92#ibcon#read 6, iclass 30, count 0 2006.201.13:45:19.92#ibcon#end of sib2, iclass 30, count 0 2006.201.13:45:19.92#ibcon#*after write, iclass 30, count 0 2006.201.13:45:19.92#ibcon#*before return 0, iclass 30, count 0 2006.201.13:45:19.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.13:45:19.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.13:45:19.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.13:45:19.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.13:45:19.92$vck44/vb=2,5 2006.201.13:45:19.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.13:45:19.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.13:45:19.92#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:19.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.13:45:19.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.13:45:19.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.13:45:19.98#ibcon#enter wrdev, iclass 32, count 2 2006.201.13:45:19.98#ibcon#first serial, iclass 32, count 2 2006.201.13:45:19.98#ibcon#enter sib2, iclass 32, count 2 2006.201.13:45:19.98#ibcon#flushed, iclass 32, count 2 2006.201.13:45:19.98#ibcon#about to write, iclass 32, count 2 2006.201.13:45:19.98#ibcon#wrote, iclass 32, count 2 2006.201.13:45:19.98#ibcon#about to read 3, iclass 32, count 2 2006.201.13:45:20.00#ibcon#read 3, iclass 32, count 2 2006.201.13:45:20.00#ibcon#about to read 4, iclass 32, count 2 2006.201.13:45:20.00#ibcon#read 4, iclass 32, count 2 2006.201.13:45:20.00#ibcon#about to read 5, iclass 32, count 2 2006.201.13:45:20.00#ibcon#read 5, iclass 32, count 2 2006.201.13:45:20.00#ibcon#about to read 6, iclass 32, count 2 2006.201.13:45:20.00#ibcon#read 6, iclass 32, count 2 2006.201.13:45:20.00#ibcon#end of sib2, iclass 32, count 2 2006.201.13:45:20.00#ibcon#*mode == 0, iclass 32, count 2 2006.201.13:45:20.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.13:45:20.00#ibcon#[27=AT02-05\r\n] 2006.201.13:45:20.00#ibcon#*before write, iclass 32, count 2 2006.201.13:45:20.00#ibcon#enter sib2, iclass 32, count 2 2006.201.13:45:20.00#ibcon#flushed, iclass 32, count 2 2006.201.13:45:20.00#ibcon#about to write, iclass 32, count 2 2006.201.13:45:20.00#ibcon#wrote, iclass 32, count 2 2006.201.13:45:20.00#ibcon#about to read 3, iclass 32, count 2 2006.201.13:45:20.03#ibcon#read 3, iclass 32, count 2 2006.201.13:45:20.03#ibcon#about to read 4, iclass 32, count 2 2006.201.13:45:20.03#ibcon#read 4, iclass 32, count 2 2006.201.13:45:20.03#ibcon#about to read 5, iclass 32, count 2 2006.201.13:45:20.03#ibcon#read 5, iclass 32, count 2 2006.201.13:45:20.03#ibcon#about to read 6, iclass 32, count 2 2006.201.13:45:20.03#ibcon#read 6, iclass 32, count 2 2006.201.13:45:20.03#ibcon#end of sib2, iclass 32, count 2 2006.201.13:45:20.03#ibcon#*after write, iclass 32, count 2 2006.201.13:45:20.03#ibcon#*before return 0, iclass 32, count 2 2006.201.13:45:20.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.13:45:20.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.13:45:20.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.13:45:20.03#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:20.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.13:45:20.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.13:45:20.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.13:45:20.15#ibcon#enter wrdev, iclass 32, count 0 2006.201.13:45:20.15#ibcon#first serial, iclass 32, count 0 2006.201.13:45:20.15#ibcon#enter sib2, iclass 32, count 0 2006.201.13:45:20.15#ibcon#flushed, iclass 32, count 0 2006.201.13:45:20.15#ibcon#about to write, iclass 32, count 0 2006.201.13:45:20.15#ibcon#wrote, iclass 32, count 0 2006.201.13:45:20.15#ibcon#about to read 3, iclass 32, count 0 2006.201.13:45:20.17#ibcon#read 3, iclass 32, count 0 2006.201.13:45:20.17#ibcon#about to read 4, iclass 32, count 0 2006.201.13:45:20.17#ibcon#read 4, iclass 32, count 0 2006.201.13:45:20.17#ibcon#about to read 5, iclass 32, count 0 2006.201.13:45:20.17#ibcon#read 5, iclass 32, count 0 2006.201.13:45:20.17#ibcon#about to read 6, iclass 32, count 0 2006.201.13:45:20.17#ibcon#read 6, iclass 32, count 0 2006.201.13:45:20.17#ibcon#end of sib2, iclass 32, count 0 2006.201.13:45:20.17#ibcon#*mode == 0, iclass 32, count 0 2006.201.13:45:20.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.13:45:20.17#ibcon#[27=USB\r\n] 2006.201.13:45:20.17#ibcon#*before write, iclass 32, count 0 2006.201.13:45:20.17#ibcon#enter sib2, iclass 32, count 0 2006.201.13:45:20.17#ibcon#flushed, iclass 32, count 0 2006.201.13:45:20.17#ibcon#about to write, iclass 32, count 0 2006.201.13:45:20.17#ibcon#wrote, iclass 32, count 0 2006.201.13:45:20.17#ibcon#about to read 3, iclass 32, count 0 2006.201.13:45:20.20#ibcon#read 3, iclass 32, count 0 2006.201.13:45:20.20#ibcon#about to read 4, iclass 32, count 0 2006.201.13:45:20.20#ibcon#read 4, iclass 32, count 0 2006.201.13:45:20.20#ibcon#about to read 5, iclass 32, count 0 2006.201.13:45:20.20#ibcon#read 5, iclass 32, count 0 2006.201.13:45:20.20#ibcon#about to read 6, iclass 32, count 0 2006.201.13:45:20.20#ibcon#read 6, iclass 32, count 0 2006.201.13:45:20.20#ibcon#end of sib2, iclass 32, count 0 2006.201.13:45:20.20#ibcon#*after write, iclass 32, count 0 2006.201.13:45:20.20#ibcon#*before return 0, iclass 32, count 0 2006.201.13:45:20.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.13:45:20.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.13:45:20.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.13:45:20.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.13:45:20.20$vck44/vblo=3,649.99 2006.201.13:45:20.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.13:45:20.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.13:45:20.20#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:20.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:20.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:20.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:20.20#ibcon#enter wrdev, iclass 34, count 0 2006.201.13:45:20.20#ibcon#first serial, iclass 34, count 0 2006.201.13:45:20.20#ibcon#enter sib2, iclass 34, count 0 2006.201.13:45:20.20#ibcon#flushed, iclass 34, count 0 2006.201.13:45:20.20#ibcon#about to write, iclass 34, count 0 2006.201.13:45:20.20#ibcon#wrote, iclass 34, count 0 2006.201.13:45:20.20#ibcon#about to read 3, iclass 34, count 0 2006.201.13:45:20.22#ibcon#read 3, iclass 34, count 0 2006.201.13:45:20.22#ibcon#about to read 4, iclass 34, count 0 2006.201.13:45:20.22#ibcon#read 4, iclass 34, count 0 2006.201.13:45:20.22#ibcon#about to read 5, iclass 34, count 0 2006.201.13:45:20.22#ibcon#read 5, iclass 34, count 0 2006.201.13:45:20.22#ibcon#about to read 6, iclass 34, count 0 2006.201.13:45:20.22#ibcon#read 6, iclass 34, count 0 2006.201.13:45:20.22#ibcon#end of sib2, iclass 34, count 0 2006.201.13:45:20.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.13:45:20.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.13:45:20.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:45:20.22#ibcon#*before write, iclass 34, count 0 2006.201.13:45:20.22#ibcon#enter sib2, iclass 34, count 0 2006.201.13:45:20.22#ibcon#flushed, iclass 34, count 0 2006.201.13:45:20.22#ibcon#about to write, iclass 34, count 0 2006.201.13:45:20.22#ibcon#wrote, iclass 34, count 0 2006.201.13:45:20.22#ibcon#about to read 3, iclass 34, count 0 2006.201.13:45:20.26#ibcon#read 3, iclass 34, count 0 2006.201.13:45:20.26#ibcon#about to read 4, iclass 34, count 0 2006.201.13:45:20.26#ibcon#read 4, iclass 34, count 0 2006.201.13:45:20.26#ibcon#about to read 5, iclass 34, count 0 2006.201.13:45:20.26#ibcon#read 5, iclass 34, count 0 2006.201.13:45:20.26#ibcon#about to read 6, iclass 34, count 0 2006.201.13:45:20.26#ibcon#read 6, iclass 34, count 0 2006.201.13:45:20.26#ibcon#end of sib2, iclass 34, count 0 2006.201.13:45:20.26#ibcon#*after write, iclass 34, count 0 2006.201.13:45:20.26#ibcon#*before return 0, iclass 34, count 0 2006.201.13:45:20.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:20.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.13:45:20.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.13:45:20.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.13:45:20.26$vck44/vb=3,4 2006.201.13:45:20.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.13:45:20.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.13:45:20.26#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:20.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:20.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:20.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:20.32#ibcon#enter wrdev, iclass 36, count 2 2006.201.13:45:20.32#ibcon#first serial, iclass 36, count 2 2006.201.13:45:20.32#ibcon#enter sib2, iclass 36, count 2 2006.201.13:45:20.32#ibcon#flushed, iclass 36, count 2 2006.201.13:45:20.32#ibcon#about to write, iclass 36, count 2 2006.201.13:45:20.32#ibcon#wrote, iclass 36, count 2 2006.201.13:45:20.32#ibcon#about to read 3, iclass 36, count 2 2006.201.13:45:20.34#ibcon#read 3, iclass 36, count 2 2006.201.13:45:20.34#ibcon#about to read 4, iclass 36, count 2 2006.201.13:45:20.34#ibcon#read 4, iclass 36, count 2 2006.201.13:45:20.34#ibcon#about to read 5, iclass 36, count 2 2006.201.13:45:20.34#ibcon#read 5, iclass 36, count 2 2006.201.13:45:20.34#ibcon#about to read 6, iclass 36, count 2 2006.201.13:45:20.34#ibcon#read 6, iclass 36, count 2 2006.201.13:45:20.34#ibcon#end of sib2, iclass 36, count 2 2006.201.13:45:20.34#ibcon#*mode == 0, iclass 36, count 2 2006.201.13:45:20.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.13:45:20.34#ibcon#[27=AT03-04\r\n] 2006.201.13:45:20.34#ibcon#*before write, iclass 36, count 2 2006.201.13:45:20.34#ibcon#enter sib2, iclass 36, count 2 2006.201.13:45:20.34#ibcon#flushed, iclass 36, count 2 2006.201.13:45:20.34#ibcon#about to write, iclass 36, count 2 2006.201.13:45:20.34#ibcon#wrote, iclass 36, count 2 2006.201.13:45:20.34#ibcon#about to read 3, iclass 36, count 2 2006.201.13:45:20.37#ibcon#read 3, iclass 36, count 2 2006.201.13:45:20.37#ibcon#about to read 4, iclass 36, count 2 2006.201.13:45:20.37#ibcon#read 4, iclass 36, count 2 2006.201.13:45:20.37#ibcon#about to read 5, iclass 36, count 2 2006.201.13:45:20.37#ibcon#read 5, iclass 36, count 2 2006.201.13:45:20.37#ibcon#about to read 6, iclass 36, count 2 2006.201.13:45:20.37#ibcon#read 6, iclass 36, count 2 2006.201.13:45:20.37#ibcon#end of sib2, iclass 36, count 2 2006.201.13:45:20.37#ibcon#*after write, iclass 36, count 2 2006.201.13:45:20.37#ibcon#*before return 0, iclass 36, count 2 2006.201.13:45:20.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:20.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.13:45:20.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.13:45:20.37#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:20.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:20.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:20.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:20.49#ibcon#enter wrdev, iclass 36, count 0 2006.201.13:45:20.49#ibcon#first serial, iclass 36, count 0 2006.201.13:45:20.49#ibcon#enter sib2, iclass 36, count 0 2006.201.13:45:20.49#ibcon#flushed, iclass 36, count 0 2006.201.13:45:20.49#ibcon#about to write, iclass 36, count 0 2006.201.13:45:20.49#ibcon#wrote, iclass 36, count 0 2006.201.13:45:20.49#ibcon#about to read 3, iclass 36, count 0 2006.201.13:45:20.51#ibcon#read 3, iclass 36, count 0 2006.201.13:45:20.51#ibcon#about to read 4, iclass 36, count 0 2006.201.13:45:20.51#ibcon#read 4, iclass 36, count 0 2006.201.13:45:20.51#ibcon#about to read 5, iclass 36, count 0 2006.201.13:45:20.51#ibcon#read 5, iclass 36, count 0 2006.201.13:45:20.51#ibcon#about to read 6, iclass 36, count 0 2006.201.13:45:20.51#ibcon#read 6, iclass 36, count 0 2006.201.13:45:20.51#ibcon#end of sib2, iclass 36, count 0 2006.201.13:45:20.51#ibcon#*mode == 0, iclass 36, count 0 2006.201.13:45:20.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.13:45:20.51#ibcon#[27=USB\r\n] 2006.201.13:45:20.51#ibcon#*before write, iclass 36, count 0 2006.201.13:45:20.51#ibcon#enter sib2, iclass 36, count 0 2006.201.13:45:20.51#ibcon#flushed, iclass 36, count 0 2006.201.13:45:20.51#ibcon#about to write, iclass 36, count 0 2006.201.13:45:20.51#ibcon#wrote, iclass 36, count 0 2006.201.13:45:20.51#ibcon#about to read 3, iclass 36, count 0 2006.201.13:45:20.54#ibcon#read 3, iclass 36, count 0 2006.201.13:45:20.54#ibcon#about to read 4, iclass 36, count 0 2006.201.13:45:20.54#ibcon#read 4, iclass 36, count 0 2006.201.13:45:20.54#ibcon#about to read 5, iclass 36, count 0 2006.201.13:45:20.54#ibcon#read 5, iclass 36, count 0 2006.201.13:45:20.54#ibcon#about to read 6, iclass 36, count 0 2006.201.13:45:20.54#ibcon#read 6, iclass 36, count 0 2006.201.13:45:20.54#ibcon#end of sib2, iclass 36, count 0 2006.201.13:45:20.54#ibcon#*after write, iclass 36, count 0 2006.201.13:45:20.54#ibcon#*before return 0, iclass 36, count 0 2006.201.13:45:20.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:20.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.13:45:20.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.13:45:20.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.13:45:20.54$vck44/vblo=4,679.99 2006.201.13:45:20.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.13:45:20.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.13:45:20.54#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:20.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:20.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:20.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:20.54#ibcon#enter wrdev, iclass 38, count 0 2006.201.13:45:20.54#ibcon#first serial, iclass 38, count 0 2006.201.13:45:20.54#ibcon#enter sib2, iclass 38, count 0 2006.201.13:45:20.54#ibcon#flushed, iclass 38, count 0 2006.201.13:45:20.54#ibcon#about to write, iclass 38, count 0 2006.201.13:45:20.54#ibcon#wrote, iclass 38, count 0 2006.201.13:45:20.54#ibcon#about to read 3, iclass 38, count 0 2006.201.13:45:20.56#ibcon#read 3, iclass 38, count 0 2006.201.13:45:20.56#ibcon#about to read 4, iclass 38, count 0 2006.201.13:45:20.56#ibcon#read 4, iclass 38, count 0 2006.201.13:45:20.56#ibcon#about to read 5, iclass 38, count 0 2006.201.13:45:20.56#ibcon#read 5, iclass 38, count 0 2006.201.13:45:20.56#ibcon#about to read 6, iclass 38, count 0 2006.201.13:45:20.56#ibcon#read 6, iclass 38, count 0 2006.201.13:45:20.56#ibcon#end of sib2, iclass 38, count 0 2006.201.13:45:20.56#ibcon#*mode == 0, iclass 38, count 0 2006.201.13:45:20.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.13:45:20.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:45:20.56#ibcon#*before write, iclass 38, count 0 2006.201.13:45:20.56#ibcon#enter sib2, iclass 38, count 0 2006.201.13:45:20.56#ibcon#flushed, iclass 38, count 0 2006.201.13:45:20.56#ibcon#about to write, iclass 38, count 0 2006.201.13:45:20.56#ibcon#wrote, iclass 38, count 0 2006.201.13:45:20.56#ibcon#about to read 3, iclass 38, count 0 2006.201.13:45:20.61#ibcon#read 3, iclass 38, count 0 2006.201.13:45:20.61#ibcon#about to read 4, iclass 38, count 0 2006.201.13:45:20.61#ibcon#read 4, iclass 38, count 0 2006.201.13:45:20.61#ibcon#about to read 5, iclass 38, count 0 2006.201.13:45:20.61#ibcon#read 5, iclass 38, count 0 2006.201.13:45:20.61#ibcon#about to read 6, iclass 38, count 0 2006.201.13:45:20.61#ibcon#read 6, iclass 38, count 0 2006.201.13:45:20.61#ibcon#end of sib2, iclass 38, count 0 2006.201.13:45:20.61#ibcon#*after write, iclass 38, count 0 2006.201.13:45:20.61#ibcon#*before return 0, iclass 38, count 0 2006.201.13:45:20.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:20.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.13:45:20.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.13:45:20.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.13:45:20.61$vck44/vb=4,5 2006.201.13:45:20.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.13:45:20.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.13:45:20.61#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:20.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:20.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:20.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:20.66#ibcon#enter wrdev, iclass 40, count 2 2006.201.13:45:20.66#ibcon#first serial, iclass 40, count 2 2006.201.13:45:20.66#ibcon#enter sib2, iclass 40, count 2 2006.201.13:45:20.66#ibcon#flushed, iclass 40, count 2 2006.201.13:45:20.66#ibcon#about to write, iclass 40, count 2 2006.201.13:45:20.66#ibcon#wrote, iclass 40, count 2 2006.201.13:45:20.66#ibcon#about to read 3, iclass 40, count 2 2006.201.13:45:20.68#ibcon#read 3, iclass 40, count 2 2006.201.13:45:20.68#ibcon#about to read 4, iclass 40, count 2 2006.201.13:45:20.68#ibcon#read 4, iclass 40, count 2 2006.201.13:45:20.68#ibcon#about to read 5, iclass 40, count 2 2006.201.13:45:20.68#ibcon#read 5, iclass 40, count 2 2006.201.13:45:20.68#ibcon#about to read 6, iclass 40, count 2 2006.201.13:45:20.68#ibcon#read 6, iclass 40, count 2 2006.201.13:45:20.68#ibcon#end of sib2, iclass 40, count 2 2006.201.13:45:20.68#ibcon#*mode == 0, iclass 40, count 2 2006.201.13:45:20.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.13:45:20.68#ibcon#[27=AT04-05\r\n] 2006.201.13:45:20.68#ibcon#*before write, iclass 40, count 2 2006.201.13:45:20.68#ibcon#enter sib2, iclass 40, count 2 2006.201.13:45:20.68#ibcon#flushed, iclass 40, count 2 2006.201.13:45:20.68#ibcon#about to write, iclass 40, count 2 2006.201.13:45:20.68#ibcon#wrote, iclass 40, count 2 2006.201.13:45:20.68#ibcon#about to read 3, iclass 40, count 2 2006.201.13:45:20.71#ibcon#read 3, iclass 40, count 2 2006.201.13:45:20.71#ibcon#about to read 4, iclass 40, count 2 2006.201.13:45:20.71#ibcon#read 4, iclass 40, count 2 2006.201.13:45:20.71#ibcon#about to read 5, iclass 40, count 2 2006.201.13:45:20.71#ibcon#read 5, iclass 40, count 2 2006.201.13:45:20.71#ibcon#about to read 6, iclass 40, count 2 2006.201.13:45:20.71#ibcon#read 6, iclass 40, count 2 2006.201.13:45:20.71#ibcon#end of sib2, iclass 40, count 2 2006.201.13:45:20.71#ibcon#*after write, iclass 40, count 2 2006.201.13:45:20.71#ibcon#*before return 0, iclass 40, count 2 2006.201.13:45:20.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:20.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.13:45:20.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.13:45:20.71#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:20.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:20.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:20.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:20.83#ibcon#enter wrdev, iclass 40, count 0 2006.201.13:45:20.83#ibcon#first serial, iclass 40, count 0 2006.201.13:45:20.83#ibcon#enter sib2, iclass 40, count 0 2006.201.13:45:20.83#ibcon#flushed, iclass 40, count 0 2006.201.13:45:20.83#ibcon#about to write, iclass 40, count 0 2006.201.13:45:20.83#ibcon#wrote, iclass 40, count 0 2006.201.13:45:20.83#ibcon#about to read 3, iclass 40, count 0 2006.201.13:45:20.85#ibcon#read 3, iclass 40, count 0 2006.201.13:45:20.85#ibcon#about to read 4, iclass 40, count 0 2006.201.13:45:20.85#ibcon#read 4, iclass 40, count 0 2006.201.13:45:20.85#ibcon#about to read 5, iclass 40, count 0 2006.201.13:45:20.85#ibcon#read 5, iclass 40, count 0 2006.201.13:45:20.85#ibcon#about to read 6, iclass 40, count 0 2006.201.13:45:20.85#ibcon#read 6, iclass 40, count 0 2006.201.13:45:20.85#ibcon#end of sib2, iclass 40, count 0 2006.201.13:45:20.85#ibcon#*mode == 0, iclass 40, count 0 2006.201.13:45:20.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.13:45:20.85#ibcon#[27=USB\r\n] 2006.201.13:45:20.85#ibcon#*before write, iclass 40, count 0 2006.201.13:45:20.85#ibcon#enter sib2, iclass 40, count 0 2006.201.13:45:20.85#ibcon#flushed, iclass 40, count 0 2006.201.13:45:20.85#ibcon#about to write, iclass 40, count 0 2006.201.13:45:20.85#ibcon#wrote, iclass 40, count 0 2006.201.13:45:20.85#ibcon#about to read 3, iclass 40, count 0 2006.201.13:45:20.88#ibcon#read 3, iclass 40, count 0 2006.201.13:45:20.88#ibcon#about to read 4, iclass 40, count 0 2006.201.13:45:20.88#ibcon#read 4, iclass 40, count 0 2006.201.13:45:20.88#ibcon#about to read 5, iclass 40, count 0 2006.201.13:45:20.88#ibcon#read 5, iclass 40, count 0 2006.201.13:45:20.88#ibcon#about to read 6, iclass 40, count 0 2006.201.13:45:20.88#ibcon#read 6, iclass 40, count 0 2006.201.13:45:20.88#ibcon#end of sib2, iclass 40, count 0 2006.201.13:45:20.88#ibcon#*after write, iclass 40, count 0 2006.201.13:45:20.88#ibcon#*before return 0, iclass 40, count 0 2006.201.13:45:20.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:20.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.13:45:20.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.13:45:20.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.13:45:20.88$vck44/vblo=5,709.99 2006.201.13:45:20.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.13:45:20.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.13:45:20.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:20.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:20.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:20.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:20.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.13:45:20.88#ibcon#first serial, iclass 4, count 0 2006.201.13:45:20.88#ibcon#enter sib2, iclass 4, count 0 2006.201.13:45:20.88#ibcon#flushed, iclass 4, count 0 2006.201.13:45:20.88#ibcon#about to write, iclass 4, count 0 2006.201.13:45:20.88#ibcon#wrote, iclass 4, count 0 2006.201.13:45:20.88#ibcon#about to read 3, iclass 4, count 0 2006.201.13:45:20.90#ibcon#read 3, iclass 4, count 0 2006.201.13:45:20.90#ibcon#about to read 4, iclass 4, count 0 2006.201.13:45:20.90#ibcon#read 4, iclass 4, count 0 2006.201.13:45:20.90#ibcon#about to read 5, iclass 4, count 0 2006.201.13:45:20.90#ibcon#read 5, iclass 4, count 0 2006.201.13:45:20.90#ibcon#about to read 6, iclass 4, count 0 2006.201.13:45:20.90#ibcon#read 6, iclass 4, count 0 2006.201.13:45:20.90#ibcon#end of sib2, iclass 4, count 0 2006.201.13:45:20.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.13:45:20.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.13:45:20.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:45:20.90#ibcon#*before write, iclass 4, count 0 2006.201.13:45:20.90#ibcon#enter sib2, iclass 4, count 0 2006.201.13:45:20.90#ibcon#flushed, iclass 4, count 0 2006.201.13:45:20.90#ibcon#about to write, iclass 4, count 0 2006.201.13:45:20.90#ibcon#wrote, iclass 4, count 0 2006.201.13:45:20.90#ibcon#about to read 3, iclass 4, count 0 2006.201.13:45:20.94#ibcon#read 3, iclass 4, count 0 2006.201.13:45:20.94#ibcon#about to read 4, iclass 4, count 0 2006.201.13:45:20.94#ibcon#read 4, iclass 4, count 0 2006.201.13:45:20.94#ibcon#about to read 5, iclass 4, count 0 2006.201.13:45:20.94#ibcon#read 5, iclass 4, count 0 2006.201.13:45:20.94#ibcon#about to read 6, iclass 4, count 0 2006.201.13:45:20.94#ibcon#read 6, iclass 4, count 0 2006.201.13:45:20.94#ibcon#end of sib2, iclass 4, count 0 2006.201.13:45:20.94#ibcon#*after write, iclass 4, count 0 2006.201.13:45:20.94#ibcon#*before return 0, iclass 4, count 0 2006.201.13:45:20.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:20.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.13:45:20.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.13:45:20.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.13:45:20.94$vck44/vb=5,4 2006.201.13:45:20.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.13:45:20.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.13:45:20.94#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:20.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:21.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:21.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:21.00#ibcon#enter wrdev, iclass 6, count 2 2006.201.13:45:21.00#ibcon#first serial, iclass 6, count 2 2006.201.13:45:21.00#ibcon#enter sib2, iclass 6, count 2 2006.201.13:45:21.00#ibcon#flushed, iclass 6, count 2 2006.201.13:45:21.00#ibcon#about to write, iclass 6, count 2 2006.201.13:45:21.00#ibcon#wrote, iclass 6, count 2 2006.201.13:45:21.00#ibcon#about to read 3, iclass 6, count 2 2006.201.13:45:21.02#ibcon#read 3, iclass 6, count 2 2006.201.13:45:21.02#ibcon#about to read 4, iclass 6, count 2 2006.201.13:45:21.02#ibcon#read 4, iclass 6, count 2 2006.201.13:45:21.02#ibcon#about to read 5, iclass 6, count 2 2006.201.13:45:21.02#ibcon#read 5, iclass 6, count 2 2006.201.13:45:21.02#ibcon#about to read 6, iclass 6, count 2 2006.201.13:45:21.02#ibcon#read 6, iclass 6, count 2 2006.201.13:45:21.02#ibcon#end of sib2, iclass 6, count 2 2006.201.13:45:21.02#ibcon#*mode == 0, iclass 6, count 2 2006.201.13:45:21.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.13:45:21.02#ibcon#[27=AT05-04\r\n] 2006.201.13:45:21.02#ibcon#*before write, iclass 6, count 2 2006.201.13:45:21.02#ibcon#enter sib2, iclass 6, count 2 2006.201.13:45:21.02#ibcon#flushed, iclass 6, count 2 2006.201.13:45:21.02#ibcon#about to write, iclass 6, count 2 2006.201.13:45:21.02#ibcon#wrote, iclass 6, count 2 2006.201.13:45:21.02#ibcon#about to read 3, iclass 6, count 2 2006.201.13:45:21.05#ibcon#read 3, iclass 6, count 2 2006.201.13:45:21.05#ibcon#about to read 4, iclass 6, count 2 2006.201.13:45:21.05#ibcon#read 4, iclass 6, count 2 2006.201.13:45:21.05#ibcon#about to read 5, iclass 6, count 2 2006.201.13:45:21.05#ibcon#read 5, iclass 6, count 2 2006.201.13:45:21.05#ibcon#about to read 6, iclass 6, count 2 2006.201.13:45:21.05#ibcon#read 6, iclass 6, count 2 2006.201.13:45:21.05#ibcon#end of sib2, iclass 6, count 2 2006.201.13:45:21.05#ibcon#*after write, iclass 6, count 2 2006.201.13:45:21.05#ibcon#*before return 0, iclass 6, count 2 2006.201.13:45:21.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:21.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.13:45:21.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.13:45:21.05#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:21.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:21.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:21.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:21.17#ibcon#enter wrdev, iclass 6, count 0 2006.201.13:45:21.17#ibcon#first serial, iclass 6, count 0 2006.201.13:45:21.17#ibcon#enter sib2, iclass 6, count 0 2006.201.13:45:21.17#ibcon#flushed, iclass 6, count 0 2006.201.13:45:21.17#ibcon#about to write, iclass 6, count 0 2006.201.13:45:21.17#ibcon#wrote, iclass 6, count 0 2006.201.13:45:21.17#ibcon#about to read 3, iclass 6, count 0 2006.201.13:45:21.19#ibcon#read 3, iclass 6, count 0 2006.201.13:45:21.19#ibcon#about to read 4, iclass 6, count 0 2006.201.13:45:21.19#ibcon#read 4, iclass 6, count 0 2006.201.13:45:21.19#ibcon#about to read 5, iclass 6, count 0 2006.201.13:45:21.19#ibcon#read 5, iclass 6, count 0 2006.201.13:45:21.19#ibcon#about to read 6, iclass 6, count 0 2006.201.13:45:21.19#ibcon#read 6, iclass 6, count 0 2006.201.13:45:21.19#ibcon#end of sib2, iclass 6, count 0 2006.201.13:45:21.19#ibcon#*mode == 0, iclass 6, count 0 2006.201.13:45:21.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.13:45:21.19#ibcon#[27=USB\r\n] 2006.201.13:45:21.19#ibcon#*before write, iclass 6, count 0 2006.201.13:45:21.19#ibcon#enter sib2, iclass 6, count 0 2006.201.13:45:21.19#ibcon#flushed, iclass 6, count 0 2006.201.13:45:21.19#ibcon#about to write, iclass 6, count 0 2006.201.13:45:21.19#ibcon#wrote, iclass 6, count 0 2006.201.13:45:21.19#ibcon#about to read 3, iclass 6, count 0 2006.201.13:45:21.22#ibcon#read 3, iclass 6, count 0 2006.201.13:45:21.22#ibcon#about to read 4, iclass 6, count 0 2006.201.13:45:21.22#ibcon#read 4, iclass 6, count 0 2006.201.13:45:21.22#ibcon#about to read 5, iclass 6, count 0 2006.201.13:45:21.22#ibcon#read 5, iclass 6, count 0 2006.201.13:45:21.22#ibcon#about to read 6, iclass 6, count 0 2006.201.13:45:21.22#ibcon#read 6, iclass 6, count 0 2006.201.13:45:21.22#ibcon#end of sib2, iclass 6, count 0 2006.201.13:45:21.22#ibcon#*after write, iclass 6, count 0 2006.201.13:45:21.22#ibcon#*before return 0, iclass 6, count 0 2006.201.13:45:21.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:21.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.13:45:21.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.13:45:21.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.13:45:21.22$vck44/vblo=6,719.99 2006.201.13:45:21.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.13:45:21.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.13:45:21.22#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:21.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:21.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:21.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:21.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.13:45:21.22#ibcon#first serial, iclass 10, count 0 2006.201.13:45:21.22#ibcon#enter sib2, iclass 10, count 0 2006.201.13:45:21.22#ibcon#flushed, iclass 10, count 0 2006.201.13:45:21.22#ibcon#about to write, iclass 10, count 0 2006.201.13:45:21.22#ibcon#wrote, iclass 10, count 0 2006.201.13:45:21.22#ibcon#about to read 3, iclass 10, count 0 2006.201.13:45:21.24#ibcon#read 3, iclass 10, count 0 2006.201.13:45:21.24#ibcon#about to read 4, iclass 10, count 0 2006.201.13:45:21.24#ibcon#read 4, iclass 10, count 0 2006.201.13:45:21.24#ibcon#about to read 5, iclass 10, count 0 2006.201.13:45:21.24#ibcon#read 5, iclass 10, count 0 2006.201.13:45:21.24#ibcon#about to read 6, iclass 10, count 0 2006.201.13:45:21.24#ibcon#read 6, iclass 10, count 0 2006.201.13:45:21.24#ibcon#end of sib2, iclass 10, count 0 2006.201.13:45:21.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.13:45:21.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.13:45:21.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:45:21.24#ibcon#*before write, iclass 10, count 0 2006.201.13:45:21.24#ibcon#enter sib2, iclass 10, count 0 2006.201.13:45:21.24#ibcon#flushed, iclass 10, count 0 2006.201.13:45:21.24#ibcon#about to write, iclass 10, count 0 2006.201.13:45:21.24#ibcon#wrote, iclass 10, count 0 2006.201.13:45:21.24#ibcon#about to read 3, iclass 10, count 0 2006.201.13:45:21.29#ibcon#read 3, iclass 10, count 0 2006.201.13:45:21.29#ibcon#about to read 4, iclass 10, count 0 2006.201.13:45:21.29#ibcon#read 4, iclass 10, count 0 2006.201.13:45:21.29#ibcon#about to read 5, iclass 10, count 0 2006.201.13:45:21.29#ibcon#read 5, iclass 10, count 0 2006.201.13:45:21.29#ibcon#about to read 6, iclass 10, count 0 2006.201.13:45:21.29#ibcon#read 6, iclass 10, count 0 2006.201.13:45:21.29#ibcon#end of sib2, iclass 10, count 0 2006.201.13:45:21.29#ibcon#*after write, iclass 10, count 0 2006.201.13:45:21.29#ibcon#*before return 0, iclass 10, count 0 2006.201.13:45:21.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:21.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.13:45:21.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.13:45:21.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.13:45:21.29$vck44/vb=6,4 2006.201.13:45:21.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.13:45:21.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.13:45:21.29#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:21.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:21.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:21.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:21.34#ibcon#enter wrdev, iclass 12, count 2 2006.201.13:45:21.34#ibcon#first serial, iclass 12, count 2 2006.201.13:45:21.34#ibcon#enter sib2, iclass 12, count 2 2006.201.13:45:21.34#ibcon#flushed, iclass 12, count 2 2006.201.13:45:21.34#ibcon#about to write, iclass 12, count 2 2006.201.13:45:21.34#ibcon#wrote, iclass 12, count 2 2006.201.13:45:21.34#ibcon#about to read 3, iclass 12, count 2 2006.201.13:45:21.36#ibcon#read 3, iclass 12, count 2 2006.201.13:45:21.36#ibcon#about to read 4, iclass 12, count 2 2006.201.13:45:21.36#ibcon#read 4, iclass 12, count 2 2006.201.13:45:21.36#ibcon#about to read 5, iclass 12, count 2 2006.201.13:45:21.36#ibcon#read 5, iclass 12, count 2 2006.201.13:45:21.36#ibcon#about to read 6, iclass 12, count 2 2006.201.13:45:21.36#ibcon#read 6, iclass 12, count 2 2006.201.13:45:21.36#ibcon#end of sib2, iclass 12, count 2 2006.201.13:45:21.36#ibcon#*mode == 0, iclass 12, count 2 2006.201.13:45:21.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.13:45:21.36#ibcon#[27=AT06-04\r\n] 2006.201.13:45:21.36#ibcon#*before write, iclass 12, count 2 2006.201.13:45:21.36#ibcon#enter sib2, iclass 12, count 2 2006.201.13:45:21.36#ibcon#flushed, iclass 12, count 2 2006.201.13:45:21.36#ibcon#about to write, iclass 12, count 2 2006.201.13:45:21.36#ibcon#wrote, iclass 12, count 2 2006.201.13:45:21.36#ibcon#about to read 3, iclass 12, count 2 2006.201.13:45:21.39#ibcon#read 3, iclass 12, count 2 2006.201.13:45:21.39#ibcon#about to read 4, iclass 12, count 2 2006.201.13:45:21.39#ibcon#read 4, iclass 12, count 2 2006.201.13:45:21.39#ibcon#about to read 5, iclass 12, count 2 2006.201.13:45:21.39#ibcon#read 5, iclass 12, count 2 2006.201.13:45:21.39#ibcon#about to read 6, iclass 12, count 2 2006.201.13:45:21.39#ibcon#read 6, iclass 12, count 2 2006.201.13:45:21.39#ibcon#end of sib2, iclass 12, count 2 2006.201.13:45:21.39#ibcon#*after write, iclass 12, count 2 2006.201.13:45:21.39#ibcon#*before return 0, iclass 12, count 2 2006.201.13:45:21.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:21.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.13:45:21.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.13:45:21.39#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:21.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:21.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:21.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:21.51#ibcon#enter wrdev, iclass 12, count 0 2006.201.13:45:21.51#ibcon#first serial, iclass 12, count 0 2006.201.13:45:21.51#ibcon#enter sib2, iclass 12, count 0 2006.201.13:45:21.51#ibcon#flushed, iclass 12, count 0 2006.201.13:45:21.51#ibcon#about to write, iclass 12, count 0 2006.201.13:45:21.51#ibcon#wrote, iclass 12, count 0 2006.201.13:45:21.51#ibcon#about to read 3, iclass 12, count 0 2006.201.13:45:21.53#ibcon#read 3, iclass 12, count 0 2006.201.13:45:21.53#ibcon#about to read 4, iclass 12, count 0 2006.201.13:45:21.53#ibcon#read 4, iclass 12, count 0 2006.201.13:45:21.53#ibcon#about to read 5, iclass 12, count 0 2006.201.13:45:21.53#ibcon#read 5, iclass 12, count 0 2006.201.13:45:21.53#ibcon#about to read 6, iclass 12, count 0 2006.201.13:45:21.53#ibcon#read 6, iclass 12, count 0 2006.201.13:45:21.53#ibcon#end of sib2, iclass 12, count 0 2006.201.13:45:21.53#ibcon#*mode == 0, iclass 12, count 0 2006.201.13:45:21.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.13:45:21.53#ibcon#[27=USB\r\n] 2006.201.13:45:21.53#ibcon#*before write, iclass 12, count 0 2006.201.13:45:21.53#ibcon#enter sib2, iclass 12, count 0 2006.201.13:45:21.53#ibcon#flushed, iclass 12, count 0 2006.201.13:45:21.53#ibcon#about to write, iclass 12, count 0 2006.201.13:45:21.53#ibcon#wrote, iclass 12, count 0 2006.201.13:45:21.53#ibcon#about to read 3, iclass 12, count 0 2006.201.13:45:21.56#ibcon#read 3, iclass 12, count 0 2006.201.13:45:21.56#ibcon#about to read 4, iclass 12, count 0 2006.201.13:45:21.56#ibcon#read 4, iclass 12, count 0 2006.201.13:45:21.56#ibcon#about to read 5, iclass 12, count 0 2006.201.13:45:21.56#ibcon#read 5, iclass 12, count 0 2006.201.13:45:21.56#ibcon#about to read 6, iclass 12, count 0 2006.201.13:45:21.56#ibcon#read 6, iclass 12, count 0 2006.201.13:45:21.56#ibcon#end of sib2, iclass 12, count 0 2006.201.13:45:21.56#ibcon#*after write, iclass 12, count 0 2006.201.13:45:21.56#ibcon#*before return 0, iclass 12, count 0 2006.201.13:45:21.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:21.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.13:45:21.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.13:45:21.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.13:45:21.56$vck44/vblo=7,734.99 2006.201.13:45:21.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.13:45:21.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.13:45:21.56#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:21.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:21.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:21.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:21.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.13:45:21.56#ibcon#first serial, iclass 14, count 0 2006.201.13:45:21.56#ibcon#enter sib2, iclass 14, count 0 2006.201.13:45:21.56#ibcon#flushed, iclass 14, count 0 2006.201.13:45:21.56#ibcon#about to write, iclass 14, count 0 2006.201.13:45:21.56#ibcon#wrote, iclass 14, count 0 2006.201.13:45:21.56#ibcon#about to read 3, iclass 14, count 0 2006.201.13:45:21.58#ibcon#read 3, iclass 14, count 0 2006.201.13:45:21.58#ibcon#about to read 4, iclass 14, count 0 2006.201.13:45:21.58#ibcon#read 4, iclass 14, count 0 2006.201.13:45:21.58#ibcon#about to read 5, iclass 14, count 0 2006.201.13:45:21.58#ibcon#read 5, iclass 14, count 0 2006.201.13:45:21.58#ibcon#about to read 6, iclass 14, count 0 2006.201.13:45:21.58#ibcon#read 6, iclass 14, count 0 2006.201.13:45:21.58#ibcon#end of sib2, iclass 14, count 0 2006.201.13:45:21.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.13:45:21.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.13:45:21.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:45:21.58#ibcon#*before write, iclass 14, count 0 2006.201.13:45:21.58#ibcon#enter sib2, iclass 14, count 0 2006.201.13:45:21.58#ibcon#flushed, iclass 14, count 0 2006.201.13:45:21.58#ibcon#about to write, iclass 14, count 0 2006.201.13:45:21.58#ibcon#wrote, iclass 14, count 0 2006.201.13:45:21.58#ibcon#about to read 3, iclass 14, count 0 2006.201.13:45:21.62#ibcon#read 3, iclass 14, count 0 2006.201.13:45:21.62#ibcon#about to read 4, iclass 14, count 0 2006.201.13:45:21.62#ibcon#read 4, iclass 14, count 0 2006.201.13:45:21.62#ibcon#about to read 5, iclass 14, count 0 2006.201.13:45:21.62#ibcon#read 5, iclass 14, count 0 2006.201.13:45:21.62#ibcon#about to read 6, iclass 14, count 0 2006.201.13:45:21.62#ibcon#read 6, iclass 14, count 0 2006.201.13:45:21.62#ibcon#end of sib2, iclass 14, count 0 2006.201.13:45:21.62#ibcon#*after write, iclass 14, count 0 2006.201.13:45:21.62#ibcon#*before return 0, iclass 14, count 0 2006.201.13:45:21.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:21.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.13:45:21.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.13:45:21.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.13:45:21.62$vck44/vb=7,4 2006.201.13:45:21.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.13:45:21.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.13:45:21.62#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:21.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:21.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:21.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:21.68#ibcon#enter wrdev, iclass 16, count 2 2006.201.13:45:21.68#ibcon#first serial, iclass 16, count 2 2006.201.13:45:21.68#ibcon#enter sib2, iclass 16, count 2 2006.201.13:45:21.68#ibcon#flushed, iclass 16, count 2 2006.201.13:45:21.68#ibcon#about to write, iclass 16, count 2 2006.201.13:45:21.68#ibcon#wrote, iclass 16, count 2 2006.201.13:45:21.68#ibcon#about to read 3, iclass 16, count 2 2006.201.13:45:21.70#ibcon#read 3, iclass 16, count 2 2006.201.13:45:21.70#ibcon#about to read 4, iclass 16, count 2 2006.201.13:45:21.70#ibcon#read 4, iclass 16, count 2 2006.201.13:45:21.70#ibcon#about to read 5, iclass 16, count 2 2006.201.13:45:21.70#ibcon#read 5, iclass 16, count 2 2006.201.13:45:21.70#ibcon#about to read 6, iclass 16, count 2 2006.201.13:45:21.70#ibcon#read 6, iclass 16, count 2 2006.201.13:45:21.70#ibcon#end of sib2, iclass 16, count 2 2006.201.13:45:21.70#ibcon#*mode == 0, iclass 16, count 2 2006.201.13:45:21.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.13:45:21.70#ibcon#[27=AT07-04\r\n] 2006.201.13:45:21.70#ibcon#*before write, iclass 16, count 2 2006.201.13:45:21.70#ibcon#enter sib2, iclass 16, count 2 2006.201.13:45:21.70#ibcon#flushed, iclass 16, count 2 2006.201.13:45:21.70#ibcon#about to write, iclass 16, count 2 2006.201.13:45:21.70#ibcon#wrote, iclass 16, count 2 2006.201.13:45:21.70#ibcon#about to read 3, iclass 16, count 2 2006.201.13:45:21.73#ibcon#read 3, iclass 16, count 2 2006.201.13:45:21.73#ibcon#about to read 4, iclass 16, count 2 2006.201.13:45:21.73#ibcon#read 4, iclass 16, count 2 2006.201.13:45:21.73#ibcon#about to read 5, iclass 16, count 2 2006.201.13:45:21.73#ibcon#read 5, iclass 16, count 2 2006.201.13:45:21.73#ibcon#about to read 6, iclass 16, count 2 2006.201.13:45:21.73#ibcon#read 6, iclass 16, count 2 2006.201.13:45:21.73#ibcon#end of sib2, iclass 16, count 2 2006.201.13:45:21.73#ibcon#*after write, iclass 16, count 2 2006.201.13:45:21.73#ibcon#*before return 0, iclass 16, count 2 2006.201.13:45:21.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:21.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.13:45:21.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.13:45:21.73#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:21.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:21.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:21.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:21.85#ibcon#enter wrdev, iclass 16, count 0 2006.201.13:45:21.85#ibcon#first serial, iclass 16, count 0 2006.201.13:45:21.85#ibcon#enter sib2, iclass 16, count 0 2006.201.13:45:21.85#ibcon#flushed, iclass 16, count 0 2006.201.13:45:21.85#ibcon#about to write, iclass 16, count 0 2006.201.13:45:21.85#ibcon#wrote, iclass 16, count 0 2006.201.13:45:21.85#ibcon#about to read 3, iclass 16, count 0 2006.201.13:45:21.87#ibcon#read 3, iclass 16, count 0 2006.201.13:45:21.87#ibcon#about to read 4, iclass 16, count 0 2006.201.13:45:21.87#ibcon#read 4, iclass 16, count 0 2006.201.13:45:21.87#ibcon#about to read 5, iclass 16, count 0 2006.201.13:45:21.87#ibcon#read 5, iclass 16, count 0 2006.201.13:45:21.87#ibcon#about to read 6, iclass 16, count 0 2006.201.13:45:21.87#ibcon#read 6, iclass 16, count 0 2006.201.13:45:21.87#ibcon#end of sib2, iclass 16, count 0 2006.201.13:45:21.87#ibcon#*mode == 0, iclass 16, count 0 2006.201.13:45:21.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.13:45:21.87#ibcon#[27=USB\r\n] 2006.201.13:45:21.87#ibcon#*before write, iclass 16, count 0 2006.201.13:45:21.87#ibcon#enter sib2, iclass 16, count 0 2006.201.13:45:21.87#ibcon#flushed, iclass 16, count 0 2006.201.13:45:21.87#ibcon#about to write, iclass 16, count 0 2006.201.13:45:21.87#ibcon#wrote, iclass 16, count 0 2006.201.13:45:21.87#ibcon#about to read 3, iclass 16, count 0 2006.201.13:45:21.90#ibcon#read 3, iclass 16, count 0 2006.201.13:45:21.90#ibcon#about to read 4, iclass 16, count 0 2006.201.13:45:21.90#ibcon#read 4, iclass 16, count 0 2006.201.13:45:21.90#ibcon#about to read 5, iclass 16, count 0 2006.201.13:45:21.90#ibcon#read 5, iclass 16, count 0 2006.201.13:45:21.90#ibcon#about to read 6, iclass 16, count 0 2006.201.13:45:21.90#ibcon#read 6, iclass 16, count 0 2006.201.13:45:21.90#ibcon#end of sib2, iclass 16, count 0 2006.201.13:45:21.90#ibcon#*after write, iclass 16, count 0 2006.201.13:45:21.90#ibcon#*before return 0, iclass 16, count 0 2006.201.13:45:21.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:21.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.13:45:21.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.13:45:21.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.13:45:21.90$vck44/vblo=8,744.99 2006.201.13:45:21.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.13:45:21.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.13:45:21.90#ibcon#ireg 17 cls_cnt 0 2006.201.13:45:21.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:21.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:21.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:21.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.13:45:21.90#ibcon#first serial, iclass 18, count 0 2006.201.13:45:21.90#ibcon#enter sib2, iclass 18, count 0 2006.201.13:45:21.90#ibcon#flushed, iclass 18, count 0 2006.201.13:45:21.90#ibcon#about to write, iclass 18, count 0 2006.201.13:45:21.90#ibcon#wrote, iclass 18, count 0 2006.201.13:45:21.90#ibcon#about to read 3, iclass 18, count 0 2006.201.13:45:21.92#ibcon#read 3, iclass 18, count 0 2006.201.13:45:21.92#ibcon#about to read 4, iclass 18, count 0 2006.201.13:45:21.92#ibcon#read 4, iclass 18, count 0 2006.201.13:45:21.92#ibcon#about to read 5, iclass 18, count 0 2006.201.13:45:21.92#ibcon#read 5, iclass 18, count 0 2006.201.13:45:21.92#ibcon#about to read 6, iclass 18, count 0 2006.201.13:45:21.92#ibcon#read 6, iclass 18, count 0 2006.201.13:45:21.92#ibcon#end of sib2, iclass 18, count 0 2006.201.13:45:21.92#ibcon#*mode == 0, iclass 18, count 0 2006.201.13:45:21.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.13:45:21.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:45:21.92#ibcon#*before write, iclass 18, count 0 2006.201.13:45:21.92#ibcon#enter sib2, iclass 18, count 0 2006.201.13:45:21.92#ibcon#flushed, iclass 18, count 0 2006.201.13:45:21.92#ibcon#about to write, iclass 18, count 0 2006.201.13:45:21.92#ibcon#wrote, iclass 18, count 0 2006.201.13:45:21.92#ibcon#about to read 3, iclass 18, count 0 2006.201.13:45:21.97#ibcon#read 3, iclass 18, count 0 2006.201.13:45:21.97#ibcon#about to read 4, iclass 18, count 0 2006.201.13:45:21.97#ibcon#read 4, iclass 18, count 0 2006.201.13:45:21.97#ibcon#about to read 5, iclass 18, count 0 2006.201.13:45:21.97#ibcon#read 5, iclass 18, count 0 2006.201.13:45:21.97#ibcon#about to read 6, iclass 18, count 0 2006.201.13:45:21.97#ibcon#read 6, iclass 18, count 0 2006.201.13:45:21.97#ibcon#end of sib2, iclass 18, count 0 2006.201.13:45:21.97#ibcon#*after write, iclass 18, count 0 2006.201.13:45:21.97#ibcon#*before return 0, iclass 18, count 0 2006.201.13:45:21.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:21.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:45:21.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.13:45:21.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.13:45:21.97$vck44/vb=8,4 2006.201.13:45:21.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.13:45:21.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.13:45:21.97#ibcon#ireg 11 cls_cnt 2 2006.201.13:45:21.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:22.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:22.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:22.02#ibcon#enter wrdev, iclass 20, count 2 2006.201.13:45:22.02#ibcon#first serial, iclass 20, count 2 2006.201.13:45:22.02#ibcon#enter sib2, iclass 20, count 2 2006.201.13:45:22.02#ibcon#flushed, iclass 20, count 2 2006.201.13:45:22.02#ibcon#about to write, iclass 20, count 2 2006.201.13:45:22.02#ibcon#wrote, iclass 20, count 2 2006.201.13:45:22.02#ibcon#about to read 3, iclass 20, count 2 2006.201.13:45:22.04#ibcon#read 3, iclass 20, count 2 2006.201.13:45:22.04#ibcon#about to read 4, iclass 20, count 2 2006.201.13:45:22.04#ibcon#read 4, iclass 20, count 2 2006.201.13:45:22.04#ibcon#about to read 5, iclass 20, count 2 2006.201.13:45:22.04#ibcon#read 5, iclass 20, count 2 2006.201.13:45:22.04#ibcon#about to read 6, iclass 20, count 2 2006.201.13:45:22.04#ibcon#read 6, iclass 20, count 2 2006.201.13:45:22.04#ibcon#end of sib2, iclass 20, count 2 2006.201.13:45:22.04#ibcon#*mode == 0, iclass 20, count 2 2006.201.13:45:22.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.13:45:22.04#ibcon#[27=AT08-04\r\n] 2006.201.13:45:22.04#ibcon#*before write, iclass 20, count 2 2006.201.13:45:22.04#ibcon#enter sib2, iclass 20, count 2 2006.201.13:45:22.04#ibcon#flushed, iclass 20, count 2 2006.201.13:45:22.04#ibcon#about to write, iclass 20, count 2 2006.201.13:45:22.04#ibcon#wrote, iclass 20, count 2 2006.201.13:45:22.04#ibcon#about to read 3, iclass 20, count 2 2006.201.13:45:22.07#ibcon#read 3, iclass 20, count 2 2006.201.13:45:22.07#ibcon#about to read 4, iclass 20, count 2 2006.201.13:45:22.07#ibcon#read 4, iclass 20, count 2 2006.201.13:45:22.07#ibcon#about to read 5, iclass 20, count 2 2006.201.13:45:22.07#ibcon#read 5, iclass 20, count 2 2006.201.13:45:22.07#ibcon#about to read 6, iclass 20, count 2 2006.201.13:45:22.07#ibcon#read 6, iclass 20, count 2 2006.201.13:45:22.07#ibcon#end of sib2, iclass 20, count 2 2006.201.13:45:22.07#ibcon#*after write, iclass 20, count 2 2006.201.13:45:22.07#ibcon#*before return 0, iclass 20, count 2 2006.201.13:45:22.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:22.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.13:45:22.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.13:45:22.07#ibcon#ireg 7 cls_cnt 0 2006.201.13:45:22.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:22.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:22.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:22.19#ibcon#enter wrdev, iclass 20, count 0 2006.201.13:45:22.19#ibcon#first serial, iclass 20, count 0 2006.201.13:45:22.19#ibcon#enter sib2, iclass 20, count 0 2006.201.13:45:22.19#ibcon#flushed, iclass 20, count 0 2006.201.13:45:22.19#ibcon#about to write, iclass 20, count 0 2006.201.13:45:22.19#ibcon#wrote, iclass 20, count 0 2006.201.13:45:22.19#ibcon#about to read 3, iclass 20, count 0 2006.201.13:45:22.21#ibcon#read 3, iclass 20, count 0 2006.201.13:45:22.21#ibcon#about to read 4, iclass 20, count 0 2006.201.13:45:22.21#ibcon#read 4, iclass 20, count 0 2006.201.13:45:22.21#ibcon#about to read 5, iclass 20, count 0 2006.201.13:45:22.21#ibcon#read 5, iclass 20, count 0 2006.201.13:45:22.21#ibcon#about to read 6, iclass 20, count 0 2006.201.13:45:22.21#ibcon#read 6, iclass 20, count 0 2006.201.13:45:22.21#ibcon#end of sib2, iclass 20, count 0 2006.201.13:45:22.21#ibcon#*mode == 0, iclass 20, count 0 2006.201.13:45:22.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.13:45:22.21#ibcon#[27=USB\r\n] 2006.201.13:45:22.21#ibcon#*before write, iclass 20, count 0 2006.201.13:45:22.21#ibcon#enter sib2, iclass 20, count 0 2006.201.13:45:22.21#ibcon#flushed, iclass 20, count 0 2006.201.13:45:22.21#ibcon#about to write, iclass 20, count 0 2006.201.13:45:22.21#ibcon#wrote, iclass 20, count 0 2006.201.13:45:22.21#ibcon#about to read 3, iclass 20, count 0 2006.201.13:45:22.24#ibcon#read 3, iclass 20, count 0 2006.201.13:45:22.24#ibcon#about to read 4, iclass 20, count 0 2006.201.13:45:22.24#ibcon#read 4, iclass 20, count 0 2006.201.13:45:22.24#ibcon#about to read 5, iclass 20, count 0 2006.201.13:45:22.24#ibcon#read 5, iclass 20, count 0 2006.201.13:45:22.24#ibcon#about to read 6, iclass 20, count 0 2006.201.13:45:22.24#ibcon#read 6, iclass 20, count 0 2006.201.13:45:22.24#ibcon#end of sib2, iclass 20, count 0 2006.201.13:45:22.24#ibcon#*after write, iclass 20, count 0 2006.201.13:45:22.24#ibcon#*before return 0, iclass 20, count 0 2006.201.13:45:22.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:22.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.13:45:22.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.13:45:22.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.13:45:22.24$vck44/vabw=wide 2006.201.13:45:22.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.13:45:22.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.13:45:22.24#ibcon#ireg 8 cls_cnt 0 2006.201.13:45:22.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:22.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:22.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:22.24#ibcon#enter wrdev, iclass 22, count 0 2006.201.13:45:22.24#ibcon#first serial, iclass 22, count 0 2006.201.13:45:22.24#ibcon#enter sib2, iclass 22, count 0 2006.201.13:45:22.24#ibcon#flushed, iclass 22, count 0 2006.201.13:45:22.24#ibcon#about to write, iclass 22, count 0 2006.201.13:45:22.24#ibcon#wrote, iclass 22, count 0 2006.201.13:45:22.24#ibcon#about to read 3, iclass 22, count 0 2006.201.13:45:22.26#ibcon#read 3, iclass 22, count 0 2006.201.13:45:22.26#ibcon#about to read 4, iclass 22, count 0 2006.201.13:45:22.26#ibcon#read 4, iclass 22, count 0 2006.201.13:45:22.26#ibcon#about to read 5, iclass 22, count 0 2006.201.13:45:22.26#ibcon#read 5, iclass 22, count 0 2006.201.13:45:22.26#ibcon#about to read 6, iclass 22, count 0 2006.201.13:45:22.26#ibcon#read 6, iclass 22, count 0 2006.201.13:45:22.26#ibcon#end of sib2, iclass 22, count 0 2006.201.13:45:22.26#ibcon#*mode == 0, iclass 22, count 0 2006.201.13:45:22.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.13:45:22.26#ibcon#[25=BW32\r\n] 2006.201.13:45:22.26#ibcon#*before write, iclass 22, count 0 2006.201.13:45:22.26#ibcon#enter sib2, iclass 22, count 0 2006.201.13:45:22.26#ibcon#flushed, iclass 22, count 0 2006.201.13:45:22.26#ibcon#about to write, iclass 22, count 0 2006.201.13:45:22.26#ibcon#wrote, iclass 22, count 0 2006.201.13:45:22.26#ibcon#about to read 3, iclass 22, count 0 2006.201.13:45:22.29#ibcon#read 3, iclass 22, count 0 2006.201.13:45:22.29#ibcon#about to read 4, iclass 22, count 0 2006.201.13:45:22.29#ibcon#read 4, iclass 22, count 0 2006.201.13:45:22.29#ibcon#about to read 5, iclass 22, count 0 2006.201.13:45:22.29#ibcon#read 5, iclass 22, count 0 2006.201.13:45:22.29#ibcon#about to read 6, iclass 22, count 0 2006.201.13:45:22.29#ibcon#read 6, iclass 22, count 0 2006.201.13:45:22.29#ibcon#end of sib2, iclass 22, count 0 2006.201.13:45:22.29#ibcon#*after write, iclass 22, count 0 2006.201.13:45:22.29#ibcon#*before return 0, iclass 22, count 0 2006.201.13:45:22.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:22.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.13:45:22.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.13:45:22.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.13:45:22.29$vck44/vbbw=wide 2006.201.13:45:22.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.13:45:22.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.13:45:22.29#ibcon#ireg 8 cls_cnt 0 2006.201.13:45:22.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:45:22.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:45:22.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:45:22.36#ibcon#enter wrdev, iclass 24, count 0 2006.201.13:45:22.36#ibcon#first serial, iclass 24, count 0 2006.201.13:45:22.36#ibcon#enter sib2, iclass 24, count 0 2006.201.13:45:22.36#ibcon#flushed, iclass 24, count 0 2006.201.13:45:22.36#ibcon#about to write, iclass 24, count 0 2006.201.13:45:22.36#ibcon#wrote, iclass 24, count 0 2006.201.13:45:22.36#ibcon#about to read 3, iclass 24, count 0 2006.201.13:45:22.38#ibcon#read 3, iclass 24, count 0 2006.201.13:45:22.38#ibcon#about to read 4, iclass 24, count 0 2006.201.13:45:22.38#ibcon#read 4, iclass 24, count 0 2006.201.13:45:22.38#ibcon#about to read 5, iclass 24, count 0 2006.201.13:45:22.38#ibcon#read 5, iclass 24, count 0 2006.201.13:45:22.38#ibcon#about to read 6, iclass 24, count 0 2006.201.13:45:22.38#ibcon#read 6, iclass 24, count 0 2006.201.13:45:22.38#ibcon#end of sib2, iclass 24, count 0 2006.201.13:45:22.38#ibcon#*mode == 0, iclass 24, count 0 2006.201.13:45:22.38#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.13:45:22.38#ibcon#[27=BW32\r\n] 2006.201.13:45:22.38#ibcon#*before write, iclass 24, count 0 2006.201.13:45:22.38#ibcon#enter sib2, iclass 24, count 0 2006.201.13:45:22.38#ibcon#flushed, iclass 24, count 0 2006.201.13:45:22.38#ibcon#about to write, iclass 24, count 0 2006.201.13:45:22.38#ibcon#wrote, iclass 24, count 0 2006.201.13:45:22.38#ibcon#about to read 3, iclass 24, count 0 2006.201.13:45:22.41#ibcon#read 3, iclass 24, count 0 2006.201.13:45:22.41#ibcon#about to read 4, iclass 24, count 0 2006.201.13:45:22.41#ibcon#read 4, iclass 24, count 0 2006.201.13:45:22.41#ibcon#about to read 5, iclass 24, count 0 2006.201.13:45:22.41#ibcon#read 5, iclass 24, count 0 2006.201.13:45:22.41#ibcon#about to read 6, iclass 24, count 0 2006.201.13:45:22.41#ibcon#read 6, iclass 24, count 0 2006.201.13:45:22.41#ibcon#end of sib2, iclass 24, count 0 2006.201.13:45:22.41#ibcon#*after write, iclass 24, count 0 2006.201.13:45:22.41#ibcon#*before return 0, iclass 24, count 0 2006.201.13:45:22.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:45:22.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:45:22.41#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.13:45:22.41#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.13:45:22.41$setupk4/ifdk4 2006.201.13:45:22.41$ifdk4/lo= 2006.201.13:45:22.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:45:22.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:45:22.41$ifdk4/patch= 2006.201.13:45:22.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:45:22.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:45:22.41$setupk4/!*+20s 2006.201.13:45:27.22#abcon#<5=/04 1.2 2.3 20.881001004.0\r\n> 2006.201.13:45:27.24#abcon#{5=INTERFACE CLEAR} 2006.201.13:45:27.30#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:45:29.14#trakl#Source acquired 2006.201.13:45:30.14#flagr#flagr/antenna,acquired 2006.201.13:45:36.89$setupk4/"tpicd 2006.201.13:45:36.89$setupk4/echo=off 2006.201.13:45:36.89$setupk4/xlog=off 2006.201.13:45:36.89:!2006.201.13:47:43 2006.201.13:47:43.00:preob 2006.201.13:47:43.13/onsource/TRACKING 2006.201.13:47:43.13:!2006.201.13:47:53 2006.201.13:47:53.00:"tape 2006.201.13:47:53.00:"st=record 2006.201.13:47:53.00:data_valid=on 2006.201.13:47:53.00:midob 2006.201.13:47:54.13/onsource/TRACKING 2006.201.13:47:54.13/wx/20.89,1003.9,100 2006.201.13:47:54.23/cable/+6.4734E-03 2006.201.13:47:55.32/va/01,08,usb,yes,28,30 2006.201.13:47:55.32/va/02,07,usb,yes,30,31 2006.201.13:47:55.32/va/03,08,usb,yes,27,28 2006.201.13:47:55.32/va/04,07,usb,yes,31,33 2006.201.13:47:55.32/va/05,04,usb,yes,27,28 2006.201.13:47:55.32/va/06,05,usb,yes,27,27 2006.201.13:47:55.32/va/07,05,usb,yes,27,28 2006.201.13:47:55.32/va/08,04,usb,yes,26,32 2006.201.13:47:55.55/valo/01,524.99,yes,locked 2006.201.13:47:55.55/valo/02,534.99,yes,locked 2006.201.13:47:55.55/valo/03,564.99,yes,locked 2006.201.13:47:55.55/valo/04,624.99,yes,locked 2006.201.13:47:55.55/valo/05,734.99,yes,locked 2006.201.13:47:55.55/valo/06,814.99,yes,locked 2006.201.13:47:55.55/valo/07,864.99,yes,locked 2006.201.13:47:55.55/valo/08,884.99,yes,locked 2006.201.13:47:56.64/vb/01,04,usb,yes,28,26 2006.201.13:47:56.64/vb/02,05,usb,yes,26,26 2006.201.13:47:56.64/vb/03,04,usb,yes,27,30 2006.201.13:47:56.64/vb/04,05,usb,yes,28,27 2006.201.13:47:56.64/vb/05,04,usb,yes,24,27 2006.201.13:47:56.64/vb/06,04,usb,yes,28,25 2006.201.13:47:56.64/vb/07,04,usb,yes,28,28 2006.201.13:47:56.64/vb/08,04,usb,yes,26,29 2006.201.13:47:56.88/vblo/01,629.99,yes,locked 2006.201.13:47:56.88/vblo/02,634.99,yes,locked 2006.201.13:47:56.88/vblo/03,649.99,yes,locked 2006.201.13:47:56.88/vblo/04,679.99,yes,locked 2006.201.13:47:56.88/vblo/05,709.99,yes,locked 2006.201.13:47:56.88/vblo/06,719.99,yes,locked 2006.201.13:47:56.88/vblo/07,734.99,yes,locked 2006.201.13:47:56.88/vblo/08,744.99,yes,locked 2006.201.13:47:57.03/vabw/8 2006.201.13:47:57.18/vbbw/8 2006.201.13:47:57.27/xfe/off,on,15.0 2006.201.13:47:57.66/ifatt/23,28,28,28 2006.201.13:47:58.05/fmout-gps/S +4.56E-07 2006.201.13:47:58.12:!2006.201.13:49:13 2006.201.13:49:13.00:data_valid=off 2006.201.13:49:13.00:"et 2006.201.13:49:13.00:!+3s 2006.201.13:49:16.02:"tape 2006.201.13:49:16.02:postob 2006.201.13:49:16.08/cable/+6.4740E-03 2006.201.13:49:16.08/wx/20.88,1003.9,100 2006.201.13:49:16.16/fmout-gps/S +4.56E-07 2006.201.13:49:16.16:scan_name=201-1353,jd0607,40 2006.201.13:49:16.17:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.201.13:49:17.14#flagr#flagr/antenna,new-source 2006.201.13:49:17.14:checkk5 2006.201.13:49:17.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:49:17.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:49:18.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:49:18.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:49:18.99/chk_obsdata//k5ts1/T2011347??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.13:49:19.36/chk_obsdata//k5ts2/T2011347??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.13:49:19.73/chk_obsdata//k5ts3/T2011347??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.13:49:20.09/chk_obsdata//k5ts4/T2011347??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.13:49:20.78/k5log//k5ts1_log_newline 2006.201.13:49:21.47/k5log//k5ts2_log_newline 2006.201.13:49:22.15/k5log//k5ts3_log_newline 2006.201.13:49:22.85/k5log//k5ts4_log_newline 2006.201.13:49:22.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:49:22.87:setupk4=1 2006.201.13:49:22.87$setupk4/echo=on 2006.201.13:49:22.87$setupk4/pcalon 2006.201.13:49:22.87$pcalon/"no phase cal control is implemented here 2006.201.13:49:22.87$setupk4/"tpicd=stop 2006.201.13:49:22.87$setupk4/"rec=synch_on 2006.201.13:49:22.87$setupk4/"rec_mode=128 2006.201.13:49:22.87$setupk4/!* 2006.201.13:49:22.87$setupk4/recpk4 2006.201.13:49:22.87$recpk4/recpatch= 2006.201.13:49:22.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:49:22.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:49:22.88$setupk4/vck44 2006.201.13:49:22.88$vck44/valo=1,524.99 2006.201.13:49:22.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.13:49:22.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.13:49:22.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:22.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:22.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:22.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:22.88#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:49:22.88#ibcon#first serial, iclass 17, count 0 2006.201.13:49:22.88#ibcon#enter sib2, iclass 17, count 0 2006.201.13:49:22.88#ibcon#flushed, iclass 17, count 0 2006.201.13:49:22.88#ibcon#about to write, iclass 17, count 0 2006.201.13:49:22.88#ibcon#wrote, iclass 17, count 0 2006.201.13:49:22.88#ibcon#about to read 3, iclass 17, count 0 2006.201.13:49:22.91#ibcon#read 3, iclass 17, count 0 2006.201.13:49:22.91#ibcon#about to read 4, iclass 17, count 0 2006.201.13:49:22.91#ibcon#read 4, iclass 17, count 0 2006.201.13:49:22.91#ibcon#about to read 5, iclass 17, count 0 2006.201.13:49:22.91#ibcon#read 5, iclass 17, count 0 2006.201.13:49:22.91#ibcon#about to read 6, iclass 17, count 0 2006.201.13:49:22.91#ibcon#read 6, iclass 17, count 0 2006.201.13:49:22.91#ibcon#end of sib2, iclass 17, count 0 2006.201.13:49:22.91#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:49:22.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:49:22.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:49:22.91#ibcon#*before write, iclass 17, count 0 2006.201.13:49:22.91#ibcon#enter sib2, iclass 17, count 0 2006.201.13:49:22.91#ibcon#flushed, iclass 17, count 0 2006.201.13:49:22.91#ibcon#about to write, iclass 17, count 0 2006.201.13:49:22.91#ibcon#wrote, iclass 17, count 0 2006.201.13:49:22.91#ibcon#about to read 3, iclass 17, count 0 2006.201.13:49:22.97#ibcon#read 3, iclass 17, count 0 2006.201.13:49:22.97#ibcon#about to read 4, iclass 17, count 0 2006.201.13:49:22.97#ibcon#read 4, iclass 17, count 0 2006.201.13:49:22.97#ibcon#about to read 5, iclass 17, count 0 2006.201.13:49:22.97#ibcon#read 5, iclass 17, count 0 2006.201.13:49:22.97#ibcon#about to read 6, iclass 17, count 0 2006.201.13:49:22.97#ibcon#read 6, iclass 17, count 0 2006.201.13:49:22.97#ibcon#end of sib2, iclass 17, count 0 2006.201.13:49:22.97#ibcon#*after write, iclass 17, count 0 2006.201.13:49:22.97#ibcon#*before return 0, iclass 17, count 0 2006.201.13:49:22.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:22.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:22.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:49:22.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:49:22.97$vck44/va=1,8 2006.201.13:49:22.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.13:49:22.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.13:49:22.97#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:22.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:22.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:22.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:22.97#ibcon#enter wrdev, iclass 19, count 2 2006.201.13:49:22.97#ibcon#first serial, iclass 19, count 2 2006.201.13:49:22.97#ibcon#enter sib2, iclass 19, count 2 2006.201.13:49:22.97#ibcon#flushed, iclass 19, count 2 2006.201.13:49:22.97#ibcon#about to write, iclass 19, count 2 2006.201.13:49:22.97#ibcon#wrote, iclass 19, count 2 2006.201.13:49:22.97#ibcon#about to read 3, iclass 19, count 2 2006.201.13:49:22.99#ibcon#read 3, iclass 19, count 2 2006.201.13:49:22.99#ibcon#about to read 4, iclass 19, count 2 2006.201.13:49:22.99#ibcon#read 4, iclass 19, count 2 2006.201.13:49:22.99#ibcon#about to read 5, iclass 19, count 2 2006.201.13:49:22.99#ibcon#read 5, iclass 19, count 2 2006.201.13:49:22.99#ibcon#about to read 6, iclass 19, count 2 2006.201.13:49:22.99#ibcon#read 6, iclass 19, count 2 2006.201.13:49:22.99#ibcon#end of sib2, iclass 19, count 2 2006.201.13:49:22.99#ibcon#*mode == 0, iclass 19, count 2 2006.201.13:49:22.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.13:49:22.99#ibcon#[25=AT01-08\r\n] 2006.201.13:49:22.99#ibcon#*before write, iclass 19, count 2 2006.201.13:49:22.99#ibcon#enter sib2, iclass 19, count 2 2006.201.13:49:22.99#ibcon#flushed, iclass 19, count 2 2006.201.13:49:22.99#ibcon#about to write, iclass 19, count 2 2006.201.13:49:22.99#ibcon#wrote, iclass 19, count 2 2006.201.13:49:22.99#ibcon#about to read 3, iclass 19, count 2 2006.201.13:49:23.03#ibcon#read 3, iclass 19, count 2 2006.201.13:49:23.03#ibcon#about to read 4, iclass 19, count 2 2006.201.13:49:23.03#ibcon#read 4, iclass 19, count 2 2006.201.13:49:23.03#ibcon#about to read 5, iclass 19, count 2 2006.201.13:49:23.03#ibcon#read 5, iclass 19, count 2 2006.201.13:49:23.03#ibcon#about to read 6, iclass 19, count 2 2006.201.13:49:23.03#ibcon#read 6, iclass 19, count 2 2006.201.13:49:23.03#ibcon#end of sib2, iclass 19, count 2 2006.201.13:49:23.03#ibcon#*after write, iclass 19, count 2 2006.201.13:49:23.03#ibcon#*before return 0, iclass 19, count 2 2006.201.13:49:23.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:23.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:23.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.13:49:23.03#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:23.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:23.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:23.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:23.15#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:49:23.15#ibcon#first serial, iclass 19, count 0 2006.201.13:49:23.15#ibcon#enter sib2, iclass 19, count 0 2006.201.13:49:23.15#ibcon#flushed, iclass 19, count 0 2006.201.13:49:23.15#ibcon#about to write, iclass 19, count 0 2006.201.13:49:23.15#ibcon#wrote, iclass 19, count 0 2006.201.13:49:23.15#ibcon#about to read 3, iclass 19, count 0 2006.201.13:49:23.17#ibcon#read 3, iclass 19, count 0 2006.201.13:49:23.17#ibcon#about to read 4, iclass 19, count 0 2006.201.13:49:23.17#ibcon#read 4, iclass 19, count 0 2006.201.13:49:23.17#ibcon#about to read 5, iclass 19, count 0 2006.201.13:49:23.17#ibcon#read 5, iclass 19, count 0 2006.201.13:49:23.17#ibcon#about to read 6, iclass 19, count 0 2006.201.13:49:23.17#ibcon#read 6, iclass 19, count 0 2006.201.13:49:23.17#ibcon#end of sib2, iclass 19, count 0 2006.201.13:49:23.17#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:49:23.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:49:23.17#ibcon#[25=USB\r\n] 2006.201.13:49:23.17#ibcon#*before write, iclass 19, count 0 2006.201.13:49:23.17#ibcon#enter sib2, iclass 19, count 0 2006.201.13:49:23.17#ibcon#flushed, iclass 19, count 0 2006.201.13:49:23.17#ibcon#about to write, iclass 19, count 0 2006.201.13:49:23.17#ibcon#wrote, iclass 19, count 0 2006.201.13:49:23.17#ibcon#about to read 3, iclass 19, count 0 2006.201.13:49:23.20#ibcon#read 3, iclass 19, count 0 2006.201.13:49:23.20#ibcon#about to read 4, iclass 19, count 0 2006.201.13:49:23.20#ibcon#read 4, iclass 19, count 0 2006.201.13:49:23.20#ibcon#about to read 5, iclass 19, count 0 2006.201.13:49:23.20#ibcon#read 5, iclass 19, count 0 2006.201.13:49:23.20#ibcon#about to read 6, iclass 19, count 0 2006.201.13:49:23.20#ibcon#read 6, iclass 19, count 0 2006.201.13:49:23.20#ibcon#end of sib2, iclass 19, count 0 2006.201.13:49:23.20#ibcon#*after write, iclass 19, count 0 2006.201.13:49:23.20#ibcon#*before return 0, iclass 19, count 0 2006.201.13:49:23.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:23.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:23.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:49:23.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:49:23.20$vck44/valo=2,534.99 2006.201.13:49:23.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.13:49:23.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.13:49:23.20#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:23.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:23.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:23.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:23.20#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:49:23.20#ibcon#first serial, iclass 21, count 0 2006.201.13:49:23.20#ibcon#enter sib2, iclass 21, count 0 2006.201.13:49:23.20#ibcon#flushed, iclass 21, count 0 2006.201.13:49:23.20#ibcon#about to write, iclass 21, count 0 2006.201.13:49:23.20#ibcon#wrote, iclass 21, count 0 2006.201.13:49:23.20#ibcon#about to read 3, iclass 21, count 0 2006.201.13:49:23.22#ibcon#read 3, iclass 21, count 0 2006.201.13:49:23.22#ibcon#about to read 4, iclass 21, count 0 2006.201.13:49:23.22#ibcon#read 4, iclass 21, count 0 2006.201.13:49:23.22#ibcon#about to read 5, iclass 21, count 0 2006.201.13:49:23.22#ibcon#read 5, iclass 21, count 0 2006.201.13:49:23.22#ibcon#about to read 6, iclass 21, count 0 2006.201.13:49:23.22#ibcon#read 6, iclass 21, count 0 2006.201.13:49:23.22#ibcon#end of sib2, iclass 21, count 0 2006.201.13:49:23.22#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:49:23.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:49:23.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:49:23.22#ibcon#*before write, iclass 21, count 0 2006.201.13:49:23.22#ibcon#enter sib2, iclass 21, count 0 2006.201.13:49:23.22#ibcon#flushed, iclass 21, count 0 2006.201.13:49:23.22#ibcon#about to write, iclass 21, count 0 2006.201.13:49:23.22#ibcon#wrote, iclass 21, count 0 2006.201.13:49:23.22#ibcon#about to read 3, iclass 21, count 0 2006.201.13:49:23.27#ibcon#read 3, iclass 21, count 0 2006.201.13:49:23.27#ibcon#about to read 4, iclass 21, count 0 2006.201.13:49:23.27#ibcon#read 4, iclass 21, count 0 2006.201.13:49:23.27#ibcon#about to read 5, iclass 21, count 0 2006.201.13:49:23.27#ibcon#read 5, iclass 21, count 0 2006.201.13:49:23.27#ibcon#about to read 6, iclass 21, count 0 2006.201.13:49:23.27#ibcon#read 6, iclass 21, count 0 2006.201.13:49:23.27#ibcon#end of sib2, iclass 21, count 0 2006.201.13:49:23.27#ibcon#*after write, iclass 21, count 0 2006.201.13:49:23.27#ibcon#*before return 0, iclass 21, count 0 2006.201.13:49:23.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:23.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:23.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:49:23.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:49:23.27$vck44/va=2,7 2006.201.13:49:23.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.13:49:23.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.13:49:23.27#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:23.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:23.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:23.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:23.32#ibcon#enter wrdev, iclass 23, count 2 2006.201.13:49:23.32#ibcon#first serial, iclass 23, count 2 2006.201.13:49:23.32#ibcon#enter sib2, iclass 23, count 2 2006.201.13:49:23.32#ibcon#flushed, iclass 23, count 2 2006.201.13:49:23.32#ibcon#about to write, iclass 23, count 2 2006.201.13:49:23.32#ibcon#wrote, iclass 23, count 2 2006.201.13:49:23.32#ibcon#about to read 3, iclass 23, count 2 2006.201.13:49:23.34#ibcon#read 3, iclass 23, count 2 2006.201.13:49:23.34#ibcon#about to read 4, iclass 23, count 2 2006.201.13:49:23.34#ibcon#read 4, iclass 23, count 2 2006.201.13:49:23.34#ibcon#about to read 5, iclass 23, count 2 2006.201.13:49:23.34#ibcon#read 5, iclass 23, count 2 2006.201.13:49:23.34#ibcon#about to read 6, iclass 23, count 2 2006.201.13:49:23.34#ibcon#read 6, iclass 23, count 2 2006.201.13:49:23.34#ibcon#end of sib2, iclass 23, count 2 2006.201.13:49:23.34#ibcon#*mode == 0, iclass 23, count 2 2006.201.13:49:23.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.13:49:23.34#ibcon#[25=AT02-07\r\n] 2006.201.13:49:23.34#ibcon#*before write, iclass 23, count 2 2006.201.13:49:23.34#ibcon#enter sib2, iclass 23, count 2 2006.201.13:49:23.34#ibcon#flushed, iclass 23, count 2 2006.201.13:49:23.34#ibcon#about to write, iclass 23, count 2 2006.201.13:49:23.34#ibcon#wrote, iclass 23, count 2 2006.201.13:49:23.34#ibcon#about to read 3, iclass 23, count 2 2006.201.13:49:23.37#ibcon#read 3, iclass 23, count 2 2006.201.13:49:23.37#ibcon#about to read 4, iclass 23, count 2 2006.201.13:49:23.37#ibcon#read 4, iclass 23, count 2 2006.201.13:49:23.37#ibcon#about to read 5, iclass 23, count 2 2006.201.13:49:23.37#ibcon#read 5, iclass 23, count 2 2006.201.13:49:23.37#ibcon#about to read 6, iclass 23, count 2 2006.201.13:49:23.37#ibcon#read 6, iclass 23, count 2 2006.201.13:49:23.37#ibcon#end of sib2, iclass 23, count 2 2006.201.13:49:23.37#ibcon#*after write, iclass 23, count 2 2006.201.13:49:23.37#ibcon#*before return 0, iclass 23, count 2 2006.201.13:49:23.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:23.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:23.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.13:49:23.37#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:23.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:23.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:23.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:23.49#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:49:23.49#ibcon#first serial, iclass 23, count 0 2006.201.13:49:23.49#ibcon#enter sib2, iclass 23, count 0 2006.201.13:49:23.49#ibcon#flushed, iclass 23, count 0 2006.201.13:49:23.49#ibcon#about to write, iclass 23, count 0 2006.201.13:49:23.49#ibcon#wrote, iclass 23, count 0 2006.201.13:49:23.49#ibcon#about to read 3, iclass 23, count 0 2006.201.13:49:23.51#ibcon#read 3, iclass 23, count 0 2006.201.13:49:23.51#ibcon#about to read 4, iclass 23, count 0 2006.201.13:49:23.51#ibcon#read 4, iclass 23, count 0 2006.201.13:49:23.51#ibcon#about to read 5, iclass 23, count 0 2006.201.13:49:23.51#ibcon#read 5, iclass 23, count 0 2006.201.13:49:23.51#ibcon#about to read 6, iclass 23, count 0 2006.201.13:49:23.51#ibcon#read 6, iclass 23, count 0 2006.201.13:49:23.51#ibcon#end of sib2, iclass 23, count 0 2006.201.13:49:23.51#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:49:23.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:49:23.51#ibcon#[25=USB\r\n] 2006.201.13:49:23.51#ibcon#*before write, iclass 23, count 0 2006.201.13:49:23.51#ibcon#enter sib2, iclass 23, count 0 2006.201.13:49:23.51#ibcon#flushed, iclass 23, count 0 2006.201.13:49:23.51#ibcon#about to write, iclass 23, count 0 2006.201.13:49:23.51#ibcon#wrote, iclass 23, count 0 2006.201.13:49:23.51#ibcon#about to read 3, iclass 23, count 0 2006.201.13:49:23.54#ibcon#read 3, iclass 23, count 0 2006.201.13:49:23.54#ibcon#about to read 4, iclass 23, count 0 2006.201.13:49:23.54#ibcon#read 4, iclass 23, count 0 2006.201.13:49:23.54#ibcon#about to read 5, iclass 23, count 0 2006.201.13:49:23.54#ibcon#read 5, iclass 23, count 0 2006.201.13:49:23.54#ibcon#about to read 6, iclass 23, count 0 2006.201.13:49:23.54#ibcon#read 6, iclass 23, count 0 2006.201.13:49:23.54#ibcon#end of sib2, iclass 23, count 0 2006.201.13:49:23.54#ibcon#*after write, iclass 23, count 0 2006.201.13:49:23.54#ibcon#*before return 0, iclass 23, count 0 2006.201.13:49:23.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:23.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:23.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:49:23.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:49:23.54$vck44/valo=3,564.99 2006.201.13:49:23.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.13:49:23.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.13:49:23.54#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:23.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:23.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:23.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:23.54#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:49:23.54#ibcon#first serial, iclass 25, count 0 2006.201.13:49:23.54#ibcon#enter sib2, iclass 25, count 0 2006.201.13:49:23.54#ibcon#flushed, iclass 25, count 0 2006.201.13:49:23.54#ibcon#about to write, iclass 25, count 0 2006.201.13:49:23.54#ibcon#wrote, iclass 25, count 0 2006.201.13:49:23.54#ibcon#about to read 3, iclass 25, count 0 2006.201.13:49:23.56#ibcon#read 3, iclass 25, count 0 2006.201.13:49:23.56#ibcon#about to read 4, iclass 25, count 0 2006.201.13:49:23.56#ibcon#read 4, iclass 25, count 0 2006.201.13:49:23.56#ibcon#about to read 5, iclass 25, count 0 2006.201.13:49:23.56#ibcon#read 5, iclass 25, count 0 2006.201.13:49:23.56#ibcon#about to read 6, iclass 25, count 0 2006.201.13:49:23.56#ibcon#read 6, iclass 25, count 0 2006.201.13:49:23.56#ibcon#end of sib2, iclass 25, count 0 2006.201.13:49:23.56#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:49:23.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:49:23.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:49:23.56#ibcon#*before write, iclass 25, count 0 2006.201.13:49:23.56#ibcon#enter sib2, iclass 25, count 0 2006.201.13:49:23.56#ibcon#flushed, iclass 25, count 0 2006.201.13:49:23.56#ibcon#about to write, iclass 25, count 0 2006.201.13:49:23.56#ibcon#wrote, iclass 25, count 0 2006.201.13:49:23.56#ibcon#about to read 3, iclass 25, count 0 2006.201.13:49:23.60#ibcon#read 3, iclass 25, count 0 2006.201.13:49:23.60#ibcon#about to read 4, iclass 25, count 0 2006.201.13:49:23.60#ibcon#read 4, iclass 25, count 0 2006.201.13:49:23.60#ibcon#about to read 5, iclass 25, count 0 2006.201.13:49:23.60#ibcon#read 5, iclass 25, count 0 2006.201.13:49:23.60#ibcon#about to read 6, iclass 25, count 0 2006.201.13:49:23.60#ibcon#read 6, iclass 25, count 0 2006.201.13:49:23.60#ibcon#end of sib2, iclass 25, count 0 2006.201.13:49:23.60#ibcon#*after write, iclass 25, count 0 2006.201.13:49:23.60#ibcon#*before return 0, iclass 25, count 0 2006.201.13:49:23.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:23.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:23.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:49:23.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:49:23.60$vck44/va=3,8 2006.201.13:49:23.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.13:49:23.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.13:49:23.60#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:23.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:23.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:23.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:23.66#ibcon#enter wrdev, iclass 27, count 2 2006.201.13:49:23.66#ibcon#first serial, iclass 27, count 2 2006.201.13:49:23.66#ibcon#enter sib2, iclass 27, count 2 2006.201.13:49:23.66#ibcon#flushed, iclass 27, count 2 2006.201.13:49:23.66#ibcon#about to write, iclass 27, count 2 2006.201.13:49:23.66#ibcon#wrote, iclass 27, count 2 2006.201.13:49:23.66#ibcon#about to read 3, iclass 27, count 2 2006.201.13:49:23.68#ibcon#read 3, iclass 27, count 2 2006.201.13:49:23.68#ibcon#about to read 4, iclass 27, count 2 2006.201.13:49:23.68#ibcon#read 4, iclass 27, count 2 2006.201.13:49:23.68#ibcon#about to read 5, iclass 27, count 2 2006.201.13:49:23.68#ibcon#read 5, iclass 27, count 2 2006.201.13:49:23.68#ibcon#about to read 6, iclass 27, count 2 2006.201.13:49:23.68#ibcon#read 6, iclass 27, count 2 2006.201.13:49:23.68#ibcon#end of sib2, iclass 27, count 2 2006.201.13:49:23.68#ibcon#*mode == 0, iclass 27, count 2 2006.201.13:49:23.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.13:49:23.68#ibcon#[25=AT03-08\r\n] 2006.201.13:49:23.68#ibcon#*before write, iclass 27, count 2 2006.201.13:49:23.68#ibcon#enter sib2, iclass 27, count 2 2006.201.13:49:23.68#ibcon#flushed, iclass 27, count 2 2006.201.13:49:23.68#ibcon#about to write, iclass 27, count 2 2006.201.13:49:23.68#ibcon#wrote, iclass 27, count 2 2006.201.13:49:23.68#ibcon#about to read 3, iclass 27, count 2 2006.201.13:49:23.71#ibcon#read 3, iclass 27, count 2 2006.201.13:49:23.71#ibcon#about to read 4, iclass 27, count 2 2006.201.13:49:23.71#ibcon#read 4, iclass 27, count 2 2006.201.13:49:23.71#ibcon#about to read 5, iclass 27, count 2 2006.201.13:49:23.71#ibcon#read 5, iclass 27, count 2 2006.201.13:49:23.71#ibcon#about to read 6, iclass 27, count 2 2006.201.13:49:23.71#ibcon#read 6, iclass 27, count 2 2006.201.13:49:23.71#ibcon#end of sib2, iclass 27, count 2 2006.201.13:49:23.71#ibcon#*after write, iclass 27, count 2 2006.201.13:49:23.71#ibcon#*before return 0, iclass 27, count 2 2006.201.13:49:23.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:23.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:23.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.13:49:23.71#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:23.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:23.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:23.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:23.83#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:49:23.83#ibcon#first serial, iclass 27, count 0 2006.201.13:49:23.83#ibcon#enter sib2, iclass 27, count 0 2006.201.13:49:23.83#ibcon#flushed, iclass 27, count 0 2006.201.13:49:23.83#ibcon#about to write, iclass 27, count 0 2006.201.13:49:23.83#ibcon#wrote, iclass 27, count 0 2006.201.13:49:23.83#ibcon#about to read 3, iclass 27, count 0 2006.201.13:49:23.85#ibcon#read 3, iclass 27, count 0 2006.201.13:49:23.85#ibcon#about to read 4, iclass 27, count 0 2006.201.13:49:23.85#ibcon#read 4, iclass 27, count 0 2006.201.13:49:23.85#ibcon#about to read 5, iclass 27, count 0 2006.201.13:49:23.85#ibcon#read 5, iclass 27, count 0 2006.201.13:49:23.85#ibcon#about to read 6, iclass 27, count 0 2006.201.13:49:23.85#ibcon#read 6, iclass 27, count 0 2006.201.13:49:23.85#ibcon#end of sib2, iclass 27, count 0 2006.201.13:49:23.85#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:49:23.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:49:23.85#ibcon#[25=USB\r\n] 2006.201.13:49:23.85#ibcon#*before write, iclass 27, count 0 2006.201.13:49:23.85#ibcon#enter sib2, iclass 27, count 0 2006.201.13:49:23.85#ibcon#flushed, iclass 27, count 0 2006.201.13:49:23.85#ibcon#about to write, iclass 27, count 0 2006.201.13:49:23.85#ibcon#wrote, iclass 27, count 0 2006.201.13:49:23.85#ibcon#about to read 3, iclass 27, count 0 2006.201.13:49:23.88#ibcon#read 3, iclass 27, count 0 2006.201.13:49:23.88#ibcon#about to read 4, iclass 27, count 0 2006.201.13:49:23.88#ibcon#read 4, iclass 27, count 0 2006.201.13:49:23.88#ibcon#about to read 5, iclass 27, count 0 2006.201.13:49:23.88#ibcon#read 5, iclass 27, count 0 2006.201.13:49:23.88#ibcon#about to read 6, iclass 27, count 0 2006.201.13:49:23.88#ibcon#read 6, iclass 27, count 0 2006.201.13:49:23.88#ibcon#end of sib2, iclass 27, count 0 2006.201.13:49:23.88#ibcon#*after write, iclass 27, count 0 2006.201.13:49:23.88#ibcon#*before return 0, iclass 27, count 0 2006.201.13:49:23.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:23.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:23.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:49:23.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:49:23.88$vck44/valo=4,624.99 2006.201.13:49:23.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.13:49:23.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.13:49:23.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:23.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:23.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:23.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:23.88#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:49:23.88#ibcon#first serial, iclass 29, count 0 2006.201.13:49:23.88#ibcon#enter sib2, iclass 29, count 0 2006.201.13:49:23.88#ibcon#flushed, iclass 29, count 0 2006.201.13:49:23.88#ibcon#about to write, iclass 29, count 0 2006.201.13:49:23.88#ibcon#wrote, iclass 29, count 0 2006.201.13:49:23.88#ibcon#about to read 3, iclass 29, count 0 2006.201.13:49:23.90#ibcon#read 3, iclass 29, count 0 2006.201.13:49:23.90#ibcon#about to read 4, iclass 29, count 0 2006.201.13:49:23.90#ibcon#read 4, iclass 29, count 0 2006.201.13:49:23.90#ibcon#about to read 5, iclass 29, count 0 2006.201.13:49:23.90#ibcon#read 5, iclass 29, count 0 2006.201.13:49:23.90#ibcon#about to read 6, iclass 29, count 0 2006.201.13:49:23.90#ibcon#read 6, iclass 29, count 0 2006.201.13:49:23.90#ibcon#end of sib2, iclass 29, count 0 2006.201.13:49:23.90#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:49:23.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:49:23.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:49:23.90#ibcon#*before write, iclass 29, count 0 2006.201.13:49:23.90#ibcon#enter sib2, iclass 29, count 0 2006.201.13:49:23.90#ibcon#flushed, iclass 29, count 0 2006.201.13:49:23.90#ibcon#about to write, iclass 29, count 0 2006.201.13:49:23.90#ibcon#wrote, iclass 29, count 0 2006.201.13:49:23.90#ibcon#about to read 3, iclass 29, count 0 2006.201.13:49:23.94#ibcon#read 3, iclass 29, count 0 2006.201.13:49:23.94#ibcon#about to read 4, iclass 29, count 0 2006.201.13:49:23.94#ibcon#read 4, iclass 29, count 0 2006.201.13:49:23.94#ibcon#about to read 5, iclass 29, count 0 2006.201.13:49:23.94#ibcon#read 5, iclass 29, count 0 2006.201.13:49:23.94#ibcon#about to read 6, iclass 29, count 0 2006.201.13:49:23.94#ibcon#read 6, iclass 29, count 0 2006.201.13:49:23.94#ibcon#end of sib2, iclass 29, count 0 2006.201.13:49:23.94#ibcon#*after write, iclass 29, count 0 2006.201.13:49:23.94#ibcon#*before return 0, iclass 29, count 0 2006.201.13:49:23.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:23.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:23.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:49:23.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:49:23.94$vck44/va=4,7 2006.201.13:49:23.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.13:49:23.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.13:49:23.94#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:23.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:24.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:24.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:24.00#ibcon#enter wrdev, iclass 31, count 2 2006.201.13:49:24.00#ibcon#first serial, iclass 31, count 2 2006.201.13:49:24.00#ibcon#enter sib2, iclass 31, count 2 2006.201.13:49:24.00#ibcon#flushed, iclass 31, count 2 2006.201.13:49:24.00#ibcon#about to write, iclass 31, count 2 2006.201.13:49:24.00#ibcon#wrote, iclass 31, count 2 2006.201.13:49:24.00#ibcon#about to read 3, iclass 31, count 2 2006.201.13:49:24.02#ibcon#read 3, iclass 31, count 2 2006.201.13:49:24.02#ibcon#about to read 4, iclass 31, count 2 2006.201.13:49:24.02#ibcon#read 4, iclass 31, count 2 2006.201.13:49:24.02#ibcon#about to read 5, iclass 31, count 2 2006.201.13:49:24.02#ibcon#read 5, iclass 31, count 2 2006.201.13:49:24.02#ibcon#about to read 6, iclass 31, count 2 2006.201.13:49:24.02#ibcon#read 6, iclass 31, count 2 2006.201.13:49:24.02#ibcon#end of sib2, iclass 31, count 2 2006.201.13:49:24.02#ibcon#*mode == 0, iclass 31, count 2 2006.201.13:49:24.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.13:49:24.02#ibcon#[25=AT04-07\r\n] 2006.201.13:49:24.02#ibcon#*before write, iclass 31, count 2 2006.201.13:49:24.02#ibcon#enter sib2, iclass 31, count 2 2006.201.13:49:24.02#ibcon#flushed, iclass 31, count 2 2006.201.13:49:24.02#ibcon#about to write, iclass 31, count 2 2006.201.13:49:24.02#ibcon#wrote, iclass 31, count 2 2006.201.13:49:24.02#ibcon#about to read 3, iclass 31, count 2 2006.201.13:49:24.05#ibcon#read 3, iclass 31, count 2 2006.201.13:49:24.05#ibcon#about to read 4, iclass 31, count 2 2006.201.13:49:24.05#ibcon#read 4, iclass 31, count 2 2006.201.13:49:24.05#ibcon#about to read 5, iclass 31, count 2 2006.201.13:49:24.05#ibcon#read 5, iclass 31, count 2 2006.201.13:49:24.05#ibcon#about to read 6, iclass 31, count 2 2006.201.13:49:24.05#ibcon#read 6, iclass 31, count 2 2006.201.13:49:24.05#ibcon#end of sib2, iclass 31, count 2 2006.201.13:49:24.05#ibcon#*after write, iclass 31, count 2 2006.201.13:49:24.05#ibcon#*before return 0, iclass 31, count 2 2006.201.13:49:24.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:24.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:24.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.13:49:24.05#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:24.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:24.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:24.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:24.17#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:49:24.17#ibcon#first serial, iclass 31, count 0 2006.201.13:49:24.17#ibcon#enter sib2, iclass 31, count 0 2006.201.13:49:24.17#ibcon#flushed, iclass 31, count 0 2006.201.13:49:24.17#ibcon#about to write, iclass 31, count 0 2006.201.13:49:24.17#ibcon#wrote, iclass 31, count 0 2006.201.13:49:24.17#ibcon#about to read 3, iclass 31, count 0 2006.201.13:49:24.19#ibcon#read 3, iclass 31, count 0 2006.201.13:49:24.19#ibcon#about to read 4, iclass 31, count 0 2006.201.13:49:24.19#ibcon#read 4, iclass 31, count 0 2006.201.13:49:24.19#ibcon#about to read 5, iclass 31, count 0 2006.201.13:49:24.19#ibcon#read 5, iclass 31, count 0 2006.201.13:49:24.19#ibcon#about to read 6, iclass 31, count 0 2006.201.13:49:24.19#ibcon#read 6, iclass 31, count 0 2006.201.13:49:24.19#ibcon#end of sib2, iclass 31, count 0 2006.201.13:49:24.19#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:49:24.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:49:24.19#ibcon#[25=USB\r\n] 2006.201.13:49:24.19#ibcon#*before write, iclass 31, count 0 2006.201.13:49:24.19#ibcon#enter sib2, iclass 31, count 0 2006.201.13:49:24.19#ibcon#flushed, iclass 31, count 0 2006.201.13:49:24.19#ibcon#about to write, iclass 31, count 0 2006.201.13:49:24.19#ibcon#wrote, iclass 31, count 0 2006.201.13:49:24.19#ibcon#about to read 3, iclass 31, count 0 2006.201.13:49:24.22#ibcon#read 3, iclass 31, count 0 2006.201.13:49:24.22#ibcon#about to read 4, iclass 31, count 0 2006.201.13:49:24.22#ibcon#read 4, iclass 31, count 0 2006.201.13:49:24.22#ibcon#about to read 5, iclass 31, count 0 2006.201.13:49:24.22#ibcon#read 5, iclass 31, count 0 2006.201.13:49:24.22#ibcon#about to read 6, iclass 31, count 0 2006.201.13:49:24.22#ibcon#read 6, iclass 31, count 0 2006.201.13:49:24.22#ibcon#end of sib2, iclass 31, count 0 2006.201.13:49:24.22#ibcon#*after write, iclass 31, count 0 2006.201.13:49:24.22#ibcon#*before return 0, iclass 31, count 0 2006.201.13:49:24.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:24.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:24.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:49:24.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:49:24.22$vck44/valo=5,734.99 2006.201.13:49:24.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.13:49:24.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.13:49:24.22#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:24.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:24.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:24.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:24.22#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:49:24.22#ibcon#first serial, iclass 33, count 0 2006.201.13:49:24.22#ibcon#enter sib2, iclass 33, count 0 2006.201.13:49:24.22#ibcon#flushed, iclass 33, count 0 2006.201.13:49:24.22#ibcon#about to write, iclass 33, count 0 2006.201.13:49:24.22#ibcon#wrote, iclass 33, count 0 2006.201.13:49:24.22#ibcon#about to read 3, iclass 33, count 0 2006.201.13:49:24.24#ibcon#read 3, iclass 33, count 0 2006.201.13:49:24.24#ibcon#about to read 4, iclass 33, count 0 2006.201.13:49:24.24#ibcon#read 4, iclass 33, count 0 2006.201.13:49:24.24#ibcon#about to read 5, iclass 33, count 0 2006.201.13:49:24.24#ibcon#read 5, iclass 33, count 0 2006.201.13:49:24.24#ibcon#about to read 6, iclass 33, count 0 2006.201.13:49:24.24#ibcon#read 6, iclass 33, count 0 2006.201.13:49:24.24#ibcon#end of sib2, iclass 33, count 0 2006.201.13:49:24.24#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:49:24.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:49:24.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:49:24.24#ibcon#*before write, iclass 33, count 0 2006.201.13:49:24.24#ibcon#enter sib2, iclass 33, count 0 2006.201.13:49:24.24#ibcon#flushed, iclass 33, count 0 2006.201.13:49:24.24#ibcon#about to write, iclass 33, count 0 2006.201.13:49:24.24#ibcon#wrote, iclass 33, count 0 2006.201.13:49:24.24#ibcon#about to read 3, iclass 33, count 0 2006.201.13:49:24.28#ibcon#read 3, iclass 33, count 0 2006.201.13:49:24.28#ibcon#about to read 4, iclass 33, count 0 2006.201.13:49:24.28#ibcon#read 4, iclass 33, count 0 2006.201.13:49:24.28#ibcon#about to read 5, iclass 33, count 0 2006.201.13:49:24.28#ibcon#read 5, iclass 33, count 0 2006.201.13:49:24.28#ibcon#about to read 6, iclass 33, count 0 2006.201.13:49:24.28#ibcon#read 6, iclass 33, count 0 2006.201.13:49:24.28#ibcon#end of sib2, iclass 33, count 0 2006.201.13:49:24.28#ibcon#*after write, iclass 33, count 0 2006.201.13:49:24.28#ibcon#*before return 0, iclass 33, count 0 2006.201.13:49:24.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:24.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:24.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:49:24.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:49:24.28$vck44/va=5,4 2006.201.13:49:24.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.13:49:24.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.13:49:24.28#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:24.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:24.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:24.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:24.34#ibcon#enter wrdev, iclass 35, count 2 2006.201.13:49:24.34#ibcon#first serial, iclass 35, count 2 2006.201.13:49:24.34#ibcon#enter sib2, iclass 35, count 2 2006.201.13:49:24.34#ibcon#flushed, iclass 35, count 2 2006.201.13:49:24.34#ibcon#about to write, iclass 35, count 2 2006.201.13:49:24.34#ibcon#wrote, iclass 35, count 2 2006.201.13:49:24.34#ibcon#about to read 3, iclass 35, count 2 2006.201.13:49:24.36#ibcon#read 3, iclass 35, count 2 2006.201.13:49:24.36#ibcon#about to read 4, iclass 35, count 2 2006.201.13:49:24.36#ibcon#read 4, iclass 35, count 2 2006.201.13:49:24.36#ibcon#about to read 5, iclass 35, count 2 2006.201.13:49:24.36#ibcon#read 5, iclass 35, count 2 2006.201.13:49:24.36#ibcon#about to read 6, iclass 35, count 2 2006.201.13:49:24.36#ibcon#read 6, iclass 35, count 2 2006.201.13:49:24.36#ibcon#end of sib2, iclass 35, count 2 2006.201.13:49:24.36#ibcon#*mode == 0, iclass 35, count 2 2006.201.13:49:24.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.13:49:24.36#ibcon#[25=AT05-04\r\n] 2006.201.13:49:24.36#ibcon#*before write, iclass 35, count 2 2006.201.13:49:24.36#ibcon#enter sib2, iclass 35, count 2 2006.201.13:49:24.36#ibcon#flushed, iclass 35, count 2 2006.201.13:49:24.36#ibcon#about to write, iclass 35, count 2 2006.201.13:49:24.36#ibcon#wrote, iclass 35, count 2 2006.201.13:49:24.36#ibcon#about to read 3, iclass 35, count 2 2006.201.13:49:24.39#ibcon#read 3, iclass 35, count 2 2006.201.13:49:24.39#ibcon#about to read 4, iclass 35, count 2 2006.201.13:49:24.39#ibcon#read 4, iclass 35, count 2 2006.201.13:49:24.39#ibcon#about to read 5, iclass 35, count 2 2006.201.13:49:24.39#ibcon#read 5, iclass 35, count 2 2006.201.13:49:24.39#ibcon#about to read 6, iclass 35, count 2 2006.201.13:49:24.39#ibcon#read 6, iclass 35, count 2 2006.201.13:49:24.39#ibcon#end of sib2, iclass 35, count 2 2006.201.13:49:24.39#ibcon#*after write, iclass 35, count 2 2006.201.13:49:24.39#ibcon#*before return 0, iclass 35, count 2 2006.201.13:49:24.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:24.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:24.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.13:49:24.39#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:24.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:24.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:24.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:24.51#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:49:24.51#ibcon#first serial, iclass 35, count 0 2006.201.13:49:24.51#ibcon#enter sib2, iclass 35, count 0 2006.201.13:49:24.51#ibcon#flushed, iclass 35, count 0 2006.201.13:49:24.51#ibcon#about to write, iclass 35, count 0 2006.201.13:49:24.51#ibcon#wrote, iclass 35, count 0 2006.201.13:49:24.51#ibcon#about to read 3, iclass 35, count 0 2006.201.13:49:24.53#ibcon#read 3, iclass 35, count 0 2006.201.13:49:24.53#ibcon#about to read 4, iclass 35, count 0 2006.201.13:49:24.53#ibcon#read 4, iclass 35, count 0 2006.201.13:49:24.53#ibcon#about to read 5, iclass 35, count 0 2006.201.13:49:24.53#ibcon#read 5, iclass 35, count 0 2006.201.13:49:24.53#ibcon#about to read 6, iclass 35, count 0 2006.201.13:49:24.53#ibcon#read 6, iclass 35, count 0 2006.201.13:49:24.53#ibcon#end of sib2, iclass 35, count 0 2006.201.13:49:24.53#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:49:24.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:49:24.53#ibcon#[25=USB\r\n] 2006.201.13:49:24.53#ibcon#*before write, iclass 35, count 0 2006.201.13:49:24.53#ibcon#enter sib2, iclass 35, count 0 2006.201.13:49:24.53#ibcon#flushed, iclass 35, count 0 2006.201.13:49:24.53#ibcon#about to write, iclass 35, count 0 2006.201.13:49:24.53#ibcon#wrote, iclass 35, count 0 2006.201.13:49:24.53#ibcon#about to read 3, iclass 35, count 0 2006.201.13:49:24.56#ibcon#read 3, iclass 35, count 0 2006.201.13:49:24.56#ibcon#about to read 4, iclass 35, count 0 2006.201.13:49:24.56#ibcon#read 4, iclass 35, count 0 2006.201.13:49:24.56#ibcon#about to read 5, iclass 35, count 0 2006.201.13:49:24.56#ibcon#read 5, iclass 35, count 0 2006.201.13:49:24.56#ibcon#about to read 6, iclass 35, count 0 2006.201.13:49:24.56#ibcon#read 6, iclass 35, count 0 2006.201.13:49:24.56#ibcon#end of sib2, iclass 35, count 0 2006.201.13:49:24.56#ibcon#*after write, iclass 35, count 0 2006.201.13:49:24.56#ibcon#*before return 0, iclass 35, count 0 2006.201.13:49:24.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:24.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:24.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:49:24.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:49:24.56$vck44/valo=6,814.99 2006.201.13:49:24.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.13:49:24.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.13:49:24.56#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:24.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:24.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:24.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:24.56#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:49:24.56#ibcon#first serial, iclass 37, count 0 2006.201.13:49:24.56#ibcon#enter sib2, iclass 37, count 0 2006.201.13:49:24.56#ibcon#flushed, iclass 37, count 0 2006.201.13:49:24.56#ibcon#about to write, iclass 37, count 0 2006.201.13:49:24.56#ibcon#wrote, iclass 37, count 0 2006.201.13:49:24.56#ibcon#about to read 3, iclass 37, count 0 2006.201.13:49:24.58#ibcon#read 3, iclass 37, count 0 2006.201.13:49:24.58#ibcon#about to read 4, iclass 37, count 0 2006.201.13:49:24.58#ibcon#read 4, iclass 37, count 0 2006.201.13:49:24.58#ibcon#about to read 5, iclass 37, count 0 2006.201.13:49:24.58#ibcon#read 5, iclass 37, count 0 2006.201.13:49:24.58#ibcon#about to read 6, iclass 37, count 0 2006.201.13:49:24.58#ibcon#read 6, iclass 37, count 0 2006.201.13:49:24.58#ibcon#end of sib2, iclass 37, count 0 2006.201.13:49:24.58#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:49:24.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:49:24.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:49:24.58#ibcon#*before write, iclass 37, count 0 2006.201.13:49:24.58#ibcon#enter sib2, iclass 37, count 0 2006.201.13:49:24.58#ibcon#flushed, iclass 37, count 0 2006.201.13:49:24.58#ibcon#about to write, iclass 37, count 0 2006.201.13:49:24.58#ibcon#wrote, iclass 37, count 0 2006.201.13:49:24.58#ibcon#about to read 3, iclass 37, count 0 2006.201.13:49:24.62#ibcon#read 3, iclass 37, count 0 2006.201.13:49:24.62#ibcon#about to read 4, iclass 37, count 0 2006.201.13:49:24.62#ibcon#read 4, iclass 37, count 0 2006.201.13:49:24.62#ibcon#about to read 5, iclass 37, count 0 2006.201.13:49:24.62#ibcon#read 5, iclass 37, count 0 2006.201.13:49:24.62#ibcon#about to read 6, iclass 37, count 0 2006.201.13:49:24.62#ibcon#read 6, iclass 37, count 0 2006.201.13:49:24.62#ibcon#end of sib2, iclass 37, count 0 2006.201.13:49:24.62#ibcon#*after write, iclass 37, count 0 2006.201.13:49:24.62#ibcon#*before return 0, iclass 37, count 0 2006.201.13:49:24.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:24.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:24.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:49:24.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:49:24.62$vck44/va=6,5 2006.201.13:49:24.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.13:49:24.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.13:49:24.62#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:24.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:24.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:24.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:24.68#ibcon#enter wrdev, iclass 39, count 2 2006.201.13:49:24.68#ibcon#first serial, iclass 39, count 2 2006.201.13:49:24.68#ibcon#enter sib2, iclass 39, count 2 2006.201.13:49:24.68#ibcon#flushed, iclass 39, count 2 2006.201.13:49:24.68#ibcon#about to write, iclass 39, count 2 2006.201.13:49:24.68#ibcon#wrote, iclass 39, count 2 2006.201.13:49:24.68#ibcon#about to read 3, iclass 39, count 2 2006.201.13:49:24.70#ibcon#read 3, iclass 39, count 2 2006.201.13:49:24.70#ibcon#about to read 4, iclass 39, count 2 2006.201.13:49:24.70#ibcon#read 4, iclass 39, count 2 2006.201.13:49:24.70#ibcon#about to read 5, iclass 39, count 2 2006.201.13:49:24.70#ibcon#read 5, iclass 39, count 2 2006.201.13:49:24.70#ibcon#about to read 6, iclass 39, count 2 2006.201.13:49:24.70#ibcon#read 6, iclass 39, count 2 2006.201.13:49:24.70#ibcon#end of sib2, iclass 39, count 2 2006.201.13:49:24.70#ibcon#*mode == 0, iclass 39, count 2 2006.201.13:49:24.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.13:49:24.70#ibcon#[25=AT06-05\r\n] 2006.201.13:49:24.70#ibcon#*before write, iclass 39, count 2 2006.201.13:49:24.70#ibcon#enter sib2, iclass 39, count 2 2006.201.13:49:24.70#ibcon#flushed, iclass 39, count 2 2006.201.13:49:24.70#ibcon#about to write, iclass 39, count 2 2006.201.13:49:24.70#ibcon#wrote, iclass 39, count 2 2006.201.13:49:24.70#ibcon#about to read 3, iclass 39, count 2 2006.201.13:49:24.73#ibcon#read 3, iclass 39, count 2 2006.201.13:49:24.73#ibcon#about to read 4, iclass 39, count 2 2006.201.13:49:24.73#ibcon#read 4, iclass 39, count 2 2006.201.13:49:24.73#ibcon#about to read 5, iclass 39, count 2 2006.201.13:49:24.73#ibcon#read 5, iclass 39, count 2 2006.201.13:49:24.73#ibcon#about to read 6, iclass 39, count 2 2006.201.13:49:24.73#ibcon#read 6, iclass 39, count 2 2006.201.13:49:24.73#ibcon#end of sib2, iclass 39, count 2 2006.201.13:49:24.73#ibcon#*after write, iclass 39, count 2 2006.201.13:49:24.73#ibcon#*before return 0, iclass 39, count 2 2006.201.13:49:24.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:24.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:24.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.13:49:24.73#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:24.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:24.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:24.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:24.85#ibcon#enter wrdev, iclass 39, count 0 2006.201.13:49:24.85#ibcon#first serial, iclass 39, count 0 2006.201.13:49:24.85#ibcon#enter sib2, iclass 39, count 0 2006.201.13:49:24.85#ibcon#flushed, iclass 39, count 0 2006.201.13:49:24.85#ibcon#about to write, iclass 39, count 0 2006.201.13:49:24.85#ibcon#wrote, iclass 39, count 0 2006.201.13:49:24.85#ibcon#about to read 3, iclass 39, count 0 2006.201.13:49:24.87#ibcon#read 3, iclass 39, count 0 2006.201.13:49:24.87#ibcon#about to read 4, iclass 39, count 0 2006.201.13:49:24.87#ibcon#read 4, iclass 39, count 0 2006.201.13:49:24.87#ibcon#about to read 5, iclass 39, count 0 2006.201.13:49:24.87#ibcon#read 5, iclass 39, count 0 2006.201.13:49:24.87#ibcon#about to read 6, iclass 39, count 0 2006.201.13:49:24.87#ibcon#read 6, iclass 39, count 0 2006.201.13:49:24.87#ibcon#end of sib2, iclass 39, count 0 2006.201.13:49:24.87#ibcon#*mode == 0, iclass 39, count 0 2006.201.13:49:24.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.13:49:24.87#ibcon#[25=USB\r\n] 2006.201.13:49:24.87#ibcon#*before write, iclass 39, count 0 2006.201.13:49:24.87#ibcon#enter sib2, iclass 39, count 0 2006.201.13:49:24.87#ibcon#flushed, iclass 39, count 0 2006.201.13:49:24.87#ibcon#about to write, iclass 39, count 0 2006.201.13:49:24.87#ibcon#wrote, iclass 39, count 0 2006.201.13:49:24.87#ibcon#about to read 3, iclass 39, count 0 2006.201.13:49:24.90#ibcon#read 3, iclass 39, count 0 2006.201.13:49:24.90#ibcon#about to read 4, iclass 39, count 0 2006.201.13:49:24.90#ibcon#read 4, iclass 39, count 0 2006.201.13:49:24.90#ibcon#about to read 5, iclass 39, count 0 2006.201.13:49:24.90#ibcon#read 5, iclass 39, count 0 2006.201.13:49:24.90#ibcon#about to read 6, iclass 39, count 0 2006.201.13:49:24.90#ibcon#read 6, iclass 39, count 0 2006.201.13:49:24.90#ibcon#end of sib2, iclass 39, count 0 2006.201.13:49:24.90#ibcon#*after write, iclass 39, count 0 2006.201.13:49:24.90#ibcon#*before return 0, iclass 39, count 0 2006.201.13:49:24.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:24.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:24.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.13:49:24.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.13:49:24.90$vck44/valo=7,864.99 2006.201.13:49:24.90#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.13:49:24.90#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.13:49:24.90#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:24.90#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:24.90#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:24.90#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:24.90#ibcon#enter wrdev, iclass 2, count 0 2006.201.13:49:24.90#ibcon#first serial, iclass 2, count 0 2006.201.13:49:24.90#ibcon#enter sib2, iclass 2, count 0 2006.201.13:49:24.90#ibcon#flushed, iclass 2, count 0 2006.201.13:49:24.90#ibcon#about to write, iclass 2, count 0 2006.201.13:49:24.90#ibcon#wrote, iclass 2, count 0 2006.201.13:49:24.90#ibcon#about to read 3, iclass 2, count 0 2006.201.13:49:24.92#ibcon#read 3, iclass 2, count 0 2006.201.13:49:24.92#ibcon#about to read 4, iclass 2, count 0 2006.201.13:49:24.92#ibcon#read 4, iclass 2, count 0 2006.201.13:49:24.92#ibcon#about to read 5, iclass 2, count 0 2006.201.13:49:24.92#ibcon#read 5, iclass 2, count 0 2006.201.13:49:24.92#ibcon#about to read 6, iclass 2, count 0 2006.201.13:49:24.92#ibcon#read 6, iclass 2, count 0 2006.201.13:49:24.92#ibcon#end of sib2, iclass 2, count 0 2006.201.13:49:24.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.13:49:24.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.13:49:24.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:49:24.92#ibcon#*before write, iclass 2, count 0 2006.201.13:49:24.92#ibcon#enter sib2, iclass 2, count 0 2006.201.13:49:24.92#ibcon#flushed, iclass 2, count 0 2006.201.13:49:24.92#ibcon#about to write, iclass 2, count 0 2006.201.13:49:24.92#ibcon#wrote, iclass 2, count 0 2006.201.13:49:24.92#ibcon#about to read 3, iclass 2, count 0 2006.201.13:49:24.96#ibcon#read 3, iclass 2, count 0 2006.201.13:49:24.96#ibcon#about to read 4, iclass 2, count 0 2006.201.13:49:24.96#ibcon#read 4, iclass 2, count 0 2006.201.13:49:24.96#ibcon#about to read 5, iclass 2, count 0 2006.201.13:49:24.96#ibcon#read 5, iclass 2, count 0 2006.201.13:49:24.96#ibcon#about to read 6, iclass 2, count 0 2006.201.13:49:24.96#ibcon#read 6, iclass 2, count 0 2006.201.13:49:24.96#ibcon#end of sib2, iclass 2, count 0 2006.201.13:49:24.96#ibcon#*after write, iclass 2, count 0 2006.201.13:49:24.96#ibcon#*before return 0, iclass 2, count 0 2006.201.13:49:24.96#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:24.96#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:24.96#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.13:49:24.96#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.13:49:24.96$vck44/va=7,5 2006.201.13:49:24.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.13:49:24.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.13:49:24.96#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:24.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:25.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:25.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:25.02#ibcon#enter wrdev, iclass 5, count 2 2006.201.13:49:25.02#ibcon#first serial, iclass 5, count 2 2006.201.13:49:25.02#ibcon#enter sib2, iclass 5, count 2 2006.201.13:49:25.02#ibcon#flushed, iclass 5, count 2 2006.201.13:49:25.02#ibcon#about to write, iclass 5, count 2 2006.201.13:49:25.02#ibcon#wrote, iclass 5, count 2 2006.201.13:49:25.02#ibcon#about to read 3, iclass 5, count 2 2006.201.13:49:25.04#ibcon#read 3, iclass 5, count 2 2006.201.13:49:25.04#ibcon#about to read 4, iclass 5, count 2 2006.201.13:49:25.04#ibcon#read 4, iclass 5, count 2 2006.201.13:49:25.04#ibcon#about to read 5, iclass 5, count 2 2006.201.13:49:25.04#ibcon#read 5, iclass 5, count 2 2006.201.13:49:25.04#ibcon#about to read 6, iclass 5, count 2 2006.201.13:49:25.04#ibcon#read 6, iclass 5, count 2 2006.201.13:49:25.04#ibcon#end of sib2, iclass 5, count 2 2006.201.13:49:25.04#ibcon#*mode == 0, iclass 5, count 2 2006.201.13:49:25.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.13:49:25.04#ibcon#[25=AT07-05\r\n] 2006.201.13:49:25.04#ibcon#*before write, iclass 5, count 2 2006.201.13:49:25.04#ibcon#enter sib2, iclass 5, count 2 2006.201.13:49:25.04#ibcon#flushed, iclass 5, count 2 2006.201.13:49:25.04#ibcon#about to write, iclass 5, count 2 2006.201.13:49:25.04#ibcon#wrote, iclass 5, count 2 2006.201.13:49:25.04#ibcon#about to read 3, iclass 5, count 2 2006.201.13:49:25.07#ibcon#read 3, iclass 5, count 2 2006.201.13:49:25.07#ibcon#about to read 4, iclass 5, count 2 2006.201.13:49:25.07#ibcon#read 4, iclass 5, count 2 2006.201.13:49:25.07#ibcon#about to read 5, iclass 5, count 2 2006.201.13:49:25.07#ibcon#read 5, iclass 5, count 2 2006.201.13:49:25.07#ibcon#about to read 6, iclass 5, count 2 2006.201.13:49:25.07#ibcon#read 6, iclass 5, count 2 2006.201.13:49:25.07#ibcon#end of sib2, iclass 5, count 2 2006.201.13:49:25.07#ibcon#*after write, iclass 5, count 2 2006.201.13:49:25.07#ibcon#*before return 0, iclass 5, count 2 2006.201.13:49:25.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:25.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:25.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.13:49:25.07#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:25.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:25.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:25.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:25.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:49:25.19#ibcon#first serial, iclass 5, count 0 2006.201.13:49:25.19#ibcon#enter sib2, iclass 5, count 0 2006.201.13:49:25.19#ibcon#flushed, iclass 5, count 0 2006.201.13:49:25.19#ibcon#about to write, iclass 5, count 0 2006.201.13:49:25.19#ibcon#wrote, iclass 5, count 0 2006.201.13:49:25.19#ibcon#about to read 3, iclass 5, count 0 2006.201.13:49:25.21#ibcon#read 3, iclass 5, count 0 2006.201.13:49:25.21#ibcon#about to read 4, iclass 5, count 0 2006.201.13:49:25.21#ibcon#read 4, iclass 5, count 0 2006.201.13:49:25.21#ibcon#about to read 5, iclass 5, count 0 2006.201.13:49:25.21#ibcon#read 5, iclass 5, count 0 2006.201.13:49:25.21#ibcon#about to read 6, iclass 5, count 0 2006.201.13:49:25.21#ibcon#read 6, iclass 5, count 0 2006.201.13:49:25.21#ibcon#end of sib2, iclass 5, count 0 2006.201.13:49:25.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:49:25.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:49:25.21#ibcon#[25=USB\r\n] 2006.201.13:49:25.21#ibcon#*before write, iclass 5, count 0 2006.201.13:49:25.21#ibcon#enter sib2, iclass 5, count 0 2006.201.13:49:25.21#ibcon#flushed, iclass 5, count 0 2006.201.13:49:25.21#ibcon#about to write, iclass 5, count 0 2006.201.13:49:25.21#ibcon#wrote, iclass 5, count 0 2006.201.13:49:25.21#ibcon#about to read 3, iclass 5, count 0 2006.201.13:49:25.24#ibcon#read 3, iclass 5, count 0 2006.201.13:49:25.24#ibcon#about to read 4, iclass 5, count 0 2006.201.13:49:25.24#ibcon#read 4, iclass 5, count 0 2006.201.13:49:25.24#ibcon#about to read 5, iclass 5, count 0 2006.201.13:49:25.24#ibcon#read 5, iclass 5, count 0 2006.201.13:49:25.24#ibcon#about to read 6, iclass 5, count 0 2006.201.13:49:25.24#ibcon#read 6, iclass 5, count 0 2006.201.13:49:25.24#ibcon#end of sib2, iclass 5, count 0 2006.201.13:49:25.24#ibcon#*after write, iclass 5, count 0 2006.201.13:49:25.24#ibcon#*before return 0, iclass 5, count 0 2006.201.13:49:25.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:25.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:25.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:49:25.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:49:25.24$vck44/valo=8,884.99 2006.201.13:49:25.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.13:49:25.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.13:49:25.24#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:25.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:25.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:25.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:25.24#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:49:25.24#ibcon#first serial, iclass 7, count 0 2006.201.13:49:25.24#ibcon#enter sib2, iclass 7, count 0 2006.201.13:49:25.24#ibcon#flushed, iclass 7, count 0 2006.201.13:49:25.24#ibcon#about to write, iclass 7, count 0 2006.201.13:49:25.24#ibcon#wrote, iclass 7, count 0 2006.201.13:49:25.24#ibcon#about to read 3, iclass 7, count 0 2006.201.13:49:25.26#ibcon#read 3, iclass 7, count 0 2006.201.13:49:25.26#ibcon#about to read 4, iclass 7, count 0 2006.201.13:49:25.26#ibcon#read 4, iclass 7, count 0 2006.201.13:49:25.26#ibcon#about to read 5, iclass 7, count 0 2006.201.13:49:25.26#ibcon#read 5, iclass 7, count 0 2006.201.13:49:25.26#ibcon#about to read 6, iclass 7, count 0 2006.201.13:49:25.26#ibcon#read 6, iclass 7, count 0 2006.201.13:49:25.26#ibcon#end of sib2, iclass 7, count 0 2006.201.13:49:25.26#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:49:25.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:49:25.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:49:25.26#ibcon#*before write, iclass 7, count 0 2006.201.13:49:25.26#ibcon#enter sib2, iclass 7, count 0 2006.201.13:49:25.26#ibcon#flushed, iclass 7, count 0 2006.201.13:49:25.26#ibcon#about to write, iclass 7, count 0 2006.201.13:49:25.26#ibcon#wrote, iclass 7, count 0 2006.201.13:49:25.26#ibcon#about to read 3, iclass 7, count 0 2006.201.13:49:25.30#ibcon#read 3, iclass 7, count 0 2006.201.13:49:25.30#ibcon#about to read 4, iclass 7, count 0 2006.201.13:49:25.30#ibcon#read 4, iclass 7, count 0 2006.201.13:49:25.30#ibcon#about to read 5, iclass 7, count 0 2006.201.13:49:25.30#ibcon#read 5, iclass 7, count 0 2006.201.13:49:25.30#ibcon#about to read 6, iclass 7, count 0 2006.201.13:49:25.30#ibcon#read 6, iclass 7, count 0 2006.201.13:49:25.30#ibcon#end of sib2, iclass 7, count 0 2006.201.13:49:25.30#ibcon#*after write, iclass 7, count 0 2006.201.13:49:25.30#ibcon#*before return 0, iclass 7, count 0 2006.201.13:49:25.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:25.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:25.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:49:25.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:49:25.30$vck44/va=8,4 2006.201.13:49:25.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.13:49:25.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.13:49:25.30#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:25.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:49:25.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:49:25.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:49:25.36#ibcon#enter wrdev, iclass 11, count 2 2006.201.13:49:25.36#ibcon#first serial, iclass 11, count 2 2006.201.13:49:25.36#ibcon#enter sib2, iclass 11, count 2 2006.201.13:49:25.36#ibcon#flushed, iclass 11, count 2 2006.201.13:49:25.36#ibcon#about to write, iclass 11, count 2 2006.201.13:49:25.36#ibcon#wrote, iclass 11, count 2 2006.201.13:49:25.36#ibcon#about to read 3, iclass 11, count 2 2006.201.13:49:25.38#ibcon#read 3, iclass 11, count 2 2006.201.13:49:25.38#ibcon#about to read 4, iclass 11, count 2 2006.201.13:49:25.38#ibcon#read 4, iclass 11, count 2 2006.201.13:49:25.38#ibcon#about to read 5, iclass 11, count 2 2006.201.13:49:25.38#ibcon#read 5, iclass 11, count 2 2006.201.13:49:25.38#ibcon#about to read 6, iclass 11, count 2 2006.201.13:49:25.38#ibcon#read 6, iclass 11, count 2 2006.201.13:49:25.38#ibcon#end of sib2, iclass 11, count 2 2006.201.13:49:25.38#ibcon#*mode == 0, iclass 11, count 2 2006.201.13:49:25.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.13:49:25.38#ibcon#[25=AT08-04\r\n] 2006.201.13:49:25.38#ibcon#*before write, iclass 11, count 2 2006.201.13:49:25.38#ibcon#enter sib2, iclass 11, count 2 2006.201.13:49:25.38#ibcon#flushed, iclass 11, count 2 2006.201.13:49:25.38#ibcon#about to write, iclass 11, count 2 2006.201.13:49:25.38#ibcon#wrote, iclass 11, count 2 2006.201.13:49:25.38#ibcon#about to read 3, iclass 11, count 2 2006.201.13:49:25.42#ibcon#read 3, iclass 11, count 2 2006.201.13:49:25.42#ibcon#about to read 4, iclass 11, count 2 2006.201.13:49:25.42#ibcon#read 4, iclass 11, count 2 2006.201.13:49:25.42#ibcon#about to read 5, iclass 11, count 2 2006.201.13:49:25.42#ibcon#read 5, iclass 11, count 2 2006.201.13:49:25.42#ibcon#about to read 6, iclass 11, count 2 2006.201.13:49:25.42#ibcon#read 6, iclass 11, count 2 2006.201.13:49:25.42#ibcon#end of sib2, iclass 11, count 2 2006.201.13:49:25.42#ibcon#*after write, iclass 11, count 2 2006.201.13:49:25.42#ibcon#*before return 0, iclass 11, count 2 2006.201.13:49:25.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:49:25.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.13:49:25.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.13:49:25.42#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:25.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:49:25.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:49:25.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:49:25.54#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:49:25.54#ibcon#first serial, iclass 11, count 0 2006.201.13:49:25.54#ibcon#enter sib2, iclass 11, count 0 2006.201.13:49:25.54#ibcon#flushed, iclass 11, count 0 2006.201.13:49:25.54#ibcon#about to write, iclass 11, count 0 2006.201.13:49:25.54#ibcon#wrote, iclass 11, count 0 2006.201.13:49:25.54#ibcon#about to read 3, iclass 11, count 0 2006.201.13:49:25.56#ibcon#read 3, iclass 11, count 0 2006.201.13:49:25.56#ibcon#about to read 4, iclass 11, count 0 2006.201.13:49:25.56#ibcon#read 4, iclass 11, count 0 2006.201.13:49:25.56#ibcon#about to read 5, iclass 11, count 0 2006.201.13:49:25.56#ibcon#read 5, iclass 11, count 0 2006.201.13:49:25.56#ibcon#about to read 6, iclass 11, count 0 2006.201.13:49:25.56#ibcon#read 6, iclass 11, count 0 2006.201.13:49:25.56#ibcon#end of sib2, iclass 11, count 0 2006.201.13:49:25.56#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:49:25.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:49:25.56#ibcon#[25=USB\r\n] 2006.201.13:49:25.56#ibcon#*before write, iclass 11, count 0 2006.201.13:49:25.56#ibcon#enter sib2, iclass 11, count 0 2006.201.13:49:25.56#ibcon#flushed, iclass 11, count 0 2006.201.13:49:25.56#ibcon#about to write, iclass 11, count 0 2006.201.13:49:25.56#ibcon#wrote, iclass 11, count 0 2006.201.13:49:25.56#ibcon#about to read 3, iclass 11, count 0 2006.201.13:49:25.59#ibcon#read 3, iclass 11, count 0 2006.201.13:49:25.59#ibcon#about to read 4, iclass 11, count 0 2006.201.13:49:25.59#ibcon#read 4, iclass 11, count 0 2006.201.13:49:25.59#ibcon#about to read 5, iclass 11, count 0 2006.201.13:49:25.59#ibcon#read 5, iclass 11, count 0 2006.201.13:49:25.59#ibcon#about to read 6, iclass 11, count 0 2006.201.13:49:25.59#ibcon#read 6, iclass 11, count 0 2006.201.13:49:25.59#ibcon#end of sib2, iclass 11, count 0 2006.201.13:49:25.59#ibcon#*after write, iclass 11, count 0 2006.201.13:49:25.59#ibcon#*before return 0, iclass 11, count 0 2006.201.13:49:25.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:49:25.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.13:49:25.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:49:25.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:49:25.59$vck44/vblo=1,629.99 2006.201.13:49:25.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.13:49:25.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.13:49:25.59#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:25.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:49:25.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:49:25.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:49:25.59#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:49:25.59#ibcon#first serial, iclass 13, count 0 2006.201.13:49:25.59#ibcon#enter sib2, iclass 13, count 0 2006.201.13:49:25.59#ibcon#flushed, iclass 13, count 0 2006.201.13:49:25.59#ibcon#about to write, iclass 13, count 0 2006.201.13:49:25.59#ibcon#wrote, iclass 13, count 0 2006.201.13:49:25.59#ibcon#about to read 3, iclass 13, count 0 2006.201.13:49:25.61#ibcon#read 3, iclass 13, count 0 2006.201.13:49:25.61#ibcon#about to read 4, iclass 13, count 0 2006.201.13:49:25.61#ibcon#read 4, iclass 13, count 0 2006.201.13:49:25.61#ibcon#about to read 5, iclass 13, count 0 2006.201.13:49:25.61#ibcon#read 5, iclass 13, count 0 2006.201.13:49:25.61#ibcon#about to read 6, iclass 13, count 0 2006.201.13:49:25.61#ibcon#read 6, iclass 13, count 0 2006.201.13:49:25.61#ibcon#end of sib2, iclass 13, count 0 2006.201.13:49:25.61#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:49:25.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:49:25.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:49:25.61#ibcon#*before write, iclass 13, count 0 2006.201.13:49:25.61#ibcon#enter sib2, iclass 13, count 0 2006.201.13:49:25.61#ibcon#flushed, iclass 13, count 0 2006.201.13:49:25.61#ibcon#about to write, iclass 13, count 0 2006.201.13:49:25.61#ibcon#wrote, iclass 13, count 0 2006.201.13:49:25.61#ibcon#about to read 3, iclass 13, count 0 2006.201.13:49:25.65#ibcon#read 3, iclass 13, count 0 2006.201.13:49:25.65#ibcon#about to read 4, iclass 13, count 0 2006.201.13:49:25.65#ibcon#read 4, iclass 13, count 0 2006.201.13:49:25.65#ibcon#about to read 5, iclass 13, count 0 2006.201.13:49:25.65#ibcon#read 5, iclass 13, count 0 2006.201.13:49:25.65#ibcon#about to read 6, iclass 13, count 0 2006.201.13:49:25.65#ibcon#read 6, iclass 13, count 0 2006.201.13:49:25.65#ibcon#end of sib2, iclass 13, count 0 2006.201.13:49:25.65#ibcon#*after write, iclass 13, count 0 2006.201.13:49:25.65#ibcon#*before return 0, iclass 13, count 0 2006.201.13:49:25.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:49:25.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.13:49:25.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:49:25.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:49:25.65$vck44/vb=1,4 2006.201.13:49:25.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.13:49:25.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.13:49:25.65#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:25.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:49:25.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:49:25.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:49:25.65#ibcon#enter wrdev, iclass 15, count 2 2006.201.13:49:25.65#ibcon#first serial, iclass 15, count 2 2006.201.13:49:25.65#ibcon#enter sib2, iclass 15, count 2 2006.201.13:49:25.65#ibcon#flushed, iclass 15, count 2 2006.201.13:49:25.65#ibcon#about to write, iclass 15, count 2 2006.201.13:49:25.65#ibcon#wrote, iclass 15, count 2 2006.201.13:49:25.65#ibcon#about to read 3, iclass 15, count 2 2006.201.13:49:25.67#ibcon#read 3, iclass 15, count 2 2006.201.13:49:25.67#ibcon#about to read 4, iclass 15, count 2 2006.201.13:49:25.67#ibcon#read 4, iclass 15, count 2 2006.201.13:49:25.67#ibcon#about to read 5, iclass 15, count 2 2006.201.13:49:25.67#ibcon#read 5, iclass 15, count 2 2006.201.13:49:25.67#ibcon#about to read 6, iclass 15, count 2 2006.201.13:49:25.67#ibcon#read 6, iclass 15, count 2 2006.201.13:49:25.67#ibcon#end of sib2, iclass 15, count 2 2006.201.13:49:25.67#ibcon#*mode == 0, iclass 15, count 2 2006.201.13:49:25.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.13:49:25.67#ibcon#[27=AT01-04\r\n] 2006.201.13:49:25.67#ibcon#*before write, iclass 15, count 2 2006.201.13:49:25.67#ibcon#enter sib2, iclass 15, count 2 2006.201.13:49:25.67#ibcon#flushed, iclass 15, count 2 2006.201.13:49:25.67#ibcon#about to write, iclass 15, count 2 2006.201.13:49:25.67#ibcon#wrote, iclass 15, count 2 2006.201.13:49:25.67#ibcon#about to read 3, iclass 15, count 2 2006.201.13:49:25.70#ibcon#read 3, iclass 15, count 2 2006.201.13:49:25.70#ibcon#about to read 4, iclass 15, count 2 2006.201.13:49:25.70#ibcon#read 4, iclass 15, count 2 2006.201.13:49:25.70#ibcon#about to read 5, iclass 15, count 2 2006.201.13:49:25.70#ibcon#read 5, iclass 15, count 2 2006.201.13:49:25.70#ibcon#about to read 6, iclass 15, count 2 2006.201.13:49:25.70#ibcon#read 6, iclass 15, count 2 2006.201.13:49:25.70#ibcon#end of sib2, iclass 15, count 2 2006.201.13:49:25.70#ibcon#*after write, iclass 15, count 2 2006.201.13:49:25.70#ibcon#*before return 0, iclass 15, count 2 2006.201.13:49:25.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:49:25.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.13:49:25.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.13:49:25.70#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:25.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:49:25.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:49:25.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:49:25.82#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:49:25.82#ibcon#first serial, iclass 15, count 0 2006.201.13:49:25.82#ibcon#enter sib2, iclass 15, count 0 2006.201.13:49:25.82#ibcon#flushed, iclass 15, count 0 2006.201.13:49:25.82#ibcon#about to write, iclass 15, count 0 2006.201.13:49:25.82#ibcon#wrote, iclass 15, count 0 2006.201.13:49:25.82#ibcon#about to read 3, iclass 15, count 0 2006.201.13:49:25.84#ibcon#read 3, iclass 15, count 0 2006.201.13:49:25.84#ibcon#about to read 4, iclass 15, count 0 2006.201.13:49:25.84#ibcon#read 4, iclass 15, count 0 2006.201.13:49:25.84#ibcon#about to read 5, iclass 15, count 0 2006.201.13:49:25.84#ibcon#read 5, iclass 15, count 0 2006.201.13:49:25.84#ibcon#about to read 6, iclass 15, count 0 2006.201.13:49:25.84#ibcon#read 6, iclass 15, count 0 2006.201.13:49:25.84#ibcon#end of sib2, iclass 15, count 0 2006.201.13:49:25.84#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:49:25.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:49:25.84#ibcon#[27=USB\r\n] 2006.201.13:49:25.84#ibcon#*before write, iclass 15, count 0 2006.201.13:49:25.84#ibcon#enter sib2, iclass 15, count 0 2006.201.13:49:25.84#ibcon#flushed, iclass 15, count 0 2006.201.13:49:25.84#ibcon#about to write, iclass 15, count 0 2006.201.13:49:25.84#ibcon#wrote, iclass 15, count 0 2006.201.13:49:25.84#ibcon#about to read 3, iclass 15, count 0 2006.201.13:49:25.87#ibcon#read 3, iclass 15, count 0 2006.201.13:49:25.87#ibcon#about to read 4, iclass 15, count 0 2006.201.13:49:25.87#ibcon#read 4, iclass 15, count 0 2006.201.13:49:25.87#ibcon#about to read 5, iclass 15, count 0 2006.201.13:49:25.87#ibcon#read 5, iclass 15, count 0 2006.201.13:49:25.87#ibcon#about to read 6, iclass 15, count 0 2006.201.13:49:25.87#ibcon#read 6, iclass 15, count 0 2006.201.13:49:25.87#ibcon#end of sib2, iclass 15, count 0 2006.201.13:49:25.87#ibcon#*after write, iclass 15, count 0 2006.201.13:49:25.87#ibcon#*before return 0, iclass 15, count 0 2006.201.13:49:25.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:49:25.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.13:49:25.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:49:25.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:49:25.87$vck44/vblo=2,634.99 2006.201.13:49:25.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.13:49:25.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.13:49:25.87#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:25.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:25.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:25.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:25.87#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:49:25.87#ibcon#first serial, iclass 17, count 0 2006.201.13:49:25.87#ibcon#enter sib2, iclass 17, count 0 2006.201.13:49:25.87#ibcon#flushed, iclass 17, count 0 2006.201.13:49:25.87#ibcon#about to write, iclass 17, count 0 2006.201.13:49:25.87#ibcon#wrote, iclass 17, count 0 2006.201.13:49:25.87#ibcon#about to read 3, iclass 17, count 0 2006.201.13:49:25.89#ibcon#read 3, iclass 17, count 0 2006.201.13:49:25.89#ibcon#about to read 4, iclass 17, count 0 2006.201.13:49:25.89#ibcon#read 4, iclass 17, count 0 2006.201.13:49:25.89#ibcon#about to read 5, iclass 17, count 0 2006.201.13:49:25.89#ibcon#read 5, iclass 17, count 0 2006.201.13:49:25.89#ibcon#about to read 6, iclass 17, count 0 2006.201.13:49:25.89#ibcon#read 6, iclass 17, count 0 2006.201.13:49:25.89#ibcon#end of sib2, iclass 17, count 0 2006.201.13:49:25.89#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:49:25.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:49:25.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:49:25.89#ibcon#*before write, iclass 17, count 0 2006.201.13:49:25.89#ibcon#enter sib2, iclass 17, count 0 2006.201.13:49:25.89#ibcon#flushed, iclass 17, count 0 2006.201.13:49:25.89#ibcon#about to write, iclass 17, count 0 2006.201.13:49:25.89#ibcon#wrote, iclass 17, count 0 2006.201.13:49:25.89#ibcon#about to read 3, iclass 17, count 0 2006.201.13:49:25.93#ibcon#read 3, iclass 17, count 0 2006.201.13:49:25.93#ibcon#about to read 4, iclass 17, count 0 2006.201.13:49:25.93#ibcon#read 4, iclass 17, count 0 2006.201.13:49:25.93#ibcon#about to read 5, iclass 17, count 0 2006.201.13:49:25.93#ibcon#read 5, iclass 17, count 0 2006.201.13:49:25.93#ibcon#about to read 6, iclass 17, count 0 2006.201.13:49:25.93#ibcon#read 6, iclass 17, count 0 2006.201.13:49:25.93#ibcon#end of sib2, iclass 17, count 0 2006.201.13:49:25.93#ibcon#*after write, iclass 17, count 0 2006.201.13:49:25.93#ibcon#*before return 0, iclass 17, count 0 2006.201.13:49:25.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:25.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.13:49:25.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:49:25.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:49:25.93$vck44/vb=2,5 2006.201.13:49:25.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.13:49:25.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.13:49:25.93#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:25.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:25.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:25.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:25.99#ibcon#enter wrdev, iclass 19, count 2 2006.201.13:49:25.99#ibcon#first serial, iclass 19, count 2 2006.201.13:49:25.99#ibcon#enter sib2, iclass 19, count 2 2006.201.13:49:25.99#ibcon#flushed, iclass 19, count 2 2006.201.13:49:25.99#ibcon#about to write, iclass 19, count 2 2006.201.13:49:25.99#ibcon#wrote, iclass 19, count 2 2006.201.13:49:25.99#ibcon#about to read 3, iclass 19, count 2 2006.201.13:49:26.01#ibcon#read 3, iclass 19, count 2 2006.201.13:49:26.01#ibcon#about to read 4, iclass 19, count 2 2006.201.13:49:26.01#ibcon#read 4, iclass 19, count 2 2006.201.13:49:26.01#ibcon#about to read 5, iclass 19, count 2 2006.201.13:49:26.01#ibcon#read 5, iclass 19, count 2 2006.201.13:49:26.01#ibcon#about to read 6, iclass 19, count 2 2006.201.13:49:26.01#ibcon#read 6, iclass 19, count 2 2006.201.13:49:26.01#ibcon#end of sib2, iclass 19, count 2 2006.201.13:49:26.01#ibcon#*mode == 0, iclass 19, count 2 2006.201.13:49:26.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.13:49:26.01#ibcon#[27=AT02-05\r\n] 2006.201.13:49:26.01#ibcon#*before write, iclass 19, count 2 2006.201.13:49:26.01#ibcon#enter sib2, iclass 19, count 2 2006.201.13:49:26.01#ibcon#flushed, iclass 19, count 2 2006.201.13:49:26.01#ibcon#about to write, iclass 19, count 2 2006.201.13:49:26.01#ibcon#wrote, iclass 19, count 2 2006.201.13:49:26.01#ibcon#about to read 3, iclass 19, count 2 2006.201.13:49:26.04#ibcon#read 3, iclass 19, count 2 2006.201.13:49:26.04#ibcon#about to read 4, iclass 19, count 2 2006.201.13:49:26.04#ibcon#read 4, iclass 19, count 2 2006.201.13:49:26.04#ibcon#about to read 5, iclass 19, count 2 2006.201.13:49:26.04#ibcon#read 5, iclass 19, count 2 2006.201.13:49:26.04#ibcon#about to read 6, iclass 19, count 2 2006.201.13:49:26.04#ibcon#read 6, iclass 19, count 2 2006.201.13:49:26.04#ibcon#end of sib2, iclass 19, count 2 2006.201.13:49:26.04#ibcon#*after write, iclass 19, count 2 2006.201.13:49:26.04#ibcon#*before return 0, iclass 19, count 2 2006.201.13:49:26.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:26.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.13:49:26.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.13:49:26.04#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:26.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:26.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:26.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:26.16#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:49:26.16#ibcon#first serial, iclass 19, count 0 2006.201.13:49:26.16#ibcon#enter sib2, iclass 19, count 0 2006.201.13:49:26.16#ibcon#flushed, iclass 19, count 0 2006.201.13:49:26.16#ibcon#about to write, iclass 19, count 0 2006.201.13:49:26.16#ibcon#wrote, iclass 19, count 0 2006.201.13:49:26.16#ibcon#about to read 3, iclass 19, count 0 2006.201.13:49:26.18#ibcon#read 3, iclass 19, count 0 2006.201.13:49:26.18#ibcon#about to read 4, iclass 19, count 0 2006.201.13:49:26.18#ibcon#read 4, iclass 19, count 0 2006.201.13:49:26.18#ibcon#about to read 5, iclass 19, count 0 2006.201.13:49:26.18#ibcon#read 5, iclass 19, count 0 2006.201.13:49:26.18#ibcon#about to read 6, iclass 19, count 0 2006.201.13:49:26.18#ibcon#read 6, iclass 19, count 0 2006.201.13:49:26.18#ibcon#end of sib2, iclass 19, count 0 2006.201.13:49:26.18#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:49:26.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:49:26.18#ibcon#[27=USB\r\n] 2006.201.13:49:26.18#ibcon#*before write, iclass 19, count 0 2006.201.13:49:26.18#ibcon#enter sib2, iclass 19, count 0 2006.201.13:49:26.18#ibcon#flushed, iclass 19, count 0 2006.201.13:49:26.18#ibcon#about to write, iclass 19, count 0 2006.201.13:49:26.18#ibcon#wrote, iclass 19, count 0 2006.201.13:49:26.18#ibcon#about to read 3, iclass 19, count 0 2006.201.13:49:26.21#ibcon#read 3, iclass 19, count 0 2006.201.13:49:26.21#ibcon#about to read 4, iclass 19, count 0 2006.201.13:49:26.21#ibcon#read 4, iclass 19, count 0 2006.201.13:49:26.21#ibcon#about to read 5, iclass 19, count 0 2006.201.13:49:26.21#ibcon#read 5, iclass 19, count 0 2006.201.13:49:26.21#ibcon#about to read 6, iclass 19, count 0 2006.201.13:49:26.21#ibcon#read 6, iclass 19, count 0 2006.201.13:49:26.21#ibcon#end of sib2, iclass 19, count 0 2006.201.13:49:26.21#ibcon#*after write, iclass 19, count 0 2006.201.13:49:26.21#ibcon#*before return 0, iclass 19, count 0 2006.201.13:49:26.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:26.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.13:49:26.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:49:26.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:49:26.21$vck44/vblo=3,649.99 2006.201.13:49:26.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.13:49:26.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.13:49:26.21#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:26.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:26.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:26.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:26.21#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:49:26.21#ibcon#first serial, iclass 21, count 0 2006.201.13:49:26.21#ibcon#enter sib2, iclass 21, count 0 2006.201.13:49:26.21#ibcon#flushed, iclass 21, count 0 2006.201.13:49:26.21#ibcon#about to write, iclass 21, count 0 2006.201.13:49:26.21#ibcon#wrote, iclass 21, count 0 2006.201.13:49:26.21#ibcon#about to read 3, iclass 21, count 0 2006.201.13:49:26.23#ibcon#read 3, iclass 21, count 0 2006.201.13:49:26.23#ibcon#about to read 4, iclass 21, count 0 2006.201.13:49:26.23#ibcon#read 4, iclass 21, count 0 2006.201.13:49:26.23#ibcon#about to read 5, iclass 21, count 0 2006.201.13:49:26.23#ibcon#read 5, iclass 21, count 0 2006.201.13:49:26.23#ibcon#about to read 6, iclass 21, count 0 2006.201.13:49:26.23#ibcon#read 6, iclass 21, count 0 2006.201.13:49:26.23#ibcon#end of sib2, iclass 21, count 0 2006.201.13:49:26.23#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:49:26.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:49:26.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:49:26.23#ibcon#*before write, iclass 21, count 0 2006.201.13:49:26.23#ibcon#enter sib2, iclass 21, count 0 2006.201.13:49:26.23#ibcon#flushed, iclass 21, count 0 2006.201.13:49:26.23#ibcon#about to write, iclass 21, count 0 2006.201.13:49:26.23#ibcon#wrote, iclass 21, count 0 2006.201.13:49:26.23#ibcon#about to read 3, iclass 21, count 0 2006.201.13:49:26.28#ibcon#read 3, iclass 21, count 0 2006.201.13:49:26.28#ibcon#about to read 4, iclass 21, count 0 2006.201.13:49:26.28#ibcon#read 4, iclass 21, count 0 2006.201.13:49:26.28#ibcon#about to read 5, iclass 21, count 0 2006.201.13:49:26.28#ibcon#read 5, iclass 21, count 0 2006.201.13:49:26.28#ibcon#about to read 6, iclass 21, count 0 2006.201.13:49:26.28#ibcon#read 6, iclass 21, count 0 2006.201.13:49:26.28#ibcon#end of sib2, iclass 21, count 0 2006.201.13:49:26.28#ibcon#*after write, iclass 21, count 0 2006.201.13:49:26.28#ibcon#*before return 0, iclass 21, count 0 2006.201.13:49:26.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:26.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.13:49:26.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:49:26.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:49:26.28$vck44/vb=3,4 2006.201.13:49:26.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.13:49:26.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.13:49:26.28#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:26.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:26.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:26.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:26.33#ibcon#enter wrdev, iclass 23, count 2 2006.201.13:49:26.33#ibcon#first serial, iclass 23, count 2 2006.201.13:49:26.33#ibcon#enter sib2, iclass 23, count 2 2006.201.13:49:26.33#ibcon#flushed, iclass 23, count 2 2006.201.13:49:26.33#ibcon#about to write, iclass 23, count 2 2006.201.13:49:26.33#ibcon#wrote, iclass 23, count 2 2006.201.13:49:26.33#ibcon#about to read 3, iclass 23, count 2 2006.201.13:49:26.35#ibcon#read 3, iclass 23, count 2 2006.201.13:49:26.35#ibcon#about to read 4, iclass 23, count 2 2006.201.13:49:26.35#ibcon#read 4, iclass 23, count 2 2006.201.13:49:26.35#ibcon#about to read 5, iclass 23, count 2 2006.201.13:49:26.35#ibcon#read 5, iclass 23, count 2 2006.201.13:49:26.35#ibcon#about to read 6, iclass 23, count 2 2006.201.13:49:26.35#ibcon#read 6, iclass 23, count 2 2006.201.13:49:26.35#ibcon#end of sib2, iclass 23, count 2 2006.201.13:49:26.35#ibcon#*mode == 0, iclass 23, count 2 2006.201.13:49:26.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.13:49:26.35#ibcon#[27=AT03-04\r\n] 2006.201.13:49:26.35#ibcon#*before write, iclass 23, count 2 2006.201.13:49:26.35#ibcon#enter sib2, iclass 23, count 2 2006.201.13:49:26.35#ibcon#flushed, iclass 23, count 2 2006.201.13:49:26.35#ibcon#about to write, iclass 23, count 2 2006.201.13:49:26.35#ibcon#wrote, iclass 23, count 2 2006.201.13:49:26.35#ibcon#about to read 3, iclass 23, count 2 2006.201.13:49:26.38#ibcon#read 3, iclass 23, count 2 2006.201.13:49:26.38#ibcon#about to read 4, iclass 23, count 2 2006.201.13:49:26.38#ibcon#read 4, iclass 23, count 2 2006.201.13:49:26.38#ibcon#about to read 5, iclass 23, count 2 2006.201.13:49:26.38#ibcon#read 5, iclass 23, count 2 2006.201.13:49:26.38#ibcon#about to read 6, iclass 23, count 2 2006.201.13:49:26.38#ibcon#read 6, iclass 23, count 2 2006.201.13:49:26.38#ibcon#end of sib2, iclass 23, count 2 2006.201.13:49:26.38#ibcon#*after write, iclass 23, count 2 2006.201.13:49:26.38#ibcon#*before return 0, iclass 23, count 2 2006.201.13:49:26.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:26.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.13:49:26.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.13:49:26.38#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:26.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:26.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:26.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:26.50#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:49:26.50#ibcon#first serial, iclass 23, count 0 2006.201.13:49:26.50#ibcon#enter sib2, iclass 23, count 0 2006.201.13:49:26.50#ibcon#flushed, iclass 23, count 0 2006.201.13:49:26.50#ibcon#about to write, iclass 23, count 0 2006.201.13:49:26.50#ibcon#wrote, iclass 23, count 0 2006.201.13:49:26.50#ibcon#about to read 3, iclass 23, count 0 2006.201.13:49:26.52#ibcon#read 3, iclass 23, count 0 2006.201.13:49:26.52#ibcon#about to read 4, iclass 23, count 0 2006.201.13:49:26.52#ibcon#read 4, iclass 23, count 0 2006.201.13:49:26.52#ibcon#about to read 5, iclass 23, count 0 2006.201.13:49:26.52#ibcon#read 5, iclass 23, count 0 2006.201.13:49:26.52#ibcon#about to read 6, iclass 23, count 0 2006.201.13:49:26.52#ibcon#read 6, iclass 23, count 0 2006.201.13:49:26.52#ibcon#end of sib2, iclass 23, count 0 2006.201.13:49:26.52#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:49:26.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:49:26.52#ibcon#[27=USB\r\n] 2006.201.13:49:26.52#ibcon#*before write, iclass 23, count 0 2006.201.13:49:26.52#ibcon#enter sib2, iclass 23, count 0 2006.201.13:49:26.52#ibcon#flushed, iclass 23, count 0 2006.201.13:49:26.52#ibcon#about to write, iclass 23, count 0 2006.201.13:49:26.52#ibcon#wrote, iclass 23, count 0 2006.201.13:49:26.52#ibcon#about to read 3, iclass 23, count 0 2006.201.13:49:26.55#ibcon#read 3, iclass 23, count 0 2006.201.13:49:26.55#ibcon#about to read 4, iclass 23, count 0 2006.201.13:49:26.55#ibcon#read 4, iclass 23, count 0 2006.201.13:49:26.55#ibcon#about to read 5, iclass 23, count 0 2006.201.13:49:26.55#ibcon#read 5, iclass 23, count 0 2006.201.13:49:26.55#ibcon#about to read 6, iclass 23, count 0 2006.201.13:49:26.55#ibcon#read 6, iclass 23, count 0 2006.201.13:49:26.55#ibcon#end of sib2, iclass 23, count 0 2006.201.13:49:26.55#ibcon#*after write, iclass 23, count 0 2006.201.13:49:26.55#ibcon#*before return 0, iclass 23, count 0 2006.201.13:49:26.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:26.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.13:49:26.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:49:26.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:49:26.55$vck44/vblo=4,679.99 2006.201.13:49:26.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.13:49:26.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.13:49:26.55#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:26.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:26.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:26.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:26.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:49:26.55#ibcon#first serial, iclass 25, count 0 2006.201.13:49:26.55#ibcon#enter sib2, iclass 25, count 0 2006.201.13:49:26.55#ibcon#flushed, iclass 25, count 0 2006.201.13:49:26.55#ibcon#about to write, iclass 25, count 0 2006.201.13:49:26.55#ibcon#wrote, iclass 25, count 0 2006.201.13:49:26.55#ibcon#about to read 3, iclass 25, count 0 2006.201.13:49:26.57#ibcon#read 3, iclass 25, count 0 2006.201.13:49:26.57#ibcon#about to read 4, iclass 25, count 0 2006.201.13:49:26.57#ibcon#read 4, iclass 25, count 0 2006.201.13:49:26.57#ibcon#about to read 5, iclass 25, count 0 2006.201.13:49:26.57#ibcon#read 5, iclass 25, count 0 2006.201.13:49:26.57#ibcon#about to read 6, iclass 25, count 0 2006.201.13:49:26.57#ibcon#read 6, iclass 25, count 0 2006.201.13:49:26.57#ibcon#end of sib2, iclass 25, count 0 2006.201.13:49:26.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:49:26.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:49:26.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:49:26.57#ibcon#*before write, iclass 25, count 0 2006.201.13:49:26.57#ibcon#enter sib2, iclass 25, count 0 2006.201.13:49:26.57#ibcon#flushed, iclass 25, count 0 2006.201.13:49:26.57#ibcon#about to write, iclass 25, count 0 2006.201.13:49:26.57#ibcon#wrote, iclass 25, count 0 2006.201.13:49:26.57#ibcon#about to read 3, iclass 25, count 0 2006.201.13:49:26.61#ibcon#read 3, iclass 25, count 0 2006.201.13:49:26.61#ibcon#about to read 4, iclass 25, count 0 2006.201.13:49:26.61#ibcon#read 4, iclass 25, count 0 2006.201.13:49:26.61#ibcon#about to read 5, iclass 25, count 0 2006.201.13:49:26.61#ibcon#read 5, iclass 25, count 0 2006.201.13:49:26.61#ibcon#about to read 6, iclass 25, count 0 2006.201.13:49:26.61#ibcon#read 6, iclass 25, count 0 2006.201.13:49:26.61#ibcon#end of sib2, iclass 25, count 0 2006.201.13:49:26.61#ibcon#*after write, iclass 25, count 0 2006.201.13:49:26.61#ibcon#*before return 0, iclass 25, count 0 2006.201.13:49:26.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:26.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.13:49:26.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:49:26.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:49:26.61$vck44/vb=4,5 2006.201.13:49:26.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.13:49:26.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.13:49:26.61#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:26.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:26.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:26.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:26.67#ibcon#enter wrdev, iclass 27, count 2 2006.201.13:49:26.67#ibcon#first serial, iclass 27, count 2 2006.201.13:49:26.67#ibcon#enter sib2, iclass 27, count 2 2006.201.13:49:26.67#ibcon#flushed, iclass 27, count 2 2006.201.13:49:26.67#ibcon#about to write, iclass 27, count 2 2006.201.13:49:26.67#ibcon#wrote, iclass 27, count 2 2006.201.13:49:26.67#ibcon#about to read 3, iclass 27, count 2 2006.201.13:49:26.69#ibcon#read 3, iclass 27, count 2 2006.201.13:49:26.69#ibcon#about to read 4, iclass 27, count 2 2006.201.13:49:26.69#ibcon#read 4, iclass 27, count 2 2006.201.13:49:26.69#ibcon#about to read 5, iclass 27, count 2 2006.201.13:49:26.69#ibcon#read 5, iclass 27, count 2 2006.201.13:49:26.69#ibcon#about to read 6, iclass 27, count 2 2006.201.13:49:26.69#ibcon#read 6, iclass 27, count 2 2006.201.13:49:26.69#ibcon#end of sib2, iclass 27, count 2 2006.201.13:49:26.69#ibcon#*mode == 0, iclass 27, count 2 2006.201.13:49:26.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.13:49:26.69#ibcon#[27=AT04-05\r\n] 2006.201.13:49:26.69#ibcon#*before write, iclass 27, count 2 2006.201.13:49:26.69#ibcon#enter sib2, iclass 27, count 2 2006.201.13:49:26.69#ibcon#flushed, iclass 27, count 2 2006.201.13:49:26.69#ibcon#about to write, iclass 27, count 2 2006.201.13:49:26.69#ibcon#wrote, iclass 27, count 2 2006.201.13:49:26.69#ibcon#about to read 3, iclass 27, count 2 2006.201.13:49:26.72#ibcon#read 3, iclass 27, count 2 2006.201.13:49:26.72#ibcon#about to read 4, iclass 27, count 2 2006.201.13:49:26.72#ibcon#read 4, iclass 27, count 2 2006.201.13:49:26.72#ibcon#about to read 5, iclass 27, count 2 2006.201.13:49:26.72#ibcon#read 5, iclass 27, count 2 2006.201.13:49:26.72#ibcon#about to read 6, iclass 27, count 2 2006.201.13:49:26.72#ibcon#read 6, iclass 27, count 2 2006.201.13:49:26.72#ibcon#end of sib2, iclass 27, count 2 2006.201.13:49:26.72#ibcon#*after write, iclass 27, count 2 2006.201.13:49:26.72#ibcon#*before return 0, iclass 27, count 2 2006.201.13:49:26.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:26.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.13:49:26.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.13:49:26.72#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:26.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:26.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:26.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:26.84#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:49:26.84#ibcon#first serial, iclass 27, count 0 2006.201.13:49:26.84#ibcon#enter sib2, iclass 27, count 0 2006.201.13:49:26.84#ibcon#flushed, iclass 27, count 0 2006.201.13:49:26.84#ibcon#about to write, iclass 27, count 0 2006.201.13:49:26.84#ibcon#wrote, iclass 27, count 0 2006.201.13:49:26.84#ibcon#about to read 3, iclass 27, count 0 2006.201.13:49:26.86#ibcon#read 3, iclass 27, count 0 2006.201.13:49:26.86#ibcon#about to read 4, iclass 27, count 0 2006.201.13:49:26.86#ibcon#read 4, iclass 27, count 0 2006.201.13:49:26.86#ibcon#about to read 5, iclass 27, count 0 2006.201.13:49:26.86#ibcon#read 5, iclass 27, count 0 2006.201.13:49:26.86#ibcon#about to read 6, iclass 27, count 0 2006.201.13:49:26.86#ibcon#read 6, iclass 27, count 0 2006.201.13:49:26.86#ibcon#end of sib2, iclass 27, count 0 2006.201.13:49:26.86#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:49:26.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:49:26.86#ibcon#[27=USB\r\n] 2006.201.13:49:26.86#ibcon#*before write, iclass 27, count 0 2006.201.13:49:26.86#ibcon#enter sib2, iclass 27, count 0 2006.201.13:49:26.86#ibcon#flushed, iclass 27, count 0 2006.201.13:49:26.86#ibcon#about to write, iclass 27, count 0 2006.201.13:49:26.86#ibcon#wrote, iclass 27, count 0 2006.201.13:49:26.86#ibcon#about to read 3, iclass 27, count 0 2006.201.13:49:26.89#ibcon#read 3, iclass 27, count 0 2006.201.13:49:26.89#ibcon#about to read 4, iclass 27, count 0 2006.201.13:49:26.89#ibcon#read 4, iclass 27, count 0 2006.201.13:49:26.89#ibcon#about to read 5, iclass 27, count 0 2006.201.13:49:26.89#ibcon#read 5, iclass 27, count 0 2006.201.13:49:26.89#ibcon#about to read 6, iclass 27, count 0 2006.201.13:49:26.89#ibcon#read 6, iclass 27, count 0 2006.201.13:49:26.89#ibcon#end of sib2, iclass 27, count 0 2006.201.13:49:26.89#ibcon#*after write, iclass 27, count 0 2006.201.13:49:26.89#ibcon#*before return 0, iclass 27, count 0 2006.201.13:49:26.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:26.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.13:49:26.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:49:26.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:49:26.89$vck44/vblo=5,709.99 2006.201.13:49:26.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.13:49:26.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.13:49:26.89#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:26.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:26.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:26.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:26.89#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:49:26.89#ibcon#first serial, iclass 29, count 0 2006.201.13:49:26.89#ibcon#enter sib2, iclass 29, count 0 2006.201.13:49:26.89#ibcon#flushed, iclass 29, count 0 2006.201.13:49:26.89#ibcon#about to write, iclass 29, count 0 2006.201.13:49:26.89#ibcon#wrote, iclass 29, count 0 2006.201.13:49:26.89#ibcon#about to read 3, iclass 29, count 0 2006.201.13:49:26.91#ibcon#read 3, iclass 29, count 0 2006.201.13:49:26.91#ibcon#about to read 4, iclass 29, count 0 2006.201.13:49:26.91#ibcon#read 4, iclass 29, count 0 2006.201.13:49:26.91#ibcon#about to read 5, iclass 29, count 0 2006.201.13:49:26.91#ibcon#read 5, iclass 29, count 0 2006.201.13:49:26.91#ibcon#about to read 6, iclass 29, count 0 2006.201.13:49:26.91#ibcon#read 6, iclass 29, count 0 2006.201.13:49:26.91#ibcon#end of sib2, iclass 29, count 0 2006.201.13:49:26.91#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:49:26.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:49:26.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:49:26.91#ibcon#*before write, iclass 29, count 0 2006.201.13:49:26.91#ibcon#enter sib2, iclass 29, count 0 2006.201.13:49:26.91#ibcon#flushed, iclass 29, count 0 2006.201.13:49:26.91#ibcon#about to write, iclass 29, count 0 2006.201.13:49:26.91#ibcon#wrote, iclass 29, count 0 2006.201.13:49:26.91#ibcon#about to read 3, iclass 29, count 0 2006.201.13:49:26.95#ibcon#read 3, iclass 29, count 0 2006.201.13:49:26.95#ibcon#about to read 4, iclass 29, count 0 2006.201.13:49:26.95#ibcon#read 4, iclass 29, count 0 2006.201.13:49:26.95#ibcon#about to read 5, iclass 29, count 0 2006.201.13:49:26.95#ibcon#read 5, iclass 29, count 0 2006.201.13:49:26.95#ibcon#about to read 6, iclass 29, count 0 2006.201.13:49:26.95#ibcon#read 6, iclass 29, count 0 2006.201.13:49:26.95#ibcon#end of sib2, iclass 29, count 0 2006.201.13:49:26.95#ibcon#*after write, iclass 29, count 0 2006.201.13:49:26.95#ibcon#*before return 0, iclass 29, count 0 2006.201.13:49:26.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:26.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.13:49:26.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:49:26.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:49:26.95$vck44/vb=5,4 2006.201.13:49:26.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.13:49:26.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.13:49:26.95#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:26.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:27.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:27.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:27.01#ibcon#enter wrdev, iclass 31, count 2 2006.201.13:49:27.01#ibcon#first serial, iclass 31, count 2 2006.201.13:49:27.01#ibcon#enter sib2, iclass 31, count 2 2006.201.13:49:27.01#ibcon#flushed, iclass 31, count 2 2006.201.13:49:27.01#ibcon#about to write, iclass 31, count 2 2006.201.13:49:27.01#ibcon#wrote, iclass 31, count 2 2006.201.13:49:27.01#ibcon#about to read 3, iclass 31, count 2 2006.201.13:49:27.03#ibcon#read 3, iclass 31, count 2 2006.201.13:49:27.03#ibcon#about to read 4, iclass 31, count 2 2006.201.13:49:27.03#ibcon#read 4, iclass 31, count 2 2006.201.13:49:27.03#ibcon#about to read 5, iclass 31, count 2 2006.201.13:49:27.03#ibcon#read 5, iclass 31, count 2 2006.201.13:49:27.03#ibcon#about to read 6, iclass 31, count 2 2006.201.13:49:27.03#ibcon#read 6, iclass 31, count 2 2006.201.13:49:27.03#ibcon#end of sib2, iclass 31, count 2 2006.201.13:49:27.03#ibcon#*mode == 0, iclass 31, count 2 2006.201.13:49:27.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.13:49:27.03#ibcon#[27=AT05-04\r\n] 2006.201.13:49:27.03#ibcon#*before write, iclass 31, count 2 2006.201.13:49:27.03#ibcon#enter sib2, iclass 31, count 2 2006.201.13:49:27.03#ibcon#flushed, iclass 31, count 2 2006.201.13:49:27.03#ibcon#about to write, iclass 31, count 2 2006.201.13:49:27.03#ibcon#wrote, iclass 31, count 2 2006.201.13:49:27.03#ibcon#about to read 3, iclass 31, count 2 2006.201.13:49:27.06#ibcon#read 3, iclass 31, count 2 2006.201.13:49:27.06#ibcon#about to read 4, iclass 31, count 2 2006.201.13:49:27.06#ibcon#read 4, iclass 31, count 2 2006.201.13:49:27.06#ibcon#about to read 5, iclass 31, count 2 2006.201.13:49:27.06#ibcon#read 5, iclass 31, count 2 2006.201.13:49:27.06#ibcon#about to read 6, iclass 31, count 2 2006.201.13:49:27.06#ibcon#read 6, iclass 31, count 2 2006.201.13:49:27.06#ibcon#end of sib2, iclass 31, count 2 2006.201.13:49:27.06#ibcon#*after write, iclass 31, count 2 2006.201.13:49:27.06#ibcon#*before return 0, iclass 31, count 2 2006.201.13:49:27.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:27.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.13:49:27.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.13:49:27.06#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:27.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:27.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:27.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:27.18#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:49:27.18#ibcon#first serial, iclass 31, count 0 2006.201.13:49:27.18#ibcon#enter sib2, iclass 31, count 0 2006.201.13:49:27.18#ibcon#flushed, iclass 31, count 0 2006.201.13:49:27.18#ibcon#about to write, iclass 31, count 0 2006.201.13:49:27.18#ibcon#wrote, iclass 31, count 0 2006.201.13:49:27.18#ibcon#about to read 3, iclass 31, count 0 2006.201.13:49:27.21#ibcon#read 3, iclass 31, count 0 2006.201.13:49:27.21#ibcon#about to read 4, iclass 31, count 0 2006.201.13:49:27.21#ibcon#read 4, iclass 31, count 0 2006.201.13:49:27.21#ibcon#about to read 5, iclass 31, count 0 2006.201.13:49:27.21#ibcon#read 5, iclass 31, count 0 2006.201.13:49:27.21#ibcon#about to read 6, iclass 31, count 0 2006.201.13:49:27.21#ibcon#read 6, iclass 31, count 0 2006.201.13:49:27.21#ibcon#end of sib2, iclass 31, count 0 2006.201.13:49:27.21#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:49:27.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:49:27.21#ibcon#[27=USB\r\n] 2006.201.13:49:27.21#ibcon#*before write, iclass 31, count 0 2006.201.13:49:27.21#ibcon#enter sib2, iclass 31, count 0 2006.201.13:49:27.21#ibcon#flushed, iclass 31, count 0 2006.201.13:49:27.21#ibcon#about to write, iclass 31, count 0 2006.201.13:49:27.21#ibcon#wrote, iclass 31, count 0 2006.201.13:49:27.21#ibcon#about to read 3, iclass 31, count 0 2006.201.13:49:27.24#ibcon#read 3, iclass 31, count 0 2006.201.13:49:27.24#ibcon#about to read 4, iclass 31, count 0 2006.201.13:49:27.24#ibcon#read 4, iclass 31, count 0 2006.201.13:49:27.24#ibcon#about to read 5, iclass 31, count 0 2006.201.13:49:27.24#ibcon#read 5, iclass 31, count 0 2006.201.13:49:27.24#ibcon#about to read 6, iclass 31, count 0 2006.201.13:49:27.24#ibcon#read 6, iclass 31, count 0 2006.201.13:49:27.24#ibcon#end of sib2, iclass 31, count 0 2006.201.13:49:27.24#ibcon#*after write, iclass 31, count 0 2006.201.13:49:27.24#ibcon#*before return 0, iclass 31, count 0 2006.201.13:49:27.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:27.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.13:49:27.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:49:27.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:49:27.24$vck44/vblo=6,719.99 2006.201.13:49:27.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.13:49:27.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.13:49:27.24#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:27.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:27.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:27.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:27.24#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:49:27.24#ibcon#first serial, iclass 33, count 0 2006.201.13:49:27.24#ibcon#enter sib2, iclass 33, count 0 2006.201.13:49:27.24#ibcon#flushed, iclass 33, count 0 2006.201.13:49:27.24#ibcon#about to write, iclass 33, count 0 2006.201.13:49:27.24#ibcon#wrote, iclass 33, count 0 2006.201.13:49:27.24#ibcon#about to read 3, iclass 33, count 0 2006.201.13:49:27.26#ibcon#read 3, iclass 33, count 0 2006.201.13:49:27.26#ibcon#about to read 4, iclass 33, count 0 2006.201.13:49:27.26#ibcon#read 4, iclass 33, count 0 2006.201.13:49:27.26#ibcon#about to read 5, iclass 33, count 0 2006.201.13:49:27.26#ibcon#read 5, iclass 33, count 0 2006.201.13:49:27.26#ibcon#about to read 6, iclass 33, count 0 2006.201.13:49:27.26#ibcon#read 6, iclass 33, count 0 2006.201.13:49:27.26#ibcon#end of sib2, iclass 33, count 0 2006.201.13:49:27.26#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:49:27.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:49:27.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:49:27.26#ibcon#*before write, iclass 33, count 0 2006.201.13:49:27.26#ibcon#enter sib2, iclass 33, count 0 2006.201.13:49:27.26#ibcon#flushed, iclass 33, count 0 2006.201.13:49:27.26#ibcon#about to write, iclass 33, count 0 2006.201.13:49:27.26#ibcon#wrote, iclass 33, count 0 2006.201.13:49:27.26#ibcon#about to read 3, iclass 33, count 0 2006.201.13:49:27.30#ibcon#read 3, iclass 33, count 0 2006.201.13:49:27.30#ibcon#about to read 4, iclass 33, count 0 2006.201.13:49:27.30#ibcon#read 4, iclass 33, count 0 2006.201.13:49:27.30#ibcon#about to read 5, iclass 33, count 0 2006.201.13:49:27.30#ibcon#read 5, iclass 33, count 0 2006.201.13:49:27.30#ibcon#about to read 6, iclass 33, count 0 2006.201.13:49:27.30#ibcon#read 6, iclass 33, count 0 2006.201.13:49:27.30#ibcon#end of sib2, iclass 33, count 0 2006.201.13:49:27.30#ibcon#*after write, iclass 33, count 0 2006.201.13:49:27.30#ibcon#*before return 0, iclass 33, count 0 2006.201.13:49:27.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:27.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.13:49:27.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:49:27.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:49:27.30$vck44/vb=6,4 2006.201.13:49:27.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.13:49:27.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.13:49:27.30#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:27.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:27.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:27.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:27.36#ibcon#enter wrdev, iclass 35, count 2 2006.201.13:49:27.36#ibcon#first serial, iclass 35, count 2 2006.201.13:49:27.36#ibcon#enter sib2, iclass 35, count 2 2006.201.13:49:27.36#ibcon#flushed, iclass 35, count 2 2006.201.13:49:27.36#ibcon#about to write, iclass 35, count 2 2006.201.13:49:27.36#ibcon#wrote, iclass 35, count 2 2006.201.13:49:27.36#ibcon#about to read 3, iclass 35, count 2 2006.201.13:49:27.38#ibcon#read 3, iclass 35, count 2 2006.201.13:49:27.38#ibcon#about to read 4, iclass 35, count 2 2006.201.13:49:27.38#ibcon#read 4, iclass 35, count 2 2006.201.13:49:27.38#ibcon#about to read 5, iclass 35, count 2 2006.201.13:49:27.38#ibcon#read 5, iclass 35, count 2 2006.201.13:49:27.38#ibcon#about to read 6, iclass 35, count 2 2006.201.13:49:27.38#ibcon#read 6, iclass 35, count 2 2006.201.13:49:27.38#ibcon#end of sib2, iclass 35, count 2 2006.201.13:49:27.38#ibcon#*mode == 0, iclass 35, count 2 2006.201.13:49:27.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.13:49:27.38#ibcon#[27=AT06-04\r\n] 2006.201.13:49:27.38#ibcon#*before write, iclass 35, count 2 2006.201.13:49:27.38#ibcon#enter sib2, iclass 35, count 2 2006.201.13:49:27.38#ibcon#flushed, iclass 35, count 2 2006.201.13:49:27.38#ibcon#about to write, iclass 35, count 2 2006.201.13:49:27.38#ibcon#wrote, iclass 35, count 2 2006.201.13:49:27.38#ibcon#about to read 3, iclass 35, count 2 2006.201.13:49:27.41#ibcon#read 3, iclass 35, count 2 2006.201.13:49:27.41#ibcon#about to read 4, iclass 35, count 2 2006.201.13:49:27.41#ibcon#read 4, iclass 35, count 2 2006.201.13:49:27.41#ibcon#about to read 5, iclass 35, count 2 2006.201.13:49:27.41#ibcon#read 5, iclass 35, count 2 2006.201.13:49:27.41#ibcon#about to read 6, iclass 35, count 2 2006.201.13:49:27.41#ibcon#read 6, iclass 35, count 2 2006.201.13:49:27.41#ibcon#end of sib2, iclass 35, count 2 2006.201.13:49:27.41#ibcon#*after write, iclass 35, count 2 2006.201.13:49:27.41#ibcon#*before return 0, iclass 35, count 2 2006.201.13:49:27.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:27.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.13:49:27.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.13:49:27.41#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:27.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:27.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:27.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:27.53#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:49:27.53#ibcon#first serial, iclass 35, count 0 2006.201.13:49:27.53#ibcon#enter sib2, iclass 35, count 0 2006.201.13:49:27.53#ibcon#flushed, iclass 35, count 0 2006.201.13:49:27.53#ibcon#about to write, iclass 35, count 0 2006.201.13:49:27.53#ibcon#wrote, iclass 35, count 0 2006.201.13:49:27.53#ibcon#about to read 3, iclass 35, count 0 2006.201.13:49:27.55#ibcon#read 3, iclass 35, count 0 2006.201.13:49:27.55#ibcon#about to read 4, iclass 35, count 0 2006.201.13:49:27.55#ibcon#read 4, iclass 35, count 0 2006.201.13:49:27.55#ibcon#about to read 5, iclass 35, count 0 2006.201.13:49:27.55#ibcon#read 5, iclass 35, count 0 2006.201.13:49:27.55#ibcon#about to read 6, iclass 35, count 0 2006.201.13:49:27.55#ibcon#read 6, iclass 35, count 0 2006.201.13:49:27.55#ibcon#end of sib2, iclass 35, count 0 2006.201.13:49:27.55#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:49:27.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:49:27.55#ibcon#[27=USB\r\n] 2006.201.13:49:27.55#ibcon#*before write, iclass 35, count 0 2006.201.13:49:27.55#ibcon#enter sib2, iclass 35, count 0 2006.201.13:49:27.55#ibcon#flushed, iclass 35, count 0 2006.201.13:49:27.55#ibcon#about to write, iclass 35, count 0 2006.201.13:49:27.55#ibcon#wrote, iclass 35, count 0 2006.201.13:49:27.55#ibcon#about to read 3, iclass 35, count 0 2006.201.13:49:27.58#ibcon#read 3, iclass 35, count 0 2006.201.13:49:27.58#ibcon#about to read 4, iclass 35, count 0 2006.201.13:49:27.58#ibcon#read 4, iclass 35, count 0 2006.201.13:49:27.58#ibcon#about to read 5, iclass 35, count 0 2006.201.13:49:27.58#ibcon#read 5, iclass 35, count 0 2006.201.13:49:27.58#ibcon#about to read 6, iclass 35, count 0 2006.201.13:49:27.58#ibcon#read 6, iclass 35, count 0 2006.201.13:49:27.58#ibcon#end of sib2, iclass 35, count 0 2006.201.13:49:27.58#ibcon#*after write, iclass 35, count 0 2006.201.13:49:27.58#ibcon#*before return 0, iclass 35, count 0 2006.201.13:49:27.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:27.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.13:49:27.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:49:27.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:49:27.58$vck44/vblo=7,734.99 2006.201.13:49:27.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.13:49:27.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.13:49:27.58#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:27.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:27.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:27.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:27.58#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:49:27.58#ibcon#first serial, iclass 37, count 0 2006.201.13:49:27.58#ibcon#enter sib2, iclass 37, count 0 2006.201.13:49:27.58#ibcon#flushed, iclass 37, count 0 2006.201.13:49:27.58#ibcon#about to write, iclass 37, count 0 2006.201.13:49:27.58#ibcon#wrote, iclass 37, count 0 2006.201.13:49:27.58#ibcon#about to read 3, iclass 37, count 0 2006.201.13:49:27.60#ibcon#read 3, iclass 37, count 0 2006.201.13:49:27.60#ibcon#about to read 4, iclass 37, count 0 2006.201.13:49:27.60#ibcon#read 4, iclass 37, count 0 2006.201.13:49:27.60#ibcon#about to read 5, iclass 37, count 0 2006.201.13:49:27.60#ibcon#read 5, iclass 37, count 0 2006.201.13:49:27.60#ibcon#about to read 6, iclass 37, count 0 2006.201.13:49:27.60#ibcon#read 6, iclass 37, count 0 2006.201.13:49:27.60#ibcon#end of sib2, iclass 37, count 0 2006.201.13:49:27.60#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:49:27.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:49:27.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:49:27.60#ibcon#*before write, iclass 37, count 0 2006.201.13:49:27.60#ibcon#enter sib2, iclass 37, count 0 2006.201.13:49:27.60#ibcon#flushed, iclass 37, count 0 2006.201.13:49:27.60#ibcon#about to write, iclass 37, count 0 2006.201.13:49:27.60#ibcon#wrote, iclass 37, count 0 2006.201.13:49:27.60#ibcon#about to read 3, iclass 37, count 0 2006.201.13:49:27.64#ibcon#read 3, iclass 37, count 0 2006.201.13:49:27.64#ibcon#about to read 4, iclass 37, count 0 2006.201.13:49:27.64#ibcon#read 4, iclass 37, count 0 2006.201.13:49:27.64#ibcon#about to read 5, iclass 37, count 0 2006.201.13:49:27.64#ibcon#read 5, iclass 37, count 0 2006.201.13:49:27.64#ibcon#about to read 6, iclass 37, count 0 2006.201.13:49:27.64#ibcon#read 6, iclass 37, count 0 2006.201.13:49:27.64#ibcon#end of sib2, iclass 37, count 0 2006.201.13:49:27.64#ibcon#*after write, iclass 37, count 0 2006.201.13:49:27.64#ibcon#*before return 0, iclass 37, count 0 2006.201.13:49:27.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:27.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:49:27.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:49:27.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:49:27.64$vck44/vb=7,4 2006.201.13:49:27.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.13:49:27.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.13:49:27.64#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:27.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:27.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:27.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:27.70#ibcon#enter wrdev, iclass 39, count 2 2006.201.13:49:27.70#ibcon#first serial, iclass 39, count 2 2006.201.13:49:27.70#ibcon#enter sib2, iclass 39, count 2 2006.201.13:49:27.70#ibcon#flushed, iclass 39, count 2 2006.201.13:49:27.70#ibcon#about to write, iclass 39, count 2 2006.201.13:49:27.70#ibcon#wrote, iclass 39, count 2 2006.201.13:49:27.70#ibcon#about to read 3, iclass 39, count 2 2006.201.13:49:27.72#ibcon#read 3, iclass 39, count 2 2006.201.13:49:27.72#ibcon#about to read 4, iclass 39, count 2 2006.201.13:49:27.72#ibcon#read 4, iclass 39, count 2 2006.201.13:49:27.72#ibcon#about to read 5, iclass 39, count 2 2006.201.13:49:27.72#ibcon#read 5, iclass 39, count 2 2006.201.13:49:27.72#ibcon#about to read 6, iclass 39, count 2 2006.201.13:49:27.72#ibcon#read 6, iclass 39, count 2 2006.201.13:49:27.72#ibcon#end of sib2, iclass 39, count 2 2006.201.13:49:27.72#ibcon#*mode == 0, iclass 39, count 2 2006.201.13:49:27.72#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.13:49:27.72#ibcon#[27=AT07-04\r\n] 2006.201.13:49:27.72#ibcon#*before write, iclass 39, count 2 2006.201.13:49:27.72#ibcon#enter sib2, iclass 39, count 2 2006.201.13:49:27.72#ibcon#flushed, iclass 39, count 2 2006.201.13:49:27.72#ibcon#about to write, iclass 39, count 2 2006.201.13:49:27.72#ibcon#wrote, iclass 39, count 2 2006.201.13:49:27.72#ibcon#about to read 3, iclass 39, count 2 2006.201.13:49:27.75#ibcon#read 3, iclass 39, count 2 2006.201.13:49:27.75#ibcon#about to read 4, iclass 39, count 2 2006.201.13:49:27.75#ibcon#read 4, iclass 39, count 2 2006.201.13:49:27.75#ibcon#about to read 5, iclass 39, count 2 2006.201.13:49:27.75#ibcon#read 5, iclass 39, count 2 2006.201.13:49:27.75#ibcon#about to read 6, iclass 39, count 2 2006.201.13:49:27.75#ibcon#read 6, iclass 39, count 2 2006.201.13:49:27.75#ibcon#end of sib2, iclass 39, count 2 2006.201.13:49:27.75#ibcon#*after write, iclass 39, count 2 2006.201.13:49:27.75#ibcon#*before return 0, iclass 39, count 2 2006.201.13:49:27.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:27.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.13:49:27.75#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.13:49:27.75#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:27.75#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:27.87#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:27.87#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:27.87#ibcon#enter wrdev, iclass 39, count 0 2006.201.13:49:27.87#ibcon#first serial, iclass 39, count 0 2006.201.13:49:27.87#ibcon#enter sib2, iclass 39, count 0 2006.201.13:49:27.87#ibcon#flushed, iclass 39, count 0 2006.201.13:49:27.87#ibcon#about to write, iclass 39, count 0 2006.201.13:49:27.87#ibcon#wrote, iclass 39, count 0 2006.201.13:49:27.87#ibcon#about to read 3, iclass 39, count 0 2006.201.13:49:27.89#ibcon#read 3, iclass 39, count 0 2006.201.13:49:27.89#ibcon#about to read 4, iclass 39, count 0 2006.201.13:49:27.89#ibcon#read 4, iclass 39, count 0 2006.201.13:49:27.89#ibcon#about to read 5, iclass 39, count 0 2006.201.13:49:27.89#ibcon#read 5, iclass 39, count 0 2006.201.13:49:27.89#ibcon#about to read 6, iclass 39, count 0 2006.201.13:49:27.89#ibcon#read 6, iclass 39, count 0 2006.201.13:49:27.89#ibcon#end of sib2, iclass 39, count 0 2006.201.13:49:27.89#ibcon#*mode == 0, iclass 39, count 0 2006.201.13:49:27.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.13:49:27.89#ibcon#[27=USB\r\n] 2006.201.13:49:27.89#ibcon#*before write, iclass 39, count 0 2006.201.13:49:27.89#ibcon#enter sib2, iclass 39, count 0 2006.201.13:49:27.89#ibcon#flushed, iclass 39, count 0 2006.201.13:49:27.89#ibcon#about to write, iclass 39, count 0 2006.201.13:49:27.89#ibcon#wrote, iclass 39, count 0 2006.201.13:49:27.89#ibcon#about to read 3, iclass 39, count 0 2006.201.13:49:27.92#ibcon#read 3, iclass 39, count 0 2006.201.13:49:27.92#ibcon#about to read 4, iclass 39, count 0 2006.201.13:49:27.92#ibcon#read 4, iclass 39, count 0 2006.201.13:49:27.92#ibcon#about to read 5, iclass 39, count 0 2006.201.13:49:27.92#ibcon#read 5, iclass 39, count 0 2006.201.13:49:27.92#ibcon#about to read 6, iclass 39, count 0 2006.201.13:49:27.92#ibcon#read 6, iclass 39, count 0 2006.201.13:49:27.92#ibcon#end of sib2, iclass 39, count 0 2006.201.13:49:27.92#ibcon#*after write, iclass 39, count 0 2006.201.13:49:27.92#ibcon#*before return 0, iclass 39, count 0 2006.201.13:49:27.92#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:27.92#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.13:49:27.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.13:49:27.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.13:49:27.92$vck44/vblo=8,744.99 2006.201.13:49:27.92#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.13:49:27.92#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.13:49:27.92#ibcon#ireg 17 cls_cnt 0 2006.201.13:49:27.92#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:27.92#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:27.92#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:27.92#ibcon#enter wrdev, iclass 2, count 0 2006.201.13:49:27.92#ibcon#first serial, iclass 2, count 0 2006.201.13:49:27.92#ibcon#enter sib2, iclass 2, count 0 2006.201.13:49:27.92#ibcon#flushed, iclass 2, count 0 2006.201.13:49:27.92#ibcon#about to write, iclass 2, count 0 2006.201.13:49:27.92#ibcon#wrote, iclass 2, count 0 2006.201.13:49:27.92#ibcon#about to read 3, iclass 2, count 0 2006.201.13:49:27.94#ibcon#read 3, iclass 2, count 0 2006.201.13:49:27.94#ibcon#about to read 4, iclass 2, count 0 2006.201.13:49:27.94#ibcon#read 4, iclass 2, count 0 2006.201.13:49:27.94#ibcon#about to read 5, iclass 2, count 0 2006.201.13:49:27.94#ibcon#read 5, iclass 2, count 0 2006.201.13:49:27.94#ibcon#about to read 6, iclass 2, count 0 2006.201.13:49:27.94#ibcon#read 6, iclass 2, count 0 2006.201.13:49:27.94#ibcon#end of sib2, iclass 2, count 0 2006.201.13:49:27.94#ibcon#*mode == 0, iclass 2, count 0 2006.201.13:49:27.94#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.13:49:27.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:49:27.94#ibcon#*before write, iclass 2, count 0 2006.201.13:49:27.94#ibcon#enter sib2, iclass 2, count 0 2006.201.13:49:27.94#ibcon#flushed, iclass 2, count 0 2006.201.13:49:27.94#ibcon#about to write, iclass 2, count 0 2006.201.13:49:27.94#ibcon#wrote, iclass 2, count 0 2006.201.13:49:27.94#ibcon#about to read 3, iclass 2, count 0 2006.201.13:49:27.99#ibcon#read 3, iclass 2, count 0 2006.201.13:49:27.99#ibcon#about to read 4, iclass 2, count 0 2006.201.13:49:27.99#ibcon#read 4, iclass 2, count 0 2006.201.13:49:27.99#ibcon#about to read 5, iclass 2, count 0 2006.201.13:49:27.99#ibcon#read 5, iclass 2, count 0 2006.201.13:49:27.99#ibcon#about to read 6, iclass 2, count 0 2006.201.13:49:27.99#ibcon#read 6, iclass 2, count 0 2006.201.13:49:27.99#ibcon#end of sib2, iclass 2, count 0 2006.201.13:49:27.99#ibcon#*after write, iclass 2, count 0 2006.201.13:49:27.99#ibcon#*before return 0, iclass 2, count 0 2006.201.13:49:27.99#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:27.99#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.13:49:27.99#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.13:49:27.99#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.13:49:27.99$vck44/vb=8,4 2006.201.13:49:27.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.13:49:27.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.13:49:27.99#ibcon#ireg 11 cls_cnt 2 2006.201.13:49:27.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:28.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:28.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:28.04#ibcon#enter wrdev, iclass 5, count 2 2006.201.13:49:28.04#ibcon#first serial, iclass 5, count 2 2006.201.13:49:28.04#ibcon#enter sib2, iclass 5, count 2 2006.201.13:49:28.04#ibcon#flushed, iclass 5, count 2 2006.201.13:49:28.04#ibcon#about to write, iclass 5, count 2 2006.201.13:49:28.04#ibcon#wrote, iclass 5, count 2 2006.201.13:49:28.04#ibcon#about to read 3, iclass 5, count 2 2006.201.13:49:28.06#ibcon#read 3, iclass 5, count 2 2006.201.13:49:28.06#ibcon#about to read 4, iclass 5, count 2 2006.201.13:49:28.06#ibcon#read 4, iclass 5, count 2 2006.201.13:49:28.06#ibcon#about to read 5, iclass 5, count 2 2006.201.13:49:28.06#ibcon#read 5, iclass 5, count 2 2006.201.13:49:28.06#ibcon#about to read 6, iclass 5, count 2 2006.201.13:49:28.06#ibcon#read 6, iclass 5, count 2 2006.201.13:49:28.06#ibcon#end of sib2, iclass 5, count 2 2006.201.13:49:28.06#ibcon#*mode == 0, iclass 5, count 2 2006.201.13:49:28.06#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.13:49:28.06#ibcon#[27=AT08-04\r\n] 2006.201.13:49:28.06#ibcon#*before write, iclass 5, count 2 2006.201.13:49:28.06#ibcon#enter sib2, iclass 5, count 2 2006.201.13:49:28.06#ibcon#flushed, iclass 5, count 2 2006.201.13:49:28.06#ibcon#about to write, iclass 5, count 2 2006.201.13:49:28.06#ibcon#wrote, iclass 5, count 2 2006.201.13:49:28.06#ibcon#about to read 3, iclass 5, count 2 2006.201.13:49:28.09#ibcon#read 3, iclass 5, count 2 2006.201.13:49:28.09#ibcon#about to read 4, iclass 5, count 2 2006.201.13:49:28.09#ibcon#read 4, iclass 5, count 2 2006.201.13:49:28.09#ibcon#about to read 5, iclass 5, count 2 2006.201.13:49:28.09#ibcon#read 5, iclass 5, count 2 2006.201.13:49:28.09#ibcon#about to read 6, iclass 5, count 2 2006.201.13:49:28.09#ibcon#read 6, iclass 5, count 2 2006.201.13:49:28.09#ibcon#end of sib2, iclass 5, count 2 2006.201.13:49:28.09#ibcon#*after write, iclass 5, count 2 2006.201.13:49:28.09#ibcon#*before return 0, iclass 5, count 2 2006.201.13:49:28.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:28.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.13:49:28.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.13:49:28.09#ibcon#ireg 7 cls_cnt 0 2006.201.13:49:28.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:28.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:28.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:28.21#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:49:28.21#ibcon#first serial, iclass 5, count 0 2006.201.13:49:28.21#ibcon#enter sib2, iclass 5, count 0 2006.201.13:49:28.21#ibcon#flushed, iclass 5, count 0 2006.201.13:49:28.21#ibcon#about to write, iclass 5, count 0 2006.201.13:49:28.21#ibcon#wrote, iclass 5, count 0 2006.201.13:49:28.21#ibcon#about to read 3, iclass 5, count 0 2006.201.13:49:28.23#ibcon#read 3, iclass 5, count 0 2006.201.13:49:28.23#ibcon#about to read 4, iclass 5, count 0 2006.201.13:49:28.23#ibcon#read 4, iclass 5, count 0 2006.201.13:49:28.23#ibcon#about to read 5, iclass 5, count 0 2006.201.13:49:28.23#ibcon#read 5, iclass 5, count 0 2006.201.13:49:28.23#ibcon#about to read 6, iclass 5, count 0 2006.201.13:49:28.23#ibcon#read 6, iclass 5, count 0 2006.201.13:49:28.23#ibcon#end of sib2, iclass 5, count 0 2006.201.13:49:28.23#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:49:28.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:49:28.23#ibcon#[27=USB\r\n] 2006.201.13:49:28.23#ibcon#*before write, iclass 5, count 0 2006.201.13:49:28.23#ibcon#enter sib2, iclass 5, count 0 2006.201.13:49:28.23#ibcon#flushed, iclass 5, count 0 2006.201.13:49:28.23#ibcon#about to write, iclass 5, count 0 2006.201.13:49:28.23#ibcon#wrote, iclass 5, count 0 2006.201.13:49:28.23#ibcon#about to read 3, iclass 5, count 0 2006.201.13:49:28.26#ibcon#read 3, iclass 5, count 0 2006.201.13:49:28.26#ibcon#about to read 4, iclass 5, count 0 2006.201.13:49:28.26#ibcon#read 4, iclass 5, count 0 2006.201.13:49:28.26#ibcon#about to read 5, iclass 5, count 0 2006.201.13:49:28.26#ibcon#read 5, iclass 5, count 0 2006.201.13:49:28.26#ibcon#about to read 6, iclass 5, count 0 2006.201.13:49:28.26#ibcon#read 6, iclass 5, count 0 2006.201.13:49:28.26#ibcon#end of sib2, iclass 5, count 0 2006.201.13:49:28.26#ibcon#*after write, iclass 5, count 0 2006.201.13:49:28.26#ibcon#*before return 0, iclass 5, count 0 2006.201.13:49:28.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:28.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.13:49:28.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:49:28.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:49:28.26$vck44/vabw=wide 2006.201.13:49:28.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.13:49:28.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.13:49:28.26#ibcon#ireg 8 cls_cnt 0 2006.201.13:49:28.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:28.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:28.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:28.26#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:49:28.26#ibcon#first serial, iclass 7, count 0 2006.201.13:49:28.26#ibcon#enter sib2, iclass 7, count 0 2006.201.13:49:28.26#ibcon#flushed, iclass 7, count 0 2006.201.13:49:28.26#ibcon#about to write, iclass 7, count 0 2006.201.13:49:28.26#ibcon#wrote, iclass 7, count 0 2006.201.13:49:28.26#ibcon#about to read 3, iclass 7, count 0 2006.201.13:49:28.28#ibcon#read 3, iclass 7, count 0 2006.201.13:49:28.28#ibcon#about to read 4, iclass 7, count 0 2006.201.13:49:28.28#ibcon#read 4, iclass 7, count 0 2006.201.13:49:28.28#ibcon#about to read 5, iclass 7, count 0 2006.201.13:49:28.28#ibcon#read 5, iclass 7, count 0 2006.201.13:49:28.28#ibcon#about to read 6, iclass 7, count 0 2006.201.13:49:28.28#ibcon#read 6, iclass 7, count 0 2006.201.13:49:28.28#ibcon#end of sib2, iclass 7, count 0 2006.201.13:49:28.28#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:49:28.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:49:28.28#ibcon#[25=BW32\r\n] 2006.201.13:49:28.28#ibcon#*before write, iclass 7, count 0 2006.201.13:49:28.28#ibcon#enter sib2, iclass 7, count 0 2006.201.13:49:28.28#ibcon#flushed, iclass 7, count 0 2006.201.13:49:28.28#ibcon#about to write, iclass 7, count 0 2006.201.13:49:28.28#ibcon#wrote, iclass 7, count 0 2006.201.13:49:28.28#ibcon#about to read 3, iclass 7, count 0 2006.201.13:49:28.31#ibcon#read 3, iclass 7, count 0 2006.201.13:49:28.31#ibcon#about to read 4, iclass 7, count 0 2006.201.13:49:28.31#ibcon#read 4, iclass 7, count 0 2006.201.13:49:28.31#ibcon#about to read 5, iclass 7, count 0 2006.201.13:49:28.31#ibcon#read 5, iclass 7, count 0 2006.201.13:49:28.31#ibcon#about to read 6, iclass 7, count 0 2006.201.13:49:28.31#ibcon#read 6, iclass 7, count 0 2006.201.13:49:28.31#ibcon#end of sib2, iclass 7, count 0 2006.201.13:49:28.31#ibcon#*after write, iclass 7, count 0 2006.201.13:49:28.31#ibcon#*before return 0, iclass 7, count 0 2006.201.13:49:28.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:28.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.13:49:28.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:49:28.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:49:28.31$vck44/vbbw=wide 2006.201.13:49:28.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.13:49:28.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.13:49:28.31#ibcon#ireg 8 cls_cnt 0 2006.201.13:49:28.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:49:28.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:49:28.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:49:28.38#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:49:28.38#ibcon#first serial, iclass 11, count 0 2006.201.13:49:28.38#ibcon#enter sib2, iclass 11, count 0 2006.201.13:49:28.38#ibcon#flushed, iclass 11, count 0 2006.201.13:49:28.38#ibcon#about to write, iclass 11, count 0 2006.201.13:49:28.38#ibcon#wrote, iclass 11, count 0 2006.201.13:49:28.38#ibcon#about to read 3, iclass 11, count 0 2006.201.13:49:28.40#ibcon#read 3, iclass 11, count 0 2006.201.13:49:28.40#ibcon#about to read 4, iclass 11, count 0 2006.201.13:49:28.40#ibcon#read 4, iclass 11, count 0 2006.201.13:49:28.40#ibcon#about to read 5, iclass 11, count 0 2006.201.13:49:28.40#ibcon#read 5, iclass 11, count 0 2006.201.13:49:28.40#ibcon#about to read 6, iclass 11, count 0 2006.201.13:49:28.40#ibcon#read 6, iclass 11, count 0 2006.201.13:49:28.40#ibcon#end of sib2, iclass 11, count 0 2006.201.13:49:28.40#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:49:28.40#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:49:28.40#ibcon#[27=BW32\r\n] 2006.201.13:49:28.40#ibcon#*before write, iclass 11, count 0 2006.201.13:49:28.40#ibcon#enter sib2, iclass 11, count 0 2006.201.13:49:28.40#ibcon#flushed, iclass 11, count 0 2006.201.13:49:28.40#ibcon#about to write, iclass 11, count 0 2006.201.13:49:28.40#ibcon#wrote, iclass 11, count 0 2006.201.13:49:28.40#ibcon#about to read 3, iclass 11, count 0 2006.201.13:49:28.43#ibcon#read 3, iclass 11, count 0 2006.201.13:49:28.43#ibcon#about to read 4, iclass 11, count 0 2006.201.13:49:28.43#ibcon#read 4, iclass 11, count 0 2006.201.13:49:28.43#ibcon#about to read 5, iclass 11, count 0 2006.201.13:49:28.43#ibcon#read 5, iclass 11, count 0 2006.201.13:49:28.43#ibcon#about to read 6, iclass 11, count 0 2006.201.13:49:28.43#ibcon#read 6, iclass 11, count 0 2006.201.13:49:28.43#ibcon#end of sib2, iclass 11, count 0 2006.201.13:49:28.43#ibcon#*after write, iclass 11, count 0 2006.201.13:49:28.43#ibcon#*before return 0, iclass 11, count 0 2006.201.13:49:28.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:49:28.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:49:28.43#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:49:28.43#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:49:28.43$setupk4/ifdk4 2006.201.13:49:28.43$ifdk4/lo= 2006.201.13:49:28.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:49:28.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:49:28.43$ifdk4/patch= 2006.201.13:49:28.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:49:28.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:49:28.43$setupk4/!*+20s 2006.201.13:49:31.30#abcon#<5=/04 1.2 2.3 20.881001003.9\r\n> 2006.201.13:49:31.32#abcon#{5=INTERFACE CLEAR} 2006.201.13:49:31.38#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:49:41.47#abcon#<5=/04 1.2 2.3 20.881001003.9\r\n> 2006.201.13:49:41.49#abcon#{5=INTERFACE CLEAR} 2006.201.13:49:41.55#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:49:42.88$setupk4/"tpicd 2006.201.13:49:42.88$setupk4/echo=off 2006.201.13:49:42.88$setupk4/xlog=off 2006.201.13:49:42.88:!2006.201.13:53:12 2006.201.13:49:44.14#trakl#Source acquired 2006.201.13:49:45.14#flagr#flagr/antenna,acquired 2006.201.13:53:12.00:preob 2006.201.13:53:13.14/onsource/TRACKING 2006.201.13:53:13.14:!2006.201.13:53:22 2006.201.13:53:22.00:"tape 2006.201.13:53:22.00:"st=record 2006.201.13:53:22.00:data_valid=on 2006.201.13:53:22.00:midob 2006.201.13:53:22.14/onsource/TRACKING 2006.201.13:53:22.14/wx/20.88,1004.0,100 2006.201.13:53:22.32/cable/+6.4748E-03 2006.201.13:53:23.41/va/01,08,usb,yes,32,35 2006.201.13:53:23.41/va/02,07,usb,yes,35,36 2006.201.13:53:23.41/va/03,08,usb,yes,31,33 2006.201.13:53:23.41/va/04,07,usb,yes,36,38 2006.201.13:53:23.41/va/05,04,usb,yes,32,32 2006.201.13:53:23.41/va/06,05,usb,yes,32,32 2006.201.13:53:23.41/va/07,05,usb,yes,31,32 2006.201.13:53:23.41/va/08,04,usb,yes,31,37 2006.201.13:53:23.64/valo/01,524.99,yes,locked 2006.201.13:53:23.64/valo/02,534.99,yes,locked 2006.201.13:53:23.64/valo/03,564.99,yes,locked 2006.201.13:53:23.64/valo/04,624.99,yes,locked 2006.201.13:53:23.64/valo/05,734.99,yes,locked 2006.201.13:53:23.64/valo/06,814.99,yes,locked 2006.201.13:53:23.64/valo/07,864.99,yes,locked 2006.201.13:53:23.64/valo/08,884.99,yes,locked 2006.201.13:53:24.73/vb/01,04,usb,yes,30,27 2006.201.13:53:24.73/vb/02,05,usb,yes,28,28 2006.201.13:53:24.73/vb/03,04,usb,yes,29,32 2006.201.13:53:24.73/vb/04,05,usb,yes,29,28 2006.201.13:53:24.73/vb/05,04,usb,yes,26,28 2006.201.13:53:24.73/vb/06,04,usb,yes,30,26 2006.201.13:53:24.73/vb/07,04,usb,yes,30,30 2006.201.13:53:24.73/vb/08,04,usb,yes,28,31 2006.201.13:53:24.96/vblo/01,629.99,yes,locked 2006.201.13:53:24.96/vblo/02,634.99,yes,locked 2006.201.13:53:24.96/vblo/03,649.99,yes,locked 2006.201.13:53:24.96/vblo/04,679.99,yes,locked 2006.201.13:53:24.96/vblo/05,709.99,yes,locked 2006.201.13:53:24.96/vblo/06,719.99,yes,locked 2006.201.13:53:24.96/vblo/07,734.99,yes,locked 2006.201.13:53:24.96/vblo/08,744.99,yes,locked 2006.201.13:53:25.11/vabw/8 2006.201.13:53:25.26/vbbw/8 2006.201.13:53:25.43/xfe/off,on,15.5 2006.201.13:53:25.85/ifatt/23,28,28,28 2006.201.13:53:26.05/fmout-gps/S +4.55E-07 2006.201.13:53:26.12:!2006.201.13:54:02 2006.201.13:54:02.00:data_valid=off 2006.201.13:54:02.00:"et 2006.201.13:54:02.00:!+3s 2006.201.13:54:05.02:"tape 2006.201.13:54:05.02:postob 2006.201.13:54:05.24/cable/+6.4750E-03 2006.201.13:54:05.24/wx/20.88,1004.0,100 2006.201.13:54:05.32/fmout-gps/S +4.53E-07 2006.201.13:54:05.32:scan_name=201-1358,jd0607,40 2006.201.13:54:05.32:source=3c454.3,225357.75,160853.6,2000.0,cw 2006.201.13:54:07.14#flagr#flagr/antenna,new-source 2006.201.13:54:07.14:checkk5 2006.201.13:54:07.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:54:07.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:54:08.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:54:08.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:54:09.00/chk_obsdata//k5ts1/T2011353??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.13:54:09.36/chk_obsdata//k5ts2/T2011353??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.13:54:09.72/chk_obsdata//k5ts3/T2011353??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.13:54:10.10/chk_obsdata//k5ts4/T2011353??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.13:54:10.78/k5log//k5ts1_log_newline 2006.201.13:54:11.46/k5log//k5ts2_log_newline 2006.201.13:54:12.15/k5log//k5ts3_log_newline 2006.201.13:54:12.84/k5log//k5ts4_log_newline 2006.201.13:54:12.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:54:12.87:setupk4=1 2006.201.13:54:12.87$setupk4/echo=on 2006.201.13:54:12.87$setupk4/pcalon 2006.201.13:54:12.87$pcalon/"no phase cal control is implemented here 2006.201.13:54:12.87$setupk4/"tpicd=stop 2006.201.13:54:12.87$setupk4/"rec=synch_on 2006.201.13:54:12.87$setupk4/"rec_mode=128 2006.201.13:54:12.87$setupk4/!* 2006.201.13:54:12.87$setupk4/recpk4 2006.201.13:54:12.87$recpk4/recpatch= 2006.201.13:54:12.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:54:12.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:54:12.87$setupk4/vck44 2006.201.13:54:12.87$vck44/valo=1,524.99 2006.201.13:54:12.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.13:54:12.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.13:54:12.87#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:12.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:12.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:12.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:12.87#ibcon#enter wrdev, iclass 20, count 0 2006.201.13:54:12.87#ibcon#first serial, iclass 20, count 0 2006.201.13:54:12.87#ibcon#enter sib2, iclass 20, count 0 2006.201.13:54:12.87#ibcon#flushed, iclass 20, count 0 2006.201.13:54:12.87#ibcon#about to write, iclass 20, count 0 2006.201.13:54:12.87#ibcon#wrote, iclass 20, count 0 2006.201.13:54:12.87#ibcon#about to read 3, iclass 20, count 0 2006.201.13:54:12.91#ibcon#read 3, iclass 20, count 0 2006.201.13:54:12.91#ibcon#about to read 4, iclass 20, count 0 2006.201.13:54:12.91#ibcon#read 4, iclass 20, count 0 2006.201.13:54:12.91#ibcon#about to read 5, iclass 20, count 0 2006.201.13:54:12.91#ibcon#read 5, iclass 20, count 0 2006.201.13:54:12.91#ibcon#about to read 6, iclass 20, count 0 2006.201.13:54:12.91#ibcon#read 6, iclass 20, count 0 2006.201.13:54:12.91#ibcon#end of sib2, iclass 20, count 0 2006.201.13:54:12.91#ibcon#*mode == 0, iclass 20, count 0 2006.201.13:54:12.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.13:54:12.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:54:12.91#ibcon#*before write, iclass 20, count 0 2006.201.13:54:12.91#ibcon#enter sib2, iclass 20, count 0 2006.201.13:54:12.91#ibcon#flushed, iclass 20, count 0 2006.201.13:54:12.91#ibcon#about to write, iclass 20, count 0 2006.201.13:54:12.91#ibcon#wrote, iclass 20, count 0 2006.201.13:54:12.91#ibcon#about to read 3, iclass 20, count 0 2006.201.13:54:12.96#ibcon#read 3, iclass 20, count 0 2006.201.13:54:12.96#ibcon#about to read 4, iclass 20, count 0 2006.201.13:54:12.96#ibcon#read 4, iclass 20, count 0 2006.201.13:54:12.96#ibcon#about to read 5, iclass 20, count 0 2006.201.13:54:12.96#ibcon#read 5, iclass 20, count 0 2006.201.13:54:12.96#ibcon#about to read 6, iclass 20, count 0 2006.201.13:54:12.96#ibcon#read 6, iclass 20, count 0 2006.201.13:54:12.96#ibcon#end of sib2, iclass 20, count 0 2006.201.13:54:12.96#ibcon#*after write, iclass 20, count 0 2006.201.13:54:12.96#ibcon#*before return 0, iclass 20, count 0 2006.201.13:54:12.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:12.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:12.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.13:54:12.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.13:54:12.96$vck44/va=1,8 2006.201.13:54:12.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.13:54:12.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.13:54:12.96#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:12.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:12.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:12.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:12.96#ibcon#enter wrdev, iclass 22, count 2 2006.201.13:54:12.96#ibcon#first serial, iclass 22, count 2 2006.201.13:54:12.96#ibcon#enter sib2, iclass 22, count 2 2006.201.13:54:12.96#ibcon#flushed, iclass 22, count 2 2006.201.13:54:12.96#ibcon#about to write, iclass 22, count 2 2006.201.13:54:12.96#ibcon#wrote, iclass 22, count 2 2006.201.13:54:12.96#ibcon#about to read 3, iclass 22, count 2 2006.201.13:54:12.98#ibcon#read 3, iclass 22, count 2 2006.201.13:54:12.98#ibcon#about to read 4, iclass 22, count 2 2006.201.13:54:12.98#ibcon#read 4, iclass 22, count 2 2006.201.13:54:12.98#ibcon#about to read 5, iclass 22, count 2 2006.201.13:54:12.98#ibcon#read 5, iclass 22, count 2 2006.201.13:54:12.98#ibcon#about to read 6, iclass 22, count 2 2006.201.13:54:12.98#ibcon#read 6, iclass 22, count 2 2006.201.13:54:12.98#ibcon#end of sib2, iclass 22, count 2 2006.201.13:54:12.98#ibcon#*mode == 0, iclass 22, count 2 2006.201.13:54:12.98#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.13:54:12.98#ibcon#[25=AT01-08\r\n] 2006.201.13:54:12.98#ibcon#*before write, iclass 22, count 2 2006.201.13:54:12.98#ibcon#enter sib2, iclass 22, count 2 2006.201.13:54:12.98#ibcon#flushed, iclass 22, count 2 2006.201.13:54:12.98#ibcon#about to write, iclass 22, count 2 2006.201.13:54:12.98#ibcon#wrote, iclass 22, count 2 2006.201.13:54:12.98#ibcon#about to read 3, iclass 22, count 2 2006.201.13:54:13.01#ibcon#read 3, iclass 22, count 2 2006.201.13:54:13.01#ibcon#about to read 4, iclass 22, count 2 2006.201.13:54:13.01#ibcon#read 4, iclass 22, count 2 2006.201.13:54:13.01#ibcon#about to read 5, iclass 22, count 2 2006.201.13:54:13.01#ibcon#read 5, iclass 22, count 2 2006.201.13:54:13.01#ibcon#about to read 6, iclass 22, count 2 2006.201.13:54:13.01#ibcon#read 6, iclass 22, count 2 2006.201.13:54:13.01#ibcon#end of sib2, iclass 22, count 2 2006.201.13:54:13.01#ibcon#*after write, iclass 22, count 2 2006.201.13:54:13.01#ibcon#*before return 0, iclass 22, count 2 2006.201.13:54:13.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:13.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:13.01#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.13:54:13.01#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:13.01#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:13.13#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:13.13#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:13.13#ibcon#enter wrdev, iclass 22, count 0 2006.201.13:54:13.13#ibcon#first serial, iclass 22, count 0 2006.201.13:54:13.13#ibcon#enter sib2, iclass 22, count 0 2006.201.13:54:13.13#ibcon#flushed, iclass 22, count 0 2006.201.13:54:13.13#ibcon#about to write, iclass 22, count 0 2006.201.13:54:13.13#ibcon#wrote, iclass 22, count 0 2006.201.13:54:13.13#ibcon#about to read 3, iclass 22, count 0 2006.201.13:54:13.15#ibcon#read 3, iclass 22, count 0 2006.201.13:54:13.15#ibcon#about to read 4, iclass 22, count 0 2006.201.13:54:13.15#ibcon#read 4, iclass 22, count 0 2006.201.13:54:13.15#ibcon#about to read 5, iclass 22, count 0 2006.201.13:54:13.15#ibcon#read 5, iclass 22, count 0 2006.201.13:54:13.15#ibcon#about to read 6, iclass 22, count 0 2006.201.13:54:13.15#ibcon#read 6, iclass 22, count 0 2006.201.13:54:13.15#ibcon#end of sib2, iclass 22, count 0 2006.201.13:54:13.15#ibcon#*mode == 0, iclass 22, count 0 2006.201.13:54:13.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.13:54:13.15#ibcon#[25=USB\r\n] 2006.201.13:54:13.15#ibcon#*before write, iclass 22, count 0 2006.201.13:54:13.15#ibcon#enter sib2, iclass 22, count 0 2006.201.13:54:13.15#ibcon#flushed, iclass 22, count 0 2006.201.13:54:13.15#ibcon#about to write, iclass 22, count 0 2006.201.13:54:13.15#ibcon#wrote, iclass 22, count 0 2006.201.13:54:13.15#ibcon#about to read 3, iclass 22, count 0 2006.201.13:54:13.18#ibcon#read 3, iclass 22, count 0 2006.201.13:54:13.18#ibcon#about to read 4, iclass 22, count 0 2006.201.13:54:13.18#ibcon#read 4, iclass 22, count 0 2006.201.13:54:13.18#ibcon#about to read 5, iclass 22, count 0 2006.201.13:54:13.18#ibcon#read 5, iclass 22, count 0 2006.201.13:54:13.18#ibcon#about to read 6, iclass 22, count 0 2006.201.13:54:13.18#ibcon#read 6, iclass 22, count 0 2006.201.13:54:13.18#ibcon#end of sib2, iclass 22, count 0 2006.201.13:54:13.18#ibcon#*after write, iclass 22, count 0 2006.201.13:54:13.18#ibcon#*before return 0, iclass 22, count 0 2006.201.13:54:13.18#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:13.18#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:13.18#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.13:54:13.18#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.13:54:13.18$vck44/valo=2,534.99 2006.201.13:54:13.18#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.13:54:13.18#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.13:54:13.18#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:13.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:13.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:13.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:13.18#ibcon#enter wrdev, iclass 24, count 0 2006.201.13:54:13.18#ibcon#first serial, iclass 24, count 0 2006.201.13:54:13.18#ibcon#enter sib2, iclass 24, count 0 2006.201.13:54:13.18#ibcon#flushed, iclass 24, count 0 2006.201.13:54:13.18#ibcon#about to write, iclass 24, count 0 2006.201.13:54:13.18#ibcon#wrote, iclass 24, count 0 2006.201.13:54:13.18#ibcon#about to read 3, iclass 24, count 0 2006.201.13:54:13.20#ibcon#read 3, iclass 24, count 0 2006.201.13:54:13.20#ibcon#about to read 4, iclass 24, count 0 2006.201.13:54:13.20#ibcon#read 4, iclass 24, count 0 2006.201.13:54:13.20#ibcon#about to read 5, iclass 24, count 0 2006.201.13:54:13.20#ibcon#read 5, iclass 24, count 0 2006.201.13:54:13.20#ibcon#about to read 6, iclass 24, count 0 2006.201.13:54:13.20#ibcon#read 6, iclass 24, count 0 2006.201.13:54:13.20#ibcon#end of sib2, iclass 24, count 0 2006.201.13:54:13.20#ibcon#*mode == 0, iclass 24, count 0 2006.201.13:54:13.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.13:54:13.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:54:13.20#ibcon#*before write, iclass 24, count 0 2006.201.13:54:13.20#ibcon#enter sib2, iclass 24, count 0 2006.201.13:54:13.20#ibcon#flushed, iclass 24, count 0 2006.201.13:54:13.20#ibcon#about to write, iclass 24, count 0 2006.201.13:54:13.20#ibcon#wrote, iclass 24, count 0 2006.201.13:54:13.20#ibcon#about to read 3, iclass 24, count 0 2006.201.13:54:13.25#ibcon#read 3, iclass 24, count 0 2006.201.13:54:13.25#ibcon#about to read 4, iclass 24, count 0 2006.201.13:54:13.25#ibcon#read 4, iclass 24, count 0 2006.201.13:54:13.25#ibcon#about to read 5, iclass 24, count 0 2006.201.13:54:13.25#ibcon#read 5, iclass 24, count 0 2006.201.13:54:13.25#ibcon#about to read 6, iclass 24, count 0 2006.201.13:54:13.25#ibcon#read 6, iclass 24, count 0 2006.201.13:54:13.25#ibcon#end of sib2, iclass 24, count 0 2006.201.13:54:13.25#ibcon#*after write, iclass 24, count 0 2006.201.13:54:13.25#ibcon#*before return 0, iclass 24, count 0 2006.201.13:54:13.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:13.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:13.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.13:54:13.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.13:54:13.25$vck44/va=2,7 2006.201.13:54:13.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.13:54:13.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.13:54:13.25#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:13.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:13.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:13.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:13.30#ibcon#enter wrdev, iclass 26, count 2 2006.201.13:54:13.30#ibcon#first serial, iclass 26, count 2 2006.201.13:54:13.30#ibcon#enter sib2, iclass 26, count 2 2006.201.13:54:13.30#ibcon#flushed, iclass 26, count 2 2006.201.13:54:13.30#ibcon#about to write, iclass 26, count 2 2006.201.13:54:13.30#ibcon#wrote, iclass 26, count 2 2006.201.13:54:13.30#ibcon#about to read 3, iclass 26, count 2 2006.201.13:54:13.32#ibcon#read 3, iclass 26, count 2 2006.201.13:54:13.32#ibcon#about to read 4, iclass 26, count 2 2006.201.13:54:13.32#ibcon#read 4, iclass 26, count 2 2006.201.13:54:13.32#ibcon#about to read 5, iclass 26, count 2 2006.201.13:54:13.32#ibcon#read 5, iclass 26, count 2 2006.201.13:54:13.32#ibcon#about to read 6, iclass 26, count 2 2006.201.13:54:13.32#ibcon#read 6, iclass 26, count 2 2006.201.13:54:13.32#ibcon#end of sib2, iclass 26, count 2 2006.201.13:54:13.32#ibcon#*mode == 0, iclass 26, count 2 2006.201.13:54:13.32#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.13:54:13.32#ibcon#[25=AT02-07\r\n] 2006.201.13:54:13.32#ibcon#*before write, iclass 26, count 2 2006.201.13:54:13.32#ibcon#enter sib2, iclass 26, count 2 2006.201.13:54:13.32#ibcon#flushed, iclass 26, count 2 2006.201.13:54:13.32#ibcon#about to write, iclass 26, count 2 2006.201.13:54:13.32#ibcon#wrote, iclass 26, count 2 2006.201.13:54:13.32#ibcon#about to read 3, iclass 26, count 2 2006.201.13:54:13.35#ibcon#read 3, iclass 26, count 2 2006.201.13:54:13.35#ibcon#about to read 4, iclass 26, count 2 2006.201.13:54:13.35#ibcon#read 4, iclass 26, count 2 2006.201.13:54:13.35#ibcon#about to read 5, iclass 26, count 2 2006.201.13:54:13.35#ibcon#read 5, iclass 26, count 2 2006.201.13:54:13.35#ibcon#about to read 6, iclass 26, count 2 2006.201.13:54:13.35#ibcon#read 6, iclass 26, count 2 2006.201.13:54:13.35#ibcon#end of sib2, iclass 26, count 2 2006.201.13:54:13.35#ibcon#*after write, iclass 26, count 2 2006.201.13:54:13.35#ibcon#*before return 0, iclass 26, count 2 2006.201.13:54:13.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:13.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:13.35#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.13:54:13.35#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:13.35#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:13.47#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:13.47#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:13.47#ibcon#enter wrdev, iclass 26, count 0 2006.201.13:54:13.47#ibcon#first serial, iclass 26, count 0 2006.201.13:54:13.47#ibcon#enter sib2, iclass 26, count 0 2006.201.13:54:13.47#ibcon#flushed, iclass 26, count 0 2006.201.13:54:13.47#ibcon#about to write, iclass 26, count 0 2006.201.13:54:13.47#ibcon#wrote, iclass 26, count 0 2006.201.13:54:13.47#ibcon#about to read 3, iclass 26, count 0 2006.201.13:54:13.49#ibcon#read 3, iclass 26, count 0 2006.201.13:54:13.49#ibcon#about to read 4, iclass 26, count 0 2006.201.13:54:13.49#ibcon#read 4, iclass 26, count 0 2006.201.13:54:13.49#ibcon#about to read 5, iclass 26, count 0 2006.201.13:54:13.49#ibcon#read 5, iclass 26, count 0 2006.201.13:54:13.49#ibcon#about to read 6, iclass 26, count 0 2006.201.13:54:13.49#ibcon#read 6, iclass 26, count 0 2006.201.13:54:13.49#ibcon#end of sib2, iclass 26, count 0 2006.201.13:54:13.49#ibcon#*mode == 0, iclass 26, count 0 2006.201.13:54:13.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.13:54:13.49#ibcon#[25=USB\r\n] 2006.201.13:54:13.49#ibcon#*before write, iclass 26, count 0 2006.201.13:54:13.49#ibcon#enter sib2, iclass 26, count 0 2006.201.13:54:13.49#ibcon#flushed, iclass 26, count 0 2006.201.13:54:13.49#ibcon#about to write, iclass 26, count 0 2006.201.13:54:13.49#ibcon#wrote, iclass 26, count 0 2006.201.13:54:13.49#ibcon#about to read 3, iclass 26, count 0 2006.201.13:54:13.52#ibcon#read 3, iclass 26, count 0 2006.201.13:54:13.52#ibcon#about to read 4, iclass 26, count 0 2006.201.13:54:13.52#ibcon#read 4, iclass 26, count 0 2006.201.13:54:13.52#ibcon#about to read 5, iclass 26, count 0 2006.201.13:54:13.52#ibcon#read 5, iclass 26, count 0 2006.201.13:54:13.52#ibcon#about to read 6, iclass 26, count 0 2006.201.13:54:13.52#ibcon#read 6, iclass 26, count 0 2006.201.13:54:13.52#ibcon#end of sib2, iclass 26, count 0 2006.201.13:54:13.52#ibcon#*after write, iclass 26, count 0 2006.201.13:54:13.52#ibcon#*before return 0, iclass 26, count 0 2006.201.13:54:13.52#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:13.52#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:13.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.13:54:13.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.13:54:13.52$vck44/valo=3,564.99 2006.201.13:54:13.52#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.13:54:13.52#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.13:54:13.52#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:13.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:13.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:13.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:13.52#ibcon#enter wrdev, iclass 28, count 0 2006.201.13:54:13.52#ibcon#first serial, iclass 28, count 0 2006.201.13:54:13.52#ibcon#enter sib2, iclass 28, count 0 2006.201.13:54:13.52#ibcon#flushed, iclass 28, count 0 2006.201.13:54:13.52#ibcon#about to write, iclass 28, count 0 2006.201.13:54:13.52#ibcon#wrote, iclass 28, count 0 2006.201.13:54:13.52#ibcon#about to read 3, iclass 28, count 0 2006.201.13:54:13.54#ibcon#read 3, iclass 28, count 0 2006.201.13:54:13.54#ibcon#about to read 4, iclass 28, count 0 2006.201.13:54:13.54#ibcon#read 4, iclass 28, count 0 2006.201.13:54:13.54#ibcon#about to read 5, iclass 28, count 0 2006.201.13:54:13.54#ibcon#read 5, iclass 28, count 0 2006.201.13:54:13.54#ibcon#about to read 6, iclass 28, count 0 2006.201.13:54:13.54#ibcon#read 6, iclass 28, count 0 2006.201.13:54:13.54#ibcon#end of sib2, iclass 28, count 0 2006.201.13:54:13.54#ibcon#*mode == 0, iclass 28, count 0 2006.201.13:54:13.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.13:54:13.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:54:13.54#ibcon#*before write, iclass 28, count 0 2006.201.13:54:13.54#ibcon#enter sib2, iclass 28, count 0 2006.201.13:54:13.54#ibcon#flushed, iclass 28, count 0 2006.201.13:54:13.54#ibcon#about to write, iclass 28, count 0 2006.201.13:54:13.54#ibcon#wrote, iclass 28, count 0 2006.201.13:54:13.54#ibcon#about to read 3, iclass 28, count 0 2006.201.13:54:13.59#ibcon#read 3, iclass 28, count 0 2006.201.13:54:13.59#ibcon#about to read 4, iclass 28, count 0 2006.201.13:54:13.59#ibcon#read 4, iclass 28, count 0 2006.201.13:54:13.59#ibcon#about to read 5, iclass 28, count 0 2006.201.13:54:13.59#ibcon#read 5, iclass 28, count 0 2006.201.13:54:13.59#ibcon#about to read 6, iclass 28, count 0 2006.201.13:54:13.59#ibcon#read 6, iclass 28, count 0 2006.201.13:54:13.59#ibcon#end of sib2, iclass 28, count 0 2006.201.13:54:13.59#ibcon#*after write, iclass 28, count 0 2006.201.13:54:13.59#ibcon#*before return 0, iclass 28, count 0 2006.201.13:54:13.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:13.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:13.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.13:54:13.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.13:54:13.59$vck44/va=3,8 2006.201.13:54:13.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.13:54:13.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.13:54:13.59#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:13.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:13.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:13.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:13.64#ibcon#enter wrdev, iclass 30, count 2 2006.201.13:54:13.64#ibcon#first serial, iclass 30, count 2 2006.201.13:54:13.64#ibcon#enter sib2, iclass 30, count 2 2006.201.13:54:13.64#ibcon#flushed, iclass 30, count 2 2006.201.13:54:13.64#ibcon#about to write, iclass 30, count 2 2006.201.13:54:13.64#ibcon#wrote, iclass 30, count 2 2006.201.13:54:13.64#ibcon#about to read 3, iclass 30, count 2 2006.201.13:54:13.66#ibcon#read 3, iclass 30, count 2 2006.201.13:54:13.66#ibcon#about to read 4, iclass 30, count 2 2006.201.13:54:13.66#ibcon#read 4, iclass 30, count 2 2006.201.13:54:13.66#ibcon#about to read 5, iclass 30, count 2 2006.201.13:54:13.66#ibcon#read 5, iclass 30, count 2 2006.201.13:54:13.66#ibcon#about to read 6, iclass 30, count 2 2006.201.13:54:13.66#ibcon#read 6, iclass 30, count 2 2006.201.13:54:13.66#ibcon#end of sib2, iclass 30, count 2 2006.201.13:54:13.66#ibcon#*mode == 0, iclass 30, count 2 2006.201.13:54:13.66#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.13:54:13.66#ibcon#[25=AT03-08\r\n] 2006.201.13:54:13.66#ibcon#*before write, iclass 30, count 2 2006.201.13:54:13.66#ibcon#enter sib2, iclass 30, count 2 2006.201.13:54:13.66#ibcon#flushed, iclass 30, count 2 2006.201.13:54:13.66#ibcon#about to write, iclass 30, count 2 2006.201.13:54:13.66#ibcon#wrote, iclass 30, count 2 2006.201.13:54:13.66#ibcon#about to read 3, iclass 30, count 2 2006.201.13:54:13.69#ibcon#read 3, iclass 30, count 2 2006.201.13:54:13.69#ibcon#about to read 4, iclass 30, count 2 2006.201.13:54:13.69#ibcon#read 4, iclass 30, count 2 2006.201.13:54:13.69#ibcon#about to read 5, iclass 30, count 2 2006.201.13:54:13.69#ibcon#read 5, iclass 30, count 2 2006.201.13:54:13.69#ibcon#about to read 6, iclass 30, count 2 2006.201.13:54:13.69#ibcon#read 6, iclass 30, count 2 2006.201.13:54:13.69#ibcon#end of sib2, iclass 30, count 2 2006.201.13:54:13.69#ibcon#*after write, iclass 30, count 2 2006.201.13:54:13.69#ibcon#*before return 0, iclass 30, count 2 2006.201.13:54:13.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:13.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:13.69#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.13:54:13.69#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:13.69#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:13.81#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:13.81#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:13.81#ibcon#enter wrdev, iclass 30, count 0 2006.201.13:54:13.81#ibcon#first serial, iclass 30, count 0 2006.201.13:54:13.81#ibcon#enter sib2, iclass 30, count 0 2006.201.13:54:13.81#ibcon#flushed, iclass 30, count 0 2006.201.13:54:13.81#ibcon#about to write, iclass 30, count 0 2006.201.13:54:13.81#ibcon#wrote, iclass 30, count 0 2006.201.13:54:13.81#ibcon#about to read 3, iclass 30, count 0 2006.201.13:54:13.83#ibcon#read 3, iclass 30, count 0 2006.201.13:54:13.83#ibcon#about to read 4, iclass 30, count 0 2006.201.13:54:13.83#ibcon#read 4, iclass 30, count 0 2006.201.13:54:13.83#ibcon#about to read 5, iclass 30, count 0 2006.201.13:54:13.83#ibcon#read 5, iclass 30, count 0 2006.201.13:54:13.83#ibcon#about to read 6, iclass 30, count 0 2006.201.13:54:13.83#ibcon#read 6, iclass 30, count 0 2006.201.13:54:13.83#ibcon#end of sib2, iclass 30, count 0 2006.201.13:54:13.83#ibcon#*mode == 0, iclass 30, count 0 2006.201.13:54:13.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.13:54:13.83#ibcon#[25=USB\r\n] 2006.201.13:54:13.83#ibcon#*before write, iclass 30, count 0 2006.201.13:54:13.83#ibcon#enter sib2, iclass 30, count 0 2006.201.13:54:13.83#ibcon#flushed, iclass 30, count 0 2006.201.13:54:13.83#ibcon#about to write, iclass 30, count 0 2006.201.13:54:13.83#ibcon#wrote, iclass 30, count 0 2006.201.13:54:13.83#ibcon#about to read 3, iclass 30, count 0 2006.201.13:54:13.86#ibcon#read 3, iclass 30, count 0 2006.201.13:54:13.86#ibcon#about to read 4, iclass 30, count 0 2006.201.13:54:13.86#ibcon#read 4, iclass 30, count 0 2006.201.13:54:13.86#ibcon#about to read 5, iclass 30, count 0 2006.201.13:54:13.86#ibcon#read 5, iclass 30, count 0 2006.201.13:54:13.86#ibcon#about to read 6, iclass 30, count 0 2006.201.13:54:13.86#ibcon#read 6, iclass 30, count 0 2006.201.13:54:13.86#ibcon#end of sib2, iclass 30, count 0 2006.201.13:54:13.86#ibcon#*after write, iclass 30, count 0 2006.201.13:54:13.86#ibcon#*before return 0, iclass 30, count 0 2006.201.13:54:13.86#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:13.86#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:13.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.13:54:13.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.13:54:13.86$vck44/valo=4,624.99 2006.201.13:54:13.86#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.13:54:13.86#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.13:54:13.86#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:13.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:54:13.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:54:13.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:54:13.86#ibcon#enter wrdev, iclass 32, count 0 2006.201.13:54:13.86#ibcon#first serial, iclass 32, count 0 2006.201.13:54:13.86#ibcon#enter sib2, iclass 32, count 0 2006.201.13:54:13.86#ibcon#flushed, iclass 32, count 0 2006.201.13:54:13.86#ibcon#about to write, iclass 32, count 0 2006.201.13:54:13.86#ibcon#wrote, iclass 32, count 0 2006.201.13:54:13.86#ibcon#about to read 3, iclass 32, count 0 2006.201.13:54:13.88#ibcon#read 3, iclass 32, count 0 2006.201.13:54:13.88#ibcon#about to read 4, iclass 32, count 0 2006.201.13:54:13.88#ibcon#read 4, iclass 32, count 0 2006.201.13:54:13.88#ibcon#about to read 5, iclass 32, count 0 2006.201.13:54:13.88#ibcon#read 5, iclass 32, count 0 2006.201.13:54:13.88#ibcon#about to read 6, iclass 32, count 0 2006.201.13:54:13.88#ibcon#read 6, iclass 32, count 0 2006.201.13:54:13.88#ibcon#end of sib2, iclass 32, count 0 2006.201.13:54:13.88#ibcon#*mode == 0, iclass 32, count 0 2006.201.13:54:13.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.13:54:13.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:54:13.88#ibcon#*before write, iclass 32, count 0 2006.201.13:54:13.88#ibcon#enter sib2, iclass 32, count 0 2006.201.13:54:13.88#ibcon#flushed, iclass 32, count 0 2006.201.13:54:13.88#ibcon#about to write, iclass 32, count 0 2006.201.13:54:13.88#ibcon#wrote, iclass 32, count 0 2006.201.13:54:13.88#ibcon#about to read 3, iclass 32, count 0 2006.201.13:54:13.93#ibcon#read 3, iclass 32, count 0 2006.201.13:54:13.93#ibcon#about to read 4, iclass 32, count 0 2006.201.13:54:13.93#ibcon#read 4, iclass 32, count 0 2006.201.13:54:13.93#ibcon#about to read 5, iclass 32, count 0 2006.201.13:54:13.93#ibcon#read 5, iclass 32, count 0 2006.201.13:54:13.93#ibcon#about to read 6, iclass 32, count 0 2006.201.13:54:13.93#ibcon#read 6, iclass 32, count 0 2006.201.13:54:13.93#ibcon#end of sib2, iclass 32, count 0 2006.201.13:54:13.93#ibcon#*after write, iclass 32, count 0 2006.201.13:54:13.93#ibcon#*before return 0, iclass 32, count 0 2006.201.13:54:13.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:54:13.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.13:54:13.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.13:54:13.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.13:54:13.93$vck44/va=4,7 2006.201.13:54:13.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.13:54:13.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.13:54:13.93#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:13.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:54:13.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:54:13.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:54:13.98#ibcon#enter wrdev, iclass 34, count 2 2006.201.13:54:13.98#ibcon#first serial, iclass 34, count 2 2006.201.13:54:13.98#ibcon#enter sib2, iclass 34, count 2 2006.201.13:54:13.98#ibcon#flushed, iclass 34, count 2 2006.201.13:54:13.98#ibcon#about to write, iclass 34, count 2 2006.201.13:54:13.98#ibcon#wrote, iclass 34, count 2 2006.201.13:54:13.98#ibcon#about to read 3, iclass 34, count 2 2006.201.13:54:14.00#ibcon#read 3, iclass 34, count 2 2006.201.13:54:14.00#ibcon#about to read 4, iclass 34, count 2 2006.201.13:54:14.00#ibcon#read 4, iclass 34, count 2 2006.201.13:54:14.00#ibcon#about to read 5, iclass 34, count 2 2006.201.13:54:14.00#ibcon#read 5, iclass 34, count 2 2006.201.13:54:14.00#ibcon#about to read 6, iclass 34, count 2 2006.201.13:54:14.00#ibcon#read 6, iclass 34, count 2 2006.201.13:54:14.00#ibcon#end of sib2, iclass 34, count 2 2006.201.13:54:14.00#ibcon#*mode == 0, iclass 34, count 2 2006.201.13:54:14.00#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.13:54:14.00#ibcon#[25=AT04-07\r\n] 2006.201.13:54:14.00#ibcon#*before write, iclass 34, count 2 2006.201.13:54:14.00#ibcon#enter sib2, iclass 34, count 2 2006.201.13:54:14.00#ibcon#flushed, iclass 34, count 2 2006.201.13:54:14.00#ibcon#about to write, iclass 34, count 2 2006.201.13:54:14.00#ibcon#wrote, iclass 34, count 2 2006.201.13:54:14.00#ibcon#about to read 3, iclass 34, count 2 2006.201.13:54:14.03#ibcon#read 3, iclass 34, count 2 2006.201.13:54:14.03#ibcon#about to read 4, iclass 34, count 2 2006.201.13:54:14.03#ibcon#read 4, iclass 34, count 2 2006.201.13:54:14.03#ibcon#about to read 5, iclass 34, count 2 2006.201.13:54:14.03#ibcon#read 5, iclass 34, count 2 2006.201.13:54:14.03#ibcon#about to read 6, iclass 34, count 2 2006.201.13:54:14.03#ibcon#read 6, iclass 34, count 2 2006.201.13:54:14.03#ibcon#end of sib2, iclass 34, count 2 2006.201.13:54:14.03#ibcon#*after write, iclass 34, count 2 2006.201.13:54:14.03#ibcon#*before return 0, iclass 34, count 2 2006.201.13:54:14.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:54:14.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.13:54:14.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.13:54:14.03#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:14.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:54:14.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:54:14.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:54:14.15#ibcon#enter wrdev, iclass 34, count 0 2006.201.13:54:14.15#ibcon#first serial, iclass 34, count 0 2006.201.13:54:14.15#ibcon#enter sib2, iclass 34, count 0 2006.201.13:54:14.15#ibcon#flushed, iclass 34, count 0 2006.201.13:54:14.15#ibcon#about to write, iclass 34, count 0 2006.201.13:54:14.15#ibcon#wrote, iclass 34, count 0 2006.201.13:54:14.15#ibcon#about to read 3, iclass 34, count 0 2006.201.13:54:14.17#ibcon#read 3, iclass 34, count 0 2006.201.13:54:14.17#ibcon#about to read 4, iclass 34, count 0 2006.201.13:54:14.17#ibcon#read 4, iclass 34, count 0 2006.201.13:54:14.17#ibcon#about to read 5, iclass 34, count 0 2006.201.13:54:14.17#ibcon#read 5, iclass 34, count 0 2006.201.13:54:14.17#ibcon#about to read 6, iclass 34, count 0 2006.201.13:54:14.17#ibcon#read 6, iclass 34, count 0 2006.201.13:54:14.17#ibcon#end of sib2, iclass 34, count 0 2006.201.13:54:14.17#ibcon#*mode == 0, iclass 34, count 0 2006.201.13:54:14.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.13:54:14.17#ibcon#[25=USB\r\n] 2006.201.13:54:14.17#ibcon#*before write, iclass 34, count 0 2006.201.13:54:14.17#ibcon#enter sib2, iclass 34, count 0 2006.201.13:54:14.17#ibcon#flushed, iclass 34, count 0 2006.201.13:54:14.17#ibcon#about to write, iclass 34, count 0 2006.201.13:54:14.17#ibcon#wrote, iclass 34, count 0 2006.201.13:54:14.17#ibcon#about to read 3, iclass 34, count 0 2006.201.13:54:14.20#ibcon#read 3, iclass 34, count 0 2006.201.13:54:14.20#ibcon#about to read 4, iclass 34, count 0 2006.201.13:54:14.20#ibcon#read 4, iclass 34, count 0 2006.201.13:54:14.20#ibcon#about to read 5, iclass 34, count 0 2006.201.13:54:14.20#ibcon#read 5, iclass 34, count 0 2006.201.13:54:14.20#ibcon#about to read 6, iclass 34, count 0 2006.201.13:54:14.20#ibcon#read 6, iclass 34, count 0 2006.201.13:54:14.20#ibcon#end of sib2, iclass 34, count 0 2006.201.13:54:14.20#ibcon#*after write, iclass 34, count 0 2006.201.13:54:14.20#ibcon#*before return 0, iclass 34, count 0 2006.201.13:54:14.20#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:54:14.20#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.13:54:14.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.13:54:14.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.13:54:14.20$vck44/valo=5,734.99 2006.201.13:54:14.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.13:54:14.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.13:54:14.20#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:14.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:14.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:14.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:14.20#ibcon#enter wrdev, iclass 36, count 0 2006.201.13:54:14.20#ibcon#first serial, iclass 36, count 0 2006.201.13:54:14.20#ibcon#enter sib2, iclass 36, count 0 2006.201.13:54:14.20#ibcon#flushed, iclass 36, count 0 2006.201.13:54:14.20#ibcon#about to write, iclass 36, count 0 2006.201.13:54:14.20#ibcon#wrote, iclass 36, count 0 2006.201.13:54:14.20#ibcon#about to read 3, iclass 36, count 0 2006.201.13:54:14.22#ibcon#read 3, iclass 36, count 0 2006.201.13:54:14.22#ibcon#about to read 4, iclass 36, count 0 2006.201.13:54:14.22#ibcon#read 4, iclass 36, count 0 2006.201.13:54:14.22#ibcon#about to read 5, iclass 36, count 0 2006.201.13:54:14.22#ibcon#read 5, iclass 36, count 0 2006.201.13:54:14.22#ibcon#about to read 6, iclass 36, count 0 2006.201.13:54:14.22#ibcon#read 6, iclass 36, count 0 2006.201.13:54:14.22#ibcon#end of sib2, iclass 36, count 0 2006.201.13:54:14.22#ibcon#*mode == 0, iclass 36, count 0 2006.201.13:54:14.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.13:54:14.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:54:14.22#ibcon#*before write, iclass 36, count 0 2006.201.13:54:14.22#ibcon#enter sib2, iclass 36, count 0 2006.201.13:54:14.22#ibcon#flushed, iclass 36, count 0 2006.201.13:54:14.22#ibcon#about to write, iclass 36, count 0 2006.201.13:54:14.22#ibcon#wrote, iclass 36, count 0 2006.201.13:54:14.22#ibcon#about to read 3, iclass 36, count 0 2006.201.13:54:14.26#ibcon#read 3, iclass 36, count 0 2006.201.13:54:14.26#ibcon#about to read 4, iclass 36, count 0 2006.201.13:54:14.26#ibcon#read 4, iclass 36, count 0 2006.201.13:54:14.26#ibcon#about to read 5, iclass 36, count 0 2006.201.13:54:14.26#ibcon#read 5, iclass 36, count 0 2006.201.13:54:14.26#ibcon#about to read 6, iclass 36, count 0 2006.201.13:54:14.26#ibcon#read 6, iclass 36, count 0 2006.201.13:54:14.26#ibcon#end of sib2, iclass 36, count 0 2006.201.13:54:14.26#ibcon#*after write, iclass 36, count 0 2006.201.13:54:14.26#ibcon#*before return 0, iclass 36, count 0 2006.201.13:54:14.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:14.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:14.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.13:54:14.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.13:54:14.26$vck44/va=5,4 2006.201.13:54:14.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.13:54:14.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.13:54:14.26#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:14.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:14.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:14.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:14.32#ibcon#enter wrdev, iclass 38, count 2 2006.201.13:54:14.32#ibcon#first serial, iclass 38, count 2 2006.201.13:54:14.32#ibcon#enter sib2, iclass 38, count 2 2006.201.13:54:14.32#ibcon#flushed, iclass 38, count 2 2006.201.13:54:14.32#ibcon#about to write, iclass 38, count 2 2006.201.13:54:14.32#ibcon#wrote, iclass 38, count 2 2006.201.13:54:14.32#ibcon#about to read 3, iclass 38, count 2 2006.201.13:54:14.34#ibcon#read 3, iclass 38, count 2 2006.201.13:54:14.34#ibcon#about to read 4, iclass 38, count 2 2006.201.13:54:14.34#ibcon#read 4, iclass 38, count 2 2006.201.13:54:14.34#ibcon#about to read 5, iclass 38, count 2 2006.201.13:54:14.34#ibcon#read 5, iclass 38, count 2 2006.201.13:54:14.34#ibcon#about to read 6, iclass 38, count 2 2006.201.13:54:14.34#ibcon#read 6, iclass 38, count 2 2006.201.13:54:14.34#ibcon#end of sib2, iclass 38, count 2 2006.201.13:54:14.34#ibcon#*mode == 0, iclass 38, count 2 2006.201.13:54:14.34#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.13:54:14.34#ibcon#[25=AT05-04\r\n] 2006.201.13:54:14.34#ibcon#*before write, iclass 38, count 2 2006.201.13:54:14.34#ibcon#enter sib2, iclass 38, count 2 2006.201.13:54:14.34#ibcon#flushed, iclass 38, count 2 2006.201.13:54:14.34#ibcon#about to write, iclass 38, count 2 2006.201.13:54:14.34#ibcon#wrote, iclass 38, count 2 2006.201.13:54:14.34#ibcon#about to read 3, iclass 38, count 2 2006.201.13:54:14.37#ibcon#read 3, iclass 38, count 2 2006.201.13:54:14.37#ibcon#about to read 4, iclass 38, count 2 2006.201.13:54:14.37#ibcon#read 4, iclass 38, count 2 2006.201.13:54:14.37#ibcon#about to read 5, iclass 38, count 2 2006.201.13:54:14.37#ibcon#read 5, iclass 38, count 2 2006.201.13:54:14.37#ibcon#about to read 6, iclass 38, count 2 2006.201.13:54:14.37#ibcon#read 6, iclass 38, count 2 2006.201.13:54:14.37#ibcon#end of sib2, iclass 38, count 2 2006.201.13:54:14.37#ibcon#*after write, iclass 38, count 2 2006.201.13:54:14.37#ibcon#*before return 0, iclass 38, count 2 2006.201.13:54:14.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:14.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:14.37#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.13:54:14.37#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:14.37#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:14.49#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:14.49#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:14.49#ibcon#enter wrdev, iclass 38, count 0 2006.201.13:54:14.49#ibcon#first serial, iclass 38, count 0 2006.201.13:54:14.49#ibcon#enter sib2, iclass 38, count 0 2006.201.13:54:14.49#ibcon#flushed, iclass 38, count 0 2006.201.13:54:14.49#ibcon#about to write, iclass 38, count 0 2006.201.13:54:14.49#ibcon#wrote, iclass 38, count 0 2006.201.13:54:14.49#ibcon#about to read 3, iclass 38, count 0 2006.201.13:54:14.51#ibcon#read 3, iclass 38, count 0 2006.201.13:54:14.51#ibcon#about to read 4, iclass 38, count 0 2006.201.13:54:14.51#ibcon#read 4, iclass 38, count 0 2006.201.13:54:14.51#ibcon#about to read 5, iclass 38, count 0 2006.201.13:54:14.51#ibcon#read 5, iclass 38, count 0 2006.201.13:54:14.51#ibcon#about to read 6, iclass 38, count 0 2006.201.13:54:14.51#ibcon#read 6, iclass 38, count 0 2006.201.13:54:14.51#ibcon#end of sib2, iclass 38, count 0 2006.201.13:54:14.51#ibcon#*mode == 0, iclass 38, count 0 2006.201.13:54:14.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.13:54:14.51#ibcon#[25=USB\r\n] 2006.201.13:54:14.51#ibcon#*before write, iclass 38, count 0 2006.201.13:54:14.51#ibcon#enter sib2, iclass 38, count 0 2006.201.13:54:14.51#ibcon#flushed, iclass 38, count 0 2006.201.13:54:14.51#ibcon#about to write, iclass 38, count 0 2006.201.13:54:14.51#ibcon#wrote, iclass 38, count 0 2006.201.13:54:14.51#ibcon#about to read 3, iclass 38, count 0 2006.201.13:54:14.54#ibcon#read 3, iclass 38, count 0 2006.201.13:54:14.54#ibcon#about to read 4, iclass 38, count 0 2006.201.13:54:14.54#ibcon#read 4, iclass 38, count 0 2006.201.13:54:14.54#ibcon#about to read 5, iclass 38, count 0 2006.201.13:54:14.54#ibcon#read 5, iclass 38, count 0 2006.201.13:54:14.54#ibcon#about to read 6, iclass 38, count 0 2006.201.13:54:14.54#ibcon#read 6, iclass 38, count 0 2006.201.13:54:14.54#ibcon#end of sib2, iclass 38, count 0 2006.201.13:54:14.54#ibcon#*after write, iclass 38, count 0 2006.201.13:54:14.54#ibcon#*before return 0, iclass 38, count 0 2006.201.13:54:14.54#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:14.54#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:14.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.13:54:14.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.13:54:14.54$vck44/valo=6,814.99 2006.201.13:54:14.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.13:54:14.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.13:54:14.54#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:14.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:14.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:14.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:14.54#ibcon#enter wrdev, iclass 40, count 0 2006.201.13:54:14.54#ibcon#first serial, iclass 40, count 0 2006.201.13:54:14.54#ibcon#enter sib2, iclass 40, count 0 2006.201.13:54:14.54#ibcon#flushed, iclass 40, count 0 2006.201.13:54:14.54#ibcon#about to write, iclass 40, count 0 2006.201.13:54:14.54#ibcon#wrote, iclass 40, count 0 2006.201.13:54:14.54#ibcon#about to read 3, iclass 40, count 0 2006.201.13:54:14.56#ibcon#read 3, iclass 40, count 0 2006.201.13:54:14.56#ibcon#about to read 4, iclass 40, count 0 2006.201.13:54:14.56#ibcon#read 4, iclass 40, count 0 2006.201.13:54:14.56#ibcon#about to read 5, iclass 40, count 0 2006.201.13:54:14.56#ibcon#read 5, iclass 40, count 0 2006.201.13:54:14.56#ibcon#about to read 6, iclass 40, count 0 2006.201.13:54:14.56#ibcon#read 6, iclass 40, count 0 2006.201.13:54:14.56#ibcon#end of sib2, iclass 40, count 0 2006.201.13:54:14.56#ibcon#*mode == 0, iclass 40, count 0 2006.201.13:54:14.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.13:54:14.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:54:14.56#ibcon#*before write, iclass 40, count 0 2006.201.13:54:14.56#ibcon#enter sib2, iclass 40, count 0 2006.201.13:54:14.56#ibcon#flushed, iclass 40, count 0 2006.201.13:54:14.56#ibcon#about to write, iclass 40, count 0 2006.201.13:54:14.56#ibcon#wrote, iclass 40, count 0 2006.201.13:54:14.56#ibcon#about to read 3, iclass 40, count 0 2006.201.13:54:14.61#ibcon#read 3, iclass 40, count 0 2006.201.13:54:14.61#ibcon#about to read 4, iclass 40, count 0 2006.201.13:54:14.61#ibcon#read 4, iclass 40, count 0 2006.201.13:54:14.61#ibcon#about to read 5, iclass 40, count 0 2006.201.13:54:14.61#ibcon#read 5, iclass 40, count 0 2006.201.13:54:14.61#ibcon#about to read 6, iclass 40, count 0 2006.201.13:54:14.61#ibcon#read 6, iclass 40, count 0 2006.201.13:54:14.61#ibcon#end of sib2, iclass 40, count 0 2006.201.13:54:14.61#ibcon#*after write, iclass 40, count 0 2006.201.13:54:14.61#ibcon#*before return 0, iclass 40, count 0 2006.201.13:54:14.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:14.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:14.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.13:54:14.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.13:54:14.61$vck44/va=6,5 2006.201.13:54:14.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.13:54:14.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.13:54:14.61#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:14.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:14.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:14.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:14.66#ibcon#enter wrdev, iclass 4, count 2 2006.201.13:54:14.66#ibcon#first serial, iclass 4, count 2 2006.201.13:54:14.66#ibcon#enter sib2, iclass 4, count 2 2006.201.13:54:14.66#ibcon#flushed, iclass 4, count 2 2006.201.13:54:14.66#ibcon#about to write, iclass 4, count 2 2006.201.13:54:14.66#ibcon#wrote, iclass 4, count 2 2006.201.13:54:14.66#ibcon#about to read 3, iclass 4, count 2 2006.201.13:54:14.68#ibcon#read 3, iclass 4, count 2 2006.201.13:54:14.68#ibcon#about to read 4, iclass 4, count 2 2006.201.13:54:14.68#ibcon#read 4, iclass 4, count 2 2006.201.13:54:14.68#ibcon#about to read 5, iclass 4, count 2 2006.201.13:54:14.68#ibcon#read 5, iclass 4, count 2 2006.201.13:54:14.68#ibcon#about to read 6, iclass 4, count 2 2006.201.13:54:14.68#ibcon#read 6, iclass 4, count 2 2006.201.13:54:14.68#ibcon#end of sib2, iclass 4, count 2 2006.201.13:54:14.68#ibcon#*mode == 0, iclass 4, count 2 2006.201.13:54:14.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.13:54:14.68#ibcon#[25=AT06-05\r\n] 2006.201.13:54:14.68#ibcon#*before write, iclass 4, count 2 2006.201.13:54:14.68#ibcon#enter sib2, iclass 4, count 2 2006.201.13:54:14.68#ibcon#flushed, iclass 4, count 2 2006.201.13:54:14.68#ibcon#about to write, iclass 4, count 2 2006.201.13:54:14.68#ibcon#wrote, iclass 4, count 2 2006.201.13:54:14.68#ibcon#about to read 3, iclass 4, count 2 2006.201.13:54:14.71#ibcon#read 3, iclass 4, count 2 2006.201.13:54:14.71#ibcon#about to read 4, iclass 4, count 2 2006.201.13:54:14.71#ibcon#read 4, iclass 4, count 2 2006.201.13:54:14.71#ibcon#about to read 5, iclass 4, count 2 2006.201.13:54:14.71#ibcon#read 5, iclass 4, count 2 2006.201.13:54:14.71#ibcon#about to read 6, iclass 4, count 2 2006.201.13:54:14.71#ibcon#read 6, iclass 4, count 2 2006.201.13:54:14.71#ibcon#end of sib2, iclass 4, count 2 2006.201.13:54:14.71#ibcon#*after write, iclass 4, count 2 2006.201.13:54:14.71#ibcon#*before return 0, iclass 4, count 2 2006.201.13:54:14.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:14.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:14.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.13:54:14.71#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:14.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:14.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:14.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:14.83#ibcon#enter wrdev, iclass 4, count 0 2006.201.13:54:14.83#ibcon#first serial, iclass 4, count 0 2006.201.13:54:14.83#ibcon#enter sib2, iclass 4, count 0 2006.201.13:54:14.83#ibcon#flushed, iclass 4, count 0 2006.201.13:54:14.83#ibcon#about to write, iclass 4, count 0 2006.201.13:54:14.83#ibcon#wrote, iclass 4, count 0 2006.201.13:54:14.83#ibcon#about to read 3, iclass 4, count 0 2006.201.13:54:14.85#ibcon#read 3, iclass 4, count 0 2006.201.13:54:14.85#ibcon#about to read 4, iclass 4, count 0 2006.201.13:54:14.85#ibcon#read 4, iclass 4, count 0 2006.201.13:54:14.85#ibcon#about to read 5, iclass 4, count 0 2006.201.13:54:14.85#ibcon#read 5, iclass 4, count 0 2006.201.13:54:14.85#ibcon#about to read 6, iclass 4, count 0 2006.201.13:54:14.85#ibcon#read 6, iclass 4, count 0 2006.201.13:54:14.85#ibcon#end of sib2, iclass 4, count 0 2006.201.13:54:14.85#ibcon#*mode == 0, iclass 4, count 0 2006.201.13:54:14.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.13:54:14.85#ibcon#[25=USB\r\n] 2006.201.13:54:14.85#ibcon#*before write, iclass 4, count 0 2006.201.13:54:14.85#ibcon#enter sib2, iclass 4, count 0 2006.201.13:54:14.85#ibcon#flushed, iclass 4, count 0 2006.201.13:54:14.85#ibcon#about to write, iclass 4, count 0 2006.201.13:54:14.85#ibcon#wrote, iclass 4, count 0 2006.201.13:54:14.85#ibcon#about to read 3, iclass 4, count 0 2006.201.13:54:14.88#ibcon#read 3, iclass 4, count 0 2006.201.13:54:14.88#ibcon#about to read 4, iclass 4, count 0 2006.201.13:54:14.88#ibcon#read 4, iclass 4, count 0 2006.201.13:54:14.88#ibcon#about to read 5, iclass 4, count 0 2006.201.13:54:14.88#ibcon#read 5, iclass 4, count 0 2006.201.13:54:14.88#ibcon#about to read 6, iclass 4, count 0 2006.201.13:54:14.88#ibcon#read 6, iclass 4, count 0 2006.201.13:54:14.88#ibcon#end of sib2, iclass 4, count 0 2006.201.13:54:14.88#ibcon#*after write, iclass 4, count 0 2006.201.13:54:14.88#ibcon#*before return 0, iclass 4, count 0 2006.201.13:54:14.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:14.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:14.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.13:54:14.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.13:54:14.88$vck44/valo=7,864.99 2006.201.13:54:14.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.13:54:14.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.13:54:14.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:14.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:14.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:14.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:14.88#ibcon#enter wrdev, iclass 6, count 0 2006.201.13:54:14.88#ibcon#first serial, iclass 6, count 0 2006.201.13:54:14.88#ibcon#enter sib2, iclass 6, count 0 2006.201.13:54:14.88#ibcon#flushed, iclass 6, count 0 2006.201.13:54:14.88#ibcon#about to write, iclass 6, count 0 2006.201.13:54:14.88#ibcon#wrote, iclass 6, count 0 2006.201.13:54:14.88#ibcon#about to read 3, iclass 6, count 0 2006.201.13:54:14.90#ibcon#read 3, iclass 6, count 0 2006.201.13:54:14.90#ibcon#about to read 4, iclass 6, count 0 2006.201.13:54:14.90#ibcon#read 4, iclass 6, count 0 2006.201.13:54:14.90#ibcon#about to read 5, iclass 6, count 0 2006.201.13:54:14.90#ibcon#read 5, iclass 6, count 0 2006.201.13:54:14.90#ibcon#about to read 6, iclass 6, count 0 2006.201.13:54:14.90#ibcon#read 6, iclass 6, count 0 2006.201.13:54:14.90#ibcon#end of sib2, iclass 6, count 0 2006.201.13:54:14.90#ibcon#*mode == 0, iclass 6, count 0 2006.201.13:54:14.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.13:54:14.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:54:14.90#ibcon#*before write, iclass 6, count 0 2006.201.13:54:14.90#ibcon#enter sib2, iclass 6, count 0 2006.201.13:54:14.90#ibcon#flushed, iclass 6, count 0 2006.201.13:54:14.90#ibcon#about to write, iclass 6, count 0 2006.201.13:54:14.90#ibcon#wrote, iclass 6, count 0 2006.201.13:54:14.90#ibcon#about to read 3, iclass 6, count 0 2006.201.13:54:14.94#ibcon#read 3, iclass 6, count 0 2006.201.13:54:14.94#ibcon#about to read 4, iclass 6, count 0 2006.201.13:54:14.94#ibcon#read 4, iclass 6, count 0 2006.201.13:54:14.94#ibcon#about to read 5, iclass 6, count 0 2006.201.13:54:14.94#ibcon#read 5, iclass 6, count 0 2006.201.13:54:14.94#ibcon#about to read 6, iclass 6, count 0 2006.201.13:54:14.94#ibcon#read 6, iclass 6, count 0 2006.201.13:54:14.94#ibcon#end of sib2, iclass 6, count 0 2006.201.13:54:14.94#ibcon#*after write, iclass 6, count 0 2006.201.13:54:14.94#ibcon#*before return 0, iclass 6, count 0 2006.201.13:54:14.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:14.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:14.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.13:54:14.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.13:54:14.94$vck44/va=7,5 2006.201.13:54:14.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.13:54:14.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.13:54:14.94#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:14.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:15.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:15.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:15.00#ibcon#enter wrdev, iclass 10, count 2 2006.201.13:54:15.00#ibcon#first serial, iclass 10, count 2 2006.201.13:54:15.00#ibcon#enter sib2, iclass 10, count 2 2006.201.13:54:15.00#ibcon#flushed, iclass 10, count 2 2006.201.13:54:15.00#ibcon#about to write, iclass 10, count 2 2006.201.13:54:15.00#ibcon#wrote, iclass 10, count 2 2006.201.13:54:15.00#ibcon#about to read 3, iclass 10, count 2 2006.201.13:54:15.02#ibcon#read 3, iclass 10, count 2 2006.201.13:54:15.02#ibcon#about to read 4, iclass 10, count 2 2006.201.13:54:15.02#ibcon#read 4, iclass 10, count 2 2006.201.13:54:15.02#ibcon#about to read 5, iclass 10, count 2 2006.201.13:54:15.02#ibcon#read 5, iclass 10, count 2 2006.201.13:54:15.02#ibcon#about to read 6, iclass 10, count 2 2006.201.13:54:15.02#ibcon#read 6, iclass 10, count 2 2006.201.13:54:15.02#ibcon#end of sib2, iclass 10, count 2 2006.201.13:54:15.02#ibcon#*mode == 0, iclass 10, count 2 2006.201.13:54:15.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.13:54:15.02#ibcon#[25=AT07-05\r\n] 2006.201.13:54:15.02#ibcon#*before write, iclass 10, count 2 2006.201.13:54:15.02#ibcon#enter sib2, iclass 10, count 2 2006.201.13:54:15.02#ibcon#flushed, iclass 10, count 2 2006.201.13:54:15.02#ibcon#about to write, iclass 10, count 2 2006.201.13:54:15.02#ibcon#wrote, iclass 10, count 2 2006.201.13:54:15.02#ibcon#about to read 3, iclass 10, count 2 2006.201.13:54:15.05#ibcon#read 3, iclass 10, count 2 2006.201.13:54:15.05#ibcon#about to read 4, iclass 10, count 2 2006.201.13:54:15.05#ibcon#read 4, iclass 10, count 2 2006.201.13:54:15.05#ibcon#about to read 5, iclass 10, count 2 2006.201.13:54:15.05#ibcon#read 5, iclass 10, count 2 2006.201.13:54:15.05#ibcon#about to read 6, iclass 10, count 2 2006.201.13:54:15.05#ibcon#read 6, iclass 10, count 2 2006.201.13:54:15.05#ibcon#end of sib2, iclass 10, count 2 2006.201.13:54:15.05#ibcon#*after write, iclass 10, count 2 2006.201.13:54:15.05#ibcon#*before return 0, iclass 10, count 2 2006.201.13:54:15.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:15.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:15.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.13:54:15.05#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:15.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:15.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:15.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:15.17#ibcon#enter wrdev, iclass 10, count 0 2006.201.13:54:15.17#ibcon#first serial, iclass 10, count 0 2006.201.13:54:15.17#ibcon#enter sib2, iclass 10, count 0 2006.201.13:54:15.17#ibcon#flushed, iclass 10, count 0 2006.201.13:54:15.17#ibcon#about to write, iclass 10, count 0 2006.201.13:54:15.17#ibcon#wrote, iclass 10, count 0 2006.201.13:54:15.17#ibcon#about to read 3, iclass 10, count 0 2006.201.13:54:15.20#ibcon#read 3, iclass 10, count 0 2006.201.13:54:15.20#ibcon#about to read 4, iclass 10, count 0 2006.201.13:54:15.20#ibcon#read 4, iclass 10, count 0 2006.201.13:54:15.20#ibcon#about to read 5, iclass 10, count 0 2006.201.13:54:15.20#ibcon#read 5, iclass 10, count 0 2006.201.13:54:15.20#ibcon#about to read 6, iclass 10, count 0 2006.201.13:54:15.20#ibcon#read 6, iclass 10, count 0 2006.201.13:54:15.20#ibcon#end of sib2, iclass 10, count 0 2006.201.13:54:15.20#ibcon#*mode == 0, iclass 10, count 0 2006.201.13:54:15.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.13:54:15.20#ibcon#[25=USB\r\n] 2006.201.13:54:15.20#ibcon#*before write, iclass 10, count 0 2006.201.13:54:15.20#ibcon#enter sib2, iclass 10, count 0 2006.201.13:54:15.20#ibcon#flushed, iclass 10, count 0 2006.201.13:54:15.20#ibcon#about to write, iclass 10, count 0 2006.201.13:54:15.20#ibcon#wrote, iclass 10, count 0 2006.201.13:54:15.20#ibcon#about to read 3, iclass 10, count 0 2006.201.13:54:15.23#ibcon#read 3, iclass 10, count 0 2006.201.13:54:15.23#ibcon#about to read 4, iclass 10, count 0 2006.201.13:54:15.23#ibcon#read 4, iclass 10, count 0 2006.201.13:54:15.23#ibcon#about to read 5, iclass 10, count 0 2006.201.13:54:15.23#ibcon#read 5, iclass 10, count 0 2006.201.13:54:15.23#ibcon#about to read 6, iclass 10, count 0 2006.201.13:54:15.23#ibcon#read 6, iclass 10, count 0 2006.201.13:54:15.23#ibcon#end of sib2, iclass 10, count 0 2006.201.13:54:15.23#ibcon#*after write, iclass 10, count 0 2006.201.13:54:15.23#ibcon#*before return 0, iclass 10, count 0 2006.201.13:54:15.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:15.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:15.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.13:54:15.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.13:54:15.23$vck44/valo=8,884.99 2006.201.13:54:15.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.13:54:15.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.13:54:15.23#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:15.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:15.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:15.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:15.23#ibcon#enter wrdev, iclass 12, count 0 2006.201.13:54:15.23#ibcon#first serial, iclass 12, count 0 2006.201.13:54:15.23#ibcon#enter sib2, iclass 12, count 0 2006.201.13:54:15.23#ibcon#flushed, iclass 12, count 0 2006.201.13:54:15.23#ibcon#about to write, iclass 12, count 0 2006.201.13:54:15.23#ibcon#wrote, iclass 12, count 0 2006.201.13:54:15.23#ibcon#about to read 3, iclass 12, count 0 2006.201.13:54:15.25#ibcon#read 3, iclass 12, count 0 2006.201.13:54:15.25#ibcon#about to read 4, iclass 12, count 0 2006.201.13:54:15.25#ibcon#read 4, iclass 12, count 0 2006.201.13:54:15.25#ibcon#about to read 5, iclass 12, count 0 2006.201.13:54:15.25#ibcon#read 5, iclass 12, count 0 2006.201.13:54:15.25#ibcon#about to read 6, iclass 12, count 0 2006.201.13:54:15.25#ibcon#read 6, iclass 12, count 0 2006.201.13:54:15.25#ibcon#end of sib2, iclass 12, count 0 2006.201.13:54:15.25#ibcon#*mode == 0, iclass 12, count 0 2006.201.13:54:15.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.13:54:15.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:54:15.25#ibcon#*before write, iclass 12, count 0 2006.201.13:54:15.25#ibcon#enter sib2, iclass 12, count 0 2006.201.13:54:15.25#ibcon#flushed, iclass 12, count 0 2006.201.13:54:15.25#ibcon#about to write, iclass 12, count 0 2006.201.13:54:15.25#ibcon#wrote, iclass 12, count 0 2006.201.13:54:15.25#ibcon#about to read 3, iclass 12, count 0 2006.201.13:54:15.29#ibcon#read 3, iclass 12, count 0 2006.201.13:54:15.29#ibcon#about to read 4, iclass 12, count 0 2006.201.13:54:15.29#ibcon#read 4, iclass 12, count 0 2006.201.13:54:15.29#ibcon#about to read 5, iclass 12, count 0 2006.201.13:54:15.29#ibcon#read 5, iclass 12, count 0 2006.201.13:54:15.29#ibcon#about to read 6, iclass 12, count 0 2006.201.13:54:15.29#ibcon#read 6, iclass 12, count 0 2006.201.13:54:15.29#ibcon#end of sib2, iclass 12, count 0 2006.201.13:54:15.29#ibcon#*after write, iclass 12, count 0 2006.201.13:54:15.29#ibcon#*before return 0, iclass 12, count 0 2006.201.13:54:15.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:15.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:15.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.13:54:15.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.13:54:15.29$vck44/va=8,4 2006.201.13:54:15.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.13:54:15.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.13:54:15.29#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:15.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:15.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:15.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:15.35#ibcon#enter wrdev, iclass 14, count 2 2006.201.13:54:15.35#ibcon#first serial, iclass 14, count 2 2006.201.13:54:15.35#ibcon#enter sib2, iclass 14, count 2 2006.201.13:54:15.35#ibcon#flushed, iclass 14, count 2 2006.201.13:54:15.35#ibcon#about to write, iclass 14, count 2 2006.201.13:54:15.35#ibcon#wrote, iclass 14, count 2 2006.201.13:54:15.35#ibcon#about to read 3, iclass 14, count 2 2006.201.13:54:15.37#ibcon#read 3, iclass 14, count 2 2006.201.13:54:15.37#ibcon#about to read 4, iclass 14, count 2 2006.201.13:54:15.37#ibcon#read 4, iclass 14, count 2 2006.201.13:54:15.37#ibcon#about to read 5, iclass 14, count 2 2006.201.13:54:15.37#ibcon#read 5, iclass 14, count 2 2006.201.13:54:15.37#ibcon#about to read 6, iclass 14, count 2 2006.201.13:54:15.37#ibcon#read 6, iclass 14, count 2 2006.201.13:54:15.37#ibcon#end of sib2, iclass 14, count 2 2006.201.13:54:15.37#ibcon#*mode == 0, iclass 14, count 2 2006.201.13:54:15.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.13:54:15.37#ibcon#[25=AT08-04\r\n] 2006.201.13:54:15.37#ibcon#*before write, iclass 14, count 2 2006.201.13:54:15.37#ibcon#enter sib2, iclass 14, count 2 2006.201.13:54:15.37#ibcon#flushed, iclass 14, count 2 2006.201.13:54:15.37#ibcon#about to write, iclass 14, count 2 2006.201.13:54:15.37#ibcon#wrote, iclass 14, count 2 2006.201.13:54:15.37#ibcon#about to read 3, iclass 14, count 2 2006.201.13:54:15.40#ibcon#read 3, iclass 14, count 2 2006.201.13:54:15.40#ibcon#about to read 4, iclass 14, count 2 2006.201.13:54:15.40#ibcon#read 4, iclass 14, count 2 2006.201.13:54:15.40#ibcon#about to read 5, iclass 14, count 2 2006.201.13:54:15.40#ibcon#read 5, iclass 14, count 2 2006.201.13:54:15.40#ibcon#about to read 6, iclass 14, count 2 2006.201.13:54:15.40#ibcon#read 6, iclass 14, count 2 2006.201.13:54:15.40#ibcon#end of sib2, iclass 14, count 2 2006.201.13:54:15.40#ibcon#*after write, iclass 14, count 2 2006.201.13:54:15.40#ibcon#*before return 0, iclass 14, count 2 2006.201.13:54:15.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:15.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:15.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.13:54:15.40#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:15.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:15.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:15.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:15.52#ibcon#enter wrdev, iclass 14, count 0 2006.201.13:54:15.52#ibcon#first serial, iclass 14, count 0 2006.201.13:54:15.52#ibcon#enter sib2, iclass 14, count 0 2006.201.13:54:15.52#ibcon#flushed, iclass 14, count 0 2006.201.13:54:15.52#ibcon#about to write, iclass 14, count 0 2006.201.13:54:15.52#ibcon#wrote, iclass 14, count 0 2006.201.13:54:15.52#ibcon#about to read 3, iclass 14, count 0 2006.201.13:54:15.54#ibcon#read 3, iclass 14, count 0 2006.201.13:54:15.54#ibcon#about to read 4, iclass 14, count 0 2006.201.13:54:15.54#ibcon#read 4, iclass 14, count 0 2006.201.13:54:15.54#ibcon#about to read 5, iclass 14, count 0 2006.201.13:54:15.54#ibcon#read 5, iclass 14, count 0 2006.201.13:54:15.54#ibcon#about to read 6, iclass 14, count 0 2006.201.13:54:15.54#ibcon#read 6, iclass 14, count 0 2006.201.13:54:15.54#ibcon#end of sib2, iclass 14, count 0 2006.201.13:54:15.54#ibcon#*mode == 0, iclass 14, count 0 2006.201.13:54:15.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.13:54:15.54#ibcon#[25=USB\r\n] 2006.201.13:54:15.54#ibcon#*before write, iclass 14, count 0 2006.201.13:54:15.54#ibcon#enter sib2, iclass 14, count 0 2006.201.13:54:15.54#ibcon#flushed, iclass 14, count 0 2006.201.13:54:15.54#ibcon#about to write, iclass 14, count 0 2006.201.13:54:15.54#ibcon#wrote, iclass 14, count 0 2006.201.13:54:15.54#ibcon#about to read 3, iclass 14, count 0 2006.201.13:54:15.57#ibcon#read 3, iclass 14, count 0 2006.201.13:54:15.57#ibcon#about to read 4, iclass 14, count 0 2006.201.13:54:15.57#ibcon#read 4, iclass 14, count 0 2006.201.13:54:15.57#ibcon#about to read 5, iclass 14, count 0 2006.201.13:54:15.57#ibcon#read 5, iclass 14, count 0 2006.201.13:54:15.57#ibcon#about to read 6, iclass 14, count 0 2006.201.13:54:15.57#ibcon#read 6, iclass 14, count 0 2006.201.13:54:15.57#ibcon#end of sib2, iclass 14, count 0 2006.201.13:54:15.57#ibcon#*after write, iclass 14, count 0 2006.201.13:54:15.57#ibcon#*before return 0, iclass 14, count 0 2006.201.13:54:15.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:15.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:15.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.13:54:15.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.13:54:15.57$vck44/vblo=1,629.99 2006.201.13:54:15.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.13:54:15.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.13:54:15.57#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:15.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:15.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:15.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:15.57#ibcon#enter wrdev, iclass 16, count 0 2006.201.13:54:15.57#ibcon#first serial, iclass 16, count 0 2006.201.13:54:15.57#ibcon#enter sib2, iclass 16, count 0 2006.201.13:54:15.57#ibcon#flushed, iclass 16, count 0 2006.201.13:54:15.57#ibcon#about to write, iclass 16, count 0 2006.201.13:54:15.57#ibcon#wrote, iclass 16, count 0 2006.201.13:54:15.57#ibcon#about to read 3, iclass 16, count 0 2006.201.13:54:15.59#ibcon#read 3, iclass 16, count 0 2006.201.13:54:15.59#ibcon#about to read 4, iclass 16, count 0 2006.201.13:54:15.59#ibcon#read 4, iclass 16, count 0 2006.201.13:54:15.59#ibcon#about to read 5, iclass 16, count 0 2006.201.13:54:15.59#ibcon#read 5, iclass 16, count 0 2006.201.13:54:15.59#ibcon#about to read 6, iclass 16, count 0 2006.201.13:54:15.59#ibcon#read 6, iclass 16, count 0 2006.201.13:54:15.59#ibcon#end of sib2, iclass 16, count 0 2006.201.13:54:15.59#ibcon#*mode == 0, iclass 16, count 0 2006.201.13:54:15.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.13:54:15.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:54:15.59#ibcon#*before write, iclass 16, count 0 2006.201.13:54:15.59#ibcon#enter sib2, iclass 16, count 0 2006.201.13:54:15.59#ibcon#flushed, iclass 16, count 0 2006.201.13:54:15.59#ibcon#about to write, iclass 16, count 0 2006.201.13:54:15.59#ibcon#wrote, iclass 16, count 0 2006.201.13:54:15.59#ibcon#about to read 3, iclass 16, count 0 2006.201.13:54:15.64#ibcon#read 3, iclass 16, count 0 2006.201.13:54:15.64#ibcon#about to read 4, iclass 16, count 0 2006.201.13:54:15.64#ibcon#read 4, iclass 16, count 0 2006.201.13:54:15.64#ibcon#about to read 5, iclass 16, count 0 2006.201.13:54:15.64#ibcon#read 5, iclass 16, count 0 2006.201.13:54:15.64#ibcon#about to read 6, iclass 16, count 0 2006.201.13:54:15.64#ibcon#read 6, iclass 16, count 0 2006.201.13:54:15.64#ibcon#end of sib2, iclass 16, count 0 2006.201.13:54:15.64#ibcon#*after write, iclass 16, count 0 2006.201.13:54:15.64#ibcon#*before return 0, iclass 16, count 0 2006.201.13:54:15.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:15.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:15.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.13:54:15.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.13:54:15.64$vck44/vb=1,4 2006.201.13:54:15.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.13:54:15.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.13:54:15.64#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:15.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:54:15.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:54:15.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:54:15.64#ibcon#enter wrdev, iclass 18, count 2 2006.201.13:54:15.64#ibcon#first serial, iclass 18, count 2 2006.201.13:54:15.64#ibcon#enter sib2, iclass 18, count 2 2006.201.13:54:15.64#ibcon#flushed, iclass 18, count 2 2006.201.13:54:15.64#ibcon#about to write, iclass 18, count 2 2006.201.13:54:15.64#ibcon#wrote, iclass 18, count 2 2006.201.13:54:15.64#ibcon#about to read 3, iclass 18, count 2 2006.201.13:54:15.66#ibcon#read 3, iclass 18, count 2 2006.201.13:54:15.66#ibcon#about to read 4, iclass 18, count 2 2006.201.13:54:15.66#ibcon#read 4, iclass 18, count 2 2006.201.13:54:15.66#ibcon#about to read 5, iclass 18, count 2 2006.201.13:54:15.66#ibcon#read 5, iclass 18, count 2 2006.201.13:54:15.66#ibcon#about to read 6, iclass 18, count 2 2006.201.13:54:15.66#ibcon#read 6, iclass 18, count 2 2006.201.13:54:15.66#ibcon#end of sib2, iclass 18, count 2 2006.201.13:54:15.66#ibcon#*mode == 0, iclass 18, count 2 2006.201.13:54:15.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.13:54:15.66#ibcon#[27=AT01-04\r\n] 2006.201.13:54:15.66#ibcon#*before write, iclass 18, count 2 2006.201.13:54:15.66#ibcon#enter sib2, iclass 18, count 2 2006.201.13:54:15.66#ibcon#flushed, iclass 18, count 2 2006.201.13:54:15.66#ibcon#about to write, iclass 18, count 2 2006.201.13:54:15.66#ibcon#wrote, iclass 18, count 2 2006.201.13:54:15.66#ibcon#about to read 3, iclass 18, count 2 2006.201.13:54:15.69#ibcon#read 3, iclass 18, count 2 2006.201.13:54:15.69#ibcon#about to read 4, iclass 18, count 2 2006.201.13:54:15.69#ibcon#read 4, iclass 18, count 2 2006.201.13:54:15.69#ibcon#about to read 5, iclass 18, count 2 2006.201.13:54:15.69#ibcon#read 5, iclass 18, count 2 2006.201.13:54:15.69#ibcon#about to read 6, iclass 18, count 2 2006.201.13:54:15.69#ibcon#read 6, iclass 18, count 2 2006.201.13:54:15.69#ibcon#end of sib2, iclass 18, count 2 2006.201.13:54:15.69#ibcon#*after write, iclass 18, count 2 2006.201.13:54:15.69#ibcon#*before return 0, iclass 18, count 2 2006.201.13:54:15.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:54:15.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.13:54:15.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.13:54:15.69#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:15.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:54:15.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:54:15.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:54:15.81#ibcon#enter wrdev, iclass 18, count 0 2006.201.13:54:15.81#ibcon#first serial, iclass 18, count 0 2006.201.13:54:15.81#ibcon#enter sib2, iclass 18, count 0 2006.201.13:54:15.81#ibcon#flushed, iclass 18, count 0 2006.201.13:54:15.81#ibcon#about to write, iclass 18, count 0 2006.201.13:54:15.81#ibcon#wrote, iclass 18, count 0 2006.201.13:54:15.81#ibcon#about to read 3, iclass 18, count 0 2006.201.13:54:15.83#ibcon#read 3, iclass 18, count 0 2006.201.13:54:15.83#ibcon#about to read 4, iclass 18, count 0 2006.201.13:54:15.83#ibcon#read 4, iclass 18, count 0 2006.201.13:54:15.83#ibcon#about to read 5, iclass 18, count 0 2006.201.13:54:15.83#ibcon#read 5, iclass 18, count 0 2006.201.13:54:15.83#ibcon#about to read 6, iclass 18, count 0 2006.201.13:54:15.83#ibcon#read 6, iclass 18, count 0 2006.201.13:54:15.83#ibcon#end of sib2, iclass 18, count 0 2006.201.13:54:15.83#ibcon#*mode == 0, iclass 18, count 0 2006.201.13:54:15.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.13:54:15.83#ibcon#[27=USB\r\n] 2006.201.13:54:15.83#ibcon#*before write, iclass 18, count 0 2006.201.13:54:15.83#ibcon#enter sib2, iclass 18, count 0 2006.201.13:54:15.83#ibcon#flushed, iclass 18, count 0 2006.201.13:54:15.83#ibcon#about to write, iclass 18, count 0 2006.201.13:54:15.83#ibcon#wrote, iclass 18, count 0 2006.201.13:54:15.83#ibcon#about to read 3, iclass 18, count 0 2006.201.13:54:15.86#ibcon#read 3, iclass 18, count 0 2006.201.13:54:15.86#ibcon#about to read 4, iclass 18, count 0 2006.201.13:54:15.86#ibcon#read 4, iclass 18, count 0 2006.201.13:54:15.86#ibcon#about to read 5, iclass 18, count 0 2006.201.13:54:15.86#ibcon#read 5, iclass 18, count 0 2006.201.13:54:15.86#ibcon#about to read 6, iclass 18, count 0 2006.201.13:54:15.86#ibcon#read 6, iclass 18, count 0 2006.201.13:54:15.86#ibcon#end of sib2, iclass 18, count 0 2006.201.13:54:15.86#ibcon#*after write, iclass 18, count 0 2006.201.13:54:15.86#ibcon#*before return 0, iclass 18, count 0 2006.201.13:54:15.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:54:15.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.13:54:15.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.13:54:15.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.13:54:15.86$vck44/vblo=2,634.99 2006.201.13:54:15.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.13:54:15.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.13:54:15.86#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:15.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:15.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:15.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:15.86#ibcon#enter wrdev, iclass 20, count 0 2006.201.13:54:15.86#ibcon#first serial, iclass 20, count 0 2006.201.13:54:15.86#ibcon#enter sib2, iclass 20, count 0 2006.201.13:54:15.86#ibcon#flushed, iclass 20, count 0 2006.201.13:54:15.86#ibcon#about to write, iclass 20, count 0 2006.201.13:54:15.86#ibcon#wrote, iclass 20, count 0 2006.201.13:54:15.86#ibcon#about to read 3, iclass 20, count 0 2006.201.13:54:15.88#ibcon#read 3, iclass 20, count 0 2006.201.13:54:15.88#ibcon#about to read 4, iclass 20, count 0 2006.201.13:54:15.88#ibcon#read 4, iclass 20, count 0 2006.201.13:54:15.88#ibcon#about to read 5, iclass 20, count 0 2006.201.13:54:15.88#ibcon#read 5, iclass 20, count 0 2006.201.13:54:15.88#ibcon#about to read 6, iclass 20, count 0 2006.201.13:54:15.88#ibcon#read 6, iclass 20, count 0 2006.201.13:54:15.88#ibcon#end of sib2, iclass 20, count 0 2006.201.13:54:15.88#ibcon#*mode == 0, iclass 20, count 0 2006.201.13:54:15.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.13:54:15.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:54:15.88#ibcon#*before write, iclass 20, count 0 2006.201.13:54:15.88#ibcon#enter sib2, iclass 20, count 0 2006.201.13:54:15.88#ibcon#flushed, iclass 20, count 0 2006.201.13:54:15.88#ibcon#about to write, iclass 20, count 0 2006.201.13:54:15.88#ibcon#wrote, iclass 20, count 0 2006.201.13:54:15.88#ibcon#about to read 3, iclass 20, count 0 2006.201.13:54:15.92#ibcon#read 3, iclass 20, count 0 2006.201.13:54:15.92#ibcon#about to read 4, iclass 20, count 0 2006.201.13:54:15.92#ibcon#read 4, iclass 20, count 0 2006.201.13:54:15.92#ibcon#about to read 5, iclass 20, count 0 2006.201.13:54:15.92#ibcon#read 5, iclass 20, count 0 2006.201.13:54:15.92#ibcon#about to read 6, iclass 20, count 0 2006.201.13:54:15.92#ibcon#read 6, iclass 20, count 0 2006.201.13:54:15.92#ibcon#end of sib2, iclass 20, count 0 2006.201.13:54:15.92#ibcon#*after write, iclass 20, count 0 2006.201.13:54:15.92#ibcon#*before return 0, iclass 20, count 0 2006.201.13:54:15.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:15.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.13:54:15.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.13:54:15.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.13:54:15.92$vck44/vb=2,5 2006.201.13:54:15.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.13:54:15.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.13:54:15.92#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:15.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:15.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:15.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:15.98#ibcon#enter wrdev, iclass 22, count 2 2006.201.13:54:15.98#ibcon#first serial, iclass 22, count 2 2006.201.13:54:15.98#ibcon#enter sib2, iclass 22, count 2 2006.201.13:54:15.98#ibcon#flushed, iclass 22, count 2 2006.201.13:54:15.98#ibcon#about to write, iclass 22, count 2 2006.201.13:54:15.98#ibcon#wrote, iclass 22, count 2 2006.201.13:54:15.98#ibcon#about to read 3, iclass 22, count 2 2006.201.13:54:16.00#ibcon#read 3, iclass 22, count 2 2006.201.13:54:16.00#ibcon#about to read 4, iclass 22, count 2 2006.201.13:54:16.00#ibcon#read 4, iclass 22, count 2 2006.201.13:54:16.00#ibcon#about to read 5, iclass 22, count 2 2006.201.13:54:16.00#ibcon#read 5, iclass 22, count 2 2006.201.13:54:16.00#ibcon#about to read 6, iclass 22, count 2 2006.201.13:54:16.00#ibcon#read 6, iclass 22, count 2 2006.201.13:54:16.00#ibcon#end of sib2, iclass 22, count 2 2006.201.13:54:16.00#ibcon#*mode == 0, iclass 22, count 2 2006.201.13:54:16.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.13:54:16.00#ibcon#[27=AT02-05\r\n] 2006.201.13:54:16.00#ibcon#*before write, iclass 22, count 2 2006.201.13:54:16.00#ibcon#enter sib2, iclass 22, count 2 2006.201.13:54:16.00#ibcon#flushed, iclass 22, count 2 2006.201.13:54:16.00#ibcon#about to write, iclass 22, count 2 2006.201.13:54:16.00#ibcon#wrote, iclass 22, count 2 2006.201.13:54:16.00#ibcon#about to read 3, iclass 22, count 2 2006.201.13:54:16.03#ibcon#read 3, iclass 22, count 2 2006.201.13:54:16.03#ibcon#about to read 4, iclass 22, count 2 2006.201.13:54:16.03#ibcon#read 4, iclass 22, count 2 2006.201.13:54:16.03#ibcon#about to read 5, iclass 22, count 2 2006.201.13:54:16.03#ibcon#read 5, iclass 22, count 2 2006.201.13:54:16.03#ibcon#about to read 6, iclass 22, count 2 2006.201.13:54:16.03#ibcon#read 6, iclass 22, count 2 2006.201.13:54:16.03#ibcon#end of sib2, iclass 22, count 2 2006.201.13:54:16.03#ibcon#*after write, iclass 22, count 2 2006.201.13:54:16.03#ibcon#*before return 0, iclass 22, count 2 2006.201.13:54:16.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:16.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.13:54:16.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.13:54:16.03#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:16.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:16.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:16.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:16.15#ibcon#enter wrdev, iclass 22, count 0 2006.201.13:54:16.15#ibcon#first serial, iclass 22, count 0 2006.201.13:54:16.15#ibcon#enter sib2, iclass 22, count 0 2006.201.13:54:16.15#ibcon#flushed, iclass 22, count 0 2006.201.13:54:16.15#ibcon#about to write, iclass 22, count 0 2006.201.13:54:16.15#ibcon#wrote, iclass 22, count 0 2006.201.13:54:16.15#ibcon#about to read 3, iclass 22, count 0 2006.201.13:54:16.17#ibcon#read 3, iclass 22, count 0 2006.201.13:54:16.17#ibcon#about to read 4, iclass 22, count 0 2006.201.13:54:16.17#ibcon#read 4, iclass 22, count 0 2006.201.13:54:16.17#ibcon#about to read 5, iclass 22, count 0 2006.201.13:54:16.17#ibcon#read 5, iclass 22, count 0 2006.201.13:54:16.17#ibcon#about to read 6, iclass 22, count 0 2006.201.13:54:16.17#ibcon#read 6, iclass 22, count 0 2006.201.13:54:16.17#ibcon#end of sib2, iclass 22, count 0 2006.201.13:54:16.17#ibcon#*mode == 0, iclass 22, count 0 2006.201.13:54:16.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.13:54:16.17#ibcon#[27=USB\r\n] 2006.201.13:54:16.17#ibcon#*before write, iclass 22, count 0 2006.201.13:54:16.17#ibcon#enter sib2, iclass 22, count 0 2006.201.13:54:16.17#ibcon#flushed, iclass 22, count 0 2006.201.13:54:16.17#ibcon#about to write, iclass 22, count 0 2006.201.13:54:16.17#ibcon#wrote, iclass 22, count 0 2006.201.13:54:16.17#ibcon#about to read 3, iclass 22, count 0 2006.201.13:54:16.20#ibcon#read 3, iclass 22, count 0 2006.201.13:54:16.20#ibcon#about to read 4, iclass 22, count 0 2006.201.13:54:16.20#ibcon#read 4, iclass 22, count 0 2006.201.13:54:16.20#ibcon#about to read 5, iclass 22, count 0 2006.201.13:54:16.20#ibcon#read 5, iclass 22, count 0 2006.201.13:54:16.20#ibcon#about to read 6, iclass 22, count 0 2006.201.13:54:16.20#ibcon#read 6, iclass 22, count 0 2006.201.13:54:16.20#ibcon#end of sib2, iclass 22, count 0 2006.201.13:54:16.20#ibcon#*after write, iclass 22, count 0 2006.201.13:54:16.20#ibcon#*before return 0, iclass 22, count 0 2006.201.13:54:16.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:16.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.13:54:16.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.13:54:16.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.13:54:16.20$vck44/vblo=3,649.99 2006.201.13:54:16.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.13:54:16.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.13:54:16.20#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:16.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:16.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:16.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:16.20#ibcon#enter wrdev, iclass 24, count 0 2006.201.13:54:16.20#ibcon#first serial, iclass 24, count 0 2006.201.13:54:16.20#ibcon#enter sib2, iclass 24, count 0 2006.201.13:54:16.20#ibcon#flushed, iclass 24, count 0 2006.201.13:54:16.20#ibcon#about to write, iclass 24, count 0 2006.201.13:54:16.20#ibcon#wrote, iclass 24, count 0 2006.201.13:54:16.20#ibcon#about to read 3, iclass 24, count 0 2006.201.13:54:16.22#ibcon#read 3, iclass 24, count 0 2006.201.13:54:16.22#ibcon#about to read 4, iclass 24, count 0 2006.201.13:54:16.22#ibcon#read 4, iclass 24, count 0 2006.201.13:54:16.22#ibcon#about to read 5, iclass 24, count 0 2006.201.13:54:16.22#ibcon#read 5, iclass 24, count 0 2006.201.13:54:16.22#ibcon#about to read 6, iclass 24, count 0 2006.201.13:54:16.22#ibcon#read 6, iclass 24, count 0 2006.201.13:54:16.22#ibcon#end of sib2, iclass 24, count 0 2006.201.13:54:16.22#ibcon#*mode == 0, iclass 24, count 0 2006.201.13:54:16.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.13:54:16.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:54:16.22#ibcon#*before write, iclass 24, count 0 2006.201.13:54:16.22#ibcon#enter sib2, iclass 24, count 0 2006.201.13:54:16.22#ibcon#flushed, iclass 24, count 0 2006.201.13:54:16.22#ibcon#about to write, iclass 24, count 0 2006.201.13:54:16.22#ibcon#wrote, iclass 24, count 0 2006.201.13:54:16.22#ibcon#about to read 3, iclass 24, count 0 2006.201.13:54:16.26#ibcon#read 3, iclass 24, count 0 2006.201.13:54:16.26#ibcon#about to read 4, iclass 24, count 0 2006.201.13:54:16.26#ibcon#read 4, iclass 24, count 0 2006.201.13:54:16.26#ibcon#about to read 5, iclass 24, count 0 2006.201.13:54:16.26#ibcon#read 5, iclass 24, count 0 2006.201.13:54:16.26#ibcon#about to read 6, iclass 24, count 0 2006.201.13:54:16.26#ibcon#read 6, iclass 24, count 0 2006.201.13:54:16.26#ibcon#end of sib2, iclass 24, count 0 2006.201.13:54:16.26#ibcon#*after write, iclass 24, count 0 2006.201.13:54:16.26#ibcon#*before return 0, iclass 24, count 0 2006.201.13:54:16.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:16.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.13:54:16.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.13:54:16.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.13:54:16.26$vck44/vb=3,4 2006.201.13:54:16.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.13:54:16.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.13:54:16.26#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:16.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:16.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:16.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:16.32#ibcon#enter wrdev, iclass 26, count 2 2006.201.13:54:16.32#ibcon#first serial, iclass 26, count 2 2006.201.13:54:16.32#ibcon#enter sib2, iclass 26, count 2 2006.201.13:54:16.32#ibcon#flushed, iclass 26, count 2 2006.201.13:54:16.32#ibcon#about to write, iclass 26, count 2 2006.201.13:54:16.32#ibcon#wrote, iclass 26, count 2 2006.201.13:54:16.32#ibcon#about to read 3, iclass 26, count 2 2006.201.13:54:16.34#ibcon#read 3, iclass 26, count 2 2006.201.13:54:16.34#ibcon#about to read 4, iclass 26, count 2 2006.201.13:54:16.34#ibcon#read 4, iclass 26, count 2 2006.201.13:54:16.34#ibcon#about to read 5, iclass 26, count 2 2006.201.13:54:16.34#ibcon#read 5, iclass 26, count 2 2006.201.13:54:16.34#ibcon#about to read 6, iclass 26, count 2 2006.201.13:54:16.34#ibcon#read 6, iclass 26, count 2 2006.201.13:54:16.34#ibcon#end of sib2, iclass 26, count 2 2006.201.13:54:16.34#ibcon#*mode == 0, iclass 26, count 2 2006.201.13:54:16.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.13:54:16.34#ibcon#[27=AT03-04\r\n] 2006.201.13:54:16.34#ibcon#*before write, iclass 26, count 2 2006.201.13:54:16.34#ibcon#enter sib2, iclass 26, count 2 2006.201.13:54:16.34#ibcon#flushed, iclass 26, count 2 2006.201.13:54:16.34#ibcon#about to write, iclass 26, count 2 2006.201.13:54:16.34#ibcon#wrote, iclass 26, count 2 2006.201.13:54:16.34#ibcon#about to read 3, iclass 26, count 2 2006.201.13:54:16.37#ibcon#read 3, iclass 26, count 2 2006.201.13:54:16.37#ibcon#about to read 4, iclass 26, count 2 2006.201.13:54:16.37#ibcon#read 4, iclass 26, count 2 2006.201.13:54:16.37#ibcon#about to read 5, iclass 26, count 2 2006.201.13:54:16.37#ibcon#read 5, iclass 26, count 2 2006.201.13:54:16.37#ibcon#about to read 6, iclass 26, count 2 2006.201.13:54:16.37#ibcon#read 6, iclass 26, count 2 2006.201.13:54:16.37#ibcon#end of sib2, iclass 26, count 2 2006.201.13:54:16.37#ibcon#*after write, iclass 26, count 2 2006.201.13:54:16.37#ibcon#*before return 0, iclass 26, count 2 2006.201.13:54:16.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:16.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.13:54:16.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.13:54:16.37#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:16.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:16.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:16.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:16.49#ibcon#enter wrdev, iclass 26, count 0 2006.201.13:54:16.49#ibcon#first serial, iclass 26, count 0 2006.201.13:54:16.49#ibcon#enter sib2, iclass 26, count 0 2006.201.13:54:16.49#ibcon#flushed, iclass 26, count 0 2006.201.13:54:16.49#ibcon#about to write, iclass 26, count 0 2006.201.13:54:16.49#ibcon#wrote, iclass 26, count 0 2006.201.13:54:16.49#ibcon#about to read 3, iclass 26, count 0 2006.201.13:54:16.51#ibcon#read 3, iclass 26, count 0 2006.201.13:54:16.51#ibcon#about to read 4, iclass 26, count 0 2006.201.13:54:16.51#ibcon#read 4, iclass 26, count 0 2006.201.13:54:16.51#ibcon#about to read 5, iclass 26, count 0 2006.201.13:54:16.51#ibcon#read 5, iclass 26, count 0 2006.201.13:54:16.51#ibcon#about to read 6, iclass 26, count 0 2006.201.13:54:16.51#ibcon#read 6, iclass 26, count 0 2006.201.13:54:16.51#ibcon#end of sib2, iclass 26, count 0 2006.201.13:54:16.51#ibcon#*mode == 0, iclass 26, count 0 2006.201.13:54:16.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.13:54:16.51#ibcon#[27=USB\r\n] 2006.201.13:54:16.51#ibcon#*before write, iclass 26, count 0 2006.201.13:54:16.51#ibcon#enter sib2, iclass 26, count 0 2006.201.13:54:16.51#ibcon#flushed, iclass 26, count 0 2006.201.13:54:16.51#ibcon#about to write, iclass 26, count 0 2006.201.13:54:16.51#ibcon#wrote, iclass 26, count 0 2006.201.13:54:16.51#ibcon#about to read 3, iclass 26, count 0 2006.201.13:54:16.54#ibcon#read 3, iclass 26, count 0 2006.201.13:54:16.54#ibcon#about to read 4, iclass 26, count 0 2006.201.13:54:16.54#ibcon#read 4, iclass 26, count 0 2006.201.13:54:16.54#ibcon#about to read 5, iclass 26, count 0 2006.201.13:54:16.54#ibcon#read 5, iclass 26, count 0 2006.201.13:54:16.54#ibcon#about to read 6, iclass 26, count 0 2006.201.13:54:16.54#ibcon#read 6, iclass 26, count 0 2006.201.13:54:16.54#ibcon#end of sib2, iclass 26, count 0 2006.201.13:54:16.54#ibcon#*after write, iclass 26, count 0 2006.201.13:54:16.54#ibcon#*before return 0, iclass 26, count 0 2006.201.13:54:16.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:16.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.13:54:16.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.13:54:16.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.13:54:16.54$vck44/vblo=4,679.99 2006.201.13:54:16.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.13:54:16.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.13:54:16.54#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:16.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:16.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:16.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:16.54#ibcon#enter wrdev, iclass 28, count 0 2006.201.13:54:16.54#ibcon#first serial, iclass 28, count 0 2006.201.13:54:16.54#ibcon#enter sib2, iclass 28, count 0 2006.201.13:54:16.54#ibcon#flushed, iclass 28, count 0 2006.201.13:54:16.54#ibcon#about to write, iclass 28, count 0 2006.201.13:54:16.54#ibcon#wrote, iclass 28, count 0 2006.201.13:54:16.54#ibcon#about to read 3, iclass 28, count 0 2006.201.13:54:16.56#ibcon#read 3, iclass 28, count 0 2006.201.13:54:16.56#ibcon#about to read 4, iclass 28, count 0 2006.201.13:54:16.56#ibcon#read 4, iclass 28, count 0 2006.201.13:54:16.56#ibcon#about to read 5, iclass 28, count 0 2006.201.13:54:16.56#ibcon#read 5, iclass 28, count 0 2006.201.13:54:16.56#ibcon#about to read 6, iclass 28, count 0 2006.201.13:54:16.56#ibcon#read 6, iclass 28, count 0 2006.201.13:54:16.56#ibcon#end of sib2, iclass 28, count 0 2006.201.13:54:16.56#ibcon#*mode == 0, iclass 28, count 0 2006.201.13:54:16.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.13:54:16.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:54:16.56#ibcon#*before write, iclass 28, count 0 2006.201.13:54:16.56#ibcon#enter sib2, iclass 28, count 0 2006.201.13:54:16.56#ibcon#flushed, iclass 28, count 0 2006.201.13:54:16.56#ibcon#about to write, iclass 28, count 0 2006.201.13:54:16.56#ibcon#wrote, iclass 28, count 0 2006.201.13:54:16.56#ibcon#about to read 3, iclass 28, count 0 2006.201.13:54:16.60#ibcon#read 3, iclass 28, count 0 2006.201.13:54:16.60#ibcon#about to read 4, iclass 28, count 0 2006.201.13:54:16.60#ibcon#read 4, iclass 28, count 0 2006.201.13:54:16.60#ibcon#about to read 5, iclass 28, count 0 2006.201.13:54:16.60#ibcon#read 5, iclass 28, count 0 2006.201.13:54:16.60#ibcon#about to read 6, iclass 28, count 0 2006.201.13:54:16.60#ibcon#read 6, iclass 28, count 0 2006.201.13:54:16.60#ibcon#end of sib2, iclass 28, count 0 2006.201.13:54:16.60#ibcon#*after write, iclass 28, count 0 2006.201.13:54:16.60#ibcon#*before return 0, iclass 28, count 0 2006.201.13:54:16.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:16.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.13:54:16.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.13:54:16.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.13:54:16.60$vck44/vb=4,5 2006.201.13:54:16.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.13:54:16.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.13:54:16.60#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:16.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:16.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:16.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:16.66#ibcon#enter wrdev, iclass 30, count 2 2006.201.13:54:16.66#ibcon#first serial, iclass 30, count 2 2006.201.13:54:16.66#ibcon#enter sib2, iclass 30, count 2 2006.201.13:54:16.66#ibcon#flushed, iclass 30, count 2 2006.201.13:54:16.66#ibcon#about to write, iclass 30, count 2 2006.201.13:54:16.66#ibcon#wrote, iclass 30, count 2 2006.201.13:54:16.66#ibcon#about to read 3, iclass 30, count 2 2006.201.13:54:16.68#ibcon#read 3, iclass 30, count 2 2006.201.13:54:16.68#ibcon#about to read 4, iclass 30, count 2 2006.201.13:54:16.68#ibcon#read 4, iclass 30, count 2 2006.201.13:54:16.68#ibcon#about to read 5, iclass 30, count 2 2006.201.13:54:16.68#ibcon#read 5, iclass 30, count 2 2006.201.13:54:16.68#ibcon#about to read 6, iclass 30, count 2 2006.201.13:54:16.68#ibcon#read 6, iclass 30, count 2 2006.201.13:54:16.68#ibcon#end of sib2, iclass 30, count 2 2006.201.13:54:16.68#ibcon#*mode == 0, iclass 30, count 2 2006.201.13:54:16.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.13:54:16.68#ibcon#[27=AT04-05\r\n] 2006.201.13:54:16.68#ibcon#*before write, iclass 30, count 2 2006.201.13:54:16.68#ibcon#enter sib2, iclass 30, count 2 2006.201.13:54:16.68#ibcon#flushed, iclass 30, count 2 2006.201.13:54:16.68#ibcon#about to write, iclass 30, count 2 2006.201.13:54:16.68#ibcon#wrote, iclass 30, count 2 2006.201.13:54:16.68#ibcon#about to read 3, iclass 30, count 2 2006.201.13:54:16.70#abcon#<5=/04 1.2 2.3 20.881001004.0\r\n> 2006.201.13:54:16.71#ibcon#read 3, iclass 30, count 2 2006.201.13:54:16.71#ibcon#about to read 4, iclass 30, count 2 2006.201.13:54:16.71#ibcon#read 4, iclass 30, count 2 2006.201.13:54:16.71#ibcon#about to read 5, iclass 30, count 2 2006.201.13:54:16.71#ibcon#read 5, iclass 30, count 2 2006.201.13:54:16.71#ibcon#about to read 6, iclass 30, count 2 2006.201.13:54:16.71#ibcon#read 6, iclass 30, count 2 2006.201.13:54:16.71#ibcon#end of sib2, iclass 30, count 2 2006.201.13:54:16.71#ibcon#*after write, iclass 30, count 2 2006.201.13:54:16.71#ibcon#*before return 0, iclass 30, count 2 2006.201.13:54:16.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:16.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.13:54:16.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.13:54:16.71#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:16.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:16.72#abcon#{5=INTERFACE CLEAR} 2006.201.13:54:16.78#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:54:16.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:16.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:16.83#ibcon#enter wrdev, iclass 30, count 0 2006.201.13:54:16.83#ibcon#first serial, iclass 30, count 0 2006.201.13:54:16.83#ibcon#enter sib2, iclass 30, count 0 2006.201.13:54:16.83#ibcon#flushed, iclass 30, count 0 2006.201.13:54:16.83#ibcon#about to write, iclass 30, count 0 2006.201.13:54:16.83#ibcon#wrote, iclass 30, count 0 2006.201.13:54:16.83#ibcon#about to read 3, iclass 30, count 0 2006.201.13:54:16.85#ibcon#read 3, iclass 30, count 0 2006.201.13:54:16.85#ibcon#about to read 4, iclass 30, count 0 2006.201.13:54:16.85#ibcon#read 4, iclass 30, count 0 2006.201.13:54:16.85#ibcon#about to read 5, iclass 30, count 0 2006.201.13:54:16.85#ibcon#read 5, iclass 30, count 0 2006.201.13:54:16.85#ibcon#about to read 6, iclass 30, count 0 2006.201.13:54:16.85#ibcon#read 6, iclass 30, count 0 2006.201.13:54:16.85#ibcon#end of sib2, iclass 30, count 0 2006.201.13:54:16.85#ibcon#*mode == 0, iclass 30, count 0 2006.201.13:54:16.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.13:54:16.85#ibcon#[27=USB\r\n] 2006.201.13:54:16.85#ibcon#*before write, iclass 30, count 0 2006.201.13:54:16.85#ibcon#enter sib2, iclass 30, count 0 2006.201.13:54:16.85#ibcon#flushed, iclass 30, count 0 2006.201.13:54:16.85#ibcon#about to write, iclass 30, count 0 2006.201.13:54:16.85#ibcon#wrote, iclass 30, count 0 2006.201.13:54:16.85#ibcon#about to read 3, iclass 30, count 0 2006.201.13:54:16.88#ibcon#read 3, iclass 30, count 0 2006.201.13:54:16.88#ibcon#about to read 4, iclass 30, count 0 2006.201.13:54:16.88#ibcon#read 4, iclass 30, count 0 2006.201.13:54:16.88#ibcon#about to read 5, iclass 30, count 0 2006.201.13:54:16.88#ibcon#read 5, iclass 30, count 0 2006.201.13:54:16.88#ibcon#about to read 6, iclass 30, count 0 2006.201.13:54:16.88#ibcon#read 6, iclass 30, count 0 2006.201.13:54:16.88#ibcon#end of sib2, iclass 30, count 0 2006.201.13:54:16.88#ibcon#*after write, iclass 30, count 0 2006.201.13:54:16.88#ibcon#*before return 0, iclass 30, count 0 2006.201.13:54:16.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:16.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.13:54:16.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.13:54:16.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.13:54:16.88$vck44/vblo=5,709.99 2006.201.13:54:16.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.13:54:16.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.13:54:16.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:16.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:16.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:16.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:16.88#ibcon#enter wrdev, iclass 36, count 0 2006.201.13:54:16.88#ibcon#first serial, iclass 36, count 0 2006.201.13:54:16.88#ibcon#enter sib2, iclass 36, count 0 2006.201.13:54:16.88#ibcon#flushed, iclass 36, count 0 2006.201.13:54:16.88#ibcon#about to write, iclass 36, count 0 2006.201.13:54:16.88#ibcon#wrote, iclass 36, count 0 2006.201.13:54:16.88#ibcon#about to read 3, iclass 36, count 0 2006.201.13:54:16.90#ibcon#read 3, iclass 36, count 0 2006.201.13:54:16.90#ibcon#about to read 4, iclass 36, count 0 2006.201.13:54:16.90#ibcon#read 4, iclass 36, count 0 2006.201.13:54:16.90#ibcon#about to read 5, iclass 36, count 0 2006.201.13:54:16.90#ibcon#read 5, iclass 36, count 0 2006.201.13:54:16.90#ibcon#about to read 6, iclass 36, count 0 2006.201.13:54:16.90#ibcon#read 6, iclass 36, count 0 2006.201.13:54:16.90#ibcon#end of sib2, iclass 36, count 0 2006.201.13:54:16.90#ibcon#*mode == 0, iclass 36, count 0 2006.201.13:54:16.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.13:54:16.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:54:16.90#ibcon#*before write, iclass 36, count 0 2006.201.13:54:16.90#ibcon#enter sib2, iclass 36, count 0 2006.201.13:54:16.90#ibcon#flushed, iclass 36, count 0 2006.201.13:54:16.90#ibcon#about to write, iclass 36, count 0 2006.201.13:54:16.90#ibcon#wrote, iclass 36, count 0 2006.201.13:54:16.90#ibcon#about to read 3, iclass 36, count 0 2006.201.13:54:16.94#ibcon#read 3, iclass 36, count 0 2006.201.13:54:16.94#ibcon#about to read 4, iclass 36, count 0 2006.201.13:54:16.94#ibcon#read 4, iclass 36, count 0 2006.201.13:54:16.94#ibcon#about to read 5, iclass 36, count 0 2006.201.13:54:16.94#ibcon#read 5, iclass 36, count 0 2006.201.13:54:16.94#ibcon#about to read 6, iclass 36, count 0 2006.201.13:54:16.94#ibcon#read 6, iclass 36, count 0 2006.201.13:54:16.94#ibcon#end of sib2, iclass 36, count 0 2006.201.13:54:16.94#ibcon#*after write, iclass 36, count 0 2006.201.13:54:16.94#ibcon#*before return 0, iclass 36, count 0 2006.201.13:54:16.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:16.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.13:54:16.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.13:54:16.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.13:54:16.94$vck44/vb=5,4 2006.201.13:54:16.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.13:54:16.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.13:54:16.94#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:16.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:17.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:17.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:17.00#ibcon#enter wrdev, iclass 38, count 2 2006.201.13:54:17.00#ibcon#first serial, iclass 38, count 2 2006.201.13:54:17.00#ibcon#enter sib2, iclass 38, count 2 2006.201.13:54:17.00#ibcon#flushed, iclass 38, count 2 2006.201.13:54:17.00#ibcon#about to write, iclass 38, count 2 2006.201.13:54:17.00#ibcon#wrote, iclass 38, count 2 2006.201.13:54:17.00#ibcon#about to read 3, iclass 38, count 2 2006.201.13:54:17.02#ibcon#read 3, iclass 38, count 2 2006.201.13:54:17.02#ibcon#about to read 4, iclass 38, count 2 2006.201.13:54:17.02#ibcon#read 4, iclass 38, count 2 2006.201.13:54:17.02#ibcon#about to read 5, iclass 38, count 2 2006.201.13:54:17.02#ibcon#read 5, iclass 38, count 2 2006.201.13:54:17.02#ibcon#about to read 6, iclass 38, count 2 2006.201.13:54:17.02#ibcon#read 6, iclass 38, count 2 2006.201.13:54:17.02#ibcon#end of sib2, iclass 38, count 2 2006.201.13:54:17.02#ibcon#*mode == 0, iclass 38, count 2 2006.201.13:54:17.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.13:54:17.02#ibcon#[27=AT05-04\r\n] 2006.201.13:54:17.02#ibcon#*before write, iclass 38, count 2 2006.201.13:54:17.02#ibcon#enter sib2, iclass 38, count 2 2006.201.13:54:17.02#ibcon#flushed, iclass 38, count 2 2006.201.13:54:17.02#ibcon#about to write, iclass 38, count 2 2006.201.13:54:17.02#ibcon#wrote, iclass 38, count 2 2006.201.13:54:17.02#ibcon#about to read 3, iclass 38, count 2 2006.201.13:54:17.05#ibcon#read 3, iclass 38, count 2 2006.201.13:54:17.05#ibcon#about to read 4, iclass 38, count 2 2006.201.13:54:17.05#ibcon#read 4, iclass 38, count 2 2006.201.13:54:17.05#ibcon#about to read 5, iclass 38, count 2 2006.201.13:54:17.05#ibcon#read 5, iclass 38, count 2 2006.201.13:54:17.05#ibcon#about to read 6, iclass 38, count 2 2006.201.13:54:17.05#ibcon#read 6, iclass 38, count 2 2006.201.13:54:17.05#ibcon#end of sib2, iclass 38, count 2 2006.201.13:54:17.05#ibcon#*after write, iclass 38, count 2 2006.201.13:54:17.05#ibcon#*before return 0, iclass 38, count 2 2006.201.13:54:17.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:17.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.13:54:17.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.13:54:17.05#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:17.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:17.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:17.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:17.17#ibcon#enter wrdev, iclass 38, count 0 2006.201.13:54:17.17#ibcon#first serial, iclass 38, count 0 2006.201.13:54:17.17#ibcon#enter sib2, iclass 38, count 0 2006.201.13:54:17.17#ibcon#flushed, iclass 38, count 0 2006.201.13:54:17.17#ibcon#about to write, iclass 38, count 0 2006.201.13:54:17.17#ibcon#wrote, iclass 38, count 0 2006.201.13:54:17.17#ibcon#about to read 3, iclass 38, count 0 2006.201.13:54:17.19#ibcon#read 3, iclass 38, count 0 2006.201.13:54:17.19#ibcon#about to read 4, iclass 38, count 0 2006.201.13:54:17.19#ibcon#read 4, iclass 38, count 0 2006.201.13:54:17.19#ibcon#about to read 5, iclass 38, count 0 2006.201.13:54:17.19#ibcon#read 5, iclass 38, count 0 2006.201.13:54:17.19#ibcon#about to read 6, iclass 38, count 0 2006.201.13:54:17.19#ibcon#read 6, iclass 38, count 0 2006.201.13:54:17.19#ibcon#end of sib2, iclass 38, count 0 2006.201.13:54:17.19#ibcon#*mode == 0, iclass 38, count 0 2006.201.13:54:17.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.13:54:17.19#ibcon#[27=USB\r\n] 2006.201.13:54:17.19#ibcon#*before write, iclass 38, count 0 2006.201.13:54:17.19#ibcon#enter sib2, iclass 38, count 0 2006.201.13:54:17.19#ibcon#flushed, iclass 38, count 0 2006.201.13:54:17.19#ibcon#about to write, iclass 38, count 0 2006.201.13:54:17.19#ibcon#wrote, iclass 38, count 0 2006.201.13:54:17.19#ibcon#about to read 3, iclass 38, count 0 2006.201.13:54:17.22#ibcon#read 3, iclass 38, count 0 2006.201.13:54:17.22#ibcon#about to read 4, iclass 38, count 0 2006.201.13:54:17.22#ibcon#read 4, iclass 38, count 0 2006.201.13:54:17.22#ibcon#about to read 5, iclass 38, count 0 2006.201.13:54:17.22#ibcon#read 5, iclass 38, count 0 2006.201.13:54:17.22#ibcon#about to read 6, iclass 38, count 0 2006.201.13:54:17.22#ibcon#read 6, iclass 38, count 0 2006.201.13:54:17.22#ibcon#end of sib2, iclass 38, count 0 2006.201.13:54:17.22#ibcon#*after write, iclass 38, count 0 2006.201.13:54:17.22#ibcon#*before return 0, iclass 38, count 0 2006.201.13:54:17.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:17.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.13:54:17.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.13:54:17.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.13:54:17.22$vck44/vblo=6,719.99 2006.201.13:54:17.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.13:54:17.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.13:54:17.22#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:17.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:17.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:17.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:17.22#ibcon#enter wrdev, iclass 40, count 0 2006.201.13:54:17.22#ibcon#first serial, iclass 40, count 0 2006.201.13:54:17.22#ibcon#enter sib2, iclass 40, count 0 2006.201.13:54:17.22#ibcon#flushed, iclass 40, count 0 2006.201.13:54:17.22#ibcon#about to write, iclass 40, count 0 2006.201.13:54:17.22#ibcon#wrote, iclass 40, count 0 2006.201.13:54:17.22#ibcon#about to read 3, iclass 40, count 0 2006.201.13:54:17.24#ibcon#read 3, iclass 40, count 0 2006.201.13:54:17.24#ibcon#about to read 4, iclass 40, count 0 2006.201.13:54:17.24#ibcon#read 4, iclass 40, count 0 2006.201.13:54:17.24#ibcon#about to read 5, iclass 40, count 0 2006.201.13:54:17.24#ibcon#read 5, iclass 40, count 0 2006.201.13:54:17.24#ibcon#about to read 6, iclass 40, count 0 2006.201.13:54:17.24#ibcon#read 6, iclass 40, count 0 2006.201.13:54:17.24#ibcon#end of sib2, iclass 40, count 0 2006.201.13:54:17.24#ibcon#*mode == 0, iclass 40, count 0 2006.201.13:54:17.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.13:54:17.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:54:17.24#ibcon#*before write, iclass 40, count 0 2006.201.13:54:17.24#ibcon#enter sib2, iclass 40, count 0 2006.201.13:54:17.24#ibcon#flushed, iclass 40, count 0 2006.201.13:54:17.24#ibcon#about to write, iclass 40, count 0 2006.201.13:54:17.24#ibcon#wrote, iclass 40, count 0 2006.201.13:54:17.24#ibcon#about to read 3, iclass 40, count 0 2006.201.13:54:17.28#ibcon#read 3, iclass 40, count 0 2006.201.13:54:17.28#ibcon#about to read 4, iclass 40, count 0 2006.201.13:54:17.28#ibcon#read 4, iclass 40, count 0 2006.201.13:54:17.28#ibcon#about to read 5, iclass 40, count 0 2006.201.13:54:17.28#ibcon#read 5, iclass 40, count 0 2006.201.13:54:17.28#ibcon#about to read 6, iclass 40, count 0 2006.201.13:54:17.28#ibcon#read 6, iclass 40, count 0 2006.201.13:54:17.28#ibcon#end of sib2, iclass 40, count 0 2006.201.13:54:17.28#ibcon#*after write, iclass 40, count 0 2006.201.13:54:17.28#ibcon#*before return 0, iclass 40, count 0 2006.201.13:54:17.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:17.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.13:54:17.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.13:54:17.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.13:54:17.28$vck44/vb=6,4 2006.201.13:54:17.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.13:54:17.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.13:54:17.28#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:17.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:17.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:17.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:17.34#ibcon#enter wrdev, iclass 4, count 2 2006.201.13:54:17.34#ibcon#first serial, iclass 4, count 2 2006.201.13:54:17.34#ibcon#enter sib2, iclass 4, count 2 2006.201.13:54:17.34#ibcon#flushed, iclass 4, count 2 2006.201.13:54:17.34#ibcon#about to write, iclass 4, count 2 2006.201.13:54:17.34#ibcon#wrote, iclass 4, count 2 2006.201.13:54:17.34#ibcon#about to read 3, iclass 4, count 2 2006.201.13:54:17.36#ibcon#read 3, iclass 4, count 2 2006.201.13:54:17.36#ibcon#about to read 4, iclass 4, count 2 2006.201.13:54:17.36#ibcon#read 4, iclass 4, count 2 2006.201.13:54:17.36#ibcon#about to read 5, iclass 4, count 2 2006.201.13:54:17.36#ibcon#read 5, iclass 4, count 2 2006.201.13:54:17.36#ibcon#about to read 6, iclass 4, count 2 2006.201.13:54:17.36#ibcon#read 6, iclass 4, count 2 2006.201.13:54:17.36#ibcon#end of sib2, iclass 4, count 2 2006.201.13:54:17.36#ibcon#*mode == 0, iclass 4, count 2 2006.201.13:54:17.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.13:54:17.36#ibcon#[27=AT06-04\r\n] 2006.201.13:54:17.36#ibcon#*before write, iclass 4, count 2 2006.201.13:54:17.36#ibcon#enter sib2, iclass 4, count 2 2006.201.13:54:17.36#ibcon#flushed, iclass 4, count 2 2006.201.13:54:17.36#ibcon#about to write, iclass 4, count 2 2006.201.13:54:17.36#ibcon#wrote, iclass 4, count 2 2006.201.13:54:17.36#ibcon#about to read 3, iclass 4, count 2 2006.201.13:54:17.39#ibcon#read 3, iclass 4, count 2 2006.201.13:54:17.39#ibcon#about to read 4, iclass 4, count 2 2006.201.13:54:17.39#ibcon#read 4, iclass 4, count 2 2006.201.13:54:17.39#ibcon#about to read 5, iclass 4, count 2 2006.201.13:54:17.39#ibcon#read 5, iclass 4, count 2 2006.201.13:54:17.39#ibcon#about to read 6, iclass 4, count 2 2006.201.13:54:17.39#ibcon#read 6, iclass 4, count 2 2006.201.13:54:17.39#ibcon#end of sib2, iclass 4, count 2 2006.201.13:54:17.39#ibcon#*after write, iclass 4, count 2 2006.201.13:54:17.39#ibcon#*before return 0, iclass 4, count 2 2006.201.13:54:17.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:17.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.13:54:17.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.13:54:17.39#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:17.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:17.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:17.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:17.51#ibcon#enter wrdev, iclass 4, count 0 2006.201.13:54:17.51#ibcon#first serial, iclass 4, count 0 2006.201.13:54:17.51#ibcon#enter sib2, iclass 4, count 0 2006.201.13:54:17.51#ibcon#flushed, iclass 4, count 0 2006.201.13:54:17.51#ibcon#about to write, iclass 4, count 0 2006.201.13:54:17.51#ibcon#wrote, iclass 4, count 0 2006.201.13:54:17.51#ibcon#about to read 3, iclass 4, count 0 2006.201.13:54:17.53#ibcon#read 3, iclass 4, count 0 2006.201.13:54:17.53#ibcon#about to read 4, iclass 4, count 0 2006.201.13:54:17.53#ibcon#read 4, iclass 4, count 0 2006.201.13:54:17.53#ibcon#about to read 5, iclass 4, count 0 2006.201.13:54:17.53#ibcon#read 5, iclass 4, count 0 2006.201.13:54:17.53#ibcon#about to read 6, iclass 4, count 0 2006.201.13:54:17.53#ibcon#read 6, iclass 4, count 0 2006.201.13:54:17.53#ibcon#end of sib2, iclass 4, count 0 2006.201.13:54:17.53#ibcon#*mode == 0, iclass 4, count 0 2006.201.13:54:17.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.13:54:17.53#ibcon#[27=USB\r\n] 2006.201.13:54:17.53#ibcon#*before write, iclass 4, count 0 2006.201.13:54:17.53#ibcon#enter sib2, iclass 4, count 0 2006.201.13:54:17.53#ibcon#flushed, iclass 4, count 0 2006.201.13:54:17.53#ibcon#about to write, iclass 4, count 0 2006.201.13:54:17.53#ibcon#wrote, iclass 4, count 0 2006.201.13:54:17.53#ibcon#about to read 3, iclass 4, count 0 2006.201.13:54:17.56#ibcon#read 3, iclass 4, count 0 2006.201.13:54:17.56#ibcon#about to read 4, iclass 4, count 0 2006.201.13:54:17.56#ibcon#read 4, iclass 4, count 0 2006.201.13:54:17.56#ibcon#about to read 5, iclass 4, count 0 2006.201.13:54:17.56#ibcon#read 5, iclass 4, count 0 2006.201.13:54:17.56#ibcon#about to read 6, iclass 4, count 0 2006.201.13:54:17.56#ibcon#read 6, iclass 4, count 0 2006.201.13:54:17.56#ibcon#end of sib2, iclass 4, count 0 2006.201.13:54:17.56#ibcon#*after write, iclass 4, count 0 2006.201.13:54:17.56#ibcon#*before return 0, iclass 4, count 0 2006.201.13:54:17.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:17.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.13:54:17.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.13:54:17.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.13:54:17.56$vck44/vblo=7,734.99 2006.201.13:54:17.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.13:54:17.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.13:54:17.56#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:17.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:17.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:17.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:17.56#ibcon#enter wrdev, iclass 6, count 0 2006.201.13:54:17.56#ibcon#first serial, iclass 6, count 0 2006.201.13:54:17.56#ibcon#enter sib2, iclass 6, count 0 2006.201.13:54:17.56#ibcon#flushed, iclass 6, count 0 2006.201.13:54:17.56#ibcon#about to write, iclass 6, count 0 2006.201.13:54:17.56#ibcon#wrote, iclass 6, count 0 2006.201.13:54:17.56#ibcon#about to read 3, iclass 6, count 0 2006.201.13:54:17.58#ibcon#read 3, iclass 6, count 0 2006.201.13:54:17.58#ibcon#about to read 4, iclass 6, count 0 2006.201.13:54:17.58#ibcon#read 4, iclass 6, count 0 2006.201.13:54:17.58#ibcon#about to read 5, iclass 6, count 0 2006.201.13:54:17.58#ibcon#read 5, iclass 6, count 0 2006.201.13:54:17.58#ibcon#about to read 6, iclass 6, count 0 2006.201.13:54:17.58#ibcon#read 6, iclass 6, count 0 2006.201.13:54:17.58#ibcon#end of sib2, iclass 6, count 0 2006.201.13:54:17.58#ibcon#*mode == 0, iclass 6, count 0 2006.201.13:54:17.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.13:54:17.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:54:17.58#ibcon#*before write, iclass 6, count 0 2006.201.13:54:17.58#ibcon#enter sib2, iclass 6, count 0 2006.201.13:54:17.58#ibcon#flushed, iclass 6, count 0 2006.201.13:54:17.58#ibcon#about to write, iclass 6, count 0 2006.201.13:54:17.58#ibcon#wrote, iclass 6, count 0 2006.201.13:54:17.58#ibcon#about to read 3, iclass 6, count 0 2006.201.13:54:17.62#ibcon#read 3, iclass 6, count 0 2006.201.13:54:17.62#ibcon#about to read 4, iclass 6, count 0 2006.201.13:54:17.62#ibcon#read 4, iclass 6, count 0 2006.201.13:54:17.62#ibcon#about to read 5, iclass 6, count 0 2006.201.13:54:17.62#ibcon#read 5, iclass 6, count 0 2006.201.13:54:17.62#ibcon#about to read 6, iclass 6, count 0 2006.201.13:54:17.62#ibcon#read 6, iclass 6, count 0 2006.201.13:54:17.62#ibcon#end of sib2, iclass 6, count 0 2006.201.13:54:17.62#ibcon#*after write, iclass 6, count 0 2006.201.13:54:17.62#ibcon#*before return 0, iclass 6, count 0 2006.201.13:54:17.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:17.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.13:54:17.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.13:54:17.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.13:54:17.62$vck44/vb=7,4 2006.201.13:54:17.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.13:54:17.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.13:54:17.62#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:17.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:17.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:17.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:17.68#ibcon#enter wrdev, iclass 10, count 2 2006.201.13:54:17.68#ibcon#first serial, iclass 10, count 2 2006.201.13:54:17.68#ibcon#enter sib2, iclass 10, count 2 2006.201.13:54:17.68#ibcon#flushed, iclass 10, count 2 2006.201.13:54:17.68#ibcon#about to write, iclass 10, count 2 2006.201.13:54:17.68#ibcon#wrote, iclass 10, count 2 2006.201.13:54:17.68#ibcon#about to read 3, iclass 10, count 2 2006.201.13:54:17.70#ibcon#read 3, iclass 10, count 2 2006.201.13:54:17.70#ibcon#about to read 4, iclass 10, count 2 2006.201.13:54:17.70#ibcon#read 4, iclass 10, count 2 2006.201.13:54:17.70#ibcon#about to read 5, iclass 10, count 2 2006.201.13:54:17.70#ibcon#read 5, iclass 10, count 2 2006.201.13:54:17.70#ibcon#about to read 6, iclass 10, count 2 2006.201.13:54:17.70#ibcon#read 6, iclass 10, count 2 2006.201.13:54:17.70#ibcon#end of sib2, iclass 10, count 2 2006.201.13:54:17.70#ibcon#*mode == 0, iclass 10, count 2 2006.201.13:54:17.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.13:54:17.70#ibcon#[27=AT07-04\r\n] 2006.201.13:54:17.70#ibcon#*before write, iclass 10, count 2 2006.201.13:54:17.70#ibcon#enter sib2, iclass 10, count 2 2006.201.13:54:17.70#ibcon#flushed, iclass 10, count 2 2006.201.13:54:17.70#ibcon#about to write, iclass 10, count 2 2006.201.13:54:17.70#ibcon#wrote, iclass 10, count 2 2006.201.13:54:17.70#ibcon#about to read 3, iclass 10, count 2 2006.201.13:54:17.73#ibcon#read 3, iclass 10, count 2 2006.201.13:54:17.73#ibcon#about to read 4, iclass 10, count 2 2006.201.13:54:17.73#ibcon#read 4, iclass 10, count 2 2006.201.13:54:17.73#ibcon#about to read 5, iclass 10, count 2 2006.201.13:54:17.73#ibcon#read 5, iclass 10, count 2 2006.201.13:54:17.73#ibcon#about to read 6, iclass 10, count 2 2006.201.13:54:17.73#ibcon#read 6, iclass 10, count 2 2006.201.13:54:17.73#ibcon#end of sib2, iclass 10, count 2 2006.201.13:54:17.73#ibcon#*after write, iclass 10, count 2 2006.201.13:54:17.73#ibcon#*before return 0, iclass 10, count 2 2006.201.13:54:17.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:17.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.13:54:17.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.13:54:17.73#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:17.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:17.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:17.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:17.85#ibcon#enter wrdev, iclass 10, count 0 2006.201.13:54:17.85#ibcon#first serial, iclass 10, count 0 2006.201.13:54:17.85#ibcon#enter sib2, iclass 10, count 0 2006.201.13:54:17.85#ibcon#flushed, iclass 10, count 0 2006.201.13:54:17.85#ibcon#about to write, iclass 10, count 0 2006.201.13:54:17.85#ibcon#wrote, iclass 10, count 0 2006.201.13:54:17.85#ibcon#about to read 3, iclass 10, count 0 2006.201.13:54:17.87#ibcon#read 3, iclass 10, count 0 2006.201.13:54:17.87#ibcon#about to read 4, iclass 10, count 0 2006.201.13:54:17.87#ibcon#read 4, iclass 10, count 0 2006.201.13:54:17.87#ibcon#about to read 5, iclass 10, count 0 2006.201.13:54:17.87#ibcon#read 5, iclass 10, count 0 2006.201.13:54:17.87#ibcon#about to read 6, iclass 10, count 0 2006.201.13:54:17.87#ibcon#read 6, iclass 10, count 0 2006.201.13:54:17.87#ibcon#end of sib2, iclass 10, count 0 2006.201.13:54:17.87#ibcon#*mode == 0, iclass 10, count 0 2006.201.13:54:17.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.13:54:17.87#ibcon#[27=USB\r\n] 2006.201.13:54:17.87#ibcon#*before write, iclass 10, count 0 2006.201.13:54:17.87#ibcon#enter sib2, iclass 10, count 0 2006.201.13:54:17.87#ibcon#flushed, iclass 10, count 0 2006.201.13:54:17.87#ibcon#about to write, iclass 10, count 0 2006.201.13:54:17.87#ibcon#wrote, iclass 10, count 0 2006.201.13:54:17.87#ibcon#about to read 3, iclass 10, count 0 2006.201.13:54:17.90#ibcon#read 3, iclass 10, count 0 2006.201.13:54:17.90#ibcon#about to read 4, iclass 10, count 0 2006.201.13:54:17.90#ibcon#read 4, iclass 10, count 0 2006.201.13:54:17.90#ibcon#about to read 5, iclass 10, count 0 2006.201.13:54:17.90#ibcon#read 5, iclass 10, count 0 2006.201.13:54:17.90#ibcon#about to read 6, iclass 10, count 0 2006.201.13:54:17.90#ibcon#read 6, iclass 10, count 0 2006.201.13:54:17.90#ibcon#end of sib2, iclass 10, count 0 2006.201.13:54:17.90#ibcon#*after write, iclass 10, count 0 2006.201.13:54:17.90#ibcon#*before return 0, iclass 10, count 0 2006.201.13:54:17.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:17.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.13:54:17.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.13:54:17.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.13:54:17.90$vck44/vblo=8,744.99 2006.201.13:54:17.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.13:54:17.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.13:54:17.90#ibcon#ireg 17 cls_cnt 0 2006.201.13:54:17.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:17.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:17.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:17.90#ibcon#enter wrdev, iclass 12, count 0 2006.201.13:54:17.90#ibcon#first serial, iclass 12, count 0 2006.201.13:54:17.90#ibcon#enter sib2, iclass 12, count 0 2006.201.13:54:17.90#ibcon#flushed, iclass 12, count 0 2006.201.13:54:17.90#ibcon#about to write, iclass 12, count 0 2006.201.13:54:17.90#ibcon#wrote, iclass 12, count 0 2006.201.13:54:17.90#ibcon#about to read 3, iclass 12, count 0 2006.201.13:54:17.92#ibcon#read 3, iclass 12, count 0 2006.201.13:54:17.92#ibcon#about to read 4, iclass 12, count 0 2006.201.13:54:17.92#ibcon#read 4, iclass 12, count 0 2006.201.13:54:17.92#ibcon#about to read 5, iclass 12, count 0 2006.201.13:54:17.92#ibcon#read 5, iclass 12, count 0 2006.201.13:54:17.92#ibcon#about to read 6, iclass 12, count 0 2006.201.13:54:17.92#ibcon#read 6, iclass 12, count 0 2006.201.13:54:17.92#ibcon#end of sib2, iclass 12, count 0 2006.201.13:54:17.92#ibcon#*mode == 0, iclass 12, count 0 2006.201.13:54:17.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.13:54:17.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:54:17.92#ibcon#*before write, iclass 12, count 0 2006.201.13:54:17.92#ibcon#enter sib2, iclass 12, count 0 2006.201.13:54:17.92#ibcon#flushed, iclass 12, count 0 2006.201.13:54:17.92#ibcon#about to write, iclass 12, count 0 2006.201.13:54:17.92#ibcon#wrote, iclass 12, count 0 2006.201.13:54:17.92#ibcon#about to read 3, iclass 12, count 0 2006.201.13:54:17.97#ibcon#read 3, iclass 12, count 0 2006.201.13:54:17.97#ibcon#about to read 4, iclass 12, count 0 2006.201.13:54:17.97#ibcon#read 4, iclass 12, count 0 2006.201.13:54:17.97#ibcon#about to read 5, iclass 12, count 0 2006.201.13:54:17.97#ibcon#read 5, iclass 12, count 0 2006.201.13:54:17.97#ibcon#about to read 6, iclass 12, count 0 2006.201.13:54:17.97#ibcon#read 6, iclass 12, count 0 2006.201.13:54:17.97#ibcon#end of sib2, iclass 12, count 0 2006.201.13:54:17.97#ibcon#*after write, iclass 12, count 0 2006.201.13:54:17.97#ibcon#*before return 0, iclass 12, count 0 2006.201.13:54:17.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:17.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.13:54:17.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.13:54:17.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.13:54:17.97$vck44/vb=8,4 2006.201.13:54:17.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.13:54:17.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.13:54:17.97#ibcon#ireg 11 cls_cnt 2 2006.201.13:54:17.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:18.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:18.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:18.02#ibcon#enter wrdev, iclass 14, count 2 2006.201.13:54:18.02#ibcon#first serial, iclass 14, count 2 2006.201.13:54:18.02#ibcon#enter sib2, iclass 14, count 2 2006.201.13:54:18.02#ibcon#flushed, iclass 14, count 2 2006.201.13:54:18.02#ibcon#about to write, iclass 14, count 2 2006.201.13:54:18.02#ibcon#wrote, iclass 14, count 2 2006.201.13:54:18.02#ibcon#about to read 3, iclass 14, count 2 2006.201.13:54:18.04#ibcon#read 3, iclass 14, count 2 2006.201.13:54:18.04#ibcon#about to read 4, iclass 14, count 2 2006.201.13:54:18.04#ibcon#read 4, iclass 14, count 2 2006.201.13:54:18.04#ibcon#about to read 5, iclass 14, count 2 2006.201.13:54:18.04#ibcon#read 5, iclass 14, count 2 2006.201.13:54:18.04#ibcon#about to read 6, iclass 14, count 2 2006.201.13:54:18.04#ibcon#read 6, iclass 14, count 2 2006.201.13:54:18.04#ibcon#end of sib2, iclass 14, count 2 2006.201.13:54:18.04#ibcon#*mode == 0, iclass 14, count 2 2006.201.13:54:18.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.13:54:18.04#ibcon#[27=AT08-04\r\n] 2006.201.13:54:18.04#ibcon#*before write, iclass 14, count 2 2006.201.13:54:18.04#ibcon#enter sib2, iclass 14, count 2 2006.201.13:54:18.04#ibcon#flushed, iclass 14, count 2 2006.201.13:54:18.04#ibcon#about to write, iclass 14, count 2 2006.201.13:54:18.04#ibcon#wrote, iclass 14, count 2 2006.201.13:54:18.04#ibcon#about to read 3, iclass 14, count 2 2006.201.13:54:18.07#ibcon#read 3, iclass 14, count 2 2006.201.13:54:18.07#ibcon#about to read 4, iclass 14, count 2 2006.201.13:54:18.07#ibcon#read 4, iclass 14, count 2 2006.201.13:54:18.07#ibcon#about to read 5, iclass 14, count 2 2006.201.13:54:18.07#ibcon#read 5, iclass 14, count 2 2006.201.13:54:18.07#ibcon#about to read 6, iclass 14, count 2 2006.201.13:54:18.07#ibcon#read 6, iclass 14, count 2 2006.201.13:54:18.07#ibcon#end of sib2, iclass 14, count 2 2006.201.13:54:18.07#ibcon#*after write, iclass 14, count 2 2006.201.13:54:18.07#ibcon#*before return 0, iclass 14, count 2 2006.201.13:54:18.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:18.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.13:54:18.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.13:54:18.07#ibcon#ireg 7 cls_cnt 0 2006.201.13:54:18.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:18.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:18.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:18.19#ibcon#enter wrdev, iclass 14, count 0 2006.201.13:54:18.19#ibcon#first serial, iclass 14, count 0 2006.201.13:54:18.19#ibcon#enter sib2, iclass 14, count 0 2006.201.13:54:18.19#ibcon#flushed, iclass 14, count 0 2006.201.13:54:18.19#ibcon#about to write, iclass 14, count 0 2006.201.13:54:18.19#ibcon#wrote, iclass 14, count 0 2006.201.13:54:18.19#ibcon#about to read 3, iclass 14, count 0 2006.201.13:54:18.21#ibcon#read 3, iclass 14, count 0 2006.201.13:54:18.21#ibcon#about to read 4, iclass 14, count 0 2006.201.13:54:18.21#ibcon#read 4, iclass 14, count 0 2006.201.13:54:18.21#ibcon#about to read 5, iclass 14, count 0 2006.201.13:54:18.21#ibcon#read 5, iclass 14, count 0 2006.201.13:54:18.21#ibcon#about to read 6, iclass 14, count 0 2006.201.13:54:18.21#ibcon#read 6, iclass 14, count 0 2006.201.13:54:18.21#ibcon#end of sib2, iclass 14, count 0 2006.201.13:54:18.21#ibcon#*mode == 0, iclass 14, count 0 2006.201.13:54:18.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.13:54:18.21#ibcon#[27=USB\r\n] 2006.201.13:54:18.21#ibcon#*before write, iclass 14, count 0 2006.201.13:54:18.21#ibcon#enter sib2, iclass 14, count 0 2006.201.13:54:18.21#ibcon#flushed, iclass 14, count 0 2006.201.13:54:18.21#ibcon#about to write, iclass 14, count 0 2006.201.13:54:18.21#ibcon#wrote, iclass 14, count 0 2006.201.13:54:18.21#ibcon#about to read 3, iclass 14, count 0 2006.201.13:54:18.24#ibcon#read 3, iclass 14, count 0 2006.201.13:54:18.24#ibcon#about to read 4, iclass 14, count 0 2006.201.13:54:18.24#ibcon#read 4, iclass 14, count 0 2006.201.13:54:18.24#ibcon#about to read 5, iclass 14, count 0 2006.201.13:54:18.24#ibcon#read 5, iclass 14, count 0 2006.201.13:54:18.24#ibcon#about to read 6, iclass 14, count 0 2006.201.13:54:18.24#ibcon#read 6, iclass 14, count 0 2006.201.13:54:18.24#ibcon#end of sib2, iclass 14, count 0 2006.201.13:54:18.24#ibcon#*after write, iclass 14, count 0 2006.201.13:54:18.24#ibcon#*before return 0, iclass 14, count 0 2006.201.13:54:18.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:18.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.13:54:18.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.13:54:18.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.13:54:18.24$vck44/vabw=wide 2006.201.13:54:18.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.13:54:18.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.13:54:18.24#ibcon#ireg 8 cls_cnt 0 2006.201.13:54:18.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:18.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:18.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:18.24#ibcon#enter wrdev, iclass 16, count 0 2006.201.13:54:18.24#ibcon#first serial, iclass 16, count 0 2006.201.13:54:18.24#ibcon#enter sib2, iclass 16, count 0 2006.201.13:54:18.24#ibcon#flushed, iclass 16, count 0 2006.201.13:54:18.24#ibcon#about to write, iclass 16, count 0 2006.201.13:54:18.24#ibcon#wrote, iclass 16, count 0 2006.201.13:54:18.24#ibcon#about to read 3, iclass 16, count 0 2006.201.13:54:18.26#ibcon#read 3, iclass 16, count 0 2006.201.13:54:18.26#ibcon#about to read 4, iclass 16, count 0 2006.201.13:54:18.26#ibcon#read 4, iclass 16, count 0 2006.201.13:54:18.26#ibcon#about to read 5, iclass 16, count 0 2006.201.13:54:18.26#ibcon#read 5, iclass 16, count 0 2006.201.13:54:18.26#ibcon#about to read 6, iclass 16, count 0 2006.201.13:54:18.26#ibcon#read 6, iclass 16, count 0 2006.201.13:54:18.26#ibcon#end of sib2, iclass 16, count 0 2006.201.13:54:18.26#ibcon#*mode == 0, iclass 16, count 0 2006.201.13:54:18.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.13:54:18.26#ibcon#[25=BW32\r\n] 2006.201.13:54:18.26#ibcon#*before write, iclass 16, count 0 2006.201.13:54:18.26#ibcon#enter sib2, iclass 16, count 0 2006.201.13:54:18.26#ibcon#flushed, iclass 16, count 0 2006.201.13:54:18.26#ibcon#about to write, iclass 16, count 0 2006.201.13:54:18.26#ibcon#wrote, iclass 16, count 0 2006.201.13:54:18.26#ibcon#about to read 3, iclass 16, count 0 2006.201.13:54:18.29#ibcon#read 3, iclass 16, count 0 2006.201.13:54:18.29#ibcon#about to read 4, iclass 16, count 0 2006.201.13:54:18.29#ibcon#read 4, iclass 16, count 0 2006.201.13:54:18.29#ibcon#about to read 5, iclass 16, count 0 2006.201.13:54:18.29#ibcon#read 5, iclass 16, count 0 2006.201.13:54:18.29#ibcon#about to read 6, iclass 16, count 0 2006.201.13:54:18.29#ibcon#read 6, iclass 16, count 0 2006.201.13:54:18.29#ibcon#end of sib2, iclass 16, count 0 2006.201.13:54:18.29#ibcon#*after write, iclass 16, count 0 2006.201.13:54:18.29#ibcon#*before return 0, iclass 16, count 0 2006.201.13:54:18.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:18.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.13:54:18.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.13:54:18.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.13:54:18.29$vck44/vbbw=wide 2006.201.13:54:18.29#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.13:54:18.29#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.13:54:18.29#ibcon#ireg 8 cls_cnt 0 2006.201.13:54:18.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:54:18.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:54:18.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:54:18.36#ibcon#enter wrdev, iclass 18, count 0 2006.201.13:54:18.36#ibcon#first serial, iclass 18, count 0 2006.201.13:54:18.36#ibcon#enter sib2, iclass 18, count 0 2006.201.13:54:18.36#ibcon#flushed, iclass 18, count 0 2006.201.13:54:18.36#ibcon#about to write, iclass 18, count 0 2006.201.13:54:18.36#ibcon#wrote, iclass 18, count 0 2006.201.13:54:18.36#ibcon#about to read 3, iclass 18, count 0 2006.201.13:54:18.38#ibcon#read 3, iclass 18, count 0 2006.201.13:54:18.38#ibcon#about to read 4, iclass 18, count 0 2006.201.13:54:18.38#ibcon#read 4, iclass 18, count 0 2006.201.13:54:18.38#ibcon#about to read 5, iclass 18, count 0 2006.201.13:54:18.38#ibcon#read 5, iclass 18, count 0 2006.201.13:54:18.38#ibcon#about to read 6, iclass 18, count 0 2006.201.13:54:18.38#ibcon#read 6, iclass 18, count 0 2006.201.13:54:18.38#ibcon#end of sib2, iclass 18, count 0 2006.201.13:54:18.38#ibcon#*mode == 0, iclass 18, count 0 2006.201.13:54:18.38#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.13:54:18.38#ibcon#[27=BW32\r\n] 2006.201.13:54:18.38#ibcon#*before write, iclass 18, count 0 2006.201.13:54:18.38#ibcon#enter sib2, iclass 18, count 0 2006.201.13:54:18.38#ibcon#flushed, iclass 18, count 0 2006.201.13:54:18.38#ibcon#about to write, iclass 18, count 0 2006.201.13:54:18.38#ibcon#wrote, iclass 18, count 0 2006.201.13:54:18.38#ibcon#about to read 3, iclass 18, count 0 2006.201.13:54:18.41#ibcon#read 3, iclass 18, count 0 2006.201.13:54:18.41#ibcon#about to read 4, iclass 18, count 0 2006.201.13:54:18.41#ibcon#read 4, iclass 18, count 0 2006.201.13:54:18.41#ibcon#about to read 5, iclass 18, count 0 2006.201.13:54:18.41#ibcon#read 5, iclass 18, count 0 2006.201.13:54:18.41#ibcon#about to read 6, iclass 18, count 0 2006.201.13:54:18.41#ibcon#read 6, iclass 18, count 0 2006.201.13:54:18.41#ibcon#end of sib2, iclass 18, count 0 2006.201.13:54:18.41#ibcon#*after write, iclass 18, count 0 2006.201.13:54:18.41#ibcon#*before return 0, iclass 18, count 0 2006.201.13:54:18.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:54:18.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.13:54:18.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.13:54:18.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.13:54:18.41$setupk4/ifdk4 2006.201.13:54:18.41$ifdk4/lo= 2006.201.13:54:18.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:54:18.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:54:18.41$ifdk4/patch= 2006.201.13:54:18.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:54:18.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:54:18.41$setupk4/!*+20s 2006.201.13:54:26.87#abcon#<5=/04 1.2 2.3 20.881001004.0\r\n> 2006.201.13:54:26.89#abcon#{5=INTERFACE CLEAR} 2006.201.13:54:26.95#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:54:32.88$setupk4/"tpicd 2006.201.13:54:32.88$setupk4/echo=off 2006.201.13:54:32.88$setupk4/xlog=off 2006.201.13:54:32.88:!2006.201.13:58:45 2006.201.13:54:39.14#trakl#Source acquired 2006.201.13:54:41.14#flagr#flagr/antenna,acquired 2006.201.13:58:45.00:preob 2006.201.13:58:45.14/onsource/TRACKING 2006.201.13:58:45.14:!2006.201.13:58:55 2006.201.13:58:55.00:"tape 2006.201.13:58:55.00:"st=record 2006.201.13:58:55.00:data_valid=on 2006.201.13:58:55.00:midob 2006.201.13:58:56.14/onsource/TRACKING 2006.201.13:58:56.14/wx/20.87,1004.1,100 2006.201.13:58:56.32/cable/+6.4747E-03 2006.201.13:58:57.41/va/01,08,usb,yes,29,31 2006.201.13:58:57.41/va/02,07,usb,yes,31,32 2006.201.13:58:57.41/va/03,08,usb,yes,28,30 2006.201.13:58:57.41/va/04,07,usb,yes,32,34 2006.201.13:58:57.41/va/05,04,usb,yes,28,29 2006.201.13:58:57.41/va/06,05,usb,yes,28,28 2006.201.13:58:57.41/va/07,05,usb,yes,28,29 2006.201.13:58:57.41/va/08,04,usb,yes,28,33 2006.201.13:58:57.64/valo/01,524.99,yes,locked 2006.201.13:58:57.64/valo/02,534.99,yes,locked 2006.201.13:58:57.64/valo/03,564.99,yes,locked 2006.201.13:58:57.64/valo/04,624.99,yes,locked 2006.201.13:58:57.64/valo/05,734.99,yes,locked 2006.201.13:58:57.64/valo/06,814.99,yes,locked 2006.201.13:58:57.64/valo/07,864.99,yes,locked 2006.201.13:58:57.64/valo/08,884.99,yes,locked 2006.201.13:58:58.73/vb/01,04,usb,yes,29,27 2006.201.13:58:58.73/vb/02,05,usb,yes,27,27 2006.201.13:58:58.73/vb/03,04,usb,yes,28,31 2006.201.13:58:58.73/vb/04,05,usb,yes,28,27 2006.201.13:58:58.73/vb/05,04,usb,yes,25,27 2006.201.13:58:58.73/vb/06,04,usb,yes,29,26 2006.201.13:58:58.73/vb/07,04,usb,yes,29,29 2006.201.13:58:58.73/vb/08,04,usb,yes,27,30 2006.201.13:58:58.97/vblo/01,629.99,yes,locked 2006.201.13:58:58.97/vblo/02,634.99,yes,locked 2006.201.13:58:58.97/vblo/03,649.99,yes,locked 2006.201.13:58:58.97/vblo/04,679.99,yes,locked 2006.201.13:58:58.97/vblo/05,709.99,yes,locked 2006.201.13:58:58.97/vblo/06,719.99,yes,locked 2006.201.13:58:58.97/vblo/07,734.99,yes,locked 2006.201.13:58:58.97/vblo/08,744.99,yes,locked 2006.201.13:58:59.12/vabw/8 2006.201.13:58:59.27/vbbw/8 2006.201.13:58:59.37/xfe/off,on,14.7 2006.201.13:58:59.77/ifatt/23,28,28,28 2006.201.13:59:00.06/fmout-gps/S +4.51E-07 2006.201.13:59:00.13:!2006.201.13:59:35 2006.201.13:59:35.00:data_valid=off 2006.201.13:59:35.00:"et 2006.201.13:59:35.00:!+3s 2006.201.13:59:38.02:"tape 2006.201.13:59:38.02:postob 2006.201.13:59:38.24/cable/+6.4767E-03 2006.201.13:59:38.24/wx/20.87,1004.0,100 2006.201.13:59:38.32/fmout-gps/S +4.52E-07 2006.201.13:59:38.32:scan_name=201-1400,jd0607,40 2006.201.13:59:38.32:source=2134+00,213638.59,004154.2,2000.0,cw 2006.201.13:59:40.14#flagr#flagr/antenna,new-source 2006.201.13:59:40.14:checkk5 2006.201.13:59:40.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.13:59:40.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.13:59:41.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.13:59:41.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.13:59:42.00/chk_obsdata//k5ts1/T2011358??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.13:59:42.37/chk_obsdata//k5ts2/T2011358??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.13:59:42.73/chk_obsdata//k5ts3/T2011358??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.13:59:43.10/chk_obsdata//k5ts4/T2011358??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.13:59:43.79/k5log//k5ts1_log_newline 2006.201.13:59:44.48/k5log//k5ts2_log_newline 2006.201.13:59:45.16/k5log//k5ts3_log_newline 2006.201.13:59:45.85/k5log//k5ts4_log_newline 2006.201.13:59:45.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.13:59:45.87:setupk4=1 2006.201.13:59:45.87$setupk4/echo=on 2006.201.13:59:45.87$setupk4/pcalon 2006.201.13:59:45.87$pcalon/"no phase cal control is implemented here 2006.201.13:59:45.87$setupk4/"tpicd=stop 2006.201.13:59:45.87$setupk4/"rec=synch_on 2006.201.13:59:45.87$setupk4/"rec_mode=128 2006.201.13:59:45.87$setupk4/!* 2006.201.13:59:45.87$setupk4/recpk4 2006.201.13:59:45.87$recpk4/recpatch= 2006.201.13:59:45.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.13:59:45.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.13:59:45.88$setupk4/vck44 2006.201.13:59:45.88$vck44/valo=1,524.99 2006.201.13:59:45.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.13:59:45.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.13:59:45.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:45.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:45.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:45.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:45.88#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:59:45.88#ibcon#first serial, iclass 5, count 0 2006.201.13:59:45.88#ibcon#enter sib2, iclass 5, count 0 2006.201.13:59:45.88#ibcon#flushed, iclass 5, count 0 2006.201.13:59:45.88#ibcon#about to write, iclass 5, count 0 2006.201.13:59:45.88#ibcon#wrote, iclass 5, count 0 2006.201.13:59:45.88#ibcon#about to read 3, iclass 5, count 0 2006.201.13:59:45.91#ibcon#read 3, iclass 5, count 0 2006.201.13:59:45.91#ibcon#about to read 4, iclass 5, count 0 2006.201.13:59:45.91#ibcon#read 4, iclass 5, count 0 2006.201.13:59:45.91#ibcon#about to read 5, iclass 5, count 0 2006.201.13:59:45.91#ibcon#read 5, iclass 5, count 0 2006.201.13:59:45.91#ibcon#about to read 6, iclass 5, count 0 2006.201.13:59:45.91#ibcon#read 6, iclass 5, count 0 2006.201.13:59:45.91#ibcon#end of sib2, iclass 5, count 0 2006.201.13:59:45.91#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:59:45.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:59:45.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.13:59:45.91#ibcon#*before write, iclass 5, count 0 2006.201.13:59:45.91#ibcon#enter sib2, iclass 5, count 0 2006.201.13:59:45.91#ibcon#flushed, iclass 5, count 0 2006.201.13:59:45.91#ibcon#about to write, iclass 5, count 0 2006.201.13:59:45.91#ibcon#wrote, iclass 5, count 0 2006.201.13:59:45.91#ibcon#about to read 3, iclass 5, count 0 2006.201.13:59:45.96#ibcon#read 3, iclass 5, count 0 2006.201.13:59:45.96#ibcon#about to read 4, iclass 5, count 0 2006.201.13:59:45.96#ibcon#read 4, iclass 5, count 0 2006.201.13:59:45.96#ibcon#about to read 5, iclass 5, count 0 2006.201.13:59:45.96#ibcon#read 5, iclass 5, count 0 2006.201.13:59:45.96#ibcon#about to read 6, iclass 5, count 0 2006.201.13:59:45.96#ibcon#read 6, iclass 5, count 0 2006.201.13:59:45.96#ibcon#end of sib2, iclass 5, count 0 2006.201.13:59:45.96#ibcon#*after write, iclass 5, count 0 2006.201.13:59:45.96#ibcon#*before return 0, iclass 5, count 0 2006.201.13:59:45.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:45.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:45.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:59:45.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:59:45.96$vck44/va=1,8 2006.201.13:59:45.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.13:59:45.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.13:59:45.96#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:45.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:45.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:45.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:45.96#ibcon#enter wrdev, iclass 7, count 2 2006.201.13:59:45.96#ibcon#first serial, iclass 7, count 2 2006.201.13:59:45.96#ibcon#enter sib2, iclass 7, count 2 2006.201.13:59:45.96#ibcon#flushed, iclass 7, count 2 2006.201.13:59:45.96#ibcon#about to write, iclass 7, count 2 2006.201.13:59:45.96#ibcon#wrote, iclass 7, count 2 2006.201.13:59:45.96#ibcon#about to read 3, iclass 7, count 2 2006.201.13:59:45.98#ibcon#read 3, iclass 7, count 2 2006.201.13:59:45.98#ibcon#about to read 4, iclass 7, count 2 2006.201.13:59:45.98#ibcon#read 4, iclass 7, count 2 2006.201.13:59:45.98#ibcon#about to read 5, iclass 7, count 2 2006.201.13:59:45.98#ibcon#read 5, iclass 7, count 2 2006.201.13:59:45.98#ibcon#about to read 6, iclass 7, count 2 2006.201.13:59:45.98#ibcon#read 6, iclass 7, count 2 2006.201.13:59:45.98#ibcon#end of sib2, iclass 7, count 2 2006.201.13:59:45.98#ibcon#*mode == 0, iclass 7, count 2 2006.201.13:59:45.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.13:59:45.98#ibcon#[25=AT01-08\r\n] 2006.201.13:59:45.98#ibcon#*before write, iclass 7, count 2 2006.201.13:59:45.98#ibcon#enter sib2, iclass 7, count 2 2006.201.13:59:45.98#ibcon#flushed, iclass 7, count 2 2006.201.13:59:45.98#ibcon#about to write, iclass 7, count 2 2006.201.13:59:45.98#ibcon#wrote, iclass 7, count 2 2006.201.13:59:45.98#ibcon#about to read 3, iclass 7, count 2 2006.201.13:59:46.01#ibcon#read 3, iclass 7, count 2 2006.201.13:59:46.01#ibcon#about to read 4, iclass 7, count 2 2006.201.13:59:46.01#ibcon#read 4, iclass 7, count 2 2006.201.13:59:46.01#ibcon#about to read 5, iclass 7, count 2 2006.201.13:59:46.01#ibcon#read 5, iclass 7, count 2 2006.201.13:59:46.01#ibcon#about to read 6, iclass 7, count 2 2006.201.13:59:46.01#ibcon#read 6, iclass 7, count 2 2006.201.13:59:46.01#ibcon#end of sib2, iclass 7, count 2 2006.201.13:59:46.01#ibcon#*after write, iclass 7, count 2 2006.201.13:59:46.01#ibcon#*before return 0, iclass 7, count 2 2006.201.13:59:46.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:46.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:46.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.13:59:46.01#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:46.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:46.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:46.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:46.13#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:59:46.13#ibcon#first serial, iclass 7, count 0 2006.201.13:59:46.13#ibcon#enter sib2, iclass 7, count 0 2006.201.13:59:46.13#ibcon#flushed, iclass 7, count 0 2006.201.13:59:46.13#ibcon#about to write, iclass 7, count 0 2006.201.13:59:46.13#ibcon#wrote, iclass 7, count 0 2006.201.13:59:46.13#ibcon#about to read 3, iclass 7, count 0 2006.201.13:59:46.15#ibcon#read 3, iclass 7, count 0 2006.201.13:59:46.15#ibcon#about to read 4, iclass 7, count 0 2006.201.13:59:46.15#ibcon#read 4, iclass 7, count 0 2006.201.13:59:46.15#ibcon#about to read 5, iclass 7, count 0 2006.201.13:59:46.15#ibcon#read 5, iclass 7, count 0 2006.201.13:59:46.15#ibcon#about to read 6, iclass 7, count 0 2006.201.13:59:46.15#ibcon#read 6, iclass 7, count 0 2006.201.13:59:46.15#ibcon#end of sib2, iclass 7, count 0 2006.201.13:59:46.15#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:59:46.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:59:46.15#ibcon#[25=USB\r\n] 2006.201.13:59:46.15#ibcon#*before write, iclass 7, count 0 2006.201.13:59:46.15#ibcon#enter sib2, iclass 7, count 0 2006.201.13:59:46.15#ibcon#flushed, iclass 7, count 0 2006.201.13:59:46.15#ibcon#about to write, iclass 7, count 0 2006.201.13:59:46.15#ibcon#wrote, iclass 7, count 0 2006.201.13:59:46.15#ibcon#about to read 3, iclass 7, count 0 2006.201.13:59:46.18#ibcon#read 3, iclass 7, count 0 2006.201.13:59:46.18#ibcon#about to read 4, iclass 7, count 0 2006.201.13:59:46.18#ibcon#read 4, iclass 7, count 0 2006.201.13:59:46.18#ibcon#about to read 5, iclass 7, count 0 2006.201.13:59:46.18#ibcon#read 5, iclass 7, count 0 2006.201.13:59:46.18#ibcon#about to read 6, iclass 7, count 0 2006.201.13:59:46.18#ibcon#read 6, iclass 7, count 0 2006.201.13:59:46.18#ibcon#end of sib2, iclass 7, count 0 2006.201.13:59:46.18#ibcon#*after write, iclass 7, count 0 2006.201.13:59:46.18#ibcon#*before return 0, iclass 7, count 0 2006.201.13:59:46.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:46.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:46.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:59:46.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:59:46.18$vck44/valo=2,534.99 2006.201.13:59:46.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.13:59:46.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.13:59:46.18#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:46.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:46.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:46.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:46.18#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:59:46.18#ibcon#first serial, iclass 11, count 0 2006.201.13:59:46.18#ibcon#enter sib2, iclass 11, count 0 2006.201.13:59:46.18#ibcon#flushed, iclass 11, count 0 2006.201.13:59:46.18#ibcon#about to write, iclass 11, count 0 2006.201.13:59:46.18#ibcon#wrote, iclass 11, count 0 2006.201.13:59:46.18#ibcon#about to read 3, iclass 11, count 0 2006.201.13:59:46.20#ibcon#read 3, iclass 11, count 0 2006.201.13:59:46.20#ibcon#about to read 4, iclass 11, count 0 2006.201.13:59:46.20#ibcon#read 4, iclass 11, count 0 2006.201.13:59:46.20#ibcon#about to read 5, iclass 11, count 0 2006.201.13:59:46.20#ibcon#read 5, iclass 11, count 0 2006.201.13:59:46.20#ibcon#about to read 6, iclass 11, count 0 2006.201.13:59:46.20#ibcon#read 6, iclass 11, count 0 2006.201.13:59:46.20#ibcon#end of sib2, iclass 11, count 0 2006.201.13:59:46.20#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:59:46.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:59:46.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.13:59:46.20#ibcon#*before write, iclass 11, count 0 2006.201.13:59:46.20#ibcon#enter sib2, iclass 11, count 0 2006.201.13:59:46.20#ibcon#flushed, iclass 11, count 0 2006.201.13:59:46.20#ibcon#about to write, iclass 11, count 0 2006.201.13:59:46.20#ibcon#wrote, iclass 11, count 0 2006.201.13:59:46.20#ibcon#about to read 3, iclass 11, count 0 2006.201.13:59:46.25#ibcon#read 3, iclass 11, count 0 2006.201.13:59:46.25#ibcon#about to read 4, iclass 11, count 0 2006.201.13:59:46.25#ibcon#read 4, iclass 11, count 0 2006.201.13:59:46.25#ibcon#about to read 5, iclass 11, count 0 2006.201.13:59:46.25#ibcon#read 5, iclass 11, count 0 2006.201.13:59:46.25#ibcon#about to read 6, iclass 11, count 0 2006.201.13:59:46.25#ibcon#read 6, iclass 11, count 0 2006.201.13:59:46.25#ibcon#end of sib2, iclass 11, count 0 2006.201.13:59:46.25#ibcon#*after write, iclass 11, count 0 2006.201.13:59:46.25#ibcon#*before return 0, iclass 11, count 0 2006.201.13:59:46.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:46.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:46.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:59:46.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:59:46.25$vck44/va=2,7 2006.201.13:59:46.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.13:59:46.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.13:59:46.25#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:46.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:46.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:46.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:46.30#ibcon#enter wrdev, iclass 13, count 2 2006.201.13:59:46.30#ibcon#first serial, iclass 13, count 2 2006.201.13:59:46.30#ibcon#enter sib2, iclass 13, count 2 2006.201.13:59:46.30#ibcon#flushed, iclass 13, count 2 2006.201.13:59:46.30#ibcon#about to write, iclass 13, count 2 2006.201.13:59:46.30#ibcon#wrote, iclass 13, count 2 2006.201.13:59:46.30#ibcon#about to read 3, iclass 13, count 2 2006.201.13:59:46.32#ibcon#read 3, iclass 13, count 2 2006.201.13:59:46.32#ibcon#about to read 4, iclass 13, count 2 2006.201.13:59:46.32#ibcon#read 4, iclass 13, count 2 2006.201.13:59:46.32#ibcon#about to read 5, iclass 13, count 2 2006.201.13:59:46.32#ibcon#read 5, iclass 13, count 2 2006.201.13:59:46.32#ibcon#about to read 6, iclass 13, count 2 2006.201.13:59:46.32#ibcon#read 6, iclass 13, count 2 2006.201.13:59:46.32#ibcon#end of sib2, iclass 13, count 2 2006.201.13:59:46.32#ibcon#*mode == 0, iclass 13, count 2 2006.201.13:59:46.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.13:59:46.32#ibcon#[25=AT02-07\r\n] 2006.201.13:59:46.32#ibcon#*before write, iclass 13, count 2 2006.201.13:59:46.32#ibcon#enter sib2, iclass 13, count 2 2006.201.13:59:46.32#ibcon#flushed, iclass 13, count 2 2006.201.13:59:46.32#ibcon#about to write, iclass 13, count 2 2006.201.13:59:46.32#ibcon#wrote, iclass 13, count 2 2006.201.13:59:46.32#ibcon#about to read 3, iclass 13, count 2 2006.201.13:59:46.35#ibcon#read 3, iclass 13, count 2 2006.201.13:59:46.35#ibcon#about to read 4, iclass 13, count 2 2006.201.13:59:46.35#ibcon#read 4, iclass 13, count 2 2006.201.13:59:46.35#ibcon#about to read 5, iclass 13, count 2 2006.201.13:59:46.35#ibcon#read 5, iclass 13, count 2 2006.201.13:59:46.35#ibcon#about to read 6, iclass 13, count 2 2006.201.13:59:46.35#ibcon#read 6, iclass 13, count 2 2006.201.13:59:46.35#ibcon#end of sib2, iclass 13, count 2 2006.201.13:59:46.35#ibcon#*after write, iclass 13, count 2 2006.201.13:59:46.35#ibcon#*before return 0, iclass 13, count 2 2006.201.13:59:46.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:46.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:46.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.13:59:46.35#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:46.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:46.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:46.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:46.47#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:59:46.47#ibcon#first serial, iclass 13, count 0 2006.201.13:59:46.47#ibcon#enter sib2, iclass 13, count 0 2006.201.13:59:46.47#ibcon#flushed, iclass 13, count 0 2006.201.13:59:46.47#ibcon#about to write, iclass 13, count 0 2006.201.13:59:46.47#ibcon#wrote, iclass 13, count 0 2006.201.13:59:46.47#ibcon#about to read 3, iclass 13, count 0 2006.201.13:59:46.49#ibcon#read 3, iclass 13, count 0 2006.201.13:59:46.49#ibcon#about to read 4, iclass 13, count 0 2006.201.13:59:46.49#ibcon#read 4, iclass 13, count 0 2006.201.13:59:46.49#ibcon#about to read 5, iclass 13, count 0 2006.201.13:59:46.49#ibcon#read 5, iclass 13, count 0 2006.201.13:59:46.49#ibcon#about to read 6, iclass 13, count 0 2006.201.13:59:46.49#ibcon#read 6, iclass 13, count 0 2006.201.13:59:46.49#ibcon#end of sib2, iclass 13, count 0 2006.201.13:59:46.49#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:59:46.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:59:46.49#ibcon#[25=USB\r\n] 2006.201.13:59:46.49#ibcon#*before write, iclass 13, count 0 2006.201.13:59:46.49#ibcon#enter sib2, iclass 13, count 0 2006.201.13:59:46.49#ibcon#flushed, iclass 13, count 0 2006.201.13:59:46.49#ibcon#about to write, iclass 13, count 0 2006.201.13:59:46.49#ibcon#wrote, iclass 13, count 0 2006.201.13:59:46.49#ibcon#about to read 3, iclass 13, count 0 2006.201.13:59:46.52#ibcon#read 3, iclass 13, count 0 2006.201.13:59:46.52#ibcon#about to read 4, iclass 13, count 0 2006.201.13:59:46.52#ibcon#read 4, iclass 13, count 0 2006.201.13:59:46.52#ibcon#about to read 5, iclass 13, count 0 2006.201.13:59:46.52#ibcon#read 5, iclass 13, count 0 2006.201.13:59:46.52#ibcon#about to read 6, iclass 13, count 0 2006.201.13:59:46.52#ibcon#read 6, iclass 13, count 0 2006.201.13:59:46.52#ibcon#end of sib2, iclass 13, count 0 2006.201.13:59:46.52#ibcon#*after write, iclass 13, count 0 2006.201.13:59:46.52#ibcon#*before return 0, iclass 13, count 0 2006.201.13:59:46.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:46.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:46.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:59:46.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:59:46.52$vck44/valo=3,564.99 2006.201.13:59:46.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.13:59:46.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.13:59:46.52#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:46.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:46.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:46.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:46.52#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:59:46.52#ibcon#first serial, iclass 15, count 0 2006.201.13:59:46.52#ibcon#enter sib2, iclass 15, count 0 2006.201.13:59:46.52#ibcon#flushed, iclass 15, count 0 2006.201.13:59:46.52#ibcon#about to write, iclass 15, count 0 2006.201.13:59:46.52#ibcon#wrote, iclass 15, count 0 2006.201.13:59:46.52#ibcon#about to read 3, iclass 15, count 0 2006.201.13:59:46.54#ibcon#read 3, iclass 15, count 0 2006.201.13:59:46.54#ibcon#about to read 4, iclass 15, count 0 2006.201.13:59:46.54#ibcon#read 4, iclass 15, count 0 2006.201.13:59:46.54#ibcon#about to read 5, iclass 15, count 0 2006.201.13:59:46.54#ibcon#read 5, iclass 15, count 0 2006.201.13:59:46.54#ibcon#about to read 6, iclass 15, count 0 2006.201.13:59:46.54#ibcon#read 6, iclass 15, count 0 2006.201.13:59:46.54#ibcon#end of sib2, iclass 15, count 0 2006.201.13:59:46.54#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:59:46.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:59:46.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.13:59:46.54#ibcon#*before write, iclass 15, count 0 2006.201.13:59:46.54#ibcon#enter sib2, iclass 15, count 0 2006.201.13:59:46.54#ibcon#flushed, iclass 15, count 0 2006.201.13:59:46.54#ibcon#about to write, iclass 15, count 0 2006.201.13:59:46.54#ibcon#wrote, iclass 15, count 0 2006.201.13:59:46.54#ibcon#about to read 3, iclass 15, count 0 2006.201.13:59:46.58#ibcon#read 3, iclass 15, count 0 2006.201.13:59:46.58#ibcon#about to read 4, iclass 15, count 0 2006.201.13:59:46.58#ibcon#read 4, iclass 15, count 0 2006.201.13:59:46.58#ibcon#about to read 5, iclass 15, count 0 2006.201.13:59:46.58#ibcon#read 5, iclass 15, count 0 2006.201.13:59:46.58#ibcon#about to read 6, iclass 15, count 0 2006.201.13:59:46.58#ibcon#read 6, iclass 15, count 0 2006.201.13:59:46.58#ibcon#end of sib2, iclass 15, count 0 2006.201.13:59:46.58#ibcon#*after write, iclass 15, count 0 2006.201.13:59:46.58#ibcon#*before return 0, iclass 15, count 0 2006.201.13:59:46.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:46.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:46.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:59:46.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:59:46.58$vck44/va=3,8 2006.201.13:59:46.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.13:59:46.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.13:59:46.58#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:46.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:46.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:46.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:46.64#ibcon#enter wrdev, iclass 17, count 2 2006.201.13:59:46.64#ibcon#first serial, iclass 17, count 2 2006.201.13:59:46.64#ibcon#enter sib2, iclass 17, count 2 2006.201.13:59:46.64#ibcon#flushed, iclass 17, count 2 2006.201.13:59:46.64#ibcon#about to write, iclass 17, count 2 2006.201.13:59:46.64#ibcon#wrote, iclass 17, count 2 2006.201.13:59:46.64#ibcon#about to read 3, iclass 17, count 2 2006.201.13:59:46.66#ibcon#read 3, iclass 17, count 2 2006.201.13:59:46.66#ibcon#about to read 4, iclass 17, count 2 2006.201.13:59:46.66#ibcon#read 4, iclass 17, count 2 2006.201.13:59:46.66#ibcon#about to read 5, iclass 17, count 2 2006.201.13:59:46.66#ibcon#read 5, iclass 17, count 2 2006.201.13:59:46.66#ibcon#about to read 6, iclass 17, count 2 2006.201.13:59:46.66#ibcon#read 6, iclass 17, count 2 2006.201.13:59:46.66#ibcon#end of sib2, iclass 17, count 2 2006.201.13:59:46.66#ibcon#*mode == 0, iclass 17, count 2 2006.201.13:59:46.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.13:59:46.66#ibcon#[25=AT03-08\r\n] 2006.201.13:59:46.66#ibcon#*before write, iclass 17, count 2 2006.201.13:59:46.66#ibcon#enter sib2, iclass 17, count 2 2006.201.13:59:46.66#ibcon#flushed, iclass 17, count 2 2006.201.13:59:46.66#ibcon#about to write, iclass 17, count 2 2006.201.13:59:46.66#ibcon#wrote, iclass 17, count 2 2006.201.13:59:46.66#ibcon#about to read 3, iclass 17, count 2 2006.201.13:59:46.69#ibcon#read 3, iclass 17, count 2 2006.201.13:59:46.69#ibcon#about to read 4, iclass 17, count 2 2006.201.13:59:46.69#ibcon#read 4, iclass 17, count 2 2006.201.13:59:46.69#ibcon#about to read 5, iclass 17, count 2 2006.201.13:59:46.69#ibcon#read 5, iclass 17, count 2 2006.201.13:59:46.69#ibcon#about to read 6, iclass 17, count 2 2006.201.13:59:46.69#ibcon#read 6, iclass 17, count 2 2006.201.13:59:46.69#ibcon#end of sib2, iclass 17, count 2 2006.201.13:59:46.69#ibcon#*after write, iclass 17, count 2 2006.201.13:59:46.69#ibcon#*before return 0, iclass 17, count 2 2006.201.13:59:46.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:46.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:46.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.13:59:46.69#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:46.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:46.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:46.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:46.81#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:59:46.81#ibcon#first serial, iclass 17, count 0 2006.201.13:59:46.81#ibcon#enter sib2, iclass 17, count 0 2006.201.13:59:46.81#ibcon#flushed, iclass 17, count 0 2006.201.13:59:46.81#ibcon#about to write, iclass 17, count 0 2006.201.13:59:46.81#ibcon#wrote, iclass 17, count 0 2006.201.13:59:46.81#ibcon#about to read 3, iclass 17, count 0 2006.201.13:59:46.83#ibcon#read 3, iclass 17, count 0 2006.201.13:59:46.83#ibcon#about to read 4, iclass 17, count 0 2006.201.13:59:46.83#ibcon#read 4, iclass 17, count 0 2006.201.13:59:46.83#ibcon#about to read 5, iclass 17, count 0 2006.201.13:59:46.83#ibcon#read 5, iclass 17, count 0 2006.201.13:59:46.83#ibcon#about to read 6, iclass 17, count 0 2006.201.13:59:46.83#ibcon#read 6, iclass 17, count 0 2006.201.13:59:46.83#ibcon#end of sib2, iclass 17, count 0 2006.201.13:59:46.83#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:59:46.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:59:46.83#ibcon#[25=USB\r\n] 2006.201.13:59:46.83#ibcon#*before write, iclass 17, count 0 2006.201.13:59:46.83#ibcon#enter sib2, iclass 17, count 0 2006.201.13:59:46.83#ibcon#flushed, iclass 17, count 0 2006.201.13:59:46.83#ibcon#about to write, iclass 17, count 0 2006.201.13:59:46.83#ibcon#wrote, iclass 17, count 0 2006.201.13:59:46.83#ibcon#about to read 3, iclass 17, count 0 2006.201.13:59:46.86#ibcon#read 3, iclass 17, count 0 2006.201.13:59:46.86#ibcon#about to read 4, iclass 17, count 0 2006.201.13:59:46.86#ibcon#read 4, iclass 17, count 0 2006.201.13:59:46.86#ibcon#about to read 5, iclass 17, count 0 2006.201.13:59:46.86#ibcon#read 5, iclass 17, count 0 2006.201.13:59:46.86#ibcon#about to read 6, iclass 17, count 0 2006.201.13:59:46.86#ibcon#read 6, iclass 17, count 0 2006.201.13:59:46.86#ibcon#end of sib2, iclass 17, count 0 2006.201.13:59:46.86#ibcon#*after write, iclass 17, count 0 2006.201.13:59:46.86#ibcon#*before return 0, iclass 17, count 0 2006.201.13:59:46.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:46.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:46.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:59:46.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:59:46.86$vck44/valo=4,624.99 2006.201.13:59:46.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.13:59:46.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.13:59:46.86#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:46.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:46.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:46.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:46.86#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:59:46.86#ibcon#first serial, iclass 19, count 0 2006.201.13:59:46.86#ibcon#enter sib2, iclass 19, count 0 2006.201.13:59:46.86#ibcon#flushed, iclass 19, count 0 2006.201.13:59:46.86#ibcon#about to write, iclass 19, count 0 2006.201.13:59:46.86#ibcon#wrote, iclass 19, count 0 2006.201.13:59:46.86#ibcon#about to read 3, iclass 19, count 0 2006.201.13:59:46.88#ibcon#read 3, iclass 19, count 0 2006.201.13:59:46.88#ibcon#about to read 4, iclass 19, count 0 2006.201.13:59:46.88#ibcon#read 4, iclass 19, count 0 2006.201.13:59:46.88#ibcon#about to read 5, iclass 19, count 0 2006.201.13:59:46.88#ibcon#read 5, iclass 19, count 0 2006.201.13:59:46.88#ibcon#about to read 6, iclass 19, count 0 2006.201.13:59:46.88#ibcon#read 6, iclass 19, count 0 2006.201.13:59:46.88#ibcon#end of sib2, iclass 19, count 0 2006.201.13:59:46.88#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:59:46.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:59:46.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.13:59:46.88#ibcon#*before write, iclass 19, count 0 2006.201.13:59:46.88#ibcon#enter sib2, iclass 19, count 0 2006.201.13:59:46.88#ibcon#flushed, iclass 19, count 0 2006.201.13:59:46.88#ibcon#about to write, iclass 19, count 0 2006.201.13:59:46.88#ibcon#wrote, iclass 19, count 0 2006.201.13:59:46.88#ibcon#about to read 3, iclass 19, count 0 2006.201.13:59:46.93#ibcon#read 3, iclass 19, count 0 2006.201.13:59:46.93#ibcon#about to read 4, iclass 19, count 0 2006.201.13:59:46.93#ibcon#read 4, iclass 19, count 0 2006.201.13:59:46.93#ibcon#about to read 5, iclass 19, count 0 2006.201.13:59:46.93#ibcon#read 5, iclass 19, count 0 2006.201.13:59:46.93#ibcon#about to read 6, iclass 19, count 0 2006.201.13:59:46.93#ibcon#read 6, iclass 19, count 0 2006.201.13:59:46.93#ibcon#end of sib2, iclass 19, count 0 2006.201.13:59:46.93#ibcon#*after write, iclass 19, count 0 2006.201.13:59:46.93#ibcon#*before return 0, iclass 19, count 0 2006.201.13:59:46.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:46.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:46.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:59:46.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:59:46.93$vck44/va=4,7 2006.201.13:59:46.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.13:59:46.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.13:59:46.93#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:46.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:46.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:46.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:46.98#ibcon#enter wrdev, iclass 21, count 2 2006.201.13:59:46.98#ibcon#first serial, iclass 21, count 2 2006.201.13:59:46.98#ibcon#enter sib2, iclass 21, count 2 2006.201.13:59:46.98#ibcon#flushed, iclass 21, count 2 2006.201.13:59:46.98#ibcon#about to write, iclass 21, count 2 2006.201.13:59:46.98#ibcon#wrote, iclass 21, count 2 2006.201.13:59:46.98#ibcon#about to read 3, iclass 21, count 2 2006.201.13:59:47.00#ibcon#read 3, iclass 21, count 2 2006.201.13:59:47.00#ibcon#about to read 4, iclass 21, count 2 2006.201.13:59:47.00#ibcon#read 4, iclass 21, count 2 2006.201.13:59:47.00#ibcon#about to read 5, iclass 21, count 2 2006.201.13:59:47.00#ibcon#read 5, iclass 21, count 2 2006.201.13:59:47.00#ibcon#about to read 6, iclass 21, count 2 2006.201.13:59:47.00#ibcon#read 6, iclass 21, count 2 2006.201.13:59:47.00#ibcon#end of sib2, iclass 21, count 2 2006.201.13:59:47.00#ibcon#*mode == 0, iclass 21, count 2 2006.201.13:59:47.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.13:59:47.00#ibcon#[25=AT04-07\r\n] 2006.201.13:59:47.00#ibcon#*before write, iclass 21, count 2 2006.201.13:59:47.00#ibcon#enter sib2, iclass 21, count 2 2006.201.13:59:47.00#ibcon#flushed, iclass 21, count 2 2006.201.13:59:47.00#ibcon#about to write, iclass 21, count 2 2006.201.13:59:47.00#ibcon#wrote, iclass 21, count 2 2006.201.13:59:47.00#ibcon#about to read 3, iclass 21, count 2 2006.201.13:59:47.03#ibcon#read 3, iclass 21, count 2 2006.201.13:59:47.03#ibcon#about to read 4, iclass 21, count 2 2006.201.13:59:47.03#ibcon#read 4, iclass 21, count 2 2006.201.13:59:47.03#ibcon#about to read 5, iclass 21, count 2 2006.201.13:59:47.03#ibcon#read 5, iclass 21, count 2 2006.201.13:59:47.03#ibcon#about to read 6, iclass 21, count 2 2006.201.13:59:47.03#ibcon#read 6, iclass 21, count 2 2006.201.13:59:47.03#ibcon#end of sib2, iclass 21, count 2 2006.201.13:59:47.03#ibcon#*after write, iclass 21, count 2 2006.201.13:59:47.03#ibcon#*before return 0, iclass 21, count 2 2006.201.13:59:47.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:47.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:47.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.13:59:47.03#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:47.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:47.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:47.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:47.15#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:59:47.15#ibcon#first serial, iclass 21, count 0 2006.201.13:59:47.15#ibcon#enter sib2, iclass 21, count 0 2006.201.13:59:47.15#ibcon#flushed, iclass 21, count 0 2006.201.13:59:47.15#ibcon#about to write, iclass 21, count 0 2006.201.13:59:47.15#ibcon#wrote, iclass 21, count 0 2006.201.13:59:47.15#ibcon#about to read 3, iclass 21, count 0 2006.201.13:59:47.17#ibcon#read 3, iclass 21, count 0 2006.201.13:59:47.17#ibcon#about to read 4, iclass 21, count 0 2006.201.13:59:47.17#ibcon#read 4, iclass 21, count 0 2006.201.13:59:47.17#ibcon#about to read 5, iclass 21, count 0 2006.201.13:59:47.17#ibcon#read 5, iclass 21, count 0 2006.201.13:59:47.17#ibcon#about to read 6, iclass 21, count 0 2006.201.13:59:47.17#ibcon#read 6, iclass 21, count 0 2006.201.13:59:47.17#ibcon#end of sib2, iclass 21, count 0 2006.201.13:59:47.17#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:59:47.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:59:47.17#ibcon#[25=USB\r\n] 2006.201.13:59:47.17#ibcon#*before write, iclass 21, count 0 2006.201.13:59:47.17#ibcon#enter sib2, iclass 21, count 0 2006.201.13:59:47.17#ibcon#flushed, iclass 21, count 0 2006.201.13:59:47.17#ibcon#about to write, iclass 21, count 0 2006.201.13:59:47.17#ibcon#wrote, iclass 21, count 0 2006.201.13:59:47.17#ibcon#about to read 3, iclass 21, count 0 2006.201.13:59:47.20#ibcon#read 3, iclass 21, count 0 2006.201.13:59:47.20#ibcon#about to read 4, iclass 21, count 0 2006.201.13:59:47.20#ibcon#read 4, iclass 21, count 0 2006.201.13:59:47.20#ibcon#about to read 5, iclass 21, count 0 2006.201.13:59:47.20#ibcon#read 5, iclass 21, count 0 2006.201.13:59:47.20#ibcon#about to read 6, iclass 21, count 0 2006.201.13:59:47.20#ibcon#read 6, iclass 21, count 0 2006.201.13:59:47.20#ibcon#end of sib2, iclass 21, count 0 2006.201.13:59:47.20#ibcon#*after write, iclass 21, count 0 2006.201.13:59:47.20#ibcon#*before return 0, iclass 21, count 0 2006.201.13:59:47.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:47.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:47.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:59:47.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:59:47.20$vck44/valo=5,734.99 2006.201.13:59:47.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.13:59:47.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.13:59:47.20#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:47.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:47.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:47.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:47.20#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:59:47.20#ibcon#first serial, iclass 23, count 0 2006.201.13:59:47.20#ibcon#enter sib2, iclass 23, count 0 2006.201.13:59:47.20#ibcon#flushed, iclass 23, count 0 2006.201.13:59:47.20#ibcon#about to write, iclass 23, count 0 2006.201.13:59:47.20#ibcon#wrote, iclass 23, count 0 2006.201.13:59:47.20#ibcon#about to read 3, iclass 23, count 0 2006.201.13:59:47.22#ibcon#read 3, iclass 23, count 0 2006.201.13:59:47.22#ibcon#about to read 4, iclass 23, count 0 2006.201.13:59:47.22#ibcon#read 4, iclass 23, count 0 2006.201.13:59:47.22#ibcon#about to read 5, iclass 23, count 0 2006.201.13:59:47.22#ibcon#read 5, iclass 23, count 0 2006.201.13:59:47.22#ibcon#about to read 6, iclass 23, count 0 2006.201.13:59:47.22#ibcon#read 6, iclass 23, count 0 2006.201.13:59:47.22#ibcon#end of sib2, iclass 23, count 0 2006.201.13:59:47.22#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:59:47.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:59:47.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.13:59:47.22#ibcon#*before write, iclass 23, count 0 2006.201.13:59:47.22#ibcon#enter sib2, iclass 23, count 0 2006.201.13:59:47.22#ibcon#flushed, iclass 23, count 0 2006.201.13:59:47.22#ibcon#about to write, iclass 23, count 0 2006.201.13:59:47.22#ibcon#wrote, iclass 23, count 0 2006.201.13:59:47.22#ibcon#about to read 3, iclass 23, count 0 2006.201.13:59:47.26#ibcon#read 3, iclass 23, count 0 2006.201.13:59:47.26#ibcon#about to read 4, iclass 23, count 0 2006.201.13:59:47.26#ibcon#read 4, iclass 23, count 0 2006.201.13:59:47.26#ibcon#about to read 5, iclass 23, count 0 2006.201.13:59:47.26#ibcon#read 5, iclass 23, count 0 2006.201.13:59:47.26#ibcon#about to read 6, iclass 23, count 0 2006.201.13:59:47.26#ibcon#read 6, iclass 23, count 0 2006.201.13:59:47.26#ibcon#end of sib2, iclass 23, count 0 2006.201.13:59:47.26#ibcon#*after write, iclass 23, count 0 2006.201.13:59:47.26#ibcon#*before return 0, iclass 23, count 0 2006.201.13:59:47.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:47.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:47.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:59:47.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:59:47.26$vck44/va=5,4 2006.201.13:59:47.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.13:59:47.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.13:59:47.26#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:47.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:47.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:47.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:47.32#ibcon#enter wrdev, iclass 25, count 2 2006.201.13:59:47.32#ibcon#first serial, iclass 25, count 2 2006.201.13:59:47.32#ibcon#enter sib2, iclass 25, count 2 2006.201.13:59:47.32#ibcon#flushed, iclass 25, count 2 2006.201.13:59:47.32#ibcon#about to write, iclass 25, count 2 2006.201.13:59:47.32#ibcon#wrote, iclass 25, count 2 2006.201.13:59:47.32#ibcon#about to read 3, iclass 25, count 2 2006.201.13:59:47.34#ibcon#read 3, iclass 25, count 2 2006.201.13:59:47.34#ibcon#about to read 4, iclass 25, count 2 2006.201.13:59:47.34#ibcon#read 4, iclass 25, count 2 2006.201.13:59:47.34#ibcon#about to read 5, iclass 25, count 2 2006.201.13:59:47.34#ibcon#read 5, iclass 25, count 2 2006.201.13:59:47.34#ibcon#about to read 6, iclass 25, count 2 2006.201.13:59:47.34#ibcon#read 6, iclass 25, count 2 2006.201.13:59:47.34#ibcon#end of sib2, iclass 25, count 2 2006.201.13:59:47.34#ibcon#*mode == 0, iclass 25, count 2 2006.201.13:59:47.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.13:59:47.34#ibcon#[25=AT05-04\r\n] 2006.201.13:59:47.34#ibcon#*before write, iclass 25, count 2 2006.201.13:59:47.34#ibcon#enter sib2, iclass 25, count 2 2006.201.13:59:47.34#ibcon#flushed, iclass 25, count 2 2006.201.13:59:47.34#ibcon#about to write, iclass 25, count 2 2006.201.13:59:47.34#ibcon#wrote, iclass 25, count 2 2006.201.13:59:47.34#ibcon#about to read 3, iclass 25, count 2 2006.201.13:59:47.37#ibcon#read 3, iclass 25, count 2 2006.201.13:59:47.37#ibcon#about to read 4, iclass 25, count 2 2006.201.13:59:47.37#ibcon#read 4, iclass 25, count 2 2006.201.13:59:47.37#ibcon#about to read 5, iclass 25, count 2 2006.201.13:59:47.37#ibcon#read 5, iclass 25, count 2 2006.201.13:59:47.37#ibcon#about to read 6, iclass 25, count 2 2006.201.13:59:47.37#ibcon#read 6, iclass 25, count 2 2006.201.13:59:47.37#ibcon#end of sib2, iclass 25, count 2 2006.201.13:59:47.37#ibcon#*after write, iclass 25, count 2 2006.201.13:59:47.37#ibcon#*before return 0, iclass 25, count 2 2006.201.13:59:47.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:47.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:47.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.13:59:47.37#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:47.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:47.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:47.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:47.49#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:59:47.49#ibcon#first serial, iclass 25, count 0 2006.201.13:59:47.49#ibcon#enter sib2, iclass 25, count 0 2006.201.13:59:47.49#ibcon#flushed, iclass 25, count 0 2006.201.13:59:47.49#ibcon#about to write, iclass 25, count 0 2006.201.13:59:47.49#ibcon#wrote, iclass 25, count 0 2006.201.13:59:47.49#ibcon#about to read 3, iclass 25, count 0 2006.201.13:59:47.51#ibcon#read 3, iclass 25, count 0 2006.201.13:59:47.51#ibcon#about to read 4, iclass 25, count 0 2006.201.13:59:47.51#ibcon#read 4, iclass 25, count 0 2006.201.13:59:47.51#ibcon#about to read 5, iclass 25, count 0 2006.201.13:59:47.51#ibcon#read 5, iclass 25, count 0 2006.201.13:59:47.51#ibcon#about to read 6, iclass 25, count 0 2006.201.13:59:47.51#ibcon#read 6, iclass 25, count 0 2006.201.13:59:47.51#ibcon#end of sib2, iclass 25, count 0 2006.201.13:59:47.51#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:59:47.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:59:47.51#ibcon#[25=USB\r\n] 2006.201.13:59:47.51#ibcon#*before write, iclass 25, count 0 2006.201.13:59:47.51#ibcon#enter sib2, iclass 25, count 0 2006.201.13:59:47.51#ibcon#flushed, iclass 25, count 0 2006.201.13:59:47.51#ibcon#about to write, iclass 25, count 0 2006.201.13:59:47.51#ibcon#wrote, iclass 25, count 0 2006.201.13:59:47.51#ibcon#about to read 3, iclass 25, count 0 2006.201.13:59:47.54#ibcon#read 3, iclass 25, count 0 2006.201.13:59:47.54#ibcon#about to read 4, iclass 25, count 0 2006.201.13:59:47.54#ibcon#read 4, iclass 25, count 0 2006.201.13:59:47.54#ibcon#about to read 5, iclass 25, count 0 2006.201.13:59:47.54#ibcon#read 5, iclass 25, count 0 2006.201.13:59:47.54#ibcon#about to read 6, iclass 25, count 0 2006.201.13:59:47.54#ibcon#read 6, iclass 25, count 0 2006.201.13:59:47.54#ibcon#end of sib2, iclass 25, count 0 2006.201.13:59:47.54#ibcon#*after write, iclass 25, count 0 2006.201.13:59:47.54#ibcon#*before return 0, iclass 25, count 0 2006.201.13:59:47.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:47.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:47.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:59:47.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:59:47.54$vck44/valo=6,814.99 2006.201.13:59:47.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.13:59:47.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.13:59:47.54#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:47.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:47.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:47.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:47.54#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:59:47.54#ibcon#first serial, iclass 27, count 0 2006.201.13:59:47.54#ibcon#enter sib2, iclass 27, count 0 2006.201.13:59:47.54#ibcon#flushed, iclass 27, count 0 2006.201.13:59:47.54#ibcon#about to write, iclass 27, count 0 2006.201.13:59:47.54#ibcon#wrote, iclass 27, count 0 2006.201.13:59:47.54#ibcon#about to read 3, iclass 27, count 0 2006.201.13:59:47.56#ibcon#read 3, iclass 27, count 0 2006.201.13:59:47.56#ibcon#about to read 4, iclass 27, count 0 2006.201.13:59:47.56#ibcon#read 4, iclass 27, count 0 2006.201.13:59:47.56#ibcon#about to read 5, iclass 27, count 0 2006.201.13:59:47.56#ibcon#read 5, iclass 27, count 0 2006.201.13:59:47.56#ibcon#about to read 6, iclass 27, count 0 2006.201.13:59:47.56#ibcon#read 6, iclass 27, count 0 2006.201.13:59:47.56#ibcon#end of sib2, iclass 27, count 0 2006.201.13:59:47.56#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:59:47.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:59:47.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.13:59:47.56#ibcon#*before write, iclass 27, count 0 2006.201.13:59:47.56#ibcon#enter sib2, iclass 27, count 0 2006.201.13:59:47.56#ibcon#flushed, iclass 27, count 0 2006.201.13:59:47.56#ibcon#about to write, iclass 27, count 0 2006.201.13:59:47.56#ibcon#wrote, iclass 27, count 0 2006.201.13:59:47.56#ibcon#about to read 3, iclass 27, count 0 2006.201.13:59:47.61#ibcon#read 3, iclass 27, count 0 2006.201.13:59:47.61#ibcon#about to read 4, iclass 27, count 0 2006.201.13:59:47.61#ibcon#read 4, iclass 27, count 0 2006.201.13:59:47.61#ibcon#about to read 5, iclass 27, count 0 2006.201.13:59:47.61#ibcon#read 5, iclass 27, count 0 2006.201.13:59:47.61#ibcon#about to read 6, iclass 27, count 0 2006.201.13:59:47.61#ibcon#read 6, iclass 27, count 0 2006.201.13:59:47.61#ibcon#end of sib2, iclass 27, count 0 2006.201.13:59:47.61#ibcon#*after write, iclass 27, count 0 2006.201.13:59:47.61#ibcon#*before return 0, iclass 27, count 0 2006.201.13:59:47.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:47.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:47.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:59:47.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:59:47.61$vck44/va=6,5 2006.201.13:59:47.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.13:59:47.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.13:59:47.61#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:47.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:47.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:47.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:47.66#ibcon#enter wrdev, iclass 29, count 2 2006.201.13:59:47.66#ibcon#first serial, iclass 29, count 2 2006.201.13:59:47.66#ibcon#enter sib2, iclass 29, count 2 2006.201.13:59:47.66#ibcon#flushed, iclass 29, count 2 2006.201.13:59:47.66#ibcon#about to write, iclass 29, count 2 2006.201.13:59:47.66#ibcon#wrote, iclass 29, count 2 2006.201.13:59:47.66#ibcon#about to read 3, iclass 29, count 2 2006.201.13:59:47.68#ibcon#read 3, iclass 29, count 2 2006.201.13:59:47.68#ibcon#about to read 4, iclass 29, count 2 2006.201.13:59:47.68#ibcon#read 4, iclass 29, count 2 2006.201.13:59:47.68#ibcon#about to read 5, iclass 29, count 2 2006.201.13:59:47.68#ibcon#read 5, iclass 29, count 2 2006.201.13:59:47.68#ibcon#about to read 6, iclass 29, count 2 2006.201.13:59:47.68#ibcon#read 6, iclass 29, count 2 2006.201.13:59:47.68#ibcon#end of sib2, iclass 29, count 2 2006.201.13:59:47.68#ibcon#*mode == 0, iclass 29, count 2 2006.201.13:59:47.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.13:59:47.68#ibcon#[25=AT06-05\r\n] 2006.201.13:59:47.68#ibcon#*before write, iclass 29, count 2 2006.201.13:59:47.68#ibcon#enter sib2, iclass 29, count 2 2006.201.13:59:47.68#ibcon#flushed, iclass 29, count 2 2006.201.13:59:47.68#ibcon#about to write, iclass 29, count 2 2006.201.13:59:47.68#ibcon#wrote, iclass 29, count 2 2006.201.13:59:47.68#ibcon#about to read 3, iclass 29, count 2 2006.201.13:59:47.71#ibcon#read 3, iclass 29, count 2 2006.201.13:59:47.71#ibcon#about to read 4, iclass 29, count 2 2006.201.13:59:47.71#ibcon#read 4, iclass 29, count 2 2006.201.13:59:47.71#ibcon#about to read 5, iclass 29, count 2 2006.201.13:59:47.71#ibcon#read 5, iclass 29, count 2 2006.201.13:59:47.71#ibcon#about to read 6, iclass 29, count 2 2006.201.13:59:47.71#ibcon#read 6, iclass 29, count 2 2006.201.13:59:47.71#ibcon#end of sib2, iclass 29, count 2 2006.201.13:59:47.71#ibcon#*after write, iclass 29, count 2 2006.201.13:59:47.71#ibcon#*before return 0, iclass 29, count 2 2006.201.13:59:47.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:47.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:47.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.13:59:47.71#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:47.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:47.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:47.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:47.83#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:59:47.83#ibcon#first serial, iclass 29, count 0 2006.201.13:59:47.83#ibcon#enter sib2, iclass 29, count 0 2006.201.13:59:47.83#ibcon#flushed, iclass 29, count 0 2006.201.13:59:47.83#ibcon#about to write, iclass 29, count 0 2006.201.13:59:47.83#ibcon#wrote, iclass 29, count 0 2006.201.13:59:47.83#ibcon#about to read 3, iclass 29, count 0 2006.201.13:59:47.85#ibcon#read 3, iclass 29, count 0 2006.201.13:59:47.85#ibcon#about to read 4, iclass 29, count 0 2006.201.13:59:47.85#ibcon#read 4, iclass 29, count 0 2006.201.13:59:47.85#ibcon#about to read 5, iclass 29, count 0 2006.201.13:59:47.85#ibcon#read 5, iclass 29, count 0 2006.201.13:59:47.85#ibcon#about to read 6, iclass 29, count 0 2006.201.13:59:47.85#ibcon#read 6, iclass 29, count 0 2006.201.13:59:47.85#ibcon#end of sib2, iclass 29, count 0 2006.201.13:59:47.85#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:59:47.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:59:47.85#ibcon#[25=USB\r\n] 2006.201.13:59:47.85#ibcon#*before write, iclass 29, count 0 2006.201.13:59:47.85#ibcon#enter sib2, iclass 29, count 0 2006.201.13:59:47.85#ibcon#flushed, iclass 29, count 0 2006.201.13:59:47.85#ibcon#about to write, iclass 29, count 0 2006.201.13:59:47.85#ibcon#wrote, iclass 29, count 0 2006.201.13:59:47.85#ibcon#about to read 3, iclass 29, count 0 2006.201.13:59:47.88#ibcon#read 3, iclass 29, count 0 2006.201.13:59:47.88#ibcon#about to read 4, iclass 29, count 0 2006.201.13:59:47.88#ibcon#read 4, iclass 29, count 0 2006.201.13:59:47.88#ibcon#about to read 5, iclass 29, count 0 2006.201.13:59:47.88#ibcon#read 5, iclass 29, count 0 2006.201.13:59:47.88#ibcon#about to read 6, iclass 29, count 0 2006.201.13:59:47.88#ibcon#read 6, iclass 29, count 0 2006.201.13:59:47.88#ibcon#end of sib2, iclass 29, count 0 2006.201.13:59:47.88#ibcon#*after write, iclass 29, count 0 2006.201.13:59:47.88#ibcon#*before return 0, iclass 29, count 0 2006.201.13:59:47.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:47.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:47.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:59:47.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:59:47.88$vck44/valo=7,864.99 2006.201.13:59:47.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.13:59:47.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.13:59:47.88#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:47.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:47.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:47.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:47.88#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:59:47.88#ibcon#first serial, iclass 31, count 0 2006.201.13:59:47.88#ibcon#enter sib2, iclass 31, count 0 2006.201.13:59:47.88#ibcon#flushed, iclass 31, count 0 2006.201.13:59:47.88#ibcon#about to write, iclass 31, count 0 2006.201.13:59:47.88#ibcon#wrote, iclass 31, count 0 2006.201.13:59:47.88#ibcon#about to read 3, iclass 31, count 0 2006.201.13:59:47.90#ibcon#read 3, iclass 31, count 0 2006.201.13:59:47.90#ibcon#about to read 4, iclass 31, count 0 2006.201.13:59:47.90#ibcon#read 4, iclass 31, count 0 2006.201.13:59:47.90#ibcon#about to read 5, iclass 31, count 0 2006.201.13:59:47.90#ibcon#read 5, iclass 31, count 0 2006.201.13:59:47.90#ibcon#about to read 6, iclass 31, count 0 2006.201.13:59:47.90#ibcon#read 6, iclass 31, count 0 2006.201.13:59:47.90#ibcon#end of sib2, iclass 31, count 0 2006.201.13:59:47.90#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:59:47.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:59:47.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.13:59:47.90#ibcon#*before write, iclass 31, count 0 2006.201.13:59:47.90#ibcon#enter sib2, iclass 31, count 0 2006.201.13:59:47.90#ibcon#flushed, iclass 31, count 0 2006.201.13:59:47.90#ibcon#about to write, iclass 31, count 0 2006.201.13:59:47.90#ibcon#wrote, iclass 31, count 0 2006.201.13:59:47.90#ibcon#about to read 3, iclass 31, count 0 2006.201.13:59:47.94#ibcon#read 3, iclass 31, count 0 2006.201.13:59:47.94#ibcon#about to read 4, iclass 31, count 0 2006.201.13:59:47.94#ibcon#read 4, iclass 31, count 0 2006.201.13:59:47.94#ibcon#about to read 5, iclass 31, count 0 2006.201.13:59:47.94#ibcon#read 5, iclass 31, count 0 2006.201.13:59:47.94#ibcon#about to read 6, iclass 31, count 0 2006.201.13:59:47.94#ibcon#read 6, iclass 31, count 0 2006.201.13:59:47.94#ibcon#end of sib2, iclass 31, count 0 2006.201.13:59:47.94#ibcon#*after write, iclass 31, count 0 2006.201.13:59:47.94#ibcon#*before return 0, iclass 31, count 0 2006.201.13:59:47.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:47.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:47.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:59:47.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:59:47.94$vck44/va=7,5 2006.201.13:59:47.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.13:59:47.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.13:59:47.94#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:47.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:48.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:48.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:48.00#ibcon#enter wrdev, iclass 33, count 2 2006.201.13:59:48.00#ibcon#first serial, iclass 33, count 2 2006.201.13:59:48.00#ibcon#enter sib2, iclass 33, count 2 2006.201.13:59:48.00#ibcon#flushed, iclass 33, count 2 2006.201.13:59:48.00#ibcon#about to write, iclass 33, count 2 2006.201.13:59:48.00#ibcon#wrote, iclass 33, count 2 2006.201.13:59:48.00#ibcon#about to read 3, iclass 33, count 2 2006.201.13:59:48.02#ibcon#read 3, iclass 33, count 2 2006.201.13:59:48.02#ibcon#about to read 4, iclass 33, count 2 2006.201.13:59:48.02#ibcon#read 4, iclass 33, count 2 2006.201.13:59:48.02#ibcon#about to read 5, iclass 33, count 2 2006.201.13:59:48.02#ibcon#read 5, iclass 33, count 2 2006.201.13:59:48.02#ibcon#about to read 6, iclass 33, count 2 2006.201.13:59:48.02#ibcon#read 6, iclass 33, count 2 2006.201.13:59:48.02#ibcon#end of sib2, iclass 33, count 2 2006.201.13:59:48.02#ibcon#*mode == 0, iclass 33, count 2 2006.201.13:59:48.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.13:59:48.02#ibcon#[25=AT07-05\r\n] 2006.201.13:59:48.02#ibcon#*before write, iclass 33, count 2 2006.201.13:59:48.02#ibcon#enter sib2, iclass 33, count 2 2006.201.13:59:48.02#ibcon#flushed, iclass 33, count 2 2006.201.13:59:48.02#ibcon#about to write, iclass 33, count 2 2006.201.13:59:48.02#ibcon#wrote, iclass 33, count 2 2006.201.13:59:48.02#ibcon#about to read 3, iclass 33, count 2 2006.201.13:59:48.05#ibcon#read 3, iclass 33, count 2 2006.201.13:59:48.05#ibcon#about to read 4, iclass 33, count 2 2006.201.13:59:48.05#ibcon#read 4, iclass 33, count 2 2006.201.13:59:48.05#ibcon#about to read 5, iclass 33, count 2 2006.201.13:59:48.05#ibcon#read 5, iclass 33, count 2 2006.201.13:59:48.05#ibcon#about to read 6, iclass 33, count 2 2006.201.13:59:48.05#ibcon#read 6, iclass 33, count 2 2006.201.13:59:48.05#ibcon#end of sib2, iclass 33, count 2 2006.201.13:59:48.05#ibcon#*after write, iclass 33, count 2 2006.201.13:59:48.05#ibcon#*before return 0, iclass 33, count 2 2006.201.13:59:48.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:48.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:48.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.13:59:48.05#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:48.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:48.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:48.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:48.17#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:59:48.17#ibcon#first serial, iclass 33, count 0 2006.201.13:59:48.17#ibcon#enter sib2, iclass 33, count 0 2006.201.13:59:48.17#ibcon#flushed, iclass 33, count 0 2006.201.13:59:48.17#ibcon#about to write, iclass 33, count 0 2006.201.13:59:48.17#ibcon#wrote, iclass 33, count 0 2006.201.13:59:48.17#ibcon#about to read 3, iclass 33, count 0 2006.201.13:59:48.19#ibcon#read 3, iclass 33, count 0 2006.201.13:59:48.19#ibcon#about to read 4, iclass 33, count 0 2006.201.13:59:48.19#ibcon#read 4, iclass 33, count 0 2006.201.13:59:48.19#ibcon#about to read 5, iclass 33, count 0 2006.201.13:59:48.19#ibcon#read 5, iclass 33, count 0 2006.201.13:59:48.19#ibcon#about to read 6, iclass 33, count 0 2006.201.13:59:48.19#ibcon#read 6, iclass 33, count 0 2006.201.13:59:48.19#ibcon#end of sib2, iclass 33, count 0 2006.201.13:59:48.19#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:59:48.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:59:48.19#ibcon#[25=USB\r\n] 2006.201.13:59:48.19#ibcon#*before write, iclass 33, count 0 2006.201.13:59:48.19#ibcon#enter sib2, iclass 33, count 0 2006.201.13:59:48.19#ibcon#flushed, iclass 33, count 0 2006.201.13:59:48.19#ibcon#about to write, iclass 33, count 0 2006.201.13:59:48.19#ibcon#wrote, iclass 33, count 0 2006.201.13:59:48.19#ibcon#about to read 3, iclass 33, count 0 2006.201.13:59:48.22#ibcon#read 3, iclass 33, count 0 2006.201.13:59:48.22#ibcon#about to read 4, iclass 33, count 0 2006.201.13:59:48.22#ibcon#read 4, iclass 33, count 0 2006.201.13:59:48.22#ibcon#about to read 5, iclass 33, count 0 2006.201.13:59:48.22#ibcon#read 5, iclass 33, count 0 2006.201.13:59:48.22#ibcon#about to read 6, iclass 33, count 0 2006.201.13:59:48.22#ibcon#read 6, iclass 33, count 0 2006.201.13:59:48.22#ibcon#end of sib2, iclass 33, count 0 2006.201.13:59:48.22#ibcon#*after write, iclass 33, count 0 2006.201.13:59:48.22#ibcon#*before return 0, iclass 33, count 0 2006.201.13:59:48.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:48.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:48.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:59:48.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:59:48.22$vck44/valo=8,884.99 2006.201.13:59:48.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.13:59:48.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.13:59:48.22#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:48.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:48.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:48.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:48.22#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:59:48.22#ibcon#first serial, iclass 35, count 0 2006.201.13:59:48.22#ibcon#enter sib2, iclass 35, count 0 2006.201.13:59:48.22#ibcon#flushed, iclass 35, count 0 2006.201.13:59:48.22#ibcon#about to write, iclass 35, count 0 2006.201.13:59:48.22#ibcon#wrote, iclass 35, count 0 2006.201.13:59:48.22#ibcon#about to read 3, iclass 35, count 0 2006.201.13:59:48.24#ibcon#read 3, iclass 35, count 0 2006.201.13:59:48.24#ibcon#about to read 4, iclass 35, count 0 2006.201.13:59:48.24#ibcon#read 4, iclass 35, count 0 2006.201.13:59:48.24#ibcon#about to read 5, iclass 35, count 0 2006.201.13:59:48.24#ibcon#read 5, iclass 35, count 0 2006.201.13:59:48.24#ibcon#about to read 6, iclass 35, count 0 2006.201.13:59:48.24#ibcon#read 6, iclass 35, count 0 2006.201.13:59:48.24#ibcon#end of sib2, iclass 35, count 0 2006.201.13:59:48.24#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:59:48.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:59:48.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.13:59:48.24#ibcon#*before write, iclass 35, count 0 2006.201.13:59:48.24#ibcon#enter sib2, iclass 35, count 0 2006.201.13:59:48.24#ibcon#flushed, iclass 35, count 0 2006.201.13:59:48.24#ibcon#about to write, iclass 35, count 0 2006.201.13:59:48.24#ibcon#wrote, iclass 35, count 0 2006.201.13:59:48.24#ibcon#about to read 3, iclass 35, count 0 2006.201.13:59:48.28#ibcon#read 3, iclass 35, count 0 2006.201.13:59:48.28#ibcon#about to read 4, iclass 35, count 0 2006.201.13:59:48.28#ibcon#read 4, iclass 35, count 0 2006.201.13:59:48.28#ibcon#about to read 5, iclass 35, count 0 2006.201.13:59:48.28#ibcon#read 5, iclass 35, count 0 2006.201.13:59:48.28#ibcon#about to read 6, iclass 35, count 0 2006.201.13:59:48.28#ibcon#read 6, iclass 35, count 0 2006.201.13:59:48.28#ibcon#end of sib2, iclass 35, count 0 2006.201.13:59:48.28#ibcon#*after write, iclass 35, count 0 2006.201.13:59:48.28#ibcon#*before return 0, iclass 35, count 0 2006.201.13:59:48.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:48.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:48.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:59:48.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:59:48.28$vck44/va=8,4 2006.201.13:59:48.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.13:59:48.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.13:59:48.28#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:48.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:59:48.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:59:48.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:59:48.34#ibcon#enter wrdev, iclass 37, count 2 2006.201.13:59:48.34#ibcon#first serial, iclass 37, count 2 2006.201.13:59:48.34#ibcon#enter sib2, iclass 37, count 2 2006.201.13:59:48.34#ibcon#flushed, iclass 37, count 2 2006.201.13:59:48.34#ibcon#about to write, iclass 37, count 2 2006.201.13:59:48.34#ibcon#wrote, iclass 37, count 2 2006.201.13:59:48.34#ibcon#about to read 3, iclass 37, count 2 2006.201.13:59:48.36#ibcon#read 3, iclass 37, count 2 2006.201.13:59:48.36#ibcon#about to read 4, iclass 37, count 2 2006.201.13:59:48.36#ibcon#read 4, iclass 37, count 2 2006.201.13:59:48.36#ibcon#about to read 5, iclass 37, count 2 2006.201.13:59:48.36#ibcon#read 5, iclass 37, count 2 2006.201.13:59:48.36#ibcon#about to read 6, iclass 37, count 2 2006.201.13:59:48.36#ibcon#read 6, iclass 37, count 2 2006.201.13:59:48.36#ibcon#end of sib2, iclass 37, count 2 2006.201.13:59:48.36#ibcon#*mode == 0, iclass 37, count 2 2006.201.13:59:48.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.13:59:48.36#ibcon#[25=AT08-04\r\n] 2006.201.13:59:48.36#ibcon#*before write, iclass 37, count 2 2006.201.13:59:48.36#ibcon#enter sib2, iclass 37, count 2 2006.201.13:59:48.36#ibcon#flushed, iclass 37, count 2 2006.201.13:59:48.36#ibcon#about to write, iclass 37, count 2 2006.201.13:59:48.36#ibcon#wrote, iclass 37, count 2 2006.201.13:59:48.36#ibcon#about to read 3, iclass 37, count 2 2006.201.13:59:48.39#ibcon#read 3, iclass 37, count 2 2006.201.13:59:48.39#ibcon#about to read 4, iclass 37, count 2 2006.201.13:59:48.39#ibcon#read 4, iclass 37, count 2 2006.201.13:59:48.39#ibcon#about to read 5, iclass 37, count 2 2006.201.13:59:48.39#ibcon#read 5, iclass 37, count 2 2006.201.13:59:48.39#ibcon#about to read 6, iclass 37, count 2 2006.201.13:59:48.39#ibcon#read 6, iclass 37, count 2 2006.201.13:59:48.39#ibcon#end of sib2, iclass 37, count 2 2006.201.13:59:48.39#ibcon#*after write, iclass 37, count 2 2006.201.13:59:48.39#ibcon#*before return 0, iclass 37, count 2 2006.201.13:59:48.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:59:48.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.13:59:48.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.13:59:48.39#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:48.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:59:48.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:59:48.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:59:48.51#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:59:48.51#ibcon#first serial, iclass 37, count 0 2006.201.13:59:48.51#ibcon#enter sib2, iclass 37, count 0 2006.201.13:59:48.51#ibcon#flushed, iclass 37, count 0 2006.201.13:59:48.51#ibcon#about to write, iclass 37, count 0 2006.201.13:59:48.51#ibcon#wrote, iclass 37, count 0 2006.201.13:59:48.51#ibcon#about to read 3, iclass 37, count 0 2006.201.13:59:48.53#ibcon#read 3, iclass 37, count 0 2006.201.13:59:48.53#ibcon#about to read 4, iclass 37, count 0 2006.201.13:59:48.53#ibcon#read 4, iclass 37, count 0 2006.201.13:59:48.53#ibcon#about to read 5, iclass 37, count 0 2006.201.13:59:48.53#ibcon#read 5, iclass 37, count 0 2006.201.13:59:48.53#ibcon#about to read 6, iclass 37, count 0 2006.201.13:59:48.53#ibcon#read 6, iclass 37, count 0 2006.201.13:59:48.53#ibcon#end of sib2, iclass 37, count 0 2006.201.13:59:48.53#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:59:48.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:59:48.53#ibcon#[25=USB\r\n] 2006.201.13:59:48.53#ibcon#*before write, iclass 37, count 0 2006.201.13:59:48.53#ibcon#enter sib2, iclass 37, count 0 2006.201.13:59:48.53#ibcon#flushed, iclass 37, count 0 2006.201.13:59:48.53#ibcon#about to write, iclass 37, count 0 2006.201.13:59:48.53#ibcon#wrote, iclass 37, count 0 2006.201.13:59:48.53#ibcon#about to read 3, iclass 37, count 0 2006.201.13:59:48.56#ibcon#read 3, iclass 37, count 0 2006.201.13:59:48.56#ibcon#about to read 4, iclass 37, count 0 2006.201.13:59:48.56#ibcon#read 4, iclass 37, count 0 2006.201.13:59:48.56#ibcon#about to read 5, iclass 37, count 0 2006.201.13:59:48.56#ibcon#read 5, iclass 37, count 0 2006.201.13:59:48.56#ibcon#about to read 6, iclass 37, count 0 2006.201.13:59:48.56#ibcon#read 6, iclass 37, count 0 2006.201.13:59:48.56#ibcon#end of sib2, iclass 37, count 0 2006.201.13:59:48.56#ibcon#*after write, iclass 37, count 0 2006.201.13:59:48.56#ibcon#*before return 0, iclass 37, count 0 2006.201.13:59:48.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:59:48.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.13:59:48.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:59:48.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:59:48.56$vck44/vblo=1,629.99 2006.201.13:59:48.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.13:59:48.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.13:59:48.56#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:48.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:59:48.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:59:48.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:59:48.56#ibcon#enter wrdev, iclass 39, count 0 2006.201.13:59:48.56#ibcon#first serial, iclass 39, count 0 2006.201.13:59:48.56#ibcon#enter sib2, iclass 39, count 0 2006.201.13:59:48.56#ibcon#flushed, iclass 39, count 0 2006.201.13:59:48.56#ibcon#about to write, iclass 39, count 0 2006.201.13:59:48.56#ibcon#wrote, iclass 39, count 0 2006.201.13:59:48.56#ibcon#about to read 3, iclass 39, count 0 2006.201.13:59:48.58#ibcon#read 3, iclass 39, count 0 2006.201.13:59:48.58#ibcon#about to read 4, iclass 39, count 0 2006.201.13:59:48.58#ibcon#read 4, iclass 39, count 0 2006.201.13:59:48.58#ibcon#about to read 5, iclass 39, count 0 2006.201.13:59:48.58#ibcon#read 5, iclass 39, count 0 2006.201.13:59:48.58#ibcon#about to read 6, iclass 39, count 0 2006.201.13:59:48.58#ibcon#read 6, iclass 39, count 0 2006.201.13:59:48.58#ibcon#end of sib2, iclass 39, count 0 2006.201.13:59:48.58#ibcon#*mode == 0, iclass 39, count 0 2006.201.13:59:48.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.13:59:48.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.13:59:48.58#ibcon#*before write, iclass 39, count 0 2006.201.13:59:48.58#ibcon#enter sib2, iclass 39, count 0 2006.201.13:59:48.58#ibcon#flushed, iclass 39, count 0 2006.201.13:59:48.58#ibcon#about to write, iclass 39, count 0 2006.201.13:59:48.58#ibcon#wrote, iclass 39, count 0 2006.201.13:59:48.58#ibcon#about to read 3, iclass 39, count 0 2006.201.13:59:48.63#ibcon#read 3, iclass 39, count 0 2006.201.13:59:48.63#ibcon#about to read 4, iclass 39, count 0 2006.201.13:59:48.63#ibcon#read 4, iclass 39, count 0 2006.201.13:59:48.63#ibcon#about to read 5, iclass 39, count 0 2006.201.13:59:48.63#ibcon#read 5, iclass 39, count 0 2006.201.13:59:48.63#ibcon#about to read 6, iclass 39, count 0 2006.201.13:59:48.63#ibcon#read 6, iclass 39, count 0 2006.201.13:59:48.63#ibcon#end of sib2, iclass 39, count 0 2006.201.13:59:48.63#ibcon#*after write, iclass 39, count 0 2006.201.13:59:48.63#ibcon#*before return 0, iclass 39, count 0 2006.201.13:59:48.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:59:48.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.13:59:48.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.13:59:48.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.13:59:48.63$vck44/vb=1,4 2006.201.13:59:48.63#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.13:59:48.63#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.13:59:48.63#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:48.63#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:59:48.63#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:59:48.63#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:59:48.63#ibcon#enter wrdev, iclass 2, count 2 2006.201.13:59:48.63#ibcon#first serial, iclass 2, count 2 2006.201.13:59:48.63#ibcon#enter sib2, iclass 2, count 2 2006.201.13:59:48.63#ibcon#flushed, iclass 2, count 2 2006.201.13:59:48.63#ibcon#about to write, iclass 2, count 2 2006.201.13:59:48.63#ibcon#wrote, iclass 2, count 2 2006.201.13:59:48.63#ibcon#about to read 3, iclass 2, count 2 2006.201.13:59:48.65#ibcon#read 3, iclass 2, count 2 2006.201.13:59:48.65#ibcon#about to read 4, iclass 2, count 2 2006.201.13:59:48.65#ibcon#read 4, iclass 2, count 2 2006.201.13:59:48.65#ibcon#about to read 5, iclass 2, count 2 2006.201.13:59:48.65#ibcon#read 5, iclass 2, count 2 2006.201.13:59:48.65#ibcon#about to read 6, iclass 2, count 2 2006.201.13:59:48.65#ibcon#read 6, iclass 2, count 2 2006.201.13:59:48.65#ibcon#end of sib2, iclass 2, count 2 2006.201.13:59:48.65#ibcon#*mode == 0, iclass 2, count 2 2006.201.13:59:48.65#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.13:59:48.65#ibcon#[27=AT01-04\r\n] 2006.201.13:59:48.65#ibcon#*before write, iclass 2, count 2 2006.201.13:59:48.65#ibcon#enter sib2, iclass 2, count 2 2006.201.13:59:48.65#ibcon#flushed, iclass 2, count 2 2006.201.13:59:48.65#ibcon#about to write, iclass 2, count 2 2006.201.13:59:48.65#ibcon#wrote, iclass 2, count 2 2006.201.13:59:48.65#ibcon#about to read 3, iclass 2, count 2 2006.201.13:59:48.68#ibcon#read 3, iclass 2, count 2 2006.201.13:59:48.68#ibcon#about to read 4, iclass 2, count 2 2006.201.13:59:48.68#ibcon#read 4, iclass 2, count 2 2006.201.13:59:48.68#ibcon#about to read 5, iclass 2, count 2 2006.201.13:59:48.68#ibcon#read 5, iclass 2, count 2 2006.201.13:59:48.68#ibcon#about to read 6, iclass 2, count 2 2006.201.13:59:48.68#ibcon#read 6, iclass 2, count 2 2006.201.13:59:48.68#ibcon#end of sib2, iclass 2, count 2 2006.201.13:59:48.68#ibcon#*after write, iclass 2, count 2 2006.201.13:59:48.68#ibcon#*before return 0, iclass 2, count 2 2006.201.13:59:48.68#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:59:48.68#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.13:59:48.68#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.13:59:48.68#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:48.68#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:59:48.80#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:59:48.80#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:59:48.80#ibcon#enter wrdev, iclass 2, count 0 2006.201.13:59:48.80#ibcon#first serial, iclass 2, count 0 2006.201.13:59:48.80#ibcon#enter sib2, iclass 2, count 0 2006.201.13:59:48.80#ibcon#flushed, iclass 2, count 0 2006.201.13:59:48.80#ibcon#about to write, iclass 2, count 0 2006.201.13:59:48.80#ibcon#wrote, iclass 2, count 0 2006.201.13:59:48.80#ibcon#about to read 3, iclass 2, count 0 2006.201.13:59:48.82#ibcon#read 3, iclass 2, count 0 2006.201.13:59:48.82#ibcon#about to read 4, iclass 2, count 0 2006.201.13:59:48.82#ibcon#read 4, iclass 2, count 0 2006.201.13:59:48.82#ibcon#about to read 5, iclass 2, count 0 2006.201.13:59:48.82#ibcon#read 5, iclass 2, count 0 2006.201.13:59:48.82#ibcon#about to read 6, iclass 2, count 0 2006.201.13:59:48.82#ibcon#read 6, iclass 2, count 0 2006.201.13:59:48.82#ibcon#end of sib2, iclass 2, count 0 2006.201.13:59:48.82#ibcon#*mode == 0, iclass 2, count 0 2006.201.13:59:48.82#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.13:59:48.82#ibcon#[27=USB\r\n] 2006.201.13:59:48.82#ibcon#*before write, iclass 2, count 0 2006.201.13:59:48.82#ibcon#enter sib2, iclass 2, count 0 2006.201.13:59:48.82#ibcon#flushed, iclass 2, count 0 2006.201.13:59:48.82#ibcon#about to write, iclass 2, count 0 2006.201.13:59:48.82#ibcon#wrote, iclass 2, count 0 2006.201.13:59:48.82#ibcon#about to read 3, iclass 2, count 0 2006.201.13:59:48.85#ibcon#read 3, iclass 2, count 0 2006.201.13:59:48.85#ibcon#about to read 4, iclass 2, count 0 2006.201.13:59:48.85#ibcon#read 4, iclass 2, count 0 2006.201.13:59:48.85#ibcon#about to read 5, iclass 2, count 0 2006.201.13:59:48.85#ibcon#read 5, iclass 2, count 0 2006.201.13:59:48.85#ibcon#about to read 6, iclass 2, count 0 2006.201.13:59:48.85#ibcon#read 6, iclass 2, count 0 2006.201.13:59:48.85#ibcon#end of sib2, iclass 2, count 0 2006.201.13:59:48.85#ibcon#*after write, iclass 2, count 0 2006.201.13:59:48.85#ibcon#*before return 0, iclass 2, count 0 2006.201.13:59:48.85#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:59:48.85#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.13:59:48.85#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.13:59:48.85#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.13:59:48.85$vck44/vblo=2,634.99 2006.201.13:59:48.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.13:59:48.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.13:59:48.85#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:48.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:48.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:48.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:48.85#ibcon#enter wrdev, iclass 5, count 0 2006.201.13:59:48.85#ibcon#first serial, iclass 5, count 0 2006.201.13:59:48.85#ibcon#enter sib2, iclass 5, count 0 2006.201.13:59:48.85#ibcon#flushed, iclass 5, count 0 2006.201.13:59:48.85#ibcon#about to write, iclass 5, count 0 2006.201.13:59:48.85#ibcon#wrote, iclass 5, count 0 2006.201.13:59:48.85#ibcon#about to read 3, iclass 5, count 0 2006.201.13:59:48.87#ibcon#read 3, iclass 5, count 0 2006.201.13:59:48.87#ibcon#about to read 4, iclass 5, count 0 2006.201.13:59:48.87#ibcon#read 4, iclass 5, count 0 2006.201.13:59:48.87#ibcon#about to read 5, iclass 5, count 0 2006.201.13:59:48.87#ibcon#read 5, iclass 5, count 0 2006.201.13:59:48.87#ibcon#about to read 6, iclass 5, count 0 2006.201.13:59:48.87#ibcon#read 6, iclass 5, count 0 2006.201.13:59:48.87#ibcon#end of sib2, iclass 5, count 0 2006.201.13:59:48.87#ibcon#*mode == 0, iclass 5, count 0 2006.201.13:59:48.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.13:59:48.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.13:59:48.87#ibcon#*before write, iclass 5, count 0 2006.201.13:59:48.87#ibcon#enter sib2, iclass 5, count 0 2006.201.13:59:48.87#ibcon#flushed, iclass 5, count 0 2006.201.13:59:48.87#ibcon#about to write, iclass 5, count 0 2006.201.13:59:48.87#ibcon#wrote, iclass 5, count 0 2006.201.13:59:48.87#ibcon#about to read 3, iclass 5, count 0 2006.201.13:59:48.91#ibcon#read 3, iclass 5, count 0 2006.201.13:59:48.91#ibcon#about to read 4, iclass 5, count 0 2006.201.13:59:48.91#ibcon#read 4, iclass 5, count 0 2006.201.13:59:48.91#ibcon#about to read 5, iclass 5, count 0 2006.201.13:59:48.91#ibcon#read 5, iclass 5, count 0 2006.201.13:59:48.91#ibcon#about to read 6, iclass 5, count 0 2006.201.13:59:48.91#ibcon#read 6, iclass 5, count 0 2006.201.13:59:48.91#ibcon#end of sib2, iclass 5, count 0 2006.201.13:59:48.91#ibcon#*after write, iclass 5, count 0 2006.201.13:59:48.91#ibcon#*before return 0, iclass 5, count 0 2006.201.13:59:48.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:48.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.13:59:48.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.13:59:48.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.13:59:48.91$vck44/vb=2,5 2006.201.13:59:48.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.13:59:48.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.13:59:48.91#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:48.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:48.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:48.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:48.97#ibcon#enter wrdev, iclass 7, count 2 2006.201.13:59:48.97#ibcon#first serial, iclass 7, count 2 2006.201.13:59:48.97#ibcon#enter sib2, iclass 7, count 2 2006.201.13:59:48.97#ibcon#flushed, iclass 7, count 2 2006.201.13:59:48.97#ibcon#about to write, iclass 7, count 2 2006.201.13:59:48.97#ibcon#wrote, iclass 7, count 2 2006.201.13:59:48.97#ibcon#about to read 3, iclass 7, count 2 2006.201.13:59:48.99#ibcon#read 3, iclass 7, count 2 2006.201.13:59:48.99#ibcon#about to read 4, iclass 7, count 2 2006.201.13:59:48.99#ibcon#read 4, iclass 7, count 2 2006.201.13:59:48.99#ibcon#about to read 5, iclass 7, count 2 2006.201.13:59:48.99#ibcon#read 5, iclass 7, count 2 2006.201.13:59:48.99#ibcon#about to read 6, iclass 7, count 2 2006.201.13:59:48.99#ibcon#read 6, iclass 7, count 2 2006.201.13:59:48.99#ibcon#end of sib2, iclass 7, count 2 2006.201.13:59:48.99#ibcon#*mode == 0, iclass 7, count 2 2006.201.13:59:48.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.13:59:48.99#ibcon#[27=AT02-05\r\n] 2006.201.13:59:48.99#ibcon#*before write, iclass 7, count 2 2006.201.13:59:48.99#ibcon#enter sib2, iclass 7, count 2 2006.201.13:59:48.99#ibcon#flushed, iclass 7, count 2 2006.201.13:59:48.99#ibcon#about to write, iclass 7, count 2 2006.201.13:59:48.99#ibcon#wrote, iclass 7, count 2 2006.201.13:59:48.99#ibcon#about to read 3, iclass 7, count 2 2006.201.13:59:49.02#ibcon#read 3, iclass 7, count 2 2006.201.13:59:49.02#ibcon#about to read 4, iclass 7, count 2 2006.201.13:59:49.02#ibcon#read 4, iclass 7, count 2 2006.201.13:59:49.02#ibcon#about to read 5, iclass 7, count 2 2006.201.13:59:49.02#ibcon#read 5, iclass 7, count 2 2006.201.13:59:49.02#ibcon#about to read 6, iclass 7, count 2 2006.201.13:59:49.02#ibcon#read 6, iclass 7, count 2 2006.201.13:59:49.02#ibcon#end of sib2, iclass 7, count 2 2006.201.13:59:49.02#ibcon#*after write, iclass 7, count 2 2006.201.13:59:49.02#ibcon#*before return 0, iclass 7, count 2 2006.201.13:59:49.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:49.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.13:59:49.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.13:59:49.02#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:49.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:49.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:49.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:49.14#ibcon#enter wrdev, iclass 7, count 0 2006.201.13:59:49.14#ibcon#first serial, iclass 7, count 0 2006.201.13:59:49.14#ibcon#enter sib2, iclass 7, count 0 2006.201.13:59:49.14#ibcon#flushed, iclass 7, count 0 2006.201.13:59:49.14#ibcon#about to write, iclass 7, count 0 2006.201.13:59:49.14#ibcon#wrote, iclass 7, count 0 2006.201.13:59:49.14#ibcon#about to read 3, iclass 7, count 0 2006.201.13:59:49.16#ibcon#read 3, iclass 7, count 0 2006.201.13:59:49.16#ibcon#about to read 4, iclass 7, count 0 2006.201.13:59:49.16#ibcon#read 4, iclass 7, count 0 2006.201.13:59:49.16#ibcon#about to read 5, iclass 7, count 0 2006.201.13:59:49.16#ibcon#read 5, iclass 7, count 0 2006.201.13:59:49.16#ibcon#about to read 6, iclass 7, count 0 2006.201.13:59:49.16#ibcon#read 6, iclass 7, count 0 2006.201.13:59:49.16#ibcon#end of sib2, iclass 7, count 0 2006.201.13:59:49.16#ibcon#*mode == 0, iclass 7, count 0 2006.201.13:59:49.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.13:59:49.16#ibcon#[27=USB\r\n] 2006.201.13:59:49.16#ibcon#*before write, iclass 7, count 0 2006.201.13:59:49.16#ibcon#enter sib2, iclass 7, count 0 2006.201.13:59:49.16#ibcon#flushed, iclass 7, count 0 2006.201.13:59:49.16#ibcon#about to write, iclass 7, count 0 2006.201.13:59:49.16#ibcon#wrote, iclass 7, count 0 2006.201.13:59:49.16#ibcon#about to read 3, iclass 7, count 0 2006.201.13:59:49.19#ibcon#read 3, iclass 7, count 0 2006.201.13:59:49.19#ibcon#about to read 4, iclass 7, count 0 2006.201.13:59:49.19#ibcon#read 4, iclass 7, count 0 2006.201.13:59:49.19#ibcon#about to read 5, iclass 7, count 0 2006.201.13:59:49.19#ibcon#read 5, iclass 7, count 0 2006.201.13:59:49.19#ibcon#about to read 6, iclass 7, count 0 2006.201.13:59:49.19#ibcon#read 6, iclass 7, count 0 2006.201.13:59:49.19#ibcon#end of sib2, iclass 7, count 0 2006.201.13:59:49.19#ibcon#*after write, iclass 7, count 0 2006.201.13:59:49.19#ibcon#*before return 0, iclass 7, count 0 2006.201.13:59:49.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:49.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.13:59:49.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.13:59:49.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.13:59:49.19$vck44/vblo=3,649.99 2006.201.13:59:49.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.13:59:49.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.13:59:49.19#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:49.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:49.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:49.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:49.19#ibcon#enter wrdev, iclass 11, count 0 2006.201.13:59:49.19#ibcon#first serial, iclass 11, count 0 2006.201.13:59:49.19#ibcon#enter sib2, iclass 11, count 0 2006.201.13:59:49.19#ibcon#flushed, iclass 11, count 0 2006.201.13:59:49.19#ibcon#about to write, iclass 11, count 0 2006.201.13:59:49.19#ibcon#wrote, iclass 11, count 0 2006.201.13:59:49.19#ibcon#about to read 3, iclass 11, count 0 2006.201.13:59:49.21#ibcon#read 3, iclass 11, count 0 2006.201.13:59:49.21#ibcon#about to read 4, iclass 11, count 0 2006.201.13:59:49.21#ibcon#read 4, iclass 11, count 0 2006.201.13:59:49.21#ibcon#about to read 5, iclass 11, count 0 2006.201.13:59:49.21#ibcon#read 5, iclass 11, count 0 2006.201.13:59:49.21#ibcon#about to read 6, iclass 11, count 0 2006.201.13:59:49.21#ibcon#read 6, iclass 11, count 0 2006.201.13:59:49.21#ibcon#end of sib2, iclass 11, count 0 2006.201.13:59:49.21#ibcon#*mode == 0, iclass 11, count 0 2006.201.13:59:49.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.13:59:49.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.13:59:49.21#ibcon#*before write, iclass 11, count 0 2006.201.13:59:49.21#ibcon#enter sib2, iclass 11, count 0 2006.201.13:59:49.21#ibcon#flushed, iclass 11, count 0 2006.201.13:59:49.21#ibcon#about to write, iclass 11, count 0 2006.201.13:59:49.21#ibcon#wrote, iclass 11, count 0 2006.201.13:59:49.21#ibcon#about to read 3, iclass 11, count 0 2006.201.13:59:49.26#ibcon#read 3, iclass 11, count 0 2006.201.13:59:49.26#ibcon#about to read 4, iclass 11, count 0 2006.201.13:59:49.26#ibcon#read 4, iclass 11, count 0 2006.201.13:59:49.26#ibcon#about to read 5, iclass 11, count 0 2006.201.13:59:49.26#ibcon#read 5, iclass 11, count 0 2006.201.13:59:49.26#ibcon#about to read 6, iclass 11, count 0 2006.201.13:59:49.26#ibcon#read 6, iclass 11, count 0 2006.201.13:59:49.26#ibcon#end of sib2, iclass 11, count 0 2006.201.13:59:49.26#ibcon#*after write, iclass 11, count 0 2006.201.13:59:49.26#ibcon#*before return 0, iclass 11, count 0 2006.201.13:59:49.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:49.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.13:59:49.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.13:59:49.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.13:59:49.26$vck44/vb=3,4 2006.201.13:59:49.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.13:59:49.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.13:59:49.26#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:49.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:49.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:49.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:49.31#ibcon#enter wrdev, iclass 13, count 2 2006.201.13:59:49.31#ibcon#first serial, iclass 13, count 2 2006.201.13:59:49.31#ibcon#enter sib2, iclass 13, count 2 2006.201.13:59:49.31#ibcon#flushed, iclass 13, count 2 2006.201.13:59:49.31#ibcon#about to write, iclass 13, count 2 2006.201.13:59:49.31#ibcon#wrote, iclass 13, count 2 2006.201.13:59:49.31#ibcon#about to read 3, iclass 13, count 2 2006.201.13:59:49.33#ibcon#read 3, iclass 13, count 2 2006.201.13:59:49.33#ibcon#about to read 4, iclass 13, count 2 2006.201.13:59:49.33#ibcon#read 4, iclass 13, count 2 2006.201.13:59:49.33#ibcon#about to read 5, iclass 13, count 2 2006.201.13:59:49.33#ibcon#read 5, iclass 13, count 2 2006.201.13:59:49.33#ibcon#about to read 6, iclass 13, count 2 2006.201.13:59:49.33#ibcon#read 6, iclass 13, count 2 2006.201.13:59:49.33#ibcon#end of sib2, iclass 13, count 2 2006.201.13:59:49.33#ibcon#*mode == 0, iclass 13, count 2 2006.201.13:59:49.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.13:59:49.33#ibcon#[27=AT03-04\r\n] 2006.201.13:59:49.33#ibcon#*before write, iclass 13, count 2 2006.201.13:59:49.33#ibcon#enter sib2, iclass 13, count 2 2006.201.13:59:49.33#ibcon#flushed, iclass 13, count 2 2006.201.13:59:49.33#ibcon#about to write, iclass 13, count 2 2006.201.13:59:49.33#ibcon#wrote, iclass 13, count 2 2006.201.13:59:49.33#ibcon#about to read 3, iclass 13, count 2 2006.201.13:59:49.36#ibcon#read 3, iclass 13, count 2 2006.201.13:59:49.36#ibcon#about to read 4, iclass 13, count 2 2006.201.13:59:49.36#ibcon#read 4, iclass 13, count 2 2006.201.13:59:49.36#ibcon#about to read 5, iclass 13, count 2 2006.201.13:59:49.36#ibcon#read 5, iclass 13, count 2 2006.201.13:59:49.36#ibcon#about to read 6, iclass 13, count 2 2006.201.13:59:49.36#ibcon#read 6, iclass 13, count 2 2006.201.13:59:49.36#ibcon#end of sib2, iclass 13, count 2 2006.201.13:59:49.36#ibcon#*after write, iclass 13, count 2 2006.201.13:59:49.36#ibcon#*before return 0, iclass 13, count 2 2006.201.13:59:49.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:49.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.13:59:49.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.13:59:49.36#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:49.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:49.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:49.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:49.48#ibcon#enter wrdev, iclass 13, count 0 2006.201.13:59:49.48#ibcon#first serial, iclass 13, count 0 2006.201.13:59:49.48#ibcon#enter sib2, iclass 13, count 0 2006.201.13:59:49.48#ibcon#flushed, iclass 13, count 0 2006.201.13:59:49.48#ibcon#about to write, iclass 13, count 0 2006.201.13:59:49.48#ibcon#wrote, iclass 13, count 0 2006.201.13:59:49.48#ibcon#about to read 3, iclass 13, count 0 2006.201.13:59:49.50#ibcon#read 3, iclass 13, count 0 2006.201.13:59:49.50#ibcon#about to read 4, iclass 13, count 0 2006.201.13:59:49.50#ibcon#read 4, iclass 13, count 0 2006.201.13:59:49.50#ibcon#about to read 5, iclass 13, count 0 2006.201.13:59:49.50#ibcon#read 5, iclass 13, count 0 2006.201.13:59:49.50#ibcon#about to read 6, iclass 13, count 0 2006.201.13:59:49.50#ibcon#read 6, iclass 13, count 0 2006.201.13:59:49.50#ibcon#end of sib2, iclass 13, count 0 2006.201.13:59:49.50#ibcon#*mode == 0, iclass 13, count 0 2006.201.13:59:49.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.13:59:49.50#ibcon#[27=USB\r\n] 2006.201.13:59:49.50#ibcon#*before write, iclass 13, count 0 2006.201.13:59:49.50#ibcon#enter sib2, iclass 13, count 0 2006.201.13:59:49.50#ibcon#flushed, iclass 13, count 0 2006.201.13:59:49.50#ibcon#about to write, iclass 13, count 0 2006.201.13:59:49.50#ibcon#wrote, iclass 13, count 0 2006.201.13:59:49.50#ibcon#about to read 3, iclass 13, count 0 2006.201.13:59:49.53#ibcon#read 3, iclass 13, count 0 2006.201.13:59:49.53#ibcon#about to read 4, iclass 13, count 0 2006.201.13:59:49.53#ibcon#read 4, iclass 13, count 0 2006.201.13:59:49.53#ibcon#about to read 5, iclass 13, count 0 2006.201.13:59:49.53#ibcon#read 5, iclass 13, count 0 2006.201.13:59:49.53#ibcon#about to read 6, iclass 13, count 0 2006.201.13:59:49.53#ibcon#read 6, iclass 13, count 0 2006.201.13:59:49.53#ibcon#end of sib2, iclass 13, count 0 2006.201.13:59:49.53#ibcon#*after write, iclass 13, count 0 2006.201.13:59:49.53#ibcon#*before return 0, iclass 13, count 0 2006.201.13:59:49.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:49.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.13:59:49.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.13:59:49.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.13:59:49.53$vck44/vblo=4,679.99 2006.201.13:59:49.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.13:59:49.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.13:59:49.53#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:49.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:49.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:49.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:49.53#ibcon#enter wrdev, iclass 15, count 0 2006.201.13:59:49.53#ibcon#first serial, iclass 15, count 0 2006.201.13:59:49.53#ibcon#enter sib2, iclass 15, count 0 2006.201.13:59:49.53#ibcon#flushed, iclass 15, count 0 2006.201.13:59:49.53#ibcon#about to write, iclass 15, count 0 2006.201.13:59:49.53#ibcon#wrote, iclass 15, count 0 2006.201.13:59:49.53#ibcon#about to read 3, iclass 15, count 0 2006.201.13:59:49.55#ibcon#read 3, iclass 15, count 0 2006.201.13:59:49.55#ibcon#about to read 4, iclass 15, count 0 2006.201.13:59:49.55#ibcon#read 4, iclass 15, count 0 2006.201.13:59:49.55#ibcon#about to read 5, iclass 15, count 0 2006.201.13:59:49.55#ibcon#read 5, iclass 15, count 0 2006.201.13:59:49.55#ibcon#about to read 6, iclass 15, count 0 2006.201.13:59:49.55#ibcon#read 6, iclass 15, count 0 2006.201.13:59:49.55#ibcon#end of sib2, iclass 15, count 0 2006.201.13:59:49.55#ibcon#*mode == 0, iclass 15, count 0 2006.201.13:59:49.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.13:59:49.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.13:59:49.55#ibcon#*before write, iclass 15, count 0 2006.201.13:59:49.55#ibcon#enter sib2, iclass 15, count 0 2006.201.13:59:49.55#ibcon#flushed, iclass 15, count 0 2006.201.13:59:49.55#ibcon#about to write, iclass 15, count 0 2006.201.13:59:49.55#ibcon#wrote, iclass 15, count 0 2006.201.13:59:49.55#ibcon#about to read 3, iclass 15, count 0 2006.201.13:59:49.59#ibcon#read 3, iclass 15, count 0 2006.201.13:59:49.59#ibcon#about to read 4, iclass 15, count 0 2006.201.13:59:49.59#ibcon#read 4, iclass 15, count 0 2006.201.13:59:49.59#ibcon#about to read 5, iclass 15, count 0 2006.201.13:59:49.59#ibcon#read 5, iclass 15, count 0 2006.201.13:59:49.59#ibcon#about to read 6, iclass 15, count 0 2006.201.13:59:49.59#ibcon#read 6, iclass 15, count 0 2006.201.13:59:49.59#ibcon#end of sib2, iclass 15, count 0 2006.201.13:59:49.59#ibcon#*after write, iclass 15, count 0 2006.201.13:59:49.59#ibcon#*before return 0, iclass 15, count 0 2006.201.13:59:49.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:49.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.13:59:49.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.13:59:49.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.13:59:49.59$vck44/vb=4,5 2006.201.13:59:49.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.13:59:49.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.13:59:49.59#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:49.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:49.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:49.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:49.65#ibcon#enter wrdev, iclass 17, count 2 2006.201.13:59:49.65#ibcon#first serial, iclass 17, count 2 2006.201.13:59:49.65#ibcon#enter sib2, iclass 17, count 2 2006.201.13:59:49.65#ibcon#flushed, iclass 17, count 2 2006.201.13:59:49.65#ibcon#about to write, iclass 17, count 2 2006.201.13:59:49.65#ibcon#wrote, iclass 17, count 2 2006.201.13:59:49.65#ibcon#about to read 3, iclass 17, count 2 2006.201.13:59:49.67#ibcon#read 3, iclass 17, count 2 2006.201.13:59:49.67#ibcon#about to read 4, iclass 17, count 2 2006.201.13:59:49.67#ibcon#read 4, iclass 17, count 2 2006.201.13:59:49.67#ibcon#about to read 5, iclass 17, count 2 2006.201.13:59:49.67#ibcon#read 5, iclass 17, count 2 2006.201.13:59:49.67#ibcon#about to read 6, iclass 17, count 2 2006.201.13:59:49.67#ibcon#read 6, iclass 17, count 2 2006.201.13:59:49.67#ibcon#end of sib2, iclass 17, count 2 2006.201.13:59:49.67#ibcon#*mode == 0, iclass 17, count 2 2006.201.13:59:49.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.13:59:49.67#ibcon#[27=AT04-05\r\n] 2006.201.13:59:49.67#ibcon#*before write, iclass 17, count 2 2006.201.13:59:49.67#ibcon#enter sib2, iclass 17, count 2 2006.201.13:59:49.67#ibcon#flushed, iclass 17, count 2 2006.201.13:59:49.67#ibcon#about to write, iclass 17, count 2 2006.201.13:59:49.67#ibcon#wrote, iclass 17, count 2 2006.201.13:59:49.67#ibcon#about to read 3, iclass 17, count 2 2006.201.13:59:49.70#ibcon#read 3, iclass 17, count 2 2006.201.13:59:49.70#ibcon#about to read 4, iclass 17, count 2 2006.201.13:59:49.70#ibcon#read 4, iclass 17, count 2 2006.201.13:59:49.70#ibcon#about to read 5, iclass 17, count 2 2006.201.13:59:49.70#ibcon#read 5, iclass 17, count 2 2006.201.13:59:49.70#ibcon#about to read 6, iclass 17, count 2 2006.201.13:59:49.70#ibcon#read 6, iclass 17, count 2 2006.201.13:59:49.70#ibcon#end of sib2, iclass 17, count 2 2006.201.13:59:49.70#ibcon#*after write, iclass 17, count 2 2006.201.13:59:49.70#ibcon#*before return 0, iclass 17, count 2 2006.201.13:59:49.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:49.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.13:59:49.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.13:59:49.70#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:49.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:49.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:49.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:49.82#ibcon#enter wrdev, iclass 17, count 0 2006.201.13:59:49.82#ibcon#first serial, iclass 17, count 0 2006.201.13:59:49.82#ibcon#enter sib2, iclass 17, count 0 2006.201.13:59:49.82#ibcon#flushed, iclass 17, count 0 2006.201.13:59:49.82#ibcon#about to write, iclass 17, count 0 2006.201.13:59:49.82#ibcon#wrote, iclass 17, count 0 2006.201.13:59:49.82#ibcon#about to read 3, iclass 17, count 0 2006.201.13:59:49.84#ibcon#read 3, iclass 17, count 0 2006.201.13:59:49.84#ibcon#about to read 4, iclass 17, count 0 2006.201.13:59:49.84#ibcon#read 4, iclass 17, count 0 2006.201.13:59:49.84#ibcon#about to read 5, iclass 17, count 0 2006.201.13:59:49.84#ibcon#read 5, iclass 17, count 0 2006.201.13:59:49.84#ibcon#about to read 6, iclass 17, count 0 2006.201.13:59:49.84#ibcon#read 6, iclass 17, count 0 2006.201.13:59:49.84#ibcon#end of sib2, iclass 17, count 0 2006.201.13:59:49.84#ibcon#*mode == 0, iclass 17, count 0 2006.201.13:59:49.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.13:59:49.84#ibcon#[27=USB\r\n] 2006.201.13:59:49.84#ibcon#*before write, iclass 17, count 0 2006.201.13:59:49.84#ibcon#enter sib2, iclass 17, count 0 2006.201.13:59:49.84#ibcon#flushed, iclass 17, count 0 2006.201.13:59:49.84#ibcon#about to write, iclass 17, count 0 2006.201.13:59:49.84#ibcon#wrote, iclass 17, count 0 2006.201.13:59:49.84#ibcon#about to read 3, iclass 17, count 0 2006.201.13:59:49.87#ibcon#read 3, iclass 17, count 0 2006.201.13:59:49.87#ibcon#about to read 4, iclass 17, count 0 2006.201.13:59:49.87#ibcon#read 4, iclass 17, count 0 2006.201.13:59:49.87#ibcon#about to read 5, iclass 17, count 0 2006.201.13:59:49.87#ibcon#read 5, iclass 17, count 0 2006.201.13:59:49.87#ibcon#about to read 6, iclass 17, count 0 2006.201.13:59:49.87#ibcon#read 6, iclass 17, count 0 2006.201.13:59:49.87#ibcon#end of sib2, iclass 17, count 0 2006.201.13:59:49.87#ibcon#*after write, iclass 17, count 0 2006.201.13:59:49.87#ibcon#*before return 0, iclass 17, count 0 2006.201.13:59:49.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:49.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.13:59:49.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.13:59:49.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.13:59:49.87$vck44/vblo=5,709.99 2006.201.13:59:49.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.13:59:49.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.13:59:49.87#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:49.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:49.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:49.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:49.87#ibcon#enter wrdev, iclass 19, count 0 2006.201.13:59:49.87#ibcon#first serial, iclass 19, count 0 2006.201.13:59:49.87#ibcon#enter sib2, iclass 19, count 0 2006.201.13:59:49.87#ibcon#flushed, iclass 19, count 0 2006.201.13:59:49.87#ibcon#about to write, iclass 19, count 0 2006.201.13:59:49.87#ibcon#wrote, iclass 19, count 0 2006.201.13:59:49.87#ibcon#about to read 3, iclass 19, count 0 2006.201.13:59:49.89#ibcon#read 3, iclass 19, count 0 2006.201.13:59:49.89#ibcon#about to read 4, iclass 19, count 0 2006.201.13:59:49.89#ibcon#read 4, iclass 19, count 0 2006.201.13:59:49.89#ibcon#about to read 5, iclass 19, count 0 2006.201.13:59:49.89#ibcon#read 5, iclass 19, count 0 2006.201.13:59:49.89#ibcon#about to read 6, iclass 19, count 0 2006.201.13:59:49.89#ibcon#read 6, iclass 19, count 0 2006.201.13:59:49.89#ibcon#end of sib2, iclass 19, count 0 2006.201.13:59:49.89#ibcon#*mode == 0, iclass 19, count 0 2006.201.13:59:49.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.13:59:49.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.13:59:49.89#ibcon#*before write, iclass 19, count 0 2006.201.13:59:49.89#ibcon#enter sib2, iclass 19, count 0 2006.201.13:59:49.89#ibcon#flushed, iclass 19, count 0 2006.201.13:59:49.89#ibcon#about to write, iclass 19, count 0 2006.201.13:59:49.89#ibcon#wrote, iclass 19, count 0 2006.201.13:59:49.89#ibcon#about to read 3, iclass 19, count 0 2006.201.13:59:49.93#ibcon#read 3, iclass 19, count 0 2006.201.13:59:49.93#ibcon#about to read 4, iclass 19, count 0 2006.201.13:59:49.93#ibcon#read 4, iclass 19, count 0 2006.201.13:59:49.93#ibcon#about to read 5, iclass 19, count 0 2006.201.13:59:49.93#ibcon#read 5, iclass 19, count 0 2006.201.13:59:49.93#ibcon#about to read 6, iclass 19, count 0 2006.201.13:59:49.93#ibcon#read 6, iclass 19, count 0 2006.201.13:59:49.93#ibcon#end of sib2, iclass 19, count 0 2006.201.13:59:49.93#ibcon#*after write, iclass 19, count 0 2006.201.13:59:49.93#ibcon#*before return 0, iclass 19, count 0 2006.201.13:59:49.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:49.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.13:59:49.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.13:59:49.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.13:59:49.93$vck44/vb=5,4 2006.201.13:59:49.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.13:59:49.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.13:59:49.93#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:49.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:49.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:49.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:49.99#ibcon#enter wrdev, iclass 21, count 2 2006.201.13:59:49.99#ibcon#first serial, iclass 21, count 2 2006.201.13:59:49.99#ibcon#enter sib2, iclass 21, count 2 2006.201.13:59:49.99#ibcon#flushed, iclass 21, count 2 2006.201.13:59:49.99#ibcon#about to write, iclass 21, count 2 2006.201.13:59:49.99#ibcon#wrote, iclass 21, count 2 2006.201.13:59:49.99#ibcon#about to read 3, iclass 21, count 2 2006.201.13:59:50.01#ibcon#read 3, iclass 21, count 2 2006.201.13:59:50.01#ibcon#about to read 4, iclass 21, count 2 2006.201.13:59:50.01#ibcon#read 4, iclass 21, count 2 2006.201.13:59:50.01#ibcon#about to read 5, iclass 21, count 2 2006.201.13:59:50.01#ibcon#read 5, iclass 21, count 2 2006.201.13:59:50.01#ibcon#about to read 6, iclass 21, count 2 2006.201.13:59:50.01#ibcon#read 6, iclass 21, count 2 2006.201.13:59:50.01#ibcon#end of sib2, iclass 21, count 2 2006.201.13:59:50.01#ibcon#*mode == 0, iclass 21, count 2 2006.201.13:59:50.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.13:59:50.01#ibcon#[27=AT05-04\r\n] 2006.201.13:59:50.01#ibcon#*before write, iclass 21, count 2 2006.201.13:59:50.01#ibcon#enter sib2, iclass 21, count 2 2006.201.13:59:50.01#ibcon#flushed, iclass 21, count 2 2006.201.13:59:50.01#ibcon#about to write, iclass 21, count 2 2006.201.13:59:50.01#ibcon#wrote, iclass 21, count 2 2006.201.13:59:50.01#ibcon#about to read 3, iclass 21, count 2 2006.201.13:59:50.04#ibcon#read 3, iclass 21, count 2 2006.201.13:59:50.04#ibcon#about to read 4, iclass 21, count 2 2006.201.13:59:50.04#ibcon#read 4, iclass 21, count 2 2006.201.13:59:50.04#ibcon#about to read 5, iclass 21, count 2 2006.201.13:59:50.04#ibcon#read 5, iclass 21, count 2 2006.201.13:59:50.04#ibcon#about to read 6, iclass 21, count 2 2006.201.13:59:50.04#ibcon#read 6, iclass 21, count 2 2006.201.13:59:50.04#ibcon#end of sib2, iclass 21, count 2 2006.201.13:59:50.04#ibcon#*after write, iclass 21, count 2 2006.201.13:59:50.04#ibcon#*before return 0, iclass 21, count 2 2006.201.13:59:50.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:50.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.13:59:50.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.13:59:50.04#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:50.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:50.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:50.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:50.16#ibcon#enter wrdev, iclass 21, count 0 2006.201.13:59:50.16#ibcon#first serial, iclass 21, count 0 2006.201.13:59:50.16#ibcon#enter sib2, iclass 21, count 0 2006.201.13:59:50.16#ibcon#flushed, iclass 21, count 0 2006.201.13:59:50.16#ibcon#about to write, iclass 21, count 0 2006.201.13:59:50.16#ibcon#wrote, iclass 21, count 0 2006.201.13:59:50.16#ibcon#about to read 3, iclass 21, count 0 2006.201.13:59:50.18#ibcon#read 3, iclass 21, count 0 2006.201.13:59:50.18#ibcon#about to read 4, iclass 21, count 0 2006.201.13:59:50.18#ibcon#read 4, iclass 21, count 0 2006.201.13:59:50.18#ibcon#about to read 5, iclass 21, count 0 2006.201.13:59:50.18#ibcon#read 5, iclass 21, count 0 2006.201.13:59:50.18#ibcon#about to read 6, iclass 21, count 0 2006.201.13:59:50.18#ibcon#read 6, iclass 21, count 0 2006.201.13:59:50.18#ibcon#end of sib2, iclass 21, count 0 2006.201.13:59:50.18#ibcon#*mode == 0, iclass 21, count 0 2006.201.13:59:50.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.13:59:50.18#ibcon#[27=USB\r\n] 2006.201.13:59:50.18#ibcon#*before write, iclass 21, count 0 2006.201.13:59:50.18#ibcon#enter sib2, iclass 21, count 0 2006.201.13:59:50.18#ibcon#flushed, iclass 21, count 0 2006.201.13:59:50.18#ibcon#about to write, iclass 21, count 0 2006.201.13:59:50.18#ibcon#wrote, iclass 21, count 0 2006.201.13:59:50.18#ibcon#about to read 3, iclass 21, count 0 2006.201.13:59:50.21#ibcon#read 3, iclass 21, count 0 2006.201.13:59:50.21#ibcon#about to read 4, iclass 21, count 0 2006.201.13:59:50.21#ibcon#read 4, iclass 21, count 0 2006.201.13:59:50.21#ibcon#about to read 5, iclass 21, count 0 2006.201.13:59:50.21#ibcon#read 5, iclass 21, count 0 2006.201.13:59:50.21#ibcon#about to read 6, iclass 21, count 0 2006.201.13:59:50.21#ibcon#read 6, iclass 21, count 0 2006.201.13:59:50.21#ibcon#end of sib2, iclass 21, count 0 2006.201.13:59:50.21#ibcon#*after write, iclass 21, count 0 2006.201.13:59:50.21#ibcon#*before return 0, iclass 21, count 0 2006.201.13:59:50.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:50.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.13:59:50.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.13:59:50.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.13:59:50.21$vck44/vblo=6,719.99 2006.201.13:59:50.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.13:59:50.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.13:59:50.21#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:50.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:50.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:50.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:50.21#ibcon#enter wrdev, iclass 23, count 0 2006.201.13:59:50.21#ibcon#first serial, iclass 23, count 0 2006.201.13:59:50.21#ibcon#enter sib2, iclass 23, count 0 2006.201.13:59:50.21#ibcon#flushed, iclass 23, count 0 2006.201.13:59:50.21#ibcon#about to write, iclass 23, count 0 2006.201.13:59:50.21#ibcon#wrote, iclass 23, count 0 2006.201.13:59:50.21#ibcon#about to read 3, iclass 23, count 0 2006.201.13:59:50.23#ibcon#read 3, iclass 23, count 0 2006.201.13:59:50.23#ibcon#about to read 4, iclass 23, count 0 2006.201.13:59:50.23#ibcon#read 4, iclass 23, count 0 2006.201.13:59:50.23#ibcon#about to read 5, iclass 23, count 0 2006.201.13:59:50.23#ibcon#read 5, iclass 23, count 0 2006.201.13:59:50.23#ibcon#about to read 6, iclass 23, count 0 2006.201.13:59:50.23#ibcon#read 6, iclass 23, count 0 2006.201.13:59:50.23#ibcon#end of sib2, iclass 23, count 0 2006.201.13:59:50.23#ibcon#*mode == 0, iclass 23, count 0 2006.201.13:59:50.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.13:59:50.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.13:59:50.23#ibcon#*before write, iclass 23, count 0 2006.201.13:59:50.23#ibcon#enter sib2, iclass 23, count 0 2006.201.13:59:50.23#ibcon#flushed, iclass 23, count 0 2006.201.13:59:50.23#ibcon#about to write, iclass 23, count 0 2006.201.13:59:50.23#ibcon#wrote, iclass 23, count 0 2006.201.13:59:50.23#ibcon#about to read 3, iclass 23, count 0 2006.201.13:59:50.27#ibcon#read 3, iclass 23, count 0 2006.201.13:59:50.27#ibcon#about to read 4, iclass 23, count 0 2006.201.13:59:50.27#ibcon#read 4, iclass 23, count 0 2006.201.13:59:50.27#ibcon#about to read 5, iclass 23, count 0 2006.201.13:59:50.27#ibcon#read 5, iclass 23, count 0 2006.201.13:59:50.27#ibcon#about to read 6, iclass 23, count 0 2006.201.13:59:50.27#ibcon#read 6, iclass 23, count 0 2006.201.13:59:50.27#ibcon#end of sib2, iclass 23, count 0 2006.201.13:59:50.27#ibcon#*after write, iclass 23, count 0 2006.201.13:59:50.27#ibcon#*before return 0, iclass 23, count 0 2006.201.13:59:50.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:50.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.13:59:50.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.13:59:50.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.13:59:50.27$vck44/vb=6,4 2006.201.13:59:50.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.13:59:50.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.13:59:50.27#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:50.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:50.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:50.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:50.33#ibcon#enter wrdev, iclass 25, count 2 2006.201.13:59:50.33#ibcon#first serial, iclass 25, count 2 2006.201.13:59:50.33#ibcon#enter sib2, iclass 25, count 2 2006.201.13:59:50.33#ibcon#flushed, iclass 25, count 2 2006.201.13:59:50.33#ibcon#about to write, iclass 25, count 2 2006.201.13:59:50.33#ibcon#wrote, iclass 25, count 2 2006.201.13:59:50.33#ibcon#about to read 3, iclass 25, count 2 2006.201.13:59:50.35#ibcon#read 3, iclass 25, count 2 2006.201.13:59:50.35#ibcon#about to read 4, iclass 25, count 2 2006.201.13:59:50.35#ibcon#read 4, iclass 25, count 2 2006.201.13:59:50.35#ibcon#about to read 5, iclass 25, count 2 2006.201.13:59:50.35#ibcon#read 5, iclass 25, count 2 2006.201.13:59:50.35#ibcon#about to read 6, iclass 25, count 2 2006.201.13:59:50.35#ibcon#read 6, iclass 25, count 2 2006.201.13:59:50.35#ibcon#end of sib2, iclass 25, count 2 2006.201.13:59:50.35#ibcon#*mode == 0, iclass 25, count 2 2006.201.13:59:50.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.13:59:50.35#ibcon#[27=AT06-04\r\n] 2006.201.13:59:50.35#ibcon#*before write, iclass 25, count 2 2006.201.13:59:50.35#ibcon#enter sib2, iclass 25, count 2 2006.201.13:59:50.35#ibcon#flushed, iclass 25, count 2 2006.201.13:59:50.35#ibcon#about to write, iclass 25, count 2 2006.201.13:59:50.35#ibcon#wrote, iclass 25, count 2 2006.201.13:59:50.35#ibcon#about to read 3, iclass 25, count 2 2006.201.13:59:50.38#ibcon#read 3, iclass 25, count 2 2006.201.13:59:50.38#ibcon#about to read 4, iclass 25, count 2 2006.201.13:59:50.38#ibcon#read 4, iclass 25, count 2 2006.201.13:59:50.38#ibcon#about to read 5, iclass 25, count 2 2006.201.13:59:50.38#ibcon#read 5, iclass 25, count 2 2006.201.13:59:50.38#ibcon#about to read 6, iclass 25, count 2 2006.201.13:59:50.38#ibcon#read 6, iclass 25, count 2 2006.201.13:59:50.38#ibcon#end of sib2, iclass 25, count 2 2006.201.13:59:50.38#ibcon#*after write, iclass 25, count 2 2006.201.13:59:50.38#ibcon#*before return 0, iclass 25, count 2 2006.201.13:59:50.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:50.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.13:59:50.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.13:59:50.38#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:50.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:50.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:50.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:50.50#ibcon#enter wrdev, iclass 25, count 0 2006.201.13:59:50.50#ibcon#first serial, iclass 25, count 0 2006.201.13:59:50.50#ibcon#enter sib2, iclass 25, count 0 2006.201.13:59:50.50#ibcon#flushed, iclass 25, count 0 2006.201.13:59:50.50#ibcon#about to write, iclass 25, count 0 2006.201.13:59:50.50#ibcon#wrote, iclass 25, count 0 2006.201.13:59:50.50#ibcon#about to read 3, iclass 25, count 0 2006.201.13:59:50.52#ibcon#read 3, iclass 25, count 0 2006.201.13:59:50.52#ibcon#about to read 4, iclass 25, count 0 2006.201.13:59:50.52#ibcon#read 4, iclass 25, count 0 2006.201.13:59:50.52#ibcon#about to read 5, iclass 25, count 0 2006.201.13:59:50.52#ibcon#read 5, iclass 25, count 0 2006.201.13:59:50.52#ibcon#about to read 6, iclass 25, count 0 2006.201.13:59:50.52#ibcon#read 6, iclass 25, count 0 2006.201.13:59:50.52#ibcon#end of sib2, iclass 25, count 0 2006.201.13:59:50.52#ibcon#*mode == 0, iclass 25, count 0 2006.201.13:59:50.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.13:59:50.52#ibcon#[27=USB\r\n] 2006.201.13:59:50.52#ibcon#*before write, iclass 25, count 0 2006.201.13:59:50.52#ibcon#enter sib2, iclass 25, count 0 2006.201.13:59:50.52#ibcon#flushed, iclass 25, count 0 2006.201.13:59:50.52#ibcon#about to write, iclass 25, count 0 2006.201.13:59:50.52#ibcon#wrote, iclass 25, count 0 2006.201.13:59:50.52#ibcon#about to read 3, iclass 25, count 0 2006.201.13:59:50.55#ibcon#read 3, iclass 25, count 0 2006.201.13:59:50.55#ibcon#about to read 4, iclass 25, count 0 2006.201.13:59:50.55#ibcon#read 4, iclass 25, count 0 2006.201.13:59:50.55#ibcon#about to read 5, iclass 25, count 0 2006.201.13:59:50.55#ibcon#read 5, iclass 25, count 0 2006.201.13:59:50.55#ibcon#about to read 6, iclass 25, count 0 2006.201.13:59:50.55#ibcon#read 6, iclass 25, count 0 2006.201.13:59:50.55#ibcon#end of sib2, iclass 25, count 0 2006.201.13:59:50.55#ibcon#*after write, iclass 25, count 0 2006.201.13:59:50.55#ibcon#*before return 0, iclass 25, count 0 2006.201.13:59:50.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:50.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.13:59:50.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.13:59:50.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.13:59:50.55$vck44/vblo=7,734.99 2006.201.13:59:50.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.13:59:50.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.13:59:50.55#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:50.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:50.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:50.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:50.55#ibcon#enter wrdev, iclass 27, count 0 2006.201.13:59:50.55#ibcon#first serial, iclass 27, count 0 2006.201.13:59:50.55#ibcon#enter sib2, iclass 27, count 0 2006.201.13:59:50.55#ibcon#flushed, iclass 27, count 0 2006.201.13:59:50.55#ibcon#about to write, iclass 27, count 0 2006.201.13:59:50.55#ibcon#wrote, iclass 27, count 0 2006.201.13:59:50.55#ibcon#about to read 3, iclass 27, count 0 2006.201.13:59:50.57#ibcon#read 3, iclass 27, count 0 2006.201.13:59:50.57#ibcon#about to read 4, iclass 27, count 0 2006.201.13:59:50.57#ibcon#read 4, iclass 27, count 0 2006.201.13:59:50.57#ibcon#about to read 5, iclass 27, count 0 2006.201.13:59:50.57#ibcon#read 5, iclass 27, count 0 2006.201.13:59:50.57#ibcon#about to read 6, iclass 27, count 0 2006.201.13:59:50.57#ibcon#read 6, iclass 27, count 0 2006.201.13:59:50.57#ibcon#end of sib2, iclass 27, count 0 2006.201.13:59:50.57#ibcon#*mode == 0, iclass 27, count 0 2006.201.13:59:50.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.13:59:50.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.13:59:50.57#ibcon#*before write, iclass 27, count 0 2006.201.13:59:50.57#ibcon#enter sib2, iclass 27, count 0 2006.201.13:59:50.57#ibcon#flushed, iclass 27, count 0 2006.201.13:59:50.57#ibcon#about to write, iclass 27, count 0 2006.201.13:59:50.57#ibcon#wrote, iclass 27, count 0 2006.201.13:59:50.57#ibcon#about to read 3, iclass 27, count 0 2006.201.13:59:50.61#ibcon#read 3, iclass 27, count 0 2006.201.13:59:50.61#ibcon#about to read 4, iclass 27, count 0 2006.201.13:59:50.61#ibcon#read 4, iclass 27, count 0 2006.201.13:59:50.61#ibcon#about to read 5, iclass 27, count 0 2006.201.13:59:50.61#ibcon#read 5, iclass 27, count 0 2006.201.13:59:50.61#ibcon#about to read 6, iclass 27, count 0 2006.201.13:59:50.61#ibcon#read 6, iclass 27, count 0 2006.201.13:59:50.61#ibcon#end of sib2, iclass 27, count 0 2006.201.13:59:50.61#ibcon#*after write, iclass 27, count 0 2006.201.13:59:50.61#ibcon#*before return 0, iclass 27, count 0 2006.201.13:59:50.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:50.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.13:59:50.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.13:59:50.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.13:59:50.61$vck44/vb=7,4 2006.201.13:59:50.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.13:59:50.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.13:59:50.61#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:50.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:50.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:50.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:50.67#ibcon#enter wrdev, iclass 29, count 2 2006.201.13:59:50.67#ibcon#first serial, iclass 29, count 2 2006.201.13:59:50.67#ibcon#enter sib2, iclass 29, count 2 2006.201.13:59:50.67#ibcon#flushed, iclass 29, count 2 2006.201.13:59:50.67#ibcon#about to write, iclass 29, count 2 2006.201.13:59:50.67#ibcon#wrote, iclass 29, count 2 2006.201.13:59:50.67#ibcon#about to read 3, iclass 29, count 2 2006.201.13:59:50.69#ibcon#read 3, iclass 29, count 2 2006.201.13:59:50.69#ibcon#about to read 4, iclass 29, count 2 2006.201.13:59:50.69#ibcon#read 4, iclass 29, count 2 2006.201.13:59:50.69#ibcon#about to read 5, iclass 29, count 2 2006.201.13:59:50.69#ibcon#read 5, iclass 29, count 2 2006.201.13:59:50.69#ibcon#about to read 6, iclass 29, count 2 2006.201.13:59:50.69#ibcon#read 6, iclass 29, count 2 2006.201.13:59:50.69#ibcon#end of sib2, iclass 29, count 2 2006.201.13:59:50.69#ibcon#*mode == 0, iclass 29, count 2 2006.201.13:59:50.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.13:59:50.69#ibcon#[27=AT07-04\r\n] 2006.201.13:59:50.69#ibcon#*before write, iclass 29, count 2 2006.201.13:59:50.69#ibcon#enter sib2, iclass 29, count 2 2006.201.13:59:50.69#ibcon#flushed, iclass 29, count 2 2006.201.13:59:50.69#ibcon#about to write, iclass 29, count 2 2006.201.13:59:50.69#ibcon#wrote, iclass 29, count 2 2006.201.13:59:50.69#ibcon#about to read 3, iclass 29, count 2 2006.201.13:59:50.72#ibcon#read 3, iclass 29, count 2 2006.201.13:59:50.72#ibcon#about to read 4, iclass 29, count 2 2006.201.13:59:50.72#ibcon#read 4, iclass 29, count 2 2006.201.13:59:50.72#ibcon#about to read 5, iclass 29, count 2 2006.201.13:59:50.72#ibcon#read 5, iclass 29, count 2 2006.201.13:59:50.72#ibcon#about to read 6, iclass 29, count 2 2006.201.13:59:50.72#ibcon#read 6, iclass 29, count 2 2006.201.13:59:50.72#ibcon#end of sib2, iclass 29, count 2 2006.201.13:59:50.72#ibcon#*after write, iclass 29, count 2 2006.201.13:59:50.72#ibcon#*before return 0, iclass 29, count 2 2006.201.13:59:50.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:50.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.13:59:50.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.13:59:50.72#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:50.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:50.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:50.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:50.84#ibcon#enter wrdev, iclass 29, count 0 2006.201.13:59:50.84#ibcon#first serial, iclass 29, count 0 2006.201.13:59:50.84#ibcon#enter sib2, iclass 29, count 0 2006.201.13:59:50.84#ibcon#flushed, iclass 29, count 0 2006.201.13:59:50.84#ibcon#about to write, iclass 29, count 0 2006.201.13:59:50.84#ibcon#wrote, iclass 29, count 0 2006.201.13:59:50.84#ibcon#about to read 3, iclass 29, count 0 2006.201.13:59:50.86#ibcon#read 3, iclass 29, count 0 2006.201.13:59:50.86#ibcon#about to read 4, iclass 29, count 0 2006.201.13:59:50.86#ibcon#read 4, iclass 29, count 0 2006.201.13:59:50.86#ibcon#about to read 5, iclass 29, count 0 2006.201.13:59:50.86#ibcon#read 5, iclass 29, count 0 2006.201.13:59:50.86#ibcon#about to read 6, iclass 29, count 0 2006.201.13:59:50.86#ibcon#read 6, iclass 29, count 0 2006.201.13:59:50.86#ibcon#end of sib2, iclass 29, count 0 2006.201.13:59:50.86#ibcon#*mode == 0, iclass 29, count 0 2006.201.13:59:50.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.13:59:50.86#ibcon#[27=USB\r\n] 2006.201.13:59:50.86#ibcon#*before write, iclass 29, count 0 2006.201.13:59:50.86#ibcon#enter sib2, iclass 29, count 0 2006.201.13:59:50.86#ibcon#flushed, iclass 29, count 0 2006.201.13:59:50.86#ibcon#about to write, iclass 29, count 0 2006.201.13:59:50.86#ibcon#wrote, iclass 29, count 0 2006.201.13:59:50.86#ibcon#about to read 3, iclass 29, count 0 2006.201.13:59:50.89#ibcon#read 3, iclass 29, count 0 2006.201.13:59:50.89#ibcon#about to read 4, iclass 29, count 0 2006.201.13:59:50.89#ibcon#read 4, iclass 29, count 0 2006.201.13:59:50.89#ibcon#about to read 5, iclass 29, count 0 2006.201.13:59:50.89#ibcon#read 5, iclass 29, count 0 2006.201.13:59:50.89#ibcon#about to read 6, iclass 29, count 0 2006.201.13:59:50.89#ibcon#read 6, iclass 29, count 0 2006.201.13:59:50.89#ibcon#end of sib2, iclass 29, count 0 2006.201.13:59:50.89#ibcon#*after write, iclass 29, count 0 2006.201.13:59:50.89#ibcon#*before return 0, iclass 29, count 0 2006.201.13:59:50.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:50.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.13:59:50.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.13:59:50.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.13:59:50.89$vck44/vblo=8,744.99 2006.201.13:59:50.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.13:59:50.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.13:59:50.89#ibcon#ireg 17 cls_cnt 0 2006.201.13:59:50.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:50.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:50.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:50.89#ibcon#enter wrdev, iclass 31, count 0 2006.201.13:59:50.89#ibcon#first serial, iclass 31, count 0 2006.201.13:59:50.89#ibcon#enter sib2, iclass 31, count 0 2006.201.13:59:50.89#ibcon#flushed, iclass 31, count 0 2006.201.13:59:50.89#ibcon#about to write, iclass 31, count 0 2006.201.13:59:50.89#ibcon#wrote, iclass 31, count 0 2006.201.13:59:50.89#ibcon#about to read 3, iclass 31, count 0 2006.201.13:59:50.91#ibcon#read 3, iclass 31, count 0 2006.201.13:59:50.91#ibcon#about to read 4, iclass 31, count 0 2006.201.13:59:50.91#ibcon#read 4, iclass 31, count 0 2006.201.13:59:50.91#ibcon#about to read 5, iclass 31, count 0 2006.201.13:59:50.91#ibcon#read 5, iclass 31, count 0 2006.201.13:59:50.91#ibcon#about to read 6, iclass 31, count 0 2006.201.13:59:50.91#ibcon#read 6, iclass 31, count 0 2006.201.13:59:50.91#ibcon#end of sib2, iclass 31, count 0 2006.201.13:59:50.91#ibcon#*mode == 0, iclass 31, count 0 2006.201.13:59:50.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.13:59:50.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.13:59:50.91#ibcon#*before write, iclass 31, count 0 2006.201.13:59:50.91#ibcon#enter sib2, iclass 31, count 0 2006.201.13:59:50.91#ibcon#flushed, iclass 31, count 0 2006.201.13:59:50.91#ibcon#about to write, iclass 31, count 0 2006.201.13:59:50.91#ibcon#wrote, iclass 31, count 0 2006.201.13:59:50.91#ibcon#about to read 3, iclass 31, count 0 2006.201.13:59:50.96#ibcon#read 3, iclass 31, count 0 2006.201.13:59:50.96#ibcon#about to read 4, iclass 31, count 0 2006.201.13:59:50.96#ibcon#read 4, iclass 31, count 0 2006.201.13:59:50.96#ibcon#about to read 5, iclass 31, count 0 2006.201.13:59:50.96#ibcon#read 5, iclass 31, count 0 2006.201.13:59:50.96#ibcon#about to read 6, iclass 31, count 0 2006.201.13:59:50.96#ibcon#read 6, iclass 31, count 0 2006.201.13:59:50.96#ibcon#end of sib2, iclass 31, count 0 2006.201.13:59:50.96#ibcon#*after write, iclass 31, count 0 2006.201.13:59:50.96#ibcon#*before return 0, iclass 31, count 0 2006.201.13:59:50.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:50.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.13:59:50.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.13:59:50.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.13:59:50.96$vck44/vb=8,4 2006.201.13:59:50.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.13:59:50.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.13:59:50.96#ibcon#ireg 11 cls_cnt 2 2006.201.13:59:50.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:51.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:51.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:51.01#ibcon#enter wrdev, iclass 33, count 2 2006.201.13:59:51.01#ibcon#first serial, iclass 33, count 2 2006.201.13:59:51.01#ibcon#enter sib2, iclass 33, count 2 2006.201.13:59:51.01#ibcon#flushed, iclass 33, count 2 2006.201.13:59:51.01#ibcon#about to write, iclass 33, count 2 2006.201.13:59:51.01#ibcon#wrote, iclass 33, count 2 2006.201.13:59:51.01#ibcon#about to read 3, iclass 33, count 2 2006.201.13:59:51.03#ibcon#read 3, iclass 33, count 2 2006.201.13:59:51.03#ibcon#about to read 4, iclass 33, count 2 2006.201.13:59:51.03#ibcon#read 4, iclass 33, count 2 2006.201.13:59:51.03#ibcon#about to read 5, iclass 33, count 2 2006.201.13:59:51.03#ibcon#read 5, iclass 33, count 2 2006.201.13:59:51.03#ibcon#about to read 6, iclass 33, count 2 2006.201.13:59:51.03#ibcon#read 6, iclass 33, count 2 2006.201.13:59:51.03#ibcon#end of sib2, iclass 33, count 2 2006.201.13:59:51.03#ibcon#*mode == 0, iclass 33, count 2 2006.201.13:59:51.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.13:59:51.03#ibcon#[27=AT08-04\r\n] 2006.201.13:59:51.03#ibcon#*before write, iclass 33, count 2 2006.201.13:59:51.03#ibcon#enter sib2, iclass 33, count 2 2006.201.13:59:51.03#ibcon#flushed, iclass 33, count 2 2006.201.13:59:51.03#ibcon#about to write, iclass 33, count 2 2006.201.13:59:51.03#ibcon#wrote, iclass 33, count 2 2006.201.13:59:51.03#ibcon#about to read 3, iclass 33, count 2 2006.201.13:59:51.06#ibcon#read 3, iclass 33, count 2 2006.201.13:59:51.06#ibcon#about to read 4, iclass 33, count 2 2006.201.13:59:51.06#ibcon#read 4, iclass 33, count 2 2006.201.13:59:51.06#ibcon#about to read 5, iclass 33, count 2 2006.201.13:59:51.06#ibcon#read 5, iclass 33, count 2 2006.201.13:59:51.06#ibcon#about to read 6, iclass 33, count 2 2006.201.13:59:51.06#ibcon#read 6, iclass 33, count 2 2006.201.13:59:51.06#ibcon#end of sib2, iclass 33, count 2 2006.201.13:59:51.06#ibcon#*after write, iclass 33, count 2 2006.201.13:59:51.06#ibcon#*before return 0, iclass 33, count 2 2006.201.13:59:51.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:51.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.13:59:51.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.13:59:51.06#ibcon#ireg 7 cls_cnt 0 2006.201.13:59:51.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:51.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:51.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:51.18#ibcon#enter wrdev, iclass 33, count 0 2006.201.13:59:51.18#ibcon#first serial, iclass 33, count 0 2006.201.13:59:51.18#ibcon#enter sib2, iclass 33, count 0 2006.201.13:59:51.18#ibcon#flushed, iclass 33, count 0 2006.201.13:59:51.18#ibcon#about to write, iclass 33, count 0 2006.201.13:59:51.18#ibcon#wrote, iclass 33, count 0 2006.201.13:59:51.18#ibcon#about to read 3, iclass 33, count 0 2006.201.13:59:51.20#ibcon#read 3, iclass 33, count 0 2006.201.13:59:51.20#ibcon#about to read 4, iclass 33, count 0 2006.201.13:59:51.20#ibcon#read 4, iclass 33, count 0 2006.201.13:59:51.20#ibcon#about to read 5, iclass 33, count 0 2006.201.13:59:51.20#ibcon#read 5, iclass 33, count 0 2006.201.13:59:51.20#ibcon#about to read 6, iclass 33, count 0 2006.201.13:59:51.20#ibcon#read 6, iclass 33, count 0 2006.201.13:59:51.20#ibcon#end of sib2, iclass 33, count 0 2006.201.13:59:51.20#ibcon#*mode == 0, iclass 33, count 0 2006.201.13:59:51.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.13:59:51.20#ibcon#[27=USB\r\n] 2006.201.13:59:51.20#ibcon#*before write, iclass 33, count 0 2006.201.13:59:51.20#ibcon#enter sib2, iclass 33, count 0 2006.201.13:59:51.20#ibcon#flushed, iclass 33, count 0 2006.201.13:59:51.20#ibcon#about to write, iclass 33, count 0 2006.201.13:59:51.20#ibcon#wrote, iclass 33, count 0 2006.201.13:59:51.20#ibcon#about to read 3, iclass 33, count 0 2006.201.13:59:51.23#ibcon#read 3, iclass 33, count 0 2006.201.13:59:51.23#ibcon#about to read 4, iclass 33, count 0 2006.201.13:59:51.23#ibcon#read 4, iclass 33, count 0 2006.201.13:59:51.23#ibcon#about to read 5, iclass 33, count 0 2006.201.13:59:51.23#ibcon#read 5, iclass 33, count 0 2006.201.13:59:51.23#ibcon#about to read 6, iclass 33, count 0 2006.201.13:59:51.23#ibcon#read 6, iclass 33, count 0 2006.201.13:59:51.23#ibcon#end of sib2, iclass 33, count 0 2006.201.13:59:51.23#ibcon#*after write, iclass 33, count 0 2006.201.13:59:51.23#ibcon#*before return 0, iclass 33, count 0 2006.201.13:59:51.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:51.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.13:59:51.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.13:59:51.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.13:59:51.23$vck44/vabw=wide 2006.201.13:59:51.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.13:59:51.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.13:59:51.23#ibcon#ireg 8 cls_cnt 0 2006.201.13:59:51.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:51.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:51.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:51.23#ibcon#enter wrdev, iclass 35, count 0 2006.201.13:59:51.23#ibcon#first serial, iclass 35, count 0 2006.201.13:59:51.23#ibcon#enter sib2, iclass 35, count 0 2006.201.13:59:51.23#ibcon#flushed, iclass 35, count 0 2006.201.13:59:51.23#ibcon#about to write, iclass 35, count 0 2006.201.13:59:51.23#ibcon#wrote, iclass 35, count 0 2006.201.13:59:51.23#ibcon#about to read 3, iclass 35, count 0 2006.201.13:59:51.25#ibcon#read 3, iclass 35, count 0 2006.201.13:59:51.25#ibcon#about to read 4, iclass 35, count 0 2006.201.13:59:51.25#ibcon#read 4, iclass 35, count 0 2006.201.13:59:51.25#ibcon#about to read 5, iclass 35, count 0 2006.201.13:59:51.25#ibcon#read 5, iclass 35, count 0 2006.201.13:59:51.25#ibcon#about to read 6, iclass 35, count 0 2006.201.13:59:51.25#ibcon#read 6, iclass 35, count 0 2006.201.13:59:51.25#ibcon#end of sib2, iclass 35, count 0 2006.201.13:59:51.25#ibcon#*mode == 0, iclass 35, count 0 2006.201.13:59:51.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.13:59:51.25#ibcon#[25=BW32\r\n] 2006.201.13:59:51.25#ibcon#*before write, iclass 35, count 0 2006.201.13:59:51.25#ibcon#enter sib2, iclass 35, count 0 2006.201.13:59:51.25#ibcon#flushed, iclass 35, count 0 2006.201.13:59:51.25#ibcon#about to write, iclass 35, count 0 2006.201.13:59:51.25#ibcon#wrote, iclass 35, count 0 2006.201.13:59:51.25#ibcon#about to read 3, iclass 35, count 0 2006.201.13:59:51.28#ibcon#read 3, iclass 35, count 0 2006.201.13:59:51.28#ibcon#about to read 4, iclass 35, count 0 2006.201.13:59:51.28#ibcon#read 4, iclass 35, count 0 2006.201.13:59:51.28#ibcon#about to read 5, iclass 35, count 0 2006.201.13:59:51.28#ibcon#read 5, iclass 35, count 0 2006.201.13:59:51.28#ibcon#about to read 6, iclass 35, count 0 2006.201.13:59:51.28#ibcon#read 6, iclass 35, count 0 2006.201.13:59:51.28#ibcon#end of sib2, iclass 35, count 0 2006.201.13:59:51.28#ibcon#*after write, iclass 35, count 0 2006.201.13:59:51.28#ibcon#*before return 0, iclass 35, count 0 2006.201.13:59:51.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:51.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.13:59:51.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.13:59:51.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.13:59:51.28$vck44/vbbw=wide 2006.201.13:59:51.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.13:59:51.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.13:59:51.28#ibcon#ireg 8 cls_cnt 0 2006.201.13:59:51.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:59:51.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:59:51.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:59:51.35#ibcon#enter wrdev, iclass 37, count 0 2006.201.13:59:51.35#ibcon#first serial, iclass 37, count 0 2006.201.13:59:51.35#ibcon#enter sib2, iclass 37, count 0 2006.201.13:59:51.35#ibcon#flushed, iclass 37, count 0 2006.201.13:59:51.35#ibcon#about to write, iclass 37, count 0 2006.201.13:59:51.35#ibcon#wrote, iclass 37, count 0 2006.201.13:59:51.35#ibcon#about to read 3, iclass 37, count 0 2006.201.13:59:51.37#ibcon#read 3, iclass 37, count 0 2006.201.13:59:51.37#ibcon#about to read 4, iclass 37, count 0 2006.201.13:59:51.37#ibcon#read 4, iclass 37, count 0 2006.201.13:59:51.37#ibcon#about to read 5, iclass 37, count 0 2006.201.13:59:51.37#ibcon#read 5, iclass 37, count 0 2006.201.13:59:51.37#ibcon#about to read 6, iclass 37, count 0 2006.201.13:59:51.37#ibcon#read 6, iclass 37, count 0 2006.201.13:59:51.37#ibcon#end of sib2, iclass 37, count 0 2006.201.13:59:51.37#ibcon#*mode == 0, iclass 37, count 0 2006.201.13:59:51.37#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.13:59:51.37#ibcon#[27=BW32\r\n] 2006.201.13:59:51.37#ibcon#*before write, iclass 37, count 0 2006.201.13:59:51.37#ibcon#enter sib2, iclass 37, count 0 2006.201.13:59:51.37#ibcon#flushed, iclass 37, count 0 2006.201.13:59:51.37#ibcon#about to write, iclass 37, count 0 2006.201.13:59:51.37#ibcon#wrote, iclass 37, count 0 2006.201.13:59:51.37#ibcon#about to read 3, iclass 37, count 0 2006.201.13:59:51.40#ibcon#read 3, iclass 37, count 0 2006.201.13:59:51.40#ibcon#about to read 4, iclass 37, count 0 2006.201.13:59:51.40#ibcon#read 4, iclass 37, count 0 2006.201.13:59:51.40#ibcon#about to read 5, iclass 37, count 0 2006.201.13:59:51.40#ibcon#read 5, iclass 37, count 0 2006.201.13:59:51.40#ibcon#about to read 6, iclass 37, count 0 2006.201.13:59:51.40#ibcon#read 6, iclass 37, count 0 2006.201.13:59:51.40#ibcon#end of sib2, iclass 37, count 0 2006.201.13:59:51.40#ibcon#*after write, iclass 37, count 0 2006.201.13:59:51.40#ibcon#*before return 0, iclass 37, count 0 2006.201.13:59:51.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:59:51.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.13:59:51.40#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.13:59:51.40#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.13:59:51.40$setupk4/ifdk4 2006.201.13:59:51.40$ifdk4/lo= 2006.201.13:59:51.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.13:59:51.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.13:59:51.40$ifdk4/patch= 2006.201.13:59:51.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.13:59:51.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.13:59:51.40$setupk4/!*+20s 2006.201.13:59:52.41#abcon#<5=/04 1.2 2.1 20.871001004.0\r\n> 2006.201.13:59:52.43#abcon#{5=INTERFACE CLEAR} 2006.201.13:59:52.49#abcon#[5=S1D000X0/0*\r\n] 2006.201.13:59:59.14#trakl#Source acquired 2006.201.13:59:59.14#flagr#flagr/antenna,acquired 2006.201.14:00:02.58#abcon#<5=/04 1.2 2.1 20.871001004.0\r\n> 2006.201.14:00:02.60#abcon#{5=INTERFACE CLEAR} 2006.201.14:00:02.66#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:00:05.88$setupk4/"tpicd 2006.201.14:00:05.88$setupk4/echo=off 2006.201.14:00:05.88$setupk4/xlog=off 2006.201.14:00:05.88:!2006.201.14:00:23 2006.201.14:00:23.00:preob 2006.201.14:00:24.14/onsource/TRACKING 2006.201.14:00:24.14:!2006.201.14:00:33 2006.201.14:00:33.00:"tape 2006.201.14:00:33.00:"st=record 2006.201.14:00:33.00:data_valid=on 2006.201.14:00:33.00:midob 2006.201.14:00:33.14/onsource/TRACKING 2006.201.14:00:33.14/wx/20.87,1004.0,100 2006.201.14:00:33.25/cable/+6.4743E-03 2006.201.14:00:34.34/va/01,08,usb,yes,29,31 2006.201.14:00:34.34/va/02,07,usb,yes,31,32 2006.201.14:00:34.34/va/03,08,usb,yes,28,29 2006.201.14:00:34.34/va/04,07,usb,yes,32,34 2006.201.14:00:34.34/va/05,04,usb,yes,28,29 2006.201.14:00:34.34/va/06,05,usb,yes,28,28 2006.201.14:00:34.34/va/07,05,usb,yes,28,29 2006.201.14:00:34.34/va/08,04,usb,yes,27,33 2006.201.14:00:34.57/valo/01,524.99,yes,locked 2006.201.14:00:34.57/valo/02,534.99,yes,locked 2006.201.14:00:34.57/valo/03,564.99,yes,locked 2006.201.14:00:34.57/valo/04,624.99,yes,locked 2006.201.14:00:34.57/valo/05,734.99,yes,locked 2006.201.14:00:34.57/valo/06,814.99,yes,locked 2006.201.14:00:34.57/valo/07,864.99,yes,locked 2006.201.14:00:34.57/valo/08,884.99,yes,locked 2006.201.14:00:35.66/vb/01,04,usb,yes,28,26 2006.201.14:00:35.66/vb/02,05,usb,yes,27,27 2006.201.14:00:35.66/vb/03,04,usb,yes,28,31 2006.201.14:00:35.66/vb/04,05,usb,yes,28,27 2006.201.14:00:35.66/vb/05,04,usb,yes,25,27 2006.201.14:00:35.66/vb/06,04,usb,yes,29,25 2006.201.14:00:35.66/vb/07,04,usb,yes,29,29 2006.201.14:00:35.66/vb/08,04,usb,yes,27,30 2006.201.14:00:35.90/vblo/01,629.99,yes,locked 2006.201.14:00:35.90/vblo/02,634.99,yes,locked 2006.201.14:00:35.90/vblo/03,649.99,yes,locked 2006.201.14:00:35.90/vblo/04,679.99,yes,locked 2006.201.14:00:35.90/vblo/05,709.99,yes,locked 2006.201.14:00:35.90/vblo/06,719.99,yes,locked 2006.201.14:00:35.90/vblo/07,734.99,yes,locked 2006.201.14:00:35.90/vblo/08,744.99,yes,locked 2006.201.14:00:36.05/vabw/8 2006.201.14:00:36.20/vbbw/8 2006.201.14:00:36.29/xfe/off,on,15.0 2006.201.14:00:36.68/ifatt/23,28,28,28 2006.201.14:00:37.05/fmout-gps/S +4.52E-07 2006.201.14:00:37.12:!2006.201.14:01:13 2006.201.14:01:13.00:data_valid=off 2006.201.14:01:13.00:"et 2006.201.14:01:13.00:!+3s 2006.201.14:01:16.02:"tape 2006.201.14:01:16.02:postob 2006.201.14:01:16.24/cable/+6.4761E-03 2006.201.14:01:16.24/wx/20.87,1004.0,100 2006.201.14:01:16.31/fmout-gps/S +4.51E-07 2006.201.14:01:16.31:scan_name=201-1403,jd0607,710 2006.201.14:01:16.31:source=1749+096,175132.82,093900.7,2000.0,cw 2006.201.14:01:18.14#flagr#flagr/antenna,new-source 2006.201.14:01:18.14:checkk5 2006.201.14:01:18.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:01:18.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:01:19.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:01:19.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:01:20.00/chk_obsdata//k5ts1/T2011400??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:01:20.37/chk_obsdata//k5ts2/T2011400??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:01:20.73/chk_obsdata//k5ts3/T2011400??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:01:21.10/chk_obsdata//k5ts4/T2011400??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:01:21.79/k5log//k5ts1_log_newline 2006.201.14:01:22.47/k5log//k5ts2_log_newline 2006.201.14:01:23.15/k5log//k5ts3_log_newline 2006.201.14:01:23.84/k5log//k5ts4_log_newline 2006.201.14:01:23.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:01:23.86:setupk4=1 2006.201.14:01:23.86$setupk4/echo=on 2006.201.14:01:23.86$setupk4/pcalon 2006.201.14:01:23.86$pcalon/"no phase cal control is implemented here 2006.201.14:01:23.86$setupk4/"tpicd=stop 2006.201.14:01:23.86$setupk4/"rec=synch_on 2006.201.14:01:23.86$setupk4/"rec_mode=128 2006.201.14:01:23.86$setupk4/!* 2006.201.14:01:23.86$setupk4/recpk4 2006.201.14:01:23.86$recpk4/recpatch= 2006.201.14:01:23.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:01:23.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:01:23.87$setupk4/vck44 2006.201.14:01:23.87$vck44/valo=1,524.99 2006.201.14:01:23.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.14:01:23.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.14:01:23.87#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:23.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:23.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:23.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:23.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.14:01:23.87#ibcon#first serial, iclass 4, count 0 2006.201.14:01:23.87#ibcon#enter sib2, iclass 4, count 0 2006.201.14:01:23.87#ibcon#flushed, iclass 4, count 0 2006.201.14:01:23.87#ibcon#about to write, iclass 4, count 0 2006.201.14:01:23.87#ibcon#wrote, iclass 4, count 0 2006.201.14:01:23.87#ibcon#about to read 3, iclass 4, count 0 2006.201.14:01:23.90#ibcon#read 3, iclass 4, count 0 2006.201.14:01:23.90#ibcon#about to read 4, iclass 4, count 0 2006.201.14:01:23.90#ibcon#read 4, iclass 4, count 0 2006.201.14:01:23.90#ibcon#about to read 5, iclass 4, count 0 2006.201.14:01:23.90#ibcon#read 5, iclass 4, count 0 2006.201.14:01:23.90#ibcon#about to read 6, iclass 4, count 0 2006.201.14:01:23.90#ibcon#read 6, iclass 4, count 0 2006.201.14:01:23.90#ibcon#end of sib2, iclass 4, count 0 2006.201.14:01:23.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.14:01:23.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.14:01:23.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:01:23.90#ibcon#*before write, iclass 4, count 0 2006.201.14:01:23.90#ibcon#enter sib2, iclass 4, count 0 2006.201.14:01:23.90#ibcon#flushed, iclass 4, count 0 2006.201.14:01:23.90#ibcon#about to write, iclass 4, count 0 2006.201.14:01:23.90#ibcon#wrote, iclass 4, count 0 2006.201.14:01:23.90#ibcon#about to read 3, iclass 4, count 0 2006.201.14:01:23.95#abcon#<5=/04 1.2 2.3 20.871001004.0\r\n> 2006.201.14:01:23.95#ibcon#read 3, iclass 4, count 0 2006.201.14:01:23.95#ibcon#about to read 4, iclass 4, count 0 2006.201.14:01:23.95#ibcon#read 4, iclass 4, count 0 2006.201.14:01:23.95#ibcon#about to read 5, iclass 4, count 0 2006.201.14:01:23.95#ibcon#read 5, iclass 4, count 0 2006.201.14:01:23.95#ibcon#about to read 6, iclass 4, count 0 2006.201.14:01:23.95#ibcon#read 6, iclass 4, count 0 2006.201.14:01:23.95#ibcon#end of sib2, iclass 4, count 0 2006.201.14:01:23.95#ibcon#*after write, iclass 4, count 0 2006.201.14:01:23.95#ibcon#*before return 0, iclass 4, count 0 2006.201.14:01:23.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:23.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:23.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.14:01:23.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.14:01:23.95$vck44/va=1,8 2006.201.14:01:23.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.14:01:23.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.14:01:23.95#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:23.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:01:23.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:01:23.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:01:23.95#ibcon#enter wrdev, iclass 11, count 2 2006.201.14:01:23.95#ibcon#first serial, iclass 11, count 2 2006.201.14:01:23.95#ibcon#enter sib2, iclass 11, count 2 2006.201.14:01:23.95#ibcon#flushed, iclass 11, count 2 2006.201.14:01:23.95#ibcon#about to write, iclass 11, count 2 2006.201.14:01:23.95#ibcon#wrote, iclass 11, count 2 2006.201.14:01:23.95#ibcon#about to read 3, iclass 11, count 2 2006.201.14:01:23.97#abcon#{5=INTERFACE CLEAR} 2006.201.14:01:23.97#ibcon#read 3, iclass 11, count 2 2006.201.14:01:23.97#ibcon#about to read 4, iclass 11, count 2 2006.201.14:01:23.97#ibcon#read 4, iclass 11, count 2 2006.201.14:01:23.97#ibcon#about to read 5, iclass 11, count 2 2006.201.14:01:23.97#ibcon#read 5, iclass 11, count 2 2006.201.14:01:23.97#ibcon#about to read 6, iclass 11, count 2 2006.201.14:01:23.97#ibcon#read 6, iclass 11, count 2 2006.201.14:01:23.97#ibcon#end of sib2, iclass 11, count 2 2006.201.14:01:23.97#ibcon#*mode == 0, iclass 11, count 2 2006.201.14:01:23.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.14:01:23.97#ibcon#[25=AT01-08\r\n] 2006.201.14:01:23.97#ibcon#*before write, iclass 11, count 2 2006.201.14:01:23.97#ibcon#enter sib2, iclass 11, count 2 2006.201.14:01:23.97#ibcon#flushed, iclass 11, count 2 2006.201.14:01:23.97#ibcon#about to write, iclass 11, count 2 2006.201.14:01:23.97#ibcon#wrote, iclass 11, count 2 2006.201.14:01:23.97#ibcon#about to read 3, iclass 11, count 2 2006.201.14:01:24.00#ibcon#read 3, iclass 11, count 2 2006.201.14:01:24.00#ibcon#about to read 4, iclass 11, count 2 2006.201.14:01:24.00#ibcon#read 4, iclass 11, count 2 2006.201.14:01:24.00#ibcon#about to read 5, iclass 11, count 2 2006.201.14:01:24.00#ibcon#read 5, iclass 11, count 2 2006.201.14:01:24.00#ibcon#about to read 6, iclass 11, count 2 2006.201.14:01:24.00#ibcon#read 6, iclass 11, count 2 2006.201.14:01:24.00#ibcon#end of sib2, iclass 11, count 2 2006.201.14:01:24.00#ibcon#*after write, iclass 11, count 2 2006.201.14:01:24.00#ibcon#*before return 0, iclass 11, count 2 2006.201.14:01:24.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:01:24.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:01:24.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.14:01:24.00#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:24.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:01:24.03#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:01:24.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:01:24.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:01:24.12#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:01:24.12#ibcon#first serial, iclass 11, count 0 2006.201.14:01:24.12#ibcon#enter sib2, iclass 11, count 0 2006.201.14:01:24.12#ibcon#flushed, iclass 11, count 0 2006.201.14:01:24.12#ibcon#about to write, iclass 11, count 0 2006.201.14:01:24.12#ibcon#wrote, iclass 11, count 0 2006.201.14:01:24.12#ibcon#about to read 3, iclass 11, count 0 2006.201.14:01:24.14#ibcon#read 3, iclass 11, count 0 2006.201.14:01:24.14#ibcon#about to read 4, iclass 11, count 0 2006.201.14:01:24.14#ibcon#read 4, iclass 11, count 0 2006.201.14:01:24.14#ibcon#about to read 5, iclass 11, count 0 2006.201.14:01:24.14#ibcon#read 5, iclass 11, count 0 2006.201.14:01:24.14#ibcon#about to read 6, iclass 11, count 0 2006.201.14:01:24.14#ibcon#read 6, iclass 11, count 0 2006.201.14:01:24.14#ibcon#end of sib2, iclass 11, count 0 2006.201.14:01:24.14#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:01:24.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:01:24.14#ibcon#[25=USB\r\n] 2006.201.14:01:24.14#ibcon#*before write, iclass 11, count 0 2006.201.14:01:24.14#ibcon#enter sib2, iclass 11, count 0 2006.201.14:01:24.14#ibcon#flushed, iclass 11, count 0 2006.201.14:01:24.14#ibcon#about to write, iclass 11, count 0 2006.201.14:01:24.14#ibcon#wrote, iclass 11, count 0 2006.201.14:01:24.14#ibcon#about to read 3, iclass 11, count 0 2006.201.14:01:24.17#ibcon#read 3, iclass 11, count 0 2006.201.14:01:24.17#ibcon#about to read 4, iclass 11, count 0 2006.201.14:01:24.17#ibcon#read 4, iclass 11, count 0 2006.201.14:01:24.17#ibcon#about to read 5, iclass 11, count 0 2006.201.14:01:24.17#ibcon#read 5, iclass 11, count 0 2006.201.14:01:24.17#ibcon#about to read 6, iclass 11, count 0 2006.201.14:01:24.17#ibcon#read 6, iclass 11, count 0 2006.201.14:01:24.17#ibcon#end of sib2, iclass 11, count 0 2006.201.14:01:24.17#ibcon#*after write, iclass 11, count 0 2006.201.14:01:24.17#ibcon#*before return 0, iclass 11, count 0 2006.201.14:01:24.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:01:24.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:01:24.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:01:24.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:01:24.17$vck44/valo=2,534.99 2006.201.14:01:24.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.14:01:24.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.14:01:24.17#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:24.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:24.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:24.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:24.17#ibcon#enter wrdev, iclass 14, count 0 2006.201.14:01:24.17#ibcon#first serial, iclass 14, count 0 2006.201.14:01:24.17#ibcon#enter sib2, iclass 14, count 0 2006.201.14:01:24.17#ibcon#flushed, iclass 14, count 0 2006.201.14:01:24.17#ibcon#about to write, iclass 14, count 0 2006.201.14:01:24.17#ibcon#wrote, iclass 14, count 0 2006.201.14:01:24.17#ibcon#about to read 3, iclass 14, count 0 2006.201.14:01:24.19#ibcon#read 3, iclass 14, count 0 2006.201.14:01:24.19#ibcon#about to read 4, iclass 14, count 0 2006.201.14:01:24.19#ibcon#read 4, iclass 14, count 0 2006.201.14:01:24.19#ibcon#about to read 5, iclass 14, count 0 2006.201.14:01:24.19#ibcon#read 5, iclass 14, count 0 2006.201.14:01:24.19#ibcon#about to read 6, iclass 14, count 0 2006.201.14:01:24.19#ibcon#read 6, iclass 14, count 0 2006.201.14:01:24.19#ibcon#end of sib2, iclass 14, count 0 2006.201.14:01:24.19#ibcon#*mode == 0, iclass 14, count 0 2006.201.14:01:24.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.14:01:24.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:01:24.19#ibcon#*before write, iclass 14, count 0 2006.201.14:01:24.19#ibcon#enter sib2, iclass 14, count 0 2006.201.14:01:24.19#ibcon#flushed, iclass 14, count 0 2006.201.14:01:24.19#ibcon#about to write, iclass 14, count 0 2006.201.14:01:24.19#ibcon#wrote, iclass 14, count 0 2006.201.14:01:24.19#ibcon#about to read 3, iclass 14, count 0 2006.201.14:01:24.24#ibcon#read 3, iclass 14, count 0 2006.201.14:01:24.24#ibcon#about to read 4, iclass 14, count 0 2006.201.14:01:24.24#ibcon#read 4, iclass 14, count 0 2006.201.14:01:24.24#ibcon#about to read 5, iclass 14, count 0 2006.201.14:01:24.24#ibcon#read 5, iclass 14, count 0 2006.201.14:01:24.24#ibcon#about to read 6, iclass 14, count 0 2006.201.14:01:24.24#ibcon#read 6, iclass 14, count 0 2006.201.14:01:24.24#ibcon#end of sib2, iclass 14, count 0 2006.201.14:01:24.24#ibcon#*after write, iclass 14, count 0 2006.201.14:01:24.24#ibcon#*before return 0, iclass 14, count 0 2006.201.14:01:24.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:24.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:24.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.14:01:24.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.14:01:24.24$vck44/va=2,7 2006.201.14:01:24.24#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.14:01:24.24#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.14:01:24.24#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:24.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:24.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:24.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:24.29#ibcon#enter wrdev, iclass 16, count 2 2006.201.14:01:24.29#ibcon#first serial, iclass 16, count 2 2006.201.14:01:24.29#ibcon#enter sib2, iclass 16, count 2 2006.201.14:01:24.29#ibcon#flushed, iclass 16, count 2 2006.201.14:01:24.29#ibcon#about to write, iclass 16, count 2 2006.201.14:01:24.29#ibcon#wrote, iclass 16, count 2 2006.201.14:01:24.29#ibcon#about to read 3, iclass 16, count 2 2006.201.14:01:24.31#ibcon#read 3, iclass 16, count 2 2006.201.14:01:24.31#ibcon#about to read 4, iclass 16, count 2 2006.201.14:01:24.31#ibcon#read 4, iclass 16, count 2 2006.201.14:01:24.31#ibcon#about to read 5, iclass 16, count 2 2006.201.14:01:24.31#ibcon#read 5, iclass 16, count 2 2006.201.14:01:24.31#ibcon#about to read 6, iclass 16, count 2 2006.201.14:01:24.31#ibcon#read 6, iclass 16, count 2 2006.201.14:01:24.31#ibcon#end of sib2, iclass 16, count 2 2006.201.14:01:24.31#ibcon#*mode == 0, iclass 16, count 2 2006.201.14:01:24.31#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.14:01:24.31#ibcon#[25=AT02-07\r\n] 2006.201.14:01:24.31#ibcon#*before write, iclass 16, count 2 2006.201.14:01:24.31#ibcon#enter sib2, iclass 16, count 2 2006.201.14:01:24.31#ibcon#flushed, iclass 16, count 2 2006.201.14:01:24.31#ibcon#about to write, iclass 16, count 2 2006.201.14:01:24.31#ibcon#wrote, iclass 16, count 2 2006.201.14:01:24.31#ibcon#about to read 3, iclass 16, count 2 2006.201.14:01:24.34#ibcon#read 3, iclass 16, count 2 2006.201.14:01:24.34#ibcon#about to read 4, iclass 16, count 2 2006.201.14:01:24.34#ibcon#read 4, iclass 16, count 2 2006.201.14:01:24.34#ibcon#about to read 5, iclass 16, count 2 2006.201.14:01:24.34#ibcon#read 5, iclass 16, count 2 2006.201.14:01:24.34#ibcon#about to read 6, iclass 16, count 2 2006.201.14:01:24.34#ibcon#read 6, iclass 16, count 2 2006.201.14:01:24.34#ibcon#end of sib2, iclass 16, count 2 2006.201.14:01:24.34#ibcon#*after write, iclass 16, count 2 2006.201.14:01:24.34#ibcon#*before return 0, iclass 16, count 2 2006.201.14:01:24.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:24.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:24.34#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.14:01:24.34#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:24.34#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:24.46#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:24.46#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:24.46#ibcon#enter wrdev, iclass 16, count 0 2006.201.14:01:24.46#ibcon#first serial, iclass 16, count 0 2006.201.14:01:24.46#ibcon#enter sib2, iclass 16, count 0 2006.201.14:01:24.46#ibcon#flushed, iclass 16, count 0 2006.201.14:01:24.46#ibcon#about to write, iclass 16, count 0 2006.201.14:01:24.46#ibcon#wrote, iclass 16, count 0 2006.201.14:01:24.46#ibcon#about to read 3, iclass 16, count 0 2006.201.14:01:24.48#ibcon#read 3, iclass 16, count 0 2006.201.14:01:24.48#ibcon#about to read 4, iclass 16, count 0 2006.201.14:01:24.48#ibcon#read 4, iclass 16, count 0 2006.201.14:01:24.48#ibcon#about to read 5, iclass 16, count 0 2006.201.14:01:24.48#ibcon#read 5, iclass 16, count 0 2006.201.14:01:24.48#ibcon#about to read 6, iclass 16, count 0 2006.201.14:01:24.48#ibcon#read 6, iclass 16, count 0 2006.201.14:01:24.48#ibcon#end of sib2, iclass 16, count 0 2006.201.14:01:24.48#ibcon#*mode == 0, iclass 16, count 0 2006.201.14:01:24.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.14:01:24.48#ibcon#[25=USB\r\n] 2006.201.14:01:24.48#ibcon#*before write, iclass 16, count 0 2006.201.14:01:24.48#ibcon#enter sib2, iclass 16, count 0 2006.201.14:01:24.48#ibcon#flushed, iclass 16, count 0 2006.201.14:01:24.48#ibcon#about to write, iclass 16, count 0 2006.201.14:01:24.48#ibcon#wrote, iclass 16, count 0 2006.201.14:01:24.48#ibcon#about to read 3, iclass 16, count 0 2006.201.14:01:24.51#ibcon#read 3, iclass 16, count 0 2006.201.14:01:24.51#ibcon#about to read 4, iclass 16, count 0 2006.201.14:01:24.51#ibcon#read 4, iclass 16, count 0 2006.201.14:01:24.51#ibcon#about to read 5, iclass 16, count 0 2006.201.14:01:24.51#ibcon#read 5, iclass 16, count 0 2006.201.14:01:24.51#ibcon#about to read 6, iclass 16, count 0 2006.201.14:01:24.51#ibcon#read 6, iclass 16, count 0 2006.201.14:01:24.51#ibcon#end of sib2, iclass 16, count 0 2006.201.14:01:24.51#ibcon#*after write, iclass 16, count 0 2006.201.14:01:24.51#ibcon#*before return 0, iclass 16, count 0 2006.201.14:01:24.51#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:24.51#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:24.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.14:01:24.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.14:01:24.51$vck44/valo=3,564.99 2006.201.14:01:24.51#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.14:01:24.51#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.14:01:24.51#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:24.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:24.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:24.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:24.51#ibcon#enter wrdev, iclass 18, count 0 2006.201.14:01:24.51#ibcon#first serial, iclass 18, count 0 2006.201.14:01:24.51#ibcon#enter sib2, iclass 18, count 0 2006.201.14:01:24.51#ibcon#flushed, iclass 18, count 0 2006.201.14:01:24.51#ibcon#about to write, iclass 18, count 0 2006.201.14:01:24.51#ibcon#wrote, iclass 18, count 0 2006.201.14:01:24.51#ibcon#about to read 3, iclass 18, count 0 2006.201.14:01:24.53#ibcon#read 3, iclass 18, count 0 2006.201.14:01:24.53#ibcon#about to read 4, iclass 18, count 0 2006.201.14:01:24.53#ibcon#read 4, iclass 18, count 0 2006.201.14:01:24.53#ibcon#about to read 5, iclass 18, count 0 2006.201.14:01:24.53#ibcon#read 5, iclass 18, count 0 2006.201.14:01:24.53#ibcon#about to read 6, iclass 18, count 0 2006.201.14:01:24.53#ibcon#read 6, iclass 18, count 0 2006.201.14:01:24.53#ibcon#end of sib2, iclass 18, count 0 2006.201.14:01:24.53#ibcon#*mode == 0, iclass 18, count 0 2006.201.14:01:24.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.14:01:24.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:01:24.53#ibcon#*before write, iclass 18, count 0 2006.201.14:01:24.53#ibcon#enter sib2, iclass 18, count 0 2006.201.14:01:24.53#ibcon#flushed, iclass 18, count 0 2006.201.14:01:24.53#ibcon#about to write, iclass 18, count 0 2006.201.14:01:24.53#ibcon#wrote, iclass 18, count 0 2006.201.14:01:24.53#ibcon#about to read 3, iclass 18, count 0 2006.201.14:01:24.58#ibcon#read 3, iclass 18, count 0 2006.201.14:01:24.58#ibcon#about to read 4, iclass 18, count 0 2006.201.14:01:24.58#ibcon#read 4, iclass 18, count 0 2006.201.14:01:24.58#ibcon#about to read 5, iclass 18, count 0 2006.201.14:01:24.58#ibcon#read 5, iclass 18, count 0 2006.201.14:01:24.58#ibcon#about to read 6, iclass 18, count 0 2006.201.14:01:24.58#ibcon#read 6, iclass 18, count 0 2006.201.14:01:24.58#ibcon#end of sib2, iclass 18, count 0 2006.201.14:01:24.58#ibcon#*after write, iclass 18, count 0 2006.201.14:01:24.58#ibcon#*before return 0, iclass 18, count 0 2006.201.14:01:24.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:24.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:24.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.14:01:24.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.14:01:24.58$vck44/va=3,8 2006.201.14:01:24.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.14:01:24.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.14:01:24.58#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:24.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:24.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:24.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:24.63#ibcon#enter wrdev, iclass 20, count 2 2006.201.14:01:24.63#ibcon#first serial, iclass 20, count 2 2006.201.14:01:24.63#ibcon#enter sib2, iclass 20, count 2 2006.201.14:01:24.63#ibcon#flushed, iclass 20, count 2 2006.201.14:01:24.63#ibcon#about to write, iclass 20, count 2 2006.201.14:01:24.63#ibcon#wrote, iclass 20, count 2 2006.201.14:01:24.63#ibcon#about to read 3, iclass 20, count 2 2006.201.14:01:24.65#ibcon#read 3, iclass 20, count 2 2006.201.14:01:24.65#ibcon#about to read 4, iclass 20, count 2 2006.201.14:01:24.65#ibcon#read 4, iclass 20, count 2 2006.201.14:01:24.65#ibcon#about to read 5, iclass 20, count 2 2006.201.14:01:24.65#ibcon#read 5, iclass 20, count 2 2006.201.14:01:24.65#ibcon#about to read 6, iclass 20, count 2 2006.201.14:01:24.65#ibcon#read 6, iclass 20, count 2 2006.201.14:01:24.65#ibcon#end of sib2, iclass 20, count 2 2006.201.14:01:24.65#ibcon#*mode == 0, iclass 20, count 2 2006.201.14:01:24.65#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.14:01:24.65#ibcon#[25=AT03-08\r\n] 2006.201.14:01:24.65#ibcon#*before write, iclass 20, count 2 2006.201.14:01:24.65#ibcon#enter sib2, iclass 20, count 2 2006.201.14:01:24.65#ibcon#flushed, iclass 20, count 2 2006.201.14:01:24.65#ibcon#about to write, iclass 20, count 2 2006.201.14:01:24.65#ibcon#wrote, iclass 20, count 2 2006.201.14:01:24.65#ibcon#about to read 3, iclass 20, count 2 2006.201.14:01:24.68#ibcon#read 3, iclass 20, count 2 2006.201.14:01:24.68#ibcon#about to read 4, iclass 20, count 2 2006.201.14:01:24.68#ibcon#read 4, iclass 20, count 2 2006.201.14:01:24.68#ibcon#about to read 5, iclass 20, count 2 2006.201.14:01:24.68#ibcon#read 5, iclass 20, count 2 2006.201.14:01:24.68#ibcon#about to read 6, iclass 20, count 2 2006.201.14:01:24.68#ibcon#read 6, iclass 20, count 2 2006.201.14:01:24.68#ibcon#end of sib2, iclass 20, count 2 2006.201.14:01:24.68#ibcon#*after write, iclass 20, count 2 2006.201.14:01:24.68#ibcon#*before return 0, iclass 20, count 2 2006.201.14:01:24.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:24.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:24.68#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.14:01:24.68#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:24.68#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:24.80#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:24.80#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:24.80#ibcon#enter wrdev, iclass 20, count 0 2006.201.14:01:24.80#ibcon#first serial, iclass 20, count 0 2006.201.14:01:24.80#ibcon#enter sib2, iclass 20, count 0 2006.201.14:01:24.80#ibcon#flushed, iclass 20, count 0 2006.201.14:01:24.80#ibcon#about to write, iclass 20, count 0 2006.201.14:01:24.80#ibcon#wrote, iclass 20, count 0 2006.201.14:01:24.80#ibcon#about to read 3, iclass 20, count 0 2006.201.14:01:24.82#ibcon#read 3, iclass 20, count 0 2006.201.14:01:24.82#ibcon#about to read 4, iclass 20, count 0 2006.201.14:01:24.82#ibcon#read 4, iclass 20, count 0 2006.201.14:01:24.82#ibcon#about to read 5, iclass 20, count 0 2006.201.14:01:24.82#ibcon#read 5, iclass 20, count 0 2006.201.14:01:24.82#ibcon#about to read 6, iclass 20, count 0 2006.201.14:01:24.82#ibcon#read 6, iclass 20, count 0 2006.201.14:01:24.82#ibcon#end of sib2, iclass 20, count 0 2006.201.14:01:24.82#ibcon#*mode == 0, iclass 20, count 0 2006.201.14:01:24.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.14:01:24.82#ibcon#[25=USB\r\n] 2006.201.14:01:24.82#ibcon#*before write, iclass 20, count 0 2006.201.14:01:24.82#ibcon#enter sib2, iclass 20, count 0 2006.201.14:01:24.82#ibcon#flushed, iclass 20, count 0 2006.201.14:01:24.82#ibcon#about to write, iclass 20, count 0 2006.201.14:01:24.82#ibcon#wrote, iclass 20, count 0 2006.201.14:01:24.82#ibcon#about to read 3, iclass 20, count 0 2006.201.14:01:24.85#ibcon#read 3, iclass 20, count 0 2006.201.14:01:24.85#ibcon#about to read 4, iclass 20, count 0 2006.201.14:01:24.85#ibcon#read 4, iclass 20, count 0 2006.201.14:01:24.85#ibcon#about to read 5, iclass 20, count 0 2006.201.14:01:24.85#ibcon#read 5, iclass 20, count 0 2006.201.14:01:24.85#ibcon#about to read 6, iclass 20, count 0 2006.201.14:01:24.85#ibcon#read 6, iclass 20, count 0 2006.201.14:01:24.85#ibcon#end of sib2, iclass 20, count 0 2006.201.14:01:24.85#ibcon#*after write, iclass 20, count 0 2006.201.14:01:24.85#ibcon#*before return 0, iclass 20, count 0 2006.201.14:01:24.85#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:24.85#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:24.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.14:01:24.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.14:01:24.85$vck44/valo=4,624.99 2006.201.14:01:24.85#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.14:01:24.85#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.14:01:24.85#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:24.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:24.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:24.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:24.85#ibcon#enter wrdev, iclass 22, count 0 2006.201.14:01:24.85#ibcon#first serial, iclass 22, count 0 2006.201.14:01:24.85#ibcon#enter sib2, iclass 22, count 0 2006.201.14:01:24.85#ibcon#flushed, iclass 22, count 0 2006.201.14:01:24.85#ibcon#about to write, iclass 22, count 0 2006.201.14:01:24.85#ibcon#wrote, iclass 22, count 0 2006.201.14:01:24.85#ibcon#about to read 3, iclass 22, count 0 2006.201.14:01:24.87#ibcon#read 3, iclass 22, count 0 2006.201.14:01:24.87#ibcon#about to read 4, iclass 22, count 0 2006.201.14:01:24.87#ibcon#read 4, iclass 22, count 0 2006.201.14:01:24.87#ibcon#about to read 5, iclass 22, count 0 2006.201.14:01:24.87#ibcon#read 5, iclass 22, count 0 2006.201.14:01:24.87#ibcon#about to read 6, iclass 22, count 0 2006.201.14:01:24.87#ibcon#read 6, iclass 22, count 0 2006.201.14:01:24.87#ibcon#end of sib2, iclass 22, count 0 2006.201.14:01:24.87#ibcon#*mode == 0, iclass 22, count 0 2006.201.14:01:24.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.14:01:24.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:01:24.87#ibcon#*before write, iclass 22, count 0 2006.201.14:01:24.87#ibcon#enter sib2, iclass 22, count 0 2006.201.14:01:24.87#ibcon#flushed, iclass 22, count 0 2006.201.14:01:24.87#ibcon#about to write, iclass 22, count 0 2006.201.14:01:24.87#ibcon#wrote, iclass 22, count 0 2006.201.14:01:24.87#ibcon#about to read 3, iclass 22, count 0 2006.201.14:01:24.92#ibcon#read 3, iclass 22, count 0 2006.201.14:01:24.92#ibcon#about to read 4, iclass 22, count 0 2006.201.14:01:24.92#ibcon#read 4, iclass 22, count 0 2006.201.14:01:24.92#ibcon#about to read 5, iclass 22, count 0 2006.201.14:01:24.92#ibcon#read 5, iclass 22, count 0 2006.201.14:01:24.92#ibcon#about to read 6, iclass 22, count 0 2006.201.14:01:24.92#ibcon#read 6, iclass 22, count 0 2006.201.14:01:24.92#ibcon#end of sib2, iclass 22, count 0 2006.201.14:01:24.92#ibcon#*after write, iclass 22, count 0 2006.201.14:01:24.92#ibcon#*before return 0, iclass 22, count 0 2006.201.14:01:24.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:24.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:24.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.14:01:24.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.14:01:24.92$vck44/va=4,7 2006.201.14:01:24.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.14:01:24.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.14:01:24.92#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:24.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:24.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:24.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:24.97#ibcon#enter wrdev, iclass 24, count 2 2006.201.14:01:24.97#ibcon#first serial, iclass 24, count 2 2006.201.14:01:24.97#ibcon#enter sib2, iclass 24, count 2 2006.201.14:01:24.97#ibcon#flushed, iclass 24, count 2 2006.201.14:01:24.97#ibcon#about to write, iclass 24, count 2 2006.201.14:01:24.97#ibcon#wrote, iclass 24, count 2 2006.201.14:01:24.97#ibcon#about to read 3, iclass 24, count 2 2006.201.14:01:24.99#ibcon#read 3, iclass 24, count 2 2006.201.14:01:24.99#ibcon#about to read 4, iclass 24, count 2 2006.201.14:01:24.99#ibcon#read 4, iclass 24, count 2 2006.201.14:01:24.99#ibcon#about to read 5, iclass 24, count 2 2006.201.14:01:24.99#ibcon#read 5, iclass 24, count 2 2006.201.14:01:24.99#ibcon#about to read 6, iclass 24, count 2 2006.201.14:01:24.99#ibcon#read 6, iclass 24, count 2 2006.201.14:01:24.99#ibcon#end of sib2, iclass 24, count 2 2006.201.14:01:24.99#ibcon#*mode == 0, iclass 24, count 2 2006.201.14:01:24.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.14:01:24.99#ibcon#[25=AT04-07\r\n] 2006.201.14:01:24.99#ibcon#*before write, iclass 24, count 2 2006.201.14:01:24.99#ibcon#enter sib2, iclass 24, count 2 2006.201.14:01:24.99#ibcon#flushed, iclass 24, count 2 2006.201.14:01:24.99#ibcon#about to write, iclass 24, count 2 2006.201.14:01:24.99#ibcon#wrote, iclass 24, count 2 2006.201.14:01:24.99#ibcon#about to read 3, iclass 24, count 2 2006.201.14:01:25.02#ibcon#read 3, iclass 24, count 2 2006.201.14:01:25.02#ibcon#about to read 4, iclass 24, count 2 2006.201.14:01:25.02#ibcon#read 4, iclass 24, count 2 2006.201.14:01:25.02#ibcon#about to read 5, iclass 24, count 2 2006.201.14:01:25.02#ibcon#read 5, iclass 24, count 2 2006.201.14:01:25.02#ibcon#about to read 6, iclass 24, count 2 2006.201.14:01:25.02#ibcon#read 6, iclass 24, count 2 2006.201.14:01:25.02#ibcon#end of sib2, iclass 24, count 2 2006.201.14:01:25.02#ibcon#*after write, iclass 24, count 2 2006.201.14:01:25.02#ibcon#*before return 0, iclass 24, count 2 2006.201.14:01:25.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:25.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:25.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.14:01:25.02#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:25.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:25.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:25.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:25.14#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:01:25.14#ibcon#first serial, iclass 24, count 0 2006.201.14:01:25.14#ibcon#enter sib2, iclass 24, count 0 2006.201.14:01:25.14#ibcon#flushed, iclass 24, count 0 2006.201.14:01:25.14#ibcon#about to write, iclass 24, count 0 2006.201.14:01:25.14#ibcon#wrote, iclass 24, count 0 2006.201.14:01:25.14#ibcon#about to read 3, iclass 24, count 0 2006.201.14:01:25.16#ibcon#read 3, iclass 24, count 0 2006.201.14:01:25.16#ibcon#about to read 4, iclass 24, count 0 2006.201.14:01:25.16#ibcon#read 4, iclass 24, count 0 2006.201.14:01:25.16#ibcon#about to read 5, iclass 24, count 0 2006.201.14:01:25.16#ibcon#read 5, iclass 24, count 0 2006.201.14:01:25.16#ibcon#about to read 6, iclass 24, count 0 2006.201.14:01:25.16#ibcon#read 6, iclass 24, count 0 2006.201.14:01:25.16#ibcon#end of sib2, iclass 24, count 0 2006.201.14:01:25.16#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:01:25.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:01:25.16#ibcon#[25=USB\r\n] 2006.201.14:01:25.16#ibcon#*before write, iclass 24, count 0 2006.201.14:01:25.16#ibcon#enter sib2, iclass 24, count 0 2006.201.14:01:25.16#ibcon#flushed, iclass 24, count 0 2006.201.14:01:25.16#ibcon#about to write, iclass 24, count 0 2006.201.14:01:25.16#ibcon#wrote, iclass 24, count 0 2006.201.14:01:25.16#ibcon#about to read 3, iclass 24, count 0 2006.201.14:01:25.19#ibcon#read 3, iclass 24, count 0 2006.201.14:01:25.19#ibcon#about to read 4, iclass 24, count 0 2006.201.14:01:25.19#ibcon#read 4, iclass 24, count 0 2006.201.14:01:25.19#ibcon#about to read 5, iclass 24, count 0 2006.201.14:01:25.19#ibcon#read 5, iclass 24, count 0 2006.201.14:01:25.19#ibcon#about to read 6, iclass 24, count 0 2006.201.14:01:25.19#ibcon#read 6, iclass 24, count 0 2006.201.14:01:25.19#ibcon#end of sib2, iclass 24, count 0 2006.201.14:01:25.19#ibcon#*after write, iclass 24, count 0 2006.201.14:01:25.19#ibcon#*before return 0, iclass 24, count 0 2006.201.14:01:25.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:25.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:25.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:01:25.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:01:25.19$vck44/valo=5,734.99 2006.201.14:01:25.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.14:01:25.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.14:01:25.19#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:25.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:25.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:25.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:25.19#ibcon#enter wrdev, iclass 26, count 0 2006.201.14:01:25.19#ibcon#first serial, iclass 26, count 0 2006.201.14:01:25.19#ibcon#enter sib2, iclass 26, count 0 2006.201.14:01:25.19#ibcon#flushed, iclass 26, count 0 2006.201.14:01:25.19#ibcon#about to write, iclass 26, count 0 2006.201.14:01:25.19#ibcon#wrote, iclass 26, count 0 2006.201.14:01:25.19#ibcon#about to read 3, iclass 26, count 0 2006.201.14:01:25.21#ibcon#read 3, iclass 26, count 0 2006.201.14:01:25.21#ibcon#about to read 4, iclass 26, count 0 2006.201.14:01:25.21#ibcon#read 4, iclass 26, count 0 2006.201.14:01:25.21#ibcon#about to read 5, iclass 26, count 0 2006.201.14:01:25.21#ibcon#read 5, iclass 26, count 0 2006.201.14:01:25.21#ibcon#about to read 6, iclass 26, count 0 2006.201.14:01:25.21#ibcon#read 6, iclass 26, count 0 2006.201.14:01:25.21#ibcon#end of sib2, iclass 26, count 0 2006.201.14:01:25.21#ibcon#*mode == 0, iclass 26, count 0 2006.201.14:01:25.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.14:01:25.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:01:25.21#ibcon#*before write, iclass 26, count 0 2006.201.14:01:25.21#ibcon#enter sib2, iclass 26, count 0 2006.201.14:01:25.21#ibcon#flushed, iclass 26, count 0 2006.201.14:01:25.21#ibcon#about to write, iclass 26, count 0 2006.201.14:01:25.21#ibcon#wrote, iclass 26, count 0 2006.201.14:01:25.21#ibcon#about to read 3, iclass 26, count 0 2006.201.14:01:25.25#ibcon#read 3, iclass 26, count 0 2006.201.14:01:25.25#ibcon#about to read 4, iclass 26, count 0 2006.201.14:01:25.25#ibcon#read 4, iclass 26, count 0 2006.201.14:01:25.25#ibcon#about to read 5, iclass 26, count 0 2006.201.14:01:25.25#ibcon#read 5, iclass 26, count 0 2006.201.14:01:25.25#ibcon#about to read 6, iclass 26, count 0 2006.201.14:01:25.25#ibcon#read 6, iclass 26, count 0 2006.201.14:01:25.25#ibcon#end of sib2, iclass 26, count 0 2006.201.14:01:25.25#ibcon#*after write, iclass 26, count 0 2006.201.14:01:25.25#ibcon#*before return 0, iclass 26, count 0 2006.201.14:01:25.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:25.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:25.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.14:01:25.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.14:01:25.25$vck44/va=5,4 2006.201.14:01:25.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.14:01:25.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.14:01:25.25#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:25.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:25.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:25.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:25.31#ibcon#enter wrdev, iclass 28, count 2 2006.201.14:01:25.31#ibcon#first serial, iclass 28, count 2 2006.201.14:01:25.31#ibcon#enter sib2, iclass 28, count 2 2006.201.14:01:25.31#ibcon#flushed, iclass 28, count 2 2006.201.14:01:25.31#ibcon#about to write, iclass 28, count 2 2006.201.14:01:25.31#ibcon#wrote, iclass 28, count 2 2006.201.14:01:25.31#ibcon#about to read 3, iclass 28, count 2 2006.201.14:01:25.33#ibcon#read 3, iclass 28, count 2 2006.201.14:01:25.33#ibcon#about to read 4, iclass 28, count 2 2006.201.14:01:25.33#ibcon#read 4, iclass 28, count 2 2006.201.14:01:25.33#ibcon#about to read 5, iclass 28, count 2 2006.201.14:01:25.33#ibcon#read 5, iclass 28, count 2 2006.201.14:01:25.33#ibcon#about to read 6, iclass 28, count 2 2006.201.14:01:25.33#ibcon#read 6, iclass 28, count 2 2006.201.14:01:25.33#ibcon#end of sib2, iclass 28, count 2 2006.201.14:01:25.33#ibcon#*mode == 0, iclass 28, count 2 2006.201.14:01:25.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.14:01:25.33#ibcon#[25=AT05-04\r\n] 2006.201.14:01:25.33#ibcon#*before write, iclass 28, count 2 2006.201.14:01:25.33#ibcon#enter sib2, iclass 28, count 2 2006.201.14:01:25.33#ibcon#flushed, iclass 28, count 2 2006.201.14:01:25.33#ibcon#about to write, iclass 28, count 2 2006.201.14:01:25.33#ibcon#wrote, iclass 28, count 2 2006.201.14:01:25.33#ibcon#about to read 3, iclass 28, count 2 2006.201.14:01:25.36#ibcon#read 3, iclass 28, count 2 2006.201.14:01:25.36#ibcon#about to read 4, iclass 28, count 2 2006.201.14:01:25.36#ibcon#read 4, iclass 28, count 2 2006.201.14:01:25.36#ibcon#about to read 5, iclass 28, count 2 2006.201.14:01:25.36#ibcon#read 5, iclass 28, count 2 2006.201.14:01:25.36#ibcon#about to read 6, iclass 28, count 2 2006.201.14:01:25.36#ibcon#read 6, iclass 28, count 2 2006.201.14:01:25.36#ibcon#end of sib2, iclass 28, count 2 2006.201.14:01:25.36#ibcon#*after write, iclass 28, count 2 2006.201.14:01:25.36#ibcon#*before return 0, iclass 28, count 2 2006.201.14:01:25.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:25.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:25.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.14:01:25.36#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:25.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:25.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:25.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:25.48#ibcon#enter wrdev, iclass 28, count 0 2006.201.14:01:25.48#ibcon#first serial, iclass 28, count 0 2006.201.14:01:25.48#ibcon#enter sib2, iclass 28, count 0 2006.201.14:01:25.48#ibcon#flushed, iclass 28, count 0 2006.201.14:01:25.48#ibcon#about to write, iclass 28, count 0 2006.201.14:01:25.48#ibcon#wrote, iclass 28, count 0 2006.201.14:01:25.48#ibcon#about to read 3, iclass 28, count 0 2006.201.14:01:25.50#ibcon#read 3, iclass 28, count 0 2006.201.14:01:25.50#ibcon#about to read 4, iclass 28, count 0 2006.201.14:01:25.50#ibcon#read 4, iclass 28, count 0 2006.201.14:01:25.50#ibcon#about to read 5, iclass 28, count 0 2006.201.14:01:25.50#ibcon#read 5, iclass 28, count 0 2006.201.14:01:25.50#ibcon#about to read 6, iclass 28, count 0 2006.201.14:01:25.50#ibcon#read 6, iclass 28, count 0 2006.201.14:01:25.50#ibcon#end of sib2, iclass 28, count 0 2006.201.14:01:25.50#ibcon#*mode == 0, iclass 28, count 0 2006.201.14:01:25.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.14:01:25.50#ibcon#[25=USB\r\n] 2006.201.14:01:25.50#ibcon#*before write, iclass 28, count 0 2006.201.14:01:25.50#ibcon#enter sib2, iclass 28, count 0 2006.201.14:01:25.50#ibcon#flushed, iclass 28, count 0 2006.201.14:01:25.50#ibcon#about to write, iclass 28, count 0 2006.201.14:01:25.50#ibcon#wrote, iclass 28, count 0 2006.201.14:01:25.50#ibcon#about to read 3, iclass 28, count 0 2006.201.14:01:25.53#ibcon#read 3, iclass 28, count 0 2006.201.14:01:25.53#ibcon#about to read 4, iclass 28, count 0 2006.201.14:01:25.53#ibcon#read 4, iclass 28, count 0 2006.201.14:01:25.53#ibcon#about to read 5, iclass 28, count 0 2006.201.14:01:25.53#ibcon#read 5, iclass 28, count 0 2006.201.14:01:25.53#ibcon#about to read 6, iclass 28, count 0 2006.201.14:01:25.53#ibcon#read 6, iclass 28, count 0 2006.201.14:01:25.53#ibcon#end of sib2, iclass 28, count 0 2006.201.14:01:25.53#ibcon#*after write, iclass 28, count 0 2006.201.14:01:25.53#ibcon#*before return 0, iclass 28, count 0 2006.201.14:01:25.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:25.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:25.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.14:01:25.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.14:01:25.53$vck44/valo=6,814.99 2006.201.14:01:25.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.14:01:25.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.14:01:25.53#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:25.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:25.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:25.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:25.53#ibcon#enter wrdev, iclass 30, count 0 2006.201.14:01:25.53#ibcon#first serial, iclass 30, count 0 2006.201.14:01:25.53#ibcon#enter sib2, iclass 30, count 0 2006.201.14:01:25.53#ibcon#flushed, iclass 30, count 0 2006.201.14:01:25.53#ibcon#about to write, iclass 30, count 0 2006.201.14:01:25.53#ibcon#wrote, iclass 30, count 0 2006.201.14:01:25.53#ibcon#about to read 3, iclass 30, count 0 2006.201.14:01:25.55#ibcon#read 3, iclass 30, count 0 2006.201.14:01:25.55#ibcon#about to read 4, iclass 30, count 0 2006.201.14:01:25.55#ibcon#read 4, iclass 30, count 0 2006.201.14:01:25.55#ibcon#about to read 5, iclass 30, count 0 2006.201.14:01:25.55#ibcon#read 5, iclass 30, count 0 2006.201.14:01:25.55#ibcon#about to read 6, iclass 30, count 0 2006.201.14:01:25.55#ibcon#read 6, iclass 30, count 0 2006.201.14:01:25.55#ibcon#end of sib2, iclass 30, count 0 2006.201.14:01:25.55#ibcon#*mode == 0, iclass 30, count 0 2006.201.14:01:25.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.14:01:25.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:01:25.55#ibcon#*before write, iclass 30, count 0 2006.201.14:01:25.55#ibcon#enter sib2, iclass 30, count 0 2006.201.14:01:25.55#ibcon#flushed, iclass 30, count 0 2006.201.14:01:25.55#ibcon#about to write, iclass 30, count 0 2006.201.14:01:25.55#ibcon#wrote, iclass 30, count 0 2006.201.14:01:25.55#ibcon#about to read 3, iclass 30, count 0 2006.201.14:01:25.60#ibcon#read 3, iclass 30, count 0 2006.201.14:01:25.60#ibcon#about to read 4, iclass 30, count 0 2006.201.14:01:25.60#ibcon#read 4, iclass 30, count 0 2006.201.14:01:25.60#ibcon#about to read 5, iclass 30, count 0 2006.201.14:01:25.60#ibcon#read 5, iclass 30, count 0 2006.201.14:01:25.60#ibcon#about to read 6, iclass 30, count 0 2006.201.14:01:25.60#ibcon#read 6, iclass 30, count 0 2006.201.14:01:25.60#ibcon#end of sib2, iclass 30, count 0 2006.201.14:01:25.60#ibcon#*after write, iclass 30, count 0 2006.201.14:01:25.60#ibcon#*before return 0, iclass 30, count 0 2006.201.14:01:25.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:25.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:25.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.14:01:25.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.14:01:25.60$vck44/va=6,5 2006.201.14:01:25.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.14:01:25.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.14:01:25.60#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:25.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:25.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:25.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:25.65#ibcon#enter wrdev, iclass 32, count 2 2006.201.14:01:25.65#ibcon#first serial, iclass 32, count 2 2006.201.14:01:25.65#ibcon#enter sib2, iclass 32, count 2 2006.201.14:01:25.65#ibcon#flushed, iclass 32, count 2 2006.201.14:01:25.65#ibcon#about to write, iclass 32, count 2 2006.201.14:01:25.65#ibcon#wrote, iclass 32, count 2 2006.201.14:01:25.65#ibcon#about to read 3, iclass 32, count 2 2006.201.14:01:25.67#ibcon#read 3, iclass 32, count 2 2006.201.14:01:25.67#ibcon#about to read 4, iclass 32, count 2 2006.201.14:01:25.67#ibcon#read 4, iclass 32, count 2 2006.201.14:01:25.67#ibcon#about to read 5, iclass 32, count 2 2006.201.14:01:25.67#ibcon#read 5, iclass 32, count 2 2006.201.14:01:25.67#ibcon#about to read 6, iclass 32, count 2 2006.201.14:01:25.67#ibcon#read 6, iclass 32, count 2 2006.201.14:01:25.67#ibcon#end of sib2, iclass 32, count 2 2006.201.14:01:25.67#ibcon#*mode == 0, iclass 32, count 2 2006.201.14:01:25.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.14:01:25.67#ibcon#[25=AT06-05\r\n] 2006.201.14:01:25.67#ibcon#*before write, iclass 32, count 2 2006.201.14:01:25.67#ibcon#enter sib2, iclass 32, count 2 2006.201.14:01:25.67#ibcon#flushed, iclass 32, count 2 2006.201.14:01:25.67#ibcon#about to write, iclass 32, count 2 2006.201.14:01:25.67#ibcon#wrote, iclass 32, count 2 2006.201.14:01:25.67#ibcon#about to read 3, iclass 32, count 2 2006.201.14:01:25.70#ibcon#read 3, iclass 32, count 2 2006.201.14:01:25.70#ibcon#about to read 4, iclass 32, count 2 2006.201.14:01:25.70#ibcon#read 4, iclass 32, count 2 2006.201.14:01:25.70#ibcon#about to read 5, iclass 32, count 2 2006.201.14:01:25.70#ibcon#read 5, iclass 32, count 2 2006.201.14:01:25.70#ibcon#about to read 6, iclass 32, count 2 2006.201.14:01:25.70#ibcon#read 6, iclass 32, count 2 2006.201.14:01:25.70#ibcon#end of sib2, iclass 32, count 2 2006.201.14:01:25.70#ibcon#*after write, iclass 32, count 2 2006.201.14:01:25.70#ibcon#*before return 0, iclass 32, count 2 2006.201.14:01:25.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:25.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:25.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.14:01:25.70#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:25.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:25.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:25.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:25.82#ibcon#enter wrdev, iclass 32, count 0 2006.201.14:01:25.82#ibcon#first serial, iclass 32, count 0 2006.201.14:01:25.82#ibcon#enter sib2, iclass 32, count 0 2006.201.14:01:25.82#ibcon#flushed, iclass 32, count 0 2006.201.14:01:25.82#ibcon#about to write, iclass 32, count 0 2006.201.14:01:25.82#ibcon#wrote, iclass 32, count 0 2006.201.14:01:25.82#ibcon#about to read 3, iclass 32, count 0 2006.201.14:01:25.84#ibcon#read 3, iclass 32, count 0 2006.201.14:01:25.84#ibcon#about to read 4, iclass 32, count 0 2006.201.14:01:25.84#ibcon#read 4, iclass 32, count 0 2006.201.14:01:25.84#ibcon#about to read 5, iclass 32, count 0 2006.201.14:01:25.84#ibcon#read 5, iclass 32, count 0 2006.201.14:01:25.84#ibcon#about to read 6, iclass 32, count 0 2006.201.14:01:25.84#ibcon#read 6, iclass 32, count 0 2006.201.14:01:25.84#ibcon#end of sib2, iclass 32, count 0 2006.201.14:01:25.84#ibcon#*mode == 0, iclass 32, count 0 2006.201.14:01:25.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.14:01:25.84#ibcon#[25=USB\r\n] 2006.201.14:01:25.84#ibcon#*before write, iclass 32, count 0 2006.201.14:01:25.84#ibcon#enter sib2, iclass 32, count 0 2006.201.14:01:25.84#ibcon#flushed, iclass 32, count 0 2006.201.14:01:25.84#ibcon#about to write, iclass 32, count 0 2006.201.14:01:25.84#ibcon#wrote, iclass 32, count 0 2006.201.14:01:25.84#ibcon#about to read 3, iclass 32, count 0 2006.201.14:01:25.87#ibcon#read 3, iclass 32, count 0 2006.201.14:01:25.87#ibcon#about to read 4, iclass 32, count 0 2006.201.14:01:25.87#ibcon#read 4, iclass 32, count 0 2006.201.14:01:25.87#ibcon#about to read 5, iclass 32, count 0 2006.201.14:01:25.87#ibcon#read 5, iclass 32, count 0 2006.201.14:01:25.87#ibcon#about to read 6, iclass 32, count 0 2006.201.14:01:25.87#ibcon#read 6, iclass 32, count 0 2006.201.14:01:25.87#ibcon#end of sib2, iclass 32, count 0 2006.201.14:01:25.87#ibcon#*after write, iclass 32, count 0 2006.201.14:01:25.87#ibcon#*before return 0, iclass 32, count 0 2006.201.14:01:25.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:25.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:25.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.14:01:25.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.14:01:25.87$vck44/valo=7,864.99 2006.201.14:01:25.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.14:01:25.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.14:01:25.87#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:25.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:25.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:25.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:25.87#ibcon#enter wrdev, iclass 34, count 0 2006.201.14:01:25.87#ibcon#first serial, iclass 34, count 0 2006.201.14:01:25.87#ibcon#enter sib2, iclass 34, count 0 2006.201.14:01:25.87#ibcon#flushed, iclass 34, count 0 2006.201.14:01:25.87#ibcon#about to write, iclass 34, count 0 2006.201.14:01:25.87#ibcon#wrote, iclass 34, count 0 2006.201.14:01:25.87#ibcon#about to read 3, iclass 34, count 0 2006.201.14:01:25.89#ibcon#read 3, iclass 34, count 0 2006.201.14:01:25.89#ibcon#about to read 4, iclass 34, count 0 2006.201.14:01:25.89#ibcon#read 4, iclass 34, count 0 2006.201.14:01:25.89#ibcon#about to read 5, iclass 34, count 0 2006.201.14:01:25.89#ibcon#read 5, iclass 34, count 0 2006.201.14:01:25.89#ibcon#about to read 6, iclass 34, count 0 2006.201.14:01:25.89#ibcon#read 6, iclass 34, count 0 2006.201.14:01:25.89#ibcon#end of sib2, iclass 34, count 0 2006.201.14:01:25.89#ibcon#*mode == 0, iclass 34, count 0 2006.201.14:01:25.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.14:01:25.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:01:25.89#ibcon#*before write, iclass 34, count 0 2006.201.14:01:25.89#ibcon#enter sib2, iclass 34, count 0 2006.201.14:01:25.89#ibcon#flushed, iclass 34, count 0 2006.201.14:01:25.89#ibcon#about to write, iclass 34, count 0 2006.201.14:01:25.89#ibcon#wrote, iclass 34, count 0 2006.201.14:01:25.89#ibcon#about to read 3, iclass 34, count 0 2006.201.14:01:25.94#ibcon#read 3, iclass 34, count 0 2006.201.14:01:25.94#ibcon#about to read 4, iclass 34, count 0 2006.201.14:01:25.94#ibcon#read 4, iclass 34, count 0 2006.201.14:01:25.94#ibcon#about to read 5, iclass 34, count 0 2006.201.14:01:25.94#ibcon#read 5, iclass 34, count 0 2006.201.14:01:25.94#ibcon#about to read 6, iclass 34, count 0 2006.201.14:01:25.94#ibcon#read 6, iclass 34, count 0 2006.201.14:01:25.94#ibcon#end of sib2, iclass 34, count 0 2006.201.14:01:25.94#ibcon#*after write, iclass 34, count 0 2006.201.14:01:25.94#ibcon#*before return 0, iclass 34, count 0 2006.201.14:01:25.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:25.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:25.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.14:01:25.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.14:01:25.94$vck44/va=7,5 2006.201.14:01:25.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.14:01:25.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.14:01:25.94#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:25.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:25.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:25.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:25.99#ibcon#enter wrdev, iclass 36, count 2 2006.201.14:01:25.99#ibcon#first serial, iclass 36, count 2 2006.201.14:01:25.99#ibcon#enter sib2, iclass 36, count 2 2006.201.14:01:25.99#ibcon#flushed, iclass 36, count 2 2006.201.14:01:25.99#ibcon#about to write, iclass 36, count 2 2006.201.14:01:25.99#ibcon#wrote, iclass 36, count 2 2006.201.14:01:25.99#ibcon#about to read 3, iclass 36, count 2 2006.201.14:01:26.01#ibcon#read 3, iclass 36, count 2 2006.201.14:01:26.01#ibcon#about to read 4, iclass 36, count 2 2006.201.14:01:26.01#ibcon#read 4, iclass 36, count 2 2006.201.14:01:26.01#ibcon#about to read 5, iclass 36, count 2 2006.201.14:01:26.01#ibcon#read 5, iclass 36, count 2 2006.201.14:01:26.01#ibcon#about to read 6, iclass 36, count 2 2006.201.14:01:26.01#ibcon#read 6, iclass 36, count 2 2006.201.14:01:26.01#ibcon#end of sib2, iclass 36, count 2 2006.201.14:01:26.01#ibcon#*mode == 0, iclass 36, count 2 2006.201.14:01:26.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.14:01:26.01#ibcon#[25=AT07-05\r\n] 2006.201.14:01:26.01#ibcon#*before write, iclass 36, count 2 2006.201.14:01:26.01#ibcon#enter sib2, iclass 36, count 2 2006.201.14:01:26.01#ibcon#flushed, iclass 36, count 2 2006.201.14:01:26.01#ibcon#about to write, iclass 36, count 2 2006.201.14:01:26.01#ibcon#wrote, iclass 36, count 2 2006.201.14:01:26.01#ibcon#about to read 3, iclass 36, count 2 2006.201.14:01:26.04#ibcon#read 3, iclass 36, count 2 2006.201.14:01:26.04#ibcon#about to read 4, iclass 36, count 2 2006.201.14:01:26.04#ibcon#read 4, iclass 36, count 2 2006.201.14:01:26.04#ibcon#about to read 5, iclass 36, count 2 2006.201.14:01:26.04#ibcon#read 5, iclass 36, count 2 2006.201.14:01:26.04#ibcon#about to read 6, iclass 36, count 2 2006.201.14:01:26.04#ibcon#read 6, iclass 36, count 2 2006.201.14:01:26.04#ibcon#end of sib2, iclass 36, count 2 2006.201.14:01:26.04#ibcon#*after write, iclass 36, count 2 2006.201.14:01:26.04#ibcon#*before return 0, iclass 36, count 2 2006.201.14:01:26.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:26.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:26.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.14:01:26.04#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:26.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:26.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:26.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:26.16#ibcon#enter wrdev, iclass 36, count 0 2006.201.14:01:26.16#ibcon#first serial, iclass 36, count 0 2006.201.14:01:26.16#ibcon#enter sib2, iclass 36, count 0 2006.201.14:01:26.16#ibcon#flushed, iclass 36, count 0 2006.201.14:01:26.16#ibcon#about to write, iclass 36, count 0 2006.201.14:01:26.16#ibcon#wrote, iclass 36, count 0 2006.201.14:01:26.16#ibcon#about to read 3, iclass 36, count 0 2006.201.14:01:26.18#ibcon#read 3, iclass 36, count 0 2006.201.14:01:26.18#ibcon#about to read 4, iclass 36, count 0 2006.201.14:01:26.18#ibcon#read 4, iclass 36, count 0 2006.201.14:01:26.18#ibcon#about to read 5, iclass 36, count 0 2006.201.14:01:26.18#ibcon#read 5, iclass 36, count 0 2006.201.14:01:26.18#ibcon#about to read 6, iclass 36, count 0 2006.201.14:01:26.18#ibcon#read 6, iclass 36, count 0 2006.201.14:01:26.18#ibcon#end of sib2, iclass 36, count 0 2006.201.14:01:26.18#ibcon#*mode == 0, iclass 36, count 0 2006.201.14:01:26.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.14:01:26.18#ibcon#[25=USB\r\n] 2006.201.14:01:26.18#ibcon#*before write, iclass 36, count 0 2006.201.14:01:26.18#ibcon#enter sib2, iclass 36, count 0 2006.201.14:01:26.18#ibcon#flushed, iclass 36, count 0 2006.201.14:01:26.18#ibcon#about to write, iclass 36, count 0 2006.201.14:01:26.18#ibcon#wrote, iclass 36, count 0 2006.201.14:01:26.18#ibcon#about to read 3, iclass 36, count 0 2006.201.14:01:26.21#ibcon#read 3, iclass 36, count 0 2006.201.14:01:26.21#ibcon#about to read 4, iclass 36, count 0 2006.201.14:01:26.21#ibcon#read 4, iclass 36, count 0 2006.201.14:01:26.21#ibcon#about to read 5, iclass 36, count 0 2006.201.14:01:26.21#ibcon#read 5, iclass 36, count 0 2006.201.14:01:26.21#ibcon#about to read 6, iclass 36, count 0 2006.201.14:01:26.21#ibcon#read 6, iclass 36, count 0 2006.201.14:01:26.21#ibcon#end of sib2, iclass 36, count 0 2006.201.14:01:26.21#ibcon#*after write, iclass 36, count 0 2006.201.14:01:26.21#ibcon#*before return 0, iclass 36, count 0 2006.201.14:01:26.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:26.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:26.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.14:01:26.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.14:01:26.21$vck44/valo=8,884.99 2006.201.14:01:26.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.14:01:26.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.14:01:26.21#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:26.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:26.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:26.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:26.21#ibcon#enter wrdev, iclass 38, count 0 2006.201.14:01:26.21#ibcon#first serial, iclass 38, count 0 2006.201.14:01:26.21#ibcon#enter sib2, iclass 38, count 0 2006.201.14:01:26.21#ibcon#flushed, iclass 38, count 0 2006.201.14:01:26.21#ibcon#about to write, iclass 38, count 0 2006.201.14:01:26.21#ibcon#wrote, iclass 38, count 0 2006.201.14:01:26.21#ibcon#about to read 3, iclass 38, count 0 2006.201.14:01:26.23#ibcon#read 3, iclass 38, count 0 2006.201.14:01:26.23#ibcon#about to read 4, iclass 38, count 0 2006.201.14:01:26.23#ibcon#read 4, iclass 38, count 0 2006.201.14:01:26.23#ibcon#about to read 5, iclass 38, count 0 2006.201.14:01:26.23#ibcon#read 5, iclass 38, count 0 2006.201.14:01:26.23#ibcon#about to read 6, iclass 38, count 0 2006.201.14:01:26.23#ibcon#read 6, iclass 38, count 0 2006.201.14:01:26.23#ibcon#end of sib2, iclass 38, count 0 2006.201.14:01:26.23#ibcon#*mode == 0, iclass 38, count 0 2006.201.14:01:26.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.14:01:26.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:01:26.23#ibcon#*before write, iclass 38, count 0 2006.201.14:01:26.23#ibcon#enter sib2, iclass 38, count 0 2006.201.14:01:26.23#ibcon#flushed, iclass 38, count 0 2006.201.14:01:26.23#ibcon#about to write, iclass 38, count 0 2006.201.14:01:26.23#ibcon#wrote, iclass 38, count 0 2006.201.14:01:26.23#ibcon#about to read 3, iclass 38, count 0 2006.201.14:01:26.27#ibcon#read 3, iclass 38, count 0 2006.201.14:01:26.27#ibcon#about to read 4, iclass 38, count 0 2006.201.14:01:26.27#ibcon#read 4, iclass 38, count 0 2006.201.14:01:26.27#ibcon#about to read 5, iclass 38, count 0 2006.201.14:01:26.27#ibcon#read 5, iclass 38, count 0 2006.201.14:01:26.27#ibcon#about to read 6, iclass 38, count 0 2006.201.14:01:26.27#ibcon#read 6, iclass 38, count 0 2006.201.14:01:26.27#ibcon#end of sib2, iclass 38, count 0 2006.201.14:01:26.27#ibcon#*after write, iclass 38, count 0 2006.201.14:01:26.27#ibcon#*before return 0, iclass 38, count 0 2006.201.14:01:26.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:26.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:26.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.14:01:26.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.14:01:26.27$vck44/va=8,4 2006.201.14:01:26.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.14:01:26.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.14:01:26.27#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:26.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:01:26.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:01:26.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:01:26.33#ibcon#enter wrdev, iclass 40, count 2 2006.201.14:01:26.33#ibcon#first serial, iclass 40, count 2 2006.201.14:01:26.33#ibcon#enter sib2, iclass 40, count 2 2006.201.14:01:26.33#ibcon#flushed, iclass 40, count 2 2006.201.14:01:26.33#ibcon#about to write, iclass 40, count 2 2006.201.14:01:26.33#ibcon#wrote, iclass 40, count 2 2006.201.14:01:26.33#ibcon#about to read 3, iclass 40, count 2 2006.201.14:01:26.35#ibcon#read 3, iclass 40, count 2 2006.201.14:01:26.35#ibcon#about to read 4, iclass 40, count 2 2006.201.14:01:26.35#ibcon#read 4, iclass 40, count 2 2006.201.14:01:26.35#ibcon#about to read 5, iclass 40, count 2 2006.201.14:01:26.35#ibcon#read 5, iclass 40, count 2 2006.201.14:01:26.35#ibcon#about to read 6, iclass 40, count 2 2006.201.14:01:26.35#ibcon#read 6, iclass 40, count 2 2006.201.14:01:26.35#ibcon#end of sib2, iclass 40, count 2 2006.201.14:01:26.35#ibcon#*mode == 0, iclass 40, count 2 2006.201.14:01:26.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.14:01:26.35#ibcon#[25=AT08-04\r\n] 2006.201.14:01:26.35#ibcon#*before write, iclass 40, count 2 2006.201.14:01:26.35#ibcon#enter sib2, iclass 40, count 2 2006.201.14:01:26.35#ibcon#flushed, iclass 40, count 2 2006.201.14:01:26.35#ibcon#about to write, iclass 40, count 2 2006.201.14:01:26.35#ibcon#wrote, iclass 40, count 2 2006.201.14:01:26.35#ibcon#about to read 3, iclass 40, count 2 2006.201.14:01:26.38#ibcon#read 3, iclass 40, count 2 2006.201.14:01:26.38#ibcon#about to read 4, iclass 40, count 2 2006.201.14:01:26.38#ibcon#read 4, iclass 40, count 2 2006.201.14:01:26.38#ibcon#about to read 5, iclass 40, count 2 2006.201.14:01:26.38#ibcon#read 5, iclass 40, count 2 2006.201.14:01:26.38#ibcon#about to read 6, iclass 40, count 2 2006.201.14:01:26.38#ibcon#read 6, iclass 40, count 2 2006.201.14:01:26.38#ibcon#end of sib2, iclass 40, count 2 2006.201.14:01:26.38#ibcon#*after write, iclass 40, count 2 2006.201.14:01:26.38#ibcon#*before return 0, iclass 40, count 2 2006.201.14:01:26.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:01:26.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:01:26.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.14:01:26.38#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:26.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:01:26.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:01:26.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:01:26.50#ibcon#enter wrdev, iclass 40, count 0 2006.201.14:01:26.50#ibcon#first serial, iclass 40, count 0 2006.201.14:01:26.50#ibcon#enter sib2, iclass 40, count 0 2006.201.14:01:26.50#ibcon#flushed, iclass 40, count 0 2006.201.14:01:26.50#ibcon#about to write, iclass 40, count 0 2006.201.14:01:26.50#ibcon#wrote, iclass 40, count 0 2006.201.14:01:26.50#ibcon#about to read 3, iclass 40, count 0 2006.201.14:01:26.52#ibcon#read 3, iclass 40, count 0 2006.201.14:01:26.52#ibcon#about to read 4, iclass 40, count 0 2006.201.14:01:26.52#ibcon#read 4, iclass 40, count 0 2006.201.14:01:26.52#ibcon#about to read 5, iclass 40, count 0 2006.201.14:01:26.52#ibcon#read 5, iclass 40, count 0 2006.201.14:01:26.52#ibcon#about to read 6, iclass 40, count 0 2006.201.14:01:26.52#ibcon#read 6, iclass 40, count 0 2006.201.14:01:26.52#ibcon#end of sib2, iclass 40, count 0 2006.201.14:01:26.52#ibcon#*mode == 0, iclass 40, count 0 2006.201.14:01:26.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.14:01:26.52#ibcon#[25=USB\r\n] 2006.201.14:01:26.52#ibcon#*before write, iclass 40, count 0 2006.201.14:01:26.52#ibcon#enter sib2, iclass 40, count 0 2006.201.14:01:26.52#ibcon#flushed, iclass 40, count 0 2006.201.14:01:26.52#ibcon#about to write, iclass 40, count 0 2006.201.14:01:26.52#ibcon#wrote, iclass 40, count 0 2006.201.14:01:26.52#ibcon#about to read 3, iclass 40, count 0 2006.201.14:01:26.55#ibcon#read 3, iclass 40, count 0 2006.201.14:01:26.55#ibcon#about to read 4, iclass 40, count 0 2006.201.14:01:26.55#ibcon#read 4, iclass 40, count 0 2006.201.14:01:26.55#ibcon#about to read 5, iclass 40, count 0 2006.201.14:01:26.55#ibcon#read 5, iclass 40, count 0 2006.201.14:01:26.55#ibcon#about to read 6, iclass 40, count 0 2006.201.14:01:26.55#ibcon#read 6, iclass 40, count 0 2006.201.14:01:26.55#ibcon#end of sib2, iclass 40, count 0 2006.201.14:01:26.55#ibcon#*after write, iclass 40, count 0 2006.201.14:01:26.55#ibcon#*before return 0, iclass 40, count 0 2006.201.14:01:26.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:01:26.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:01:26.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.14:01:26.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.14:01:26.55$vck44/vblo=1,629.99 2006.201.14:01:26.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.14:01:26.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.14:01:26.55#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:26.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:26.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:26.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:26.55#ibcon#enter wrdev, iclass 4, count 0 2006.201.14:01:26.55#ibcon#first serial, iclass 4, count 0 2006.201.14:01:26.55#ibcon#enter sib2, iclass 4, count 0 2006.201.14:01:26.55#ibcon#flushed, iclass 4, count 0 2006.201.14:01:26.55#ibcon#about to write, iclass 4, count 0 2006.201.14:01:26.55#ibcon#wrote, iclass 4, count 0 2006.201.14:01:26.55#ibcon#about to read 3, iclass 4, count 0 2006.201.14:01:26.57#ibcon#read 3, iclass 4, count 0 2006.201.14:01:26.57#ibcon#about to read 4, iclass 4, count 0 2006.201.14:01:26.57#ibcon#read 4, iclass 4, count 0 2006.201.14:01:26.57#ibcon#about to read 5, iclass 4, count 0 2006.201.14:01:26.57#ibcon#read 5, iclass 4, count 0 2006.201.14:01:26.57#ibcon#about to read 6, iclass 4, count 0 2006.201.14:01:26.57#ibcon#read 6, iclass 4, count 0 2006.201.14:01:26.57#ibcon#end of sib2, iclass 4, count 0 2006.201.14:01:26.57#ibcon#*mode == 0, iclass 4, count 0 2006.201.14:01:26.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.14:01:26.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:01:26.57#ibcon#*before write, iclass 4, count 0 2006.201.14:01:26.57#ibcon#enter sib2, iclass 4, count 0 2006.201.14:01:26.57#ibcon#flushed, iclass 4, count 0 2006.201.14:01:26.57#ibcon#about to write, iclass 4, count 0 2006.201.14:01:26.57#ibcon#wrote, iclass 4, count 0 2006.201.14:01:26.57#ibcon#about to read 3, iclass 4, count 0 2006.201.14:01:26.62#ibcon#read 3, iclass 4, count 0 2006.201.14:01:26.62#ibcon#about to read 4, iclass 4, count 0 2006.201.14:01:26.62#ibcon#read 4, iclass 4, count 0 2006.201.14:01:26.62#ibcon#about to read 5, iclass 4, count 0 2006.201.14:01:26.62#ibcon#read 5, iclass 4, count 0 2006.201.14:01:26.62#ibcon#about to read 6, iclass 4, count 0 2006.201.14:01:26.62#ibcon#read 6, iclass 4, count 0 2006.201.14:01:26.62#ibcon#end of sib2, iclass 4, count 0 2006.201.14:01:26.62#ibcon#*after write, iclass 4, count 0 2006.201.14:01:26.62#ibcon#*before return 0, iclass 4, count 0 2006.201.14:01:26.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:26.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:01:26.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.14:01:26.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.14:01:26.62$vck44/vb=1,4 2006.201.14:01:26.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.14:01:26.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.14:01:26.62#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:26.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:01:26.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:01:26.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:01:26.62#ibcon#enter wrdev, iclass 6, count 2 2006.201.14:01:26.62#ibcon#first serial, iclass 6, count 2 2006.201.14:01:26.62#ibcon#enter sib2, iclass 6, count 2 2006.201.14:01:26.62#ibcon#flushed, iclass 6, count 2 2006.201.14:01:26.62#ibcon#about to write, iclass 6, count 2 2006.201.14:01:26.62#ibcon#wrote, iclass 6, count 2 2006.201.14:01:26.62#ibcon#about to read 3, iclass 6, count 2 2006.201.14:01:26.64#ibcon#read 3, iclass 6, count 2 2006.201.14:01:26.64#ibcon#about to read 4, iclass 6, count 2 2006.201.14:01:26.64#ibcon#read 4, iclass 6, count 2 2006.201.14:01:26.64#ibcon#about to read 5, iclass 6, count 2 2006.201.14:01:26.64#ibcon#read 5, iclass 6, count 2 2006.201.14:01:26.64#ibcon#about to read 6, iclass 6, count 2 2006.201.14:01:26.64#ibcon#read 6, iclass 6, count 2 2006.201.14:01:26.64#ibcon#end of sib2, iclass 6, count 2 2006.201.14:01:26.64#ibcon#*mode == 0, iclass 6, count 2 2006.201.14:01:26.64#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.14:01:26.64#ibcon#[27=AT01-04\r\n] 2006.201.14:01:26.64#ibcon#*before write, iclass 6, count 2 2006.201.14:01:26.64#ibcon#enter sib2, iclass 6, count 2 2006.201.14:01:26.64#ibcon#flushed, iclass 6, count 2 2006.201.14:01:26.64#ibcon#about to write, iclass 6, count 2 2006.201.14:01:26.64#ibcon#wrote, iclass 6, count 2 2006.201.14:01:26.64#ibcon#about to read 3, iclass 6, count 2 2006.201.14:01:26.67#ibcon#read 3, iclass 6, count 2 2006.201.14:01:26.67#ibcon#about to read 4, iclass 6, count 2 2006.201.14:01:26.67#ibcon#read 4, iclass 6, count 2 2006.201.14:01:26.67#ibcon#about to read 5, iclass 6, count 2 2006.201.14:01:26.67#ibcon#read 5, iclass 6, count 2 2006.201.14:01:26.67#ibcon#about to read 6, iclass 6, count 2 2006.201.14:01:26.67#ibcon#read 6, iclass 6, count 2 2006.201.14:01:26.67#ibcon#end of sib2, iclass 6, count 2 2006.201.14:01:26.67#ibcon#*after write, iclass 6, count 2 2006.201.14:01:26.67#ibcon#*before return 0, iclass 6, count 2 2006.201.14:01:26.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:01:26.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:01:26.67#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.14:01:26.67#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:26.67#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:01:26.79#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:01:26.79#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:01:26.79#ibcon#enter wrdev, iclass 6, count 0 2006.201.14:01:26.79#ibcon#first serial, iclass 6, count 0 2006.201.14:01:26.79#ibcon#enter sib2, iclass 6, count 0 2006.201.14:01:26.79#ibcon#flushed, iclass 6, count 0 2006.201.14:01:26.79#ibcon#about to write, iclass 6, count 0 2006.201.14:01:26.79#ibcon#wrote, iclass 6, count 0 2006.201.14:01:26.79#ibcon#about to read 3, iclass 6, count 0 2006.201.14:01:26.81#ibcon#read 3, iclass 6, count 0 2006.201.14:01:26.81#ibcon#about to read 4, iclass 6, count 0 2006.201.14:01:26.81#ibcon#read 4, iclass 6, count 0 2006.201.14:01:26.81#ibcon#about to read 5, iclass 6, count 0 2006.201.14:01:26.81#ibcon#read 5, iclass 6, count 0 2006.201.14:01:26.81#ibcon#about to read 6, iclass 6, count 0 2006.201.14:01:26.81#ibcon#read 6, iclass 6, count 0 2006.201.14:01:26.81#ibcon#end of sib2, iclass 6, count 0 2006.201.14:01:26.81#ibcon#*mode == 0, iclass 6, count 0 2006.201.14:01:26.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.14:01:26.81#ibcon#[27=USB\r\n] 2006.201.14:01:26.81#ibcon#*before write, iclass 6, count 0 2006.201.14:01:26.81#ibcon#enter sib2, iclass 6, count 0 2006.201.14:01:26.81#ibcon#flushed, iclass 6, count 0 2006.201.14:01:26.81#ibcon#about to write, iclass 6, count 0 2006.201.14:01:26.81#ibcon#wrote, iclass 6, count 0 2006.201.14:01:26.81#ibcon#about to read 3, iclass 6, count 0 2006.201.14:01:26.84#ibcon#read 3, iclass 6, count 0 2006.201.14:01:26.84#ibcon#about to read 4, iclass 6, count 0 2006.201.14:01:26.84#ibcon#read 4, iclass 6, count 0 2006.201.14:01:26.84#ibcon#about to read 5, iclass 6, count 0 2006.201.14:01:26.84#ibcon#read 5, iclass 6, count 0 2006.201.14:01:26.84#ibcon#about to read 6, iclass 6, count 0 2006.201.14:01:26.84#ibcon#read 6, iclass 6, count 0 2006.201.14:01:26.84#ibcon#end of sib2, iclass 6, count 0 2006.201.14:01:26.84#ibcon#*after write, iclass 6, count 0 2006.201.14:01:26.84#ibcon#*before return 0, iclass 6, count 0 2006.201.14:01:26.84#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:01:26.84#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:01:26.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.14:01:26.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.14:01:26.84$vck44/vblo=2,634.99 2006.201.14:01:26.84#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.14:01:26.84#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.14:01:26.84#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:26.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:01:26.84#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:01:26.84#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:01:26.84#ibcon#enter wrdev, iclass 10, count 0 2006.201.14:01:26.84#ibcon#first serial, iclass 10, count 0 2006.201.14:01:26.84#ibcon#enter sib2, iclass 10, count 0 2006.201.14:01:26.84#ibcon#flushed, iclass 10, count 0 2006.201.14:01:26.84#ibcon#about to write, iclass 10, count 0 2006.201.14:01:26.84#ibcon#wrote, iclass 10, count 0 2006.201.14:01:26.84#ibcon#about to read 3, iclass 10, count 0 2006.201.14:01:26.86#ibcon#read 3, iclass 10, count 0 2006.201.14:01:26.86#ibcon#about to read 4, iclass 10, count 0 2006.201.14:01:26.86#ibcon#read 4, iclass 10, count 0 2006.201.14:01:26.86#ibcon#about to read 5, iclass 10, count 0 2006.201.14:01:26.86#ibcon#read 5, iclass 10, count 0 2006.201.14:01:26.86#ibcon#about to read 6, iclass 10, count 0 2006.201.14:01:26.86#ibcon#read 6, iclass 10, count 0 2006.201.14:01:26.86#ibcon#end of sib2, iclass 10, count 0 2006.201.14:01:26.86#ibcon#*mode == 0, iclass 10, count 0 2006.201.14:01:26.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.14:01:26.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:01:26.86#ibcon#*before write, iclass 10, count 0 2006.201.14:01:26.86#ibcon#enter sib2, iclass 10, count 0 2006.201.14:01:26.86#ibcon#flushed, iclass 10, count 0 2006.201.14:01:26.86#ibcon#about to write, iclass 10, count 0 2006.201.14:01:26.86#ibcon#wrote, iclass 10, count 0 2006.201.14:01:26.86#ibcon#about to read 3, iclass 10, count 0 2006.201.14:01:26.90#ibcon#read 3, iclass 10, count 0 2006.201.14:01:26.90#ibcon#about to read 4, iclass 10, count 0 2006.201.14:01:26.90#ibcon#read 4, iclass 10, count 0 2006.201.14:01:26.90#ibcon#about to read 5, iclass 10, count 0 2006.201.14:01:26.90#ibcon#read 5, iclass 10, count 0 2006.201.14:01:26.90#ibcon#about to read 6, iclass 10, count 0 2006.201.14:01:26.90#ibcon#read 6, iclass 10, count 0 2006.201.14:01:26.90#ibcon#end of sib2, iclass 10, count 0 2006.201.14:01:26.90#ibcon#*after write, iclass 10, count 0 2006.201.14:01:26.90#ibcon#*before return 0, iclass 10, count 0 2006.201.14:01:26.90#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:01:26.90#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:01:26.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.14:01:26.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.14:01:26.90$vck44/vb=2,5 2006.201.14:01:26.90#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.14:01:26.90#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.14:01:26.90#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:26.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:01:26.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:01:26.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:01:26.96#ibcon#enter wrdev, iclass 12, count 2 2006.201.14:01:26.96#ibcon#first serial, iclass 12, count 2 2006.201.14:01:26.96#ibcon#enter sib2, iclass 12, count 2 2006.201.14:01:26.96#ibcon#flushed, iclass 12, count 2 2006.201.14:01:26.96#ibcon#about to write, iclass 12, count 2 2006.201.14:01:26.96#ibcon#wrote, iclass 12, count 2 2006.201.14:01:26.96#ibcon#about to read 3, iclass 12, count 2 2006.201.14:01:26.98#ibcon#read 3, iclass 12, count 2 2006.201.14:01:26.98#ibcon#about to read 4, iclass 12, count 2 2006.201.14:01:26.98#ibcon#read 4, iclass 12, count 2 2006.201.14:01:26.98#ibcon#about to read 5, iclass 12, count 2 2006.201.14:01:26.98#ibcon#read 5, iclass 12, count 2 2006.201.14:01:26.98#ibcon#about to read 6, iclass 12, count 2 2006.201.14:01:26.98#ibcon#read 6, iclass 12, count 2 2006.201.14:01:26.98#ibcon#end of sib2, iclass 12, count 2 2006.201.14:01:26.98#ibcon#*mode == 0, iclass 12, count 2 2006.201.14:01:26.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.14:01:26.98#ibcon#[27=AT02-05\r\n] 2006.201.14:01:26.98#ibcon#*before write, iclass 12, count 2 2006.201.14:01:26.98#ibcon#enter sib2, iclass 12, count 2 2006.201.14:01:26.98#ibcon#flushed, iclass 12, count 2 2006.201.14:01:26.98#ibcon#about to write, iclass 12, count 2 2006.201.14:01:26.98#ibcon#wrote, iclass 12, count 2 2006.201.14:01:26.98#ibcon#about to read 3, iclass 12, count 2 2006.201.14:01:27.01#ibcon#read 3, iclass 12, count 2 2006.201.14:01:27.01#ibcon#about to read 4, iclass 12, count 2 2006.201.14:01:27.01#ibcon#read 4, iclass 12, count 2 2006.201.14:01:27.01#ibcon#about to read 5, iclass 12, count 2 2006.201.14:01:27.01#ibcon#read 5, iclass 12, count 2 2006.201.14:01:27.01#ibcon#about to read 6, iclass 12, count 2 2006.201.14:01:27.01#ibcon#read 6, iclass 12, count 2 2006.201.14:01:27.01#ibcon#end of sib2, iclass 12, count 2 2006.201.14:01:27.01#ibcon#*after write, iclass 12, count 2 2006.201.14:01:27.01#ibcon#*before return 0, iclass 12, count 2 2006.201.14:01:27.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:01:27.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:01:27.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.14:01:27.01#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:27.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:01:27.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:01:27.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:01:27.13#ibcon#enter wrdev, iclass 12, count 0 2006.201.14:01:27.13#ibcon#first serial, iclass 12, count 0 2006.201.14:01:27.13#ibcon#enter sib2, iclass 12, count 0 2006.201.14:01:27.13#ibcon#flushed, iclass 12, count 0 2006.201.14:01:27.13#ibcon#about to write, iclass 12, count 0 2006.201.14:01:27.13#ibcon#wrote, iclass 12, count 0 2006.201.14:01:27.13#ibcon#about to read 3, iclass 12, count 0 2006.201.14:01:27.15#ibcon#read 3, iclass 12, count 0 2006.201.14:01:27.15#ibcon#about to read 4, iclass 12, count 0 2006.201.14:01:27.15#ibcon#read 4, iclass 12, count 0 2006.201.14:01:27.15#ibcon#about to read 5, iclass 12, count 0 2006.201.14:01:27.15#ibcon#read 5, iclass 12, count 0 2006.201.14:01:27.15#ibcon#about to read 6, iclass 12, count 0 2006.201.14:01:27.15#ibcon#read 6, iclass 12, count 0 2006.201.14:01:27.15#ibcon#end of sib2, iclass 12, count 0 2006.201.14:01:27.15#ibcon#*mode == 0, iclass 12, count 0 2006.201.14:01:27.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.14:01:27.15#ibcon#[27=USB\r\n] 2006.201.14:01:27.15#ibcon#*before write, iclass 12, count 0 2006.201.14:01:27.15#ibcon#enter sib2, iclass 12, count 0 2006.201.14:01:27.15#ibcon#flushed, iclass 12, count 0 2006.201.14:01:27.15#ibcon#about to write, iclass 12, count 0 2006.201.14:01:27.15#ibcon#wrote, iclass 12, count 0 2006.201.14:01:27.15#ibcon#about to read 3, iclass 12, count 0 2006.201.14:01:27.18#ibcon#read 3, iclass 12, count 0 2006.201.14:01:27.18#ibcon#about to read 4, iclass 12, count 0 2006.201.14:01:27.18#ibcon#read 4, iclass 12, count 0 2006.201.14:01:27.18#ibcon#about to read 5, iclass 12, count 0 2006.201.14:01:27.18#ibcon#read 5, iclass 12, count 0 2006.201.14:01:27.18#ibcon#about to read 6, iclass 12, count 0 2006.201.14:01:27.18#ibcon#read 6, iclass 12, count 0 2006.201.14:01:27.18#ibcon#end of sib2, iclass 12, count 0 2006.201.14:01:27.18#ibcon#*after write, iclass 12, count 0 2006.201.14:01:27.18#ibcon#*before return 0, iclass 12, count 0 2006.201.14:01:27.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:01:27.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:01:27.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.14:01:27.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.14:01:27.18$vck44/vblo=3,649.99 2006.201.14:01:27.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.14:01:27.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.14:01:27.18#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:27.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:27.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:27.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:27.18#ibcon#enter wrdev, iclass 14, count 0 2006.201.14:01:27.18#ibcon#first serial, iclass 14, count 0 2006.201.14:01:27.18#ibcon#enter sib2, iclass 14, count 0 2006.201.14:01:27.18#ibcon#flushed, iclass 14, count 0 2006.201.14:01:27.18#ibcon#about to write, iclass 14, count 0 2006.201.14:01:27.18#ibcon#wrote, iclass 14, count 0 2006.201.14:01:27.18#ibcon#about to read 3, iclass 14, count 0 2006.201.14:01:27.20#ibcon#read 3, iclass 14, count 0 2006.201.14:01:27.20#ibcon#about to read 4, iclass 14, count 0 2006.201.14:01:27.20#ibcon#read 4, iclass 14, count 0 2006.201.14:01:27.20#ibcon#about to read 5, iclass 14, count 0 2006.201.14:01:27.20#ibcon#read 5, iclass 14, count 0 2006.201.14:01:27.20#ibcon#about to read 6, iclass 14, count 0 2006.201.14:01:27.20#ibcon#read 6, iclass 14, count 0 2006.201.14:01:27.20#ibcon#end of sib2, iclass 14, count 0 2006.201.14:01:27.20#ibcon#*mode == 0, iclass 14, count 0 2006.201.14:01:27.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.14:01:27.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:01:27.20#ibcon#*before write, iclass 14, count 0 2006.201.14:01:27.20#ibcon#enter sib2, iclass 14, count 0 2006.201.14:01:27.20#ibcon#flushed, iclass 14, count 0 2006.201.14:01:27.20#ibcon#about to write, iclass 14, count 0 2006.201.14:01:27.20#ibcon#wrote, iclass 14, count 0 2006.201.14:01:27.20#ibcon#about to read 3, iclass 14, count 0 2006.201.14:01:27.25#ibcon#read 3, iclass 14, count 0 2006.201.14:01:27.25#ibcon#about to read 4, iclass 14, count 0 2006.201.14:01:27.25#ibcon#read 4, iclass 14, count 0 2006.201.14:01:27.25#ibcon#about to read 5, iclass 14, count 0 2006.201.14:01:27.25#ibcon#read 5, iclass 14, count 0 2006.201.14:01:27.25#ibcon#about to read 6, iclass 14, count 0 2006.201.14:01:27.25#ibcon#read 6, iclass 14, count 0 2006.201.14:01:27.25#ibcon#end of sib2, iclass 14, count 0 2006.201.14:01:27.25#ibcon#*after write, iclass 14, count 0 2006.201.14:01:27.25#ibcon#*before return 0, iclass 14, count 0 2006.201.14:01:27.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:27.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:01:27.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.14:01:27.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.14:01:27.25$vck44/vb=3,4 2006.201.14:01:27.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.14:01:27.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.14:01:27.25#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:27.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:27.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:27.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:27.30#ibcon#enter wrdev, iclass 16, count 2 2006.201.14:01:27.30#ibcon#first serial, iclass 16, count 2 2006.201.14:01:27.30#ibcon#enter sib2, iclass 16, count 2 2006.201.14:01:27.30#ibcon#flushed, iclass 16, count 2 2006.201.14:01:27.30#ibcon#about to write, iclass 16, count 2 2006.201.14:01:27.30#ibcon#wrote, iclass 16, count 2 2006.201.14:01:27.30#ibcon#about to read 3, iclass 16, count 2 2006.201.14:01:27.32#ibcon#read 3, iclass 16, count 2 2006.201.14:01:27.32#ibcon#about to read 4, iclass 16, count 2 2006.201.14:01:27.32#ibcon#read 4, iclass 16, count 2 2006.201.14:01:27.32#ibcon#about to read 5, iclass 16, count 2 2006.201.14:01:27.32#ibcon#read 5, iclass 16, count 2 2006.201.14:01:27.32#ibcon#about to read 6, iclass 16, count 2 2006.201.14:01:27.32#ibcon#read 6, iclass 16, count 2 2006.201.14:01:27.32#ibcon#end of sib2, iclass 16, count 2 2006.201.14:01:27.32#ibcon#*mode == 0, iclass 16, count 2 2006.201.14:01:27.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.14:01:27.32#ibcon#[27=AT03-04\r\n] 2006.201.14:01:27.32#ibcon#*before write, iclass 16, count 2 2006.201.14:01:27.32#ibcon#enter sib2, iclass 16, count 2 2006.201.14:01:27.32#ibcon#flushed, iclass 16, count 2 2006.201.14:01:27.32#ibcon#about to write, iclass 16, count 2 2006.201.14:01:27.32#ibcon#wrote, iclass 16, count 2 2006.201.14:01:27.32#ibcon#about to read 3, iclass 16, count 2 2006.201.14:01:27.35#ibcon#read 3, iclass 16, count 2 2006.201.14:01:27.35#ibcon#about to read 4, iclass 16, count 2 2006.201.14:01:27.35#ibcon#read 4, iclass 16, count 2 2006.201.14:01:27.35#ibcon#about to read 5, iclass 16, count 2 2006.201.14:01:27.35#ibcon#read 5, iclass 16, count 2 2006.201.14:01:27.35#ibcon#about to read 6, iclass 16, count 2 2006.201.14:01:27.35#ibcon#read 6, iclass 16, count 2 2006.201.14:01:27.35#ibcon#end of sib2, iclass 16, count 2 2006.201.14:01:27.35#ibcon#*after write, iclass 16, count 2 2006.201.14:01:27.35#ibcon#*before return 0, iclass 16, count 2 2006.201.14:01:27.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:27.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:01:27.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.14:01:27.35#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:27.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:27.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:27.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:27.47#ibcon#enter wrdev, iclass 16, count 0 2006.201.14:01:27.47#ibcon#first serial, iclass 16, count 0 2006.201.14:01:27.47#ibcon#enter sib2, iclass 16, count 0 2006.201.14:01:27.47#ibcon#flushed, iclass 16, count 0 2006.201.14:01:27.47#ibcon#about to write, iclass 16, count 0 2006.201.14:01:27.47#ibcon#wrote, iclass 16, count 0 2006.201.14:01:27.47#ibcon#about to read 3, iclass 16, count 0 2006.201.14:01:27.49#ibcon#read 3, iclass 16, count 0 2006.201.14:01:27.49#ibcon#about to read 4, iclass 16, count 0 2006.201.14:01:27.49#ibcon#read 4, iclass 16, count 0 2006.201.14:01:27.49#ibcon#about to read 5, iclass 16, count 0 2006.201.14:01:27.49#ibcon#read 5, iclass 16, count 0 2006.201.14:01:27.49#ibcon#about to read 6, iclass 16, count 0 2006.201.14:01:27.49#ibcon#read 6, iclass 16, count 0 2006.201.14:01:27.49#ibcon#end of sib2, iclass 16, count 0 2006.201.14:01:27.49#ibcon#*mode == 0, iclass 16, count 0 2006.201.14:01:27.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.14:01:27.49#ibcon#[27=USB\r\n] 2006.201.14:01:27.49#ibcon#*before write, iclass 16, count 0 2006.201.14:01:27.49#ibcon#enter sib2, iclass 16, count 0 2006.201.14:01:27.49#ibcon#flushed, iclass 16, count 0 2006.201.14:01:27.49#ibcon#about to write, iclass 16, count 0 2006.201.14:01:27.49#ibcon#wrote, iclass 16, count 0 2006.201.14:01:27.49#ibcon#about to read 3, iclass 16, count 0 2006.201.14:01:27.52#ibcon#read 3, iclass 16, count 0 2006.201.14:01:27.52#ibcon#about to read 4, iclass 16, count 0 2006.201.14:01:27.52#ibcon#read 4, iclass 16, count 0 2006.201.14:01:27.52#ibcon#about to read 5, iclass 16, count 0 2006.201.14:01:27.52#ibcon#read 5, iclass 16, count 0 2006.201.14:01:27.52#ibcon#about to read 6, iclass 16, count 0 2006.201.14:01:27.52#ibcon#read 6, iclass 16, count 0 2006.201.14:01:27.52#ibcon#end of sib2, iclass 16, count 0 2006.201.14:01:27.52#ibcon#*after write, iclass 16, count 0 2006.201.14:01:27.52#ibcon#*before return 0, iclass 16, count 0 2006.201.14:01:27.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:27.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:01:27.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.14:01:27.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.14:01:27.52$vck44/vblo=4,679.99 2006.201.14:01:27.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.14:01:27.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.14:01:27.52#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:27.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:27.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:27.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:27.52#ibcon#enter wrdev, iclass 18, count 0 2006.201.14:01:27.52#ibcon#first serial, iclass 18, count 0 2006.201.14:01:27.52#ibcon#enter sib2, iclass 18, count 0 2006.201.14:01:27.52#ibcon#flushed, iclass 18, count 0 2006.201.14:01:27.52#ibcon#about to write, iclass 18, count 0 2006.201.14:01:27.52#ibcon#wrote, iclass 18, count 0 2006.201.14:01:27.52#ibcon#about to read 3, iclass 18, count 0 2006.201.14:01:27.54#ibcon#read 3, iclass 18, count 0 2006.201.14:01:27.54#ibcon#about to read 4, iclass 18, count 0 2006.201.14:01:27.54#ibcon#read 4, iclass 18, count 0 2006.201.14:01:27.54#ibcon#about to read 5, iclass 18, count 0 2006.201.14:01:27.54#ibcon#read 5, iclass 18, count 0 2006.201.14:01:27.54#ibcon#about to read 6, iclass 18, count 0 2006.201.14:01:27.54#ibcon#read 6, iclass 18, count 0 2006.201.14:01:27.54#ibcon#end of sib2, iclass 18, count 0 2006.201.14:01:27.54#ibcon#*mode == 0, iclass 18, count 0 2006.201.14:01:27.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.14:01:27.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:01:27.54#ibcon#*before write, iclass 18, count 0 2006.201.14:01:27.54#ibcon#enter sib2, iclass 18, count 0 2006.201.14:01:27.54#ibcon#flushed, iclass 18, count 0 2006.201.14:01:27.54#ibcon#about to write, iclass 18, count 0 2006.201.14:01:27.54#ibcon#wrote, iclass 18, count 0 2006.201.14:01:27.54#ibcon#about to read 3, iclass 18, count 0 2006.201.14:01:27.58#ibcon#read 3, iclass 18, count 0 2006.201.14:01:27.58#ibcon#about to read 4, iclass 18, count 0 2006.201.14:01:27.58#ibcon#read 4, iclass 18, count 0 2006.201.14:01:27.58#ibcon#about to read 5, iclass 18, count 0 2006.201.14:01:27.58#ibcon#read 5, iclass 18, count 0 2006.201.14:01:27.58#ibcon#about to read 6, iclass 18, count 0 2006.201.14:01:27.58#ibcon#read 6, iclass 18, count 0 2006.201.14:01:27.58#ibcon#end of sib2, iclass 18, count 0 2006.201.14:01:27.58#ibcon#*after write, iclass 18, count 0 2006.201.14:01:27.58#ibcon#*before return 0, iclass 18, count 0 2006.201.14:01:27.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:27.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:01:27.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.14:01:27.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.14:01:27.58$vck44/vb=4,5 2006.201.14:01:27.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.14:01:27.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.14:01:27.58#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:27.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:27.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:27.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:27.64#ibcon#enter wrdev, iclass 20, count 2 2006.201.14:01:27.64#ibcon#first serial, iclass 20, count 2 2006.201.14:01:27.64#ibcon#enter sib2, iclass 20, count 2 2006.201.14:01:27.64#ibcon#flushed, iclass 20, count 2 2006.201.14:01:27.64#ibcon#about to write, iclass 20, count 2 2006.201.14:01:27.64#ibcon#wrote, iclass 20, count 2 2006.201.14:01:27.64#ibcon#about to read 3, iclass 20, count 2 2006.201.14:01:27.66#ibcon#read 3, iclass 20, count 2 2006.201.14:01:27.66#ibcon#about to read 4, iclass 20, count 2 2006.201.14:01:27.66#ibcon#read 4, iclass 20, count 2 2006.201.14:01:27.66#ibcon#about to read 5, iclass 20, count 2 2006.201.14:01:27.66#ibcon#read 5, iclass 20, count 2 2006.201.14:01:27.66#ibcon#about to read 6, iclass 20, count 2 2006.201.14:01:27.66#ibcon#read 6, iclass 20, count 2 2006.201.14:01:27.66#ibcon#end of sib2, iclass 20, count 2 2006.201.14:01:27.66#ibcon#*mode == 0, iclass 20, count 2 2006.201.14:01:27.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.14:01:27.66#ibcon#[27=AT04-05\r\n] 2006.201.14:01:27.66#ibcon#*before write, iclass 20, count 2 2006.201.14:01:27.66#ibcon#enter sib2, iclass 20, count 2 2006.201.14:01:27.66#ibcon#flushed, iclass 20, count 2 2006.201.14:01:27.66#ibcon#about to write, iclass 20, count 2 2006.201.14:01:27.66#ibcon#wrote, iclass 20, count 2 2006.201.14:01:27.66#ibcon#about to read 3, iclass 20, count 2 2006.201.14:01:27.69#ibcon#read 3, iclass 20, count 2 2006.201.14:01:27.69#ibcon#about to read 4, iclass 20, count 2 2006.201.14:01:27.69#ibcon#read 4, iclass 20, count 2 2006.201.14:01:27.69#ibcon#about to read 5, iclass 20, count 2 2006.201.14:01:27.69#ibcon#read 5, iclass 20, count 2 2006.201.14:01:27.69#ibcon#about to read 6, iclass 20, count 2 2006.201.14:01:27.69#ibcon#read 6, iclass 20, count 2 2006.201.14:01:27.69#ibcon#end of sib2, iclass 20, count 2 2006.201.14:01:27.69#ibcon#*after write, iclass 20, count 2 2006.201.14:01:27.69#ibcon#*before return 0, iclass 20, count 2 2006.201.14:01:27.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:27.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:01:27.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.14:01:27.69#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:27.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:27.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:27.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:27.81#ibcon#enter wrdev, iclass 20, count 0 2006.201.14:01:27.81#ibcon#first serial, iclass 20, count 0 2006.201.14:01:27.81#ibcon#enter sib2, iclass 20, count 0 2006.201.14:01:27.81#ibcon#flushed, iclass 20, count 0 2006.201.14:01:27.81#ibcon#about to write, iclass 20, count 0 2006.201.14:01:27.81#ibcon#wrote, iclass 20, count 0 2006.201.14:01:27.81#ibcon#about to read 3, iclass 20, count 0 2006.201.14:01:27.83#ibcon#read 3, iclass 20, count 0 2006.201.14:01:27.83#ibcon#about to read 4, iclass 20, count 0 2006.201.14:01:27.83#ibcon#read 4, iclass 20, count 0 2006.201.14:01:27.83#ibcon#about to read 5, iclass 20, count 0 2006.201.14:01:27.83#ibcon#read 5, iclass 20, count 0 2006.201.14:01:27.83#ibcon#about to read 6, iclass 20, count 0 2006.201.14:01:27.83#ibcon#read 6, iclass 20, count 0 2006.201.14:01:27.83#ibcon#end of sib2, iclass 20, count 0 2006.201.14:01:27.83#ibcon#*mode == 0, iclass 20, count 0 2006.201.14:01:27.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.14:01:27.83#ibcon#[27=USB\r\n] 2006.201.14:01:27.83#ibcon#*before write, iclass 20, count 0 2006.201.14:01:27.83#ibcon#enter sib2, iclass 20, count 0 2006.201.14:01:27.83#ibcon#flushed, iclass 20, count 0 2006.201.14:01:27.83#ibcon#about to write, iclass 20, count 0 2006.201.14:01:27.83#ibcon#wrote, iclass 20, count 0 2006.201.14:01:27.83#ibcon#about to read 3, iclass 20, count 0 2006.201.14:01:27.86#ibcon#read 3, iclass 20, count 0 2006.201.14:01:27.86#ibcon#about to read 4, iclass 20, count 0 2006.201.14:01:27.86#ibcon#read 4, iclass 20, count 0 2006.201.14:01:27.86#ibcon#about to read 5, iclass 20, count 0 2006.201.14:01:27.86#ibcon#read 5, iclass 20, count 0 2006.201.14:01:27.86#ibcon#about to read 6, iclass 20, count 0 2006.201.14:01:27.86#ibcon#read 6, iclass 20, count 0 2006.201.14:01:27.86#ibcon#end of sib2, iclass 20, count 0 2006.201.14:01:27.86#ibcon#*after write, iclass 20, count 0 2006.201.14:01:27.86#ibcon#*before return 0, iclass 20, count 0 2006.201.14:01:27.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:27.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:01:27.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.14:01:27.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.14:01:27.86$vck44/vblo=5,709.99 2006.201.14:01:27.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.14:01:27.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.14:01:27.86#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:27.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:27.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:27.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:27.86#ibcon#enter wrdev, iclass 22, count 0 2006.201.14:01:27.86#ibcon#first serial, iclass 22, count 0 2006.201.14:01:27.86#ibcon#enter sib2, iclass 22, count 0 2006.201.14:01:27.86#ibcon#flushed, iclass 22, count 0 2006.201.14:01:27.86#ibcon#about to write, iclass 22, count 0 2006.201.14:01:27.86#ibcon#wrote, iclass 22, count 0 2006.201.14:01:27.86#ibcon#about to read 3, iclass 22, count 0 2006.201.14:01:27.88#ibcon#read 3, iclass 22, count 0 2006.201.14:01:27.88#ibcon#about to read 4, iclass 22, count 0 2006.201.14:01:27.88#ibcon#read 4, iclass 22, count 0 2006.201.14:01:27.88#ibcon#about to read 5, iclass 22, count 0 2006.201.14:01:27.88#ibcon#read 5, iclass 22, count 0 2006.201.14:01:27.88#ibcon#about to read 6, iclass 22, count 0 2006.201.14:01:27.88#ibcon#read 6, iclass 22, count 0 2006.201.14:01:27.88#ibcon#end of sib2, iclass 22, count 0 2006.201.14:01:27.88#ibcon#*mode == 0, iclass 22, count 0 2006.201.14:01:27.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.14:01:27.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:01:27.88#ibcon#*before write, iclass 22, count 0 2006.201.14:01:27.88#ibcon#enter sib2, iclass 22, count 0 2006.201.14:01:27.88#ibcon#flushed, iclass 22, count 0 2006.201.14:01:27.88#ibcon#about to write, iclass 22, count 0 2006.201.14:01:27.88#ibcon#wrote, iclass 22, count 0 2006.201.14:01:27.88#ibcon#about to read 3, iclass 22, count 0 2006.201.14:01:27.92#ibcon#read 3, iclass 22, count 0 2006.201.14:01:27.92#ibcon#about to read 4, iclass 22, count 0 2006.201.14:01:27.92#ibcon#read 4, iclass 22, count 0 2006.201.14:01:27.92#ibcon#about to read 5, iclass 22, count 0 2006.201.14:01:27.92#ibcon#read 5, iclass 22, count 0 2006.201.14:01:27.92#ibcon#about to read 6, iclass 22, count 0 2006.201.14:01:27.92#ibcon#read 6, iclass 22, count 0 2006.201.14:01:27.92#ibcon#end of sib2, iclass 22, count 0 2006.201.14:01:27.92#ibcon#*after write, iclass 22, count 0 2006.201.14:01:27.92#ibcon#*before return 0, iclass 22, count 0 2006.201.14:01:27.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:27.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:01:27.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.14:01:27.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.14:01:27.92$vck44/vb=5,4 2006.201.14:01:27.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.14:01:27.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.14:01:27.92#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:27.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:27.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:27.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:27.98#ibcon#enter wrdev, iclass 24, count 2 2006.201.14:01:27.98#ibcon#first serial, iclass 24, count 2 2006.201.14:01:27.98#ibcon#enter sib2, iclass 24, count 2 2006.201.14:01:27.98#ibcon#flushed, iclass 24, count 2 2006.201.14:01:27.98#ibcon#about to write, iclass 24, count 2 2006.201.14:01:27.98#ibcon#wrote, iclass 24, count 2 2006.201.14:01:27.98#ibcon#about to read 3, iclass 24, count 2 2006.201.14:01:28.00#ibcon#read 3, iclass 24, count 2 2006.201.14:01:28.00#ibcon#about to read 4, iclass 24, count 2 2006.201.14:01:28.00#ibcon#read 4, iclass 24, count 2 2006.201.14:01:28.00#ibcon#about to read 5, iclass 24, count 2 2006.201.14:01:28.00#ibcon#read 5, iclass 24, count 2 2006.201.14:01:28.00#ibcon#about to read 6, iclass 24, count 2 2006.201.14:01:28.00#ibcon#read 6, iclass 24, count 2 2006.201.14:01:28.00#ibcon#end of sib2, iclass 24, count 2 2006.201.14:01:28.00#ibcon#*mode == 0, iclass 24, count 2 2006.201.14:01:28.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.14:01:28.00#ibcon#[27=AT05-04\r\n] 2006.201.14:01:28.00#ibcon#*before write, iclass 24, count 2 2006.201.14:01:28.00#ibcon#enter sib2, iclass 24, count 2 2006.201.14:01:28.00#ibcon#flushed, iclass 24, count 2 2006.201.14:01:28.00#ibcon#about to write, iclass 24, count 2 2006.201.14:01:28.00#ibcon#wrote, iclass 24, count 2 2006.201.14:01:28.00#ibcon#about to read 3, iclass 24, count 2 2006.201.14:01:28.03#ibcon#read 3, iclass 24, count 2 2006.201.14:01:28.03#ibcon#about to read 4, iclass 24, count 2 2006.201.14:01:28.03#ibcon#read 4, iclass 24, count 2 2006.201.14:01:28.03#ibcon#about to read 5, iclass 24, count 2 2006.201.14:01:28.03#ibcon#read 5, iclass 24, count 2 2006.201.14:01:28.03#ibcon#about to read 6, iclass 24, count 2 2006.201.14:01:28.03#ibcon#read 6, iclass 24, count 2 2006.201.14:01:28.03#ibcon#end of sib2, iclass 24, count 2 2006.201.14:01:28.03#ibcon#*after write, iclass 24, count 2 2006.201.14:01:28.03#ibcon#*before return 0, iclass 24, count 2 2006.201.14:01:28.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:28.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:01:28.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.14:01:28.03#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:28.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:28.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:28.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:28.15#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:01:28.15#ibcon#first serial, iclass 24, count 0 2006.201.14:01:28.15#ibcon#enter sib2, iclass 24, count 0 2006.201.14:01:28.15#ibcon#flushed, iclass 24, count 0 2006.201.14:01:28.15#ibcon#about to write, iclass 24, count 0 2006.201.14:01:28.15#ibcon#wrote, iclass 24, count 0 2006.201.14:01:28.15#ibcon#about to read 3, iclass 24, count 0 2006.201.14:01:28.17#ibcon#read 3, iclass 24, count 0 2006.201.14:01:28.17#ibcon#about to read 4, iclass 24, count 0 2006.201.14:01:28.17#ibcon#read 4, iclass 24, count 0 2006.201.14:01:28.17#ibcon#about to read 5, iclass 24, count 0 2006.201.14:01:28.17#ibcon#read 5, iclass 24, count 0 2006.201.14:01:28.17#ibcon#about to read 6, iclass 24, count 0 2006.201.14:01:28.17#ibcon#read 6, iclass 24, count 0 2006.201.14:01:28.17#ibcon#end of sib2, iclass 24, count 0 2006.201.14:01:28.17#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:01:28.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:01:28.17#ibcon#[27=USB\r\n] 2006.201.14:01:28.17#ibcon#*before write, iclass 24, count 0 2006.201.14:01:28.17#ibcon#enter sib2, iclass 24, count 0 2006.201.14:01:28.17#ibcon#flushed, iclass 24, count 0 2006.201.14:01:28.17#ibcon#about to write, iclass 24, count 0 2006.201.14:01:28.17#ibcon#wrote, iclass 24, count 0 2006.201.14:01:28.17#ibcon#about to read 3, iclass 24, count 0 2006.201.14:01:28.20#ibcon#read 3, iclass 24, count 0 2006.201.14:01:28.20#ibcon#about to read 4, iclass 24, count 0 2006.201.14:01:28.20#ibcon#read 4, iclass 24, count 0 2006.201.14:01:28.20#ibcon#about to read 5, iclass 24, count 0 2006.201.14:01:28.20#ibcon#read 5, iclass 24, count 0 2006.201.14:01:28.20#ibcon#about to read 6, iclass 24, count 0 2006.201.14:01:28.20#ibcon#read 6, iclass 24, count 0 2006.201.14:01:28.20#ibcon#end of sib2, iclass 24, count 0 2006.201.14:01:28.20#ibcon#*after write, iclass 24, count 0 2006.201.14:01:28.20#ibcon#*before return 0, iclass 24, count 0 2006.201.14:01:28.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:28.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:01:28.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:01:28.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:01:28.20$vck44/vblo=6,719.99 2006.201.14:01:28.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.14:01:28.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.14:01:28.20#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:28.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:28.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:28.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:28.20#ibcon#enter wrdev, iclass 26, count 0 2006.201.14:01:28.20#ibcon#first serial, iclass 26, count 0 2006.201.14:01:28.20#ibcon#enter sib2, iclass 26, count 0 2006.201.14:01:28.20#ibcon#flushed, iclass 26, count 0 2006.201.14:01:28.20#ibcon#about to write, iclass 26, count 0 2006.201.14:01:28.20#ibcon#wrote, iclass 26, count 0 2006.201.14:01:28.20#ibcon#about to read 3, iclass 26, count 0 2006.201.14:01:28.22#ibcon#read 3, iclass 26, count 0 2006.201.14:01:28.22#ibcon#about to read 4, iclass 26, count 0 2006.201.14:01:28.22#ibcon#read 4, iclass 26, count 0 2006.201.14:01:28.22#ibcon#about to read 5, iclass 26, count 0 2006.201.14:01:28.22#ibcon#read 5, iclass 26, count 0 2006.201.14:01:28.22#ibcon#about to read 6, iclass 26, count 0 2006.201.14:01:28.22#ibcon#read 6, iclass 26, count 0 2006.201.14:01:28.22#ibcon#end of sib2, iclass 26, count 0 2006.201.14:01:28.22#ibcon#*mode == 0, iclass 26, count 0 2006.201.14:01:28.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.14:01:28.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:01:28.22#ibcon#*before write, iclass 26, count 0 2006.201.14:01:28.22#ibcon#enter sib2, iclass 26, count 0 2006.201.14:01:28.22#ibcon#flushed, iclass 26, count 0 2006.201.14:01:28.22#ibcon#about to write, iclass 26, count 0 2006.201.14:01:28.22#ibcon#wrote, iclass 26, count 0 2006.201.14:01:28.22#ibcon#about to read 3, iclass 26, count 0 2006.201.14:01:28.26#ibcon#read 3, iclass 26, count 0 2006.201.14:01:28.26#ibcon#about to read 4, iclass 26, count 0 2006.201.14:01:28.26#ibcon#read 4, iclass 26, count 0 2006.201.14:01:28.26#ibcon#about to read 5, iclass 26, count 0 2006.201.14:01:28.26#ibcon#read 5, iclass 26, count 0 2006.201.14:01:28.26#ibcon#about to read 6, iclass 26, count 0 2006.201.14:01:28.26#ibcon#read 6, iclass 26, count 0 2006.201.14:01:28.26#ibcon#end of sib2, iclass 26, count 0 2006.201.14:01:28.26#ibcon#*after write, iclass 26, count 0 2006.201.14:01:28.26#ibcon#*before return 0, iclass 26, count 0 2006.201.14:01:28.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:28.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:01:28.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.14:01:28.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.14:01:28.26$vck44/vb=6,4 2006.201.14:01:28.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.14:01:28.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.14:01:28.26#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:28.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:28.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:28.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:28.32#ibcon#enter wrdev, iclass 28, count 2 2006.201.14:01:28.32#ibcon#first serial, iclass 28, count 2 2006.201.14:01:28.32#ibcon#enter sib2, iclass 28, count 2 2006.201.14:01:28.32#ibcon#flushed, iclass 28, count 2 2006.201.14:01:28.32#ibcon#about to write, iclass 28, count 2 2006.201.14:01:28.32#ibcon#wrote, iclass 28, count 2 2006.201.14:01:28.32#ibcon#about to read 3, iclass 28, count 2 2006.201.14:01:28.34#ibcon#read 3, iclass 28, count 2 2006.201.14:01:28.34#ibcon#about to read 4, iclass 28, count 2 2006.201.14:01:28.34#ibcon#read 4, iclass 28, count 2 2006.201.14:01:28.34#ibcon#about to read 5, iclass 28, count 2 2006.201.14:01:28.34#ibcon#read 5, iclass 28, count 2 2006.201.14:01:28.34#ibcon#about to read 6, iclass 28, count 2 2006.201.14:01:28.34#ibcon#read 6, iclass 28, count 2 2006.201.14:01:28.34#ibcon#end of sib2, iclass 28, count 2 2006.201.14:01:28.34#ibcon#*mode == 0, iclass 28, count 2 2006.201.14:01:28.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.14:01:28.34#ibcon#[27=AT06-04\r\n] 2006.201.14:01:28.34#ibcon#*before write, iclass 28, count 2 2006.201.14:01:28.34#ibcon#enter sib2, iclass 28, count 2 2006.201.14:01:28.34#ibcon#flushed, iclass 28, count 2 2006.201.14:01:28.34#ibcon#about to write, iclass 28, count 2 2006.201.14:01:28.34#ibcon#wrote, iclass 28, count 2 2006.201.14:01:28.34#ibcon#about to read 3, iclass 28, count 2 2006.201.14:01:28.37#ibcon#read 3, iclass 28, count 2 2006.201.14:01:28.37#ibcon#about to read 4, iclass 28, count 2 2006.201.14:01:28.37#ibcon#read 4, iclass 28, count 2 2006.201.14:01:28.37#ibcon#about to read 5, iclass 28, count 2 2006.201.14:01:28.37#ibcon#read 5, iclass 28, count 2 2006.201.14:01:28.37#ibcon#about to read 6, iclass 28, count 2 2006.201.14:01:28.37#ibcon#read 6, iclass 28, count 2 2006.201.14:01:28.37#ibcon#end of sib2, iclass 28, count 2 2006.201.14:01:28.37#ibcon#*after write, iclass 28, count 2 2006.201.14:01:28.37#ibcon#*before return 0, iclass 28, count 2 2006.201.14:01:28.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:28.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:01:28.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.14:01:28.37#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:28.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:28.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:28.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:28.49#ibcon#enter wrdev, iclass 28, count 0 2006.201.14:01:28.49#ibcon#first serial, iclass 28, count 0 2006.201.14:01:28.49#ibcon#enter sib2, iclass 28, count 0 2006.201.14:01:28.49#ibcon#flushed, iclass 28, count 0 2006.201.14:01:28.49#ibcon#about to write, iclass 28, count 0 2006.201.14:01:28.49#ibcon#wrote, iclass 28, count 0 2006.201.14:01:28.49#ibcon#about to read 3, iclass 28, count 0 2006.201.14:01:28.51#ibcon#read 3, iclass 28, count 0 2006.201.14:01:28.51#ibcon#about to read 4, iclass 28, count 0 2006.201.14:01:28.51#ibcon#read 4, iclass 28, count 0 2006.201.14:01:28.51#ibcon#about to read 5, iclass 28, count 0 2006.201.14:01:28.51#ibcon#read 5, iclass 28, count 0 2006.201.14:01:28.51#ibcon#about to read 6, iclass 28, count 0 2006.201.14:01:28.51#ibcon#read 6, iclass 28, count 0 2006.201.14:01:28.51#ibcon#end of sib2, iclass 28, count 0 2006.201.14:01:28.51#ibcon#*mode == 0, iclass 28, count 0 2006.201.14:01:28.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.14:01:28.51#ibcon#[27=USB\r\n] 2006.201.14:01:28.51#ibcon#*before write, iclass 28, count 0 2006.201.14:01:28.51#ibcon#enter sib2, iclass 28, count 0 2006.201.14:01:28.51#ibcon#flushed, iclass 28, count 0 2006.201.14:01:28.51#ibcon#about to write, iclass 28, count 0 2006.201.14:01:28.51#ibcon#wrote, iclass 28, count 0 2006.201.14:01:28.51#ibcon#about to read 3, iclass 28, count 0 2006.201.14:01:28.54#ibcon#read 3, iclass 28, count 0 2006.201.14:01:28.54#ibcon#about to read 4, iclass 28, count 0 2006.201.14:01:28.54#ibcon#read 4, iclass 28, count 0 2006.201.14:01:28.54#ibcon#about to read 5, iclass 28, count 0 2006.201.14:01:28.54#ibcon#read 5, iclass 28, count 0 2006.201.14:01:28.54#ibcon#about to read 6, iclass 28, count 0 2006.201.14:01:28.54#ibcon#read 6, iclass 28, count 0 2006.201.14:01:28.54#ibcon#end of sib2, iclass 28, count 0 2006.201.14:01:28.54#ibcon#*after write, iclass 28, count 0 2006.201.14:01:28.54#ibcon#*before return 0, iclass 28, count 0 2006.201.14:01:28.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:28.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:01:28.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.14:01:28.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.14:01:28.54$vck44/vblo=7,734.99 2006.201.14:01:28.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.14:01:28.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.14:01:28.54#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:28.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:28.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:28.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:28.54#ibcon#enter wrdev, iclass 30, count 0 2006.201.14:01:28.54#ibcon#first serial, iclass 30, count 0 2006.201.14:01:28.54#ibcon#enter sib2, iclass 30, count 0 2006.201.14:01:28.54#ibcon#flushed, iclass 30, count 0 2006.201.14:01:28.54#ibcon#about to write, iclass 30, count 0 2006.201.14:01:28.54#ibcon#wrote, iclass 30, count 0 2006.201.14:01:28.54#ibcon#about to read 3, iclass 30, count 0 2006.201.14:01:28.56#ibcon#read 3, iclass 30, count 0 2006.201.14:01:28.56#ibcon#about to read 4, iclass 30, count 0 2006.201.14:01:28.56#ibcon#read 4, iclass 30, count 0 2006.201.14:01:28.56#ibcon#about to read 5, iclass 30, count 0 2006.201.14:01:28.56#ibcon#read 5, iclass 30, count 0 2006.201.14:01:28.56#ibcon#about to read 6, iclass 30, count 0 2006.201.14:01:28.56#ibcon#read 6, iclass 30, count 0 2006.201.14:01:28.56#ibcon#end of sib2, iclass 30, count 0 2006.201.14:01:28.56#ibcon#*mode == 0, iclass 30, count 0 2006.201.14:01:28.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.14:01:28.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:01:28.56#ibcon#*before write, iclass 30, count 0 2006.201.14:01:28.56#ibcon#enter sib2, iclass 30, count 0 2006.201.14:01:28.56#ibcon#flushed, iclass 30, count 0 2006.201.14:01:28.56#ibcon#about to write, iclass 30, count 0 2006.201.14:01:28.56#ibcon#wrote, iclass 30, count 0 2006.201.14:01:28.56#ibcon#about to read 3, iclass 30, count 0 2006.201.14:01:28.60#ibcon#read 3, iclass 30, count 0 2006.201.14:01:28.60#ibcon#about to read 4, iclass 30, count 0 2006.201.14:01:28.60#ibcon#read 4, iclass 30, count 0 2006.201.14:01:28.60#ibcon#about to read 5, iclass 30, count 0 2006.201.14:01:28.60#ibcon#read 5, iclass 30, count 0 2006.201.14:01:28.60#ibcon#about to read 6, iclass 30, count 0 2006.201.14:01:28.60#ibcon#read 6, iclass 30, count 0 2006.201.14:01:28.60#ibcon#end of sib2, iclass 30, count 0 2006.201.14:01:28.60#ibcon#*after write, iclass 30, count 0 2006.201.14:01:28.60#ibcon#*before return 0, iclass 30, count 0 2006.201.14:01:28.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:28.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:01:28.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.14:01:28.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.14:01:28.60$vck44/vb=7,4 2006.201.14:01:28.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.14:01:28.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.14:01:28.60#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:28.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:28.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:28.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:28.66#ibcon#enter wrdev, iclass 32, count 2 2006.201.14:01:28.66#ibcon#first serial, iclass 32, count 2 2006.201.14:01:28.66#ibcon#enter sib2, iclass 32, count 2 2006.201.14:01:28.66#ibcon#flushed, iclass 32, count 2 2006.201.14:01:28.66#ibcon#about to write, iclass 32, count 2 2006.201.14:01:28.66#ibcon#wrote, iclass 32, count 2 2006.201.14:01:28.66#ibcon#about to read 3, iclass 32, count 2 2006.201.14:01:28.68#ibcon#read 3, iclass 32, count 2 2006.201.14:01:28.68#ibcon#about to read 4, iclass 32, count 2 2006.201.14:01:28.68#ibcon#read 4, iclass 32, count 2 2006.201.14:01:28.68#ibcon#about to read 5, iclass 32, count 2 2006.201.14:01:28.68#ibcon#read 5, iclass 32, count 2 2006.201.14:01:28.68#ibcon#about to read 6, iclass 32, count 2 2006.201.14:01:28.68#ibcon#read 6, iclass 32, count 2 2006.201.14:01:28.68#ibcon#end of sib2, iclass 32, count 2 2006.201.14:01:28.68#ibcon#*mode == 0, iclass 32, count 2 2006.201.14:01:28.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.14:01:28.68#ibcon#[27=AT07-04\r\n] 2006.201.14:01:28.68#ibcon#*before write, iclass 32, count 2 2006.201.14:01:28.68#ibcon#enter sib2, iclass 32, count 2 2006.201.14:01:28.68#ibcon#flushed, iclass 32, count 2 2006.201.14:01:28.68#ibcon#about to write, iclass 32, count 2 2006.201.14:01:28.68#ibcon#wrote, iclass 32, count 2 2006.201.14:01:28.68#ibcon#about to read 3, iclass 32, count 2 2006.201.14:01:28.71#ibcon#read 3, iclass 32, count 2 2006.201.14:01:28.71#ibcon#about to read 4, iclass 32, count 2 2006.201.14:01:28.71#ibcon#read 4, iclass 32, count 2 2006.201.14:01:28.71#ibcon#about to read 5, iclass 32, count 2 2006.201.14:01:28.71#ibcon#read 5, iclass 32, count 2 2006.201.14:01:28.71#ibcon#about to read 6, iclass 32, count 2 2006.201.14:01:28.71#ibcon#read 6, iclass 32, count 2 2006.201.14:01:28.71#ibcon#end of sib2, iclass 32, count 2 2006.201.14:01:28.71#ibcon#*after write, iclass 32, count 2 2006.201.14:01:28.71#ibcon#*before return 0, iclass 32, count 2 2006.201.14:01:28.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:28.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:01:28.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.14:01:28.71#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:28.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:28.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:28.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:28.83#ibcon#enter wrdev, iclass 32, count 0 2006.201.14:01:28.83#ibcon#first serial, iclass 32, count 0 2006.201.14:01:28.83#ibcon#enter sib2, iclass 32, count 0 2006.201.14:01:28.83#ibcon#flushed, iclass 32, count 0 2006.201.14:01:28.83#ibcon#about to write, iclass 32, count 0 2006.201.14:01:28.83#ibcon#wrote, iclass 32, count 0 2006.201.14:01:28.83#ibcon#about to read 3, iclass 32, count 0 2006.201.14:01:28.85#ibcon#read 3, iclass 32, count 0 2006.201.14:01:28.85#ibcon#about to read 4, iclass 32, count 0 2006.201.14:01:28.85#ibcon#read 4, iclass 32, count 0 2006.201.14:01:28.85#ibcon#about to read 5, iclass 32, count 0 2006.201.14:01:28.85#ibcon#read 5, iclass 32, count 0 2006.201.14:01:28.85#ibcon#about to read 6, iclass 32, count 0 2006.201.14:01:28.85#ibcon#read 6, iclass 32, count 0 2006.201.14:01:28.85#ibcon#end of sib2, iclass 32, count 0 2006.201.14:01:28.85#ibcon#*mode == 0, iclass 32, count 0 2006.201.14:01:28.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.14:01:28.85#ibcon#[27=USB\r\n] 2006.201.14:01:28.85#ibcon#*before write, iclass 32, count 0 2006.201.14:01:28.85#ibcon#enter sib2, iclass 32, count 0 2006.201.14:01:28.85#ibcon#flushed, iclass 32, count 0 2006.201.14:01:28.85#ibcon#about to write, iclass 32, count 0 2006.201.14:01:28.85#ibcon#wrote, iclass 32, count 0 2006.201.14:01:28.85#ibcon#about to read 3, iclass 32, count 0 2006.201.14:01:28.88#ibcon#read 3, iclass 32, count 0 2006.201.14:01:28.88#ibcon#about to read 4, iclass 32, count 0 2006.201.14:01:28.88#ibcon#read 4, iclass 32, count 0 2006.201.14:01:28.88#ibcon#about to read 5, iclass 32, count 0 2006.201.14:01:28.88#ibcon#read 5, iclass 32, count 0 2006.201.14:01:28.88#ibcon#about to read 6, iclass 32, count 0 2006.201.14:01:28.88#ibcon#read 6, iclass 32, count 0 2006.201.14:01:28.88#ibcon#end of sib2, iclass 32, count 0 2006.201.14:01:28.88#ibcon#*after write, iclass 32, count 0 2006.201.14:01:28.88#ibcon#*before return 0, iclass 32, count 0 2006.201.14:01:28.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:28.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:01:28.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.14:01:28.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.14:01:28.88$vck44/vblo=8,744.99 2006.201.14:01:28.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.14:01:28.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.14:01:28.88#ibcon#ireg 17 cls_cnt 0 2006.201.14:01:28.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:28.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:28.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:28.88#ibcon#enter wrdev, iclass 34, count 0 2006.201.14:01:28.88#ibcon#first serial, iclass 34, count 0 2006.201.14:01:28.88#ibcon#enter sib2, iclass 34, count 0 2006.201.14:01:28.88#ibcon#flushed, iclass 34, count 0 2006.201.14:01:28.88#ibcon#about to write, iclass 34, count 0 2006.201.14:01:28.88#ibcon#wrote, iclass 34, count 0 2006.201.14:01:28.88#ibcon#about to read 3, iclass 34, count 0 2006.201.14:01:28.90#ibcon#read 3, iclass 34, count 0 2006.201.14:01:28.90#ibcon#about to read 4, iclass 34, count 0 2006.201.14:01:28.90#ibcon#read 4, iclass 34, count 0 2006.201.14:01:28.90#ibcon#about to read 5, iclass 34, count 0 2006.201.14:01:28.90#ibcon#read 5, iclass 34, count 0 2006.201.14:01:28.90#ibcon#about to read 6, iclass 34, count 0 2006.201.14:01:28.90#ibcon#read 6, iclass 34, count 0 2006.201.14:01:28.90#ibcon#end of sib2, iclass 34, count 0 2006.201.14:01:28.90#ibcon#*mode == 0, iclass 34, count 0 2006.201.14:01:28.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.14:01:28.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:01:28.90#ibcon#*before write, iclass 34, count 0 2006.201.14:01:28.90#ibcon#enter sib2, iclass 34, count 0 2006.201.14:01:28.90#ibcon#flushed, iclass 34, count 0 2006.201.14:01:28.90#ibcon#about to write, iclass 34, count 0 2006.201.14:01:28.90#ibcon#wrote, iclass 34, count 0 2006.201.14:01:28.90#ibcon#about to read 3, iclass 34, count 0 2006.201.14:01:28.95#ibcon#read 3, iclass 34, count 0 2006.201.14:01:28.95#ibcon#about to read 4, iclass 34, count 0 2006.201.14:01:28.95#ibcon#read 4, iclass 34, count 0 2006.201.14:01:28.95#ibcon#about to read 5, iclass 34, count 0 2006.201.14:01:28.95#ibcon#read 5, iclass 34, count 0 2006.201.14:01:28.95#ibcon#about to read 6, iclass 34, count 0 2006.201.14:01:28.95#ibcon#read 6, iclass 34, count 0 2006.201.14:01:28.95#ibcon#end of sib2, iclass 34, count 0 2006.201.14:01:28.95#ibcon#*after write, iclass 34, count 0 2006.201.14:01:28.95#ibcon#*before return 0, iclass 34, count 0 2006.201.14:01:28.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:28.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:01:28.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.14:01:28.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.14:01:28.95$vck44/vb=8,4 2006.201.14:01:28.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.14:01:28.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.14:01:28.95#ibcon#ireg 11 cls_cnt 2 2006.201.14:01:28.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:29.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:29.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:29.00#ibcon#enter wrdev, iclass 36, count 2 2006.201.14:01:29.00#ibcon#first serial, iclass 36, count 2 2006.201.14:01:29.00#ibcon#enter sib2, iclass 36, count 2 2006.201.14:01:29.00#ibcon#flushed, iclass 36, count 2 2006.201.14:01:29.00#ibcon#about to write, iclass 36, count 2 2006.201.14:01:29.00#ibcon#wrote, iclass 36, count 2 2006.201.14:01:29.00#ibcon#about to read 3, iclass 36, count 2 2006.201.14:01:29.02#ibcon#read 3, iclass 36, count 2 2006.201.14:01:29.02#ibcon#about to read 4, iclass 36, count 2 2006.201.14:01:29.02#ibcon#read 4, iclass 36, count 2 2006.201.14:01:29.02#ibcon#about to read 5, iclass 36, count 2 2006.201.14:01:29.02#ibcon#read 5, iclass 36, count 2 2006.201.14:01:29.02#ibcon#about to read 6, iclass 36, count 2 2006.201.14:01:29.02#ibcon#read 6, iclass 36, count 2 2006.201.14:01:29.02#ibcon#end of sib2, iclass 36, count 2 2006.201.14:01:29.02#ibcon#*mode == 0, iclass 36, count 2 2006.201.14:01:29.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.14:01:29.02#ibcon#[27=AT08-04\r\n] 2006.201.14:01:29.02#ibcon#*before write, iclass 36, count 2 2006.201.14:01:29.02#ibcon#enter sib2, iclass 36, count 2 2006.201.14:01:29.02#ibcon#flushed, iclass 36, count 2 2006.201.14:01:29.02#ibcon#about to write, iclass 36, count 2 2006.201.14:01:29.02#ibcon#wrote, iclass 36, count 2 2006.201.14:01:29.02#ibcon#about to read 3, iclass 36, count 2 2006.201.14:01:29.05#ibcon#read 3, iclass 36, count 2 2006.201.14:01:29.05#ibcon#about to read 4, iclass 36, count 2 2006.201.14:01:29.05#ibcon#read 4, iclass 36, count 2 2006.201.14:01:29.05#ibcon#about to read 5, iclass 36, count 2 2006.201.14:01:29.05#ibcon#read 5, iclass 36, count 2 2006.201.14:01:29.05#ibcon#about to read 6, iclass 36, count 2 2006.201.14:01:29.05#ibcon#read 6, iclass 36, count 2 2006.201.14:01:29.05#ibcon#end of sib2, iclass 36, count 2 2006.201.14:01:29.05#ibcon#*after write, iclass 36, count 2 2006.201.14:01:29.05#ibcon#*before return 0, iclass 36, count 2 2006.201.14:01:29.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:29.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:01:29.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.14:01:29.05#ibcon#ireg 7 cls_cnt 0 2006.201.14:01:29.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:29.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:29.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:29.17#ibcon#enter wrdev, iclass 36, count 0 2006.201.14:01:29.17#ibcon#first serial, iclass 36, count 0 2006.201.14:01:29.17#ibcon#enter sib2, iclass 36, count 0 2006.201.14:01:29.17#ibcon#flushed, iclass 36, count 0 2006.201.14:01:29.17#ibcon#about to write, iclass 36, count 0 2006.201.14:01:29.17#ibcon#wrote, iclass 36, count 0 2006.201.14:01:29.17#ibcon#about to read 3, iclass 36, count 0 2006.201.14:01:29.20#ibcon#read 3, iclass 36, count 0 2006.201.14:01:29.20#ibcon#about to read 4, iclass 36, count 0 2006.201.14:01:29.20#ibcon#read 4, iclass 36, count 0 2006.201.14:01:29.20#ibcon#about to read 5, iclass 36, count 0 2006.201.14:01:29.20#ibcon#read 5, iclass 36, count 0 2006.201.14:01:29.20#ibcon#about to read 6, iclass 36, count 0 2006.201.14:01:29.20#ibcon#read 6, iclass 36, count 0 2006.201.14:01:29.20#ibcon#end of sib2, iclass 36, count 0 2006.201.14:01:29.20#ibcon#*mode == 0, iclass 36, count 0 2006.201.14:01:29.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.14:01:29.20#ibcon#[27=USB\r\n] 2006.201.14:01:29.20#ibcon#*before write, iclass 36, count 0 2006.201.14:01:29.20#ibcon#enter sib2, iclass 36, count 0 2006.201.14:01:29.20#ibcon#flushed, iclass 36, count 0 2006.201.14:01:29.20#ibcon#about to write, iclass 36, count 0 2006.201.14:01:29.20#ibcon#wrote, iclass 36, count 0 2006.201.14:01:29.20#ibcon#about to read 3, iclass 36, count 0 2006.201.14:01:29.23#ibcon#read 3, iclass 36, count 0 2006.201.14:01:29.23#ibcon#about to read 4, iclass 36, count 0 2006.201.14:01:29.23#ibcon#read 4, iclass 36, count 0 2006.201.14:01:29.23#ibcon#about to read 5, iclass 36, count 0 2006.201.14:01:29.23#ibcon#read 5, iclass 36, count 0 2006.201.14:01:29.23#ibcon#about to read 6, iclass 36, count 0 2006.201.14:01:29.23#ibcon#read 6, iclass 36, count 0 2006.201.14:01:29.23#ibcon#end of sib2, iclass 36, count 0 2006.201.14:01:29.23#ibcon#*after write, iclass 36, count 0 2006.201.14:01:29.23#ibcon#*before return 0, iclass 36, count 0 2006.201.14:01:29.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:29.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:01:29.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.14:01:29.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.14:01:29.23$vck44/vabw=wide 2006.201.14:01:29.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.14:01:29.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.14:01:29.23#ibcon#ireg 8 cls_cnt 0 2006.201.14:01:29.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:29.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:29.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:29.23#ibcon#enter wrdev, iclass 38, count 0 2006.201.14:01:29.23#ibcon#first serial, iclass 38, count 0 2006.201.14:01:29.23#ibcon#enter sib2, iclass 38, count 0 2006.201.14:01:29.23#ibcon#flushed, iclass 38, count 0 2006.201.14:01:29.23#ibcon#about to write, iclass 38, count 0 2006.201.14:01:29.23#ibcon#wrote, iclass 38, count 0 2006.201.14:01:29.23#ibcon#about to read 3, iclass 38, count 0 2006.201.14:01:29.25#ibcon#read 3, iclass 38, count 0 2006.201.14:01:29.25#ibcon#about to read 4, iclass 38, count 0 2006.201.14:01:29.25#ibcon#read 4, iclass 38, count 0 2006.201.14:01:29.25#ibcon#about to read 5, iclass 38, count 0 2006.201.14:01:29.25#ibcon#read 5, iclass 38, count 0 2006.201.14:01:29.25#ibcon#about to read 6, iclass 38, count 0 2006.201.14:01:29.25#ibcon#read 6, iclass 38, count 0 2006.201.14:01:29.25#ibcon#end of sib2, iclass 38, count 0 2006.201.14:01:29.25#ibcon#*mode == 0, iclass 38, count 0 2006.201.14:01:29.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.14:01:29.25#ibcon#[25=BW32\r\n] 2006.201.14:01:29.25#ibcon#*before write, iclass 38, count 0 2006.201.14:01:29.25#ibcon#enter sib2, iclass 38, count 0 2006.201.14:01:29.25#ibcon#flushed, iclass 38, count 0 2006.201.14:01:29.25#ibcon#about to write, iclass 38, count 0 2006.201.14:01:29.25#ibcon#wrote, iclass 38, count 0 2006.201.14:01:29.25#ibcon#about to read 3, iclass 38, count 0 2006.201.14:01:29.28#ibcon#read 3, iclass 38, count 0 2006.201.14:01:29.28#ibcon#about to read 4, iclass 38, count 0 2006.201.14:01:29.28#ibcon#read 4, iclass 38, count 0 2006.201.14:01:29.28#ibcon#about to read 5, iclass 38, count 0 2006.201.14:01:29.28#ibcon#read 5, iclass 38, count 0 2006.201.14:01:29.28#ibcon#about to read 6, iclass 38, count 0 2006.201.14:01:29.28#ibcon#read 6, iclass 38, count 0 2006.201.14:01:29.28#ibcon#end of sib2, iclass 38, count 0 2006.201.14:01:29.28#ibcon#*after write, iclass 38, count 0 2006.201.14:01:29.28#ibcon#*before return 0, iclass 38, count 0 2006.201.14:01:29.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:29.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:01:29.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.14:01:29.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.14:01:29.28$vck44/vbbw=wide 2006.201.14:01:29.28#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.14:01:29.28#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.14:01:29.28#ibcon#ireg 8 cls_cnt 0 2006.201.14:01:29.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:01:29.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:01:29.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:01:29.35#ibcon#enter wrdev, iclass 40, count 0 2006.201.14:01:29.35#ibcon#first serial, iclass 40, count 0 2006.201.14:01:29.35#ibcon#enter sib2, iclass 40, count 0 2006.201.14:01:29.35#ibcon#flushed, iclass 40, count 0 2006.201.14:01:29.35#ibcon#about to write, iclass 40, count 0 2006.201.14:01:29.35#ibcon#wrote, iclass 40, count 0 2006.201.14:01:29.35#ibcon#about to read 3, iclass 40, count 0 2006.201.14:01:29.37#ibcon#read 3, iclass 40, count 0 2006.201.14:01:29.37#ibcon#about to read 4, iclass 40, count 0 2006.201.14:01:29.37#ibcon#read 4, iclass 40, count 0 2006.201.14:01:29.37#ibcon#about to read 5, iclass 40, count 0 2006.201.14:01:29.37#ibcon#read 5, iclass 40, count 0 2006.201.14:01:29.37#ibcon#about to read 6, iclass 40, count 0 2006.201.14:01:29.37#ibcon#read 6, iclass 40, count 0 2006.201.14:01:29.37#ibcon#end of sib2, iclass 40, count 0 2006.201.14:01:29.37#ibcon#*mode == 0, iclass 40, count 0 2006.201.14:01:29.37#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.14:01:29.37#ibcon#[27=BW32\r\n] 2006.201.14:01:29.37#ibcon#*before write, iclass 40, count 0 2006.201.14:01:29.37#ibcon#enter sib2, iclass 40, count 0 2006.201.14:01:29.37#ibcon#flushed, iclass 40, count 0 2006.201.14:01:29.37#ibcon#about to write, iclass 40, count 0 2006.201.14:01:29.37#ibcon#wrote, iclass 40, count 0 2006.201.14:01:29.37#ibcon#about to read 3, iclass 40, count 0 2006.201.14:01:29.40#ibcon#read 3, iclass 40, count 0 2006.201.14:01:29.40#ibcon#about to read 4, iclass 40, count 0 2006.201.14:01:29.40#ibcon#read 4, iclass 40, count 0 2006.201.14:01:29.40#ibcon#about to read 5, iclass 40, count 0 2006.201.14:01:29.40#ibcon#read 5, iclass 40, count 0 2006.201.14:01:29.40#ibcon#about to read 6, iclass 40, count 0 2006.201.14:01:29.40#ibcon#read 6, iclass 40, count 0 2006.201.14:01:29.40#ibcon#end of sib2, iclass 40, count 0 2006.201.14:01:29.40#ibcon#*after write, iclass 40, count 0 2006.201.14:01:29.40#ibcon#*before return 0, iclass 40, count 0 2006.201.14:01:29.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:01:29.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:01:29.40#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.14:01:29.40#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.14:01:29.40$setupk4/ifdk4 2006.201.14:01:29.40$ifdk4/lo= 2006.201.14:01:29.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:01:29.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:01:29.40$ifdk4/patch= 2006.201.14:01:29.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:01:29.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:01:29.40$setupk4/!*+20s 2006.201.14:01:34.12#abcon#<5=/04 1.2 2.3 20.871001004.0\r\n> 2006.201.14:01:34.14#abcon#{5=INTERFACE CLEAR} 2006.201.14:01:34.20#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:01:43.87$setupk4/"tpicd 2006.201.14:01:43.87$setupk4/echo=off 2006.201.14:01:43.87$setupk4/xlog=off 2006.201.14:01:43.87:!2006.201.14:02:51 2006.201.14:01:56.14#trakl#Source acquired 2006.201.14:01:58.14#flagr#flagr/antenna,acquired 2006.201.14:02:51.00:preob 2006.201.14:02:51.14/onsource/TRACKING 2006.201.14:02:51.14:!2006.201.14:03:01 2006.201.14:03:01.00:"tape 2006.201.14:03:01.00:"st=record 2006.201.14:03:01.00:data_valid=on 2006.201.14:03:01.00:midob 2006.201.14:03:01.14/onsource/TRACKING 2006.201.14:03:01.14/wx/20.86,1003.9,100 2006.201.14:03:01.36/cable/+6.4766E-03 2006.201.14:03:02.45/va/01,08,usb,yes,28,30 2006.201.14:03:02.45/va/02,07,usb,yes,30,31 2006.201.14:03:02.45/va/03,08,usb,yes,27,28 2006.201.14:03:02.45/va/04,07,usb,yes,31,33 2006.201.14:03:02.45/va/05,04,usb,yes,27,28 2006.201.14:03:02.45/va/06,05,usb,yes,27,27 2006.201.14:03:02.45/va/07,05,usb,yes,27,28 2006.201.14:03:02.45/va/08,04,usb,yes,26,32 2006.201.14:03:02.68/valo/01,524.99,yes,locked 2006.201.14:03:02.68/valo/02,534.99,yes,locked 2006.201.14:03:02.68/valo/03,564.99,yes,locked 2006.201.14:03:02.68/valo/04,624.99,yes,locked 2006.201.14:03:02.68/valo/05,734.99,yes,locked 2006.201.14:03:02.68/valo/06,814.99,yes,locked 2006.201.14:03:02.68/valo/07,864.99,yes,locked 2006.201.14:03:02.68/valo/08,884.99,yes,locked 2006.201.14:03:03.77/vb/01,04,usb,yes,28,26 2006.201.14:03:03.77/vb/02,05,usb,yes,27,26 2006.201.14:03:03.77/vb/03,04,usb,yes,27,30 2006.201.14:03:03.77/vb/04,05,usb,yes,28,27 2006.201.14:03:03.77/vb/05,04,usb,yes,24,27 2006.201.14:03:03.77/vb/06,04,usb,yes,28,25 2006.201.14:03:03.77/vb/07,04,usb,yes,28,28 2006.201.14:03:03.77/vb/08,04,usb,yes,26,29 2006.201.14:03:04.01/vblo/01,629.99,yes,locked 2006.201.14:03:04.01/vblo/02,634.99,yes,locked 2006.201.14:03:04.01/vblo/03,649.99,yes,locked 2006.201.14:03:04.01/vblo/04,679.99,yes,locked 2006.201.14:03:04.01/vblo/05,709.99,yes,locked 2006.201.14:03:04.01/vblo/06,719.99,yes,locked 2006.201.14:03:04.01/vblo/07,734.99,yes,locked 2006.201.14:03:04.01/vblo/08,744.99,yes,locked 2006.201.14:03:04.16/vabw/8 2006.201.14:03:04.31/vbbw/8 2006.201.14:03:04.40/xfe/off,on,14.5 2006.201.14:03:04.80/ifatt/23,28,28,28 2006.201.14:03:05.05/fmout-gps/S +4.52E-07 2006.201.14:03:05.12:!2006.201.14:14:51 2006.201.14:14:51.00:data_valid=off 2006.201.14:14:51.00:"et 2006.201.14:14:51.00:!+3s 2006.201.14:14:54.02:"tape 2006.201.14:14:54.02:postob 2006.201.14:14:54.13/cable/+6.4758E-03 2006.201.14:14:54.13/wx/20.85,1003.5,100 2006.201.14:14:54.20/fmout-gps/S +4.55E-07 2006.201.14:14:54.20:scan_name=201-1416,jd0607,40 2006.201.14:14:54.21:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.201.14:14:55.14#flagr#flagr/antenna,new-source 2006.201.14:14:55.14:checkk5 2006.201.14:14:55.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:14:55.92/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:14:56.31/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:14:56.69/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:14:57.36/chk_obsdata//k5ts1/T2011403??a.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.201.14:14:58.03/chk_obsdata//k5ts2/T2011403??b.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.201.14:14:58.71/chk_obsdata//k5ts3/T2011403??c.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.201.14:14:59.40/chk_obsdata//k5ts4/T2011403??d.dat file size is correct (nominal:2840MB, actual:2836MB). 2006.201.14:15:00.10/k5log//k5ts1_log_newline 2006.201.14:15:00.79/k5log//k5ts2_log_newline 2006.201.14:15:01.47/k5log//k5ts3_log_newline 2006.201.14:15:02.15/k5log//k5ts4_log_newline 2006.201.14:15:02.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:15:02.21:setupk4=1 2006.201.14:15:02.21$setupk4/echo=on 2006.201.14:15:02.21$setupk4/pcalon 2006.201.14:15:02.21$pcalon/"no phase cal control is implemented here 2006.201.14:15:02.21$setupk4/"tpicd=stop 2006.201.14:15:02.21$setupk4/"rec=synch_on 2006.201.14:15:02.21$setupk4/"rec_mode=128 2006.201.14:15:02.21$setupk4/!* 2006.201.14:15:02.21$setupk4/recpk4 2006.201.14:15:02.21$recpk4/recpatch= 2006.201.14:15:02.21$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:15:02.21$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:15:02.21$setupk4/vck44 2006.201.14:15:02.21$vck44/valo=1,524.99 2006.201.14:15:02.21#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.14:15:02.21#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.14:15:02.21#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:02.21#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:02.21#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:02.21#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:02.21#ibcon#enter wrdev, iclass 2, count 0 2006.201.14:15:02.21#ibcon#first serial, iclass 2, count 0 2006.201.14:15:02.21#ibcon#enter sib2, iclass 2, count 0 2006.201.14:15:02.21#ibcon#flushed, iclass 2, count 0 2006.201.14:15:02.21#ibcon#about to write, iclass 2, count 0 2006.201.14:15:02.21#ibcon#wrote, iclass 2, count 0 2006.201.14:15:02.21#ibcon#about to read 3, iclass 2, count 0 2006.201.14:15:02.23#ibcon#read 3, iclass 2, count 0 2006.201.14:15:02.23#ibcon#about to read 4, iclass 2, count 0 2006.201.14:15:02.23#ibcon#read 4, iclass 2, count 0 2006.201.14:15:02.23#ibcon#about to read 5, iclass 2, count 0 2006.201.14:15:02.23#ibcon#read 5, iclass 2, count 0 2006.201.14:15:02.23#ibcon#about to read 6, iclass 2, count 0 2006.201.14:15:02.23#ibcon#read 6, iclass 2, count 0 2006.201.14:15:02.23#ibcon#end of sib2, iclass 2, count 0 2006.201.14:15:02.23#ibcon#*mode == 0, iclass 2, count 0 2006.201.14:15:02.23#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.14:15:02.23#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:15:02.23#ibcon#*before write, iclass 2, count 0 2006.201.14:15:02.23#ibcon#enter sib2, iclass 2, count 0 2006.201.14:15:02.23#ibcon#flushed, iclass 2, count 0 2006.201.14:15:02.23#ibcon#about to write, iclass 2, count 0 2006.201.14:15:02.23#ibcon#wrote, iclass 2, count 0 2006.201.14:15:02.23#ibcon#about to read 3, iclass 2, count 0 2006.201.14:15:02.28#ibcon#read 3, iclass 2, count 0 2006.201.14:15:02.28#ibcon#about to read 4, iclass 2, count 0 2006.201.14:15:02.28#ibcon#read 4, iclass 2, count 0 2006.201.14:15:02.28#ibcon#about to read 5, iclass 2, count 0 2006.201.14:15:02.28#ibcon#read 5, iclass 2, count 0 2006.201.14:15:02.28#ibcon#about to read 6, iclass 2, count 0 2006.201.14:15:02.28#ibcon#read 6, iclass 2, count 0 2006.201.14:15:02.28#ibcon#end of sib2, iclass 2, count 0 2006.201.14:15:02.28#ibcon#*after write, iclass 2, count 0 2006.201.14:15:02.28#ibcon#*before return 0, iclass 2, count 0 2006.201.14:15:02.28#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:02.28#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:02.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.14:15:02.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.14:15:02.28$vck44/va=1,8 2006.201.14:15:02.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.14:15:02.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.14:15:02.28#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:02.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:02.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:02.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:02.28#ibcon#enter wrdev, iclass 5, count 2 2006.201.14:15:02.28#ibcon#first serial, iclass 5, count 2 2006.201.14:15:02.28#ibcon#enter sib2, iclass 5, count 2 2006.201.14:15:02.28#ibcon#flushed, iclass 5, count 2 2006.201.14:15:02.28#ibcon#about to write, iclass 5, count 2 2006.201.14:15:02.28#ibcon#wrote, iclass 5, count 2 2006.201.14:15:02.28#ibcon#about to read 3, iclass 5, count 2 2006.201.14:15:02.30#ibcon#read 3, iclass 5, count 2 2006.201.14:15:02.30#ibcon#about to read 4, iclass 5, count 2 2006.201.14:15:02.30#ibcon#read 4, iclass 5, count 2 2006.201.14:15:02.30#ibcon#about to read 5, iclass 5, count 2 2006.201.14:15:02.30#ibcon#read 5, iclass 5, count 2 2006.201.14:15:02.30#ibcon#about to read 6, iclass 5, count 2 2006.201.14:15:02.30#ibcon#read 6, iclass 5, count 2 2006.201.14:15:02.30#ibcon#end of sib2, iclass 5, count 2 2006.201.14:15:02.30#ibcon#*mode == 0, iclass 5, count 2 2006.201.14:15:02.30#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.14:15:02.30#ibcon#[25=AT01-08\r\n] 2006.201.14:15:02.30#ibcon#*before write, iclass 5, count 2 2006.201.14:15:02.30#ibcon#enter sib2, iclass 5, count 2 2006.201.14:15:02.30#ibcon#flushed, iclass 5, count 2 2006.201.14:15:02.30#ibcon#about to write, iclass 5, count 2 2006.201.14:15:02.30#ibcon#wrote, iclass 5, count 2 2006.201.14:15:02.30#ibcon#about to read 3, iclass 5, count 2 2006.201.14:15:02.33#ibcon#read 3, iclass 5, count 2 2006.201.14:15:02.33#ibcon#about to read 4, iclass 5, count 2 2006.201.14:15:02.33#ibcon#read 4, iclass 5, count 2 2006.201.14:15:02.33#ibcon#about to read 5, iclass 5, count 2 2006.201.14:15:02.33#ibcon#read 5, iclass 5, count 2 2006.201.14:15:02.33#ibcon#about to read 6, iclass 5, count 2 2006.201.14:15:02.33#ibcon#read 6, iclass 5, count 2 2006.201.14:15:02.33#ibcon#end of sib2, iclass 5, count 2 2006.201.14:15:02.33#ibcon#*after write, iclass 5, count 2 2006.201.14:15:02.33#ibcon#*before return 0, iclass 5, count 2 2006.201.14:15:02.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:02.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:02.33#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.14:15:02.33#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:02.33#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:02.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:02.45#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:02.45#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:15:02.45#ibcon#first serial, iclass 5, count 0 2006.201.14:15:02.45#ibcon#enter sib2, iclass 5, count 0 2006.201.14:15:02.45#ibcon#flushed, iclass 5, count 0 2006.201.14:15:02.45#ibcon#about to write, iclass 5, count 0 2006.201.14:15:02.45#ibcon#wrote, iclass 5, count 0 2006.201.14:15:02.45#ibcon#about to read 3, iclass 5, count 0 2006.201.14:15:02.47#ibcon#read 3, iclass 5, count 0 2006.201.14:15:02.47#ibcon#about to read 4, iclass 5, count 0 2006.201.14:15:02.47#ibcon#read 4, iclass 5, count 0 2006.201.14:15:02.47#ibcon#about to read 5, iclass 5, count 0 2006.201.14:15:02.47#ibcon#read 5, iclass 5, count 0 2006.201.14:15:02.47#ibcon#about to read 6, iclass 5, count 0 2006.201.14:15:02.47#ibcon#read 6, iclass 5, count 0 2006.201.14:15:02.47#ibcon#end of sib2, iclass 5, count 0 2006.201.14:15:02.47#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:15:02.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:15:02.47#ibcon#[25=USB\r\n] 2006.201.14:15:02.47#ibcon#*before write, iclass 5, count 0 2006.201.14:15:02.47#ibcon#enter sib2, iclass 5, count 0 2006.201.14:15:02.47#ibcon#flushed, iclass 5, count 0 2006.201.14:15:02.47#ibcon#about to write, iclass 5, count 0 2006.201.14:15:02.47#ibcon#wrote, iclass 5, count 0 2006.201.14:15:02.47#ibcon#about to read 3, iclass 5, count 0 2006.201.14:15:02.50#ibcon#read 3, iclass 5, count 0 2006.201.14:15:02.50#ibcon#about to read 4, iclass 5, count 0 2006.201.14:15:02.50#ibcon#read 4, iclass 5, count 0 2006.201.14:15:02.50#ibcon#about to read 5, iclass 5, count 0 2006.201.14:15:02.50#ibcon#read 5, iclass 5, count 0 2006.201.14:15:02.50#ibcon#about to read 6, iclass 5, count 0 2006.201.14:15:02.50#ibcon#read 6, iclass 5, count 0 2006.201.14:15:02.50#ibcon#end of sib2, iclass 5, count 0 2006.201.14:15:02.50#ibcon#*after write, iclass 5, count 0 2006.201.14:15:02.50#ibcon#*before return 0, iclass 5, count 0 2006.201.14:15:02.50#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:02.50#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:02.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:15:02.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:15:02.50$vck44/valo=2,534.99 2006.201.14:15:02.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.14:15:02.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.14:15:02.50#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:02.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:02.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:02.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:02.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:15:02.50#ibcon#first serial, iclass 7, count 0 2006.201.14:15:02.50#ibcon#enter sib2, iclass 7, count 0 2006.201.14:15:02.50#ibcon#flushed, iclass 7, count 0 2006.201.14:15:02.50#ibcon#about to write, iclass 7, count 0 2006.201.14:15:02.50#ibcon#wrote, iclass 7, count 0 2006.201.14:15:02.50#ibcon#about to read 3, iclass 7, count 0 2006.201.14:15:02.52#ibcon#read 3, iclass 7, count 0 2006.201.14:15:02.52#ibcon#about to read 4, iclass 7, count 0 2006.201.14:15:02.52#ibcon#read 4, iclass 7, count 0 2006.201.14:15:02.52#ibcon#about to read 5, iclass 7, count 0 2006.201.14:15:02.52#ibcon#read 5, iclass 7, count 0 2006.201.14:15:02.52#ibcon#about to read 6, iclass 7, count 0 2006.201.14:15:02.52#ibcon#read 6, iclass 7, count 0 2006.201.14:15:02.52#ibcon#end of sib2, iclass 7, count 0 2006.201.14:15:02.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:15:02.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:15:02.52#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:15:02.52#ibcon#*before write, iclass 7, count 0 2006.201.14:15:02.52#ibcon#enter sib2, iclass 7, count 0 2006.201.14:15:02.52#ibcon#flushed, iclass 7, count 0 2006.201.14:15:02.52#ibcon#about to write, iclass 7, count 0 2006.201.14:15:02.52#ibcon#wrote, iclass 7, count 0 2006.201.14:15:02.52#ibcon#about to read 3, iclass 7, count 0 2006.201.14:15:02.57#ibcon#read 3, iclass 7, count 0 2006.201.14:15:02.57#ibcon#about to read 4, iclass 7, count 0 2006.201.14:15:02.57#ibcon#read 4, iclass 7, count 0 2006.201.14:15:02.57#ibcon#about to read 5, iclass 7, count 0 2006.201.14:15:02.57#ibcon#read 5, iclass 7, count 0 2006.201.14:15:02.57#ibcon#about to read 6, iclass 7, count 0 2006.201.14:15:02.57#ibcon#read 6, iclass 7, count 0 2006.201.14:15:02.57#ibcon#end of sib2, iclass 7, count 0 2006.201.14:15:02.57#ibcon#*after write, iclass 7, count 0 2006.201.14:15:02.57#ibcon#*before return 0, iclass 7, count 0 2006.201.14:15:02.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:02.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:02.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:15:02.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:15:02.57$vck44/va=2,7 2006.201.14:15:02.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.14:15:02.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.14:15:02.57#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:02.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:02.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:02.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:02.62#ibcon#enter wrdev, iclass 11, count 2 2006.201.14:15:02.62#ibcon#first serial, iclass 11, count 2 2006.201.14:15:02.62#ibcon#enter sib2, iclass 11, count 2 2006.201.14:15:02.62#ibcon#flushed, iclass 11, count 2 2006.201.14:15:02.62#ibcon#about to write, iclass 11, count 2 2006.201.14:15:02.62#ibcon#wrote, iclass 11, count 2 2006.201.14:15:02.62#ibcon#about to read 3, iclass 11, count 2 2006.201.14:15:02.64#ibcon#read 3, iclass 11, count 2 2006.201.14:15:02.64#ibcon#about to read 4, iclass 11, count 2 2006.201.14:15:02.64#ibcon#read 4, iclass 11, count 2 2006.201.14:15:02.64#ibcon#about to read 5, iclass 11, count 2 2006.201.14:15:02.64#ibcon#read 5, iclass 11, count 2 2006.201.14:15:02.64#ibcon#about to read 6, iclass 11, count 2 2006.201.14:15:02.64#ibcon#read 6, iclass 11, count 2 2006.201.14:15:02.64#ibcon#end of sib2, iclass 11, count 2 2006.201.14:15:02.64#ibcon#*mode == 0, iclass 11, count 2 2006.201.14:15:02.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.14:15:02.64#ibcon#[25=AT02-07\r\n] 2006.201.14:15:02.64#ibcon#*before write, iclass 11, count 2 2006.201.14:15:02.64#ibcon#enter sib2, iclass 11, count 2 2006.201.14:15:02.64#ibcon#flushed, iclass 11, count 2 2006.201.14:15:02.64#ibcon#about to write, iclass 11, count 2 2006.201.14:15:02.64#ibcon#wrote, iclass 11, count 2 2006.201.14:15:02.64#ibcon#about to read 3, iclass 11, count 2 2006.201.14:15:02.67#ibcon#read 3, iclass 11, count 2 2006.201.14:15:02.67#ibcon#about to read 4, iclass 11, count 2 2006.201.14:15:02.67#ibcon#read 4, iclass 11, count 2 2006.201.14:15:02.67#ibcon#about to read 5, iclass 11, count 2 2006.201.14:15:02.67#ibcon#read 5, iclass 11, count 2 2006.201.14:15:02.67#ibcon#about to read 6, iclass 11, count 2 2006.201.14:15:02.67#ibcon#read 6, iclass 11, count 2 2006.201.14:15:02.67#ibcon#end of sib2, iclass 11, count 2 2006.201.14:15:02.67#ibcon#*after write, iclass 11, count 2 2006.201.14:15:02.67#ibcon#*before return 0, iclass 11, count 2 2006.201.14:15:02.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:02.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:02.67#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.14:15:02.67#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:02.67#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:02.79#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:02.79#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:02.79#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:15:02.79#ibcon#first serial, iclass 11, count 0 2006.201.14:15:02.79#ibcon#enter sib2, iclass 11, count 0 2006.201.14:15:02.79#ibcon#flushed, iclass 11, count 0 2006.201.14:15:02.79#ibcon#about to write, iclass 11, count 0 2006.201.14:15:02.79#ibcon#wrote, iclass 11, count 0 2006.201.14:15:02.79#ibcon#about to read 3, iclass 11, count 0 2006.201.14:15:02.81#ibcon#read 3, iclass 11, count 0 2006.201.14:15:02.81#ibcon#about to read 4, iclass 11, count 0 2006.201.14:15:02.81#ibcon#read 4, iclass 11, count 0 2006.201.14:15:02.81#ibcon#about to read 5, iclass 11, count 0 2006.201.14:15:02.81#ibcon#read 5, iclass 11, count 0 2006.201.14:15:02.81#ibcon#about to read 6, iclass 11, count 0 2006.201.14:15:02.81#ibcon#read 6, iclass 11, count 0 2006.201.14:15:02.81#ibcon#end of sib2, iclass 11, count 0 2006.201.14:15:02.81#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:15:02.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:15:02.81#ibcon#[25=USB\r\n] 2006.201.14:15:02.81#ibcon#*before write, iclass 11, count 0 2006.201.14:15:02.81#ibcon#enter sib2, iclass 11, count 0 2006.201.14:15:02.81#ibcon#flushed, iclass 11, count 0 2006.201.14:15:02.81#ibcon#about to write, iclass 11, count 0 2006.201.14:15:02.81#ibcon#wrote, iclass 11, count 0 2006.201.14:15:02.81#ibcon#about to read 3, iclass 11, count 0 2006.201.14:15:02.84#ibcon#read 3, iclass 11, count 0 2006.201.14:15:02.84#ibcon#about to read 4, iclass 11, count 0 2006.201.14:15:02.84#ibcon#read 4, iclass 11, count 0 2006.201.14:15:02.84#ibcon#about to read 5, iclass 11, count 0 2006.201.14:15:02.84#ibcon#read 5, iclass 11, count 0 2006.201.14:15:02.84#ibcon#about to read 6, iclass 11, count 0 2006.201.14:15:02.84#ibcon#read 6, iclass 11, count 0 2006.201.14:15:02.84#ibcon#end of sib2, iclass 11, count 0 2006.201.14:15:02.84#ibcon#*after write, iclass 11, count 0 2006.201.14:15:02.84#ibcon#*before return 0, iclass 11, count 0 2006.201.14:15:02.84#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:02.84#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:02.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:15:02.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:15:02.84$vck44/valo=3,564.99 2006.201.14:15:02.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.14:15:02.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.14:15:02.84#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:02.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:02.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:02.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:02.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:15:02.84#ibcon#first serial, iclass 13, count 0 2006.201.14:15:02.84#ibcon#enter sib2, iclass 13, count 0 2006.201.14:15:02.84#ibcon#flushed, iclass 13, count 0 2006.201.14:15:02.84#ibcon#about to write, iclass 13, count 0 2006.201.14:15:02.84#ibcon#wrote, iclass 13, count 0 2006.201.14:15:02.84#ibcon#about to read 3, iclass 13, count 0 2006.201.14:15:02.86#ibcon#read 3, iclass 13, count 0 2006.201.14:15:02.86#ibcon#about to read 4, iclass 13, count 0 2006.201.14:15:02.86#ibcon#read 4, iclass 13, count 0 2006.201.14:15:02.86#ibcon#about to read 5, iclass 13, count 0 2006.201.14:15:02.86#ibcon#read 5, iclass 13, count 0 2006.201.14:15:02.86#ibcon#about to read 6, iclass 13, count 0 2006.201.14:15:02.86#ibcon#read 6, iclass 13, count 0 2006.201.14:15:02.86#ibcon#end of sib2, iclass 13, count 0 2006.201.14:15:02.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:15:02.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:15:02.86#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:15:02.86#ibcon#*before write, iclass 13, count 0 2006.201.14:15:02.86#ibcon#enter sib2, iclass 13, count 0 2006.201.14:15:02.86#ibcon#flushed, iclass 13, count 0 2006.201.14:15:02.86#ibcon#about to write, iclass 13, count 0 2006.201.14:15:02.86#ibcon#wrote, iclass 13, count 0 2006.201.14:15:02.86#ibcon#about to read 3, iclass 13, count 0 2006.201.14:15:02.91#ibcon#read 3, iclass 13, count 0 2006.201.14:15:02.91#ibcon#about to read 4, iclass 13, count 0 2006.201.14:15:02.91#ibcon#read 4, iclass 13, count 0 2006.201.14:15:02.91#ibcon#about to read 5, iclass 13, count 0 2006.201.14:15:02.91#ibcon#read 5, iclass 13, count 0 2006.201.14:15:02.91#ibcon#about to read 6, iclass 13, count 0 2006.201.14:15:02.91#ibcon#read 6, iclass 13, count 0 2006.201.14:15:02.91#ibcon#end of sib2, iclass 13, count 0 2006.201.14:15:02.91#ibcon#*after write, iclass 13, count 0 2006.201.14:15:02.91#ibcon#*before return 0, iclass 13, count 0 2006.201.14:15:02.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:02.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:02.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:15:02.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:15:02.91$vck44/va=3,8 2006.201.14:15:02.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.14:15:02.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.14:15:02.91#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:02.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:02.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:02.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:02.96#ibcon#enter wrdev, iclass 15, count 2 2006.201.14:15:02.96#ibcon#first serial, iclass 15, count 2 2006.201.14:15:02.96#ibcon#enter sib2, iclass 15, count 2 2006.201.14:15:02.96#ibcon#flushed, iclass 15, count 2 2006.201.14:15:02.96#ibcon#about to write, iclass 15, count 2 2006.201.14:15:02.96#ibcon#wrote, iclass 15, count 2 2006.201.14:15:02.96#ibcon#about to read 3, iclass 15, count 2 2006.201.14:15:02.98#ibcon#read 3, iclass 15, count 2 2006.201.14:15:02.98#ibcon#about to read 4, iclass 15, count 2 2006.201.14:15:02.98#ibcon#read 4, iclass 15, count 2 2006.201.14:15:02.98#ibcon#about to read 5, iclass 15, count 2 2006.201.14:15:02.98#ibcon#read 5, iclass 15, count 2 2006.201.14:15:02.98#ibcon#about to read 6, iclass 15, count 2 2006.201.14:15:02.98#ibcon#read 6, iclass 15, count 2 2006.201.14:15:02.98#ibcon#end of sib2, iclass 15, count 2 2006.201.14:15:02.98#ibcon#*mode == 0, iclass 15, count 2 2006.201.14:15:02.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.14:15:02.98#ibcon#[25=AT03-08\r\n] 2006.201.14:15:02.98#ibcon#*before write, iclass 15, count 2 2006.201.14:15:02.98#ibcon#enter sib2, iclass 15, count 2 2006.201.14:15:02.98#ibcon#flushed, iclass 15, count 2 2006.201.14:15:02.98#ibcon#about to write, iclass 15, count 2 2006.201.14:15:02.98#ibcon#wrote, iclass 15, count 2 2006.201.14:15:02.98#ibcon#about to read 3, iclass 15, count 2 2006.201.14:15:03.01#ibcon#read 3, iclass 15, count 2 2006.201.14:15:03.01#ibcon#about to read 4, iclass 15, count 2 2006.201.14:15:03.01#ibcon#read 4, iclass 15, count 2 2006.201.14:15:03.01#ibcon#about to read 5, iclass 15, count 2 2006.201.14:15:03.01#ibcon#read 5, iclass 15, count 2 2006.201.14:15:03.01#ibcon#about to read 6, iclass 15, count 2 2006.201.14:15:03.01#ibcon#read 6, iclass 15, count 2 2006.201.14:15:03.01#ibcon#end of sib2, iclass 15, count 2 2006.201.14:15:03.01#ibcon#*after write, iclass 15, count 2 2006.201.14:15:03.01#ibcon#*before return 0, iclass 15, count 2 2006.201.14:15:03.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:03.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:03.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.14:15:03.01#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:03.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:03.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:03.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:03.13#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:15:03.13#ibcon#first serial, iclass 15, count 0 2006.201.14:15:03.13#ibcon#enter sib2, iclass 15, count 0 2006.201.14:15:03.13#ibcon#flushed, iclass 15, count 0 2006.201.14:15:03.13#ibcon#about to write, iclass 15, count 0 2006.201.14:15:03.13#ibcon#wrote, iclass 15, count 0 2006.201.14:15:03.13#ibcon#about to read 3, iclass 15, count 0 2006.201.14:15:03.15#ibcon#read 3, iclass 15, count 0 2006.201.14:15:03.15#ibcon#about to read 4, iclass 15, count 0 2006.201.14:15:03.15#ibcon#read 4, iclass 15, count 0 2006.201.14:15:03.15#ibcon#about to read 5, iclass 15, count 0 2006.201.14:15:03.15#ibcon#read 5, iclass 15, count 0 2006.201.14:15:03.15#ibcon#about to read 6, iclass 15, count 0 2006.201.14:15:03.15#ibcon#read 6, iclass 15, count 0 2006.201.14:15:03.15#ibcon#end of sib2, iclass 15, count 0 2006.201.14:15:03.15#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:15:03.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:15:03.15#ibcon#[25=USB\r\n] 2006.201.14:15:03.15#ibcon#*before write, iclass 15, count 0 2006.201.14:15:03.15#ibcon#enter sib2, iclass 15, count 0 2006.201.14:15:03.15#ibcon#flushed, iclass 15, count 0 2006.201.14:15:03.15#ibcon#about to write, iclass 15, count 0 2006.201.14:15:03.15#ibcon#wrote, iclass 15, count 0 2006.201.14:15:03.15#ibcon#about to read 3, iclass 15, count 0 2006.201.14:15:03.18#ibcon#read 3, iclass 15, count 0 2006.201.14:15:03.18#ibcon#about to read 4, iclass 15, count 0 2006.201.14:15:03.18#ibcon#read 4, iclass 15, count 0 2006.201.14:15:03.18#ibcon#about to read 5, iclass 15, count 0 2006.201.14:15:03.18#ibcon#read 5, iclass 15, count 0 2006.201.14:15:03.18#ibcon#about to read 6, iclass 15, count 0 2006.201.14:15:03.18#ibcon#read 6, iclass 15, count 0 2006.201.14:15:03.18#ibcon#end of sib2, iclass 15, count 0 2006.201.14:15:03.18#ibcon#*after write, iclass 15, count 0 2006.201.14:15:03.18#ibcon#*before return 0, iclass 15, count 0 2006.201.14:15:03.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:03.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:03.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:15:03.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:15:03.18$vck44/valo=4,624.99 2006.201.14:15:03.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.14:15:03.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.14:15:03.18#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:03.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:03.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:03.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:03.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:15:03.18#ibcon#first serial, iclass 17, count 0 2006.201.14:15:03.18#ibcon#enter sib2, iclass 17, count 0 2006.201.14:15:03.18#ibcon#flushed, iclass 17, count 0 2006.201.14:15:03.18#ibcon#about to write, iclass 17, count 0 2006.201.14:15:03.18#ibcon#wrote, iclass 17, count 0 2006.201.14:15:03.18#ibcon#about to read 3, iclass 17, count 0 2006.201.14:15:03.20#ibcon#read 3, iclass 17, count 0 2006.201.14:15:03.20#ibcon#about to read 4, iclass 17, count 0 2006.201.14:15:03.20#ibcon#read 4, iclass 17, count 0 2006.201.14:15:03.20#ibcon#about to read 5, iclass 17, count 0 2006.201.14:15:03.20#ibcon#read 5, iclass 17, count 0 2006.201.14:15:03.20#ibcon#about to read 6, iclass 17, count 0 2006.201.14:15:03.20#ibcon#read 6, iclass 17, count 0 2006.201.14:15:03.20#ibcon#end of sib2, iclass 17, count 0 2006.201.14:15:03.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:15:03.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:15:03.20#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:15:03.20#ibcon#*before write, iclass 17, count 0 2006.201.14:15:03.20#ibcon#enter sib2, iclass 17, count 0 2006.201.14:15:03.20#ibcon#flushed, iclass 17, count 0 2006.201.14:15:03.20#ibcon#about to write, iclass 17, count 0 2006.201.14:15:03.20#ibcon#wrote, iclass 17, count 0 2006.201.14:15:03.20#ibcon#about to read 3, iclass 17, count 0 2006.201.14:15:03.24#ibcon#read 3, iclass 17, count 0 2006.201.14:15:03.24#ibcon#about to read 4, iclass 17, count 0 2006.201.14:15:03.24#ibcon#read 4, iclass 17, count 0 2006.201.14:15:03.24#ibcon#about to read 5, iclass 17, count 0 2006.201.14:15:03.24#ibcon#read 5, iclass 17, count 0 2006.201.14:15:03.24#ibcon#about to read 6, iclass 17, count 0 2006.201.14:15:03.24#ibcon#read 6, iclass 17, count 0 2006.201.14:15:03.24#ibcon#end of sib2, iclass 17, count 0 2006.201.14:15:03.24#ibcon#*after write, iclass 17, count 0 2006.201.14:15:03.24#ibcon#*before return 0, iclass 17, count 0 2006.201.14:15:03.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:03.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:03.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:15:03.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:15:03.24$vck44/va=4,7 2006.201.14:15:03.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.14:15:03.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.14:15:03.24#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:03.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:03.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:03.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:03.30#ibcon#enter wrdev, iclass 19, count 2 2006.201.14:15:03.30#ibcon#first serial, iclass 19, count 2 2006.201.14:15:03.30#ibcon#enter sib2, iclass 19, count 2 2006.201.14:15:03.30#ibcon#flushed, iclass 19, count 2 2006.201.14:15:03.30#ibcon#about to write, iclass 19, count 2 2006.201.14:15:03.30#ibcon#wrote, iclass 19, count 2 2006.201.14:15:03.30#ibcon#about to read 3, iclass 19, count 2 2006.201.14:15:03.32#ibcon#read 3, iclass 19, count 2 2006.201.14:15:03.32#ibcon#about to read 4, iclass 19, count 2 2006.201.14:15:03.32#ibcon#read 4, iclass 19, count 2 2006.201.14:15:03.32#ibcon#about to read 5, iclass 19, count 2 2006.201.14:15:03.32#ibcon#read 5, iclass 19, count 2 2006.201.14:15:03.32#ibcon#about to read 6, iclass 19, count 2 2006.201.14:15:03.32#ibcon#read 6, iclass 19, count 2 2006.201.14:15:03.32#ibcon#end of sib2, iclass 19, count 2 2006.201.14:15:03.32#ibcon#*mode == 0, iclass 19, count 2 2006.201.14:15:03.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.14:15:03.32#ibcon#[25=AT04-07\r\n] 2006.201.14:15:03.32#ibcon#*before write, iclass 19, count 2 2006.201.14:15:03.32#ibcon#enter sib2, iclass 19, count 2 2006.201.14:15:03.32#ibcon#flushed, iclass 19, count 2 2006.201.14:15:03.32#ibcon#about to write, iclass 19, count 2 2006.201.14:15:03.32#ibcon#wrote, iclass 19, count 2 2006.201.14:15:03.32#ibcon#about to read 3, iclass 19, count 2 2006.201.14:15:03.35#ibcon#read 3, iclass 19, count 2 2006.201.14:15:03.35#ibcon#about to read 4, iclass 19, count 2 2006.201.14:15:03.35#ibcon#read 4, iclass 19, count 2 2006.201.14:15:03.35#ibcon#about to read 5, iclass 19, count 2 2006.201.14:15:03.35#ibcon#read 5, iclass 19, count 2 2006.201.14:15:03.35#ibcon#about to read 6, iclass 19, count 2 2006.201.14:15:03.35#ibcon#read 6, iclass 19, count 2 2006.201.14:15:03.35#ibcon#end of sib2, iclass 19, count 2 2006.201.14:15:03.35#ibcon#*after write, iclass 19, count 2 2006.201.14:15:03.35#ibcon#*before return 0, iclass 19, count 2 2006.201.14:15:03.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:03.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:03.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.14:15:03.35#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:03.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:03.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:03.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:03.47#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:15:03.47#ibcon#first serial, iclass 19, count 0 2006.201.14:15:03.47#ibcon#enter sib2, iclass 19, count 0 2006.201.14:15:03.47#ibcon#flushed, iclass 19, count 0 2006.201.14:15:03.47#ibcon#about to write, iclass 19, count 0 2006.201.14:15:03.47#ibcon#wrote, iclass 19, count 0 2006.201.14:15:03.47#ibcon#about to read 3, iclass 19, count 0 2006.201.14:15:03.49#ibcon#read 3, iclass 19, count 0 2006.201.14:15:03.49#ibcon#about to read 4, iclass 19, count 0 2006.201.14:15:03.49#ibcon#read 4, iclass 19, count 0 2006.201.14:15:03.49#ibcon#about to read 5, iclass 19, count 0 2006.201.14:15:03.49#ibcon#read 5, iclass 19, count 0 2006.201.14:15:03.49#ibcon#about to read 6, iclass 19, count 0 2006.201.14:15:03.49#ibcon#read 6, iclass 19, count 0 2006.201.14:15:03.49#ibcon#end of sib2, iclass 19, count 0 2006.201.14:15:03.49#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:15:03.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:15:03.49#ibcon#[25=USB\r\n] 2006.201.14:15:03.49#ibcon#*before write, iclass 19, count 0 2006.201.14:15:03.49#ibcon#enter sib2, iclass 19, count 0 2006.201.14:15:03.49#ibcon#flushed, iclass 19, count 0 2006.201.14:15:03.49#ibcon#about to write, iclass 19, count 0 2006.201.14:15:03.49#ibcon#wrote, iclass 19, count 0 2006.201.14:15:03.49#ibcon#about to read 3, iclass 19, count 0 2006.201.14:15:03.52#ibcon#read 3, iclass 19, count 0 2006.201.14:15:03.52#ibcon#about to read 4, iclass 19, count 0 2006.201.14:15:03.52#ibcon#read 4, iclass 19, count 0 2006.201.14:15:03.52#ibcon#about to read 5, iclass 19, count 0 2006.201.14:15:03.52#ibcon#read 5, iclass 19, count 0 2006.201.14:15:03.52#ibcon#about to read 6, iclass 19, count 0 2006.201.14:15:03.52#ibcon#read 6, iclass 19, count 0 2006.201.14:15:03.52#ibcon#end of sib2, iclass 19, count 0 2006.201.14:15:03.52#ibcon#*after write, iclass 19, count 0 2006.201.14:15:03.52#ibcon#*before return 0, iclass 19, count 0 2006.201.14:15:03.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:03.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:03.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:15:03.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:15:03.52$vck44/valo=5,734.99 2006.201.14:15:03.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.14:15:03.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.14:15:03.52#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:03.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:03.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:03.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:03.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:15:03.52#ibcon#first serial, iclass 21, count 0 2006.201.14:15:03.52#ibcon#enter sib2, iclass 21, count 0 2006.201.14:15:03.52#ibcon#flushed, iclass 21, count 0 2006.201.14:15:03.52#ibcon#about to write, iclass 21, count 0 2006.201.14:15:03.52#ibcon#wrote, iclass 21, count 0 2006.201.14:15:03.52#ibcon#about to read 3, iclass 21, count 0 2006.201.14:15:03.54#ibcon#read 3, iclass 21, count 0 2006.201.14:15:03.54#ibcon#about to read 4, iclass 21, count 0 2006.201.14:15:03.54#ibcon#read 4, iclass 21, count 0 2006.201.14:15:03.54#ibcon#about to read 5, iclass 21, count 0 2006.201.14:15:03.54#ibcon#read 5, iclass 21, count 0 2006.201.14:15:03.54#ibcon#about to read 6, iclass 21, count 0 2006.201.14:15:03.54#ibcon#read 6, iclass 21, count 0 2006.201.14:15:03.54#ibcon#end of sib2, iclass 21, count 0 2006.201.14:15:03.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:15:03.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:15:03.54#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:15:03.54#ibcon#*before write, iclass 21, count 0 2006.201.14:15:03.54#ibcon#enter sib2, iclass 21, count 0 2006.201.14:15:03.54#ibcon#flushed, iclass 21, count 0 2006.201.14:15:03.54#ibcon#about to write, iclass 21, count 0 2006.201.14:15:03.54#ibcon#wrote, iclass 21, count 0 2006.201.14:15:03.54#ibcon#about to read 3, iclass 21, count 0 2006.201.14:15:03.58#ibcon#read 3, iclass 21, count 0 2006.201.14:15:03.58#ibcon#about to read 4, iclass 21, count 0 2006.201.14:15:03.58#ibcon#read 4, iclass 21, count 0 2006.201.14:15:03.58#ibcon#about to read 5, iclass 21, count 0 2006.201.14:15:03.58#ibcon#read 5, iclass 21, count 0 2006.201.14:15:03.58#ibcon#about to read 6, iclass 21, count 0 2006.201.14:15:03.58#ibcon#read 6, iclass 21, count 0 2006.201.14:15:03.58#ibcon#end of sib2, iclass 21, count 0 2006.201.14:15:03.58#ibcon#*after write, iclass 21, count 0 2006.201.14:15:03.58#ibcon#*before return 0, iclass 21, count 0 2006.201.14:15:03.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:03.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:03.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:15:03.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:15:03.58$vck44/va=5,4 2006.201.14:15:03.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.14:15:03.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.14:15:03.58#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:03.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:03.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:03.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:03.64#ibcon#enter wrdev, iclass 23, count 2 2006.201.14:15:03.64#ibcon#first serial, iclass 23, count 2 2006.201.14:15:03.64#ibcon#enter sib2, iclass 23, count 2 2006.201.14:15:03.64#ibcon#flushed, iclass 23, count 2 2006.201.14:15:03.64#ibcon#about to write, iclass 23, count 2 2006.201.14:15:03.64#ibcon#wrote, iclass 23, count 2 2006.201.14:15:03.64#ibcon#about to read 3, iclass 23, count 2 2006.201.14:15:03.66#ibcon#read 3, iclass 23, count 2 2006.201.14:15:03.66#ibcon#about to read 4, iclass 23, count 2 2006.201.14:15:03.66#ibcon#read 4, iclass 23, count 2 2006.201.14:15:03.66#ibcon#about to read 5, iclass 23, count 2 2006.201.14:15:03.66#ibcon#read 5, iclass 23, count 2 2006.201.14:15:03.66#ibcon#about to read 6, iclass 23, count 2 2006.201.14:15:03.66#ibcon#read 6, iclass 23, count 2 2006.201.14:15:03.66#ibcon#end of sib2, iclass 23, count 2 2006.201.14:15:03.66#ibcon#*mode == 0, iclass 23, count 2 2006.201.14:15:03.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.14:15:03.66#ibcon#[25=AT05-04\r\n] 2006.201.14:15:03.66#ibcon#*before write, iclass 23, count 2 2006.201.14:15:03.66#ibcon#enter sib2, iclass 23, count 2 2006.201.14:15:03.66#ibcon#flushed, iclass 23, count 2 2006.201.14:15:03.66#ibcon#about to write, iclass 23, count 2 2006.201.14:15:03.66#ibcon#wrote, iclass 23, count 2 2006.201.14:15:03.66#ibcon#about to read 3, iclass 23, count 2 2006.201.14:15:03.69#ibcon#read 3, iclass 23, count 2 2006.201.14:15:03.69#ibcon#about to read 4, iclass 23, count 2 2006.201.14:15:03.69#ibcon#read 4, iclass 23, count 2 2006.201.14:15:03.69#ibcon#about to read 5, iclass 23, count 2 2006.201.14:15:03.69#ibcon#read 5, iclass 23, count 2 2006.201.14:15:03.69#ibcon#about to read 6, iclass 23, count 2 2006.201.14:15:03.69#ibcon#read 6, iclass 23, count 2 2006.201.14:15:03.69#ibcon#end of sib2, iclass 23, count 2 2006.201.14:15:03.69#ibcon#*after write, iclass 23, count 2 2006.201.14:15:03.69#ibcon#*before return 0, iclass 23, count 2 2006.201.14:15:03.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:03.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:03.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.14:15:03.69#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:03.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:03.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:03.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:03.81#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:15:03.81#ibcon#first serial, iclass 23, count 0 2006.201.14:15:03.81#ibcon#enter sib2, iclass 23, count 0 2006.201.14:15:03.81#ibcon#flushed, iclass 23, count 0 2006.201.14:15:03.81#ibcon#about to write, iclass 23, count 0 2006.201.14:15:03.81#ibcon#wrote, iclass 23, count 0 2006.201.14:15:03.81#ibcon#about to read 3, iclass 23, count 0 2006.201.14:15:03.83#ibcon#read 3, iclass 23, count 0 2006.201.14:15:03.83#ibcon#about to read 4, iclass 23, count 0 2006.201.14:15:03.83#ibcon#read 4, iclass 23, count 0 2006.201.14:15:03.83#ibcon#about to read 5, iclass 23, count 0 2006.201.14:15:03.83#ibcon#read 5, iclass 23, count 0 2006.201.14:15:03.83#ibcon#about to read 6, iclass 23, count 0 2006.201.14:15:03.83#ibcon#read 6, iclass 23, count 0 2006.201.14:15:03.83#ibcon#end of sib2, iclass 23, count 0 2006.201.14:15:03.83#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:15:03.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:15:03.83#ibcon#[25=USB\r\n] 2006.201.14:15:03.83#ibcon#*before write, iclass 23, count 0 2006.201.14:15:03.83#ibcon#enter sib2, iclass 23, count 0 2006.201.14:15:03.83#ibcon#flushed, iclass 23, count 0 2006.201.14:15:03.83#ibcon#about to write, iclass 23, count 0 2006.201.14:15:03.83#ibcon#wrote, iclass 23, count 0 2006.201.14:15:03.83#ibcon#about to read 3, iclass 23, count 0 2006.201.14:15:03.86#ibcon#read 3, iclass 23, count 0 2006.201.14:15:03.86#ibcon#about to read 4, iclass 23, count 0 2006.201.14:15:03.86#ibcon#read 4, iclass 23, count 0 2006.201.14:15:03.86#ibcon#about to read 5, iclass 23, count 0 2006.201.14:15:03.86#ibcon#read 5, iclass 23, count 0 2006.201.14:15:03.86#ibcon#about to read 6, iclass 23, count 0 2006.201.14:15:03.86#ibcon#read 6, iclass 23, count 0 2006.201.14:15:03.86#ibcon#end of sib2, iclass 23, count 0 2006.201.14:15:03.86#ibcon#*after write, iclass 23, count 0 2006.201.14:15:03.86#ibcon#*before return 0, iclass 23, count 0 2006.201.14:15:03.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:03.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:03.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:15:03.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:15:03.86$vck44/valo=6,814.99 2006.201.14:15:03.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.14:15:03.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.14:15:03.86#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:03.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:03.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:03.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:03.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:15:03.86#ibcon#first serial, iclass 25, count 0 2006.201.14:15:03.86#ibcon#enter sib2, iclass 25, count 0 2006.201.14:15:03.86#ibcon#flushed, iclass 25, count 0 2006.201.14:15:03.86#ibcon#about to write, iclass 25, count 0 2006.201.14:15:03.86#ibcon#wrote, iclass 25, count 0 2006.201.14:15:03.86#ibcon#about to read 3, iclass 25, count 0 2006.201.14:15:03.88#ibcon#read 3, iclass 25, count 0 2006.201.14:15:03.88#ibcon#about to read 4, iclass 25, count 0 2006.201.14:15:03.88#ibcon#read 4, iclass 25, count 0 2006.201.14:15:03.88#ibcon#about to read 5, iclass 25, count 0 2006.201.14:15:03.88#ibcon#read 5, iclass 25, count 0 2006.201.14:15:03.88#ibcon#about to read 6, iclass 25, count 0 2006.201.14:15:03.88#ibcon#read 6, iclass 25, count 0 2006.201.14:15:03.88#ibcon#end of sib2, iclass 25, count 0 2006.201.14:15:03.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:15:03.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:15:03.88#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:15:03.88#ibcon#*before write, iclass 25, count 0 2006.201.14:15:03.88#ibcon#enter sib2, iclass 25, count 0 2006.201.14:15:03.88#ibcon#flushed, iclass 25, count 0 2006.201.14:15:03.88#ibcon#about to write, iclass 25, count 0 2006.201.14:15:03.88#ibcon#wrote, iclass 25, count 0 2006.201.14:15:03.88#ibcon#about to read 3, iclass 25, count 0 2006.201.14:15:03.93#ibcon#read 3, iclass 25, count 0 2006.201.14:15:03.93#ibcon#about to read 4, iclass 25, count 0 2006.201.14:15:03.93#ibcon#read 4, iclass 25, count 0 2006.201.14:15:03.93#ibcon#about to read 5, iclass 25, count 0 2006.201.14:15:03.93#ibcon#read 5, iclass 25, count 0 2006.201.14:15:03.93#ibcon#about to read 6, iclass 25, count 0 2006.201.14:15:03.93#ibcon#read 6, iclass 25, count 0 2006.201.14:15:03.93#ibcon#end of sib2, iclass 25, count 0 2006.201.14:15:03.93#ibcon#*after write, iclass 25, count 0 2006.201.14:15:03.93#ibcon#*before return 0, iclass 25, count 0 2006.201.14:15:03.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:03.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:03.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:15:03.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:15:03.93$vck44/va=6,5 2006.201.14:15:03.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.14:15:03.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.14:15:03.93#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:03.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:03.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:03.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:03.98#ibcon#enter wrdev, iclass 27, count 2 2006.201.14:15:03.98#ibcon#first serial, iclass 27, count 2 2006.201.14:15:03.98#ibcon#enter sib2, iclass 27, count 2 2006.201.14:15:03.98#ibcon#flushed, iclass 27, count 2 2006.201.14:15:03.98#ibcon#about to write, iclass 27, count 2 2006.201.14:15:03.98#ibcon#wrote, iclass 27, count 2 2006.201.14:15:03.98#ibcon#about to read 3, iclass 27, count 2 2006.201.14:15:04.00#ibcon#read 3, iclass 27, count 2 2006.201.14:15:04.00#ibcon#about to read 4, iclass 27, count 2 2006.201.14:15:04.00#ibcon#read 4, iclass 27, count 2 2006.201.14:15:04.00#ibcon#about to read 5, iclass 27, count 2 2006.201.14:15:04.00#ibcon#read 5, iclass 27, count 2 2006.201.14:15:04.00#ibcon#about to read 6, iclass 27, count 2 2006.201.14:15:04.00#ibcon#read 6, iclass 27, count 2 2006.201.14:15:04.00#ibcon#end of sib2, iclass 27, count 2 2006.201.14:15:04.00#ibcon#*mode == 0, iclass 27, count 2 2006.201.14:15:04.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.14:15:04.00#ibcon#[25=AT06-05\r\n] 2006.201.14:15:04.00#ibcon#*before write, iclass 27, count 2 2006.201.14:15:04.00#ibcon#enter sib2, iclass 27, count 2 2006.201.14:15:04.00#ibcon#flushed, iclass 27, count 2 2006.201.14:15:04.00#ibcon#about to write, iclass 27, count 2 2006.201.14:15:04.00#ibcon#wrote, iclass 27, count 2 2006.201.14:15:04.00#ibcon#about to read 3, iclass 27, count 2 2006.201.14:15:04.03#ibcon#read 3, iclass 27, count 2 2006.201.14:15:04.03#ibcon#about to read 4, iclass 27, count 2 2006.201.14:15:04.03#ibcon#read 4, iclass 27, count 2 2006.201.14:15:04.03#ibcon#about to read 5, iclass 27, count 2 2006.201.14:15:04.03#ibcon#read 5, iclass 27, count 2 2006.201.14:15:04.03#ibcon#about to read 6, iclass 27, count 2 2006.201.14:15:04.03#ibcon#read 6, iclass 27, count 2 2006.201.14:15:04.03#ibcon#end of sib2, iclass 27, count 2 2006.201.14:15:04.03#ibcon#*after write, iclass 27, count 2 2006.201.14:15:04.03#ibcon#*before return 0, iclass 27, count 2 2006.201.14:15:04.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:04.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:04.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.14:15:04.03#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:04.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:04.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:04.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:04.15#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:15:04.15#ibcon#first serial, iclass 27, count 0 2006.201.14:15:04.15#ibcon#enter sib2, iclass 27, count 0 2006.201.14:15:04.15#ibcon#flushed, iclass 27, count 0 2006.201.14:15:04.15#ibcon#about to write, iclass 27, count 0 2006.201.14:15:04.15#ibcon#wrote, iclass 27, count 0 2006.201.14:15:04.15#ibcon#about to read 3, iclass 27, count 0 2006.201.14:15:04.17#ibcon#read 3, iclass 27, count 0 2006.201.14:15:04.17#ibcon#about to read 4, iclass 27, count 0 2006.201.14:15:04.17#ibcon#read 4, iclass 27, count 0 2006.201.14:15:04.17#ibcon#about to read 5, iclass 27, count 0 2006.201.14:15:04.17#ibcon#read 5, iclass 27, count 0 2006.201.14:15:04.17#ibcon#about to read 6, iclass 27, count 0 2006.201.14:15:04.17#ibcon#read 6, iclass 27, count 0 2006.201.14:15:04.17#ibcon#end of sib2, iclass 27, count 0 2006.201.14:15:04.17#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:15:04.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:15:04.17#ibcon#[25=USB\r\n] 2006.201.14:15:04.17#ibcon#*before write, iclass 27, count 0 2006.201.14:15:04.17#ibcon#enter sib2, iclass 27, count 0 2006.201.14:15:04.17#ibcon#flushed, iclass 27, count 0 2006.201.14:15:04.17#ibcon#about to write, iclass 27, count 0 2006.201.14:15:04.17#ibcon#wrote, iclass 27, count 0 2006.201.14:15:04.17#ibcon#about to read 3, iclass 27, count 0 2006.201.14:15:04.20#ibcon#read 3, iclass 27, count 0 2006.201.14:15:04.20#ibcon#about to read 4, iclass 27, count 0 2006.201.14:15:04.20#ibcon#read 4, iclass 27, count 0 2006.201.14:15:04.20#ibcon#about to read 5, iclass 27, count 0 2006.201.14:15:04.20#ibcon#read 5, iclass 27, count 0 2006.201.14:15:04.20#ibcon#about to read 6, iclass 27, count 0 2006.201.14:15:04.20#ibcon#read 6, iclass 27, count 0 2006.201.14:15:04.20#ibcon#end of sib2, iclass 27, count 0 2006.201.14:15:04.20#ibcon#*after write, iclass 27, count 0 2006.201.14:15:04.20#ibcon#*before return 0, iclass 27, count 0 2006.201.14:15:04.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:04.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:04.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:15:04.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:15:04.20$vck44/valo=7,864.99 2006.201.14:15:04.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.14:15:04.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.14:15:04.20#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:04.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:04.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:04.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:04.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:15:04.20#ibcon#first serial, iclass 29, count 0 2006.201.14:15:04.20#ibcon#enter sib2, iclass 29, count 0 2006.201.14:15:04.20#ibcon#flushed, iclass 29, count 0 2006.201.14:15:04.20#ibcon#about to write, iclass 29, count 0 2006.201.14:15:04.20#ibcon#wrote, iclass 29, count 0 2006.201.14:15:04.20#ibcon#about to read 3, iclass 29, count 0 2006.201.14:15:04.22#ibcon#read 3, iclass 29, count 0 2006.201.14:15:04.22#ibcon#about to read 4, iclass 29, count 0 2006.201.14:15:04.22#ibcon#read 4, iclass 29, count 0 2006.201.14:15:04.22#ibcon#about to read 5, iclass 29, count 0 2006.201.14:15:04.22#ibcon#read 5, iclass 29, count 0 2006.201.14:15:04.22#ibcon#about to read 6, iclass 29, count 0 2006.201.14:15:04.22#ibcon#read 6, iclass 29, count 0 2006.201.14:15:04.22#ibcon#end of sib2, iclass 29, count 0 2006.201.14:15:04.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:15:04.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:15:04.22#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:15:04.22#ibcon#*before write, iclass 29, count 0 2006.201.14:15:04.22#ibcon#enter sib2, iclass 29, count 0 2006.201.14:15:04.22#ibcon#flushed, iclass 29, count 0 2006.201.14:15:04.22#ibcon#about to write, iclass 29, count 0 2006.201.14:15:04.22#ibcon#wrote, iclass 29, count 0 2006.201.14:15:04.22#ibcon#about to read 3, iclass 29, count 0 2006.201.14:15:04.26#ibcon#read 3, iclass 29, count 0 2006.201.14:15:04.26#ibcon#about to read 4, iclass 29, count 0 2006.201.14:15:04.26#ibcon#read 4, iclass 29, count 0 2006.201.14:15:04.26#ibcon#about to read 5, iclass 29, count 0 2006.201.14:15:04.26#ibcon#read 5, iclass 29, count 0 2006.201.14:15:04.26#ibcon#about to read 6, iclass 29, count 0 2006.201.14:15:04.26#ibcon#read 6, iclass 29, count 0 2006.201.14:15:04.26#ibcon#end of sib2, iclass 29, count 0 2006.201.14:15:04.26#ibcon#*after write, iclass 29, count 0 2006.201.14:15:04.26#ibcon#*before return 0, iclass 29, count 0 2006.201.14:15:04.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:04.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:04.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:15:04.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:15:04.26$vck44/va=7,5 2006.201.14:15:04.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.14:15:04.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.14:15:04.26#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:04.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:04.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:04.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:04.32#ibcon#enter wrdev, iclass 31, count 2 2006.201.14:15:04.32#ibcon#first serial, iclass 31, count 2 2006.201.14:15:04.32#ibcon#enter sib2, iclass 31, count 2 2006.201.14:15:04.32#ibcon#flushed, iclass 31, count 2 2006.201.14:15:04.32#ibcon#about to write, iclass 31, count 2 2006.201.14:15:04.32#ibcon#wrote, iclass 31, count 2 2006.201.14:15:04.32#ibcon#about to read 3, iclass 31, count 2 2006.201.14:15:04.34#ibcon#read 3, iclass 31, count 2 2006.201.14:15:04.34#ibcon#about to read 4, iclass 31, count 2 2006.201.14:15:04.34#ibcon#read 4, iclass 31, count 2 2006.201.14:15:04.34#ibcon#about to read 5, iclass 31, count 2 2006.201.14:15:04.34#ibcon#read 5, iclass 31, count 2 2006.201.14:15:04.34#ibcon#about to read 6, iclass 31, count 2 2006.201.14:15:04.34#ibcon#read 6, iclass 31, count 2 2006.201.14:15:04.34#ibcon#end of sib2, iclass 31, count 2 2006.201.14:15:04.34#ibcon#*mode == 0, iclass 31, count 2 2006.201.14:15:04.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.14:15:04.34#ibcon#[25=AT07-05\r\n] 2006.201.14:15:04.34#ibcon#*before write, iclass 31, count 2 2006.201.14:15:04.34#ibcon#enter sib2, iclass 31, count 2 2006.201.14:15:04.34#ibcon#flushed, iclass 31, count 2 2006.201.14:15:04.34#ibcon#about to write, iclass 31, count 2 2006.201.14:15:04.34#ibcon#wrote, iclass 31, count 2 2006.201.14:15:04.34#ibcon#about to read 3, iclass 31, count 2 2006.201.14:15:04.37#ibcon#read 3, iclass 31, count 2 2006.201.14:15:04.37#ibcon#about to read 4, iclass 31, count 2 2006.201.14:15:04.37#ibcon#read 4, iclass 31, count 2 2006.201.14:15:04.37#ibcon#about to read 5, iclass 31, count 2 2006.201.14:15:04.37#ibcon#read 5, iclass 31, count 2 2006.201.14:15:04.37#ibcon#about to read 6, iclass 31, count 2 2006.201.14:15:04.37#ibcon#read 6, iclass 31, count 2 2006.201.14:15:04.37#ibcon#end of sib2, iclass 31, count 2 2006.201.14:15:04.37#ibcon#*after write, iclass 31, count 2 2006.201.14:15:04.37#ibcon#*before return 0, iclass 31, count 2 2006.201.14:15:04.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:04.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:04.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.14:15:04.37#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:04.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:04.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:04.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:04.49#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:15:04.49#ibcon#first serial, iclass 31, count 0 2006.201.14:15:04.49#ibcon#enter sib2, iclass 31, count 0 2006.201.14:15:04.49#ibcon#flushed, iclass 31, count 0 2006.201.14:15:04.49#ibcon#about to write, iclass 31, count 0 2006.201.14:15:04.49#ibcon#wrote, iclass 31, count 0 2006.201.14:15:04.49#ibcon#about to read 3, iclass 31, count 0 2006.201.14:15:04.51#ibcon#read 3, iclass 31, count 0 2006.201.14:15:04.51#ibcon#about to read 4, iclass 31, count 0 2006.201.14:15:04.51#ibcon#read 4, iclass 31, count 0 2006.201.14:15:04.51#ibcon#about to read 5, iclass 31, count 0 2006.201.14:15:04.51#ibcon#read 5, iclass 31, count 0 2006.201.14:15:04.51#ibcon#about to read 6, iclass 31, count 0 2006.201.14:15:04.51#ibcon#read 6, iclass 31, count 0 2006.201.14:15:04.51#ibcon#end of sib2, iclass 31, count 0 2006.201.14:15:04.51#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:15:04.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:15:04.51#ibcon#[25=USB\r\n] 2006.201.14:15:04.51#ibcon#*before write, iclass 31, count 0 2006.201.14:15:04.51#ibcon#enter sib2, iclass 31, count 0 2006.201.14:15:04.51#ibcon#flushed, iclass 31, count 0 2006.201.14:15:04.51#ibcon#about to write, iclass 31, count 0 2006.201.14:15:04.51#ibcon#wrote, iclass 31, count 0 2006.201.14:15:04.51#ibcon#about to read 3, iclass 31, count 0 2006.201.14:15:04.54#ibcon#read 3, iclass 31, count 0 2006.201.14:15:04.54#ibcon#about to read 4, iclass 31, count 0 2006.201.14:15:04.54#ibcon#read 4, iclass 31, count 0 2006.201.14:15:04.54#ibcon#about to read 5, iclass 31, count 0 2006.201.14:15:04.54#ibcon#read 5, iclass 31, count 0 2006.201.14:15:04.54#ibcon#about to read 6, iclass 31, count 0 2006.201.14:15:04.54#ibcon#read 6, iclass 31, count 0 2006.201.14:15:04.54#ibcon#end of sib2, iclass 31, count 0 2006.201.14:15:04.54#ibcon#*after write, iclass 31, count 0 2006.201.14:15:04.54#ibcon#*before return 0, iclass 31, count 0 2006.201.14:15:04.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:04.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:04.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:15:04.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:15:04.54$vck44/valo=8,884.99 2006.201.14:15:04.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.14:15:04.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.14:15:04.54#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:04.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:04.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:04.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:04.54#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:15:04.54#ibcon#first serial, iclass 33, count 0 2006.201.14:15:04.54#ibcon#enter sib2, iclass 33, count 0 2006.201.14:15:04.54#ibcon#flushed, iclass 33, count 0 2006.201.14:15:04.54#ibcon#about to write, iclass 33, count 0 2006.201.14:15:04.54#ibcon#wrote, iclass 33, count 0 2006.201.14:15:04.54#ibcon#about to read 3, iclass 33, count 0 2006.201.14:15:04.56#ibcon#read 3, iclass 33, count 0 2006.201.14:15:04.56#ibcon#about to read 4, iclass 33, count 0 2006.201.14:15:04.56#ibcon#read 4, iclass 33, count 0 2006.201.14:15:04.56#ibcon#about to read 5, iclass 33, count 0 2006.201.14:15:04.56#ibcon#read 5, iclass 33, count 0 2006.201.14:15:04.56#ibcon#about to read 6, iclass 33, count 0 2006.201.14:15:04.56#ibcon#read 6, iclass 33, count 0 2006.201.14:15:04.56#ibcon#end of sib2, iclass 33, count 0 2006.201.14:15:04.56#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:15:04.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:15:04.56#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:15:04.56#ibcon#*before write, iclass 33, count 0 2006.201.14:15:04.56#ibcon#enter sib2, iclass 33, count 0 2006.201.14:15:04.56#ibcon#flushed, iclass 33, count 0 2006.201.14:15:04.56#ibcon#about to write, iclass 33, count 0 2006.201.14:15:04.56#ibcon#wrote, iclass 33, count 0 2006.201.14:15:04.56#ibcon#about to read 3, iclass 33, count 0 2006.201.14:15:04.60#ibcon#read 3, iclass 33, count 0 2006.201.14:15:04.60#ibcon#about to read 4, iclass 33, count 0 2006.201.14:15:04.60#ibcon#read 4, iclass 33, count 0 2006.201.14:15:04.60#ibcon#about to read 5, iclass 33, count 0 2006.201.14:15:04.60#ibcon#read 5, iclass 33, count 0 2006.201.14:15:04.60#ibcon#about to read 6, iclass 33, count 0 2006.201.14:15:04.60#ibcon#read 6, iclass 33, count 0 2006.201.14:15:04.60#ibcon#end of sib2, iclass 33, count 0 2006.201.14:15:04.60#ibcon#*after write, iclass 33, count 0 2006.201.14:15:04.60#ibcon#*before return 0, iclass 33, count 0 2006.201.14:15:04.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:04.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:04.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:15:04.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:15:04.60$vck44/va=8,4 2006.201.14:15:04.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.14:15:04.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.14:15:04.60#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:04.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:15:04.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:15:04.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:15:04.66#ibcon#enter wrdev, iclass 35, count 2 2006.201.14:15:04.66#ibcon#first serial, iclass 35, count 2 2006.201.14:15:04.66#ibcon#enter sib2, iclass 35, count 2 2006.201.14:15:04.66#ibcon#flushed, iclass 35, count 2 2006.201.14:15:04.66#ibcon#about to write, iclass 35, count 2 2006.201.14:15:04.66#ibcon#wrote, iclass 35, count 2 2006.201.14:15:04.66#ibcon#about to read 3, iclass 35, count 2 2006.201.14:15:04.68#ibcon#read 3, iclass 35, count 2 2006.201.14:15:04.68#ibcon#about to read 4, iclass 35, count 2 2006.201.14:15:04.68#ibcon#read 4, iclass 35, count 2 2006.201.14:15:04.68#ibcon#about to read 5, iclass 35, count 2 2006.201.14:15:04.68#ibcon#read 5, iclass 35, count 2 2006.201.14:15:04.68#ibcon#about to read 6, iclass 35, count 2 2006.201.14:15:04.68#ibcon#read 6, iclass 35, count 2 2006.201.14:15:04.68#ibcon#end of sib2, iclass 35, count 2 2006.201.14:15:04.68#ibcon#*mode == 0, iclass 35, count 2 2006.201.14:15:04.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.14:15:04.68#ibcon#[25=AT08-04\r\n] 2006.201.14:15:04.68#ibcon#*before write, iclass 35, count 2 2006.201.14:15:04.68#ibcon#enter sib2, iclass 35, count 2 2006.201.14:15:04.68#ibcon#flushed, iclass 35, count 2 2006.201.14:15:04.68#ibcon#about to write, iclass 35, count 2 2006.201.14:15:04.68#ibcon#wrote, iclass 35, count 2 2006.201.14:15:04.68#ibcon#about to read 3, iclass 35, count 2 2006.201.14:15:04.71#ibcon#read 3, iclass 35, count 2 2006.201.14:15:04.71#ibcon#about to read 4, iclass 35, count 2 2006.201.14:15:04.71#ibcon#read 4, iclass 35, count 2 2006.201.14:15:04.71#ibcon#about to read 5, iclass 35, count 2 2006.201.14:15:04.71#ibcon#read 5, iclass 35, count 2 2006.201.14:15:04.71#ibcon#about to read 6, iclass 35, count 2 2006.201.14:15:04.71#ibcon#read 6, iclass 35, count 2 2006.201.14:15:04.71#ibcon#end of sib2, iclass 35, count 2 2006.201.14:15:04.71#ibcon#*after write, iclass 35, count 2 2006.201.14:15:04.71#ibcon#*before return 0, iclass 35, count 2 2006.201.14:15:04.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:15:04.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:15:04.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.14:15:04.71#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:04.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:15:04.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:15:04.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:15:04.83#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:15:04.83#ibcon#first serial, iclass 35, count 0 2006.201.14:15:04.83#ibcon#enter sib2, iclass 35, count 0 2006.201.14:15:04.83#ibcon#flushed, iclass 35, count 0 2006.201.14:15:04.83#ibcon#about to write, iclass 35, count 0 2006.201.14:15:04.83#ibcon#wrote, iclass 35, count 0 2006.201.14:15:04.83#ibcon#about to read 3, iclass 35, count 0 2006.201.14:15:04.85#ibcon#read 3, iclass 35, count 0 2006.201.14:15:04.85#ibcon#about to read 4, iclass 35, count 0 2006.201.14:15:04.85#ibcon#read 4, iclass 35, count 0 2006.201.14:15:04.85#ibcon#about to read 5, iclass 35, count 0 2006.201.14:15:04.85#ibcon#read 5, iclass 35, count 0 2006.201.14:15:04.85#ibcon#about to read 6, iclass 35, count 0 2006.201.14:15:04.85#ibcon#read 6, iclass 35, count 0 2006.201.14:15:04.85#ibcon#end of sib2, iclass 35, count 0 2006.201.14:15:04.85#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:15:04.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:15:04.85#ibcon#[25=USB\r\n] 2006.201.14:15:04.85#ibcon#*before write, iclass 35, count 0 2006.201.14:15:04.85#ibcon#enter sib2, iclass 35, count 0 2006.201.14:15:04.85#ibcon#flushed, iclass 35, count 0 2006.201.14:15:04.85#ibcon#about to write, iclass 35, count 0 2006.201.14:15:04.85#ibcon#wrote, iclass 35, count 0 2006.201.14:15:04.85#ibcon#about to read 3, iclass 35, count 0 2006.201.14:15:04.88#ibcon#read 3, iclass 35, count 0 2006.201.14:15:04.88#ibcon#about to read 4, iclass 35, count 0 2006.201.14:15:04.88#ibcon#read 4, iclass 35, count 0 2006.201.14:15:04.88#ibcon#about to read 5, iclass 35, count 0 2006.201.14:15:04.88#ibcon#read 5, iclass 35, count 0 2006.201.14:15:04.88#ibcon#about to read 6, iclass 35, count 0 2006.201.14:15:04.88#ibcon#read 6, iclass 35, count 0 2006.201.14:15:04.88#ibcon#end of sib2, iclass 35, count 0 2006.201.14:15:04.88#ibcon#*after write, iclass 35, count 0 2006.201.14:15:04.88#ibcon#*before return 0, iclass 35, count 0 2006.201.14:15:04.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:15:04.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:15:04.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:15:04.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:15:04.88$vck44/vblo=1,629.99 2006.201.14:15:04.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.14:15:04.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.14:15:04.88#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:04.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:15:04.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:15:04.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:15:04.88#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:15:04.88#ibcon#first serial, iclass 37, count 0 2006.201.14:15:04.88#ibcon#enter sib2, iclass 37, count 0 2006.201.14:15:04.88#ibcon#flushed, iclass 37, count 0 2006.201.14:15:04.88#ibcon#about to write, iclass 37, count 0 2006.201.14:15:04.88#ibcon#wrote, iclass 37, count 0 2006.201.14:15:04.88#ibcon#about to read 3, iclass 37, count 0 2006.201.14:15:04.90#ibcon#read 3, iclass 37, count 0 2006.201.14:15:04.90#ibcon#about to read 4, iclass 37, count 0 2006.201.14:15:04.90#ibcon#read 4, iclass 37, count 0 2006.201.14:15:04.90#ibcon#about to read 5, iclass 37, count 0 2006.201.14:15:04.90#ibcon#read 5, iclass 37, count 0 2006.201.14:15:04.90#ibcon#about to read 6, iclass 37, count 0 2006.201.14:15:04.90#ibcon#read 6, iclass 37, count 0 2006.201.14:15:04.90#ibcon#end of sib2, iclass 37, count 0 2006.201.14:15:04.90#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:15:04.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:15:04.90#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:15:04.90#ibcon#*before write, iclass 37, count 0 2006.201.14:15:04.90#ibcon#enter sib2, iclass 37, count 0 2006.201.14:15:04.90#ibcon#flushed, iclass 37, count 0 2006.201.14:15:04.90#ibcon#about to write, iclass 37, count 0 2006.201.14:15:04.90#ibcon#wrote, iclass 37, count 0 2006.201.14:15:04.90#ibcon#about to read 3, iclass 37, count 0 2006.201.14:15:04.94#ibcon#read 3, iclass 37, count 0 2006.201.14:15:04.94#ibcon#about to read 4, iclass 37, count 0 2006.201.14:15:04.94#ibcon#read 4, iclass 37, count 0 2006.201.14:15:04.94#ibcon#about to read 5, iclass 37, count 0 2006.201.14:15:04.94#ibcon#read 5, iclass 37, count 0 2006.201.14:15:04.94#ibcon#about to read 6, iclass 37, count 0 2006.201.14:15:04.94#ibcon#read 6, iclass 37, count 0 2006.201.14:15:04.94#ibcon#end of sib2, iclass 37, count 0 2006.201.14:15:04.94#ibcon#*after write, iclass 37, count 0 2006.201.14:15:04.94#ibcon#*before return 0, iclass 37, count 0 2006.201.14:15:04.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:15:04.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:15:04.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:15:04.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:15:04.94$vck44/vb=1,4 2006.201.14:15:04.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.14:15:04.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.14:15:04.94#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:04.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:15:04.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:15:04.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:15:04.94#ibcon#enter wrdev, iclass 39, count 2 2006.201.14:15:04.94#ibcon#first serial, iclass 39, count 2 2006.201.14:15:04.94#ibcon#enter sib2, iclass 39, count 2 2006.201.14:15:04.94#ibcon#flushed, iclass 39, count 2 2006.201.14:15:04.94#ibcon#about to write, iclass 39, count 2 2006.201.14:15:04.94#ibcon#wrote, iclass 39, count 2 2006.201.14:15:04.94#ibcon#about to read 3, iclass 39, count 2 2006.201.14:15:04.96#ibcon#read 3, iclass 39, count 2 2006.201.14:15:04.96#ibcon#about to read 4, iclass 39, count 2 2006.201.14:15:04.96#ibcon#read 4, iclass 39, count 2 2006.201.14:15:04.96#ibcon#about to read 5, iclass 39, count 2 2006.201.14:15:04.96#ibcon#read 5, iclass 39, count 2 2006.201.14:15:04.96#ibcon#about to read 6, iclass 39, count 2 2006.201.14:15:04.96#ibcon#read 6, iclass 39, count 2 2006.201.14:15:04.96#ibcon#end of sib2, iclass 39, count 2 2006.201.14:15:04.96#ibcon#*mode == 0, iclass 39, count 2 2006.201.14:15:04.96#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.14:15:04.96#ibcon#[27=AT01-04\r\n] 2006.201.14:15:04.96#ibcon#*before write, iclass 39, count 2 2006.201.14:15:04.96#ibcon#enter sib2, iclass 39, count 2 2006.201.14:15:04.96#ibcon#flushed, iclass 39, count 2 2006.201.14:15:04.96#ibcon#about to write, iclass 39, count 2 2006.201.14:15:04.96#ibcon#wrote, iclass 39, count 2 2006.201.14:15:04.96#ibcon#about to read 3, iclass 39, count 2 2006.201.14:15:04.99#ibcon#read 3, iclass 39, count 2 2006.201.14:15:04.99#ibcon#about to read 4, iclass 39, count 2 2006.201.14:15:04.99#ibcon#read 4, iclass 39, count 2 2006.201.14:15:04.99#ibcon#about to read 5, iclass 39, count 2 2006.201.14:15:04.99#ibcon#read 5, iclass 39, count 2 2006.201.14:15:04.99#ibcon#about to read 6, iclass 39, count 2 2006.201.14:15:04.99#ibcon#read 6, iclass 39, count 2 2006.201.14:15:04.99#ibcon#end of sib2, iclass 39, count 2 2006.201.14:15:04.99#ibcon#*after write, iclass 39, count 2 2006.201.14:15:04.99#ibcon#*before return 0, iclass 39, count 2 2006.201.14:15:04.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:15:04.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:15:04.99#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.14:15:04.99#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:04.99#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:15:05.11#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:15:05.11#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:15:05.11#ibcon#enter wrdev, iclass 39, count 0 2006.201.14:15:05.11#ibcon#first serial, iclass 39, count 0 2006.201.14:15:05.11#ibcon#enter sib2, iclass 39, count 0 2006.201.14:15:05.11#ibcon#flushed, iclass 39, count 0 2006.201.14:15:05.11#ibcon#about to write, iclass 39, count 0 2006.201.14:15:05.11#ibcon#wrote, iclass 39, count 0 2006.201.14:15:05.11#ibcon#about to read 3, iclass 39, count 0 2006.201.14:15:05.13#ibcon#read 3, iclass 39, count 0 2006.201.14:15:05.13#ibcon#about to read 4, iclass 39, count 0 2006.201.14:15:05.13#ibcon#read 4, iclass 39, count 0 2006.201.14:15:05.13#ibcon#about to read 5, iclass 39, count 0 2006.201.14:15:05.13#ibcon#read 5, iclass 39, count 0 2006.201.14:15:05.13#ibcon#about to read 6, iclass 39, count 0 2006.201.14:15:05.13#ibcon#read 6, iclass 39, count 0 2006.201.14:15:05.13#ibcon#end of sib2, iclass 39, count 0 2006.201.14:15:05.13#ibcon#*mode == 0, iclass 39, count 0 2006.201.14:15:05.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.14:15:05.13#ibcon#[27=USB\r\n] 2006.201.14:15:05.13#ibcon#*before write, iclass 39, count 0 2006.201.14:15:05.13#ibcon#enter sib2, iclass 39, count 0 2006.201.14:15:05.13#ibcon#flushed, iclass 39, count 0 2006.201.14:15:05.13#ibcon#about to write, iclass 39, count 0 2006.201.14:15:05.13#ibcon#wrote, iclass 39, count 0 2006.201.14:15:05.13#ibcon#about to read 3, iclass 39, count 0 2006.201.14:15:05.16#ibcon#read 3, iclass 39, count 0 2006.201.14:15:05.16#ibcon#about to read 4, iclass 39, count 0 2006.201.14:15:05.16#ibcon#read 4, iclass 39, count 0 2006.201.14:15:05.16#ibcon#about to read 5, iclass 39, count 0 2006.201.14:15:05.16#ibcon#read 5, iclass 39, count 0 2006.201.14:15:05.16#ibcon#about to read 6, iclass 39, count 0 2006.201.14:15:05.16#ibcon#read 6, iclass 39, count 0 2006.201.14:15:05.16#ibcon#end of sib2, iclass 39, count 0 2006.201.14:15:05.16#ibcon#*after write, iclass 39, count 0 2006.201.14:15:05.16#ibcon#*before return 0, iclass 39, count 0 2006.201.14:15:05.16#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:15:05.16#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:15:05.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.14:15:05.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.14:15:05.16$vck44/vblo=2,634.99 2006.201.14:15:05.16#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.14:15:05.16#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.14:15:05.16#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:05.16#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:05.16#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:05.16#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:05.16#ibcon#enter wrdev, iclass 2, count 0 2006.201.14:15:05.16#ibcon#first serial, iclass 2, count 0 2006.201.14:15:05.16#ibcon#enter sib2, iclass 2, count 0 2006.201.14:15:05.16#ibcon#flushed, iclass 2, count 0 2006.201.14:15:05.16#ibcon#about to write, iclass 2, count 0 2006.201.14:15:05.16#ibcon#wrote, iclass 2, count 0 2006.201.14:15:05.16#ibcon#about to read 3, iclass 2, count 0 2006.201.14:15:05.18#ibcon#read 3, iclass 2, count 0 2006.201.14:15:05.18#ibcon#about to read 4, iclass 2, count 0 2006.201.14:15:05.18#ibcon#read 4, iclass 2, count 0 2006.201.14:15:05.18#ibcon#about to read 5, iclass 2, count 0 2006.201.14:15:05.18#ibcon#read 5, iclass 2, count 0 2006.201.14:15:05.18#ibcon#about to read 6, iclass 2, count 0 2006.201.14:15:05.18#ibcon#read 6, iclass 2, count 0 2006.201.14:15:05.18#ibcon#end of sib2, iclass 2, count 0 2006.201.14:15:05.18#ibcon#*mode == 0, iclass 2, count 0 2006.201.14:15:05.18#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.14:15:05.18#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:15:05.18#ibcon#*before write, iclass 2, count 0 2006.201.14:15:05.18#ibcon#enter sib2, iclass 2, count 0 2006.201.14:15:05.18#ibcon#flushed, iclass 2, count 0 2006.201.14:15:05.18#ibcon#about to write, iclass 2, count 0 2006.201.14:15:05.18#ibcon#wrote, iclass 2, count 0 2006.201.14:15:05.18#ibcon#about to read 3, iclass 2, count 0 2006.201.14:15:05.22#ibcon#read 3, iclass 2, count 0 2006.201.14:15:05.22#ibcon#about to read 4, iclass 2, count 0 2006.201.14:15:05.22#ibcon#read 4, iclass 2, count 0 2006.201.14:15:05.22#ibcon#about to read 5, iclass 2, count 0 2006.201.14:15:05.22#ibcon#read 5, iclass 2, count 0 2006.201.14:15:05.22#ibcon#about to read 6, iclass 2, count 0 2006.201.14:15:05.22#ibcon#read 6, iclass 2, count 0 2006.201.14:15:05.22#ibcon#end of sib2, iclass 2, count 0 2006.201.14:15:05.22#ibcon#*after write, iclass 2, count 0 2006.201.14:15:05.22#ibcon#*before return 0, iclass 2, count 0 2006.201.14:15:05.22#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:05.22#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:15:05.22#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.14:15:05.22#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.14:15:05.22$vck44/vb=2,5 2006.201.14:15:05.22#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.14:15:05.22#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.14:15:05.22#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:05.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:05.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:05.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:05.28#ibcon#enter wrdev, iclass 5, count 2 2006.201.14:15:05.28#ibcon#first serial, iclass 5, count 2 2006.201.14:15:05.28#ibcon#enter sib2, iclass 5, count 2 2006.201.14:15:05.28#ibcon#flushed, iclass 5, count 2 2006.201.14:15:05.28#ibcon#about to write, iclass 5, count 2 2006.201.14:15:05.28#ibcon#wrote, iclass 5, count 2 2006.201.14:15:05.28#ibcon#about to read 3, iclass 5, count 2 2006.201.14:15:05.30#ibcon#read 3, iclass 5, count 2 2006.201.14:15:05.30#ibcon#about to read 4, iclass 5, count 2 2006.201.14:15:05.30#ibcon#read 4, iclass 5, count 2 2006.201.14:15:05.30#ibcon#about to read 5, iclass 5, count 2 2006.201.14:15:05.30#ibcon#read 5, iclass 5, count 2 2006.201.14:15:05.30#ibcon#about to read 6, iclass 5, count 2 2006.201.14:15:05.30#ibcon#read 6, iclass 5, count 2 2006.201.14:15:05.30#ibcon#end of sib2, iclass 5, count 2 2006.201.14:15:05.30#ibcon#*mode == 0, iclass 5, count 2 2006.201.14:15:05.30#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.14:15:05.30#ibcon#[27=AT02-05\r\n] 2006.201.14:15:05.30#ibcon#*before write, iclass 5, count 2 2006.201.14:15:05.30#ibcon#enter sib2, iclass 5, count 2 2006.201.14:15:05.30#ibcon#flushed, iclass 5, count 2 2006.201.14:15:05.30#ibcon#about to write, iclass 5, count 2 2006.201.14:15:05.30#ibcon#wrote, iclass 5, count 2 2006.201.14:15:05.30#ibcon#about to read 3, iclass 5, count 2 2006.201.14:15:05.33#ibcon#read 3, iclass 5, count 2 2006.201.14:15:05.33#ibcon#about to read 4, iclass 5, count 2 2006.201.14:15:05.33#ibcon#read 4, iclass 5, count 2 2006.201.14:15:05.33#ibcon#about to read 5, iclass 5, count 2 2006.201.14:15:05.33#ibcon#read 5, iclass 5, count 2 2006.201.14:15:05.33#ibcon#about to read 6, iclass 5, count 2 2006.201.14:15:05.33#ibcon#read 6, iclass 5, count 2 2006.201.14:15:05.33#ibcon#end of sib2, iclass 5, count 2 2006.201.14:15:05.33#ibcon#*after write, iclass 5, count 2 2006.201.14:15:05.33#ibcon#*before return 0, iclass 5, count 2 2006.201.14:15:05.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:05.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:15:05.33#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.14:15:05.33#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:05.33#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:05.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:05.45#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:05.45#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:15:05.45#ibcon#first serial, iclass 5, count 0 2006.201.14:15:05.45#ibcon#enter sib2, iclass 5, count 0 2006.201.14:15:05.45#ibcon#flushed, iclass 5, count 0 2006.201.14:15:05.45#ibcon#about to write, iclass 5, count 0 2006.201.14:15:05.45#ibcon#wrote, iclass 5, count 0 2006.201.14:15:05.45#ibcon#about to read 3, iclass 5, count 0 2006.201.14:15:05.47#ibcon#read 3, iclass 5, count 0 2006.201.14:15:05.47#ibcon#about to read 4, iclass 5, count 0 2006.201.14:15:05.47#ibcon#read 4, iclass 5, count 0 2006.201.14:15:05.47#ibcon#about to read 5, iclass 5, count 0 2006.201.14:15:05.47#ibcon#read 5, iclass 5, count 0 2006.201.14:15:05.47#ibcon#about to read 6, iclass 5, count 0 2006.201.14:15:05.47#ibcon#read 6, iclass 5, count 0 2006.201.14:15:05.47#ibcon#end of sib2, iclass 5, count 0 2006.201.14:15:05.47#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:15:05.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:15:05.47#ibcon#[27=USB\r\n] 2006.201.14:15:05.47#ibcon#*before write, iclass 5, count 0 2006.201.14:15:05.47#ibcon#enter sib2, iclass 5, count 0 2006.201.14:15:05.47#ibcon#flushed, iclass 5, count 0 2006.201.14:15:05.47#ibcon#about to write, iclass 5, count 0 2006.201.14:15:05.47#ibcon#wrote, iclass 5, count 0 2006.201.14:15:05.47#ibcon#about to read 3, iclass 5, count 0 2006.201.14:15:05.50#ibcon#read 3, iclass 5, count 0 2006.201.14:15:05.50#ibcon#about to read 4, iclass 5, count 0 2006.201.14:15:05.50#ibcon#read 4, iclass 5, count 0 2006.201.14:15:05.50#ibcon#about to read 5, iclass 5, count 0 2006.201.14:15:05.50#ibcon#read 5, iclass 5, count 0 2006.201.14:15:05.50#ibcon#about to read 6, iclass 5, count 0 2006.201.14:15:05.50#ibcon#read 6, iclass 5, count 0 2006.201.14:15:05.50#ibcon#end of sib2, iclass 5, count 0 2006.201.14:15:05.50#ibcon#*after write, iclass 5, count 0 2006.201.14:15:05.50#ibcon#*before return 0, iclass 5, count 0 2006.201.14:15:05.50#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:05.50#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:15:05.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:15:05.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:15:05.50$vck44/vblo=3,649.99 2006.201.14:15:05.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.14:15:05.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.14:15:05.50#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:05.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:05.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:05.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:05.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:15:05.50#ibcon#first serial, iclass 7, count 0 2006.201.14:15:05.50#ibcon#enter sib2, iclass 7, count 0 2006.201.14:15:05.50#ibcon#flushed, iclass 7, count 0 2006.201.14:15:05.50#ibcon#about to write, iclass 7, count 0 2006.201.14:15:05.50#ibcon#wrote, iclass 7, count 0 2006.201.14:15:05.50#ibcon#about to read 3, iclass 7, count 0 2006.201.14:15:05.52#ibcon#read 3, iclass 7, count 0 2006.201.14:15:05.52#ibcon#about to read 4, iclass 7, count 0 2006.201.14:15:05.52#ibcon#read 4, iclass 7, count 0 2006.201.14:15:05.52#ibcon#about to read 5, iclass 7, count 0 2006.201.14:15:05.52#ibcon#read 5, iclass 7, count 0 2006.201.14:15:05.52#ibcon#about to read 6, iclass 7, count 0 2006.201.14:15:05.52#ibcon#read 6, iclass 7, count 0 2006.201.14:15:05.52#ibcon#end of sib2, iclass 7, count 0 2006.201.14:15:05.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:15:05.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:15:05.52#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:15:05.52#ibcon#*before write, iclass 7, count 0 2006.201.14:15:05.52#ibcon#enter sib2, iclass 7, count 0 2006.201.14:15:05.52#ibcon#flushed, iclass 7, count 0 2006.201.14:15:05.52#ibcon#about to write, iclass 7, count 0 2006.201.14:15:05.52#ibcon#wrote, iclass 7, count 0 2006.201.14:15:05.52#ibcon#about to read 3, iclass 7, count 0 2006.201.14:15:05.56#ibcon#read 3, iclass 7, count 0 2006.201.14:15:05.56#ibcon#about to read 4, iclass 7, count 0 2006.201.14:15:05.56#ibcon#read 4, iclass 7, count 0 2006.201.14:15:05.56#ibcon#about to read 5, iclass 7, count 0 2006.201.14:15:05.56#ibcon#read 5, iclass 7, count 0 2006.201.14:15:05.56#ibcon#about to read 6, iclass 7, count 0 2006.201.14:15:05.56#ibcon#read 6, iclass 7, count 0 2006.201.14:15:05.56#ibcon#end of sib2, iclass 7, count 0 2006.201.14:15:05.56#ibcon#*after write, iclass 7, count 0 2006.201.14:15:05.56#ibcon#*before return 0, iclass 7, count 0 2006.201.14:15:05.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:05.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:15:05.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:15:05.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:15:05.56$vck44/vb=3,4 2006.201.14:15:05.56#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.14:15:05.56#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.14:15:05.56#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:05.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:05.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:05.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:05.62#ibcon#enter wrdev, iclass 11, count 2 2006.201.14:15:05.62#ibcon#first serial, iclass 11, count 2 2006.201.14:15:05.62#ibcon#enter sib2, iclass 11, count 2 2006.201.14:15:05.62#ibcon#flushed, iclass 11, count 2 2006.201.14:15:05.62#ibcon#about to write, iclass 11, count 2 2006.201.14:15:05.62#ibcon#wrote, iclass 11, count 2 2006.201.14:15:05.62#ibcon#about to read 3, iclass 11, count 2 2006.201.14:15:05.64#ibcon#read 3, iclass 11, count 2 2006.201.14:15:05.64#ibcon#about to read 4, iclass 11, count 2 2006.201.14:15:05.64#ibcon#read 4, iclass 11, count 2 2006.201.14:15:05.64#ibcon#about to read 5, iclass 11, count 2 2006.201.14:15:05.64#ibcon#read 5, iclass 11, count 2 2006.201.14:15:05.64#ibcon#about to read 6, iclass 11, count 2 2006.201.14:15:05.64#ibcon#read 6, iclass 11, count 2 2006.201.14:15:05.64#ibcon#end of sib2, iclass 11, count 2 2006.201.14:15:05.64#ibcon#*mode == 0, iclass 11, count 2 2006.201.14:15:05.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.14:15:05.64#ibcon#[27=AT03-04\r\n] 2006.201.14:15:05.64#ibcon#*before write, iclass 11, count 2 2006.201.14:15:05.64#ibcon#enter sib2, iclass 11, count 2 2006.201.14:15:05.64#ibcon#flushed, iclass 11, count 2 2006.201.14:15:05.64#ibcon#about to write, iclass 11, count 2 2006.201.14:15:05.64#ibcon#wrote, iclass 11, count 2 2006.201.14:15:05.64#ibcon#about to read 3, iclass 11, count 2 2006.201.14:15:05.67#ibcon#read 3, iclass 11, count 2 2006.201.14:15:05.67#ibcon#about to read 4, iclass 11, count 2 2006.201.14:15:05.67#ibcon#read 4, iclass 11, count 2 2006.201.14:15:05.67#ibcon#about to read 5, iclass 11, count 2 2006.201.14:15:05.67#ibcon#read 5, iclass 11, count 2 2006.201.14:15:05.67#ibcon#about to read 6, iclass 11, count 2 2006.201.14:15:05.67#ibcon#read 6, iclass 11, count 2 2006.201.14:15:05.67#ibcon#end of sib2, iclass 11, count 2 2006.201.14:15:05.67#ibcon#*after write, iclass 11, count 2 2006.201.14:15:05.67#ibcon#*before return 0, iclass 11, count 2 2006.201.14:15:05.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:05.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:15:05.67#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.14:15:05.67#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:05.67#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:05.79#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:05.79#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:05.79#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:15:05.79#ibcon#first serial, iclass 11, count 0 2006.201.14:15:05.79#ibcon#enter sib2, iclass 11, count 0 2006.201.14:15:05.79#ibcon#flushed, iclass 11, count 0 2006.201.14:15:05.79#ibcon#about to write, iclass 11, count 0 2006.201.14:15:05.79#ibcon#wrote, iclass 11, count 0 2006.201.14:15:05.79#ibcon#about to read 3, iclass 11, count 0 2006.201.14:15:05.81#ibcon#read 3, iclass 11, count 0 2006.201.14:15:05.81#ibcon#about to read 4, iclass 11, count 0 2006.201.14:15:05.81#ibcon#read 4, iclass 11, count 0 2006.201.14:15:05.81#ibcon#about to read 5, iclass 11, count 0 2006.201.14:15:05.81#ibcon#read 5, iclass 11, count 0 2006.201.14:15:05.81#ibcon#about to read 6, iclass 11, count 0 2006.201.14:15:05.81#ibcon#read 6, iclass 11, count 0 2006.201.14:15:05.81#ibcon#end of sib2, iclass 11, count 0 2006.201.14:15:05.81#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:15:05.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:15:05.81#ibcon#[27=USB\r\n] 2006.201.14:15:05.81#ibcon#*before write, iclass 11, count 0 2006.201.14:15:05.81#ibcon#enter sib2, iclass 11, count 0 2006.201.14:15:05.81#ibcon#flushed, iclass 11, count 0 2006.201.14:15:05.81#ibcon#about to write, iclass 11, count 0 2006.201.14:15:05.81#ibcon#wrote, iclass 11, count 0 2006.201.14:15:05.81#ibcon#about to read 3, iclass 11, count 0 2006.201.14:15:05.84#ibcon#read 3, iclass 11, count 0 2006.201.14:15:05.84#ibcon#about to read 4, iclass 11, count 0 2006.201.14:15:05.84#ibcon#read 4, iclass 11, count 0 2006.201.14:15:05.84#ibcon#about to read 5, iclass 11, count 0 2006.201.14:15:05.84#ibcon#read 5, iclass 11, count 0 2006.201.14:15:05.84#ibcon#about to read 6, iclass 11, count 0 2006.201.14:15:05.84#ibcon#read 6, iclass 11, count 0 2006.201.14:15:05.84#ibcon#end of sib2, iclass 11, count 0 2006.201.14:15:05.84#ibcon#*after write, iclass 11, count 0 2006.201.14:15:05.84#ibcon#*before return 0, iclass 11, count 0 2006.201.14:15:05.84#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:05.84#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:15:05.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:15:05.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:15:05.84$vck44/vblo=4,679.99 2006.201.14:15:05.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.14:15:05.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.14:15:05.84#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:05.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:05.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:05.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:05.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:15:05.84#ibcon#first serial, iclass 13, count 0 2006.201.14:15:05.84#ibcon#enter sib2, iclass 13, count 0 2006.201.14:15:05.84#ibcon#flushed, iclass 13, count 0 2006.201.14:15:05.84#ibcon#about to write, iclass 13, count 0 2006.201.14:15:05.84#ibcon#wrote, iclass 13, count 0 2006.201.14:15:05.84#ibcon#about to read 3, iclass 13, count 0 2006.201.14:15:05.86#ibcon#read 3, iclass 13, count 0 2006.201.14:15:05.86#ibcon#about to read 4, iclass 13, count 0 2006.201.14:15:05.86#ibcon#read 4, iclass 13, count 0 2006.201.14:15:05.86#ibcon#about to read 5, iclass 13, count 0 2006.201.14:15:05.86#ibcon#read 5, iclass 13, count 0 2006.201.14:15:05.86#ibcon#about to read 6, iclass 13, count 0 2006.201.14:15:05.86#ibcon#read 6, iclass 13, count 0 2006.201.14:15:05.86#ibcon#end of sib2, iclass 13, count 0 2006.201.14:15:05.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:15:05.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:15:05.86#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:15:05.86#ibcon#*before write, iclass 13, count 0 2006.201.14:15:05.86#ibcon#enter sib2, iclass 13, count 0 2006.201.14:15:05.86#ibcon#flushed, iclass 13, count 0 2006.201.14:15:05.86#ibcon#about to write, iclass 13, count 0 2006.201.14:15:05.86#ibcon#wrote, iclass 13, count 0 2006.201.14:15:05.86#ibcon#about to read 3, iclass 13, count 0 2006.201.14:15:05.90#ibcon#read 3, iclass 13, count 0 2006.201.14:15:05.90#ibcon#about to read 4, iclass 13, count 0 2006.201.14:15:05.90#ibcon#read 4, iclass 13, count 0 2006.201.14:15:05.90#ibcon#about to read 5, iclass 13, count 0 2006.201.14:15:05.90#ibcon#read 5, iclass 13, count 0 2006.201.14:15:05.90#ibcon#about to read 6, iclass 13, count 0 2006.201.14:15:05.90#ibcon#read 6, iclass 13, count 0 2006.201.14:15:05.90#ibcon#end of sib2, iclass 13, count 0 2006.201.14:15:05.90#ibcon#*after write, iclass 13, count 0 2006.201.14:15:05.90#ibcon#*before return 0, iclass 13, count 0 2006.201.14:15:05.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:05.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:15:05.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:15:05.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:15:05.90$vck44/vb=4,5 2006.201.14:15:05.90#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.14:15:05.90#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.14:15:05.90#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:05.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:05.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:05.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:05.96#ibcon#enter wrdev, iclass 15, count 2 2006.201.14:15:05.96#ibcon#first serial, iclass 15, count 2 2006.201.14:15:05.96#ibcon#enter sib2, iclass 15, count 2 2006.201.14:15:05.96#ibcon#flushed, iclass 15, count 2 2006.201.14:15:05.96#ibcon#about to write, iclass 15, count 2 2006.201.14:15:05.96#ibcon#wrote, iclass 15, count 2 2006.201.14:15:05.96#ibcon#about to read 3, iclass 15, count 2 2006.201.14:15:05.98#ibcon#read 3, iclass 15, count 2 2006.201.14:15:05.98#ibcon#about to read 4, iclass 15, count 2 2006.201.14:15:05.98#ibcon#read 4, iclass 15, count 2 2006.201.14:15:05.98#ibcon#about to read 5, iclass 15, count 2 2006.201.14:15:05.98#ibcon#read 5, iclass 15, count 2 2006.201.14:15:05.98#ibcon#about to read 6, iclass 15, count 2 2006.201.14:15:05.98#ibcon#read 6, iclass 15, count 2 2006.201.14:15:05.98#ibcon#end of sib2, iclass 15, count 2 2006.201.14:15:05.98#ibcon#*mode == 0, iclass 15, count 2 2006.201.14:15:05.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.14:15:05.98#ibcon#[27=AT04-05\r\n] 2006.201.14:15:05.98#ibcon#*before write, iclass 15, count 2 2006.201.14:15:05.98#ibcon#enter sib2, iclass 15, count 2 2006.201.14:15:05.98#ibcon#flushed, iclass 15, count 2 2006.201.14:15:05.98#ibcon#about to write, iclass 15, count 2 2006.201.14:15:05.98#ibcon#wrote, iclass 15, count 2 2006.201.14:15:05.98#ibcon#about to read 3, iclass 15, count 2 2006.201.14:15:06.01#ibcon#read 3, iclass 15, count 2 2006.201.14:15:06.01#ibcon#about to read 4, iclass 15, count 2 2006.201.14:15:06.01#ibcon#read 4, iclass 15, count 2 2006.201.14:15:06.01#ibcon#about to read 5, iclass 15, count 2 2006.201.14:15:06.01#ibcon#read 5, iclass 15, count 2 2006.201.14:15:06.01#ibcon#about to read 6, iclass 15, count 2 2006.201.14:15:06.01#ibcon#read 6, iclass 15, count 2 2006.201.14:15:06.01#ibcon#end of sib2, iclass 15, count 2 2006.201.14:15:06.01#ibcon#*after write, iclass 15, count 2 2006.201.14:15:06.01#ibcon#*before return 0, iclass 15, count 2 2006.201.14:15:06.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:06.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:15:06.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.14:15:06.01#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:06.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:06.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:06.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:06.13#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:15:06.13#ibcon#first serial, iclass 15, count 0 2006.201.14:15:06.13#ibcon#enter sib2, iclass 15, count 0 2006.201.14:15:06.13#ibcon#flushed, iclass 15, count 0 2006.201.14:15:06.13#ibcon#about to write, iclass 15, count 0 2006.201.14:15:06.13#ibcon#wrote, iclass 15, count 0 2006.201.14:15:06.13#ibcon#about to read 3, iclass 15, count 0 2006.201.14:15:06.15#ibcon#read 3, iclass 15, count 0 2006.201.14:15:06.15#ibcon#about to read 4, iclass 15, count 0 2006.201.14:15:06.15#ibcon#read 4, iclass 15, count 0 2006.201.14:15:06.15#ibcon#about to read 5, iclass 15, count 0 2006.201.14:15:06.15#ibcon#read 5, iclass 15, count 0 2006.201.14:15:06.15#ibcon#about to read 6, iclass 15, count 0 2006.201.14:15:06.15#ibcon#read 6, iclass 15, count 0 2006.201.14:15:06.15#ibcon#end of sib2, iclass 15, count 0 2006.201.14:15:06.15#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:15:06.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:15:06.15#ibcon#[27=USB\r\n] 2006.201.14:15:06.15#ibcon#*before write, iclass 15, count 0 2006.201.14:15:06.15#ibcon#enter sib2, iclass 15, count 0 2006.201.14:15:06.15#ibcon#flushed, iclass 15, count 0 2006.201.14:15:06.15#ibcon#about to write, iclass 15, count 0 2006.201.14:15:06.15#ibcon#wrote, iclass 15, count 0 2006.201.14:15:06.15#ibcon#about to read 3, iclass 15, count 0 2006.201.14:15:06.18#ibcon#read 3, iclass 15, count 0 2006.201.14:15:06.18#ibcon#about to read 4, iclass 15, count 0 2006.201.14:15:06.18#ibcon#read 4, iclass 15, count 0 2006.201.14:15:06.18#ibcon#about to read 5, iclass 15, count 0 2006.201.14:15:06.18#ibcon#read 5, iclass 15, count 0 2006.201.14:15:06.18#ibcon#about to read 6, iclass 15, count 0 2006.201.14:15:06.18#ibcon#read 6, iclass 15, count 0 2006.201.14:15:06.18#ibcon#end of sib2, iclass 15, count 0 2006.201.14:15:06.18#ibcon#*after write, iclass 15, count 0 2006.201.14:15:06.18#ibcon#*before return 0, iclass 15, count 0 2006.201.14:15:06.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:06.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:15:06.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:15:06.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:15:06.18$vck44/vblo=5,709.99 2006.201.14:15:06.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.14:15:06.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.14:15:06.18#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:06.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:06.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:06.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:06.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:15:06.18#ibcon#first serial, iclass 17, count 0 2006.201.14:15:06.18#ibcon#enter sib2, iclass 17, count 0 2006.201.14:15:06.18#ibcon#flushed, iclass 17, count 0 2006.201.14:15:06.18#ibcon#about to write, iclass 17, count 0 2006.201.14:15:06.18#ibcon#wrote, iclass 17, count 0 2006.201.14:15:06.18#ibcon#about to read 3, iclass 17, count 0 2006.201.14:15:06.20#ibcon#read 3, iclass 17, count 0 2006.201.14:15:06.20#ibcon#about to read 4, iclass 17, count 0 2006.201.14:15:06.20#ibcon#read 4, iclass 17, count 0 2006.201.14:15:06.20#ibcon#about to read 5, iclass 17, count 0 2006.201.14:15:06.20#ibcon#read 5, iclass 17, count 0 2006.201.14:15:06.20#ibcon#about to read 6, iclass 17, count 0 2006.201.14:15:06.20#ibcon#read 6, iclass 17, count 0 2006.201.14:15:06.20#ibcon#end of sib2, iclass 17, count 0 2006.201.14:15:06.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:15:06.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:15:06.20#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:15:06.20#ibcon#*before write, iclass 17, count 0 2006.201.14:15:06.20#ibcon#enter sib2, iclass 17, count 0 2006.201.14:15:06.20#ibcon#flushed, iclass 17, count 0 2006.201.14:15:06.20#ibcon#about to write, iclass 17, count 0 2006.201.14:15:06.20#ibcon#wrote, iclass 17, count 0 2006.201.14:15:06.20#ibcon#about to read 3, iclass 17, count 0 2006.201.14:15:06.24#ibcon#read 3, iclass 17, count 0 2006.201.14:15:06.24#ibcon#about to read 4, iclass 17, count 0 2006.201.14:15:06.24#ibcon#read 4, iclass 17, count 0 2006.201.14:15:06.24#ibcon#about to read 5, iclass 17, count 0 2006.201.14:15:06.24#ibcon#read 5, iclass 17, count 0 2006.201.14:15:06.24#ibcon#about to read 6, iclass 17, count 0 2006.201.14:15:06.24#ibcon#read 6, iclass 17, count 0 2006.201.14:15:06.24#ibcon#end of sib2, iclass 17, count 0 2006.201.14:15:06.24#ibcon#*after write, iclass 17, count 0 2006.201.14:15:06.24#ibcon#*before return 0, iclass 17, count 0 2006.201.14:15:06.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:06.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:15:06.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:15:06.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:15:06.24$vck44/vb=5,4 2006.201.14:15:06.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.14:15:06.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.14:15:06.24#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:06.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:06.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:06.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:06.30#ibcon#enter wrdev, iclass 19, count 2 2006.201.14:15:06.30#ibcon#first serial, iclass 19, count 2 2006.201.14:15:06.30#ibcon#enter sib2, iclass 19, count 2 2006.201.14:15:06.30#ibcon#flushed, iclass 19, count 2 2006.201.14:15:06.30#ibcon#about to write, iclass 19, count 2 2006.201.14:15:06.30#ibcon#wrote, iclass 19, count 2 2006.201.14:15:06.30#ibcon#about to read 3, iclass 19, count 2 2006.201.14:15:06.32#ibcon#read 3, iclass 19, count 2 2006.201.14:15:06.32#ibcon#about to read 4, iclass 19, count 2 2006.201.14:15:06.32#ibcon#read 4, iclass 19, count 2 2006.201.14:15:06.32#ibcon#about to read 5, iclass 19, count 2 2006.201.14:15:06.32#ibcon#read 5, iclass 19, count 2 2006.201.14:15:06.32#ibcon#about to read 6, iclass 19, count 2 2006.201.14:15:06.32#ibcon#read 6, iclass 19, count 2 2006.201.14:15:06.32#ibcon#end of sib2, iclass 19, count 2 2006.201.14:15:06.32#ibcon#*mode == 0, iclass 19, count 2 2006.201.14:15:06.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.14:15:06.32#ibcon#[27=AT05-04\r\n] 2006.201.14:15:06.32#ibcon#*before write, iclass 19, count 2 2006.201.14:15:06.32#ibcon#enter sib2, iclass 19, count 2 2006.201.14:15:06.32#ibcon#flushed, iclass 19, count 2 2006.201.14:15:06.32#ibcon#about to write, iclass 19, count 2 2006.201.14:15:06.32#ibcon#wrote, iclass 19, count 2 2006.201.14:15:06.32#ibcon#about to read 3, iclass 19, count 2 2006.201.14:15:06.35#ibcon#read 3, iclass 19, count 2 2006.201.14:15:06.35#ibcon#about to read 4, iclass 19, count 2 2006.201.14:15:06.35#ibcon#read 4, iclass 19, count 2 2006.201.14:15:06.35#ibcon#about to read 5, iclass 19, count 2 2006.201.14:15:06.35#ibcon#read 5, iclass 19, count 2 2006.201.14:15:06.35#ibcon#about to read 6, iclass 19, count 2 2006.201.14:15:06.35#ibcon#read 6, iclass 19, count 2 2006.201.14:15:06.35#ibcon#end of sib2, iclass 19, count 2 2006.201.14:15:06.35#ibcon#*after write, iclass 19, count 2 2006.201.14:15:06.35#ibcon#*before return 0, iclass 19, count 2 2006.201.14:15:06.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:06.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:15:06.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.14:15:06.35#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:06.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:06.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:06.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:06.47#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:15:06.47#ibcon#first serial, iclass 19, count 0 2006.201.14:15:06.47#ibcon#enter sib2, iclass 19, count 0 2006.201.14:15:06.47#ibcon#flushed, iclass 19, count 0 2006.201.14:15:06.47#ibcon#about to write, iclass 19, count 0 2006.201.14:15:06.47#ibcon#wrote, iclass 19, count 0 2006.201.14:15:06.47#ibcon#about to read 3, iclass 19, count 0 2006.201.14:15:06.49#ibcon#read 3, iclass 19, count 0 2006.201.14:15:06.49#ibcon#about to read 4, iclass 19, count 0 2006.201.14:15:06.49#ibcon#read 4, iclass 19, count 0 2006.201.14:15:06.49#ibcon#about to read 5, iclass 19, count 0 2006.201.14:15:06.49#ibcon#read 5, iclass 19, count 0 2006.201.14:15:06.49#ibcon#about to read 6, iclass 19, count 0 2006.201.14:15:06.49#ibcon#read 6, iclass 19, count 0 2006.201.14:15:06.49#ibcon#end of sib2, iclass 19, count 0 2006.201.14:15:06.49#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:15:06.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:15:06.49#ibcon#[27=USB\r\n] 2006.201.14:15:06.49#ibcon#*before write, iclass 19, count 0 2006.201.14:15:06.49#ibcon#enter sib2, iclass 19, count 0 2006.201.14:15:06.49#ibcon#flushed, iclass 19, count 0 2006.201.14:15:06.49#ibcon#about to write, iclass 19, count 0 2006.201.14:15:06.49#ibcon#wrote, iclass 19, count 0 2006.201.14:15:06.49#ibcon#about to read 3, iclass 19, count 0 2006.201.14:15:06.52#ibcon#read 3, iclass 19, count 0 2006.201.14:15:06.52#ibcon#about to read 4, iclass 19, count 0 2006.201.14:15:06.52#ibcon#read 4, iclass 19, count 0 2006.201.14:15:06.52#ibcon#about to read 5, iclass 19, count 0 2006.201.14:15:06.52#ibcon#read 5, iclass 19, count 0 2006.201.14:15:06.52#ibcon#about to read 6, iclass 19, count 0 2006.201.14:15:06.52#ibcon#read 6, iclass 19, count 0 2006.201.14:15:06.52#ibcon#end of sib2, iclass 19, count 0 2006.201.14:15:06.52#ibcon#*after write, iclass 19, count 0 2006.201.14:15:06.52#ibcon#*before return 0, iclass 19, count 0 2006.201.14:15:06.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:06.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:15:06.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:15:06.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:15:06.52$vck44/vblo=6,719.99 2006.201.14:15:06.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.14:15:06.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.14:15:06.52#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:06.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:06.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:06.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:06.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:15:06.52#ibcon#first serial, iclass 21, count 0 2006.201.14:15:06.52#ibcon#enter sib2, iclass 21, count 0 2006.201.14:15:06.52#ibcon#flushed, iclass 21, count 0 2006.201.14:15:06.52#ibcon#about to write, iclass 21, count 0 2006.201.14:15:06.52#ibcon#wrote, iclass 21, count 0 2006.201.14:15:06.52#ibcon#about to read 3, iclass 21, count 0 2006.201.14:15:06.54#ibcon#read 3, iclass 21, count 0 2006.201.14:15:06.54#ibcon#about to read 4, iclass 21, count 0 2006.201.14:15:06.54#ibcon#read 4, iclass 21, count 0 2006.201.14:15:06.54#ibcon#about to read 5, iclass 21, count 0 2006.201.14:15:06.54#ibcon#read 5, iclass 21, count 0 2006.201.14:15:06.54#ibcon#about to read 6, iclass 21, count 0 2006.201.14:15:06.54#ibcon#read 6, iclass 21, count 0 2006.201.14:15:06.54#ibcon#end of sib2, iclass 21, count 0 2006.201.14:15:06.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:15:06.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:15:06.54#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:15:06.54#ibcon#*before write, iclass 21, count 0 2006.201.14:15:06.54#ibcon#enter sib2, iclass 21, count 0 2006.201.14:15:06.54#ibcon#flushed, iclass 21, count 0 2006.201.14:15:06.54#ibcon#about to write, iclass 21, count 0 2006.201.14:15:06.54#ibcon#wrote, iclass 21, count 0 2006.201.14:15:06.54#ibcon#about to read 3, iclass 21, count 0 2006.201.14:15:06.58#ibcon#read 3, iclass 21, count 0 2006.201.14:15:06.58#ibcon#about to read 4, iclass 21, count 0 2006.201.14:15:06.58#ibcon#read 4, iclass 21, count 0 2006.201.14:15:06.58#ibcon#about to read 5, iclass 21, count 0 2006.201.14:15:06.58#ibcon#read 5, iclass 21, count 0 2006.201.14:15:06.58#ibcon#about to read 6, iclass 21, count 0 2006.201.14:15:06.58#ibcon#read 6, iclass 21, count 0 2006.201.14:15:06.58#ibcon#end of sib2, iclass 21, count 0 2006.201.14:15:06.58#ibcon#*after write, iclass 21, count 0 2006.201.14:15:06.58#ibcon#*before return 0, iclass 21, count 0 2006.201.14:15:06.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:06.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:15:06.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:15:06.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:15:06.58$vck44/vb=6,4 2006.201.14:15:06.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.14:15:06.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.14:15:06.58#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:06.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:06.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:06.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:06.64#ibcon#enter wrdev, iclass 23, count 2 2006.201.14:15:06.64#ibcon#first serial, iclass 23, count 2 2006.201.14:15:06.64#ibcon#enter sib2, iclass 23, count 2 2006.201.14:15:06.64#ibcon#flushed, iclass 23, count 2 2006.201.14:15:06.64#ibcon#about to write, iclass 23, count 2 2006.201.14:15:06.64#ibcon#wrote, iclass 23, count 2 2006.201.14:15:06.64#ibcon#about to read 3, iclass 23, count 2 2006.201.14:15:06.66#ibcon#read 3, iclass 23, count 2 2006.201.14:15:06.66#ibcon#about to read 4, iclass 23, count 2 2006.201.14:15:06.66#ibcon#read 4, iclass 23, count 2 2006.201.14:15:06.66#ibcon#about to read 5, iclass 23, count 2 2006.201.14:15:06.66#ibcon#read 5, iclass 23, count 2 2006.201.14:15:06.66#ibcon#about to read 6, iclass 23, count 2 2006.201.14:15:06.66#ibcon#read 6, iclass 23, count 2 2006.201.14:15:06.66#ibcon#end of sib2, iclass 23, count 2 2006.201.14:15:06.66#ibcon#*mode == 0, iclass 23, count 2 2006.201.14:15:06.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.14:15:06.66#ibcon#[27=AT06-04\r\n] 2006.201.14:15:06.66#ibcon#*before write, iclass 23, count 2 2006.201.14:15:06.66#ibcon#enter sib2, iclass 23, count 2 2006.201.14:15:06.66#ibcon#flushed, iclass 23, count 2 2006.201.14:15:06.66#ibcon#about to write, iclass 23, count 2 2006.201.14:15:06.66#ibcon#wrote, iclass 23, count 2 2006.201.14:15:06.66#ibcon#about to read 3, iclass 23, count 2 2006.201.14:15:06.69#ibcon#read 3, iclass 23, count 2 2006.201.14:15:06.69#ibcon#about to read 4, iclass 23, count 2 2006.201.14:15:06.69#ibcon#read 4, iclass 23, count 2 2006.201.14:15:06.69#ibcon#about to read 5, iclass 23, count 2 2006.201.14:15:06.69#ibcon#read 5, iclass 23, count 2 2006.201.14:15:06.69#ibcon#about to read 6, iclass 23, count 2 2006.201.14:15:06.69#ibcon#read 6, iclass 23, count 2 2006.201.14:15:06.69#ibcon#end of sib2, iclass 23, count 2 2006.201.14:15:06.69#ibcon#*after write, iclass 23, count 2 2006.201.14:15:06.69#ibcon#*before return 0, iclass 23, count 2 2006.201.14:15:06.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:06.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:15:06.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.14:15:06.69#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:06.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:06.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:06.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:06.81#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:15:06.81#ibcon#first serial, iclass 23, count 0 2006.201.14:15:06.81#ibcon#enter sib2, iclass 23, count 0 2006.201.14:15:06.81#ibcon#flushed, iclass 23, count 0 2006.201.14:15:06.81#ibcon#about to write, iclass 23, count 0 2006.201.14:15:06.81#ibcon#wrote, iclass 23, count 0 2006.201.14:15:06.81#ibcon#about to read 3, iclass 23, count 0 2006.201.14:15:06.83#ibcon#read 3, iclass 23, count 0 2006.201.14:15:06.83#ibcon#about to read 4, iclass 23, count 0 2006.201.14:15:06.83#ibcon#read 4, iclass 23, count 0 2006.201.14:15:06.83#ibcon#about to read 5, iclass 23, count 0 2006.201.14:15:06.83#ibcon#read 5, iclass 23, count 0 2006.201.14:15:06.83#ibcon#about to read 6, iclass 23, count 0 2006.201.14:15:06.83#ibcon#read 6, iclass 23, count 0 2006.201.14:15:06.83#ibcon#end of sib2, iclass 23, count 0 2006.201.14:15:06.83#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:15:06.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:15:06.83#ibcon#[27=USB\r\n] 2006.201.14:15:06.83#ibcon#*before write, iclass 23, count 0 2006.201.14:15:06.83#ibcon#enter sib2, iclass 23, count 0 2006.201.14:15:06.83#ibcon#flushed, iclass 23, count 0 2006.201.14:15:06.83#ibcon#about to write, iclass 23, count 0 2006.201.14:15:06.83#ibcon#wrote, iclass 23, count 0 2006.201.14:15:06.83#ibcon#about to read 3, iclass 23, count 0 2006.201.14:15:06.86#ibcon#read 3, iclass 23, count 0 2006.201.14:15:06.86#ibcon#about to read 4, iclass 23, count 0 2006.201.14:15:06.86#ibcon#read 4, iclass 23, count 0 2006.201.14:15:06.86#ibcon#about to read 5, iclass 23, count 0 2006.201.14:15:06.86#ibcon#read 5, iclass 23, count 0 2006.201.14:15:06.86#ibcon#about to read 6, iclass 23, count 0 2006.201.14:15:06.86#ibcon#read 6, iclass 23, count 0 2006.201.14:15:06.86#ibcon#end of sib2, iclass 23, count 0 2006.201.14:15:06.86#ibcon#*after write, iclass 23, count 0 2006.201.14:15:06.86#ibcon#*before return 0, iclass 23, count 0 2006.201.14:15:06.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:06.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:15:06.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:15:06.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:15:06.86$vck44/vblo=7,734.99 2006.201.14:15:06.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.14:15:06.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.14:15:06.86#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:06.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:06.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:06.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:06.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:15:06.86#ibcon#first serial, iclass 25, count 0 2006.201.14:15:06.86#ibcon#enter sib2, iclass 25, count 0 2006.201.14:15:06.86#ibcon#flushed, iclass 25, count 0 2006.201.14:15:06.86#ibcon#about to write, iclass 25, count 0 2006.201.14:15:06.86#ibcon#wrote, iclass 25, count 0 2006.201.14:15:06.86#ibcon#about to read 3, iclass 25, count 0 2006.201.14:15:06.88#ibcon#read 3, iclass 25, count 0 2006.201.14:15:06.88#ibcon#about to read 4, iclass 25, count 0 2006.201.14:15:06.88#ibcon#read 4, iclass 25, count 0 2006.201.14:15:06.88#ibcon#about to read 5, iclass 25, count 0 2006.201.14:15:06.88#ibcon#read 5, iclass 25, count 0 2006.201.14:15:06.88#ibcon#about to read 6, iclass 25, count 0 2006.201.14:15:06.88#ibcon#read 6, iclass 25, count 0 2006.201.14:15:06.88#ibcon#end of sib2, iclass 25, count 0 2006.201.14:15:06.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:15:06.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:15:06.88#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:15:06.88#ibcon#*before write, iclass 25, count 0 2006.201.14:15:06.88#ibcon#enter sib2, iclass 25, count 0 2006.201.14:15:06.88#ibcon#flushed, iclass 25, count 0 2006.201.14:15:06.88#ibcon#about to write, iclass 25, count 0 2006.201.14:15:06.88#ibcon#wrote, iclass 25, count 0 2006.201.14:15:06.88#ibcon#about to read 3, iclass 25, count 0 2006.201.14:15:06.93#ibcon#read 3, iclass 25, count 0 2006.201.14:15:06.93#ibcon#about to read 4, iclass 25, count 0 2006.201.14:15:06.93#ibcon#read 4, iclass 25, count 0 2006.201.14:15:06.93#ibcon#about to read 5, iclass 25, count 0 2006.201.14:15:06.93#ibcon#read 5, iclass 25, count 0 2006.201.14:15:06.93#ibcon#about to read 6, iclass 25, count 0 2006.201.14:15:06.93#ibcon#read 6, iclass 25, count 0 2006.201.14:15:06.93#ibcon#end of sib2, iclass 25, count 0 2006.201.14:15:06.93#ibcon#*after write, iclass 25, count 0 2006.201.14:15:06.93#ibcon#*before return 0, iclass 25, count 0 2006.201.14:15:06.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:06.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:15:06.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:15:06.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:15:06.93$vck44/vb=7,4 2006.201.14:15:06.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.14:15:06.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.14:15:06.93#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:06.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:06.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:06.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:06.98#ibcon#enter wrdev, iclass 27, count 2 2006.201.14:15:06.98#ibcon#first serial, iclass 27, count 2 2006.201.14:15:06.98#ibcon#enter sib2, iclass 27, count 2 2006.201.14:15:06.98#ibcon#flushed, iclass 27, count 2 2006.201.14:15:06.98#ibcon#about to write, iclass 27, count 2 2006.201.14:15:06.98#ibcon#wrote, iclass 27, count 2 2006.201.14:15:06.98#ibcon#about to read 3, iclass 27, count 2 2006.201.14:15:07.00#ibcon#read 3, iclass 27, count 2 2006.201.14:15:07.00#ibcon#about to read 4, iclass 27, count 2 2006.201.14:15:07.00#ibcon#read 4, iclass 27, count 2 2006.201.14:15:07.00#ibcon#about to read 5, iclass 27, count 2 2006.201.14:15:07.00#ibcon#read 5, iclass 27, count 2 2006.201.14:15:07.00#ibcon#about to read 6, iclass 27, count 2 2006.201.14:15:07.00#ibcon#read 6, iclass 27, count 2 2006.201.14:15:07.00#ibcon#end of sib2, iclass 27, count 2 2006.201.14:15:07.00#ibcon#*mode == 0, iclass 27, count 2 2006.201.14:15:07.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.14:15:07.00#ibcon#[27=AT07-04\r\n] 2006.201.14:15:07.00#ibcon#*before write, iclass 27, count 2 2006.201.14:15:07.00#ibcon#enter sib2, iclass 27, count 2 2006.201.14:15:07.00#ibcon#flushed, iclass 27, count 2 2006.201.14:15:07.00#ibcon#about to write, iclass 27, count 2 2006.201.14:15:07.00#ibcon#wrote, iclass 27, count 2 2006.201.14:15:07.00#ibcon#about to read 3, iclass 27, count 2 2006.201.14:15:07.03#ibcon#read 3, iclass 27, count 2 2006.201.14:15:07.03#ibcon#about to read 4, iclass 27, count 2 2006.201.14:15:07.03#ibcon#read 4, iclass 27, count 2 2006.201.14:15:07.03#ibcon#about to read 5, iclass 27, count 2 2006.201.14:15:07.03#ibcon#read 5, iclass 27, count 2 2006.201.14:15:07.03#ibcon#about to read 6, iclass 27, count 2 2006.201.14:15:07.03#ibcon#read 6, iclass 27, count 2 2006.201.14:15:07.03#ibcon#end of sib2, iclass 27, count 2 2006.201.14:15:07.03#ibcon#*after write, iclass 27, count 2 2006.201.14:15:07.03#ibcon#*before return 0, iclass 27, count 2 2006.201.14:15:07.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:07.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:15:07.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.14:15:07.03#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:07.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:07.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:07.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:07.15#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:15:07.15#ibcon#first serial, iclass 27, count 0 2006.201.14:15:07.15#ibcon#enter sib2, iclass 27, count 0 2006.201.14:15:07.15#ibcon#flushed, iclass 27, count 0 2006.201.14:15:07.15#ibcon#about to write, iclass 27, count 0 2006.201.14:15:07.15#ibcon#wrote, iclass 27, count 0 2006.201.14:15:07.15#ibcon#about to read 3, iclass 27, count 0 2006.201.14:15:07.17#ibcon#read 3, iclass 27, count 0 2006.201.14:15:07.17#ibcon#about to read 4, iclass 27, count 0 2006.201.14:15:07.17#ibcon#read 4, iclass 27, count 0 2006.201.14:15:07.17#ibcon#about to read 5, iclass 27, count 0 2006.201.14:15:07.17#ibcon#read 5, iclass 27, count 0 2006.201.14:15:07.17#ibcon#about to read 6, iclass 27, count 0 2006.201.14:15:07.17#ibcon#read 6, iclass 27, count 0 2006.201.14:15:07.17#ibcon#end of sib2, iclass 27, count 0 2006.201.14:15:07.17#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:15:07.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:15:07.17#ibcon#[27=USB\r\n] 2006.201.14:15:07.17#ibcon#*before write, iclass 27, count 0 2006.201.14:15:07.17#ibcon#enter sib2, iclass 27, count 0 2006.201.14:15:07.17#ibcon#flushed, iclass 27, count 0 2006.201.14:15:07.17#ibcon#about to write, iclass 27, count 0 2006.201.14:15:07.17#ibcon#wrote, iclass 27, count 0 2006.201.14:15:07.17#ibcon#about to read 3, iclass 27, count 0 2006.201.14:15:07.20#ibcon#read 3, iclass 27, count 0 2006.201.14:15:07.20#ibcon#about to read 4, iclass 27, count 0 2006.201.14:15:07.20#ibcon#read 4, iclass 27, count 0 2006.201.14:15:07.20#ibcon#about to read 5, iclass 27, count 0 2006.201.14:15:07.20#ibcon#read 5, iclass 27, count 0 2006.201.14:15:07.20#ibcon#about to read 6, iclass 27, count 0 2006.201.14:15:07.20#ibcon#read 6, iclass 27, count 0 2006.201.14:15:07.20#ibcon#end of sib2, iclass 27, count 0 2006.201.14:15:07.20#ibcon#*after write, iclass 27, count 0 2006.201.14:15:07.20#ibcon#*before return 0, iclass 27, count 0 2006.201.14:15:07.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:07.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:15:07.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:15:07.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:15:07.20$vck44/vblo=8,744.99 2006.201.14:15:07.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.14:15:07.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.14:15:07.20#ibcon#ireg 17 cls_cnt 0 2006.201.14:15:07.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:07.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:07.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:07.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:15:07.20#ibcon#first serial, iclass 29, count 0 2006.201.14:15:07.20#ibcon#enter sib2, iclass 29, count 0 2006.201.14:15:07.20#ibcon#flushed, iclass 29, count 0 2006.201.14:15:07.20#ibcon#about to write, iclass 29, count 0 2006.201.14:15:07.20#ibcon#wrote, iclass 29, count 0 2006.201.14:15:07.20#ibcon#about to read 3, iclass 29, count 0 2006.201.14:15:07.22#ibcon#read 3, iclass 29, count 0 2006.201.14:15:07.22#ibcon#about to read 4, iclass 29, count 0 2006.201.14:15:07.22#ibcon#read 4, iclass 29, count 0 2006.201.14:15:07.22#ibcon#about to read 5, iclass 29, count 0 2006.201.14:15:07.22#ibcon#read 5, iclass 29, count 0 2006.201.14:15:07.22#ibcon#about to read 6, iclass 29, count 0 2006.201.14:15:07.22#ibcon#read 6, iclass 29, count 0 2006.201.14:15:07.22#ibcon#end of sib2, iclass 29, count 0 2006.201.14:15:07.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:15:07.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:15:07.22#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:15:07.22#ibcon#*before write, iclass 29, count 0 2006.201.14:15:07.22#ibcon#enter sib2, iclass 29, count 0 2006.201.14:15:07.22#ibcon#flushed, iclass 29, count 0 2006.201.14:15:07.22#ibcon#about to write, iclass 29, count 0 2006.201.14:15:07.22#ibcon#wrote, iclass 29, count 0 2006.201.14:15:07.22#ibcon#about to read 3, iclass 29, count 0 2006.201.14:15:07.26#ibcon#read 3, iclass 29, count 0 2006.201.14:15:07.26#ibcon#about to read 4, iclass 29, count 0 2006.201.14:15:07.26#ibcon#read 4, iclass 29, count 0 2006.201.14:15:07.26#ibcon#about to read 5, iclass 29, count 0 2006.201.14:15:07.26#ibcon#read 5, iclass 29, count 0 2006.201.14:15:07.26#ibcon#about to read 6, iclass 29, count 0 2006.201.14:15:07.26#ibcon#read 6, iclass 29, count 0 2006.201.14:15:07.26#ibcon#end of sib2, iclass 29, count 0 2006.201.14:15:07.26#ibcon#*after write, iclass 29, count 0 2006.201.14:15:07.26#ibcon#*before return 0, iclass 29, count 0 2006.201.14:15:07.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:07.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:15:07.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:15:07.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:15:07.26$vck44/vb=8,4 2006.201.14:15:07.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.14:15:07.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.14:15:07.26#ibcon#ireg 11 cls_cnt 2 2006.201.14:15:07.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:07.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:07.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:07.32#ibcon#enter wrdev, iclass 31, count 2 2006.201.14:15:07.32#ibcon#first serial, iclass 31, count 2 2006.201.14:15:07.32#ibcon#enter sib2, iclass 31, count 2 2006.201.14:15:07.32#ibcon#flushed, iclass 31, count 2 2006.201.14:15:07.32#ibcon#about to write, iclass 31, count 2 2006.201.14:15:07.32#ibcon#wrote, iclass 31, count 2 2006.201.14:15:07.32#ibcon#about to read 3, iclass 31, count 2 2006.201.14:15:07.34#ibcon#read 3, iclass 31, count 2 2006.201.14:15:07.34#ibcon#about to read 4, iclass 31, count 2 2006.201.14:15:07.34#ibcon#read 4, iclass 31, count 2 2006.201.14:15:07.34#ibcon#about to read 5, iclass 31, count 2 2006.201.14:15:07.34#ibcon#read 5, iclass 31, count 2 2006.201.14:15:07.34#ibcon#about to read 6, iclass 31, count 2 2006.201.14:15:07.34#ibcon#read 6, iclass 31, count 2 2006.201.14:15:07.34#ibcon#end of sib2, iclass 31, count 2 2006.201.14:15:07.34#ibcon#*mode == 0, iclass 31, count 2 2006.201.14:15:07.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.14:15:07.34#ibcon#[27=AT08-04\r\n] 2006.201.14:15:07.34#ibcon#*before write, iclass 31, count 2 2006.201.14:15:07.34#ibcon#enter sib2, iclass 31, count 2 2006.201.14:15:07.34#ibcon#flushed, iclass 31, count 2 2006.201.14:15:07.34#ibcon#about to write, iclass 31, count 2 2006.201.14:15:07.34#ibcon#wrote, iclass 31, count 2 2006.201.14:15:07.34#ibcon#about to read 3, iclass 31, count 2 2006.201.14:15:07.37#ibcon#read 3, iclass 31, count 2 2006.201.14:15:07.37#ibcon#about to read 4, iclass 31, count 2 2006.201.14:15:07.37#ibcon#read 4, iclass 31, count 2 2006.201.14:15:07.37#ibcon#about to read 5, iclass 31, count 2 2006.201.14:15:07.37#ibcon#read 5, iclass 31, count 2 2006.201.14:15:07.37#ibcon#about to read 6, iclass 31, count 2 2006.201.14:15:07.37#ibcon#read 6, iclass 31, count 2 2006.201.14:15:07.37#ibcon#end of sib2, iclass 31, count 2 2006.201.14:15:07.37#ibcon#*after write, iclass 31, count 2 2006.201.14:15:07.37#ibcon#*before return 0, iclass 31, count 2 2006.201.14:15:07.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:07.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:15:07.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.14:15:07.37#ibcon#ireg 7 cls_cnt 0 2006.201.14:15:07.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:07.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:07.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:07.49#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:15:07.49#ibcon#first serial, iclass 31, count 0 2006.201.14:15:07.49#ibcon#enter sib2, iclass 31, count 0 2006.201.14:15:07.49#ibcon#flushed, iclass 31, count 0 2006.201.14:15:07.49#ibcon#about to write, iclass 31, count 0 2006.201.14:15:07.49#ibcon#wrote, iclass 31, count 0 2006.201.14:15:07.49#ibcon#about to read 3, iclass 31, count 0 2006.201.14:15:07.51#ibcon#read 3, iclass 31, count 0 2006.201.14:15:07.51#ibcon#about to read 4, iclass 31, count 0 2006.201.14:15:07.51#ibcon#read 4, iclass 31, count 0 2006.201.14:15:07.51#ibcon#about to read 5, iclass 31, count 0 2006.201.14:15:07.51#ibcon#read 5, iclass 31, count 0 2006.201.14:15:07.51#ibcon#about to read 6, iclass 31, count 0 2006.201.14:15:07.51#ibcon#read 6, iclass 31, count 0 2006.201.14:15:07.51#ibcon#end of sib2, iclass 31, count 0 2006.201.14:15:07.51#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:15:07.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:15:07.51#ibcon#[27=USB\r\n] 2006.201.14:15:07.51#ibcon#*before write, iclass 31, count 0 2006.201.14:15:07.51#ibcon#enter sib2, iclass 31, count 0 2006.201.14:15:07.51#ibcon#flushed, iclass 31, count 0 2006.201.14:15:07.51#ibcon#about to write, iclass 31, count 0 2006.201.14:15:07.51#ibcon#wrote, iclass 31, count 0 2006.201.14:15:07.51#ibcon#about to read 3, iclass 31, count 0 2006.201.14:15:07.54#ibcon#read 3, iclass 31, count 0 2006.201.14:15:07.54#ibcon#about to read 4, iclass 31, count 0 2006.201.14:15:07.54#ibcon#read 4, iclass 31, count 0 2006.201.14:15:07.54#ibcon#about to read 5, iclass 31, count 0 2006.201.14:15:07.54#ibcon#read 5, iclass 31, count 0 2006.201.14:15:07.54#ibcon#about to read 6, iclass 31, count 0 2006.201.14:15:07.54#ibcon#read 6, iclass 31, count 0 2006.201.14:15:07.54#ibcon#end of sib2, iclass 31, count 0 2006.201.14:15:07.54#ibcon#*after write, iclass 31, count 0 2006.201.14:15:07.54#ibcon#*before return 0, iclass 31, count 0 2006.201.14:15:07.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:07.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:15:07.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:15:07.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:15:07.54$vck44/vabw=wide 2006.201.14:15:07.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.14:15:07.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.14:15:07.54#ibcon#ireg 8 cls_cnt 0 2006.201.14:15:07.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:07.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:07.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:07.54#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:15:07.54#ibcon#first serial, iclass 33, count 0 2006.201.14:15:07.54#ibcon#enter sib2, iclass 33, count 0 2006.201.14:15:07.54#ibcon#flushed, iclass 33, count 0 2006.201.14:15:07.54#ibcon#about to write, iclass 33, count 0 2006.201.14:15:07.54#ibcon#wrote, iclass 33, count 0 2006.201.14:15:07.54#ibcon#about to read 3, iclass 33, count 0 2006.201.14:15:07.56#ibcon#read 3, iclass 33, count 0 2006.201.14:15:07.56#ibcon#about to read 4, iclass 33, count 0 2006.201.14:15:07.56#ibcon#read 4, iclass 33, count 0 2006.201.14:15:07.56#ibcon#about to read 5, iclass 33, count 0 2006.201.14:15:07.56#ibcon#read 5, iclass 33, count 0 2006.201.14:15:07.56#ibcon#about to read 6, iclass 33, count 0 2006.201.14:15:07.56#ibcon#read 6, iclass 33, count 0 2006.201.14:15:07.56#ibcon#end of sib2, iclass 33, count 0 2006.201.14:15:07.56#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:15:07.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:15:07.56#ibcon#[25=BW32\r\n] 2006.201.14:15:07.56#ibcon#*before write, iclass 33, count 0 2006.201.14:15:07.56#ibcon#enter sib2, iclass 33, count 0 2006.201.14:15:07.56#ibcon#flushed, iclass 33, count 0 2006.201.14:15:07.56#ibcon#about to write, iclass 33, count 0 2006.201.14:15:07.56#ibcon#wrote, iclass 33, count 0 2006.201.14:15:07.56#ibcon#about to read 3, iclass 33, count 0 2006.201.14:15:07.59#ibcon#read 3, iclass 33, count 0 2006.201.14:15:07.59#ibcon#about to read 4, iclass 33, count 0 2006.201.14:15:07.59#ibcon#read 4, iclass 33, count 0 2006.201.14:15:07.59#ibcon#about to read 5, iclass 33, count 0 2006.201.14:15:07.59#ibcon#read 5, iclass 33, count 0 2006.201.14:15:07.59#ibcon#about to read 6, iclass 33, count 0 2006.201.14:15:07.59#ibcon#read 6, iclass 33, count 0 2006.201.14:15:07.59#ibcon#end of sib2, iclass 33, count 0 2006.201.14:15:07.59#ibcon#*after write, iclass 33, count 0 2006.201.14:15:07.59#ibcon#*before return 0, iclass 33, count 0 2006.201.14:15:07.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:07.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:15:07.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:15:07.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:15:07.59$vck44/vbbw=wide 2006.201.14:15:07.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.14:15:07.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.14:15:07.59#ibcon#ireg 8 cls_cnt 0 2006.201.14:15:07.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:15:07.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:15:07.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:15:07.66#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:15:07.66#ibcon#first serial, iclass 35, count 0 2006.201.14:15:07.66#ibcon#enter sib2, iclass 35, count 0 2006.201.14:15:07.66#ibcon#flushed, iclass 35, count 0 2006.201.14:15:07.66#ibcon#about to write, iclass 35, count 0 2006.201.14:15:07.66#ibcon#wrote, iclass 35, count 0 2006.201.14:15:07.66#ibcon#about to read 3, iclass 35, count 0 2006.201.14:15:07.68#ibcon#read 3, iclass 35, count 0 2006.201.14:15:07.68#ibcon#about to read 4, iclass 35, count 0 2006.201.14:15:07.68#ibcon#read 4, iclass 35, count 0 2006.201.14:15:07.68#ibcon#about to read 5, iclass 35, count 0 2006.201.14:15:07.68#ibcon#read 5, iclass 35, count 0 2006.201.14:15:07.68#ibcon#about to read 6, iclass 35, count 0 2006.201.14:15:07.68#ibcon#read 6, iclass 35, count 0 2006.201.14:15:07.68#ibcon#end of sib2, iclass 35, count 0 2006.201.14:15:07.68#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:15:07.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:15:07.68#ibcon#[27=BW32\r\n] 2006.201.14:15:07.68#ibcon#*before write, iclass 35, count 0 2006.201.14:15:07.68#ibcon#enter sib2, iclass 35, count 0 2006.201.14:15:07.68#ibcon#flushed, iclass 35, count 0 2006.201.14:15:07.68#ibcon#about to write, iclass 35, count 0 2006.201.14:15:07.68#ibcon#wrote, iclass 35, count 0 2006.201.14:15:07.68#ibcon#about to read 3, iclass 35, count 0 2006.201.14:15:07.71#ibcon#read 3, iclass 35, count 0 2006.201.14:15:07.71#ibcon#about to read 4, iclass 35, count 0 2006.201.14:15:07.71#ibcon#read 4, iclass 35, count 0 2006.201.14:15:07.71#ibcon#about to read 5, iclass 35, count 0 2006.201.14:15:07.71#ibcon#read 5, iclass 35, count 0 2006.201.14:15:07.71#ibcon#about to read 6, iclass 35, count 0 2006.201.14:15:07.71#ibcon#read 6, iclass 35, count 0 2006.201.14:15:07.71#ibcon#end of sib2, iclass 35, count 0 2006.201.14:15:07.71#ibcon#*after write, iclass 35, count 0 2006.201.14:15:07.71#ibcon#*before return 0, iclass 35, count 0 2006.201.14:15:07.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:15:07.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:15:07.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:15:07.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:15:07.71$setupk4/ifdk4 2006.201.14:15:07.71$ifdk4/lo= 2006.201.14:15:07.71$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:15:07.71$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:15:07.71$ifdk4/patch= 2006.201.14:15:07.71$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:15:07.71$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:15:07.71$setupk4/!*+20s 2006.201.14:15:08.07#abcon#<5=/05 1.5 2.7 20.851001003.5\r\n> 2006.201.14:15:08.09#abcon#{5=INTERFACE CLEAR} 2006.201.14:15:08.15#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:15:11.14#trakl#Source acquired 2006.201.14:15:11.14#flagr#flagr/antenna,acquired 2006.201.14:15:18.24#abcon#<5=/05 1.5 2.7 20.851001003.5\r\n> 2006.201.14:15:18.26#abcon#{5=INTERFACE CLEAR} 2006.201.14:15:18.32#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:15:22.22$setupk4/"tpicd 2006.201.14:15:22.22$setupk4/echo=off 2006.201.14:15:22.22$setupk4/xlog=off 2006.201.14:15:22.22:!2006.201.14:16:42 2006.201.14:16:42.00:preob 2006.201.14:16:42.14/onsource/TRACKING 2006.201.14:16:42.14:!2006.201.14:16:52 2006.201.14:16:52.00:"tape 2006.201.14:16:52.00:"st=record 2006.201.14:16:52.00:data_valid=on 2006.201.14:16:52.00:midob 2006.201.14:16:53.14/onsource/TRACKING 2006.201.14:16:53.14/wx/20.84,1003.4,100 2006.201.14:16:53.26/cable/+6.4766E-03 2006.201.14:16:54.35/va/01,08,usb,yes,29,31 2006.201.14:16:54.35/va/02,07,usb,yes,31,32 2006.201.14:16:54.35/va/03,08,usb,yes,28,29 2006.201.14:16:54.35/va/04,07,usb,yes,32,33 2006.201.14:16:54.35/va/05,04,usb,yes,28,29 2006.201.14:16:54.35/va/06,05,usb,yes,28,28 2006.201.14:16:54.35/va/07,05,usb,yes,27,28 2006.201.14:16:54.35/va/08,04,usb,yes,27,33 2006.201.14:16:54.58/valo/01,524.99,yes,locked 2006.201.14:16:54.58/valo/02,534.99,yes,locked 2006.201.14:16:54.58/valo/03,564.99,yes,locked 2006.201.14:16:54.58/valo/04,624.99,yes,locked 2006.201.14:16:54.58/valo/05,734.99,yes,locked 2006.201.14:16:54.58/valo/06,814.99,yes,locked 2006.201.14:16:54.58/valo/07,864.99,yes,locked 2006.201.14:16:54.58/valo/08,884.99,yes,locked 2006.201.14:16:55.67/vb/01,04,usb,yes,28,26 2006.201.14:16:55.67/vb/02,05,usb,yes,27,27 2006.201.14:16:55.67/vb/03,04,usb,yes,28,30 2006.201.14:16:55.67/vb/04,05,usb,yes,28,27 2006.201.14:16:55.67/vb/05,04,usb,yes,24,27 2006.201.14:16:55.67/vb/06,04,usb,yes,28,25 2006.201.14:16:55.67/vb/07,04,usb,yes,28,28 2006.201.14:16:55.67/vb/08,04,usb,yes,26,29 2006.201.14:16:55.90/vblo/01,629.99,yes,locked 2006.201.14:16:55.90/vblo/02,634.99,yes,locked 2006.201.14:16:55.90/vblo/03,649.99,yes,locked 2006.201.14:16:55.90/vblo/04,679.99,yes,locked 2006.201.14:16:55.90/vblo/05,709.99,yes,locked 2006.201.14:16:55.90/vblo/06,719.99,yes,locked 2006.201.14:16:55.90/vblo/07,734.99,yes,locked 2006.201.14:16:55.90/vblo/08,744.99,yes,locked 2006.201.14:16:56.05/vabw/8 2006.201.14:16:56.20/vbbw/8 2006.201.14:16:56.29/xfe/off,on,15.0 2006.201.14:16:56.66/ifatt/23,28,28,28 2006.201.14:16:57.06/fmout-gps/S +4.55E-07 2006.201.14:16:57.11:!2006.201.14:17:32 2006.201.14:17:32.00:data_valid=off 2006.201.14:17:32.00:"et 2006.201.14:17:32.00:!+3s 2006.201.14:17:35.02:"tape 2006.201.14:17:35.02:postob 2006.201.14:17:35.14/cable/+6.4760E-03 2006.201.14:17:35.14/wx/20.84,1003.4,100 2006.201.14:17:35.21/fmout-gps/S +4.54E-07 2006.201.14:17:35.22:scan_name=201-1418,jd0607,40 2006.201.14:17:35.22:source=1921-293,192451.06,-291430.1,2000.0,cw 2006.201.14:17:37.14#flagr#flagr/antenna,new-source 2006.201.14:17:37.14:checkk5 2006.201.14:17:37.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:17:37.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:17:38.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:17:38.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:17:39.01/chk_obsdata//k5ts1/T2011416??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:17:39.40/chk_obsdata//k5ts2/T2011416??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:17:39.77/chk_obsdata//k5ts3/T2011416??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:17:40.14/chk_obsdata//k5ts4/T2011416??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:17:40.84/k5log//k5ts1_log_newline 2006.201.14:17:41.53/k5log//k5ts2_log_newline 2006.201.14:17:42.22/k5log//k5ts3_log_newline 2006.201.14:17:42.90/k5log//k5ts4_log_newline 2006.201.14:17:42.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:17:42.93:setupk4=1 2006.201.14:17:42.93$setupk4/echo=on 2006.201.14:17:42.93$setupk4/pcalon 2006.201.14:17:42.93$pcalon/"no phase cal control is implemented here 2006.201.14:17:42.93$setupk4/"tpicd=stop 2006.201.14:17:42.93$setupk4/"rec=synch_on 2006.201.14:17:42.93$setupk4/"rec_mode=128 2006.201.14:17:42.93$setupk4/!* 2006.201.14:17:42.93$setupk4/recpk4 2006.201.14:17:42.93$recpk4/recpatch= 2006.201.14:17:42.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:17:42.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:17:42.93$setupk4/vck44 2006.201.14:17:42.93$vck44/valo=1,524.99 2006.201.14:17:42.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.14:17:42.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.14:17:42.93#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:42.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:42.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:42.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:42.93#ibcon#enter wrdev, iclass 32, count 0 2006.201.14:17:42.93#ibcon#first serial, iclass 32, count 0 2006.201.14:17:42.93#ibcon#enter sib2, iclass 32, count 0 2006.201.14:17:42.93#ibcon#flushed, iclass 32, count 0 2006.201.14:17:42.93#ibcon#about to write, iclass 32, count 0 2006.201.14:17:42.93#ibcon#wrote, iclass 32, count 0 2006.201.14:17:42.93#ibcon#about to read 3, iclass 32, count 0 2006.201.14:17:42.97#ibcon#read 3, iclass 32, count 0 2006.201.14:17:42.97#ibcon#about to read 4, iclass 32, count 0 2006.201.14:17:42.97#ibcon#read 4, iclass 32, count 0 2006.201.14:17:42.97#ibcon#about to read 5, iclass 32, count 0 2006.201.14:17:42.97#ibcon#read 5, iclass 32, count 0 2006.201.14:17:42.97#ibcon#about to read 6, iclass 32, count 0 2006.201.14:17:42.97#ibcon#read 6, iclass 32, count 0 2006.201.14:17:42.97#ibcon#end of sib2, iclass 32, count 0 2006.201.14:17:42.97#ibcon#*mode == 0, iclass 32, count 0 2006.201.14:17:42.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.14:17:42.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:17:42.97#ibcon#*before write, iclass 32, count 0 2006.201.14:17:42.97#ibcon#enter sib2, iclass 32, count 0 2006.201.14:17:42.97#ibcon#flushed, iclass 32, count 0 2006.201.14:17:42.97#ibcon#about to write, iclass 32, count 0 2006.201.14:17:42.97#ibcon#wrote, iclass 32, count 0 2006.201.14:17:42.97#ibcon#about to read 3, iclass 32, count 0 2006.201.14:17:43.02#ibcon#read 3, iclass 32, count 0 2006.201.14:17:43.02#ibcon#about to read 4, iclass 32, count 0 2006.201.14:17:43.02#ibcon#read 4, iclass 32, count 0 2006.201.14:17:43.02#ibcon#about to read 5, iclass 32, count 0 2006.201.14:17:43.02#ibcon#read 5, iclass 32, count 0 2006.201.14:17:43.02#ibcon#about to read 6, iclass 32, count 0 2006.201.14:17:43.02#ibcon#read 6, iclass 32, count 0 2006.201.14:17:43.02#ibcon#end of sib2, iclass 32, count 0 2006.201.14:17:43.02#ibcon#*after write, iclass 32, count 0 2006.201.14:17:43.02#ibcon#*before return 0, iclass 32, count 0 2006.201.14:17:43.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:43.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:43.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.14:17:43.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.14:17:43.02$vck44/va=1,8 2006.201.14:17:43.02#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.14:17:43.02#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.14:17:43.02#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:43.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:43.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:43.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:43.02#ibcon#enter wrdev, iclass 34, count 2 2006.201.14:17:43.02#ibcon#first serial, iclass 34, count 2 2006.201.14:17:43.02#ibcon#enter sib2, iclass 34, count 2 2006.201.14:17:43.02#ibcon#flushed, iclass 34, count 2 2006.201.14:17:43.02#ibcon#about to write, iclass 34, count 2 2006.201.14:17:43.02#ibcon#wrote, iclass 34, count 2 2006.201.14:17:43.02#ibcon#about to read 3, iclass 34, count 2 2006.201.14:17:43.04#ibcon#read 3, iclass 34, count 2 2006.201.14:17:43.04#ibcon#about to read 4, iclass 34, count 2 2006.201.14:17:43.04#ibcon#read 4, iclass 34, count 2 2006.201.14:17:43.04#ibcon#about to read 5, iclass 34, count 2 2006.201.14:17:43.04#ibcon#read 5, iclass 34, count 2 2006.201.14:17:43.04#ibcon#about to read 6, iclass 34, count 2 2006.201.14:17:43.04#ibcon#read 6, iclass 34, count 2 2006.201.14:17:43.04#ibcon#end of sib2, iclass 34, count 2 2006.201.14:17:43.04#ibcon#*mode == 0, iclass 34, count 2 2006.201.14:17:43.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.14:17:43.04#ibcon#[25=AT01-08\r\n] 2006.201.14:17:43.04#ibcon#*before write, iclass 34, count 2 2006.201.14:17:43.04#ibcon#enter sib2, iclass 34, count 2 2006.201.14:17:43.04#ibcon#flushed, iclass 34, count 2 2006.201.14:17:43.04#ibcon#about to write, iclass 34, count 2 2006.201.14:17:43.04#ibcon#wrote, iclass 34, count 2 2006.201.14:17:43.04#ibcon#about to read 3, iclass 34, count 2 2006.201.14:17:43.07#ibcon#read 3, iclass 34, count 2 2006.201.14:17:43.07#ibcon#about to read 4, iclass 34, count 2 2006.201.14:17:43.07#ibcon#read 4, iclass 34, count 2 2006.201.14:17:43.07#ibcon#about to read 5, iclass 34, count 2 2006.201.14:17:43.07#ibcon#read 5, iclass 34, count 2 2006.201.14:17:43.07#ibcon#about to read 6, iclass 34, count 2 2006.201.14:17:43.07#ibcon#read 6, iclass 34, count 2 2006.201.14:17:43.07#ibcon#end of sib2, iclass 34, count 2 2006.201.14:17:43.07#ibcon#*after write, iclass 34, count 2 2006.201.14:17:43.07#ibcon#*before return 0, iclass 34, count 2 2006.201.14:17:43.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:43.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:43.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.14:17:43.07#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:43.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:43.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:43.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:43.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.14:17:43.19#ibcon#first serial, iclass 34, count 0 2006.201.14:17:43.19#ibcon#enter sib2, iclass 34, count 0 2006.201.14:17:43.19#ibcon#flushed, iclass 34, count 0 2006.201.14:17:43.19#ibcon#about to write, iclass 34, count 0 2006.201.14:17:43.19#ibcon#wrote, iclass 34, count 0 2006.201.14:17:43.19#ibcon#about to read 3, iclass 34, count 0 2006.201.14:17:43.21#ibcon#read 3, iclass 34, count 0 2006.201.14:17:43.21#ibcon#about to read 4, iclass 34, count 0 2006.201.14:17:43.21#ibcon#read 4, iclass 34, count 0 2006.201.14:17:43.21#ibcon#about to read 5, iclass 34, count 0 2006.201.14:17:43.21#ibcon#read 5, iclass 34, count 0 2006.201.14:17:43.21#ibcon#about to read 6, iclass 34, count 0 2006.201.14:17:43.21#ibcon#read 6, iclass 34, count 0 2006.201.14:17:43.21#ibcon#end of sib2, iclass 34, count 0 2006.201.14:17:43.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.14:17:43.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.14:17:43.21#ibcon#[25=USB\r\n] 2006.201.14:17:43.21#ibcon#*before write, iclass 34, count 0 2006.201.14:17:43.21#ibcon#enter sib2, iclass 34, count 0 2006.201.14:17:43.21#ibcon#flushed, iclass 34, count 0 2006.201.14:17:43.21#ibcon#about to write, iclass 34, count 0 2006.201.14:17:43.21#ibcon#wrote, iclass 34, count 0 2006.201.14:17:43.21#ibcon#about to read 3, iclass 34, count 0 2006.201.14:17:43.24#ibcon#read 3, iclass 34, count 0 2006.201.14:17:43.24#ibcon#about to read 4, iclass 34, count 0 2006.201.14:17:43.24#ibcon#read 4, iclass 34, count 0 2006.201.14:17:43.24#ibcon#about to read 5, iclass 34, count 0 2006.201.14:17:43.24#ibcon#read 5, iclass 34, count 0 2006.201.14:17:43.24#ibcon#about to read 6, iclass 34, count 0 2006.201.14:17:43.24#ibcon#read 6, iclass 34, count 0 2006.201.14:17:43.24#ibcon#end of sib2, iclass 34, count 0 2006.201.14:17:43.24#ibcon#*after write, iclass 34, count 0 2006.201.14:17:43.24#ibcon#*before return 0, iclass 34, count 0 2006.201.14:17:43.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:43.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:43.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.14:17:43.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.14:17:43.24$vck44/valo=2,534.99 2006.201.14:17:43.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.14:17:43.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.14:17:43.24#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:43.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:43.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:43.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:43.24#ibcon#enter wrdev, iclass 36, count 0 2006.201.14:17:43.24#ibcon#first serial, iclass 36, count 0 2006.201.14:17:43.24#ibcon#enter sib2, iclass 36, count 0 2006.201.14:17:43.24#ibcon#flushed, iclass 36, count 0 2006.201.14:17:43.24#ibcon#about to write, iclass 36, count 0 2006.201.14:17:43.24#ibcon#wrote, iclass 36, count 0 2006.201.14:17:43.24#ibcon#about to read 3, iclass 36, count 0 2006.201.14:17:43.26#ibcon#read 3, iclass 36, count 0 2006.201.14:17:43.26#ibcon#about to read 4, iclass 36, count 0 2006.201.14:17:43.26#ibcon#read 4, iclass 36, count 0 2006.201.14:17:43.26#ibcon#about to read 5, iclass 36, count 0 2006.201.14:17:43.26#ibcon#read 5, iclass 36, count 0 2006.201.14:17:43.26#ibcon#about to read 6, iclass 36, count 0 2006.201.14:17:43.26#ibcon#read 6, iclass 36, count 0 2006.201.14:17:43.26#ibcon#end of sib2, iclass 36, count 0 2006.201.14:17:43.26#ibcon#*mode == 0, iclass 36, count 0 2006.201.14:17:43.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.14:17:43.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:17:43.26#ibcon#*before write, iclass 36, count 0 2006.201.14:17:43.26#ibcon#enter sib2, iclass 36, count 0 2006.201.14:17:43.26#ibcon#flushed, iclass 36, count 0 2006.201.14:17:43.26#ibcon#about to write, iclass 36, count 0 2006.201.14:17:43.26#ibcon#wrote, iclass 36, count 0 2006.201.14:17:43.26#ibcon#about to read 3, iclass 36, count 0 2006.201.14:17:43.31#ibcon#read 3, iclass 36, count 0 2006.201.14:17:43.31#ibcon#about to read 4, iclass 36, count 0 2006.201.14:17:43.31#ibcon#read 4, iclass 36, count 0 2006.201.14:17:43.31#ibcon#about to read 5, iclass 36, count 0 2006.201.14:17:43.31#ibcon#read 5, iclass 36, count 0 2006.201.14:17:43.31#ibcon#about to read 6, iclass 36, count 0 2006.201.14:17:43.31#ibcon#read 6, iclass 36, count 0 2006.201.14:17:43.31#ibcon#end of sib2, iclass 36, count 0 2006.201.14:17:43.31#ibcon#*after write, iclass 36, count 0 2006.201.14:17:43.31#ibcon#*before return 0, iclass 36, count 0 2006.201.14:17:43.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:43.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:43.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.14:17:43.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.14:17:43.31$vck44/va=2,7 2006.201.14:17:43.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.14:17:43.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.14:17:43.31#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:43.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:43.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:43.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:43.36#ibcon#enter wrdev, iclass 38, count 2 2006.201.14:17:43.36#ibcon#first serial, iclass 38, count 2 2006.201.14:17:43.36#ibcon#enter sib2, iclass 38, count 2 2006.201.14:17:43.36#ibcon#flushed, iclass 38, count 2 2006.201.14:17:43.36#ibcon#about to write, iclass 38, count 2 2006.201.14:17:43.36#ibcon#wrote, iclass 38, count 2 2006.201.14:17:43.36#ibcon#about to read 3, iclass 38, count 2 2006.201.14:17:43.38#ibcon#read 3, iclass 38, count 2 2006.201.14:17:43.38#ibcon#about to read 4, iclass 38, count 2 2006.201.14:17:43.38#ibcon#read 4, iclass 38, count 2 2006.201.14:17:43.38#ibcon#about to read 5, iclass 38, count 2 2006.201.14:17:43.38#ibcon#read 5, iclass 38, count 2 2006.201.14:17:43.38#ibcon#about to read 6, iclass 38, count 2 2006.201.14:17:43.38#ibcon#read 6, iclass 38, count 2 2006.201.14:17:43.38#ibcon#end of sib2, iclass 38, count 2 2006.201.14:17:43.38#ibcon#*mode == 0, iclass 38, count 2 2006.201.14:17:43.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.14:17:43.38#ibcon#[25=AT02-07\r\n] 2006.201.14:17:43.38#ibcon#*before write, iclass 38, count 2 2006.201.14:17:43.38#ibcon#enter sib2, iclass 38, count 2 2006.201.14:17:43.38#ibcon#flushed, iclass 38, count 2 2006.201.14:17:43.38#ibcon#about to write, iclass 38, count 2 2006.201.14:17:43.38#ibcon#wrote, iclass 38, count 2 2006.201.14:17:43.38#ibcon#about to read 3, iclass 38, count 2 2006.201.14:17:43.41#ibcon#read 3, iclass 38, count 2 2006.201.14:17:43.41#ibcon#about to read 4, iclass 38, count 2 2006.201.14:17:43.41#ibcon#read 4, iclass 38, count 2 2006.201.14:17:43.41#ibcon#about to read 5, iclass 38, count 2 2006.201.14:17:43.41#ibcon#read 5, iclass 38, count 2 2006.201.14:17:43.41#ibcon#about to read 6, iclass 38, count 2 2006.201.14:17:43.41#ibcon#read 6, iclass 38, count 2 2006.201.14:17:43.41#ibcon#end of sib2, iclass 38, count 2 2006.201.14:17:43.41#ibcon#*after write, iclass 38, count 2 2006.201.14:17:43.41#ibcon#*before return 0, iclass 38, count 2 2006.201.14:17:43.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:43.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:43.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.14:17:43.41#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:43.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:43.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:43.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:43.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.14:17:43.53#ibcon#first serial, iclass 38, count 0 2006.201.14:17:43.53#ibcon#enter sib2, iclass 38, count 0 2006.201.14:17:43.53#ibcon#flushed, iclass 38, count 0 2006.201.14:17:43.53#ibcon#about to write, iclass 38, count 0 2006.201.14:17:43.53#ibcon#wrote, iclass 38, count 0 2006.201.14:17:43.53#ibcon#about to read 3, iclass 38, count 0 2006.201.14:17:43.55#ibcon#read 3, iclass 38, count 0 2006.201.14:17:43.55#ibcon#about to read 4, iclass 38, count 0 2006.201.14:17:43.55#ibcon#read 4, iclass 38, count 0 2006.201.14:17:43.55#ibcon#about to read 5, iclass 38, count 0 2006.201.14:17:43.55#ibcon#read 5, iclass 38, count 0 2006.201.14:17:43.55#ibcon#about to read 6, iclass 38, count 0 2006.201.14:17:43.55#ibcon#read 6, iclass 38, count 0 2006.201.14:17:43.55#ibcon#end of sib2, iclass 38, count 0 2006.201.14:17:43.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.14:17:43.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.14:17:43.55#ibcon#[25=USB\r\n] 2006.201.14:17:43.55#ibcon#*before write, iclass 38, count 0 2006.201.14:17:43.55#ibcon#enter sib2, iclass 38, count 0 2006.201.14:17:43.55#ibcon#flushed, iclass 38, count 0 2006.201.14:17:43.55#ibcon#about to write, iclass 38, count 0 2006.201.14:17:43.55#ibcon#wrote, iclass 38, count 0 2006.201.14:17:43.55#ibcon#about to read 3, iclass 38, count 0 2006.201.14:17:43.58#ibcon#read 3, iclass 38, count 0 2006.201.14:17:43.58#ibcon#about to read 4, iclass 38, count 0 2006.201.14:17:43.58#ibcon#read 4, iclass 38, count 0 2006.201.14:17:43.58#ibcon#about to read 5, iclass 38, count 0 2006.201.14:17:43.58#ibcon#read 5, iclass 38, count 0 2006.201.14:17:43.58#ibcon#about to read 6, iclass 38, count 0 2006.201.14:17:43.58#ibcon#read 6, iclass 38, count 0 2006.201.14:17:43.58#ibcon#end of sib2, iclass 38, count 0 2006.201.14:17:43.58#ibcon#*after write, iclass 38, count 0 2006.201.14:17:43.58#ibcon#*before return 0, iclass 38, count 0 2006.201.14:17:43.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:43.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:43.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.14:17:43.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.14:17:43.58$vck44/valo=3,564.99 2006.201.14:17:43.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.14:17:43.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.14:17:43.58#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:43.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:43.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:43.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:43.58#ibcon#enter wrdev, iclass 40, count 0 2006.201.14:17:43.58#ibcon#first serial, iclass 40, count 0 2006.201.14:17:43.58#ibcon#enter sib2, iclass 40, count 0 2006.201.14:17:43.58#ibcon#flushed, iclass 40, count 0 2006.201.14:17:43.58#ibcon#about to write, iclass 40, count 0 2006.201.14:17:43.58#ibcon#wrote, iclass 40, count 0 2006.201.14:17:43.58#ibcon#about to read 3, iclass 40, count 0 2006.201.14:17:43.60#ibcon#read 3, iclass 40, count 0 2006.201.14:17:43.60#ibcon#about to read 4, iclass 40, count 0 2006.201.14:17:43.60#ibcon#read 4, iclass 40, count 0 2006.201.14:17:43.60#ibcon#about to read 5, iclass 40, count 0 2006.201.14:17:43.60#ibcon#read 5, iclass 40, count 0 2006.201.14:17:43.60#ibcon#about to read 6, iclass 40, count 0 2006.201.14:17:43.60#ibcon#read 6, iclass 40, count 0 2006.201.14:17:43.60#ibcon#end of sib2, iclass 40, count 0 2006.201.14:17:43.60#ibcon#*mode == 0, iclass 40, count 0 2006.201.14:17:43.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.14:17:43.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:17:43.60#ibcon#*before write, iclass 40, count 0 2006.201.14:17:43.60#ibcon#enter sib2, iclass 40, count 0 2006.201.14:17:43.60#ibcon#flushed, iclass 40, count 0 2006.201.14:17:43.60#ibcon#about to write, iclass 40, count 0 2006.201.14:17:43.60#ibcon#wrote, iclass 40, count 0 2006.201.14:17:43.60#ibcon#about to read 3, iclass 40, count 0 2006.201.14:17:43.65#ibcon#read 3, iclass 40, count 0 2006.201.14:17:43.65#ibcon#about to read 4, iclass 40, count 0 2006.201.14:17:43.65#ibcon#read 4, iclass 40, count 0 2006.201.14:17:43.65#ibcon#about to read 5, iclass 40, count 0 2006.201.14:17:43.65#ibcon#read 5, iclass 40, count 0 2006.201.14:17:43.65#ibcon#about to read 6, iclass 40, count 0 2006.201.14:17:43.65#ibcon#read 6, iclass 40, count 0 2006.201.14:17:43.65#ibcon#end of sib2, iclass 40, count 0 2006.201.14:17:43.65#ibcon#*after write, iclass 40, count 0 2006.201.14:17:43.65#ibcon#*before return 0, iclass 40, count 0 2006.201.14:17:43.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:43.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:43.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.14:17:43.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.14:17:43.65$vck44/va=3,8 2006.201.14:17:43.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.14:17:43.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.14:17:43.65#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:43.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:43.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:43.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:43.70#ibcon#enter wrdev, iclass 4, count 2 2006.201.14:17:43.70#ibcon#first serial, iclass 4, count 2 2006.201.14:17:43.70#ibcon#enter sib2, iclass 4, count 2 2006.201.14:17:43.70#ibcon#flushed, iclass 4, count 2 2006.201.14:17:43.70#ibcon#about to write, iclass 4, count 2 2006.201.14:17:43.70#ibcon#wrote, iclass 4, count 2 2006.201.14:17:43.70#ibcon#about to read 3, iclass 4, count 2 2006.201.14:17:43.72#ibcon#read 3, iclass 4, count 2 2006.201.14:17:43.72#ibcon#about to read 4, iclass 4, count 2 2006.201.14:17:43.72#ibcon#read 4, iclass 4, count 2 2006.201.14:17:43.72#ibcon#about to read 5, iclass 4, count 2 2006.201.14:17:43.72#ibcon#read 5, iclass 4, count 2 2006.201.14:17:43.72#ibcon#about to read 6, iclass 4, count 2 2006.201.14:17:43.72#ibcon#read 6, iclass 4, count 2 2006.201.14:17:43.72#ibcon#end of sib2, iclass 4, count 2 2006.201.14:17:43.72#ibcon#*mode == 0, iclass 4, count 2 2006.201.14:17:43.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.14:17:43.72#ibcon#[25=AT03-08\r\n] 2006.201.14:17:43.72#ibcon#*before write, iclass 4, count 2 2006.201.14:17:43.72#ibcon#enter sib2, iclass 4, count 2 2006.201.14:17:43.72#ibcon#flushed, iclass 4, count 2 2006.201.14:17:43.72#ibcon#about to write, iclass 4, count 2 2006.201.14:17:43.72#ibcon#wrote, iclass 4, count 2 2006.201.14:17:43.72#ibcon#about to read 3, iclass 4, count 2 2006.201.14:17:43.75#ibcon#read 3, iclass 4, count 2 2006.201.14:17:43.75#ibcon#about to read 4, iclass 4, count 2 2006.201.14:17:43.75#ibcon#read 4, iclass 4, count 2 2006.201.14:17:43.75#ibcon#about to read 5, iclass 4, count 2 2006.201.14:17:43.75#ibcon#read 5, iclass 4, count 2 2006.201.14:17:43.75#ibcon#about to read 6, iclass 4, count 2 2006.201.14:17:43.75#ibcon#read 6, iclass 4, count 2 2006.201.14:17:43.75#ibcon#end of sib2, iclass 4, count 2 2006.201.14:17:43.75#ibcon#*after write, iclass 4, count 2 2006.201.14:17:43.75#ibcon#*before return 0, iclass 4, count 2 2006.201.14:17:43.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:43.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:43.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.14:17:43.75#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:43.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:43.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:43.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:43.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.14:17:43.87#ibcon#first serial, iclass 4, count 0 2006.201.14:17:43.87#ibcon#enter sib2, iclass 4, count 0 2006.201.14:17:43.87#ibcon#flushed, iclass 4, count 0 2006.201.14:17:43.87#ibcon#about to write, iclass 4, count 0 2006.201.14:17:43.87#ibcon#wrote, iclass 4, count 0 2006.201.14:17:43.87#ibcon#about to read 3, iclass 4, count 0 2006.201.14:17:43.89#ibcon#read 3, iclass 4, count 0 2006.201.14:17:43.89#ibcon#about to read 4, iclass 4, count 0 2006.201.14:17:43.89#ibcon#read 4, iclass 4, count 0 2006.201.14:17:43.89#ibcon#about to read 5, iclass 4, count 0 2006.201.14:17:43.89#ibcon#read 5, iclass 4, count 0 2006.201.14:17:43.89#ibcon#about to read 6, iclass 4, count 0 2006.201.14:17:43.89#ibcon#read 6, iclass 4, count 0 2006.201.14:17:43.89#ibcon#end of sib2, iclass 4, count 0 2006.201.14:17:43.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.14:17:43.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.14:17:43.89#ibcon#[25=USB\r\n] 2006.201.14:17:43.89#ibcon#*before write, iclass 4, count 0 2006.201.14:17:43.89#ibcon#enter sib2, iclass 4, count 0 2006.201.14:17:43.89#ibcon#flushed, iclass 4, count 0 2006.201.14:17:43.89#ibcon#about to write, iclass 4, count 0 2006.201.14:17:43.89#ibcon#wrote, iclass 4, count 0 2006.201.14:17:43.89#ibcon#about to read 3, iclass 4, count 0 2006.201.14:17:43.92#ibcon#read 3, iclass 4, count 0 2006.201.14:17:43.92#ibcon#about to read 4, iclass 4, count 0 2006.201.14:17:43.92#ibcon#read 4, iclass 4, count 0 2006.201.14:17:43.92#ibcon#about to read 5, iclass 4, count 0 2006.201.14:17:43.92#ibcon#read 5, iclass 4, count 0 2006.201.14:17:43.92#ibcon#about to read 6, iclass 4, count 0 2006.201.14:17:43.92#ibcon#read 6, iclass 4, count 0 2006.201.14:17:43.92#ibcon#end of sib2, iclass 4, count 0 2006.201.14:17:43.92#ibcon#*after write, iclass 4, count 0 2006.201.14:17:43.92#ibcon#*before return 0, iclass 4, count 0 2006.201.14:17:43.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:43.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:43.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.14:17:43.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.14:17:43.92$vck44/valo=4,624.99 2006.201.14:17:43.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.14:17:43.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.14:17:43.92#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:43.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:43.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:43.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:43.92#ibcon#enter wrdev, iclass 6, count 0 2006.201.14:17:43.92#ibcon#first serial, iclass 6, count 0 2006.201.14:17:43.92#ibcon#enter sib2, iclass 6, count 0 2006.201.14:17:43.92#ibcon#flushed, iclass 6, count 0 2006.201.14:17:43.92#ibcon#about to write, iclass 6, count 0 2006.201.14:17:43.92#ibcon#wrote, iclass 6, count 0 2006.201.14:17:43.92#ibcon#about to read 3, iclass 6, count 0 2006.201.14:17:43.94#ibcon#read 3, iclass 6, count 0 2006.201.14:17:43.94#ibcon#about to read 4, iclass 6, count 0 2006.201.14:17:43.94#ibcon#read 4, iclass 6, count 0 2006.201.14:17:43.94#ibcon#about to read 5, iclass 6, count 0 2006.201.14:17:43.94#ibcon#read 5, iclass 6, count 0 2006.201.14:17:43.94#ibcon#about to read 6, iclass 6, count 0 2006.201.14:17:43.94#ibcon#read 6, iclass 6, count 0 2006.201.14:17:43.94#ibcon#end of sib2, iclass 6, count 0 2006.201.14:17:43.94#ibcon#*mode == 0, iclass 6, count 0 2006.201.14:17:43.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.14:17:43.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:17:43.94#ibcon#*before write, iclass 6, count 0 2006.201.14:17:43.94#ibcon#enter sib2, iclass 6, count 0 2006.201.14:17:43.94#ibcon#flushed, iclass 6, count 0 2006.201.14:17:43.94#ibcon#about to write, iclass 6, count 0 2006.201.14:17:43.94#ibcon#wrote, iclass 6, count 0 2006.201.14:17:43.94#ibcon#about to read 3, iclass 6, count 0 2006.201.14:17:43.99#ibcon#read 3, iclass 6, count 0 2006.201.14:17:43.99#ibcon#about to read 4, iclass 6, count 0 2006.201.14:17:43.99#ibcon#read 4, iclass 6, count 0 2006.201.14:17:43.99#ibcon#about to read 5, iclass 6, count 0 2006.201.14:17:43.99#ibcon#read 5, iclass 6, count 0 2006.201.14:17:43.99#ibcon#about to read 6, iclass 6, count 0 2006.201.14:17:43.99#ibcon#read 6, iclass 6, count 0 2006.201.14:17:43.99#ibcon#end of sib2, iclass 6, count 0 2006.201.14:17:43.99#ibcon#*after write, iclass 6, count 0 2006.201.14:17:43.99#ibcon#*before return 0, iclass 6, count 0 2006.201.14:17:43.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:43.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:43.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.14:17:43.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.14:17:43.99$vck44/va=4,7 2006.201.14:17:43.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.14:17:43.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.14:17:43.99#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:43.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:44.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:44.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:44.04#ibcon#enter wrdev, iclass 10, count 2 2006.201.14:17:44.04#ibcon#first serial, iclass 10, count 2 2006.201.14:17:44.04#ibcon#enter sib2, iclass 10, count 2 2006.201.14:17:44.04#ibcon#flushed, iclass 10, count 2 2006.201.14:17:44.04#ibcon#about to write, iclass 10, count 2 2006.201.14:17:44.04#ibcon#wrote, iclass 10, count 2 2006.201.14:17:44.04#ibcon#about to read 3, iclass 10, count 2 2006.201.14:17:44.06#ibcon#read 3, iclass 10, count 2 2006.201.14:17:44.06#ibcon#about to read 4, iclass 10, count 2 2006.201.14:17:44.06#ibcon#read 4, iclass 10, count 2 2006.201.14:17:44.06#ibcon#about to read 5, iclass 10, count 2 2006.201.14:17:44.06#ibcon#read 5, iclass 10, count 2 2006.201.14:17:44.06#ibcon#about to read 6, iclass 10, count 2 2006.201.14:17:44.06#ibcon#read 6, iclass 10, count 2 2006.201.14:17:44.06#ibcon#end of sib2, iclass 10, count 2 2006.201.14:17:44.06#ibcon#*mode == 0, iclass 10, count 2 2006.201.14:17:44.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.14:17:44.06#ibcon#[25=AT04-07\r\n] 2006.201.14:17:44.06#ibcon#*before write, iclass 10, count 2 2006.201.14:17:44.06#ibcon#enter sib2, iclass 10, count 2 2006.201.14:17:44.06#ibcon#flushed, iclass 10, count 2 2006.201.14:17:44.06#ibcon#about to write, iclass 10, count 2 2006.201.14:17:44.06#ibcon#wrote, iclass 10, count 2 2006.201.14:17:44.06#ibcon#about to read 3, iclass 10, count 2 2006.201.14:17:44.09#ibcon#read 3, iclass 10, count 2 2006.201.14:17:44.09#ibcon#about to read 4, iclass 10, count 2 2006.201.14:17:44.09#ibcon#read 4, iclass 10, count 2 2006.201.14:17:44.09#ibcon#about to read 5, iclass 10, count 2 2006.201.14:17:44.09#ibcon#read 5, iclass 10, count 2 2006.201.14:17:44.09#ibcon#about to read 6, iclass 10, count 2 2006.201.14:17:44.09#ibcon#read 6, iclass 10, count 2 2006.201.14:17:44.09#ibcon#end of sib2, iclass 10, count 2 2006.201.14:17:44.09#ibcon#*after write, iclass 10, count 2 2006.201.14:17:44.09#ibcon#*before return 0, iclass 10, count 2 2006.201.14:17:44.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:44.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:44.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.14:17:44.09#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:44.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:44.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:44.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:44.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.14:17:44.21#ibcon#first serial, iclass 10, count 0 2006.201.14:17:44.21#ibcon#enter sib2, iclass 10, count 0 2006.201.14:17:44.21#ibcon#flushed, iclass 10, count 0 2006.201.14:17:44.21#ibcon#about to write, iclass 10, count 0 2006.201.14:17:44.21#ibcon#wrote, iclass 10, count 0 2006.201.14:17:44.21#ibcon#about to read 3, iclass 10, count 0 2006.201.14:17:44.23#ibcon#read 3, iclass 10, count 0 2006.201.14:17:44.23#ibcon#about to read 4, iclass 10, count 0 2006.201.14:17:44.23#ibcon#read 4, iclass 10, count 0 2006.201.14:17:44.23#ibcon#about to read 5, iclass 10, count 0 2006.201.14:17:44.23#ibcon#read 5, iclass 10, count 0 2006.201.14:17:44.23#ibcon#about to read 6, iclass 10, count 0 2006.201.14:17:44.23#ibcon#read 6, iclass 10, count 0 2006.201.14:17:44.23#ibcon#end of sib2, iclass 10, count 0 2006.201.14:17:44.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.14:17:44.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.14:17:44.23#ibcon#[25=USB\r\n] 2006.201.14:17:44.23#ibcon#*before write, iclass 10, count 0 2006.201.14:17:44.23#ibcon#enter sib2, iclass 10, count 0 2006.201.14:17:44.23#ibcon#flushed, iclass 10, count 0 2006.201.14:17:44.23#ibcon#about to write, iclass 10, count 0 2006.201.14:17:44.23#ibcon#wrote, iclass 10, count 0 2006.201.14:17:44.23#ibcon#about to read 3, iclass 10, count 0 2006.201.14:17:44.26#ibcon#read 3, iclass 10, count 0 2006.201.14:17:44.26#ibcon#about to read 4, iclass 10, count 0 2006.201.14:17:44.26#ibcon#read 4, iclass 10, count 0 2006.201.14:17:44.26#ibcon#about to read 5, iclass 10, count 0 2006.201.14:17:44.26#ibcon#read 5, iclass 10, count 0 2006.201.14:17:44.26#ibcon#about to read 6, iclass 10, count 0 2006.201.14:17:44.26#ibcon#read 6, iclass 10, count 0 2006.201.14:17:44.26#ibcon#end of sib2, iclass 10, count 0 2006.201.14:17:44.26#ibcon#*after write, iclass 10, count 0 2006.201.14:17:44.26#ibcon#*before return 0, iclass 10, count 0 2006.201.14:17:44.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:44.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:44.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.14:17:44.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.14:17:44.26$vck44/valo=5,734.99 2006.201.14:17:44.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.14:17:44.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.14:17:44.26#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:44.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:44.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:44.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:44.26#ibcon#enter wrdev, iclass 12, count 0 2006.201.14:17:44.26#ibcon#first serial, iclass 12, count 0 2006.201.14:17:44.26#ibcon#enter sib2, iclass 12, count 0 2006.201.14:17:44.26#ibcon#flushed, iclass 12, count 0 2006.201.14:17:44.26#ibcon#about to write, iclass 12, count 0 2006.201.14:17:44.26#ibcon#wrote, iclass 12, count 0 2006.201.14:17:44.26#ibcon#about to read 3, iclass 12, count 0 2006.201.14:17:44.28#ibcon#read 3, iclass 12, count 0 2006.201.14:17:44.28#ibcon#about to read 4, iclass 12, count 0 2006.201.14:17:44.28#ibcon#read 4, iclass 12, count 0 2006.201.14:17:44.28#ibcon#about to read 5, iclass 12, count 0 2006.201.14:17:44.28#ibcon#read 5, iclass 12, count 0 2006.201.14:17:44.28#ibcon#about to read 6, iclass 12, count 0 2006.201.14:17:44.28#ibcon#read 6, iclass 12, count 0 2006.201.14:17:44.28#ibcon#end of sib2, iclass 12, count 0 2006.201.14:17:44.28#ibcon#*mode == 0, iclass 12, count 0 2006.201.14:17:44.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.14:17:44.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:17:44.28#ibcon#*before write, iclass 12, count 0 2006.201.14:17:44.28#ibcon#enter sib2, iclass 12, count 0 2006.201.14:17:44.28#ibcon#flushed, iclass 12, count 0 2006.201.14:17:44.28#ibcon#about to write, iclass 12, count 0 2006.201.14:17:44.28#ibcon#wrote, iclass 12, count 0 2006.201.14:17:44.28#ibcon#about to read 3, iclass 12, count 0 2006.201.14:17:44.32#ibcon#read 3, iclass 12, count 0 2006.201.14:17:44.32#ibcon#about to read 4, iclass 12, count 0 2006.201.14:17:44.32#ibcon#read 4, iclass 12, count 0 2006.201.14:17:44.32#ibcon#about to read 5, iclass 12, count 0 2006.201.14:17:44.32#ibcon#read 5, iclass 12, count 0 2006.201.14:17:44.32#ibcon#about to read 6, iclass 12, count 0 2006.201.14:17:44.32#ibcon#read 6, iclass 12, count 0 2006.201.14:17:44.32#ibcon#end of sib2, iclass 12, count 0 2006.201.14:17:44.32#ibcon#*after write, iclass 12, count 0 2006.201.14:17:44.32#ibcon#*before return 0, iclass 12, count 0 2006.201.14:17:44.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:44.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:44.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.14:17:44.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.14:17:44.32$vck44/va=5,4 2006.201.14:17:44.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.14:17:44.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.14:17:44.32#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:44.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:44.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:44.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:44.38#ibcon#enter wrdev, iclass 14, count 2 2006.201.14:17:44.38#ibcon#first serial, iclass 14, count 2 2006.201.14:17:44.38#ibcon#enter sib2, iclass 14, count 2 2006.201.14:17:44.38#ibcon#flushed, iclass 14, count 2 2006.201.14:17:44.38#ibcon#about to write, iclass 14, count 2 2006.201.14:17:44.38#ibcon#wrote, iclass 14, count 2 2006.201.14:17:44.38#ibcon#about to read 3, iclass 14, count 2 2006.201.14:17:44.40#ibcon#read 3, iclass 14, count 2 2006.201.14:17:44.40#ibcon#about to read 4, iclass 14, count 2 2006.201.14:17:44.40#ibcon#read 4, iclass 14, count 2 2006.201.14:17:44.40#ibcon#about to read 5, iclass 14, count 2 2006.201.14:17:44.40#ibcon#read 5, iclass 14, count 2 2006.201.14:17:44.40#ibcon#about to read 6, iclass 14, count 2 2006.201.14:17:44.40#ibcon#read 6, iclass 14, count 2 2006.201.14:17:44.40#ibcon#end of sib2, iclass 14, count 2 2006.201.14:17:44.40#ibcon#*mode == 0, iclass 14, count 2 2006.201.14:17:44.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.14:17:44.40#ibcon#[25=AT05-04\r\n] 2006.201.14:17:44.40#ibcon#*before write, iclass 14, count 2 2006.201.14:17:44.40#ibcon#enter sib2, iclass 14, count 2 2006.201.14:17:44.40#ibcon#flushed, iclass 14, count 2 2006.201.14:17:44.40#ibcon#about to write, iclass 14, count 2 2006.201.14:17:44.40#ibcon#wrote, iclass 14, count 2 2006.201.14:17:44.40#ibcon#about to read 3, iclass 14, count 2 2006.201.14:17:44.43#ibcon#read 3, iclass 14, count 2 2006.201.14:17:44.43#ibcon#about to read 4, iclass 14, count 2 2006.201.14:17:44.43#ibcon#read 4, iclass 14, count 2 2006.201.14:17:44.43#ibcon#about to read 5, iclass 14, count 2 2006.201.14:17:44.43#ibcon#read 5, iclass 14, count 2 2006.201.14:17:44.43#ibcon#about to read 6, iclass 14, count 2 2006.201.14:17:44.43#ibcon#read 6, iclass 14, count 2 2006.201.14:17:44.43#ibcon#end of sib2, iclass 14, count 2 2006.201.14:17:44.43#ibcon#*after write, iclass 14, count 2 2006.201.14:17:44.43#ibcon#*before return 0, iclass 14, count 2 2006.201.14:17:44.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:44.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:44.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.14:17:44.43#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:44.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:44.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:44.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:44.55#ibcon#enter wrdev, iclass 14, count 0 2006.201.14:17:44.55#ibcon#first serial, iclass 14, count 0 2006.201.14:17:44.55#ibcon#enter sib2, iclass 14, count 0 2006.201.14:17:44.55#ibcon#flushed, iclass 14, count 0 2006.201.14:17:44.55#ibcon#about to write, iclass 14, count 0 2006.201.14:17:44.55#ibcon#wrote, iclass 14, count 0 2006.201.14:17:44.55#ibcon#about to read 3, iclass 14, count 0 2006.201.14:17:44.57#ibcon#read 3, iclass 14, count 0 2006.201.14:17:44.57#ibcon#about to read 4, iclass 14, count 0 2006.201.14:17:44.57#ibcon#read 4, iclass 14, count 0 2006.201.14:17:44.57#ibcon#about to read 5, iclass 14, count 0 2006.201.14:17:44.57#ibcon#read 5, iclass 14, count 0 2006.201.14:17:44.57#ibcon#about to read 6, iclass 14, count 0 2006.201.14:17:44.57#ibcon#read 6, iclass 14, count 0 2006.201.14:17:44.57#ibcon#end of sib2, iclass 14, count 0 2006.201.14:17:44.57#ibcon#*mode == 0, iclass 14, count 0 2006.201.14:17:44.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.14:17:44.57#ibcon#[25=USB\r\n] 2006.201.14:17:44.57#ibcon#*before write, iclass 14, count 0 2006.201.14:17:44.57#ibcon#enter sib2, iclass 14, count 0 2006.201.14:17:44.57#ibcon#flushed, iclass 14, count 0 2006.201.14:17:44.57#ibcon#about to write, iclass 14, count 0 2006.201.14:17:44.57#ibcon#wrote, iclass 14, count 0 2006.201.14:17:44.57#ibcon#about to read 3, iclass 14, count 0 2006.201.14:17:44.60#ibcon#read 3, iclass 14, count 0 2006.201.14:17:44.60#ibcon#about to read 4, iclass 14, count 0 2006.201.14:17:44.60#ibcon#read 4, iclass 14, count 0 2006.201.14:17:44.60#ibcon#about to read 5, iclass 14, count 0 2006.201.14:17:44.60#ibcon#read 5, iclass 14, count 0 2006.201.14:17:44.60#ibcon#about to read 6, iclass 14, count 0 2006.201.14:17:44.60#ibcon#read 6, iclass 14, count 0 2006.201.14:17:44.60#ibcon#end of sib2, iclass 14, count 0 2006.201.14:17:44.60#ibcon#*after write, iclass 14, count 0 2006.201.14:17:44.60#ibcon#*before return 0, iclass 14, count 0 2006.201.14:17:44.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:44.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:44.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.14:17:44.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.14:17:44.60$vck44/valo=6,814.99 2006.201.14:17:44.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.14:17:44.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.14:17:44.60#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:44.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:44.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:44.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:44.60#ibcon#enter wrdev, iclass 16, count 0 2006.201.14:17:44.60#ibcon#first serial, iclass 16, count 0 2006.201.14:17:44.60#ibcon#enter sib2, iclass 16, count 0 2006.201.14:17:44.60#ibcon#flushed, iclass 16, count 0 2006.201.14:17:44.60#ibcon#about to write, iclass 16, count 0 2006.201.14:17:44.60#ibcon#wrote, iclass 16, count 0 2006.201.14:17:44.60#ibcon#about to read 3, iclass 16, count 0 2006.201.14:17:44.62#ibcon#read 3, iclass 16, count 0 2006.201.14:17:44.62#ibcon#about to read 4, iclass 16, count 0 2006.201.14:17:44.62#ibcon#read 4, iclass 16, count 0 2006.201.14:17:44.62#ibcon#about to read 5, iclass 16, count 0 2006.201.14:17:44.62#ibcon#read 5, iclass 16, count 0 2006.201.14:17:44.62#ibcon#about to read 6, iclass 16, count 0 2006.201.14:17:44.62#ibcon#read 6, iclass 16, count 0 2006.201.14:17:44.62#ibcon#end of sib2, iclass 16, count 0 2006.201.14:17:44.62#ibcon#*mode == 0, iclass 16, count 0 2006.201.14:17:44.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.14:17:44.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:17:44.62#ibcon#*before write, iclass 16, count 0 2006.201.14:17:44.62#ibcon#enter sib2, iclass 16, count 0 2006.201.14:17:44.62#ibcon#flushed, iclass 16, count 0 2006.201.14:17:44.62#ibcon#about to write, iclass 16, count 0 2006.201.14:17:44.62#ibcon#wrote, iclass 16, count 0 2006.201.14:17:44.62#ibcon#about to read 3, iclass 16, count 0 2006.201.14:17:44.66#ibcon#read 3, iclass 16, count 0 2006.201.14:17:44.66#ibcon#about to read 4, iclass 16, count 0 2006.201.14:17:44.66#ibcon#read 4, iclass 16, count 0 2006.201.14:17:44.66#ibcon#about to read 5, iclass 16, count 0 2006.201.14:17:44.66#ibcon#read 5, iclass 16, count 0 2006.201.14:17:44.66#ibcon#about to read 6, iclass 16, count 0 2006.201.14:17:44.66#ibcon#read 6, iclass 16, count 0 2006.201.14:17:44.66#ibcon#end of sib2, iclass 16, count 0 2006.201.14:17:44.66#ibcon#*after write, iclass 16, count 0 2006.201.14:17:44.66#ibcon#*before return 0, iclass 16, count 0 2006.201.14:17:44.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:44.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:44.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.14:17:44.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.14:17:44.66$vck44/va=6,5 2006.201.14:17:44.66#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.14:17:44.66#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.14:17:44.66#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:44.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:44.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:44.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:44.72#ibcon#enter wrdev, iclass 18, count 2 2006.201.14:17:44.72#ibcon#first serial, iclass 18, count 2 2006.201.14:17:44.72#ibcon#enter sib2, iclass 18, count 2 2006.201.14:17:44.72#ibcon#flushed, iclass 18, count 2 2006.201.14:17:44.72#ibcon#about to write, iclass 18, count 2 2006.201.14:17:44.72#ibcon#wrote, iclass 18, count 2 2006.201.14:17:44.72#ibcon#about to read 3, iclass 18, count 2 2006.201.14:17:44.74#ibcon#read 3, iclass 18, count 2 2006.201.14:17:44.74#ibcon#about to read 4, iclass 18, count 2 2006.201.14:17:44.74#ibcon#read 4, iclass 18, count 2 2006.201.14:17:44.74#ibcon#about to read 5, iclass 18, count 2 2006.201.14:17:44.74#ibcon#read 5, iclass 18, count 2 2006.201.14:17:44.74#ibcon#about to read 6, iclass 18, count 2 2006.201.14:17:44.74#ibcon#read 6, iclass 18, count 2 2006.201.14:17:44.74#ibcon#end of sib2, iclass 18, count 2 2006.201.14:17:44.74#ibcon#*mode == 0, iclass 18, count 2 2006.201.14:17:44.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.14:17:44.74#ibcon#[25=AT06-05\r\n] 2006.201.14:17:44.74#ibcon#*before write, iclass 18, count 2 2006.201.14:17:44.74#ibcon#enter sib2, iclass 18, count 2 2006.201.14:17:44.74#ibcon#flushed, iclass 18, count 2 2006.201.14:17:44.74#ibcon#about to write, iclass 18, count 2 2006.201.14:17:44.74#ibcon#wrote, iclass 18, count 2 2006.201.14:17:44.74#ibcon#about to read 3, iclass 18, count 2 2006.201.14:17:44.77#ibcon#read 3, iclass 18, count 2 2006.201.14:17:44.77#ibcon#about to read 4, iclass 18, count 2 2006.201.14:17:44.77#ibcon#read 4, iclass 18, count 2 2006.201.14:17:44.77#ibcon#about to read 5, iclass 18, count 2 2006.201.14:17:44.77#ibcon#read 5, iclass 18, count 2 2006.201.14:17:44.77#ibcon#about to read 6, iclass 18, count 2 2006.201.14:17:44.77#ibcon#read 6, iclass 18, count 2 2006.201.14:17:44.77#ibcon#end of sib2, iclass 18, count 2 2006.201.14:17:44.77#ibcon#*after write, iclass 18, count 2 2006.201.14:17:44.77#ibcon#*before return 0, iclass 18, count 2 2006.201.14:17:44.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:44.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:44.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.14:17:44.77#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:44.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:44.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:44.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:44.89#ibcon#enter wrdev, iclass 18, count 0 2006.201.14:17:44.89#ibcon#first serial, iclass 18, count 0 2006.201.14:17:44.89#ibcon#enter sib2, iclass 18, count 0 2006.201.14:17:44.89#ibcon#flushed, iclass 18, count 0 2006.201.14:17:44.89#ibcon#about to write, iclass 18, count 0 2006.201.14:17:44.89#ibcon#wrote, iclass 18, count 0 2006.201.14:17:44.89#ibcon#about to read 3, iclass 18, count 0 2006.201.14:17:44.91#ibcon#read 3, iclass 18, count 0 2006.201.14:17:44.91#ibcon#about to read 4, iclass 18, count 0 2006.201.14:17:44.91#ibcon#read 4, iclass 18, count 0 2006.201.14:17:44.91#ibcon#about to read 5, iclass 18, count 0 2006.201.14:17:44.91#ibcon#read 5, iclass 18, count 0 2006.201.14:17:44.91#ibcon#about to read 6, iclass 18, count 0 2006.201.14:17:44.91#ibcon#read 6, iclass 18, count 0 2006.201.14:17:44.91#ibcon#end of sib2, iclass 18, count 0 2006.201.14:17:44.91#ibcon#*mode == 0, iclass 18, count 0 2006.201.14:17:44.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.14:17:44.91#ibcon#[25=USB\r\n] 2006.201.14:17:44.91#ibcon#*before write, iclass 18, count 0 2006.201.14:17:44.91#ibcon#enter sib2, iclass 18, count 0 2006.201.14:17:44.91#ibcon#flushed, iclass 18, count 0 2006.201.14:17:44.91#ibcon#about to write, iclass 18, count 0 2006.201.14:17:44.91#ibcon#wrote, iclass 18, count 0 2006.201.14:17:44.91#ibcon#about to read 3, iclass 18, count 0 2006.201.14:17:44.94#ibcon#read 3, iclass 18, count 0 2006.201.14:17:44.94#ibcon#about to read 4, iclass 18, count 0 2006.201.14:17:44.94#ibcon#read 4, iclass 18, count 0 2006.201.14:17:44.94#ibcon#about to read 5, iclass 18, count 0 2006.201.14:17:44.94#ibcon#read 5, iclass 18, count 0 2006.201.14:17:44.94#ibcon#about to read 6, iclass 18, count 0 2006.201.14:17:44.94#ibcon#read 6, iclass 18, count 0 2006.201.14:17:44.94#ibcon#end of sib2, iclass 18, count 0 2006.201.14:17:44.94#ibcon#*after write, iclass 18, count 0 2006.201.14:17:44.94#ibcon#*before return 0, iclass 18, count 0 2006.201.14:17:44.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:44.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:44.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.14:17:44.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.14:17:44.94$vck44/valo=7,864.99 2006.201.14:17:44.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.14:17:44.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.14:17:44.94#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:44.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:44.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:44.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:44.94#ibcon#enter wrdev, iclass 20, count 0 2006.201.14:17:44.94#ibcon#first serial, iclass 20, count 0 2006.201.14:17:44.94#ibcon#enter sib2, iclass 20, count 0 2006.201.14:17:44.94#ibcon#flushed, iclass 20, count 0 2006.201.14:17:44.94#ibcon#about to write, iclass 20, count 0 2006.201.14:17:44.94#ibcon#wrote, iclass 20, count 0 2006.201.14:17:44.94#ibcon#about to read 3, iclass 20, count 0 2006.201.14:17:44.96#ibcon#read 3, iclass 20, count 0 2006.201.14:17:44.96#ibcon#about to read 4, iclass 20, count 0 2006.201.14:17:44.96#ibcon#read 4, iclass 20, count 0 2006.201.14:17:44.96#ibcon#about to read 5, iclass 20, count 0 2006.201.14:17:44.96#ibcon#read 5, iclass 20, count 0 2006.201.14:17:44.96#ibcon#about to read 6, iclass 20, count 0 2006.201.14:17:44.96#ibcon#read 6, iclass 20, count 0 2006.201.14:17:44.96#ibcon#end of sib2, iclass 20, count 0 2006.201.14:17:44.96#ibcon#*mode == 0, iclass 20, count 0 2006.201.14:17:44.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.14:17:44.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:17:44.96#ibcon#*before write, iclass 20, count 0 2006.201.14:17:44.96#ibcon#enter sib2, iclass 20, count 0 2006.201.14:17:44.96#ibcon#flushed, iclass 20, count 0 2006.201.14:17:44.96#ibcon#about to write, iclass 20, count 0 2006.201.14:17:44.96#ibcon#wrote, iclass 20, count 0 2006.201.14:17:44.96#ibcon#about to read 3, iclass 20, count 0 2006.201.14:17:45.01#ibcon#read 3, iclass 20, count 0 2006.201.14:17:45.01#ibcon#about to read 4, iclass 20, count 0 2006.201.14:17:45.01#ibcon#read 4, iclass 20, count 0 2006.201.14:17:45.01#ibcon#about to read 5, iclass 20, count 0 2006.201.14:17:45.01#ibcon#read 5, iclass 20, count 0 2006.201.14:17:45.01#ibcon#about to read 6, iclass 20, count 0 2006.201.14:17:45.01#ibcon#read 6, iclass 20, count 0 2006.201.14:17:45.01#ibcon#end of sib2, iclass 20, count 0 2006.201.14:17:45.01#ibcon#*after write, iclass 20, count 0 2006.201.14:17:45.01#ibcon#*before return 0, iclass 20, count 0 2006.201.14:17:45.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:45.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:45.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.14:17:45.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.14:17:45.01$vck44/va=7,5 2006.201.14:17:45.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.14:17:45.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.14:17:45.01#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:45.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:45.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:45.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:45.06#ibcon#enter wrdev, iclass 22, count 2 2006.201.14:17:45.06#ibcon#first serial, iclass 22, count 2 2006.201.14:17:45.06#ibcon#enter sib2, iclass 22, count 2 2006.201.14:17:45.06#ibcon#flushed, iclass 22, count 2 2006.201.14:17:45.06#ibcon#about to write, iclass 22, count 2 2006.201.14:17:45.06#ibcon#wrote, iclass 22, count 2 2006.201.14:17:45.06#ibcon#about to read 3, iclass 22, count 2 2006.201.14:17:45.08#ibcon#read 3, iclass 22, count 2 2006.201.14:17:45.08#ibcon#about to read 4, iclass 22, count 2 2006.201.14:17:45.08#ibcon#read 4, iclass 22, count 2 2006.201.14:17:45.08#ibcon#about to read 5, iclass 22, count 2 2006.201.14:17:45.08#ibcon#read 5, iclass 22, count 2 2006.201.14:17:45.08#ibcon#about to read 6, iclass 22, count 2 2006.201.14:17:45.08#ibcon#read 6, iclass 22, count 2 2006.201.14:17:45.08#ibcon#end of sib2, iclass 22, count 2 2006.201.14:17:45.08#ibcon#*mode == 0, iclass 22, count 2 2006.201.14:17:45.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.14:17:45.08#ibcon#[25=AT07-05\r\n] 2006.201.14:17:45.08#ibcon#*before write, iclass 22, count 2 2006.201.14:17:45.08#ibcon#enter sib2, iclass 22, count 2 2006.201.14:17:45.08#ibcon#flushed, iclass 22, count 2 2006.201.14:17:45.08#ibcon#about to write, iclass 22, count 2 2006.201.14:17:45.08#ibcon#wrote, iclass 22, count 2 2006.201.14:17:45.08#ibcon#about to read 3, iclass 22, count 2 2006.201.14:17:45.11#ibcon#read 3, iclass 22, count 2 2006.201.14:17:45.11#ibcon#about to read 4, iclass 22, count 2 2006.201.14:17:45.11#ibcon#read 4, iclass 22, count 2 2006.201.14:17:45.11#ibcon#about to read 5, iclass 22, count 2 2006.201.14:17:45.11#ibcon#read 5, iclass 22, count 2 2006.201.14:17:45.11#ibcon#about to read 6, iclass 22, count 2 2006.201.14:17:45.11#ibcon#read 6, iclass 22, count 2 2006.201.14:17:45.11#ibcon#end of sib2, iclass 22, count 2 2006.201.14:17:45.11#ibcon#*after write, iclass 22, count 2 2006.201.14:17:45.11#ibcon#*before return 0, iclass 22, count 2 2006.201.14:17:45.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:45.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:45.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.14:17:45.11#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:45.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:45.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:45.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:45.23#ibcon#enter wrdev, iclass 22, count 0 2006.201.14:17:45.23#ibcon#first serial, iclass 22, count 0 2006.201.14:17:45.23#ibcon#enter sib2, iclass 22, count 0 2006.201.14:17:45.23#ibcon#flushed, iclass 22, count 0 2006.201.14:17:45.23#ibcon#about to write, iclass 22, count 0 2006.201.14:17:45.23#ibcon#wrote, iclass 22, count 0 2006.201.14:17:45.23#ibcon#about to read 3, iclass 22, count 0 2006.201.14:17:45.25#ibcon#read 3, iclass 22, count 0 2006.201.14:17:45.25#ibcon#about to read 4, iclass 22, count 0 2006.201.14:17:45.25#ibcon#read 4, iclass 22, count 0 2006.201.14:17:45.25#ibcon#about to read 5, iclass 22, count 0 2006.201.14:17:45.25#ibcon#read 5, iclass 22, count 0 2006.201.14:17:45.25#ibcon#about to read 6, iclass 22, count 0 2006.201.14:17:45.25#ibcon#read 6, iclass 22, count 0 2006.201.14:17:45.25#ibcon#end of sib2, iclass 22, count 0 2006.201.14:17:45.25#ibcon#*mode == 0, iclass 22, count 0 2006.201.14:17:45.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.14:17:45.25#ibcon#[25=USB\r\n] 2006.201.14:17:45.25#ibcon#*before write, iclass 22, count 0 2006.201.14:17:45.25#ibcon#enter sib2, iclass 22, count 0 2006.201.14:17:45.25#ibcon#flushed, iclass 22, count 0 2006.201.14:17:45.25#ibcon#about to write, iclass 22, count 0 2006.201.14:17:45.25#ibcon#wrote, iclass 22, count 0 2006.201.14:17:45.25#ibcon#about to read 3, iclass 22, count 0 2006.201.14:17:45.28#ibcon#read 3, iclass 22, count 0 2006.201.14:17:45.28#ibcon#about to read 4, iclass 22, count 0 2006.201.14:17:45.28#ibcon#read 4, iclass 22, count 0 2006.201.14:17:45.28#ibcon#about to read 5, iclass 22, count 0 2006.201.14:17:45.28#ibcon#read 5, iclass 22, count 0 2006.201.14:17:45.28#ibcon#about to read 6, iclass 22, count 0 2006.201.14:17:45.28#ibcon#read 6, iclass 22, count 0 2006.201.14:17:45.28#ibcon#end of sib2, iclass 22, count 0 2006.201.14:17:45.28#ibcon#*after write, iclass 22, count 0 2006.201.14:17:45.28#ibcon#*before return 0, iclass 22, count 0 2006.201.14:17:45.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:45.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:45.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.14:17:45.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.14:17:45.28$vck44/valo=8,884.99 2006.201.14:17:45.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.14:17:45.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.14:17:45.28#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:45.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:45.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:45.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:45.28#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:17:45.28#ibcon#first serial, iclass 24, count 0 2006.201.14:17:45.28#ibcon#enter sib2, iclass 24, count 0 2006.201.14:17:45.28#ibcon#flushed, iclass 24, count 0 2006.201.14:17:45.28#ibcon#about to write, iclass 24, count 0 2006.201.14:17:45.28#ibcon#wrote, iclass 24, count 0 2006.201.14:17:45.28#ibcon#about to read 3, iclass 24, count 0 2006.201.14:17:45.30#ibcon#read 3, iclass 24, count 0 2006.201.14:17:45.30#ibcon#about to read 4, iclass 24, count 0 2006.201.14:17:45.30#ibcon#read 4, iclass 24, count 0 2006.201.14:17:45.30#ibcon#about to read 5, iclass 24, count 0 2006.201.14:17:45.30#ibcon#read 5, iclass 24, count 0 2006.201.14:17:45.30#ibcon#about to read 6, iclass 24, count 0 2006.201.14:17:45.30#ibcon#read 6, iclass 24, count 0 2006.201.14:17:45.30#ibcon#end of sib2, iclass 24, count 0 2006.201.14:17:45.30#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:17:45.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:17:45.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:17:45.30#ibcon#*before write, iclass 24, count 0 2006.201.14:17:45.30#ibcon#enter sib2, iclass 24, count 0 2006.201.14:17:45.30#ibcon#flushed, iclass 24, count 0 2006.201.14:17:45.30#ibcon#about to write, iclass 24, count 0 2006.201.14:17:45.30#ibcon#wrote, iclass 24, count 0 2006.201.14:17:45.30#ibcon#about to read 3, iclass 24, count 0 2006.201.14:17:45.34#ibcon#read 3, iclass 24, count 0 2006.201.14:17:45.34#ibcon#about to read 4, iclass 24, count 0 2006.201.14:17:45.34#ibcon#read 4, iclass 24, count 0 2006.201.14:17:45.34#ibcon#about to read 5, iclass 24, count 0 2006.201.14:17:45.34#ibcon#read 5, iclass 24, count 0 2006.201.14:17:45.34#ibcon#about to read 6, iclass 24, count 0 2006.201.14:17:45.34#ibcon#read 6, iclass 24, count 0 2006.201.14:17:45.34#ibcon#end of sib2, iclass 24, count 0 2006.201.14:17:45.34#ibcon#*after write, iclass 24, count 0 2006.201.14:17:45.34#ibcon#*before return 0, iclass 24, count 0 2006.201.14:17:45.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:45.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:45.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:17:45.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:17:45.34$vck44/va=8,4 2006.201.14:17:45.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.14:17:45.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.14:17:45.34#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:45.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:17:45.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:17:45.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:17:45.40#ibcon#enter wrdev, iclass 26, count 2 2006.201.14:17:45.40#ibcon#first serial, iclass 26, count 2 2006.201.14:17:45.40#ibcon#enter sib2, iclass 26, count 2 2006.201.14:17:45.40#ibcon#flushed, iclass 26, count 2 2006.201.14:17:45.40#ibcon#about to write, iclass 26, count 2 2006.201.14:17:45.40#ibcon#wrote, iclass 26, count 2 2006.201.14:17:45.40#ibcon#about to read 3, iclass 26, count 2 2006.201.14:17:45.42#ibcon#read 3, iclass 26, count 2 2006.201.14:17:45.42#ibcon#about to read 4, iclass 26, count 2 2006.201.14:17:45.42#ibcon#read 4, iclass 26, count 2 2006.201.14:17:45.42#ibcon#about to read 5, iclass 26, count 2 2006.201.14:17:45.42#ibcon#read 5, iclass 26, count 2 2006.201.14:17:45.42#ibcon#about to read 6, iclass 26, count 2 2006.201.14:17:45.42#ibcon#read 6, iclass 26, count 2 2006.201.14:17:45.42#ibcon#end of sib2, iclass 26, count 2 2006.201.14:17:45.42#ibcon#*mode == 0, iclass 26, count 2 2006.201.14:17:45.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.14:17:45.42#ibcon#[25=AT08-04\r\n] 2006.201.14:17:45.42#ibcon#*before write, iclass 26, count 2 2006.201.14:17:45.42#ibcon#enter sib2, iclass 26, count 2 2006.201.14:17:45.42#ibcon#flushed, iclass 26, count 2 2006.201.14:17:45.42#ibcon#about to write, iclass 26, count 2 2006.201.14:17:45.42#ibcon#wrote, iclass 26, count 2 2006.201.14:17:45.42#ibcon#about to read 3, iclass 26, count 2 2006.201.14:17:45.45#ibcon#read 3, iclass 26, count 2 2006.201.14:17:45.45#ibcon#about to read 4, iclass 26, count 2 2006.201.14:17:45.45#ibcon#read 4, iclass 26, count 2 2006.201.14:17:45.45#ibcon#about to read 5, iclass 26, count 2 2006.201.14:17:45.45#ibcon#read 5, iclass 26, count 2 2006.201.14:17:45.45#ibcon#about to read 6, iclass 26, count 2 2006.201.14:17:45.45#ibcon#read 6, iclass 26, count 2 2006.201.14:17:45.45#ibcon#end of sib2, iclass 26, count 2 2006.201.14:17:45.45#ibcon#*after write, iclass 26, count 2 2006.201.14:17:45.45#ibcon#*before return 0, iclass 26, count 2 2006.201.14:17:45.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:17:45.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:17:45.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.14:17:45.45#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:45.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:17:45.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:17:45.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:17:45.57#ibcon#enter wrdev, iclass 26, count 0 2006.201.14:17:45.57#ibcon#first serial, iclass 26, count 0 2006.201.14:17:45.57#ibcon#enter sib2, iclass 26, count 0 2006.201.14:17:45.57#ibcon#flushed, iclass 26, count 0 2006.201.14:17:45.57#ibcon#about to write, iclass 26, count 0 2006.201.14:17:45.57#ibcon#wrote, iclass 26, count 0 2006.201.14:17:45.57#ibcon#about to read 3, iclass 26, count 0 2006.201.14:17:45.59#ibcon#read 3, iclass 26, count 0 2006.201.14:17:45.59#ibcon#about to read 4, iclass 26, count 0 2006.201.14:17:45.59#ibcon#read 4, iclass 26, count 0 2006.201.14:17:45.59#ibcon#about to read 5, iclass 26, count 0 2006.201.14:17:45.59#ibcon#read 5, iclass 26, count 0 2006.201.14:17:45.59#ibcon#about to read 6, iclass 26, count 0 2006.201.14:17:45.59#ibcon#read 6, iclass 26, count 0 2006.201.14:17:45.59#ibcon#end of sib2, iclass 26, count 0 2006.201.14:17:45.59#ibcon#*mode == 0, iclass 26, count 0 2006.201.14:17:45.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.14:17:45.59#ibcon#[25=USB\r\n] 2006.201.14:17:45.59#ibcon#*before write, iclass 26, count 0 2006.201.14:17:45.59#ibcon#enter sib2, iclass 26, count 0 2006.201.14:17:45.59#ibcon#flushed, iclass 26, count 0 2006.201.14:17:45.59#ibcon#about to write, iclass 26, count 0 2006.201.14:17:45.59#ibcon#wrote, iclass 26, count 0 2006.201.14:17:45.59#ibcon#about to read 3, iclass 26, count 0 2006.201.14:17:45.62#ibcon#read 3, iclass 26, count 0 2006.201.14:17:45.62#ibcon#about to read 4, iclass 26, count 0 2006.201.14:17:45.62#ibcon#read 4, iclass 26, count 0 2006.201.14:17:45.62#ibcon#about to read 5, iclass 26, count 0 2006.201.14:17:45.62#ibcon#read 5, iclass 26, count 0 2006.201.14:17:45.62#ibcon#about to read 6, iclass 26, count 0 2006.201.14:17:45.62#ibcon#read 6, iclass 26, count 0 2006.201.14:17:45.62#ibcon#end of sib2, iclass 26, count 0 2006.201.14:17:45.62#ibcon#*after write, iclass 26, count 0 2006.201.14:17:45.62#ibcon#*before return 0, iclass 26, count 0 2006.201.14:17:45.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:17:45.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:17:45.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.14:17:45.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.14:17:45.62$vck44/vblo=1,629.99 2006.201.14:17:45.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.14:17:45.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.14:17:45.62#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:45.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:17:45.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:17:45.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:17:45.62#ibcon#enter wrdev, iclass 28, count 0 2006.201.14:17:45.62#ibcon#first serial, iclass 28, count 0 2006.201.14:17:45.62#ibcon#enter sib2, iclass 28, count 0 2006.201.14:17:45.62#ibcon#flushed, iclass 28, count 0 2006.201.14:17:45.62#ibcon#about to write, iclass 28, count 0 2006.201.14:17:45.62#ibcon#wrote, iclass 28, count 0 2006.201.14:17:45.62#ibcon#about to read 3, iclass 28, count 0 2006.201.14:17:45.64#ibcon#read 3, iclass 28, count 0 2006.201.14:17:45.64#ibcon#about to read 4, iclass 28, count 0 2006.201.14:17:45.64#ibcon#read 4, iclass 28, count 0 2006.201.14:17:45.64#ibcon#about to read 5, iclass 28, count 0 2006.201.14:17:45.64#ibcon#read 5, iclass 28, count 0 2006.201.14:17:45.64#ibcon#about to read 6, iclass 28, count 0 2006.201.14:17:45.64#ibcon#read 6, iclass 28, count 0 2006.201.14:17:45.64#ibcon#end of sib2, iclass 28, count 0 2006.201.14:17:45.64#ibcon#*mode == 0, iclass 28, count 0 2006.201.14:17:45.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.14:17:45.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:17:45.64#ibcon#*before write, iclass 28, count 0 2006.201.14:17:45.64#ibcon#enter sib2, iclass 28, count 0 2006.201.14:17:45.64#ibcon#flushed, iclass 28, count 0 2006.201.14:17:45.64#ibcon#about to write, iclass 28, count 0 2006.201.14:17:45.64#ibcon#wrote, iclass 28, count 0 2006.201.14:17:45.64#ibcon#about to read 3, iclass 28, count 0 2006.201.14:17:45.69#ibcon#read 3, iclass 28, count 0 2006.201.14:17:45.69#ibcon#about to read 4, iclass 28, count 0 2006.201.14:17:45.69#ibcon#read 4, iclass 28, count 0 2006.201.14:17:45.69#ibcon#about to read 5, iclass 28, count 0 2006.201.14:17:45.69#ibcon#read 5, iclass 28, count 0 2006.201.14:17:45.69#ibcon#about to read 6, iclass 28, count 0 2006.201.14:17:45.69#ibcon#read 6, iclass 28, count 0 2006.201.14:17:45.69#ibcon#end of sib2, iclass 28, count 0 2006.201.14:17:45.69#ibcon#*after write, iclass 28, count 0 2006.201.14:17:45.69#ibcon#*before return 0, iclass 28, count 0 2006.201.14:17:45.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:17:45.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:17:45.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.14:17:45.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.14:17:45.69$vck44/vb=1,4 2006.201.14:17:45.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.14:17:45.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.14:17:45.69#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:45.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:17:45.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:17:45.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:17:45.69#ibcon#enter wrdev, iclass 30, count 2 2006.201.14:17:45.69#ibcon#first serial, iclass 30, count 2 2006.201.14:17:45.69#ibcon#enter sib2, iclass 30, count 2 2006.201.14:17:45.69#ibcon#flushed, iclass 30, count 2 2006.201.14:17:45.69#ibcon#about to write, iclass 30, count 2 2006.201.14:17:45.69#ibcon#wrote, iclass 30, count 2 2006.201.14:17:45.69#ibcon#about to read 3, iclass 30, count 2 2006.201.14:17:45.71#ibcon#read 3, iclass 30, count 2 2006.201.14:17:45.71#ibcon#about to read 4, iclass 30, count 2 2006.201.14:17:45.71#ibcon#read 4, iclass 30, count 2 2006.201.14:17:45.71#ibcon#about to read 5, iclass 30, count 2 2006.201.14:17:45.71#ibcon#read 5, iclass 30, count 2 2006.201.14:17:45.71#ibcon#about to read 6, iclass 30, count 2 2006.201.14:17:45.71#ibcon#read 6, iclass 30, count 2 2006.201.14:17:45.71#ibcon#end of sib2, iclass 30, count 2 2006.201.14:17:45.71#ibcon#*mode == 0, iclass 30, count 2 2006.201.14:17:45.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.14:17:45.71#ibcon#[27=AT01-04\r\n] 2006.201.14:17:45.71#ibcon#*before write, iclass 30, count 2 2006.201.14:17:45.71#ibcon#enter sib2, iclass 30, count 2 2006.201.14:17:45.71#ibcon#flushed, iclass 30, count 2 2006.201.14:17:45.71#ibcon#about to write, iclass 30, count 2 2006.201.14:17:45.71#ibcon#wrote, iclass 30, count 2 2006.201.14:17:45.71#ibcon#about to read 3, iclass 30, count 2 2006.201.14:17:45.74#ibcon#read 3, iclass 30, count 2 2006.201.14:17:45.74#ibcon#about to read 4, iclass 30, count 2 2006.201.14:17:45.74#ibcon#read 4, iclass 30, count 2 2006.201.14:17:45.74#ibcon#about to read 5, iclass 30, count 2 2006.201.14:17:45.74#ibcon#read 5, iclass 30, count 2 2006.201.14:17:45.74#ibcon#about to read 6, iclass 30, count 2 2006.201.14:17:45.74#ibcon#read 6, iclass 30, count 2 2006.201.14:17:45.74#ibcon#end of sib2, iclass 30, count 2 2006.201.14:17:45.74#ibcon#*after write, iclass 30, count 2 2006.201.14:17:45.74#ibcon#*before return 0, iclass 30, count 2 2006.201.14:17:45.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:17:45.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:17:45.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.14:17:45.74#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:45.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:17:45.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:17:45.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:17:45.86#ibcon#enter wrdev, iclass 30, count 0 2006.201.14:17:45.86#ibcon#first serial, iclass 30, count 0 2006.201.14:17:45.86#ibcon#enter sib2, iclass 30, count 0 2006.201.14:17:45.86#ibcon#flushed, iclass 30, count 0 2006.201.14:17:45.86#ibcon#about to write, iclass 30, count 0 2006.201.14:17:45.86#ibcon#wrote, iclass 30, count 0 2006.201.14:17:45.86#ibcon#about to read 3, iclass 30, count 0 2006.201.14:17:45.88#ibcon#read 3, iclass 30, count 0 2006.201.14:17:45.88#ibcon#about to read 4, iclass 30, count 0 2006.201.14:17:45.88#ibcon#read 4, iclass 30, count 0 2006.201.14:17:45.88#ibcon#about to read 5, iclass 30, count 0 2006.201.14:17:45.88#ibcon#read 5, iclass 30, count 0 2006.201.14:17:45.88#ibcon#about to read 6, iclass 30, count 0 2006.201.14:17:45.88#ibcon#read 6, iclass 30, count 0 2006.201.14:17:45.88#ibcon#end of sib2, iclass 30, count 0 2006.201.14:17:45.88#ibcon#*mode == 0, iclass 30, count 0 2006.201.14:17:45.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.14:17:45.88#ibcon#[27=USB\r\n] 2006.201.14:17:45.88#ibcon#*before write, iclass 30, count 0 2006.201.14:17:45.88#ibcon#enter sib2, iclass 30, count 0 2006.201.14:17:45.88#ibcon#flushed, iclass 30, count 0 2006.201.14:17:45.88#ibcon#about to write, iclass 30, count 0 2006.201.14:17:45.88#ibcon#wrote, iclass 30, count 0 2006.201.14:17:45.88#ibcon#about to read 3, iclass 30, count 0 2006.201.14:17:45.91#ibcon#read 3, iclass 30, count 0 2006.201.14:17:45.91#ibcon#about to read 4, iclass 30, count 0 2006.201.14:17:45.91#ibcon#read 4, iclass 30, count 0 2006.201.14:17:45.91#ibcon#about to read 5, iclass 30, count 0 2006.201.14:17:45.91#ibcon#read 5, iclass 30, count 0 2006.201.14:17:45.91#ibcon#about to read 6, iclass 30, count 0 2006.201.14:17:45.91#ibcon#read 6, iclass 30, count 0 2006.201.14:17:45.91#ibcon#end of sib2, iclass 30, count 0 2006.201.14:17:45.91#ibcon#*after write, iclass 30, count 0 2006.201.14:17:45.91#ibcon#*before return 0, iclass 30, count 0 2006.201.14:17:45.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:17:45.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:17:45.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.14:17:45.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.14:17:45.91$vck44/vblo=2,634.99 2006.201.14:17:45.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.14:17:45.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.14:17:45.91#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:45.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:45.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:45.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:45.91#ibcon#enter wrdev, iclass 32, count 0 2006.201.14:17:45.91#ibcon#first serial, iclass 32, count 0 2006.201.14:17:45.91#ibcon#enter sib2, iclass 32, count 0 2006.201.14:17:45.91#ibcon#flushed, iclass 32, count 0 2006.201.14:17:45.91#ibcon#about to write, iclass 32, count 0 2006.201.14:17:45.91#ibcon#wrote, iclass 32, count 0 2006.201.14:17:45.91#ibcon#about to read 3, iclass 32, count 0 2006.201.14:17:45.93#ibcon#read 3, iclass 32, count 0 2006.201.14:17:45.93#ibcon#about to read 4, iclass 32, count 0 2006.201.14:17:45.93#ibcon#read 4, iclass 32, count 0 2006.201.14:17:45.93#ibcon#about to read 5, iclass 32, count 0 2006.201.14:17:45.93#ibcon#read 5, iclass 32, count 0 2006.201.14:17:45.93#ibcon#about to read 6, iclass 32, count 0 2006.201.14:17:45.93#ibcon#read 6, iclass 32, count 0 2006.201.14:17:45.93#ibcon#end of sib2, iclass 32, count 0 2006.201.14:17:45.93#ibcon#*mode == 0, iclass 32, count 0 2006.201.14:17:45.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.14:17:45.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:17:45.93#ibcon#*before write, iclass 32, count 0 2006.201.14:17:45.93#ibcon#enter sib2, iclass 32, count 0 2006.201.14:17:45.93#ibcon#flushed, iclass 32, count 0 2006.201.14:17:45.93#ibcon#about to write, iclass 32, count 0 2006.201.14:17:45.93#ibcon#wrote, iclass 32, count 0 2006.201.14:17:45.93#ibcon#about to read 3, iclass 32, count 0 2006.201.14:17:45.97#ibcon#read 3, iclass 32, count 0 2006.201.14:17:45.97#ibcon#about to read 4, iclass 32, count 0 2006.201.14:17:45.97#ibcon#read 4, iclass 32, count 0 2006.201.14:17:45.97#ibcon#about to read 5, iclass 32, count 0 2006.201.14:17:45.97#ibcon#read 5, iclass 32, count 0 2006.201.14:17:45.97#ibcon#about to read 6, iclass 32, count 0 2006.201.14:17:45.97#ibcon#read 6, iclass 32, count 0 2006.201.14:17:45.97#ibcon#end of sib2, iclass 32, count 0 2006.201.14:17:45.97#ibcon#*after write, iclass 32, count 0 2006.201.14:17:45.97#ibcon#*before return 0, iclass 32, count 0 2006.201.14:17:45.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:45.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:17:45.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.14:17:45.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.14:17:45.97$vck44/vb=2,5 2006.201.14:17:45.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.14:17:45.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.14:17:45.97#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:45.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:46.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:46.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:46.03#ibcon#enter wrdev, iclass 34, count 2 2006.201.14:17:46.03#ibcon#first serial, iclass 34, count 2 2006.201.14:17:46.03#ibcon#enter sib2, iclass 34, count 2 2006.201.14:17:46.03#ibcon#flushed, iclass 34, count 2 2006.201.14:17:46.03#ibcon#about to write, iclass 34, count 2 2006.201.14:17:46.03#ibcon#wrote, iclass 34, count 2 2006.201.14:17:46.03#ibcon#about to read 3, iclass 34, count 2 2006.201.14:17:46.05#ibcon#read 3, iclass 34, count 2 2006.201.14:17:46.05#ibcon#about to read 4, iclass 34, count 2 2006.201.14:17:46.05#ibcon#read 4, iclass 34, count 2 2006.201.14:17:46.05#ibcon#about to read 5, iclass 34, count 2 2006.201.14:17:46.05#ibcon#read 5, iclass 34, count 2 2006.201.14:17:46.05#ibcon#about to read 6, iclass 34, count 2 2006.201.14:17:46.05#ibcon#read 6, iclass 34, count 2 2006.201.14:17:46.05#ibcon#end of sib2, iclass 34, count 2 2006.201.14:17:46.05#ibcon#*mode == 0, iclass 34, count 2 2006.201.14:17:46.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.14:17:46.05#ibcon#[27=AT02-05\r\n] 2006.201.14:17:46.05#ibcon#*before write, iclass 34, count 2 2006.201.14:17:46.05#ibcon#enter sib2, iclass 34, count 2 2006.201.14:17:46.05#ibcon#flushed, iclass 34, count 2 2006.201.14:17:46.05#ibcon#about to write, iclass 34, count 2 2006.201.14:17:46.05#ibcon#wrote, iclass 34, count 2 2006.201.14:17:46.05#ibcon#about to read 3, iclass 34, count 2 2006.201.14:17:46.08#ibcon#read 3, iclass 34, count 2 2006.201.14:17:46.08#ibcon#about to read 4, iclass 34, count 2 2006.201.14:17:46.08#ibcon#read 4, iclass 34, count 2 2006.201.14:17:46.08#ibcon#about to read 5, iclass 34, count 2 2006.201.14:17:46.08#ibcon#read 5, iclass 34, count 2 2006.201.14:17:46.08#ibcon#about to read 6, iclass 34, count 2 2006.201.14:17:46.08#ibcon#read 6, iclass 34, count 2 2006.201.14:17:46.08#ibcon#end of sib2, iclass 34, count 2 2006.201.14:17:46.08#ibcon#*after write, iclass 34, count 2 2006.201.14:17:46.08#ibcon#*before return 0, iclass 34, count 2 2006.201.14:17:46.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:46.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:17:46.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.14:17:46.08#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:46.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:46.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:46.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:46.20#ibcon#enter wrdev, iclass 34, count 0 2006.201.14:17:46.20#ibcon#first serial, iclass 34, count 0 2006.201.14:17:46.20#ibcon#enter sib2, iclass 34, count 0 2006.201.14:17:46.20#ibcon#flushed, iclass 34, count 0 2006.201.14:17:46.20#ibcon#about to write, iclass 34, count 0 2006.201.14:17:46.20#ibcon#wrote, iclass 34, count 0 2006.201.14:17:46.20#ibcon#about to read 3, iclass 34, count 0 2006.201.14:17:46.22#ibcon#read 3, iclass 34, count 0 2006.201.14:17:46.22#ibcon#about to read 4, iclass 34, count 0 2006.201.14:17:46.22#ibcon#read 4, iclass 34, count 0 2006.201.14:17:46.22#ibcon#about to read 5, iclass 34, count 0 2006.201.14:17:46.22#ibcon#read 5, iclass 34, count 0 2006.201.14:17:46.22#ibcon#about to read 6, iclass 34, count 0 2006.201.14:17:46.22#ibcon#read 6, iclass 34, count 0 2006.201.14:17:46.22#ibcon#end of sib2, iclass 34, count 0 2006.201.14:17:46.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.14:17:46.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.14:17:46.22#ibcon#[27=USB\r\n] 2006.201.14:17:46.22#ibcon#*before write, iclass 34, count 0 2006.201.14:17:46.22#ibcon#enter sib2, iclass 34, count 0 2006.201.14:17:46.22#ibcon#flushed, iclass 34, count 0 2006.201.14:17:46.22#ibcon#about to write, iclass 34, count 0 2006.201.14:17:46.22#ibcon#wrote, iclass 34, count 0 2006.201.14:17:46.22#ibcon#about to read 3, iclass 34, count 0 2006.201.14:17:46.25#ibcon#read 3, iclass 34, count 0 2006.201.14:17:46.25#ibcon#about to read 4, iclass 34, count 0 2006.201.14:17:46.25#ibcon#read 4, iclass 34, count 0 2006.201.14:17:46.25#ibcon#about to read 5, iclass 34, count 0 2006.201.14:17:46.25#ibcon#read 5, iclass 34, count 0 2006.201.14:17:46.25#ibcon#about to read 6, iclass 34, count 0 2006.201.14:17:46.25#ibcon#read 6, iclass 34, count 0 2006.201.14:17:46.25#ibcon#end of sib2, iclass 34, count 0 2006.201.14:17:46.25#ibcon#*after write, iclass 34, count 0 2006.201.14:17:46.25#ibcon#*before return 0, iclass 34, count 0 2006.201.14:17:46.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:46.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:17:46.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.14:17:46.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.14:17:46.25$vck44/vblo=3,649.99 2006.201.14:17:46.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.14:17:46.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.14:17:46.25#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:46.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:46.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:46.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:46.25#ibcon#enter wrdev, iclass 36, count 0 2006.201.14:17:46.25#ibcon#first serial, iclass 36, count 0 2006.201.14:17:46.25#ibcon#enter sib2, iclass 36, count 0 2006.201.14:17:46.25#ibcon#flushed, iclass 36, count 0 2006.201.14:17:46.25#ibcon#about to write, iclass 36, count 0 2006.201.14:17:46.25#ibcon#wrote, iclass 36, count 0 2006.201.14:17:46.25#ibcon#about to read 3, iclass 36, count 0 2006.201.14:17:46.27#ibcon#read 3, iclass 36, count 0 2006.201.14:17:46.27#ibcon#about to read 4, iclass 36, count 0 2006.201.14:17:46.27#ibcon#read 4, iclass 36, count 0 2006.201.14:17:46.27#ibcon#about to read 5, iclass 36, count 0 2006.201.14:17:46.27#ibcon#read 5, iclass 36, count 0 2006.201.14:17:46.27#ibcon#about to read 6, iclass 36, count 0 2006.201.14:17:46.27#ibcon#read 6, iclass 36, count 0 2006.201.14:17:46.27#ibcon#end of sib2, iclass 36, count 0 2006.201.14:17:46.27#ibcon#*mode == 0, iclass 36, count 0 2006.201.14:17:46.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.14:17:46.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:17:46.27#ibcon#*before write, iclass 36, count 0 2006.201.14:17:46.27#ibcon#enter sib2, iclass 36, count 0 2006.201.14:17:46.27#ibcon#flushed, iclass 36, count 0 2006.201.14:17:46.27#ibcon#about to write, iclass 36, count 0 2006.201.14:17:46.27#ibcon#wrote, iclass 36, count 0 2006.201.14:17:46.27#ibcon#about to read 3, iclass 36, count 0 2006.201.14:17:46.31#ibcon#read 3, iclass 36, count 0 2006.201.14:17:46.31#ibcon#about to read 4, iclass 36, count 0 2006.201.14:17:46.31#ibcon#read 4, iclass 36, count 0 2006.201.14:17:46.31#ibcon#about to read 5, iclass 36, count 0 2006.201.14:17:46.31#ibcon#read 5, iclass 36, count 0 2006.201.14:17:46.31#ibcon#about to read 6, iclass 36, count 0 2006.201.14:17:46.31#ibcon#read 6, iclass 36, count 0 2006.201.14:17:46.31#ibcon#end of sib2, iclass 36, count 0 2006.201.14:17:46.31#ibcon#*after write, iclass 36, count 0 2006.201.14:17:46.31#ibcon#*before return 0, iclass 36, count 0 2006.201.14:17:46.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:46.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:17:46.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.14:17:46.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.14:17:46.31$vck44/vb=3,4 2006.201.14:17:46.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.14:17:46.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.14:17:46.31#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:46.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:46.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:46.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:46.37#ibcon#enter wrdev, iclass 38, count 2 2006.201.14:17:46.37#ibcon#first serial, iclass 38, count 2 2006.201.14:17:46.37#ibcon#enter sib2, iclass 38, count 2 2006.201.14:17:46.37#ibcon#flushed, iclass 38, count 2 2006.201.14:17:46.37#ibcon#about to write, iclass 38, count 2 2006.201.14:17:46.37#ibcon#wrote, iclass 38, count 2 2006.201.14:17:46.37#ibcon#about to read 3, iclass 38, count 2 2006.201.14:17:46.39#ibcon#read 3, iclass 38, count 2 2006.201.14:17:46.39#ibcon#about to read 4, iclass 38, count 2 2006.201.14:17:46.39#ibcon#read 4, iclass 38, count 2 2006.201.14:17:46.39#ibcon#about to read 5, iclass 38, count 2 2006.201.14:17:46.39#ibcon#read 5, iclass 38, count 2 2006.201.14:17:46.39#ibcon#about to read 6, iclass 38, count 2 2006.201.14:17:46.39#ibcon#read 6, iclass 38, count 2 2006.201.14:17:46.39#ibcon#end of sib2, iclass 38, count 2 2006.201.14:17:46.39#ibcon#*mode == 0, iclass 38, count 2 2006.201.14:17:46.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.14:17:46.39#ibcon#[27=AT03-04\r\n] 2006.201.14:17:46.39#ibcon#*before write, iclass 38, count 2 2006.201.14:17:46.39#ibcon#enter sib2, iclass 38, count 2 2006.201.14:17:46.39#ibcon#flushed, iclass 38, count 2 2006.201.14:17:46.39#ibcon#about to write, iclass 38, count 2 2006.201.14:17:46.39#ibcon#wrote, iclass 38, count 2 2006.201.14:17:46.39#ibcon#about to read 3, iclass 38, count 2 2006.201.14:17:46.42#ibcon#read 3, iclass 38, count 2 2006.201.14:17:46.42#ibcon#about to read 4, iclass 38, count 2 2006.201.14:17:46.42#ibcon#read 4, iclass 38, count 2 2006.201.14:17:46.42#ibcon#about to read 5, iclass 38, count 2 2006.201.14:17:46.42#ibcon#read 5, iclass 38, count 2 2006.201.14:17:46.42#ibcon#about to read 6, iclass 38, count 2 2006.201.14:17:46.42#ibcon#read 6, iclass 38, count 2 2006.201.14:17:46.42#ibcon#end of sib2, iclass 38, count 2 2006.201.14:17:46.42#ibcon#*after write, iclass 38, count 2 2006.201.14:17:46.42#ibcon#*before return 0, iclass 38, count 2 2006.201.14:17:46.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:46.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:17:46.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.14:17:46.42#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:46.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:46.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:46.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:46.54#ibcon#enter wrdev, iclass 38, count 0 2006.201.14:17:46.54#ibcon#first serial, iclass 38, count 0 2006.201.14:17:46.54#ibcon#enter sib2, iclass 38, count 0 2006.201.14:17:46.54#ibcon#flushed, iclass 38, count 0 2006.201.14:17:46.54#ibcon#about to write, iclass 38, count 0 2006.201.14:17:46.54#ibcon#wrote, iclass 38, count 0 2006.201.14:17:46.54#ibcon#about to read 3, iclass 38, count 0 2006.201.14:17:46.56#ibcon#read 3, iclass 38, count 0 2006.201.14:17:46.56#ibcon#about to read 4, iclass 38, count 0 2006.201.14:17:46.56#ibcon#read 4, iclass 38, count 0 2006.201.14:17:46.56#ibcon#about to read 5, iclass 38, count 0 2006.201.14:17:46.56#ibcon#read 5, iclass 38, count 0 2006.201.14:17:46.56#ibcon#about to read 6, iclass 38, count 0 2006.201.14:17:46.56#ibcon#read 6, iclass 38, count 0 2006.201.14:17:46.56#ibcon#end of sib2, iclass 38, count 0 2006.201.14:17:46.56#ibcon#*mode == 0, iclass 38, count 0 2006.201.14:17:46.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.14:17:46.56#ibcon#[27=USB\r\n] 2006.201.14:17:46.56#ibcon#*before write, iclass 38, count 0 2006.201.14:17:46.56#ibcon#enter sib2, iclass 38, count 0 2006.201.14:17:46.56#ibcon#flushed, iclass 38, count 0 2006.201.14:17:46.56#ibcon#about to write, iclass 38, count 0 2006.201.14:17:46.56#ibcon#wrote, iclass 38, count 0 2006.201.14:17:46.56#ibcon#about to read 3, iclass 38, count 0 2006.201.14:17:46.59#ibcon#read 3, iclass 38, count 0 2006.201.14:17:46.59#ibcon#about to read 4, iclass 38, count 0 2006.201.14:17:46.59#ibcon#read 4, iclass 38, count 0 2006.201.14:17:46.59#ibcon#about to read 5, iclass 38, count 0 2006.201.14:17:46.59#ibcon#read 5, iclass 38, count 0 2006.201.14:17:46.59#ibcon#about to read 6, iclass 38, count 0 2006.201.14:17:46.59#ibcon#read 6, iclass 38, count 0 2006.201.14:17:46.59#ibcon#end of sib2, iclass 38, count 0 2006.201.14:17:46.59#ibcon#*after write, iclass 38, count 0 2006.201.14:17:46.59#ibcon#*before return 0, iclass 38, count 0 2006.201.14:17:46.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:46.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:17:46.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.14:17:46.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.14:17:46.59$vck44/vblo=4,679.99 2006.201.14:17:46.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.14:17:46.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.14:17:46.59#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:46.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:46.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:46.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:46.59#ibcon#enter wrdev, iclass 40, count 0 2006.201.14:17:46.59#ibcon#first serial, iclass 40, count 0 2006.201.14:17:46.59#ibcon#enter sib2, iclass 40, count 0 2006.201.14:17:46.59#ibcon#flushed, iclass 40, count 0 2006.201.14:17:46.59#ibcon#about to write, iclass 40, count 0 2006.201.14:17:46.59#ibcon#wrote, iclass 40, count 0 2006.201.14:17:46.59#ibcon#about to read 3, iclass 40, count 0 2006.201.14:17:46.61#ibcon#read 3, iclass 40, count 0 2006.201.14:17:46.61#ibcon#about to read 4, iclass 40, count 0 2006.201.14:17:46.61#ibcon#read 4, iclass 40, count 0 2006.201.14:17:46.61#ibcon#about to read 5, iclass 40, count 0 2006.201.14:17:46.61#ibcon#read 5, iclass 40, count 0 2006.201.14:17:46.61#ibcon#about to read 6, iclass 40, count 0 2006.201.14:17:46.61#ibcon#read 6, iclass 40, count 0 2006.201.14:17:46.61#ibcon#end of sib2, iclass 40, count 0 2006.201.14:17:46.61#ibcon#*mode == 0, iclass 40, count 0 2006.201.14:17:46.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.14:17:46.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:17:46.61#ibcon#*before write, iclass 40, count 0 2006.201.14:17:46.61#ibcon#enter sib2, iclass 40, count 0 2006.201.14:17:46.61#ibcon#flushed, iclass 40, count 0 2006.201.14:17:46.61#ibcon#about to write, iclass 40, count 0 2006.201.14:17:46.61#ibcon#wrote, iclass 40, count 0 2006.201.14:17:46.61#ibcon#about to read 3, iclass 40, count 0 2006.201.14:17:46.66#ibcon#read 3, iclass 40, count 0 2006.201.14:17:46.66#ibcon#about to read 4, iclass 40, count 0 2006.201.14:17:46.66#ibcon#read 4, iclass 40, count 0 2006.201.14:17:46.66#ibcon#about to read 5, iclass 40, count 0 2006.201.14:17:46.66#ibcon#read 5, iclass 40, count 0 2006.201.14:17:46.66#ibcon#about to read 6, iclass 40, count 0 2006.201.14:17:46.66#ibcon#read 6, iclass 40, count 0 2006.201.14:17:46.66#ibcon#end of sib2, iclass 40, count 0 2006.201.14:17:46.66#ibcon#*after write, iclass 40, count 0 2006.201.14:17:46.66#ibcon#*before return 0, iclass 40, count 0 2006.201.14:17:46.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:46.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:17:46.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.14:17:46.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.14:17:46.66$vck44/vb=4,5 2006.201.14:17:46.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.14:17:46.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.14:17:46.66#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:46.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:46.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:46.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:46.71#ibcon#enter wrdev, iclass 4, count 2 2006.201.14:17:46.71#ibcon#first serial, iclass 4, count 2 2006.201.14:17:46.71#ibcon#enter sib2, iclass 4, count 2 2006.201.14:17:46.71#ibcon#flushed, iclass 4, count 2 2006.201.14:17:46.71#ibcon#about to write, iclass 4, count 2 2006.201.14:17:46.71#ibcon#wrote, iclass 4, count 2 2006.201.14:17:46.71#ibcon#about to read 3, iclass 4, count 2 2006.201.14:17:46.73#ibcon#read 3, iclass 4, count 2 2006.201.14:17:46.73#ibcon#about to read 4, iclass 4, count 2 2006.201.14:17:46.73#ibcon#read 4, iclass 4, count 2 2006.201.14:17:46.73#ibcon#about to read 5, iclass 4, count 2 2006.201.14:17:46.73#ibcon#read 5, iclass 4, count 2 2006.201.14:17:46.73#ibcon#about to read 6, iclass 4, count 2 2006.201.14:17:46.73#ibcon#read 6, iclass 4, count 2 2006.201.14:17:46.73#ibcon#end of sib2, iclass 4, count 2 2006.201.14:17:46.73#ibcon#*mode == 0, iclass 4, count 2 2006.201.14:17:46.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.14:17:46.73#ibcon#[27=AT04-05\r\n] 2006.201.14:17:46.73#ibcon#*before write, iclass 4, count 2 2006.201.14:17:46.73#ibcon#enter sib2, iclass 4, count 2 2006.201.14:17:46.73#ibcon#flushed, iclass 4, count 2 2006.201.14:17:46.73#ibcon#about to write, iclass 4, count 2 2006.201.14:17:46.73#ibcon#wrote, iclass 4, count 2 2006.201.14:17:46.73#ibcon#about to read 3, iclass 4, count 2 2006.201.14:17:46.76#ibcon#read 3, iclass 4, count 2 2006.201.14:17:46.76#ibcon#about to read 4, iclass 4, count 2 2006.201.14:17:46.76#ibcon#read 4, iclass 4, count 2 2006.201.14:17:46.76#ibcon#about to read 5, iclass 4, count 2 2006.201.14:17:46.76#ibcon#read 5, iclass 4, count 2 2006.201.14:17:46.76#ibcon#about to read 6, iclass 4, count 2 2006.201.14:17:46.76#ibcon#read 6, iclass 4, count 2 2006.201.14:17:46.76#ibcon#end of sib2, iclass 4, count 2 2006.201.14:17:46.76#ibcon#*after write, iclass 4, count 2 2006.201.14:17:46.76#ibcon#*before return 0, iclass 4, count 2 2006.201.14:17:46.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:46.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:17:46.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.14:17:46.76#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:46.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:46.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:46.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:46.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.14:17:46.88#ibcon#first serial, iclass 4, count 0 2006.201.14:17:46.88#ibcon#enter sib2, iclass 4, count 0 2006.201.14:17:46.88#ibcon#flushed, iclass 4, count 0 2006.201.14:17:46.88#ibcon#about to write, iclass 4, count 0 2006.201.14:17:46.88#ibcon#wrote, iclass 4, count 0 2006.201.14:17:46.88#ibcon#about to read 3, iclass 4, count 0 2006.201.14:17:46.90#ibcon#read 3, iclass 4, count 0 2006.201.14:17:46.90#ibcon#about to read 4, iclass 4, count 0 2006.201.14:17:46.90#ibcon#read 4, iclass 4, count 0 2006.201.14:17:46.90#ibcon#about to read 5, iclass 4, count 0 2006.201.14:17:46.90#ibcon#read 5, iclass 4, count 0 2006.201.14:17:46.90#ibcon#about to read 6, iclass 4, count 0 2006.201.14:17:46.90#ibcon#read 6, iclass 4, count 0 2006.201.14:17:46.90#ibcon#end of sib2, iclass 4, count 0 2006.201.14:17:46.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.14:17:46.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.14:17:46.90#ibcon#[27=USB\r\n] 2006.201.14:17:46.90#ibcon#*before write, iclass 4, count 0 2006.201.14:17:46.90#ibcon#enter sib2, iclass 4, count 0 2006.201.14:17:46.90#ibcon#flushed, iclass 4, count 0 2006.201.14:17:46.90#ibcon#about to write, iclass 4, count 0 2006.201.14:17:46.90#ibcon#wrote, iclass 4, count 0 2006.201.14:17:46.90#ibcon#about to read 3, iclass 4, count 0 2006.201.14:17:46.93#ibcon#read 3, iclass 4, count 0 2006.201.14:17:46.93#ibcon#about to read 4, iclass 4, count 0 2006.201.14:17:46.93#ibcon#read 4, iclass 4, count 0 2006.201.14:17:46.93#ibcon#about to read 5, iclass 4, count 0 2006.201.14:17:46.93#ibcon#read 5, iclass 4, count 0 2006.201.14:17:46.93#ibcon#about to read 6, iclass 4, count 0 2006.201.14:17:46.93#ibcon#read 6, iclass 4, count 0 2006.201.14:17:46.93#ibcon#end of sib2, iclass 4, count 0 2006.201.14:17:46.93#ibcon#*after write, iclass 4, count 0 2006.201.14:17:46.93#ibcon#*before return 0, iclass 4, count 0 2006.201.14:17:46.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:46.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:17:46.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.14:17:46.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.14:17:46.93$vck44/vblo=5,709.99 2006.201.14:17:46.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.14:17:46.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.14:17:46.93#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:46.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:46.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:46.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:46.93#ibcon#enter wrdev, iclass 6, count 0 2006.201.14:17:46.93#ibcon#first serial, iclass 6, count 0 2006.201.14:17:46.93#ibcon#enter sib2, iclass 6, count 0 2006.201.14:17:46.93#ibcon#flushed, iclass 6, count 0 2006.201.14:17:46.93#ibcon#about to write, iclass 6, count 0 2006.201.14:17:46.93#ibcon#wrote, iclass 6, count 0 2006.201.14:17:46.93#ibcon#about to read 3, iclass 6, count 0 2006.201.14:17:46.95#ibcon#read 3, iclass 6, count 0 2006.201.14:17:46.95#ibcon#about to read 4, iclass 6, count 0 2006.201.14:17:46.95#ibcon#read 4, iclass 6, count 0 2006.201.14:17:46.95#ibcon#about to read 5, iclass 6, count 0 2006.201.14:17:46.95#ibcon#read 5, iclass 6, count 0 2006.201.14:17:46.95#ibcon#about to read 6, iclass 6, count 0 2006.201.14:17:46.95#ibcon#read 6, iclass 6, count 0 2006.201.14:17:46.95#ibcon#end of sib2, iclass 6, count 0 2006.201.14:17:46.95#ibcon#*mode == 0, iclass 6, count 0 2006.201.14:17:46.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.14:17:46.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:17:46.95#ibcon#*before write, iclass 6, count 0 2006.201.14:17:46.95#ibcon#enter sib2, iclass 6, count 0 2006.201.14:17:46.95#ibcon#flushed, iclass 6, count 0 2006.201.14:17:46.95#ibcon#about to write, iclass 6, count 0 2006.201.14:17:46.95#ibcon#wrote, iclass 6, count 0 2006.201.14:17:46.95#ibcon#about to read 3, iclass 6, count 0 2006.201.14:17:46.99#ibcon#read 3, iclass 6, count 0 2006.201.14:17:46.99#ibcon#about to read 4, iclass 6, count 0 2006.201.14:17:46.99#ibcon#read 4, iclass 6, count 0 2006.201.14:17:46.99#ibcon#about to read 5, iclass 6, count 0 2006.201.14:17:46.99#ibcon#read 5, iclass 6, count 0 2006.201.14:17:46.99#ibcon#about to read 6, iclass 6, count 0 2006.201.14:17:46.99#ibcon#read 6, iclass 6, count 0 2006.201.14:17:46.99#ibcon#end of sib2, iclass 6, count 0 2006.201.14:17:46.99#ibcon#*after write, iclass 6, count 0 2006.201.14:17:46.99#ibcon#*before return 0, iclass 6, count 0 2006.201.14:17:46.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:46.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:17:46.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.14:17:46.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.14:17:46.99$vck44/vb=5,4 2006.201.14:17:46.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.14:17:46.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.14:17:46.99#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:46.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:47.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:47.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:47.05#ibcon#enter wrdev, iclass 10, count 2 2006.201.14:17:47.05#ibcon#first serial, iclass 10, count 2 2006.201.14:17:47.05#ibcon#enter sib2, iclass 10, count 2 2006.201.14:17:47.05#ibcon#flushed, iclass 10, count 2 2006.201.14:17:47.05#ibcon#about to write, iclass 10, count 2 2006.201.14:17:47.05#ibcon#wrote, iclass 10, count 2 2006.201.14:17:47.05#ibcon#about to read 3, iclass 10, count 2 2006.201.14:17:47.07#ibcon#read 3, iclass 10, count 2 2006.201.14:17:47.07#ibcon#about to read 4, iclass 10, count 2 2006.201.14:17:47.07#ibcon#read 4, iclass 10, count 2 2006.201.14:17:47.07#ibcon#about to read 5, iclass 10, count 2 2006.201.14:17:47.07#ibcon#read 5, iclass 10, count 2 2006.201.14:17:47.07#ibcon#about to read 6, iclass 10, count 2 2006.201.14:17:47.07#ibcon#read 6, iclass 10, count 2 2006.201.14:17:47.07#ibcon#end of sib2, iclass 10, count 2 2006.201.14:17:47.07#ibcon#*mode == 0, iclass 10, count 2 2006.201.14:17:47.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.14:17:47.07#ibcon#[27=AT05-04\r\n] 2006.201.14:17:47.07#ibcon#*before write, iclass 10, count 2 2006.201.14:17:47.07#ibcon#enter sib2, iclass 10, count 2 2006.201.14:17:47.07#ibcon#flushed, iclass 10, count 2 2006.201.14:17:47.07#ibcon#about to write, iclass 10, count 2 2006.201.14:17:47.07#ibcon#wrote, iclass 10, count 2 2006.201.14:17:47.07#ibcon#about to read 3, iclass 10, count 2 2006.201.14:17:47.10#ibcon#read 3, iclass 10, count 2 2006.201.14:17:47.10#ibcon#about to read 4, iclass 10, count 2 2006.201.14:17:47.10#ibcon#read 4, iclass 10, count 2 2006.201.14:17:47.10#ibcon#about to read 5, iclass 10, count 2 2006.201.14:17:47.10#ibcon#read 5, iclass 10, count 2 2006.201.14:17:47.10#ibcon#about to read 6, iclass 10, count 2 2006.201.14:17:47.10#ibcon#read 6, iclass 10, count 2 2006.201.14:17:47.10#ibcon#end of sib2, iclass 10, count 2 2006.201.14:17:47.10#ibcon#*after write, iclass 10, count 2 2006.201.14:17:47.10#ibcon#*before return 0, iclass 10, count 2 2006.201.14:17:47.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:47.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:17:47.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.14:17:47.10#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:47.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:47.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:47.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:47.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.14:17:47.22#ibcon#first serial, iclass 10, count 0 2006.201.14:17:47.22#ibcon#enter sib2, iclass 10, count 0 2006.201.14:17:47.22#ibcon#flushed, iclass 10, count 0 2006.201.14:17:47.22#ibcon#about to write, iclass 10, count 0 2006.201.14:17:47.22#ibcon#wrote, iclass 10, count 0 2006.201.14:17:47.22#ibcon#about to read 3, iclass 10, count 0 2006.201.14:17:47.24#ibcon#read 3, iclass 10, count 0 2006.201.14:17:47.24#ibcon#about to read 4, iclass 10, count 0 2006.201.14:17:47.24#ibcon#read 4, iclass 10, count 0 2006.201.14:17:47.24#ibcon#about to read 5, iclass 10, count 0 2006.201.14:17:47.24#ibcon#read 5, iclass 10, count 0 2006.201.14:17:47.24#ibcon#about to read 6, iclass 10, count 0 2006.201.14:17:47.24#ibcon#read 6, iclass 10, count 0 2006.201.14:17:47.24#ibcon#end of sib2, iclass 10, count 0 2006.201.14:17:47.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.14:17:47.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.14:17:47.24#ibcon#[27=USB\r\n] 2006.201.14:17:47.24#ibcon#*before write, iclass 10, count 0 2006.201.14:17:47.24#ibcon#enter sib2, iclass 10, count 0 2006.201.14:17:47.24#ibcon#flushed, iclass 10, count 0 2006.201.14:17:47.24#ibcon#about to write, iclass 10, count 0 2006.201.14:17:47.24#ibcon#wrote, iclass 10, count 0 2006.201.14:17:47.24#ibcon#about to read 3, iclass 10, count 0 2006.201.14:17:47.27#ibcon#read 3, iclass 10, count 0 2006.201.14:17:47.27#ibcon#about to read 4, iclass 10, count 0 2006.201.14:17:47.27#ibcon#read 4, iclass 10, count 0 2006.201.14:17:47.27#ibcon#about to read 5, iclass 10, count 0 2006.201.14:17:47.27#ibcon#read 5, iclass 10, count 0 2006.201.14:17:47.27#ibcon#about to read 6, iclass 10, count 0 2006.201.14:17:47.27#ibcon#read 6, iclass 10, count 0 2006.201.14:17:47.27#ibcon#end of sib2, iclass 10, count 0 2006.201.14:17:47.27#ibcon#*after write, iclass 10, count 0 2006.201.14:17:47.27#ibcon#*before return 0, iclass 10, count 0 2006.201.14:17:47.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:47.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:17:47.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.14:17:47.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.14:17:47.27$vck44/vblo=6,719.99 2006.201.14:17:47.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.14:17:47.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.14:17:47.27#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:47.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:47.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:47.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:47.27#ibcon#enter wrdev, iclass 12, count 0 2006.201.14:17:47.27#ibcon#first serial, iclass 12, count 0 2006.201.14:17:47.27#ibcon#enter sib2, iclass 12, count 0 2006.201.14:17:47.27#ibcon#flushed, iclass 12, count 0 2006.201.14:17:47.27#ibcon#about to write, iclass 12, count 0 2006.201.14:17:47.27#ibcon#wrote, iclass 12, count 0 2006.201.14:17:47.27#ibcon#about to read 3, iclass 12, count 0 2006.201.14:17:47.29#ibcon#read 3, iclass 12, count 0 2006.201.14:17:47.29#ibcon#about to read 4, iclass 12, count 0 2006.201.14:17:47.29#ibcon#read 4, iclass 12, count 0 2006.201.14:17:47.29#ibcon#about to read 5, iclass 12, count 0 2006.201.14:17:47.29#ibcon#read 5, iclass 12, count 0 2006.201.14:17:47.29#ibcon#about to read 6, iclass 12, count 0 2006.201.14:17:47.29#ibcon#read 6, iclass 12, count 0 2006.201.14:17:47.29#ibcon#end of sib2, iclass 12, count 0 2006.201.14:17:47.29#ibcon#*mode == 0, iclass 12, count 0 2006.201.14:17:47.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.14:17:47.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:17:47.29#ibcon#*before write, iclass 12, count 0 2006.201.14:17:47.29#ibcon#enter sib2, iclass 12, count 0 2006.201.14:17:47.29#ibcon#flushed, iclass 12, count 0 2006.201.14:17:47.29#ibcon#about to write, iclass 12, count 0 2006.201.14:17:47.29#ibcon#wrote, iclass 12, count 0 2006.201.14:17:47.29#ibcon#about to read 3, iclass 12, count 0 2006.201.14:17:47.33#ibcon#read 3, iclass 12, count 0 2006.201.14:17:47.33#ibcon#about to read 4, iclass 12, count 0 2006.201.14:17:47.33#ibcon#read 4, iclass 12, count 0 2006.201.14:17:47.33#ibcon#about to read 5, iclass 12, count 0 2006.201.14:17:47.33#ibcon#read 5, iclass 12, count 0 2006.201.14:17:47.33#ibcon#about to read 6, iclass 12, count 0 2006.201.14:17:47.33#ibcon#read 6, iclass 12, count 0 2006.201.14:17:47.33#ibcon#end of sib2, iclass 12, count 0 2006.201.14:17:47.33#ibcon#*after write, iclass 12, count 0 2006.201.14:17:47.33#ibcon#*before return 0, iclass 12, count 0 2006.201.14:17:47.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:47.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:17:47.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.14:17:47.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.14:17:47.33$vck44/vb=6,4 2006.201.14:17:47.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.14:17:47.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.14:17:47.33#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:47.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:47.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:47.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:47.39#ibcon#enter wrdev, iclass 14, count 2 2006.201.14:17:47.39#ibcon#first serial, iclass 14, count 2 2006.201.14:17:47.39#ibcon#enter sib2, iclass 14, count 2 2006.201.14:17:47.39#ibcon#flushed, iclass 14, count 2 2006.201.14:17:47.39#ibcon#about to write, iclass 14, count 2 2006.201.14:17:47.39#ibcon#wrote, iclass 14, count 2 2006.201.14:17:47.39#ibcon#about to read 3, iclass 14, count 2 2006.201.14:17:47.41#ibcon#read 3, iclass 14, count 2 2006.201.14:17:47.41#ibcon#about to read 4, iclass 14, count 2 2006.201.14:17:47.41#ibcon#read 4, iclass 14, count 2 2006.201.14:17:47.41#ibcon#about to read 5, iclass 14, count 2 2006.201.14:17:47.41#ibcon#read 5, iclass 14, count 2 2006.201.14:17:47.41#ibcon#about to read 6, iclass 14, count 2 2006.201.14:17:47.41#ibcon#read 6, iclass 14, count 2 2006.201.14:17:47.41#ibcon#end of sib2, iclass 14, count 2 2006.201.14:17:47.41#ibcon#*mode == 0, iclass 14, count 2 2006.201.14:17:47.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.14:17:47.41#ibcon#[27=AT06-04\r\n] 2006.201.14:17:47.41#ibcon#*before write, iclass 14, count 2 2006.201.14:17:47.41#ibcon#enter sib2, iclass 14, count 2 2006.201.14:17:47.41#ibcon#flushed, iclass 14, count 2 2006.201.14:17:47.41#ibcon#about to write, iclass 14, count 2 2006.201.14:17:47.41#ibcon#wrote, iclass 14, count 2 2006.201.14:17:47.41#ibcon#about to read 3, iclass 14, count 2 2006.201.14:17:47.44#ibcon#read 3, iclass 14, count 2 2006.201.14:17:47.44#ibcon#about to read 4, iclass 14, count 2 2006.201.14:17:47.44#ibcon#read 4, iclass 14, count 2 2006.201.14:17:47.44#ibcon#about to read 5, iclass 14, count 2 2006.201.14:17:47.44#ibcon#read 5, iclass 14, count 2 2006.201.14:17:47.44#ibcon#about to read 6, iclass 14, count 2 2006.201.14:17:47.44#ibcon#read 6, iclass 14, count 2 2006.201.14:17:47.44#ibcon#end of sib2, iclass 14, count 2 2006.201.14:17:47.44#ibcon#*after write, iclass 14, count 2 2006.201.14:17:47.44#ibcon#*before return 0, iclass 14, count 2 2006.201.14:17:47.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:47.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:17:47.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.14:17:47.44#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:47.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:47.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:47.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:47.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.14:17:47.56#ibcon#first serial, iclass 14, count 0 2006.201.14:17:47.56#ibcon#enter sib2, iclass 14, count 0 2006.201.14:17:47.56#ibcon#flushed, iclass 14, count 0 2006.201.14:17:47.56#ibcon#about to write, iclass 14, count 0 2006.201.14:17:47.56#ibcon#wrote, iclass 14, count 0 2006.201.14:17:47.56#ibcon#about to read 3, iclass 14, count 0 2006.201.14:17:47.58#ibcon#read 3, iclass 14, count 0 2006.201.14:17:47.58#ibcon#about to read 4, iclass 14, count 0 2006.201.14:17:47.58#ibcon#read 4, iclass 14, count 0 2006.201.14:17:47.58#ibcon#about to read 5, iclass 14, count 0 2006.201.14:17:47.58#ibcon#read 5, iclass 14, count 0 2006.201.14:17:47.58#ibcon#about to read 6, iclass 14, count 0 2006.201.14:17:47.58#ibcon#read 6, iclass 14, count 0 2006.201.14:17:47.58#ibcon#end of sib2, iclass 14, count 0 2006.201.14:17:47.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.14:17:47.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.14:17:47.58#ibcon#[27=USB\r\n] 2006.201.14:17:47.58#ibcon#*before write, iclass 14, count 0 2006.201.14:17:47.58#ibcon#enter sib2, iclass 14, count 0 2006.201.14:17:47.58#ibcon#flushed, iclass 14, count 0 2006.201.14:17:47.58#ibcon#about to write, iclass 14, count 0 2006.201.14:17:47.58#ibcon#wrote, iclass 14, count 0 2006.201.14:17:47.58#ibcon#about to read 3, iclass 14, count 0 2006.201.14:17:47.61#ibcon#read 3, iclass 14, count 0 2006.201.14:17:47.61#ibcon#about to read 4, iclass 14, count 0 2006.201.14:17:47.61#ibcon#read 4, iclass 14, count 0 2006.201.14:17:47.61#ibcon#about to read 5, iclass 14, count 0 2006.201.14:17:47.61#ibcon#read 5, iclass 14, count 0 2006.201.14:17:47.61#ibcon#about to read 6, iclass 14, count 0 2006.201.14:17:47.61#ibcon#read 6, iclass 14, count 0 2006.201.14:17:47.61#ibcon#end of sib2, iclass 14, count 0 2006.201.14:17:47.61#ibcon#*after write, iclass 14, count 0 2006.201.14:17:47.61#ibcon#*before return 0, iclass 14, count 0 2006.201.14:17:47.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:47.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:17:47.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.14:17:47.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.14:17:47.61$vck44/vblo=7,734.99 2006.201.14:17:47.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.14:17:47.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.14:17:47.61#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:47.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:47.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:47.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:47.61#ibcon#enter wrdev, iclass 16, count 0 2006.201.14:17:47.61#ibcon#first serial, iclass 16, count 0 2006.201.14:17:47.61#ibcon#enter sib2, iclass 16, count 0 2006.201.14:17:47.61#ibcon#flushed, iclass 16, count 0 2006.201.14:17:47.61#ibcon#about to write, iclass 16, count 0 2006.201.14:17:47.61#ibcon#wrote, iclass 16, count 0 2006.201.14:17:47.61#ibcon#about to read 3, iclass 16, count 0 2006.201.14:17:47.63#ibcon#read 3, iclass 16, count 0 2006.201.14:17:47.63#ibcon#about to read 4, iclass 16, count 0 2006.201.14:17:47.63#ibcon#read 4, iclass 16, count 0 2006.201.14:17:47.63#ibcon#about to read 5, iclass 16, count 0 2006.201.14:17:47.63#ibcon#read 5, iclass 16, count 0 2006.201.14:17:47.63#ibcon#about to read 6, iclass 16, count 0 2006.201.14:17:47.63#ibcon#read 6, iclass 16, count 0 2006.201.14:17:47.63#ibcon#end of sib2, iclass 16, count 0 2006.201.14:17:47.63#ibcon#*mode == 0, iclass 16, count 0 2006.201.14:17:47.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.14:17:47.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:17:47.63#ibcon#*before write, iclass 16, count 0 2006.201.14:17:47.63#ibcon#enter sib2, iclass 16, count 0 2006.201.14:17:47.63#ibcon#flushed, iclass 16, count 0 2006.201.14:17:47.63#ibcon#about to write, iclass 16, count 0 2006.201.14:17:47.63#ibcon#wrote, iclass 16, count 0 2006.201.14:17:47.63#ibcon#about to read 3, iclass 16, count 0 2006.201.14:17:47.68#ibcon#read 3, iclass 16, count 0 2006.201.14:17:47.68#ibcon#about to read 4, iclass 16, count 0 2006.201.14:17:47.68#ibcon#read 4, iclass 16, count 0 2006.201.14:17:47.68#ibcon#about to read 5, iclass 16, count 0 2006.201.14:17:47.68#ibcon#read 5, iclass 16, count 0 2006.201.14:17:47.68#ibcon#about to read 6, iclass 16, count 0 2006.201.14:17:47.68#ibcon#read 6, iclass 16, count 0 2006.201.14:17:47.68#ibcon#end of sib2, iclass 16, count 0 2006.201.14:17:47.68#ibcon#*after write, iclass 16, count 0 2006.201.14:17:47.68#ibcon#*before return 0, iclass 16, count 0 2006.201.14:17:47.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:47.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:17:47.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.14:17:47.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.14:17:47.68$vck44/vb=7,4 2006.201.14:17:47.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.14:17:47.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.14:17:47.68#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:47.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:47.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:47.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:47.73#ibcon#enter wrdev, iclass 18, count 2 2006.201.14:17:47.73#ibcon#first serial, iclass 18, count 2 2006.201.14:17:47.73#ibcon#enter sib2, iclass 18, count 2 2006.201.14:17:47.73#ibcon#flushed, iclass 18, count 2 2006.201.14:17:47.73#ibcon#about to write, iclass 18, count 2 2006.201.14:17:47.73#ibcon#wrote, iclass 18, count 2 2006.201.14:17:47.73#ibcon#about to read 3, iclass 18, count 2 2006.201.14:17:47.75#ibcon#read 3, iclass 18, count 2 2006.201.14:17:47.75#ibcon#about to read 4, iclass 18, count 2 2006.201.14:17:47.75#ibcon#read 4, iclass 18, count 2 2006.201.14:17:47.75#ibcon#about to read 5, iclass 18, count 2 2006.201.14:17:47.75#ibcon#read 5, iclass 18, count 2 2006.201.14:17:47.75#ibcon#about to read 6, iclass 18, count 2 2006.201.14:17:47.75#ibcon#read 6, iclass 18, count 2 2006.201.14:17:47.75#ibcon#end of sib2, iclass 18, count 2 2006.201.14:17:47.75#ibcon#*mode == 0, iclass 18, count 2 2006.201.14:17:47.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.14:17:47.75#ibcon#[27=AT07-04\r\n] 2006.201.14:17:47.75#ibcon#*before write, iclass 18, count 2 2006.201.14:17:47.75#ibcon#enter sib2, iclass 18, count 2 2006.201.14:17:47.75#ibcon#flushed, iclass 18, count 2 2006.201.14:17:47.75#ibcon#about to write, iclass 18, count 2 2006.201.14:17:47.75#ibcon#wrote, iclass 18, count 2 2006.201.14:17:47.75#ibcon#about to read 3, iclass 18, count 2 2006.201.14:17:47.78#ibcon#read 3, iclass 18, count 2 2006.201.14:17:47.78#ibcon#about to read 4, iclass 18, count 2 2006.201.14:17:47.78#ibcon#read 4, iclass 18, count 2 2006.201.14:17:47.78#ibcon#about to read 5, iclass 18, count 2 2006.201.14:17:47.78#ibcon#read 5, iclass 18, count 2 2006.201.14:17:47.78#ibcon#about to read 6, iclass 18, count 2 2006.201.14:17:47.78#ibcon#read 6, iclass 18, count 2 2006.201.14:17:47.78#ibcon#end of sib2, iclass 18, count 2 2006.201.14:17:47.78#ibcon#*after write, iclass 18, count 2 2006.201.14:17:47.78#ibcon#*before return 0, iclass 18, count 2 2006.201.14:17:47.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:47.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:17:47.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.14:17:47.78#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:47.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:47.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:47.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:47.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.14:17:47.90#ibcon#first serial, iclass 18, count 0 2006.201.14:17:47.90#ibcon#enter sib2, iclass 18, count 0 2006.201.14:17:47.90#ibcon#flushed, iclass 18, count 0 2006.201.14:17:47.90#ibcon#about to write, iclass 18, count 0 2006.201.14:17:47.90#ibcon#wrote, iclass 18, count 0 2006.201.14:17:47.90#ibcon#about to read 3, iclass 18, count 0 2006.201.14:17:47.92#ibcon#read 3, iclass 18, count 0 2006.201.14:17:47.92#ibcon#about to read 4, iclass 18, count 0 2006.201.14:17:47.92#ibcon#read 4, iclass 18, count 0 2006.201.14:17:47.92#ibcon#about to read 5, iclass 18, count 0 2006.201.14:17:47.92#ibcon#read 5, iclass 18, count 0 2006.201.14:17:47.92#ibcon#about to read 6, iclass 18, count 0 2006.201.14:17:47.92#ibcon#read 6, iclass 18, count 0 2006.201.14:17:47.92#ibcon#end of sib2, iclass 18, count 0 2006.201.14:17:47.92#ibcon#*mode == 0, iclass 18, count 0 2006.201.14:17:47.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.14:17:47.92#ibcon#[27=USB\r\n] 2006.201.14:17:47.92#ibcon#*before write, iclass 18, count 0 2006.201.14:17:47.92#ibcon#enter sib2, iclass 18, count 0 2006.201.14:17:47.92#ibcon#flushed, iclass 18, count 0 2006.201.14:17:47.92#ibcon#about to write, iclass 18, count 0 2006.201.14:17:47.92#ibcon#wrote, iclass 18, count 0 2006.201.14:17:47.92#ibcon#about to read 3, iclass 18, count 0 2006.201.14:17:47.95#ibcon#read 3, iclass 18, count 0 2006.201.14:17:47.95#ibcon#about to read 4, iclass 18, count 0 2006.201.14:17:47.95#ibcon#read 4, iclass 18, count 0 2006.201.14:17:47.95#ibcon#about to read 5, iclass 18, count 0 2006.201.14:17:47.95#ibcon#read 5, iclass 18, count 0 2006.201.14:17:47.95#ibcon#about to read 6, iclass 18, count 0 2006.201.14:17:47.95#ibcon#read 6, iclass 18, count 0 2006.201.14:17:47.95#ibcon#end of sib2, iclass 18, count 0 2006.201.14:17:47.95#ibcon#*after write, iclass 18, count 0 2006.201.14:17:47.95#ibcon#*before return 0, iclass 18, count 0 2006.201.14:17:47.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:47.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:17:47.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.14:17:47.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.14:17:47.95$vck44/vblo=8,744.99 2006.201.14:17:47.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.14:17:47.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.14:17:47.95#ibcon#ireg 17 cls_cnt 0 2006.201.14:17:47.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:47.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:47.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:47.95#ibcon#enter wrdev, iclass 20, count 0 2006.201.14:17:47.95#ibcon#first serial, iclass 20, count 0 2006.201.14:17:47.95#ibcon#enter sib2, iclass 20, count 0 2006.201.14:17:47.95#ibcon#flushed, iclass 20, count 0 2006.201.14:17:47.95#ibcon#about to write, iclass 20, count 0 2006.201.14:17:47.95#ibcon#wrote, iclass 20, count 0 2006.201.14:17:47.95#ibcon#about to read 3, iclass 20, count 0 2006.201.14:17:47.97#ibcon#read 3, iclass 20, count 0 2006.201.14:17:47.97#ibcon#about to read 4, iclass 20, count 0 2006.201.14:17:47.97#ibcon#read 4, iclass 20, count 0 2006.201.14:17:47.97#ibcon#about to read 5, iclass 20, count 0 2006.201.14:17:47.97#ibcon#read 5, iclass 20, count 0 2006.201.14:17:47.97#ibcon#about to read 6, iclass 20, count 0 2006.201.14:17:47.97#ibcon#read 6, iclass 20, count 0 2006.201.14:17:47.97#ibcon#end of sib2, iclass 20, count 0 2006.201.14:17:47.97#ibcon#*mode == 0, iclass 20, count 0 2006.201.14:17:47.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.14:17:47.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:17:47.97#ibcon#*before write, iclass 20, count 0 2006.201.14:17:47.97#ibcon#enter sib2, iclass 20, count 0 2006.201.14:17:47.97#ibcon#flushed, iclass 20, count 0 2006.201.14:17:47.97#ibcon#about to write, iclass 20, count 0 2006.201.14:17:47.97#ibcon#wrote, iclass 20, count 0 2006.201.14:17:47.97#ibcon#about to read 3, iclass 20, count 0 2006.201.14:17:48.01#ibcon#read 3, iclass 20, count 0 2006.201.14:17:48.01#ibcon#about to read 4, iclass 20, count 0 2006.201.14:17:48.01#ibcon#read 4, iclass 20, count 0 2006.201.14:17:48.01#ibcon#about to read 5, iclass 20, count 0 2006.201.14:17:48.01#ibcon#read 5, iclass 20, count 0 2006.201.14:17:48.01#ibcon#about to read 6, iclass 20, count 0 2006.201.14:17:48.01#ibcon#read 6, iclass 20, count 0 2006.201.14:17:48.01#ibcon#end of sib2, iclass 20, count 0 2006.201.14:17:48.01#ibcon#*after write, iclass 20, count 0 2006.201.14:17:48.01#ibcon#*before return 0, iclass 20, count 0 2006.201.14:17:48.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:48.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:17:48.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.14:17:48.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.14:17:48.01$vck44/vb=8,4 2006.201.14:17:48.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.14:17:48.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.14:17:48.01#ibcon#ireg 11 cls_cnt 2 2006.201.14:17:48.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:48.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:48.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:48.07#ibcon#enter wrdev, iclass 22, count 2 2006.201.14:17:48.07#ibcon#first serial, iclass 22, count 2 2006.201.14:17:48.07#ibcon#enter sib2, iclass 22, count 2 2006.201.14:17:48.07#ibcon#flushed, iclass 22, count 2 2006.201.14:17:48.07#ibcon#about to write, iclass 22, count 2 2006.201.14:17:48.07#ibcon#wrote, iclass 22, count 2 2006.201.14:17:48.07#ibcon#about to read 3, iclass 22, count 2 2006.201.14:17:48.09#ibcon#read 3, iclass 22, count 2 2006.201.14:17:48.09#ibcon#about to read 4, iclass 22, count 2 2006.201.14:17:48.09#ibcon#read 4, iclass 22, count 2 2006.201.14:17:48.09#ibcon#about to read 5, iclass 22, count 2 2006.201.14:17:48.09#ibcon#read 5, iclass 22, count 2 2006.201.14:17:48.09#ibcon#about to read 6, iclass 22, count 2 2006.201.14:17:48.09#ibcon#read 6, iclass 22, count 2 2006.201.14:17:48.09#ibcon#end of sib2, iclass 22, count 2 2006.201.14:17:48.09#ibcon#*mode == 0, iclass 22, count 2 2006.201.14:17:48.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.14:17:48.09#ibcon#[27=AT08-04\r\n] 2006.201.14:17:48.09#ibcon#*before write, iclass 22, count 2 2006.201.14:17:48.09#ibcon#enter sib2, iclass 22, count 2 2006.201.14:17:48.09#ibcon#flushed, iclass 22, count 2 2006.201.14:17:48.09#ibcon#about to write, iclass 22, count 2 2006.201.14:17:48.09#ibcon#wrote, iclass 22, count 2 2006.201.14:17:48.09#ibcon#about to read 3, iclass 22, count 2 2006.201.14:17:48.12#ibcon#read 3, iclass 22, count 2 2006.201.14:17:48.12#ibcon#about to read 4, iclass 22, count 2 2006.201.14:17:48.12#ibcon#read 4, iclass 22, count 2 2006.201.14:17:48.12#ibcon#about to read 5, iclass 22, count 2 2006.201.14:17:48.12#ibcon#read 5, iclass 22, count 2 2006.201.14:17:48.12#ibcon#about to read 6, iclass 22, count 2 2006.201.14:17:48.12#ibcon#read 6, iclass 22, count 2 2006.201.14:17:48.12#ibcon#end of sib2, iclass 22, count 2 2006.201.14:17:48.12#ibcon#*after write, iclass 22, count 2 2006.201.14:17:48.12#ibcon#*before return 0, iclass 22, count 2 2006.201.14:17:48.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:48.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:17:48.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.14:17:48.12#ibcon#ireg 7 cls_cnt 0 2006.201.14:17:48.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:48.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:48.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:48.24#ibcon#enter wrdev, iclass 22, count 0 2006.201.14:17:48.24#ibcon#first serial, iclass 22, count 0 2006.201.14:17:48.24#ibcon#enter sib2, iclass 22, count 0 2006.201.14:17:48.24#ibcon#flushed, iclass 22, count 0 2006.201.14:17:48.24#ibcon#about to write, iclass 22, count 0 2006.201.14:17:48.24#ibcon#wrote, iclass 22, count 0 2006.201.14:17:48.24#ibcon#about to read 3, iclass 22, count 0 2006.201.14:17:48.26#ibcon#read 3, iclass 22, count 0 2006.201.14:17:48.26#ibcon#about to read 4, iclass 22, count 0 2006.201.14:17:48.26#ibcon#read 4, iclass 22, count 0 2006.201.14:17:48.26#ibcon#about to read 5, iclass 22, count 0 2006.201.14:17:48.26#ibcon#read 5, iclass 22, count 0 2006.201.14:17:48.26#ibcon#about to read 6, iclass 22, count 0 2006.201.14:17:48.26#ibcon#read 6, iclass 22, count 0 2006.201.14:17:48.26#ibcon#end of sib2, iclass 22, count 0 2006.201.14:17:48.26#ibcon#*mode == 0, iclass 22, count 0 2006.201.14:17:48.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.14:17:48.26#ibcon#[27=USB\r\n] 2006.201.14:17:48.26#ibcon#*before write, iclass 22, count 0 2006.201.14:17:48.26#ibcon#enter sib2, iclass 22, count 0 2006.201.14:17:48.26#ibcon#flushed, iclass 22, count 0 2006.201.14:17:48.26#ibcon#about to write, iclass 22, count 0 2006.201.14:17:48.26#ibcon#wrote, iclass 22, count 0 2006.201.14:17:48.26#ibcon#about to read 3, iclass 22, count 0 2006.201.14:17:48.29#ibcon#read 3, iclass 22, count 0 2006.201.14:17:48.29#ibcon#about to read 4, iclass 22, count 0 2006.201.14:17:48.29#ibcon#read 4, iclass 22, count 0 2006.201.14:17:48.29#ibcon#about to read 5, iclass 22, count 0 2006.201.14:17:48.29#ibcon#read 5, iclass 22, count 0 2006.201.14:17:48.29#ibcon#about to read 6, iclass 22, count 0 2006.201.14:17:48.29#ibcon#read 6, iclass 22, count 0 2006.201.14:17:48.29#ibcon#end of sib2, iclass 22, count 0 2006.201.14:17:48.29#ibcon#*after write, iclass 22, count 0 2006.201.14:17:48.29#ibcon#*before return 0, iclass 22, count 0 2006.201.14:17:48.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:48.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:17:48.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.14:17:48.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.14:17:48.29$vck44/vabw=wide 2006.201.14:17:48.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.14:17:48.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.14:17:48.29#ibcon#ireg 8 cls_cnt 0 2006.201.14:17:48.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:48.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:48.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:48.29#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:17:48.29#ibcon#first serial, iclass 24, count 0 2006.201.14:17:48.29#ibcon#enter sib2, iclass 24, count 0 2006.201.14:17:48.29#ibcon#flushed, iclass 24, count 0 2006.201.14:17:48.29#ibcon#about to write, iclass 24, count 0 2006.201.14:17:48.29#ibcon#wrote, iclass 24, count 0 2006.201.14:17:48.29#ibcon#about to read 3, iclass 24, count 0 2006.201.14:17:48.31#ibcon#read 3, iclass 24, count 0 2006.201.14:17:48.31#ibcon#about to read 4, iclass 24, count 0 2006.201.14:17:48.31#ibcon#read 4, iclass 24, count 0 2006.201.14:17:48.31#ibcon#about to read 5, iclass 24, count 0 2006.201.14:17:48.31#ibcon#read 5, iclass 24, count 0 2006.201.14:17:48.31#ibcon#about to read 6, iclass 24, count 0 2006.201.14:17:48.31#ibcon#read 6, iclass 24, count 0 2006.201.14:17:48.31#ibcon#end of sib2, iclass 24, count 0 2006.201.14:17:48.31#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:17:48.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:17:48.31#ibcon#[25=BW32\r\n] 2006.201.14:17:48.31#ibcon#*before write, iclass 24, count 0 2006.201.14:17:48.31#ibcon#enter sib2, iclass 24, count 0 2006.201.14:17:48.31#ibcon#flushed, iclass 24, count 0 2006.201.14:17:48.31#ibcon#about to write, iclass 24, count 0 2006.201.14:17:48.31#ibcon#wrote, iclass 24, count 0 2006.201.14:17:48.31#ibcon#about to read 3, iclass 24, count 0 2006.201.14:17:48.34#ibcon#read 3, iclass 24, count 0 2006.201.14:17:48.34#ibcon#about to read 4, iclass 24, count 0 2006.201.14:17:48.34#ibcon#read 4, iclass 24, count 0 2006.201.14:17:48.34#ibcon#about to read 5, iclass 24, count 0 2006.201.14:17:48.34#ibcon#read 5, iclass 24, count 0 2006.201.14:17:48.34#ibcon#about to read 6, iclass 24, count 0 2006.201.14:17:48.34#ibcon#read 6, iclass 24, count 0 2006.201.14:17:48.34#ibcon#end of sib2, iclass 24, count 0 2006.201.14:17:48.34#ibcon#*after write, iclass 24, count 0 2006.201.14:17:48.34#ibcon#*before return 0, iclass 24, count 0 2006.201.14:17:48.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:48.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:17:48.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:17:48.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:17:48.34$vck44/vbbw=wide 2006.201.14:17:48.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.14:17:48.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.14:17:48.34#ibcon#ireg 8 cls_cnt 0 2006.201.14:17:48.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:17:48.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:17:48.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:17:48.41#ibcon#enter wrdev, iclass 26, count 0 2006.201.14:17:48.41#ibcon#first serial, iclass 26, count 0 2006.201.14:17:48.41#ibcon#enter sib2, iclass 26, count 0 2006.201.14:17:48.41#ibcon#flushed, iclass 26, count 0 2006.201.14:17:48.41#ibcon#about to write, iclass 26, count 0 2006.201.14:17:48.41#ibcon#wrote, iclass 26, count 0 2006.201.14:17:48.41#ibcon#about to read 3, iclass 26, count 0 2006.201.14:17:48.43#ibcon#read 3, iclass 26, count 0 2006.201.14:17:48.43#ibcon#about to read 4, iclass 26, count 0 2006.201.14:17:48.43#ibcon#read 4, iclass 26, count 0 2006.201.14:17:48.43#ibcon#about to read 5, iclass 26, count 0 2006.201.14:17:48.43#ibcon#read 5, iclass 26, count 0 2006.201.14:17:48.43#ibcon#about to read 6, iclass 26, count 0 2006.201.14:17:48.43#ibcon#read 6, iclass 26, count 0 2006.201.14:17:48.43#ibcon#end of sib2, iclass 26, count 0 2006.201.14:17:48.43#ibcon#*mode == 0, iclass 26, count 0 2006.201.14:17:48.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.14:17:48.43#ibcon#[27=BW32\r\n] 2006.201.14:17:48.43#ibcon#*before write, iclass 26, count 0 2006.201.14:17:48.43#ibcon#enter sib2, iclass 26, count 0 2006.201.14:17:48.43#ibcon#flushed, iclass 26, count 0 2006.201.14:17:48.43#ibcon#about to write, iclass 26, count 0 2006.201.14:17:48.43#ibcon#wrote, iclass 26, count 0 2006.201.14:17:48.43#ibcon#about to read 3, iclass 26, count 0 2006.201.14:17:48.46#ibcon#read 3, iclass 26, count 0 2006.201.14:17:48.46#ibcon#about to read 4, iclass 26, count 0 2006.201.14:17:48.46#ibcon#read 4, iclass 26, count 0 2006.201.14:17:48.46#ibcon#about to read 5, iclass 26, count 0 2006.201.14:17:48.46#ibcon#read 5, iclass 26, count 0 2006.201.14:17:48.46#ibcon#about to read 6, iclass 26, count 0 2006.201.14:17:48.46#ibcon#read 6, iclass 26, count 0 2006.201.14:17:48.46#ibcon#end of sib2, iclass 26, count 0 2006.201.14:17:48.46#ibcon#*after write, iclass 26, count 0 2006.201.14:17:48.46#ibcon#*before return 0, iclass 26, count 0 2006.201.14:17:48.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:17:48.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:17:48.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.14:17:48.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.14:17:48.46$setupk4/ifdk4 2006.201.14:17:48.46$ifdk4/lo= 2006.201.14:17:48.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:17:48.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:17:48.46$ifdk4/patch= 2006.201.14:17:48.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:17:48.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:17:48.46$setupk4/!*+20s 2006.201.14:17:50.79#abcon#<5=/05 1.6 2.8 20.841001003.4\r\n> 2006.201.14:17:50.81#abcon#{5=INTERFACE CLEAR} 2006.201.14:17:50.88#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:17:58.14#trakl#Source acquired 2006.201.14:17:59.14#flagr#flagr/antenna,acquired 2006.201.14:18:00.97#abcon#<5=/05 1.7 2.8 20.841001003.4\r\n> 2006.201.14:18:00.99#abcon#{5=INTERFACE CLEAR} 2006.201.14:18:01.05#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:18:02.94$setupk4/"tpicd 2006.201.14:18:02.94$setupk4/echo=off 2006.201.14:18:02.94$setupk4/xlog=off 2006.201.14:18:02.94:!2006.201.14:18:39 2006.201.14:18:39.00:preob 2006.201.14:18:39.14/onsource/TRACKING 2006.201.14:18:39.14:!2006.201.14:18:49 2006.201.14:18:49.00:"tape 2006.201.14:18:49.00:"st=record 2006.201.14:18:49.00:data_valid=on 2006.201.14:18:49.00:midob 2006.201.14:18:50.14/onsource/TRACKING 2006.201.14:18:50.14/wx/20.84,1003.4,100 2006.201.14:18:50.33/cable/+6.4753E-03 2006.201.14:18:51.42/va/01,08,usb,yes,30,33 2006.201.14:18:51.42/va/02,07,usb,yes,33,34 2006.201.14:18:51.42/va/03,08,usb,yes,30,31 2006.201.14:18:51.42/va/04,07,usb,yes,34,35 2006.201.14:18:51.42/va/05,04,usb,yes,30,30 2006.201.14:18:51.42/va/06,05,usb,yes,30,30 2006.201.14:18:51.42/va/07,05,usb,yes,29,30 2006.201.14:18:51.42/va/08,04,usb,yes,29,35 2006.201.14:18:51.65/valo/01,524.99,yes,locked 2006.201.14:18:51.65/valo/02,534.99,yes,locked 2006.201.14:18:51.65/valo/03,564.99,yes,locked 2006.201.14:18:51.65/valo/04,624.99,yes,locked 2006.201.14:18:51.65/valo/05,734.99,yes,locked 2006.201.14:18:51.65/valo/06,814.99,yes,locked 2006.201.14:18:51.65/valo/07,864.99,yes,locked 2006.201.14:18:51.65/valo/08,884.99,yes,locked 2006.201.14:18:52.74/vb/01,04,usb,yes,30,27 2006.201.14:18:52.74/vb/02,05,usb,yes,28,28 2006.201.14:18:52.74/vb/03,04,usb,yes,29,32 2006.201.14:18:52.74/vb/04,05,usb,yes,29,28 2006.201.14:18:52.74/vb/05,04,usb,yes,26,28 2006.201.14:18:52.74/vb/06,04,usb,yes,30,26 2006.201.14:18:52.74/vb/07,04,usb,yes,30,30 2006.201.14:18:52.74/vb/08,04,usb,yes,28,31 2006.201.14:18:52.98/vblo/01,629.99,yes,locked 2006.201.14:18:52.98/vblo/02,634.99,yes,locked 2006.201.14:18:52.98/vblo/03,649.99,yes,locked 2006.201.14:18:52.98/vblo/04,679.99,yes,locked 2006.201.14:18:52.98/vblo/05,709.99,yes,locked 2006.201.14:18:52.98/vblo/06,719.99,yes,locked 2006.201.14:18:52.98/vblo/07,734.99,yes,locked 2006.201.14:18:52.98/vblo/08,744.99,yes,locked 2006.201.14:18:53.13/vabw/8 2006.201.14:18:53.28/vbbw/8 2006.201.14:18:53.37/xfe/off,on,15.0 2006.201.14:18:53.77/ifatt/23,28,28,28 2006.201.14:18:54.06/fmout-gps/S +4.54E-07 2006.201.14:18:54.10:!2006.201.14:19:29 2006.201.14:19:29.00:data_valid=off 2006.201.14:19:29.00:"et 2006.201.14:19:29.00:!+3s 2006.201.14:19:32.02:"tape 2006.201.14:19:32.02:postob 2006.201.14:19:32.21/cable/+6.4765E-03 2006.201.14:19:32.21/wx/20.83,1003.5,100 2006.201.14:19:32.28/fmout-gps/S +4.53E-07 2006.201.14:19:32.28:scan_name=201-1421,jd0607,120 2006.201.14:19:32.28:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.14:19:34.14#flagr#flagr/antenna,new-source 2006.201.14:19:34.14:checkk5 2006.201.14:19:34.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:19:34.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:19:35.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:19:35.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:19:36.00/chk_obsdata//k5ts1/T2011418??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:19:36.36/chk_obsdata//k5ts2/T2011418??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:19:36.73/chk_obsdata//k5ts3/T2011418??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:19:37.09/chk_obsdata//k5ts4/T2011418??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.14:19:37.78/k5log//k5ts1_log_newline 2006.201.14:19:38.47/k5log//k5ts2_log_newline 2006.201.14:19:39.16/k5log//k5ts3_log_newline 2006.201.14:19:39.84/k5log//k5ts4_log_newline 2006.201.14:19:39.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:19:39.87:setupk4=1 2006.201.14:19:39.87$setupk4/echo=on 2006.201.14:19:39.87$setupk4/pcalon 2006.201.14:19:39.87$pcalon/"no phase cal control is implemented here 2006.201.14:19:39.87$setupk4/"tpicd=stop 2006.201.14:19:39.87$setupk4/"rec=synch_on 2006.201.14:19:39.87$setupk4/"rec_mode=128 2006.201.14:19:39.87$setupk4/!* 2006.201.14:19:39.87$setupk4/recpk4 2006.201.14:19:39.87$recpk4/recpatch= 2006.201.14:19:39.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:19:39.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:19:39.87$setupk4/vck44 2006.201.14:19:39.87$vck44/valo=1,524.99 2006.201.14:19:39.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.14:19:39.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.14:19:39.87#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:39.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:19:39.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:19:39.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:19:39.87#ibcon#enter wrdev, iclass 39, count 0 2006.201.14:19:39.87#ibcon#first serial, iclass 39, count 0 2006.201.14:19:39.87#ibcon#enter sib2, iclass 39, count 0 2006.201.14:19:39.87#ibcon#flushed, iclass 39, count 0 2006.201.14:19:39.87#ibcon#about to write, iclass 39, count 0 2006.201.14:19:39.87#ibcon#wrote, iclass 39, count 0 2006.201.14:19:39.87#ibcon#about to read 3, iclass 39, count 0 2006.201.14:19:39.89#ibcon#read 3, iclass 39, count 0 2006.201.14:19:39.89#ibcon#about to read 4, iclass 39, count 0 2006.201.14:19:39.89#ibcon#read 4, iclass 39, count 0 2006.201.14:19:39.89#ibcon#about to read 5, iclass 39, count 0 2006.201.14:19:39.89#ibcon#read 5, iclass 39, count 0 2006.201.14:19:39.89#ibcon#about to read 6, iclass 39, count 0 2006.201.14:19:39.89#ibcon#read 6, iclass 39, count 0 2006.201.14:19:39.89#ibcon#end of sib2, iclass 39, count 0 2006.201.14:19:39.89#ibcon#*mode == 0, iclass 39, count 0 2006.201.14:19:39.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.14:19:39.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:19:39.89#ibcon#*before write, iclass 39, count 0 2006.201.14:19:39.89#ibcon#enter sib2, iclass 39, count 0 2006.201.14:19:39.89#ibcon#flushed, iclass 39, count 0 2006.201.14:19:39.89#ibcon#about to write, iclass 39, count 0 2006.201.14:19:39.89#ibcon#wrote, iclass 39, count 0 2006.201.14:19:39.89#ibcon#about to read 3, iclass 39, count 0 2006.201.14:19:39.94#ibcon#read 3, iclass 39, count 0 2006.201.14:19:39.94#ibcon#about to read 4, iclass 39, count 0 2006.201.14:19:39.94#ibcon#read 4, iclass 39, count 0 2006.201.14:19:39.94#ibcon#about to read 5, iclass 39, count 0 2006.201.14:19:39.94#ibcon#read 5, iclass 39, count 0 2006.201.14:19:39.94#ibcon#about to read 6, iclass 39, count 0 2006.201.14:19:39.94#ibcon#read 6, iclass 39, count 0 2006.201.14:19:39.94#ibcon#end of sib2, iclass 39, count 0 2006.201.14:19:39.94#ibcon#*after write, iclass 39, count 0 2006.201.14:19:39.94#ibcon#*before return 0, iclass 39, count 0 2006.201.14:19:39.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:19:39.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:19:39.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.14:19:39.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.14:19:39.94$vck44/va=1,8 2006.201.14:19:39.94#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.14:19:39.94#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.14:19:39.94#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:39.94#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:19:39.94#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:19:39.94#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:19:39.94#ibcon#enter wrdev, iclass 2, count 2 2006.201.14:19:39.94#ibcon#first serial, iclass 2, count 2 2006.201.14:19:39.94#ibcon#enter sib2, iclass 2, count 2 2006.201.14:19:39.94#ibcon#flushed, iclass 2, count 2 2006.201.14:19:39.94#ibcon#about to write, iclass 2, count 2 2006.201.14:19:39.94#ibcon#wrote, iclass 2, count 2 2006.201.14:19:39.94#ibcon#about to read 3, iclass 2, count 2 2006.201.14:19:39.96#ibcon#read 3, iclass 2, count 2 2006.201.14:19:39.96#ibcon#about to read 4, iclass 2, count 2 2006.201.14:19:39.96#ibcon#read 4, iclass 2, count 2 2006.201.14:19:39.96#ibcon#about to read 5, iclass 2, count 2 2006.201.14:19:39.96#ibcon#read 5, iclass 2, count 2 2006.201.14:19:39.96#ibcon#about to read 6, iclass 2, count 2 2006.201.14:19:39.96#ibcon#read 6, iclass 2, count 2 2006.201.14:19:39.96#ibcon#end of sib2, iclass 2, count 2 2006.201.14:19:39.96#ibcon#*mode == 0, iclass 2, count 2 2006.201.14:19:39.96#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.14:19:39.96#ibcon#[25=AT01-08\r\n] 2006.201.14:19:39.96#ibcon#*before write, iclass 2, count 2 2006.201.14:19:39.96#ibcon#enter sib2, iclass 2, count 2 2006.201.14:19:39.96#ibcon#flushed, iclass 2, count 2 2006.201.14:19:39.96#ibcon#about to write, iclass 2, count 2 2006.201.14:19:39.96#ibcon#wrote, iclass 2, count 2 2006.201.14:19:39.96#ibcon#about to read 3, iclass 2, count 2 2006.201.14:19:39.99#ibcon#read 3, iclass 2, count 2 2006.201.14:19:39.99#ibcon#about to read 4, iclass 2, count 2 2006.201.14:19:39.99#ibcon#read 4, iclass 2, count 2 2006.201.14:19:39.99#ibcon#about to read 5, iclass 2, count 2 2006.201.14:19:39.99#ibcon#read 5, iclass 2, count 2 2006.201.14:19:39.99#ibcon#about to read 6, iclass 2, count 2 2006.201.14:19:39.99#ibcon#read 6, iclass 2, count 2 2006.201.14:19:39.99#ibcon#end of sib2, iclass 2, count 2 2006.201.14:19:39.99#ibcon#*after write, iclass 2, count 2 2006.201.14:19:39.99#ibcon#*before return 0, iclass 2, count 2 2006.201.14:19:39.99#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:19:39.99#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:19:39.99#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.14:19:39.99#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:39.99#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:19:40.11#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:19:40.11#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:19:40.11#ibcon#enter wrdev, iclass 2, count 0 2006.201.14:19:40.11#ibcon#first serial, iclass 2, count 0 2006.201.14:19:40.11#ibcon#enter sib2, iclass 2, count 0 2006.201.14:19:40.11#ibcon#flushed, iclass 2, count 0 2006.201.14:19:40.11#ibcon#about to write, iclass 2, count 0 2006.201.14:19:40.11#ibcon#wrote, iclass 2, count 0 2006.201.14:19:40.11#ibcon#about to read 3, iclass 2, count 0 2006.201.14:19:40.13#ibcon#read 3, iclass 2, count 0 2006.201.14:19:40.13#ibcon#about to read 4, iclass 2, count 0 2006.201.14:19:40.13#ibcon#read 4, iclass 2, count 0 2006.201.14:19:40.13#ibcon#about to read 5, iclass 2, count 0 2006.201.14:19:40.13#ibcon#read 5, iclass 2, count 0 2006.201.14:19:40.13#ibcon#about to read 6, iclass 2, count 0 2006.201.14:19:40.13#ibcon#read 6, iclass 2, count 0 2006.201.14:19:40.13#ibcon#end of sib2, iclass 2, count 0 2006.201.14:19:40.13#ibcon#*mode == 0, iclass 2, count 0 2006.201.14:19:40.13#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.14:19:40.13#ibcon#[25=USB\r\n] 2006.201.14:19:40.13#ibcon#*before write, iclass 2, count 0 2006.201.14:19:40.13#ibcon#enter sib2, iclass 2, count 0 2006.201.14:19:40.13#ibcon#flushed, iclass 2, count 0 2006.201.14:19:40.13#ibcon#about to write, iclass 2, count 0 2006.201.14:19:40.13#ibcon#wrote, iclass 2, count 0 2006.201.14:19:40.13#ibcon#about to read 3, iclass 2, count 0 2006.201.14:19:40.16#ibcon#read 3, iclass 2, count 0 2006.201.14:19:40.16#ibcon#about to read 4, iclass 2, count 0 2006.201.14:19:40.16#ibcon#read 4, iclass 2, count 0 2006.201.14:19:40.16#ibcon#about to read 5, iclass 2, count 0 2006.201.14:19:40.16#ibcon#read 5, iclass 2, count 0 2006.201.14:19:40.16#ibcon#about to read 6, iclass 2, count 0 2006.201.14:19:40.16#ibcon#read 6, iclass 2, count 0 2006.201.14:19:40.16#ibcon#end of sib2, iclass 2, count 0 2006.201.14:19:40.16#ibcon#*after write, iclass 2, count 0 2006.201.14:19:40.16#ibcon#*before return 0, iclass 2, count 0 2006.201.14:19:40.16#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:19:40.16#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:19:40.16#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.14:19:40.16#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.14:19:40.16$vck44/valo=2,534.99 2006.201.14:19:40.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.14:19:40.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.14:19:40.16#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:40.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:40.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:40.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:40.16#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:19:40.16#ibcon#first serial, iclass 5, count 0 2006.201.14:19:40.16#ibcon#enter sib2, iclass 5, count 0 2006.201.14:19:40.16#ibcon#flushed, iclass 5, count 0 2006.201.14:19:40.16#ibcon#about to write, iclass 5, count 0 2006.201.14:19:40.16#ibcon#wrote, iclass 5, count 0 2006.201.14:19:40.16#ibcon#about to read 3, iclass 5, count 0 2006.201.14:19:40.18#ibcon#read 3, iclass 5, count 0 2006.201.14:19:40.18#ibcon#about to read 4, iclass 5, count 0 2006.201.14:19:40.18#ibcon#read 4, iclass 5, count 0 2006.201.14:19:40.18#ibcon#about to read 5, iclass 5, count 0 2006.201.14:19:40.18#ibcon#read 5, iclass 5, count 0 2006.201.14:19:40.18#ibcon#about to read 6, iclass 5, count 0 2006.201.14:19:40.18#ibcon#read 6, iclass 5, count 0 2006.201.14:19:40.18#ibcon#end of sib2, iclass 5, count 0 2006.201.14:19:40.18#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:19:40.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:19:40.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:19:40.18#ibcon#*before write, iclass 5, count 0 2006.201.14:19:40.18#ibcon#enter sib2, iclass 5, count 0 2006.201.14:19:40.18#ibcon#flushed, iclass 5, count 0 2006.201.14:19:40.18#ibcon#about to write, iclass 5, count 0 2006.201.14:19:40.18#ibcon#wrote, iclass 5, count 0 2006.201.14:19:40.18#ibcon#about to read 3, iclass 5, count 0 2006.201.14:19:40.22#ibcon#read 3, iclass 5, count 0 2006.201.14:19:40.22#ibcon#about to read 4, iclass 5, count 0 2006.201.14:19:40.22#ibcon#read 4, iclass 5, count 0 2006.201.14:19:40.22#ibcon#about to read 5, iclass 5, count 0 2006.201.14:19:40.22#ibcon#read 5, iclass 5, count 0 2006.201.14:19:40.22#ibcon#about to read 6, iclass 5, count 0 2006.201.14:19:40.22#ibcon#read 6, iclass 5, count 0 2006.201.14:19:40.22#ibcon#end of sib2, iclass 5, count 0 2006.201.14:19:40.22#ibcon#*after write, iclass 5, count 0 2006.201.14:19:40.22#ibcon#*before return 0, iclass 5, count 0 2006.201.14:19:40.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:40.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:40.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:19:40.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:19:40.22$vck44/va=2,7 2006.201.14:19:40.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.14:19:40.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.14:19:40.22#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:40.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:40.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:40.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:40.28#ibcon#enter wrdev, iclass 7, count 2 2006.201.14:19:40.28#ibcon#first serial, iclass 7, count 2 2006.201.14:19:40.28#ibcon#enter sib2, iclass 7, count 2 2006.201.14:19:40.28#ibcon#flushed, iclass 7, count 2 2006.201.14:19:40.28#ibcon#about to write, iclass 7, count 2 2006.201.14:19:40.28#ibcon#wrote, iclass 7, count 2 2006.201.14:19:40.28#ibcon#about to read 3, iclass 7, count 2 2006.201.14:19:40.30#ibcon#read 3, iclass 7, count 2 2006.201.14:19:40.30#ibcon#about to read 4, iclass 7, count 2 2006.201.14:19:40.30#ibcon#read 4, iclass 7, count 2 2006.201.14:19:40.30#ibcon#about to read 5, iclass 7, count 2 2006.201.14:19:40.30#ibcon#read 5, iclass 7, count 2 2006.201.14:19:40.30#ibcon#about to read 6, iclass 7, count 2 2006.201.14:19:40.30#ibcon#read 6, iclass 7, count 2 2006.201.14:19:40.30#ibcon#end of sib2, iclass 7, count 2 2006.201.14:19:40.30#ibcon#*mode == 0, iclass 7, count 2 2006.201.14:19:40.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.14:19:40.30#ibcon#[25=AT02-07\r\n] 2006.201.14:19:40.30#ibcon#*before write, iclass 7, count 2 2006.201.14:19:40.30#ibcon#enter sib2, iclass 7, count 2 2006.201.14:19:40.30#ibcon#flushed, iclass 7, count 2 2006.201.14:19:40.30#ibcon#about to write, iclass 7, count 2 2006.201.14:19:40.30#ibcon#wrote, iclass 7, count 2 2006.201.14:19:40.30#ibcon#about to read 3, iclass 7, count 2 2006.201.14:19:40.33#ibcon#read 3, iclass 7, count 2 2006.201.14:19:40.33#ibcon#about to read 4, iclass 7, count 2 2006.201.14:19:40.33#ibcon#read 4, iclass 7, count 2 2006.201.14:19:40.33#ibcon#about to read 5, iclass 7, count 2 2006.201.14:19:40.33#ibcon#read 5, iclass 7, count 2 2006.201.14:19:40.33#ibcon#about to read 6, iclass 7, count 2 2006.201.14:19:40.33#ibcon#read 6, iclass 7, count 2 2006.201.14:19:40.33#ibcon#end of sib2, iclass 7, count 2 2006.201.14:19:40.33#ibcon#*after write, iclass 7, count 2 2006.201.14:19:40.33#ibcon#*before return 0, iclass 7, count 2 2006.201.14:19:40.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:40.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:40.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.14:19:40.33#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:40.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:40.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:40.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:40.45#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:19:40.45#ibcon#first serial, iclass 7, count 0 2006.201.14:19:40.45#ibcon#enter sib2, iclass 7, count 0 2006.201.14:19:40.45#ibcon#flushed, iclass 7, count 0 2006.201.14:19:40.45#ibcon#about to write, iclass 7, count 0 2006.201.14:19:40.45#ibcon#wrote, iclass 7, count 0 2006.201.14:19:40.45#ibcon#about to read 3, iclass 7, count 0 2006.201.14:19:40.47#ibcon#read 3, iclass 7, count 0 2006.201.14:19:40.47#ibcon#about to read 4, iclass 7, count 0 2006.201.14:19:40.47#ibcon#read 4, iclass 7, count 0 2006.201.14:19:40.47#ibcon#about to read 5, iclass 7, count 0 2006.201.14:19:40.47#ibcon#read 5, iclass 7, count 0 2006.201.14:19:40.47#ibcon#about to read 6, iclass 7, count 0 2006.201.14:19:40.47#ibcon#read 6, iclass 7, count 0 2006.201.14:19:40.47#ibcon#end of sib2, iclass 7, count 0 2006.201.14:19:40.47#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:19:40.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:19:40.47#ibcon#[25=USB\r\n] 2006.201.14:19:40.47#ibcon#*before write, iclass 7, count 0 2006.201.14:19:40.47#ibcon#enter sib2, iclass 7, count 0 2006.201.14:19:40.47#ibcon#flushed, iclass 7, count 0 2006.201.14:19:40.47#ibcon#about to write, iclass 7, count 0 2006.201.14:19:40.47#ibcon#wrote, iclass 7, count 0 2006.201.14:19:40.47#ibcon#about to read 3, iclass 7, count 0 2006.201.14:19:40.50#ibcon#read 3, iclass 7, count 0 2006.201.14:19:40.50#ibcon#about to read 4, iclass 7, count 0 2006.201.14:19:40.50#ibcon#read 4, iclass 7, count 0 2006.201.14:19:40.50#ibcon#about to read 5, iclass 7, count 0 2006.201.14:19:40.50#ibcon#read 5, iclass 7, count 0 2006.201.14:19:40.50#ibcon#about to read 6, iclass 7, count 0 2006.201.14:19:40.50#ibcon#read 6, iclass 7, count 0 2006.201.14:19:40.50#ibcon#end of sib2, iclass 7, count 0 2006.201.14:19:40.50#ibcon#*after write, iclass 7, count 0 2006.201.14:19:40.50#ibcon#*before return 0, iclass 7, count 0 2006.201.14:19:40.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:40.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:40.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:19:40.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:19:40.50$vck44/valo=3,564.99 2006.201.14:19:40.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.14:19:40.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.14:19:40.50#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:40.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:40.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:40.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:40.50#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:19:40.50#ibcon#first serial, iclass 11, count 0 2006.201.14:19:40.50#ibcon#enter sib2, iclass 11, count 0 2006.201.14:19:40.50#ibcon#flushed, iclass 11, count 0 2006.201.14:19:40.50#ibcon#about to write, iclass 11, count 0 2006.201.14:19:40.50#ibcon#wrote, iclass 11, count 0 2006.201.14:19:40.50#ibcon#about to read 3, iclass 11, count 0 2006.201.14:19:40.52#ibcon#read 3, iclass 11, count 0 2006.201.14:19:40.52#ibcon#about to read 4, iclass 11, count 0 2006.201.14:19:40.52#ibcon#read 4, iclass 11, count 0 2006.201.14:19:40.52#ibcon#about to read 5, iclass 11, count 0 2006.201.14:19:40.52#ibcon#read 5, iclass 11, count 0 2006.201.14:19:40.52#ibcon#about to read 6, iclass 11, count 0 2006.201.14:19:40.52#ibcon#read 6, iclass 11, count 0 2006.201.14:19:40.52#ibcon#end of sib2, iclass 11, count 0 2006.201.14:19:40.52#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:19:40.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:19:40.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:19:40.52#ibcon#*before write, iclass 11, count 0 2006.201.14:19:40.52#ibcon#enter sib2, iclass 11, count 0 2006.201.14:19:40.52#ibcon#flushed, iclass 11, count 0 2006.201.14:19:40.52#ibcon#about to write, iclass 11, count 0 2006.201.14:19:40.52#ibcon#wrote, iclass 11, count 0 2006.201.14:19:40.52#ibcon#about to read 3, iclass 11, count 0 2006.201.14:19:40.57#ibcon#read 3, iclass 11, count 0 2006.201.14:19:40.57#ibcon#about to read 4, iclass 11, count 0 2006.201.14:19:40.57#ibcon#read 4, iclass 11, count 0 2006.201.14:19:40.57#ibcon#about to read 5, iclass 11, count 0 2006.201.14:19:40.57#ibcon#read 5, iclass 11, count 0 2006.201.14:19:40.57#ibcon#about to read 6, iclass 11, count 0 2006.201.14:19:40.57#ibcon#read 6, iclass 11, count 0 2006.201.14:19:40.57#ibcon#end of sib2, iclass 11, count 0 2006.201.14:19:40.57#ibcon#*after write, iclass 11, count 0 2006.201.14:19:40.57#ibcon#*before return 0, iclass 11, count 0 2006.201.14:19:40.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:40.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:40.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:19:40.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:19:40.57$vck44/va=3,8 2006.201.14:19:40.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.14:19:40.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.14:19:40.57#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:40.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:40.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:40.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:40.62#ibcon#enter wrdev, iclass 13, count 2 2006.201.14:19:40.62#ibcon#first serial, iclass 13, count 2 2006.201.14:19:40.62#ibcon#enter sib2, iclass 13, count 2 2006.201.14:19:40.62#ibcon#flushed, iclass 13, count 2 2006.201.14:19:40.62#ibcon#about to write, iclass 13, count 2 2006.201.14:19:40.62#ibcon#wrote, iclass 13, count 2 2006.201.14:19:40.62#ibcon#about to read 3, iclass 13, count 2 2006.201.14:19:40.64#ibcon#read 3, iclass 13, count 2 2006.201.14:19:40.64#ibcon#about to read 4, iclass 13, count 2 2006.201.14:19:40.64#ibcon#read 4, iclass 13, count 2 2006.201.14:19:40.64#ibcon#about to read 5, iclass 13, count 2 2006.201.14:19:40.64#ibcon#read 5, iclass 13, count 2 2006.201.14:19:40.64#ibcon#about to read 6, iclass 13, count 2 2006.201.14:19:40.64#ibcon#read 6, iclass 13, count 2 2006.201.14:19:40.64#ibcon#end of sib2, iclass 13, count 2 2006.201.14:19:40.64#ibcon#*mode == 0, iclass 13, count 2 2006.201.14:19:40.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.14:19:40.64#ibcon#[25=AT03-08\r\n] 2006.201.14:19:40.64#ibcon#*before write, iclass 13, count 2 2006.201.14:19:40.64#ibcon#enter sib2, iclass 13, count 2 2006.201.14:19:40.64#ibcon#flushed, iclass 13, count 2 2006.201.14:19:40.64#ibcon#about to write, iclass 13, count 2 2006.201.14:19:40.64#ibcon#wrote, iclass 13, count 2 2006.201.14:19:40.64#ibcon#about to read 3, iclass 13, count 2 2006.201.14:19:40.67#ibcon#read 3, iclass 13, count 2 2006.201.14:19:40.67#ibcon#about to read 4, iclass 13, count 2 2006.201.14:19:40.67#ibcon#read 4, iclass 13, count 2 2006.201.14:19:40.67#ibcon#about to read 5, iclass 13, count 2 2006.201.14:19:40.67#ibcon#read 5, iclass 13, count 2 2006.201.14:19:40.67#ibcon#about to read 6, iclass 13, count 2 2006.201.14:19:40.67#ibcon#read 6, iclass 13, count 2 2006.201.14:19:40.67#ibcon#end of sib2, iclass 13, count 2 2006.201.14:19:40.67#ibcon#*after write, iclass 13, count 2 2006.201.14:19:40.67#ibcon#*before return 0, iclass 13, count 2 2006.201.14:19:40.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:40.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:40.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.14:19:40.67#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:40.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:40.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:40.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:40.79#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:19:40.79#ibcon#first serial, iclass 13, count 0 2006.201.14:19:40.79#ibcon#enter sib2, iclass 13, count 0 2006.201.14:19:40.79#ibcon#flushed, iclass 13, count 0 2006.201.14:19:40.79#ibcon#about to write, iclass 13, count 0 2006.201.14:19:40.79#ibcon#wrote, iclass 13, count 0 2006.201.14:19:40.79#ibcon#about to read 3, iclass 13, count 0 2006.201.14:19:40.81#ibcon#read 3, iclass 13, count 0 2006.201.14:19:40.81#ibcon#about to read 4, iclass 13, count 0 2006.201.14:19:40.81#ibcon#read 4, iclass 13, count 0 2006.201.14:19:40.81#ibcon#about to read 5, iclass 13, count 0 2006.201.14:19:40.81#ibcon#read 5, iclass 13, count 0 2006.201.14:19:40.81#ibcon#about to read 6, iclass 13, count 0 2006.201.14:19:40.81#ibcon#read 6, iclass 13, count 0 2006.201.14:19:40.81#ibcon#end of sib2, iclass 13, count 0 2006.201.14:19:40.81#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:19:40.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:19:40.81#ibcon#[25=USB\r\n] 2006.201.14:19:40.81#ibcon#*before write, iclass 13, count 0 2006.201.14:19:40.81#ibcon#enter sib2, iclass 13, count 0 2006.201.14:19:40.81#ibcon#flushed, iclass 13, count 0 2006.201.14:19:40.81#ibcon#about to write, iclass 13, count 0 2006.201.14:19:40.81#ibcon#wrote, iclass 13, count 0 2006.201.14:19:40.81#ibcon#about to read 3, iclass 13, count 0 2006.201.14:19:40.84#ibcon#read 3, iclass 13, count 0 2006.201.14:19:40.84#ibcon#about to read 4, iclass 13, count 0 2006.201.14:19:40.84#ibcon#read 4, iclass 13, count 0 2006.201.14:19:40.84#ibcon#about to read 5, iclass 13, count 0 2006.201.14:19:40.84#ibcon#read 5, iclass 13, count 0 2006.201.14:19:40.84#ibcon#about to read 6, iclass 13, count 0 2006.201.14:19:40.84#ibcon#read 6, iclass 13, count 0 2006.201.14:19:40.84#ibcon#end of sib2, iclass 13, count 0 2006.201.14:19:40.84#ibcon#*after write, iclass 13, count 0 2006.201.14:19:40.84#ibcon#*before return 0, iclass 13, count 0 2006.201.14:19:40.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:40.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:40.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:19:40.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:19:40.84$vck44/valo=4,624.99 2006.201.14:19:40.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.14:19:40.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.14:19:40.84#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:40.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:40.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:40.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:40.84#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:19:40.84#ibcon#first serial, iclass 15, count 0 2006.201.14:19:40.84#ibcon#enter sib2, iclass 15, count 0 2006.201.14:19:40.84#ibcon#flushed, iclass 15, count 0 2006.201.14:19:40.84#ibcon#about to write, iclass 15, count 0 2006.201.14:19:40.84#ibcon#wrote, iclass 15, count 0 2006.201.14:19:40.84#ibcon#about to read 3, iclass 15, count 0 2006.201.14:19:40.86#ibcon#read 3, iclass 15, count 0 2006.201.14:19:40.86#ibcon#about to read 4, iclass 15, count 0 2006.201.14:19:40.86#ibcon#read 4, iclass 15, count 0 2006.201.14:19:40.86#ibcon#about to read 5, iclass 15, count 0 2006.201.14:19:40.86#ibcon#read 5, iclass 15, count 0 2006.201.14:19:40.86#ibcon#about to read 6, iclass 15, count 0 2006.201.14:19:40.86#ibcon#read 6, iclass 15, count 0 2006.201.14:19:40.86#ibcon#end of sib2, iclass 15, count 0 2006.201.14:19:40.86#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:19:40.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:19:40.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:19:40.86#ibcon#*before write, iclass 15, count 0 2006.201.14:19:40.86#ibcon#enter sib2, iclass 15, count 0 2006.201.14:19:40.86#ibcon#flushed, iclass 15, count 0 2006.201.14:19:40.86#ibcon#about to write, iclass 15, count 0 2006.201.14:19:40.86#ibcon#wrote, iclass 15, count 0 2006.201.14:19:40.86#ibcon#about to read 3, iclass 15, count 0 2006.201.14:19:40.90#ibcon#read 3, iclass 15, count 0 2006.201.14:19:40.90#ibcon#about to read 4, iclass 15, count 0 2006.201.14:19:40.90#ibcon#read 4, iclass 15, count 0 2006.201.14:19:40.90#ibcon#about to read 5, iclass 15, count 0 2006.201.14:19:40.90#ibcon#read 5, iclass 15, count 0 2006.201.14:19:40.90#ibcon#about to read 6, iclass 15, count 0 2006.201.14:19:40.90#ibcon#read 6, iclass 15, count 0 2006.201.14:19:40.90#ibcon#end of sib2, iclass 15, count 0 2006.201.14:19:40.90#ibcon#*after write, iclass 15, count 0 2006.201.14:19:40.90#ibcon#*before return 0, iclass 15, count 0 2006.201.14:19:40.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:40.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:40.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:19:40.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:19:40.90$vck44/va=4,7 2006.201.14:19:40.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.14:19:40.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.14:19:40.90#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:40.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:40.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:40.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:40.96#ibcon#enter wrdev, iclass 17, count 2 2006.201.14:19:40.96#ibcon#first serial, iclass 17, count 2 2006.201.14:19:40.96#ibcon#enter sib2, iclass 17, count 2 2006.201.14:19:40.96#ibcon#flushed, iclass 17, count 2 2006.201.14:19:40.96#ibcon#about to write, iclass 17, count 2 2006.201.14:19:40.96#ibcon#wrote, iclass 17, count 2 2006.201.14:19:40.96#ibcon#about to read 3, iclass 17, count 2 2006.201.14:19:40.98#ibcon#read 3, iclass 17, count 2 2006.201.14:19:40.98#ibcon#about to read 4, iclass 17, count 2 2006.201.14:19:40.98#ibcon#read 4, iclass 17, count 2 2006.201.14:19:40.98#ibcon#about to read 5, iclass 17, count 2 2006.201.14:19:40.98#ibcon#read 5, iclass 17, count 2 2006.201.14:19:40.98#ibcon#about to read 6, iclass 17, count 2 2006.201.14:19:40.98#ibcon#read 6, iclass 17, count 2 2006.201.14:19:40.98#ibcon#end of sib2, iclass 17, count 2 2006.201.14:19:40.98#ibcon#*mode == 0, iclass 17, count 2 2006.201.14:19:40.98#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.14:19:40.98#ibcon#[25=AT04-07\r\n] 2006.201.14:19:40.98#ibcon#*before write, iclass 17, count 2 2006.201.14:19:40.98#ibcon#enter sib2, iclass 17, count 2 2006.201.14:19:40.98#ibcon#flushed, iclass 17, count 2 2006.201.14:19:40.98#ibcon#about to write, iclass 17, count 2 2006.201.14:19:40.98#ibcon#wrote, iclass 17, count 2 2006.201.14:19:40.98#ibcon#about to read 3, iclass 17, count 2 2006.201.14:19:41.01#ibcon#read 3, iclass 17, count 2 2006.201.14:19:41.01#ibcon#about to read 4, iclass 17, count 2 2006.201.14:19:41.01#ibcon#read 4, iclass 17, count 2 2006.201.14:19:41.01#ibcon#about to read 5, iclass 17, count 2 2006.201.14:19:41.01#ibcon#read 5, iclass 17, count 2 2006.201.14:19:41.01#ibcon#about to read 6, iclass 17, count 2 2006.201.14:19:41.01#ibcon#read 6, iclass 17, count 2 2006.201.14:19:41.01#ibcon#end of sib2, iclass 17, count 2 2006.201.14:19:41.01#ibcon#*after write, iclass 17, count 2 2006.201.14:19:41.01#ibcon#*before return 0, iclass 17, count 2 2006.201.14:19:41.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:41.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:41.01#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.14:19:41.01#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:41.01#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:41.13#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:41.13#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:41.13#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:19:41.13#ibcon#first serial, iclass 17, count 0 2006.201.14:19:41.13#ibcon#enter sib2, iclass 17, count 0 2006.201.14:19:41.13#ibcon#flushed, iclass 17, count 0 2006.201.14:19:41.13#ibcon#about to write, iclass 17, count 0 2006.201.14:19:41.13#ibcon#wrote, iclass 17, count 0 2006.201.14:19:41.13#ibcon#about to read 3, iclass 17, count 0 2006.201.14:19:41.15#ibcon#read 3, iclass 17, count 0 2006.201.14:19:41.15#ibcon#about to read 4, iclass 17, count 0 2006.201.14:19:41.15#ibcon#read 4, iclass 17, count 0 2006.201.14:19:41.15#ibcon#about to read 5, iclass 17, count 0 2006.201.14:19:41.15#ibcon#read 5, iclass 17, count 0 2006.201.14:19:41.15#ibcon#about to read 6, iclass 17, count 0 2006.201.14:19:41.15#ibcon#read 6, iclass 17, count 0 2006.201.14:19:41.15#ibcon#end of sib2, iclass 17, count 0 2006.201.14:19:41.15#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:19:41.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:19:41.15#ibcon#[25=USB\r\n] 2006.201.14:19:41.15#ibcon#*before write, iclass 17, count 0 2006.201.14:19:41.15#ibcon#enter sib2, iclass 17, count 0 2006.201.14:19:41.15#ibcon#flushed, iclass 17, count 0 2006.201.14:19:41.15#ibcon#about to write, iclass 17, count 0 2006.201.14:19:41.15#ibcon#wrote, iclass 17, count 0 2006.201.14:19:41.15#ibcon#about to read 3, iclass 17, count 0 2006.201.14:19:41.18#ibcon#read 3, iclass 17, count 0 2006.201.14:19:41.18#ibcon#about to read 4, iclass 17, count 0 2006.201.14:19:41.18#ibcon#read 4, iclass 17, count 0 2006.201.14:19:41.18#ibcon#about to read 5, iclass 17, count 0 2006.201.14:19:41.18#ibcon#read 5, iclass 17, count 0 2006.201.14:19:41.18#ibcon#about to read 6, iclass 17, count 0 2006.201.14:19:41.18#ibcon#read 6, iclass 17, count 0 2006.201.14:19:41.18#ibcon#end of sib2, iclass 17, count 0 2006.201.14:19:41.18#ibcon#*after write, iclass 17, count 0 2006.201.14:19:41.18#ibcon#*before return 0, iclass 17, count 0 2006.201.14:19:41.18#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:41.18#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:41.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:19:41.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:19:41.18$vck44/valo=5,734.99 2006.201.14:19:41.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.14:19:41.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.14:19:41.18#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:41.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:41.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:41.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:41.18#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:19:41.18#ibcon#first serial, iclass 19, count 0 2006.201.14:19:41.18#ibcon#enter sib2, iclass 19, count 0 2006.201.14:19:41.18#ibcon#flushed, iclass 19, count 0 2006.201.14:19:41.18#ibcon#about to write, iclass 19, count 0 2006.201.14:19:41.18#ibcon#wrote, iclass 19, count 0 2006.201.14:19:41.18#ibcon#about to read 3, iclass 19, count 0 2006.201.14:19:41.20#ibcon#read 3, iclass 19, count 0 2006.201.14:19:41.20#ibcon#about to read 4, iclass 19, count 0 2006.201.14:19:41.20#ibcon#read 4, iclass 19, count 0 2006.201.14:19:41.20#ibcon#about to read 5, iclass 19, count 0 2006.201.14:19:41.20#ibcon#read 5, iclass 19, count 0 2006.201.14:19:41.20#ibcon#about to read 6, iclass 19, count 0 2006.201.14:19:41.20#ibcon#read 6, iclass 19, count 0 2006.201.14:19:41.20#ibcon#end of sib2, iclass 19, count 0 2006.201.14:19:41.20#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:19:41.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:19:41.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:19:41.20#ibcon#*before write, iclass 19, count 0 2006.201.14:19:41.20#ibcon#enter sib2, iclass 19, count 0 2006.201.14:19:41.20#ibcon#flushed, iclass 19, count 0 2006.201.14:19:41.20#ibcon#about to write, iclass 19, count 0 2006.201.14:19:41.20#ibcon#wrote, iclass 19, count 0 2006.201.14:19:41.20#ibcon#about to read 3, iclass 19, count 0 2006.201.14:19:41.24#ibcon#read 3, iclass 19, count 0 2006.201.14:19:41.24#ibcon#about to read 4, iclass 19, count 0 2006.201.14:19:41.24#ibcon#read 4, iclass 19, count 0 2006.201.14:19:41.24#ibcon#about to read 5, iclass 19, count 0 2006.201.14:19:41.24#ibcon#read 5, iclass 19, count 0 2006.201.14:19:41.24#ibcon#about to read 6, iclass 19, count 0 2006.201.14:19:41.24#ibcon#read 6, iclass 19, count 0 2006.201.14:19:41.24#ibcon#end of sib2, iclass 19, count 0 2006.201.14:19:41.24#ibcon#*after write, iclass 19, count 0 2006.201.14:19:41.24#ibcon#*before return 0, iclass 19, count 0 2006.201.14:19:41.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:41.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:41.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:19:41.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:19:41.24$vck44/va=5,4 2006.201.14:19:41.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.14:19:41.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.14:19:41.24#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:41.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:41.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:41.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:41.30#ibcon#enter wrdev, iclass 21, count 2 2006.201.14:19:41.30#ibcon#first serial, iclass 21, count 2 2006.201.14:19:41.30#ibcon#enter sib2, iclass 21, count 2 2006.201.14:19:41.30#ibcon#flushed, iclass 21, count 2 2006.201.14:19:41.30#ibcon#about to write, iclass 21, count 2 2006.201.14:19:41.30#ibcon#wrote, iclass 21, count 2 2006.201.14:19:41.30#ibcon#about to read 3, iclass 21, count 2 2006.201.14:19:41.32#ibcon#read 3, iclass 21, count 2 2006.201.14:19:41.32#ibcon#about to read 4, iclass 21, count 2 2006.201.14:19:41.32#ibcon#read 4, iclass 21, count 2 2006.201.14:19:41.32#ibcon#about to read 5, iclass 21, count 2 2006.201.14:19:41.32#ibcon#read 5, iclass 21, count 2 2006.201.14:19:41.32#ibcon#about to read 6, iclass 21, count 2 2006.201.14:19:41.32#ibcon#read 6, iclass 21, count 2 2006.201.14:19:41.32#ibcon#end of sib2, iclass 21, count 2 2006.201.14:19:41.32#ibcon#*mode == 0, iclass 21, count 2 2006.201.14:19:41.32#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.14:19:41.32#ibcon#[25=AT05-04\r\n] 2006.201.14:19:41.32#ibcon#*before write, iclass 21, count 2 2006.201.14:19:41.32#ibcon#enter sib2, iclass 21, count 2 2006.201.14:19:41.32#ibcon#flushed, iclass 21, count 2 2006.201.14:19:41.32#ibcon#about to write, iclass 21, count 2 2006.201.14:19:41.32#ibcon#wrote, iclass 21, count 2 2006.201.14:19:41.32#ibcon#about to read 3, iclass 21, count 2 2006.201.14:19:41.35#ibcon#read 3, iclass 21, count 2 2006.201.14:19:41.35#ibcon#about to read 4, iclass 21, count 2 2006.201.14:19:41.35#ibcon#read 4, iclass 21, count 2 2006.201.14:19:41.35#ibcon#about to read 5, iclass 21, count 2 2006.201.14:19:41.35#ibcon#read 5, iclass 21, count 2 2006.201.14:19:41.35#ibcon#about to read 6, iclass 21, count 2 2006.201.14:19:41.35#ibcon#read 6, iclass 21, count 2 2006.201.14:19:41.35#ibcon#end of sib2, iclass 21, count 2 2006.201.14:19:41.35#ibcon#*after write, iclass 21, count 2 2006.201.14:19:41.35#ibcon#*before return 0, iclass 21, count 2 2006.201.14:19:41.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:41.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:41.35#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.14:19:41.35#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:41.35#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:41.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:41.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:41.47#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:19:41.47#ibcon#first serial, iclass 21, count 0 2006.201.14:19:41.47#ibcon#enter sib2, iclass 21, count 0 2006.201.14:19:41.47#ibcon#flushed, iclass 21, count 0 2006.201.14:19:41.47#ibcon#about to write, iclass 21, count 0 2006.201.14:19:41.47#ibcon#wrote, iclass 21, count 0 2006.201.14:19:41.47#ibcon#about to read 3, iclass 21, count 0 2006.201.14:19:41.49#ibcon#read 3, iclass 21, count 0 2006.201.14:19:41.49#ibcon#about to read 4, iclass 21, count 0 2006.201.14:19:41.49#ibcon#read 4, iclass 21, count 0 2006.201.14:19:41.49#ibcon#about to read 5, iclass 21, count 0 2006.201.14:19:41.49#ibcon#read 5, iclass 21, count 0 2006.201.14:19:41.49#ibcon#about to read 6, iclass 21, count 0 2006.201.14:19:41.49#ibcon#read 6, iclass 21, count 0 2006.201.14:19:41.49#ibcon#end of sib2, iclass 21, count 0 2006.201.14:19:41.49#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:19:41.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:19:41.49#ibcon#[25=USB\r\n] 2006.201.14:19:41.49#ibcon#*before write, iclass 21, count 0 2006.201.14:19:41.49#ibcon#enter sib2, iclass 21, count 0 2006.201.14:19:41.49#ibcon#flushed, iclass 21, count 0 2006.201.14:19:41.49#ibcon#about to write, iclass 21, count 0 2006.201.14:19:41.49#ibcon#wrote, iclass 21, count 0 2006.201.14:19:41.49#ibcon#about to read 3, iclass 21, count 0 2006.201.14:19:41.52#ibcon#read 3, iclass 21, count 0 2006.201.14:19:41.52#ibcon#about to read 4, iclass 21, count 0 2006.201.14:19:41.52#ibcon#read 4, iclass 21, count 0 2006.201.14:19:41.52#ibcon#about to read 5, iclass 21, count 0 2006.201.14:19:41.52#ibcon#read 5, iclass 21, count 0 2006.201.14:19:41.52#ibcon#about to read 6, iclass 21, count 0 2006.201.14:19:41.52#ibcon#read 6, iclass 21, count 0 2006.201.14:19:41.52#ibcon#end of sib2, iclass 21, count 0 2006.201.14:19:41.52#ibcon#*after write, iclass 21, count 0 2006.201.14:19:41.52#ibcon#*before return 0, iclass 21, count 0 2006.201.14:19:41.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:41.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:41.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:19:41.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:19:41.52$vck44/valo=6,814.99 2006.201.14:19:41.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.14:19:41.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.14:19:41.52#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:41.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:41.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:41.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:41.52#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:19:41.52#ibcon#first serial, iclass 23, count 0 2006.201.14:19:41.52#ibcon#enter sib2, iclass 23, count 0 2006.201.14:19:41.52#ibcon#flushed, iclass 23, count 0 2006.201.14:19:41.52#ibcon#about to write, iclass 23, count 0 2006.201.14:19:41.52#ibcon#wrote, iclass 23, count 0 2006.201.14:19:41.52#ibcon#about to read 3, iclass 23, count 0 2006.201.14:19:41.54#ibcon#read 3, iclass 23, count 0 2006.201.14:19:41.54#ibcon#about to read 4, iclass 23, count 0 2006.201.14:19:41.54#ibcon#read 4, iclass 23, count 0 2006.201.14:19:41.54#ibcon#about to read 5, iclass 23, count 0 2006.201.14:19:41.54#ibcon#read 5, iclass 23, count 0 2006.201.14:19:41.54#ibcon#about to read 6, iclass 23, count 0 2006.201.14:19:41.54#ibcon#read 6, iclass 23, count 0 2006.201.14:19:41.54#ibcon#end of sib2, iclass 23, count 0 2006.201.14:19:41.54#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:19:41.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:19:41.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:19:41.54#ibcon#*before write, iclass 23, count 0 2006.201.14:19:41.54#ibcon#enter sib2, iclass 23, count 0 2006.201.14:19:41.54#ibcon#flushed, iclass 23, count 0 2006.201.14:19:41.54#ibcon#about to write, iclass 23, count 0 2006.201.14:19:41.54#ibcon#wrote, iclass 23, count 0 2006.201.14:19:41.54#ibcon#about to read 3, iclass 23, count 0 2006.201.14:19:41.58#ibcon#read 3, iclass 23, count 0 2006.201.14:19:41.58#ibcon#about to read 4, iclass 23, count 0 2006.201.14:19:41.58#ibcon#read 4, iclass 23, count 0 2006.201.14:19:41.58#ibcon#about to read 5, iclass 23, count 0 2006.201.14:19:41.58#ibcon#read 5, iclass 23, count 0 2006.201.14:19:41.58#ibcon#about to read 6, iclass 23, count 0 2006.201.14:19:41.58#ibcon#read 6, iclass 23, count 0 2006.201.14:19:41.58#ibcon#end of sib2, iclass 23, count 0 2006.201.14:19:41.58#ibcon#*after write, iclass 23, count 0 2006.201.14:19:41.58#ibcon#*before return 0, iclass 23, count 0 2006.201.14:19:41.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:41.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:41.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:19:41.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:19:41.58$vck44/va=6,5 2006.201.14:19:41.58#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.14:19:41.58#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.14:19:41.58#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:41.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:41.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:41.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:41.64#ibcon#enter wrdev, iclass 25, count 2 2006.201.14:19:41.64#ibcon#first serial, iclass 25, count 2 2006.201.14:19:41.64#ibcon#enter sib2, iclass 25, count 2 2006.201.14:19:41.64#ibcon#flushed, iclass 25, count 2 2006.201.14:19:41.64#ibcon#about to write, iclass 25, count 2 2006.201.14:19:41.64#ibcon#wrote, iclass 25, count 2 2006.201.14:19:41.64#ibcon#about to read 3, iclass 25, count 2 2006.201.14:19:41.66#ibcon#read 3, iclass 25, count 2 2006.201.14:19:41.66#ibcon#about to read 4, iclass 25, count 2 2006.201.14:19:41.66#ibcon#read 4, iclass 25, count 2 2006.201.14:19:41.66#ibcon#about to read 5, iclass 25, count 2 2006.201.14:19:41.66#ibcon#read 5, iclass 25, count 2 2006.201.14:19:41.66#ibcon#about to read 6, iclass 25, count 2 2006.201.14:19:41.66#ibcon#read 6, iclass 25, count 2 2006.201.14:19:41.66#ibcon#end of sib2, iclass 25, count 2 2006.201.14:19:41.66#ibcon#*mode == 0, iclass 25, count 2 2006.201.14:19:41.66#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.14:19:41.66#ibcon#[25=AT06-05\r\n] 2006.201.14:19:41.66#ibcon#*before write, iclass 25, count 2 2006.201.14:19:41.66#ibcon#enter sib2, iclass 25, count 2 2006.201.14:19:41.66#ibcon#flushed, iclass 25, count 2 2006.201.14:19:41.66#ibcon#about to write, iclass 25, count 2 2006.201.14:19:41.66#ibcon#wrote, iclass 25, count 2 2006.201.14:19:41.66#ibcon#about to read 3, iclass 25, count 2 2006.201.14:19:41.69#ibcon#read 3, iclass 25, count 2 2006.201.14:19:41.69#ibcon#about to read 4, iclass 25, count 2 2006.201.14:19:41.69#ibcon#read 4, iclass 25, count 2 2006.201.14:19:41.69#ibcon#about to read 5, iclass 25, count 2 2006.201.14:19:41.69#ibcon#read 5, iclass 25, count 2 2006.201.14:19:41.69#ibcon#about to read 6, iclass 25, count 2 2006.201.14:19:41.69#ibcon#read 6, iclass 25, count 2 2006.201.14:19:41.69#ibcon#end of sib2, iclass 25, count 2 2006.201.14:19:41.69#ibcon#*after write, iclass 25, count 2 2006.201.14:19:41.69#ibcon#*before return 0, iclass 25, count 2 2006.201.14:19:41.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:41.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:41.69#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.14:19:41.69#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:41.69#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:41.81#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:41.81#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:41.81#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:19:41.81#ibcon#first serial, iclass 25, count 0 2006.201.14:19:41.81#ibcon#enter sib2, iclass 25, count 0 2006.201.14:19:41.81#ibcon#flushed, iclass 25, count 0 2006.201.14:19:41.81#ibcon#about to write, iclass 25, count 0 2006.201.14:19:41.81#ibcon#wrote, iclass 25, count 0 2006.201.14:19:41.81#ibcon#about to read 3, iclass 25, count 0 2006.201.14:19:41.83#ibcon#read 3, iclass 25, count 0 2006.201.14:19:41.83#ibcon#about to read 4, iclass 25, count 0 2006.201.14:19:41.83#ibcon#read 4, iclass 25, count 0 2006.201.14:19:41.83#ibcon#about to read 5, iclass 25, count 0 2006.201.14:19:41.83#ibcon#read 5, iclass 25, count 0 2006.201.14:19:41.83#ibcon#about to read 6, iclass 25, count 0 2006.201.14:19:41.83#ibcon#read 6, iclass 25, count 0 2006.201.14:19:41.83#ibcon#end of sib2, iclass 25, count 0 2006.201.14:19:41.83#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:19:41.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:19:41.83#ibcon#[25=USB\r\n] 2006.201.14:19:41.83#ibcon#*before write, iclass 25, count 0 2006.201.14:19:41.83#ibcon#enter sib2, iclass 25, count 0 2006.201.14:19:41.83#ibcon#flushed, iclass 25, count 0 2006.201.14:19:41.83#ibcon#about to write, iclass 25, count 0 2006.201.14:19:41.83#ibcon#wrote, iclass 25, count 0 2006.201.14:19:41.83#ibcon#about to read 3, iclass 25, count 0 2006.201.14:19:41.86#ibcon#read 3, iclass 25, count 0 2006.201.14:19:41.86#ibcon#about to read 4, iclass 25, count 0 2006.201.14:19:41.86#ibcon#read 4, iclass 25, count 0 2006.201.14:19:41.86#ibcon#about to read 5, iclass 25, count 0 2006.201.14:19:41.86#ibcon#read 5, iclass 25, count 0 2006.201.14:19:41.86#ibcon#about to read 6, iclass 25, count 0 2006.201.14:19:41.86#ibcon#read 6, iclass 25, count 0 2006.201.14:19:41.86#ibcon#end of sib2, iclass 25, count 0 2006.201.14:19:41.86#ibcon#*after write, iclass 25, count 0 2006.201.14:19:41.86#ibcon#*before return 0, iclass 25, count 0 2006.201.14:19:41.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:41.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:41.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:19:41.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:19:41.86$vck44/valo=7,864.99 2006.201.14:19:41.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.14:19:41.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.14:19:41.86#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:41.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:41.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:41.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:41.86#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:19:41.86#ibcon#first serial, iclass 27, count 0 2006.201.14:19:41.86#ibcon#enter sib2, iclass 27, count 0 2006.201.14:19:41.86#ibcon#flushed, iclass 27, count 0 2006.201.14:19:41.86#ibcon#about to write, iclass 27, count 0 2006.201.14:19:41.86#ibcon#wrote, iclass 27, count 0 2006.201.14:19:41.86#ibcon#about to read 3, iclass 27, count 0 2006.201.14:19:41.88#ibcon#read 3, iclass 27, count 0 2006.201.14:19:41.88#ibcon#about to read 4, iclass 27, count 0 2006.201.14:19:41.88#ibcon#read 4, iclass 27, count 0 2006.201.14:19:41.88#ibcon#about to read 5, iclass 27, count 0 2006.201.14:19:41.88#ibcon#read 5, iclass 27, count 0 2006.201.14:19:41.88#ibcon#about to read 6, iclass 27, count 0 2006.201.14:19:41.88#ibcon#read 6, iclass 27, count 0 2006.201.14:19:41.88#ibcon#end of sib2, iclass 27, count 0 2006.201.14:19:41.88#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:19:41.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:19:41.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:19:41.88#ibcon#*before write, iclass 27, count 0 2006.201.14:19:41.88#ibcon#enter sib2, iclass 27, count 0 2006.201.14:19:41.88#ibcon#flushed, iclass 27, count 0 2006.201.14:19:41.88#ibcon#about to write, iclass 27, count 0 2006.201.14:19:41.88#ibcon#wrote, iclass 27, count 0 2006.201.14:19:41.88#ibcon#about to read 3, iclass 27, count 0 2006.201.14:19:41.92#ibcon#read 3, iclass 27, count 0 2006.201.14:19:41.92#ibcon#about to read 4, iclass 27, count 0 2006.201.14:19:41.92#ibcon#read 4, iclass 27, count 0 2006.201.14:19:41.92#ibcon#about to read 5, iclass 27, count 0 2006.201.14:19:41.92#ibcon#read 5, iclass 27, count 0 2006.201.14:19:41.92#ibcon#about to read 6, iclass 27, count 0 2006.201.14:19:41.92#ibcon#read 6, iclass 27, count 0 2006.201.14:19:41.92#ibcon#end of sib2, iclass 27, count 0 2006.201.14:19:41.92#ibcon#*after write, iclass 27, count 0 2006.201.14:19:41.92#ibcon#*before return 0, iclass 27, count 0 2006.201.14:19:41.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:41.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:41.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:19:41.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:19:41.92$vck44/va=7,5 2006.201.14:19:41.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.14:19:41.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.14:19:41.92#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:41.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:41.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:41.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:41.98#ibcon#enter wrdev, iclass 29, count 2 2006.201.14:19:41.98#ibcon#first serial, iclass 29, count 2 2006.201.14:19:41.98#ibcon#enter sib2, iclass 29, count 2 2006.201.14:19:41.98#ibcon#flushed, iclass 29, count 2 2006.201.14:19:41.98#ibcon#about to write, iclass 29, count 2 2006.201.14:19:41.98#ibcon#wrote, iclass 29, count 2 2006.201.14:19:41.98#ibcon#about to read 3, iclass 29, count 2 2006.201.14:19:42.00#ibcon#read 3, iclass 29, count 2 2006.201.14:19:42.00#ibcon#about to read 4, iclass 29, count 2 2006.201.14:19:42.00#ibcon#read 4, iclass 29, count 2 2006.201.14:19:42.00#ibcon#about to read 5, iclass 29, count 2 2006.201.14:19:42.00#ibcon#read 5, iclass 29, count 2 2006.201.14:19:42.00#ibcon#about to read 6, iclass 29, count 2 2006.201.14:19:42.00#ibcon#read 6, iclass 29, count 2 2006.201.14:19:42.00#ibcon#end of sib2, iclass 29, count 2 2006.201.14:19:42.00#ibcon#*mode == 0, iclass 29, count 2 2006.201.14:19:42.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.14:19:42.00#ibcon#[25=AT07-05\r\n] 2006.201.14:19:42.00#ibcon#*before write, iclass 29, count 2 2006.201.14:19:42.00#ibcon#enter sib2, iclass 29, count 2 2006.201.14:19:42.00#ibcon#flushed, iclass 29, count 2 2006.201.14:19:42.00#ibcon#about to write, iclass 29, count 2 2006.201.14:19:42.00#ibcon#wrote, iclass 29, count 2 2006.201.14:19:42.00#ibcon#about to read 3, iclass 29, count 2 2006.201.14:19:42.03#ibcon#read 3, iclass 29, count 2 2006.201.14:19:42.03#ibcon#about to read 4, iclass 29, count 2 2006.201.14:19:42.03#ibcon#read 4, iclass 29, count 2 2006.201.14:19:42.03#ibcon#about to read 5, iclass 29, count 2 2006.201.14:19:42.03#ibcon#read 5, iclass 29, count 2 2006.201.14:19:42.03#ibcon#about to read 6, iclass 29, count 2 2006.201.14:19:42.03#ibcon#read 6, iclass 29, count 2 2006.201.14:19:42.03#ibcon#end of sib2, iclass 29, count 2 2006.201.14:19:42.03#ibcon#*after write, iclass 29, count 2 2006.201.14:19:42.03#ibcon#*before return 0, iclass 29, count 2 2006.201.14:19:42.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:42.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:42.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.14:19:42.03#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:42.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:42.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:42.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:42.15#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:19:42.15#ibcon#first serial, iclass 29, count 0 2006.201.14:19:42.15#ibcon#enter sib2, iclass 29, count 0 2006.201.14:19:42.15#ibcon#flushed, iclass 29, count 0 2006.201.14:19:42.15#ibcon#about to write, iclass 29, count 0 2006.201.14:19:42.15#ibcon#wrote, iclass 29, count 0 2006.201.14:19:42.15#ibcon#about to read 3, iclass 29, count 0 2006.201.14:19:42.17#ibcon#read 3, iclass 29, count 0 2006.201.14:19:42.17#ibcon#about to read 4, iclass 29, count 0 2006.201.14:19:42.17#ibcon#read 4, iclass 29, count 0 2006.201.14:19:42.17#ibcon#about to read 5, iclass 29, count 0 2006.201.14:19:42.17#ibcon#read 5, iclass 29, count 0 2006.201.14:19:42.17#ibcon#about to read 6, iclass 29, count 0 2006.201.14:19:42.17#ibcon#read 6, iclass 29, count 0 2006.201.14:19:42.17#ibcon#end of sib2, iclass 29, count 0 2006.201.14:19:42.17#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:19:42.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:19:42.17#ibcon#[25=USB\r\n] 2006.201.14:19:42.17#ibcon#*before write, iclass 29, count 0 2006.201.14:19:42.17#ibcon#enter sib2, iclass 29, count 0 2006.201.14:19:42.17#ibcon#flushed, iclass 29, count 0 2006.201.14:19:42.17#ibcon#about to write, iclass 29, count 0 2006.201.14:19:42.17#ibcon#wrote, iclass 29, count 0 2006.201.14:19:42.17#ibcon#about to read 3, iclass 29, count 0 2006.201.14:19:42.20#ibcon#read 3, iclass 29, count 0 2006.201.14:19:42.20#ibcon#about to read 4, iclass 29, count 0 2006.201.14:19:42.20#ibcon#read 4, iclass 29, count 0 2006.201.14:19:42.20#ibcon#about to read 5, iclass 29, count 0 2006.201.14:19:42.20#ibcon#read 5, iclass 29, count 0 2006.201.14:19:42.20#ibcon#about to read 6, iclass 29, count 0 2006.201.14:19:42.20#ibcon#read 6, iclass 29, count 0 2006.201.14:19:42.20#ibcon#end of sib2, iclass 29, count 0 2006.201.14:19:42.20#ibcon#*after write, iclass 29, count 0 2006.201.14:19:42.20#ibcon#*before return 0, iclass 29, count 0 2006.201.14:19:42.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:42.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:42.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:19:42.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:19:42.20$vck44/valo=8,884.99 2006.201.14:19:42.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.14:19:42.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.14:19:42.20#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:42.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:42.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:42.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:42.20#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:19:42.20#ibcon#first serial, iclass 31, count 0 2006.201.14:19:42.20#ibcon#enter sib2, iclass 31, count 0 2006.201.14:19:42.20#ibcon#flushed, iclass 31, count 0 2006.201.14:19:42.20#ibcon#about to write, iclass 31, count 0 2006.201.14:19:42.20#ibcon#wrote, iclass 31, count 0 2006.201.14:19:42.20#ibcon#about to read 3, iclass 31, count 0 2006.201.14:19:42.22#ibcon#read 3, iclass 31, count 0 2006.201.14:19:42.22#ibcon#about to read 4, iclass 31, count 0 2006.201.14:19:42.22#ibcon#read 4, iclass 31, count 0 2006.201.14:19:42.22#ibcon#about to read 5, iclass 31, count 0 2006.201.14:19:42.22#ibcon#read 5, iclass 31, count 0 2006.201.14:19:42.22#ibcon#about to read 6, iclass 31, count 0 2006.201.14:19:42.22#ibcon#read 6, iclass 31, count 0 2006.201.14:19:42.22#ibcon#end of sib2, iclass 31, count 0 2006.201.14:19:42.22#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:19:42.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:19:42.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:19:42.22#ibcon#*before write, iclass 31, count 0 2006.201.14:19:42.22#ibcon#enter sib2, iclass 31, count 0 2006.201.14:19:42.22#ibcon#flushed, iclass 31, count 0 2006.201.14:19:42.22#ibcon#about to write, iclass 31, count 0 2006.201.14:19:42.22#ibcon#wrote, iclass 31, count 0 2006.201.14:19:42.22#ibcon#about to read 3, iclass 31, count 0 2006.201.14:19:42.26#ibcon#read 3, iclass 31, count 0 2006.201.14:19:42.26#ibcon#about to read 4, iclass 31, count 0 2006.201.14:19:42.26#ibcon#read 4, iclass 31, count 0 2006.201.14:19:42.26#ibcon#about to read 5, iclass 31, count 0 2006.201.14:19:42.26#ibcon#read 5, iclass 31, count 0 2006.201.14:19:42.26#ibcon#about to read 6, iclass 31, count 0 2006.201.14:19:42.26#ibcon#read 6, iclass 31, count 0 2006.201.14:19:42.26#ibcon#end of sib2, iclass 31, count 0 2006.201.14:19:42.26#ibcon#*after write, iclass 31, count 0 2006.201.14:19:42.26#ibcon#*before return 0, iclass 31, count 0 2006.201.14:19:42.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:42.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:42.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:19:42.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:19:42.26$vck44/va=8,4 2006.201.14:19:42.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.14:19:42.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.14:19:42.26#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:42.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:42.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:42.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:42.32#ibcon#enter wrdev, iclass 33, count 2 2006.201.14:19:42.32#ibcon#first serial, iclass 33, count 2 2006.201.14:19:42.32#ibcon#enter sib2, iclass 33, count 2 2006.201.14:19:42.32#ibcon#flushed, iclass 33, count 2 2006.201.14:19:42.32#ibcon#about to write, iclass 33, count 2 2006.201.14:19:42.32#ibcon#wrote, iclass 33, count 2 2006.201.14:19:42.32#ibcon#about to read 3, iclass 33, count 2 2006.201.14:19:42.34#ibcon#read 3, iclass 33, count 2 2006.201.14:19:42.34#ibcon#about to read 4, iclass 33, count 2 2006.201.14:19:42.34#ibcon#read 4, iclass 33, count 2 2006.201.14:19:42.34#ibcon#about to read 5, iclass 33, count 2 2006.201.14:19:42.34#ibcon#read 5, iclass 33, count 2 2006.201.14:19:42.34#ibcon#about to read 6, iclass 33, count 2 2006.201.14:19:42.34#ibcon#read 6, iclass 33, count 2 2006.201.14:19:42.34#ibcon#end of sib2, iclass 33, count 2 2006.201.14:19:42.34#ibcon#*mode == 0, iclass 33, count 2 2006.201.14:19:42.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.14:19:42.34#ibcon#[25=AT08-04\r\n] 2006.201.14:19:42.34#ibcon#*before write, iclass 33, count 2 2006.201.14:19:42.34#ibcon#enter sib2, iclass 33, count 2 2006.201.14:19:42.34#ibcon#flushed, iclass 33, count 2 2006.201.14:19:42.34#ibcon#about to write, iclass 33, count 2 2006.201.14:19:42.34#ibcon#wrote, iclass 33, count 2 2006.201.14:19:42.34#ibcon#about to read 3, iclass 33, count 2 2006.201.14:19:42.37#ibcon#read 3, iclass 33, count 2 2006.201.14:19:42.37#ibcon#about to read 4, iclass 33, count 2 2006.201.14:19:42.37#ibcon#read 4, iclass 33, count 2 2006.201.14:19:42.37#ibcon#about to read 5, iclass 33, count 2 2006.201.14:19:42.37#ibcon#read 5, iclass 33, count 2 2006.201.14:19:42.37#ibcon#about to read 6, iclass 33, count 2 2006.201.14:19:42.37#ibcon#read 6, iclass 33, count 2 2006.201.14:19:42.37#ibcon#end of sib2, iclass 33, count 2 2006.201.14:19:42.37#ibcon#*after write, iclass 33, count 2 2006.201.14:19:42.37#ibcon#*before return 0, iclass 33, count 2 2006.201.14:19:42.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:42.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:42.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.14:19:42.37#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:42.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:42.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:42.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:42.49#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:19:42.49#ibcon#first serial, iclass 33, count 0 2006.201.14:19:42.49#ibcon#enter sib2, iclass 33, count 0 2006.201.14:19:42.49#ibcon#flushed, iclass 33, count 0 2006.201.14:19:42.49#ibcon#about to write, iclass 33, count 0 2006.201.14:19:42.49#ibcon#wrote, iclass 33, count 0 2006.201.14:19:42.49#ibcon#about to read 3, iclass 33, count 0 2006.201.14:19:42.51#ibcon#read 3, iclass 33, count 0 2006.201.14:19:42.51#ibcon#about to read 4, iclass 33, count 0 2006.201.14:19:42.51#ibcon#read 4, iclass 33, count 0 2006.201.14:19:42.51#ibcon#about to read 5, iclass 33, count 0 2006.201.14:19:42.51#ibcon#read 5, iclass 33, count 0 2006.201.14:19:42.51#ibcon#about to read 6, iclass 33, count 0 2006.201.14:19:42.51#ibcon#read 6, iclass 33, count 0 2006.201.14:19:42.51#ibcon#end of sib2, iclass 33, count 0 2006.201.14:19:42.51#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:19:42.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:19:42.51#ibcon#[25=USB\r\n] 2006.201.14:19:42.51#ibcon#*before write, iclass 33, count 0 2006.201.14:19:42.51#ibcon#enter sib2, iclass 33, count 0 2006.201.14:19:42.51#ibcon#flushed, iclass 33, count 0 2006.201.14:19:42.51#ibcon#about to write, iclass 33, count 0 2006.201.14:19:42.51#ibcon#wrote, iclass 33, count 0 2006.201.14:19:42.51#ibcon#about to read 3, iclass 33, count 0 2006.201.14:19:42.54#ibcon#read 3, iclass 33, count 0 2006.201.14:19:42.54#ibcon#about to read 4, iclass 33, count 0 2006.201.14:19:42.54#ibcon#read 4, iclass 33, count 0 2006.201.14:19:42.54#ibcon#about to read 5, iclass 33, count 0 2006.201.14:19:42.54#ibcon#read 5, iclass 33, count 0 2006.201.14:19:42.54#ibcon#about to read 6, iclass 33, count 0 2006.201.14:19:42.54#ibcon#read 6, iclass 33, count 0 2006.201.14:19:42.54#ibcon#end of sib2, iclass 33, count 0 2006.201.14:19:42.54#ibcon#*after write, iclass 33, count 0 2006.201.14:19:42.54#ibcon#*before return 0, iclass 33, count 0 2006.201.14:19:42.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:42.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:42.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:19:42.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:19:42.54$vck44/vblo=1,629.99 2006.201.14:19:42.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.14:19:42.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.14:19:42.54#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:42.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:42.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:42.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:42.54#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:19:42.54#ibcon#first serial, iclass 35, count 0 2006.201.14:19:42.54#ibcon#enter sib2, iclass 35, count 0 2006.201.14:19:42.54#ibcon#flushed, iclass 35, count 0 2006.201.14:19:42.54#ibcon#about to write, iclass 35, count 0 2006.201.14:19:42.54#ibcon#wrote, iclass 35, count 0 2006.201.14:19:42.54#ibcon#about to read 3, iclass 35, count 0 2006.201.14:19:42.56#ibcon#read 3, iclass 35, count 0 2006.201.14:19:42.56#ibcon#about to read 4, iclass 35, count 0 2006.201.14:19:42.56#ibcon#read 4, iclass 35, count 0 2006.201.14:19:42.56#ibcon#about to read 5, iclass 35, count 0 2006.201.14:19:42.56#ibcon#read 5, iclass 35, count 0 2006.201.14:19:42.56#ibcon#about to read 6, iclass 35, count 0 2006.201.14:19:42.56#ibcon#read 6, iclass 35, count 0 2006.201.14:19:42.56#ibcon#end of sib2, iclass 35, count 0 2006.201.14:19:42.56#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:19:42.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:19:42.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:19:42.56#ibcon#*before write, iclass 35, count 0 2006.201.14:19:42.56#ibcon#enter sib2, iclass 35, count 0 2006.201.14:19:42.56#ibcon#flushed, iclass 35, count 0 2006.201.14:19:42.56#ibcon#about to write, iclass 35, count 0 2006.201.14:19:42.56#ibcon#wrote, iclass 35, count 0 2006.201.14:19:42.56#ibcon#about to read 3, iclass 35, count 0 2006.201.14:19:42.60#ibcon#read 3, iclass 35, count 0 2006.201.14:19:42.60#ibcon#about to read 4, iclass 35, count 0 2006.201.14:19:42.60#ibcon#read 4, iclass 35, count 0 2006.201.14:19:42.60#ibcon#about to read 5, iclass 35, count 0 2006.201.14:19:42.60#ibcon#read 5, iclass 35, count 0 2006.201.14:19:42.60#ibcon#about to read 6, iclass 35, count 0 2006.201.14:19:42.60#ibcon#read 6, iclass 35, count 0 2006.201.14:19:42.60#ibcon#end of sib2, iclass 35, count 0 2006.201.14:19:42.60#ibcon#*after write, iclass 35, count 0 2006.201.14:19:42.60#ibcon#*before return 0, iclass 35, count 0 2006.201.14:19:42.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:42.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:42.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:19:42.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:19:42.60$vck44/vb=1,4 2006.201.14:19:42.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.14:19:42.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.14:19:42.60#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:42.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:19:42.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:19:42.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:19:42.60#ibcon#enter wrdev, iclass 37, count 2 2006.201.14:19:42.60#ibcon#first serial, iclass 37, count 2 2006.201.14:19:42.60#ibcon#enter sib2, iclass 37, count 2 2006.201.14:19:42.60#ibcon#flushed, iclass 37, count 2 2006.201.14:19:42.60#ibcon#about to write, iclass 37, count 2 2006.201.14:19:42.60#ibcon#wrote, iclass 37, count 2 2006.201.14:19:42.60#ibcon#about to read 3, iclass 37, count 2 2006.201.14:19:42.62#ibcon#read 3, iclass 37, count 2 2006.201.14:19:42.62#ibcon#about to read 4, iclass 37, count 2 2006.201.14:19:42.62#ibcon#read 4, iclass 37, count 2 2006.201.14:19:42.62#ibcon#about to read 5, iclass 37, count 2 2006.201.14:19:42.62#ibcon#read 5, iclass 37, count 2 2006.201.14:19:42.62#ibcon#about to read 6, iclass 37, count 2 2006.201.14:19:42.62#ibcon#read 6, iclass 37, count 2 2006.201.14:19:42.62#ibcon#end of sib2, iclass 37, count 2 2006.201.14:19:42.62#ibcon#*mode == 0, iclass 37, count 2 2006.201.14:19:42.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.14:19:42.62#ibcon#[27=AT01-04\r\n] 2006.201.14:19:42.62#ibcon#*before write, iclass 37, count 2 2006.201.14:19:42.62#ibcon#enter sib2, iclass 37, count 2 2006.201.14:19:42.62#ibcon#flushed, iclass 37, count 2 2006.201.14:19:42.62#ibcon#about to write, iclass 37, count 2 2006.201.14:19:42.62#ibcon#wrote, iclass 37, count 2 2006.201.14:19:42.62#ibcon#about to read 3, iclass 37, count 2 2006.201.14:19:42.65#ibcon#read 3, iclass 37, count 2 2006.201.14:19:42.65#ibcon#about to read 4, iclass 37, count 2 2006.201.14:19:42.65#ibcon#read 4, iclass 37, count 2 2006.201.14:19:42.65#ibcon#about to read 5, iclass 37, count 2 2006.201.14:19:42.65#ibcon#read 5, iclass 37, count 2 2006.201.14:19:42.65#ibcon#about to read 6, iclass 37, count 2 2006.201.14:19:42.65#ibcon#read 6, iclass 37, count 2 2006.201.14:19:42.65#ibcon#end of sib2, iclass 37, count 2 2006.201.14:19:42.65#ibcon#*after write, iclass 37, count 2 2006.201.14:19:42.65#ibcon#*before return 0, iclass 37, count 2 2006.201.14:19:42.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:19:42.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:19:42.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.14:19:42.65#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:42.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:19:42.67#abcon#<5=/05 1.7 2.8 20.831001003.5\r\n> 2006.201.14:19:42.69#abcon#{5=INTERFACE CLEAR} 2006.201.14:19:42.75#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:19:42.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:19:42.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:19:42.77#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:19:42.77#ibcon#first serial, iclass 37, count 0 2006.201.14:19:42.77#ibcon#enter sib2, iclass 37, count 0 2006.201.14:19:42.77#ibcon#flushed, iclass 37, count 0 2006.201.14:19:42.77#ibcon#about to write, iclass 37, count 0 2006.201.14:19:42.77#ibcon#wrote, iclass 37, count 0 2006.201.14:19:42.77#ibcon#about to read 3, iclass 37, count 0 2006.201.14:19:42.79#ibcon#read 3, iclass 37, count 0 2006.201.14:19:42.79#ibcon#about to read 4, iclass 37, count 0 2006.201.14:19:42.79#ibcon#read 4, iclass 37, count 0 2006.201.14:19:42.79#ibcon#about to read 5, iclass 37, count 0 2006.201.14:19:42.79#ibcon#read 5, iclass 37, count 0 2006.201.14:19:42.79#ibcon#about to read 6, iclass 37, count 0 2006.201.14:19:42.79#ibcon#read 6, iclass 37, count 0 2006.201.14:19:42.79#ibcon#end of sib2, iclass 37, count 0 2006.201.14:19:42.79#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:19:42.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:19:42.79#ibcon#[27=USB\r\n] 2006.201.14:19:42.79#ibcon#*before write, iclass 37, count 0 2006.201.14:19:42.79#ibcon#enter sib2, iclass 37, count 0 2006.201.14:19:42.79#ibcon#flushed, iclass 37, count 0 2006.201.14:19:42.79#ibcon#about to write, iclass 37, count 0 2006.201.14:19:42.79#ibcon#wrote, iclass 37, count 0 2006.201.14:19:42.79#ibcon#about to read 3, iclass 37, count 0 2006.201.14:19:42.82#ibcon#read 3, iclass 37, count 0 2006.201.14:19:42.82#ibcon#about to read 4, iclass 37, count 0 2006.201.14:19:42.82#ibcon#read 4, iclass 37, count 0 2006.201.14:19:42.82#ibcon#about to read 5, iclass 37, count 0 2006.201.14:19:42.82#ibcon#read 5, iclass 37, count 0 2006.201.14:19:42.82#ibcon#about to read 6, iclass 37, count 0 2006.201.14:19:42.82#ibcon#read 6, iclass 37, count 0 2006.201.14:19:42.82#ibcon#end of sib2, iclass 37, count 0 2006.201.14:19:42.82#ibcon#*after write, iclass 37, count 0 2006.201.14:19:42.82#ibcon#*before return 0, iclass 37, count 0 2006.201.14:19:42.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:19:42.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:19:42.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:19:42.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:19:42.82$vck44/vblo=2,634.99 2006.201.14:19:42.82#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.14:19:42.82#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.14:19:42.82#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:42.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:42.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:42.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:42.82#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:19:42.82#ibcon#first serial, iclass 5, count 0 2006.201.14:19:42.82#ibcon#enter sib2, iclass 5, count 0 2006.201.14:19:42.82#ibcon#flushed, iclass 5, count 0 2006.201.14:19:42.82#ibcon#about to write, iclass 5, count 0 2006.201.14:19:42.82#ibcon#wrote, iclass 5, count 0 2006.201.14:19:42.82#ibcon#about to read 3, iclass 5, count 0 2006.201.14:19:42.84#ibcon#read 3, iclass 5, count 0 2006.201.14:19:42.84#ibcon#about to read 4, iclass 5, count 0 2006.201.14:19:42.84#ibcon#read 4, iclass 5, count 0 2006.201.14:19:42.84#ibcon#about to read 5, iclass 5, count 0 2006.201.14:19:42.84#ibcon#read 5, iclass 5, count 0 2006.201.14:19:42.84#ibcon#about to read 6, iclass 5, count 0 2006.201.14:19:42.84#ibcon#read 6, iclass 5, count 0 2006.201.14:19:42.84#ibcon#end of sib2, iclass 5, count 0 2006.201.14:19:42.84#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:19:42.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:19:42.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:19:42.84#ibcon#*before write, iclass 5, count 0 2006.201.14:19:42.84#ibcon#enter sib2, iclass 5, count 0 2006.201.14:19:42.84#ibcon#flushed, iclass 5, count 0 2006.201.14:19:42.84#ibcon#about to write, iclass 5, count 0 2006.201.14:19:42.84#ibcon#wrote, iclass 5, count 0 2006.201.14:19:42.84#ibcon#about to read 3, iclass 5, count 0 2006.201.14:19:42.88#ibcon#read 3, iclass 5, count 0 2006.201.14:19:42.88#ibcon#about to read 4, iclass 5, count 0 2006.201.14:19:42.88#ibcon#read 4, iclass 5, count 0 2006.201.14:19:42.88#ibcon#about to read 5, iclass 5, count 0 2006.201.14:19:42.88#ibcon#read 5, iclass 5, count 0 2006.201.14:19:42.88#ibcon#about to read 6, iclass 5, count 0 2006.201.14:19:42.88#ibcon#read 6, iclass 5, count 0 2006.201.14:19:42.88#ibcon#end of sib2, iclass 5, count 0 2006.201.14:19:42.88#ibcon#*after write, iclass 5, count 0 2006.201.14:19:42.88#ibcon#*before return 0, iclass 5, count 0 2006.201.14:19:42.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:42.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:19:42.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:19:42.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:19:42.88$vck44/vb=2,5 2006.201.14:19:42.88#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.14:19:42.88#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.14:19:42.88#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:42.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:42.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:42.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:42.94#ibcon#enter wrdev, iclass 7, count 2 2006.201.14:19:42.94#ibcon#first serial, iclass 7, count 2 2006.201.14:19:42.94#ibcon#enter sib2, iclass 7, count 2 2006.201.14:19:42.94#ibcon#flushed, iclass 7, count 2 2006.201.14:19:42.94#ibcon#about to write, iclass 7, count 2 2006.201.14:19:42.94#ibcon#wrote, iclass 7, count 2 2006.201.14:19:42.94#ibcon#about to read 3, iclass 7, count 2 2006.201.14:19:42.96#ibcon#read 3, iclass 7, count 2 2006.201.14:19:42.96#ibcon#about to read 4, iclass 7, count 2 2006.201.14:19:42.96#ibcon#read 4, iclass 7, count 2 2006.201.14:19:42.96#ibcon#about to read 5, iclass 7, count 2 2006.201.14:19:42.96#ibcon#read 5, iclass 7, count 2 2006.201.14:19:42.96#ibcon#about to read 6, iclass 7, count 2 2006.201.14:19:42.96#ibcon#read 6, iclass 7, count 2 2006.201.14:19:42.96#ibcon#end of sib2, iclass 7, count 2 2006.201.14:19:42.96#ibcon#*mode == 0, iclass 7, count 2 2006.201.14:19:42.96#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.14:19:42.96#ibcon#[27=AT02-05\r\n] 2006.201.14:19:42.96#ibcon#*before write, iclass 7, count 2 2006.201.14:19:42.96#ibcon#enter sib2, iclass 7, count 2 2006.201.14:19:42.96#ibcon#flushed, iclass 7, count 2 2006.201.14:19:42.96#ibcon#about to write, iclass 7, count 2 2006.201.14:19:42.96#ibcon#wrote, iclass 7, count 2 2006.201.14:19:42.96#ibcon#about to read 3, iclass 7, count 2 2006.201.14:19:42.99#ibcon#read 3, iclass 7, count 2 2006.201.14:19:42.99#ibcon#about to read 4, iclass 7, count 2 2006.201.14:19:42.99#ibcon#read 4, iclass 7, count 2 2006.201.14:19:42.99#ibcon#about to read 5, iclass 7, count 2 2006.201.14:19:42.99#ibcon#read 5, iclass 7, count 2 2006.201.14:19:42.99#ibcon#about to read 6, iclass 7, count 2 2006.201.14:19:42.99#ibcon#read 6, iclass 7, count 2 2006.201.14:19:42.99#ibcon#end of sib2, iclass 7, count 2 2006.201.14:19:42.99#ibcon#*after write, iclass 7, count 2 2006.201.14:19:42.99#ibcon#*before return 0, iclass 7, count 2 2006.201.14:19:42.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:42.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:19:42.99#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.14:19:42.99#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:42.99#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:43.11#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:43.11#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:43.11#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:19:43.11#ibcon#first serial, iclass 7, count 0 2006.201.14:19:43.11#ibcon#enter sib2, iclass 7, count 0 2006.201.14:19:43.11#ibcon#flushed, iclass 7, count 0 2006.201.14:19:43.11#ibcon#about to write, iclass 7, count 0 2006.201.14:19:43.11#ibcon#wrote, iclass 7, count 0 2006.201.14:19:43.11#ibcon#about to read 3, iclass 7, count 0 2006.201.14:19:43.13#ibcon#read 3, iclass 7, count 0 2006.201.14:19:43.13#ibcon#about to read 4, iclass 7, count 0 2006.201.14:19:43.13#ibcon#read 4, iclass 7, count 0 2006.201.14:19:43.13#ibcon#about to read 5, iclass 7, count 0 2006.201.14:19:43.13#ibcon#read 5, iclass 7, count 0 2006.201.14:19:43.13#ibcon#about to read 6, iclass 7, count 0 2006.201.14:19:43.13#ibcon#read 6, iclass 7, count 0 2006.201.14:19:43.13#ibcon#end of sib2, iclass 7, count 0 2006.201.14:19:43.13#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:19:43.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:19:43.13#ibcon#[27=USB\r\n] 2006.201.14:19:43.13#ibcon#*before write, iclass 7, count 0 2006.201.14:19:43.13#ibcon#enter sib2, iclass 7, count 0 2006.201.14:19:43.13#ibcon#flushed, iclass 7, count 0 2006.201.14:19:43.13#ibcon#about to write, iclass 7, count 0 2006.201.14:19:43.13#ibcon#wrote, iclass 7, count 0 2006.201.14:19:43.13#ibcon#about to read 3, iclass 7, count 0 2006.201.14:19:43.16#ibcon#read 3, iclass 7, count 0 2006.201.14:19:43.16#ibcon#about to read 4, iclass 7, count 0 2006.201.14:19:43.16#ibcon#read 4, iclass 7, count 0 2006.201.14:19:43.16#ibcon#about to read 5, iclass 7, count 0 2006.201.14:19:43.16#ibcon#read 5, iclass 7, count 0 2006.201.14:19:43.16#ibcon#about to read 6, iclass 7, count 0 2006.201.14:19:43.16#ibcon#read 6, iclass 7, count 0 2006.201.14:19:43.16#ibcon#end of sib2, iclass 7, count 0 2006.201.14:19:43.16#ibcon#*after write, iclass 7, count 0 2006.201.14:19:43.16#ibcon#*before return 0, iclass 7, count 0 2006.201.14:19:43.16#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:43.16#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:19:43.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:19:43.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:19:43.16$vck44/vblo=3,649.99 2006.201.14:19:43.16#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.14:19:43.16#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.14:19:43.16#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:43.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:43.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:43.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:43.16#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:19:43.16#ibcon#first serial, iclass 11, count 0 2006.201.14:19:43.16#ibcon#enter sib2, iclass 11, count 0 2006.201.14:19:43.16#ibcon#flushed, iclass 11, count 0 2006.201.14:19:43.16#ibcon#about to write, iclass 11, count 0 2006.201.14:19:43.16#ibcon#wrote, iclass 11, count 0 2006.201.14:19:43.16#ibcon#about to read 3, iclass 11, count 0 2006.201.14:19:43.18#ibcon#read 3, iclass 11, count 0 2006.201.14:19:43.18#ibcon#about to read 4, iclass 11, count 0 2006.201.14:19:43.18#ibcon#read 4, iclass 11, count 0 2006.201.14:19:43.18#ibcon#about to read 5, iclass 11, count 0 2006.201.14:19:43.18#ibcon#read 5, iclass 11, count 0 2006.201.14:19:43.18#ibcon#about to read 6, iclass 11, count 0 2006.201.14:19:43.18#ibcon#read 6, iclass 11, count 0 2006.201.14:19:43.18#ibcon#end of sib2, iclass 11, count 0 2006.201.14:19:43.18#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:19:43.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:19:43.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:19:43.18#ibcon#*before write, iclass 11, count 0 2006.201.14:19:43.18#ibcon#enter sib2, iclass 11, count 0 2006.201.14:19:43.18#ibcon#flushed, iclass 11, count 0 2006.201.14:19:43.18#ibcon#about to write, iclass 11, count 0 2006.201.14:19:43.18#ibcon#wrote, iclass 11, count 0 2006.201.14:19:43.18#ibcon#about to read 3, iclass 11, count 0 2006.201.14:19:43.22#ibcon#read 3, iclass 11, count 0 2006.201.14:19:43.22#ibcon#about to read 4, iclass 11, count 0 2006.201.14:19:43.22#ibcon#read 4, iclass 11, count 0 2006.201.14:19:43.22#ibcon#about to read 5, iclass 11, count 0 2006.201.14:19:43.22#ibcon#read 5, iclass 11, count 0 2006.201.14:19:43.22#ibcon#about to read 6, iclass 11, count 0 2006.201.14:19:43.22#ibcon#read 6, iclass 11, count 0 2006.201.14:19:43.22#ibcon#end of sib2, iclass 11, count 0 2006.201.14:19:43.22#ibcon#*after write, iclass 11, count 0 2006.201.14:19:43.22#ibcon#*before return 0, iclass 11, count 0 2006.201.14:19:43.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:43.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:19:43.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:19:43.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:19:43.22$vck44/vb=3,4 2006.201.14:19:43.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.14:19:43.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.14:19:43.22#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:43.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:43.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:43.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:43.28#ibcon#enter wrdev, iclass 13, count 2 2006.201.14:19:43.28#ibcon#first serial, iclass 13, count 2 2006.201.14:19:43.28#ibcon#enter sib2, iclass 13, count 2 2006.201.14:19:43.28#ibcon#flushed, iclass 13, count 2 2006.201.14:19:43.28#ibcon#about to write, iclass 13, count 2 2006.201.14:19:43.28#ibcon#wrote, iclass 13, count 2 2006.201.14:19:43.28#ibcon#about to read 3, iclass 13, count 2 2006.201.14:19:43.30#ibcon#read 3, iclass 13, count 2 2006.201.14:19:43.30#ibcon#about to read 4, iclass 13, count 2 2006.201.14:19:43.30#ibcon#read 4, iclass 13, count 2 2006.201.14:19:43.30#ibcon#about to read 5, iclass 13, count 2 2006.201.14:19:43.30#ibcon#read 5, iclass 13, count 2 2006.201.14:19:43.30#ibcon#about to read 6, iclass 13, count 2 2006.201.14:19:43.30#ibcon#read 6, iclass 13, count 2 2006.201.14:19:43.30#ibcon#end of sib2, iclass 13, count 2 2006.201.14:19:43.30#ibcon#*mode == 0, iclass 13, count 2 2006.201.14:19:43.30#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.14:19:43.30#ibcon#[27=AT03-04\r\n] 2006.201.14:19:43.30#ibcon#*before write, iclass 13, count 2 2006.201.14:19:43.30#ibcon#enter sib2, iclass 13, count 2 2006.201.14:19:43.30#ibcon#flushed, iclass 13, count 2 2006.201.14:19:43.30#ibcon#about to write, iclass 13, count 2 2006.201.14:19:43.30#ibcon#wrote, iclass 13, count 2 2006.201.14:19:43.30#ibcon#about to read 3, iclass 13, count 2 2006.201.14:19:43.33#ibcon#read 3, iclass 13, count 2 2006.201.14:19:43.33#ibcon#about to read 4, iclass 13, count 2 2006.201.14:19:43.33#ibcon#read 4, iclass 13, count 2 2006.201.14:19:43.33#ibcon#about to read 5, iclass 13, count 2 2006.201.14:19:43.33#ibcon#read 5, iclass 13, count 2 2006.201.14:19:43.33#ibcon#about to read 6, iclass 13, count 2 2006.201.14:19:43.33#ibcon#read 6, iclass 13, count 2 2006.201.14:19:43.33#ibcon#end of sib2, iclass 13, count 2 2006.201.14:19:43.33#ibcon#*after write, iclass 13, count 2 2006.201.14:19:43.33#ibcon#*before return 0, iclass 13, count 2 2006.201.14:19:43.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:43.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:19:43.33#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.14:19:43.33#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:43.33#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:43.45#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:43.45#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:43.45#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:19:43.45#ibcon#first serial, iclass 13, count 0 2006.201.14:19:43.45#ibcon#enter sib2, iclass 13, count 0 2006.201.14:19:43.45#ibcon#flushed, iclass 13, count 0 2006.201.14:19:43.45#ibcon#about to write, iclass 13, count 0 2006.201.14:19:43.45#ibcon#wrote, iclass 13, count 0 2006.201.14:19:43.45#ibcon#about to read 3, iclass 13, count 0 2006.201.14:19:43.47#ibcon#read 3, iclass 13, count 0 2006.201.14:19:43.47#ibcon#about to read 4, iclass 13, count 0 2006.201.14:19:43.47#ibcon#read 4, iclass 13, count 0 2006.201.14:19:43.47#ibcon#about to read 5, iclass 13, count 0 2006.201.14:19:43.47#ibcon#read 5, iclass 13, count 0 2006.201.14:19:43.47#ibcon#about to read 6, iclass 13, count 0 2006.201.14:19:43.47#ibcon#read 6, iclass 13, count 0 2006.201.14:19:43.47#ibcon#end of sib2, iclass 13, count 0 2006.201.14:19:43.47#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:19:43.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:19:43.47#ibcon#[27=USB\r\n] 2006.201.14:19:43.47#ibcon#*before write, iclass 13, count 0 2006.201.14:19:43.47#ibcon#enter sib2, iclass 13, count 0 2006.201.14:19:43.47#ibcon#flushed, iclass 13, count 0 2006.201.14:19:43.47#ibcon#about to write, iclass 13, count 0 2006.201.14:19:43.47#ibcon#wrote, iclass 13, count 0 2006.201.14:19:43.47#ibcon#about to read 3, iclass 13, count 0 2006.201.14:19:43.50#ibcon#read 3, iclass 13, count 0 2006.201.14:19:43.50#ibcon#about to read 4, iclass 13, count 0 2006.201.14:19:43.50#ibcon#read 4, iclass 13, count 0 2006.201.14:19:43.50#ibcon#about to read 5, iclass 13, count 0 2006.201.14:19:43.50#ibcon#read 5, iclass 13, count 0 2006.201.14:19:43.50#ibcon#about to read 6, iclass 13, count 0 2006.201.14:19:43.50#ibcon#read 6, iclass 13, count 0 2006.201.14:19:43.50#ibcon#end of sib2, iclass 13, count 0 2006.201.14:19:43.50#ibcon#*after write, iclass 13, count 0 2006.201.14:19:43.50#ibcon#*before return 0, iclass 13, count 0 2006.201.14:19:43.50#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:43.50#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:19:43.50#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:19:43.50#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:19:43.50$vck44/vblo=4,679.99 2006.201.14:19:43.50#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.14:19:43.50#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.14:19:43.50#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:43.50#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:43.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:43.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:43.50#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:19:43.50#ibcon#first serial, iclass 15, count 0 2006.201.14:19:43.50#ibcon#enter sib2, iclass 15, count 0 2006.201.14:19:43.50#ibcon#flushed, iclass 15, count 0 2006.201.14:19:43.50#ibcon#about to write, iclass 15, count 0 2006.201.14:19:43.50#ibcon#wrote, iclass 15, count 0 2006.201.14:19:43.50#ibcon#about to read 3, iclass 15, count 0 2006.201.14:19:43.52#ibcon#read 3, iclass 15, count 0 2006.201.14:19:43.52#ibcon#about to read 4, iclass 15, count 0 2006.201.14:19:43.52#ibcon#read 4, iclass 15, count 0 2006.201.14:19:43.52#ibcon#about to read 5, iclass 15, count 0 2006.201.14:19:43.52#ibcon#read 5, iclass 15, count 0 2006.201.14:19:43.52#ibcon#about to read 6, iclass 15, count 0 2006.201.14:19:43.52#ibcon#read 6, iclass 15, count 0 2006.201.14:19:43.52#ibcon#end of sib2, iclass 15, count 0 2006.201.14:19:43.52#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:19:43.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:19:43.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:19:43.52#ibcon#*before write, iclass 15, count 0 2006.201.14:19:43.52#ibcon#enter sib2, iclass 15, count 0 2006.201.14:19:43.52#ibcon#flushed, iclass 15, count 0 2006.201.14:19:43.52#ibcon#about to write, iclass 15, count 0 2006.201.14:19:43.52#ibcon#wrote, iclass 15, count 0 2006.201.14:19:43.52#ibcon#about to read 3, iclass 15, count 0 2006.201.14:19:43.56#ibcon#read 3, iclass 15, count 0 2006.201.14:19:43.56#ibcon#about to read 4, iclass 15, count 0 2006.201.14:19:43.56#ibcon#read 4, iclass 15, count 0 2006.201.14:19:43.56#ibcon#about to read 5, iclass 15, count 0 2006.201.14:19:43.56#ibcon#read 5, iclass 15, count 0 2006.201.14:19:43.56#ibcon#about to read 6, iclass 15, count 0 2006.201.14:19:43.56#ibcon#read 6, iclass 15, count 0 2006.201.14:19:43.56#ibcon#end of sib2, iclass 15, count 0 2006.201.14:19:43.56#ibcon#*after write, iclass 15, count 0 2006.201.14:19:43.56#ibcon#*before return 0, iclass 15, count 0 2006.201.14:19:43.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:43.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:19:43.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:19:43.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:19:43.56$vck44/vb=4,5 2006.201.14:19:43.56#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.14:19:43.56#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.14:19:43.56#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:43.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:43.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:43.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:43.62#ibcon#enter wrdev, iclass 17, count 2 2006.201.14:19:43.62#ibcon#first serial, iclass 17, count 2 2006.201.14:19:43.62#ibcon#enter sib2, iclass 17, count 2 2006.201.14:19:43.62#ibcon#flushed, iclass 17, count 2 2006.201.14:19:43.62#ibcon#about to write, iclass 17, count 2 2006.201.14:19:43.62#ibcon#wrote, iclass 17, count 2 2006.201.14:19:43.62#ibcon#about to read 3, iclass 17, count 2 2006.201.14:19:43.64#ibcon#read 3, iclass 17, count 2 2006.201.14:19:43.64#ibcon#about to read 4, iclass 17, count 2 2006.201.14:19:43.64#ibcon#read 4, iclass 17, count 2 2006.201.14:19:43.64#ibcon#about to read 5, iclass 17, count 2 2006.201.14:19:43.64#ibcon#read 5, iclass 17, count 2 2006.201.14:19:43.64#ibcon#about to read 6, iclass 17, count 2 2006.201.14:19:43.64#ibcon#read 6, iclass 17, count 2 2006.201.14:19:43.64#ibcon#end of sib2, iclass 17, count 2 2006.201.14:19:43.64#ibcon#*mode == 0, iclass 17, count 2 2006.201.14:19:43.64#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.14:19:43.64#ibcon#[27=AT04-05\r\n] 2006.201.14:19:43.64#ibcon#*before write, iclass 17, count 2 2006.201.14:19:43.64#ibcon#enter sib2, iclass 17, count 2 2006.201.14:19:43.64#ibcon#flushed, iclass 17, count 2 2006.201.14:19:43.64#ibcon#about to write, iclass 17, count 2 2006.201.14:19:43.64#ibcon#wrote, iclass 17, count 2 2006.201.14:19:43.64#ibcon#about to read 3, iclass 17, count 2 2006.201.14:19:43.67#ibcon#read 3, iclass 17, count 2 2006.201.14:19:43.67#ibcon#about to read 4, iclass 17, count 2 2006.201.14:19:43.67#ibcon#read 4, iclass 17, count 2 2006.201.14:19:43.67#ibcon#about to read 5, iclass 17, count 2 2006.201.14:19:43.67#ibcon#read 5, iclass 17, count 2 2006.201.14:19:43.67#ibcon#about to read 6, iclass 17, count 2 2006.201.14:19:43.67#ibcon#read 6, iclass 17, count 2 2006.201.14:19:43.67#ibcon#end of sib2, iclass 17, count 2 2006.201.14:19:43.67#ibcon#*after write, iclass 17, count 2 2006.201.14:19:43.67#ibcon#*before return 0, iclass 17, count 2 2006.201.14:19:43.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:43.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:19:43.67#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.14:19:43.67#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:43.67#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:43.79#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:43.79#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:43.79#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:19:43.79#ibcon#first serial, iclass 17, count 0 2006.201.14:19:43.79#ibcon#enter sib2, iclass 17, count 0 2006.201.14:19:43.79#ibcon#flushed, iclass 17, count 0 2006.201.14:19:43.79#ibcon#about to write, iclass 17, count 0 2006.201.14:19:43.79#ibcon#wrote, iclass 17, count 0 2006.201.14:19:43.79#ibcon#about to read 3, iclass 17, count 0 2006.201.14:19:43.81#ibcon#read 3, iclass 17, count 0 2006.201.14:19:43.81#ibcon#about to read 4, iclass 17, count 0 2006.201.14:19:43.81#ibcon#read 4, iclass 17, count 0 2006.201.14:19:43.81#ibcon#about to read 5, iclass 17, count 0 2006.201.14:19:43.81#ibcon#read 5, iclass 17, count 0 2006.201.14:19:43.81#ibcon#about to read 6, iclass 17, count 0 2006.201.14:19:43.81#ibcon#read 6, iclass 17, count 0 2006.201.14:19:43.81#ibcon#end of sib2, iclass 17, count 0 2006.201.14:19:43.81#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:19:43.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:19:43.81#ibcon#[27=USB\r\n] 2006.201.14:19:43.81#ibcon#*before write, iclass 17, count 0 2006.201.14:19:43.81#ibcon#enter sib2, iclass 17, count 0 2006.201.14:19:43.81#ibcon#flushed, iclass 17, count 0 2006.201.14:19:43.81#ibcon#about to write, iclass 17, count 0 2006.201.14:19:43.81#ibcon#wrote, iclass 17, count 0 2006.201.14:19:43.81#ibcon#about to read 3, iclass 17, count 0 2006.201.14:19:43.84#ibcon#read 3, iclass 17, count 0 2006.201.14:19:43.84#ibcon#about to read 4, iclass 17, count 0 2006.201.14:19:43.84#ibcon#read 4, iclass 17, count 0 2006.201.14:19:43.84#ibcon#about to read 5, iclass 17, count 0 2006.201.14:19:43.84#ibcon#read 5, iclass 17, count 0 2006.201.14:19:43.84#ibcon#about to read 6, iclass 17, count 0 2006.201.14:19:43.84#ibcon#read 6, iclass 17, count 0 2006.201.14:19:43.84#ibcon#end of sib2, iclass 17, count 0 2006.201.14:19:43.84#ibcon#*after write, iclass 17, count 0 2006.201.14:19:43.84#ibcon#*before return 0, iclass 17, count 0 2006.201.14:19:43.84#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:43.84#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:19:43.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:19:43.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:19:43.84$vck44/vblo=5,709.99 2006.201.14:19:43.84#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.14:19:43.84#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.14:19:43.84#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:43.84#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:43.84#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:43.84#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:43.84#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:19:43.84#ibcon#first serial, iclass 19, count 0 2006.201.14:19:43.84#ibcon#enter sib2, iclass 19, count 0 2006.201.14:19:43.84#ibcon#flushed, iclass 19, count 0 2006.201.14:19:43.84#ibcon#about to write, iclass 19, count 0 2006.201.14:19:43.84#ibcon#wrote, iclass 19, count 0 2006.201.14:19:43.84#ibcon#about to read 3, iclass 19, count 0 2006.201.14:19:43.86#ibcon#read 3, iclass 19, count 0 2006.201.14:19:43.86#ibcon#about to read 4, iclass 19, count 0 2006.201.14:19:43.86#ibcon#read 4, iclass 19, count 0 2006.201.14:19:43.86#ibcon#about to read 5, iclass 19, count 0 2006.201.14:19:43.86#ibcon#read 5, iclass 19, count 0 2006.201.14:19:43.86#ibcon#about to read 6, iclass 19, count 0 2006.201.14:19:43.86#ibcon#read 6, iclass 19, count 0 2006.201.14:19:43.86#ibcon#end of sib2, iclass 19, count 0 2006.201.14:19:43.86#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:19:43.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:19:43.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:19:43.86#ibcon#*before write, iclass 19, count 0 2006.201.14:19:43.86#ibcon#enter sib2, iclass 19, count 0 2006.201.14:19:43.86#ibcon#flushed, iclass 19, count 0 2006.201.14:19:43.86#ibcon#about to write, iclass 19, count 0 2006.201.14:19:43.86#ibcon#wrote, iclass 19, count 0 2006.201.14:19:43.86#ibcon#about to read 3, iclass 19, count 0 2006.201.14:19:43.91#ibcon#read 3, iclass 19, count 0 2006.201.14:19:43.91#ibcon#about to read 4, iclass 19, count 0 2006.201.14:19:43.91#ibcon#read 4, iclass 19, count 0 2006.201.14:19:43.91#ibcon#about to read 5, iclass 19, count 0 2006.201.14:19:43.91#ibcon#read 5, iclass 19, count 0 2006.201.14:19:43.91#ibcon#about to read 6, iclass 19, count 0 2006.201.14:19:43.91#ibcon#read 6, iclass 19, count 0 2006.201.14:19:43.91#ibcon#end of sib2, iclass 19, count 0 2006.201.14:19:43.91#ibcon#*after write, iclass 19, count 0 2006.201.14:19:43.91#ibcon#*before return 0, iclass 19, count 0 2006.201.14:19:43.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:43.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:19:43.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:19:43.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:19:43.91$vck44/vb=5,4 2006.201.14:19:43.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.14:19:43.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.14:19:43.91#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:43.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:43.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:43.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:43.96#ibcon#enter wrdev, iclass 21, count 2 2006.201.14:19:43.96#ibcon#first serial, iclass 21, count 2 2006.201.14:19:43.96#ibcon#enter sib2, iclass 21, count 2 2006.201.14:19:43.96#ibcon#flushed, iclass 21, count 2 2006.201.14:19:43.96#ibcon#about to write, iclass 21, count 2 2006.201.14:19:43.96#ibcon#wrote, iclass 21, count 2 2006.201.14:19:43.96#ibcon#about to read 3, iclass 21, count 2 2006.201.14:19:43.98#ibcon#read 3, iclass 21, count 2 2006.201.14:19:43.98#ibcon#about to read 4, iclass 21, count 2 2006.201.14:19:43.98#ibcon#read 4, iclass 21, count 2 2006.201.14:19:43.98#ibcon#about to read 5, iclass 21, count 2 2006.201.14:19:43.98#ibcon#read 5, iclass 21, count 2 2006.201.14:19:43.98#ibcon#about to read 6, iclass 21, count 2 2006.201.14:19:43.98#ibcon#read 6, iclass 21, count 2 2006.201.14:19:43.98#ibcon#end of sib2, iclass 21, count 2 2006.201.14:19:43.98#ibcon#*mode == 0, iclass 21, count 2 2006.201.14:19:43.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.14:19:43.98#ibcon#[27=AT05-04\r\n] 2006.201.14:19:43.98#ibcon#*before write, iclass 21, count 2 2006.201.14:19:43.98#ibcon#enter sib2, iclass 21, count 2 2006.201.14:19:43.98#ibcon#flushed, iclass 21, count 2 2006.201.14:19:43.98#ibcon#about to write, iclass 21, count 2 2006.201.14:19:43.98#ibcon#wrote, iclass 21, count 2 2006.201.14:19:43.98#ibcon#about to read 3, iclass 21, count 2 2006.201.14:19:44.01#ibcon#read 3, iclass 21, count 2 2006.201.14:19:44.01#ibcon#about to read 4, iclass 21, count 2 2006.201.14:19:44.01#ibcon#read 4, iclass 21, count 2 2006.201.14:19:44.01#ibcon#about to read 5, iclass 21, count 2 2006.201.14:19:44.01#ibcon#read 5, iclass 21, count 2 2006.201.14:19:44.01#ibcon#about to read 6, iclass 21, count 2 2006.201.14:19:44.01#ibcon#read 6, iclass 21, count 2 2006.201.14:19:44.01#ibcon#end of sib2, iclass 21, count 2 2006.201.14:19:44.01#ibcon#*after write, iclass 21, count 2 2006.201.14:19:44.01#ibcon#*before return 0, iclass 21, count 2 2006.201.14:19:44.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:44.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:19:44.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.14:19:44.01#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:44.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:44.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:44.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:44.13#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:19:44.13#ibcon#first serial, iclass 21, count 0 2006.201.14:19:44.13#ibcon#enter sib2, iclass 21, count 0 2006.201.14:19:44.13#ibcon#flushed, iclass 21, count 0 2006.201.14:19:44.13#ibcon#about to write, iclass 21, count 0 2006.201.14:19:44.13#ibcon#wrote, iclass 21, count 0 2006.201.14:19:44.13#ibcon#about to read 3, iclass 21, count 0 2006.201.14:19:44.15#ibcon#read 3, iclass 21, count 0 2006.201.14:19:44.15#ibcon#about to read 4, iclass 21, count 0 2006.201.14:19:44.15#ibcon#read 4, iclass 21, count 0 2006.201.14:19:44.15#ibcon#about to read 5, iclass 21, count 0 2006.201.14:19:44.15#ibcon#read 5, iclass 21, count 0 2006.201.14:19:44.15#ibcon#about to read 6, iclass 21, count 0 2006.201.14:19:44.15#ibcon#read 6, iclass 21, count 0 2006.201.14:19:44.15#ibcon#end of sib2, iclass 21, count 0 2006.201.14:19:44.15#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:19:44.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:19:44.15#ibcon#[27=USB\r\n] 2006.201.14:19:44.15#ibcon#*before write, iclass 21, count 0 2006.201.14:19:44.15#ibcon#enter sib2, iclass 21, count 0 2006.201.14:19:44.15#ibcon#flushed, iclass 21, count 0 2006.201.14:19:44.15#ibcon#about to write, iclass 21, count 0 2006.201.14:19:44.15#ibcon#wrote, iclass 21, count 0 2006.201.14:19:44.15#ibcon#about to read 3, iclass 21, count 0 2006.201.14:19:44.18#ibcon#read 3, iclass 21, count 0 2006.201.14:19:44.18#ibcon#about to read 4, iclass 21, count 0 2006.201.14:19:44.18#ibcon#read 4, iclass 21, count 0 2006.201.14:19:44.18#ibcon#about to read 5, iclass 21, count 0 2006.201.14:19:44.18#ibcon#read 5, iclass 21, count 0 2006.201.14:19:44.18#ibcon#about to read 6, iclass 21, count 0 2006.201.14:19:44.18#ibcon#read 6, iclass 21, count 0 2006.201.14:19:44.18#ibcon#end of sib2, iclass 21, count 0 2006.201.14:19:44.18#ibcon#*after write, iclass 21, count 0 2006.201.14:19:44.18#ibcon#*before return 0, iclass 21, count 0 2006.201.14:19:44.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:44.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:19:44.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:19:44.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:19:44.18$vck44/vblo=6,719.99 2006.201.14:19:44.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.14:19:44.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.14:19:44.18#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:44.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:44.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:44.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:44.18#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:19:44.18#ibcon#first serial, iclass 23, count 0 2006.201.14:19:44.18#ibcon#enter sib2, iclass 23, count 0 2006.201.14:19:44.18#ibcon#flushed, iclass 23, count 0 2006.201.14:19:44.18#ibcon#about to write, iclass 23, count 0 2006.201.14:19:44.18#ibcon#wrote, iclass 23, count 0 2006.201.14:19:44.18#ibcon#about to read 3, iclass 23, count 0 2006.201.14:19:44.20#ibcon#read 3, iclass 23, count 0 2006.201.14:19:44.20#ibcon#about to read 4, iclass 23, count 0 2006.201.14:19:44.20#ibcon#read 4, iclass 23, count 0 2006.201.14:19:44.20#ibcon#about to read 5, iclass 23, count 0 2006.201.14:19:44.20#ibcon#read 5, iclass 23, count 0 2006.201.14:19:44.20#ibcon#about to read 6, iclass 23, count 0 2006.201.14:19:44.20#ibcon#read 6, iclass 23, count 0 2006.201.14:19:44.20#ibcon#end of sib2, iclass 23, count 0 2006.201.14:19:44.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:19:44.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:19:44.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:19:44.20#ibcon#*before write, iclass 23, count 0 2006.201.14:19:44.20#ibcon#enter sib2, iclass 23, count 0 2006.201.14:19:44.20#ibcon#flushed, iclass 23, count 0 2006.201.14:19:44.20#ibcon#about to write, iclass 23, count 0 2006.201.14:19:44.20#ibcon#wrote, iclass 23, count 0 2006.201.14:19:44.20#ibcon#about to read 3, iclass 23, count 0 2006.201.14:19:44.24#ibcon#read 3, iclass 23, count 0 2006.201.14:19:44.24#ibcon#about to read 4, iclass 23, count 0 2006.201.14:19:44.24#ibcon#read 4, iclass 23, count 0 2006.201.14:19:44.24#ibcon#about to read 5, iclass 23, count 0 2006.201.14:19:44.24#ibcon#read 5, iclass 23, count 0 2006.201.14:19:44.24#ibcon#about to read 6, iclass 23, count 0 2006.201.14:19:44.24#ibcon#read 6, iclass 23, count 0 2006.201.14:19:44.24#ibcon#end of sib2, iclass 23, count 0 2006.201.14:19:44.24#ibcon#*after write, iclass 23, count 0 2006.201.14:19:44.24#ibcon#*before return 0, iclass 23, count 0 2006.201.14:19:44.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:44.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:19:44.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:19:44.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:19:44.24$vck44/vb=6,4 2006.201.14:19:44.24#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.14:19:44.24#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.14:19:44.24#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:44.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:44.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:44.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:44.30#ibcon#enter wrdev, iclass 25, count 2 2006.201.14:19:44.30#ibcon#first serial, iclass 25, count 2 2006.201.14:19:44.30#ibcon#enter sib2, iclass 25, count 2 2006.201.14:19:44.30#ibcon#flushed, iclass 25, count 2 2006.201.14:19:44.30#ibcon#about to write, iclass 25, count 2 2006.201.14:19:44.30#ibcon#wrote, iclass 25, count 2 2006.201.14:19:44.30#ibcon#about to read 3, iclass 25, count 2 2006.201.14:19:44.32#ibcon#read 3, iclass 25, count 2 2006.201.14:19:44.32#ibcon#about to read 4, iclass 25, count 2 2006.201.14:19:44.32#ibcon#read 4, iclass 25, count 2 2006.201.14:19:44.32#ibcon#about to read 5, iclass 25, count 2 2006.201.14:19:44.32#ibcon#read 5, iclass 25, count 2 2006.201.14:19:44.32#ibcon#about to read 6, iclass 25, count 2 2006.201.14:19:44.32#ibcon#read 6, iclass 25, count 2 2006.201.14:19:44.32#ibcon#end of sib2, iclass 25, count 2 2006.201.14:19:44.32#ibcon#*mode == 0, iclass 25, count 2 2006.201.14:19:44.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.14:19:44.32#ibcon#[27=AT06-04\r\n] 2006.201.14:19:44.32#ibcon#*before write, iclass 25, count 2 2006.201.14:19:44.32#ibcon#enter sib2, iclass 25, count 2 2006.201.14:19:44.32#ibcon#flushed, iclass 25, count 2 2006.201.14:19:44.32#ibcon#about to write, iclass 25, count 2 2006.201.14:19:44.32#ibcon#wrote, iclass 25, count 2 2006.201.14:19:44.32#ibcon#about to read 3, iclass 25, count 2 2006.201.14:19:44.35#ibcon#read 3, iclass 25, count 2 2006.201.14:19:44.35#ibcon#about to read 4, iclass 25, count 2 2006.201.14:19:44.35#ibcon#read 4, iclass 25, count 2 2006.201.14:19:44.35#ibcon#about to read 5, iclass 25, count 2 2006.201.14:19:44.35#ibcon#read 5, iclass 25, count 2 2006.201.14:19:44.35#ibcon#about to read 6, iclass 25, count 2 2006.201.14:19:44.35#ibcon#read 6, iclass 25, count 2 2006.201.14:19:44.35#ibcon#end of sib2, iclass 25, count 2 2006.201.14:19:44.35#ibcon#*after write, iclass 25, count 2 2006.201.14:19:44.35#ibcon#*before return 0, iclass 25, count 2 2006.201.14:19:44.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:44.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:19:44.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.14:19:44.35#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:44.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:44.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:44.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:44.47#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:19:44.47#ibcon#first serial, iclass 25, count 0 2006.201.14:19:44.47#ibcon#enter sib2, iclass 25, count 0 2006.201.14:19:44.47#ibcon#flushed, iclass 25, count 0 2006.201.14:19:44.47#ibcon#about to write, iclass 25, count 0 2006.201.14:19:44.47#ibcon#wrote, iclass 25, count 0 2006.201.14:19:44.47#ibcon#about to read 3, iclass 25, count 0 2006.201.14:19:44.49#ibcon#read 3, iclass 25, count 0 2006.201.14:19:44.49#ibcon#about to read 4, iclass 25, count 0 2006.201.14:19:44.49#ibcon#read 4, iclass 25, count 0 2006.201.14:19:44.49#ibcon#about to read 5, iclass 25, count 0 2006.201.14:19:44.49#ibcon#read 5, iclass 25, count 0 2006.201.14:19:44.49#ibcon#about to read 6, iclass 25, count 0 2006.201.14:19:44.49#ibcon#read 6, iclass 25, count 0 2006.201.14:19:44.49#ibcon#end of sib2, iclass 25, count 0 2006.201.14:19:44.49#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:19:44.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:19:44.49#ibcon#[27=USB\r\n] 2006.201.14:19:44.49#ibcon#*before write, iclass 25, count 0 2006.201.14:19:44.49#ibcon#enter sib2, iclass 25, count 0 2006.201.14:19:44.49#ibcon#flushed, iclass 25, count 0 2006.201.14:19:44.49#ibcon#about to write, iclass 25, count 0 2006.201.14:19:44.49#ibcon#wrote, iclass 25, count 0 2006.201.14:19:44.49#ibcon#about to read 3, iclass 25, count 0 2006.201.14:19:44.52#ibcon#read 3, iclass 25, count 0 2006.201.14:19:44.52#ibcon#about to read 4, iclass 25, count 0 2006.201.14:19:44.52#ibcon#read 4, iclass 25, count 0 2006.201.14:19:44.52#ibcon#about to read 5, iclass 25, count 0 2006.201.14:19:44.52#ibcon#read 5, iclass 25, count 0 2006.201.14:19:44.52#ibcon#about to read 6, iclass 25, count 0 2006.201.14:19:44.52#ibcon#read 6, iclass 25, count 0 2006.201.14:19:44.52#ibcon#end of sib2, iclass 25, count 0 2006.201.14:19:44.52#ibcon#*after write, iclass 25, count 0 2006.201.14:19:44.52#ibcon#*before return 0, iclass 25, count 0 2006.201.14:19:44.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:44.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:19:44.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:19:44.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:19:44.52$vck44/vblo=7,734.99 2006.201.14:19:44.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.14:19:44.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.14:19:44.52#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:44.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:44.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:44.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:44.52#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:19:44.52#ibcon#first serial, iclass 27, count 0 2006.201.14:19:44.52#ibcon#enter sib2, iclass 27, count 0 2006.201.14:19:44.52#ibcon#flushed, iclass 27, count 0 2006.201.14:19:44.52#ibcon#about to write, iclass 27, count 0 2006.201.14:19:44.52#ibcon#wrote, iclass 27, count 0 2006.201.14:19:44.52#ibcon#about to read 3, iclass 27, count 0 2006.201.14:19:44.54#ibcon#read 3, iclass 27, count 0 2006.201.14:19:44.54#ibcon#about to read 4, iclass 27, count 0 2006.201.14:19:44.54#ibcon#read 4, iclass 27, count 0 2006.201.14:19:44.54#ibcon#about to read 5, iclass 27, count 0 2006.201.14:19:44.54#ibcon#read 5, iclass 27, count 0 2006.201.14:19:44.54#ibcon#about to read 6, iclass 27, count 0 2006.201.14:19:44.54#ibcon#read 6, iclass 27, count 0 2006.201.14:19:44.54#ibcon#end of sib2, iclass 27, count 0 2006.201.14:19:44.54#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:19:44.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:19:44.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:19:44.54#ibcon#*before write, iclass 27, count 0 2006.201.14:19:44.54#ibcon#enter sib2, iclass 27, count 0 2006.201.14:19:44.54#ibcon#flushed, iclass 27, count 0 2006.201.14:19:44.54#ibcon#about to write, iclass 27, count 0 2006.201.14:19:44.54#ibcon#wrote, iclass 27, count 0 2006.201.14:19:44.54#ibcon#about to read 3, iclass 27, count 0 2006.201.14:19:44.58#ibcon#read 3, iclass 27, count 0 2006.201.14:19:44.58#ibcon#about to read 4, iclass 27, count 0 2006.201.14:19:44.58#ibcon#read 4, iclass 27, count 0 2006.201.14:19:44.58#ibcon#about to read 5, iclass 27, count 0 2006.201.14:19:44.58#ibcon#read 5, iclass 27, count 0 2006.201.14:19:44.58#ibcon#about to read 6, iclass 27, count 0 2006.201.14:19:44.58#ibcon#read 6, iclass 27, count 0 2006.201.14:19:44.58#ibcon#end of sib2, iclass 27, count 0 2006.201.14:19:44.58#ibcon#*after write, iclass 27, count 0 2006.201.14:19:44.58#ibcon#*before return 0, iclass 27, count 0 2006.201.14:19:44.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:44.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:19:44.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:19:44.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:19:44.58$vck44/vb=7,4 2006.201.14:19:44.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.14:19:44.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.14:19:44.58#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:44.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:44.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:44.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:44.64#ibcon#enter wrdev, iclass 29, count 2 2006.201.14:19:44.64#ibcon#first serial, iclass 29, count 2 2006.201.14:19:44.64#ibcon#enter sib2, iclass 29, count 2 2006.201.14:19:44.64#ibcon#flushed, iclass 29, count 2 2006.201.14:19:44.64#ibcon#about to write, iclass 29, count 2 2006.201.14:19:44.64#ibcon#wrote, iclass 29, count 2 2006.201.14:19:44.64#ibcon#about to read 3, iclass 29, count 2 2006.201.14:19:44.66#ibcon#read 3, iclass 29, count 2 2006.201.14:19:44.66#ibcon#about to read 4, iclass 29, count 2 2006.201.14:19:44.66#ibcon#read 4, iclass 29, count 2 2006.201.14:19:44.66#ibcon#about to read 5, iclass 29, count 2 2006.201.14:19:44.66#ibcon#read 5, iclass 29, count 2 2006.201.14:19:44.66#ibcon#about to read 6, iclass 29, count 2 2006.201.14:19:44.66#ibcon#read 6, iclass 29, count 2 2006.201.14:19:44.66#ibcon#end of sib2, iclass 29, count 2 2006.201.14:19:44.66#ibcon#*mode == 0, iclass 29, count 2 2006.201.14:19:44.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.14:19:44.66#ibcon#[27=AT07-04\r\n] 2006.201.14:19:44.66#ibcon#*before write, iclass 29, count 2 2006.201.14:19:44.66#ibcon#enter sib2, iclass 29, count 2 2006.201.14:19:44.66#ibcon#flushed, iclass 29, count 2 2006.201.14:19:44.66#ibcon#about to write, iclass 29, count 2 2006.201.14:19:44.66#ibcon#wrote, iclass 29, count 2 2006.201.14:19:44.66#ibcon#about to read 3, iclass 29, count 2 2006.201.14:19:44.69#ibcon#read 3, iclass 29, count 2 2006.201.14:19:44.69#ibcon#about to read 4, iclass 29, count 2 2006.201.14:19:44.69#ibcon#read 4, iclass 29, count 2 2006.201.14:19:44.69#ibcon#about to read 5, iclass 29, count 2 2006.201.14:19:44.69#ibcon#read 5, iclass 29, count 2 2006.201.14:19:44.69#ibcon#about to read 6, iclass 29, count 2 2006.201.14:19:44.69#ibcon#read 6, iclass 29, count 2 2006.201.14:19:44.69#ibcon#end of sib2, iclass 29, count 2 2006.201.14:19:44.69#ibcon#*after write, iclass 29, count 2 2006.201.14:19:44.69#ibcon#*before return 0, iclass 29, count 2 2006.201.14:19:44.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:44.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:19:44.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.14:19:44.69#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:44.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:44.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:44.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:44.81#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:19:44.81#ibcon#first serial, iclass 29, count 0 2006.201.14:19:44.81#ibcon#enter sib2, iclass 29, count 0 2006.201.14:19:44.81#ibcon#flushed, iclass 29, count 0 2006.201.14:19:44.81#ibcon#about to write, iclass 29, count 0 2006.201.14:19:44.81#ibcon#wrote, iclass 29, count 0 2006.201.14:19:44.81#ibcon#about to read 3, iclass 29, count 0 2006.201.14:19:44.83#ibcon#read 3, iclass 29, count 0 2006.201.14:19:44.83#ibcon#about to read 4, iclass 29, count 0 2006.201.14:19:44.83#ibcon#read 4, iclass 29, count 0 2006.201.14:19:44.83#ibcon#about to read 5, iclass 29, count 0 2006.201.14:19:44.83#ibcon#read 5, iclass 29, count 0 2006.201.14:19:44.83#ibcon#about to read 6, iclass 29, count 0 2006.201.14:19:44.83#ibcon#read 6, iclass 29, count 0 2006.201.14:19:44.83#ibcon#end of sib2, iclass 29, count 0 2006.201.14:19:44.83#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:19:44.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:19:44.83#ibcon#[27=USB\r\n] 2006.201.14:19:44.83#ibcon#*before write, iclass 29, count 0 2006.201.14:19:44.83#ibcon#enter sib2, iclass 29, count 0 2006.201.14:19:44.83#ibcon#flushed, iclass 29, count 0 2006.201.14:19:44.83#ibcon#about to write, iclass 29, count 0 2006.201.14:19:44.83#ibcon#wrote, iclass 29, count 0 2006.201.14:19:44.83#ibcon#about to read 3, iclass 29, count 0 2006.201.14:19:44.86#ibcon#read 3, iclass 29, count 0 2006.201.14:19:44.86#ibcon#about to read 4, iclass 29, count 0 2006.201.14:19:44.86#ibcon#read 4, iclass 29, count 0 2006.201.14:19:44.86#ibcon#about to read 5, iclass 29, count 0 2006.201.14:19:44.86#ibcon#read 5, iclass 29, count 0 2006.201.14:19:44.86#ibcon#about to read 6, iclass 29, count 0 2006.201.14:19:44.86#ibcon#read 6, iclass 29, count 0 2006.201.14:19:44.86#ibcon#end of sib2, iclass 29, count 0 2006.201.14:19:44.86#ibcon#*after write, iclass 29, count 0 2006.201.14:19:44.86#ibcon#*before return 0, iclass 29, count 0 2006.201.14:19:44.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:44.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:19:44.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:19:44.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:19:44.86$vck44/vblo=8,744.99 2006.201.14:19:44.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.14:19:44.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.14:19:44.86#ibcon#ireg 17 cls_cnt 0 2006.201.14:19:44.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:44.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:44.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:44.86#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:19:44.86#ibcon#first serial, iclass 31, count 0 2006.201.14:19:44.86#ibcon#enter sib2, iclass 31, count 0 2006.201.14:19:44.86#ibcon#flushed, iclass 31, count 0 2006.201.14:19:44.86#ibcon#about to write, iclass 31, count 0 2006.201.14:19:44.86#ibcon#wrote, iclass 31, count 0 2006.201.14:19:44.86#ibcon#about to read 3, iclass 31, count 0 2006.201.14:19:44.88#ibcon#read 3, iclass 31, count 0 2006.201.14:19:44.88#ibcon#about to read 4, iclass 31, count 0 2006.201.14:19:44.88#ibcon#read 4, iclass 31, count 0 2006.201.14:19:44.88#ibcon#about to read 5, iclass 31, count 0 2006.201.14:19:44.88#ibcon#read 5, iclass 31, count 0 2006.201.14:19:44.88#ibcon#about to read 6, iclass 31, count 0 2006.201.14:19:44.88#ibcon#read 6, iclass 31, count 0 2006.201.14:19:44.88#ibcon#end of sib2, iclass 31, count 0 2006.201.14:19:44.88#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:19:44.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:19:44.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:19:44.88#ibcon#*before write, iclass 31, count 0 2006.201.14:19:44.88#ibcon#enter sib2, iclass 31, count 0 2006.201.14:19:44.88#ibcon#flushed, iclass 31, count 0 2006.201.14:19:44.88#ibcon#about to write, iclass 31, count 0 2006.201.14:19:44.88#ibcon#wrote, iclass 31, count 0 2006.201.14:19:44.88#ibcon#about to read 3, iclass 31, count 0 2006.201.14:19:44.92#ibcon#read 3, iclass 31, count 0 2006.201.14:19:44.92#ibcon#about to read 4, iclass 31, count 0 2006.201.14:19:44.92#ibcon#read 4, iclass 31, count 0 2006.201.14:19:44.92#ibcon#about to read 5, iclass 31, count 0 2006.201.14:19:44.92#ibcon#read 5, iclass 31, count 0 2006.201.14:19:44.92#ibcon#about to read 6, iclass 31, count 0 2006.201.14:19:44.92#ibcon#read 6, iclass 31, count 0 2006.201.14:19:44.92#ibcon#end of sib2, iclass 31, count 0 2006.201.14:19:44.92#ibcon#*after write, iclass 31, count 0 2006.201.14:19:44.92#ibcon#*before return 0, iclass 31, count 0 2006.201.14:19:44.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:44.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:19:44.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:19:44.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:19:44.92$vck44/vb=8,4 2006.201.14:19:44.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.14:19:44.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.14:19:44.92#ibcon#ireg 11 cls_cnt 2 2006.201.14:19:44.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:44.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:44.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:44.98#ibcon#enter wrdev, iclass 33, count 2 2006.201.14:19:44.98#ibcon#first serial, iclass 33, count 2 2006.201.14:19:44.98#ibcon#enter sib2, iclass 33, count 2 2006.201.14:19:44.98#ibcon#flushed, iclass 33, count 2 2006.201.14:19:44.98#ibcon#about to write, iclass 33, count 2 2006.201.14:19:44.98#ibcon#wrote, iclass 33, count 2 2006.201.14:19:44.98#ibcon#about to read 3, iclass 33, count 2 2006.201.14:19:45.00#ibcon#read 3, iclass 33, count 2 2006.201.14:19:45.00#ibcon#about to read 4, iclass 33, count 2 2006.201.14:19:45.00#ibcon#read 4, iclass 33, count 2 2006.201.14:19:45.00#ibcon#about to read 5, iclass 33, count 2 2006.201.14:19:45.00#ibcon#read 5, iclass 33, count 2 2006.201.14:19:45.00#ibcon#about to read 6, iclass 33, count 2 2006.201.14:19:45.00#ibcon#read 6, iclass 33, count 2 2006.201.14:19:45.00#ibcon#end of sib2, iclass 33, count 2 2006.201.14:19:45.00#ibcon#*mode == 0, iclass 33, count 2 2006.201.14:19:45.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.14:19:45.00#ibcon#[27=AT08-04\r\n] 2006.201.14:19:45.00#ibcon#*before write, iclass 33, count 2 2006.201.14:19:45.00#ibcon#enter sib2, iclass 33, count 2 2006.201.14:19:45.00#ibcon#flushed, iclass 33, count 2 2006.201.14:19:45.00#ibcon#about to write, iclass 33, count 2 2006.201.14:19:45.00#ibcon#wrote, iclass 33, count 2 2006.201.14:19:45.00#ibcon#about to read 3, iclass 33, count 2 2006.201.14:19:45.03#ibcon#read 3, iclass 33, count 2 2006.201.14:19:45.03#ibcon#about to read 4, iclass 33, count 2 2006.201.14:19:45.03#ibcon#read 4, iclass 33, count 2 2006.201.14:19:45.03#ibcon#about to read 5, iclass 33, count 2 2006.201.14:19:45.03#ibcon#read 5, iclass 33, count 2 2006.201.14:19:45.03#ibcon#about to read 6, iclass 33, count 2 2006.201.14:19:45.03#ibcon#read 6, iclass 33, count 2 2006.201.14:19:45.03#ibcon#end of sib2, iclass 33, count 2 2006.201.14:19:45.03#ibcon#*after write, iclass 33, count 2 2006.201.14:19:45.03#ibcon#*before return 0, iclass 33, count 2 2006.201.14:19:45.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:45.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:19:45.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.14:19:45.03#ibcon#ireg 7 cls_cnt 0 2006.201.14:19:45.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:45.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:45.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:45.15#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:19:45.15#ibcon#first serial, iclass 33, count 0 2006.201.14:19:45.15#ibcon#enter sib2, iclass 33, count 0 2006.201.14:19:45.15#ibcon#flushed, iclass 33, count 0 2006.201.14:19:45.15#ibcon#about to write, iclass 33, count 0 2006.201.14:19:45.15#ibcon#wrote, iclass 33, count 0 2006.201.14:19:45.15#ibcon#about to read 3, iclass 33, count 0 2006.201.14:19:45.17#ibcon#read 3, iclass 33, count 0 2006.201.14:19:45.17#ibcon#about to read 4, iclass 33, count 0 2006.201.14:19:45.17#ibcon#read 4, iclass 33, count 0 2006.201.14:19:45.17#ibcon#about to read 5, iclass 33, count 0 2006.201.14:19:45.17#ibcon#read 5, iclass 33, count 0 2006.201.14:19:45.17#ibcon#about to read 6, iclass 33, count 0 2006.201.14:19:45.17#ibcon#read 6, iclass 33, count 0 2006.201.14:19:45.17#ibcon#end of sib2, iclass 33, count 0 2006.201.14:19:45.17#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:19:45.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:19:45.17#ibcon#[27=USB\r\n] 2006.201.14:19:45.17#ibcon#*before write, iclass 33, count 0 2006.201.14:19:45.17#ibcon#enter sib2, iclass 33, count 0 2006.201.14:19:45.17#ibcon#flushed, iclass 33, count 0 2006.201.14:19:45.17#ibcon#about to write, iclass 33, count 0 2006.201.14:19:45.17#ibcon#wrote, iclass 33, count 0 2006.201.14:19:45.17#ibcon#about to read 3, iclass 33, count 0 2006.201.14:19:45.20#ibcon#read 3, iclass 33, count 0 2006.201.14:19:45.20#ibcon#about to read 4, iclass 33, count 0 2006.201.14:19:45.20#ibcon#read 4, iclass 33, count 0 2006.201.14:19:45.20#ibcon#about to read 5, iclass 33, count 0 2006.201.14:19:45.20#ibcon#read 5, iclass 33, count 0 2006.201.14:19:45.20#ibcon#about to read 6, iclass 33, count 0 2006.201.14:19:45.20#ibcon#read 6, iclass 33, count 0 2006.201.14:19:45.20#ibcon#end of sib2, iclass 33, count 0 2006.201.14:19:45.20#ibcon#*after write, iclass 33, count 0 2006.201.14:19:45.20#ibcon#*before return 0, iclass 33, count 0 2006.201.14:19:45.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:45.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:19:45.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:19:45.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:19:45.20$vck44/vabw=wide 2006.201.14:19:45.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.14:19:45.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.14:19:45.20#ibcon#ireg 8 cls_cnt 0 2006.201.14:19:45.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:45.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:45.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:45.20#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:19:45.20#ibcon#first serial, iclass 35, count 0 2006.201.14:19:45.20#ibcon#enter sib2, iclass 35, count 0 2006.201.14:19:45.20#ibcon#flushed, iclass 35, count 0 2006.201.14:19:45.20#ibcon#about to write, iclass 35, count 0 2006.201.14:19:45.20#ibcon#wrote, iclass 35, count 0 2006.201.14:19:45.20#ibcon#about to read 3, iclass 35, count 0 2006.201.14:19:45.22#ibcon#read 3, iclass 35, count 0 2006.201.14:19:45.22#ibcon#about to read 4, iclass 35, count 0 2006.201.14:19:45.22#ibcon#read 4, iclass 35, count 0 2006.201.14:19:45.22#ibcon#about to read 5, iclass 35, count 0 2006.201.14:19:45.22#ibcon#read 5, iclass 35, count 0 2006.201.14:19:45.22#ibcon#about to read 6, iclass 35, count 0 2006.201.14:19:45.22#ibcon#read 6, iclass 35, count 0 2006.201.14:19:45.22#ibcon#end of sib2, iclass 35, count 0 2006.201.14:19:45.22#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:19:45.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:19:45.22#ibcon#[25=BW32\r\n] 2006.201.14:19:45.22#ibcon#*before write, iclass 35, count 0 2006.201.14:19:45.22#ibcon#enter sib2, iclass 35, count 0 2006.201.14:19:45.22#ibcon#flushed, iclass 35, count 0 2006.201.14:19:45.22#ibcon#about to write, iclass 35, count 0 2006.201.14:19:45.22#ibcon#wrote, iclass 35, count 0 2006.201.14:19:45.22#ibcon#about to read 3, iclass 35, count 0 2006.201.14:19:45.25#ibcon#read 3, iclass 35, count 0 2006.201.14:19:45.25#ibcon#about to read 4, iclass 35, count 0 2006.201.14:19:45.25#ibcon#read 4, iclass 35, count 0 2006.201.14:19:45.25#ibcon#about to read 5, iclass 35, count 0 2006.201.14:19:45.25#ibcon#read 5, iclass 35, count 0 2006.201.14:19:45.25#ibcon#about to read 6, iclass 35, count 0 2006.201.14:19:45.25#ibcon#read 6, iclass 35, count 0 2006.201.14:19:45.25#ibcon#end of sib2, iclass 35, count 0 2006.201.14:19:45.25#ibcon#*after write, iclass 35, count 0 2006.201.14:19:45.25#ibcon#*before return 0, iclass 35, count 0 2006.201.14:19:45.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:45.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:19:45.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:19:45.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:19:45.25$vck44/vbbw=wide 2006.201.14:19:45.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.14:19:45.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.14:19:45.25#ibcon#ireg 8 cls_cnt 0 2006.201.14:19:45.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:19:45.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:19:45.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:19:45.32#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:19:45.32#ibcon#first serial, iclass 37, count 0 2006.201.14:19:45.32#ibcon#enter sib2, iclass 37, count 0 2006.201.14:19:45.32#ibcon#flushed, iclass 37, count 0 2006.201.14:19:45.32#ibcon#about to write, iclass 37, count 0 2006.201.14:19:45.32#ibcon#wrote, iclass 37, count 0 2006.201.14:19:45.32#ibcon#about to read 3, iclass 37, count 0 2006.201.14:19:45.34#ibcon#read 3, iclass 37, count 0 2006.201.14:19:45.34#ibcon#about to read 4, iclass 37, count 0 2006.201.14:19:45.34#ibcon#read 4, iclass 37, count 0 2006.201.14:19:45.34#ibcon#about to read 5, iclass 37, count 0 2006.201.14:19:45.34#ibcon#read 5, iclass 37, count 0 2006.201.14:19:45.34#ibcon#about to read 6, iclass 37, count 0 2006.201.14:19:45.34#ibcon#read 6, iclass 37, count 0 2006.201.14:19:45.34#ibcon#end of sib2, iclass 37, count 0 2006.201.14:19:45.34#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:19:45.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:19:45.34#ibcon#[27=BW32\r\n] 2006.201.14:19:45.34#ibcon#*before write, iclass 37, count 0 2006.201.14:19:45.34#ibcon#enter sib2, iclass 37, count 0 2006.201.14:19:45.34#ibcon#flushed, iclass 37, count 0 2006.201.14:19:45.34#ibcon#about to write, iclass 37, count 0 2006.201.14:19:45.34#ibcon#wrote, iclass 37, count 0 2006.201.14:19:45.34#ibcon#about to read 3, iclass 37, count 0 2006.201.14:19:45.37#ibcon#read 3, iclass 37, count 0 2006.201.14:19:45.37#ibcon#about to read 4, iclass 37, count 0 2006.201.14:19:45.37#ibcon#read 4, iclass 37, count 0 2006.201.14:19:45.37#ibcon#about to read 5, iclass 37, count 0 2006.201.14:19:45.37#ibcon#read 5, iclass 37, count 0 2006.201.14:19:45.37#ibcon#about to read 6, iclass 37, count 0 2006.201.14:19:45.37#ibcon#read 6, iclass 37, count 0 2006.201.14:19:45.37#ibcon#end of sib2, iclass 37, count 0 2006.201.14:19:45.37#ibcon#*after write, iclass 37, count 0 2006.201.14:19:45.37#ibcon#*before return 0, iclass 37, count 0 2006.201.14:19:45.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:19:45.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:19:45.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:19:45.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:19:45.37$setupk4/ifdk4 2006.201.14:19:45.37$ifdk4/lo= 2006.201.14:19:45.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:19:45.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:19:45.37$ifdk4/patch= 2006.201.14:19:45.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:19:45.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:19:45.37$setupk4/!*+20s 2006.201.14:19:52.84#abcon#<5=/05 1.8 2.8 20.831001003.5\r\n> 2006.201.14:19:52.86#abcon#{5=INTERFACE CLEAR} 2006.201.14:19:52.92#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:19:59.88$setupk4/"tpicd 2006.201.14:19:59.88$setupk4/echo=off 2006.201.14:19:59.88$setupk4/xlog=off 2006.201.14:19:59.88:!2006.201.14:21:08 2006.201.14:20:13.14#trakl#Source acquired 2006.201.14:20:14.14#flagr#flagr/antenna,acquired 2006.201.14:21:08.00:preob 2006.201.14:21:09.13/onsource/TRACKING 2006.201.14:21:09.13:!2006.201.14:21:18 2006.201.14:21:18.00:"tape 2006.201.14:21:18.00:"st=record 2006.201.14:21:18.00:data_valid=on 2006.201.14:21:18.00:midob 2006.201.14:21:18.13/onsource/TRACKING 2006.201.14:21:18.13/wx/20.82,1003.5,100 2006.201.14:21:18.30/cable/+6.4739E-03 2006.201.14:21:19.39/va/01,08,usb,yes,28,30 2006.201.14:21:19.39/va/02,07,usb,yes,30,31 2006.201.14:21:19.39/va/03,08,usb,yes,27,28 2006.201.14:21:19.39/va/04,07,usb,yes,31,32 2006.201.14:21:19.39/va/05,04,usb,yes,27,28 2006.201.14:21:19.39/va/06,05,usb,yes,27,27 2006.201.14:21:19.39/va/07,05,usb,yes,26,28 2006.201.14:21:19.39/va/08,04,usb,yes,26,32 2006.201.14:21:19.62/valo/01,524.99,yes,locked 2006.201.14:21:19.62/valo/02,534.99,yes,locked 2006.201.14:21:19.62/valo/03,564.99,yes,locked 2006.201.14:21:19.62/valo/04,624.99,yes,locked 2006.201.14:21:19.62/valo/05,734.99,yes,locked 2006.201.14:21:19.62/valo/06,814.99,yes,locked 2006.201.14:21:19.62/valo/07,864.99,yes,locked 2006.201.14:21:19.62/valo/08,884.99,yes,locked 2006.201.14:21:20.71/vb/01,04,usb,yes,28,26 2006.201.14:21:20.71/vb/02,05,usb,yes,27,26 2006.201.14:21:20.71/vb/03,04,usb,yes,27,30 2006.201.14:21:20.71/vb/04,05,usb,yes,28,27 2006.201.14:21:20.71/vb/05,04,usb,yes,24,27 2006.201.14:21:20.71/vb/06,04,usb,yes,29,25 2006.201.14:21:20.71/vb/07,04,usb,yes,28,28 2006.201.14:21:20.71/vb/08,04,usb,yes,26,29 2006.201.14:21:20.94/vblo/01,629.99,yes,locked 2006.201.14:21:20.94/vblo/02,634.99,yes,locked 2006.201.14:21:20.94/vblo/03,649.99,yes,locked 2006.201.14:21:20.94/vblo/04,679.99,yes,locked 2006.201.14:21:20.94/vblo/05,709.99,yes,locked 2006.201.14:21:20.94/vblo/06,719.99,yes,locked 2006.201.14:21:20.94/vblo/07,734.99,yes,locked 2006.201.14:21:20.94/vblo/08,744.99,yes,locked 2006.201.14:21:21.09/vabw/8 2006.201.14:21:21.24/vbbw/8 2006.201.14:21:21.33/xfe/off,on,14.5 2006.201.14:21:21.72/ifatt/23,28,28,28 2006.201.14:21:22.06/fmout-gps/S +4.54E-07 2006.201.14:21:22.13:!2006.201.14:23:18 2006.201.14:23:18.00:data_valid=off 2006.201.14:23:18.00:"et 2006.201.14:23:18.00:!+3s 2006.201.14:23:21.02:"tape 2006.201.14:23:21.02:postob 2006.201.14:23:21.21/cable/+6.4751E-03 2006.201.14:23:21.21/wx/20.81,1003.4,100 2006.201.14:23:21.28/fmout-gps/S +4.55E-07 2006.201.14:23:21.28:scan_name=201-1429,jd0607,230 2006.201.14:23:21.28:source=0059+581,010245.76,582411.1,2000.0,cw 2006.201.14:23:22.14#flagr#flagr/antenna,new-source 2006.201.14:23:22.14:checkk5 2006.201.14:23:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:23:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:23:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:23:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:23:24.00/chk_obsdata//k5ts1/T2011421??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.14:23:24.36/chk_obsdata//k5ts2/T2011421??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.14:23:24.73/chk_obsdata//k5ts3/T2011421??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.14:23:25.10/chk_obsdata//k5ts4/T2011421??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.14:23:25.78/k5log//k5ts1_log_newline 2006.201.14:23:26.47/k5log//k5ts2_log_newline 2006.201.14:23:27.16/k5log//k5ts3_log_newline 2006.201.14:23:27.85/k5log//k5ts4_log_newline 2006.201.14:23:27.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:23:27.87:setupk4=1 2006.201.14:23:27.87$setupk4/echo=on 2006.201.14:23:27.87$setupk4/pcalon 2006.201.14:23:27.87$pcalon/"no phase cal control is implemented here 2006.201.14:23:27.87$setupk4/"tpicd=stop 2006.201.14:23:27.87$setupk4/"rec=synch_on 2006.201.14:23:27.87$setupk4/"rec_mode=128 2006.201.14:23:27.87$setupk4/!* 2006.201.14:23:27.87$setupk4/recpk4 2006.201.14:23:27.87$recpk4/recpatch= 2006.201.14:23:27.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:23:27.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:23:27.88$setupk4/vck44 2006.201.14:23:27.88$vck44/valo=1,524.99 2006.201.14:23:27.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.14:23:27.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.14:23:27.88#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:27.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:27.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:27.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:27.88#ibcon#enter wrdev, iclass 22, count 0 2006.201.14:23:27.88#ibcon#first serial, iclass 22, count 0 2006.201.14:23:27.88#ibcon#enter sib2, iclass 22, count 0 2006.201.14:23:27.88#ibcon#flushed, iclass 22, count 0 2006.201.14:23:27.88#ibcon#about to write, iclass 22, count 0 2006.201.14:23:27.88#ibcon#wrote, iclass 22, count 0 2006.201.14:23:27.88#ibcon#about to read 3, iclass 22, count 0 2006.201.14:23:27.91#ibcon#read 3, iclass 22, count 0 2006.201.14:23:27.91#ibcon#about to read 4, iclass 22, count 0 2006.201.14:23:27.91#ibcon#read 4, iclass 22, count 0 2006.201.14:23:27.91#ibcon#about to read 5, iclass 22, count 0 2006.201.14:23:27.91#ibcon#read 5, iclass 22, count 0 2006.201.14:23:27.91#ibcon#about to read 6, iclass 22, count 0 2006.201.14:23:27.91#ibcon#read 6, iclass 22, count 0 2006.201.14:23:27.91#ibcon#end of sib2, iclass 22, count 0 2006.201.14:23:27.91#ibcon#*mode == 0, iclass 22, count 0 2006.201.14:23:27.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.14:23:27.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:23:27.91#ibcon#*before write, iclass 22, count 0 2006.201.14:23:27.91#ibcon#enter sib2, iclass 22, count 0 2006.201.14:23:27.91#ibcon#flushed, iclass 22, count 0 2006.201.14:23:27.91#ibcon#about to write, iclass 22, count 0 2006.201.14:23:27.91#ibcon#wrote, iclass 22, count 0 2006.201.14:23:27.91#ibcon#about to read 3, iclass 22, count 0 2006.201.14:23:27.96#ibcon#read 3, iclass 22, count 0 2006.201.14:23:27.96#ibcon#about to read 4, iclass 22, count 0 2006.201.14:23:27.96#ibcon#read 4, iclass 22, count 0 2006.201.14:23:27.96#ibcon#about to read 5, iclass 22, count 0 2006.201.14:23:27.96#ibcon#read 5, iclass 22, count 0 2006.201.14:23:27.96#ibcon#about to read 6, iclass 22, count 0 2006.201.14:23:27.96#ibcon#read 6, iclass 22, count 0 2006.201.14:23:27.96#ibcon#end of sib2, iclass 22, count 0 2006.201.14:23:27.96#ibcon#*after write, iclass 22, count 0 2006.201.14:23:27.96#ibcon#*before return 0, iclass 22, count 0 2006.201.14:23:27.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:27.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:27.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.14:23:27.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.14:23:27.96$vck44/va=1,8 2006.201.14:23:27.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.14:23:27.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.14:23:27.96#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:27.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:27.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:27.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:27.96#ibcon#enter wrdev, iclass 24, count 2 2006.201.14:23:27.96#ibcon#first serial, iclass 24, count 2 2006.201.14:23:27.96#ibcon#enter sib2, iclass 24, count 2 2006.201.14:23:27.96#ibcon#flushed, iclass 24, count 2 2006.201.14:23:27.96#ibcon#about to write, iclass 24, count 2 2006.201.14:23:27.96#ibcon#wrote, iclass 24, count 2 2006.201.14:23:27.96#ibcon#about to read 3, iclass 24, count 2 2006.201.14:23:27.98#ibcon#read 3, iclass 24, count 2 2006.201.14:23:27.98#ibcon#about to read 4, iclass 24, count 2 2006.201.14:23:27.98#ibcon#read 4, iclass 24, count 2 2006.201.14:23:27.98#ibcon#about to read 5, iclass 24, count 2 2006.201.14:23:27.98#ibcon#read 5, iclass 24, count 2 2006.201.14:23:27.98#ibcon#about to read 6, iclass 24, count 2 2006.201.14:23:27.98#ibcon#read 6, iclass 24, count 2 2006.201.14:23:27.98#ibcon#end of sib2, iclass 24, count 2 2006.201.14:23:27.98#ibcon#*mode == 0, iclass 24, count 2 2006.201.14:23:27.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.14:23:27.98#ibcon#[25=AT01-08\r\n] 2006.201.14:23:27.98#ibcon#*before write, iclass 24, count 2 2006.201.14:23:27.98#ibcon#enter sib2, iclass 24, count 2 2006.201.14:23:27.98#ibcon#flushed, iclass 24, count 2 2006.201.14:23:27.98#ibcon#about to write, iclass 24, count 2 2006.201.14:23:27.98#ibcon#wrote, iclass 24, count 2 2006.201.14:23:27.98#ibcon#about to read 3, iclass 24, count 2 2006.201.14:23:28.01#ibcon#read 3, iclass 24, count 2 2006.201.14:23:28.01#ibcon#about to read 4, iclass 24, count 2 2006.201.14:23:28.01#ibcon#read 4, iclass 24, count 2 2006.201.14:23:28.01#ibcon#about to read 5, iclass 24, count 2 2006.201.14:23:28.01#ibcon#read 5, iclass 24, count 2 2006.201.14:23:28.01#ibcon#about to read 6, iclass 24, count 2 2006.201.14:23:28.01#ibcon#read 6, iclass 24, count 2 2006.201.14:23:28.01#ibcon#end of sib2, iclass 24, count 2 2006.201.14:23:28.01#ibcon#*after write, iclass 24, count 2 2006.201.14:23:28.01#ibcon#*before return 0, iclass 24, count 2 2006.201.14:23:28.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:28.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:28.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.14:23:28.01#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:28.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:28.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:28.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:28.13#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:23:28.13#ibcon#first serial, iclass 24, count 0 2006.201.14:23:28.13#ibcon#enter sib2, iclass 24, count 0 2006.201.14:23:28.13#ibcon#flushed, iclass 24, count 0 2006.201.14:23:28.13#ibcon#about to write, iclass 24, count 0 2006.201.14:23:28.13#ibcon#wrote, iclass 24, count 0 2006.201.14:23:28.13#ibcon#about to read 3, iclass 24, count 0 2006.201.14:23:28.15#ibcon#read 3, iclass 24, count 0 2006.201.14:23:28.15#ibcon#about to read 4, iclass 24, count 0 2006.201.14:23:28.15#ibcon#read 4, iclass 24, count 0 2006.201.14:23:28.15#ibcon#about to read 5, iclass 24, count 0 2006.201.14:23:28.15#ibcon#read 5, iclass 24, count 0 2006.201.14:23:28.15#ibcon#about to read 6, iclass 24, count 0 2006.201.14:23:28.15#ibcon#read 6, iclass 24, count 0 2006.201.14:23:28.15#ibcon#end of sib2, iclass 24, count 0 2006.201.14:23:28.15#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:23:28.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:23:28.15#ibcon#[25=USB\r\n] 2006.201.14:23:28.15#ibcon#*before write, iclass 24, count 0 2006.201.14:23:28.15#ibcon#enter sib2, iclass 24, count 0 2006.201.14:23:28.15#ibcon#flushed, iclass 24, count 0 2006.201.14:23:28.15#ibcon#about to write, iclass 24, count 0 2006.201.14:23:28.15#ibcon#wrote, iclass 24, count 0 2006.201.14:23:28.15#ibcon#about to read 3, iclass 24, count 0 2006.201.14:23:28.18#ibcon#read 3, iclass 24, count 0 2006.201.14:23:28.18#ibcon#about to read 4, iclass 24, count 0 2006.201.14:23:28.18#ibcon#read 4, iclass 24, count 0 2006.201.14:23:28.18#ibcon#about to read 5, iclass 24, count 0 2006.201.14:23:28.18#ibcon#read 5, iclass 24, count 0 2006.201.14:23:28.18#ibcon#about to read 6, iclass 24, count 0 2006.201.14:23:28.18#ibcon#read 6, iclass 24, count 0 2006.201.14:23:28.18#ibcon#end of sib2, iclass 24, count 0 2006.201.14:23:28.18#ibcon#*after write, iclass 24, count 0 2006.201.14:23:28.18#ibcon#*before return 0, iclass 24, count 0 2006.201.14:23:28.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:28.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:28.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:23:28.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:23:28.18$vck44/valo=2,534.99 2006.201.14:23:28.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.14:23:28.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.14:23:28.18#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:28.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:28.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:28.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:28.18#ibcon#enter wrdev, iclass 26, count 0 2006.201.14:23:28.18#ibcon#first serial, iclass 26, count 0 2006.201.14:23:28.18#ibcon#enter sib2, iclass 26, count 0 2006.201.14:23:28.18#ibcon#flushed, iclass 26, count 0 2006.201.14:23:28.18#ibcon#about to write, iclass 26, count 0 2006.201.14:23:28.18#ibcon#wrote, iclass 26, count 0 2006.201.14:23:28.18#ibcon#about to read 3, iclass 26, count 0 2006.201.14:23:28.20#ibcon#read 3, iclass 26, count 0 2006.201.14:23:28.20#ibcon#about to read 4, iclass 26, count 0 2006.201.14:23:28.20#ibcon#read 4, iclass 26, count 0 2006.201.14:23:28.20#ibcon#about to read 5, iclass 26, count 0 2006.201.14:23:28.20#ibcon#read 5, iclass 26, count 0 2006.201.14:23:28.20#ibcon#about to read 6, iclass 26, count 0 2006.201.14:23:28.20#ibcon#read 6, iclass 26, count 0 2006.201.14:23:28.20#ibcon#end of sib2, iclass 26, count 0 2006.201.14:23:28.20#ibcon#*mode == 0, iclass 26, count 0 2006.201.14:23:28.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.14:23:28.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:23:28.20#ibcon#*before write, iclass 26, count 0 2006.201.14:23:28.20#ibcon#enter sib2, iclass 26, count 0 2006.201.14:23:28.20#ibcon#flushed, iclass 26, count 0 2006.201.14:23:28.20#ibcon#about to write, iclass 26, count 0 2006.201.14:23:28.20#ibcon#wrote, iclass 26, count 0 2006.201.14:23:28.20#ibcon#about to read 3, iclass 26, count 0 2006.201.14:23:28.24#ibcon#read 3, iclass 26, count 0 2006.201.14:23:28.24#ibcon#about to read 4, iclass 26, count 0 2006.201.14:23:28.24#ibcon#read 4, iclass 26, count 0 2006.201.14:23:28.24#ibcon#about to read 5, iclass 26, count 0 2006.201.14:23:28.24#ibcon#read 5, iclass 26, count 0 2006.201.14:23:28.24#ibcon#about to read 6, iclass 26, count 0 2006.201.14:23:28.24#ibcon#read 6, iclass 26, count 0 2006.201.14:23:28.24#ibcon#end of sib2, iclass 26, count 0 2006.201.14:23:28.24#ibcon#*after write, iclass 26, count 0 2006.201.14:23:28.24#ibcon#*before return 0, iclass 26, count 0 2006.201.14:23:28.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:28.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:28.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.14:23:28.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.14:23:28.24$vck44/va=2,7 2006.201.14:23:28.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.14:23:28.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.14:23:28.24#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:28.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:28.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:28.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:28.30#ibcon#enter wrdev, iclass 28, count 2 2006.201.14:23:28.30#ibcon#first serial, iclass 28, count 2 2006.201.14:23:28.30#ibcon#enter sib2, iclass 28, count 2 2006.201.14:23:28.30#ibcon#flushed, iclass 28, count 2 2006.201.14:23:28.30#ibcon#about to write, iclass 28, count 2 2006.201.14:23:28.30#ibcon#wrote, iclass 28, count 2 2006.201.14:23:28.30#ibcon#about to read 3, iclass 28, count 2 2006.201.14:23:28.32#ibcon#read 3, iclass 28, count 2 2006.201.14:23:28.32#ibcon#about to read 4, iclass 28, count 2 2006.201.14:23:28.32#ibcon#read 4, iclass 28, count 2 2006.201.14:23:28.32#ibcon#about to read 5, iclass 28, count 2 2006.201.14:23:28.32#ibcon#read 5, iclass 28, count 2 2006.201.14:23:28.32#ibcon#about to read 6, iclass 28, count 2 2006.201.14:23:28.32#ibcon#read 6, iclass 28, count 2 2006.201.14:23:28.32#ibcon#end of sib2, iclass 28, count 2 2006.201.14:23:28.32#ibcon#*mode == 0, iclass 28, count 2 2006.201.14:23:28.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.14:23:28.32#ibcon#[25=AT02-07\r\n] 2006.201.14:23:28.32#ibcon#*before write, iclass 28, count 2 2006.201.14:23:28.32#ibcon#enter sib2, iclass 28, count 2 2006.201.14:23:28.32#ibcon#flushed, iclass 28, count 2 2006.201.14:23:28.32#ibcon#about to write, iclass 28, count 2 2006.201.14:23:28.32#ibcon#wrote, iclass 28, count 2 2006.201.14:23:28.32#ibcon#about to read 3, iclass 28, count 2 2006.201.14:23:28.35#ibcon#read 3, iclass 28, count 2 2006.201.14:23:28.35#ibcon#about to read 4, iclass 28, count 2 2006.201.14:23:28.35#ibcon#read 4, iclass 28, count 2 2006.201.14:23:28.35#ibcon#about to read 5, iclass 28, count 2 2006.201.14:23:28.35#ibcon#read 5, iclass 28, count 2 2006.201.14:23:28.35#ibcon#about to read 6, iclass 28, count 2 2006.201.14:23:28.35#ibcon#read 6, iclass 28, count 2 2006.201.14:23:28.35#ibcon#end of sib2, iclass 28, count 2 2006.201.14:23:28.35#ibcon#*after write, iclass 28, count 2 2006.201.14:23:28.35#ibcon#*before return 0, iclass 28, count 2 2006.201.14:23:28.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:28.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:28.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.14:23:28.35#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:28.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:28.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:28.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:28.47#ibcon#enter wrdev, iclass 28, count 0 2006.201.14:23:28.47#ibcon#first serial, iclass 28, count 0 2006.201.14:23:28.47#ibcon#enter sib2, iclass 28, count 0 2006.201.14:23:28.47#ibcon#flushed, iclass 28, count 0 2006.201.14:23:28.47#ibcon#about to write, iclass 28, count 0 2006.201.14:23:28.47#ibcon#wrote, iclass 28, count 0 2006.201.14:23:28.47#ibcon#about to read 3, iclass 28, count 0 2006.201.14:23:28.49#ibcon#read 3, iclass 28, count 0 2006.201.14:23:28.49#ibcon#about to read 4, iclass 28, count 0 2006.201.14:23:28.49#ibcon#read 4, iclass 28, count 0 2006.201.14:23:28.49#ibcon#about to read 5, iclass 28, count 0 2006.201.14:23:28.49#ibcon#read 5, iclass 28, count 0 2006.201.14:23:28.49#ibcon#about to read 6, iclass 28, count 0 2006.201.14:23:28.49#ibcon#read 6, iclass 28, count 0 2006.201.14:23:28.49#ibcon#end of sib2, iclass 28, count 0 2006.201.14:23:28.49#ibcon#*mode == 0, iclass 28, count 0 2006.201.14:23:28.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.14:23:28.49#ibcon#[25=USB\r\n] 2006.201.14:23:28.49#ibcon#*before write, iclass 28, count 0 2006.201.14:23:28.49#ibcon#enter sib2, iclass 28, count 0 2006.201.14:23:28.49#ibcon#flushed, iclass 28, count 0 2006.201.14:23:28.49#ibcon#about to write, iclass 28, count 0 2006.201.14:23:28.49#ibcon#wrote, iclass 28, count 0 2006.201.14:23:28.49#ibcon#about to read 3, iclass 28, count 0 2006.201.14:23:28.52#ibcon#read 3, iclass 28, count 0 2006.201.14:23:28.52#ibcon#about to read 4, iclass 28, count 0 2006.201.14:23:28.52#ibcon#read 4, iclass 28, count 0 2006.201.14:23:28.52#ibcon#about to read 5, iclass 28, count 0 2006.201.14:23:28.52#ibcon#read 5, iclass 28, count 0 2006.201.14:23:28.52#ibcon#about to read 6, iclass 28, count 0 2006.201.14:23:28.52#ibcon#read 6, iclass 28, count 0 2006.201.14:23:28.52#ibcon#end of sib2, iclass 28, count 0 2006.201.14:23:28.52#ibcon#*after write, iclass 28, count 0 2006.201.14:23:28.52#ibcon#*before return 0, iclass 28, count 0 2006.201.14:23:28.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:28.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:28.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.14:23:28.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.14:23:28.52$vck44/valo=3,564.99 2006.201.14:23:28.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.14:23:28.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.14:23:28.52#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:28.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:28.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:28.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:28.52#ibcon#enter wrdev, iclass 30, count 0 2006.201.14:23:28.52#ibcon#first serial, iclass 30, count 0 2006.201.14:23:28.52#ibcon#enter sib2, iclass 30, count 0 2006.201.14:23:28.52#ibcon#flushed, iclass 30, count 0 2006.201.14:23:28.52#ibcon#about to write, iclass 30, count 0 2006.201.14:23:28.52#ibcon#wrote, iclass 30, count 0 2006.201.14:23:28.52#ibcon#about to read 3, iclass 30, count 0 2006.201.14:23:28.54#ibcon#read 3, iclass 30, count 0 2006.201.14:23:28.54#ibcon#about to read 4, iclass 30, count 0 2006.201.14:23:28.54#ibcon#read 4, iclass 30, count 0 2006.201.14:23:28.54#ibcon#about to read 5, iclass 30, count 0 2006.201.14:23:28.54#ibcon#read 5, iclass 30, count 0 2006.201.14:23:28.54#ibcon#about to read 6, iclass 30, count 0 2006.201.14:23:28.54#ibcon#read 6, iclass 30, count 0 2006.201.14:23:28.54#ibcon#end of sib2, iclass 30, count 0 2006.201.14:23:28.54#ibcon#*mode == 0, iclass 30, count 0 2006.201.14:23:28.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.14:23:28.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:23:28.54#ibcon#*before write, iclass 30, count 0 2006.201.14:23:28.54#ibcon#enter sib2, iclass 30, count 0 2006.201.14:23:28.54#ibcon#flushed, iclass 30, count 0 2006.201.14:23:28.54#ibcon#about to write, iclass 30, count 0 2006.201.14:23:28.54#ibcon#wrote, iclass 30, count 0 2006.201.14:23:28.54#ibcon#about to read 3, iclass 30, count 0 2006.201.14:23:28.59#ibcon#read 3, iclass 30, count 0 2006.201.14:23:28.59#ibcon#about to read 4, iclass 30, count 0 2006.201.14:23:28.59#ibcon#read 4, iclass 30, count 0 2006.201.14:23:28.59#ibcon#about to read 5, iclass 30, count 0 2006.201.14:23:28.59#ibcon#read 5, iclass 30, count 0 2006.201.14:23:28.59#ibcon#about to read 6, iclass 30, count 0 2006.201.14:23:28.59#ibcon#read 6, iclass 30, count 0 2006.201.14:23:28.59#ibcon#end of sib2, iclass 30, count 0 2006.201.14:23:28.59#ibcon#*after write, iclass 30, count 0 2006.201.14:23:28.59#ibcon#*before return 0, iclass 30, count 0 2006.201.14:23:28.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:28.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:28.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.14:23:28.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.14:23:28.59$vck44/va=3,8 2006.201.14:23:28.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.14:23:28.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.14:23:28.59#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:28.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:28.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:28.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:28.64#ibcon#enter wrdev, iclass 32, count 2 2006.201.14:23:28.64#ibcon#first serial, iclass 32, count 2 2006.201.14:23:28.64#ibcon#enter sib2, iclass 32, count 2 2006.201.14:23:28.64#ibcon#flushed, iclass 32, count 2 2006.201.14:23:28.64#ibcon#about to write, iclass 32, count 2 2006.201.14:23:28.64#ibcon#wrote, iclass 32, count 2 2006.201.14:23:28.64#ibcon#about to read 3, iclass 32, count 2 2006.201.14:23:28.66#ibcon#read 3, iclass 32, count 2 2006.201.14:23:28.66#ibcon#about to read 4, iclass 32, count 2 2006.201.14:23:28.66#ibcon#read 4, iclass 32, count 2 2006.201.14:23:28.66#ibcon#about to read 5, iclass 32, count 2 2006.201.14:23:28.66#ibcon#read 5, iclass 32, count 2 2006.201.14:23:28.66#ibcon#about to read 6, iclass 32, count 2 2006.201.14:23:28.66#ibcon#read 6, iclass 32, count 2 2006.201.14:23:28.66#ibcon#end of sib2, iclass 32, count 2 2006.201.14:23:28.66#ibcon#*mode == 0, iclass 32, count 2 2006.201.14:23:28.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.14:23:28.66#ibcon#[25=AT03-08\r\n] 2006.201.14:23:28.66#ibcon#*before write, iclass 32, count 2 2006.201.14:23:28.66#ibcon#enter sib2, iclass 32, count 2 2006.201.14:23:28.66#ibcon#flushed, iclass 32, count 2 2006.201.14:23:28.66#ibcon#about to write, iclass 32, count 2 2006.201.14:23:28.66#ibcon#wrote, iclass 32, count 2 2006.201.14:23:28.66#ibcon#about to read 3, iclass 32, count 2 2006.201.14:23:28.69#ibcon#read 3, iclass 32, count 2 2006.201.14:23:28.69#ibcon#about to read 4, iclass 32, count 2 2006.201.14:23:28.69#ibcon#read 4, iclass 32, count 2 2006.201.14:23:28.69#ibcon#about to read 5, iclass 32, count 2 2006.201.14:23:28.69#ibcon#read 5, iclass 32, count 2 2006.201.14:23:28.69#ibcon#about to read 6, iclass 32, count 2 2006.201.14:23:28.69#ibcon#read 6, iclass 32, count 2 2006.201.14:23:28.69#ibcon#end of sib2, iclass 32, count 2 2006.201.14:23:28.69#ibcon#*after write, iclass 32, count 2 2006.201.14:23:28.69#ibcon#*before return 0, iclass 32, count 2 2006.201.14:23:28.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:28.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:28.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.14:23:28.69#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:28.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:28.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:28.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:28.81#ibcon#enter wrdev, iclass 32, count 0 2006.201.14:23:28.81#ibcon#first serial, iclass 32, count 0 2006.201.14:23:28.81#ibcon#enter sib2, iclass 32, count 0 2006.201.14:23:28.81#ibcon#flushed, iclass 32, count 0 2006.201.14:23:28.81#ibcon#about to write, iclass 32, count 0 2006.201.14:23:28.81#ibcon#wrote, iclass 32, count 0 2006.201.14:23:28.81#ibcon#about to read 3, iclass 32, count 0 2006.201.14:23:28.83#ibcon#read 3, iclass 32, count 0 2006.201.14:23:28.83#ibcon#about to read 4, iclass 32, count 0 2006.201.14:23:28.83#ibcon#read 4, iclass 32, count 0 2006.201.14:23:28.83#ibcon#about to read 5, iclass 32, count 0 2006.201.14:23:28.83#ibcon#read 5, iclass 32, count 0 2006.201.14:23:28.83#ibcon#about to read 6, iclass 32, count 0 2006.201.14:23:28.83#ibcon#read 6, iclass 32, count 0 2006.201.14:23:28.83#ibcon#end of sib2, iclass 32, count 0 2006.201.14:23:28.83#ibcon#*mode == 0, iclass 32, count 0 2006.201.14:23:28.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.14:23:28.83#ibcon#[25=USB\r\n] 2006.201.14:23:28.83#ibcon#*before write, iclass 32, count 0 2006.201.14:23:28.83#ibcon#enter sib2, iclass 32, count 0 2006.201.14:23:28.83#ibcon#flushed, iclass 32, count 0 2006.201.14:23:28.83#ibcon#about to write, iclass 32, count 0 2006.201.14:23:28.83#ibcon#wrote, iclass 32, count 0 2006.201.14:23:28.83#ibcon#about to read 3, iclass 32, count 0 2006.201.14:23:28.86#ibcon#read 3, iclass 32, count 0 2006.201.14:23:28.86#ibcon#about to read 4, iclass 32, count 0 2006.201.14:23:28.86#ibcon#read 4, iclass 32, count 0 2006.201.14:23:28.86#ibcon#about to read 5, iclass 32, count 0 2006.201.14:23:28.86#ibcon#read 5, iclass 32, count 0 2006.201.14:23:28.86#ibcon#about to read 6, iclass 32, count 0 2006.201.14:23:28.86#ibcon#read 6, iclass 32, count 0 2006.201.14:23:28.86#ibcon#end of sib2, iclass 32, count 0 2006.201.14:23:28.86#ibcon#*after write, iclass 32, count 0 2006.201.14:23:28.86#ibcon#*before return 0, iclass 32, count 0 2006.201.14:23:28.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:28.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:28.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.14:23:28.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.14:23:28.86$vck44/valo=4,624.99 2006.201.14:23:28.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.14:23:28.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.14:23:28.86#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:28.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:28.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:28.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:28.86#ibcon#enter wrdev, iclass 34, count 0 2006.201.14:23:28.86#ibcon#first serial, iclass 34, count 0 2006.201.14:23:28.86#ibcon#enter sib2, iclass 34, count 0 2006.201.14:23:28.86#ibcon#flushed, iclass 34, count 0 2006.201.14:23:28.86#ibcon#about to write, iclass 34, count 0 2006.201.14:23:28.86#ibcon#wrote, iclass 34, count 0 2006.201.14:23:28.86#ibcon#about to read 3, iclass 34, count 0 2006.201.14:23:28.88#ibcon#read 3, iclass 34, count 0 2006.201.14:23:28.88#ibcon#about to read 4, iclass 34, count 0 2006.201.14:23:28.88#ibcon#read 4, iclass 34, count 0 2006.201.14:23:28.88#ibcon#about to read 5, iclass 34, count 0 2006.201.14:23:28.88#ibcon#read 5, iclass 34, count 0 2006.201.14:23:28.88#ibcon#about to read 6, iclass 34, count 0 2006.201.14:23:28.88#ibcon#read 6, iclass 34, count 0 2006.201.14:23:28.88#ibcon#end of sib2, iclass 34, count 0 2006.201.14:23:28.88#ibcon#*mode == 0, iclass 34, count 0 2006.201.14:23:28.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.14:23:28.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:23:28.88#ibcon#*before write, iclass 34, count 0 2006.201.14:23:28.88#ibcon#enter sib2, iclass 34, count 0 2006.201.14:23:28.88#ibcon#flushed, iclass 34, count 0 2006.201.14:23:28.88#ibcon#about to write, iclass 34, count 0 2006.201.14:23:28.88#ibcon#wrote, iclass 34, count 0 2006.201.14:23:28.88#ibcon#about to read 3, iclass 34, count 0 2006.201.14:23:28.93#ibcon#read 3, iclass 34, count 0 2006.201.14:23:28.93#ibcon#about to read 4, iclass 34, count 0 2006.201.14:23:28.93#ibcon#read 4, iclass 34, count 0 2006.201.14:23:28.93#ibcon#about to read 5, iclass 34, count 0 2006.201.14:23:28.93#ibcon#read 5, iclass 34, count 0 2006.201.14:23:28.93#ibcon#about to read 6, iclass 34, count 0 2006.201.14:23:28.93#ibcon#read 6, iclass 34, count 0 2006.201.14:23:28.93#ibcon#end of sib2, iclass 34, count 0 2006.201.14:23:28.93#ibcon#*after write, iclass 34, count 0 2006.201.14:23:28.93#ibcon#*before return 0, iclass 34, count 0 2006.201.14:23:28.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:28.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:28.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.14:23:28.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.14:23:28.93$vck44/va=4,7 2006.201.14:23:28.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.14:23:28.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.14:23:28.93#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:28.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:28.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:28.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:28.98#ibcon#enter wrdev, iclass 36, count 2 2006.201.14:23:28.98#ibcon#first serial, iclass 36, count 2 2006.201.14:23:28.98#ibcon#enter sib2, iclass 36, count 2 2006.201.14:23:28.98#ibcon#flushed, iclass 36, count 2 2006.201.14:23:28.98#ibcon#about to write, iclass 36, count 2 2006.201.14:23:28.98#ibcon#wrote, iclass 36, count 2 2006.201.14:23:28.98#ibcon#about to read 3, iclass 36, count 2 2006.201.14:23:29.00#ibcon#read 3, iclass 36, count 2 2006.201.14:23:29.00#ibcon#about to read 4, iclass 36, count 2 2006.201.14:23:29.00#ibcon#read 4, iclass 36, count 2 2006.201.14:23:29.00#ibcon#about to read 5, iclass 36, count 2 2006.201.14:23:29.00#ibcon#read 5, iclass 36, count 2 2006.201.14:23:29.00#ibcon#about to read 6, iclass 36, count 2 2006.201.14:23:29.00#ibcon#read 6, iclass 36, count 2 2006.201.14:23:29.00#ibcon#end of sib2, iclass 36, count 2 2006.201.14:23:29.00#ibcon#*mode == 0, iclass 36, count 2 2006.201.14:23:29.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.14:23:29.00#ibcon#[25=AT04-07\r\n] 2006.201.14:23:29.00#ibcon#*before write, iclass 36, count 2 2006.201.14:23:29.00#ibcon#enter sib2, iclass 36, count 2 2006.201.14:23:29.00#ibcon#flushed, iclass 36, count 2 2006.201.14:23:29.00#ibcon#about to write, iclass 36, count 2 2006.201.14:23:29.00#ibcon#wrote, iclass 36, count 2 2006.201.14:23:29.00#ibcon#about to read 3, iclass 36, count 2 2006.201.14:23:29.03#ibcon#read 3, iclass 36, count 2 2006.201.14:23:29.03#ibcon#about to read 4, iclass 36, count 2 2006.201.14:23:29.03#ibcon#read 4, iclass 36, count 2 2006.201.14:23:29.03#ibcon#about to read 5, iclass 36, count 2 2006.201.14:23:29.03#ibcon#read 5, iclass 36, count 2 2006.201.14:23:29.03#ibcon#about to read 6, iclass 36, count 2 2006.201.14:23:29.03#ibcon#read 6, iclass 36, count 2 2006.201.14:23:29.03#ibcon#end of sib2, iclass 36, count 2 2006.201.14:23:29.03#ibcon#*after write, iclass 36, count 2 2006.201.14:23:29.03#ibcon#*before return 0, iclass 36, count 2 2006.201.14:23:29.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:29.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:29.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.14:23:29.03#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:29.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:29.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:29.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:29.15#ibcon#enter wrdev, iclass 36, count 0 2006.201.14:23:29.15#ibcon#first serial, iclass 36, count 0 2006.201.14:23:29.15#ibcon#enter sib2, iclass 36, count 0 2006.201.14:23:29.15#ibcon#flushed, iclass 36, count 0 2006.201.14:23:29.15#ibcon#about to write, iclass 36, count 0 2006.201.14:23:29.15#ibcon#wrote, iclass 36, count 0 2006.201.14:23:29.15#ibcon#about to read 3, iclass 36, count 0 2006.201.14:23:29.17#ibcon#read 3, iclass 36, count 0 2006.201.14:23:29.17#ibcon#about to read 4, iclass 36, count 0 2006.201.14:23:29.17#ibcon#read 4, iclass 36, count 0 2006.201.14:23:29.17#ibcon#about to read 5, iclass 36, count 0 2006.201.14:23:29.17#ibcon#read 5, iclass 36, count 0 2006.201.14:23:29.17#ibcon#about to read 6, iclass 36, count 0 2006.201.14:23:29.17#ibcon#read 6, iclass 36, count 0 2006.201.14:23:29.17#ibcon#end of sib2, iclass 36, count 0 2006.201.14:23:29.17#ibcon#*mode == 0, iclass 36, count 0 2006.201.14:23:29.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.14:23:29.17#ibcon#[25=USB\r\n] 2006.201.14:23:29.17#ibcon#*before write, iclass 36, count 0 2006.201.14:23:29.17#ibcon#enter sib2, iclass 36, count 0 2006.201.14:23:29.17#ibcon#flushed, iclass 36, count 0 2006.201.14:23:29.17#ibcon#about to write, iclass 36, count 0 2006.201.14:23:29.17#ibcon#wrote, iclass 36, count 0 2006.201.14:23:29.17#ibcon#about to read 3, iclass 36, count 0 2006.201.14:23:29.20#ibcon#read 3, iclass 36, count 0 2006.201.14:23:29.20#ibcon#about to read 4, iclass 36, count 0 2006.201.14:23:29.20#ibcon#read 4, iclass 36, count 0 2006.201.14:23:29.20#ibcon#about to read 5, iclass 36, count 0 2006.201.14:23:29.20#ibcon#read 5, iclass 36, count 0 2006.201.14:23:29.20#ibcon#about to read 6, iclass 36, count 0 2006.201.14:23:29.20#ibcon#read 6, iclass 36, count 0 2006.201.14:23:29.20#ibcon#end of sib2, iclass 36, count 0 2006.201.14:23:29.20#ibcon#*after write, iclass 36, count 0 2006.201.14:23:29.20#ibcon#*before return 0, iclass 36, count 0 2006.201.14:23:29.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:29.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:29.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.14:23:29.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.14:23:29.20$vck44/valo=5,734.99 2006.201.14:23:29.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.14:23:29.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.14:23:29.20#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:29.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:29.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:29.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:29.20#ibcon#enter wrdev, iclass 38, count 0 2006.201.14:23:29.20#ibcon#first serial, iclass 38, count 0 2006.201.14:23:29.20#ibcon#enter sib2, iclass 38, count 0 2006.201.14:23:29.20#ibcon#flushed, iclass 38, count 0 2006.201.14:23:29.20#ibcon#about to write, iclass 38, count 0 2006.201.14:23:29.20#ibcon#wrote, iclass 38, count 0 2006.201.14:23:29.20#ibcon#about to read 3, iclass 38, count 0 2006.201.14:23:29.22#ibcon#read 3, iclass 38, count 0 2006.201.14:23:29.22#ibcon#about to read 4, iclass 38, count 0 2006.201.14:23:29.22#ibcon#read 4, iclass 38, count 0 2006.201.14:23:29.22#ibcon#about to read 5, iclass 38, count 0 2006.201.14:23:29.22#ibcon#read 5, iclass 38, count 0 2006.201.14:23:29.22#ibcon#about to read 6, iclass 38, count 0 2006.201.14:23:29.22#ibcon#read 6, iclass 38, count 0 2006.201.14:23:29.22#ibcon#end of sib2, iclass 38, count 0 2006.201.14:23:29.22#ibcon#*mode == 0, iclass 38, count 0 2006.201.14:23:29.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.14:23:29.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:23:29.22#ibcon#*before write, iclass 38, count 0 2006.201.14:23:29.22#ibcon#enter sib2, iclass 38, count 0 2006.201.14:23:29.22#ibcon#flushed, iclass 38, count 0 2006.201.14:23:29.22#ibcon#about to write, iclass 38, count 0 2006.201.14:23:29.22#ibcon#wrote, iclass 38, count 0 2006.201.14:23:29.22#ibcon#about to read 3, iclass 38, count 0 2006.201.14:23:29.26#ibcon#read 3, iclass 38, count 0 2006.201.14:23:29.26#ibcon#about to read 4, iclass 38, count 0 2006.201.14:23:29.26#ibcon#read 4, iclass 38, count 0 2006.201.14:23:29.26#ibcon#about to read 5, iclass 38, count 0 2006.201.14:23:29.26#ibcon#read 5, iclass 38, count 0 2006.201.14:23:29.26#ibcon#about to read 6, iclass 38, count 0 2006.201.14:23:29.26#ibcon#read 6, iclass 38, count 0 2006.201.14:23:29.26#ibcon#end of sib2, iclass 38, count 0 2006.201.14:23:29.26#ibcon#*after write, iclass 38, count 0 2006.201.14:23:29.26#ibcon#*before return 0, iclass 38, count 0 2006.201.14:23:29.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:29.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:29.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.14:23:29.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.14:23:29.26$vck44/va=5,4 2006.201.14:23:29.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.14:23:29.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.14:23:29.26#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:29.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:29.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:29.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:29.32#ibcon#enter wrdev, iclass 40, count 2 2006.201.14:23:29.32#ibcon#first serial, iclass 40, count 2 2006.201.14:23:29.32#ibcon#enter sib2, iclass 40, count 2 2006.201.14:23:29.32#ibcon#flushed, iclass 40, count 2 2006.201.14:23:29.32#ibcon#about to write, iclass 40, count 2 2006.201.14:23:29.32#ibcon#wrote, iclass 40, count 2 2006.201.14:23:29.32#ibcon#about to read 3, iclass 40, count 2 2006.201.14:23:29.34#ibcon#read 3, iclass 40, count 2 2006.201.14:23:29.34#ibcon#about to read 4, iclass 40, count 2 2006.201.14:23:29.34#ibcon#read 4, iclass 40, count 2 2006.201.14:23:29.34#ibcon#about to read 5, iclass 40, count 2 2006.201.14:23:29.34#ibcon#read 5, iclass 40, count 2 2006.201.14:23:29.34#ibcon#about to read 6, iclass 40, count 2 2006.201.14:23:29.34#ibcon#read 6, iclass 40, count 2 2006.201.14:23:29.34#ibcon#end of sib2, iclass 40, count 2 2006.201.14:23:29.34#ibcon#*mode == 0, iclass 40, count 2 2006.201.14:23:29.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.14:23:29.34#ibcon#[25=AT05-04\r\n] 2006.201.14:23:29.34#ibcon#*before write, iclass 40, count 2 2006.201.14:23:29.34#ibcon#enter sib2, iclass 40, count 2 2006.201.14:23:29.34#ibcon#flushed, iclass 40, count 2 2006.201.14:23:29.34#ibcon#about to write, iclass 40, count 2 2006.201.14:23:29.34#ibcon#wrote, iclass 40, count 2 2006.201.14:23:29.34#ibcon#about to read 3, iclass 40, count 2 2006.201.14:23:29.37#ibcon#read 3, iclass 40, count 2 2006.201.14:23:29.37#ibcon#about to read 4, iclass 40, count 2 2006.201.14:23:29.37#ibcon#read 4, iclass 40, count 2 2006.201.14:23:29.37#ibcon#about to read 5, iclass 40, count 2 2006.201.14:23:29.37#ibcon#read 5, iclass 40, count 2 2006.201.14:23:29.37#ibcon#about to read 6, iclass 40, count 2 2006.201.14:23:29.37#ibcon#read 6, iclass 40, count 2 2006.201.14:23:29.37#ibcon#end of sib2, iclass 40, count 2 2006.201.14:23:29.37#ibcon#*after write, iclass 40, count 2 2006.201.14:23:29.37#ibcon#*before return 0, iclass 40, count 2 2006.201.14:23:29.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:29.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:29.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.14:23:29.37#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:29.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:29.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:29.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:29.49#ibcon#enter wrdev, iclass 40, count 0 2006.201.14:23:29.49#ibcon#first serial, iclass 40, count 0 2006.201.14:23:29.49#ibcon#enter sib2, iclass 40, count 0 2006.201.14:23:29.49#ibcon#flushed, iclass 40, count 0 2006.201.14:23:29.49#ibcon#about to write, iclass 40, count 0 2006.201.14:23:29.49#ibcon#wrote, iclass 40, count 0 2006.201.14:23:29.49#ibcon#about to read 3, iclass 40, count 0 2006.201.14:23:29.51#ibcon#read 3, iclass 40, count 0 2006.201.14:23:29.51#ibcon#about to read 4, iclass 40, count 0 2006.201.14:23:29.51#ibcon#read 4, iclass 40, count 0 2006.201.14:23:29.51#ibcon#about to read 5, iclass 40, count 0 2006.201.14:23:29.51#ibcon#read 5, iclass 40, count 0 2006.201.14:23:29.51#ibcon#about to read 6, iclass 40, count 0 2006.201.14:23:29.51#ibcon#read 6, iclass 40, count 0 2006.201.14:23:29.51#ibcon#end of sib2, iclass 40, count 0 2006.201.14:23:29.51#ibcon#*mode == 0, iclass 40, count 0 2006.201.14:23:29.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.14:23:29.51#ibcon#[25=USB\r\n] 2006.201.14:23:29.51#ibcon#*before write, iclass 40, count 0 2006.201.14:23:29.51#ibcon#enter sib2, iclass 40, count 0 2006.201.14:23:29.51#ibcon#flushed, iclass 40, count 0 2006.201.14:23:29.51#ibcon#about to write, iclass 40, count 0 2006.201.14:23:29.51#ibcon#wrote, iclass 40, count 0 2006.201.14:23:29.51#ibcon#about to read 3, iclass 40, count 0 2006.201.14:23:29.54#ibcon#read 3, iclass 40, count 0 2006.201.14:23:29.54#ibcon#about to read 4, iclass 40, count 0 2006.201.14:23:29.54#ibcon#read 4, iclass 40, count 0 2006.201.14:23:29.54#ibcon#about to read 5, iclass 40, count 0 2006.201.14:23:29.54#ibcon#read 5, iclass 40, count 0 2006.201.14:23:29.54#ibcon#about to read 6, iclass 40, count 0 2006.201.14:23:29.54#ibcon#read 6, iclass 40, count 0 2006.201.14:23:29.54#ibcon#end of sib2, iclass 40, count 0 2006.201.14:23:29.54#ibcon#*after write, iclass 40, count 0 2006.201.14:23:29.54#ibcon#*before return 0, iclass 40, count 0 2006.201.14:23:29.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:29.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:29.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.14:23:29.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.14:23:29.54$vck44/valo=6,814.99 2006.201.14:23:29.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.14:23:29.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.14:23:29.54#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:29.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:29.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:29.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:29.54#ibcon#enter wrdev, iclass 4, count 0 2006.201.14:23:29.54#ibcon#first serial, iclass 4, count 0 2006.201.14:23:29.54#ibcon#enter sib2, iclass 4, count 0 2006.201.14:23:29.54#ibcon#flushed, iclass 4, count 0 2006.201.14:23:29.54#ibcon#about to write, iclass 4, count 0 2006.201.14:23:29.54#ibcon#wrote, iclass 4, count 0 2006.201.14:23:29.54#ibcon#about to read 3, iclass 4, count 0 2006.201.14:23:29.56#ibcon#read 3, iclass 4, count 0 2006.201.14:23:29.56#ibcon#about to read 4, iclass 4, count 0 2006.201.14:23:29.56#ibcon#read 4, iclass 4, count 0 2006.201.14:23:29.56#ibcon#about to read 5, iclass 4, count 0 2006.201.14:23:29.56#ibcon#read 5, iclass 4, count 0 2006.201.14:23:29.56#ibcon#about to read 6, iclass 4, count 0 2006.201.14:23:29.56#ibcon#read 6, iclass 4, count 0 2006.201.14:23:29.56#ibcon#end of sib2, iclass 4, count 0 2006.201.14:23:29.56#ibcon#*mode == 0, iclass 4, count 0 2006.201.14:23:29.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.14:23:29.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:23:29.56#ibcon#*before write, iclass 4, count 0 2006.201.14:23:29.56#ibcon#enter sib2, iclass 4, count 0 2006.201.14:23:29.56#ibcon#flushed, iclass 4, count 0 2006.201.14:23:29.56#ibcon#about to write, iclass 4, count 0 2006.201.14:23:29.56#ibcon#wrote, iclass 4, count 0 2006.201.14:23:29.56#ibcon#about to read 3, iclass 4, count 0 2006.201.14:23:29.60#ibcon#read 3, iclass 4, count 0 2006.201.14:23:29.60#ibcon#about to read 4, iclass 4, count 0 2006.201.14:23:29.60#ibcon#read 4, iclass 4, count 0 2006.201.14:23:29.60#ibcon#about to read 5, iclass 4, count 0 2006.201.14:23:29.60#ibcon#read 5, iclass 4, count 0 2006.201.14:23:29.60#ibcon#about to read 6, iclass 4, count 0 2006.201.14:23:29.60#ibcon#read 6, iclass 4, count 0 2006.201.14:23:29.60#ibcon#end of sib2, iclass 4, count 0 2006.201.14:23:29.60#ibcon#*after write, iclass 4, count 0 2006.201.14:23:29.60#ibcon#*before return 0, iclass 4, count 0 2006.201.14:23:29.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:29.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:29.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.14:23:29.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.14:23:29.60$vck44/va=6,5 2006.201.14:23:29.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.14:23:29.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.14:23:29.60#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:29.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:29.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:29.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:29.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.14:23:29.66#ibcon#first serial, iclass 6, count 2 2006.201.14:23:29.66#ibcon#enter sib2, iclass 6, count 2 2006.201.14:23:29.66#ibcon#flushed, iclass 6, count 2 2006.201.14:23:29.66#ibcon#about to write, iclass 6, count 2 2006.201.14:23:29.66#ibcon#wrote, iclass 6, count 2 2006.201.14:23:29.66#ibcon#about to read 3, iclass 6, count 2 2006.201.14:23:29.68#ibcon#read 3, iclass 6, count 2 2006.201.14:23:29.68#ibcon#about to read 4, iclass 6, count 2 2006.201.14:23:29.68#ibcon#read 4, iclass 6, count 2 2006.201.14:23:29.68#ibcon#about to read 5, iclass 6, count 2 2006.201.14:23:29.68#ibcon#read 5, iclass 6, count 2 2006.201.14:23:29.68#ibcon#about to read 6, iclass 6, count 2 2006.201.14:23:29.68#ibcon#read 6, iclass 6, count 2 2006.201.14:23:29.68#ibcon#end of sib2, iclass 6, count 2 2006.201.14:23:29.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.14:23:29.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.14:23:29.68#ibcon#[25=AT06-05\r\n] 2006.201.14:23:29.68#ibcon#*before write, iclass 6, count 2 2006.201.14:23:29.68#ibcon#enter sib2, iclass 6, count 2 2006.201.14:23:29.68#ibcon#flushed, iclass 6, count 2 2006.201.14:23:29.68#ibcon#about to write, iclass 6, count 2 2006.201.14:23:29.68#ibcon#wrote, iclass 6, count 2 2006.201.14:23:29.68#ibcon#about to read 3, iclass 6, count 2 2006.201.14:23:29.71#ibcon#read 3, iclass 6, count 2 2006.201.14:23:29.71#ibcon#about to read 4, iclass 6, count 2 2006.201.14:23:29.71#ibcon#read 4, iclass 6, count 2 2006.201.14:23:29.71#ibcon#about to read 5, iclass 6, count 2 2006.201.14:23:29.71#ibcon#read 5, iclass 6, count 2 2006.201.14:23:29.71#ibcon#about to read 6, iclass 6, count 2 2006.201.14:23:29.71#ibcon#read 6, iclass 6, count 2 2006.201.14:23:29.71#ibcon#end of sib2, iclass 6, count 2 2006.201.14:23:29.71#ibcon#*after write, iclass 6, count 2 2006.201.14:23:29.71#ibcon#*before return 0, iclass 6, count 2 2006.201.14:23:29.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:29.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:29.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.14:23:29.71#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:29.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:29.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:29.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:29.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.14:23:29.83#ibcon#first serial, iclass 6, count 0 2006.201.14:23:29.83#ibcon#enter sib2, iclass 6, count 0 2006.201.14:23:29.83#ibcon#flushed, iclass 6, count 0 2006.201.14:23:29.83#ibcon#about to write, iclass 6, count 0 2006.201.14:23:29.83#ibcon#wrote, iclass 6, count 0 2006.201.14:23:29.83#ibcon#about to read 3, iclass 6, count 0 2006.201.14:23:29.85#ibcon#read 3, iclass 6, count 0 2006.201.14:23:29.85#ibcon#about to read 4, iclass 6, count 0 2006.201.14:23:29.85#ibcon#read 4, iclass 6, count 0 2006.201.14:23:29.85#ibcon#about to read 5, iclass 6, count 0 2006.201.14:23:29.85#ibcon#read 5, iclass 6, count 0 2006.201.14:23:29.85#ibcon#about to read 6, iclass 6, count 0 2006.201.14:23:29.85#ibcon#read 6, iclass 6, count 0 2006.201.14:23:29.85#ibcon#end of sib2, iclass 6, count 0 2006.201.14:23:29.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.14:23:29.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.14:23:29.85#ibcon#[25=USB\r\n] 2006.201.14:23:29.85#ibcon#*before write, iclass 6, count 0 2006.201.14:23:29.85#ibcon#enter sib2, iclass 6, count 0 2006.201.14:23:29.85#ibcon#flushed, iclass 6, count 0 2006.201.14:23:29.85#ibcon#about to write, iclass 6, count 0 2006.201.14:23:29.85#ibcon#wrote, iclass 6, count 0 2006.201.14:23:29.85#ibcon#about to read 3, iclass 6, count 0 2006.201.14:23:29.88#ibcon#read 3, iclass 6, count 0 2006.201.14:23:29.88#ibcon#about to read 4, iclass 6, count 0 2006.201.14:23:29.88#ibcon#read 4, iclass 6, count 0 2006.201.14:23:29.88#ibcon#about to read 5, iclass 6, count 0 2006.201.14:23:29.88#ibcon#read 5, iclass 6, count 0 2006.201.14:23:29.88#ibcon#about to read 6, iclass 6, count 0 2006.201.14:23:29.88#ibcon#read 6, iclass 6, count 0 2006.201.14:23:29.88#ibcon#end of sib2, iclass 6, count 0 2006.201.14:23:29.88#ibcon#*after write, iclass 6, count 0 2006.201.14:23:29.88#ibcon#*before return 0, iclass 6, count 0 2006.201.14:23:29.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:29.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:29.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.14:23:29.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.14:23:29.88$vck44/valo=7,864.99 2006.201.14:23:29.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.14:23:29.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.14:23:29.88#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:29.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:29.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:29.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:29.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.14:23:29.88#ibcon#first serial, iclass 10, count 0 2006.201.14:23:29.88#ibcon#enter sib2, iclass 10, count 0 2006.201.14:23:29.88#ibcon#flushed, iclass 10, count 0 2006.201.14:23:29.88#ibcon#about to write, iclass 10, count 0 2006.201.14:23:29.88#ibcon#wrote, iclass 10, count 0 2006.201.14:23:29.88#ibcon#about to read 3, iclass 10, count 0 2006.201.14:23:29.90#ibcon#read 3, iclass 10, count 0 2006.201.14:23:29.90#ibcon#about to read 4, iclass 10, count 0 2006.201.14:23:29.90#ibcon#read 4, iclass 10, count 0 2006.201.14:23:29.90#ibcon#about to read 5, iclass 10, count 0 2006.201.14:23:29.90#ibcon#read 5, iclass 10, count 0 2006.201.14:23:29.90#ibcon#about to read 6, iclass 10, count 0 2006.201.14:23:29.90#ibcon#read 6, iclass 10, count 0 2006.201.14:23:29.90#ibcon#end of sib2, iclass 10, count 0 2006.201.14:23:29.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.14:23:29.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.14:23:29.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:23:29.90#ibcon#*before write, iclass 10, count 0 2006.201.14:23:29.90#ibcon#enter sib2, iclass 10, count 0 2006.201.14:23:29.90#ibcon#flushed, iclass 10, count 0 2006.201.14:23:29.90#ibcon#about to write, iclass 10, count 0 2006.201.14:23:29.90#ibcon#wrote, iclass 10, count 0 2006.201.14:23:29.90#ibcon#about to read 3, iclass 10, count 0 2006.201.14:23:29.94#ibcon#read 3, iclass 10, count 0 2006.201.14:23:29.94#ibcon#about to read 4, iclass 10, count 0 2006.201.14:23:29.94#ibcon#read 4, iclass 10, count 0 2006.201.14:23:29.94#ibcon#about to read 5, iclass 10, count 0 2006.201.14:23:29.94#ibcon#read 5, iclass 10, count 0 2006.201.14:23:29.94#ibcon#about to read 6, iclass 10, count 0 2006.201.14:23:29.94#ibcon#read 6, iclass 10, count 0 2006.201.14:23:29.94#ibcon#end of sib2, iclass 10, count 0 2006.201.14:23:29.94#ibcon#*after write, iclass 10, count 0 2006.201.14:23:29.94#ibcon#*before return 0, iclass 10, count 0 2006.201.14:23:29.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:29.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:29.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.14:23:29.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.14:23:29.94$vck44/va=7,5 2006.201.14:23:29.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.14:23:29.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.14:23:29.94#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:29.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:30.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:30.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:30.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.14:23:30.00#ibcon#first serial, iclass 12, count 2 2006.201.14:23:30.00#ibcon#enter sib2, iclass 12, count 2 2006.201.14:23:30.00#ibcon#flushed, iclass 12, count 2 2006.201.14:23:30.00#ibcon#about to write, iclass 12, count 2 2006.201.14:23:30.00#ibcon#wrote, iclass 12, count 2 2006.201.14:23:30.00#ibcon#about to read 3, iclass 12, count 2 2006.201.14:23:30.02#ibcon#read 3, iclass 12, count 2 2006.201.14:23:30.02#ibcon#about to read 4, iclass 12, count 2 2006.201.14:23:30.02#ibcon#read 4, iclass 12, count 2 2006.201.14:23:30.02#ibcon#about to read 5, iclass 12, count 2 2006.201.14:23:30.02#ibcon#read 5, iclass 12, count 2 2006.201.14:23:30.02#ibcon#about to read 6, iclass 12, count 2 2006.201.14:23:30.02#ibcon#read 6, iclass 12, count 2 2006.201.14:23:30.02#ibcon#end of sib2, iclass 12, count 2 2006.201.14:23:30.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.14:23:30.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.14:23:30.02#ibcon#[25=AT07-05\r\n] 2006.201.14:23:30.02#ibcon#*before write, iclass 12, count 2 2006.201.14:23:30.02#ibcon#enter sib2, iclass 12, count 2 2006.201.14:23:30.02#ibcon#flushed, iclass 12, count 2 2006.201.14:23:30.02#ibcon#about to write, iclass 12, count 2 2006.201.14:23:30.02#ibcon#wrote, iclass 12, count 2 2006.201.14:23:30.02#ibcon#about to read 3, iclass 12, count 2 2006.201.14:23:30.05#ibcon#read 3, iclass 12, count 2 2006.201.14:23:30.05#ibcon#about to read 4, iclass 12, count 2 2006.201.14:23:30.05#ibcon#read 4, iclass 12, count 2 2006.201.14:23:30.05#ibcon#about to read 5, iclass 12, count 2 2006.201.14:23:30.05#ibcon#read 5, iclass 12, count 2 2006.201.14:23:30.05#ibcon#about to read 6, iclass 12, count 2 2006.201.14:23:30.05#ibcon#read 6, iclass 12, count 2 2006.201.14:23:30.05#ibcon#end of sib2, iclass 12, count 2 2006.201.14:23:30.05#ibcon#*after write, iclass 12, count 2 2006.201.14:23:30.05#ibcon#*before return 0, iclass 12, count 2 2006.201.14:23:30.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:30.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:30.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.14:23:30.05#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:30.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:30.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:30.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:30.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.14:23:30.17#ibcon#first serial, iclass 12, count 0 2006.201.14:23:30.17#ibcon#enter sib2, iclass 12, count 0 2006.201.14:23:30.17#ibcon#flushed, iclass 12, count 0 2006.201.14:23:30.17#ibcon#about to write, iclass 12, count 0 2006.201.14:23:30.17#ibcon#wrote, iclass 12, count 0 2006.201.14:23:30.17#ibcon#about to read 3, iclass 12, count 0 2006.201.14:23:30.19#ibcon#read 3, iclass 12, count 0 2006.201.14:23:30.20#ibcon#about to read 4, iclass 12, count 0 2006.201.14:23:30.20#ibcon#read 4, iclass 12, count 0 2006.201.14:23:30.20#ibcon#about to read 5, iclass 12, count 0 2006.201.14:23:30.20#ibcon#read 5, iclass 12, count 0 2006.201.14:23:30.20#ibcon#about to read 6, iclass 12, count 0 2006.201.14:23:30.20#ibcon#read 6, iclass 12, count 0 2006.201.14:23:30.20#ibcon#end of sib2, iclass 12, count 0 2006.201.14:23:30.20#ibcon#*mode == 0, iclass 12, count 0 2006.201.14:23:30.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.14:23:30.20#ibcon#[25=USB\r\n] 2006.201.14:23:30.20#ibcon#*before write, iclass 12, count 0 2006.201.14:23:30.20#ibcon#enter sib2, iclass 12, count 0 2006.201.14:23:30.20#ibcon#flushed, iclass 12, count 0 2006.201.14:23:30.20#ibcon#about to write, iclass 12, count 0 2006.201.14:23:30.20#ibcon#wrote, iclass 12, count 0 2006.201.14:23:30.20#ibcon#about to read 3, iclass 12, count 0 2006.201.14:23:30.23#ibcon#read 3, iclass 12, count 0 2006.201.14:23:30.23#ibcon#about to read 4, iclass 12, count 0 2006.201.14:23:30.23#ibcon#read 4, iclass 12, count 0 2006.201.14:23:30.23#ibcon#about to read 5, iclass 12, count 0 2006.201.14:23:30.23#ibcon#read 5, iclass 12, count 0 2006.201.14:23:30.23#ibcon#about to read 6, iclass 12, count 0 2006.201.14:23:30.23#ibcon#read 6, iclass 12, count 0 2006.201.14:23:30.23#ibcon#end of sib2, iclass 12, count 0 2006.201.14:23:30.23#ibcon#*after write, iclass 12, count 0 2006.201.14:23:30.23#ibcon#*before return 0, iclass 12, count 0 2006.201.14:23:30.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:30.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:30.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.14:23:30.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.14:23:30.23$vck44/valo=8,884.99 2006.201.14:23:30.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.14:23:30.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.14:23:30.23#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:30.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:30.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:30.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:30.23#ibcon#enter wrdev, iclass 14, count 0 2006.201.14:23:30.23#ibcon#first serial, iclass 14, count 0 2006.201.14:23:30.23#ibcon#enter sib2, iclass 14, count 0 2006.201.14:23:30.23#ibcon#flushed, iclass 14, count 0 2006.201.14:23:30.23#ibcon#about to write, iclass 14, count 0 2006.201.14:23:30.23#ibcon#wrote, iclass 14, count 0 2006.201.14:23:30.23#ibcon#about to read 3, iclass 14, count 0 2006.201.14:23:30.25#ibcon#read 3, iclass 14, count 0 2006.201.14:23:30.25#ibcon#about to read 4, iclass 14, count 0 2006.201.14:23:30.25#ibcon#read 4, iclass 14, count 0 2006.201.14:23:30.25#ibcon#about to read 5, iclass 14, count 0 2006.201.14:23:30.25#ibcon#read 5, iclass 14, count 0 2006.201.14:23:30.25#ibcon#about to read 6, iclass 14, count 0 2006.201.14:23:30.25#ibcon#read 6, iclass 14, count 0 2006.201.14:23:30.25#ibcon#end of sib2, iclass 14, count 0 2006.201.14:23:30.25#ibcon#*mode == 0, iclass 14, count 0 2006.201.14:23:30.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.14:23:30.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:23:30.25#ibcon#*before write, iclass 14, count 0 2006.201.14:23:30.25#ibcon#enter sib2, iclass 14, count 0 2006.201.14:23:30.25#ibcon#flushed, iclass 14, count 0 2006.201.14:23:30.25#ibcon#about to write, iclass 14, count 0 2006.201.14:23:30.25#ibcon#wrote, iclass 14, count 0 2006.201.14:23:30.25#ibcon#about to read 3, iclass 14, count 0 2006.201.14:23:30.29#ibcon#read 3, iclass 14, count 0 2006.201.14:23:30.29#ibcon#about to read 4, iclass 14, count 0 2006.201.14:23:30.29#ibcon#read 4, iclass 14, count 0 2006.201.14:23:30.29#ibcon#about to read 5, iclass 14, count 0 2006.201.14:23:30.29#ibcon#read 5, iclass 14, count 0 2006.201.14:23:30.29#ibcon#about to read 6, iclass 14, count 0 2006.201.14:23:30.29#ibcon#read 6, iclass 14, count 0 2006.201.14:23:30.29#ibcon#end of sib2, iclass 14, count 0 2006.201.14:23:30.29#ibcon#*after write, iclass 14, count 0 2006.201.14:23:30.29#ibcon#*before return 0, iclass 14, count 0 2006.201.14:23:30.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:30.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:30.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.14:23:30.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.14:23:30.29$vck44/va=8,4 2006.201.14:23:30.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.14:23:30.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.14:23:30.29#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:30.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:23:30.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:23:30.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:23:30.35#ibcon#enter wrdev, iclass 16, count 2 2006.201.14:23:30.35#ibcon#first serial, iclass 16, count 2 2006.201.14:23:30.35#ibcon#enter sib2, iclass 16, count 2 2006.201.14:23:30.35#ibcon#flushed, iclass 16, count 2 2006.201.14:23:30.35#ibcon#about to write, iclass 16, count 2 2006.201.14:23:30.35#ibcon#wrote, iclass 16, count 2 2006.201.14:23:30.35#ibcon#about to read 3, iclass 16, count 2 2006.201.14:23:30.37#ibcon#read 3, iclass 16, count 2 2006.201.14:23:30.37#ibcon#about to read 4, iclass 16, count 2 2006.201.14:23:30.37#ibcon#read 4, iclass 16, count 2 2006.201.14:23:30.37#ibcon#about to read 5, iclass 16, count 2 2006.201.14:23:30.37#ibcon#read 5, iclass 16, count 2 2006.201.14:23:30.37#ibcon#about to read 6, iclass 16, count 2 2006.201.14:23:30.37#ibcon#read 6, iclass 16, count 2 2006.201.14:23:30.37#ibcon#end of sib2, iclass 16, count 2 2006.201.14:23:30.37#ibcon#*mode == 0, iclass 16, count 2 2006.201.14:23:30.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.14:23:30.37#ibcon#[25=AT08-04\r\n] 2006.201.14:23:30.37#ibcon#*before write, iclass 16, count 2 2006.201.14:23:30.37#ibcon#enter sib2, iclass 16, count 2 2006.201.14:23:30.37#ibcon#flushed, iclass 16, count 2 2006.201.14:23:30.37#ibcon#about to write, iclass 16, count 2 2006.201.14:23:30.37#ibcon#wrote, iclass 16, count 2 2006.201.14:23:30.37#ibcon#about to read 3, iclass 16, count 2 2006.201.14:23:30.40#ibcon#read 3, iclass 16, count 2 2006.201.14:23:30.40#ibcon#about to read 4, iclass 16, count 2 2006.201.14:23:30.40#ibcon#read 4, iclass 16, count 2 2006.201.14:23:30.40#ibcon#about to read 5, iclass 16, count 2 2006.201.14:23:30.40#ibcon#read 5, iclass 16, count 2 2006.201.14:23:30.40#ibcon#about to read 6, iclass 16, count 2 2006.201.14:23:30.40#ibcon#read 6, iclass 16, count 2 2006.201.14:23:30.40#ibcon#end of sib2, iclass 16, count 2 2006.201.14:23:30.40#ibcon#*after write, iclass 16, count 2 2006.201.14:23:30.40#ibcon#*before return 0, iclass 16, count 2 2006.201.14:23:30.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:23:30.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.14:23:30.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.14:23:30.40#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:30.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:23:30.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:23:30.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:23:30.52#ibcon#enter wrdev, iclass 16, count 0 2006.201.14:23:30.52#ibcon#first serial, iclass 16, count 0 2006.201.14:23:30.52#ibcon#enter sib2, iclass 16, count 0 2006.201.14:23:30.52#ibcon#flushed, iclass 16, count 0 2006.201.14:23:30.52#ibcon#about to write, iclass 16, count 0 2006.201.14:23:30.52#ibcon#wrote, iclass 16, count 0 2006.201.14:23:30.52#ibcon#about to read 3, iclass 16, count 0 2006.201.14:23:30.54#ibcon#read 3, iclass 16, count 0 2006.201.14:23:30.54#ibcon#about to read 4, iclass 16, count 0 2006.201.14:23:30.54#ibcon#read 4, iclass 16, count 0 2006.201.14:23:30.54#ibcon#about to read 5, iclass 16, count 0 2006.201.14:23:30.54#ibcon#read 5, iclass 16, count 0 2006.201.14:23:30.54#ibcon#about to read 6, iclass 16, count 0 2006.201.14:23:30.54#ibcon#read 6, iclass 16, count 0 2006.201.14:23:30.54#ibcon#end of sib2, iclass 16, count 0 2006.201.14:23:30.54#ibcon#*mode == 0, iclass 16, count 0 2006.201.14:23:30.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.14:23:30.54#ibcon#[25=USB\r\n] 2006.201.14:23:30.54#ibcon#*before write, iclass 16, count 0 2006.201.14:23:30.54#ibcon#enter sib2, iclass 16, count 0 2006.201.14:23:30.54#ibcon#flushed, iclass 16, count 0 2006.201.14:23:30.54#ibcon#about to write, iclass 16, count 0 2006.201.14:23:30.54#ibcon#wrote, iclass 16, count 0 2006.201.14:23:30.54#ibcon#about to read 3, iclass 16, count 0 2006.201.14:23:30.57#ibcon#read 3, iclass 16, count 0 2006.201.14:23:30.57#ibcon#about to read 4, iclass 16, count 0 2006.201.14:23:30.57#ibcon#read 4, iclass 16, count 0 2006.201.14:23:30.57#ibcon#about to read 5, iclass 16, count 0 2006.201.14:23:30.57#ibcon#read 5, iclass 16, count 0 2006.201.14:23:30.57#ibcon#about to read 6, iclass 16, count 0 2006.201.14:23:30.57#ibcon#read 6, iclass 16, count 0 2006.201.14:23:30.57#ibcon#end of sib2, iclass 16, count 0 2006.201.14:23:30.57#ibcon#*after write, iclass 16, count 0 2006.201.14:23:30.57#ibcon#*before return 0, iclass 16, count 0 2006.201.14:23:30.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:23:30.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.14:23:30.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.14:23:30.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.14:23:30.57$vck44/vblo=1,629.99 2006.201.14:23:30.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.14:23:30.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.14:23:30.57#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:30.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:23:30.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:23:30.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:23:30.57#ibcon#enter wrdev, iclass 18, count 0 2006.201.14:23:30.57#ibcon#first serial, iclass 18, count 0 2006.201.14:23:30.57#ibcon#enter sib2, iclass 18, count 0 2006.201.14:23:30.57#ibcon#flushed, iclass 18, count 0 2006.201.14:23:30.57#ibcon#about to write, iclass 18, count 0 2006.201.14:23:30.57#ibcon#wrote, iclass 18, count 0 2006.201.14:23:30.57#ibcon#about to read 3, iclass 18, count 0 2006.201.14:23:30.59#ibcon#read 3, iclass 18, count 0 2006.201.14:23:30.59#ibcon#about to read 4, iclass 18, count 0 2006.201.14:23:30.59#ibcon#read 4, iclass 18, count 0 2006.201.14:23:30.59#ibcon#about to read 5, iclass 18, count 0 2006.201.14:23:30.59#ibcon#read 5, iclass 18, count 0 2006.201.14:23:30.59#ibcon#about to read 6, iclass 18, count 0 2006.201.14:23:30.59#ibcon#read 6, iclass 18, count 0 2006.201.14:23:30.59#ibcon#end of sib2, iclass 18, count 0 2006.201.14:23:30.59#ibcon#*mode == 0, iclass 18, count 0 2006.201.14:23:30.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.14:23:30.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:23:30.59#ibcon#*before write, iclass 18, count 0 2006.201.14:23:30.59#ibcon#enter sib2, iclass 18, count 0 2006.201.14:23:30.59#ibcon#flushed, iclass 18, count 0 2006.201.14:23:30.59#ibcon#about to write, iclass 18, count 0 2006.201.14:23:30.59#ibcon#wrote, iclass 18, count 0 2006.201.14:23:30.59#ibcon#about to read 3, iclass 18, count 0 2006.201.14:23:30.63#ibcon#read 3, iclass 18, count 0 2006.201.14:23:30.63#ibcon#about to read 4, iclass 18, count 0 2006.201.14:23:30.63#ibcon#read 4, iclass 18, count 0 2006.201.14:23:30.63#ibcon#about to read 5, iclass 18, count 0 2006.201.14:23:30.63#ibcon#read 5, iclass 18, count 0 2006.201.14:23:30.63#ibcon#about to read 6, iclass 18, count 0 2006.201.14:23:30.63#ibcon#read 6, iclass 18, count 0 2006.201.14:23:30.63#ibcon#end of sib2, iclass 18, count 0 2006.201.14:23:30.63#ibcon#*after write, iclass 18, count 0 2006.201.14:23:30.63#ibcon#*before return 0, iclass 18, count 0 2006.201.14:23:30.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:23:30.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.14:23:30.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.14:23:30.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.14:23:30.63$vck44/vb=1,4 2006.201.14:23:30.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.14:23:30.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.14:23:30.63#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:30.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:23:30.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:23:30.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:23:30.63#ibcon#enter wrdev, iclass 20, count 2 2006.201.14:23:30.63#ibcon#first serial, iclass 20, count 2 2006.201.14:23:30.63#ibcon#enter sib2, iclass 20, count 2 2006.201.14:23:30.63#ibcon#flushed, iclass 20, count 2 2006.201.14:23:30.63#ibcon#about to write, iclass 20, count 2 2006.201.14:23:30.63#ibcon#wrote, iclass 20, count 2 2006.201.14:23:30.63#ibcon#about to read 3, iclass 20, count 2 2006.201.14:23:30.65#ibcon#read 3, iclass 20, count 2 2006.201.14:23:30.65#ibcon#about to read 4, iclass 20, count 2 2006.201.14:23:30.65#ibcon#read 4, iclass 20, count 2 2006.201.14:23:30.65#ibcon#about to read 5, iclass 20, count 2 2006.201.14:23:30.65#ibcon#read 5, iclass 20, count 2 2006.201.14:23:30.65#ibcon#about to read 6, iclass 20, count 2 2006.201.14:23:30.65#ibcon#read 6, iclass 20, count 2 2006.201.14:23:30.65#ibcon#end of sib2, iclass 20, count 2 2006.201.14:23:30.65#ibcon#*mode == 0, iclass 20, count 2 2006.201.14:23:30.65#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.14:23:30.65#ibcon#[27=AT01-04\r\n] 2006.201.14:23:30.65#ibcon#*before write, iclass 20, count 2 2006.201.14:23:30.65#ibcon#enter sib2, iclass 20, count 2 2006.201.14:23:30.65#ibcon#flushed, iclass 20, count 2 2006.201.14:23:30.65#ibcon#about to write, iclass 20, count 2 2006.201.14:23:30.65#ibcon#wrote, iclass 20, count 2 2006.201.14:23:30.65#ibcon#about to read 3, iclass 20, count 2 2006.201.14:23:30.68#ibcon#read 3, iclass 20, count 2 2006.201.14:23:30.68#ibcon#about to read 4, iclass 20, count 2 2006.201.14:23:30.68#ibcon#read 4, iclass 20, count 2 2006.201.14:23:30.68#ibcon#about to read 5, iclass 20, count 2 2006.201.14:23:30.68#ibcon#read 5, iclass 20, count 2 2006.201.14:23:30.68#ibcon#about to read 6, iclass 20, count 2 2006.201.14:23:30.68#ibcon#read 6, iclass 20, count 2 2006.201.14:23:30.68#ibcon#end of sib2, iclass 20, count 2 2006.201.14:23:30.68#ibcon#*after write, iclass 20, count 2 2006.201.14:23:30.68#ibcon#*before return 0, iclass 20, count 2 2006.201.14:23:30.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:23:30.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.14:23:30.68#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.14:23:30.68#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:30.68#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:23:30.80#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:23:30.80#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:23:30.80#ibcon#enter wrdev, iclass 20, count 0 2006.201.14:23:30.80#ibcon#first serial, iclass 20, count 0 2006.201.14:23:30.80#ibcon#enter sib2, iclass 20, count 0 2006.201.14:23:30.80#ibcon#flushed, iclass 20, count 0 2006.201.14:23:30.80#ibcon#about to write, iclass 20, count 0 2006.201.14:23:30.80#ibcon#wrote, iclass 20, count 0 2006.201.14:23:30.80#ibcon#about to read 3, iclass 20, count 0 2006.201.14:23:30.82#ibcon#read 3, iclass 20, count 0 2006.201.14:23:30.82#ibcon#about to read 4, iclass 20, count 0 2006.201.14:23:30.82#ibcon#read 4, iclass 20, count 0 2006.201.14:23:30.82#ibcon#about to read 5, iclass 20, count 0 2006.201.14:23:30.82#ibcon#read 5, iclass 20, count 0 2006.201.14:23:30.82#ibcon#about to read 6, iclass 20, count 0 2006.201.14:23:30.82#ibcon#read 6, iclass 20, count 0 2006.201.14:23:30.82#ibcon#end of sib2, iclass 20, count 0 2006.201.14:23:30.82#ibcon#*mode == 0, iclass 20, count 0 2006.201.14:23:30.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.14:23:30.82#ibcon#[27=USB\r\n] 2006.201.14:23:30.82#ibcon#*before write, iclass 20, count 0 2006.201.14:23:30.82#ibcon#enter sib2, iclass 20, count 0 2006.201.14:23:30.82#ibcon#flushed, iclass 20, count 0 2006.201.14:23:30.82#ibcon#about to write, iclass 20, count 0 2006.201.14:23:30.82#ibcon#wrote, iclass 20, count 0 2006.201.14:23:30.82#ibcon#about to read 3, iclass 20, count 0 2006.201.14:23:30.85#ibcon#read 3, iclass 20, count 0 2006.201.14:23:30.85#ibcon#about to read 4, iclass 20, count 0 2006.201.14:23:30.85#ibcon#read 4, iclass 20, count 0 2006.201.14:23:30.85#ibcon#about to read 5, iclass 20, count 0 2006.201.14:23:30.85#ibcon#read 5, iclass 20, count 0 2006.201.14:23:30.85#ibcon#about to read 6, iclass 20, count 0 2006.201.14:23:30.85#ibcon#read 6, iclass 20, count 0 2006.201.14:23:30.85#ibcon#end of sib2, iclass 20, count 0 2006.201.14:23:30.85#ibcon#*after write, iclass 20, count 0 2006.201.14:23:30.85#ibcon#*before return 0, iclass 20, count 0 2006.201.14:23:30.85#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:23:30.85#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.14:23:30.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.14:23:30.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.14:23:30.85$vck44/vblo=2,634.99 2006.201.14:23:30.85#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.14:23:30.85#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.14:23:30.85#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:30.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:30.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:30.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:30.85#ibcon#enter wrdev, iclass 22, count 0 2006.201.14:23:30.85#ibcon#first serial, iclass 22, count 0 2006.201.14:23:30.85#ibcon#enter sib2, iclass 22, count 0 2006.201.14:23:30.85#ibcon#flushed, iclass 22, count 0 2006.201.14:23:30.85#ibcon#about to write, iclass 22, count 0 2006.201.14:23:30.85#ibcon#wrote, iclass 22, count 0 2006.201.14:23:30.85#ibcon#about to read 3, iclass 22, count 0 2006.201.14:23:30.87#ibcon#read 3, iclass 22, count 0 2006.201.14:23:30.87#ibcon#about to read 4, iclass 22, count 0 2006.201.14:23:30.87#ibcon#read 4, iclass 22, count 0 2006.201.14:23:30.87#ibcon#about to read 5, iclass 22, count 0 2006.201.14:23:30.87#ibcon#read 5, iclass 22, count 0 2006.201.14:23:30.87#ibcon#about to read 6, iclass 22, count 0 2006.201.14:23:30.87#ibcon#read 6, iclass 22, count 0 2006.201.14:23:30.87#ibcon#end of sib2, iclass 22, count 0 2006.201.14:23:30.87#ibcon#*mode == 0, iclass 22, count 0 2006.201.14:23:30.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.14:23:30.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:23:30.87#ibcon#*before write, iclass 22, count 0 2006.201.14:23:30.87#ibcon#enter sib2, iclass 22, count 0 2006.201.14:23:30.87#ibcon#flushed, iclass 22, count 0 2006.201.14:23:30.87#ibcon#about to write, iclass 22, count 0 2006.201.14:23:30.87#ibcon#wrote, iclass 22, count 0 2006.201.14:23:30.87#ibcon#about to read 3, iclass 22, count 0 2006.201.14:23:30.91#ibcon#read 3, iclass 22, count 0 2006.201.14:23:30.91#ibcon#about to read 4, iclass 22, count 0 2006.201.14:23:30.91#ibcon#read 4, iclass 22, count 0 2006.201.14:23:30.91#ibcon#about to read 5, iclass 22, count 0 2006.201.14:23:30.91#ibcon#read 5, iclass 22, count 0 2006.201.14:23:30.91#ibcon#about to read 6, iclass 22, count 0 2006.201.14:23:30.91#ibcon#read 6, iclass 22, count 0 2006.201.14:23:30.91#ibcon#end of sib2, iclass 22, count 0 2006.201.14:23:30.91#ibcon#*after write, iclass 22, count 0 2006.201.14:23:30.91#ibcon#*before return 0, iclass 22, count 0 2006.201.14:23:30.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:30.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.14:23:30.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.14:23:30.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.14:23:30.91$vck44/vb=2,5 2006.201.14:23:30.91#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.14:23:30.91#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.14:23:30.91#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:30.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:30.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:30.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:30.97#ibcon#enter wrdev, iclass 24, count 2 2006.201.14:23:30.97#ibcon#first serial, iclass 24, count 2 2006.201.14:23:30.97#ibcon#enter sib2, iclass 24, count 2 2006.201.14:23:30.97#ibcon#flushed, iclass 24, count 2 2006.201.14:23:30.97#ibcon#about to write, iclass 24, count 2 2006.201.14:23:30.97#ibcon#wrote, iclass 24, count 2 2006.201.14:23:30.97#ibcon#about to read 3, iclass 24, count 2 2006.201.14:23:30.99#ibcon#read 3, iclass 24, count 2 2006.201.14:23:30.99#ibcon#about to read 4, iclass 24, count 2 2006.201.14:23:30.99#ibcon#read 4, iclass 24, count 2 2006.201.14:23:30.99#ibcon#about to read 5, iclass 24, count 2 2006.201.14:23:30.99#ibcon#read 5, iclass 24, count 2 2006.201.14:23:30.99#ibcon#about to read 6, iclass 24, count 2 2006.201.14:23:30.99#ibcon#read 6, iclass 24, count 2 2006.201.14:23:30.99#ibcon#end of sib2, iclass 24, count 2 2006.201.14:23:30.99#ibcon#*mode == 0, iclass 24, count 2 2006.201.14:23:30.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.14:23:30.99#ibcon#[27=AT02-05\r\n] 2006.201.14:23:30.99#ibcon#*before write, iclass 24, count 2 2006.201.14:23:30.99#ibcon#enter sib2, iclass 24, count 2 2006.201.14:23:30.99#ibcon#flushed, iclass 24, count 2 2006.201.14:23:30.99#ibcon#about to write, iclass 24, count 2 2006.201.14:23:30.99#ibcon#wrote, iclass 24, count 2 2006.201.14:23:30.99#ibcon#about to read 3, iclass 24, count 2 2006.201.14:23:31.02#ibcon#read 3, iclass 24, count 2 2006.201.14:23:31.02#ibcon#about to read 4, iclass 24, count 2 2006.201.14:23:31.02#ibcon#read 4, iclass 24, count 2 2006.201.14:23:31.02#ibcon#about to read 5, iclass 24, count 2 2006.201.14:23:31.02#ibcon#read 5, iclass 24, count 2 2006.201.14:23:31.02#ibcon#about to read 6, iclass 24, count 2 2006.201.14:23:31.02#ibcon#read 6, iclass 24, count 2 2006.201.14:23:31.02#ibcon#end of sib2, iclass 24, count 2 2006.201.14:23:31.02#ibcon#*after write, iclass 24, count 2 2006.201.14:23:31.02#ibcon#*before return 0, iclass 24, count 2 2006.201.14:23:31.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:31.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:23:31.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.14:23:31.02#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:31.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:31.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:31.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:31.14#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:23:31.14#ibcon#first serial, iclass 24, count 0 2006.201.14:23:31.14#ibcon#enter sib2, iclass 24, count 0 2006.201.14:23:31.14#ibcon#flushed, iclass 24, count 0 2006.201.14:23:31.14#ibcon#about to write, iclass 24, count 0 2006.201.14:23:31.14#ibcon#wrote, iclass 24, count 0 2006.201.14:23:31.14#ibcon#about to read 3, iclass 24, count 0 2006.201.14:23:31.16#ibcon#read 3, iclass 24, count 0 2006.201.14:23:31.16#ibcon#about to read 4, iclass 24, count 0 2006.201.14:23:31.16#ibcon#read 4, iclass 24, count 0 2006.201.14:23:31.16#ibcon#about to read 5, iclass 24, count 0 2006.201.14:23:31.16#ibcon#read 5, iclass 24, count 0 2006.201.14:23:31.16#ibcon#about to read 6, iclass 24, count 0 2006.201.14:23:31.16#ibcon#read 6, iclass 24, count 0 2006.201.14:23:31.16#ibcon#end of sib2, iclass 24, count 0 2006.201.14:23:31.16#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:23:31.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:23:31.16#ibcon#[27=USB\r\n] 2006.201.14:23:31.16#ibcon#*before write, iclass 24, count 0 2006.201.14:23:31.16#ibcon#enter sib2, iclass 24, count 0 2006.201.14:23:31.16#ibcon#flushed, iclass 24, count 0 2006.201.14:23:31.16#ibcon#about to write, iclass 24, count 0 2006.201.14:23:31.16#ibcon#wrote, iclass 24, count 0 2006.201.14:23:31.16#ibcon#about to read 3, iclass 24, count 0 2006.201.14:23:31.19#ibcon#read 3, iclass 24, count 0 2006.201.14:23:31.19#ibcon#about to read 4, iclass 24, count 0 2006.201.14:23:31.19#ibcon#read 4, iclass 24, count 0 2006.201.14:23:31.19#ibcon#about to read 5, iclass 24, count 0 2006.201.14:23:31.19#ibcon#read 5, iclass 24, count 0 2006.201.14:23:31.19#ibcon#about to read 6, iclass 24, count 0 2006.201.14:23:31.19#ibcon#read 6, iclass 24, count 0 2006.201.14:23:31.19#ibcon#end of sib2, iclass 24, count 0 2006.201.14:23:31.19#ibcon#*after write, iclass 24, count 0 2006.201.14:23:31.19#ibcon#*before return 0, iclass 24, count 0 2006.201.14:23:31.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:31.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:23:31.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:23:31.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:23:31.19$vck44/vblo=3,649.99 2006.201.14:23:31.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.14:23:31.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.14:23:31.19#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:31.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:31.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:31.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:31.19#ibcon#enter wrdev, iclass 26, count 0 2006.201.14:23:31.19#ibcon#first serial, iclass 26, count 0 2006.201.14:23:31.19#ibcon#enter sib2, iclass 26, count 0 2006.201.14:23:31.19#ibcon#flushed, iclass 26, count 0 2006.201.14:23:31.19#ibcon#about to write, iclass 26, count 0 2006.201.14:23:31.19#ibcon#wrote, iclass 26, count 0 2006.201.14:23:31.19#ibcon#about to read 3, iclass 26, count 0 2006.201.14:23:31.21#ibcon#read 3, iclass 26, count 0 2006.201.14:23:31.21#ibcon#about to read 4, iclass 26, count 0 2006.201.14:23:31.21#ibcon#read 4, iclass 26, count 0 2006.201.14:23:31.21#ibcon#about to read 5, iclass 26, count 0 2006.201.14:23:31.21#ibcon#read 5, iclass 26, count 0 2006.201.14:23:31.21#ibcon#about to read 6, iclass 26, count 0 2006.201.14:23:31.21#ibcon#read 6, iclass 26, count 0 2006.201.14:23:31.21#ibcon#end of sib2, iclass 26, count 0 2006.201.14:23:31.21#ibcon#*mode == 0, iclass 26, count 0 2006.201.14:23:31.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.14:23:31.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:23:31.21#ibcon#*before write, iclass 26, count 0 2006.201.14:23:31.21#ibcon#enter sib2, iclass 26, count 0 2006.201.14:23:31.21#ibcon#flushed, iclass 26, count 0 2006.201.14:23:31.21#ibcon#about to write, iclass 26, count 0 2006.201.14:23:31.21#ibcon#wrote, iclass 26, count 0 2006.201.14:23:31.21#ibcon#about to read 3, iclass 26, count 0 2006.201.14:23:31.25#ibcon#read 3, iclass 26, count 0 2006.201.14:23:31.25#ibcon#about to read 4, iclass 26, count 0 2006.201.14:23:31.25#ibcon#read 4, iclass 26, count 0 2006.201.14:23:31.25#ibcon#about to read 5, iclass 26, count 0 2006.201.14:23:31.25#ibcon#read 5, iclass 26, count 0 2006.201.14:23:31.25#ibcon#about to read 6, iclass 26, count 0 2006.201.14:23:31.25#ibcon#read 6, iclass 26, count 0 2006.201.14:23:31.25#ibcon#end of sib2, iclass 26, count 0 2006.201.14:23:31.25#ibcon#*after write, iclass 26, count 0 2006.201.14:23:31.25#ibcon#*before return 0, iclass 26, count 0 2006.201.14:23:31.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:31.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:23:31.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.14:23:31.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.14:23:31.25$vck44/vb=3,4 2006.201.14:23:31.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.14:23:31.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.14:23:31.25#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:31.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:31.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:31.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:31.31#ibcon#enter wrdev, iclass 28, count 2 2006.201.14:23:31.31#ibcon#first serial, iclass 28, count 2 2006.201.14:23:31.31#ibcon#enter sib2, iclass 28, count 2 2006.201.14:23:31.31#ibcon#flushed, iclass 28, count 2 2006.201.14:23:31.31#ibcon#about to write, iclass 28, count 2 2006.201.14:23:31.31#ibcon#wrote, iclass 28, count 2 2006.201.14:23:31.31#ibcon#about to read 3, iclass 28, count 2 2006.201.14:23:31.33#ibcon#read 3, iclass 28, count 2 2006.201.14:23:31.33#ibcon#about to read 4, iclass 28, count 2 2006.201.14:23:31.33#ibcon#read 4, iclass 28, count 2 2006.201.14:23:31.33#ibcon#about to read 5, iclass 28, count 2 2006.201.14:23:31.33#ibcon#read 5, iclass 28, count 2 2006.201.14:23:31.33#ibcon#about to read 6, iclass 28, count 2 2006.201.14:23:31.33#ibcon#read 6, iclass 28, count 2 2006.201.14:23:31.33#ibcon#end of sib2, iclass 28, count 2 2006.201.14:23:31.33#ibcon#*mode == 0, iclass 28, count 2 2006.201.14:23:31.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.14:23:31.33#ibcon#[27=AT03-04\r\n] 2006.201.14:23:31.33#ibcon#*before write, iclass 28, count 2 2006.201.14:23:31.33#ibcon#enter sib2, iclass 28, count 2 2006.201.14:23:31.33#ibcon#flushed, iclass 28, count 2 2006.201.14:23:31.33#ibcon#about to write, iclass 28, count 2 2006.201.14:23:31.33#ibcon#wrote, iclass 28, count 2 2006.201.14:23:31.33#ibcon#about to read 3, iclass 28, count 2 2006.201.14:23:31.36#ibcon#read 3, iclass 28, count 2 2006.201.14:23:31.36#ibcon#about to read 4, iclass 28, count 2 2006.201.14:23:31.36#ibcon#read 4, iclass 28, count 2 2006.201.14:23:31.36#ibcon#about to read 5, iclass 28, count 2 2006.201.14:23:31.36#ibcon#read 5, iclass 28, count 2 2006.201.14:23:31.36#ibcon#about to read 6, iclass 28, count 2 2006.201.14:23:31.36#ibcon#read 6, iclass 28, count 2 2006.201.14:23:31.36#ibcon#end of sib2, iclass 28, count 2 2006.201.14:23:31.36#ibcon#*after write, iclass 28, count 2 2006.201.14:23:31.36#ibcon#*before return 0, iclass 28, count 2 2006.201.14:23:31.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:31.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.14:23:31.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.14:23:31.36#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:31.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:31.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:31.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:31.48#ibcon#enter wrdev, iclass 28, count 0 2006.201.14:23:31.48#ibcon#first serial, iclass 28, count 0 2006.201.14:23:31.48#ibcon#enter sib2, iclass 28, count 0 2006.201.14:23:31.48#ibcon#flushed, iclass 28, count 0 2006.201.14:23:31.48#ibcon#about to write, iclass 28, count 0 2006.201.14:23:31.48#ibcon#wrote, iclass 28, count 0 2006.201.14:23:31.48#ibcon#about to read 3, iclass 28, count 0 2006.201.14:23:31.50#ibcon#read 3, iclass 28, count 0 2006.201.14:23:31.50#ibcon#about to read 4, iclass 28, count 0 2006.201.14:23:31.50#ibcon#read 4, iclass 28, count 0 2006.201.14:23:31.50#ibcon#about to read 5, iclass 28, count 0 2006.201.14:23:31.50#ibcon#read 5, iclass 28, count 0 2006.201.14:23:31.50#ibcon#about to read 6, iclass 28, count 0 2006.201.14:23:31.50#ibcon#read 6, iclass 28, count 0 2006.201.14:23:31.50#ibcon#end of sib2, iclass 28, count 0 2006.201.14:23:31.50#ibcon#*mode == 0, iclass 28, count 0 2006.201.14:23:31.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.14:23:31.50#ibcon#[27=USB\r\n] 2006.201.14:23:31.50#ibcon#*before write, iclass 28, count 0 2006.201.14:23:31.50#ibcon#enter sib2, iclass 28, count 0 2006.201.14:23:31.50#ibcon#flushed, iclass 28, count 0 2006.201.14:23:31.50#ibcon#about to write, iclass 28, count 0 2006.201.14:23:31.50#ibcon#wrote, iclass 28, count 0 2006.201.14:23:31.50#ibcon#about to read 3, iclass 28, count 0 2006.201.14:23:31.53#ibcon#read 3, iclass 28, count 0 2006.201.14:23:31.53#ibcon#about to read 4, iclass 28, count 0 2006.201.14:23:31.53#ibcon#read 4, iclass 28, count 0 2006.201.14:23:31.53#ibcon#about to read 5, iclass 28, count 0 2006.201.14:23:31.53#ibcon#read 5, iclass 28, count 0 2006.201.14:23:31.53#ibcon#about to read 6, iclass 28, count 0 2006.201.14:23:31.53#ibcon#read 6, iclass 28, count 0 2006.201.14:23:31.53#ibcon#end of sib2, iclass 28, count 0 2006.201.14:23:31.53#ibcon#*after write, iclass 28, count 0 2006.201.14:23:31.53#ibcon#*before return 0, iclass 28, count 0 2006.201.14:23:31.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:31.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.14:23:31.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.14:23:31.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.14:23:31.53$vck44/vblo=4,679.99 2006.201.14:23:31.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.14:23:31.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.14:23:31.53#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:31.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:31.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:31.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:31.53#ibcon#enter wrdev, iclass 30, count 0 2006.201.14:23:31.53#ibcon#first serial, iclass 30, count 0 2006.201.14:23:31.53#ibcon#enter sib2, iclass 30, count 0 2006.201.14:23:31.53#ibcon#flushed, iclass 30, count 0 2006.201.14:23:31.53#ibcon#about to write, iclass 30, count 0 2006.201.14:23:31.53#ibcon#wrote, iclass 30, count 0 2006.201.14:23:31.53#ibcon#about to read 3, iclass 30, count 0 2006.201.14:23:31.55#ibcon#read 3, iclass 30, count 0 2006.201.14:23:31.55#ibcon#about to read 4, iclass 30, count 0 2006.201.14:23:31.55#ibcon#read 4, iclass 30, count 0 2006.201.14:23:31.55#ibcon#about to read 5, iclass 30, count 0 2006.201.14:23:31.55#ibcon#read 5, iclass 30, count 0 2006.201.14:23:31.55#ibcon#about to read 6, iclass 30, count 0 2006.201.14:23:31.55#ibcon#read 6, iclass 30, count 0 2006.201.14:23:31.55#ibcon#end of sib2, iclass 30, count 0 2006.201.14:23:31.55#ibcon#*mode == 0, iclass 30, count 0 2006.201.14:23:31.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.14:23:31.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:23:31.55#ibcon#*before write, iclass 30, count 0 2006.201.14:23:31.55#ibcon#enter sib2, iclass 30, count 0 2006.201.14:23:31.55#ibcon#flushed, iclass 30, count 0 2006.201.14:23:31.55#ibcon#about to write, iclass 30, count 0 2006.201.14:23:31.55#ibcon#wrote, iclass 30, count 0 2006.201.14:23:31.55#ibcon#about to read 3, iclass 30, count 0 2006.201.14:23:31.59#ibcon#read 3, iclass 30, count 0 2006.201.14:23:31.59#ibcon#about to read 4, iclass 30, count 0 2006.201.14:23:31.59#ibcon#read 4, iclass 30, count 0 2006.201.14:23:31.59#ibcon#about to read 5, iclass 30, count 0 2006.201.14:23:31.59#ibcon#read 5, iclass 30, count 0 2006.201.14:23:31.59#ibcon#about to read 6, iclass 30, count 0 2006.201.14:23:31.59#ibcon#read 6, iclass 30, count 0 2006.201.14:23:31.59#ibcon#end of sib2, iclass 30, count 0 2006.201.14:23:31.59#ibcon#*after write, iclass 30, count 0 2006.201.14:23:31.59#ibcon#*before return 0, iclass 30, count 0 2006.201.14:23:31.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:31.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.14:23:31.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.14:23:31.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.14:23:31.59$vck44/vb=4,5 2006.201.14:23:31.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.14:23:31.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.14:23:31.59#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:31.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:31.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:31.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:31.65#ibcon#enter wrdev, iclass 32, count 2 2006.201.14:23:31.65#ibcon#first serial, iclass 32, count 2 2006.201.14:23:31.65#ibcon#enter sib2, iclass 32, count 2 2006.201.14:23:31.65#ibcon#flushed, iclass 32, count 2 2006.201.14:23:31.65#ibcon#about to write, iclass 32, count 2 2006.201.14:23:31.65#ibcon#wrote, iclass 32, count 2 2006.201.14:23:31.65#ibcon#about to read 3, iclass 32, count 2 2006.201.14:23:31.67#ibcon#read 3, iclass 32, count 2 2006.201.14:23:31.67#ibcon#about to read 4, iclass 32, count 2 2006.201.14:23:31.67#ibcon#read 4, iclass 32, count 2 2006.201.14:23:31.67#ibcon#about to read 5, iclass 32, count 2 2006.201.14:23:31.67#ibcon#read 5, iclass 32, count 2 2006.201.14:23:31.67#ibcon#about to read 6, iclass 32, count 2 2006.201.14:23:31.67#ibcon#read 6, iclass 32, count 2 2006.201.14:23:31.67#ibcon#end of sib2, iclass 32, count 2 2006.201.14:23:31.67#ibcon#*mode == 0, iclass 32, count 2 2006.201.14:23:31.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.14:23:31.67#ibcon#[27=AT04-05\r\n] 2006.201.14:23:31.67#ibcon#*before write, iclass 32, count 2 2006.201.14:23:31.67#ibcon#enter sib2, iclass 32, count 2 2006.201.14:23:31.67#ibcon#flushed, iclass 32, count 2 2006.201.14:23:31.67#ibcon#about to write, iclass 32, count 2 2006.201.14:23:31.67#ibcon#wrote, iclass 32, count 2 2006.201.14:23:31.67#ibcon#about to read 3, iclass 32, count 2 2006.201.14:23:31.70#ibcon#read 3, iclass 32, count 2 2006.201.14:23:31.70#ibcon#about to read 4, iclass 32, count 2 2006.201.14:23:31.70#ibcon#read 4, iclass 32, count 2 2006.201.14:23:31.70#ibcon#about to read 5, iclass 32, count 2 2006.201.14:23:31.70#ibcon#read 5, iclass 32, count 2 2006.201.14:23:31.70#ibcon#about to read 6, iclass 32, count 2 2006.201.14:23:31.70#ibcon#read 6, iclass 32, count 2 2006.201.14:23:31.70#ibcon#end of sib2, iclass 32, count 2 2006.201.14:23:31.70#ibcon#*after write, iclass 32, count 2 2006.201.14:23:31.70#ibcon#*before return 0, iclass 32, count 2 2006.201.14:23:31.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:31.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.14:23:31.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.14:23:31.70#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:31.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:31.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:31.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:31.82#ibcon#enter wrdev, iclass 32, count 0 2006.201.14:23:31.82#ibcon#first serial, iclass 32, count 0 2006.201.14:23:31.82#ibcon#enter sib2, iclass 32, count 0 2006.201.14:23:31.82#ibcon#flushed, iclass 32, count 0 2006.201.14:23:31.82#ibcon#about to write, iclass 32, count 0 2006.201.14:23:31.82#ibcon#wrote, iclass 32, count 0 2006.201.14:23:31.82#ibcon#about to read 3, iclass 32, count 0 2006.201.14:23:31.84#ibcon#read 3, iclass 32, count 0 2006.201.14:23:31.84#ibcon#about to read 4, iclass 32, count 0 2006.201.14:23:31.84#ibcon#read 4, iclass 32, count 0 2006.201.14:23:31.84#ibcon#about to read 5, iclass 32, count 0 2006.201.14:23:31.84#ibcon#read 5, iclass 32, count 0 2006.201.14:23:31.84#ibcon#about to read 6, iclass 32, count 0 2006.201.14:23:31.84#ibcon#read 6, iclass 32, count 0 2006.201.14:23:31.84#ibcon#end of sib2, iclass 32, count 0 2006.201.14:23:31.84#ibcon#*mode == 0, iclass 32, count 0 2006.201.14:23:31.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.14:23:31.84#ibcon#[27=USB\r\n] 2006.201.14:23:31.84#ibcon#*before write, iclass 32, count 0 2006.201.14:23:31.84#ibcon#enter sib2, iclass 32, count 0 2006.201.14:23:31.84#ibcon#flushed, iclass 32, count 0 2006.201.14:23:31.84#ibcon#about to write, iclass 32, count 0 2006.201.14:23:31.84#ibcon#wrote, iclass 32, count 0 2006.201.14:23:31.84#ibcon#about to read 3, iclass 32, count 0 2006.201.14:23:31.87#ibcon#read 3, iclass 32, count 0 2006.201.14:23:31.87#ibcon#about to read 4, iclass 32, count 0 2006.201.14:23:31.87#ibcon#read 4, iclass 32, count 0 2006.201.14:23:31.87#ibcon#about to read 5, iclass 32, count 0 2006.201.14:23:31.87#ibcon#read 5, iclass 32, count 0 2006.201.14:23:31.87#ibcon#about to read 6, iclass 32, count 0 2006.201.14:23:31.87#ibcon#read 6, iclass 32, count 0 2006.201.14:23:31.87#ibcon#end of sib2, iclass 32, count 0 2006.201.14:23:31.87#ibcon#*after write, iclass 32, count 0 2006.201.14:23:31.87#ibcon#*before return 0, iclass 32, count 0 2006.201.14:23:31.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:31.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.14:23:31.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.14:23:31.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.14:23:31.87$vck44/vblo=5,709.99 2006.201.14:23:31.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.14:23:31.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.14:23:31.87#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:31.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:31.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:31.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:31.87#ibcon#enter wrdev, iclass 34, count 0 2006.201.14:23:31.87#ibcon#first serial, iclass 34, count 0 2006.201.14:23:31.87#ibcon#enter sib2, iclass 34, count 0 2006.201.14:23:31.87#ibcon#flushed, iclass 34, count 0 2006.201.14:23:31.87#ibcon#about to write, iclass 34, count 0 2006.201.14:23:31.87#ibcon#wrote, iclass 34, count 0 2006.201.14:23:31.87#ibcon#about to read 3, iclass 34, count 0 2006.201.14:23:31.89#ibcon#read 3, iclass 34, count 0 2006.201.14:23:31.89#ibcon#about to read 4, iclass 34, count 0 2006.201.14:23:31.89#ibcon#read 4, iclass 34, count 0 2006.201.14:23:31.89#ibcon#about to read 5, iclass 34, count 0 2006.201.14:23:31.89#ibcon#read 5, iclass 34, count 0 2006.201.14:23:31.89#ibcon#about to read 6, iclass 34, count 0 2006.201.14:23:31.89#ibcon#read 6, iclass 34, count 0 2006.201.14:23:31.89#ibcon#end of sib2, iclass 34, count 0 2006.201.14:23:31.89#ibcon#*mode == 0, iclass 34, count 0 2006.201.14:23:31.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.14:23:31.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:23:31.89#ibcon#*before write, iclass 34, count 0 2006.201.14:23:31.89#ibcon#enter sib2, iclass 34, count 0 2006.201.14:23:31.89#ibcon#flushed, iclass 34, count 0 2006.201.14:23:31.89#ibcon#about to write, iclass 34, count 0 2006.201.14:23:31.89#ibcon#wrote, iclass 34, count 0 2006.201.14:23:31.89#ibcon#about to read 3, iclass 34, count 0 2006.201.14:23:31.94#ibcon#read 3, iclass 34, count 0 2006.201.14:23:31.94#ibcon#about to read 4, iclass 34, count 0 2006.201.14:23:31.94#ibcon#read 4, iclass 34, count 0 2006.201.14:23:31.94#ibcon#about to read 5, iclass 34, count 0 2006.201.14:23:31.94#ibcon#read 5, iclass 34, count 0 2006.201.14:23:31.94#ibcon#about to read 6, iclass 34, count 0 2006.201.14:23:31.94#ibcon#read 6, iclass 34, count 0 2006.201.14:23:31.94#ibcon#end of sib2, iclass 34, count 0 2006.201.14:23:31.94#ibcon#*after write, iclass 34, count 0 2006.201.14:23:31.94#ibcon#*before return 0, iclass 34, count 0 2006.201.14:23:31.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:31.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.14:23:31.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.14:23:31.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.14:23:31.94$vck44/vb=5,4 2006.201.14:23:31.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.14:23:31.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.14:23:31.94#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:31.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:31.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:31.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:31.99#ibcon#enter wrdev, iclass 36, count 2 2006.201.14:23:31.99#ibcon#first serial, iclass 36, count 2 2006.201.14:23:31.99#ibcon#enter sib2, iclass 36, count 2 2006.201.14:23:31.99#ibcon#flushed, iclass 36, count 2 2006.201.14:23:31.99#ibcon#about to write, iclass 36, count 2 2006.201.14:23:31.99#ibcon#wrote, iclass 36, count 2 2006.201.14:23:31.99#ibcon#about to read 3, iclass 36, count 2 2006.201.14:23:32.01#ibcon#read 3, iclass 36, count 2 2006.201.14:23:32.01#ibcon#about to read 4, iclass 36, count 2 2006.201.14:23:32.01#ibcon#read 4, iclass 36, count 2 2006.201.14:23:32.01#ibcon#about to read 5, iclass 36, count 2 2006.201.14:23:32.01#ibcon#read 5, iclass 36, count 2 2006.201.14:23:32.01#ibcon#about to read 6, iclass 36, count 2 2006.201.14:23:32.01#ibcon#read 6, iclass 36, count 2 2006.201.14:23:32.01#ibcon#end of sib2, iclass 36, count 2 2006.201.14:23:32.01#ibcon#*mode == 0, iclass 36, count 2 2006.201.14:23:32.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.14:23:32.01#ibcon#[27=AT05-04\r\n] 2006.201.14:23:32.01#ibcon#*before write, iclass 36, count 2 2006.201.14:23:32.01#ibcon#enter sib2, iclass 36, count 2 2006.201.14:23:32.01#ibcon#flushed, iclass 36, count 2 2006.201.14:23:32.01#ibcon#about to write, iclass 36, count 2 2006.201.14:23:32.01#ibcon#wrote, iclass 36, count 2 2006.201.14:23:32.01#ibcon#about to read 3, iclass 36, count 2 2006.201.14:23:32.04#ibcon#read 3, iclass 36, count 2 2006.201.14:23:32.04#ibcon#about to read 4, iclass 36, count 2 2006.201.14:23:32.04#ibcon#read 4, iclass 36, count 2 2006.201.14:23:32.04#ibcon#about to read 5, iclass 36, count 2 2006.201.14:23:32.04#ibcon#read 5, iclass 36, count 2 2006.201.14:23:32.04#ibcon#about to read 6, iclass 36, count 2 2006.201.14:23:32.04#ibcon#read 6, iclass 36, count 2 2006.201.14:23:32.04#ibcon#end of sib2, iclass 36, count 2 2006.201.14:23:32.04#ibcon#*after write, iclass 36, count 2 2006.201.14:23:32.04#ibcon#*before return 0, iclass 36, count 2 2006.201.14:23:32.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:32.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.14:23:32.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.14:23:32.04#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:32.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:32.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:32.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:32.16#ibcon#enter wrdev, iclass 36, count 0 2006.201.14:23:32.16#ibcon#first serial, iclass 36, count 0 2006.201.14:23:32.16#ibcon#enter sib2, iclass 36, count 0 2006.201.14:23:32.16#ibcon#flushed, iclass 36, count 0 2006.201.14:23:32.16#ibcon#about to write, iclass 36, count 0 2006.201.14:23:32.16#ibcon#wrote, iclass 36, count 0 2006.201.14:23:32.16#ibcon#about to read 3, iclass 36, count 0 2006.201.14:23:32.18#ibcon#read 3, iclass 36, count 0 2006.201.14:23:32.18#ibcon#about to read 4, iclass 36, count 0 2006.201.14:23:32.18#ibcon#read 4, iclass 36, count 0 2006.201.14:23:32.18#ibcon#about to read 5, iclass 36, count 0 2006.201.14:23:32.18#ibcon#read 5, iclass 36, count 0 2006.201.14:23:32.18#ibcon#about to read 6, iclass 36, count 0 2006.201.14:23:32.18#ibcon#read 6, iclass 36, count 0 2006.201.14:23:32.18#ibcon#end of sib2, iclass 36, count 0 2006.201.14:23:32.18#ibcon#*mode == 0, iclass 36, count 0 2006.201.14:23:32.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.14:23:32.18#ibcon#[27=USB\r\n] 2006.201.14:23:32.18#ibcon#*before write, iclass 36, count 0 2006.201.14:23:32.18#ibcon#enter sib2, iclass 36, count 0 2006.201.14:23:32.18#ibcon#flushed, iclass 36, count 0 2006.201.14:23:32.18#ibcon#about to write, iclass 36, count 0 2006.201.14:23:32.18#ibcon#wrote, iclass 36, count 0 2006.201.14:23:32.18#ibcon#about to read 3, iclass 36, count 0 2006.201.14:23:32.21#ibcon#read 3, iclass 36, count 0 2006.201.14:23:32.21#ibcon#about to read 4, iclass 36, count 0 2006.201.14:23:32.21#ibcon#read 4, iclass 36, count 0 2006.201.14:23:32.21#ibcon#about to read 5, iclass 36, count 0 2006.201.14:23:32.21#ibcon#read 5, iclass 36, count 0 2006.201.14:23:32.21#ibcon#about to read 6, iclass 36, count 0 2006.201.14:23:32.21#ibcon#read 6, iclass 36, count 0 2006.201.14:23:32.21#ibcon#end of sib2, iclass 36, count 0 2006.201.14:23:32.21#ibcon#*after write, iclass 36, count 0 2006.201.14:23:32.21#ibcon#*before return 0, iclass 36, count 0 2006.201.14:23:32.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:32.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.14:23:32.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.14:23:32.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.14:23:32.21$vck44/vblo=6,719.99 2006.201.14:23:32.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.14:23:32.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.14:23:32.21#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:32.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:32.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:32.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:32.21#ibcon#enter wrdev, iclass 38, count 0 2006.201.14:23:32.21#ibcon#first serial, iclass 38, count 0 2006.201.14:23:32.21#ibcon#enter sib2, iclass 38, count 0 2006.201.14:23:32.21#ibcon#flushed, iclass 38, count 0 2006.201.14:23:32.21#ibcon#about to write, iclass 38, count 0 2006.201.14:23:32.21#ibcon#wrote, iclass 38, count 0 2006.201.14:23:32.21#ibcon#about to read 3, iclass 38, count 0 2006.201.14:23:32.23#ibcon#read 3, iclass 38, count 0 2006.201.14:23:32.23#ibcon#about to read 4, iclass 38, count 0 2006.201.14:23:32.23#ibcon#read 4, iclass 38, count 0 2006.201.14:23:32.23#ibcon#about to read 5, iclass 38, count 0 2006.201.14:23:32.23#ibcon#read 5, iclass 38, count 0 2006.201.14:23:32.23#ibcon#about to read 6, iclass 38, count 0 2006.201.14:23:32.23#ibcon#read 6, iclass 38, count 0 2006.201.14:23:32.23#ibcon#end of sib2, iclass 38, count 0 2006.201.14:23:32.23#ibcon#*mode == 0, iclass 38, count 0 2006.201.14:23:32.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.14:23:32.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:23:32.23#ibcon#*before write, iclass 38, count 0 2006.201.14:23:32.23#ibcon#enter sib2, iclass 38, count 0 2006.201.14:23:32.23#ibcon#flushed, iclass 38, count 0 2006.201.14:23:32.23#ibcon#about to write, iclass 38, count 0 2006.201.14:23:32.23#ibcon#wrote, iclass 38, count 0 2006.201.14:23:32.23#ibcon#about to read 3, iclass 38, count 0 2006.201.14:23:32.27#ibcon#read 3, iclass 38, count 0 2006.201.14:23:32.27#ibcon#about to read 4, iclass 38, count 0 2006.201.14:23:32.27#ibcon#read 4, iclass 38, count 0 2006.201.14:23:32.27#ibcon#about to read 5, iclass 38, count 0 2006.201.14:23:32.27#ibcon#read 5, iclass 38, count 0 2006.201.14:23:32.27#ibcon#about to read 6, iclass 38, count 0 2006.201.14:23:32.27#ibcon#read 6, iclass 38, count 0 2006.201.14:23:32.27#ibcon#end of sib2, iclass 38, count 0 2006.201.14:23:32.27#ibcon#*after write, iclass 38, count 0 2006.201.14:23:32.27#ibcon#*before return 0, iclass 38, count 0 2006.201.14:23:32.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:32.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.14:23:32.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.14:23:32.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.14:23:32.27$vck44/vb=6,4 2006.201.14:23:32.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.14:23:32.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.14:23:32.27#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:32.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:32.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:32.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:32.33#ibcon#enter wrdev, iclass 40, count 2 2006.201.14:23:32.33#ibcon#first serial, iclass 40, count 2 2006.201.14:23:32.33#ibcon#enter sib2, iclass 40, count 2 2006.201.14:23:32.33#ibcon#flushed, iclass 40, count 2 2006.201.14:23:32.33#ibcon#about to write, iclass 40, count 2 2006.201.14:23:32.33#ibcon#wrote, iclass 40, count 2 2006.201.14:23:32.33#ibcon#about to read 3, iclass 40, count 2 2006.201.14:23:32.35#ibcon#read 3, iclass 40, count 2 2006.201.14:23:32.35#ibcon#about to read 4, iclass 40, count 2 2006.201.14:23:32.35#ibcon#read 4, iclass 40, count 2 2006.201.14:23:32.35#ibcon#about to read 5, iclass 40, count 2 2006.201.14:23:32.35#ibcon#read 5, iclass 40, count 2 2006.201.14:23:32.35#ibcon#about to read 6, iclass 40, count 2 2006.201.14:23:32.35#ibcon#read 6, iclass 40, count 2 2006.201.14:23:32.35#ibcon#end of sib2, iclass 40, count 2 2006.201.14:23:32.35#ibcon#*mode == 0, iclass 40, count 2 2006.201.14:23:32.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.14:23:32.35#ibcon#[27=AT06-04\r\n] 2006.201.14:23:32.35#ibcon#*before write, iclass 40, count 2 2006.201.14:23:32.35#ibcon#enter sib2, iclass 40, count 2 2006.201.14:23:32.35#ibcon#flushed, iclass 40, count 2 2006.201.14:23:32.35#ibcon#about to write, iclass 40, count 2 2006.201.14:23:32.35#ibcon#wrote, iclass 40, count 2 2006.201.14:23:32.35#ibcon#about to read 3, iclass 40, count 2 2006.201.14:23:32.38#ibcon#read 3, iclass 40, count 2 2006.201.14:23:32.38#ibcon#about to read 4, iclass 40, count 2 2006.201.14:23:32.38#ibcon#read 4, iclass 40, count 2 2006.201.14:23:32.38#ibcon#about to read 5, iclass 40, count 2 2006.201.14:23:32.38#ibcon#read 5, iclass 40, count 2 2006.201.14:23:32.38#ibcon#about to read 6, iclass 40, count 2 2006.201.14:23:32.38#ibcon#read 6, iclass 40, count 2 2006.201.14:23:32.38#ibcon#end of sib2, iclass 40, count 2 2006.201.14:23:32.38#ibcon#*after write, iclass 40, count 2 2006.201.14:23:32.38#ibcon#*before return 0, iclass 40, count 2 2006.201.14:23:32.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:32.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.14:23:32.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.14:23:32.38#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:32.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:32.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:32.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:32.50#ibcon#enter wrdev, iclass 40, count 0 2006.201.14:23:32.50#ibcon#first serial, iclass 40, count 0 2006.201.14:23:32.50#ibcon#enter sib2, iclass 40, count 0 2006.201.14:23:32.50#ibcon#flushed, iclass 40, count 0 2006.201.14:23:32.50#ibcon#about to write, iclass 40, count 0 2006.201.14:23:32.50#ibcon#wrote, iclass 40, count 0 2006.201.14:23:32.50#ibcon#about to read 3, iclass 40, count 0 2006.201.14:23:32.52#ibcon#read 3, iclass 40, count 0 2006.201.14:23:32.52#ibcon#about to read 4, iclass 40, count 0 2006.201.14:23:32.52#ibcon#read 4, iclass 40, count 0 2006.201.14:23:32.52#ibcon#about to read 5, iclass 40, count 0 2006.201.14:23:32.52#ibcon#read 5, iclass 40, count 0 2006.201.14:23:32.52#ibcon#about to read 6, iclass 40, count 0 2006.201.14:23:32.52#ibcon#read 6, iclass 40, count 0 2006.201.14:23:32.52#ibcon#end of sib2, iclass 40, count 0 2006.201.14:23:32.52#ibcon#*mode == 0, iclass 40, count 0 2006.201.14:23:32.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.14:23:32.52#ibcon#[27=USB\r\n] 2006.201.14:23:32.52#ibcon#*before write, iclass 40, count 0 2006.201.14:23:32.52#ibcon#enter sib2, iclass 40, count 0 2006.201.14:23:32.52#ibcon#flushed, iclass 40, count 0 2006.201.14:23:32.52#ibcon#about to write, iclass 40, count 0 2006.201.14:23:32.52#ibcon#wrote, iclass 40, count 0 2006.201.14:23:32.52#ibcon#about to read 3, iclass 40, count 0 2006.201.14:23:32.55#ibcon#read 3, iclass 40, count 0 2006.201.14:23:32.55#ibcon#about to read 4, iclass 40, count 0 2006.201.14:23:32.55#ibcon#read 4, iclass 40, count 0 2006.201.14:23:32.55#ibcon#about to read 5, iclass 40, count 0 2006.201.14:23:32.55#ibcon#read 5, iclass 40, count 0 2006.201.14:23:32.55#ibcon#about to read 6, iclass 40, count 0 2006.201.14:23:32.55#ibcon#read 6, iclass 40, count 0 2006.201.14:23:32.55#ibcon#end of sib2, iclass 40, count 0 2006.201.14:23:32.55#ibcon#*after write, iclass 40, count 0 2006.201.14:23:32.55#ibcon#*before return 0, iclass 40, count 0 2006.201.14:23:32.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:32.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.14:23:32.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.14:23:32.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.14:23:32.55$vck44/vblo=7,734.99 2006.201.14:23:32.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.14:23:32.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.14:23:32.55#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:32.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:32.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:32.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:32.55#ibcon#enter wrdev, iclass 4, count 0 2006.201.14:23:32.55#ibcon#first serial, iclass 4, count 0 2006.201.14:23:32.55#ibcon#enter sib2, iclass 4, count 0 2006.201.14:23:32.55#ibcon#flushed, iclass 4, count 0 2006.201.14:23:32.55#ibcon#about to write, iclass 4, count 0 2006.201.14:23:32.55#ibcon#wrote, iclass 4, count 0 2006.201.14:23:32.55#ibcon#about to read 3, iclass 4, count 0 2006.201.14:23:32.57#ibcon#read 3, iclass 4, count 0 2006.201.14:23:32.57#ibcon#about to read 4, iclass 4, count 0 2006.201.14:23:32.57#ibcon#read 4, iclass 4, count 0 2006.201.14:23:32.57#ibcon#about to read 5, iclass 4, count 0 2006.201.14:23:32.57#ibcon#read 5, iclass 4, count 0 2006.201.14:23:32.57#ibcon#about to read 6, iclass 4, count 0 2006.201.14:23:32.57#ibcon#read 6, iclass 4, count 0 2006.201.14:23:32.57#ibcon#end of sib2, iclass 4, count 0 2006.201.14:23:32.57#ibcon#*mode == 0, iclass 4, count 0 2006.201.14:23:32.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.14:23:32.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:23:32.57#ibcon#*before write, iclass 4, count 0 2006.201.14:23:32.57#ibcon#enter sib2, iclass 4, count 0 2006.201.14:23:32.57#ibcon#flushed, iclass 4, count 0 2006.201.14:23:32.57#ibcon#about to write, iclass 4, count 0 2006.201.14:23:32.57#ibcon#wrote, iclass 4, count 0 2006.201.14:23:32.57#ibcon#about to read 3, iclass 4, count 0 2006.201.14:23:32.61#ibcon#read 3, iclass 4, count 0 2006.201.14:23:32.61#ibcon#about to read 4, iclass 4, count 0 2006.201.14:23:32.61#ibcon#read 4, iclass 4, count 0 2006.201.14:23:32.61#ibcon#about to read 5, iclass 4, count 0 2006.201.14:23:32.61#ibcon#read 5, iclass 4, count 0 2006.201.14:23:32.61#ibcon#about to read 6, iclass 4, count 0 2006.201.14:23:32.61#ibcon#read 6, iclass 4, count 0 2006.201.14:23:32.61#ibcon#end of sib2, iclass 4, count 0 2006.201.14:23:32.61#ibcon#*after write, iclass 4, count 0 2006.201.14:23:32.61#ibcon#*before return 0, iclass 4, count 0 2006.201.14:23:32.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:32.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.14:23:32.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.14:23:32.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.14:23:32.61$vck44/vb=7,4 2006.201.14:23:32.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.14:23:32.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.14:23:32.61#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:32.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:32.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:32.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:32.67#ibcon#enter wrdev, iclass 6, count 2 2006.201.14:23:32.67#ibcon#first serial, iclass 6, count 2 2006.201.14:23:32.67#ibcon#enter sib2, iclass 6, count 2 2006.201.14:23:32.67#ibcon#flushed, iclass 6, count 2 2006.201.14:23:32.67#ibcon#about to write, iclass 6, count 2 2006.201.14:23:32.67#ibcon#wrote, iclass 6, count 2 2006.201.14:23:32.67#ibcon#about to read 3, iclass 6, count 2 2006.201.14:23:32.69#ibcon#read 3, iclass 6, count 2 2006.201.14:23:32.69#ibcon#about to read 4, iclass 6, count 2 2006.201.14:23:32.69#ibcon#read 4, iclass 6, count 2 2006.201.14:23:32.69#ibcon#about to read 5, iclass 6, count 2 2006.201.14:23:32.69#ibcon#read 5, iclass 6, count 2 2006.201.14:23:32.69#ibcon#about to read 6, iclass 6, count 2 2006.201.14:23:32.69#ibcon#read 6, iclass 6, count 2 2006.201.14:23:32.69#ibcon#end of sib2, iclass 6, count 2 2006.201.14:23:32.69#ibcon#*mode == 0, iclass 6, count 2 2006.201.14:23:32.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.14:23:32.69#ibcon#[27=AT07-04\r\n] 2006.201.14:23:32.69#ibcon#*before write, iclass 6, count 2 2006.201.14:23:32.69#ibcon#enter sib2, iclass 6, count 2 2006.201.14:23:32.69#ibcon#flushed, iclass 6, count 2 2006.201.14:23:32.69#ibcon#about to write, iclass 6, count 2 2006.201.14:23:32.69#ibcon#wrote, iclass 6, count 2 2006.201.14:23:32.69#ibcon#about to read 3, iclass 6, count 2 2006.201.14:23:32.72#ibcon#read 3, iclass 6, count 2 2006.201.14:23:32.72#ibcon#about to read 4, iclass 6, count 2 2006.201.14:23:32.72#ibcon#read 4, iclass 6, count 2 2006.201.14:23:32.72#ibcon#about to read 5, iclass 6, count 2 2006.201.14:23:32.72#ibcon#read 5, iclass 6, count 2 2006.201.14:23:32.72#ibcon#about to read 6, iclass 6, count 2 2006.201.14:23:32.72#ibcon#read 6, iclass 6, count 2 2006.201.14:23:32.72#ibcon#end of sib2, iclass 6, count 2 2006.201.14:23:32.72#ibcon#*after write, iclass 6, count 2 2006.201.14:23:32.72#ibcon#*before return 0, iclass 6, count 2 2006.201.14:23:32.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:32.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.14:23:32.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.14:23:32.72#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:32.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:32.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:32.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:32.84#ibcon#enter wrdev, iclass 6, count 0 2006.201.14:23:32.84#ibcon#first serial, iclass 6, count 0 2006.201.14:23:32.84#ibcon#enter sib2, iclass 6, count 0 2006.201.14:23:32.84#ibcon#flushed, iclass 6, count 0 2006.201.14:23:32.84#ibcon#about to write, iclass 6, count 0 2006.201.14:23:32.84#ibcon#wrote, iclass 6, count 0 2006.201.14:23:32.84#ibcon#about to read 3, iclass 6, count 0 2006.201.14:23:32.86#ibcon#read 3, iclass 6, count 0 2006.201.14:23:32.86#ibcon#about to read 4, iclass 6, count 0 2006.201.14:23:32.86#ibcon#read 4, iclass 6, count 0 2006.201.14:23:32.86#ibcon#about to read 5, iclass 6, count 0 2006.201.14:23:32.86#ibcon#read 5, iclass 6, count 0 2006.201.14:23:32.86#ibcon#about to read 6, iclass 6, count 0 2006.201.14:23:32.86#ibcon#read 6, iclass 6, count 0 2006.201.14:23:32.86#ibcon#end of sib2, iclass 6, count 0 2006.201.14:23:32.86#ibcon#*mode == 0, iclass 6, count 0 2006.201.14:23:32.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.14:23:32.86#ibcon#[27=USB\r\n] 2006.201.14:23:32.86#ibcon#*before write, iclass 6, count 0 2006.201.14:23:32.86#ibcon#enter sib2, iclass 6, count 0 2006.201.14:23:32.86#ibcon#flushed, iclass 6, count 0 2006.201.14:23:32.86#ibcon#about to write, iclass 6, count 0 2006.201.14:23:32.86#ibcon#wrote, iclass 6, count 0 2006.201.14:23:32.86#ibcon#about to read 3, iclass 6, count 0 2006.201.14:23:32.89#ibcon#read 3, iclass 6, count 0 2006.201.14:23:32.89#ibcon#about to read 4, iclass 6, count 0 2006.201.14:23:32.89#ibcon#read 4, iclass 6, count 0 2006.201.14:23:32.89#ibcon#about to read 5, iclass 6, count 0 2006.201.14:23:32.89#ibcon#read 5, iclass 6, count 0 2006.201.14:23:32.89#ibcon#about to read 6, iclass 6, count 0 2006.201.14:23:32.89#ibcon#read 6, iclass 6, count 0 2006.201.14:23:32.89#ibcon#end of sib2, iclass 6, count 0 2006.201.14:23:32.89#ibcon#*after write, iclass 6, count 0 2006.201.14:23:32.89#ibcon#*before return 0, iclass 6, count 0 2006.201.14:23:32.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:32.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.14:23:32.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.14:23:32.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.14:23:32.89$vck44/vblo=8,744.99 2006.201.14:23:32.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.14:23:32.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.14:23:32.89#ibcon#ireg 17 cls_cnt 0 2006.201.14:23:32.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:32.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:32.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:32.89#ibcon#enter wrdev, iclass 10, count 0 2006.201.14:23:32.89#ibcon#first serial, iclass 10, count 0 2006.201.14:23:32.89#ibcon#enter sib2, iclass 10, count 0 2006.201.14:23:32.89#ibcon#flushed, iclass 10, count 0 2006.201.14:23:32.89#ibcon#about to write, iclass 10, count 0 2006.201.14:23:32.89#ibcon#wrote, iclass 10, count 0 2006.201.14:23:32.89#ibcon#about to read 3, iclass 10, count 0 2006.201.14:23:32.91#ibcon#read 3, iclass 10, count 0 2006.201.14:23:32.91#ibcon#about to read 4, iclass 10, count 0 2006.201.14:23:32.91#ibcon#read 4, iclass 10, count 0 2006.201.14:23:32.91#ibcon#about to read 5, iclass 10, count 0 2006.201.14:23:32.91#ibcon#read 5, iclass 10, count 0 2006.201.14:23:32.91#ibcon#about to read 6, iclass 10, count 0 2006.201.14:23:32.91#ibcon#read 6, iclass 10, count 0 2006.201.14:23:32.91#ibcon#end of sib2, iclass 10, count 0 2006.201.14:23:32.91#ibcon#*mode == 0, iclass 10, count 0 2006.201.14:23:32.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.14:23:32.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:23:32.91#ibcon#*before write, iclass 10, count 0 2006.201.14:23:32.91#ibcon#enter sib2, iclass 10, count 0 2006.201.14:23:32.91#ibcon#flushed, iclass 10, count 0 2006.201.14:23:32.91#ibcon#about to write, iclass 10, count 0 2006.201.14:23:32.91#ibcon#wrote, iclass 10, count 0 2006.201.14:23:32.91#ibcon#about to read 3, iclass 10, count 0 2006.201.14:23:32.95#ibcon#read 3, iclass 10, count 0 2006.201.14:23:32.95#ibcon#about to read 4, iclass 10, count 0 2006.201.14:23:32.95#ibcon#read 4, iclass 10, count 0 2006.201.14:23:32.95#ibcon#about to read 5, iclass 10, count 0 2006.201.14:23:32.95#ibcon#read 5, iclass 10, count 0 2006.201.14:23:32.95#ibcon#about to read 6, iclass 10, count 0 2006.201.14:23:32.95#ibcon#read 6, iclass 10, count 0 2006.201.14:23:32.95#ibcon#end of sib2, iclass 10, count 0 2006.201.14:23:32.95#ibcon#*after write, iclass 10, count 0 2006.201.14:23:32.95#ibcon#*before return 0, iclass 10, count 0 2006.201.14:23:32.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:32.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.14:23:32.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.14:23:32.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.14:23:32.95$vck44/vb=8,4 2006.201.14:23:32.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.14:23:32.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.14:23:32.95#ibcon#ireg 11 cls_cnt 2 2006.201.14:23:32.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:33.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:33.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:33.01#ibcon#enter wrdev, iclass 12, count 2 2006.201.14:23:33.01#ibcon#first serial, iclass 12, count 2 2006.201.14:23:33.01#ibcon#enter sib2, iclass 12, count 2 2006.201.14:23:33.01#ibcon#flushed, iclass 12, count 2 2006.201.14:23:33.01#ibcon#about to write, iclass 12, count 2 2006.201.14:23:33.01#ibcon#wrote, iclass 12, count 2 2006.201.14:23:33.01#ibcon#about to read 3, iclass 12, count 2 2006.201.14:23:33.03#ibcon#read 3, iclass 12, count 2 2006.201.14:23:33.03#ibcon#about to read 4, iclass 12, count 2 2006.201.14:23:33.03#ibcon#read 4, iclass 12, count 2 2006.201.14:23:33.03#ibcon#about to read 5, iclass 12, count 2 2006.201.14:23:33.03#ibcon#read 5, iclass 12, count 2 2006.201.14:23:33.03#ibcon#about to read 6, iclass 12, count 2 2006.201.14:23:33.03#ibcon#read 6, iclass 12, count 2 2006.201.14:23:33.03#ibcon#end of sib2, iclass 12, count 2 2006.201.14:23:33.03#ibcon#*mode == 0, iclass 12, count 2 2006.201.14:23:33.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.14:23:33.03#ibcon#[27=AT08-04\r\n] 2006.201.14:23:33.03#ibcon#*before write, iclass 12, count 2 2006.201.14:23:33.03#ibcon#enter sib2, iclass 12, count 2 2006.201.14:23:33.03#ibcon#flushed, iclass 12, count 2 2006.201.14:23:33.03#ibcon#about to write, iclass 12, count 2 2006.201.14:23:33.03#ibcon#wrote, iclass 12, count 2 2006.201.14:23:33.03#ibcon#about to read 3, iclass 12, count 2 2006.201.14:23:33.06#ibcon#read 3, iclass 12, count 2 2006.201.14:23:33.06#ibcon#about to read 4, iclass 12, count 2 2006.201.14:23:33.06#ibcon#read 4, iclass 12, count 2 2006.201.14:23:33.06#ibcon#about to read 5, iclass 12, count 2 2006.201.14:23:33.06#ibcon#read 5, iclass 12, count 2 2006.201.14:23:33.06#ibcon#about to read 6, iclass 12, count 2 2006.201.14:23:33.06#ibcon#read 6, iclass 12, count 2 2006.201.14:23:33.06#ibcon#end of sib2, iclass 12, count 2 2006.201.14:23:33.06#ibcon#*after write, iclass 12, count 2 2006.201.14:23:33.06#ibcon#*before return 0, iclass 12, count 2 2006.201.14:23:33.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:33.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.14:23:33.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.14:23:33.06#ibcon#ireg 7 cls_cnt 0 2006.201.14:23:33.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:33.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:33.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:33.18#ibcon#enter wrdev, iclass 12, count 0 2006.201.14:23:33.18#ibcon#first serial, iclass 12, count 0 2006.201.14:23:33.18#ibcon#enter sib2, iclass 12, count 0 2006.201.14:23:33.18#ibcon#flushed, iclass 12, count 0 2006.201.14:23:33.18#ibcon#about to write, iclass 12, count 0 2006.201.14:23:33.18#ibcon#wrote, iclass 12, count 0 2006.201.14:23:33.18#ibcon#about to read 3, iclass 12, count 0 2006.201.14:23:33.20#ibcon#read 3, iclass 12, count 0 2006.201.14:23:33.20#ibcon#about to read 4, iclass 12, count 0 2006.201.14:23:33.20#ibcon#read 4, iclass 12, count 0 2006.201.14:23:33.20#ibcon#about to read 5, iclass 12, count 0 2006.201.14:23:33.20#ibcon#read 5, iclass 12, count 0 2006.201.14:23:33.20#ibcon#about to read 6, iclass 12, count 0 2006.201.14:23:33.20#ibcon#read 6, iclass 12, count 0 2006.201.14:23:33.20#ibcon#end of sib2, iclass 12, count 0 2006.201.14:23:33.20#ibcon#*mode == 0, iclass 12, count 0 2006.201.14:23:33.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.14:23:33.20#ibcon#[27=USB\r\n] 2006.201.14:23:33.20#ibcon#*before write, iclass 12, count 0 2006.201.14:23:33.20#ibcon#enter sib2, iclass 12, count 0 2006.201.14:23:33.20#ibcon#flushed, iclass 12, count 0 2006.201.14:23:33.20#ibcon#about to write, iclass 12, count 0 2006.201.14:23:33.20#ibcon#wrote, iclass 12, count 0 2006.201.14:23:33.20#ibcon#about to read 3, iclass 12, count 0 2006.201.14:23:33.23#ibcon#read 3, iclass 12, count 0 2006.201.14:23:33.23#ibcon#about to read 4, iclass 12, count 0 2006.201.14:23:33.23#ibcon#read 4, iclass 12, count 0 2006.201.14:23:33.23#ibcon#about to read 5, iclass 12, count 0 2006.201.14:23:33.23#ibcon#read 5, iclass 12, count 0 2006.201.14:23:33.23#ibcon#about to read 6, iclass 12, count 0 2006.201.14:23:33.23#ibcon#read 6, iclass 12, count 0 2006.201.14:23:33.23#ibcon#end of sib2, iclass 12, count 0 2006.201.14:23:33.23#ibcon#*after write, iclass 12, count 0 2006.201.14:23:33.23#ibcon#*before return 0, iclass 12, count 0 2006.201.14:23:33.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:33.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.14:23:33.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.14:23:33.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.14:23:33.23$vck44/vabw=wide 2006.201.14:23:33.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.14:23:33.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.14:23:33.23#ibcon#ireg 8 cls_cnt 0 2006.201.14:23:33.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:33.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:33.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:33.23#ibcon#enter wrdev, iclass 14, count 0 2006.201.14:23:33.23#ibcon#first serial, iclass 14, count 0 2006.201.14:23:33.23#ibcon#enter sib2, iclass 14, count 0 2006.201.14:23:33.23#ibcon#flushed, iclass 14, count 0 2006.201.14:23:33.23#ibcon#about to write, iclass 14, count 0 2006.201.14:23:33.23#ibcon#wrote, iclass 14, count 0 2006.201.14:23:33.23#ibcon#about to read 3, iclass 14, count 0 2006.201.14:23:33.25#ibcon#read 3, iclass 14, count 0 2006.201.14:23:33.25#ibcon#about to read 4, iclass 14, count 0 2006.201.14:23:33.25#ibcon#read 4, iclass 14, count 0 2006.201.14:23:33.25#ibcon#about to read 5, iclass 14, count 0 2006.201.14:23:33.25#ibcon#read 5, iclass 14, count 0 2006.201.14:23:33.25#ibcon#about to read 6, iclass 14, count 0 2006.201.14:23:33.25#ibcon#read 6, iclass 14, count 0 2006.201.14:23:33.25#ibcon#end of sib2, iclass 14, count 0 2006.201.14:23:33.25#ibcon#*mode == 0, iclass 14, count 0 2006.201.14:23:33.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.14:23:33.25#ibcon#[25=BW32\r\n] 2006.201.14:23:33.25#ibcon#*before write, iclass 14, count 0 2006.201.14:23:33.25#ibcon#enter sib2, iclass 14, count 0 2006.201.14:23:33.25#ibcon#flushed, iclass 14, count 0 2006.201.14:23:33.25#ibcon#about to write, iclass 14, count 0 2006.201.14:23:33.25#ibcon#wrote, iclass 14, count 0 2006.201.14:23:33.25#ibcon#about to read 3, iclass 14, count 0 2006.201.14:23:33.28#ibcon#read 3, iclass 14, count 0 2006.201.14:23:33.28#ibcon#about to read 4, iclass 14, count 0 2006.201.14:23:33.28#ibcon#read 4, iclass 14, count 0 2006.201.14:23:33.28#ibcon#about to read 5, iclass 14, count 0 2006.201.14:23:33.28#ibcon#read 5, iclass 14, count 0 2006.201.14:23:33.28#ibcon#about to read 6, iclass 14, count 0 2006.201.14:23:33.28#ibcon#read 6, iclass 14, count 0 2006.201.14:23:33.28#ibcon#end of sib2, iclass 14, count 0 2006.201.14:23:33.28#ibcon#*after write, iclass 14, count 0 2006.201.14:23:33.28#ibcon#*before return 0, iclass 14, count 0 2006.201.14:23:33.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:33.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.14:23:33.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.14:23:33.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.14:23:33.28$vck44/vbbw=wide 2006.201.14:23:33.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.14:23:33.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.14:23:33.28#ibcon#ireg 8 cls_cnt 0 2006.201.14:23:33.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:23:33.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:23:33.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:23:33.35#ibcon#enter wrdev, iclass 16, count 0 2006.201.14:23:33.35#ibcon#first serial, iclass 16, count 0 2006.201.14:23:33.35#ibcon#enter sib2, iclass 16, count 0 2006.201.14:23:33.35#ibcon#flushed, iclass 16, count 0 2006.201.14:23:33.35#ibcon#about to write, iclass 16, count 0 2006.201.14:23:33.35#ibcon#wrote, iclass 16, count 0 2006.201.14:23:33.35#ibcon#about to read 3, iclass 16, count 0 2006.201.14:23:33.37#ibcon#read 3, iclass 16, count 0 2006.201.14:23:33.37#ibcon#about to read 4, iclass 16, count 0 2006.201.14:23:33.37#ibcon#read 4, iclass 16, count 0 2006.201.14:23:33.37#ibcon#about to read 5, iclass 16, count 0 2006.201.14:23:33.37#ibcon#read 5, iclass 16, count 0 2006.201.14:23:33.37#ibcon#about to read 6, iclass 16, count 0 2006.201.14:23:33.37#ibcon#read 6, iclass 16, count 0 2006.201.14:23:33.37#ibcon#end of sib2, iclass 16, count 0 2006.201.14:23:33.37#ibcon#*mode == 0, iclass 16, count 0 2006.201.14:23:33.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.14:23:33.37#ibcon#[27=BW32\r\n] 2006.201.14:23:33.37#ibcon#*before write, iclass 16, count 0 2006.201.14:23:33.37#ibcon#enter sib2, iclass 16, count 0 2006.201.14:23:33.37#ibcon#flushed, iclass 16, count 0 2006.201.14:23:33.37#ibcon#about to write, iclass 16, count 0 2006.201.14:23:33.37#ibcon#wrote, iclass 16, count 0 2006.201.14:23:33.37#ibcon#about to read 3, iclass 16, count 0 2006.201.14:23:33.40#ibcon#read 3, iclass 16, count 0 2006.201.14:23:33.40#ibcon#about to read 4, iclass 16, count 0 2006.201.14:23:33.40#ibcon#read 4, iclass 16, count 0 2006.201.14:23:33.40#ibcon#about to read 5, iclass 16, count 0 2006.201.14:23:33.40#ibcon#read 5, iclass 16, count 0 2006.201.14:23:33.40#ibcon#about to read 6, iclass 16, count 0 2006.201.14:23:33.40#ibcon#read 6, iclass 16, count 0 2006.201.14:23:33.40#ibcon#end of sib2, iclass 16, count 0 2006.201.14:23:33.40#ibcon#*after write, iclass 16, count 0 2006.201.14:23:33.40#ibcon#*before return 0, iclass 16, count 0 2006.201.14:23:33.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:23:33.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:23:33.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.14:23:33.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.14:23:33.40$setupk4/ifdk4 2006.201.14:23:33.40$ifdk4/lo= 2006.201.14:23:33.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:23:33.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:23:33.40$ifdk4/patch= 2006.201.14:23:33.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:23:33.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:23:33.40$setupk4/!*+20s 2006.201.14:23:36.72#abcon#<5=/05 1.9 3.0 20.811001003.5\r\n> 2006.201.14:23:36.74#abcon#{5=INTERFACE CLEAR} 2006.201.14:23:36.80#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:23:46.89#abcon#<5=/05 1.9 3.0 20.801001003.4\r\n> 2006.201.14:23:46.91#abcon#{5=INTERFACE CLEAR} 2006.201.14:23:46.97#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:23:47.14#trakl#Source acquired 2006.201.14:23:47.88$setupk4/"tpicd 2006.201.14:23:47.88$setupk4/echo=off 2006.201.14:23:47.88$setupk4/xlog=off 2006.201.14:23:47.88:!2006.201.14:29:05 2006.201.14:23:48.14#flagr#flagr/antenna,acquired 2006.201.14:29:05.00:preob 2006.201.14:29:05.14/onsource/TRACKING 2006.201.14:29:05.14:!2006.201.14:29:15 2006.201.14:29:15.00:"tape 2006.201.14:29:15.00:"st=record 2006.201.14:29:15.00:data_valid=on 2006.201.14:29:15.00:midob 2006.201.14:29:15.14/onsource/TRACKING 2006.201.14:29:15.14/wx/20.78,1003.6,100 2006.201.14:29:15.27/cable/+6.4737E-03 2006.201.14:29:16.36/va/01,08,usb,yes,29,31 2006.201.14:29:16.36/va/02,07,usb,yes,31,32 2006.201.14:29:16.36/va/03,08,usb,yes,28,29 2006.201.14:29:16.36/va/04,07,usb,yes,32,34 2006.201.14:29:16.36/va/05,04,usb,yes,28,29 2006.201.14:29:16.36/va/06,05,usb,yes,28,28 2006.201.14:29:16.36/va/07,05,usb,yes,27,29 2006.201.14:29:16.36/va/08,04,usb,yes,27,33 2006.201.14:29:16.59/valo/01,524.99,yes,locked 2006.201.14:29:16.59/valo/02,534.99,yes,locked 2006.201.14:29:16.59/valo/03,564.99,yes,locked 2006.201.14:29:16.59/valo/04,624.99,yes,locked 2006.201.14:29:16.59/valo/05,734.99,yes,locked 2006.201.14:29:16.59/valo/06,814.99,yes,locked 2006.201.14:29:16.59/valo/07,864.99,yes,locked 2006.201.14:29:16.59/valo/08,884.99,yes,locked 2006.201.14:29:17.68/vb/01,04,usb,yes,28,26 2006.201.14:29:17.68/vb/02,05,usb,yes,27,27 2006.201.14:29:17.68/vb/03,04,usb,yes,28,31 2006.201.14:29:17.68/vb/04,05,usb,yes,28,27 2006.201.14:29:17.68/vb/05,04,usb,yes,25,27 2006.201.14:29:17.68/vb/06,04,usb,yes,29,25 2006.201.14:29:17.68/vb/07,04,usb,yes,29,29 2006.201.14:29:17.68/vb/08,04,usb,yes,27,30 2006.201.14:29:17.91/vblo/01,629.99,yes,locked 2006.201.14:29:17.91/vblo/02,634.99,yes,locked 2006.201.14:29:17.91/vblo/03,649.99,yes,locked 2006.201.14:29:17.91/vblo/04,679.99,yes,locked 2006.201.14:29:17.91/vblo/05,709.99,yes,locked 2006.201.14:29:17.91/vblo/06,719.99,yes,locked 2006.201.14:29:17.91/vblo/07,734.99,yes,locked 2006.201.14:29:17.91/vblo/08,744.99,yes,locked 2006.201.14:29:18.06/vabw/8 2006.201.14:29:18.21/vbbw/8 2006.201.14:29:18.34/xfe/off,on,14.5 2006.201.14:29:18.73/ifatt/23,28,28,28 2006.201.14:29:19.06/fmout-gps/S +4.53E-07 2006.201.14:29:19.13:!2006.201.14:33:05 2006.201.14:33:05.00:data_valid=off 2006.201.14:33:05.00:"et 2006.201.14:33:05.00:!+3s 2006.201.14:33:08.02:"tape 2006.201.14:33:08.02:postob 2006.201.14:33:08.13/cable/+6.4770E-03 2006.201.14:33:08.13/wx/20.77,1003.6,100 2006.201.14:33:08.21/fmout-gps/S +4.57E-07 2006.201.14:33:08.21:scan_name=201-1436,jd0607,80 2006.201.14:33:08.21:source=2136+141,213901.31,142336.0,2000.0,cw 2006.201.14:33:09.14#flagr#flagr/antenna,new-source 2006.201.14:33:09.14:checkk5 2006.201.14:33:09.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:33:09.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:33:10.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:33:10.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:33:11.02/chk_obsdata//k5ts1/T2011429??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.14:33:11.39/chk_obsdata//k5ts2/T2011429??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.14:33:11.76/chk_obsdata//k5ts3/T2011429??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.14:33:12.12/chk_obsdata//k5ts4/T2011429??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.14:33:12.82/k5log//k5ts1_log_newline 2006.201.14:33:13.50/k5log//k5ts2_log_newline 2006.201.14:33:14.19/k5log//k5ts3_log_newline 2006.201.14:33:14.88/k5log//k5ts4_log_newline 2006.201.14:33:14.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:33:14.90:setupk4=1 2006.201.14:33:14.90$setupk4/echo=on 2006.201.14:33:14.90$setupk4/pcalon 2006.201.14:33:14.90$pcalon/"no phase cal control is implemented here 2006.201.14:33:14.90$setupk4/"tpicd=stop 2006.201.14:33:14.90$setupk4/"rec=synch_on 2006.201.14:33:14.90$setupk4/"rec_mode=128 2006.201.14:33:14.90$setupk4/!* 2006.201.14:33:14.90$setupk4/recpk4 2006.201.14:33:14.90$recpk4/recpatch= 2006.201.14:33:14.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:33:14.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:33:14.91$setupk4/vck44 2006.201.14:33:14.91$vck44/valo=1,524.99 2006.201.14:33:14.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.14:33:14.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.14:33:14.91#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:14.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:14.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:14.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:14.91#ibcon#enter wrdev, iclass 28, count 0 2006.201.14:33:14.91#ibcon#first serial, iclass 28, count 0 2006.201.14:33:14.91#ibcon#enter sib2, iclass 28, count 0 2006.201.14:33:14.91#ibcon#flushed, iclass 28, count 0 2006.201.14:33:14.91#ibcon#about to write, iclass 28, count 0 2006.201.14:33:14.91#ibcon#wrote, iclass 28, count 0 2006.201.14:33:14.91#ibcon#about to read 3, iclass 28, count 0 2006.201.14:33:14.95#ibcon#read 3, iclass 28, count 0 2006.201.14:33:14.95#ibcon#about to read 4, iclass 28, count 0 2006.201.14:33:14.95#ibcon#read 4, iclass 28, count 0 2006.201.14:33:14.95#ibcon#about to read 5, iclass 28, count 0 2006.201.14:33:14.95#ibcon#read 5, iclass 28, count 0 2006.201.14:33:14.95#ibcon#about to read 6, iclass 28, count 0 2006.201.14:33:14.95#ibcon#read 6, iclass 28, count 0 2006.201.14:33:14.95#ibcon#end of sib2, iclass 28, count 0 2006.201.14:33:14.95#ibcon#*mode == 0, iclass 28, count 0 2006.201.14:33:14.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.14:33:14.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:33:14.95#ibcon#*before write, iclass 28, count 0 2006.201.14:33:14.95#ibcon#enter sib2, iclass 28, count 0 2006.201.14:33:14.95#ibcon#flushed, iclass 28, count 0 2006.201.14:33:14.95#ibcon#about to write, iclass 28, count 0 2006.201.14:33:14.95#ibcon#wrote, iclass 28, count 0 2006.201.14:33:14.95#ibcon#about to read 3, iclass 28, count 0 2006.201.14:33:15.00#ibcon#read 3, iclass 28, count 0 2006.201.14:33:15.00#ibcon#about to read 4, iclass 28, count 0 2006.201.14:33:15.00#ibcon#read 4, iclass 28, count 0 2006.201.14:33:15.00#ibcon#about to read 5, iclass 28, count 0 2006.201.14:33:15.00#ibcon#read 5, iclass 28, count 0 2006.201.14:33:15.00#ibcon#about to read 6, iclass 28, count 0 2006.201.14:33:15.00#ibcon#read 6, iclass 28, count 0 2006.201.14:33:15.00#ibcon#end of sib2, iclass 28, count 0 2006.201.14:33:15.00#ibcon#*after write, iclass 28, count 0 2006.201.14:33:15.00#ibcon#*before return 0, iclass 28, count 0 2006.201.14:33:15.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:15.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:15.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.14:33:15.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.14:33:15.00$vck44/va=1,8 2006.201.14:33:15.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.14:33:15.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.14:33:15.00#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:15.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:15.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:15.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:15.00#ibcon#enter wrdev, iclass 30, count 2 2006.201.14:33:15.00#ibcon#first serial, iclass 30, count 2 2006.201.14:33:15.00#ibcon#enter sib2, iclass 30, count 2 2006.201.14:33:15.00#ibcon#flushed, iclass 30, count 2 2006.201.14:33:15.00#ibcon#about to write, iclass 30, count 2 2006.201.14:33:15.00#ibcon#wrote, iclass 30, count 2 2006.201.14:33:15.00#ibcon#about to read 3, iclass 30, count 2 2006.201.14:33:15.02#ibcon#read 3, iclass 30, count 2 2006.201.14:33:15.02#ibcon#about to read 4, iclass 30, count 2 2006.201.14:33:15.02#ibcon#read 4, iclass 30, count 2 2006.201.14:33:15.02#ibcon#about to read 5, iclass 30, count 2 2006.201.14:33:15.02#ibcon#read 5, iclass 30, count 2 2006.201.14:33:15.02#ibcon#about to read 6, iclass 30, count 2 2006.201.14:33:15.02#ibcon#read 6, iclass 30, count 2 2006.201.14:33:15.02#ibcon#end of sib2, iclass 30, count 2 2006.201.14:33:15.02#ibcon#*mode == 0, iclass 30, count 2 2006.201.14:33:15.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.14:33:15.02#ibcon#[25=AT01-08\r\n] 2006.201.14:33:15.02#ibcon#*before write, iclass 30, count 2 2006.201.14:33:15.02#ibcon#enter sib2, iclass 30, count 2 2006.201.14:33:15.02#ibcon#flushed, iclass 30, count 2 2006.201.14:33:15.02#ibcon#about to write, iclass 30, count 2 2006.201.14:33:15.02#ibcon#wrote, iclass 30, count 2 2006.201.14:33:15.02#ibcon#about to read 3, iclass 30, count 2 2006.201.14:33:15.06#ibcon#read 3, iclass 30, count 2 2006.201.14:33:15.06#ibcon#about to read 4, iclass 30, count 2 2006.201.14:33:15.06#ibcon#read 4, iclass 30, count 2 2006.201.14:33:15.06#ibcon#about to read 5, iclass 30, count 2 2006.201.14:33:15.06#ibcon#read 5, iclass 30, count 2 2006.201.14:33:15.06#ibcon#about to read 6, iclass 30, count 2 2006.201.14:33:15.06#ibcon#read 6, iclass 30, count 2 2006.201.14:33:15.06#ibcon#end of sib2, iclass 30, count 2 2006.201.14:33:15.06#ibcon#*after write, iclass 30, count 2 2006.201.14:33:15.06#ibcon#*before return 0, iclass 30, count 2 2006.201.14:33:15.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:15.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:15.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.14:33:15.06#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:15.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:15.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:15.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:15.18#ibcon#enter wrdev, iclass 30, count 0 2006.201.14:33:15.18#ibcon#first serial, iclass 30, count 0 2006.201.14:33:15.18#ibcon#enter sib2, iclass 30, count 0 2006.201.14:33:15.18#ibcon#flushed, iclass 30, count 0 2006.201.14:33:15.18#ibcon#about to write, iclass 30, count 0 2006.201.14:33:15.18#ibcon#wrote, iclass 30, count 0 2006.201.14:33:15.18#ibcon#about to read 3, iclass 30, count 0 2006.201.14:33:15.21#ibcon#read 3, iclass 30, count 0 2006.201.14:33:15.21#ibcon#about to read 4, iclass 30, count 0 2006.201.14:33:15.21#ibcon#read 4, iclass 30, count 0 2006.201.14:33:15.21#ibcon#about to read 5, iclass 30, count 0 2006.201.14:33:15.21#ibcon#read 5, iclass 30, count 0 2006.201.14:33:15.21#ibcon#about to read 6, iclass 30, count 0 2006.201.14:33:15.21#ibcon#read 6, iclass 30, count 0 2006.201.14:33:15.21#ibcon#end of sib2, iclass 30, count 0 2006.201.14:33:15.21#ibcon#*mode == 0, iclass 30, count 0 2006.201.14:33:15.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.14:33:15.21#ibcon#[25=USB\r\n] 2006.201.14:33:15.21#ibcon#*before write, iclass 30, count 0 2006.201.14:33:15.21#ibcon#enter sib2, iclass 30, count 0 2006.201.14:33:15.21#ibcon#flushed, iclass 30, count 0 2006.201.14:33:15.21#ibcon#about to write, iclass 30, count 0 2006.201.14:33:15.21#ibcon#wrote, iclass 30, count 0 2006.201.14:33:15.21#ibcon#about to read 3, iclass 30, count 0 2006.201.14:33:15.24#ibcon#read 3, iclass 30, count 0 2006.201.14:33:15.24#ibcon#about to read 4, iclass 30, count 0 2006.201.14:33:15.24#ibcon#read 4, iclass 30, count 0 2006.201.14:33:15.24#ibcon#about to read 5, iclass 30, count 0 2006.201.14:33:15.24#ibcon#read 5, iclass 30, count 0 2006.201.14:33:15.24#ibcon#about to read 6, iclass 30, count 0 2006.201.14:33:15.24#ibcon#read 6, iclass 30, count 0 2006.201.14:33:15.24#ibcon#end of sib2, iclass 30, count 0 2006.201.14:33:15.24#ibcon#*after write, iclass 30, count 0 2006.201.14:33:15.24#ibcon#*before return 0, iclass 30, count 0 2006.201.14:33:15.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:15.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:15.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.14:33:15.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.14:33:15.24$vck44/valo=2,534.99 2006.201.14:33:15.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.14:33:15.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.14:33:15.24#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:15.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:15.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:15.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:15.24#ibcon#enter wrdev, iclass 32, count 0 2006.201.14:33:15.24#ibcon#first serial, iclass 32, count 0 2006.201.14:33:15.24#ibcon#enter sib2, iclass 32, count 0 2006.201.14:33:15.24#ibcon#flushed, iclass 32, count 0 2006.201.14:33:15.24#ibcon#about to write, iclass 32, count 0 2006.201.14:33:15.24#ibcon#wrote, iclass 32, count 0 2006.201.14:33:15.24#ibcon#about to read 3, iclass 32, count 0 2006.201.14:33:15.26#ibcon#read 3, iclass 32, count 0 2006.201.14:33:15.26#ibcon#about to read 4, iclass 32, count 0 2006.201.14:33:15.26#ibcon#read 4, iclass 32, count 0 2006.201.14:33:15.26#ibcon#about to read 5, iclass 32, count 0 2006.201.14:33:15.26#ibcon#read 5, iclass 32, count 0 2006.201.14:33:15.26#ibcon#about to read 6, iclass 32, count 0 2006.201.14:33:15.26#ibcon#read 6, iclass 32, count 0 2006.201.14:33:15.26#ibcon#end of sib2, iclass 32, count 0 2006.201.14:33:15.26#ibcon#*mode == 0, iclass 32, count 0 2006.201.14:33:15.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.14:33:15.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:33:15.26#ibcon#*before write, iclass 32, count 0 2006.201.14:33:15.26#ibcon#enter sib2, iclass 32, count 0 2006.201.14:33:15.26#ibcon#flushed, iclass 32, count 0 2006.201.14:33:15.26#ibcon#about to write, iclass 32, count 0 2006.201.14:33:15.26#ibcon#wrote, iclass 32, count 0 2006.201.14:33:15.26#ibcon#about to read 3, iclass 32, count 0 2006.201.14:33:15.30#ibcon#read 3, iclass 32, count 0 2006.201.14:33:15.30#ibcon#about to read 4, iclass 32, count 0 2006.201.14:33:15.30#ibcon#read 4, iclass 32, count 0 2006.201.14:33:15.30#ibcon#about to read 5, iclass 32, count 0 2006.201.14:33:15.30#ibcon#read 5, iclass 32, count 0 2006.201.14:33:15.30#ibcon#about to read 6, iclass 32, count 0 2006.201.14:33:15.30#ibcon#read 6, iclass 32, count 0 2006.201.14:33:15.30#ibcon#end of sib2, iclass 32, count 0 2006.201.14:33:15.30#ibcon#*after write, iclass 32, count 0 2006.201.14:33:15.30#ibcon#*before return 0, iclass 32, count 0 2006.201.14:33:15.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:15.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:15.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.14:33:15.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.14:33:15.30$vck44/va=2,7 2006.201.14:33:15.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.14:33:15.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.14:33:15.30#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:15.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:15.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:15.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:15.36#ibcon#enter wrdev, iclass 34, count 2 2006.201.14:33:15.36#ibcon#first serial, iclass 34, count 2 2006.201.14:33:15.36#ibcon#enter sib2, iclass 34, count 2 2006.201.14:33:15.36#ibcon#flushed, iclass 34, count 2 2006.201.14:33:15.36#ibcon#about to write, iclass 34, count 2 2006.201.14:33:15.36#ibcon#wrote, iclass 34, count 2 2006.201.14:33:15.36#ibcon#about to read 3, iclass 34, count 2 2006.201.14:33:15.38#ibcon#read 3, iclass 34, count 2 2006.201.14:33:15.38#ibcon#about to read 4, iclass 34, count 2 2006.201.14:33:15.38#ibcon#read 4, iclass 34, count 2 2006.201.14:33:15.38#ibcon#about to read 5, iclass 34, count 2 2006.201.14:33:15.38#ibcon#read 5, iclass 34, count 2 2006.201.14:33:15.38#ibcon#about to read 6, iclass 34, count 2 2006.201.14:33:15.38#ibcon#read 6, iclass 34, count 2 2006.201.14:33:15.38#ibcon#end of sib2, iclass 34, count 2 2006.201.14:33:15.38#ibcon#*mode == 0, iclass 34, count 2 2006.201.14:33:15.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.14:33:15.38#ibcon#[25=AT02-07\r\n] 2006.201.14:33:15.38#ibcon#*before write, iclass 34, count 2 2006.201.14:33:15.38#ibcon#enter sib2, iclass 34, count 2 2006.201.14:33:15.38#ibcon#flushed, iclass 34, count 2 2006.201.14:33:15.38#ibcon#about to write, iclass 34, count 2 2006.201.14:33:15.38#ibcon#wrote, iclass 34, count 2 2006.201.14:33:15.38#ibcon#about to read 3, iclass 34, count 2 2006.201.14:33:15.41#ibcon#read 3, iclass 34, count 2 2006.201.14:33:15.41#ibcon#about to read 4, iclass 34, count 2 2006.201.14:33:15.41#ibcon#read 4, iclass 34, count 2 2006.201.14:33:15.41#ibcon#about to read 5, iclass 34, count 2 2006.201.14:33:15.41#ibcon#read 5, iclass 34, count 2 2006.201.14:33:15.41#ibcon#about to read 6, iclass 34, count 2 2006.201.14:33:15.41#ibcon#read 6, iclass 34, count 2 2006.201.14:33:15.41#ibcon#end of sib2, iclass 34, count 2 2006.201.14:33:15.41#ibcon#*after write, iclass 34, count 2 2006.201.14:33:15.41#ibcon#*before return 0, iclass 34, count 2 2006.201.14:33:15.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:15.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:15.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.14:33:15.41#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:15.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:15.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:15.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:15.53#ibcon#enter wrdev, iclass 34, count 0 2006.201.14:33:15.53#ibcon#first serial, iclass 34, count 0 2006.201.14:33:15.53#ibcon#enter sib2, iclass 34, count 0 2006.201.14:33:15.53#ibcon#flushed, iclass 34, count 0 2006.201.14:33:15.53#ibcon#about to write, iclass 34, count 0 2006.201.14:33:15.53#ibcon#wrote, iclass 34, count 0 2006.201.14:33:15.53#ibcon#about to read 3, iclass 34, count 0 2006.201.14:33:15.55#ibcon#read 3, iclass 34, count 0 2006.201.14:33:15.55#ibcon#about to read 4, iclass 34, count 0 2006.201.14:33:15.55#ibcon#read 4, iclass 34, count 0 2006.201.14:33:15.55#ibcon#about to read 5, iclass 34, count 0 2006.201.14:33:15.55#ibcon#read 5, iclass 34, count 0 2006.201.14:33:15.55#ibcon#about to read 6, iclass 34, count 0 2006.201.14:33:15.55#ibcon#read 6, iclass 34, count 0 2006.201.14:33:15.55#ibcon#end of sib2, iclass 34, count 0 2006.201.14:33:15.55#ibcon#*mode == 0, iclass 34, count 0 2006.201.14:33:15.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.14:33:15.55#ibcon#[25=USB\r\n] 2006.201.14:33:15.55#ibcon#*before write, iclass 34, count 0 2006.201.14:33:15.55#ibcon#enter sib2, iclass 34, count 0 2006.201.14:33:15.55#ibcon#flushed, iclass 34, count 0 2006.201.14:33:15.55#ibcon#about to write, iclass 34, count 0 2006.201.14:33:15.55#ibcon#wrote, iclass 34, count 0 2006.201.14:33:15.55#ibcon#about to read 3, iclass 34, count 0 2006.201.14:33:15.58#ibcon#read 3, iclass 34, count 0 2006.201.14:33:15.58#ibcon#about to read 4, iclass 34, count 0 2006.201.14:33:15.58#ibcon#read 4, iclass 34, count 0 2006.201.14:33:15.58#ibcon#about to read 5, iclass 34, count 0 2006.201.14:33:15.58#ibcon#read 5, iclass 34, count 0 2006.201.14:33:15.58#ibcon#about to read 6, iclass 34, count 0 2006.201.14:33:15.58#ibcon#read 6, iclass 34, count 0 2006.201.14:33:15.58#ibcon#end of sib2, iclass 34, count 0 2006.201.14:33:15.58#ibcon#*after write, iclass 34, count 0 2006.201.14:33:15.58#ibcon#*before return 0, iclass 34, count 0 2006.201.14:33:15.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:15.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:15.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.14:33:15.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.14:33:15.58$vck44/valo=3,564.99 2006.201.14:33:15.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.14:33:15.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.14:33:15.58#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:15.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:15.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:15.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:15.58#ibcon#enter wrdev, iclass 36, count 0 2006.201.14:33:15.58#ibcon#first serial, iclass 36, count 0 2006.201.14:33:15.58#ibcon#enter sib2, iclass 36, count 0 2006.201.14:33:15.58#ibcon#flushed, iclass 36, count 0 2006.201.14:33:15.58#ibcon#about to write, iclass 36, count 0 2006.201.14:33:15.58#ibcon#wrote, iclass 36, count 0 2006.201.14:33:15.58#ibcon#about to read 3, iclass 36, count 0 2006.201.14:33:15.60#ibcon#read 3, iclass 36, count 0 2006.201.14:33:15.60#ibcon#about to read 4, iclass 36, count 0 2006.201.14:33:15.60#ibcon#read 4, iclass 36, count 0 2006.201.14:33:15.60#ibcon#about to read 5, iclass 36, count 0 2006.201.14:33:15.60#ibcon#read 5, iclass 36, count 0 2006.201.14:33:15.60#ibcon#about to read 6, iclass 36, count 0 2006.201.14:33:15.60#ibcon#read 6, iclass 36, count 0 2006.201.14:33:15.60#ibcon#end of sib2, iclass 36, count 0 2006.201.14:33:15.60#ibcon#*mode == 0, iclass 36, count 0 2006.201.14:33:15.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.14:33:15.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:33:15.60#ibcon#*before write, iclass 36, count 0 2006.201.14:33:15.60#ibcon#enter sib2, iclass 36, count 0 2006.201.14:33:15.60#ibcon#flushed, iclass 36, count 0 2006.201.14:33:15.60#ibcon#about to write, iclass 36, count 0 2006.201.14:33:15.60#ibcon#wrote, iclass 36, count 0 2006.201.14:33:15.60#ibcon#about to read 3, iclass 36, count 0 2006.201.14:33:15.65#ibcon#read 3, iclass 36, count 0 2006.201.14:33:15.65#ibcon#about to read 4, iclass 36, count 0 2006.201.14:33:15.65#ibcon#read 4, iclass 36, count 0 2006.201.14:33:15.65#ibcon#about to read 5, iclass 36, count 0 2006.201.14:33:15.65#ibcon#read 5, iclass 36, count 0 2006.201.14:33:15.65#ibcon#about to read 6, iclass 36, count 0 2006.201.14:33:15.65#ibcon#read 6, iclass 36, count 0 2006.201.14:33:15.65#ibcon#end of sib2, iclass 36, count 0 2006.201.14:33:15.65#ibcon#*after write, iclass 36, count 0 2006.201.14:33:15.65#ibcon#*before return 0, iclass 36, count 0 2006.201.14:33:15.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:15.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:15.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.14:33:15.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.14:33:15.65$vck44/va=3,8 2006.201.14:33:15.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.14:33:15.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.14:33:15.65#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:15.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:15.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:15.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:15.70#ibcon#enter wrdev, iclass 38, count 2 2006.201.14:33:15.70#ibcon#first serial, iclass 38, count 2 2006.201.14:33:15.70#ibcon#enter sib2, iclass 38, count 2 2006.201.14:33:15.70#ibcon#flushed, iclass 38, count 2 2006.201.14:33:15.70#ibcon#about to write, iclass 38, count 2 2006.201.14:33:15.70#ibcon#wrote, iclass 38, count 2 2006.201.14:33:15.70#ibcon#about to read 3, iclass 38, count 2 2006.201.14:33:15.72#ibcon#read 3, iclass 38, count 2 2006.201.14:33:15.72#ibcon#about to read 4, iclass 38, count 2 2006.201.14:33:15.72#ibcon#read 4, iclass 38, count 2 2006.201.14:33:15.72#ibcon#about to read 5, iclass 38, count 2 2006.201.14:33:15.72#ibcon#read 5, iclass 38, count 2 2006.201.14:33:15.72#ibcon#about to read 6, iclass 38, count 2 2006.201.14:33:15.72#ibcon#read 6, iclass 38, count 2 2006.201.14:33:15.72#ibcon#end of sib2, iclass 38, count 2 2006.201.14:33:15.72#ibcon#*mode == 0, iclass 38, count 2 2006.201.14:33:15.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.14:33:15.72#ibcon#[25=AT03-08\r\n] 2006.201.14:33:15.72#ibcon#*before write, iclass 38, count 2 2006.201.14:33:15.72#ibcon#enter sib2, iclass 38, count 2 2006.201.14:33:15.72#ibcon#flushed, iclass 38, count 2 2006.201.14:33:15.72#ibcon#about to write, iclass 38, count 2 2006.201.14:33:15.72#ibcon#wrote, iclass 38, count 2 2006.201.14:33:15.72#ibcon#about to read 3, iclass 38, count 2 2006.201.14:33:15.75#ibcon#read 3, iclass 38, count 2 2006.201.14:33:15.75#ibcon#about to read 4, iclass 38, count 2 2006.201.14:33:15.75#ibcon#read 4, iclass 38, count 2 2006.201.14:33:15.75#ibcon#about to read 5, iclass 38, count 2 2006.201.14:33:15.75#ibcon#read 5, iclass 38, count 2 2006.201.14:33:15.75#ibcon#about to read 6, iclass 38, count 2 2006.201.14:33:15.75#ibcon#read 6, iclass 38, count 2 2006.201.14:33:15.75#ibcon#end of sib2, iclass 38, count 2 2006.201.14:33:15.75#ibcon#*after write, iclass 38, count 2 2006.201.14:33:15.75#ibcon#*before return 0, iclass 38, count 2 2006.201.14:33:15.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:15.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:15.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.14:33:15.75#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:15.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:15.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:15.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:15.87#ibcon#enter wrdev, iclass 38, count 0 2006.201.14:33:15.87#ibcon#first serial, iclass 38, count 0 2006.201.14:33:15.87#ibcon#enter sib2, iclass 38, count 0 2006.201.14:33:15.87#ibcon#flushed, iclass 38, count 0 2006.201.14:33:15.87#ibcon#about to write, iclass 38, count 0 2006.201.14:33:15.87#ibcon#wrote, iclass 38, count 0 2006.201.14:33:15.87#ibcon#about to read 3, iclass 38, count 0 2006.201.14:33:15.89#ibcon#read 3, iclass 38, count 0 2006.201.14:33:15.89#ibcon#about to read 4, iclass 38, count 0 2006.201.14:33:15.89#ibcon#read 4, iclass 38, count 0 2006.201.14:33:15.89#ibcon#about to read 5, iclass 38, count 0 2006.201.14:33:15.89#ibcon#read 5, iclass 38, count 0 2006.201.14:33:15.89#ibcon#about to read 6, iclass 38, count 0 2006.201.14:33:15.89#ibcon#read 6, iclass 38, count 0 2006.201.14:33:15.89#ibcon#end of sib2, iclass 38, count 0 2006.201.14:33:15.89#ibcon#*mode == 0, iclass 38, count 0 2006.201.14:33:15.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.14:33:15.89#ibcon#[25=USB\r\n] 2006.201.14:33:15.89#ibcon#*before write, iclass 38, count 0 2006.201.14:33:15.89#ibcon#enter sib2, iclass 38, count 0 2006.201.14:33:15.89#ibcon#flushed, iclass 38, count 0 2006.201.14:33:15.89#ibcon#about to write, iclass 38, count 0 2006.201.14:33:15.89#ibcon#wrote, iclass 38, count 0 2006.201.14:33:15.89#ibcon#about to read 3, iclass 38, count 0 2006.201.14:33:15.92#ibcon#read 3, iclass 38, count 0 2006.201.14:33:15.92#ibcon#about to read 4, iclass 38, count 0 2006.201.14:33:15.92#ibcon#read 4, iclass 38, count 0 2006.201.14:33:15.92#ibcon#about to read 5, iclass 38, count 0 2006.201.14:33:15.92#ibcon#read 5, iclass 38, count 0 2006.201.14:33:15.92#ibcon#about to read 6, iclass 38, count 0 2006.201.14:33:15.92#ibcon#read 6, iclass 38, count 0 2006.201.14:33:15.92#ibcon#end of sib2, iclass 38, count 0 2006.201.14:33:15.92#ibcon#*after write, iclass 38, count 0 2006.201.14:33:15.92#ibcon#*before return 0, iclass 38, count 0 2006.201.14:33:15.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:15.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:15.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.14:33:15.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.14:33:15.92$vck44/valo=4,624.99 2006.201.14:33:15.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.14:33:15.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.14:33:15.92#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:15.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:15.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:15.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:15.92#ibcon#enter wrdev, iclass 40, count 0 2006.201.14:33:15.92#ibcon#first serial, iclass 40, count 0 2006.201.14:33:15.92#ibcon#enter sib2, iclass 40, count 0 2006.201.14:33:15.92#ibcon#flushed, iclass 40, count 0 2006.201.14:33:15.92#ibcon#about to write, iclass 40, count 0 2006.201.14:33:15.92#ibcon#wrote, iclass 40, count 0 2006.201.14:33:15.92#ibcon#about to read 3, iclass 40, count 0 2006.201.14:33:15.94#ibcon#read 3, iclass 40, count 0 2006.201.14:33:15.94#ibcon#about to read 4, iclass 40, count 0 2006.201.14:33:15.94#ibcon#read 4, iclass 40, count 0 2006.201.14:33:15.94#ibcon#about to read 5, iclass 40, count 0 2006.201.14:33:15.94#ibcon#read 5, iclass 40, count 0 2006.201.14:33:15.94#ibcon#about to read 6, iclass 40, count 0 2006.201.14:33:15.94#ibcon#read 6, iclass 40, count 0 2006.201.14:33:15.94#ibcon#end of sib2, iclass 40, count 0 2006.201.14:33:15.94#ibcon#*mode == 0, iclass 40, count 0 2006.201.14:33:15.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.14:33:15.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:33:15.94#ibcon#*before write, iclass 40, count 0 2006.201.14:33:15.94#ibcon#enter sib2, iclass 40, count 0 2006.201.14:33:15.94#ibcon#flushed, iclass 40, count 0 2006.201.14:33:15.94#ibcon#about to write, iclass 40, count 0 2006.201.14:33:15.94#ibcon#wrote, iclass 40, count 0 2006.201.14:33:15.94#ibcon#about to read 3, iclass 40, count 0 2006.201.14:33:15.98#ibcon#read 3, iclass 40, count 0 2006.201.14:33:15.98#ibcon#about to read 4, iclass 40, count 0 2006.201.14:33:15.98#ibcon#read 4, iclass 40, count 0 2006.201.14:33:15.98#ibcon#about to read 5, iclass 40, count 0 2006.201.14:33:15.98#ibcon#read 5, iclass 40, count 0 2006.201.14:33:15.98#ibcon#about to read 6, iclass 40, count 0 2006.201.14:33:15.98#ibcon#read 6, iclass 40, count 0 2006.201.14:33:15.98#ibcon#end of sib2, iclass 40, count 0 2006.201.14:33:15.98#ibcon#*after write, iclass 40, count 0 2006.201.14:33:15.98#ibcon#*before return 0, iclass 40, count 0 2006.201.14:33:15.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:15.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:15.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.14:33:15.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.14:33:15.98$vck44/va=4,7 2006.201.14:33:15.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.14:33:15.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.14:33:15.98#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:15.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:16.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:16.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:16.04#ibcon#enter wrdev, iclass 4, count 2 2006.201.14:33:16.04#ibcon#first serial, iclass 4, count 2 2006.201.14:33:16.04#ibcon#enter sib2, iclass 4, count 2 2006.201.14:33:16.04#ibcon#flushed, iclass 4, count 2 2006.201.14:33:16.04#ibcon#about to write, iclass 4, count 2 2006.201.14:33:16.04#ibcon#wrote, iclass 4, count 2 2006.201.14:33:16.04#ibcon#about to read 3, iclass 4, count 2 2006.201.14:33:16.06#ibcon#read 3, iclass 4, count 2 2006.201.14:33:16.06#ibcon#about to read 4, iclass 4, count 2 2006.201.14:33:16.06#ibcon#read 4, iclass 4, count 2 2006.201.14:33:16.06#ibcon#about to read 5, iclass 4, count 2 2006.201.14:33:16.06#ibcon#read 5, iclass 4, count 2 2006.201.14:33:16.06#ibcon#about to read 6, iclass 4, count 2 2006.201.14:33:16.06#ibcon#read 6, iclass 4, count 2 2006.201.14:33:16.06#ibcon#end of sib2, iclass 4, count 2 2006.201.14:33:16.06#ibcon#*mode == 0, iclass 4, count 2 2006.201.14:33:16.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.14:33:16.06#ibcon#[25=AT04-07\r\n] 2006.201.14:33:16.06#ibcon#*before write, iclass 4, count 2 2006.201.14:33:16.06#ibcon#enter sib2, iclass 4, count 2 2006.201.14:33:16.06#ibcon#flushed, iclass 4, count 2 2006.201.14:33:16.06#ibcon#about to write, iclass 4, count 2 2006.201.14:33:16.06#ibcon#wrote, iclass 4, count 2 2006.201.14:33:16.06#ibcon#about to read 3, iclass 4, count 2 2006.201.14:33:16.09#ibcon#read 3, iclass 4, count 2 2006.201.14:33:16.09#ibcon#about to read 4, iclass 4, count 2 2006.201.14:33:16.09#ibcon#read 4, iclass 4, count 2 2006.201.14:33:16.09#ibcon#about to read 5, iclass 4, count 2 2006.201.14:33:16.09#ibcon#read 5, iclass 4, count 2 2006.201.14:33:16.09#ibcon#about to read 6, iclass 4, count 2 2006.201.14:33:16.09#ibcon#read 6, iclass 4, count 2 2006.201.14:33:16.09#ibcon#end of sib2, iclass 4, count 2 2006.201.14:33:16.09#ibcon#*after write, iclass 4, count 2 2006.201.14:33:16.09#ibcon#*before return 0, iclass 4, count 2 2006.201.14:33:16.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:16.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:16.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.14:33:16.09#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:16.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:16.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:16.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:16.21#ibcon#enter wrdev, iclass 4, count 0 2006.201.14:33:16.21#ibcon#first serial, iclass 4, count 0 2006.201.14:33:16.21#ibcon#enter sib2, iclass 4, count 0 2006.201.14:33:16.21#ibcon#flushed, iclass 4, count 0 2006.201.14:33:16.21#ibcon#about to write, iclass 4, count 0 2006.201.14:33:16.21#ibcon#wrote, iclass 4, count 0 2006.201.14:33:16.21#ibcon#about to read 3, iclass 4, count 0 2006.201.14:33:16.23#ibcon#read 3, iclass 4, count 0 2006.201.14:33:16.23#ibcon#about to read 4, iclass 4, count 0 2006.201.14:33:16.23#ibcon#read 4, iclass 4, count 0 2006.201.14:33:16.23#ibcon#about to read 5, iclass 4, count 0 2006.201.14:33:16.23#ibcon#read 5, iclass 4, count 0 2006.201.14:33:16.23#ibcon#about to read 6, iclass 4, count 0 2006.201.14:33:16.23#ibcon#read 6, iclass 4, count 0 2006.201.14:33:16.23#ibcon#end of sib2, iclass 4, count 0 2006.201.14:33:16.23#ibcon#*mode == 0, iclass 4, count 0 2006.201.14:33:16.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.14:33:16.23#ibcon#[25=USB\r\n] 2006.201.14:33:16.23#ibcon#*before write, iclass 4, count 0 2006.201.14:33:16.23#ibcon#enter sib2, iclass 4, count 0 2006.201.14:33:16.23#ibcon#flushed, iclass 4, count 0 2006.201.14:33:16.23#ibcon#about to write, iclass 4, count 0 2006.201.14:33:16.23#ibcon#wrote, iclass 4, count 0 2006.201.14:33:16.23#ibcon#about to read 3, iclass 4, count 0 2006.201.14:33:16.26#ibcon#read 3, iclass 4, count 0 2006.201.14:33:16.26#ibcon#about to read 4, iclass 4, count 0 2006.201.14:33:16.26#ibcon#read 4, iclass 4, count 0 2006.201.14:33:16.26#ibcon#about to read 5, iclass 4, count 0 2006.201.14:33:16.26#ibcon#read 5, iclass 4, count 0 2006.201.14:33:16.26#ibcon#about to read 6, iclass 4, count 0 2006.201.14:33:16.26#ibcon#read 6, iclass 4, count 0 2006.201.14:33:16.26#ibcon#end of sib2, iclass 4, count 0 2006.201.14:33:16.26#ibcon#*after write, iclass 4, count 0 2006.201.14:33:16.26#ibcon#*before return 0, iclass 4, count 0 2006.201.14:33:16.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:16.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:16.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.14:33:16.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.14:33:16.26$vck44/valo=5,734.99 2006.201.14:33:16.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.14:33:16.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.14:33:16.26#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:16.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:33:16.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:33:16.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:33:16.26#ibcon#enter wrdev, iclass 6, count 0 2006.201.14:33:16.26#ibcon#first serial, iclass 6, count 0 2006.201.14:33:16.26#ibcon#enter sib2, iclass 6, count 0 2006.201.14:33:16.26#ibcon#flushed, iclass 6, count 0 2006.201.14:33:16.26#ibcon#about to write, iclass 6, count 0 2006.201.14:33:16.26#ibcon#wrote, iclass 6, count 0 2006.201.14:33:16.26#ibcon#about to read 3, iclass 6, count 0 2006.201.14:33:16.28#ibcon#read 3, iclass 6, count 0 2006.201.14:33:16.28#ibcon#about to read 4, iclass 6, count 0 2006.201.14:33:16.28#ibcon#read 4, iclass 6, count 0 2006.201.14:33:16.28#ibcon#about to read 5, iclass 6, count 0 2006.201.14:33:16.28#ibcon#read 5, iclass 6, count 0 2006.201.14:33:16.28#ibcon#about to read 6, iclass 6, count 0 2006.201.14:33:16.28#ibcon#read 6, iclass 6, count 0 2006.201.14:33:16.28#ibcon#end of sib2, iclass 6, count 0 2006.201.14:33:16.28#ibcon#*mode == 0, iclass 6, count 0 2006.201.14:33:16.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.14:33:16.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:33:16.28#ibcon#*before write, iclass 6, count 0 2006.201.14:33:16.28#ibcon#enter sib2, iclass 6, count 0 2006.201.14:33:16.28#ibcon#flushed, iclass 6, count 0 2006.201.14:33:16.28#ibcon#about to write, iclass 6, count 0 2006.201.14:33:16.28#ibcon#wrote, iclass 6, count 0 2006.201.14:33:16.28#ibcon#about to read 3, iclass 6, count 0 2006.201.14:33:16.32#ibcon#read 3, iclass 6, count 0 2006.201.14:33:16.32#ibcon#about to read 4, iclass 6, count 0 2006.201.14:33:16.32#ibcon#read 4, iclass 6, count 0 2006.201.14:33:16.32#ibcon#about to read 5, iclass 6, count 0 2006.201.14:33:16.32#ibcon#read 5, iclass 6, count 0 2006.201.14:33:16.32#ibcon#about to read 6, iclass 6, count 0 2006.201.14:33:16.32#ibcon#read 6, iclass 6, count 0 2006.201.14:33:16.32#ibcon#end of sib2, iclass 6, count 0 2006.201.14:33:16.32#ibcon#*after write, iclass 6, count 0 2006.201.14:33:16.32#ibcon#*before return 0, iclass 6, count 0 2006.201.14:33:16.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:33:16.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.14:33:16.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.14:33:16.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.14:33:16.32$vck44/va=5,4 2006.201.14:33:16.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.14:33:16.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.14:33:16.32#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:16.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:33:16.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:33:16.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:33:16.38#ibcon#enter wrdev, iclass 10, count 2 2006.201.14:33:16.38#ibcon#first serial, iclass 10, count 2 2006.201.14:33:16.38#ibcon#enter sib2, iclass 10, count 2 2006.201.14:33:16.38#ibcon#flushed, iclass 10, count 2 2006.201.14:33:16.38#ibcon#about to write, iclass 10, count 2 2006.201.14:33:16.38#ibcon#wrote, iclass 10, count 2 2006.201.14:33:16.38#ibcon#about to read 3, iclass 10, count 2 2006.201.14:33:16.40#ibcon#read 3, iclass 10, count 2 2006.201.14:33:16.40#ibcon#about to read 4, iclass 10, count 2 2006.201.14:33:16.40#ibcon#read 4, iclass 10, count 2 2006.201.14:33:16.40#ibcon#about to read 5, iclass 10, count 2 2006.201.14:33:16.40#ibcon#read 5, iclass 10, count 2 2006.201.14:33:16.40#ibcon#about to read 6, iclass 10, count 2 2006.201.14:33:16.40#ibcon#read 6, iclass 10, count 2 2006.201.14:33:16.40#ibcon#end of sib2, iclass 10, count 2 2006.201.14:33:16.40#ibcon#*mode == 0, iclass 10, count 2 2006.201.14:33:16.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.14:33:16.40#ibcon#[25=AT05-04\r\n] 2006.201.14:33:16.40#ibcon#*before write, iclass 10, count 2 2006.201.14:33:16.40#ibcon#enter sib2, iclass 10, count 2 2006.201.14:33:16.40#ibcon#flushed, iclass 10, count 2 2006.201.14:33:16.40#ibcon#about to write, iclass 10, count 2 2006.201.14:33:16.40#ibcon#wrote, iclass 10, count 2 2006.201.14:33:16.40#ibcon#about to read 3, iclass 10, count 2 2006.201.14:33:16.43#ibcon#read 3, iclass 10, count 2 2006.201.14:33:16.43#ibcon#about to read 4, iclass 10, count 2 2006.201.14:33:16.43#ibcon#read 4, iclass 10, count 2 2006.201.14:33:16.43#ibcon#about to read 5, iclass 10, count 2 2006.201.14:33:16.43#ibcon#read 5, iclass 10, count 2 2006.201.14:33:16.43#ibcon#about to read 6, iclass 10, count 2 2006.201.14:33:16.43#ibcon#read 6, iclass 10, count 2 2006.201.14:33:16.43#ibcon#end of sib2, iclass 10, count 2 2006.201.14:33:16.43#ibcon#*after write, iclass 10, count 2 2006.201.14:33:16.43#ibcon#*before return 0, iclass 10, count 2 2006.201.14:33:16.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:33:16.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.14:33:16.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.14:33:16.43#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:16.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:33:16.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:33:16.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:33:16.55#ibcon#enter wrdev, iclass 10, count 0 2006.201.14:33:16.55#ibcon#first serial, iclass 10, count 0 2006.201.14:33:16.55#ibcon#enter sib2, iclass 10, count 0 2006.201.14:33:16.55#ibcon#flushed, iclass 10, count 0 2006.201.14:33:16.55#ibcon#about to write, iclass 10, count 0 2006.201.14:33:16.55#ibcon#wrote, iclass 10, count 0 2006.201.14:33:16.55#ibcon#about to read 3, iclass 10, count 0 2006.201.14:33:16.57#ibcon#read 3, iclass 10, count 0 2006.201.14:33:16.57#ibcon#about to read 4, iclass 10, count 0 2006.201.14:33:16.57#ibcon#read 4, iclass 10, count 0 2006.201.14:33:16.57#ibcon#about to read 5, iclass 10, count 0 2006.201.14:33:16.57#ibcon#read 5, iclass 10, count 0 2006.201.14:33:16.57#ibcon#about to read 6, iclass 10, count 0 2006.201.14:33:16.57#ibcon#read 6, iclass 10, count 0 2006.201.14:33:16.57#ibcon#end of sib2, iclass 10, count 0 2006.201.14:33:16.57#ibcon#*mode == 0, iclass 10, count 0 2006.201.14:33:16.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.14:33:16.57#ibcon#[25=USB\r\n] 2006.201.14:33:16.57#ibcon#*before write, iclass 10, count 0 2006.201.14:33:16.57#ibcon#enter sib2, iclass 10, count 0 2006.201.14:33:16.57#ibcon#flushed, iclass 10, count 0 2006.201.14:33:16.57#ibcon#about to write, iclass 10, count 0 2006.201.14:33:16.57#ibcon#wrote, iclass 10, count 0 2006.201.14:33:16.57#ibcon#about to read 3, iclass 10, count 0 2006.201.14:33:16.60#ibcon#read 3, iclass 10, count 0 2006.201.14:33:16.60#ibcon#about to read 4, iclass 10, count 0 2006.201.14:33:16.60#ibcon#read 4, iclass 10, count 0 2006.201.14:33:16.60#ibcon#about to read 5, iclass 10, count 0 2006.201.14:33:16.60#ibcon#read 5, iclass 10, count 0 2006.201.14:33:16.60#ibcon#about to read 6, iclass 10, count 0 2006.201.14:33:16.60#ibcon#read 6, iclass 10, count 0 2006.201.14:33:16.60#ibcon#end of sib2, iclass 10, count 0 2006.201.14:33:16.60#ibcon#*after write, iclass 10, count 0 2006.201.14:33:16.60#ibcon#*before return 0, iclass 10, count 0 2006.201.14:33:16.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:33:16.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.14:33:16.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.14:33:16.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.14:33:16.60$vck44/valo=6,814.99 2006.201.14:33:16.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.14:33:16.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.14:33:16.60#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:16.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:33:16.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:33:16.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:33:16.60#ibcon#enter wrdev, iclass 12, count 0 2006.201.14:33:16.60#ibcon#first serial, iclass 12, count 0 2006.201.14:33:16.60#ibcon#enter sib2, iclass 12, count 0 2006.201.14:33:16.60#ibcon#flushed, iclass 12, count 0 2006.201.14:33:16.60#ibcon#about to write, iclass 12, count 0 2006.201.14:33:16.60#ibcon#wrote, iclass 12, count 0 2006.201.14:33:16.60#ibcon#about to read 3, iclass 12, count 0 2006.201.14:33:16.62#ibcon#read 3, iclass 12, count 0 2006.201.14:33:16.62#ibcon#about to read 4, iclass 12, count 0 2006.201.14:33:16.62#ibcon#read 4, iclass 12, count 0 2006.201.14:33:16.62#ibcon#about to read 5, iclass 12, count 0 2006.201.14:33:16.62#ibcon#read 5, iclass 12, count 0 2006.201.14:33:16.62#ibcon#about to read 6, iclass 12, count 0 2006.201.14:33:16.62#ibcon#read 6, iclass 12, count 0 2006.201.14:33:16.62#ibcon#end of sib2, iclass 12, count 0 2006.201.14:33:16.62#ibcon#*mode == 0, iclass 12, count 0 2006.201.14:33:16.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.14:33:16.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:33:16.62#ibcon#*before write, iclass 12, count 0 2006.201.14:33:16.62#ibcon#enter sib2, iclass 12, count 0 2006.201.14:33:16.62#ibcon#flushed, iclass 12, count 0 2006.201.14:33:16.62#ibcon#about to write, iclass 12, count 0 2006.201.14:33:16.62#ibcon#wrote, iclass 12, count 0 2006.201.14:33:16.62#ibcon#about to read 3, iclass 12, count 0 2006.201.14:33:16.67#ibcon#read 3, iclass 12, count 0 2006.201.14:33:16.67#ibcon#about to read 4, iclass 12, count 0 2006.201.14:33:16.67#ibcon#read 4, iclass 12, count 0 2006.201.14:33:16.67#ibcon#about to read 5, iclass 12, count 0 2006.201.14:33:16.67#ibcon#read 5, iclass 12, count 0 2006.201.14:33:16.67#ibcon#about to read 6, iclass 12, count 0 2006.201.14:33:16.67#ibcon#read 6, iclass 12, count 0 2006.201.14:33:16.67#ibcon#end of sib2, iclass 12, count 0 2006.201.14:33:16.67#ibcon#*after write, iclass 12, count 0 2006.201.14:33:16.67#ibcon#*before return 0, iclass 12, count 0 2006.201.14:33:16.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:33:16.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.14:33:16.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.14:33:16.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.14:33:16.67$vck44/va=6,5 2006.201.14:33:16.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.14:33:16.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.14:33:16.67#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:16.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:16.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:16.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:16.72#ibcon#enter wrdev, iclass 14, count 2 2006.201.14:33:16.72#ibcon#first serial, iclass 14, count 2 2006.201.14:33:16.72#ibcon#enter sib2, iclass 14, count 2 2006.201.14:33:16.72#ibcon#flushed, iclass 14, count 2 2006.201.14:33:16.72#ibcon#about to write, iclass 14, count 2 2006.201.14:33:16.72#ibcon#wrote, iclass 14, count 2 2006.201.14:33:16.72#ibcon#about to read 3, iclass 14, count 2 2006.201.14:33:16.74#ibcon#read 3, iclass 14, count 2 2006.201.14:33:16.74#ibcon#about to read 4, iclass 14, count 2 2006.201.14:33:16.74#ibcon#read 4, iclass 14, count 2 2006.201.14:33:16.74#ibcon#about to read 5, iclass 14, count 2 2006.201.14:33:16.74#ibcon#read 5, iclass 14, count 2 2006.201.14:33:16.74#ibcon#about to read 6, iclass 14, count 2 2006.201.14:33:16.74#ibcon#read 6, iclass 14, count 2 2006.201.14:33:16.74#ibcon#end of sib2, iclass 14, count 2 2006.201.14:33:16.74#ibcon#*mode == 0, iclass 14, count 2 2006.201.14:33:16.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.14:33:16.74#ibcon#[25=AT06-05\r\n] 2006.201.14:33:16.74#ibcon#*before write, iclass 14, count 2 2006.201.14:33:16.74#ibcon#enter sib2, iclass 14, count 2 2006.201.14:33:16.74#ibcon#flushed, iclass 14, count 2 2006.201.14:33:16.74#ibcon#about to write, iclass 14, count 2 2006.201.14:33:16.74#ibcon#wrote, iclass 14, count 2 2006.201.14:33:16.74#ibcon#about to read 3, iclass 14, count 2 2006.201.14:33:16.77#ibcon#read 3, iclass 14, count 2 2006.201.14:33:16.77#ibcon#about to read 4, iclass 14, count 2 2006.201.14:33:16.77#ibcon#read 4, iclass 14, count 2 2006.201.14:33:16.77#ibcon#about to read 5, iclass 14, count 2 2006.201.14:33:16.77#ibcon#read 5, iclass 14, count 2 2006.201.14:33:16.77#ibcon#about to read 6, iclass 14, count 2 2006.201.14:33:16.77#ibcon#read 6, iclass 14, count 2 2006.201.14:33:16.77#ibcon#end of sib2, iclass 14, count 2 2006.201.14:33:16.77#ibcon#*after write, iclass 14, count 2 2006.201.14:33:16.77#ibcon#*before return 0, iclass 14, count 2 2006.201.14:33:16.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:16.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:16.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.14:33:16.77#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:16.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:16.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:16.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:16.89#ibcon#enter wrdev, iclass 14, count 0 2006.201.14:33:16.89#ibcon#first serial, iclass 14, count 0 2006.201.14:33:16.89#ibcon#enter sib2, iclass 14, count 0 2006.201.14:33:16.89#ibcon#flushed, iclass 14, count 0 2006.201.14:33:16.89#ibcon#about to write, iclass 14, count 0 2006.201.14:33:16.89#ibcon#wrote, iclass 14, count 0 2006.201.14:33:16.89#ibcon#about to read 3, iclass 14, count 0 2006.201.14:33:16.91#ibcon#read 3, iclass 14, count 0 2006.201.14:33:16.91#ibcon#about to read 4, iclass 14, count 0 2006.201.14:33:16.91#ibcon#read 4, iclass 14, count 0 2006.201.14:33:16.91#ibcon#about to read 5, iclass 14, count 0 2006.201.14:33:16.91#ibcon#read 5, iclass 14, count 0 2006.201.14:33:16.91#ibcon#about to read 6, iclass 14, count 0 2006.201.14:33:16.91#ibcon#read 6, iclass 14, count 0 2006.201.14:33:16.91#ibcon#end of sib2, iclass 14, count 0 2006.201.14:33:16.91#ibcon#*mode == 0, iclass 14, count 0 2006.201.14:33:16.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.14:33:16.91#ibcon#[25=USB\r\n] 2006.201.14:33:16.91#ibcon#*before write, iclass 14, count 0 2006.201.14:33:16.91#ibcon#enter sib2, iclass 14, count 0 2006.201.14:33:16.91#ibcon#flushed, iclass 14, count 0 2006.201.14:33:16.91#ibcon#about to write, iclass 14, count 0 2006.201.14:33:16.91#ibcon#wrote, iclass 14, count 0 2006.201.14:33:16.91#ibcon#about to read 3, iclass 14, count 0 2006.201.14:33:16.94#ibcon#read 3, iclass 14, count 0 2006.201.14:33:16.94#ibcon#about to read 4, iclass 14, count 0 2006.201.14:33:16.94#ibcon#read 4, iclass 14, count 0 2006.201.14:33:16.94#ibcon#about to read 5, iclass 14, count 0 2006.201.14:33:16.94#ibcon#read 5, iclass 14, count 0 2006.201.14:33:16.94#ibcon#about to read 6, iclass 14, count 0 2006.201.14:33:16.94#ibcon#read 6, iclass 14, count 0 2006.201.14:33:16.94#ibcon#end of sib2, iclass 14, count 0 2006.201.14:33:16.94#ibcon#*after write, iclass 14, count 0 2006.201.14:33:16.94#ibcon#*before return 0, iclass 14, count 0 2006.201.14:33:16.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:16.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:16.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.14:33:16.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.14:33:16.94$vck44/valo=7,864.99 2006.201.14:33:16.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.14:33:16.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.14:33:16.94#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:16.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:16.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:16.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:16.94#ibcon#enter wrdev, iclass 16, count 0 2006.201.14:33:16.94#ibcon#first serial, iclass 16, count 0 2006.201.14:33:16.94#ibcon#enter sib2, iclass 16, count 0 2006.201.14:33:16.94#ibcon#flushed, iclass 16, count 0 2006.201.14:33:16.94#ibcon#about to write, iclass 16, count 0 2006.201.14:33:16.94#ibcon#wrote, iclass 16, count 0 2006.201.14:33:16.94#ibcon#about to read 3, iclass 16, count 0 2006.201.14:33:16.96#ibcon#read 3, iclass 16, count 0 2006.201.14:33:16.96#ibcon#about to read 4, iclass 16, count 0 2006.201.14:33:16.96#ibcon#read 4, iclass 16, count 0 2006.201.14:33:16.96#ibcon#about to read 5, iclass 16, count 0 2006.201.14:33:16.96#ibcon#read 5, iclass 16, count 0 2006.201.14:33:16.96#ibcon#about to read 6, iclass 16, count 0 2006.201.14:33:16.96#ibcon#read 6, iclass 16, count 0 2006.201.14:33:16.96#ibcon#end of sib2, iclass 16, count 0 2006.201.14:33:16.96#ibcon#*mode == 0, iclass 16, count 0 2006.201.14:33:16.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.14:33:16.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:33:16.96#ibcon#*before write, iclass 16, count 0 2006.201.14:33:16.96#ibcon#enter sib2, iclass 16, count 0 2006.201.14:33:16.96#ibcon#flushed, iclass 16, count 0 2006.201.14:33:16.96#ibcon#about to write, iclass 16, count 0 2006.201.14:33:16.96#ibcon#wrote, iclass 16, count 0 2006.201.14:33:16.96#ibcon#about to read 3, iclass 16, count 0 2006.201.14:33:17.00#ibcon#read 3, iclass 16, count 0 2006.201.14:33:17.00#ibcon#about to read 4, iclass 16, count 0 2006.201.14:33:17.00#ibcon#read 4, iclass 16, count 0 2006.201.14:33:17.00#ibcon#about to read 5, iclass 16, count 0 2006.201.14:33:17.00#ibcon#read 5, iclass 16, count 0 2006.201.14:33:17.00#ibcon#about to read 6, iclass 16, count 0 2006.201.14:33:17.00#ibcon#read 6, iclass 16, count 0 2006.201.14:33:17.00#ibcon#end of sib2, iclass 16, count 0 2006.201.14:33:17.00#ibcon#*after write, iclass 16, count 0 2006.201.14:33:17.00#ibcon#*before return 0, iclass 16, count 0 2006.201.14:33:17.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:17.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:17.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.14:33:17.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.14:33:17.00$vck44/va=7,5 2006.201.14:33:17.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.14:33:17.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.14:33:17.00#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:17.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:17.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:17.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:17.06#ibcon#enter wrdev, iclass 18, count 2 2006.201.14:33:17.06#ibcon#first serial, iclass 18, count 2 2006.201.14:33:17.06#ibcon#enter sib2, iclass 18, count 2 2006.201.14:33:17.06#ibcon#flushed, iclass 18, count 2 2006.201.14:33:17.06#ibcon#about to write, iclass 18, count 2 2006.201.14:33:17.06#ibcon#wrote, iclass 18, count 2 2006.201.14:33:17.06#ibcon#about to read 3, iclass 18, count 2 2006.201.14:33:17.08#ibcon#read 3, iclass 18, count 2 2006.201.14:33:17.08#ibcon#about to read 4, iclass 18, count 2 2006.201.14:33:17.08#ibcon#read 4, iclass 18, count 2 2006.201.14:33:17.08#ibcon#about to read 5, iclass 18, count 2 2006.201.14:33:17.08#ibcon#read 5, iclass 18, count 2 2006.201.14:33:17.08#ibcon#about to read 6, iclass 18, count 2 2006.201.14:33:17.08#ibcon#read 6, iclass 18, count 2 2006.201.14:33:17.08#ibcon#end of sib2, iclass 18, count 2 2006.201.14:33:17.08#ibcon#*mode == 0, iclass 18, count 2 2006.201.14:33:17.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.14:33:17.08#ibcon#[25=AT07-05\r\n] 2006.201.14:33:17.08#ibcon#*before write, iclass 18, count 2 2006.201.14:33:17.08#ibcon#enter sib2, iclass 18, count 2 2006.201.14:33:17.08#ibcon#flushed, iclass 18, count 2 2006.201.14:33:17.08#ibcon#about to write, iclass 18, count 2 2006.201.14:33:17.08#ibcon#wrote, iclass 18, count 2 2006.201.14:33:17.08#ibcon#about to read 3, iclass 18, count 2 2006.201.14:33:17.11#ibcon#read 3, iclass 18, count 2 2006.201.14:33:17.11#ibcon#about to read 4, iclass 18, count 2 2006.201.14:33:17.11#ibcon#read 4, iclass 18, count 2 2006.201.14:33:17.11#ibcon#about to read 5, iclass 18, count 2 2006.201.14:33:17.11#ibcon#read 5, iclass 18, count 2 2006.201.14:33:17.11#ibcon#about to read 6, iclass 18, count 2 2006.201.14:33:17.11#ibcon#read 6, iclass 18, count 2 2006.201.14:33:17.11#ibcon#end of sib2, iclass 18, count 2 2006.201.14:33:17.11#ibcon#*after write, iclass 18, count 2 2006.201.14:33:17.11#ibcon#*before return 0, iclass 18, count 2 2006.201.14:33:17.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:17.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:17.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.14:33:17.11#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:17.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:17.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:17.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:17.23#ibcon#enter wrdev, iclass 18, count 0 2006.201.14:33:17.23#ibcon#first serial, iclass 18, count 0 2006.201.14:33:17.23#ibcon#enter sib2, iclass 18, count 0 2006.201.14:33:17.23#ibcon#flushed, iclass 18, count 0 2006.201.14:33:17.23#ibcon#about to write, iclass 18, count 0 2006.201.14:33:17.23#ibcon#wrote, iclass 18, count 0 2006.201.14:33:17.23#ibcon#about to read 3, iclass 18, count 0 2006.201.14:33:17.25#ibcon#read 3, iclass 18, count 0 2006.201.14:33:17.25#ibcon#about to read 4, iclass 18, count 0 2006.201.14:33:17.25#ibcon#read 4, iclass 18, count 0 2006.201.14:33:17.25#ibcon#about to read 5, iclass 18, count 0 2006.201.14:33:17.25#ibcon#read 5, iclass 18, count 0 2006.201.14:33:17.25#ibcon#about to read 6, iclass 18, count 0 2006.201.14:33:17.25#ibcon#read 6, iclass 18, count 0 2006.201.14:33:17.25#ibcon#end of sib2, iclass 18, count 0 2006.201.14:33:17.25#ibcon#*mode == 0, iclass 18, count 0 2006.201.14:33:17.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.14:33:17.25#ibcon#[25=USB\r\n] 2006.201.14:33:17.25#ibcon#*before write, iclass 18, count 0 2006.201.14:33:17.25#ibcon#enter sib2, iclass 18, count 0 2006.201.14:33:17.25#ibcon#flushed, iclass 18, count 0 2006.201.14:33:17.25#ibcon#about to write, iclass 18, count 0 2006.201.14:33:17.25#ibcon#wrote, iclass 18, count 0 2006.201.14:33:17.25#ibcon#about to read 3, iclass 18, count 0 2006.201.14:33:17.28#ibcon#read 3, iclass 18, count 0 2006.201.14:33:17.28#ibcon#about to read 4, iclass 18, count 0 2006.201.14:33:17.28#ibcon#read 4, iclass 18, count 0 2006.201.14:33:17.28#ibcon#about to read 5, iclass 18, count 0 2006.201.14:33:17.28#ibcon#read 5, iclass 18, count 0 2006.201.14:33:17.28#ibcon#about to read 6, iclass 18, count 0 2006.201.14:33:17.28#ibcon#read 6, iclass 18, count 0 2006.201.14:33:17.28#ibcon#end of sib2, iclass 18, count 0 2006.201.14:33:17.28#ibcon#*after write, iclass 18, count 0 2006.201.14:33:17.28#ibcon#*before return 0, iclass 18, count 0 2006.201.14:33:17.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:17.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:17.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.14:33:17.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.14:33:17.28$vck44/valo=8,884.99 2006.201.14:33:17.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.14:33:17.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.14:33:17.28#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:17.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:17.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:17.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:17.28#ibcon#enter wrdev, iclass 20, count 0 2006.201.14:33:17.28#ibcon#first serial, iclass 20, count 0 2006.201.14:33:17.28#ibcon#enter sib2, iclass 20, count 0 2006.201.14:33:17.28#ibcon#flushed, iclass 20, count 0 2006.201.14:33:17.28#ibcon#about to write, iclass 20, count 0 2006.201.14:33:17.28#ibcon#wrote, iclass 20, count 0 2006.201.14:33:17.28#ibcon#about to read 3, iclass 20, count 0 2006.201.14:33:17.30#ibcon#read 3, iclass 20, count 0 2006.201.14:33:17.30#ibcon#about to read 4, iclass 20, count 0 2006.201.14:33:17.30#ibcon#read 4, iclass 20, count 0 2006.201.14:33:17.30#ibcon#about to read 5, iclass 20, count 0 2006.201.14:33:17.30#ibcon#read 5, iclass 20, count 0 2006.201.14:33:17.30#ibcon#about to read 6, iclass 20, count 0 2006.201.14:33:17.30#ibcon#read 6, iclass 20, count 0 2006.201.14:33:17.30#ibcon#end of sib2, iclass 20, count 0 2006.201.14:33:17.30#ibcon#*mode == 0, iclass 20, count 0 2006.201.14:33:17.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.14:33:17.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:33:17.30#ibcon#*before write, iclass 20, count 0 2006.201.14:33:17.30#ibcon#enter sib2, iclass 20, count 0 2006.201.14:33:17.30#ibcon#flushed, iclass 20, count 0 2006.201.14:33:17.30#ibcon#about to write, iclass 20, count 0 2006.201.14:33:17.30#ibcon#wrote, iclass 20, count 0 2006.201.14:33:17.30#ibcon#about to read 3, iclass 20, count 0 2006.201.14:33:17.34#ibcon#read 3, iclass 20, count 0 2006.201.14:33:17.34#ibcon#about to read 4, iclass 20, count 0 2006.201.14:33:17.34#ibcon#read 4, iclass 20, count 0 2006.201.14:33:17.34#ibcon#about to read 5, iclass 20, count 0 2006.201.14:33:17.34#ibcon#read 5, iclass 20, count 0 2006.201.14:33:17.34#ibcon#about to read 6, iclass 20, count 0 2006.201.14:33:17.34#ibcon#read 6, iclass 20, count 0 2006.201.14:33:17.34#ibcon#end of sib2, iclass 20, count 0 2006.201.14:33:17.34#ibcon#*after write, iclass 20, count 0 2006.201.14:33:17.34#ibcon#*before return 0, iclass 20, count 0 2006.201.14:33:17.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:17.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:17.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.14:33:17.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.14:33:17.34$vck44/va=8,4 2006.201.14:33:17.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.14:33:17.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.14:33:17.34#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:17.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:17.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:17.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:17.40#ibcon#enter wrdev, iclass 22, count 2 2006.201.14:33:17.40#ibcon#first serial, iclass 22, count 2 2006.201.14:33:17.40#ibcon#enter sib2, iclass 22, count 2 2006.201.14:33:17.40#ibcon#flushed, iclass 22, count 2 2006.201.14:33:17.40#ibcon#about to write, iclass 22, count 2 2006.201.14:33:17.40#ibcon#wrote, iclass 22, count 2 2006.201.14:33:17.40#ibcon#about to read 3, iclass 22, count 2 2006.201.14:33:17.42#ibcon#read 3, iclass 22, count 2 2006.201.14:33:17.42#ibcon#about to read 4, iclass 22, count 2 2006.201.14:33:17.42#ibcon#read 4, iclass 22, count 2 2006.201.14:33:17.42#ibcon#about to read 5, iclass 22, count 2 2006.201.14:33:17.42#ibcon#read 5, iclass 22, count 2 2006.201.14:33:17.42#ibcon#about to read 6, iclass 22, count 2 2006.201.14:33:17.42#ibcon#read 6, iclass 22, count 2 2006.201.14:33:17.42#ibcon#end of sib2, iclass 22, count 2 2006.201.14:33:17.42#ibcon#*mode == 0, iclass 22, count 2 2006.201.14:33:17.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.14:33:17.42#ibcon#[25=AT08-04\r\n] 2006.201.14:33:17.42#ibcon#*before write, iclass 22, count 2 2006.201.14:33:17.42#ibcon#enter sib2, iclass 22, count 2 2006.201.14:33:17.42#ibcon#flushed, iclass 22, count 2 2006.201.14:33:17.42#ibcon#about to write, iclass 22, count 2 2006.201.14:33:17.42#ibcon#wrote, iclass 22, count 2 2006.201.14:33:17.42#ibcon#about to read 3, iclass 22, count 2 2006.201.14:33:17.45#ibcon#read 3, iclass 22, count 2 2006.201.14:33:17.45#ibcon#about to read 4, iclass 22, count 2 2006.201.14:33:17.45#ibcon#read 4, iclass 22, count 2 2006.201.14:33:17.45#ibcon#about to read 5, iclass 22, count 2 2006.201.14:33:17.45#ibcon#read 5, iclass 22, count 2 2006.201.14:33:17.45#ibcon#about to read 6, iclass 22, count 2 2006.201.14:33:17.45#ibcon#read 6, iclass 22, count 2 2006.201.14:33:17.45#ibcon#end of sib2, iclass 22, count 2 2006.201.14:33:17.45#ibcon#*after write, iclass 22, count 2 2006.201.14:33:17.45#ibcon#*before return 0, iclass 22, count 2 2006.201.14:33:17.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:17.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:17.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.14:33:17.45#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:17.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:17.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:17.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:17.57#ibcon#enter wrdev, iclass 22, count 0 2006.201.14:33:17.57#ibcon#first serial, iclass 22, count 0 2006.201.14:33:17.57#ibcon#enter sib2, iclass 22, count 0 2006.201.14:33:17.57#ibcon#flushed, iclass 22, count 0 2006.201.14:33:17.57#ibcon#about to write, iclass 22, count 0 2006.201.14:33:17.57#ibcon#wrote, iclass 22, count 0 2006.201.14:33:17.57#ibcon#about to read 3, iclass 22, count 0 2006.201.14:33:17.59#ibcon#read 3, iclass 22, count 0 2006.201.14:33:17.59#ibcon#about to read 4, iclass 22, count 0 2006.201.14:33:17.59#ibcon#read 4, iclass 22, count 0 2006.201.14:33:17.59#ibcon#about to read 5, iclass 22, count 0 2006.201.14:33:17.59#ibcon#read 5, iclass 22, count 0 2006.201.14:33:17.59#ibcon#about to read 6, iclass 22, count 0 2006.201.14:33:17.59#ibcon#read 6, iclass 22, count 0 2006.201.14:33:17.59#ibcon#end of sib2, iclass 22, count 0 2006.201.14:33:17.59#ibcon#*mode == 0, iclass 22, count 0 2006.201.14:33:17.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.14:33:17.59#ibcon#[25=USB\r\n] 2006.201.14:33:17.59#ibcon#*before write, iclass 22, count 0 2006.201.14:33:17.59#ibcon#enter sib2, iclass 22, count 0 2006.201.14:33:17.59#ibcon#flushed, iclass 22, count 0 2006.201.14:33:17.59#ibcon#about to write, iclass 22, count 0 2006.201.14:33:17.59#ibcon#wrote, iclass 22, count 0 2006.201.14:33:17.59#ibcon#about to read 3, iclass 22, count 0 2006.201.14:33:17.62#ibcon#read 3, iclass 22, count 0 2006.201.14:33:17.62#ibcon#about to read 4, iclass 22, count 0 2006.201.14:33:17.62#ibcon#read 4, iclass 22, count 0 2006.201.14:33:17.62#ibcon#about to read 5, iclass 22, count 0 2006.201.14:33:17.62#ibcon#read 5, iclass 22, count 0 2006.201.14:33:17.62#ibcon#about to read 6, iclass 22, count 0 2006.201.14:33:17.62#ibcon#read 6, iclass 22, count 0 2006.201.14:33:17.62#ibcon#end of sib2, iclass 22, count 0 2006.201.14:33:17.62#ibcon#*after write, iclass 22, count 0 2006.201.14:33:17.62#ibcon#*before return 0, iclass 22, count 0 2006.201.14:33:17.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:17.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:17.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.14:33:17.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.14:33:17.62$vck44/vblo=1,629.99 2006.201.14:33:17.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.14:33:17.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.14:33:17.62#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:17.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:17.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:17.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:17.62#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:33:17.62#ibcon#first serial, iclass 24, count 0 2006.201.14:33:17.62#ibcon#enter sib2, iclass 24, count 0 2006.201.14:33:17.62#ibcon#flushed, iclass 24, count 0 2006.201.14:33:17.62#ibcon#about to write, iclass 24, count 0 2006.201.14:33:17.62#ibcon#wrote, iclass 24, count 0 2006.201.14:33:17.62#ibcon#about to read 3, iclass 24, count 0 2006.201.14:33:17.64#ibcon#read 3, iclass 24, count 0 2006.201.14:33:17.64#ibcon#about to read 4, iclass 24, count 0 2006.201.14:33:17.64#ibcon#read 4, iclass 24, count 0 2006.201.14:33:17.64#ibcon#about to read 5, iclass 24, count 0 2006.201.14:33:17.64#ibcon#read 5, iclass 24, count 0 2006.201.14:33:17.64#ibcon#about to read 6, iclass 24, count 0 2006.201.14:33:17.64#ibcon#read 6, iclass 24, count 0 2006.201.14:33:17.64#ibcon#end of sib2, iclass 24, count 0 2006.201.14:33:17.64#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:33:17.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:33:17.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:33:17.64#ibcon#*before write, iclass 24, count 0 2006.201.14:33:17.64#ibcon#enter sib2, iclass 24, count 0 2006.201.14:33:17.64#ibcon#flushed, iclass 24, count 0 2006.201.14:33:17.64#ibcon#about to write, iclass 24, count 0 2006.201.14:33:17.64#ibcon#wrote, iclass 24, count 0 2006.201.14:33:17.64#ibcon#about to read 3, iclass 24, count 0 2006.201.14:33:17.69#ibcon#read 3, iclass 24, count 0 2006.201.14:33:17.69#ibcon#about to read 4, iclass 24, count 0 2006.201.14:33:17.69#ibcon#read 4, iclass 24, count 0 2006.201.14:33:17.69#ibcon#about to read 5, iclass 24, count 0 2006.201.14:33:17.69#ibcon#read 5, iclass 24, count 0 2006.201.14:33:17.69#ibcon#about to read 6, iclass 24, count 0 2006.201.14:33:17.69#ibcon#read 6, iclass 24, count 0 2006.201.14:33:17.69#ibcon#end of sib2, iclass 24, count 0 2006.201.14:33:17.69#ibcon#*after write, iclass 24, count 0 2006.201.14:33:17.69#ibcon#*before return 0, iclass 24, count 0 2006.201.14:33:17.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:17.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:17.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:33:17.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:33:17.69$vck44/vb=1,4 2006.201.14:33:17.69#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.14:33:17.69#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.14:33:17.69#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:17.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:33:17.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:33:17.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:33:17.69#ibcon#enter wrdev, iclass 26, count 2 2006.201.14:33:17.69#ibcon#first serial, iclass 26, count 2 2006.201.14:33:17.69#ibcon#enter sib2, iclass 26, count 2 2006.201.14:33:17.69#ibcon#flushed, iclass 26, count 2 2006.201.14:33:17.69#ibcon#about to write, iclass 26, count 2 2006.201.14:33:17.69#ibcon#wrote, iclass 26, count 2 2006.201.14:33:17.69#ibcon#about to read 3, iclass 26, count 2 2006.201.14:33:17.71#ibcon#read 3, iclass 26, count 2 2006.201.14:33:17.71#ibcon#about to read 4, iclass 26, count 2 2006.201.14:33:17.71#ibcon#read 4, iclass 26, count 2 2006.201.14:33:17.71#ibcon#about to read 5, iclass 26, count 2 2006.201.14:33:17.71#ibcon#read 5, iclass 26, count 2 2006.201.14:33:17.71#ibcon#about to read 6, iclass 26, count 2 2006.201.14:33:17.71#ibcon#read 6, iclass 26, count 2 2006.201.14:33:17.71#ibcon#end of sib2, iclass 26, count 2 2006.201.14:33:17.71#ibcon#*mode == 0, iclass 26, count 2 2006.201.14:33:17.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.14:33:17.71#ibcon#[27=AT01-04\r\n] 2006.201.14:33:17.71#ibcon#*before write, iclass 26, count 2 2006.201.14:33:17.71#ibcon#enter sib2, iclass 26, count 2 2006.201.14:33:17.71#ibcon#flushed, iclass 26, count 2 2006.201.14:33:17.71#ibcon#about to write, iclass 26, count 2 2006.201.14:33:17.71#ibcon#wrote, iclass 26, count 2 2006.201.14:33:17.71#ibcon#about to read 3, iclass 26, count 2 2006.201.14:33:17.74#ibcon#read 3, iclass 26, count 2 2006.201.14:33:17.74#ibcon#about to read 4, iclass 26, count 2 2006.201.14:33:17.74#ibcon#read 4, iclass 26, count 2 2006.201.14:33:17.74#ibcon#about to read 5, iclass 26, count 2 2006.201.14:33:17.74#ibcon#read 5, iclass 26, count 2 2006.201.14:33:17.74#ibcon#about to read 6, iclass 26, count 2 2006.201.14:33:17.74#ibcon#read 6, iclass 26, count 2 2006.201.14:33:17.74#ibcon#end of sib2, iclass 26, count 2 2006.201.14:33:17.74#ibcon#*after write, iclass 26, count 2 2006.201.14:33:17.74#ibcon#*before return 0, iclass 26, count 2 2006.201.14:33:17.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:33:17.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.14:33:17.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.14:33:17.74#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:17.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:33:17.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:33:17.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:33:17.86#ibcon#enter wrdev, iclass 26, count 0 2006.201.14:33:17.86#ibcon#first serial, iclass 26, count 0 2006.201.14:33:17.86#ibcon#enter sib2, iclass 26, count 0 2006.201.14:33:17.86#ibcon#flushed, iclass 26, count 0 2006.201.14:33:17.86#ibcon#about to write, iclass 26, count 0 2006.201.14:33:17.86#ibcon#wrote, iclass 26, count 0 2006.201.14:33:17.86#ibcon#about to read 3, iclass 26, count 0 2006.201.14:33:17.88#ibcon#read 3, iclass 26, count 0 2006.201.14:33:17.88#ibcon#about to read 4, iclass 26, count 0 2006.201.14:33:17.88#ibcon#read 4, iclass 26, count 0 2006.201.14:33:17.88#ibcon#about to read 5, iclass 26, count 0 2006.201.14:33:17.88#ibcon#read 5, iclass 26, count 0 2006.201.14:33:17.88#ibcon#about to read 6, iclass 26, count 0 2006.201.14:33:17.88#ibcon#read 6, iclass 26, count 0 2006.201.14:33:17.88#ibcon#end of sib2, iclass 26, count 0 2006.201.14:33:17.88#ibcon#*mode == 0, iclass 26, count 0 2006.201.14:33:17.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.14:33:17.88#ibcon#[27=USB\r\n] 2006.201.14:33:17.88#ibcon#*before write, iclass 26, count 0 2006.201.14:33:17.88#ibcon#enter sib2, iclass 26, count 0 2006.201.14:33:17.88#ibcon#flushed, iclass 26, count 0 2006.201.14:33:17.88#ibcon#about to write, iclass 26, count 0 2006.201.14:33:17.88#ibcon#wrote, iclass 26, count 0 2006.201.14:33:17.88#ibcon#about to read 3, iclass 26, count 0 2006.201.14:33:17.91#ibcon#read 3, iclass 26, count 0 2006.201.14:33:17.91#ibcon#about to read 4, iclass 26, count 0 2006.201.14:33:17.91#ibcon#read 4, iclass 26, count 0 2006.201.14:33:17.91#ibcon#about to read 5, iclass 26, count 0 2006.201.14:33:17.91#ibcon#read 5, iclass 26, count 0 2006.201.14:33:17.91#ibcon#about to read 6, iclass 26, count 0 2006.201.14:33:17.91#ibcon#read 6, iclass 26, count 0 2006.201.14:33:17.91#ibcon#end of sib2, iclass 26, count 0 2006.201.14:33:17.91#ibcon#*after write, iclass 26, count 0 2006.201.14:33:17.91#ibcon#*before return 0, iclass 26, count 0 2006.201.14:33:17.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:33:17.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.14:33:17.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.14:33:17.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.14:33:17.91$vck44/vblo=2,634.99 2006.201.14:33:17.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.14:33:17.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.14:33:17.91#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:17.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:17.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:17.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:17.91#ibcon#enter wrdev, iclass 28, count 0 2006.201.14:33:17.91#ibcon#first serial, iclass 28, count 0 2006.201.14:33:17.91#ibcon#enter sib2, iclass 28, count 0 2006.201.14:33:17.91#ibcon#flushed, iclass 28, count 0 2006.201.14:33:17.91#ibcon#about to write, iclass 28, count 0 2006.201.14:33:17.91#ibcon#wrote, iclass 28, count 0 2006.201.14:33:17.91#ibcon#about to read 3, iclass 28, count 0 2006.201.14:33:17.93#ibcon#read 3, iclass 28, count 0 2006.201.14:33:17.93#ibcon#about to read 4, iclass 28, count 0 2006.201.14:33:17.93#ibcon#read 4, iclass 28, count 0 2006.201.14:33:17.93#ibcon#about to read 5, iclass 28, count 0 2006.201.14:33:17.93#ibcon#read 5, iclass 28, count 0 2006.201.14:33:17.93#ibcon#about to read 6, iclass 28, count 0 2006.201.14:33:17.93#ibcon#read 6, iclass 28, count 0 2006.201.14:33:17.93#ibcon#end of sib2, iclass 28, count 0 2006.201.14:33:17.93#ibcon#*mode == 0, iclass 28, count 0 2006.201.14:33:17.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.14:33:17.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:33:17.93#ibcon#*before write, iclass 28, count 0 2006.201.14:33:17.93#ibcon#enter sib2, iclass 28, count 0 2006.201.14:33:17.93#ibcon#flushed, iclass 28, count 0 2006.201.14:33:17.93#ibcon#about to write, iclass 28, count 0 2006.201.14:33:17.93#ibcon#wrote, iclass 28, count 0 2006.201.14:33:17.93#ibcon#about to read 3, iclass 28, count 0 2006.201.14:33:17.97#ibcon#read 3, iclass 28, count 0 2006.201.14:33:17.97#ibcon#about to read 4, iclass 28, count 0 2006.201.14:33:17.97#ibcon#read 4, iclass 28, count 0 2006.201.14:33:17.97#ibcon#about to read 5, iclass 28, count 0 2006.201.14:33:17.97#ibcon#read 5, iclass 28, count 0 2006.201.14:33:17.97#ibcon#about to read 6, iclass 28, count 0 2006.201.14:33:17.97#ibcon#read 6, iclass 28, count 0 2006.201.14:33:17.97#ibcon#end of sib2, iclass 28, count 0 2006.201.14:33:17.97#ibcon#*after write, iclass 28, count 0 2006.201.14:33:17.97#ibcon#*before return 0, iclass 28, count 0 2006.201.14:33:17.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:17.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.14:33:17.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.14:33:17.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.14:33:17.97$vck44/vb=2,5 2006.201.14:33:17.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.14:33:17.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.14:33:17.97#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:17.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:18.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:18.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:18.03#ibcon#enter wrdev, iclass 30, count 2 2006.201.14:33:18.03#ibcon#first serial, iclass 30, count 2 2006.201.14:33:18.03#ibcon#enter sib2, iclass 30, count 2 2006.201.14:33:18.03#ibcon#flushed, iclass 30, count 2 2006.201.14:33:18.03#ibcon#about to write, iclass 30, count 2 2006.201.14:33:18.03#ibcon#wrote, iclass 30, count 2 2006.201.14:33:18.03#ibcon#about to read 3, iclass 30, count 2 2006.201.14:33:18.05#ibcon#read 3, iclass 30, count 2 2006.201.14:33:18.05#ibcon#about to read 4, iclass 30, count 2 2006.201.14:33:18.05#ibcon#read 4, iclass 30, count 2 2006.201.14:33:18.05#ibcon#about to read 5, iclass 30, count 2 2006.201.14:33:18.05#ibcon#read 5, iclass 30, count 2 2006.201.14:33:18.05#ibcon#about to read 6, iclass 30, count 2 2006.201.14:33:18.05#ibcon#read 6, iclass 30, count 2 2006.201.14:33:18.05#ibcon#end of sib2, iclass 30, count 2 2006.201.14:33:18.05#ibcon#*mode == 0, iclass 30, count 2 2006.201.14:33:18.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.14:33:18.05#ibcon#[27=AT02-05\r\n] 2006.201.14:33:18.05#ibcon#*before write, iclass 30, count 2 2006.201.14:33:18.05#ibcon#enter sib2, iclass 30, count 2 2006.201.14:33:18.05#ibcon#flushed, iclass 30, count 2 2006.201.14:33:18.05#ibcon#about to write, iclass 30, count 2 2006.201.14:33:18.05#ibcon#wrote, iclass 30, count 2 2006.201.14:33:18.05#ibcon#about to read 3, iclass 30, count 2 2006.201.14:33:18.08#ibcon#read 3, iclass 30, count 2 2006.201.14:33:18.08#ibcon#about to read 4, iclass 30, count 2 2006.201.14:33:18.08#ibcon#read 4, iclass 30, count 2 2006.201.14:33:18.08#ibcon#about to read 5, iclass 30, count 2 2006.201.14:33:18.08#ibcon#read 5, iclass 30, count 2 2006.201.14:33:18.08#ibcon#about to read 6, iclass 30, count 2 2006.201.14:33:18.08#ibcon#read 6, iclass 30, count 2 2006.201.14:33:18.08#ibcon#end of sib2, iclass 30, count 2 2006.201.14:33:18.08#ibcon#*after write, iclass 30, count 2 2006.201.14:33:18.08#ibcon#*before return 0, iclass 30, count 2 2006.201.14:33:18.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:18.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.14:33:18.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.14:33:18.08#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:18.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:18.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:18.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:18.20#ibcon#enter wrdev, iclass 30, count 0 2006.201.14:33:18.20#ibcon#first serial, iclass 30, count 0 2006.201.14:33:18.20#ibcon#enter sib2, iclass 30, count 0 2006.201.14:33:18.20#ibcon#flushed, iclass 30, count 0 2006.201.14:33:18.20#ibcon#about to write, iclass 30, count 0 2006.201.14:33:18.20#ibcon#wrote, iclass 30, count 0 2006.201.14:33:18.20#ibcon#about to read 3, iclass 30, count 0 2006.201.14:33:18.22#ibcon#read 3, iclass 30, count 0 2006.201.14:33:18.22#ibcon#about to read 4, iclass 30, count 0 2006.201.14:33:18.22#ibcon#read 4, iclass 30, count 0 2006.201.14:33:18.22#ibcon#about to read 5, iclass 30, count 0 2006.201.14:33:18.22#ibcon#read 5, iclass 30, count 0 2006.201.14:33:18.22#ibcon#about to read 6, iclass 30, count 0 2006.201.14:33:18.22#ibcon#read 6, iclass 30, count 0 2006.201.14:33:18.22#ibcon#end of sib2, iclass 30, count 0 2006.201.14:33:18.22#ibcon#*mode == 0, iclass 30, count 0 2006.201.14:33:18.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.14:33:18.22#ibcon#[27=USB\r\n] 2006.201.14:33:18.22#ibcon#*before write, iclass 30, count 0 2006.201.14:33:18.22#ibcon#enter sib2, iclass 30, count 0 2006.201.14:33:18.22#ibcon#flushed, iclass 30, count 0 2006.201.14:33:18.22#ibcon#about to write, iclass 30, count 0 2006.201.14:33:18.22#ibcon#wrote, iclass 30, count 0 2006.201.14:33:18.22#ibcon#about to read 3, iclass 30, count 0 2006.201.14:33:18.25#ibcon#read 3, iclass 30, count 0 2006.201.14:33:18.25#ibcon#about to read 4, iclass 30, count 0 2006.201.14:33:18.25#ibcon#read 4, iclass 30, count 0 2006.201.14:33:18.25#ibcon#about to read 5, iclass 30, count 0 2006.201.14:33:18.25#ibcon#read 5, iclass 30, count 0 2006.201.14:33:18.25#ibcon#about to read 6, iclass 30, count 0 2006.201.14:33:18.25#ibcon#read 6, iclass 30, count 0 2006.201.14:33:18.25#ibcon#end of sib2, iclass 30, count 0 2006.201.14:33:18.25#ibcon#*after write, iclass 30, count 0 2006.201.14:33:18.25#ibcon#*before return 0, iclass 30, count 0 2006.201.14:33:18.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:18.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.14:33:18.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.14:33:18.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.14:33:18.25$vck44/vblo=3,649.99 2006.201.14:33:18.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.14:33:18.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.14:33:18.25#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:18.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:18.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:18.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:18.25#ibcon#enter wrdev, iclass 32, count 0 2006.201.14:33:18.25#ibcon#first serial, iclass 32, count 0 2006.201.14:33:18.25#ibcon#enter sib2, iclass 32, count 0 2006.201.14:33:18.25#ibcon#flushed, iclass 32, count 0 2006.201.14:33:18.25#ibcon#about to write, iclass 32, count 0 2006.201.14:33:18.25#ibcon#wrote, iclass 32, count 0 2006.201.14:33:18.25#ibcon#about to read 3, iclass 32, count 0 2006.201.14:33:18.27#ibcon#read 3, iclass 32, count 0 2006.201.14:33:18.27#ibcon#about to read 4, iclass 32, count 0 2006.201.14:33:18.27#ibcon#read 4, iclass 32, count 0 2006.201.14:33:18.27#ibcon#about to read 5, iclass 32, count 0 2006.201.14:33:18.27#ibcon#read 5, iclass 32, count 0 2006.201.14:33:18.27#ibcon#about to read 6, iclass 32, count 0 2006.201.14:33:18.27#ibcon#read 6, iclass 32, count 0 2006.201.14:33:18.27#ibcon#end of sib2, iclass 32, count 0 2006.201.14:33:18.27#ibcon#*mode == 0, iclass 32, count 0 2006.201.14:33:18.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.14:33:18.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:33:18.27#ibcon#*before write, iclass 32, count 0 2006.201.14:33:18.27#ibcon#enter sib2, iclass 32, count 0 2006.201.14:33:18.27#ibcon#flushed, iclass 32, count 0 2006.201.14:33:18.27#ibcon#about to write, iclass 32, count 0 2006.201.14:33:18.27#ibcon#wrote, iclass 32, count 0 2006.201.14:33:18.27#ibcon#about to read 3, iclass 32, count 0 2006.201.14:33:18.31#ibcon#read 3, iclass 32, count 0 2006.201.14:33:18.31#ibcon#about to read 4, iclass 32, count 0 2006.201.14:33:18.31#ibcon#read 4, iclass 32, count 0 2006.201.14:33:18.31#ibcon#about to read 5, iclass 32, count 0 2006.201.14:33:18.31#ibcon#read 5, iclass 32, count 0 2006.201.14:33:18.31#ibcon#about to read 6, iclass 32, count 0 2006.201.14:33:18.31#ibcon#read 6, iclass 32, count 0 2006.201.14:33:18.31#ibcon#end of sib2, iclass 32, count 0 2006.201.14:33:18.31#ibcon#*after write, iclass 32, count 0 2006.201.14:33:18.31#ibcon#*before return 0, iclass 32, count 0 2006.201.14:33:18.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:18.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.14:33:18.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.14:33:18.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.14:33:18.31$vck44/vb=3,4 2006.201.14:33:18.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.14:33:18.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.14:33:18.31#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:18.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:18.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:18.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:18.37#ibcon#enter wrdev, iclass 34, count 2 2006.201.14:33:18.37#ibcon#first serial, iclass 34, count 2 2006.201.14:33:18.37#ibcon#enter sib2, iclass 34, count 2 2006.201.14:33:18.37#ibcon#flushed, iclass 34, count 2 2006.201.14:33:18.37#ibcon#about to write, iclass 34, count 2 2006.201.14:33:18.37#ibcon#wrote, iclass 34, count 2 2006.201.14:33:18.37#ibcon#about to read 3, iclass 34, count 2 2006.201.14:33:18.39#ibcon#read 3, iclass 34, count 2 2006.201.14:33:18.39#ibcon#about to read 4, iclass 34, count 2 2006.201.14:33:18.39#ibcon#read 4, iclass 34, count 2 2006.201.14:33:18.39#ibcon#about to read 5, iclass 34, count 2 2006.201.14:33:18.39#ibcon#read 5, iclass 34, count 2 2006.201.14:33:18.39#ibcon#about to read 6, iclass 34, count 2 2006.201.14:33:18.39#ibcon#read 6, iclass 34, count 2 2006.201.14:33:18.39#ibcon#end of sib2, iclass 34, count 2 2006.201.14:33:18.39#ibcon#*mode == 0, iclass 34, count 2 2006.201.14:33:18.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.14:33:18.39#ibcon#[27=AT03-04\r\n] 2006.201.14:33:18.39#ibcon#*before write, iclass 34, count 2 2006.201.14:33:18.39#ibcon#enter sib2, iclass 34, count 2 2006.201.14:33:18.39#ibcon#flushed, iclass 34, count 2 2006.201.14:33:18.39#ibcon#about to write, iclass 34, count 2 2006.201.14:33:18.39#ibcon#wrote, iclass 34, count 2 2006.201.14:33:18.39#ibcon#about to read 3, iclass 34, count 2 2006.201.14:33:18.43#ibcon#read 3, iclass 34, count 2 2006.201.14:33:18.43#ibcon#about to read 4, iclass 34, count 2 2006.201.14:33:18.43#ibcon#read 4, iclass 34, count 2 2006.201.14:33:18.43#ibcon#about to read 5, iclass 34, count 2 2006.201.14:33:18.43#ibcon#read 5, iclass 34, count 2 2006.201.14:33:18.43#ibcon#about to read 6, iclass 34, count 2 2006.201.14:33:18.43#ibcon#read 6, iclass 34, count 2 2006.201.14:33:18.43#ibcon#end of sib2, iclass 34, count 2 2006.201.14:33:18.43#ibcon#*after write, iclass 34, count 2 2006.201.14:33:18.43#ibcon#*before return 0, iclass 34, count 2 2006.201.14:33:18.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:18.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.14:33:18.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.14:33:18.43#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:18.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:18.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:18.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:18.55#ibcon#enter wrdev, iclass 34, count 0 2006.201.14:33:18.55#ibcon#first serial, iclass 34, count 0 2006.201.14:33:18.55#ibcon#enter sib2, iclass 34, count 0 2006.201.14:33:18.55#ibcon#flushed, iclass 34, count 0 2006.201.14:33:18.55#ibcon#about to write, iclass 34, count 0 2006.201.14:33:18.55#ibcon#wrote, iclass 34, count 0 2006.201.14:33:18.55#ibcon#about to read 3, iclass 34, count 0 2006.201.14:33:18.57#ibcon#read 3, iclass 34, count 0 2006.201.14:33:18.57#ibcon#about to read 4, iclass 34, count 0 2006.201.14:33:18.57#ibcon#read 4, iclass 34, count 0 2006.201.14:33:18.57#ibcon#about to read 5, iclass 34, count 0 2006.201.14:33:18.57#ibcon#read 5, iclass 34, count 0 2006.201.14:33:18.57#ibcon#about to read 6, iclass 34, count 0 2006.201.14:33:18.57#ibcon#read 6, iclass 34, count 0 2006.201.14:33:18.57#ibcon#end of sib2, iclass 34, count 0 2006.201.14:33:18.57#ibcon#*mode == 0, iclass 34, count 0 2006.201.14:33:18.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.14:33:18.57#ibcon#[27=USB\r\n] 2006.201.14:33:18.57#ibcon#*before write, iclass 34, count 0 2006.201.14:33:18.57#ibcon#enter sib2, iclass 34, count 0 2006.201.14:33:18.57#ibcon#flushed, iclass 34, count 0 2006.201.14:33:18.57#ibcon#about to write, iclass 34, count 0 2006.201.14:33:18.57#ibcon#wrote, iclass 34, count 0 2006.201.14:33:18.57#ibcon#about to read 3, iclass 34, count 0 2006.201.14:33:18.60#ibcon#read 3, iclass 34, count 0 2006.201.14:33:18.60#ibcon#about to read 4, iclass 34, count 0 2006.201.14:33:18.60#ibcon#read 4, iclass 34, count 0 2006.201.14:33:18.60#ibcon#about to read 5, iclass 34, count 0 2006.201.14:33:18.60#ibcon#read 5, iclass 34, count 0 2006.201.14:33:18.60#ibcon#about to read 6, iclass 34, count 0 2006.201.14:33:18.60#ibcon#read 6, iclass 34, count 0 2006.201.14:33:18.60#ibcon#end of sib2, iclass 34, count 0 2006.201.14:33:18.60#ibcon#*after write, iclass 34, count 0 2006.201.14:33:18.60#ibcon#*before return 0, iclass 34, count 0 2006.201.14:33:18.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:18.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.14:33:18.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.14:33:18.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.14:33:18.60$vck44/vblo=4,679.99 2006.201.14:33:18.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.14:33:18.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.14:33:18.60#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:18.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:18.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:18.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:18.60#ibcon#enter wrdev, iclass 36, count 0 2006.201.14:33:18.60#ibcon#first serial, iclass 36, count 0 2006.201.14:33:18.60#ibcon#enter sib2, iclass 36, count 0 2006.201.14:33:18.60#ibcon#flushed, iclass 36, count 0 2006.201.14:33:18.60#ibcon#about to write, iclass 36, count 0 2006.201.14:33:18.60#ibcon#wrote, iclass 36, count 0 2006.201.14:33:18.60#ibcon#about to read 3, iclass 36, count 0 2006.201.14:33:18.62#ibcon#read 3, iclass 36, count 0 2006.201.14:33:18.62#ibcon#about to read 4, iclass 36, count 0 2006.201.14:33:18.62#ibcon#read 4, iclass 36, count 0 2006.201.14:33:18.62#ibcon#about to read 5, iclass 36, count 0 2006.201.14:33:18.62#ibcon#read 5, iclass 36, count 0 2006.201.14:33:18.62#ibcon#about to read 6, iclass 36, count 0 2006.201.14:33:18.62#ibcon#read 6, iclass 36, count 0 2006.201.14:33:18.62#ibcon#end of sib2, iclass 36, count 0 2006.201.14:33:18.62#ibcon#*mode == 0, iclass 36, count 0 2006.201.14:33:18.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.14:33:18.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:33:18.62#ibcon#*before write, iclass 36, count 0 2006.201.14:33:18.62#ibcon#enter sib2, iclass 36, count 0 2006.201.14:33:18.62#ibcon#flushed, iclass 36, count 0 2006.201.14:33:18.62#ibcon#about to write, iclass 36, count 0 2006.201.14:33:18.62#ibcon#wrote, iclass 36, count 0 2006.201.14:33:18.62#ibcon#about to read 3, iclass 36, count 0 2006.201.14:33:18.67#ibcon#read 3, iclass 36, count 0 2006.201.14:33:18.67#ibcon#about to read 4, iclass 36, count 0 2006.201.14:33:18.67#ibcon#read 4, iclass 36, count 0 2006.201.14:33:18.67#ibcon#about to read 5, iclass 36, count 0 2006.201.14:33:18.67#ibcon#read 5, iclass 36, count 0 2006.201.14:33:18.67#ibcon#about to read 6, iclass 36, count 0 2006.201.14:33:18.67#ibcon#read 6, iclass 36, count 0 2006.201.14:33:18.67#ibcon#end of sib2, iclass 36, count 0 2006.201.14:33:18.67#ibcon#*after write, iclass 36, count 0 2006.201.14:33:18.67#ibcon#*before return 0, iclass 36, count 0 2006.201.14:33:18.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:18.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.14:33:18.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.14:33:18.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.14:33:18.67$vck44/vb=4,5 2006.201.14:33:18.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.14:33:18.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.14:33:18.67#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:18.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:18.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:18.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:18.72#ibcon#enter wrdev, iclass 38, count 2 2006.201.14:33:18.72#ibcon#first serial, iclass 38, count 2 2006.201.14:33:18.72#ibcon#enter sib2, iclass 38, count 2 2006.201.14:33:18.72#ibcon#flushed, iclass 38, count 2 2006.201.14:33:18.72#ibcon#about to write, iclass 38, count 2 2006.201.14:33:18.72#ibcon#wrote, iclass 38, count 2 2006.201.14:33:18.72#ibcon#about to read 3, iclass 38, count 2 2006.201.14:33:18.74#ibcon#read 3, iclass 38, count 2 2006.201.14:33:18.74#ibcon#about to read 4, iclass 38, count 2 2006.201.14:33:18.74#ibcon#read 4, iclass 38, count 2 2006.201.14:33:18.74#ibcon#about to read 5, iclass 38, count 2 2006.201.14:33:18.74#ibcon#read 5, iclass 38, count 2 2006.201.14:33:18.74#ibcon#about to read 6, iclass 38, count 2 2006.201.14:33:18.74#ibcon#read 6, iclass 38, count 2 2006.201.14:33:18.74#ibcon#end of sib2, iclass 38, count 2 2006.201.14:33:18.74#ibcon#*mode == 0, iclass 38, count 2 2006.201.14:33:18.74#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.14:33:18.74#ibcon#[27=AT04-05\r\n] 2006.201.14:33:18.74#ibcon#*before write, iclass 38, count 2 2006.201.14:33:18.74#ibcon#enter sib2, iclass 38, count 2 2006.201.14:33:18.74#ibcon#flushed, iclass 38, count 2 2006.201.14:33:18.74#ibcon#about to write, iclass 38, count 2 2006.201.14:33:18.74#ibcon#wrote, iclass 38, count 2 2006.201.14:33:18.74#ibcon#about to read 3, iclass 38, count 2 2006.201.14:33:18.77#ibcon#read 3, iclass 38, count 2 2006.201.14:33:18.77#ibcon#about to read 4, iclass 38, count 2 2006.201.14:33:18.77#ibcon#read 4, iclass 38, count 2 2006.201.14:33:18.77#ibcon#about to read 5, iclass 38, count 2 2006.201.14:33:18.77#ibcon#read 5, iclass 38, count 2 2006.201.14:33:18.77#ibcon#about to read 6, iclass 38, count 2 2006.201.14:33:18.77#ibcon#read 6, iclass 38, count 2 2006.201.14:33:18.77#ibcon#end of sib2, iclass 38, count 2 2006.201.14:33:18.77#ibcon#*after write, iclass 38, count 2 2006.201.14:33:18.77#ibcon#*before return 0, iclass 38, count 2 2006.201.14:33:18.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:18.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.14:33:18.77#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.14:33:18.77#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:18.77#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:18.89#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:18.89#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:18.89#ibcon#enter wrdev, iclass 38, count 0 2006.201.14:33:18.89#ibcon#first serial, iclass 38, count 0 2006.201.14:33:18.89#ibcon#enter sib2, iclass 38, count 0 2006.201.14:33:18.89#ibcon#flushed, iclass 38, count 0 2006.201.14:33:18.89#ibcon#about to write, iclass 38, count 0 2006.201.14:33:18.89#ibcon#wrote, iclass 38, count 0 2006.201.14:33:18.89#ibcon#about to read 3, iclass 38, count 0 2006.201.14:33:18.91#ibcon#read 3, iclass 38, count 0 2006.201.14:33:18.91#ibcon#about to read 4, iclass 38, count 0 2006.201.14:33:18.91#ibcon#read 4, iclass 38, count 0 2006.201.14:33:18.91#ibcon#about to read 5, iclass 38, count 0 2006.201.14:33:18.91#ibcon#read 5, iclass 38, count 0 2006.201.14:33:18.91#ibcon#about to read 6, iclass 38, count 0 2006.201.14:33:18.91#ibcon#read 6, iclass 38, count 0 2006.201.14:33:18.91#ibcon#end of sib2, iclass 38, count 0 2006.201.14:33:18.91#ibcon#*mode == 0, iclass 38, count 0 2006.201.14:33:18.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.14:33:18.91#ibcon#[27=USB\r\n] 2006.201.14:33:18.91#ibcon#*before write, iclass 38, count 0 2006.201.14:33:18.91#ibcon#enter sib2, iclass 38, count 0 2006.201.14:33:18.91#ibcon#flushed, iclass 38, count 0 2006.201.14:33:18.91#ibcon#about to write, iclass 38, count 0 2006.201.14:33:18.91#ibcon#wrote, iclass 38, count 0 2006.201.14:33:18.91#ibcon#about to read 3, iclass 38, count 0 2006.201.14:33:18.94#ibcon#read 3, iclass 38, count 0 2006.201.14:33:18.94#ibcon#about to read 4, iclass 38, count 0 2006.201.14:33:18.94#ibcon#read 4, iclass 38, count 0 2006.201.14:33:18.94#ibcon#about to read 5, iclass 38, count 0 2006.201.14:33:18.94#ibcon#read 5, iclass 38, count 0 2006.201.14:33:18.94#ibcon#about to read 6, iclass 38, count 0 2006.201.14:33:18.94#ibcon#read 6, iclass 38, count 0 2006.201.14:33:18.94#ibcon#end of sib2, iclass 38, count 0 2006.201.14:33:18.94#ibcon#*after write, iclass 38, count 0 2006.201.14:33:18.94#ibcon#*before return 0, iclass 38, count 0 2006.201.14:33:18.94#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:18.94#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.14:33:18.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.14:33:18.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.14:33:18.94$vck44/vblo=5,709.99 2006.201.14:33:18.94#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.14:33:18.94#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.14:33:18.94#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:18.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:18.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:18.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:18.94#ibcon#enter wrdev, iclass 40, count 0 2006.201.14:33:18.94#ibcon#first serial, iclass 40, count 0 2006.201.14:33:18.94#ibcon#enter sib2, iclass 40, count 0 2006.201.14:33:18.94#ibcon#flushed, iclass 40, count 0 2006.201.14:33:18.94#ibcon#about to write, iclass 40, count 0 2006.201.14:33:18.94#ibcon#wrote, iclass 40, count 0 2006.201.14:33:18.94#ibcon#about to read 3, iclass 40, count 0 2006.201.14:33:18.96#ibcon#read 3, iclass 40, count 0 2006.201.14:33:18.96#ibcon#about to read 4, iclass 40, count 0 2006.201.14:33:18.96#ibcon#read 4, iclass 40, count 0 2006.201.14:33:18.96#ibcon#about to read 5, iclass 40, count 0 2006.201.14:33:18.96#ibcon#read 5, iclass 40, count 0 2006.201.14:33:18.96#ibcon#about to read 6, iclass 40, count 0 2006.201.14:33:18.96#ibcon#read 6, iclass 40, count 0 2006.201.14:33:18.96#ibcon#end of sib2, iclass 40, count 0 2006.201.14:33:18.96#ibcon#*mode == 0, iclass 40, count 0 2006.201.14:33:18.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.14:33:18.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:33:18.96#ibcon#*before write, iclass 40, count 0 2006.201.14:33:18.96#ibcon#enter sib2, iclass 40, count 0 2006.201.14:33:18.96#ibcon#flushed, iclass 40, count 0 2006.201.14:33:18.96#ibcon#about to write, iclass 40, count 0 2006.201.14:33:18.96#ibcon#wrote, iclass 40, count 0 2006.201.14:33:18.96#ibcon#about to read 3, iclass 40, count 0 2006.201.14:33:19.00#ibcon#read 3, iclass 40, count 0 2006.201.14:33:19.00#ibcon#about to read 4, iclass 40, count 0 2006.201.14:33:19.00#ibcon#read 4, iclass 40, count 0 2006.201.14:33:19.00#ibcon#about to read 5, iclass 40, count 0 2006.201.14:33:19.00#ibcon#read 5, iclass 40, count 0 2006.201.14:33:19.00#ibcon#about to read 6, iclass 40, count 0 2006.201.14:33:19.00#ibcon#read 6, iclass 40, count 0 2006.201.14:33:19.00#ibcon#end of sib2, iclass 40, count 0 2006.201.14:33:19.00#ibcon#*after write, iclass 40, count 0 2006.201.14:33:19.00#ibcon#*before return 0, iclass 40, count 0 2006.201.14:33:19.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:19.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.14:33:19.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.14:33:19.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.14:33:19.00$vck44/vb=5,4 2006.201.14:33:19.00#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.14:33:19.00#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.14:33:19.00#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:19.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:19.06#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:19.06#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:19.06#ibcon#enter wrdev, iclass 4, count 2 2006.201.14:33:19.06#ibcon#first serial, iclass 4, count 2 2006.201.14:33:19.06#ibcon#enter sib2, iclass 4, count 2 2006.201.14:33:19.06#ibcon#flushed, iclass 4, count 2 2006.201.14:33:19.06#ibcon#about to write, iclass 4, count 2 2006.201.14:33:19.06#ibcon#wrote, iclass 4, count 2 2006.201.14:33:19.06#ibcon#about to read 3, iclass 4, count 2 2006.201.14:33:19.08#ibcon#read 3, iclass 4, count 2 2006.201.14:33:19.08#ibcon#about to read 4, iclass 4, count 2 2006.201.14:33:19.08#ibcon#read 4, iclass 4, count 2 2006.201.14:33:19.08#ibcon#about to read 5, iclass 4, count 2 2006.201.14:33:19.08#ibcon#read 5, iclass 4, count 2 2006.201.14:33:19.08#ibcon#about to read 6, iclass 4, count 2 2006.201.14:33:19.08#ibcon#read 6, iclass 4, count 2 2006.201.14:33:19.08#ibcon#end of sib2, iclass 4, count 2 2006.201.14:33:19.08#ibcon#*mode == 0, iclass 4, count 2 2006.201.14:33:19.08#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.14:33:19.08#ibcon#[27=AT05-04\r\n] 2006.201.14:33:19.08#ibcon#*before write, iclass 4, count 2 2006.201.14:33:19.08#ibcon#enter sib2, iclass 4, count 2 2006.201.14:33:19.08#ibcon#flushed, iclass 4, count 2 2006.201.14:33:19.08#ibcon#about to write, iclass 4, count 2 2006.201.14:33:19.08#ibcon#wrote, iclass 4, count 2 2006.201.14:33:19.08#ibcon#about to read 3, iclass 4, count 2 2006.201.14:33:19.11#ibcon#read 3, iclass 4, count 2 2006.201.14:33:19.11#ibcon#about to read 4, iclass 4, count 2 2006.201.14:33:19.11#ibcon#read 4, iclass 4, count 2 2006.201.14:33:19.11#ibcon#about to read 5, iclass 4, count 2 2006.201.14:33:19.11#ibcon#read 5, iclass 4, count 2 2006.201.14:33:19.11#ibcon#about to read 6, iclass 4, count 2 2006.201.14:33:19.11#ibcon#read 6, iclass 4, count 2 2006.201.14:33:19.11#ibcon#end of sib2, iclass 4, count 2 2006.201.14:33:19.11#ibcon#*after write, iclass 4, count 2 2006.201.14:33:19.11#ibcon#*before return 0, iclass 4, count 2 2006.201.14:33:19.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:19.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.14:33:19.11#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.14:33:19.11#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:19.11#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:19.23#abcon#<5=/04 1.3 2.9 20.771001003.5\r\n> 2006.201.14:33:19.23#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:19.23#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:19.23#ibcon#enter wrdev, iclass 4, count 0 2006.201.14:33:19.23#ibcon#first serial, iclass 4, count 0 2006.201.14:33:19.23#ibcon#enter sib2, iclass 4, count 0 2006.201.14:33:19.23#ibcon#flushed, iclass 4, count 0 2006.201.14:33:19.23#ibcon#about to write, iclass 4, count 0 2006.201.14:33:19.23#ibcon#wrote, iclass 4, count 0 2006.201.14:33:19.23#ibcon#about to read 3, iclass 4, count 0 2006.201.14:33:19.25#ibcon#read 3, iclass 4, count 0 2006.201.14:33:19.25#ibcon#about to read 4, iclass 4, count 0 2006.201.14:33:19.25#ibcon#read 4, iclass 4, count 0 2006.201.14:33:19.25#ibcon#about to read 5, iclass 4, count 0 2006.201.14:33:19.25#ibcon#read 5, iclass 4, count 0 2006.201.14:33:19.25#ibcon#about to read 6, iclass 4, count 0 2006.201.14:33:19.25#ibcon#read 6, iclass 4, count 0 2006.201.14:33:19.25#ibcon#end of sib2, iclass 4, count 0 2006.201.14:33:19.25#ibcon#*mode == 0, iclass 4, count 0 2006.201.14:33:19.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.14:33:19.25#ibcon#[27=USB\r\n] 2006.201.14:33:19.25#ibcon#*before write, iclass 4, count 0 2006.201.14:33:19.25#ibcon#enter sib2, iclass 4, count 0 2006.201.14:33:19.25#ibcon#flushed, iclass 4, count 0 2006.201.14:33:19.25#ibcon#about to write, iclass 4, count 0 2006.201.14:33:19.25#ibcon#wrote, iclass 4, count 0 2006.201.14:33:19.25#ibcon#about to read 3, iclass 4, count 0 2006.201.14:33:19.25#abcon#{5=INTERFACE CLEAR} 2006.201.14:33:19.28#ibcon#read 3, iclass 4, count 0 2006.201.14:33:19.28#ibcon#about to read 4, iclass 4, count 0 2006.201.14:33:19.28#ibcon#read 4, iclass 4, count 0 2006.201.14:33:19.28#ibcon#about to read 5, iclass 4, count 0 2006.201.14:33:19.28#ibcon#read 5, iclass 4, count 0 2006.201.14:33:19.28#ibcon#about to read 6, iclass 4, count 0 2006.201.14:33:19.28#ibcon#read 6, iclass 4, count 0 2006.201.14:33:19.28#ibcon#end of sib2, iclass 4, count 0 2006.201.14:33:19.28#ibcon#*after write, iclass 4, count 0 2006.201.14:33:19.28#ibcon#*before return 0, iclass 4, count 0 2006.201.14:33:19.28#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:19.28#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.14:33:19.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.14:33:19.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.14:33:19.28$vck44/vblo=6,719.99 2006.201.14:33:19.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.14:33:19.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.14:33:19.28#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:19.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:33:19.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:33:19.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:33:19.28#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:33:19.28#ibcon#first serial, iclass 11, count 0 2006.201.14:33:19.28#ibcon#enter sib2, iclass 11, count 0 2006.201.14:33:19.28#ibcon#flushed, iclass 11, count 0 2006.201.14:33:19.28#ibcon#about to write, iclass 11, count 0 2006.201.14:33:19.28#ibcon#wrote, iclass 11, count 0 2006.201.14:33:19.28#ibcon#about to read 3, iclass 11, count 0 2006.201.14:33:19.30#ibcon#read 3, iclass 11, count 0 2006.201.14:33:19.30#ibcon#about to read 4, iclass 11, count 0 2006.201.14:33:19.30#ibcon#read 4, iclass 11, count 0 2006.201.14:33:19.30#ibcon#about to read 5, iclass 11, count 0 2006.201.14:33:19.30#ibcon#read 5, iclass 11, count 0 2006.201.14:33:19.30#ibcon#about to read 6, iclass 11, count 0 2006.201.14:33:19.30#ibcon#read 6, iclass 11, count 0 2006.201.14:33:19.30#ibcon#end of sib2, iclass 11, count 0 2006.201.14:33:19.30#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:33:19.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:33:19.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:33:19.30#ibcon#*before write, iclass 11, count 0 2006.201.14:33:19.30#ibcon#enter sib2, iclass 11, count 0 2006.201.14:33:19.30#ibcon#flushed, iclass 11, count 0 2006.201.14:33:19.30#ibcon#about to write, iclass 11, count 0 2006.201.14:33:19.30#ibcon#wrote, iclass 11, count 0 2006.201.14:33:19.30#ibcon#about to read 3, iclass 11, count 0 2006.201.14:33:19.31#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:33:19.35#ibcon#read 3, iclass 11, count 0 2006.201.14:33:19.35#ibcon#about to read 4, iclass 11, count 0 2006.201.14:33:19.35#ibcon#read 4, iclass 11, count 0 2006.201.14:33:19.35#ibcon#about to read 5, iclass 11, count 0 2006.201.14:33:19.35#ibcon#read 5, iclass 11, count 0 2006.201.14:33:19.35#ibcon#about to read 6, iclass 11, count 0 2006.201.14:33:19.35#ibcon#read 6, iclass 11, count 0 2006.201.14:33:19.35#ibcon#end of sib2, iclass 11, count 0 2006.201.14:33:19.35#ibcon#*after write, iclass 11, count 0 2006.201.14:33:19.35#ibcon#*before return 0, iclass 11, count 0 2006.201.14:33:19.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:33:19.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:33:19.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:33:19.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:33:19.35$vck44/vb=6,4 2006.201.14:33:19.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.14:33:19.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.14:33:19.35#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:19.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:19.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:19.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:19.40#ibcon#enter wrdev, iclass 14, count 2 2006.201.14:33:19.40#ibcon#first serial, iclass 14, count 2 2006.201.14:33:19.40#ibcon#enter sib2, iclass 14, count 2 2006.201.14:33:19.40#ibcon#flushed, iclass 14, count 2 2006.201.14:33:19.40#ibcon#about to write, iclass 14, count 2 2006.201.14:33:19.40#ibcon#wrote, iclass 14, count 2 2006.201.14:33:19.40#ibcon#about to read 3, iclass 14, count 2 2006.201.14:33:19.42#ibcon#read 3, iclass 14, count 2 2006.201.14:33:19.42#ibcon#about to read 4, iclass 14, count 2 2006.201.14:33:19.42#ibcon#read 4, iclass 14, count 2 2006.201.14:33:19.42#ibcon#about to read 5, iclass 14, count 2 2006.201.14:33:19.42#ibcon#read 5, iclass 14, count 2 2006.201.14:33:19.42#ibcon#about to read 6, iclass 14, count 2 2006.201.14:33:19.42#ibcon#read 6, iclass 14, count 2 2006.201.14:33:19.42#ibcon#end of sib2, iclass 14, count 2 2006.201.14:33:19.42#ibcon#*mode == 0, iclass 14, count 2 2006.201.14:33:19.42#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.14:33:19.42#ibcon#[27=AT06-04\r\n] 2006.201.14:33:19.42#ibcon#*before write, iclass 14, count 2 2006.201.14:33:19.42#ibcon#enter sib2, iclass 14, count 2 2006.201.14:33:19.42#ibcon#flushed, iclass 14, count 2 2006.201.14:33:19.42#ibcon#about to write, iclass 14, count 2 2006.201.14:33:19.42#ibcon#wrote, iclass 14, count 2 2006.201.14:33:19.42#ibcon#about to read 3, iclass 14, count 2 2006.201.14:33:19.45#ibcon#read 3, iclass 14, count 2 2006.201.14:33:19.45#ibcon#about to read 4, iclass 14, count 2 2006.201.14:33:19.45#ibcon#read 4, iclass 14, count 2 2006.201.14:33:19.45#ibcon#about to read 5, iclass 14, count 2 2006.201.14:33:19.45#ibcon#read 5, iclass 14, count 2 2006.201.14:33:19.45#ibcon#about to read 6, iclass 14, count 2 2006.201.14:33:19.45#ibcon#read 6, iclass 14, count 2 2006.201.14:33:19.45#ibcon#end of sib2, iclass 14, count 2 2006.201.14:33:19.45#ibcon#*after write, iclass 14, count 2 2006.201.14:33:19.45#ibcon#*before return 0, iclass 14, count 2 2006.201.14:33:19.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:19.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.14:33:19.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.14:33:19.45#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:19.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:19.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:19.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:19.57#ibcon#enter wrdev, iclass 14, count 0 2006.201.14:33:19.57#ibcon#first serial, iclass 14, count 0 2006.201.14:33:19.57#ibcon#enter sib2, iclass 14, count 0 2006.201.14:33:19.57#ibcon#flushed, iclass 14, count 0 2006.201.14:33:19.57#ibcon#about to write, iclass 14, count 0 2006.201.14:33:19.57#ibcon#wrote, iclass 14, count 0 2006.201.14:33:19.57#ibcon#about to read 3, iclass 14, count 0 2006.201.14:33:19.59#ibcon#read 3, iclass 14, count 0 2006.201.14:33:19.59#ibcon#about to read 4, iclass 14, count 0 2006.201.14:33:19.59#ibcon#read 4, iclass 14, count 0 2006.201.14:33:19.59#ibcon#about to read 5, iclass 14, count 0 2006.201.14:33:19.59#ibcon#read 5, iclass 14, count 0 2006.201.14:33:19.59#ibcon#about to read 6, iclass 14, count 0 2006.201.14:33:19.59#ibcon#read 6, iclass 14, count 0 2006.201.14:33:19.59#ibcon#end of sib2, iclass 14, count 0 2006.201.14:33:19.59#ibcon#*mode == 0, iclass 14, count 0 2006.201.14:33:19.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.14:33:19.59#ibcon#[27=USB\r\n] 2006.201.14:33:19.59#ibcon#*before write, iclass 14, count 0 2006.201.14:33:19.59#ibcon#enter sib2, iclass 14, count 0 2006.201.14:33:19.59#ibcon#flushed, iclass 14, count 0 2006.201.14:33:19.59#ibcon#about to write, iclass 14, count 0 2006.201.14:33:19.59#ibcon#wrote, iclass 14, count 0 2006.201.14:33:19.59#ibcon#about to read 3, iclass 14, count 0 2006.201.14:33:19.62#ibcon#read 3, iclass 14, count 0 2006.201.14:33:19.62#ibcon#about to read 4, iclass 14, count 0 2006.201.14:33:19.62#ibcon#read 4, iclass 14, count 0 2006.201.14:33:19.62#ibcon#about to read 5, iclass 14, count 0 2006.201.14:33:19.62#ibcon#read 5, iclass 14, count 0 2006.201.14:33:19.62#ibcon#about to read 6, iclass 14, count 0 2006.201.14:33:19.62#ibcon#read 6, iclass 14, count 0 2006.201.14:33:19.62#ibcon#end of sib2, iclass 14, count 0 2006.201.14:33:19.62#ibcon#*after write, iclass 14, count 0 2006.201.14:33:19.62#ibcon#*before return 0, iclass 14, count 0 2006.201.14:33:19.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:19.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.14:33:19.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.14:33:19.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.14:33:19.62$vck44/vblo=7,734.99 2006.201.14:33:19.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.14:33:19.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.14:33:19.62#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:19.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:19.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:19.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:19.62#ibcon#enter wrdev, iclass 16, count 0 2006.201.14:33:19.62#ibcon#first serial, iclass 16, count 0 2006.201.14:33:19.62#ibcon#enter sib2, iclass 16, count 0 2006.201.14:33:19.62#ibcon#flushed, iclass 16, count 0 2006.201.14:33:19.62#ibcon#about to write, iclass 16, count 0 2006.201.14:33:19.62#ibcon#wrote, iclass 16, count 0 2006.201.14:33:19.62#ibcon#about to read 3, iclass 16, count 0 2006.201.14:33:19.64#ibcon#read 3, iclass 16, count 0 2006.201.14:33:19.64#ibcon#about to read 4, iclass 16, count 0 2006.201.14:33:19.64#ibcon#read 4, iclass 16, count 0 2006.201.14:33:19.64#ibcon#about to read 5, iclass 16, count 0 2006.201.14:33:19.64#ibcon#read 5, iclass 16, count 0 2006.201.14:33:19.64#ibcon#about to read 6, iclass 16, count 0 2006.201.14:33:19.64#ibcon#read 6, iclass 16, count 0 2006.201.14:33:19.64#ibcon#end of sib2, iclass 16, count 0 2006.201.14:33:19.64#ibcon#*mode == 0, iclass 16, count 0 2006.201.14:33:19.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.14:33:19.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:33:19.64#ibcon#*before write, iclass 16, count 0 2006.201.14:33:19.64#ibcon#enter sib2, iclass 16, count 0 2006.201.14:33:19.64#ibcon#flushed, iclass 16, count 0 2006.201.14:33:19.64#ibcon#about to write, iclass 16, count 0 2006.201.14:33:19.64#ibcon#wrote, iclass 16, count 0 2006.201.14:33:19.64#ibcon#about to read 3, iclass 16, count 0 2006.201.14:33:19.68#ibcon#read 3, iclass 16, count 0 2006.201.14:33:19.68#ibcon#about to read 4, iclass 16, count 0 2006.201.14:33:19.68#ibcon#read 4, iclass 16, count 0 2006.201.14:33:19.68#ibcon#about to read 5, iclass 16, count 0 2006.201.14:33:19.68#ibcon#read 5, iclass 16, count 0 2006.201.14:33:19.68#ibcon#about to read 6, iclass 16, count 0 2006.201.14:33:19.68#ibcon#read 6, iclass 16, count 0 2006.201.14:33:19.68#ibcon#end of sib2, iclass 16, count 0 2006.201.14:33:19.68#ibcon#*after write, iclass 16, count 0 2006.201.14:33:19.68#ibcon#*before return 0, iclass 16, count 0 2006.201.14:33:19.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:19.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.14:33:19.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.14:33:19.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.14:33:19.68$vck44/vb=7,4 2006.201.14:33:19.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.14:33:19.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.14:33:19.68#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:19.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:19.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:19.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:19.74#ibcon#enter wrdev, iclass 18, count 2 2006.201.14:33:19.74#ibcon#first serial, iclass 18, count 2 2006.201.14:33:19.74#ibcon#enter sib2, iclass 18, count 2 2006.201.14:33:19.74#ibcon#flushed, iclass 18, count 2 2006.201.14:33:19.74#ibcon#about to write, iclass 18, count 2 2006.201.14:33:19.74#ibcon#wrote, iclass 18, count 2 2006.201.14:33:19.74#ibcon#about to read 3, iclass 18, count 2 2006.201.14:33:19.76#ibcon#read 3, iclass 18, count 2 2006.201.14:33:19.76#ibcon#about to read 4, iclass 18, count 2 2006.201.14:33:19.76#ibcon#read 4, iclass 18, count 2 2006.201.14:33:19.76#ibcon#about to read 5, iclass 18, count 2 2006.201.14:33:19.76#ibcon#read 5, iclass 18, count 2 2006.201.14:33:19.76#ibcon#about to read 6, iclass 18, count 2 2006.201.14:33:19.76#ibcon#read 6, iclass 18, count 2 2006.201.14:33:19.76#ibcon#end of sib2, iclass 18, count 2 2006.201.14:33:19.76#ibcon#*mode == 0, iclass 18, count 2 2006.201.14:33:19.76#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.14:33:19.76#ibcon#[27=AT07-04\r\n] 2006.201.14:33:19.76#ibcon#*before write, iclass 18, count 2 2006.201.14:33:19.76#ibcon#enter sib2, iclass 18, count 2 2006.201.14:33:19.76#ibcon#flushed, iclass 18, count 2 2006.201.14:33:19.76#ibcon#about to write, iclass 18, count 2 2006.201.14:33:19.76#ibcon#wrote, iclass 18, count 2 2006.201.14:33:19.76#ibcon#about to read 3, iclass 18, count 2 2006.201.14:33:19.79#ibcon#read 3, iclass 18, count 2 2006.201.14:33:19.79#ibcon#about to read 4, iclass 18, count 2 2006.201.14:33:19.79#ibcon#read 4, iclass 18, count 2 2006.201.14:33:19.79#ibcon#about to read 5, iclass 18, count 2 2006.201.14:33:19.79#ibcon#read 5, iclass 18, count 2 2006.201.14:33:19.79#ibcon#about to read 6, iclass 18, count 2 2006.201.14:33:19.79#ibcon#read 6, iclass 18, count 2 2006.201.14:33:19.79#ibcon#end of sib2, iclass 18, count 2 2006.201.14:33:19.79#ibcon#*after write, iclass 18, count 2 2006.201.14:33:19.79#ibcon#*before return 0, iclass 18, count 2 2006.201.14:33:19.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:19.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.14:33:19.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.14:33:19.79#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:19.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:19.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:19.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:19.91#ibcon#enter wrdev, iclass 18, count 0 2006.201.14:33:19.91#ibcon#first serial, iclass 18, count 0 2006.201.14:33:19.91#ibcon#enter sib2, iclass 18, count 0 2006.201.14:33:19.91#ibcon#flushed, iclass 18, count 0 2006.201.14:33:19.91#ibcon#about to write, iclass 18, count 0 2006.201.14:33:19.91#ibcon#wrote, iclass 18, count 0 2006.201.14:33:19.91#ibcon#about to read 3, iclass 18, count 0 2006.201.14:33:19.93#ibcon#read 3, iclass 18, count 0 2006.201.14:33:19.93#ibcon#about to read 4, iclass 18, count 0 2006.201.14:33:19.93#ibcon#read 4, iclass 18, count 0 2006.201.14:33:19.93#ibcon#about to read 5, iclass 18, count 0 2006.201.14:33:19.93#ibcon#read 5, iclass 18, count 0 2006.201.14:33:19.93#ibcon#about to read 6, iclass 18, count 0 2006.201.14:33:19.93#ibcon#read 6, iclass 18, count 0 2006.201.14:33:19.93#ibcon#end of sib2, iclass 18, count 0 2006.201.14:33:19.93#ibcon#*mode == 0, iclass 18, count 0 2006.201.14:33:19.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.14:33:19.93#ibcon#[27=USB\r\n] 2006.201.14:33:19.93#ibcon#*before write, iclass 18, count 0 2006.201.14:33:19.93#ibcon#enter sib2, iclass 18, count 0 2006.201.14:33:19.93#ibcon#flushed, iclass 18, count 0 2006.201.14:33:19.93#ibcon#about to write, iclass 18, count 0 2006.201.14:33:19.93#ibcon#wrote, iclass 18, count 0 2006.201.14:33:19.93#ibcon#about to read 3, iclass 18, count 0 2006.201.14:33:19.96#ibcon#read 3, iclass 18, count 0 2006.201.14:33:19.96#ibcon#about to read 4, iclass 18, count 0 2006.201.14:33:19.96#ibcon#read 4, iclass 18, count 0 2006.201.14:33:19.96#ibcon#about to read 5, iclass 18, count 0 2006.201.14:33:19.96#ibcon#read 5, iclass 18, count 0 2006.201.14:33:19.96#ibcon#about to read 6, iclass 18, count 0 2006.201.14:33:19.96#ibcon#read 6, iclass 18, count 0 2006.201.14:33:19.96#ibcon#end of sib2, iclass 18, count 0 2006.201.14:33:19.96#ibcon#*after write, iclass 18, count 0 2006.201.14:33:19.96#ibcon#*before return 0, iclass 18, count 0 2006.201.14:33:19.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:19.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.14:33:19.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.14:33:19.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.14:33:19.96$vck44/vblo=8,744.99 2006.201.14:33:19.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.14:33:19.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.14:33:19.96#ibcon#ireg 17 cls_cnt 0 2006.201.14:33:19.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:19.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:19.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:19.96#ibcon#enter wrdev, iclass 20, count 0 2006.201.14:33:19.96#ibcon#first serial, iclass 20, count 0 2006.201.14:33:19.96#ibcon#enter sib2, iclass 20, count 0 2006.201.14:33:19.96#ibcon#flushed, iclass 20, count 0 2006.201.14:33:19.96#ibcon#about to write, iclass 20, count 0 2006.201.14:33:19.96#ibcon#wrote, iclass 20, count 0 2006.201.14:33:19.96#ibcon#about to read 3, iclass 20, count 0 2006.201.14:33:19.98#ibcon#read 3, iclass 20, count 0 2006.201.14:33:19.98#ibcon#about to read 4, iclass 20, count 0 2006.201.14:33:19.98#ibcon#read 4, iclass 20, count 0 2006.201.14:33:19.98#ibcon#about to read 5, iclass 20, count 0 2006.201.14:33:19.98#ibcon#read 5, iclass 20, count 0 2006.201.14:33:19.98#ibcon#about to read 6, iclass 20, count 0 2006.201.14:33:19.98#ibcon#read 6, iclass 20, count 0 2006.201.14:33:19.98#ibcon#end of sib2, iclass 20, count 0 2006.201.14:33:19.98#ibcon#*mode == 0, iclass 20, count 0 2006.201.14:33:19.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.14:33:19.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:33:19.98#ibcon#*before write, iclass 20, count 0 2006.201.14:33:19.98#ibcon#enter sib2, iclass 20, count 0 2006.201.14:33:19.98#ibcon#flushed, iclass 20, count 0 2006.201.14:33:19.98#ibcon#about to write, iclass 20, count 0 2006.201.14:33:19.98#ibcon#wrote, iclass 20, count 0 2006.201.14:33:19.98#ibcon#about to read 3, iclass 20, count 0 2006.201.14:33:20.02#ibcon#read 3, iclass 20, count 0 2006.201.14:33:20.02#ibcon#about to read 4, iclass 20, count 0 2006.201.14:33:20.02#ibcon#read 4, iclass 20, count 0 2006.201.14:33:20.02#ibcon#about to read 5, iclass 20, count 0 2006.201.14:33:20.02#ibcon#read 5, iclass 20, count 0 2006.201.14:33:20.02#ibcon#about to read 6, iclass 20, count 0 2006.201.14:33:20.02#ibcon#read 6, iclass 20, count 0 2006.201.14:33:20.02#ibcon#end of sib2, iclass 20, count 0 2006.201.14:33:20.02#ibcon#*after write, iclass 20, count 0 2006.201.14:33:20.02#ibcon#*before return 0, iclass 20, count 0 2006.201.14:33:20.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:20.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.14:33:20.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.14:33:20.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.14:33:20.02$vck44/vb=8,4 2006.201.14:33:20.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.14:33:20.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.14:33:20.02#ibcon#ireg 11 cls_cnt 2 2006.201.14:33:20.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:20.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:20.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:20.08#ibcon#enter wrdev, iclass 22, count 2 2006.201.14:33:20.08#ibcon#first serial, iclass 22, count 2 2006.201.14:33:20.08#ibcon#enter sib2, iclass 22, count 2 2006.201.14:33:20.08#ibcon#flushed, iclass 22, count 2 2006.201.14:33:20.08#ibcon#about to write, iclass 22, count 2 2006.201.14:33:20.08#ibcon#wrote, iclass 22, count 2 2006.201.14:33:20.08#ibcon#about to read 3, iclass 22, count 2 2006.201.14:33:20.10#ibcon#read 3, iclass 22, count 2 2006.201.14:33:20.10#ibcon#about to read 4, iclass 22, count 2 2006.201.14:33:20.10#ibcon#read 4, iclass 22, count 2 2006.201.14:33:20.10#ibcon#about to read 5, iclass 22, count 2 2006.201.14:33:20.10#ibcon#read 5, iclass 22, count 2 2006.201.14:33:20.10#ibcon#about to read 6, iclass 22, count 2 2006.201.14:33:20.10#ibcon#read 6, iclass 22, count 2 2006.201.14:33:20.10#ibcon#end of sib2, iclass 22, count 2 2006.201.14:33:20.10#ibcon#*mode == 0, iclass 22, count 2 2006.201.14:33:20.10#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.14:33:20.10#ibcon#[27=AT08-04\r\n] 2006.201.14:33:20.10#ibcon#*before write, iclass 22, count 2 2006.201.14:33:20.10#ibcon#enter sib2, iclass 22, count 2 2006.201.14:33:20.10#ibcon#flushed, iclass 22, count 2 2006.201.14:33:20.10#ibcon#about to write, iclass 22, count 2 2006.201.14:33:20.10#ibcon#wrote, iclass 22, count 2 2006.201.14:33:20.10#ibcon#about to read 3, iclass 22, count 2 2006.201.14:33:20.13#ibcon#read 3, iclass 22, count 2 2006.201.14:33:20.13#ibcon#about to read 4, iclass 22, count 2 2006.201.14:33:20.13#ibcon#read 4, iclass 22, count 2 2006.201.14:33:20.13#ibcon#about to read 5, iclass 22, count 2 2006.201.14:33:20.13#ibcon#read 5, iclass 22, count 2 2006.201.14:33:20.13#ibcon#about to read 6, iclass 22, count 2 2006.201.14:33:20.13#ibcon#read 6, iclass 22, count 2 2006.201.14:33:20.13#ibcon#end of sib2, iclass 22, count 2 2006.201.14:33:20.13#ibcon#*after write, iclass 22, count 2 2006.201.14:33:20.13#ibcon#*before return 0, iclass 22, count 2 2006.201.14:33:20.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:20.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.14:33:20.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.14:33:20.13#ibcon#ireg 7 cls_cnt 0 2006.201.14:33:20.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:20.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:20.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:20.25#ibcon#enter wrdev, iclass 22, count 0 2006.201.14:33:20.25#ibcon#first serial, iclass 22, count 0 2006.201.14:33:20.25#ibcon#enter sib2, iclass 22, count 0 2006.201.14:33:20.25#ibcon#flushed, iclass 22, count 0 2006.201.14:33:20.25#ibcon#about to write, iclass 22, count 0 2006.201.14:33:20.25#ibcon#wrote, iclass 22, count 0 2006.201.14:33:20.25#ibcon#about to read 3, iclass 22, count 0 2006.201.14:33:20.27#ibcon#read 3, iclass 22, count 0 2006.201.14:33:20.27#ibcon#about to read 4, iclass 22, count 0 2006.201.14:33:20.27#ibcon#read 4, iclass 22, count 0 2006.201.14:33:20.27#ibcon#about to read 5, iclass 22, count 0 2006.201.14:33:20.27#ibcon#read 5, iclass 22, count 0 2006.201.14:33:20.27#ibcon#about to read 6, iclass 22, count 0 2006.201.14:33:20.27#ibcon#read 6, iclass 22, count 0 2006.201.14:33:20.27#ibcon#end of sib2, iclass 22, count 0 2006.201.14:33:20.27#ibcon#*mode == 0, iclass 22, count 0 2006.201.14:33:20.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.14:33:20.27#ibcon#[27=USB\r\n] 2006.201.14:33:20.27#ibcon#*before write, iclass 22, count 0 2006.201.14:33:20.27#ibcon#enter sib2, iclass 22, count 0 2006.201.14:33:20.27#ibcon#flushed, iclass 22, count 0 2006.201.14:33:20.27#ibcon#about to write, iclass 22, count 0 2006.201.14:33:20.27#ibcon#wrote, iclass 22, count 0 2006.201.14:33:20.27#ibcon#about to read 3, iclass 22, count 0 2006.201.14:33:20.30#ibcon#read 3, iclass 22, count 0 2006.201.14:33:20.30#ibcon#about to read 4, iclass 22, count 0 2006.201.14:33:20.30#ibcon#read 4, iclass 22, count 0 2006.201.14:33:20.30#ibcon#about to read 5, iclass 22, count 0 2006.201.14:33:20.30#ibcon#read 5, iclass 22, count 0 2006.201.14:33:20.30#ibcon#about to read 6, iclass 22, count 0 2006.201.14:33:20.30#ibcon#read 6, iclass 22, count 0 2006.201.14:33:20.30#ibcon#end of sib2, iclass 22, count 0 2006.201.14:33:20.30#ibcon#*after write, iclass 22, count 0 2006.201.14:33:20.30#ibcon#*before return 0, iclass 22, count 0 2006.201.14:33:20.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:20.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.14:33:20.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.14:33:20.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.14:33:20.30$vck44/vabw=wide 2006.201.14:33:20.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.14:33:20.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.14:33:20.30#ibcon#ireg 8 cls_cnt 0 2006.201.14:33:20.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:20.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:20.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:20.30#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:33:20.30#ibcon#first serial, iclass 24, count 0 2006.201.14:33:20.30#ibcon#enter sib2, iclass 24, count 0 2006.201.14:33:20.30#ibcon#flushed, iclass 24, count 0 2006.201.14:33:20.30#ibcon#about to write, iclass 24, count 0 2006.201.14:33:20.30#ibcon#wrote, iclass 24, count 0 2006.201.14:33:20.30#ibcon#about to read 3, iclass 24, count 0 2006.201.14:33:20.32#ibcon#read 3, iclass 24, count 0 2006.201.14:33:20.32#ibcon#about to read 4, iclass 24, count 0 2006.201.14:33:20.32#ibcon#read 4, iclass 24, count 0 2006.201.14:33:20.32#ibcon#about to read 5, iclass 24, count 0 2006.201.14:33:20.32#ibcon#read 5, iclass 24, count 0 2006.201.14:33:20.32#ibcon#about to read 6, iclass 24, count 0 2006.201.14:33:20.32#ibcon#read 6, iclass 24, count 0 2006.201.14:33:20.32#ibcon#end of sib2, iclass 24, count 0 2006.201.14:33:20.32#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:33:20.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:33:20.32#ibcon#[25=BW32\r\n] 2006.201.14:33:20.32#ibcon#*before write, iclass 24, count 0 2006.201.14:33:20.32#ibcon#enter sib2, iclass 24, count 0 2006.201.14:33:20.32#ibcon#flushed, iclass 24, count 0 2006.201.14:33:20.32#ibcon#about to write, iclass 24, count 0 2006.201.14:33:20.32#ibcon#wrote, iclass 24, count 0 2006.201.14:33:20.32#ibcon#about to read 3, iclass 24, count 0 2006.201.14:33:20.36#ibcon#read 3, iclass 24, count 0 2006.201.14:33:20.36#ibcon#about to read 4, iclass 24, count 0 2006.201.14:33:20.36#ibcon#read 4, iclass 24, count 0 2006.201.14:33:20.36#ibcon#about to read 5, iclass 24, count 0 2006.201.14:33:20.36#ibcon#read 5, iclass 24, count 0 2006.201.14:33:20.36#ibcon#about to read 6, iclass 24, count 0 2006.201.14:33:20.36#ibcon#read 6, iclass 24, count 0 2006.201.14:33:20.36#ibcon#end of sib2, iclass 24, count 0 2006.201.14:33:20.36#ibcon#*after write, iclass 24, count 0 2006.201.14:33:20.36#ibcon#*before return 0, iclass 24, count 0 2006.201.14:33:20.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:20.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.14:33:20.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:33:20.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:33:20.36$vck44/vbbw=wide 2006.201.14:33:20.36#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.14:33:20.36#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.14:33:20.36#ibcon#ireg 8 cls_cnt 0 2006.201.14:33:20.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:33:20.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:33:20.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:33:20.42#ibcon#enter wrdev, iclass 26, count 0 2006.201.14:33:20.42#ibcon#first serial, iclass 26, count 0 2006.201.14:33:20.42#ibcon#enter sib2, iclass 26, count 0 2006.201.14:33:20.42#ibcon#flushed, iclass 26, count 0 2006.201.14:33:20.42#ibcon#about to write, iclass 26, count 0 2006.201.14:33:20.42#ibcon#wrote, iclass 26, count 0 2006.201.14:33:20.42#ibcon#about to read 3, iclass 26, count 0 2006.201.14:33:20.44#ibcon#read 3, iclass 26, count 0 2006.201.14:33:20.44#ibcon#about to read 4, iclass 26, count 0 2006.201.14:33:20.44#ibcon#read 4, iclass 26, count 0 2006.201.14:33:20.44#ibcon#about to read 5, iclass 26, count 0 2006.201.14:33:20.44#ibcon#read 5, iclass 26, count 0 2006.201.14:33:20.44#ibcon#about to read 6, iclass 26, count 0 2006.201.14:33:20.44#ibcon#read 6, iclass 26, count 0 2006.201.14:33:20.44#ibcon#end of sib2, iclass 26, count 0 2006.201.14:33:20.44#ibcon#*mode == 0, iclass 26, count 0 2006.201.14:33:20.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.14:33:20.44#ibcon#[27=BW32\r\n] 2006.201.14:33:20.44#ibcon#*before write, iclass 26, count 0 2006.201.14:33:20.44#ibcon#enter sib2, iclass 26, count 0 2006.201.14:33:20.44#ibcon#flushed, iclass 26, count 0 2006.201.14:33:20.44#ibcon#about to write, iclass 26, count 0 2006.201.14:33:20.44#ibcon#wrote, iclass 26, count 0 2006.201.14:33:20.44#ibcon#about to read 3, iclass 26, count 0 2006.201.14:33:20.47#ibcon#read 3, iclass 26, count 0 2006.201.14:33:20.47#ibcon#about to read 4, iclass 26, count 0 2006.201.14:33:20.47#ibcon#read 4, iclass 26, count 0 2006.201.14:33:20.47#ibcon#about to read 5, iclass 26, count 0 2006.201.14:33:20.47#ibcon#read 5, iclass 26, count 0 2006.201.14:33:20.47#ibcon#about to read 6, iclass 26, count 0 2006.201.14:33:20.47#ibcon#read 6, iclass 26, count 0 2006.201.14:33:20.47#ibcon#end of sib2, iclass 26, count 0 2006.201.14:33:20.47#ibcon#*after write, iclass 26, count 0 2006.201.14:33:20.47#ibcon#*before return 0, iclass 26, count 0 2006.201.14:33:20.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:33:20.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.14:33:20.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.14:33:20.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.14:33:20.47$setupk4/ifdk4 2006.201.14:33:20.47$ifdk4/lo= 2006.201.14:33:20.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:33:20.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:33:20.47$ifdk4/patch= 2006.201.14:33:20.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:33:20.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:33:20.47$setupk4/!*+20s 2006.201.14:33:29.40#abcon#<5=/04 1.3 2.9 20.771001003.5\r\n> 2006.201.14:33:29.42#abcon#{5=INTERFACE CLEAR} 2006.201.14:33:29.48#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:33:34.91$setupk4/"tpicd 2006.201.14:33:34.91$setupk4/echo=off 2006.201.14:33:34.91$setupk4/xlog=off 2006.201.14:33:34.91:!2006.201.14:36:47 2006.201.14:33:44.14#trakl#Source acquired 2006.201.14:33:46.14#flagr#flagr/antenna,acquired 2006.201.14:36:47.00:preob 2006.201.14:36:47.14/onsource/TRACKING 2006.201.14:36:47.14:!2006.201.14:36:57 2006.201.14:36:57.00:"tape 2006.201.14:36:57.00:"st=record 2006.201.14:36:57.00:data_valid=on 2006.201.14:36:57.00:midob 2006.201.14:36:58.14/onsource/TRACKING 2006.201.14:36:58.14/wx/20.77,1003.5,100 2006.201.14:36:58.24/cable/+6.4757E-03 2006.201.14:36:59.33/va/01,08,usb,yes,28,30 2006.201.14:36:59.33/va/02,07,usb,yes,30,31 2006.201.14:36:59.33/va/03,08,usb,yes,27,28 2006.201.14:36:59.33/va/04,07,usb,yes,31,32 2006.201.14:36:59.33/va/05,04,usb,yes,27,28 2006.201.14:36:59.33/va/06,05,usb,yes,27,27 2006.201.14:36:59.33/va/07,05,usb,yes,26,28 2006.201.14:36:59.33/va/08,04,usb,yes,26,32 2006.201.14:36:59.56/valo/01,524.99,yes,locked 2006.201.14:36:59.56/valo/02,534.99,yes,locked 2006.201.14:36:59.56/valo/03,564.99,yes,locked 2006.201.14:36:59.56/valo/04,624.99,yes,locked 2006.201.14:36:59.56/valo/05,734.99,yes,locked 2006.201.14:36:59.56/valo/06,814.99,yes,locked 2006.201.14:36:59.56/valo/07,864.99,yes,locked 2006.201.14:36:59.56/valo/08,884.99,yes,locked 2006.201.14:37:00.65/vb/01,04,usb,yes,28,26 2006.201.14:37:00.65/vb/02,05,usb,yes,26,26 2006.201.14:37:00.65/vb/03,04,usb,yes,27,30 2006.201.14:37:00.65/vb/04,05,usb,yes,27,26 2006.201.14:37:00.65/vb/05,04,usb,yes,24,26 2006.201.14:37:00.65/vb/06,04,usb,yes,28,25 2006.201.14:37:00.65/vb/07,04,usb,yes,28,28 2006.201.14:37:00.65/vb/08,04,usb,yes,26,29 2006.201.14:37:00.89/vblo/01,629.99,yes,locked 2006.201.14:37:00.89/vblo/02,634.99,yes,locked 2006.201.14:37:00.89/vblo/03,649.99,yes,locked 2006.201.14:37:00.89/vblo/04,679.99,yes,locked 2006.201.14:37:00.89/vblo/05,709.99,yes,locked 2006.201.14:37:00.89/vblo/06,719.99,yes,locked 2006.201.14:37:00.89/vblo/07,734.99,yes,locked 2006.201.14:37:00.89/vblo/08,744.99,yes,locked 2006.201.14:37:01.04/vabw/8 2006.201.14:37:01.19/vbbw/8 2006.201.14:37:01.28/xfe/off,on,14.5 2006.201.14:37:01.67/ifatt/23,28,28,28 2006.201.14:37:02.06/fmout-gps/S +4.58E-07 2006.201.14:37:02.11:!2006.201.14:38:17 2006.201.14:38:17.00:data_valid=off 2006.201.14:38:17.00:"et 2006.201.14:38:17.00:!+3s 2006.201.14:38:20.02:"tape 2006.201.14:38:20.02:postob 2006.201.14:38:20.24/cable/+6.4753E-03 2006.201.14:38:20.24/wx/20.77,1003.4,100 2006.201.14:38:20.31/fmout-gps/S +4.57E-07 2006.201.14:38:20.31:scan_name=201-1442,jd0607,70 2006.201.14:38:20.31:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.201.14:38:21.13#flagr#flagr/antenna,new-source 2006.201.14:38:21.13:checkk5 2006.201.14:38:21.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:38:21.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:38:22.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:38:22.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:38:22.99/chk_obsdata//k5ts1/T2011436??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.14:38:23.36/chk_obsdata//k5ts2/T2011436??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.14:38:23.73/chk_obsdata//k5ts3/T2011436??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.14:38:24.10/chk_obsdata//k5ts4/T2011436??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.14:38:24.81/k5log//k5ts1_log_newline 2006.201.14:38:25.51/k5log//k5ts2_log_newline 2006.201.14:38:26.21/k5log//k5ts3_log_newline 2006.201.14:38:26.90/k5log//k5ts4_log_newline 2006.201.14:38:26.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:38:26.92:setupk4=1 2006.201.14:38:26.92$setupk4/echo=on 2006.201.14:38:26.92$setupk4/pcalon 2006.201.14:38:26.92$pcalon/"no phase cal control is implemented here 2006.201.14:38:26.92$setupk4/"tpicd=stop 2006.201.14:38:26.92$setupk4/"rec=synch_on 2006.201.14:38:26.92$setupk4/"rec_mode=128 2006.201.14:38:26.92$setupk4/!* 2006.201.14:38:26.92$setupk4/recpk4 2006.201.14:38:26.92$recpk4/recpatch= 2006.201.14:38:26.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:38:26.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:38:26.93$setupk4/vck44 2006.201.14:38:26.93$vck44/valo=1,524.99 2006.201.14:38:26.93#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.14:38:26.93#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.14:38:26.93#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:26.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:26.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:26.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:26.93#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:38:26.93#ibcon#first serial, iclass 5, count 0 2006.201.14:38:26.93#ibcon#enter sib2, iclass 5, count 0 2006.201.14:38:26.93#ibcon#flushed, iclass 5, count 0 2006.201.14:38:26.93#ibcon#about to write, iclass 5, count 0 2006.201.14:38:26.93#ibcon#wrote, iclass 5, count 0 2006.201.14:38:26.93#ibcon#about to read 3, iclass 5, count 0 2006.201.14:38:26.96#ibcon#read 3, iclass 5, count 0 2006.201.14:38:26.96#ibcon#about to read 4, iclass 5, count 0 2006.201.14:38:26.96#ibcon#read 4, iclass 5, count 0 2006.201.14:38:26.96#ibcon#about to read 5, iclass 5, count 0 2006.201.14:38:26.96#ibcon#read 5, iclass 5, count 0 2006.201.14:38:26.96#ibcon#about to read 6, iclass 5, count 0 2006.201.14:38:26.96#ibcon#read 6, iclass 5, count 0 2006.201.14:38:26.96#ibcon#end of sib2, iclass 5, count 0 2006.201.14:38:26.96#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:38:26.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:38:26.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:38:26.96#ibcon#*before write, iclass 5, count 0 2006.201.14:38:26.96#ibcon#enter sib2, iclass 5, count 0 2006.201.14:38:26.96#ibcon#flushed, iclass 5, count 0 2006.201.14:38:26.96#ibcon#about to write, iclass 5, count 0 2006.201.14:38:26.96#ibcon#wrote, iclass 5, count 0 2006.201.14:38:26.96#ibcon#about to read 3, iclass 5, count 0 2006.201.14:38:27.01#ibcon#read 3, iclass 5, count 0 2006.201.14:38:27.01#ibcon#about to read 4, iclass 5, count 0 2006.201.14:38:27.01#ibcon#read 4, iclass 5, count 0 2006.201.14:38:27.01#ibcon#about to read 5, iclass 5, count 0 2006.201.14:38:27.01#ibcon#read 5, iclass 5, count 0 2006.201.14:38:27.01#ibcon#about to read 6, iclass 5, count 0 2006.201.14:38:27.01#ibcon#read 6, iclass 5, count 0 2006.201.14:38:27.01#ibcon#end of sib2, iclass 5, count 0 2006.201.14:38:27.01#ibcon#*after write, iclass 5, count 0 2006.201.14:38:27.01#ibcon#*before return 0, iclass 5, count 0 2006.201.14:38:27.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:27.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:27.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:38:27.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:38:27.01$vck44/va=1,8 2006.201.14:38:27.01#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.14:38:27.01#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.14:38:27.01#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:27.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:27.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:27.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:27.01#ibcon#enter wrdev, iclass 7, count 2 2006.201.14:38:27.01#ibcon#first serial, iclass 7, count 2 2006.201.14:38:27.01#ibcon#enter sib2, iclass 7, count 2 2006.201.14:38:27.01#ibcon#flushed, iclass 7, count 2 2006.201.14:38:27.01#ibcon#about to write, iclass 7, count 2 2006.201.14:38:27.01#ibcon#wrote, iclass 7, count 2 2006.201.14:38:27.01#ibcon#about to read 3, iclass 7, count 2 2006.201.14:38:27.03#ibcon#read 3, iclass 7, count 2 2006.201.14:38:27.03#ibcon#about to read 4, iclass 7, count 2 2006.201.14:38:27.03#ibcon#read 4, iclass 7, count 2 2006.201.14:38:27.03#ibcon#about to read 5, iclass 7, count 2 2006.201.14:38:27.03#ibcon#read 5, iclass 7, count 2 2006.201.14:38:27.03#ibcon#about to read 6, iclass 7, count 2 2006.201.14:38:27.03#ibcon#read 6, iclass 7, count 2 2006.201.14:38:27.03#ibcon#end of sib2, iclass 7, count 2 2006.201.14:38:27.03#ibcon#*mode == 0, iclass 7, count 2 2006.201.14:38:27.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.14:38:27.03#ibcon#[25=AT01-08\r\n] 2006.201.14:38:27.03#ibcon#*before write, iclass 7, count 2 2006.201.14:38:27.03#ibcon#enter sib2, iclass 7, count 2 2006.201.14:38:27.03#ibcon#flushed, iclass 7, count 2 2006.201.14:38:27.03#ibcon#about to write, iclass 7, count 2 2006.201.14:38:27.03#ibcon#wrote, iclass 7, count 2 2006.201.14:38:27.03#ibcon#about to read 3, iclass 7, count 2 2006.201.14:38:27.06#ibcon#read 3, iclass 7, count 2 2006.201.14:38:27.06#ibcon#about to read 4, iclass 7, count 2 2006.201.14:38:27.06#ibcon#read 4, iclass 7, count 2 2006.201.14:38:27.06#ibcon#about to read 5, iclass 7, count 2 2006.201.14:38:27.06#ibcon#read 5, iclass 7, count 2 2006.201.14:38:27.06#ibcon#about to read 6, iclass 7, count 2 2006.201.14:38:27.06#ibcon#read 6, iclass 7, count 2 2006.201.14:38:27.06#ibcon#end of sib2, iclass 7, count 2 2006.201.14:38:27.06#ibcon#*after write, iclass 7, count 2 2006.201.14:38:27.06#ibcon#*before return 0, iclass 7, count 2 2006.201.14:38:27.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:27.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:27.06#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.14:38:27.06#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:27.06#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:27.18#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:27.18#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:27.18#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:38:27.18#ibcon#first serial, iclass 7, count 0 2006.201.14:38:27.18#ibcon#enter sib2, iclass 7, count 0 2006.201.14:38:27.18#ibcon#flushed, iclass 7, count 0 2006.201.14:38:27.18#ibcon#about to write, iclass 7, count 0 2006.201.14:38:27.18#ibcon#wrote, iclass 7, count 0 2006.201.14:38:27.18#ibcon#about to read 3, iclass 7, count 0 2006.201.14:38:27.20#ibcon#read 3, iclass 7, count 0 2006.201.14:38:27.20#ibcon#about to read 4, iclass 7, count 0 2006.201.14:38:27.20#ibcon#read 4, iclass 7, count 0 2006.201.14:38:27.20#ibcon#about to read 5, iclass 7, count 0 2006.201.14:38:27.20#ibcon#read 5, iclass 7, count 0 2006.201.14:38:27.20#ibcon#about to read 6, iclass 7, count 0 2006.201.14:38:27.20#ibcon#read 6, iclass 7, count 0 2006.201.14:38:27.20#ibcon#end of sib2, iclass 7, count 0 2006.201.14:38:27.20#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:38:27.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:38:27.20#ibcon#[25=USB\r\n] 2006.201.14:38:27.20#ibcon#*before write, iclass 7, count 0 2006.201.14:38:27.20#ibcon#enter sib2, iclass 7, count 0 2006.201.14:38:27.20#ibcon#flushed, iclass 7, count 0 2006.201.14:38:27.20#ibcon#about to write, iclass 7, count 0 2006.201.14:38:27.20#ibcon#wrote, iclass 7, count 0 2006.201.14:38:27.20#ibcon#about to read 3, iclass 7, count 0 2006.201.14:38:27.23#ibcon#read 3, iclass 7, count 0 2006.201.14:38:27.23#ibcon#about to read 4, iclass 7, count 0 2006.201.14:38:27.23#ibcon#read 4, iclass 7, count 0 2006.201.14:38:27.23#ibcon#about to read 5, iclass 7, count 0 2006.201.14:38:27.23#ibcon#read 5, iclass 7, count 0 2006.201.14:38:27.23#ibcon#about to read 6, iclass 7, count 0 2006.201.14:38:27.23#ibcon#read 6, iclass 7, count 0 2006.201.14:38:27.23#ibcon#end of sib2, iclass 7, count 0 2006.201.14:38:27.23#ibcon#*after write, iclass 7, count 0 2006.201.14:38:27.23#ibcon#*before return 0, iclass 7, count 0 2006.201.14:38:27.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:27.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:27.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:38:27.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:38:27.23$vck44/valo=2,534.99 2006.201.14:38:27.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.14:38:27.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.14:38:27.23#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:27.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:27.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:27.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:27.23#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:38:27.23#ibcon#first serial, iclass 11, count 0 2006.201.14:38:27.23#ibcon#enter sib2, iclass 11, count 0 2006.201.14:38:27.23#ibcon#flushed, iclass 11, count 0 2006.201.14:38:27.23#ibcon#about to write, iclass 11, count 0 2006.201.14:38:27.23#ibcon#wrote, iclass 11, count 0 2006.201.14:38:27.23#ibcon#about to read 3, iclass 11, count 0 2006.201.14:38:27.25#ibcon#read 3, iclass 11, count 0 2006.201.14:38:27.25#ibcon#about to read 4, iclass 11, count 0 2006.201.14:38:27.25#ibcon#read 4, iclass 11, count 0 2006.201.14:38:27.25#ibcon#about to read 5, iclass 11, count 0 2006.201.14:38:27.25#ibcon#read 5, iclass 11, count 0 2006.201.14:38:27.25#ibcon#about to read 6, iclass 11, count 0 2006.201.14:38:27.25#ibcon#read 6, iclass 11, count 0 2006.201.14:38:27.25#ibcon#end of sib2, iclass 11, count 0 2006.201.14:38:27.25#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:38:27.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:38:27.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:38:27.25#ibcon#*before write, iclass 11, count 0 2006.201.14:38:27.25#ibcon#enter sib2, iclass 11, count 0 2006.201.14:38:27.25#ibcon#flushed, iclass 11, count 0 2006.201.14:38:27.25#ibcon#about to write, iclass 11, count 0 2006.201.14:38:27.25#ibcon#wrote, iclass 11, count 0 2006.201.14:38:27.25#ibcon#about to read 3, iclass 11, count 0 2006.201.14:38:27.29#ibcon#read 3, iclass 11, count 0 2006.201.14:38:27.29#ibcon#about to read 4, iclass 11, count 0 2006.201.14:38:27.29#ibcon#read 4, iclass 11, count 0 2006.201.14:38:27.29#ibcon#about to read 5, iclass 11, count 0 2006.201.14:38:27.29#ibcon#read 5, iclass 11, count 0 2006.201.14:38:27.29#ibcon#about to read 6, iclass 11, count 0 2006.201.14:38:27.29#ibcon#read 6, iclass 11, count 0 2006.201.14:38:27.29#ibcon#end of sib2, iclass 11, count 0 2006.201.14:38:27.29#ibcon#*after write, iclass 11, count 0 2006.201.14:38:27.29#ibcon#*before return 0, iclass 11, count 0 2006.201.14:38:27.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:27.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:27.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:38:27.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:38:27.29$vck44/va=2,7 2006.201.14:38:27.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.14:38:27.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.14:38:27.29#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:27.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:27.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:27.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:27.35#ibcon#enter wrdev, iclass 13, count 2 2006.201.14:38:27.35#ibcon#first serial, iclass 13, count 2 2006.201.14:38:27.35#ibcon#enter sib2, iclass 13, count 2 2006.201.14:38:27.35#ibcon#flushed, iclass 13, count 2 2006.201.14:38:27.35#ibcon#about to write, iclass 13, count 2 2006.201.14:38:27.35#ibcon#wrote, iclass 13, count 2 2006.201.14:38:27.35#ibcon#about to read 3, iclass 13, count 2 2006.201.14:38:27.37#ibcon#read 3, iclass 13, count 2 2006.201.14:38:27.37#ibcon#about to read 4, iclass 13, count 2 2006.201.14:38:27.37#ibcon#read 4, iclass 13, count 2 2006.201.14:38:27.37#ibcon#about to read 5, iclass 13, count 2 2006.201.14:38:27.37#ibcon#read 5, iclass 13, count 2 2006.201.14:38:27.37#ibcon#about to read 6, iclass 13, count 2 2006.201.14:38:27.37#ibcon#read 6, iclass 13, count 2 2006.201.14:38:27.37#ibcon#end of sib2, iclass 13, count 2 2006.201.14:38:27.37#ibcon#*mode == 0, iclass 13, count 2 2006.201.14:38:27.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.14:38:27.37#ibcon#[25=AT02-07\r\n] 2006.201.14:38:27.37#ibcon#*before write, iclass 13, count 2 2006.201.14:38:27.37#ibcon#enter sib2, iclass 13, count 2 2006.201.14:38:27.37#ibcon#flushed, iclass 13, count 2 2006.201.14:38:27.37#ibcon#about to write, iclass 13, count 2 2006.201.14:38:27.37#ibcon#wrote, iclass 13, count 2 2006.201.14:38:27.37#ibcon#about to read 3, iclass 13, count 2 2006.201.14:38:27.40#ibcon#read 3, iclass 13, count 2 2006.201.14:38:27.40#ibcon#about to read 4, iclass 13, count 2 2006.201.14:38:27.40#ibcon#read 4, iclass 13, count 2 2006.201.14:38:27.40#ibcon#about to read 5, iclass 13, count 2 2006.201.14:38:27.40#ibcon#read 5, iclass 13, count 2 2006.201.14:38:27.40#ibcon#about to read 6, iclass 13, count 2 2006.201.14:38:27.40#ibcon#read 6, iclass 13, count 2 2006.201.14:38:27.40#ibcon#end of sib2, iclass 13, count 2 2006.201.14:38:27.40#ibcon#*after write, iclass 13, count 2 2006.201.14:38:27.40#ibcon#*before return 0, iclass 13, count 2 2006.201.14:38:27.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:27.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:27.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.14:38:27.40#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:27.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:27.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:27.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:27.52#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:38:27.52#ibcon#first serial, iclass 13, count 0 2006.201.14:38:27.52#ibcon#enter sib2, iclass 13, count 0 2006.201.14:38:27.52#ibcon#flushed, iclass 13, count 0 2006.201.14:38:27.52#ibcon#about to write, iclass 13, count 0 2006.201.14:38:27.52#ibcon#wrote, iclass 13, count 0 2006.201.14:38:27.52#ibcon#about to read 3, iclass 13, count 0 2006.201.14:38:27.54#ibcon#read 3, iclass 13, count 0 2006.201.14:38:27.54#ibcon#about to read 4, iclass 13, count 0 2006.201.14:38:27.54#ibcon#read 4, iclass 13, count 0 2006.201.14:38:27.54#ibcon#about to read 5, iclass 13, count 0 2006.201.14:38:27.54#ibcon#read 5, iclass 13, count 0 2006.201.14:38:27.54#ibcon#about to read 6, iclass 13, count 0 2006.201.14:38:27.54#ibcon#read 6, iclass 13, count 0 2006.201.14:38:27.54#ibcon#end of sib2, iclass 13, count 0 2006.201.14:38:27.54#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:38:27.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:38:27.54#ibcon#[25=USB\r\n] 2006.201.14:38:27.54#ibcon#*before write, iclass 13, count 0 2006.201.14:38:27.54#ibcon#enter sib2, iclass 13, count 0 2006.201.14:38:27.54#ibcon#flushed, iclass 13, count 0 2006.201.14:38:27.54#ibcon#about to write, iclass 13, count 0 2006.201.14:38:27.54#ibcon#wrote, iclass 13, count 0 2006.201.14:38:27.54#ibcon#about to read 3, iclass 13, count 0 2006.201.14:38:27.57#ibcon#read 3, iclass 13, count 0 2006.201.14:38:27.57#ibcon#about to read 4, iclass 13, count 0 2006.201.14:38:27.57#ibcon#read 4, iclass 13, count 0 2006.201.14:38:27.57#ibcon#about to read 5, iclass 13, count 0 2006.201.14:38:27.57#ibcon#read 5, iclass 13, count 0 2006.201.14:38:27.57#ibcon#about to read 6, iclass 13, count 0 2006.201.14:38:27.57#ibcon#read 6, iclass 13, count 0 2006.201.14:38:27.57#ibcon#end of sib2, iclass 13, count 0 2006.201.14:38:27.57#ibcon#*after write, iclass 13, count 0 2006.201.14:38:27.57#ibcon#*before return 0, iclass 13, count 0 2006.201.14:38:27.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:27.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:27.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:38:27.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:38:27.57$vck44/valo=3,564.99 2006.201.14:38:27.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.14:38:27.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.14:38:27.57#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:27.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:27.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:27.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:27.57#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:38:27.57#ibcon#first serial, iclass 15, count 0 2006.201.14:38:27.57#ibcon#enter sib2, iclass 15, count 0 2006.201.14:38:27.57#ibcon#flushed, iclass 15, count 0 2006.201.14:38:27.57#ibcon#about to write, iclass 15, count 0 2006.201.14:38:27.57#ibcon#wrote, iclass 15, count 0 2006.201.14:38:27.57#ibcon#about to read 3, iclass 15, count 0 2006.201.14:38:27.59#ibcon#read 3, iclass 15, count 0 2006.201.14:38:27.59#ibcon#about to read 4, iclass 15, count 0 2006.201.14:38:27.59#ibcon#read 4, iclass 15, count 0 2006.201.14:38:27.59#ibcon#about to read 5, iclass 15, count 0 2006.201.14:38:27.59#ibcon#read 5, iclass 15, count 0 2006.201.14:38:27.59#ibcon#about to read 6, iclass 15, count 0 2006.201.14:38:27.59#ibcon#read 6, iclass 15, count 0 2006.201.14:38:27.59#ibcon#end of sib2, iclass 15, count 0 2006.201.14:38:27.59#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:38:27.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:38:27.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:38:27.59#ibcon#*before write, iclass 15, count 0 2006.201.14:38:27.59#ibcon#enter sib2, iclass 15, count 0 2006.201.14:38:27.59#ibcon#flushed, iclass 15, count 0 2006.201.14:38:27.59#ibcon#about to write, iclass 15, count 0 2006.201.14:38:27.59#ibcon#wrote, iclass 15, count 0 2006.201.14:38:27.59#ibcon#about to read 3, iclass 15, count 0 2006.201.14:38:27.64#ibcon#read 3, iclass 15, count 0 2006.201.14:38:27.64#ibcon#about to read 4, iclass 15, count 0 2006.201.14:38:27.64#ibcon#read 4, iclass 15, count 0 2006.201.14:38:27.64#ibcon#about to read 5, iclass 15, count 0 2006.201.14:38:27.64#ibcon#read 5, iclass 15, count 0 2006.201.14:38:27.64#ibcon#about to read 6, iclass 15, count 0 2006.201.14:38:27.64#ibcon#read 6, iclass 15, count 0 2006.201.14:38:27.64#ibcon#end of sib2, iclass 15, count 0 2006.201.14:38:27.64#ibcon#*after write, iclass 15, count 0 2006.201.14:38:27.64#ibcon#*before return 0, iclass 15, count 0 2006.201.14:38:27.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:27.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:27.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:38:27.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:38:27.64$vck44/va=3,8 2006.201.14:38:27.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.14:38:27.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.14:38:27.64#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:27.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:27.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:27.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:27.69#ibcon#enter wrdev, iclass 17, count 2 2006.201.14:38:27.69#ibcon#first serial, iclass 17, count 2 2006.201.14:38:27.69#ibcon#enter sib2, iclass 17, count 2 2006.201.14:38:27.69#ibcon#flushed, iclass 17, count 2 2006.201.14:38:27.69#ibcon#about to write, iclass 17, count 2 2006.201.14:38:27.69#ibcon#wrote, iclass 17, count 2 2006.201.14:38:27.69#ibcon#about to read 3, iclass 17, count 2 2006.201.14:38:27.71#ibcon#read 3, iclass 17, count 2 2006.201.14:38:27.71#ibcon#about to read 4, iclass 17, count 2 2006.201.14:38:27.71#ibcon#read 4, iclass 17, count 2 2006.201.14:38:27.71#ibcon#about to read 5, iclass 17, count 2 2006.201.14:38:27.71#ibcon#read 5, iclass 17, count 2 2006.201.14:38:27.71#ibcon#about to read 6, iclass 17, count 2 2006.201.14:38:27.71#ibcon#read 6, iclass 17, count 2 2006.201.14:38:27.71#ibcon#end of sib2, iclass 17, count 2 2006.201.14:38:27.71#ibcon#*mode == 0, iclass 17, count 2 2006.201.14:38:27.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.14:38:27.71#ibcon#[25=AT03-08\r\n] 2006.201.14:38:27.71#ibcon#*before write, iclass 17, count 2 2006.201.14:38:27.71#ibcon#enter sib2, iclass 17, count 2 2006.201.14:38:27.71#ibcon#flushed, iclass 17, count 2 2006.201.14:38:27.71#ibcon#about to write, iclass 17, count 2 2006.201.14:38:27.71#ibcon#wrote, iclass 17, count 2 2006.201.14:38:27.71#ibcon#about to read 3, iclass 17, count 2 2006.201.14:38:27.74#ibcon#read 3, iclass 17, count 2 2006.201.14:38:27.74#ibcon#about to read 4, iclass 17, count 2 2006.201.14:38:27.74#ibcon#read 4, iclass 17, count 2 2006.201.14:38:27.74#ibcon#about to read 5, iclass 17, count 2 2006.201.14:38:27.74#ibcon#read 5, iclass 17, count 2 2006.201.14:38:27.74#ibcon#about to read 6, iclass 17, count 2 2006.201.14:38:27.74#ibcon#read 6, iclass 17, count 2 2006.201.14:38:27.74#ibcon#end of sib2, iclass 17, count 2 2006.201.14:38:27.74#ibcon#*after write, iclass 17, count 2 2006.201.14:38:27.74#ibcon#*before return 0, iclass 17, count 2 2006.201.14:38:27.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:27.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:27.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.14:38:27.74#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:27.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:27.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:27.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:27.86#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:38:27.86#ibcon#first serial, iclass 17, count 0 2006.201.14:38:27.86#ibcon#enter sib2, iclass 17, count 0 2006.201.14:38:27.86#ibcon#flushed, iclass 17, count 0 2006.201.14:38:27.86#ibcon#about to write, iclass 17, count 0 2006.201.14:38:27.86#ibcon#wrote, iclass 17, count 0 2006.201.14:38:27.86#ibcon#about to read 3, iclass 17, count 0 2006.201.14:38:27.88#ibcon#read 3, iclass 17, count 0 2006.201.14:38:27.88#ibcon#about to read 4, iclass 17, count 0 2006.201.14:38:27.88#ibcon#read 4, iclass 17, count 0 2006.201.14:38:27.88#ibcon#about to read 5, iclass 17, count 0 2006.201.14:38:27.88#ibcon#read 5, iclass 17, count 0 2006.201.14:38:27.88#ibcon#about to read 6, iclass 17, count 0 2006.201.14:38:27.88#ibcon#read 6, iclass 17, count 0 2006.201.14:38:27.88#ibcon#end of sib2, iclass 17, count 0 2006.201.14:38:27.88#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:38:27.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:38:27.88#ibcon#[25=USB\r\n] 2006.201.14:38:27.88#ibcon#*before write, iclass 17, count 0 2006.201.14:38:27.88#ibcon#enter sib2, iclass 17, count 0 2006.201.14:38:27.88#ibcon#flushed, iclass 17, count 0 2006.201.14:38:27.88#ibcon#about to write, iclass 17, count 0 2006.201.14:38:27.88#ibcon#wrote, iclass 17, count 0 2006.201.14:38:27.88#ibcon#about to read 3, iclass 17, count 0 2006.201.14:38:27.91#ibcon#read 3, iclass 17, count 0 2006.201.14:38:27.91#ibcon#about to read 4, iclass 17, count 0 2006.201.14:38:27.91#ibcon#read 4, iclass 17, count 0 2006.201.14:38:27.91#ibcon#about to read 5, iclass 17, count 0 2006.201.14:38:27.91#ibcon#read 5, iclass 17, count 0 2006.201.14:38:27.91#ibcon#about to read 6, iclass 17, count 0 2006.201.14:38:27.91#ibcon#read 6, iclass 17, count 0 2006.201.14:38:27.91#ibcon#end of sib2, iclass 17, count 0 2006.201.14:38:27.91#ibcon#*after write, iclass 17, count 0 2006.201.14:38:27.91#ibcon#*before return 0, iclass 17, count 0 2006.201.14:38:27.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:27.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:27.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:38:27.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:38:27.91$vck44/valo=4,624.99 2006.201.14:38:27.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.14:38:27.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.14:38:27.91#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:27.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:27.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:27.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:27.91#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:38:27.91#ibcon#first serial, iclass 19, count 0 2006.201.14:38:27.91#ibcon#enter sib2, iclass 19, count 0 2006.201.14:38:27.91#ibcon#flushed, iclass 19, count 0 2006.201.14:38:27.91#ibcon#about to write, iclass 19, count 0 2006.201.14:38:27.91#ibcon#wrote, iclass 19, count 0 2006.201.14:38:27.91#ibcon#about to read 3, iclass 19, count 0 2006.201.14:38:27.93#ibcon#read 3, iclass 19, count 0 2006.201.14:38:27.93#ibcon#about to read 4, iclass 19, count 0 2006.201.14:38:27.93#ibcon#read 4, iclass 19, count 0 2006.201.14:38:27.93#ibcon#about to read 5, iclass 19, count 0 2006.201.14:38:27.93#ibcon#read 5, iclass 19, count 0 2006.201.14:38:27.93#ibcon#about to read 6, iclass 19, count 0 2006.201.14:38:27.93#ibcon#read 6, iclass 19, count 0 2006.201.14:38:27.93#ibcon#end of sib2, iclass 19, count 0 2006.201.14:38:27.93#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:38:27.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:38:27.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:38:27.93#ibcon#*before write, iclass 19, count 0 2006.201.14:38:27.93#ibcon#enter sib2, iclass 19, count 0 2006.201.14:38:27.93#ibcon#flushed, iclass 19, count 0 2006.201.14:38:27.93#ibcon#about to write, iclass 19, count 0 2006.201.14:38:27.93#ibcon#wrote, iclass 19, count 0 2006.201.14:38:27.93#ibcon#about to read 3, iclass 19, count 0 2006.201.14:38:27.98#ibcon#read 3, iclass 19, count 0 2006.201.14:38:27.98#ibcon#about to read 4, iclass 19, count 0 2006.201.14:38:27.98#ibcon#read 4, iclass 19, count 0 2006.201.14:38:27.98#ibcon#about to read 5, iclass 19, count 0 2006.201.14:38:27.98#ibcon#read 5, iclass 19, count 0 2006.201.14:38:27.98#ibcon#about to read 6, iclass 19, count 0 2006.201.14:38:27.98#ibcon#read 6, iclass 19, count 0 2006.201.14:38:27.98#ibcon#end of sib2, iclass 19, count 0 2006.201.14:38:27.98#ibcon#*after write, iclass 19, count 0 2006.201.14:38:27.98#ibcon#*before return 0, iclass 19, count 0 2006.201.14:38:27.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:27.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:27.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:38:27.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:38:27.98$vck44/va=4,7 2006.201.14:38:27.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.14:38:27.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.14:38:27.98#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:27.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:28.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:28.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:28.03#ibcon#enter wrdev, iclass 21, count 2 2006.201.14:38:28.03#ibcon#first serial, iclass 21, count 2 2006.201.14:38:28.03#ibcon#enter sib2, iclass 21, count 2 2006.201.14:38:28.03#ibcon#flushed, iclass 21, count 2 2006.201.14:38:28.03#ibcon#about to write, iclass 21, count 2 2006.201.14:38:28.03#ibcon#wrote, iclass 21, count 2 2006.201.14:38:28.03#ibcon#about to read 3, iclass 21, count 2 2006.201.14:38:28.05#ibcon#read 3, iclass 21, count 2 2006.201.14:38:28.05#ibcon#about to read 4, iclass 21, count 2 2006.201.14:38:28.05#ibcon#read 4, iclass 21, count 2 2006.201.14:38:28.05#ibcon#about to read 5, iclass 21, count 2 2006.201.14:38:28.05#ibcon#read 5, iclass 21, count 2 2006.201.14:38:28.05#ibcon#about to read 6, iclass 21, count 2 2006.201.14:38:28.05#ibcon#read 6, iclass 21, count 2 2006.201.14:38:28.05#ibcon#end of sib2, iclass 21, count 2 2006.201.14:38:28.05#ibcon#*mode == 0, iclass 21, count 2 2006.201.14:38:28.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.14:38:28.05#ibcon#[25=AT04-07\r\n] 2006.201.14:38:28.05#ibcon#*before write, iclass 21, count 2 2006.201.14:38:28.05#ibcon#enter sib2, iclass 21, count 2 2006.201.14:38:28.05#ibcon#flushed, iclass 21, count 2 2006.201.14:38:28.05#ibcon#about to write, iclass 21, count 2 2006.201.14:38:28.05#ibcon#wrote, iclass 21, count 2 2006.201.14:38:28.05#ibcon#about to read 3, iclass 21, count 2 2006.201.14:38:28.08#ibcon#read 3, iclass 21, count 2 2006.201.14:38:28.08#ibcon#about to read 4, iclass 21, count 2 2006.201.14:38:28.08#ibcon#read 4, iclass 21, count 2 2006.201.14:38:28.08#ibcon#about to read 5, iclass 21, count 2 2006.201.14:38:28.08#ibcon#read 5, iclass 21, count 2 2006.201.14:38:28.08#ibcon#about to read 6, iclass 21, count 2 2006.201.14:38:28.08#ibcon#read 6, iclass 21, count 2 2006.201.14:38:28.08#ibcon#end of sib2, iclass 21, count 2 2006.201.14:38:28.08#ibcon#*after write, iclass 21, count 2 2006.201.14:38:28.08#ibcon#*before return 0, iclass 21, count 2 2006.201.14:38:28.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:28.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:28.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.14:38:28.08#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:28.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:28.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:28.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:28.20#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:38:28.20#ibcon#first serial, iclass 21, count 0 2006.201.14:38:28.20#ibcon#enter sib2, iclass 21, count 0 2006.201.14:38:28.20#ibcon#flushed, iclass 21, count 0 2006.201.14:38:28.20#ibcon#about to write, iclass 21, count 0 2006.201.14:38:28.20#ibcon#wrote, iclass 21, count 0 2006.201.14:38:28.20#ibcon#about to read 3, iclass 21, count 0 2006.201.14:38:28.22#ibcon#read 3, iclass 21, count 0 2006.201.14:38:28.22#ibcon#about to read 4, iclass 21, count 0 2006.201.14:38:28.22#ibcon#read 4, iclass 21, count 0 2006.201.14:38:28.22#ibcon#about to read 5, iclass 21, count 0 2006.201.14:38:28.22#ibcon#read 5, iclass 21, count 0 2006.201.14:38:28.22#ibcon#about to read 6, iclass 21, count 0 2006.201.14:38:28.22#ibcon#read 6, iclass 21, count 0 2006.201.14:38:28.22#ibcon#end of sib2, iclass 21, count 0 2006.201.14:38:28.22#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:38:28.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:38:28.22#ibcon#[25=USB\r\n] 2006.201.14:38:28.22#ibcon#*before write, iclass 21, count 0 2006.201.14:38:28.22#ibcon#enter sib2, iclass 21, count 0 2006.201.14:38:28.22#ibcon#flushed, iclass 21, count 0 2006.201.14:38:28.22#ibcon#about to write, iclass 21, count 0 2006.201.14:38:28.22#ibcon#wrote, iclass 21, count 0 2006.201.14:38:28.22#ibcon#about to read 3, iclass 21, count 0 2006.201.14:38:28.25#ibcon#read 3, iclass 21, count 0 2006.201.14:38:28.25#ibcon#about to read 4, iclass 21, count 0 2006.201.14:38:28.25#ibcon#read 4, iclass 21, count 0 2006.201.14:38:28.25#ibcon#about to read 5, iclass 21, count 0 2006.201.14:38:28.25#ibcon#read 5, iclass 21, count 0 2006.201.14:38:28.25#ibcon#about to read 6, iclass 21, count 0 2006.201.14:38:28.25#ibcon#read 6, iclass 21, count 0 2006.201.14:38:28.25#ibcon#end of sib2, iclass 21, count 0 2006.201.14:38:28.25#ibcon#*after write, iclass 21, count 0 2006.201.14:38:28.25#ibcon#*before return 0, iclass 21, count 0 2006.201.14:38:28.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:28.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:28.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:38:28.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:38:28.25$vck44/valo=5,734.99 2006.201.14:38:28.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.14:38:28.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.14:38:28.25#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:28.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:28.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:28.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:28.25#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:38:28.25#ibcon#first serial, iclass 23, count 0 2006.201.14:38:28.25#ibcon#enter sib2, iclass 23, count 0 2006.201.14:38:28.25#ibcon#flushed, iclass 23, count 0 2006.201.14:38:28.25#ibcon#about to write, iclass 23, count 0 2006.201.14:38:28.25#ibcon#wrote, iclass 23, count 0 2006.201.14:38:28.25#ibcon#about to read 3, iclass 23, count 0 2006.201.14:38:28.27#ibcon#read 3, iclass 23, count 0 2006.201.14:38:28.27#ibcon#about to read 4, iclass 23, count 0 2006.201.14:38:28.27#ibcon#read 4, iclass 23, count 0 2006.201.14:38:28.27#ibcon#about to read 5, iclass 23, count 0 2006.201.14:38:28.27#ibcon#read 5, iclass 23, count 0 2006.201.14:38:28.27#ibcon#about to read 6, iclass 23, count 0 2006.201.14:38:28.27#ibcon#read 6, iclass 23, count 0 2006.201.14:38:28.27#ibcon#end of sib2, iclass 23, count 0 2006.201.14:38:28.27#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:38:28.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:38:28.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:38:28.27#ibcon#*before write, iclass 23, count 0 2006.201.14:38:28.27#ibcon#enter sib2, iclass 23, count 0 2006.201.14:38:28.27#ibcon#flushed, iclass 23, count 0 2006.201.14:38:28.27#ibcon#about to write, iclass 23, count 0 2006.201.14:38:28.27#ibcon#wrote, iclass 23, count 0 2006.201.14:38:28.27#ibcon#about to read 3, iclass 23, count 0 2006.201.14:38:28.31#ibcon#read 3, iclass 23, count 0 2006.201.14:38:28.31#ibcon#about to read 4, iclass 23, count 0 2006.201.14:38:28.31#ibcon#read 4, iclass 23, count 0 2006.201.14:38:28.31#ibcon#about to read 5, iclass 23, count 0 2006.201.14:38:28.31#ibcon#read 5, iclass 23, count 0 2006.201.14:38:28.31#ibcon#about to read 6, iclass 23, count 0 2006.201.14:38:28.31#ibcon#read 6, iclass 23, count 0 2006.201.14:38:28.31#ibcon#end of sib2, iclass 23, count 0 2006.201.14:38:28.31#ibcon#*after write, iclass 23, count 0 2006.201.14:38:28.31#ibcon#*before return 0, iclass 23, count 0 2006.201.14:38:28.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:28.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:28.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:38:28.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:38:28.31$vck44/va=5,4 2006.201.14:38:28.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.14:38:28.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.14:38:28.31#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:28.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:28.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:28.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:28.37#ibcon#enter wrdev, iclass 25, count 2 2006.201.14:38:28.37#ibcon#first serial, iclass 25, count 2 2006.201.14:38:28.37#ibcon#enter sib2, iclass 25, count 2 2006.201.14:38:28.37#ibcon#flushed, iclass 25, count 2 2006.201.14:38:28.37#ibcon#about to write, iclass 25, count 2 2006.201.14:38:28.37#ibcon#wrote, iclass 25, count 2 2006.201.14:38:28.37#ibcon#about to read 3, iclass 25, count 2 2006.201.14:38:28.39#ibcon#read 3, iclass 25, count 2 2006.201.14:38:28.39#ibcon#about to read 4, iclass 25, count 2 2006.201.14:38:28.39#ibcon#read 4, iclass 25, count 2 2006.201.14:38:28.39#ibcon#about to read 5, iclass 25, count 2 2006.201.14:38:28.39#ibcon#read 5, iclass 25, count 2 2006.201.14:38:28.39#ibcon#about to read 6, iclass 25, count 2 2006.201.14:38:28.39#ibcon#read 6, iclass 25, count 2 2006.201.14:38:28.39#ibcon#end of sib2, iclass 25, count 2 2006.201.14:38:28.39#ibcon#*mode == 0, iclass 25, count 2 2006.201.14:38:28.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.14:38:28.39#ibcon#[25=AT05-04\r\n] 2006.201.14:38:28.39#ibcon#*before write, iclass 25, count 2 2006.201.14:38:28.39#ibcon#enter sib2, iclass 25, count 2 2006.201.14:38:28.39#ibcon#flushed, iclass 25, count 2 2006.201.14:38:28.39#ibcon#about to write, iclass 25, count 2 2006.201.14:38:28.39#ibcon#wrote, iclass 25, count 2 2006.201.14:38:28.39#ibcon#about to read 3, iclass 25, count 2 2006.201.14:38:28.42#ibcon#read 3, iclass 25, count 2 2006.201.14:38:28.42#ibcon#about to read 4, iclass 25, count 2 2006.201.14:38:28.42#ibcon#read 4, iclass 25, count 2 2006.201.14:38:28.42#ibcon#about to read 5, iclass 25, count 2 2006.201.14:38:28.42#ibcon#read 5, iclass 25, count 2 2006.201.14:38:28.42#ibcon#about to read 6, iclass 25, count 2 2006.201.14:38:28.42#ibcon#read 6, iclass 25, count 2 2006.201.14:38:28.42#ibcon#end of sib2, iclass 25, count 2 2006.201.14:38:28.42#ibcon#*after write, iclass 25, count 2 2006.201.14:38:28.42#ibcon#*before return 0, iclass 25, count 2 2006.201.14:38:28.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:28.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:28.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.14:38:28.42#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:28.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:28.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:28.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:28.54#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:38:28.54#ibcon#first serial, iclass 25, count 0 2006.201.14:38:28.54#ibcon#enter sib2, iclass 25, count 0 2006.201.14:38:28.54#ibcon#flushed, iclass 25, count 0 2006.201.14:38:28.54#ibcon#about to write, iclass 25, count 0 2006.201.14:38:28.54#ibcon#wrote, iclass 25, count 0 2006.201.14:38:28.54#ibcon#about to read 3, iclass 25, count 0 2006.201.14:38:28.56#ibcon#read 3, iclass 25, count 0 2006.201.14:38:28.56#ibcon#about to read 4, iclass 25, count 0 2006.201.14:38:28.56#ibcon#read 4, iclass 25, count 0 2006.201.14:38:28.56#ibcon#about to read 5, iclass 25, count 0 2006.201.14:38:28.56#ibcon#read 5, iclass 25, count 0 2006.201.14:38:28.56#ibcon#about to read 6, iclass 25, count 0 2006.201.14:38:28.56#ibcon#read 6, iclass 25, count 0 2006.201.14:38:28.56#ibcon#end of sib2, iclass 25, count 0 2006.201.14:38:28.56#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:38:28.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:38:28.56#ibcon#[25=USB\r\n] 2006.201.14:38:28.56#ibcon#*before write, iclass 25, count 0 2006.201.14:38:28.56#ibcon#enter sib2, iclass 25, count 0 2006.201.14:38:28.56#ibcon#flushed, iclass 25, count 0 2006.201.14:38:28.56#ibcon#about to write, iclass 25, count 0 2006.201.14:38:28.56#ibcon#wrote, iclass 25, count 0 2006.201.14:38:28.56#ibcon#about to read 3, iclass 25, count 0 2006.201.14:38:28.59#ibcon#read 3, iclass 25, count 0 2006.201.14:38:28.59#ibcon#about to read 4, iclass 25, count 0 2006.201.14:38:28.59#ibcon#read 4, iclass 25, count 0 2006.201.14:38:28.59#ibcon#about to read 5, iclass 25, count 0 2006.201.14:38:28.59#ibcon#read 5, iclass 25, count 0 2006.201.14:38:28.59#ibcon#about to read 6, iclass 25, count 0 2006.201.14:38:28.59#ibcon#read 6, iclass 25, count 0 2006.201.14:38:28.59#ibcon#end of sib2, iclass 25, count 0 2006.201.14:38:28.59#ibcon#*after write, iclass 25, count 0 2006.201.14:38:28.59#ibcon#*before return 0, iclass 25, count 0 2006.201.14:38:28.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:28.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:28.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:38:28.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:38:28.59$vck44/valo=6,814.99 2006.201.14:38:28.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.14:38:28.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.14:38:28.59#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:28.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:28.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:28.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:28.59#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:38:28.59#ibcon#first serial, iclass 27, count 0 2006.201.14:38:28.59#ibcon#enter sib2, iclass 27, count 0 2006.201.14:38:28.59#ibcon#flushed, iclass 27, count 0 2006.201.14:38:28.59#ibcon#about to write, iclass 27, count 0 2006.201.14:38:28.59#ibcon#wrote, iclass 27, count 0 2006.201.14:38:28.59#ibcon#about to read 3, iclass 27, count 0 2006.201.14:38:28.61#ibcon#read 3, iclass 27, count 0 2006.201.14:38:28.61#ibcon#about to read 4, iclass 27, count 0 2006.201.14:38:28.61#ibcon#read 4, iclass 27, count 0 2006.201.14:38:28.61#ibcon#about to read 5, iclass 27, count 0 2006.201.14:38:28.61#ibcon#read 5, iclass 27, count 0 2006.201.14:38:28.61#ibcon#about to read 6, iclass 27, count 0 2006.201.14:38:28.61#ibcon#read 6, iclass 27, count 0 2006.201.14:38:28.61#ibcon#end of sib2, iclass 27, count 0 2006.201.14:38:28.61#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:38:28.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:38:28.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:38:28.61#ibcon#*before write, iclass 27, count 0 2006.201.14:38:28.61#ibcon#enter sib2, iclass 27, count 0 2006.201.14:38:28.61#ibcon#flushed, iclass 27, count 0 2006.201.14:38:28.61#ibcon#about to write, iclass 27, count 0 2006.201.14:38:28.61#ibcon#wrote, iclass 27, count 0 2006.201.14:38:28.61#ibcon#about to read 3, iclass 27, count 0 2006.201.14:38:28.65#ibcon#read 3, iclass 27, count 0 2006.201.14:38:28.65#ibcon#about to read 4, iclass 27, count 0 2006.201.14:38:28.65#ibcon#read 4, iclass 27, count 0 2006.201.14:38:28.65#ibcon#about to read 5, iclass 27, count 0 2006.201.14:38:28.65#ibcon#read 5, iclass 27, count 0 2006.201.14:38:28.65#ibcon#about to read 6, iclass 27, count 0 2006.201.14:38:28.65#ibcon#read 6, iclass 27, count 0 2006.201.14:38:28.65#ibcon#end of sib2, iclass 27, count 0 2006.201.14:38:28.65#ibcon#*after write, iclass 27, count 0 2006.201.14:38:28.65#ibcon#*before return 0, iclass 27, count 0 2006.201.14:38:28.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:28.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:28.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:38:28.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:38:28.65$vck44/va=6,5 2006.201.14:38:28.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.14:38:28.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.14:38:28.65#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:28.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:28.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:28.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:28.71#ibcon#enter wrdev, iclass 29, count 2 2006.201.14:38:28.71#ibcon#first serial, iclass 29, count 2 2006.201.14:38:28.71#ibcon#enter sib2, iclass 29, count 2 2006.201.14:38:28.71#ibcon#flushed, iclass 29, count 2 2006.201.14:38:28.71#ibcon#about to write, iclass 29, count 2 2006.201.14:38:28.71#ibcon#wrote, iclass 29, count 2 2006.201.14:38:28.71#ibcon#about to read 3, iclass 29, count 2 2006.201.14:38:28.73#ibcon#read 3, iclass 29, count 2 2006.201.14:38:28.73#ibcon#about to read 4, iclass 29, count 2 2006.201.14:38:28.73#ibcon#read 4, iclass 29, count 2 2006.201.14:38:28.73#ibcon#about to read 5, iclass 29, count 2 2006.201.14:38:28.73#ibcon#read 5, iclass 29, count 2 2006.201.14:38:28.73#ibcon#about to read 6, iclass 29, count 2 2006.201.14:38:28.73#ibcon#read 6, iclass 29, count 2 2006.201.14:38:28.73#ibcon#end of sib2, iclass 29, count 2 2006.201.14:38:28.73#ibcon#*mode == 0, iclass 29, count 2 2006.201.14:38:28.73#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.14:38:28.73#ibcon#[25=AT06-05\r\n] 2006.201.14:38:28.73#ibcon#*before write, iclass 29, count 2 2006.201.14:38:28.73#ibcon#enter sib2, iclass 29, count 2 2006.201.14:38:28.73#ibcon#flushed, iclass 29, count 2 2006.201.14:38:28.73#ibcon#about to write, iclass 29, count 2 2006.201.14:38:28.73#ibcon#wrote, iclass 29, count 2 2006.201.14:38:28.73#ibcon#about to read 3, iclass 29, count 2 2006.201.14:38:28.76#ibcon#read 3, iclass 29, count 2 2006.201.14:38:28.76#ibcon#about to read 4, iclass 29, count 2 2006.201.14:38:28.76#ibcon#read 4, iclass 29, count 2 2006.201.14:38:28.76#ibcon#about to read 5, iclass 29, count 2 2006.201.14:38:28.76#ibcon#read 5, iclass 29, count 2 2006.201.14:38:28.76#ibcon#about to read 6, iclass 29, count 2 2006.201.14:38:28.76#ibcon#read 6, iclass 29, count 2 2006.201.14:38:28.76#ibcon#end of sib2, iclass 29, count 2 2006.201.14:38:28.76#ibcon#*after write, iclass 29, count 2 2006.201.14:38:28.76#ibcon#*before return 0, iclass 29, count 2 2006.201.14:38:28.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:28.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:28.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.14:38:28.76#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:28.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:28.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:28.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:28.88#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:38:28.88#ibcon#first serial, iclass 29, count 0 2006.201.14:38:28.88#ibcon#enter sib2, iclass 29, count 0 2006.201.14:38:28.88#ibcon#flushed, iclass 29, count 0 2006.201.14:38:28.88#ibcon#about to write, iclass 29, count 0 2006.201.14:38:28.88#ibcon#wrote, iclass 29, count 0 2006.201.14:38:28.88#ibcon#about to read 3, iclass 29, count 0 2006.201.14:38:28.90#ibcon#read 3, iclass 29, count 0 2006.201.14:38:28.90#ibcon#about to read 4, iclass 29, count 0 2006.201.14:38:28.90#ibcon#read 4, iclass 29, count 0 2006.201.14:38:28.90#ibcon#about to read 5, iclass 29, count 0 2006.201.14:38:28.90#ibcon#read 5, iclass 29, count 0 2006.201.14:38:28.90#ibcon#about to read 6, iclass 29, count 0 2006.201.14:38:28.90#ibcon#read 6, iclass 29, count 0 2006.201.14:38:28.90#ibcon#end of sib2, iclass 29, count 0 2006.201.14:38:28.90#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:38:28.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:38:28.90#ibcon#[25=USB\r\n] 2006.201.14:38:28.90#ibcon#*before write, iclass 29, count 0 2006.201.14:38:28.90#ibcon#enter sib2, iclass 29, count 0 2006.201.14:38:28.90#ibcon#flushed, iclass 29, count 0 2006.201.14:38:28.90#ibcon#about to write, iclass 29, count 0 2006.201.14:38:28.90#ibcon#wrote, iclass 29, count 0 2006.201.14:38:28.90#ibcon#about to read 3, iclass 29, count 0 2006.201.14:38:28.93#ibcon#read 3, iclass 29, count 0 2006.201.14:38:28.93#ibcon#about to read 4, iclass 29, count 0 2006.201.14:38:28.93#ibcon#read 4, iclass 29, count 0 2006.201.14:38:28.93#ibcon#about to read 5, iclass 29, count 0 2006.201.14:38:28.93#ibcon#read 5, iclass 29, count 0 2006.201.14:38:28.93#ibcon#about to read 6, iclass 29, count 0 2006.201.14:38:28.93#ibcon#read 6, iclass 29, count 0 2006.201.14:38:28.93#ibcon#end of sib2, iclass 29, count 0 2006.201.14:38:28.93#ibcon#*after write, iclass 29, count 0 2006.201.14:38:28.93#ibcon#*before return 0, iclass 29, count 0 2006.201.14:38:28.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:28.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:28.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:38:28.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:38:28.93$vck44/valo=7,864.99 2006.201.14:38:28.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.14:38:28.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.14:38:28.93#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:28.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:28.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:28.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:28.93#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:38:28.93#ibcon#first serial, iclass 31, count 0 2006.201.14:38:28.93#ibcon#enter sib2, iclass 31, count 0 2006.201.14:38:28.93#ibcon#flushed, iclass 31, count 0 2006.201.14:38:28.93#ibcon#about to write, iclass 31, count 0 2006.201.14:38:28.93#ibcon#wrote, iclass 31, count 0 2006.201.14:38:28.93#ibcon#about to read 3, iclass 31, count 0 2006.201.14:38:28.95#ibcon#read 3, iclass 31, count 0 2006.201.14:38:28.95#ibcon#about to read 4, iclass 31, count 0 2006.201.14:38:28.95#ibcon#read 4, iclass 31, count 0 2006.201.14:38:28.95#ibcon#about to read 5, iclass 31, count 0 2006.201.14:38:28.95#ibcon#read 5, iclass 31, count 0 2006.201.14:38:28.95#ibcon#about to read 6, iclass 31, count 0 2006.201.14:38:28.95#ibcon#read 6, iclass 31, count 0 2006.201.14:38:28.95#ibcon#end of sib2, iclass 31, count 0 2006.201.14:38:28.95#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:38:28.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:38:28.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:38:28.95#ibcon#*before write, iclass 31, count 0 2006.201.14:38:28.95#ibcon#enter sib2, iclass 31, count 0 2006.201.14:38:28.95#ibcon#flushed, iclass 31, count 0 2006.201.14:38:28.95#ibcon#about to write, iclass 31, count 0 2006.201.14:38:28.95#ibcon#wrote, iclass 31, count 0 2006.201.14:38:28.95#ibcon#about to read 3, iclass 31, count 0 2006.201.14:38:29.00#ibcon#read 3, iclass 31, count 0 2006.201.14:38:29.00#ibcon#about to read 4, iclass 31, count 0 2006.201.14:38:29.00#ibcon#read 4, iclass 31, count 0 2006.201.14:38:29.00#ibcon#about to read 5, iclass 31, count 0 2006.201.14:38:29.00#ibcon#read 5, iclass 31, count 0 2006.201.14:38:29.00#ibcon#about to read 6, iclass 31, count 0 2006.201.14:38:29.00#ibcon#read 6, iclass 31, count 0 2006.201.14:38:29.00#ibcon#end of sib2, iclass 31, count 0 2006.201.14:38:29.00#ibcon#*after write, iclass 31, count 0 2006.201.14:38:29.00#ibcon#*before return 0, iclass 31, count 0 2006.201.14:38:29.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:29.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:29.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:38:29.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:38:29.00$vck44/va=7,5 2006.201.14:38:29.00#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.14:38:29.00#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.14:38:29.00#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:29.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:29.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:29.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:29.05#ibcon#enter wrdev, iclass 33, count 2 2006.201.14:38:29.05#ibcon#first serial, iclass 33, count 2 2006.201.14:38:29.05#ibcon#enter sib2, iclass 33, count 2 2006.201.14:38:29.05#ibcon#flushed, iclass 33, count 2 2006.201.14:38:29.05#ibcon#about to write, iclass 33, count 2 2006.201.14:38:29.05#ibcon#wrote, iclass 33, count 2 2006.201.14:38:29.05#ibcon#about to read 3, iclass 33, count 2 2006.201.14:38:29.07#ibcon#read 3, iclass 33, count 2 2006.201.14:38:29.07#ibcon#about to read 4, iclass 33, count 2 2006.201.14:38:29.07#ibcon#read 4, iclass 33, count 2 2006.201.14:38:29.07#ibcon#about to read 5, iclass 33, count 2 2006.201.14:38:29.07#ibcon#read 5, iclass 33, count 2 2006.201.14:38:29.07#ibcon#about to read 6, iclass 33, count 2 2006.201.14:38:29.07#ibcon#read 6, iclass 33, count 2 2006.201.14:38:29.07#ibcon#end of sib2, iclass 33, count 2 2006.201.14:38:29.07#ibcon#*mode == 0, iclass 33, count 2 2006.201.14:38:29.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.14:38:29.07#ibcon#[25=AT07-05\r\n] 2006.201.14:38:29.07#ibcon#*before write, iclass 33, count 2 2006.201.14:38:29.07#ibcon#enter sib2, iclass 33, count 2 2006.201.14:38:29.07#ibcon#flushed, iclass 33, count 2 2006.201.14:38:29.07#ibcon#about to write, iclass 33, count 2 2006.201.14:38:29.07#ibcon#wrote, iclass 33, count 2 2006.201.14:38:29.07#ibcon#about to read 3, iclass 33, count 2 2006.201.14:38:29.10#ibcon#read 3, iclass 33, count 2 2006.201.14:38:29.10#ibcon#about to read 4, iclass 33, count 2 2006.201.14:38:29.10#ibcon#read 4, iclass 33, count 2 2006.201.14:38:29.10#ibcon#about to read 5, iclass 33, count 2 2006.201.14:38:29.10#ibcon#read 5, iclass 33, count 2 2006.201.14:38:29.10#ibcon#about to read 6, iclass 33, count 2 2006.201.14:38:29.10#ibcon#read 6, iclass 33, count 2 2006.201.14:38:29.10#ibcon#end of sib2, iclass 33, count 2 2006.201.14:38:29.10#ibcon#*after write, iclass 33, count 2 2006.201.14:38:29.10#ibcon#*before return 0, iclass 33, count 2 2006.201.14:38:29.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:29.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:29.10#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.14:38:29.10#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:29.10#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:29.22#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:29.22#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:29.22#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:38:29.22#ibcon#first serial, iclass 33, count 0 2006.201.14:38:29.22#ibcon#enter sib2, iclass 33, count 0 2006.201.14:38:29.22#ibcon#flushed, iclass 33, count 0 2006.201.14:38:29.22#ibcon#about to write, iclass 33, count 0 2006.201.14:38:29.22#ibcon#wrote, iclass 33, count 0 2006.201.14:38:29.22#ibcon#about to read 3, iclass 33, count 0 2006.201.14:38:29.24#ibcon#read 3, iclass 33, count 0 2006.201.14:38:29.24#ibcon#about to read 4, iclass 33, count 0 2006.201.14:38:29.24#ibcon#read 4, iclass 33, count 0 2006.201.14:38:29.24#ibcon#about to read 5, iclass 33, count 0 2006.201.14:38:29.24#ibcon#read 5, iclass 33, count 0 2006.201.14:38:29.24#ibcon#about to read 6, iclass 33, count 0 2006.201.14:38:29.24#ibcon#read 6, iclass 33, count 0 2006.201.14:38:29.24#ibcon#end of sib2, iclass 33, count 0 2006.201.14:38:29.24#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:38:29.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:38:29.24#ibcon#[25=USB\r\n] 2006.201.14:38:29.24#ibcon#*before write, iclass 33, count 0 2006.201.14:38:29.24#ibcon#enter sib2, iclass 33, count 0 2006.201.14:38:29.24#ibcon#flushed, iclass 33, count 0 2006.201.14:38:29.24#ibcon#about to write, iclass 33, count 0 2006.201.14:38:29.24#ibcon#wrote, iclass 33, count 0 2006.201.14:38:29.24#ibcon#about to read 3, iclass 33, count 0 2006.201.14:38:29.27#ibcon#read 3, iclass 33, count 0 2006.201.14:38:29.27#ibcon#about to read 4, iclass 33, count 0 2006.201.14:38:29.27#ibcon#read 4, iclass 33, count 0 2006.201.14:38:29.27#ibcon#about to read 5, iclass 33, count 0 2006.201.14:38:29.27#ibcon#read 5, iclass 33, count 0 2006.201.14:38:29.27#ibcon#about to read 6, iclass 33, count 0 2006.201.14:38:29.27#ibcon#read 6, iclass 33, count 0 2006.201.14:38:29.27#ibcon#end of sib2, iclass 33, count 0 2006.201.14:38:29.27#ibcon#*after write, iclass 33, count 0 2006.201.14:38:29.27#ibcon#*before return 0, iclass 33, count 0 2006.201.14:38:29.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:29.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:29.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:38:29.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:38:29.27$vck44/valo=8,884.99 2006.201.14:38:29.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.14:38:29.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.14:38:29.27#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:29.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:29.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:29.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:29.27#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:38:29.27#ibcon#first serial, iclass 35, count 0 2006.201.14:38:29.27#ibcon#enter sib2, iclass 35, count 0 2006.201.14:38:29.27#ibcon#flushed, iclass 35, count 0 2006.201.14:38:29.27#ibcon#about to write, iclass 35, count 0 2006.201.14:38:29.27#ibcon#wrote, iclass 35, count 0 2006.201.14:38:29.27#ibcon#about to read 3, iclass 35, count 0 2006.201.14:38:29.29#ibcon#read 3, iclass 35, count 0 2006.201.14:38:29.29#ibcon#about to read 4, iclass 35, count 0 2006.201.14:38:29.29#ibcon#read 4, iclass 35, count 0 2006.201.14:38:29.29#ibcon#about to read 5, iclass 35, count 0 2006.201.14:38:29.29#ibcon#read 5, iclass 35, count 0 2006.201.14:38:29.29#ibcon#about to read 6, iclass 35, count 0 2006.201.14:38:29.29#ibcon#read 6, iclass 35, count 0 2006.201.14:38:29.29#ibcon#end of sib2, iclass 35, count 0 2006.201.14:38:29.29#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:38:29.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:38:29.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:38:29.29#ibcon#*before write, iclass 35, count 0 2006.201.14:38:29.29#ibcon#enter sib2, iclass 35, count 0 2006.201.14:38:29.29#ibcon#flushed, iclass 35, count 0 2006.201.14:38:29.29#ibcon#about to write, iclass 35, count 0 2006.201.14:38:29.29#ibcon#wrote, iclass 35, count 0 2006.201.14:38:29.29#ibcon#about to read 3, iclass 35, count 0 2006.201.14:38:29.33#ibcon#read 3, iclass 35, count 0 2006.201.14:38:29.33#ibcon#about to read 4, iclass 35, count 0 2006.201.14:38:29.33#ibcon#read 4, iclass 35, count 0 2006.201.14:38:29.33#ibcon#about to read 5, iclass 35, count 0 2006.201.14:38:29.33#ibcon#read 5, iclass 35, count 0 2006.201.14:38:29.33#ibcon#about to read 6, iclass 35, count 0 2006.201.14:38:29.33#ibcon#read 6, iclass 35, count 0 2006.201.14:38:29.33#ibcon#end of sib2, iclass 35, count 0 2006.201.14:38:29.33#ibcon#*after write, iclass 35, count 0 2006.201.14:38:29.33#ibcon#*before return 0, iclass 35, count 0 2006.201.14:38:29.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:29.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:29.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:38:29.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:38:29.33$vck44/va=8,4 2006.201.14:38:29.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.14:38:29.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.14:38:29.33#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:29.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:38:29.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:38:29.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:38:29.39#ibcon#enter wrdev, iclass 37, count 2 2006.201.14:38:29.39#ibcon#first serial, iclass 37, count 2 2006.201.14:38:29.39#ibcon#enter sib2, iclass 37, count 2 2006.201.14:38:29.39#ibcon#flushed, iclass 37, count 2 2006.201.14:38:29.39#ibcon#about to write, iclass 37, count 2 2006.201.14:38:29.39#ibcon#wrote, iclass 37, count 2 2006.201.14:38:29.39#ibcon#about to read 3, iclass 37, count 2 2006.201.14:38:29.41#ibcon#read 3, iclass 37, count 2 2006.201.14:38:29.41#ibcon#about to read 4, iclass 37, count 2 2006.201.14:38:29.41#ibcon#read 4, iclass 37, count 2 2006.201.14:38:29.41#ibcon#about to read 5, iclass 37, count 2 2006.201.14:38:29.41#ibcon#read 5, iclass 37, count 2 2006.201.14:38:29.41#ibcon#about to read 6, iclass 37, count 2 2006.201.14:38:29.41#ibcon#read 6, iclass 37, count 2 2006.201.14:38:29.41#ibcon#end of sib2, iclass 37, count 2 2006.201.14:38:29.41#ibcon#*mode == 0, iclass 37, count 2 2006.201.14:38:29.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.14:38:29.41#ibcon#[25=AT08-04\r\n] 2006.201.14:38:29.41#ibcon#*before write, iclass 37, count 2 2006.201.14:38:29.41#ibcon#enter sib2, iclass 37, count 2 2006.201.14:38:29.41#ibcon#flushed, iclass 37, count 2 2006.201.14:38:29.41#ibcon#about to write, iclass 37, count 2 2006.201.14:38:29.41#ibcon#wrote, iclass 37, count 2 2006.201.14:38:29.41#ibcon#about to read 3, iclass 37, count 2 2006.201.14:38:29.44#ibcon#read 3, iclass 37, count 2 2006.201.14:38:29.44#ibcon#about to read 4, iclass 37, count 2 2006.201.14:38:29.44#ibcon#read 4, iclass 37, count 2 2006.201.14:38:29.44#ibcon#about to read 5, iclass 37, count 2 2006.201.14:38:29.44#ibcon#read 5, iclass 37, count 2 2006.201.14:38:29.44#ibcon#about to read 6, iclass 37, count 2 2006.201.14:38:29.44#ibcon#read 6, iclass 37, count 2 2006.201.14:38:29.44#ibcon#end of sib2, iclass 37, count 2 2006.201.14:38:29.44#ibcon#*after write, iclass 37, count 2 2006.201.14:38:29.44#ibcon#*before return 0, iclass 37, count 2 2006.201.14:38:29.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:38:29.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:38:29.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.14:38:29.44#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:29.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:38:29.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:38:29.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:38:29.56#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:38:29.56#ibcon#first serial, iclass 37, count 0 2006.201.14:38:29.56#ibcon#enter sib2, iclass 37, count 0 2006.201.14:38:29.56#ibcon#flushed, iclass 37, count 0 2006.201.14:38:29.56#ibcon#about to write, iclass 37, count 0 2006.201.14:38:29.56#ibcon#wrote, iclass 37, count 0 2006.201.14:38:29.56#ibcon#about to read 3, iclass 37, count 0 2006.201.14:38:29.58#ibcon#read 3, iclass 37, count 0 2006.201.14:38:29.58#ibcon#about to read 4, iclass 37, count 0 2006.201.14:38:29.58#ibcon#read 4, iclass 37, count 0 2006.201.14:38:29.58#ibcon#about to read 5, iclass 37, count 0 2006.201.14:38:29.58#ibcon#read 5, iclass 37, count 0 2006.201.14:38:29.58#ibcon#about to read 6, iclass 37, count 0 2006.201.14:38:29.58#ibcon#read 6, iclass 37, count 0 2006.201.14:38:29.58#ibcon#end of sib2, iclass 37, count 0 2006.201.14:38:29.58#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:38:29.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:38:29.58#ibcon#[25=USB\r\n] 2006.201.14:38:29.58#ibcon#*before write, iclass 37, count 0 2006.201.14:38:29.58#ibcon#enter sib2, iclass 37, count 0 2006.201.14:38:29.58#ibcon#flushed, iclass 37, count 0 2006.201.14:38:29.58#ibcon#about to write, iclass 37, count 0 2006.201.14:38:29.58#ibcon#wrote, iclass 37, count 0 2006.201.14:38:29.58#ibcon#about to read 3, iclass 37, count 0 2006.201.14:38:29.61#ibcon#read 3, iclass 37, count 0 2006.201.14:38:29.61#ibcon#about to read 4, iclass 37, count 0 2006.201.14:38:29.61#ibcon#read 4, iclass 37, count 0 2006.201.14:38:29.61#ibcon#about to read 5, iclass 37, count 0 2006.201.14:38:29.61#ibcon#read 5, iclass 37, count 0 2006.201.14:38:29.61#ibcon#about to read 6, iclass 37, count 0 2006.201.14:38:29.61#ibcon#read 6, iclass 37, count 0 2006.201.14:38:29.61#ibcon#end of sib2, iclass 37, count 0 2006.201.14:38:29.61#ibcon#*after write, iclass 37, count 0 2006.201.14:38:29.61#ibcon#*before return 0, iclass 37, count 0 2006.201.14:38:29.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:38:29.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:38:29.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:38:29.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:38:29.61$vck44/vblo=1,629.99 2006.201.14:38:29.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.14:38:29.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.14:38:29.61#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:29.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:38:29.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:38:29.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:38:29.61#ibcon#enter wrdev, iclass 39, count 0 2006.201.14:38:29.61#ibcon#first serial, iclass 39, count 0 2006.201.14:38:29.61#ibcon#enter sib2, iclass 39, count 0 2006.201.14:38:29.61#ibcon#flushed, iclass 39, count 0 2006.201.14:38:29.61#ibcon#about to write, iclass 39, count 0 2006.201.14:38:29.61#ibcon#wrote, iclass 39, count 0 2006.201.14:38:29.61#ibcon#about to read 3, iclass 39, count 0 2006.201.14:38:29.63#ibcon#read 3, iclass 39, count 0 2006.201.14:38:29.63#ibcon#about to read 4, iclass 39, count 0 2006.201.14:38:29.63#ibcon#read 4, iclass 39, count 0 2006.201.14:38:29.63#ibcon#about to read 5, iclass 39, count 0 2006.201.14:38:29.63#ibcon#read 5, iclass 39, count 0 2006.201.14:38:29.63#ibcon#about to read 6, iclass 39, count 0 2006.201.14:38:29.63#ibcon#read 6, iclass 39, count 0 2006.201.14:38:29.63#ibcon#end of sib2, iclass 39, count 0 2006.201.14:38:29.63#ibcon#*mode == 0, iclass 39, count 0 2006.201.14:38:29.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.14:38:29.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:38:29.63#ibcon#*before write, iclass 39, count 0 2006.201.14:38:29.63#ibcon#enter sib2, iclass 39, count 0 2006.201.14:38:29.63#ibcon#flushed, iclass 39, count 0 2006.201.14:38:29.63#ibcon#about to write, iclass 39, count 0 2006.201.14:38:29.63#ibcon#wrote, iclass 39, count 0 2006.201.14:38:29.63#ibcon#about to read 3, iclass 39, count 0 2006.201.14:38:29.67#ibcon#read 3, iclass 39, count 0 2006.201.14:38:29.67#ibcon#about to read 4, iclass 39, count 0 2006.201.14:38:29.67#ibcon#read 4, iclass 39, count 0 2006.201.14:38:29.67#ibcon#about to read 5, iclass 39, count 0 2006.201.14:38:29.67#ibcon#read 5, iclass 39, count 0 2006.201.14:38:29.67#ibcon#about to read 6, iclass 39, count 0 2006.201.14:38:29.67#ibcon#read 6, iclass 39, count 0 2006.201.14:38:29.67#ibcon#end of sib2, iclass 39, count 0 2006.201.14:38:29.67#ibcon#*after write, iclass 39, count 0 2006.201.14:38:29.67#ibcon#*before return 0, iclass 39, count 0 2006.201.14:38:29.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:38:29.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:38:29.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.14:38:29.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.14:38:29.67$vck44/vb=1,4 2006.201.14:38:29.67#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.14:38:29.67#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.14:38:29.67#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:29.67#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:38:29.67#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:38:29.67#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:38:29.67#ibcon#enter wrdev, iclass 2, count 2 2006.201.14:38:29.67#ibcon#first serial, iclass 2, count 2 2006.201.14:38:29.67#ibcon#enter sib2, iclass 2, count 2 2006.201.14:38:29.67#ibcon#flushed, iclass 2, count 2 2006.201.14:38:29.67#ibcon#about to write, iclass 2, count 2 2006.201.14:38:29.67#ibcon#wrote, iclass 2, count 2 2006.201.14:38:29.67#ibcon#about to read 3, iclass 2, count 2 2006.201.14:38:29.69#ibcon#read 3, iclass 2, count 2 2006.201.14:38:29.69#ibcon#about to read 4, iclass 2, count 2 2006.201.14:38:29.69#ibcon#read 4, iclass 2, count 2 2006.201.14:38:29.69#ibcon#about to read 5, iclass 2, count 2 2006.201.14:38:29.69#ibcon#read 5, iclass 2, count 2 2006.201.14:38:29.69#ibcon#about to read 6, iclass 2, count 2 2006.201.14:38:29.69#ibcon#read 6, iclass 2, count 2 2006.201.14:38:29.69#ibcon#end of sib2, iclass 2, count 2 2006.201.14:38:29.69#ibcon#*mode == 0, iclass 2, count 2 2006.201.14:38:29.69#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.14:38:29.69#ibcon#[27=AT01-04\r\n] 2006.201.14:38:29.69#ibcon#*before write, iclass 2, count 2 2006.201.14:38:29.69#ibcon#enter sib2, iclass 2, count 2 2006.201.14:38:29.69#ibcon#flushed, iclass 2, count 2 2006.201.14:38:29.69#ibcon#about to write, iclass 2, count 2 2006.201.14:38:29.69#ibcon#wrote, iclass 2, count 2 2006.201.14:38:29.69#ibcon#about to read 3, iclass 2, count 2 2006.201.14:38:29.72#ibcon#read 3, iclass 2, count 2 2006.201.14:38:29.72#ibcon#about to read 4, iclass 2, count 2 2006.201.14:38:29.72#ibcon#read 4, iclass 2, count 2 2006.201.14:38:29.72#ibcon#about to read 5, iclass 2, count 2 2006.201.14:38:29.72#ibcon#read 5, iclass 2, count 2 2006.201.14:38:29.72#ibcon#about to read 6, iclass 2, count 2 2006.201.14:38:29.72#ibcon#read 6, iclass 2, count 2 2006.201.14:38:29.72#ibcon#end of sib2, iclass 2, count 2 2006.201.14:38:29.72#ibcon#*after write, iclass 2, count 2 2006.201.14:38:29.72#ibcon#*before return 0, iclass 2, count 2 2006.201.14:38:29.72#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:38:29.72#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:38:29.72#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.14:38:29.72#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:29.72#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:38:29.84#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:38:29.84#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:38:29.84#ibcon#enter wrdev, iclass 2, count 0 2006.201.14:38:29.84#ibcon#first serial, iclass 2, count 0 2006.201.14:38:29.84#ibcon#enter sib2, iclass 2, count 0 2006.201.14:38:29.84#ibcon#flushed, iclass 2, count 0 2006.201.14:38:29.84#ibcon#about to write, iclass 2, count 0 2006.201.14:38:29.84#ibcon#wrote, iclass 2, count 0 2006.201.14:38:29.84#ibcon#about to read 3, iclass 2, count 0 2006.201.14:38:29.86#ibcon#read 3, iclass 2, count 0 2006.201.14:38:29.86#ibcon#about to read 4, iclass 2, count 0 2006.201.14:38:29.86#ibcon#read 4, iclass 2, count 0 2006.201.14:38:29.86#ibcon#about to read 5, iclass 2, count 0 2006.201.14:38:29.86#ibcon#read 5, iclass 2, count 0 2006.201.14:38:29.86#ibcon#about to read 6, iclass 2, count 0 2006.201.14:38:29.86#ibcon#read 6, iclass 2, count 0 2006.201.14:38:29.86#ibcon#end of sib2, iclass 2, count 0 2006.201.14:38:29.86#ibcon#*mode == 0, iclass 2, count 0 2006.201.14:38:29.86#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.14:38:29.86#ibcon#[27=USB\r\n] 2006.201.14:38:29.86#ibcon#*before write, iclass 2, count 0 2006.201.14:38:29.86#ibcon#enter sib2, iclass 2, count 0 2006.201.14:38:29.86#ibcon#flushed, iclass 2, count 0 2006.201.14:38:29.86#ibcon#about to write, iclass 2, count 0 2006.201.14:38:29.86#ibcon#wrote, iclass 2, count 0 2006.201.14:38:29.86#ibcon#about to read 3, iclass 2, count 0 2006.201.14:38:29.89#ibcon#read 3, iclass 2, count 0 2006.201.14:38:29.89#ibcon#about to read 4, iclass 2, count 0 2006.201.14:38:29.89#ibcon#read 4, iclass 2, count 0 2006.201.14:38:29.89#ibcon#about to read 5, iclass 2, count 0 2006.201.14:38:29.89#ibcon#read 5, iclass 2, count 0 2006.201.14:38:29.89#ibcon#about to read 6, iclass 2, count 0 2006.201.14:38:29.89#ibcon#read 6, iclass 2, count 0 2006.201.14:38:29.89#ibcon#end of sib2, iclass 2, count 0 2006.201.14:38:29.89#ibcon#*after write, iclass 2, count 0 2006.201.14:38:29.89#ibcon#*before return 0, iclass 2, count 0 2006.201.14:38:29.89#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:38:29.89#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:38:29.89#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.14:38:29.89#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.14:38:29.89$vck44/vblo=2,634.99 2006.201.14:38:29.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.14:38:29.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.14:38:29.89#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:29.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:29.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:29.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:29.89#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:38:29.89#ibcon#first serial, iclass 5, count 0 2006.201.14:38:29.89#ibcon#enter sib2, iclass 5, count 0 2006.201.14:38:29.89#ibcon#flushed, iclass 5, count 0 2006.201.14:38:29.89#ibcon#about to write, iclass 5, count 0 2006.201.14:38:29.89#ibcon#wrote, iclass 5, count 0 2006.201.14:38:29.89#ibcon#about to read 3, iclass 5, count 0 2006.201.14:38:29.91#ibcon#read 3, iclass 5, count 0 2006.201.14:38:29.91#ibcon#about to read 4, iclass 5, count 0 2006.201.14:38:29.91#ibcon#read 4, iclass 5, count 0 2006.201.14:38:29.91#ibcon#about to read 5, iclass 5, count 0 2006.201.14:38:29.91#ibcon#read 5, iclass 5, count 0 2006.201.14:38:29.91#ibcon#about to read 6, iclass 5, count 0 2006.201.14:38:29.91#ibcon#read 6, iclass 5, count 0 2006.201.14:38:29.91#ibcon#end of sib2, iclass 5, count 0 2006.201.14:38:29.91#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:38:29.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:38:29.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:38:29.91#ibcon#*before write, iclass 5, count 0 2006.201.14:38:29.91#ibcon#enter sib2, iclass 5, count 0 2006.201.14:38:29.91#ibcon#flushed, iclass 5, count 0 2006.201.14:38:29.91#ibcon#about to write, iclass 5, count 0 2006.201.14:38:29.91#ibcon#wrote, iclass 5, count 0 2006.201.14:38:29.91#ibcon#about to read 3, iclass 5, count 0 2006.201.14:38:29.95#ibcon#read 3, iclass 5, count 0 2006.201.14:38:29.95#ibcon#about to read 4, iclass 5, count 0 2006.201.14:38:29.95#ibcon#read 4, iclass 5, count 0 2006.201.14:38:29.95#ibcon#about to read 5, iclass 5, count 0 2006.201.14:38:29.95#ibcon#read 5, iclass 5, count 0 2006.201.14:38:29.95#ibcon#about to read 6, iclass 5, count 0 2006.201.14:38:29.95#ibcon#read 6, iclass 5, count 0 2006.201.14:38:29.95#ibcon#end of sib2, iclass 5, count 0 2006.201.14:38:29.95#ibcon#*after write, iclass 5, count 0 2006.201.14:38:29.95#ibcon#*before return 0, iclass 5, count 0 2006.201.14:38:29.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:29.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:38:29.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:38:29.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:38:29.95$vck44/vb=2,5 2006.201.14:38:29.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.14:38:29.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.14:38:29.95#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:29.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:30.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:30.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:30.01#ibcon#enter wrdev, iclass 7, count 2 2006.201.14:38:30.01#ibcon#first serial, iclass 7, count 2 2006.201.14:38:30.01#ibcon#enter sib2, iclass 7, count 2 2006.201.14:38:30.01#ibcon#flushed, iclass 7, count 2 2006.201.14:38:30.01#ibcon#about to write, iclass 7, count 2 2006.201.14:38:30.01#ibcon#wrote, iclass 7, count 2 2006.201.14:38:30.01#ibcon#about to read 3, iclass 7, count 2 2006.201.14:38:30.03#ibcon#read 3, iclass 7, count 2 2006.201.14:38:30.03#ibcon#about to read 4, iclass 7, count 2 2006.201.14:38:30.03#ibcon#read 4, iclass 7, count 2 2006.201.14:38:30.03#ibcon#about to read 5, iclass 7, count 2 2006.201.14:38:30.03#ibcon#read 5, iclass 7, count 2 2006.201.14:38:30.03#ibcon#about to read 6, iclass 7, count 2 2006.201.14:38:30.03#ibcon#read 6, iclass 7, count 2 2006.201.14:38:30.03#ibcon#end of sib2, iclass 7, count 2 2006.201.14:38:30.03#ibcon#*mode == 0, iclass 7, count 2 2006.201.14:38:30.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.14:38:30.03#ibcon#[27=AT02-05\r\n] 2006.201.14:38:30.03#ibcon#*before write, iclass 7, count 2 2006.201.14:38:30.03#ibcon#enter sib2, iclass 7, count 2 2006.201.14:38:30.03#ibcon#flushed, iclass 7, count 2 2006.201.14:38:30.03#ibcon#about to write, iclass 7, count 2 2006.201.14:38:30.03#ibcon#wrote, iclass 7, count 2 2006.201.14:38:30.03#ibcon#about to read 3, iclass 7, count 2 2006.201.14:38:30.06#ibcon#read 3, iclass 7, count 2 2006.201.14:38:30.06#ibcon#about to read 4, iclass 7, count 2 2006.201.14:38:30.06#ibcon#read 4, iclass 7, count 2 2006.201.14:38:30.06#ibcon#about to read 5, iclass 7, count 2 2006.201.14:38:30.06#ibcon#read 5, iclass 7, count 2 2006.201.14:38:30.06#ibcon#about to read 6, iclass 7, count 2 2006.201.14:38:30.06#ibcon#read 6, iclass 7, count 2 2006.201.14:38:30.06#ibcon#end of sib2, iclass 7, count 2 2006.201.14:38:30.06#ibcon#*after write, iclass 7, count 2 2006.201.14:38:30.06#ibcon#*before return 0, iclass 7, count 2 2006.201.14:38:30.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:30.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:38:30.06#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.14:38:30.06#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:30.06#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:30.18#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:30.18#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:30.18#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:38:30.18#ibcon#first serial, iclass 7, count 0 2006.201.14:38:30.18#ibcon#enter sib2, iclass 7, count 0 2006.201.14:38:30.18#ibcon#flushed, iclass 7, count 0 2006.201.14:38:30.18#ibcon#about to write, iclass 7, count 0 2006.201.14:38:30.18#ibcon#wrote, iclass 7, count 0 2006.201.14:38:30.18#ibcon#about to read 3, iclass 7, count 0 2006.201.14:38:30.20#ibcon#read 3, iclass 7, count 0 2006.201.14:38:30.20#ibcon#about to read 4, iclass 7, count 0 2006.201.14:38:30.20#ibcon#read 4, iclass 7, count 0 2006.201.14:38:30.20#ibcon#about to read 5, iclass 7, count 0 2006.201.14:38:30.20#ibcon#read 5, iclass 7, count 0 2006.201.14:38:30.20#ibcon#about to read 6, iclass 7, count 0 2006.201.14:38:30.20#ibcon#read 6, iclass 7, count 0 2006.201.14:38:30.20#ibcon#end of sib2, iclass 7, count 0 2006.201.14:38:30.20#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:38:30.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:38:30.20#ibcon#[27=USB\r\n] 2006.201.14:38:30.20#ibcon#*before write, iclass 7, count 0 2006.201.14:38:30.20#ibcon#enter sib2, iclass 7, count 0 2006.201.14:38:30.20#ibcon#flushed, iclass 7, count 0 2006.201.14:38:30.20#ibcon#about to write, iclass 7, count 0 2006.201.14:38:30.20#ibcon#wrote, iclass 7, count 0 2006.201.14:38:30.20#ibcon#about to read 3, iclass 7, count 0 2006.201.14:38:30.23#ibcon#read 3, iclass 7, count 0 2006.201.14:38:30.23#ibcon#about to read 4, iclass 7, count 0 2006.201.14:38:30.23#ibcon#read 4, iclass 7, count 0 2006.201.14:38:30.23#ibcon#about to read 5, iclass 7, count 0 2006.201.14:38:30.23#ibcon#read 5, iclass 7, count 0 2006.201.14:38:30.23#ibcon#about to read 6, iclass 7, count 0 2006.201.14:38:30.23#ibcon#read 6, iclass 7, count 0 2006.201.14:38:30.23#ibcon#end of sib2, iclass 7, count 0 2006.201.14:38:30.23#ibcon#*after write, iclass 7, count 0 2006.201.14:38:30.23#ibcon#*before return 0, iclass 7, count 0 2006.201.14:38:30.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:30.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:38:30.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:38:30.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:38:30.23$vck44/vblo=3,649.99 2006.201.14:38:30.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.14:38:30.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.14:38:30.23#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:30.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:30.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:30.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:30.23#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:38:30.23#ibcon#first serial, iclass 11, count 0 2006.201.14:38:30.23#ibcon#enter sib2, iclass 11, count 0 2006.201.14:38:30.23#ibcon#flushed, iclass 11, count 0 2006.201.14:38:30.23#ibcon#about to write, iclass 11, count 0 2006.201.14:38:30.23#ibcon#wrote, iclass 11, count 0 2006.201.14:38:30.23#ibcon#about to read 3, iclass 11, count 0 2006.201.14:38:30.25#ibcon#read 3, iclass 11, count 0 2006.201.14:38:30.25#ibcon#about to read 4, iclass 11, count 0 2006.201.14:38:30.25#ibcon#read 4, iclass 11, count 0 2006.201.14:38:30.25#ibcon#about to read 5, iclass 11, count 0 2006.201.14:38:30.25#ibcon#read 5, iclass 11, count 0 2006.201.14:38:30.25#ibcon#about to read 6, iclass 11, count 0 2006.201.14:38:30.25#ibcon#read 6, iclass 11, count 0 2006.201.14:38:30.25#ibcon#end of sib2, iclass 11, count 0 2006.201.14:38:30.25#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:38:30.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:38:30.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:38:30.25#ibcon#*before write, iclass 11, count 0 2006.201.14:38:30.25#ibcon#enter sib2, iclass 11, count 0 2006.201.14:38:30.25#ibcon#flushed, iclass 11, count 0 2006.201.14:38:30.25#ibcon#about to write, iclass 11, count 0 2006.201.14:38:30.25#ibcon#wrote, iclass 11, count 0 2006.201.14:38:30.25#ibcon#about to read 3, iclass 11, count 0 2006.201.14:38:30.29#ibcon#read 3, iclass 11, count 0 2006.201.14:38:30.29#ibcon#about to read 4, iclass 11, count 0 2006.201.14:38:30.29#ibcon#read 4, iclass 11, count 0 2006.201.14:38:30.29#ibcon#about to read 5, iclass 11, count 0 2006.201.14:38:30.29#ibcon#read 5, iclass 11, count 0 2006.201.14:38:30.29#ibcon#about to read 6, iclass 11, count 0 2006.201.14:38:30.29#ibcon#read 6, iclass 11, count 0 2006.201.14:38:30.29#ibcon#end of sib2, iclass 11, count 0 2006.201.14:38:30.29#ibcon#*after write, iclass 11, count 0 2006.201.14:38:30.29#ibcon#*before return 0, iclass 11, count 0 2006.201.14:38:30.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:30.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:38:30.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:38:30.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:38:30.29$vck44/vb=3,4 2006.201.14:38:30.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.14:38:30.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.14:38:30.29#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:30.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:30.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:30.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:30.35#ibcon#enter wrdev, iclass 13, count 2 2006.201.14:38:30.35#ibcon#first serial, iclass 13, count 2 2006.201.14:38:30.35#ibcon#enter sib2, iclass 13, count 2 2006.201.14:38:30.35#ibcon#flushed, iclass 13, count 2 2006.201.14:38:30.35#ibcon#about to write, iclass 13, count 2 2006.201.14:38:30.35#ibcon#wrote, iclass 13, count 2 2006.201.14:38:30.35#ibcon#about to read 3, iclass 13, count 2 2006.201.14:38:30.37#ibcon#read 3, iclass 13, count 2 2006.201.14:38:30.37#ibcon#about to read 4, iclass 13, count 2 2006.201.14:38:30.37#ibcon#read 4, iclass 13, count 2 2006.201.14:38:30.37#ibcon#about to read 5, iclass 13, count 2 2006.201.14:38:30.37#ibcon#read 5, iclass 13, count 2 2006.201.14:38:30.37#ibcon#about to read 6, iclass 13, count 2 2006.201.14:38:30.37#ibcon#read 6, iclass 13, count 2 2006.201.14:38:30.37#ibcon#end of sib2, iclass 13, count 2 2006.201.14:38:30.37#ibcon#*mode == 0, iclass 13, count 2 2006.201.14:38:30.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.14:38:30.37#ibcon#[27=AT03-04\r\n] 2006.201.14:38:30.37#ibcon#*before write, iclass 13, count 2 2006.201.14:38:30.37#ibcon#enter sib2, iclass 13, count 2 2006.201.14:38:30.37#ibcon#flushed, iclass 13, count 2 2006.201.14:38:30.37#ibcon#about to write, iclass 13, count 2 2006.201.14:38:30.37#ibcon#wrote, iclass 13, count 2 2006.201.14:38:30.37#ibcon#about to read 3, iclass 13, count 2 2006.201.14:38:30.40#ibcon#read 3, iclass 13, count 2 2006.201.14:38:30.40#ibcon#about to read 4, iclass 13, count 2 2006.201.14:38:30.40#ibcon#read 4, iclass 13, count 2 2006.201.14:38:30.40#ibcon#about to read 5, iclass 13, count 2 2006.201.14:38:30.40#ibcon#read 5, iclass 13, count 2 2006.201.14:38:30.40#ibcon#about to read 6, iclass 13, count 2 2006.201.14:38:30.40#ibcon#read 6, iclass 13, count 2 2006.201.14:38:30.40#ibcon#end of sib2, iclass 13, count 2 2006.201.14:38:30.40#ibcon#*after write, iclass 13, count 2 2006.201.14:38:30.40#ibcon#*before return 0, iclass 13, count 2 2006.201.14:38:30.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:30.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:38:30.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.14:38:30.40#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:30.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:30.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:30.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:30.52#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:38:30.52#ibcon#first serial, iclass 13, count 0 2006.201.14:38:30.52#ibcon#enter sib2, iclass 13, count 0 2006.201.14:38:30.52#ibcon#flushed, iclass 13, count 0 2006.201.14:38:30.52#ibcon#about to write, iclass 13, count 0 2006.201.14:38:30.52#ibcon#wrote, iclass 13, count 0 2006.201.14:38:30.52#ibcon#about to read 3, iclass 13, count 0 2006.201.14:38:30.54#ibcon#read 3, iclass 13, count 0 2006.201.14:38:30.54#ibcon#about to read 4, iclass 13, count 0 2006.201.14:38:30.54#ibcon#read 4, iclass 13, count 0 2006.201.14:38:30.54#ibcon#about to read 5, iclass 13, count 0 2006.201.14:38:30.54#ibcon#read 5, iclass 13, count 0 2006.201.14:38:30.54#ibcon#about to read 6, iclass 13, count 0 2006.201.14:38:30.54#ibcon#read 6, iclass 13, count 0 2006.201.14:38:30.54#ibcon#end of sib2, iclass 13, count 0 2006.201.14:38:30.54#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:38:30.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:38:30.54#ibcon#[27=USB\r\n] 2006.201.14:38:30.54#ibcon#*before write, iclass 13, count 0 2006.201.14:38:30.54#ibcon#enter sib2, iclass 13, count 0 2006.201.14:38:30.54#ibcon#flushed, iclass 13, count 0 2006.201.14:38:30.54#ibcon#about to write, iclass 13, count 0 2006.201.14:38:30.54#ibcon#wrote, iclass 13, count 0 2006.201.14:38:30.54#ibcon#about to read 3, iclass 13, count 0 2006.201.14:38:30.57#ibcon#read 3, iclass 13, count 0 2006.201.14:38:30.57#ibcon#about to read 4, iclass 13, count 0 2006.201.14:38:30.57#ibcon#read 4, iclass 13, count 0 2006.201.14:38:30.57#ibcon#about to read 5, iclass 13, count 0 2006.201.14:38:30.57#ibcon#read 5, iclass 13, count 0 2006.201.14:38:30.57#ibcon#about to read 6, iclass 13, count 0 2006.201.14:38:30.57#ibcon#read 6, iclass 13, count 0 2006.201.14:38:30.57#ibcon#end of sib2, iclass 13, count 0 2006.201.14:38:30.57#ibcon#*after write, iclass 13, count 0 2006.201.14:38:30.57#ibcon#*before return 0, iclass 13, count 0 2006.201.14:38:30.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:30.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:38:30.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:38:30.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:38:30.57$vck44/vblo=4,679.99 2006.201.14:38:30.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.14:38:30.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.14:38:30.57#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:30.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:30.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:30.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:30.57#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:38:30.57#ibcon#first serial, iclass 15, count 0 2006.201.14:38:30.57#ibcon#enter sib2, iclass 15, count 0 2006.201.14:38:30.57#ibcon#flushed, iclass 15, count 0 2006.201.14:38:30.57#ibcon#about to write, iclass 15, count 0 2006.201.14:38:30.57#ibcon#wrote, iclass 15, count 0 2006.201.14:38:30.57#ibcon#about to read 3, iclass 15, count 0 2006.201.14:38:30.59#ibcon#read 3, iclass 15, count 0 2006.201.14:38:30.59#ibcon#about to read 4, iclass 15, count 0 2006.201.14:38:30.59#ibcon#read 4, iclass 15, count 0 2006.201.14:38:30.59#ibcon#about to read 5, iclass 15, count 0 2006.201.14:38:30.59#ibcon#read 5, iclass 15, count 0 2006.201.14:38:30.59#ibcon#about to read 6, iclass 15, count 0 2006.201.14:38:30.59#ibcon#read 6, iclass 15, count 0 2006.201.14:38:30.59#ibcon#end of sib2, iclass 15, count 0 2006.201.14:38:30.59#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:38:30.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:38:30.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:38:30.59#ibcon#*before write, iclass 15, count 0 2006.201.14:38:30.59#ibcon#enter sib2, iclass 15, count 0 2006.201.14:38:30.59#ibcon#flushed, iclass 15, count 0 2006.201.14:38:30.59#ibcon#about to write, iclass 15, count 0 2006.201.14:38:30.59#ibcon#wrote, iclass 15, count 0 2006.201.14:38:30.59#ibcon#about to read 3, iclass 15, count 0 2006.201.14:38:30.64#ibcon#read 3, iclass 15, count 0 2006.201.14:38:30.64#ibcon#about to read 4, iclass 15, count 0 2006.201.14:38:30.64#ibcon#read 4, iclass 15, count 0 2006.201.14:38:30.64#ibcon#about to read 5, iclass 15, count 0 2006.201.14:38:30.64#ibcon#read 5, iclass 15, count 0 2006.201.14:38:30.64#ibcon#about to read 6, iclass 15, count 0 2006.201.14:38:30.64#ibcon#read 6, iclass 15, count 0 2006.201.14:38:30.64#ibcon#end of sib2, iclass 15, count 0 2006.201.14:38:30.64#ibcon#*after write, iclass 15, count 0 2006.201.14:38:30.64#ibcon#*before return 0, iclass 15, count 0 2006.201.14:38:30.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:30.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:38:30.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:38:30.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:38:30.64$vck44/vb=4,5 2006.201.14:38:30.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.14:38:30.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.14:38:30.64#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:30.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:30.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:30.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:30.69#ibcon#enter wrdev, iclass 17, count 2 2006.201.14:38:30.69#ibcon#first serial, iclass 17, count 2 2006.201.14:38:30.69#ibcon#enter sib2, iclass 17, count 2 2006.201.14:38:30.69#ibcon#flushed, iclass 17, count 2 2006.201.14:38:30.69#ibcon#about to write, iclass 17, count 2 2006.201.14:38:30.69#ibcon#wrote, iclass 17, count 2 2006.201.14:38:30.69#ibcon#about to read 3, iclass 17, count 2 2006.201.14:38:30.71#ibcon#read 3, iclass 17, count 2 2006.201.14:38:30.71#ibcon#about to read 4, iclass 17, count 2 2006.201.14:38:30.71#ibcon#read 4, iclass 17, count 2 2006.201.14:38:30.71#ibcon#about to read 5, iclass 17, count 2 2006.201.14:38:30.71#ibcon#read 5, iclass 17, count 2 2006.201.14:38:30.71#ibcon#about to read 6, iclass 17, count 2 2006.201.14:38:30.71#ibcon#read 6, iclass 17, count 2 2006.201.14:38:30.71#ibcon#end of sib2, iclass 17, count 2 2006.201.14:38:30.71#ibcon#*mode == 0, iclass 17, count 2 2006.201.14:38:30.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.14:38:30.71#ibcon#[27=AT04-05\r\n] 2006.201.14:38:30.71#ibcon#*before write, iclass 17, count 2 2006.201.14:38:30.71#ibcon#enter sib2, iclass 17, count 2 2006.201.14:38:30.71#ibcon#flushed, iclass 17, count 2 2006.201.14:38:30.71#ibcon#about to write, iclass 17, count 2 2006.201.14:38:30.71#ibcon#wrote, iclass 17, count 2 2006.201.14:38:30.71#ibcon#about to read 3, iclass 17, count 2 2006.201.14:38:30.74#ibcon#read 3, iclass 17, count 2 2006.201.14:38:30.74#ibcon#about to read 4, iclass 17, count 2 2006.201.14:38:30.74#ibcon#read 4, iclass 17, count 2 2006.201.14:38:30.74#ibcon#about to read 5, iclass 17, count 2 2006.201.14:38:30.74#ibcon#read 5, iclass 17, count 2 2006.201.14:38:30.74#ibcon#about to read 6, iclass 17, count 2 2006.201.14:38:30.74#ibcon#read 6, iclass 17, count 2 2006.201.14:38:30.74#ibcon#end of sib2, iclass 17, count 2 2006.201.14:38:30.74#ibcon#*after write, iclass 17, count 2 2006.201.14:38:30.74#ibcon#*before return 0, iclass 17, count 2 2006.201.14:38:30.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:30.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:38:30.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.14:38:30.74#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:30.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:30.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:30.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:30.86#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:38:30.86#ibcon#first serial, iclass 17, count 0 2006.201.14:38:30.86#ibcon#enter sib2, iclass 17, count 0 2006.201.14:38:30.86#ibcon#flushed, iclass 17, count 0 2006.201.14:38:30.86#ibcon#about to write, iclass 17, count 0 2006.201.14:38:30.86#ibcon#wrote, iclass 17, count 0 2006.201.14:38:30.86#ibcon#about to read 3, iclass 17, count 0 2006.201.14:38:30.88#ibcon#read 3, iclass 17, count 0 2006.201.14:38:30.88#ibcon#about to read 4, iclass 17, count 0 2006.201.14:38:30.88#ibcon#read 4, iclass 17, count 0 2006.201.14:38:30.88#ibcon#about to read 5, iclass 17, count 0 2006.201.14:38:30.88#ibcon#read 5, iclass 17, count 0 2006.201.14:38:30.88#ibcon#about to read 6, iclass 17, count 0 2006.201.14:38:30.88#ibcon#read 6, iclass 17, count 0 2006.201.14:38:30.88#ibcon#end of sib2, iclass 17, count 0 2006.201.14:38:30.88#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:38:30.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:38:30.88#ibcon#[27=USB\r\n] 2006.201.14:38:30.88#ibcon#*before write, iclass 17, count 0 2006.201.14:38:30.88#ibcon#enter sib2, iclass 17, count 0 2006.201.14:38:30.88#ibcon#flushed, iclass 17, count 0 2006.201.14:38:30.88#ibcon#about to write, iclass 17, count 0 2006.201.14:38:30.88#ibcon#wrote, iclass 17, count 0 2006.201.14:38:30.88#ibcon#about to read 3, iclass 17, count 0 2006.201.14:38:30.91#ibcon#read 3, iclass 17, count 0 2006.201.14:38:30.91#ibcon#about to read 4, iclass 17, count 0 2006.201.14:38:30.91#ibcon#read 4, iclass 17, count 0 2006.201.14:38:30.91#ibcon#about to read 5, iclass 17, count 0 2006.201.14:38:30.91#ibcon#read 5, iclass 17, count 0 2006.201.14:38:30.91#ibcon#about to read 6, iclass 17, count 0 2006.201.14:38:30.91#ibcon#read 6, iclass 17, count 0 2006.201.14:38:30.91#ibcon#end of sib2, iclass 17, count 0 2006.201.14:38:30.91#ibcon#*after write, iclass 17, count 0 2006.201.14:38:30.91#ibcon#*before return 0, iclass 17, count 0 2006.201.14:38:30.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:30.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:38:30.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:38:30.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:38:30.91$vck44/vblo=5,709.99 2006.201.14:38:30.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.14:38:30.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.14:38:30.91#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:30.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:30.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:30.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:30.91#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:38:30.91#ibcon#first serial, iclass 19, count 0 2006.201.14:38:30.91#ibcon#enter sib2, iclass 19, count 0 2006.201.14:38:30.91#ibcon#flushed, iclass 19, count 0 2006.201.14:38:30.91#ibcon#about to write, iclass 19, count 0 2006.201.14:38:30.91#ibcon#wrote, iclass 19, count 0 2006.201.14:38:30.91#ibcon#about to read 3, iclass 19, count 0 2006.201.14:38:30.93#ibcon#read 3, iclass 19, count 0 2006.201.14:38:30.93#ibcon#about to read 4, iclass 19, count 0 2006.201.14:38:30.93#ibcon#read 4, iclass 19, count 0 2006.201.14:38:30.93#ibcon#about to read 5, iclass 19, count 0 2006.201.14:38:30.93#ibcon#read 5, iclass 19, count 0 2006.201.14:38:30.93#ibcon#about to read 6, iclass 19, count 0 2006.201.14:38:30.93#ibcon#read 6, iclass 19, count 0 2006.201.14:38:30.93#ibcon#end of sib2, iclass 19, count 0 2006.201.14:38:30.93#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:38:30.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:38:30.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:38:30.93#ibcon#*before write, iclass 19, count 0 2006.201.14:38:30.93#ibcon#enter sib2, iclass 19, count 0 2006.201.14:38:30.93#ibcon#flushed, iclass 19, count 0 2006.201.14:38:30.93#ibcon#about to write, iclass 19, count 0 2006.201.14:38:30.93#ibcon#wrote, iclass 19, count 0 2006.201.14:38:30.93#ibcon#about to read 3, iclass 19, count 0 2006.201.14:38:30.97#ibcon#read 3, iclass 19, count 0 2006.201.14:38:30.97#ibcon#about to read 4, iclass 19, count 0 2006.201.14:38:30.97#ibcon#read 4, iclass 19, count 0 2006.201.14:38:30.97#ibcon#about to read 5, iclass 19, count 0 2006.201.14:38:30.97#ibcon#read 5, iclass 19, count 0 2006.201.14:38:30.97#ibcon#about to read 6, iclass 19, count 0 2006.201.14:38:30.97#ibcon#read 6, iclass 19, count 0 2006.201.14:38:30.97#ibcon#end of sib2, iclass 19, count 0 2006.201.14:38:30.97#ibcon#*after write, iclass 19, count 0 2006.201.14:38:30.97#ibcon#*before return 0, iclass 19, count 0 2006.201.14:38:30.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:30.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:38:30.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:38:30.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:38:30.97$vck44/vb=5,4 2006.201.14:38:30.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.14:38:30.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.14:38:30.97#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:30.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:31.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:31.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:31.03#ibcon#enter wrdev, iclass 21, count 2 2006.201.14:38:31.03#ibcon#first serial, iclass 21, count 2 2006.201.14:38:31.03#ibcon#enter sib2, iclass 21, count 2 2006.201.14:38:31.03#ibcon#flushed, iclass 21, count 2 2006.201.14:38:31.03#ibcon#about to write, iclass 21, count 2 2006.201.14:38:31.03#ibcon#wrote, iclass 21, count 2 2006.201.14:38:31.03#ibcon#about to read 3, iclass 21, count 2 2006.201.14:38:31.05#ibcon#read 3, iclass 21, count 2 2006.201.14:38:31.05#ibcon#about to read 4, iclass 21, count 2 2006.201.14:38:31.05#ibcon#read 4, iclass 21, count 2 2006.201.14:38:31.05#ibcon#about to read 5, iclass 21, count 2 2006.201.14:38:31.05#ibcon#read 5, iclass 21, count 2 2006.201.14:38:31.05#ibcon#about to read 6, iclass 21, count 2 2006.201.14:38:31.05#ibcon#read 6, iclass 21, count 2 2006.201.14:38:31.05#ibcon#end of sib2, iclass 21, count 2 2006.201.14:38:31.05#ibcon#*mode == 0, iclass 21, count 2 2006.201.14:38:31.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.14:38:31.05#ibcon#[27=AT05-04\r\n] 2006.201.14:38:31.05#ibcon#*before write, iclass 21, count 2 2006.201.14:38:31.05#ibcon#enter sib2, iclass 21, count 2 2006.201.14:38:31.05#ibcon#flushed, iclass 21, count 2 2006.201.14:38:31.05#ibcon#about to write, iclass 21, count 2 2006.201.14:38:31.05#ibcon#wrote, iclass 21, count 2 2006.201.14:38:31.05#ibcon#about to read 3, iclass 21, count 2 2006.201.14:38:31.08#ibcon#read 3, iclass 21, count 2 2006.201.14:38:31.08#ibcon#about to read 4, iclass 21, count 2 2006.201.14:38:31.08#ibcon#read 4, iclass 21, count 2 2006.201.14:38:31.08#ibcon#about to read 5, iclass 21, count 2 2006.201.14:38:31.08#ibcon#read 5, iclass 21, count 2 2006.201.14:38:31.08#ibcon#about to read 6, iclass 21, count 2 2006.201.14:38:31.08#ibcon#read 6, iclass 21, count 2 2006.201.14:38:31.08#ibcon#end of sib2, iclass 21, count 2 2006.201.14:38:31.08#ibcon#*after write, iclass 21, count 2 2006.201.14:38:31.08#ibcon#*before return 0, iclass 21, count 2 2006.201.14:38:31.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:31.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:38:31.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.14:38:31.08#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:31.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:31.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:31.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:31.20#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:38:31.20#ibcon#first serial, iclass 21, count 0 2006.201.14:38:31.20#ibcon#enter sib2, iclass 21, count 0 2006.201.14:38:31.20#ibcon#flushed, iclass 21, count 0 2006.201.14:38:31.20#ibcon#about to write, iclass 21, count 0 2006.201.14:38:31.20#ibcon#wrote, iclass 21, count 0 2006.201.14:38:31.20#ibcon#about to read 3, iclass 21, count 0 2006.201.14:38:31.22#ibcon#read 3, iclass 21, count 0 2006.201.14:38:31.22#ibcon#about to read 4, iclass 21, count 0 2006.201.14:38:31.22#ibcon#read 4, iclass 21, count 0 2006.201.14:38:31.22#ibcon#about to read 5, iclass 21, count 0 2006.201.14:38:31.22#ibcon#read 5, iclass 21, count 0 2006.201.14:38:31.22#ibcon#about to read 6, iclass 21, count 0 2006.201.14:38:31.22#ibcon#read 6, iclass 21, count 0 2006.201.14:38:31.22#ibcon#end of sib2, iclass 21, count 0 2006.201.14:38:31.22#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:38:31.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:38:31.22#ibcon#[27=USB\r\n] 2006.201.14:38:31.22#ibcon#*before write, iclass 21, count 0 2006.201.14:38:31.22#ibcon#enter sib2, iclass 21, count 0 2006.201.14:38:31.22#ibcon#flushed, iclass 21, count 0 2006.201.14:38:31.22#ibcon#about to write, iclass 21, count 0 2006.201.14:38:31.22#ibcon#wrote, iclass 21, count 0 2006.201.14:38:31.22#ibcon#about to read 3, iclass 21, count 0 2006.201.14:38:31.25#ibcon#read 3, iclass 21, count 0 2006.201.14:38:31.25#ibcon#about to read 4, iclass 21, count 0 2006.201.14:38:31.25#ibcon#read 4, iclass 21, count 0 2006.201.14:38:31.25#ibcon#about to read 5, iclass 21, count 0 2006.201.14:38:31.25#ibcon#read 5, iclass 21, count 0 2006.201.14:38:31.25#ibcon#about to read 6, iclass 21, count 0 2006.201.14:38:31.25#ibcon#read 6, iclass 21, count 0 2006.201.14:38:31.25#ibcon#end of sib2, iclass 21, count 0 2006.201.14:38:31.25#ibcon#*after write, iclass 21, count 0 2006.201.14:38:31.25#ibcon#*before return 0, iclass 21, count 0 2006.201.14:38:31.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:31.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:38:31.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:38:31.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:38:31.25$vck44/vblo=6,719.99 2006.201.14:38:31.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.14:38:31.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.14:38:31.25#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:31.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:31.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:31.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:31.25#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:38:31.25#ibcon#first serial, iclass 23, count 0 2006.201.14:38:31.25#ibcon#enter sib2, iclass 23, count 0 2006.201.14:38:31.25#ibcon#flushed, iclass 23, count 0 2006.201.14:38:31.25#ibcon#about to write, iclass 23, count 0 2006.201.14:38:31.25#ibcon#wrote, iclass 23, count 0 2006.201.14:38:31.25#ibcon#about to read 3, iclass 23, count 0 2006.201.14:38:31.27#ibcon#read 3, iclass 23, count 0 2006.201.14:38:31.27#ibcon#about to read 4, iclass 23, count 0 2006.201.14:38:31.27#ibcon#read 4, iclass 23, count 0 2006.201.14:38:31.27#ibcon#about to read 5, iclass 23, count 0 2006.201.14:38:31.27#ibcon#read 5, iclass 23, count 0 2006.201.14:38:31.27#ibcon#about to read 6, iclass 23, count 0 2006.201.14:38:31.27#ibcon#read 6, iclass 23, count 0 2006.201.14:38:31.27#ibcon#end of sib2, iclass 23, count 0 2006.201.14:38:31.27#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:38:31.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:38:31.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:38:31.27#ibcon#*before write, iclass 23, count 0 2006.201.14:38:31.27#ibcon#enter sib2, iclass 23, count 0 2006.201.14:38:31.27#ibcon#flushed, iclass 23, count 0 2006.201.14:38:31.27#ibcon#about to write, iclass 23, count 0 2006.201.14:38:31.27#ibcon#wrote, iclass 23, count 0 2006.201.14:38:31.27#ibcon#about to read 3, iclass 23, count 0 2006.201.14:38:31.31#ibcon#read 3, iclass 23, count 0 2006.201.14:38:31.31#ibcon#about to read 4, iclass 23, count 0 2006.201.14:38:31.31#ibcon#read 4, iclass 23, count 0 2006.201.14:38:31.31#ibcon#about to read 5, iclass 23, count 0 2006.201.14:38:31.31#ibcon#read 5, iclass 23, count 0 2006.201.14:38:31.31#ibcon#about to read 6, iclass 23, count 0 2006.201.14:38:31.31#ibcon#read 6, iclass 23, count 0 2006.201.14:38:31.31#ibcon#end of sib2, iclass 23, count 0 2006.201.14:38:31.31#ibcon#*after write, iclass 23, count 0 2006.201.14:38:31.31#ibcon#*before return 0, iclass 23, count 0 2006.201.14:38:31.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:31.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:38:31.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:38:31.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:38:31.31$vck44/vb=6,4 2006.201.14:38:31.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.14:38:31.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.14:38:31.31#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:31.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:31.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:31.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:31.37#ibcon#enter wrdev, iclass 25, count 2 2006.201.14:38:31.37#ibcon#first serial, iclass 25, count 2 2006.201.14:38:31.37#ibcon#enter sib2, iclass 25, count 2 2006.201.14:38:31.37#ibcon#flushed, iclass 25, count 2 2006.201.14:38:31.37#ibcon#about to write, iclass 25, count 2 2006.201.14:38:31.37#ibcon#wrote, iclass 25, count 2 2006.201.14:38:31.37#ibcon#about to read 3, iclass 25, count 2 2006.201.14:38:31.39#ibcon#read 3, iclass 25, count 2 2006.201.14:38:31.39#ibcon#about to read 4, iclass 25, count 2 2006.201.14:38:31.39#ibcon#read 4, iclass 25, count 2 2006.201.14:38:31.39#ibcon#about to read 5, iclass 25, count 2 2006.201.14:38:31.39#ibcon#read 5, iclass 25, count 2 2006.201.14:38:31.39#ibcon#about to read 6, iclass 25, count 2 2006.201.14:38:31.39#ibcon#read 6, iclass 25, count 2 2006.201.14:38:31.39#ibcon#end of sib2, iclass 25, count 2 2006.201.14:38:31.39#ibcon#*mode == 0, iclass 25, count 2 2006.201.14:38:31.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.14:38:31.39#ibcon#[27=AT06-04\r\n] 2006.201.14:38:31.39#ibcon#*before write, iclass 25, count 2 2006.201.14:38:31.39#ibcon#enter sib2, iclass 25, count 2 2006.201.14:38:31.39#ibcon#flushed, iclass 25, count 2 2006.201.14:38:31.39#ibcon#about to write, iclass 25, count 2 2006.201.14:38:31.39#ibcon#wrote, iclass 25, count 2 2006.201.14:38:31.39#ibcon#about to read 3, iclass 25, count 2 2006.201.14:38:31.43#ibcon#read 3, iclass 25, count 2 2006.201.14:38:31.43#ibcon#about to read 4, iclass 25, count 2 2006.201.14:38:31.43#ibcon#read 4, iclass 25, count 2 2006.201.14:38:31.43#ibcon#about to read 5, iclass 25, count 2 2006.201.14:38:31.43#ibcon#read 5, iclass 25, count 2 2006.201.14:38:31.43#ibcon#about to read 6, iclass 25, count 2 2006.201.14:38:31.43#ibcon#read 6, iclass 25, count 2 2006.201.14:38:31.43#ibcon#end of sib2, iclass 25, count 2 2006.201.14:38:31.43#ibcon#*after write, iclass 25, count 2 2006.201.14:38:31.43#ibcon#*before return 0, iclass 25, count 2 2006.201.14:38:31.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:31.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:38:31.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.14:38:31.43#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:31.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:31.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:31.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:31.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:38:31.55#ibcon#first serial, iclass 25, count 0 2006.201.14:38:31.55#ibcon#enter sib2, iclass 25, count 0 2006.201.14:38:31.55#ibcon#flushed, iclass 25, count 0 2006.201.14:38:31.55#ibcon#about to write, iclass 25, count 0 2006.201.14:38:31.55#ibcon#wrote, iclass 25, count 0 2006.201.14:38:31.55#ibcon#about to read 3, iclass 25, count 0 2006.201.14:38:31.57#ibcon#read 3, iclass 25, count 0 2006.201.14:38:31.57#ibcon#about to read 4, iclass 25, count 0 2006.201.14:38:31.57#ibcon#read 4, iclass 25, count 0 2006.201.14:38:31.57#ibcon#about to read 5, iclass 25, count 0 2006.201.14:38:31.57#ibcon#read 5, iclass 25, count 0 2006.201.14:38:31.57#ibcon#about to read 6, iclass 25, count 0 2006.201.14:38:31.57#ibcon#read 6, iclass 25, count 0 2006.201.14:38:31.57#ibcon#end of sib2, iclass 25, count 0 2006.201.14:38:31.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:38:31.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:38:31.57#ibcon#[27=USB\r\n] 2006.201.14:38:31.57#ibcon#*before write, iclass 25, count 0 2006.201.14:38:31.57#ibcon#enter sib2, iclass 25, count 0 2006.201.14:38:31.57#ibcon#flushed, iclass 25, count 0 2006.201.14:38:31.57#ibcon#about to write, iclass 25, count 0 2006.201.14:38:31.57#ibcon#wrote, iclass 25, count 0 2006.201.14:38:31.57#ibcon#about to read 3, iclass 25, count 0 2006.201.14:38:31.60#ibcon#read 3, iclass 25, count 0 2006.201.14:38:31.60#ibcon#about to read 4, iclass 25, count 0 2006.201.14:38:31.60#ibcon#read 4, iclass 25, count 0 2006.201.14:38:31.60#ibcon#about to read 5, iclass 25, count 0 2006.201.14:38:31.60#ibcon#read 5, iclass 25, count 0 2006.201.14:38:31.60#ibcon#about to read 6, iclass 25, count 0 2006.201.14:38:31.60#ibcon#read 6, iclass 25, count 0 2006.201.14:38:31.60#ibcon#end of sib2, iclass 25, count 0 2006.201.14:38:31.60#ibcon#*after write, iclass 25, count 0 2006.201.14:38:31.60#ibcon#*before return 0, iclass 25, count 0 2006.201.14:38:31.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:31.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:38:31.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:38:31.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:38:31.60$vck44/vblo=7,734.99 2006.201.14:38:31.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.14:38:31.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.14:38:31.60#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:31.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:31.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:31.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:31.60#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:38:31.60#ibcon#first serial, iclass 27, count 0 2006.201.14:38:31.60#ibcon#enter sib2, iclass 27, count 0 2006.201.14:38:31.60#ibcon#flushed, iclass 27, count 0 2006.201.14:38:31.60#ibcon#about to write, iclass 27, count 0 2006.201.14:38:31.60#ibcon#wrote, iclass 27, count 0 2006.201.14:38:31.60#ibcon#about to read 3, iclass 27, count 0 2006.201.14:38:31.62#ibcon#read 3, iclass 27, count 0 2006.201.14:38:31.62#ibcon#about to read 4, iclass 27, count 0 2006.201.14:38:31.62#ibcon#read 4, iclass 27, count 0 2006.201.14:38:31.62#ibcon#about to read 5, iclass 27, count 0 2006.201.14:38:31.62#ibcon#read 5, iclass 27, count 0 2006.201.14:38:31.62#ibcon#about to read 6, iclass 27, count 0 2006.201.14:38:31.62#ibcon#read 6, iclass 27, count 0 2006.201.14:38:31.62#ibcon#end of sib2, iclass 27, count 0 2006.201.14:38:31.62#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:38:31.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:38:31.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:38:31.62#ibcon#*before write, iclass 27, count 0 2006.201.14:38:31.62#ibcon#enter sib2, iclass 27, count 0 2006.201.14:38:31.62#ibcon#flushed, iclass 27, count 0 2006.201.14:38:31.62#ibcon#about to write, iclass 27, count 0 2006.201.14:38:31.62#ibcon#wrote, iclass 27, count 0 2006.201.14:38:31.62#ibcon#about to read 3, iclass 27, count 0 2006.201.14:38:31.66#ibcon#read 3, iclass 27, count 0 2006.201.14:38:31.66#ibcon#about to read 4, iclass 27, count 0 2006.201.14:38:31.66#ibcon#read 4, iclass 27, count 0 2006.201.14:38:31.66#ibcon#about to read 5, iclass 27, count 0 2006.201.14:38:31.66#ibcon#read 5, iclass 27, count 0 2006.201.14:38:31.66#ibcon#about to read 6, iclass 27, count 0 2006.201.14:38:31.66#ibcon#read 6, iclass 27, count 0 2006.201.14:38:31.66#ibcon#end of sib2, iclass 27, count 0 2006.201.14:38:31.66#ibcon#*after write, iclass 27, count 0 2006.201.14:38:31.66#ibcon#*before return 0, iclass 27, count 0 2006.201.14:38:31.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:31.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:38:31.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:38:31.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:38:31.66$vck44/vb=7,4 2006.201.14:38:31.66#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.14:38:31.66#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.14:38:31.66#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:31.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:31.72#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:31.72#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:31.72#ibcon#enter wrdev, iclass 29, count 2 2006.201.14:38:31.72#ibcon#first serial, iclass 29, count 2 2006.201.14:38:31.72#ibcon#enter sib2, iclass 29, count 2 2006.201.14:38:31.72#ibcon#flushed, iclass 29, count 2 2006.201.14:38:31.72#ibcon#about to write, iclass 29, count 2 2006.201.14:38:31.72#ibcon#wrote, iclass 29, count 2 2006.201.14:38:31.72#ibcon#about to read 3, iclass 29, count 2 2006.201.14:38:31.74#ibcon#read 3, iclass 29, count 2 2006.201.14:38:31.74#ibcon#about to read 4, iclass 29, count 2 2006.201.14:38:31.74#ibcon#read 4, iclass 29, count 2 2006.201.14:38:31.74#ibcon#about to read 5, iclass 29, count 2 2006.201.14:38:31.74#ibcon#read 5, iclass 29, count 2 2006.201.14:38:31.74#ibcon#about to read 6, iclass 29, count 2 2006.201.14:38:31.74#ibcon#read 6, iclass 29, count 2 2006.201.14:38:31.74#ibcon#end of sib2, iclass 29, count 2 2006.201.14:38:31.74#ibcon#*mode == 0, iclass 29, count 2 2006.201.14:38:31.74#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.14:38:31.74#ibcon#[27=AT07-04\r\n] 2006.201.14:38:31.74#ibcon#*before write, iclass 29, count 2 2006.201.14:38:31.74#ibcon#enter sib2, iclass 29, count 2 2006.201.14:38:31.74#ibcon#flushed, iclass 29, count 2 2006.201.14:38:31.74#ibcon#about to write, iclass 29, count 2 2006.201.14:38:31.74#ibcon#wrote, iclass 29, count 2 2006.201.14:38:31.74#ibcon#about to read 3, iclass 29, count 2 2006.201.14:38:31.77#ibcon#read 3, iclass 29, count 2 2006.201.14:38:31.77#ibcon#about to read 4, iclass 29, count 2 2006.201.14:38:31.77#ibcon#read 4, iclass 29, count 2 2006.201.14:38:31.77#ibcon#about to read 5, iclass 29, count 2 2006.201.14:38:31.77#ibcon#read 5, iclass 29, count 2 2006.201.14:38:31.77#ibcon#about to read 6, iclass 29, count 2 2006.201.14:38:31.77#ibcon#read 6, iclass 29, count 2 2006.201.14:38:31.77#ibcon#end of sib2, iclass 29, count 2 2006.201.14:38:31.77#ibcon#*after write, iclass 29, count 2 2006.201.14:38:31.77#ibcon#*before return 0, iclass 29, count 2 2006.201.14:38:31.77#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:31.77#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:38:31.77#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.14:38:31.77#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:31.77#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:31.89#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:31.89#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:31.89#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:38:31.89#ibcon#first serial, iclass 29, count 0 2006.201.14:38:31.89#ibcon#enter sib2, iclass 29, count 0 2006.201.14:38:31.89#ibcon#flushed, iclass 29, count 0 2006.201.14:38:31.89#ibcon#about to write, iclass 29, count 0 2006.201.14:38:31.89#ibcon#wrote, iclass 29, count 0 2006.201.14:38:31.89#ibcon#about to read 3, iclass 29, count 0 2006.201.14:38:31.91#ibcon#read 3, iclass 29, count 0 2006.201.14:38:31.91#ibcon#about to read 4, iclass 29, count 0 2006.201.14:38:31.91#ibcon#read 4, iclass 29, count 0 2006.201.14:38:31.91#ibcon#about to read 5, iclass 29, count 0 2006.201.14:38:31.91#ibcon#read 5, iclass 29, count 0 2006.201.14:38:31.91#ibcon#about to read 6, iclass 29, count 0 2006.201.14:38:31.91#ibcon#read 6, iclass 29, count 0 2006.201.14:38:31.91#ibcon#end of sib2, iclass 29, count 0 2006.201.14:38:31.91#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:38:31.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:38:31.91#ibcon#[27=USB\r\n] 2006.201.14:38:31.91#ibcon#*before write, iclass 29, count 0 2006.201.14:38:31.91#ibcon#enter sib2, iclass 29, count 0 2006.201.14:38:31.91#ibcon#flushed, iclass 29, count 0 2006.201.14:38:31.91#ibcon#about to write, iclass 29, count 0 2006.201.14:38:31.91#ibcon#wrote, iclass 29, count 0 2006.201.14:38:31.91#ibcon#about to read 3, iclass 29, count 0 2006.201.14:38:31.94#ibcon#read 3, iclass 29, count 0 2006.201.14:38:31.94#ibcon#about to read 4, iclass 29, count 0 2006.201.14:38:31.94#ibcon#read 4, iclass 29, count 0 2006.201.14:38:31.94#ibcon#about to read 5, iclass 29, count 0 2006.201.14:38:31.94#ibcon#read 5, iclass 29, count 0 2006.201.14:38:31.94#ibcon#about to read 6, iclass 29, count 0 2006.201.14:38:31.94#ibcon#read 6, iclass 29, count 0 2006.201.14:38:31.94#ibcon#end of sib2, iclass 29, count 0 2006.201.14:38:31.94#ibcon#*after write, iclass 29, count 0 2006.201.14:38:31.94#ibcon#*before return 0, iclass 29, count 0 2006.201.14:38:31.94#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:31.94#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:38:31.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:38:31.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:38:31.94$vck44/vblo=8,744.99 2006.201.14:38:31.94#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.14:38:31.94#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.14:38:31.94#ibcon#ireg 17 cls_cnt 0 2006.201.14:38:31.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:31.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:31.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:31.94#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:38:31.94#ibcon#first serial, iclass 31, count 0 2006.201.14:38:31.94#ibcon#enter sib2, iclass 31, count 0 2006.201.14:38:31.94#ibcon#flushed, iclass 31, count 0 2006.201.14:38:31.94#ibcon#about to write, iclass 31, count 0 2006.201.14:38:31.94#ibcon#wrote, iclass 31, count 0 2006.201.14:38:31.94#ibcon#about to read 3, iclass 31, count 0 2006.201.14:38:31.96#ibcon#read 3, iclass 31, count 0 2006.201.14:38:31.96#ibcon#about to read 4, iclass 31, count 0 2006.201.14:38:31.96#ibcon#read 4, iclass 31, count 0 2006.201.14:38:31.96#ibcon#about to read 5, iclass 31, count 0 2006.201.14:38:31.96#ibcon#read 5, iclass 31, count 0 2006.201.14:38:31.96#ibcon#about to read 6, iclass 31, count 0 2006.201.14:38:31.96#ibcon#read 6, iclass 31, count 0 2006.201.14:38:31.96#ibcon#end of sib2, iclass 31, count 0 2006.201.14:38:31.96#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:38:31.96#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:38:31.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:38:31.96#ibcon#*before write, iclass 31, count 0 2006.201.14:38:31.96#ibcon#enter sib2, iclass 31, count 0 2006.201.14:38:31.96#ibcon#flushed, iclass 31, count 0 2006.201.14:38:31.96#ibcon#about to write, iclass 31, count 0 2006.201.14:38:31.96#ibcon#wrote, iclass 31, count 0 2006.201.14:38:31.96#ibcon#about to read 3, iclass 31, count 0 2006.201.14:38:32.00#ibcon#read 3, iclass 31, count 0 2006.201.14:38:32.00#ibcon#about to read 4, iclass 31, count 0 2006.201.14:38:32.00#ibcon#read 4, iclass 31, count 0 2006.201.14:38:32.00#ibcon#about to read 5, iclass 31, count 0 2006.201.14:38:32.00#ibcon#read 5, iclass 31, count 0 2006.201.14:38:32.00#ibcon#about to read 6, iclass 31, count 0 2006.201.14:38:32.00#ibcon#read 6, iclass 31, count 0 2006.201.14:38:32.00#ibcon#end of sib2, iclass 31, count 0 2006.201.14:38:32.00#ibcon#*after write, iclass 31, count 0 2006.201.14:38:32.00#ibcon#*before return 0, iclass 31, count 0 2006.201.14:38:32.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:32.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:38:32.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:38:32.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:38:32.00$vck44/vb=8,4 2006.201.14:38:32.00#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.14:38:32.00#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.14:38:32.00#ibcon#ireg 11 cls_cnt 2 2006.201.14:38:32.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:32.06#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:32.06#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:32.06#ibcon#enter wrdev, iclass 33, count 2 2006.201.14:38:32.06#ibcon#first serial, iclass 33, count 2 2006.201.14:38:32.06#ibcon#enter sib2, iclass 33, count 2 2006.201.14:38:32.06#ibcon#flushed, iclass 33, count 2 2006.201.14:38:32.06#ibcon#about to write, iclass 33, count 2 2006.201.14:38:32.06#ibcon#wrote, iclass 33, count 2 2006.201.14:38:32.06#ibcon#about to read 3, iclass 33, count 2 2006.201.14:38:32.08#ibcon#read 3, iclass 33, count 2 2006.201.14:38:32.08#ibcon#about to read 4, iclass 33, count 2 2006.201.14:38:32.08#ibcon#read 4, iclass 33, count 2 2006.201.14:38:32.08#ibcon#about to read 5, iclass 33, count 2 2006.201.14:38:32.08#ibcon#read 5, iclass 33, count 2 2006.201.14:38:32.08#ibcon#about to read 6, iclass 33, count 2 2006.201.14:38:32.08#ibcon#read 6, iclass 33, count 2 2006.201.14:38:32.08#ibcon#end of sib2, iclass 33, count 2 2006.201.14:38:32.08#ibcon#*mode == 0, iclass 33, count 2 2006.201.14:38:32.08#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.14:38:32.08#ibcon#[27=AT08-04\r\n] 2006.201.14:38:32.08#ibcon#*before write, iclass 33, count 2 2006.201.14:38:32.08#ibcon#enter sib2, iclass 33, count 2 2006.201.14:38:32.08#ibcon#flushed, iclass 33, count 2 2006.201.14:38:32.08#ibcon#about to write, iclass 33, count 2 2006.201.14:38:32.08#ibcon#wrote, iclass 33, count 2 2006.201.14:38:32.08#ibcon#about to read 3, iclass 33, count 2 2006.201.14:38:32.11#ibcon#read 3, iclass 33, count 2 2006.201.14:38:32.11#ibcon#about to read 4, iclass 33, count 2 2006.201.14:38:32.11#ibcon#read 4, iclass 33, count 2 2006.201.14:38:32.11#ibcon#about to read 5, iclass 33, count 2 2006.201.14:38:32.11#ibcon#read 5, iclass 33, count 2 2006.201.14:38:32.11#ibcon#about to read 6, iclass 33, count 2 2006.201.14:38:32.11#ibcon#read 6, iclass 33, count 2 2006.201.14:38:32.11#ibcon#end of sib2, iclass 33, count 2 2006.201.14:38:32.11#ibcon#*after write, iclass 33, count 2 2006.201.14:38:32.11#ibcon#*before return 0, iclass 33, count 2 2006.201.14:38:32.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:32.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:38:32.11#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.14:38:32.11#ibcon#ireg 7 cls_cnt 0 2006.201.14:38:32.11#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:32.23#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:32.23#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:32.23#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:38:32.23#ibcon#first serial, iclass 33, count 0 2006.201.14:38:32.23#ibcon#enter sib2, iclass 33, count 0 2006.201.14:38:32.23#ibcon#flushed, iclass 33, count 0 2006.201.14:38:32.23#ibcon#about to write, iclass 33, count 0 2006.201.14:38:32.23#ibcon#wrote, iclass 33, count 0 2006.201.14:38:32.23#ibcon#about to read 3, iclass 33, count 0 2006.201.14:38:32.25#ibcon#read 3, iclass 33, count 0 2006.201.14:38:32.25#ibcon#about to read 4, iclass 33, count 0 2006.201.14:38:32.25#ibcon#read 4, iclass 33, count 0 2006.201.14:38:32.25#ibcon#about to read 5, iclass 33, count 0 2006.201.14:38:32.25#ibcon#read 5, iclass 33, count 0 2006.201.14:38:32.25#ibcon#about to read 6, iclass 33, count 0 2006.201.14:38:32.25#ibcon#read 6, iclass 33, count 0 2006.201.14:38:32.25#ibcon#end of sib2, iclass 33, count 0 2006.201.14:38:32.25#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:38:32.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:38:32.25#ibcon#[27=USB\r\n] 2006.201.14:38:32.25#ibcon#*before write, iclass 33, count 0 2006.201.14:38:32.25#ibcon#enter sib2, iclass 33, count 0 2006.201.14:38:32.25#ibcon#flushed, iclass 33, count 0 2006.201.14:38:32.25#ibcon#about to write, iclass 33, count 0 2006.201.14:38:32.25#ibcon#wrote, iclass 33, count 0 2006.201.14:38:32.25#ibcon#about to read 3, iclass 33, count 0 2006.201.14:38:32.28#ibcon#read 3, iclass 33, count 0 2006.201.14:38:32.28#ibcon#about to read 4, iclass 33, count 0 2006.201.14:38:32.28#ibcon#read 4, iclass 33, count 0 2006.201.14:38:32.28#ibcon#about to read 5, iclass 33, count 0 2006.201.14:38:32.28#ibcon#read 5, iclass 33, count 0 2006.201.14:38:32.28#ibcon#about to read 6, iclass 33, count 0 2006.201.14:38:32.28#ibcon#read 6, iclass 33, count 0 2006.201.14:38:32.28#ibcon#end of sib2, iclass 33, count 0 2006.201.14:38:32.28#ibcon#*after write, iclass 33, count 0 2006.201.14:38:32.28#ibcon#*before return 0, iclass 33, count 0 2006.201.14:38:32.28#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:32.28#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:38:32.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:38:32.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:38:32.28$vck44/vabw=wide 2006.201.14:38:32.28#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.14:38:32.28#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.14:38:32.28#ibcon#ireg 8 cls_cnt 0 2006.201.14:38:32.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:32.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:32.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:32.28#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:38:32.28#ibcon#first serial, iclass 35, count 0 2006.201.14:38:32.28#ibcon#enter sib2, iclass 35, count 0 2006.201.14:38:32.28#ibcon#flushed, iclass 35, count 0 2006.201.14:38:32.28#ibcon#about to write, iclass 35, count 0 2006.201.14:38:32.28#ibcon#wrote, iclass 35, count 0 2006.201.14:38:32.28#ibcon#about to read 3, iclass 35, count 0 2006.201.14:38:32.30#ibcon#read 3, iclass 35, count 0 2006.201.14:38:32.30#ibcon#about to read 4, iclass 35, count 0 2006.201.14:38:32.30#ibcon#read 4, iclass 35, count 0 2006.201.14:38:32.30#ibcon#about to read 5, iclass 35, count 0 2006.201.14:38:32.30#ibcon#read 5, iclass 35, count 0 2006.201.14:38:32.30#ibcon#about to read 6, iclass 35, count 0 2006.201.14:38:32.30#ibcon#read 6, iclass 35, count 0 2006.201.14:38:32.30#ibcon#end of sib2, iclass 35, count 0 2006.201.14:38:32.30#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:38:32.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:38:32.30#ibcon#[25=BW32\r\n] 2006.201.14:38:32.30#ibcon#*before write, iclass 35, count 0 2006.201.14:38:32.30#ibcon#enter sib2, iclass 35, count 0 2006.201.14:38:32.30#ibcon#flushed, iclass 35, count 0 2006.201.14:38:32.30#ibcon#about to write, iclass 35, count 0 2006.201.14:38:32.30#ibcon#wrote, iclass 35, count 0 2006.201.14:38:32.30#ibcon#about to read 3, iclass 35, count 0 2006.201.14:38:32.34#ibcon#read 3, iclass 35, count 0 2006.201.14:38:32.34#ibcon#about to read 4, iclass 35, count 0 2006.201.14:38:32.34#ibcon#read 4, iclass 35, count 0 2006.201.14:38:32.34#ibcon#about to read 5, iclass 35, count 0 2006.201.14:38:32.34#ibcon#read 5, iclass 35, count 0 2006.201.14:38:32.34#ibcon#about to read 6, iclass 35, count 0 2006.201.14:38:32.34#ibcon#read 6, iclass 35, count 0 2006.201.14:38:32.34#ibcon#end of sib2, iclass 35, count 0 2006.201.14:38:32.34#ibcon#*after write, iclass 35, count 0 2006.201.14:38:32.34#ibcon#*before return 0, iclass 35, count 0 2006.201.14:38:32.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:32.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:38:32.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:38:32.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:38:32.34$vck44/vbbw=wide 2006.201.14:38:32.34#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.14:38:32.34#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.14:38:32.34#ibcon#ireg 8 cls_cnt 0 2006.201.14:38:32.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:38:32.40#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:38:32.40#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:38:32.40#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:38:32.40#ibcon#first serial, iclass 37, count 0 2006.201.14:38:32.40#ibcon#enter sib2, iclass 37, count 0 2006.201.14:38:32.40#ibcon#flushed, iclass 37, count 0 2006.201.14:38:32.40#ibcon#about to write, iclass 37, count 0 2006.201.14:38:32.40#ibcon#wrote, iclass 37, count 0 2006.201.14:38:32.40#ibcon#about to read 3, iclass 37, count 0 2006.201.14:38:32.42#ibcon#read 3, iclass 37, count 0 2006.201.14:38:32.42#ibcon#about to read 4, iclass 37, count 0 2006.201.14:38:32.42#ibcon#read 4, iclass 37, count 0 2006.201.14:38:32.42#ibcon#about to read 5, iclass 37, count 0 2006.201.14:38:32.42#ibcon#read 5, iclass 37, count 0 2006.201.14:38:32.42#ibcon#about to read 6, iclass 37, count 0 2006.201.14:38:32.42#ibcon#read 6, iclass 37, count 0 2006.201.14:38:32.42#ibcon#end of sib2, iclass 37, count 0 2006.201.14:38:32.42#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:38:32.42#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:38:32.42#ibcon#[27=BW32\r\n] 2006.201.14:38:32.42#ibcon#*before write, iclass 37, count 0 2006.201.14:38:32.42#ibcon#enter sib2, iclass 37, count 0 2006.201.14:38:32.42#ibcon#flushed, iclass 37, count 0 2006.201.14:38:32.42#ibcon#about to write, iclass 37, count 0 2006.201.14:38:32.42#ibcon#wrote, iclass 37, count 0 2006.201.14:38:32.42#ibcon#about to read 3, iclass 37, count 0 2006.201.14:38:32.45#ibcon#read 3, iclass 37, count 0 2006.201.14:38:32.45#ibcon#about to read 4, iclass 37, count 0 2006.201.14:38:32.45#ibcon#read 4, iclass 37, count 0 2006.201.14:38:32.45#ibcon#about to read 5, iclass 37, count 0 2006.201.14:38:32.45#ibcon#read 5, iclass 37, count 0 2006.201.14:38:32.45#ibcon#about to read 6, iclass 37, count 0 2006.201.14:38:32.45#ibcon#read 6, iclass 37, count 0 2006.201.14:38:32.45#ibcon#end of sib2, iclass 37, count 0 2006.201.14:38:32.45#ibcon#*after write, iclass 37, count 0 2006.201.14:38:32.45#ibcon#*before return 0, iclass 37, count 0 2006.201.14:38:32.45#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:38:32.45#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:38:32.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:38:32.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:38:32.45$setupk4/ifdk4 2006.201.14:38:32.45$ifdk4/lo= 2006.201.14:38:32.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:38:32.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:38:32.45$ifdk4/patch= 2006.201.14:38:32.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:38:32.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:38:32.45$setupk4/!*+20s 2006.201.14:38:34.60#abcon#<5=/04 1.2 2.3 20.771001003.4\r\n> 2006.201.14:38:34.62#abcon#{5=INTERFACE CLEAR} 2006.201.14:38:34.68#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:38:44.77#abcon#<5=/04 1.3 2.4 20.771001003.4\r\n> 2006.201.14:38:44.79#abcon#{5=INTERFACE CLEAR} 2006.201.14:38:44.85#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:38:46.93$setupk4/"tpicd 2006.201.14:38:46.93$setupk4/echo=off 2006.201.14:38:46.93$setupk4/xlog=off 2006.201.14:38:46.93:!2006.201.14:42:11 2006.201.14:38:51.13#trakl#Source acquired 2006.201.14:38:52.13#flagr#flagr/antenna,acquired 2006.201.14:42:11.00:preob 2006.201.14:42:11.14/onsource/TRACKING 2006.201.14:42:11.14:!2006.201.14:42:21 2006.201.14:42:21.00:"tape 2006.201.14:42:21.00:"st=record 2006.201.14:42:21.00:data_valid=on 2006.201.14:42:21.00:midob 2006.201.14:42:22.14/onsource/TRACKING 2006.201.14:42:22.14/wx/20.77,1003.3,100 2006.201.14:42:22.32/cable/+6.4752E-03 2006.201.14:42:23.41/va/01,08,usb,yes,29,31 2006.201.14:42:23.41/va/02,07,usb,yes,32,32 2006.201.14:42:23.41/va/03,08,usb,yes,28,30 2006.201.14:42:23.41/va/04,07,usb,yes,33,34 2006.201.14:42:23.41/va/05,04,usb,yes,29,29 2006.201.14:42:23.41/va/06,05,usb,yes,29,29 2006.201.14:42:23.41/va/07,05,usb,yes,28,29 2006.201.14:42:23.41/va/08,04,usb,yes,28,33 2006.201.14:42:23.64/valo/01,524.99,yes,locked 2006.201.14:42:23.64/valo/02,534.99,yes,locked 2006.201.14:42:23.64/valo/03,564.99,yes,locked 2006.201.14:42:23.64/valo/04,624.99,yes,locked 2006.201.14:42:23.64/valo/05,734.99,yes,locked 2006.201.14:42:23.64/valo/06,814.99,yes,locked 2006.201.14:42:23.64/valo/07,864.99,yes,locked 2006.201.14:42:23.64/valo/08,884.99,yes,locked 2006.201.14:42:24.73/vb/01,04,usb,yes,29,27 2006.201.14:42:24.73/vb/02,05,usb,yes,27,27 2006.201.14:42:24.73/vb/03,04,usb,yes,28,31 2006.201.14:42:24.73/vb/04,05,usb,yes,28,27 2006.201.14:42:24.73/vb/05,04,usb,yes,25,27 2006.201.14:42:24.73/vb/06,04,usb,yes,29,26 2006.201.14:42:24.73/vb/07,04,usb,yes,29,29 2006.201.14:42:24.73/vb/08,04,usb,yes,27,30 2006.201.14:42:24.97/vblo/01,629.99,yes,locked 2006.201.14:42:24.97/vblo/02,634.99,yes,locked 2006.201.14:42:24.97/vblo/03,649.99,yes,locked 2006.201.14:42:24.97/vblo/04,679.99,yes,locked 2006.201.14:42:24.97/vblo/05,709.99,yes,locked 2006.201.14:42:24.97/vblo/06,719.99,yes,locked 2006.201.14:42:24.97/vblo/07,734.99,yes,locked 2006.201.14:42:24.97/vblo/08,744.99,yes,locked 2006.201.14:42:25.12/vabw/8 2006.201.14:42:25.27/vbbw/8 2006.201.14:42:25.36/xfe/off,on,14.2 2006.201.14:42:25.73/ifatt/23,28,28,28 2006.201.14:42:26.06/fmout-gps/S +4.56E-07 2006.201.14:42:26.13:!2006.201.14:43:31 2006.201.14:43:31.00:data_valid=off 2006.201.14:43:31.00:"et 2006.201.14:43:31.00:!+3s 2006.201.14:43:34.02:"tape 2006.201.14:43:34.02:postob 2006.201.14:43:34.13/cable/+6.4761E-03 2006.201.14:43:34.13/wx/20.76,1003.4,100 2006.201.14:43:34.21/fmout-gps/S +4.56E-07 2006.201.14:43:34.21:scan_name=201-1446,jd0607,720 2006.201.14:43:34.21:source=1749+096,175132.82,093900.7,2000.0,cw 2006.201.14:43:36.14#flagr#flagr/antenna,new-source 2006.201.14:43:36.14:checkk5 2006.201.14:43:36.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:43:36.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:43:37.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:43:37.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:43:38.01/chk_obsdata//k5ts1/T2011442??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.14:43:38.38/chk_obsdata//k5ts2/T2011442??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.14:43:38.74/chk_obsdata//k5ts3/T2011442??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.14:43:39.11/chk_obsdata//k5ts4/T2011442??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.14:43:39.80/k5log//k5ts1_log_newline 2006.201.14:43:40.50/k5log//k5ts2_log_newline 2006.201.14:43:41.18/k5log//k5ts3_log_newline 2006.201.14:43:41.86/k5log//k5ts4_log_newline 2006.201.14:43:41.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:43:41.89:setupk4=1 2006.201.14:43:41.89$setupk4/echo=on 2006.201.14:43:41.89$setupk4/pcalon 2006.201.14:43:41.89$pcalon/"no phase cal control is implemented here 2006.201.14:43:41.89$setupk4/"tpicd=stop 2006.201.14:43:41.89$setupk4/"rec=synch_on 2006.201.14:43:41.89$setupk4/"rec_mode=128 2006.201.14:43:41.89$setupk4/!* 2006.201.14:43:41.89$setupk4/recpk4 2006.201.14:43:41.89$recpk4/recpatch= 2006.201.14:43:41.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:43:41.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:43:41.90$setupk4/vck44 2006.201.14:43:41.90$vck44/valo=1,524.99 2006.201.14:43:41.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.14:43:41.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.14:43:41.90#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:41.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:41.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:41.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:41.90#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:43:41.90#ibcon#first serial, iclass 13, count 0 2006.201.14:43:41.90#ibcon#enter sib2, iclass 13, count 0 2006.201.14:43:41.90#ibcon#flushed, iclass 13, count 0 2006.201.14:43:41.90#ibcon#about to write, iclass 13, count 0 2006.201.14:43:41.90#ibcon#wrote, iclass 13, count 0 2006.201.14:43:41.90#ibcon#about to read 3, iclass 13, count 0 2006.201.14:43:41.93#ibcon#read 3, iclass 13, count 0 2006.201.14:43:41.93#ibcon#about to read 4, iclass 13, count 0 2006.201.14:43:41.93#ibcon#read 4, iclass 13, count 0 2006.201.14:43:41.93#ibcon#about to read 5, iclass 13, count 0 2006.201.14:43:41.93#ibcon#read 5, iclass 13, count 0 2006.201.14:43:41.93#ibcon#about to read 6, iclass 13, count 0 2006.201.14:43:41.93#ibcon#read 6, iclass 13, count 0 2006.201.14:43:41.93#ibcon#end of sib2, iclass 13, count 0 2006.201.14:43:41.93#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:43:41.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:43:41.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:43:41.93#ibcon#*before write, iclass 13, count 0 2006.201.14:43:41.93#ibcon#enter sib2, iclass 13, count 0 2006.201.14:43:41.93#ibcon#flushed, iclass 13, count 0 2006.201.14:43:41.93#ibcon#about to write, iclass 13, count 0 2006.201.14:43:41.93#ibcon#wrote, iclass 13, count 0 2006.201.14:43:41.93#ibcon#about to read 3, iclass 13, count 0 2006.201.14:43:41.98#ibcon#read 3, iclass 13, count 0 2006.201.14:43:41.98#ibcon#about to read 4, iclass 13, count 0 2006.201.14:43:41.98#ibcon#read 4, iclass 13, count 0 2006.201.14:43:41.98#ibcon#about to read 5, iclass 13, count 0 2006.201.14:43:41.98#ibcon#read 5, iclass 13, count 0 2006.201.14:43:41.98#ibcon#about to read 6, iclass 13, count 0 2006.201.14:43:41.98#ibcon#read 6, iclass 13, count 0 2006.201.14:43:41.98#ibcon#end of sib2, iclass 13, count 0 2006.201.14:43:41.98#ibcon#*after write, iclass 13, count 0 2006.201.14:43:41.98#ibcon#*before return 0, iclass 13, count 0 2006.201.14:43:41.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:41.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:41.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:43:41.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:43:41.98$vck44/va=1,8 2006.201.14:43:41.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.14:43:41.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.14:43:41.98#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:41.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:41.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:41.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:41.98#ibcon#enter wrdev, iclass 15, count 2 2006.201.14:43:41.98#ibcon#first serial, iclass 15, count 2 2006.201.14:43:41.98#ibcon#enter sib2, iclass 15, count 2 2006.201.14:43:41.98#ibcon#flushed, iclass 15, count 2 2006.201.14:43:41.98#ibcon#about to write, iclass 15, count 2 2006.201.14:43:41.98#ibcon#wrote, iclass 15, count 2 2006.201.14:43:41.98#ibcon#about to read 3, iclass 15, count 2 2006.201.14:43:42.00#ibcon#read 3, iclass 15, count 2 2006.201.14:43:42.00#ibcon#about to read 4, iclass 15, count 2 2006.201.14:43:42.00#ibcon#read 4, iclass 15, count 2 2006.201.14:43:42.00#ibcon#about to read 5, iclass 15, count 2 2006.201.14:43:42.00#ibcon#read 5, iclass 15, count 2 2006.201.14:43:42.00#ibcon#about to read 6, iclass 15, count 2 2006.201.14:43:42.00#ibcon#read 6, iclass 15, count 2 2006.201.14:43:42.00#ibcon#end of sib2, iclass 15, count 2 2006.201.14:43:42.00#ibcon#*mode == 0, iclass 15, count 2 2006.201.14:43:42.00#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.14:43:42.00#ibcon#[25=AT01-08\r\n] 2006.201.14:43:42.00#ibcon#*before write, iclass 15, count 2 2006.201.14:43:42.00#ibcon#enter sib2, iclass 15, count 2 2006.201.14:43:42.00#ibcon#flushed, iclass 15, count 2 2006.201.14:43:42.00#ibcon#about to write, iclass 15, count 2 2006.201.14:43:42.00#ibcon#wrote, iclass 15, count 2 2006.201.14:43:42.00#ibcon#about to read 3, iclass 15, count 2 2006.201.14:43:42.03#ibcon#read 3, iclass 15, count 2 2006.201.14:43:42.03#ibcon#about to read 4, iclass 15, count 2 2006.201.14:43:42.03#ibcon#read 4, iclass 15, count 2 2006.201.14:43:42.03#ibcon#about to read 5, iclass 15, count 2 2006.201.14:43:42.03#ibcon#read 5, iclass 15, count 2 2006.201.14:43:42.03#ibcon#about to read 6, iclass 15, count 2 2006.201.14:43:42.03#ibcon#read 6, iclass 15, count 2 2006.201.14:43:42.03#ibcon#end of sib2, iclass 15, count 2 2006.201.14:43:42.03#ibcon#*after write, iclass 15, count 2 2006.201.14:43:42.03#ibcon#*before return 0, iclass 15, count 2 2006.201.14:43:42.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:42.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:42.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.14:43:42.03#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:42.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:42.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:42.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:42.15#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:43:42.15#ibcon#first serial, iclass 15, count 0 2006.201.14:43:42.15#ibcon#enter sib2, iclass 15, count 0 2006.201.14:43:42.15#ibcon#flushed, iclass 15, count 0 2006.201.14:43:42.15#ibcon#about to write, iclass 15, count 0 2006.201.14:43:42.15#ibcon#wrote, iclass 15, count 0 2006.201.14:43:42.15#ibcon#about to read 3, iclass 15, count 0 2006.201.14:43:42.17#ibcon#read 3, iclass 15, count 0 2006.201.14:43:42.17#ibcon#about to read 4, iclass 15, count 0 2006.201.14:43:42.17#ibcon#read 4, iclass 15, count 0 2006.201.14:43:42.17#ibcon#about to read 5, iclass 15, count 0 2006.201.14:43:42.17#ibcon#read 5, iclass 15, count 0 2006.201.14:43:42.17#ibcon#about to read 6, iclass 15, count 0 2006.201.14:43:42.17#ibcon#read 6, iclass 15, count 0 2006.201.14:43:42.17#ibcon#end of sib2, iclass 15, count 0 2006.201.14:43:42.17#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:43:42.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:43:42.17#ibcon#[25=USB\r\n] 2006.201.14:43:42.17#ibcon#*before write, iclass 15, count 0 2006.201.14:43:42.17#ibcon#enter sib2, iclass 15, count 0 2006.201.14:43:42.17#ibcon#flushed, iclass 15, count 0 2006.201.14:43:42.17#ibcon#about to write, iclass 15, count 0 2006.201.14:43:42.17#ibcon#wrote, iclass 15, count 0 2006.201.14:43:42.17#ibcon#about to read 3, iclass 15, count 0 2006.201.14:43:42.20#ibcon#read 3, iclass 15, count 0 2006.201.14:43:42.20#ibcon#about to read 4, iclass 15, count 0 2006.201.14:43:42.20#ibcon#read 4, iclass 15, count 0 2006.201.14:43:42.20#ibcon#about to read 5, iclass 15, count 0 2006.201.14:43:42.20#ibcon#read 5, iclass 15, count 0 2006.201.14:43:42.20#ibcon#about to read 6, iclass 15, count 0 2006.201.14:43:42.20#ibcon#read 6, iclass 15, count 0 2006.201.14:43:42.20#ibcon#end of sib2, iclass 15, count 0 2006.201.14:43:42.20#ibcon#*after write, iclass 15, count 0 2006.201.14:43:42.20#ibcon#*before return 0, iclass 15, count 0 2006.201.14:43:42.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:42.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:42.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:43:42.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:43:42.20$vck44/valo=2,534.99 2006.201.14:43:42.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.14:43:42.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.14:43:42.20#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:42.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:42.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:42.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:42.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:43:42.20#ibcon#first serial, iclass 17, count 0 2006.201.14:43:42.20#ibcon#enter sib2, iclass 17, count 0 2006.201.14:43:42.20#ibcon#flushed, iclass 17, count 0 2006.201.14:43:42.20#ibcon#about to write, iclass 17, count 0 2006.201.14:43:42.20#ibcon#wrote, iclass 17, count 0 2006.201.14:43:42.20#ibcon#about to read 3, iclass 17, count 0 2006.201.14:43:42.22#ibcon#read 3, iclass 17, count 0 2006.201.14:43:42.22#ibcon#about to read 4, iclass 17, count 0 2006.201.14:43:42.22#ibcon#read 4, iclass 17, count 0 2006.201.14:43:42.22#ibcon#about to read 5, iclass 17, count 0 2006.201.14:43:42.22#ibcon#read 5, iclass 17, count 0 2006.201.14:43:42.22#ibcon#about to read 6, iclass 17, count 0 2006.201.14:43:42.22#ibcon#read 6, iclass 17, count 0 2006.201.14:43:42.22#ibcon#end of sib2, iclass 17, count 0 2006.201.14:43:42.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:43:42.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:43:42.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:43:42.22#ibcon#*before write, iclass 17, count 0 2006.201.14:43:42.22#ibcon#enter sib2, iclass 17, count 0 2006.201.14:43:42.22#ibcon#flushed, iclass 17, count 0 2006.201.14:43:42.22#ibcon#about to write, iclass 17, count 0 2006.201.14:43:42.22#ibcon#wrote, iclass 17, count 0 2006.201.14:43:42.22#ibcon#about to read 3, iclass 17, count 0 2006.201.14:43:42.26#ibcon#read 3, iclass 17, count 0 2006.201.14:43:42.26#ibcon#about to read 4, iclass 17, count 0 2006.201.14:43:42.26#ibcon#read 4, iclass 17, count 0 2006.201.14:43:42.26#ibcon#about to read 5, iclass 17, count 0 2006.201.14:43:42.26#ibcon#read 5, iclass 17, count 0 2006.201.14:43:42.26#ibcon#about to read 6, iclass 17, count 0 2006.201.14:43:42.26#ibcon#read 6, iclass 17, count 0 2006.201.14:43:42.26#ibcon#end of sib2, iclass 17, count 0 2006.201.14:43:42.26#ibcon#*after write, iclass 17, count 0 2006.201.14:43:42.26#ibcon#*before return 0, iclass 17, count 0 2006.201.14:43:42.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:42.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:42.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:43:42.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:43:42.26$vck44/va=2,7 2006.201.14:43:42.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.14:43:42.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.14:43:42.26#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:42.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:42.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:42.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:42.32#ibcon#enter wrdev, iclass 19, count 2 2006.201.14:43:42.32#ibcon#first serial, iclass 19, count 2 2006.201.14:43:42.32#ibcon#enter sib2, iclass 19, count 2 2006.201.14:43:42.32#ibcon#flushed, iclass 19, count 2 2006.201.14:43:42.32#ibcon#about to write, iclass 19, count 2 2006.201.14:43:42.32#ibcon#wrote, iclass 19, count 2 2006.201.14:43:42.32#ibcon#about to read 3, iclass 19, count 2 2006.201.14:43:42.34#ibcon#read 3, iclass 19, count 2 2006.201.14:43:42.34#ibcon#about to read 4, iclass 19, count 2 2006.201.14:43:42.34#ibcon#read 4, iclass 19, count 2 2006.201.14:43:42.34#ibcon#about to read 5, iclass 19, count 2 2006.201.14:43:42.34#ibcon#read 5, iclass 19, count 2 2006.201.14:43:42.34#ibcon#about to read 6, iclass 19, count 2 2006.201.14:43:42.34#ibcon#read 6, iclass 19, count 2 2006.201.14:43:42.34#ibcon#end of sib2, iclass 19, count 2 2006.201.14:43:42.34#ibcon#*mode == 0, iclass 19, count 2 2006.201.14:43:42.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.14:43:42.34#ibcon#[25=AT02-07\r\n] 2006.201.14:43:42.34#ibcon#*before write, iclass 19, count 2 2006.201.14:43:42.34#ibcon#enter sib2, iclass 19, count 2 2006.201.14:43:42.34#ibcon#flushed, iclass 19, count 2 2006.201.14:43:42.34#ibcon#about to write, iclass 19, count 2 2006.201.14:43:42.34#ibcon#wrote, iclass 19, count 2 2006.201.14:43:42.34#ibcon#about to read 3, iclass 19, count 2 2006.201.14:43:42.37#ibcon#read 3, iclass 19, count 2 2006.201.14:43:42.37#ibcon#about to read 4, iclass 19, count 2 2006.201.14:43:42.37#ibcon#read 4, iclass 19, count 2 2006.201.14:43:42.37#ibcon#about to read 5, iclass 19, count 2 2006.201.14:43:42.37#ibcon#read 5, iclass 19, count 2 2006.201.14:43:42.37#ibcon#about to read 6, iclass 19, count 2 2006.201.14:43:42.37#ibcon#read 6, iclass 19, count 2 2006.201.14:43:42.37#ibcon#end of sib2, iclass 19, count 2 2006.201.14:43:42.37#ibcon#*after write, iclass 19, count 2 2006.201.14:43:42.37#ibcon#*before return 0, iclass 19, count 2 2006.201.14:43:42.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:42.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:42.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.14:43:42.37#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:42.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:42.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:42.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:42.49#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:43:42.49#ibcon#first serial, iclass 19, count 0 2006.201.14:43:42.49#ibcon#enter sib2, iclass 19, count 0 2006.201.14:43:42.49#ibcon#flushed, iclass 19, count 0 2006.201.14:43:42.49#ibcon#about to write, iclass 19, count 0 2006.201.14:43:42.49#ibcon#wrote, iclass 19, count 0 2006.201.14:43:42.49#ibcon#about to read 3, iclass 19, count 0 2006.201.14:43:42.51#ibcon#read 3, iclass 19, count 0 2006.201.14:43:42.51#ibcon#about to read 4, iclass 19, count 0 2006.201.14:43:42.51#ibcon#read 4, iclass 19, count 0 2006.201.14:43:42.51#ibcon#about to read 5, iclass 19, count 0 2006.201.14:43:42.51#ibcon#read 5, iclass 19, count 0 2006.201.14:43:42.51#ibcon#about to read 6, iclass 19, count 0 2006.201.14:43:42.51#ibcon#read 6, iclass 19, count 0 2006.201.14:43:42.51#ibcon#end of sib2, iclass 19, count 0 2006.201.14:43:42.51#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:43:42.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:43:42.51#ibcon#[25=USB\r\n] 2006.201.14:43:42.51#ibcon#*before write, iclass 19, count 0 2006.201.14:43:42.51#ibcon#enter sib2, iclass 19, count 0 2006.201.14:43:42.51#ibcon#flushed, iclass 19, count 0 2006.201.14:43:42.51#ibcon#about to write, iclass 19, count 0 2006.201.14:43:42.51#ibcon#wrote, iclass 19, count 0 2006.201.14:43:42.51#ibcon#about to read 3, iclass 19, count 0 2006.201.14:43:42.54#ibcon#read 3, iclass 19, count 0 2006.201.14:43:42.54#ibcon#about to read 4, iclass 19, count 0 2006.201.14:43:42.54#ibcon#read 4, iclass 19, count 0 2006.201.14:43:42.54#ibcon#about to read 5, iclass 19, count 0 2006.201.14:43:42.54#ibcon#read 5, iclass 19, count 0 2006.201.14:43:42.54#ibcon#about to read 6, iclass 19, count 0 2006.201.14:43:42.54#ibcon#read 6, iclass 19, count 0 2006.201.14:43:42.54#ibcon#end of sib2, iclass 19, count 0 2006.201.14:43:42.54#ibcon#*after write, iclass 19, count 0 2006.201.14:43:42.54#ibcon#*before return 0, iclass 19, count 0 2006.201.14:43:42.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:42.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:42.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:43:42.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:43:42.54$vck44/valo=3,564.99 2006.201.14:43:42.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.14:43:42.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.14:43:42.54#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:42.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:42.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:42.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:42.54#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:43:42.54#ibcon#first serial, iclass 21, count 0 2006.201.14:43:42.54#ibcon#enter sib2, iclass 21, count 0 2006.201.14:43:42.54#ibcon#flushed, iclass 21, count 0 2006.201.14:43:42.54#ibcon#about to write, iclass 21, count 0 2006.201.14:43:42.54#ibcon#wrote, iclass 21, count 0 2006.201.14:43:42.54#ibcon#about to read 3, iclass 21, count 0 2006.201.14:43:42.56#ibcon#read 3, iclass 21, count 0 2006.201.14:43:42.56#ibcon#about to read 4, iclass 21, count 0 2006.201.14:43:42.56#ibcon#read 4, iclass 21, count 0 2006.201.14:43:42.56#ibcon#about to read 5, iclass 21, count 0 2006.201.14:43:42.56#ibcon#read 5, iclass 21, count 0 2006.201.14:43:42.56#ibcon#about to read 6, iclass 21, count 0 2006.201.14:43:42.56#ibcon#read 6, iclass 21, count 0 2006.201.14:43:42.56#ibcon#end of sib2, iclass 21, count 0 2006.201.14:43:42.56#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:43:42.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:43:42.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:43:42.56#ibcon#*before write, iclass 21, count 0 2006.201.14:43:42.56#ibcon#enter sib2, iclass 21, count 0 2006.201.14:43:42.56#ibcon#flushed, iclass 21, count 0 2006.201.14:43:42.56#ibcon#about to write, iclass 21, count 0 2006.201.14:43:42.56#ibcon#wrote, iclass 21, count 0 2006.201.14:43:42.56#ibcon#about to read 3, iclass 21, count 0 2006.201.14:43:42.61#ibcon#read 3, iclass 21, count 0 2006.201.14:43:42.61#ibcon#about to read 4, iclass 21, count 0 2006.201.14:43:42.61#ibcon#read 4, iclass 21, count 0 2006.201.14:43:42.61#ibcon#about to read 5, iclass 21, count 0 2006.201.14:43:42.61#ibcon#read 5, iclass 21, count 0 2006.201.14:43:42.61#ibcon#about to read 6, iclass 21, count 0 2006.201.14:43:42.61#ibcon#read 6, iclass 21, count 0 2006.201.14:43:42.61#ibcon#end of sib2, iclass 21, count 0 2006.201.14:43:42.61#ibcon#*after write, iclass 21, count 0 2006.201.14:43:42.61#ibcon#*before return 0, iclass 21, count 0 2006.201.14:43:42.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:42.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:42.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:43:42.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:43:42.61$vck44/va=3,8 2006.201.14:43:42.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.14:43:42.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.14:43:42.61#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:42.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:43:42.62#abcon#<5=/05 1.3 2.4 20.761001003.4\r\n> 2006.201.14:43:42.64#abcon#{5=INTERFACE CLEAR} 2006.201.14:43:42.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:43:42.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:43:42.66#ibcon#enter wrdev, iclass 24, count 2 2006.201.14:43:42.66#ibcon#first serial, iclass 24, count 2 2006.201.14:43:42.66#ibcon#enter sib2, iclass 24, count 2 2006.201.14:43:42.66#ibcon#flushed, iclass 24, count 2 2006.201.14:43:42.66#ibcon#about to write, iclass 24, count 2 2006.201.14:43:42.66#ibcon#wrote, iclass 24, count 2 2006.201.14:43:42.66#ibcon#about to read 3, iclass 24, count 2 2006.201.14:43:42.68#ibcon#read 3, iclass 24, count 2 2006.201.14:43:42.68#ibcon#about to read 4, iclass 24, count 2 2006.201.14:43:42.68#ibcon#read 4, iclass 24, count 2 2006.201.14:43:42.68#ibcon#about to read 5, iclass 24, count 2 2006.201.14:43:42.68#ibcon#read 5, iclass 24, count 2 2006.201.14:43:42.68#ibcon#about to read 6, iclass 24, count 2 2006.201.14:43:42.68#ibcon#read 6, iclass 24, count 2 2006.201.14:43:42.68#ibcon#end of sib2, iclass 24, count 2 2006.201.14:43:42.68#ibcon#*mode == 0, iclass 24, count 2 2006.201.14:43:42.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.14:43:42.68#ibcon#[25=AT03-08\r\n] 2006.201.14:43:42.68#ibcon#*before write, iclass 24, count 2 2006.201.14:43:42.68#ibcon#enter sib2, iclass 24, count 2 2006.201.14:43:42.68#ibcon#flushed, iclass 24, count 2 2006.201.14:43:42.68#ibcon#about to write, iclass 24, count 2 2006.201.14:43:42.68#ibcon#wrote, iclass 24, count 2 2006.201.14:43:42.68#ibcon#about to read 3, iclass 24, count 2 2006.201.14:43:42.70#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:43:42.71#ibcon#read 3, iclass 24, count 2 2006.201.14:43:42.71#ibcon#about to read 4, iclass 24, count 2 2006.201.14:43:42.71#ibcon#read 4, iclass 24, count 2 2006.201.14:43:42.71#ibcon#about to read 5, iclass 24, count 2 2006.201.14:43:42.71#ibcon#read 5, iclass 24, count 2 2006.201.14:43:42.71#ibcon#about to read 6, iclass 24, count 2 2006.201.14:43:42.71#ibcon#read 6, iclass 24, count 2 2006.201.14:43:42.71#ibcon#end of sib2, iclass 24, count 2 2006.201.14:43:42.71#ibcon#*after write, iclass 24, count 2 2006.201.14:43:42.71#ibcon#*before return 0, iclass 24, count 2 2006.201.14:43:42.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:43:42.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.14:43:42.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.14:43:42.71#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:42.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:43:42.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:43:42.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:43:42.83#ibcon#enter wrdev, iclass 24, count 0 2006.201.14:43:42.83#ibcon#first serial, iclass 24, count 0 2006.201.14:43:42.83#ibcon#enter sib2, iclass 24, count 0 2006.201.14:43:42.83#ibcon#flushed, iclass 24, count 0 2006.201.14:43:42.83#ibcon#about to write, iclass 24, count 0 2006.201.14:43:42.83#ibcon#wrote, iclass 24, count 0 2006.201.14:43:42.83#ibcon#about to read 3, iclass 24, count 0 2006.201.14:43:42.85#ibcon#read 3, iclass 24, count 0 2006.201.14:43:42.85#ibcon#about to read 4, iclass 24, count 0 2006.201.14:43:42.85#ibcon#read 4, iclass 24, count 0 2006.201.14:43:42.85#ibcon#about to read 5, iclass 24, count 0 2006.201.14:43:42.85#ibcon#read 5, iclass 24, count 0 2006.201.14:43:42.85#ibcon#about to read 6, iclass 24, count 0 2006.201.14:43:42.85#ibcon#read 6, iclass 24, count 0 2006.201.14:43:42.85#ibcon#end of sib2, iclass 24, count 0 2006.201.14:43:42.85#ibcon#*mode == 0, iclass 24, count 0 2006.201.14:43:42.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.14:43:42.85#ibcon#[25=USB\r\n] 2006.201.14:43:42.85#ibcon#*before write, iclass 24, count 0 2006.201.14:43:42.85#ibcon#enter sib2, iclass 24, count 0 2006.201.14:43:42.85#ibcon#flushed, iclass 24, count 0 2006.201.14:43:42.85#ibcon#about to write, iclass 24, count 0 2006.201.14:43:42.85#ibcon#wrote, iclass 24, count 0 2006.201.14:43:42.85#ibcon#about to read 3, iclass 24, count 0 2006.201.14:43:42.88#ibcon#read 3, iclass 24, count 0 2006.201.14:43:42.88#ibcon#about to read 4, iclass 24, count 0 2006.201.14:43:42.88#ibcon#read 4, iclass 24, count 0 2006.201.14:43:42.88#ibcon#about to read 5, iclass 24, count 0 2006.201.14:43:42.88#ibcon#read 5, iclass 24, count 0 2006.201.14:43:42.88#ibcon#about to read 6, iclass 24, count 0 2006.201.14:43:42.88#ibcon#read 6, iclass 24, count 0 2006.201.14:43:42.88#ibcon#end of sib2, iclass 24, count 0 2006.201.14:43:42.88#ibcon#*after write, iclass 24, count 0 2006.201.14:43:42.88#ibcon#*before return 0, iclass 24, count 0 2006.201.14:43:42.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:43:42.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.14:43:42.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.14:43:42.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.14:43:42.88$vck44/valo=4,624.99 2006.201.14:43:42.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.14:43:42.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.14:43:42.88#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:42.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:42.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:42.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:42.88#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:43:42.88#ibcon#first serial, iclass 29, count 0 2006.201.14:43:42.88#ibcon#enter sib2, iclass 29, count 0 2006.201.14:43:42.88#ibcon#flushed, iclass 29, count 0 2006.201.14:43:42.88#ibcon#about to write, iclass 29, count 0 2006.201.14:43:42.88#ibcon#wrote, iclass 29, count 0 2006.201.14:43:42.88#ibcon#about to read 3, iclass 29, count 0 2006.201.14:43:42.90#ibcon#read 3, iclass 29, count 0 2006.201.14:43:42.90#ibcon#about to read 4, iclass 29, count 0 2006.201.14:43:42.90#ibcon#read 4, iclass 29, count 0 2006.201.14:43:42.90#ibcon#about to read 5, iclass 29, count 0 2006.201.14:43:42.90#ibcon#read 5, iclass 29, count 0 2006.201.14:43:42.90#ibcon#about to read 6, iclass 29, count 0 2006.201.14:43:42.90#ibcon#read 6, iclass 29, count 0 2006.201.14:43:42.90#ibcon#end of sib2, iclass 29, count 0 2006.201.14:43:42.90#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:43:42.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:43:42.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:43:42.90#ibcon#*before write, iclass 29, count 0 2006.201.14:43:42.90#ibcon#enter sib2, iclass 29, count 0 2006.201.14:43:42.90#ibcon#flushed, iclass 29, count 0 2006.201.14:43:42.90#ibcon#about to write, iclass 29, count 0 2006.201.14:43:42.90#ibcon#wrote, iclass 29, count 0 2006.201.14:43:42.90#ibcon#about to read 3, iclass 29, count 0 2006.201.14:43:42.95#ibcon#read 3, iclass 29, count 0 2006.201.14:43:42.95#ibcon#about to read 4, iclass 29, count 0 2006.201.14:43:42.95#ibcon#read 4, iclass 29, count 0 2006.201.14:43:42.95#ibcon#about to read 5, iclass 29, count 0 2006.201.14:43:42.95#ibcon#read 5, iclass 29, count 0 2006.201.14:43:42.95#ibcon#about to read 6, iclass 29, count 0 2006.201.14:43:42.95#ibcon#read 6, iclass 29, count 0 2006.201.14:43:42.95#ibcon#end of sib2, iclass 29, count 0 2006.201.14:43:42.95#ibcon#*after write, iclass 29, count 0 2006.201.14:43:42.95#ibcon#*before return 0, iclass 29, count 0 2006.201.14:43:42.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:42.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:42.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:43:42.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:43:42.95$vck44/va=4,7 2006.201.14:43:42.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.14:43:42.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.14:43:42.95#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:42.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:43.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:43.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:43.00#ibcon#enter wrdev, iclass 31, count 2 2006.201.14:43:43.00#ibcon#first serial, iclass 31, count 2 2006.201.14:43:43.00#ibcon#enter sib2, iclass 31, count 2 2006.201.14:43:43.00#ibcon#flushed, iclass 31, count 2 2006.201.14:43:43.00#ibcon#about to write, iclass 31, count 2 2006.201.14:43:43.00#ibcon#wrote, iclass 31, count 2 2006.201.14:43:43.00#ibcon#about to read 3, iclass 31, count 2 2006.201.14:43:43.02#ibcon#read 3, iclass 31, count 2 2006.201.14:43:43.02#ibcon#about to read 4, iclass 31, count 2 2006.201.14:43:43.02#ibcon#read 4, iclass 31, count 2 2006.201.14:43:43.02#ibcon#about to read 5, iclass 31, count 2 2006.201.14:43:43.02#ibcon#read 5, iclass 31, count 2 2006.201.14:43:43.02#ibcon#about to read 6, iclass 31, count 2 2006.201.14:43:43.02#ibcon#read 6, iclass 31, count 2 2006.201.14:43:43.02#ibcon#end of sib2, iclass 31, count 2 2006.201.14:43:43.02#ibcon#*mode == 0, iclass 31, count 2 2006.201.14:43:43.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.14:43:43.02#ibcon#[25=AT04-07\r\n] 2006.201.14:43:43.02#ibcon#*before write, iclass 31, count 2 2006.201.14:43:43.02#ibcon#enter sib2, iclass 31, count 2 2006.201.14:43:43.02#ibcon#flushed, iclass 31, count 2 2006.201.14:43:43.02#ibcon#about to write, iclass 31, count 2 2006.201.14:43:43.02#ibcon#wrote, iclass 31, count 2 2006.201.14:43:43.02#ibcon#about to read 3, iclass 31, count 2 2006.201.14:43:43.05#ibcon#read 3, iclass 31, count 2 2006.201.14:43:43.05#ibcon#about to read 4, iclass 31, count 2 2006.201.14:43:43.05#ibcon#read 4, iclass 31, count 2 2006.201.14:43:43.05#ibcon#about to read 5, iclass 31, count 2 2006.201.14:43:43.05#ibcon#read 5, iclass 31, count 2 2006.201.14:43:43.05#ibcon#about to read 6, iclass 31, count 2 2006.201.14:43:43.05#ibcon#read 6, iclass 31, count 2 2006.201.14:43:43.05#ibcon#end of sib2, iclass 31, count 2 2006.201.14:43:43.05#ibcon#*after write, iclass 31, count 2 2006.201.14:43:43.05#ibcon#*before return 0, iclass 31, count 2 2006.201.14:43:43.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:43.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:43.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.14:43:43.05#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:43.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:43.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:43.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:43.17#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:43:43.17#ibcon#first serial, iclass 31, count 0 2006.201.14:43:43.17#ibcon#enter sib2, iclass 31, count 0 2006.201.14:43:43.17#ibcon#flushed, iclass 31, count 0 2006.201.14:43:43.17#ibcon#about to write, iclass 31, count 0 2006.201.14:43:43.17#ibcon#wrote, iclass 31, count 0 2006.201.14:43:43.17#ibcon#about to read 3, iclass 31, count 0 2006.201.14:43:43.19#ibcon#read 3, iclass 31, count 0 2006.201.14:43:43.19#ibcon#about to read 4, iclass 31, count 0 2006.201.14:43:43.19#ibcon#read 4, iclass 31, count 0 2006.201.14:43:43.19#ibcon#about to read 5, iclass 31, count 0 2006.201.14:43:43.19#ibcon#read 5, iclass 31, count 0 2006.201.14:43:43.19#ibcon#about to read 6, iclass 31, count 0 2006.201.14:43:43.19#ibcon#read 6, iclass 31, count 0 2006.201.14:43:43.19#ibcon#end of sib2, iclass 31, count 0 2006.201.14:43:43.19#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:43:43.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:43:43.19#ibcon#[25=USB\r\n] 2006.201.14:43:43.19#ibcon#*before write, iclass 31, count 0 2006.201.14:43:43.19#ibcon#enter sib2, iclass 31, count 0 2006.201.14:43:43.19#ibcon#flushed, iclass 31, count 0 2006.201.14:43:43.19#ibcon#about to write, iclass 31, count 0 2006.201.14:43:43.19#ibcon#wrote, iclass 31, count 0 2006.201.14:43:43.19#ibcon#about to read 3, iclass 31, count 0 2006.201.14:43:43.22#ibcon#read 3, iclass 31, count 0 2006.201.14:43:43.22#ibcon#about to read 4, iclass 31, count 0 2006.201.14:43:43.22#ibcon#read 4, iclass 31, count 0 2006.201.14:43:43.22#ibcon#about to read 5, iclass 31, count 0 2006.201.14:43:43.22#ibcon#read 5, iclass 31, count 0 2006.201.14:43:43.22#ibcon#about to read 6, iclass 31, count 0 2006.201.14:43:43.22#ibcon#read 6, iclass 31, count 0 2006.201.14:43:43.22#ibcon#end of sib2, iclass 31, count 0 2006.201.14:43:43.22#ibcon#*after write, iclass 31, count 0 2006.201.14:43:43.22#ibcon#*before return 0, iclass 31, count 0 2006.201.14:43:43.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:43.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:43.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:43:43.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:43:43.22$vck44/valo=5,734.99 2006.201.14:43:43.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.14:43:43.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.14:43:43.22#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:43.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:43.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:43.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:43.22#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:43:43.22#ibcon#first serial, iclass 33, count 0 2006.201.14:43:43.22#ibcon#enter sib2, iclass 33, count 0 2006.201.14:43:43.22#ibcon#flushed, iclass 33, count 0 2006.201.14:43:43.22#ibcon#about to write, iclass 33, count 0 2006.201.14:43:43.22#ibcon#wrote, iclass 33, count 0 2006.201.14:43:43.22#ibcon#about to read 3, iclass 33, count 0 2006.201.14:43:43.24#ibcon#read 3, iclass 33, count 0 2006.201.14:43:43.24#ibcon#about to read 4, iclass 33, count 0 2006.201.14:43:43.24#ibcon#read 4, iclass 33, count 0 2006.201.14:43:43.24#ibcon#about to read 5, iclass 33, count 0 2006.201.14:43:43.24#ibcon#read 5, iclass 33, count 0 2006.201.14:43:43.24#ibcon#about to read 6, iclass 33, count 0 2006.201.14:43:43.24#ibcon#read 6, iclass 33, count 0 2006.201.14:43:43.24#ibcon#end of sib2, iclass 33, count 0 2006.201.14:43:43.24#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:43:43.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:43:43.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:43:43.24#ibcon#*before write, iclass 33, count 0 2006.201.14:43:43.24#ibcon#enter sib2, iclass 33, count 0 2006.201.14:43:43.24#ibcon#flushed, iclass 33, count 0 2006.201.14:43:43.24#ibcon#about to write, iclass 33, count 0 2006.201.14:43:43.24#ibcon#wrote, iclass 33, count 0 2006.201.14:43:43.24#ibcon#about to read 3, iclass 33, count 0 2006.201.14:43:43.28#ibcon#read 3, iclass 33, count 0 2006.201.14:43:43.28#ibcon#about to read 4, iclass 33, count 0 2006.201.14:43:43.28#ibcon#read 4, iclass 33, count 0 2006.201.14:43:43.28#ibcon#about to read 5, iclass 33, count 0 2006.201.14:43:43.28#ibcon#read 5, iclass 33, count 0 2006.201.14:43:43.28#ibcon#about to read 6, iclass 33, count 0 2006.201.14:43:43.28#ibcon#read 6, iclass 33, count 0 2006.201.14:43:43.28#ibcon#end of sib2, iclass 33, count 0 2006.201.14:43:43.28#ibcon#*after write, iclass 33, count 0 2006.201.14:43:43.28#ibcon#*before return 0, iclass 33, count 0 2006.201.14:43:43.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:43.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:43.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:43:43.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:43:43.28$vck44/va=5,4 2006.201.14:43:43.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.14:43:43.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.14:43:43.28#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:43.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:43.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:43.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:43.34#ibcon#enter wrdev, iclass 35, count 2 2006.201.14:43:43.34#ibcon#first serial, iclass 35, count 2 2006.201.14:43:43.34#ibcon#enter sib2, iclass 35, count 2 2006.201.14:43:43.34#ibcon#flushed, iclass 35, count 2 2006.201.14:43:43.34#ibcon#about to write, iclass 35, count 2 2006.201.14:43:43.34#ibcon#wrote, iclass 35, count 2 2006.201.14:43:43.34#ibcon#about to read 3, iclass 35, count 2 2006.201.14:43:43.36#ibcon#read 3, iclass 35, count 2 2006.201.14:43:43.36#ibcon#about to read 4, iclass 35, count 2 2006.201.14:43:43.36#ibcon#read 4, iclass 35, count 2 2006.201.14:43:43.36#ibcon#about to read 5, iclass 35, count 2 2006.201.14:43:43.36#ibcon#read 5, iclass 35, count 2 2006.201.14:43:43.36#ibcon#about to read 6, iclass 35, count 2 2006.201.14:43:43.36#ibcon#read 6, iclass 35, count 2 2006.201.14:43:43.36#ibcon#end of sib2, iclass 35, count 2 2006.201.14:43:43.36#ibcon#*mode == 0, iclass 35, count 2 2006.201.14:43:43.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.14:43:43.36#ibcon#[25=AT05-04\r\n] 2006.201.14:43:43.36#ibcon#*before write, iclass 35, count 2 2006.201.14:43:43.36#ibcon#enter sib2, iclass 35, count 2 2006.201.14:43:43.36#ibcon#flushed, iclass 35, count 2 2006.201.14:43:43.36#ibcon#about to write, iclass 35, count 2 2006.201.14:43:43.36#ibcon#wrote, iclass 35, count 2 2006.201.14:43:43.36#ibcon#about to read 3, iclass 35, count 2 2006.201.14:43:43.39#ibcon#read 3, iclass 35, count 2 2006.201.14:43:43.39#ibcon#about to read 4, iclass 35, count 2 2006.201.14:43:43.39#ibcon#read 4, iclass 35, count 2 2006.201.14:43:43.39#ibcon#about to read 5, iclass 35, count 2 2006.201.14:43:43.39#ibcon#read 5, iclass 35, count 2 2006.201.14:43:43.39#ibcon#about to read 6, iclass 35, count 2 2006.201.14:43:43.39#ibcon#read 6, iclass 35, count 2 2006.201.14:43:43.39#ibcon#end of sib2, iclass 35, count 2 2006.201.14:43:43.39#ibcon#*after write, iclass 35, count 2 2006.201.14:43:43.39#ibcon#*before return 0, iclass 35, count 2 2006.201.14:43:43.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:43.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:43.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.14:43:43.39#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:43.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:43.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:43.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:43.51#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:43:43.51#ibcon#first serial, iclass 35, count 0 2006.201.14:43:43.51#ibcon#enter sib2, iclass 35, count 0 2006.201.14:43:43.51#ibcon#flushed, iclass 35, count 0 2006.201.14:43:43.51#ibcon#about to write, iclass 35, count 0 2006.201.14:43:43.51#ibcon#wrote, iclass 35, count 0 2006.201.14:43:43.51#ibcon#about to read 3, iclass 35, count 0 2006.201.14:43:43.53#ibcon#read 3, iclass 35, count 0 2006.201.14:43:43.53#ibcon#about to read 4, iclass 35, count 0 2006.201.14:43:43.53#ibcon#read 4, iclass 35, count 0 2006.201.14:43:43.53#ibcon#about to read 5, iclass 35, count 0 2006.201.14:43:43.53#ibcon#read 5, iclass 35, count 0 2006.201.14:43:43.53#ibcon#about to read 6, iclass 35, count 0 2006.201.14:43:43.53#ibcon#read 6, iclass 35, count 0 2006.201.14:43:43.53#ibcon#end of sib2, iclass 35, count 0 2006.201.14:43:43.53#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:43:43.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:43:43.53#ibcon#[25=USB\r\n] 2006.201.14:43:43.53#ibcon#*before write, iclass 35, count 0 2006.201.14:43:43.53#ibcon#enter sib2, iclass 35, count 0 2006.201.14:43:43.53#ibcon#flushed, iclass 35, count 0 2006.201.14:43:43.53#ibcon#about to write, iclass 35, count 0 2006.201.14:43:43.53#ibcon#wrote, iclass 35, count 0 2006.201.14:43:43.53#ibcon#about to read 3, iclass 35, count 0 2006.201.14:43:43.56#ibcon#read 3, iclass 35, count 0 2006.201.14:43:43.56#ibcon#about to read 4, iclass 35, count 0 2006.201.14:43:43.56#ibcon#read 4, iclass 35, count 0 2006.201.14:43:43.56#ibcon#about to read 5, iclass 35, count 0 2006.201.14:43:43.56#ibcon#read 5, iclass 35, count 0 2006.201.14:43:43.56#ibcon#about to read 6, iclass 35, count 0 2006.201.14:43:43.56#ibcon#read 6, iclass 35, count 0 2006.201.14:43:43.56#ibcon#end of sib2, iclass 35, count 0 2006.201.14:43:43.56#ibcon#*after write, iclass 35, count 0 2006.201.14:43:43.56#ibcon#*before return 0, iclass 35, count 0 2006.201.14:43:43.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:43.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:43.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:43:43.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:43:43.56$vck44/valo=6,814.99 2006.201.14:43:43.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.14:43:43.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.14:43:43.56#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:43.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:43.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:43.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:43.56#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:43:43.56#ibcon#first serial, iclass 37, count 0 2006.201.14:43:43.56#ibcon#enter sib2, iclass 37, count 0 2006.201.14:43:43.56#ibcon#flushed, iclass 37, count 0 2006.201.14:43:43.56#ibcon#about to write, iclass 37, count 0 2006.201.14:43:43.56#ibcon#wrote, iclass 37, count 0 2006.201.14:43:43.56#ibcon#about to read 3, iclass 37, count 0 2006.201.14:43:43.58#ibcon#read 3, iclass 37, count 0 2006.201.14:43:43.58#ibcon#about to read 4, iclass 37, count 0 2006.201.14:43:43.58#ibcon#read 4, iclass 37, count 0 2006.201.14:43:43.58#ibcon#about to read 5, iclass 37, count 0 2006.201.14:43:43.58#ibcon#read 5, iclass 37, count 0 2006.201.14:43:43.58#ibcon#about to read 6, iclass 37, count 0 2006.201.14:43:43.58#ibcon#read 6, iclass 37, count 0 2006.201.14:43:43.58#ibcon#end of sib2, iclass 37, count 0 2006.201.14:43:43.58#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:43:43.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:43:43.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:43:43.58#ibcon#*before write, iclass 37, count 0 2006.201.14:43:43.58#ibcon#enter sib2, iclass 37, count 0 2006.201.14:43:43.58#ibcon#flushed, iclass 37, count 0 2006.201.14:43:43.58#ibcon#about to write, iclass 37, count 0 2006.201.14:43:43.58#ibcon#wrote, iclass 37, count 0 2006.201.14:43:43.58#ibcon#about to read 3, iclass 37, count 0 2006.201.14:43:43.62#ibcon#read 3, iclass 37, count 0 2006.201.14:43:43.62#ibcon#about to read 4, iclass 37, count 0 2006.201.14:43:43.62#ibcon#read 4, iclass 37, count 0 2006.201.14:43:43.62#ibcon#about to read 5, iclass 37, count 0 2006.201.14:43:43.62#ibcon#read 5, iclass 37, count 0 2006.201.14:43:43.62#ibcon#about to read 6, iclass 37, count 0 2006.201.14:43:43.62#ibcon#read 6, iclass 37, count 0 2006.201.14:43:43.62#ibcon#end of sib2, iclass 37, count 0 2006.201.14:43:43.62#ibcon#*after write, iclass 37, count 0 2006.201.14:43:43.62#ibcon#*before return 0, iclass 37, count 0 2006.201.14:43:43.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:43.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:43.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:43:43.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:43:43.62$vck44/va=6,5 2006.201.14:43:43.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.14:43:43.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.14:43:43.62#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:43.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:43.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:43.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:43.68#ibcon#enter wrdev, iclass 39, count 2 2006.201.14:43:43.68#ibcon#first serial, iclass 39, count 2 2006.201.14:43:43.68#ibcon#enter sib2, iclass 39, count 2 2006.201.14:43:43.68#ibcon#flushed, iclass 39, count 2 2006.201.14:43:43.68#ibcon#about to write, iclass 39, count 2 2006.201.14:43:43.68#ibcon#wrote, iclass 39, count 2 2006.201.14:43:43.68#ibcon#about to read 3, iclass 39, count 2 2006.201.14:43:43.70#ibcon#read 3, iclass 39, count 2 2006.201.14:43:43.70#ibcon#about to read 4, iclass 39, count 2 2006.201.14:43:43.70#ibcon#read 4, iclass 39, count 2 2006.201.14:43:43.70#ibcon#about to read 5, iclass 39, count 2 2006.201.14:43:43.70#ibcon#read 5, iclass 39, count 2 2006.201.14:43:43.70#ibcon#about to read 6, iclass 39, count 2 2006.201.14:43:43.70#ibcon#read 6, iclass 39, count 2 2006.201.14:43:43.70#ibcon#end of sib2, iclass 39, count 2 2006.201.14:43:43.70#ibcon#*mode == 0, iclass 39, count 2 2006.201.14:43:43.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.14:43:43.70#ibcon#[25=AT06-05\r\n] 2006.201.14:43:43.70#ibcon#*before write, iclass 39, count 2 2006.201.14:43:43.70#ibcon#enter sib2, iclass 39, count 2 2006.201.14:43:43.70#ibcon#flushed, iclass 39, count 2 2006.201.14:43:43.70#ibcon#about to write, iclass 39, count 2 2006.201.14:43:43.70#ibcon#wrote, iclass 39, count 2 2006.201.14:43:43.70#ibcon#about to read 3, iclass 39, count 2 2006.201.14:43:43.73#ibcon#read 3, iclass 39, count 2 2006.201.14:43:43.73#ibcon#about to read 4, iclass 39, count 2 2006.201.14:43:43.73#ibcon#read 4, iclass 39, count 2 2006.201.14:43:43.73#ibcon#about to read 5, iclass 39, count 2 2006.201.14:43:43.73#ibcon#read 5, iclass 39, count 2 2006.201.14:43:43.73#ibcon#about to read 6, iclass 39, count 2 2006.201.14:43:43.73#ibcon#read 6, iclass 39, count 2 2006.201.14:43:43.73#ibcon#end of sib2, iclass 39, count 2 2006.201.14:43:43.73#ibcon#*after write, iclass 39, count 2 2006.201.14:43:43.73#ibcon#*before return 0, iclass 39, count 2 2006.201.14:43:43.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:43.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:43.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.14:43:43.73#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:43.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:43.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:43.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:43.85#ibcon#enter wrdev, iclass 39, count 0 2006.201.14:43:43.85#ibcon#first serial, iclass 39, count 0 2006.201.14:43:43.85#ibcon#enter sib2, iclass 39, count 0 2006.201.14:43:43.85#ibcon#flushed, iclass 39, count 0 2006.201.14:43:43.85#ibcon#about to write, iclass 39, count 0 2006.201.14:43:43.85#ibcon#wrote, iclass 39, count 0 2006.201.14:43:43.85#ibcon#about to read 3, iclass 39, count 0 2006.201.14:43:43.87#ibcon#read 3, iclass 39, count 0 2006.201.14:43:43.87#ibcon#about to read 4, iclass 39, count 0 2006.201.14:43:43.87#ibcon#read 4, iclass 39, count 0 2006.201.14:43:43.87#ibcon#about to read 5, iclass 39, count 0 2006.201.14:43:43.87#ibcon#read 5, iclass 39, count 0 2006.201.14:43:43.87#ibcon#about to read 6, iclass 39, count 0 2006.201.14:43:43.87#ibcon#read 6, iclass 39, count 0 2006.201.14:43:43.87#ibcon#end of sib2, iclass 39, count 0 2006.201.14:43:43.87#ibcon#*mode == 0, iclass 39, count 0 2006.201.14:43:43.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.14:43:43.87#ibcon#[25=USB\r\n] 2006.201.14:43:43.87#ibcon#*before write, iclass 39, count 0 2006.201.14:43:43.87#ibcon#enter sib2, iclass 39, count 0 2006.201.14:43:43.87#ibcon#flushed, iclass 39, count 0 2006.201.14:43:43.87#ibcon#about to write, iclass 39, count 0 2006.201.14:43:43.87#ibcon#wrote, iclass 39, count 0 2006.201.14:43:43.87#ibcon#about to read 3, iclass 39, count 0 2006.201.14:43:43.90#ibcon#read 3, iclass 39, count 0 2006.201.14:43:43.90#ibcon#about to read 4, iclass 39, count 0 2006.201.14:43:43.90#ibcon#read 4, iclass 39, count 0 2006.201.14:43:43.90#ibcon#about to read 5, iclass 39, count 0 2006.201.14:43:43.90#ibcon#read 5, iclass 39, count 0 2006.201.14:43:43.90#ibcon#about to read 6, iclass 39, count 0 2006.201.14:43:43.90#ibcon#read 6, iclass 39, count 0 2006.201.14:43:43.90#ibcon#end of sib2, iclass 39, count 0 2006.201.14:43:43.90#ibcon#*after write, iclass 39, count 0 2006.201.14:43:43.90#ibcon#*before return 0, iclass 39, count 0 2006.201.14:43:43.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:43.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:43.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.14:43:43.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.14:43:43.90$vck44/valo=7,864.99 2006.201.14:43:43.90#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.14:43:43.90#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.14:43:43.90#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:43.90#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:43.90#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:43.90#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:43.90#ibcon#enter wrdev, iclass 2, count 0 2006.201.14:43:43.90#ibcon#first serial, iclass 2, count 0 2006.201.14:43:43.90#ibcon#enter sib2, iclass 2, count 0 2006.201.14:43:43.90#ibcon#flushed, iclass 2, count 0 2006.201.14:43:43.90#ibcon#about to write, iclass 2, count 0 2006.201.14:43:43.90#ibcon#wrote, iclass 2, count 0 2006.201.14:43:43.90#ibcon#about to read 3, iclass 2, count 0 2006.201.14:43:43.92#ibcon#read 3, iclass 2, count 0 2006.201.14:43:43.92#ibcon#about to read 4, iclass 2, count 0 2006.201.14:43:43.92#ibcon#read 4, iclass 2, count 0 2006.201.14:43:43.92#ibcon#about to read 5, iclass 2, count 0 2006.201.14:43:43.92#ibcon#read 5, iclass 2, count 0 2006.201.14:43:43.92#ibcon#about to read 6, iclass 2, count 0 2006.201.14:43:43.92#ibcon#read 6, iclass 2, count 0 2006.201.14:43:43.92#ibcon#end of sib2, iclass 2, count 0 2006.201.14:43:43.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.14:43:43.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.14:43:43.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:43:43.92#ibcon#*before write, iclass 2, count 0 2006.201.14:43:43.92#ibcon#enter sib2, iclass 2, count 0 2006.201.14:43:43.92#ibcon#flushed, iclass 2, count 0 2006.201.14:43:43.92#ibcon#about to write, iclass 2, count 0 2006.201.14:43:43.92#ibcon#wrote, iclass 2, count 0 2006.201.14:43:43.92#ibcon#about to read 3, iclass 2, count 0 2006.201.14:43:43.96#ibcon#read 3, iclass 2, count 0 2006.201.14:43:43.96#ibcon#about to read 4, iclass 2, count 0 2006.201.14:43:43.96#ibcon#read 4, iclass 2, count 0 2006.201.14:43:43.96#ibcon#about to read 5, iclass 2, count 0 2006.201.14:43:43.96#ibcon#read 5, iclass 2, count 0 2006.201.14:43:43.96#ibcon#about to read 6, iclass 2, count 0 2006.201.14:43:43.96#ibcon#read 6, iclass 2, count 0 2006.201.14:43:43.96#ibcon#end of sib2, iclass 2, count 0 2006.201.14:43:43.96#ibcon#*after write, iclass 2, count 0 2006.201.14:43:43.96#ibcon#*before return 0, iclass 2, count 0 2006.201.14:43:43.96#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:43.96#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:43.96#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.14:43:43.96#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.14:43:43.96$vck44/va=7,5 2006.201.14:43:43.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.14:43:43.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.14:43:43.96#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:43.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:44.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:44.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:44.02#ibcon#enter wrdev, iclass 5, count 2 2006.201.14:43:44.02#ibcon#first serial, iclass 5, count 2 2006.201.14:43:44.02#ibcon#enter sib2, iclass 5, count 2 2006.201.14:43:44.02#ibcon#flushed, iclass 5, count 2 2006.201.14:43:44.02#ibcon#about to write, iclass 5, count 2 2006.201.14:43:44.02#ibcon#wrote, iclass 5, count 2 2006.201.14:43:44.02#ibcon#about to read 3, iclass 5, count 2 2006.201.14:43:44.04#ibcon#read 3, iclass 5, count 2 2006.201.14:43:44.04#ibcon#about to read 4, iclass 5, count 2 2006.201.14:43:44.04#ibcon#read 4, iclass 5, count 2 2006.201.14:43:44.04#ibcon#about to read 5, iclass 5, count 2 2006.201.14:43:44.04#ibcon#read 5, iclass 5, count 2 2006.201.14:43:44.04#ibcon#about to read 6, iclass 5, count 2 2006.201.14:43:44.04#ibcon#read 6, iclass 5, count 2 2006.201.14:43:44.04#ibcon#end of sib2, iclass 5, count 2 2006.201.14:43:44.04#ibcon#*mode == 0, iclass 5, count 2 2006.201.14:43:44.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.14:43:44.04#ibcon#[25=AT07-05\r\n] 2006.201.14:43:44.04#ibcon#*before write, iclass 5, count 2 2006.201.14:43:44.04#ibcon#enter sib2, iclass 5, count 2 2006.201.14:43:44.04#ibcon#flushed, iclass 5, count 2 2006.201.14:43:44.04#ibcon#about to write, iclass 5, count 2 2006.201.14:43:44.04#ibcon#wrote, iclass 5, count 2 2006.201.14:43:44.04#ibcon#about to read 3, iclass 5, count 2 2006.201.14:43:44.07#ibcon#read 3, iclass 5, count 2 2006.201.14:43:44.07#ibcon#about to read 4, iclass 5, count 2 2006.201.14:43:44.07#ibcon#read 4, iclass 5, count 2 2006.201.14:43:44.07#ibcon#about to read 5, iclass 5, count 2 2006.201.14:43:44.07#ibcon#read 5, iclass 5, count 2 2006.201.14:43:44.07#ibcon#about to read 6, iclass 5, count 2 2006.201.14:43:44.07#ibcon#read 6, iclass 5, count 2 2006.201.14:43:44.07#ibcon#end of sib2, iclass 5, count 2 2006.201.14:43:44.07#ibcon#*after write, iclass 5, count 2 2006.201.14:43:44.07#ibcon#*before return 0, iclass 5, count 2 2006.201.14:43:44.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:44.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:44.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.14:43:44.07#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:44.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:44.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:44.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:44.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:43:44.19#ibcon#first serial, iclass 5, count 0 2006.201.14:43:44.19#ibcon#enter sib2, iclass 5, count 0 2006.201.14:43:44.19#ibcon#flushed, iclass 5, count 0 2006.201.14:43:44.19#ibcon#about to write, iclass 5, count 0 2006.201.14:43:44.19#ibcon#wrote, iclass 5, count 0 2006.201.14:43:44.19#ibcon#about to read 3, iclass 5, count 0 2006.201.14:43:44.21#ibcon#read 3, iclass 5, count 0 2006.201.14:43:44.21#ibcon#about to read 4, iclass 5, count 0 2006.201.14:43:44.21#ibcon#read 4, iclass 5, count 0 2006.201.14:43:44.21#ibcon#about to read 5, iclass 5, count 0 2006.201.14:43:44.21#ibcon#read 5, iclass 5, count 0 2006.201.14:43:44.21#ibcon#about to read 6, iclass 5, count 0 2006.201.14:43:44.21#ibcon#read 6, iclass 5, count 0 2006.201.14:43:44.21#ibcon#end of sib2, iclass 5, count 0 2006.201.14:43:44.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:43:44.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:43:44.21#ibcon#[25=USB\r\n] 2006.201.14:43:44.21#ibcon#*before write, iclass 5, count 0 2006.201.14:43:44.21#ibcon#enter sib2, iclass 5, count 0 2006.201.14:43:44.21#ibcon#flushed, iclass 5, count 0 2006.201.14:43:44.21#ibcon#about to write, iclass 5, count 0 2006.201.14:43:44.21#ibcon#wrote, iclass 5, count 0 2006.201.14:43:44.21#ibcon#about to read 3, iclass 5, count 0 2006.201.14:43:44.24#ibcon#read 3, iclass 5, count 0 2006.201.14:43:44.24#ibcon#about to read 4, iclass 5, count 0 2006.201.14:43:44.24#ibcon#read 4, iclass 5, count 0 2006.201.14:43:44.24#ibcon#about to read 5, iclass 5, count 0 2006.201.14:43:44.24#ibcon#read 5, iclass 5, count 0 2006.201.14:43:44.24#ibcon#about to read 6, iclass 5, count 0 2006.201.14:43:44.24#ibcon#read 6, iclass 5, count 0 2006.201.14:43:44.24#ibcon#end of sib2, iclass 5, count 0 2006.201.14:43:44.24#ibcon#*after write, iclass 5, count 0 2006.201.14:43:44.24#ibcon#*before return 0, iclass 5, count 0 2006.201.14:43:44.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:44.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:44.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:43:44.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:43:44.24$vck44/valo=8,884.99 2006.201.14:43:44.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.14:43:44.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.14:43:44.24#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:44.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:44.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:44.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:44.24#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:43:44.24#ibcon#first serial, iclass 7, count 0 2006.201.14:43:44.24#ibcon#enter sib2, iclass 7, count 0 2006.201.14:43:44.24#ibcon#flushed, iclass 7, count 0 2006.201.14:43:44.24#ibcon#about to write, iclass 7, count 0 2006.201.14:43:44.24#ibcon#wrote, iclass 7, count 0 2006.201.14:43:44.24#ibcon#about to read 3, iclass 7, count 0 2006.201.14:43:44.26#ibcon#read 3, iclass 7, count 0 2006.201.14:43:44.26#ibcon#about to read 4, iclass 7, count 0 2006.201.14:43:44.26#ibcon#read 4, iclass 7, count 0 2006.201.14:43:44.26#ibcon#about to read 5, iclass 7, count 0 2006.201.14:43:44.26#ibcon#read 5, iclass 7, count 0 2006.201.14:43:44.26#ibcon#about to read 6, iclass 7, count 0 2006.201.14:43:44.26#ibcon#read 6, iclass 7, count 0 2006.201.14:43:44.26#ibcon#end of sib2, iclass 7, count 0 2006.201.14:43:44.26#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:43:44.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:43:44.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:43:44.26#ibcon#*before write, iclass 7, count 0 2006.201.14:43:44.26#ibcon#enter sib2, iclass 7, count 0 2006.201.14:43:44.26#ibcon#flushed, iclass 7, count 0 2006.201.14:43:44.26#ibcon#about to write, iclass 7, count 0 2006.201.14:43:44.26#ibcon#wrote, iclass 7, count 0 2006.201.14:43:44.26#ibcon#about to read 3, iclass 7, count 0 2006.201.14:43:44.30#ibcon#read 3, iclass 7, count 0 2006.201.14:43:44.30#ibcon#about to read 4, iclass 7, count 0 2006.201.14:43:44.30#ibcon#read 4, iclass 7, count 0 2006.201.14:43:44.30#ibcon#about to read 5, iclass 7, count 0 2006.201.14:43:44.30#ibcon#read 5, iclass 7, count 0 2006.201.14:43:44.30#ibcon#about to read 6, iclass 7, count 0 2006.201.14:43:44.30#ibcon#read 6, iclass 7, count 0 2006.201.14:43:44.30#ibcon#end of sib2, iclass 7, count 0 2006.201.14:43:44.30#ibcon#*after write, iclass 7, count 0 2006.201.14:43:44.30#ibcon#*before return 0, iclass 7, count 0 2006.201.14:43:44.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:44.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:44.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:43:44.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:43:44.30$vck44/va=8,4 2006.201.14:43:44.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.14:43:44.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.14:43:44.30#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:44.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:43:44.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:43:44.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:43:44.36#ibcon#enter wrdev, iclass 11, count 2 2006.201.14:43:44.36#ibcon#first serial, iclass 11, count 2 2006.201.14:43:44.36#ibcon#enter sib2, iclass 11, count 2 2006.201.14:43:44.36#ibcon#flushed, iclass 11, count 2 2006.201.14:43:44.36#ibcon#about to write, iclass 11, count 2 2006.201.14:43:44.36#ibcon#wrote, iclass 11, count 2 2006.201.14:43:44.36#ibcon#about to read 3, iclass 11, count 2 2006.201.14:43:44.38#ibcon#read 3, iclass 11, count 2 2006.201.14:43:44.38#ibcon#about to read 4, iclass 11, count 2 2006.201.14:43:44.38#ibcon#read 4, iclass 11, count 2 2006.201.14:43:44.38#ibcon#about to read 5, iclass 11, count 2 2006.201.14:43:44.38#ibcon#read 5, iclass 11, count 2 2006.201.14:43:44.38#ibcon#about to read 6, iclass 11, count 2 2006.201.14:43:44.38#ibcon#read 6, iclass 11, count 2 2006.201.14:43:44.38#ibcon#end of sib2, iclass 11, count 2 2006.201.14:43:44.38#ibcon#*mode == 0, iclass 11, count 2 2006.201.14:43:44.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.14:43:44.38#ibcon#[25=AT08-04\r\n] 2006.201.14:43:44.38#ibcon#*before write, iclass 11, count 2 2006.201.14:43:44.38#ibcon#enter sib2, iclass 11, count 2 2006.201.14:43:44.38#ibcon#flushed, iclass 11, count 2 2006.201.14:43:44.38#ibcon#about to write, iclass 11, count 2 2006.201.14:43:44.38#ibcon#wrote, iclass 11, count 2 2006.201.14:43:44.38#ibcon#about to read 3, iclass 11, count 2 2006.201.14:43:44.41#ibcon#read 3, iclass 11, count 2 2006.201.14:43:44.41#ibcon#about to read 4, iclass 11, count 2 2006.201.14:43:44.41#ibcon#read 4, iclass 11, count 2 2006.201.14:43:44.41#ibcon#about to read 5, iclass 11, count 2 2006.201.14:43:44.41#ibcon#read 5, iclass 11, count 2 2006.201.14:43:44.41#ibcon#about to read 6, iclass 11, count 2 2006.201.14:43:44.41#ibcon#read 6, iclass 11, count 2 2006.201.14:43:44.41#ibcon#end of sib2, iclass 11, count 2 2006.201.14:43:44.41#ibcon#*after write, iclass 11, count 2 2006.201.14:43:44.41#ibcon#*before return 0, iclass 11, count 2 2006.201.14:43:44.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:43:44.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.14:43:44.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.14:43:44.41#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:44.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:43:44.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:43:44.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:43:44.53#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:43:44.53#ibcon#first serial, iclass 11, count 0 2006.201.14:43:44.53#ibcon#enter sib2, iclass 11, count 0 2006.201.14:43:44.53#ibcon#flushed, iclass 11, count 0 2006.201.14:43:44.53#ibcon#about to write, iclass 11, count 0 2006.201.14:43:44.53#ibcon#wrote, iclass 11, count 0 2006.201.14:43:44.53#ibcon#about to read 3, iclass 11, count 0 2006.201.14:43:44.55#ibcon#read 3, iclass 11, count 0 2006.201.14:43:44.55#ibcon#about to read 4, iclass 11, count 0 2006.201.14:43:44.55#ibcon#read 4, iclass 11, count 0 2006.201.14:43:44.55#ibcon#about to read 5, iclass 11, count 0 2006.201.14:43:44.55#ibcon#read 5, iclass 11, count 0 2006.201.14:43:44.55#ibcon#about to read 6, iclass 11, count 0 2006.201.14:43:44.55#ibcon#read 6, iclass 11, count 0 2006.201.14:43:44.55#ibcon#end of sib2, iclass 11, count 0 2006.201.14:43:44.55#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:43:44.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:43:44.55#ibcon#[25=USB\r\n] 2006.201.14:43:44.55#ibcon#*before write, iclass 11, count 0 2006.201.14:43:44.55#ibcon#enter sib2, iclass 11, count 0 2006.201.14:43:44.55#ibcon#flushed, iclass 11, count 0 2006.201.14:43:44.55#ibcon#about to write, iclass 11, count 0 2006.201.14:43:44.55#ibcon#wrote, iclass 11, count 0 2006.201.14:43:44.55#ibcon#about to read 3, iclass 11, count 0 2006.201.14:43:44.58#ibcon#read 3, iclass 11, count 0 2006.201.14:43:44.58#ibcon#about to read 4, iclass 11, count 0 2006.201.14:43:44.58#ibcon#read 4, iclass 11, count 0 2006.201.14:43:44.58#ibcon#about to read 5, iclass 11, count 0 2006.201.14:43:44.58#ibcon#read 5, iclass 11, count 0 2006.201.14:43:44.58#ibcon#about to read 6, iclass 11, count 0 2006.201.14:43:44.58#ibcon#read 6, iclass 11, count 0 2006.201.14:43:44.58#ibcon#end of sib2, iclass 11, count 0 2006.201.14:43:44.58#ibcon#*after write, iclass 11, count 0 2006.201.14:43:44.58#ibcon#*before return 0, iclass 11, count 0 2006.201.14:43:44.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:43:44.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.14:43:44.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:43:44.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:43:44.58$vck44/vblo=1,629.99 2006.201.14:43:44.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.14:43:44.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.14:43:44.58#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:44.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:44.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:44.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:44.58#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:43:44.58#ibcon#first serial, iclass 13, count 0 2006.201.14:43:44.58#ibcon#enter sib2, iclass 13, count 0 2006.201.14:43:44.58#ibcon#flushed, iclass 13, count 0 2006.201.14:43:44.58#ibcon#about to write, iclass 13, count 0 2006.201.14:43:44.58#ibcon#wrote, iclass 13, count 0 2006.201.14:43:44.58#ibcon#about to read 3, iclass 13, count 0 2006.201.14:43:44.60#ibcon#read 3, iclass 13, count 0 2006.201.14:43:44.60#ibcon#about to read 4, iclass 13, count 0 2006.201.14:43:44.60#ibcon#read 4, iclass 13, count 0 2006.201.14:43:44.60#ibcon#about to read 5, iclass 13, count 0 2006.201.14:43:44.60#ibcon#read 5, iclass 13, count 0 2006.201.14:43:44.60#ibcon#about to read 6, iclass 13, count 0 2006.201.14:43:44.60#ibcon#read 6, iclass 13, count 0 2006.201.14:43:44.60#ibcon#end of sib2, iclass 13, count 0 2006.201.14:43:44.60#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:43:44.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:43:44.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:43:44.60#ibcon#*before write, iclass 13, count 0 2006.201.14:43:44.60#ibcon#enter sib2, iclass 13, count 0 2006.201.14:43:44.60#ibcon#flushed, iclass 13, count 0 2006.201.14:43:44.60#ibcon#about to write, iclass 13, count 0 2006.201.14:43:44.60#ibcon#wrote, iclass 13, count 0 2006.201.14:43:44.60#ibcon#about to read 3, iclass 13, count 0 2006.201.14:43:44.64#ibcon#read 3, iclass 13, count 0 2006.201.14:43:44.64#ibcon#about to read 4, iclass 13, count 0 2006.201.14:43:44.64#ibcon#read 4, iclass 13, count 0 2006.201.14:43:44.64#ibcon#about to read 5, iclass 13, count 0 2006.201.14:43:44.64#ibcon#read 5, iclass 13, count 0 2006.201.14:43:44.64#ibcon#about to read 6, iclass 13, count 0 2006.201.14:43:44.64#ibcon#read 6, iclass 13, count 0 2006.201.14:43:44.64#ibcon#end of sib2, iclass 13, count 0 2006.201.14:43:44.64#ibcon#*after write, iclass 13, count 0 2006.201.14:43:44.64#ibcon#*before return 0, iclass 13, count 0 2006.201.14:43:44.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:44.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.14:43:44.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:43:44.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:43:44.64$vck44/vb=1,4 2006.201.14:43:44.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.14:43:44.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.14:43:44.64#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:44.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:44.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:44.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:44.64#ibcon#enter wrdev, iclass 15, count 2 2006.201.14:43:44.64#ibcon#first serial, iclass 15, count 2 2006.201.14:43:44.64#ibcon#enter sib2, iclass 15, count 2 2006.201.14:43:44.64#ibcon#flushed, iclass 15, count 2 2006.201.14:43:44.64#ibcon#about to write, iclass 15, count 2 2006.201.14:43:44.64#ibcon#wrote, iclass 15, count 2 2006.201.14:43:44.64#ibcon#about to read 3, iclass 15, count 2 2006.201.14:43:44.66#ibcon#read 3, iclass 15, count 2 2006.201.14:43:44.66#ibcon#about to read 4, iclass 15, count 2 2006.201.14:43:44.66#ibcon#read 4, iclass 15, count 2 2006.201.14:43:44.66#ibcon#about to read 5, iclass 15, count 2 2006.201.14:43:44.66#ibcon#read 5, iclass 15, count 2 2006.201.14:43:44.66#ibcon#about to read 6, iclass 15, count 2 2006.201.14:43:44.66#ibcon#read 6, iclass 15, count 2 2006.201.14:43:44.66#ibcon#end of sib2, iclass 15, count 2 2006.201.14:43:44.66#ibcon#*mode == 0, iclass 15, count 2 2006.201.14:43:44.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.14:43:44.66#ibcon#[27=AT01-04\r\n] 2006.201.14:43:44.66#ibcon#*before write, iclass 15, count 2 2006.201.14:43:44.66#ibcon#enter sib2, iclass 15, count 2 2006.201.14:43:44.66#ibcon#flushed, iclass 15, count 2 2006.201.14:43:44.66#ibcon#about to write, iclass 15, count 2 2006.201.14:43:44.66#ibcon#wrote, iclass 15, count 2 2006.201.14:43:44.66#ibcon#about to read 3, iclass 15, count 2 2006.201.14:43:44.69#ibcon#read 3, iclass 15, count 2 2006.201.14:43:44.69#ibcon#about to read 4, iclass 15, count 2 2006.201.14:43:44.69#ibcon#read 4, iclass 15, count 2 2006.201.14:43:44.69#ibcon#about to read 5, iclass 15, count 2 2006.201.14:43:44.69#ibcon#read 5, iclass 15, count 2 2006.201.14:43:44.69#ibcon#about to read 6, iclass 15, count 2 2006.201.14:43:44.69#ibcon#read 6, iclass 15, count 2 2006.201.14:43:44.69#ibcon#end of sib2, iclass 15, count 2 2006.201.14:43:44.69#ibcon#*after write, iclass 15, count 2 2006.201.14:43:44.69#ibcon#*before return 0, iclass 15, count 2 2006.201.14:43:44.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:44.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.14:43:44.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.14:43:44.69#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:44.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:44.81#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:44.81#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:44.81#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:43:44.81#ibcon#first serial, iclass 15, count 0 2006.201.14:43:44.81#ibcon#enter sib2, iclass 15, count 0 2006.201.14:43:44.81#ibcon#flushed, iclass 15, count 0 2006.201.14:43:44.81#ibcon#about to write, iclass 15, count 0 2006.201.14:43:44.81#ibcon#wrote, iclass 15, count 0 2006.201.14:43:44.81#ibcon#about to read 3, iclass 15, count 0 2006.201.14:43:44.83#ibcon#read 3, iclass 15, count 0 2006.201.14:43:44.83#ibcon#about to read 4, iclass 15, count 0 2006.201.14:43:44.83#ibcon#read 4, iclass 15, count 0 2006.201.14:43:44.83#ibcon#about to read 5, iclass 15, count 0 2006.201.14:43:44.83#ibcon#read 5, iclass 15, count 0 2006.201.14:43:44.83#ibcon#about to read 6, iclass 15, count 0 2006.201.14:43:44.83#ibcon#read 6, iclass 15, count 0 2006.201.14:43:44.83#ibcon#end of sib2, iclass 15, count 0 2006.201.14:43:44.83#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:43:44.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:43:44.83#ibcon#[27=USB\r\n] 2006.201.14:43:44.83#ibcon#*before write, iclass 15, count 0 2006.201.14:43:44.83#ibcon#enter sib2, iclass 15, count 0 2006.201.14:43:44.83#ibcon#flushed, iclass 15, count 0 2006.201.14:43:44.83#ibcon#about to write, iclass 15, count 0 2006.201.14:43:44.83#ibcon#wrote, iclass 15, count 0 2006.201.14:43:44.83#ibcon#about to read 3, iclass 15, count 0 2006.201.14:43:44.86#ibcon#read 3, iclass 15, count 0 2006.201.14:43:44.86#ibcon#about to read 4, iclass 15, count 0 2006.201.14:43:44.86#ibcon#read 4, iclass 15, count 0 2006.201.14:43:44.86#ibcon#about to read 5, iclass 15, count 0 2006.201.14:43:44.86#ibcon#read 5, iclass 15, count 0 2006.201.14:43:44.86#ibcon#about to read 6, iclass 15, count 0 2006.201.14:43:44.86#ibcon#read 6, iclass 15, count 0 2006.201.14:43:44.86#ibcon#end of sib2, iclass 15, count 0 2006.201.14:43:44.86#ibcon#*after write, iclass 15, count 0 2006.201.14:43:44.86#ibcon#*before return 0, iclass 15, count 0 2006.201.14:43:44.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:44.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.14:43:44.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:43:44.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:43:44.86$vck44/vblo=2,634.99 2006.201.14:43:44.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.14:43:44.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.14:43:44.86#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:44.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:44.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:44.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:44.86#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:43:44.86#ibcon#first serial, iclass 17, count 0 2006.201.14:43:44.86#ibcon#enter sib2, iclass 17, count 0 2006.201.14:43:44.86#ibcon#flushed, iclass 17, count 0 2006.201.14:43:44.86#ibcon#about to write, iclass 17, count 0 2006.201.14:43:44.86#ibcon#wrote, iclass 17, count 0 2006.201.14:43:44.86#ibcon#about to read 3, iclass 17, count 0 2006.201.14:43:44.88#ibcon#read 3, iclass 17, count 0 2006.201.14:43:44.88#ibcon#about to read 4, iclass 17, count 0 2006.201.14:43:44.88#ibcon#read 4, iclass 17, count 0 2006.201.14:43:44.88#ibcon#about to read 5, iclass 17, count 0 2006.201.14:43:44.88#ibcon#read 5, iclass 17, count 0 2006.201.14:43:44.88#ibcon#about to read 6, iclass 17, count 0 2006.201.14:43:44.88#ibcon#read 6, iclass 17, count 0 2006.201.14:43:44.88#ibcon#end of sib2, iclass 17, count 0 2006.201.14:43:44.88#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:43:44.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:43:44.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:43:44.88#ibcon#*before write, iclass 17, count 0 2006.201.14:43:44.88#ibcon#enter sib2, iclass 17, count 0 2006.201.14:43:44.88#ibcon#flushed, iclass 17, count 0 2006.201.14:43:44.88#ibcon#about to write, iclass 17, count 0 2006.201.14:43:44.88#ibcon#wrote, iclass 17, count 0 2006.201.14:43:44.88#ibcon#about to read 3, iclass 17, count 0 2006.201.14:43:44.92#ibcon#read 3, iclass 17, count 0 2006.201.14:43:44.92#ibcon#about to read 4, iclass 17, count 0 2006.201.14:43:44.92#ibcon#read 4, iclass 17, count 0 2006.201.14:43:44.92#ibcon#about to read 5, iclass 17, count 0 2006.201.14:43:44.92#ibcon#read 5, iclass 17, count 0 2006.201.14:43:44.92#ibcon#about to read 6, iclass 17, count 0 2006.201.14:43:44.92#ibcon#read 6, iclass 17, count 0 2006.201.14:43:44.92#ibcon#end of sib2, iclass 17, count 0 2006.201.14:43:44.92#ibcon#*after write, iclass 17, count 0 2006.201.14:43:44.92#ibcon#*before return 0, iclass 17, count 0 2006.201.14:43:44.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:44.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.14:43:44.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:43:44.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:43:44.92$vck44/vb=2,5 2006.201.14:43:44.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.14:43:44.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.14:43:44.92#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:44.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:44.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:44.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:44.98#ibcon#enter wrdev, iclass 19, count 2 2006.201.14:43:44.98#ibcon#first serial, iclass 19, count 2 2006.201.14:43:44.98#ibcon#enter sib2, iclass 19, count 2 2006.201.14:43:44.98#ibcon#flushed, iclass 19, count 2 2006.201.14:43:44.98#ibcon#about to write, iclass 19, count 2 2006.201.14:43:44.98#ibcon#wrote, iclass 19, count 2 2006.201.14:43:44.98#ibcon#about to read 3, iclass 19, count 2 2006.201.14:43:45.00#ibcon#read 3, iclass 19, count 2 2006.201.14:43:45.00#ibcon#about to read 4, iclass 19, count 2 2006.201.14:43:45.00#ibcon#read 4, iclass 19, count 2 2006.201.14:43:45.00#ibcon#about to read 5, iclass 19, count 2 2006.201.14:43:45.00#ibcon#read 5, iclass 19, count 2 2006.201.14:43:45.00#ibcon#about to read 6, iclass 19, count 2 2006.201.14:43:45.00#ibcon#read 6, iclass 19, count 2 2006.201.14:43:45.00#ibcon#end of sib2, iclass 19, count 2 2006.201.14:43:45.00#ibcon#*mode == 0, iclass 19, count 2 2006.201.14:43:45.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.14:43:45.00#ibcon#[27=AT02-05\r\n] 2006.201.14:43:45.00#ibcon#*before write, iclass 19, count 2 2006.201.14:43:45.00#ibcon#enter sib2, iclass 19, count 2 2006.201.14:43:45.00#ibcon#flushed, iclass 19, count 2 2006.201.14:43:45.00#ibcon#about to write, iclass 19, count 2 2006.201.14:43:45.00#ibcon#wrote, iclass 19, count 2 2006.201.14:43:45.00#ibcon#about to read 3, iclass 19, count 2 2006.201.14:43:45.03#ibcon#read 3, iclass 19, count 2 2006.201.14:43:45.03#ibcon#about to read 4, iclass 19, count 2 2006.201.14:43:45.03#ibcon#read 4, iclass 19, count 2 2006.201.14:43:45.03#ibcon#about to read 5, iclass 19, count 2 2006.201.14:43:45.03#ibcon#read 5, iclass 19, count 2 2006.201.14:43:45.03#ibcon#about to read 6, iclass 19, count 2 2006.201.14:43:45.03#ibcon#read 6, iclass 19, count 2 2006.201.14:43:45.03#ibcon#end of sib2, iclass 19, count 2 2006.201.14:43:45.03#ibcon#*after write, iclass 19, count 2 2006.201.14:43:45.03#ibcon#*before return 0, iclass 19, count 2 2006.201.14:43:45.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:45.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.14:43:45.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.14:43:45.03#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:45.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:45.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:45.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:45.15#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:43:45.15#ibcon#first serial, iclass 19, count 0 2006.201.14:43:45.15#ibcon#enter sib2, iclass 19, count 0 2006.201.14:43:45.15#ibcon#flushed, iclass 19, count 0 2006.201.14:43:45.15#ibcon#about to write, iclass 19, count 0 2006.201.14:43:45.15#ibcon#wrote, iclass 19, count 0 2006.201.14:43:45.15#ibcon#about to read 3, iclass 19, count 0 2006.201.14:43:45.17#ibcon#read 3, iclass 19, count 0 2006.201.14:43:45.17#ibcon#about to read 4, iclass 19, count 0 2006.201.14:43:45.17#ibcon#read 4, iclass 19, count 0 2006.201.14:43:45.17#ibcon#about to read 5, iclass 19, count 0 2006.201.14:43:45.17#ibcon#read 5, iclass 19, count 0 2006.201.14:43:45.17#ibcon#about to read 6, iclass 19, count 0 2006.201.14:43:45.17#ibcon#read 6, iclass 19, count 0 2006.201.14:43:45.17#ibcon#end of sib2, iclass 19, count 0 2006.201.14:43:45.17#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:43:45.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:43:45.17#ibcon#[27=USB\r\n] 2006.201.14:43:45.17#ibcon#*before write, iclass 19, count 0 2006.201.14:43:45.17#ibcon#enter sib2, iclass 19, count 0 2006.201.14:43:45.17#ibcon#flushed, iclass 19, count 0 2006.201.14:43:45.17#ibcon#about to write, iclass 19, count 0 2006.201.14:43:45.17#ibcon#wrote, iclass 19, count 0 2006.201.14:43:45.17#ibcon#about to read 3, iclass 19, count 0 2006.201.14:43:45.20#ibcon#read 3, iclass 19, count 0 2006.201.14:43:45.20#ibcon#about to read 4, iclass 19, count 0 2006.201.14:43:45.20#ibcon#read 4, iclass 19, count 0 2006.201.14:43:45.20#ibcon#about to read 5, iclass 19, count 0 2006.201.14:43:45.20#ibcon#read 5, iclass 19, count 0 2006.201.14:43:45.20#ibcon#about to read 6, iclass 19, count 0 2006.201.14:43:45.20#ibcon#read 6, iclass 19, count 0 2006.201.14:43:45.20#ibcon#end of sib2, iclass 19, count 0 2006.201.14:43:45.20#ibcon#*after write, iclass 19, count 0 2006.201.14:43:45.20#ibcon#*before return 0, iclass 19, count 0 2006.201.14:43:45.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:45.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.14:43:45.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:43:45.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:43:45.20$vck44/vblo=3,649.99 2006.201.14:43:45.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.14:43:45.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.14:43:45.20#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:45.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:45.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:45.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:45.20#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:43:45.20#ibcon#first serial, iclass 21, count 0 2006.201.14:43:45.20#ibcon#enter sib2, iclass 21, count 0 2006.201.14:43:45.20#ibcon#flushed, iclass 21, count 0 2006.201.14:43:45.20#ibcon#about to write, iclass 21, count 0 2006.201.14:43:45.20#ibcon#wrote, iclass 21, count 0 2006.201.14:43:45.20#ibcon#about to read 3, iclass 21, count 0 2006.201.14:43:45.22#ibcon#read 3, iclass 21, count 0 2006.201.14:43:45.22#ibcon#about to read 4, iclass 21, count 0 2006.201.14:43:45.22#ibcon#read 4, iclass 21, count 0 2006.201.14:43:45.22#ibcon#about to read 5, iclass 21, count 0 2006.201.14:43:45.22#ibcon#read 5, iclass 21, count 0 2006.201.14:43:45.22#ibcon#about to read 6, iclass 21, count 0 2006.201.14:43:45.22#ibcon#read 6, iclass 21, count 0 2006.201.14:43:45.22#ibcon#end of sib2, iclass 21, count 0 2006.201.14:43:45.22#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:43:45.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:43:45.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:43:45.22#ibcon#*before write, iclass 21, count 0 2006.201.14:43:45.22#ibcon#enter sib2, iclass 21, count 0 2006.201.14:43:45.22#ibcon#flushed, iclass 21, count 0 2006.201.14:43:45.22#ibcon#about to write, iclass 21, count 0 2006.201.14:43:45.22#ibcon#wrote, iclass 21, count 0 2006.201.14:43:45.22#ibcon#about to read 3, iclass 21, count 0 2006.201.14:43:45.26#ibcon#read 3, iclass 21, count 0 2006.201.14:43:45.26#ibcon#about to read 4, iclass 21, count 0 2006.201.14:43:45.26#ibcon#read 4, iclass 21, count 0 2006.201.14:43:45.26#ibcon#about to read 5, iclass 21, count 0 2006.201.14:43:45.26#ibcon#read 5, iclass 21, count 0 2006.201.14:43:45.26#ibcon#about to read 6, iclass 21, count 0 2006.201.14:43:45.26#ibcon#read 6, iclass 21, count 0 2006.201.14:43:45.26#ibcon#end of sib2, iclass 21, count 0 2006.201.14:43:45.26#ibcon#*after write, iclass 21, count 0 2006.201.14:43:45.26#ibcon#*before return 0, iclass 21, count 0 2006.201.14:43:45.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:45.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.14:43:45.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:43:45.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:43:45.26$vck44/vb=3,4 2006.201.14:43:45.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.14:43:45.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.14:43:45.26#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:45.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:43:45.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:43:45.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:43:45.32#ibcon#enter wrdev, iclass 23, count 2 2006.201.14:43:45.32#ibcon#first serial, iclass 23, count 2 2006.201.14:43:45.32#ibcon#enter sib2, iclass 23, count 2 2006.201.14:43:45.32#ibcon#flushed, iclass 23, count 2 2006.201.14:43:45.32#ibcon#about to write, iclass 23, count 2 2006.201.14:43:45.32#ibcon#wrote, iclass 23, count 2 2006.201.14:43:45.32#ibcon#about to read 3, iclass 23, count 2 2006.201.14:43:45.34#ibcon#read 3, iclass 23, count 2 2006.201.14:43:45.34#ibcon#about to read 4, iclass 23, count 2 2006.201.14:43:45.34#ibcon#read 4, iclass 23, count 2 2006.201.14:43:45.34#ibcon#about to read 5, iclass 23, count 2 2006.201.14:43:45.34#ibcon#read 5, iclass 23, count 2 2006.201.14:43:45.34#ibcon#about to read 6, iclass 23, count 2 2006.201.14:43:45.34#ibcon#read 6, iclass 23, count 2 2006.201.14:43:45.34#ibcon#end of sib2, iclass 23, count 2 2006.201.14:43:45.34#ibcon#*mode == 0, iclass 23, count 2 2006.201.14:43:45.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.14:43:45.34#ibcon#[27=AT03-04\r\n] 2006.201.14:43:45.34#ibcon#*before write, iclass 23, count 2 2006.201.14:43:45.34#ibcon#enter sib2, iclass 23, count 2 2006.201.14:43:45.34#ibcon#flushed, iclass 23, count 2 2006.201.14:43:45.34#ibcon#about to write, iclass 23, count 2 2006.201.14:43:45.34#ibcon#wrote, iclass 23, count 2 2006.201.14:43:45.34#ibcon#about to read 3, iclass 23, count 2 2006.201.14:43:45.37#ibcon#read 3, iclass 23, count 2 2006.201.14:43:45.37#ibcon#about to read 4, iclass 23, count 2 2006.201.14:43:45.37#ibcon#read 4, iclass 23, count 2 2006.201.14:43:45.37#ibcon#about to read 5, iclass 23, count 2 2006.201.14:43:45.37#ibcon#read 5, iclass 23, count 2 2006.201.14:43:45.37#ibcon#about to read 6, iclass 23, count 2 2006.201.14:43:45.37#ibcon#read 6, iclass 23, count 2 2006.201.14:43:45.37#ibcon#end of sib2, iclass 23, count 2 2006.201.14:43:45.37#ibcon#*after write, iclass 23, count 2 2006.201.14:43:45.37#ibcon#*before return 0, iclass 23, count 2 2006.201.14:43:45.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:43:45.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.14:43:45.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.14:43:45.37#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:45.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:43:45.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:43:45.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:43:45.49#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:43:45.49#ibcon#first serial, iclass 23, count 0 2006.201.14:43:45.49#ibcon#enter sib2, iclass 23, count 0 2006.201.14:43:45.49#ibcon#flushed, iclass 23, count 0 2006.201.14:43:45.49#ibcon#about to write, iclass 23, count 0 2006.201.14:43:45.49#ibcon#wrote, iclass 23, count 0 2006.201.14:43:45.49#ibcon#about to read 3, iclass 23, count 0 2006.201.14:43:45.51#ibcon#read 3, iclass 23, count 0 2006.201.14:43:45.51#ibcon#about to read 4, iclass 23, count 0 2006.201.14:43:45.51#ibcon#read 4, iclass 23, count 0 2006.201.14:43:45.51#ibcon#about to read 5, iclass 23, count 0 2006.201.14:43:45.51#ibcon#read 5, iclass 23, count 0 2006.201.14:43:45.51#ibcon#about to read 6, iclass 23, count 0 2006.201.14:43:45.51#ibcon#read 6, iclass 23, count 0 2006.201.14:43:45.51#ibcon#end of sib2, iclass 23, count 0 2006.201.14:43:45.51#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:43:45.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:43:45.51#ibcon#[27=USB\r\n] 2006.201.14:43:45.51#ibcon#*before write, iclass 23, count 0 2006.201.14:43:45.51#ibcon#enter sib2, iclass 23, count 0 2006.201.14:43:45.51#ibcon#flushed, iclass 23, count 0 2006.201.14:43:45.51#ibcon#about to write, iclass 23, count 0 2006.201.14:43:45.51#ibcon#wrote, iclass 23, count 0 2006.201.14:43:45.51#ibcon#about to read 3, iclass 23, count 0 2006.201.14:43:45.54#ibcon#read 3, iclass 23, count 0 2006.201.14:43:45.54#ibcon#about to read 4, iclass 23, count 0 2006.201.14:43:45.54#ibcon#read 4, iclass 23, count 0 2006.201.14:43:45.54#ibcon#about to read 5, iclass 23, count 0 2006.201.14:43:45.54#ibcon#read 5, iclass 23, count 0 2006.201.14:43:45.54#ibcon#about to read 6, iclass 23, count 0 2006.201.14:43:45.54#ibcon#read 6, iclass 23, count 0 2006.201.14:43:45.54#ibcon#end of sib2, iclass 23, count 0 2006.201.14:43:45.54#ibcon#*after write, iclass 23, count 0 2006.201.14:43:45.54#ibcon#*before return 0, iclass 23, count 0 2006.201.14:43:45.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:43:45.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.14:43:45.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:43:45.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:43:45.54$vck44/vblo=4,679.99 2006.201.14:43:45.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.14:43:45.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.14:43:45.54#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:45.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:43:45.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:43:45.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:43:45.54#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:43:45.54#ibcon#first serial, iclass 25, count 0 2006.201.14:43:45.54#ibcon#enter sib2, iclass 25, count 0 2006.201.14:43:45.54#ibcon#flushed, iclass 25, count 0 2006.201.14:43:45.54#ibcon#about to write, iclass 25, count 0 2006.201.14:43:45.54#ibcon#wrote, iclass 25, count 0 2006.201.14:43:45.54#ibcon#about to read 3, iclass 25, count 0 2006.201.14:43:45.56#ibcon#read 3, iclass 25, count 0 2006.201.14:43:45.56#ibcon#about to read 4, iclass 25, count 0 2006.201.14:43:45.56#ibcon#read 4, iclass 25, count 0 2006.201.14:43:45.56#ibcon#about to read 5, iclass 25, count 0 2006.201.14:43:45.56#ibcon#read 5, iclass 25, count 0 2006.201.14:43:45.56#ibcon#about to read 6, iclass 25, count 0 2006.201.14:43:45.56#ibcon#read 6, iclass 25, count 0 2006.201.14:43:45.56#ibcon#end of sib2, iclass 25, count 0 2006.201.14:43:45.56#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:43:45.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:43:45.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:43:45.56#ibcon#*before write, iclass 25, count 0 2006.201.14:43:45.56#ibcon#enter sib2, iclass 25, count 0 2006.201.14:43:45.56#ibcon#flushed, iclass 25, count 0 2006.201.14:43:45.56#ibcon#about to write, iclass 25, count 0 2006.201.14:43:45.56#ibcon#wrote, iclass 25, count 0 2006.201.14:43:45.56#ibcon#about to read 3, iclass 25, count 0 2006.201.14:43:45.61#ibcon#read 3, iclass 25, count 0 2006.201.14:43:45.61#ibcon#about to read 4, iclass 25, count 0 2006.201.14:43:45.61#ibcon#read 4, iclass 25, count 0 2006.201.14:43:45.61#ibcon#about to read 5, iclass 25, count 0 2006.201.14:43:45.61#ibcon#read 5, iclass 25, count 0 2006.201.14:43:45.61#ibcon#about to read 6, iclass 25, count 0 2006.201.14:43:45.61#ibcon#read 6, iclass 25, count 0 2006.201.14:43:45.61#ibcon#end of sib2, iclass 25, count 0 2006.201.14:43:45.61#ibcon#*after write, iclass 25, count 0 2006.201.14:43:45.61#ibcon#*before return 0, iclass 25, count 0 2006.201.14:43:45.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:43:45.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.14:43:45.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:43:45.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:43:45.61$vck44/vb=4,5 2006.201.14:43:45.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.14:43:45.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.14:43:45.61#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:45.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:43:45.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:43:45.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:43:45.66#ibcon#enter wrdev, iclass 27, count 2 2006.201.14:43:45.66#ibcon#first serial, iclass 27, count 2 2006.201.14:43:45.66#ibcon#enter sib2, iclass 27, count 2 2006.201.14:43:45.66#ibcon#flushed, iclass 27, count 2 2006.201.14:43:45.66#ibcon#about to write, iclass 27, count 2 2006.201.14:43:45.66#ibcon#wrote, iclass 27, count 2 2006.201.14:43:45.66#ibcon#about to read 3, iclass 27, count 2 2006.201.14:43:45.68#ibcon#read 3, iclass 27, count 2 2006.201.14:43:45.68#ibcon#about to read 4, iclass 27, count 2 2006.201.14:43:45.68#ibcon#read 4, iclass 27, count 2 2006.201.14:43:45.68#ibcon#about to read 5, iclass 27, count 2 2006.201.14:43:45.68#ibcon#read 5, iclass 27, count 2 2006.201.14:43:45.68#ibcon#about to read 6, iclass 27, count 2 2006.201.14:43:45.68#ibcon#read 6, iclass 27, count 2 2006.201.14:43:45.68#ibcon#end of sib2, iclass 27, count 2 2006.201.14:43:45.68#ibcon#*mode == 0, iclass 27, count 2 2006.201.14:43:45.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.14:43:45.68#ibcon#[27=AT04-05\r\n] 2006.201.14:43:45.68#ibcon#*before write, iclass 27, count 2 2006.201.14:43:45.68#ibcon#enter sib2, iclass 27, count 2 2006.201.14:43:45.68#ibcon#flushed, iclass 27, count 2 2006.201.14:43:45.68#ibcon#about to write, iclass 27, count 2 2006.201.14:43:45.68#ibcon#wrote, iclass 27, count 2 2006.201.14:43:45.68#ibcon#about to read 3, iclass 27, count 2 2006.201.14:43:45.71#ibcon#read 3, iclass 27, count 2 2006.201.14:43:45.71#ibcon#about to read 4, iclass 27, count 2 2006.201.14:43:45.71#ibcon#read 4, iclass 27, count 2 2006.201.14:43:45.71#ibcon#about to read 5, iclass 27, count 2 2006.201.14:43:45.71#ibcon#read 5, iclass 27, count 2 2006.201.14:43:45.71#ibcon#about to read 6, iclass 27, count 2 2006.201.14:43:45.71#ibcon#read 6, iclass 27, count 2 2006.201.14:43:45.71#ibcon#end of sib2, iclass 27, count 2 2006.201.14:43:45.71#ibcon#*after write, iclass 27, count 2 2006.201.14:43:45.71#ibcon#*before return 0, iclass 27, count 2 2006.201.14:43:45.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:43:45.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.14:43:45.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.14:43:45.71#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:45.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:43:45.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:43:45.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:43:45.83#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:43:45.83#ibcon#first serial, iclass 27, count 0 2006.201.14:43:45.83#ibcon#enter sib2, iclass 27, count 0 2006.201.14:43:45.83#ibcon#flushed, iclass 27, count 0 2006.201.14:43:45.83#ibcon#about to write, iclass 27, count 0 2006.201.14:43:45.83#ibcon#wrote, iclass 27, count 0 2006.201.14:43:45.83#ibcon#about to read 3, iclass 27, count 0 2006.201.14:43:45.85#ibcon#read 3, iclass 27, count 0 2006.201.14:43:45.85#ibcon#about to read 4, iclass 27, count 0 2006.201.14:43:45.85#ibcon#read 4, iclass 27, count 0 2006.201.14:43:45.85#ibcon#about to read 5, iclass 27, count 0 2006.201.14:43:45.85#ibcon#read 5, iclass 27, count 0 2006.201.14:43:45.85#ibcon#about to read 6, iclass 27, count 0 2006.201.14:43:45.85#ibcon#read 6, iclass 27, count 0 2006.201.14:43:45.85#ibcon#end of sib2, iclass 27, count 0 2006.201.14:43:45.85#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:43:45.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:43:45.85#ibcon#[27=USB\r\n] 2006.201.14:43:45.85#ibcon#*before write, iclass 27, count 0 2006.201.14:43:45.85#ibcon#enter sib2, iclass 27, count 0 2006.201.14:43:45.85#ibcon#flushed, iclass 27, count 0 2006.201.14:43:45.85#ibcon#about to write, iclass 27, count 0 2006.201.14:43:45.85#ibcon#wrote, iclass 27, count 0 2006.201.14:43:45.85#ibcon#about to read 3, iclass 27, count 0 2006.201.14:43:45.88#ibcon#read 3, iclass 27, count 0 2006.201.14:43:45.88#ibcon#about to read 4, iclass 27, count 0 2006.201.14:43:45.88#ibcon#read 4, iclass 27, count 0 2006.201.14:43:45.88#ibcon#about to read 5, iclass 27, count 0 2006.201.14:43:45.88#ibcon#read 5, iclass 27, count 0 2006.201.14:43:45.88#ibcon#about to read 6, iclass 27, count 0 2006.201.14:43:45.88#ibcon#read 6, iclass 27, count 0 2006.201.14:43:45.88#ibcon#end of sib2, iclass 27, count 0 2006.201.14:43:45.88#ibcon#*after write, iclass 27, count 0 2006.201.14:43:45.88#ibcon#*before return 0, iclass 27, count 0 2006.201.14:43:45.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:43:45.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.14:43:45.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:43:45.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:43:45.88$vck44/vblo=5,709.99 2006.201.14:43:45.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.14:43:45.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.14:43:45.88#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:45.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:45.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:45.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:45.88#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:43:45.88#ibcon#first serial, iclass 29, count 0 2006.201.14:43:45.88#ibcon#enter sib2, iclass 29, count 0 2006.201.14:43:45.88#ibcon#flushed, iclass 29, count 0 2006.201.14:43:45.88#ibcon#about to write, iclass 29, count 0 2006.201.14:43:45.88#ibcon#wrote, iclass 29, count 0 2006.201.14:43:45.88#ibcon#about to read 3, iclass 29, count 0 2006.201.14:43:45.90#ibcon#read 3, iclass 29, count 0 2006.201.14:43:45.90#ibcon#about to read 4, iclass 29, count 0 2006.201.14:43:45.90#ibcon#read 4, iclass 29, count 0 2006.201.14:43:45.90#ibcon#about to read 5, iclass 29, count 0 2006.201.14:43:45.90#ibcon#read 5, iclass 29, count 0 2006.201.14:43:45.90#ibcon#about to read 6, iclass 29, count 0 2006.201.14:43:45.90#ibcon#read 6, iclass 29, count 0 2006.201.14:43:45.90#ibcon#end of sib2, iclass 29, count 0 2006.201.14:43:45.90#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:43:45.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:43:45.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:43:45.90#ibcon#*before write, iclass 29, count 0 2006.201.14:43:45.90#ibcon#enter sib2, iclass 29, count 0 2006.201.14:43:45.90#ibcon#flushed, iclass 29, count 0 2006.201.14:43:45.90#ibcon#about to write, iclass 29, count 0 2006.201.14:43:45.90#ibcon#wrote, iclass 29, count 0 2006.201.14:43:45.90#ibcon#about to read 3, iclass 29, count 0 2006.201.14:43:45.94#ibcon#read 3, iclass 29, count 0 2006.201.14:43:45.94#ibcon#about to read 4, iclass 29, count 0 2006.201.14:43:45.94#ibcon#read 4, iclass 29, count 0 2006.201.14:43:45.94#ibcon#about to read 5, iclass 29, count 0 2006.201.14:43:45.94#ibcon#read 5, iclass 29, count 0 2006.201.14:43:45.94#ibcon#about to read 6, iclass 29, count 0 2006.201.14:43:45.94#ibcon#read 6, iclass 29, count 0 2006.201.14:43:45.94#ibcon#end of sib2, iclass 29, count 0 2006.201.14:43:45.94#ibcon#*after write, iclass 29, count 0 2006.201.14:43:45.94#ibcon#*before return 0, iclass 29, count 0 2006.201.14:43:45.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:45.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.14:43:45.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:43:45.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:43:45.94$vck44/vb=5,4 2006.201.14:43:45.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.14:43:45.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.14:43:45.94#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:45.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:46.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:46.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:46.00#ibcon#enter wrdev, iclass 31, count 2 2006.201.14:43:46.00#ibcon#first serial, iclass 31, count 2 2006.201.14:43:46.00#ibcon#enter sib2, iclass 31, count 2 2006.201.14:43:46.00#ibcon#flushed, iclass 31, count 2 2006.201.14:43:46.00#ibcon#about to write, iclass 31, count 2 2006.201.14:43:46.00#ibcon#wrote, iclass 31, count 2 2006.201.14:43:46.00#ibcon#about to read 3, iclass 31, count 2 2006.201.14:43:46.02#ibcon#read 3, iclass 31, count 2 2006.201.14:43:46.02#ibcon#about to read 4, iclass 31, count 2 2006.201.14:43:46.02#ibcon#read 4, iclass 31, count 2 2006.201.14:43:46.02#ibcon#about to read 5, iclass 31, count 2 2006.201.14:43:46.02#ibcon#read 5, iclass 31, count 2 2006.201.14:43:46.02#ibcon#about to read 6, iclass 31, count 2 2006.201.14:43:46.02#ibcon#read 6, iclass 31, count 2 2006.201.14:43:46.02#ibcon#end of sib2, iclass 31, count 2 2006.201.14:43:46.02#ibcon#*mode == 0, iclass 31, count 2 2006.201.14:43:46.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.14:43:46.02#ibcon#[27=AT05-04\r\n] 2006.201.14:43:46.02#ibcon#*before write, iclass 31, count 2 2006.201.14:43:46.02#ibcon#enter sib2, iclass 31, count 2 2006.201.14:43:46.02#ibcon#flushed, iclass 31, count 2 2006.201.14:43:46.02#ibcon#about to write, iclass 31, count 2 2006.201.14:43:46.02#ibcon#wrote, iclass 31, count 2 2006.201.14:43:46.02#ibcon#about to read 3, iclass 31, count 2 2006.201.14:43:46.05#ibcon#read 3, iclass 31, count 2 2006.201.14:43:46.05#ibcon#about to read 4, iclass 31, count 2 2006.201.14:43:46.05#ibcon#read 4, iclass 31, count 2 2006.201.14:43:46.05#ibcon#about to read 5, iclass 31, count 2 2006.201.14:43:46.05#ibcon#read 5, iclass 31, count 2 2006.201.14:43:46.05#ibcon#about to read 6, iclass 31, count 2 2006.201.14:43:46.05#ibcon#read 6, iclass 31, count 2 2006.201.14:43:46.05#ibcon#end of sib2, iclass 31, count 2 2006.201.14:43:46.05#ibcon#*after write, iclass 31, count 2 2006.201.14:43:46.05#ibcon#*before return 0, iclass 31, count 2 2006.201.14:43:46.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:46.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.14:43:46.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.14:43:46.05#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:46.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:46.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:46.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:46.17#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:43:46.17#ibcon#first serial, iclass 31, count 0 2006.201.14:43:46.17#ibcon#enter sib2, iclass 31, count 0 2006.201.14:43:46.17#ibcon#flushed, iclass 31, count 0 2006.201.14:43:46.17#ibcon#about to write, iclass 31, count 0 2006.201.14:43:46.17#ibcon#wrote, iclass 31, count 0 2006.201.14:43:46.17#ibcon#about to read 3, iclass 31, count 0 2006.201.14:43:46.19#ibcon#read 3, iclass 31, count 0 2006.201.14:43:46.19#ibcon#about to read 4, iclass 31, count 0 2006.201.14:43:46.19#ibcon#read 4, iclass 31, count 0 2006.201.14:43:46.19#ibcon#about to read 5, iclass 31, count 0 2006.201.14:43:46.19#ibcon#read 5, iclass 31, count 0 2006.201.14:43:46.19#ibcon#about to read 6, iclass 31, count 0 2006.201.14:43:46.19#ibcon#read 6, iclass 31, count 0 2006.201.14:43:46.19#ibcon#end of sib2, iclass 31, count 0 2006.201.14:43:46.19#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:43:46.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:43:46.19#ibcon#[27=USB\r\n] 2006.201.14:43:46.19#ibcon#*before write, iclass 31, count 0 2006.201.14:43:46.19#ibcon#enter sib2, iclass 31, count 0 2006.201.14:43:46.19#ibcon#flushed, iclass 31, count 0 2006.201.14:43:46.19#ibcon#about to write, iclass 31, count 0 2006.201.14:43:46.19#ibcon#wrote, iclass 31, count 0 2006.201.14:43:46.19#ibcon#about to read 3, iclass 31, count 0 2006.201.14:43:46.22#ibcon#read 3, iclass 31, count 0 2006.201.14:43:46.22#ibcon#about to read 4, iclass 31, count 0 2006.201.14:43:46.22#ibcon#read 4, iclass 31, count 0 2006.201.14:43:46.22#ibcon#about to read 5, iclass 31, count 0 2006.201.14:43:46.22#ibcon#read 5, iclass 31, count 0 2006.201.14:43:46.22#ibcon#about to read 6, iclass 31, count 0 2006.201.14:43:46.22#ibcon#read 6, iclass 31, count 0 2006.201.14:43:46.22#ibcon#end of sib2, iclass 31, count 0 2006.201.14:43:46.22#ibcon#*after write, iclass 31, count 0 2006.201.14:43:46.22#ibcon#*before return 0, iclass 31, count 0 2006.201.14:43:46.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:46.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.14:43:46.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:43:46.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:43:46.22$vck44/vblo=6,719.99 2006.201.14:43:46.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.14:43:46.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.14:43:46.22#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:46.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:46.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:46.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:46.22#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:43:46.22#ibcon#first serial, iclass 33, count 0 2006.201.14:43:46.22#ibcon#enter sib2, iclass 33, count 0 2006.201.14:43:46.22#ibcon#flushed, iclass 33, count 0 2006.201.14:43:46.22#ibcon#about to write, iclass 33, count 0 2006.201.14:43:46.22#ibcon#wrote, iclass 33, count 0 2006.201.14:43:46.22#ibcon#about to read 3, iclass 33, count 0 2006.201.14:43:46.24#ibcon#read 3, iclass 33, count 0 2006.201.14:43:46.24#ibcon#about to read 4, iclass 33, count 0 2006.201.14:43:46.24#ibcon#read 4, iclass 33, count 0 2006.201.14:43:46.24#ibcon#about to read 5, iclass 33, count 0 2006.201.14:43:46.24#ibcon#read 5, iclass 33, count 0 2006.201.14:43:46.24#ibcon#about to read 6, iclass 33, count 0 2006.201.14:43:46.24#ibcon#read 6, iclass 33, count 0 2006.201.14:43:46.24#ibcon#end of sib2, iclass 33, count 0 2006.201.14:43:46.24#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:43:46.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:43:46.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:43:46.24#ibcon#*before write, iclass 33, count 0 2006.201.14:43:46.24#ibcon#enter sib2, iclass 33, count 0 2006.201.14:43:46.24#ibcon#flushed, iclass 33, count 0 2006.201.14:43:46.24#ibcon#about to write, iclass 33, count 0 2006.201.14:43:46.24#ibcon#wrote, iclass 33, count 0 2006.201.14:43:46.24#ibcon#about to read 3, iclass 33, count 0 2006.201.14:43:46.28#ibcon#read 3, iclass 33, count 0 2006.201.14:43:46.28#ibcon#about to read 4, iclass 33, count 0 2006.201.14:43:46.28#ibcon#read 4, iclass 33, count 0 2006.201.14:43:46.28#ibcon#about to read 5, iclass 33, count 0 2006.201.14:43:46.28#ibcon#read 5, iclass 33, count 0 2006.201.14:43:46.28#ibcon#about to read 6, iclass 33, count 0 2006.201.14:43:46.28#ibcon#read 6, iclass 33, count 0 2006.201.14:43:46.28#ibcon#end of sib2, iclass 33, count 0 2006.201.14:43:46.28#ibcon#*after write, iclass 33, count 0 2006.201.14:43:46.28#ibcon#*before return 0, iclass 33, count 0 2006.201.14:43:46.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:46.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.14:43:46.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:43:46.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:43:46.28$vck44/vb=6,4 2006.201.14:43:46.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.14:43:46.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.14:43:46.28#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:46.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:46.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:46.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:46.34#ibcon#enter wrdev, iclass 35, count 2 2006.201.14:43:46.34#ibcon#first serial, iclass 35, count 2 2006.201.14:43:46.34#ibcon#enter sib2, iclass 35, count 2 2006.201.14:43:46.34#ibcon#flushed, iclass 35, count 2 2006.201.14:43:46.34#ibcon#about to write, iclass 35, count 2 2006.201.14:43:46.34#ibcon#wrote, iclass 35, count 2 2006.201.14:43:46.34#ibcon#about to read 3, iclass 35, count 2 2006.201.14:43:46.36#ibcon#read 3, iclass 35, count 2 2006.201.14:43:46.36#ibcon#about to read 4, iclass 35, count 2 2006.201.14:43:46.36#ibcon#read 4, iclass 35, count 2 2006.201.14:43:46.36#ibcon#about to read 5, iclass 35, count 2 2006.201.14:43:46.36#ibcon#read 5, iclass 35, count 2 2006.201.14:43:46.36#ibcon#about to read 6, iclass 35, count 2 2006.201.14:43:46.36#ibcon#read 6, iclass 35, count 2 2006.201.14:43:46.36#ibcon#end of sib2, iclass 35, count 2 2006.201.14:43:46.36#ibcon#*mode == 0, iclass 35, count 2 2006.201.14:43:46.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.14:43:46.36#ibcon#[27=AT06-04\r\n] 2006.201.14:43:46.36#ibcon#*before write, iclass 35, count 2 2006.201.14:43:46.36#ibcon#enter sib2, iclass 35, count 2 2006.201.14:43:46.36#ibcon#flushed, iclass 35, count 2 2006.201.14:43:46.36#ibcon#about to write, iclass 35, count 2 2006.201.14:43:46.36#ibcon#wrote, iclass 35, count 2 2006.201.14:43:46.36#ibcon#about to read 3, iclass 35, count 2 2006.201.14:43:46.39#ibcon#read 3, iclass 35, count 2 2006.201.14:43:46.39#ibcon#about to read 4, iclass 35, count 2 2006.201.14:43:46.39#ibcon#read 4, iclass 35, count 2 2006.201.14:43:46.39#ibcon#about to read 5, iclass 35, count 2 2006.201.14:43:46.39#ibcon#read 5, iclass 35, count 2 2006.201.14:43:46.39#ibcon#about to read 6, iclass 35, count 2 2006.201.14:43:46.39#ibcon#read 6, iclass 35, count 2 2006.201.14:43:46.39#ibcon#end of sib2, iclass 35, count 2 2006.201.14:43:46.39#ibcon#*after write, iclass 35, count 2 2006.201.14:43:46.39#ibcon#*before return 0, iclass 35, count 2 2006.201.14:43:46.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:46.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.14:43:46.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.14:43:46.39#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:46.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:46.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:46.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:46.51#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:43:46.51#ibcon#first serial, iclass 35, count 0 2006.201.14:43:46.51#ibcon#enter sib2, iclass 35, count 0 2006.201.14:43:46.51#ibcon#flushed, iclass 35, count 0 2006.201.14:43:46.51#ibcon#about to write, iclass 35, count 0 2006.201.14:43:46.51#ibcon#wrote, iclass 35, count 0 2006.201.14:43:46.51#ibcon#about to read 3, iclass 35, count 0 2006.201.14:43:46.53#ibcon#read 3, iclass 35, count 0 2006.201.14:43:46.53#ibcon#about to read 4, iclass 35, count 0 2006.201.14:43:46.53#ibcon#read 4, iclass 35, count 0 2006.201.14:43:46.53#ibcon#about to read 5, iclass 35, count 0 2006.201.14:43:46.53#ibcon#read 5, iclass 35, count 0 2006.201.14:43:46.53#ibcon#about to read 6, iclass 35, count 0 2006.201.14:43:46.53#ibcon#read 6, iclass 35, count 0 2006.201.14:43:46.53#ibcon#end of sib2, iclass 35, count 0 2006.201.14:43:46.53#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:43:46.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:43:46.53#ibcon#[27=USB\r\n] 2006.201.14:43:46.53#ibcon#*before write, iclass 35, count 0 2006.201.14:43:46.53#ibcon#enter sib2, iclass 35, count 0 2006.201.14:43:46.53#ibcon#flushed, iclass 35, count 0 2006.201.14:43:46.53#ibcon#about to write, iclass 35, count 0 2006.201.14:43:46.53#ibcon#wrote, iclass 35, count 0 2006.201.14:43:46.53#ibcon#about to read 3, iclass 35, count 0 2006.201.14:43:46.56#ibcon#read 3, iclass 35, count 0 2006.201.14:43:46.56#ibcon#about to read 4, iclass 35, count 0 2006.201.14:43:46.56#ibcon#read 4, iclass 35, count 0 2006.201.14:43:46.56#ibcon#about to read 5, iclass 35, count 0 2006.201.14:43:46.56#ibcon#read 5, iclass 35, count 0 2006.201.14:43:46.56#ibcon#about to read 6, iclass 35, count 0 2006.201.14:43:46.56#ibcon#read 6, iclass 35, count 0 2006.201.14:43:46.56#ibcon#end of sib2, iclass 35, count 0 2006.201.14:43:46.56#ibcon#*after write, iclass 35, count 0 2006.201.14:43:46.56#ibcon#*before return 0, iclass 35, count 0 2006.201.14:43:46.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:46.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.14:43:46.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:43:46.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:43:46.56$vck44/vblo=7,734.99 2006.201.14:43:46.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.14:43:46.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.14:43:46.56#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:46.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:46.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:46.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:46.56#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:43:46.56#ibcon#first serial, iclass 37, count 0 2006.201.14:43:46.56#ibcon#enter sib2, iclass 37, count 0 2006.201.14:43:46.56#ibcon#flushed, iclass 37, count 0 2006.201.14:43:46.56#ibcon#about to write, iclass 37, count 0 2006.201.14:43:46.56#ibcon#wrote, iclass 37, count 0 2006.201.14:43:46.56#ibcon#about to read 3, iclass 37, count 0 2006.201.14:43:46.58#ibcon#read 3, iclass 37, count 0 2006.201.14:43:46.58#ibcon#about to read 4, iclass 37, count 0 2006.201.14:43:46.58#ibcon#read 4, iclass 37, count 0 2006.201.14:43:46.58#ibcon#about to read 5, iclass 37, count 0 2006.201.14:43:46.58#ibcon#read 5, iclass 37, count 0 2006.201.14:43:46.58#ibcon#about to read 6, iclass 37, count 0 2006.201.14:43:46.58#ibcon#read 6, iclass 37, count 0 2006.201.14:43:46.58#ibcon#end of sib2, iclass 37, count 0 2006.201.14:43:46.58#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:43:46.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:43:46.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:43:46.58#ibcon#*before write, iclass 37, count 0 2006.201.14:43:46.58#ibcon#enter sib2, iclass 37, count 0 2006.201.14:43:46.58#ibcon#flushed, iclass 37, count 0 2006.201.14:43:46.58#ibcon#about to write, iclass 37, count 0 2006.201.14:43:46.58#ibcon#wrote, iclass 37, count 0 2006.201.14:43:46.58#ibcon#about to read 3, iclass 37, count 0 2006.201.14:43:46.62#ibcon#read 3, iclass 37, count 0 2006.201.14:43:46.62#ibcon#about to read 4, iclass 37, count 0 2006.201.14:43:46.62#ibcon#read 4, iclass 37, count 0 2006.201.14:43:46.62#ibcon#about to read 5, iclass 37, count 0 2006.201.14:43:46.62#ibcon#read 5, iclass 37, count 0 2006.201.14:43:46.62#ibcon#about to read 6, iclass 37, count 0 2006.201.14:43:46.62#ibcon#read 6, iclass 37, count 0 2006.201.14:43:46.62#ibcon#end of sib2, iclass 37, count 0 2006.201.14:43:46.62#ibcon#*after write, iclass 37, count 0 2006.201.14:43:46.62#ibcon#*before return 0, iclass 37, count 0 2006.201.14:43:46.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:46.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.14:43:46.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:43:46.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:43:46.62$vck44/vb=7,4 2006.201.14:43:46.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.14:43:46.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.14:43:46.62#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:46.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:46.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:46.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:46.68#ibcon#enter wrdev, iclass 39, count 2 2006.201.14:43:46.68#ibcon#first serial, iclass 39, count 2 2006.201.14:43:46.68#ibcon#enter sib2, iclass 39, count 2 2006.201.14:43:46.68#ibcon#flushed, iclass 39, count 2 2006.201.14:43:46.68#ibcon#about to write, iclass 39, count 2 2006.201.14:43:46.68#ibcon#wrote, iclass 39, count 2 2006.201.14:43:46.68#ibcon#about to read 3, iclass 39, count 2 2006.201.14:43:46.70#ibcon#read 3, iclass 39, count 2 2006.201.14:43:46.70#ibcon#about to read 4, iclass 39, count 2 2006.201.14:43:46.70#ibcon#read 4, iclass 39, count 2 2006.201.14:43:46.70#ibcon#about to read 5, iclass 39, count 2 2006.201.14:43:46.70#ibcon#read 5, iclass 39, count 2 2006.201.14:43:46.70#ibcon#about to read 6, iclass 39, count 2 2006.201.14:43:46.70#ibcon#read 6, iclass 39, count 2 2006.201.14:43:46.70#ibcon#end of sib2, iclass 39, count 2 2006.201.14:43:46.70#ibcon#*mode == 0, iclass 39, count 2 2006.201.14:43:46.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.14:43:46.70#ibcon#[27=AT07-04\r\n] 2006.201.14:43:46.70#ibcon#*before write, iclass 39, count 2 2006.201.14:43:46.70#ibcon#enter sib2, iclass 39, count 2 2006.201.14:43:46.70#ibcon#flushed, iclass 39, count 2 2006.201.14:43:46.70#ibcon#about to write, iclass 39, count 2 2006.201.14:43:46.70#ibcon#wrote, iclass 39, count 2 2006.201.14:43:46.70#ibcon#about to read 3, iclass 39, count 2 2006.201.14:43:46.73#ibcon#read 3, iclass 39, count 2 2006.201.14:43:46.73#ibcon#about to read 4, iclass 39, count 2 2006.201.14:43:46.73#ibcon#read 4, iclass 39, count 2 2006.201.14:43:46.73#ibcon#about to read 5, iclass 39, count 2 2006.201.14:43:46.73#ibcon#read 5, iclass 39, count 2 2006.201.14:43:46.73#ibcon#about to read 6, iclass 39, count 2 2006.201.14:43:46.73#ibcon#read 6, iclass 39, count 2 2006.201.14:43:46.73#ibcon#end of sib2, iclass 39, count 2 2006.201.14:43:46.73#ibcon#*after write, iclass 39, count 2 2006.201.14:43:46.73#ibcon#*before return 0, iclass 39, count 2 2006.201.14:43:46.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:46.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.14:43:46.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.14:43:46.73#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:46.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:46.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:46.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:46.85#ibcon#enter wrdev, iclass 39, count 0 2006.201.14:43:46.85#ibcon#first serial, iclass 39, count 0 2006.201.14:43:46.85#ibcon#enter sib2, iclass 39, count 0 2006.201.14:43:46.85#ibcon#flushed, iclass 39, count 0 2006.201.14:43:46.85#ibcon#about to write, iclass 39, count 0 2006.201.14:43:46.85#ibcon#wrote, iclass 39, count 0 2006.201.14:43:46.85#ibcon#about to read 3, iclass 39, count 0 2006.201.14:43:46.87#ibcon#read 3, iclass 39, count 0 2006.201.14:43:46.87#ibcon#about to read 4, iclass 39, count 0 2006.201.14:43:46.87#ibcon#read 4, iclass 39, count 0 2006.201.14:43:46.87#ibcon#about to read 5, iclass 39, count 0 2006.201.14:43:46.87#ibcon#read 5, iclass 39, count 0 2006.201.14:43:46.87#ibcon#about to read 6, iclass 39, count 0 2006.201.14:43:46.87#ibcon#read 6, iclass 39, count 0 2006.201.14:43:46.87#ibcon#end of sib2, iclass 39, count 0 2006.201.14:43:46.87#ibcon#*mode == 0, iclass 39, count 0 2006.201.14:43:46.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.14:43:46.87#ibcon#[27=USB\r\n] 2006.201.14:43:46.87#ibcon#*before write, iclass 39, count 0 2006.201.14:43:46.87#ibcon#enter sib2, iclass 39, count 0 2006.201.14:43:46.87#ibcon#flushed, iclass 39, count 0 2006.201.14:43:46.87#ibcon#about to write, iclass 39, count 0 2006.201.14:43:46.87#ibcon#wrote, iclass 39, count 0 2006.201.14:43:46.87#ibcon#about to read 3, iclass 39, count 0 2006.201.14:43:46.90#ibcon#read 3, iclass 39, count 0 2006.201.14:43:46.90#ibcon#about to read 4, iclass 39, count 0 2006.201.14:43:46.90#ibcon#read 4, iclass 39, count 0 2006.201.14:43:46.90#ibcon#about to read 5, iclass 39, count 0 2006.201.14:43:46.90#ibcon#read 5, iclass 39, count 0 2006.201.14:43:46.90#ibcon#about to read 6, iclass 39, count 0 2006.201.14:43:46.90#ibcon#read 6, iclass 39, count 0 2006.201.14:43:46.90#ibcon#end of sib2, iclass 39, count 0 2006.201.14:43:46.90#ibcon#*after write, iclass 39, count 0 2006.201.14:43:46.90#ibcon#*before return 0, iclass 39, count 0 2006.201.14:43:46.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:46.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.14:43:46.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.14:43:46.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.14:43:46.90$vck44/vblo=8,744.99 2006.201.14:43:46.90#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.14:43:46.90#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.14:43:46.90#ibcon#ireg 17 cls_cnt 0 2006.201.14:43:46.90#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:46.90#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:46.90#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:46.90#ibcon#enter wrdev, iclass 2, count 0 2006.201.14:43:46.90#ibcon#first serial, iclass 2, count 0 2006.201.14:43:46.90#ibcon#enter sib2, iclass 2, count 0 2006.201.14:43:46.90#ibcon#flushed, iclass 2, count 0 2006.201.14:43:46.90#ibcon#about to write, iclass 2, count 0 2006.201.14:43:46.90#ibcon#wrote, iclass 2, count 0 2006.201.14:43:46.90#ibcon#about to read 3, iclass 2, count 0 2006.201.14:43:46.92#ibcon#read 3, iclass 2, count 0 2006.201.14:43:46.92#ibcon#about to read 4, iclass 2, count 0 2006.201.14:43:46.92#ibcon#read 4, iclass 2, count 0 2006.201.14:43:46.92#ibcon#about to read 5, iclass 2, count 0 2006.201.14:43:46.92#ibcon#read 5, iclass 2, count 0 2006.201.14:43:46.92#ibcon#about to read 6, iclass 2, count 0 2006.201.14:43:46.92#ibcon#read 6, iclass 2, count 0 2006.201.14:43:46.92#ibcon#end of sib2, iclass 2, count 0 2006.201.14:43:46.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.14:43:46.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.14:43:46.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:43:46.92#ibcon#*before write, iclass 2, count 0 2006.201.14:43:46.92#ibcon#enter sib2, iclass 2, count 0 2006.201.14:43:46.92#ibcon#flushed, iclass 2, count 0 2006.201.14:43:46.92#ibcon#about to write, iclass 2, count 0 2006.201.14:43:46.92#ibcon#wrote, iclass 2, count 0 2006.201.14:43:46.92#ibcon#about to read 3, iclass 2, count 0 2006.201.14:43:46.96#ibcon#read 3, iclass 2, count 0 2006.201.14:43:46.96#ibcon#about to read 4, iclass 2, count 0 2006.201.14:43:46.96#ibcon#read 4, iclass 2, count 0 2006.201.14:43:46.96#ibcon#about to read 5, iclass 2, count 0 2006.201.14:43:46.96#ibcon#read 5, iclass 2, count 0 2006.201.14:43:46.96#ibcon#about to read 6, iclass 2, count 0 2006.201.14:43:46.96#ibcon#read 6, iclass 2, count 0 2006.201.14:43:46.96#ibcon#end of sib2, iclass 2, count 0 2006.201.14:43:46.96#ibcon#*after write, iclass 2, count 0 2006.201.14:43:46.96#ibcon#*before return 0, iclass 2, count 0 2006.201.14:43:46.96#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:46.96#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:43:46.96#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.14:43:46.96#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.14:43:46.96$vck44/vb=8,4 2006.201.14:43:46.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.14:43:46.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.14:43:46.96#ibcon#ireg 11 cls_cnt 2 2006.201.14:43:46.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:47.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:47.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:47.02#ibcon#enter wrdev, iclass 5, count 2 2006.201.14:43:47.02#ibcon#first serial, iclass 5, count 2 2006.201.14:43:47.02#ibcon#enter sib2, iclass 5, count 2 2006.201.14:43:47.02#ibcon#flushed, iclass 5, count 2 2006.201.14:43:47.02#ibcon#about to write, iclass 5, count 2 2006.201.14:43:47.02#ibcon#wrote, iclass 5, count 2 2006.201.14:43:47.02#ibcon#about to read 3, iclass 5, count 2 2006.201.14:43:47.04#ibcon#read 3, iclass 5, count 2 2006.201.14:43:47.04#ibcon#about to read 4, iclass 5, count 2 2006.201.14:43:47.04#ibcon#read 4, iclass 5, count 2 2006.201.14:43:47.04#ibcon#about to read 5, iclass 5, count 2 2006.201.14:43:47.04#ibcon#read 5, iclass 5, count 2 2006.201.14:43:47.04#ibcon#about to read 6, iclass 5, count 2 2006.201.14:43:47.04#ibcon#read 6, iclass 5, count 2 2006.201.14:43:47.04#ibcon#end of sib2, iclass 5, count 2 2006.201.14:43:47.04#ibcon#*mode == 0, iclass 5, count 2 2006.201.14:43:47.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.14:43:47.04#ibcon#[27=AT08-04\r\n] 2006.201.14:43:47.04#ibcon#*before write, iclass 5, count 2 2006.201.14:43:47.04#ibcon#enter sib2, iclass 5, count 2 2006.201.14:43:47.04#ibcon#flushed, iclass 5, count 2 2006.201.14:43:47.04#ibcon#about to write, iclass 5, count 2 2006.201.14:43:47.04#ibcon#wrote, iclass 5, count 2 2006.201.14:43:47.04#ibcon#about to read 3, iclass 5, count 2 2006.201.14:43:47.07#ibcon#read 3, iclass 5, count 2 2006.201.14:43:47.07#ibcon#about to read 4, iclass 5, count 2 2006.201.14:43:47.07#ibcon#read 4, iclass 5, count 2 2006.201.14:43:47.07#ibcon#about to read 5, iclass 5, count 2 2006.201.14:43:47.07#ibcon#read 5, iclass 5, count 2 2006.201.14:43:47.07#ibcon#about to read 6, iclass 5, count 2 2006.201.14:43:47.07#ibcon#read 6, iclass 5, count 2 2006.201.14:43:47.07#ibcon#end of sib2, iclass 5, count 2 2006.201.14:43:47.07#ibcon#*after write, iclass 5, count 2 2006.201.14:43:47.07#ibcon#*before return 0, iclass 5, count 2 2006.201.14:43:47.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:47.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.14:43:47.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.14:43:47.07#ibcon#ireg 7 cls_cnt 0 2006.201.14:43:47.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:47.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:47.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:47.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:43:47.19#ibcon#first serial, iclass 5, count 0 2006.201.14:43:47.19#ibcon#enter sib2, iclass 5, count 0 2006.201.14:43:47.19#ibcon#flushed, iclass 5, count 0 2006.201.14:43:47.19#ibcon#about to write, iclass 5, count 0 2006.201.14:43:47.19#ibcon#wrote, iclass 5, count 0 2006.201.14:43:47.19#ibcon#about to read 3, iclass 5, count 0 2006.201.14:43:47.22#ibcon#read 3, iclass 5, count 0 2006.201.14:43:47.22#ibcon#about to read 4, iclass 5, count 0 2006.201.14:43:47.22#ibcon#read 4, iclass 5, count 0 2006.201.14:43:47.22#ibcon#about to read 5, iclass 5, count 0 2006.201.14:43:47.22#ibcon#read 5, iclass 5, count 0 2006.201.14:43:47.22#ibcon#about to read 6, iclass 5, count 0 2006.201.14:43:47.22#ibcon#read 6, iclass 5, count 0 2006.201.14:43:47.22#ibcon#end of sib2, iclass 5, count 0 2006.201.14:43:47.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:43:47.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:43:47.22#ibcon#[27=USB\r\n] 2006.201.14:43:47.22#ibcon#*before write, iclass 5, count 0 2006.201.14:43:47.22#ibcon#enter sib2, iclass 5, count 0 2006.201.14:43:47.22#ibcon#flushed, iclass 5, count 0 2006.201.14:43:47.22#ibcon#about to write, iclass 5, count 0 2006.201.14:43:47.22#ibcon#wrote, iclass 5, count 0 2006.201.14:43:47.22#ibcon#about to read 3, iclass 5, count 0 2006.201.14:43:47.25#ibcon#read 3, iclass 5, count 0 2006.201.14:43:47.25#ibcon#about to read 4, iclass 5, count 0 2006.201.14:43:47.25#ibcon#read 4, iclass 5, count 0 2006.201.14:43:47.25#ibcon#about to read 5, iclass 5, count 0 2006.201.14:43:47.25#ibcon#read 5, iclass 5, count 0 2006.201.14:43:47.25#ibcon#about to read 6, iclass 5, count 0 2006.201.14:43:47.25#ibcon#read 6, iclass 5, count 0 2006.201.14:43:47.25#ibcon#end of sib2, iclass 5, count 0 2006.201.14:43:47.25#ibcon#*after write, iclass 5, count 0 2006.201.14:43:47.25#ibcon#*before return 0, iclass 5, count 0 2006.201.14:43:47.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:47.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.14:43:47.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:43:47.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:43:47.25$vck44/vabw=wide 2006.201.14:43:47.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.14:43:47.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.14:43:47.25#ibcon#ireg 8 cls_cnt 0 2006.201.14:43:47.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:47.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:47.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:47.25#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:43:47.25#ibcon#first serial, iclass 7, count 0 2006.201.14:43:47.25#ibcon#enter sib2, iclass 7, count 0 2006.201.14:43:47.25#ibcon#flushed, iclass 7, count 0 2006.201.14:43:47.25#ibcon#about to write, iclass 7, count 0 2006.201.14:43:47.25#ibcon#wrote, iclass 7, count 0 2006.201.14:43:47.25#ibcon#about to read 3, iclass 7, count 0 2006.201.14:43:47.27#ibcon#read 3, iclass 7, count 0 2006.201.14:43:47.27#ibcon#about to read 4, iclass 7, count 0 2006.201.14:43:47.27#ibcon#read 4, iclass 7, count 0 2006.201.14:43:47.27#ibcon#about to read 5, iclass 7, count 0 2006.201.14:43:47.27#ibcon#read 5, iclass 7, count 0 2006.201.14:43:47.27#ibcon#about to read 6, iclass 7, count 0 2006.201.14:43:47.27#ibcon#read 6, iclass 7, count 0 2006.201.14:43:47.27#ibcon#end of sib2, iclass 7, count 0 2006.201.14:43:47.27#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:43:47.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:43:47.27#ibcon#[25=BW32\r\n] 2006.201.14:43:47.27#ibcon#*before write, iclass 7, count 0 2006.201.14:43:47.27#ibcon#enter sib2, iclass 7, count 0 2006.201.14:43:47.27#ibcon#flushed, iclass 7, count 0 2006.201.14:43:47.27#ibcon#about to write, iclass 7, count 0 2006.201.14:43:47.27#ibcon#wrote, iclass 7, count 0 2006.201.14:43:47.27#ibcon#about to read 3, iclass 7, count 0 2006.201.14:43:47.30#ibcon#read 3, iclass 7, count 0 2006.201.14:43:47.30#ibcon#about to read 4, iclass 7, count 0 2006.201.14:43:47.30#ibcon#read 4, iclass 7, count 0 2006.201.14:43:47.30#ibcon#about to read 5, iclass 7, count 0 2006.201.14:43:47.30#ibcon#read 5, iclass 7, count 0 2006.201.14:43:47.30#ibcon#about to read 6, iclass 7, count 0 2006.201.14:43:47.30#ibcon#read 6, iclass 7, count 0 2006.201.14:43:47.30#ibcon#end of sib2, iclass 7, count 0 2006.201.14:43:47.30#ibcon#*after write, iclass 7, count 0 2006.201.14:43:47.30#ibcon#*before return 0, iclass 7, count 0 2006.201.14:43:47.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:47.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.14:43:47.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:43:47.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:43:47.30$vck44/vbbw=wide 2006.201.14:43:47.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.14:43:47.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.14:43:47.30#ibcon#ireg 8 cls_cnt 0 2006.201.14:43:47.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:43:47.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:43:47.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:43:47.37#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:43:47.37#ibcon#first serial, iclass 11, count 0 2006.201.14:43:47.37#ibcon#enter sib2, iclass 11, count 0 2006.201.14:43:47.37#ibcon#flushed, iclass 11, count 0 2006.201.14:43:47.37#ibcon#about to write, iclass 11, count 0 2006.201.14:43:47.37#ibcon#wrote, iclass 11, count 0 2006.201.14:43:47.37#ibcon#about to read 3, iclass 11, count 0 2006.201.14:43:47.39#ibcon#read 3, iclass 11, count 0 2006.201.14:43:47.39#ibcon#about to read 4, iclass 11, count 0 2006.201.14:43:47.39#ibcon#read 4, iclass 11, count 0 2006.201.14:43:47.39#ibcon#about to read 5, iclass 11, count 0 2006.201.14:43:47.39#ibcon#read 5, iclass 11, count 0 2006.201.14:43:47.39#ibcon#about to read 6, iclass 11, count 0 2006.201.14:43:47.39#ibcon#read 6, iclass 11, count 0 2006.201.14:43:47.39#ibcon#end of sib2, iclass 11, count 0 2006.201.14:43:47.39#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:43:47.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:43:47.39#ibcon#[27=BW32\r\n] 2006.201.14:43:47.39#ibcon#*before write, iclass 11, count 0 2006.201.14:43:47.39#ibcon#enter sib2, iclass 11, count 0 2006.201.14:43:47.39#ibcon#flushed, iclass 11, count 0 2006.201.14:43:47.39#ibcon#about to write, iclass 11, count 0 2006.201.14:43:47.39#ibcon#wrote, iclass 11, count 0 2006.201.14:43:47.39#ibcon#about to read 3, iclass 11, count 0 2006.201.14:43:47.42#ibcon#read 3, iclass 11, count 0 2006.201.14:43:47.42#ibcon#about to read 4, iclass 11, count 0 2006.201.14:43:47.42#ibcon#read 4, iclass 11, count 0 2006.201.14:43:47.42#ibcon#about to read 5, iclass 11, count 0 2006.201.14:43:47.42#ibcon#read 5, iclass 11, count 0 2006.201.14:43:47.42#ibcon#about to read 6, iclass 11, count 0 2006.201.14:43:47.42#ibcon#read 6, iclass 11, count 0 2006.201.14:43:47.42#ibcon#end of sib2, iclass 11, count 0 2006.201.14:43:47.42#ibcon#*after write, iclass 11, count 0 2006.201.14:43:47.42#ibcon#*before return 0, iclass 11, count 0 2006.201.14:43:47.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:43:47.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:43:47.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:43:47.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:43:47.42$setupk4/ifdk4 2006.201.14:43:47.42$ifdk4/lo= 2006.201.14:43:47.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:43:47.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:43:47.42$ifdk4/patch= 2006.201.14:43:47.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:43:47.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:43:47.42$setupk4/!*+20s 2006.201.14:43:52.79#abcon#<5=/05 1.3 2.4 20.761001003.4\r\n> 2006.201.14:43:52.81#abcon#{5=INTERFACE CLEAR} 2006.201.14:43:52.87#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:43:59.14#trakl#Source acquired 2006.201.14:44:01.14#flagr#flagr/antenna,acquired 2006.201.14:44:01.90$setupk4/"tpicd 2006.201.14:44:01.90$setupk4/echo=off 2006.201.14:44:01.90$setupk4/xlog=off 2006.201.14:44:01.90:!2006.201.14:46:38 2006.201.14:46:38.00:preob 2006.201.14:46:38.13/onsource/TRACKING 2006.201.14:46:38.13:!2006.201.14:46:48 2006.201.14:46:48.00:"tape 2006.201.14:46:48.00:"st=record 2006.201.14:46:48.00:data_valid=on 2006.201.14:46:48.00:midob 2006.201.14:46:49.13/onsource/TRACKING 2006.201.14:46:49.13/wx/20.76,1003.4,100 2006.201.14:46:49.29/cable/+6.4758E-03 2006.201.14:46:50.38/va/01,08,usb,yes,28,31 2006.201.14:46:50.38/va/02,07,usb,yes,31,32 2006.201.14:46:50.38/va/03,08,usb,yes,28,29 2006.201.14:46:50.38/va/04,07,usb,yes,32,33 2006.201.14:46:50.38/va/05,04,usb,yes,28,28 2006.201.14:46:50.38/va/06,05,usb,yes,28,28 2006.201.14:46:50.38/va/07,05,usb,yes,27,28 2006.201.14:46:50.38/va/08,04,usb,yes,27,32 2006.201.14:46:50.61/valo/01,524.99,yes,locked 2006.201.14:46:50.61/valo/02,534.99,yes,locked 2006.201.14:46:50.61/valo/03,564.99,yes,locked 2006.201.14:46:50.61/valo/04,624.99,yes,locked 2006.201.14:46:50.61/valo/05,734.99,yes,locked 2006.201.14:46:50.61/valo/06,814.99,yes,locked 2006.201.14:46:50.61/valo/07,864.99,yes,locked 2006.201.14:46:50.61/valo/08,884.99,yes,locked 2006.201.14:46:51.70/vb/01,04,usb,yes,28,26 2006.201.14:46:51.70/vb/02,05,usb,yes,27,26 2006.201.14:46:51.70/vb/03,04,usb,yes,27,30 2006.201.14:46:51.70/vb/04,05,usb,yes,28,27 2006.201.14:46:51.70/vb/05,04,usb,yes,24,27 2006.201.14:46:51.70/vb/06,04,usb,yes,28,25 2006.201.14:46:51.70/vb/07,04,usb,yes,28,28 2006.201.14:46:51.70/vb/08,04,usb,yes,26,29 2006.201.14:46:51.94/vblo/01,629.99,yes,locked 2006.201.14:46:51.94/vblo/02,634.99,yes,locked 2006.201.14:46:51.94/vblo/03,649.99,yes,locked 2006.201.14:46:51.94/vblo/04,679.99,yes,locked 2006.201.14:46:51.94/vblo/05,709.99,yes,locked 2006.201.14:46:51.94/vblo/06,719.99,yes,locked 2006.201.14:46:51.94/vblo/07,734.99,yes,locked 2006.201.14:46:51.94/vblo/08,744.99,yes,locked 2006.201.14:46:52.09/vabw/8 2006.201.14:46:52.24/vbbw/8 2006.201.14:46:52.37/xfe/off,on,15.2 2006.201.14:46:52.75/ifatt/23,28,28,28 2006.201.14:46:53.06/fmout-gps/S +4.56E-07 2006.201.14:46:53.12:!2006.201.14:58:48 2006.201.14:58:48.00:data_valid=off 2006.201.14:58:48.00:"et 2006.201.14:58:48.00:!+3s 2006.201.14:58:51.02:"tape 2006.201.14:58:51.02:postob 2006.201.14:58:51.25/cable/+6.4754E-03 2006.201.14:58:51.25/wx/20.76,1003.4,100 2006.201.14:58:51.33/fmout-gps/S +4.57E-07 2006.201.14:58:51.33:scan_name=201-1500,jd0607,60 2006.201.14:58:51.33:source=1611+343,161341.06,341247.9,2000.0,cw 2006.201.14:58:52.14#flagr#flagr/antenna,new-source 2006.201.14:58:52.14:checkk5 2006.201.14:58:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.14:58:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.14:58:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.14:58:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.14:58:54.32/chk_obsdata//k5ts1/T2011446??a.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.201.14:58:54.99/chk_obsdata//k5ts2/T2011446??b.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.201.14:58:55.67/chk_obsdata//k5ts3/T2011446??c.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.201.14:58:56.34/chk_obsdata//k5ts4/T2011446??d.dat file size is correct (nominal:2880MB, actual:2876MB). 2006.201.14:58:57.02/k5log//k5ts1_log_newline 2006.201.14:58:57.71/k5log//k5ts2_log_newline 2006.201.14:58:58.40/k5log//k5ts3_log_newline 2006.201.14:58:59.09/k5log//k5ts4_log_newline 2006.201.14:58:59.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.14:58:59.12:setupk4=1 2006.201.14:58:59.12$setupk4/echo=on 2006.201.14:58:59.12$setupk4/pcalon 2006.201.14:58:59.12$pcalon/"no phase cal control is implemented here 2006.201.14:58:59.12$setupk4/"tpicd=stop 2006.201.14:58:59.12$setupk4/"rec=synch_on 2006.201.14:58:59.12$setupk4/"rec_mode=128 2006.201.14:58:59.12$setupk4/!* 2006.201.14:58:59.12$setupk4/recpk4 2006.201.14:58:59.12$recpk4/recpatch= 2006.201.14:58:59.12$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.14:58:59.12$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.14:58:59.12$setupk4/vck44 2006.201.14:58:59.12$vck44/valo=1,524.99 2006.201.14:58:59.12#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.14:58:59.12#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.14:58:59.12#ibcon#ireg 17 cls_cnt 0 2006.201.14:58:59.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:58:59.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:58:59.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:58:59.12#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:58:59.12#ibcon#first serial, iclass 5, count 0 2006.201.14:58:59.12#ibcon#enter sib2, iclass 5, count 0 2006.201.14:58:59.12#ibcon#flushed, iclass 5, count 0 2006.201.14:58:59.12#ibcon#about to write, iclass 5, count 0 2006.201.14:58:59.12#ibcon#wrote, iclass 5, count 0 2006.201.14:58:59.12#ibcon#about to read 3, iclass 5, count 0 2006.201.14:58:59.16#ibcon#read 3, iclass 5, count 0 2006.201.14:58:59.16#ibcon#about to read 4, iclass 5, count 0 2006.201.14:58:59.16#ibcon#read 4, iclass 5, count 0 2006.201.14:58:59.16#ibcon#about to read 5, iclass 5, count 0 2006.201.14:58:59.16#ibcon#read 5, iclass 5, count 0 2006.201.14:58:59.16#ibcon#about to read 6, iclass 5, count 0 2006.201.14:58:59.16#ibcon#read 6, iclass 5, count 0 2006.201.14:58:59.16#ibcon#end of sib2, iclass 5, count 0 2006.201.14:58:59.16#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:58:59.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:58:59.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.14:58:59.16#ibcon#*before write, iclass 5, count 0 2006.201.14:58:59.16#ibcon#enter sib2, iclass 5, count 0 2006.201.14:58:59.16#ibcon#flushed, iclass 5, count 0 2006.201.14:58:59.16#ibcon#about to write, iclass 5, count 0 2006.201.14:58:59.16#ibcon#wrote, iclass 5, count 0 2006.201.14:58:59.16#ibcon#about to read 3, iclass 5, count 0 2006.201.14:58:59.21#ibcon#read 3, iclass 5, count 0 2006.201.14:58:59.21#ibcon#about to read 4, iclass 5, count 0 2006.201.14:58:59.21#ibcon#read 4, iclass 5, count 0 2006.201.14:58:59.21#ibcon#about to read 5, iclass 5, count 0 2006.201.14:58:59.21#ibcon#read 5, iclass 5, count 0 2006.201.14:58:59.21#ibcon#about to read 6, iclass 5, count 0 2006.201.14:58:59.21#ibcon#read 6, iclass 5, count 0 2006.201.14:58:59.21#ibcon#end of sib2, iclass 5, count 0 2006.201.14:58:59.21#ibcon#*after write, iclass 5, count 0 2006.201.14:58:59.21#ibcon#*before return 0, iclass 5, count 0 2006.201.14:58:59.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:58:59.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:58:59.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:58:59.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:58:59.21$vck44/va=1,8 2006.201.14:58:59.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.14:58:59.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.14:58:59.21#ibcon#ireg 11 cls_cnt 2 2006.201.14:58:59.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:58:59.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:58:59.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:58:59.21#ibcon#enter wrdev, iclass 7, count 2 2006.201.14:58:59.21#ibcon#first serial, iclass 7, count 2 2006.201.14:58:59.21#ibcon#enter sib2, iclass 7, count 2 2006.201.14:58:59.21#ibcon#flushed, iclass 7, count 2 2006.201.14:58:59.21#ibcon#about to write, iclass 7, count 2 2006.201.14:58:59.21#ibcon#wrote, iclass 7, count 2 2006.201.14:58:59.21#ibcon#about to read 3, iclass 7, count 2 2006.201.14:58:59.23#ibcon#read 3, iclass 7, count 2 2006.201.14:58:59.23#ibcon#about to read 4, iclass 7, count 2 2006.201.14:58:59.23#ibcon#read 4, iclass 7, count 2 2006.201.14:58:59.23#ibcon#about to read 5, iclass 7, count 2 2006.201.14:58:59.23#ibcon#read 5, iclass 7, count 2 2006.201.14:58:59.23#ibcon#about to read 6, iclass 7, count 2 2006.201.14:58:59.23#ibcon#read 6, iclass 7, count 2 2006.201.14:58:59.23#ibcon#end of sib2, iclass 7, count 2 2006.201.14:58:59.23#ibcon#*mode == 0, iclass 7, count 2 2006.201.14:58:59.23#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.14:58:59.23#ibcon#[25=AT01-08\r\n] 2006.201.14:58:59.23#ibcon#*before write, iclass 7, count 2 2006.201.14:58:59.23#ibcon#enter sib2, iclass 7, count 2 2006.201.14:58:59.23#ibcon#flushed, iclass 7, count 2 2006.201.14:58:59.23#ibcon#about to write, iclass 7, count 2 2006.201.14:58:59.23#ibcon#wrote, iclass 7, count 2 2006.201.14:58:59.23#ibcon#about to read 3, iclass 7, count 2 2006.201.14:58:59.27#ibcon#read 3, iclass 7, count 2 2006.201.14:58:59.27#ibcon#about to read 4, iclass 7, count 2 2006.201.14:58:59.27#ibcon#read 4, iclass 7, count 2 2006.201.14:58:59.27#ibcon#about to read 5, iclass 7, count 2 2006.201.14:58:59.27#ibcon#read 5, iclass 7, count 2 2006.201.14:58:59.27#ibcon#about to read 6, iclass 7, count 2 2006.201.14:58:59.27#ibcon#read 6, iclass 7, count 2 2006.201.14:58:59.27#ibcon#end of sib2, iclass 7, count 2 2006.201.14:58:59.27#ibcon#*after write, iclass 7, count 2 2006.201.14:58:59.27#ibcon#*before return 0, iclass 7, count 2 2006.201.14:58:59.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:58:59.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:58:59.27#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.14:58:59.27#ibcon#ireg 7 cls_cnt 0 2006.201.14:58:59.27#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:58:59.39#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:58:59.39#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:58:59.39#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:58:59.39#ibcon#first serial, iclass 7, count 0 2006.201.14:58:59.39#ibcon#enter sib2, iclass 7, count 0 2006.201.14:58:59.39#ibcon#flushed, iclass 7, count 0 2006.201.14:58:59.39#ibcon#about to write, iclass 7, count 0 2006.201.14:58:59.39#ibcon#wrote, iclass 7, count 0 2006.201.14:58:59.39#ibcon#about to read 3, iclass 7, count 0 2006.201.14:58:59.41#ibcon#read 3, iclass 7, count 0 2006.201.14:58:59.41#ibcon#about to read 4, iclass 7, count 0 2006.201.14:58:59.41#ibcon#read 4, iclass 7, count 0 2006.201.14:58:59.41#ibcon#about to read 5, iclass 7, count 0 2006.201.14:58:59.41#ibcon#read 5, iclass 7, count 0 2006.201.14:58:59.41#ibcon#about to read 6, iclass 7, count 0 2006.201.14:58:59.41#ibcon#read 6, iclass 7, count 0 2006.201.14:58:59.41#ibcon#end of sib2, iclass 7, count 0 2006.201.14:58:59.41#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:58:59.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:58:59.41#ibcon#[25=USB\r\n] 2006.201.14:58:59.41#ibcon#*before write, iclass 7, count 0 2006.201.14:58:59.41#ibcon#enter sib2, iclass 7, count 0 2006.201.14:58:59.41#ibcon#flushed, iclass 7, count 0 2006.201.14:58:59.41#ibcon#about to write, iclass 7, count 0 2006.201.14:58:59.41#ibcon#wrote, iclass 7, count 0 2006.201.14:58:59.41#ibcon#about to read 3, iclass 7, count 0 2006.201.14:58:59.44#ibcon#read 3, iclass 7, count 0 2006.201.14:58:59.44#ibcon#about to read 4, iclass 7, count 0 2006.201.14:58:59.44#ibcon#read 4, iclass 7, count 0 2006.201.14:58:59.44#ibcon#about to read 5, iclass 7, count 0 2006.201.14:58:59.44#ibcon#read 5, iclass 7, count 0 2006.201.14:58:59.44#ibcon#about to read 6, iclass 7, count 0 2006.201.14:58:59.44#ibcon#read 6, iclass 7, count 0 2006.201.14:58:59.44#ibcon#end of sib2, iclass 7, count 0 2006.201.14:58:59.44#ibcon#*after write, iclass 7, count 0 2006.201.14:58:59.44#ibcon#*before return 0, iclass 7, count 0 2006.201.14:58:59.44#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:58:59.44#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:58:59.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:58:59.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:58:59.44$vck44/valo=2,534.99 2006.201.14:58:59.44#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.14:58:59.44#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.14:58:59.44#ibcon#ireg 17 cls_cnt 0 2006.201.14:58:59.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:58:59.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:58:59.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:58:59.44#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:58:59.44#ibcon#first serial, iclass 11, count 0 2006.201.14:58:59.44#ibcon#enter sib2, iclass 11, count 0 2006.201.14:58:59.44#ibcon#flushed, iclass 11, count 0 2006.201.14:58:59.44#ibcon#about to write, iclass 11, count 0 2006.201.14:58:59.44#ibcon#wrote, iclass 11, count 0 2006.201.14:58:59.44#ibcon#about to read 3, iclass 11, count 0 2006.201.14:58:59.46#ibcon#read 3, iclass 11, count 0 2006.201.14:58:59.46#ibcon#about to read 4, iclass 11, count 0 2006.201.14:58:59.46#ibcon#read 4, iclass 11, count 0 2006.201.14:58:59.46#ibcon#about to read 5, iclass 11, count 0 2006.201.14:58:59.46#ibcon#read 5, iclass 11, count 0 2006.201.14:58:59.46#ibcon#about to read 6, iclass 11, count 0 2006.201.14:58:59.46#ibcon#read 6, iclass 11, count 0 2006.201.14:58:59.46#ibcon#end of sib2, iclass 11, count 0 2006.201.14:58:59.46#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:58:59.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:58:59.46#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.14:58:59.46#ibcon#*before write, iclass 11, count 0 2006.201.14:58:59.46#ibcon#enter sib2, iclass 11, count 0 2006.201.14:58:59.46#ibcon#flushed, iclass 11, count 0 2006.201.14:58:59.46#ibcon#about to write, iclass 11, count 0 2006.201.14:58:59.46#ibcon#wrote, iclass 11, count 0 2006.201.14:58:59.46#ibcon#about to read 3, iclass 11, count 0 2006.201.14:58:59.51#ibcon#read 3, iclass 11, count 0 2006.201.14:58:59.51#ibcon#about to read 4, iclass 11, count 0 2006.201.14:58:59.51#ibcon#read 4, iclass 11, count 0 2006.201.14:58:59.51#ibcon#about to read 5, iclass 11, count 0 2006.201.14:58:59.51#ibcon#read 5, iclass 11, count 0 2006.201.14:58:59.51#ibcon#about to read 6, iclass 11, count 0 2006.201.14:58:59.51#ibcon#read 6, iclass 11, count 0 2006.201.14:58:59.51#ibcon#end of sib2, iclass 11, count 0 2006.201.14:58:59.51#ibcon#*after write, iclass 11, count 0 2006.201.14:58:59.51#ibcon#*before return 0, iclass 11, count 0 2006.201.14:58:59.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:58:59.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:58:59.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:58:59.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:58:59.51$vck44/va=2,7 2006.201.14:58:59.51#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.14:58:59.51#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.14:58:59.51#ibcon#ireg 11 cls_cnt 2 2006.201.14:58:59.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:58:59.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:58:59.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:58:59.56#ibcon#enter wrdev, iclass 13, count 2 2006.201.14:58:59.56#ibcon#first serial, iclass 13, count 2 2006.201.14:58:59.56#ibcon#enter sib2, iclass 13, count 2 2006.201.14:58:59.56#ibcon#flushed, iclass 13, count 2 2006.201.14:58:59.56#ibcon#about to write, iclass 13, count 2 2006.201.14:58:59.56#ibcon#wrote, iclass 13, count 2 2006.201.14:58:59.56#ibcon#about to read 3, iclass 13, count 2 2006.201.14:58:59.58#ibcon#read 3, iclass 13, count 2 2006.201.14:58:59.58#ibcon#about to read 4, iclass 13, count 2 2006.201.14:58:59.58#ibcon#read 4, iclass 13, count 2 2006.201.14:58:59.58#ibcon#about to read 5, iclass 13, count 2 2006.201.14:58:59.58#ibcon#read 5, iclass 13, count 2 2006.201.14:58:59.58#ibcon#about to read 6, iclass 13, count 2 2006.201.14:58:59.58#ibcon#read 6, iclass 13, count 2 2006.201.14:58:59.58#ibcon#end of sib2, iclass 13, count 2 2006.201.14:58:59.58#ibcon#*mode == 0, iclass 13, count 2 2006.201.14:58:59.58#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.14:58:59.58#ibcon#[25=AT02-07\r\n] 2006.201.14:58:59.58#ibcon#*before write, iclass 13, count 2 2006.201.14:58:59.58#ibcon#enter sib2, iclass 13, count 2 2006.201.14:58:59.58#ibcon#flushed, iclass 13, count 2 2006.201.14:58:59.58#ibcon#about to write, iclass 13, count 2 2006.201.14:58:59.58#ibcon#wrote, iclass 13, count 2 2006.201.14:58:59.58#ibcon#about to read 3, iclass 13, count 2 2006.201.14:58:59.61#ibcon#read 3, iclass 13, count 2 2006.201.14:58:59.61#ibcon#about to read 4, iclass 13, count 2 2006.201.14:58:59.61#ibcon#read 4, iclass 13, count 2 2006.201.14:58:59.61#ibcon#about to read 5, iclass 13, count 2 2006.201.14:58:59.61#ibcon#read 5, iclass 13, count 2 2006.201.14:58:59.61#ibcon#about to read 6, iclass 13, count 2 2006.201.14:58:59.61#ibcon#read 6, iclass 13, count 2 2006.201.14:58:59.61#ibcon#end of sib2, iclass 13, count 2 2006.201.14:58:59.61#ibcon#*after write, iclass 13, count 2 2006.201.14:58:59.61#ibcon#*before return 0, iclass 13, count 2 2006.201.14:58:59.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:58:59.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:58:59.61#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.14:58:59.61#ibcon#ireg 7 cls_cnt 0 2006.201.14:58:59.61#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:58:59.73#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:58:59.73#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:58:59.73#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:58:59.73#ibcon#first serial, iclass 13, count 0 2006.201.14:58:59.73#ibcon#enter sib2, iclass 13, count 0 2006.201.14:58:59.73#ibcon#flushed, iclass 13, count 0 2006.201.14:58:59.73#ibcon#about to write, iclass 13, count 0 2006.201.14:58:59.73#ibcon#wrote, iclass 13, count 0 2006.201.14:58:59.73#ibcon#about to read 3, iclass 13, count 0 2006.201.14:58:59.75#ibcon#read 3, iclass 13, count 0 2006.201.14:58:59.75#ibcon#about to read 4, iclass 13, count 0 2006.201.14:58:59.75#ibcon#read 4, iclass 13, count 0 2006.201.14:58:59.75#ibcon#about to read 5, iclass 13, count 0 2006.201.14:58:59.75#ibcon#read 5, iclass 13, count 0 2006.201.14:58:59.75#ibcon#about to read 6, iclass 13, count 0 2006.201.14:58:59.75#ibcon#read 6, iclass 13, count 0 2006.201.14:58:59.75#ibcon#end of sib2, iclass 13, count 0 2006.201.14:58:59.75#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:58:59.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:58:59.75#ibcon#[25=USB\r\n] 2006.201.14:58:59.75#ibcon#*before write, iclass 13, count 0 2006.201.14:58:59.75#ibcon#enter sib2, iclass 13, count 0 2006.201.14:58:59.75#ibcon#flushed, iclass 13, count 0 2006.201.14:58:59.75#ibcon#about to write, iclass 13, count 0 2006.201.14:58:59.75#ibcon#wrote, iclass 13, count 0 2006.201.14:58:59.75#ibcon#about to read 3, iclass 13, count 0 2006.201.14:58:59.78#ibcon#read 3, iclass 13, count 0 2006.201.14:58:59.78#ibcon#about to read 4, iclass 13, count 0 2006.201.14:58:59.78#ibcon#read 4, iclass 13, count 0 2006.201.14:58:59.78#ibcon#about to read 5, iclass 13, count 0 2006.201.14:58:59.78#ibcon#read 5, iclass 13, count 0 2006.201.14:58:59.78#ibcon#about to read 6, iclass 13, count 0 2006.201.14:58:59.78#ibcon#read 6, iclass 13, count 0 2006.201.14:58:59.78#ibcon#end of sib2, iclass 13, count 0 2006.201.14:58:59.78#ibcon#*after write, iclass 13, count 0 2006.201.14:58:59.78#ibcon#*before return 0, iclass 13, count 0 2006.201.14:58:59.78#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:58:59.78#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:58:59.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:58:59.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:58:59.78$vck44/valo=3,564.99 2006.201.14:58:59.78#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.14:58:59.78#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.14:58:59.78#ibcon#ireg 17 cls_cnt 0 2006.201.14:58:59.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:58:59.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:58:59.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:58:59.78#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:58:59.78#ibcon#first serial, iclass 15, count 0 2006.201.14:58:59.78#ibcon#enter sib2, iclass 15, count 0 2006.201.14:58:59.78#ibcon#flushed, iclass 15, count 0 2006.201.14:58:59.78#ibcon#about to write, iclass 15, count 0 2006.201.14:58:59.78#ibcon#wrote, iclass 15, count 0 2006.201.14:58:59.78#ibcon#about to read 3, iclass 15, count 0 2006.201.14:58:59.80#ibcon#read 3, iclass 15, count 0 2006.201.14:58:59.80#ibcon#about to read 4, iclass 15, count 0 2006.201.14:58:59.80#ibcon#read 4, iclass 15, count 0 2006.201.14:58:59.80#ibcon#about to read 5, iclass 15, count 0 2006.201.14:58:59.80#ibcon#read 5, iclass 15, count 0 2006.201.14:58:59.80#ibcon#about to read 6, iclass 15, count 0 2006.201.14:58:59.80#ibcon#read 6, iclass 15, count 0 2006.201.14:58:59.80#ibcon#end of sib2, iclass 15, count 0 2006.201.14:58:59.80#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:58:59.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:58:59.80#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.14:58:59.80#ibcon#*before write, iclass 15, count 0 2006.201.14:58:59.80#ibcon#enter sib2, iclass 15, count 0 2006.201.14:58:59.80#ibcon#flushed, iclass 15, count 0 2006.201.14:58:59.80#ibcon#about to write, iclass 15, count 0 2006.201.14:58:59.80#ibcon#wrote, iclass 15, count 0 2006.201.14:58:59.80#ibcon#about to read 3, iclass 15, count 0 2006.201.14:58:59.85#ibcon#read 3, iclass 15, count 0 2006.201.14:58:59.85#ibcon#about to read 4, iclass 15, count 0 2006.201.14:58:59.85#ibcon#read 4, iclass 15, count 0 2006.201.14:58:59.85#ibcon#about to read 5, iclass 15, count 0 2006.201.14:58:59.85#ibcon#read 5, iclass 15, count 0 2006.201.14:58:59.85#ibcon#about to read 6, iclass 15, count 0 2006.201.14:58:59.85#ibcon#read 6, iclass 15, count 0 2006.201.14:58:59.85#ibcon#end of sib2, iclass 15, count 0 2006.201.14:58:59.85#ibcon#*after write, iclass 15, count 0 2006.201.14:58:59.85#ibcon#*before return 0, iclass 15, count 0 2006.201.14:58:59.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:58:59.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:58:59.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:58:59.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:58:59.85$vck44/va=3,8 2006.201.14:58:59.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.14:58:59.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.14:58:59.85#ibcon#ireg 11 cls_cnt 2 2006.201.14:58:59.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:58:59.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:58:59.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:58:59.90#ibcon#enter wrdev, iclass 17, count 2 2006.201.14:58:59.90#ibcon#first serial, iclass 17, count 2 2006.201.14:58:59.90#ibcon#enter sib2, iclass 17, count 2 2006.201.14:58:59.90#ibcon#flushed, iclass 17, count 2 2006.201.14:58:59.90#ibcon#about to write, iclass 17, count 2 2006.201.14:58:59.90#ibcon#wrote, iclass 17, count 2 2006.201.14:58:59.90#ibcon#about to read 3, iclass 17, count 2 2006.201.14:58:59.92#ibcon#read 3, iclass 17, count 2 2006.201.14:58:59.92#ibcon#about to read 4, iclass 17, count 2 2006.201.14:58:59.92#ibcon#read 4, iclass 17, count 2 2006.201.14:58:59.92#ibcon#about to read 5, iclass 17, count 2 2006.201.14:58:59.92#ibcon#read 5, iclass 17, count 2 2006.201.14:58:59.92#ibcon#about to read 6, iclass 17, count 2 2006.201.14:58:59.92#ibcon#read 6, iclass 17, count 2 2006.201.14:58:59.92#ibcon#end of sib2, iclass 17, count 2 2006.201.14:58:59.92#ibcon#*mode == 0, iclass 17, count 2 2006.201.14:58:59.92#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.14:58:59.92#ibcon#[25=AT03-08\r\n] 2006.201.14:58:59.92#ibcon#*before write, iclass 17, count 2 2006.201.14:58:59.92#ibcon#enter sib2, iclass 17, count 2 2006.201.14:58:59.92#ibcon#flushed, iclass 17, count 2 2006.201.14:58:59.92#ibcon#about to write, iclass 17, count 2 2006.201.14:58:59.92#ibcon#wrote, iclass 17, count 2 2006.201.14:58:59.92#ibcon#about to read 3, iclass 17, count 2 2006.201.14:58:59.95#ibcon#read 3, iclass 17, count 2 2006.201.14:58:59.95#ibcon#about to read 4, iclass 17, count 2 2006.201.14:58:59.95#ibcon#read 4, iclass 17, count 2 2006.201.14:58:59.95#ibcon#about to read 5, iclass 17, count 2 2006.201.14:58:59.95#ibcon#read 5, iclass 17, count 2 2006.201.14:58:59.95#ibcon#about to read 6, iclass 17, count 2 2006.201.14:58:59.95#ibcon#read 6, iclass 17, count 2 2006.201.14:58:59.95#ibcon#end of sib2, iclass 17, count 2 2006.201.14:58:59.95#ibcon#*after write, iclass 17, count 2 2006.201.14:58:59.95#ibcon#*before return 0, iclass 17, count 2 2006.201.14:58:59.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:58:59.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:58:59.95#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.14:58:59.95#ibcon#ireg 7 cls_cnt 0 2006.201.14:58:59.95#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:00.07#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:00.07#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:00.07#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:59:00.07#ibcon#first serial, iclass 17, count 0 2006.201.14:59:00.07#ibcon#enter sib2, iclass 17, count 0 2006.201.14:59:00.07#ibcon#flushed, iclass 17, count 0 2006.201.14:59:00.07#ibcon#about to write, iclass 17, count 0 2006.201.14:59:00.07#ibcon#wrote, iclass 17, count 0 2006.201.14:59:00.07#ibcon#about to read 3, iclass 17, count 0 2006.201.14:59:00.09#ibcon#read 3, iclass 17, count 0 2006.201.14:59:00.09#ibcon#about to read 4, iclass 17, count 0 2006.201.14:59:00.09#ibcon#read 4, iclass 17, count 0 2006.201.14:59:00.09#ibcon#about to read 5, iclass 17, count 0 2006.201.14:59:00.09#ibcon#read 5, iclass 17, count 0 2006.201.14:59:00.09#ibcon#about to read 6, iclass 17, count 0 2006.201.14:59:00.09#ibcon#read 6, iclass 17, count 0 2006.201.14:59:00.09#ibcon#end of sib2, iclass 17, count 0 2006.201.14:59:00.09#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:59:00.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:59:00.09#ibcon#[25=USB\r\n] 2006.201.14:59:00.09#ibcon#*before write, iclass 17, count 0 2006.201.14:59:00.09#ibcon#enter sib2, iclass 17, count 0 2006.201.14:59:00.09#ibcon#flushed, iclass 17, count 0 2006.201.14:59:00.09#ibcon#about to write, iclass 17, count 0 2006.201.14:59:00.09#ibcon#wrote, iclass 17, count 0 2006.201.14:59:00.09#ibcon#about to read 3, iclass 17, count 0 2006.201.14:59:00.12#ibcon#read 3, iclass 17, count 0 2006.201.14:59:00.12#ibcon#about to read 4, iclass 17, count 0 2006.201.14:59:00.12#ibcon#read 4, iclass 17, count 0 2006.201.14:59:00.12#ibcon#about to read 5, iclass 17, count 0 2006.201.14:59:00.12#ibcon#read 5, iclass 17, count 0 2006.201.14:59:00.12#ibcon#about to read 6, iclass 17, count 0 2006.201.14:59:00.12#ibcon#read 6, iclass 17, count 0 2006.201.14:59:00.12#ibcon#end of sib2, iclass 17, count 0 2006.201.14:59:00.12#ibcon#*after write, iclass 17, count 0 2006.201.14:59:00.12#ibcon#*before return 0, iclass 17, count 0 2006.201.14:59:00.12#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:00.12#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:00.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:59:00.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:59:00.12$vck44/valo=4,624.99 2006.201.14:59:00.12#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.14:59:00.12#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.14:59:00.12#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:00.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:00.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:00.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:00.12#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:59:00.12#ibcon#first serial, iclass 19, count 0 2006.201.14:59:00.12#ibcon#enter sib2, iclass 19, count 0 2006.201.14:59:00.12#ibcon#flushed, iclass 19, count 0 2006.201.14:59:00.12#ibcon#about to write, iclass 19, count 0 2006.201.14:59:00.12#ibcon#wrote, iclass 19, count 0 2006.201.14:59:00.12#ibcon#about to read 3, iclass 19, count 0 2006.201.14:59:00.14#ibcon#read 3, iclass 19, count 0 2006.201.14:59:00.14#ibcon#about to read 4, iclass 19, count 0 2006.201.14:59:00.14#ibcon#read 4, iclass 19, count 0 2006.201.14:59:00.14#ibcon#about to read 5, iclass 19, count 0 2006.201.14:59:00.14#ibcon#read 5, iclass 19, count 0 2006.201.14:59:00.14#ibcon#about to read 6, iclass 19, count 0 2006.201.14:59:00.14#ibcon#read 6, iclass 19, count 0 2006.201.14:59:00.14#ibcon#end of sib2, iclass 19, count 0 2006.201.14:59:00.14#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:59:00.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:59:00.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.14:59:00.14#ibcon#*before write, iclass 19, count 0 2006.201.14:59:00.14#ibcon#enter sib2, iclass 19, count 0 2006.201.14:59:00.14#ibcon#flushed, iclass 19, count 0 2006.201.14:59:00.14#ibcon#about to write, iclass 19, count 0 2006.201.14:59:00.14#ibcon#wrote, iclass 19, count 0 2006.201.14:59:00.14#ibcon#about to read 3, iclass 19, count 0 2006.201.14:59:00.19#ibcon#read 3, iclass 19, count 0 2006.201.14:59:00.19#ibcon#about to read 4, iclass 19, count 0 2006.201.14:59:00.19#ibcon#read 4, iclass 19, count 0 2006.201.14:59:00.19#ibcon#about to read 5, iclass 19, count 0 2006.201.14:59:00.19#ibcon#read 5, iclass 19, count 0 2006.201.14:59:00.19#ibcon#about to read 6, iclass 19, count 0 2006.201.14:59:00.19#ibcon#read 6, iclass 19, count 0 2006.201.14:59:00.19#ibcon#end of sib2, iclass 19, count 0 2006.201.14:59:00.19#ibcon#*after write, iclass 19, count 0 2006.201.14:59:00.19#ibcon#*before return 0, iclass 19, count 0 2006.201.14:59:00.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:00.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:00.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:59:00.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:59:00.19$vck44/va=4,7 2006.201.14:59:00.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.14:59:00.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.14:59:00.19#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:00.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:00.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:00.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:00.24#ibcon#enter wrdev, iclass 21, count 2 2006.201.14:59:00.24#ibcon#first serial, iclass 21, count 2 2006.201.14:59:00.24#ibcon#enter sib2, iclass 21, count 2 2006.201.14:59:00.24#ibcon#flushed, iclass 21, count 2 2006.201.14:59:00.24#ibcon#about to write, iclass 21, count 2 2006.201.14:59:00.24#ibcon#wrote, iclass 21, count 2 2006.201.14:59:00.24#ibcon#about to read 3, iclass 21, count 2 2006.201.14:59:00.26#ibcon#read 3, iclass 21, count 2 2006.201.14:59:00.26#ibcon#about to read 4, iclass 21, count 2 2006.201.14:59:00.26#ibcon#read 4, iclass 21, count 2 2006.201.14:59:00.26#ibcon#about to read 5, iclass 21, count 2 2006.201.14:59:00.26#ibcon#read 5, iclass 21, count 2 2006.201.14:59:00.26#ibcon#about to read 6, iclass 21, count 2 2006.201.14:59:00.26#ibcon#read 6, iclass 21, count 2 2006.201.14:59:00.26#ibcon#end of sib2, iclass 21, count 2 2006.201.14:59:00.26#ibcon#*mode == 0, iclass 21, count 2 2006.201.14:59:00.26#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.14:59:00.26#ibcon#[25=AT04-07\r\n] 2006.201.14:59:00.26#ibcon#*before write, iclass 21, count 2 2006.201.14:59:00.26#ibcon#enter sib2, iclass 21, count 2 2006.201.14:59:00.26#ibcon#flushed, iclass 21, count 2 2006.201.14:59:00.26#ibcon#about to write, iclass 21, count 2 2006.201.14:59:00.26#ibcon#wrote, iclass 21, count 2 2006.201.14:59:00.26#ibcon#about to read 3, iclass 21, count 2 2006.201.14:59:00.29#ibcon#read 3, iclass 21, count 2 2006.201.14:59:00.29#ibcon#about to read 4, iclass 21, count 2 2006.201.14:59:00.29#ibcon#read 4, iclass 21, count 2 2006.201.14:59:00.29#ibcon#about to read 5, iclass 21, count 2 2006.201.14:59:00.29#ibcon#read 5, iclass 21, count 2 2006.201.14:59:00.29#ibcon#about to read 6, iclass 21, count 2 2006.201.14:59:00.29#ibcon#read 6, iclass 21, count 2 2006.201.14:59:00.29#ibcon#end of sib2, iclass 21, count 2 2006.201.14:59:00.29#ibcon#*after write, iclass 21, count 2 2006.201.14:59:00.29#ibcon#*before return 0, iclass 21, count 2 2006.201.14:59:00.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:00.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:00.29#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.14:59:00.29#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:00.29#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:00.41#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:00.41#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:00.41#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:59:00.41#ibcon#first serial, iclass 21, count 0 2006.201.14:59:00.41#ibcon#enter sib2, iclass 21, count 0 2006.201.14:59:00.41#ibcon#flushed, iclass 21, count 0 2006.201.14:59:00.41#ibcon#about to write, iclass 21, count 0 2006.201.14:59:00.41#ibcon#wrote, iclass 21, count 0 2006.201.14:59:00.41#ibcon#about to read 3, iclass 21, count 0 2006.201.14:59:00.43#ibcon#read 3, iclass 21, count 0 2006.201.14:59:00.43#ibcon#about to read 4, iclass 21, count 0 2006.201.14:59:00.43#ibcon#read 4, iclass 21, count 0 2006.201.14:59:00.43#ibcon#about to read 5, iclass 21, count 0 2006.201.14:59:00.43#ibcon#read 5, iclass 21, count 0 2006.201.14:59:00.43#ibcon#about to read 6, iclass 21, count 0 2006.201.14:59:00.43#ibcon#read 6, iclass 21, count 0 2006.201.14:59:00.43#ibcon#end of sib2, iclass 21, count 0 2006.201.14:59:00.43#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:59:00.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:59:00.43#ibcon#[25=USB\r\n] 2006.201.14:59:00.43#ibcon#*before write, iclass 21, count 0 2006.201.14:59:00.43#ibcon#enter sib2, iclass 21, count 0 2006.201.14:59:00.43#ibcon#flushed, iclass 21, count 0 2006.201.14:59:00.43#ibcon#about to write, iclass 21, count 0 2006.201.14:59:00.43#ibcon#wrote, iclass 21, count 0 2006.201.14:59:00.43#ibcon#about to read 3, iclass 21, count 0 2006.201.14:59:00.46#ibcon#read 3, iclass 21, count 0 2006.201.14:59:00.46#ibcon#about to read 4, iclass 21, count 0 2006.201.14:59:00.46#ibcon#read 4, iclass 21, count 0 2006.201.14:59:00.46#ibcon#about to read 5, iclass 21, count 0 2006.201.14:59:00.46#ibcon#read 5, iclass 21, count 0 2006.201.14:59:00.46#ibcon#about to read 6, iclass 21, count 0 2006.201.14:59:00.46#ibcon#read 6, iclass 21, count 0 2006.201.14:59:00.46#ibcon#end of sib2, iclass 21, count 0 2006.201.14:59:00.46#ibcon#*after write, iclass 21, count 0 2006.201.14:59:00.46#ibcon#*before return 0, iclass 21, count 0 2006.201.14:59:00.46#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:00.46#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:00.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:59:00.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:59:00.46$vck44/valo=5,734.99 2006.201.14:59:00.46#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.14:59:00.46#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.14:59:00.46#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:00.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:00.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:00.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:00.46#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:59:00.46#ibcon#first serial, iclass 23, count 0 2006.201.14:59:00.46#ibcon#enter sib2, iclass 23, count 0 2006.201.14:59:00.46#ibcon#flushed, iclass 23, count 0 2006.201.14:59:00.46#ibcon#about to write, iclass 23, count 0 2006.201.14:59:00.46#ibcon#wrote, iclass 23, count 0 2006.201.14:59:00.46#ibcon#about to read 3, iclass 23, count 0 2006.201.14:59:00.48#ibcon#read 3, iclass 23, count 0 2006.201.14:59:00.48#ibcon#about to read 4, iclass 23, count 0 2006.201.14:59:00.48#ibcon#read 4, iclass 23, count 0 2006.201.14:59:00.48#ibcon#about to read 5, iclass 23, count 0 2006.201.14:59:00.48#ibcon#read 5, iclass 23, count 0 2006.201.14:59:00.48#ibcon#about to read 6, iclass 23, count 0 2006.201.14:59:00.48#ibcon#read 6, iclass 23, count 0 2006.201.14:59:00.48#ibcon#end of sib2, iclass 23, count 0 2006.201.14:59:00.48#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:59:00.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:59:00.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.14:59:00.48#ibcon#*before write, iclass 23, count 0 2006.201.14:59:00.48#ibcon#enter sib2, iclass 23, count 0 2006.201.14:59:00.48#ibcon#flushed, iclass 23, count 0 2006.201.14:59:00.48#ibcon#about to write, iclass 23, count 0 2006.201.14:59:00.48#ibcon#wrote, iclass 23, count 0 2006.201.14:59:00.48#ibcon#about to read 3, iclass 23, count 0 2006.201.14:59:00.52#ibcon#read 3, iclass 23, count 0 2006.201.14:59:00.52#ibcon#about to read 4, iclass 23, count 0 2006.201.14:59:00.52#ibcon#read 4, iclass 23, count 0 2006.201.14:59:00.52#ibcon#about to read 5, iclass 23, count 0 2006.201.14:59:00.52#ibcon#read 5, iclass 23, count 0 2006.201.14:59:00.52#ibcon#about to read 6, iclass 23, count 0 2006.201.14:59:00.52#ibcon#read 6, iclass 23, count 0 2006.201.14:59:00.52#ibcon#end of sib2, iclass 23, count 0 2006.201.14:59:00.52#ibcon#*after write, iclass 23, count 0 2006.201.14:59:00.52#ibcon#*before return 0, iclass 23, count 0 2006.201.14:59:00.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:00.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:00.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:59:00.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:59:00.52$vck44/va=5,4 2006.201.14:59:00.52#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.14:59:00.52#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.14:59:00.52#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:00.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:00.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:00.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:00.58#ibcon#enter wrdev, iclass 25, count 2 2006.201.14:59:00.58#ibcon#first serial, iclass 25, count 2 2006.201.14:59:00.58#ibcon#enter sib2, iclass 25, count 2 2006.201.14:59:00.58#ibcon#flushed, iclass 25, count 2 2006.201.14:59:00.58#ibcon#about to write, iclass 25, count 2 2006.201.14:59:00.58#ibcon#wrote, iclass 25, count 2 2006.201.14:59:00.58#ibcon#about to read 3, iclass 25, count 2 2006.201.14:59:00.60#ibcon#read 3, iclass 25, count 2 2006.201.14:59:00.60#ibcon#about to read 4, iclass 25, count 2 2006.201.14:59:00.60#ibcon#read 4, iclass 25, count 2 2006.201.14:59:00.60#ibcon#about to read 5, iclass 25, count 2 2006.201.14:59:00.60#ibcon#read 5, iclass 25, count 2 2006.201.14:59:00.60#ibcon#about to read 6, iclass 25, count 2 2006.201.14:59:00.60#ibcon#read 6, iclass 25, count 2 2006.201.14:59:00.60#ibcon#end of sib2, iclass 25, count 2 2006.201.14:59:00.60#ibcon#*mode == 0, iclass 25, count 2 2006.201.14:59:00.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.14:59:00.60#ibcon#[25=AT05-04\r\n] 2006.201.14:59:00.60#ibcon#*before write, iclass 25, count 2 2006.201.14:59:00.60#ibcon#enter sib2, iclass 25, count 2 2006.201.14:59:00.60#ibcon#flushed, iclass 25, count 2 2006.201.14:59:00.60#ibcon#about to write, iclass 25, count 2 2006.201.14:59:00.60#ibcon#wrote, iclass 25, count 2 2006.201.14:59:00.60#ibcon#about to read 3, iclass 25, count 2 2006.201.14:59:00.63#ibcon#read 3, iclass 25, count 2 2006.201.14:59:00.63#ibcon#about to read 4, iclass 25, count 2 2006.201.14:59:00.63#ibcon#read 4, iclass 25, count 2 2006.201.14:59:00.63#ibcon#about to read 5, iclass 25, count 2 2006.201.14:59:00.63#ibcon#read 5, iclass 25, count 2 2006.201.14:59:00.63#ibcon#about to read 6, iclass 25, count 2 2006.201.14:59:00.63#ibcon#read 6, iclass 25, count 2 2006.201.14:59:00.63#ibcon#end of sib2, iclass 25, count 2 2006.201.14:59:00.63#ibcon#*after write, iclass 25, count 2 2006.201.14:59:00.63#ibcon#*before return 0, iclass 25, count 2 2006.201.14:59:00.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:00.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:00.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.14:59:00.63#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:00.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:00.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:00.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:00.75#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:59:00.75#ibcon#first serial, iclass 25, count 0 2006.201.14:59:00.75#ibcon#enter sib2, iclass 25, count 0 2006.201.14:59:00.75#ibcon#flushed, iclass 25, count 0 2006.201.14:59:00.75#ibcon#about to write, iclass 25, count 0 2006.201.14:59:00.75#ibcon#wrote, iclass 25, count 0 2006.201.14:59:00.75#ibcon#about to read 3, iclass 25, count 0 2006.201.14:59:00.77#ibcon#read 3, iclass 25, count 0 2006.201.14:59:00.77#ibcon#about to read 4, iclass 25, count 0 2006.201.14:59:00.77#ibcon#read 4, iclass 25, count 0 2006.201.14:59:00.77#ibcon#about to read 5, iclass 25, count 0 2006.201.14:59:00.77#ibcon#read 5, iclass 25, count 0 2006.201.14:59:00.77#ibcon#about to read 6, iclass 25, count 0 2006.201.14:59:00.77#ibcon#read 6, iclass 25, count 0 2006.201.14:59:00.77#ibcon#end of sib2, iclass 25, count 0 2006.201.14:59:00.77#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:59:00.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:59:00.77#ibcon#[25=USB\r\n] 2006.201.14:59:00.77#ibcon#*before write, iclass 25, count 0 2006.201.14:59:00.77#ibcon#enter sib2, iclass 25, count 0 2006.201.14:59:00.77#ibcon#flushed, iclass 25, count 0 2006.201.14:59:00.77#ibcon#about to write, iclass 25, count 0 2006.201.14:59:00.77#ibcon#wrote, iclass 25, count 0 2006.201.14:59:00.77#ibcon#about to read 3, iclass 25, count 0 2006.201.14:59:00.80#ibcon#read 3, iclass 25, count 0 2006.201.14:59:00.80#ibcon#about to read 4, iclass 25, count 0 2006.201.14:59:00.80#ibcon#read 4, iclass 25, count 0 2006.201.14:59:00.80#ibcon#about to read 5, iclass 25, count 0 2006.201.14:59:00.80#ibcon#read 5, iclass 25, count 0 2006.201.14:59:00.80#ibcon#about to read 6, iclass 25, count 0 2006.201.14:59:00.80#ibcon#read 6, iclass 25, count 0 2006.201.14:59:00.80#ibcon#end of sib2, iclass 25, count 0 2006.201.14:59:00.80#ibcon#*after write, iclass 25, count 0 2006.201.14:59:00.80#ibcon#*before return 0, iclass 25, count 0 2006.201.14:59:00.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:00.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:00.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:59:00.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:59:00.80$vck44/valo=6,814.99 2006.201.14:59:00.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.14:59:00.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.14:59:00.80#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:00.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:00.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:00.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:00.80#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:59:00.80#ibcon#first serial, iclass 27, count 0 2006.201.14:59:00.80#ibcon#enter sib2, iclass 27, count 0 2006.201.14:59:00.80#ibcon#flushed, iclass 27, count 0 2006.201.14:59:00.80#ibcon#about to write, iclass 27, count 0 2006.201.14:59:00.80#ibcon#wrote, iclass 27, count 0 2006.201.14:59:00.80#ibcon#about to read 3, iclass 27, count 0 2006.201.14:59:00.82#ibcon#read 3, iclass 27, count 0 2006.201.14:59:00.82#ibcon#about to read 4, iclass 27, count 0 2006.201.14:59:00.82#ibcon#read 4, iclass 27, count 0 2006.201.14:59:00.82#ibcon#about to read 5, iclass 27, count 0 2006.201.14:59:00.82#ibcon#read 5, iclass 27, count 0 2006.201.14:59:00.82#ibcon#about to read 6, iclass 27, count 0 2006.201.14:59:00.82#ibcon#read 6, iclass 27, count 0 2006.201.14:59:00.82#ibcon#end of sib2, iclass 27, count 0 2006.201.14:59:00.82#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:59:00.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:59:00.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.14:59:00.82#ibcon#*before write, iclass 27, count 0 2006.201.14:59:00.82#ibcon#enter sib2, iclass 27, count 0 2006.201.14:59:00.82#ibcon#flushed, iclass 27, count 0 2006.201.14:59:00.82#ibcon#about to write, iclass 27, count 0 2006.201.14:59:00.82#ibcon#wrote, iclass 27, count 0 2006.201.14:59:00.82#ibcon#about to read 3, iclass 27, count 0 2006.201.14:59:00.87#ibcon#read 3, iclass 27, count 0 2006.201.14:59:00.87#ibcon#about to read 4, iclass 27, count 0 2006.201.14:59:00.87#ibcon#read 4, iclass 27, count 0 2006.201.14:59:00.87#ibcon#about to read 5, iclass 27, count 0 2006.201.14:59:00.87#ibcon#read 5, iclass 27, count 0 2006.201.14:59:00.87#ibcon#about to read 6, iclass 27, count 0 2006.201.14:59:00.87#ibcon#read 6, iclass 27, count 0 2006.201.14:59:00.87#ibcon#end of sib2, iclass 27, count 0 2006.201.14:59:00.87#ibcon#*after write, iclass 27, count 0 2006.201.14:59:00.87#ibcon#*before return 0, iclass 27, count 0 2006.201.14:59:00.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:00.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:00.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:59:00.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:59:00.87$vck44/va=6,5 2006.201.14:59:00.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.14:59:00.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.14:59:00.87#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:00.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:00.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:00.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:00.92#ibcon#enter wrdev, iclass 29, count 2 2006.201.14:59:00.92#ibcon#first serial, iclass 29, count 2 2006.201.14:59:00.92#ibcon#enter sib2, iclass 29, count 2 2006.201.14:59:00.92#ibcon#flushed, iclass 29, count 2 2006.201.14:59:00.92#ibcon#about to write, iclass 29, count 2 2006.201.14:59:00.92#ibcon#wrote, iclass 29, count 2 2006.201.14:59:00.92#ibcon#about to read 3, iclass 29, count 2 2006.201.14:59:00.94#ibcon#read 3, iclass 29, count 2 2006.201.14:59:00.94#ibcon#about to read 4, iclass 29, count 2 2006.201.14:59:00.94#ibcon#read 4, iclass 29, count 2 2006.201.14:59:00.94#ibcon#about to read 5, iclass 29, count 2 2006.201.14:59:00.94#ibcon#read 5, iclass 29, count 2 2006.201.14:59:00.94#ibcon#about to read 6, iclass 29, count 2 2006.201.14:59:00.94#ibcon#read 6, iclass 29, count 2 2006.201.14:59:00.94#ibcon#end of sib2, iclass 29, count 2 2006.201.14:59:00.94#ibcon#*mode == 0, iclass 29, count 2 2006.201.14:59:00.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.14:59:00.94#ibcon#[25=AT06-05\r\n] 2006.201.14:59:00.94#ibcon#*before write, iclass 29, count 2 2006.201.14:59:00.94#ibcon#enter sib2, iclass 29, count 2 2006.201.14:59:00.94#ibcon#flushed, iclass 29, count 2 2006.201.14:59:00.94#ibcon#about to write, iclass 29, count 2 2006.201.14:59:00.94#ibcon#wrote, iclass 29, count 2 2006.201.14:59:00.94#ibcon#about to read 3, iclass 29, count 2 2006.201.14:59:00.97#ibcon#read 3, iclass 29, count 2 2006.201.14:59:00.97#ibcon#about to read 4, iclass 29, count 2 2006.201.14:59:00.97#ibcon#read 4, iclass 29, count 2 2006.201.14:59:00.97#ibcon#about to read 5, iclass 29, count 2 2006.201.14:59:00.97#ibcon#read 5, iclass 29, count 2 2006.201.14:59:00.97#ibcon#about to read 6, iclass 29, count 2 2006.201.14:59:00.97#ibcon#read 6, iclass 29, count 2 2006.201.14:59:00.97#ibcon#end of sib2, iclass 29, count 2 2006.201.14:59:00.97#ibcon#*after write, iclass 29, count 2 2006.201.14:59:00.97#ibcon#*before return 0, iclass 29, count 2 2006.201.14:59:00.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:00.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:00.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.14:59:00.97#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:00.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:01.02#abcon#<5=/04 0.9 1.9 20.761001003.4\r\n> 2006.201.14:59:01.04#abcon#{5=INTERFACE CLEAR} 2006.201.14:59:01.10#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:59:01.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:01.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:01.10#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:59:01.10#ibcon#first serial, iclass 29, count 0 2006.201.14:59:01.10#ibcon#enter sib2, iclass 29, count 0 2006.201.14:59:01.10#ibcon#flushed, iclass 29, count 0 2006.201.14:59:01.10#ibcon#about to write, iclass 29, count 0 2006.201.14:59:01.10#ibcon#wrote, iclass 29, count 0 2006.201.14:59:01.10#ibcon#about to read 3, iclass 29, count 0 2006.201.14:59:01.12#ibcon#read 3, iclass 29, count 0 2006.201.14:59:01.12#ibcon#about to read 4, iclass 29, count 0 2006.201.14:59:01.12#ibcon#read 4, iclass 29, count 0 2006.201.14:59:01.12#ibcon#about to read 5, iclass 29, count 0 2006.201.14:59:01.12#ibcon#read 5, iclass 29, count 0 2006.201.14:59:01.12#ibcon#about to read 6, iclass 29, count 0 2006.201.14:59:01.12#ibcon#read 6, iclass 29, count 0 2006.201.14:59:01.12#ibcon#end of sib2, iclass 29, count 0 2006.201.14:59:01.12#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:59:01.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:59:01.12#ibcon#[25=USB\r\n] 2006.201.14:59:01.12#ibcon#*before write, iclass 29, count 0 2006.201.14:59:01.12#ibcon#enter sib2, iclass 29, count 0 2006.201.14:59:01.12#ibcon#flushed, iclass 29, count 0 2006.201.14:59:01.12#ibcon#about to write, iclass 29, count 0 2006.201.14:59:01.12#ibcon#wrote, iclass 29, count 0 2006.201.14:59:01.12#ibcon#about to read 3, iclass 29, count 0 2006.201.14:59:01.15#ibcon#read 3, iclass 29, count 0 2006.201.14:59:01.15#ibcon#about to read 4, iclass 29, count 0 2006.201.14:59:01.15#ibcon#read 4, iclass 29, count 0 2006.201.14:59:01.15#ibcon#about to read 5, iclass 29, count 0 2006.201.14:59:01.15#ibcon#read 5, iclass 29, count 0 2006.201.14:59:01.15#ibcon#about to read 6, iclass 29, count 0 2006.201.14:59:01.15#ibcon#read 6, iclass 29, count 0 2006.201.14:59:01.15#ibcon#end of sib2, iclass 29, count 0 2006.201.14:59:01.15#ibcon#*after write, iclass 29, count 0 2006.201.14:59:01.15#ibcon#*before return 0, iclass 29, count 0 2006.201.14:59:01.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:01.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:01.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:59:01.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:59:01.15$vck44/valo=7,864.99 2006.201.14:59:01.15#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.14:59:01.15#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.14:59:01.15#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:01.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:01.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:01.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:01.15#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:59:01.15#ibcon#first serial, iclass 35, count 0 2006.201.14:59:01.15#ibcon#enter sib2, iclass 35, count 0 2006.201.14:59:01.15#ibcon#flushed, iclass 35, count 0 2006.201.14:59:01.15#ibcon#about to write, iclass 35, count 0 2006.201.14:59:01.15#ibcon#wrote, iclass 35, count 0 2006.201.14:59:01.15#ibcon#about to read 3, iclass 35, count 0 2006.201.14:59:01.17#ibcon#read 3, iclass 35, count 0 2006.201.14:59:01.17#ibcon#about to read 4, iclass 35, count 0 2006.201.14:59:01.17#ibcon#read 4, iclass 35, count 0 2006.201.14:59:01.17#ibcon#about to read 5, iclass 35, count 0 2006.201.14:59:01.17#ibcon#read 5, iclass 35, count 0 2006.201.14:59:01.17#ibcon#about to read 6, iclass 35, count 0 2006.201.14:59:01.17#ibcon#read 6, iclass 35, count 0 2006.201.14:59:01.17#ibcon#end of sib2, iclass 35, count 0 2006.201.14:59:01.17#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:59:01.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:59:01.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.14:59:01.17#ibcon#*before write, iclass 35, count 0 2006.201.14:59:01.17#ibcon#enter sib2, iclass 35, count 0 2006.201.14:59:01.17#ibcon#flushed, iclass 35, count 0 2006.201.14:59:01.17#ibcon#about to write, iclass 35, count 0 2006.201.14:59:01.17#ibcon#wrote, iclass 35, count 0 2006.201.14:59:01.17#ibcon#about to read 3, iclass 35, count 0 2006.201.14:59:01.21#ibcon#read 3, iclass 35, count 0 2006.201.14:59:01.21#ibcon#about to read 4, iclass 35, count 0 2006.201.14:59:01.21#ibcon#read 4, iclass 35, count 0 2006.201.14:59:01.21#ibcon#about to read 5, iclass 35, count 0 2006.201.14:59:01.21#ibcon#read 5, iclass 35, count 0 2006.201.14:59:01.21#ibcon#about to read 6, iclass 35, count 0 2006.201.14:59:01.21#ibcon#read 6, iclass 35, count 0 2006.201.14:59:01.21#ibcon#end of sib2, iclass 35, count 0 2006.201.14:59:01.21#ibcon#*after write, iclass 35, count 0 2006.201.14:59:01.21#ibcon#*before return 0, iclass 35, count 0 2006.201.14:59:01.21#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:01.21#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:01.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:59:01.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:59:01.21$vck44/va=7,5 2006.201.14:59:01.21#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.14:59:01.21#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.14:59:01.21#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:01.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:01.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:01.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:01.27#ibcon#enter wrdev, iclass 37, count 2 2006.201.14:59:01.27#ibcon#first serial, iclass 37, count 2 2006.201.14:59:01.27#ibcon#enter sib2, iclass 37, count 2 2006.201.14:59:01.27#ibcon#flushed, iclass 37, count 2 2006.201.14:59:01.27#ibcon#about to write, iclass 37, count 2 2006.201.14:59:01.27#ibcon#wrote, iclass 37, count 2 2006.201.14:59:01.27#ibcon#about to read 3, iclass 37, count 2 2006.201.14:59:01.29#ibcon#read 3, iclass 37, count 2 2006.201.14:59:01.29#ibcon#about to read 4, iclass 37, count 2 2006.201.14:59:01.29#ibcon#read 4, iclass 37, count 2 2006.201.14:59:01.29#ibcon#about to read 5, iclass 37, count 2 2006.201.14:59:01.29#ibcon#read 5, iclass 37, count 2 2006.201.14:59:01.29#ibcon#about to read 6, iclass 37, count 2 2006.201.14:59:01.29#ibcon#read 6, iclass 37, count 2 2006.201.14:59:01.29#ibcon#end of sib2, iclass 37, count 2 2006.201.14:59:01.29#ibcon#*mode == 0, iclass 37, count 2 2006.201.14:59:01.29#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.14:59:01.29#ibcon#[25=AT07-05\r\n] 2006.201.14:59:01.29#ibcon#*before write, iclass 37, count 2 2006.201.14:59:01.29#ibcon#enter sib2, iclass 37, count 2 2006.201.14:59:01.29#ibcon#flushed, iclass 37, count 2 2006.201.14:59:01.29#ibcon#about to write, iclass 37, count 2 2006.201.14:59:01.29#ibcon#wrote, iclass 37, count 2 2006.201.14:59:01.29#ibcon#about to read 3, iclass 37, count 2 2006.201.14:59:01.32#ibcon#read 3, iclass 37, count 2 2006.201.14:59:01.32#ibcon#about to read 4, iclass 37, count 2 2006.201.14:59:01.32#ibcon#read 4, iclass 37, count 2 2006.201.14:59:01.32#ibcon#about to read 5, iclass 37, count 2 2006.201.14:59:01.32#ibcon#read 5, iclass 37, count 2 2006.201.14:59:01.32#ibcon#about to read 6, iclass 37, count 2 2006.201.14:59:01.32#ibcon#read 6, iclass 37, count 2 2006.201.14:59:01.32#ibcon#end of sib2, iclass 37, count 2 2006.201.14:59:01.32#ibcon#*after write, iclass 37, count 2 2006.201.14:59:01.32#ibcon#*before return 0, iclass 37, count 2 2006.201.14:59:01.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:01.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:01.32#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.14:59:01.32#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:01.32#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:01.44#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:01.44#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:01.44#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:59:01.44#ibcon#first serial, iclass 37, count 0 2006.201.14:59:01.44#ibcon#enter sib2, iclass 37, count 0 2006.201.14:59:01.44#ibcon#flushed, iclass 37, count 0 2006.201.14:59:01.44#ibcon#about to write, iclass 37, count 0 2006.201.14:59:01.44#ibcon#wrote, iclass 37, count 0 2006.201.14:59:01.44#ibcon#about to read 3, iclass 37, count 0 2006.201.14:59:01.46#ibcon#read 3, iclass 37, count 0 2006.201.14:59:01.46#ibcon#about to read 4, iclass 37, count 0 2006.201.14:59:01.46#ibcon#read 4, iclass 37, count 0 2006.201.14:59:01.46#ibcon#about to read 5, iclass 37, count 0 2006.201.14:59:01.46#ibcon#read 5, iclass 37, count 0 2006.201.14:59:01.46#ibcon#about to read 6, iclass 37, count 0 2006.201.14:59:01.46#ibcon#read 6, iclass 37, count 0 2006.201.14:59:01.46#ibcon#end of sib2, iclass 37, count 0 2006.201.14:59:01.46#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:59:01.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:59:01.46#ibcon#[25=USB\r\n] 2006.201.14:59:01.46#ibcon#*before write, iclass 37, count 0 2006.201.14:59:01.46#ibcon#enter sib2, iclass 37, count 0 2006.201.14:59:01.46#ibcon#flushed, iclass 37, count 0 2006.201.14:59:01.46#ibcon#about to write, iclass 37, count 0 2006.201.14:59:01.46#ibcon#wrote, iclass 37, count 0 2006.201.14:59:01.46#ibcon#about to read 3, iclass 37, count 0 2006.201.14:59:01.49#ibcon#read 3, iclass 37, count 0 2006.201.14:59:01.49#ibcon#about to read 4, iclass 37, count 0 2006.201.14:59:01.49#ibcon#read 4, iclass 37, count 0 2006.201.14:59:01.49#ibcon#about to read 5, iclass 37, count 0 2006.201.14:59:01.49#ibcon#read 5, iclass 37, count 0 2006.201.14:59:01.49#ibcon#about to read 6, iclass 37, count 0 2006.201.14:59:01.49#ibcon#read 6, iclass 37, count 0 2006.201.14:59:01.49#ibcon#end of sib2, iclass 37, count 0 2006.201.14:59:01.49#ibcon#*after write, iclass 37, count 0 2006.201.14:59:01.49#ibcon#*before return 0, iclass 37, count 0 2006.201.14:59:01.49#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:01.49#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:01.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:59:01.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:59:01.49$vck44/valo=8,884.99 2006.201.14:59:01.49#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.14:59:01.49#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.14:59:01.49#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:01.49#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:01.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:01.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:01.49#ibcon#enter wrdev, iclass 39, count 0 2006.201.14:59:01.49#ibcon#first serial, iclass 39, count 0 2006.201.14:59:01.49#ibcon#enter sib2, iclass 39, count 0 2006.201.14:59:01.49#ibcon#flushed, iclass 39, count 0 2006.201.14:59:01.49#ibcon#about to write, iclass 39, count 0 2006.201.14:59:01.49#ibcon#wrote, iclass 39, count 0 2006.201.14:59:01.49#ibcon#about to read 3, iclass 39, count 0 2006.201.14:59:01.51#ibcon#read 3, iclass 39, count 0 2006.201.14:59:01.51#ibcon#about to read 4, iclass 39, count 0 2006.201.14:59:01.51#ibcon#read 4, iclass 39, count 0 2006.201.14:59:01.51#ibcon#about to read 5, iclass 39, count 0 2006.201.14:59:01.51#ibcon#read 5, iclass 39, count 0 2006.201.14:59:01.51#ibcon#about to read 6, iclass 39, count 0 2006.201.14:59:01.51#ibcon#read 6, iclass 39, count 0 2006.201.14:59:01.51#ibcon#end of sib2, iclass 39, count 0 2006.201.14:59:01.51#ibcon#*mode == 0, iclass 39, count 0 2006.201.14:59:01.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.14:59:01.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.14:59:01.51#ibcon#*before write, iclass 39, count 0 2006.201.14:59:01.51#ibcon#enter sib2, iclass 39, count 0 2006.201.14:59:01.51#ibcon#flushed, iclass 39, count 0 2006.201.14:59:01.51#ibcon#about to write, iclass 39, count 0 2006.201.14:59:01.51#ibcon#wrote, iclass 39, count 0 2006.201.14:59:01.51#ibcon#about to read 3, iclass 39, count 0 2006.201.14:59:01.55#ibcon#read 3, iclass 39, count 0 2006.201.14:59:01.55#ibcon#about to read 4, iclass 39, count 0 2006.201.14:59:01.55#ibcon#read 4, iclass 39, count 0 2006.201.14:59:01.55#ibcon#about to read 5, iclass 39, count 0 2006.201.14:59:01.55#ibcon#read 5, iclass 39, count 0 2006.201.14:59:01.55#ibcon#about to read 6, iclass 39, count 0 2006.201.14:59:01.55#ibcon#read 6, iclass 39, count 0 2006.201.14:59:01.55#ibcon#end of sib2, iclass 39, count 0 2006.201.14:59:01.55#ibcon#*after write, iclass 39, count 0 2006.201.14:59:01.55#ibcon#*before return 0, iclass 39, count 0 2006.201.14:59:01.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:01.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:01.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.14:59:01.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.14:59:01.55$vck44/va=8,4 2006.201.14:59:01.55#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.14:59:01.55#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.14:59:01.55#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:01.55#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:59:01.61#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:59:01.61#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:59:01.61#ibcon#enter wrdev, iclass 2, count 2 2006.201.14:59:01.61#ibcon#first serial, iclass 2, count 2 2006.201.14:59:01.61#ibcon#enter sib2, iclass 2, count 2 2006.201.14:59:01.61#ibcon#flushed, iclass 2, count 2 2006.201.14:59:01.61#ibcon#about to write, iclass 2, count 2 2006.201.14:59:01.61#ibcon#wrote, iclass 2, count 2 2006.201.14:59:01.61#ibcon#about to read 3, iclass 2, count 2 2006.201.14:59:01.63#ibcon#read 3, iclass 2, count 2 2006.201.14:59:01.63#ibcon#about to read 4, iclass 2, count 2 2006.201.14:59:01.63#ibcon#read 4, iclass 2, count 2 2006.201.14:59:01.63#ibcon#about to read 5, iclass 2, count 2 2006.201.14:59:01.63#ibcon#read 5, iclass 2, count 2 2006.201.14:59:01.63#ibcon#about to read 6, iclass 2, count 2 2006.201.14:59:01.63#ibcon#read 6, iclass 2, count 2 2006.201.14:59:01.63#ibcon#end of sib2, iclass 2, count 2 2006.201.14:59:01.63#ibcon#*mode == 0, iclass 2, count 2 2006.201.14:59:01.63#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.14:59:01.63#ibcon#[25=AT08-04\r\n] 2006.201.14:59:01.63#ibcon#*before write, iclass 2, count 2 2006.201.14:59:01.63#ibcon#enter sib2, iclass 2, count 2 2006.201.14:59:01.63#ibcon#flushed, iclass 2, count 2 2006.201.14:59:01.63#ibcon#about to write, iclass 2, count 2 2006.201.14:59:01.63#ibcon#wrote, iclass 2, count 2 2006.201.14:59:01.63#ibcon#about to read 3, iclass 2, count 2 2006.201.14:59:01.66#ibcon#read 3, iclass 2, count 2 2006.201.14:59:01.66#ibcon#about to read 4, iclass 2, count 2 2006.201.14:59:01.66#ibcon#read 4, iclass 2, count 2 2006.201.14:59:01.66#ibcon#about to read 5, iclass 2, count 2 2006.201.14:59:01.66#ibcon#read 5, iclass 2, count 2 2006.201.14:59:01.66#ibcon#about to read 6, iclass 2, count 2 2006.201.14:59:01.66#ibcon#read 6, iclass 2, count 2 2006.201.14:59:01.66#ibcon#end of sib2, iclass 2, count 2 2006.201.14:59:01.66#ibcon#*after write, iclass 2, count 2 2006.201.14:59:01.66#ibcon#*before return 0, iclass 2, count 2 2006.201.14:59:01.66#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:59:01.66#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.14:59:01.66#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.14:59:01.66#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:01.66#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:59:01.78#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:59:01.78#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:59:01.78#ibcon#enter wrdev, iclass 2, count 0 2006.201.14:59:01.78#ibcon#first serial, iclass 2, count 0 2006.201.14:59:01.78#ibcon#enter sib2, iclass 2, count 0 2006.201.14:59:01.78#ibcon#flushed, iclass 2, count 0 2006.201.14:59:01.78#ibcon#about to write, iclass 2, count 0 2006.201.14:59:01.78#ibcon#wrote, iclass 2, count 0 2006.201.14:59:01.78#ibcon#about to read 3, iclass 2, count 0 2006.201.14:59:01.80#ibcon#read 3, iclass 2, count 0 2006.201.14:59:01.80#ibcon#about to read 4, iclass 2, count 0 2006.201.14:59:01.80#ibcon#read 4, iclass 2, count 0 2006.201.14:59:01.80#ibcon#about to read 5, iclass 2, count 0 2006.201.14:59:01.80#ibcon#read 5, iclass 2, count 0 2006.201.14:59:01.80#ibcon#about to read 6, iclass 2, count 0 2006.201.14:59:01.80#ibcon#read 6, iclass 2, count 0 2006.201.14:59:01.80#ibcon#end of sib2, iclass 2, count 0 2006.201.14:59:01.80#ibcon#*mode == 0, iclass 2, count 0 2006.201.14:59:01.80#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.14:59:01.80#ibcon#[25=USB\r\n] 2006.201.14:59:01.80#ibcon#*before write, iclass 2, count 0 2006.201.14:59:01.80#ibcon#enter sib2, iclass 2, count 0 2006.201.14:59:01.80#ibcon#flushed, iclass 2, count 0 2006.201.14:59:01.80#ibcon#about to write, iclass 2, count 0 2006.201.14:59:01.80#ibcon#wrote, iclass 2, count 0 2006.201.14:59:01.80#ibcon#about to read 3, iclass 2, count 0 2006.201.14:59:01.83#ibcon#read 3, iclass 2, count 0 2006.201.14:59:01.83#ibcon#about to read 4, iclass 2, count 0 2006.201.14:59:01.83#ibcon#read 4, iclass 2, count 0 2006.201.14:59:01.83#ibcon#about to read 5, iclass 2, count 0 2006.201.14:59:01.83#ibcon#read 5, iclass 2, count 0 2006.201.14:59:01.83#ibcon#about to read 6, iclass 2, count 0 2006.201.14:59:01.83#ibcon#read 6, iclass 2, count 0 2006.201.14:59:01.83#ibcon#end of sib2, iclass 2, count 0 2006.201.14:59:01.83#ibcon#*after write, iclass 2, count 0 2006.201.14:59:01.83#ibcon#*before return 0, iclass 2, count 0 2006.201.14:59:01.83#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:59:01.83#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.14:59:01.83#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.14:59:01.83#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.14:59:01.83$vck44/vblo=1,629.99 2006.201.14:59:01.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.14:59:01.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.14:59:01.83#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:01.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:59:01.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:59:01.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:59:01.83#ibcon#enter wrdev, iclass 5, count 0 2006.201.14:59:01.83#ibcon#first serial, iclass 5, count 0 2006.201.14:59:01.83#ibcon#enter sib2, iclass 5, count 0 2006.201.14:59:01.83#ibcon#flushed, iclass 5, count 0 2006.201.14:59:01.83#ibcon#about to write, iclass 5, count 0 2006.201.14:59:01.83#ibcon#wrote, iclass 5, count 0 2006.201.14:59:01.83#ibcon#about to read 3, iclass 5, count 0 2006.201.14:59:01.85#ibcon#read 3, iclass 5, count 0 2006.201.14:59:01.85#ibcon#about to read 4, iclass 5, count 0 2006.201.14:59:01.85#ibcon#read 4, iclass 5, count 0 2006.201.14:59:01.85#ibcon#about to read 5, iclass 5, count 0 2006.201.14:59:01.85#ibcon#read 5, iclass 5, count 0 2006.201.14:59:01.85#ibcon#about to read 6, iclass 5, count 0 2006.201.14:59:01.85#ibcon#read 6, iclass 5, count 0 2006.201.14:59:01.85#ibcon#end of sib2, iclass 5, count 0 2006.201.14:59:01.85#ibcon#*mode == 0, iclass 5, count 0 2006.201.14:59:01.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.14:59:01.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.14:59:01.85#ibcon#*before write, iclass 5, count 0 2006.201.14:59:01.85#ibcon#enter sib2, iclass 5, count 0 2006.201.14:59:01.85#ibcon#flushed, iclass 5, count 0 2006.201.14:59:01.85#ibcon#about to write, iclass 5, count 0 2006.201.14:59:01.85#ibcon#wrote, iclass 5, count 0 2006.201.14:59:01.85#ibcon#about to read 3, iclass 5, count 0 2006.201.14:59:01.90#ibcon#read 3, iclass 5, count 0 2006.201.14:59:01.90#ibcon#about to read 4, iclass 5, count 0 2006.201.14:59:01.90#ibcon#read 4, iclass 5, count 0 2006.201.14:59:01.90#ibcon#about to read 5, iclass 5, count 0 2006.201.14:59:01.90#ibcon#read 5, iclass 5, count 0 2006.201.14:59:01.90#ibcon#about to read 6, iclass 5, count 0 2006.201.14:59:01.90#ibcon#read 6, iclass 5, count 0 2006.201.14:59:01.90#ibcon#end of sib2, iclass 5, count 0 2006.201.14:59:01.90#ibcon#*after write, iclass 5, count 0 2006.201.14:59:01.90#ibcon#*before return 0, iclass 5, count 0 2006.201.14:59:01.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:59:01.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.14:59:01.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.14:59:01.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.14:59:01.90$vck44/vb=1,4 2006.201.14:59:01.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.14:59:01.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.14:59:01.90#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:01.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:59:01.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:59:01.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:59:01.90#ibcon#enter wrdev, iclass 7, count 2 2006.201.14:59:01.90#ibcon#first serial, iclass 7, count 2 2006.201.14:59:01.90#ibcon#enter sib2, iclass 7, count 2 2006.201.14:59:01.90#ibcon#flushed, iclass 7, count 2 2006.201.14:59:01.90#ibcon#about to write, iclass 7, count 2 2006.201.14:59:01.90#ibcon#wrote, iclass 7, count 2 2006.201.14:59:01.90#ibcon#about to read 3, iclass 7, count 2 2006.201.14:59:01.92#ibcon#read 3, iclass 7, count 2 2006.201.14:59:01.92#ibcon#about to read 4, iclass 7, count 2 2006.201.14:59:01.92#ibcon#read 4, iclass 7, count 2 2006.201.14:59:01.92#ibcon#about to read 5, iclass 7, count 2 2006.201.14:59:01.92#ibcon#read 5, iclass 7, count 2 2006.201.14:59:01.92#ibcon#about to read 6, iclass 7, count 2 2006.201.14:59:01.92#ibcon#read 6, iclass 7, count 2 2006.201.14:59:01.92#ibcon#end of sib2, iclass 7, count 2 2006.201.14:59:01.92#ibcon#*mode == 0, iclass 7, count 2 2006.201.14:59:01.92#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.14:59:01.92#ibcon#[27=AT01-04\r\n] 2006.201.14:59:01.92#ibcon#*before write, iclass 7, count 2 2006.201.14:59:01.92#ibcon#enter sib2, iclass 7, count 2 2006.201.14:59:01.92#ibcon#flushed, iclass 7, count 2 2006.201.14:59:01.92#ibcon#about to write, iclass 7, count 2 2006.201.14:59:01.92#ibcon#wrote, iclass 7, count 2 2006.201.14:59:01.92#ibcon#about to read 3, iclass 7, count 2 2006.201.14:59:01.95#ibcon#read 3, iclass 7, count 2 2006.201.14:59:01.95#ibcon#about to read 4, iclass 7, count 2 2006.201.14:59:01.95#ibcon#read 4, iclass 7, count 2 2006.201.14:59:01.95#ibcon#about to read 5, iclass 7, count 2 2006.201.14:59:01.95#ibcon#read 5, iclass 7, count 2 2006.201.14:59:01.95#ibcon#about to read 6, iclass 7, count 2 2006.201.14:59:01.95#ibcon#read 6, iclass 7, count 2 2006.201.14:59:01.95#ibcon#end of sib2, iclass 7, count 2 2006.201.14:59:01.95#ibcon#*after write, iclass 7, count 2 2006.201.14:59:01.95#ibcon#*before return 0, iclass 7, count 2 2006.201.14:59:01.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:59:01.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.14:59:01.95#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.14:59:01.95#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:01.95#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:59:02.07#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:59:02.07#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:59:02.07#ibcon#enter wrdev, iclass 7, count 0 2006.201.14:59:02.07#ibcon#first serial, iclass 7, count 0 2006.201.14:59:02.07#ibcon#enter sib2, iclass 7, count 0 2006.201.14:59:02.07#ibcon#flushed, iclass 7, count 0 2006.201.14:59:02.07#ibcon#about to write, iclass 7, count 0 2006.201.14:59:02.07#ibcon#wrote, iclass 7, count 0 2006.201.14:59:02.07#ibcon#about to read 3, iclass 7, count 0 2006.201.14:59:02.09#ibcon#read 3, iclass 7, count 0 2006.201.14:59:02.09#ibcon#about to read 4, iclass 7, count 0 2006.201.14:59:02.09#ibcon#read 4, iclass 7, count 0 2006.201.14:59:02.09#ibcon#about to read 5, iclass 7, count 0 2006.201.14:59:02.09#ibcon#read 5, iclass 7, count 0 2006.201.14:59:02.09#ibcon#about to read 6, iclass 7, count 0 2006.201.14:59:02.09#ibcon#read 6, iclass 7, count 0 2006.201.14:59:02.09#ibcon#end of sib2, iclass 7, count 0 2006.201.14:59:02.09#ibcon#*mode == 0, iclass 7, count 0 2006.201.14:59:02.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.14:59:02.09#ibcon#[27=USB\r\n] 2006.201.14:59:02.09#ibcon#*before write, iclass 7, count 0 2006.201.14:59:02.09#ibcon#enter sib2, iclass 7, count 0 2006.201.14:59:02.09#ibcon#flushed, iclass 7, count 0 2006.201.14:59:02.09#ibcon#about to write, iclass 7, count 0 2006.201.14:59:02.09#ibcon#wrote, iclass 7, count 0 2006.201.14:59:02.09#ibcon#about to read 3, iclass 7, count 0 2006.201.14:59:02.12#ibcon#read 3, iclass 7, count 0 2006.201.14:59:02.12#ibcon#about to read 4, iclass 7, count 0 2006.201.14:59:02.12#ibcon#read 4, iclass 7, count 0 2006.201.14:59:02.12#ibcon#about to read 5, iclass 7, count 0 2006.201.14:59:02.12#ibcon#read 5, iclass 7, count 0 2006.201.14:59:02.12#ibcon#about to read 6, iclass 7, count 0 2006.201.14:59:02.12#ibcon#read 6, iclass 7, count 0 2006.201.14:59:02.12#ibcon#end of sib2, iclass 7, count 0 2006.201.14:59:02.12#ibcon#*after write, iclass 7, count 0 2006.201.14:59:02.12#ibcon#*before return 0, iclass 7, count 0 2006.201.14:59:02.12#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:59:02.12#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.14:59:02.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.14:59:02.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.14:59:02.12$vck44/vblo=2,634.99 2006.201.14:59:02.12#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.14:59:02.12#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.14:59:02.12#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:02.12#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:59:02.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:59:02.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:59:02.12#ibcon#enter wrdev, iclass 11, count 0 2006.201.14:59:02.12#ibcon#first serial, iclass 11, count 0 2006.201.14:59:02.12#ibcon#enter sib2, iclass 11, count 0 2006.201.14:59:02.12#ibcon#flushed, iclass 11, count 0 2006.201.14:59:02.12#ibcon#about to write, iclass 11, count 0 2006.201.14:59:02.12#ibcon#wrote, iclass 11, count 0 2006.201.14:59:02.12#ibcon#about to read 3, iclass 11, count 0 2006.201.14:59:02.14#ibcon#read 3, iclass 11, count 0 2006.201.14:59:02.14#ibcon#about to read 4, iclass 11, count 0 2006.201.14:59:02.14#ibcon#read 4, iclass 11, count 0 2006.201.14:59:02.14#ibcon#about to read 5, iclass 11, count 0 2006.201.14:59:02.14#ibcon#read 5, iclass 11, count 0 2006.201.14:59:02.14#ibcon#about to read 6, iclass 11, count 0 2006.201.14:59:02.14#ibcon#read 6, iclass 11, count 0 2006.201.14:59:02.14#ibcon#end of sib2, iclass 11, count 0 2006.201.14:59:02.14#ibcon#*mode == 0, iclass 11, count 0 2006.201.14:59:02.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.14:59:02.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.14:59:02.14#ibcon#*before write, iclass 11, count 0 2006.201.14:59:02.14#ibcon#enter sib2, iclass 11, count 0 2006.201.14:59:02.14#ibcon#flushed, iclass 11, count 0 2006.201.14:59:02.14#ibcon#about to write, iclass 11, count 0 2006.201.14:59:02.14#ibcon#wrote, iclass 11, count 0 2006.201.14:59:02.14#ibcon#about to read 3, iclass 11, count 0 2006.201.14:59:02.18#ibcon#read 3, iclass 11, count 0 2006.201.14:59:02.18#ibcon#about to read 4, iclass 11, count 0 2006.201.14:59:02.18#ibcon#read 4, iclass 11, count 0 2006.201.14:59:02.18#ibcon#about to read 5, iclass 11, count 0 2006.201.14:59:02.18#ibcon#read 5, iclass 11, count 0 2006.201.14:59:02.18#ibcon#about to read 6, iclass 11, count 0 2006.201.14:59:02.18#ibcon#read 6, iclass 11, count 0 2006.201.14:59:02.18#ibcon#end of sib2, iclass 11, count 0 2006.201.14:59:02.18#ibcon#*after write, iclass 11, count 0 2006.201.14:59:02.18#ibcon#*before return 0, iclass 11, count 0 2006.201.14:59:02.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:59:02.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.14:59:02.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.14:59:02.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.14:59:02.18$vck44/vb=2,5 2006.201.14:59:02.18#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.14:59:02.18#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.14:59:02.18#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:02.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:59:02.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:59:02.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:59:02.24#ibcon#enter wrdev, iclass 13, count 2 2006.201.14:59:02.24#ibcon#first serial, iclass 13, count 2 2006.201.14:59:02.24#ibcon#enter sib2, iclass 13, count 2 2006.201.14:59:02.24#ibcon#flushed, iclass 13, count 2 2006.201.14:59:02.24#ibcon#about to write, iclass 13, count 2 2006.201.14:59:02.24#ibcon#wrote, iclass 13, count 2 2006.201.14:59:02.24#ibcon#about to read 3, iclass 13, count 2 2006.201.14:59:02.26#ibcon#read 3, iclass 13, count 2 2006.201.14:59:02.26#ibcon#about to read 4, iclass 13, count 2 2006.201.14:59:02.26#ibcon#read 4, iclass 13, count 2 2006.201.14:59:02.26#ibcon#about to read 5, iclass 13, count 2 2006.201.14:59:02.26#ibcon#read 5, iclass 13, count 2 2006.201.14:59:02.26#ibcon#about to read 6, iclass 13, count 2 2006.201.14:59:02.26#ibcon#read 6, iclass 13, count 2 2006.201.14:59:02.26#ibcon#end of sib2, iclass 13, count 2 2006.201.14:59:02.26#ibcon#*mode == 0, iclass 13, count 2 2006.201.14:59:02.26#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.14:59:02.26#ibcon#[27=AT02-05\r\n] 2006.201.14:59:02.26#ibcon#*before write, iclass 13, count 2 2006.201.14:59:02.26#ibcon#enter sib2, iclass 13, count 2 2006.201.14:59:02.26#ibcon#flushed, iclass 13, count 2 2006.201.14:59:02.26#ibcon#about to write, iclass 13, count 2 2006.201.14:59:02.26#ibcon#wrote, iclass 13, count 2 2006.201.14:59:02.26#ibcon#about to read 3, iclass 13, count 2 2006.201.14:59:02.29#ibcon#read 3, iclass 13, count 2 2006.201.14:59:02.29#ibcon#about to read 4, iclass 13, count 2 2006.201.14:59:02.29#ibcon#read 4, iclass 13, count 2 2006.201.14:59:02.29#ibcon#about to read 5, iclass 13, count 2 2006.201.14:59:02.29#ibcon#read 5, iclass 13, count 2 2006.201.14:59:02.29#ibcon#about to read 6, iclass 13, count 2 2006.201.14:59:02.29#ibcon#read 6, iclass 13, count 2 2006.201.14:59:02.29#ibcon#end of sib2, iclass 13, count 2 2006.201.14:59:02.29#ibcon#*after write, iclass 13, count 2 2006.201.14:59:02.29#ibcon#*before return 0, iclass 13, count 2 2006.201.14:59:02.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:59:02.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.14:59:02.29#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.14:59:02.29#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:02.29#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:59:02.41#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:59:02.41#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:59:02.41#ibcon#enter wrdev, iclass 13, count 0 2006.201.14:59:02.41#ibcon#first serial, iclass 13, count 0 2006.201.14:59:02.41#ibcon#enter sib2, iclass 13, count 0 2006.201.14:59:02.41#ibcon#flushed, iclass 13, count 0 2006.201.14:59:02.41#ibcon#about to write, iclass 13, count 0 2006.201.14:59:02.41#ibcon#wrote, iclass 13, count 0 2006.201.14:59:02.41#ibcon#about to read 3, iclass 13, count 0 2006.201.14:59:02.43#ibcon#read 3, iclass 13, count 0 2006.201.14:59:02.43#ibcon#about to read 4, iclass 13, count 0 2006.201.14:59:02.43#ibcon#read 4, iclass 13, count 0 2006.201.14:59:02.43#ibcon#about to read 5, iclass 13, count 0 2006.201.14:59:02.43#ibcon#read 5, iclass 13, count 0 2006.201.14:59:02.43#ibcon#about to read 6, iclass 13, count 0 2006.201.14:59:02.43#ibcon#read 6, iclass 13, count 0 2006.201.14:59:02.43#ibcon#end of sib2, iclass 13, count 0 2006.201.14:59:02.43#ibcon#*mode == 0, iclass 13, count 0 2006.201.14:59:02.43#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.14:59:02.43#ibcon#[27=USB\r\n] 2006.201.14:59:02.43#ibcon#*before write, iclass 13, count 0 2006.201.14:59:02.43#ibcon#enter sib2, iclass 13, count 0 2006.201.14:59:02.43#ibcon#flushed, iclass 13, count 0 2006.201.14:59:02.43#ibcon#about to write, iclass 13, count 0 2006.201.14:59:02.43#ibcon#wrote, iclass 13, count 0 2006.201.14:59:02.43#ibcon#about to read 3, iclass 13, count 0 2006.201.14:59:02.46#ibcon#read 3, iclass 13, count 0 2006.201.14:59:02.46#ibcon#about to read 4, iclass 13, count 0 2006.201.14:59:02.46#ibcon#read 4, iclass 13, count 0 2006.201.14:59:02.46#ibcon#about to read 5, iclass 13, count 0 2006.201.14:59:02.46#ibcon#read 5, iclass 13, count 0 2006.201.14:59:02.46#ibcon#about to read 6, iclass 13, count 0 2006.201.14:59:02.46#ibcon#read 6, iclass 13, count 0 2006.201.14:59:02.46#ibcon#end of sib2, iclass 13, count 0 2006.201.14:59:02.46#ibcon#*after write, iclass 13, count 0 2006.201.14:59:02.46#ibcon#*before return 0, iclass 13, count 0 2006.201.14:59:02.46#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:59:02.46#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.14:59:02.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.14:59:02.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.14:59:02.46$vck44/vblo=3,649.99 2006.201.14:59:02.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.14:59:02.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.14:59:02.46#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:02.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:59:02.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:59:02.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:59:02.46#ibcon#enter wrdev, iclass 15, count 0 2006.201.14:59:02.46#ibcon#first serial, iclass 15, count 0 2006.201.14:59:02.46#ibcon#enter sib2, iclass 15, count 0 2006.201.14:59:02.46#ibcon#flushed, iclass 15, count 0 2006.201.14:59:02.46#ibcon#about to write, iclass 15, count 0 2006.201.14:59:02.46#ibcon#wrote, iclass 15, count 0 2006.201.14:59:02.46#ibcon#about to read 3, iclass 15, count 0 2006.201.14:59:02.48#ibcon#read 3, iclass 15, count 0 2006.201.14:59:02.48#ibcon#about to read 4, iclass 15, count 0 2006.201.14:59:02.48#ibcon#read 4, iclass 15, count 0 2006.201.14:59:02.48#ibcon#about to read 5, iclass 15, count 0 2006.201.14:59:02.48#ibcon#read 5, iclass 15, count 0 2006.201.14:59:02.48#ibcon#about to read 6, iclass 15, count 0 2006.201.14:59:02.48#ibcon#read 6, iclass 15, count 0 2006.201.14:59:02.48#ibcon#end of sib2, iclass 15, count 0 2006.201.14:59:02.48#ibcon#*mode == 0, iclass 15, count 0 2006.201.14:59:02.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.14:59:02.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.14:59:02.48#ibcon#*before write, iclass 15, count 0 2006.201.14:59:02.48#ibcon#enter sib2, iclass 15, count 0 2006.201.14:59:02.48#ibcon#flushed, iclass 15, count 0 2006.201.14:59:02.48#ibcon#about to write, iclass 15, count 0 2006.201.14:59:02.48#ibcon#wrote, iclass 15, count 0 2006.201.14:59:02.48#ibcon#about to read 3, iclass 15, count 0 2006.201.14:59:02.52#ibcon#read 3, iclass 15, count 0 2006.201.14:59:02.52#ibcon#about to read 4, iclass 15, count 0 2006.201.14:59:02.52#ibcon#read 4, iclass 15, count 0 2006.201.14:59:02.52#ibcon#about to read 5, iclass 15, count 0 2006.201.14:59:02.52#ibcon#read 5, iclass 15, count 0 2006.201.14:59:02.52#ibcon#about to read 6, iclass 15, count 0 2006.201.14:59:02.52#ibcon#read 6, iclass 15, count 0 2006.201.14:59:02.52#ibcon#end of sib2, iclass 15, count 0 2006.201.14:59:02.52#ibcon#*after write, iclass 15, count 0 2006.201.14:59:02.52#ibcon#*before return 0, iclass 15, count 0 2006.201.14:59:02.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:59:02.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.14:59:02.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.14:59:02.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.14:59:02.52$vck44/vb=3,4 2006.201.14:59:02.52#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.14:59:02.52#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.14:59:02.52#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:02.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:59:02.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:59:02.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:59:02.58#ibcon#enter wrdev, iclass 17, count 2 2006.201.14:59:02.58#ibcon#first serial, iclass 17, count 2 2006.201.14:59:02.58#ibcon#enter sib2, iclass 17, count 2 2006.201.14:59:02.58#ibcon#flushed, iclass 17, count 2 2006.201.14:59:02.58#ibcon#about to write, iclass 17, count 2 2006.201.14:59:02.58#ibcon#wrote, iclass 17, count 2 2006.201.14:59:02.58#ibcon#about to read 3, iclass 17, count 2 2006.201.14:59:02.60#ibcon#read 3, iclass 17, count 2 2006.201.14:59:02.60#ibcon#about to read 4, iclass 17, count 2 2006.201.14:59:02.60#ibcon#read 4, iclass 17, count 2 2006.201.14:59:02.60#ibcon#about to read 5, iclass 17, count 2 2006.201.14:59:02.60#ibcon#read 5, iclass 17, count 2 2006.201.14:59:02.60#ibcon#about to read 6, iclass 17, count 2 2006.201.14:59:02.60#ibcon#read 6, iclass 17, count 2 2006.201.14:59:02.60#ibcon#end of sib2, iclass 17, count 2 2006.201.14:59:02.60#ibcon#*mode == 0, iclass 17, count 2 2006.201.14:59:02.60#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.14:59:02.60#ibcon#[27=AT03-04\r\n] 2006.201.14:59:02.60#ibcon#*before write, iclass 17, count 2 2006.201.14:59:02.60#ibcon#enter sib2, iclass 17, count 2 2006.201.14:59:02.60#ibcon#flushed, iclass 17, count 2 2006.201.14:59:02.60#ibcon#about to write, iclass 17, count 2 2006.201.14:59:02.60#ibcon#wrote, iclass 17, count 2 2006.201.14:59:02.60#ibcon#about to read 3, iclass 17, count 2 2006.201.14:59:02.63#ibcon#read 3, iclass 17, count 2 2006.201.14:59:02.63#ibcon#about to read 4, iclass 17, count 2 2006.201.14:59:02.63#ibcon#read 4, iclass 17, count 2 2006.201.14:59:02.63#ibcon#about to read 5, iclass 17, count 2 2006.201.14:59:02.63#ibcon#read 5, iclass 17, count 2 2006.201.14:59:02.63#ibcon#about to read 6, iclass 17, count 2 2006.201.14:59:02.63#ibcon#read 6, iclass 17, count 2 2006.201.14:59:02.63#ibcon#end of sib2, iclass 17, count 2 2006.201.14:59:02.63#ibcon#*after write, iclass 17, count 2 2006.201.14:59:02.63#ibcon#*before return 0, iclass 17, count 2 2006.201.14:59:02.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:59:02.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.14:59:02.63#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.14:59:02.63#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:02.63#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:02.75#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:02.75#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:02.75#ibcon#enter wrdev, iclass 17, count 0 2006.201.14:59:02.75#ibcon#first serial, iclass 17, count 0 2006.201.14:59:02.75#ibcon#enter sib2, iclass 17, count 0 2006.201.14:59:02.75#ibcon#flushed, iclass 17, count 0 2006.201.14:59:02.75#ibcon#about to write, iclass 17, count 0 2006.201.14:59:02.75#ibcon#wrote, iclass 17, count 0 2006.201.14:59:02.75#ibcon#about to read 3, iclass 17, count 0 2006.201.14:59:02.77#ibcon#read 3, iclass 17, count 0 2006.201.14:59:02.77#ibcon#about to read 4, iclass 17, count 0 2006.201.14:59:02.77#ibcon#read 4, iclass 17, count 0 2006.201.14:59:02.77#ibcon#about to read 5, iclass 17, count 0 2006.201.14:59:02.77#ibcon#read 5, iclass 17, count 0 2006.201.14:59:02.77#ibcon#about to read 6, iclass 17, count 0 2006.201.14:59:02.77#ibcon#read 6, iclass 17, count 0 2006.201.14:59:02.77#ibcon#end of sib2, iclass 17, count 0 2006.201.14:59:02.77#ibcon#*mode == 0, iclass 17, count 0 2006.201.14:59:02.77#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.14:59:02.77#ibcon#[27=USB\r\n] 2006.201.14:59:02.77#ibcon#*before write, iclass 17, count 0 2006.201.14:59:02.77#ibcon#enter sib2, iclass 17, count 0 2006.201.14:59:02.77#ibcon#flushed, iclass 17, count 0 2006.201.14:59:02.77#ibcon#about to write, iclass 17, count 0 2006.201.14:59:02.77#ibcon#wrote, iclass 17, count 0 2006.201.14:59:02.77#ibcon#about to read 3, iclass 17, count 0 2006.201.14:59:02.80#ibcon#read 3, iclass 17, count 0 2006.201.14:59:02.80#ibcon#about to read 4, iclass 17, count 0 2006.201.14:59:02.80#ibcon#read 4, iclass 17, count 0 2006.201.14:59:02.80#ibcon#about to read 5, iclass 17, count 0 2006.201.14:59:02.80#ibcon#read 5, iclass 17, count 0 2006.201.14:59:02.80#ibcon#about to read 6, iclass 17, count 0 2006.201.14:59:02.80#ibcon#read 6, iclass 17, count 0 2006.201.14:59:02.80#ibcon#end of sib2, iclass 17, count 0 2006.201.14:59:02.80#ibcon#*after write, iclass 17, count 0 2006.201.14:59:02.80#ibcon#*before return 0, iclass 17, count 0 2006.201.14:59:02.80#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:02.80#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.14:59:02.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.14:59:02.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.14:59:02.80$vck44/vblo=4,679.99 2006.201.14:59:02.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.14:59:02.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.14:59:02.80#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:02.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:02.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:02.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:02.80#ibcon#enter wrdev, iclass 19, count 0 2006.201.14:59:02.80#ibcon#first serial, iclass 19, count 0 2006.201.14:59:02.80#ibcon#enter sib2, iclass 19, count 0 2006.201.14:59:02.80#ibcon#flushed, iclass 19, count 0 2006.201.14:59:02.80#ibcon#about to write, iclass 19, count 0 2006.201.14:59:02.80#ibcon#wrote, iclass 19, count 0 2006.201.14:59:02.80#ibcon#about to read 3, iclass 19, count 0 2006.201.14:59:02.82#ibcon#read 3, iclass 19, count 0 2006.201.14:59:02.82#ibcon#about to read 4, iclass 19, count 0 2006.201.14:59:02.82#ibcon#read 4, iclass 19, count 0 2006.201.14:59:02.82#ibcon#about to read 5, iclass 19, count 0 2006.201.14:59:02.82#ibcon#read 5, iclass 19, count 0 2006.201.14:59:02.82#ibcon#about to read 6, iclass 19, count 0 2006.201.14:59:02.82#ibcon#read 6, iclass 19, count 0 2006.201.14:59:02.82#ibcon#end of sib2, iclass 19, count 0 2006.201.14:59:02.82#ibcon#*mode == 0, iclass 19, count 0 2006.201.14:59:02.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.14:59:02.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.14:59:02.82#ibcon#*before write, iclass 19, count 0 2006.201.14:59:02.82#ibcon#enter sib2, iclass 19, count 0 2006.201.14:59:02.82#ibcon#flushed, iclass 19, count 0 2006.201.14:59:02.82#ibcon#about to write, iclass 19, count 0 2006.201.14:59:02.82#ibcon#wrote, iclass 19, count 0 2006.201.14:59:02.82#ibcon#about to read 3, iclass 19, count 0 2006.201.14:59:02.87#ibcon#read 3, iclass 19, count 0 2006.201.14:59:02.87#ibcon#about to read 4, iclass 19, count 0 2006.201.14:59:02.87#ibcon#read 4, iclass 19, count 0 2006.201.14:59:02.87#ibcon#about to read 5, iclass 19, count 0 2006.201.14:59:02.87#ibcon#read 5, iclass 19, count 0 2006.201.14:59:02.87#ibcon#about to read 6, iclass 19, count 0 2006.201.14:59:02.87#ibcon#read 6, iclass 19, count 0 2006.201.14:59:02.87#ibcon#end of sib2, iclass 19, count 0 2006.201.14:59:02.87#ibcon#*after write, iclass 19, count 0 2006.201.14:59:02.87#ibcon#*before return 0, iclass 19, count 0 2006.201.14:59:02.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:02.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.14:59:02.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.14:59:02.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.14:59:02.87$vck44/vb=4,5 2006.201.14:59:02.87#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.14:59:02.87#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.14:59:02.87#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:02.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:02.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:02.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:02.92#ibcon#enter wrdev, iclass 21, count 2 2006.201.14:59:02.92#ibcon#first serial, iclass 21, count 2 2006.201.14:59:02.92#ibcon#enter sib2, iclass 21, count 2 2006.201.14:59:02.92#ibcon#flushed, iclass 21, count 2 2006.201.14:59:02.92#ibcon#about to write, iclass 21, count 2 2006.201.14:59:02.92#ibcon#wrote, iclass 21, count 2 2006.201.14:59:02.92#ibcon#about to read 3, iclass 21, count 2 2006.201.14:59:02.94#ibcon#read 3, iclass 21, count 2 2006.201.14:59:02.94#ibcon#about to read 4, iclass 21, count 2 2006.201.14:59:02.94#ibcon#read 4, iclass 21, count 2 2006.201.14:59:02.94#ibcon#about to read 5, iclass 21, count 2 2006.201.14:59:02.94#ibcon#read 5, iclass 21, count 2 2006.201.14:59:02.94#ibcon#about to read 6, iclass 21, count 2 2006.201.14:59:02.94#ibcon#read 6, iclass 21, count 2 2006.201.14:59:02.94#ibcon#end of sib2, iclass 21, count 2 2006.201.14:59:02.94#ibcon#*mode == 0, iclass 21, count 2 2006.201.14:59:02.94#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.14:59:02.94#ibcon#[27=AT04-05\r\n] 2006.201.14:59:02.94#ibcon#*before write, iclass 21, count 2 2006.201.14:59:02.94#ibcon#enter sib2, iclass 21, count 2 2006.201.14:59:02.94#ibcon#flushed, iclass 21, count 2 2006.201.14:59:02.94#ibcon#about to write, iclass 21, count 2 2006.201.14:59:02.94#ibcon#wrote, iclass 21, count 2 2006.201.14:59:02.94#ibcon#about to read 3, iclass 21, count 2 2006.201.14:59:02.97#ibcon#read 3, iclass 21, count 2 2006.201.14:59:02.97#ibcon#about to read 4, iclass 21, count 2 2006.201.14:59:02.97#ibcon#read 4, iclass 21, count 2 2006.201.14:59:02.97#ibcon#about to read 5, iclass 21, count 2 2006.201.14:59:02.97#ibcon#read 5, iclass 21, count 2 2006.201.14:59:02.97#ibcon#about to read 6, iclass 21, count 2 2006.201.14:59:02.97#ibcon#read 6, iclass 21, count 2 2006.201.14:59:02.97#ibcon#end of sib2, iclass 21, count 2 2006.201.14:59:02.97#ibcon#*after write, iclass 21, count 2 2006.201.14:59:02.97#ibcon#*before return 0, iclass 21, count 2 2006.201.14:59:02.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:02.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.14:59:02.97#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.14:59:02.97#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:02.97#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:03.09#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:03.09#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:03.09#ibcon#enter wrdev, iclass 21, count 0 2006.201.14:59:03.09#ibcon#first serial, iclass 21, count 0 2006.201.14:59:03.09#ibcon#enter sib2, iclass 21, count 0 2006.201.14:59:03.09#ibcon#flushed, iclass 21, count 0 2006.201.14:59:03.09#ibcon#about to write, iclass 21, count 0 2006.201.14:59:03.09#ibcon#wrote, iclass 21, count 0 2006.201.14:59:03.09#ibcon#about to read 3, iclass 21, count 0 2006.201.14:59:03.11#ibcon#read 3, iclass 21, count 0 2006.201.14:59:03.11#ibcon#about to read 4, iclass 21, count 0 2006.201.14:59:03.11#ibcon#read 4, iclass 21, count 0 2006.201.14:59:03.11#ibcon#about to read 5, iclass 21, count 0 2006.201.14:59:03.11#ibcon#read 5, iclass 21, count 0 2006.201.14:59:03.11#ibcon#about to read 6, iclass 21, count 0 2006.201.14:59:03.11#ibcon#read 6, iclass 21, count 0 2006.201.14:59:03.11#ibcon#end of sib2, iclass 21, count 0 2006.201.14:59:03.11#ibcon#*mode == 0, iclass 21, count 0 2006.201.14:59:03.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.14:59:03.11#ibcon#[27=USB\r\n] 2006.201.14:59:03.11#ibcon#*before write, iclass 21, count 0 2006.201.14:59:03.11#ibcon#enter sib2, iclass 21, count 0 2006.201.14:59:03.11#ibcon#flushed, iclass 21, count 0 2006.201.14:59:03.11#ibcon#about to write, iclass 21, count 0 2006.201.14:59:03.11#ibcon#wrote, iclass 21, count 0 2006.201.14:59:03.11#ibcon#about to read 3, iclass 21, count 0 2006.201.14:59:03.14#ibcon#read 3, iclass 21, count 0 2006.201.14:59:03.14#ibcon#about to read 4, iclass 21, count 0 2006.201.14:59:03.14#ibcon#read 4, iclass 21, count 0 2006.201.14:59:03.14#ibcon#about to read 5, iclass 21, count 0 2006.201.14:59:03.14#ibcon#read 5, iclass 21, count 0 2006.201.14:59:03.14#ibcon#about to read 6, iclass 21, count 0 2006.201.14:59:03.14#ibcon#read 6, iclass 21, count 0 2006.201.14:59:03.14#ibcon#end of sib2, iclass 21, count 0 2006.201.14:59:03.14#ibcon#*after write, iclass 21, count 0 2006.201.14:59:03.14#ibcon#*before return 0, iclass 21, count 0 2006.201.14:59:03.14#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:03.14#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.14:59:03.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.14:59:03.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.14:59:03.14$vck44/vblo=5,709.99 2006.201.14:59:03.14#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.14:59:03.14#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.14:59:03.14#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:03.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:03.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:03.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:03.14#ibcon#enter wrdev, iclass 23, count 0 2006.201.14:59:03.14#ibcon#first serial, iclass 23, count 0 2006.201.14:59:03.14#ibcon#enter sib2, iclass 23, count 0 2006.201.14:59:03.14#ibcon#flushed, iclass 23, count 0 2006.201.14:59:03.14#ibcon#about to write, iclass 23, count 0 2006.201.14:59:03.14#ibcon#wrote, iclass 23, count 0 2006.201.14:59:03.14#ibcon#about to read 3, iclass 23, count 0 2006.201.14:59:03.16#ibcon#read 3, iclass 23, count 0 2006.201.14:59:03.16#ibcon#about to read 4, iclass 23, count 0 2006.201.14:59:03.16#ibcon#read 4, iclass 23, count 0 2006.201.14:59:03.16#ibcon#about to read 5, iclass 23, count 0 2006.201.14:59:03.16#ibcon#read 5, iclass 23, count 0 2006.201.14:59:03.16#ibcon#about to read 6, iclass 23, count 0 2006.201.14:59:03.16#ibcon#read 6, iclass 23, count 0 2006.201.14:59:03.16#ibcon#end of sib2, iclass 23, count 0 2006.201.14:59:03.16#ibcon#*mode == 0, iclass 23, count 0 2006.201.14:59:03.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.14:59:03.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.14:59:03.16#ibcon#*before write, iclass 23, count 0 2006.201.14:59:03.16#ibcon#enter sib2, iclass 23, count 0 2006.201.14:59:03.16#ibcon#flushed, iclass 23, count 0 2006.201.14:59:03.16#ibcon#about to write, iclass 23, count 0 2006.201.14:59:03.16#ibcon#wrote, iclass 23, count 0 2006.201.14:59:03.16#ibcon#about to read 3, iclass 23, count 0 2006.201.14:59:03.20#ibcon#read 3, iclass 23, count 0 2006.201.14:59:03.20#ibcon#about to read 4, iclass 23, count 0 2006.201.14:59:03.20#ibcon#read 4, iclass 23, count 0 2006.201.14:59:03.20#ibcon#about to read 5, iclass 23, count 0 2006.201.14:59:03.20#ibcon#read 5, iclass 23, count 0 2006.201.14:59:03.20#ibcon#about to read 6, iclass 23, count 0 2006.201.14:59:03.20#ibcon#read 6, iclass 23, count 0 2006.201.14:59:03.20#ibcon#end of sib2, iclass 23, count 0 2006.201.14:59:03.20#ibcon#*after write, iclass 23, count 0 2006.201.14:59:03.20#ibcon#*before return 0, iclass 23, count 0 2006.201.14:59:03.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:03.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.14:59:03.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.14:59:03.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.14:59:03.20$vck44/vb=5,4 2006.201.14:59:03.20#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.14:59:03.20#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.14:59:03.20#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:03.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:03.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:03.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:03.26#ibcon#enter wrdev, iclass 25, count 2 2006.201.14:59:03.26#ibcon#first serial, iclass 25, count 2 2006.201.14:59:03.26#ibcon#enter sib2, iclass 25, count 2 2006.201.14:59:03.26#ibcon#flushed, iclass 25, count 2 2006.201.14:59:03.26#ibcon#about to write, iclass 25, count 2 2006.201.14:59:03.26#ibcon#wrote, iclass 25, count 2 2006.201.14:59:03.26#ibcon#about to read 3, iclass 25, count 2 2006.201.14:59:03.28#ibcon#read 3, iclass 25, count 2 2006.201.14:59:03.28#ibcon#about to read 4, iclass 25, count 2 2006.201.14:59:03.28#ibcon#read 4, iclass 25, count 2 2006.201.14:59:03.28#ibcon#about to read 5, iclass 25, count 2 2006.201.14:59:03.28#ibcon#read 5, iclass 25, count 2 2006.201.14:59:03.28#ibcon#about to read 6, iclass 25, count 2 2006.201.14:59:03.28#ibcon#read 6, iclass 25, count 2 2006.201.14:59:03.28#ibcon#end of sib2, iclass 25, count 2 2006.201.14:59:03.28#ibcon#*mode == 0, iclass 25, count 2 2006.201.14:59:03.28#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.14:59:03.28#ibcon#[27=AT05-04\r\n] 2006.201.14:59:03.28#ibcon#*before write, iclass 25, count 2 2006.201.14:59:03.28#ibcon#enter sib2, iclass 25, count 2 2006.201.14:59:03.28#ibcon#flushed, iclass 25, count 2 2006.201.14:59:03.28#ibcon#about to write, iclass 25, count 2 2006.201.14:59:03.28#ibcon#wrote, iclass 25, count 2 2006.201.14:59:03.28#ibcon#about to read 3, iclass 25, count 2 2006.201.14:59:03.31#ibcon#read 3, iclass 25, count 2 2006.201.14:59:03.31#ibcon#about to read 4, iclass 25, count 2 2006.201.14:59:03.31#ibcon#read 4, iclass 25, count 2 2006.201.14:59:03.31#ibcon#about to read 5, iclass 25, count 2 2006.201.14:59:03.31#ibcon#read 5, iclass 25, count 2 2006.201.14:59:03.31#ibcon#about to read 6, iclass 25, count 2 2006.201.14:59:03.31#ibcon#read 6, iclass 25, count 2 2006.201.14:59:03.31#ibcon#end of sib2, iclass 25, count 2 2006.201.14:59:03.31#ibcon#*after write, iclass 25, count 2 2006.201.14:59:03.31#ibcon#*before return 0, iclass 25, count 2 2006.201.14:59:03.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:03.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.14:59:03.31#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.14:59:03.31#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:03.31#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:03.43#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:03.43#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:03.43#ibcon#enter wrdev, iclass 25, count 0 2006.201.14:59:03.43#ibcon#first serial, iclass 25, count 0 2006.201.14:59:03.43#ibcon#enter sib2, iclass 25, count 0 2006.201.14:59:03.43#ibcon#flushed, iclass 25, count 0 2006.201.14:59:03.43#ibcon#about to write, iclass 25, count 0 2006.201.14:59:03.43#ibcon#wrote, iclass 25, count 0 2006.201.14:59:03.43#ibcon#about to read 3, iclass 25, count 0 2006.201.14:59:03.45#ibcon#read 3, iclass 25, count 0 2006.201.14:59:03.45#ibcon#about to read 4, iclass 25, count 0 2006.201.14:59:03.45#ibcon#read 4, iclass 25, count 0 2006.201.14:59:03.45#ibcon#about to read 5, iclass 25, count 0 2006.201.14:59:03.45#ibcon#read 5, iclass 25, count 0 2006.201.14:59:03.45#ibcon#about to read 6, iclass 25, count 0 2006.201.14:59:03.45#ibcon#read 6, iclass 25, count 0 2006.201.14:59:03.45#ibcon#end of sib2, iclass 25, count 0 2006.201.14:59:03.45#ibcon#*mode == 0, iclass 25, count 0 2006.201.14:59:03.45#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.14:59:03.45#ibcon#[27=USB\r\n] 2006.201.14:59:03.45#ibcon#*before write, iclass 25, count 0 2006.201.14:59:03.45#ibcon#enter sib2, iclass 25, count 0 2006.201.14:59:03.45#ibcon#flushed, iclass 25, count 0 2006.201.14:59:03.45#ibcon#about to write, iclass 25, count 0 2006.201.14:59:03.45#ibcon#wrote, iclass 25, count 0 2006.201.14:59:03.45#ibcon#about to read 3, iclass 25, count 0 2006.201.14:59:03.48#ibcon#read 3, iclass 25, count 0 2006.201.14:59:03.48#ibcon#about to read 4, iclass 25, count 0 2006.201.14:59:03.48#ibcon#read 4, iclass 25, count 0 2006.201.14:59:03.48#ibcon#about to read 5, iclass 25, count 0 2006.201.14:59:03.48#ibcon#read 5, iclass 25, count 0 2006.201.14:59:03.48#ibcon#about to read 6, iclass 25, count 0 2006.201.14:59:03.48#ibcon#read 6, iclass 25, count 0 2006.201.14:59:03.48#ibcon#end of sib2, iclass 25, count 0 2006.201.14:59:03.48#ibcon#*after write, iclass 25, count 0 2006.201.14:59:03.48#ibcon#*before return 0, iclass 25, count 0 2006.201.14:59:03.48#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:03.48#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.14:59:03.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.14:59:03.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.14:59:03.48$vck44/vblo=6,719.99 2006.201.14:59:03.48#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.14:59:03.48#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.14:59:03.48#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:03.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:03.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:03.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:03.48#ibcon#enter wrdev, iclass 27, count 0 2006.201.14:59:03.48#ibcon#first serial, iclass 27, count 0 2006.201.14:59:03.48#ibcon#enter sib2, iclass 27, count 0 2006.201.14:59:03.48#ibcon#flushed, iclass 27, count 0 2006.201.14:59:03.48#ibcon#about to write, iclass 27, count 0 2006.201.14:59:03.48#ibcon#wrote, iclass 27, count 0 2006.201.14:59:03.48#ibcon#about to read 3, iclass 27, count 0 2006.201.14:59:03.50#ibcon#read 3, iclass 27, count 0 2006.201.14:59:03.50#ibcon#about to read 4, iclass 27, count 0 2006.201.14:59:03.50#ibcon#read 4, iclass 27, count 0 2006.201.14:59:03.50#ibcon#about to read 5, iclass 27, count 0 2006.201.14:59:03.50#ibcon#read 5, iclass 27, count 0 2006.201.14:59:03.50#ibcon#about to read 6, iclass 27, count 0 2006.201.14:59:03.50#ibcon#read 6, iclass 27, count 0 2006.201.14:59:03.50#ibcon#end of sib2, iclass 27, count 0 2006.201.14:59:03.50#ibcon#*mode == 0, iclass 27, count 0 2006.201.14:59:03.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.14:59:03.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.14:59:03.50#ibcon#*before write, iclass 27, count 0 2006.201.14:59:03.50#ibcon#enter sib2, iclass 27, count 0 2006.201.14:59:03.50#ibcon#flushed, iclass 27, count 0 2006.201.14:59:03.50#ibcon#about to write, iclass 27, count 0 2006.201.14:59:03.50#ibcon#wrote, iclass 27, count 0 2006.201.14:59:03.50#ibcon#about to read 3, iclass 27, count 0 2006.201.14:59:03.55#ibcon#read 3, iclass 27, count 0 2006.201.14:59:03.55#ibcon#about to read 4, iclass 27, count 0 2006.201.14:59:03.55#ibcon#read 4, iclass 27, count 0 2006.201.14:59:03.55#ibcon#about to read 5, iclass 27, count 0 2006.201.14:59:03.55#ibcon#read 5, iclass 27, count 0 2006.201.14:59:03.55#ibcon#about to read 6, iclass 27, count 0 2006.201.14:59:03.55#ibcon#read 6, iclass 27, count 0 2006.201.14:59:03.55#ibcon#end of sib2, iclass 27, count 0 2006.201.14:59:03.55#ibcon#*after write, iclass 27, count 0 2006.201.14:59:03.55#ibcon#*before return 0, iclass 27, count 0 2006.201.14:59:03.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:03.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.14:59:03.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.14:59:03.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.14:59:03.55$vck44/vb=6,4 2006.201.14:59:03.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.14:59:03.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.14:59:03.55#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:03.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:03.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:03.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:03.60#ibcon#enter wrdev, iclass 29, count 2 2006.201.14:59:03.60#ibcon#first serial, iclass 29, count 2 2006.201.14:59:03.60#ibcon#enter sib2, iclass 29, count 2 2006.201.14:59:03.60#ibcon#flushed, iclass 29, count 2 2006.201.14:59:03.60#ibcon#about to write, iclass 29, count 2 2006.201.14:59:03.60#ibcon#wrote, iclass 29, count 2 2006.201.14:59:03.60#ibcon#about to read 3, iclass 29, count 2 2006.201.14:59:03.62#ibcon#read 3, iclass 29, count 2 2006.201.14:59:03.62#ibcon#about to read 4, iclass 29, count 2 2006.201.14:59:03.62#ibcon#read 4, iclass 29, count 2 2006.201.14:59:03.62#ibcon#about to read 5, iclass 29, count 2 2006.201.14:59:03.62#ibcon#read 5, iclass 29, count 2 2006.201.14:59:03.62#ibcon#about to read 6, iclass 29, count 2 2006.201.14:59:03.62#ibcon#read 6, iclass 29, count 2 2006.201.14:59:03.62#ibcon#end of sib2, iclass 29, count 2 2006.201.14:59:03.62#ibcon#*mode == 0, iclass 29, count 2 2006.201.14:59:03.62#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.14:59:03.62#ibcon#[27=AT06-04\r\n] 2006.201.14:59:03.62#ibcon#*before write, iclass 29, count 2 2006.201.14:59:03.62#ibcon#enter sib2, iclass 29, count 2 2006.201.14:59:03.62#ibcon#flushed, iclass 29, count 2 2006.201.14:59:03.62#ibcon#about to write, iclass 29, count 2 2006.201.14:59:03.62#ibcon#wrote, iclass 29, count 2 2006.201.14:59:03.62#ibcon#about to read 3, iclass 29, count 2 2006.201.14:59:03.65#ibcon#read 3, iclass 29, count 2 2006.201.14:59:03.65#ibcon#about to read 4, iclass 29, count 2 2006.201.14:59:03.65#ibcon#read 4, iclass 29, count 2 2006.201.14:59:03.65#ibcon#about to read 5, iclass 29, count 2 2006.201.14:59:03.65#ibcon#read 5, iclass 29, count 2 2006.201.14:59:03.65#ibcon#about to read 6, iclass 29, count 2 2006.201.14:59:03.65#ibcon#read 6, iclass 29, count 2 2006.201.14:59:03.65#ibcon#end of sib2, iclass 29, count 2 2006.201.14:59:03.65#ibcon#*after write, iclass 29, count 2 2006.201.14:59:03.65#ibcon#*before return 0, iclass 29, count 2 2006.201.14:59:03.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:03.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.14:59:03.65#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.14:59:03.65#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:03.65#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:03.77#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:03.77#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:03.77#ibcon#enter wrdev, iclass 29, count 0 2006.201.14:59:03.77#ibcon#first serial, iclass 29, count 0 2006.201.14:59:03.77#ibcon#enter sib2, iclass 29, count 0 2006.201.14:59:03.77#ibcon#flushed, iclass 29, count 0 2006.201.14:59:03.77#ibcon#about to write, iclass 29, count 0 2006.201.14:59:03.77#ibcon#wrote, iclass 29, count 0 2006.201.14:59:03.77#ibcon#about to read 3, iclass 29, count 0 2006.201.14:59:03.79#ibcon#read 3, iclass 29, count 0 2006.201.14:59:03.79#ibcon#about to read 4, iclass 29, count 0 2006.201.14:59:03.79#ibcon#read 4, iclass 29, count 0 2006.201.14:59:03.79#ibcon#about to read 5, iclass 29, count 0 2006.201.14:59:03.79#ibcon#read 5, iclass 29, count 0 2006.201.14:59:03.79#ibcon#about to read 6, iclass 29, count 0 2006.201.14:59:03.79#ibcon#read 6, iclass 29, count 0 2006.201.14:59:03.79#ibcon#end of sib2, iclass 29, count 0 2006.201.14:59:03.79#ibcon#*mode == 0, iclass 29, count 0 2006.201.14:59:03.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.14:59:03.79#ibcon#[27=USB\r\n] 2006.201.14:59:03.79#ibcon#*before write, iclass 29, count 0 2006.201.14:59:03.79#ibcon#enter sib2, iclass 29, count 0 2006.201.14:59:03.79#ibcon#flushed, iclass 29, count 0 2006.201.14:59:03.79#ibcon#about to write, iclass 29, count 0 2006.201.14:59:03.79#ibcon#wrote, iclass 29, count 0 2006.201.14:59:03.79#ibcon#about to read 3, iclass 29, count 0 2006.201.14:59:03.82#ibcon#read 3, iclass 29, count 0 2006.201.14:59:03.82#ibcon#about to read 4, iclass 29, count 0 2006.201.14:59:03.82#ibcon#read 4, iclass 29, count 0 2006.201.14:59:03.82#ibcon#about to read 5, iclass 29, count 0 2006.201.14:59:03.82#ibcon#read 5, iclass 29, count 0 2006.201.14:59:03.82#ibcon#about to read 6, iclass 29, count 0 2006.201.14:59:03.82#ibcon#read 6, iclass 29, count 0 2006.201.14:59:03.82#ibcon#end of sib2, iclass 29, count 0 2006.201.14:59:03.82#ibcon#*after write, iclass 29, count 0 2006.201.14:59:03.82#ibcon#*before return 0, iclass 29, count 0 2006.201.14:59:03.82#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:03.82#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.14:59:03.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.14:59:03.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.14:59:03.82$vck44/vblo=7,734.99 2006.201.14:59:03.82#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.14:59:03.82#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.14:59:03.82#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:03.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:59:03.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:59:03.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:59:03.82#ibcon#enter wrdev, iclass 31, count 0 2006.201.14:59:03.82#ibcon#first serial, iclass 31, count 0 2006.201.14:59:03.82#ibcon#enter sib2, iclass 31, count 0 2006.201.14:59:03.82#ibcon#flushed, iclass 31, count 0 2006.201.14:59:03.82#ibcon#about to write, iclass 31, count 0 2006.201.14:59:03.82#ibcon#wrote, iclass 31, count 0 2006.201.14:59:03.82#ibcon#about to read 3, iclass 31, count 0 2006.201.14:59:03.84#ibcon#read 3, iclass 31, count 0 2006.201.14:59:03.84#ibcon#about to read 4, iclass 31, count 0 2006.201.14:59:03.84#ibcon#read 4, iclass 31, count 0 2006.201.14:59:03.84#ibcon#about to read 5, iclass 31, count 0 2006.201.14:59:03.84#ibcon#read 5, iclass 31, count 0 2006.201.14:59:03.84#ibcon#about to read 6, iclass 31, count 0 2006.201.14:59:03.84#ibcon#read 6, iclass 31, count 0 2006.201.14:59:03.84#ibcon#end of sib2, iclass 31, count 0 2006.201.14:59:03.84#ibcon#*mode == 0, iclass 31, count 0 2006.201.14:59:03.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.14:59:03.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.14:59:03.84#ibcon#*before write, iclass 31, count 0 2006.201.14:59:03.84#ibcon#enter sib2, iclass 31, count 0 2006.201.14:59:03.84#ibcon#flushed, iclass 31, count 0 2006.201.14:59:03.84#ibcon#about to write, iclass 31, count 0 2006.201.14:59:03.84#ibcon#wrote, iclass 31, count 0 2006.201.14:59:03.84#ibcon#about to read 3, iclass 31, count 0 2006.201.14:59:03.89#ibcon#read 3, iclass 31, count 0 2006.201.14:59:03.89#ibcon#about to read 4, iclass 31, count 0 2006.201.14:59:03.89#ibcon#read 4, iclass 31, count 0 2006.201.14:59:03.89#ibcon#about to read 5, iclass 31, count 0 2006.201.14:59:03.89#ibcon#read 5, iclass 31, count 0 2006.201.14:59:03.89#ibcon#about to read 6, iclass 31, count 0 2006.201.14:59:03.89#ibcon#read 6, iclass 31, count 0 2006.201.14:59:03.89#ibcon#end of sib2, iclass 31, count 0 2006.201.14:59:03.89#ibcon#*after write, iclass 31, count 0 2006.201.14:59:03.89#ibcon#*before return 0, iclass 31, count 0 2006.201.14:59:03.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:59:03.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.14:59:03.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.14:59:03.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.14:59:03.89$vck44/vb=7,4 2006.201.14:59:03.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.14:59:03.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.14:59:03.89#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:03.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:59:03.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:59:03.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:59:03.94#ibcon#enter wrdev, iclass 33, count 2 2006.201.14:59:03.94#ibcon#first serial, iclass 33, count 2 2006.201.14:59:03.94#ibcon#enter sib2, iclass 33, count 2 2006.201.14:59:03.94#ibcon#flushed, iclass 33, count 2 2006.201.14:59:03.94#ibcon#about to write, iclass 33, count 2 2006.201.14:59:03.94#ibcon#wrote, iclass 33, count 2 2006.201.14:59:03.94#ibcon#about to read 3, iclass 33, count 2 2006.201.14:59:03.96#ibcon#read 3, iclass 33, count 2 2006.201.14:59:03.96#ibcon#about to read 4, iclass 33, count 2 2006.201.14:59:03.96#ibcon#read 4, iclass 33, count 2 2006.201.14:59:03.96#ibcon#about to read 5, iclass 33, count 2 2006.201.14:59:03.96#ibcon#read 5, iclass 33, count 2 2006.201.14:59:03.96#ibcon#about to read 6, iclass 33, count 2 2006.201.14:59:03.96#ibcon#read 6, iclass 33, count 2 2006.201.14:59:03.96#ibcon#end of sib2, iclass 33, count 2 2006.201.14:59:03.96#ibcon#*mode == 0, iclass 33, count 2 2006.201.14:59:03.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.14:59:03.96#ibcon#[27=AT07-04\r\n] 2006.201.14:59:03.96#ibcon#*before write, iclass 33, count 2 2006.201.14:59:03.96#ibcon#enter sib2, iclass 33, count 2 2006.201.14:59:03.96#ibcon#flushed, iclass 33, count 2 2006.201.14:59:03.96#ibcon#about to write, iclass 33, count 2 2006.201.14:59:03.96#ibcon#wrote, iclass 33, count 2 2006.201.14:59:03.96#ibcon#about to read 3, iclass 33, count 2 2006.201.14:59:03.99#ibcon#read 3, iclass 33, count 2 2006.201.14:59:03.99#ibcon#about to read 4, iclass 33, count 2 2006.201.14:59:03.99#ibcon#read 4, iclass 33, count 2 2006.201.14:59:03.99#ibcon#about to read 5, iclass 33, count 2 2006.201.14:59:03.99#ibcon#read 5, iclass 33, count 2 2006.201.14:59:03.99#ibcon#about to read 6, iclass 33, count 2 2006.201.14:59:03.99#ibcon#read 6, iclass 33, count 2 2006.201.14:59:03.99#ibcon#end of sib2, iclass 33, count 2 2006.201.14:59:03.99#ibcon#*after write, iclass 33, count 2 2006.201.14:59:03.99#ibcon#*before return 0, iclass 33, count 2 2006.201.14:59:03.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:59:03.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.14:59:03.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.14:59:03.99#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:03.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:59:04.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:59:04.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:59:04.11#ibcon#enter wrdev, iclass 33, count 0 2006.201.14:59:04.11#ibcon#first serial, iclass 33, count 0 2006.201.14:59:04.11#ibcon#enter sib2, iclass 33, count 0 2006.201.14:59:04.11#ibcon#flushed, iclass 33, count 0 2006.201.14:59:04.11#ibcon#about to write, iclass 33, count 0 2006.201.14:59:04.11#ibcon#wrote, iclass 33, count 0 2006.201.14:59:04.11#ibcon#about to read 3, iclass 33, count 0 2006.201.14:59:04.13#ibcon#read 3, iclass 33, count 0 2006.201.14:59:04.13#ibcon#about to read 4, iclass 33, count 0 2006.201.14:59:04.13#ibcon#read 4, iclass 33, count 0 2006.201.14:59:04.13#ibcon#about to read 5, iclass 33, count 0 2006.201.14:59:04.13#ibcon#read 5, iclass 33, count 0 2006.201.14:59:04.13#ibcon#about to read 6, iclass 33, count 0 2006.201.14:59:04.13#ibcon#read 6, iclass 33, count 0 2006.201.14:59:04.13#ibcon#end of sib2, iclass 33, count 0 2006.201.14:59:04.13#ibcon#*mode == 0, iclass 33, count 0 2006.201.14:59:04.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.14:59:04.13#ibcon#[27=USB\r\n] 2006.201.14:59:04.13#ibcon#*before write, iclass 33, count 0 2006.201.14:59:04.13#ibcon#enter sib2, iclass 33, count 0 2006.201.14:59:04.13#ibcon#flushed, iclass 33, count 0 2006.201.14:59:04.13#ibcon#about to write, iclass 33, count 0 2006.201.14:59:04.13#ibcon#wrote, iclass 33, count 0 2006.201.14:59:04.13#ibcon#about to read 3, iclass 33, count 0 2006.201.14:59:04.16#ibcon#read 3, iclass 33, count 0 2006.201.14:59:04.16#ibcon#about to read 4, iclass 33, count 0 2006.201.14:59:04.16#ibcon#read 4, iclass 33, count 0 2006.201.14:59:04.16#ibcon#about to read 5, iclass 33, count 0 2006.201.14:59:04.16#ibcon#read 5, iclass 33, count 0 2006.201.14:59:04.16#ibcon#about to read 6, iclass 33, count 0 2006.201.14:59:04.16#ibcon#read 6, iclass 33, count 0 2006.201.14:59:04.16#ibcon#end of sib2, iclass 33, count 0 2006.201.14:59:04.16#ibcon#*after write, iclass 33, count 0 2006.201.14:59:04.16#ibcon#*before return 0, iclass 33, count 0 2006.201.14:59:04.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:59:04.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.14:59:04.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.14:59:04.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.14:59:04.16$vck44/vblo=8,744.99 2006.201.14:59:04.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.14:59:04.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.14:59:04.16#ibcon#ireg 17 cls_cnt 0 2006.201.14:59:04.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:04.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:04.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:04.16#ibcon#enter wrdev, iclass 35, count 0 2006.201.14:59:04.16#ibcon#first serial, iclass 35, count 0 2006.201.14:59:04.16#ibcon#enter sib2, iclass 35, count 0 2006.201.14:59:04.16#ibcon#flushed, iclass 35, count 0 2006.201.14:59:04.16#ibcon#about to write, iclass 35, count 0 2006.201.14:59:04.16#ibcon#wrote, iclass 35, count 0 2006.201.14:59:04.16#ibcon#about to read 3, iclass 35, count 0 2006.201.14:59:04.18#ibcon#read 3, iclass 35, count 0 2006.201.14:59:04.18#ibcon#about to read 4, iclass 35, count 0 2006.201.14:59:04.18#ibcon#read 4, iclass 35, count 0 2006.201.14:59:04.18#ibcon#about to read 5, iclass 35, count 0 2006.201.14:59:04.18#ibcon#read 5, iclass 35, count 0 2006.201.14:59:04.18#ibcon#about to read 6, iclass 35, count 0 2006.201.14:59:04.18#ibcon#read 6, iclass 35, count 0 2006.201.14:59:04.18#ibcon#end of sib2, iclass 35, count 0 2006.201.14:59:04.18#ibcon#*mode == 0, iclass 35, count 0 2006.201.14:59:04.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.14:59:04.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.14:59:04.18#ibcon#*before write, iclass 35, count 0 2006.201.14:59:04.18#ibcon#enter sib2, iclass 35, count 0 2006.201.14:59:04.18#ibcon#flushed, iclass 35, count 0 2006.201.14:59:04.18#ibcon#about to write, iclass 35, count 0 2006.201.14:59:04.18#ibcon#wrote, iclass 35, count 0 2006.201.14:59:04.18#ibcon#about to read 3, iclass 35, count 0 2006.201.14:59:04.22#ibcon#read 3, iclass 35, count 0 2006.201.14:59:04.22#ibcon#about to read 4, iclass 35, count 0 2006.201.14:59:04.22#ibcon#read 4, iclass 35, count 0 2006.201.14:59:04.22#ibcon#about to read 5, iclass 35, count 0 2006.201.14:59:04.22#ibcon#read 5, iclass 35, count 0 2006.201.14:59:04.22#ibcon#about to read 6, iclass 35, count 0 2006.201.14:59:04.22#ibcon#read 6, iclass 35, count 0 2006.201.14:59:04.22#ibcon#end of sib2, iclass 35, count 0 2006.201.14:59:04.22#ibcon#*after write, iclass 35, count 0 2006.201.14:59:04.22#ibcon#*before return 0, iclass 35, count 0 2006.201.14:59:04.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:04.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.14:59:04.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.14:59:04.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.14:59:04.22$vck44/vb=8,4 2006.201.14:59:04.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.14:59:04.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.14:59:04.22#ibcon#ireg 11 cls_cnt 2 2006.201.14:59:04.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:04.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:04.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:04.28#ibcon#enter wrdev, iclass 37, count 2 2006.201.14:59:04.28#ibcon#first serial, iclass 37, count 2 2006.201.14:59:04.28#ibcon#enter sib2, iclass 37, count 2 2006.201.14:59:04.28#ibcon#flushed, iclass 37, count 2 2006.201.14:59:04.28#ibcon#about to write, iclass 37, count 2 2006.201.14:59:04.28#ibcon#wrote, iclass 37, count 2 2006.201.14:59:04.28#ibcon#about to read 3, iclass 37, count 2 2006.201.14:59:04.30#ibcon#read 3, iclass 37, count 2 2006.201.14:59:04.30#ibcon#about to read 4, iclass 37, count 2 2006.201.14:59:04.30#ibcon#read 4, iclass 37, count 2 2006.201.14:59:04.30#ibcon#about to read 5, iclass 37, count 2 2006.201.14:59:04.30#ibcon#read 5, iclass 37, count 2 2006.201.14:59:04.30#ibcon#about to read 6, iclass 37, count 2 2006.201.14:59:04.30#ibcon#read 6, iclass 37, count 2 2006.201.14:59:04.30#ibcon#end of sib2, iclass 37, count 2 2006.201.14:59:04.30#ibcon#*mode == 0, iclass 37, count 2 2006.201.14:59:04.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.14:59:04.30#ibcon#[27=AT08-04\r\n] 2006.201.14:59:04.30#ibcon#*before write, iclass 37, count 2 2006.201.14:59:04.30#ibcon#enter sib2, iclass 37, count 2 2006.201.14:59:04.30#ibcon#flushed, iclass 37, count 2 2006.201.14:59:04.30#ibcon#about to write, iclass 37, count 2 2006.201.14:59:04.30#ibcon#wrote, iclass 37, count 2 2006.201.14:59:04.30#ibcon#about to read 3, iclass 37, count 2 2006.201.14:59:04.33#ibcon#read 3, iclass 37, count 2 2006.201.14:59:04.33#ibcon#about to read 4, iclass 37, count 2 2006.201.14:59:04.33#ibcon#read 4, iclass 37, count 2 2006.201.14:59:04.33#ibcon#about to read 5, iclass 37, count 2 2006.201.14:59:04.33#ibcon#read 5, iclass 37, count 2 2006.201.14:59:04.33#ibcon#about to read 6, iclass 37, count 2 2006.201.14:59:04.33#ibcon#read 6, iclass 37, count 2 2006.201.14:59:04.33#ibcon#end of sib2, iclass 37, count 2 2006.201.14:59:04.33#ibcon#*after write, iclass 37, count 2 2006.201.14:59:04.33#ibcon#*before return 0, iclass 37, count 2 2006.201.14:59:04.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:04.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.14:59:04.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.14:59:04.33#ibcon#ireg 7 cls_cnt 0 2006.201.14:59:04.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:04.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:04.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:04.45#ibcon#enter wrdev, iclass 37, count 0 2006.201.14:59:04.45#ibcon#first serial, iclass 37, count 0 2006.201.14:59:04.45#ibcon#enter sib2, iclass 37, count 0 2006.201.14:59:04.45#ibcon#flushed, iclass 37, count 0 2006.201.14:59:04.45#ibcon#about to write, iclass 37, count 0 2006.201.14:59:04.45#ibcon#wrote, iclass 37, count 0 2006.201.14:59:04.45#ibcon#about to read 3, iclass 37, count 0 2006.201.14:59:04.47#ibcon#read 3, iclass 37, count 0 2006.201.14:59:04.47#ibcon#about to read 4, iclass 37, count 0 2006.201.14:59:04.47#ibcon#read 4, iclass 37, count 0 2006.201.14:59:04.47#ibcon#about to read 5, iclass 37, count 0 2006.201.14:59:04.47#ibcon#read 5, iclass 37, count 0 2006.201.14:59:04.47#ibcon#about to read 6, iclass 37, count 0 2006.201.14:59:04.47#ibcon#read 6, iclass 37, count 0 2006.201.14:59:04.47#ibcon#end of sib2, iclass 37, count 0 2006.201.14:59:04.47#ibcon#*mode == 0, iclass 37, count 0 2006.201.14:59:04.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.14:59:04.47#ibcon#[27=USB\r\n] 2006.201.14:59:04.47#ibcon#*before write, iclass 37, count 0 2006.201.14:59:04.47#ibcon#enter sib2, iclass 37, count 0 2006.201.14:59:04.47#ibcon#flushed, iclass 37, count 0 2006.201.14:59:04.47#ibcon#about to write, iclass 37, count 0 2006.201.14:59:04.47#ibcon#wrote, iclass 37, count 0 2006.201.14:59:04.47#ibcon#about to read 3, iclass 37, count 0 2006.201.14:59:04.50#ibcon#read 3, iclass 37, count 0 2006.201.14:59:04.50#ibcon#about to read 4, iclass 37, count 0 2006.201.14:59:04.50#ibcon#read 4, iclass 37, count 0 2006.201.14:59:04.50#ibcon#about to read 5, iclass 37, count 0 2006.201.14:59:04.50#ibcon#read 5, iclass 37, count 0 2006.201.14:59:04.50#ibcon#about to read 6, iclass 37, count 0 2006.201.14:59:04.50#ibcon#read 6, iclass 37, count 0 2006.201.14:59:04.50#ibcon#end of sib2, iclass 37, count 0 2006.201.14:59:04.50#ibcon#*after write, iclass 37, count 0 2006.201.14:59:04.50#ibcon#*before return 0, iclass 37, count 0 2006.201.14:59:04.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:04.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.14:59:04.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.14:59:04.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.14:59:04.50$vck44/vabw=wide 2006.201.14:59:04.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.14:59:04.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.14:59:04.50#ibcon#ireg 8 cls_cnt 0 2006.201.14:59:04.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:04.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:04.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:04.50#ibcon#enter wrdev, iclass 39, count 0 2006.201.14:59:04.50#ibcon#first serial, iclass 39, count 0 2006.201.14:59:04.50#ibcon#enter sib2, iclass 39, count 0 2006.201.14:59:04.50#ibcon#flushed, iclass 39, count 0 2006.201.14:59:04.50#ibcon#about to write, iclass 39, count 0 2006.201.14:59:04.50#ibcon#wrote, iclass 39, count 0 2006.201.14:59:04.50#ibcon#about to read 3, iclass 39, count 0 2006.201.14:59:04.52#ibcon#read 3, iclass 39, count 0 2006.201.14:59:04.52#ibcon#about to read 4, iclass 39, count 0 2006.201.14:59:04.52#ibcon#read 4, iclass 39, count 0 2006.201.14:59:04.52#ibcon#about to read 5, iclass 39, count 0 2006.201.14:59:04.52#ibcon#read 5, iclass 39, count 0 2006.201.14:59:04.52#ibcon#about to read 6, iclass 39, count 0 2006.201.14:59:04.52#ibcon#read 6, iclass 39, count 0 2006.201.14:59:04.52#ibcon#end of sib2, iclass 39, count 0 2006.201.14:59:04.52#ibcon#*mode == 0, iclass 39, count 0 2006.201.14:59:04.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.14:59:04.52#ibcon#[25=BW32\r\n] 2006.201.14:59:04.52#ibcon#*before write, iclass 39, count 0 2006.201.14:59:04.52#ibcon#enter sib2, iclass 39, count 0 2006.201.14:59:04.52#ibcon#flushed, iclass 39, count 0 2006.201.14:59:04.52#ibcon#about to write, iclass 39, count 0 2006.201.14:59:04.52#ibcon#wrote, iclass 39, count 0 2006.201.14:59:04.52#ibcon#about to read 3, iclass 39, count 0 2006.201.14:59:04.56#ibcon#read 3, iclass 39, count 0 2006.201.14:59:04.56#ibcon#about to read 4, iclass 39, count 0 2006.201.14:59:04.56#ibcon#read 4, iclass 39, count 0 2006.201.14:59:04.56#ibcon#about to read 5, iclass 39, count 0 2006.201.14:59:04.56#ibcon#read 5, iclass 39, count 0 2006.201.14:59:04.56#ibcon#about to read 6, iclass 39, count 0 2006.201.14:59:04.56#ibcon#read 6, iclass 39, count 0 2006.201.14:59:04.56#ibcon#end of sib2, iclass 39, count 0 2006.201.14:59:04.56#ibcon#*after write, iclass 39, count 0 2006.201.14:59:04.56#ibcon#*before return 0, iclass 39, count 0 2006.201.14:59:04.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:04.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.14:59:04.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.14:59:04.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.14:59:04.56$vck44/vbbw=wide 2006.201.14:59:04.56#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.14:59:04.56#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.14:59:04.56#ibcon#ireg 8 cls_cnt 0 2006.201.14:59:04.56#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:59:04.62#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:59:04.62#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:59:04.62#ibcon#enter wrdev, iclass 2, count 0 2006.201.14:59:04.62#ibcon#first serial, iclass 2, count 0 2006.201.14:59:04.62#ibcon#enter sib2, iclass 2, count 0 2006.201.14:59:04.62#ibcon#flushed, iclass 2, count 0 2006.201.14:59:04.62#ibcon#about to write, iclass 2, count 0 2006.201.14:59:04.62#ibcon#wrote, iclass 2, count 0 2006.201.14:59:04.62#ibcon#about to read 3, iclass 2, count 0 2006.201.14:59:04.64#ibcon#read 3, iclass 2, count 0 2006.201.14:59:04.64#ibcon#about to read 4, iclass 2, count 0 2006.201.14:59:04.64#ibcon#read 4, iclass 2, count 0 2006.201.14:59:04.64#ibcon#about to read 5, iclass 2, count 0 2006.201.14:59:04.64#ibcon#read 5, iclass 2, count 0 2006.201.14:59:04.64#ibcon#about to read 6, iclass 2, count 0 2006.201.14:59:04.64#ibcon#read 6, iclass 2, count 0 2006.201.14:59:04.64#ibcon#end of sib2, iclass 2, count 0 2006.201.14:59:04.64#ibcon#*mode == 0, iclass 2, count 0 2006.201.14:59:04.64#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.14:59:04.64#ibcon#[27=BW32\r\n] 2006.201.14:59:04.64#ibcon#*before write, iclass 2, count 0 2006.201.14:59:04.64#ibcon#enter sib2, iclass 2, count 0 2006.201.14:59:04.64#ibcon#flushed, iclass 2, count 0 2006.201.14:59:04.64#ibcon#about to write, iclass 2, count 0 2006.201.14:59:04.64#ibcon#wrote, iclass 2, count 0 2006.201.14:59:04.64#ibcon#about to read 3, iclass 2, count 0 2006.201.14:59:04.67#ibcon#read 3, iclass 2, count 0 2006.201.14:59:04.67#ibcon#about to read 4, iclass 2, count 0 2006.201.14:59:04.67#ibcon#read 4, iclass 2, count 0 2006.201.14:59:04.67#ibcon#about to read 5, iclass 2, count 0 2006.201.14:59:04.67#ibcon#read 5, iclass 2, count 0 2006.201.14:59:04.67#ibcon#about to read 6, iclass 2, count 0 2006.201.14:59:04.67#ibcon#read 6, iclass 2, count 0 2006.201.14:59:04.67#ibcon#end of sib2, iclass 2, count 0 2006.201.14:59:04.67#ibcon#*after write, iclass 2, count 0 2006.201.14:59:04.67#ibcon#*before return 0, iclass 2, count 0 2006.201.14:59:04.67#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:59:04.67#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.14:59:04.67#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.14:59:04.67#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.14:59:04.67$setupk4/ifdk4 2006.201.14:59:04.67$ifdk4/lo= 2006.201.14:59:04.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.14:59:04.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.14:59:04.67$ifdk4/patch= 2006.201.14:59:04.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.14:59:04.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.14:59:04.67$setupk4/!*+20s 2006.201.14:59:11.20#abcon#<5=/04 0.9 1.9 20.761001003.4\r\n> 2006.201.14:59:11.22#abcon#{5=INTERFACE CLEAR} 2006.201.14:59:11.29#abcon#[5=S1D000X0/0*\r\n] 2006.201.14:59:16.14#trakl#Source acquired 2006.201.14:59:18.14#flagr#flagr/antenna,acquired 2006.201.14:59:19.13$setupk4/"tpicd 2006.201.14:59:19.13$setupk4/echo=off 2006.201.14:59:19.13$setupk4/xlog=off 2006.201.14:59:19.13:!2006.201.15:00:29 2006.201.15:00:29.00:preob 2006.201.15:00:29.14/onsource/TRACKING 2006.201.15:00:29.14:!2006.201.15:00:39 2006.201.15:00:39.00:"tape 2006.201.15:00:39.00:"st=record 2006.201.15:00:39.00:data_valid=on 2006.201.15:00:39.00:midob 2006.201.15:00:39.14/onsource/TRACKING 2006.201.15:00:39.14/wx/20.76,1003.4,100 2006.201.15:00:39.30/cable/+6.4778E-03 2006.201.15:00:40.39/va/01,08,usb,yes,29,31 2006.201.15:00:40.39/va/02,07,usb,yes,31,32 2006.201.15:00:40.39/va/03,08,usb,yes,28,29 2006.201.15:00:40.39/va/04,07,usb,yes,32,34 2006.201.15:00:40.39/va/05,04,usb,yes,28,29 2006.201.15:00:40.39/va/06,05,usb,yes,28,28 2006.201.15:00:40.39/va/07,05,usb,yes,27,29 2006.201.15:00:40.39/va/08,04,usb,yes,27,33 2006.201.15:00:40.62/valo/01,524.99,yes,locked 2006.201.15:00:40.62/valo/02,534.99,yes,locked 2006.201.15:00:40.62/valo/03,564.99,yes,locked 2006.201.15:00:40.62/valo/04,624.99,yes,locked 2006.201.15:00:40.62/valo/05,734.99,yes,locked 2006.201.15:00:40.62/valo/06,814.99,yes,locked 2006.201.15:00:40.62/valo/07,864.99,yes,locked 2006.201.15:00:40.62/valo/08,884.99,yes,locked 2006.201.15:00:41.71/vb/01,04,usb,yes,29,27 2006.201.15:00:41.71/vb/02,05,usb,yes,27,27 2006.201.15:00:41.71/vb/03,04,usb,yes,28,31 2006.201.15:00:41.71/vb/04,05,usb,yes,28,27 2006.201.15:00:41.71/vb/05,04,usb,yes,25,27 2006.201.15:00:41.71/vb/06,04,usb,yes,29,25 2006.201.15:00:41.71/vb/07,04,usb,yes,29,29 2006.201.15:00:41.71/vb/08,04,usb,yes,27,30 2006.201.15:00:41.95/vblo/01,629.99,yes,locked 2006.201.15:00:41.95/vblo/02,634.99,yes,locked 2006.201.15:00:41.95/vblo/03,649.99,yes,locked 2006.201.15:00:41.95/vblo/04,679.99,yes,locked 2006.201.15:00:41.95/vblo/05,709.99,yes,locked 2006.201.15:00:41.95/vblo/06,719.99,yes,locked 2006.201.15:00:41.95/vblo/07,734.99,yes,locked 2006.201.15:00:41.95/vblo/08,744.99,yes,locked 2006.201.15:00:42.10/vabw/8 2006.201.15:00:42.25/vbbw/8 2006.201.15:00:42.34/xfe/off,on,14.5 2006.201.15:00:42.72/ifatt/23,28,28,28 2006.201.15:00:43.06/fmout-gps/S +4.57E-07 2006.201.15:00:43.10:!2006.201.15:01:39 2006.201.15:01:39.00:data_valid=off 2006.201.15:01:39.00:"et 2006.201.15:01:39.00:!+3s 2006.201.15:01:42.02:"tape 2006.201.15:01:42.02:postob 2006.201.15:01:42.21/cable/+6.4765E-03 2006.201.15:01:42.21/wx/20.76,1003.3,100 2006.201.15:01:42.29/fmout-gps/S +4.57E-07 2006.201.15:01:42.29:scan_name=201-1504,jd0607,40 2006.201.15:01:42.29:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.201.15:01:43.14#flagr#flagr/antenna,new-source 2006.201.15:01:43.14:checkk5 2006.201.15:01:43.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:01:43.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:01:44.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:01:44.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:01:44.98/chk_obsdata//k5ts1/T2011500??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.15:01:45.35/chk_obsdata//k5ts2/T2011500??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.15:01:45.71/chk_obsdata//k5ts3/T2011500??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.15:01:46.09/chk_obsdata//k5ts4/T2011500??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.201.15:01:46.77/k5log//k5ts1_log_newline 2006.201.15:01:47.46/k5log//k5ts2_log_newline 2006.201.15:01:48.15/k5log//k5ts3_log_newline 2006.201.15:01:48.83/k5log//k5ts4_log_newline 2006.201.15:01:48.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:01:48.86:setupk4=1 2006.201.15:01:48.86$setupk4/echo=on 2006.201.15:01:48.86$setupk4/pcalon 2006.201.15:01:48.86$pcalon/"no phase cal control is implemented here 2006.201.15:01:48.86$setupk4/"tpicd=stop 2006.201.15:01:48.86$setupk4/"rec=synch_on 2006.201.15:01:48.86$setupk4/"rec_mode=128 2006.201.15:01:48.86$setupk4/!* 2006.201.15:01:48.86$setupk4/recpk4 2006.201.15:01:48.86$recpk4/recpatch= 2006.201.15:01:48.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:01:48.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:01:48.86$setupk4/vck44 2006.201.15:01:48.86$vck44/valo=1,524.99 2006.201.15:01:48.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.15:01:48.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.15:01:48.86#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:48.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:48.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:48.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:48.86#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:01:48.86#ibcon#first serial, iclass 38, count 0 2006.201.15:01:48.86#ibcon#enter sib2, iclass 38, count 0 2006.201.15:01:48.86#ibcon#flushed, iclass 38, count 0 2006.201.15:01:48.86#ibcon#about to write, iclass 38, count 0 2006.201.15:01:48.86#ibcon#wrote, iclass 38, count 0 2006.201.15:01:48.86#ibcon#about to read 3, iclass 38, count 0 2006.201.15:01:48.90#ibcon#read 3, iclass 38, count 0 2006.201.15:01:48.90#ibcon#about to read 4, iclass 38, count 0 2006.201.15:01:48.90#ibcon#read 4, iclass 38, count 0 2006.201.15:01:48.90#ibcon#about to read 5, iclass 38, count 0 2006.201.15:01:48.90#ibcon#read 5, iclass 38, count 0 2006.201.15:01:48.90#ibcon#about to read 6, iclass 38, count 0 2006.201.15:01:48.90#ibcon#read 6, iclass 38, count 0 2006.201.15:01:48.90#ibcon#end of sib2, iclass 38, count 0 2006.201.15:01:48.90#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:01:48.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:01:48.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:01:48.90#ibcon#*before write, iclass 38, count 0 2006.201.15:01:48.90#ibcon#enter sib2, iclass 38, count 0 2006.201.15:01:48.90#ibcon#flushed, iclass 38, count 0 2006.201.15:01:48.90#ibcon#about to write, iclass 38, count 0 2006.201.15:01:48.90#ibcon#wrote, iclass 38, count 0 2006.201.15:01:48.90#ibcon#about to read 3, iclass 38, count 0 2006.201.15:01:48.95#ibcon#read 3, iclass 38, count 0 2006.201.15:01:48.95#ibcon#about to read 4, iclass 38, count 0 2006.201.15:01:48.95#ibcon#read 4, iclass 38, count 0 2006.201.15:01:48.95#ibcon#about to read 5, iclass 38, count 0 2006.201.15:01:48.95#ibcon#read 5, iclass 38, count 0 2006.201.15:01:48.95#ibcon#about to read 6, iclass 38, count 0 2006.201.15:01:48.95#ibcon#read 6, iclass 38, count 0 2006.201.15:01:48.95#ibcon#end of sib2, iclass 38, count 0 2006.201.15:01:48.95#ibcon#*after write, iclass 38, count 0 2006.201.15:01:48.95#ibcon#*before return 0, iclass 38, count 0 2006.201.15:01:48.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:48.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:48.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:01:48.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:01:48.95$vck44/va=1,8 2006.201.15:01:48.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.15:01:48.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.15:01:48.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:48.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:48.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:48.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:48.95#ibcon#enter wrdev, iclass 40, count 2 2006.201.15:01:48.95#ibcon#first serial, iclass 40, count 2 2006.201.15:01:48.95#ibcon#enter sib2, iclass 40, count 2 2006.201.15:01:48.95#ibcon#flushed, iclass 40, count 2 2006.201.15:01:48.95#ibcon#about to write, iclass 40, count 2 2006.201.15:01:48.95#ibcon#wrote, iclass 40, count 2 2006.201.15:01:48.95#ibcon#about to read 3, iclass 40, count 2 2006.201.15:01:48.97#ibcon#read 3, iclass 40, count 2 2006.201.15:01:48.97#ibcon#about to read 4, iclass 40, count 2 2006.201.15:01:48.97#ibcon#read 4, iclass 40, count 2 2006.201.15:01:48.97#ibcon#about to read 5, iclass 40, count 2 2006.201.15:01:48.97#ibcon#read 5, iclass 40, count 2 2006.201.15:01:48.97#ibcon#about to read 6, iclass 40, count 2 2006.201.15:01:48.97#ibcon#read 6, iclass 40, count 2 2006.201.15:01:48.97#ibcon#end of sib2, iclass 40, count 2 2006.201.15:01:48.97#ibcon#*mode == 0, iclass 40, count 2 2006.201.15:01:48.97#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.15:01:48.97#ibcon#[25=AT01-08\r\n] 2006.201.15:01:48.97#ibcon#*before write, iclass 40, count 2 2006.201.15:01:48.97#ibcon#enter sib2, iclass 40, count 2 2006.201.15:01:48.97#ibcon#flushed, iclass 40, count 2 2006.201.15:01:48.97#ibcon#about to write, iclass 40, count 2 2006.201.15:01:48.97#ibcon#wrote, iclass 40, count 2 2006.201.15:01:48.97#ibcon#about to read 3, iclass 40, count 2 2006.201.15:01:49.01#ibcon#read 3, iclass 40, count 2 2006.201.15:01:49.01#ibcon#about to read 4, iclass 40, count 2 2006.201.15:01:49.01#ibcon#read 4, iclass 40, count 2 2006.201.15:01:49.01#ibcon#about to read 5, iclass 40, count 2 2006.201.15:01:49.01#ibcon#read 5, iclass 40, count 2 2006.201.15:01:49.01#ibcon#about to read 6, iclass 40, count 2 2006.201.15:01:49.01#ibcon#read 6, iclass 40, count 2 2006.201.15:01:49.01#ibcon#end of sib2, iclass 40, count 2 2006.201.15:01:49.01#ibcon#*after write, iclass 40, count 2 2006.201.15:01:49.01#ibcon#*before return 0, iclass 40, count 2 2006.201.15:01:49.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:49.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:49.01#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.15:01:49.01#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:49.01#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:49.13#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:49.13#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:49.13#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:01:49.13#ibcon#first serial, iclass 40, count 0 2006.201.15:01:49.13#ibcon#enter sib2, iclass 40, count 0 2006.201.15:01:49.13#ibcon#flushed, iclass 40, count 0 2006.201.15:01:49.13#ibcon#about to write, iclass 40, count 0 2006.201.15:01:49.13#ibcon#wrote, iclass 40, count 0 2006.201.15:01:49.13#ibcon#about to read 3, iclass 40, count 0 2006.201.15:01:49.15#ibcon#read 3, iclass 40, count 0 2006.201.15:01:49.15#ibcon#about to read 4, iclass 40, count 0 2006.201.15:01:49.15#ibcon#read 4, iclass 40, count 0 2006.201.15:01:49.15#ibcon#about to read 5, iclass 40, count 0 2006.201.15:01:49.15#ibcon#read 5, iclass 40, count 0 2006.201.15:01:49.15#ibcon#about to read 6, iclass 40, count 0 2006.201.15:01:49.15#ibcon#read 6, iclass 40, count 0 2006.201.15:01:49.15#ibcon#end of sib2, iclass 40, count 0 2006.201.15:01:49.15#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:01:49.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:01:49.15#ibcon#[25=USB\r\n] 2006.201.15:01:49.15#ibcon#*before write, iclass 40, count 0 2006.201.15:01:49.15#ibcon#enter sib2, iclass 40, count 0 2006.201.15:01:49.15#ibcon#flushed, iclass 40, count 0 2006.201.15:01:49.15#ibcon#about to write, iclass 40, count 0 2006.201.15:01:49.15#ibcon#wrote, iclass 40, count 0 2006.201.15:01:49.15#ibcon#about to read 3, iclass 40, count 0 2006.201.15:01:49.18#ibcon#read 3, iclass 40, count 0 2006.201.15:01:49.18#ibcon#about to read 4, iclass 40, count 0 2006.201.15:01:49.18#ibcon#read 4, iclass 40, count 0 2006.201.15:01:49.18#ibcon#about to read 5, iclass 40, count 0 2006.201.15:01:49.18#ibcon#read 5, iclass 40, count 0 2006.201.15:01:49.18#ibcon#about to read 6, iclass 40, count 0 2006.201.15:01:49.18#ibcon#read 6, iclass 40, count 0 2006.201.15:01:49.18#ibcon#end of sib2, iclass 40, count 0 2006.201.15:01:49.18#ibcon#*after write, iclass 40, count 0 2006.201.15:01:49.18#ibcon#*before return 0, iclass 40, count 0 2006.201.15:01:49.18#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:49.18#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:49.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:01:49.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:01:49.18$vck44/valo=2,534.99 2006.201.15:01:49.18#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.15:01:49.18#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.15:01:49.18#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:49.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:49.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:49.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:49.18#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:01:49.18#ibcon#first serial, iclass 4, count 0 2006.201.15:01:49.18#ibcon#enter sib2, iclass 4, count 0 2006.201.15:01:49.18#ibcon#flushed, iclass 4, count 0 2006.201.15:01:49.18#ibcon#about to write, iclass 4, count 0 2006.201.15:01:49.18#ibcon#wrote, iclass 4, count 0 2006.201.15:01:49.18#ibcon#about to read 3, iclass 4, count 0 2006.201.15:01:49.20#ibcon#read 3, iclass 4, count 0 2006.201.15:01:49.20#ibcon#about to read 4, iclass 4, count 0 2006.201.15:01:49.20#ibcon#read 4, iclass 4, count 0 2006.201.15:01:49.20#ibcon#about to read 5, iclass 4, count 0 2006.201.15:01:49.20#ibcon#read 5, iclass 4, count 0 2006.201.15:01:49.20#ibcon#about to read 6, iclass 4, count 0 2006.201.15:01:49.20#ibcon#read 6, iclass 4, count 0 2006.201.15:01:49.20#ibcon#end of sib2, iclass 4, count 0 2006.201.15:01:49.20#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:01:49.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:01:49.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:01:49.20#ibcon#*before write, iclass 4, count 0 2006.201.15:01:49.20#ibcon#enter sib2, iclass 4, count 0 2006.201.15:01:49.20#ibcon#flushed, iclass 4, count 0 2006.201.15:01:49.20#ibcon#about to write, iclass 4, count 0 2006.201.15:01:49.20#ibcon#wrote, iclass 4, count 0 2006.201.15:01:49.20#ibcon#about to read 3, iclass 4, count 0 2006.201.15:01:49.25#ibcon#read 3, iclass 4, count 0 2006.201.15:01:49.25#ibcon#about to read 4, iclass 4, count 0 2006.201.15:01:49.25#ibcon#read 4, iclass 4, count 0 2006.201.15:01:49.25#ibcon#about to read 5, iclass 4, count 0 2006.201.15:01:49.25#ibcon#read 5, iclass 4, count 0 2006.201.15:01:49.25#ibcon#about to read 6, iclass 4, count 0 2006.201.15:01:49.25#ibcon#read 6, iclass 4, count 0 2006.201.15:01:49.25#ibcon#end of sib2, iclass 4, count 0 2006.201.15:01:49.25#ibcon#*after write, iclass 4, count 0 2006.201.15:01:49.25#ibcon#*before return 0, iclass 4, count 0 2006.201.15:01:49.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:49.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:49.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:01:49.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:01:49.25$vck44/va=2,7 2006.201.15:01:49.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.15:01:49.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.15:01:49.25#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:49.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:49.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:49.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:49.30#ibcon#enter wrdev, iclass 6, count 2 2006.201.15:01:49.30#ibcon#first serial, iclass 6, count 2 2006.201.15:01:49.30#ibcon#enter sib2, iclass 6, count 2 2006.201.15:01:49.30#ibcon#flushed, iclass 6, count 2 2006.201.15:01:49.30#ibcon#about to write, iclass 6, count 2 2006.201.15:01:49.30#ibcon#wrote, iclass 6, count 2 2006.201.15:01:49.30#ibcon#about to read 3, iclass 6, count 2 2006.201.15:01:49.32#ibcon#read 3, iclass 6, count 2 2006.201.15:01:49.32#ibcon#about to read 4, iclass 6, count 2 2006.201.15:01:49.32#ibcon#read 4, iclass 6, count 2 2006.201.15:01:49.32#ibcon#about to read 5, iclass 6, count 2 2006.201.15:01:49.32#ibcon#read 5, iclass 6, count 2 2006.201.15:01:49.32#ibcon#about to read 6, iclass 6, count 2 2006.201.15:01:49.32#ibcon#read 6, iclass 6, count 2 2006.201.15:01:49.32#ibcon#end of sib2, iclass 6, count 2 2006.201.15:01:49.32#ibcon#*mode == 0, iclass 6, count 2 2006.201.15:01:49.32#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.15:01:49.32#ibcon#[25=AT02-07\r\n] 2006.201.15:01:49.32#ibcon#*before write, iclass 6, count 2 2006.201.15:01:49.32#ibcon#enter sib2, iclass 6, count 2 2006.201.15:01:49.32#ibcon#flushed, iclass 6, count 2 2006.201.15:01:49.32#ibcon#about to write, iclass 6, count 2 2006.201.15:01:49.32#ibcon#wrote, iclass 6, count 2 2006.201.15:01:49.32#ibcon#about to read 3, iclass 6, count 2 2006.201.15:01:49.35#ibcon#read 3, iclass 6, count 2 2006.201.15:01:49.35#ibcon#about to read 4, iclass 6, count 2 2006.201.15:01:49.35#ibcon#read 4, iclass 6, count 2 2006.201.15:01:49.35#ibcon#about to read 5, iclass 6, count 2 2006.201.15:01:49.35#ibcon#read 5, iclass 6, count 2 2006.201.15:01:49.35#ibcon#about to read 6, iclass 6, count 2 2006.201.15:01:49.35#ibcon#read 6, iclass 6, count 2 2006.201.15:01:49.35#ibcon#end of sib2, iclass 6, count 2 2006.201.15:01:49.35#ibcon#*after write, iclass 6, count 2 2006.201.15:01:49.35#ibcon#*before return 0, iclass 6, count 2 2006.201.15:01:49.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:49.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:49.35#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.15:01:49.35#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:49.35#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:49.47#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:49.47#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:49.47#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:01:49.47#ibcon#first serial, iclass 6, count 0 2006.201.15:01:49.47#ibcon#enter sib2, iclass 6, count 0 2006.201.15:01:49.47#ibcon#flushed, iclass 6, count 0 2006.201.15:01:49.47#ibcon#about to write, iclass 6, count 0 2006.201.15:01:49.47#ibcon#wrote, iclass 6, count 0 2006.201.15:01:49.47#ibcon#about to read 3, iclass 6, count 0 2006.201.15:01:49.49#ibcon#read 3, iclass 6, count 0 2006.201.15:01:49.49#ibcon#about to read 4, iclass 6, count 0 2006.201.15:01:49.49#ibcon#read 4, iclass 6, count 0 2006.201.15:01:49.49#ibcon#about to read 5, iclass 6, count 0 2006.201.15:01:49.49#ibcon#read 5, iclass 6, count 0 2006.201.15:01:49.49#ibcon#about to read 6, iclass 6, count 0 2006.201.15:01:49.49#ibcon#read 6, iclass 6, count 0 2006.201.15:01:49.49#ibcon#end of sib2, iclass 6, count 0 2006.201.15:01:49.49#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:01:49.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:01:49.49#ibcon#[25=USB\r\n] 2006.201.15:01:49.49#ibcon#*before write, iclass 6, count 0 2006.201.15:01:49.49#ibcon#enter sib2, iclass 6, count 0 2006.201.15:01:49.49#ibcon#flushed, iclass 6, count 0 2006.201.15:01:49.49#ibcon#about to write, iclass 6, count 0 2006.201.15:01:49.49#ibcon#wrote, iclass 6, count 0 2006.201.15:01:49.49#ibcon#about to read 3, iclass 6, count 0 2006.201.15:01:49.52#ibcon#read 3, iclass 6, count 0 2006.201.15:01:49.52#ibcon#about to read 4, iclass 6, count 0 2006.201.15:01:49.52#ibcon#read 4, iclass 6, count 0 2006.201.15:01:49.52#ibcon#about to read 5, iclass 6, count 0 2006.201.15:01:49.52#ibcon#read 5, iclass 6, count 0 2006.201.15:01:49.52#ibcon#about to read 6, iclass 6, count 0 2006.201.15:01:49.52#ibcon#read 6, iclass 6, count 0 2006.201.15:01:49.52#ibcon#end of sib2, iclass 6, count 0 2006.201.15:01:49.52#ibcon#*after write, iclass 6, count 0 2006.201.15:01:49.52#ibcon#*before return 0, iclass 6, count 0 2006.201.15:01:49.52#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:49.52#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:49.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:01:49.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:01:49.52$vck44/valo=3,564.99 2006.201.15:01:49.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.15:01:49.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.15:01:49.52#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:49.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:49.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:49.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:49.52#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:01:49.52#ibcon#first serial, iclass 10, count 0 2006.201.15:01:49.52#ibcon#enter sib2, iclass 10, count 0 2006.201.15:01:49.52#ibcon#flushed, iclass 10, count 0 2006.201.15:01:49.52#ibcon#about to write, iclass 10, count 0 2006.201.15:01:49.52#ibcon#wrote, iclass 10, count 0 2006.201.15:01:49.52#ibcon#about to read 3, iclass 10, count 0 2006.201.15:01:49.54#ibcon#read 3, iclass 10, count 0 2006.201.15:01:49.54#ibcon#about to read 4, iclass 10, count 0 2006.201.15:01:49.54#ibcon#read 4, iclass 10, count 0 2006.201.15:01:49.54#ibcon#about to read 5, iclass 10, count 0 2006.201.15:01:49.54#ibcon#read 5, iclass 10, count 0 2006.201.15:01:49.54#ibcon#about to read 6, iclass 10, count 0 2006.201.15:01:49.54#ibcon#read 6, iclass 10, count 0 2006.201.15:01:49.54#ibcon#end of sib2, iclass 10, count 0 2006.201.15:01:49.54#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:01:49.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:01:49.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:01:49.54#ibcon#*before write, iclass 10, count 0 2006.201.15:01:49.54#ibcon#enter sib2, iclass 10, count 0 2006.201.15:01:49.54#ibcon#flushed, iclass 10, count 0 2006.201.15:01:49.54#ibcon#about to write, iclass 10, count 0 2006.201.15:01:49.54#ibcon#wrote, iclass 10, count 0 2006.201.15:01:49.54#ibcon#about to read 3, iclass 10, count 0 2006.201.15:01:49.59#ibcon#read 3, iclass 10, count 0 2006.201.15:01:49.59#ibcon#about to read 4, iclass 10, count 0 2006.201.15:01:49.59#ibcon#read 4, iclass 10, count 0 2006.201.15:01:49.59#ibcon#about to read 5, iclass 10, count 0 2006.201.15:01:49.59#ibcon#read 5, iclass 10, count 0 2006.201.15:01:49.59#ibcon#about to read 6, iclass 10, count 0 2006.201.15:01:49.59#ibcon#read 6, iclass 10, count 0 2006.201.15:01:49.59#ibcon#end of sib2, iclass 10, count 0 2006.201.15:01:49.59#ibcon#*after write, iclass 10, count 0 2006.201.15:01:49.59#ibcon#*before return 0, iclass 10, count 0 2006.201.15:01:49.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:49.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:49.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:01:49.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:01:49.59$vck44/va=3,8 2006.201.15:01:49.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.15:01:49.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.15:01:49.59#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:49.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:49.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:49.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:49.64#ibcon#enter wrdev, iclass 12, count 2 2006.201.15:01:49.64#ibcon#first serial, iclass 12, count 2 2006.201.15:01:49.64#ibcon#enter sib2, iclass 12, count 2 2006.201.15:01:49.64#ibcon#flushed, iclass 12, count 2 2006.201.15:01:49.64#ibcon#about to write, iclass 12, count 2 2006.201.15:01:49.64#ibcon#wrote, iclass 12, count 2 2006.201.15:01:49.64#ibcon#about to read 3, iclass 12, count 2 2006.201.15:01:49.66#ibcon#read 3, iclass 12, count 2 2006.201.15:01:49.66#ibcon#about to read 4, iclass 12, count 2 2006.201.15:01:49.66#ibcon#read 4, iclass 12, count 2 2006.201.15:01:49.66#ibcon#about to read 5, iclass 12, count 2 2006.201.15:01:49.66#ibcon#read 5, iclass 12, count 2 2006.201.15:01:49.66#ibcon#about to read 6, iclass 12, count 2 2006.201.15:01:49.66#ibcon#read 6, iclass 12, count 2 2006.201.15:01:49.66#ibcon#end of sib2, iclass 12, count 2 2006.201.15:01:49.66#ibcon#*mode == 0, iclass 12, count 2 2006.201.15:01:49.66#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.15:01:49.66#ibcon#[25=AT03-08\r\n] 2006.201.15:01:49.66#ibcon#*before write, iclass 12, count 2 2006.201.15:01:49.66#ibcon#enter sib2, iclass 12, count 2 2006.201.15:01:49.66#ibcon#flushed, iclass 12, count 2 2006.201.15:01:49.66#ibcon#about to write, iclass 12, count 2 2006.201.15:01:49.66#ibcon#wrote, iclass 12, count 2 2006.201.15:01:49.66#ibcon#about to read 3, iclass 12, count 2 2006.201.15:01:49.69#ibcon#read 3, iclass 12, count 2 2006.201.15:01:49.69#ibcon#about to read 4, iclass 12, count 2 2006.201.15:01:49.69#ibcon#read 4, iclass 12, count 2 2006.201.15:01:49.69#ibcon#about to read 5, iclass 12, count 2 2006.201.15:01:49.69#ibcon#read 5, iclass 12, count 2 2006.201.15:01:49.69#ibcon#about to read 6, iclass 12, count 2 2006.201.15:01:49.69#ibcon#read 6, iclass 12, count 2 2006.201.15:01:49.69#ibcon#end of sib2, iclass 12, count 2 2006.201.15:01:49.69#ibcon#*after write, iclass 12, count 2 2006.201.15:01:49.69#ibcon#*before return 0, iclass 12, count 2 2006.201.15:01:49.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:49.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:49.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.15:01:49.69#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:49.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:49.81#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:49.81#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:49.81#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:01:49.81#ibcon#first serial, iclass 12, count 0 2006.201.15:01:49.81#ibcon#enter sib2, iclass 12, count 0 2006.201.15:01:49.81#ibcon#flushed, iclass 12, count 0 2006.201.15:01:49.81#ibcon#about to write, iclass 12, count 0 2006.201.15:01:49.81#ibcon#wrote, iclass 12, count 0 2006.201.15:01:49.81#ibcon#about to read 3, iclass 12, count 0 2006.201.15:01:49.83#ibcon#read 3, iclass 12, count 0 2006.201.15:01:49.83#ibcon#about to read 4, iclass 12, count 0 2006.201.15:01:49.83#ibcon#read 4, iclass 12, count 0 2006.201.15:01:49.83#ibcon#about to read 5, iclass 12, count 0 2006.201.15:01:49.83#ibcon#read 5, iclass 12, count 0 2006.201.15:01:49.83#ibcon#about to read 6, iclass 12, count 0 2006.201.15:01:49.83#ibcon#read 6, iclass 12, count 0 2006.201.15:01:49.83#ibcon#end of sib2, iclass 12, count 0 2006.201.15:01:49.83#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:01:49.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:01:49.83#ibcon#[25=USB\r\n] 2006.201.15:01:49.83#ibcon#*before write, iclass 12, count 0 2006.201.15:01:49.83#ibcon#enter sib2, iclass 12, count 0 2006.201.15:01:49.83#ibcon#flushed, iclass 12, count 0 2006.201.15:01:49.83#ibcon#about to write, iclass 12, count 0 2006.201.15:01:49.83#ibcon#wrote, iclass 12, count 0 2006.201.15:01:49.83#ibcon#about to read 3, iclass 12, count 0 2006.201.15:01:49.86#ibcon#read 3, iclass 12, count 0 2006.201.15:01:49.86#ibcon#about to read 4, iclass 12, count 0 2006.201.15:01:49.86#ibcon#read 4, iclass 12, count 0 2006.201.15:01:49.86#ibcon#about to read 5, iclass 12, count 0 2006.201.15:01:49.86#ibcon#read 5, iclass 12, count 0 2006.201.15:01:49.86#ibcon#about to read 6, iclass 12, count 0 2006.201.15:01:49.86#ibcon#read 6, iclass 12, count 0 2006.201.15:01:49.86#ibcon#end of sib2, iclass 12, count 0 2006.201.15:01:49.86#ibcon#*after write, iclass 12, count 0 2006.201.15:01:49.86#ibcon#*before return 0, iclass 12, count 0 2006.201.15:01:49.86#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:49.86#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:49.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:01:49.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:01:49.86$vck44/valo=4,624.99 2006.201.15:01:49.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.15:01:49.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.15:01:49.86#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:49.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:49.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:49.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:49.86#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:01:49.86#ibcon#first serial, iclass 14, count 0 2006.201.15:01:49.86#ibcon#enter sib2, iclass 14, count 0 2006.201.15:01:49.86#ibcon#flushed, iclass 14, count 0 2006.201.15:01:49.86#ibcon#about to write, iclass 14, count 0 2006.201.15:01:49.86#ibcon#wrote, iclass 14, count 0 2006.201.15:01:49.86#ibcon#about to read 3, iclass 14, count 0 2006.201.15:01:49.88#ibcon#read 3, iclass 14, count 0 2006.201.15:01:49.88#ibcon#about to read 4, iclass 14, count 0 2006.201.15:01:49.88#ibcon#read 4, iclass 14, count 0 2006.201.15:01:49.88#ibcon#about to read 5, iclass 14, count 0 2006.201.15:01:49.88#ibcon#read 5, iclass 14, count 0 2006.201.15:01:49.88#ibcon#about to read 6, iclass 14, count 0 2006.201.15:01:49.88#ibcon#read 6, iclass 14, count 0 2006.201.15:01:49.88#ibcon#end of sib2, iclass 14, count 0 2006.201.15:01:49.88#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:01:49.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:01:49.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:01:49.88#ibcon#*before write, iclass 14, count 0 2006.201.15:01:49.88#ibcon#enter sib2, iclass 14, count 0 2006.201.15:01:49.88#ibcon#flushed, iclass 14, count 0 2006.201.15:01:49.88#ibcon#about to write, iclass 14, count 0 2006.201.15:01:49.88#ibcon#wrote, iclass 14, count 0 2006.201.15:01:49.88#ibcon#about to read 3, iclass 14, count 0 2006.201.15:01:49.93#ibcon#read 3, iclass 14, count 0 2006.201.15:01:49.93#ibcon#about to read 4, iclass 14, count 0 2006.201.15:01:49.93#ibcon#read 4, iclass 14, count 0 2006.201.15:01:49.93#ibcon#about to read 5, iclass 14, count 0 2006.201.15:01:49.93#ibcon#read 5, iclass 14, count 0 2006.201.15:01:49.93#ibcon#about to read 6, iclass 14, count 0 2006.201.15:01:49.93#ibcon#read 6, iclass 14, count 0 2006.201.15:01:49.93#ibcon#end of sib2, iclass 14, count 0 2006.201.15:01:49.93#ibcon#*after write, iclass 14, count 0 2006.201.15:01:49.93#ibcon#*before return 0, iclass 14, count 0 2006.201.15:01:49.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:49.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:49.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:01:49.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:01:49.93$vck44/va=4,7 2006.201.15:01:49.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.15:01:49.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.15:01:49.93#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:49.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:49.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:49.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:49.98#ibcon#enter wrdev, iclass 16, count 2 2006.201.15:01:49.98#ibcon#first serial, iclass 16, count 2 2006.201.15:01:49.98#ibcon#enter sib2, iclass 16, count 2 2006.201.15:01:49.98#ibcon#flushed, iclass 16, count 2 2006.201.15:01:49.98#ibcon#about to write, iclass 16, count 2 2006.201.15:01:49.98#ibcon#wrote, iclass 16, count 2 2006.201.15:01:49.98#ibcon#about to read 3, iclass 16, count 2 2006.201.15:01:50.00#ibcon#read 3, iclass 16, count 2 2006.201.15:01:50.00#ibcon#about to read 4, iclass 16, count 2 2006.201.15:01:50.00#ibcon#read 4, iclass 16, count 2 2006.201.15:01:50.00#ibcon#about to read 5, iclass 16, count 2 2006.201.15:01:50.00#ibcon#read 5, iclass 16, count 2 2006.201.15:01:50.00#ibcon#about to read 6, iclass 16, count 2 2006.201.15:01:50.00#ibcon#read 6, iclass 16, count 2 2006.201.15:01:50.00#ibcon#end of sib2, iclass 16, count 2 2006.201.15:01:50.00#ibcon#*mode == 0, iclass 16, count 2 2006.201.15:01:50.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.15:01:50.00#ibcon#[25=AT04-07\r\n] 2006.201.15:01:50.00#ibcon#*before write, iclass 16, count 2 2006.201.15:01:50.00#ibcon#enter sib2, iclass 16, count 2 2006.201.15:01:50.00#ibcon#flushed, iclass 16, count 2 2006.201.15:01:50.00#ibcon#about to write, iclass 16, count 2 2006.201.15:01:50.00#ibcon#wrote, iclass 16, count 2 2006.201.15:01:50.00#ibcon#about to read 3, iclass 16, count 2 2006.201.15:01:50.03#ibcon#read 3, iclass 16, count 2 2006.201.15:01:50.03#ibcon#about to read 4, iclass 16, count 2 2006.201.15:01:50.03#ibcon#read 4, iclass 16, count 2 2006.201.15:01:50.03#ibcon#about to read 5, iclass 16, count 2 2006.201.15:01:50.03#ibcon#read 5, iclass 16, count 2 2006.201.15:01:50.03#ibcon#about to read 6, iclass 16, count 2 2006.201.15:01:50.03#ibcon#read 6, iclass 16, count 2 2006.201.15:01:50.03#ibcon#end of sib2, iclass 16, count 2 2006.201.15:01:50.03#ibcon#*after write, iclass 16, count 2 2006.201.15:01:50.03#ibcon#*before return 0, iclass 16, count 2 2006.201.15:01:50.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:50.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:50.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.15:01:50.03#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:50.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:50.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:50.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:50.15#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:01:50.15#ibcon#first serial, iclass 16, count 0 2006.201.15:01:50.15#ibcon#enter sib2, iclass 16, count 0 2006.201.15:01:50.15#ibcon#flushed, iclass 16, count 0 2006.201.15:01:50.15#ibcon#about to write, iclass 16, count 0 2006.201.15:01:50.15#ibcon#wrote, iclass 16, count 0 2006.201.15:01:50.15#ibcon#about to read 3, iclass 16, count 0 2006.201.15:01:50.17#ibcon#read 3, iclass 16, count 0 2006.201.15:01:50.17#ibcon#about to read 4, iclass 16, count 0 2006.201.15:01:50.17#ibcon#read 4, iclass 16, count 0 2006.201.15:01:50.17#ibcon#about to read 5, iclass 16, count 0 2006.201.15:01:50.17#ibcon#read 5, iclass 16, count 0 2006.201.15:01:50.17#ibcon#about to read 6, iclass 16, count 0 2006.201.15:01:50.17#ibcon#read 6, iclass 16, count 0 2006.201.15:01:50.17#ibcon#end of sib2, iclass 16, count 0 2006.201.15:01:50.17#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:01:50.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:01:50.17#ibcon#[25=USB\r\n] 2006.201.15:01:50.17#ibcon#*before write, iclass 16, count 0 2006.201.15:01:50.17#ibcon#enter sib2, iclass 16, count 0 2006.201.15:01:50.17#ibcon#flushed, iclass 16, count 0 2006.201.15:01:50.17#ibcon#about to write, iclass 16, count 0 2006.201.15:01:50.17#ibcon#wrote, iclass 16, count 0 2006.201.15:01:50.17#ibcon#about to read 3, iclass 16, count 0 2006.201.15:01:50.20#ibcon#read 3, iclass 16, count 0 2006.201.15:01:50.20#ibcon#about to read 4, iclass 16, count 0 2006.201.15:01:50.20#ibcon#read 4, iclass 16, count 0 2006.201.15:01:50.20#ibcon#about to read 5, iclass 16, count 0 2006.201.15:01:50.20#ibcon#read 5, iclass 16, count 0 2006.201.15:01:50.20#ibcon#about to read 6, iclass 16, count 0 2006.201.15:01:50.20#ibcon#read 6, iclass 16, count 0 2006.201.15:01:50.20#ibcon#end of sib2, iclass 16, count 0 2006.201.15:01:50.20#ibcon#*after write, iclass 16, count 0 2006.201.15:01:50.20#ibcon#*before return 0, iclass 16, count 0 2006.201.15:01:50.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:50.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:50.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:01:50.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:01:50.20$vck44/valo=5,734.99 2006.201.15:01:50.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.15:01:50.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.15:01:50.20#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:50.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:50.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:50.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:50.20#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:01:50.20#ibcon#first serial, iclass 18, count 0 2006.201.15:01:50.20#ibcon#enter sib2, iclass 18, count 0 2006.201.15:01:50.20#ibcon#flushed, iclass 18, count 0 2006.201.15:01:50.20#ibcon#about to write, iclass 18, count 0 2006.201.15:01:50.20#ibcon#wrote, iclass 18, count 0 2006.201.15:01:50.20#ibcon#about to read 3, iclass 18, count 0 2006.201.15:01:50.22#ibcon#read 3, iclass 18, count 0 2006.201.15:01:50.22#ibcon#about to read 4, iclass 18, count 0 2006.201.15:01:50.22#ibcon#read 4, iclass 18, count 0 2006.201.15:01:50.22#ibcon#about to read 5, iclass 18, count 0 2006.201.15:01:50.22#ibcon#read 5, iclass 18, count 0 2006.201.15:01:50.22#ibcon#about to read 6, iclass 18, count 0 2006.201.15:01:50.22#ibcon#read 6, iclass 18, count 0 2006.201.15:01:50.22#ibcon#end of sib2, iclass 18, count 0 2006.201.15:01:50.22#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:01:50.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:01:50.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:01:50.22#ibcon#*before write, iclass 18, count 0 2006.201.15:01:50.22#ibcon#enter sib2, iclass 18, count 0 2006.201.15:01:50.22#ibcon#flushed, iclass 18, count 0 2006.201.15:01:50.22#ibcon#about to write, iclass 18, count 0 2006.201.15:01:50.22#ibcon#wrote, iclass 18, count 0 2006.201.15:01:50.22#ibcon#about to read 3, iclass 18, count 0 2006.201.15:01:50.26#ibcon#read 3, iclass 18, count 0 2006.201.15:01:50.26#ibcon#about to read 4, iclass 18, count 0 2006.201.15:01:50.26#ibcon#read 4, iclass 18, count 0 2006.201.15:01:50.26#ibcon#about to read 5, iclass 18, count 0 2006.201.15:01:50.26#ibcon#read 5, iclass 18, count 0 2006.201.15:01:50.26#ibcon#about to read 6, iclass 18, count 0 2006.201.15:01:50.26#ibcon#read 6, iclass 18, count 0 2006.201.15:01:50.26#ibcon#end of sib2, iclass 18, count 0 2006.201.15:01:50.26#ibcon#*after write, iclass 18, count 0 2006.201.15:01:50.26#ibcon#*before return 0, iclass 18, count 0 2006.201.15:01:50.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:50.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:50.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:01:50.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:01:50.26$vck44/va=5,4 2006.201.15:01:50.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.15:01:50.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.15:01:50.26#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:50.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:50.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:50.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:50.32#ibcon#enter wrdev, iclass 20, count 2 2006.201.15:01:50.32#ibcon#first serial, iclass 20, count 2 2006.201.15:01:50.32#ibcon#enter sib2, iclass 20, count 2 2006.201.15:01:50.32#ibcon#flushed, iclass 20, count 2 2006.201.15:01:50.32#ibcon#about to write, iclass 20, count 2 2006.201.15:01:50.32#ibcon#wrote, iclass 20, count 2 2006.201.15:01:50.32#ibcon#about to read 3, iclass 20, count 2 2006.201.15:01:50.34#ibcon#read 3, iclass 20, count 2 2006.201.15:01:50.34#ibcon#about to read 4, iclass 20, count 2 2006.201.15:01:50.34#ibcon#read 4, iclass 20, count 2 2006.201.15:01:50.34#ibcon#about to read 5, iclass 20, count 2 2006.201.15:01:50.34#ibcon#read 5, iclass 20, count 2 2006.201.15:01:50.34#ibcon#about to read 6, iclass 20, count 2 2006.201.15:01:50.34#ibcon#read 6, iclass 20, count 2 2006.201.15:01:50.34#ibcon#end of sib2, iclass 20, count 2 2006.201.15:01:50.34#ibcon#*mode == 0, iclass 20, count 2 2006.201.15:01:50.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.15:01:50.34#ibcon#[25=AT05-04\r\n] 2006.201.15:01:50.34#ibcon#*before write, iclass 20, count 2 2006.201.15:01:50.34#ibcon#enter sib2, iclass 20, count 2 2006.201.15:01:50.34#ibcon#flushed, iclass 20, count 2 2006.201.15:01:50.34#ibcon#about to write, iclass 20, count 2 2006.201.15:01:50.34#ibcon#wrote, iclass 20, count 2 2006.201.15:01:50.34#ibcon#about to read 3, iclass 20, count 2 2006.201.15:01:50.37#ibcon#read 3, iclass 20, count 2 2006.201.15:01:50.37#ibcon#about to read 4, iclass 20, count 2 2006.201.15:01:50.37#ibcon#read 4, iclass 20, count 2 2006.201.15:01:50.37#ibcon#about to read 5, iclass 20, count 2 2006.201.15:01:50.37#ibcon#read 5, iclass 20, count 2 2006.201.15:01:50.37#ibcon#about to read 6, iclass 20, count 2 2006.201.15:01:50.37#ibcon#read 6, iclass 20, count 2 2006.201.15:01:50.37#ibcon#end of sib2, iclass 20, count 2 2006.201.15:01:50.37#ibcon#*after write, iclass 20, count 2 2006.201.15:01:50.37#ibcon#*before return 0, iclass 20, count 2 2006.201.15:01:50.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:50.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:50.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.15:01:50.37#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:50.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:50.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:50.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:50.49#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:01:50.49#ibcon#first serial, iclass 20, count 0 2006.201.15:01:50.49#ibcon#enter sib2, iclass 20, count 0 2006.201.15:01:50.49#ibcon#flushed, iclass 20, count 0 2006.201.15:01:50.49#ibcon#about to write, iclass 20, count 0 2006.201.15:01:50.49#ibcon#wrote, iclass 20, count 0 2006.201.15:01:50.49#ibcon#about to read 3, iclass 20, count 0 2006.201.15:01:50.51#ibcon#read 3, iclass 20, count 0 2006.201.15:01:50.51#ibcon#about to read 4, iclass 20, count 0 2006.201.15:01:50.51#ibcon#read 4, iclass 20, count 0 2006.201.15:01:50.51#ibcon#about to read 5, iclass 20, count 0 2006.201.15:01:50.51#ibcon#read 5, iclass 20, count 0 2006.201.15:01:50.51#ibcon#about to read 6, iclass 20, count 0 2006.201.15:01:50.51#ibcon#read 6, iclass 20, count 0 2006.201.15:01:50.51#ibcon#end of sib2, iclass 20, count 0 2006.201.15:01:50.51#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:01:50.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:01:50.51#ibcon#[25=USB\r\n] 2006.201.15:01:50.51#ibcon#*before write, iclass 20, count 0 2006.201.15:01:50.51#ibcon#enter sib2, iclass 20, count 0 2006.201.15:01:50.51#ibcon#flushed, iclass 20, count 0 2006.201.15:01:50.51#ibcon#about to write, iclass 20, count 0 2006.201.15:01:50.51#ibcon#wrote, iclass 20, count 0 2006.201.15:01:50.51#ibcon#about to read 3, iclass 20, count 0 2006.201.15:01:50.54#ibcon#read 3, iclass 20, count 0 2006.201.15:01:50.54#ibcon#about to read 4, iclass 20, count 0 2006.201.15:01:50.54#ibcon#read 4, iclass 20, count 0 2006.201.15:01:50.54#ibcon#about to read 5, iclass 20, count 0 2006.201.15:01:50.54#ibcon#read 5, iclass 20, count 0 2006.201.15:01:50.54#ibcon#about to read 6, iclass 20, count 0 2006.201.15:01:50.54#ibcon#read 6, iclass 20, count 0 2006.201.15:01:50.54#ibcon#end of sib2, iclass 20, count 0 2006.201.15:01:50.54#ibcon#*after write, iclass 20, count 0 2006.201.15:01:50.54#ibcon#*before return 0, iclass 20, count 0 2006.201.15:01:50.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:50.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:50.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:01:50.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:01:50.54$vck44/valo=6,814.99 2006.201.15:01:50.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.15:01:50.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.15:01:50.54#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:50.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:50.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:50.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:50.54#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:01:50.54#ibcon#first serial, iclass 22, count 0 2006.201.15:01:50.54#ibcon#enter sib2, iclass 22, count 0 2006.201.15:01:50.54#ibcon#flushed, iclass 22, count 0 2006.201.15:01:50.54#ibcon#about to write, iclass 22, count 0 2006.201.15:01:50.54#ibcon#wrote, iclass 22, count 0 2006.201.15:01:50.54#ibcon#about to read 3, iclass 22, count 0 2006.201.15:01:50.56#ibcon#read 3, iclass 22, count 0 2006.201.15:01:50.56#ibcon#about to read 4, iclass 22, count 0 2006.201.15:01:50.56#ibcon#read 4, iclass 22, count 0 2006.201.15:01:50.56#ibcon#about to read 5, iclass 22, count 0 2006.201.15:01:50.56#ibcon#read 5, iclass 22, count 0 2006.201.15:01:50.56#ibcon#about to read 6, iclass 22, count 0 2006.201.15:01:50.56#ibcon#read 6, iclass 22, count 0 2006.201.15:01:50.56#ibcon#end of sib2, iclass 22, count 0 2006.201.15:01:50.56#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:01:50.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:01:50.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:01:50.56#ibcon#*before write, iclass 22, count 0 2006.201.15:01:50.56#ibcon#enter sib2, iclass 22, count 0 2006.201.15:01:50.56#ibcon#flushed, iclass 22, count 0 2006.201.15:01:50.56#ibcon#about to write, iclass 22, count 0 2006.201.15:01:50.56#ibcon#wrote, iclass 22, count 0 2006.201.15:01:50.56#ibcon#about to read 3, iclass 22, count 0 2006.201.15:01:50.61#ibcon#read 3, iclass 22, count 0 2006.201.15:01:50.61#ibcon#about to read 4, iclass 22, count 0 2006.201.15:01:50.61#ibcon#read 4, iclass 22, count 0 2006.201.15:01:50.61#ibcon#about to read 5, iclass 22, count 0 2006.201.15:01:50.61#ibcon#read 5, iclass 22, count 0 2006.201.15:01:50.61#ibcon#about to read 6, iclass 22, count 0 2006.201.15:01:50.61#ibcon#read 6, iclass 22, count 0 2006.201.15:01:50.61#ibcon#end of sib2, iclass 22, count 0 2006.201.15:01:50.61#ibcon#*after write, iclass 22, count 0 2006.201.15:01:50.61#ibcon#*before return 0, iclass 22, count 0 2006.201.15:01:50.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:50.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:50.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:01:50.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:01:50.61$vck44/va=6,5 2006.201.15:01:50.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.15:01:50.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.15:01:50.61#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:50.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:50.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:50.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:50.66#ibcon#enter wrdev, iclass 24, count 2 2006.201.15:01:50.66#ibcon#first serial, iclass 24, count 2 2006.201.15:01:50.66#ibcon#enter sib2, iclass 24, count 2 2006.201.15:01:50.66#ibcon#flushed, iclass 24, count 2 2006.201.15:01:50.66#ibcon#about to write, iclass 24, count 2 2006.201.15:01:50.66#ibcon#wrote, iclass 24, count 2 2006.201.15:01:50.66#ibcon#about to read 3, iclass 24, count 2 2006.201.15:01:50.68#ibcon#read 3, iclass 24, count 2 2006.201.15:01:50.68#ibcon#about to read 4, iclass 24, count 2 2006.201.15:01:50.68#ibcon#read 4, iclass 24, count 2 2006.201.15:01:50.68#ibcon#about to read 5, iclass 24, count 2 2006.201.15:01:50.68#ibcon#read 5, iclass 24, count 2 2006.201.15:01:50.68#ibcon#about to read 6, iclass 24, count 2 2006.201.15:01:50.68#ibcon#read 6, iclass 24, count 2 2006.201.15:01:50.68#ibcon#end of sib2, iclass 24, count 2 2006.201.15:01:50.68#ibcon#*mode == 0, iclass 24, count 2 2006.201.15:01:50.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.15:01:50.68#ibcon#[25=AT06-05\r\n] 2006.201.15:01:50.68#ibcon#*before write, iclass 24, count 2 2006.201.15:01:50.68#ibcon#enter sib2, iclass 24, count 2 2006.201.15:01:50.68#ibcon#flushed, iclass 24, count 2 2006.201.15:01:50.68#ibcon#about to write, iclass 24, count 2 2006.201.15:01:50.68#ibcon#wrote, iclass 24, count 2 2006.201.15:01:50.68#ibcon#about to read 3, iclass 24, count 2 2006.201.15:01:50.71#ibcon#read 3, iclass 24, count 2 2006.201.15:01:50.71#ibcon#about to read 4, iclass 24, count 2 2006.201.15:01:50.71#ibcon#read 4, iclass 24, count 2 2006.201.15:01:50.71#ibcon#about to read 5, iclass 24, count 2 2006.201.15:01:50.71#ibcon#read 5, iclass 24, count 2 2006.201.15:01:50.71#ibcon#about to read 6, iclass 24, count 2 2006.201.15:01:50.71#ibcon#read 6, iclass 24, count 2 2006.201.15:01:50.71#ibcon#end of sib2, iclass 24, count 2 2006.201.15:01:50.71#ibcon#*after write, iclass 24, count 2 2006.201.15:01:50.71#ibcon#*before return 0, iclass 24, count 2 2006.201.15:01:50.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:50.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:50.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.15:01:50.71#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:50.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:50.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:50.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:50.83#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:01:50.83#ibcon#first serial, iclass 24, count 0 2006.201.15:01:50.83#ibcon#enter sib2, iclass 24, count 0 2006.201.15:01:50.83#ibcon#flushed, iclass 24, count 0 2006.201.15:01:50.83#ibcon#about to write, iclass 24, count 0 2006.201.15:01:50.83#ibcon#wrote, iclass 24, count 0 2006.201.15:01:50.83#ibcon#about to read 3, iclass 24, count 0 2006.201.15:01:50.85#ibcon#read 3, iclass 24, count 0 2006.201.15:01:50.85#ibcon#about to read 4, iclass 24, count 0 2006.201.15:01:50.85#ibcon#read 4, iclass 24, count 0 2006.201.15:01:50.85#ibcon#about to read 5, iclass 24, count 0 2006.201.15:01:50.85#ibcon#read 5, iclass 24, count 0 2006.201.15:01:50.85#ibcon#about to read 6, iclass 24, count 0 2006.201.15:01:50.85#ibcon#read 6, iclass 24, count 0 2006.201.15:01:50.85#ibcon#end of sib2, iclass 24, count 0 2006.201.15:01:50.85#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:01:50.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:01:50.85#ibcon#[25=USB\r\n] 2006.201.15:01:50.85#ibcon#*before write, iclass 24, count 0 2006.201.15:01:50.85#ibcon#enter sib2, iclass 24, count 0 2006.201.15:01:50.85#ibcon#flushed, iclass 24, count 0 2006.201.15:01:50.85#ibcon#about to write, iclass 24, count 0 2006.201.15:01:50.85#ibcon#wrote, iclass 24, count 0 2006.201.15:01:50.85#ibcon#about to read 3, iclass 24, count 0 2006.201.15:01:50.88#ibcon#read 3, iclass 24, count 0 2006.201.15:01:50.88#ibcon#about to read 4, iclass 24, count 0 2006.201.15:01:50.88#ibcon#read 4, iclass 24, count 0 2006.201.15:01:50.88#ibcon#about to read 5, iclass 24, count 0 2006.201.15:01:50.88#ibcon#read 5, iclass 24, count 0 2006.201.15:01:50.88#ibcon#about to read 6, iclass 24, count 0 2006.201.15:01:50.88#ibcon#read 6, iclass 24, count 0 2006.201.15:01:50.88#ibcon#end of sib2, iclass 24, count 0 2006.201.15:01:50.88#ibcon#*after write, iclass 24, count 0 2006.201.15:01:50.88#ibcon#*before return 0, iclass 24, count 0 2006.201.15:01:50.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:50.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:50.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:01:50.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:01:50.88$vck44/valo=7,864.99 2006.201.15:01:50.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.15:01:50.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.15:01:50.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:50.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:50.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:50.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:50.88#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:01:50.88#ibcon#first serial, iclass 26, count 0 2006.201.15:01:50.88#ibcon#enter sib2, iclass 26, count 0 2006.201.15:01:50.88#ibcon#flushed, iclass 26, count 0 2006.201.15:01:50.88#ibcon#about to write, iclass 26, count 0 2006.201.15:01:50.88#ibcon#wrote, iclass 26, count 0 2006.201.15:01:50.88#ibcon#about to read 3, iclass 26, count 0 2006.201.15:01:50.90#ibcon#read 3, iclass 26, count 0 2006.201.15:01:50.90#ibcon#about to read 4, iclass 26, count 0 2006.201.15:01:50.90#ibcon#read 4, iclass 26, count 0 2006.201.15:01:50.90#ibcon#about to read 5, iclass 26, count 0 2006.201.15:01:50.90#ibcon#read 5, iclass 26, count 0 2006.201.15:01:50.90#ibcon#about to read 6, iclass 26, count 0 2006.201.15:01:50.90#ibcon#read 6, iclass 26, count 0 2006.201.15:01:50.90#ibcon#end of sib2, iclass 26, count 0 2006.201.15:01:50.90#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:01:50.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:01:50.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:01:50.90#ibcon#*before write, iclass 26, count 0 2006.201.15:01:50.90#ibcon#enter sib2, iclass 26, count 0 2006.201.15:01:50.90#ibcon#flushed, iclass 26, count 0 2006.201.15:01:50.90#ibcon#about to write, iclass 26, count 0 2006.201.15:01:50.90#ibcon#wrote, iclass 26, count 0 2006.201.15:01:50.90#ibcon#about to read 3, iclass 26, count 0 2006.201.15:01:50.94#ibcon#read 3, iclass 26, count 0 2006.201.15:01:50.94#ibcon#about to read 4, iclass 26, count 0 2006.201.15:01:50.94#ibcon#read 4, iclass 26, count 0 2006.201.15:01:50.94#ibcon#about to read 5, iclass 26, count 0 2006.201.15:01:50.94#ibcon#read 5, iclass 26, count 0 2006.201.15:01:50.94#ibcon#about to read 6, iclass 26, count 0 2006.201.15:01:50.94#ibcon#read 6, iclass 26, count 0 2006.201.15:01:50.94#ibcon#end of sib2, iclass 26, count 0 2006.201.15:01:50.94#ibcon#*after write, iclass 26, count 0 2006.201.15:01:50.94#ibcon#*before return 0, iclass 26, count 0 2006.201.15:01:50.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:50.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:50.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:01:50.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:01:50.94$vck44/va=7,5 2006.201.15:01:50.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.15:01:50.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.15:01:50.94#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:50.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:01:51.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:01:51.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:01:51.00#ibcon#enter wrdev, iclass 28, count 2 2006.201.15:01:51.00#ibcon#first serial, iclass 28, count 2 2006.201.15:01:51.00#ibcon#enter sib2, iclass 28, count 2 2006.201.15:01:51.00#ibcon#flushed, iclass 28, count 2 2006.201.15:01:51.00#ibcon#about to write, iclass 28, count 2 2006.201.15:01:51.00#ibcon#wrote, iclass 28, count 2 2006.201.15:01:51.00#ibcon#about to read 3, iclass 28, count 2 2006.201.15:01:51.02#ibcon#read 3, iclass 28, count 2 2006.201.15:01:51.02#ibcon#about to read 4, iclass 28, count 2 2006.201.15:01:51.02#ibcon#read 4, iclass 28, count 2 2006.201.15:01:51.02#ibcon#about to read 5, iclass 28, count 2 2006.201.15:01:51.02#ibcon#read 5, iclass 28, count 2 2006.201.15:01:51.02#ibcon#about to read 6, iclass 28, count 2 2006.201.15:01:51.02#ibcon#read 6, iclass 28, count 2 2006.201.15:01:51.02#ibcon#end of sib2, iclass 28, count 2 2006.201.15:01:51.02#ibcon#*mode == 0, iclass 28, count 2 2006.201.15:01:51.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.15:01:51.02#ibcon#[25=AT07-05\r\n] 2006.201.15:01:51.02#ibcon#*before write, iclass 28, count 2 2006.201.15:01:51.02#ibcon#enter sib2, iclass 28, count 2 2006.201.15:01:51.02#ibcon#flushed, iclass 28, count 2 2006.201.15:01:51.02#ibcon#about to write, iclass 28, count 2 2006.201.15:01:51.02#ibcon#wrote, iclass 28, count 2 2006.201.15:01:51.02#ibcon#about to read 3, iclass 28, count 2 2006.201.15:01:51.05#ibcon#read 3, iclass 28, count 2 2006.201.15:01:51.05#ibcon#about to read 4, iclass 28, count 2 2006.201.15:01:51.05#ibcon#read 4, iclass 28, count 2 2006.201.15:01:51.05#ibcon#about to read 5, iclass 28, count 2 2006.201.15:01:51.05#ibcon#read 5, iclass 28, count 2 2006.201.15:01:51.05#ibcon#about to read 6, iclass 28, count 2 2006.201.15:01:51.05#ibcon#read 6, iclass 28, count 2 2006.201.15:01:51.05#ibcon#end of sib2, iclass 28, count 2 2006.201.15:01:51.05#ibcon#*after write, iclass 28, count 2 2006.201.15:01:51.05#ibcon#*before return 0, iclass 28, count 2 2006.201.15:01:51.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:01:51.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:01:51.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.15:01:51.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:51.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:01:51.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:01:51.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:01:51.17#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:01:51.17#ibcon#first serial, iclass 28, count 0 2006.201.15:01:51.17#ibcon#enter sib2, iclass 28, count 0 2006.201.15:01:51.17#ibcon#flushed, iclass 28, count 0 2006.201.15:01:51.17#ibcon#about to write, iclass 28, count 0 2006.201.15:01:51.17#ibcon#wrote, iclass 28, count 0 2006.201.15:01:51.17#ibcon#about to read 3, iclass 28, count 0 2006.201.15:01:51.19#ibcon#read 3, iclass 28, count 0 2006.201.15:01:51.19#ibcon#about to read 4, iclass 28, count 0 2006.201.15:01:51.19#ibcon#read 4, iclass 28, count 0 2006.201.15:01:51.19#ibcon#about to read 5, iclass 28, count 0 2006.201.15:01:51.19#ibcon#read 5, iclass 28, count 0 2006.201.15:01:51.19#ibcon#about to read 6, iclass 28, count 0 2006.201.15:01:51.19#ibcon#read 6, iclass 28, count 0 2006.201.15:01:51.19#ibcon#end of sib2, iclass 28, count 0 2006.201.15:01:51.19#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:01:51.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:01:51.19#ibcon#[25=USB\r\n] 2006.201.15:01:51.19#ibcon#*before write, iclass 28, count 0 2006.201.15:01:51.19#ibcon#enter sib2, iclass 28, count 0 2006.201.15:01:51.19#ibcon#flushed, iclass 28, count 0 2006.201.15:01:51.19#ibcon#about to write, iclass 28, count 0 2006.201.15:01:51.19#ibcon#wrote, iclass 28, count 0 2006.201.15:01:51.19#ibcon#about to read 3, iclass 28, count 0 2006.201.15:01:51.22#ibcon#read 3, iclass 28, count 0 2006.201.15:01:51.22#ibcon#about to read 4, iclass 28, count 0 2006.201.15:01:51.22#ibcon#read 4, iclass 28, count 0 2006.201.15:01:51.22#ibcon#about to read 5, iclass 28, count 0 2006.201.15:01:51.22#ibcon#read 5, iclass 28, count 0 2006.201.15:01:51.22#ibcon#about to read 6, iclass 28, count 0 2006.201.15:01:51.22#ibcon#read 6, iclass 28, count 0 2006.201.15:01:51.22#ibcon#end of sib2, iclass 28, count 0 2006.201.15:01:51.22#ibcon#*after write, iclass 28, count 0 2006.201.15:01:51.22#ibcon#*before return 0, iclass 28, count 0 2006.201.15:01:51.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:01:51.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:01:51.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:01:51.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:01:51.22$vck44/valo=8,884.99 2006.201.15:01:51.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.15:01:51.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.15:01:51.22#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:51.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:01:51.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:01:51.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:01:51.22#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:01:51.22#ibcon#first serial, iclass 30, count 0 2006.201.15:01:51.22#ibcon#enter sib2, iclass 30, count 0 2006.201.15:01:51.22#ibcon#flushed, iclass 30, count 0 2006.201.15:01:51.22#ibcon#about to write, iclass 30, count 0 2006.201.15:01:51.22#ibcon#wrote, iclass 30, count 0 2006.201.15:01:51.22#ibcon#about to read 3, iclass 30, count 0 2006.201.15:01:51.24#ibcon#read 3, iclass 30, count 0 2006.201.15:01:51.24#ibcon#about to read 4, iclass 30, count 0 2006.201.15:01:51.24#ibcon#read 4, iclass 30, count 0 2006.201.15:01:51.24#ibcon#about to read 5, iclass 30, count 0 2006.201.15:01:51.24#ibcon#read 5, iclass 30, count 0 2006.201.15:01:51.24#ibcon#about to read 6, iclass 30, count 0 2006.201.15:01:51.24#ibcon#read 6, iclass 30, count 0 2006.201.15:01:51.24#ibcon#end of sib2, iclass 30, count 0 2006.201.15:01:51.24#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:01:51.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:01:51.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:01:51.24#ibcon#*before write, iclass 30, count 0 2006.201.15:01:51.24#ibcon#enter sib2, iclass 30, count 0 2006.201.15:01:51.24#ibcon#flushed, iclass 30, count 0 2006.201.15:01:51.24#ibcon#about to write, iclass 30, count 0 2006.201.15:01:51.24#ibcon#wrote, iclass 30, count 0 2006.201.15:01:51.24#ibcon#about to read 3, iclass 30, count 0 2006.201.15:01:51.28#ibcon#read 3, iclass 30, count 0 2006.201.15:01:51.28#ibcon#about to read 4, iclass 30, count 0 2006.201.15:01:51.28#ibcon#read 4, iclass 30, count 0 2006.201.15:01:51.28#ibcon#about to read 5, iclass 30, count 0 2006.201.15:01:51.28#ibcon#read 5, iclass 30, count 0 2006.201.15:01:51.28#ibcon#about to read 6, iclass 30, count 0 2006.201.15:01:51.28#ibcon#read 6, iclass 30, count 0 2006.201.15:01:51.28#ibcon#end of sib2, iclass 30, count 0 2006.201.15:01:51.28#ibcon#*after write, iclass 30, count 0 2006.201.15:01:51.28#ibcon#*before return 0, iclass 30, count 0 2006.201.15:01:51.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:01:51.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:01:51.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:01:51.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:01:51.28$vck44/va=8,4 2006.201.15:01:51.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.15:01:51.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.15:01:51.28#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:51.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:01:51.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:01:51.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:01:51.34#ibcon#enter wrdev, iclass 32, count 2 2006.201.15:01:51.34#ibcon#first serial, iclass 32, count 2 2006.201.15:01:51.34#ibcon#enter sib2, iclass 32, count 2 2006.201.15:01:51.34#ibcon#flushed, iclass 32, count 2 2006.201.15:01:51.34#ibcon#about to write, iclass 32, count 2 2006.201.15:01:51.34#ibcon#wrote, iclass 32, count 2 2006.201.15:01:51.34#ibcon#about to read 3, iclass 32, count 2 2006.201.15:01:51.36#ibcon#read 3, iclass 32, count 2 2006.201.15:01:51.36#ibcon#about to read 4, iclass 32, count 2 2006.201.15:01:51.36#ibcon#read 4, iclass 32, count 2 2006.201.15:01:51.36#ibcon#about to read 5, iclass 32, count 2 2006.201.15:01:51.36#ibcon#read 5, iclass 32, count 2 2006.201.15:01:51.36#ibcon#about to read 6, iclass 32, count 2 2006.201.15:01:51.36#ibcon#read 6, iclass 32, count 2 2006.201.15:01:51.36#ibcon#end of sib2, iclass 32, count 2 2006.201.15:01:51.36#ibcon#*mode == 0, iclass 32, count 2 2006.201.15:01:51.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.15:01:51.36#ibcon#[25=AT08-04\r\n] 2006.201.15:01:51.36#ibcon#*before write, iclass 32, count 2 2006.201.15:01:51.36#ibcon#enter sib2, iclass 32, count 2 2006.201.15:01:51.36#ibcon#flushed, iclass 32, count 2 2006.201.15:01:51.36#ibcon#about to write, iclass 32, count 2 2006.201.15:01:51.36#ibcon#wrote, iclass 32, count 2 2006.201.15:01:51.36#ibcon#about to read 3, iclass 32, count 2 2006.201.15:01:51.39#ibcon#read 3, iclass 32, count 2 2006.201.15:01:51.39#ibcon#about to read 4, iclass 32, count 2 2006.201.15:01:51.39#ibcon#read 4, iclass 32, count 2 2006.201.15:01:51.39#ibcon#about to read 5, iclass 32, count 2 2006.201.15:01:51.39#ibcon#read 5, iclass 32, count 2 2006.201.15:01:51.39#ibcon#about to read 6, iclass 32, count 2 2006.201.15:01:51.39#ibcon#read 6, iclass 32, count 2 2006.201.15:01:51.39#ibcon#end of sib2, iclass 32, count 2 2006.201.15:01:51.39#ibcon#*after write, iclass 32, count 2 2006.201.15:01:51.39#ibcon#*before return 0, iclass 32, count 2 2006.201.15:01:51.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:01:51.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:01:51.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.15:01:51.39#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:51.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:01:51.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:01:51.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:01:51.51#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:01:51.51#ibcon#first serial, iclass 32, count 0 2006.201.15:01:51.51#ibcon#enter sib2, iclass 32, count 0 2006.201.15:01:51.51#ibcon#flushed, iclass 32, count 0 2006.201.15:01:51.51#ibcon#about to write, iclass 32, count 0 2006.201.15:01:51.51#ibcon#wrote, iclass 32, count 0 2006.201.15:01:51.51#ibcon#about to read 3, iclass 32, count 0 2006.201.15:01:51.53#ibcon#read 3, iclass 32, count 0 2006.201.15:01:51.53#ibcon#about to read 4, iclass 32, count 0 2006.201.15:01:51.53#ibcon#read 4, iclass 32, count 0 2006.201.15:01:51.53#ibcon#about to read 5, iclass 32, count 0 2006.201.15:01:51.53#ibcon#read 5, iclass 32, count 0 2006.201.15:01:51.53#ibcon#about to read 6, iclass 32, count 0 2006.201.15:01:51.53#ibcon#read 6, iclass 32, count 0 2006.201.15:01:51.53#ibcon#end of sib2, iclass 32, count 0 2006.201.15:01:51.53#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:01:51.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:01:51.53#ibcon#[25=USB\r\n] 2006.201.15:01:51.53#ibcon#*before write, iclass 32, count 0 2006.201.15:01:51.53#ibcon#enter sib2, iclass 32, count 0 2006.201.15:01:51.53#ibcon#flushed, iclass 32, count 0 2006.201.15:01:51.53#ibcon#about to write, iclass 32, count 0 2006.201.15:01:51.53#ibcon#wrote, iclass 32, count 0 2006.201.15:01:51.53#ibcon#about to read 3, iclass 32, count 0 2006.201.15:01:51.56#ibcon#read 3, iclass 32, count 0 2006.201.15:01:51.56#ibcon#about to read 4, iclass 32, count 0 2006.201.15:01:51.56#ibcon#read 4, iclass 32, count 0 2006.201.15:01:51.56#ibcon#about to read 5, iclass 32, count 0 2006.201.15:01:51.56#ibcon#read 5, iclass 32, count 0 2006.201.15:01:51.56#ibcon#about to read 6, iclass 32, count 0 2006.201.15:01:51.56#ibcon#read 6, iclass 32, count 0 2006.201.15:01:51.56#ibcon#end of sib2, iclass 32, count 0 2006.201.15:01:51.56#ibcon#*after write, iclass 32, count 0 2006.201.15:01:51.56#ibcon#*before return 0, iclass 32, count 0 2006.201.15:01:51.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:01:51.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:01:51.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:01:51.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:01:51.56$vck44/vblo=1,629.99 2006.201.15:01:51.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.15:01:51.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.15:01:51.56#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:51.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:51.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:51.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:51.56#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:01:51.56#ibcon#first serial, iclass 34, count 0 2006.201.15:01:51.56#ibcon#enter sib2, iclass 34, count 0 2006.201.15:01:51.56#ibcon#flushed, iclass 34, count 0 2006.201.15:01:51.56#ibcon#about to write, iclass 34, count 0 2006.201.15:01:51.56#ibcon#wrote, iclass 34, count 0 2006.201.15:01:51.56#ibcon#about to read 3, iclass 34, count 0 2006.201.15:01:51.58#ibcon#read 3, iclass 34, count 0 2006.201.15:01:51.58#ibcon#about to read 4, iclass 34, count 0 2006.201.15:01:51.58#ibcon#read 4, iclass 34, count 0 2006.201.15:01:51.58#ibcon#about to read 5, iclass 34, count 0 2006.201.15:01:51.58#ibcon#read 5, iclass 34, count 0 2006.201.15:01:51.58#ibcon#about to read 6, iclass 34, count 0 2006.201.15:01:51.58#ibcon#read 6, iclass 34, count 0 2006.201.15:01:51.58#ibcon#end of sib2, iclass 34, count 0 2006.201.15:01:51.58#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:01:51.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:01:51.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:01:51.58#ibcon#*before write, iclass 34, count 0 2006.201.15:01:51.58#ibcon#enter sib2, iclass 34, count 0 2006.201.15:01:51.58#ibcon#flushed, iclass 34, count 0 2006.201.15:01:51.58#ibcon#about to write, iclass 34, count 0 2006.201.15:01:51.58#ibcon#wrote, iclass 34, count 0 2006.201.15:01:51.58#ibcon#about to read 3, iclass 34, count 0 2006.201.15:01:51.62#ibcon#read 3, iclass 34, count 0 2006.201.15:01:51.62#ibcon#about to read 4, iclass 34, count 0 2006.201.15:01:51.62#ibcon#read 4, iclass 34, count 0 2006.201.15:01:51.62#ibcon#about to read 5, iclass 34, count 0 2006.201.15:01:51.62#ibcon#read 5, iclass 34, count 0 2006.201.15:01:51.62#ibcon#about to read 6, iclass 34, count 0 2006.201.15:01:51.62#ibcon#read 6, iclass 34, count 0 2006.201.15:01:51.62#ibcon#end of sib2, iclass 34, count 0 2006.201.15:01:51.62#ibcon#*after write, iclass 34, count 0 2006.201.15:01:51.62#ibcon#*before return 0, iclass 34, count 0 2006.201.15:01:51.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:51.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:51.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:01:51.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:01:51.62$vck44/vb=1,4 2006.201.15:01:51.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.15:01:51.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.15:01:51.62#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:51.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:01:51.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:01:51.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:01:51.62#ibcon#enter wrdev, iclass 36, count 2 2006.201.15:01:51.62#ibcon#first serial, iclass 36, count 2 2006.201.15:01:51.62#ibcon#enter sib2, iclass 36, count 2 2006.201.15:01:51.62#ibcon#flushed, iclass 36, count 2 2006.201.15:01:51.62#ibcon#about to write, iclass 36, count 2 2006.201.15:01:51.62#ibcon#wrote, iclass 36, count 2 2006.201.15:01:51.62#ibcon#about to read 3, iclass 36, count 2 2006.201.15:01:51.64#ibcon#read 3, iclass 36, count 2 2006.201.15:01:51.64#ibcon#about to read 4, iclass 36, count 2 2006.201.15:01:51.64#ibcon#read 4, iclass 36, count 2 2006.201.15:01:51.64#ibcon#about to read 5, iclass 36, count 2 2006.201.15:01:51.64#ibcon#read 5, iclass 36, count 2 2006.201.15:01:51.64#ibcon#about to read 6, iclass 36, count 2 2006.201.15:01:51.64#ibcon#read 6, iclass 36, count 2 2006.201.15:01:51.64#ibcon#end of sib2, iclass 36, count 2 2006.201.15:01:51.64#ibcon#*mode == 0, iclass 36, count 2 2006.201.15:01:51.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.15:01:51.64#ibcon#[27=AT01-04\r\n] 2006.201.15:01:51.64#ibcon#*before write, iclass 36, count 2 2006.201.15:01:51.64#ibcon#enter sib2, iclass 36, count 2 2006.201.15:01:51.64#ibcon#flushed, iclass 36, count 2 2006.201.15:01:51.64#ibcon#about to write, iclass 36, count 2 2006.201.15:01:51.64#ibcon#wrote, iclass 36, count 2 2006.201.15:01:51.64#ibcon#about to read 3, iclass 36, count 2 2006.201.15:01:51.67#ibcon#read 3, iclass 36, count 2 2006.201.15:01:51.67#ibcon#about to read 4, iclass 36, count 2 2006.201.15:01:51.67#ibcon#read 4, iclass 36, count 2 2006.201.15:01:51.67#ibcon#about to read 5, iclass 36, count 2 2006.201.15:01:51.67#ibcon#read 5, iclass 36, count 2 2006.201.15:01:51.67#ibcon#about to read 6, iclass 36, count 2 2006.201.15:01:51.67#ibcon#read 6, iclass 36, count 2 2006.201.15:01:51.67#ibcon#end of sib2, iclass 36, count 2 2006.201.15:01:51.67#ibcon#*after write, iclass 36, count 2 2006.201.15:01:51.67#ibcon#*before return 0, iclass 36, count 2 2006.201.15:01:51.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:01:51.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:01:51.67#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.15:01:51.67#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:51.67#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:01:51.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:01:51.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:01:51.79#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:01:51.79#ibcon#first serial, iclass 36, count 0 2006.201.15:01:51.79#ibcon#enter sib2, iclass 36, count 0 2006.201.15:01:51.79#ibcon#flushed, iclass 36, count 0 2006.201.15:01:51.79#ibcon#about to write, iclass 36, count 0 2006.201.15:01:51.79#ibcon#wrote, iclass 36, count 0 2006.201.15:01:51.79#ibcon#about to read 3, iclass 36, count 0 2006.201.15:01:51.81#ibcon#read 3, iclass 36, count 0 2006.201.15:01:51.81#ibcon#about to read 4, iclass 36, count 0 2006.201.15:01:51.81#ibcon#read 4, iclass 36, count 0 2006.201.15:01:51.81#ibcon#about to read 5, iclass 36, count 0 2006.201.15:01:51.81#ibcon#read 5, iclass 36, count 0 2006.201.15:01:51.81#ibcon#about to read 6, iclass 36, count 0 2006.201.15:01:51.81#ibcon#read 6, iclass 36, count 0 2006.201.15:01:51.81#ibcon#end of sib2, iclass 36, count 0 2006.201.15:01:51.81#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:01:51.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:01:51.81#ibcon#[27=USB\r\n] 2006.201.15:01:51.81#ibcon#*before write, iclass 36, count 0 2006.201.15:01:51.81#ibcon#enter sib2, iclass 36, count 0 2006.201.15:01:51.81#ibcon#flushed, iclass 36, count 0 2006.201.15:01:51.81#ibcon#about to write, iclass 36, count 0 2006.201.15:01:51.81#ibcon#wrote, iclass 36, count 0 2006.201.15:01:51.81#ibcon#about to read 3, iclass 36, count 0 2006.201.15:01:51.84#ibcon#read 3, iclass 36, count 0 2006.201.15:01:51.84#ibcon#about to read 4, iclass 36, count 0 2006.201.15:01:51.84#ibcon#read 4, iclass 36, count 0 2006.201.15:01:51.84#ibcon#about to read 5, iclass 36, count 0 2006.201.15:01:51.84#ibcon#read 5, iclass 36, count 0 2006.201.15:01:51.84#ibcon#about to read 6, iclass 36, count 0 2006.201.15:01:51.84#ibcon#read 6, iclass 36, count 0 2006.201.15:01:51.84#ibcon#end of sib2, iclass 36, count 0 2006.201.15:01:51.84#ibcon#*after write, iclass 36, count 0 2006.201.15:01:51.84#ibcon#*before return 0, iclass 36, count 0 2006.201.15:01:51.84#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:01:51.84#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:01:51.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:01:51.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:01:51.84$vck44/vblo=2,634.99 2006.201.15:01:51.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.15:01:51.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.15:01:51.84#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:51.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:51.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:51.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:51.84#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:01:51.84#ibcon#first serial, iclass 38, count 0 2006.201.15:01:51.84#ibcon#enter sib2, iclass 38, count 0 2006.201.15:01:51.84#ibcon#flushed, iclass 38, count 0 2006.201.15:01:51.84#ibcon#about to write, iclass 38, count 0 2006.201.15:01:51.84#ibcon#wrote, iclass 38, count 0 2006.201.15:01:51.84#ibcon#about to read 3, iclass 38, count 0 2006.201.15:01:51.86#ibcon#read 3, iclass 38, count 0 2006.201.15:01:51.86#ibcon#about to read 4, iclass 38, count 0 2006.201.15:01:51.86#ibcon#read 4, iclass 38, count 0 2006.201.15:01:51.86#ibcon#about to read 5, iclass 38, count 0 2006.201.15:01:51.86#ibcon#read 5, iclass 38, count 0 2006.201.15:01:51.86#ibcon#about to read 6, iclass 38, count 0 2006.201.15:01:51.86#ibcon#read 6, iclass 38, count 0 2006.201.15:01:51.86#ibcon#end of sib2, iclass 38, count 0 2006.201.15:01:51.86#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:01:51.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:01:51.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:01:51.86#ibcon#*before write, iclass 38, count 0 2006.201.15:01:51.86#ibcon#enter sib2, iclass 38, count 0 2006.201.15:01:51.86#ibcon#flushed, iclass 38, count 0 2006.201.15:01:51.86#ibcon#about to write, iclass 38, count 0 2006.201.15:01:51.86#ibcon#wrote, iclass 38, count 0 2006.201.15:01:51.86#ibcon#about to read 3, iclass 38, count 0 2006.201.15:01:51.90#ibcon#read 3, iclass 38, count 0 2006.201.15:01:51.90#ibcon#about to read 4, iclass 38, count 0 2006.201.15:01:51.90#ibcon#read 4, iclass 38, count 0 2006.201.15:01:51.90#ibcon#about to read 5, iclass 38, count 0 2006.201.15:01:51.90#ibcon#read 5, iclass 38, count 0 2006.201.15:01:51.90#ibcon#about to read 6, iclass 38, count 0 2006.201.15:01:51.90#ibcon#read 6, iclass 38, count 0 2006.201.15:01:51.90#ibcon#end of sib2, iclass 38, count 0 2006.201.15:01:51.90#ibcon#*after write, iclass 38, count 0 2006.201.15:01:51.90#ibcon#*before return 0, iclass 38, count 0 2006.201.15:01:51.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:51.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:01:51.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:01:51.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:01:51.90$vck44/vb=2,5 2006.201.15:01:51.90#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.15:01:51.90#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.15:01:51.90#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:51.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:51.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:51.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:51.96#ibcon#enter wrdev, iclass 40, count 2 2006.201.15:01:51.96#ibcon#first serial, iclass 40, count 2 2006.201.15:01:51.96#ibcon#enter sib2, iclass 40, count 2 2006.201.15:01:51.96#ibcon#flushed, iclass 40, count 2 2006.201.15:01:51.96#ibcon#about to write, iclass 40, count 2 2006.201.15:01:51.96#ibcon#wrote, iclass 40, count 2 2006.201.15:01:51.96#ibcon#about to read 3, iclass 40, count 2 2006.201.15:01:51.98#ibcon#read 3, iclass 40, count 2 2006.201.15:01:51.98#ibcon#about to read 4, iclass 40, count 2 2006.201.15:01:51.98#ibcon#read 4, iclass 40, count 2 2006.201.15:01:51.98#ibcon#about to read 5, iclass 40, count 2 2006.201.15:01:51.98#ibcon#read 5, iclass 40, count 2 2006.201.15:01:51.98#ibcon#about to read 6, iclass 40, count 2 2006.201.15:01:51.98#ibcon#read 6, iclass 40, count 2 2006.201.15:01:51.98#ibcon#end of sib2, iclass 40, count 2 2006.201.15:01:51.98#ibcon#*mode == 0, iclass 40, count 2 2006.201.15:01:51.98#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.15:01:51.98#ibcon#[27=AT02-05\r\n] 2006.201.15:01:51.98#ibcon#*before write, iclass 40, count 2 2006.201.15:01:51.98#ibcon#enter sib2, iclass 40, count 2 2006.201.15:01:51.98#ibcon#flushed, iclass 40, count 2 2006.201.15:01:51.98#ibcon#about to write, iclass 40, count 2 2006.201.15:01:51.98#ibcon#wrote, iclass 40, count 2 2006.201.15:01:51.98#ibcon#about to read 3, iclass 40, count 2 2006.201.15:01:52.01#ibcon#read 3, iclass 40, count 2 2006.201.15:01:52.01#ibcon#about to read 4, iclass 40, count 2 2006.201.15:01:52.01#ibcon#read 4, iclass 40, count 2 2006.201.15:01:52.01#ibcon#about to read 5, iclass 40, count 2 2006.201.15:01:52.01#ibcon#read 5, iclass 40, count 2 2006.201.15:01:52.01#ibcon#about to read 6, iclass 40, count 2 2006.201.15:01:52.01#ibcon#read 6, iclass 40, count 2 2006.201.15:01:52.01#ibcon#end of sib2, iclass 40, count 2 2006.201.15:01:52.01#ibcon#*after write, iclass 40, count 2 2006.201.15:01:52.01#ibcon#*before return 0, iclass 40, count 2 2006.201.15:01:52.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:52.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:01:52.01#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.15:01:52.01#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:52.01#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:52.13#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:52.13#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:52.13#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:01:52.13#ibcon#first serial, iclass 40, count 0 2006.201.15:01:52.13#ibcon#enter sib2, iclass 40, count 0 2006.201.15:01:52.13#ibcon#flushed, iclass 40, count 0 2006.201.15:01:52.13#ibcon#about to write, iclass 40, count 0 2006.201.15:01:52.13#ibcon#wrote, iclass 40, count 0 2006.201.15:01:52.13#ibcon#about to read 3, iclass 40, count 0 2006.201.15:01:52.15#ibcon#read 3, iclass 40, count 0 2006.201.15:01:52.15#ibcon#about to read 4, iclass 40, count 0 2006.201.15:01:52.15#ibcon#read 4, iclass 40, count 0 2006.201.15:01:52.15#ibcon#about to read 5, iclass 40, count 0 2006.201.15:01:52.15#ibcon#read 5, iclass 40, count 0 2006.201.15:01:52.15#ibcon#about to read 6, iclass 40, count 0 2006.201.15:01:52.15#ibcon#read 6, iclass 40, count 0 2006.201.15:01:52.15#ibcon#end of sib2, iclass 40, count 0 2006.201.15:01:52.15#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:01:52.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:01:52.15#ibcon#[27=USB\r\n] 2006.201.15:01:52.15#ibcon#*before write, iclass 40, count 0 2006.201.15:01:52.15#ibcon#enter sib2, iclass 40, count 0 2006.201.15:01:52.15#ibcon#flushed, iclass 40, count 0 2006.201.15:01:52.15#ibcon#about to write, iclass 40, count 0 2006.201.15:01:52.15#ibcon#wrote, iclass 40, count 0 2006.201.15:01:52.15#ibcon#about to read 3, iclass 40, count 0 2006.201.15:01:52.18#ibcon#read 3, iclass 40, count 0 2006.201.15:01:52.18#ibcon#about to read 4, iclass 40, count 0 2006.201.15:01:52.18#ibcon#read 4, iclass 40, count 0 2006.201.15:01:52.18#ibcon#about to read 5, iclass 40, count 0 2006.201.15:01:52.18#ibcon#read 5, iclass 40, count 0 2006.201.15:01:52.18#ibcon#about to read 6, iclass 40, count 0 2006.201.15:01:52.18#ibcon#read 6, iclass 40, count 0 2006.201.15:01:52.18#ibcon#end of sib2, iclass 40, count 0 2006.201.15:01:52.18#ibcon#*after write, iclass 40, count 0 2006.201.15:01:52.18#ibcon#*before return 0, iclass 40, count 0 2006.201.15:01:52.18#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:52.18#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:01:52.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:01:52.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:01:52.18$vck44/vblo=3,649.99 2006.201.15:01:52.18#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.15:01:52.18#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.15:01:52.18#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:52.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:52.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:52.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:52.18#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:01:52.18#ibcon#first serial, iclass 4, count 0 2006.201.15:01:52.18#ibcon#enter sib2, iclass 4, count 0 2006.201.15:01:52.18#ibcon#flushed, iclass 4, count 0 2006.201.15:01:52.18#ibcon#about to write, iclass 4, count 0 2006.201.15:01:52.18#ibcon#wrote, iclass 4, count 0 2006.201.15:01:52.18#ibcon#about to read 3, iclass 4, count 0 2006.201.15:01:52.20#ibcon#read 3, iclass 4, count 0 2006.201.15:01:52.20#ibcon#about to read 4, iclass 4, count 0 2006.201.15:01:52.20#ibcon#read 4, iclass 4, count 0 2006.201.15:01:52.20#ibcon#about to read 5, iclass 4, count 0 2006.201.15:01:52.20#ibcon#read 5, iclass 4, count 0 2006.201.15:01:52.20#ibcon#about to read 6, iclass 4, count 0 2006.201.15:01:52.20#ibcon#read 6, iclass 4, count 0 2006.201.15:01:52.20#ibcon#end of sib2, iclass 4, count 0 2006.201.15:01:52.20#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:01:52.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:01:52.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:01:52.20#ibcon#*before write, iclass 4, count 0 2006.201.15:01:52.20#ibcon#enter sib2, iclass 4, count 0 2006.201.15:01:52.20#ibcon#flushed, iclass 4, count 0 2006.201.15:01:52.20#ibcon#about to write, iclass 4, count 0 2006.201.15:01:52.20#ibcon#wrote, iclass 4, count 0 2006.201.15:01:52.20#ibcon#about to read 3, iclass 4, count 0 2006.201.15:01:52.25#ibcon#read 3, iclass 4, count 0 2006.201.15:01:52.25#ibcon#about to read 4, iclass 4, count 0 2006.201.15:01:52.25#ibcon#read 4, iclass 4, count 0 2006.201.15:01:52.25#ibcon#about to read 5, iclass 4, count 0 2006.201.15:01:52.25#ibcon#read 5, iclass 4, count 0 2006.201.15:01:52.25#ibcon#about to read 6, iclass 4, count 0 2006.201.15:01:52.25#ibcon#read 6, iclass 4, count 0 2006.201.15:01:52.25#ibcon#end of sib2, iclass 4, count 0 2006.201.15:01:52.25#ibcon#*after write, iclass 4, count 0 2006.201.15:01:52.25#ibcon#*before return 0, iclass 4, count 0 2006.201.15:01:52.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:52.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:01:52.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:01:52.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:01:52.25$vck44/vb=3,4 2006.201.15:01:52.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.15:01:52.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.15:01:52.25#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:52.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:52.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:52.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:52.30#ibcon#enter wrdev, iclass 6, count 2 2006.201.15:01:52.30#ibcon#first serial, iclass 6, count 2 2006.201.15:01:52.30#ibcon#enter sib2, iclass 6, count 2 2006.201.15:01:52.30#ibcon#flushed, iclass 6, count 2 2006.201.15:01:52.30#ibcon#about to write, iclass 6, count 2 2006.201.15:01:52.30#ibcon#wrote, iclass 6, count 2 2006.201.15:01:52.30#ibcon#about to read 3, iclass 6, count 2 2006.201.15:01:52.32#ibcon#read 3, iclass 6, count 2 2006.201.15:01:52.32#ibcon#about to read 4, iclass 6, count 2 2006.201.15:01:52.32#ibcon#read 4, iclass 6, count 2 2006.201.15:01:52.32#ibcon#about to read 5, iclass 6, count 2 2006.201.15:01:52.32#ibcon#read 5, iclass 6, count 2 2006.201.15:01:52.32#ibcon#about to read 6, iclass 6, count 2 2006.201.15:01:52.32#ibcon#read 6, iclass 6, count 2 2006.201.15:01:52.32#ibcon#end of sib2, iclass 6, count 2 2006.201.15:01:52.32#ibcon#*mode == 0, iclass 6, count 2 2006.201.15:01:52.32#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.15:01:52.32#ibcon#[27=AT03-04\r\n] 2006.201.15:01:52.32#ibcon#*before write, iclass 6, count 2 2006.201.15:01:52.32#ibcon#enter sib2, iclass 6, count 2 2006.201.15:01:52.32#ibcon#flushed, iclass 6, count 2 2006.201.15:01:52.32#ibcon#about to write, iclass 6, count 2 2006.201.15:01:52.32#ibcon#wrote, iclass 6, count 2 2006.201.15:01:52.32#ibcon#about to read 3, iclass 6, count 2 2006.201.15:01:52.35#ibcon#read 3, iclass 6, count 2 2006.201.15:01:52.35#ibcon#about to read 4, iclass 6, count 2 2006.201.15:01:52.35#ibcon#read 4, iclass 6, count 2 2006.201.15:01:52.35#ibcon#about to read 5, iclass 6, count 2 2006.201.15:01:52.35#ibcon#read 5, iclass 6, count 2 2006.201.15:01:52.35#ibcon#about to read 6, iclass 6, count 2 2006.201.15:01:52.35#ibcon#read 6, iclass 6, count 2 2006.201.15:01:52.35#ibcon#end of sib2, iclass 6, count 2 2006.201.15:01:52.35#ibcon#*after write, iclass 6, count 2 2006.201.15:01:52.35#ibcon#*before return 0, iclass 6, count 2 2006.201.15:01:52.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:52.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:01:52.35#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.15:01:52.35#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:52.35#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:52.47#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:52.47#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:52.47#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:01:52.47#ibcon#first serial, iclass 6, count 0 2006.201.15:01:52.47#ibcon#enter sib2, iclass 6, count 0 2006.201.15:01:52.47#ibcon#flushed, iclass 6, count 0 2006.201.15:01:52.47#ibcon#about to write, iclass 6, count 0 2006.201.15:01:52.47#ibcon#wrote, iclass 6, count 0 2006.201.15:01:52.47#ibcon#about to read 3, iclass 6, count 0 2006.201.15:01:52.49#ibcon#read 3, iclass 6, count 0 2006.201.15:01:52.49#ibcon#about to read 4, iclass 6, count 0 2006.201.15:01:52.49#ibcon#read 4, iclass 6, count 0 2006.201.15:01:52.49#ibcon#about to read 5, iclass 6, count 0 2006.201.15:01:52.49#ibcon#read 5, iclass 6, count 0 2006.201.15:01:52.49#ibcon#about to read 6, iclass 6, count 0 2006.201.15:01:52.49#ibcon#read 6, iclass 6, count 0 2006.201.15:01:52.49#ibcon#end of sib2, iclass 6, count 0 2006.201.15:01:52.49#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:01:52.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:01:52.49#ibcon#[27=USB\r\n] 2006.201.15:01:52.49#ibcon#*before write, iclass 6, count 0 2006.201.15:01:52.49#ibcon#enter sib2, iclass 6, count 0 2006.201.15:01:52.49#ibcon#flushed, iclass 6, count 0 2006.201.15:01:52.49#ibcon#about to write, iclass 6, count 0 2006.201.15:01:52.49#ibcon#wrote, iclass 6, count 0 2006.201.15:01:52.49#ibcon#about to read 3, iclass 6, count 0 2006.201.15:01:52.52#ibcon#read 3, iclass 6, count 0 2006.201.15:01:52.52#ibcon#about to read 4, iclass 6, count 0 2006.201.15:01:52.52#ibcon#read 4, iclass 6, count 0 2006.201.15:01:52.52#ibcon#about to read 5, iclass 6, count 0 2006.201.15:01:52.52#ibcon#read 5, iclass 6, count 0 2006.201.15:01:52.52#ibcon#about to read 6, iclass 6, count 0 2006.201.15:01:52.52#ibcon#read 6, iclass 6, count 0 2006.201.15:01:52.52#ibcon#end of sib2, iclass 6, count 0 2006.201.15:01:52.52#ibcon#*after write, iclass 6, count 0 2006.201.15:01:52.52#ibcon#*before return 0, iclass 6, count 0 2006.201.15:01:52.52#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:52.52#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:01:52.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:01:52.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:01:52.52$vck44/vblo=4,679.99 2006.201.15:01:52.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.15:01:52.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.15:01:52.52#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:52.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:52.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:52.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:52.52#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:01:52.52#ibcon#first serial, iclass 10, count 0 2006.201.15:01:52.52#ibcon#enter sib2, iclass 10, count 0 2006.201.15:01:52.52#ibcon#flushed, iclass 10, count 0 2006.201.15:01:52.52#ibcon#about to write, iclass 10, count 0 2006.201.15:01:52.52#ibcon#wrote, iclass 10, count 0 2006.201.15:01:52.52#ibcon#about to read 3, iclass 10, count 0 2006.201.15:01:52.54#ibcon#read 3, iclass 10, count 0 2006.201.15:01:52.54#ibcon#about to read 4, iclass 10, count 0 2006.201.15:01:52.54#ibcon#read 4, iclass 10, count 0 2006.201.15:01:52.54#ibcon#about to read 5, iclass 10, count 0 2006.201.15:01:52.54#ibcon#read 5, iclass 10, count 0 2006.201.15:01:52.54#ibcon#about to read 6, iclass 10, count 0 2006.201.15:01:52.54#ibcon#read 6, iclass 10, count 0 2006.201.15:01:52.54#ibcon#end of sib2, iclass 10, count 0 2006.201.15:01:52.54#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:01:52.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:01:52.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:01:52.54#ibcon#*before write, iclass 10, count 0 2006.201.15:01:52.54#ibcon#enter sib2, iclass 10, count 0 2006.201.15:01:52.54#ibcon#flushed, iclass 10, count 0 2006.201.15:01:52.54#ibcon#about to write, iclass 10, count 0 2006.201.15:01:52.54#ibcon#wrote, iclass 10, count 0 2006.201.15:01:52.54#ibcon#about to read 3, iclass 10, count 0 2006.201.15:01:52.58#ibcon#read 3, iclass 10, count 0 2006.201.15:01:52.58#ibcon#about to read 4, iclass 10, count 0 2006.201.15:01:52.58#ibcon#read 4, iclass 10, count 0 2006.201.15:01:52.58#ibcon#about to read 5, iclass 10, count 0 2006.201.15:01:52.58#ibcon#read 5, iclass 10, count 0 2006.201.15:01:52.58#ibcon#about to read 6, iclass 10, count 0 2006.201.15:01:52.58#ibcon#read 6, iclass 10, count 0 2006.201.15:01:52.58#ibcon#end of sib2, iclass 10, count 0 2006.201.15:01:52.58#ibcon#*after write, iclass 10, count 0 2006.201.15:01:52.58#ibcon#*before return 0, iclass 10, count 0 2006.201.15:01:52.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:52.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:01:52.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:01:52.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:01:52.58$vck44/vb=4,5 2006.201.15:01:52.58#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.15:01:52.58#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.15:01:52.58#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:52.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:52.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:52.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:52.64#ibcon#enter wrdev, iclass 12, count 2 2006.201.15:01:52.64#ibcon#first serial, iclass 12, count 2 2006.201.15:01:52.64#ibcon#enter sib2, iclass 12, count 2 2006.201.15:01:52.64#ibcon#flushed, iclass 12, count 2 2006.201.15:01:52.64#ibcon#about to write, iclass 12, count 2 2006.201.15:01:52.64#ibcon#wrote, iclass 12, count 2 2006.201.15:01:52.64#ibcon#about to read 3, iclass 12, count 2 2006.201.15:01:52.66#ibcon#read 3, iclass 12, count 2 2006.201.15:01:52.66#ibcon#about to read 4, iclass 12, count 2 2006.201.15:01:52.66#ibcon#read 4, iclass 12, count 2 2006.201.15:01:52.66#ibcon#about to read 5, iclass 12, count 2 2006.201.15:01:52.66#ibcon#read 5, iclass 12, count 2 2006.201.15:01:52.66#ibcon#about to read 6, iclass 12, count 2 2006.201.15:01:52.66#ibcon#read 6, iclass 12, count 2 2006.201.15:01:52.66#ibcon#end of sib2, iclass 12, count 2 2006.201.15:01:52.66#ibcon#*mode == 0, iclass 12, count 2 2006.201.15:01:52.66#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.15:01:52.66#ibcon#[27=AT04-05\r\n] 2006.201.15:01:52.66#ibcon#*before write, iclass 12, count 2 2006.201.15:01:52.66#ibcon#enter sib2, iclass 12, count 2 2006.201.15:01:52.66#ibcon#flushed, iclass 12, count 2 2006.201.15:01:52.66#ibcon#about to write, iclass 12, count 2 2006.201.15:01:52.66#ibcon#wrote, iclass 12, count 2 2006.201.15:01:52.66#ibcon#about to read 3, iclass 12, count 2 2006.201.15:01:52.69#ibcon#read 3, iclass 12, count 2 2006.201.15:01:52.69#ibcon#about to read 4, iclass 12, count 2 2006.201.15:01:52.69#ibcon#read 4, iclass 12, count 2 2006.201.15:01:52.69#ibcon#about to read 5, iclass 12, count 2 2006.201.15:01:52.69#ibcon#read 5, iclass 12, count 2 2006.201.15:01:52.69#ibcon#about to read 6, iclass 12, count 2 2006.201.15:01:52.69#ibcon#read 6, iclass 12, count 2 2006.201.15:01:52.69#ibcon#end of sib2, iclass 12, count 2 2006.201.15:01:52.69#ibcon#*after write, iclass 12, count 2 2006.201.15:01:52.69#ibcon#*before return 0, iclass 12, count 2 2006.201.15:01:52.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:52.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:01:52.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.15:01:52.69#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:52.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:52.81#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:52.81#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:52.81#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:01:52.81#ibcon#first serial, iclass 12, count 0 2006.201.15:01:52.81#ibcon#enter sib2, iclass 12, count 0 2006.201.15:01:52.81#ibcon#flushed, iclass 12, count 0 2006.201.15:01:52.81#ibcon#about to write, iclass 12, count 0 2006.201.15:01:52.81#ibcon#wrote, iclass 12, count 0 2006.201.15:01:52.81#ibcon#about to read 3, iclass 12, count 0 2006.201.15:01:52.83#ibcon#read 3, iclass 12, count 0 2006.201.15:01:52.83#ibcon#about to read 4, iclass 12, count 0 2006.201.15:01:52.83#ibcon#read 4, iclass 12, count 0 2006.201.15:01:52.83#ibcon#about to read 5, iclass 12, count 0 2006.201.15:01:52.83#ibcon#read 5, iclass 12, count 0 2006.201.15:01:52.83#ibcon#about to read 6, iclass 12, count 0 2006.201.15:01:52.83#ibcon#read 6, iclass 12, count 0 2006.201.15:01:52.83#ibcon#end of sib2, iclass 12, count 0 2006.201.15:01:52.83#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:01:52.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:01:52.83#ibcon#[27=USB\r\n] 2006.201.15:01:52.83#ibcon#*before write, iclass 12, count 0 2006.201.15:01:52.83#ibcon#enter sib2, iclass 12, count 0 2006.201.15:01:52.83#ibcon#flushed, iclass 12, count 0 2006.201.15:01:52.83#ibcon#about to write, iclass 12, count 0 2006.201.15:01:52.83#ibcon#wrote, iclass 12, count 0 2006.201.15:01:52.83#ibcon#about to read 3, iclass 12, count 0 2006.201.15:01:52.86#ibcon#read 3, iclass 12, count 0 2006.201.15:01:52.86#ibcon#about to read 4, iclass 12, count 0 2006.201.15:01:52.86#ibcon#read 4, iclass 12, count 0 2006.201.15:01:52.86#ibcon#about to read 5, iclass 12, count 0 2006.201.15:01:52.86#ibcon#read 5, iclass 12, count 0 2006.201.15:01:52.86#ibcon#about to read 6, iclass 12, count 0 2006.201.15:01:52.86#ibcon#read 6, iclass 12, count 0 2006.201.15:01:52.86#ibcon#end of sib2, iclass 12, count 0 2006.201.15:01:52.86#ibcon#*after write, iclass 12, count 0 2006.201.15:01:52.86#ibcon#*before return 0, iclass 12, count 0 2006.201.15:01:52.86#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:52.86#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:01:52.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:01:52.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:01:52.86$vck44/vblo=5,709.99 2006.201.15:01:52.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.15:01:52.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.15:01:52.86#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:52.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:52.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:52.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:52.86#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:01:52.86#ibcon#first serial, iclass 14, count 0 2006.201.15:01:52.86#ibcon#enter sib2, iclass 14, count 0 2006.201.15:01:52.86#ibcon#flushed, iclass 14, count 0 2006.201.15:01:52.86#ibcon#about to write, iclass 14, count 0 2006.201.15:01:52.86#ibcon#wrote, iclass 14, count 0 2006.201.15:01:52.86#ibcon#about to read 3, iclass 14, count 0 2006.201.15:01:52.88#ibcon#read 3, iclass 14, count 0 2006.201.15:01:52.88#ibcon#about to read 4, iclass 14, count 0 2006.201.15:01:52.88#ibcon#read 4, iclass 14, count 0 2006.201.15:01:52.88#ibcon#about to read 5, iclass 14, count 0 2006.201.15:01:52.88#ibcon#read 5, iclass 14, count 0 2006.201.15:01:52.88#ibcon#about to read 6, iclass 14, count 0 2006.201.15:01:52.88#ibcon#read 6, iclass 14, count 0 2006.201.15:01:52.88#ibcon#end of sib2, iclass 14, count 0 2006.201.15:01:52.88#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:01:52.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:01:52.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:01:52.88#ibcon#*before write, iclass 14, count 0 2006.201.15:01:52.88#ibcon#enter sib2, iclass 14, count 0 2006.201.15:01:52.88#ibcon#flushed, iclass 14, count 0 2006.201.15:01:52.88#ibcon#about to write, iclass 14, count 0 2006.201.15:01:52.88#ibcon#wrote, iclass 14, count 0 2006.201.15:01:52.88#ibcon#about to read 3, iclass 14, count 0 2006.201.15:01:52.93#ibcon#read 3, iclass 14, count 0 2006.201.15:01:52.93#ibcon#about to read 4, iclass 14, count 0 2006.201.15:01:52.93#ibcon#read 4, iclass 14, count 0 2006.201.15:01:52.93#ibcon#about to read 5, iclass 14, count 0 2006.201.15:01:52.93#ibcon#read 5, iclass 14, count 0 2006.201.15:01:52.93#ibcon#about to read 6, iclass 14, count 0 2006.201.15:01:52.93#ibcon#read 6, iclass 14, count 0 2006.201.15:01:52.93#ibcon#end of sib2, iclass 14, count 0 2006.201.15:01:52.93#ibcon#*after write, iclass 14, count 0 2006.201.15:01:52.93#ibcon#*before return 0, iclass 14, count 0 2006.201.15:01:52.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:52.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:01:52.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:01:52.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:01:52.93$vck44/vb=5,4 2006.201.15:01:52.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.15:01:52.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.15:01:52.93#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:52.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:52.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:52.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:52.98#ibcon#enter wrdev, iclass 16, count 2 2006.201.15:01:52.98#ibcon#first serial, iclass 16, count 2 2006.201.15:01:52.98#ibcon#enter sib2, iclass 16, count 2 2006.201.15:01:52.98#ibcon#flushed, iclass 16, count 2 2006.201.15:01:52.98#ibcon#about to write, iclass 16, count 2 2006.201.15:01:52.98#ibcon#wrote, iclass 16, count 2 2006.201.15:01:52.98#ibcon#about to read 3, iclass 16, count 2 2006.201.15:01:53.00#ibcon#read 3, iclass 16, count 2 2006.201.15:01:53.00#ibcon#about to read 4, iclass 16, count 2 2006.201.15:01:53.00#ibcon#read 4, iclass 16, count 2 2006.201.15:01:53.00#ibcon#about to read 5, iclass 16, count 2 2006.201.15:01:53.00#ibcon#read 5, iclass 16, count 2 2006.201.15:01:53.00#ibcon#about to read 6, iclass 16, count 2 2006.201.15:01:53.00#ibcon#read 6, iclass 16, count 2 2006.201.15:01:53.00#ibcon#end of sib2, iclass 16, count 2 2006.201.15:01:53.00#ibcon#*mode == 0, iclass 16, count 2 2006.201.15:01:53.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.15:01:53.00#ibcon#[27=AT05-04\r\n] 2006.201.15:01:53.00#ibcon#*before write, iclass 16, count 2 2006.201.15:01:53.00#ibcon#enter sib2, iclass 16, count 2 2006.201.15:01:53.00#ibcon#flushed, iclass 16, count 2 2006.201.15:01:53.00#ibcon#about to write, iclass 16, count 2 2006.201.15:01:53.00#ibcon#wrote, iclass 16, count 2 2006.201.15:01:53.00#ibcon#about to read 3, iclass 16, count 2 2006.201.15:01:53.03#ibcon#read 3, iclass 16, count 2 2006.201.15:01:53.03#ibcon#about to read 4, iclass 16, count 2 2006.201.15:01:53.03#ibcon#read 4, iclass 16, count 2 2006.201.15:01:53.03#ibcon#about to read 5, iclass 16, count 2 2006.201.15:01:53.03#ibcon#read 5, iclass 16, count 2 2006.201.15:01:53.03#ibcon#about to read 6, iclass 16, count 2 2006.201.15:01:53.03#ibcon#read 6, iclass 16, count 2 2006.201.15:01:53.03#ibcon#end of sib2, iclass 16, count 2 2006.201.15:01:53.03#ibcon#*after write, iclass 16, count 2 2006.201.15:01:53.03#ibcon#*before return 0, iclass 16, count 2 2006.201.15:01:53.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:53.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:01:53.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.15:01:53.03#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:53.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:53.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:53.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:53.15#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:01:53.15#ibcon#first serial, iclass 16, count 0 2006.201.15:01:53.15#ibcon#enter sib2, iclass 16, count 0 2006.201.15:01:53.15#ibcon#flushed, iclass 16, count 0 2006.201.15:01:53.15#ibcon#about to write, iclass 16, count 0 2006.201.15:01:53.15#ibcon#wrote, iclass 16, count 0 2006.201.15:01:53.15#ibcon#about to read 3, iclass 16, count 0 2006.201.15:01:53.17#ibcon#read 3, iclass 16, count 0 2006.201.15:01:53.17#ibcon#about to read 4, iclass 16, count 0 2006.201.15:01:53.17#ibcon#read 4, iclass 16, count 0 2006.201.15:01:53.17#ibcon#about to read 5, iclass 16, count 0 2006.201.15:01:53.17#ibcon#read 5, iclass 16, count 0 2006.201.15:01:53.17#ibcon#about to read 6, iclass 16, count 0 2006.201.15:01:53.17#ibcon#read 6, iclass 16, count 0 2006.201.15:01:53.17#ibcon#end of sib2, iclass 16, count 0 2006.201.15:01:53.17#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:01:53.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:01:53.17#ibcon#[27=USB\r\n] 2006.201.15:01:53.17#ibcon#*before write, iclass 16, count 0 2006.201.15:01:53.17#ibcon#enter sib2, iclass 16, count 0 2006.201.15:01:53.17#ibcon#flushed, iclass 16, count 0 2006.201.15:01:53.17#ibcon#about to write, iclass 16, count 0 2006.201.15:01:53.17#ibcon#wrote, iclass 16, count 0 2006.201.15:01:53.17#ibcon#about to read 3, iclass 16, count 0 2006.201.15:01:53.20#ibcon#read 3, iclass 16, count 0 2006.201.15:01:53.20#ibcon#about to read 4, iclass 16, count 0 2006.201.15:01:53.20#ibcon#read 4, iclass 16, count 0 2006.201.15:01:53.20#ibcon#about to read 5, iclass 16, count 0 2006.201.15:01:53.20#ibcon#read 5, iclass 16, count 0 2006.201.15:01:53.20#ibcon#about to read 6, iclass 16, count 0 2006.201.15:01:53.20#ibcon#read 6, iclass 16, count 0 2006.201.15:01:53.20#ibcon#end of sib2, iclass 16, count 0 2006.201.15:01:53.20#ibcon#*after write, iclass 16, count 0 2006.201.15:01:53.20#ibcon#*before return 0, iclass 16, count 0 2006.201.15:01:53.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:53.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:01:53.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:01:53.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:01:53.20$vck44/vblo=6,719.99 2006.201.15:01:53.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.15:01:53.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.15:01:53.20#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:53.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:53.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:53.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:53.20#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:01:53.20#ibcon#first serial, iclass 18, count 0 2006.201.15:01:53.20#ibcon#enter sib2, iclass 18, count 0 2006.201.15:01:53.20#ibcon#flushed, iclass 18, count 0 2006.201.15:01:53.20#ibcon#about to write, iclass 18, count 0 2006.201.15:01:53.20#ibcon#wrote, iclass 18, count 0 2006.201.15:01:53.20#ibcon#about to read 3, iclass 18, count 0 2006.201.15:01:53.22#ibcon#read 3, iclass 18, count 0 2006.201.15:01:53.22#ibcon#about to read 4, iclass 18, count 0 2006.201.15:01:53.22#ibcon#read 4, iclass 18, count 0 2006.201.15:01:53.22#ibcon#about to read 5, iclass 18, count 0 2006.201.15:01:53.22#ibcon#read 5, iclass 18, count 0 2006.201.15:01:53.22#ibcon#about to read 6, iclass 18, count 0 2006.201.15:01:53.22#ibcon#read 6, iclass 18, count 0 2006.201.15:01:53.22#ibcon#end of sib2, iclass 18, count 0 2006.201.15:01:53.22#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:01:53.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:01:53.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:01:53.22#ibcon#*before write, iclass 18, count 0 2006.201.15:01:53.22#ibcon#enter sib2, iclass 18, count 0 2006.201.15:01:53.22#ibcon#flushed, iclass 18, count 0 2006.201.15:01:53.22#ibcon#about to write, iclass 18, count 0 2006.201.15:01:53.22#ibcon#wrote, iclass 18, count 0 2006.201.15:01:53.22#ibcon#about to read 3, iclass 18, count 0 2006.201.15:01:53.26#ibcon#read 3, iclass 18, count 0 2006.201.15:01:53.26#ibcon#about to read 4, iclass 18, count 0 2006.201.15:01:53.26#ibcon#read 4, iclass 18, count 0 2006.201.15:01:53.26#ibcon#about to read 5, iclass 18, count 0 2006.201.15:01:53.26#ibcon#read 5, iclass 18, count 0 2006.201.15:01:53.26#ibcon#about to read 6, iclass 18, count 0 2006.201.15:01:53.26#ibcon#read 6, iclass 18, count 0 2006.201.15:01:53.26#ibcon#end of sib2, iclass 18, count 0 2006.201.15:01:53.26#ibcon#*after write, iclass 18, count 0 2006.201.15:01:53.26#ibcon#*before return 0, iclass 18, count 0 2006.201.15:01:53.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:53.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:01:53.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:01:53.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:01:53.26$vck44/vb=6,4 2006.201.15:01:53.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.15:01:53.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.15:01:53.26#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:53.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:53.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:53.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:53.32#ibcon#enter wrdev, iclass 20, count 2 2006.201.15:01:53.32#ibcon#first serial, iclass 20, count 2 2006.201.15:01:53.32#ibcon#enter sib2, iclass 20, count 2 2006.201.15:01:53.32#ibcon#flushed, iclass 20, count 2 2006.201.15:01:53.32#ibcon#about to write, iclass 20, count 2 2006.201.15:01:53.32#ibcon#wrote, iclass 20, count 2 2006.201.15:01:53.32#ibcon#about to read 3, iclass 20, count 2 2006.201.15:01:53.34#ibcon#read 3, iclass 20, count 2 2006.201.15:01:53.34#ibcon#about to read 4, iclass 20, count 2 2006.201.15:01:53.34#ibcon#read 4, iclass 20, count 2 2006.201.15:01:53.34#ibcon#about to read 5, iclass 20, count 2 2006.201.15:01:53.34#ibcon#read 5, iclass 20, count 2 2006.201.15:01:53.34#ibcon#about to read 6, iclass 20, count 2 2006.201.15:01:53.34#ibcon#read 6, iclass 20, count 2 2006.201.15:01:53.34#ibcon#end of sib2, iclass 20, count 2 2006.201.15:01:53.34#ibcon#*mode == 0, iclass 20, count 2 2006.201.15:01:53.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.15:01:53.34#ibcon#[27=AT06-04\r\n] 2006.201.15:01:53.34#ibcon#*before write, iclass 20, count 2 2006.201.15:01:53.34#ibcon#enter sib2, iclass 20, count 2 2006.201.15:01:53.34#ibcon#flushed, iclass 20, count 2 2006.201.15:01:53.34#ibcon#about to write, iclass 20, count 2 2006.201.15:01:53.34#ibcon#wrote, iclass 20, count 2 2006.201.15:01:53.34#ibcon#about to read 3, iclass 20, count 2 2006.201.15:01:53.37#ibcon#read 3, iclass 20, count 2 2006.201.15:01:53.37#ibcon#about to read 4, iclass 20, count 2 2006.201.15:01:53.37#ibcon#read 4, iclass 20, count 2 2006.201.15:01:53.37#ibcon#about to read 5, iclass 20, count 2 2006.201.15:01:53.37#ibcon#read 5, iclass 20, count 2 2006.201.15:01:53.37#ibcon#about to read 6, iclass 20, count 2 2006.201.15:01:53.37#ibcon#read 6, iclass 20, count 2 2006.201.15:01:53.37#ibcon#end of sib2, iclass 20, count 2 2006.201.15:01:53.37#ibcon#*after write, iclass 20, count 2 2006.201.15:01:53.37#ibcon#*before return 0, iclass 20, count 2 2006.201.15:01:53.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:53.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:01:53.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.15:01:53.37#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:53.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:53.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:53.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:53.49#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:01:53.49#ibcon#first serial, iclass 20, count 0 2006.201.15:01:53.49#ibcon#enter sib2, iclass 20, count 0 2006.201.15:01:53.49#ibcon#flushed, iclass 20, count 0 2006.201.15:01:53.49#ibcon#about to write, iclass 20, count 0 2006.201.15:01:53.49#ibcon#wrote, iclass 20, count 0 2006.201.15:01:53.49#ibcon#about to read 3, iclass 20, count 0 2006.201.15:01:53.51#ibcon#read 3, iclass 20, count 0 2006.201.15:01:53.51#ibcon#about to read 4, iclass 20, count 0 2006.201.15:01:53.51#ibcon#read 4, iclass 20, count 0 2006.201.15:01:53.51#ibcon#about to read 5, iclass 20, count 0 2006.201.15:01:53.51#ibcon#read 5, iclass 20, count 0 2006.201.15:01:53.51#ibcon#about to read 6, iclass 20, count 0 2006.201.15:01:53.51#ibcon#read 6, iclass 20, count 0 2006.201.15:01:53.51#ibcon#end of sib2, iclass 20, count 0 2006.201.15:01:53.51#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:01:53.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:01:53.51#ibcon#[27=USB\r\n] 2006.201.15:01:53.51#ibcon#*before write, iclass 20, count 0 2006.201.15:01:53.51#ibcon#enter sib2, iclass 20, count 0 2006.201.15:01:53.51#ibcon#flushed, iclass 20, count 0 2006.201.15:01:53.51#ibcon#about to write, iclass 20, count 0 2006.201.15:01:53.51#ibcon#wrote, iclass 20, count 0 2006.201.15:01:53.51#ibcon#about to read 3, iclass 20, count 0 2006.201.15:01:53.54#ibcon#read 3, iclass 20, count 0 2006.201.15:01:53.54#ibcon#about to read 4, iclass 20, count 0 2006.201.15:01:53.54#ibcon#read 4, iclass 20, count 0 2006.201.15:01:53.54#ibcon#about to read 5, iclass 20, count 0 2006.201.15:01:53.54#ibcon#read 5, iclass 20, count 0 2006.201.15:01:53.54#ibcon#about to read 6, iclass 20, count 0 2006.201.15:01:53.54#ibcon#read 6, iclass 20, count 0 2006.201.15:01:53.54#ibcon#end of sib2, iclass 20, count 0 2006.201.15:01:53.54#ibcon#*after write, iclass 20, count 0 2006.201.15:01:53.54#ibcon#*before return 0, iclass 20, count 0 2006.201.15:01:53.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:53.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:01:53.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:01:53.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:01:53.54$vck44/vblo=7,734.99 2006.201.15:01:53.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.15:01:53.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.15:01:53.54#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:53.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:53.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:53.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:53.54#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:01:53.54#ibcon#first serial, iclass 22, count 0 2006.201.15:01:53.54#ibcon#enter sib2, iclass 22, count 0 2006.201.15:01:53.54#ibcon#flushed, iclass 22, count 0 2006.201.15:01:53.54#ibcon#about to write, iclass 22, count 0 2006.201.15:01:53.54#ibcon#wrote, iclass 22, count 0 2006.201.15:01:53.54#ibcon#about to read 3, iclass 22, count 0 2006.201.15:01:53.56#ibcon#read 3, iclass 22, count 0 2006.201.15:01:53.56#ibcon#about to read 4, iclass 22, count 0 2006.201.15:01:53.56#ibcon#read 4, iclass 22, count 0 2006.201.15:01:53.56#ibcon#about to read 5, iclass 22, count 0 2006.201.15:01:53.56#ibcon#read 5, iclass 22, count 0 2006.201.15:01:53.56#ibcon#about to read 6, iclass 22, count 0 2006.201.15:01:53.56#ibcon#read 6, iclass 22, count 0 2006.201.15:01:53.56#ibcon#end of sib2, iclass 22, count 0 2006.201.15:01:53.56#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:01:53.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:01:53.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:01:53.56#ibcon#*before write, iclass 22, count 0 2006.201.15:01:53.56#ibcon#enter sib2, iclass 22, count 0 2006.201.15:01:53.56#ibcon#flushed, iclass 22, count 0 2006.201.15:01:53.56#ibcon#about to write, iclass 22, count 0 2006.201.15:01:53.56#ibcon#wrote, iclass 22, count 0 2006.201.15:01:53.56#ibcon#about to read 3, iclass 22, count 0 2006.201.15:01:53.61#ibcon#read 3, iclass 22, count 0 2006.201.15:01:53.61#ibcon#about to read 4, iclass 22, count 0 2006.201.15:01:53.61#ibcon#read 4, iclass 22, count 0 2006.201.15:01:53.61#ibcon#about to read 5, iclass 22, count 0 2006.201.15:01:53.61#ibcon#read 5, iclass 22, count 0 2006.201.15:01:53.61#ibcon#about to read 6, iclass 22, count 0 2006.201.15:01:53.61#ibcon#read 6, iclass 22, count 0 2006.201.15:01:53.61#ibcon#end of sib2, iclass 22, count 0 2006.201.15:01:53.61#ibcon#*after write, iclass 22, count 0 2006.201.15:01:53.61#ibcon#*before return 0, iclass 22, count 0 2006.201.15:01:53.61#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:53.61#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:01:53.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:01:53.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:01:53.61$vck44/vb=7,4 2006.201.15:01:53.61#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.15:01:53.61#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.15:01:53.61#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:53.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:53.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:53.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:53.66#ibcon#enter wrdev, iclass 24, count 2 2006.201.15:01:53.66#ibcon#first serial, iclass 24, count 2 2006.201.15:01:53.66#ibcon#enter sib2, iclass 24, count 2 2006.201.15:01:53.66#ibcon#flushed, iclass 24, count 2 2006.201.15:01:53.66#ibcon#about to write, iclass 24, count 2 2006.201.15:01:53.66#ibcon#wrote, iclass 24, count 2 2006.201.15:01:53.66#ibcon#about to read 3, iclass 24, count 2 2006.201.15:01:53.68#ibcon#read 3, iclass 24, count 2 2006.201.15:01:53.68#ibcon#about to read 4, iclass 24, count 2 2006.201.15:01:53.68#ibcon#read 4, iclass 24, count 2 2006.201.15:01:53.68#ibcon#about to read 5, iclass 24, count 2 2006.201.15:01:53.68#ibcon#read 5, iclass 24, count 2 2006.201.15:01:53.68#ibcon#about to read 6, iclass 24, count 2 2006.201.15:01:53.68#ibcon#read 6, iclass 24, count 2 2006.201.15:01:53.68#ibcon#end of sib2, iclass 24, count 2 2006.201.15:01:53.68#ibcon#*mode == 0, iclass 24, count 2 2006.201.15:01:53.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.15:01:53.68#ibcon#[27=AT07-04\r\n] 2006.201.15:01:53.68#ibcon#*before write, iclass 24, count 2 2006.201.15:01:53.68#ibcon#enter sib2, iclass 24, count 2 2006.201.15:01:53.68#ibcon#flushed, iclass 24, count 2 2006.201.15:01:53.68#ibcon#about to write, iclass 24, count 2 2006.201.15:01:53.68#ibcon#wrote, iclass 24, count 2 2006.201.15:01:53.68#ibcon#about to read 3, iclass 24, count 2 2006.201.15:01:53.71#ibcon#read 3, iclass 24, count 2 2006.201.15:01:53.71#ibcon#about to read 4, iclass 24, count 2 2006.201.15:01:53.71#ibcon#read 4, iclass 24, count 2 2006.201.15:01:53.71#ibcon#about to read 5, iclass 24, count 2 2006.201.15:01:53.71#ibcon#read 5, iclass 24, count 2 2006.201.15:01:53.71#ibcon#about to read 6, iclass 24, count 2 2006.201.15:01:53.71#ibcon#read 6, iclass 24, count 2 2006.201.15:01:53.71#ibcon#end of sib2, iclass 24, count 2 2006.201.15:01:53.71#ibcon#*after write, iclass 24, count 2 2006.201.15:01:53.71#ibcon#*before return 0, iclass 24, count 2 2006.201.15:01:53.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:53.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:01:53.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.15:01:53.71#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:53.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:53.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:53.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:53.83#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:01:53.83#ibcon#first serial, iclass 24, count 0 2006.201.15:01:53.83#ibcon#enter sib2, iclass 24, count 0 2006.201.15:01:53.83#ibcon#flushed, iclass 24, count 0 2006.201.15:01:53.83#ibcon#about to write, iclass 24, count 0 2006.201.15:01:53.83#ibcon#wrote, iclass 24, count 0 2006.201.15:01:53.83#ibcon#about to read 3, iclass 24, count 0 2006.201.15:01:53.85#ibcon#read 3, iclass 24, count 0 2006.201.15:01:53.85#ibcon#about to read 4, iclass 24, count 0 2006.201.15:01:53.85#ibcon#read 4, iclass 24, count 0 2006.201.15:01:53.85#ibcon#about to read 5, iclass 24, count 0 2006.201.15:01:53.85#ibcon#read 5, iclass 24, count 0 2006.201.15:01:53.85#ibcon#about to read 6, iclass 24, count 0 2006.201.15:01:53.85#ibcon#read 6, iclass 24, count 0 2006.201.15:01:53.85#ibcon#end of sib2, iclass 24, count 0 2006.201.15:01:53.85#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:01:53.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:01:53.85#ibcon#[27=USB\r\n] 2006.201.15:01:53.85#ibcon#*before write, iclass 24, count 0 2006.201.15:01:53.85#ibcon#enter sib2, iclass 24, count 0 2006.201.15:01:53.85#ibcon#flushed, iclass 24, count 0 2006.201.15:01:53.85#ibcon#about to write, iclass 24, count 0 2006.201.15:01:53.85#ibcon#wrote, iclass 24, count 0 2006.201.15:01:53.85#ibcon#about to read 3, iclass 24, count 0 2006.201.15:01:53.88#ibcon#read 3, iclass 24, count 0 2006.201.15:01:53.88#ibcon#about to read 4, iclass 24, count 0 2006.201.15:01:53.88#ibcon#read 4, iclass 24, count 0 2006.201.15:01:53.88#ibcon#about to read 5, iclass 24, count 0 2006.201.15:01:53.88#ibcon#read 5, iclass 24, count 0 2006.201.15:01:53.88#ibcon#about to read 6, iclass 24, count 0 2006.201.15:01:53.88#ibcon#read 6, iclass 24, count 0 2006.201.15:01:53.88#ibcon#end of sib2, iclass 24, count 0 2006.201.15:01:53.88#ibcon#*after write, iclass 24, count 0 2006.201.15:01:53.88#ibcon#*before return 0, iclass 24, count 0 2006.201.15:01:53.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:53.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:01:53.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:01:53.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:01:53.88$vck44/vblo=8,744.99 2006.201.15:01:53.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.15:01:53.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.15:01:53.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:01:53.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:53.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:53.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:53.88#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:01:53.88#ibcon#first serial, iclass 26, count 0 2006.201.15:01:53.88#ibcon#enter sib2, iclass 26, count 0 2006.201.15:01:53.88#ibcon#flushed, iclass 26, count 0 2006.201.15:01:53.88#ibcon#about to write, iclass 26, count 0 2006.201.15:01:53.88#ibcon#wrote, iclass 26, count 0 2006.201.15:01:53.88#ibcon#about to read 3, iclass 26, count 0 2006.201.15:01:53.90#ibcon#read 3, iclass 26, count 0 2006.201.15:01:53.90#ibcon#about to read 4, iclass 26, count 0 2006.201.15:01:53.90#ibcon#read 4, iclass 26, count 0 2006.201.15:01:53.90#ibcon#about to read 5, iclass 26, count 0 2006.201.15:01:53.90#ibcon#read 5, iclass 26, count 0 2006.201.15:01:53.90#ibcon#about to read 6, iclass 26, count 0 2006.201.15:01:53.90#ibcon#read 6, iclass 26, count 0 2006.201.15:01:53.90#ibcon#end of sib2, iclass 26, count 0 2006.201.15:01:53.90#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:01:53.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:01:53.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:01:53.90#ibcon#*before write, iclass 26, count 0 2006.201.15:01:53.90#ibcon#enter sib2, iclass 26, count 0 2006.201.15:01:53.90#ibcon#flushed, iclass 26, count 0 2006.201.15:01:53.90#ibcon#about to write, iclass 26, count 0 2006.201.15:01:53.90#ibcon#wrote, iclass 26, count 0 2006.201.15:01:53.90#ibcon#about to read 3, iclass 26, count 0 2006.201.15:01:53.95#ibcon#read 3, iclass 26, count 0 2006.201.15:01:53.95#ibcon#about to read 4, iclass 26, count 0 2006.201.15:01:53.95#ibcon#read 4, iclass 26, count 0 2006.201.15:01:53.95#ibcon#about to read 5, iclass 26, count 0 2006.201.15:01:53.95#ibcon#read 5, iclass 26, count 0 2006.201.15:01:53.95#ibcon#about to read 6, iclass 26, count 0 2006.201.15:01:53.95#ibcon#read 6, iclass 26, count 0 2006.201.15:01:53.95#ibcon#end of sib2, iclass 26, count 0 2006.201.15:01:53.95#ibcon#*after write, iclass 26, count 0 2006.201.15:01:53.95#ibcon#*before return 0, iclass 26, count 0 2006.201.15:01:53.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:53.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:01:53.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:01:53.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:01:53.95$vck44/vb=8,4 2006.201.15:01:53.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.15:01:53.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.15:01:53.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:01:53.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:01:53.96#abcon#<5=/04 0.8 1.9 20.761001003.3\r\n> 2006.201.15:01:53.98#abcon#{5=INTERFACE CLEAR} 2006.201.15:01:54.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:01:54.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:01:54.00#ibcon#enter wrdev, iclass 29, count 2 2006.201.15:01:54.00#ibcon#first serial, iclass 29, count 2 2006.201.15:01:54.00#ibcon#enter sib2, iclass 29, count 2 2006.201.15:01:54.00#ibcon#flushed, iclass 29, count 2 2006.201.15:01:54.00#ibcon#about to write, iclass 29, count 2 2006.201.15:01:54.00#ibcon#wrote, iclass 29, count 2 2006.201.15:01:54.00#ibcon#about to read 3, iclass 29, count 2 2006.201.15:01:54.02#ibcon#read 3, iclass 29, count 2 2006.201.15:01:54.02#ibcon#about to read 4, iclass 29, count 2 2006.201.15:01:54.02#ibcon#read 4, iclass 29, count 2 2006.201.15:01:54.02#ibcon#about to read 5, iclass 29, count 2 2006.201.15:01:54.02#ibcon#read 5, iclass 29, count 2 2006.201.15:01:54.02#ibcon#about to read 6, iclass 29, count 2 2006.201.15:01:54.02#ibcon#read 6, iclass 29, count 2 2006.201.15:01:54.02#ibcon#end of sib2, iclass 29, count 2 2006.201.15:01:54.02#ibcon#*mode == 0, iclass 29, count 2 2006.201.15:01:54.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.15:01:54.02#ibcon#[27=AT08-04\r\n] 2006.201.15:01:54.02#ibcon#*before write, iclass 29, count 2 2006.201.15:01:54.02#ibcon#enter sib2, iclass 29, count 2 2006.201.15:01:54.02#ibcon#flushed, iclass 29, count 2 2006.201.15:01:54.02#ibcon#about to write, iclass 29, count 2 2006.201.15:01:54.02#ibcon#wrote, iclass 29, count 2 2006.201.15:01:54.02#ibcon#about to read 3, iclass 29, count 2 2006.201.15:01:54.04#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:01:54.05#ibcon#read 3, iclass 29, count 2 2006.201.15:01:54.05#ibcon#about to read 4, iclass 29, count 2 2006.201.15:01:54.05#ibcon#read 4, iclass 29, count 2 2006.201.15:01:54.05#ibcon#about to read 5, iclass 29, count 2 2006.201.15:01:54.05#ibcon#read 5, iclass 29, count 2 2006.201.15:01:54.05#ibcon#about to read 6, iclass 29, count 2 2006.201.15:01:54.05#ibcon#read 6, iclass 29, count 2 2006.201.15:01:54.05#ibcon#end of sib2, iclass 29, count 2 2006.201.15:01:54.05#ibcon#*after write, iclass 29, count 2 2006.201.15:01:54.05#ibcon#*before return 0, iclass 29, count 2 2006.201.15:01:54.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:01:54.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:01:54.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.15:01:54.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:01:54.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:01:54.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:01:54.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:01:54.17#ibcon#enter wrdev, iclass 29, count 0 2006.201.15:01:54.17#ibcon#first serial, iclass 29, count 0 2006.201.15:01:54.17#ibcon#enter sib2, iclass 29, count 0 2006.201.15:01:54.17#ibcon#flushed, iclass 29, count 0 2006.201.15:01:54.17#ibcon#about to write, iclass 29, count 0 2006.201.15:01:54.17#ibcon#wrote, iclass 29, count 0 2006.201.15:01:54.17#ibcon#about to read 3, iclass 29, count 0 2006.201.15:01:54.20#ibcon#read 3, iclass 29, count 0 2006.201.15:01:54.20#ibcon#about to read 4, iclass 29, count 0 2006.201.15:01:54.20#ibcon#read 4, iclass 29, count 0 2006.201.15:01:54.20#ibcon#about to read 5, iclass 29, count 0 2006.201.15:01:54.20#ibcon#read 5, iclass 29, count 0 2006.201.15:01:54.20#ibcon#about to read 6, iclass 29, count 0 2006.201.15:01:54.20#ibcon#read 6, iclass 29, count 0 2006.201.15:01:54.20#ibcon#end of sib2, iclass 29, count 0 2006.201.15:01:54.20#ibcon#*mode == 0, iclass 29, count 0 2006.201.15:01:54.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.15:01:54.20#ibcon#[27=USB\r\n] 2006.201.15:01:54.20#ibcon#*before write, iclass 29, count 0 2006.201.15:01:54.20#ibcon#enter sib2, iclass 29, count 0 2006.201.15:01:54.20#ibcon#flushed, iclass 29, count 0 2006.201.15:01:54.20#ibcon#about to write, iclass 29, count 0 2006.201.15:01:54.20#ibcon#wrote, iclass 29, count 0 2006.201.15:01:54.20#ibcon#about to read 3, iclass 29, count 0 2006.201.15:01:54.23#ibcon#read 3, iclass 29, count 0 2006.201.15:01:54.23#ibcon#about to read 4, iclass 29, count 0 2006.201.15:01:54.23#ibcon#read 4, iclass 29, count 0 2006.201.15:01:54.23#ibcon#about to read 5, iclass 29, count 0 2006.201.15:01:54.23#ibcon#read 5, iclass 29, count 0 2006.201.15:01:54.23#ibcon#about to read 6, iclass 29, count 0 2006.201.15:01:54.23#ibcon#read 6, iclass 29, count 0 2006.201.15:01:54.23#ibcon#end of sib2, iclass 29, count 0 2006.201.15:01:54.23#ibcon#*after write, iclass 29, count 0 2006.201.15:01:54.23#ibcon#*before return 0, iclass 29, count 0 2006.201.15:01:54.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:01:54.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:01:54.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.15:01:54.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.15:01:54.23$vck44/vabw=wide 2006.201.15:01:54.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.15:01:54.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.15:01:54.23#ibcon#ireg 8 cls_cnt 0 2006.201.15:01:54.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:54.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:54.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:54.23#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:01:54.23#ibcon#first serial, iclass 34, count 0 2006.201.15:01:54.23#ibcon#enter sib2, iclass 34, count 0 2006.201.15:01:54.23#ibcon#flushed, iclass 34, count 0 2006.201.15:01:54.23#ibcon#about to write, iclass 34, count 0 2006.201.15:01:54.23#ibcon#wrote, iclass 34, count 0 2006.201.15:01:54.23#ibcon#about to read 3, iclass 34, count 0 2006.201.15:01:54.25#ibcon#read 3, iclass 34, count 0 2006.201.15:01:54.25#ibcon#about to read 4, iclass 34, count 0 2006.201.15:01:54.25#ibcon#read 4, iclass 34, count 0 2006.201.15:01:54.25#ibcon#about to read 5, iclass 34, count 0 2006.201.15:01:54.25#ibcon#read 5, iclass 34, count 0 2006.201.15:01:54.25#ibcon#about to read 6, iclass 34, count 0 2006.201.15:01:54.25#ibcon#read 6, iclass 34, count 0 2006.201.15:01:54.25#ibcon#end of sib2, iclass 34, count 0 2006.201.15:01:54.25#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:01:54.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:01:54.25#ibcon#[25=BW32\r\n] 2006.201.15:01:54.25#ibcon#*before write, iclass 34, count 0 2006.201.15:01:54.25#ibcon#enter sib2, iclass 34, count 0 2006.201.15:01:54.25#ibcon#flushed, iclass 34, count 0 2006.201.15:01:54.25#ibcon#about to write, iclass 34, count 0 2006.201.15:01:54.25#ibcon#wrote, iclass 34, count 0 2006.201.15:01:54.25#ibcon#about to read 3, iclass 34, count 0 2006.201.15:01:54.28#ibcon#read 3, iclass 34, count 0 2006.201.15:01:54.28#ibcon#about to read 4, iclass 34, count 0 2006.201.15:01:54.28#ibcon#read 4, iclass 34, count 0 2006.201.15:01:54.28#ibcon#about to read 5, iclass 34, count 0 2006.201.15:01:54.28#ibcon#read 5, iclass 34, count 0 2006.201.15:01:54.28#ibcon#about to read 6, iclass 34, count 0 2006.201.15:01:54.28#ibcon#read 6, iclass 34, count 0 2006.201.15:01:54.28#ibcon#end of sib2, iclass 34, count 0 2006.201.15:01:54.28#ibcon#*after write, iclass 34, count 0 2006.201.15:01:54.28#ibcon#*before return 0, iclass 34, count 0 2006.201.15:01:54.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:54.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:01:54.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:01:54.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:01:54.28$vck44/vbbw=wide 2006.201.15:01:54.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.15:01:54.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.15:01:54.28#ibcon#ireg 8 cls_cnt 0 2006.201.15:01:54.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:01:54.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:01:54.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:01:54.35#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:01:54.35#ibcon#first serial, iclass 36, count 0 2006.201.15:01:54.35#ibcon#enter sib2, iclass 36, count 0 2006.201.15:01:54.35#ibcon#flushed, iclass 36, count 0 2006.201.15:01:54.35#ibcon#about to write, iclass 36, count 0 2006.201.15:01:54.35#ibcon#wrote, iclass 36, count 0 2006.201.15:01:54.35#ibcon#about to read 3, iclass 36, count 0 2006.201.15:01:54.37#ibcon#read 3, iclass 36, count 0 2006.201.15:01:54.37#ibcon#about to read 4, iclass 36, count 0 2006.201.15:01:54.37#ibcon#read 4, iclass 36, count 0 2006.201.15:01:54.37#ibcon#about to read 5, iclass 36, count 0 2006.201.15:01:54.37#ibcon#read 5, iclass 36, count 0 2006.201.15:01:54.37#ibcon#about to read 6, iclass 36, count 0 2006.201.15:01:54.37#ibcon#read 6, iclass 36, count 0 2006.201.15:01:54.37#ibcon#end of sib2, iclass 36, count 0 2006.201.15:01:54.37#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:01:54.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:01:54.37#ibcon#[27=BW32\r\n] 2006.201.15:01:54.37#ibcon#*before write, iclass 36, count 0 2006.201.15:01:54.37#ibcon#enter sib2, iclass 36, count 0 2006.201.15:01:54.37#ibcon#flushed, iclass 36, count 0 2006.201.15:01:54.37#ibcon#about to write, iclass 36, count 0 2006.201.15:01:54.37#ibcon#wrote, iclass 36, count 0 2006.201.15:01:54.37#ibcon#about to read 3, iclass 36, count 0 2006.201.15:01:54.40#ibcon#read 3, iclass 36, count 0 2006.201.15:01:54.40#ibcon#about to read 4, iclass 36, count 0 2006.201.15:01:54.40#ibcon#read 4, iclass 36, count 0 2006.201.15:01:54.40#ibcon#about to read 5, iclass 36, count 0 2006.201.15:01:54.40#ibcon#read 5, iclass 36, count 0 2006.201.15:01:54.40#ibcon#about to read 6, iclass 36, count 0 2006.201.15:01:54.40#ibcon#read 6, iclass 36, count 0 2006.201.15:01:54.40#ibcon#end of sib2, iclass 36, count 0 2006.201.15:01:54.40#ibcon#*after write, iclass 36, count 0 2006.201.15:01:54.40#ibcon#*before return 0, iclass 36, count 0 2006.201.15:01:54.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:01:54.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:01:54.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:01:54.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:01:54.40$setupk4/ifdk4 2006.201.15:01:54.40$ifdk4/lo= 2006.201.15:01:54.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:01:54.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:01:54.40$ifdk4/patch= 2006.201.15:01:54.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:01:54.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:01:54.40$setupk4/!*+20s 2006.201.15:02:04.13#abcon#<5=/04 0.8 1.9 20.761001003.3\r\n> 2006.201.15:02:04.15#abcon#{5=INTERFACE CLEAR} 2006.201.15:02:04.22#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:02:08.87$setupk4/"tpicd 2006.201.15:02:08.87$setupk4/echo=off 2006.201.15:02:08.87$setupk4/xlog=off 2006.201.15:02:08.87:!2006.201.15:04:37 2006.201.15:02:10.14#trakl#Source acquired 2006.201.15:02:12.14#flagr#flagr/antenna,acquired 2006.201.15:04:37.00:preob 2006.201.15:04:37.13/onsource/TRACKING 2006.201.15:04:37.13:!2006.201.15:04:47 2006.201.15:04:47.00:"tape 2006.201.15:04:47.00:"st=record 2006.201.15:04:47.00:data_valid=on 2006.201.15:04:47.00:midob 2006.201.15:04:48.13/onsource/TRACKING 2006.201.15:04:48.13/wx/20.77,1003.3,100 2006.201.15:04:48.21/cable/+6.4760E-03 2006.201.15:04:49.30/va/01,08,usb,yes,29,31 2006.201.15:04:49.30/va/02,07,usb,yes,31,32 2006.201.15:04:49.30/va/03,08,usb,yes,28,29 2006.201.15:04:49.30/va/04,07,usb,yes,32,34 2006.201.15:04:49.30/va/05,04,usb,yes,28,29 2006.201.15:04:49.30/va/06,05,usb,yes,28,28 2006.201.15:04:49.30/va/07,05,usb,yes,27,29 2006.201.15:04:49.30/va/08,04,usb,yes,27,33 2006.201.15:04:49.53/valo/01,524.99,yes,locked 2006.201.15:04:49.53/valo/02,534.99,yes,locked 2006.201.15:04:49.53/valo/03,564.99,yes,locked 2006.201.15:04:49.53/valo/04,624.99,yes,locked 2006.201.15:04:49.53/valo/05,734.99,yes,locked 2006.201.15:04:49.53/valo/06,814.99,yes,locked 2006.201.15:04:49.53/valo/07,864.99,yes,locked 2006.201.15:04:49.53/valo/08,884.99,yes,locked 2006.201.15:04:50.62/vb/01,04,usb,yes,29,27 2006.201.15:04:50.62/vb/02,05,usb,yes,27,27 2006.201.15:04:50.62/vb/03,04,usb,yes,28,31 2006.201.15:04:50.62/vb/04,05,usb,yes,29,28 2006.201.15:04:50.62/vb/05,04,usb,yes,25,28 2006.201.15:04:50.62/vb/06,04,usb,yes,30,26 2006.201.15:04:50.62/vb/07,04,usb,yes,29,29 2006.201.15:04:50.62/vb/08,04,usb,yes,27,30 2006.201.15:04:50.86/vblo/01,629.99,yes,locked 2006.201.15:04:50.86/vblo/02,634.99,yes,locked 2006.201.15:04:50.86/vblo/03,649.99,yes,locked 2006.201.15:04:50.86/vblo/04,679.99,yes,locked 2006.201.15:04:50.86/vblo/05,709.99,yes,locked 2006.201.15:04:50.86/vblo/06,719.99,yes,locked 2006.201.15:04:50.86/vblo/07,734.99,yes,locked 2006.201.15:04:50.86/vblo/08,744.99,yes,locked 2006.201.15:04:51.01/vabw/8 2006.201.15:04:51.16/vbbw/8 2006.201.15:04:51.25/xfe/off,on,15.0 2006.201.15:04:51.63/ifatt/23,28,28,28 2006.201.15:04:52.06/fmout-gps/S +4.57E-07 2006.201.15:04:52.13:!2006.201.15:05:27 2006.201.15:05:27.00:data_valid=off 2006.201.15:05:27.00:"et 2006.201.15:05:27.00:!+3s 2006.201.15:05:30.02:"tape 2006.201.15:05:30.02:postob 2006.201.15:05:30.17/cable/+6.4761E-03 2006.201.15:05:30.20/wx/20.77,1003.3,100 2006.201.15:05:30.28/fmout-gps/S +4.56E-07 2006.201.15:05:30.28:scan_name=201-1506,jd0607,40 2006.201.15:05:30.28:source=1954-388,195800.00,-384506.4,2000.0,cw 2006.201.15:05:32.13#flagr#flagr/antenna,new-source 2006.201.15:05:32.13:checkk5 2006.201.15:05:32.56/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:05:32.94/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:05:33.33/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:05:33.72/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:05:34.08/chk_obsdata//k5ts1/T2011504??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.15:05:34.45/chk_obsdata//k5ts2/T2011504??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.15:05:34.82/chk_obsdata//k5ts3/T2011504??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.15:05:35.18/chk_obsdata//k5ts4/T2011504??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.15:05:35.87/k5log//k5ts1_log_newline 2006.201.15:05:36.57/k5log//k5ts2_log_newline 2006.201.15:05:37.26/k5log//k5ts3_log_newline 2006.201.15:05:37.94/k5log//k5ts4_log_newline 2006.201.15:05:37.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:05:37.97:setupk4=1 2006.201.15:05:37.97$setupk4/echo=on 2006.201.15:05:37.97$setupk4/pcalon 2006.201.15:05:37.97$pcalon/"no phase cal control is implemented here 2006.201.15:05:37.97$setupk4/"tpicd=stop 2006.201.15:05:37.97$setupk4/"rec=synch_on 2006.201.15:05:37.97$setupk4/"rec_mode=128 2006.201.15:05:37.97$setupk4/!* 2006.201.15:05:37.97$setupk4/recpk4 2006.201.15:05:37.97$recpk4/recpatch= 2006.201.15:05:37.97$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:05:37.97$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:05:37.97$setupk4/vck44 2006.201.15:05:37.97$vck44/valo=1,524.99 2006.201.15:05:37.97#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.15:05:37.97#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.15:05:37.97#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:37.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:37.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:37.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:37.97#ibcon#enter wrdev, iclass 21, count 0 2006.201.15:05:37.97#ibcon#first serial, iclass 21, count 0 2006.201.15:05:37.97#ibcon#enter sib2, iclass 21, count 0 2006.201.15:05:37.97#ibcon#flushed, iclass 21, count 0 2006.201.15:05:37.97#ibcon#about to write, iclass 21, count 0 2006.201.15:05:37.97#ibcon#wrote, iclass 21, count 0 2006.201.15:05:37.97#ibcon#about to read 3, iclass 21, count 0 2006.201.15:05:37.99#ibcon#read 3, iclass 21, count 0 2006.201.15:05:37.99#ibcon#about to read 4, iclass 21, count 0 2006.201.15:05:37.99#ibcon#read 4, iclass 21, count 0 2006.201.15:05:37.99#ibcon#about to read 5, iclass 21, count 0 2006.201.15:05:37.99#ibcon#read 5, iclass 21, count 0 2006.201.15:05:37.99#ibcon#about to read 6, iclass 21, count 0 2006.201.15:05:37.99#ibcon#read 6, iclass 21, count 0 2006.201.15:05:37.99#ibcon#end of sib2, iclass 21, count 0 2006.201.15:05:37.99#ibcon#*mode == 0, iclass 21, count 0 2006.201.15:05:37.99#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.15:05:37.99#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:05:37.99#ibcon#*before write, iclass 21, count 0 2006.201.15:05:37.99#ibcon#enter sib2, iclass 21, count 0 2006.201.15:05:37.99#ibcon#flushed, iclass 21, count 0 2006.201.15:05:37.99#ibcon#about to write, iclass 21, count 0 2006.201.15:05:37.99#ibcon#wrote, iclass 21, count 0 2006.201.15:05:37.99#ibcon#about to read 3, iclass 21, count 0 2006.201.15:05:38.04#ibcon#read 3, iclass 21, count 0 2006.201.15:05:38.04#ibcon#about to read 4, iclass 21, count 0 2006.201.15:05:38.04#ibcon#read 4, iclass 21, count 0 2006.201.15:05:38.04#ibcon#about to read 5, iclass 21, count 0 2006.201.15:05:38.04#ibcon#read 5, iclass 21, count 0 2006.201.15:05:38.04#ibcon#about to read 6, iclass 21, count 0 2006.201.15:05:38.04#ibcon#read 6, iclass 21, count 0 2006.201.15:05:38.04#ibcon#end of sib2, iclass 21, count 0 2006.201.15:05:38.04#ibcon#*after write, iclass 21, count 0 2006.201.15:05:38.04#ibcon#*before return 0, iclass 21, count 0 2006.201.15:05:38.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:38.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:38.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.15:05:38.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.15:05:38.04$vck44/va=1,8 2006.201.15:05:38.04#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.15:05:38.04#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.15:05:38.04#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:38.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:38.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:38.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:38.04#ibcon#enter wrdev, iclass 23, count 2 2006.201.15:05:38.04#ibcon#first serial, iclass 23, count 2 2006.201.15:05:38.04#ibcon#enter sib2, iclass 23, count 2 2006.201.15:05:38.04#ibcon#flushed, iclass 23, count 2 2006.201.15:05:38.04#ibcon#about to write, iclass 23, count 2 2006.201.15:05:38.04#ibcon#wrote, iclass 23, count 2 2006.201.15:05:38.04#ibcon#about to read 3, iclass 23, count 2 2006.201.15:05:38.06#ibcon#read 3, iclass 23, count 2 2006.201.15:05:38.06#ibcon#about to read 4, iclass 23, count 2 2006.201.15:05:38.06#ibcon#read 4, iclass 23, count 2 2006.201.15:05:38.06#ibcon#about to read 5, iclass 23, count 2 2006.201.15:05:38.06#ibcon#read 5, iclass 23, count 2 2006.201.15:05:38.06#ibcon#about to read 6, iclass 23, count 2 2006.201.15:05:38.06#ibcon#read 6, iclass 23, count 2 2006.201.15:05:38.06#ibcon#end of sib2, iclass 23, count 2 2006.201.15:05:38.06#ibcon#*mode == 0, iclass 23, count 2 2006.201.15:05:38.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.15:05:38.06#ibcon#[25=AT01-08\r\n] 2006.201.15:05:38.06#ibcon#*before write, iclass 23, count 2 2006.201.15:05:38.06#ibcon#enter sib2, iclass 23, count 2 2006.201.15:05:38.06#ibcon#flushed, iclass 23, count 2 2006.201.15:05:38.06#ibcon#about to write, iclass 23, count 2 2006.201.15:05:38.06#ibcon#wrote, iclass 23, count 2 2006.201.15:05:38.06#ibcon#about to read 3, iclass 23, count 2 2006.201.15:05:38.09#ibcon#read 3, iclass 23, count 2 2006.201.15:05:38.09#ibcon#about to read 4, iclass 23, count 2 2006.201.15:05:38.09#ibcon#read 4, iclass 23, count 2 2006.201.15:05:38.09#ibcon#about to read 5, iclass 23, count 2 2006.201.15:05:38.09#ibcon#read 5, iclass 23, count 2 2006.201.15:05:38.09#ibcon#about to read 6, iclass 23, count 2 2006.201.15:05:38.09#ibcon#read 6, iclass 23, count 2 2006.201.15:05:38.09#ibcon#end of sib2, iclass 23, count 2 2006.201.15:05:38.09#ibcon#*after write, iclass 23, count 2 2006.201.15:05:38.09#ibcon#*before return 0, iclass 23, count 2 2006.201.15:05:38.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:38.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:38.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.15:05:38.09#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:38.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:38.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:38.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:38.21#ibcon#enter wrdev, iclass 23, count 0 2006.201.15:05:38.21#ibcon#first serial, iclass 23, count 0 2006.201.15:05:38.21#ibcon#enter sib2, iclass 23, count 0 2006.201.15:05:38.21#ibcon#flushed, iclass 23, count 0 2006.201.15:05:38.21#ibcon#about to write, iclass 23, count 0 2006.201.15:05:38.21#ibcon#wrote, iclass 23, count 0 2006.201.15:05:38.21#ibcon#about to read 3, iclass 23, count 0 2006.201.15:05:38.23#ibcon#read 3, iclass 23, count 0 2006.201.15:05:38.23#ibcon#about to read 4, iclass 23, count 0 2006.201.15:05:38.23#ibcon#read 4, iclass 23, count 0 2006.201.15:05:38.23#ibcon#about to read 5, iclass 23, count 0 2006.201.15:05:38.23#ibcon#read 5, iclass 23, count 0 2006.201.15:05:38.23#ibcon#about to read 6, iclass 23, count 0 2006.201.15:05:38.23#ibcon#read 6, iclass 23, count 0 2006.201.15:05:38.23#ibcon#end of sib2, iclass 23, count 0 2006.201.15:05:38.23#ibcon#*mode == 0, iclass 23, count 0 2006.201.15:05:38.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.15:05:38.23#ibcon#[25=USB\r\n] 2006.201.15:05:38.23#ibcon#*before write, iclass 23, count 0 2006.201.15:05:38.23#ibcon#enter sib2, iclass 23, count 0 2006.201.15:05:38.23#ibcon#flushed, iclass 23, count 0 2006.201.15:05:38.23#ibcon#about to write, iclass 23, count 0 2006.201.15:05:38.23#ibcon#wrote, iclass 23, count 0 2006.201.15:05:38.23#ibcon#about to read 3, iclass 23, count 0 2006.201.15:05:38.26#ibcon#read 3, iclass 23, count 0 2006.201.15:05:38.26#ibcon#about to read 4, iclass 23, count 0 2006.201.15:05:38.26#ibcon#read 4, iclass 23, count 0 2006.201.15:05:38.26#ibcon#about to read 5, iclass 23, count 0 2006.201.15:05:38.26#ibcon#read 5, iclass 23, count 0 2006.201.15:05:38.26#ibcon#about to read 6, iclass 23, count 0 2006.201.15:05:38.26#ibcon#read 6, iclass 23, count 0 2006.201.15:05:38.26#ibcon#end of sib2, iclass 23, count 0 2006.201.15:05:38.26#ibcon#*after write, iclass 23, count 0 2006.201.15:05:38.26#ibcon#*before return 0, iclass 23, count 0 2006.201.15:05:38.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:38.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:38.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.15:05:38.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.15:05:38.26$vck44/valo=2,534.99 2006.201.15:05:38.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.15:05:38.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.15:05:38.26#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:38.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:38.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:38.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:38.26#ibcon#enter wrdev, iclass 25, count 0 2006.201.15:05:38.26#ibcon#first serial, iclass 25, count 0 2006.201.15:05:38.26#ibcon#enter sib2, iclass 25, count 0 2006.201.15:05:38.26#ibcon#flushed, iclass 25, count 0 2006.201.15:05:38.26#ibcon#about to write, iclass 25, count 0 2006.201.15:05:38.26#ibcon#wrote, iclass 25, count 0 2006.201.15:05:38.26#ibcon#about to read 3, iclass 25, count 0 2006.201.15:05:38.28#ibcon#read 3, iclass 25, count 0 2006.201.15:05:38.28#ibcon#about to read 4, iclass 25, count 0 2006.201.15:05:38.28#ibcon#read 4, iclass 25, count 0 2006.201.15:05:38.28#ibcon#about to read 5, iclass 25, count 0 2006.201.15:05:38.28#ibcon#read 5, iclass 25, count 0 2006.201.15:05:38.28#ibcon#about to read 6, iclass 25, count 0 2006.201.15:05:38.28#ibcon#read 6, iclass 25, count 0 2006.201.15:05:38.28#ibcon#end of sib2, iclass 25, count 0 2006.201.15:05:38.28#ibcon#*mode == 0, iclass 25, count 0 2006.201.15:05:38.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.15:05:38.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:05:38.28#ibcon#*before write, iclass 25, count 0 2006.201.15:05:38.28#ibcon#enter sib2, iclass 25, count 0 2006.201.15:05:38.28#ibcon#flushed, iclass 25, count 0 2006.201.15:05:38.28#ibcon#about to write, iclass 25, count 0 2006.201.15:05:38.28#ibcon#wrote, iclass 25, count 0 2006.201.15:05:38.28#ibcon#about to read 3, iclass 25, count 0 2006.201.15:05:38.33#ibcon#read 3, iclass 25, count 0 2006.201.15:05:38.33#ibcon#about to read 4, iclass 25, count 0 2006.201.15:05:38.33#ibcon#read 4, iclass 25, count 0 2006.201.15:05:38.33#ibcon#about to read 5, iclass 25, count 0 2006.201.15:05:38.33#ibcon#read 5, iclass 25, count 0 2006.201.15:05:38.33#ibcon#about to read 6, iclass 25, count 0 2006.201.15:05:38.33#ibcon#read 6, iclass 25, count 0 2006.201.15:05:38.33#ibcon#end of sib2, iclass 25, count 0 2006.201.15:05:38.33#ibcon#*after write, iclass 25, count 0 2006.201.15:05:38.33#ibcon#*before return 0, iclass 25, count 0 2006.201.15:05:38.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:38.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:38.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.15:05:38.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.15:05:38.33$vck44/va=2,7 2006.201.15:05:38.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.15:05:38.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.15:05:38.33#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:38.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:38.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:38.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:38.38#ibcon#enter wrdev, iclass 27, count 2 2006.201.15:05:38.38#ibcon#first serial, iclass 27, count 2 2006.201.15:05:38.38#ibcon#enter sib2, iclass 27, count 2 2006.201.15:05:38.38#ibcon#flushed, iclass 27, count 2 2006.201.15:05:38.38#ibcon#about to write, iclass 27, count 2 2006.201.15:05:38.38#ibcon#wrote, iclass 27, count 2 2006.201.15:05:38.38#ibcon#about to read 3, iclass 27, count 2 2006.201.15:05:38.40#ibcon#read 3, iclass 27, count 2 2006.201.15:05:38.40#ibcon#about to read 4, iclass 27, count 2 2006.201.15:05:38.40#ibcon#read 4, iclass 27, count 2 2006.201.15:05:38.40#ibcon#about to read 5, iclass 27, count 2 2006.201.15:05:38.40#ibcon#read 5, iclass 27, count 2 2006.201.15:05:38.40#ibcon#about to read 6, iclass 27, count 2 2006.201.15:05:38.40#ibcon#read 6, iclass 27, count 2 2006.201.15:05:38.40#ibcon#end of sib2, iclass 27, count 2 2006.201.15:05:38.40#ibcon#*mode == 0, iclass 27, count 2 2006.201.15:05:38.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.15:05:38.40#ibcon#[25=AT02-07\r\n] 2006.201.15:05:38.40#ibcon#*before write, iclass 27, count 2 2006.201.15:05:38.40#ibcon#enter sib2, iclass 27, count 2 2006.201.15:05:38.40#ibcon#flushed, iclass 27, count 2 2006.201.15:05:38.40#ibcon#about to write, iclass 27, count 2 2006.201.15:05:38.40#ibcon#wrote, iclass 27, count 2 2006.201.15:05:38.40#ibcon#about to read 3, iclass 27, count 2 2006.201.15:05:38.43#ibcon#read 3, iclass 27, count 2 2006.201.15:05:38.43#ibcon#about to read 4, iclass 27, count 2 2006.201.15:05:38.43#ibcon#read 4, iclass 27, count 2 2006.201.15:05:38.43#ibcon#about to read 5, iclass 27, count 2 2006.201.15:05:38.43#ibcon#read 5, iclass 27, count 2 2006.201.15:05:38.43#ibcon#about to read 6, iclass 27, count 2 2006.201.15:05:38.43#ibcon#read 6, iclass 27, count 2 2006.201.15:05:38.43#ibcon#end of sib2, iclass 27, count 2 2006.201.15:05:38.43#ibcon#*after write, iclass 27, count 2 2006.201.15:05:38.43#ibcon#*before return 0, iclass 27, count 2 2006.201.15:05:38.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:38.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:38.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.15:05:38.43#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:38.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:38.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:38.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:38.55#ibcon#enter wrdev, iclass 27, count 0 2006.201.15:05:38.55#ibcon#first serial, iclass 27, count 0 2006.201.15:05:38.55#ibcon#enter sib2, iclass 27, count 0 2006.201.15:05:38.55#ibcon#flushed, iclass 27, count 0 2006.201.15:05:38.55#ibcon#about to write, iclass 27, count 0 2006.201.15:05:38.55#ibcon#wrote, iclass 27, count 0 2006.201.15:05:38.55#ibcon#about to read 3, iclass 27, count 0 2006.201.15:05:38.57#ibcon#read 3, iclass 27, count 0 2006.201.15:05:38.57#ibcon#about to read 4, iclass 27, count 0 2006.201.15:05:38.57#ibcon#read 4, iclass 27, count 0 2006.201.15:05:38.57#ibcon#about to read 5, iclass 27, count 0 2006.201.15:05:38.57#ibcon#read 5, iclass 27, count 0 2006.201.15:05:38.57#ibcon#about to read 6, iclass 27, count 0 2006.201.15:05:38.57#ibcon#read 6, iclass 27, count 0 2006.201.15:05:38.57#ibcon#end of sib2, iclass 27, count 0 2006.201.15:05:38.57#ibcon#*mode == 0, iclass 27, count 0 2006.201.15:05:38.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.15:05:38.57#ibcon#[25=USB\r\n] 2006.201.15:05:38.57#ibcon#*before write, iclass 27, count 0 2006.201.15:05:38.57#ibcon#enter sib2, iclass 27, count 0 2006.201.15:05:38.57#ibcon#flushed, iclass 27, count 0 2006.201.15:05:38.57#ibcon#about to write, iclass 27, count 0 2006.201.15:05:38.57#ibcon#wrote, iclass 27, count 0 2006.201.15:05:38.57#ibcon#about to read 3, iclass 27, count 0 2006.201.15:05:38.60#ibcon#read 3, iclass 27, count 0 2006.201.15:05:38.60#ibcon#about to read 4, iclass 27, count 0 2006.201.15:05:38.60#ibcon#read 4, iclass 27, count 0 2006.201.15:05:38.60#ibcon#about to read 5, iclass 27, count 0 2006.201.15:05:38.60#ibcon#read 5, iclass 27, count 0 2006.201.15:05:38.60#ibcon#about to read 6, iclass 27, count 0 2006.201.15:05:38.60#ibcon#read 6, iclass 27, count 0 2006.201.15:05:38.60#ibcon#end of sib2, iclass 27, count 0 2006.201.15:05:38.60#ibcon#*after write, iclass 27, count 0 2006.201.15:05:38.60#ibcon#*before return 0, iclass 27, count 0 2006.201.15:05:38.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:38.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:38.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.15:05:38.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.15:05:38.60$vck44/valo=3,564.99 2006.201.15:05:38.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.15:05:38.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.15:05:38.60#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:38.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:38.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:38.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:38.60#ibcon#enter wrdev, iclass 29, count 0 2006.201.15:05:38.60#ibcon#first serial, iclass 29, count 0 2006.201.15:05:38.60#ibcon#enter sib2, iclass 29, count 0 2006.201.15:05:38.60#ibcon#flushed, iclass 29, count 0 2006.201.15:05:38.60#ibcon#about to write, iclass 29, count 0 2006.201.15:05:38.60#ibcon#wrote, iclass 29, count 0 2006.201.15:05:38.60#ibcon#about to read 3, iclass 29, count 0 2006.201.15:05:38.62#ibcon#read 3, iclass 29, count 0 2006.201.15:05:38.62#ibcon#about to read 4, iclass 29, count 0 2006.201.15:05:38.62#ibcon#read 4, iclass 29, count 0 2006.201.15:05:38.62#ibcon#about to read 5, iclass 29, count 0 2006.201.15:05:38.62#ibcon#read 5, iclass 29, count 0 2006.201.15:05:38.62#ibcon#about to read 6, iclass 29, count 0 2006.201.15:05:38.62#ibcon#read 6, iclass 29, count 0 2006.201.15:05:38.62#ibcon#end of sib2, iclass 29, count 0 2006.201.15:05:38.62#ibcon#*mode == 0, iclass 29, count 0 2006.201.15:05:38.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.15:05:38.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:05:38.62#ibcon#*before write, iclass 29, count 0 2006.201.15:05:38.62#ibcon#enter sib2, iclass 29, count 0 2006.201.15:05:38.62#ibcon#flushed, iclass 29, count 0 2006.201.15:05:38.62#ibcon#about to write, iclass 29, count 0 2006.201.15:05:38.62#ibcon#wrote, iclass 29, count 0 2006.201.15:05:38.62#ibcon#about to read 3, iclass 29, count 0 2006.201.15:05:38.67#ibcon#read 3, iclass 29, count 0 2006.201.15:05:38.67#ibcon#about to read 4, iclass 29, count 0 2006.201.15:05:38.67#ibcon#read 4, iclass 29, count 0 2006.201.15:05:38.67#ibcon#about to read 5, iclass 29, count 0 2006.201.15:05:38.67#ibcon#read 5, iclass 29, count 0 2006.201.15:05:38.67#ibcon#about to read 6, iclass 29, count 0 2006.201.15:05:38.67#ibcon#read 6, iclass 29, count 0 2006.201.15:05:38.67#ibcon#end of sib2, iclass 29, count 0 2006.201.15:05:38.67#ibcon#*after write, iclass 29, count 0 2006.201.15:05:38.67#ibcon#*before return 0, iclass 29, count 0 2006.201.15:05:38.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:38.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:38.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.15:05:38.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.15:05:38.67$vck44/va=3,8 2006.201.15:05:38.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.15:05:38.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.15:05:38.67#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:38.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:38.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:38.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:38.72#ibcon#enter wrdev, iclass 31, count 2 2006.201.15:05:38.72#ibcon#first serial, iclass 31, count 2 2006.201.15:05:38.72#ibcon#enter sib2, iclass 31, count 2 2006.201.15:05:38.72#ibcon#flushed, iclass 31, count 2 2006.201.15:05:38.72#ibcon#about to write, iclass 31, count 2 2006.201.15:05:38.72#ibcon#wrote, iclass 31, count 2 2006.201.15:05:38.72#ibcon#about to read 3, iclass 31, count 2 2006.201.15:05:38.74#ibcon#read 3, iclass 31, count 2 2006.201.15:05:38.74#ibcon#about to read 4, iclass 31, count 2 2006.201.15:05:38.74#ibcon#read 4, iclass 31, count 2 2006.201.15:05:38.74#ibcon#about to read 5, iclass 31, count 2 2006.201.15:05:38.74#ibcon#read 5, iclass 31, count 2 2006.201.15:05:38.74#ibcon#about to read 6, iclass 31, count 2 2006.201.15:05:38.74#ibcon#read 6, iclass 31, count 2 2006.201.15:05:38.74#ibcon#end of sib2, iclass 31, count 2 2006.201.15:05:38.74#ibcon#*mode == 0, iclass 31, count 2 2006.201.15:05:38.74#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.15:05:38.74#ibcon#[25=AT03-08\r\n] 2006.201.15:05:38.74#ibcon#*before write, iclass 31, count 2 2006.201.15:05:38.74#ibcon#enter sib2, iclass 31, count 2 2006.201.15:05:38.74#ibcon#flushed, iclass 31, count 2 2006.201.15:05:38.74#ibcon#about to write, iclass 31, count 2 2006.201.15:05:38.74#ibcon#wrote, iclass 31, count 2 2006.201.15:05:38.74#ibcon#about to read 3, iclass 31, count 2 2006.201.15:05:38.77#ibcon#read 3, iclass 31, count 2 2006.201.15:05:38.77#ibcon#about to read 4, iclass 31, count 2 2006.201.15:05:38.77#ibcon#read 4, iclass 31, count 2 2006.201.15:05:38.77#ibcon#about to read 5, iclass 31, count 2 2006.201.15:05:38.77#ibcon#read 5, iclass 31, count 2 2006.201.15:05:38.77#ibcon#about to read 6, iclass 31, count 2 2006.201.15:05:38.77#ibcon#read 6, iclass 31, count 2 2006.201.15:05:38.77#ibcon#end of sib2, iclass 31, count 2 2006.201.15:05:38.77#ibcon#*after write, iclass 31, count 2 2006.201.15:05:38.77#ibcon#*before return 0, iclass 31, count 2 2006.201.15:05:38.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:38.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:38.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.15:05:38.77#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:38.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:38.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:38.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:38.89#ibcon#enter wrdev, iclass 31, count 0 2006.201.15:05:38.89#ibcon#first serial, iclass 31, count 0 2006.201.15:05:38.89#ibcon#enter sib2, iclass 31, count 0 2006.201.15:05:38.89#ibcon#flushed, iclass 31, count 0 2006.201.15:05:38.89#ibcon#about to write, iclass 31, count 0 2006.201.15:05:38.89#ibcon#wrote, iclass 31, count 0 2006.201.15:05:38.89#ibcon#about to read 3, iclass 31, count 0 2006.201.15:05:38.91#ibcon#read 3, iclass 31, count 0 2006.201.15:05:38.91#ibcon#about to read 4, iclass 31, count 0 2006.201.15:05:38.91#ibcon#read 4, iclass 31, count 0 2006.201.15:05:38.91#ibcon#about to read 5, iclass 31, count 0 2006.201.15:05:38.91#ibcon#read 5, iclass 31, count 0 2006.201.15:05:38.91#ibcon#about to read 6, iclass 31, count 0 2006.201.15:05:38.91#ibcon#read 6, iclass 31, count 0 2006.201.15:05:38.91#ibcon#end of sib2, iclass 31, count 0 2006.201.15:05:38.91#ibcon#*mode == 0, iclass 31, count 0 2006.201.15:05:38.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.15:05:38.91#ibcon#[25=USB\r\n] 2006.201.15:05:38.91#ibcon#*before write, iclass 31, count 0 2006.201.15:05:38.91#ibcon#enter sib2, iclass 31, count 0 2006.201.15:05:38.91#ibcon#flushed, iclass 31, count 0 2006.201.15:05:38.91#ibcon#about to write, iclass 31, count 0 2006.201.15:05:38.91#ibcon#wrote, iclass 31, count 0 2006.201.15:05:38.91#ibcon#about to read 3, iclass 31, count 0 2006.201.15:05:38.94#ibcon#read 3, iclass 31, count 0 2006.201.15:05:38.94#ibcon#about to read 4, iclass 31, count 0 2006.201.15:05:38.94#ibcon#read 4, iclass 31, count 0 2006.201.15:05:38.94#ibcon#about to read 5, iclass 31, count 0 2006.201.15:05:38.94#ibcon#read 5, iclass 31, count 0 2006.201.15:05:38.94#ibcon#about to read 6, iclass 31, count 0 2006.201.15:05:38.94#ibcon#read 6, iclass 31, count 0 2006.201.15:05:38.94#ibcon#end of sib2, iclass 31, count 0 2006.201.15:05:38.94#ibcon#*after write, iclass 31, count 0 2006.201.15:05:38.94#ibcon#*before return 0, iclass 31, count 0 2006.201.15:05:38.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:38.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:38.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.15:05:38.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.15:05:38.94$vck44/valo=4,624.99 2006.201.15:05:38.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.15:05:38.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.15:05:38.94#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:38.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:38.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:38.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:38.94#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:05:38.94#ibcon#first serial, iclass 33, count 0 2006.201.15:05:38.94#ibcon#enter sib2, iclass 33, count 0 2006.201.15:05:38.94#ibcon#flushed, iclass 33, count 0 2006.201.15:05:38.94#ibcon#about to write, iclass 33, count 0 2006.201.15:05:38.94#ibcon#wrote, iclass 33, count 0 2006.201.15:05:38.94#ibcon#about to read 3, iclass 33, count 0 2006.201.15:05:38.96#ibcon#read 3, iclass 33, count 0 2006.201.15:05:38.96#ibcon#about to read 4, iclass 33, count 0 2006.201.15:05:38.96#ibcon#read 4, iclass 33, count 0 2006.201.15:05:38.96#ibcon#about to read 5, iclass 33, count 0 2006.201.15:05:38.96#ibcon#read 5, iclass 33, count 0 2006.201.15:05:38.96#ibcon#about to read 6, iclass 33, count 0 2006.201.15:05:38.96#ibcon#read 6, iclass 33, count 0 2006.201.15:05:38.96#ibcon#end of sib2, iclass 33, count 0 2006.201.15:05:38.96#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:05:38.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:05:38.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:05:38.96#ibcon#*before write, iclass 33, count 0 2006.201.15:05:38.96#ibcon#enter sib2, iclass 33, count 0 2006.201.15:05:38.96#ibcon#flushed, iclass 33, count 0 2006.201.15:05:38.96#ibcon#about to write, iclass 33, count 0 2006.201.15:05:38.96#ibcon#wrote, iclass 33, count 0 2006.201.15:05:38.96#ibcon#about to read 3, iclass 33, count 0 2006.201.15:05:39.01#ibcon#read 3, iclass 33, count 0 2006.201.15:05:39.01#ibcon#about to read 4, iclass 33, count 0 2006.201.15:05:39.01#ibcon#read 4, iclass 33, count 0 2006.201.15:05:39.01#ibcon#about to read 5, iclass 33, count 0 2006.201.15:05:39.01#ibcon#read 5, iclass 33, count 0 2006.201.15:05:39.01#ibcon#about to read 6, iclass 33, count 0 2006.201.15:05:39.01#ibcon#read 6, iclass 33, count 0 2006.201.15:05:39.01#ibcon#end of sib2, iclass 33, count 0 2006.201.15:05:39.01#ibcon#*after write, iclass 33, count 0 2006.201.15:05:39.01#ibcon#*before return 0, iclass 33, count 0 2006.201.15:05:39.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:39.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:39.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:05:39.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:05:39.01$vck44/va=4,7 2006.201.15:05:39.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.15:05:39.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.15:05:39.01#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:39.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:39.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:39.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:39.06#ibcon#enter wrdev, iclass 35, count 2 2006.201.15:05:39.06#ibcon#first serial, iclass 35, count 2 2006.201.15:05:39.06#ibcon#enter sib2, iclass 35, count 2 2006.201.15:05:39.06#ibcon#flushed, iclass 35, count 2 2006.201.15:05:39.06#ibcon#about to write, iclass 35, count 2 2006.201.15:05:39.06#ibcon#wrote, iclass 35, count 2 2006.201.15:05:39.06#ibcon#about to read 3, iclass 35, count 2 2006.201.15:05:39.08#ibcon#read 3, iclass 35, count 2 2006.201.15:05:39.08#ibcon#about to read 4, iclass 35, count 2 2006.201.15:05:39.08#ibcon#read 4, iclass 35, count 2 2006.201.15:05:39.08#ibcon#about to read 5, iclass 35, count 2 2006.201.15:05:39.08#ibcon#read 5, iclass 35, count 2 2006.201.15:05:39.08#ibcon#about to read 6, iclass 35, count 2 2006.201.15:05:39.08#ibcon#read 6, iclass 35, count 2 2006.201.15:05:39.08#ibcon#end of sib2, iclass 35, count 2 2006.201.15:05:39.08#ibcon#*mode == 0, iclass 35, count 2 2006.201.15:05:39.08#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.15:05:39.08#ibcon#[25=AT04-07\r\n] 2006.201.15:05:39.08#ibcon#*before write, iclass 35, count 2 2006.201.15:05:39.08#ibcon#enter sib2, iclass 35, count 2 2006.201.15:05:39.08#ibcon#flushed, iclass 35, count 2 2006.201.15:05:39.08#ibcon#about to write, iclass 35, count 2 2006.201.15:05:39.08#ibcon#wrote, iclass 35, count 2 2006.201.15:05:39.08#ibcon#about to read 3, iclass 35, count 2 2006.201.15:05:39.11#ibcon#read 3, iclass 35, count 2 2006.201.15:05:39.11#ibcon#about to read 4, iclass 35, count 2 2006.201.15:05:39.11#ibcon#read 4, iclass 35, count 2 2006.201.15:05:39.11#ibcon#about to read 5, iclass 35, count 2 2006.201.15:05:39.11#ibcon#read 5, iclass 35, count 2 2006.201.15:05:39.11#ibcon#about to read 6, iclass 35, count 2 2006.201.15:05:39.11#ibcon#read 6, iclass 35, count 2 2006.201.15:05:39.11#ibcon#end of sib2, iclass 35, count 2 2006.201.15:05:39.11#ibcon#*after write, iclass 35, count 2 2006.201.15:05:39.11#ibcon#*before return 0, iclass 35, count 2 2006.201.15:05:39.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:39.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:39.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.15:05:39.11#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:39.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:39.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:39.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:39.23#ibcon#enter wrdev, iclass 35, count 0 2006.201.15:05:39.23#ibcon#first serial, iclass 35, count 0 2006.201.15:05:39.23#ibcon#enter sib2, iclass 35, count 0 2006.201.15:05:39.23#ibcon#flushed, iclass 35, count 0 2006.201.15:05:39.23#ibcon#about to write, iclass 35, count 0 2006.201.15:05:39.23#ibcon#wrote, iclass 35, count 0 2006.201.15:05:39.23#ibcon#about to read 3, iclass 35, count 0 2006.201.15:05:39.25#ibcon#read 3, iclass 35, count 0 2006.201.15:05:39.25#ibcon#about to read 4, iclass 35, count 0 2006.201.15:05:39.25#ibcon#read 4, iclass 35, count 0 2006.201.15:05:39.25#ibcon#about to read 5, iclass 35, count 0 2006.201.15:05:39.25#ibcon#read 5, iclass 35, count 0 2006.201.15:05:39.25#ibcon#about to read 6, iclass 35, count 0 2006.201.15:05:39.25#ibcon#read 6, iclass 35, count 0 2006.201.15:05:39.25#ibcon#end of sib2, iclass 35, count 0 2006.201.15:05:39.25#ibcon#*mode == 0, iclass 35, count 0 2006.201.15:05:39.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.15:05:39.25#ibcon#[25=USB\r\n] 2006.201.15:05:39.25#ibcon#*before write, iclass 35, count 0 2006.201.15:05:39.25#ibcon#enter sib2, iclass 35, count 0 2006.201.15:05:39.25#ibcon#flushed, iclass 35, count 0 2006.201.15:05:39.25#ibcon#about to write, iclass 35, count 0 2006.201.15:05:39.25#ibcon#wrote, iclass 35, count 0 2006.201.15:05:39.25#ibcon#about to read 3, iclass 35, count 0 2006.201.15:05:39.28#ibcon#read 3, iclass 35, count 0 2006.201.15:05:39.28#ibcon#about to read 4, iclass 35, count 0 2006.201.15:05:39.28#ibcon#read 4, iclass 35, count 0 2006.201.15:05:39.28#ibcon#about to read 5, iclass 35, count 0 2006.201.15:05:39.28#ibcon#read 5, iclass 35, count 0 2006.201.15:05:39.28#ibcon#about to read 6, iclass 35, count 0 2006.201.15:05:39.28#ibcon#read 6, iclass 35, count 0 2006.201.15:05:39.28#ibcon#end of sib2, iclass 35, count 0 2006.201.15:05:39.28#ibcon#*after write, iclass 35, count 0 2006.201.15:05:39.28#ibcon#*before return 0, iclass 35, count 0 2006.201.15:05:39.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:39.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:39.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.15:05:39.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.15:05:39.28$vck44/valo=5,734.99 2006.201.15:05:39.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.15:05:39.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.15:05:39.28#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:39.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:39.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:39.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:39.28#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:05:39.28#ibcon#first serial, iclass 37, count 0 2006.201.15:05:39.28#ibcon#enter sib2, iclass 37, count 0 2006.201.15:05:39.28#ibcon#flushed, iclass 37, count 0 2006.201.15:05:39.28#ibcon#about to write, iclass 37, count 0 2006.201.15:05:39.28#ibcon#wrote, iclass 37, count 0 2006.201.15:05:39.28#ibcon#about to read 3, iclass 37, count 0 2006.201.15:05:39.30#ibcon#read 3, iclass 37, count 0 2006.201.15:05:39.30#ibcon#about to read 4, iclass 37, count 0 2006.201.15:05:39.30#ibcon#read 4, iclass 37, count 0 2006.201.15:05:39.30#ibcon#about to read 5, iclass 37, count 0 2006.201.15:05:39.30#ibcon#read 5, iclass 37, count 0 2006.201.15:05:39.30#ibcon#about to read 6, iclass 37, count 0 2006.201.15:05:39.30#ibcon#read 6, iclass 37, count 0 2006.201.15:05:39.30#ibcon#end of sib2, iclass 37, count 0 2006.201.15:05:39.30#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:05:39.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:05:39.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:05:39.30#ibcon#*before write, iclass 37, count 0 2006.201.15:05:39.30#ibcon#enter sib2, iclass 37, count 0 2006.201.15:05:39.30#ibcon#flushed, iclass 37, count 0 2006.201.15:05:39.30#ibcon#about to write, iclass 37, count 0 2006.201.15:05:39.30#ibcon#wrote, iclass 37, count 0 2006.201.15:05:39.30#ibcon#about to read 3, iclass 37, count 0 2006.201.15:05:39.34#ibcon#read 3, iclass 37, count 0 2006.201.15:05:39.34#ibcon#about to read 4, iclass 37, count 0 2006.201.15:05:39.34#ibcon#read 4, iclass 37, count 0 2006.201.15:05:39.34#ibcon#about to read 5, iclass 37, count 0 2006.201.15:05:39.34#ibcon#read 5, iclass 37, count 0 2006.201.15:05:39.34#ibcon#about to read 6, iclass 37, count 0 2006.201.15:05:39.34#ibcon#read 6, iclass 37, count 0 2006.201.15:05:39.34#ibcon#end of sib2, iclass 37, count 0 2006.201.15:05:39.34#ibcon#*after write, iclass 37, count 0 2006.201.15:05:39.34#ibcon#*before return 0, iclass 37, count 0 2006.201.15:05:39.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:39.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:39.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:05:39.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:05:39.34$vck44/va=5,4 2006.201.15:05:39.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.15:05:39.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.15:05:39.34#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:39.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:39.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:39.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:39.40#ibcon#enter wrdev, iclass 39, count 2 2006.201.15:05:39.40#ibcon#first serial, iclass 39, count 2 2006.201.15:05:39.40#ibcon#enter sib2, iclass 39, count 2 2006.201.15:05:39.40#ibcon#flushed, iclass 39, count 2 2006.201.15:05:39.40#ibcon#about to write, iclass 39, count 2 2006.201.15:05:39.40#ibcon#wrote, iclass 39, count 2 2006.201.15:05:39.40#ibcon#about to read 3, iclass 39, count 2 2006.201.15:05:39.42#ibcon#read 3, iclass 39, count 2 2006.201.15:05:39.42#ibcon#about to read 4, iclass 39, count 2 2006.201.15:05:39.42#ibcon#read 4, iclass 39, count 2 2006.201.15:05:39.42#ibcon#about to read 5, iclass 39, count 2 2006.201.15:05:39.42#ibcon#read 5, iclass 39, count 2 2006.201.15:05:39.42#ibcon#about to read 6, iclass 39, count 2 2006.201.15:05:39.42#ibcon#read 6, iclass 39, count 2 2006.201.15:05:39.42#ibcon#end of sib2, iclass 39, count 2 2006.201.15:05:39.42#ibcon#*mode == 0, iclass 39, count 2 2006.201.15:05:39.42#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.15:05:39.42#ibcon#[25=AT05-04\r\n] 2006.201.15:05:39.42#ibcon#*before write, iclass 39, count 2 2006.201.15:05:39.42#ibcon#enter sib2, iclass 39, count 2 2006.201.15:05:39.42#ibcon#flushed, iclass 39, count 2 2006.201.15:05:39.42#ibcon#about to write, iclass 39, count 2 2006.201.15:05:39.42#ibcon#wrote, iclass 39, count 2 2006.201.15:05:39.42#ibcon#about to read 3, iclass 39, count 2 2006.201.15:05:39.45#ibcon#read 3, iclass 39, count 2 2006.201.15:05:39.45#ibcon#about to read 4, iclass 39, count 2 2006.201.15:05:39.45#ibcon#read 4, iclass 39, count 2 2006.201.15:05:39.45#ibcon#about to read 5, iclass 39, count 2 2006.201.15:05:39.45#ibcon#read 5, iclass 39, count 2 2006.201.15:05:39.45#ibcon#about to read 6, iclass 39, count 2 2006.201.15:05:39.45#ibcon#read 6, iclass 39, count 2 2006.201.15:05:39.45#ibcon#end of sib2, iclass 39, count 2 2006.201.15:05:39.45#ibcon#*after write, iclass 39, count 2 2006.201.15:05:39.45#ibcon#*before return 0, iclass 39, count 2 2006.201.15:05:39.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:39.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:39.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.15:05:39.45#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:39.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:39.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:39.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:39.57#ibcon#enter wrdev, iclass 39, count 0 2006.201.15:05:39.57#ibcon#first serial, iclass 39, count 0 2006.201.15:05:39.57#ibcon#enter sib2, iclass 39, count 0 2006.201.15:05:39.57#ibcon#flushed, iclass 39, count 0 2006.201.15:05:39.57#ibcon#about to write, iclass 39, count 0 2006.201.15:05:39.57#ibcon#wrote, iclass 39, count 0 2006.201.15:05:39.57#ibcon#about to read 3, iclass 39, count 0 2006.201.15:05:39.59#ibcon#read 3, iclass 39, count 0 2006.201.15:05:39.59#ibcon#about to read 4, iclass 39, count 0 2006.201.15:05:39.59#ibcon#read 4, iclass 39, count 0 2006.201.15:05:39.59#ibcon#about to read 5, iclass 39, count 0 2006.201.15:05:39.59#ibcon#read 5, iclass 39, count 0 2006.201.15:05:39.59#ibcon#about to read 6, iclass 39, count 0 2006.201.15:05:39.59#ibcon#read 6, iclass 39, count 0 2006.201.15:05:39.59#ibcon#end of sib2, iclass 39, count 0 2006.201.15:05:39.59#ibcon#*mode == 0, iclass 39, count 0 2006.201.15:05:39.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.15:05:39.59#ibcon#[25=USB\r\n] 2006.201.15:05:39.59#ibcon#*before write, iclass 39, count 0 2006.201.15:05:39.59#ibcon#enter sib2, iclass 39, count 0 2006.201.15:05:39.59#ibcon#flushed, iclass 39, count 0 2006.201.15:05:39.59#ibcon#about to write, iclass 39, count 0 2006.201.15:05:39.59#ibcon#wrote, iclass 39, count 0 2006.201.15:05:39.59#ibcon#about to read 3, iclass 39, count 0 2006.201.15:05:39.62#ibcon#read 3, iclass 39, count 0 2006.201.15:05:39.62#ibcon#about to read 4, iclass 39, count 0 2006.201.15:05:39.62#ibcon#read 4, iclass 39, count 0 2006.201.15:05:39.62#ibcon#about to read 5, iclass 39, count 0 2006.201.15:05:39.62#ibcon#read 5, iclass 39, count 0 2006.201.15:05:39.62#ibcon#about to read 6, iclass 39, count 0 2006.201.15:05:39.62#ibcon#read 6, iclass 39, count 0 2006.201.15:05:39.62#ibcon#end of sib2, iclass 39, count 0 2006.201.15:05:39.62#ibcon#*after write, iclass 39, count 0 2006.201.15:05:39.62#ibcon#*before return 0, iclass 39, count 0 2006.201.15:05:39.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:39.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:39.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.15:05:39.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.15:05:39.62$vck44/valo=6,814.99 2006.201.15:05:39.62#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.15:05:39.62#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.15:05:39.62#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:39.62#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:39.62#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:39.62#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:39.62#ibcon#enter wrdev, iclass 2, count 0 2006.201.15:05:39.62#ibcon#first serial, iclass 2, count 0 2006.201.15:05:39.62#ibcon#enter sib2, iclass 2, count 0 2006.201.15:05:39.62#ibcon#flushed, iclass 2, count 0 2006.201.15:05:39.62#ibcon#about to write, iclass 2, count 0 2006.201.15:05:39.62#ibcon#wrote, iclass 2, count 0 2006.201.15:05:39.62#ibcon#about to read 3, iclass 2, count 0 2006.201.15:05:39.64#ibcon#read 3, iclass 2, count 0 2006.201.15:05:39.64#ibcon#about to read 4, iclass 2, count 0 2006.201.15:05:39.64#ibcon#read 4, iclass 2, count 0 2006.201.15:05:39.64#ibcon#about to read 5, iclass 2, count 0 2006.201.15:05:39.64#ibcon#read 5, iclass 2, count 0 2006.201.15:05:39.64#ibcon#about to read 6, iclass 2, count 0 2006.201.15:05:39.64#ibcon#read 6, iclass 2, count 0 2006.201.15:05:39.64#ibcon#end of sib2, iclass 2, count 0 2006.201.15:05:39.64#ibcon#*mode == 0, iclass 2, count 0 2006.201.15:05:39.64#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.15:05:39.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:05:39.64#ibcon#*before write, iclass 2, count 0 2006.201.15:05:39.64#ibcon#enter sib2, iclass 2, count 0 2006.201.15:05:39.64#ibcon#flushed, iclass 2, count 0 2006.201.15:05:39.64#ibcon#about to write, iclass 2, count 0 2006.201.15:05:39.64#ibcon#wrote, iclass 2, count 0 2006.201.15:05:39.64#ibcon#about to read 3, iclass 2, count 0 2006.201.15:05:39.69#ibcon#read 3, iclass 2, count 0 2006.201.15:05:39.69#ibcon#about to read 4, iclass 2, count 0 2006.201.15:05:39.69#ibcon#read 4, iclass 2, count 0 2006.201.15:05:39.69#ibcon#about to read 5, iclass 2, count 0 2006.201.15:05:39.69#ibcon#read 5, iclass 2, count 0 2006.201.15:05:39.69#ibcon#about to read 6, iclass 2, count 0 2006.201.15:05:39.69#ibcon#read 6, iclass 2, count 0 2006.201.15:05:39.69#ibcon#end of sib2, iclass 2, count 0 2006.201.15:05:39.69#ibcon#*after write, iclass 2, count 0 2006.201.15:05:39.69#ibcon#*before return 0, iclass 2, count 0 2006.201.15:05:39.69#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:39.69#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:39.69#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.15:05:39.69#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.15:05:39.69$vck44/va=6,5 2006.201.15:05:39.69#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.15:05:39.69#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.15:05:39.69#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:39.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:39.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:39.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:39.74#ibcon#enter wrdev, iclass 5, count 2 2006.201.15:05:39.74#ibcon#first serial, iclass 5, count 2 2006.201.15:05:39.74#ibcon#enter sib2, iclass 5, count 2 2006.201.15:05:39.74#ibcon#flushed, iclass 5, count 2 2006.201.15:05:39.74#ibcon#about to write, iclass 5, count 2 2006.201.15:05:39.74#ibcon#wrote, iclass 5, count 2 2006.201.15:05:39.74#ibcon#about to read 3, iclass 5, count 2 2006.201.15:05:39.76#ibcon#read 3, iclass 5, count 2 2006.201.15:05:39.76#ibcon#about to read 4, iclass 5, count 2 2006.201.15:05:39.76#ibcon#read 4, iclass 5, count 2 2006.201.15:05:39.76#ibcon#about to read 5, iclass 5, count 2 2006.201.15:05:39.76#ibcon#read 5, iclass 5, count 2 2006.201.15:05:39.76#ibcon#about to read 6, iclass 5, count 2 2006.201.15:05:39.76#ibcon#read 6, iclass 5, count 2 2006.201.15:05:39.76#ibcon#end of sib2, iclass 5, count 2 2006.201.15:05:39.76#ibcon#*mode == 0, iclass 5, count 2 2006.201.15:05:39.76#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.15:05:39.76#ibcon#[25=AT06-05\r\n] 2006.201.15:05:39.76#ibcon#*before write, iclass 5, count 2 2006.201.15:05:39.76#ibcon#enter sib2, iclass 5, count 2 2006.201.15:05:39.76#ibcon#flushed, iclass 5, count 2 2006.201.15:05:39.76#ibcon#about to write, iclass 5, count 2 2006.201.15:05:39.76#ibcon#wrote, iclass 5, count 2 2006.201.15:05:39.76#ibcon#about to read 3, iclass 5, count 2 2006.201.15:05:39.79#ibcon#read 3, iclass 5, count 2 2006.201.15:05:39.79#ibcon#about to read 4, iclass 5, count 2 2006.201.15:05:39.79#ibcon#read 4, iclass 5, count 2 2006.201.15:05:39.79#ibcon#about to read 5, iclass 5, count 2 2006.201.15:05:39.79#ibcon#read 5, iclass 5, count 2 2006.201.15:05:39.79#ibcon#about to read 6, iclass 5, count 2 2006.201.15:05:39.79#ibcon#read 6, iclass 5, count 2 2006.201.15:05:39.79#ibcon#end of sib2, iclass 5, count 2 2006.201.15:05:39.79#ibcon#*after write, iclass 5, count 2 2006.201.15:05:39.79#ibcon#*before return 0, iclass 5, count 2 2006.201.15:05:39.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:39.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:39.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.15:05:39.79#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:39.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:39.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:39.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:39.91#ibcon#enter wrdev, iclass 5, count 0 2006.201.15:05:39.91#ibcon#first serial, iclass 5, count 0 2006.201.15:05:39.91#ibcon#enter sib2, iclass 5, count 0 2006.201.15:05:39.91#ibcon#flushed, iclass 5, count 0 2006.201.15:05:39.91#ibcon#about to write, iclass 5, count 0 2006.201.15:05:39.91#ibcon#wrote, iclass 5, count 0 2006.201.15:05:39.91#ibcon#about to read 3, iclass 5, count 0 2006.201.15:05:39.93#ibcon#read 3, iclass 5, count 0 2006.201.15:05:39.93#ibcon#about to read 4, iclass 5, count 0 2006.201.15:05:39.93#ibcon#read 4, iclass 5, count 0 2006.201.15:05:39.93#ibcon#about to read 5, iclass 5, count 0 2006.201.15:05:39.93#ibcon#read 5, iclass 5, count 0 2006.201.15:05:39.93#ibcon#about to read 6, iclass 5, count 0 2006.201.15:05:39.93#ibcon#read 6, iclass 5, count 0 2006.201.15:05:39.93#ibcon#end of sib2, iclass 5, count 0 2006.201.15:05:39.93#ibcon#*mode == 0, iclass 5, count 0 2006.201.15:05:39.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.15:05:39.93#ibcon#[25=USB\r\n] 2006.201.15:05:39.93#ibcon#*before write, iclass 5, count 0 2006.201.15:05:39.93#ibcon#enter sib2, iclass 5, count 0 2006.201.15:05:39.93#ibcon#flushed, iclass 5, count 0 2006.201.15:05:39.93#ibcon#about to write, iclass 5, count 0 2006.201.15:05:39.93#ibcon#wrote, iclass 5, count 0 2006.201.15:05:39.93#ibcon#about to read 3, iclass 5, count 0 2006.201.15:05:39.96#ibcon#read 3, iclass 5, count 0 2006.201.15:05:39.96#ibcon#about to read 4, iclass 5, count 0 2006.201.15:05:39.96#ibcon#read 4, iclass 5, count 0 2006.201.15:05:39.96#ibcon#about to read 5, iclass 5, count 0 2006.201.15:05:39.96#ibcon#read 5, iclass 5, count 0 2006.201.15:05:39.96#ibcon#about to read 6, iclass 5, count 0 2006.201.15:05:39.96#ibcon#read 6, iclass 5, count 0 2006.201.15:05:39.96#ibcon#end of sib2, iclass 5, count 0 2006.201.15:05:39.96#ibcon#*after write, iclass 5, count 0 2006.201.15:05:39.96#ibcon#*before return 0, iclass 5, count 0 2006.201.15:05:39.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:39.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:39.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.15:05:39.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.15:05:39.96$vck44/valo=7,864.99 2006.201.15:05:39.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.15:05:39.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.15:05:39.96#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:39.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:39.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:39.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:39.96#ibcon#enter wrdev, iclass 7, count 0 2006.201.15:05:39.96#ibcon#first serial, iclass 7, count 0 2006.201.15:05:39.96#ibcon#enter sib2, iclass 7, count 0 2006.201.15:05:39.96#ibcon#flushed, iclass 7, count 0 2006.201.15:05:39.96#ibcon#about to write, iclass 7, count 0 2006.201.15:05:39.96#ibcon#wrote, iclass 7, count 0 2006.201.15:05:39.96#ibcon#about to read 3, iclass 7, count 0 2006.201.15:05:39.98#ibcon#read 3, iclass 7, count 0 2006.201.15:05:39.98#ibcon#about to read 4, iclass 7, count 0 2006.201.15:05:39.98#ibcon#read 4, iclass 7, count 0 2006.201.15:05:39.98#ibcon#about to read 5, iclass 7, count 0 2006.201.15:05:39.98#ibcon#read 5, iclass 7, count 0 2006.201.15:05:39.98#ibcon#about to read 6, iclass 7, count 0 2006.201.15:05:39.98#ibcon#read 6, iclass 7, count 0 2006.201.15:05:39.98#ibcon#end of sib2, iclass 7, count 0 2006.201.15:05:39.98#ibcon#*mode == 0, iclass 7, count 0 2006.201.15:05:39.98#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.15:05:39.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:05:39.98#ibcon#*before write, iclass 7, count 0 2006.201.15:05:39.98#ibcon#enter sib2, iclass 7, count 0 2006.201.15:05:39.98#ibcon#flushed, iclass 7, count 0 2006.201.15:05:39.98#ibcon#about to write, iclass 7, count 0 2006.201.15:05:39.98#ibcon#wrote, iclass 7, count 0 2006.201.15:05:39.98#ibcon#about to read 3, iclass 7, count 0 2006.201.15:05:40.03#ibcon#read 3, iclass 7, count 0 2006.201.15:05:40.03#ibcon#about to read 4, iclass 7, count 0 2006.201.15:05:40.03#ibcon#read 4, iclass 7, count 0 2006.201.15:05:40.03#ibcon#about to read 5, iclass 7, count 0 2006.201.15:05:40.03#ibcon#read 5, iclass 7, count 0 2006.201.15:05:40.03#ibcon#about to read 6, iclass 7, count 0 2006.201.15:05:40.03#ibcon#read 6, iclass 7, count 0 2006.201.15:05:40.03#ibcon#end of sib2, iclass 7, count 0 2006.201.15:05:40.03#ibcon#*after write, iclass 7, count 0 2006.201.15:05:40.03#ibcon#*before return 0, iclass 7, count 0 2006.201.15:05:40.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:40.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:40.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.15:05:40.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.15:05:40.03$vck44/va=7,5 2006.201.15:05:40.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.15:05:40.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.15:05:40.03#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:40.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:40.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:40.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:40.08#ibcon#enter wrdev, iclass 11, count 2 2006.201.15:05:40.08#ibcon#first serial, iclass 11, count 2 2006.201.15:05:40.08#ibcon#enter sib2, iclass 11, count 2 2006.201.15:05:40.08#ibcon#flushed, iclass 11, count 2 2006.201.15:05:40.08#ibcon#about to write, iclass 11, count 2 2006.201.15:05:40.08#ibcon#wrote, iclass 11, count 2 2006.201.15:05:40.08#ibcon#about to read 3, iclass 11, count 2 2006.201.15:05:40.10#ibcon#read 3, iclass 11, count 2 2006.201.15:05:40.10#ibcon#about to read 4, iclass 11, count 2 2006.201.15:05:40.10#ibcon#read 4, iclass 11, count 2 2006.201.15:05:40.10#ibcon#about to read 5, iclass 11, count 2 2006.201.15:05:40.10#ibcon#read 5, iclass 11, count 2 2006.201.15:05:40.10#ibcon#about to read 6, iclass 11, count 2 2006.201.15:05:40.10#ibcon#read 6, iclass 11, count 2 2006.201.15:05:40.10#ibcon#end of sib2, iclass 11, count 2 2006.201.15:05:40.10#ibcon#*mode == 0, iclass 11, count 2 2006.201.15:05:40.10#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.15:05:40.10#ibcon#[25=AT07-05\r\n] 2006.201.15:05:40.10#ibcon#*before write, iclass 11, count 2 2006.201.15:05:40.10#ibcon#enter sib2, iclass 11, count 2 2006.201.15:05:40.10#ibcon#flushed, iclass 11, count 2 2006.201.15:05:40.10#ibcon#about to write, iclass 11, count 2 2006.201.15:05:40.10#ibcon#wrote, iclass 11, count 2 2006.201.15:05:40.10#ibcon#about to read 3, iclass 11, count 2 2006.201.15:05:40.13#ibcon#read 3, iclass 11, count 2 2006.201.15:05:40.13#ibcon#about to read 4, iclass 11, count 2 2006.201.15:05:40.13#ibcon#read 4, iclass 11, count 2 2006.201.15:05:40.13#ibcon#about to read 5, iclass 11, count 2 2006.201.15:05:40.13#ibcon#read 5, iclass 11, count 2 2006.201.15:05:40.13#ibcon#about to read 6, iclass 11, count 2 2006.201.15:05:40.13#ibcon#read 6, iclass 11, count 2 2006.201.15:05:40.13#ibcon#end of sib2, iclass 11, count 2 2006.201.15:05:40.13#ibcon#*after write, iclass 11, count 2 2006.201.15:05:40.13#ibcon#*before return 0, iclass 11, count 2 2006.201.15:05:40.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:40.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:40.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.15:05:40.13#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:40.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:40.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:40.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:40.25#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:05:40.25#ibcon#first serial, iclass 11, count 0 2006.201.15:05:40.25#ibcon#enter sib2, iclass 11, count 0 2006.201.15:05:40.25#ibcon#flushed, iclass 11, count 0 2006.201.15:05:40.25#ibcon#about to write, iclass 11, count 0 2006.201.15:05:40.25#ibcon#wrote, iclass 11, count 0 2006.201.15:05:40.25#ibcon#about to read 3, iclass 11, count 0 2006.201.15:05:40.27#ibcon#read 3, iclass 11, count 0 2006.201.15:05:40.27#ibcon#about to read 4, iclass 11, count 0 2006.201.15:05:40.27#ibcon#read 4, iclass 11, count 0 2006.201.15:05:40.27#ibcon#about to read 5, iclass 11, count 0 2006.201.15:05:40.27#ibcon#read 5, iclass 11, count 0 2006.201.15:05:40.27#ibcon#about to read 6, iclass 11, count 0 2006.201.15:05:40.27#ibcon#read 6, iclass 11, count 0 2006.201.15:05:40.27#ibcon#end of sib2, iclass 11, count 0 2006.201.15:05:40.27#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:05:40.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:05:40.27#ibcon#[25=USB\r\n] 2006.201.15:05:40.27#ibcon#*before write, iclass 11, count 0 2006.201.15:05:40.27#ibcon#enter sib2, iclass 11, count 0 2006.201.15:05:40.27#ibcon#flushed, iclass 11, count 0 2006.201.15:05:40.27#ibcon#about to write, iclass 11, count 0 2006.201.15:05:40.27#ibcon#wrote, iclass 11, count 0 2006.201.15:05:40.27#ibcon#about to read 3, iclass 11, count 0 2006.201.15:05:40.30#ibcon#read 3, iclass 11, count 0 2006.201.15:05:40.30#ibcon#about to read 4, iclass 11, count 0 2006.201.15:05:40.30#ibcon#read 4, iclass 11, count 0 2006.201.15:05:40.30#ibcon#about to read 5, iclass 11, count 0 2006.201.15:05:40.30#ibcon#read 5, iclass 11, count 0 2006.201.15:05:40.30#ibcon#about to read 6, iclass 11, count 0 2006.201.15:05:40.30#ibcon#read 6, iclass 11, count 0 2006.201.15:05:40.30#ibcon#end of sib2, iclass 11, count 0 2006.201.15:05:40.30#ibcon#*after write, iclass 11, count 0 2006.201.15:05:40.30#ibcon#*before return 0, iclass 11, count 0 2006.201.15:05:40.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:40.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:40.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:05:40.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:05:40.30$vck44/valo=8,884.99 2006.201.15:05:40.30#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.15:05:40.30#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.15:05:40.30#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:40.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:40.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:40.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:40.30#ibcon#enter wrdev, iclass 13, count 0 2006.201.15:05:40.30#ibcon#first serial, iclass 13, count 0 2006.201.15:05:40.30#ibcon#enter sib2, iclass 13, count 0 2006.201.15:05:40.30#ibcon#flushed, iclass 13, count 0 2006.201.15:05:40.30#ibcon#about to write, iclass 13, count 0 2006.201.15:05:40.30#ibcon#wrote, iclass 13, count 0 2006.201.15:05:40.30#ibcon#about to read 3, iclass 13, count 0 2006.201.15:05:40.32#ibcon#read 3, iclass 13, count 0 2006.201.15:05:40.32#ibcon#about to read 4, iclass 13, count 0 2006.201.15:05:40.32#ibcon#read 4, iclass 13, count 0 2006.201.15:05:40.32#ibcon#about to read 5, iclass 13, count 0 2006.201.15:05:40.32#ibcon#read 5, iclass 13, count 0 2006.201.15:05:40.32#ibcon#about to read 6, iclass 13, count 0 2006.201.15:05:40.32#ibcon#read 6, iclass 13, count 0 2006.201.15:05:40.32#ibcon#end of sib2, iclass 13, count 0 2006.201.15:05:40.32#ibcon#*mode == 0, iclass 13, count 0 2006.201.15:05:40.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.15:05:40.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:05:40.32#ibcon#*before write, iclass 13, count 0 2006.201.15:05:40.32#ibcon#enter sib2, iclass 13, count 0 2006.201.15:05:40.32#ibcon#flushed, iclass 13, count 0 2006.201.15:05:40.32#ibcon#about to write, iclass 13, count 0 2006.201.15:05:40.32#ibcon#wrote, iclass 13, count 0 2006.201.15:05:40.32#ibcon#about to read 3, iclass 13, count 0 2006.201.15:05:40.36#ibcon#read 3, iclass 13, count 0 2006.201.15:05:40.36#ibcon#about to read 4, iclass 13, count 0 2006.201.15:05:40.36#ibcon#read 4, iclass 13, count 0 2006.201.15:05:40.36#ibcon#about to read 5, iclass 13, count 0 2006.201.15:05:40.36#ibcon#read 5, iclass 13, count 0 2006.201.15:05:40.36#ibcon#about to read 6, iclass 13, count 0 2006.201.15:05:40.36#ibcon#read 6, iclass 13, count 0 2006.201.15:05:40.36#ibcon#end of sib2, iclass 13, count 0 2006.201.15:05:40.36#ibcon#*after write, iclass 13, count 0 2006.201.15:05:40.36#ibcon#*before return 0, iclass 13, count 0 2006.201.15:05:40.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:40.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:40.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.15:05:40.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.15:05:40.36$vck44/va=8,4 2006.201.15:05:40.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.15:05:40.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.15:05:40.36#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:40.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:05:40.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:05:40.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:05:40.42#ibcon#enter wrdev, iclass 15, count 2 2006.201.15:05:40.42#ibcon#first serial, iclass 15, count 2 2006.201.15:05:40.42#ibcon#enter sib2, iclass 15, count 2 2006.201.15:05:40.42#ibcon#flushed, iclass 15, count 2 2006.201.15:05:40.42#ibcon#about to write, iclass 15, count 2 2006.201.15:05:40.42#ibcon#wrote, iclass 15, count 2 2006.201.15:05:40.42#ibcon#about to read 3, iclass 15, count 2 2006.201.15:05:40.44#ibcon#read 3, iclass 15, count 2 2006.201.15:05:40.44#ibcon#about to read 4, iclass 15, count 2 2006.201.15:05:40.44#ibcon#read 4, iclass 15, count 2 2006.201.15:05:40.44#ibcon#about to read 5, iclass 15, count 2 2006.201.15:05:40.44#ibcon#read 5, iclass 15, count 2 2006.201.15:05:40.44#ibcon#about to read 6, iclass 15, count 2 2006.201.15:05:40.44#ibcon#read 6, iclass 15, count 2 2006.201.15:05:40.44#ibcon#end of sib2, iclass 15, count 2 2006.201.15:05:40.44#ibcon#*mode == 0, iclass 15, count 2 2006.201.15:05:40.44#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.15:05:40.44#ibcon#[25=AT08-04\r\n] 2006.201.15:05:40.44#ibcon#*before write, iclass 15, count 2 2006.201.15:05:40.44#ibcon#enter sib2, iclass 15, count 2 2006.201.15:05:40.44#ibcon#flushed, iclass 15, count 2 2006.201.15:05:40.44#ibcon#about to write, iclass 15, count 2 2006.201.15:05:40.44#ibcon#wrote, iclass 15, count 2 2006.201.15:05:40.44#ibcon#about to read 3, iclass 15, count 2 2006.201.15:05:40.47#ibcon#read 3, iclass 15, count 2 2006.201.15:05:40.47#ibcon#about to read 4, iclass 15, count 2 2006.201.15:05:40.47#ibcon#read 4, iclass 15, count 2 2006.201.15:05:40.47#ibcon#about to read 5, iclass 15, count 2 2006.201.15:05:40.47#ibcon#read 5, iclass 15, count 2 2006.201.15:05:40.47#ibcon#about to read 6, iclass 15, count 2 2006.201.15:05:40.47#ibcon#read 6, iclass 15, count 2 2006.201.15:05:40.47#ibcon#end of sib2, iclass 15, count 2 2006.201.15:05:40.47#ibcon#*after write, iclass 15, count 2 2006.201.15:05:40.47#ibcon#*before return 0, iclass 15, count 2 2006.201.15:05:40.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:05:40.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:05:40.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.15:05:40.47#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:40.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:05:40.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:05:40.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:05:40.59#ibcon#enter wrdev, iclass 15, count 0 2006.201.15:05:40.59#ibcon#first serial, iclass 15, count 0 2006.201.15:05:40.59#ibcon#enter sib2, iclass 15, count 0 2006.201.15:05:40.59#ibcon#flushed, iclass 15, count 0 2006.201.15:05:40.59#ibcon#about to write, iclass 15, count 0 2006.201.15:05:40.59#ibcon#wrote, iclass 15, count 0 2006.201.15:05:40.59#ibcon#about to read 3, iclass 15, count 0 2006.201.15:05:40.61#ibcon#read 3, iclass 15, count 0 2006.201.15:05:40.61#ibcon#about to read 4, iclass 15, count 0 2006.201.15:05:40.61#ibcon#read 4, iclass 15, count 0 2006.201.15:05:40.61#ibcon#about to read 5, iclass 15, count 0 2006.201.15:05:40.61#ibcon#read 5, iclass 15, count 0 2006.201.15:05:40.61#ibcon#about to read 6, iclass 15, count 0 2006.201.15:05:40.61#ibcon#read 6, iclass 15, count 0 2006.201.15:05:40.61#ibcon#end of sib2, iclass 15, count 0 2006.201.15:05:40.61#ibcon#*mode == 0, iclass 15, count 0 2006.201.15:05:40.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.15:05:40.61#ibcon#[25=USB\r\n] 2006.201.15:05:40.61#ibcon#*before write, iclass 15, count 0 2006.201.15:05:40.61#ibcon#enter sib2, iclass 15, count 0 2006.201.15:05:40.61#ibcon#flushed, iclass 15, count 0 2006.201.15:05:40.61#ibcon#about to write, iclass 15, count 0 2006.201.15:05:40.61#ibcon#wrote, iclass 15, count 0 2006.201.15:05:40.61#ibcon#about to read 3, iclass 15, count 0 2006.201.15:05:40.64#ibcon#read 3, iclass 15, count 0 2006.201.15:05:40.64#ibcon#about to read 4, iclass 15, count 0 2006.201.15:05:40.64#ibcon#read 4, iclass 15, count 0 2006.201.15:05:40.64#ibcon#about to read 5, iclass 15, count 0 2006.201.15:05:40.64#ibcon#read 5, iclass 15, count 0 2006.201.15:05:40.64#ibcon#about to read 6, iclass 15, count 0 2006.201.15:05:40.64#ibcon#read 6, iclass 15, count 0 2006.201.15:05:40.64#ibcon#end of sib2, iclass 15, count 0 2006.201.15:05:40.64#ibcon#*after write, iclass 15, count 0 2006.201.15:05:40.64#ibcon#*before return 0, iclass 15, count 0 2006.201.15:05:40.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:05:40.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:05:40.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.15:05:40.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.15:05:40.64$vck44/vblo=1,629.99 2006.201.15:05:40.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.15:05:40.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.15:05:40.64#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:40.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:05:40.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:05:40.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:05:40.64#ibcon#enter wrdev, iclass 17, count 0 2006.201.15:05:40.64#ibcon#first serial, iclass 17, count 0 2006.201.15:05:40.64#ibcon#enter sib2, iclass 17, count 0 2006.201.15:05:40.64#ibcon#flushed, iclass 17, count 0 2006.201.15:05:40.64#ibcon#about to write, iclass 17, count 0 2006.201.15:05:40.64#ibcon#wrote, iclass 17, count 0 2006.201.15:05:40.64#ibcon#about to read 3, iclass 17, count 0 2006.201.15:05:40.66#ibcon#read 3, iclass 17, count 0 2006.201.15:05:40.66#ibcon#about to read 4, iclass 17, count 0 2006.201.15:05:40.66#ibcon#read 4, iclass 17, count 0 2006.201.15:05:40.66#ibcon#about to read 5, iclass 17, count 0 2006.201.15:05:40.66#ibcon#read 5, iclass 17, count 0 2006.201.15:05:40.66#ibcon#about to read 6, iclass 17, count 0 2006.201.15:05:40.66#ibcon#read 6, iclass 17, count 0 2006.201.15:05:40.66#ibcon#end of sib2, iclass 17, count 0 2006.201.15:05:40.66#ibcon#*mode == 0, iclass 17, count 0 2006.201.15:05:40.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.15:05:40.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:05:40.66#ibcon#*before write, iclass 17, count 0 2006.201.15:05:40.66#ibcon#enter sib2, iclass 17, count 0 2006.201.15:05:40.66#ibcon#flushed, iclass 17, count 0 2006.201.15:05:40.66#ibcon#about to write, iclass 17, count 0 2006.201.15:05:40.66#ibcon#wrote, iclass 17, count 0 2006.201.15:05:40.66#ibcon#about to read 3, iclass 17, count 0 2006.201.15:05:40.71#ibcon#read 3, iclass 17, count 0 2006.201.15:05:40.71#ibcon#about to read 4, iclass 17, count 0 2006.201.15:05:40.71#ibcon#read 4, iclass 17, count 0 2006.201.15:05:40.71#ibcon#about to read 5, iclass 17, count 0 2006.201.15:05:40.71#ibcon#read 5, iclass 17, count 0 2006.201.15:05:40.71#ibcon#about to read 6, iclass 17, count 0 2006.201.15:05:40.71#ibcon#read 6, iclass 17, count 0 2006.201.15:05:40.71#ibcon#end of sib2, iclass 17, count 0 2006.201.15:05:40.71#ibcon#*after write, iclass 17, count 0 2006.201.15:05:40.71#ibcon#*before return 0, iclass 17, count 0 2006.201.15:05:40.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:05:40.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:05:40.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.15:05:40.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.15:05:40.71$vck44/vb=1,4 2006.201.15:05:40.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.15:05:40.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.15:05:40.71#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:40.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:05:40.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:05:40.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:05:40.71#ibcon#enter wrdev, iclass 19, count 2 2006.201.15:05:40.71#ibcon#first serial, iclass 19, count 2 2006.201.15:05:40.71#ibcon#enter sib2, iclass 19, count 2 2006.201.15:05:40.71#ibcon#flushed, iclass 19, count 2 2006.201.15:05:40.71#ibcon#about to write, iclass 19, count 2 2006.201.15:05:40.71#ibcon#wrote, iclass 19, count 2 2006.201.15:05:40.71#ibcon#about to read 3, iclass 19, count 2 2006.201.15:05:40.73#ibcon#read 3, iclass 19, count 2 2006.201.15:05:40.73#ibcon#about to read 4, iclass 19, count 2 2006.201.15:05:40.73#ibcon#read 4, iclass 19, count 2 2006.201.15:05:40.73#ibcon#about to read 5, iclass 19, count 2 2006.201.15:05:40.73#ibcon#read 5, iclass 19, count 2 2006.201.15:05:40.73#ibcon#about to read 6, iclass 19, count 2 2006.201.15:05:40.73#ibcon#read 6, iclass 19, count 2 2006.201.15:05:40.73#ibcon#end of sib2, iclass 19, count 2 2006.201.15:05:40.73#ibcon#*mode == 0, iclass 19, count 2 2006.201.15:05:40.73#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.15:05:40.73#ibcon#[27=AT01-04\r\n] 2006.201.15:05:40.73#ibcon#*before write, iclass 19, count 2 2006.201.15:05:40.73#ibcon#enter sib2, iclass 19, count 2 2006.201.15:05:40.73#ibcon#flushed, iclass 19, count 2 2006.201.15:05:40.73#ibcon#about to write, iclass 19, count 2 2006.201.15:05:40.73#ibcon#wrote, iclass 19, count 2 2006.201.15:05:40.73#ibcon#about to read 3, iclass 19, count 2 2006.201.15:05:40.76#ibcon#read 3, iclass 19, count 2 2006.201.15:05:40.76#ibcon#about to read 4, iclass 19, count 2 2006.201.15:05:40.76#ibcon#read 4, iclass 19, count 2 2006.201.15:05:40.76#ibcon#about to read 5, iclass 19, count 2 2006.201.15:05:40.76#ibcon#read 5, iclass 19, count 2 2006.201.15:05:40.76#ibcon#about to read 6, iclass 19, count 2 2006.201.15:05:40.76#ibcon#read 6, iclass 19, count 2 2006.201.15:05:40.76#ibcon#end of sib2, iclass 19, count 2 2006.201.15:05:40.76#ibcon#*after write, iclass 19, count 2 2006.201.15:05:40.76#ibcon#*before return 0, iclass 19, count 2 2006.201.15:05:40.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:05:40.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:05:40.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.15:05:40.76#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:40.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:05:40.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:05:40.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:05:40.88#ibcon#enter wrdev, iclass 19, count 0 2006.201.15:05:40.88#ibcon#first serial, iclass 19, count 0 2006.201.15:05:40.88#ibcon#enter sib2, iclass 19, count 0 2006.201.15:05:40.88#ibcon#flushed, iclass 19, count 0 2006.201.15:05:40.88#ibcon#about to write, iclass 19, count 0 2006.201.15:05:40.88#ibcon#wrote, iclass 19, count 0 2006.201.15:05:40.88#ibcon#about to read 3, iclass 19, count 0 2006.201.15:05:40.90#ibcon#read 3, iclass 19, count 0 2006.201.15:05:40.90#ibcon#about to read 4, iclass 19, count 0 2006.201.15:05:40.90#ibcon#read 4, iclass 19, count 0 2006.201.15:05:40.90#ibcon#about to read 5, iclass 19, count 0 2006.201.15:05:40.90#ibcon#read 5, iclass 19, count 0 2006.201.15:05:40.90#ibcon#about to read 6, iclass 19, count 0 2006.201.15:05:40.90#ibcon#read 6, iclass 19, count 0 2006.201.15:05:40.90#ibcon#end of sib2, iclass 19, count 0 2006.201.15:05:40.90#ibcon#*mode == 0, iclass 19, count 0 2006.201.15:05:40.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.15:05:40.90#ibcon#[27=USB\r\n] 2006.201.15:05:40.90#ibcon#*before write, iclass 19, count 0 2006.201.15:05:40.90#ibcon#enter sib2, iclass 19, count 0 2006.201.15:05:40.90#ibcon#flushed, iclass 19, count 0 2006.201.15:05:40.90#ibcon#about to write, iclass 19, count 0 2006.201.15:05:40.90#ibcon#wrote, iclass 19, count 0 2006.201.15:05:40.90#ibcon#about to read 3, iclass 19, count 0 2006.201.15:05:40.93#ibcon#read 3, iclass 19, count 0 2006.201.15:05:40.93#ibcon#about to read 4, iclass 19, count 0 2006.201.15:05:40.93#ibcon#read 4, iclass 19, count 0 2006.201.15:05:40.93#ibcon#about to read 5, iclass 19, count 0 2006.201.15:05:40.93#ibcon#read 5, iclass 19, count 0 2006.201.15:05:40.93#ibcon#about to read 6, iclass 19, count 0 2006.201.15:05:40.93#ibcon#read 6, iclass 19, count 0 2006.201.15:05:40.93#ibcon#end of sib2, iclass 19, count 0 2006.201.15:05:40.93#ibcon#*after write, iclass 19, count 0 2006.201.15:05:40.93#ibcon#*before return 0, iclass 19, count 0 2006.201.15:05:40.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:05:40.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:05:40.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.15:05:40.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.15:05:40.93$vck44/vblo=2,634.99 2006.201.15:05:40.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.15:05:40.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.15:05:40.93#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:40.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:40.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:40.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:40.93#ibcon#enter wrdev, iclass 21, count 0 2006.201.15:05:40.93#ibcon#first serial, iclass 21, count 0 2006.201.15:05:40.93#ibcon#enter sib2, iclass 21, count 0 2006.201.15:05:40.93#ibcon#flushed, iclass 21, count 0 2006.201.15:05:40.93#ibcon#about to write, iclass 21, count 0 2006.201.15:05:40.93#ibcon#wrote, iclass 21, count 0 2006.201.15:05:40.93#ibcon#about to read 3, iclass 21, count 0 2006.201.15:05:40.95#ibcon#read 3, iclass 21, count 0 2006.201.15:05:40.95#ibcon#about to read 4, iclass 21, count 0 2006.201.15:05:40.95#ibcon#read 4, iclass 21, count 0 2006.201.15:05:40.95#ibcon#about to read 5, iclass 21, count 0 2006.201.15:05:40.95#ibcon#read 5, iclass 21, count 0 2006.201.15:05:40.95#ibcon#about to read 6, iclass 21, count 0 2006.201.15:05:40.95#ibcon#read 6, iclass 21, count 0 2006.201.15:05:40.95#ibcon#end of sib2, iclass 21, count 0 2006.201.15:05:40.95#ibcon#*mode == 0, iclass 21, count 0 2006.201.15:05:40.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.15:05:40.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:05:40.95#ibcon#*before write, iclass 21, count 0 2006.201.15:05:40.95#ibcon#enter sib2, iclass 21, count 0 2006.201.15:05:40.95#ibcon#flushed, iclass 21, count 0 2006.201.15:05:40.95#ibcon#about to write, iclass 21, count 0 2006.201.15:05:40.95#ibcon#wrote, iclass 21, count 0 2006.201.15:05:40.95#ibcon#about to read 3, iclass 21, count 0 2006.201.15:05:40.99#ibcon#read 3, iclass 21, count 0 2006.201.15:05:40.99#ibcon#about to read 4, iclass 21, count 0 2006.201.15:05:40.99#ibcon#read 4, iclass 21, count 0 2006.201.15:05:40.99#ibcon#about to read 5, iclass 21, count 0 2006.201.15:05:40.99#ibcon#read 5, iclass 21, count 0 2006.201.15:05:40.99#ibcon#about to read 6, iclass 21, count 0 2006.201.15:05:40.99#ibcon#read 6, iclass 21, count 0 2006.201.15:05:40.99#ibcon#end of sib2, iclass 21, count 0 2006.201.15:05:40.99#ibcon#*after write, iclass 21, count 0 2006.201.15:05:40.99#ibcon#*before return 0, iclass 21, count 0 2006.201.15:05:40.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:40.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:05:40.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.15:05:40.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.15:05:40.99$vck44/vb=2,5 2006.201.15:05:40.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.15:05:40.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.15:05:40.99#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:40.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:41.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:41.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:41.05#ibcon#enter wrdev, iclass 23, count 2 2006.201.15:05:41.05#ibcon#first serial, iclass 23, count 2 2006.201.15:05:41.05#ibcon#enter sib2, iclass 23, count 2 2006.201.15:05:41.05#ibcon#flushed, iclass 23, count 2 2006.201.15:05:41.05#ibcon#about to write, iclass 23, count 2 2006.201.15:05:41.05#ibcon#wrote, iclass 23, count 2 2006.201.15:05:41.05#ibcon#about to read 3, iclass 23, count 2 2006.201.15:05:41.07#ibcon#read 3, iclass 23, count 2 2006.201.15:05:41.07#ibcon#about to read 4, iclass 23, count 2 2006.201.15:05:41.07#ibcon#read 4, iclass 23, count 2 2006.201.15:05:41.07#ibcon#about to read 5, iclass 23, count 2 2006.201.15:05:41.07#ibcon#read 5, iclass 23, count 2 2006.201.15:05:41.07#ibcon#about to read 6, iclass 23, count 2 2006.201.15:05:41.07#ibcon#read 6, iclass 23, count 2 2006.201.15:05:41.07#ibcon#end of sib2, iclass 23, count 2 2006.201.15:05:41.07#ibcon#*mode == 0, iclass 23, count 2 2006.201.15:05:41.07#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.15:05:41.07#ibcon#[27=AT02-05\r\n] 2006.201.15:05:41.07#ibcon#*before write, iclass 23, count 2 2006.201.15:05:41.07#ibcon#enter sib2, iclass 23, count 2 2006.201.15:05:41.07#ibcon#flushed, iclass 23, count 2 2006.201.15:05:41.07#ibcon#about to write, iclass 23, count 2 2006.201.15:05:41.07#ibcon#wrote, iclass 23, count 2 2006.201.15:05:41.07#ibcon#about to read 3, iclass 23, count 2 2006.201.15:05:41.10#ibcon#read 3, iclass 23, count 2 2006.201.15:05:41.10#ibcon#about to read 4, iclass 23, count 2 2006.201.15:05:41.10#ibcon#read 4, iclass 23, count 2 2006.201.15:05:41.10#ibcon#about to read 5, iclass 23, count 2 2006.201.15:05:41.10#ibcon#read 5, iclass 23, count 2 2006.201.15:05:41.10#ibcon#about to read 6, iclass 23, count 2 2006.201.15:05:41.10#ibcon#read 6, iclass 23, count 2 2006.201.15:05:41.10#ibcon#end of sib2, iclass 23, count 2 2006.201.15:05:41.10#ibcon#*after write, iclass 23, count 2 2006.201.15:05:41.10#ibcon#*before return 0, iclass 23, count 2 2006.201.15:05:41.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:41.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:05:41.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.15:05:41.10#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:41.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:41.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:41.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:41.22#ibcon#enter wrdev, iclass 23, count 0 2006.201.15:05:41.22#ibcon#first serial, iclass 23, count 0 2006.201.15:05:41.22#ibcon#enter sib2, iclass 23, count 0 2006.201.15:05:41.22#ibcon#flushed, iclass 23, count 0 2006.201.15:05:41.22#ibcon#about to write, iclass 23, count 0 2006.201.15:05:41.22#ibcon#wrote, iclass 23, count 0 2006.201.15:05:41.22#ibcon#about to read 3, iclass 23, count 0 2006.201.15:05:41.24#ibcon#read 3, iclass 23, count 0 2006.201.15:05:41.24#ibcon#about to read 4, iclass 23, count 0 2006.201.15:05:41.24#ibcon#read 4, iclass 23, count 0 2006.201.15:05:41.24#ibcon#about to read 5, iclass 23, count 0 2006.201.15:05:41.24#ibcon#read 5, iclass 23, count 0 2006.201.15:05:41.24#ibcon#about to read 6, iclass 23, count 0 2006.201.15:05:41.24#ibcon#read 6, iclass 23, count 0 2006.201.15:05:41.24#ibcon#end of sib2, iclass 23, count 0 2006.201.15:05:41.24#ibcon#*mode == 0, iclass 23, count 0 2006.201.15:05:41.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.15:05:41.24#ibcon#[27=USB\r\n] 2006.201.15:05:41.24#ibcon#*before write, iclass 23, count 0 2006.201.15:05:41.24#ibcon#enter sib2, iclass 23, count 0 2006.201.15:05:41.24#ibcon#flushed, iclass 23, count 0 2006.201.15:05:41.24#ibcon#about to write, iclass 23, count 0 2006.201.15:05:41.24#ibcon#wrote, iclass 23, count 0 2006.201.15:05:41.24#ibcon#about to read 3, iclass 23, count 0 2006.201.15:05:41.27#ibcon#read 3, iclass 23, count 0 2006.201.15:05:41.27#ibcon#about to read 4, iclass 23, count 0 2006.201.15:05:41.27#ibcon#read 4, iclass 23, count 0 2006.201.15:05:41.27#ibcon#about to read 5, iclass 23, count 0 2006.201.15:05:41.27#ibcon#read 5, iclass 23, count 0 2006.201.15:05:41.27#ibcon#about to read 6, iclass 23, count 0 2006.201.15:05:41.27#ibcon#read 6, iclass 23, count 0 2006.201.15:05:41.27#ibcon#end of sib2, iclass 23, count 0 2006.201.15:05:41.27#ibcon#*after write, iclass 23, count 0 2006.201.15:05:41.27#ibcon#*before return 0, iclass 23, count 0 2006.201.15:05:41.27#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:41.27#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:05:41.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.15:05:41.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.15:05:41.27$vck44/vblo=3,649.99 2006.201.15:05:41.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.15:05:41.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.15:05:41.27#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:41.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:41.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:41.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:41.27#ibcon#enter wrdev, iclass 25, count 0 2006.201.15:05:41.27#ibcon#first serial, iclass 25, count 0 2006.201.15:05:41.27#ibcon#enter sib2, iclass 25, count 0 2006.201.15:05:41.27#ibcon#flushed, iclass 25, count 0 2006.201.15:05:41.27#ibcon#about to write, iclass 25, count 0 2006.201.15:05:41.27#ibcon#wrote, iclass 25, count 0 2006.201.15:05:41.27#ibcon#about to read 3, iclass 25, count 0 2006.201.15:05:41.29#ibcon#read 3, iclass 25, count 0 2006.201.15:05:41.29#ibcon#about to read 4, iclass 25, count 0 2006.201.15:05:41.29#ibcon#read 4, iclass 25, count 0 2006.201.15:05:41.29#ibcon#about to read 5, iclass 25, count 0 2006.201.15:05:41.29#ibcon#read 5, iclass 25, count 0 2006.201.15:05:41.29#ibcon#about to read 6, iclass 25, count 0 2006.201.15:05:41.29#ibcon#read 6, iclass 25, count 0 2006.201.15:05:41.29#ibcon#end of sib2, iclass 25, count 0 2006.201.15:05:41.29#ibcon#*mode == 0, iclass 25, count 0 2006.201.15:05:41.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.15:05:41.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:05:41.29#ibcon#*before write, iclass 25, count 0 2006.201.15:05:41.29#ibcon#enter sib2, iclass 25, count 0 2006.201.15:05:41.29#ibcon#flushed, iclass 25, count 0 2006.201.15:05:41.29#ibcon#about to write, iclass 25, count 0 2006.201.15:05:41.29#ibcon#wrote, iclass 25, count 0 2006.201.15:05:41.29#ibcon#about to read 3, iclass 25, count 0 2006.201.15:05:41.33#ibcon#read 3, iclass 25, count 0 2006.201.15:05:41.33#ibcon#about to read 4, iclass 25, count 0 2006.201.15:05:41.33#ibcon#read 4, iclass 25, count 0 2006.201.15:05:41.33#ibcon#about to read 5, iclass 25, count 0 2006.201.15:05:41.33#ibcon#read 5, iclass 25, count 0 2006.201.15:05:41.33#ibcon#about to read 6, iclass 25, count 0 2006.201.15:05:41.33#ibcon#read 6, iclass 25, count 0 2006.201.15:05:41.33#ibcon#end of sib2, iclass 25, count 0 2006.201.15:05:41.33#ibcon#*after write, iclass 25, count 0 2006.201.15:05:41.33#ibcon#*before return 0, iclass 25, count 0 2006.201.15:05:41.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:41.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:05:41.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.15:05:41.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.15:05:41.33$vck44/vb=3,4 2006.201.15:05:41.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.15:05:41.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.15:05:41.33#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:41.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:41.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:41.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:41.39#ibcon#enter wrdev, iclass 27, count 2 2006.201.15:05:41.39#ibcon#first serial, iclass 27, count 2 2006.201.15:05:41.39#ibcon#enter sib2, iclass 27, count 2 2006.201.15:05:41.39#ibcon#flushed, iclass 27, count 2 2006.201.15:05:41.39#ibcon#about to write, iclass 27, count 2 2006.201.15:05:41.39#ibcon#wrote, iclass 27, count 2 2006.201.15:05:41.39#ibcon#about to read 3, iclass 27, count 2 2006.201.15:05:41.41#ibcon#read 3, iclass 27, count 2 2006.201.15:05:41.41#ibcon#about to read 4, iclass 27, count 2 2006.201.15:05:41.41#ibcon#read 4, iclass 27, count 2 2006.201.15:05:41.41#ibcon#about to read 5, iclass 27, count 2 2006.201.15:05:41.41#ibcon#read 5, iclass 27, count 2 2006.201.15:05:41.41#ibcon#about to read 6, iclass 27, count 2 2006.201.15:05:41.41#ibcon#read 6, iclass 27, count 2 2006.201.15:05:41.41#ibcon#end of sib2, iclass 27, count 2 2006.201.15:05:41.41#ibcon#*mode == 0, iclass 27, count 2 2006.201.15:05:41.41#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.15:05:41.41#ibcon#[27=AT03-04\r\n] 2006.201.15:05:41.41#ibcon#*before write, iclass 27, count 2 2006.201.15:05:41.41#ibcon#enter sib2, iclass 27, count 2 2006.201.15:05:41.41#ibcon#flushed, iclass 27, count 2 2006.201.15:05:41.41#ibcon#about to write, iclass 27, count 2 2006.201.15:05:41.41#ibcon#wrote, iclass 27, count 2 2006.201.15:05:41.41#ibcon#about to read 3, iclass 27, count 2 2006.201.15:05:41.44#ibcon#read 3, iclass 27, count 2 2006.201.15:05:41.44#ibcon#about to read 4, iclass 27, count 2 2006.201.15:05:41.44#ibcon#read 4, iclass 27, count 2 2006.201.15:05:41.44#ibcon#about to read 5, iclass 27, count 2 2006.201.15:05:41.44#ibcon#read 5, iclass 27, count 2 2006.201.15:05:41.44#ibcon#about to read 6, iclass 27, count 2 2006.201.15:05:41.44#ibcon#read 6, iclass 27, count 2 2006.201.15:05:41.44#ibcon#end of sib2, iclass 27, count 2 2006.201.15:05:41.44#ibcon#*after write, iclass 27, count 2 2006.201.15:05:41.44#ibcon#*before return 0, iclass 27, count 2 2006.201.15:05:41.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:41.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:05:41.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.15:05:41.44#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:41.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:41.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:41.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:41.56#ibcon#enter wrdev, iclass 27, count 0 2006.201.15:05:41.56#ibcon#first serial, iclass 27, count 0 2006.201.15:05:41.56#ibcon#enter sib2, iclass 27, count 0 2006.201.15:05:41.56#ibcon#flushed, iclass 27, count 0 2006.201.15:05:41.56#ibcon#about to write, iclass 27, count 0 2006.201.15:05:41.56#ibcon#wrote, iclass 27, count 0 2006.201.15:05:41.56#ibcon#about to read 3, iclass 27, count 0 2006.201.15:05:41.58#ibcon#read 3, iclass 27, count 0 2006.201.15:05:41.58#ibcon#about to read 4, iclass 27, count 0 2006.201.15:05:41.58#ibcon#read 4, iclass 27, count 0 2006.201.15:05:41.58#ibcon#about to read 5, iclass 27, count 0 2006.201.15:05:41.58#ibcon#read 5, iclass 27, count 0 2006.201.15:05:41.58#ibcon#about to read 6, iclass 27, count 0 2006.201.15:05:41.58#ibcon#read 6, iclass 27, count 0 2006.201.15:05:41.58#ibcon#end of sib2, iclass 27, count 0 2006.201.15:05:41.58#ibcon#*mode == 0, iclass 27, count 0 2006.201.15:05:41.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.15:05:41.58#ibcon#[27=USB\r\n] 2006.201.15:05:41.58#ibcon#*before write, iclass 27, count 0 2006.201.15:05:41.58#ibcon#enter sib2, iclass 27, count 0 2006.201.15:05:41.58#ibcon#flushed, iclass 27, count 0 2006.201.15:05:41.58#ibcon#about to write, iclass 27, count 0 2006.201.15:05:41.58#ibcon#wrote, iclass 27, count 0 2006.201.15:05:41.58#ibcon#about to read 3, iclass 27, count 0 2006.201.15:05:41.61#ibcon#read 3, iclass 27, count 0 2006.201.15:05:41.61#ibcon#about to read 4, iclass 27, count 0 2006.201.15:05:41.61#ibcon#read 4, iclass 27, count 0 2006.201.15:05:41.61#ibcon#about to read 5, iclass 27, count 0 2006.201.15:05:41.61#ibcon#read 5, iclass 27, count 0 2006.201.15:05:41.61#ibcon#about to read 6, iclass 27, count 0 2006.201.15:05:41.61#ibcon#read 6, iclass 27, count 0 2006.201.15:05:41.61#ibcon#end of sib2, iclass 27, count 0 2006.201.15:05:41.61#ibcon#*after write, iclass 27, count 0 2006.201.15:05:41.61#ibcon#*before return 0, iclass 27, count 0 2006.201.15:05:41.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:41.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:05:41.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.15:05:41.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.15:05:41.61$vck44/vblo=4,679.99 2006.201.15:05:41.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.15:05:41.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.15:05:41.61#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:41.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:41.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:41.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:41.61#ibcon#enter wrdev, iclass 29, count 0 2006.201.15:05:41.61#ibcon#first serial, iclass 29, count 0 2006.201.15:05:41.61#ibcon#enter sib2, iclass 29, count 0 2006.201.15:05:41.61#ibcon#flushed, iclass 29, count 0 2006.201.15:05:41.61#ibcon#about to write, iclass 29, count 0 2006.201.15:05:41.61#ibcon#wrote, iclass 29, count 0 2006.201.15:05:41.61#ibcon#about to read 3, iclass 29, count 0 2006.201.15:05:41.63#ibcon#read 3, iclass 29, count 0 2006.201.15:05:41.63#ibcon#about to read 4, iclass 29, count 0 2006.201.15:05:41.63#ibcon#read 4, iclass 29, count 0 2006.201.15:05:41.63#ibcon#about to read 5, iclass 29, count 0 2006.201.15:05:41.63#ibcon#read 5, iclass 29, count 0 2006.201.15:05:41.63#ibcon#about to read 6, iclass 29, count 0 2006.201.15:05:41.63#ibcon#read 6, iclass 29, count 0 2006.201.15:05:41.63#ibcon#end of sib2, iclass 29, count 0 2006.201.15:05:41.63#ibcon#*mode == 0, iclass 29, count 0 2006.201.15:05:41.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.15:05:41.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:05:41.63#ibcon#*before write, iclass 29, count 0 2006.201.15:05:41.63#ibcon#enter sib2, iclass 29, count 0 2006.201.15:05:41.63#ibcon#flushed, iclass 29, count 0 2006.201.15:05:41.63#ibcon#about to write, iclass 29, count 0 2006.201.15:05:41.63#ibcon#wrote, iclass 29, count 0 2006.201.15:05:41.63#ibcon#about to read 3, iclass 29, count 0 2006.201.15:05:41.68#ibcon#read 3, iclass 29, count 0 2006.201.15:05:41.68#ibcon#about to read 4, iclass 29, count 0 2006.201.15:05:41.68#ibcon#read 4, iclass 29, count 0 2006.201.15:05:41.68#ibcon#about to read 5, iclass 29, count 0 2006.201.15:05:41.68#ibcon#read 5, iclass 29, count 0 2006.201.15:05:41.68#ibcon#about to read 6, iclass 29, count 0 2006.201.15:05:41.68#ibcon#read 6, iclass 29, count 0 2006.201.15:05:41.68#ibcon#end of sib2, iclass 29, count 0 2006.201.15:05:41.68#ibcon#*after write, iclass 29, count 0 2006.201.15:05:41.68#ibcon#*before return 0, iclass 29, count 0 2006.201.15:05:41.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:41.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:05:41.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.15:05:41.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.15:05:41.68$vck44/vb=4,5 2006.201.15:05:41.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.15:05:41.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.15:05:41.68#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:41.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:41.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:41.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:41.73#ibcon#enter wrdev, iclass 31, count 2 2006.201.15:05:41.73#ibcon#first serial, iclass 31, count 2 2006.201.15:05:41.73#ibcon#enter sib2, iclass 31, count 2 2006.201.15:05:41.73#ibcon#flushed, iclass 31, count 2 2006.201.15:05:41.73#ibcon#about to write, iclass 31, count 2 2006.201.15:05:41.73#ibcon#wrote, iclass 31, count 2 2006.201.15:05:41.73#ibcon#about to read 3, iclass 31, count 2 2006.201.15:05:41.75#ibcon#read 3, iclass 31, count 2 2006.201.15:05:41.75#ibcon#about to read 4, iclass 31, count 2 2006.201.15:05:41.75#ibcon#read 4, iclass 31, count 2 2006.201.15:05:41.75#ibcon#about to read 5, iclass 31, count 2 2006.201.15:05:41.75#ibcon#read 5, iclass 31, count 2 2006.201.15:05:41.75#ibcon#about to read 6, iclass 31, count 2 2006.201.15:05:41.75#ibcon#read 6, iclass 31, count 2 2006.201.15:05:41.75#ibcon#end of sib2, iclass 31, count 2 2006.201.15:05:41.75#ibcon#*mode == 0, iclass 31, count 2 2006.201.15:05:41.75#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.15:05:41.75#ibcon#[27=AT04-05\r\n] 2006.201.15:05:41.75#ibcon#*before write, iclass 31, count 2 2006.201.15:05:41.75#ibcon#enter sib2, iclass 31, count 2 2006.201.15:05:41.75#ibcon#flushed, iclass 31, count 2 2006.201.15:05:41.75#ibcon#about to write, iclass 31, count 2 2006.201.15:05:41.75#ibcon#wrote, iclass 31, count 2 2006.201.15:05:41.75#ibcon#about to read 3, iclass 31, count 2 2006.201.15:05:41.78#ibcon#read 3, iclass 31, count 2 2006.201.15:05:41.78#ibcon#about to read 4, iclass 31, count 2 2006.201.15:05:41.78#ibcon#read 4, iclass 31, count 2 2006.201.15:05:41.78#ibcon#about to read 5, iclass 31, count 2 2006.201.15:05:41.78#ibcon#read 5, iclass 31, count 2 2006.201.15:05:41.78#ibcon#about to read 6, iclass 31, count 2 2006.201.15:05:41.78#ibcon#read 6, iclass 31, count 2 2006.201.15:05:41.78#ibcon#end of sib2, iclass 31, count 2 2006.201.15:05:41.78#ibcon#*after write, iclass 31, count 2 2006.201.15:05:41.78#ibcon#*before return 0, iclass 31, count 2 2006.201.15:05:41.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:41.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:05:41.78#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.15:05:41.78#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:41.78#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:41.90#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:41.90#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:41.90#ibcon#enter wrdev, iclass 31, count 0 2006.201.15:05:41.90#ibcon#first serial, iclass 31, count 0 2006.201.15:05:41.90#ibcon#enter sib2, iclass 31, count 0 2006.201.15:05:41.90#ibcon#flushed, iclass 31, count 0 2006.201.15:05:41.90#ibcon#about to write, iclass 31, count 0 2006.201.15:05:41.90#ibcon#wrote, iclass 31, count 0 2006.201.15:05:41.90#ibcon#about to read 3, iclass 31, count 0 2006.201.15:05:41.92#ibcon#read 3, iclass 31, count 0 2006.201.15:05:41.92#ibcon#about to read 4, iclass 31, count 0 2006.201.15:05:41.92#ibcon#read 4, iclass 31, count 0 2006.201.15:05:41.92#ibcon#about to read 5, iclass 31, count 0 2006.201.15:05:41.92#ibcon#read 5, iclass 31, count 0 2006.201.15:05:41.92#ibcon#about to read 6, iclass 31, count 0 2006.201.15:05:41.92#ibcon#read 6, iclass 31, count 0 2006.201.15:05:41.92#ibcon#end of sib2, iclass 31, count 0 2006.201.15:05:41.92#ibcon#*mode == 0, iclass 31, count 0 2006.201.15:05:41.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.15:05:41.92#ibcon#[27=USB\r\n] 2006.201.15:05:41.92#ibcon#*before write, iclass 31, count 0 2006.201.15:05:41.92#ibcon#enter sib2, iclass 31, count 0 2006.201.15:05:41.92#ibcon#flushed, iclass 31, count 0 2006.201.15:05:41.92#ibcon#about to write, iclass 31, count 0 2006.201.15:05:41.92#ibcon#wrote, iclass 31, count 0 2006.201.15:05:41.92#ibcon#about to read 3, iclass 31, count 0 2006.201.15:05:41.95#ibcon#read 3, iclass 31, count 0 2006.201.15:05:41.95#ibcon#about to read 4, iclass 31, count 0 2006.201.15:05:41.95#ibcon#read 4, iclass 31, count 0 2006.201.15:05:41.95#ibcon#about to read 5, iclass 31, count 0 2006.201.15:05:41.95#ibcon#read 5, iclass 31, count 0 2006.201.15:05:41.95#ibcon#about to read 6, iclass 31, count 0 2006.201.15:05:41.95#ibcon#read 6, iclass 31, count 0 2006.201.15:05:41.95#ibcon#end of sib2, iclass 31, count 0 2006.201.15:05:41.95#ibcon#*after write, iclass 31, count 0 2006.201.15:05:41.95#ibcon#*before return 0, iclass 31, count 0 2006.201.15:05:41.95#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:41.95#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:05:41.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.15:05:41.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.15:05:41.95$vck44/vblo=5,709.99 2006.201.15:05:41.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.15:05:41.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.15:05:41.95#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:41.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:41.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:41.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:41.95#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:05:41.95#ibcon#first serial, iclass 33, count 0 2006.201.15:05:41.95#ibcon#enter sib2, iclass 33, count 0 2006.201.15:05:41.95#ibcon#flushed, iclass 33, count 0 2006.201.15:05:41.95#ibcon#about to write, iclass 33, count 0 2006.201.15:05:41.95#ibcon#wrote, iclass 33, count 0 2006.201.15:05:41.95#ibcon#about to read 3, iclass 33, count 0 2006.201.15:05:41.97#ibcon#read 3, iclass 33, count 0 2006.201.15:05:41.97#ibcon#about to read 4, iclass 33, count 0 2006.201.15:05:41.97#ibcon#read 4, iclass 33, count 0 2006.201.15:05:41.97#ibcon#about to read 5, iclass 33, count 0 2006.201.15:05:41.97#ibcon#read 5, iclass 33, count 0 2006.201.15:05:41.97#ibcon#about to read 6, iclass 33, count 0 2006.201.15:05:41.97#ibcon#read 6, iclass 33, count 0 2006.201.15:05:41.97#ibcon#end of sib2, iclass 33, count 0 2006.201.15:05:41.97#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:05:41.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:05:41.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:05:41.97#ibcon#*before write, iclass 33, count 0 2006.201.15:05:41.97#ibcon#enter sib2, iclass 33, count 0 2006.201.15:05:41.97#ibcon#flushed, iclass 33, count 0 2006.201.15:05:41.97#ibcon#about to write, iclass 33, count 0 2006.201.15:05:41.97#ibcon#wrote, iclass 33, count 0 2006.201.15:05:41.97#ibcon#about to read 3, iclass 33, count 0 2006.201.15:05:42.01#ibcon#read 3, iclass 33, count 0 2006.201.15:05:42.01#ibcon#about to read 4, iclass 33, count 0 2006.201.15:05:42.01#ibcon#read 4, iclass 33, count 0 2006.201.15:05:42.01#ibcon#about to read 5, iclass 33, count 0 2006.201.15:05:42.01#ibcon#read 5, iclass 33, count 0 2006.201.15:05:42.01#ibcon#about to read 6, iclass 33, count 0 2006.201.15:05:42.01#ibcon#read 6, iclass 33, count 0 2006.201.15:05:42.01#ibcon#end of sib2, iclass 33, count 0 2006.201.15:05:42.01#ibcon#*after write, iclass 33, count 0 2006.201.15:05:42.01#ibcon#*before return 0, iclass 33, count 0 2006.201.15:05:42.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:42.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:05:42.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:05:42.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:05:42.01$vck44/vb=5,4 2006.201.15:05:42.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.15:05:42.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.15:05:42.01#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:42.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:42.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:42.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:42.07#ibcon#enter wrdev, iclass 35, count 2 2006.201.15:05:42.07#ibcon#first serial, iclass 35, count 2 2006.201.15:05:42.07#ibcon#enter sib2, iclass 35, count 2 2006.201.15:05:42.07#ibcon#flushed, iclass 35, count 2 2006.201.15:05:42.07#ibcon#about to write, iclass 35, count 2 2006.201.15:05:42.07#ibcon#wrote, iclass 35, count 2 2006.201.15:05:42.07#ibcon#about to read 3, iclass 35, count 2 2006.201.15:05:42.09#ibcon#read 3, iclass 35, count 2 2006.201.15:05:42.09#ibcon#about to read 4, iclass 35, count 2 2006.201.15:05:42.09#ibcon#read 4, iclass 35, count 2 2006.201.15:05:42.09#ibcon#about to read 5, iclass 35, count 2 2006.201.15:05:42.09#ibcon#read 5, iclass 35, count 2 2006.201.15:05:42.09#ibcon#about to read 6, iclass 35, count 2 2006.201.15:05:42.09#ibcon#read 6, iclass 35, count 2 2006.201.15:05:42.09#ibcon#end of sib2, iclass 35, count 2 2006.201.15:05:42.09#ibcon#*mode == 0, iclass 35, count 2 2006.201.15:05:42.09#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.15:05:42.09#ibcon#[27=AT05-04\r\n] 2006.201.15:05:42.09#ibcon#*before write, iclass 35, count 2 2006.201.15:05:42.09#ibcon#enter sib2, iclass 35, count 2 2006.201.15:05:42.09#ibcon#flushed, iclass 35, count 2 2006.201.15:05:42.09#ibcon#about to write, iclass 35, count 2 2006.201.15:05:42.09#ibcon#wrote, iclass 35, count 2 2006.201.15:05:42.09#ibcon#about to read 3, iclass 35, count 2 2006.201.15:05:42.12#ibcon#read 3, iclass 35, count 2 2006.201.15:05:42.12#ibcon#about to read 4, iclass 35, count 2 2006.201.15:05:42.12#ibcon#read 4, iclass 35, count 2 2006.201.15:05:42.12#ibcon#about to read 5, iclass 35, count 2 2006.201.15:05:42.12#ibcon#read 5, iclass 35, count 2 2006.201.15:05:42.12#ibcon#about to read 6, iclass 35, count 2 2006.201.15:05:42.12#ibcon#read 6, iclass 35, count 2 2006.201.15:05:42.12#ibcon#end of sib2, iclass 35, count 2 2006.201.15:05:42.12#ibcon#*after write, iclass 35, count 2 2006.201.15:05:42.12#ibcon#*before return 0, iclass 35, count 2 2006.201.15:05:42.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:42.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:05:42.12#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.15:05:42.12#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:42.12#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:42.24#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:42.24#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:42.24#ibcon#enter wrdev, iclass 35, count 0 2006.201.15:05:42.24#ibcon#first serial, iclass 35, count 0 2006.201.15:05:42.24#ibcon#enter sib2, iclass 35, count 0 2006.201.15:05:42.24#ibcon#flushed, iclass 35, count 0 2006.201.15:05:42.24#ibcon#about to write, iclass 35, count 0 2006.201.15:05:42.24#ibcon#wrote, iclass 35, count 0 2006.201.15:05:42.24#ibcon#about to read 3, iclass 35, count 0 2006.201.15:05:42.26#ibcon#read 3, iclass 35, count 0 2006.201.15:05:42.26#ibcon#about to read 4, iclass 35, count 0 2006.201.15:05:42.26#ibcon#read 4, iclass 35, count 0 2006.201.15:05:42.26#ibcon#about to read 5, iclass 35, count 0 2006.201.15:05:42.26#ibcon#read 5, iclass 35, count 0 2006.201.15:05:42.26#ibcon#about to read 6, iclass 35, count 0 2006.201.15:05:42.26#ibcon#read 6, iclass 35, count 0 2006.201.15:05:42.26#ibcon#end of sib2, iclass 35, count 0 2006.201.15:05:42.26#ibcon#*mode == 0, iclass 35, count 0 2006.201.15:05:42.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.15:05:42.26#ibcon#[27=USB\r\n] 2006.201.15:05:42.26#ibcon#*before write, iclass 35, count 0 2006.201.15:05:42.26#ibcon#enter sib2, iclass 35, count 0 2006.201.15:05:42.26#ibcon#flushed, iclass 35, count 0 2006.201.15:05:42.26#ibcon#about to write, iclass 35, count 0 2006.201.15:05:42.26#ibcon#wrote, iclass 35, count 0 2006.201.15:05:42.26#ibcon#about to read 3, iclass 35, count 0 2006.201.15:05:42.29#ibcon#read 3, iclass 35, count 0 2006.201.15:05:42.29#ibcon#about to read 4, iclass 35, count 0 2006.201.15:05:42.29#ibcon#read 4, iclass 35, count 0 2006.201.15:05:42.29#ibcon#about to read 5, iclass 35, count 0 2006.201.15:05:42.29#ibcon#read 5, iclass 35, count 0 2006.201.15:05:42.29#ibcon#about to read 6, iclass 35, count 0 2006.201.15:05:42.29#ibcon#read 6, iclass 35, count 0 2006.201.15:05:42.29#ibcon#end of sib2, iclass 35, count 0 2006.201.15:05:42.29#ibcon#*after write, iclass 35, count 0 2006.201.15:05:42.29#ibcon#*before return 0, iclass 35, count 0 2006.201.15:05:42.29#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:42.29#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:05:42.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.15:05:42.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.15:05:42.29$vck44/vblo=6,719.99 2006.201.15:05:42.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.15:05:42.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.15:05:42.29#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:42.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:42.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:42.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:42.29#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:05:42.29#ibcon#first serial, iclass 37, count 0 2006.201.15:05:42.29#ibcon#enter sib2, iclass 37, count 0 2006.201.15:05:42.29#ibcon#flushed, iclass 37, count 0 2006.201.15:05:42.29#ibcon#about to write, iclass 37, count 0 2006.201.15:05:42.29#ibcon#wrote, iclass 37, count 0 2006.201.15:05:42.29#ibcon#about to read 3, iclass 37, count 0 2006.201.15:05:42.31#ibcon#read 3, iclass 37, count 0 2006.201.15:05:42.31#ibcon#about to read 4, iclass 37, count 0 2006.201.15:05:42.31#ibcon#read 4, iclass 37, count 0 2006.201.15:05:42.31#ibcon#about to read 5, iclass 37, count 0 2006.201.15:05:42.31#ibcon#read 5, iclass 37, count 0 2006.201.15:05:42.31#ibcon#about to read 6, iclass 37, count 0 2006.201.15:05:42.31#ibcon#read 6, iclass 37, count 0 2006.201.15:05:42.31#ibcon#end of sib2, iclass 37, count 0 2006.201.15:05:42.31#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:05:42.31#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:05:42.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:05:42.31#ibcon#*before write, iclass 37, count 0 2006.201.15:05:42.31#ibcon#enter sib2, iclass 37, count 0 2006.201.15:05:42.31#ibcon#flushed, iclass 37, count 0 2006.201.15:05:42.31#ibcon#about to write, iclass 37, count 0 2006.201.15:05:42.31#ibcon#wrote, iclass 37, count 0 2006.201.15:05:42.31#ibcon#about to read 3, iclass 37, count 0 2006.201.15:05:42.36#ibcon#read 3, iclass 37, count 0 2006.201.15:05:42.36#ibcon#about to read 4, iclass 37, count 0 2006.201.15:05:42.36#ibcon#read 4, iclass 37, count 0 2006.201.15:05:42.36#ibcon#about to read 5, iclass 37, count 0 2006.201.15:05:42.36#ibcon#read 5, iclass 37, count 0 2006.201.15:05:42.36#ibcon#about to read 6, iclass 37, count 0 2006.201.15:05:42.36#ibcon#read 6, iclass 37, count 0 2006.201.15:05:42.36#ibcon#end of sib2, iclass 37, count 0 2006.201.15:05:42.36#ibcon#*after write, iclass 37, count 0 2006.201.15:05:42.36#ibcon#*before return 0, iclass 37, count 0 2006.201.15:05:42.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:42.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:05:42.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:05:42.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:05:42.36$vck44/vb=6,4 2006.201.15:05:42.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.15:05:42.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.15:05:42.36#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:42.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:42.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:42.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:42.41#ibcon#enter wrdev, iclass 39, count 2 2006.201.15:05:42.41#ibcon#first serial, iclass 39, count 2 2006.201.15:05:42.41#ibcon#enter sib2, iclass 39, count 2 2006.201.15:05:42.41#ibcon#flushed, iclass 39, count 2 2006.201.15:05:42.41#ibcon#about to write, iclass 39, count 2 2006.201.15:05:42.41#ibcon#wrote, iclass 39, count 2 2006.201.15:05:42.41#ibcon#about to read 3, iclass 39, count 2 2006.201.15:05:42.43#ibcon#read 3, iclass 39, count 2 2006.201.15:05:42.43#ibcon#about to read 4, iclass 39, count 2 2006.201.15:05:42.43#ibcon#read 4, iclass 39, count 2 2006.201.15:05:42.43#ibcon#about to read 5, iclass 39, count 2 2006.201.15:05:42.43#ibcon#read 5, iclass 39, count 2 2006.201.15:05:42.43#ibcon#about to read 6, iclass 39, count 2 2006.201.15:05:42.43#ibcon#read 6, iclass 39, count 2 2006.201.15:05:42.43#ibcon#end of sib2, iclass 39, count 2 2006.201.15:05:42.43#ibcon#*mode == 0, iclass 39, count 2 2006.201.15:05:42.43#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.15:05:42.43#ibcon#[27=AT06-04\r\n] 2006.201.15:05:42.43#ibcon#*before write, iclass 39, count 2 2006.201.15:05:42.43#ibcon#enter sib2, iclass 39, count 2 2006.201.15:05:42.43#ibcon#flushed, iclass 39, count 2 2006.201.15:05:42.43#ibcon#about to write, iclass 39, count 2 2006.201.15:05:42.43#ibcon#wrote, iclass 39, count 2 2006.201.15:05:42.43#ibcon#about to read 3, iclass 39, count 2 2006.201.15:05:42.46#ibcon#read 3, iclass 39, count 2 2006.201.15:05:42.46#ibcon#about to read 4, iclass 39, count 2 2006.201.15:05:42.46#ibcon#read 4, iclass 39, count 2 2006.201.15:05:42.46#ibcon#about to read 5, iclass 39, count 2 2006.201.15:05:42.46#ibcon#read 5, iclass 39, count 2 2006.201.15:05:42.46#ibcon#about to read 6, iclass 39, count 2 2006.201.15:05:42.46#ibcon#read 6, iclass 39, count 2 2006.201.15:05:42.46#ibcon#end of sib2, iclass 39, count 2 2006.201.15:05:42.46#ibcon#*after write, iclass 39, count 2 2006.201.15:05:42.46#ibcon#*before return 0, iclass 39, count 2 2006.201.15:05:42.46#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:42.46#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:05:42.46#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.15:05:42.46#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:42.46#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:42.58#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:42.58#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:42.58#ibcon#enter wrdev, iclass 39, count 0 2006.201.15:05:42.58#ibcon#first serial, iclass 39, count 0 2006.201.15:05:42.58#ibcon#enter sib2, iclass 39, count 0 2006.201.15:05:42.58#ibcon#flushed, iclass 39, count 0 2006.201.15:05:42.58#ibcon#about to write, iclass 39, count 0 2006.201.15:05:42.58#ibcon#wrote, iclass 39, count 0 2006.201.15:05:42.58#ibcon#about to read 3, iclass 39, count 0 2006.201.15:05:42.60#ibcon#read 3, iclass 39, count 0 2006.201.15:05:42.60#ibcon#about to read 4, iclass 39, count 0 2006.201.15:05:42.60#ibcon#read 4, iclass 39, count 0 2006.201.15:05:42.60#ibcon#about to read 5, iclass 39, count 0 2006.201.15:05:42.60#ibcon#read 5, iclass 39, count 0 2006.201.15:05:42.60#ibcon#about to read 6, iclass 39, count 0 2006.201.15:05:42.60#ibcon#read 6, iclass 39, count 0 2006.201.15:05:42.60#ibcon#end of sib2, iclass 39, count 0 2006.201.15:05:42.60#ibcon#*mode == 0, iclass 39, count 0 2006.201.15:05:42.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.15:05:42.60#ibcon#[27=USB\r\n] 2006.201.15:05:42.60#ibcon#*before write, iclass 39, count 0 2006.201.15:05:42.60#ibcon#enter sib2, iclass 39, count 0 2006.201.15:05:42.60#ibcon#flushed, iclass 39, count 0 2006.201.15:05:42.60#ibcon#about to write, iclass 39, count 0 2006.201.15:05:42.60#ibcon#wrote, iclass 39, count 0 2006.201.15:05:42.60#ibcon#about to read 3, iclass 39, count 0 2006.201.15:05:42.63#ibcon#read 3, iclass 39, count 0 2006.201.15:05:42.63#ibcon#about to read 4, iclass 39, count 0 2006.201.15:05:42.63#ibcon#read 4, iclass 39, count 0 2006.201.15:05:42.63#ibcon#about to read 5, iclass 39, count 0 2006.201.15:05:42.63#ibcon#read 5, iclass 39, count 0 2006.201.15:05:42.63#ibcon#about to read 6, iclass 39, count 0 2006.201.15:05:42.63#ibcon#read 6, iclass 39, count 0 2006.201.15:05:42.63#ibcon#end of sib2, iclass 39, count 0 2006.201.15:05:42.63#ibcon#*after write, iclass 39, count 0 2006.201.15:05:42.63#ibcon#*before return 0, iclass 39, count 0 2006.201.15:05:42.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:42.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:05:42.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.15:05:42.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.15:05:42.63$vck44/vblo=7,734.99 2006.201.15:05:42.63#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.15:05:42.63#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.15:05:42.63#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:42.63#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:42.63#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:42.63#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:42.63#ibcon#enter wrdev, iclass 2, count 0 2006.201.15:05:42.63#ibcon#first serial, iclass 2, count 0 2006.201.15:05:42.63#ibcon#enter sib2, iclass 2, count 0 2006.201.15:05:42.63#ibcon#flushed, iclass 2, count 0 2006.201.15:05:42.63#ibcon#about to write, iclass 2, count 0 2006.201.15:05:42.63#ibcon#wrote, iclass 2, count 0 2006.201.15:05:42.63#ibcon#about to read 3, iclass 2, count 0 2006.201.15:05:42.65#ibcon#read 3, iclass 2, count 0 2006.201.15:05:42.65#ibcon#about to read 4, iclass 2, count 0 2006.201.15:05:42.65#ibcon#read 4, iclass 2, count 0 2006.201.15:05:42.65#ibcon#about to read 5, iclass 2, count 0 2006.201.15:05:42.65#ibcon#read 5, iclass 2, count 0 2006.201.15:05:42.65#ibcon#about to read 6, iclass 2, count 0 2006.201.15:05:42.65#ibcon#read 6, iclass 2, count 0 2006.201.15:05:42.65#ibcon#end of sib2, iclass 2, count 0 2006.201.15:05:42.65#ibcon#*mode == 0, iclass 2, count 0 2006.201.15:05:42.65#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.15:05:42.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:05:42.65#ibcon#*before write, iclass 2, count 0 2006.201.15:05:42.65#ibcon#enter sib2, iclass 2, count 0 2006.201.15:05:42.65#ibcon#flushed, iclass 2, count 0 2006.201.15:05:42.65#ibcon#about to write, iclass 2, count 0 2006.201.15:05:42.65#ibcon#wrote, iclass 2, count 0 2006.201.15:05:42.65#ibcon#about to read 3, iclass 2, count 0 2006.201.15:05:42.69#ibcon#read 3, iclass 2, count 0 2006.201.15:05:42.69#ibcon#about to read 4, iclass 2, count 0 2006.201.15:05:42.69#ibcon#read 4, iclass 2, count 0 2006.201.15:05:42.69#ibcon#about to read 5, iclass 2, count 0 2006.201.15:05:42.69#ibcon#read 5, iclass 2, count 0 2006.201.15:05:42.69#ibcon#about to read 6, iclass 2, count 0 2006.201.15:05:42.69#ibcon#read 6, iclass 2, count 0 2006.201.15:05:42.69#ibcon#end of sib2, iclass 2, count 0 2006.201.15:05:42.69#ibcon#*after write, iclass 2, count 0 2006.201.15:05:42.69#ibcon#*before return 0, iclass 2, count 0 2006.201.15:05:42.69#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:42.69#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:05:42.69#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.15:05:42.69#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.15:05:42.69$vck44/vb=7,4 2006.201.15:05:42.69#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.15:05:42.69#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.15:05:42.69#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:42.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:42.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:42.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:42.75#ibcon#enter wrdev, iclass 5, count 2 2006.201.15:05:42.75#ibcon#first serial, iclass 5, count 2 2006.201.15:05:42.75#ibcon#enter sib2, iclass 5, count 2 2006.201.15:05:42.75#ibcon#flushed, iclass 5, count 2 2006.201.15:05:42.75#ibcon#about to write, iclass 5, count 2 2006.201.15:05:42.75#ibcon#wrote, iclass 5, count 2 2006.201.15:05:42.75#ibcon#about to read 3, iclass 5, count 2 2006.201.15:05:42.77#ibcon#read 3, iclass 5, count 2 2006.201.15:05:42.77#ibcon#about to read 4, iclass 5, count 2 2006.201.15:05:42.77#ibcon#read 4, iclass 5, count 2 2006.201.15:05:42.77#ibcon#about to read 5, iclass 5, count 2 2006.201.15:05:42.77#ibcon#read 5, iclass 5, count 2 2006.201.15:05:42.77#ibcon#about to read 6, iclass 5, count 2 2006.201.15:05:42.77#ibcon#read 6, iclass 5, count 2 2006.201.15:05:42.77#ibcon#end of sib2, iclass 5, count 2 2006.201.15:05:42.77#ibcon#*mode == 0, iclass 5, count 2 2006.201.15:05:42.77#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.15:05:42.77#ibcon#[27=AT07-04\r\n] 2006.201.15:05:42.77#ibcon#*before write, iclass 5, count 2 2006.201.15:05:42.77#ibcon#enter sib2, iclass 5, count 2 2006.201.15:05:42.77#ibcon#flushed, iclass 5, count 2 2006.201.15:05:42.77#ibcon#about to write, iclass 5, count 2 2006.201.15:05:42.77#ibcon#wrote, iclass 5, count 2 2006.201.15:05:42.77#ibcon#about to read 3, iclass 5, count 2 2006.201.15:05:42.80#ibcon#read 3, iclass 5, count 2 2006.201.15:05:42.80#ibcon#about to read 4, iclass 5, count 2 2006.201.15:05:42.80#ibcon#read 4, iclass 5, count 2 2006.201.15:05:42.80#ibcon#about to read 5, iclass 5, count 2 2006.201.15:05:42.80#ibcon#read 5, iclass 5, count 2 2006.201.15:05:42.80#ibcon#about to read 6, iclass 5, count 2 2006.201.15:05:42.80#ibcon#read 6, iclass 5, count 2 2006.201.15:05:42.80#ibcon#end of sib2, iclass 5, count 2 2006.201.15:05:42.80#ibcon#*after write, iclass 5, count 2 2006.201.15:05:42.80#ibcon#*before return 0, iclass 5, count 2 2006.201.15:05:42.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:42.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:05:42.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.15:05:42.80#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:42.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:42.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:42.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:42.92#ibcon#enter wrdev, iclass 5, count 0 2006.201.15:05:42.92#ibcon#first serial, iclass 5, count 0 2006.201.15:05:42.92#ibcon#enter sib2, iclass 5, count 0 2006.201.15:05:42.92#ibcon#flushed, iclass 5, count 0 2006.201.15:05:42.92#ibcon#about to write, iclass 5, count 0 2006.201.15:05:42.92#ibcon#wrote, iclass 5, count 0 2006.201.15:05:42.92#ibcon#about to read 3, iclass 5, count 0 2006.201.15:05:42.94#ibcon#read 3, iclass 5, count 0 2006.201.15:05:42.94#ibcon#about to read 4, iclass 5, count 0 2006.201.15:05:42.94#ibcon#read 4, iclass 5, count 0 2006.201.15:05:42.94#ibcon#about to read 5, iclass 5, count 0 2006.201.15:05:42.94#ibcon#read 5, iclass 5, count 0 2006.201.15:05:42.94#ibcon#about to read 6, iclass 5, count 0 2006.201.15:05:42.94#ibcon#read 6, iclass 5, count 0 2006.201.15:05:42.94#ibcon#end of sib2, iclass 5, count 0 2006.201.15:05:42.94#ibcon#*mode == 0, iclass 5, count 0 2006.201.15:05:42.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.15:05:42.94#ibcon#[27=USB\r\n] 2006.201.15:05:42.94#ibcon#*before write, iclass 5, count 0 2006.201.15:05:42.94#ibcon#enter sib2, iclass 5, count 0 2006.201.15:05:42.94#ibcon#flushed, iclass 5, count 0 2006.201.15:05:42.94#ibcon#about to write, iclass 5, count 0 2006.201.15:05:42.94#ibcon#wrote, iclass 5, count 0 2006.201.15:05:42.94#ibcon#about to read 3, iclass 5, count 0 2006.201.15:05:42.97#ibcon#read 3, iclass 5, count 0 2006.201.15:05:42.97#ibcon#about to read 4, iclass 5, count 0 2006.201.15:05:42.97#ibcon#read 4, iclass 5, count 0 2006.201.15:05:42.97#ibcon#about to read 5, iclass 5, count 0 2006.201.15:05:42.97#ibcon#read 5, iclass 5, count 0 2006.201.15:05:42.97#ibcon#about to read 6, iclass 5, count 0 2006.201.15:05:42.97#ibcon#read 6, iclass 5, count 0 2006.201.15:05:42.97#ibcon#end of sib2, iclass 5, count 0 2006.201.15:05:42.97#ibcon#*after write, iclass 5, count 0 2006.201.15:05:42.97#ibcon#*before return 0, iclass 5, count 0 2006.201.15:05:42.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:42.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:05:42.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.15:05:42.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.15:05:42.97$vck44/vblo=8,744.99 2006.201.15:05:42.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.15:05:42.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.15:05:42.97#ibcon#ireg 17 cls_cnt 0 2006.201.15:05:42.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:42.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:42.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:42.97#ibcon#enter wrdev, iclass 7, count 0 2006.201.15:05:42.97#ibcon#first serial, iclass 7, count 0 2006.201.15:05:42.97#ibcon#enter sib2, iclass 7, count 0 2006.201.15:05:42.97#ibcon#flushed, iclass 7, count 0 2006.201.15:05:42.97#ibcon#about to write, iclass 7, count 0 2006.201.15:05:42.97#ibcon#wrote, iclass 7, count 0 2006.201.15:05:42.97#ibcon#about to read 3, iclass 7, count 0 2006.201.15:05:42.99#ibcon#read 3, iclass 7, count 0 2006.201.15:05:42.99#ibcon#about to read 4, iclass 7, count 0 2006.201.15:05:42.99#ibcon#read 4, iclass 7, count 0 2006.201.15:05:42.99#ibcon#about to read 5, iclass 7, count 0 2006.201.15:05:42.99#ibcon#read 5, iclass 7, count 0 2006.201.15:05:42.99#ibcon#about to read 6, iclass 7, count 0 2006.201.15:05:42.99#ibcon#read 6, iclass 7, count 0 2006.201.15:05:42.99#ibcon#end of sib2, iclass 7, count 0 2006.201.15:05:42.99#ibcon#*mode == 0, iclass 7, count 0 2006.201.15:05:42.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.15:05:42.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:05:42.99#ibcon#*before write, iclass 7, count 0 2006.201.15:05:42.99#ibcon#enter sib2, iclass 7, count 0 2006.201.15:05:42.99#ibcon#flushed, iclass 7, count 0 2006.201.15:05:42.99#ibcon#about to write, iclass 7, count 0 2006.201.15:05:42.99#ibcon#wrote, iclass 7, count 0 2006.201.15:05:42.99#ibcon#about to read 3, iclass 7, count 0 2006.201.15:05:43.04#ibcon#read 3, iclass 7, count 0 2006.201.15:05:43.04#ibcon#about to read 4, iclass 7, count 0 2006.201.15:05:43.04#ibcon#read 4, iclass 7, count 0 2006.201.15:05:43.04#ibcon#about to read 5, iclass 7, count 0 2006.201.15:05:43.04#ibcon#read 5, iclass 7, count 0 2006.201.15:05:43.04#ibcon#about to read 6, iclass 7, count 0 2006.201.15:05:43.04#ibcon#read 6, iclass 7, count 0 2006.201.15:05:43.04#ibcon#end of sib2, iclass 7, count 0 2006.201.15:05:43.04#ibcon#*after write, iclass 7, count 0 2006.201.15:05:43.04#ibcon#*before return 0, iclass 7, count 0 2006.201.15:05:43.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:43.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:05:43.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.15:05:43.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.15:05:43.04$vck44/vb=8,4 2006.201.15:05:43.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.15:05:43.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.15:05:43.04#ibcon#ireg 11 cls_cnt 2 2006.201.15:05:43.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:43.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:43.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:43.09#ibcon#enter wrdev, iclass 11, count 2 2006.201.15:05:43.09#ibcon#first serial, iclass 11, count 2 2006.201.15:05:43.09#ibcon#enter sib2, iclass 11, count 2 2006.201.15:05:43.09#ibcon#flushed, iclass 11, count 2 2006.201.15:05:43.09#ibcon#about to write, iclass 11, count 2 2006.201.15:05:43.09#ibcon#wrote, iclass 11, count 2 2006.201.15:05:43.09#ibcon#about to read 3, iclass 11, count 2 2006.201.15:05:43.11#ibcon#read 3, iclass 11, count 2 2006.201.15:05:43.11#ibcon#about to read 4, iclass 11, count 2 2006.201.15:05:43.11#ibcon#read 4, iclass 11, count 2 2006.201.15:05:43.11#ibcon#about to read 5, iclass 11, count 2 2006.201.15:05:43.11#ibcon#read 5, iclass 11, count 2 2006.201.15:05:43.11#ibcon#about to read 6, iclass 11, count 2 2006.201.15:05:43.11#ibcon#read 6, iclass 11, count 2 2006.201.15:05:43.11#ibcon#end of sib2, iclass 11, count 2 2006.201.15:05:43.11#ibcon#*mode == 0, iclass 11, count 2 2006.201.15:05:43.11#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.15:05:43.11#ibcon#[27=AT08-04\r\n] 2006.201.15:05:43.11#ibcon#*before write, iclass 11, count 2 2006.201.15:05:43.11#ibcon#enter sib2, iclass 11, count 2 2006.201.15:05:43.11#ibcon#flushed, iclass 11, count 2 2006.201.15:05:43.11#ibcon#about to write, iclass 11, count 2 2006.201.15:05:43.11#ibcon#wrote, iclass 11, count 2 2006.201.15:05:43.11#ibcon#about to read 3, iclass 11, count 2 2006.201.15:05:43.14#ibcon#read 3, iclass 11, count 2 2006.201.15:05:43.14#ibcon#about to read 4, iclass 11, count 2 2006.201.15:05:43.14#ibcon#read 4, iclass 11, count 2 2006.201.15:05:43.14#ibcon#about to read 5, iclass 11, count 2 2006.201.15:05:43.14#ibcon#read 5, iclass 11, count 2 2006.201.15:05:43.14#ibcon#about to read 6, iclass 11, count 2 2006.201.15:05:43.14#ibcon#read 6, iclass 11, count 2 2006.201.15:05:43.14#ibcon#end of sib2, iclass 11, count 2 2006.201.15:05:43.14#ibcon#*after write, iclass 11, count 2 2006.201.15:05:43.14#ibcon#*before return 0, iclass 11, count 2 2006.201.15:05:43.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:43.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:05:43.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.15:05:43.14#ibcon#ireg 7 cls_cnt 0 2006.201.15:05:43.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:43.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:43.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:43.26#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:05:43.26#ibcon#first serial, iclass 11, count 0 2006.201.15:05:43.26#ibcon#enter sib2, iclass 11, count 0 2006.201.15:05:43.26#ibcon#flushed, iclass 11, count 0 2006.201.15:05:43.26#ibcon#about to write, iclass 11, count 0 2006.201.15:05:43.26#ibcon#wrote, iclass 11, count 0 2006.201.15:05:43.26#ibcon#about to read 3, iclass 11, count 0 2006.201.15:05:43.28#ibcon#read 3, iclass 11, count 0 2006.201.15:05:43.28#ibcon#about to read 4, iclass 11, count 0 2006.201.15:05:43.28#ibcon#read 4, iclass 11, count 0 2006.201.15:05:43.28#ibcon#about to read 5, iclass 11, count 0 2006.201.15:05:43.28#ibcon#read 5, iclass 11, count 0 2006.201.15:05:43.28#ibcon#about to read 6, iclass 11, count 0 2006.201.15:05:43.28#ibcon#read 6, iclass 11, count 0 2006.201.15:05:43.28#ibcon#end of sib2, iclass 11, count 0 2006.201.15:05:43.28#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:05:43.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:05:43.28#ibcon#[27=USB\r\n] 2006.201.15:05:43.28#ibcon#*before write, iclass 11, count 0 2006.201.15:05:43.28#ibcon#enter sib2, iclass 11, count 0 2006.201.15:05:43.28#ibcon#flushed, iclass 11, count 0 2006.201.15:05:43.28#ibcon#about to write, iclass 11, count 0 2006.201.15:05:43.28#ibcon#wrote, iclass 11, count 0 2006.201.15:05:43.28#ibcon#about to read 3, iclass 11, count 0 2006.201.15:05:43.31#ibcon#read 3, iclass 11, count 0 2006.201.15:05:43.31#ibcon#about to read 4, iclass 11, count 0 2006.201.15:05:43.31#ibcon#read 4, iclass 11, count 0 2006.201.15:05:43.31#ibcon#about to read 5, iclass 11, count 0 2006.201.15:05:43.31#ibcon#read 5, iclass 11, count 0 2006.201.15:05:43.31#ibcon#about to read 6, iclass 11, count 0 2006.201.15:05:43.31#ibcon#read 6, iclass 11, count 0 2006.201.15:05:43.31#ibcon#end of sib2, iclass 11, count 0 2006.201.15:05:43.31#ibcon#*after write, iclass 11, count 0 2006.201.15:05:43.31#ibcon#*before return 0, iclass 11, count 0 2006.201.15:05:43.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:43.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:05:43.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:05:43.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:05:43.31$vck44/vabw=wide 2006.201.15:05:43.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.15:05:43.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.15:05:43.31#ibcon#ireg 8 cls_cnt 0 2006.201.15:05:43.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:43.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:43.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:43.31#ibcon#enter wrdev, iclass 13, count 0 2006.201.15:05:43.31#ibcon#first serial, iclass 13, count 0 2006.201.15:05:43.31#ibcon#enter sib2, iclass 13, count 0 2006.201.15:05:43.31#ibcon#flushed, iclass 13, count 0 2006.201.15:05:43.31#ibcon#about to write, iclass 13, count 0 2006.201.15:05:43.31#ibcon#wrote, iclass 13, count 0 2006.201.15:05:43.31#ibcon#about to read 3, iclass 13, count 0 2006.201.15:05:43.33#ibcon#read 3, iclass 13, count 0 2006.201.15:05:43.33#ibcon#about to read 4, iclass 13, count 0 2006.201.15:05:43.33#ibcon#read 4, iclass 13, count 0 2006.201.15:05:43.33#ibcon#about to read 5, iclass 13, count 0 2006.201.15:05:43.33#ibcon#read 5, iclass 13, count 0 2006.201.15:05:43.33#ibcon#about to read 6, iclass 13, count 0 2006.201.15:05:43.33#ibcon#read 6, iclass 13, count 0 2006.201.15:05:43.33#ibcon#end of sib2, iclass 13, count 0 2006.201.15:05:43.33#ibcon#*mode == 0, iclass 13, count 0 2006.201.15:05:43.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.15:05:43.33#ibcon#[25=BW32\r\n] 2006.201.15:05:43.33#ibcon#*before write, iclass 13, count 0 2006.201.15:05:43.33#ibcon#enter sib2, iclass 13, count 0 2006.201.15:05:43.33#ibcon#flushed, iclass 13, count 0 2006.201.15:05:43.33#ibcon#about to write, iclass 13, count 0 2006.201.15:05:43.33#ibcon#wrote, iclass 13, count 0 2006.201.15:05:43.33#ibcon#about to read 3, iclass 13, count 0 2006.201.15:05:43.36#ibcon#read 3, iclass 13, count 0 2006.201.15:05:43.36#ibcon#about to read 4, iclass 13, count 0 2006.201.15:05:43.36#ibcon#read 4, iclass 13, count 0 2006.201.15:05:43.36#ibcon#about to read 5, iclass 13, count 0 2006.201.15:05:43.36#ibcon#read 5, iclass 13, count 0 2006.201.15:05:43.36#ibcon#about to read 6, iclass 13, count 0 2006.201.15:05:43.36#ibcon#read 6, iclass 13, count 0 2006.201.15:05:43.36#ibcon#end of sib2, iclass 13, count 0 2006.201.15:05:43.36#ibcon#*after write, iclass 13, count 0 2006.201.15:05:43.36#ibcon#*before return 0, iclass 13, count 0 2006.201.15:05:43.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:43.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:05:43.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.15:05:43.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.15:05:43.36$vck44/vbbw=wide 2006.201.15:05:43.36#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.15:05:43.36#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.15:05:43.36#ibcon#ireg 8 cls_cnt 0 2006.201.15:05:43.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:05:43.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:05:43.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:05:43.43#ibcon#enter wrdev, iclass 15, count 0 2006.201.15:05:43.43#ibcon#first serial, iclass 15, count 0 2006.201.15:05:43.43#ibcon#enter sib2, iclass 15, count 0 2006.201.15:05:43.43#ibcon#flushed, iclass 15, count 0 2006.201.15:05:43.43#ibcon#about to write, iclass 15, count 0 2006.201.15:05:43.43#ibcon#wrote, iclass 15, count 0 2006.201.15:05:43.43#ibcon#about to read 3, iclass 15, count 0 2006.201.15:05:43.45#ibcon#read 3, iclass 15, count 0 2006.201.15:05:43.45#ibcon#about to read 4, iclass 15, count 0 2006.201.15:05:43.45#ibcon#read 4, iclass 15, count 0 2006.201.15:05:43.45#ibcon#about to read 5, iclass 15, count 0 2006.201.15:05:43.45#ibcon#read 5, iclass 15, count 0 2006.201.15:05:43.45#ibcon#about to read 6, iclass 15, count 0 2006.201.15:05:43.45#ibcon#read 6, iclass 15, count 0 2006.201.15:05:43.45#ibcon#end of sib2, iclass 15, count 0 2006.201.15:05:43.45#ibcon#*mode == 0, iclass 15, count 0 2006.201.15:05:43.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.15:05:43.45#ibcon#[27=BW32\r\n] 2006.201.15:05:43.45#ibcon#*before write, iclass 15, count 0 2006.201.15:05:43.45#ibcon#enter sib2, iclass 15, count 0 2006.201.15:05:43.45#ibcon#flushed, iclass 15, count 0 2006.201.15:05:43.45#ibcon#about to write, iclass 15, count 0 2006.201.15:05:43.45#ibcon#wrote, iclass 15, count 0 2006.201.15:05:43.45#ibcon#about to read 3, iclass 15, count 0 2006.201.15:05:43.48#ibcon#read 3, iclass 15, count 0 2006.201.15:05:43.48#ibcon#about to read 4, iclass 15, count 0 2006.201.15:05:43.48#ibcon#read 4, iclass 15, count 0 2006.201.15:05:43.48#ibcon#about to read 5, iclass 15, count 0 2006.201.15:05:43.48#ibcon#read 5, iclass 15, count 0 2006.201.15:05:43.48#ibcon#about to read 6, iclass 15, count 0 2006.201.15:05:43.48#ibcon#read 6, iclass 15, count 0 2006.201.15:05:43.48#ibcon#end of sib2, iclass 15, count 0 2006.201.15:05:43.48#ibcon#*after write, iclass 15, count 0 2006.201.15:05:43.48#ibcon#*before return 0, iclass 15, count 0 2006.201.15:05:43.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:05:43.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:05:43.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.15:05:43.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.15:05:43.48$setupk4/ifdk4 2006.201.15:05:43.48$ifdk4/lo= 2006.201.15:05:43.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:05:43.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:05:43.48$ifdk4/patch= 2006.201.15:05:43.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:05:43.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:05:43.48$setupk4/!*+20s 2006.201.15:05:48.06#abcon#<5=/04 0.9 1.9 20.771001003.3\r\n> 2006.201.15:05:48.08#abcon#{5=INTERFACE CLEAR} 2006.201.15:05:48.14#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:05:56.14#trakl#Source acquired 2006.201.15:05:57.14#flagr#flagr/antenna,acquired 2006.201.15:05:57.98$setupk4/"tpicd 2006.201.15:05:57.98$setupk4/echo=off 2006.201.15:05:57.98$setupk4/xlog=off 2006.201.15:05:57.98:!2006.201.15:06:34 2006.201.15:06:34.00:preob 2006.201.15:06:34.14/onsource/TRACKING 2006.201.15:06:34.14:!2006.201.15:06:44 2006.201.15:06:44.00:"tape 2006.201.15:06:44.00:"st=record 2006.201.15:06:44.00:data_valid=on 2006.201.15:06:44.00:midob 2006.201.15:06:45.14/onsource/TRACKING 2006.201.15:06:45.14/wx/20.77,1003.3,100 2006.201.15:06:45.20/cable/+6.4762E-03 2006.201.15:06:46.29/va/01,08,usb,yes,32,34 2006.201.15:06:46.29/va/02,07,usb,yes,35,35 2006.201.15:06:46.29/va/03,08,usb,yes,31,33 2006.201.15:06:46.29/va/04,07,usb,yes,36,37 2006.201.15:06:46.29/va/05,04,usb,yes,32,32 2006.201.15:06:46.29/va/06,05,usb,yes,32,32 2006.201.15:06:46.29/va/07,05,usb,yes,31,32 2006.201.15:06:46.29/va/08,04,usb,yes,30,37 2006.201.15:06:46.52/valo/01,524.99,yes,locked 2006.201.15:06:46.52/valo/02,534.99,yes,locked 2006.201.15:06:46.52/valo/03,564.99,yes,locked 2006.201.15:06:46.52/valo/04,624.99,yes,locked 2006.201.15:06:46.52/valo/05,734.99,yes,locked 2006.201.15:06:46.52/valo/06,814.99,yes,locked 2006.201.15:06:46.52/valo/07,864.99,yes,locked 2006.201.15:06:46.52/valo/08,884.99,yes,locked 2006.201.15:06:47.61/vb/01,04,usb,yes,30,28 2006.201.15:06:47.61/vb/02,05,usb,yes,28,28 2006.201.15:06:47.61/vb/03,04,usb,yes,29,32 2006.201.15:06:47.61/vb/04,05,usb,yes,30,29 2006.201.15:06:47.61/vb/05,04,usb,yes,26,29 2006.201.15:06:47.61/vb/06,04,usb,yes,31,27 2006.201.15:06:47.61/vb/07,04,usb,yes,30,30 2006.201.15:06:47.61/vb/08,04,usb,yes,28,31 2006.201.15:06:47.85/vblo/01,629.99,yes,locked 2006.201.15:06:47.85/vblo/02,634.99,yes,locked 2006.201.15:06:47.85/vblo/03,649.99,yes,locked 2006.201.15:06:47.85/vblo/04,679.99,yes,locked 2006.201.15:06:47.85/vblo/05,709.99,yes,locked 2006.201.15:06:47.85/vblo/06,719.99,yes,locked 2006.201.15:06:47.85/vblo/07,734.99,yes,locked 2006.201.15:06:47.85/vblo/08,744.99,yes,locked 2006.201.15:06:48.00/vabw/8 2006.201.15:06:48.15/vbbw/8 2006.201.15:06:48.26/xfe/off,on,15.0 2006.201.15:06:48.65/ifatt/23,28,28,28 2006.201.15:06:49.06/fmout-gps/S +4.56E-07 2006.201.15:06:49.13:!2006.201.15:07:24 2006.201.15:07:24.00:data_valid=off 2006.201.15:07:24.00:"et 2006.201.15:07:24.00:!+3s 2006.201.15:07:27.02:"tape 2006.201.15:07:27.02:postob 2006.201.15:07:27.08/cable/+6.4756E-03 2006.201.15:07:27.08/wx/20.77,1003.2,100 2006.201.15:07:27.16/fmout-gps/S +4.56E-07 2006.201.15:07:27.16:scan_name=201-1512,jd0607,120 2006.201.15:07:27.17:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.15:07:29.14#flagr#flagr/antenna,new-source 2006.201.15:07:29.14:checkk5 2006.201.15:07:29.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:07:29.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:07:30.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:07:30.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:07:31.00/chk_obsdata//k5ts1/T2011506??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.15:07:31.36/chk_obsdata//k5ts2/T2011506??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.15:07:31.73/chk_obsdata//k5ts3/T2011506??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.15:07:32.10/chk_obsdata//k5ts4/T2011506??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.15:07:32.80/k5log//k5ts1_log_newline 2006.201.15:07:33.48/k5log//k5ts2_log_newline 2006.201.15:07:34.17/k5log//k5ts3_log_newline 2006.201.15:07:34.87/k5log//k5ts4_log_newline 2006.201.15:07:34.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:07:34.90:setupk4=1 2006.201.15:07:34.90$setupk4/echo=on 2006.201.15:07:34.90$setupk4/pcalon 2006.201.15:07:34.90$pcalon/"no phase cal control is implemented here 2006.201.15:07:34.90$setupk4/"tpicd=stop 2006.201.15:07:34.90$setupk4/"rec=synch_on 2006.201.15:07:34.90$setupk4/"rec_mode=128 2006.201.15:07:34.90$setupk4/!* 2006.201.15:07:34.90$setupk4/recpk4 2006.201.15:07:34.90$recpk4/recpatch= 2006.201.15:07:34.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:07:34.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:07:34.90$setupk4/vck44 2006.201.15:07:34.90$vck44/valo=1,524.99 2006.201.15:07:34.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.15:07:34.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.15:07:34.90#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:34.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:34.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:34.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:34.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:07:34.90#ibcon#first serial, iclass 28, count 0 2006.201.15:07:34.90#ibcon#enter sib2, iclass 28, count 0 2006.201.15:07:34.90#ibcon#flushed, iclass 28, count 0 2006.201.15:07:34.90#ibcon#about to write, iclass 28, count 0 2006.201.15:07:34.90#ibcon#wrote, iclass 28, count 0 2006.201.15:07:34.90#ibcon#about to read 3, iclass 28, count 0 2006.201.15:07:34.92#ibcon#read 3, iclass 28, count 0 2006.201.15:07:34.92#ibcon#about to read 4, iclass 28, count 0 2006.201.15:07:34.92#ibcon#read 4, iclass 28, count 0 2006.201.15:07:34.92#ibcon#about to read 5, iclass 28, count 0 2006.201.15:07:34.92#ibcon#read 5, iclass 28, count 0 2006.201.15:07:34.92#ibcon#about to read 6, iclass 28, count 0 2006.201.15:07:34.92#ibcon#read 6, iclass 28, count 0 2006.201.15:07:34.92#ibcon#end of sib2, iclass 28, count 0 2006.201.15:07:34.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:07:34.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:07:34.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:07:34.92#ibcon#*before write, iclass 28, count 0 2006.201.15:07:34.92#ibcon#enter sib2, iclass 28, count 0 2006.201.15:07:34.92#ibcon#flushed, iclass 28, count 0 2006.201.15:07:34.92#ibcon#about to write, iclass 28, count 0 2006.201.15:07:34.92#ibcon#wrote, iclass 28, count 0 2006.201.15:07:34.92#ibcon#about to read 3, iclass 28, count 0 2006.201.15:07:34.97#ibcon#read 3, iclass 28, count 0 2006.201.15:07:34.97#ibcon#about to read 4, iclass 28, count 0 2006.201.15:07:34.97#ibcon#read 4, iclass 28, count 0 2006.201.15:07:34.97#ibcon#about to read 5, iclass 28, count 0 2006.201.15:07:34.97#ibcon#read 5, iclass 28, count 0 2006.201.15:07:34.97#ibcon#about to read 6, iclass 28, count 0 2006.201.15:07:34.97#ibcon#read 6, iclass 28, count 0 2006.201.15:07:34.97#ibcon#end of sib2, iclass 28, count 0 2006.201.15:07:34.97#ibcon#*after write, iclass 28, count 0 2006.201.15:07:34.97#ibcon#*before return 0, iclass 28, count 0 2006.201.15:07:34.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:34.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:34.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:07:34.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:07:34.97$vck44/va=1,8 2006.201.15:07:34.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.15:07:34.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.15:07:34.97#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:34.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:34.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:34.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:34.97#ibcon#enter wrdev, iclass 30, count 2 2006.201.15:07:34.97#ibcon#first serial, iclass 30, count 2 2006.201.15:07:34.97#ibcon#enter sib2, iclass 30, count 2 2006.201.15:07:34.97#ibcon#flushed, iclass 30, count 2 2006.201.15:07:34.97#ibcon#about to write, iclass 30, count 2 2006.201.15:07:34.97#ibcon#wrote, iclass 30, count 2 2006.201.15:07:34.97#ibcon#about to read 3, iclass 30, count 2 2006.201.15:07:34.99#ibcon#read 3, iclass 30, count 2 2006.201.15:07:34.99#ibcon#about to read 4, iclass 30, count 2 2006.201.15:07:34.99#ibcon#read 4, iclass 30, count 2 2006.201.15:07:34.99#ibcon#about to read 5, iclass 30, count 2 2006.201.15:07:34.99#ibcon#read 5, iclass 30, count 2 2006.201.15:07:34.99#ibcon#about to read 6, iclass 30, count 2 2006.201.15:07:34.99#ibcon#read 6, iclass 30, count 2 2006.201.15:07:34.99#ibcon#end of sib2, iclass 30, count 2 2006.201.15:07:34.99#ibcon#*mode == 0, iclass 30, count 2 2006.201.15:07:34.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.15:07:34.99#ibcon#[25=AT01-08\r\n] 2006.201.15:07:34.99#ibcon#*before write, iclass 30, count 2 2006.201.15:07:34.99#ibcon#enter sib2, iclass 30, count 2 2006.201.15:07:34.99#ibcon#flushed, iclass 30, count 2 2006.201.15:07:34.99#ibcon#about to write, iclass 30, count 2 2006.201.15:07:34.99#ibcon#wrote, iclass 30, count 2 2006.201.15:07:34.99#ibcon#about to read 3, iclass 30, count 2 2006.201.15:07:35.02#ibcon#read 3, iclass 30, count 2 2006.201.15:07:35.02#ibcon#about to read 4, iclass 30, count 2 2006.201.15:07:35.02#ibcon#read 4, iclass 30, count 2 2006.201.15:07:35.02#ibcon#about to read 5, iclass 30, count 2 2006.201.15:07:35.02#ibcon#read 5, iclass 30, count 2 2006.201.15:07:35.02#ibcon#about to read 6, iclass 30, count 2 2006.201.15:07:35.02#ibcon#read 6, iclass 30, count 2 2006.201.15:07:35.02#ibcon#end of sib2, iclass 30, count 2 2006.201.15:07:35.02#ibcon#*after write, iclass 30, count 2 2006.201.15:07:35.02#ibcon#*before return 0, iclass 30, count 2 2006.201.15:07:35.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:35.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:35.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.15:07:35.02#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:35.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:35.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:35.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:35.14#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:07:35.14#ibcon#first serial, iclass 30, count 0 2006.201.15:07:35.14#ibcon#enter sib2, iclass 30, count 0 2006.201.15:07:35.14#ibcon#flushed, iclass 30, count 0 2006.201.15:07:35.14#ibcon#about to write, iclass 30, count 0 2006.201.15:07:35.14#ibcon#wrote, iclass 30, count 0 2006.201.15:07:35.14#ibcon#about to read 3, iclass 30, count 0 2006.201.15:07:35.16#ibcon#read 3, iclass 30, count 0 2006.201.15:07:35.16#ibcon#about to read 4, iclass 30, count 0 2006.201.15:07:35.16#ibcon#read 4, iclass 30, count 0 2006.201.15:07:35.16#ibcon#about to read 5, iclass 30, count 0 2006.201.15:07:35.16#ibcon#read 5, iclass 30, count 0 2006.201.15:07:35.16#ibcon#about to read 6, iclass 30, count 0 2006.201.15:07:35.16#ibcon#read 6, iclass 30, count 0 2006.201.15:07:35.16#ibcon#end of sib2, iclass 30, count 0 2006.201.15:07:35.16#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:07:35.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:07:35.16#ibcon#[25=USB\r\n] 2006.201.15:07:35.16#ibcon#*before write, iclass 30, count 0 2006.201.15:07:35.16#ibcon#enter sib2, iclass 30, count 0 2006.201.15:07:35.16#ibcon#flushed, iclass 30, count 0 2006.201.15:07:35.16#ibcon#about to write, iclass 30, count 0 2006.201.15:07:35.16#ibcon#wrote, iclass 30, count 0 2006.201.15:07:35.16#ibcon#about to read 3, iclass 30, count 0 2006.201.15:07:35.19#ibcon#read 3, iclass 30, count 0 2006.201.15:07:35.19#ibcon#about to read 4, iclass 30, count 0 2006.201.15:07:35.19#ibcon#read 4, iclass 30, count 0 2006.201.15:07:35.19#ibcon#about to read 5, iclass 30, count 0 2006.201.15:07:35.19#ibcon#read 5, iclass 30, count 0 2006.201.15:07:35.19#ibcon#about to read 6, iclass 30, count 0 2006.201.15:07:35.19#ibcon#read 6, iclass 30, count 0 2006.201.15:07:35.19#ibcon#end of sib2, iclass 30, count 0 2006.201.15:07:35.19#ibcon#*after write, iclass 30, count 0 2006.201.15:07:35.19#ibcon#*before return 0, iclass 30, count 0 2006.201.15:07:35.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:35.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:35.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:07:35.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:07:35.19$vck44/valo=2,534.99 2006.201.15:07:35.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.15:07:35.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.15:07:35.19#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:35.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:35.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:35.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:35.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:07:35.19#ibcon#first serial, iclass 32, count 0 2006.201.15:07:35.19#ibcon#enter sib2, iclass 32, count 0 2006.201.15:07:35.19#ibcon#flushed, iclass 32, count 0 2006.201.15:07:35.19#ibcon#about to write, iclass 32, count 0 2006.201.15:07:35.19#ibcon#wrote, iclass 32, count 0 2006.201.15:07:35.19#ibcon#about to read 3, iclass 32, count 0 2006.201.15:07:35.21#ibcon#read 3, iclass 32, count 0 2006.201.15:07:35.21#ibcon#about to read 4, iclass 32, count 0 2006.201.15:07:35.21#ibcon#read 4, iclass 32, count 0 2006.201.15:07:35.21#ibcon#about to read 5, iclass 32, count 0 2006.201.15:07:35.21#ibcon#read 5, iclass 32, count 0 2006.201.15:07:35.21#ibcon#about to read 6, iclass 32, count 0 2006.201.15:07:35.21#ibcon#read 6, iclass 32, count 0 2006.201.15:07:35.21#ibcon#end of sib2, iclass 32, count 0 2006.201.15:07:35.21#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:07:35.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:07:35.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:07:35.21#ibcon#*before write, iclass 32, count 0 2006.201.15:07:35.21#ibcon#enter sib2, iclass 32, count 0 2006.201.15:07:35.21#ibcon#flushed, iclass 32, count 0 2006.201.15:07:35.21#ibcon#about to write, iclass 32, count 0 2006.201.15:07:35.21#ibcon#wrote, iclass 32, count 0 2006.201.15:07:35.21#ibcon#about to read 3, iclass 32, count 0 2006.201.15:07:35.26#ibcon#read 3, iclass 32, count 0 2006.201.15:07:35.26#ibcon#about to read 4, iclass 32, count 0 2006.201.15:07:35.26#ibcon#read 4, iclass 32, count 0 2006.201.15:07:35.26#ibcon#about to read 5, iclass 32, count 0 2006.201.15:07:35.26#ibcon#read 5, iclass 32, count 0 2006.201.15:07:35.26#ibcon#about to read 6, iclass 32, count 0 2006.201.15:07:35.26#ibcon#read 6, iclass 32, count 0 2006.201.15:07:35.26#ibcon#end of sib2, iclass 32, count 0 2006.201.15:07:35.26#ibcon#*after write, iclass 32, count 0 2006.201.15:07:35.26#ibcon#*before return 0, iclass 32, count 0 2006.201.15:07:35.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:35.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:35.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:07:35.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:07:35.26$vck44/va=2,7 2006.201.15:07:35.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.15:07:35.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.15:07:35.26#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:35.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:35.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:35.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:35.31#ibcon#enter wrdev, iclass 34, count 2 2006.201.15:07:35.31#ibcon#first serial, iclass 34, count 2 2006.201.15:07:35.31#ibcon#enter sib2, iclass 34, count 2 2006.201.15:07:35.31#ibcon#flushed, iclass 34, count 2 2006.201.15:07:35.31#ibcon#about to write, iclass 34, count 2 2006.201.15:07:35.31#ibcon#wrote, iclass 34, count 2 2006.201.15:07:35.31#ibcon#about to read 3, iclass 34, count 2 2006.201.15:07:35.33#ibcon#read 3, iclass 34, count 2 2006.201.15:07:35.33#ibcon#about to read 4, iclass 34, count 2 2006.201.15:07:35.33#ibcon#read 4, iclass 34, count 2 2006.201.15:07:35.33#ibcon#about to read 5, iclass 34, count 2 2006.201.15:07:35.33#ibcon#read 5, iclass 34, count 2 2006.201.15:07:35.33#ibcon#about to read 6, iclass 34, count 2 2006.201.15:07:35.33#ibcon#read 6, iclass 34, count 2 2006.201.15:07:35.33#ibcon#end of sib2, iclass 34, count 2 2006.201.15:07:35.33#ibcon#*mode == 0, iclass 34, count 2 2006.201.15:07:35.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.15:07:35.33#ibcon#[25=AT02-07\r\n] 2006.201.15:07:35.33#ibcon#*before write, iclass 34, count 2 2006.201.15:07:35.33#ibcon#enter sib2, iclass 34, count 2 2006.201.15:07:35.33#ibcon#flushed, iclass 34, count 2 2006.201.15:07:35.33#ibcon#about to write, iclass 34, count 2 2006.201.15:07:35.33#ibcon#wrote, iclass 34, count 2 2006.201.15:07:35.33#ibcon#about to read 3, iclass 34, count 2 2006.201.15:07:35.36#ibcon#read 3, iclass 34, count 2 2006.201.15:07:35.36#ibcon#about to read 4, iclass 34, count 2 2006.201.15:07:35.36#ibcon#read 4, iclass 34, count 2 2006.201.15:07:35.36#ibcon#about to read 5, iclass 34, count 2 2006.201.15:07:35.36#ibcon#read 5, iclass 34, count 2 2006.201.15:07:35.36#ibcon#about to read 6, iclass 34, count 2 2006.201.15:07:35.36#ibcon#read 6, iclass 34, count 2 2006.201.15:07:35.36#ibcon#end of sib2, iclass 34, count 2 2006.201.15:07:35.36#ibcon#*after write, iclass 34, count 2 2006.201.15:07:35.36#ibcon#*before return 0, iclass 34, count 2 2006.201.15:07:35.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:35.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:35.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.15:07:35.36#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:35.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:35.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:35.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:35.48#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:07:35.48#ibcon#first serial, iclass 34, count 0 2006.201.15:07:35.48#ibcon#enter sib2, iclass 34, count 0 2006.201.15:07:35.48#ibcon#flushed, iclass 34, count 0 2006.201.15:07:35.48#ibcon#about to write, iclass 34, count 0 2006.201.15:07:35.48#ibcon#wrote, iclass 34, count 0 2006.201.15:07:35.48#ibcon#about to read 3, iclass 34, count 0 2006.201.15:07:35.50#ibcon#read 3, iclass 34, count 0 2006.201.15:07:35.50#ibcon#about to read 4, iclass 34, count 0 2006.201.15:07:35.50#ibcon#read 4, iclass 34, count 0 2006.201.15:07:35.50#ibcon#about to read 5, iclass 34, count 0 2006.201.15:07:35.50#ibcon#read 5, iclass 34, count 0 2006.201.15:07:35.50#ibcon#about to read 6, iclass 34, count 0 2006.201.15:07:35.50#ibcon#read 6, iclass 34, count 0 2006.201.15:07:35.50#ibcon#end of sib2, iclass 34, count 0 2006.201.15:07:35.50#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:07:35.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:07:35.50#ibcon#[25=USB\r\n] 2006.201.15:07:35.50#ibcon#*before write, iclass 34, count 0 2006.201.15:07:35.50#ibcon#enter sib2, iclass 34, count 0 2006.201.15:07:35.50#ibcon#flushed, iclass 34, count 0 2006.201.15:07:35.50#ibcon#about to write, iclass 34, count 0 2006.201.15:07:35.50#ibcon#wrote, iclass 34, count 0 2006.201.15:07:35.50#ibcon#about to read 3, iclass 34, count 0 2006.201.15:07:35.53#ibcon#read 3, iclass 34, count 0 2006.201.15:07:35.53#ibcon#about to read 4, iclass 34, count 0 2006.201.15:07:35.53#ibcon#read 4, iclass 34, count 0 2006.201.15:07:35.53#ibcon#about to read 5, iclass 34, count 0 2006.201.15:07:35.53#ibcon#read 5, iclass 34, count 0 2006.201.15:07:35.53#ibcon#about to read 6, iclass 34, count 0 2006.201.15:07:35.53#ibcon#read 6, iclass 34, count 0 2006.201.15:07:35.53#ibcon#end of sib2, iclass 34, count 0 2006.201.15:07:35.53#ibcon#*after write, iclass 34, count 0 2006.201.15:07:35.53#ibcon#*before return 0, iclass 34, count 0 2006.201.15:07:35.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:35.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:35.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:07:35.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:07:35.53$vck44/valo=3,564.99 2006.201.15:07:35.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.15:07:35.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.15:07:35.53#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:35.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:35.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:35.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:35.53#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:07:35.53#ibcon#first serial, iclass 36, count 0 2006.201.15:07:35.53#ibcon#enter sib2, iclass 36, count 0 2006.201.15:07:35.53#ibcon#flushed, iclass 36, count 0 2006.201.15:07:35.53#ibcon#about to write, iclass 36, count 0 2006.201.15:07:35.53#ibcon#wrote, iclass 36, count 0 2006.201.15:07:35.53#ibcon#about to read 3, iclass 36, count 0 2006.201.15:07:35.55#ibcon#read 3, iclass 36, count 0 2006.201.15:07:35.55#ibcon#about to read 4, iclass 36, count 0 2006.201.15:07:35.55#ibcon#read 4, iclass 36, count 0 2006.201.15:07:35.55#ibcon#about to read 5, iclass 36, count 0 2006.201.15:07:35.55#ibcon#read 5, iclass 36, count 0 2006.201.15:07:35.55#ibcon#about to read 6, iclass 36, count 0 2006.201.15:07:35.55#ibcon#read 6, iclass 36, count 0 2006.201.15:07:35.55#ibcon#end of sib2, iclass 36, count 0 2006.201.15:07:35.55#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:07:35.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:07:35.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:07:35.55#ibcon#*before write, iclass 36, count 0 2006.201.15:07:35.55#ibcon#enter sib2, iclass 36, count 0 2006.201.15:07:35.55#ibcon#flushed, iclass 36, count 0 2006.201.15:07:35.55#ibcon#about to write, iclass 36, count 0 2006.201.15:07:35.55#ibcon#wrote, iclass 36, count 0 2006.201.15:07:35.55#ibcon#about to read 3, iclass 36, count 0 2006.201.15:07:35.59#ibcon#read 3, iclass 36, count 0 2006.201.15:07:35.59#ibcon#about to read 4, iclass 36, count 0 2006.201.15:07:35.59#ibcon#read 4, iclass 36, count 0 2006.201.15:07:35.59#ibcon#about to read 5, iclass 36, count 0 2006.201.15:07:35.59#ibcon#read 5, iclass 36, count 0 2006.201.15:07:35.59#ibcon#about to read 6, iclass 36, count 0 2006.201.15:07:35.59#ibcon#read 6, iclass 36, count 0 2006.201.15:07:35.59#ibcon#end of sib2, iclass 36, count 0 2006.201.15:07:35.59#ibcon#*after write, iclass 36, count 0 2006.201.15:07:35.59#ibcon#*before return 0, iclass 36, count 0 2006.201.15:07:35.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:35.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:35.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:07:35.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:07:35.59$vck44/va=3,8 2006.201.15:07:35.59#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.15:07:35.59#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.15:07:35.59#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:35.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:35.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:35.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:35.65#ibcon#enter wrdev, iclass 38, count 2 2006.201.15:07:35.65#ibcon#first serial, iclass 38, count 2 2006.201.15:07:35.65#ibcon#enter sib2, iclass 38, count 2 2006.201.15:07:35.65#ibcon#flushed, iclass 38, count 2 2006.201.15:07:35.65#ibcon#about to write, iclass 38, count 2 2006.201.15:07:35.65#ibcon#wrote, iclass 38, count 2 2006.201.15:07:35.65#ibcon#about to read 3, iclass 38, count 2 2006.201.15:07:35.67#ibcon#read 3, iclass 38, count 2 2006.201.15:07:35.67#ibcon#about to read 4, iclass 38, count 2 2006.201.15:07:35.67#ibcon#read 4, iclass 38, count 2 2006.201.15:07:35.67#ibcon#about to read 5, iclass 38, count 2 2006.201.15:07:35.67#ibcon#read 5, iclass 38, count 2 2006.201.15:07:35.67#ibcon#about to read 6, iclass 38, count 2 2006.201.15:07:35.67#ibcon#read 6, iclass 38, count 2 2006.201.15:07:35.67#ibcon#end of sib2, iclass 38, count 2 2006.201.15:07:35.67#ibcon#*mode == 0, iclass 38, count 2 2006.201.15:07:35.67#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.15:07:35.67#ibcon#[25=AT03-08\r\n] 2006.201.15:07:35.67#ibcon#*before write, iclass 38, count 2 2006.201.15:07:35.67#ibcon#enter sib2, iclass 38, count 2 2006.201.15:07:35.67#ibcon#flushed, iclass 38, count 2 2006.201.15:07:35.67#ibcon#about to write, iclass 38, count 2 2006.201.15:07:35.67#ibcon#wrote, iclass 38, count 2 2006.201.15:07:35.67#ibcon#about to read 3, iclass 38, count 2 2006.201.15:07:35.70#ibcon#read 3, iclass 38, count 2 2006.201.15:07:35.70#ibcon#about to read 4, iclass 38, count 2 2006.201.15:07:35.70#ibcon#read 4, iclass 38, count 2 2006.201.15:07:35.70#ibcon#about to read 5, iclass 38, count 2 2006.201.15:07:35.70#ibcon#read 5, iclass 38, count 2 2006.201.15:07:35.70#ibcon#about to read 6, iclass 38, count 2 2006.201.15:07:35.70#ibcon#read 6, iclass 38, count 2 2006.201.15:07:35.70#ibcon#end of sib2, iclass 38, count 2 2006.201.15:07:35.70#ibcon#*after write, iclass 38, count 2 2006.201.15:07:35.70#ibcon#*before return 0, iclass 38, count 2 2006.201.15:07:35.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:35.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:35.70#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.15:07:35.70#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:35.70#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:35.82#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:35.82#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:35.82#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:07:35.82#ibcon#first serial, iclass 38, count 0 2006.201.15:07:35.82#ibcon#enter sib2, iclass 38, count 0 2006.201.15:07:35.82#ibcon#flushed, iclass 38, count 0 2006.201.15:07:35.82#ibcon#about to write, iclass 38, count 0 2006.201.15:07:35.82#ibcon#wrote, iclass 38, count 0 2006.201.15:07:35.82#ibcon#about to read 3, iclass 38, count 0 2006.201.15:07:35.84#ibcon#read 3, iclass 38, count 0 2006.201.15:07:35.84#ibcon#about to read 4, iclass 38, count 0 2006.201.15:07:35.84#ibcon#read 4, iclass 38, count 0 2006.201.15:07:35.84#ibcon#about to read 5, iclass 38, count 0 2006.201.15:07:35.84#ibcon#read 5, iclass 38, count 0 2006.201.15:07:35.84#ibcon#about to read 6, iclass 38, count 0 2006.201.15:07:35.84#ibcon#read 6, iclass 38, count 0 2006.201.15:07:35.84#ibcon#end of sib2, iclass 38, count 0 2006.201.15:07:35.84#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:07:35.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:07:35.84#ibcon#[25=USB\r\n] 2006.201.15:07:35.84#ibcon#*before write, iclass 38, count 0 2006.201.15:07:35.84#ibcon#enter sib2, iclass 38, count 0 2006.201.15:07:35.84#ibcon#flushed, iclass 38, count 0 2006.201.15:07:35.84#ibcon#about to write, iclass 38, count 0 2006.201.15:07:35.84#ibcon#wrote, iclass 38, count 0 2006.201.15:07:35.84#ibcon#about to read 3, iclass 38, count 0 2006.201.15:07:35.87#ibcon#read 3, iclass 38, count 0 2006.201.15:07:35.87#ibcon#about to read 4, iclass 38, count 0 2006.201.15:07:35.87#ibcon#read 4, iclass 38, count 0 2006.201.15:07:35.87#ibcon#about to read 5, iclass 38, count 0 2006.201.15:07:35.87#ibcon#read 5, iclass 38, count 0 2006.201.15:07:35.87#ibcon#about to read 6, iclass 38, count 0 2006.201.15:07:35.87#ibcon#read 6, iclass 38, count 0 2006.201.15:07:35.87#ibcon#end of sib2, iclass 38, count 0 2006.201.15:07:35.87#ibcon#*after write, iclass 38, count 0 2006.201.15:07:35.87#ibcon#*before return 0, iclass 38, count 0 2006.201.15:07:35.87#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:35.87#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:35.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:07:35.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:07:35.87$vck44/valo=4,624.99 2006.201.15:07:35.87#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.15:07:35.87#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.15:07:35.87#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:35.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:35.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:35.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:35.87#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:07:35.87#ibcon#first serial, iclass 40, count 0 2006.201.15:07:35.87#ibcon#enter sib2, iclass 40, count 0 2006.201.15:07:35.87#ibcon#flushed, iclass 40, count 0 2006.201.15:07:35.87#ibcon#about to write, iclass 40, count 0 2006.201.15:07:35.87#ibcon#wrote, iclass 40, count 0 2006.201.15:07:35.87#ibcon#about to read 3, iclass 40, count 0 2006.201.15:07:35.89#ibcon#read 3, iclass 40, count 0 2006.201.15:07:35.89#ibcon#about to read 4, iclass 40, count 0 2006.201.15:07:35.89#ibcon#read 4, iclass 40, count 0 2006.201.15:07:35.89#ibcon#about to read 5, iclass 40, count 0 2006.201.15:07:35.89#ibcon#read 5, iclass 40, count 0 2006.201.15:07:35.89#ibcon#about to read 6, iclass 40, count 0 2006.201.15:07:35.89#ibcon#read 6, iclass 40, count 0 2006.201.15:07:35.89#ibcon#end of sib2, iclass 40, count 0 2006.201.15:07:35.89#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:07:35.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:07:35.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:07:35.89#ibcon#*before write, iclass 40, count 0 2006.201.15:07:35.89#ibcon#enter sib2, iclass 40, count 0 2006.201.15:07:35.89#ibcon#flushed, iclass 40, count 0 2006.201.15:07:35.89#ibcon#about to write, iclass 40, count 0 2006.201.15:07:35.89#ibcon#wrote, iclass 40, count 0 2006.201.15:07:35.89#ibcon#about to read 3, iclass 40, count 0 2006.201.15:07:35.94#ibcon#read 3, iclass 40, count 0 2006.201.15:07:35.94#ibcon#about to read 4, iclass 40, count 0 2006.201.15:07:35.94#ibcon#read 4, iclass 40, count 0 2006.201.15:07:35.94#ibcon#about to read 5, iclass 40, count 0 2006.201.15:07:35.94#ibcon#read 5, iclass 40, count 0 2006.201.15:07:35.94#ibcon#about to read 6, iclass 40, count 0 2006.201.15:07:35.94#ibcon#read 6, iclass 40, count 0 2006.201.15:07:35.94#ibcon#end of sib2, iclass 40, count 0 2006.201.15:07:35.94#ibcon#*after write, iclass 40, count 0 2006.201.15:07:35.94#ibcon#*before return 0, iclass 40, count 0 2006.201.15:07:35.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:35.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:35.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:07:35.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:07:35.94$vck44/va=4,7 2006.201.15:07:35.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.15:07:35.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.15:07:35.94#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:35.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:35.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:35.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:35.99#ibcon#enter wrdev, iclass 4, count 2 2006.201.15:07:35.99#ibcon#first serial, iclass 4, count 2 2006.201.15:07:35.99#ibcon#enter sib2, iclass 4, count 2 2006.201.15:07:35.99#ibcon#flushed, iclass 4, count 2 2006.201.15:07:35.99#ibcon#about to write, iclass 4, count 2 2006.201.15:07:35.99#ibcon#wrote, iclass 4, count 2 2006.201.15:07:35.99#ibcon#about to read 3, iclass 4, count 2 2006.201.15:07:36.01#ibcon#read 3, iclass 4, count 2 2006.201.15:07:36.01#ibcon#about to read 4, iclass 4, count 2 2006.201.15:07:36.01#ibcon#read 4, iclass 4, count 2 2006.201.15:07:36.01#ibcon#about to read 5, iclass 4, count 2 2006.201.15:07:36.01#ibcon#read 5, iclass 4, count 2 2006.201.15:07:36.01#ibcon#about to read 6, iclass 4, count 2 2006.201.15:07:36.01#ibcon#read 6, iclass 4, count 2 2006.201.15:07:36.01#ibcon#end of sib2, iclass 4, count 2 2006.201.15:07:36.01#ibcon#*mode == 0, iclass 4, count 2 2006.201.15:07:36.01#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.15:07:36.01#ibcon#[25=AT04-07\r\n] 2006.201.15:07:36.01#ibcon#*before write, iclass 4, count 2 2006.201.15:07:36.01#ibcon#enter sib2, iclass 4, count 2 2006.201.15:07:36.01#ibcon#flushed, iclass 4, count 2 2006.201.15:07:36.01#ibcon#about to write, iclass 4, count 2 2006.201.15:07:36.01#ibcon#wrote, iclass 4, count 2 2006.201.15:07:36.01#ibcon#about to read 3, iclass 4, count 2 2006.201.15:07:36.04#ibcon#read 3, iclass 4, count 2 2006.201.15:07:36.04#ibcon#about to read 4, iclass 4, count 2 2006.201.15:07:36.04#ibcon#read 4, iclass 4, count 2 2006.201.15:07:36.04#ibcon#about to read 5, iclass 4, count 2 2006.201.15:07:36.04#ibcon#read 5, iclass 4, count 2 2006.201.15:07:36.04#ibcon#about to read 6, iclass 4, count 2 2006.201.15:07:36.04#ibcon#read 6, iclass 4, count 2 2006.201.15:07:36.04#ibcon#end of sib2, iclass 4, count 2 2006.201.15:07:36.04#ibcon#*after write, iclass 4, count 2 2006.201.15:07:36.04#ibcon#*before return 0, iclass 4, count 2 2006.201.15:07:36.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:36.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:36.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.15:07:36.04#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:36.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:36.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:36.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:36.16#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:07:36.16#ibcon#first serial, iclass 4, count 0 2006.201.15:07:36.16#ibcon#enter sib2, iclass 4, count 0 2006.201.15:07:36.16#ibcon#flushed, iclass 4, count 0 2006.201.15:07:36.16#ibcon#about to write, iclass 4, count 0 2006.201.15:07:36.16#ibcon#wrote, iclass 4, count 0 2006.201.15:07:36.16#ibcon#about to read 3, iclass 4, count 0 2006.201.15:07:36.18#ibcon#read 3, iclass 4, count 0 2006.201.15:07:36.18#ibcon#about to read 4, iclass 4, count 0 2006.201.15:07:36.18#ibcon#read 4, iclass 4, count 0 2006.201.15:07:36.18#ibcon#about to read 5, iclass 4, count 0 2006.201.15:07:36.18#ibcon#read 5, iclass 4, count 0 2006.201.15:07:36.18#ibcon#about to read 6, iclass 4, count 0 2006.201.15:07:36.18#ibcon#read 6, iclass 4, count 0 2006.201.15:07:36.18#ibcon#end of sib2, iclass 4, count 0 2006.201.15:07:36.18#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:07:36.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:07:36.18#ibcon#[25=USB\r\n] 2006.201.15:07:36.18#ibcon#*before write, iclass 4, count 0 2006.201.15:07:36.18#ibcon#enter sib2, iclass 4, count 0 2006.201.15:07:36.18#ibcon#flushed, iclass 4, count 0 2006.201.15:07:36.18#ibcon#about to write, iclass 4, count 0 2006.201.15:07:36.18#ibcon#wrote, iclass 4, count 0 2006.201.15:07:36.18#ibcon#about to read 3, iclass 4, count 0 2006.201.15:07:36.21#ibcon#read 3, iclass 4, count 0 2006.201.15:07:36.21#ibcon#about to read 4, iclass 4, count 0 2006.201.15:07:36.21#ibcon#read 4, iclass 4, count 0 2006.201.15:07:36.21#ibcon#about to read 5, iclass 4, count 0 2006.201.15:07:36.21#ibcon#read 5, iclass 4, count 0 2006.201.15:07:36.21#ibcon#about to read 6, iclass 4, count 0 2006.201.15:07:36.21#ibcon#read 6, iclass 4, count 0 2006.201.15:07:36.21#ibcon#end of sib2, iclass 4, count 0 2006.201.15:07:36.21#ibcon#*after write, iclass 4, count 0 2006.201.15:07:36.21#ibcon#*before return 0, iclass 4, count 0 2006.201.15:07:36.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:36.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:36.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:07:36.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:07:36.21$vck44/valo=5,734.99 2006.201.15:07:36.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.15:07:36.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.15:07:36.21#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:36.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:36.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:36.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:36.21#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:07:36.21#ibcon#first serial, iclass 6, count 0 2006.201.15:07:36.21#ibcon#enter sib2, iclass 6, count 0 2006.201.15:07:36.21#ibcon#flushed, iclass 6, count 0 2006.201.15:07:36.21#ibcon#about to write, iclass 6, count 0 2006.201.15:07:36.21#ibcon#wrote, iclass 6, count 0 2006.201.15:07:36.21#ibcon#about to read 3, iclass 6, count 0 2006.201.15:07:36.23#ibcon#read 3, iclass 6, count 0 2006.201.15:07:36.23#ibcon#about to read 4, iclass 6, count 0 2006.201.15:07:36.23#ibcon#read 4, iclass 6, count 0 2006.201.15:07:36.23#ibcon#about to read 5, iclass 6, count 0 2006.201.15:07:36.23#ibcon#read 5, iclass 6, count 0 2006.201.15:07:36.23#ibcon#about to read 6, iclass 6, count 0 2006.201.15:07:36.23#ibcon#read 6, iclass 6, count 0 2006.201.15:07:36.23#ibcon#end of sib2, iclass 6, count 0 2006.201.15:07:36.23#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:07:36.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:07:36.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:07:36.23#ibcon#*before write, iclass 6, count 0 2006.201.15:07:36.23#ibcon#enter sib2, iclass 6, count 0 2006.201.15:07:36.23#ibcon#flushed, iclass 6, count 0 2006.201.15:07:36.23#ibcon#about to write, iclass 6, count 0 2006.201.15:07:36.23#ibcon#wrote, iclass 6, count 0 2006.201.15:07:36.23#ibcon#about to read 3, iclass 6, count 0 2006.201.15:07:36.27#ibcon#read 3, iclass 6, count 0 2006.201.15:07:36.27#ibcon#about to read 4, iclass 6, count 0 2006.201.15:07:36.27#ibcon#read 4, iclass 6, count 0 2006.201.15:07:36.27#ibcon#about to read 5, iclass 6, count 0 2006.201.15:07:36.27#ibcon#read 5, iclass 6, count 0 2006.201.15:07:36.27#ibcon#about to read 6, iclass 6, count 0 2006.201.15:07:36.27#ibcon#read 6, iclass 6, count 0 2006.201.15:07:36.27#ibcon#end of sib2, iclass 6, count 0 2006.201.15:07:36.27#ibcon#*after write, iclass 6, count 0 2006.201.15:07:36.27#ibcon#*before return 0, iclass 6, count 0 2006.201.15:07:36.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:36.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:36.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:07:36.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:07:36.27$vck44/va=5,4 2006.201.15:07:36.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.15:07:36.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.15:07:36.27#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:36.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:36.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:36.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:36.33#ibcon#enter wrdev, iclass 10, count 2 2006.201.15:07:36.33#ibcon#first serial, iclass 10, count 2 2006.201.15:07:36.33#ibcon#enter sib2, iclass 10, count 2 2006.201.15:07:36.33#ibcon#flushed, iclass 10, count 2 2006.201.15:07:36.33#ibcon#about to write, iclass 10, count 2 2006.201.15:07:36.33#ibcon#wrote, iclass 10, count 2 2006.201.15:07:36.33#ibcon#about to read 3, iclass 10, count 2 2006.201.15:07:36.35#ibcon#read 3, iclass 10, count 2 2006.201.15:07:36.35#ibcon#about to read 4, iclass 10, count 2 2006.201.15:07:36.35#ibcon#read 4, iclass 10, count 2 2006.201.15:07:36.35#ibcon#about to read 5, iclass 10, count 2 2006.201.15:07:36.35#ibcon#read 5, iclass 10, count 2 2006.201.15:07:36.35#ibcon#about to read 6, iclass 10, count 2 2006.201.15:07:36.35#ibcon#read 6, iclass 10, count 2 2006.201.15:07:36.35#ibcon#end of sib2, iclass 10, count 2 2006.201.15:07:36.35#ibcon#*mode == 0, iclass 10, count 2 2006.201.15:07:36.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.15:07:36.35#ibcon#[25=AT05-04\r\n] 2006.201.15:07:36.35#ibcon#*before write, iclass 10, count 2 2006.201.15:07:36.35#ibcon#enter sib2, iclass 10, count 2 2006.201.15:07:36.35#ibcon#flushed, iclass 10, count 2 2006.201.15:07:36.35#ibcon#about to write, iclass 10, count 2 2006.201.15:07:36.35#ibcon#wrote, iclass 10, count 2 2006.201.15:07:36.35#ibcon#about to read 3, iclass 10, count 2 2006.201.15:07:36.38#ibcon#read 3, iclass 10, count 2 2006.201.15:07:36.38#ibcon#about to read 4, iclass 10, count 2 2006.201.15:07:36.38#ibcon#read 4, iclass 10, count 2 2006.201.15:07:36.38#ibcon#about to read 5, iclass 10, count 2 2006.201.15:07:36.38#ibcon#read 5, iclass 10, count 2 2006.201.15:07:36.38#ibcon#about to read 6, iclass 10, count 2 2006.201.15:07:36.38#ibcon#read 6, iclass 10, count 2 2006.201.15:07:36.38#ibcon#end of sib2, iclass 10, count 2 2006.201.15:07:36.38#ibcon#*after write, iclass 10, count 2 2006.201.15:07:36.38#ibcon#*before return 0, iclass 10, count 2 2006.201.15:07:36.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:36.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:36.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.15:07:36.38#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:36.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:36.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:36.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:36.50#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:07:36.50#ibcon#first serial, iclass 10, count 0 2006.201.15:07:36.50#ibcon#enter sib2, iclass 10, count 0 2006.201.15:07:36.50#ibcon#flushed, iclass 10, count 0 2006.201.15:07:36.50#ibcon#about to write, iclass 10, count 0 2006.201.15:07:36.50#ibcon#wrote, iclass 10, count 0 2006.201.15:07:36.50#ibcon#about to read 3, iclass 10, count 0 2006.201.15:07:36.52#ibcon#read 3, iclass 10, count 0 2006.201.15:07:36.52#ibcon#about to read 4, iclass 10, count 0 2006.201.15:07:36.52#ibcon#read 4, iclass 10, count 0 2006.201.15:07:36.52#ibcon#about to read 5, iclass 10, count 0 2006.201.15:07:36.52#ibcon#read 5, iclass 10, count 0 2006.201.15:07:36.52#ibcon#about to read 6, iclass 10, count 0 2006.201.15:07:36.52#ibcon#read 6, iclass 10, count 0 2006.201.15:07:36.52#ibcon#end of sib2, iclass 10, count 0 2006.201.15:07:36.52#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:07:36.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:07:36.52#ibcon#[25=USB\r\n] 2006.201.15:07:36.52#ibcon#*before write, iclass 10, count 0 2006.201.15:07:36.52#ibcon#enter sib2, iclass 10, count 0 2006.201.15:07:36.52#ibcon#flushed, iclass 10, count 0 2006.201.15:07:36.52#ibcon#about to write, iclass 10, count 0 2006.201.15:07:36.52#ibcon#wrote, iclass 10, count 0 2006.201.15:07:36.52#ibcon#about to read 3, iclass 10, count 0 2006.201.15:07:36.55#ibcon#read 3, iclass 10, count 0 2006.201.15:07:36.55#ibcon#about to read 4, iclass 10, count 0 2006.201.15:07:36.55#ibcon#read 4, iclass 10, count 0 2006.201.15:07:36.55#ibcon#about to read 5, iclass 10, count 0 2006.201.15:07:36.55#ibcon#read 5, iclass 10, count 0 2006.201.15:07:36.55#ibcon#about to read 6, iclass 10, count 0 2006.201.15:07:36.55#ibcon#read 6, iclass 10, count 0 2006.201.15:07:36.55#ibcon#end of sib2, iclass 10, count 0 2006.201.15:07:36.55#ibcon#*after write, iclass 10, count 0 2006.201.15:07:36.55#ibcon#*before return 0, iclass 10, count 0 2006.201.15:07:36.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:36.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:36.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:07:36.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:07:36.55$vck44/valo=6,814.99 2006.201.15:07:36.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.15:07:36.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.15:07:36.55#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:36.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:36.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:36.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:36.55#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:07:36.55#ibcon#first serial, iclass 12, count 0 2006.201.15:07:36.55#ibcon#enter sib2, iclass 12, count 0 2006.201.15:07:36.55#ibcon#flushed, iclass 12, count 0 2006.201.15:07:36.55#ibcon#about to write, iclass 12, count 0 2006.201.15:07:36.55#ibcon#wrote, iclass 12, count 0 2006.201.15:07:36.55#ibcon#about to read 3, iclass 12, count 0 2006.201.15:07:36.57#ibcon#read 3, iclass 12, count 0 2006.201.15:07:36.57#ibcon#about to read 4, iclass 12, count 0 2006.201.15:07:36.57#ibcon#read 4, iclass 12, count 0 2006.201.15:07:36.57#ibcon#about to read 5, iclass 12, count 0 2006.201.15:07:36.57#ibcon#read 5, iclass 12, count 0 2006.201.15:07:36.57#ibcon#about to read 6, iclass 12, count 0 2006.201.15:07:36.57#ibcon#read 6, iclass 12, count 0 2006.201.15:07:36.57#ibcon#end of sib2, iclass 12, count 0 2006.201.15:07:36.57#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:07:36.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:07:36.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:07:36.57#ibcon#*before write, iclass 12, count 0 2006.201.15:07:36.57#ibcon#enter sib2, iclass 12, count 0 2006.201.15:07:36.57#ibcon#flushed, iclass 12, count 0 2006.201.15:07:36.57#ibcon#about to write, iclass 12, count 0 2006.201.15:07:36.57#ibcon#wrote, iclass 12, count 0 2006.201.15:07:36.57#ibcon#about to read 3, iclass 12, count 0 2006.201.15:07:36.61#ibcon#read 3, iclass 12, count 0 2006.201.15:07:36.61#ibcon#about to read 4, iclass 12, count 0 2006.201.15:07:36.61#ibcon#read 4, iclass 12, count 0 2006.201.15:07:36.61#ibcon#about to read 5, iclass 12, count 0 2006.201.15:07:36.61#ibcon#read 5, iclass 12, count 0 2006.201.15:07:36.61#ibcon#about to read 6, iclass 12, count 0 2006.201.15:07:36.61#ibcon#read 6, iclass 12, count 0 2006.201.15:07:36.61#ibcon#end of sib2, iclass 12, count 0 2006.201.15:07:36.61#ibcon#*after write, iclass 12, count 0 2006.201.15:07:36.61#ibcon#*before return 0, iclass 12, count 0 2006.201.15:07:36.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:36.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:36.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:07:36.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:07:36.61$vck44/va=6,5 2006.201.15:07:36.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.15:07:36.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.15:07:36.61#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:36.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:36.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:36.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:36.67#ibcon#enter wrdev, iclass 14, count 2 2006.201.15:07:36.67#ibcon#first serial, iclass 14, count 2 2006.201.15:07:36.67#ibcon#enter sib2, iclass 14, count 2 2006.201.15:07:36.67#ibcon#flushed, iclass 14, count 2 2006.201.15:07:36.67#ibcon#about to write, iclass 14, count 2 2006.201.15:07:36.67#ibcon#wrote, iclass 14, count 2 2006.201.15:07:36.67#ibcon#about to read 3, iclass 14, count 2 2006.201.15:07:36.69#ibcon#read 3, iclass 14, count 2 2006.201.15:07:36.69#ibcon#about to read 4, iclass 14, count 2 2006.201.15:07:36.69#ibcon#read 4, iclass 14, count 2 2006.201.15:07:36.69#ibcon#about to read 5, iclass 14, count 2 2006.201.15:07:36.69#ibcon#read 5, iclass 14, count 2 2006.201.15:07:36.69#ibcon#about to read 6, iclass 14, count 2 2006.201.15:07:36.69#ibcon#read 6, iclass 14, count 2 2006.201.15:07:36.69#ibcon#end of sib2, iclass 14, count 2 2006.201.15:07:36.69#ibcon#*mode == 0, iclass 14, count 2 2006.201.15:07:36.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.15:07:36.69#ibcon#[25=AT06-05\r\n] 2006.201.15:07:36.69#ibcon#*before write, iclass 14, count 2 2006.201.15:07:36.69#ibcon#enter sib2, iclass 14, count 2 2006.201.15:07:36.69#ibcon#flushed, iclass 14, count 2 2006.201.15:07:36.69#ibcon#about to write, iclass 14, count 2 2006.201.15:07:36.69#ibcon#wrote, iclass 14, count 2 2006.201.15:07:36.69#ibcon#about to read 3, iclass 14, count 2 2006.201.15:07:36.72#ibcon#read 3, iclass 14, count 2 2006.201.15:07:36.72#ibcon#about to read 4, iclass 14, count 2 2006.201.15:07:36.72#ibcon#read 4, iclass 14, count 2 2006.201.15:07:36.72#ibcon#about to read 5, iclass 14, count 2 2006.201.15:07:36.72#ibcon#read 5, iclass 14, count 2 2006.201.15:07:36.72#ibcon#about to read 6, iclass 14, count 2 2006.201.15:07:36.72#ibcon#read 6, iclass 14, count 2 2006.201.15:07:36.72#ibcon#end of sib2, iclass 14, count 2 2006.201.15:07:36.72#ibcon#*after write, iclass 14, count 2 2006.201.15:07:36.72#ibcon#*before return 0, iclass 14, count 2 2006.201.15:07:36.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:36.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:36.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.15:07:36.72#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:36.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:36.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:36.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:36.84#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:07:36.84#ibcon#first serial, iclass 14, count 0 2006.201.15:07:36.84#ibcon#enter sib2, iclass 14, count 0 2006.201.15:07:36.84#ibcon#flushed, iclass 14, count 0 2006.201.15:07:36.84#ibcon#about to write, iclass 14, count 0 2006.201.15:07:36.84#ibcon#wrote, iclass 14, count 0 2006.201.15:07:36.84#ibcon#about to read 3, iclass 14, count 0 2006.201.15:07:36.86#ibcon#read 3, iclass 14, count 0 2006.201.15:07:36.86#ibcon#about to read 4, iclass 14, count 0 2006.201.15:07:36.86#ibcon#read 4, iclass 14, count 0 2006.201.15:07:36.86#ibcon#about to read 5, iclass 14, count 0 2006.201.15:07:36.86#ibcon#read 5, iclass 14, count 0 2006.201.15:07:36.86#ibcon#about to read 6, iclass 14, count 0 2006.201.15:07:36.86#ibcon#read 6, iclass 14, count 0 2006.201.15:07:36.86#ibcon#end of sib2, iclass 14, count 0 2006.201.15:07:36.86#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:07:36.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:07:36.86#ibcon#[25=USB\r\n] 2006.201.15:07:36.86#ibcon#*before write, iclass 14, count 0 2006.201.15:07:36.86#ibcon#enter sib2, iclass 14, count 0 2006.201.15:07:36.86#ibcon#flushed, iclass 14, count 0 2006.201.15:07:36.86#ibcon#about to write, iclass 14, count 0 2006.201.15:07:36.86#ibcon#wrote, iclass 14, count 0 2006.201.15:07:36.86#ibcon#about to read 3, iclass 14, count 0 2006.201.15:07:36.89#ibcon#read 3, iclass 14, count 0 2006.201.15:07:36.89#ibcon#about to read 4, iclass 14, count 0 2006.201.15:07:36.89#ibcon#read 4, iclass 14, count 0 2006.201.15:07:36.89#ibcon#about to read 5, iclass 14, count 0 2006.201.15:07:36.89#ibcon#read 5, iclass 14, count 0 2006.201.15:07:36.89#ibcon#about to read 6, iclass 14, count 0 2006.201.15:07:36.89#ibcon#read 6, iclass 14, count 0 2006.201.15:07:36.89#ibcon#end of sib2, iclass 14, count 0 2006.201.15:07:36.89#ibcon#*after write, iclass 14, count 0 2006.201.15:07:36.89#ibcon#*before return 0, iclass 14, count 0 2006.201.15:07:36.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:36.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:36.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:07:36.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:07:36.89$vck44/valo=7,864.99 2006.201.15:07:36.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.15:07:36.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.15:07:36.89#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:36.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:36.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:36.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:36.89#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:07:36.89#ibcon#first serial, iclass 16, count 0 2006.201.15:07:36.89#ibcon#enter sib2, iclass 16, count 0 2006.201.15:07:36.89#ibcon#flushed, iclass 16, count 0 2006.201.15:07:36.89#ibcon#about to write, iclass 16, count 0 2006.201.15:07:36.89#ibcon#wrote, iclass 16, count 0 2006.201.15:07:36.89#ibcon#about to read 3, iclass 16, count 0 2006.201.15:07:36.91#ibcon#read 3, iclass 16, count 0 2006.201.15:07:36.91#ibcon#about to read 4, iclass 16, count 0 2006.201.15:07:36.91#ibcon#read 4, iclass 16, count 0 2006.201.15:07:36.91#ibcon#about to read 5, iclass 16, count 0 2006.201.15:07:36.91#ibcon#read 5, iclass 16, count 0 2006.201.15:07:36.91#ibcon#about to read 6, iclass 16, count 0 2006.201.15:07:36.91#ibcon#read 6, iclass 16, count 0 2006.201.15:07:36.91#ibcon#end of sib2, iclass 16, count 0 2006.201.15:07:36.91#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:07:36.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:07:36.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:07:36.91#ibcon#*before write, iclass 16, count 0 2006.201.15:07:36.91#ibcon#enter sib2, iclass 16, count 0 2006.201.15:07:36.91#ibcon#flushed, iclass 16, count 0 2006.201.15:07:36.91#ibcon#about to write, iclass 16, count 0 2006.201.15:07:36.91#ibcon#wrote, iclass 16, count 0 2006.201.15:07:36.91#ibcon#about to read 3, iclass 16, count 0 2006.201.15:07:36.95#ibcon#read 3, iclass 16, count 0 2006.201.15:07:36.95#ibcon#about to read 4, iclass 16, count 0 2006.201.15:07:36.95#ibcon#read 4, iclass 16, count 0 2006.201.15:07:36.95#ibcon#about to read 5, iclass 16, count 0 2006.201.15:07:36.95#ibcon#read 5, iclass 16, count 0 2006.201.15:07:36.95#ibcon#about to read 6, iclass 16, count 0 2006.201.15:07:36.95#ibcon#read 6, iclass 16, count 0 2006.201.15:07:36.95#ibcon#end of sib2, iclass 16, count 0 2006.201.15:07:36.95#ibcon#*after write, iclass 16, count 0 2006.201.15:07:36.95#ibcon#*before return 0, iclass 16, count 0 2006.201.15:07:36.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:36.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:36.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:07:36.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:07:36.95$vck44/va=7,5 2006.201.15:07:36.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.15:07:36.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.15:07:36.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:36.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:37.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:37.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:37.01#ibcon#enter wrdev, iclass 18, count 2 2006.201.15:07:37.01#ibcon#first serial, iclass 18, count 2 2006.201.15:07:37.01#ibcon#enter sib2, iclass 18, count 2 2006.201.15:07:37.01#ibcon#flushed, iclass 18, count 2 2006.201.15:07:37.01#ibcon#about to write, iclass 18, count 2 2006.201.15:07:37.01#ibcon#wrote, iclass 18, count 2 2006.201.15:07:37.01#ibcon#about to read 3, iclass 18, count 2 2006.201.15:07:37.03#ibcon#read 3, iclass 18, count 2 2006.201.15:07:37.03#ibcon#about to read 4, iclass 18, count 2 2006.201.15:07:37.03#ibcon#read 4, iclass 18, count 2 2006.201.15:07:37.03#ibcon#about to read 5, iclass 18, count 2 2006.201.15:07:37.03#ibcon#read 5, iclass 18, count 2 2006.201.15:07:37.03#ibcon#about to read 6, iclass 18, count 2 2006.201.15:07:37.03#ibcon#read 6, iclass 18, count 2 2006.201.15:07:37.03#ibcon#end of sib2, iclass 18, count 2 2006.201.15:07:37.03#ibcon#*mode == 0, iclass 18, count 2 2006.201.15:07:37.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.15:07:37.03#ibcon#[25=AT07-05\r\n] 2006.201.15:07:37.03#ibcon#*before write, iclass 18, count 2 2006.201.15:07:37.03#ibcon#enter sib2, iclass 18, count 2 2006.201.15:07:37.03#ibcon#flushed, iclass 18, count 2 2006.201.15:07:37.03#ibcon#about to write, iclass 18, count 2 2006.201.15:07:37.03#ibcon#wrote, iclass 18, count 2 2006.201.15:07:37.03#ibcon#about to read 3, iclass 18, count 2 2006.201.15:07:37.06#ibcon#read 3, iclass 18, count 2 2006.201.15:07:37.06#ibcon#about to read 4, iclass 18, count 2 2006.201.15:07:37.06#ibcon#read 4, iclass 18, count 2 2006.201.15:07:37.06#ibcon#about to read 5, iclass 18, count 2 2006.201.15:07:37.06#ibcon#read 5, iclass 18, count 2 2006.201.15:07:37.06#ibcon#about to read 6, iclass 18, count 2 2006.201.15:07:37.06#ibcon#read 6, iclass 18, count 2 2006.201.15:07:37.06#ibcon#end of sib2, iclass 18, count 2 2006.201.15:07:37.06#ibcon#*after write, iclass 18, count 2 2006.201.15:07:37.06#ibcon#*before return 0, iclass 18, count 2 2006.201.15:07:37.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:37.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:37.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.15:07:37.06#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:37.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:37.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:37.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:37.18#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:07:37.18#ibcon#first serial, iclass 18, count 0 2006.201.15:07:37.18#ibcon#enter sib2, iclass 18, count 0 2006.201.15:07:37.18#ibcon#flushed, iclass 18, count 0 2006.201.15:07:37.18#ibcon#about to write, iclass 18, count 0 2006.201.15:07:37.18#ibcon#wrote, iclass 18, count 0 2006.201.15:07:37.18#ibcon#about to read 3, iclass 18, count 0 2006.201.15:07:37.20#ibcon#read 3, iclass 18, count 0 2006.201.15:07:37.20#ibcon#about to read 4, iclass 18, count 0 2006.201.15:07:37.20#ibcon#read 4, iclass 18, count 0 2006.201.15:07:37.20#ibcon#about to read 5, iclass 18, count 0 2006.201.15:07:37.20#ibcon#read 5, iclass 18, count 0 2006.201.15:07:37.20#ibcon#about to read 6, iclass 18, count 0 2006.201.15:07:37.20#ibcon#read 6, iclass 18, count 0 2006.201.15:07:37.20#ibcon#end of sib2, iclass 18, count 0 2006.201.15:07:37.20#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:07:37.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:07:37.20#ibcon#[25=USB\r\n] 2006.201.15:07:37.20#ibcon#*before write, iclass 18, count 0 2006.201.15:07:37.20#ibcon#enter sib2, iclass 18, count 0 2006.201.15:07:37.20#ibcon#flushed, iclass 18, count 0 2006.201.15:07:37.20#ibcon#about to write, iclass 18, count 0 2006.201.15:07:37.20#ibcon#wrote, iclass 18, count 0 2006.201.15:07:37.20#ibcon#about to read 3, iclass 18, count 0 2006.201.15:07:37.23#ibcon#read 3, iclass 18, count 0 2006.201.15:07:37.23#ibcon#about to read 4, iclass 18, count 0 2006.201.15:07:37.23#ibcon#read 4, iclass 18, count 0 2006.201.15:07:37.23#ibcon#about to read 5, iclass 18, count 0 2006.201.15:07:37.23#ibcon#read 5, iclass 18, count 0 2006.201.15:07:37.23#ibcon#about to read 6, iclass 18, count 0 2006.201.15:07:37.23#ibcon#read 6, iclass 18, count 0 2006.201.15:07:37.23#ibcon#end of sib2, iclass 18, count 0 2006.201.15:07:37.23#ibcon#*after write, iclass 18, count 0 2006.201.15:07:37.23#ibcon#*before return 0, iclass 18, count 0 2006.201.15:07:37.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:37.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:37.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:07:37.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:07:37.23$vck44/valo=8,884.99 2006.201.15:07:37.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.15:07:37.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.15:07:37.23#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:37.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:07:37.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:07:37.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:07:37.23#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:07:37.23#ibcon#first serial, iclass 20, count 0 2006.201.15:07:37.23#ibcon#enter sib2, iclass 20, count 0 2006.201.15:07:37.23#ibcon#flushed, iclass 20, count 0 2006.201.15:07:37.23#ibcon#about to write, iclass 20, count 0 2006.201.15:07:37.23#ibcon#wrote, iclass 20, count 0 2006.201.15:07:37.23#ibcon#about to read 3, iclass 20, count 0 2006.201.15:07:37.25#ibcon#read 3, iclass 20, count 0 2006.201.15:07:37.25#ibcon#about to read 4, iclass 20, count 0 2006.201.15:07:37.25#ibcon#read 4, iclass 20, count 0 2006.201.15:07:37.25#ibcon#about to read 5, iclass 20, count 0 2006.201.15:07:37.25#ibcon#read 5, iclass 20, count 0 2006.201.15:07:37.25#ibcon#about to read 6, iclass 20, count 0 2006.201.15:07:37.25#ibcon#read 6, iclass 20, count 0 2006.201.15:07:37.25#ibcon#end of sib2, iclass 20, count 0 2006.201.15:07:37.25#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:07:37.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:07:37.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:07:37.25#ibcon#*before write, iclass 20, count 0 2006.201.15:07:37.25#ibcon#enter sib2, iclass 20, count 0 2006.201.15:07:37.25#ibcon#flushed, iclass 20, count 0 2006.201.15:07:37.25#ibcon#about to write, iclass 20, count 0 2006.201.15:07:37.25#ibcon#wrote, iclass 20, count 0 2006.201.15:07:37.25#ibcon#about to read 3, iclass 20, count 0 2006.201.15:07:37.29#ibcon#read 3, iclass 20, count 0 2006.201.15:07:37.29#ibcon#about to read 4, iclass 20, count 0 2006.201.15:07:37.29#ibcon#read 4, iclass 20, count 0 2006.201.15:07:37.29#ibcon#about to read 5, iclass 20, count 0 2006.201.15:07:37.29#ibcon#read 5, iclass 20, count 0 2006.201.15:07:37.29#ibcon#about to read 6, iclass 20, count 0 2006.201.15:07:37.29#ibcon#read 6, iclass 20, count 0 2006.201.15:07:37.29#ibcon#end of sib2, iclass 20, count 0 2006.201.15:07:37.29#ibcon#*after write, iclass 20, count 0 2006.201.15:07:37.29#ibcon#*before return 0, iclass 20, count 0 2006.201.15:07:37.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:07:37.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:07:37.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:07:37.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:07:37.29$vck44/va=8,4 2006.201.15:07:37.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.15:07:37.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.15:07:37.29#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:37.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:07:37.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:07:37.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:07:37.35#ibcon#enter wrdev, iclass 22, count 2 2006.201.15:07:37.35#ibcon#first serial, iclass 22, count 2 2006.201.15:07:37.35#ibcon#enter sib2, iclass 22, count 2 2006.201.15:07:37.35#ibcon#flushed, iclass 22, count 2 2006.201.15:07:37.35#ibcon#about to write, iclass 22, count 2 2006.201.15:07:37.35#ibcon#wrote, iclass 22, count 2 2006.201.15:07:37.35#ibcon#about to read 3, iclass 22, count 2 2006.201.15:07:37.37#ibcon#read 3, iclass 22, count 2 2006.201.15:07:37.37#ibcon#about to read 4, iclass 22, count 2 2006.201.15:07:37.37#ibcon#read 4, iclass 22, count 2 2006.201.15:07:37.37#ibcon#about to read 5, iclass 22, count 2 2006.201.15:07:37.37#ibcon#read 5, iclass 22, count 2 2006.201.15:07:37.37#ibcon#about to read 6, iclass 22, count 2 2006.201.15:07:37.37#ibcon#read 6, iclass 22, count 2 2006.201.15:07:37.37#ibcon#end of sib2, iclass 22, count 2 2006.201.15:07:37.37#ibcon#*mode == 0, iclass 22, count 2 2006.201.15:07:37.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.15:07:37.37#ibcon#[25=AT08-04\r\n] 2006.201.15:07:37.37#ibcon#*before write, iclass 22, count 2 2006.201.15:07:37.37#ibcon#enter sib2, iclass 22, count 2 2006.201.15:07:37.37#ibcon#flushed, iclass 22, count 2 2006.201.15:07:37.37#ibcon#about to write, iclass 22, count 2 2006.201.15:07:37.37#ibcon#wrote, iclass 22, count 2 2006.201.15:07:37.37#ibcon#about to read 3, iclass 22, count 2 2006.201.15:07:37.40#ibcon#read 3, iclass 22, count 2 2006.201.15:07:37.40#ibcon#about to read 4, iclass 22, count 2 2006.201.15:07:37.40#ibcon#read 4, iclass 22, count 2 2006.201.15:07:37.40#ibcon#about to read 5, iclass 22, count 2 2006.201.15:07:37.40#ibcon#read 5, iclass 22, count 2 2006.201.15:07:37.40#ibcon#about to read 6, iclass 22, count 2 2006.201.15:07:37.40#ibcon#read 6, iclass 22, count 2 2006.201.15:07:37.40#ibcon#end of sib2, iclass 22, count 2 2006.201.15:07:37.40#ibcon#*after write, iclass 22, count 2 2006.201.15:07:37.40#ibcon#*before return 0, iclass 22, count 2 2006.201.15:07:37.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:07:37.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:07:37.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.15:07:37.40#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:37.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:07:37.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:07:37.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:07:37.52#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:07:37.52#ibcon#first serial, iclass 22, count 0 2006.201.15:07:37.52#ibcon#enter sib2, iclass 22, count 0 2006.201.15:07:37.52#ibcon#flushed, iclass 22, count 0 2006.201.15:07:37.52#ibcon#about to write, iclass 22, count 0 2006.201.15:07:37.52#ibcon#wrote, iclass 22, count 0 2006.201.15:07:37.52#ibcon#about to read 3, iclass 22, count 0 2006.201.15:07:37.54#ibcon#read 3, iclass 22, count 0 2006.201.15:07:37.54#ibcon#about to read 4, iclass 22, count 0 2006.201.15:07:37.54#ibcon#read 4, iclass 22, count 0 2006.201.15:07:37.54#ibcon#about to read 5, iclass 22, count 0 2006.201.15:07:37.54#ibcon#read 5, iclass 22, count 0 2006.201.15:07:37.54#ibcon#about to read 6, iclass 22, count 0 2006.201.15:07:37.54#ibcon#read 6, iclass 22, count 0 2006.201.15:07:37.54#ibcon#end of sib2, iclass 22, count 0 2006.201.15:07:37.54#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:07:37.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:07:37.54#ibcon#[25=USB\r\n] 2006.201.15:07:37.54#ibcon#*before write, iclass 22, count 0 2006.201.15:07:37.54#ibcon#enter sib2, iclass 22, count 0 2006.201.15:07:37.54#ibcon#flushed, iclass 22, count 0 2006.201.15:07:37.54#ibcon#about to write, iclass 22, count 0 2006.201.15:07:37.54#ibcon#wrote, iclass 22, count 0 2006.201.15:07:37.54#ibcon#about to read 3, iclass 22, count 0 2006.201.15:07:37.57#ibcon#read 3, iclass 22, count 0 2006.201.15:07:37.57#ibcon#about to read 4, iclass 22, count 0 2006.201.15:07:37.57#ibcon#read 4, iclass 22, count 0 2006.201.15:07:37.57#ibcon#about to read 5, iclass 22, count 0 2006.201.15:07:37.57#ibcon#read 5, iclass 22, count 0 2006.201.15:07:37.57#ibcon#about to read 6, iclass 22, count 0 2006.201.15:07:37.57#ibcon#read 6, iclass 22, count 0 2006.201.15:07:37.57#ibcon#end of sib2, iclass 22, count 0 2006.201.15:07:37.57#ibcon#*after write, iclass 22, count 0 2006.201.15:07:37.57#ibcon#*before return 0, iclass 22, count 0 2006.201.15:07:37.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:07:37.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:07:37.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:07:37.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:07:37.57$vck44/vblo=1,629.99 2006.201.15:07:37.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.15:07:37.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.15:07:37.57#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:37.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:37.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:37.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:37.57#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:07:37.57#ibcon#first serial, iclass 24, count 0 2006.201.15:07:37.57#ibcon#enter sib2, iclass 24, count 0 2006.201.15:07:37.57#ibcon#flushed, iclass 24, count 0 2006.201.15:07:37.57#ibcon#about to write, iclass 24, count 0 2006.201.15:07:37.57#ibcon#wrote, iclass 24, count 0 2006.201.15:07:37.57#ibcon#about to read 3, iclass 24, count 0 2006.201.15:07:37.59#ibcon#read 3, iclass 24, count 0 2006.201.15:07:37.59#ibcon#about to read 4, iclass 24, count 0 2006.201.15:07:37.59#ibcon#read 4, iclass 24, count 0 2006.201.15:07:37.59#ibcon#about to read 5, iclass 24, count 0 2006.201.15:07:37.59#ibcon#read 5, iclass 24, count 0 2006.201.15:07:37.59#ibcon#about to read 6, iclass 24, count 0 2006.201.15:07:37.59#ibcon#read 6, iclass 24, count 0 2006.201.15:07:37.59#ibcon#end of sib2, iclass 24, count 0 2006.201.15:07:37.59#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:07:37.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:07:37.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:07:37.59#ibcon#*before write, iclass 24, count 0 2006.201.15:07:37.59#ibcon#enter sib2, iclass 24, count 0 2006.201.15:07:37.59#ibcon#flushed, iclass 24, count 0 2006.201.15:07:37.59#ibcon#about to write, iclass 24, count 0 2006.201.15:07:37.59#ibcon#wrote, iclass 24, count 0 2006.201.15:07:37.59#ibcon#about to read 3, iclass 24, count 0 2006.201.15:07:37.63#ibcon#read 3, iclass 24, count 0 2006.201.15:07:37.63#ibcon#about to read 4, iclass 24, count 0 2006.201.15:07:37.63#ibcon#read 4, iclass 24, count 0 2006.201.15:07:37.63#ibcon#about to read 5, iclass 24, count 0 2006.201.15:07:37.63#ibcon#read 5, iclass 24, count 0 2006.201.15:07:37.63#ibcon#about to read 6, iclass 24, count 0 2006.201.15:07:37.63#ibcon#read 6, iclass 24, count 0 2006.201.15:07:37.63#ibcon#end of sib2, iclass 24, count 0 2006.201.15:07:37.63#ibcon#*after write, iclass 24, count 0 2006.201.15:07:37.63#ibcon#*before return 0, iclass 24, count 0 2006.201.15:07:37.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:37.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:37.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:07:37.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:07:37.63$vck44/vb=1,4 2006.201.15:07:37.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.15:07:37.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.15:07:37.63#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:37.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:07:37.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:07:37.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:07:37.63#ibcon#enter wrdev, iclass 26, count 2 2006.201.15:07:37.63#ibcon#first serial, iclass 26, count 2 2006.201.15:07:37.63#ibcon#enter sib2, iclass 26, count 2 2006.201.15:07:37.63#ibcon#flushed, iclass 26, count 2 2006.201.15:07:37.63#ibcon#about to write, iclass 26, count 2 2006.201.15:07:37.63#ibcon#wrote, iclass 26, count 2 2006.201.15:07:37.63#ibcon#about to read 3, iclass 26, count 2 2006.201.15:07:37.65#ibcon#read 3, iclass 26, count 2 2006.201.15:07:37.65#ibcon#about to read 4, iclass 26, count 2 2006.201.15:07:37.65#ibcon#read 4, iclass 26, count 2 2006.201.15:07:37.65#ibcon#about to read 5, iclass 26, count 2 2006.201.15:07:37.65#ibcon#read 5, iclass 26, count 2 2006.201.15:07:37.65#ibcon#about to read 6, iclass 26, count 2 2006.201.15:07:37.65#ibcon#read 6, iclass 26, count 2 2006.201.15:07:37.65#ibcon#end of sib2, iclass 26, count 2 2006.201.15:07:37.65#ibcon#*mode == 0, iclass 26, count 2 2006.201.15:07:37.65#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.15:07:37.65#ibcon#[27=AT01-04\r\n] 2006.201.15:07:37.65#ibcon#*before write, iclass 26, count 2 2006.201.15:07:37.65#ibcon#enter sib2, iclass 26, count 2 2006.201.15:07:37.65#ibcon#flushed, iclass 26, count 2 2006.201.15:07:37.65#ibcon#about to write, iclass 26, count 2 2006.201.15:07:37.65#ibcon#wrote, iclass 26, count 2 2006.201.15:07:37.65#ibcon#about to read 3, iclass 26, count 2 2006.201.15:07:37.68#ibcon#read 3, iclass 26, count 2 2006.201.15:07:37.68#ibcon#about to read 4, iclass 26, count 2 2006.201.15:07:37.68#ibcon#read 4, iclass 26, count 2 2006.201.15:07:37.68#ibcon#about to read 5, iclass 26, count 2 2006.201.15:07:37.68#ibcon#read 5, iclass 26, count 2 2006.201.15:07:37.68#ibcon#about to read 6, iclass 26, count 2 2006.201.15:07:37.68#ibcon#read 6, iclass 26, count 2 2006.201.15:07:37.68#ibcon#end of sib2, iclass 26, count 2 2006.201.15:07:37.68#ibcon#*after write, iclass 26, count 2 2006.201.15:07:37.68#ibcon#*before return 0, iclass 26, count 2 2006.201.15:07:37.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:07:37.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:07:37.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.15:07:37.68#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:37.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:07:37.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:07:37.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:07:37.80#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:07:37.80#ibcon#first serial, iclass 26, count 0 2006.201.15:07:37.80#ibcon#enter sib2, iclass 26, count 0 2006.201.15:07:37.80#ibcon#flushed, iclass 26, count 0 2006.201.15:07:37.80#ibcon#about to write, iclass 26, count 0 2006.201.15:07:37.80#ibcon#wrote, iclass 26, count 0 2006.201.15:07:37.80#ibcon#about to read 3, iclass 26, count 0 2006.201.15:07:37.82#ibcon#read 3, iclass 26, count 0 2006.201.15:07:37.82#ibcon#about to read 4, iclass 26, count 0 2006.201.15:07:37.82#ibcon#read 4, iclass 26, count 0 2006.201.15:07:37.82#ibcon#about to read 5, iclass 26, count 0 2006.201.15:07:37.82#ibcon#read 5, iclass 26, count 0 2006.201.15:07:37.82#ibcon#about to read 6, iclass 26, count 0 2006.201.15:07:37.82#ibcon#read 6, iclass 26, count 0 2006.201.15:07:37.82#ibcon#end of sib2, iclass 26, count 0 2006.201.15:07:37.82#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:07:37.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:07:37.82#ibcon#[27=USB\r\n] 2006.201.15:07:37.82#ibcon#*before write, iclass 26, count 0 2006.201.15:07:37.82#ibcon#enter sib2, iclass 26, count 0 2006.201.15:07:37.82#ibcon#flushed, iclass 26, count 0 2006.201.15:07:37.82#ibcon#about to write, iclass 26, count 0 2006.201.15:07:37.82#ibcon#wrote, iclass 26, count 0 2006.201.15:07:37.82#ibcon#about to read 3, iclass 26, count 0 2006.201.15:07:37.85#ibcon#read 3, iclass 26, count 0 2006.201.15:07:37.85#ibcon#about to read 4, iclass 26, count 0 2006.201.15:07:37.85#ibcon#read 4, iclass 26, count 0 2006.201.15:07:37.85#ibcon#about to read 5, iclass 26, count 0 2006.201.15:07:37.85#ibcon#read 5, iclass 26, count 0 2006.201.15:07:37.85#ibcon#about to read 6, iclass 26, count 0 2006.201.15:07:37.85#ibcon#read 6, iclass 26, count 0 2006.201.15:07:37.85#ibcon#end of sib2, iclass 26, count 0 2006.201.15:07:37.85#ibcon#*after write, iclass 26, count 0 2006.201.15:07:37.85#ibcon#*before return 0, iclass 26, count 0 2006.201.15:07:37.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:07:37.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:07:37.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:07:37.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:07:37.85$vck44/vblo=2,634.99 2006.201.15:07:37.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.15:07:37.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.15:07:37.85#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:37.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:37.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:37.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:37.85#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:07:37.85#ibcon#first serial, iclass 28, count 0 2006.201.15:07:37.85#ibcon#enter sib2, iclass 28, count 0 2006.201.15:07:37.85#ibcon#flushed, iclass 28, count 0 2006.201.15:07:37.85#ibcon#about to write, iclass 28, count 0 2006.201.15:07:37.85#ibcon#wrote, iclass 28, count 0 2006.201.15:07:37.85#ibcon#about to read 3, iclass 28, count 0 2006.201.15:07:37.87#ibcon#read 3, iclass 28, count 0 2006.201.15:07:37.87#ibcon#about to read 4, iclass 28, count 0 2006.201.15:07:37.87#ibcon#read 4, iclass 28, count 0 2006.201.15:07:37.87#ibcon#about to read 5, iclass 28, count 0 2006.201.15:07:37.87#ibcon#read 5, iclass 28, count 0 2006.201.15:07:37.87#ibcon#about to read 6, iclass 28, count 0 2006.201.15:07:37.87#ibcon#read 6, iclass 28, count 0 2006.201.15:07:37.87#ibcon#end of sib2, iclass 28, count 0 2006.201.15:07:37.87#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:07:37.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:07:37.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:07:37.87#ibcon#*before write, iclass 28, count 0 2006.201.15:07:37.87#ibcon#enter sib2, iclass 28, count 0 2006.201.15:07:37.87#ibcon#flushed, iclass 28, count 0 2006.201.15:07:37.87#ibcon#about to write, iclass 28, count 0 2006.201.15:07:37.87#ibcon#wrote, iclass 28, count 0 2006.201.15:07:37.87#ibcon#about to read 3, iclass 28, count 0 2006.201.15:07:37.91#ibcon#read 3, iclass 28, count 0 2006.201.15:07:37.91#ibcon#about to read 4, iclass 28, count 0 2006.201.15:07:37.91#ibcon#read 4, iclass 28, count 0 2006.201.15:07:37.91#ibcon#about to read 5, iclass 28, count 0 2006.201.15:07:37.91#ibcon#read 5, iclass 28, count 0 2006.201.15:07:37.91#ibcon#about to read 6, iclass 28, count 0 2006.201.15:07:37.91#ibcon#read 6, iclass 28, count 0 2006.201.15:07:37.91#ibcon#end of sib2, iclass 28, count 0 2006.201.15:07:37.91#ibcon#*after write, iclass 28, count 0 2006.201.15:07:37.91#ibcon#*before return 0, iclass 28, count 0 2006.201.15:07:37.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:37.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:07:37.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:07:37.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:07:37.91$vck44/vb=2,5 2006.201.15:07:37.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.15:07:37.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.15:07:37.91#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:37.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:37.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:37.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:37.97#ibcon#enter wrdev, iclass 30, count 2 2006.201.15:07:37.97#ibcon#first serial, iclass 30, count 2 2006.201.15:07:37.97#ibcon#enter sib2, iclass 30, count 2 2006.201.15:07:37.97#ibcon#flushed, iclass 30, count 2 2006.201.15:07:37.97#ibcon#about to write, iclass 30, count 2 2006.201.15:07:37.97#ibcon#wrote, iclass 30, count 2 2006.201.15:07:37.97#ibcon#about to read 3, iclass 30, count 2 2006.201.15:07:37.99#ibcon#read 3, iclass 30, count 2 2006.201.15:07:37.99#ibcon#about to read 4, iclass 30, count 2 2006.201.15:07:37.99#ibcon#read 4, iclass 30, count 2 2006.201.15:07:37.99#ibcon#about to read 5, iclass 30, count 2 2006.201.15:07:37.99#ibcon#read 5, iclass 30, count 2 2006.201.15:07:37.99#ibcon#about to read 6, iclass 30, count 2 2006.201.15:07:37.99#ibcon#read 6, iclass 30, count 2 2006.201.15:07:37.99#ibcon#end of sib2, iclass 30, count 2 2006.201.15:07:37.99#ibcon#*mode == 0, iclass 30, count 2 2006.201.15:07:37.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.15:07:37.99#ibcon#[27=AT02-05\r\n] 2006.201.15:07:37.99#ibcon#*before write, iclass 30, count 2 2006.201.15:07:37.99#ibcon#enter sib2, iclass 30, count 2 2006.201.15:07:37.99#ibcon#flushed, iclass 30, count 2 2006.201.15:07:37.99#ibcon#about to write, iclass 30, count 2 2006.201.15:07:37.99#ibcon#wrote, iclass 30, count 2 2006.201.15:07:37.99#ibcon#about to read 3, iclass 30, count 2 2006.201.15:07:38.02#ibcon#read 3, iclass 30, count 2 2006.201.15:07:38.02#ibcon#about to read 4, iclass 30, count 2 2006.201.15:07:38.02#ibcon#read 4, iclass 30, count 2 2006.201.15:07:38.02#ibcon#about to read 5, iclass 30, count 2 2006.201.15:07:38.02#ibcon#read 5, iclass 30, count 2 2006.201.15:07:38.02#ibcon#about to read 6, iclass 30, count 2 2006.201.15:07:38.02#ibcon#read 6, iclass 30, count 2 2006.201.15:07:38.02#ibcon#end of sib2, iclass 30, count 2 2006.201.15:07:38.02#ibcon#*after write, iclass 30, count 2 2006.201.15:07:38.02#ibcon#*before return 0, iclass 30, count 2 2006.201.15:07:38.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:38.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:07:38.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.15:07:38.02#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:38.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:38.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:38.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:38.14#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:07:38.14#ibcon#first serial, iclass 30, count 0 2006.201.15:07:38.14#ibcon#enter sib2, iclass 30, count 0 2006.201.15:07:38.14#ibcon#flushed, iclass 30, count 0 2006.201.15:07:38.14#ibcon#about to write, iclass 30, count 0 2006.201.15:07:38.14#ibcon#wrote, iclass 30, count 0 2006.201.15:07:38.14#ibcon#about to read 3, iclass 30, count 0 2006.201.15:07:38.16#ibcon#read 3, iclass 30, count 0 2006.201.15:07:38.16#ibcon#about to read 4, iclass 30, count 0 2006.201.15:07:38.16#ibcon#read 4, iclass 30, count 0 2006.201.15:07:38.16#ibcon#about to read 5, iclass 30, count 0 2006.201.15:07:38.16#ibcon#read 5, iclass 30, count 0 2006.201.15:07:38.16#ibcon#about to read 6, iclass 30, count 0 2006.201.15:07:38.16#ibcon#read 6, iclass 30, count 0 2006.201.15:07:38.16#ibcon#end of sib2, iclass 30, count 0 2006.201.15:07:38.16#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:07:38.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:07:38.16#ibcon#[27=USB\r\n] 2006.201.15:07:38.16#ibcon#*before write, iclass 30, count 0 2006.201.15:07:38.16#ibcon#enter sib2, iclass 30, count 0 2006.201.15:07:38.16#ibcon#flushed, iclass 30, count 0 2006.201.15:07:38.16#ibcon#about to write, iclass 30, count 0 2006.201.15:07:38.16#ibcon#wrote, iclass 30, count 0 2006.201.15:07:38.16#ibcon#about to read 3, iclass 30, count 0 2006.201.15:07:38.19#ibcon#read 3, iclass 30, count 0 2006.201.15:07:38.19#ibcon#about to read 4, iclass 30, count 0 2006.201.15:07:38.19#ibcon#read 4, iclass 30, count 0 2006.201.15:07:38.19#ibcon#about to read 5, iclass 30, count 0 2006.201.15:07:38.19#ibcon#read 5, iclass 30, count 0 2006.201.15:07:38.19#ibcon#about to read 6, iclass 30, count 0 2006.201.15:07:38.19#ibcon#read 6, iclass 30, count 0 2006.201.15:07:38.19#ibcon#end of sib2, iclass 30, count 0 2006.201.15:07:38.19#ibcon#*after write, iclass 30, count 0 2006.201.15:07:38.19#ibcon#*before return 0, iclass 30, count 0 2006.201.15:07:38.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:38.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:07:38.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:07:38.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:07:38.19$vck44/vblo=3,649.99 2006.201.15:07:38.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.15:07:38.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.15:07:38.19#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:38.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:38.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:38.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:38.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:07:38.19#ibcon#first serial, iclass 32, count 0 2006.201.15:07:38.19#ibcon#enter sib2, iclass 32, count 0 2006.201.15:07:38.19#ibcon#flushed, iclass 32, count 0 2006.201.15:07:38.19#ibcon#about to write, iclass 32, count 0 2006.201.15:07:38.19#ibcon#wrote, iclass 32, count 0 2006.201.15:07:38.19#ibcon#about to read 3, iclass 32, count 0 2006.201.15:07:38.21#ibcon#read 3, iclass 32, count 0 2006.201.15:07:38.21#ibcon#about to read 4, iclass 32, count 0 2006.201.15:07:38.21#ibcon#read 4, iclass 32, count 0 2006.201.15:07:38.21#ibcon#about to read 5, iclass 32, count 0 2006.201.15:07:38.21#ibcon#read 5, iclass 32, count 0 2006.201.15:07:38.21#ibcon#about to read 6, iclass 32, count 0 2006.201.15:07:38.21#ibcon#read 6, iclass 32, count 0 2006.201.15:07:38.21#ibcon#end of sib2, iclass 32, count 0 2006.201.15:07:38.21#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:07:38.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:07:38.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:07:38.21#ibcon#*before write, iclass 32, count 0 2006.201.15:07:38.21#ibcon#enter sib2, iclass 32, count 0 2006.201.15:07:38.21#ibcon#flushed, iclass 32, count 0 2006.201.15:07:38.21#ibcon#about to write, iclass 32, count 0 2006.201.15:07:38.21#ibcon#wrote, iclass 32, count 0 2006.201.15:07:38.21#ibcon#about to read 3, iclass 32, count 0 2006.201.15:07:38.25#ibcon#read 3, iclass 32, count 0 2006.201.15:07:38.25#ibcon#about to read 4, iclass 32, count 0 2006.201.15:07:38.25#ibcon#read 4, iclass 32, count 0 2006.201.15:07:38.25#ibcon#about to read 5, iclass 32, count 0 2006.201.15:07:38.25#ibcon#read 5, iclass 32, count 0 2006.201.15:07:38.25#ibcon#about to read 6, iclass 32, count 0 2006.201.15:07:38.25#ibcon#read 6, iclass 32, count 0 2006.201.15:07:38.25#ibcon#end of sib2, iclass 32, count 0 2006.201.15:07:38.25#ibcon#*after write, iclass 32, count 0 2006.201.15:07:38.25#ibcon#*before return 0, iclass 32, count 0 2006.201.15:07:38.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:38.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:07:38.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:07:38.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:07:38.25$vck44/vb=3,4 2006.201.15:07:38.25#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.15:07:38.25#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.15:07:38.25#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:38.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:38.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:38.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:38.31#ibcon#enter wrdev, iclass 34, count 2 2006.201.15:07:38.31#ibcon#first serial, iclass 34, count 2 2006.201.15:07:38.31#ibcon#enter sib2, iclass 34, count 2 2006.201.15:07:38.31#ibcon#flushed, iclass 34, count 2 2006.201.15:07:38.31#ibcon#about to write, iclass 34, count 2 2006.201.15:07:38.31#ibcon#wrote, iclass 34, count 2 2006.201.15:07:38.31#ibcon#about to read 3, iclass 34, count 2 2006.201.15:07:38.33#ibcon#read 3, iclass 34, count 2 2006.201.15:07:38.33#ibcon#about to read 4, iclass 34, count 2 2006.201.15:07:38.33#ibcon#read 4, iclass 34, count 2 2006.201.15:07:38.33#ibcon#about to read 5, iclass 34, count 2 2006.201.15:07:38.33#ibcon#read 5, iclass 34, count 2 2006.201.15:07:38.33#ibcon#about to read 6, iclass 34, count 2 2006.201.15:07:38.33#ibcon#read 6, iclass 34, count 2 2006.201.15:07:38.33#ibcon#end of sib2, iclass 34, count 2 2006.201.15:07:38.33#ibcon#*mode == 0, iclass 34, count 2 2006.201.15:07:38.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.15:07:38.33#ibcon#[27=AT03-04\r\n] 2006.201.15:07:38.33#ibcon#*before write, iclass 34, count 2 2006.201.15:07:38.33#ibcon#enter sib2, iclass 34, count 2 2006.201.15:07:38.33#ibcon#flushed, iclass 34, count 2 2006.201.15:07:38.33#ibcon#about to write, iclass 34, count 2 2006.201.15:07:38.33#ibcon#wrote, iclass 34, count 2 2006.201.15:07:38.33#ibcon#about to read 3, iclass 34, count 2 2006.201.15:07:38.36#ibcon#read 3, iclass 34, count 2 2006.201.15:07:38.36#ibcon#about to read 4, iclass 34, count 2 2006.201.15:07:38.36#ibcon#read 4, iclass 34, count 2 2006.201.15:07:38.36#ibcon#about to read 5, iclass 34, count 2 2006.201.15:07:38.36#ibcon#read 5, iclass 34, count 2 2006.201.15:07:38.36#ibcon#about to read 6, iclass 34, count 2 2006.201.15:07:38.36#ibcon#read 6, iclass 34, count 2 2006.201.15:07:38.36#ibcon#end of sib2, iclass 34, count 2 2006.201.15:07:38.36#ibcon#*after write, iclass 34, count 2 2006.201.15:07:38.36#ibcon#*before return 0, iclass 34, count 2 2006.201.15:07:38.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:38.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:07:38.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.15:07:38.36#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:38.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:38.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:38.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:38.48#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:07:38.48#ibcon#first serial, iclass 34, count 0 2006.201.15:07:38.48#ibcon#enter sib2, iclass 34, count 0 2006.201.15:07:38.48#ibcon#flushed, iclass 34, count 0 2006.201.15:07:38.48#ibcon#about to write, iclass 34, count 0 2006.201.15:07:38.48#ibcon#wrote, iclass 34, count 0 2006.201.15:07:38.48#ibcon#about to read 3, iclass 34, count 0 2006.201.15:07:38.50#ibcon#read 3, iclass 34, count 0 2006.201.15:07:38.50#ibcon#about to read 4, iclass 34, count 0 2006.201.15:07:38.50#ibcon#read 4, iclass 34, count 0 2006.201.15:07:38.50#ibcon#about to read 5, iclass 34, count 0 2006.201.15:07:38.50#ibcon#read 5, iclass 34, count 0 2006.201.15:07:38.50#ibcon#about to read 6, iclass 34, count 0 2006.201.15:07:38.50#ibcon#read 6, iclass 34, count 0 2006.201.15:07:38.50#ibcon#end of sib2, iclass 34, count 0 2006.201.15:07:38.50#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:07:38.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:07:38.50#ibcon#[27=USB\r\n] 2006.201.15:07:38.50#ibcon#*before write, iclass 34, count 0 2006.201.15:07:38.50#ibcon#enter sib2, iclass 34, count 0 2006.201.15:07:38.50#ibcon#flushed, iclass 34, count 0 2006.201.15:07:38.50#ibcon#about to write, iclass 34, count 0 2006.201.15:07:38.50#ibcon#wrote, iclass 34, count 0 2006.201.15:07:38.50#ibcon#about to read 3, iclass 34, count 0 2006.201.15:07:38.53#ibcon#read 3, iclass 34, count 0 2006.201.15:07:38.53#ibcon#about to read 4, iclass 34, count 0 2006.201.15:07:38.53#ibcon#read 4, iclass 34, count 0 2006.201.15:07:38.53#ibcon#about to read 5, iclass 34, count 0 2006.201.15:07:38.53#ibcon#read 5, iclass 34, count 0 2006.201.15:07:38.53#ibcon#about to read 6, iclass 34, count 0 2006.201.15:07:38.53#ibcon#read 6, iclass 34, count 0 2006.201.15:07:38.53#ibcon#end of sib2, iclass 34, count 0 2006.201.15:07:38.53#ibcon#*after write, iclass 34, count 0 2006.201.15:07:38.53#ibcon#*before return 0, iclass 34, count 0 2006.201.15:07:38.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:38.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:07:38.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:07:38.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:07:38.53$vck44/vblo=4,679.99 2006.201.15:07:38.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.15:07:38.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.15:07:38.53#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:38.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:38.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:38.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:38.53#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:07:38.53#ibcon#first serial, iclass 36, count 0 2006.201.15:07:38.53#ibcon#enter sib2, iclass 36, count 0 2006.201.15:07:38.53#ibcon#flushed, iclass 36, count 0 2006.201.15:07:38.53#ibcon#about to write, iclass 36, count 0 2006.201.15:07:38.53#ibcon#wrote, iclass 36, count 0 2006.201.15:07:38.53#ibcon#about to read 3, iclass 36, count 0 2006.201.15:07:38.55#ibcon#read 3, iclass 36, count 0 2006.201.15:07:38.55#ibcon#about to read 4, iclass 36, count 0 2006.201.15:07:38.55#ibcon#read 4, iclass 36, count 0 2006.201.15:07:38.55#ibcon#about to read 5, iclass 36, count 0 2006.201.15:07:38.55#ibcon#read 5, iclass 36, count 0 2006.201.15:07:38.55#ibcon#about to read 6, iclass 36, count 0 2006.201.15:07:38.55#ibcon#read 6, iclass 36, count 0 2006.201.15:07:38.55#ibcon#end of sib2, iclass 36, count 0 2006.201.15:07:38.55#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:07:38.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:07:38.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:07:38.55#ibcon#*before write, iclass 36, count 0 2006.201.15:07:38.55#ibcon#enter sib2, iclass 36, count 0 2006.201.15:07:38.55#ibcon#flushed, iclass 36, count 0 2006.201.15:07:38.55#ibcon#about to write, iclass 36, count 0 2006.201.15:07:38.55#ibcon#wrote, iclass 36, count 0 2006.201.15:07:38.55#ibcon#about to read 3, iclass 36, count 0 2006.201.15:07:38.59#ibcon#read 3, iclass 36, count 0 2006.201.15:07:38.59#ibcon#about to read 4, iclass 36, count 0 2006.201.15:07:38.59#ibcon#read 4, iclass 36, count 0 2006.201.15:07:38.59#ibcon#about to read 5, iclass 36, count 0 2006.201.15:07:38.59#ibcon#read 5, iclass 36, count 0 2006.201.15:07:38.59#ibcon#about to read 6, iclass 36, count 0 2006.201.15:07:38.59#ibcon#read 6, iclass 36, count 0 2006.201.15:07:38.59#ibcon#end of sib2, iclass 36, count 0 2006.201.15:07:38.59#ibcon#*after write, iclass 36, count 0 2006.201.15:07:38.59#ibcon#*before return 0, iclass 36, count 0 2006.201.15:07:38.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:38.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:07:38.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:07:38.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:07:38.59$vck44/vb=4,5 2006.201.15:07:38.59#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.15:07:38.59#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.15:07:38.59#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:38.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:38.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:38.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:38.65#ibcon#enter wrdev, iclass 38, count 2 2006.201.15:07:38.65#ibcon#first serial, iclass 38, count 2 2006.201.15:07:38.65#ibcon#enter sib2, iclass 38, count 2 2006.201.15:07:38.65#ibcon#flushed, iclass 38, count 2 2006.201.15:07:38.65#ibcon#about to write, iclass 38, count 2 2006.201.15:07:38.65#ibcon#wrote, iclass 38, count 2 2006.201.15:07:38.65#ibcon#about to read 3, iclass 38, count 2 2006.201.15:07:38.67#ibcon#read 3, iclass 38, count 2 2006.201.15:07:38.67#ibcon#about to read 4, iclass 38, count 2 2006.201.15:07:38.67#ibcon#read 4, iclass 38, count 2 2006.201.15:07:38.67#ibcon#about to read 5, iclass 38, count 2 2006.201.15:07:38.67#ibcon#read 5, iclass 38, count 2 2006.201.15:07:38.67#ibcon#about to read 6, iclass 38, count 2 2006.201.15:07:38.67#ibcon#read 6, iclass 38, count 2 2006.201.15:07:38.67#ibcon#end of sib2, iclass 38, count 2 2006.201.15:07:38.67#ibcon#*mode == 0, iclass 38, count 2 2006.201.15:07:38.67#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.15:07:38.67#ibcon#[27=AT04-05\r\n] 2006.201.15:07:38.67#ibcon#*before write, iclass 38, count 2 2006.201.15:07:38.67#ibcon#enter sib2, iclass 38, count 2 2006.201.15:07:38.67#ibcon#flushed, iclass 38, count 2 2006.201.15:07:38.67#ibcon#about to write, iclass 38, count 2 2006.201.15:07:38.67#ibcon#wrote, iclass 38, count 2 2006.201.15:07:38.67#ibcon#about to read 3, iclass 38, count 2 2006.201.15:07:38.70#ibcon#read 3, iclass 38, count 2 2006.201.15:07:38.70#ibcon#about to read 4, iclass 38, count 2 2006.201.15:07:38.70#ibcon#read 4, iclass 38, count 2 2006.201.15:07:38.70#ibcon#about to read 5, iclass 38, count 2 2006.201.15:07:38.70#ibcon#read 5, iclass 38, count 2 2006.201.15:07:38.70#ibcon#about to read 6, iclass 38, count 2 2006.201.15:07:38.70#ibcon#read 6, iclass 38, count 2 2006.201.15:07:38.70#ibcon#end of sib2, iclass 38, count 2 2006.201.15:07:38.70#ibcon#*after write, iclass 38, count 2 2006.201.15:07:38.70#ibcon#*before return 0, iclass 38, count 2 2006.201.15:07:38.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:38.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:07:38.70#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.15:07:38.70#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:38.70#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:38.82#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:38.82#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:38.82#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:07:38.82#ibcon#first serial, iclass 38, count 0 2006.201.15:07:38.82#ibcon#enter sib2, iclass 38, count 0 2006.201.15:07:38.82#ibcon#flushed, iclass 38, count 0 2006.201.15:07:38.82#ibcon#about to write, iclass 38, count 0 2006.201.15:07:38.82#ibcon#wrote, iclass 38, count 0 2006.201.15:07:38.82#ibcon#about to read 3, iclass 38, count 0 2006.201.15:07:38.84#ibcon#read 3, iclass 38, count 0 2006.201.15:07:38.84#ibcon#about to read 4, iclass 38, count 0 2006.201.15:07:38.84#ibcon#read 4, iclass 38, count 0 2006.201.15:07:38.84#ibcon#about to read 5, iclass 38, count 0 2006.201.15:07:38.84#ibcon#read 5, iclass 38, count 0 2006.201.15:07:38.84#ibcon#about to read 6, iclass 38, count 0 2006.201.15:07:38.84#ibcon#read 6, iclass 38, count 0 2006.201.15:07:38.84#ibcon#end of sib2, iclass 38, count 0 2006.201.15:07:38.84#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:07:38.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:07:38.84#ibcon#[27=USB\r\n] 2006.201.15:07:38.84#ibcon#*before write, iclass 38, count 0 2006.201.15:07:38.84#ibcon#enter sib2, iclass 38, count 0 2006.201.15:07:38.84#ibcon#flushed, iclass 38, count 0 2006.201.15:07:38.84#ibcon#about to write, iclass 38, count 0 2006.201.15:07:38.84#ibcon#wrote, iclass 38, count 0 2006.201.15:07:38.84#ibcon#about to read 3, iclass 38, count 0 2006.201.15:07:38.87#ibcon#read 3, iclass 38, count 0 2006.201.15:07:38.87#ibcon#about to read 4, iclass 38, count 0 2006.201.15:07:38.87#ibcon#read 4, iclass 38, count 0 2006.201.15:07:38.87#ibcon#about to read 5, iclass 38, count 0 2006.201.15:07:38.87#ibcon#read 5, iclass 38, count 0 2006.201.15:07:38.87#ibcon#about to read 6, iclass 38, count 0 2006.201.15:07:38.87#ibcon#read 6, iclass 38, count 0 2006.201.15:07:38.87#ibcon#end of sib2, iclass 38, count 0 2006.201.15:07:38.87#ibcon#*after write, iclass 38, count 0 2006.201.15:07:38.87#ibcon#*before return 0, iclass 38, count 0 2006.201.15:07:38.87#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:38.87#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:07:38.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:07:38.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:07:38.87$vck44/vblo=5,709.99 2006.201.15:07:38.87#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.15:07:38.87#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.15:07:38.87#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:38.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:38.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:38.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:38.87#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:07:38.87#ibcon#first serial, iclass 40, count 0 2006.201.15:07:38.87#ibcon#enter sib2, iclass 40, count 0 2006.201.15:07:38.87#ibcon#flushed, iclass 40, count 0 2006.201.15:07:38.87#ibcon#about to write, iclass 40, count 0 2006.201.15:07:38.87#ibcon#wrote, iclass 40, count 0 2006.201.15:07:38.87#ibcon#about to read 3, iclass 40, count 0 2006.201.15:07:38.89#ibcon#read 3, iclass 40, count 0 2006.201.15:07:38.89#ibcon#about to read 4, iclass 40, count 0 2006.201.15:07:38.89#ibcon#read 4, iclass 40, count 0 2006.201.15:07:38.89#ibcon#about to read 5, iclass 40, count 0 2006.201.15:07:38.89#ibcon#read 5, iclass 40, count 0 2006.201.15:07:38.89#ibcon#about to read 6, iclass 40, count 0 2006.201.15:07:38.89#ibcon#read 6, iclass 40, count 0 2006.201.15:07:38.89#ibcon#end of sib2, iclass 40, count 0 2006.201.15:07:38.89#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:07:38.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:07:38.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:07:38.89#ibcon#*before write, iclass 40, count 0 2006.201.15:07:38.89#ibcon#enter sib2, iclass 40, count 0 2006.201.15:07:38.89#ibcon#flushed, iclass 40, count 0 2006.201.15:07:38.89#ibcon#about to write, iclass 40, count 0 2006.201.15:07:38.89#ibcon#wrote, iclass 40, count 0 2006.201.15:07:38.89#ibcon#about to read 3, iclass 40, count 0 2006.201.15:07:38.93#ibcon#read 3, iclass 40, count 0 2006.201.15:07:38.93#ibcon#about to read 4, iclass 40, count 0 2006.201.15:07:38.93#ibcon#read 4, iclass 40, count 0 2006.201.15:07:38.93#ibcon#about to read 5, iclass 40, count 0 2006.201.15:07:38.93#ibcon#read 5, iclass 40, count 0 2006.201.15:07:38.93#ibcon#about to read 6, iclass 40, count 0 2006.201.15:07:38.93#ibcon#read 6, iclass 40, count 0 2006.201.15:07:38.93#ibcon#end of sib2, iclass 40, count 0 2006.201.15:07:38.93#ibcon#*after write, iclass 40, count 0 2006.201.15:07:38.93#ibcon#*before return 0, iclass 40, count 0 2006.201.15:07:38.93#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:38.93#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:07:38.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:07:38.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:07:38.93$vck44/vb=5,4 2006.201.15:07:38.93#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.15:07:38.93#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.15:07:38.93#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:38.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:38.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:38.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:38.99#ibcon#enter wrdev, iclass 4, count 2 2006.201.15:07:38.99#ibcon#first serial, iclass 4, count 2 2006.201.15:07:38.99#ibcon#enter sib2, iclass 4, count 2 2006.201.15:07:38.99#ibcon#flushed, iclass 4, count 2 2006.201.15:07:38.99#ibcon#about to write, iclass 4, count 2 2006.201.15:07:38.99#ibcon#wrote, iclass 4, count 2 2006.201.15:07:38.99#ibcon#about to read 3, iclass 4, count 2 2006.201.15:07:39.01#ibcon#read 3, iclass 4, count 2 2006.201.15:07:39.01#ibcon#about to read 4, iclass 4, count 2 2006.201.15:07:39.01#ibcon#read 4, iclass 4, count 2 2006.201.15:07:39.01#ibcon#about to read 5, iclass 4, count 2 2006.201.15:07:39.01#ibcon#read 5, iclass 4, count 2 2006.201.15:07:39.01#ibcon#about to read 6, iclass 4, count 2 2006.201.15:07:39.01#ibcon#read 6, iclass 4, count 2 2006.201.15:07:39.01#ibcon#end of sib2, iclass 4, count 2 2006.201.15:07:39.01#ibcon#*mode == 0, iclass 4, count 2 2006.201.15:07:39.01#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.15:07:39.01#ibcon#[27=AT05-04\r\n] 2006.201.15:07:39.01#ibcon#*before write, iclass 4, count 2 2006.201.15:07:39.01#ibcon#enter sib2, iclass 4, count 2 2006.201.15:07:39.01#ibcon#flushed, iclass 4, count 2 2006.201.15:07:39.01#ibcon#about to write, iclass 4, count 2 2006.201.15:07:39.01#ibcon#wrote, iclass 4, count 2 2006.201.15:07:39.01#ibcon#about to read 3, iclass 4, count 2 2006.201.15:07:39.04#ibcon#read 3, iclass 4, count 2 2006.201.15:07:39.04#ibcon#about to read 4, iclass 4, count 2 2006.201.15:07:39.04#ibcon#read 4, iclass 4, count 2 2006.201.15:07:39.04#ibcon#about to read 5, iclass 4, count 2 2006.201.15:07:39.04#ibcon#read 5, iclass 4, count 2 2006.201.15:07:39.04#ibcon#about to read 6, iclass 4, count 2 2006.201.15:07:39.04#ibcon#read 6, iclass 4, count 2 2006.201.15:07:39.04#ibcon#end of sib2, iclass 4, count 2 2006.201.15:07:39.04#ibcon#*after write, iclass 4, count 2 2006.201.15:07:39.04#ibcon#*before return 0, iclass 4, count 2 2006.201.15:07:39.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:39.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:07:39.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.15:07:39.04#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:39.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:39.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:39.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:39.16#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:07:39.16#ibcon#first serial, iclass 4, count 0 2006.201.15:07:39.16#ibcon#enter sib2, iclass 4, count 0 2006.201.15:07:39.16#ibcon#flushed, iclass 4, count 0 2006.201.15:07:39.16#ibcon#about to write, iclass 4, count 0 2006.201.15:07:39.16#ibcon#wrote, iclass 4, count 0 2006.201.15:07:39.16#ibcon#about to read 3, iclass 4, count 0 2006.201.15:07:39.18#ibcon#read 3, iclass 4, count 0 2006.201.15:07:39.18#ibcon#about to read 4, iclass 4, count 0 2006.201.15:07:39.18#ibcon#read 4, iclass 4, count 0 2006.201.15:07:39.18#ibcon#about to read 5, iclass 4, count 0 2006.201.15:07:39.18#ibcon#read 5, iclass 4, count 0 2006.201.15:07:39.18#ibcon#about to read 6, iclass 4, count 0 2006.201.15:07:39.18#ibcon#read 6, iclass 4, count 0 2006.201.15:07:39.18#ibcon#end of sib2, iclass 4, count 0 2006.201.15:07:39.18#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:07:39.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:07:39.18#ibcon#[27=USB\r\n] 2006.201.15:07:39.18#ibcon#*before write, iclass 4, count 0 2006.201.15:07:39.18#ibcon#enter sib2, iclass 4, count 0 2006.201.15:07:39.18#ibcon#flushed, iclass 4, count 0 2006.201.15:07:39.18#ibcon#about to write, iclass 4, count 0 2006.201.15:07:39.18#ibcon#wrote, iclass 4, count 0 2006.201.15:07:39.18#ibcon#about to read 3, iclass 4, count 0 2006.201.15:07:39.21#ibcon#read 3, iclass 4, count 0 2006.201.15:07:39.21#ibcon#about to read 4, iclass 4, count 0 2006.201.15:07:39.21#ibcon#read 4, iclass 4, count 0 2006.201.15:07:39.21#ibcon#about to read 5, iclass 4, count 0 2006.201.15:07:39.21#ibcon#read 5, iclass 4, count 0 2006.201.15:07:39.21#ibcon#about to read 6, iclass 4, count 0 2006.201.15:07:39.21#ibcon#read 6, iclass 4, count 0 2006.201.15:07:39.21#ibcon#end of sib2, iclass 4, count 0 2006.201.15:07:39.21#ibcon#*after write, iclass 4, count 0 2006.201.15:07:39.21#ibcon#*before return 0, iclass 4, count 0 2006.201.15:07:39.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:39.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:07:39.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:07:39.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:07:39.21$vck44/vblo=6,719.99 2006.201.15:07:39.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.15:07:39.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.15:07:39.21#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:39.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:39.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:39.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:39.21#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:07:39.21#ibcon#first serial, iclass 6, count 0 2006.201.15:07:39.21#ibcon#enter sib2, iclass 6, count 0 2006.201.15:07:39.21#ibcon#flushed, iclass 6, count 0 2006.201.15:07:39.21#ibcon#about to write, iclass 6, count 0 2006.201.15:07:39.21#ibcon#wrote, iclass 6, count 0 2006.201.15:07:39.21#ibcon#about to read 3, iclass 6, count 0 2006.201.15:07:39.23#ibcon#read 3, iclass 6, count 0 2006.201.15:07:39.23#ibcon#about to read 4, iclass 6, count 0 2006.201.15:07:39.23#ibcon#read 4, iclass 6, count 0 2006.201.15:07:39.23#ibcon#about to read 5, iclass 6, count 0 2006.201.15:07:39.23#ibcon#read 5, iclass 6, count 0 2006.201.15:07:39.23#ibcon#about to read 6, iclass 6, count 0 2006.201.15:07:39.23#ibcon#read 6, iclass 6, count 0 2006.201.15:07:39.23#ibcon#end of sib2, iclass 6, count 0 2006.201.15:07:39.23#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:07:39.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:07:39.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:07:39.23#ibcon#*before write, iclass 6, count 0 2006.201.15:07:39.23#ibcon#enter sib2, iclass 6, count 0 2006.201.15:07:39.23#ibcon#flushed, iclass 6, count 0 2006.201.15:07:39.23#ibcon#about to write, iclass 6, count 0 2006.201.15:07:39.23#ibcon#wrote, iclass 6, count 0 2006.201.15:07:39.23#ibcon#about to read 3, iclass 6, count 0 2006.201.15:07:39.27#ibcon#read 3, iclass 6, count 0 2006.201.15:07:39.27#ibcon#about to read 4, iclass 6, count 0 2006.201.15:07:39.27#ibcon#read 4, iclass 6, count 0 2006.201.15:07:39.27#ibcon#about to read 5, iclass 6, count 0 2006.201.15:07:39.27#ibcon#read 5, iclass 6, count 0 2006.201.15:07:39.27#ibcon#about to read 6, iclass 6, count 0 2006.201.15:07:39.27#ibcon#read 6, iclass 6, count 0 2006.201.15:07:39.27#ibcon#end of sib2, iclass 6, count 0 2006.201.15:07:39.27#ibcon#*after write, iclass 6, count 0 2006.201.15:07:39.27#ibcon#*before return 0, iclass 6, count 0 2006.201.15:07:39.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:39.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:07:39.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:07:39.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:07:39.27$vck44/vb=6,4 2006.201.15:07:39.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.15:07:39.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.15:07:39.27#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:39.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:39.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:39.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:39.33#ibcon#enter wrdev, iclass 10, count 2 2006.201.15:07:39.33#ibcon#first serial, iclass 10, count 2 2006.201.15:07:39.33#ibcon#enter sib2, iclass 10, count 2 2006.201.15:07:39.33#ibcon#flushed, iclass 10, count 2 2006.201.15:07:39.33#ibcon#about to write, iclass 10, count 2 2006.201.15:07:39.33#ibcon#wrote, iclass 10, count 2 2006.201.15:07:39.33#ibcon#about to read 3, iclass 10, count 2 2006.201.15:07:39.35#ibcon#read 3, iclass 10, count 2 2006.201.15:07:39.35#ibcon#about to read 4, iclass 10, count 2 2006.201.15:07:39.35#ibcon#read 4, iclass 10, count 2 2006.201.15:07:39.35#ibcon#about to read 5, iclass 10, count 2 2006.201.15:07:39.35#ibcon#read 5, iclass 10, count 2 2006.201.15:07:39.35#ibcon#about to read 6, iclass 10, count 2 2006.201.15:07:39.35#ibcon#read 6, iclass 10, count 2 2006.201.15:07:39.35#ibcon#end of sib2, iclass 10, count 2 2006.201.15:07:39.35#ibcon#*mode == 0, iclass 10, count 2 2006.201.15:07:39.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.15:07:39.35#ibcon#[27=AT06-04\r\n] 2006.201.15:07:39.35#ibcon#*before write, iclass 10, count 2 2006.201.15:07:39.35#ibcon#enter sib2, iclass 10, count 2 2006.201.15:07:39.35#ibcon#flushed, iclass 10, count 2 2006.201.15:07:39.35#ibcon#about to write, iclass 10, count 2 2006.201.15:07:39.35#ibcon#wrote, iclass 10, count 2 2006.201.15:07:39.35#ibcon#about to read 3, iclass 10, count 2 2006.201.15:07:39.38#ibcon#read 3, iclass 10, count 2 2006.201.15:07:39.38#ibcon#about to read 4, iclass 10, count 2 2006.201.15:07:39.38#ibcon#read 4, iclass 10, count 2 2006.201.15:07:39.38#ibcon#about to read 5, iclass 10, count 2 2006.201.15:07:39.38#ibcon#read 5, iclass 10, count 2 2006.201.15:07:39.38#ibcon#about to read 6, iclass 10, count 2 2006.201.15:07:39.38#ibcon#read 6, iclass 10, count 2 2006.201.15:07:39.38#ibcon#end of sib2, iclass 10, count 2 2006.201.15:07:39.38#ibcon#*after write, iclass 10, count 2 2006.201.15:07:39.38#ibcon#*before return 0, iclass 10, count 2 2006.201.15:07:39.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:39.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:07:39.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.15:07:39.38#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:39.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:39.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:39.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:39.50#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:07:39.50#ibcon#first serial, iclass 10, count 0 2006.201.15:07:39.50#ibcon#enter sib2, iclass 10, count 0 2006.201.15:07:39.50#ibcon#flushed, iclass 10, count 0 2006.201.15:07:39.50#ibcon#about to write, iclass 10, count 0 2006.201.15:07:39.50#ibcon#wrote, iclass 10, count 0 2006.201.15:07:39.50#ibcon#about to read 3, iclass 10, count 0 2006.201.15:07:39.52#ibcon#read 3, iclass 10, count 0 2006.201.15:07:39.52#ibcon#about to read 4, iclass 10, count 0 2006.201.15:07:39.52#ibcon#read 4, iclass 10, count 0 2006.201.15:07:39.52#ibcon#about to read 5, iclass 10, count 0 2006.201.15:07:39.52#ibcon#read 5, iclass 10, count 0 2006.201.15:07:39.52#ibcon#about to read 6, iclass 10, count 0 2006.201.15:07:39.52#ibcon#read 6, iclass 10, count 0 2006.201.15:07:39.52#ibcon#end of sib2, iclass 10, count 0 2006.201.15:07:39.52#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:07:39.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:07:39.52#ibcon#[27=USB\r\n] 2006.201.15:07:39.52#ibcon#*before write, iclass 10, count 0 2006.201.15:07:39.52#ibcon#enter sib2, iclass 10, count 0 2006.201.15:07:39.52#ibcon#flushed, iclass 10, count 0 2006.201.15:07:39.52#ibcon#about to write, iclass 10, count 0 2006.201.15:07:39.52#ibcon#wrote, iclass 10, count 0 2006.201.15:07:39.52#ibcon#about to read 3, iclass 10, count 0 2006.201.15:07:39.55#ibcon#read 3, iclass 10, count 0 2006.201.15:07:39.55#ibcon#about to read 4, iclass 10, count 0 2006.201.15:07:39.55#ibcon#read 4, iclass 10, count 0 2006.201.15:07:39.55#ibcon#about to read 5, iclass 10, count 0 2006.201.15:07:39.55#ibcon#read 5, iclass 10, count 0 2006.201.15:07:39.55#ibcon#about to read 6, iclass 10, count 0 2006.201.15:07:39.55#ibcon#read 6, iclass 10, count 0 2006.201.15:07:39.55#ibcon#end of sib2, iclass 10, count 0 2006.201.15:07:39.55#ibcon#*after write, iclass 10, count 0 2006.201.15:07:39.55#ibcon#*before return 0, iclass 10, count 0 2006.201.15:07:39.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:39.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:07:39.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:07:39.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:07:39.55$vck44/vblo=7,734.99 2006.201.15:07:39.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.15:07:39.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.15:07:39.55#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:39.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:39.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:39.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:39.55#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:07:39.55#ibcon#first serial, iclass 12, count 0 2006.201.15:07:39.55#ibcon#enter sib2, iclass 12, count 0 2006.201.15:07:39.55#ibcon#flushed, iclass 12, count 0 2006.201.15:07:39.55#ibcon#about to write, iclass 12, count 0 2006.201.15:07:39.55#ibcon#wrote, iclass 12, count 0 2006.201.15:07:39.55#ibcon#about to read 3, iclass 12, count 0 2006.201.15:07:39.57#ibcon#read 3, iclass 12, count 0 2006.201.15:07:39.57#ibcon#about to read 4, iclass 12, count 0 2006.201.15:07:39.57#ibcon#read 4, iclass 12, count 0 2006.201.15:07:39.57#ibcon#about to read 5, iclass 12, count 0 2006.201.15:07:39.57#ibcon#read 5, iclass 12, count 0 2006.201.15:07:39.57#ibcon#about to read 6, iclass 12, count 0 2006.201.15:07:39.57#ibcon#read 6, iclass 12, count 0 2006.201.15:07:39.57#ibcon#end of sib2, iclass 12, count 0 2006.201.15:07:39.57#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:07:39.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:07:39.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:07:39.57#ibcon#*before write, iclass 12, count 0 2006.201.15:07:39.57#ibcon#enter sib2, iclass 12, count 0 2006.201.15:07:39.57#ibcon#flushed, iclass 12, count 0 2006.201.15:07:39.57#ibcon#about to write, iclass 12, count 0 2006.201.15:07:39.57#ibcon#wrote, iclass 12, count 0 2006.201.15:07:39.57#ibcon#about to read 3, iclass 12, count 0 2006.201.15:07:39.61#ibcon#read 3, iclass 12, count 0 2006.201.15:07:39.61#ibcon#about to read 4, iclass 12, count 0 2006.201.15:07:39.61#ibcon#read 4, iclass 12, count 0 2006.201.15:07:39.61#ibcon#about to read 5, iclass 12, count 0 2006.201.15:07:39.61#ibcon#read 5, iclass 12, count 0 2006.201.15:07:39.61#ibcon#about to read 6, iclass 12, count 0 2006.201.15:07:39.61#ibcon#read 6, iclass 12, count 0 2006.201.15:07:39.61#ibcon#end of sib2, iclass 12, count 0 2006.201.15:07:39.61#ibcon#*after write, iclass 12, count 0 2006.201.15:07:39.61#ibcon#*before return 0, iclass 12, count 0 2006.201.15:07:39.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:39.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:07:39.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:07:39.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:07:39.61$vck44/vb=7,4 2006.201.15:07:39.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.15:07:39.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.15:07:39.61#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:39.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:39.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:39.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:39.67#ibcon#enter wrdev, iclass 14, count 2 2006.201.15:07:39.67#ibcon#first serial, iclass 14, count 2 2006.201.15:07:39.67#ibcon#enter sib2, iclass 14, count 2 2006.201.15:07:39.67#ibcon#flushed, iclass 14, count 2 2006.201.15:07:39.67#ibcon#about to write, iclass 14, count 2 2006.201.15:07:39.67#ibcon#wrote, iclass 14, count 2 2006.201.15:07:39.67#ibcon#about to read 3, iclass 14, count 2 2006.201.15:07:39.69#ibcon#read 3, iclass 14, count 2 2006.201.15:07:39.69#ibcon#about to read 4, iclass 14, count 2 2006.201.15:07:39.69#ibcon#read 4, iclass 14, count 2 2006.201.15:07:39.69#ibcon#about to read 5, iclass 14, count 2 2006.201.15:07:39.69#ibcon#read 5, iclass 14, count 2 2006.201.15:07:39.69#ibcon#about to read 6, iclass 14, count 2 2006.201.15:07:39.69#ibcon#read 6, iclass 14, count 2 2006.201.15:07:39.69#ibcon#end of sib2, iclass 14, count 2 2006.201.15:07:39.69#ibcon#*mode == 0, iclass 14, count 2 2006.201.15:07:39.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.15:07:39.69#ibcon#[27=AT07-04\r\n] 2006.201.15:07:39.69#ibcon#*before write, iclass 14, count 2 2006.201.15:07:39.69#ibcon#enter sib2, iclass 14, count 2 2006.201.15:07:39.69#ibcon#flushed, iclass 14, count 2 2006.201.15:07:39.69#ibcon#about to write, iclass 14, count 2 2006.201.15:07:39.69#ibcon#wrote, iclass 14, count 2 2006.201.15:07:39.69#ibcon#about to read 3, iclass 14, count 2 2006.201.15:07:39.72#ibcon#read 3, iclass 14, count 2 2006.201.15:07:39.72#ibcon#about to read 4, iclass 14, count 2 2006.201.15:07:39.72#ibcon#read 4, iclass 14, count 2 2006.201.15:07:39.72#ibcon#about to read 5, iclass 14, count 2 2006.201.15:07:39.72#ibcon#read 5, iclass 14, count 2 2006.201.15:07:39.72#ibcon#about to read 6, iclass 14, count 2 2006.201.15:07:39.72#ibcon#read 6, iclass 14, count 2 2006.201.15:07:39.72#ibcon#end of sib2, iclass 14, count 2 2006.201.15:07:39.72#ibcon#*after write, iclass 14, count 2 2006.201.15:07:39.72#ibcon#*before return 0, iclass 14, count 2 2006.201.15:07:39.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:39.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:07:39.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.15:07:39.72#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:39.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:39.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:39.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:39.84#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:07:39.84#ibcon#first serial, iclass 14, count 0 2006.201.15:07:39.84#ibcon#enter sib2, iclass 14, count 0 2006.201.15:07:39.84#ibcon#flushed, iclass 14, count 0 2006.201.15:07:39.84#ibcon#about to write, iclass 14, count 0 2006.201.15:07:39.84#ibcon#wrote, iclass 14, count 0 2006.201.15:07:39.84#ibcon#about to read 3, iclass 14, count 0 2006.201.15:07:39.86#ibcon#read 3, iclass 14, count 0 2006.201.15:07:39.86#ibcon#about to read 4, iclass 14, count 0 2006.201.15:07:39.86#ibcon#read 4, iclass 14, count 0 2006.201.15:07:39.86#ibcon#about to read 5, iclass 14, count 0 2006.201.15:07:39.86#ibcon#read 5, iclass 14, count 0 2006.201.15:07:39.86#ibcon#about to read 6, iclass 14, count 0 2006.201.15:07:39.86#ibcon#read 6, iclass 14, count 0 2006.201.15:07:39.86#ibcon#end of sib2, iclass 14, count 0 2006.201.15:07:39.86#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:07:39.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:07:39.86#ibcon#[27=USB\r\n] 2006.201.15:07:39.86#ibcon#*before write, iclass 14, count 0 2006.201.15:07:39.86#ibcon#enter sib2, iclass 14, count 0 2006.201.15:07:39.86#ibcon#flushed, iclass 14, count 0 2006.201.15:07:39.86#ibcon#about to write, iclass 14, count 0 2006.201.15:07:39.86#ibcon#wrote, iclass 14, count 0 2006.201.15:07:39.86#ibcon#about to read 3, iclass 14, count 0 2006.201.15:07:39.89#ibcon#read 3, iclass 14, count 0 2006.201.15:07:39.89#ibcon#about to read 4, iclass 14, count 0 2006.201.15:07:39.89#ibcon#read 4, iclass 14, count 0 2006.201.15:07:39.89#ibcon#about to read 5, iclass 14, count 0 2006.201.15:07:39.89#ibcon#read 5, iclass 14, count 0 2006.201.15:07:39.89#ibcon#about to read 6, iclass 14, count 0 2006.201.15:07:39.89#ibcon#read 6, iclass 14, count 0 2006.201.15:07:39.89#ibcon#end of sib2, iclass 14, count 0 2006.201.15:07:39.89#ibcon#*after write, iclass 14, count 0 2006.201.15:07:39.89#ibcon#*before return 0, iclass 14, count 0 2006.201.15:07:39.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:39.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:07:39.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:07:39.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:07:39.89$vck44/vblo=8,744.99 2006.201.15:07:39.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.15:07:39.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.15:07:39.89#ibcon#ireg 17 cls_cnt 0 2006.201.15:07:39.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:39.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:39.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:39.89#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:07:39.89#ibcon#first serial, iclass 16, count 0 2006.201.15:07:39.89#ibcon#enter sib2, iclass 16, count 0 2006.201.15:07:39.89#ibcon#flushed, iclass 16, count 0 2006.201.15:07:39.89#ibcon#about to write, iclass 16, count 0 2006.201.15:07:39.89#ibcon#wrote, iclass 16, count 0 2006.201.15:07:39.89#ibcon#about to read 3, iclass 16, count 0 2006.201.15:07:39.91#ibcon#read 3, iclass 16, count 0 2006.201.15:07:39.91#ibcon#about to read 4, iclass 16, count 0 2006.201.15:07:39.91#ibcon#read 4, iclass 16, count 0 2006.201.15:07:39.91#ibcon#about to read 5, iclass 16, count 0 2006.201.15:07:39.91#ibcon#read 5, iclass 16, count 0 2006.201.15:07:39.91#ibcon#about to read 6, iclass 16, count 0 2006.201.15:07:39.91#ibcon#read 6, iclass 16, count 0 2006.201.15:07:39.91#ibcon#end of sib2, iclass 16, count 0 2006.201.15:07:39.91#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:07:39.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:07:39.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:07:39.91#ibcon#*before write, iclass 16, count 0 2006.201.15:07:39.91#ibcon#enter sib2, iclass 16, count 0 2006.201.15:07:39.91#ibcon#flushed, iclass 16, count 0 2006.201.15:07:39.91#ibcon#about to write, iclass 16, count 0 2006.201.15:07:39.91#ibcon#wrote, iclass 16, count 0 2006.201.15:07:39.91#ibcon#about to read 3, iclass 16, count 0 2006.201.15:07:39.95#ibcon#read 3, iclass 16, count 0 2006.201.15:07:39.95#ibcon#about to read 4, iclass 16, count 0 2006.201.15:07:39.95#ibcon#read 4, iclass 16, count 0 2006.201.15:07:39.95#ibcon#about to read 5, iclass 16, count 0 2006.201.15:07:39.95#ibcon#read 5, iclass 16, count 0 2006.201.15:07:39.95#ibcon#about to read 6, iclass 16, count 0 2006.201.15:07:39.95#ibcon#read 6, iclass 16, count 0 2006.201.15:07:39.95#ibcon#end of sib2, iclass 16, count 0 2006.201.15:07:39.95#ibcon#*after write, iclass 16, count 0 2006.201.15:07:39.95#ibcon#*before return 0, iclass 16, count 0 2006.201.15:07:39.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:39.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:07:39.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:07:39.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:07:39.95$vck44/vb=8,4 2006.201.15:07:39.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.15:07:39.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.15:07:39.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:07:39.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:40.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:40.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:40.01#ibcon#enter wrdev, iclass 18, count 2 2006.201.15:07:40.01#ibcon#first serial, iclass 18, count 2 2006.201.15:07:40.01#ibcon#enter sib2, iclass 18, count 2 2006.201.15:07:40.01#ibcon#flushed, iclass 18, count 2 2006.201.15:07:40.01#ibcon#about to write, iclass 18, count 2 2006.201.15:07:40.01#ibcon#wrote, iclass 18, count 2 2006.201.15:07:40.01#ibcon#about to read 3, iclass 18, count 2 2006.201.15:07:40.03#ibcon#read 3, iclass 18, count 2 2006.201.15:07:40.03#ibcon#about to read 4, iclass 18, count 2 2006.201.15:07:40.03#ibcon#read 4, iclass 18, count 2 2006.201.15:07:40.03#ibcon#about to read 5, iclass 18, count 2 2006.201.15:07:40.03#ibcon#read 5, iclass 18, count 2 2006.201.15:07:40.03#ibcon#about to read 6, iclass 18, count 2 2006.201.15:07:40.03#ibcon#read 6, iclass 18, count 2 2006.201.15:07:40.03#ibcon#end of sib2, iclass 18, count 2 2006.201.15:07:40.03#ibcon#*mode == 0, iclass 18, count 2 2006.201.15:07:40.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.15:07:40.03#ibcon#[27=AT08-04\r\n] 2006.201.15:07:40.03#ibcon#*before write, iclass 18, count 2 2006.201.15:07:40.03#ibcon#enter sib2, iclass 18, count 2 2006.201.15:07:40.03#ibcon#flushed, iclass 18, count 2 2006.201.15:07:40.03#ibcon#about to write, iclass 18, count 2 2006.201.15:07:40.03#ibcon#wrote, iclass 18, count 2 2006.201.15:07:40.03#ibcon#about to read 3, iclass 18, count 2 2006.201.15:07:40.05#abcon#<5=/04 0.9 2.1 20.771001003.2\r\n> 2006.201.15:07:40.06#ibcon#read 3, iclass 18, count 2 2006.201.15:07:40.06#ibcon#about to read 4, iclass 18, count 2 2006.201.15:07:40.06#ibcon#read 4, iclass 18, count 2 2006.201.15:07:40.06#ibcon#about to read 5, iclass 18, count 2 2006.201.15:07:40.06#ibcon#read 5, iclass 18, count 2 2006.201.15:07:40.06#ibcon#about to read 6, iclass 18, count 2 2006.201.15:07:40.06#ibcon#read 6, iclass 18, count 2 2006.201.15:07:40.06#ibcon#end of sib2, iclass 18, count 2 2006.201.15:07:40.06#ibcon#*after write, iclass 18, count 2 2006.201.15:07:40.06#ibcon#*before return 0, iclass 18, count 2 2006.201.15:07:40.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:40.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:07:40.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.15:07:40.06#ibcon#ireg 7 cls_cnt 0 2006.201.15:07:40.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:40.07#abcon#{5=INTERFACE CLEAR} 2006.201.15:07:40.13#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:07:40.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:40.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:40.18#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:07:40.18#ibcon#first serial, iclass 18, count 0 2006.201.15:07:40.18#ibcon#enter sib2, iclass 18, count 0 2006.201.15:07:40.18#ibcon#flushed, iclass 18, count 0 2006.201.15:07:40.18#ibcon#about to write, iclass 18, count 0 2006.201.15:07:40.18#ibcon#wrote, iclass 18, count 0 2006.201.15:07:40.18#ibcon#about to read 3, iclass 18, count 0 2006.201.15:07:40.20#ibcon#read 3, iclass 18, count 0 2006.201.15:07:40.20#ibcon#about to read 4, iclass 18, count 0 2006.201.15:07:40.20#ibcon#read 4, iclass 18, count 0 2006.201.15:07:40.20#ibcon#about to read 5, iclass 18, count 0 2006.201.15:07:40.20#ibcon#read 5, iclass 18, count 0 2006.201.15:07:40.20#ibcon#about to read 6, iclass 18, count 0 2006.201.15:07:40.20#ibcon#read 6, iclass 18, count 0 2006.201.15:07:40.20#ibcon#end of sib2, iclass 18, count 0 2006.201.15:07:40.20#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:07:40.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:07:40.20#ibcon#[27=USB\r\n] 2006.201.15:07:40.20#ibcon#*before write, iclass 18, count 0 2006.201.15:07:40.20#ibcon#enter sib2, iclass 18, count 0 2006.201.15:07:40.20#ibcon#flushed, iclass 18, count 0 2006.201.15:07:40.20#ibcon#about to write, iclass 18, count 0 2006.201.15:07:40.20#ibcon#wrote, iclass 18, count 0 2006.201.15:07:40.20#ibcon#about to read 3, iclass 18, count 0 2006.201.15:07:40.23#ibcon#read 3, iclass 18, count 0 2006.201.15:07:40.23#ibcon#about to read 4, iclass 18, count 0 2006.201.15:07:40.23#ibcon#read 4, iclass 18, count 0 2006.201.15:07:40.23#ibcon#about to read 5, iclass 18, count 0 2006.201.15:07:40.23#ibcon#read 5, iclass 18, count 0 2006.201.15:07:40.23#ibcon#about to read 6, iclass 18, count 0 2006.201.15:07:40.23#ibcon#read 6, iclass 18, count 0 2006.201.15:07:40.23#ibcon#end of sib2, iclass 18, count 0 2006.201.15:07:40.23#ibcon#*after write, iclass 18, count 0 2006.201.15:07:40.23#ibcon#*before return 0, iclass 18, count 0 2006.201.15:07:40.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:40.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:07:40.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:07:40.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:07:40.23$vck44/vabw=wide 2006.201.15:07:40.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.15:07:40.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.15:07:40.23#ibcon#ireg 8 cls_cnt 0 2006.201.15:07:40.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:40.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:40.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:40.23#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:07:40.23#ibcon#first serial, iclass 24, count 0 2006.201.15:07:40.23#ibcon#enter sib2, iclass 24, count 0 2006.201.15:07:40.23#ibcon#flushed, iclass 24, count 0 2006.201.15:07:40.23#ibcon#about to write, iclass 24, count 0 2006.201.15:07:40.23#ibcon#wrote, iclass 24, count 0 2006.201.15:07:40.23#ibcon#about to read 3, iclass 24, count 0 2006.201.15:07:40.25#ibcon#read 3, iclass 24, count 0 2006.201.15:07:40.25#ibcon#about to read 4, iclass 24, count 0 2006.201.15:07:40.25#ibcon#read 4, iclass 24, count 0 2006.201.15:07:40.25#ibcon#about to read 5, iclass 24, count 0 2006.201.15:07:40.25#ibcon#read 5, iclass 24, count 0 2006.201.15:07:40.25#ibcon#about to read 6, iclass 24, count 0 2006.201.15:07:40.25#ibcon#read 6, iclass 24, count 0 2006.201.15:07:40.25#ibcon#end of sib2, iclass 24, count 0 2006.201.15:07:40.25#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:07:40.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:07:40.25#ibcon#[25=BW32\r\n] 2006.201.15:07:40.25#ibcon#*before write, iclass 24, count 0 2006.201.15:07:40.25#ibcon#enter sib2, iclass 24, count 0 2006.201.15:07:40.25#ibcon#flushed, iclass 24, count 0 2006.201.15:07:40.25#ibcon#about to write, iclass 24, count 0 2006.201.15:07:40.25#ibcon#wrote, iclass 24, count 0 2006.201.15:07:40.25#ibcon#about to read 3, iclass 24, count 0 2006.201.15:07:40.28#ibcon#read 3, iclass 24, count 0 2006.201.15:07:40.28#ibcon#about to read 4, iclass 24, count 0 2006.201.15:07:40.28#ibcon#read 4, iclass 24, count 0 2006.201.15:07:40.28#ibcon#about to read 5, iclass 24, count 0 2006.201.15:07:40.28#ibcon#read 5, iclass 24, count 0 2006.201.15:07:40.28#ibcon#about to read 6, iclass 24, count 0 2006.201.15:07:40.28#ibcon#read 6, iclass 24, count 0 2006.201.15:07:40.28#ibcon#end of sib2, iclass 24, count 0 2006.201.15:07:40.28#ibcon#*after write, iclass 24, count 0 2006.201.15:07:40.28#ibcon#*before return 0, iclass 24, count 0 2006.201.15:07:40.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:40.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:07:40.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:07:40.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:07:40.28$vck44/vbbw=wide 2006.201.15:07:40.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.15:07:40.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.15:07:40.28#ibcon#ireg 8 cls_cnt 0 2006.201.15:07:40.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:07:40.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:07:40.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:07:40.35#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:07:40.35#ibcon#first serial, iclass 26, count 0 2006.201.15:07:40.35#ibcon#enter sib2, iclass 26, count 0 2006.201.15:07:40.35#ibcon#flushed, iclass 26, count 0 2006.201.15:07:40.35#ibcon#about to write, iclass 26, count 0 2006.201.15:07:40.35#ibcon#wrote, iclass 26, count 0 2006.201.15:07:40.35#ibcon#about to read 3, iclass 26, count 0 2006.201.15:07:40.37#ibcon#read 3, iclass 26, count 0 2006.201.15:07:40.37#ibcon#about to read 4, iclass 26, count 0 2006.201.15:07:40.37#ibcon#read 4, iclass 26, count 0 2006.201.15:07:40.37#ibcon#about to read 5, iclass 26, count 0 2006.201.15:07:40.37#ibcon#read 5, iclass 26, count 0 2006.201.15:07:40.37#ibcon#about to read 6, iclass 26, count 0 2006.201.15:07:40.37#ibcon#read 6, iclass 26, count 0 2006.201.15:07:40.37#ibcon#end of sib2, iclass 26, count 0 2006.201.15:07:40.37#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:07:40.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:07:40.37#ibcon#[27=BW32\r\n] 2006.201.15:07:40.37#ibcon#*before write, iclass 26, count 0 2006.201.15:07:40.37#ibcon#enter sib2, iclass 26, count 0 2006.201.15:07:40.37#ibcon#flushed, iclass 26, count 0 2006.201.15:07:40.37#ibcon#about to write, iclass 26, count 0 2006.201.15:07:40.37#ibcon#wrote, iclass 26, count 0 2006.201.15:07:40.37#ibcon#about to read 3, iclass 26, count 0 2006.201.15:07:40.40#ibcon#read 3, iclass 26, count 0 2006.201.15:07:40.40#ibcon#about to read 4, iclass 26, count 0 2006.201.15:07:40.40#ibcon#read 4, iclass 26, count 0 2006.201.15:07:40.40#ibcon#about to read 5, iclass 26, count 0 2006.201.15:07:40.40#ibcon#read 5, iclass 26, count 0 2006.201.15:07:40.40#ibcon#about to read 6, iclass 26, count 0 2006.201.15:07:40.40#ibcon#read 6, iclass 26, count 0 2006.201.15:07:40.40#ibcon#end of sib2, iclass 26, count 0 2006.201.15:07:40.40#ibcon#*after write, iclass 26, count 0 2006.201.15:07:40.40#ibcon#*before return 0, iclass 26, count 0 2006.201.15:07:40.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:07:40.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:07:40.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:07:40.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:07:40.40$setupk4/ifdk4 2006.201.15:07:40.40$ifdk4/lo= 2006.201.15:07:40.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:07:40.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:07:40.40$ifdk4/patch= 2006.201.15:07:40.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:07:40.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:07:40.40$setupk4/!*+20s 2006.201.15:07:50.22#abcon#<5=/04 0.9 2.1 20.771001003.2\r\n> 2006.201.15:07:50.24#abcon#{5=INTERFACE CLEAR} 2006.201.15:07:50.30#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:07:54.91$setupk4/"tpicd 2006.201.15:07:54.91$setupk4/echo=off 2006.201.15:07:54.91$setupk4/xlog=off 2006.201.15:07:54.91:!2006.201.15:12:09 2006.201.15:08:06.14#trakl#Source acquired 2006.201.15:08:06.14#flagr#flagr/antenna,acquired 2006.201.15:12:09.00:preob 2006.201.15:12:10.13/onsource/TRACKING 2006.201.15:12:10.13:!2006.201.15:12:19 2006.201.15:12:19.00:"tape 2006.201.15:12:19.00:"st=record 2006.201.15:12:19.00:data_valid=on 2006.201.15:12:19.00:midob 2006.201.15:12:19.13/onsource/TRACKING 2006.201.15:12:19.13/wx/20.78,1003.2,100 2006.201.15:12:19.29/cable/+6.4743E-03 2006.201.15:12:20.38/va/01,08,usb,yes,28,30 2006.201.15:12:20.38/va/02,07,usb,yes,30,31 2006.201.15:12:20.38/va/03,08,usb,yes,27,28 2006.201.15:12:20.38/va/04,07,usb,yes,31,32 2006.201.15:12:20.38/va/05,04,usb,yes,27,28 2006.201.15:12:20.38/va/06,05,usb,yes,27,27 2006.201.15:12:20.38/va/07,05,usb,yes,26,28 2006.201.15:12:20.38/va/08,04,usb,yes,26,32 2006.201.15:12:20.61/valo/01,524.99,yes,locked 2006.201.15:12:20.61/valo/02,534.99,yes,locked 2006.201.15:12:20.61/valo/03,564.99,yes,locked 2006.201.15:12:20.61/valo/04,624.99,yes,locked 2006.201.15:12:20.61/valo/05,734.99,yes,locked 2006.201.15:12:20.61/valo/06,814.99,yes,locked 2006.201.15:12:20.61/valo/07,864.99,yes,locked 2006.201.15:12:20.61/valo/08,884.99,yes,locked 2006.201.15:12:21.70/vb/01,04,usb,yes,28,26 2006.201.15:12:21.70/vb/02,05,usb,yes,27,26 2006.201.15:12:21.70/vb/03,04,usb,yes,27,30 2006.201.15:12:21.70/vb/04,05,usb,yes,28,27 2006.201.15:12:21.70/vb/05,04,usb,yes,24,27 2006.201.15:12:21.70/vb/06,04,usb,yes,28,25 2006.201.15:12:21.70/vb/07,04,usb,yes,28,28 2006.201.15:12:21.70/vb/08,04,usb,yes,26,29 2006.201.15:12:21.93/vblo/01,629.99,yes,locked 2006.201.15:12:21.93/vblo/02,634.99,yes,locked 2006.201.15:12:21.93/vblo/03,649.99,yes,locked 2006.201.15:12:21.93/vblo/04,679.99,yes,locked 2006.201.15:12:21.93/vblo/05,709.99,yes,locked 2006.201.15:12:21.93/vblo/06,719.99,yes,locked 2006.201.15:12:21.93/vblo/07,734.99,yes,locked 2006.201.15:12:21.93/vblo/08,744.99,yes,locked 2006.201.15:12:22.08/vabw/8 2006.201.15:12:22.23/vbbw/8 2006.201.15:12:22.32/xfe/off,on,15.0 2006.201.15:12:22.70/ifatt/23,28,28,28 2006.201.15:12:23.06/fmout-gps/S +4.55E-07 2006.201.15:12:23.13:!2006.201.15:14:19 2006.201.15:14:19.00:data_valid=off 2006.201.15:14:19.00:"et 2006.201.15:14:19.00:!+3s 2006.201.15:14:22.02:"tape 2006.201.15:14:22.02:postob 2006.201.15:14:22.16/cable/+6.4747E-03 2006.201.15:14:22.16/wx/20.78,1003.2,100 2006.201.15:14:22.22/fmout-gps/S +4.55E-07 2006.201.15:14:22.22:scan_name=201-1520,jd0607,40 2006.201.15:14:22.22:source=1921-293,192451.06,-291430.1,2000.0,cw 2006.201.15:14:23.14#flagr#flagr/antenna,new-source 2006.201.15:14:23.14:checkk5 2006.201.15:14:23.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:14:23.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:14:24.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:14:24.61/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:14:24.97/chk_obsdata//k5ts1/T2011512??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.15:14:25.35/chk_obsdata//k5ts2/T2011512??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.15:14:25.72/chk_obsdata//k5ts3/T2011512??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.15:14:26.08/chk_obsdata//k5ts4/T2011512??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.15:14:26.77/k5log//k5ts1_log_newline 2006.201.15:14:27.47/k5log//k5ts2_log_newline 2006.201.15:14:28.16/k5log//k5ts3_log_newline 2006.201.15:14:28.85/k5log//k5ts4_log_newline 2006.201.15:14:28.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:14:28.87:setupk4=1 2006.201.15:14:28.87$setupk4/echo=on 2006.201.15:14:28.87$setupk4/pcalon 2006.201.15:14:28.87$pcalon/"no phase cal control is implemented here 2006.201.15:14:28.87$setupk4/"tpicd=stop 2006.201.15:14:28.87$setupk4/"rec=synch_on 2006.201.15:14:28.87$setupk4/"rec_mode=128 2006.201.15:14:28.87$setupk4/!* 2006.201.15:14:28.87$setupk4/recpk4 2006.201.15:14:28.87$recpk4/recpatch= 2006.201.15:14:28.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:14:28.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:14:28.88$setupk4/vck44 2006.201.15:14:28.88$vck44/valo=1,524.99 2006.201.15:14:28.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.15:14:28.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.15:14:28.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:28.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:28.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:28.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:28.88#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:14:28.88#ibcon#first serial, iclass 11, count 0 2006.201.15:14:28.88#ibcon#enter sib2, iclass 11, count 0 2006.201.15:14:28.88#ibcon#flushed, iclass 11, count 0 2006.201.15:14:28.88#ibcon#about to write, iclass 11, count 0 2006.201.15:14:28.88#ibcon#wrote, iclass 11, count 0 2006.201.15:14:28.88#ibcon#about to read 3, iclass 11, count 0 2006.201.15:14:28.91#ibcon#read 3, iclass 11, count 0 2006.201.15:14:28.91#ibcon#about to read 4, iclass 11, count 0 2006.201.15:14:28.91#ibcon#read 4, iclass 11, count 0 2006.201.15:14:28.91#ibcon#about to read 5, iclass 11, count 0 2006.201.15:14:28.91#ibcon#read 5, iclass 11, count 0 2006.201.15:14:28.91#ibcon#about to read 6, iclass 11, count 0 2006.201.15:14:28.91#ibcon#read 6, iclass 11, count 0 2006.201.15:14:28.91#ibcon#end of sib2, iclass 11, count 0 2006.201.15:14:28.91#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:14:28.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:14:28.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:14:28.91#ibcon#*before write, iclass 11, count 0 2006.201.15:14:28.91#ibcon#enter sib2, iclass 11, count 0 2006.201.15:14:28.91#ibcon#flushed, iclass 11, count 0 2006.201.15:14:28.91#ibcon#about to write, iclass 11, count 0 2006.201.15:14:28.91#ibcon#wrote, iclass 11, count 0 2006.201.15:14:28.91#ibcon#about to read 3, iclass 11, count 0 2006.201.15:14:28.96#ibcon#read 3, iclass 11, count 0 2006.201.15:14:28.96#ibcon#about to read 4, iclass 11, count 0 2006.201.15:14:28.96#ibcon#read 4, iclass 11, count 0 2006.201.15:14:28.96#ibcon#about to read 5, iclass 11, count 0 2006.201.15:14:28.96#ibcon#read 5, iclass 11, count 0 2006.201.15:14:28.96#ibcon#about to read 6, iclass 11, count 0 2006.201.15:14:28.96#ibcon#read 6, iclass 11, count 0 2006.201.15:14:28.96#ibcon#end of sib2, iclass 11, count 0 2006.201.15:14:28.96#ibcon#*after write, iclass 11, count 0 2006.201.15:14:28.96#ibcon#*before return 0, iclass 11, count 0 2006.201.15:14:28.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:28.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:28.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:14:28.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:14:28.96$vck44/va=1,8 2006.201.15:14:28.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.15:14:28.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.15:14:28.96#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:28.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:28.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:28.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:28.96#ibcon#enter wrdev, iclass 13, count 2 2006.201.15:14:28.96#ibcon#first serial, iclass 13, count 2 2006.201.15:14:28.96#ibcon#enter sib2, iclass 13, count 2 2006.201.15:14:28.96#ibcon#flushed, iclass 13, count 2 2006.201.15:14:28.96#ibcon#about to write, iclass 13, count 2 2006.201.15:14:28.96#ibcon#wrote, iclass 13, count 2 2006.201.15:14:28.96#ibcon#about to read 3, iclass 13, count 2 2006.201.15:14:28.98#ibcon#read 3, iclass 13, count 2 2006.201.15:14:28.98#ibcon#about to read 4, iclass 13, count 2 2006.201.15:14:28.98#ibcon#read 4, iclass 13, count 2 2006.201.15:14:28.98#ibcon#about to read 5, iclass 13, count 2 2006.201.15:14:28.98#ibcon#read 5, iclass 13, count 2 2006.201.15:14:28.98#ibcon#about to read 6, iclass 13, count 2 2006.201.15:14:28.98#ibcon#read 6, iclass 13, count 2 2006.201.15:14:28.98#ibcon#end of sib2, iclass 13, count 2 2006.201.15:14:28.98#ibcon#*mode == 0, iclass 13, count 2 2006.201.15:14:28.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.15:14:28.98#ibcon#[25=AT01-08\r\n] 2006.201.15:14:28.98#ibcon#*before write, iclass 13, count 2 2006.201.15:14:28.98#ibcon#enter sib2, iclass 13, count 2 2006.201.15:14:28.98#ibcon#flushed, iclass 13, count 2 2006.201.15:14:28.98#ibcon#about to write, iclass 13, count 2 2006.201.15:14:28.98#ibcon#wrote, iclass 13, count 2 2006.201.15:14:28.98#ibcon#about to read 3, iclass 13, count 2 2006.201.15:14:29.01#ibcon#read 3, iclass 13, count 2 2006.201.15:14:29.01#ibcon#about to read 4, iclass 13, count 2 2006.201.15:14:29.01#ibcon#read 4, iclass 13, count 2 2006.201.15:14:29.01#ibcon#about to read 5, iclass 13, count 2 2006.201.15:14:29.01#ibcon#read 5, iclass 13, count 2 2006.201.15:14:29.01#ibcon#about to read 6, iclass 13, count 2 2006.201.15:14:29.01#ibcon#read 6, iclass 13, count 2 2006.201.15:14:29.01#ibcon#end of sib2, iclass 13, count 2 2006.201.15:14:29.01#ibcon#*after write, iclass 13, count 2 2006.201.15:14:29.01#ibcon#*before return 0, iclass 13, count 2 2006.201.15:14:29.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:29.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:29.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.15:14:29.01#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:29.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:29.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:29.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:29.13#ibcon#enter wrdev, iclass 13, count 0 2006.201.15:14:29.13#ibcon#first serial, iclass 13, count 0 2006.201.15:14:29.13#ibcon#enter sib2, iclass 13, count 0 2006.201.15:14:29.13#ibcon#flushed, iclass 13, count 0 2006.201.15:14:29.13#ibcon#about to write, iclass 13, count 0 2006.201.15:14:29.13#ibcon#wrote, iclass 13, count 0 2006.201.15:14:29.13#ibcon#about to read 3, iclass 13, count 0 2006.201.15:14:29.15#ibcon#read 3, iclass 13, count 0 2006.201.15:14:29.15#ibcon#about to read 4, iclass 13, count 0 2006.201.15:14:29.15#ibcon#read 4, iclass 13, count 0 2006.201.15:14:29.15#ibcon#about to read 5, iclass 13, count 0 2006.201.15:14:29.15#ibcon#read 5, iclass 13, count 0 2006.201.15:14:29.15#ibcon#about to read 6, iclass 13, count 0 2006.201.15:14:29.15#ibcon#read 6, iclass 13, count 0 2006.201.15:14:29.15#ibcon#end of sib2, iclass 13, count 0 2006.201.15:14:29.15#ibcon#*mode == 0, iclass 13, count 0 2006.201.15:14:29.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.15:14:29.15#ibcon#[25=USB\r\n] 2006.201.15:14:29.15#ibcon#*before write, iclass 13, count 0 2006.201.15:14:29.15#ibcon#enter sib2, iclass 13, count 0 2006.201.15:14:29.15#ibcon#flushed, iclass 13, count 0 2006.201.15:14:29.15#ibcon#about to write, iclass 13, count 0 2006.201.15:14:29.15#ibcon#wrote, iclass 13, count 0 2006.201.15:14:29.15#ibcon#about to read 3, iclass 13, count 0 2006.201.15:14:29.18#ibcon#read 3, iclass 13, count 0 2006.201.15:14:29.18#ibcon#about to read 4, iclass 13, count 0 2006.201.15:14:29.18#ibcon#read 4, iclass 13, count 0 2006.201.15:14:29.18#ibcon#about to read 5, iclass 13, count 0 2006.201.15:14:29.18#ibcon#read 5, iclass 13, count 0 2006.201.15:14:29.18#ibcon#about to read 6, iclass 13, count 0 2006.201.15:14:29.18#ibcon#read 6, iclass 13, count 0 2006.201.15:14:29.18#ibcon#end of sib2, iclass 13, count 0 2006.201.15:14:29.18#ibcon#*after write, iclass 13, count 0 2006.201.15:14:29.18#ibcon#*before return 0, iclass 13, count 0 2006.201.15:14:29.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:29.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:29.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.15:14:29.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.15:14:29.18$vck44/valo=2,534.99 2006.201.15:14:29.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.15:14:29.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.15:14:29.18#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:29.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:29.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:29.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:29.18#ibcon#enter wrdev, iclass 15, count 0 2006.201.15:14:29.18#ibcon#first serial, iclass 15, count 0 2006.201.15:14:29.18#ibcon#enter sib2, iclass 15, count 0 2006.201.15:14:29.18#ibcon#flushed, iclass 15, count 0 2006.201.15:14:29.18#ibcon#about to write, iclass 15, count 0 2006.201.15:14:29.18#ibcon#wrote, iclass 15, count 0 2006.201.15:14:29.18#ibcon#about to read 3, iclass 15, count 0 2006.201.15:14:29.20#ibcon#read 3, iclass 15, count 0 2006.201.15:14:29.20#ibcon#about to read 4, iclass 15, count 0 2006.201.15:14:29.20#ibcon#read 4, iclass 15, count 0 2006.201.15:14:29.20#ibcon#about to read 5, iclass 15, count 0 2006.201.15:14:29.20#ibcon#read 5, iclass 15, count 0 2006.201.15:14:29.20#ibcon#about to read 6, iclass 15, count 0 2006.201.15:14:29.20#ibcon#read 6, iclass 15, count 0 2006.201.15:14:29.20#ibcon#end of sib2, iclass 15, count 0 2006.201.15:14:29.20#ibcon#*mode == 0, iclass 15, count 0 2006.201.15:14:29.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.15:14:29.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:14:29.20#ibcon#*before write, iclass 15, count 0 2006.201.15:14:29.20#ibcon#enter sib2, iclass 15, count 0 2006.201.15:14:29.20#ibcon#flushed, iclass 15, count 0 2006.201.15:14:29.20#ibcon#about to write, iclass 15, count 0 2006.201.15:14:29.20#ibcon#wrote, iclass 15, count 0 2006.201.15:14:29.20#ibcon#about to read 3, iclass 15, count 0 2006.201.15:14:29.24#ibcon#read 3, iclass 15, count 0 2006.201.15:14:29.24#ibcon#about to read 4, iclass 15, count 0 2006.201.15:14:29.24#ibcon#read 4, iclass 15, count 0 2006.201.15:14:29.24#ibcon#about to read 5, iclass 15, count 0 2006.201.15:14:29.24#ibcon#read 5, iclass 15, count 0 2006.201.15:14:29.24#ibcon#about to read 6, iclass 15, count 0 2006.201.15:14:29.24#ibcon#read 6, iclass 15, count 0 2006.201.15:14:29.24#ibcon#end of sib2, iclass 15, count 0 2006.201.15:14:29.24#ibcon#*after write, iclass 15, count 0 2006.201.15:14:29.24#ibcon#*before return 0, iclass 15, count 0 2006.201.15:14:29.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:29.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:29.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.15:14:29.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.15:14:29.24$vck44/va=2,7 2006.201.15:14:29.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.15:14:29.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.15:14:29.24#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:29.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:29.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:29.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:29.30#ibcon#enter wrdev, iclass 17, count 2 2006.201.15:14:29.30#ibcon#first serial, iclass 17, count 2 2006.201.15:14:29.30#ibcon#enter sib2, iclass 17, count 2 2006.201.15:14:29.30#ibcon#flushed, iclass 17, count 2 2006.201.15:14:29.30#ibcon#about to write, iclass 17, count 2 2006.201.15:14:29.30#ibcon#wrote, iclass 17, count 2 2006.201.15:14:29.30#ibcon#about to read 3, iclass 17, count 2 2006.201.15:14:29.32#ibcon#read 3, iclass 17, count 2 2006.201.15:14:29.32#ibcon#about to read 4, iclass 17, count 2 2006.201.15:14:29.32#ibcon#read 4, iclass 17, count 2 2006.201.15:14:29.32#ibcon#about to read 5, iclass 17, count 2 2006.201.15:14:29.32#ibcon#read 5, iclass 17, count 2 2006.201.15:14:29.32#ibcon#about to read 6, iclass 17, count 2 2006.201.15:14:29.32#ibcon#read 6, iclass 17, count 2 2006.201.15:14:29.32#ibcon#end of sib2, iclass 17, count 2 2006.201.15:14:29.32#ibcon#*mode == 0, iclass 17, count 2 2006.201.15:14:29.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.15:14:29.32#ibcon#[25=AT02-07\r\n] 2006.201.15:14:29.32#ibcon#*before write, iclass 17, count 2 2006.201.15:14:29.32#ibcon#enter sib2, iclass 17, count 2 2006.201.15:14:29.32#ibcon#flushed, iclass 17, count 2 2006.201.15:14:29.32#ibcon#about to write, iclass 17, count 2 2006.201.15:14:29.32#ibcon#wrote, iclass 17, count 2 2006.201.15:14:29.32#ibcon#about to read 3, iclass 17, count 2 2006.201.15:14:29.35#ibcon#read 3, iclass 17, count 2 2006.201.15:14:29.35#ibcon#about to read 4, iclass 17, count 2 2006.201.15:14:29.35#ibcon#read 4, iclass 17, count 2 2006.201.15:14:29.35#ibcon#about to read 5, iclass 17, count 2 2006.201.15:14:29.35#ibcon#read 5, iclass 17, count 2 2006.201.15:14:29.35#ibcon#about to read 6, iclass 17, count 2 2006.201.15:14:29.35#ibcon#read 6, iclass 17, count 2 2006.201.15:14:29.35#ibcon#end of sib2, iclass 17, count 2 2006.201.15:14:29.35#ibcon#*after write, iclass 17, count 2 2006.201.15:14:29.35#ibcon#*before return 0, iclass 17, count 2 2006.201.15:14:29.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:29.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:29.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.15:14:29.35#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:29.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:29.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:29.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:29.47#ibcon#enter wrdev, iclass 17, count 0 2006.201.15:14:29.47#ibcon#first serial, iclass 17, count 0 2006.201.15:14:29.47#ibcon#enter sib2, iclass 17, count 0 2006.201.15:14:29.47#ibcon#flushed, iclass 17, count 0 2006.201.15:14:29.47#ibcon#about to write, iclass 17, count 0 2006.201.15:14:29.47#ibcon#wrote, iclass 17, count 0 2006.201.15:14:29.47#ibcon#about to read 3, iclass 17, count 0 2006.201.15:14:29.49#ibcon#read 3, iclass 17, count 0 2006.201.15:14:29.49#ibcon#about to read 4, iclass 17, count 0 2006.201.15:14:29.49#ibcon#read 4, iclass 17, count 0 2006.201.15:14:29.49#ibcon#about to read 5, iclass 17, count 0 2006.201.15:14:29.49#ibcon#read 5, iclass 17, count 0 2006.201.15:14:29.49#ibcon#about to read 6, iclass 17, count 0 2006.201.15:14:29.49#ibcon#read 6, iclass 17, count 0 2006.201.15:14:29.49#ibcon#end of sib2, iclass 17, count 0 2006.201.15:14:29.49#ibcon#*mode == 0, iclass 17, count 0 2006.201.15:14:29.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.15:14:29.49#ibcon#[25=USB\r\n] 2006.201.15:14:29.49#ibcon#*before write, iclass 17, count 0 2006.201.15:14:29.49#ibcon#enter sib2, iclass 17, count 0 2006.201.15:14:29.49#ibcon#flushed, iclass 17, count 0 2006.201.15:14:29.49#ibcon#about to write, iclass 17, count 0 2006.201.15:14:29.49#ibcon#wrote, iclass 17, count 0 2006.201.15:14:29.49#ibcon#about to read 3, iclass 17, count 0 2006.201.15:14:29.52#ibcon#read 3, iclass 17, count 0 2006.201.15:14:29.52#ibcon#about to read 4, iclass 17, count 0 2006.201.15:14:29.52#ibcon#read 4, iclass 17, count 0 2006.201.15:14:29.52#ibcon#about to read 5, iclass 17, count 0 2006.201.15:14:29.52#ibcon#read 5, iclass 17, count 0 2006.201.15:14:29.52#ibcon#about to read 6, iclass 17, count 0 2006.201.15:14:29.52#ibcon#read 6, iclass 17, count 0 2006.201.15:14:29.52#ibcon#end of sib2, iclass 17, count 0 2006.201.15:14:29.52#ibcon#*after write, iclass 17, count 0 2006.201.15:14:29.52#ibcon#*before return 0, iclass 17, count 0 2006.201.15:14:29.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:29.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:29.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.15:14:29.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.15:14:29.52$vck44/valo=3,564.99 2006.201.15:14:29.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.15:14:29.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.15:14:29.52#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:29.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:29.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:29.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:29.52#ibcon#enter wrdev, iclass 19, count 0 2006.201.15:14:29.52#ibcon#first serial, iclass 19, count 0 2006.201.15:14:29.52#ibcon#enter sib2, iclass 19, count 0 2006.201.15:14:29.52#ibcon#flushed, iclass 19, count 0 2006.201.15:14:29.52#ibcon#about to write, iclass 19, count 0 2006.201.15:14:29.52#ibcon#wrote, iclass 19, count 0 2006.201.15:14:29.52#ibcon#about to read 3, iclass 19, count 0 2006.201.15:14:29.54#ibcon#read 3, iclass 19, count 0 2006.201.15:14:29.54#ibcon#about to read 4, iclass 19, count 0 2006.201.15:14:29.54#ibcon#read 4, iclass 19, count 0 2006.201.15:14:29.54#ibcon#about to read 5, iclass 19, count 0 2006.201.15:14:29.54#ibcon#read 5, iclass 19, count 0 2006.201.15:14:29.54#ibcon#about to read 6, iclass 19, count 0 2006.201.15:14:29.54#ibcon#read 6, iclass 19, count 0 2006.201.15:14:29.54#ibcon#end of sib2, iclass 19, count 0 2006.201.15:14:29.54#ibcon#*mode == 0, iclass 19, count 0 2006.201.15:14:29.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.15:14:29.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:14:29.54#ibcon#*before write, iclass 19, count 0 2006.201.15:14:29.54#ibcon#enter sib2, iclass 19, count 0 2006.201.15:14:29.54#ibcon#flushed, iclass 19, count 0 2006.201.15:14:29.54#ibcon#about to write, iclass 19, count 0 2006.201.15:14:29.54#ibcon#wrote, iclass 19, count 0 2006.201.15:14:29.54#ibcon#about to read 3, iclass 19, count 0 2006.201.15:14:29.58#ibcon#read 3, iclass 19, count 0 2006.201.15:14:29.58#ibcon#about to read 4, iclass 19, count 0 2006.201.15:14:29.58#ibcon#read 4, iclass 19, count 0 2006.201.15:14:29.58#ibcon#about to read 5, iclass 19, count 0 2006.201.15:14:29.58#ibcon#read 5, iclass 19, count 0 2006.201.15:14:29.58#ibcon#about to read 6, iclass 19, count 0 2006.201.15:14:29.58#ibcon#read 6, iclass 19, count 0 2006.201.15:14:29.58#ibcon#end of sib2, iclass 19, count 0 2006.201.15:14:29.58#ibcon#*after write, iclass 19, count 0 2006.201.15:14:29.58#ibcon#*before return 0, iclass 19, count 0 2006.201.15:14:29.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:29.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:29.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.15:14:29.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.15:14:29.58$vck44/va=3,8 2006.201.15:14:29.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.15:14:29.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.15:14:29.58#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:29.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:29.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:29.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:29.64#ibcon#enter wrdev, iclass 21, count 2 2006.201.15:14:29.64#ibcon#first serial, iclass 21, count 2 2006.201.15:14:29.64#ibcon#enter sib2, iclass 21, count 2 2006.201.15:14:29.64#ibcon#flushed, iclass 21, count 2 2006.201.15:14:29.64#ibcon#about to write, iclass 21, count 2 2006.201.15:14:29.64#ibcon#wrote, iclass 21, count 2 2006.201.15:14:29.64#ibcon#about to read 3, iclass 21, count 2 2006.201.15:14:29.66#ibcon#read 3, iclass 21, count 2 2006.201.15:14:29.66#ibcon#about to read 4, iclass 21, count 2 2006.201.15:14:29.66#ibcon#read 4, iclass 21, count 2 2006.201.15:14:29.66#ibcon#about to read 5, iclass 21, count 2 2006.201.15:14:29.66#ibcon#read 5, iclass 21, count 2 2006.201.15:14:29.66#ibcon#about to read 6, iclass 21, count 2 2006.201.15:14:29.66#ibcon#read 6, iclass 21, count 2 2006.201.15:14:29.66#ibcon#end of sib2, iclass 21, count 2 2006.201.15:14:29.66#ibcon#*mode == 0, iclass 21, count 2 2006.201.15:14:29.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.15:14:29.66#ibcon#[25=AT03-08\r\n] 2006.201.15:14:29.66#ibcon#*before write, iclass 21, count 2 2006.201.15:14:29.66#ibcon#enter sib2, iclass 21, count 2 2006.201.15:14:29.66#ibcon#flushed, iclass 21, count 2 2006.201.15:14:29.66#ibcon#about to write, iclass 21, count 2 2006.201.15:14:29.66#ibcon#wrote, iclass 21, count 2 2006.201.15:14:29.66#ibcon#about to read 3, iclass 21, count 2 2006.201.15:14:29.69#ibcon#read 3, iclass 21, count 2 2006.201.15:14:29.69#ibcon#about to read 4, iclass 21, count 2 2006.201.15:14:29.69#ibcon#read 4, iclass 21, count 2 2006.201.15:14:29.69#ibcon#about to read 5, iclass 21, count 2 2006.201.15:14:29.69#ibcon#read 5, iclass 21, count 2 2006.201.15:14:29.69#ibcon#about to read 6, iclass 21, count 2 2006.201.15:14:29.69#ibcon#read 6, iclass 21, count 2 2006.201.15:14:29.69#ibcon#end of sib2, iclass 21, count 2 2006.201.15:14:29.69#ibcon#*after write, iclass 21, count 2 2006.201.15:14:29.69#ibcon#*before return 0, iclass 21, count 2 2006.201.15:14:29.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:29.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:29.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.15:14:29.69#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:29.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:29.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:29.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:29.81#ibcon#enter wrdev, iclass 21, count 0 2006.201.15:14:29.81#ibcon#first serial, iclass 21, count 0 2006.201.15:14:29.81#ibcon#enter sib2, iclass 21, count 0 2006.201.15:14:29.81#ibcon#flushed, iclass 21, count 0 2006.201.15:14:29.81#ibcon#about to write, iclass 21, count 0 2006.201.15:14:29.81#ibcon#wrote, iclass 21, count 0 2006.201.15:14:29.81#ibcon#about to read 3, iclass 21, count 0 2006.201.15:14:29.83#ibcon#read 3, iclass 21, count 0 2006.201.15:14:29.83#ibcon#about to read 4, iclass 21, count 0 2006.201.15:14:29.83#ibcon#read 4, iclass 21, count 0 2006.201.15:14:29.83#ibcon#about to read 5, iclass 21, count 0 2006.201.15:14:29.83#ibcon#read 5, iclass 21, count 0 2006.201.15:14:29.83#ibcon#about to read 6, iclass 21, count 0 2006.201.15:14:29.83#ibcon#read 6, iclass 21, count 0 2006.201.15:14:29.83#ibcon#end of sib2, iclass 21, count 0 2006.201.15:14:29.83#ibcon#*mode == 0, iclass 21, count 0 2006.201.15:14:29.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.15:14:29.83#ibcon#[25=USB\r\n] 2006.201.15:14:29.83#ibcon#*before write, iclass 21, count 0 2006.201.15:14:29.83#ibcon#enter sib2, iclass 21, count 0 2006.201.15:14:29.83#ibcon#flushed, iclass 21, count 0 2006.201.15:14:29.83#ibcon#about to write, iclass 21, count 0 2006.201.15:14:29.83#ibcon#wrote, iclass 21, count 0 2006.201.15:14:29.83#ibcon#about to read 3, iclass 21, count 0 2006.201.15:14:29.86#ibcon#read 3, iclass 21, count 0 2006.201.15:14:29.86#ibcon#about to read 4, iclass 21, count 0 2006.201.15:14:29.86#ibcon#read 4, iclass 21, count 0 2006.201.15:14:29.86#ibcon#about to read 5, iclass 21, count 0 2006.201.15:14:29.86#ibcon#read 5, iclass 21, count 0 2006.201.15:14:29.86#ibcon#about to read 6, iclass 21, count 0 2006.201.15:14:29.86#ibcon#read 6, iclass 21, count 0 2006.201.15:14:29.86#ibcon#end of sib2, iclass 21, count 0 2006.201.15:14:29.86#ibcon#*after write, iclass 21, count 0 2006.201.15:14:29.86#ibcon#*before return 0, iclass 21, count 0 2006.201.15:14:29.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:29.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:29.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.15:14:29.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.15:14:29.86$vck44/valo=4,624.99 2006.201.15:14:29.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.15:14:29.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.15:14:29.86#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:29.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:29.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:29.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:29.86#ibcon#enter wrdev, iclass 23, count 0 2006.201.15:14:29.86#ibcon#first serial, iclass 23, count 0 2006.201.15:14:29.86#ibcon#enter sib2, iclass 23, count 0 2006.201.15:14:29.86#ibcon#flushed, iclass 23, count 0 2006.201.15:14:29.86#ibcon#about to write, iclass 23, count 0 2006.201.15:14:29.86#ibcon#wrote, iclass 23, count 0 2006.201.15:14:29.86#ibcon#about to read 3, iclass 23, count 0 2006.201.15:14:29.88#ibcon#read 3, iclass 23, count 0 2006.201.15:14:29.88#ibcon#about to read 4, iclass 23, count 0 2006.201.15:14:29.88#ibcon#read 4, iclass 23, count 0 2006.201.15:14:29.88#ibcon#about to read 5, iclass 23, count 0 2006.201.15:14:29.88#ibcon#read 5, iclass 23, count 0 2006.201.15:14:29.88#ibcon#about to read 6, iclass 23, count 0 2006.201.15:14:29.88#ibcon#read 6, iclass 23, count 0 2006.201.15:14:29.88#ibcon#end of sib2, iclass 23, count 0 2006.201.15:14:29.88#ibcon#*mode == 0, iclass 23, count 0 2006.201.15:14:29.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.15:14:29.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:14:29.88#ibcon#*before write, iclass 23, count 0 2006.201.15:14:29.88#ibcon#enter sib2, iclass 23, count 0 2006.201.15:14:29.88#ibcon#flushed, iclass 23, count 0 2006.201.15:14:29.88#ibcon#about to write, iclass 23, count 0 2006.201.15:14:29.88#ibcon#wrote, iclass 23, count 0 2006.201.15:14:29.88#ibcon#about to read 3, iclass 23, count 0 2006.201.15:14:29.93#ibcon#read 3, iclass 23, count 0 2006.201.15:14:29.93#ibcon#about to read 4, iclass 23, count 0 2006.201.15:14:29.93#ibcon#read 4, iclass 23, count 0 2006.201.15:14:29.93#ibcon#about to read 5, iclass 23, count 0 2006.201.15:14:29.93#ibcon#read 5, iclass 23, count 0 2006.201.15:14:29.93#ibcon#about to read 6, iclass 23, count 0 2006.201.15:14:29.93#ibcon#read 6, iclass 23, count 0 2006.201.15:14:29.93#ibcon#end of sib2, iclass 23, count 0 2006.201.15:14:29.93#ibcon#*after write, iclass 23, count 0 2006.201.15:14:29.93#ibcon#*before return 0, iclass 23, count 0 2006.201.15:14:29.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:29.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:29.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.15:14:29.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.15:14:29.93$vck44/va=4,7 2006.201.15:14:29.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.15:14:29.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.15:14:29.93#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:29.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:29.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:29.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:29.98#ibcon#enter wrdev, iclass 25, count 2 2006.201.15:14:29.98#ibcon#first serial, iclass 25, count 2 2006.201.15:14:29.98#ibcon#enter sib2, iclass 25, count 2 2006.201.15:14:29.98#ibcon#flushed, iclass 25, count 2 2006.201.15:14:29.98#ibcon#about to write, iclass 25, count 2 2006.201.15:14:29.98#ibcon#wrote, iclass 25, count 2 2006.201.15:14:29.98#ibcon#about to read 3, iclass 25, count 2 2006.201.15:14:30.00#ibcon#read 3, iclass 25, count 2 2006.201.15:14:30.00#ibcon#about to read 4, iclass 25, count 2 2006.201.15:14:30.00#ibcon#read 4, iclass 25, count 2 2006.201.15:14:30.00#ibcon#about to read 5, iclass 25, count 2 2006.201.15:14:30.00#ibcon#read 5, iclass 25, count 2 2006.201.15:14:30.00#ibcon#about to read 6, iclass 25, count 2 2006.201.15:14:30.00#ibcon#read 6, iclass 25, count 2 2006.201.15:14:30.00#ibcon#end of sib2, iclass 25, count 2 2006.201.15:14:30.00#ibcon#*mode == 0, iclass 25, count 2 2006.201.15:14:30.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.15:14:30.00#ibcon#[25=AT04-07\r\n] 2006.201.15:14:30.00#ibcon#*before write, iclass 25, count 2 2006.201.15:14:30.00#ibcon#enter sib2, iclass 25, count 2 2006.201.15:14:30.00#ibcon#flushed, iclass 25, count 2 2006.201.15:14:30.00#ibcon#about to write, iclass 25, count 2 2006.201.15:14:30.00#ibcon#wrote, iclass 25, count 2 2006.201.15:14:30.00#ibcon#about to read 3, iclass 25, count 2 2006.201.15:14:30.03#ibcon#read 3, iclass 25, count 2 2006.201.15:14:30.03#ibcon#about to read 4, iclass 25, count 2 2006.201.15:14:30.03#ibcon#read 4, iclass 25, count 2 2006.201.15:14:30.03#ibcon#about to read 5, iclass 25, count 2 2006.201.15:14:30.03#ibcon#read 5, iclass 25, count 2 2006.201.15:14:30.03#ibcon#about to read 6, iclass 25, count 2 2006.201.15:14:30.03#ibcon#read 6, iclass 25, count 2 2006.201.15:14:30.03#ibcon#end of sib2, iclass 25, count 2 2006.201.15:14:30.03#ibcon#*after write, iclass 25, count 2 2006.201.15:14:30.03#ibcon#*before return 0, iclass 25, count 2 2006.201.15:14:30.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:30.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:30.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.15:14:30.03#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:30.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:30.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:30.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:30.15#ibcon#enter wrdev, iclass 25, count 0 2006.201.15:14:30.15#ibcon#first serial, iclass 25, count 0 2006.201.15:14:30.15#ibcon#enter sib2, iclass 25, count 0 2006.201.15:14:30.15#ibcon#flushed, iclass 25, count 0 2006.201.15:14:30.15#ibcon#about to write, iclass 25, count 0 2006.201.15:14:30.15#ibcon#wrote, iclass 25, count 0 2006.201.15:14:30.15#ibcon#about to read 3, iclass 25, count 0 2006.201.15:14:30.17#ibcon#read 3, iclass 25, count 0 2006.201.15:14:30.17#ibcon#about to read 4, iclass 25, count 0 2006.201.15:14:30.17#ibcon#read 4, iclass 25, count 0 2006.201.15:14:30.17#ibcon#about to read 5, iclass 25, count 0 2006.201.15:14:30.17#ibcon#read 5, iclass 25, count 0 2006.201.15:14:30.17#ibcon#about to read 6, iclass 25, count 0 2006.201.15:14:30.17#ibcon#read 6, iclass 25, count 0 2006.201.15:14:30.17#ibcon#end of sib2, iclass 25, count 0 2006.201.15:14:30.17#ibcon#*mode == 0, iclass 25, count 0 2006.201.15:14:30.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.15:14:30.17#ibcon#[25=USB\r\n] 2006.201.15:14:30.17#ibcon#*before write, iclass 25, count 0 2006.201.15:14:30.17#ibcon#enter sib2, iclass 25, count 0 2006.201.15:14:30.17#ibcon#flushed, iclass 25, count 0 2006.201.15:14:30.17#ibcon#about to write, iclass 25, count 0 2006.201.15:14:30.17#ibcon#wrote, iclass 25, count 0 2006.201.15:14:30.17#ibcon#about to read 3, iclass 25, count 0 2006.201.15:14:30.20#ibcon#read 3, iclass 25, count 0 2006.201.15:14:30.20#ibcon#about to read 4, iclass 25, count 0 2006.201.15:14:30.20#ibcon#read 4, iclass 25, count 0 2006.201.15:14:30.20#ibcon#about to read 5, iclass 25, count 0 2006.201.15:14:30.20#ibcon#read 5, iclass 25, count 0 2006.201.15:14:30.20#ibcon#about to read 6, iclass 25, count 0 2006.201.15:14:30.20#ibcon#read 6, iclass 25, count 0 2006.201.15:14:30.20#ibcon#end of sib2, iclass 25, count 0 2006.201.15:14:30.20#ibcon#*after write, iclass 25, count 0 2006.201.15:14:30.20#ibcon#*before return 0, iclass 25, count 0 2006.201.15:14:30.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:30.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:30.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.15:14:30.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.15:14:30.20$vck44/valo=5,734.99 2006.201.15:14:30.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.15:14:30.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.15:14:30.20#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:30.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:30.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:30.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:30.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.15:14:30.20#ibcon#first serial, iclass 27, count 0 2006.201.15:14:30.20#ibcon#enter sib2, iclass 27, count 0 2006.201.15:14:30.20#ibcon#flushed, iclass 27, count 0 2006.201.15:14:30.20#ibcon#about to write, iclass 27, count 0 2006.201.15:14:30.20#ibcon#wrote, iclass 27, count 0 2006.201.15:14:30.20#ibcon#about to read 3, iclass 27, count 0 2006.201.15:14:30.22#ibcon#read 3, iclass 27, count 0 2006.201.15:14:30.22#ibcon#about to read 4, iclass 27, count 0 2006.201.15:14:30.22#ibcon#read 4, iclass 27, count 0 2006.201.15:14:30.22#ibcon#about to read 5, iclass 27, count 0 2006.201.15:14:30.22#ibcon#read 5, iclass 27, count 0 2006.201.15:14:30.22#ibcon#about to read 6, iclass 27, count 0 2006.201.15:14:30.22#ibcon#read 6, iclass 27, count 0 2006.201.15:14:30.22#ibcon#end of sib2, iclass 27, count 0 2006.201.15:14:30.22#ibcon#*mode == 0, iclass 27, count 0 2006.201.15:14:30.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.15:14:30.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:14:30.22#ibcon#*before write, iclass 27, count 0 2006.201.15:14:30.22#ibcon#enter sib2, iclass 27, count 0 2006.201.15:14:30.22#ibcon#flushed, iclass 27, count 0 2006.201.15:14:30.22#ibcon#about to write, iclass 27, count 0 2006.201.15:14:30.22#ibcon#wrote, iclass 27, count 0 2006.201.15:14:30.22#ibcon#about to read 3, iclass 27, count 0 2006.201.15:14:30.26#ibcon#read 3, iclass 27, count 0 2006.201.15:14:30.26#ibcon#about to read 4, iclass 27, count 0 2006.201.15:14:30.26#ibcon#read 4, iclass 27, count 0 2006.201.15:14:30.26#ibcon#about to read 5, iclass 27, count 0 2006.201.15:14:30.26#ibcon#read 5, iclass 27, count 0 2006.201.15:14:30.26#ibcon#about to read 6, iclass 27, count 0 2006.201.15:14:30.26#ibcon#read 6, iclass 27, count 0 2006.201.15:14:30.26#ibcon#end of sib2, iclass 27, count 0 2006.201.15:14:30.26#ibcon#*after write, iclass 27, count 0 2006.201.15:14:30.26#ibcon#*before return 0, iclass 27, count 0 2006.201.15:14:30.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:30.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:30.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.15:14:30.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.15:14:30.26$vck44/va=5,4 2006.201.15:14:30.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.15:14:30.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.15:14:30.26#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:30.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:30.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:30.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:30.32#ibcon#enter wrdev, iclass 29, count 2 2006.201.15:14:30.32#ibcon#first serial, iclass 29, count 2 2006.201.15:14:30.32#ibcon#enter sib2, iclass 29, count 2 2006.201.15:14:30.32#ibcon#flushed, iclass 29, count 2 2006.201.15:14:30.32#ibcon#about to write, iclass 29, count 2 2006.201.15:14:30.32#ibcon#wrote, iclass 29, count 2 2006.201.15:14:30.32#ibcon#about to read 3, iclass 29, count 2 2006.201.15:14:30.34#ibcon#read 3, iclass 29, count 2 2006.201.15:14:30.34#ibcon#about to read 4, iclass 29, count 2 2006.201.15:14:30.34#ibcon#read 4, iclass 29, count 2 2006.201.15:14:30.34#ibcon#about to read 5, iclass 29, count 2 2006.201.15:14:30.34#ibcon#read 5, iclass 29, count 2 2006.201.15:14:30.34#ibcon#about to read 6, iclass 29, count 2 2006.201.15:14:30.34#ibcon#read 6, iclass 29, count 2 2006.201.15:14:30.34#ibcon#end of sib2, iclass 29, count 2 2006.201.15:14:30.34#ibcon#*mode == 0, iclass 29, count 2 2006.201.15:14:30.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.15:14:30.34#ibcon#[25=AT05-04\r\n] 2006.201.15:14:30.34#ibcon#*before write, iclass 29, count 2 2006.201.15:14:30.34#ibcon#enter sib2, iclass 29, count 2 2006.201.15:14:30.34#ibcon#flushed, iclass 29, count 2 2006.201.15:14:30.34#ibcon#about to write, iclass 29, count 2 2006.201.15:14:30.34#ibcon#wrote, iclass 29, count 2 2006.201.15:14:30.34#ibcon#about to read 3, iclass 29, count 2 2006.201.15:14:30.37#ibcon#read 3, iclass 29, count 2 2006.201.15:14:30.37#ibcon#about to read 4, iclass 29, count 2 2006.201.15:14:30.37#ibcon#read 4, iclass 29, count 2 2006.201.15:14:30.37#ibcon#about to read 5, iclass 29, count 2 2006.201.15:14:30.37#ibcon#read 5, iclass 29, count 2 2006.201.15:14:30.37#ibcon#about to read 6, iclass 29, count 2 2006.201.15:14:30.37#ibcon#read 6, iclass 29, count 2 2006.201.15:14:30.37#ibcon#end of sib2, iclass 29, count 2 2006.201.15:14:30.37#ibcon#*after write, iclass 29, count 2 2006.201.15:14:30.37#ibcon#*before return 0, iclass 29, count 2 2006.201.15:14:30.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:30.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:30.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.15:14:30.37#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:30.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:30.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:30.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:30.49#ibcon#enter wrdev, iclass 29, count 0 2006.201.15:14:30.49#ibcon#first serial, iclass 29, count 0 2006.201.15:14:30.49#ibcon#enter sib2, iclass 29, count 0 2006.201.15:14:30.49#ibcon#flushed, iclass 29, count 0 2006.201.15:14:30.49#ibcon#about to write, iclass 29, count 0 2006.201.15:14:30.49#ibcon#wrote, iclass 29, count 0 2006.201.15:14:30.49#ibcon#about to read 3, iclass 29, count 0 2006.201.15:14:30.51#ibcon#read 3, iclass 29, count 0 2006.201.15:14:30.51#ibcon#about to read 4, iclass 29, count 0 2006.201.15:14:30.51#ibcon#read 4, iclass 29, count 0 2006.201.15:14:30.51#ibcon#about to read 5, iclass 29, count 0 2006.201.15:14:30.51#ibcon#read 5, iclass 29, count 0 2006.201.15:14:30.51#ibcon#about to read 6, iclass 29, count 0 2006.201.15:14:30.51#ibcon#read 6, iclass 29, count 0 2006.201.15:14:30.51#ibcon#end of sib2, iclass 29, count 0 2006.201.15:14:30.51#ibcon#*mode == 0, iclass 29, count 0 2006.201.15:14:30.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.15:14:30.51#ibcon#[25=USB\r\n] 2006.201.15:14:30.51#ibcon#*before write, iclass 29, count 0 2006.201.15:14:30.51#ibcon#enter sib2, iclass 29, count 0 2006.201.15:14:30.51#ibcon#flushed, iclass 29, count 0 2006.201.15:14:30.51#ibcon#about to write, iclass 29, count 0 2006.201.15:14:30.51#ibcon#wrote, iclass 29, count 0 2006.201.15:14:30.51#ibcon#about to read 3, iclass 29, count 0 2006.201.15:14:30.54#ibcon#read 3, iclass 29, count 0 2006.201.15:14:30.54#ibcon#about to read 4, iclass 29, count 0 2006.201.15:14:30.54#ibcon#read 4, iclass 29, count 0 2006.201.15:14:30.54#ibcon#about to read 5, iclass 29, count 0 2006.201.15:14:30.54#ibcon#read 5, iclass 29, count 0 2006.201.15:14:30.54#ibcon#about to read 6, iclass 29, count 0 2006.201.15:14:30.54#ibcon#read 6, iclass 29, count 0 2006.201.15:14:30.54#ibcon#end of sib2, iclass 29, count 0 2006.201.15:14:30.54#ibcon#*after write, iclass 29, count 0 2006.201.15:14:30.54#ibcon#*before return 0, iclass 29, count 0 2006.201.15:14:30.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:30.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:30.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.15:14:30.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.15:14:30.54$vck44/valo=6,814.99 2006.201.15:14:30.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.15:14:30.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.15:14:30.54#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:30.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:30.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:30.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:30.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.15:14:30.54#ibcon#first serial, iclass 31, count 0 2006.201.15:14:30.54#ibcon#enter sib2, iclass 31, count 0 2006.201.15:14:30.54#ibcon#flushed, iclass 31, count 0 2006.201.15:14:30.54#ibcon#about to write, iclass 31, count 0 2006.201.15:14:30.54#ibcon#wrote, iclass 31, count 0 2006.201.15:14:30.54#ibcon#about to read 3, iclass 31, count 0 2006.201.15:14:30.56#ibcon#read 3, iclass 31, count 0 2006.201.15:14:30.56#ibcon#about to read 4, iclass 31, count 0 2006.201.15:14:30.56#ibcon#read 4, iclass 31, count 0 2006.201.15:14:30.56#ibcon#about to read 5, iclass 31, count 0 2006.201.15:14:30.56#ibcon#read 5, iclass 31, count 0 2006.201.15:14:30.56#ibcon#about to read 6, iclass 31, count 0 2006.201.15:14:30.56#ibcon#read 6, iclass 31, count 0 2006.201.15:14:30.56#ibcon#end of sib2, iclass 31, count 0 2006.201.15:14:30.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.15:14:30.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.15:14:30.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:14:30.56#ibcon#*before write, iclass 31, count 0 2006.201.15:14:30.56#ibcon#enter sib2, iclass 31, count 0 2006.201.15:14:30.56#ibcon#flushed, iclass 31, count 0 2006.201.15:14:30.56#ibcon#about to write, iclass 31, count 0 2006.201.15:14:30.56#ibcon#wrote, iclass 31, count 0 2006.201.15:14:30.56#ibcon#about to read 3, iclass 31, count 0 2006.201.15:14:30.60#ibcon#read 3, iclass 31, count 0 2006.201.15:14:30.60#ibcon#about to read 4, iclass 31, count 0 2006.201.15:14:30.60#ibcon#read 4, iclass 31, count 0 2006.201.15:14:30.60#ibcon#about to read 5, iclass 31, count 0 2006.201.15:14:30.60#ibcon#read 5, iclass 31, count 0 2006.201.15:14:30.60#ibcon#about to read 6, iclass 31, count 0 2006.201.15:14:30.60#ibcon#read 6, iclass 31, count 0 2006.201.15:14:30.60#ibcon#end of sib2, iclass 31, count 0 2006.201.15:14:30.60#ibcon#*after write, iclass 31, count 0 2006.201.15:14:30.60#ibcon#*before return 0, iclass 31, count 0 2006.201.15:14:30.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:30.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:30.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.15:14:30.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.15:14:30.60$vck44/va=6,5 2006.201.15:14:30.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.15:14:30.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.15:14:30.60#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:30.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:30.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:30.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:30.66#ibcon#enter wrdev, iclass 33, count 2 2006.201.15:14:30.66#ibcon#first serial, iclass 33, count 2 2006.201.15:14:30.66#ibcon#enter sib2, iclass 33, count 2 2006.201.15:14:30.66#ibcon#flushed, iclass 33, count 2 2006.201.15:14:30.66#ibcon#about to write, iclass 33, count 2 2006.201.15:14:30.66#ibcon#wrote, iclass 33, count 2 2006.201.15:14:30.66#ibcon#about to read 3, iclass 33, count 2 2006.201.15:14:30.68#ibcon#read 3, iclass 33, count 2 2006.201.15:14:30.68#ibcon#about to read 4, iclass 33, count 2 2006.201.15:14:30.68#ibcon#read 4, iclass 33, count 2 2006.201.15:14:30.68#ibcon#about to read 5, iclass 33, count 2 2006.201.15:14:30.68#ibcon#read 5, iclass 33, count 2 2006.201.15:14:30.68#ibcon#about to read 6, iclass 33, count 2 2006.201.15:14:30.68#ibcon#read 6, iclass 33, count 2 2006.201.15:14:30.68#ibcon#end of sib2, iclass 33, count 2 2006.201.15:14:30.68#ibcon#*mode == 0, iclass 33, count 2 2006.201.15:14:30.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.15:14:30.68#ibcon#[25=AT06-05\r\n] 2006.201.15:14:30.68#ibcon#*before write, iclass 33, count 2 2006.201.15:14:30.68#ibcon#enter sib2, iclass 33, count 2 2006.201.15:14:30.68#ibcon#flushed, iclass 33, count 2 2006.201.15:14:30.68#ibcon#about to write, iclass 33, count 2 2006.201.15:14:30.68#ibcon#wrote, iclass 33, count 2 2006.201.15:14:30.68#ibcon#about to read 3, iclass 33, count 2 2006.201.15:14:30.71#ibcon#read 3, iclass 33, count 2 2006.201.15:14:30.71#ibcon#about to read 4, iclass 33, count 2 2006.201.15:14:30.71#ibcon#read 4, iclass 33, count 2 2006.201.15:14:30.71#ibcon#about to read 5, iclass 33, count 2 2006.201.15:14:30.71#ibcon#read 5, iclass 33, count 2 2006.201.15:14:30.71#ibcon#about to read 6, iclass 33, count 2 2006.201.15:14:30.71#ibcon#read 6, iclass 33, count 2 2006.201.15:14:30.71#ibcon#end of sib2, iclass 33, count 2 2006.201.15:14:30.71#ibcon#*after write, iclass 33, count 2 2006.201.15:14:30.71#ibcon#*before return 0, iclass 33, count 2 2006.201.15:14:30.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:30.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:30.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.15:14:30.71#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:30.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:30.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:30.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:30.83#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:14:30.83#ibcon#first serial, iclass 33, count 0 2006.201.15:14:30.83#ibcon#enter sib2, iclass 33, count 0 2006.201.15:14:30.83#ibcon#flushed, iclass 33, count 0 2006.201.15:14:30.83#ibcon#about to write, iclass 33, count 0 2006.201.15:14:30.83#ibcon#wrote, iclass 33, count 0 2006.201.15:14:30.83#ibcon#about to read 3, iclass 33, count 0 2006.201.15:14:30.85#ibcon#read 3, iclass 33, count 0 2006.201.15:14:30.85#ibcon#about to read 4, iclass 33, count 0 2006.201.15:14:30.85#ibcon#read 4, iclass 33, count 0 2006.201.15:14:30.85#ibcon#about to read 5, iclass 33, count 0 2006.201.15:14:30.85#ibcon#read 5, iclass 33, count 0 2006.201.15:14:30.85#ibcon#about to read 6, iclass 33, count 0 2006.201.15:14:30.85#ibcon#read 6, iclass 33, count 0 2006.201.15:14:30.85#ibcon#end of sib2, iclass 33, count 0 2006.201.15:14:30.85#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:14:30.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:14:30.85#ibcon#[25=USB\r\n] 2006.201.15:14:30.85#ibcon#*before write, iclass 33, count 0 2006.201.15:14:30.85#ibcon#enter sib2, iclass 33, count 0 2006.201.15:14:30.85#ibcon#flushed, iclass 33, count 0 2006.201.15:14:30.85#ibcon#about to write, iclass 33, count 0 2006.201.15:14:30.85#ibcon#wrote, iclass 33, count 0 2006.201.15:14:30.85#ibcon#about to read 3, iclass 33, count 0 2006.201.15:14:30.88#ibcon#read 3, iclass 33, count 0 2006.201.15:14:30.88#ibcon#about to read 4, iclass 33, count 0 2006.201.15:14:30.88#ibcon#read 4, iclass 33, count 0 2006.201.15:14:30.88#ibcon#about to read 5, iclass 33, count 0 2006.201.15:14:30.88#ibcon#read 5, iclass 33, count 0 2006.201.15:14:30.88#ibcon#about to read 6, iclass 33, count 0 2006.201.15:14:30.88#ibcon#read 6, iclass 33, count 0 2006.201.15:14:30.88#ibcon#end of sib2, iclass 33, count 0 2006.201.15:14:30.88#ibcon#*after write, iclass 33, count 0 2006.201.15:14:30.88#ibcon#*before return 0, iclass 33, count 0 2006.201.15:14:30.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:30.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:30.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:14:30.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:14:30.88$vck44/valo=7,864.99 2006.201.15:14:30.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.15:14:30.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.15:14:30.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:30.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:30.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:30.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:30.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.15:14:30.88#ibcon#first serial, iclass 35, count 0 2006.201.15:14:30.88#ibcon#enter sib2, iclass 35, count 0 2006.201.15:14:30.88#ibcon#flushed, iclass 35, count 0 2006.201.15:14:30.88#ibcon#about to write, iclass 35, count 0 2006.201.15:14:30.88#ibcon#wrote, iclass 35, count 0 2006.201.15:14:30.88#ibcon#about to read 3, iclass 35, count 0 2006.201.15:14:30.90#ibcon#read 3, iclass 35, count 0 2006.201.15:14:30.90#ibcon#about to read 4, iclass 35, count 0 2006.201.15:14:30.90#ibcon#read 4, iclass 35, count 0 2006.201.15:14:30.90#ibcon#about to read 5, iclass 35, count 0 2006.201.15:14:30.90#ibcon#read 5, iclass 35, count 0 2006.201.15:14:30.90#ibcon#about to read 6, iclass 35, count 0 2006.201.15:14:30.90#ibcon#read 6, iclass 35, count 0 2006.201.15:14:30.90#ibcon#end of sib2, iclass 35, count 0 2006.201.15:14:30.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.15:14:30.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.15:14:30.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:14:30.90#ibcon#*before write, iclass 35, count 0 2006.201.15:14:30.90#ibcon#enter sib2, iclass 35, count 0 2006.201.15:14:30.90#ibcon#flushed, iclass 35, count 0 2006.201.15:14:30.90#ibcon#about to write, iclass 35, count 0 2006.201.15:14:30.90#ibcon#wrote, iclass 35, count 0 2006.201.15:14:30.90#ibcon#about to read 3, iclass 35, count 0 2006.201.15:14:30.94#ibcon#read 3, iclass 35, count 0 2006.201.15:14:30.94#ibcon#about to read 4, iclass 35, count 0 2006.201.15:14:30.94#ibcon#read 4, iclass 35, count 0 2006.201.15:14:30.94#ibcon#about to read 5, iclass 35, count 0 2006.201.15:14:30.94#ibcon#read 5, iclass 35, count 0 2006.201.15:14:30.94#ibcon#about to read 6, iclass 35, count 0 2006.201.15:14:30.94#ibcon#read 6, iclass 35, count 0 2006.201.15:14:30.94#ibcon#end of sib2, iclass 35, count 0 2006.201.15:14:30.94#ibcon#*after write, iclass 35, count 0 2006.201.15:14:30.94#ibcon#*before return 0, iclass 35, count 0 2006.201.15:14:30.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:30.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:30.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.15:14:30.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.15:14:30.94$vck44/va=7,5 2006.201.15:14:30.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.15:14:30.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.15:14:30.94#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:30.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:31.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:31.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:31.00#ibcon#enter wrdev, iclass 37, count 2 2006.201.15:14:31.00#ibcon#first serial, iclass 37, count 2 2006.201.15:14:31.00#ibcon#enter sib2, iclass 37, count 2 2006.201.15:14:31.00#ibcon#flushed, iclass 37, count 2 2006.201.15:14:31.00#ibcon#about to write, iclass 37, count 2 2006.201.15:14:31.00#ibcon#wrote, iclass 37, count 2 2006.201.15:14:31.00#ibcon#about to read 3, iclass 37, count 2 2006.201.15:14:31.02#ibcon#read 3, iclass 37, count 2 2006.201.15:14:31.02#ibcon#about to read 4, iclass 37, count 2 2006.201.15:14:31.02#ibcon#read 4, iclass 37, count 2 2006.201.15:14:31.02#ibcon#about to read 5, iclass 37, count 2 2006.201.15:14:31.02#ibcon#read 5, iclass 37, count 2 2006.201.15:14:31.02#ibcon#about to read 6, iclass 37, count 2 2006.201.15:14:31.02#ibcon#read 6, iclass 37, count 2 2006.201.15:14:31.02#ibcon#end of sib2, iclass 37, count 2 2006.201.15:14:31.02#ibcon#*mode == 0, iclass 37, count 2 2006.201.15:14:31.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.15:14:31.02#ibcon#[25=AT07-05\r\n] 2006.201.15:14:31.02#ibcon#*before write, iclass 37, count 2 2006.201.15:14:31.02#ibcon#enter sib2, iclass 37, count 2 2006.201.15:14:31.02#ibcon#flushed, iclass 37, count 2 2006.201.15:14:31.02#ibcon#about to write, iclass 37, count 2 2006.201.15:14:31.02#ibcon#wrote, iclass 37, count 2 2006.201.15:14:31.02#ibcon#about to read 3, iclass 37, count 2 2006.201.15:14:31.05#ibcon#read 3, iclass 37, count 2 2006.201.15:14:31.05#ibcon#about to read 4, iclass 37, count 2 2006.201.15:14:31.05#ibcon#read 4, iclass 37, count 2 2006.201.15:14:31.05#ibcon#about to read 5, iclass 37, count 2 2006.201.15:14:31.05#ibcon#read 5, iclass 37, count 2 2006.201.15:14:31.05#ibcon#about to read 6, iclass 37, count 2 2006.201.15:14:31.05#ibcon#read 6, iclass 37, count 2 2006.201.15:14:31.05#ibcon#end of sib2, iclass 37, count 2 2006.201.15:14:31.05#ibcon#*after write, iclass 37, count 2 2006.201.15:14:31.05#ibcon#*before return 0, iclass 37, count 2 2006.201.15:14:31.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:31.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:31.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.15:14:31.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:31.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:31.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:31.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:31.17#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:14:31.17#ibcon#first serial, iclass 37, count 0 2006.201.15:14:31.17#ibcon#enter sib2, iclass 37, count 0 2006.201.15:14:31.17#ibcon#flushed, iclass 37, count 0 2006.201.15:14:31.17#ibcon#about to write, iclass 37, count 0 2006.201.15:14:31.17#ibcon#wrote, iclass 37, count 0 2006.201.15:14:31.17#ibcon#about to read 3, iclass 37, count 0 2006.201.15:14:31.19#ibcon#read 3, iclass 37, count 0 2006.201.15:14:31.19#ibcon#about to read 4, iclass 37, count 0 2006.201.15:14:31.19#ibcon#read 4, iclass 37, count 0 2006.201.15:14:31.19#ibcon#about to read 5, iclass 37, count 0 2006.201.15:14:31.19#ibcon#read 5, iclass 37, count 0 2006.201.15:14:31.19#ibcon#about to read 6, iclass 37, count 0 2006.201.15:14:31.19#ibcon#read 6, iclass 37, count 0 2006.201.15:14:31.19#ibcon#end of sib2, iclass 37, count 0 2006.201.15:14:31.19#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:14:31.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:14:31.19#ibcon#[25=USB\r\n] 2006.201.15:14:31.19#ibcon#*before write, iclass 37, count 0 2006.201.15:14:31.19#ibcon#enter sib2, iclass 37, count 0 2006.201.15:14:31.19#ibcon#flushed, iclass 37, count 0 2006.201.15:14:31.19#ibcon#about to write, iclass 37, count 0 2006.201.15:14:31.19#ibcon#wrote, iclass 37, count 0 2006.201.15:14:31.19#ibcon#about to read 3, iclass 37, count 0 2006.201.15:14:31.22#ibcon#read 3, iclass 37, count 0 2006.201.15:14:31.22#ibcon#about to read 4, iclass 37, count 0 2006.201.15:14:31.22#ibcon#read 4, iclass 37, count 0 2006.201.15:14:31.22#ibcon#about to read 5, iclass 37, count 0 2006.201.15:14:31.22#ibcon#read 5, iclass 37, count 0 2006.201.15:14:31.22#ibcon#about to read 6, iclass 37, count 0 2006.201.15:14:31.22#ibcon#read 6, iclass 37, count 0 2006.201.15:14:31.22#ibcon#end of sib2, iclass 37, count 0 2006.201.15:14:31.22#ibcon#*after write, iclass 37, count 0 2006.201.15:14:31.22#ibcon#*before return 0, iclass 37, count 0 2006.201.15:14:31.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:31.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:31.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:14:31.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:14:31.22$vck44/valo=8,884.99 2006.201.15:14:31.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.15:14:31.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.15:14:31.22#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:31.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:31.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:31.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:31.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.15:14:31.22#ibcon#first serial, iclass 39, count 0 2006.201.15:14:31.22#ibcon#enter sib2, iclass 39, count 0 2006.201.15:14:31.22#ibcon#flushed, iclass 39, count 0 2006.201.15:14:31.22#ibcon#about to write, iclass 39, count 0 2006.201.15:14:31.22#ibcon#wrote, iclass 39, count 0 2006.201.15:14:31.22#ibcon#about to read 3, iclass 39, count 0 2006.201.15:14:31.24#ibcon#read 3, iclass 39, count 0 2006.201.15:14:31.24#ibcon#about to read 4, iclass 39, count 0 2006.201.15:14:31.24#ibcon#read 4, iclass 39, count 0 2006.201.15:14:31.24#ibcon#about to read 5, iclass 39, count 0 2006.201.15:14:31.24#ibcon#read 5, iclass 39, count 0 2006.201.15:14:31.24#ibcon#about to read 6, iclass 39, count 0 2006.201.15:14:31.24#ibcon#read 6, iclass 39, count 0 2006.201.15:14:31.24#ibcon#end of sib2, iclass 39, count 0 2006.201.15:14:31.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.15:14:31.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.15:14:31.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:14:31.24#ibcon#*before write, iclass 39, count 0 2006.201.15:14:31.24#ibcon#enter sib2, iclass 39, count 0 2006.201.15:14:31.24#ibcon#flushed, iclass 39, count 0 2006.201.15:14:31.24#ibcon#about to write, iclass 39, count 0 2006.201.15:14:31.24#ibcon#wrote, iclass 39, count 0 2006.201.15:14:31.24#ibcon#about to read 3, iclass 39, count 0 2006.201.15:14:31.28#ibcon#read 3, iclass 39, count 0 2006.201.15:14:31.28#ibcon#about to read 4, iclass 39, count 0 2006.201.15:14:31.28#ibcon#read 4, iclass 39, count 0 2006.201.15:14:31.28#ibcon#about to read 5, iclass 39, count 0 2006.201.15:14:31.28#ibcon#read 5, iclass 39, count 0 2006.201.15:14:31.28#ibcon#about to read 6, iclass 39, count 0 2006.201.15:14:31.28#ibcon#read 6, iclass 39, count 0 2006.201.15:14:31.28#ibcon#end of sib2, iclass 39, count 0 2006.201.15:14:31.28#ibcon#*after write, iclass 39, count 0 2006.201.15:14:31.28#ibcon#*before return 0, iclass 39, count 0 2006.201.15:14:31.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:31.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:31.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.15:14:31.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.15:14:31.28$vck44/va=8,4 2006.201.15:14:31.28#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.15:14:31.28#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.15:14:31.28#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:31.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.15:14:31.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.15:14:31.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.15:14:31.34#ibcon#enter wrdev, iclass 2, count 2 2006.201.15:14:31.34#ibcon#first serial, iclass 2, count 2 2006.201.15:14:31.34#ibcon#enter sib2, iclass 2, count 2 2006.201.15:14:31.34#ibcon#flushed, iclass 2, count 2 2006.201.15:14:31.34#ibcon#about to write, iclass 2, count 2 2006.201.15:14:31.34#ibcon#wrote, iclass 2, count 2 2006.201.15:14:31.34#ibcon#about to read 3, iclass 2, count 2 2006.201.15:14:31.36#ibcon#read 3, iclass 2, count 2 2006.201.15:14:31.36#ibcon#about to read 4, iclass 2, count 2 2006.201.15:14:31.36#ibcon#read 4, iclass 2, count 2 2006.201.15:14:31.36#ibcon#about to read 5, iclass 2, count 2 2006.201.15:14:31.36#ibcon#read 5, iclass 2, count 2 2006.201.15:14:31.36#ibcon#about to read 6, iclass 2, count 2 2006.201.15:14:31.36#ibcon#read 6, iclass 2, count 2 2006.201.15:14:31.36#ibcon#end of sib2, iclass 2, count 2 2006.201.15:14:31.36#ibcon#*mode == 0, iclass 2, count 2 2006.201.15:14:31.36#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.15:14:31.36#ibcon#[25=AT08-04\r\n] 2006.201.15:14:31.36#ibcon#*before write, iclass 2, count 2 2006.201.15:14:31.36#ibcon#enter sib2, iclass 2, count 2 2006.201.15:14:31.36#ibcon#flushed, iclass 2, count 2 2006.201.15:14:31.36#ibcon#about to write, iclass 2, count 2 2006.201.15:14:31.36#ibcon#wrote, iclass 2, count 2 2006.201.15:14:31.36#ibcon#about to read 3, iclass 2, count 2 2006.201.15:14:31.39#ibcon#read 3, iclass 2, count 2 2006.201.15:14:31.39#ibcon#about to read 4, iclass 2, count 2 2006.201.15:14:31.39#ibcon#read 4, iclass 2, count 2 2006.201.15:14:31.39#ibcon#about to read 5, iclass 2, count 2 2006.201.15:14:31.39#ibcon#read 5, iclass 2, count 2 2006.201.15:14:31.39#ibcon#about to read 6, iclass 2, count 2 2006.201.15:14:31.39#ibcon#read 6, iclass 2, count 2 2006.201.15:14:31.39#ibcon#end of sib2, iclass 2, count 2 2006.201.15:14:31.39#ibcon#*after write, iclass 2, count 2 2006.201.15:14:31.39#ibcon#*before return 0, iclass 2, count 2 2006.201.15:14:31.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.15:14:31.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.15:14:31.39#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.15:14:31.39#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:31.39#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.15:14:31.51#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.15:14:31.51#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.15:14:31.51#ibcon#enter wrdev, iclass 2, count 0 2006.201.15:14:31.51#ibcon#first serial, iclass 2, count 0 2006.201.15:14:31.51#ibcon#enter sib2, iclass 2, count 0 2006.201.15:14:31.51#ibcon#flushed, iclass 2, count 0 2006.201.15:14:31.51#ibcon#about to write, iclass 2, count 0 2006.201.15:14:31.51#ibcon#wrote, iclass 2, count 0 2006.201.15:14:31.51#ibcon#about to read 3, iclass 2, count 0 2006.201.15:14:31.53#ibcon#read 3, iclass 2, count 0 2006.201.15:14:31.53#ibcon#about to read 4, iclass 2, count 0 2006.201.15:14:31.53#ibcon#read 4, iclass 2, count 0 2006.201.15:14:31.53#ibcon#about to read 5, iclass 2, count 0 2006.201.15:14:31.53#ibcon#read 5, iclass 2, count 0 2006.201.15:14:31.53#ibcon#about to read 6, iclass 2, count 0 2006.201.15:14:31.53#ibcon#read 6, iclass 2, count 0 2006.201.15:14:31.53#ibcon#end of sib2, iclass 2, count 0 2006.201.15:14:31.53#ibcon#*mode == 0, iclass 2, count 0 2006.201.15:14:31.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.15:14:31.53#ibcon#[25=USB\r\n] 2006.201.15:14:31.53#ibcon#*before write, iclass 2, count 0 2006.201.15:14:31.53#ibcon#enter sib2, iclass 2, count 0 2006.201.15:14:31.53#ibcon#flushed, iclass 2, count 0 2006.201.15:14:31.53#ibcon#about to write, iclass 2, count 0 2006.201.15:14:31.53#ibcon#wrote, iclass 2, count 0 2006.201.15:14:31.53#ibcon#about to read 3, iclass 2, count 0 2006.201.15:14:31.56#ibcon#read 3, iclass 2, count 0 2006.201.15:14:31.56#ibcon#about to read 4, iclass 2, count 0 2006.201.15:14:31.56#ibcon#read 4, iclass 2, count 0 2006.201.15:14:31.56#ibcon#about to read 5, iclass 2, count 0 2006.201.15:14:31.56#ibcon#read 5, iclass 2, count 0 2006.201.15:14:31.56#ibcon#about to read 6, iclass 2, count 0 2006.201.15:14:31.56#ibcon#read 6, iclass 2, count 0 2006.201.15:14:31.56#ibcon#end of sib2, iclass 2, count 0 2006.201.15:14:31.56#ibcon#*after write, iclass 2, count 0 2006.201.15:14:31.56#ibcon#*before return 0, iclass 2, count 0 2006.201.15:14:31.56#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.15:14:31.56#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.15:14:31.56#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.15:14:31.56#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.15:14:31.56$vck44/vblo=1,629.99 2006.201.15:14:31.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.15:14:31.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.15:14:31.56#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:31.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.15:14:31.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.15:14:31.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.15:14:31.56#ibcon#enter wrdev, iclass 5, count 0 2006.201.15:14:31.56#ibcon#first serial, iclass 5, count 0 2006.201.15:14:31.56#ibcon#enter sib2, iclass 5, count 0 2006.201.15:14:31.56#ibcon#flushed, iclass 5, count 0 2006.201.15:14:31.56#ibcon#about to write, iclass 5, count 0 2006.201.15:14:31.56#ibcon#wrote, iclass 5, count 0 2006.201.15:14:31.56#ibcon#about to read 3, iclass 5, count 0 2006.201.15:14:31.58#ibcon#read 3, iclass 5, count 0 2006.201.15:14:31.58#ibcon#about to read 4, iclass 5, count 0 2006.201.15:14:31.58#ibcon#read 4, iclass 5, count 0 2006.201.15:14:31.58#ibcon#about to read 5, iclass 5, count 0 2006.201.15:14:31.58#ibcon#read 5, iclass 5, count 0 2006.201.15:14:31.58#ibcon#about to read 6, iclass 5, count 0 2006.201.15:14:31.58#ibcon#read 6, iclass 5, count 0 2006.201.15:14:31.58#ibcon#end of sib2, iclass 5, count 0 2006.201.15:14:31.58#ibcon#*mode == 0, iclass 5, count 0 2006.201.15:14:31.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.15:14:31.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:14:31.58#ibcon#*before write, iclass 5, count 0 2006.201.15:14:31.58#ibcon#enter sib2, iclass 5, count 0 2006.201.15:14:31.58#ibcon#flushed, iclass 5, count 0 2006.201.15:14:31.58#ibcon#about to write, iclass 5, count 0 2006.201.15:14:31.58#ibcon#wrote, iclass 5, count 0 2006.201.15:14:31.58#ibcon#about to read 3, iclass 5, count 0 2006.201.15:14:31.62#ibcon#read 3, iclass 5, count 0 2006.201.15:14:31.62#ibcon#about to read 4, iclass 5, count 0 2006.201.15:14:31.62#ibcon#read 4, iclass 5, count 0 2006.201.15:14:31.62#ibcon#about to read 5, iclass 5, count 0 2006.201.15:14:31.62#ibcon#read 5, iclass 5, count 0 2006.201.15:14:31.62#ibcon#about to read 6, iclass 5, count 0 2006.201.15:14:31.62#ibcon#read 6, iclass 5, count 0 2006.201.15:14:31.62#ibcon#end of sib2, iclass 5, count 0 2006.201.15:14:31.62#ibcon#*after write, iclass 5, count 0 2006.201.15:14:31.62#ibcon#*before return 0, iclass 5, count 0 2006.201.15:14:31.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.15:14:31.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.15:14:31.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.15:14:31.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.15:14:31.62$vck44/vb=1,4 2006.201.15:14:31.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.15:14:31.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.15:14:31.62#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:31.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.15:14:31.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.15:14:31.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.15:14:31.62#ibcon#enter wrdev, iclass 7, count 2 2006.201.15:14:31.62#ibcon#first serial, iclass 7, count 2 2006.201.15:14:31.62#ibcon#enter sib2, iclass 7, count 2 2006.201.15:14:31.62#ibcon#flushed, iclass 7, count 2 2006.201.15:14:31.62#ibcon#about to write, iclass 7, count 2 2006.201.15:14:31.62#ibcon#wrote, iclass 7, count 2 2006.201.15:14:31.62#ibcon#about to read 3, iclass 7, count 2 2006.201.15:14:31.64#ibcon#read 3, iclass 7, count 2 2006.201.15:14:31.64#ibcon#about to read 4, iclass 7, count 2 2006.201.15:14:31.64#ibcon#read 4, iclass 7, count 2 2006.201.15:14:31.64#ibcon#about to read 5, iclass 7, count 2 2006.201.15:14:31.64#ibcon#read 5, iclass 7, count 2 2006.201.15:14:31.64#ibcon#about to read 6, iclass 7, count 2 2006.201.15:14:31.64#ibcon#read 6, iclass 7, count 2 2006.201.15:14:31.64#ibcon#end of sib2, iclass 7, count 2 2006.201.15:14:31.64#ibcon#*mode == 0, iclass 7, count 2 2006.201.15:14:31.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.15:14:31.64#ibcon#[27=AT01-04\r\n] 2006.201.15:14:31.64#ibcon#*before write, iclass 7, count 2 2006.201.15:14:31.64#ibcon#enter sib2, iclass 7, count 2 2006.201.15:14:31.64#ibcon#flushed, iclass 7, count 2 2006.201.15:14:31.64#ibcon#about to write, iclass 7, count 2 2006.201.15:14:31.64#ibcon#wrote, iclass 7, count 2 2006.201.15:14:31.64#ibcon#about to read 3, iclass 7, count 2 2006.201.15:14:31.67#ibcon#read 3, iclass 7, count 2 2006.201.15:14:31.67#ibcon#about to read 4, iclass 7, count 2 2006.201.15:14:31.67#ibcon#read 4, iclass 7, count 2 2006.201.15:14:31.67#ibcon#about to read 5, iclass 7, count 2 2006.201.15:14:31.67#ibcon#read 5, iclass 7, count 2 2006.201.15:14:31.67#ibcon#about to read 6, iclass 7, count 2 2006.201.15:14:31.67#ibcon#read 6, iclass 7, count 2 2006.201.15:14:31.67#ibcon#end of sib2, iclass 7, count 2 2006.201.15:14:31.67#ibcon#*after write, iclass 7, count 2 2006.201.15:14:31.67#ibcon#*before return 0, iclass 7, count 2 2006.201.15:14:31.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.15:14:31.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.15:14:31.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.15:14:31.67#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:31.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.15:14:31.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.15:14:31.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.15:14:31.79#ibcon#enter wrdev, iclass 7, count 0 2006.201.15:14:31.79#ibcon#first serial, iclass 7, count 0 2006.201.15:14:31.79#ibcon#enter sib2, iclass 7, count 0 2006.201.15:14:31.79#ibcon#flushed, iclass 7, count 0 2006.201.15:14:31.79#ibcon#about to write, iclass 7, count 0 2006.201.15:14:31.79#ibcon#wrote, iclass 7, count 0 2006.201.15:14:31.79#ibcon#about to read 3, iclass 7, count 0 2006.201.15:14:31.81#ibcon#read 3, iclass 7, count 0 2006.201.15:14:31.81#ibcon#about to read 4, iclass 7, count 0 2006.201.15:14:31.81#ibcon#read 4, iclass 7, count 0 2006.201.15:14:31.81#ibcon#about to read 5, iclass 7, count 0 2006.201.15:14:31.81#ibcon#read 5, iclass 7, count 0 2006.201.15:14:31.81#ibcon#about to read 6, iclass 7, count 0 2006.201.15:14:31.81#ibcon#read 6, iclass 7, count 0 2006.201.15:14:31.81#ibcon#end of sib2, iclass 7, count 0 2006.201.15:14:31.81#ibcon#*mode == 0, iclass 7, count 0 2006.201.15:14:31.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.15:14:31.81#ibcon#[27=USB\r\n] 2006.201.15:14:31.81#ibcon#*before write, iclass 7, count 0 2006.201.15:14:31.81#ibcon#enter sib2, iclass 7, count 0 2006.201.15:14:31.81#ibcon#flushed, iclass 7, count 0 2006.201.15:14:31.81#ibcon#about to write, iclass 7, count 0 2006.201.15:14:31.81#ibcon#wrote, iclass 7, count 0 2006.201.15:14:31.81#ibcon#about to read 3, iclass 7, count 0 2006.201.15:14:31.84#ibcon#read 3, iclass 7, count 0 2006.201.15:14:31.84#ibcon#about to read 4, iclass 7, count 0 2006.201.15:14:31.84#ibcon#read 4, iclass 7, count 0 2006.201.15:14:31.84#ibcon#about to read 5, iclass 7, count 0 2006.201.15:14:31.84#ibcon#read 5, iclass 7, count 0 2006.201.15:14:31.84#ibcon#about to read 6, iclass 7, count 0 2006.201.15:14:31.84#ibcon#read 6, iclass 7, count 0 2006.201.15:14:31.84#ibcon#end of sib2, iclass 7, count 0 2006.201.15:14:31.84#ibcon#*after write, iclass 7, count 0 2006.201.15:14:31.84#ibcon#*before return 0, iclass 7, count 0 2006.201.15:14:31.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.15:14:31.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.15:14:31.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.15:14:31.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.15:14:31.84$vck44/vblo=2,634.99 2006.201.15:14:31.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.15:14:31.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.15:14:31.84#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:31.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:31.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:31.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:31.84#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:14:31.84#ibcon#first serial, iclass 11, count 0 2006.201.15:14:31.84#ibcon#enter sib2, iclass 11, count 0 2006.201.15:14:31.84#ibcon#flushed, iclass 11, count 0 2006.201.15:14:31.84#ibcon#about to write, iclass 11, count 0 2006.201.15:14:31.84#ibcon#wrote, iclass 11, count 0 2006.201.15:14:31.84#ibcon#about to read 3, iclass 11, count 0 2006.201.15:14:31.86#ibcon#read 3, iclass 11, count 0 2006.201.15:14:31.86#ibcon#about to read 4, iclass 11, count 0 2006.201.15:14:31.86#ibcon#read 4, iclass 11, count 0 2006.201.15:14:31.86#ibcon#about to read 5, iclass 11, count 0 2006.201.15:14:31.86#ibcon#read 5, iclass 11, count 0 2006.201.15:14:31.86#ibcon#about to read 6, iclass 11, count 0 2006.201.15:14:31.86#ibcon#read 6, iclass 11, count 0 2006.201.15:14:31.86#ibcon#end of sib2, iclass 11, count 0 2006.201.15:14:31.86#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:14:31.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:14:31.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:14:31.86#ibcon#*before write, iclass 11, count 0 2006.201.15:14:31.86#ibcon#enter sib2, iclass 11, count 0 2006.201.15:14:31.86#ibcon#flushed, iclass 11, count 0 2006.201.15:14:31.86#ibcon#about to write, iclass 11, count 0 2006.201.15:14:31.86#ibcon#wrote, iclass 11, count 0 2006.201.15:14:31.86#ibcon#about to read 3, iclass 11, count 0 2006.201.15:14:31.90#ibcon#read 3, iclass 11, count 0 2006.201.15:14:31.90#ibcon#about to read 4, iclass 11, count 0 2006.201.15:14:31.90#ibcon#read 4, iclass 11, count 0 2006.201.15:14:31.90#ibcon#about to read 5, iclass 11, count 0 2006.201.15:14:31.90#ibcon#read 5, iclass 11, count 0 2006.201.15:14:31.90#ibcon#about to read 6, iclass 11, count 0 2006.201.15:14:31.90#ibcon#read 6, iclass 11, count 0 2006.201.15:14:31.90#ibcon#end of sib2, iclass 11, count 0 2006.201.15:14:31.90#ibcon#*after write, iclass 11, count 0 2006.201.15:14:31.90#ibcon#*before return 0, iclass 11, count 0 2006.201.15:14:31.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:31.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:14:31.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:14:31.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:14:31.90$vck44/vb=2,5 2006.201.15:14:31.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.15:14:31.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.15:14:31.90#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:31.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:31.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:31.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:31.96#ibcon#enter wrdev, iclass 13, count 2 2006.201.15:14:31.96#ibcon#first serial, iclass 13, count 2 2006.201.15:14:31.96#ibcon#enter sib2, iclass 13, count 2 2006.201.15:14:31.96#ibcon#flushed, iclass 13, count 2 2006.201.15:14:31.96#ibcon#about to write, iclass 13, count 2 2006.201.15:14:31.96#ibcon#wrote, iclass 13, count 2 2006.201.15:14:31.96#ibcon#about to read 3, iclass 13, count 2 2006.201.15:14:31.98#ibcon#read 3, iclass 13, count 2 2006.201.15:14:31.98#ibcon#about to read 4, iclass 13, count 2 2006.201.15:14:31.98#ibcon#read 4, iclass 13, count 2 2006.201.15:14:31.98#ibcon#about to read 5, iclass 13, count 2 2006.201.15:14:31.98#ibcon#read 5, iclass 13, count 2 2006.201.15:14:31.98#ibcon#about to read 6, iclass 13, count 2 2006.201.15:14:31.98#ibcon#read 6, iclass 13, count 2 2006.201.15:14:31.98#ibcon#end of sib2, iclass 13, count 2 2006.201.15:14:31.98#ibcon#*mode == 0, iclass 13, count 2 2006.201.15:14:31.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.15:14:31.98#ibcon#[27=AT02-05\r\n] 2006.201.15:14:31.98#ibcon#*before write, iclass 13, count 2 2006.201.15:14:31.98#ibcon#enter sib2, iclass 13, count 2 2006.201.15:14:31.98#ibcon#flushed, iclass 13, count 2 2006.201.15:14:31.98#ibcon#about to write, iclass 13, count 2 2006.201.15:14:31.98#ibcon#wrote, iclass 13, count 2 2006.201.15:14:31.98#ibcon#about to read 3, iclass 13, count 2 2006.201.15:14:32.01#ibcon#read 3, iclass 13, count 2 2006.201.15:14:32.01#ibcon#about to read 4, iclass 13, count 2 2006.201.15:14:32.01#ibcon#read 4, iclass 13, count 2 2006.201.15:14:32.01#ibcon#about to read 5, iclass 13, count 2 2006.201.15:14:32.01#ibcon#read 5, iclass 13, count 2 2006.201.15:14:32.01#ibcon#about to read 6, iclass 13, count 2 2006.201.15:14:32.01#ibcon#read 6, iclass 13, count 2 2006.201.15:14:32.01#ibcon#end of sib2, iclass 13, count 2 2006.201.15:14:32.01#ibcon#*after write, iclass 13, count 2 2006.201.15:14:32.01#ibcon#*before return 0, iclass 13, count 2 2006.201.15:14:32.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:32.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.15:14:32.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.15:14:32.01#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:32.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:32.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:32.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:32.13#ibcon#enter wrdev, iclass 13, count 0 2006.201.15:14:32.13#ibcon#first serial, iclass 13, count 0 2006.201.15:14:32.13#ibcon#enter sib2, iclass 13, count 0 2006.201.15:14:32.13#ibcon#flushed, iclass 13, count 0 2006.201.15:14:32.13#ibcon#about to write, iclass 13, count 0 2006.201.15:14:32.13#ibcon#wrote, iclass 13, count 0 2006.201.15:14:32.13#ibcon#about to read 3, iclass 13, count 0 2006.201.15:14:32.15#ibcon#read 3, iclass 13, count 0 2006.201.15:14:32.15#ibcon#about to read 4, iclass 13, count 0 2006.201.15:14:32.15#ibcon#read 4, iclass 13, count 0 2006.201.15:14:32.15#ibcon#about to read 5, iclass 13, count 0 2006.201.15:14:32.15#ibcon#read 5, iclass 13, count 0 2006.201.15:14:32.15#ibcon#about to read 6, iclass 13, count 0 2006.201.15:14:32.15#ibcon#read 6, iclass 13, count 0 2006.201.15:14:32.15#ibcon#end of sib2, iclass 13, count 0 2006.201.15:14:32.15#ibcon#*mode == 0, iclass 13, count 0 2006.201.15:14:32.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.15:14:32.15#ibcon#[27=USB\r\n] 2006.201.15:14:32.15#ibcon#*before write, iclass 13, count 0 2006.201.15:14:32.15#ibcon#enter sib2, iclass 13, count 0 2006.201.15:14:32.15#ibcon#flushed, iclass 13, count 0 2006.201.15:14:32.15#ibcon#about to write, iclass 13, count 0 2006.201.15:14:32.15#ibcon#wrote, iclass 13, count 0 2006.201.15:14:32.15#ibcon#about to read 3, iclass 13, count 0 2006.201.15:14:32.18#ibcon#read 3, iclass 13, count 0 2006.201.15:14:32.18#ibcon#about to read 4, iclass 13, count 0 2006.201.15:14:32.18#ibcon#read 4, iclass 13, count 0 2006.201.15:14:32.18#ibcon#about to read 5, iclass 13, count 0 2006.201.15:14:32.18#ibcon#read 5, iclass 13, count 0 2006.201.15:14:32.18#ibcon#about to read 6, iclass 13, count 0 2006.201.15:14:32.18#ibcon#read 6, iclass 13, count 0 2006.201.15:14:32.18#ibcon#end of sib2, iclass 13, count 0 2006.201.15:14:32.18#ibcon#*after write, iclass 13, count 0 2006.201.15:14:32.18#ibcon#*before return 0, iclass 13, count 0 2006.201.15:14:32.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:32.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.15:14:32.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.15:14:32.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.15:14:32.18$vck44/vblo=3,649.99 2006.201.15:14:32.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.15:14:32.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.15:14:32.18#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:32.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:32.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:32.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:32.18#ibcon#enter wrdev, iclass 15, count 0 2006.201.15:14:32.18#ibcon#first serial, iclass 15, count 0 2006.201.15:14:32.18#ibcon#enter sib2, iclass 15, count 0 2006.201.15:14:32.18#ibcon#flushed, iclass 15, count 0 2006.201.15:14:32.18#ibcon#about to write, iclass 15, count 0 2006.201.15:14:32.18#ibcon#wrote, iclass 15, count 0 2006.201.15:14:32.18#ibcon#about to read 3, iclass 15, count 0 2006.201.15:14:32.20#ibcon#read 3, iclass 15, count 0 2006.201.15:14:32.20#ibcon#about to read 4, iclass 15, count 0 2006.201.15:14:32.20#ibcon#read 4, iclass 15, count 0 2006.201.15:14:32.20#ibcon#about to read 5, iclass 15, count 0 2006.201.15:14:32.20#ibcon#read 5, iclass 15, count 0 2006.201.15:14:32.20#ibcon#about to read 6, iclass 15, count 0 2006.201.15:14:32.20#ibcon#read 6, iclass 15, count 0 2006.201.15:14:32.20#ibcon#end of sib2, iclass 15, count 0 2006.201.15:14:32.20#ibcon#*mode == 0, iclass 15, count 0 2006.201.15:14:32.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.15:14:32.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:14:32.20#ibcon#*before write, iclass 15, count 0 2006.201.15:14:32.20#ibcon#enter sib2, iclass 15, count 0 2006.201.15:14:32.20#ibcon#flushed, iclass 15, count 0 2006.201.15:14:32.20#ibcon#about to write, iclass 15, count 0 2006.201.15:14:32.20#ibcon#wrote, iclass 15, count 0 2006.201.15:14:32.20#ibcon#about to read 3, iclass 15, count 0 2006.201.15:14:32.24#ibcon#read 3, iclass 15, count 0 2006.201.15:14:32.24#ibcon#about to read 4, iclass 15, count 0 2006.201.15:14:32.24#ibcon#read 4, iclass 15, count 0 2006.201.15:14:32.24#ibcon#about to read 5, iclass 15, count 0 2006.201.15:14:32.24#ibcon#read 5, iclass 15, count 0 2006.201.15:14:32.24#ibcon#about to read 6, iclass 15, count 0 2006.201.15:14:32.24#ibcon#read 6, iclass 15, count 0 2006.201.15:14:32.24#ibcon#end of sib2, iclass 15, count 0 2006.201.15:14:32.24#ibcon#*after write, iclass 15, count 0 2006.201.15:14:32.24#ibcon#*before return 0, iclass 15, count 0 2006.201.15:14:32.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:32.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.15:14:32.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.15:14:32.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.15:14:32.24$vck44/vb=3,4 2006.201.15:14:32.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.15:14:32.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.15:14:32.24#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:32.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:32.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:32.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:32.30#ibcon#enter wrdev, iclass 17, count 2 2006.201.15:14:32.30#ibcon#first serial, iclass 17, count 2 2006.201.15:14:32.30#ibcon#enter sib2, iclass 17, count 2 2006.201.15:14:32.30#ibcon#flushed, iclass 17, count 2 2006.201.15:14:32.30#ibcon#about to write, iclass 17, count 2 2006.201.15:14:32.30#ibcon#wrote, iclass 17, count 2 2006.201.15:14:32.30#ibcon#about to read 3, iclass 17, count 2 2006.201.15:14:32.32#ibcon#read 3, iclass 17, count 2 2006.201.15:14:32.32#ibcon#about to read 4, iclass 17, count 2 2006.201.15:14:32.32#ibcon#read 4, iclass 17, count 2 2006.201.15:14:32.32#ibcon#about to read 5, iclass 17, count 2 2006.201.15:14:32.32#ibcon#read 5, iclass 17, count 2 2006.201.15:14:32.32#ibcon#about to read 6, iclass 17, count 2 2006.201.15:14:32.32#ibcon#read 6, iclass 17, count 2 2006.201.15:14:32.32#ibcon#end of sib2, iclass 17, count 2 2006.201.15:14:32.32#ibcon#*mode == 0, iclass 17, count 2 2006.201.15:14:32.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.15:14:32.32#ibcon#[27=AT03-04\r\n] 2006.201.15:14:32.32#ibcon#*before write, iclass 17, count 2 2006.201.15:14:32.32#ibcon#enter sib2, iclass 17, count 2 2006.201.15:14:32.32#ibcon#flushed, iclass 17, count 2 2006.201.15:14:32.32#ibcon#about to write, iclass 17, count 2 2006.201.15:14:32.32#ibcon#wrote, iclass 17, count 2 2006.201.15:14:32.32#ibcon#about to read 3, iclass 17, count 2 2006.201.15:14:32.35#ibcon#read 3, iclass 17, count 2 2006.201.15:14:32.35#ibcon#about to read 4, iclass 17, count 2 2006.201.15:14:32.35#ibcon#read 4, iclass 17, count 2 2006.201.15:14:32.35#ibcon#about to read 5, iclass 17, count 2 2006.201.15:14:32.35#ibcon#read 5, iclass 17, count 2 2006.201.15:14:32.35#ibcon#about to read 6, iclass 17, count 2 2006.201.15:14:32.35#ibcon#read 6, iclass 17, count 2 2006.201.15:14:32.35#ibcon#end of sib2, iclass 17, count 2 2006.201.15:14:32.35#ibcon#*after write, iclass 17, count 2 2006.201.15:14:32.35#ibcon#*before return 0, iclass 17, count 2 2006.201.15:14:32.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:32.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.15:14:32.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.15:14:32.35#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:32.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:32.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:32.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:32.47#ibcon#enter wrdev, iclass 17, count 0 2006.201.15:14:32.47#ibcon#first serial, iclass 17, count 0 2006.201.15:14:32.47#ibcon#enter sib2, iclass 17, count 0 2006.201.15:14:32.47#ibcon#flushed, iclass 17, count 0 2006.201.15:14:32.47#ibcon#about to write, iclass 17, count 0 2006.201.15:14:32.47#ibcon#wrote, iclass 17, count 0 2006.201.15:14:32.47#ibcon#about to read 3, iclass 17, count 0 2006.201.15:14:32.49#ibcon#read 3, iclass 17, count 0 2006.201.15:14:32.49#ibcon#about to read 4, iclass 17, count 0 2006.201.15:14:32.49#ibcon#read 4, iclass 17, count 0 2006.201.15:14:32.49#ibcon#about to read 5, iclass 17, count 0 2006.201.15:14:32.49#ibcon#read 5, iclass 17, count 0 2006.201.15:14:32.49#ibcon#about to read 6, iclass 17, count 0 2006.201.15:14:32.49#ibcon#read 6, iclass 17, count 0 2006.201.15:14:32.49#ibcon#end of sib2, iclass 17, count 0 2006.201.15:14:32.49#ibcon#*mode == 0, iclass 17, count 0 2006.201.15:14:32.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.15:14:32.49#ibcon#[27=USB\r\n] 2006.201.15:14:32.49#ibcon#*before write, iclass 17, count 0 2006.201.15:14:32.49#ibcon#enter sib2, iclass 17, count 0 2006.201.15:14:32.49#ibcon#flushed, iclass 17, count 0 2006.201.15:14:32.49#ibcon#about to write, iclass 17, count 0 2006.201.15:14:32.49#ibcon#wrote, iclass 17, count 0 2006.201.15:14:32.49#ibcon#about to read 3, iclass 17, count 0 2006.201.15:14:32.52#ibcon#read 3, iclass 17, count 0 2006.201.15:14:32.52#ibcon#about to read 4, iclass 17, count 0 2006.201.15:14:32.52#ibcon#read 4, iclass 17, count 0 2006.201.15:14:32.52#ibcon#about to read 5, iclass 17, count 0 2006.201.15:14:32.52#ibcon#read 5, iclass 17, count 0 2006.201.15:14:32.52#ibcon#about to read 6, iclass 17, count 0 2006.201.15:14:32.52#ibcon#read 6, iclass 17, count 0 2006.201.15:14:32.52#ibcon#end of sib2, iclass 17, count 0 2006.201.15:14:32.52#ibcon#*after write, iclass 17, count 0 2006.201.15:14:32.52#ibcon#*before return 0, iclass 17, count 0 2006.201.15:14:32.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:32.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.15:14:32.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.15:14:32.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.15:14:32.52$vck44/vblo=4,679.99 2006.201.15:14:32.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.15:14:32.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.15:14:32.52#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:32.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:32.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:32.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:32.52#ibcon#enter wrdev, iclass 19, count 0 2006.201.15:14:32.52#ibcon#first serial, iclass 19, count 0 2006.201.15:14:32.52#ibcon#enter sib2, iclass 19, count 0 2006.201.15:14:32.52#ibcon#flushed, iclass 19, count 0 2006.201.15:14:32.52#ibcon#about to write, iclass 19, count 0 2006.201.15:14:32.52#ibcon#wrote, iclass 19, count 0 2006.201.15:14:32.52#ibcon#about to read 3, iclass 19, count 0 2006.201.15:14:32.54#ibcon#read 3, iclass 19, count 0 2006.201.15:14:32.54#ibcon#about to read 4, iclass 19, count 0 2006.201.15:14:32.54#ibcon#read 4, iclass 19, count 0 2006.201.15:14:32.54#ibcon#about to read 5, iclass 19, count 0 2006.201.15:14:32.54#ibcon#read 5, iclass 19, count 0 2006.201.15:14:32.54#ibcon#about to read 6, iclass 19, count 0 2006.201.15:14:32.54#ibcon#read 6, iclass 19, count 0 2006.201.15:14:32.54#ibcon#end of sib2, iclass 19, count 0 2006.201.15:14:32.54#ibcon#*mode == 0, iclass 19, count 0 2006.201.15:14:32.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.15:14:32.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:14:32.54#ibcon#*before write, iclass 19, count 0 2006.201.15:14:32.54#ibcon#enter sib2, iclass 19, count 0 2006.201.15:14:32.54#ibcon#flushed, iclass 19, count 0 2006.201.15:14:32.54#ibcon#about to write, iclass 19, count 0 2006.201.15:14:32.54#ibcon#wrote, iclass 19, count 0 2006.201.15:14:32.54#ibcon#about to read 3, iclass 19, count 0 2006.201.15:14:32.58#ibcon#read 3, iclass 19, count 0 2006.201.15:14:32.58#ibcon#about to read 4, iclass 19, count 0 2006.201.15:14:32.58#ibcon#read 4, iclass 19, count 0 2006.201.15:14:32.58#ibcon#about to read 5, iclass 19, count 0 2006.201.15:14:32.58#ibcon#read 5, iclass 19, count 0 2006.201.15:14:32.58#ibcon#about to read 6, iclass 19, count 0 2006.201.15:14:32.58#ibcon#read 6, iclass 19, count 0 2006.201.15:14:32.58#ibcon#end of sib2, iclass 19, count 0 2006.201.15:14:32.58#ibcon#*after write, iclass 19, count 0 2006.201.15:14:32.58#ibcon#*before return 0, iclass 19, count 0 2006.201.15:14:32.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:32.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.15:14:32.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.15:14:32.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.15:14:32.58$vck44/vb=4,5 2006.201.15:14:32.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.15:14:32.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.15:14:32.58#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:32.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:32.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:32.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:32.64#ibcon#enter wrdev, iclass 21, count 2 2006.201.15:14:32.64#ibcon#first serial, iclass 21, count 2 2006.201.15:14:32.64#ibcon#enter sib2, iclass 21, count 2 2006.201.15:14:32.64#ibcon#flushed, iclass 21, count 2 2006.201.15:14:32.64#ibcon#about to write, iclass 21, count 2 2006.201.15:14:32.64#ibcon#wrote, iclass 21, count 2 2006.201.15:14:32.64#ibcon#about to read 3, iclass 21, count 2 2006.201.15:14:32.66#ibcon#read 3, iclass 21, count 2 2006.201.15:14:32.66#ibcon#about to read 4, iclass 21, count 2 2006.201.15:14:32.66#ibcon#read 4, iclass 21, count 2 2006.201.15:14:32.66#ibcon#about to read 5, iclass 21, count 2 2006.201.15:14:32.66#ibcon#read 5, iclass 21, count 2 2006.201.15:14:32.66#ibcon#about to read 6, iclass 21, count 2 2006.201.15:14:32.66#ibcon#read 6, iclass 21, count 2 2006.201.15:14:32.66#ibcon#end of sib2, iclass 21, count 2 2006.201.15:14:32.66#ibcon#*mode == 0, iclass 21, count 2 2006.201.15:14:32.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.15:14:32.66#ibcon#[27=AT04-05\r\n] 2006.201.15:14:32.66#ibcon#*before write, iclass 21, count 2 2006.201.15:14:32.66#ibcon#enter sib2, iclass 21, count 2 2006.201.15:14:32.66#ibcon#flushed, iclass 21, count 2 2006.201.15:14:32.66#ibcon#about to write, iclass 21, count 2 2006.201.15:14:32.66#ibcon#wrote, iclass 21, count 2 2006.201.15:14:32.66#ibcon#about to read 3, iclass 21, count 2 2006.201.15:14:32.69#ibcon#read 3, iclass 21, count 2 2006.201.15:14:32.69#ibcon#about to read 4, iclass 21, count 2 2006.201.15:14:32.69#ibcon#read 4, iclass 21, count 2 2006.201.15:14:32.69#ibcon#about to read 5, iclass 21, count 2 2006.201.15:14:32.69#ibcon#read 5, iclass 21, count 2 2006.201.15:14:32.69#ibcon#about to read 6, iclass 21, count 2 2006.201.15:14:32.69#ibcon#read 6, iclass 21, count 2 2006.201.15:14:32.69#ibcon#end of sib2, iclass 21, count 2 2006.201.15:14:32.69#ibcon#*after write, iclass 21, count 2 2006.201.15:14:32.69#ibcon#*before return 0, iclass 21, count 2 2006.201.15:14:32.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:32.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.15:14:32.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.15:14:32.69#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:32.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:32.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:32.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:32.81#ibcon#enter wrdev, iclass 21, count 0 2006.201.15:14:32.81#ibcon#first serial, iclass 21, count 0 2006.201.15:14:32.81#ibcon#enter sib2, iclass 21, count 0 2006.201.15:14:32.81#ibcon#flushed, iclass 21, count 0 2006.201.15:14:32.81#ibcon#about to write, iclass 21, count 0 2006.201.15:14:32.81#ibcon#wrote, iclass 21, count 0 2006.201.15:14:32.81#ibcon#about to read 3, iclass 21, count 0 2006.201.15:14:32.83#ibcon#read 3, iclass 21, count 0 2006.201.15:14:32.83#ibcon#about to read 4, iclass 21, count 0 2006.201.15:14:32.83#ibcon#read 4, iclass 21, count 0 2006.201.15:14:32.83#ibcon#about to read 5, iclass 21, count 0 2006.201.15:14:32.83#ibcon#read 5, iclass 21, count 0 2006.201.15:14:32.83#ibcon#about to read 6, iclass 21, count 0 2006.201.15:14:32.83#ibcon#read 6, iclass 21, count 0 2006.201.15:14:32.83#ibcon#end of sib2, iclass 21, count 0 2006.201.15:14:32.83#ibcon#*mode == 0, iclass 21, count 0 2006.201.15:14:32.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.15:14:32.83#ibcon#[27=USB\r\n] 2006.201.15:14:32.83#ibcon#*before write, iclass 21, count 0 2006.201.15:14:32.83#ibcon#enter sib2, iclass 21, count 0 2006.201.15:14:32.83#ibcon#flushed, iclass 21, count 0 2006.201.15:14:32.83#ibcon#about to write, iclass 21, count 0 2006.201.15:14:32.83#ibcon#wrote, iclass 21, count 0 2006.201.15:14:32.83#ibcon#about to read 3, iclass 21, count 0 2006.201.15:14:32.86#ibcon#read 3, iclass 21, count 0 2006.201.15:14:32.86#ibcon#about to read 4, iclass 21, count 0 2006.201.15:14:32.86#ibcon#read 4, iclass 21, count 0 2006.201.15:14:32.86#ibcon#about to read 5, iclass 21, count 0 2006.201.15:14:32.86#ibcon#read 5, iclass 21, count 0 2006.201.15:14:32.86#ibcon#about to read 6, iclass 21, count 0 2006.201.15:14:32.86#ibcon#read 6, iclass 21, count 0 2006.201.15:14:32.86#ibcon#end of sib2, iclass 21, count 0 2006.201.15:14:32.86#ibcon#*after write, iclass 21, count 0 2006.201.15:14:32.86#ibcon#*before return 0, iclass 21, count 0 2006.201.15:14:32.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:32.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.15:14:32.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.15:14:32.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.15:14:32.86$vck44/vblo=5,709.99 2006.201.15:14:32.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.15:14:32.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.15:14:32.86#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:32.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:32.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:32.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:32.86#ibcon#enter wrdev, iclass 23, count 0 2006.201.15:14:32.86#ibcon#first serial, iclass 23, count 0 2006.201.15:14:32.86#ibcon#enter sib2, iclass 23, count 0 2006.201.15:14:32.86#ibcon#flushed, iclass 23, count 0 2006.201.15:14:32.86#ibcon#about to write, iclass 23, count 0 2006.201.15:14:32.86#ibcon#wrote, iclass 23, count 0 2006.201.15:14:32.86#ibcon#about to read 3, iclass 23, count 0 2006.201.15:14:32.88#ibcon#read 3, iclass 23, count 0 2006.201.15:14:32.88#ibcon#about to read 4, iclass 23, count 0 2006.201.15:14:32.88#ibcon#read 4, iclass 23, count 0 2006.201.15:14:32.88#ibcon#about to read 5, iclass 23, count 0 2006.201.15:14:32.88#ibcon#read 5, iclass 23, count 0 2006.201.15:14:32.88#ibcon#about to read 6, iclass 23, count 0 2006.201.15:14:32.88#ibcon#read 6, iclass 23, count 0 2006.201.15:14:32.88#ibcon#end of sib2, iclass 23, count 0 2006.201.15:14:32.88#ibcon#*mode == 0, iclass 23, count 0 2006.201.15:14:32.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.15:14:32.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:14:32.88#ibcon#*before write, iclass 23, count 0 2006.201.15:14:32.88#ibcon#enter sib2, iclass 23, count 0 2006.201.15:14:32.88#ibcon#flushed, iclass 23, count 0 2006.201.15:14:32.88#ibcon#about to write, iclass 23, count 0 2006.201.15:14:32.88#ibcon#wrote, iclass 23, count 0 2006.201.15:14:32.88#ibcon#about to read 3, iclass 23, count 0 2006.201.15:14:32.92#ibcon#read 3, iclass 23, count 0 2006.201.15:14:32.92#ibcon#about to read 4, iclass 23, count 0 2006.201.15:14:32.92#ibcon#read 4, iclass 23, count 0 2006.201.15:14:32.92#ibcon#about to read 5, iclass 23, count 0 2006.201.15:14:32.92#ibcon#read 5, iclass 23, count 0 2006.201.15:14:32.92#ibcon#about to read 6, iclass 23, count 0 2006.201.15:14:32.92#ibcon#read 6, iclass 23, count 0 2006.201.15:14:32.92#ibcon#end of sib2, iclass 23, count 0 2006.201.15:14:32.92#ibcon#*after write, iclass 23, count 0 2006.201.15:14:32.92#ibcon#*before return 0, iclass 23, count 0 2006.201.15:14:32.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:32.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.15:14:32.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.15:14:32.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.15:14:32.92$vck44/vb=5,4 2006.201.15:14:32.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.15:14:32.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.15:14:32.92#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:32.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:32.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:32.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:32.98#ibcon#enter wrdev, iclass 25, count 2 2006.201.15:14:32.98#ibcon#first serial, iclass 25, count 2 2006.201.15:14:32.98#ibcon#enter sib2, iclass 25, count 2 2006.201.15:14:32.98#ibcon#flushed, iclass 25, count 2 2006.201.15:14:32.98#ibcon#about to write, iclass 25, count 2 2006.201.15:14:32.98#ibcon#wrote, iclass 25, count 2 2006.201.15:14:32.98#ibcon#about to read 3, iclass 25, count 2 2006.201.15:14:33.00#ibcon#read 3, iclass 25, count 2 2006.201.15:14:33.00#ibcon#about to read 4, iclass 25, count 2 2006.201.15:14:33.00#ibcon#read 4, iclass 25, count 2 2006.201.15:14:33.00#ibcon#about to read 5, iclass 25, count 2 2006.201.15:14:33.00#ibcon#read 5, iclass 25, count 2 2006.201.15:14:33.00#ibcon#about to read 6, iclass 25, count 2 2006.201.15:14:33.00#ibcon#read 6, iclass 25, count 2 2006.201.15:14:33.00#ibcon#end of sib2, iclass 25, count 2 2006.201.15:14:33.00#ibcon#*mode == 0, iclass 25, count 2 2006.201.15:14:33.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.15:14:33.00#ibcon#[27=AT05-04\r\n] 2006.201.15:14:33.00#ibcon#*before write, iclass 25, count 2 2006.201.15:14:33.00#ibcon#enter sib2, iclass 25, count 2 2006.201.15:14:33.00#ibcon#flushed, iclass 25, count 2 2006.201.15:14:33.00#ibcon#about to write, iclass 25, count 2 2006.201.15:14:33.00#ibcon#wrote, iclass 25, count 2 2006.201.15:14:33.00#ibcon#about to read 3, iclass 25, count 2 2006.201.15:14:33.03#ibcon#read 3, iclass 25, count 2 2006.201.15:14:33.03#ibcon#about to read 4, iclass 25, count 2 2006.201.15:14:33.03#ibcon#read 4, iclass 25, count 2 2006.201.15:14:33.03#ibcon#about to read 5, iclass 25, count 2 2006.201.15:14:33.03#ibcon#read 5, iclass 25, count 2 2006.201.15:14:33.03#ibcon#about to read 6, iclass 25, count 2 2006.201.15:14:33.03#ibcon#read 6, iclass 25, count 2 2006.201.15:14:33.03#ibcon#end of sib2, iclass 25, count 2 2006.201.15:14:33.03#ibcon#*after write, iclass 25, count 2 2006.201.15:14:33.03#ibcon#*before return 0, iclass 25, count 2 2006.201.15:14:33.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:33.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.15:14:33.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.15:14:33.03#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:33.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:33.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:33.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:33.15#ibcon#enter wrdev, iclass 25, count 0 2006.201.15:14:33.15#ibcon#first serial, iclass 25, count 0 2006.201.15:14:33.15#ibcon#enter sib2, iclass 25, count 0 2006.201.15:14:33.15#ibcon#flushed, iclass 25, count 0 2006.201.15:14:33.15#ibcon#about to write, iclass 25, count 0 2006.201.15:14:33.15#ibcon#wrote, iclass 25, count 0 2006.201.15:14:33.15#ibcon#about to read 3, iclass 25, count 0 2006.201.15:14:33.17#ibcon#read 3, iclass 25, count 0 2006.201.15:14:33.17#ibcon#about to read 4, iclass 25, count 0 2006.201.15:14:33.17#ibcon#read 4, iclass 25, count 0 2006.201.15:14:33.17#ibcon#about to read 5, iclass 25, count 0 2006.201.15:14:33.17#ibcon#read 5, iclass 25, count 0 2006.201.15:14:33.17#ibcon#about to read 6, iclass 25, count 0 2006.201.15:14:33.17#ibcon#read 6, iclass 25, count 0 2006.201.15:14:33.17#ibcon#end of sib2, iclass 25, count 0 2006.201.15:14:33.17#ibcon#*mode == 0, iclass 25, count 0 2006.201.15:14:33.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.15:14:33.17#ibcon#[27=USB\r\n] 2006.201.15:14:33.17#ibcon#*before write, iclass 25, count 0 2006.201.15:14:33.17#ibcon#enter sib2, iclass 25, count 0 2006.201.15:14:33.17#ibcon#flushed, iclass 25, count 0 2006.201.15:14:33.17#ibcon#about to write, iclass 25, count 0 2006.201.15:14:33.17#ibcon#wrote, iclass 25, count 0 2006.201.15:14:33.17#ibcon#about to read 3, iclass 25, count 0 2006.201.15:14:33.20#ibcon#read 3, iclass 25, count 0 2006.201.15:14:33.20#ibcon#about to read 4, iclass 25, count 0 2006.201.15:14:33.20#ibcon#read 4, iclass 25, count 0 2006.201.15:14:33.20#ibcon#about to read 5, iclass 25, count 0 2006.201.15:14:33.20#ibcon#read 5, iclass 25, count 0 2006.201.15:14:33.20#ibcon#about to read 6, iclass 25, count 0 2006.201.15:14:33.20#ibcon#read 6, iclass 25, count 0 2006.201.15:14:33.20#ibcon#end of sib2, iclass 25, count 0 2006.201.15:14:33.20#ibcon#*after write, iclass 25, count 0 2006.201.15:14:33.20#ibcon#*before return 0, iclass 25, count 0 2006.201.15:14:33.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:33.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.15:14:33.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.15:14:33.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.15:14:33.20$vck44/vblo=6,719.99 2006.201.15:14:33.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.15:14:33.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.15:14:33.20#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:33.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:33.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:33.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:33.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.15:14:33.20#ibcon#first serial, iclass 27, count 0 2006.201.15:14:33.20#ibcon#enter sib2, iclass 27, count 0 2006.201.15:14:33.20#ibcon#flushed, iclass 27, count 0 2006.201.15:14:33.20#ibcon#about to write, iclass 27, count 0 2006.201.15:14:33.20#ibcon#wrote, iclass 27, count 0 2006.201.15:14:33.20#ibcon#about to read 3, iclass 27, count 0 2006.201.15:14:33.22#ibcon#read 3, iclass 27, count 0 2006.201.15:14:33.22#ibcon#about to read 4, iclass 27, count 0 2006.201.15:14:33.22#ibcon#read 4, iclass 27, count 0 2006.201.15:14:33.22#ibcon#about to read 5, iclass 27, count 0 2006.201.15:14:33.22#ibcon#read 5, iclass 27, count 0 2006.201.15:14:33.22#ibcon#about to read 6, iclass 27, count 0 2006.201.15:14:33.22#ibcon#read 6, iclass 27, count 0 2006.201.15:14:33.22#ibcon#end of sib2, iclass 27, count 0 2006.201.15:14:33.22#ibcon#*mode == 0, iclass 27, count 0 2006.201.15:14:33.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.15:14:33.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:14:33.22#ibcon#*before write, iclass 27, count 0 2006.201.15:14:33.22#ibcon#enter sib2, iclass 27, count 0 2006.201.15:14:33.22#ibcon#flushed, iclass 27, count 0 2006.201.15:14:33.22#ibcon#about to write, iclass 27, count 0 2006.201.15:14:33.22#ibcon#wrote, iclass 27, count 0 2006.201.15:14:33.22#ibcon#about to read 3, iclass 27, count 0 2006.201.15:14:33.26#ibcon#read 3, iclass 27, count 0 2006.201.15:14:33.26#ibcon#about to read 4, iclass 27, count 0 2006.201.15:14:33.26#ibcon#read 4, iclass 27, count 0 2006.201.15:14:33.26#ibcon#about to read 5, iclass 27, count 0 2006.201.15:14:33.26#ibcon#read 5, iclass 27, count 0 2006.201.15:14:33.26#ibcon#about to read 6, iclass 27, count 0 2006.201.15:14:33.26#ibcon#read 6, iclass 27, count 0 2006.201.15:14:33.26#ibcon#end of sib2, iclass 27, count 0 2006.201.15:14:33.26#ibcon#*after write, iclass 27, count 0 2006.201.15:14:33.26#ibcon#*before return 0, iclass 27, count 0 2006.201.15:14:33.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:33.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:14:33.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.15:14:33.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.15:14:33.26$vck44/vb=6,4 2006.201.15:14:33.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.15:14:33.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.15:14:33.26#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:33.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:33.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:33.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:33.32#ibcon#enter wrdev, iclass 29, count 2 2006.201.15:14:33.32#ibcon#first serial, iclass 29, count 2 2006.201.15:14:33.32#ibcon#enter sib2, iclass 29, count 2 2006.201.15:14:33.32#ibcon#flushed, iclass 29, count 2 2006.201.15:14:33.32#ibcon#about to write, iclass 29, count 2 2006.201.15:14:33.32#ibcon#wrote, iclass 29, count 2 2006.201.15:14:33.32#ibcon#about to read 3, iclass 29, count 2 2006.201.15:14:33.34#ibcon#read 3, iclass 29, count 2 2006.201.15:14:33.34#ibcon#about to read 4, iclass 29, count 2 2006.201.15:14:33.34#ibcon#read 4, iclass 29, count 2 2006.201.15:14:33.34#ibcon#about to read 5, iclass 29, count 2 2006.201.15:14:33.34#ibcon#read 5, iclass 29, count 2 2006.201.15:14:33.34#ibcon#about to read 6, iclass 29, count 2 2006.201.15:14:33.34#ibcon#read 6, iclass 29, count 2 2006.201.15:14:33.34#ibcon#end of sib2, iclass 29, count 2 2006.201.15:14:33.34#ibcon#*mode == 0, iclass 29, count 2 2006.201.15:14:33.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.15:14:33.34#ibcon#[27=AT06-04\r\n] 2006.201.15:14:33.34#ibcon#*before write, iclass 29, count 2 2006.201.15:14:33.34#ibcon#enter sib2, iclass 29, count 2 2006.201.15:14:33.34#ibcon#flushed, iclass 29, count 2 2006.201.15:14:33.34#ibcon#about to write, iclass 29, count 2 2006.201.15:14:33.34#ibcon#wrote, iclass 29, count 2 2006.201.15:14:33.34#ibcon#about to read 3, iclass 29, count 2 2006.201.15:14:33.37#ibcon#read 3, iclass 29, count 2 2006.201.15:14:33.37#ibcon#about to read 4, iclass 29, count 2 2006.201.15:14:33.37#ibcon#read 4, iclass 29, count 2 2006.201.15:14:33.37#ibcon#about to read 5, iclass 29, count 2 2006.201.15:14:33.37#ibcon#read 5, iclass 29, count 2 2006.201.15:14:33.37#ibcon#about to read 6, iclass 29, count 2 2006.201.15:14:33.37#ibcon#read 6, iclass 29, count 2 2006.201.15:14:33.37#ibcon#end of sib2, iclass 29, count 2 2006.201.15:14:33.37#ibcon#*after write, iclass 29, count 2 2006.201.15:14:33.37#ibcon#*before return 0, iclass 29, count 2 2006.201.15:14:33.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:33.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.15:14:33.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.15:14:33.37#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:33.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:33.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:33.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:33.49#ibcon#enter wrdev, iclass 29, count 0 2006.201.15:14:33.49#ibcon#first serial, iclass 29, count 0 2006.201.15:14:33.49#ibcon#enter sib2, iclass 29, count 0 2006.201.15:14:33.49#ibcon#flushed, iclass 29, count 0 2006.201.15:14:33.49#ibcon#about to write, iclass 29, count 0 2006.201.15:14:33.49#ibcon#wrote, iclass 29, count 0 2006.201.15:14:33.49#ibcon#about to read 3, iclass 29, count 0 2006.201.15:14:33.51#ibcon#read 3, iclass 29, count 0 2006.201.15:14:33.51#ibcon#about to read 4, iclass 29, count 0 2006.201.15:14:33.51#ibcon#read 4, iclass 29, count 0 2006.201.15:14:33.51#ibcon#about to read 5, iclass 29, count 0 2006.201.15:14:33.51#ibcon#read 5, iclass 29, count 0 2006.201.15:14:33.51#ibcon#about to read 6, iclass 29, count 0 2006.201.15:14:33.51#ibcon#read 6, iclass 29, count 0 2006.201.15:14:33.51#ibcon#end of sib2, iclass 29, count 0 2006.201.15:14:33.51#ibcon#*mode == 0, iclass 29, count 0 2006.201.15:14:33.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.15:14:33.51#ibcon#[27=USB\r\n] 2006.201.15:14:33.51#ibcon#*before write, iclass 29, count 0 2006.201.15:14:33.51#ibcon#enter sib2, iclass 29, count 0 2006.201.15:14:33.51#ibcon#flushed, iclass 29, count 0 2006.201.15:14:33.51#ibcon#about to write, iclass 29, count 0 2006.201.15:14:33.51#ibcon#wrote, iclass 29, count 0 2006.201.15:14:33.51#ibcon#about to read 3, iclass 29, count 0 2006.201.15:14:33.54#ibcon#read 3, iclass 29, count 0 2006.201.15:14:33.54#ibcon#about to read 4, iclass 29, count 0 2006.201.15:14:33.54#ibcon#read 4, iclass 29, count 0 2006.201.15:14:33.54#ibcon#about to read 5, iclass 29, count 0 2006.201.15:14:33.54#ibcon#read 5, iclass 29, count 0 2006.201.15:14:33.54#ibcon#about to read 6, iclass 29, count 0 2006.201.15:14:33.54#ibcon#read 6, iclass 29, count 0 2006.201.15:14:33.54#ibcon#end of sib2, iclass 29, count 0 2006.201.15:14:33.54#ibcon#*after write, iclass 29, count 0 2006.201.15:14:33.54#ibcon#*before return 0, iclass 29, count 0 2006.201.15:14:33.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:33.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.15:14:33.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.15:14:33.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.15:14:33.54$vck44/vblo=7,734.99 2006.201.15:14:33.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.15:14:33.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.15:14:33.54#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:33.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:33.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:33.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:33.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.15:14:33.54#ibcon#first serial, iclass 31, count 0 2006.201.15:14:33.54#ibcon#enter sib2, iclass 31, count 0 2006.201.15:14:33.54#ibcon#flushed, iclass 31, count 0 2006.201.15:14:33.54#ibcon#about to write, iclass 31, count 0 2006.201.15:14:33.54#ibcon#wrote, iclass 31, count 0 2006.201.15:14:33.54#ibcon#about to read 3, iclass 31, count 0 2006.201.15:14:33.56#ibcon#read 3, iclass 31, count 0 2006.201.15:14:33.56#ibcon#about to read 4, iclass 31, count 0 2006.201.15:14:33.56#ibcon#read 4, iclass 31, count 0 2006.201.15:14:33.56#ibcon#about to read 5, iclass 31, count 0 2006.201.15:14:33.56#ibcon#read 5, iclass 31, count 0 2006.201.15:14:33.56#ibcon#about to read 6, iclass 31, count 0 2006.201.15:14:33.56#ibcon#read 6, iclass 31, count 0 2006.201.15:14:33.56#ibcon#end of sib2, iclass 31, count 0 2006.201.15:14:33.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.15:14:33.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.15:14:33.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:14:33.56#ibcon#*before write, iclass 31, count 0 2006.201.15:14:33.56#ibcon#enter sib2, iclass 31, count 0 2006.201.15:14:33.56#ibcon#flushed, iclass 31, count 0 2006.201.15:14:33.56#ibcon#about to write, iclass 31, count 0 2006.201.15:14:33.56#ibcon#wrote, iclass 31, count 0 2006.201.15:14:33.56#ibcon#about to read 3, iclass 31, count 0 2006.201.15:14:33.60#ibcon#read 3, iclass 31, count 0 2006.201.15:14:33.60#ibcon#about to read 4, iclass 31, count 0 2006.201.15:14:33.60#ibcon#read 4, iclass 31, count 0 2006.201.15:14:33.60#ibcon#about to read 5, iclass 31, count 0 2006.201.15:14:33.60#ibcon#read 5, iclass 31, count 0 2006.201.15:14:33.60#ibcon#about to read 6, iclass 31, count 0 2006.201.15:14:33.60#ibcon#read 6, iclass 31, count 0 2006.201.15:14:33.60#ibcon#end of sib2, iclass 31, count 0 2006.201.15:14:33.60#ibcon#*after write, iclass 31, count 0 2006.201.15:14:33.60#ibcon#*before return 0, iclass 31, count 0 2006.201.15:14:33.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:33.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.15:14:33.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.15:14:33.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.15:14:33.60$vck44/vb=7,4 2006.201.15:14:33.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.15:14:33.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.15:14:33.60#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:33.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:33.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:33.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:33.66#ibcon#enter wrdev, iclass 33, count 2 2006.201.15:14:33.66#ibcon#first serial, iclass 33, count 2 2006.201.15:14:33.66#ibcon#enter sib2, iclass 33, count 2 2006.201.15:14:33.66#ibcon#flushed, iclass 33, count 2 2006.201.15:14:33.66#ibcon#about to write, iclass 33, count 2 2006.201.15:14:33.66#ibcon#wrote, iclass 33, count 2 2006.201.15:14:33.66#ibcon#about to read 3, iclass 33, count 2 2006.201.15:14:33.68#ibcon#read 3, iclass 33, count 2 2006.201.15:14:33.68#ibcon#about to read 4, iclass 33, count 2 2006.201.15:14:33.68#ibcon#read 4, iclass 33, count 2 2006.201.15:14:33.68#ibcon#about to read 5, iclass 33, count 2 2006.201.15:14:33.68#ibcon#read 5, iclass 33, count 2 2006.201.15:14:33.68#ibcon#about to read 6, iclass 33, count 2 2006.201.15:14:33.68#ibcon#read 6, iclass 33, count 2 2006.201.15:14:33.68#ibcon#end of sib2, iclass 33, count 2 2006.201.15:14:33.68#ibcon#*mode == 0, iclass 33, count 2 2006.201.15:14:33.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.15:14:33.68#ibcon#[27=AT07-04\r\n] 2006.201.15:14:33.68#ibcon#*before write, iclass 33, count 2 2006.201.15:14:33.68#ibcon#enter sib2, iclass 33, count 2 2006.201.15:14:33.68#ibcon#flushed, iclass 33, count 2 2006.201.15:14:33.68#ibcon#about to write, iclass 33, count 2 2006.201.15:14:33.68#ibcon#wrote, iclass 33, count 2 2006.201.15:14:33.68#ibcon#about to read 3, iclass 33, count 2 2006.201.15:14:33.71#ibcon#read 3, iclass 33, count 2 2006.201.15:14:33.71#ibcon#about to read 4, iclass 33, count 2 2006.201.15:14:33.71#ibcon#read 4, iclass 33, count 2 2006.201.15:14:33.71#ibcon#about to read 5, iclass 33, count 2 2006.201.15:14:33.71#ibcon#read 5, iclass 33, count 2 2006.201.15:14:33.71#ibcon#about to read 6, iclass 33, count 2 2006.201.15:14:33.71#ibcon#read 6, iclass 33, count 2 2006.201.15:14:33.71#ibcon#end of sib2, iclass 33, count 2 2006.201.15:14:33.71#ibcon#*after write, iclass 33, count 2 2006.201.15:14:33.71#ibcon#*before return 0, iclass 33, count 2 2006.201.15:14:33.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:33.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.15:14:33.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.15:14:33.71#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:33.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:33.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:33.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:33.83#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:14:33.83#ibcon#first serial, iclass 33, count 0 2006.201.15:14:33.83#ibcon#enter sib2, iclass 33, count 0 2006.201.15:14:33.83#ibcon#flushed, iclass 33, count 0 2006.201.15:14:33.83#ibcon#about to write, iclass 33, count 0 2006.201.15:14:33.83#ibcon#wrote, iclass 33, count 0 2006.201.15:14:33.83#ibcon#about to read 3, iclass 33, count 0 2006.201.15:14:33.85#ibcon#read 3, iclass 33, count 0 2006.201.15:14:33.85#ibcon#about to read 4, iclass 33, count 0 2006.201.15:14:33.85#ibcon#read 4, iclass 33, count 0 2006.201.15:14:33.85#ibcon#about to read 5, iclass 33, count 0 2006.201.15:14:33.85#ibcon#read 5, iclass 33, count 0 2006.201.15:14:33.85#ibcon#about to read 6, iclass 33, count 0 2006.201.15:14:33.85#ibcon#read 6, iclass 33, count 0 2006.201.15:14:33.85#ibcon#end of sib2, iclass 33, count 0 2006.201.15:14:33.85#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:14:33.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:14:33.85#ibcon#[27=USB\r\n] 2006.201.15:14:33.85#ibcon#*before write, iclass 33, count 0 2006.201.15:14:33.85#ibcon#enter sib2, iclass 33, count 0 2006.201.15:14:33.85#ibcon#flushed, iclass 33, count 0 2006.201.15:14:33.85#ibcon#about to write, iclass 33, count 0 2006.201.15:14:33.85#ibcon#wrote, iclass 33, count 0 2006.201.15:14:33.85#ibcon#about to read 3, iclass 33, count 0 2006.201.15:14:33.88#ibcon#read 3, iclass 33, count 0 2006.201.15:14:33.88#ibcon#about to read 4, iclass 33, count 0 2006.201.15:14:33.88#ibcon#read 4, iclass 33, count 0 2006.201.15:14:33.88#ibcon#about to read 5, iclass 33, count 0 2006.201.15:14:33.88#ibcon#read 5, iclass 33, count 0 2006.201.15:14:33.88#ibcon#about to read 6, iclass 33, count 0 2006.201.15:14:33.88#ibcon#read 6, iclass 33, count 0 2006.201.15:14:33.88#ibcon#end of sib2, iclass 33, count 0 2006.201.15:14:33.88#ibcon#*after write, iclass 33, count 0 2006.201.15:14:33.88#ibcon#*before return 0, iclass 33, count 0 2006.201.15:14:33.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:33.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.15:14:33.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:14:33.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:14:33.88$vck44/vblo=8,744.99 2006.201.15:14:33.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.15:14:33.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.15:14:33.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:14:33.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:33.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:33.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:33.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.15:14:33.88#ibcon#first serial, iclass 35, count 0 2006.201.15:14:33.88#ibcon#enter sib2, iclass 35, count 0 2006.201.15:14:33.88#ibcon#flushed, iclass 35, count 0 2006.201.15:14:33.88#ibcon#about to write, iclass 35, count 0 2006.201.15:14:33.88#ibcon#wrote, iclass 35, count 0 2006.201.15:14:33.88#ibcon#about to read 3, iclass 35, count 0 2006.201.15:14:33.90#ibcon#read 3, iclass 35, count 0 2006.201.15:14:33.90#ibcon#about to read 4, iclass 35, count 0 2006.201.15:14:33.90#ibcon#read 4, iclass 35, count 0 2006.201.15:14:33.90#ibcon#about to read 5, iclass 35, count 0 2006.201.15:14:33.90#ibcon#read 5, iclass 35, count 0 2006.201.15:14:33.90#ibcon#about to read 6, iclass 35, count 0 2006.201.15:14:33.90#ibcon#read 6, iclass 35, count 0 2006.201.15:14:33.90#ibcon#end of sib2, iclass 35, count 0 2006.201.15:14:33.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.15:14:33.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.15:14:33.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:14:33.90#ibcon#*before write, iclass 35, count 0 2006.201.15:14:33.90#ibcon#enter sib2, iclass 35, count 0 2006.201.15:14:33.90#ibcon#flushed, iclass 35, count 0 2006.201.15:14:33.90#ibcon#about to write, iclass 35, count 0 2006.201.15:14:33.90#ibcon#wrote, iclass 35, count 0 2006.201.15:14:33.90#ibcon#about to read 3, iclass 35, count 0 2006.201.15:14:33.95#ibcon#read 3, iclass 35, count 0 2006.201.15:14:33.95#ibcon#about to read 4, iclass 35, count 0 2006.201.15:14:33.95#ibcon#read 4, iclass 35, count 0 2006.201.15:14:33.95#ibcon#about to read 5, iclass 35, count 0 2006.201.15:14:33.95#ibcon#read 5, iclass 35, count 0 2006.201.15:14:33.95#ibcon#about to read 6, iclass 35, count 0 2006.201.15:14:33.95#ibcon#read 6, iclass 35, count 0 2006.201.15:14:33.95#ibcon#end of sib2, iclass 35, count 0 2006.201.15:14:33.95#ibcon#*after write, iclass 35, count 0 2006.201.15:14:33.95#ibcon#*before return 0, iclass 35, count 0 2006.201.15:14:33.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:33.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.15:14:33.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.15:14:33.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.15:14:33.95$vck44/vb=8,4 2006.201.15:14:33.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.15:14:33.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.15:14:33.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:14:33.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:34.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:34.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:34.00#ibcon#enter wrdev, iclass 37, count 2 2006.201.15:14:34.00#ibcon#first serial, iclass 37, count 2 2006.201.15:14:34.00#ibcon#enter sib2, iclass 37, count 2 2006.201.15:14:34.00#ibcon#flushed, iclass 37, count 2 2006.201.15:14:34.00#ibcon#about to write, iclass 37, count 2 2006.201.15:14:34.00#ibcon#wrote, iclass 37, count 2 2006.201.15:14:34.00#ibcon#about to read 3, iclass 37, count 2 2006.201.15:14:34.02#ibcon#read 3, iclass 37, count 2 2006.201.15:14:34.02#ibcon#about to read 4, iclass 37, count 2 2006.201.15:14:34.02#ibcon#read 4, iclass 37, count 2 2006.201.15:14:34.02#ibcon#about to read 5, iclass 37, count 2 2006.201.15:14:34.02#ibcon#read 5, iclass 37, count 2 2006.201.15:14:34.02#ibcon#about to read 6, iclass 37, count 2 2006.201.15:14:34.02#ibcon#read 6, iclass 37, count 2 2006.201.15:14:34.02#ibcon#end of sib2, iclass 37, count 2 2006.201.15:14:34.02#ibcon#*mode == 0, iclass 37, count 2 2006.201.15:14:34.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.15:14:34.02#ibcon#[27=AT08-04\r\n] 2006.201.15:14:34.02#ibcon#*before write, iclass 37, count 2 2006.201.15:14:34.02#ibcon#enter sib2, iclass 37, count 2 2006.201.15:14:34.02#ibcon#flushed, iclass 37, count 2 2006.201.15:14:34.02#ibcon#about to write, iclass 37, count 2 2006.201.15:14:34.02#ibcon#wrote, iclass 37, count 2 2006.201.15:14:34.02#ibcon#about to read 3, iclass 37, count 2 2006.201.15:14:34.05#ibcon#read 3, iclass 37, count 2 2006.201.15:14:34.05#ibcon#about to read 4, iclass 37, count 2 2006.201.15:14:34.05#ibcon#read 4, iclass 37, count 2 2006.201.15:14:34.05#ibcon#about to read 5, iclass 37, count 2 2006.201.15:14:34.05#ibcon#read 5, iclass 37, count 2 2006.201.15:14:34.05#ibcon#about to read 6, iclass 37, count 2 2006.201.15:14:34.05#ibcon#read 6, iclass 37, count 2 2006.201.15:14:34.05#ibcon#end of sib2, iclass 37, count 2 2006.201.15:14:34.05#ibcon#*after write, iclass 37, count 2 2006.201.15:14:34.05#ibcon#*before return 0, iclass 37, count 2 2006.201.15:14:34.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:34.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:14:34.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.15:14:34.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:14:34.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:34.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:34.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:34.17#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:14:34.17#ibcon#first serial, iclass 37, count 0 2006.201.15:14:34.17#ibcon#enter sib2, iclass 37, count 0 2006.201.15:14:34.17#ibcon#flushed, iclass 37, count 0 2006.201.15:14:34.17#ibcon#about to write, iclass 37, count 0 2006.201.15:14:34.17#ibcon#wrote, iclass 37, count 0 2006.201.15:14:34.17#ibcon#about to read 3, iclass 37, count 0 2006.201.15:14:34.19#ibcon#read 3, iclass 37, count 0 2006.201.15:14:34.19#ibcon#about to read 4, iclass 37, count 0 2006.201.15:14:34.19#ibcon#read 4, iclass 37, count 0 2006.201.15:14:34.19#ibcon#about to read 5, iclass 37, count 0 2006.201.15:14:34.19#ibcon#read 5, iclass 37, count 0 2006.201.15:14:34.19#ibcon#about to read 6, iclass 37, count 0 2006.201.15:14:34.19#ibcon#read 6, iclass 37, count 0 2006.201.15:14:34.19#ibcon#end of sib2, iclass 37, count 0 2006.201.15:14:34.19#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:14:34.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:14:34.19#ibcon#[27=USB\r\n] 2006.201.15:14:34.19#ibcon#*before write, iclass 37, count 0 2006.201.15:14:34.19#ibcon#enter sib2, iclass 37, count 0 2006.201.15:14:34.19#ibcon#flushed, iclass 37, count 0 2006.201.15:14:34.19#ibcon#about to write, iclass 37, count 0 2006.201.15:14:34.19#ibcon#wrote, iclass 37, count 0 2006.201.15:14:34.19#ibcon#about to read 3, iclass 37, count 0 2006.201.15:14:34.22#ibcon#read 3, iclass 37, count 0 2006.201.15:14:34.22#ibcon#about to read 4, iclass 37, count 0 2006.201.15:14:34.22#ibcon#read 4, iclass 37, count 0 2006.201.15:14:34.22#ibcon#about to read 5, iclass 37, count 0 2006.201.15:14:34.22#ibcon#read 5, iclass 37, count 0 2006.201.15:14:34.22#ibcon#about to read 6, iclass 37, count 0 2006.201.15:14:34.22#ibcon#read 6, iclass 37, count 0 2006.201.15:14:34.22#ibcon#end of sib2, iclass 37, count 0 2006.201.15:14:34.22#ibcon#*after write, iclass 37, count 0 2006.201.15:14:34.22#ibcon#*before return 0, iclass 37, count 0 2006.201.15:14:34.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:34.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:14:34.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:14:34.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:14:34.22$vck44/vabw=wide 2006.201.15:14:34.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.15:14:34.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.15:14:34.22#ibcon#ireg 8 cls_cnt 0 2006.201.15:14:34.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:34.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:34.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:34.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.15:14:34.22#ibcon#first serial, iclass 39, count 0 2006.201.15:14:34.22#ibcon#enter sib2, iclass 39, count 0 2006.201.15:14:34.22#ibcon#flushed, iclass 39, count 0 2006.201.15:14:34.22#ibcon#about to write, iclass 39, count 0 2006.201.15:14:34.22#ibcon#wrote, iclass 39, count 0 2006.201.15:14:34.22#ibcon#about to read 3, iclass 39, count 0 2006.201.15:14:34.24#ibcon#read 3, iclass 39, count 0 2006.201.15:14:34.24#ibcon#about to read 4, iclass 39, count 0 2006.201.15:14:34.24#ibcon#read 4, iclass 39, count 0 2006.201.15:14:34.24#ibcon#about to read 5, iclass 39, count 0 2006.201.15:14:34.24#ibcon#read 5, iclass 39, count 0 2006.201.15:14:34.24#ibcon#about to read 6, iclass 39, count 0 2006.201.15:14:34.24#ibcon#read 6, iclass 39, count 0 2006.201.15:14:34.24#ibcon#end of sib2, iclass 39, count 0 2006.201.15:14:34.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.15:14:34.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.15:14:34.24#ibcon#[25=BW32\r\n] 2006.201.15:14:34.24#ibcon#*before write, iclass 39, count 0 2006.201.15:14:34.24#ibcon#enter sib2, iclass 39, count 0 2006.201.15:14:34.24#ibcon#flushed, iclass 39, count 0 2006.201.15:14:34.24#ibcon#about to write, iclass 39, count 0 2006.201.15:14:34.24#ibcon#wrote, iclass 39, count 0 2006.201.15:14:34.24#ibcon#about to read 3, iclass 39, count 0 2006.201.15:14:34.27#ibcon#read 3, iclass 39, count 0 2006.201.15:14:34.27#ibcon#about to read 4, iclass 39, count 0 2006.201.15:14:34.27#ibcon#read 4, iclass 39, count 0 2006.201.15:14:34.27#ibcon#about to read 5, iclass 39, count 0 2006.201.15:14:34.27#ibcon#read 5, iclass 39, count 0 2006.201.15:14:34.27#ibcon#about to read 6, iclass 39, count 0 2006.201.15:14:34.27#ibcon#read 6, iclass 39, count 0 2006.201.15:14:34.27#ibcon#end of sib2, iclass 39, count 0 2006.201.15:14:34.27#ibcon#*after write, iclass 39, count 0 2006.201.15:14:34.27#ibcon#*before return 0, iclass 39, count 0 2006.201.15:14:34.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:34.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.15:14:34.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.15:14:34.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.15:14:34.27$vck44/vbbw=wide 2006.201.15:14:34.27#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.15:14:34.27#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.15:14:34.27#ibcon#ireg 8 cls_cnt 0 2006.201.15:14:34.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:14:34.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:14:34.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:14:34.34#ibcon#enter wrdev, iclass 2, count 0 2006.201.15:14:34.34#ibcon#first serial, iclass 2, count 0 2006.201.15:14:34.34#ibcon#enter sib2, iclass 2, count 0 2006.201.15:14:34.34#ibcon#flushed, iclass 2, count 0 2006.201.15:14:34.34#ibcon#about to write, iclass 2, count 0 2006.201.15:14:34.34#ibcon#wrote, iclass 2, count 0 2006.201.15:14:34.34#ibcon#about to read 3, iclass 2, count 0 2006.201.15:14:34.36#ibcon#read 3, iclass 2, count 0 2006.201.15:14:34.36#ibcon#about to read 4, iclass 2, count 0 2006.201.15:14:34.36#ibcon#read 4, iclass 2, count 0 2006.201.15:14:34.36#ibcon#about to read 5, iclass 2, count 0 2006.201.15:14:34.36#ibcon#read 5, iclass 2, count 0 2006.201.15:14:34.36#ibcon#about to read 6, iclass 2, count 0 2006.201.15:14:34.36#ibcon#read 6, iclass 2, count 0 2006.201.15:14:34.36#ibcon#end of sib2, iclass 2, count 0 2006.201.15:14:34.36#ibcon#*mode == 0, iclass 2, count 0 2006.201.15:14:34.36#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.15:14:34.36#ibcon#[27=BW32\r\n] 2006.201.15:14:34.36#ibcon#*before write, iclass 2, count 0 2006.201.15:14:34.36#ibcon#enter sib2, iclass 2, count 0 2006.201.15:14:34.36#ibcon#flushed, iclass 2, count 0 2006.201.15:14:34.36#ibcon#about to write, iclass 2, count 0 2006.201.15:14:34.36#ibcon#wrote, iclass 2, count 0 2006.201.15:14:34.36#ibcon#about to read 3, iclass 2, count 0 2006.201.15:14:34.39#ibcon#read 3, iclass 2, count 0 2006.201.15:14:34.39#ibcon#about to read 4, iclass 2, count 0 2006.201.15:14:34.39#ibcon#read 4, iclass 2, count 0 2006.201.15:14:34.39#ibcon#about to read 5, iclass 2, count 0 2006.201.15:14:34.39#ibcon#read 5, iclass 2, count 0 2006.201.15:14:34.39#ibcon#about to read 6, iclass 2, count 0 2006.201.15:14:34.39#ibcon#read 6, iclass 2, count 0 2006.201.15:14:34.39#ibcon#end of sib2, iclass 2, count 0 2006.201.15:14:34.39#ibcon#*after write, iclass 2, count 0 2006.201.15:14:34.39#ibcon#*before return 0, iclass 2, count 0 2006.201.15:14:34.39#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:14:34.39#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:14:34.39#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.15:14:34.39#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.15:14:34.39$setupk4/ifdk4 2006.201.15:14:34.39$ifdk4/lo= 2006.201.15:14:34.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:14:34.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:14:34.39$ifdk4/patch= 2006.201.15:14:34.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:14:34.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:14:34.39$setupk4/!*+20s 2006.201.15:14:37.22#abcon#<5=/04 1.1 2.1 20.781001003.2\r\n> 2006.201.15:14:37.24#abcon#{5=INTERFACE CLEAR} 2006.201.15:14:37.30#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:14:47.39#abcon#<5=/04 1.1 2.1 20.781001003.2\r\n> 2006.201.15:14:47.41#abcon#{5=INTERFACE CLEAR} 2006.201.15:14:47.47#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:14:48.88$setupk4/"tpicd 2006.201.15:14:48.88$setupk4/echo=off 2006.201.15:14:48.88$setupk4/xlog=off 2006.201.15:14:48.88:!2006.201.15:20:09 2006.201.15:15:03.14#trakl#Source acquired 2006.201.15:15:04.14#flagr#flagr/antenna,acquired 2006.201.15:20:09.00:preob 2006.201.15:20:09.14/onsource/TRACKING 2006.201.15:20:09.14:!2006.201.15:20:19 2006.201.15:20:19.00:"tape 2006.201.15:20:19.00:"st=record 2006.201.15:20:19.00:data_valid=on 2006.201.15:20:19.00:midob 2006.201.15:20:19.14/onsource/TRACKING 2006.201.15:20:19.14/wx/20.80,1003.2,100 2006.201.15:20:19.32/cable/+6.4777E-03 2006.201.15:20:20.41/va/01,08,usb,yes,31,33 2006.201.15:20:20.41/va/02,07,usb,yes,33,34 2006.201.15:20:20.41/va/03,08,usb,yes,30,31 2006.201.15:20:20.41/va/04,07,usb,yes,34,36 2006.201.15:20:20.41/va/05,04,usb,yes,30,30 2006.201.15:20:20.41/va/06,05,usb,yes,30,30 2006.201.15:20:20.41/va/07,05,usb,yes,29,30 2006.201.15:20:20.41/va/08,04,usb,yes,29,35 2006.201.15:20:20.64/valo/01,524.99,yes,locked 2006.201.15:20:20.64/valo/02,534.99,yes,locked 2006.201.15:20:20.64/valo/03,564.99,yes,locked 2006.201.15:20:20.64/valo/04,624.99,yes,locked 2006.201.15:20:20.64/valo/05,734.99,yes,locked 2006.201.15:20:20.64/valo/06,814.99,yes,locked 2006.201.15:20:20.64/valo/07,864.99,yes,locked 2006.201.15:20:20.64/valo/08,884.99,yes,locked 2006.201.15:20:21.73/vb/01,04,usb,yes,30,28 2006.201.15:20:21.73/vb/02,05,usb,yes,28,28 2006.201.15:20:21.73/vb/03,04,usb,yes,29,32 2006.201.15:20:21.73/vb/04,05,usb,yes,29,28 2006.201.15:20:21.73/vb/05,04,usb,yes,26,28 2006.201.15:20:21.73/vb/06,04,usb,yes,30,26 2006.201.15:20:21.73/vb/07,04,usb,yes,30,30 2006.201.15:20:21.73/vb/08,04,usb,yes,28,31 2006.201.15:20:21.97/vblo/01,629.99,yes,locked 2006.201.15:20:21.97/vblo/02,634.99,yes,locked 2006.201.15:20:21.97/vblo/03,649.99,yes,locked 2006.201.15:20:21.97/vblo/04,679.99,yes,locked 2006.201.15:20:21.97/vblo/05,709.99,yes,locked 2006.201.15:20:21.97/vblo/06,719.99,yes,locked 2006.201.15:20:21.97/vblo/07,734.99,yes,locked 2006.201.15:20:21.97/vblo/08,744.99,yes,locked 2006.201.15:20:22.12/vabw/8 2006.201.15:20:22.27/vbbw/8 2006.201.15:20:22.38/xfe/off,on,13.7 2006.201.15:20:22.76/ifatt/23,28,28,28 2006.201.15:20:23.06/fmout-gps/S +4.56E-07 2006.201.15:20:23.13:!2006.201.15:20:59 2006.201.15:20:59.00:data_valid=off 2006.201.15:20:59.00:"et 2006.201.15:20:59.00:!+3s 2006.201.15:21:02.02:"tape 2006.201.15:21:02.02:postob 2006.201.15:21:02.08/cable/+6.4767E-03 2006.201.15:21:02.08/wx/20.80,1003.2,100 2006.201.15:21:02.14/fmout-gps/S +4.56E-07 2006.201.15:21:02.14:scan_name=201-1523,jd0607,520 2006.201.15:21:02.14:source=1418+546,141946.60,542314.8,2000.0,cw 2006.201.15:21:04.13#flagr#flagr/antenna,new-source 2006.201.15:21:04.13:checkk5 2006.201.15:21:04.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:21:04.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:21:05.24/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:21:05.61/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:21:05.97/chk_obsdata//k5ts1/T2011520??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.15:21:06.34/chk_obsdata//k5ts2/T2011520??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.15:21:06.70/chk_obsdata//k5ts3/T2011520??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.15:21:07.07/chk_obsdata//k5ts4/T2011520??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.15:21:07.76/k5log//k5ts1_log_newline 2006.201.15:21:08.46/k5log//k5ts2_log_newline 2006.201.15:21:09.14/k5log//k5ts3_log_newline 2006.201.15:21:09.83/k5log//k5ts4_log_newline 2006.201.15:21:09.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:21:09.85:setupk4=1 2006.201.15:21:09.85$setupk4/echo=on 2006.201.15:21:09.85$setupk4/pcalon 2006.201.15:21:09.85$pcalon/"no phase cal control is implemented here 2006.201.15:21:09.85$setupk4/"tpicd=stop 2006.201.15:21:09.85$setupk4/"rec=synch_on 2006.201.15:21:09.85$setupk4/"rec_mode=128 2006.201.15:21:09.86$setupk4/!* 2006.201.15:21:09.86$setupk4/recpk4 2006.201.15:21:09.86$recpk4/recpatch= 2006.201.15:21:09.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:21:09.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:21:09.86$setupk4/vck44 2006.201.15:21:09.86$vck44/valo=1,524.99 2006.201.15:21:09.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.15:21:09.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.15:21:09.86#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:09.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:09.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:09.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:09.86#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:21:09.86#ibcon#first serial, iclass 22, count 0 2006.201.15:21:09.86#ibcon#enter sib2, iclass 22, count 0 2006.201.15:21:09.86#ibcon#flushed, iclass 22, count 0 2006.201.15:21:09.86#ibcon#about to write, iclass 22, count 0 2006.201.15:21:09.86#ibcon#wrote, iclass 22, count 0 2006.201.15:21:09.86#ibcon#about to read 3, iclass 22, count 0 2006.201.15:21:09.90#ibcon#read 3, iclass 22, count 0 2006.201.15:21:09.90#ibcon#about to read 4, iclass 22, count 0 2006.201.15:21:09.90#ibcon#read 4, iclass 22, count 0 2006.201.15:21:09.90#ibcon#about to read 5, iclass 22, count 0 2006.201.15:21:09.90#ibcon#read 5, iclass 22, count 0 2006.201.15:21:09.90#ibcon#about to read 6, iclass 22, count 0 2006.201.15:21:09.90#ibcon#read 6, iclass 22, count 0 2006.201.15:21:09.90#ibcon#end of sib2, iclass 22, count 0 2006.201.15:21:09.90#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:21:09.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:21:09.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:21:09.90#ibcon#*before write, iclass 22, count 0 2006.201.15:21:09.90#ibcon#enter sib2, iclass 22, count 0 2006.201.15:21:09.90#ibcon#flushed, iclass 22, count 0 2006.201.15:21:09.90#ibcon#about to write, iclass 22, count 0 2006.201.15:21:09.90#ibcon#wrote, iclass 22, count 0 2006.201.15:21:09.90#ibcon#about to read 3, iclass 22, count 0 2006.201.15:21:09.95#ibcon#read 3, iclass 22, count 0 2006.201.15:21:09.95#ibcon#about to read 4, iclass 22, count 0 2006.201.15:21:09.95#ibcon#read 4, iclass 22, count 0 2006.201.15:21:09.95#ibcon#about to read 5, iclass 22, count 0 2006.201.15:21:09.95#ibcon#read 5, iclass 22, count 0 2006.201.15:21:09.95#ibcon#about to read 6, iclass 22, count 0 2006.201.15:21:09.95#ibcon#read 6, iclass 22, count 0 2006.201.15:21:09.95#ibcon#end of sib2, iclass 22, count 0 2006.201.15:21:09.95#ibcon#*after write, iclass 22, count 0 2006.201.15:21:09.95#ibcon#*before return 0, iclass 22, count 0 2006.201.15:21:09.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:09.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:09.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:21:09.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:21:09.95$vck44/va=1,8 2006.201.15:21:09.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.15:21:09.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.15:21:09.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:09.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:09.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:09.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:09.95#ibcon#enter wrdev, iclass 24, count 2 2006.201.15:21:09.95#ibcon#first serial, iclass 24, count 2 2006.201.15:21:09.95#ibcon#enter sib2, iclass 24, count 2 2006.201.15:21:09.95#ibcon#flushed, iclass 24, count 2 2006.201.15:21:09.95#ibcon#about to write, iclass 24, count 2 2006.201.15:21:09.95#ibcon#wrote, iclass 24, count 2 2006.201.15:21:09.95#ibcon#about to read 3, iclass 24, count 2 2006.201.15:21:09.97#ibcon#read 3, iclass 24, count 2 2006.201.15:21:09.97#ibcon#about to read 4, iclass 24, count 2 2006.201.15:21:09.97#ibcon#read 4, iclass 24, count 2 2006.201.15:21:09.97#ibcon#about to read 5, iclass 24, count 2 2006.201.15:21:09.97#ibcon#read 5, iclass 24, count 2 2006.201.15:21:09.97#ibcon#about to read 6, iclass 24, count 2 2006.201.15:21:09.97#ibcon#read 6, iclass 24, count 2 2006.201.15:21:09.97#ibcon#end of sib2, iclass 24, count 2 2006.201.15:21:09.97#ibcon#*mode == 0, iclass 24, count 2 2006.201.15:21:09.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.15:21:09.97#ibcon#[25=AT01-08\r\n] 2006.201.15:21:09.97#ibcon#*before write, iclass 24, count 2 2006.201.15:21:09.97#ibcon#enter sib2, iclass 24, count 2 2006.201.15:21:09.97#ibcon#flushed, iclass 24, count 2 2006.201.15:21:09.97#ibcon#about to write, iclass 24, count 2 2006.201.15:21:09.97#ibcon#wrote, iclass 24, count 2 2006.201.15:21:09.97#ibcon#about to read 3, iclass 24, count 2 2006.201.15:21:10.01#ibcon#read 3, iclass 24, count 2 2006.201.15:21:10.01#ibcon#about to read 4, iclass 24, count 2 2006.201.15:21:10.01#ibcon#read 4, iclass 24, count 2 2006.201.15:21:10.01#ibcon#about to read 5, iclass 24, count 2 2006.201.15:21:10.01#ibcon#read 5, iclass 24, count 2 2006.201.15:21:10.01#ibcon#about to read 6, iclass 24, count 2 2006.201.15:21:10.01#ibcon#read 6, iclass 24, count 2 2006.201.15:21:10.01#ibcon#end of sib2, iclass 24, count 2 2006.201.15:21:10.01#ibcon#*after write, iclass 24, count 2 2006.201.15:21:10.01#ibcon#*before return 0, iclass 24, count 2 2006.201.15:21:10.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:10.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:10.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.15:21:10.01#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:10.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:10.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:10.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:10.13#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:21:10.13#ibcon#first serial, iclass 24, count 0 2006.201.15:21:10.13#ibcon#enter sib2, iclass 24, count 0 2006.201.15:21:10.13#ibcon#flushed, iclass 24, count 0 2006.201.15:21:10.13#ibcon#about to write, iclass 24, count 0 2006.201.15:21:10.13#ibcon#wrote, iclass 24, count 0 2006.201.15:21:10.13#ibcon#about to read 3, iclass 24, count 0 2006.201.15:21:10.15#ibcon#read 3, iclass 24, count 0 2006.201.15:21:10.15#ibcon#about to read 4, iclass 24, count 0 2006.201.15:21:10.15#ibcon#read 4, iclass 24, count 0 2006.201.15:21:10.15#ibcon#about to read 5, iclass 24, count 0 2006.201.15:21:10.15#ibcon#read 5, iclass 24, count 0 2006.201.15:21:10.15#ibcon#about to read 6, iclass 24, count 0 2006.201.15:21:10.15#ibcon#read 6, iclass 24, count 0 2006.201.15:21:10.15#ibcon#end of sib2, iclass 24, count 0 2006.201.15:21:10.15#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:21:10.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:21:10.15#ibcon#[25=USB\r\n] 2006.201.15:21:10.15#ibcon#*before write, iclass 24, count 0 2006.201.15:21:10.15#ibcon#enter sib2, iclass 24, count 0 2006.201.15:21:10.15#ibcon#flushed, iclass 24, count 0 2006.201.15:21:10.15#ibcon#about to write, iclass 24, count 0 2006.201.15:21:10.15#ibcon#wrote, iclass 24, count 0 2006.201.15:21:10.15#ibcon#about to read 3, iclass 24, count 0 2006.201.15:21:10.18#ibcon#read 3, iclass 24, count 0 2006.201.15:21:10.18#ibcon#about to read 4, iclass 24, count 0 2006.201.15:21:10.18#ibcon#read 4, iclass 24, count 0 2006.201.15:21:10.18#ibcon#about to read 5, iclass 24, count 0 2006.201.15:21:10.18#ibcon#read 5, iclass 24, count 0 2006.201.15:21:10.18#ibcon#about to read 6, iclass 24, count 0 2006.201.15:21:10.18#ibcon#read 6, iclass 24, count 0 2006.201.15:21:10.18#ibcon#end of sib2, iclass 24, count 0 2006.201.15:21:10.18#ibcon#*after write, iclass 24, count 0 2006.201.15:21:10.18#ibcon#*before return 0, iclass 24, count 0 2006.201.15:21:10.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:10.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:10.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:21:10.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:21:10.18$vck44/valo=2,534.99 2006.201.15:21:10.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.15:21:10.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.15:21:10.18#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:10.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:10.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:10.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:10.18#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:21:10.18#ibcon#first serial, iclass 26, count 0 2006.201.15:21:10.18#ibcon#enter sib2, iclass 26, count 0 2006.201.15:21:10.18#ibcon#flushed, iclass 26, count 0 2006.201.15:21:10.18#ibcon#about to write, iclass 26, count 0 2006.201.15:21:10.18#ibcon#wrote, iclass 26, count 0 2006.201.15:21:10.18#ibcon#about to read 3, iclass 26, count 0 2006.201.15:21:10.20#ibcon#read 3, iclass 26, count 0 2006.201.15:21:10.20#ibcon#about to read 4, iclass 26, count 0 2006.201.15:21:10.20#ibcon#read 4, iclass 26, count 0 2006.201.15:21:10.20#ibcon#about to read 5, iclass 26, count 0 2006.201.15:21:10.20#ibcon#read 5, iclass 26, count 0 2006.201.15:21:10.20#ibcon#about to read 6, iclass 26, count 0 2006.201.15:21:10.20#ibcon#read 6, iclass 26, count 0 2006.201.15:21:10.20#ibcon#end of sib2, iclass 26, count 0 2006.201.15:21:10.20#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:21:10.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:21:10.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:21:10.20#ibcon#*before write, iclass 26, count 0 2006.201.15:21:10.20#ibcon#enter sib2, iclass 26, count 0 2006.201.15:21:10.20#ibcon#flushed, iclass 26, count 0 2006.201.15:21:10.20#ibcon#about to write, iclass 26, count 0 2006.201.15:21:10.20#ibcon#wrote, iclass 26, count 0 2006.201.15:21:10.20#ibcon#about to read 3, iclass 26, count 0 2006.201.15:21:10.25#ibcon#read 3, iclass 26, count 0 2006.201.15:21:10.25#ibcon#about to read 4, iclass 26, count 0 2006.201.15:21:10.25#ibcon#read 4, iclass 26, count 0 2006.201.15:21:10.25#ibcon#about to read 5, iclass 26, count 0 2006.201.15:21:10.25#ibcon#read 5, iclass 26, count 0 2006.201.15:21:10.25#ibcon#about to read 6, iclass 26, count 0 2006.201.15:21:10.25#ibcon#read 6, iclass 26, count 0 2006.201.15:21:10.25#ibcon#end of sib2, iclass 26, count 0 2006.201.15:21:10.25#ibcon#*after write, iclass 26, count 0 2006.201.15:21:10.25#ibcon#*before return 0, iclass 26, count 0 2006.201.15:21:10.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:10.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:10.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:21:10.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:21:10.25$vck44/va=2,7 2006.201.15:21:10.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.15:21:10.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.15:21:10.25#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:10.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:10.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:10.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:10.30#ibcon#enter wrdev, iclass 28, count 2 2006.201.15:21:10.30#ibcon#first serial, iclass 28, count 2 2006.201.15:21:10.30#ibcon#enter sib2, iclass 28, count 2 2006.201.15:21:10.30#ibcon#flushed, iclass 28, count 2 2006.201.15:21:10.30#ibcon#about to write, iclass 28, count 2 2006.201.15:21:10.30#ibcon#wrote, iclass 28, count 2 2006.201.15:21:10.30#ibcon#about to read 3, iclass 28, count 2 2006.201.15:21:10.32#ibcon#read 3, iclass 28, count 2 2006.201.15:21:10.32#ibcon#about to read 4, iclass 28, count 2 2006.201.15:21:10.32#ibcon#read 4, iclass 28, count 2 2006.201.15:21:10.32#ibcon#about to read 5, iclass 28, count 2 2006.201.15:21:10.32#ibcon#read 5, iclass 28, count 2 2006.201.15:21:10.32#ibcon#about to read 6, iclass 28, count 2 2006.201.15:21:10.32#ibcon#read 6, iclass 28, count 2 2006.201.15:21:10.32#ibcon#end of sib2, iclass 28, count 2 2006.201.15:21:10.32#ibcon#*mode == 0, iclass 28, count 2 2006.201.15:21:10.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.15:21:10.32#ibcon#[25=AT02-07\r\n] 2006.201.15:21:10.32#ibcon#*before write, iclass 28, count 2 2006.201.15:21:10.32#ibcon#enter sib2, iclass 28, count 2 2006.201.15:21:10.32#ibcon#flushed, iclass 28, count 2 2006.201.15:21:10.32#ibcon#about to write, iclass 28, count 2 2006.201.15:21:10.32#ibcon#wrote, iclass 28, count 2 2006.201.15:21:10.32#ibcon#about to read 3, iclass 28, count 2 2006.201.15:21:10.35#ibcon#read 3, iclass 28, count 2 2006.201.15:21:10.35#ibcon#about to read 4, iclass 28, count 2 2006.201.15:21:10.35#ibcon#read 4, iclass 28, count 2 2006.201.15:21:10.35#ibcon#about to read 5, iclass 28, count 2 2006.201.15:21:10.35#ibcon#read 5, iclass 28, count 2 2006.201.15:21:10.35#ibcon#about to read 6, iclass 28, count 2 2006.201.15:21:10.35#ibcon#read 6, iclass 28, count 2 2006.201.15:21:10.35#ibcon#end of sib2, iclass 28, count 2 2006.201.15:21:10.35#ibcon#*after write, iclass 28, count 2 2006.201.15:21:10.35#ibcon#*before return 0, iclass 28, count 2 2006.201.15:21:10.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:10.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:10.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.15:21:10.35#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:10.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:10.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:10.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:10.47#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:21:10.47#ibcon#first serial, iclass 28, count 0 2006.201.15:21:10.47#ibcon#enter sib2, iclass 28, count 0 2006.201.15:21:10.47#ibcon#flushed, iclass 28, count 0 2006.201.15:21:10.47#ibcon#about to write, iclass 28, count 0 2006.201.15:21:10.47#ibcon#wrote, iclass 28, count 0 2006.201.15:21:10.47#ibcon#about to read 3, iclass 28, count 0 2006.201.15:21:10.49#ibcon#read 3, iclass 28, count 0 2006.201.15:21:10.49#ibcon#about to read 4, iclass 28, count 0 2006.201.15:21:10.49#ibcon#read 4, iclass 28, count 0 2006.201.15:21:10.49#ibcon#about to read 5, iclass 28, count 0 2006.201.15:21:10.49#ibcon#read 5, iclass 28, count 0 2006.201.15:21:10.49#ibcon#about to read 6, iclass 28, count 0 2006.201.15:21:10.49#ibcon#read 6, iclass 28, count 0 2006.201.15:21:10.49#ibcon#end of sib2, iclass 28, count 0 2006.201.15:21:10.49#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:21:10.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:21:10.49#ibcon#[25=USB\r\n] 2006.201.15:21:10.49#ibcon#*before write, iclass 28, count 0 2006.201.15:21:10.49#ibcon#enter sib2, iclass 28, count 0 2006.201.15:21:10.49#ibcon#flushed, iclass 28, count 0 2006.201.15:21:10.49#ibcon#about to write, iclass 28, count 0 2006.201.15:21:10.49#ibcon#wrote, iclass 28, count 0 2006.201.15:21:10.49#ibcon#about to read 3, iclass 28, count 0 2006.201.15:21:10.52#ibcon#read 3, iclass 28, count 0 2006.201.15:21:10.52#ibcon#about to read 4, iclass 28, count 0 2006.201.15:21:10.52#ibcon#read 4, iclass 28, count 0 2006.201.15:21:10.52#ibcon#about to read 5, iclass 28, count 0 2006.201.15:21:10.52#ibcon#read 5, iclass 28, count 0 2006.201.15:21:10.52#ibcon#about to read 6, iclass 28, count 0 2006.201.15:21:10.52#ibcon#read 6, iclass 28, count 0 2006.201.15:21:10.52#ibcon#end of sib2, iclass 28, count 0 2006.201.15:21:10.52#ibcon#*after write, iclass 28, count 0 2006.201.15:21:10.52#ibcon#*before return 0, iclass 28, count 0 2006.201.15:21:10.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:10.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:10.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:21:10.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:21:10.52$vck44/valo=3,564.99 2006.201.15:21:10.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.15:21:10.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.15:21:10.52#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:10.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:10.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:10.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:10.52#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:21:10.52#ibcon#first serial, iclass 30, count 0 2006.201.15:21:10.52#ibcon#enter sib2, iclass 30, count 0 2006.201.15:21:10.52#ibcon#flushed, iclass 30, count 0 2006.201.15:21:10.52#ibcon#about to write, iclass 30, count 0 2006.201.15:21:10.52#ibcon#wrote, iclass 30, count 0 2006.201.15:21:10.52#ibcon#about to read 3, iclass 30, count 0 2006.201.15:21:10.54#ibcon#read 3, iclass 30, count 0 2006.201.15:21:10.54#ibcon#about to read 4, iclass 30, count 0 2006.201.15:21:10.54#ibcon#read 4, iclass 30, count 0 2006.201.15:21:10.54#ibcon#about to read 5, iclass 30, count 0 2006.201.15:21:10.54#ibcon#read 5, iclass 30, count 0 2006.201.15:21:10.54#ibcon#about to read 6, iclass 30, count 0 2006.201.15:21:10.54#ibcon#read 6, iclass 30, count 0 2006.201.15:21:10.54#ibcon#end of sib2, iclass 30, count 0 2006.201.15:21:10.54#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:21:10.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:21:10.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:21:10.54#ibcon#*before write, iclass 30, count 0 2006.201.15:21:10.54#ibcon#enter sib2, iclass 30, count 0 2006.201.15:21:10.54#ibcon#flushed, iclass 30, count 0 2006.201.15:21:10.54#ibcon#about to write, iclass 30, count 0 2006.201.15:21:10.54#ibcon#wrote, iclass 30, count 0 2006.201.15:21:10.54#ibcon#about to read 3, iclass 30, count 0 2006.201.15:21:10.59#ibcon#read 3, iclass 30, count 0 2006.201.15:21:10.59#ibcon#about to read 4, iclass 30, count 0 2006.201.15:21:10.59#ibcon#read 4, iclass 30, count 0 2006.201.15:21:10.59#ibcon#about to read 5, iclass 30, count 0 2006.201.15:21:10.59#ibcon#read 5, iclass 30, count 0 2006.201.15:21:10.59#ibcon#about to read 6, iclass 30, count 0 2006.201.15:21:10.59#ibcon#read 6, iclass 30, count 0 2006.201.15:21:10.59#ibcon#end of sib2, iclass 30, count 0 2006.201.15:21:10.59#ibcon#*after write, iclass 30, count 0 2006.201.15:21:10.59#ibcon#*before return 0, iclass 30, count 0 2006.201.15:21:10.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:10.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:10.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:21:10.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:21:10.59$vck44/va=3,8 2006.201.15:21:10.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.15:21:10.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.15:21:10.59#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:10.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:10.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:10.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:10.64#ibcon#enter wrdev, iclass 32, count 2 2006.201.15:21:10.64#ibcon#first serial, iclass 32, count 2 2006.201.15:21:10.64#ibcon#enter sib2, iclass 32, count 2 2006.201.15:21:10.64#ibcon#flushed, iclass 32, count 2 2006.201.15:21:10.64#ibcon#about to write, iclass 32, count 2 2006.201.15:21:10.64#ibcon#wrote, iclass 32, count 2 2006.201.15:21:10.64#ibcon#about to read 3, iclass 32, count 2 2006.201.15:21:10.66#ibcon#read 3, iclass 32, count 2 2006.201.15:21:10.66#ibcon#about to read 4, iclass 32, count 2 2006.201.15:21:10.66#ibcon#read 4, iclass 32, count 2 2006.201.15:21:10.66#ibcon#about to read 5, iclass 32, count 2 2006.201.15:21:10.66#ibcon#read 5, iclass 32, count 2 2006.201.15:21:10.66#ibcon#about to read 6, iclass 32, count 2 2006.201.15:21:10.66#ibcon#read 6, iclass 32, count 2 2006.201.15:21:10.66#ibcon#end of sib2, iclass 32, count 2 2006.201.15:21:10.66#ibcon#*mode == 0, iclass 32, count 2 2006.201.15:21:10.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.15:21:10.66#ibcon#[25=AT03-08\r\n] 2006.201.15:21:10.66#ibcon#*before write, iclass 32, count 2 2006.201.15:21:10.66#ibcon#enter sib2, iclass 32, count 2 2006.201.15:21:10.66#ibcon#flushed, iclass 32, count 2 2006.201.15:21:10.66#ibcon#about to write, iclass 32, count 2 2006.201.15:21:10.66#ibcon#wrote, iclass 32, count 2 2006.201.15:21:10.66#ibcon#about to read 3, iclass 32, count 2 2006.201.15:21:10.69#ibcon#read 3, iclass 32, count 2 2006.201.15:21:10.69#ibcon#about to read 4, iclass 32, count 2 2006.201.15:21:10.69#ibcon#read 4, iclass 32, count 2 2006.201.15:21:10.69#ibcon#about to read 5, iclass 32, count 2 2006.201.15:21:10.69#ibcon#read 5, iclass 32, count 2 2006.201.15:21:10.69#ibcon#about to read 6, iclass 32, count 2 2006.201.15:21:10.69#ibcon#read 6, iclass 32, count 2 2006.201.15:21:10.69#ibcon#end of sib2, iclass 32, count 2 2006.201.15:21:10.69#ibcon#*after write, iclass 32, count 2 2006.201.15:21:10.69#ibcon#*before return 0, iclass 32, count 2 2006.201.15:21:10.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:10.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:10.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.15:21:10.69#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:10.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:10.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:10.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:10.81#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:21:10.81#ibcon#first serial, iclass 32, count 0 2006.201.15:21:10.81#ibcon#enter sib2, iclass 32, count 0 2006.201.15:21:10.81#ibcon#flushed, iclass 32, count 0 2006.201.15:21:10.81#ibcon#about to write, iclass 32, count 0 2006.201.15:21:10.81#ibcon#wrote, iclass 32, count 0 2006.201.15:21:10.81#ibcon#about to read 3, iclass 32, count 0 2006.201.15:21:10.83#ibcon#read 3, iclass 32, count 0 2006.201.15:21:10.83#ibcon#about to read 4, iclass 32, count 0 2006.201.15:21:10.83#ibcon#read 4, iclass 32, count 0 2006.201.15:21:10.83#ibcon#about to read 5, iclass 32, count 0 2006.201.15:21:10.83#ibcon#read 5, iclass 32, count 0 2006.201.15:21:10.83#ibcon#about to read 6, iclass 32, count 0 2006.201.15:21:10.83#ibcon#read 6, iclass 32, count 0 2006.201.15:21:10.83#ibcon#end of sib2, iclass 32, count 0 2006.201.15:21:10.83#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:21:10.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:21:10.83#ibcon#[25=USB\r\n] 2006.201.15:21:10.83#ibcon#*before write, iclass 32, count 0 2006.201.15:21:10.83#ibcon#enter sib2, iclass 32, count 0 2006.201.15:21:10.83#ibcon#flushed, iclass 32, count 0 2006.201.15:21:10.83#ibcon#about to write, iclass 32, count 0 2006.201.15:21:10.83#ibcon#wrote, iclass 32, count 0 2006.201.15:21:10.83#ibcon#about to read 3, iclass 32, count 0 2006.201.15:21:10.86#ibcon#read 3, iclass 32, count 0 2006.201.15:21:10.86#ibcon#about to read 4, iclass 32, count 0 2006.201.15:21:10.86#ibcon#read 4, iclass 32, count 0 2006.201.15:21:10.86#ibcon#about to read 5, iclass 32, count 0 2006.201.15:21:10.86#ibcon#read 5, iclass 32, count 0 2006.201.15:21:10.86#ibcon#about to read 6, iclass 32, count 0 2006.201.15:21:10.86#ibcon#read 6, iclass 32, count 0 2006.201.15:21:10.86#ibcon#end of sib2, iclass 32, count 0 2006.201.15:21:10.86#ibcon#*after write, iclass 32, count 0 2006.201.15:21:10.86#ibcon#*before return 0, iclass 32, count 0 2006.201.15:21:10.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:10.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:10.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:21:10.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:21:10.86$vck44/valo=4,624.99 2006.201.15:21:10.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.15:21:10.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.15:21:10.86#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:10.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:10.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:10.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:10.86#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:21:10.86#ibcon#first serial, iclass 34, count 0 2006.201.15:21:10.86#ibcon#enter sib2, iclass 34, count 0 2006.201.15:21:10.86#ibcon#flushed, iclass 34, count 0 2006.201.15:21:10.86#ibcon#about to write, iclass 34, count 0 2006.201.15:21:10.86#ibcon#wrote, iclass 34, count 0 2006.201.15:21:10.86#ibcon#about to read 3, iclass 34, count 0 2006.201.15:21:10.88#ibcon#read 3, iclass 34, count 0 2006.201.15:21:10.88#ibcon#about to read 4, iclass 34, count 0 2006.201.15:21:10.88#ibcon#read 4, iclass 34, count 0 2006.201.15:21:10.88#ibcon#about to read 5, iclass 34, count 0 2006.201.15:21:10.88#ibcon#read 5, iclass 34, count 0 2006.201.15:21:10.88#ibcon#about to read 6, iclass 34, count 0 2006.201.15:21:10.88#ibcon#read 6, iclass 34, count 0 2006.201.15:21:10.88#ibcon#end of sib2, iclass 34, count 0 2006.201.15:21:10.88#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:21:10.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:21:10.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:21:10.88#ibcon#*before write, iclass 34, count 0 2006.201.15:21:10.88#ibcon#enter sib2, iclass 34, count 0 2006.201.15:21:10.88#ibcon#flushed, iclass 34, count 0 2006.201.15:21:10.88#ibcon#about to write, iclass 34, count 0 2006.201.15:21:10.88#ibcon#wrote, iclass 34, count 0 2006.201.15:21:10.88#ibcon#about to read 3, iclass 34, count 0 2006.201.15:21:10.93#ibcon#read 3, iclass 34, count 0 2006.201.15:21:10.93#ibcon#about to read 4, iclass 34, count 0 2006.201.15:21:10.93#ibcon#read 4, iclass 34, count 0 2006.201.15:21:10.93#ibcon#about to read 5, iclass 34, count 0 2006.201.15:21:10.93#ibcon#read 5, iclass 34, count 0 2006.201.15:21:10.93#ibcon#about to read 6, iclass 34, count 0 2006.201.15:21:10.93#ibcon#read 6, iclass 34, count 0 2006.201.15:21:10.93#ibcon#end of sib2, iclass 34, count 0 2006.201.15:21:10.93#ibcon#*after write, iclass 34, count 0 2006.201.15:21:10.93#ibcon#*before return 0, iclass 34, count 0 2006.201.15:21:10.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:10.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:10.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:21:10.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:21:10.93$vck44/va=4,7 2006.201.15:21:10.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.15:21:10.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.15:21:10.93#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:10.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:21:10.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:21:10.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:21:10.98#ibcon#enter wrdev, iclass 36, count 2 2006.201.15:21:10.98#ibcon#first serial, iclass 36, count 2 2006.201.15:21:10.98#ibcon#enter sib2, iclass 36, count 2 2006.201.15:21:10.98#ibcon#flushed, iclass 36, count 2 2006.201.15:21:10.98#ibcon#about to write, iclass 36, count 2 2006.201.15:21:10.98#ibcon#wrote, iclass 36, count 2 2006.201.15:21:10.98#ibcon#about to read 3, iclass 36, count 2 2006.201.15:21:11.00#ibcon#read 3, iclass 36, count 2 2006.201.15:21:11.00#ibcon#about to read 4, iclass 36, count 2 2006.201.15:21:11.00#ibcon#read 4, iclass 36, count 2 2006.201.15:21:11.00#ibcon#about to read 5, iclass 36, count 2 2006.201.15:21:11.00#ibcon#read 5, iclass 36, count 2 2006.201.15:21:11.00#ibcon#about to read 6, iclass 36, count 2 2006.201.15:21:11.00#ibcon#read 6, iclass 36, count 2 2006.201.15:21:11.00#ibcon#end of sib2, iclass 36, count 2 2006.201.15:21:11.00#ibcon#*mode == 0, iclass 36, count 2 2006.201.15:21:11.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.15:21:11.00#ibcon#[25=AT04-07\r\n] 2006.201.15:21:11.00#ibcon#*before write, iclass 36, count 2 2006.201.15:21:11.00#ibcon#enter sib2, iclass 36, count 2 2006.201.15:21:11.00#ibcon#flushed, iclass 36, count 2 2006.201.15:21:11.00#ibcon#about to write, iclass 36, count 2 2006.201.15:21:11.00#ibcon#wrote, iclass 36, count 2 2006.201.15:21:11.00#ibcon#about to read 3, iclass 36, count 2 2006.201.15:21:11.03#ibcon#read 3, iclass 36, count 2 2006.201.15:21:11.03#ibcon#about to read 4, iclass 36, count 2 2006.201.15:21:11.03#ibcon#read 4, iclass 36, count 2 2006.201.15:21:11.03#ibcon#about to read 5, iclass 36, count 2 2006.201.15:21:11.03#ibcon#read 5, iclass 36, count 2 2006.201.15:21:11.03#ibcon#about to read 6, iclass 36, count 2 2006.201.15:21:11.03#ibcon#read 6, iclass 36, count 2 2006.201.15:21:11.03#ibcon#end of sib2, iclass 36, count 2 2006.201.15:21:11.03#ibcon#*after write, iclass 36, count 2 2006.201.15:21:11.03#ibcon#*before return 0, iclass 36, count 2 2006.201.15:21:11.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:21:11.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:21:11.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.15:21:11.03#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:11.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:21:11.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:21:11.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:21:11.15#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:21:11.15#ibcon#first serial, iclass 36, count 0 2006.201.15:21:11.15#ibcon#enter sib2, iclass 36, count 0 2006.201.15:21:11.15#ibcon#flushed, iclass 36, count 0 2006.201.15:21:11.15#ibcon#about to write, iclass 36, count 0 2006.201.15:21:11.15#ibcon#wrote, iclass 36, count 0 2006.201.15:21:11.15#ibcon#about to read 3, iclass 36, count 0 2006.201.15:21:11.17#ibcon#read 3, iclass 36, count 0 2006.201.15:21:11.17#ibcon#about to read 4, iclass 36, count 0 2006.201.15:21:11.17#ibcon#read 4, iclass 36, count 0 2006.201.15:21:11.17#ibcon#about to read 5, iclass 36, count 0 2006.201.15:21:11.17#ibcon#read 5, iclass 36, count 0 2006.201.15:21:11.17#ibcon#about to read 6, iclass 36, count 0 2006.201.15:21:11.17#ibcon#read 6, iclass 36, count 0 2006.201.15:21:11.17#ibcon#end of sib2, iclass 36, count 0 2006.201.15:21:11.17#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:21:11.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:21:11.17#ibcon#[25=USB\r\n] 2006.201.15:21:11.17#ibcon#*before write, iclass 36, count 0 2006.201.15:21:11.17#ibcon#enter sib2, iclass 36, count 0 2006.201.15:21:11.17#ibcon#flushed, iclass 36, count 0 2006.201.15:21:11.17#ibcon#about to write, iclass 36, count 0 2006.201.15:21:11.17#ibcon#wrote, iclass 36, count 0 2006.201.15:21:11.17#ibcon#about to read 3, iclass 36, count 0 2006.201.15:21:11.20#ibcon#read 3, iclass 36, count 0 2006.201.15:21:11.20#ibcon#about to read 4, iclass 36, count 0 2006.201.15:21:11.20#ibcon#read 4, iclass 36, count 0 2006.201.15:21:11.20#ibcon#about to read 5, iclass 36, count 0 2006.201.15:21:11.20#ibcon#read 5, iclass 36, count 0 2006.201.15:21:11.20#ibcon#about to read 6, iclass 36, count 0 2006.201.15:21:11.20#ibcon#read 6, iclass 36, count 0 2006.201.15:21:11.20#ibcon#end of sib2, iclass 36, count 0 2006.201.15:21:11.20#ibcon#*after write, iclass 36, count 0 2006.201.15:21:11.20#ibcon#*before return 0, iclass 36, count 0 2006.201.15:21:11.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:21:11.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:21:11.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:21:11.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:21:11.20$vck44/valo=5,734.99 2006.201.15:21:11.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.15:21:11.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.15:21:11.20#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:11.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:21:11.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:21:11.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:21:11.20#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:21:11.20#ibcon#first serial, iclass 38, count 0 2006.201.15:21:11.20#ibcon#enter sib2, iclass 38, count 0 2006.201.15:21:11.20#ibcon#flushed, iclass 38, count 0 2006.201.15:21:11.20#ibcon#about to write, iclass 38, count 0 2006.201.15:21:11.20#ibcon#wrote, iclass 38, count 0 2006.201.15:21:11.20#ibcon#about to read 3, iclass 38, count 0 2006.201.15:21:11.22#ibcon#read 3, iclass 38, count 0 2006.201.15:21:11.22#ibcon#about to read 4, iclass 38, count 0 2006.201.15:21:11.22#ibcon#read 4, iclass 38, count 0 2006.201.15:21:11.22#ibcon#about to read 5, iclass 38, count 0 2006.201.15:21:11.22#ibcon#read 5, iclass 38, count 0 2006.201.15:21:11.22#ibcon#about to read 6, iclass 38, count 0 2006.201.15:21:11.22#ibcon#read 6, iclass 38, count 0 2006.201.15:21:11.22#ibcon#end of sib2, iclass 38, count 0 2006.201.15:21:11.22#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:21:11.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:21:11.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:21:11.22#ibcon#*before write, iclass 38, count 0 2006.201.15:21:11.22#ibcon#enter sib2, iclass 38, count 0 2006.201.15:21:11.22#ibcon#flushed, iclass 38, count 0 2006.201.15:21:11.22#ibcon#about to write, iclass 38, count 0 2006.201.15:21:11.22#ibcon#wrote, iclass 38, count 0 2006.201.15:21:11.22#ibcon#about to read 3, iclass 38, count 0 2006.201.15:21:11.26#ibcon#read 3, iclass 38, count 0 2006.201.15:21:11.26#ibcon#about to read 4, iclass 38, count 0 2006.201.15:21:11.26#ibcon#read 4, iclass 38, count 0 2006.201.15:21:11.26#ibcon#about to read 5, iclass 38, count 0 2006.201.15:21:11.26#ibcon#read 5, iclass 38, count 0 2006.201.15:21:11.26#ibcon#about to read 6, iclass 38, count 0 2006.201.15:21:11.26#ibcon#read 6, iclass 38, count 0 2006.201.15:21:11.26#ibcon#end of sib2, iclass 38, count 0 2006.201.15:21:11.26#ibcon#*after write, iclass 38, count 0 2006.201.15:21:11.26#ibcon#*before return 0, iclass 38, count 0 2006.201.15:21:11.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:21:11.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:21:11.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:21:11.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:21:11.26$vck44/va=5,4 2006.201.15:21:11.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.15:21:11.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.15:21:11.26#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:11.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:21:11.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:21:11.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:21:11.32#ibcon#enter wrdev, iclass 40, count 2 2006.201.15:21:11.32#ibcon#first serial, iclass 40, count 2 2006.201.15:21:11.32#ibcon#enter sib2, iclass 40, count 2 2006.201.15:21:11.32#ibcon#flushed, iclass 40, count 2 2006.201.15:21:11.32#ibcon#about to write, iclass 40, count 2 2006.201.15:21:11.32#ibcon#wrote, iclass 40, count 2 2006.201.15:21:11.32#ibcon#about to read 3, iclass 40, count 2 2006.201.15:21:11.34#ibcon#read 3, iclass 40, count 2 2006.201.15:21:11.34#ibcon#about to read 4, iclass 40, count 2 2006.201.15:21:11.34#ibcon#read 4, iclass 40, count 2 2006.201.15:21:11.34#ibcon#about to read 5, iclass 40, count 2 2006.201.15:21:11.34#ibcon#read 5, iclass 40, count 2 2006.201.15:21:11.34#ibcon#about to read 6, iclass 40, count 2 2006.201.15:21:11.34#ibcon#read 6, iclass 40, count 2 2006.201.15:21:11.34#ibcon#end of sib2, iclass 40, count 2 2006.201.15:21:11.34#ibcon#*mode == 0, iclass 40, count 2 2006.201.15:21:11.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.15:21:11.34#ibcon#[25=AT05-04\r\n] 2006.201.15:21:11.34#ibcon#*before write, iclass 40, count 2 2006.201.15:21:11.34#ibcon#enter sib2, iclass 40, count 2 2006.201.15:21:11.34#ibcon#flushed, iclass 40, count 2 2006.201.15:21:11.34#ibcon#about to write, iclass 40, count 2 2006.201.15:21:11.34#ibcon#wrote, iclass 40, count 2 2006.201.15:21:11.34#ibcon#about to read 3, iclass 40, count 2 2006.201.15:21:11.37#ibcon#read 3, iclass 40, count 2 2006.201.15:21:11.37#ibcon#about to read 4, iclass 40, count 2 2006.201.15:21:11.37#ibcon#read 4, iclass 40, count 2 2006.201.15:21:11.37#ibcon#about to read 5, iclass 40, count 2 2006.201.15:21:11.37#ibcon#read 5, iclass 40, count 2 2006.201.15:21:11.37#ibcon#about to read 6, iclass 40, count 2 2006.201.15:21:11.37#ibcon#read 6, iclass 40, count 2 2006.201.15:21:11.37#ibcon#end of sib2, iclass 40, count 2 2006.201.15:21:11.37#ibcon#*after write, iclass 40, count 2 2006.201.15:21:11.37#ibcon#*before return 0, iclass 40, count 2 2006.201.15:21:11.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:21:11.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:21:11.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.15:21:11.37#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:11.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:21:11.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:21:11.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:21:11.49#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:21:11.49#ibcon#first serial, iclass 40, count 0 2006.201.15:21:11.49#ibcon#enter sib2, iclass 40, count 0 2006.201.15:21:11.49#ibcon#flushed, iclass 40, count 0 2006.201.15:21:11.49#ibcon#about to write, iclass 40, count 0 2006.201.15:21:11.49#ibcon#wrote, iclass 40, count 0 2006.201.15:21:11.49#ibcon#about to read 3, iclass 40, count 0 2006.201.15:21:11.51#ibcon#read 3, iclass 40, count 0 2006.201.15:21:11.51#ibcon#about to read 4, iclass 40, count 0 2006.201.15:21:11.51#ibcon#read 4, iclass 40, count 0 2006.201.15:21:11.51#ibcon#about to read 5, iclass 40, count 0 2006.201.15:21:11.51#ibcon#read 5, iclass 40, count 0 2006.201.15:21:11.51#ibcon#about to read 6, iclass 40, count 0 2006.201.15:21:11.51#ibcon#read 6, iclass 40, count 0 2006.201.15:21:11.51#ibcon#end of sib2, iclass 40, count 0 2006.201.15:21:11.51#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:21:11.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:21:11.51#ibcon#[25=USB\r\n] 2006.201.15:21:11.51#ibcon#*before write, iclass 40, count 0 2006.201.15:21:11.51#ibcon#enter sib2, iclass 40, count 0 2006.201.15:21:11.51#ibcon#flushed, iclass 40, count 0 2006.201.15:21:11.51#ibcon#about to write, iclass 40, count 0 2006.201.15:21:11.51#ibcon#wrote, iclass 40, count 0 2006.201.15:21:11.51#ibcon#about to read 3, iclass 40, count 0 2006.201.15:21:11.54#ibcon#read 3, iclass 40, count 0 2006.201.15:21:11.54#ibcon#about to read 4, iclass 40, count 0 2006.201.15:21:11.54#ibcon#read 4, iclass 40, count 0 2006.201.15:21:11.54#ibcon#about to read 5, iclass 40, count 0 2006.201.15:21:11.54#ibcon#read 5, iclass 40, count 0 2006.201.15:21:11.54#ibcon#about to read 6, iclass 40, count 0 2006.201.15:21:11.54#ibcon#read 6, iclass 40, count 0 2006.201.15:21:11.54#ibcon#end of sib2, iclass 40, count 0 2006.201.15:21:11.54#ibcon#*after write, iclass 40, count 0 2006.201.15:21:11.54#ibcon#*before return 0, iclass 40, count 0 2006.201.15:21:11.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:21:11.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:21:11.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:21:11.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:21:11.54$vck44/valo=6,814.99 2006.201.15:21:11.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.15:21:11.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.15:21:11.54#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:11.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:11.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:11.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:11.54#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:21:11.54#ibcon#first serial, iclass 4, count 0 2006.201.15:21:11.54#ibcon#enter sib2, iclass 4, count 0 2006.201.15:21:11.54#ibcon#flushed, iclass 4, count 0 2006.201.15:21:11.54#ibcon#about to write, iclass 4, count 0 2006.201.15:21:11.54#ibcon#wrote, iclass 4, count 0 2006.201.15:21:11.54#ibcon#about to read 3, iclass 4, count 0 2006.201.15:21:11.56#ibcon#read 3, iclass 4, count 0 2006.201.15:21:11.56#ibcon#about to read 4, iclass 4, count 0 2006.201.15:21:11.56#ibcon#read 4, iclass 4, count 0 2006.201.15:21:11.56#ibcon#about to read 5, iclass 4, count 0 2006.201.15:21:11.56#ibcon#read 5, iclass 4, count 0 2006.201.15:21:11.56#ibcon#about to read 6, iclass 4, count 0 2006.201.15:21:11.56#ibcon#read 6, iclass 4, count 0 2006.201.15:21:11.56#ibcon#end of sib2, iclass 4, count 0 2006.201.15:21:11.56#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:21:11.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:21:11.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:21:11.56#ibcon#*before write, iclass 4, count 0 2006.201.15:21:11.56#ibcon#enter sib2, iclass 4, count 0 2006.201.15:21:11.56#ibcon#flushed, iclass 4, count 0 2006.201.15:21:11.56#ibcon#about to write, iclass 4, count 0 2006.201.15:21:11.56#ibcon#wrote, iclass 4, count 0 2006.201.15:21:11.56#ibcon#about to read 3, iclass 4, count 0 2006.201.15:21:11.61#ibcon#read 3, iclass 4, count 0 2006.201.15:21:11.61#ibcon#about to read 4, iclass 4, count 0 2006.201.15:21:11.61#ibcon#read 4, iclass 4, count 0 2006.201.15:21:11.61#ibcon#about to read 5, iclass 4, count 0 2006.201.15:21:11.61#ibcon#read 5, iclass 4, count 0 2006.201.15:21:11.61#ibcon#about to read 6, iclass 4, count 0 2006.201.15:21:11.61#ibcon#read 6, iclass 4, count 0 2006.201.15:21:11.61#ibcon#end of sib2, iclass 4, count 0 2006.201.15:21:11.61#ibcon#*after write, iclass 4, count 0 2006.201.15:21:11.61#ibcon#*before return 0, iclass 4, count 0 2006.201.15:21:11.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:11.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:11.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:21:11.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:21:11.61$vck44/va=6,5 2006.201.15:21:11.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.15:21:11.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.15:21:11.61#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:11.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:11.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:11.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:11.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.15:21:11.66#ibcon#first serial, iclass 6, count 2 2006.201.15:21:11.66#ibcon#enter sib2, iclass 6, count 2 2006.201.15:21:11.66#ibcon#flushed, iclass 6, count 2 2006.201.15:21:11.66#ibcon#about to write, iclass 6, count 2 2006.201.15:21:11.66#ibcon#wrote, iclass 6, count 2 2006.201.15:21:11.66#ibcon#about to read 3, iclass 6, count 2 2006.201.15:21:11.68#ibcon#read 3, iclass 6, count 2 2006.201.15:21:11.68#ibcon#about to read 4, iclass 6, count 2 2006.201.15:21:11.68#ibcon#read 4, iclass 6, count 2 2006.201.15:21:11.68#ibcon#about to read 5, iclass 6, count 2 2006.201.15:21:11.68#ibcon#read 5, iclass 6, count 2 2006.201.15:21:11.68#ibcon#about to read 6, iclass 6, count 2 2006.201.15:21:11.68#ibcon#read 6, iclass 6, count 2 2006.201.15:21:11.68#ibcon#end of sib2, iclass 6, count 2 2006.201.15:21:11.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.15:21:11.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.15:21:11.68#ibcon#[25=AT06-05\r\n] 2006.201.15:21:11.68#ibcon#*before write, iclass 6, count 2 2006.201.15:21:11.68#ibcon#enter sib2, iclass 6, count 2 2006.201.15:21:11.68#ibcon#flushed, iclass 6, count 2 2006.201.15:21:11.68#ibcon#about to write, iclass 6, count 2 2006.201.15:21:11.68#ibcon#wrote, iclass 6, count 2 2006.201.15:21:11.68#ibcon#about to read 3, iclass 6, count 2 2006.201.15:21:11.71#ibcon#read 3, iclass 6, count 2 2006.201.15:21:11.71#ibcon#about to read 4, iclass 6, count 2 2006.201.15:21:11.71#ibcon#read 4, iclass 6, count 2 2006.201.15:21:11.71#ibcon#about to read 5, iclass 6, count 2 2006.201.15:21:11.71#ibcon#read 5, iclass 6, count 2 2006.201.15:21:11.71#ibcon#about to read 6, iclass 6, count 2 2006.201.15:21:11.71#ibcon#read 6, iclass 6, count 2 2006.201.15:21:11.71#ibcon#end of sib2, iclass 6, count 2 2006.201.15:21:11.71#ibcon#*after write, iclass 6, count 2 2006.201.15:21:11.71#ibcon#*before return 0, iclass 6, count 2 2006.201.15:21:11.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:11.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:11.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.15:21:11.71#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:11.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:11.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:11.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:11.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:21:11.83#ibcon#first serial, iclass 6, count 0 2006.201.15:21:11.83#ibcon#enter sib2, iclass 6, count 0 2006.201.15:21:11.83#ibcon#flushed, iclass 6, count 0 2006.201.15:21:11.83#ibcon#about to write, iclass 6, count 0 2006.201.15:21:11.83#ibcon#wrote, iclass 6, count 0 2006.201.15:21:11.83#ibcon#about to read 3, iclass 6, count 0 2006.201.15:21:11.85#ibcon#read 3, iclass 6, count 0 2006.201.15:21:11.85#ibcon#about to read 4, iclass 6, count 0 2006.201.15:21:11.85#ibcon#read 4, iclass 6, count 0 2006.201.15:21:11.85#ibcon#about to read 5, iclass 6, count 0 2006.201.15:21:11.85#ibcon#read 5, iclass 6, count 0 2006.201.15:21:11.85#ibcon#about to read 6, iclass 6, count 0 2006.201.15:21:11.85#ibcon#read 6, iclass 6, count 0 2006.201.15:21:11.85#ibcon#end of sib2, iclass 6, count 0 2006.201.15:21:11.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:21:11.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:21:11.85#ibcon#[25=USB\r\n] 2006.201.15:21:11.85#ibcon#*before write, iclass 6, count 0 2006.201.15:21:11.85#ibcon#enter sib2, iclass 6, count 0 2006.201.15:21:11.85#ibcon#flushed, iclass 6, count 0 2006.201.15:21:11.85#ibcon#about to write, iclass 6, count 0 2006.201.15:21:11.85#ibcon#wrote, iclass 6, count 0 2006.201.15:21:11.85#ibcon#about to read 3, iclass 6, count 0 2006.201.15:21:11.88#ibcon#read 3, iclass 6, count 0 2006.201.15:21:11.88#ibcon#about to read 4, iclass 6, count 0 2006.201.15:21:11.88#ibcon#read 4, iclass 6, count 0 2006.201.15:21:11.88#ibcon#about to read 5, iclass 6, count 0 2006.201.15:21:11.88#ibcon#read 5, iclass 6, count 0 2006.201.15:21:11.88#ibcon#about to read 6, iclass 6, count 0 2006.201.15:21:11.88#ibcon#read 6, iclass 6, count 0 2006.201.15:21:11.88#ibcon#end of sib2, iclass 6, count 0 2006.201.15:21:11.88#ibcon#*after write, iclass 6, count 0 2006.201.15:21:11.88#ibcon#*before return 0, iclass 6, count 0 2006.201.15:21:11.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:11.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:11.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:21:11.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:21:11.88$vck44/valo=7,864.99 2006.201.15:21:11.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.15:21:11.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.15:21:11.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:11.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:11.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:11.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:11.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:21:11.88#ibcon#first serial, iclass 10, count 0 2006.201.15:21:11.88#ibcon#enter sib2, iclass 10, count 0 2006.201.15:21:11.88#ibcon#flushed, iclass 10, count 0 2006.201.15:21:11.88#ibcon#about to write, iclass 10, count 0 2006.201.15:21:11.88#ibcon#wrote, iclass 10, count 0 2006.201.15:21:11.88#ibcon#about to read 3, iclass 10, count 0 2006.201.15:21:11.90#ibcon#read 3, iclass 10, count 0 2006.201.15:21:11.90#ibcon#about to read 4, iclass 10, count 0 2006.201.15:21:11.90#ibcon#read 4, iclass 10, count 0 2006.201.15:21:11.90#ibcon#about to read 5, iclass 10, count 0 2006.201.15:21:11.90#ibcon#read 5, iclass 10, count 0 2006.201.15:21:11.90#ibcon#about to read 6, iclass 10, count 0 2006.201.15:21:11.90#ibcon#read 6, iclass 10, count 0 2006.201.15:21:11.90#ibcon#end of sib2, iclass 10, count 0 2006.201.15:21:11.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:21:11.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:21:11.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:21:11.90#ibcon#*before write, iclass 10, count 0 2006.201.15:21:11.90#ibcon#enter sib2, iclass 10, count 0 2006.201.15:21:11.90#ibcon#flushed, iclass 10, count 0 2006.201.15:21:11.90#ibcon#about to write, iclass 10, count 0 2006.201.15:21:11.90#ibcon#wrote, iclass 10, count 0 2006.201.15:21:11.90#ibcon#about to read 3, iclass 10, count 0 2006.201.15:21:11.94#ibcon#read 3, iclass 10, count 0 2006.201.15:21:11.94#ibcon#about to read 4, iclass 10, count 0 2006.201.15:21:11.94#ibcon#read 4, iclass 10, count 0 2006.201.15:21:11.94#ibcon#about to read 5, iclass 10, count 0 2006.201.15:21:11.94#ibcon#read 5, iclass 10, count 0 2006.201.15:21:11.94#ibcon#about to read 6, iclass 10, count 0 2006.201.15:21:11.94#ibcon#read 6, iclass 10, count 0 2006.201.15:21:11.94#ibcon#end of sib2, iclass 10, count 0 2006.201.15:21:11.94#ibcon#*after write, iclass 10, count 0 2006.201.15:21:11.94#ibcon#*before return 0, iclass 10, count 0 2006.201.15:21:11.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:11.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:11.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:21:11.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:21:11.94$vck44/va=7,5 2006.201.15:21:11.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.15:21:11.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.15:21:11.94#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:11.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:12.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:12.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:12.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.15:21:12.00#ibcon#first serial, iclass 12, count 2 2006.201.15:21:12.00#ibcon#enter sib2, iclass 12, count 2 2006.201.15:21:12.00#ibcon#flushed, iclass 12, count 2 2006.201.15:21:12.00#ibcon#about to write, iclass 12, count 2 2006.201.15:21:12.00#ibcon#wrote, iclass 12, count 2 2006.201.15:21:12.00#ibcon#about to read 3, iclass 12, count 2 2006.201.15:21:12.02#ibcon#read 3, iclass 12, count 2 2006.201.15:21:12.02#ibcon#about to read 4, iclass 12, count 2 2006.201.15:21:12.02#ibcon#read 4, iclass 12, count 2 2006.201.15:21:12.02#ibcon#about to read 5, iclass 12, count 2 2006.201.15:21:12.02#ibcon#read 5, iclass 12, count 2 2006.201.15:21:12.02#ibcon#about to read 6, iclass 12, count 2 2006.201.15:21:12.02#ibcon#read 6, iclass 12, count 2 2006.201.15:21:12.02#ibcon#end of sib2, iclass 12, count 2 2006.201.15:21:12.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.15:21:12.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.15:21:12.02#ibcon#[25=AT07-05\r\n] 2006.201.15:21:12.02#ibcon#*before write, iclass 12, count 2 2006.201.15:21:12.02#ibcon#enter sib2, iclass 12, count 2 2006.201.15:21:12.02#ibcon#flushed, iclass 12, count 2 2006.201.15:21:12.02#ibcon#about to write, iclass 12, count 2 2006.201.15:21:12.02#ibcon#wrote, iclass 12, count 2 2006.201.15:21:12.02#ibcon#about to read 3, iclass 12, count 2 2006.201.15:21:12.05#ibcon#read 3, iclass 12, count 2 2006.201.15:21:12.05#ibcon#about to read 4, iclass 12, count 2 2006.201.15:21:12.05#ibcon#read 4, iclass 12, count 2 2006.201.15:21:12.05#ibcon#about to read 5, iclass 12, count 2 2006.201.15:21:12.05#ibcon#read 5, iclass 12, count 2 2006.201.15:21:12.05#ibcon#about to read 6, iclass 12, count 2 2006.201.15:21:12.05#ibcon#read 6, iclass 12, count 2 2006.201.15:21:12.05#ibcon#end of sib2, iclass 12, count 2 2006.201.15:21:12.05#ibcon#*after write, iclass 12, count 2 2006.201.15:21:12.05#ibcon#*before return 0, iclass 12, count 2 2006.201.15:21:12.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:12.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:12.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.15:21:12.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:12.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:12.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:12.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:12.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:21:12.17#ibcon#first serial, iclass 12, count 0 2006.201.15:21:12.17#ibcon#enter sib2, iclass 12, count 0 2006.201.15:21:12.17#ibcon#flushed, iclass 12, count 0 2006.201.15:21:12.17#ibcon#about to write, iclass 12, count 0 2006.201.15:21:12.17#ibcon#wrote, iclass 12, count 0 2006.201.15:21:12.17#ibcon#about to read 3, iclass 12, count 0 2006.201.15:21:12.20#ibcon#read 3, iclass 12, count 0 2006.201.15:21:12.20#ibcon#about to read 4, iclass 12, count 0 2006.201.15:21:12.20#ibcon#read 4, iclass 12, count 0 2006.201.15:21:12.20#ibcon#about to read 5, iclass 12, count 0 2006.201.15:21:12.20#ibcon#read 5, iclass 12, count 0 2006.201.15:21:12.20#ibcon#about to read 6, iclass 12, count 0 2006.201.15:21:12.20#ibcon#read 6, iclass 12, count 0 2006.201.15:21:12.20#ibcon#end of sib2, iclass 12, count 0 2006.201.15:21:12.20#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:21:12.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:21:12.20#ibcon#[25=USB\r\n] 2006.201.15:21:12.20#ibcon#*before write, iclass 12, count 0 2006.201.15:21:12.20#ibcon#enter sib2, iclass 12, count 0 2006.201.15:21:12.20#ibcon#flushed, iclass 12, count 0 2006.201.15:21:12.20#ibcon#about to write, iclass 12, count 0 2006.201.15:21:12.20#ibcon#wrote, iclass 12, count 0 2006.201.15:21:12.20#ibcon#about to read 3, iclass 12, count 0 2006.201.15:21:12.23#ibcon#read 3, iclass 12, count 0 2006.201.15:21:12.23#ibcon#about to read 4, iclass 12, count 0 2006.201.15:21:12.23#ibcon#read 4, iclass 12, count 0 2006.201.15:21:12.23#ibcon#about to read 5, iclass 12, count 0 2006.201.15:21:12.23#ibcon#read 5, iclass 12, count 0 2006.201.15:21:12.23#ibcon#about to read 6, iclass 12, count 0 2006.201.15:21:12.23#ibcon#read 6, iclass 12, count 0 2006.201.15:21:12.23#ibcon#end of sib2, iclass 12, count 0 2006.201.15:21:12.23#ibcon#*after write, iclass 12, count 0 2006.201.15:21:12.23#ibcon#*before return 0, iclass 12, count 0 2006.201.15:21:12.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:12.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:12.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:21:12.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:21:12.23$vck44/valo=8,884.99 2006.201.15:21:12.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.15:21:12.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.15:21:12.23#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:12.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:12.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:12.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:12.23#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:21:12.23#ibcon#first serial, iclass 14, count 0 2006.201.15:21:12.23#ibcon#enter sib2, iclass 14, count 0 2006.201.15:21:12.23#ibcon#flushed, iclass 14, count 0 2006.201.15:21:12.23#ibcon#about to write, iclass 14, count 0 2006.201.15:21:12.23#ibcon#wrote, iclass 14, count 0 2006.201.15:21:12.23#ibcon#about to read 3, iclass 14, count 0 2006.201.15:21:12.25#ibcon#read 3, iclass 14, count 0 2006.201.15:21:12.25#ibcon#about to read 4, iclass 14, count 0 2006.201.15:21:12.25#ibcon#read 4, iclass 14, count 0 2006.201.15:21:12.25#ibcon#about to read 5, iclass 14, count 0 2006.201.15:21:12.25#ibcon#read 5, iclass 14, count 0 2006.201.15:21:12.25#ibcon#about to read 6, iclass 14, count 0 2006.201.15:21:12.25#ibcon#read 6, iclass 14, count 0 2006.201.15:21:12.25#ibcon#end of sib2, iclass 14, count 0 2006.201.15:21:12.25#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:21:12.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:21:12.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:21:12.25#ibcon#*before write, iclass 14, count 0 2006.201.15:21:12.25#ibcon#enter sib2, iclass 14, count 0 2006.201.15:21:12.25#ibcon#flushed, iclass 14, count 0 2006.201.15:21:12.25#ibcon#about to write, iclass 14, count 0 2006.201.15:21:12.25#ibcon#wrote, iclass 14, count 0 2006.201.15:21:12.25#ibcon#about to read 3, iclass 14, count 0 2006.201.15:21:12.29#ibcon#read 3, iclass 14, count 0 2006.201.15:21:12.29#ibcon#about to read 4, iclass 14, count 0 2006.201.15:21:12.29#ibcon#read 4, iclass 14, count 0 2006.201.15:21:12.29#ibcon#about to read 5, iclass 14, count 0 2006.201.15:21:12.29#ibcon#read 5, iclass 14, count 0 2006.201.15:21:12.29#ibcon#about to read 6, iclass 14, count 0 2006.201.15:21:12.29#ibcon#read 6, iclass 14, count 0 2006.201.15:21:12.29#ibcon#end of sib2, iclass 14, count 0 2006.201.15:21:12.29#ibcon#*after write, iclass 14, count 0 2006.201.15:21:12.29#ibcon#*before return 0, iclass 14, count 0 2006.201.15:21:12.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:12.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:12.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:21:12.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:21:12.29$vck44/va=8,4 2006.201.15:21:12.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.15:21:12.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.15:21:12.29#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:12.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:12.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:12.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:12.35#ibcon#enter wrdev, iclass 16, count 2 2006.201.15:21:12.35#ibcon#first serial, iclass 16, count 2 2006.201.15:21:12.35#ibcon#enter sib2, iclass 16, count 2 2006.201.15:21:12.35#ibcon#flushed, iclass 16, count 2 2006.201.15:21:12.35#ibcon#about to write, iclass 16, count 2 2006.201.15:21:12.35#ibcon#wrote, iclass 16, count 2 2006.201.15:21:12.35#ibcon#about to read 3, iclass 16, count 2 2006.201.15:21:12.37#ibcon#read 3, iclass 16, count 2 2006.201.15:21:12.37#ibcon#about to read 4, iclass 16, count 2 2006.201.15:21:12.37#ibcon#read 4, iclass 16, count 2 2006.201.15:21:12.37#ibcon#about to read 5, iclass 16, count 2 2006.201.15:21:12.37#ibcon#read 5, iclass 16, count 2 2006.201.15:21:12.37#ibcon#about to read 6, iclass 16, count 2 2006.201.15:21:12.37#ibcon#read 6, iclass 16, count 2 2006.201.15:21:12.37#ibcon#end of sib2, iclass 16, count 2 2006.201.15:21:12.37#ibcon#*mode == 0, iclass 16, count 2 2006.201.15:21:12.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.15:21:12.37#ibcon#[25=AT08-04\r\n] 2006.201.15:21:12.37#ibcon#*before write, iclass 16, count 2 2006.201.15:21:12.37#ibcon#enter sib2, iclass 16, count 2 2006.201.15:21:12.37#ibcon#flushed, iclass 16, count 2 2006.201.15:21:12.37#ibcon#about to write, iclass 16, count 2 2006.201.15:21:12.37#ibcon#wrote, iclass 16, count 2 2006.201.15:21:12.37#ibcon#about to read 3, iclass 16, count 2 2006.201.15:21:12.40#ibcon#read 3, iclass 16, count 2 2006.201.15:21:12.40#ibcon#about to read 4, iclass 16, count 2 2006.201.15:21:12.40#ibcon#read 4, iclass 16, count 2 2006.201.15:21:12.40#ibcon#about to read 5, iclass 16, count 2 2006.201.15:21:12.40#ibcon#read 5, iclass 16, count 2 2006.201.15:21:12.40#ibcon#about to read 6, iclass 16, count 2 2006.201.15:21:12.40#ibcon#read 6, iclass 16, count 2 2006.201.15:21:12.40#ibcon#end of sib2, iclass 16, count 2 2006.201.15:21:12.40#ibcon#*after write, iclass 16, count 2 2006.201.15:21:12.40#ibcon#*before return 0, iclass 16, count 2 2006.201.15:21:12.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:12.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:12.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.15:21:12.40#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:12.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:12.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:12.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:12.52#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:21:12.52#ibcon#first serial, iclass 16, count 0 2006.201.15:21:12.52#ibcon#enter sib2, iclass 16, count 0 2006.201.15:21:12.52#ibcon#flushed, iclass 16, count 0 2006.201.15:21:12.52#ibcon#about to write, iclass 16, count 0 2006.201.15:21:12.52#ibcon#wrote, iclass 16, count 0 2006.201.15:21:12.52#ibcon#about to read 3, iclass 16, count 0 2006.201.15:21:12.54#ibcon#read 3, iclass 16, count 0 2006.201.15:21:12.54#ibcon#about to read 4, iclass 16, count 0 2006.201.15:21:12.54#ibcon#read 4, iclass 16, count 0 2006.201.15:21:12.54#ibcon#about to read 5, iclass 16, count 0 2006.201.15:21:12.54#ibcon#read 5, iclass 16, count 0 2006.201.15:21:12.54#ibcon#about to read 6, iclass 16, count 0 2006.201.15:21:12.54#ibcon#read 6, iclass 16, count 0 2006.201.15:21:12.54#ibcon#end of sib2, iclass 16, count 0 2006.201.15:21:12.54#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:21:12.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:21:12.54#ibcon#[25=USB\r\n] 2006.201.15:21:12.54#ibcon#*before write, iclass 16, count 0 2006.201.15:21:12.54#ibcon#enter sib2, iclass 16, count 0 2006.201.15:21:12.54#ibcon#flushed, iclass 16, count 0 2006.201.15:21:12.54#ibcon#about to write, iclass 16, count 0 2006.201.15:21:12.54#ibcon#wrote, iclass 16, count 0 2006.201.15:21:12.54#ibcon#about to read 3, iclass 16, count 0 2006.201.15:21:12.57#ibcon#read 3, iclass 16, count 0 2006.201.15:21:12.57#ibcon#about to read 4, iclass 16, count 0 2006.201.15:21:12.57#ibcon#read 4, iclass 16, count 0 2006.201.15:21:12.57#ibcon#about to read 5, iclass 16, count 0 2006.201.15:21:12.57#ibcon#read 5, iclass 16, count 0 2006.201.15:21:12.57#ibcon#about to read 6, iclass 16, count 0 2006.201.15:21:12.57#ibcon#read 6, iclass 16, count 0 2006.201.15:21:12.57#ibcon#end of sib2, iclass 16, count 0 2006.201.15:21:12.57#ibcon#*after write, iclass 16, count 0 2006.201.15:21:12.57#ibcon#*before return 0, iclass 16, count 0 2006.201.15:21:12.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:12.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:12.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:21:12.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:21:12.57$vck44/vblo=1,629.99 2006.201.15:21:12.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.15:21:12.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.15:21:12.57#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:12.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:12.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:12.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:12.57#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:21:12.57#ibcon#first serial, iclass 18, count 0 2006.201.15:21:12.57#ibcon#enter sib2, iclass 18, count 0 2006.201.15:21:12.57#ibcon#flushed, iclass 18, count 0 2006.201.15:21:12.57#ibcon#about to write, iclass 18, count 0 2006.201.15:21:12.57#ibcon#wrote, iclass 18, count 0 2006.201.15:21:12.57#ibcon#about to read 3, iclass 18, count 0 2006.201.15:21:12.59#ibcon#read 3, iclass 18, count 0 2006.201.15:21:12.59#ibcon#about to read 4, iclass 18, count 0 2006.201.15:21:12.59#ibcon#read 4, iclass 18, count 0 2006.201.15:21:12.59#ibcon#about to read 5, iclass 18, count 0 2006.201.15:21:12.59#ibcon#read 5, iclass 18, count 0 2006.201.15:21:12.59#ibcon#about to read 6, iclass 18, count 0 2006.201.15:21:12.59#ibcon#read 6, iclass 18, count 0 2006.201.15:21:12.59#ibcon#end of sib2, iclass 18, count 0 2006.201.15:21:12.59#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:21:12.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:21:12.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:21:12.59#ibcon#*before write, iclass 18, count 0 2006.201.15:21:12.59#ibcon#enter sib2, iclass 18, count 0 2006.201.15:21:12.59#ibcon#flushed, iclass 18, count 0 2006.201.15:21:12.59#ibcon#about to write, iclass 18, count 0 2006.201.15:21:12.59#ibcon#wrote, iclass 18, count 0 2006.201.15:21:12.59#ibcon#about to read 3, iclass 18, count 0 2006.201.15:21:12.63#ibcon#read 3, iclass 18, count 0 2006.201.15:21:12.63#ibcon#about to read 4, iclass 18, count 0 2006.201.15:21:12.63#ibcon#read 4, iclass 18, count 0 2006.201.15:21:12.63#ibcon#about to read 5, iclass 18, count 0 2006.201.15:21:12.63#ibcon#read 5, iclass 18, count 0 2006.201.15:21:12.63#ibcon#about to read 6, iclass 18, count 0 2006.201.15:21:12.63#ibcon#read 6, iclass 18, count 0 2006.201.15:21:12.63#ibcon#end of sib2, iclass 18, count 0 2006.201.15:21:12.63#ibcon#*after write, iclass 18, count 0 2006.201.15:21:12.63#ibcon#*before return 0, iclass 18, count 0 2006.201.15:21:12.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:12.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:12.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:21:12.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:21:12.63$vck44/vb=1,4 2006.201.15:21:12.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.15:21:12.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.15:21:12.63#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:12.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:21:12.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:21:12.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:21:12.63#ibcon#enter wrdev, iclass 20, count 2 2006.201.15:21:12.63#ibcon#first serial, iclass 20, count 2 2006.201.15:21:12.63#ibcon#enter sib2, iclass 20, count 2 2006.201.15:21:12.63#ibcon#flushed, iclass 20, count 2 2006.201.15:21:12.63#ibcon#about to write, iclass 20, count 2 2006.201.15:21:12.63#ibcon#wrote, iclass 20, count 2 2006.201.15:21:12.63#ibcon#about to read 3, iclass 20, count 2 2006.201.15:21:12.65#ibcon#read 3, iclass 20, count 2 2006.201.15:21:12.65#ibcon#about to read 4, iclass 20, count 2 2006.201.15:21:12.65#ibcon#read 4, iclass 20, count 2 2006.201.15:21:12.65#ibcon#about to read 5, iclass 20, count 2 2006.201.15:21:12.65#ibcon#read 5, iclass 20, count 2 2006.201.15:21:12.65#ibcon#about to read 6, iclass 20, count 2 2006.201.15:21:12.65#ibcon#read 6, iclass 20, count 2 2006.201.15:21:12.65#ibcon#end of sib2, iclass 20, count 2 2006.201.15:21:12.65#ibcon#*mode == 0, iclass 20, count 2 2006.201.15:21:12.65#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.15:21:12.65#ibcon#[27=AT01-04\r\n] 2006.201.15:21:12.65#ibcon#*before write, iclass 20, count 2 2006.201.15:21:12.65#ibcon#enter sib2, iclass 20, count 2 2006.201.15:21:12.65#ibcon#flushed, iclass 20, count 2 2006.201.15:21:12.65#ibcon#about to write, iclass 20, count 2 2006.201.15:21:12.65#ibcon#wrote, iclass 20, count 2 2006.201.15:21:12.65#ibcon#about to read 3, iclass 20, count 2 2006.201.15:21:12.68#ibcon#read 3, iclass 20, count 2 2006.201.15:21:12.68#ibcon#about to read 4, iclass 20, count 2 2006.201.15:21:12.68#ibcon#read 4, iclass 20, count 2 2006.201.15:21:12.68#ibcon#about to read 5, iclass 20, count 2 2006.201.15:21:12.68#ibcon#read 5, iclass 20, count 2 2006.201.15:21:12.68#ibcon#about to read 6, iclass 20, count 2 2006.201.15:21:12.68#ibcon#read 6, iclass 20, count 2 2006.201.15:21:12.68#ibcon#end of sib2, iclass 20, count 2 2006.201.15:21:12.68#ibcon#*after write, iclass 20, count 2 2006.201.15:21:12.68#ibcon#*before return 0, iclass 20, count 2 2006.201.15:21:12.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:21:12.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:21:12.68#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.15:21:12.68#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:12.68#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:21:12.80#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:21:12.80#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:21:12.80#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:21:12.80#ibcon#first serial, iclass 20, count 0 2006.201.15:21:12.80#ibcon#enter sib2, iclass 20, count 0 2006.201.15:21:12.80#ibcon#flushed, iclass 20, count 0 2006.201.15:21:12.80#ibcon#about to write, iclass 20, count 0 2006.201.15:21:12.80#ibcon#wrote, iclass 20, count 0 2006.201.15:21:12.80#ibcon#about to read 3, iclass 20, count 0 2006.201.15:21:12.82#ibcon#read 3, iclass 20, count 0 2006.201.15:21:12.82#ibcon#about to read 4, iclass 20, count 0 2006.201.15:21:12.82#ibcon#read 4, iclass 20, count 0 2006.201.15:21:12.82#ibcon#about to read 5, iclass 20, count 0 2006.201.15:21:12.82#ibcon#read 5, iclass 20, count 0 2006.201.15:21:12.82#ibcon#about to read 6, iclass 20, count 0 2006.201.15:21:12.82#ibcon#read 6, iclass 20, count 0 2006.201.15:21:12.82#ibcon#end of sib2, iclass 20, count 0 2006.201.15:21:12.82#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:21:12.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:21:12.82#ibcon#[27=USB\r\n] 2006.201.15:21:12.82#ibcon#*before write, iclass 20, count 0 2006.201.15:21:12.82#ibcon#enter sib2, iclass 20, count 0 2006.201.15:21:12.82#ibcon#flushed, iclass 20, count 0 2006.201.15:21:12.82#ibcon#about to write, iclass 20, count 0 2006.201.15:21:12.82#ibcon#wrote, iclass 20, count 0 2006.201.15:21:12.82#ibcon#about to read 3, iclass 20, count 0 2006.201.15:21:12.85#ibcon#read 3, iclass 20, count 0 2006.201.15:21:12.85#ibcon#about to read 4, iclass 20, count 0 2006.201.15:21:12.85#ibcon#read 4, iclass 20, count 0 2006.201.15:21:12.85#ibcon#about to read 5, iclass 20, count 0 2006.201.15:21:12.85#ibcon#read 5, iclass 20, count 0 2006.201.15:21:12.85#ibcon#about to read 6, iclass 20, count 0 2006.201.15:21:12.85#ibcon#read 6, iclass 20, count 0 2006.201.15:21:12.85#ibcon#end of sib2, iclass 20, count 0 2006.201.15:21:12.85#ibcon#*after write, iclass 20, count 0 2006.201.15:21:12.85#ibcon#*before return 0, iclass 20, count 0 2006.201.15:21:12.85#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:21:12.85#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:21:12.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:21:12.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:21:12.85$vck44/vblo=2,634.99 2006.201.15:21:12.85#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.15:21:12.85#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.15:21:12.85#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:12.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:12.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:12.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:12.85#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:21:12.85#ibcon#first serial, iclass 22, count 0 2006.201.15:21:12.85#ibcon#enter sib2, iclass 22, count 0 2006.201.15:21:12.85#ibcon#flushed, iclass 22, count 0 2006.201.15:21:12.85#ibcon#about to write, iclass 22, count 0 2006.201.15:21:12.85#ibcon#wrote, iclass 22, count 0 2006.201.15:21:12.85#ibcon#about to read 3, iclass 22, count 0 2006.201.15:21:12.87#ibcon#read 3, iclass 22, count 0 2006.201.15:21:12.87#ibcon#about to read 4, iclass 22, count 0 2006.201.15:21:12.87#ibcon#read 4, iclass 22, count 0 2006.201.15:21:12.87#ibcon#about to read 5, iclass 22, count 0 2006.201.15:21:12.87#ibcon#read 5, iclass 22, count 0 2006.201.15:21:12.87#ibcon#about to read 6, iclass 22, count 0 2006.201.15:21:12.87#ibcon#read 6, iclass 22, count 0 2006.201.15:21:12.87#ibcon#end of sib2, iclass 22, count 0 2006.201.15:21:12.87#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:21:12.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:21:12.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:21:12.87#ibcon#*before write, iclass 22, count 0 2006.201.15:21:12.87#ibcon#enter sib2, iclass 22, count 0 2006.201.15:21:12.87#ibcon#flushed, iclass 22, count 0 2006.201.15:21:12.87#ibcon#about to write, iclass 22, count 0 2006.201.15:21:12.87#ibcon#wrote, iclass 22, count 0 2006.201.15:21:12.87#ibcon#about to read 3, iclass 22, count 0 2006.201.15:21:12.92#ibcon#read 3, iclass 22, count 0 2006.201.15:21:12.92#ibcon#about to read 4, iclass 22, count 0 2006.201.15:21:12.92#ibcon#read 4, iclass 22, count 0 2006.201.15:21:12.92#ibcon#about to read 5, iclass 22, count 0 2006.201.15:21:12.92#ibcon#read 5, iclass 22, count 0 2006.201.15:21:12.92#ibcon#about to read 6, iclass 22, count 0 2006.201.15:21:12.92#ibcon#read 6, iclass 22, count 0 2006.201.15:21:12.92#ibcon#end of sib2, iclass 22, count 0 2006.201.15:21:12.92#ibcon#*after write, iclass 22, count 0 2006.201.15:21:12.92#ibcon#*before return 0, iclass 22, count 0 2006.201.15:21:12.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:12.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:21:12.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:21:12.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:21:12.92$vck44/vb=2,5 2006.201.15:21:12.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.15:21:12.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.15:21:12.92#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:12.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:12.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:12.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:12.97#ibcon#enter wrdev, iclass 24, count 2 2006.201.15:21:12.97#ibcon#first serial, iclass 24, count 2 2006.201.15:21:12.97#ibcon#enter sib2, iclass 24, count 2 2006.201.15:21:12.97#ibcon#flushed, iclass 24, count 2 2006.201.15:21:12.97#ibcon#about to write, iclass 24, count 2 2006.201.15:21:12.97#ibcon#wrote, iclass 24, count 2 2006.201.15:21:12.97#ibcon#about to read 3, iclass 24, count 2 2006.201.15:21:12.99#ibcon#read 3, iclass 24, count 2 2006.201.15:21:12.99#ibcon#about to read 4, iclass 24, count 2 2006.201.15:21:12.99#ibcon#read 4, iclass 24, count 2 2006.201.15:21:12.99#ibcon#about to read 5, iclass 24, count 2 2006.201.15:21:12.99#ibcon#read 5, iclass 24, count 2 2006.201.15:21:12.99#ibcon#about to read 6, iclass 24, count 2 2006.201.15:21:12.99#ibcon#read 6, iclass 24, count 2 2006.201.15:21:12.99#ibcon#end of sib2, iclass 24, count 2 2006.201.15:21:12.99#ibcon#*mode == 0, iclass 24, count 2 2006.201.15:21:12.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.15:21:12.99#ibcon#[27=AT02-05\r\n] 2006.201.15:21:12.99#ibcon#*before write, iclass 24, count 2 2006.201.15:21:12.99#ibcon#enter sib2, iclass 24, count 2 2006.201.15:21:12.99#ibcon#flushed, iclass 24, count 2 2006.201.15:21:12.99#ibcon#about to write, iclass 24, count 2 2006.201.15:21:12.99#ibcon#wrote, iclass 24, count 2 2006.201.15:21:12.99#ibcon#about to read 3, iclass 24, count 2 2006.201.15:21:13.02#ibcon#read 3, iclass 24, count 2 2006.201.15:21:13.02#ibcon#about to read 4, iclass 24, count 2 2006.201.15:21:13.02#ibcon#read 4, iclass 24, count 2 2006.201.15:21:13.02#ibcon#about to read 5, iclass 24, count 2 2006.201.15:21:13.02#ibcon#read 5, iclass 24, count 2 2006.201.15:21:13.02#ibcon#about to read 6, iclass 24, count 2 2006.201.15:21:13.02#ibcon#read 6, iclass 24, count 2 2006.201.15:21:13.02#ibcon#end of sib2, iclass 24, count 2 2006.201.15:21:13.02#ibcon#*after write, iclass 24, count 2 2006.201.15:21:13.02#ibcon#*before return 0, iclass 24, count 2 2006.201.15:21:13.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:13.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:21:13.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.15:21:13.02#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:13.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:13.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:13.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:13.14#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:21:13.14#ibcon#first serial, iclass 24, count 0 2006.201.15:21:13.14#ibcon#enter sib2, iclass 24, count 0 2006.201.15:21:13.14#ibcon#flushed, iclass 24, count 0 2006.201.15:21:13.14#ibcon#about to write, iclass 24, count 0 2006.201.15:21:13.14#ibcon#wrote, iclass 24, count 0 2006.201.15:21:13.14#ibcon#about to read 3, iclass 24, count 0 2006.201.15:21:13.16#ibcon#read 3, iclass 24, count 0 2006.201.15:21:13.16#ibcon#about to read 4, iclass 24, count 0 2006.201.15:21:13.16#ibcon#read 4, iclass 24, count 0 2006.201.15:21:13.16#ibcon#about to read 5, iclass 24, count 0 2006.201.15:21:13.16#ibcon#read 5, iclass 24, count 0 2006.201.15:21:13.16#ibcon#about to read 6, iclass 24, count 0 2006.201.15:21:13.16#ibcon#read 6, iclass 24, count 0 2006.201.15:21:13.16#ibcon#end of sib2, iclass 24, count 0 2006.201.15:21:13.16#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:21:13.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:21:13.16#ibcon#[27=USB\r\n] 2006.201.15:21:13.16#ibcon#*before write, iclass 24, count 0 2006.201.15:21:13.16#ibcon#enter sib2, iclass 24, count 0 2006.201.15:21:13.16#ibcon#flushed, iclass 24, count 0 2006.201.15:21:13.16#ibcon#about to write, iclass 24, count 0 2006.201.15:21:13.16#ibcon#wrote, iclass 24, count 0 2006.201.15:21:13.16#ibcon#about to read 3, iclass 24, count 0 2006.201.15:21:13.19#ibcon#read 3, iclass 24, count 0 2006.201.15:21:13.19#ibcon#about to read 4, iclass 24, count 0 2006.201.15:21:13.19#ibcon#read 4, iclass 24, count 0 2006.201.15:21:13.19#ibcon#about to read 5, iclass 24, count 0 2006.201.15:21:13.19#ibcon#read 5, iclass 24, count 0 2006.201.15:21:13.19#ibcon#about to read 6, iclass 24, count 0 2006.201.15:21:13.19#ibcon#read 6, iclass 24, count 0 2006.201.15:21:13.19#ibcon#end of sib2, iclass 24, count 0 2006.201.15:21:13.19#ibcon#*after write, iclass 24, count 0 2006.201.15:21:13.19#ibcon#*before return 0, iclass 24, count 0 2006.201.15:21:13.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:13.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:21:13.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:21:13.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:21:13.19$vck44/vblo=3,649.99 2006.201.15:21:13.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.15:21:13.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.15:21:13.19#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:13.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:13.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:13.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:13.19#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:21:13.19#ibcon#first serial, iclass 26, count 0 2006.201.15:21:13.19#ibcon#enter sib2, iclass 26, count 0 2006.201.15:21:13.19#ibcon#flushed, iclass 26, count 0 2006.201.15:21:13.19#ibcon#about to write, iclass 26, count 0 2006.201.15:21:13.19#ibcon#wrote, iclass 26, count 0 2006.201.15:21:13.19#ibcon#about to read 3, iclass 26, count 0 2006.201.15:21:13.21#ibcon#read 3, iclass 26, count 0 2006.201.15:21:13.21#ibcon#about to read 4, iclass 26, count 0 2006.201.15:21:13.21#ibcon#read 4, iclass 26, count 0 2006.201.15:21:13.21#ibcon#about to read 5, iclass 26, count 0 2006.201.15:21:13.21#ibcon#read 5, iclass 26, count 0 2006.201.15:21:13.21#ibcon#about to read 6, iclass 26, count 0 2006.201.15:21:13.21#ibcon#read 6, iclass 26, count 0 2006.201.15:21:13.21#ibcon#end of sib2, iclass 26, count 0 2006.201.15:21:13.21#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:21:13.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:21:13.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:21:13.21#ibcon#*before write, iclass 26, count 0 2006.201.15:21:13.21#ibcon#enter sib2, iclass 26, count 0 2006.201.15:21:13.21#ibcon#flushed, iclass 26, count 0 2006.201.15:21:13.21#ibcon#about to write, iclass 26, count 0 2006.201.15:21:13.21#ibcon#wrote, iclass 26, count 0 2006.201.15:21:13.21#ibcon#about to read 3, iclass 26, count 0 2006.201.15:21:13.25#ibcon#read 3, iclass 26, count 0 2006.201.15:21:13.25#ibcon#about to read 4, iclass 26, count 0 2006.201.15:21:13.25#ibcon#read 4, iclass 26, count 0 2006.201.15:21:13.25#ibcon#about to read 5, iclass 26, count 0 2006.201.15:21:13.25#ibcon#read 5, iclass 26, count 0 2006.201.15:21:13.25#ibcon#about to read 6, iclass 26, count 0 2006.201.15:21:13.25#ibcon#read 6, iclass 26, count 0 2006.201.15:21:13.25#ibcon#end of sib2, iclass 26, count 0 2006.201.15:21:13.25#ibcon#*after write, iclass 26, count 0 2006.201.15:21:13.25#ibcon#*before return 0, iclass 26, count 0 2006.201.15:21:13.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:13.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:21:13.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:21:13.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:21:13.25$vck44/vb=3,4 2006.201.15:21:13.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.15:21:13.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.15:21:13.25#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:13.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:13.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:13.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:13.31#ibcon#enter wrdev, iclass 28, count 2 2006.201.15:21:13.31#ibcon#first serial, iclass 28, count 2 2006.201.15:21:13.31#ibcon#enter sib2, iclass 28, count 2 2006.201.15:21:13.31#ibcon#flushed, iclass 28, count 2 2006.201.15:21:13.31#ibcon#about to write, iclass 28, count 2 2006.201.15:21:13.31#ibcon#wrote, iclass 28, count 2 2006.201.15:21:13.31#ibcon#about to read 3, iclass 28, count 2 2006.201.15:21:13.33#ibcon#read 3, iclass 28, count 2 2006.201.15:21:13.33#ibcon#about to read 4, iclass 28, count 2 2006.201.15:21:13.33#ibcon#read 4, iclass 28, count 2 2006.201.15:21:13.33#ibcon#about to read 5, iclass 28, count 2 2006.201.15:21:13.33#ibcon#read 5, iclass 28, count 2 2006.201.15:21:13.33#ibcon#about to read 6, iclass 28, count 2 2006.201.15:21:13.33#ibcon#read 6, iclass 28, count 2 2006.201.15:21:13.33#ibcon#end of sib2, iclass 28, count 2 2006.201.15:21:13.33#ibcon#*mode == 0, iclass 28, count 2 2006.201.15:21:13.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.15:21:13.33#ibcon#[27=AT03-04\r\n] 2006.201.15:21:13.33#ibcon#*before write, iclass 28, count 2 2006.201.15:21:13.33#ibcon#enter sib2, iclass 28, count 2 2006.201.15:21:13.33#ibcon#flushed, iclass 28, count 2 2006.201.15:21:13.33#ibcon#about to write, iclass 28, count 2 2006.201.15:21:13.33#ibcon#wrote, iclass 28, count 2 2006.201.15:21:13.33#ibcon#about to read 3, iclass 28, count 2 2006.201.15:21:13.36#ibcon#read 3, iclass 28, count 2 2006.201.15:21:13.36#ibcon#about to read 4, iclass 28, count 2 2006.201.15:21:13.36#ibcon#read 4, iclass 28, count 2 2006.201.15:21:13.36#ibcon#about to read 5, iclass 28, count 2 2006.201.15:21:13.36#ibcon#read 5, iclass 28, count 2 2006.201.15:21:13.36#ibcon#about to read 6, iclass 28, count 2 2006.201.15:21:13.36#ibcon#read 6, iclass 28, count 2 2006.201.15:21:13.36#ibcon#end of sib2, iclass 28, count 2 2006.201.15:21:13.36#ibcon#*after write, iclass 28, count 2 2006.201.15:21:13.36#ibcon#*before return 0, iclass 28, count 2 2006.201.15:21:13.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:13.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:21:13.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.15:21:13.36#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:13.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:13.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:13.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:13.48#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:21:13.48#ibcon#first serial, iclass 28, count 0 2006.201.15:21:13.48#ibcon#enter sib2, iclass 28, count 0 2006.201.15:21:13.48#ibcon#flushed, iclass 28, count 0 2006.201.15:21:13.48#ibcon#about to write, iclass 28, count 0 2006.201.15:21:13.48#ibcon#wrote, iclass 28, count 0 2006.201.15:21:13.48#ibcon#about to read 3, iclass 28, count 0 2006.201.15:21:13.50#ibcon#read 3, iclass 28, count 0 2006.201.15:21:13.50#ibcon#about to read 4, iclass 28, count 0 2006.201.15:21:13.50#ibcon#read 4, iclass 28, count 0 2006.201.15:21:13.50#ibcon#about to read 5, iclass 28, count 0 2006.201.15:21:13.50#ibcon#read 5, iclass 28, count 0 2006.201.15:21:13.50#ibcon#about to read 6, iclass 28, count 0 2006.201.15:21:13.50#ibcon#read 6, iclass 28, count 0 2006.201.15:21:13.50#ibcon#end of sib2, iclass 28, count 0 2006.201.15:21:13.50#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:21:13.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:21:13.50#ibcon#[27=USB\r\n] 2006.201.15:21:13.50#ibcon#*before write, iclass 28, count 0 2006.201.15:21:13.50#ibcon#enter sib2, iclass 28, count 0 2006.201.15:21:13.50#ibcon#flushed, iclass 28, count 0 2006.201.15:21:13.50#ibcon#about to write, iclass 28, count 0 2006.201.15:21:13.50#ibcon#wrote, iclass 28, count 0 2006.201.15:21:13.50#ibcon#about to read 3, iclass 28, count 0 2006.201.15:21:13.53#ibcon#read 3, iclass 28, count 0 2006.201.15:21:13.53#ibcon#about to read 4, iclass 28, count 0 2006.201.15:21:13.53#ibcon#read 4, iclass 28, count 0 2006.201.15:21:13.53#ibcon#about to read 5, iclass 28, count 0 2006.201.15:21:13.53#ibcon#read 5, iclass 28, count 0 2006.201.15:21:13.53#ibcon#about to read 6, iclass 28, count 0 2006.201.15:21:13.53#ibcon#read 6, iclass 28, count 0 2006.201.15:21:13.53#ibcon#end of sib2, iclass 28, count 0 2006.201.15:21:13.53#ibcon#*after write, iclass 28, count 0 2006.201.15:21:13.53#ibcon#*before return 0, iclass 28, count 0 2006.201.15:21:13.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:13.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:21:13.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:21:13.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:21:13.53$vck44/vblo=4,679.99 2006.201.15:21:13.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.15:21:13.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.15:21:13.53#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:13.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:13.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:13.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:13.53#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:21:13.53#ibcon#first serial, iclass 30, count 0 2006.201.15:21:13.53#ibcon#enter sib2, iclass 30, count 0 2006.201.15:21:13.53#ibcon#flushed, iclass 30, count 0 2006.201.15:21:13.53#ibcon#about to write, iclass 30, count 0 2006.201.15:21:13.53#ibcon#wrote, iclass 30, count 0 2006.201.15:21:13.53#ibcon#about to read 3, iclass 30, count 0 2006.201.15:21:13.55#ibcon#read 3, iclass 30, count 0 2006.201.15:21:13.55#ibcon#about to read 4, iclass 30, count 0 2006.201.15:21:13.55#ibcon#read 4, iclass 30, count 0 2006.201.15:21:13.55#ibcon#about to read 5, iclass 30, count 0 2006.201.15:21:13.55#ibcon#read 5, iclass 30, count 0 2006.201.15:21:13.55#ibcon#about to read 6, iclass 30, count 0 2006.201.15:21:13.55#ibcon#read 6, iclass 30, count 0 2006.201.15:21:13.55#ibcon#end of sib2, iclass 30, count 0 2006.201.15:21:13.55#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:21:13.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:21:13.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:21:13.55#ibcon#*before write, iclass 30, count 0 2006.201.15:21:13.55#ibcon#enter sib2, iclass 30, count 0 2006.201.15:21:13.55#ibcon#flushed, iclass 30, count 0 2006.201.15:21:13.55#ibcon#about to write, iclass 30, count 0 2006.201.15:21:13.55#ibcon#wrote, iclass 30, count 0 2006.201.15:21:13.55#ibcon#about to read 3, iclass 30, count 0 2006.201.15:21:13.60#ibcon#read 3, iclass 30, count 0 2006.201.15:21:13.60#ibcon#about to read 4, iclass 30, count 0 2006.201.15:21:13.60#ibcon#read 4, iclass 30, count 0 2006.201.15:21:13.60#ibcon#about to read 5, iclass 30, count 0 2006.201.15:21:13.60#ibcon#read 5, iclass 30, count 0 2006.201.15:21:13.60#ibcon#about to read 6, iclass 30, count 0 2006.201.15:21:13.60#ibcon#read 6, iclass 30, count 0 2006.201.15:21:13.60#ibcon#end of sib2, iclass 30, count 0 2006.201.15:21:13.60#ibcon#*after write, iclass 30, count 0 2006.201.15:21:13.60#ibcon#*before return 0, iclass 30, count 0 2006.201.15:21:13.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:13.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:21:13.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:21:13.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:21:13.60$vck44/vb=4,5 2006.201.15:21:13.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.15:21:13.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.15:21:13.60#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:13.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:13.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:13.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:13.65#ibcon#enter wrdev, iclass 32, count 2 2006.201.15:21:13.65#ibcon#first serial, iclass 32, count 2 2006.201.15:21:13.65#ibcon#enter sib2, iclass 32, count 2 2006.201.15:21:13.65#ibcon#flushed, iclass 32, count 2 2006.201.15:21:13.65#ibcon#about to write, iclass 32, count 2 2006.201.15:21:13.65#ibcon#wrote, iclass 32, count 2 2006.201.15:21:13.65#ibcon#about to read 3, iclass 32, count 2 2006.201.15:21:13.67#ibcon#read 3, iclass 32, count 2 2006.201.15:21:13.67#ibcon#about to read 4, iclass 32, count 2 2006.201.15:21:13.67#ibcon#read 4, iclass 32, count 2 2006.201.15:21:13.67#ibcon#about to read 5, iclass 32, count 2 2006.201.15:21:13.67#ibcon#read 5, iclass 32, count 2 2006.201.15:21:13.67#ibcon#about to read 6, iclass 32, count 2 2006.201.15:21:13.67#ibcon#read 6, iclass 32, count 2 2006.201.15:21:13.67#ibcon#end of sib2, iclass 32, count 2 2006.201.15:21:13.67#ibcon#*mode == 0, iclass 32, count 2 2006.201.15:21:13.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.15:21:13.67#ibcon#[27=AT04-05\r\n] 2006.201.15:21:13.67#ibcon#*before write, iclass 32, count 2 2006.201.15:21:13.67#ibcon#enter sib2, iclass 32, count 2 2006.201.15:21:13.67#ibcon#flushed, iclass 32, count 2 2006.201.15:21:13.67#ibcon#about to write, iclass 32, count 2 2006.201.15:21:13.67#ibcon#wrote, iclass 32, count 2 2006.201.15:21:13.67#ibcon#about to read 3, iclass 32, count 2 2006.201.15:21:13.70#ibcon#read 3, iclass 32, count 2 2006.201.15:21:13.70#ibcon#about to read 4, iclass 32, count 2 2006.201.15:21:13.70#ibcon#read 4, iclass 32, count 2 2006.201.15:21:13.70#ibcon#about to read 5, iclass 32, count 2 2006.201.15:21:13.70#ibcon#read 5, iclass 32, count 2 2006.201.15:21:13.70#ibcon#about to read 6, iclass 32, count 2 2006.201.15:21:13.70#ibcon#read 6, iclass 32, count 2 2006.201.15:21:13.70#ibcon#end of sib2, iclass 32, count 2 2006.201.15:21:13.70#ibcon#*after write, iclass 32, count 2 2006.201.15:21:13.70#ibcon#*before return 0, iclass 32, count 2 2006.201.15:21:13.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:13.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:21:13.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.15:21:13.70#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:13.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:13.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:13.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:13.82#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:21:13.82#ibcon#first serial, iclass 32, count 0 2006.201.15:21:13.82#ibcon#enter sib2, iclass 32, count 0 2006.201.15:21:13.82#ibcon#flushed, iclass 32, count 0 2006.201.15:21:13.82#ibcon#about to write, iclass 32, count 0 2006.201.15:21:13.82#ibcon#wrote, iclass 32, count 0 2006.201.15:21:13.82#ibcon#about to read 3, iclass 32, count 0 2006.201.15:21:13.84#ibcon#read 3, iclass 32, count 0 2006.201.15:21:13.84#ibcon#about to read 4, iclass 32, count 0 2006.201.15:21:13.84#ibcon#read 4, iclass 32, count 0 2006.201.15:21:13.84#ibcon#about to read 5, iclass 32, count 0 2006.201.15:21:13.84#ibcon#read 5, iclass 32, count 0 2006.201.15:21:13.84#ibcon#about to read 6, iclass 32, count 0 2006.201.15:21:13.84#ibcon#read 6, iclass 32, count 0 2006.201.15:21:13.84#ibcon#end of sib2, iclass 32, count 0 2006.201.15:21:13.84#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:21:13.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:21:13.84#ibcon#[27=USB\r\n] 2006.201.15:21:13.84#ibcon#*before write, iclass 32, count 0 2006.201.15:21:13.84#ibcon#enter sib2, iclass 32, count 0 2006.201.15:21:13.84#ibcon#flushed, iclass 32, count 0 2006.201.15:21:13.84#ibcon#about to write, iclass 32, count 0 2006.201.15:21:13.84#ibcon#wrote, iclass 32, count 0 2006.201.15:21:13.84#ibcon#about to read 3, iclass 32, count 0 2006.201.15:21:13.87#ibcon#read 3, iclass 32, count 0 2006.201.15:21:13.87#ibcon#about to read 4, iclass 32, count 0 2006.201.15:21:13.87#ibcon#read 4, iclass 32, count 0 2006.201.15:21:13.87#ibcon#about to read 5, iclass 32, count 0 2006.201.15:21:13.87#ibcon#read 5, iclass 32, count 0 2006.201.15:21:13.87#ibcon#about to read 6, iclass 32, count 0 2006.201.15:21:13.87#ibcon#read 6, iclass 32, count 0 2006.201.15:21:13.87#ibcon#end of sib2, iclass 32, count 0 2006.201.15:21:13.87#ibcon#*after write, iclass 32, count 0 2006.201.15:21:13.87#ibcon#*before return 0, iclass 32, count 0 2006.201.15:21:13.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:13.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:21:13.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:21:13.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:21:13.87$vck44/vblo=5,709.99 2006.201.15:21:13.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.15:21:13.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.15:21:13.87#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:13.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:13.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:13.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:13.87#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:21:13.87#ibcon#first serial, iclass 34, count 0 2006.201.15:21:13.87#ibcon#enter sib2, iclass 34, count 0 2006.201.15:21:13.87#ibcon#flushed, iclass 34, count 0 2006.201.15:21:13.87#ibcon#about to write, iclass 34, count 0 2006.201.15:21:13.87#ibcon#wrote, iclass 34, count 0 2006.201.15:21:13.87#ibcon#about to read 3, iclass 34, count 0 2006.201.15:21:13.89#ibcon#read 3, iclass 34, count 0 2006.201.15:21:13.89#ibcon#about to read 4, iclass 34, count 0 2006.201.15:21:13.89#ibcon#read 4, iclass 34, count 0 2006.201.15:21:13.89#ibcon#about to read 5, iclass 34, count 0 2006.201.15:21:13.89#ibcon#read 5, iclass 34, count 0 2006.201.15:21:13.89#ibcon#about to read 6, iclass 34, count 0 2006.201.15:21:13.89#ibcon#read 6, iclass 34, count 0 2006.201.15:21:13.89#ibcon#end of sib2, iclass 34, count 0 2006.201.15:21:13.89#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:21:13.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:21:13.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:21:13.89#ibcon#*before write, iclass 34, count 0 2006.201.15:21:13.89#ibcon#enter sib2, iclass 34, count 0 2006.201.15:21:13.89#ibcon#flushed, iclass 34, count 0 2006.201.15:21:13.89#ibcon#about to write, iclass 34, count 0 2006.201.15:21:13.89#ibcon#wrote, iclass 34, count 0 2006.201.15:21:13.89#ibcon#about to read 3, iclass 34, count 0 2006.201.15:21:13.94#ibcon#read 3, iclass 34, count 0 2006.201.15:21:13.94#ibcon#about to read 4, iclass 34, count 0 2006.201.15:21:13.94#ibcon#read 4, iclass 34, count 0 2006.201.15:21:13.94#ibcon#about to read 5, iclass 34, count 0 2006.201.15:21:13.94#ibcon#read 5, iclass 34, count 0 2006.201.15:21:13.94#ibcon#about to read 6, iclass 34, count 0 2006.201.15:21:13.94#ibcon#read 6, iclass 34, count 0 2006.201.15:21:13.94#ibcon#end of sib2, iclass 34, count 0 2006.201.15:21:13.94#ibcon#*after write, iclass 34, count 0 2006.201.15:21:13.94#ibcon#*before return 0, iclass 34, count 0 2006.201.15:21:13.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:13.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:21:13.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:21:13.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:21:13.94$vck44/vb=5,4 2006.201.15:21:13.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.15:21:13.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.15:21:13.94#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:13.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:21:13.94#abcon#<5=/04 1.1 2.4 20.801001003.2\r\n> 2006.201.15:21:13.96#abcon#{5=INTERFACE CLEAR} 2006.201.15:21:13.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:21:13.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:21:13.99#ibcon#enter wrdev, iclass 37, count 2 2006.201.15:21:13.99#ibcon#first serial, iclass 37, count 2 2006.201.15:21:13.99#ibcon#enter sib2, iclass 37, count 2 2006.201.15:21:13.99#ibcon#flushed, iclass 37, count 2 2006.201.15:21:13.99#ibcon#about to write, iclass 37, count 2 2006.201.15:21:13.99#ibcon#wrote, iclass 37, count 2 2006.201.15:21:13.99#ibcon#about to read 3, iclass 37, count 2 2006.201.15:21:14.01#ibcon#read 3, iclass 37, count 2 2006.201.15:21:14.01#ibcon#about to read 4, iclass 37, count 2 2006.201.15:21:14.01#ibcon#read 4, iclass 37, count 2 2006.201.15:21:14.01#ibcon#about to read 5, iclass 37, count 2 2006.201.15:21:14.01#ibcon#read 5, iclass 37, count 2 2006.201.15:21:14.01#ibcon#about to read 6, iclass 37, count 2 2006.201.15:21:14.01#ibcon#read 6, iclass 37, count 2 2006.201.15:21:14.01#ibcon#end of sib2, iclass 37, count 2 2006.201.15:21:14.01#ibcon#*mode == 0, iclass 37, count 2 2006.201.15:21:14.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.15:21:14.01#ibcon#[27=AT05-04\r\n] 2006.201.15:21:14.01#ibcon#*before write, iclass 37, count 2 2006.201.15:21:14.01#ibcon#enter sib2, iclass 37, count 2 2006.201.15:21:14.01#ibcon#flushed, iclass 37, count 2 2006.201.15:21:14.01#ibcon#about to write, iclass 37, count 2 2006.201.15:21:14.01#ibcon#wrote, iclass 37, count 2 2006.201.15:21:14.01#ibcon#about to read 3, iclass 37, count 2 2006.201.15:21:14.02#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:21:14.04#ibcon#read 3, iclass 37, count 2 2006.201.15:21:14.04#ibcon#about to read 4, iclass 37, count 2 2006.201.15:21:14.04#ibcon#read 4, iclass 37, count 2 2006.201.15:21:14.04#ibcon#about to read 5, iclass 37, count 2 2006.201.15:21:14.04#ibcon#read 5, iclass 37, count 2 2006.201.15:21:14.04#ibcon#about to read 6, iclass 37, count 2 2006.201.15:21:14.04#ibcon#read 6, iclass 37, count 2 2006.201.15:21:14.04#ibcon#end of sib2, iclass 37, count 2 2006.201.15:21:14.04#ibcon#*after write, iclass 37, count 2 2006.201.15:21:14.04#ibcon#*before return 0, iclass 37, count 2 2006.201.15:21:14.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:21:14.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.15:21:14.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.15:21:14.04#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:14.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:21:14.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:21:14.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:21:14.16#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:21:14.16#ibcon#first serial, iclass 37, count 0 2006.201.15:21:14.16#ibcon#enter sib2, iclass 37, count 0 2006.201.15:21:14.16#ibcon#flushed, iclass 37, count 0 2006.201.15:21:14.16#ibcon#about to write, iclass 37, count 0 2006.201.15:21:14.16#ibcon#wrote, iclass 37, count 0 2006.201.15:21:14.16#ibcon#about to read 3, iclass 37, count 0 2006.201.15:21:14.18#ibcon#read 3, iclass 37, count 0 2006.201.15:21:14.18#ibcon#about to read 4, iclass 37, count 0 2006.201.15:21:14.18#ibcon#read 4, iclass 37, count 0 2006.201.15:21:14.18#ibcon#about to read 5, iclass 37, count 0 2006.201.15:21:14.18#ibcon#read 5, iclass 37, count 0 2006.201.15:21:14.18#ibcon#about to read 6, iclass 37, count 0 2006.201.15:21:14.18#ibcon#read 6, iclass 37, count 0 2006.201.15:21:14.18#ibcon#end of sib2, iclass 37, count 0 2006.201.15:21:14.18#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:21:14.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:21:14.18#ibcon#[27=USB\r\n] 2006.201.15:21:14.18#ibcon#*before write, iclass 37, count 0 2006.201.15:21:14.18#ibcon#enter sib2, iclass 37, count 0 2006.201.15:21:14.18#ibcon#flushed, iclass 37, count 0 2006.201.15:21:14.18#ibcon#about to write, iclass 37, count 0 2006.201.15:21:14.18#ibcon#wrote, iclass 37, count 0 2006.201.15:21:14.18#ibcon#about to read 3, iclass 37, count 0 2006.201.15:21:14.21#ibcon#read 3, iclass 37, count 0 2006.201.15:21:14.21#ibcon#about to read 4, iclass 37, count 0 2006.201.15:21:14.21#ibcon#read 4, iclass 37, count 0 2006.201.15:21:14.21#ibcon#about to read 5, iclass 37, count 0 2006.201.15:21:14.21#ibcon#read 5, iclass 37, count 0 2006.201.15:21:14.21#ibcon#about to read 6, iclass 37, count 0 2006.201.15:21:14.21#ibcon#read 6, iclass 37, count 0 2006.201.15:21:14.21#ibcon#end of sib2, iclass 37, count 0 2006.201.15:21:14.21#ibcon#*after write, iclass 37, count 0 2006.201.15:21:14.21#ibcon#*before return 0, iclass 37, count 0 2006.201.15:21:14.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:21:14.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.15:21:14.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:21:14.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:21:14.21$vck44/vblo=6,719.99 2006.201.15:21:14.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.15:21:14.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.15:21:14.21#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:14.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:14.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:14.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:14.21#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:21:14.21#ibcon#first serial, iclass 4, count 0 2006.201.15:21:14.21#ibcon#enter sib2, iclass 4, count 0 2006.201.15:21:14.21#ibcon#flushed, iclass 4, count 0 2006.201.15:21:14.21#ibcon#about to write, iclass 4, count 0 2006.201.15:21:14.21#ibcon#wrote, iclass 4, count 0 2006.201.15:21:14.21#ibcon#about to read 3, iclass 4, count 0 2006.201.15:21:14.23#ibcon#read 3, iclass 4, count 0 2006.201.15:21:14.23#ibcon#about to read 4, iclass 4, count 0 2006.201.15:21:14.23#ibcon#read 4, iclass 4, count 0 2006.201.15:21:14.23#ibcon#about to read 5, iclass 4, count 0 2006.201.15:21:14.23#ibcon#read 5, iclass 4, count 0 2006.201.15:21:14.23#ibcon#about to read 6, iclass 4, count 0 2006.201.15:21:14.23#ibcon#read 6, iclass 4, count 0 2006.201.15:21:14.23#ibcon#end of sib2, iclass 4, count 0 2006.201.15:21:14.23#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:21:14.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:21:14.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:21:14.23#ibcon#*before write, iclass 4, count 0 2006.201.15:21:14.23#ibcon#enter sib2, iclass 4, count 0 2006.201.15:21:14.23#ibcon#flushed, iclass 4, count 0 2006.201.15:21:14.23#ibcon#about to write, iclass 4, count 0 2006.201.15:21:14.23#ibcon#wrote, iclass 4, count 0 2006.201.15:21:14.23#ibcon#about to read 3, iclass 4, count 0 2006.201.15:21:14.27#ibcon#read 3, iclass 4, count 0 2006.201.15:21:14.27#ibcon#about to read 4, iclass 4, count 0 2006.201.15:21:14.27#ibcon#read 4, iclass 4, count 0 2006.201.15:21:14.27#ibcon#about to read 5, iclass 4, count 0 2006.201.15:21:14.27#ibcon#read 5, iclass 4, count 0 2006.201.15:21:14.27#ibcon#about to read 6, iclass 4, count 0 2006.201.15:21:14.27#ibcon#read 6, iclass 4, count 0 2006.201.15:21:14.27#ibcon#end of sib2, iclass 4, count 0 2006.201.15:21:14.27#ibcon#*after write, iclass 4, count 0 2006.201.15:21:14.27#ibcon#*before return 0, iclass 4, count 0 2006.201.15:21:14.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:14.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:21:14.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:21:14.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:21:14.27$vck44/vb=6,4 2006.201.15:21:14.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.15:21:14.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.15:21:14.27#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:14.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:14.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:14.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:14.33#ibcon#enter wrdev, iclass 6, count 2 2006.201.15:21:14.33#ibcon#first serial, iclass 6, count 2 2006.201.15:21:14.33#ibcon#enter sib2, iclass 6, count 2 2006.201.15:21:14.33#ibcon#flushed, iclass 6, count 2 2006.201.15:21:14.33#ibcon#about to write, iclass 6, count 2 2006.201.15:21:14.33#ibcon#wrote, iclass 6, count 2 2006.201.15:21:14.33#ibcon#about to read 3, iclass 6, count 2 2006.201.15:21:14.35#ibcon#read 3, iclass 6, count 2 2006.201.15:21:14.35#ibcon#about to read 4, iclass 6, count 2 2006.201.15:21:14.35#ibcon#read 4, iclass 6, count 2 2006.201.15:21:14.35#ibcon#about to read 5, iclass 6, count 2 2006.201.15:21:14.35#ibcon#read 5, iclass 6, count 2 2006.201.15:21:14.35#ibcon#about to read 6, iclass 6, count 2 2006.201.15:21:14.35#ibcon#read 6, iclass 6, count 2 2006.201.15:21:14.35#ibcon#end of sib2, iclass 6, count 2 2006.201.15:21:14.35#ibcon#*mode == 0, iclass 6, count 2 2006.201.15:21:14.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.15:21:14.35#ibcon#[27=AT06-04\r\n] 2006.201.15:21:14.35#ibcon#*before write, iclass 6, count 2 2006.201.15:21:14.35#ibcon#enter sib2, iclass 6, count 2 2006.201.15:21:14.35#ibcon#flushed, iclass 6, count 2 2006.201.15:21:14.35#ibcon#about to write, iclass 6, count 2 2006.201.15:21:14.35#ibcon#wrote, iclass 6, count 2 2006.201.15:21:14.35#ibcon#about to read 3, iclass 6, count 2 2006.201.15:21:14.38#ibcon#read 3, iclass 6, count 2 2006.201.15:21:14.38#ibcon#about to read 4, iclass 6, count 2 2006.201.15:21:14.38#ibcon#read 4, iclass 6, count 2 2006.201.15:21:14.38#ibcon#about to read 5, iclass 6, count 2 2006.201.15:21:14.38#ibcon#read 5, iclass 6, count 2 2006.201.15:21:14.38#ibcon#about to read 6, iclass 6, count 2 2006.201.15:21:14.38#ibcon#read 6, iclass 6, count 2 2006.201.15:21:14.38#ibcon#end of sib2, iclass 6, count 2 2006.201.15:21:14.38#ibcon#*after write, iclass 6, count 2 2006.201.15:21:14.38#ibcon#*before return 0, iclass 6, count 2 2006.201.15:21:14.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:14.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:21:14.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.15:21:14.38#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:14.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:14.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:14.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:14.50#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:21:14.50#ibcon#first serial, iclass 6, count 0 2006.201.15:21:14.50#ibcon#enter sib2, iclass 6, count 0 2006.201.15:21:14.50#ibcon#flushed, iclass 6, count 0 2006.201.15:21:14.50#ibcon#about to write, iclass 6, count 0 2006.201.15:21:14.50#ibcon#wrote, iclass 6, count 0 2006.201.15:21:14.50#ibcon#about to read 3, iclass 6, count 0 2006.201.15:21:14.52#ibcon#read 3, iclass 6, count 0 2006.201.15:21:14.52#ibcon#about to read 4, iclass 6, count 0 2006.201.15:21:14.52#ibcon#read 4, iclass 6, count 0 2006.201.15:21:14.52#ibcon#about to read 5, iclass 6, count 0 2006.201.15:21:14.52#ibcon#read 5, iclass 6, count 0 2006.201.15:21:14.52#ibcon#about to read 6, iclass 6, count 0 2006.201.15:21:14.52#ibcon#read 6, iclass 6, count 0 2006.201.15:21:14.52#ibcon#end of sib2, iclass 6, count 0 2006.201.15:21:14.52#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:21:14.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:21:14.52#ibcon#[27=USB\r\n] 2006.201.15:21:14.52#ibcon#*before write, iclass 6, count 0 2006.201.15:21:14.52#ibcon#enter sib2, iclass 6, count 0 2006.201.15:21:14.52#ibcon#flushed, iclass 6, count 0 2006.201.15:21:14.52#ibcon#about to write, iclass 6, count 0 2006.201.15:21:14.52#ibcon#wrote, iclass 6, count 0 2006.201.15:21:14.52#ibcon#about to read 3, iclass 6, count 0 2006.201.15:21:14.55#ibcon#read 3, iclass 6, count 0 2006.201.15:21:14.55#ibcon#about to read 4, iclass 6, count 0 2006.201.15:21:14.55#ibcon#read 4, iclass 6, count 0 2006.201.15:21:14.55#ibcon#about to read 5, iclass 6, count 0 2006.201.15:21:14.55#ibcon#read 5, iclass 6, count 0 2006.201.15:21:14.55#ibcon#about to read 6, iclass 6, count 0 2006.201.15:21:14.55#ibcon#read 6, iclass 6, count 0 2006.201.15:21:14.55#ibcon#end of sib2, iclass 6, count 0 2006.201.15:21:14.55#ibcon#*after write, iclass 6, count 0 2006.201.15:21:14.55#ibcon#*before return 0, iclass 6, count 0 2006.201.15:21:14.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:14.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:21:14.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:21:14.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:21:14.55$vck44/vblo=7,734.99 2006.201.15:21:14.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.15:21:14.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.15:21:14.55#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:14.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:14.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:14.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:14.55#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:21:14.55#ibcon#first serial, iclass 10, count 0 2006.201.15:21:14.55#ibcon#enter sib2, iclass 10, count 0 2006.201.15:21:14.55#ibcon#flushed, iclass 10, count 0 2006.201.15:21:14.55#ibcon#about to write, iclass 10, count 0 2006.201.15:21:14.55#ibcon#wrote, iclass 10, count 0 2006.201.15:21:14.55#ibcon#about to read 3, iclass 10, count 0 2006.201.15:21:14.57#ibcon#read 3, iclass 10, count 0 2006.201.15:21:14.57#ibcon#about to read 4, iclass 10, count 0 2006.201.15:21:14.57#ibcon#read 4, iclass 10, count 0 2006.201.15:21:14.57#ibcon#about to read 5, iclass 10, count 0 2006.201.15:21:14.57#ibcon#read 5, iclass 10, count 0 2006.201.15:21:14.57#ibcon#about to read 6, iclass 10, count 0 2006.201.15:21:14.57#ibcon#read 6, iclass 10, count 0 2006.201.15:21:14.57#ibcon#end of sib2, iclass 10, count 0 2006.201.15:21:14.57#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:21:14.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:21:14.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:21:14.57#ibcon#*before write, iclass 10, count 0 2006.201.15:21:14.57#ibcon#enter sib2, iclass 10, count 0 2006.201.15:21:14.57#ibcon#flushed, iclass 10, count 0 2006.201.15:21:14.57#ibcon#about to write, iclass 10, count 0 2006.201.15:21:14.57#ibcon#wrote, iclass 10, count 0 2006.201.15:21:14.57#ibcon#about to read 3, iclass 10, count 0 2006.201.15:21:14.62#ibcon#read 3, iclass 10, count 0 2006.201.15:21:14.62#ibcon#about to read 4, iclass 10, count 0 2006.201.15:21:14.62#ibcon#read 4, iclass 10, count 0 2006.201.15:21:14.62#ibcon#about to read 5, iclass 10, count 0 2006.201.15:21:14.62#ibcon#read 5, iclass 10, count 0 2006.201.15:21:14.62#ibcon#about to read 6, iclass 10, count 0 2006.201.15:21:14.62#ibcon#read 6, iclass 10, count 0 2006.201.15:21:14.62#ibcon#end of sib2, iclass 10, count 0 2006.201.15:21:14.62#ibcon#*after write, iclass 10, count 0 2006.201.15:21:14.62#ibcon#*before return 0, iclass 10, count 0 2006.201.15:21:14.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:14.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:21:14.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:21:14.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:21:14.62$vck44/vb=7,4 2006.201.15:21:14.62#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.15:21:14.62#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.15:21:14.62#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:14.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:14.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:14.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:14.67#ibcon#enter wrdev, iclass 12, count 2 2006.201.15:21:14.67#ibcon#first serial, iclass 12, count 2 2006.201.15:21:14.67#ibcon#enter sib2, iclass 12, count 2 2006.201.15:21:14.67#ibcon#flushed, iclass 12, count 2 2006.201.15:21:14.67#ibcon#about to write, iclass 12, count 2 2006.201.15:21:14.67#ibcon#wrote, iclass 12, count 2 2006.201.15:21:14.67#ibcon#about to read 3, iclass 12, count 2 2006.201.15:21:14.69#ibcon#read 3, iclass 12, count 2 2006.201.15:21:14.69#ibcon#about to read 4, iclass 12, count 2 2006.201.15:21:14.69#ibcon#read 4, iclass 12, count 2 2006.201.15:21:14.69#ibcon#about to read 5, iclass 12, count 2 2006.201.15:21:14.69#ibcon#read 5, iclass 12, count 2 2006.201.15:21:14.69#ibcon#about to read 6, iclass 12, count 2 2006.201.15:21:14.69#ibcon#read 6, iclass 12, count 2 2006.201.15:21:14.69#ibcon#end of sib2, iclass 12, count 2 2006.201.15:21:14.69#ibcon#*mode == 0, iclass 12, count 2 2006.201.15:21:14.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.15:21:14.69#ibcon#[27=AT07-04\r\n] 2006.201.15:21:14.69#ibcon#*before write, iclass 12, count 2 2006.201.15:21:14.69#ibcon#enter sib2, iclass 12, count 2 2006.201.15:21:14.69#ibcon#flushed, iclass 12, count 2 2006.201.15:21:14.69#ibcon#about to write, iclass 12, count 2 2006.201.15:21:14.69#ibcon#wrote, iclass 12, count 2 2006.201.15:21:14.69#ibcon#about to read 3, iclass 12, count 2 2006.201.15:21:14.72#ibcon#read 3, iclass 12, count 2 2006.201.15:21:14.72#ibcon#about to read 4, iclass 12, count 2 2006.201.15:21:14.72#ibcon#read 4, iclass 12, count 2 2006.201.15:21:14.72#ibcon#about to read 5, iclass 12, count 2 2006.201.15:21:14.72#ibcon#read 5, iclass 12, count 2 2006.201.15:21:14.72#ibcon#about to read 6, iclass 12, count 2 2006.201.15:21:14.72#ibcon#read 6, iclass 12, count 2 2006.201.15:21:14.72#ibcon#end of sib2, iclass 12, count 2 2006.201.15:21:14.72#ibcon#*after write, iclass 12, count 2 2006.201.15:21:14.72#ibcon#*before return 0, iclass 12, count 2 2006.201.15:21:14.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:14.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:21:14.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.15:21:14.72#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:14.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:14.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:14.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:14.84#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:21:14.84#ibcon#first serial, iclass 12, count 0 2006.201.15:21:14.84#ibcon#enter sib2, iclass 12, count 0 2006.201.15:21:14.84#ibcon#flushed, iclass 12, count 0 2006.201.15:21:14.84#ibcon#about to write, iclass 12, count 0 2006.201.15:21:14.84#ibcon#wrote, iclass 12, count 0 2006.201.15:21:14.84#ibcon#about to read 3, iclass 12, count 0 2006.201.15:21:14.86#ibcon#read 3, iclass 12, count 0 2006.201.15:21:14.86#ibcon#about to read 4, iclass 12, count 0 2006.201.15:21:14.86#ibcon#read 4, iclass 12, count 0 2006.201.15:21:14.86#ibcon#about to read 5, iclass 12, count 0 2006.201.15:21:14.86#ibcon#read 5, iclass 12, count 0 2006.201.15:21:14.86#ibcon#about to read 6, iclass 12, count 0 2006.201.15:21:14.86#ibcon#read 6, iclass 12, count 0 2006.201.15:21:14.86#ibcon#end of sib2, iclass 12, count 0 2006.201.15:21:14.86#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:21:14.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:21:14.86#ibcon#[27=USB\r\n] 2006.201.15:21:14.86#ibcon#*before write, iclass 12, count 0 2006.201.15:21:14.86#ibcon#enter sib2, iclass 12, count 0 2006.201.15:21:14.86#ibcon#flushed, iclass 12, count 0 2006.201.15:21:14.86#ibcon#about to write, iclass 12, count 0 2006.201.15:21:14.86#ibcon#wrote, iclass 12, count 0 2006.201.15:21:14.86#ibcon#about to read 3, iclass 12, count 0 2006.201.15:21:14.89#ibcon#read 3, iclass 12, count 0 2006.201.15:21:14.89#ibcon#about to read 4, iclass 12, count 0 2006.201.15:21:14.89#ibcon#read 4, iclass 12, count 0 2006.201.15:21:14.89#ibcon#about to read 5, iclass 12, count 0 2006.201.15:21:14.89#ibcon#read 5, iclass 12, count 0 2006.201.15:21:14.89#ibcon#about to read 6, iclass 12, count 0 2006.201.15:21:14.89#ibcon#read 6, iclass 12, count 0 2006.201.15:21:14.89#ibcon#end of sib2, iclass 12, count 0 2006.201.15:21:14.89#ibcon#*after write, iclass 12, count 0 2006.201.15:21:14.89#ibcon#*before return 0, iclass 12, count 0 2006.201.15:21:14.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:14.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:21:14.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:21:14.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:21:14.89$vck44/vblo=8,744.99 2006.201.15:21:14.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.15:21:14.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.15:21:14.89#ibcon#ireg 17 cls_cnt 0 2006.201.15:21:14.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:14.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:14.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:14.89#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:21:14.89#ibcon#first serial, iclass 14, count 0 2006.201.15:21:14.89#ibcon#enter sib2, iclass 14, count 0 2006.201.15:21:14.89#ibcon#flushed, iclass 14, count 0 2006.201.15:21:14.89#ibcon#about to write, iclass 14, count 0 2006.201.15:21:14.89#ibcon#wrote, iclass 14, count 0 2006.201.15:21:14.89#ibcon#about to read 3, iclass 14, count 0 2006.201.15:21:14.91#ibcon#read 3, iclass 14, count 0 2006.201.15:21:14.91#ibcon#about to read 4, iclass 14, count 0 2006.201.15:21:14.91#ibcon#read 4, iclass 14, count 0 2006.201.15:21:14.91#ibcon#about to read 5, iclass 14, count 0 2006.201.15:21:14.91#ibcon#read 5, iclass 14, count 0 2006.201.15:21:14.91#ibcon#about to read 6, iclass 14, count 0 2006.201.15:21:14.91#ibcon#read 6, iclass 14, count 0 2006.201.15:21:14.91#ibcon#end of sib2, iclass 14, count 0 2006.201.15:21:14.91#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:21:14.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:21:14.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:21:14.91#ibcon#*before write, iclass 14, count 0 2006.201.15:21:14.91#ibcon#enter sib2, iclass 14, count 0 2006.201.15:21:14.91#ibcon#flushed, iclass 14, count 0 2006.201.15:21:14.91#ibcon#about to write, iclass 14, count 0 2006.201.15:21:14.91#ibcon#wrote, iclass 14, count 0 2006.201.15:21:14.91#ibcon#about to read 3, iclass 14, count 0 2006.201.15:21:14.95#ibcon#read 3, iclass 14, count 0 2006.201.15:21:14.95#ibcon#about to read 4, iclass 14, count 0 2006.201.15:21:14.95#ibcon#read 4, iclass 14, count 0 2006.201.15:21:14.95#ibcon#about to read 5, iclass 14, count 0 2006.201.15:21:14.95#ibcon#read 5, iclass 14, count 0 2006.201.15:21:14.95#ibcon#about to read 6, iclass 14, count 0 2006.201.15:21:14.95#ibcon#read 6, iclass 14, count 0 2006.201.15:21:14.95#ibcon#end of sib2, iclass 14, count 0 2006.201.15:21:14.95#ibcon#*after write, iclass 14, count 0 2006.201.15:21:14.95#ibcon#*before return 0, iclass 14, count 0 2006.201.15:21:14.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:14.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:21:14.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:21:14.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:21:14.95$vck44/vb=8,4 2006.201.15:21:14.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.15:21:14.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.15:21:14.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:21:14.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:15.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:15.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:15.01#ibcon#enter wrdev, iclass 16, count 2 2006.201.15:21:15.01#ibcon#first serial, iclass 16, count 2 2006.201.15:21:15.01#ibcon#enter sib2, iclass 16, count 2 2006.201.15:21:15.01#ibcon#flushed, iclass 16, count 2 2006.201.15:21:15.01#ibcon#about to write, iclass 16, count 2 2006.201.15:21:15.01#ibcon#wrote, iclass 16, count 2 2006.201.15:21:15.01#ibcon#about to read 3, iclass 16, count 2 2006.201.15:21:15.03#ibcon#read 3, iclass 16, count 2 2006.201.15:21:15.03#ibcon#about to read 4, iclass 16, count 2 2006.201.15:21:15.03#ibcon#read 4, iclass 16, count 2 2006.201.15:21:15.03#ibcon#about to read 5, iclass 16, count 2 2006.201.15:21:15.03#ibcon#read 5, iclass 16, count 2 2006.201.15:21:15.03#ibcon#about to read 6, iclass 16, count 2 2006.201.15:21:15.03#ibcon#read 6, iclass 16, count 2 2006.201.15:21:15.03#ibcon#end of sib2, iclass 16, count 2 2006.201.15:21:15.03#ibcon#*mode == 0, iclass 16, count 2 2006.201.15:21:15.03#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.15:21:15.03#ibcon#[27=AT08-04\r\n] 2006.201.15:21:15.03#ibcon#*before write, iclass 16, count 2 2006.201.15:21:15.03#ibcon#enter sib2, iclass 16, count 2 2006.201.15:21:15.03#ibcon#flushed, iclass 16, count 2 2006.201.15:21:15.03#ibcon#about to write, iclass 16, count 2 2006.201.15:21:15.03#ibcon#wrote, iclass 16, count 2 2006.201.15:21:15.03#ibcon#about to read 3, iclass 16, count 2 2006.201.15:21:15.06#ibcon#read 3, iclass 16, count 2 2006.201.15:21:15.06#ibcon#about to read 4, iclass 16, count 2 2006.201.15:21:15.06#ibcon#read 4, iclass 16, count 2 2006.201.15:21:15.06#ibcon#about to read 5, iclass 16, count 2 2006.201.15:21:15.06#ibcon#read 5, iclass 16, count 2 2006.201.15:21:15.06#ibcon#about to read 6, iclass 16, count 2 2006.201.15:21:15.06#ibcon#read 6, iclass 16, count 2 2006.201.15:21:15.06#ibcon#end of sib2, iclass 16, count 2 2006.201.15:21:15.06#ibcon#*after write, iclass 16, count 2 2006.201.15:21:15.06#ibcon#*before return 0, iclass 16, count 2 2006.201.15:21:15.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:15.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:21:15.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.15:21:15.06#ibcon#ireg 7 cls_cnt 0 2006.201.15:21:15.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:15.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:15.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:15.18#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:21:15.18#ibcon#first serial, iclass 16, count 0 2006.201.15:21:15.18#ibcon#enter sib2, iclass 16, count 0 2006.201.15:21:15.18#ibcon#flushed, iclass 16, count 0 2006.201.15:21:15.18#ibcon#about to write, iclass 16, count 0 2006.201.15:21:15.18#ibcon#wrote, iclass 16, count 0 2006.201.15:21:15.18#ibcon#about to read 3, iclass 16, count 0 2006.201.15:21:15.21#ibcon#read 3, iclass 16, count 0 2006.201.15:21:15.21#ibcon#about to read 4, iclass 16, count 0 2006.201.15:21:15.21#ibcon#read 4, iclass 16, count 0 2006.201.15:21:15.21#ibcon#about to read 5, iclass 16, count 0 2006.201.15:21:15.21#ibcon#read 5, iclass 16, count 0 2006.201.15:21:15.21#ibcon#about to read 6, iclass 16, count 0 2006.201.15:21:15.21#ibcon#read 6, iclass 16, count 0 2006.201.15:21:15.21#ibcon#end of sib2, iclass 16, count 0 2006.201.15:21:15.21#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:21:15.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:21:15.21#ibcon#[27=USB\r\n] 2006.201.15:21:15.21#ibcon#*before write, iclass 16, count 0 2006.201.15:21:15.21#ibcon#enter sib2, iclass 16, count 0 2006.201.15:21:15.21#ibcon#flushed, iclass 16, count 0 2006.201.15:21:15.21#ibcon#about to write, iclass 16, count 0 2006.201.15:21:15.21#ibcon#wrote, iclass 16, count 0 2006.201.15:21:15.21#ibcon#about to read 3, iclass 16, count 0 2006.201.15:21:15.24#ibcon#read 3, iclass 16, count 0 2006.201.15:21:15.24#ibcon#about to read 4, iclass 16, count 0 2006.201.15:21:15.24#ibcon#read 4, iclass 16, count 0 2006.201.15:21:15.24#ibcon#about to read 5, iclass 16, count 0 2006.201.15:21:15.24#ibcon#read 5, iclass 16, count 0 2006.201.15:21:15.24#ibcon#about to read 6, iclass 16, count 0 2006.201.15:21:15.24#ibcon#read 6, iclass 16, count 0 2006.201.15:21:15.24#ibcon#end of sib2, iclass 16, count 0 2006.201.15:21:15.24#ibcon#*after write, iclass 16, count 0 2006.201.15:21:15.24#ibcon#*before return 0, iclass 16, count 0 2006.201.15:21:15.24#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:15.24#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:21:15.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:21:15.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:21:15.24$vck44/vabw=wide 2006.201.15:21:15.24#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.15:21:15.24#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.15:21:15.24#ibcon#ireg 8 cls_cnt 0 2006.201.15:21:15.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:15.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:15.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:15.24#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:21:15.24#ibcon#first serial, iclass 18, count 0 2006.201.15:21:15.24#ibcon#enter sib2, iclass 18, count 0 2006.201.15:21:15.24#ibcon#flushed, iclass 18, count 0 2006.201.15:21:15.24#ibcon#about to write, iclass 18, count 0 2006.201.15:21:15.24#ibcon#wrote, iclass 18, count 0 2006.201.15:21:15.24#ibcon#about to read 3, iclass 18, count 0 2006.201.15:21:15.26#ibcon#read 3, iclass 18, count 0 2006.201.15:21:15.26#ibcon#about to read 4, iclass 18, count 0 2006.201.15:21:15.26#ibcon#read 4, iclass 18, count 0 2006.201.15:21:15.26#ibcon#about to read 5, iclass 18, count 0 2006.201.15:21:15.26#ibcon#read 5, iclass 18, count 0 2006.201.15:21:15.26#ibcon#about to read 6, iclass 18, count 0 2006.201.15:21:15.26#ibcon#read 6, iclass 18, count 0 2006.201.15:21:15.26#ibcon#end of sib2, iclass 18, count 0 2006.201.15:21:15.26#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:21:15.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:21:15.26#ibcon#[25=BW32\r\n] 2006.201.15:21:15.26#ibcon#*before write, iclass 18, count 0 2006.201.15:21:15.26#ibcon#enter sib2, iclass 18, count 0 2006.201.15:21:15.26#ibcon#flushed, iclass 18, count 0 2006.201.15:21:15.26#ibcon#about to write, iclass 18, count 0 2006.201.15:21:15.26#ibcon#wrote, iclass 18, count 0 2006.201.15:21:15.26#ibcon#about to read 3, iclass 18, count 0 2006.201.15:21:15.29#ibcon#read 3, iclass 18, count 0 2006.201.15:21:15.29#ibcon#about to read 4, iclass 18, count 0 2006.201.15:21:15.29#ibcon#read 4, iclass 18, count 0 2006.201.15:21:15.29#ibcon#about to read 5, iclass 18, count 0 2006.201.15:21:15.29#ibcon#read 5, iclass 18, count 0 2006.201.15:21:15.29#ibcon#about to read 6, iclass 18, count 0 2006.201.15:21:15.29#ibcon#read 6, iclass 18, count 0 2006.201.15:21:15.29#ibcon#end of sib2, iclass 18, count 0 2006.201.15:21:15.29#ibcon#*after write, iclass 18, count 0 2006.201.15:21:15.29#ibcon#*before return 0, iclass 18, count 0 2006.201.15:21:15.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:15.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:21:15.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:21:15.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:21:15.29$vck44/vbbw=wide 2006.201.15:21:15.29#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.15:21:15.29#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.15:21:15.29#ibcon#ireg 8 cls_cnt 0 2006.201.15:21:15.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:21:15.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:21:15.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:21:15.36#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:21:15.36#ibcon#first serial, iclass 20, count 0 2006.201.15:21:15.36#ibcon#enter sib2, iclass 20, count 0 2006.201.15:21:15.36#ibcon#flushed, iclass 20, count 0 2006.201.15:21:15.36#ibcon#about to write, iclass 20, count 0 2006.201.15:21:15.36#ibcon#wrote, iclass 20, count 0 2006.201.15:21:15.36#ibcon#about to read 3, iclass 20, count 0 2006.201.15:21:15.38#ibcon#read 3, iclass 20, count 0 2006.201.15:21:15.38#ibcon#about to read 4, iclass 20, count 0 2006.201.15:21:15.38#ibcon#read 4, iclass 20, count 0 2006.201.15:21:15.38#ibcon#about to read 5, iclass 20, count 0 2006.201.15:21:15.38#ibcon#read 5, iclass 20, count 0 2006.201.15:21:15.38#ibcon#about to read 6, iclass 20, count 0 2006.201.15:21:15.38#ibcon#read 6, iclass 20, count 0 2006.201.15:21:15.38#ibcon#end of sib2, iclass 20, count 0 2006.201.15:21:15.38#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:21:15.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:21:15.38#ibcon#[27=BW32\r\n] 2006.201.15:21:15.38#ibcon#*before write, iclass 20, count 0 2006.201.15:21:15.38#ibcon#enter sib2, iclass 20, count 0 2006.201.15:21:15.38#ibcon#flushed, iclass 20, count 0 2006.201.15:21:15.38#ibcon#about to write, iclass 20, count 0 2006.201.15:21:15.38#ibcon#wrote, iclass 20, count 0 2006.201.15:21:15.38#ibcon#about to read 3, iclass 20, count 0 2006.201.15:21:15.41#ibcon#read 3, iclass 20, count 0 2006.201.15:21:15.41#ibcon#about to read 4, iclass 20, count 0 2006.201.15:21:15.41#ibcon#read 4, iclass 20, count 0 2006.201.15:21:15.41#ibcon#about to read 5, iclass 20, count 0 2006.201.15:21:15.41#ibcon#read 5, iclass 20, count 0 2006.201.15:21:15.41#ibcon#about to read 6, iclass 20, count 0 2006.201.15:21:15.41#ibcon#read 6, iclass 20, count 0 2006.201.15:21:15.41#ibcon#end of sib2, iclass 20, count 0 2006.201.15:21:15.41#ibcon#*after write, iclass 20, count 0 2006.201.15:21:15.41#ibcon#*before return 0, iclass 20, count 0 2006.201.15:21:15.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:21:15.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:21:15.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:21:15.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:21:15.41$setupk4/ifdk4 2006.201.15:21:15.41$ifdk4/lo= 2006.201.15:21:15.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:21:15.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:21:15.41$ifdk4/patch= 2006.201.15:21:15.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:21:15.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:21:15.41$setupk4/!*+20s 2006.201.15:21:24.11#abcon#<5=/04 1.1 2.4 20.801001003.2\r\n> 2006.201.15:21:24.13#abcon#{5=INTERFACE CLEAR} 2006.201.15:21:24.19#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:21:29.87$setupk4/"tpicd 2006.201.15:21:29.87$setupk4/echo=off 2006.201.15:21:29.87$setupk4/xlog=off 2006.201.15:21:29.87:!2006.201.15:23:16 2006.201.15:21:52.13#trakl#Source acquired 2006.201.15:21:53.13#flagr#flagr/antenna,acquired 2006.201.15:23:16.00:preob 2006.201.15:23:16.14/onsource/TRACKING 2006.201.15:23:16.14:!2006.201.15:23:26 2006.201.15:23:26.00:"tape 2006.201.15:23:26.00:"st=record 2006.201.15:23:26.00:data_valid=on 2006.201.15:23:26.00:midob 2006.201.15:23:26.14/onsource/TRACKING 2006.201.15:23:26.14/wx/20.81,1003.2,100 2006.201.15:23:26.37/cable/+6.4765E-03 2006.201.15:23:27.46/va/01,08,usb,yes,29,32 2006.201.15:23:27.46/va/02,07,usb,yes,32,33 2006.201.15:23:27.46/va/03,08,usb,yes,29,30 2006.201.15:23:27.46/va/04,07,usb,yes,33,34 2006.201.15:23:27.46/va/05,04,usb,yes,29,29 2006.201.15:23:27.46/va/06,05,usb,yes,29,29 2006.201.15:23:27.46/va/07,05,usb,yes,28,29 2006.201.15:23:27.46/va/08,04,usb,yes,28,34 2006.201.15:23:27.69/valo/01,524.99,yes,locked 2006.201.15:23:27.69/valo/02,534.99,yes,locked 2006.201.15:23:27.69/valo/03,564.99,yes,locked 2006.201.15:23:27.69/valo/04,624.99,yes,locked 2006.201.15:23:27.69/valo/05,734.99,yes,locked 2006.201.15:23:27.69/valo/06,814.99,yes,locked 2006.201.15:23:27.69/valo/07,864.99,yes,locked 2006.201.15:23:27.69/valo/08,884.99,yes,locked 2006.201.15:23:28.78/vb/01,04,usb,yes,29,27 2006.201.15:23:28.78/vb/02,05,usb,yes,28,27 2006.201.15:23:28.78/vb/03,04,usb,yes,28,31 2006.201.15:23:28.78/vb/04,05,usb,yes,29,28 2006.201.15:23:28.78/vb/05,04,usb,yes,25,28 2006.201.15:23:28.78/vb/06,04,usb,yes,30,26 2006.201.15:23:28.78/vb/07,04,usb,yes,30,29 2006.201.15:23:28.78/vb/08,04,usb,yes,27,30 2006.201.15:23:29.01/vblo/01,629.99,yes,locked 2006.201.15:23:29.01/vblo/02,634.99,yes,locked 2006.201.15:23:29.01/vblo/03,649.99,yes,locked 2006.201.15:23:29.01/vblo/04,679.99,yes,locked 2006.201.15:23:29.01/vblo/05,709.99,yes,locked 2006.201.15:23:29.01/vblo/06,719.99,yes,locked 2006.201.15:23:29.01/vblo/07,734.99,yes,locked 2006.201.15:23:29.01/vblo/08,744.99,yes,locked 2006.201.15:23:29.16/vabw/8 2006.201.15:23:29.31/vbbw/8 2006.201.15:23:29.43/xfe/off,on,14.5 2006.201.15:23:29.81/ifatt/23,28,28,28 2006.201.15:23:30.06/fmout-gps/S +4.56E-07 2006.201.15:23:30.13:!2006.201.15:32:06 2006.201.15:32:06.00:data_valid=off 2006.201.15:32:06.00:"et 2006.201.15:32:06.00:!+3s 2006.201.15:32:09.02:"tape 2006.201.15:32:09.02:postob 2006.201.15:32:09.12/cable/+6.4758E-03 2006.201.15:32:09.12/wx/20.84,1003.0,100 2006.201.15:32:09.19/fmout-gps/S +4.51E-07 2006.201.15:32:09.19:scan_name=201-1537,jd0607,170 2006.201.15:32:09.19:source=3c446,222547.26,-045701.4,2000.0,cw 2006.201.15:32:11.14#flagr#flagr/antenna,new-source 2006.201.15:32:11.14:checkk5 2006.201.15:32:11.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:32:11.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:32:12.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:32:12.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:32:13.34/chk_obsdata//k5ts1/T2011523??a.dat file size is correct (nominal:2080MB, actual:2076MB). 2006.201.15:32:14.01/chk_obsdata//k5ts2/T2011523??b.dat file size is correct (nominal:2080MB, actual:2076MB). 2006.201.15:32:14.69/chk_obsdata//k5ts3/T2011523??c.dat file size is correct (nominal:2080MB, actual:2076MB). 2006.201.15:32:15.37/chk_obsdata//k5ts4/T2011523??d.dat file size is correct (nominal:2080MB, actual:2076MB). 2006.201.15:32:16.05/k5log//k5ts1_log_newline 2006.201.15:32:16.74/k5log//k5ts2_log_newline 2006.201.15:32:17.42/k5log//k5ts3_log_newline 2006.201.15:32:18.12/k5log//k5ts4_log_newline 2006.201.15:32:18.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:32:18.14:setupk4=1 2006.201.15:32:18.14$setupk4/echo=on 2006.201.15:32:18.14$setupk4/pcalon 2006.201.15:32:18.14$pcalon/"no phase cal control is implemented here 2006.201.15:32:18.14$setupk4/"tpicd=stop 2006.201.15:32:18.14$setupk4/"rec=synch_on 2006.201.15:32:18.14$setupk4/"rec_mode=128 2006.201.15:32:18.14$setupk4/!* 2006.201.15:32:18.14$setupk4/recpk4 2006.201.15:32:18.14$recpk4/recpatch= 2006.201.15:32:18.15$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:32:18.15$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:32:18.15$setupk4/vck44 2006.201.15:32:18.15$vck44/valo=1,524.99 2006.201.15:32:18.15#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.15:32:18.15#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.15:32:18.15#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:18.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:18.15#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:18.15#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:18.15#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:32:18.15#ibcon#first serial, iclass 33, count 0 2006.201.15:32:18.15#ibcon#enter sib2, iclass 33, count 0 2006.201.15:32:18.15#ibcon#flushed, iclass 33, count 0 2006.201.15:32:18.15#ibcon#about to write, iclass 33, count 0 2006.201.15:32:18.15#ibcon#wrote, iclass 33, count 0 2006.201.15:32:18.15#ibcon#about to read 3, iclass 33, count 0 2006.201.15:32:18.18#ibcon#read 3, iclass 33, count 0 2006.201.15:32:18.18#ibcon#about to read 4, iclass 33, count 0 2006.201.15:32:18.18#ibcon#read 4, iclass 33, count 0 2006.201.15:32:18.18#ibcon#about to read 5, iclass 33, count 0 2006.201.15:32:18.18#ibcon#read 5, iclass 33, count 0 2006.201.15:32:18.18#ibcon#about to read 6, iclass 33, count 0 2006.201.15:32:18.18#ibcon#read 6, iclass 33, count 0 2006.201.15:32:18.18#ibcon#end of sib2, iclass 33, count 0 2006.201.15:32:18.18#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:32:18.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:32:18.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:32:18.18#ibcon#*before write, iclass 33, count 0 2006.201.15:32:18.18#ibcon#enter sib2, iclass 33, count 0 2006.201.15:32:18.18#ibcon#flushed, iclass 33, count 0 2006.201.15:32:18.18#ibcon#about to write, iclass 33, count 0 2006.201.15:32:18.18#ibcon#wrote, iclass 33, count 0 2006.201.15:32:18.18#ibcon#about to read 3, iclass 33, count 0 2006.201.15:32:18.23#ibcon#read 3, iclass 33, count 0 2006.201.15:32:18.23#ibcon#about to read 4, iclass 33, count 0 2006.201.15:32:18.23#ibcon#read 4, iclass 33, count 0 2006.201.15:32:18.23#ibcon#about to read 5, iclass 33, count 0 2006.201.15:32:18.23#ibcon#read 5, iclass 33, count 0 2006.201.15:32:18.23#ibcon#about to read 6, iclass 33, count 0 2006.201.15:32:18.23#ibcon#read 6, iclass 33, count 0 2006.201.15:32:18.23#ibcon#end of sib2, iclass 33, count 0 2006.201.15:32:18.23#ibcon#*after write, iclass 33, count 0 2006.201.15:32:18.23#ibcon#*before return 0, iclass 33, count 0 2006.201.15:32:18.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:18.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:18.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:32:18.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:32:18.23$vck44/va=1,8 2006.201.15:32:18.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.15:32:18.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.15:32:18.23#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:18.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:18.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:18.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:18.23#ibcon#enter wrdev, iclass 35, count 2 2006.201.15:32:18.23#ibcon#first serial, iclass 35, count 2 2006.201.15:32:18.23#ibcon#enter sib2, iclass 35, count 2 2006.201.15:32:18.23#ibcon#flushed, iclass 35, count 2 2006.201.15:32:18.23#ibcon#about to write, iclass 35, count 2 2006.201.15:32:18.23#ibcon#wrote, iclass 35, count 2 2006.201.15:32:18.23#ibcon#about to read 3, iclass 35, count 2 2006.201.15:32:18.25#ibcon#read 3, iclass 35, count 2 2006.201.15:32:18.25#ibcon#about to read 4, iclass 35, count 2 2006.201.15:32:18.25#ibcon#read 4, iclass 35, count 2 2006.201.15:32:18.25#ibcon#about to read 5, iclass 35, count 2 2006.201.15:32:18.25#ibcon#read 5, iclass 35, count 2 2006.201.15:32:18.25#ibcon#about to read 6, iclass 35, count 2 2006.201.15:32:18.25#ibcon#read 6, iclass 35, count 2 2006.201.15:32:18.25#ibcon#end of sib2, iclass 35, count 2 2006.201.15:32:18.25#ibcon#*mode == 0, iclass 35, count 2 2006.201.15:32:18.25#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.15:32:18.25#ibcon#[25=AT01-08\r\n] 2006.201.15:32:18.25#ibcon#*before write, iclass 35, count 2 2006.201.15:32:18.25#ibcon#enter sib2, iclass 35, count 2 2006.201.15:32:18.25#ibcon#flushed, iclass 35, count 2 2006.201.15:32:18.25#ibcon#about to write, iclass 35, count 2 2006.201.15:32:18.25#ibcon#wrote, iclass 35, count 2 2006.201.15:32:18.25#ibcon#about to read 3, iclass 35, count 2 2006.201.15:32:18.28#ibcon#read 3, iclass 35, count 2 2006.201.15:32:18.28#ibcon#about to read 4, iclass 35, count 2 2006.201.15:32:18.28#ibcon#read 4, iclass 35, count 2 2006.201.15:32:18.28#ibcon#about to read 5, iclass 35, count 2 2006.201.15:32:18.28#ibcon#read 5, iclass 35, count 2 2006.201.15:32:18.28#ibcon#about to read 6, iclass 35, count 2 2006.201.15:32:18.28#ibcon#read 6, iclass 35, count 2 2006.201.15:32:18.28#ibcon#end of sib2, iclass 35, count 2 2006.201.15:32:18.28#ibcon#*after write, iclass 35, count 2 2006.201.15:32:18.28#ibcon#*before return 0, iclass 35, count 2 2006.201.15:32:18.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:18.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:18.28#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.15:32:18.28#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:18.28#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:18.40#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:18.40#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:18.40#ibcon#enter wrdev, iclass 35, count 0 2006.201.15:32:18.40#ibcon#first serial, iclass 35, count 0 2006.201.15:32:18.40#ibcon#enter sib2, iclass 35, count 0 2006.201.15:32:18.40#ibcon#flushed, iclass 35, count 0 2006.201.15:32:18.40#ibcon#about to write, iclass 35, count 0 2006.201.15:32:18.40#ibcon#wrote, iclass 35, count 0 2006.201.15:32:18.40#ibcon#about to read 3, iclass 35, count 0 2006.201.15:32:18.42#ibcon#read 3, iclass 35, count 0 2006.201.15:32:18.42#ibcon#about to read 4, iclass 35, count 0 2006.201.15:32:18.42#ibcon#read 4, iclass 35, count 0 2006.201.15:32:18.42#ibcon#about to read 5, iclass 35, count 0 2006.201.15:32:18.42#ibcon#read 5, iclass 35, count 0 2006.201.15:32:18.42#ibcon#about to read 6, iclass 35, count 0 2006.201.15:32:18.42#ibcon#read 6, iclass 35, count 0 2006.201.15:32:18.42#ibcon#end of sib2, iclass 35, count 0 2006.201.15:32:18.42#ibcon#*mode == 0, iclass 35, count 0 2006.201.15:32:18.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.15:32:18.42#ibcon#[25=USB\r\n] 2006.201.15:32:18.42#ibcon#*before write, iclass 35, count 0 2006.201.15:32:18.42#ibcon#enter sib2, iclass 35, count 0 2006.201.15:32:18.42#ibcon#flushed, iclass 35, count 0 2006.201.15:32:18.42#ibcon#about to write, iclass 35, count 0 2006.201.15:32:18.42#ibcon#wrote, iclass 35, count 0 2006.201.15:32:18.42#ibcon#about to read 3, iclass 35, count 0 2006.201.15:32:18.45#ibcon#read 3, iclass 35, count 0 2006.201.15:32:18.45#ibcon#about to read 4, iclass 35, count 0 2006.201.15:32:18.45#ibcon#read 4, iclass 35, count 0 2006.201.15:32:18.45#ibcon#about to read 5, iclass 35, count 0 2006.201.15:32:18.45#ibcon#read 5, iclass 35, count 0 2006.201.15:32:18.45#ibcon#about to read 6, iclass 35, count 0 2006.201.15:32:18.45#ibcon#read 6, iclass 35, count 0 2006.201.15:32:18.45#ibcon#end of sib2, iclass 35, count 0 2006.201.15:32:18.45#ibcon#*after write, iclass 35, count 0 2006.201.15:32:18.45#ibcon#*before return 0, iclass 35, count 0 2006.201.15:32:18.45#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:18.45#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:18.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.15:32:18.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.15:32:18.45$vck44/valo=2,534.99 2006.201.15:32:18.45#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.15:32:18.45#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.15:32:18.45#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:18.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:18.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:18.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:18.45#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:32:18.45#ibcon#first serial, iclass 37, count 0 2006.201.15:32:18.45#ibcon#enter sib2, iclass 37, count 0 2006.201.15:32:18.45#ibcon#flushed, iclass 37, count 0 2006.201.15:32:18.45#ibcon#about to write, iclass 37, count 0 2006.201.15:32:18.45#ibcon#wrote, iclass 37, count 0 2006.201.15:32:18.45#ibcon#about to read 3, iclass 37, count 0 2006.201.15:32:18.47#ibcon#read 3, iclass 37, count 0 2006.201.15:32:18.47#ibcon#about to read 4, iclass 37, count 0 2006.201.15:32:18.47#ibcon#read 4, iclass 37, count 0 2006.201.15:32:18.47#ibcon#about to read 5, iclass 37, count 0 2006.201.15:32:18.47#ibcon#read 5, iclass 37, count 0 2006.201.15:32:18.47#ibcon#about to read 6, iclass 37, count 0 2006.201.15:32:18.47#ibcon#read 6, iclass 37, count 0 2006.201.15:32:18.47#ibcon#end of sib2, iclass 37, count 0 2006.201.15:32:18.47#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:32:18.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:32:18.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:32:18.47#ibcon#*before write, iclass 37, count 0 2006.201.15:32:18.47#ibcon#enter sib2, iclass 37, count 0 2006.201.15:32:18.47#ibcon#flushed, iclass 37, count 0 2006.201.15:32:18.47#ibcon#about to write, iclass 37, count 0 2006.201.15:32:18.47#ibcon#wrote, iclass 37, count 0 2006.201.15:32:18.47#ibcon#about to read 3, iclass 37, count 0 2006.201.15:32:18.51#ibcon#read 3, iclass 37, count 0 2006.201.15:32:18.51#ibcon#about to read 4, iclass 37, count 0 2006.201.15:32:18.51#ibcon#read 4, iclass 37, count 0 2006.201.15:32:18.51#ibcon#about to read 5, iclass 37, count 0 2006.201.15:32:18.51#ibcon#read 5, iclass 37, count 0 2006.201.15:32:18.51#ibcon#about to read 6, iclass 37, count 0 2006.201.15:32:18.51#ibcon#read 6, iclass 37, count 0 2006.201.15:32:18.51#ibcon#end of sib2, iclass 37, count 0 2006.201.15:32:18.51#ibcon#*after write, iclass 37, count 0 2006.201.15:32:18.51#ibcon#*before return 0, iclass 37, count 0 2006.201.15:32:18.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:18.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:18.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:32:18.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:32:18.51$vck44/va=2,7 2006.201.15:32:18.51#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.15:32:18.51#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.15:32:18.51#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:18.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:18.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:18.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:18.57#ibcon#enter wrdev, iclass 39, count 2 2006.201.15:32:18.57#ibcon#first serial, iclass 39, count 2 2006.201.15:32:18.57#ibcon#enter sib2, iclass 39, count 2 2006.201.15:32:18.57#ibcon#flushed, iclass 39, count 2 2006.201.15:32:18.57#ibcon#about to write, iclass 39, count 2 2006.201.15:32:18.57#ibcon#wrote, iclass 39, count 2 2006.201.15:32:18.57#ibcon#about to read 3, iclass 39, count 2 2006.201.15:32:18.59#ibcon#read 3, iclass 39, count 2 2006.201.15:32:18.59#ibcon#about to read 4, iclass 39, count 2 2006.201.15:32:18.59#ibcon#read 4, iclass 39, count 2 2006.201.15:32:18.59#ibcon#about to read 5, iclass 39, count 2 2006.201.15:32:18.59#ibcon#read 5, iclass 39, count 2 2006.201.15:32:18.59#ibcon#about to read 6, iclass 39, count 2 2006.201.15:32:18.59#ibcon#read 6, iclass 39, count 2 2006.201.15:32:18.59#ibcon#end of sib2, iclass 39, count 2 2006.201.15:32:18.59#ibcon#*mode == 0, iclass 39, count 2 2006.201.15:32:18.59#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.15:32:18.59#ibcon#[25=AT02-07\r\n] 2006.201.15:32:18.59#ibcon#*before write, iclass 39, count 2 2006.201.15:32:18.59#ibcon#enter sib2, iclass 39, count 2 2006.201.15:32:18.59#ibcon#flushed, iclass 39, count 2 2006.201.15:32:18.59#ibcon#about to write, iclass 39, count 2 2006.201.15:32:18.59#ibcon#wrote, iclass 39, count 2 2006.201.15:32:18.59#ibcon#about to read 3, iclass 39, count 2 2006.201.15:32:18.62#ibcon#read 3, iclass 39, count 2 2006.201.15:32:18.62#ibcon#about to read 4, iclass 39, count 2 2006.201.15:32:18.62#ibcon#read 4, iclass 39, count 2 2006.201.15:32:18.62#ibcon#about to read 5, iclass 39, count 2 2006.201.15:32:18.62#ibcon#read 5, iclass 39, count 2 2006.201.15:32:18.62#ibcon#about to read 6, iclass 39, count 2 2006.201.15:32:18.62#ibcon#read 6, iclass 39, count 2 2006.201.15:32:18.62#ibcon#end of sib2, iclass 39, count 2 2006.201.15:32:18.62#ibcon#*after write, iclass 39, count 2 2006.201.15:32:18.62#ibcon#*before return 0, iclass 39, count 2 2006.201.15:32:18.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:18.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:18.62#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.15:32:18.62#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:18.62#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:18.74#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:18.74#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:18.74#ibcon#enter wrdev, iclass 39, count 0 2006.201.15:32:18.74#ibcon#first serial, iclass 39, count 0 2006.201.15:32:18.74#ibcon#enter sib2, iclass 39, count 0 2006.201.15:32:18.74#ibcon#flushed, iclass 39, count 0 2006.201.15:32:18.74#ibcon#about to write, iclass 39, count 0 2006.201.15:32:18.74#ibcon#wrote, iclass 39, count 0 2006.201.15:32:18.74#ibcon#about to read 3, iclass 39, count 0 2006.201.15:32:18.76#ibcon#read 3, iclass 39, count 0 2006.201.15:32:18.76#ibcon#about to read 4, iclass 39, count 0 2006.201.15:32:18.76#ibcon#read 4, iclass 39, count 0 2006.201.15:32:18.76#ibcon#about to read 5, iclass 39, count 0 2006.201.15:32:18.76#ibcon#read 5, iclass 39, count 0 2006.201.15:32:18.76#ibcon#about to read 6, iclass 39, count 0 2006.201.15:32:18.76#ibcon#read 6, iclass 39, count 0 2006.201.15:32:18.76#ibcon#end of sib2, iclass 39, count 0 2006.201.15:32:18.76#ibcon#*mode == 0, iclass 39, count 0 2006.201.15:32:18.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.15:32:18.76#ibcon#[25=USB\r\n] 2006.201.15:32:18.76#ibcon#*before write, iclass 39, count 0 2006.201.15:32:18.76#ibcon#enter sib2, iclass 39, count 0 2006.201.15:32:18.76#ibcon#flushed, iclass 39, count 0 2006.201.15:32:18.76#ibcon#about to write, iclass 39, count 0 2006.201.15:32:18.76#ibcon#wrote, iclass 39, count 0 2006.201.15:32:18.76#ibcon#about to read 3, iclass 39, count 0 2006.201.15:32:18.79#ibcon#read 3, iclass 39, count 0 2006.201.15:32:18.79#ibcon#about to read 4, iclass 39, count 0 2006.201.15:32:18.79#ibcon#read 4, iclass 39, count 0 2006.201.15:32:18.79#ibcon#about to read 5, iclass 39, count 0 2006.201.15:32:18.79#ibcon#read 5, iclass 39, count 0 2006.201.15:32:18.79#ibcon#about to read 6, iclass 39, count 0 2006.201.15:32:18.79#ibcon#read 6, iclass 39, count 0 2006.201.15:32:18.79#ibcon#end of sib2, iclass 39, count 0 2006.201.15:32:18.79#ibcon#*after write, iclass 39, count 0 2006.201.15:32:18.79#ibcon#*before return 0, iclass 39, count 0 2006.201.15:32:18.79#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:18.79#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:18.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.15:32:18.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.15:32:18.79$vck44/valo=3,564.99 2006.201.15:32:18.79#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.15:32:18.79#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.15:32:18.79#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:18.79#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:18.79#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:18.79#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:18.79#ibcon#enter wrdev, iclass 2, count 0 2006.201.15:32:18.79#ibcon#first serial, iclass 2, count 0 2006.201.15:32:18.79#ibcon#enter sib2, iclass 2, count 0 2006.201.15:32:18.79#ibcon#flushed, iclass 2, count 0 2006.201.15:32:18.79#ibcon#about to write, iclass 2, count 0 2006.201.15:32:18.79#ibcon#wrote, iclass 2, count 0 2006.201.15:32:18.79#ibcon#about to read 3, iclass 2, count 0 2006.201.15:32:18.81#ibcon#read 3, iclass 2, count 0 2006.201.15:32:18.81#ibcon#about to read 4, iclass 2, count 0 2006.201.15:32:18.81#ibcon#read 4, iclass 2, count 0 2006.201.15:32:18.81#ibcon#about to read 5, iclass 2, count 0 2006.201.15:32:18.81#ibcon#read 5, iclass 2, count 0 2006.201.15:32:18.81#ibcon#about to read 6, iclass 2, count 0 2006.201.15:32:18.81#ibcon#read 6, iclass 2, count 0 2006.201.15:32:18.81#ibcon#end of sib2, iclass 2, count 0 2006.201.15:32:18.81#ibcon#*mode == 0, iclass 2, count 0 2006.201.15:32:18.81#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.15:32:18.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:32:18.81#ibcon#*before write, iclass 2, count 0 2006.201.15:32:18.81#ibcon#enter sib2, iclass 2, count 0 2006.201.15:32:18.81#ibcon#flushed, iclass 2, count 0 2006.201.15:32:18.81#ibcon#about to write, iclass 2, count 0 2006.201.15:32:18.81#ibcon#wrote, iclass 2, count 0 2006.201.15:32:18.81#ibcon#about to read 3, iclass 2, count 0 2006.201.15:32:18.86#ibcon#read 3, iclass 2, count 0 2006.201.15:32:18.86#ibcon#about to read 4, iclass 2, count 0 2006.201.15:32:18.86#ibcon#read 4, iclass 2, count 0 2006.201.15:32:18.86#ibcon#about to read 5, iclass 2, count 0 2006.201.15:32:18.86#ibcon#read 5, iclass 2, count 0 2006.201.15:32:18.86#ibcon#about to read 6, iclass 2, count 0 2006.201.15:32:18.86#ibcon#read 6, iclass 2, count 0 2006.201.15:32:18.86#ibcon#end of sib2, iclass 2, count 0 2006.201.15:32:18.86#ibcon#*after write, iclass 2, count 0 2006.201.15:32:18.86#ibcon#*before return 0, iclass 2, count 0 2006.201.15:32:18.86#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:18.86#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:18.86#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.15:32:18.86#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.15:32:18.86$vck44/va=3,8 2006.201.15:32:18.86#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.15:32:18.86#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.15:32:18.86#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:18.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:18.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:18.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:18.91#ibcon#enter wrdev, iclass 5, count 2 2006.201.15:32:18.91#ibcon#first serial, iclass 5, count 2 2006.201.15:32:18.91#ibcon#enter sib2, iclass 5, count 2 2006.201.15:32:18.91#ibcon#flushed, iclass 5, count 2 2006.201.15:32:18.91#ibcon#about to write, iclass 5, count 2 2006.201.15:32:18.91#ibcon#wrote, iclass 5, count 2 2006.201.15:32:18.91#ibcon#about to read 3, iclass 5, count 2 2006.201.15:32:18.93#ibcon#read 3, iclass 5, count 2 2006.201.15:32:18.93#ibcon#about to read 4, iclass 5, count 2 2006.201.15:32:18.93#ibcon#read 4, iclass 5, count 2 2006.201.15:32:18.93#ibcon#about to read 5, iclass 5, count 2 2006.201.15:32:18.93#ibcon#read 5, iclass 5, count 2 2006.201.15:32:18.93#ibcon#about to read 6, iclass 5, count 2 2006.201.15:32:18.93#ibcon#read 6, iclass 5, count 2 2006.201.15:32:18.93#ibcon#end of sib2, iclass 5, count 2 2006.201.15:32:18.93#ibcon#*mode == 0, iclass 5, count 2 2006.201.15:32:18.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.15:32:18.93#ibcon#[25=AT03-08\r\n] 2006.201.15:32:18.93#ibcon#*before write, iclass 5, count 2 2006.201.15:32:18.93#ibcon#enter sib2, iclass 5, count 2 2006.201.15:32:18.93#ibcon#flushed, iclass 5, count 2 2006.201.15:32:18.93#ibcon#about to write, iclass 5, count 2 2006.201.15:32:18.93#ibcon#wrote, iclass 5, count 2 2006.201.15:32:18.93#ibcon#about to read 3, iclass 5, count 2 2006.201.15:32:18.96#ibcon#read 3, iclass 5, count 2 2006.201.15:32:18.96#ibcon#about to read 4, iclass 5, count 2 2006.201.15:32:18.96#ibcon#read 4, iclass 5, count 2 2006.201.15:32:18.96#ibcon#about to read 5, iclass 5, count 2 2006.201.15:32:18.96#ibcon#read 5, iclass 5, count 2 2006.201.15:32:18.96#ibcon#about to read 6, iclass 5, count 2 2006.201.15:32:18.96#ibcon#read 6, iclass 5, count 2 2006.201.15:32:18.96#ibcon#end of sib2, iclass 5, count 2 2006.201.15:32:18.96#ibcon#*after write, iclass 5, count 2 2006.201.15:32:18.96#ibcon#*before return 0, iclass 5, count 2 2006.201.15:32:18.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:18.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:18.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.15:32:18.96#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:18.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:19.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:19.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:19.08#ibcon#enter wrdev, iclass 5, count 0 2006.201.15:32:19.08#ibcon#first serial, iclass 5, count 0 2006.201.15:32:19.08#ibcon#enter sib2, iclass 5, count 0 2006.201.15:32:19.08#ibcon#flushed, iclass 5, count 0 2006.201.15:32:19.08#ibcon#about to write, iclass 5, count 0 2006.201.15:32:19.08#ibcon#wrote, iclass 5, count 0 2006.201.15:32:19.08#ibcon#about to read 3, iclass 5, count 0 2006.201.15:32:19.10#ibcon#read 3, iclass 5, count 0 2006.201.15:32:19.10#ibcon#about to read 4, iclass 5, count 0 2006.201.15:32:19.10#ibcon#read 4, iclass 5, count 0 2006.201.15:32:19.10#ibcon#about to read 5, iclass 5, count 0 2006.201.15:32:19.10#ibcon#read 5, iclass 5, count 0 2006.201.15:32:19.10#ibcon#about to read 6, iclass 5, count 0 2006.201.15:32:19.10#ibcon#read 6, iclass 5, count 0 2006.201.15:32:19.10#ibcon#end of sib2, iclass 5, count 0 2006.201.15:32:19.10#ibcon#*mode == 0, iclass 5, count 0 2006.201.15:32:19.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.15:32:19.10#ibcon#[25=USB\r\n] 2006.201.15:32:19.10#ibcon#*before write, iclass 5, count 0 2006.201.15:32:19.10#ibcon#enter sib2, iclass 5, count 0 2006.201.15:32:19.10#ibcon#flushed, iclass 5, count 0 2006.201.15:32:19.10#ibcon#about to write, iclass 5, count 0 2006.201.15:32:19.10#ibcon#wrote, iclass 5, count 0 2006.201.15:32:19.10#ibcon#about to read 3, iclass 5, count 0 2006.201.15:32:19.13#ibcon#read 3, iclass 5, count 0 2006.201.15:32:19.13#ibcon#about to read 4, iclass 5, count 0 2006.201.15:32:19.13#ibcon#read 4, iclass 5, count 0 2006.201.15:32:19.13#ibcon#about to read 5, iclass 5, count 0 2006.201.15:32:19.13#ibcon#read 5, iclass 5, count 0 2006.201.15:32:19.13#ibcon#about to read 6, iclass 5, count 0 2006.201.15:32:19.13#ibcon#read 6, iclass 5, count 0 2006.201.15:32:19.13#ibcon#end of sib2, iclass 5, count 0 2006.201.15:32:19.13#ibcon#*after write, iclass 5, count 0 2006.201.15:32:19.13#ibcon#*before return 0, iclass 5, count 0 2006.201.15:32:19.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:19.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:19.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.15:32:19.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.15:32:19.13$vck44/valo=4,624.99 2006.201.15:32:19.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.15:32:19.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.15:32:19.13#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:19.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:19.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:19.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:19.13#ibcon#enter wrdev, iclass 7, count 0 2006.201.15:32:19.13#ibcon#first serial, iclass 7, count 0 2006.201.15:32:19.13#ibcon#enter sib2, iclass 7, count 0 2006.201.15:32:19.13#ibcon#flushed, iclass 7, count 0 2006.201.15:32:19.13#ibcon#about to write, iclass 7, count 0 2006.201.15:32:19.13#ibcon#wrote, iclass 7, count 0 2006.201.15:32:19.13#ibcon#about to read 3, iclass 7, count 0 2006.201.15:32:19.15#ibcon#read 3, iclass 7, count 0 2006.201.15:32:19.15#ibcon#about to read 4, iclass 7, count 0 2006.201.15:32:19.15#ibcon#read 4, iclass 7, count 0 2006.201.15:32:19.15#ibcon#about to read 5, iclass 7, count 0 2006.201.15:32:19.15#ibcon#read 5, iclass 7, count 0 2006.201.15:32:19.15#ibcon#about to read 6, iclass 7, count 0 2006.201.15:32:19.15#ibcon#read 6, iclass 7, count 0 2006.201.15:32:19.15#ibcon#end of sib2, iclass 7, count 0 2006.201.15:32:19.15#ibcon#*mode == 0, iclass 7, count 0 2006.201.15:32:19.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.15:32:19.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:32:19.15#ibcon#*before write, iclass 7, count 0 2006.201.15:32:19.15#ibcon#enter sib2, iclass 7, count 0 2006.201.15:32:19.15#ibcon#flushed, iclass 7, count 0 2006.201.15:32:19.15#ibcon#about to write, iclass 7, count 0 2006.201.15:32:19.15#ibcon#wrote, iclass 7, count 0 2006.201.15:32:19.15#ibcon#about to read 3, iclass 7, count 0 2006.201.15:32:19.19#ibcon#read 3, iclass 7, count 0 2006.201.15:32:19.19#ibcon#about to read 4, iclass 7, count 0 2006.201.15:32:19.19#ibcon#read 4, iclass 7, count 0 2006.201.15:32:19.19#ibcon#about to read 5, iclass 7, count 0 2006.201.15:32:19.19#ibcon#read 5, iclass 7, count 0 2006.201.15:32:19.19#ibcon#about to read 6, iclass 7, count 0 2006.201.15:32:19.19#ibcon#read 6, iclass 7, count 0 2006.201.15:32:19.19#ibcon#end of sib2, iclass 7, count 0 2006.201.15:32:19.19#ibcon#*after write, iclass 7, count 0 2006.201.15:32:19.19#ibcon#*before return 0, iclass 7, count 0 2006.201.15:32:19.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:19.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:19.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.15:32:19.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.15:32:19.19$vck44/va=4,7 2006.201.15:32:19.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.15:32:19.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.15:32:19.19#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:19.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:19.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:19.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:19.25#ibcon#enter wrdev, iclass 11, count 2 2006.201.15:32:19.25#ibcon#first serial, iclass 11, count 2 2006.201.15:32:19.25#ibcon#enter sib2, iclass 11, count 2 2006.201.15:32:19.25#ibcon#flushed, iclass 11, count 2 2006.201.15:32:19.25#ibcon#about to write, iclass 11, count 2 2006.201.15:32:19.25#ibcon#wrote, iclass 11, count 2 2006.201.15:32:19.25#ibcon#about to read 3, iclass 11, count 2 2006.201.15:32:19.27#ibcon#read 3, iclass 11, count 2 2006.201.15:32:19.27#ibcon#about to read 4, iclass 11, count 2 2006.201.15:32:19.27#ibcon#read 4, iclass 11, count 2 2006.201.15:32:19.27#ibcon#about to read 5, iclass 11, count 2 2006.201.15:32:19.27#ibcon#read 5, iclass 11, count 2 2006.201.15:32:19.27#ibcon#about to read 6, iclass 11, count 2 2006.201.15:32:19.27#ibcon#read 6, iclass 11, count 2 2006.201.15:32:19.27#ibcon#end of sib2, iclass 11, count 2 2006.201.15:32:19.27#ibcon#*mode == 0, iclass 11, count 2 2006.201.15:32:19.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.15:32:19.27#ibcon#[25=AT04-07\r\n] 2006.201.15:32:19.27#ibcon#*before write, iclass 11, count 2 2006.201.15:32:19.27#ibcon#enter sib2, iclass 11, count 2 2006.201.15:32:19.27#ibcon#flushed, iclass 11, count 2 2006.201.15:32:19.27#ibcon#about to write, iclass 11, count 2 2006.201.15:32:19.27#ibcon#wrote, iclass 11, count 2 2006.201.15:32:19.27#ibcon#about to read 3, iclass 11, count 2 2006.201.15:32:19.30#ibcon#read 3, iclass 11, count 2 2006.201.15:32:19.30#ibcon#about to read 4, iclass 11, count 2 2006.201.15:32:19.30#ibcon#read 4, iclass 11, count 2 2006.201.15:32:19.30#ibcon#about to read 5, iclass 11, count 2 2006.201.15:32:19.30#ibcon#read 5, iclass 11, count 2 2006.201.15:32:19.30#ibcon#about to read 6, iclass 11, count 2 2006.201.15:32:19.30#ibcon#read 6, iclass 11, count 2 2006.201.15:32:19.30#ibcon#end of sib2, iclass 11, count 2 2006.201.15:32:19.30#ibcon#*after write, iclass 11, count 2 2006.201.15:32:19.30#ibcon#*before return 0, iclass 11, count 2 2006.201.15:32:19.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:19.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:19.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.15:32:19.30#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:19.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:19.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:19.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:19.42#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:32:19.42#ibcon#first serial, iclass 11, count 0 2006.201.15:32:19.42#ibcon#enter sib2, iclass 11, count 0 2006.201.15:32:19.42#ibcon#flushed, iclass 11, count 0 2006.201.15:32:19.42#ibcon#about to write, iclass 11, count 0 2006.201.15:32:19.42#ibcon#wrote, iclass 11, count 0 2006.201.15:32:19.42#ibcon#about to read 3, iclass 11, count 0 2006.201.15:32:19.44#ibcon#read 3, iclass 11, count 0 2006.201.15:32:19.44#ibcon#about to read 4, iclass 11, count 0 2006.201.15:32:19.44#ibcon#read 4, iclass 11, count 0 2006.201.15:32:19.44#ibcon#about to read 5, iclass 11, count 0 2006.201.15:32:19.44#ibcon#read 5, iclass 11, count 0 2006.201.15:32:19.44#ibcon#about to read 6, iclass 11, count 0 2006.201.15:32:19.44#ibcon#read 6, iclass 11, count 0 2006.201.15:32:19.44#ibcon#end of sib2, iclass 11, count 0 2006.201.15:32:19.44#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:32:19.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:32:19.44#ibcon#[25=USB\r\n] 2006.201.15:32:19.44#ibcon#*before write, iclass 11, count 0 2006.201.15:32:19.44#ibcon#enter sib2, iclass 11, count 0 2006.201.15:32:19.44#ibcon#flushed, iclass 11, count 0 2006.201.15:32:19.44#ibcon#about to write, iclass 11, count 0 2006.201.15:32:19.44#ibcon#wrote, iclass 11, count 0 2006.201.15:32:19.44#ibcon#about to read 3, iclass 11, count 0 2006.201.15:32:19.47#ibcon#read 3, iclass 11, count 0 2006.201.15:32:19.47#ibcon#about to read 4, iclass 11, count 0 2006.201.15:32:19.47#ibcon#read 4, iclass 11, count 0 2006.201.15:32:19.47#ibcon#about to read 5, iclass 11, count 0 2006.201.15:32:19.47#ibcon#read 5, iclass 11, count 0 2006.201.15:32:19.47#ibcon#about to read 6, iclass 11, count 0 2006.201.15:32:19.47#ibcon#read 6, iclass 11, count 0 2006.201.15:32:19.47#ibcon#end of sib2, iclass 11, count 0 2006.201.15:32:19.47#ibcon#*after write, iclass 11, count 0 2006.201.15:32:19.47#ibcon#*before return 0, iclass 11, count 0 2006.201.15:32:19.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:19.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:19.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:32:19.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:32:19.47$vck44/valo=5,734.99 2006.201.15:32:19.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.15:32:19.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.15:32:19.47#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:19.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:19.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:19.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:19.47#ibcon#enter wrdev, iclass 13, count 0 2006.201.15:32:19.47#ibcon#first serial, iclass 13, count 0 2006.201.15:32:19.47#ibcon#enter sib2, iclass 13, count 0 2006.201.15:32:19.47#ibcon#flushed, iclass 13, count 0 2006.201.15:32:19.47#ibcon#about to write, iclass 13, count 0 2006.201.15:32:19.47#ibcon#wrote, iclass 13, count 0 2006.201.15:32:19.47#ibcon#about to read 3, iclass 13, count 0 2006.201.15:32:19.49#ibcon#read 3, iclass 13, count 0 2006.201.15:32:19.49#ibcon#about to read 4, iclass 13, count 0 2006.201.15:32:19.49#ibcon#read 4, iclass 13, count 0 2006.201.15:32:19.49#ibcon#about to read 5, iclass 13, count 0 2006.201.15:32:19.49#ibcon#read 5, iclass 13, count 0 2006.201.15:32:19.49#ibcon#about to read 6, iclass 13, count 0 2006.201.15:32:19.49#ibcon#read 6, iclass 13, count 0 2006.201.15:32:19.49#ibcon#end of sib2, iclass 13, count 0 2006.201.15:32:19.49#ibcon#*mode == 0, iclass 13, count 0 2006.201.15:32:19.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.15:32:19.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:32:19.49#ibcon#*before write, iclass 13, count 0 2006.201.15:32:19.49#ibcon#enter sib2, iclass 13, count 0 2006.201.15:32:19.49#ibcon#flushed, iclass 13, count 0 2006.201.15:32:19.49#ibcon#about to write, iclass 13, count 0 2006.201.15:32:19.49#ibcon#wrote, iclass 13, count 0 2006.201.15:32:19.49#ibcon#about to read 3, iclass 13, count 0 2006.201.15:32:19.53#ibcon#read 3, iclass 13, count 0 2006.201.15:32:19.53#ibcon#about to read 4, iclass 13, count 0 2006.201.15:32:19.53#ibcon#read 4, iclass 13, count 0 2006.201.15:32:19.53#ibcon#about to read 5, iclass 13, count 0 2006.201.15:32:19.53#ibcon#read 5, iclass 13, count 0 2006.201.15:32:19.53#ibcon#about to read 6, iclass 13, count 0 2006.201.15:32:19.53#ibcon#read 6, iclass 13, count 0 2006.201.15:32:19.53#ibcon#end of sib2, iclass 13, count 0 2006.201.15:32:19.53#ibcon#*after write, iclass 13, count 0 2006.201.15:32:19.53#ibcon#*before return 0, iclass 13, count 0 2006.201.15:32:19.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:19.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:19.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.15:32:19.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.15:32:19.53$vck44/va=5,4 2006.201.15:32:19.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.15:32:19.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.15:32:19.53#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:19.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:19.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:19.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:19.59#ibcon#enter wrdev, iclass 15, count 2 2006.201.15:32:19.59#ibcon#first serial, iclass 15, count 2 2006.201.15:32:19.59#ibcon#enter sib2, iclass 15, count 2 2006.201.15:32:19.59#ibcon#flushed, iclass 15, count 2 2006.201.15:32:19.59#ibcon#about to write, iclass 15, count 2 2006.201.15:32:19.59#ibcon#wrote, iclass 15, count 2 2006.201.15:32:19.59#ibcon#about to read 3, iclass 15, count 2 2006.201.15:32:19.61#ibcon#read 3, iclass 15, count 2 2006.201.15:32:19.61#ibcon#about to read 4, iclass 15, count 2 2006.201.15:32:19.61#ibcon#read 4, iclass 15, count 2 2006.201.15:32:19.61#ibcon#about to read 5, iclass 15, count 2 2006.201.15:32:19.61#ibcon#read 5, iclass 15, count 2 2006.201.15:32:19.61#ibcon#about to read 6, iclass 15, count 2 2006.201.15:32:19.61#ibcon#read 6, iclass 15, count 2 2006.201.15:32:19.61#ibcon#end of sib2, iclass 15, count 2 2006.201.15:32:19.61#ibcon#*mode == 0, iclass 15, count 2 2006.201.15:32:19.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.15:32:19.61#ibcon#[25=AT05-04\r\n] 2006.201.15:32:19.61#ibcon#*before write, iclass 15, count 2 2006.201.15:32:19.61#ibcon#enter sib2, iclass 15, count 2 2006.201.15:32:19.61#ibcon#flushed, iclass 15, count 2 2006.201.15:32:19.61#ibcon#about to write, iclass 15, count 2 2006.201.15:32:19.61#ibcon#wrote, iclass 15, count 2 2006.201.15:32:19.61#ibcon#about to read 3, iclass 15, count 2 2006.201.15:32:19.64#ibcon#read 3, iclass 15, count 2 2006.201.15:32:19.64#ibcon#about to read 4, iclass 15, count 2 2006.201.15:32:19.64#ibcon#read 4, iclass 15, count 2 2006.201.15:32:19.64#ibcon#about to read 5, iclass 15, count 2 2006.201.15:32:19.64#ibcon#read 5, iclass 15, count 2 2006.201.15:32:19.64#ibcon#about to read 6, iclass 15, count 2 2006.201.15:32:19.64#ibcon#read 6, iclass 15, count 2 2006.201.15:32:19.64#ibcon#end of sib2, iclass 15, count 2 2006.201.15:32:19.64#ibcon#*after write, iclass 15, count 2 2006.201.15:32:19.64#ibcon#*before return 0, iclass 15, count 2 2006.201.15:32:19.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:19.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:19.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.15:32:19.64#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:19.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:19.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:19.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:19.76#ibcon#enter wrdev, iclass 15, count 0 2006.201.15:32:19.76#ibcon#first serial, iclass 15, count 0 2006.201.15:32:19.76#ibcon#enter sib2, iclass 15, count 0 2006.201.15:32:19.76#ibcon#flushed, iclass 15, count 0 2006.201.15:32:19.76#ibcon#about to write, iclass 15, count 0 2006.201.15:32:19.76#ibcon#wrote, iclass 15, count 0 2006.201.15:32:19.76#ibcon#about to read 3, iclass 15, count 0 2006.201.15:32:19.78#ibcon#read 3, iclass 15, count 0 2006.201.15:32:19.78#ibcon#about to read 4, iclass 15, count 0 2006.201.15:32:19.78#ibcon#read 4, iclass 15, count 0 2006.201.15:32:19.78#ibcon#about to read 5, iclass 15, count 0 2006.201.15:32:19.78#ibcon#read 5, iclass 15, count 0 2006.201.15:32:19.78#ibcon#about to read 6, iclass 15, count 0 2006.201.15:32:19.78#ibcon#read 6, iclass 15, count 0 2006.201.15:32:19.78#ibcon#end of sib2, iclass 15, count 0 2006.201.15:32:19.78#ibcon#*mode == 0, iclass 15, count 0 2006.201.15:32:19.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.15:32:19.78#ibcon#[25=USB\r\n] 2006.201.15:32:19.78#ibcon#*before write, iclass 15, count 0 2006.201.15:32:19.78#ibcon#enter sib2, iclass 15, count 0 2006.201.15:32:19.78#ibcon#flushed, iclass 15, count 0 2006.201.15:32:19.78#ibcon#about to write, iclass 15, count 0 2006.201.15:32:19.78#ibcon#wrote, iclass 15, count 0 2006.201.15:32:19.78#ibcon#about to read 3, iclass 15, count 0 2006.201.15:32:19.81#ibcon#read 3, iclass 15, count 0 2006.201.15:32:19.81#ibcon#about to read 4, iclass 15, count 0 2006.201.15:32:19.81#ibcon#read 4, iclass 15, count 0 2006.201.15:32:19.81#ibcon#about to read 5, iclass 15, count 0 2006.201.15:32:19.81#ibcon#read 5, iclass 15, count 0 2006.201.15:32:19.81#ibcon#about to read 6, iclass 15, count 0 2006.201.15:32:19.81#ibcon#read 6, iclass 15, count 0 2006.201.15:32:19.81#ibcon#end of sib2, iclass 15, count 0 2006.201.15:32:19.81#ibcon#*after write, iclass 15, count 0 2006.201.15:32:19.81#ibcon#*before return 0, iclass 15, count 0 2006.201.15:32:19.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:19.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:19.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.15:32:19.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.15:32:19.81$vck44/valo=6,814.99 2006.201.15:32:19.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.15:32:19.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.15:32:19.81#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:19.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:19.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:19.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:19.81#ibcon#enter wrdev, iclass 17, count 0 2006.201.15:32:19.81#ibcon#first serial, iclass 17, count 0 2006.201.15:32:19.81#ibcon#enter sib2, iclass 17, count 0 2006.201.15:32:19.81#ibcon#flushed, iclass 17, count 0 2006.201.15:32:19.81#ibcon#about to write, iclass 17, count 0 2006.201.15:32:19.81#ibcon#wrote, iclass 17, count 0 2006.201.15:32:19.81#ibcon#about to read 3, iclass 17, count 0 2006.201.15:32:19.83#ibcon#read 3, iclass 17, count 0 2006.201.15:32:19.83#ibcon#about to read 4, iclass 17, count 0 2006.201.15:32:19.83#ibcon#read 4, iclass 17, count 0 2006.201.15:32:19.83#ibcon#about to read 5, iclass 17, count 0 2006.201.15:32:19.83#ibcon#read 5, iclass 17, count 0 2006.201.15:32:19.83#ibcon#about to read 6, iclass 17, count 0 2006.201.15:32:19.83#ibcon#read 6, iclass 17, count 0 2006.201.15:32:19.83#ibcon#end of sib2, iclass 17, count 0 2006.201.15:32:19.83#ibcon#*mode == 0, iclass 17, count 0 2006.201.15:32:19.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.15:32:19.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:32:19.83#ibcon#*before write, iclass 17, count 0 2006.201.15:32:19.83#ibcon#enter sib2, iclass 17, count 0 2006.201.15:32:19.83#ibcon#flushed, iclass 17, count 0 2006.201.15:32:19.83#ibcon#about to write, iclass 17, count 0 2006.201.15:32:19.83#ibcon#wrote, iclass 17, count 0 2006.201.15:32:19.83#ibcon#about to read 3, iclass 17, count 0 2006.201.15:32:19.87#ibcon#read 3, iclass 17, count 0 2006.201.15:32:19.87#ibcon#about to read 4, iclass 17, count 0 2006.201.15:32:19.87#ibcon#read 4, iclass 17, count 0 2006.201.15:32:19.87#ibcon#about to read 5, iclass 17, count 0 2006.201.15:32:19.87#ibcon#read 5, iclass 17, count 0 2006.201.15:32:19.87#ibcon#about to read 6, iclass 17, count 0 2006.201.15:32:19.87#ibcon#read 6, iclass 17, count 0 2006.201.15:32:19.87#ibcon#end of sib2, iclass 17, count 0 2006.201.15:32:19.87#ibcon#*after write, iclass 17, count 0 2006.201.15:32:19.87#ibcon#*before return 0, iclass 17, count 0 2006.201.15:32:19.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:19.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:19.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.15:32:19.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.15:32:19.87$vck44/va=6,5 2006.201.15:32:19.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.15:32:19.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.15:32:19.87#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:19.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:19.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:19.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:19.93#ibcon#enter wrdev, iclass 19, count 2 2006.201.15:32:19.93#ibcon#first serial, iclass 19, count 2 2006.201.15:32:19.93#ibcon#enter sib2, iclass 19, count 2 2006.201.15:32:19.93#ibcon#flushed, iclass 19, count 2 2006.201.15:32:19.93#ibcon#about to write, iclass 19, count 2 2006.201.15:32:19.93#ibcon#wrote, iclass 19, count 2 2006.201.15:32:19.93#ibcon#about to read 3, iclass 19, count 2 2006.201.15:32:19.95#ibcon#read 3, iclass 19, count 2 2006.201.15:32:19.95#ibcon#about to read 4, iclass 19, count 2 2006.201.15:32:19.95#ibcon#read 4, iclass 19, count 2 2006.201.15:32:19.95#ibcon#about to read 5, iclass 19, count 2 2006.201.15:32:19.95#ibcon#read 5, iclass 19, count 2 2006.201.15:32:19.95#ibcon#about to read 6, iclass 19, count 2 2006.201.15:32:19.95#ibcon#read 6, iclass 19, count 2 2006.201.15:32:19.95#ibcon#end of sib2, iclass 19, count 2 2006.201.15:32:19.95#ibcon#*mode == 0, iclass 19, count 2 2006.201.15:32:19.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.15:32:19.95#ibcon#[25=AT06-05\r\n] 2006.201.15:32:19.95#ibcon#*before write, iclass 19, count 2 2006.201.15:32:19.95#ibcon#enter sib2, iclass 19, count 2 2006.201.15:32:19.95#ibcon#flushed, iclass 19, count 2 2006.201.15:32:19.95#ibcon#about to write, iclass 19, count 2 2006.201.15:32:19.95#ibcon#wrote, iclass 19, count 2 2006.201.15:32:19.95#ibcon#about to read 3, iclass 19, count 2 2006.201.15:32:19.98#ibcon#read 3, iclass 19, count 2 2006.201.15:32:19.98#ibcon#about to read 4, iclass 19, count 2 2006.201.15:32:19.98#ibcon#read 4, iclass 19, count 2 2006.201.15:32:19.98#ibcon#about to read 5, iclass 19, count 2 2006.201.15:32:19.98#ibcon#read 5, iclass 19, count 2 2006.201.15:32:19.98#ibcon#about to read 6, iclass 19, count 2 2006.201.15:32:19.98#ibcon#read 6, iclass 19, count 2 2006.201.15:32:19.98#ibcon#end of sib2, iclass 19, count 2 2006.201.15:32:19.98#ibcon#*after write, iclass 19, count 2 2006.201.15:32:19.98#ibcon#*before return 0, iclass 19, count 2 2006.201.15:32:19.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:19.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:19.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.15:32:19.98#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:19.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:20.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:20.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:20.10#ibcon#enter wrdev, iclass 19, count 0 2006.201.15:32:20.10#ibcon#first serial, iclass 19, count 0 2006.201.15:32:20.10#ibcon#enter sib2, iclass 19, count 0 2006.201.15:32:20.10#ibcon#flushed, iclass 19, count 0 2006.201.15:32:20.10#ibcon#about to write, iclass 19, count 0 2006.201.15:32:20.10#ibcon#wrote, iclass 19, count 0 2006.201.15:32:20.10#ibcon#about to read 3, iclass 19, count 0 2006.201.15:32:20.12#ibcon#read 3, iclass 19, count 0 2006.201.15:32:20.12#ibcon#about to read 4, iclass 19, count 0 2006.201.15:32:20.12#ibcon#read 4, iclass 19, count 0 2006.201.15:32:20.12#ibcon#about to read 5, iclass 19, count 0 2006.201.15:32:20.12#ibcon#read 5, iclass 19, count 0 2006.201.15:32:20.12#ibcon#about to read 6, iclass 19, count 0 2006.201.15:32:20.12#ibcon#read 6, iclass 19, count 0 2006.201.15:32:20.12#ibcon#end of sib2, iclass 19, count 0 2006.201.15:32:20.12#ibcon#*mode == 0, iclass 19, count 0 2006.201.15:32:20.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.15:32:20.12#ibcon#[25=USB\r\n] 2006.201.15:32:20.12#ibcon#*before write, iclass 19, count 0 2006.201.15:32:20.12#ibcon#enter sib2, iclass 19, count 0 2006.201.15:32:20.12#ibcon#flushed, iclass 19, count 0 2006.201.15:32:20.12#ibcon#about to write, iclass 19, count 0 2006.201.15:32:20.12#ibcon#wrote, iclass 19, count 0 2006.201.15:32:20.12#ibcon#about to read 3, iclass 19, count 0 2006.201.15:32:20.15#ibcon#read 3, iclass 19, count 0 2006.201.15:32:20.15#ibcon#about to read 4, iclass 19, count 0 2006.201.15:32:20.15#ibcon#read 4, iclass 19, count 0 2006.201.15:32:20.15#ibcon#about to read 5, iclass 19, count 0 2006.201.15:32:20.15#ibcon#read 5, iclass 19, count 0 2006.201.15:32:20.15#ibcon#about to read 6, iclass 19, count 0 2006.201.15:32:20.15#ibcon#read 6, iclass 19, count 0 2006.201.15:32:20.15#ibcon#end of sib2, iclass 19, count 0 2006.201.15:32:20.15#ibcon#*after write, iclass 19, count 0 2006.201.15:32:20.15#ibcon#*before return 0, iclass 19, count 0 2006.201.15:32:20.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:20.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:20.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.15:32:20.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.15:32:20.15$vck44/valo=7,864.99 2006.201.15:32:20.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.15:32:20.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.15:32:20.15#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:20.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:20.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:20.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:20.15#ibcon#enter wrdev, iclass 21, count 0 2006.201.15:32:20.15#ibcon#first serial, iclass 21, count 0 2006.201.15:32:20.15#ibcon#enter sib2, iclass 21, count 0 2006.201.15:32:20.15#ibcon#flushed, iclass 21, count 0 2006.201.15:32:20.15#ibcon#about to write, iclass 21, count 0 2006.201.15:32:20.15#ibcon#wrote, iclass 21, count 0 2006.201.15:32:20.15#ibcon#about to read 3, iclass 21, count 0 2006.201.15:32:20.17#ibcon#read 3, iclass 21, count 0 2006.201.15:32:20.17#ibcon#about to read 4, iclass 21, count 0 2006.201.15:32:20.17#ibcon#read 4, iclass 21, count 0 2006.201.15:32:20.17#ibcon#about to read 5, iclass 21, count 0 2006.201.15:32:20.17#ibcon#read 5, iclass 21, count 0 2006.201.15:32:20.17#ibcon#about to read 6, iclass 21, count 0 2006.201.15:32:20.17#ibcon#read 6, iclass 21, count 0 2006.201.15:32:20.17#ibcon#end of sib2, iclass 21, count 0 2006.201.15:32:20.17#ibcon#*mode == 0, iclass 21, count 0 2006.201.15:32:20.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.15:32:20.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:32:20.17#ibcon#*before write, iclass 21, count 0 2006.201.15:32:20.17#ibcon#enter sib2, iclass 21, count 0 2006.201.15:32:20.17#ibcon#flushed, iclass 21, count 0 2006.201.15:32:20.17#ibcon#about to write, iclass 21, count 0 2006.201.15:32:20.17#ibcon#wrote, iclass 21, count 0 2006.201.15:32:20.17#ibcon#about to read 3, iclass 21, count 0 2006.201.15:32:20.21#ibcon#read 3, iclass 21, count 0 2006.201.15:32:20.21#ibcon#about to read 4, iclass 21, count 0 2006.201.15:32:20.21#ibcon#read 4, iclass 21, count 0 2006.201.15:32:20.21#ibcon#about to read 5, iclass 21, count 0 2006.201.15:32:20.21#ibcon#read 5, iclass 21, count 0 2006.201.15:32:20.21#ibcon#about to read 6, iclass 21, count 0 2006.201.15:32:20.21#ibcon#read 6, iclass 21, count 0 2006.201.15:32:20.21#ibcon#end of sib2, iclass 21, count 0 2006.201.15:32:20.21#ibcon#*after write, iclass 21, count 0 2006.201.15:32:20.21#ibcon#*before return 0, iclass 21, count 0 2006.201.15:32:20.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:20.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:20.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.15:32:20.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.15:32:20.21$vck44/va=7,5 2006.201.15:32:20.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.15:32:20.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.15:32:20.21#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:20.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:20.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:20.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:20.27#ibcon#enter wrdev, iclass 23, count 2 2006.201.15:32:20.27#ibcon#first serial, iclass 23, count 2 2006.201.15:32:20.27#ibcon#enter sib2, iclass 23, count 2 2006.201.15:32:20.27#ibcon#flushed, iclass 23, count 2 2006.201.15:32:20.27#ibcon#about to write, iclass 23, count 2 2006.201.15:32:20.27#ibcon#wrote, iclass 23, count 2 2006.201.15:32:20.27#ibcon#about to read 3, iclass 23, count 2 2006.201.15:32:20.29#ibcon#read 3, iclass 23, count 2 2006.201.15:32:20.29#ibcon#about to read 4, iclass 23, count 2 2006.201.15:32:20.29#ibcon#read 4, iclass 23, count 2 2006.201.15:32:20.29#ibcon#about to read 5, iclass 23, count 2 2006.201.15:32:20.29#ibcon#read 5, iclass 23, count 2 2006.201.15:32:20.29#ibcon#about to read 6, iclass 23, count 2 2006.201.15:32:20.29#ibcon#read 6, iclass 23, count 2 2006.201.15:32:20.29#ibcon#end of sib2, iclass 23, count 2 2006.201.15:32:20.29#ibcon#*mode == 0, iclass 23, count 2 2006.201.15:32:20.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.15:32:20.29#ibcon#[25=AT07-05\r\n] 2006.201.15:32:20.29#ibcon#*before write, iclass 23, count 2 2006.201.15:32:20.29#ibcon#enter sib2, iclass 23, count 2 2006.201.15:32:20.29#ibcon#flushed, iclass 23, count 2 2006.201.15:32:20.29#ibcon#about to write, iclass 23, count 2 2006.201.15:32:20.29#ibcon#wrote, iclass 23, count 2 2006.201.15:32:20.29#ibcon#about to read 3, iclass 23, count 2 2006.201.15:32:20.32#ibcon#read 3, iclass 23, count 2 2006.201.15:32:20.32#ibcon#about to read 4, iclass 23, count 2 2006.201.15:32:20.32#ibcon#read 4, iclass 23, count 2 2006.201.15:32:20.32#ibcon#about to read 5, iclass 23, count 2 2006.201.15:32:20.32#ibcon#read 5, iclass 23, count 2 2006.201.15:32:20.32#ibcon#about to read 6, iclass 23, count 2 2006.201.15:32:20.32#ibcon#read 6, iclass 23, count 2 2006.201.15:32:20.32#ibcon#end of sib2, iclass 23, count 2 2006.201.15:32:20.32#ibcon#*after write, iclass 23, count 2 2006.201.15:32:20.32#ibcon#*before return 0, iclass 23, count 2 2006.201.15:32:20.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:20.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:20.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.15:32:20.32#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:20.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:20.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:20.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:20.44#ibcon#enter wrdev, iclass 23, count 0 2006.201.15:32:20.44#ibcon#first serial, iclass 23, count 0 2006.201.15:32:20.44#ibcon#enter sib2, iclass 23, count 0 2006.201.15:32:20.44#ibcon#flushed, iclass 23, count 0 2006.201.15:32:20.44#ibcon#about to write, iclass 23, count 0 2006.201.15:32:20.44#ibcon#wrote, iclass 23, count 0 2006.201.15:32:20.44#ibcon#about to read 3, iclass 23, count 0 2006.201.15:32:20.46#ibcon#read 3, iclass 23, count 0 2006.201.15:32:20.46#ibcon#about to read 4, iclass 23, count 0 2006.201.15:32:20.46#ibcon#read 4, iclass 23, count 0 2006.201.15:32:20.46#ibcon#about to read 5, iclass 23, count 0 2006.201.15:32:20.46#ibcon#read 5, iclass 23, count 0 2006.201.15:32:20.46#ibcon#about to read 6, iclass 23, count 0 2006.201.15:32:20.46#ibcon#read 6, iclass 23, count 0 2006.201.15:32:20.46#ibcon#end of sib2, iclass 23, count 0 2006.201.15:32:20.46#ibcon#*mode == 0, iclass 23, count 0 2006.201.15:32:20.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.15:32:20.46#ibcon#[25=USB\r\n] 2006.201.15:32:20.46#ibcon#*before write, iclass 23, count 0 2006.201.15:32:20.46#ibcon#enter sib2, iclass 23, count 0 2006.201.15:32:20.46#ibcon#flushed, iclass 23, count 0 2006.201.15:32:20.46#ibcon#about to write, iclass 23, count 0 2006.201.15:32:20.46#ibcon#wrote, iclass 23, count 0 2006.201.15:32:20.46#ibcon#about to read 3, iclass 23, count 0 2006.201.15:32:20.49#ibcon#read 3, iclass 23, count 0 2006.201.15:32:20.49#ibcon#about to read 4, iclass 23, count 0 2006.201.15:32:20.49#ibcon#read 4, iclass 23, count 0 2006.201.15:32:20.49#ibcon#about to read 5, iclass 23, count 0 2006.201.15:32:20.49#ibcon#read 5, iclass 23, count 0 2006.201.15:32:20.49#ibcon#about to read 6, iclass 23, count 0 2006.201.15:32:20.49#ibcon#read 6, iclass 23, count 0 2006.201.15:32:20.49#ibcon#end of sib2, iclass 23, count 0 2006.201.15:32:20.49#ibcon#*after write, iclass 23, count 0 2006.201.15:32:20.49#ibcon#*before return 0, iclass 23, count 0 2006.201.15:32:20.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:20.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:20.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.15:32:20.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.15:32:20.49$vck44/valo=8,884.99 2006.201.15:32:20.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.15:32:20.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.15:32:20.49#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:20.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:20.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:20.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:20.49#ibcon#enter wrdev, iclass 25, count 0 2006.201.15:32:20.49#ibcon#first serial, iclass 25, count 0 2006.201.15:32:20.49#ibcon#enter sib2, iclass 25, count 0 2006.201.15:32:20.49#ibcon#flushed, iclass 25, count 0 2006.201.15:32:20.49#ibcon#about to write, iclass 25, count 0 2006.201.15:32:20.49#ibcon#wrote, iclass 25, count 0 2006.201.15:32:20.49#ibcon#about to read 3, iclass 25, count 0 2006.201.15:32:20.51#ibcon#read 3, iclass 25, count 0 2006.201.15:32:20.51#ibcon#about to read 4, iclass 25, count 0 2006.201.15:32:20.51#ibcon#read 4, iclass 25, count 0 2006.201.15:32:20.51#ibcon#about to read 5, iclass 25, count 0 2006.201.15:32:20.51#ibcon#read 5, iclass 25, count 0 2006.201.15:32:20.51#ibcon#about to read 6, iclass 25, count 0 2006.201.15:32:20.51#ibcon#read 6, iclass 25, count 0 2006.201.15:32:20.51#ibcon#end of sib2, iclass 25, count 0 2006.201.15:32:20.51#ibcon#*mode == 0, iclass 25, count 0 2006.201.15:32:20.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.15:32:20.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:32:20.51#ibcon#*before write, iclass 25, count 0 2006.201.15:32:20.51#ibcon#enter sib2, iclass 25, count 0 2006.201.15:32:20.51#ibcon#flushed, iclass 25, count 0 2006.201.15:32:20.51#ibcon#about to write, iclass 25, count 0 2006.201.15:32:20.51#ibcon#wrote, iclass 25, count 0 2006.201.15:32:20.51#ibcon#about to read 3, iclass 25, count 0 2006.201.15:32:20.55#ibcon#read 3, iclass 25, count 0 2006.201.15:32:20.55#ibcon#about to read 4, iclass 25, count 0 2006.201.15:32:20.55#ibcon#read 4, iclass 25, count 0 2006.201.15:32:20.55#ibcon#about to read 5, iclass 25, count 0 2006.201.15:32:20.55#ibcon#read 5, iclass 25, count 0 2006.201.15:32:20.55#ibcon#about to read 6, iclass 25, count 0 2006.201.15:32:20.55#ibcon#read 6, iclass 25, count 0 2006.201.15:32:20.55#ibcon#end of sib2, iclass 25, count 0 2006.201.15:32:20.55#ibcon#*after write, iclass 25, count 0 2006.201.15:32:20.55#ibcon#*before return 0, iclass 25, count 0 2006.201.15:32:20.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:20.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:20.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.15:32:20.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.15:32:20.55$vck44/va=8,4 2006.201.15:32:20.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.15:32:20.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.15:32:20.55#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:20.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:32:20.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:32:20.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:32:20.61#ibcon#enter wrdev, iclass 27, count 2 2006.201.15:32:20.61#ibcon#first serial, iclass 27, count 2 2006.201.15:32:20.61#ibcon#enter sib2, iclass 27, count 2 2006.201.15:32:20.61#ibcon#flushed, iclass 27, count 2 2006.201.15:32:20.61#ibcon#about to write, iclass 27, count 2 2006.201.15:32:20.61#ibcon#wrote, iclass 27, count 2 2006.201.15:32:20.61#ibcon#about to read 3, iclass 27, count 2 2006.201.15:32:20.63#ibcon#read 3, iclass 27, count 2 2006.201.15:32:20.63#ibcon#about to read 4, iclass 27, count 2 2006.201.15:32:20.63#ibcon#read 4, iclass 27, count 2 2006.201.15:32:20.63#ibcon#about to read 5, iclass 27, count 2 2006.201.15:32:20.63#ibcon#read 5, iclass 27, count 2 2006.201.15:32:20.63#ibcon#about to read 6, iclass 27, count 2 2006.201.15:32:20.63#ibcon#read 6, iclass 27, count 2 2006.201.15:32:20.63#ibcon#end of sib2, iclass 27, count 2 2006.201.15:32:20.63#ibcon#*mode == 0, iclass 27, count 2 2006.201.15:32:20.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.15:32:20.63#ibcon#[25=AT08-04\r\n] 2006.201.15:32:20.63#ibcon#*before write, iclass 27, count 2 2006.201.15:32:20.63#ibcon#enter sib2, iclass 27, count 2 2006.201.15:32:20.63#ibcon#flushed, iclass 27, count 2 2006.201.15:32:20.63#ibcon#about to write, iclass 27, count 2 2006.201.15:32:20.63#ibcon#wrote, iclass 27, count 2 2006.201.15:32:20.63#ibcon#about to read 3, iclass 27, count 2 2006.201.15:32:20.66#ibcon#read 3, iclass 27, count 2 2006.201.15:32:20.66#ibcon#about to read 4, iclass 27, count 2 2006.201.15:32:20.66#ibcon#read 4, iclass 27, count 2 2006.201.15:32:20.66#ibcon#about to read 5, iclass 27, count 2 2006.201.15:32:20.66#ibcon#read 5, iclass 27, count 2 2006.201.15:32:20.66#ibcon#about to read 6, iclass 27, count 2 2006.201.15:32:20.66#ibcon#read 6, iclass 27, count 2 2006.201.15:32:20.66#ibcon#end of sib2, iclass 27, count 2 2006.201.15:32:20.66#ibcon#*after write, iclass 27, count 2 2006.201.15:32:20.66#ibcon#*before return 0, iclass 27, count 2 2006.201.15:32:20.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:32:20.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:32:20.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.15:32:20.66#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:20.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:32:20.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:32:20.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:32:20.78#ibcon#enter wrdev, iclass 27, count 0 2006.201.15:32:20.78#ibcon#first serial, iclass 27, count 0 2006.201.15:32:20.78#ibcon#enter sib2, iclass 27, count 0 2006.201.15:32:20.78#ibcon#flushed, iclass 27, count 0 2006.201.15:32:20.78#ibcon#about to write, iclass 27, count 0 2006.201.15:32:20.78#ibcon#wrote, iclass 27, count 0 2006.201.15:32:20.78#ibcon#about to read 3, iclass 27, count 0 2006.201.15:32:20.80#ibcon#read 3, iclass 27, count 0 2006.201.15:32:20.80#ibcon#about to read 4, iclass 27, count 0 2006.201.15:32:20.80#ibcon#read 4, iclass 27, count 0 2006.201.15:32:20.80#ibcon#about to read 5, iclass 27, count 0 2006.201.15:32:20.80#ibcon#read 5, iclass 27, count 0 2006.201.15:32:20.80#ibcon#about to read 6, iclass 27, count 0 2006.201.15:32:20.80#ibcon#read 6, iclass 27, count 0 2006.201.15:32:20.80#ibcon#end of sib2, iclass 27, count 0 2006.201.15:32:20.80#ibcon#*mode == 0, iclass 27, count 0 2006.201.15:32:20.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.15:32:20.80#ibcon#[25=USB\r\n] 2006.201.15:32:20.80#ibcon#*before write, iclass 27, count 0 2006.201.15:32:20.80#ibcon#enter sib2, iclass 27, count 0 2006.201.15:32:20.80#ibcon#flushed, iclass 27, count 0 2006.201.15:32:20.80#ibcon#about to write, iclass 27, count 0 2006.201.15:32:20.80#ibcon#wrote, iclass 27, count 0 2006.201.15:32:20.80#ibcon#about to read 3, iclass 27, count 0 2006.201.15:32:20.83#ibcon#read 3, iclass 27, count 0 2006.201.15:32:20.83#ibcon#about to read 4, iclass 27, count 0 2006.201.15:32:20.83#ibcon#read 4, iclass 27, count 0 2006.201.15:32:20.83#ibcon#about to read 5, iclass 27, count 0 2006.201.15:32:20.83#ibcon#read 5, iclass 27, count 0 2006.201.15:32:20.83#ibcon#about to read 6, iclass 27, count 0 2006.201.15:32:20.83#ibcon#read 6, iclass 27, count 0 2006.201.15:32:20.83#ibcon#end of sib2, iclass 27, count 0 2006.201.15:32:20.83#ibcon#*after write, iclass 27, count 0 2006.201.15:32:20.83#ibcon#*before return 0, iclass 27, count 0 2006.201.15:32:20.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:32:20.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:32:20.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.15:32:20.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.15:32:20.83$vck44/vblo=1,629.99 2006.201.15:32:20.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.15:32:20.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.15:32:20.83#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:20.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:32:20.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:32:20.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:32:20.83#ibcon#enter wrdev, iclass 29, count 0 2006.201.15:32:20.83#ibcon#first serial, iclass 29, count 0 2006.201.15:32:20.83#ibcon#enter sib2, iclass 29, count 0 2006.201.15:32:20.83#ibcon#flushed, iclass 29, count 0 2006.201.15:32:20.83#ibcon#about to write, iclass 29, count 0 2006.201.15:32:20.83#ibcon#wrote, iclass 29, count 0 2006.201.15:32:20.83#ibcon#about to read 3, iclass 29, count 0 2006.201.15:32:20.85#ibcon#read 3, iclass 29, count 0 2006.201.15:32:20.85#ibcon#about to read 4, iclass 29, count 0 2006.201.15:32:20.85#ibcon#read 4, iclass 29, count 0 2006.201.15:32:20.85#ibcon#about to read 5, iclass 29, count 0 2006.201.15:32:20.85#ibcon#read 5, iclass 29, count 0 2006.201.15:32:20.85#ibcon#about to read 6, iclass 29, count 0 2006.201.15:32:20.85#ibcon#read 6, iclass 29, count 0 2006.201.15:32:20.85#ibcon#end of sib2, iclass 29, count 0 2006.201.15:32:20.85#ibcon#*mode == 0, iclass 29, count 0 2006.201.15:32:20.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.15:32:20.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:32:20.85#ibcon#*before write, iclass 29, count 0 2006.201.15:32:20.85#ibcon#enter sib2, iclass 29, count 0 2006.201.15:32:20.85#ibcon#flushed, iclass 29, count 0 2006.201.15:32:20.85#ibcon#about to write, iclass 29, count 0 2006.201.15:32:20.85#ibcon#wrote, iclass 29, count 0 2006.201.15:32:20.85#ibcon#about to read 3, iclass 29, count 0 2006.201.15:32:20.90#ibcon#read 3, iclass 29, count 0 2006.201.15:32:20.90#ibcon#about to read 4, iclass 29, count 0 2006.201.15:32:20.90#ibcon#read 4, iclass 29, count 0 2006.201.15:32:20.90#ibcon#about to read 5, iclass 29, count 0 2006.201.15:32:20.90#ibcon#read 5, iclass 29, count 0 2006.201.15:32:20.90#ibcon#about to read 6, iclass 29, count 0 2006.201.15:32:20.90#ibcon#read 6, iclass 29, count 0 2006.201.15:32:20.90#ibcon#end of sib2, iclass 29, count 0 2006.201.15:32:20.90#ibcon#*after write, iclass 29, count 0 2006.201.15:32:20.90#ibcon#*before return 0, iclass 29, count 0 2006.201.15:32:20.90#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:32:20.90#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:32:20.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.15:32:20.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.15:32:20.90$vck44/vb=1,4 2006.201.15:32:20.90#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.15:32:20.90#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.15:32:20.90#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:20.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:32:20.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:32:20.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:32:20.90#ibcon#enter wrdev, iclass 31, count 2 2006.201.15:32:20.90#ibcon#first serial, iclass 31, count 2 2006.201.15:32:20.90#ibcon#enter sib2, iclass 31, count 2 2006.201.15:32:20.90#ibcon#flushed, iclass 31, count 2 2006.201.15:32:20.90#ibcon#about to write, iclass 31, count 2 2006.201.15:32:20.90#ibcon#wrote, iclass 31, count 2 2006.201.15:32:20.90#ibcon#about to read 3, iclass 31, count 2 2006.201.15:32:20.92#ibcon#read 3, iclass 31, count 2 2006.201.15:32:20.92#ibcon#about to read 4, iclass 31, count 2 2006.201.15:32:20.92#ibcon#read 4, iclass 31, count 2 2006.201.15:32:20.92#ibcon#about to read 5, iclass 31, count 2 2006.201.15:32:20.92#ibcon#read 5, iclass 31, count 2 2006.201.15:32:20.92#ibcon#about to read 6, iclass 31, count 2 2006.201.15:32:20.92#ibcon#read 6, iclass 31, count 2 2006.201.15:32:20.92#ibcon#end of sib2, iclass 31, count 2 2006.201.15:32:20.92#ibcon#*mode == 0, iclass 31, count 2 2006.201.15:32:20.92#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.15:32:20.92#ibcon#[27=AT01-04\r\n] 2006.201.15:32:20.92#ibcon#*before write, iclass 31, count 2 2006.201.15:32:20.92#ibcon#enter sib2, iclass 31, count 2 2006.201.15:32:20.92#ibcon#flushed, iclass 31, count 2 2006.201.15:32:20.92#ibcon#about to write, iclass 31, count 2 2006.201.15:32:20.92#ibcon#wrote, iclass 31, count 2 2006.201.15:32:20.92#ibcon#about to read 3, iclass 31, count 2 2006.201.15:32:20.95#ibcon#read 3, iclass 31, count 2 2006.201.15:32:20.95#ibcon#about to read 4, iclass 31, count 2 2006.201.15:32:20.95#ibcon#read 4, iclass 31, count 2 2006.201.15:32:20.95#ibcon#about to read 5, iclass 31, count 2 2006.201.15:32:20.95#ibcon#read 5, iclass 31, count 2 2006.201.15:32:20.95#ibcon#about to read 6, iclass 31, count 2 2006.201.15:32:20.95#ibcon#read 6, iclass 31, count 2 2006.201.15:32:20.95#ibcon#end of sib2, iclass 31, count 2 2006.201.15:32:20.95#ibcon#*after write, iclass 31, count 2 2006.201.15:32:20.95#ibcon#*before return 0, iclass 31, count 2 2006.201.15:32:20.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:32:20.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:32:20.95#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.15:32:20.95#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:20.95#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:32:21.07#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:32:21.07#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:32:21.07#ibcon#enter wrdev, iclass 31, count 0 2006.201.15:32:21.07#ibcon#first serial, iclass 31, count 0 2006.201.15:32:21.07#ibcon#enter sib2, iclass 31, count 0 2006.201.15:32:21.07#ibcon#flushed, iclass 31, count 0 2006.201.15:32:21.07#ibcon#about to write, iclass 31, count 0 2006.201.15:32:21.07#ibcon#wrote, iclass 31, count 0 2006.201.15:32:21.07#ibcon#about to read 3, iclass 31, count 0 2006.201.15:32:21.09#ibcon#read 3, iclass 31, count 0 2006.201.15:32:21.09#ibcon#about to read 4, iclass 31, count 0 2006.201.15:32:21.09#ibcon#read 4, iclass 31, count 0 2006.201.15:32:21.09#ibcon#about to read 5, iclass 31, count 0 2006.201.15:32:21.09#ibcon#read 5, iclass 31, count 0 2006.201.15:32:21.09#ibcon#about to read 6, iclass 31, count 0 2006.201.15:32:21.09#ibcon#read 6, iclass 31, count 0 2006.201.15:32:21.09#ibcon#end of sib2, iclass 31, count 0 2006.201.15:32:21.09#ibcon#*mode == 0, iclass 31, count 0 2006.201.15:32:21.09#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.15:32:21.09#ibcon#[27=USB\r\n] 2006.201.15:32:21.09#ibcon#*before write, iclass 31, count 0 2006.201.15:32:21.09#ibcon#enter sib2, iclass 31, count 0 2006.201.15:32:21.09#ibcon#flushed, iclass 31, count 0 2006.201.15:32:21.09#ibcon#about to write, iclass 31, count 0 2006.201.15:32:21.09#ibcon#wrote, iclass 31, count 0 2006.201.15:32:21.09#ibcon#about to read 3, iclass 31, count 0 2006.201.15:32:21.12#ibcon#read 3, iclass 31, count 0 2006.201.15:32:21.12#ibcon#about to read 4, iclass 31, count 0 2006.201.15:32:21.12#ibcon#read 4, iclass 31, count 0 2006.201.15:32:21.12#ibcon#about to read 5, iclass 31, count 0 2006.201.15:32:21.12#ibcon#read 5, iclass 31, count 0 2006.201.15:32:21.12#ibcon#about to read 6, iclass 31, count 0 2006.201.15:32:21.12#ibcon#read 6, iclass 31, count 0 2006.201.15:32:21.12#ibcon#end of sib2, iclass 31, count 0 2006.201.15:32:21.12#ibcon#*after write, iclass 31, count 0 2006.201.15:32:21.12#ibcon#*before return 0, iclass 31, count 0 2006.201.15:32:21.12#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:32:21.12#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:32:21.12#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.15:32:21.12#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.15:32:21.12$vck44/vblo=2,634.99 2006.201.15:32:21.12#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.15:32:21.12#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.15:32:21.12#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:21.12#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:21.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:21.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:21.12#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:32:21.12#ibcon#first serial, iclass 33, count 0 2006.201.15:32:21.12#ibcon#enter sib2, iclass 33, count 0 2006.201.15:32:21.12#ibcon#flushed, iclass 33, count 0 2006.201.15:32:21.12#ibcon#about to write, iclass 33, count 0 2006.201.15:32:21.12#ibcon#wrote, iclass 33, count 0 2006.201.15:32:21.12#ibcon#about to read 3, iclass 33, count 0 2006.201.15:32:21.14#ibcon#read 3, iclass 33, count 0 2006.201.15:32:21.14#ibcon#about to read 4, iclass 33, count 0 2006.201.15:32:21.14#ibcon#read 4, iclass 33, count 0 2006.201.15:32:21.14#ibcon#about to read 5, iclass 33, count 0 2006.201.15:32:21.14#ibcon#read 5, iclass 33, count 0 2006.201.15:32:21.14#ibcon#about to read 6, iclass 33, count 0 2006.201.15:32:21.14#ibcon#read 6, iclass 33, count 0 2006.201.15:32:21.14#ibcon#end of sib2, iclass 33, count 0 2006.201.15:32:21.14#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:32:21.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:32:21.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:32:21.14#ibcon#*before write, iclass 33, count 0 2006.201.15:32:21.14#ibcon#enter sib2, iclass 33, count 0 2006.201.15:32:21.14#ibcon#flushed, iclass 33, count 0 2006.201.15:32:21.14#ibcon#about to write, iclass 33, count 0 2006.201.15:32:21.14#ibcon#wrote, iclass 33, count 0 2006.201.15:32:21.14#ibcon#about to read 3, iclass 33, count 0 2006.201.15:32:21.18#ibcon#read 3, iclass 33, count 0 2006.201.15:32:21.18#ibcon#about to read 4, iclass 33, count 0 2006.201.15:32:21.18#ibcon#read 4, iclass 33, count 0 2006.201.15:32:21.18#ibcon#about to read 5, iclass 33, count 0 2006.201.15:32:21.18#ibcon#read 5, iclass 33, count 0 2006.201.15:32:21.18#ibcon#about to read 6, iclass 33, count 0 2006.201.15:32:21.18#ibcon#read 6, iclass 33, count 0 2006.201.15:32:21.18#ibcon#end of sib2, iclass 33, count 0 2006.201.15:32:21.18#ibcon#*after write, iclass 33, count 0 2006.201.15:32:21.18#ibcon#*before return 0, iclass 33, count 0 2006.201.15:32:21.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:21.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:32:21.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:32:21.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:32:21.18$vck44/vb=2,5 2006.201.15:32:21.18#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.15:32:21.18#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.15:32:21.18#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:21.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:21.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:21.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:21.24#ibcon#enter wrdev, iclass 35, count 2 2006.201.15:32:21.24#ibcon#first serial, iclass 35, count 2 2006.201.15:32:21.24#ibcon#enter sib2, iclass 35, count 2 2006.201.15:32:21.24#ibcon#flushed, iclass 35, count 2 2006.201.15:32:21.24#ibcon#about to write, iclass 35, count 2 2006.201.15:32:21.24#ibcon#wrote, iclass 35, count 2 2006.201.15:32:21.24#ibcon#about to read 3, iclass 35, count 2 2006.201.15:32:21.26#ibcon#read 3, iclass 35, count 2 2006.201.15:32:21.26#ibcon#about to read 4, iclass 35, count 2 2006.201.15:32:21.26#ibcon#read 4, iclass 35, count 2 2006.201.15:32:21.26#ibcon#about to read 5, iclass 35, count 2 2006.201.15:32:21.26#ibcon#read 5, iclass 35, count 2 2006.201.15:32:21.26#ibcon#about to read 6, iclass 35, count 2 2006.201.15:32:21.26#ibcon#read 6, iclass 35, count 2 2006.201.15:32:21.26#ibcon#end of sib2, iclass 35, count 2 2006.201.15:32:21.26#ibcon#*mode == 0, iclass 35, count 2 2006.201.15:32:21.26#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.15:32:21.26#ibcon#[27=AT02-05\r\n] 2006.201.15:32:21.26#ibcon#*before write, iclass 35, count 2 2006.201.15:32:21.26#ibcon#enter sib2, iclass 35, count 2 2006.201.15:32:21.26#ibcon#flushed, iclass 35, count 2 2006.201.15:32:21.26#ibcon#about to write, iclass 35, count 2 2006.201.15:32:21.26#ibcon#wrote, iclass 35, count 2 2006.201.15:32:21.26#ibcon#about to read 3, iclass 35, count 2 2006.201.15:32:21.29#ibcon#read 3, iclass 35, count 2 2006.201.15:32:21.29#ibcon#about to read 4, iclass 35, count 2 2006.201.15:32:21.29#ibcon#read 4, iclass 35, count 2 2006.201.15:32:21.29#ibcon#about to read 5, iclass 35, count 2 2006.201.15:32:21.29#ibcon#read 5, iclass 35, count 2 2006.201.15:32:21.29#ibcon#about to read 6, iclass 35, count 2 2006.201.15:32:21.29#ibcon#read 6, iclass 35, count 2 2006.201.15:32:21.29#ibcon#end of sib2, iclass 35, count 2 2006.201.15:32:21.29#ibcon#*after write, iclass 35, count 2 2006.201.15:32:21.29#ibcon#*before return 0, iclass 35, count 2 2006.201.15:32:21.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:21.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:32:21.29#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.15:32:21.29#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:21.29#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:21.41#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:21.41#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:21.41#ibcon#enter wrdev, iclass 35, count 0 2006.201.15:32:21.41#ibcon#first serial, iclass 35, count 0 2006.201.15:32:21.41#ibcon#enter sib2, iclass 35, count 0 2006.201.15:32:21.41#ibcon#flushed, iclass 35, count 0 2006.201.15:32:21.41#ibcon#about to write, iclass 35, count 0 2006.201.15:32:21.41#ibcon#wrote, iclass 35, count 0 2006.201.15:32:21.41#ibcon#about to read 3, iclass 35, count 0 2006.201.15:32:21.43#ibcon#read 3, iclass 35, count 0 2006.201.15:32:21.43#ibcon#about to read 4, iclass 35, count 0 2006.201.15:32:21.43#ibcon#read 4, iclass 35, count 0 2006.201.15:32:21.43#ibcon#about to read 5, iclass 35, count 0 2006.201.15:32:21.43#ibcon#read 5, iclass 35, count 0 2006.201.15:32:21.43#ibcon#about to read 6, iclass 35, count 0 2006.201.15:32:21.43#ibcon#read 6, iclass 35, count 0 2006.201.15:32:21.43#ibcon#end of sib2, iclass 35, count 0 2006.201.15:32:21.43#ibcon#*mode == 0, iclass 35, count 0 2006.201.15:32:21.43#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.15:32:21.43#ibcon#[27=USB\r\n] 2006.201.15:32:21.43#ibcon#*before write, iclass 35, count 0 2006.201.15:32:21.43#ibcon#enter sib2, iclass 35, count 0 2006.201.15:32:21.43#ibcon#flushed, iclass 35, count 0 2006.201.15:32:21.43#ibcon#about to write, iclass 35, count 0 2006.201.15:32:21.43#ibcon#wrote, iclass 35, count 0 2006.201.15:32:21.43#ibcon#about to read 3, iclass 35, count 0 2006.201.15:32:21.46#ibcon#read 3, iclass 35, count 0 2006.201.15:32:21.46#ibcon#about to read 4, iclass 35, count 0 2006.201.15:32:21.46#ibcon#read 4, iclass 35, count 0 2006.201.15:32:21.46#ibcon#about to read 5, iclass 35, count 0 2006.201.15:32:21.46#ibcon#read 5, iclass 35, count 0 2006.201.15:32:21.46#ibcon#about to read 6, iclass 35, count 0 2006.201.15:32:21.46#ibcon#read 6, iclass 35, count 0 2006.201.15:32:21.46#ibcon#end of sib2, iclass 35, count 0 2006.201.15:32:21.46#ibcon#*after write, iclass 35, count 0 2006.201.15:32:21.46#ibcon#*before return 0, iclass 35, count 0 2006.201.15:32:21.46#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:21.46#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:32:21.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.15:32:21.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.15:32:21.46$vck44/vblo=3,649.99 2006.201.15:32:21.46#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.15:32:21.46#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.15:32:21.46#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:21.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:21.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:21.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:21.46#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:32:21.46#ibcon#first serial, iclass 37, count 0 2006.201.15:32:21.46#ibcon#enter sib2, iclass 37, count 0 2006.201.15:32:21.46#ibcon#flushed, iclass 37, count 0 2006.201.15:32:21.46#ibcon#about to write, iclass 37, count 0 2006.201.15:32:21.46#ibcon#wrote, iclass 37, count 0 2006.201.15:32:21.46#ibcon#about to read 3, iclass 37, count 0 2006.201.15:32:21.48#ibcon#read 3, iclass 37, count 0 2006.201.15:32:21.48#ibcon#about to read 4, iclass 37, count 0 2006.201.15:32:21.48#ibcon#read 4, iclass 37, count 0 2006.201.15:32:21.48#ibcon#about to read 5, iclass 37, count 0 2006.201.15:32:21.48#ibcon#read 5, iclass 37, count 0 2006.201.15:32:21.48#ibcon#about to read 6, iclass 37, count 0 2006.201.15:32:21.48#ibcon#read 6, iclass 37, count 0 2006.201.15:32:21.48#ibcon#end of sib2, iclass 37, count 0 2006.201.15:32:21.48#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:32:21.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:32:21.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:32:21.48#ibcon#*before write, iclass 37, count 0 2006.201.15:32:21.48#ibcon#enter sib2, iclass 37, count 0 2006.201.15:32:21.48#ibcon#flushed, iclass 37, count 0 2006.201.15:32:21.48#ibcon#about to write, iclass 37, count 0 2006.201.15:32:21.48#ibcon#wrote, iclass 37, count 0 2006.201.15:32:21.48#ibcon#about to read 3, iclass 37, count 0 2006.201.15:32:21.53#ibcon#read 3, iclass 37, count 0 2006.201.15:32:21.53#ibcon#about to read 4, iclass 37, count 0 2006.201.15:32:21.53#ibcon#read 4, iclass 37, count 0 2006.201.15:32:21.53#ibcon#about to read 5, iclass 37, count 0 2006.201.15:32:21.53#ibcon#read 5, iclass 37, count 0 2006.201.15:32:21.53#ibcon#about to read 6, iclass 37, count 0 2006.201.15:32:21.53#ibcon#read 6, iclass 37, count 0 2006.201.15:32:21.53#ibcon#end of sib2, iclass 37, count 0 2006.201.15:32:21.53#ibcon#*after write, iclass 37, count 0 2006.201.15:32:21.53#ibcon#*before return 0, iclass 37, count 0 2006.201.15:32:21.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:21.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:32:21.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:32:21.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:32:21.53$vck44/vb=3,4 2006.201.15:32:21.53#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.15:32:21.53#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.15:32:21.53#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:21.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:21.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:21.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:21.58#ibcon#enter wrdev, iclass 39, count 2 2006.201.15:32:21.58#ibcon#first serial, iclass 39, count 2 2006.201.15:32:21.58#ibcon#enter sib2, iclass 39, count 2 2006.201.15:32:21.58#ibcon#flushed, iclass 39, count 2 2006.201.15:32:21.58#ibcon#about to write, iclass 39, count 2 2006.201.15:32:21.58#ibcon#wrote, iclass 39, count 2 2006.201.15:32:21.58#ibcon#about to read 3, iclass 39, count 2 2006.201.15:32:21.60#ibcon#read 3, iclass 39, count 2 2006.201.15:32:21.60#ibcon#about to read 4, iclass 39, count 2 2006.201.15:32:21.60#ibcon#read 4, iclass 39, count 2 2006.201.15:32:21.60#ibcon#about to read 5, iclass 39, count 2 2006.201.15:32:21.60#ibcon#read 5, iclass 39, count 2 2006.201.15:32:21.60#ibcon#about to read 6, iclass 39, count 2 2006.201.15:32:21.60#ibcon#read 6, iclass 39, count 2 2006.201.15:32:21.60#ibcon#end of sib2, iclass 39, count 2 2006.201.15:32:21.60#ibcon#*mode == 0, iclass 39, count 2 2006.201.15:32:21.60#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.15:32:21.60#ibcon#[27=AT03-04\r\n] 2006.201.15:32:21.60#ibcon#*before write, iclass 39, count 2 2006.201.15:32:21.60#ibcon#enter sib2, iclass 39, count 2 2006.201.15:32:21.60#ibcon#flushed, iclass 39, count 2 2006.201.15:32:21.60#ibcon#about to write, iclass 39, count 2 2006.201.15:32:21.60#ibcon#wrote, iclass 39, count 2 2006.201.15:32:21.60#ibcon#about to read 3, iclass 39, count 2 2006.201.15:32:21.63#ibcon#read 3, iclass 39, count 2 2006.201.15:32:21.63#ibcon#about to read 4, iclass 39, count 2 2006.201.15:32:21.63#ibcon#read 4, iclass 39, count 2 2006.201.15:32:21.63#ibcon#about to read 5, iclass 39, count 2 2006.201.15:32:21.63#ibcon#read 5, iclass 39, count 2 2006.201.15:32:21.63#ibcon#about to read 6, iclass 39, count 2 2006.201.15:32:21.63#ibcon#read 6, iclass 39, count 2 2006.201.15:32:21.63#ibcon#end of sib2, iclass 39, count 2 2006.201.15:32:21.63#ibcon#*after write, iclass 39, count 2 2006.201.15:32:21.63#ibcon#*before return 0, iclass 39, count 2 2006.201.15:32:21.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:21.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:32:21.63#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.15:32:21.63#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:21.63#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:21.75#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:21.75#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:21.75#ibcon#enter wrdev, iclass 39, count 0 2006.201.15:32:21.75#ibcon#first serial, iclass 39, count 0 2006.201.15:32:21.75#ibcon#enter sib2, iclass 39, count 0 2006.201.15:32:21.75#ibcon#flushed, iclass 39, count 0 2006.201.15:32:21.75#ibcon#about to write, iclass 39, count 0 2006.201.15:32:21.75#ibcon#wrote, iclass 39, count 0 2006.201.15:32:21.75#ibcon#about to read 3, iclass 39, count 0 2006.201.15:32:21.77#ibcon#read 3, iclass 39, count 0 2006.201.15:32:21.77#ibcon#about to read 4, iclass 39, count 0 2006.201.15:32:21.77#ibcon#read 4, iclass 39, count 0 2006.201.15:32:21.77#ibcon#about to read 5, iclass 39, count 0 2006.201.15:32:21.77#ibcon#read 5, iclass 39, count 0 2006.201.15:32:21.77#ibcon#about to read 6, iclass 39, count 0 2006.201.15:32:21.77#ibcon#read 6, iclass 39, count 0 2006.201.15:32:21.77#ibcon#end of sib2, iclass 39, count 0 2006.201.15:32:21.77#ibcon#*mode == 0, iclass 39, count 0 2006.201.15:32:21.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.15:32:21.77#ibcon#[27=USB\r\n] 2006.201.15:32:21.77#ibcon#*before write, iclass 39, count 0 2006.201.15:32:21.77#ibcon#enter sib2, iclass 39, count 0 2006.201.15:32:21.77#ibcon#flushed, iclass 39, count 0 2006.201.15:32:21.77#ibcon#about to write, iclass 39, count 0 2006.201.15:32:21.77#ibcon#wrote, iclass 39, count 0 2006.201.15:32:21.77#ibcon#about to read 3, iclass 39, count 0 2006.201.15:32:21.80#ibcon#read 3, iclass 39, count 0 2006.201.15:32:21.80#ibcon#about to read 4, iclass 39, count 0 2006.201.15:32:21.80#ibcon#read 4, iclass 39, count 0 2006.201.15:32:21.80#ibcon#about to read 5, iclass 39, count 0 2006.201.15:32:21.80#ibcon#read 5, iclass 39, count 0 2006.201.15:32:21.80#ibcon#about to read 6, iclass 39, count 0 2006.201.15:32:21.80#ibcon#read 6, iclass 39, count 0 2006.201.15:32:21.80#ibcon#end of sib2, iclass 39, count 0 2006.201.15:32:21.80#ibcon#*after write, iclass 39, count 0 2006.201.15:32:21.80#ibcon#*before return 0, iclass 39, count 0 2006.201.15:32:21.80#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:21.80#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:32:21.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.15:32:21.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.15:32:21.80$vck44/vblo=4,679.99 2006.201.15:32:21.80#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.15:32:21.80#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.15:32:21.80#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:21.80#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:21.80#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:21.80#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:21.80#ibcon#enter wrdev, iclass 2, count 0 2006.201.15:32:21.80#ibcon#first serial, iclass 2, count 0 2006.201.15:32:21.80#ibcon#enter sib2, iclass 2, count 0 2006.201.15:32:21.80#ibcon#flushed, iclass 2, count 0 2006.201.15:32:21.80#ibcon#about to write, iclass 2, count 0 2006.201.15:32:21.80#ibcon#wrote, iclass 2, count 0 2006.201.15:32:21.80#ibcon#about to read 3, iclass 2, count 0 2006.201.15:32:21.82#ibcon#read 3, iclass 2, count 0 2006.201.15:32:21.82#ibcon#about to read 4, iclass 2, count 0 2006.201.15:32:21.82#ibcon#read 4, iclass 2, count 0 2006.201.15:32:21.82#ibcon#about to read 5, iclass 2, count 0 2006.201.15:32:21.82#ibcon#read 5, iclass 2, count 0 2006.201.15:32:21.82#ibcon#about to read 6, iclass 2, count 0 2006.201.15:32:21.82#ibcon#read 6, iclass 2, count 0 2006.201.15:32:21.82#ibcon#end of sib2, iclass 2, count 0 2006.201.15:32:21.82#ibcon#*mode == 0, iclass 2, count 0 2006.201.15:32:21.82#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.15:32:21.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:32:21.82#ibcon#*before write, iclass 2, count 0 2006.201.15:32:21.82#ibcon#enter sib2, iclass 2, count 0 2006.201.15:32:21.82#ibcon#flushed, iclass 2, count 0 2006.201.15:32:21.82#ibcon#about to write, iclass 2, count 0 2006.201.15:32:21.82#ibcon#wrote, iclass 2, count 0 2006.201.15:32:21.82#ibcon#about to read 3, iclass 2, count 0 2006.201.15:32:21.86#ibcon#read 3, iclass 2, count 0 2006.201.15:32:21.86#ibcon#about to read 4, iclass 2, count 0 2006.201.15:32:21.86#ibcon#read 4, iclass 2, count 0 2006.201.15:32:21.86#ibcon#about to read 5, iclass 2, count 0 2006.201.15:32:21.86#ibcon#read 5, iclass 2, count 0 2006.201.15:32:21.86#ibcon#about to read 6, iclass 2, count 0 2006.201.15:32:21.86#ibcon#read 6, iclass 2, count 0 2006.201.15:32:21.86#ibcon#end of sib2, iclass 2, count 0 2006.201.15:32:21.86#ibcon#*after write, iclass 2, count 0 2006.201.15:32:21.86#ibcon#*before return 0, iclass 2, count 0 2006.201.15:32:21.86#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:21.86#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:32:21.86#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.15:32:21.86#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.15:32:21.86$vck44/vb=4,5 2006.201.15:32:21.86#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.15:32:21.86#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.15:32:21.86#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:21.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:21.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:21.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:21.92#ibcon#enter wrdev, iclass 5, count 2 2006.201.15:32:21.92#ibcon#first serial, iclass 5, count 2 2006.201.15:32:21.92#ibcon#enter sib2, iclass 5, count 2 2006.201.15:32:21.92#ibcon#flushed, iclass 5, count 2 2006.201.15:32:21.92#ibcon#about to write, iclass 5, count 2 2006.201.15:32:21.92#ibcon#wrote, iclass 5, count 2 2006.201.15:32:21.92#ibcon#about to read 3, iclass 5, count 2 2006.201.15:32:21.94#ibcon#read 3, iclass 5, count 2 2006.201.15:32:21.94#ibcon#about to read 4, iclass 5, count 2 2006.201.15:32:21.94#ibcon#read 4, iclass 5, count 2 2006.201.15:32:21.94#ibcon#about to read 5, iclass 5, count 2 2006.201.15:32:21.94#ibcon#read 5, iclass 5, count 2 2006.201.15:32:21.94#ibcon#about to read 6, iclass 5, count 2 2006.201.15:32:21.94#ibcon#read 6, iclass 5, count 2 2006.201.15:32:21.94#ibcon#end of sib2, iclass 5, count 2 2006.201.15:32:21.94#ibcon#*mode == 0, iclass 5, count 2 2006.201.15:32:21.94#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.15:32:21.94#ibcon#[27=AT04-05\r\n] 2006.201.15:32:21.94#ibcon#*before write, iclass 5, count 2 2006.201.15:32:21.94#ibcon#enter sib2, iclass 5, count 2 2006.201.15:32:21.94#ibcon#flushed, iclass 5, count 2 2006.201.15:32:21.94#ibcon#about to write, iclass 5, count 2 2006.201.15:32:21.94#ibcon#wrote, iclass 5, count 2 2006.201.15:32:21.94#ibcon#about to read 3, iclass 5, count 2 2006.201.15:32:21.97#ibcon#read 3, iclass 5, count 2 2006.201.15:32:21.97#ibcon#about to read 4, iclass 5, count 2 2006.201.15:32:21.97#ibcon#read 4, iclass 5, count 2 2006.201.15:32:21.97#ibcon#about to read 5, iclass 5, count 2 2006.201.15:32:21.97#ibcon#read 5, iclass 5, count 2 2006.201.15:32:21.97#ibcon#about to read 6, iclass 5, count 2 2006.201.15:32:21.97#ibcon#read 6, iclass 5, count 2 2006.201.15:32:21.97#ibcon#end of sib2, iclass 5, count 2 2006.201.15:32:21.97#ibcon#*after write, iclass 5, count 2 2006.201.15:32:21.97#ibcon#*before return 0, iclass 5, count 2 2006.201.15:32:21.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:21.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:32:21.97#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.15:32:21.97#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:21.97#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:22.09#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:22.09#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:22.09#ibcon#enter wrdev, iclass 5, count 0 2006.201.15:32:22.09#ibcon#first serial, iclass 5, count 0 2006.201.15:32:22.09#ibcon#enter sib2, iclass 5, count 0 2006.201.15:32:22.09#ibcon#flushed, iclass 5, count 0 2006.201.15:32:22.09#ibcon#about to write, iclass 5, count 0 2006.201.15:32:22.09#ibcon#wrote, iclass 5, count 0 2006.201.15:32:22.09#ibcon#about to read 3, iclass 5, count 0 2006.201.15:32:22.11#ibcon#read 3, iclass 5, count 0 2006.201.15:32:22.11#ibcon#about to read 4, iclass 5, count 0 2006.201.15:32:22.11#ibcon#read 4, iclass 5, count 0 2006.201.15:32:22.11#ibcon#about to read 5, iclass 5, count 0 2006.201.15:32:22.11#ibcon#read 5, iclass 5, count 0 2006.201.15:32:22.11#ibcon#about to read 6, iclass 5, count 0 2006.201.15:32:22.11#ibcon#read 6, iclass 5, count 0 2006.201.15:32:22.11#ibcon#end of sib2, iclass 5, count 0 2006.201.15:32:22.11#ibcon#*mode == 0, iclass 5, count 0 2006.201.15:32:22.11#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.15:32:22.11#ibcon#[27=USB\r\n] 2006.201.15:32:22.11#ibcon#*before write, iclass 5, count 0 2006.201.15:32:22.11#ibcon#enter sib2, iclass 5, count 0 2006.201.15:32:22.11#ibcon#flushed, iclass 5, count 0 2006.201.15:32:22.11#ibcon#about to write, iclass 5, count 0 2006.201.15:32:22.11#ibcon#wrote, iclass 5, count 0 2006.201.15:32:22.11#ibcon#about to read 3, iclass 5, count 0 2006.201.15:32:22.14#ibcon#read 3, iclass 5, count 0 2006.201.15:32:22.14#ibcon#about to read 4, iclass 5, count 0 2006.201.15:32:22.14#ibcon#read 4, iclass 5, count 0 2006.201.15:32:22.14#ibcon#about to read 5, iclass 5, count 0 2006.201.15:32:22.14#ibcon#read 5, iclass 5, count 0 2006.201.15:32:22.14#ibcon#about to read 6, iclass 5, count 0 2006.201.15:32:22.14#ibcon#read 6, iclass 5, count 0 2006.201.15:32:22.14#ibcon#end of sib2, iclass 5, count 0 2006.201.15:32:22.14#ibcon#*after write, iclass 5, count 0 2006.201.15:32:22.14#ibcon#*before return 0, iclass 5, count 0 2006.201.15:32:22.14#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:22.14#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:32:22.14#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.15:32:22.14#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.15:32:22.14$vck44/vblo=5,709.99 2006.201.15:32:22.14#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.15:32:22.14#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.15:32:22.14#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:22.14#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:22.14#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:22.14#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:22.14#ibcon#enter wrdev, iclass 7, count 0 2006.201.15:32:22.14#ibcon#first serial, iclass 7, count 0 2006.201.15:32:22.14#ibcon#enter sib2, iclass 7, count 0 2006.201.15:32:22.14#ibcon#flushed, iclass 7, count 0 2006.201.15:32:22.14#ibcon#about to write, iclass 7, count 0 2006.201.15:32:22.14#ibcon#wrote, iclass 7, count 0 2006.201.15:32:22.14#ibcon#about to read 3, iclass 7, count 0 2006.201.15:32:22.16#ibcon#read 3, iclass 7, count 0 2006.201.15:32:22.16#ibcon#about to read 4, iclass 7, count 0 2006.201.15:32:22.16#ibcon#read 4, iclass 7, count 0 2006.201.15:32:22.16#ibcon#about to read 5, iclass 7, count 0 2006.201.15:32:22.16#ibcon#read 5, iclass 7, count 0 2006.201.15:32:22.16#ibcon#about to read 6, iclass 7, count 0 2006.201.15:32:22.16#ibcon#read 6, iclass 7, count 0 2006.201.15:32:22.16#ibcon#end of sib2, iclass 7, count 0 2006.201.15:32:22.16#ibcon#*mode == 0, iclass 7, count 0 2006.201.15:32:22.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.15:32:22.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:32:22.16#ibcon#*before write, iclass 7, count 0 2006.201.15:32:22.16#ibcon#enter sib2, iclass 7, count 0 2006.201.15:32:22.16#ibcon#flushed, iclass 7, count 0 2006.201.15:32:22.16#ibcon#about to write, iclass 7, count 0 2006.201.15:32:22.16#ibcon#wrote, iclass 7, count 0 2006.201.15:32:22.16#ibcon#about to read 3, iclass 7, count 0 2006.201.15:32:22.20#ibcon#read 3, iclass 7, count 0 2006.201.15:32:22.20#ibcon#about to read 4, iclass 7, count 0 2006.201.15:32:22.20#ibcon#read 4, iclass 7, count 0 2006.201.15:32:22.20#ibcon#about to read 5, iclass 7, count 0 2006.201.15:32:22.20#ibcon#read 5, iclass 7, count 0 2006.201.15:32:22.20#ibcon#about to read 6, iclass 7, count 0 2006.201.15:32:22.20#ibcon#read 6, iclass 7, count 0 2006.201.15:32:22.20#ibcon#end of sib2, iclass 7, count 0 2006.201.15:32:22.20#ibcon#*after write, iclass 7, count 0 2006.201.15:32:22.20#ibcon#*before return 0, iclass 7, count 0 2006.201.15:32:22.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:22.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:32:22.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.15:32:22.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.15:32:22.20$vck44/vb=5,4 2006.201.15:32:22.20#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.15:32:22.20#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.15:32:22.20#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:22.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:22.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:22.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:22.26#ibcon#enter wrdev, iclass 11, count 2 2006.201.15:32:22.26#ibcon#first serial, iclass 11, count 2 2006.201.15:32:22.26#ibcon#enter sib2, iclass 11, count 2 2006.201.15:32:22.26#ibcon#flushed, iclass 11, count 2 2006.201.15:32:22.26#ibcon#about to write, iclass 11, count 2 2006.201.15:32:22.26#ibcon#wrote, iclass 11, count 2 2006.201.15:32:22.26#ibcon#about to read 3, iclass 11, count 2 2006.201.15:32:22.28#ibcon#read 3, iclass 11, count 2 2006.201.15:32:22.28#ibcon#about to read 4, iclass 11, count 2 2006.201.15:32:22.28#ibcon#read 4, iclass 11, count 2 2006.201.15:32:22.28#ibcon#about to read 5, iclass 11, count 2 2006.201.15:32:22.28#ibcon#read 5, iclass 11, count 2 2006.201.15:32:22.28#ibcon#about to read 6, iclass 11, count 2 2006.201.15:32:22.28#ibcon#read 6, iclass 11, count 2 2006.201.15:32:22.28#ibcon#end of sib2, iclass 11, count 2 2006.201.15:32:22.28#ibcon#*mode == 0, iclass 11, count 2 2006.201.15:32:22.28#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.15:32:22.28#ibcon#[27=AT05-04\r\n] 2006.201.15:32:22.28#ibcon#*before write, iclass 11, count 2 2006.201.15:32:22.28#ibcon#enter sib2, iclass 11, count 2 2006.201.15:32:22.28#ibcon#flushed, iclass 11, count 2 2006.201.15:32:22.28#ibcon#about to write, iclass 11, count 2 2006.201.15:32:22.28#ibcon#wrote, iclass 11, count 2 2006.201.15:32:22.28#ibcon#about to read 3, iclass 11, count 2 2006.201.15:32:22.31#ibcon#read 3, iclass 11, count 2 2006.201.15:32:22.31#ibcon#about to read 4, iclass 11, count 2 2006.201.15:32:22.31#ibcon#read 4, iclass 11, count 2 2006.201.15:32:22.31#ibcon#about to read 5, iclass 11, count 2 2006.201.15:32:22.31#ibcon#read 5, iclass 11, count 2 2006.201.15:32:22.31#ibcon#about to read 6, iclass 11, count 2 2006.201.15:32:22.31#ibcon#read 6, iclass 11, count 2 2006.201.15:32:22.31#ibcon#end of sib2, iclass 11, count 2 2006.201.15:32:22.31#ibcon#*after write, iclass 11, count 2 2006.201.15:32:22.31#ibcon#*before return 0, iclass 11, count 2 2006.201.15:32:22.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:22.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:32:22.31#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.15:32:22.31#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:22.31#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:22.43#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:22.43#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:22.43#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:32:22.43#ibcon#first serial, iclass 11, count 0 2006.201.15:32:22.43#ibcon#enter sib2, iclass 11, count 0 2006.201.15:32:22.43#ibcon#flushed, iclass 11, count 0 2006.201.15:32:22.43#ibcon#about to write, iclass 11, count 0 2006.201.15:32:22.43#ibcon#wrote, iclass 11, count 0 2006.201.15:32:22.43#ibcon#about to read 3, iclass 11, count 0 2006.201.15:32:22.45#ibcon#read 3, iclass 11, count 0 2006.201.15:32:22.45#ibcon#about to read 4, iclass 11, count 0 2006.201.15:32:22.45#ibcon#read 4, iclass 11, count 0 2006.201.15:32:22.45#ibcon#about to read 5, iclass 11, count 0 2006.201.15:32:22.45#ibcon#read 5, iclass 11, count 0 2006.201.15:32:22.45#ibcon#about to read 6, iclass 11, count 0 2006.201.15:32:22.45#ibcon#read 6, iclass 11, count 0 2006.201.15:32:22.45#ibcon#end of sib2, iclass 11, count 0 2006.201.15:32:22.45#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:32:22.45#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:32:22.45#ibcon#[27=USB\r\n] 2006.201.15:32:22.45#ibcon#*before write, iclass 11, count 0 2006.201.15:32:22.45#ibcon#enter sib2, iclass 11, count 0 2006.201.15:32:22.45#ibcon#flushed, iclass 11, count 0 2006.201.15:32:22.45#ibcon#about to write, iclass 11, count 0 2006.201.15:32:22.45#ibcon#wrote, iclass 11, count 0 2006.201.15:32:22.45#ibcon#about to read 3, iclass 11, count 0 2006.201.15:32:22.48#ibcon#read 3, iclass 11, count 0 2006.201.15:32:22.48#ibcon#about to read 4, iclass 11, count 0 2006.201.15:32:22.48#ibcon#read 4, iclass 11, count 0 2006.201.15:32:22.48#ibcon#about to read 5, iclass 11, count 0 2006.201.15:32:22.48#ibcon#read 5, iclass 11, count 0 2006.201.15:32:22.48#ibcon#about to read 6, iclass 11, count 0 2006.201.15:32:22.48#ibcon#read 6, iclass 11, count 0 2006.201.15:32:22.48#ibcon#end of sib2, iclass 11, count 0 2006.201.15:32:22.48#ibcon#*after write, iclass 11, count 0 2006.201.15:32:22.48#ibcon#*before return 0, iclass 11, count 0 2006.201.15:32:22.48#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:22.48#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:32:22.48#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:32:22.48#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:32:22.48$vck44/vblo=6,719.99 2006.201.15:32:22.48#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.15:32:22.48#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.15:32:22.48#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:22.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:22.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:22.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:22.48#ibcon#enter wrdev, iclass 13, count 0 2006.201.15:32:22.48#ibcon#first serial, iclass 13, count 0 2006.201.15:32:22.48#ibcon#enter sib2, iclass 13, count 0 2006.201.15:32:22.48#ibcon#flushed, iclass 13, count 0 2006.201.15:32:22.48#ibcon#about to write, iclass 13, count 0 2006.201.15:32:22.48#ibcon#wrote, iclass 13, count 0 2006.201.15:32:22.48#ibcon#about to read 3, iclass 13, count 0 2006.201.15:32:22.50#ibcon#read 3, iclass 13, count 0 2006.201.15:32:22.50#ibcon#about to read 4, iclass 13, count 0 2006.201.15:32:22.50#ibcon#read 4, iclass 13, count 0 2006.201.15:32:22.50#ibcon#about to read 5, iclass 13, count 0 2006.201.15:32:22.50#ibcon#read 5, iclass 13, count 0 2006.201.15:32:22.50#ibcon#about to read 6, iclass 13, count 0 2006.201.15:32:22.50#ibcon#read 6, iclass 13, count 0 2006.201.15:32:22.50#ibcon#end of sib2, iclass 13, count 0 2006.201.15:32:22.50#ibcon#*mode == 0, iclass 13, count 0 2006.201.15:32:22.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.15:32:22.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:32:22.50#ibcon#*before write, iclass 13, count 0 2006.201.15:32:22.50#ibcon#enter sib2, iclass 13, count 0 2006.201.15:32:22.50#ibcon#flushed, iclass 13, count 0 2006.201.15:32:22.50#ibcon#about to write, iclass 13, count 0 2006.201.15:32:22.50#ibcon#wrote, iclass 13, count 0 2006.201.15:32:22.50#ibcon#about to read 3, iclass 13, count 0 2006.201.15:32:22.54#ibcon#read 3, iclass 13, count 0 2006.201.15:32:22.54#ibcon#about to read 4, iclass 13, count 0 2006.201.15:32:22.54#ibcon#read 4, iclass 13, count 0 2006.201.15:32:22.54#ibcon#about to read 5, iclass 13, count 0 2006.201.15:32:22.54#ibcon#read 5, iclass 13, count 0 2006.201.15:32:22.54#ibcon#about to read 6, iclass 13, count 0 2006.201.15:32:22.54#ibcon#read 6, iclass 13, count 0 2006.201.15:32:22.54#ibcon#end of sib2, iclass 13, count 0 2006.201.15:32:22.54#ibcon#*after write, iclass 13, count 0 2006.201.15:32:22.54#ibcon#*before return 0, iclass 13, count 0 2006.201.15:32:22.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:22.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:32:22.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.15:32:22.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.15:32:22.54$vck44/vb=6,4 2006.201.15:32:22.54#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.15:32:22.54#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.15:32:22.54#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:22.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:22.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:22.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:22.60#ibcon#enter wrdev, iclass 15, count 2 2006.201.15:32:22.60#ibcon#first serial, iclass 15, count 2 2006.201.15:32:22.60#ibcon#enter sib2, iclass 15, count 2 2006.201.15:32:22.60#ibcon#flushed, iclass 15, count 2 2006.201.15:32:22.60#ibcon#about to write, iclass 15, count 2 2006.201.15:32:22.60#ibcon#wrote, iclass 15, count 2 2006.201.15:32:22.60#ibcon#about to read 3, iclass 15, count 2 2006.201.15:32:22.62#ibcon#read 3, iclass 15, count 2 2006.201.15:32:22.62#ibcon#about to read 4, iclass 15, count 2 2006.201.15:32:22.62#ibcon#read 4, iclass 15, count 2 2006.201.15:32:22.62#ibcon#about to read 5, iclass 15, count 2 2006.201.15:32:22.62#ibcon#read 5, iclass 15, count 2 2006.201.15:32:22.62#ibcon#about to read 6, iclass 15, count 2 2006.201.15:32:22.62#ibcon#read 6, iclass 15, count 2 2006.201.15:32:22.62#ibcon#end of sib2, iclass 15, count 2 2006.201.15:32:22.62#ibcon#*mode == 0, iclass 15, count 2 2006.201.15:32:22.62#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.15:32:22.62#ibcon#[27=AT06-04\r\n] 2006.201.15:32:22.62#ibcon#*before write, iclass 15, count 2 2006.201.15:32:22.62#ibcon#enter sib2, iclass 15, count 2 2006.201.15:32:22.62#ibcon#flushed, iclass 15, count 2 2006.201.15:32:22.62#ibcon#about to write, iclass 15, count 2 2006.201.15:32:22.62#ibcon#wrote, iclass 15, count 2 2006.201.15:32:22.62#ibcon#about to read 3, iclass 15, count 2 2006.201.15:32:22.65#ibcon#read 3, iclass 15, count 2 2006.201.15:32:22.65#ibcon#about to read 4, iclass 15, count 2 2006.201.15:32:22.65#ibcon#read 4, iclass 15, count 2 2006.201.15:32:22.65#ibcon#about to read 5, iclass 15, count 2 2006.201.15:32:22.65#ibcon#read 5, iclass 15, count 2 2006.201.15:32:22.65#ibcon#about to read 6, iclass 15, count 2 2006.201.15:32:22.65#ibcon#read 6, iclass 15, count 2 2006.201.15:32:22.65#ibcon#end of sib2, iclass 15, count 2 2006.201.15:32:22.65#ibcon#*after write, iclass 15, count 2 2006.201.15:32:22.65#ibcon#*before return 0, iclass 15, count 2 2006.201.15:32:22.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:22.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:32:22.65#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.15:32:22.65#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:22.65#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:22.77#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:22.77#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:22.77#ibcon#enter wrdev, iclass 15, count 0 2006.201.15:32:22.77#ibcon#first serial, iclass 15, count 0 2006.201.15:32:22.77#ibcon#enter sib2, iclass 15, count 0 2006.201.15:32:22.77#ibcon#flushed, iclass 15, count 0 2006.201.15:32:22.77#ibcon#about to write, iclass 15, count 0 2006.201.15:32:22.77#ibcon#wrote, iclass 15, count 0 2006.201.15:32:22.77#ibcon#about to read 3, iclass 15, count 0 2006.201.15:32:22.79#ibcon#read 3, iclass 15, count 0 2006.201.15:32:22.79#ibcon#about to read 4, iclass 15, count 0 2006.201.15:32:22.79#ibcon#read 4, iclass 15, count 0 2006.201.15:32:22.79#ibcon#about to read 5, iclass 15, count 0 2006.201.15:32:22.79#ibcon#read 5, iclass 15, count 0 2006.201.15:32:22.79#ibcon#about to read 6, iclass 15, count 0 2006.201.15:32:22.79#ibcon#read 6, iclass 15, count 0 2006.201.15:32:22.79#ibcon#end of sib2, iclass 15, count 0 2006.201.15:32:22.79#ibcon#*mode == 0, iclass 15, count 0 2006.201.15:32:22.79#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.15:32:22.79#ibcon#[27=USB\r\n] 2006.201.15:32:22.79#ibcon#*before write, iclass 15, count 0 2006.201.15:32:22.79#ibcon#enter sib2, iclass 15, count 0 2006.201.15:32:22.79#ibcon#flushed, iclass 15, count 0 2006.201.15:32:22.79#ibcon#about to write, iclass 15, count 0 2006.201.15:32:22.79#ibcon#wrote, iclass 15, count 0 2006.201.15:32:22.79#ibcon#about to read 3, iclass 15, count 0 2006.201.15:32:22.82#ibcon#read 3, iclass 15, count 0 2006.201.15:32:22.82#ibcon#about to read 4, iclass 15, count 0 2006.201.15:32:22.82#ibcon#read 4, iclass 15, count 0 2006.201.15:32:22.82#ibcon#about to read 5, iclass 15, count 0 2006.201.15:32:22.82#ibcon#read 5, iclass 15, count 0 2006.201.15:32:22.82#ibcon#about to read 6, iclass 15, count 0 2006.201.15:32:22.82#ibcon#read 6, iclass 15, count 0 2006.201.15:32:22.82#ibcon#end of sib2, iclass 15, count 0 2006.201.15:32:22.82#ibcon#*after write, iclass 15, count 0 2006.201.15:32:22.82#ibcon#*before return 0, iclass 15, count 0 2006.201.15:32:22.82#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:22.82#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:32:22.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.15:32:22.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.15:32:22.82$vck44/vblo=7,734.99 2006.201.15:32:22.82#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.15:32:22.82#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.15:32:22.82#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:22.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:22.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:22.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:22.82#ibcon#enter wrdev, iclass 17, count 0 2006.201.15:32:22.82#ibcon#first serial, iclass 17, count 0 2006.201.15:32:22.82#ibcon#enter sib2, iclass 17, count 0 2006.201.15:32:22.82#ibcon#flushed, iclass 17, count 0 2006.201.15:32:22.82#ibcon#about to write, iclass 17, count 0 2006.201.15:32:22.82#ibcon#wrote, iclass 17, count 0 2006.201.15:32:22.82#ibcon#about to read 3, iclass 17, count 0 2006.201.15:32:22.84#ibcon#read 3, iclass 17, count 0 2006.201.15:32:22.84#ibcon#about to read 4, iclass 17, count 0 2006.201.15:32:22.84#ibcon#read 4, iclass 17, count 0 2006.201.15:32:22.84#ibcon#about to read 5, iclass 17, count 0 2006.201.15:32:22.84#ibcon#read 5, iclass 17, count 0 2006.201.15:32:22.84#ibcon#about to read 6, iclass 17, count 0 2006.201.15:32:22.84#ibcon#read 6, iclass 17, count 0 2006.201.15:32:22.84#ibcon#end of sib2, iclass 17, count 0 2006.201.15:32:22.84#ibcon#*mode == 0, iclass 17, count 0 2006.201.15:32:22.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.15:32:22.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:32:22.84#ibcon#*before write, iclass 17, count 0 2006.201.15:32:22.84#ibcon#enter sib2, iclass 17, count 0 2006.201.15:32:22.84#ibcon#flushed, iclass 17, count 0 2006.201.15:32:22.84#ibcon#about to write, iclass 17, count 0 2006.201.15:32:22.84#ibcon#wrote, iclass 17, count 0 2006.201.15:32:22.84#ibcon#about to read 3, iclass 17, count 0 2006.201.15:32:22.88#ibcon#read 3, iclass 17, count 0 2006.201.15:32:22.88#ibcon#about to read 4, iclass 17, count 0 2006.201.15:32:22.88#ibcon#read 4, iclass 17, count 0 2006.201.15:32:22.88#ibcon#about to read 5, iclass 17, count 0 2006.201.15:32:22.88#ibcon#read 5, iclass 17, count 0 2006.201.15:32:22.88#ibcon#about to read 6, iclass 17, count 0 2006.201.15:32:22.88#ibcon#read 6, iclass 17, count 0 2006.201.15:32:22.88#ibcon#end of sib2, iclass 17, count 0 2006.201.15:32:22.88#ibcon#*after write, iclass 17, count 0 2006.201.15:32:22.88#ibcon#*before return 0, iclass 17, count 0 2006.201.15:32:22.88#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:22.88#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:32:22.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.15:32:22.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.15:32:22.88$vck44/vb=7,4 2006.201.15:32:22.88#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.15:32:22.88#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.15:32:22.88#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:22.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:22.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:22.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:22.94#ibcon#enter wrdev, iclass 19, count 2 2006.201.15:32:22.94#ibcon#first serial, iclass 19, count 2 2006.201.15:32:22.94#ibcon#enter sib2, iclass 19, count 2 2006.201.15:32:22.94#ibcon#flushed, iclass 19, count 2 2006.201.15:32:22.94#ibcon#about to write, iclass 19, count 2 2006.201.15:32:22.94#ibcon#wrote, iclass 19, count 2 2006.201.15:32:22.94#ibcon#about to read 3, iclass 19, count 2 2006.201.15:32:22.96#ibcon#read 3, iclass 19, count 2 2006.201.15:32:22.96#ibcon#about to read 4, iclass 19, count 2 2006.201.15:32:22.96#ibcon#read 4, iclass 19, count 2 2006.201.15:32:22.96#ibcon#about to read 5, iclass 19, count 2 2006.201.15:32:22.96#ibcon#read 5, iclass 19, count 2 2006.201.15:32:22.96#ibcon#about to read 6, iclass 19, count 2 2006.201.15:32:22.96#ibcon#read 6, iclass 19, count 2 2006.201.15:32:22.96#ibcon#end of sib2, iclass 19, count 2 2006.201.15:32:22.96#ibcon#*mode == 0, iclass 19, count 2 2006.201.15:32:22.96#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.15:32:22.96#ibcon#[27=AT07-04\r\n] 2006.201.15:32:22.96#ibcon#*before write, iclass 19, count 2 2006.201.15:32:22.96#ibcon#enter sib2, iclass 19, count 2 2006.201.15:32:22.96#ibcon#flushed, iclass 19, count 2 2006.201.15:32:22.96#ibcon#about to write, iclass 19, count 2 2006.201.15:32:22.96#ibcon#wrote, iclass 19, count 2 2006.201.15:32:22.96#ibcon#about to read 3, iclass 19, count 2 2006.201.15:32:22.99#ibcon#read 3, iclass 19, count 2 2006.201.15:32:22.99#ibcon#about to read 4, iclass 19, count 2 2006.201.15:32:22.99#ibcon#read 4, iclass 19, count 2 2006.201.15:32:22.99#ibcon#about to read 5, iclass 19, count 2 2006.201.15:32:22.99#ibcon#read 5, iclass 19, count 2 2006.201.15:32:22.99#ibcon#about to read 6, iclass 19, count 2 2006.201.15:32:22.99#ibcon#read 6, iclass 19, count 2 2006.201.15:32:22.99#ibcon#end of sib2, iclass 19, count 2 2006.201.15:32:22.99#ibcon#*after write, iclass 19, count 2 2006.201.15:32:22.99#ibcon#*before return 0, iclass 19, count 2 2006.201.15:32:22.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:22.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:32:22.99#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.15:32:22.99#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:22.99#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:23.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:23.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:23.11#ibcon#enter wrdev, iclass 19, count 0 2006.201.15:32:23.11#ibcon#first serial, iclass 19, count 0 2006.201.15:32:23.11#ibcon#enter sib2, iclass 19, count 0 2006.201.15:32:23.11#ibcon#flushed, iclass 19, count 0 2006.201.15:32:23.11#ibcon#about to write, iclass 19, count 0 2006.201.15:32:23.11#ibcon#wrote, iclass 19, count 0 2006.201.15:32:23.11#ibcon#about to read 3, iclass 19, count 0 2006.201.15:32:23.13#ibcon#read 3, iclass 19, count 0 2006.201.15:32:23.13#ibcon#about to read 4, iclass 19, count 0 2006.201.15:32:23.13#ibcon#read 4, iclass 19, count 0 2006.201.15:32:23.13#ibcon#about to read 5, iclass 19, count 0 2006.201.15:32:23.13#ibcon#read 5, iclass 19, count 0 2006.201.15:32:23.13#ibcon#about to read 6, iclass 19, count 0 2006.201.15:32:23.13#ibcon#read 6, iclass 19, count 0 2006.201.15:32:23.13#ibcon#end of sib2, iclass 19, count 0 2006.201.15:32:23.13#ibcon#*mode == 0, iclass 19, count 0 2006.201.15:32:23.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.15:32:23.13#ibcon#[27=USB\r\n] 2006.201.15:32:23.13#ibcon#*before write, iclass 19, count 0 2006.201.15:32:23.13#ibcon#enter sib2, iclass 19, count 0 2006.201.15:32:23.13#ibcon#flushed, iclass 19, count 0 2006.201.15:32:23.13#ibcon#about to write, iclass 19, count 0 2006.201.15:32:23.13#ibcon#wrote, iclass 19, count 0 2006.201.15:32:23.13#ibcon#about to read 3, iclass 19, count 0 2006.201.15:32:23.16#ibcon#read 3, iclass 19, count 0 2006.201.15:32:23.16#ibcon#about to read 4, iclass 19, count 0 2006.201.15:32:23.16#ibcon#read 4, iclass 19, count 0 2006.201.15:32:23.16#ibcon#about to read 5, iclass 19, count 0 2006.201.15:32:23.16#ibcon#read 5, iclass 19, count 0 2006.201.15:32:23.16#ibcon#about to read 6, iclass 19, count 0 2006.201.15:32:23.16#ibcon#read 6, iclass 19, count 0 2006.201.15:32:23.16#ibcon#end of sib2, iclass 19, count 0 2006.201.15:32:23.16#ibcon#*after write, iclass 19, count 0 2006.201.15:32:23.16#ibcon#*before return 0, iclass 19, count 0 2006.201.15:32:23.16#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:23.16#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:32:23.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.15:32:23.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.15:32:23.16$vck44/vblo=8,744.99 2006.201.15:32:23.16#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.15:32:23.16#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.15:32:23.16#ibcon#ireg 17 cls_cnt 0 2006.201.15:32:23.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:23.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:23.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:23.16#ibcon#enter wrdev, iclass 21, count 0 2006.201.15:32:23.16#ibcon#first serial, iclass 21, count 0 2006.201.15:32:23.16#ibcon#enter sib2, iclass 21, count 0 2006.201.15:32:23.16#ibcon#flushed, iclass 21, count 0 2006.201.15:32:23.16#ibcon#about to write, iclass 21, count 0 2006.201.15:32:23.16#ibcon#wrote, iclass 21, count 0 2006.201.15:32:23.16#ibcon#about to read 3, iclass 21, count 0 2006.201.15:32:23.18#ibcon#read 3, iclass 21, count 0 2006.201.15:32:23.18#ibcon#about to read 4, iclass 21, count 0 2006.201.15:32:23.18#ibcon#read 4, iclass 21, count 0 2006.201.15:32:23.18#ibcon#about to read 5, iclass 21, count 0 2006.201.15:32:23.18#ibcon#read 5, iclass 21, count 0 2006.201.15:32:23.18#ibcon#about to read 6, iclass 21, count 0 2006.201.15:32:23.18#ibcon#read 6, iclass 21, count 0 2006.201.15:32:23.18#ibcon#end of sib2, iclass 21, count 0 2006.201.15:32:23.18#ibcon#*mode == 0, iclass 21, count 0 2006.201.15:32:23.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.15:32:23.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:32:23.18#ibcon#*before write, iclass 21, count 0 2006.201.15:32:23.18#ibcon#enter sib2, iclass 21, count 0 2006.201.15:32:23.18#ibcon#flushed, iclass 21, count 0 2006.201.15:32:23.18#ibcon#about to write, iclass 21, count 0 2006.201.15:32:23.18#ibcon#wrote, iclass 21, count 0 2006.201.15:32:23.18#ibcon#about to read 3, iclass 21, count 0 2006.201.15:32:23.22#ibcon#read 3, iclass 21, count 0 2006.201.15:32:23.22#ibcon#about to read 4, iclass 21, count 0 2006.201.15:32:23.22#ibcon#read 4, iclass 21, count 0 2006.201.15:32:23.22#ibcon#about to read 5, iclass 21, count 0 2006.201.15:32:23.22#ibcon#read 5, iclass 21, count 0 2006.201.15:32:23.22#ibcon#about to read 6, iclass 21, count 0 2006.201.15:32:23.22#ibcon#read 6, iclass 21, count 0 2006.201.15:32:23.22#ibcon#end of sib2, iclass 21, count 0 2006.201.15:32:23.22#ibcon#*after write, iclass 21, count 0 2006.201.15:32:23.22#ibcon#*before return 0, iclass 21, count 0 2006.201.15:32:23.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:23.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:32:23.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.15:32:23.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.15:32:23.22$vck44/vb=8,4 2006.201.15:32:23.22#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.15:32:23.22#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.15:32:23.22#ibcon#ireg 11 cls_cnt 2 2006.201.15:32:23.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:23.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:23.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:23.28#ibcon#enter wrdev, iclass 23, count 2 2006.201.15:32:23.28#ibcon#first serial, iclass 23, count 2 2006.201.15:32:23.28#ibcon#enter sib2, iclass 23, count 2 2006.201.15:32:23.28#ibcon#flushed, iclass 23, count 2 2006.201.15:32:23.28#ibcon#about to write, iclass 23, count 2 2006.201.15:32:23.28#ibcon#wrote, iclass 23, count 2 2006.201.15:32:23.28#ibcon#about to read 3, iclass 23, count 2 2006.201.15:32:23.30#ibcon#read 3, iclass 23, count 2 2006.201.15:32:23.30#ibcon#about to read 4, iclass 23, count 2 2006.201.15:32:23.30#ibcon#read 4, iclass 23, count 2 2006.201.15:32:23.30#ibcon#about to read 5, iclass 23, count 2 2006.201.15:32:23.30#ibcon#read 5, iclass 23, count 2 2006.201.15:32:23.30#ibcon#about to read 6, iclass 23, count 2 2006.201.15:32:23.30#ibcon#read 6, iclass 23, count 2 2006.201.15:32:23.30#ibcon#end of sib2, iclass 23, count 2 2006.201.15:32:23.30#ibcon#*mode == 0, iclass 23, count 2 2006.201.15:32:23.30#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.15:32:23.30#ibcon#[27=AT08-04\r\n] 2006.201.15:32:23.30#ibcon#*before write, iclass 23, count 2 2006.201.15:32:23.30#ibcon#enter sib2, iclass 23, count 2 2006.201.15:32:23.30#ibcon#flushed, iclass 23, count 2 2006.201.15:32:23.30#ibcon#about to write, iclass 23, count 2 2006.201.15:32:23.30#ibcon#wrote, iclass 23, count 2 2006.201.15:32:23.30#ibcon#about to read 3, iclass 23, count 2 2006.201.15:32:23.33#ibcon#read 3, iclass 23, count 2 2006.201.15:32:23.33#ibcon#about to read 4, iclass 23, count 2 2006.201.15:32:23.33#ibcon#read 4, iclass 23, count 2 2006.201.15:32:23.33#ibcon#about to read 5, iclass 23, count 2 2006.201.15:32:23.33#ibcon#read 5, iclass 23, count 2 2006.201.15:32:23.33#ibcon#about to read 6, iclass 23, count 2 2006.201.15:32:23.33#ibcon#read 6, iclass 23, count 2 2006.201.15:32:23.33#ibcon#end of sib2, iclass 23, count 2 2006.201.15:32:23.33#ibcon#*after write, iclass 23, count 2 2006.201.15:32:23.33#ibcon#*before return 0, iclass 23, count 2 2006.201.15:32:23.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:23.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:32:23.33#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.15:32:23.33#ibcon#ireg 7 cls_cnt 0 2006.201.15:32:23.33#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:23.45#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:23.45#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:23.45#ibcon#enter wrdev, iclass 23, count 0 2006.201.15:32:23.45#ibcon#first serial, iclass 23, count 0 2006.201.15:32:23.45#ibcon#enter sib2, iclass 23, count 0 2006.201.15:32:23.45#ibcon#flushed, iclass 23, count 0 2006.201.15:32:23.45#ibcon#about to write, iclass 23, count 0 2006.201.15:32:23.45#ibcon#wrote, iclass 23, count 0 2006.201.15:32:23.45#ibcon#about to read 3, iclass 23, count 0 2006.201.15:32:23.47#ibcon#read 3, iclass 23, count 0 2006.201.15:32:23.47#ibcon#about to read 4, iclass 23, count 0 2006.201.15:32:23.47#ibcon#read 4, iclass 23, count 0 2006.201.15:32:23.47#ibcon#about to read 5, iclass 23, count 0 2006.201.15:32:23.47#ibcon#read 5, iclass 23, count 0 2006.201.15:32:23.47#ibcon#about to read 6, iclass 23, count 0 2006.201.15:32:23.47#ibcon#read 6, iclass 23, count 0 2006.201.15:32:23.47#ibcon#end of sib2, iclass 23, count 0 2006.201.15:32:23.47#ibcon#*mode == 0, iclass 23, count 0 2006.201.15:32:23.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.15:32:23.47#ibcon#[27=USB\r\n] 2006.201.15:32:23.47#ibcon#*before write, iclass 23, count 0 2006.201.15:32:23.47#ibcon#enter sib2, iclass 23, count 0 2006.201.15:32:23.47#ibcon#flushed, iclass 23, count 0 2006.201.15:32:23.47#ibcon#about to write, iclass 23, count 0 2006.201.15:32:23.47#ibcon#wrote, iclass 23, count 0 2006.201.15:32:23.47#ibcon#about to read 3, iclass 23, count 0 2006.201.15:32:23.50#ibcon#read 3, iclass 23, count 0 2006.201.15:32:23.50#ibcon#about to read 4, iclass 23, count 0 2006.201.15:32:23.50#ibcon#read 4, iclass 23, count 0 2006.201.15:32:23.50#ibcon#about to read 5, iclass 23, count 0 2006.201.15:32:23.50#ibcon#read 5, iclass 23, count 0 2006.201.15:32:23.50#ibcon#about to read 6, iclass 23, count 0 2006.201.15:32:23.50#ibcon#read 6, iclass 23, count 0 2006.201.15:32:23.50#ibcon#end of sib2, iclass 23, count 0 2006.201.15:32:23.50#ibcon#*after write, iclass 23, count 0 2006.201.15:32:23.50#ibcon#*before return 0, iclass 23, count 0 2006.201.15:32:23.50#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:23.50#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:32:23.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.15:32:23.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.15:32:23.50$vck44/vabw=wide 2006.201.15:32:23.50#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.15:32:23.50#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.15:32:23.50#ibcon#ireg 8 cls_cnt 0 2006.201.15:32:23.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:23.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:23.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:23.50#ibcon#enter wrdev, iclass 25, count 0 2006.201.15:32:23.50#ibcon#first serial, iclass 25, count 0 2006.201.15:32:23.50#ibcon#enter sib2, iclass 25, count 0 2006.201.15:32:23.50#ibcon#flushed, iclass 25, count 0 2006.201.15:32:23.50#ibcon#about to write, iclass 25, count 0 2006.201.15:32:23.50#ibcon#wrote, iclass 25, count 0 2006.201.15:32:23.50#ibcon#about to read 3, iclass 25, count 0 2006.201.15:32:23.52#ibcon#read 3, iclass 25, count 0 2006.201.15:32:23.52#ibcon#about to read 4, iclass 25, count 0 2006.201.15:32:23.52#ibcon#read 4, iclass 25, count 0 2006.201.15:32:23.52#ibcon#about to read 5, iclass 25, count 0 2006.201.15:32:23.52#ibcon#read 5, iclass 25, count 0 2006.201.15:32:23.52#ibcon#about to read 6, iclass 25, count 0 2006.201.15:32:23.52#ibcon#read 6, iclass 25, count 0 2006.201.15:32:23.52#ibcon#end of sib2, iclass 25, count 0 2006.201.15:32:23.52#ibcon#*mode == 0, iclass 25, count 0 2006.201.15:32:23.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.15:32:23.52#ibcon#[25=BW32\r\n] 2006.201.15:32:23.52#ibcon#*before write, iclass 25, count 0 2006.201.15:32:23.52#ibcon#enter sib2, iclass 25, count 0 2006.201.15:32:23.52#ibcon#flushed, iclass 25, count 0 2006.201.15:32:23.52#ibcon#about to write, iclass 25, count 0 2006.201.15:32:23.52#ibcon#wrote, iclass 25, count 0 2006.201.15:32:23.52#ibcon#about to read 3, iclass 25, count 0 2006.201.15:32:23.55#ibcon#read 3, iclass 25, count 0 2006.201.15:32:23.55#ibcon#about to read 4, iclass 25, count 0 2006.201.15:32:23.55#ibcon#read 4, iclass 25, count 0 2006.201.15:32:23.55#ibcon#about to read 5, iclass 25, count 0 2006.201.15:32:23.55#ibcon#read 5, iclass 25, count 0 2006.201.15:32:23.55#ibcon#about to read 6, iclass 25, count 0 2006.201.15:32:23.55#ibcon#read 6, iclass 25, count 0 2006.201.15:32:23.55#ibcon#end of sib2, iclass 25, count 0 2006.201.15:32:23.55#ibcon#*after write, iclass 25, count 0 2006.201.15:32:23.55#ibcon#*before return 0, iclass 25, count 0 2006.201.15:32:23.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:23.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:32:23.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.15:32:23.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.15:32:23.55$vck44/vbbw=wide 2006.201.15:32:23.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.15:32:23.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.15:32:23.55#ibcon#ireg 8 cls_cnt 0 2006.201.15:32:23.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:32:23.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:32:23.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:32:23.62#ibcon#enter wrdev, iclass 27, count 0 2006.201.15:32:23.62#ibcon#first serial, iclass 27, count 0 2006.201.15:32:23.62#ibcon#enter sib2, iclass 27, count 0 2006.201.15:32:23.62#ibcon#flushed, iclass 27, count 0 2006.201.15:32:23.62#ibcon#about to write, iclass 27, count 0 2006.201.15:32:23.62#ibcon#wrote, iclass 27, count 0 2006.201.15:32:23.62#ibcon#about to read 3, iclass 27, count 0 2006.201.15:32:23.64#ibcon#read 3, iclass 27, count 0 2006.201.15:32:23.64#ibcon#about to read 4, iclass 27, count 0 2006.201.15:32:23.64#ibcon#read 4, iclass 27, count 0 2006.201.15:32:23.64#ibcon#about to read 5, iclass 27, count 0 2006.201.15:32:23.64#ibcon#read 5, iclass 27, count 0 2006.201.15:32:23.64#ibcon#about to read 6, iclass 27, count 0 2006.201.15:32:23.64#ibcon#read 6, iclass 27, count 0 2006.201.15:32:23.64#ibcon#end of sib2, iclass 27, count 0 2006.201.15:32:23.64#ibcon#*mode == 0, iclass 27, count 0 2006.201.15:32:23.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.15:32:23.64#ibcon#[27=BW32\r\n] 2006.201.15:32:23.64#ibcon#*before write, iclass 27, count 0 2006.201.15:32:23.64#ibcon#enter sib2, iclass 27, count 0 2006.201.15:32:23.64#ibcon#flushed, iclass 27, count 0 2006.201.15:32:23.64#ibcon#about to write, iclass 27, count 0 2006.201.15:32:23.64#ibcon#wrote, iclass 27, count 0 2006.201.15:32:23.64#ibcon#about to read 3, iclass 27, count 0 2006.201.15:32:23.67#ibcon#read 3, iclass 27, count 0 2006.201.15:32:23.67#ibcon#about to read 4, iclass 27, count 0 2006.201.15:32:23.67#ibcon#read 4, iclass 27, count 0 2006.201.15:32:23.67#ibcon#about to read 5, iclass 27, count 0 2006.201.15:32:23.67#ibcon#read 5, iclass 27, count 0 2006.201.15:32:23.67#ibcon#about to read 6, iclass 27, count 0 2006.201.15:32:23.67#ibcon#read 6, iclass 27, count 0 2006.201.15:32:23.67#ibcon#end of sib2, iclass 27, count 0 2006.201.15:32:23.67#ibcon#*after write, iclass 27, count 0 2006.201.15:32:23.67#ibcon#*before return 0, iclass 27, count 0 2006.201.15:32:23.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:32:23.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.15:32:23.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.15:32:23.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.15:32:23.67$setupk4/ifdk4 2006.201.15:32:23.67$ifdk4/lo= 2006.201.15:32:23.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:32:23.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:32:23.67$ifdk4/patch= 2006.201.15:32:23.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:32:23.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:32:23.67$setupk4/!*+20s 2006.201.15:32:25.34#abcon#<5=/04 0.8 1.5 20.841001003.0\r\n> 2006.201.15:32:25.36#abcon#{5=INTERFACE CLEAR} 2006.201.15:32:25.42#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:32:35.51#abcon#<5=/04 0.8 1.5 20.841001003.0\r\n> 2006.201.15:32:35.53#abcon#{5=INTERFACE CLEAR} 2006.201.15:32:35.59#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:32:38.15$setupk4/"tpicd 2006.201.15:32:38.15$setupk4/echo=off 2006.201.15:32:38.15$setupk4/xlog=off 2006.201.15:32:38.15:!2006.201.15:37:49 2006.201.15:33:14.14#trakl#Source acquired 2006.201.15:33:15.14#flagr#flagr/antenna,acquired 2006.201.15:37:49.00:preob 2006.201.15:37:49.13/onsource/TRACKING 2006.201.15:37:49.13:!2006.201.15:37:59 2006.201.15:37:59.00:"tape 2006.201.15:37:59.00:"st=record 2006.201.15:37:59.00:data_valid=on 2006.201.15:37:59.00:midob 2006.201.15:38:00.13/onsource/TRACKING 2006.201.15:38:00.13/wx/20.84,1002.9,100 2006.201.15:38:00.22/cable/+6.4776E-03 2006.201.15:38:01.31/va/01,08,usb,yes,29,31 2006.201.15:38:01.31/va/02,07,usb,yes,31,32 2006.201.15:38:01.31/va/03,08,usb,yes,28,29 2006.201.15:38:01.31/va/04,07,usb,yes,32,33 2006.201.15:38:01.31/va/05,04,usb,yes,28,28 2006.201.15:38:01.31/va/06,05,usb,yes,28,28 2006.201.15:38:01.31/va/07,05,usb,yes,27,28 2006.201.15:38:01.31/va/08,04,usb,yes,27,33 2006.201.15:38:01.54/valo/01,524.99,yes,locked 2006.201.15:38:01.54/valo/02,534.99,yes,locked 2006.201.15:38:01.54/valo/03,564.99,yes,locked 2006.201.15:38:01.54/valo/04,624.99,yes,locked 2006.201.15:38:01.54/valo/05,734.99,yes,locked 2006.201.15:38:01.54/valo/06,814.99,yes,locked 2006.201.15:38:01.54/valo/07,864.99,yes,locked 2006.201.15:38:01.54/valo/08,884.99,yes,locked 2006.201.15:38:02.63/vb/01,04,usb,yes,28,27 2006.201.15:38:02.63/vb/02,05,usb,yes,27,27 2006.201.15:38:02.63/vb/03,04,usb,yes,28,31 2006.201.15:38:02.63/vb/04,05,usb,yes,28,27 2006.201.15:38:02.63/vb/05,04,usb,yes,25,27 2006.201.15:38:02.63/vb/06,04,usb,yes,29,25 2006.201.15:38:02.63/vb/07,04,usb,yes,29,29 2006.201.15:38:02.63/vb/08,04,usb,yes,27,30 2006.201.15:38:02.86/vblo/01,629.99,yes,locked 2006.201.15:38:02.86/vblo/02,634.99,yes,locked 2006.201.15:38:02.86/vblo/03,649.99,yes,locked 2006.201.15:38:02.86/vblo/04,679.99,yes,locked 2006.201.15:38:02.86/vblo/05,709.99,yes,locked 2006.201.15:38:02.86/vblo/06,719.99,yes,locked 2006.201.15:38:02.86/vblo/07,734.99,yes,locked 2006.201.15:38:02.86/vblo/08,744.99,yes,locked 2006.201.15:38:03.01/vabw/8 2006.201.15:38:03.16/vbbw/8 2006.201.15:38:03.25/xfe/off,on,15.2 2006.201.15:38:03.62/ifatt/23,28,28,28 2006.201.15:38:04.06/fmout-gps/S +4.50E-07 2006.201.15:38:04.13:!2006.201.15:40:49 2006.201.15:40:49.00:data_valid=off 2006.201.15:40:49.00:"et 2006.201.15:40:49.00:!+3s 2006.201.15:40:52.02:"tape 2006.201.15:40:52.02:postob 2006.201.15:40:52.08/cable/+6.4756E-03 2006.201.15:40:52.08/wx/20.84,1002.8,100 2006.201.15:40:52.16/fmout-gps/S +4.50E-07 2006.201.15:40:52.16:scan_name=201-1543,jd0607,80 2006.201.15:40:52.17:source=2136+141,213901.31,142336.0,2000.0,cw 2006.201.15:40:53.14#flagr#flagr/antenna,new-source 2006.201.15:40:53.14:checkk5 2006.201.15:40:53.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:40:53.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:40:54.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:40:54.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:40:55.01/chk_obsdata//k5ts1/T2011537??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.15:40:55.37/chk_obsdata//k5ts2/T2011537??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.15:40:55.74/chk_obsdata//k5ts3/T2011537??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.15:40:56.11/chk_obsdata//k5ts4/T2011537??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.15:40:56.80/k5log//k5ts1_log_newline 2006.201.15:40:57.49/k5log//k5ts2_log_newline 2006.201.15:40:58.18/k5log//k5ts3_log_newline 2006.201.15:40:58.87/k5log//k5ts4_log_newline 2006.201.15:40:58.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:40:58.89:setupk4=1 2006.201.15:40:58.89$setupk4/echo=on 2006.201.15:40:58.89$setupk4/pcalon 2006.201.15:40:58.89$pcalon/"no phase cal control is implemented here 2006.201.15:40:58.89$setupk4/"tpicd=stop 2006.201.15:40:58.89$setupk4/"rec=synch_on 2006.201.15:40:58.89$setupk4/"rec_mode=128 2006.201.15:40:58.89$setupk4/!* 2006.201.15:40:58.89$setupk4/recpk4 2006.201.15:40:58.89$recpk4/recpatch= 2006.201.15:40:58.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:40:58.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:40:58.90$setupk4/vck44 2006.201.15:40:58.90$vck44/valo=1,524.99 2006.201.15:40:58.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.15:40:58.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.15:40:58.90#ibcon#ireg 17 cls_cnt 0 2006.201.15:40:58.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:40:58.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:40:58.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:40:58.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:40:58.90#ibcon#first serial, iclass 20, count 0 2006.201.15:40:58.90#ibcon#enter sib2, iclass 20, count 0 2006.201.15:40:58.90#ibcon#flushed, iclass 20, count 0 2006.201.15:40:58.90#ibcon#about to write, iclass 20, count 0 2006.201.15:40:58.90#ibcon#wrote, iclass 20, count 0 2006.201.15:40:58.90#ibcon#about to read 3, iclass 20, count 0 2006.201.15:40:58.93#ibcon#read 3, iclass 20, count 0 2006.201.15:40:58.93#ibcon#about to read 4, iclass 20, count 0 2006.201.15:40:58.93#ibcon#read 4, iclass 20, count 0 2006.201.15:40:58.93#ibcon#about to read 5, iclass 20, count 0 2006.201.15:40:58.93#ibcon#read 5, iclass 20, count 0 2006.201.15:40:58.93#ibcon#about to read 6, iclass 20, count 0 2006.201.15:40:58.93#ibcon#read 6, iclass 20, count 0 2006.201.15:40:58.93#ibcon#end of sib2, iclass 20, count 0 2006.201.15:40:58.93#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:40:58.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:40:58.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:40:58.93#ibcon#*before write, iclass 20, count 0 2006.201.15:40:58.93#ibcon#enter sib2, iclass 20, count 0 2006.201.15:40:58.93#ibcon#flushed, iclass 20, count 0 2006.201.15:40:58.93#ibcon#about to write, iclass 20, count 0 2006.201.15:40:58.93#ibcon#wrote, iclass 20, count 0 2006.201.15:40:58.93#ibcon#about to read 3, iclass 20, count 0 2006.201.15:40:58.99#ibcon#read 3, iclass 20, count 0 2006.201.15:40:58.99#ibcon#about to read 4, iclass 20, count 0 2006.201.15:40:58.99#ibcon#read 4, iclass 20, count 0 2006.201.15:40:58.99#ibcon#about to read 5, iclass 20, count 0 2006.201.15:40:58.99#ibcon#read 5, iclass 20, count 0 2006.201.15:40:58.99#ibcon#about to read 6, iclass 20, count 0 2006.201.15:40:58.99#ibcon#read 6, iclass 20, count 0 2006.201.15:40:58.99#ibcon#end of sib2, iclass 20, count 0 2006.201.15:40:58.99#ibcon#*after write, iclass 20, count 0 2006.201.15:40:58.99#ibcon#*before return 0, iclass 20, count 0 2006.201.15:40:58.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:40:58.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:40:58.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:40:58.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:40:58.99$vck44/va=1,8 2006.201.15:40:58.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.15:40:58.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.15:40:58.99#ibcon#ireg 11 cls_cnt 2 2006.201.15:40:58.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:40:58.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:40:58.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:40:58.99#ibcon#enter wrdev, iclass 22, count 2 2006.201.15:40:58.99#ibcon#first serial, iclass 22, count 2 2006.201.15:40:58.99#ibcon#enter sib2, iclass 22, count 2 2006.201.15:40:58.99#ibcon#flushed, iclass 22, count 2 2006.201.15:40:58.99#ibcon#about to write, iclass 22, count 2 2006.201.15:40:58.99#ibcon#wrote, iclass 22, count 2 2006.201.15:40:58.99#ibcon#about to read 3, iclass 22, count 2 2006.201.15:40:59.01#ibcon#read 3, iclass 22, count 2 2006.201.15:40:59.01#ibcon#about to read 4, iclass 22, count 2 2006.201.15:40:59.01#ibcon#read 4, iclass 22, count 2 2006.201.15:40:59.01#ibcon#about to read 5, iclass 22, count 2 2006.201.15:40:59.01#ibcon#read 5, iclass 22, count 2 2006.201.15:40:59.01#ibcon#about to read 6, iclass 22, count 2 2006.201.15:40:59.01#ibcon#read 6, iclass 22, count 2 2006.201.15:40:59.01#ibcon#end of sib2, iclass 22, count 2 2006.201.15:40:59.01#ibcon#*mode == 0, iclass 22, count 2 2006.201.15:40:59.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.15:40:59.01#ibcon#[25=AT01-08\r\n] 2006.201.15:40:59.01#ibcon#*before write, iclass 22, count 2 2006.201.15:40:59.01#ibcon#enter sib2, iclass 22, count 2 2006.201.15:40:59.01#ibcon#flushed, iclass 22, count 2 2006.201.15:40:59.01#ibcon#about to write, iclass 22, count 2 2006.201.15:40:59.01#ibcon#wrote, iclass 22, count 2 2006.201.15:40:59.01#ibcon#about to read 3, iclass 22, count 2 2006.201.15:40:59.05#ibcon#read 3, iclass 22, count 2 2006.201.15:40:59.05#ibcon#about to read 4, iclass 22, count 2 2006.201.15:40:59.05#ibcon#read 4, iclass 22, count 2 2006.201.15:40:59.05#ibcon#about to read 5, iclass 22, count 2 2006.201.15:40:59.05#ibcon#read 5, iclass 22, count 2 2006.201.15:40:59.05#ibcon#about to read 6, iclass 22, count 2 2006.201.15:40:59.05#ibcon#read 6, iclass 22, count 2 2006.201.15:40:59.05#ibcon#end of sib2, iclass 22, count 2 2006.201.15:40:59.05#ibcon#*after write, iclass 22, count 2 2006.201.15:40:59.05#ibcon#*before return 0, iclass 22, count 2 2006.201.15:40:59.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:40:59.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:40:59.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.15:40:59.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:40:59.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:40:59.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:40:59.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:40:59.17#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:40:59.17#ibcon#first serial, iclass 22, count 0 2006.201.15:40:59.17#ibcon#enter sib2, iclass 22, count 0 2006.201.15:40:59.17#ibcon#flushed, iclass 22, count 0 2006.201.15:40:59.17#ibcon#about to write, iclass 22, count 0 2006.201.15:40:59.17#ibcon#wrote, iclass 22, count 0 2006.201.15:40:59.17#ibcon#about to read 3, iclass 22, count 0 2006.201.15:40:59.20#ibcon#read 3, iclass 22, count 0 2006.201.15:40:59.20#ibcon#about to read 4, iclass 22, count 0 2006.201.15:40:59.20#ibcon#read 4, iclass 22, count 0 2006.201.15:40:59.20#ibcon#about to read 5, iclass 22, count 0 2006.201.15:40:59.20#ibcon#read 5, iclass 22, count 0 2006.201.15:40:59.20#ibcon#about to read 6, iclass 22, count 0 2006.201.15:40:59.20#ibcon#read 6, iclass 22, count 0 2006.201.15:40:59.20#ibcon#end of sib2, iclass 22, count 0 2006.201.15:40:59.20#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:40:59.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:40:59.20#ibcon#[25=USB\r\n] 2006.201.15:40:59.20#ibcon#*before write, iclass 22, count 0 2006.201.15:40:59.20#ibcon#enter sib2, iclass 22, count 0 2006.201.15:40:59.20#ibcon#flushed, iclass 22, count 0 2006.201.15:40:59.20#ibcon#about to write, iclass 22, count 0 2006.201.15:40:59.20#ibcon#wrote, iclass 22, count 0 2006.201.15:40:59.20#ibcon#about to read 3, iclass 22, count 0 2006.201.15:40:59.23#ibcon#read 3, iclass 22, count 0 2006.201.15:40:59.23#ibcon#about to read 4, iclass 22, count 0 2006.201.15:40:59.23#ibcon#read 4, iclass 22, count 0 2006.201.15:40:59.23#ibcon#about to read 5, iclass 22, count 0 2006.201.15:40:59.23#ibcon#read 5, iclass 22, count 0 2006.201.15:40:59.23#ibcon#about to read 6, iclass 22, count 0 2006.201.15:40:59.23#ibcon#read 6, iclass 22, count 0 2006.201.15:40:59.23#ibcon#end of sib2, iclass 22, count 0 2006.201.15:40:59.23#ibcon#*after write, iclass 22, count 0 2006.201.15:40:59.23#ibcon#*before return 0, iclass 22, count 0 2006.201.15:40:59.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:40:59.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:40:59.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:40:59.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:40:59.23$vck44/valo=2,534.99 2006.201.15:40:59.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.15:40:59.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.15:40:59.23#ibcon#ireg 17 cls_cnt 0 2006.201.15:40:59.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:40:59.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:40:59.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:40:59.23#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:40:59.23#ibcon#first serial, iclass 24, count 0 2006.201.15:40:59.23#ibcon#enter sib2, iclass 24, count 0 2006.201.15:40:59.23#ibcon#flushed, iclass 24, count 0 2006.201.15:40:59.23#ibcon#about to write, iclass 24, count 0 2006.201.15:40:59.23#ibcon#wrote, iclass 24, count 0 2006.201.15:40:59.23#ibcon#about to read 3, iclass 24, count 0 2006.201.15:40:59.25#ibcon#read 3, iclass 24, count 0 2006.201.15:40:59.25#ibcon#about to read 4, iclass 24, count 0 2006.201.15:40:59.25#ibcon#read 4, iclass 24, count 0 2006.201.15:40:59.25#ibcon#about to read 5, iclass 24, count 0 2006.201.15:40:59.25#ibcon#read 5, iclass 24, count 0 2006.201.15:40:59.25#ibcon#about to read 6, iclass 24, count 0 2006.201.15:40:59.25#ibcon#read 6, iclass 24, count 0 2006.201.15:40:59.25#ibcon#end of sib2, iclass 24, count 0 2006.201.15:40:59.25#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:40:59.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:40:59.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:40:59.25#ibcon#*before write, iclass 24, count 0 2006.201.15:40:59.25#ibcon#enter sib2, iclass 24, count 0 2006.201.15:40:59.25#ibcon#flushed, iclass 24, count 0 2006.201.15:40:59.25#ibcon#about to write, iclass 24, count 0 2006.201.15:40:59.25#ibcon#wrote, iclass 24, count 0 2006.201.15:40:59.25#ibcon#about to read 3, iclass 24, count 0 2006.201.15:40:59.29#ibcon#read 3, iclass 24, count 0 2006.201.15:40:59.29#ibcon#about to read 4, iclass 24, count 0 2006.201.15:40:59.29#ibcon#read 4, iclass 24, count 0 2006.201.15:40:59.29#ibcon#about to read 5, iclass 24, count 0 2006.201.15:40:59.29#ibcon#read 5, iclass 24, count 0 2006.201.15:40:59.29#ibcon#about to read 6, iclass 24, count 0 2006.201.15:40:59.29#ibcon#read 6, iclass 24, count 0 2006.201.15:40:59.29#ibcon#end of sib2, iclass 24, count 0 2006.201.15:40:59.29#ibcon#*after write, iclass 24, count 0 2006.201.15:40:59.29#ibcon#*before return 0, iclass 24, count 0 2006.201.15:40:59.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:40:59.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:40:59.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:40:59.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:40:59.29$vck44/va=2,7 2006.201.15:40:59.29#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.15:40:59.29#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.15:40:59.29#ibcon#ireg 11 cls_cnt 2 2006.201.15:40:59.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:40:59.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:40:59.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:40:59.35#ibcon#enter wrdev, iclass 26, count 2 2006.201.15:40:59.35#ibcon#first serial, iclass 26, count 2 2006.201.15:40:59.35#ibcon#enter sib2, iclass 26, count 2 2006.201.15:40:59.35#ibcon#flushed, iclass 26, count 2 2006.201.15:40:59.35#ibcon#about to write, iclass 26, count 2 2006.201.15:40:59.35#ibcon#wrote, iclass 26, count 2 2006.201.15:40:59.35#ibcon#about to read 3, iclass 26, count 2 2006.201.15:40:59.37#ibcon#read 3, iclass 26, count 2 2006.201.15:40:59.37#ibcon#about to read 4, iclass 26, count 2 2006.201.15:40:59.37#ibcon#read 4, iclass 26, count 2 2006.201.15:40:59.37#ibcon#about to read 5, iclass 26, count 2 2006.201.15:40:59.37#ibcon#read 5, iclass 26, count 2 2006.201.15:40:59.37#ibcon#about to read 6, iclass 26, count 2 2006.201.15:40:59.37#ibcon#read 6, iclass 26, count 2 2006.201.15:40:59.37#ibcon#end of sib2, iclass 26, count 2 2006.201.15:40:59.37#ibcon#*mode == 0, iclass 26, count 2 2006.201.15:40:59.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.15:40:59.37#ibcon#[25=AT02-07\r\n] 2006.201.15:40:59.37#ibcon#*before write, iclass 26, count 2 2006.201.15:40:59.37#ibcon#enter sib2, iclass 26, count 2 2006.201.15:40:59.37#ibcon#flushed, iclass 26, count 2 2006.201.15:40:59.37#ibcon#about to write, iclass 26, count 2 2006.201.15:40:59.37#ibcon#wrote, iclass 26, count 2 2006.201.15:40:59.37#ibcon#about to read 3, iclass 26, count 2 2006.201.15:40:59.40#ibcon#read 3, iclass 26, count 2 2006.201.15:40:59.40#ibcon#about to read 4, iclass 26, count 2 2006.201.15:40:59.40#ibcon#read 4, iclass 26, count 2 2006.201.15:40:59.40#ibcon#about to read 5, iclass 26, count 2 2006.201.15:40:59.40#ibcon#read 5, iclass 26, count 2 2006.201.15:40:59.40#ibcon#about to read 6, iclass 26, count 2 2006.201.15:40:59.40#ibcon#read 6, iclass 26, count 2 2006.201.15:40:59.40#ibcon#end of sib2, iclass 26, count 2 2006.201.15:40:59.40#ibcon#*after write, iclass 26, count 2 2006.201.15:40:59.40#ibcon#*before return 0, iclass 26, count 2 2006.201.15:40:59.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:40:59.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:40:59.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.15:40:59.40#ibcon#ireg 7 cls_cnt 0 2006.201.15:40:59.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:40:59.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:40:59.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:40:59.52#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:40:59.52#ibcon#first serial, iclass 26, count 0 2006.201.15:40:59.52#ibcon#enter sib2, iclass 26, count 0 2006.201.15:40:59.52#ibcon#flushed, iclass 26, count 0 2006.201.15:40:59.52#ibcon#about to write, iclass 26, count 0 2006.201.15:40:59.52#ibcon#wrote, iclass 26, count 0 2006.201.15:40:59.52#ibcon#about to read 3, iclass 26, count 0 2006.201.15:40:59.54#ibcon#read 3, iclass 26, count 0 2006.201.15:40:59.54#ibcon#about to read 4, iclass 26, count 0 2006.201.15:40:59.54#ibcon#read 4, iclass 26, count 0 2006.201.15:40:59.54#ibcon#about to read 5, iclass 26, count 0 2006.201.15:40:59.54#ibcon#read 5, iclass 26, count 0 2006.201.15:40:59.54#ibcon#about to read 6, iclass 26, count 0 2006.201.15:40:59.54#ibcon#read 6, iclass 26, count 0 2006.201.15:40:59.54#ibcon#end of sib2, iclass 26, count 0 2006.201.15:40:59.54#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:40:59.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:40:59.54#ibcon#[25=USB\r\n] 2006.201.15:40:59.54#ibcon#*before write, iclass 26, count 0 2006.201.15:40:59.54#ibcon#enter sib2, iclass 26, count 0 2006.201.15:40:59.54#ibcon#flushed, iclass 26, count 0 2006.201.15:40:59.54#ibcon#about to write, iclass 26, count 0 2006.201.15:40:59.54#ibcon#wrote, iclass 26, count 0 2006.201.15:40:59.54#ibcon#about to read 3, iclass 26, count 0 2006.201.15:40:59.57#ibcon#read 3, iclass 26, count 0 2006.201.15:40:59.57#ibcon#about to read 4, iclass 26, count 0 2006.201.15:40:59.57#ibcon#read 4, iclass 26, count 0 2006.201.15:40:59.57#ibcon#about to read 5, iclass 26, count 0 2006.201.15:40:59.57#ibcon#read 5, iclass 26, count 0 2006.201.15:40:59.57#ibcon#about to read 6, iclass 26, count 0 2006.201.15:40:59.57#ibcon#read 6, iclass 26, count 0 2006.201.15:40:59.57#ibcon#end of sib2, iclass 26, count 0 2006.201.15:40:59.57#ibcon#*after write, iclass 26, count 0 2006.201.15:40:59.57#ibcon#*before return 0, iclass 26, count 0 2006.201.15:40:59.57#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:40:59.57#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:40:59.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:40:59.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:40:59.57$vck44/valo=3,564.99 2006.201.15:40:59.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.15:40:59.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.15:40:59.57#ibcon#ireg 17 cls_cnt 0 2006.201.15:40:59.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:40:59.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:40:59.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:40:59.57#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:40:59.57#ibcon#first serial, iclass 28, count 0 2006.201.15:40:59.57#ibcon#enter sib2, iclass 28, count 0 2006.201.15:40:59.57#ibcon#flushed, iclass 28, count 0 2006.201.15:40:59.57#ibcon#about to write, iclass 28, count 0 2006.201.15:40:59.57#ibcon#wrote, iclass 28, count 0 2006.201.15:40:59.57#ibcon#about to read 3, iclass 28, count 0 2006.201.15:40:59.59#ibcon#read 3, iclass 28, count 0 2006.201.15:40:59.59#ibcon#about to read 4, iclass 28, count 0 2006.201.15:40:59.59#ibcon#read 4, iclass 28, count 0 2006.201.15:40:59.59#ibcon#about to read 5, iclass 28, count 0 2006.201.15:40:59.59#ibcon#read 5, iclass 28, count 0 2006.201.15:40:59.59#ibcon#about to read 6, iclass 28, count 0 2006.201.15:40:59.59#ibcon#read 6, iclass 28, count 0 2006.201.15:40:59.59#ibcon#end of sib2, iclass 28, count 0 2006.201.15:40:59.59#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:40:59.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:40:59.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:40:59.59#ibcon#*before write, iclass 28, count 0 2006.201.15:40:59.59#ibcon#enter sib2, iclass 28, count 0 2006.201.15:40:59.59#ibcon#flushed, iclass 28, count 0 2006.201.15:40:59.59#ibcon#about to write, iclass 28, count 0 2006.201.15:40:59.59#ibcon#wrote, iclass 28, count 0 2006.201.15:40:59.59#ibcon#about to read 3, iclass 28, count 0 2006.201.15:40:59.64#ibcon#read 3, iclass 28, count 0 2006.201.15:40:59.64#ibcon#about to read 4, iclass 28, count 0 2006.201.15:40:59.64#ibcon#read 4, iclass 28, count 0 2006.201.15:40:59.64#ibcon#about to read 5, iclass 28, count 0 2006.201.15:40:59.64#ibcon#read 5, iclass 28, count 0 2006.201.15:40:59.64#ibcon#about to read 6, iclass 28, count 0 2006.201.15:40:59.64#ibcon#read 6, iclass 28, count 0 2006.201.15:40:59.64#ibcon#end of sib2, iclass 28, count 0 2006.201.15:40:59.64#ibcon#*after write, iclass 28, count 0 2006.201.15:40:59.64#ibcon#*before return 0, iclass 28, count 0 2006.201.15:40:59.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:40:59.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:40:59.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:40:59.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:40:59.64$vck44/va=3,8 2006.201.15:40:59.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.15:40:59.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.15:40:59.64#ibcon#ireg 11 cls_cnt 2 2006.201.15:40:59.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:40:59.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:40:59.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:40:59.69#ibcon#enter wrdev, iclass 30, count 2 2006.201.15:40:59.69#ibcon#first serial, iclass 30, count 2 2006.201.15:40:59.69#ibcon#enter sib2, iclass 30, count 2 2006.201.15:40:59.69#ibcon#flushed, iclass 30, count 2 2006.201.15:40:59.69#ibcon#about to write, iclass 30, count 2 2006.201.15:40:59.69#ibcon#wrote, iclass 30, count 2 2006.201.15:40:59.69#ibcon#about to read 3, iclass 30, count 2 2006.201.15:40:59.71#ibcon#read 3, iclass 30, count 2 2006.201.15:40:59.71#ibcon#about to read 4, iclass 30, count 2 2006.201.15:40:59.71#ibcon#read 4, iclass 30, count 2 2006.201.15:40:59.71#ibcon#about to read 5, iclass 30, count 2 2006.201.15:40:59.71#ibcon#read 5, iclass 30, count 2 2006.201.15:40:59.71#ibcon#about to read 6, iclass 30, count 2 2006.201.15:40:59.71#ibcon#read 6, iclass 30, count 2 2006.201.15:40:59.71#ibcon#end of sib2, iclass 30, count 2 2006.201.15:40:59.71#ibcon#*mode == 0, iclass 30, count 2 2006.201.15:40:59.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.15:40:59.71#ibcon#[25=AT03-08\r\n] 2006.201.15:40:59.71#ibcon#*before write, iclass 30, count 2 2006.201.15:40:59.71#ibcon#enter sib2, iclass 30, count 2 2006.201.15:40:59.71#ibcon#flushed, iclass 30, count 2 2006.201.15:40:59.71#ibcon#about to write, iclass 30, count 2 2006.201.15:40:59.71#ibcon#wrote, iclass 30, count 2 2006.201.15:40:59.71#ibcon#about to read 3, iclass 30, count 2 2006.201.15:40:59.74#ibcon#read 3, iclass 30, count 2 2006.201.15:40:59.74#ibcon#about to read 4, iclass 30, count 2 2006.201.15:40:59.74#ibcon#read 4, iclass 30, count 2 2006.201.15:40:59.74#ibcon#about to read 5, iclass 30, count 2 2006.201.15:40:59.74#ibcon#read 5, iclass 30, count 2 2006.201.15:40:59.74#ibcon#about to read 6, iclass 30, count 2 2006.201.15:40:59.74#ibcon#read 6, iclass 30, count 2 2006.201.15:40:59.74#ibcon#end of sib2, iclass 30, count 2 2006.201.15:40:59.74#ibcon#*after write, iclass 30, count 2 2006.201.15:40:59.74#ibcon#*before return 0, iclass 30, count 2 2006.201.15:40:59.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:40:59.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:40:59.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.15:40:59.74#ibcon#ireg 7 cls_cnt 0 2006.201.15:40:59.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:40:59.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:40:59.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:40:59.86#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:40:59.86#ibcon#first serial, iclass 30, count 0 2006.201.15:40:59.86#ibcon#enter sib2, iclass 30, count 0 2006.201.15:40:59.86#ibcon#flushed, iclass 30, count 0 2006.201.15:40:59.86#ibcon#about to write, iclass 30, count 0 2006.201.15:40:59.86#ibcon#wrote, iclass 30, count 0 2006.201.15:40:59.86#ibcon#about to read 3, iclass 30, count 0 2006.201.15:40:59.88#ibcon#read 3, iclass 30, count 0 2006.201.15:40:59.88#ibcon#about to read 4, iclass 30, count 0 2006.201.15:40:59.88#ibcon#read 4, iclass 30, count 0 2006.201.15:40:59.88#ibcon#about to read 5, iclass 30, count 0 2006.201.15:40:59.88#ibcon#read 5, iclass 30, count 0 2006.201.15:40:59.88#ibcon#about to read 6, iclass 30, count 0 2006.201.15:40:59.88#ibcon#read 6, iclass 30, count 0 2006.201.15:40:59.88#ibcon#end of sib2, iclass 30, count 0 2006.201.15:40:59.88#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:40:59.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:40:59.88#ibcon#[25=USB\r\n] 2006.201.15:40:59.88#ibcon#*before write, iclass 30, count 0 2006.201.15:40:59.88#ibcon#enter sib2, iclass 30, count 0 2006.201.15:40:59.88#ibcon#flushed, iclass 30, count 0 2006.201.15:40:59.88#ibcon#about to write, iclass 30, count 0 2006.201.15:40:59.88#ibcon#wrote, iclass 30, count 0 2006.201.15:40:59.88#ibcon#about to read 3, iclass 30, count 0 2006.201.15:40:59.91#ibcon#read 3, iclass 30, count 0 2006.201.15:40:59.91#ibcon#about to read 4, iclass 30, count 0 2006.201.15:40:59.91#ibcon#read 4, iclass 30, count 0 2006.201.15:40:59.91#ibcon#about to read 5, iclass 30, count 0 2006.201.15:40:59.91#ibcon#read 5, iclass 30, count 0 2006.201.15:40:59.91#ibcon#about to read 6, iclass 30, count 0 2006.201.15:40:59.91#ibcon#read 6, iclass 30, count 0 2006.201.15:40:59.91#ibcon#end of sib2, iclass 30, count 0 2006.201.15:40:59.91#ibcon#*after write, iclass 30, count 0 2006.201.15:40:59.91#ibcon#*before return 0, iclass 30, count 0 2006.201.15:40:59.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:40:59.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:40:59.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:40:59.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:40:59.91$vck44/valo=4,624.99 2006.201.15:40:59.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.15:40:59.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.15:40:59.91#ibcon#ireg 17 cls_cnt 0 2006.201.15:40:59.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:40:59.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:40:59.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:40:59.91#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:40:59.91#ibcon#first serial, iclass 32, count 0 2006.201.15:40:59.91#ibcon#enter sib2, iclass 32, count 0 2006.201.15:40:59.91#ibcon#flushed, iclass 32, count 0 2006.201.15:40:59.91#ibcon#about to write, iclass 32, count 0 2006.201.15:40:59.91#ibcon#wrote, iclass 32, count 0 2006.201.15:40:59.91#ibcon#about to read 3, iclass 32, count 0 2006.201.15:40:59.93#ibcon#read 3, iclass 32, count 0 2006.201.15:40:59.93#ibcon#about to read 4, iclass 32, count 0 2006.201.15:40:59.93#ibcon#read 4, iclass 32, count 0 2006.201.15:40:59.93#ibcon#about to read 5, iclass 32, count 0 2006.201.15:40:59.93#ibcon#read 5, iclass 32, count 0 2006.201.15:40:59.93#ibcon#about to read 6, iclass 32, count 0 2006.201.15:40:59.93#ibcon#read 6, iclass 32, count 0 2006.201.15:40:59.93#ibcon#end of sib2, iclass 32, count 0 2006.201.15:40:59.93#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:40:59.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:40:59.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:40:59.93#ibcon#*before write, iclass 32, count 0 2006.201.15:40:59.93#ibcon#enter sib2, iclass 32, count 0 2006.201.15:40:59.93#ibcon#flushed, iclass 32, count 0 2006.201.15:40:59.93#ibcon#about to write, iclass 32, count 0 2006.201.15:40:59.93#ibcon#wrote, iclass 32, count 0 2006.201.15:40:59.93#ibcon#about to read 3, iclass 32, count 0 2006.201.15:40:59.98#ibcon#read 3, iclass 32, count 0 2006.201.15:40:59.98#ibcon#about to read 4, iclass 32, count 0 2006.201.15:40:59.98#ibcon#read 4, iclass 32, count 0 2006.201.15:40:59.98#ibcon#about to read 5, iclass 32, count 0 2006.201.15:40:59.98#ibcon#read 5, iclass 32, count 0 2006.201.15:40:59.98#ibcon#about to read 6, iclass 32, count 0 2006.201.15:40:59.98#ibcon#read 6, iclass 32, count 0 2006.201.15:40:59.98#ibcon#end of sib2, iclass 32, count 0 2006.201.15:40:59.98#ibcon#*after write, iclass 32, count 0 2006.201.15:40:59.98#ibcon#*before return 0, iclass 32, count 0 2006.201.15:40:59.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:40:59.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:40:59.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:40:59.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:40:59.98$vck44/va=4,7 2006.201.15:40:59.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.15:40:59.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.15:40:59.98#ibcon#ireg 11 cls_cnt 2 2006.201.15:40:59.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:00.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:00.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:00.03#ibcon#enter wrdev, iclass 34, count 2 2006.201.15:41:00.03#ibcon#first serial, iclass 34, count 2 2006.201.15:41:00.03#ibcon#enter sib2, iclass 34, count 2 2006.201.15:41:00.03#ibcon#flushed, iclass 34, count 2 2006.201.15:41:00.03#ibcon#about to write, iclass 34, count 2 2006.201.15:41:00.03#ibcon#wrote, iclass 34, count 2 2006.201.15:41:00.03#ibcon#about to read 3, iclass 34, count 2 2006.201.15:41:00.05#ibcon#read 3, iclass 34, count 2 2006.201.15:41:00.05#ibcon#about to read 4, iclass 34, count 2 2006.201.15:41:00.05#ibcon#read 4, iclass 34, count 2 2006.201.15:41:00.05#ibcon#about to read 5, iclass 34, count 2 2006.201.15:41:00.05#ibcon#read 5, iclass 34, count 2 2006.201.15:41:00.05#ibcon#about to read 6, iclass 34, count 2 2006.201.15:41:00.05#ibcon#read 6, iclass 34, count 2 2006.201.15:41:00.05#ibcon#end of sib2, iclass 34, count 2 2006.201.15:41:00.05#ibcon#*mode == 0, iclass 34, count 2 2006.201.15:41:00.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.15:41:00.05#ibcon#[25=AT04-07\r\n] 2006.201.15:41:00.05#ibcon#*before write, iclass 34, count 2 2006.201.15:41:00.05#ibcon#enter sib2, iclass 34, count 2 2006.201.15:41:00.05#ibcon#flushed, iclass 34, count 2 2006.201.15:41:00.05#ibcon#about to write, iclass 34, count 2 2006.201.15:41:00.05#ibcon#wrote, iclass 34, count 2 2006.201.15:41:00.05#ibcon#about to read 3, iclass 34, count 2 2006.201.15:41:00.08#ibcon#read 3, iclass 34, count 2 2006.201.15:41:00.08#ibcon#about to read 4, iclass 34, count 2 2006.201.15:41:00.08#ibcon#read 4, iclass 34, count 2 2006.201.15:41:00.08#ibcon#about to read 5, iclass 34, count 2 2006.201.15:41:00.08#ibcon#read 5, iclass 34, count 2 2006.201.15:41:00.08#ibcon#about to read 6, iclass 34, count 2 2006.201.15:41:00.08#ibcon#read 6, iclass 34, count 2 2006.201.15:41:00.08#ibcon#end of sib2, iclass 34, count 2 2006.201.15:41:00.08#ibcon#*after write, iclass 34, count 2 2006.201.15:41:00.08#ibcon#*before return 0, iclass 34, count 2 2006.201.15:41:00.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:00.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:00.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.15:41:00.08#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:00.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:00.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:00.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:00.20#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:41:00.20#ibcon#first serial, iclass 34, count 0 2006.201.15:41:00.20#ibcon#enter sib2, iclass 34, count 0 2006.201.15:41:00.20#ibcon#flushed, iclass 34, count 0 2006.201.15:41:00.20#ibcon#about to write, iclass 34, count 0 2006.201.15:41:00.20#ibcon#wrote, iclass 34, count 0 2006.201.15:41:00.20#ibcon#about to read 3, iclass 34, count 0 2006.201.15:41:00.22#ibcon#read 3, iclass 34, count 0 2006.201.15:41:00.22#ibcon#about to read 4, iclass 34, count 0 2006.201.15:41:00.22#ibcon#read 4, iclass 34, count 0 2006.201.15:41:00.22#ibcon#about to read 5, iclass 34, count 0 2006.201.15:41:00.22#ibcon#read 5, iclass 34, count 0 2006.201.15:41:00.22#ibcon#about to read 6, iclass 34, count 0 2006.201.15:41:00.22#ibcon#read 6, iclass 34, count 0 2006.201.15:41:00.22#ibcon#end of sib2, iclass 34, count 0 2006.201.15:41:00.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:41:00.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:41:00.22#ibcon#[25=USB\r\n] 2006.201.15:41:00.22#ibcon#*before write, iclass 34, count 0 2006.201.15:41:00.22#ibcon#enter sib2, iclass 34, count 0 2006.201.15:41:00.22#ibcon#flushed, iclass 34, count 0 2006.201.15:41:00.22#ibcon#about to write, iclass 34, count 0 2006.201.15:41:00.22#ibcon#wrote, iclass 34, count 0 2006.201.15:41:00.22#ibcon#about to read 3, iclass 34, count 0 2006.201.15:41:00.25#ibcon#read 3, iclass 34, count 0 2006.201.15:41:00.25#ibcon#about to read 4, iclass 34, count 0 2006.201.15:41:00.25#ibcon#read 4, iclass 34, count 0 2006.201.15:41:00.25#ibcon#about to read 5, iclass 34, count 0 2006.201.15:41:00.25#ibcon#read 5, iclass 34, count 0 2006.201.15:41:00.25#ibcon#about to read 6, iclass 34, count 0 2006.201.15:41:00.25#ibcon#read 6, iclass 34, count 0 2006.201.15:41:00.25#ibcon#end of sib2, iclass 34, count 0 2006.201.15:41:00.25#ibcon#*after write, iclass 34, count 0 2006.201.15:41:00.25#ibcon#*before return 0, iclass 34, count 0 2006.201.15:41:00.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:00.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:00.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:41:00.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:41:00.25$vck44/valo=5,734.99 2006.201.15:41:00.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.15:41:00.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.15:41:00.25#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:00.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:00.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:00.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:00.25#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:41:00.25#ibcon#first serial, iclass 36, count 0 2006.201.15:41:00.25#ibcon#enter sib2, iclass 36, count 0 2006.201.15:41:00.25#ibcon#flushed, iclass 36, count 0 2006.201.15:41:00.25#ibcon#about to write, iclass 36, count 0 2006.201.15:41:00.25#ibcon#wrote, iclass 36, count 0 2006.201.15:41:00.25#ibcon#about to read 3, iclass 36, count 0 2006.201.15:41:00.27#ibcon#read 3, iclass 36, count 0 2006.201.15:41:00.27#ibcon#about to read 4, iclass 36, count 0 2006.201.15:41:00.27#ibcon#read 4, iclass 36, count 0 2006.201.15:41:00.27#ibcon#about to read 5, iclass 36, count 0 2006.201.15:41:00.27#ibcon#read 5, iclass 36, count 0 2006.201.15:41:00.27#ibcon#about to read 6, iclass 36, count 0 2006.201.15:41:00.27#ibcon#read 6, iclass 36, count 0 2006.201.15:41:00.27#ibcon#end of sib2, iclass 36, count 0 2006.201.15:41:00.27#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:41:00.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:41:00.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:41:00.27#ibcon#*before write, iclass 36, count 0 2006.201.15:41:00.27#ibcon#enter sib2, iclass 36, count 0 2006.201.15:41:00.27#ibcon#flushed, iclass 36, count 0 2006.201.15:41:00.27#ibcon#about to write, iclass 36, count 0 2006.201.15:41:00.27#ibcon#wrote, iclass 36, count 0 2006.201.15:41:00.27#ibcon#about to read 3, iclass 36, count 0 2006.201.15:41:00.31#ibcon#read 3, iclass 36, count 0 2006.201.15:41:00.31#ibcon#about to read 4, iclass 36, count 0 2006.201.15:41:00.31#ibcon#read 4, iclass 36, count 0 2006.201.15:41:00.31#ibcon#about to read 5, iclass 36, count 0 2006.201.15:41:00.31#ibcon#read 5, iclass 36, count 0 2006.201.15:41:00.31#ibcon#about to read 6, iclass 36, count 0 2006.201.15:41:00.31#ibcon#read 6, iclass 36, count 0 2006.201.15:41:00.31#ibcon#end of sib2, iclass 36, count 0 2006.201.15:41:00.31#ibcon#*after write, iclass 36, count 0 2006.201.15:41:00.31#ibcon#*before return 0, iclass 36, count 0 2006.201.15:41:00.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:00.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:00.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:41:00.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:41:00.31$vck44/va=5,4 2006.201.15:41:00.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.15:41:00.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.15:41:00.31#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:00.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:00.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:00.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:00.37#ibcon#enter wrdev, iclass 38, count 2 2006.201.15:41:00.37#ibcon#first serial, iclass 38, count 2 2006.201.15:41:00.37#ibcon#enter sib2, iclass 38, count 2 2006.201.15:41:00.37#ibcon#flushed, iclass 38, count 2 2006.201.15:41:00.37#ibcon#about to write, iclass 38, count 2 2006.201.15:41:00.37#ibcon#wrote, iclass 38, count 2 2006.201.15:41:00.37#ibcon#about to read 3, iclass 38, count 2 2006.201.15:41:00.39#ibcon#read 3, iclass 38, count 2 2006.201.15:41:00.39#ibcon#about to read 4, iclass 38, count 2 2006.201.15:41:00.39#ibcon#read 4, iclass 38, count 2 2006.201.15:41:00.39#ibcon#about to read 5, iclass 38, count 2 2006.201.15:41:00.39#ibcon#read 5, iclass 38, count 2 2006.201.15:41:00.39#ibcon#about to read 6, iclass 38, count 2 2006.201.15:41:00.39#ibcon#read 6, iclass 38, count 2 2006.201.15:41:00.39#ibcon#end of sib2, iclass 38, count 2 2006.201.15:41:00.39#ibcon#*mode == 0, iclass 38, count 2 2006.201.15:41:00.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.15:41:00.39#ibcon#[25=AT05-04\r\n] 2006.201.15:41:00.39#ibcon#*before write, iclass 38, count 2 2006.201.15:41:00.39#ibcon#enter sib2, iclass 38, count 2 2006.201.15:41:00.39#ibcon#flushed, iclass 38, count 2 2006.201.15:41:00.39#ibcon#about to write, iclass 38, count 2 2006.201.15:41:00.39#ibcon#wrote, iclass 38, count 2 2006.201.15:41:00.39#ibcon#about to read 3, iclass 38, count 2 2006.201.15:41:00.42#ibcon#read 3, iclass 38, count 2 2006.201.15:41:00.42#ibcon#about to read 4, iclass 38, count 2 2006.201.15:41:00.42#ibcon#read 4, iclass 38, count 2 2006.201.15:41:00.42#ibcon#about to read 5, iclass 38, count 2 2006.201.15:41:00.42#ibcon#read 5, iclass 38, count 2 2006.201.15:41:00.42#ibcon#about to read 6, iclass 38, count 2 2006.201.15:41:00.42#ibcon#read 6, iclass 38, count 2 2006.201.15:41:00.42#ibcon#end of sib2, iclass 38, count 2 2006.201.15:41:00.42#ibcon#*after write, iclass 38, count 2 2006.201.15:41:00.42#ibcon#*before return 0, iclass 38, count 2 2006.201.15:41:00.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:00.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:00.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.15:41:00.42#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:00.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:00.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:00.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:00.54#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:41:00.54#ibcon#first serial, iclass 38, count 0 2006.201.15:41:00.54#ibcon#enter sib2, iclass 38, count 0 2006.201.15:41:00.54#ibcon#flushed, iclass 38, count 0 2006.201.15:41:00.54#ibcon#about to write, iclass 38, count 0 2006.201.15:41:00.54#ibcon#wrote, iclass 38, count 0 2006.201.15:41:00.54#ibcon#about to read 3, iclass 38, count 0 2006.201.15:41:00.56#ibcon#read 3, iclass 38, count 0 2006.201.15:41:00.56#ibcon#about to read 4, iclass 38, count 0 2006.201.15:41:00.56#ibcon#read 4, iclass 38, count 0 2006.201.15:41:00.56#ibcon#about to read 5, iclass 38, count 0 2006.201.15:41:00.56#ibcon#read 5, iclass 38, count 0 2006.201.15:41:00.56#ibcon#about to read 6, iclass 38, count 0 2006.201.15:41:00.56#ibcon#read 6, iclass 38, count 0 2006.201.15:41:00.56#ibcon#end of sib2, iclass 38, count 0 2006.201.15:41:00.56#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:41:00.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:41:00.56#ibcon#[25=USB\r\n] 2006.201.15:41:00.56#ibcon#*before write, iclass 38, count 0 2006.201.15:41:00.56#ibcon#enter sib2, iclass 38, count 0 2006.201.15:41:00.56#ibcon#flushed, iclass 38, count 0 2006.201.15:41:00.56#ibcon#about to write, iclass 38, count 0 2006.201.15:41:00.56#ibcon#wrote, iclass 38, count 0 2006.201.15:41:00.56#ibcon#about to read 3, iclass 38, count 0 2006.201.15:41:00.59#ibcon#read 3, iclass 38, count 0 2006.201.15:41:00.59#ibcon#about to read 4, iclass 38, count 0 2006.201.15:41:00.59#ibcon#read 4, iclass 38, count 0 2006.201.15:41:00.59#ibcon#about to read 5, iclass 38, count 0 2006.201.15:41:00.59#ibcon#read 5, iclass 38, count 0 2006.201.15:41:00.59#ibcon#about to read 6, iclass 38, count 0 2006.201.15:41:00.59#ibcon#read 6, iclass 38, count 0 2006.201.15:41:00.59#ibcon#end of sib2, iclass 38, count 0 2006.201.15:41:00.59#ibcon#*after write, iclass 38, count 0 2006.201.15:41:00.59#ibcon#*before return 0, iclass 38, count 0 2006.201.15:41:00.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:00.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:00.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:41:00.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:41:00.59$vck44/valo=6,814.99 2006.201.15:41:00.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.15:41:00.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.15:41:00.59#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:00.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:00.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:00.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:00.59#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:41:00.59#ibcon#first serial, iclass 40, count 0 2006.201.15:41:00.59#ibcon#enter sib2, iclass 40, count 0 2006.201.15:41:00.59#ibcon#flushed, iclass 40, count 0 2006.201.15:41:00.59#ibcon#about to write, iclass 40, count 0 2006.201.15:41:00.59#ibcon#wrote, iclass 40, count 0 2006.201.15:41:00.59#ibcon#about to read 3, iclass 40, count 0 2006.201.15:41:00.61#ibcon#read 3, iclass 40, count 0 2006.201.15:41:00.61#ibcon#about to read 4, iclass 40, count 0 2006.201.15:41:00.61#ibcon#read 4, iclass 40, count 0 2006.201.15:41:00.61#ibcon#about to read 5, iclass 40, count 0 2006.201.15:41:00.61#ibcon#read 5, iclass 40, count 0 2006.201.15:41:00.61#ibcon#about to read 6, iclass 40, count 0 2006.201.15:41:00.61#ibcon#read 6, iclass 40, count 0 2006.201.15:41:00.61#ibcon#end of sib2, iclass 40, count 0 2006.201.15:41:00.61#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:41:00.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:41:00.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:41:00.61#ibcon#*before write, iclass 40, count 0 2006.201.15:41:00.61#ibcon#enter sib2, iclass 40, count 0 2006.201.15:41:00.61#ibcon#flushed, iclass 40, count 0 2006.201.15:41:00.61#ibcon#about to write, iclass 40, count 0 2006.201.15:41:00.61#ibcon#wrote, iclass 40, count 0 2006.201.15:41:00.61#ibcon#about to read 3, iclass 40, count 0 2006.201.15:41:00.66#ibcon#read 3, iclass 40, count 0 2006.201.15:41:00.66#ibcon#about to read 4, iclass 40, count 0 2006.201.15:41:00.66#ibcon#read 4, iclass 40, count 0 2006.201.15:41:00.66#ibcon#about to read 5, iclass 40, count 0 2006.201.15:41:00.66#ibcon#read 5, iclass 40, count 0 2006.201.15:41:00.66#ibcon#about to read 6, iclass 40, count 0 2006.201.15:41:00.66#ibcon#read 6, iclass 40, count 0 2006.201.15:41:00.66#ibcon#end of sib2, iclass 40, count 0 2006.201.15:41:00.66#ibcon#*after write, iclass 40, count 0 2006.201.15:41:00.66#ibcon#*before return 0, iclass 40, count 0 2006.201.15:41:00.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:00.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:00.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:41:00.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:41:00.66$vck44/va=6,5 2006.201.15:41:00.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.15:41:00.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.15:41:00.66#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:00.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:00.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:00.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:00.71#ibcon#enter wrdev, iclass 4, count 2 2006.201.15:41:00.71#ibcon#first serial, iclass 4, count 2 2006.201.15:41:00.71#ibcon#enter sib2, iclass 4, count 2 2006.201.15:41:00.71#ibcon#flushed, iclass 4, count 2 2006.201.15:41:00.71#ibcon#about to write, iclass 4, count 2 2006.201.15:41:00.71#ibcon#wrote, iclass 4, count 2 2006.201.15:41:00.71#ibcon#about to read 3, iclass 4, count 2 2006.201.15:41:00.73#ibcon#read 3, iclass 4, count 2 2006.201.15:41:00.73#ibcon#about to read 4, iclass 4, count 2 2006.201.15:41:00.73#ibcon#read 4, iclass 4, count 2 2006.201.15:41:00.73#ibcon#about to read 5, iclass 4, count 2 2006.201.15:41:00.73#ibcon#read 5, iclass 4, count 2 2006.201.15:41:00.73#ibcon#about to read 6, iclass 4, count 2 2006.201.15:41:00.73#ibcon#read 6, iclass 4, count 2 2006.201.15:41:00.73#ibcon#end of sib2, iclass 4, count 2 2006.201.15:41:00.73#ibcon#*mode == 0, iclass 4, count 2 2006.201.15:41:00.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.15:41:00.73#ibcon#[25=AT06-05\r\n] 2006.201.15:41:00.73#ibcon#*before write, iclass 4, count 2 2006.201.15:41:00.73#ibcon#enter sib2, iclass 4, count 2 2006.201.15:41:00.73#ibcon#flushed, iclass 4, count 2 2006.201.15:41:00.73#ibcon#about to write, iclass 4, count 2 2006.201.15:41:00.73#ibcon#wrote, iclass 4, count 2 2006.201.15:41:00.73#ibcon#about to read 3, iclass 4, count 2 2006.201.15:41:00.76#ibcon#read 3, iclass 4, count 2 2006.201.15:41:00.76#ibcon#about to read 4, iclass 4, count 2 2006.201.15:41:00.76#ibcon#read 4, iclass 4, count 2 2006.201.15:41:00.76#ibcon#about to read 5, iclass 4, count 2 2006.201.15:41:00.76#ibcon#read 5, iclass 4, count 2 2006.201.15:41:00.76#ibcon#about to read 6, iclass 4, count 2 2006.201.15:41:00.76#ibcon#read 6, iclass 4, count 2 2006.201.15:41:00.76#ibcon#end of sib2, iclass 4, count 2 2006.201.15:41:00.76#ibcon#*after write, iclass 4, count 2 2006.201.15:41:00.76#ibcon#*before return 0, iclass 4, count 2 2006.201.15:41:00.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:00.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:00.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.15:41:00.76#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:00.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:00.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:00.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:00.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:41:00.88#ibcon#first serial, iclass 4, count 0 2006.201.15:41:00.88#ibcon#enter sib2, iclass 4, count 0 2006.201.15:41:00.88#ibcon#flushed, iclass 4, count 0 2006.201.15:41:00.88#ibcon#about to write, iclass 4, count 0 2006.201.15:41:00.88#ibcon#wrote, iclass 4, count 0 2006.201.15:41:00.88#ibcon#about to read 3, iclass 4, count 0 2006.201.15:41:00.90#ibcon#read 3, iclass 4, count 0 2006.201.15:41:00.90#ibcon#about to read 4, iclass 4, count 0 2006.201.15:41:00.90#ibcon#read 4, iclass 4, count 0 2006.201.15:41:00.90#ibcon#about to read 5, iclass 4, count 0 2006.201.15:41:00.90#ibcon#read 5, iclass 4, count 0 2006.201.15:41:00.90#ibcon#about to read 6, iclass 4, count 0 2006.201.15:41:00.90#ibcon#read 6, iclass 4, count 0 2006.201.15:41:00.90#ibcon#end of sib2, iclass 4, count 0 2006.201.15:41:00.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:41:00.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:41:00.90#ibcon#[25=USB\r\n] 2006.201.15:41:00.90#ibcon#*before write, iclass 4, count 0 2006.201.15:41:00.90#ibcon#enter sib2, iclass 4, count 0 2006.201.15:41:00.90#ibcon#flushed, iclass 4, count 0 2006.201.15:41:00.90#ibcon#about to write, iclass 4, count 0 2006.201.15:41:00.90#ibcon#wrote, iclass 4, count 0 2006.201.15:41:00.90#ibcon#about to read 3, iclass 4, count 0 2006.201.15:41:00.93#ibcon#read 3, iclass 4, count 0 2006.201.15:41:00.93#ibcon#about to read 4, iclass 4, count 0 2006.201.15:41:00.93#ibcon#read 4, iclass 4, count 0 2006.201.15:41:00.93#ibcon#about to read 5, iclass 4, count 0 2006.201.15:41:00.93#ibcon#read 5, iclass 4, count 0 2006.201.15:41:00.93#ibcon#about to read 6, iclass 4, count 0 2006.201.15:41:00.93#ibcon#read 6, iclass 4, count 0 2006.201.15:41:00.93#ibcon#end of sib2, iclass 4, count 0 2006.201.15:41:00.93#ibcon#*after write, iclass 4, count 0 2006.201.15:41:00.93#ibcon#*before return 0, iclass 4, count 0 2006.201.15:41:00.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:00.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:00.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:41:00.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:41:00.93$vck44/valo=7,864.99 2006.201.15:41:00.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.15:41:00.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.15:41:00.93#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:00.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:00.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:00.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:00.93#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:41:00.93#ibcon#first serial, iclass 6, count 0 2006.201.15:41:00.93#ibcon#enter sib2, iclass 6, count 0 2006.201.15:41:00.93#ibcon#flushed, iclass 6, count 0 2006.201.15:41:00.93#ibcon#about to write, iclass 6, count 0 2006.201.15:41:00.93#ibcon#wrote, iclass 6, count 0 2006.201.15:41:00.93#ibcon#about to read 3, iclass 6, count 0 2006.201.15:41:00.95#ibcon#read 3, iclass 6, count 0 2006.201.15:41:00.95#ibcon#about to read 4, iclass 6, count 0 2006.201.15:41:00.95#ibcon#read 4, iclass 6, count 0 2006.201.15:41:00.95#ibcon#about to read 5, iclass 6, count 0 2006.201.15:41:00.95#ibcon#read 5, iclass 6, count 0 2006.201.15:41:00.95#ibcon#about to read 6, iclass 6, count 0 2006.201.15:41:00.95#ibcon#read 6, iclass 6, count 0 2006.201.15:41:00.95#ibcon#end of sib2, iclass 6, count 0 2006.201.15:41:00.95#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:41:00.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:41:00.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:41:00.95#ibcon#*before write, iclass 6, count 0 2006.201.15:41:00.95#ibcon#enter sib2, iclass 6, count 0 2006.201.15:41:00.95#ibcon#flushed, iclass 6, count 0 2006.201.15:41:00.95#ibcon#about to write, iclass 6, count 0 2006.201.15:41:00.95#ibcon#wrote, iclass 6, count 0 2006.201.15:41:00.95#ibcon#about to read 3, iclass 6, count 0 2006.201.15:41:00.99#ibcon#read 3, iclass 6, count 0 2006.201.15:41:00.99#ibcon#about to read 4, iclass 6, count 0 2006.201.15:41:00.99#ibcon#read 4, iclass 6, count 0 2006.201.15:41:00.99#ibcon#about to read 5, iclass 6, count 0 2006.201.15:41:00.99#ibcon#read 5, iclass 6, count 0 2006.201.15:41:00.99#ibcon#about to read 6, iclass 6, count 0 2006.201.15:41:00.99#ibcon#read 6, iclass 6, count 0 2006.201.15:41:00.99#ibcon#end of sib2, iclass 6, count 0 2006.201.15:41:00.99#ibcon#*after write, iclass 6, count 0 2006.201.15:41:00.99#ibcon#*before return 0, iclass 6, count 0 2006.201.15:41:00.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:00.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:00.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:41:00.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:41:00.99$vck44/va=7,5 2006.201.15:41:00.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.15:41:00.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.15:41:00.99#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:00.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:41:01.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:41:01.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:41:01.05#ibcon#enter wrdev, iclass 10, count 2 2006.201.15:41:01.05#ibcon#first serial, iclass 10, count 2 2006.201.15:41:01.05#ibcon#enter sib2, iclass 10, count 2 2006.201.15:41:01.05#ibcon#flushed, iclass 10, count 2 2006.201.15:41:01.05#ibcon#about to write, iclass 10, count 2 2006.201.15:41:01.05#ibcon#wrote, iclass 10, count 2 2006.201.15:41:01.05#ibcon#about to read 3, iclass 10, count 2 2006.201.15:41:01.07#ibcon#read 3, iclass 10, count 2 2006.201.15:41:01.07#ibcon#about to read 4, iclass 10, count 2 2006.201.15:41:01.07#ibcon#read 4, iclass 10, count 2 2006.201.15:41:01.07#ibcon#about to read 5, iclass 10, count 2 2006.201.15:41:01.07#ibcon#read 5, iclass 10, count 2 2006.201.15:41:01.07#ibcon#about to read 6, iclass 10, count 2 2006.201.15:41:01.07#ibcon#read 6, iclass 10, count 2 2006.201.15:41:01.07#ibcon#end of sib2, iclass 10, count 2 2006.201.15:41:01.07#ibcon#*mode == 0, iclass 10, count 2 2006.201.15:41:01.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.15:41:01.07#ibcon#[25=AT07-05\r\n] 2006.201.15:41:01.07#ibcon#*before write, iclass 10, count 2 2006.201.15:41:01.07#ibcon#enter sib2, iclass 10, count 2 2006.201.15:41:01.07#ibcon#flushed, iclass 10, count 2 2006.201.15:41:01.07#ibcon#about to write, iclass 10, count 2 2006.201.15:41:01.07#ibcon#wrote, iclass 10, count 2 2006.201.15:41:01.07#ibcon#about to read 3, iclass 10, count 2 2006.201.15:41:01.10#ibcon#read 3, iclass 10, count 2 2006.201.15:41:01.10#ibcon#about to read 4, iclass 10, count 2 2006.201.15:41:01.10#ibcon#read 4, iclass 10, count 2 2006.201.15:41:01.10#ibcon#about to read 5, iclass 10, count 2 2006.201.15:41:01.10#ibcon#read 5, iclass 10, count 2 2006.201.15:41:01.10#ibcon#about to read 6, iclass 10, count 2 2006.201.15:41:01.10#ibcon#read 6, iclass 10, count 2 2006.201.15:41:01.10#ibcon#end of sib2, iclass 10, count 2 2006.201.15:41:01.10#ibcon#*after write, iclass 10, count 2 2006.201.15:41:01.10#ibcon#*before return 0, iclass 10, count 2 2006.201.15:41:01.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:41:01.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:41:01.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.15:41:01.10#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:01.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:41:01.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:41:01.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:41:01.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:41:01.22#ibcon#first serial, iclass 10, count 0 2006.201.15:41:01.22#ibcon#enter sib2, iclass 10, count 0 2006.201.15:41:01.22#ibcon#flushed, iclass 10, count 0 2006.201.15:41:01.22#ibcon#about to write, iclass 10, count 0 2006.201.15:41:01.22#ibcon#wrote, iclass 10, count 0 2006.201.15:41:01.22#ibcon#about to read 3, iclass 10, count 0 2006.201.15:41:01.24#ibcon#read 3, iclass 10, count 0 2006.201.15:41:01.24#ibcon#about to read 4, iclass 10, count 0 2006.201.15:41:01.24#ibcon#read 4, iclass 10, count 0 2006.201.15:41:01.24#ibcon#about to read 5, iclass 10, count 0 2006.201.15:41:01.24#ibcon#read 5, iclass 10, count 0 2006.201.15:41:01.24#ibcon#about to read 6, iclass 10, count 0 2006.201.15:41:01.24#ibcon#read 6, iclass 10, count 0 2006.201.15:41:01.24#ibcon#end of sib2, iclass 10, count 0 2006.201.15:41:01.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:41:01.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:41:01.24#ibcon#[25=USB\r\n] 2006.201.15:41:01.24#ibcon#*before write, iclass 10, count 0 2006.201.15:41:01.24#ibcon#enter sib2, iclass 10, count 0 2006.201.15:41:01.24#ibcon#flushed, iclass 10, count 0 2006.201.15:41:01.24#ibcon#about to write, iclass 10, count 0 2006.201.15:41:01.24#ibcon#wrote, iclass 10, count 0 2006.201.15:41:01.24#ibcon#about to read 3, iclass 10, count 0 2006.201.15:41:01.27#ibcon#read 3, iclass 10, count 0 2006.201.15:41:01.27#ibcon#about to read 4, iclass 10, count 0 2006.201.15:41:01.27#ibcon#read 4, iclass 10, count 0 2006.201.15:41:01.27#ibcon#about to read 5, iclass 10, count 0 2006.201.15:41:01.27#ibcon#read 5, iclass 10, count 0 2006.201.15:41:01.27#ibcon#about to read 6, iclass 10, count 0 2006.201.15:41:01.27#ibcon#read 6, iclass 10, count 0 2006.201.15:41:01.27#ibcon#end of sib2, iclass 10, count 0 2006.201.15:41:01.27#ibcon#*after write, iclass 10, count 0 2006.201.15:41:01.27#ibcon#*before return 0, iclass 10, count 0 2006.201.15:41:01.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:41:01.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:41:01.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:41:01.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:41:01.27$vck44/valo=8,884.99 2006.201.15:41:01.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.15:41:01.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.15:41:01.27#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:01.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:41:01.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:41:01.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:41:01.27#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:41:01.27#ibcon#first serial, iclass 12, count 0 2006.201.15:41:01.27#ibcon#enter sib2, iclass 12, count 0 2006.201.15:41:01.27#ibcon#flushed, iclass 12, count 0 2006.201.15:41:01.27#ibcon#about to write, iclass 12, count 0 2006.201.15:41:01.27#ibcon#wrote, iclass 12, count 0 2006.201.15:41:01.27#ibcon#about to read 3, iclass 12, count 0 2006.201.15:41:01.29#ibcon#read 3, iclass 12, count 0 2006.201.15:41:01.29#ibcon#about to read 4, iclass 12, count 0 2006.201.15:41:01.29#ibcon#read 4, iclass 12, count 0 2006.201.15:41:01.29#ibcon#about to read 5, iclass 12, count 0 2006.201.15:41:01.29#ibcon#read 5, iclass 12, count 0 2006.201.15:41:01.29#ibcon#about to read 6, iclass 12, count 0 2006.201.15:41:01.29#ibcon#read 6, iclass 12, count 0 2006.201.15:41:01.29#ibcon#end of sib2, iclass 12, count 0 2006.201.15:41:01.29#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:41:01.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:41:01.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:41:01.29#ibcon#*before write, iclass 12, count 0 2006.201.15:41:01.29#ibcon#enter sib2, iclass 12, count 0 2006.201.15:41:01.29#ibcon#flushed, iclass 12, count 0 2006.201.15:41:01.29#ibcon#about to write, iclass 12, count 0 2006.201.15:41:01.29#ibcon#wrote, iclass 12, count 0 2006.201.15:41:01.29#ibcon#about to read 3, iclass 12, count 0 2006.201.15:41:01.33#ibcon#read 3, iclass 12, count 0 2006.201.15:41:01.33#ibcon#about to read 4, iclass 12, count 0 2006.201.15:41:01.33#ibcon#read 4, iclass 12, count 0 2006.201.15:41:01.33#ibcon#about to read 5, iclass 12, count 0 2006.201.15:41:01.33#ibcon#read 5, iclass 12, count 0 2006.201.15:41:01.33#ibcon#about to read 6, iclass 12, count 0 2006.201.15:41:01.33#ibcon#read 6, iclass 12, count 0 2006.201.15:41:01.33#ibcon#end of sib2, iclass 12, count 0 2006.201.15:41:01.33#ibcon#*after write, iclass 12, count 0 2006.201.15:41:01.33#ibcon#*before return 0, iclass 12, count 0 2006.201.15:41:01.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:41:01.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:41:01.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:41:01.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:41:01.33$vck44/va=8,4 2006.201.15:41:01.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.15:41:01.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.15:41:01.33#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:01.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:41:01.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:41:01.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:41:01.39#ibcon#enter wrdev, iclass 14, count 2 2006.201.15:41:01.39#ibcon#first serial, iclass 14, count 2 2006.201.15:41:01.39#ibcon#enter sib2, iclass 14, count 2 2006.201.15:41:01.39#ibcon#flushed, iclass 14, count 2 2006.201.15:41:01.39#ibcon#about to write, iclass 14, count 2 2006.201.15:41:01.39#ibcon#wrote, iclass 14, count 2 2006.201.15:41:01.39#ibcon#about to read 3, iclass 14, count 2 2006.201.15:41:01.41#ibcon#read 3, iclass 14, count 2 2006.201.15:41:01.41#ibcon#about to read 4, iclass 14, count 2 2006.201.15:41:01.41#ibcon#read 4, iclass 14, count 2 2006.201.15:41:01.41#ibcon#about to read 5, iclass 14, count 2 2006.201.15:41:01.41#ibcon#read 5, iclass 14, count 2 2006.201.15:41:01.41#ibcon#about to read 6, iclass 14, count 2 2006.201.15:41:01.41#ibcon#read 6, iclass 14, count 2 2006.201.15:41:01.41#ibcon#end of sib2, iclass 14, count 2 2006.201.15:41:01.41#ibcon#*mode == 0, iclass 14, count 2 2006.201.15:41:01.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.15:41:01.41#ibcon#[25=AT08-04\r\n] 2006.201.15:41:01.41#ibcon#*before write, iclass 14, count 2 2006.201.15:41:01.41#ibcon#enter sib2, iclass 14, count 2 2006.201.15:41:01.41#ibcon#flushed, iclass 14, count 2 2006.201.15:41:01.41#ibcon#about to write, iclass 14, count 2 2006.201.15:41:01.41#ibcon#wrote, iclass 14, count 2 2006.201.15:41:01.41#ibcon#about to read 3, iclass 14, count 2 2006.201.15:41:01.44#ibcon#read 3, iclass 14, count 2 2006.201.15:41:01.44#ibcon#about to read 4, iclass 14, count 2 2006.201.15:41:01.44#ibcon#read 4, iclass 14, count 2 2006.201.15:41:01.44#ibcon#about to read 5, iclass 14, count 2 2006.201.15:41:01.44#ibcon#read 5, iclass 14, count 2 2006.201.15:41:01.44#ibcon#about to read 6, iclass 14, count 2 2006.201.15:41:01.44#ibcon#read 6, iclass 14, count 2 2006.201.15:41:01.44#ibcon#end of sib2, iclass 14, count 2 2006.201.15:41:01.44#ibcon#*after write, iclass 14, count 2 2006.201.15:41:01.44#ibcon#*before return 0, iclass 14, count 2 2006.201.15:41:01.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:41:01.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:41:01.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.15:41:01.44#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:01.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:41:01.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:41:01.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:41:01.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:41:01.56#ibcon#first serial, iclass 14, count 0 2006.201.15:41:01.56#ibcon#enter sib2, iclass 14, count 0 2006.201.15:41:01.56#ibcon#flushed, iclass 14, count 0 2006.201.15:41:01.56#ibcon#about to write, iclass 14, count 0 2006.201.15:41:01.56#ibcon#wrote, iclass 14, count 0 2006.201.15:41:01.56#ibcon#about to read 3, iclass 14, count 0 2006.201.15:41:01.58#ibcon#read 3, iclass 14, count 0 2006.201.15:41:01.58#ibcon#about to read 4, iclass 14, count 0 2006.201.15:41:01.58#ibcon#read 4, iclass 14, count 0 2006.201.15:41:01.58#ibcon#about to read 5, iclass 14, count 0 2006.201.15:41:01.58#ibcon#read 5, iclass 14, count 0 2006.201.15:41:01.58#ibcon#about to read 6, iclass 14, count 0 2006.201.15:41:01.58#ibcon#read 6, iclass 14, count 0 2006.201.15:41:01.58#ibcon#end of sib2, iclass 14, count 0 2006.201.15:41:01.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:41:01.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:41:01.58#ibcon#[25=USB\r\n] 2006.201.15:41:01.58#ibcon#*before write, iclass 14, count 0 2006.201.15:41:01.58#ibcon#enter sib2, iclass 14, count 0 2006.201.15:41:01.58#ibcon#flushed, iclass 14, count 0 2006.201.15:41:01.58#ibcon#about to write, iclass 14, count 0 2006.201.15:41:01.58#ibcon#wrote, iclass 14, count 0 2006.201.15:41:01.58#ibcon#about to read 3, iclass 14, count 0 2006.201.15:41:01.61#ibcon#read 3, iclass 14, count 0 2006.201.15:41:01.61#ibcon#about to read 4, iclass 14, count 0 2006.201.15:41:01.61#ibcon#read 4, iclass 14, count 0 2006.201.15:41:01.61#ibcon#about to read 5, iclass 14, count 0 2006.201.15:41:01.61#ibcon#read 5, iclass 14, count 0 2006.201.15:41:01.61#ibcon#about to read 6, iclass 14, count 0 2006.201.15:41:01.61#ibcon#read 6, iclass 14, count 0 2006.201.15:41:01.61#ibcon#end of sib2, iclass 14, count 0 2006.201.15:41:01.61#ibcon#*after write, iclass 14, count 0 2006.201.15:41:01.61#ibcon#*before return 0, iclass 14, count 0 2006.201.15:41:01.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:41:01.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:41:01.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:41:01.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:41:01.61$vck44/vblo=1,629.99 2006.201.15:41:01.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.15:41:01.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.15:41:01.61#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:01.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:01.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:01.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:01.61#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:41:01.61#ibcon#first serial, iclass 16, count 0 2006.201.15:41:01.61#ibcon#enter sib2, iclass 16, count 0 2006.201.15:41:01.61#ibcon#flushed, iclass 16, count 0 2006.201.15:41:01.61#ibcon#about to write, iclass 16, count 0 2006.201.15:41:01.61#ibcon#wrote, iclass 16, count 0 2006.201.15:41:01.61#ibcon#about to read 3, iclass 16, count 0 2006.201.15:41:01.63#ibcon#read 3, iclass 16, count 0 2006.201.15:41:01.63#ibcon#about to read 4, iclass 16, count 0 2006.201.15:41:01.63#ibcon#read 4, iclass 16, count 0 2006.201.15:41:01.63#ibcon#about to read 5, iclass 16, count 0 2006.201.15:41:01.63#ibcon#read 5, iclass 16, count 0 2006.201.15:41:01.63#ibcon#about to read 6, iclass 16, count 0 2006.201.15:41:01.63#ibcon#read 6, iclass 16, count 0 2006.201.15:41:01.63#ibcon#end of sib2, iclass 16, count 0 2006.201.15:41:01.63#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:41:01.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:41:01.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:41:01.63#ibcon#*before write, iclass 16, count 0 2006.201.15:41:01.63#ibcon#enter sib2, iclass 16, count 0 2006.201.15:41:01.63#ibcon#flushed, iclass 16, count 0 2006.201.15:41:01.63#ibcon#about to write, iclass 16, count 0 2006.201.15:41:01.63#ibcon#wrote, iclass 16, count 0 2006.201.15:41:01.63#ibcon#about to read 3, iclass 16, count 0 2006.201.15:41:01.68#ibcon#read 3, iclass 16, count 0 2006.201.15:41:01.68#ibcon#about to read 4, iclass 16, count 0 2006.201.15:41:01.68#ibcon#read 4, iclass 16, count 0 2006.201.15:41:01.68#ibcon#about to read 5, iclass 16, count 0 2006.201.15:41:01.68#ibcon#read 5, iclass 16, count 0 2006.201.15:41:01.68#ibcon#about to read 6, iclass 16, count 0 2006.201.15:41:01.68#ibcon#read 6, iclass 16, count 0 2006.201.15:41:01.68#ibcon#end of sib2, iclass 16, count 0 2006.201.15:41:01.68#ibcon#*after write, iclass 16, count 0 2006.201.15:41:01.68#ibcon#*before return 0, iclass 16, count 0 2006.201.15:41:01.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:01.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:01.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:41:01.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:41:01.68$vck44/vb=1,4 2006.201.15:41:01.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.15:41:01.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.15:41:01.68#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:01.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:41:01.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:41:01.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:41:01.68#ibcon#enter wrdev, iclass 18, count 2 2006.201.15:41:01.68#ibcon#first serial, iclass 18, count 2 2006.201.15:41:01.68#ibcon#enter sib2, iclass 18, count 2 2006.201.15:41:01.68#ibcon#flushed, iclass 18, count 2 2006.201.15:41:01.68#ibcon#about to write, iclass 18, count 2 2006.201.15:41:01.68#ibcon#wrote, iclass 18, count 2 2006.201.15:41:01.68#ibcon#about to read 3, iclass 18, count 2 2006.201.15:41:01.70#ibcon#read 3, iclass 18, count 2 2006.201.15:41:01.70#ibcon#about to read 4, iclass 18, count 2 2006.201.15:41:01.70#ibcon#read 4, iclass 18, count 2 2006.201.15:41:01.70#ibcon#about to read 5, iclass 18, count 2 2006.201.15:41:01.70#ibcon#read 5, iclass 18, count 2 2006.201.15:41:01.70#ibcon#about to read 6, iclass 18, count 2 2006.201.15:41:01.70#ibcon#read 6, iclass 18, count 2 2006.201.15:41:01.70#ibcon#end of sib2, iclass 18, count 2 2006.201.15:41:01.70#ibcon#*mode == 0, iclass 18, count 2 2006.201.15:41:01.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.15:41:01.70#ibcon#[27=AT01-04\r\n] 2006.201.15:41:01.70#ibcon#*before write, iclass 18, count 2 2006.201.15:41:01.70#ibcon#enter sib2, iclass 18, count 2 2006.201.15:41:01.70#ibcon#flushed, iclass 18, count 2 2006.201.15:41:01.70#ibcon#about to write, iclass 18, count 2 2006.201.15:41:01.70#ibcon#wrote, iclass 18, count 2 2006.201.15:41:01.70#ibcon#about to read 3, iclass 18, count 2 2006.201.15:41:01.73#ibcon#read 3, iclass 18, count 2 2006.201.15:41:01.73#ibcon#about to read 4, iclass 18, count 2 2006.201.15:41:01.73#ibcon#read 4, iclass 18, count 2 2006.201.15:41:01.73#ibcon#about to read 5, iclass 18, count 2 2006.201.15:41:01.73#ibcon#read 5, iclass 18, count 2 2006.201.15:41:01.73#ibcon#about to read 6, iclass 18, count 2 2006.201.15:41:01.73#ibcon#read 6, iclass 18, count 2 2006.201.15:41:01.73#ibcon#end of sib2, iclass 18, count 2 2006.201.15:41:01.73#ibcon#*after write, iclass 18, count 2 2006.201.15:41:01.73#ibcon#*before return 0, iclass 18, count 2 2006.201.15:41:01.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:41:01.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:41:01.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.15:41:01.73#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:01.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:41:01.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:41:01.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:41:01.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:41:01.85#ibcon#first serial, iclass 18, count 0 2006.201.15:41:01.85#ibcon#enter sib2, iclass 18, count 0 2006.201.15:41:01.85#ibcon#flushed, iclass 18, count 0 2006.201.15:41:01.85#ibcon#about to write, iclass 18, count 0 2006.201.15:41:01.85#ibcon#wrote, iclass 18, count 0 2006.201.15:41:01.85#ibcon#about to read 3, iclass 18, count 0 2006.201.15:41:01.87#ibcon#read 3, iclass 18, count 0 2006.201.15:41:01.87#ibcon#about to read 4, iclass 18, count 0 2006.201.15:41:01.87#ibcon#read 4, iclass 18, count 0 2006.201.15:41:01.87#ibcon#about to read 5, iclass 18, count 0 2006.201.15:41:01.87#ibcon#read 5, iclass 18, count 0 2006.201.15:41:01.87#ibcon#about to read 6, iclass 18, count 0 2006.201.15:41:01.87#ibcon#read 6, iclass 18, count 0 2006.201.15:41:01.87#ibcon#end of sib2, iclass 18, count 0 2006.201.15:41:01.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:41:01.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:41:01.87#ibcon#[27=USB\r\n] 2006.201.15:41:01.87#ibcon#*before write, iclass 18, count 0 2006.201.15:41:01.87#ibcon#enter sib2, iclass 18, count 0 2006.201.15:41:01.87#ibcon#flushed, iclass 18, count 0 2006.201.15:41:01.87#ibcon#about to write, iclass 18, count 0 2006.201.15:41:01.87#ibcon#wrote, iclass 18, count 0 2006.201.15:41:01.87#ibcon#about to read 3, iclass 18, count 0 2006.201.15:41:01.90#ibcon#read 3, iclass 18, count 0 2006.201.15:41:01.90#ibcon#about to read 4, iclass 18, count 0 2006.201.15:41:01.90#ibcon#read 4, iclass 18, count 0 2006.201.15:41:01.90#ibcon#about to read 5, iclass 18, count 0 2006.201.15:41:01.90#ibcon#read 5, iclass 18, count 0 2006.201.15:41:01.90#ibcon#about to read 6, iclass 18, count 0 2006.201.15:41:01.90#ibcon#read 6, iclass 18, count 0 2006.201.15:41:01.90#ibcon#end of sib2, iclass 18, count 0 2006.201.15:41:01.90#ibcon#*after write, iclass 18, count 0 2006.201.15:41:01.90#ibcon#*before return 0, iclass 18, count 0 2006.201.15:41:01.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:41:01.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:41:01.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:41:01.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:41:01.90$vck44/vblo=2,634.99 2006.201.15:41:01.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.15:41:01.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.15:41:01.90#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:01.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:41:01.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:41:01.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:41:01.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:41:01.90#ibcon#first serial, iclass 20, count 0 2006.201.15:41:01.90#ibcon#enter sib2, iclass 20, count 0 2006.201.15:41:01.90#ibcon#flushed, iclass 20, count 0 2006.201.15:41:01.90#ibcon#about to write, iclass 20, count 0 2006.201.15:41:01.90#ibcon#wrote, iclass 20, count 0 2006.201.15:41:01.90#ibcon#about to read 3, iclass 20, count 0 2006.201.15:41:01.92#ibcon#read 3, iclass 20, count 0 2006.201.15:41:01.92#ibcon#about to read 4, iclass 20, count 0 2006.201.15:41:01.92#ibcon#read 4, iclass 20, count 0 2006.201.15:41:01.92#ibcon#about to read 5, iclass 20, count 0 2006.201.15:41:01.92#ibcon#read 5, iclass 20, count 0 2006.201.15:41:01.92#ibcon#about to read 6, iclass 20, count 0 2006.201.15:41:01.92#ibcon#read 6, iclass 20, count 0 2006.201.15:41:01.92#ibcon#end of sib2, iclass 20, count 0 2006.201.15:41:01.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:41:01.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:41:01.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:41:01.92#ibcon#*before write, iclass 20, count 0 2006.201.15:41:01.92#ibcon#enter sib2, iclass 20, count 0 2006.201.15:41:01.92#ibcon#flushed, iclass 20, count 0 2006.201.15:41:01.92#ibcon#about to write, iclass 20, count 0 2006.201.15:41:01.92#ibcon#wrote, iclass 20, count 0 2006.201.15:41:01.92#ibcon#about to read 3, iclass 20, count 0 2006.201.15:41:01.96#ibcon#read 3, iclass 20, count 0 2006.201.15:41:01.96#ibcon#about to read 4, iclass 20, count 0 2006.201.15:41:01.96#ibcon#read 4, iclass 20, count 0 2006.201.15:41:01.96#ibcon#about to read 5, iclass 20, count 0 2006.201.15:41:01.96#ibcon#read 5, iclass 20, count 0 2006.201.15:41:01.96#ibcon#about to read 6, iclass 20, count 0 2006.201.15:41:01.96#ibcon#read 6, iclass 20, count 0 2006.201.15:41:01.96#ibcon#end of sib2, iclass 20, count 0 2006.201.15:41:01.96#ibcon#*after write, iclass 20, count 0 2006.201.15:41:01.96#ibcon#*before return 0, iclass 20, count 0 2006.201.15:41:01.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:41:01.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:41:01.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:41:01.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:41:01.96$vck44/vb=2,5 2006.201.15:41:01.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.15:41:01.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.15:41:01.96#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:01.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:41:02.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:41:02.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:41:02.02#ibcon#enter wrdev, iclass 22, count 2 2006.201.15:41:02.02#ibcon#first serial, iclass 22, count 2 2006.201.15:41:02.02#ibcon#enter sib2, iclass 22, count 2 2006.201.15:41:02.02#ibcon#flushed, iclass 22, count 2 2006.201.15:41:02.02#ibcon#about to write, iclass 22, count 2 2006.201.15:41:02.02#ibcon#wrote, iclass 22, count 2 2006.201.15:41:02.02#ibcon#about to read 3, iclass 22, count 2 2006.201.15:41:02.04#ibcon#read 3, iclass 22, count 2 2006.201.15:41:02.04#ibcon#about to read 4, iclass 22, count 2 2006.201.15:41:02.04#ibcon#read 4, iclass 22, count 2 2006.201.15:41:02.04#ibcon#about to read 5, iclass 22, count 2 2006.201.15:41:02.04#ibcon#read 5, iclass 22, count 2 2006.201.15:41:02.04#ibcon#about to read 6, iclass 22, count 2 2006.201.15:41:02.04#ibcon#read 6, iclass 22, count 2 2006.201.15:41:02.04#ibcon#end of sib2, iclass 22, count 2 2006.201.15:41:02.04#ibcon#*mode == 0, iclass 22, count 2 2006.201.15:41:02.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.15:41:02.04#ibcon#[27=AT02-05\r\n] 2006.201.15:41:02.04#ibcon#*before write, iclass 22, count 2 2006.201.15:41:02.04#ibcon#enter sib2, iclass 22, count 2 2006.201.15:41:02.04#ibcon#flushed, iclass 22, count 2 2006.201.15:41:02.04#ibcon#about to write, iclass 22, count 2 2006.201.15:41:02.04#ibcon#wrote, iclass 22, count 2 2006.201.15:41:02.04#ibcon#about to read 3, iclass 22, count 2 2006.201.15:41:02.07#ibcon#read 3, iclass 22, count 2 2006.201.15:41:02.07#ibcon#about to read 4, iclass 22, count 2 2006.201.15:41:02.07#ibcon#read 4, iclass 22, count 2 2006.201.15:41:02.07#ibcon#about to read 5, iclass 22, count 2 2006.201.15:41:02.07#ibcon#read 5, iclass 22, count 2 2006.201.15:41:02.07#ibcon#about to read 6, iclass 22, count 2 2006.201.15:41:02.07#ibcon#read 6, iclass 22, count 2 2006.201.15:41:02.07#ibcon#end of sib2, iclass 22, count 2 2006.201.15:41:02.07#ibcon#*after write, iclass 22, count 2 2006.201.15:41:02.07#ibcon#*before return 0, iclass 22, count 2 2006.201.15:41:02.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:41:02.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:41:02.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.15:41:02.07#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:02.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:41:02.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:41:02.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:41:02.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:41:02.19#ibcon#first serial, iclass 22, count 0 2006.201.15:41:02.19#ibcon#enter sib2, iclass 22, count 0 2006.201.15:41:02.19#ibcon#flushed, iclass 22, count 0 2006.201.15:41:02.19#ibcon#about to write, iclass 22, count 0 2006.201.15:41:02.19#ibcon#wrote, iclass 22, count 0 2006.201.15:41:02.19#ibcon#about to read 3, iclass 22, count 0 2006.201.15:41:02.22#ibcon#read 3, iclass 22, count 0 2006.201.15:41:02.22#ibcon#about to read 4, iclass 22, count 0 2006.201.15:41:02.22#ibcon#read 4, iclass 22, count 0 2006.201.15:41:02.22#ibcon#about to read 5, iclass 22, count 0 2006.201.15:41:02.22#ibcon#read 5, iclass 22, count 0 2006.201.15:41:02.22#ibcon#about to read 6, iclass 22, count 0 2006.201.15:41:02.22#ibcon#read 6, iclass 22, count 0 2006.201.15:41:02.22#ibcon#end of sib2, iclass 22, count 0 2006.201.15:41:02.22#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:41:02.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:41:02.22#ibcon#[27=USB\r\n] 2006.201.15:41:02.22#ibcon#*before write, iclass 22, count 0 2006.201.15:41:02.22#ibcon#enter sib2, iclass 22, count 0 2006.201.15:41:02.22#ibcon#flushed, iclass 22, count 0 2006.201.15:41:02.22#ibcon#about to write, iclass 22, count 0 2006.201.15:41:02.22#ibcon#wrote, iclass 22, count 0 2006.201.15:41:02.22#ibcon#about to read 3, iclass 22, count 0 2006.201.15:41:02.25#ibcon#read 3, iclass 22, count 0 2006.201.15:41:02.25#ibcon#about to read 4, iclass 22, count 0 2006.201.15:41:02.25#ibcon#read 4, iclass 22, count 0 2006.201.15:41:02.25#ibcon#about to read 5, iclass 22, count 0 2006.201.15:41:02.25#ibcon#read 5, iclass 22, count 0 2006.201.15:41:02.25#ibcon#about to read 6, iclass 22, count 0 2006.201.15:41:02.25#ibcon#read 6, iclass 22, count 0 2006.201.15:41:02.25#ibcon#end of sib2, iclass 22, count 0 2006.201.15:41:02.25#ibcon#*after write, iclass 22, count 0 2006.201.15:41:02.25#ibcon#*before return 0, iclass 22, count 0 2006.201.15:41:02.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:41:02.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:41:02.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:41:02.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:41:02.25$vck44/vblo=3,649.99 2006.201.15:41:02.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.15:41:02.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.15:41:02.25#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:02.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:41:02.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:41:02.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:41:02.25#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:41:02.25#ibcon#first serial, iclass 24, count 0 2006.201.15:41:02.25#ibcon#enter sib2, iclass 24, count 0 2006.201.15:41:02.25#ibcon#flushed, iclass 24, count 0 2006.201.15:41:02.25#ibcon#about to write, iclass 24, count 0 2006.201.15:41:02.25#ibcon#wrote, iclass 24, count 0 2006.201.15:41:02.25#ibcon#about to read 3, iclass 24, count 0 2006.201.15:41:02.27#ibcon#read 3, iclass 24, count 0 2006.201.15:41:02.27#ibcon#about to read 4, iclass 24, count 0 2006.201.15:41:02.27#ibcon#read 4, iclass 24, count 0 2006.201.15:41:02.27#ibcon#about to read 5, iclass 24, count 0 2006.201.15:41:02.27#ibcon#read 5, iclass 24, count 0 2006.201.15:41:02.27#ibcon#about to read 6, iclass 24, count 0 2006.201.15:41:02.27#ibcon#read 6, iclass 24, count 0 2006.201.15:41:02.27#ibcon#end of sib2, iclass 24, count 0 2006.201.15:41:02.27#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:41:02.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:41:02.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:41:02.27#ibcon#*before write, iclass 24, count 0 2006.201.15:41:02.27#ibcon#enter sib2, iclass 24, count 0 2006.201.15:41:02.27#ibcon#flushed, iclass 24, count 0 2006.201.15:41:02.27#ibcon#about to write, iclass 24, count 0 2006.201.15:41:02.27#ibcon#wrote, iclass 24, count 0 2006.201.15:41:02.27#ibcon#about to read 3, iclass 24, count 0 2006.201.15:41:02.31#ibcon#read 3, iclass 24, count 0 2006.201.15:41:02.31#ibcon#about to read 4, iclass 24, count 0 2006.201.15:41:02.31#ibcon#read 4, iclass 24, count 0 2006.201.15:41:02.31#ibcon#about to read 5, iclass 24, count 0 2006.201.15:41:02.31#ibcon#read 5, iclass 24, count 0 2006.201.15:41:02.31#ibcon#about to read 6, iclass 24, count 0 2006.201.15:41:02.31#ibcon#read 6, iclass 24, count 0 2006.201.15:41:02.31#ibcon#end of sib2, iclass 24, count 0 2006.201.15:41:02.31#ibcon#*after write, iclass 24, count 0 2006.201.15:41:02.31#ibcon#*before return 0, iclass 24, count 0 2006.201.15:41:02.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:41:02.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:41:02.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:41:02.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:41:02.31$vck44/vb=3,4 2006.201.15:41:02.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.15:41:02.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.15:41:02.31#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:02.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:41:02.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:41:02.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:41:02.37#ibcon#enter wrdev, iclass 26, count 2 2006.201.15:41:02.37#ibcon#first serial, iclass 26, count 2 2006.201.15:41:02.37#ibcon#enter sib2, iclass 26, count 2 2006.201.15:41:02.37#ibcon#flushed, iclass 26, count 2 2006.201.15:41:02.37#ibcon#about to write, iclass 26, count 2 2006.201.15:41:02.37#ibcon#wrote, iclass 26, count 2 2006.201.15:41:02.37#ibcon#about to read 3, iclass 26, count 2 2006.201.15:41:02.39#ibcon#read 3, iclass 26, count 2 2006.201.15:41:02.39#ibcon#about to read 4, iclass 26, count 2 2006.201.15:41:02.39#ibcon#read 4, iclass 26, count 2 2006.201.15:41:02.39#ibcon#about to read 5, iclass 26, count 2 2006.201.15:41:02.39#ibcon#read 5, iclass 26, count 2 2006.201.15:41:02.39#ibcon#about to read 6, iclass 26, count 2 2006.201.15:41:02.39#ibcon#read 6, iclass 26, count 2 2006.201.15:41:02.39#ibcon#end of sib2, iclass 26, count 2 2006.201.15:41:02.39#ibcon#*mode == 0, iclass 26, count 2 2006.201.15:41:02.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.15:41:02.39#ibcon#[27=AT03-04\r\n] 2006.201.15:41:02.39#ibcon#*before write, iclass 26, count 2 2006.201.15:41:02.39#ibcon#enter sib2, iclass 26, count 2 2006.201.15:41:02.39#ibcon#flushed, iclass 26, count 2 2006.201.15:41:02.39#ibcon#about to write, iclass 26, count 2 2006.201.15:41:02.39#ibcon#wrote, iclass 26, count 2 2006.201.15:41:02.39#ibcon#about to read 3, iclass 26, count 2 2006.201.15:41:02.42#ibcon#read 3, iclass 26, count 2 2006.201.15:41:02.42#ibcon#about to read 4, iclass 26, count 2 2006.201.15:41:02.42#ibcon#read 4, iclass 26, count 2 2006.201.15:41:02.42#ibcon#about to read 5, iclass 26, count 2 2006.201.15:41:02.42#ibcon#read 5, iclass 26, count 2 2006.201.15:41:02.42#ibcon#about to read 6, iclass 26, count 2 2006.201.15:41:02.42#ibcon#read 6, iclass 26, count 2 2006.201.15:41:02.42#ibcon#end of sib2, iclass 26, count 2 2006.201.15:41:02.42#ibcon#*after write, iclass 26, count 2 2006.201.15:41:02.42#ibcon#*before return 0, iclass 26, count 2 2006.201.15:41:02.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:41:02.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:41:02.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.15:41:02.42#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:02.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:41:02.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:41:02.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:41:02.54#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:41:02.54#ibcon#first serial, iclass 26, count 0 2006.201.15:41:02.54#ibcon#enter sib2, iclass 26, count 0 2006.201.15:41:02.54#ibcon#flushed, iclass 26, count 0 2006.201.15:41:02.54#ibcon#about to write, iclass 26, count 0 2006.201.15:41:02.54#ibcon#wrote, iclass 26, count 0 2006.201.15:41:02.54#ibcon#about to read 3, iclass 26, count 0 2006.201.15:41:02.56#ibcon#read 3, iclass 26, count 0 2006.201.15:41:02.56#ibcon#about to read 4, iclass 26, count 0 2006.201.15:41:02.56#ibcon#read 4, iclass 26, count 0 2006.201.15:41:02.56#ibcon#about to read 5, iclass 26, count 0 2006.201.15:41:02.56#ibcon#read 5, iclass 26, count 0 2006.201.15:41:02.56#ibcon#about to read 6, iclass 26, count 0 2006.201.15:41:02.56#ibcon#read 6, iclass 26, count 0 2006.201.15:41:02.56#ibcon#end of sib2, iclass 26, count 0 2006.201.15:41:02.56#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:41:02.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:41:02.56#ibcon#[27=USB\r\n] 2006.201.15:41:02.56#ibcon#*before write, iclass 26, count 0 2006.201.15:41:02.56#ibcon#enter sib2, iclass 26, count 0 2006.201.15:41:02.56#ibcon#flushed, iclass 26, count 0 2006.201.15:41:02.56#ibcon#about to write, iclass 26, count 0 2006.201.15:41:02.56#ibcon#wrote, iclass 26, count 0 2006.201.15:41:02.56#ibcon#about to read 3, iclass 26, count 0 2006.201.15:41:02.59#ibcon#read 3, iclass 26, count 0 2006.201.15:41:02.59#ibcon#about to read 4, iclass 26, count 0 2006.201.15:41:02.59#ibcon#read 4, iclass 26, count 0 2006.201.15:41:02.59#ibcon#about to read 5, iclass 26, count 0 2006.201.15:41:02.59#ibcon#read 5, iclass 26, count 0 2006.201.15:41:02.59#ibcon#about to read 6, iclass 26, count 0 2006.201.15:41:02.59#ibcon#read 6, iclass 26, count 0 2006.201.15:41:02.59#ibcon#end of sib2, iclass 26, count 0 2006.201.15:41:02.59#ibcon#*after write, iclass 26, count 0 2006.201.15:41:02.59#ibcon#*before return 0, iclass 26, count 0 2006.201.15:41:02.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:41:02.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:41:02.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:41:02.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:41:02.59$vck44/vblo=4,679.99 2006.201.15:41:02.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.15:41:02.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.15:41:02.59#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:02.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:41:02.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:41:02.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:41:02.59#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:41:02.59#ibcon#first serial, iclass 28, count 0 2006.201.15:41:02.59#ibcon#enter sib2, iclass 28, count 0 2006.201.15:41:02.59#ibcon#flushed, iclass 28, count 0 2006.201.15:41:02.59#ibcon#about to write, iclass 28, count 0 2006.201.15:41:02.59#ibcon#wrote, iclass 28, count 0 2006.201.15:41:02.59#ibcon#about to read 3, iclass 28, count 0 2006.201.15:41:02.61#ibcon#read 3, iclass 28, count 0 2006.201.15:41:02.61#ibcon#about to read 4, iclass 28, count 0 2006.201.15:41:02.61#ibcon#read 4, iclass 28, count 0 2006.201.15:41:02.61#ibcon#about to read 5, iclass 28, count 0 2006.201.15:41:02.61#ibcon#read 5, iclass 28, count 0 2006.201.15:41:02.61#ibcon#about to read 6, iclass 28, count 0 2006.201.15:41:02.61#ibcon#read 6, iclass 28, count 0 2006.201.15:41:02.61#ibcon#end of sib2, iclass 28, count 0 2006.201.15:41:02.61#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:41:02.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:41:02.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:41:02.61#ibcon#*before write, iclass 28, count 0 2006.201.15:41:02.61#ibcon#enter sib2, iclass 28, count 0 2006.201.15:41:02.61#ibcon#flushed, iclass 28, count 0 2006.201.15:41:02.61#ibcon#about to write, iclass 28, count 0 2006.201.15:41:02.61#ibcon#wrote, iclass 28, count 0 2006.201.15:41:02.61#ibcon#about to read 3, iclass 28, count 0 2006.201.15:41:02.65#ibcon#read 3, iclass 28, count 0 2006.201.15:41:02.65#ibcon#about to read 4, iclass 28, count 0 2006.201.15:41:02.65#ibcon#read 4, iclass 28, count 0 2006.201.15:41:02.65#ibcon#about to read 5, iclass 28, count 0 2006.201.15:41:02.65#ibcon#read 5, iclass 28, count 0 2006.201.15:41:02.65#ibcon#about to read 6, iclass 28, count 0 2006.201.15:41:02.65#ibcon#read 6, iclass 28, count 0 2006.201.15:41:02.65#ibcon#end of sib2, iclass 28, count 0 2006.201.15:41:02.65#ibcon#*after write, iclass 28, count 0 2006.201.15:41:02.65#ibcon#*before return 0, iclass 28, count 0 2006.201.15:41:02.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:41:02.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:41:02.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:41:02.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:41:02.65$vck44/vb=4,5 2006.201.15:41:02.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.15:41:02.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.15:41:02.65#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:02.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:41:02.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:41:02.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:41:02.71#ibcon#enter wrdev, iclass 30, count 2 2006.201.15:41:02.71#ibcon#first serial, iclass 30, count 2 2006.201.15:41:02.71#ibcon#enter sib2, iclass 30, count 2 2006.201.15:41:02.71#ibcon#flushed, iclass 30, count 2 2006.201.15:41:02.71#ibcon#about to write, iclass 30, count 2 2006.201.15:41:02.71#ibcon#wrote, iclass 30, count 2 2006.201.15:41:02.71#ibcon#about to read 3, iclass 30, count 2 2006.201.15:41:02.73#ibcon#read 3, iclass 30, count 2 2006.201.15:41:02.73#ibcon#about to read 4, iclass 30, count 2 2006.201.15:41:02.73#ibcon#read 4, iclass 30, count 2 2006.201.15:41:02.73#ibcon#about to read 5, iclass 30, count 2 2006.201.15:41:02.73#ibcon#read 5, iclass 30, count 2 2006.201.15:41:02.73#ibcon#about to read 6, iclass 30, count 2 2006.201.15:41:02.73#ibcon#read 6, iclass 30, count 2 2006.201.15:41:02.73#ibcon#end of sib2, iclass 30, count 2 2006.201.15:41:02.73#ibcon#*mode == 0, iclass 30, count 2 2006.201.15:41:02.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.15:41:02.73#ibcon#[27=AT04-05\r\n] 2006.201.15:41:02.73#ibcon#*before write, iclass 30, count 2 2006.201.15:41:02.73#ibcon#enter sib2, iclass 30, count 2 2006.201.15:41:02.73#ibcon#flushed, iclass 30, count 2 2006.201.15:41:02.73#ibcon#about to write, iclass 30, count 2 2006.201.15:41:02.73#ibcon#wrote, iclass 30, count 2 2006.201.15:41:02.73#ibcon#about to read 3, iclass 30, count 2 2006.201.15:41:02.76#ibcon#read 3, iclass 30, count 2 2006.201.15:41:02.76#ibcon#about to read 4, iclass 30, count 2 2006.201.15:41:02.76#ibcon#read 4, iclass 30, count 2 2006.201.15:41:02.76#ibcon#about to read 5, iclass 30, count 2 2006.201.15:41:02.76#ibcon#read 5, iclass 30, count 2 2006.201.15:41:02.76#ibcon#about to read 6, iclass 30, count 2 2006.201.15:41:02.76#ibcon#read 6, iclass 30, count 2 2006.201.15:41:02.76#ibcon#end of sib2, iclass 30, count 2 2006.201.15:41:02.76#ibcon#*after write, iclass 30, count 2 2006.201.15:41:02.76#ibcon#*before return 0, iclass 30, count 2 2006.201.15:41:02.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:41:02.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:41:02.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.15:41:02.76#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:02.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:41:02.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:41:02.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:41:02.88#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:41:02.88#ibcon#first serial, iclass 30, count 0 2006.201.15:41:02.88#ibcon#enter sib2, iclass 30, count 0 2006.201.15:41:02.88#ibcon#flushed, iclass 30, count 0 2006.201.15:41:02.88#ibcon#about to write, iclass 30, count 0 2006.201.15:41:02.88#ibcon#wrote, iclass 30, count 0 2006.201.15:41:02.88#ibcon#about to read 3, iclass 30, count 0 2006.201.15:41:02.90#ibcon#read 3, iclass 30, count 0 2006.201.15:41:02.90#ibcon#about to read 4, iclass 30, count 0 2006.201.15:41:02.90#ibcon#read 4, iclass 30, count 0 2006.201.15:41:02.90#ibcon#about to read 5, iclass 30, count 0 2006.201.15:41:02.90#ibcon#read 5, iclass 30, count 0 2006.201.15:41:02.90#ibcon#about to read 6, iclass 30, count 0 2006.201.15:41:02.90#ibcon#read 6, iclass 30, count 0 2006.201.15:41:02.90#ibcon#end of sib2, iclass 30, count 0 2006.201.15:41:02.90#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:41:02.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:41:02.90#ibcon#[27=USB\r\n] 2006.201.15:41:02.90#ibcon#*before write, iclass 30, count 0 2006.201.15:41:02.90#ibcon#enter sib2, iclass 30, count 0 2006.201.15:41:02.90#ibcon#flushed, iclass 30, count 0 2006.201.15:41:02.90#ibcon#about to write, iclass 30, count 0 2006.201.15:41:02.90#ibcon#wrote, iclass 30, count 0 2006.201.15:41:02.90#ibcon#about to read 3, iclass 30, count 0 2006.201.15:41:02.93#ibcon#read 3, iclass 30, count 0 2006.201.15:41:02.93#ibcon#about to read 4, iclass 30, count 0 2006.201.15:41:02.93#ibcon#read 4, iclass 30, count 0 2006.201.15:41:02.93#ibcon#about to read 5, iclass 30, count 0 2006.201.15:41:02.93#ibcon#read 5, iclass 30, count 0 2006.201.15:41:02.93#ibcon#about to read 6, iclass 30, count 0 2006.201.15:41:02.93#ibcon#read 6, iclass 30, count 0 2006.201.15:41:02.93#ibcon#end of sib2, iclass 30, count 0 2006.201.15:41:02.93#ibcon#*after write, iclass 30, count 0 2006.201.15:41:02.93#ibcon#*before return 0, iclass 30, count 0 2006.201.15:41:02.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:41:02.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:41:02.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:41:02.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:41:02.93$vck44/vblo=5,709.99 2006.201.15:41:02.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.15:41:02.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.15:41:02.93#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:02.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:41:02.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:41:02.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:41:02.93#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:41:02.93#ibcon#first serial, iclass 32, count 0 2006.201.15:41:02.93#ibcon#enter sib2, iclass 32, count 0 2006.201.15:41:02.93#ibcon#flushed, iclass 32, count 0 2006.201.15:41:02.93#ibcon#about to write, iclass 32, count 0 2006.201.15:41:02.93#ibcon#wrote, iclass 32, count 0 2006.201.15:41:02.93#ibcon#about to read 3, iclass 32, count 0 2006.201.15:41:02.95#ibcon#read 3, iclass 32, count 0 2006.201.15:41:02.95#ibcon#about to read 4, iclass 32, count 0 2006.201.15:41:02.95#ibcon#read 4, iclass 32, count 0 2006.201.15:41:02.95#ibcon#about to read 5, iclass 32, count 0 2006.201.15:41:02.95#ibcon#read 5, iclass 32, count 0 2006.201.15:41:02.95#ibcon#about to read 6, iclass 32, count 0 2006.201.15:41:02.95#ibcon#read 6, iclass 32, count 0 2006.201.15:41:02.95#ibcon#end of sib2, iclass 32, count 0 2006.201.15:41:02.95#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:41:02.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:41:02.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:41:02.95#ibcon#*before write, iclass 32, count 0 2006.201.15:41:02.95#ibcon#enter sib2, iclass 32, count 0 2006.201.15:41:02.95#ibcon#flushed, iclass 32, count 0 2006.201.15:41:02.95#ibcon#about to write, iclass 32, count 0 2006.201.15:41:02.95#ibcon#wrote, iclass 32, count 0 2006.201.15:41:02.95#ibcon#about to read 3, iclass 32, count 0 2006.201.15:41:02.99#ibcon#read 3, iclass 32, count 0 2006.201.15:41:02.99#ibcon#about to read 4, iclass 32, count 0 2006.201.15:41:02.99#ibcon#read 4, iclass 32, count 0 2006.201.15:41:02.99#ibcon#about to read 5, iclass 32, count 0 2006.201.15:41:02.99#ibcon#read 5, iclass 32, count 0 2006.201.15:41:02.99#ibcon#about to read 6, iclass 32, count 0 2006.201.15:41:02.99#ibcon#read 6, iclass 32, count 0 2006.201.15:41:02.99#ibcon#end of sib2, iclass 32, count 0 2006.201.15:41:02.99#ibcon#*after write, iclass 32, count 0 2006.201.15:41:02.99#ibcon#*before return 0, iclass 32, count 0 2006.201.15:41:02.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:41:02.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:41:02.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:41:02.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:41:02.99$vck44/vb=5,4 2006.201.15:41:02.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.15:41:02.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.15:41:02.99#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:02.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:03.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:03.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:03.05#ibcon#enter wrdev, iclass 34, count 2 2006.201.15:41:03.05#ibcon#first serial, iclass 34, count 2 2006.201.15:41:03.05#ibcon#enter sib2, iclass 34, count 2 2006.201.15:41:03.05#ibcon#flushed, iclass 34, count 2 2006.201.15:41:03.05#ibcon#about to write, iclass 34, count 2 2006.201.15:41:03.05#ibcon#wrote, iclass 34, count 2 2006.201.15:41:03.05#ibcon#about to read 3, iclass 34, count 2 2006.201.15:41:03.07#ibcon#read 3, iclass 34, count 2 2006.201.15:41:03.07#ibcon#about to read 4, iclass 34, count 2 2006.201.15:41:03.07#ibcon#read 4, iclass 34, count 2 2006.201.15:41:03.07#ibcon#about to read 5, iclass 34, count 2 2006.201.15:41:03.07#ibcon#read 5, iclass 34, count 2 2006.201.15:41:03.07#ibcon#about to read 6, iclass 34, count 2 2006.201.15:41:03.07#ibcon#read 6, iclass 34, count 2 2006.201.15:41:03.07#ibcon#end of sib2, iclass 34, count 2 2006.201.15:41:03.07#ibcon#*mode == 0, iclass 34, count 2 2006.201.15:41:03.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.15:41:03.07#ibcon#[27=AT05-04\r\n] 2006.201.15:41:03.07#ibcon#*before write, iclass 34, count 2 2006.201.15:41:03.07#ibcon#enter sib2, iclass 34, count 2 2006.201.15:41:03.07#ibcon#flushed, iclass 34, count 2 2006.201.15:41:03.07#ibcon#about to write, iclass 34, count 2 2006.201.15:41:03.07#ibcon#wrote, iclass 34, count 2 2006.201.15:41:03.07#ibcon#about to read 3, iclass 34, count 2 2006.201.15:41:03.10#ibcon#read 3, iclass 34, count 2 2006.201.15:41:03.10#ibcon#about to read 4, iclass 34, count 2 2006.201.15:41:03.10#ibcon#read 4, iclass 34, count 2 2006.201.15:41:03.10#ibcon#about to read 5, iclass 34, count 2 2006.201.15:41:03.10#ibcon#read 5, iclass 34, count 2 2006.201.15:41:03.10#ibcon#about to read 6, iclass 34, count 2 2006.201.15:41:03.10#ibcon#read 6, iclass 34, count 2 2006.201.15:41:03.10#ibcon#end of sib2, iclass 34, count 2 2006.201.15:41:03.10#ibcon#*after write, iclass 34, count 2 2006.201.15:41:03.10#ibcon#*before return 0, iclass 34, count 2 2006.201.15:41:03.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:03.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:41:03.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.15:41:03.10#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:03.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:03.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:03.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:03.22#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:41:03.22#ibcon#first serial, iclass 34, count 0 2006.201.15:41:03.22#ibcon#enter sib2, iclass 34, count 0 2006.201.15:41:03.22#ibcon#flushed, iclass 34, count 0 2006.201.15:41:03.22#ibcon#about to write, iclass 34, count 0 2006.201.15:41:03.22#ibcon#wrote, iclass 34, count 0 2006.201.15:41:03.22#ibcon#about to read 3, iclass 34, count 0 2006.201.15:41:03.25#ibcon#read 3, iclass 34, count 0 2006.201.15:41:03.25#ibcon#about to read 4, iclass 34, count 0 2006.201.15:41:03.25#ibcon#read 4, iclass 34, count 0 2006.201.15:41:03.25#ibcon#about to read 5, iclass 34, count 0 2006.201.15:41:03.25#ibcon#read 5, iclass 34, count 0 2006.201.15:41:03.25#ibcon#about to read 6, iclass 34, count 0 2006.201.15:41:03.25#ibcon#read 6, iclass 34, count 0 2006.201.15:41:03.25#ibcon#end of sib2, iclass 34, count 0 2006.201.15:41:03.25#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:41:03.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:41:03.25#ibcon#[27=USB\r\n] 2006.201.15:41:03.25#ibcon#*before write, iclass 34, count 0 2006.201.15:41:03.25#ibcon#enter sib2, iclass 34, count 0 2006.201.15:41:03.25#ibcon#flushed, iclass 34, count 0 2006.201.15:41:03.25#ibcon#about to write, iclass 34, count 0 2006.201.15:41:03.25#ibcon#wrote, iclass 34, count 0 2006.201.15:41:03.25#ibcon#about to read 3, iclass 34, count 0 2006.201.15:41:03.28#ibcon#read 3, iclass 34, count 0 2006.201.15:41:03.28#ibcon#about to read 4, iclass 34, count 0 2006.201.15:41:03.28#ibcon#read 4, iclass 34, count 0 2006.201.15:41:03.28#ibcon#about to read 5, iclass 34, count 0 2006.201.15:41:03.28#ibcon#read 5, iclass 34, count 0 2006.201.15:41:03.28#ibcon#about to read 6, iclass 34, count 0 2006.201.15:41:03.28#ibcon#read 6, iclass 34, count 0 2006.201.15:41:03.28#ibcon#end of sib2, iclass 34, count 0 2006.201.15:41:03.28#ibcon#*after write, iclass 34, count 0 2006.201.15:41:03.28#ibcon#*before return 0, iclass 34, count 0 2006.201.15:41:03.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:03.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:41:03.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:41:03.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:41:03.28$vck44/vblo=6,719.99 2006.201.15:41:03.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.15:41:03.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.15:41:03.28#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:03.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:03.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:03.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:03.28#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:41:03.28#ibcon#first serial, iclass 36, count 0 2006.201.15:41:03.28#ibcon#enter sib2, iclass 36, count 0 2006.201.15:41:03.28#ibcon#flushed, iclass 36, count 0 2006.201.15:41:03.28#ibcon#about to write, iclass 36, count 0 2006.201.15:41:03.28#ibcon#wrote, iclass 36, count 0 2006.201.15:41:03.28#ibcon#about to read 3, iclass 36, count 0 2006.201.15:41:03.30#ibcon#read 3, iclass 36, count 0 2006.201.15:41:03.30#ibcon#about to read 4, iclass 36, count 0 2006.201.15:41:03.30#ibcon#read 4, iclass 36, count 0 2006.201.15:41:03.30#ibcon#about to read 5, iclass 36, count 0 2006.201.15:41:03.30#ibcon#read 5, iclass 36, count 0 2006.201.15:41:03.30#ibcon#about to read 6, iclass 36, count 0 2006.201.15:41:03.30#ibcon#read 6, iclass 36, count 0 2006.201.15:41:03.30#ibcon#end of sib2, iclass 36, count 0 2006.201.15:41:03.30#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:41:03.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:41:03.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:41:03.30#ibcon#*before write, iclass 36, count 0 2006.201.15:41:03.30#ibcon#enter sib2, iclass 36, count 0 2006.201.15:41:03.30#ibcon#flushed, iclass 36, count 0 2006.201.15:41:03.30#ibcon#about to write, iclass 36, count 0 2006.201.15:41:03.30#ibcon#wrote, iclass 36, count 0 2006.201.15:41:03.30#ibcon#about to read 3, iclass 36, count 0 2006.201.15:41:03.34#ibcon#read 3, iclass 36, count 0 2006.201.15:41:03.34#ibcon#about to read 4, iclass 36, count 0 2006.201.15:41:03.34#ibcon#read 4, iclass 36, count 0 2006.201.15:41:03.34#ibcon#about to read 5, iclass 36, count 0 2006.201.15:41:03.34#ibcon#read 5, iclass 36, count 0 2006.201.15:41:03.34#ibcon#about to read 6, iclass 36, count 0 2006.201.15:41:03.34#ibcon#read 6, iclass 36, count 0 2006.201.15:41:03.34#ibcon#end of sib2, iclass 36, count 0 2006.201.15:41:03.34#ibcon#*after write, iclass 36, count 0 2006.201.15:41:03.34#ibcon#*before return 0, iclass 36, count 0 2006.201.15:41:03.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:03.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:41:03.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:41:03.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:41:03.34$vck44/vb=6,4 2006.201.15:41:03.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.15:41:03.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.15:41:03.34#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:03.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:03.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:03.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:03.40#ibcon#enter wrdev, iclass 38, count 2 2006.201.15:41:03.40#ibcon#first serial, iclass 38, count 2 2006.201.15:41:03.40#ibcon#enter sib2, iclass 38, count 2 2006.201.15:41:03.40#ibcon#flushed, iclass 38, count 2 2006.201.15:41:03.40#ibcon#about to write, iclass 38, count 2 2006.201.15:41:03.40#ibcon#wrote, iclass 38, count 2 2006.201.15:41:03.40#ibcon#about to read 3, iclass 38, count 2 2006.201.15:41:03.42#ibcon#read 3, iclass 38, count 2 2006.201.15:41:03.42#ibcon#about to read 4, iclass 38, count 2 2006.201.15:41:03.42#ibcon#read 4, iclass 38, count 2 2006.201.15:41:03.42#ibcon#about to read 5, iclass 38, count 2 2006.201.15:41:03.42#ibcon#read 5, iclass 38, count 2 2006.201.15:41:03.42#ibcon#about to read 6, iclass 38, count 2 2006.201.15:41:03.42#ibcon#read 6, iclass 38, count 2 2006.201.15:41:03.42#ibcon#end of sib2, iclass 38, count 2 2006.201.15:41:03.42#ibcon#*mode == 0, iclass 38, count 2 2006.201.15:41:03.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.15:41:03.42#ibcon#[27=AT06-04\r\n] 2006.201.15:41:03.42#ibcon#*before write, iclass 38, count 2 2006.201.15:41:03.42#ibcon#enter sib2, iclass 38, count 2 2006.201.15:41:03.42#ibcon#flushed, iclass 38, count 2 2006.201.15:41:03.42#ibcon#about to write, iclass 38, count 2 2006.201.15:41:03.42#ibcon#wrote, iclass 38, count 2 2006.201.15:41:03.42#ibcon#about to read 3, iclass 38, count 2 2006.201.15:41:03.45#ibcon#read 3, iclass 38, count 2 2006.201.15:41:03.45#ibcon#about to read 4, iclass 38, count 2 2006.201.15:41:03.45#ibcon#read 4, iclass 38, count 2 2006.201.15:41:03.45#ibcon#about to read 5, iclass 38, count 2 2006.201.15:41:03.45#ibcon#read 5, iclass 38, count 2 2006.201.15:41:03.45#ibcon#about to read 6, iclass 38, count 2 2006.201.15:41:03.45#ibcon#read 6, iclass 38, count 2 2006.201.15:41:03.45#ibcon#end of sib2, iclass 38, count 2 2006.201.15:41:03.45#ibcon#*after write, iclass 38, count 2 2006.201.15:41:03.45#ibcon#*before return 0, iclass 38, count 2 2006.201.15:41:03.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:03.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:41:03.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.15:41:03.45#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:03.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:03.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:03.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:03.57#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:41:03.57#ibcon#first serial, iclass 38, count 0 2006.201.15:41:03.57#ibcon#enter sib2, iclass 38, count 0 2006.201.15:41:03.57#ibcon#flushed, iclass 38, count 0 2006.201.15:41:03.57#ibcon#about to write, iclass 38, count 0 2006.201.15:41:03.57#ibcon#wrote, iclass 38, count 0 2006.201.15:41:03.57#ibcon#about to read 3, iclass 38, count 0 2006.201.15:41:03.59#ibcon#read 3, iclass 38, count 0 2006.201.15:41:03.59#ibcon#about to read 4, iclass 38, count 0 2006.201.15:41:03.59#ibcon#read 4, iclass 38, count 0 2006.201.15:41:03.59#ibcon#about to read 5, iclass 38, count 0 2006.201.15:41:03.59#ibcon#read 5, iclass 38, count 0 2006.201.15:41:03.59#ibcon#about to read 6, iclass 38, count 0 2006.201.15:41:03.59#ibcon#read 6, iclass 38, count 0 2006.201.15:41:03.59#ibcon#end of sib2, iclass 38, count 0 2006.201.15:41:03.59#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:41:03.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:41:03.59#ibcon#[27=USB\r\n] 2006.201.15:41:03.59#ibcon#*before write, iclass 38, count 0 2006.201.15:41:03.59#ibcon#enter sib2, iclass 38, count 0 2006.201.15:41:03.59#ibcon#flushed, iclass 38, count 0 2006.201.15:41:03.59#ibcon#about to write, iclass 38, count 0 2006.201.15:41:03.59#ibcon#wrote, iclass 38, count 0 2006.201.15:41:03.59#ibcon#about to read 3, iclass 38, count 0 2006.201.15:41:03.62#ibcon#read 3, iclass 38, count 0 2006.201.15:41:03.62#ibcon#about to read 4, iclass 38, count 0 2006.201.15:41:03.62#ibcon#read 4, iclass 38, count 0 2006.201.15:41:03.62#ibcon#about to read 5, iclass 38, count 0 2006.201.15:41:03.62#ibcon#read 5, iclass 38, count 0 2006.201.15:41:03.62#ibcon#about to read 6, iclass 38, count 0 2006.201.15:41:03.62#ibcon#read 6, iclass 38, count 0 2006.201.15:41:03.62#ibcon#end of sib2, iclass 38, count 0 2006.201.15:41:03.62#ibcon#*after write, iclass 38, count 0 2006.201.15:41:03.62#ibcon#*before return 0, iclass 38, count 0 2006.201.15:41:03.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:03.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:41:03.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:41:03.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:41:03.62$vck44/vblo=7,734.99 2006.201.15:41:03.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.15:41:03.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.15:41:03.62#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:03.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:03.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:03.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:03.62#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:41:03.62#ibcon#first serial, iclass 40, count 0 2006.201.15:41:03.62#ibcon#enter sib2, iclass 40, count 0 2006.201.15:41:03.62#ibcon#flushed, iclass 40, count 0 2006.201.15:41:03.62#ibcon#about to write, iclass 40, count 0 2006.201.15:41:03.62#ibcon#wrote, iclass 40, count 0 2006.201.15:41:03.62#ibcon#about to read 3, iclass 40, count 0 2006.201.15:41:03.64#ibcon#read 3, iclass 40, count 0 2006.201.15:41:03.64#ibcon#about to read 4, iclass 40, count 0 2006.201.15:41:03.64#ibcon#read 4, iclass 40, count 0 2006.201.15:41:03.64#ibcon#about to read 5, iclass 40, count 0 2006.201.15:41:03.64#ibcon#read 5, iclass 40, count 0 2006.201.15:41:03.64#ibcon#about to read 6, iclass 40, count 0 2006.201.15:41:03.64#ibcon#read 6, iclass 40, count 0 2006.201.15:41:03.64#ibcon#end of sib2, iclass 40, count 0 2006.201.15:41:03.64#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:41:03.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:41:03.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:41:03.64#ibcon#*before write, iclass 40, count 0 2006.201.15:41:03.64#ibcon#enter sib2, iclass 40, count 0 2006.201.15:41:03.64#ibcon#flushed, iclass 40, count 0 2006.201.15:41:03.64#ibcon#about to write, iclass 40, count 0 2006.201.15:41:03.64#ibcon#wrote, iclass 40, count 0 2006.201.15:41:03.64#ibcon#about to read 3, iclass 40, count 0 2006.201.15:41:03.68#ibcon#read 3, iclass 40, count 0 2006.201.15:41:03.68#ibcon#about to read 4, iclass 40, count 0 2006.201.15:41:03.68#ibcon#read 4, iclass 40, count 0 2006.201.15:41:03.68#ibcon#about to read 5, iclass 40, count 0 2006.201.15:41:03.68#ibcon#read 5, iclass 40, count 0 2006.201.15:41:03.68#ibcon#about to read 6, iclass 40, count 0 2006.201.15:41:03.68#ibcon#read 6, iclass 40, count 0 2006.201.15:41:03.68#ibcon#end of sib2, iclass 40, count 0 2006.201.15:41:03.68#ibcon#*after write, iclass 40, count 0 2006.201.15:41:03.68#ibcon#*before return 0, iclass 40, count 0 2006.201.15:41:03.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:03.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:41:03.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:41:03.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:41:03.68$vck44/vb=7,4 2006.201.15:41:03.68#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.15:41:03.68#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.15:41:03.68#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:03.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:03.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:03.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:03.74#ibcon#enter wrdev, iclass 4, count 2 2006.201.15:41:03.74#ibcon#first serial, iclass 4, count 2 2006.201.15:41:03.74#ibcon#enter sib2, iclass 4, count 2 2006.201.15:41:03.74#ibcon#flushed, iclass 4, count 2 2006.201.15:41:03.74#ibcon#about to write, iclass 4, count 2 2006.201.15:41:03.74#ibcon#wrote, iclass 4, count 2 2006.201.15:41:03.74#ibcon#about to read 3, iclass 4, count 2 2006.201.15:41:03.76#ibcon#read 3, iclass 4, count 2 2006.201.15:41:03.76#ibcon#about to read 4, iclass 4, count 2 2006.201.15:41:03.76#ibcon#read 4, iclass 4, count 2 2006.201.15:41:03.76#ibcon#about to read 5, iclass 4, count 2 2006.201.15:41:03.76#ibcon#read 5, iclass 4, count 2 2006.201.15:41:03.76#ibcon#about to read 6, iclass 4, count 2 2006.201.15:41:03.76#ibcon#read 6, iclass 4, count 2 2006.201.15:41:03.76#ibcon#end of sib2, iclass 4, count 2 2006.201.15:41:03.76#ibcon#*mode == 0, iclass 4, count 2 2006.201.15:41:03.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.15:41:03.76#ibcon#[27=AT07-04\r\n] 2006.201.15:41:03.76#ibcon#*before write, iclass 4, count 2 2006.201.15:41:03.76#ibcon#enter sib2, iclass 4, count 2 2006.201.15:41:03.76#ibcon#flushed, iclass 4, count 2 2006.201.15:41:03.76#ibcon#about to write, iclass 4, count 2 2006.201.15:41:03.76#ibcon#wrote, iclass 4, count 2 2006.201.15:41:03.76#ibcon#about to read 3, iclass 4, count 2 2006.201.15:41:03.79#ibcon#read 3, iclass 4, count 2 2006.201.15:41:03.79#ibcon#about to read 4, iclass 4, count 2 2006.201.15:41:03.79#ibcon#read 4, iclass 4, count 2 2006.201.15:41:03.79#ibcon#about to read 5, iclass 4, count 2 2006.201.15:41:03.79#ibcon#read 5, iclass 4, count 2 2006.201.15:41:03.79#ibcon#about to read 6, iclass 4, count 2 2006.201.15:41:03.79#ibcon#read 6, iclass 4, count 2 2006.201.15:41:03.79#ibcon#end of sib2, iclass 4, count 2 2006.201.15:41:03.79#ibcon#*after write, iclass 4, count 2 2006.201.15:41:03.79#ibcon#*before return 0, iclass 4, count 2 2006.201.15:41:03.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:03.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:41:03.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.15:41:03.79#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:03.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:03.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:03.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:03.91#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:41:03.91#ibcon#first serial, iclass 4, count 0 2006.201.15:41:03.91#ibcon#enter sib2, iclass 4, count 0 2006.201.15:41:03.91#ibcon#flushed, iclass 4, count 0 2006.201.15:41:03.91#ibcon#about to write, iclass 4, count 0 2006.201.15:41:03.91#ibcon#wrote, iclass 4, count 0 2006.201.15:41:03.91#ibcon#about to read 3, iclass 4, count 0 2006.201.15:41:03.93#ibcon#read 3, iclass 4, count 0 2006.201.15:41:03.93#ibcon#about to read 4, iclass 4, count 0 2006.201.15:41:03.93#ibcon#read 4, iclass 4, count 0 2006.201.15:41:03.93#ibcon#about to read 5, iclass 4, count 0 2006.201.15:41:03.93#ibcon#read 5, iclass 4, count 0 2006.201.15:41:03.93#ibcon#about to read 6, iclass 4, count 0 2006.201.15:41:03.93#ibcon#read 6, iclass 4, count 0 2006.201.15:41:03.93#ibcon#end of sib2, iclass 4, count 0 2006.201.15:41:03.93#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:41:03.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:41:03.93#ibcon#[27=USB\r\n] 2006.201.15:41:03.93#ibcon#*before write, iclass 4, count 0 2006.201.15:41:03.93#ibcon#enter sib2, iclass 4, count 0 2006.201.15:41:03.93#ibcon#flushed, iclass 4, count 0 2006.201.15:41:03.93#ibcon#about to write, iclass 4, count 0 2006.201.15:41:03.93#ibcon#wrote, iclass 4, count 0 2006.201.15:41:03.93#ibcon#about to read 3, iclass 4, count 0 2006.201.15:41:03.96#ibcon#read 3, iclass 4, count 0 2006.201.15:41:03.96#ibcon#about to read 4, iclass 4, count 0 2006.201.15:41:03.96#ibcon#read 4, iclass 4, count 0 2006.201.15:41:03.96#ibcon#about to read 5, iclass 4, count 0 2006.201.15:41:03.96#ibcon#read 5, iclass 4, count 0 2006.201.15:41:03.96#ibcon#about to read 6, iclass 4, count 0 2006.201.15:41:03.96#ibcon#read 6, iclass 4, count 0 2006.201.15:41:03.96#ibcon#end of sib2, iclass 4, count 0 2006.201.15:41:03.96#ibcon#*after write, iclass 4, count 0 2006.201.15:41:03.96#ibcon#*before return 0, iclass 4, count 0 2006.201.15:41:03.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:03.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:41:03.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:41:03.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:41:03.96$vck44/vblo=8,744.99 2006.201.15:41:03.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.15:41:03.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.15:41:03.96#ibcon#ireg 17 cls_cnt 0 2006.201.15:41:03.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:03.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:03.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:03.96#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:41:03.96#ibcon#first serial, iclass 6, count 0 2006.201.15:41:03.96#ibcon#enter sib2, iclass 6, count 0 2006.201.15:41:03.96#ibcon#flushed, iclass 6, count 0 2006.201.15:41:03.96#ibcon#about to write, iclass 6, count 0 2006.201.15:41:03.96#ibcon#wrote, iclass 6, count 0 2006.201.15:41:03.96#ibcon#about to read 3, iclass 6, count 0 2006.201.15:41:03.98#ibcon#read 3, iclass 6, count 0 2006.201.15:41:03.98#ibcon#about to read 4, iclass 6, count 0 2006.201.15:41:03.98#ibcon#read 4, iclass 6, count 0 2006.201.15:41:03.98#ibcon#about to read 5, iclass 6, count 0 2006.201.15:41:03.98#ibcon#read 5, iclass 6, count 0 2006.201.15:41:03.98#ibcon#about to read 6, iclass 6, count 0 2006.201.15:41:03.98#ibcon#read 6, iclass 6, count 0 2006.201.15:41:03.98#ibcon#end of sib2, iclass 6, count 0 2006.201.15:41:03.98#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:41:03.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:41:03.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:41:03.98#ibcon#*before write, iclass 6, count 0 2006.201.15:41:03.98#ibcon#enter sib2, iclass 6, count 0 2006.201.15:41:03.98#ibcon#flushed, iclass 6, count 0 2006.201.15:41:03.98#ibcon#about to write, iclass 6, count 0 2006.201.15:41:03.98#ibcon#wrote, iclass 6, count 0 2006.201.15:41:03.98#ibcon#about to read 3, iclass 6, count 0 2006.201.15:41:04.03#ibcon#read 3, iclass 6, count 0 2006.201.15:41:04.03#ibcon#about to read 4, iclass 6, count 0 2006.201.15:41:04.03#ibcon#read 4, iclass 6, count 0 2006.201.15:41:04.03#ibcon#about to read 5, iclass 6, count 0 2006.201.15:41:04.03#ibcon#read 5, iclass 6, count 0 2006.201.15:41:04.03#ibcon#about to read 6, iclass 6, count 0 2006.201.15:41:04.03#ibcon#read 6, iclass 6, count 0 2006.201.15:41:04.03#ibcon#end of sib2, iclass 6, count 0 2006.201.15:41:04.03#ibcon#*after write, iclass 6, count 0 2006.201.15:41:04.03#ibcon#*before return 0, iclass 6, count 0 2006.201.15:41:04.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:04.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:41:04.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:41:04.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:41:04.03$vck44/vb=8,4 2006.201.15:41:04.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.15:41:04.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.15:41:04.03#ibcon#ireg 11 cls_cnt 2 2006.201.15:41:04.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:41:04.03#abcon#<5=/05 1.1 1.7 20.841001002.9\r\n> 2006.201.15:41:04.05#abcon#{5=INTERFACE CLEAR} 2006.201.15:41:04.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:41:04.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:41:04.08#ibcon#enter wrdev, iclass 11, count 2 2006.201.15:41:04.08#ibcon#first serial, iclass 11, count 2 2006.201.15:41:04.08#ibcon#enter sib2, iclass 11, count 2 2006.201.15:41:04.08#ibcon#flushed, iclass 11, count 2 2006.201.15:41:04.08#ibcon#about to write, iclass 11, count 2 2006.201.15:41:04.08#ibcon#wrote, iclass 11, count 2 2006.201.15:41:04.08#ibcon#about to read 3, iclass 11, count 2 2006.201.15:41:04.10#ibcon#read 3, iclass 11, count 2 2006.201.15:41:04.10#ibcon#about to read 4, iclass 11, count 2 2006.201.15:41:04.10#ibcon#read 4, iclass 11, count 2 2006.201.15:41:04.10#ibcon#about to read 5, iclass 11, count 2 2006.201.15:41:04.10#ibcon#read 5, iclass 11, count 2 2006.201.15:41:04.10#ibcon#about to read 6, iclass 11, count 2 2006.201.15:41:04.10#ibcon#read 6, iclass 11, count 2 2006.201.15:41:04.10#ibcon#end of sib2, iclass 11, count 2 2006.201.15:41:04.10#ibcon#*mode == 0, iclass 11, count 2 2006.201.15:41:04.10#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.15:41:04.10#ibcon#[27=AT08-04\r\n] 2006.201.15:41:04.10#ibcon#*before write, iclass 11, count 2 2006.201.15:41:04.10#ibcon#enter sib2, iclass 11, count 2 2006.201.15:41:04.10#ibcon#flushed, iclass 11, count 2 2006.201.15:41:04.10#ibcon#about to write, iclass 11, count 2 2006.201.15:41:04.10#ibcon#wrote, iclass 11, count 2 2006.201.15:41:04.10#ibcon#about to read 3, iclass 11, count 2 2006.201.15:41:04.11#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:41:04.13#ibcon#read 3, iclass 11, count 2 2006.201.15:41:04.13#ibcon#about to read 4, iclass 11, count 2 2006.201.15:41:04.13#ibcon#read 4, iclass 11, count 2 2006.201.15:41:04.13#ibcon#about to read 5, iclass 11, count 2 2006.201.15:41:04.13#ibcon#read 5, iclass 11, count 2 2006.201.15:41:04.13#ibcon#about to read 6, iclass 11, count 2 2006.201.15:41:04.13#ibcon#read 6, iclass 11, count 2 2006.201.15:41:04.13#ibcon#end of sib2, iclass 11, count 2 2006.201.15:41:04.13#ibcon#*after write, iclass 11, count 2 2006.201.15:41:04.13#ibcon#*before return 0, iclass 11, count 2 2006.201.15:41:04.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:41:04.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:41:04.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.15:41:04.13#ibcon#ireg 7 cls_cnt 0 2006.201.15:41:04.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:41:04.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:41:04.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:41:04.25#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:41:04.25#ibcon#first serial, iclass 11, count 0 2006.201.15:41:04.25#ibcon#enter sib2, iclass 11, count 0 2006.201.15:41:04.25#ibcon#flushed, iclass 11, count 0 2006.201.15:41:04.25#ibcon#about to write, iclass 11, count 0 2006.201.15:41:04.25#ibcon#wrote, iclass 11, count 0 2006.201.15:41:04.25#ibcon#about to read 3, iclass 11, count 0 2006.201.15:41:04.27#ibcon#read 3, iclass 11, count 0 2006.201.15:41:04.27#ibcon#about to read 4, iclass 11, count 0 2006.201.15:41:04.27#ibcon#read 4, iclass 11, count 0 2006.201.15:41:04.27#ibcon#about to read 5, iclass 11, count 0 2006.201.15:41:04.27#ibcon#read 5, iclass 11, count 0 2006.201.15:41:04.27#ibcon#about to read 6, iclass 11, count 0 2006.201.15:41:04.27#ibcon#read 6, iclass 11, count 0 2006.201.15:41:04.27#ibcon#end of sib2, iclass 11, count 0 2006.201.15:41:04.27#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:41:04.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:41:04.27#ibcon#[27=USB\r\n] 2006.201.15:41:04.27#ibcon#*before write, iclass 11, count 0 2006.201.15:41:04.27#ibcon#enter sib2, iclass 11, count 0 2006.201.15:41:04.27#ibcon#flushed, iclass 11, count 0 2006.201.15:41:04.27#ibcon#about to write, iclass 11, count 0 2006.201.15:41:04.27#ibcon#wrote, iclass 11, count 0 2006.201.15:41:04.27#ibcon#about to read 3, iclass 11, count 0 2006.201.15:41:04.30#ibcon#read 3, iclass 11, count 0 2006.201.15:41:04.30#ibcon#about to read 4, iclass 11, count 0 2006.201.15:41:04.30#ibcon#read 4, iclass 11, count 0 2006.201.15:41:04.30#ibcon#about to read 5, iclass 11, count 0 2006.201.15:41:04.30#ibcon#read 5, iclass 11, count 0 2006.201.15:41:04.30#ibcon#about to read 6, iclass 11, count 0 2006.201.15:41:04.30#ibcon#read 6, iclass 11, count 0 2006.201.15:41:04.30#ibcon#end of sib2, iclass 11, count 0 2006.201.15:41:04.30#ibcon#*after write, iclass 11, count 0 2006.201.15:41:04.30#ibcon#*before return 0, iclass 11, count 0 2006.201.15:41:04.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:41:04.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:41:04.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:41:04.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:41:04.30$vck44/vabw=wide 2006.201.15:41:04.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.15:41:04.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.15:41:04.30#ibcon#ireg 8 cls_cnt 0 2006.201.15:41:04.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:04.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:04.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:04.30#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:41:04.30#ibcon#first serial, iclass 16, count 0 2006.201.15:41:04.30#ibcon#enter sib2, iclass 16, count 0 2006.201.15:41:04.30#ibcon#flushed, iclass 16, count 0 2006.201.15:41:04.30#ibcon#about to write, iclass 16, count 0 2006.201.15:41:04.30#ibcon#wrote, iclass 16, count 0 2006.201.15:41:04.30#ibcon#about to read 3, iclass 16, count 0 2006.201.15:41:04.32#ibcon#read 3, iclass 16, count 0 2006.201.15:41:04.32#ibcon#about to read 4, iclass 16, count 0 2006.201.15:41:04.32#ibcon#read 4, iclass 16, count 0 2006.201.15:41:04.32#ibcon#about to read 5, iclass 16, count 0 2006.201.15:41:04.32#ibcon#read 5, iclass 16, count 0 2006.201.15:41:04.32#ibcon#about to read 6, iclass 16, count 0 2006.201.15:41:04.32#ibcon#read 6, iclass 16, count 0 2006.201.15:41:04.32#ibcon#end of sib2, iclass 16, count 0 2006.201.15:41:04.32#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:41:04.32#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:41:04.32#ibcon#[25=BW32\r\n] 2006.201.15:41:04.32#ibcon#*before write, iclass 16, count 0 2006.201.15:41:04.32#ibcon#enter sib2, iclass 16, count 0 2006.201.15:41:04.32#ibcon#flushed, iclass 16, count 0 2006.201.15:41:04.32#ibcon#about to write, iclass 16, count 0 2006.201.15:41:04.32#ibcon#wrote, iclass 16, count 0 2006.201.15:41:04.32#ibcon#about to read 3, iclass 16, count 0 2006.201.15:41:04.35#ibcon#read 3, iclass 16, count 0 2006.201.15:41:04.35#ibcon#about to read 4, iclass 16, count 0 2006.201.15:41:04.35#ibcon#read 4, iclass 16, count 0 2006.201.15:41:04.35#ibcon#about to read 5, iclass 16, count 0 2006.201.15:41:04.35#ibcon#read 5, iclass 16, count 0 2006.201.15:41:04.35#ibcon#about to read 6, iclass 16, count 0 2006.201.15:41:04.35#ibcon#read 6, iclass 16, count 0 2006.201.15:41:04.35#ibcon#end of sib2, iclass 16, count 0 2006.201.15:41:04.35#ibcon#*after write, iclass 16, count 0 2006.201.15:41:04.35#ibcon#*before return 0, iclass 16, count 0 2006.201.15:41:04.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:04.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:41:04.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:41:04.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:41:04.35$vck44/vbbw=wide 2006.201.15:41:04.35#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.15:41:04.35#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.15:41:04.35#ibcon#ireg 8 cls_cnt 0 2006.201.15:41:04.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:41:04.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:41:04.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:41:04.42#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:41:04.42#ibcon#first serial, iclass 18, count 0 2006.201.15:41:04.42#ibcon#enter sib2, iclass 18, count 0 2006.201.15:41:04.42#ibcon#flushed, iclass 18, count 0 2006.201.15:41:04.42#ibcon#about to write, iclass 18, count 0 2006.201.15:41:04.42#ibcon#wrote, iclass 18, count 0 2006.201.15:41:04.42#ibcon#about to read 3, iclass 18, count 0 2006.201.15:41:04.44#ibcon#read 3, iclass 18, count 0 2006.201.15:41:04.44#ibcon#about to read 4, iclass 18, count 0 2006.201.15:41:04.44#ibcon#read 4, iclass 18, count 0 2006.201.15:41:04.44#ibcon#about to read 5, iclass 18, count 0 2006.201.15:41:04.44#ibcon#read 5, iclass 18, count 0 2006.201.15:41:04.44#ibcon#about to read 6, iclass 18, count 0 2006.201.15:41:04.44#ibcon#read 6, iclass 18, count 0 2006.201.15:41:04.44#ibcon#end of sib2, iclass 18, count 0 2006.201.15:41:04.44#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:41:04.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:41:04.44#ibcon#[27=BW32\r\n] 2006.201.15:41:04.44#ibcon#*before write, iclass 18, count 0 2006.201.15:41:04.44#ibcon#enter sib2, iclass 18, count 0 2006.201.15:41:04.44#ibcon#flushed, iclass 18, count 0 2006.201.15:41:04.44#ibcon#about to write, iclass 18, count 0 2006.201.15:41:04.44#ibcon#wrote, iclass 18, count 0 2006.201.15:41:04.44#ibcon#about to read 3, iclass 18, count 0 2006.201.15:41:04.47#ibcon#read 3, iclass 18, count 0 2006.201.15:41:04.47#ibcon#about to read 4, iclass 18, count 0 2006.201.15:41:04.47#ibcon#read 4, iclass 18, count 0 2006.201.15:41:04.47#ibcon#about to read 5, iclass 18, count 0 2006.201.15:41:04.47#ibcon#read 5, iclass 18, count 0 2006.201.15:41:04.47#ibcon#about to read 6, iclass 18, count 0 2006.201.15:41:04.47#ibcon#read 6, iclass 18, count 0 2006.201.15:41:04.47#ibcon#end of sib2, iclass 18, count 0 2006.201.15:41:04.47#ibcon#*after write, iclass 18, count 0 2006.201.15:41:04.47#ibcon#*before return 0, iclass 18, count 0 2006.201.15:41:04.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:41:04.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:41:04.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:41:04.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:41:04.47$setupk4/ifdk4 2006.201.15:41:04.47$ifdk4/lo= 2006.201.15:41:04.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:41:04.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:41:04.47$ifdk4/patch= 2006.201.15:41:04.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:41:04.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:41:04.47$setupk4/!*+20s 2006.201.15:41:11.14#trakl#Source acquired 2006.201.15:41:12.14#flagr#flagr/antenna,acquired 2006.201.15:41:14.20#abcon#<5=/05 1.1 1.7 20.841001002.9\r\n> 2006.201.15:41:14.22#abcon#{5=INTERFACE CLEAR} 2006.201.15:41:14.28#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:41:18.90$setupk4/"tpicd 2006.201.15:41:18.90$setupk4/echo=off 2006.201.15:41:18.90$setupk4/xlog=off 2006.201.15:41:18.90:!2006.201.15:43:26 2006.201.15:43:26.00:preob 2006.201.15:43:26.14/onsource/TRACKING 2006.201.15:43:26.14:!2006.201.15:43:36 2006.201.15:43:36.00:"tape 2006.201.15:43:36.00:"st=record 2006.201.15:43:36.00:data_valid=on 2006.201.15:43:36.00:midob 2006.201.15:43:36.14/onsource/TRACKING 2006.201.15:43:36.14/wx/20.84,1002.9,100 2006.201.15:43:36.34/cable/+6.4776E-03 2006.201.15:43:37.43/va/01,08,usb,yes,28,30 2006.201.15:43:37.43/va/02,07,usb,yes,30,31 2006.201.15:43:37.43/va/03,08,usb,yes,27,28 2006.201.15:43:37.43/va/04,07,usb,yes,31,32 2006.201.15:43:37.43/va/05,04,usb,yes,27,28 2006.201.15:43:37.43/va/06,05,usb,yes,27,27 2006.201.15:43:37.43/va/07,05,usb,yes,26,28 2006.201.15:43:37.43/va/08,04,usb,yes,26,32 2006.201.15:43:37.66/valo/01,524.99,yes,locked 2006.201.15:43:37.66/valo/02,534.99,yes,locked 2006.201.15:43:37.66/valo/03,564.99,yes,locked 2006.201.15:43:37.66/valo/04,624.99,yes,locked 2006.201.15:43:37.66/valo/05,734.99,yes,locked 2006.201.15:43:37.66/valo/06,814.99,yes,locked 2006.201.15:43:37.66/valo/07,864.99,yes,locked 2006.201.15:43:37.66/valo/08,884.99,yes,locked 2006.201.15:43:38.75/vb/01,04,usb,yes,28,26 2006.201.15:43:38.75/vb/02,05,usb,yes,27,26 2006.201.15:43:38.75/vb/03,04,usb,yes,27,30 2006.201.15:43:38.75/vb/04,05,usb,yes,28,27 2006.201.15:43:38.75/vb/05,04,usb,yes,24,27 2006.201.15:43:38.75/vb/06,04,usb,yes,28,25 2006.201.15:43:38.75/vb/07,04,usb,yes,28,28 2006.201.15:43:38.75/vb/08,04,usb,yes,26,29 2006.201.15:43:38.98/vblo/01,629.99,yes,locked 2006.201.15:43:38.98/vblo/02,634.99,yes,locked 2006.201.15:43:38.98/vblo/03,649.99,yes,locked 2006.201.15:43:38.98/vblo/04,679.99,yes,locked 2006.201.15:43:38.98/vblo/05,709.99,yes,locked 2006.201.15:43:38.98/vblo/06,719.99,yes,locked 2006.201.15:43:38.98/vblo/07,734.99,yes,locked 2006.201.15:43:38.98/vblo/08,744.99,yes,locked 2006.201.15:43:39.13/vabw/8 2006.201.15:43:39.28/vbbw/8 2006.201.15:43:39.37/xfe/off,on,15.2 2006.201.15:43:39.82/ifatt/23,28,28,28 2006.201.15:43:40.07/fmout-gps/S +4.48E-07 2006.201.15:43:40.11:!2006.201.15:44:56 2006.201.15:44:56.00:data_valid=off 2006.201.15:44:56.00:"et 2006.201.15:44:56.00:!+3s 2006.201.15:44:59.02:"tape 2006.201.15:44:59.02:postob 2006.201.15:44:59.13/cable/+6.4771E-03 2006.201.15:44:59.13/wx/20.84,1002.9,100 2006.201.15:44:59.21/fmout-gps/S +4.48E-07 2006.201.15:44:59.21:scan_name=201-1548,jd0607,80 2006.201.15:44:59.21:source=1908-201,191109.65,-200655.1,2000.0,cw 2006.201.15:45:00.14#flagr#flagr/antenna,new-source 2006.201.15:45:00.14:checkk5 2006.201.15:45:00.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:45:00.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:45:01.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:45:01.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:45:02.01/chk_obsdata//k5ts1/T2011543??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.15:45:02.38/chk_obsdata//k5ts2/T2011543??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.15:45:02.74/chk_obsdata//k5ts3/T2011543??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.15:45:03.11/chk_obsdata//k5ts4/T2011543??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.15:45:03.80/k5log//k5ts1_log_newline 2006.201.15:45:04.49/k5log//k5ts2_log_newline 2006.201.15:45:05.17/k5log//k5ts3_log_newline 2006.201.15:45:05.86/k5log//k5ts4_log_newline 2006.201.15:45:05.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:45:05.88:setupk4=1 2006.201.15:45:05.89$setupk4/echo=on 2006.201.15:45:05.89$setupk4/pcalon 2006.201.15:45:05.89$pcalon/"no phase cal control is implemented here 2006.201.15:45:05.89$setupk4/"tpicd=stop 2006.201.15:45:05.89$setupk4/"rec=synch_on 2006.201.15:45:05.89$setupk4/"rec_mode=128 2006.201.15:45:05.89$setupk4/!* 2006.201.15:45:05.89$setupk4/recpk4 2006.201.15:45:05.89$recpk4/recpatch= 2006.201.15:45:05.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:45:05.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:45:05.89$setupk4/vck44 2006.201.15:45:05.89$vck44/valo=1,524.99 2006.201.15:45:05.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.15:45:05.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.15:45:05.89#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:05.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:05.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:05.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:05.89#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:45:05.89#ibcon#first serial, iclass 38, count 0 2006.201.15:45:05.89#ibcon#enter sib2, iclass 38, count 0 2006.201.15:45:05.89#ibcon#flushed, iclass 38, count 0 2006.201.15:45:05.89#ibcon#about to write, iclass 38, count 0 2006.201.15:45:05.89#ibcon#wrote, iclass 38, count 0 2006.201.15:45:05.89#ibcon#about to read 3, iclass 38, count 0 2006.201.15:45:05.93#ibcon#read 3, iclass 38, count 0 2006.201.15:45:05.93#ibcon#about to read 4, iclass 38, count 0 2006.201.15:45:05.93#ibcon#read 4, iclass 38, count 0 2006.201.15:45:05.93#ibcon#about to read 5, iclass 38, count 0 2006.201.15:45:05.93#ibcon#read 5, iclass 38, count 0 2006.201.15:45:05.93#ibcon#about to read 6, iclass 38, count 0 2006.201.15:45:05.93#ibcon#read 6, iclass 38, count 0 2006.201.15:45:05.93#ibcon#end of sib2, iclass 38, count 0 2006.201.15:45:05.93#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:45:05.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:45:05.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:45:05.93#ibcon#*before write, iclass 38, count 0 2006.201.15:45:05.93#ibcon#enter sib2, iclass 38, count 0 2006.201.15:45:05.93#ibcon#flushed, iclass 38, count 0 2006.201.15:45:05.93#ibcon#about to write, iclass 38, count 0 2006.201.15:45:05.93#ibcon#wrote, iclass 38, count 0 2006.201.15:45:05.93#ibcon#about to read 3, iclass 38, count 0 2006.201.15:45:05.98#ibcon#read 3, iclass 38, count 0 2006.201.15:45:05.98#ibcon#about to read 4, iclass 38, count 0 2006.201.15:45:05.98#ibcon#read 4, iclass 38, count 0 2006.201.15:45:05.98#ibcon#about to read 5, iclass 38, count 0 2006.201.15:45:05.98#ibcon#read 5, iclass 38, count 0 2006.201.15:45:05.98#ibcon#about to read 6, iclass 38, count 0 2006.201.15:45:05.98#ibcon#read 6, iclass 38, count 0 2006.201.15:45:05.98#ibcon#end of sib2, iclass 38, count 0 2006.201.15:45:05.98#ibcon#*after write, iclass 38, count 0 2006.201.15:45:05.98#ibcon#*before return 0, iclass 38, count 0 2006.201.15:45:05.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:05.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:05.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:45:05.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:45:05.98$vck44/va=1,8 2006.201.15:45:05.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.15:45:05.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.15:45:05.98#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:05.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:05.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:05.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:05.98#ibcon#enter wrdev, iclass 40, count 2 2006.201.15:45:05.98#ibcon#first serial, iclass 40, count 2 2006.201.15:45:05.98#ibcon#enter sib2, iclass 40, count 2 2006.201.15:45:05.98#ibcon#flushed, iclass 40, count 2 2006.201.15:45:05.98#ibcon#about to write, iclass 40, count 2 2006.201.15:45:05.98#ibcon#wrote, iclass 40, count 2 2006.201.15:45:05.98#ibcon#about to read 3, iclass 40, count 2 2006.201.15:45:06.00#ibcon#read 3, iclass 40, count 2 2006.201.15:45:06.00#ibcon#about to read 4, iclass 40, count 2 2006.201.15:45:06.00#ibcon#read 4, iclass 40, count 2 2006.201.15:45:06.00#ibcon#about to read 5, iclass 40, count 2 2006.201.15:45:06.00#ibcon#read 5, iclass 40, count 2 2006.201.15:45:06.00#ibcon#about to read 6, iclass 40, count 2 2006.201.15:45:06.00#ibcon#read 6, iclass 40, count 2 2006.201.15:45:06.00#ibcon#end of sib2, iclass 40, count 2 2006.201.15:45:06.00#ibcon#*mode == 0, iclass 40, count 2 2006.201.15:45:06.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.15:45:06.00#ibcon#[25=AT01-08\r\n] 2006.201.15:45:06.00#ibcon#*before write, iclass 40, count 2 2006.201.15:45:06.00#ibcon#enter sib2, iclass 40, count 2 2006.201.15:45:06.00#ibcon#flushed, iclass 40, count 2 2006.201.15:45:06.00#ibcon#about to write, iclass 40, count 2 2006.201.15:45:06.00#ibcon#wrote, iclass 40, count 2 2006.201.15:45:06.00#ibcon#about to read 3, iclass 40, count 2 2006.201.15:45:06.03#ibcon#read 3, iclass 40, count 2 2006.201.15:45:06.03#ibcon#about to read 4, iclass 40, count 2 2006.201.15:45:06.03#ibcon#read 4, iclass 40, count 2 2006.201.15:45:06.03#ibcon#about to read 5, iclass 40, count 2 2006.201.15:45:06.03#ibcon#read 5, iclass 40, count 2 2006.201.15:45:06.03#ibcon#about to read 6, iclass 40, count 2 2006.201.15:45:06.03#ibcon#read 6, iclass 40, count 2 2006.201.15:45:06.03#ibcon#end of sib2, iclass 40, count 2 2006.201.15:45:06.03#ibcon#*after write, iclass 40, count 2 2006.201.15:45:06.03#ibcon#*before return 0, iclass 40, count 2 2006.201.15:45:06.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:06.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:06.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.15:45:06.03#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:06.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:06.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:06.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:06.15#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:45:06.15#ibcon#first serial, iclass 40, count 0 2006.201.15:45:06.15#ibcon#enter sib2, iclass 40, count 0 2006.201.15:45:06.15#ibcon#flushed, iclass 40, count 0 2006.201.15:45:06.15#ibcon#about to write, iclass 40, count 0 2006.201.15:45:06.15#ibcon#wrote, iclass 40, count 0 2006.201.15:45:06.15#ibcon#about to read 3, iclass 40, count 0 2006.201.15:45:06.17#ibcon#read 3, iclass 40, count 0 2006.201.15:45:06.17#ibcon#about to read 4, iclass 40, count 0 2006.201.15:45:06.17#ibcon#read 4, iclass 40, count 0 2006.201.15:45:06.17#ibcon#about to read 5, iclass 40, count 0 2006.201.15:45:06.17#ibcon#read 5, iclass 40, count 0 2006.201.15:45:06.17#ibcon#about to read 6, iclass 40, count 0 2006.201.15:45:06.17#ibcon#read 6, iclass 40, count 0 2006.201.15:45:06.17#ibcon#end of sib2, iclass 40, count 0 2006.201.15:45:06.17#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:45:06.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:45:06.17#ibcon#[25=USB\r\n] 2006.201.15:45:06.17#ibcon#*before write, iclass 40, count 0 2006.201.15:45:06.17#ibcon#enter sib2, iclass 40, count 0 2006.201.15:45:06.17#ibcon#flushed, iclass 40, count 0 2006.201.15:45:06.17#ibcon#about to write, iclass 40, count 0 2006.201.15:45:06.17#ibcon#wrote, iclass 40, count 0 2006.201.15:45:06.17#ibcon#about to read 3, iclass 40, count 0 2006.201.15:45:06.20#ibcon#read 3, iclass 40, count 0 2006.201.15:45:06.20#ibcon#about to read 4, iclass 40, count 0 2006.201.15:45:06.20#ibcon#read 4, iclass 40, count 0 2006.201.15:45:06.20#ibcon#about to read 5, iclass 40, count 0 2006.201.15:45:06.20#ibcon#read 5, iclass 40, count 0 2006.201.15:45:06.20#ibcon#about to read 6, iclass 40, count 0 2006.201.15:45:06.20#ibcon#read 6, iclass 40, count 0 2006.201.15:45:06.20#ibcon#end of sib2, iclass 40, count 0 2006.201.15:45:06.20#ibcon#*after write, iclass 40, count 0 2006.201.15:45:06.20#ibcon#*before return 0, iclass 40, count 0 2006.201.15:45:06.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:06.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:06.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:45:06.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:45:06.20$vck44/valo=2,534.99 2006.201.15:45:06.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.15:45:06.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.15:45:06.20#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:06.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:06.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:06.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:06.20#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:45:06.20#ibcon#first serial, iclass 4, count 0 2006.201.15:45:06.20#ibcon#enter sib2, iclass 4, count 0 2006.201.15:45:06.20#ibcon#flushed, iclass 4, count 0 2006.201.15:45:06.20#ibcon#about to write, iclass 4, count 0 2006.201.15:45:06.20#ibcon#wrote, iclass 4, count 0 2006.201.15:45:06.20#ibcon#about to read 3, iclass 4, count 0 2006.201.15:45:06.22#ibcon#read 3, iclass 4, count 0 2006.201.15:45:06.22#ibcon#about to read 4, iclass 4, count 0 2006.201.15:45:06.22#ibcon#read 4, iclass 4, count 0 2006.201.15:45:06.22#ibcon#about to read 5, iclass 4, count 0 2006.201.15:45:06.22#ibcon#read 5, iclass 4, count 0 2006.201.15:45:06.22#ibcon#about to read 6, iclass 4, count 0 2006.201.15:45:06.22#ibcon#read 6, iclass 4, count 0 2006.201.15:45:06.22#ibcon#end of sib2, iclass 4, count 0 2006.201.15:45:06.22#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:45:06.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:45:06.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:45:06.22#ibcon#*before write, iclass 4, count 0 2006.201.15:45:06.22#ibcon#enter sib2, iclass 4, count 0 2006.201.15:45:06.22#ibcon#flushed, iclass 4, count 0 2006.201.15:45:06.22#ibcon#about to write, iclass 4, count 0 2006.201.15:45:06.22#ibcon#wrote, iclass 4, count 0 2006.201.15:45:06.22#ibcon#about to read 3, iclass 4, count 0 2006.201.15:45:06.26#ibcon#read 3, iclass 4, count 0 2006.201.15:45:06.26#ibcon#about to read 4, iclass 4, count 0 2006.201.15:45:06.26#ibcon#read 4, iclass 4, count 0 2006.201.15:45:06.26#ibcon#about to read 5, iclass 4, count 0 2006.201.15:45:06.26#ibcon#read 5, iclass 4, count 0 2006.201.15:45:06.26#ibcon#about to read 6, iclass 4, count 0 2006.201.15:45:06.26#ibcon#read 6, iclass 4, count 0 2006.201.15:45:06.26#ibcon#end of sib2, iclass 4, count 0 2006.201.15:45:06.26#ibcon#*after write, iclass 4, count 0 2006.201.15:45:06.26#ibcon#*before return 0, iclass 4, count 0 2006.201.15:45:06.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:06.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:06.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:45:06.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:45:06.26$vck44/va=2,7 2006.201.15:45:06.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.15:45:06.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.15:45:06.26#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:06.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:06.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:06.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:06.32#ibcon#enter wrdev, iclass 6, count 2 2006.201.15:45:06.32#ibcon#first serial, iclass 6, count 2 2006.201.15:45:06.32#ibcon#enter sib2, iclass 6, count 2 2006.201.15:45:06.32#ibcon#flushed, iclass 6, count 2 2006.201.15:45:06.32#ibcon#about to write, iclass 6, count 2 2006.201.15:45:06.32#ibcon#wrote, iclass 6, count 2 2006.201.15:45:06.32#ibcon#about to read 3, iclass 6, count 2 2006.201.15:45:06.34#ibcon#read 3, iclass 6, count 2 2006.201.15:45:06.34#ibcon#about to read 4, iclass 6, count 2 2006.201.15:45:06.34#ibcon#read 4, iclass 6, count 2 2006.201.15:45:06.34#ibcon#about to read 5, iclass 6, count 2 2006.201.15:45:06.34#ibcon#read 5, iclass 6, count 2 2006.201.15:45:06.34#ibcon#about to read 6, iclass 6, count 2 2006.201.15:45:06.34#ibcon#read 6, iclass 6, count 2 2006.201.15:45:06.34#ibcon#end of sib2, iclass 6, count 2 2006.201.15:45:06.34#ibcon#*mode == 0, iclass 6, count 2 2006.201.15:45:06.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.15:45:06.34#ibcon#[25=AT02-07\r\n] 2006.201.15:45:06.34#ibcon#*before write, iclass 6, count 2 2006.201.15:45:06.34#ibcon#enter sib2, iclass 6, count 2 2006.201.15:45:06.34#ibcon#flushed, iclass 6, count 2 2006.201.15:45:06.34#ibcon#about to write, iclass 6, count 2 2006.201.15:45:06.34#ibcon#wrote, iclass 6, count 2 2006.201.15:45:06.34#ibcon#about to read 3, iclass 6, count 2 2006.201.15:45:06.37#ibcon#read 3, iclass 6, count 2 2006.201.15:45:06.37#ibcon#about to read 4, iclass 6, count 2 2006.201.15:45:06.37#ibcon#read 4, iclass 6, count 2 2006.201.15:45:06.37#ibcon#about to read 5, iclass 6, count 2 2006.201.15:45:06.37#ibcon#read 5, iclass 6, count 2 2006.201.15:45:06.37#ibcon#about to read 6, iclass 6, count 2 2006.201.15:45:06.37#ibcon#read 6, iclass 6, count 2 2006.201.15:45:06.37#ibcon#end of sib2, iclass 6, count 2 2006.201.15:45:06.37#ibcon#*after write, iclass 6, count 2 2006.201.15:45:06.37#ibcon#*before return 0, iclass 6, count 2 2006.201.15:45:06.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:06.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:06.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.15:45:06.37#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:06.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:06.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:06.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:06.49#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:45:06.49#ibcon#first serial, iclass 6, count 0 2006.201.15:45:06.49#ibcon#enter sib2, iclass 6, count 0 2006.201.15:45:06.49#ibcon#flushed, iclass 6, count 0 2006.201.15:45:06.49#ibcon#about to write, iclass 6, count 0 2006.201.15:45:06.49#ibcon#wrote, iclass 6, count 0 2006.201.15:45:06.49#ibcon#about to read 3, iclass 6, count 0 2006.201.15:45:06.51#ibcon#read 3, iclass 6, count 0 2006.201.15:45:06.51#ibcon#about to read 4, iclass 6, count 0 2006.201.15:45:06.51#ibcon#read 4, iclass 6, count 0 2006.201.15:45:06.51#ibcon#about to read 5, iclass 6, count 0 2006.201.15:45:06.51#ibcon#read 5, iclass 6, count 0 2006.201.15:45:06.51#ibcon#about to read 6, iclass 6, count 0 2006.201.15:45:06.51#ibcon#read 6, iclass 6, count 0 2006.201.15:45:06.51#ibcon#end of sib2, iclass 6, count 0 2006.201.15:45:06.51#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:45:06.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:45:06.51#ibcon#[25=USB\r\n] 2006.201.15:45:06.51#ibcon#*before write, iclass 6, count 0 2006.201.15:45:06.51#ibcon#enter sib2, iclass 6, count 0 2006.201.15:45:06.51#ibcon#flushed, iclass 6, count 0 2006.201.15:45:06.51#ibcon#about to write, iclass 6, count 0 2006.201.15:45:06.51#ibcon#wrote, iclass 6, count 0 2006.201.15:45:06.51#ibcon#about to read 3, iclass 6, count 0 2006.201.15:45:06.54#ibcon#read 3, iclass 6, count 0 2006.201.15:45:06.54#ibcon#about to read 4, iclass 6, count 0 2006.201.15:45:06.54#ibcon#read 4, iclass 6, count 0 2006.201.15:45:06.54#ibcon#about to read 5, iclass 6, count 0 2006.201.15:45:06.54#ibcon#read 5, iclass 6, count 0 2006.201.15:45:06.54#ibcon#about to read 6, iclass 6, count 0 2006.201.15:45:06.54#ibcon#read 6, iclass 6, count 0 2006.201.15:45:06.54#ibcon#end of sib2, iclass 6, count 0 2006.201.15:45:06.54#ibcon#*after write, iclass 6, count 0 2006.201.15:45:06.54#ibcon#*before return 0, iclass 6, count 0 2006.201.15:45:06.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:06.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:06.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:45:06.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:45:06.54$vck44/valo=3,564.99 2006.201.15:45:06.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.15:45:06.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.15:45:06.54#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:06.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:06.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:06.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:06.54#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:45:06.54#ibcon#first serial, iclass 10, count 0 2006.201.15:45:06.54#ibcon#enter sib2, iclass 10, count 0 2006.201.15:45:06.54#ibcon#flushed, iclass 10, count 0 2006.201.15:45:06.54#ibcon#about to write, iclass 10, count 0 2006.201.15:45:06.54#ibcon#wrote, iclass 10, count 0 2006.201.15:45:06.54#ibcon#about to read 3, iclass 10, count 0 2006.201.15:45:06.56#ibcon#read 3, iclass 10, count 0 2006.201.15:45:06.56#ibcon#about to read 4, iclass 10, count 0 2006.201.15:45:06.56#ibcon#read 4, iclass 10, count 0 2006.201.15:45:06.56#ibcon#about to read 5, iclass 10, count 0 2006.201.15:45:06.56#ibcon#read 5, iclass 10, count 0 2006.201.15:45:06.56#ibcon#about to read 6, iclass 10, count 0 2006.201.15:45:06.56#ibcon#read 6, iclass 10, count 0 2006.201.15:45:06.56#ibcon#end of sib2, iclass 10, count 0 2006.201.15:45:06.56#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:45:06.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:45:06.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:45:06.56#ibcon#*before write, iclass 10, count 0 2006.201.15:45:06.56#ibcon#enter sib2, iclass 10, count 0 2006.201.15:45:06.56#ibcon#flushed, iclass 10, count 0 2006.201.15:45:06.56#ibcon#about to write, iclass 10, count 0 2006.201.15:45:06.56#ibcon#wrote, iclass 10, count 0 2006.201.15:45:06.56#ibcon#about to read 3, iclass 10, count 0 2006.201.15:45:06.61#ibcon#read 3, iclass 10, count 0 2006.201.15:45:06.61#ibcon#about to read 4, iclass 10, count 0 2006.201.15:45:06.61#ibcon#read 4, iclass 10, count 0 2006.201.15:45:06.61#ibcon#about to read 5, iclass 10, count 0 2006.201.15:45:06.61#ibcon#read 5, iclass 10, count 0 2006.201.15:45:06.61#ibcon#about to read 6, iclass 10, count 0 2006.201.15:45:06.61#ibcon#read 6, iclass 10, count 0 2006.201.15:45:06.61#ibcon#end of sib2, iclass 10, count 0 2006.201.15:45:06.61#ibcon#*after write, iclass 10, count 0 2006.201.15:45:06.61#ibcon#*before return 0, iclass 10, count 0 2006.201.15:45:06.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:06.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:06.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:45:06.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:45:06.61$vck44/va=3,8 2006.201.15:45:06.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.15:45:06.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.15:45:06.61#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:06.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:06.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:06.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:06.66#ibcon#enter wrdev, iclass 12, count 2 2006.201.15:45:06.66#ibcon#first serial, iclass 12, count 2 2006.201.15:45:06.66#ibcon#enter sib2, iclass 12, count 2 2006.201.15:45:06.66#ibcon#flushed, iclass 12, count 2 2006.201.15:45:06.66#ibcon#about to write, iclass 12, count 2 2006.201.15:45:06.66#ibcon#wrote, iclass 12, count 2 2006.201.15:45:06.66#ibcon#about to read 3, iclass 12, count 2 2006.201.15:45:06.68#ibcon#read 3, iclass 12, count 2 2006.201.15:45:06.68#ibcon#about to read 4, iclass 12, count 2 2006.201.15:45:06.68#ibcon#read 4, iclass 12, count 2 2006.201.15:45:06.68#ibcon#about to read 5, iclass 12, count 2 2006.201.15:45:06.68#ibcon#read 5, iclass 12, count 2 2006.201.15:45:06.68#ibcon#about to read 6, iclass 12, count 2 2006.201.15:45:06.68#ibcon#read 6, iclass 12, count 2 2006.201.15:45:06.68#ibcon#end of sib2, iclass 12, count 2 2006.201.15:45:06.68#ibcon#*mode == 0, iclass 12, count 2 2006.201.15:45:06.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.15:45:06.68#ibcon#[25=AT03-08\r\n] 2006.201.15:45:06.68#ibcon#*before write, iclass 12, count 2 2006.201.15:45:06.68#ibcon#enter sib2, iclass 12, count 2 2006.201.15:45:06.68#ibcon#flushed, iclass 12, count 2 2006.201.15:45:06.68#ibcon#about to write, iclass 12, count 2 2006.201.15:45:06.68#ibcon#wrote, iclass 12, count 2 2006.201.15:45:06.68#ibcon#about to read 3, iclass 12, count 2 2006.201.15:45:06.71#ibcon#read 3, iclass 12, count 2 2006.201.15:45:06.71#ibcon#about to read 4, iclass 12, count 2 2006.201.15:45:06.71#ibcon#read 4, iclass 12, count 2 2006.201.15:45:06.71#ibcon#about to read 5, iclass 12, count 2 2006.201.15:45:06.71#ibcon#read 5, iclass 12, count 2 2006.201.15:45:06.71#ibcon#about to read 6, iclass 12, count 2 2006.201.15:45:06.71#ibcon#read 6, iclass 12, count 2 2006.201.15:45:06.71#ibcon#end of sib2, iclass 12, count 2 2006.201.15:45:06.71#ibcon#*after write, iclass 12, count 2 2006.201.15:45:06.71#ibcon#*before return 0, iclass 12, count 2 2006.201.15:45:06.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:06.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:06.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.15:45:06.71#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:06.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:06.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:06.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:06.83#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:45:06.83#ibcon#first serial, iclass 12, count 0 2006.201.15:45:06.83#ibcon#enter sib2, iclass 12, count 0 2006.201.15:45:06.83#ibcon#flushed, iclass 12, count 0 2006.201.15:45:06.83#ibcon#about to write, iclass 12, count 0 2006.201.15:45:06.83#ibcon#wrote, iclass 12, count 0 2006.201.15:45:06.83#ibcon#about to read 3, iclass 12, count 0 2006.201.15:45:06.85#ibcon#read 3, iclass 12, count 0 2006.201.15:45:06.85#ibcon#about to read 4, iclass 12, count 0 2006.201.15:45:06.85#ibcon#read 4, iclass 12, count 0 2006.201.15:45:06.85#ibcon#about to read 5, iclass 12, count 0 2006.201.15:45:06.85#ibcon#read 5, iclass 12, count 0 2006.201.15:45:06.85#ibcon#about to read 6, iclass 12, count 0 2006.201.15:45:06.85#ibcon#read 6, iclass 12, count 0 2006.201.15:45:06.85#ibcon#end of sib2, iclass 12, count 0 2006.201.15:45:06.85#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:45:06.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:45:06.85#ibcon#[25=USB\r\n] 2006.201.15:45:06.85#ibcon#*before write, iclass 12, count 0 2006.201.15:45:06.85#ibcon#enter sib2, iclass 12, count 0 2006.201.15:45:06.85#ibcon#flushed, iclass 12, count 0 2006.201.15:45:06.85#ibcon#about to write, iclass 12, count 0 2006.201.15:45:06.85#ibcon#wrote, iclass 12, count 0 2006.201.15:45:06.85#ibcon#about to read 3, iclass 12, count 0 2006.201.15:45:06.88#ibcon#read 3, iclass 12, count 0 2006.201.15:45:06.88#ibcon#about to read 4, iclass 12, count 0 2006.201.15:45:06.88#ibcon#read 4, iclass 12, count 0 2006.201.15:45:06.88#ibcon#about to read 5, iclass 12, count 0 2006.201.15:45:06.88#ibcon#read 5, iclass 12, count 0 2006.201.15:45:06.88#ibcon#about to read 6, iclass 12, count 0 2006.201.15:45:06.88#ibcon#read 6, iclass 12, count 0 2006.201.15:45:06.88#ibcon#end of sib2, iclass 12, count 0 2006.201.15:45:06.88#ibcon#*after write, iclass 12, count 0 2006.201.15:45:06.88#ibcon#*before return 0, iclass 12, count 0 2006.201.15:45:06.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:06.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:06.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:45:06.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:45:06.88$vck44/valo=4,624.99 2006.201.15:45:06.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.15:45:06.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.15:45:06.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:06.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:06.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:06.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:06.88#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:45:06.88#ibcon#first serial, iclass 14, count 0 2006.201.15:45:06.88#ibcon#enter sib2, iclass 14, count 0 2006.201.15:45:06.88#ibcon#flushed, iclass 14, count 0 2006.201.15:45:06.88#ibcon#about to write, iclass 14, count 0 2006.201.15:45:06.88#ibcon#wrote, iclass 14, count 0 2006.201.15:45:06.88#ibcon#about to read 3, iclass 14, count 0 2006.201.15:45:06.90#ibcon#read 3, iclass 14, count 0 2006.201.15:45:06.90#ibcon#about to read 4, iclass 14, count 0 2006.201.15:45:06.90#ibcon#read 4, iclass 14, count 0 2006.201.15:45:06.90#ibcon#about to read 5, iclass 14, count 0 2006.201.15:45:06.90#ibcon#read 5, iclass 14, count 0 2006.201.15:45:06.90#ibcon#about to read 6, iclass 14, count 0 2006.201.15:45:06.90#ibcon#read 6, iclass 14, count 0 2006.201.15:45:06.90#ibcon#end of sib2, iclass 14, count 0 2006.201.15:45:06.90#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:45:06.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:45:06.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:45:06.90#ibcon#*before write, iclass 14, count 0 2006.201.15:45:06.90#ibcon#enter sib2, iclass 14, count 0 2006.201.15:45:06.90#ibcon#flushed, iclass 14, count 0 2006.201.15:45:06.90#ibcon#about to write, iclass 14, count 0 2006.201.15:45:06.90#ibcon#wrote, iclass 14, count 0 2006.201.15:45:06.90#ibcon#about to read 3, iclass 14, count 0 2006.201.15:45:06.95#ibcon#read 3, iclass 14, count 0 2006.201.15:45:06.95#ibcon#about to read 4, iclass 14, count 0 2006.201.15:45:06.95#ibcon#read 4, iclass 14, count 0 2006.201.15:45:06.95#ibcon#about to read 5, iclass 14, count 0 2006.201.15:45:06.95#ibcon#read 5, iclass 14, count 0 2006.201.15:45:06.95#ibcon#about to read 6, iclass 14, count 0 2006.201.15:45:06.95#ibcon#read 6, iclass 14, count 0 2006.201.15:45:06.95#ibcon#end of sib2, iclass 14, count 0 2006.201.15:45:06.95#ibcon#*after write, iclass 14, count 0 2006.201.15:45:06.95#ibcon#*before return 0, iclass 14, count 0 2006.201.15:45:06.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:06.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:06.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:45:06.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:45:06.95$vck44/va=4,7 2006.201.15:45:06.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.15:45:06.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.15:45:06.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:06.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:07.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:07.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:07.00#ibcon#enter wrdev, iclass 16, count 2 2006.201.15:45:07.00#ibcon#first serial, iclass 16, count 2 2006.201.15:45:07.00#ibcon#enter sib2, iclass 16, count 2 2006.201.15:45:07.00#ibcon#flushed, iclass 16, count 2 2006.201.15:45:07.00#ibcon#about to write, iclass 16, count 2 2006.201.15:45:07.00#ibcon#wrote, iclass 16, count 2 2006.201.15:45:07.00#ibcon#about to read 3, iclass 16, count 2 2006.201.15:45:07.02#ibcon#read 3, iclass 16, count 2 2006.201.15:45:07.02#ibcon#about to read 4, iclass 16, count 2 2006.201.15:45:07.02#ibcon#read 4, iclass 16, count 2 2006.201.15:45:07.02#ibcon#about to read 5, iclass 16, count 2 2006.201.15:45:07.02#ibcon#read 5, iclass 16, count 2 2006.201.15:45:07.02#ibcon#about to read 6, iclass 16, count 2 2006.201.15:45:07.02#ibcon#read 6, iclass 16, count 2 2006.201.15:45:07.02#ibcon#end of sib2, iclass 16, count 2 2006.201.15:45:07.02#ibcon#*mode == 0, iclass 16, count 2 2006.201.15:45:07.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.15:45:07.02#ibcon#[25=AT04-07\r\n] 2006.201.15:45:07.02#ibcon#*before write, iclass 16, count 2 2006.201.15:45:07.02#ibcon#enter sib2, iclass 16, count 2 2006.201.15:45:07.02#ibcon#flushed, iclass 16, count 2 2006.201.15:45:07.02#ibcon#about to write, iclass 16, count 2 2006.201.15:45:07.02#ibcon#wrote, iclass 16, count 2 2006.201.15:45:07.02#ibcon#about to read 3, iclass 16, count 2 2006.201.15:45:07.05#ibcon#read 3, iclass 16, count 2 2006.201.15:45:07.05#ibcon#about to read 4, iclass 16, count 2 2006.201.15:45:07.05#ibcon#read 4, iclass 16, count 2 2006.201.15:45:07.05#ibcon#about to read 5, iclass 16, count 2 2006.201.15:45:07.05#ibcon#read 5, iclass 16, count 2 2006.201.15:45:07.05#ibcon#about to read 6, iclass 16, count 2 2006.201.15:45:07.05#ibcon#read 6, iclass 16, count 2 2006.201.15:45:07.05#ibcon#end of sib2, iclass 16, count 2 2006.201.15:45:07.05#ibcon#*after write, iclass 16, count 2 2006.201.15:45:07.05#ibcon#*before return 0, iclass 16, count 2 2006.201.15:45:07.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:07.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:07.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.15:45:07.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:07.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:07.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:07.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:07.17#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:45:07.17#ibcon#first serial, iclass 16, count 0 2006.201.15:45:07.17#ibcon#enter sib2, iclass 16, count 0 2006.201.15:45:07.17#ibcon#flushed, iclass 16, count 0 2006.201.15:45:07.17#ibcon#about to write, iclass 16, count 0 2006.201.15:45:07.17#ibcon#wrote, iclass 16, count 0 2006.201.15:45:07.17#ibcon#about to read 3, iclass 16, count 0 2006.201.15:45:07.19#ibcon#read 3, iclass 16, count 0 2006.201.15:45:07.19#ibcon#about to read 4, iclass 16, count 0 2006.201.15:45:07.19#ibcon#read 4, iclass 16, count 0 2006.201.15:45:07.19#ibcon#about to read 5, iclass 16, count 0 2006.201.15:45:07.19#ibcon#read 5, iclass 16, count 0 2006.201.15:45:07.19#ibcon#about to read 6, iclass 16, count 0 2006.201.15:45:07.19#ibcon#read 6, iclass 16, count 0 2006.201.15:45:07.19#ibcon#end of sib2, iclass 16, count 0 2006.201.15:45:07.19#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:45:07.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:45:07.19#ibcon#[25=USB\r\n] 2006.201.15:45:07.19#ibcon#*before write, iclass 16, count 0 2006.201.15:45:07.19#ibcon#enter sib2, iclass 16, count 0 2006.201.15:45:07.19#ibcon#flushed, iclass 16, count 0 2006.201.15:45:07.19#ibcon#about to write, iclass 16, count 0 2006.201.15:45:07.19#ibcon#wrote, iclass 16, count 0 2006.201.15:45:07.19#ibcon#about to read 3, iclass 16, count 0 2006.201.15:45:07.22#ibcon#read 3, iclass 16, count 0 2006.201.15:45:07.22#ibcon#about to read 4, iclass 16, count 0 2006.201.15:45:07.22#ibcon#read 4, iclass 16, count 0 2006.201.15:45:07.22#ibcon#about to read 5, iclass 16, count 0 2006.201.15:45:07.22#ibcon#read 5, iclass 16, count 0 2006.201.15:45:07.22#ibcon#about to read 6, iclass 16, count 0 2006.201.15:45:07.22#ibcon#read 6, iclass 16, count 0 2006.201.15:45:07.22#ibcon#end of sib2, iclass 16, count 0 2006.201.15:45:07.22#ibcon#*after write, iclass 16, count 0 2006.201.15:45:07.22#ibcon#*before return 0, iclass 16, count 0 2006.201.15:45:07.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:07.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:07.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:45:07.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:45:07.22$vck44/valo=5,734.99 2006.201.15:45:07.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.15:45:07.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.15:45:07.22#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:07.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:07.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:07.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:07.22#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:45:07.22#ibcon#first serial, iclass 18, count 0 2006.201.15:45:07.22#ibcon#enter sib2, iclass 18, count 0 2006.201.15:45:07.22#ibcon#flushed, iclass 18, count 0 2006.201.15:45:07.22#ibcon#about to write, iclass 18, count 0 2006.201.15:45:07.22#ibcon#wrote, iclass 18, count 0 2006.201.15:45:07.22#ibcon#about to read 3, iclass 18, count 0 2006.201.15:45:07.24#ibcon#read 3, iclass 18, count 0 2006.201.15:45:07.24#ibcon#about to read 4, iclass 18, count 0 2006.201.15:45:07.24#ibcon#read 4, iclass 18, count 0 2006.201.15:45:07.24#ibcon#about to read 5, iclass 18, count 0 2006.201.15:45:07.24#ibcon#read 5, iclass 18, count 0 2006.201.15:45:07.24#ibcon#about to read 6, iclass 18, count 0 2006.201.15:45:07.24#ibcon#read 6, iclass 18, count 0 2006.201.15:45:07.24#ibcon#end of sib2, iclass 18, count 0 2006.201.15:45:07.24#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:45:07.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:45:07.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:45:07.24#ibcon#*before write, iclass 18, count 0 2006.201.15:45:07.24#ibcon#enter sib2, iclass 18, count 0 2006.201.15:45:07.24#ibcon#flushed, iclass 18, count 0 2006.201.15:45:07.24#ibcon#about to write, iclass 18, count 0 2006.201.15:45:07.24#ibcon#wrote, iclass 18, count 0 2006.201.15:45:07.24#ibcon#about to read 3, iclass 18, count 0 2006.201.15:45:07.28#ibcon#read 3, iclass 18, count 0 2006.201.15:45:07.28#ibcon#about to read 4, iclass 18, count 0 2006.201.15:45:07.28#ibcon#read 4, iclass 18, count 0 2006.201.15:45:07.28#ibcon#about to read 5, iclass 18, count 0 2006.201.15:45:07.28#ibcon#read 5, iclass 18, count 0 2006.201.15:45:07.28#ibcon#about to read 6, iclass 18, count 0 2006.201.15:45:07.28#ibcon#read 6, iclass 18, count 0 2006.201.15:45:07.28#ibcon#end of sib2, iclass 18, count 0 2006.201.15:45:07.28#ibcon#*after write, iclass 18, count 0 2006.201.15:45:07.28#ibcon#*before return 0, iclass 18, count 0 2006.201.15:45:07.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:07.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:07.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:45:07.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:45:07.28$vck44/va=5,4 2006.201.15:45:07.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.15:45:07.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.15:45:07.28#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:07.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:07.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:07.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:07.34#ibcon#enter wrdev, iclass 20, count 2 2006.201.15:45:07.34#ibcon#first serial, iclass 20, count 2 2006.201.15:45:07.34#ibcon#enter sib2, iclass 20, count 2 2006.201.15:45:07.34#ibcon#flushed, iclass 20, count 2 2006.201.15:45:07.34#ibcon#about to write, iclass 20, count 2 2006.201.15:45:07.34#ibcon#wrote, iclass 20, count 2 2006.201.15:45:07.34#ibcon#about to read 3, iclass 20, count 2 2006.201.15:45:07.36#ibcon#read 3, iclass 20, count 2 2006.201.15:45:07.36#ibcon#about to read 4, iclass 20, count 2 2006.201.15:45:07.36#ibcon#read 4, iclass 20, count 2 2006.201.15:45:07.36#ibcon#about to read 5, iclass 20, count 2 2006.201.15:45:07.36#ibcon#read 5, iclass 20, count 2 2006.201.15:45:07.36#ibcon#about to read 6, iclass 20, count 2 2006.201.15:45:07.36#ibcon#read 6, iclass 20, count 2 2006.201.15:45:07.36#ibcon#end of sib2, iclass 20, count 2 2006.201.15:45:07.36#ibcon#*mode == 0, iclass 20, count 2 2006.201.15:45:07.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.15:45:07.36#ibcon#[25=AT05-04\r\n] 2006.201.15:45:07.36#ibcon#*before write, iclass 20, count 2 2006.201.15:45:07.36#ibcon#enter sib2, iclass 20, count 2 2006.201.15:45:07.36#ibcon#flushed, iclass 20, count 2 2006.201.15:45:07.36#ibcon#about to write, iclass 20, count 2 2006.201.15:45:07.36#ibcon#wrote, iclass 20, count 2 2006.201.15:45:07.36#ibcon#about to read 3, iclass 20, count 2 2006.201.15:45:07.39#ibcon#read 3, iclass 20, count 2 2006.201.15:45:07.39#ibcon#about to read 4, iclass 20, count 2 2006.201.15:45:07.39#ibcon#read 4, iclass 20, count 2 2006.201.15:45:07.39#ibcon#about to read 5, iclass 20, count 2 2006.201.15:45:07.39#ibcon#read 5, iclass 20, count 2 2006.201.15:45:07.39#ibcon#about to read 6, iclass 20, count 2 2006.201.15:45:07.39#ibcon#read 6, iclass 20, count 2 2006.201.15:45:07.39#ibcon#end of sib2, iclass 20, count 2 2006.201.15:45:07.39#ibcon#*after write, iclass 20, count 2 2006.201.15:45:07.39#ibcon#*before return 0, iclass 20, count 2 2006.201.15:45:07.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:07.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:07.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.15:45:07.39#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:07.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:07.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:07.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:07.51#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:45:07.51#ibcon#first serial, iclass 20, count 0 2006.201.15:45:07.51#ibcon#enter sib2, iclass 20, count 0 2006.201.15:45:07.51#ibcon#flushed, iclass 20, count 0 2006.201.15:45:07.51#ibcon#about to write, iclass 20, count 0 2006.201.15:45:07.51#ibcon#wrote, iclass 20, count 0 2006.201.15:45:07.51#ibcon#about to read 3, iclass 20, count 0 2006.201.15:45:07.53#ibcon#read 3, iclass 20, count 0 2006.201.15:45:07.53#ibcon#about to read 4, iclass 20, count 0 2006.201.15:45:07.53#ibcon#read 4, iclass 20, count 0 2006.201.15:45:07.53#ibcon#about to read 5, iclass 20, count 0 2006.201.15:45:07.53#ibcon#read 5, iclass 20, count 0 2006.201.15:45:07.53#ibcon#about to read 6, iclass 20, count 0 2006.201.15:45:07.53#ibcon#read 6, iclass 20, count 0 2006.201.15:45:07.53#ibcon#end of sib2, iclass 20, count 0 2006.201.15:45:07.53#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:45:07.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:45:07.53#ibcon#[25=USB\r\n] 2006.201.15:45:07.53#ibcon#*before write, iclass 20, count 0 2006.201.15:45:07.53#ibcon#enter sib2, iclass 20, count 0 2006.201.15:45:07.53#ibcon#flushed, iclass 20, count 0 2006.201.15:45:07.53#ibcon#about to write, iclass 20, count 0 2006.201.15:45:07.53#ibcon#wrote, iclass 20, count 0 2006.201.15:45:07.53#ibcon#about to read 3, iclass 20, count 0 2006.201.15:45:07.56#ibcon#read 3, iclass 20, count 0 2006.201.15:45:07.56#ibcon#about to read 4, iclass 20, count 0 2006.201.15:45:07.56#ibcon#read 4, iclass 20, count 0 2006.201.15:45:07.56#ibcon#about to read 5, iclass 20, count 0 2006.201.15:45:07.56#ibcon#read 5, iclass 20, count 0 2006.201.15:45:07.56#ibcon#about to read 6, iclass 20, count 0 2006.201.15:45:07.56#ibcon#read 6, iclass 20, count 0 2006.201.15:45:07.56#ibcon#end of sib2, iclass 20, count 0 2006.201.15:45:07.56#ibcon#*after write, iclass 20, count 0 2006.201.15:45:07.56#ibcon#*before return 0, iclass 20, count 0 2006.201.15:45:07.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:07.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:07.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:45:07.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:45:07.56$vck44/valo=6,814.99 2006.201.15:45:07.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.15:45:07.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.15:45:07.56#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:07.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:07.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:07.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:07.56#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:45:07.56#ibcon#first serial, iclass 22, count 0 2006.201.15:45:07.56#ibcon#enter sib2, iclass 22, count 0 2006.201.15:45:07.56#ibcon#flushed, iclass 22, count 0 2006.201.15:45:07.56#ibcon#about to write, iclass 22, count 0 2006.201.15:45:07.56#ibcon#wrote, iclass 22, count 0 2006.201.15:45:07.56#ibcon#about to read 3, iclass 22, count 0 2006.201.15:45:07.58#ibcon#read 3, iclass 22, count 0 2006.201.15:45:07.58#ibcon#about to read 4, iclass 22, count 0 2006.201.15:45:07.58#ibcon#read 4, iclass 22, count 0 2006.201.15:45:07.58#ibcon#about to read 5, iclass 22, count 0 2006.201.15:45:07.58#ibcon#read 5, iclass 22, count 0 2006.201.15:45:07.58#ibcon#about to read 6, iclass 22, count 0 2006.201.15:45:07.58#ibcon#read 6, iclass 22, count 0 2006.201.15:45:07.58#ibcon#end of sib2, iclass 22, count 0 2006.201.15:45:07.58#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:45:07.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:45:07.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:45:07.58#ibcon#*before write, iclass 22, count 0 2006.201.15:45:07.58#ibcon#enter sib2, iclass 22, count 0 2006.201.15:45:07.58#ibcon#flushed, iclass 22, count 0 2006.201.15:45:07.58#ibcon#about to write, iclass 22, count 0 2006.201.15:45:07.58#ibcon#wrote, iclass 22, count 0 2006.201.15:45:07.58#ibcon#about to read 3, iclass 22, count 0 2006.201.15:45:07.63#ibcon#read 3, iclass 22, count 0 2006.201.15:45:07.63#ibcon#about to read 4, iclass 22, count 0 2006.201.15:45:07.63#ibcon#read 4, iclass 22, count 0 2006.201.15:45:07.63#ibcon#about to read 5, iclass 22, count 0 2006.201.15:45:07.63#ibcon#read 5, iclass 22, count 0 2006.201.15:45:07.63#ibcon#about to read 6, iclass 22, count 0 2006.201.15:45:07.63#ibcon#read 6, iclass 22, count 0 2006.201.15:45:07.63#ibcon#end of sib2, iclass 22, count 0 2006.201.15:45:07.63#ibcon#*after write, iclass 22, count 0 2006.201.15:45:07.63#ibcon#*before return 0, iclass 22, count 0 2006.201.15:45:07.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:07.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:07.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:45:07.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:45:07.63$vck44/va=6,5 2006.201.15:45:07.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.15:45:07.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.15:45:07.63#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:07.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:07.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:07.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:07.68#ibcon#enter wrdev, iclass 24, count 2 2006.201.15:45:07.68#ibcon#first serial, iclass 24, count 2 2006.201.15:45:07.68#ibcon#enter sib2, iclass 24, count 2 2006.201.15:45:07.68#ibcon#flushed, iclass 24, count 2 2006.201.15:45:07.68#ibcon#about to write, iclass 24, count 2 2006.201.15:45:07.68#ibcon#wrote, iclass 24, count 2 2006.201.15:45:07.68#ibcon#about to read 3, iclass 24, count 2 2006.201.15:45:07.70#ibcon#read 3, iclass 24, count 2 2006.201.15:45:07.70#ibcon#about to read 4, iclass 24, count 2 2006.201.15:45:07.70#ibcon#read 4, iclass 24, count 2 2006.201.15:45:07.70#ibcon#about to read 5, iclass 24, count 2 2006.201.15:45:07.70#ibcon#read 5, iclass 24, count 2 2006.201.15:45:07.70#ibcon#about to read 6, iclass 24, count 2 2006.201.15:45:07.70#ibcon#read 6, iclass 24, count 2 2006.201.15:45:07.70#ibcon#end of sib2, iclass 24, count 2 2006.201.15:45:07.70#ibcon#*mode == 0, iclass 24, count 2 2006.201.15:45:07.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.15:45:07.70#ibcon#[25=AT06-05\r\n] 2006.201.15:45:07.70#ibcon#*before write, iclass 24, count 2 2006.201.15:45:07.70#ibcon#enter sib2, iclass 24, count 2 2006.201.15:45:07.70#ibcon#flushed, iclass 24, count 2 2006.201.15:45:07.70#ibcon#about to write, iclass 24, count 2 2006.201.15:45:07.70#ibcon#wrote, iclass 24, count 2 2006.201.15:45:07.70#ibcon#about to read 3, iclass 24, count 2 2006.201.15:45:07.73#ibcon#read 3, iclass 24, count 2 2006.201.15:45:07.73#ibcon#about to read 4, iclass 24, count 2 2006.201.15:45:07.73#ibcon#read 4, iclass 24, count 2 2006.201.15:45:07.73#ibcon#about to read 5, iclass 24, count 2 2006.201.15:45:07.73#ibcon#read 5, iclass 24, count 2 2006.201.15:45:07.73#ibcon#about to read 6, iclass 24, count 2 2006.201.15:45:07.73#ibcon#read 6, iclass 24, count 2 2006.201.15:45:07.73#ibcon#end of sib2, iclass 24, count 2 2006.201.15:45:07.73#ibcon#*after write, iclass 24, count 2 2006.201.15:45:07.73#ibcon#*before return 0, iclass 24, count 2 2006.201.15:45:07.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:07.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:07.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.15:45:07.73#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:07.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:07.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:07.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:07.85#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:45:07.85#ibcon#first serial, iclass 24, count 0 2006.201.15:45:07.85#ibcon#enter sib2, iclass 24, count 0 2006.201.15:45:07.85#ibcon#flushed, iclass 24, count 0 2006.201.15:45:07.85#ibcon#about to write, iclass 24, count 0 2006.201.15:45:07.85#ibcon#wrote, iclass 24, count 0 2006.201.15:45:07.85#ibcon#about to read 3, iclass 24, count 0 2006.201.15:45:07.87#ibcon#read 3, iclass 24, count 0 2006.201.15:45:07.87#ibcon#about to read 4, iclass 24, count 0 2006.201.15:45:07.87#ibcon#read 4, iclass 24, count 0 2006.201.15:45:07.87#ibcon#about to read 5, iclass 24, count 0 2006.201.15:45:07.87#ibcon#read 5, iclass 24, count 0 2006.201.15:45:07.87#ibcon#about to read 6, iclass 24, count 0 2006.201.15:45:07.87#ibcon#read 6, iclass 24, count 0 2006.201.15:45:07.87#ibcon#end of sib2, iclass 24, count 0 2006.201.15:45:07.87#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:45:07.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:45:07.87#ibcon#[25=USB\r\n] 2006.201.15:45:07.87#ibcon#*before write, iclass 24, count 0 2006.201.15:45:07.87#ibcon#enter sib2, iclass 24, count 0 2006.201.15:45:07.87#ibcon#flushed, iclass 24, count 0 2006.201.15:45:07.87#ibcon#about to write, iclass 24, count 0 2006.201.15:45:07.87#ibcon#wrote, iclass 24, count 0 2006.201.15:45:07.87#ibcon#about to read 3, iclass 24, count 0 2006.201.15:45:07.90#ibcon#read 3, iclass 24, count 0 2006.201.15:45:07.90#ibcon#about to read 4, iclass 24, count 0 2006.201.15:45:07.90#ibcon#read 4, iclass 24, count 0 2006.201.15:45:07.90#ibcon#about to read 5, iclass 24, count 0 2006.201.15:45:07.90#ibcon#read 5, iclass 24, count 0 2006.201.15:45:07.90#ibcon#about to read 6, iclass 24, count 0 2006.201.15:45:07.90#ibcon#read 6, iclass 24, count 0 2006.201.15:45:07.90#ibcon#end of sib2, iclass 24, count 0 2006.201.15:45:07.90#ibcon#*after write, iclass 24, count 0 2006.201.15:45:07.90#ibcon#*before return 0, iclass 24, count 0 2006.201.15:45:07.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:07.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:07.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:45:07.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:45:07.90$vck44/valo=7,864.99 2006.201.15:45:07.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.15:45:07.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.15:45:07.90#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:07.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:07.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:07.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:07.90#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:45:07.90#ibcon#first serial, iclass 26, count 0 2006.201.15:45:07.90#ibcon#enter sib2, iclass 26, count 0 2006.201.15:45:07.90#ibcon#flushed, iclass 26, count 0 2006.201.15:45:07.90#ibcon#about to write, iclass 26, count 0 2006.201.15:45:07.90#ibcon#wrote, iclass 26, count 0 2006.201.15:45:07.90#ibcon#about to read 3, iclass 26, count 0 2006.201.15:45:07.92#ibcon#read 3, iclass 26, count 0 2006.201.15:45:07.92#ibcon#about to read 4, iclass 26, count 0 2006.201.15:45:07.92#ibcon#read 4, iclass 26, count 0 2006.201.15:45:07.92#ibcon#about to read 5, iclass 26, count 0 2006.201.15:45:07.92#ibcon#read 5, iclass 26, count 0 2006.201.15:45:07.92#ibcon#about to read 6, iclass 26, count 0 2006.201.15:45:07.92#ibcon#read 6, iclass 26, count 0 2006.201.15:45:07.92#ibcon#end of sib2, iclass 26, count 0 2006.201.15:45:07.92#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:45:07.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:45:07.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:45:07.92#ibcon#*before write, iclass 26, count 0 2006.201.15:45:07.92#ibcon#enter sib2, iclass 26, count 0 2006.201.15:45:07.92#ibcon#flushed, iclass 26, count 0 2006.201.15:45:07.92#ibcon#about to write, iclass 26, count 0 2006.201.15:45:07.92#ibcon#wrote, iclass 26, count 0 2006.201.15:45:07.92#ibcon#about to read 3, iclass 26, count 0 2006.201.15:45:07.97#ibcon#read 3, iclass 26, count 0 2006.201.15:45:07.97#ibcon#about to read 4, iclass 26, count 0 2006.201.15:45:07.97#ibcon#read 4, iclass 26, count 0 2006.201.15:45:07.97#ibcon#about to read 5, iclass 26, count 0 2006.201.15:45:07.97#ibcon#read 5, iclass 26, count 0 2006.201.15:45:07.97#ibcon#about to read 6, iclass 26, count 0 2006.201.15:45:07.97#ibcon#read 6, iclass 26, count 0 2006.201.15:45:07.97#ibcon#end of sib2, iclass 26, count 0 2006.201.15:45:07.97#ibcon#*after write, iclass 26, count 0 2006.201.15:45:07.97#ibcon#*before return 0, iclass 26, count 0 2006.201.15:45:07.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:07.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:07.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:45:07.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:45:07.97$vck44/va=7,5 2006.201.15:45:07.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.15:45:07.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.15:45:07.97#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:07.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:08.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:08.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:08.02#ibcon#enter wrdev, iclass 28, count 2 2006.201.15:45:08.02#ibcon#first serial, iclass 28, count 2 2006.201.15:45:08.02#ibcon#enter sib2, iclass 28, count 2 2006.201.15:45:08.02#ibcon#flushed, iclass 28, count 2 2006.201.15:45:08.02#ibcon#about to write, iclass 28, count 2 2006.201.15:45:08.02#ibcon#wrote, iclass 28, count 2 2006.201.15:45:08.02#ibcon#about to read 3, iclass 28, count 2 2006.201.15:45:08.04#ibcon#read 3, iclass 28, count 2 2006.201.15:45:08.04#ibcon#about to read 4, iclass 28, count 2 2006.201.15:45:08.04#ibcon#read 4, iclass 28, count 2 2006.201.15:45:08.04#ibcon#about to read 5, iclass 28, count 2 2006.201.15:45:08.04#ibcon#read 5, iclass 28, count 2 2006.201.15:45:08.04#ibcon#about to read 6, iclass 28, count 2 2006.201.15:45:08.04#ibcon#read 6, iclass 28, count 2 2006.201.15:45:08.04#ibcon#end of sib2, iclass 28, count 2 2006.201.15:45:08.04#ibcon#*mode == 0, iclass 28, count 2 2006.201.15:45:08.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.15:45:08.04#ibcon#[25=AT07-05\r\n] 2006.201.15:45:08.04#ibcon#*before write, iclass 28, count 2 2006.201.15:45:08.04#ibcon#enter sib2, iclass 28, count 2 2006.201.15:45:08.04#ibcon#flushed, iclass 28, count 2 2006.201.15:45:08.04#ibcon#about to write, iclass 28, count 2 2006.201.15:45:08.04#ibcon#wrote, iclass 28, count 2 2006.201.15:45:08.04#ibcon#about to read 3, iclass 28, count 2 2006.201.15:45:08.07#ibcon#read 3, iclass 28, count 2 2006.201.15:45:08.07#ibcon#about to read 4, iclass 28, count 2 2006.201.15:45:08.07#ibcon#read 4, iclass 28, count 2 2006.201.15:45:08.07#ibcon#about to read 5, iclass 28, count 2 2006.201.15:45:08.07#ibcon#read 5, iclass 28, count 2 2006.201.15:45:08.07#ibcon#about to read 6, iclass 28, count 2 2006.201.15:45:08.07#ibcon#read 6, iclass 28, count 2 2006.201.15:45:08.07#ibcon#end of sib2, iclass 28, count 2 2006.201.15:45:08.07#ibcon#*after write, iclass 28, count 2 2006.201.15:45:08.07#ibcon#*before return 0, iclass 28, count 2 2006.201.15:45:08.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:08.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:08.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.15:45:08.07#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:08.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:08.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:08.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:08.19#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:45:08.19#ibcon#first serial, iclass 28, count 0 2006.201.15:45:08.19#ibcon#enter sib2, iclass 28, count 0 2006.201.15:45:08.19#ibcon#flushed, iclass 28, count 0 2006.201.15:45:08.19#ibcon#about to write, iclass 28, count 0 2006.201.15:45:08.19#ibcon#wrote, iclass 28, count 0 2006.201.15:45:08.19#ibcon#about to read 3, iclass 28, count 0 2006.201.15:45:08.21#ibcon#read 3, iclass 28, count 0 2006.201.15:45:08.21#ibcon#about to read 4, iclass 28, count 0 2006.201.15:45:08.21#ibcon#read 4, iclass 28, count 0 2006.201.15:45:08.21#ibcon#about to read 5, iclass 28, count 0 2006.201.15:45:08.21#ibcon#read 5, iclass 28, count 0 2006.201.15:45:08.21#ibcon#about to read 6, iclass 28, count 0 2006.201.15:45:08.21#ibcon#read 6, iclass 28, count 0 2006.201.15:45:08.21#ibcon#end of sib2, iclass 28, count 0 2006.201.15:45:08.21#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:45:08.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:45:08.21#ibcon#[25=USB\r\n] 2006.201.15:45:08.21#ibcon#*before write, iclass 28, count 0 2006.201.15:45:08.21#ibcon#enter sib2, iclass 28, count 0 2006.201.15:45:08.21#ibcon#flushed, iclass 28, count 0 2006.201.15:45:08.21#ibcon#about to write, iclass 28, count 0 2006.201.15:45:08.21#ibcon#wrote, iclass 28, count 0 2006.201.15:45:08.21#ibcon#about to read 3, iclass 28, count 0 2006.201.15:45:08.24#ibcon#read 3, iclass 28, count 0 2006.201.15:45:08.24#ibcon#about to read 4, iclass 28, count 0 2006.201.15:45:08.24#ibcon#read 4, iclass 28, count 0 2006.201.15:45:08.24#ibcon#about to read 5, iclass 28, count 0 2006.201.15:45:08.24#ibcon#read 5, iclass 28, count 0 2006.201.15:45:08.24#ibcon#about to read 6, iclass 28, count 0 2006.201.15:45:08.24#ibcon#read 6, iclass 28, count 0 2006.201.15:45:08.24#ibcon#end of sib2, iclass 28, count 0 2006.201.15:45:08.24#ibcon#*after write, iclass 28, count 0 2006.201.15:45:08.24#ibcon#*before return 0, iclass 28, count 0 2006.201.15:45:08.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:08.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:08.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:45:08.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:45:08.24$vck44/valo=8,884.99 2006.201.15:45:08.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.15:45:08.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.15:45:08.24#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:08.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:08.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:08.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:08.24#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:45:08.24#ibcon#first serial, iclass 30, count 0 2006.201.15:45:08.24#ibcon#enter sib2, iclass 30, count 0 2006.201.15:45:08.24#ibcon#flushed, iclass 30, count 0 2006.201.15:45:08.24#ibcon#about to write, iclass 30, count 0 2006.201.15:45:08.24#ibcon#wrote, iclass 30, count 0 2006.201.15:45:08.24#ibcon#about to read 3, iclass 30, count 0 2006.201.15:45:08.26#ibcon#read 3, iclass 30, count 0 2006.201.15:45:08.26#ibcon#about to read 4, iclass 30, count 0 2006.201.15:45:08.26#ibcon#read 4, iclass 30, count 0 2006.201.15:45:08.26#ibcon#about to read 5, iclass 30, count 0 2006.201.15:45:08.26#ibcon#read 5, iclass 30, count 0 2006.201.15:45:08.26#ibcon#about to read 6, iclass 30, count 0 2006.201.15:45:08.26#ibcon#read 6, iclass 30, count 0 2006.201.15:45:08.26#ibcon#end of sib2, iclass 30, count 0 2006.201.15:45:08.26#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:45:08.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:45:08.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:45:08.26#ibcon#*before write, iclass 30, count 0 2006.201.15:45:08.26#ibcon#enter sib2, iclass 30, count 0 2006.201.15:45:08.26#ibcon#flushed, iclass 30, count 0 2006.201.15:45:08.26#ibcon#about to write, iclass 30, count 0 2006.201.15:45:08.26#ibcon#wrote, iclass 30, count 0 2006.201.15:45:08.26#ibcon#about to read 3, iclass 30, count 0 2006.201.15:45:08.30#ibcon#read 3, iclass 30, count 0 2006.201.15:45:08.30#ibcon#about to read 4, iclass 30, count 0 2006.201.15:45:08.30#ibcon#read 4, iclass 30, count 0 2006.201.15:45:08.30#ibcon#about to read 5, iclass 30, count 0 2006.201.15:45:08.30#ibcon#read 5, iclass 30, count 0 2006.201.15:45:08.30#ibcon#about to read 6, iclass 30, count 0 2006.201.15:45:08.30#ibcon#read 6, iclass 30, count 0 2006.201.15:45:08.30#ibcon#end of sib2, iclass 30, count 0 2006.201.15:45:08.30#ibcon#*after write, iclass 30, count 0 2006.201.15:45:08.30#ibcon#*before return 0, iclass 30, count 0 2006.201.15:45:08.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:08.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:08.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:45:08.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:45:08.30$vck44/va=8,4 2006.201.15:45:08.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.15:45:08.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.15:45:08.30#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:08.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:45:08.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:45:08.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:45:08.36#ibcon#enter wrdev, iclass 32, count 2 2006.201.15:45:08.36#ibcon#first serial, iclass 32, count 2 2006.201.15:45:08.36#ibcon#enter sib2, iclass 32, count 2 2006.201.15:45:08.36#ibcon#flushed, iclass 32, count 2 2006.201.15:45:08.36#ibcon#about to write, iclass 32, count 2 2006.201.15:45:08.36#ibcon#wrote, iclass 32, count 2 2006.201.15:45:08.36#ibcon#about to read 3, iclass 32, count 2 2006.201.15:45:08.38#ibcon#read 3, iclass 32, count 2 2006.201.15:45:08.38#ibcon#about to read 4, iclass 32, count 2 2006.201.15:45:08.38#ibcon#read 4, iclass 32, count 2 2006.201.15:45:08.38#ibcon#about to read 5, iclass 32, count 2 2006.201.15:45:08.38#ibcon#read 5, iclass 32, count 2 2006.201.15:45:08.38#ibcon#about to read 6, iclass 32, count 2 2006.201.15:45:08.38#ibcon#read 6, iclass 32, count 2 2006.201.15:45:08.38#ibcon#end of sib2, iclass 32, count 2 2006.201.15:45:08.38#ibcon#*mode == 0, iclass 32, count 2 2006.201.15:45:08.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.15:45:08.38#ibcon#[25=AT08-04\r\n] 2006.201.15:45:08.38#ibcon#*before write, iclass 32, count 2 2006.201.15:45:08.38#ibcon#enter sib2, iclass 32, count 2 2006.201.15:45:08.38#ibcon#flushed, iclass 32, count 2 2006.201.15:45:08.38#ibcon#about to write, iclass 32, count 2 2006.201.15:45:08.38#ibcon#wrote, iclass 32, count 2 2006.201.15:45:08.38#ibcon#about to read 3, iclass 32, count 2 2006.201.15:45:08.41#ibcon#read 3, iclass 32, count 2 2006.201.15:45:08.41#ibcon#about to read 4, iclass 32, count 2 2006.201.15:45:08.41#ibcon#read 4, iclass 32, count 2 2006.201.15:45:08.41#ibcon#about to read 5, iclass 32, count 2 2006.201.15:45:08.41#ibcon#read 5, iclass 32, count 2 2006.201.15:45:08.41#ibcon#about to read 6, iclass 32, count 2 2006.201.15:45:08.41#ibcon#read 6, iclass 32, count 2 2006.201.15:45:08.41#ibcon#end of sib2, iclass 32, count 2 2006.201.15:45:08.41#ibcon#*after write, iclass 32, count 2 2006.201.15:45:08.41#ibcon#*before return 0, iclass 32, count 2 2006.201.15:45:08.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:45:08.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.15:45:08.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.15:45:08.41#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:08.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:45:08.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:45:08.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:45:08.53#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:45:08.53#ibcon#first serial, iclass 32, count 0 2006.201.15:45:08.53#ibcon#enter sib2, iclass 32, count 0 2006.201.15:45:08.53#ibcon#flushed, iclass 32, count 0 2006.201.15:45:08.53#ibcon#about to write, iclass 32, count 0 2006.201.15:45:08.53#ibcon#wrote, iclass 32, count 0 2006.201.15:45:08.53#ibcon#about to read 3, iclass 32, count 0 2006.201.15:45:08.55#ibcon#read 3, iclass 32, count 0 2006.201.15:45:08.55#ibcon#about to read 4, iclass 32, count 0 2006.201.15:45:08.55#ibcon#read 4, iclass 32, count 0 2006.201.15:45:08.55#ibcon#about to read 5, iclass 32, count 0 2006.201.15:45:08.55#ibcon#read 5, iclass 32, count 0 2006.201.15:45:08.55#ibcon#about to read 6, iclass 32, count 0 2006.201.15:45:08.55#ibcon#read 6, iclass 32, count 0 2006.201.15:45:08.55#ibcon#end of sib2, iclass 32, count 0 2006.201.15:45:08.55#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:45:08.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:45:08.55#ibcon#[25=USB\r\n] 2006.201.15:45:08.55#ibcon#*before write, iclass 32, count 0 2006.201.15:45:08.55#ibcon#enter sib2, iclass 32, count 0 2006.201.15:45:08.55#ibcon#flushed, iclass 32, count 0 2006.201.15:45:08.55#ibcon#about to write, iclass 32, count 0 2006.201.15:45:08.55#ibcon#wrote, iclass 32, count 0 2006.201.15:45:08.55#ibcon#about to read 3, iclass 32, count 0 2006.201.15:45:08.58#ibcon#read 3, iclass 32, count 0 2006.201.15:45:08.58#ibcon#about to read 4, iclass 32, count 0 2006.201.15:45:08.58#ibcon#read 4, iclass 32, count 0 2006.201.15:45:08.58#ibcon#about to read 5, iclass 32, count 0 2006.201.15:45:08.58#ibcon#read 5, iclass 32, count 0 2006.201.15:45:08.58#ibcon#about to read 6, iclass 32, count 0 2006.201.15:45:08.58#ibcon#read 6, iclass 32, count 0 2006.201.15:45:08.58#ibcon#end of sib2, iclass 32, count 0 2006.201.15:45:08.58#ibcon#*after write, iclass 32, count 0 2006.201.15:45:08.58#ibcon#*before return 0, iclass 32, count 0 2006.201.15:45:08.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:45:08.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.15:45:08.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:45:08.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:45:08.58$vck44/vblo=1,629.99 2006.201.15:45:08.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.15:45:08.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.15:45:08.58#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:08.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:45:08.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:45:08.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:45:08.58#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:45:08.58#ibcon#first serial, iclass 34, count 0 2006.201.15:45:08.58#ibcon#enter sib2, iclass 34, count 0 2006.201.15:45:08.58#ibcon#flushed, iclass 34, count 0 2006.201.15:45:08.58#ibcon#about to write, iclass 34, count 0 2006.201.15:45:08.58#ibcon#wrote, iclass 34, count 0 2006.201.15:45:08.58#ibcon#about to read 3, iclass 34, count 0 2006.201.15:45:08.60#ibcon#read 3, iclass 34, count 0 2006.201.15:45:08.60#ibcon#about to read 4, iclass 34, count 0 2006.201.15:45:08.60#ibcon#read 4, iclass 34, count 0 2006.201.15:45:08.60#ibcon#about to read 5, iclass 34, count 0 2006.201.15:45:08.60#ibcon#read 5, iclass 34, count 0 2006.201.15:45:08.60#ibcon#about to read 6, iclass 34, count 0 2006.201.15:45:08.60#ibcon#read 6, iclass 34, count 0 2006.201.15:45:08.60#ibcon#end of sib2, iclass 34, count 0 2006.201.15:45:08.60#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:45:08.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:45:08.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:45:08.60#ibcon#*before write, iclass 34, count 0 2006.201.15:45:08.60#ibcon#enter sib2, iclass 34, count 0 2006.201.15:45:08.60#ibcon#flushed, iclass 34, count 0 2006.201.15:45:08.60#ibcon#about to write, iclass 34, count 0 2006.201.15:45:08.60#ibcon#wrote, iclass 34, count 0 2006.201.15:45:08.60#ibcon#about to read 3, iclass 34, count 0 2006.201.15:45:08.65#ibcon#read 3, iclass 34, count 0 2006.201.15:45:08.65#ibcon#about to read 4, iclass 34, count 0 2006.201.15:45:08.65#ibcon#read 4, iclass 34, count 0 2006.201.15:45:08.65#ibcon#about to read 5, iclass 34, count 0 2006.201.15:45:08.65#ibcon#read 5, iclass 34, count 0 2006.201.15:45:08.65#ibcon#about to read 6, iclass 34, count 0 2006.201.15:45:08.65#ibcon#read 6, iclass 34, count 0 2006.201.15:45:08.65#ibcon#end of sib2, iclass 34, count 0 2006.201.15:45:08.65#ibcon#*after write, iclass 34, count 0 2006.201.15:45:08.65#ibcon#*before return 0, iclass 34, count 0 2006.201.15:45:08.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:45:08.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.15:45:08.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:45:08.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:45:08.65$vck44/vb=1,4 2006.201.15:45:08.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.15:45:08.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.15:45:08.65#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:08.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:45:08.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:45:08.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:45:08.65#ibcon#enter wrdev, iclass 36, count 2 2006.201.15:45:08.65#ibcon#first serial, iclass 36, count 2 2006.201.15:45:08.65#ibcon#enter sib2, iclass 36, count 2 2006.201.15:45:08.65#ibcon#flushed, iclass 36, count 2 2006.201.15:45:08.65#ibcon#about to write, iclass 36, count 2 2006.201.15:45:08.65#ibcon#wrote, iclass 36, count 2 2006.201.15:45:08.65#ibcon#about to read 3, iclass 36, count 2 2006.201.15:45:08.67#ibcon#read 3, iclass 36, count 2 2006.201.15:45:08.67#ibcon#about to read 4, iclass 36, count 2 2006.201.15:45:08.67#ibcon#read 4, iclass 36, count 2 2006.201.15:45:08.67#ibcon#about to read 5, iclass 36, count 2 2006.201.15:45:08.67#ibcon#read 5, iclass 36, count 2 2006.201.15:45:08.67#ibcon#about to read 6, iclass 36, count 2 2006.201.15:45:08.67#ibcon#read 6, iclass 36, count 2 2006.201.15:45:08.67#ibcon#end of sib2, iclass 36, count 2 2006.201.15:45:08.67#ibcon#*mode == 0, iclass 36, count 2 2006.201.15:45:08.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.15:45:08.67#ibcon#[27=AT01-04\r\n] 2006.201.15:45:08.67#ibcon#*before write, iclass 36, count 2 2006.201.15:45:08.67#ibcon#enter sib2, iclass 36, count 2 2006.201.15:45:08.67#ibcon#flushed, iclass 36, count 2 2006.201.15:45:08.67#ibcon#about to write, iclass 36, count 2 2006.201.15:45:08.67#ibcon#wrote, iclass 36, count 2 2006.201.15:45:08.67#ibcon#about to read 3, iclass 36, count 2 2006.201.15:45:08.70#ibcon#read 3, iclass 36, count 2 2006.201.15:45:08.70#ibcon#about to read 4, iclass 36, count 2 2006.201.15:45:08.70#ibcon#read 4, iclass 36, count 2 2006.201.15:45:08.70#ibcon#about to read 5, iclass 36, count 2 2006.201.15:45:08.70#ibcon#read 5, iclass 36, count 2 2006.201.15:45:08.70#ibcon#about to read 6, iclass 36, count 2 2006.201.15:45:08.70#ibcon#read 6, iclass 36, count 2 2006.201.15:45:08.70#ibcon#end of sib2, iclass 36, count 2 2006.201.15:45:08.70#ibcon#*after write, iclass 36, count 2 2006.201.15:45:08.70#ibcon#*before return 0, iclass 36, count 2 2006.201.15:45:08.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:45:08.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.15:45:08.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.15:45:08.70#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:08.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:45:08.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:45:08.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:45:08.82#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:45:08.82#ibcon#first serial, iclass 36, count 0 2006.201.15:45:08.82#ibcon#enter sib2, iclass 36, count 0 2006.201.15:45:08.82#ibcon#flushed, iclass 36, count 0 2006.201.15:45:08.82#ibcon#about to write, iclass 36, count 0 2006.201.15:45:08.82#ibcon#wrote, iclass 36, count 0 2006.201.15:45:08.82#ibcon#about to read 3, iclass 36, count 0 2006.201.15:45:08.84#ibcon#read 3, iclass 36, count 0 2006.201.15:45:08.84#ibcon#about to read 4, iclass 36, count 0 2006.201.15:45:08.84#ibcon#read 4, iclass 36, count 0 2006.201.15:45:08.84#ibcon#about to read 5, iclass 36, count 0 2006.201.15:45:08.84#ibcon#read 5, iclass 36, count 0 2006.201.15:45:08.84#ibcon#about to read 6, iclass 36, count 0 2006.201.15:45:08.84#ibcon#read 6, iclass 36, count 0 2006.201.15:45:08.84#ibcon#end of sib2, iclass 36, count 0 2006.201.15:45:08.84#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:45:08.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:45:08.84#ibcon#[27=USB\r\n] 2006.201.15:45:08.84#ibcon#*before write, iclass 36, count 0 2006.201.15:45:08.84#ibcon#enter sib2, iclass 36, count 0 2006.201.15:45:08.84#ibcon#flushed, iclass 36, count 0 2006.201.15:45:08.84#ibcon#about to write, iclass 36, count 0 2006.201.15:45:08.84#ibcon#wrote, iclass 36, count 0 2006.201.15:45:08.84#ibcon#about to read 3, iclass 36, count 0 2006.201.15:45:08.87#ibcon#read 3, iclass 36, count 0 2006.201.15:45:08.87#ibcon#about to read 4, iclass 36, count 0 2006.201.15:45:08.87#ibcon#read 4, iclass 36, count 0 2006.201.15:45:08.87#ibcon#about to read 5, iclass 36, count 0 2006.201.15:45:08.87#ibcon#read 5, iclass 36, count 0 2006.201.15:45:08.87#ibcon#about to read 6, iclass 36, count 0 2006.201.15:45:08.87#ibcon#read 6, iclass 36, count 0 2006.201.15:45:08.87#ibcon#end of sib2, iclass 36, count 0 2006.201.15:45:08.87#ibcon#*after write, iclass 36, count 0 2006.201.15:45:08.87#ibcon#*before return 0, iclass 36, count 0 2006.201.15:45:08.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:45:08.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.15:45:08.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:45:08.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:45:08.87$vck44/vblo=2,634.99 2006.201.15:45:08.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.15:45:08.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.15:45:08.87#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:08.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:08.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:08.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:08.87#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:45:08.87#ibcon#first serial, iclass 38, count 0 2006.201.15:45:08.87#ibcon#enter sib2, iclass 38, count 0 2006.201.15:45:08.87#ibcon#flushed, iclass 38, count 0 2006.201.15:45:08.87#ibcon#about to write, iclass 38, count 0 2006.201.15:45:08.87#ibcon#wrote, iclass 38, count 0 2006.201.15:45:08.87#ibcon#about to read 3, iclass 38, count 0 2006.201.15:45:08.89#ibcon#read 3, iclass 38, count 0 2006.201.15:45:08.89#ibcon#about to read 4, iclass 38, count 0 2006.201.15:45:08.89#ibcon#read 4, iclass 38, count 0 2006.201.15:45:08.89#ibcon#about to read 5, iclass 38, count 0 2006.201.15:45:08.89#ibcon#read 5, iclass 38, count 0 2006.201.15:45:08.89#ibcon#about to read 6, iclass 38, count 0 2006.201.15:45:08.89#ibcon#read 6, iclass 38, count 0 2006.201.15:45:08.89#ibcon#end of sib2, iclass 38, count 0 2006.201.15:45:08.89#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:45:08.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:45:08.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:45:08.89#ibcon#*before write, iclass 38, count 0 2006.201.15:45:08.89#ibcon#enter sib2, iclass 38, count 0 2006.201.15:45:08.89#ibcon#flushed, iclass 38, count 0 2006.201.15:45:08.89#ibcon#about to write, iclass 38, count 0 2006.201.15:45:08.89#ibcon#wrote, iclass 38, count 0 2006.201.15:45:08.89#ibcon#about to read 3, iclass 38, count 0 2006.201.15:45:08.93#ibcon#read 3, iclass 38, count 0 2006.201.15:45:08.93#ibcon#about to read 4, iclass 38, count 0 2006.201.15:45:08.93#ibcon#read 4, iclass 38, count 0 2006.201.15:45:08.93#ibcon#about to read 5, iclass 38, count 0 2006.201.15:45:08.93#ibcon#read 5, iclass 38, count 0 2006.201.15:45:08.93#ibcon#about to read 6, iclass 38, count 0 2006.201.15:45:08.93#ibcon#read 6, iclass 38, count 0 2006.201.15:45:08.93#ibcon#end of sib2, iclass 38, count 0 2006.201.15:45:08.93#ibcon#*after write, iclass 38, count 0 2006.201.15:45:08.93#ibcon#*before return 0, iclass 38, count 0 2006.201.15:45:08.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:08.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.15:45:08.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:45:08.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:45:08.93$vck44/vb=2,5 2006.201.15:45:08.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.15:45:08.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.15:45:08.93#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:08.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:08.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:08.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:08.99#ibcon#enter wrdev, iclass 40, count 2 2006.201.15:45:08.99#ibcon#first serial, iclass 40, count 2 2006.201.15:45:08.99#ibcon#enter sib2, iclass 40, count 2 2006.201.15:45:08.99#ibcon#flushed, iclass 40, count 2 2006.201.15:45:08.99#ibcon#about to write, iclass 40, count 2 2006.201.15:45:08.99#ibcon#wrote, iclass 40, count 2 2006.201.15:45:08.99#ibcon#about to read 3, iclass 40, count 2 2006.201.15:45:09.01#ibcon#read 3, iclass 40, count 2 2006.201.15:45:09.01#ibcon#about to read 4, iclass 40, count 2 2006.201.15:45:09.01#ibcon#read 4, iclass 40, count 2 2006.201.15:45:09.01#ibcon#about to read 5, iclass 40, count 2 2006.201.15:45:09.01#ibcon#read 5, iclass 40, count 2 2006.201.15:45:09.01#ibcon#about to read 6, iclass 40, count 2 2006.201.15:45:09.01#ibcon#read 6, iclass 40, count 2 2006.201.15:45:09.01#ibcon#end of sib2, iclass 40, count 2 2006.201.15:45:09.01#ibcon#*mode == 0, iclass 40, count 2 2006.201.15:45:09.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.15:45:09.01#ibcon#[27=AT02-05\r\n] 2006.201.15:45:09.01#ibcon#*before write, iclass 40, count 2 2006.201.15:45:09.01#ibcon#enter sib2, iclass 40, count 2 2006.201.15:45:09.01#ibcon#flushed, iclass 40, count 2 2006.201.15:45:09.01#ibcon#about to write, iclass 40, count 2 2006.201.15:45:09.01#ibcon#wrote, iclass 40, count 2 2006.201.15:45:09.01#ibcon#about to read 3, iclass 40, count 2 2006.201.15:45:09.04#ibcon#read 3, iclass 40, count 2 2006.201.15:45:09.04#ibcon#about to read 4, iclass 40, count 2 2006.201.15:45:09.04#ibcon#read 4, iclass 40, count 2 2006.201.15:45:09.04#ibcon#about to read 5, iclass 40, count 2 2006.201.15:45:09.04#ibcon#read 5, iclass 40, count 2 2006.201.15:45:09.04#ibcon#about to read 6, iclass 40, count 2 2006.201.15:45:09.04#ibcon#read 6, iclass 40, count 2 2006.201.15:45:09.04#ibcon#end of sib2, iclass 40, count 2 2006.201.15:45:09.04#ibcon#*after write, iclass 40, count 2 2006.201.15:45:09.04#ibcon#*before return 0, iclass 40, count 2 2006.201.15:45:09.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:09.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.15:45:09.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.15:45:09.04#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:09.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:09.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:09.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:09.16#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:45:09.16#ibcon#first serial, iclass 40, count 0 2006.201.15:45:09.16#ibcon#enter sib2, iclass 40, count 0 2006.201.15:45:09.16#ibcon#flushed, iclass 40, count 0 2006.201.15:45:09.16#ibcon#about to write, iclass 40, count 0 2006.201.15:45:09.16#ibcon#wrote, iclass 40, count 0 2006.201.15:45:09.16#ibcon#about to read 3, iclass 40, count 0 2006.201.15:45:09.18#ibcon#read 3, iclass 40, count 0 2006.201.15:45:09.18#ibcon#about to read 4, iclass 40, count 0 2006.201.15:45:09.18#ibcon#read 4, iclass 40, count 0 2006.201.15:45:09.18#ibcon#about to read 5, iclass 40, count 0 2006.201.15:45:09.18#ibcon#read 5, iclass 40, count 0 2006.201.15:45:09.18#ibcon#about to read 6, iclass 40, count 0 2006.201.15:45:09.18#ibcon#read 6, iclass 40, count 0 2006.201.15:45:09.18#ibcon#end of sib2, iclass 40, count 0 2006.201.15:45:09.18#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:45:09.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:45:09.18#ibcon#[27=USB\r\n] 2006.201.15:45:09.18#ibcon#*before write, iclass 40, count 0 2006.201.15:45:09.18#ibcon#enter sib2, iclass 40, count 0 2006.201.15:45:09.18#ibcon#flushed, iclass 40, count 0 2006.201.15:45:09.18#ibcon#about to write, iclass 40, count 0 2006.201.15:45:09.18#ibcon#wrote, iclass 40, count 0 2006.201.15:45:09.18#ibcon#about to read 3, iclass 40, count 0 2006.201.15:45:09.21#ibcon#read 3, iclass 40, count 0 2006.201.15:45:09.21#ibcon#about to read 4, iclass 40, count 0 2006.201.15:45:09.21#ibcon#read 4, iclass 40, count 0 2006.201.15:45:09.21#ibcon#about to read 5, iclass 40, count 0 2006.201.15:45:09.21#ibcon#read 5, iclass 40, count 0 2006.201.15:45:09.21#ibcon#about to read 6, iclass 40, count 0 2006.201.15:45:09.21#ibcon#read 6, iclass 40, count 0 2006.201.15:45:09.21#ibcon#end of sib2, iclass 40, count 0 2006.201.15:45:09.21#ibcon#*after write, iclass 40, count 0 2006.201.15:45:09.21#ibcon#*before return 0, iclass 40, count 0 2006.201.15:45:09.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:09.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.15:45:09.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:45:09.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:45:09.21$vck44/vblo=3,649.99 2006.201.15:45:09.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.15:45:09.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.15:45:09.21#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:09.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:09.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:09.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:09.21#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:45:09.21#ibcon#first serial, iclass 4, count 0 2006.201.15:45:09.21#ibcon#enter sib2, iclass 4, count 0 2006.201.15:45:09.21#ibcon#flushed, iclass 4, count 0 2006.201.15:45:09.21#ibcon#about to write, iclass 4, count 0 2006.201.15:45:09.21#ibcon#wrote, iclass 4, count 0 2006.201.15:45:09.21#ibcon#about to read 3, iclass 4, count 0 2006.201.15:45:09.23#ibcon#read 3, iclass 4, count 0 2006.201.15:45:09.23#ibcon#about to read 4, iclass 4, count 0 2006.201.15:45:09.23#ibcon#read 4, iclass 4, count 0 2006.201.15:45:09.23#ibcon#about to read 5, iclass 4, count 0 2006.201.15:45:09.23#ibcon#read 5, iclass 4, count 0 2006.201.15:45:09.23#ibcon#about to read 6, iclass 4, count 0 2006.201.15:45:09.23#ibcon#read 6, iclass 4, count 0 2006.201.15:45:09.23#ibcon#end of sib2, iclass 4, count 0 2006.201.15:45:09.23#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:45:09.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:45:09.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:45:09.23#ibcon#*before write, iclass 4, count 0 2006.201.15:45:09.23#ibcon#enter sib2, iclass 4, count 0 2006.201.15:45:09.23#ibcon#flushed, iclass 4, count 0 2006.201.15:45:09.23#ibcon#about to write, iclass 4, count 0 2006.201.15:45:09.23#ibcon#wrote, iclass 4, count 0 2006.201.15:45:09.23#ibcon#about to read 3, iclass 4, count 0 2006.201.15:45:09.27#ibcon#read 3, iclass 4, count 0 2006.201.15:45:09.27#ibcon#about to read 4, iclass 4, count 0 2006.201.15:45:09.27#ibcon#read 4, iclass 4, count 0 2006.201.15:45:09.27#ibcon#about to read 5, iclass 4, count 0 2006.201.15:45:09.27#ibcon#read 5, iclass 4, count 0 2006.201.15:45:09.27#ibcon#about to read 6, iclass 4, count 0 2006.201.15:45:09.27#ibcon#read 6, iclass 4, count 0 2006.201.15:45:09.27#ibcon#end of sib2, iclass 4, count 0 2006.201.15:45:09.27#ibcon#*after write, iclass 4, count 0 2006.201.15:45:09.27#ibcon#*before return 0, iclass 4, count 0 2006.201.15:45:09.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:09.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.15:45:09.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:45:09.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:45:09.27$vck44/vb=3,4 2006.201.15:45:09.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.15:45:09.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.15:45:09.27#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:09.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:09.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:09.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:09.33#ibcon#enter wrdev, iclass 6, count 2 2006.201.15:45:09.33#ibcon#first serial, iclass 6, count 2 2006.201.15:45:09.33#ibcon#enter sib2, iclass 6, count 2 2006.201.15:45:09.33#ibcon#flushed, iclass 6, count 2 2006.201.15:45:09.33#ibcon#about to write, iclass 6, count 2 2006.201.15:45:09.33#ibcon#wrote, iclass 6, count 2 2006.201.15:45:09.33#ibcon#about to read 3, iclass 6, count 2 2006.201.15:45:09.35#ibcon#read 3, iclass 6, count 2 2006.201.15:45:09.35#ibcon#about to read 4, iclass 6, count 2 2006.201.15:45:09.35#ibcon#read 4, iclass 6, count 2 2006.201.15:45:09.35#ibcon#about to read 5, iclass 6, count 2 2006.201.15:45:09.35#ibcon#read 5, iclass 6, count 2 2006.201.15:45:09.35#ibcon#about to read 6, iclass 6, count 2 2006.201.15:45:09.35#ibcon#read 6, iclass 6, count 2 2006.201.15:45:09.35#ibcon#end of sib2, iclass 6, count 2 2006.201.15:45:09.35#ibcon#*mode == 0, iclass 6, count 2 2006.201.15:45:09.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.15:45:09.35#ibcon#[27=AT03-04\r\n] 2006.201.15:45:09.35#ibcon#*before write, iclass 6, count 2 2006.201.15:45:09.35#ibcon#enter sib2, iclass 6, count 2 2006.201.15:45:09.35#ibcon#flushed, iclass 6, count 2 2006.201.15:45:09.35#ibcon#about to write, iclass 6, count 2 2006.201.15:45:09.35#ibcon#wrote, iclass 6, count 2 2006.201.15:45:09.35#ibcon#about to read 3, iclass 6, count 2 2006.201.15:45:09.38#ibcon#read 3, iclass 6, count 2 2006.201.15:45:09.38#ibcon#about to read 4, iclass 6, count 2 2006.201.15:45:09.38#ibcon#read 4, iclass 6, count 2 2006.201.15:45:09.38#ibcon#about to read 5, iclass 6, count 2 2006.201.15:45:09.38#ibcon#read 5, iclass 6, count 2 2006.201.15:45:09.38#ibcon#about to read 6, iclass 6, count 2 2006.201.15:45:09.38#ibcon#read 6, iclass 6, count 2 2006.201.15:45:09.38#ibcon#end of sib2, iclass 6, count 2 2006.201.15:45:09.38#ibcon#*after write, iclass 6, count 2 2006.201.15:45:09.38#ibcon#*before return 0, iclass 6, count 2 2006.201.15:45:09.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:09.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.15:45:09.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.15:45:09.38#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:09.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:09.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:09.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:09.50#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:45:09.50#ibcon#first serial, iclass 6, count 0 2006.201.15:45:09.50#ibcon#enter sib2, iclass 6, count 0 2006.201.15:45:09.50#ibcon#flushed, iclass 6, count 0 2006.201.15:45:09.50#ibcon#about to write, iclass 6, count 0 2006.201.15:45:09.50#ibcon#wrote, iclass 6, count 0 2006.201.15:45:09.50#ibcon#about to read 3, iclass 6, count 0 2006.201.15:45:09.52#ibcon#read 3, iclass 6, count 0 2006.201.15:45:09.52#ibcon#about to read 4, iclass 6, count 0 2006.201.15:45:09.52#ibcon#read 4, iclass 6, count 0 2006.201.15:45:09.52#ibcon#about to read 5, iclass 6, count 0 2006.201.15:45:09.52#ibcon#read 5, iclass 6, count 0 2006.201.15:45:09.52#ibcon#about to read 6, iclass 6, count 0 2006.201.15:45:09.52#ibcon#read 6, iclass 6, count 0 2006.201.15:45:09.52#ibcon#end of sib2, iclass 6, count 0 2006.201.15:45:09.52#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:45:09.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:45:09.52#ibcon#[27=USB\r\n] 2006.201.15:45:09.52#ibcon#*before write, iclass 6, count 0 2006.201.15:45:09.52#ibcon#enter sib2, iclass 6, count 0 2006.201.15:45:09.52#ibcon#flushed, iclass 6, count 0 2006.201.15:45:09.52#ibcon#about to write, iclass 6, count 0 2006.201.15:45:09.52#ibcon#wrote, iclass 6, count 0 2006.201.15:45:09.52#ibcon#about to read 3, iclass 6, count 0 2006.201.15:45:09.55#ibcon#read 3, iclass 6, count 0 2006.201.15:45:09.55#ibcon#about to read 4, iclass 6, count 0 2006.201.15:45:09.55#ibcon#read 4, iclass 6, count 0 2006.201.15:45:09.55#ibcon#about to read 5, iclass 6, count 0 2006.201.15:45:09.55#ibcon#read 5, iclass 6, count 0 2006.201.15:45:09.55#ibcon#about to read 6, iclass 6, count 0 2006.201.15:45:09.55#ibcon#read 6, iclass 6, count 0 2006.201.15:45:09.55#ibcon#end of sib2, iclass 6, count 0 2006.201.15:45:09.55#ibcon#*after write, iclass 6, count 0 2006.201.15:45:09.55#ibcon#*before return 0, iclass 6, count 0 2006.201.15:45:09.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:09.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.15:45:09.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:45:09.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:45:09.55$vck44/vblo=4,679.99 2006.201.15:45:09.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.15:45:09.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.15:45:09.55#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:09.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:09.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:09.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:09.55#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:45:09.55#ibcon#first serial, iclass 10, count 0 2006.201.15:45:09.55#ibcon#enter sib2, iclass 10, count 0 2006.201.15:45:09.55#ibcon#flushed, iclass 10, count 0 2006.201.15:45:09.55#ibcon#about to write, iclass 10, count 0 2006.201.15:45:09.55#ibcon#wrote, iclass 10, count 0 2006.201.15:45:09.55#ibcon#about to read 3, iclass 10, count 0 2006.201.15:45:09.57#ibcon#read 3, iclass 10, count 0 2006.201.15:45:09.57#ibcon#about to read 4, iclass 10, count 0 2006.201.15:45:09.57#ibcon#read 4, iclass 10, count 0 2006.201.15:45:09.57#ibcon#about to read 5, iclass 10, count 0 2006.201.15:45:09.57#ibcon#read 5, iclass 10, count 0 2006.201.15:45:09.57#ibcon#about to read 6, iclass 10, count 0 2006.201.15:45:09.57#ibcon#read 6, iclass 10, count 0 2006.201.15:45:09.57#ibcon#end of sib2, iclass 10, count 0 2006.201.15:45:09.57#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:45:09.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:45:09.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:45:09.57#ibcon#*before write, iclass 10, count 0 2006.201.15:45:09.57#ibcon#enter sib2, iclass 10, count 0 2006.201.15:45:09.57#ibcon#flushed, iclass 10, count 0 2006.201.15:45:09.57#ibcon#about to write, iclass 10, count 0 2006.201.15:45:09.57#ibcon#wrote, iclass 10, count 0 2006.201.15:45:09.57#ibcon#about to read 3, iclass 10, count 0 2006.201.15:45:09.61#ibcon#read 3, iclass 10, count 0 2006.201.15:45:09.61#ibcon#about to read 4, iclass 10, count 0 2006.201.15:45:09.61#ibcon#read 4, iclass 10, count 0 2006.201.15:45:09.61#ibcon#about to read 5, iclass 10, count 0 2006.201.15:45:09.61#ibcon#read 5, iclass 10, count 0 2006.201.15:45:09.61#ibcon#about to read 6, iclass 10, count 0 2006.201.15:45:09.61#ibcon#read 6, iclass 10, count 0 2006.201.15:45:09.61#ibcon#end of sib2, iclass 10, count 0 2006.201.15:45:09.61#ibcon#*after write, iclass 10, count 0 2006.201.15:45:09.61#ibcon#*before return 0, iclass 10, count 0 2006.201.15:45:09.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:09.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.15:45:09.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:45:09.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:45:09.61$vck44/vb=4,5 2006.201.15:45:09.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.15:45:09.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.15:45:09.61#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:09.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:09.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:09.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:09.67#ibcon#enter wrdev, iclass 12, count 2 2006.201.15:45:09.67#ibcon#first serial, iclass 12, count 2 2006.201.15:45:09.67#ibcon#enter sib2, iclass 12, count 2 2006.201.15:45:09.67#ibcon#flushed, iclass 12, count 2 2006.201.15:45:09.67#ibcon#about to write, iclass 12, count 2 2006.201.15:45:09.67#ibcon#wrote, iclass 12, count 2 2006.201.15:45:09.67#ibcon#about to read 3, iclass 12, count 2 2006.201.15:45:09.69#ibcon#read 3, iclass 12, count 2 2006.201.15:45:09.69#ibcon#about to read 4, iclass 12, count 2 2006.201.15:45:09.69#ibcon#read 4, iclass 12, count 2 2006.201.15:45:09.69#ibcon#about to read 5, iclass 12, count 2 2006.201.15:45:09.69#ibcon#read 5, iclass 12, count 2 2006.201.15:45:09.69#ibcon#about to read 6, iclass 12, count 2 2006.201.15:45:09.69#ibcon#read 6, iclass 12, count 2 2006.201.15:45:09.69#ibcon#end of sib2, iclass 12, count 2 2006.201.15:45:09.69#ibcon#*mode == 0, iclass 12, count 2 2006.201.15:45:09.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.15:45:09.69#ibcon#[27=AT04-05\r\n] 2006.201.15:45:09.69#ibcon#*before write, iclass 12, count 2 2006.201.15:45:09.69#ibcon#enter sib2, iclass 12, count 2 2006.201.15:45:09.69#ibcon#flushed, iclass 12, count 2 2006.201.15:45:09.69#ibcon#about to write, iclass 12, count 2 2006.201.15:45:09.69#ibcon#wrote, iclass 12, count 2 2006.201.15:45:09.69#ibcon#about to read 3, iclass 12, count 2 2006.201.15:45:09.72#ibcon#read 3, iclass 12, count 2 2006.201.15:45:09.72#ibcon#about to read 4, iclass 12, count 2 2006.201.15:45:09.72#ibcon#read 4, iclass 12, count 2 2006.201.15:45:09.72#ibcon#about to read 5, iclass 12, count 2 2006.201.15:45:09.72#ibcon#read 5, iclass 12, count 2 2006.201.15:45:09.72#ibcon#about to read 6, iclass 12, count 2 2006.201.15:45:09.72#ibcon#read 6, iclass 12, count 2 2006.201.15:45:09.72#ibcon#end of sib2, iclass 12, count 2 2006.201.15:45:09.72#ibcon#*after write, iclass 12, count 2 2006.201.15:45:09.72#ibcon#*before return 0, iclass 12, count 2 2006.201.15:45:09.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:09.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.15:45:09.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.15:45:09.72#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:09.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:09.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:09.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:09.84#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:45:09.84#ibcon#first serial, iclass 12, count 0 2006.201.15:45:09.84#ibcon#enter sib2, iclass 12, count 0 2006.201.15:45:09.84#ibcon#flushed, iclass 12, count 0 2006.201.15:45:09.84#ibcon#about to write, iclass 12, count 0 2006.201.15:45:09.84#ibcon#wrote, iclass 12, count 0 2006.201.15:45:09.84#ibcon#about to read 3, iclass 12, count 0 2006.201.15:45:09.86#ibcon#read 3, iclass 12, count 0 2006.201.15:45:09.86#ibcon#about to read 4, iclass 12, count 0 2006.201.15:45:09.86#ibcon#read 4, iclass 12, count 0 2006.201.15:45:09.86#ibcon#about to read 5, iclass 12, count 0 2006.201.15:45:09.86#ibcon#read 5, iclass 12, count 0 2006.201.15:45:09.86#ibcon#about to read 6, iclass 12, count 0 2006.201.15:45:09.86#ibcon#read 6, iclass 12, count 0 2006.201.15:45:09.86#ibcon#end of sib2, iclass 12, count 0 2006.201.15:45:09.86#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:45:09.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:45:09.86#ibcon#[27=USB\r\n] 2006.201.15:45:09.86#ibcon#*before write, iclass 12, count 0 2006.201.15:45:09.86#ibcon#enter sib2, iclass 12, count 0 2006.201.15:45:09.86#ibcon#flushed, iclass 12, count 0 2006.201.15:45:09.86#ibcon#about to write, iclass 12, count 0 2006.201.15:45:09.86#ibcon#wrote, iclass 12, count 0 2006.201.15:45:09.86#ibcon#about to read 3, iclass 12, count 0 2006.201.15:45:09.89#ibcon#read 3, iclass 12, count 0 2006.201.15:45:09.89#ibcon#about to read 4, iclass 12, count 0 2006.201.15:45:09.89#ibcon#read 4, iclass 12, count 0 2006.201.15:45:09.89#ibcon#about to read 5, iclass 12, count 0 2006.201.15:45:09.89#ibcon#read 5, iclass 12, count 0 2006.201.15:45:09.89#ibcon#about to read 6, iclass 12, count 0 2006.201.15:45:09.89#ibcon#read 6, iclass 12, count 0 2006.201.15:45:09.89#ibcon#end of sib2, iclass 12, count 0 2006.201.15:45:09.89#ibcon#*after write, iclass 12, count 0 2006.201.15:45:09.89#ibcon#*before return 0, iclass 12, count 0 2006.201.15:45:09.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:09.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.15:45:09.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:45:09.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:45:09.89$vck44/vblo=5,709.99 2006.201.15:45:09.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.15:45:09.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.15:45:09.89#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:09.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:09.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:09.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:09.89#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:45:09.89#ibcon#first serial, iclass 14, count 0 2006.201.15:45:09.89#ibcon#enter sib2, iclass 14, count 0 2006.201.15:45:09.89#ibcon#flushed, iclass 14, count 0 2006.201.15:45:09.89#ibcon#about to write, iclass 14, count 0 2006.201.15:45:09.89#ibcon#wrote, iclass 14, count 0 2006.201.15:45:09.89#ibcon#about to read 3, iclass 14, count 0 2006.201.15:45:09.91#ibcon#read 3, iclass 14, count 0 2006.201.15:45:09.91#ibcon#about to read 4, iclass 14, count 0 2006.201.15:45:09.91#ibcon#read 4, iclass 14, count 0 2006.201.15:45:09.91#ibcon#about to read 5, iclass 14, count 0 2006.201.15:45:09.91#ibcon#read 5, iclass 14, count 0 2006.201.15:45:09.91#ibcon#about to read 6, iclass 14, count 0 2006.201.15:45:09.91#ibcon#read 6, iclass 14, count 0 2006.201.15:45:09.91#ibcon#end of sib2, iclass 14, count 0 2006.201.15:45:09.91#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:45:09.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:45:09.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:45:09.91#ibcon#*before write, iclass 14, count 0 2006.201.15:45:09.91#ibcon#enter sib2, iclass 14, count 0 2006.201.15:45:09.91#ibcon#flushed, iclass 14, count 0 2006.201.15:45:09.91#ibcon#about to write, iclass 14, count 0 2006.201.15:45:09.91#ibcon#wrote, iclass 14, count 0 2006.201.15:45:09.91#ibcon#about to read 3, iclass 14, count 0 2006.201.15:45:09.95#ibcon#read 3, iclass 14, count 0 2006.201.15:45:09.95#ibcon#about to read 4, iclass 14, count 0 2006.201.15:45:09.95#ibcon#read 4, iclass 14, count 0 2006.201.15:45:09.95#ibcon#about to read 5, iclass 14, count 0 2006.201.15:45:09.95#ibcon#read 5, iclass 14, count 0 2006.201.15:45:09.95#ibcon#about to read 6, iclass 14, count 0 2006.201.15:45:09.95#ibcon#read 6, iclass 14, count 0 2006.201.15:45:09.95#ibcon#end of sib2, iclass 14, count 0 2006.201.15:45:09.95#ibcon#*after write, iclass 14, count 0 2006.201.15:45:09.95#ibcon#*before return 0, iclass 14, count 0 2006.201.15:45:09.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:09.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.15:45:09.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:45:09.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:45:09.95$vck44/vb=5,4 2006.201.15:45:09.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.15:45:09.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.15:45:09.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:09.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:10.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:10.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:10.01#ibcon#enter wrdev, iclass 16, count 2 2006.201.15:45:10.01#ibcon#first serial, iclass 16, count 2 2006.201.15:45:10.01#ibcon#enter sib2, iclass 16, count 2 2006.201.15:45:10.01#ibcon#flushed, iclass 16, count 2 2006.201.15:45:10.01#ibcon#about to write, iclass 16, count 2 2006.201.15:45:10.01#ibcon#wrote, iclass 16, count 2 2006.201.15:45:10.01#ibcon#about to read 3, iclass 16, count 2 2006.201.15:45:10.03#ibcon#read 3, iclass 16, count 2 2006.201.15:45:10.03#ibcon#about to read 4, iclass 16, count 2 2006.201.15:45:10.03#ibcon#read 4, iclass 16, count 2 2006.201.15:45:10.03#ibcon#about to read 5, iclass 16, count 2 2006.201.15:45:10.03#ibcon#read 5, iclass 16, count 2 2006.201.15:45:10.03#ibcon#about to read 6, iclass 16, count 2 2006.201.15:45:10.03#ibcon#read 6, iclass 16, count 2 2006.201.15:45:10.03#ibcon#end of sib2, iclass 16, count 2 2006.201.15:45:10.03#ibcon#*mode == 0, iclass 16, count 2 2006.201.15:45:10.03#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.15:45:10.03#ibcon#[27=AT05-04\r\n] 2006.201.15:45:10.03#ibcon#*before write, iclass 16, count 2 2006.201.15:45:10.03#ibcon#enter sib2, iclass 16, count 2 2006.201.15:45:10.03#ibcon#flushed, iclass 16, count 2 2006.201.15:45:10.03#ibcon#about to write, iclass 16, count 2 2006.201.15:45:10.03#ibcon#wrote, iclass 16, count 2 2006.201.15:45:10.03#ibcon#about to read 3, iclass 16, count 2 2006.201.15:45:10.06#ibcon#read 3, iclass 16, count 2 2006.201.15:45:10.06#ibcon#about to read 4, iclass 16, count 2 2006.201.15:45:10.06#ibcon#read 4, iclass 16, count 2 2006.201.15:45:10.06#ibcon#about to read 5, iclass 16, count 2 2006.201.15:45:10.06#ibcon#read 5, iclass 16, count 2 2006.201.15:45:10.06#ibcon#about to read 6, iclass 16, count 2 2006.201.15:45:10.06#ibcon#read 6, iclass 16, count 2 2006.201.15:45:10.06#ibcon#end of sib2, iclass 16, count 2 2006.201.15:45:10.06#ibcon#*after write, iclass 16, count 2 2006.201.15:45:10.06#ibcon#*before return 0, iclass 16, count 2 2006.201.15:45:10.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:10.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.15:45:10.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.15:45:10.06#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:10.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:10.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:10.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:10.18#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:45:10.18#ibcon#first serial, iclass 16, count 0 2006.201.15:45:10.18#ibcon#enter sib2, iclass 16, count 0 2006.201.15:45:10.18#ibcon#flushed, iclass 16, count 0 2006.201.15:45:10.18#ibcon#about to write, iclass 16, count 0 2006.201.15:45:10.18#ibcon#wrote, iclass 16, count 0 2006.201.15:45:10.18#ibcon#about to read 3, iclass 16, count 0 2006.201.15:45:10.20#ibcon#read 3, iclass 16, count 0 2006.201.15:45:10.20#ibcon#about to read 4, iclass 16, count 0 2006.201.15:45:10.20#ibcon#read 4, iclass 16, count 0 2006.201.15:45:10.20#ibcon#about to read 5, iclass 16, count 0 2006.201.15:45:10.20#ibcon#read 5, iclass 16, count 0 2006.201.15:45:10.20#ibcon#about to read 6, iclass 16, count 0 2006.201.15:45:10.20#ibcon#read 6, iclass 16, count 0 2006.201.15:45:10.20#ibcon#end of sib2, iclass 16, count 0 2006.201.15:45:10.20#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:45:10.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:45:10.20#ibcon#[27=USB\r\n] 2006.201.15:45:10.20#ibcon#*before write, iclass 16, count 0 2006.201.15:45:10.20#ibcon#enter sib2, iclass 16, count 0 2006.201.15:45:10.20#ibcon#flushed, iclass 16, count 0 2006.201.15:45:10.20#ibcon#about to write, iclass 16, count 0 2006.201.15:45:10.20#ibcon#wrote, iclass 16, count 0 2006.201.15:45:10.20#ibcon#about to read 3, iclass 16, count 0 2006.201.15:45:10.23#ibcon#read 3, iclass 16, count 0 2006.201.15:45:10.23#ibcon#about to read 4, iclass 16, count 0 2006.201.15:45:10.23#ibcon#read 4, iclass 16, count 0 2006.201.15:45:10.23#ibcon#about to read 5, iclass 16, count 0 2006.201.15:45:10.23#ibcon#read 5, iclass 16, count 0 2006.201.15:45:10.23#ibcon#about to read 6, iclass 16, count 0 2006.201.15:45:10.23#ibcon#read 6, iclass 16, count 0 2006.201.15:45:10.23#ibcon#end of sib2, iclass 16, count 0 2006.201.15:45:10.23#ibcon#*after write, iclass 16, count 0 2006.201.15:45:10.23#ibcon#*before return 0, iclass 16, count 0 2006.201.15:45:10.23#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:10.23#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.15:45:10.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:45:10.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:45:10.23$vck44/vblo=6,719.99 2006.201.15:45:10.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.15:45:10.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.15:45:10.23#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:10.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:10.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:10.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:10.23#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:45:10.23#ibcon#first serial, iclass 18, count 0 2006.201.15:45:10.23#ibcon#enter sib2, iclass 18, count 0 2006.201.15:45:10.23#ibcon#flushed, iclass 18, count 0 2006.201.15:45:10.23#ibcon#about to write, iclass 18, count 0 2006.201.15:45:10.23#ibcon#wrote, iclass 18, count 0 2006.201.15:45:10.23#ibcon#about to read 3, iclass 18, count 0 2006.201.15:45:10.25#ibcon#read 3, iclass 18, count 0 2006.201.15:45:10.25#ibcon#about to read 4, iclass 18, count 0 2006.201.15:45:10.25#ibcon#read 4, iclass 18, count 0 2006.201.15:45:10.25#ibcon#about to read 5, iclass 18, count 0 2006.201.15:45:10.25#ibcon#read 5, iclass 18, count 0 2006.201.15:45:10.25#ibcon#about to read 6, iclass 18, count 0 2006.201.15:45:10.25#ibcon#read 6, iclass 18, count 0 2006.201.15:45:10.25#ibcon#end of sib2, iclass 18, count 0 2006.201.15:45:10.25#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:45:10.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:45:10.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:45:10.25#ibcon#*before write, iclass 18, count 0 2006.201.15:45:10.25#ibcon#enter sib2, iclass 18, count 0 2006.201.15:45:10.25#ibcon#flushed, iclass 18, count 0 2006.201.15:45:10.25#ibcon#about to write, iclass 18, count 0 2006.201.15:45:10.25#ibcon#wrote, iclass 18, count 0 2006.201.15:45:10.25#ibcon#about to read 3, iclass 18, count 0 2006.201.15:45:10.29#ibcon#read 3, iclass 18, count 0 2006.201.15:45:10.29#ibcon#about to read 4, iclass 18, count 0 2006.201.15:45:10.29#ibcon#read 4, iclass 18, count 0 2006.201.15:45:10.29#ibcon#about to read 5, iclass 18, count 0 2006.201.15:45:10.29#ibcon#read 5, iclass 18, count 0 2006.201.15:45:10.29#ibcon#about to read 6, iclass 18, count 0 2006.201.15:45:10.29#ibcon#read 6, iclass 18, count 0 2006.201.15:45:10.29#ibcon#end of sib2, iclass 18, count 0 2006.201.15:45:10.29#ibcon#*after write, iclass 18, count 0 2006.201.15:45:10.29#ibcon#*before return 0, iclass 18, count 0 2006.201.15:45:10.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:10.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.15:45:10.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:45:10.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:45:10.29$vck44/vb=6,4 2006.201.15:45:10.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.15:45:10.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.15:45:10.29#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:10.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:10.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:10.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:10.35#ibcon#enter wrdev, iclass 20, count 2 2006.201.15:45:10.35#ibcon#first serial, iclass 20, count 2 2006.201.15:45:10.35#ibcon#enter sib2, iclass 20, count 2 2006.201.15:45:10.35#ibcon#flushed, iclass 20, count 2 2006.201.15:45:10.35#ibcon#about to write, iclass 20, count 2 2006.201.15:45:10.35#ibcon#wrote, iclass 20, count 2 2006.201.15:45:10.35#ibcon#about to read 3, iclass 20, count 2 2006.201.15:45:10.37#ibcon#read 3, iclass 20, count 2 2006.201.15:45:10.37#ibcon#about to read 4, iclass 20, count 2 2006.201.15:45:10.37#ibcon#read 4, iclass 20, count 2 2006.201.15:45:10.37#ibcon#about to read 5, iclass 20, count 2 2006.201.15:45:10.37#ibcon#read 5, iclass 20, count 2 2006.201.15:45:10.37#ibcon#about to read 6, iclass 20, count 2 2006.201.15:45:10.37#ibcon#read 6, iclass 20, count 2 2006.201.15:45:10.37#ibcon#end of sib2, iclass 20, count 2 2006.201.15:45:10.37#ibcon#*mode == 0, iclass 20, count 2 2006.201.15:45:10.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.15:45:10.37#ibcon#[27=AT06-04\r\n] 2006.201.15:45:10.37#ibcon#*before write, iclass 20, count 2 2006.201.15:45:10.37#ibcon#enter sib2, iclass 20, count 2 2006.201.15:45:10.37#ibcon#flushed, iclass 20, count 2 2006.201.15:45:10.37#ibcon#about to write, iclass 20, count 2 2006.201.15:45:10.37#ibcon#wrote, iclass 20, count 2 2006.201.15:45:10.37#ibcon#about to read 3, iclass 20, count 2 2006.201.15:45:10.41#ibcon#read 3, iclass 20, count 2 2006.201.15:45:10.41#ibcon#about to read 4, iclass 20, count 2 2006.201.15:45:10.41#ibcon#read 4, iclass 20, count 2 2006.201.15:45:10.41#ibcon#about to read 5, iclass 20, count 2 2006.201.15:45:10.41#ibcon#read 5, iclass 20, count 2 2006.201.15:45:10.41#ibcon#about to read 6, iclass 20, count 2 2006.201.15:45:10.41#ibcon#read 6, iclass 20, count 2 2006.201.15:45:10.41#ibcon#end of sib2, iclass 20, count 2 2006.201.15:45:10.41#ibcon#*after write, iclass 20, count 2 2006.201.15:45:10.41#ibcon#*before return 0, iclass 20, count 2 2006.201.15:45:10.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:10.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.15:45:10.41#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.15:45:10.41#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:10.41#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:10.53#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:10.53#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:10.53#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:45:10.53#ibcon#first serial, iclass 20, count 0 2006.201.15:45:10.53#ibcon#enter sib2, iclass 20, count 0 2006.201.15:45:10.53#ibcon#flushed, iclass 20, count 0 2006.201.15:45:10.53#ibcon#about to write, iclass 20, count 0 2006.201.15:45:10.53#ibcon#wrote, iclass 20, count 0 2006.201.15:45:10.53#ibcon#about to read 3, iclass 20, count 0 2006.201.15:45:10.55#ibcon#read 3, iclass 20, count 0 2006.201.15:45:10.55#ibcon#about to read 4, iclass 20, count 0 2006.201.15:45:10.55#ibcon#read 4, iclass 20, count 0 2006.201.15:45:10.55#ibcon#about to read 5, iclass 20, count 0 2006.201.15:45:10.55#ibcon#read 5, iclass 20, count 0 2006.201.15:45:10.55#ibcon#about to read 6, iclass 20, count 0 2006.201.15:45:10.55#ibcon#read 6, iclass 20, count 0 2006.201.15:45:10.55#ibcon#end of sib2, iclass 20, count 0 2006.201.15:45:10.55#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:45:10.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:45:10.55#ibcon#[27=USB\r\n] 2006.201.15:45:10.55#ibcon#*before write, iclass 20, count 0 2006.201.15:45:10.55#ibcon#enter sib2, iclass 20, count 0 2006.201.15:45:10.55#ibcon#flushed, iclass 20, count 0 2006.201.15:45:10.55#ibcon#about to write, iclass 20, count 0 2006.201.15:45:10.55#ibcon#wrote, iclass 20, count 0 2006.201.15:45:10.55#ibcon#about to read 3, iclass 20, count 0 2006.201.15:45:10.58#ibcon#read 3, iclass 20, count 0 2006.201.15:45:10.58#ibcon#about to read 4, iclass 20, count 0 2006.201.15:45:10.58#ibcon#read 4, iclass 20, count 0 2006.201.15:45:10.58#ibcon#about to read 5, iclass 20, count 0 2006.201.15:45:10.58#ibcon#read 5, iclass 20, count 0 2006.201.15:45:10.58#ibcon#about to read 6, iclass 20, count 0 2006.201.15:45:10.58#ibcon#read 6, iclass 20, count 0 2006.201.15:45:10.58#ibcon#end of sib2, iclass 20, count 0 2006.201.15:45:10.58#ibcon#*after write, iclass 20, count 0 2006.201.15:45:10.58#ibcon#*before return 0, iclass 20, count 0 2006.201.15:45:10.58#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:10.58#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.15:45:10.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:45:10.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:45:10.58$vck44/vblo=7,734.99 2006.201.15:45:10.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.15:45:10.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.15:45:10.58#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:10.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:10.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:10.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:10.58#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:45:10.58#ibcon#first serial, iclass 22, count 0 2006.201.15:45:10.58#ibcon#enter sib2, iclass 22, count 0 2006.201.15:45:10.58#ibcon#flushed, iclass 22, count 0 2006.201.15:45:10.58#ibcon#about to write, iclass 22, count 0 2006.201.15:45:10.58#ibcon#wrote, iclass 22, count 0 2006.201.15:45:10.58#ibcon#about to read 3, iclass 22, count 0 2006.201.15:45:10.60#ibcon#read 3, iclass 22, count 0 2006.201.15:45:10.60#ibcon#about to read 4, iclass 22, count 0 2006.201.15:45:10.60#ibcon#read 4, iclass 22, count 0 2006.201.15:45:10.60#ibcon#about to read 5, iclass 22, count 0 2006.201.15:45:10.60#ibcon#read 5, iclass 22, count 0 2006.201.15:45:10.60#ibcon#about to read 6, iclass 22, count 0 2006.201.15:45:10.60#ibcon#read 6, iclass 22, count 0 2006.201.15:45:10.60#ibcon#end of sib2, iclass 22, count 0 2006.201.15:45:10.60#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:45:10.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:45:10.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:45:10.60#ibcon#*before write, iclass 22, count 0 2006.201.15:45:10.60#ibcon#enter sib2, iclass 22, count 0 2006.201.15:45:10.60#ibcon#flushed, iclass 22, count 0 2006.201.15:45:10.60#ibcon#about to write, iclass 22, count 0 2006.201.15:45:10.60#ibcon#wrote, iclass 22, count 0 2006.201.15:45:10.60#ibcon#about to read 3, iclass 22, count 0 2006.201.15:45:10.64#ibcon#read 3, iclass 22, count 0 2006.201.15:45:10.64#ibcon#about to read 4, iclass 22, count 0 2006.201.15:45:10.64#ibcon#read 4, iclass 22, count 0 2006.201.15:45:10.64#ibcon#about to read 5, iclass 22, count 0 2006.201.15:45:10.64#ibcon#read 5, iclass 22, count 0 2006.201.15:45:10.64#ibcon#about to read 6, iclass 22, count 0 2006.201.15:45:10.64#ibcon#read 6, iclass 22, count 0 2006.201.15:45:10.64#ibcon#end of sib2, iclass 22, count 0 2006.201.15:45:10.64#ibcon#*after write, iclass 22, count 0 2006.201.15:45:10.64#ibcon#*before return 0, iclass 22, count 0 2006.201.15:45:10.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:10.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.15:45:10.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:45:10.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:45:10.64$vck44/vb=7,4 2006.201.15:45:10.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.15:45:10.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.15:45:10.64#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:10.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:10.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:10.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:10.70#ibcon#enter wrdev, iclass 24, count 2 2006.201.15:45:10.70#ibcon#first serial, iclass 24, count 2 2006.201.15:45:10.70#ibcon#enter sib2, iclass 24, count 2 2006.201.15:45:10.70#ibcon#flushed, iclass 24, count 2 2006.201.15:45:10.70#ibcon#about to write, iclass 24, count 2 2006.201.15:45:10.70#ibcon#wrote, iclass 24, count 2 2006.201.15:45:10.70#ibcon#about to read 3, iclass 24, count 2 2006.201.15:45:10.72#ibcon#read 3, iclass 24, count 2 2006.201.15:45:10.72#ibcon#about to read 4, iclass 24, count 2 2006.201.15:45:10.72#ibcon#read 4, iclass 24, count 2 2006.201.15:45:10.72#ibcon#about to read 5, iclass 24, count 2 2006.201.15:45:10.72#ibcon#read 5, iclass 24, count 2 2006.201.15:45:10.72#ibcon#about to read 6, iclass 24, count 2 2006.201.15:45:10.72#ibcon#read 6, iclass 24, count 2 2006.201.15:45:10.72#ibcon#end of sib2, iclass 24, count 2 2006.201.15:45:10.72#ibcon#*mode == 0, iclass 24, count 2 2006.201.15:45:10.72#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.15:45:10.72#ibcon#[27=AT07-04\r\n] 2006.201.15:45:10.72#ibcon#*before write, iclass 24, count 2 2006.201.15:45:10.72#ibcon#enter sib2, iclass 24, count 2 2006.201.15:45:10.72#ibcon#flushed, iclass 24, count 2 2006.201.15:45:10.72#ibcon#about to write, iclass 24, count 2 2006.201.15:45:10.72#ibcon#wrote, iclass 24, count 2 2006.201.15:45:10.72#ibcon#about to read 3, iclass 24, count 2 2006.201.15:45:10.75#ibcon#read 3, iclass 24, count 2 2006.201.15:45:10.75#ibcon#about to read 4, iclass 24, count 2 2006.201.15:45:10.75#ibcon#read 4, iclass 24, count 2 2006.201.15:45:10.75#ibcon#about to read 5, iclass 24, count 2 2006.201.15:45:10.75#ibcon#read 5, iclass 24, count 2 2006.201.15:45:10.75#ibcon#about to read 6, iclass 24, count 2 2006.201.15:45:10.75#ibcon#read 6, iclass 24, count 2 2006.201.15:45:10.75#ibcon#end of sib2, iclass 24, count 2 2006.201.15:45:10.75#ibcon#*after write, iclass 24, count 2 2006.201.15:45:10.75#ibcon#*before return 0, iclass 24, count 2 2006.201.15:45:10.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:10.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.15:45:10.75#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.15:45:10.75#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:10.75#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:10.87#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:10.87#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:10.87#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:45:10.87#ibcon#first serial, iclass 24, count 0 2006.201.15:45:10.87#ibcon#enter sib2, iclass 24, count 0 2006.201.15:45:10.87#ibcon#flushed, iclass 24, count 0 2006.201.15:45:10.87#ibcon#about to write, iclass 24, count 0 2006.201.15:45:10.87#ibcon#wrote, iclass 24, count 0 2006.201.15:45:10.87#ibcon#about to read 3, iclass 24, count 0 2006.201.15:45:10.89#ibcon#read 3, iclass 24, count 0 2006.201.15:45:10.89#ibcon#about to read 4, iclass 24, count 0 2006.201.15:45:10.89#ibcon#read 4, iclass 24, count 0 2006.201.15:45:10.89#ibcon#about to read 5, iclass 24, count 0 2006.201.15:45:10.89#ibcon#read 5, iclass 24, count 0 2006.201.15:45:10.89#ibcon#about to read 6, iclass 24, count 0 2006.201.15:45:10.89#ibcon#read 6, iclass 24, count 0 2006.201.15:45:10.89#ibcon#end of sib2, iclass 24, count 0 2006.201.15:45:10.89#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:45:10.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:45:10.89#ibcon#[27=USB\r\n] 2006.201.15:45:10.89#ibcon#*before write, iclass 24, count 0 2006.201.15:45:10.89#ibcon#enter sib2, iclass 24, count 0 2006.201.15:45:10.89#ibcon#flushed, iclass 24, count 0 2006.201.15:45:10.89#ibcon#about to write, iclass 24, count 0 2006.201.15:45:10.89#ibcon#wrote, iclass 24, count 0 2006.201.15:45:10.89#ibcon#about to read 3, iclass 24, count 0 2006.201.15:45:10.92#ibcon#read 3, iclass 24, count 0 2006.201.15:45:10.92#ibcon#about to read 4, iclass 24, count 0 2006.201.15:45:10.92#ibcon#read 4, iclass 24, count 0 2006.201.15:45:10.92#ibcon#about to read 5, iclass 24, count 0 2006.201.15:45:10.92#ibcon#read 5, iclass 24, count 0 2006.201.15:45:10.92#ibcon#about to read 6, iclass 24, count 0 2006.201.15:45:10.92#ibcon#read 6, iclass 24, count 0 2006.201.15:45:10.92#ibcon#end of sib2, iclass 24, count 0 2006.201.15:45:10.92#ibcon#*after write, iclass 24, count 0 2006.201.15:45:10.92#ibcon#*before return 0, iclass 24, count 0 2006.201.15:45:10.92#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:10.92#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.15:45:10.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:45:10.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:45:10.92$vck44/vblo=8,744.99 2006.201.15:45:10.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.15:45:10.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.15:45:10.92#ibcon#ireg 17 cls_cnt 0 2006.201.15:45:10.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:10.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:10.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:10.92#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:45:10.92#ibcon#first serial, iclass 26, count 0 2006.201.15:45:10.92#ibcon#enter sib2, iclass 26, count 0 2006.201.15:45:10.92#ibcon#flushed, iclass 26, count 0 2006.201.15:45:10.92#ibcon#about to write, iclass 26, count 0 2006.201.15:45:10.92#ibcon#wrote, iclass 26, count 0 2006.201.15:45:10.92#ibcon#about to read 3, iclass 26, count 0 2006.201.15:45:10.94#ibcon#read 3, iclass 26, count 0 2006.201.15:45:10.94#ibcon#about to read 4, iclass 26, count 0 2006.201.15:45:10.94#ibcon#read 4, iclass 26, count 0 2006.201.15:45:10.94#ibcon#about to read 5, iclass 26, count 0 2006.201.15:45:10.94#ibcon#read 5, iclass 26, count 0 2006.201.15:45:10.94#ibcon#about to read 6, iclass 26, count 0 2006.201.15:45:10.94#ibcon#read 6, iclass 26, count 0 2006.201.15:45:10.94#ibcon#end of sib2, iclass 26, count 0 2006.201.15:45:10.94#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:45:10.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:45:10.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:45:10.94#ibcon#*before write, iclass 26, count 0 2006.201.15:45:10.94#ibcon#enter sib2, iclass 26, count 0 2006.201.15:45:10.94#ibcon#flushed, iclass 26, count 0 2006.201.15:45:10.94#ibcon#about to write, iclass 26, count 0 2006.201.15:45:10.94#ibcon#wrote, iclass 26, count 0 2006.201.15:45:10.94#ibcon#about to read 3, iclass 26, count 0 2006.201.15:45:10.98#ibcon#read 3, iclass 26, count 0 2006.201.15:45:10.98#ibcon#about to read 4, iclass 26, count 0 2006.201.15:45:10.98#ibcon#read 4, iclass 26, count 0 2006.201.15:45:10.98#ibcon#about to read 5, iclass 26, count 0 2006.201.15:45:10.98#ibcon#read 5, iclass 26, count 0 2006.201.15:45:10.98#ibcon#about to read 6, iclass 26, count 0 2006.201.15:45:10.98#ibcon#read 6, iclass 26, count 0 2006.201.15:45:10.98#ibcon#end of sib2, iclass 26, count 0 2006.201.15:45:10.98#ibcon#*after write, iclass 26, count 0 2006.201.15:45:10.98#ibcon#*before return 0, iclass 26, count 0 2006.201.15:45:10.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:10.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.15:45:10.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:45:10.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:45:10.98$vck44/vb=8,4 2006.201.15:45:10.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.15:45:10.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.15:45:10.98#ibcon#ireg 11 cls_cnt 2 2006.201.15:45:10.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:11.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:11.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:11.04#ibcon#enter wrdev, iclass 28, count 2 2006.201.15:45:11.04#ibcon#first serial, iclass 28, count 2 2006.201.15:45:11.04#ibcon#enter sib2, iclass 28, count 2 2006.201.15:45:11.04#ibcon#flushed, iclass 28, count 2 2006.201.15:45:11.04#ibcon#about to write, iclass 28, count 2 2006.201.15:45:11.04#ibcon#wrote, iclass 28, count 2 2006.201.15:45:11.04#ibcon#about to read 3, iclass 28, count 2 2006.201.15:45:11.06#ibcon#read 3, iclass 28, count 2 2006.201.15:45:11.06#ibcon#about to read 4, iclass 28, count 2 2006.201.15:45:11.06#ibcon#read 4, iclass 28, count 2 2006.201.15:45:11.06#ibcon#about to read 5, iclass 28, count 2 2006.201.15:45:11.06#ibcon#read 5, iclass 28, count 2 2006.201.15:45:11.06#ibcon#about to read 6, iclass 28, count 2 2006.201.15:45:11.06#ibcon#read 6, iclass 28, count 2 2006.201.15:45:11.06#ibcon#end of sib2, iclass 28, count 2 2006.201.15:45:11.06#ibcon#*mode == 0, iclass 28, count 2 2006.201.15:45:11.06#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.15:45:11.06#ibcon#[27=AT08-04\r\n] 2006.201.15:45:11.06#ibcon#*before write, iclass 28, count 2 2006.201.15:45:11.06#ibcon#enter sib2, iclass 28, count 2 2006.201.15:45:11.06#ibcon#flushed, iclass 28, count 2 2006.201.15:45:11.06#ibcon#about to write, iclass 28, count 2 2006.201.15:45:11.06#ibcon#wrote, iclass 28, count 2 2006.201.15:45:11.06#ibcon#about to read 3, iclass 28, count 2 2006.201.15:45:11.09#ibcon#read 3, iclass 28, count 2 2006.201.15:45:11.09#ibcon#about to read 4, iclass 28, count 2 2006.201.15:45:11.09#ibcon#read 4, iclass 28, count 2 2006.201.15:45:11.09#ibcon#about to read 5, iclass 28, count 2 2006.201.15:45:11.09#ibcon#read 5, iclass 28, count 2 2006.201.15:45:11.09#ibcon#about to read 6, iclass 28, count 2 2006.201.15:45:11.09#ibcon#read 6, iclass 28, count 2 2006.201.15:45:11.09#ibcon#end of sib2, iclass 28, count 2 2006.201.15:45:11.09#ibcon#*after write, iclass 28, count 2 2006.201.15:45:11.09#ibcon#*before return 0, iclass 28, count 2 2006.201.15:45:11.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:11.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.15:45:11.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.15:45:11.09#ibcon#ireg 7 cls_cnt 0 2006.201.15:45:11.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:11.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:11.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:11.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:45:11.21#ibcon#first serial, iclass 28, count 0 2006.201.15:45:11.21#ibcon#enter sib2, iclass 28, count 0 2006.201.15:45:11.21#ibcon#flushed, iclass 28, count 0 2006.201.15:45:11.21#ibcon#about to write, iclass 28, count 0 2006.201.15:45:11.21#ibcon#wrote, iclass 28, count 0 2006.201.15:45:11.21#ibcon#about to read 3, iclass 28, count 0 2006.201.15:45:11.24#ibcon#read 3, iclass 28, count 0 2006.201.15:45:11.24#ibcon#about to read 4, iclass 28, count 0 2006.201.15:45:11.24#ibcon#read 4, iclass 28, count 0 2006.201.15:45:11.24#ibcon#about to read 5, iclass 28, count 0 2006.201.15:45:11.24#ibcon#read 5, iclass 28, count 0 2006.201.15:45:11.24#ibcon#about to read 6, iclass 28, count 0 2006.201.15:45:11.24#ibcon#read 6, iclass 28, count 0 2006.201.15:45:11.24#ibcon#end of sib2, iclass 28, count 0 2006.201.15:45:11.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:45:11.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:45:11.24#ibcon#[27=USB\r\n] 2006.201.15:45:11.24#ibcon#*before write, iclass 28, count 0 2006.201.15:45:11.24#ibcon#enter sib2, iclass 28, count 0 2006.201.15:45:11.24#ibcon#flushed, iclass 28, count 0 2006.201.15:45:11.24#ibcon#about to write, iclass 28, count 0 2006.201.15:45:11.24#ibcon#wrote, iclass 28, count 0 2006.201.15:45:11.24#ibcon#about to read 3, iclass 28, count 0 2006.201.15:45:11.27#ibcon#read 3, iclass 28, count 0 2006.201.15:45:11.27#ibcon#about to read 4, iclass 28, count 0 2006.201.15:45:11.27#ibcon#read 4, iclass 28, count 0 2006.201.15:45:11.27#ibcon#about to read 5, iclass 28, count 0 2006.201.15:45:11.27#ibcon#read 5, iclass 28, count 0 2006.201.15:45:11.27#ibcon#about to read 6, iclass 28, count 0 2006.201.15:45:11.27#ibcon#read 6, iclass 28, count 0 2006.201.15:45:11.27#ibcon#end of sib2, iclass 28, count 0 2006.201.15:45:11.27#ibcon#*after write, iclass 28, count 0 2006.201.15:45:11.27#ibcon#*before return 0, iclass 28, count 0 2006.201.15:45:11.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:11.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.15:45:11.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:45:11.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:45:11.27$vck44/vabw=wide 2006.201.15:45:11.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.15:45:11.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.15:45:11.27#ibcon#ireg 8 cls_cnt 0 2006.201.15:45:11.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:11.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:11.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:11.27#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:45:11.27#ibcon#first serial, iclass 30, count 0 2006.201.15:45:11.27#ibcon#enter sib2, iclass 30, count 0 2006.201.15:45:11.27#ibcon#flushed, iclass 30, count 0 2006.201.15:45:11.27#ibcon#about to write, iclass 30, count 0 2006.201.15:45:11.27#ibcon#wrote, iclass 30, count 0 2006.201.15:45:11.27#ibcon#about to read 3, iclass 30, count 0 2006.201.15:45:11.29#ibcon#read 3, iclass 30, count 0 2006.201.15:45:11.29#ibcon#about to read 4, iclass 30, count 0 2006.201.15:45:11.29#ibcon#read 4, iclass 30, count 0 2006.201.15:45:11.29#ibcon#about to read 5, iclass 30, count 0 2006.201.15:45:11.29#ibcon#read 5, iclass 30, count 0 2006.201.15:45:11.29#ibcon#about to read 6, iclass 30, count 0 2006.201.15:45:11.29#ibcon#read 6, iclass 30, count 0 2006.201.15:45:11.29#ibcon#end of sib2, iclass 30, count 0 2006.201.15:45:11.29#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:45:11.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:45:11.29#ibcon#[25=BW32\r\n] 2006.201.15:45:11.29#ibcon#*before write, iclass 30, count 0 2006.201.15:45:11.29#ibcon#enter sib2, iclass 30, count 0 2006.201.15:45:11.29#ibcon#flushed, iclass 30, count 0 2006.201.15:45:11.29#ibcon#about to write, iclass 30, count 0 2006.201.15:45:11.29#ibcon#wrote, iclass 30, count 0 2006.201.15:45:11.29#ibcon#about to read 3, iclass 30, count 0 2006.201.15:45:11.32#ibcon#read 3, iclass 30, count 0 2006.201.15:45:11.32#ibcon#about to read 4, iclass 30, count 0 2006.201.15:45:11.32#ibcon#read 4, iclass 30, count 0 2006.201.15:45:11.32#ibcon#about to read 5, iclass 30, count 0 2006.201.15:45:11.32#ibcon#read 5, iclass 30, count 0 2006.201.15:45:11.32#ibcon#about to read 6, iclass 30, count 0 2006.201.15:45:11.32#ibcon#read 6, iclass 30, count 0 2006.201.15:45:11.32#ibcon#end of sib2, iclass 30, count 0 2006.201.15:45:11.32#ibcon#*after write, iclass 30, count 0 2006.201.15:45:11.32#ibcon#*before return 0, iclass 30, count 0 2006.201.15:45:11.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:11.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:45:11.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:45:11.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:45:11.32$vck44/vbbw=wide 2006.201.15:45:11.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.15:45:11.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.15:45:11.32#ibcon#ireg 8 cls_cnt 0 2006.201.15:45:11.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:45:11.34#abcon#<5=/04 1.0 1.7 20.841001002.9\r\n> 2006.201.15:45:11.36#abcon#{5=INTERFACE CLEAR} 2006.201.15:45:11.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:45:11.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:45:11.39#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:45:11.39#ibcon#first serial, iclass 33, count 0 2006.201.15:45:11.39#ibcon#enter sib2, iclass 33, count 0 2006.201.15:45:11.39#ibcon#flushed, iclass 33, count 0 2006.201.15:45:11.39#ibcon#about to write, iclass 33, count 0 2006.201.15:45:11.39#ibcon#wrote, iclass 33, count 0 2006.201.15:45:11.39#ibcon#about to read 3, iclass 33, count 0 2006.201.15:45:11.41#ibcon#read 3, iclass 33, count 0 2006.201.15:45:11.41#ibcon#about to read 4, iclass 33, count 0 2006.201.15:45:11.41#ibcon#read 4, iclass 33, count 0 2006.201.15:45:11.41#ibcon#about to read 5, iclass 33, count 0 2006.201.15:45:11.41#ibcon#read 5, iclass 33, count 0 2006.201.15:45:11.41#ibcon#about to read 6, iclass 33, count 0 2006.201.15:45:11.41#ibcon#read 6, iclass 33, count 0 2006.201.15:45:11.41#ibcon#end of sib2, iclass 33, count 0 2006.201.15:45:11.41#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:45:11.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:45:11.41#ibcon#[27=BW32\r\n] 2006.201.15:45:11.41#ibcon#*before write, iclass 33, count 0 2006.201.15:45:11.41#ibcon#enter sib2, iclass 33, count 0 2006.201.15:45:11.41#ibcon#flushed, iclass 33, count 0 2006.201.15:45:11.41#ibcon#about to write, iclass 33, count 0 2006.201.15:45:11.41#ibcon#wrote, iclass 33, count 0 2006.201.15:45:11.41#ibcon#about to read 3, iclass 33, count 0 2006.201.15:45:11.42#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:45:11.44#ibcon#read 3, iclass 33, count 0 2006.201.15:45:11.44#ibcon#about to read 4, iclass 33, count 0 2006.201.15:45:11.44#ibcon#read 4, iclass 33, count 0 2006.201.15:45:11.44#ibcon#about to read 5, iclass 33, count 0 2006.201.15:45:11.44#ibcon#read 5, iclass 33, count 0 2006.201.15:45:11.44#ibcon#about to read 6, iclass 33, count 0 2006.201.15:45:11.44#ibcon#read 6, iclass 33, count 0 2006.201.15:45:11.44#ibcon#end of sib2, iclass 33, count 0 2006.201.15:45:11.44#ibcon#*after write, iclass 33, count 0 2006.201.15:45:11.44#ibcon#*before return 0, iclass 33, count 0 2006.201.15:45:11.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:45:11.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:45:11.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:45:11.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:45:11.44$setupk4/ifdk4 2006.201.15:45:11.44$ifdk4/lo= 2006.201.15:45:11.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:45:11.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:45:11.44$ifdk4/patch= 2006.201.15:45:11.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:45:11.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:45:11.44$setupk4/!*+20s 2006.201.15:45:21.51#abcon#<5=/04 1.0 1.7 20.841001002.9\r\n> 2006.201.15:45:21.53#abcon#{5=INTERFACE CLEAR} 2006.201.15:45:21.59#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:45:25.90$setupk4/"tpicd 2006.201.15:45:25.90$setupk4/echo=off 2006.201.15:45:25.90$setupk4/xlog=off 2006.201.15:45:25.90:!2006.201.15:48:36 2006.201.15:45:26.14#trakl#Source acquired 2006.201.15:45:28.14#flagr#flagr/antenna,acquired 2006.201.15:48:36.00:preob 2006.201.15:48:36.14/onsource/TRACKING 2006.201.15:48:36.14:!2006.201.15:48:46 2006.201.15:48:46.00:"tape 2006.201.15:48:46.00:"st=record 2006.201.15:48:46.00:data_valid=on 2006.201.15:48:46.00:midob 2006.201.15:48:46.14/onsource/TRACKING 2006.201.15:48:46.14/wx/20.84,1002.8,100 2006.201.15:48:46.24/cable/+6.4767E-03 2006.201.15:48:47.33/va/01,08,usb,yes,30,32 2006.201.15:48:47.33/va/02,07,usb,yes,32,33 2006.201.15:48:47.33/va/03,08,usb,yes,29,30 2006.201.15:48:47.33/va/04,07,usb,yes,33,35 2006.201.15:48:47.33/va/05,04,usb,yes,29,30 2006.201.15:48:47.33/va/06,05,usb,yes,29,29 2006.201.15:48:47.33/va/07,05,usb,yes,28,30 2006.201.15:48:47.33/va/08,04,usb,yes,28,34 2006.201.15:48:47.56/valo/01,524.99,yes,locked 2006.201.15:48:47.56/valo/02,534.99,yes,locked 2006.201.15:48:47.56/valo/03,564.99,yes,locked 2006.201.15:48:47.56/valo/04,624.99,yes,locked 2006.201.15:48:47.56/valo/05,734.99,yes,locked 2006.201.15:48:47.56/valo/06,814.99,yes,locked 2006.201.15:48:47.56/valo/07,864.99,yes,locked 2006.201.15:48:47.56/valo/08,884.99,yes,locked 2006.201.15:48:48.65/vb/01,04,usb,yes,29,27 2006.201.15:48:48.65/vb/02,05,usb,yes,27,27 2006.201.15:48:48.65/vb/03,04,usb,yes,28,31 2006.201.15:48:48.65/vb/04,05,usb,yes,29,28 2006.201.15:48:48.65/vb/05,04,usb,yes,25,28 2006.201.15:48:48.65/vb/06,04,usb,yes,30,26 2006.201.15:48:48.65/vb/07,04,usb,yes,29,29 2006.201.15:48:48.65/vb/08,04,usb,yes,27,30 2006.201.15:48:48.88/vblo/01,629.99,yes,locked 2006.201.15:48:48.88/vblo/02,634.99,yes,locked 2006.201.15:48:48.88/vblo/03,649.99,yes,locked 2006.201.15:48:48.88/vblo/04,679.99,yes,locked 2006.201.15:48:48.88/vblo/05,709.99,yes,locked 2006.201.15:48:48.88/vblo/06,719.99,yes,locked 2006.201.15:48:48.88/vblo/07,734.99,yes,locked 2006.201.15:48:48.88/vblo/08,744.99,yes,locked 2006.201.15:48:49.03/vabw/8 2006.201.15:48:49.18/vbbw/8 2006.201.15:48:49.27/xfe/off,on,15.2 2006.201.15:48:49.65/ifatt/23,28,28,28 2006.201.15:48:50.05/fmout-gps/S +4.49E-07 2006.201.15:48:50.12:!2006.201.15:50:06 2006.201.15:50:06.00:data_valid=off 2006.201.15:50:06.00:"et 2006.201.15:50:06.00:!+3s 2006.201.15:50:09.02:"tape 2006.201.15:50:09.02:postob 2006.201.15:50:09.09/cable/+6.4767E-03 2006.201.15:50:09.09/wx/20.84,1002.8,100 2006.201.15:50:09.16/fmout-gps/S +4.50E-07 2006.201.15:50:09.16:scan_name=201-1553,jd0607,40 2006.201.15:50:09.17:source=1741-038,174358.86,-035004.6,2000.0,cw 2006.201.15:50:10.14#flagr#flagr/antenna,new-source 2006.201.15:50:10.14:checkk5 2006.201.15:50:10.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:50:10.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:50:11.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:50:11.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:50:12.01/chk_obsdata//k5ts1/T2011548??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.15:50:12.37/chk_obsdata//k5ts2/T2011548??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.15:50:12.74/chk_obsdata//k5ts3/T2011548??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.15:50:13.10/chk_obsdata//k5ts4/T2011548??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.15:50:13.79/k5log//k5ts1_log_newline 2006.201.15:50:14.48/k5log//k5ts2_log_newline 2006.201.15:50:15.17/k5log//k5ts3_log_newline 2006.201.15:50:15.85/k5log//k5ts4_log_newline 2006.201.15:50:15.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:50:15.88:setupk4=1 2006.201.15:50:15.88$setupk4/echo=on 2006.201.15:50:15.88$setupk4/pcalon 2006.201.15:50:15.88$pcalon/"no phase cal control is implemented here 2006.201.15:50:15.88$setupk4/"tpicd=stop 2006.201.15:50:15.88$setupk4/"rec=synch_on 2006.201.15:50:15.88$setupk4/"rec_mode=128 2006.201.15:50:15.88$setupk4/!* 2006.201.15:50:15.88$setupk4/recpk4 2006.201.15:50:15.88$recpk4/recpatch= 2006.201.15:50:15.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:50:15.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:50:15.88$setupk4/vck44 2006.201.15:50:15.88$vck44/valo=1,524.99 2006.201.15:50:15.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.15:50:15.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.15:50:15.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:15.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:15.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:15.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:15.88#ibcon#enter wrdev, iclass 13, count 0 2006.201.15:50:15.88#ibcon#first serial, iclass 13, count 0 2006.201.15:50:15.88#ibcon#enter sib2, iclass 13, count 0 2006.201.15:50:15.88#ibcon#flushed, iclass 13, count 0 2006.201.15:50:15.88#ibcon#about to write, iclass 13, count 0 2006.201.15:50:15.88#ibcon#wrote, iclass 13, count 0 2006.201.15:50:15.88#ibcon#about to read 3, iclass 13, count 0 2006.201.15:50:15.92#ibcon#read 3, iclass 13, count 0 2006.201.15:50:15.92#ibcon#about to read 4, iclass 13, count 0 2006.201.15:50:15.92#ibcon#read 4, iclass 13, count 0 2006.201.15:50:15.92#ibcon#about to read 5, iclass 13, count 0 2006.201.15:50:15.92#ibcon#read 5, iclass 13, count 0 2006.201.15:50:15.92#ibcon#about to read 6, iclass 13, count 0 2006.201.15:50:15.92#ibcon#read 6, iclass 13, count 0 2006.201.15:50:15.92#ibcon#end of sib2, iclass 13, count 0 2006.201.15:50:15.92#ibcon#*mode == 0, iclass 13, count 0 2006.201.15:50:15.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.15:50:15.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:50:15.92#ibcon#*before write, iclass 13, count 0 2006.201.15:50:15.92#ibcon#enter sib2, iclass 13, count 0 2006.201.15:50:15.92#ibcon#flushed, iclass 13, count 0 2006.201.15:50:15.92#ibcon#about to write, iclass 13, count 0 2006.201.15:50:15.92#ibcon#wrote, iclass 13, count 0 2006.201.15:50:15.92#ibcon#about to read 3, iclass 13, count 0 2006.201.15:50:15.97#ibcon#read 3, iclass 13, count 0 2006.201.15:50:15.97#ibcon#about to read 4, iclass 13, count 0 2006.201.15:50:15.97#ibcon#read 4, iclass 13, count 0 2006.201.15:50:15.97#ibcon#about to read 5, iclass 13, count 0 2006.201.15:50:15.97#ibcon#read 5, iclass 13, count 0 2006.201.15:50:15.97#ibcon#about to read 6, iclass 13, count 0 2006.201.15:50:15.97#ibcon#read 6, iclass 13, count 0 2006.201.15:50:15.97#ibcon#end of sib2, iclass 13, count 0 2006.201.15:50:15.97#ibcon#*after write, iclass 13, count 0 2006.201.15:50:15.97#ibcon#*before return 0, iclass 13, count 0 2006.201.15:50:15.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:15.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:15.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.15:50:15.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.15:50:15.97$vck44/va=1,8 2006.201.15:50:15.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.15:50:15.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.15:50:15.97#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:15.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:15.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:15.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:15.97#ibcon#enter wrdev, iclass 15, count 2 2006.201.15:50:15.97#ibcon#first serial, iclass 15, count 2 2006.201.15:50:15.97#ibcon#enter sib2, iclass 15, count 2 2006.201.15:50:15.97#ibcon#flushed, iclass 15, count 2 2006.201.15:50:15.97#ibcon#about to write, iclass 15, count 2 2006.201.15:50:15.97#ibcon#wrote, iclass 15, count 2 2006.201.15:50:15.97#ibcon#about to read 3, iclass 15, count 2 2006.201.15:50:15.99#ibcon#read 3, iclass 15, count 2 2006.201.15:50:15.99#ibcon#about to read 4, iclass 15, count 2 2006.201.15:50:15.99#ibcon#read 4, iclass 15, count 2 2006.201.15:50:15.99#ibcon#about to read 5, iclass 15, count 2 2006.201.15:50:15.99#ibcon#read 5, iclass 15, count 2 2006.201.15:50:15.99#ibcon#about to read 6, iclass 15, count 2 2006.201.15:50:15.99#ibcon#read 6, iclass 15, count 2 2006.201.15:50:15.99#ibcon#end of sib2, iclass 15, count 2 2006.201.15:50:15.99#ibcon#*mode == 0, iclass 15, count 2 2006.201.15:50:15.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.15:50:15.99#ibcon#[25=AT01-08\r\n] 2006.201.15:50:15.99#ibcon#*before write, iclass 15, count 2 2006.201.15:50:15.99#ibcon#enter sib2, iclass 15, count 2 2006.201.15:50:15.99#ibcon#flushed, iclass 15, count 2 2006.201.15:50:15.99#ibcon#about to write, iclass 15, count 2 2006.201.15:50:15.99#ibcon#wrote, iclass 15, count 2 2006.201.15:50:15.99#ibcon#about to read 3, iclass 15, count 2 2006.201.15:50:16.03#ibcon#read 3, iclass 15, count 2 2006.201.15:50:16.03#ibcon#about to read 4, iclass 15, count 2 2006.201.15:50:16.03#ibcon#read 4, iclass 15, count 2 2006.201.15:50:16.03#ibcon#about to read 5, iclass 15, count 2 2006.201.15:50:16.03#ibcon#read 5, iclass 15, count 2 2006.201.15:50:16.03#ibcon#about to read 6, iclass 15, count 2 2006.201.15:50:16.03#ibcon#read 6, iclass 15, count 2 2006.201.15:50:16.03#ibcon#end of sib2, iclass 15, count 2 2006.201.15:50:16.03#ibcon#*after write, iclass 15, count 2 2006.201.15:50:16.03#ibcon#*before return 0, iclass 15, count 2 2006.201.15:50:16.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:16.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:16.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.15:50:16.03#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:16.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:16.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:16.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:16.15#ibcon#enter wrdev, iclass 15, count 0 2006.201.15:50:16.15#ibcon#first serial, iclass 15, count 0 2006.201.15:50:16.15#ibcon#enter sib2, iclass 15, count 0 2006.201.15:50:16.15#ibcon#flushed, iclass 15, count 0 2006.201.15:50:16.15#ibcon#about to write, iclass 15, count 0 2006.201.15:50:16.15#ibcon#wrote, iclass 15, count 0 2006.201.15:50:16.15#ibcon#about to read 3, iclass 15, count 0 2006.201.15:50:16.17#ibcon#read 3, iclass 15, count 0 2006.201.15:50:16.17#ibcon#about to read 4, iclass 15, count 0 2006.201.15:50:16.17#ibcon#read 4, iclass 15, count 0 2006.201.15:50:16.17#ibcon#about to read 5, iclass 15, count 0 2006.201.15:50:16.17#ibcon#read 5, iclass 15, count 0 2006.201.15:50:16.17#ibcon#about to read 6, iclass 15, count 0 2006.201.15:50:16.17#ibcon#read 6, iclass 15, count 0 2006.201.15:50:16.17#ibcon#end of sib2, iclass 15, count 0 2006.201.15:50:16.17#ibcon#*mode == 0, iclass 15, count 0 2006.201.15:50:16.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.15:50:16.17#ibcon#[25=USB\r\n] 2006.201.15:50:16.17#ibcon#*before write, iclass 15, count 0 2006.201.15:50:16.17#ibcon#enter sib2, iclass 15, count 0 2006.201.15:50:16.17#ibcon#flushed, iclass 15, count 0 2006.201.15:50:16.17#ibcon#about to write, iclass 15, count 0 2006.201.15:50:16.17#ibcon#wrote, iclass 15, count 0 2006.201.15:50:16.17#ibcon#about to read 3, iclass 15, count 0 2006.201.15:50:16.20#ibcon#read 3, iclass 15, count 0 2006.201.15:50:16.20#ibcon#about to read 4, iclass 15, count 0 2006.201.15:50:16.20#ibcon#read 4, iclass 15, count 0 2006.201.15:50:16.20#ibcon#about to read 5, iclass 15, count 0 2006.201.15:50:16.20#ibcon#read 5, iclass 15, count 0 2006.201.15:50:16.20#ibcon#about to read 6, iclass 15, count 0 2006.201.15:50:16.20#ibcon#read 6, iclass 15, count 0 2006.201.15:50:16.20#ibcon#end of sib2, iclass 15, count 0 2006.201.15:50:16.20#ibcon#*after write, iclass 15, count 0 2006.201.15:50:16.20#ibcon#*before return 0, iclass 15, count 0 2006.201.15:50:16.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:16.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:16.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.15:50:16.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.15:50:16.20$vck44/valo=2,534.99 2006.201.15:50:16.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.15:50:16.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.15:50:16.20#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:16.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:16.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:16.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:16.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.15:50:16.20#ibcon#first serial, iclass 17, count 0 2006.201.15:50:16.20#ibcon#enter sib2, iclass 17, count 0 2006.201.15:50:16.20#ibcon#flushed, iclass 17, count 0 2006.201.15:50:16.20#ibcon#about to write, iclass 17, count 0 2006.201.15:50:16.20#ibcon#wrote, iclass 17, count 0 2006.201.15:50:16.20#ibcon#about to read 3, iclass 17, count 0 2006.201.15:50:16.22#ibcon#read 3, iclass 17, count 0 2006.201.15:50:16.22#ibcon#about to read 4, iclass 17, count 0 2006.201.15:50:16.22#ibcon#read 4, iclass 17, count 0 2006.201.15:50:16.22#ibcon#about to read 5, iclass 17, count 0 2006.201.15:50:16.22#ibcon#read 5, iclass 17, count 0 2006.201.15:50:16.22#ibcon#about to read 6, iclass 17, count 0 2006.201.15:50:16.22#ibcon#read 6, iclass 17, count 0 2006.201.15:50:16.22#ibcon#end of sib2, iclass 17, count 0 2006.201.15:50:16.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.15:50:16.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.15:50:16.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:50:16.22#ibcon#*before write, iclass 17, count 0 2006.201.15:50:16.22#ibcon#enter sib2, iclass 17, count 0 2006.201.15:50:16.22#ibcon#flushed, iclass 17, count 0 2006.201.15:50:16.22#ibcon#about to write, iclass 17, count 0 2006.201.15:50:16.22#ibcon#wrote, iclass 17, count 0 2006.201.15:50:16.22#ibcon#about to read 3, iclass 17, count 0 2006.201.15:50:16.26#ibcon#read 3, iclass 17, count 0 2006.201.15:50:16.26#ibcon#about to read 4, iclass 17, count 0 2006.201.15:50:16.26#ibcon#read 4, iclass 17, count 0 2006.201.15:50:16.26#ibcon#about to read 5, iclass 17, count 0 2006.201.15:50:16.26#ibcon#read 5, iclass 17, count 0 2006.201.15:50:16.26#ibcon#about to read 6, iclass 17, count 0 2006.201.15:50:16.26#ibcon#read 6, iclass 17, count 0 2006.201.15:50:16.26#ibcon#end of sib2, iclass 17, count 0 2006.201.15:50:16.26#ibcon#*after write, iclass 17, count 0 2006.201.15:50:16.26#ibcon#*before return 0, iclass 17, count 0 2006.201.15:50:16.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:16.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:16.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.15:50:16.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.15:50:16.26$vck44/va=2,7 2006.201.15:50:16.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.15:50:16.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.15:50:16.26#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:16.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:16.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:16.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:16.32#ibcon#enter wrdev, iclass 19, count 2 2006.201.15:50:16.32#ibcon#first serial, iclass 19, count 2 2006.201.15:50:16.32#ibcon#enter sib2, iclass 19, count 2 2006.201.15:50:16.32#ibcon#flushed, iclass 19, count 2 2006.201.15:50:16.32#ibcon#about to write, iclass 19, count 2 2006.201.15:50:16.32#ibcon#wrote, iclass 19, count 2 2006.201.15:50:16.32#ibcon#about to read 3, iclass 19, count 2 2006.201.15:50:16.34#ibcon#read 3, iclass 19, count 2 2006.201.15:50:16.34#ibcon#about to read 4, iclass 19, count 2 2006.201.15:50:16.34#ibcon#read 4, iclass 19, count 2 2006.201.15:50:16.34#ibcon#about to read 5, iclass 19, count 2 2006.201.15:50:16.34#ibcon#read 5, iclass 19, count 2 2006.201.15:50:16.34#ibcon#about to read 6, iclass 19, count 2 2006.201.15:50:16.34#ibcon#read 6, iclass 19, count 2 2006.201.15:50:16.34#ibcon#end of sib2, iclass 19, count 2 2006.201.15:50:16.34#ibcon#*mode == 0, iclass 19, count 2 2006.201.15:50:16.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.15:50:16.34#ibcon#[25=AT02-07\r\n] 2006.201.15:50:16.34#ibcon#*before write, iclass 19, count 2 2006.201.15:50:16.34#ibcon#enter sib2, iclass 19, count 2 2006.201.15:50:16.34#ibcon#flushed, iclass 19, count 2 2006.201.15:50:16.34#ibcon#about to write, iclass 19, count 2 2006.201.15:50:16.34#ibcon#wrote, iclass 19, count 2 2006.201.15:50:16.34#ibcon#about to read 3, iclass 19, count 2 2006.201.15:50:16.37#ibcon#read 3, iclass 19, count 2 2006.201.15:50:16.37#ibcon#about to read 4, iclass 19, count 2 2006.201.15:50:16.37#ibcon#read 4, iclass 19, count 2 2006.201.15:50:16.37#ibcon#about to read 5, iclass 19, count 2 2006.201.15:50:16.37#ibcon#read 5, iclass 19, count 2 2006.201.15:50:16.37#ibcon#about to read 6, iclass 19, count 2 2006.201.15:50:16.37#ibcon#read 6, iclass 19, count 2 2006.201.15:50:16.37#ibcon#end of sib2, iclass 19, count 2 2006.201.15:50:16.37#ibcon#*after write, iclass 19, count 2 2006.201.15:50:16.37#ibcon#*before return 0, iclass 19, count 2 2006.201.15:50:16.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:16.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:16.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.15:50:16.37#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:16.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:16.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:16.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:16.49#ibcon#enter wrdev, iclass 19, count 0 2006.201.15:50:16.49#ibcon#first serial, iclass 19, count 0 2006.201.15:50:16.49#ibcon#enter sib2, iclass 19, count 0 2006.201.15:50:16.49#ibcon#flushed, iclass 19, count 0 2006.201.15:50:16.49#ibcon#about to write, iclass 19, count 0 2006.201.15:50:16.49#ibcon#wrote, iclass 19, count 0 2006.201.15:50:16.49#ibcon#about to read 3, iclass 19, count 0 2006.201.15:50:16.51#ibcon#read 3, iclass 19, count 0 2006.201.15:50:16.51#ibcon#about to read 4, iclass 19, count 0 2006.201.15:50:16.51#ibcon#read 4, iclass 19, count 0 2006.201.15:50:16.51#ibcon#about to read 5, iclass 19, count 0 2006.201.15:50:16.51#ibcon#read 5, iclass 19, count 0 2006.201.15:50:16.51#ibcon#about to read 6, iclass 19, count 0 2006.201.15:50:16.51#ibcon#read 6, iclass 19, count 0 2006.201.15:50:16.51#ibcon#end of sib2, iclass 19, count 0 2006.201.15:50:16.51#ibcon#*mode == 0, iclass 19, count 0 2006.201.15:50:16.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.15:50:16.51#ibcon#[25=USB\r\n] 2006.201.15:50:16.51#ibcon#*before write, iclass 19, count 0 2006.201.15:50:16.51#ibcon#enter sib2, iclass 19, count 0 2006.201.15:50:16.51#ibcon#flushed, iclass 19, count 0 2006.201.15:50:16.51#ibcon#about to write, iclass 19, count 0 2006.201.15:50:16.51#ibcon#wrote, iclass 19, count 0 2006.201.15:50:16.51#ibcon#about to read 3, iclass 19, count 0 2006.201.15:50:16.53#abcon#<5=/04 1.0 1.5 20.841001002.8\r\n> 2006.201.15:50:16.54#ibcon#read 3, iclass 19, count 0 2006.201.15:50:16.54#ibcon#about to read 4, iclass 19, count 0 2006.201.15:50:16.54#ibcon#read 4, iclass 19, count 0 2006.201.15:50:16.54#ibcon#about to read 5, iclass 19, count 0 2006.201.15:50:16.54#ibcon#read 5, iclass 19, count 0 2006.201.15:50:16.54#ibcon#about to read 6, iclass 19, count 0 2006.201.15:50:16.54#ibcon#read 6, iclass 19, count 0 2006.201.15:50:16.54#ibcon#end of sib2, iclass 19, count 0 2006.201.15:50:16.54#ibcon#*after write, iclass 19, count 0 2006.201.15:50:16.54#ibcon#*before return 0, iclass 19, count 0 2006.201.15:50:16.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:16.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:16.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.15:50:16.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.15:50:16.54$vck44/valo=3,564.99 2006.201.15:50:16.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.15:50:16.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.15:50:16.54#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:16.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:50:16.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:50:16.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:50:16.54#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:50:16.54#ibcon#first serial, iclass 24, count 0 2006.201.15:50:16.54#ibcon#enter sib2, iclass 24, count 0 2006.201.15:50:16.54#ibcon#flushed, iclass 24, count 0 2006.201.15:50:16.54#ibcon#about to write, iclass 24, count 0 2006.201.15:50:16.54#ibcon#wrote, iclass 24, count 0 2006.201.15:50:16.54#ibcon#about to read 3, iclass 24, count 0 2006.201.15:50:16.55#abcon#{5=INTERFACE CLEAR} 2006.201.15:50:16.56#ibcon#read 3, iclass 24, count 0 2006.201.15:50:16.56#ibcon#about to read 4, iclass 24, count 0 2006.201.15:50:16.56#ibcon#read 4, iclass 24, count 0 2006.201.15:50:16.56#ibcon#about to read 5, iclass 24, count 0 2006.201.15:50:16.56#ibcon#read 5, iclass 24, count 0 2006.201.15:50:16.56#ibcon#about to read 6, iclass 24, count 0 2006.201.15:50:16.56#ibcon#read 6, iclass 24, count 0 2006.201.15:50:16.56#ibcon#end of sib2, iclass 24, count 0 2006.201.15:50:16.56#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:50:16.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:50:16.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:50:16.56#ibcon#*before write, iclass 24, count 0 2006.201.15:50:16.56#ibcon#enter sib2, iclass 24, count 0 2006.201.15:50:16.56#ibcon#flushed, iclass 24, count 0 2006.201.15:50:16.56#ibcon#about to write, iclass 24, count 0 2006.201.15:50:16.56#ibcon#wrote, iclass 24, count 0 2006.201.15:50:16.56#ibcon#about to read 3, iclass 24, count 0 2006.201.15:50:16.60#ibcon#read 3, iclass 24, count 0 2006.201.15:50:16.60#ibcon#about to read 4, iclass 24, count 0 2006.201.15:50:16.60#ibcon#read 4, iclass 24, count 0 2006.201.15:50:16.60#ibcon#about to read 5, iclass 24, count 0 2006.201.15:50:16.60#ibcon#read 5, iclass 24, count 0 2006.201.15:50:16.60#ibcon#about to read 6, iclass 24, count 0 2006.201.15:50:16.60#ibcon#read 6, iclass 24, count 0 2006.201.15:50:16.60#ibcon#end of sib2, iclass 24, count 0 2006.201.15:50:16.60#ibcon#*after write, iclass 24, count 0 2006.201.15:50:16.60#ibcon#*before return 0, iclass 24, count 0 2006.201.15:50:16.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:50:16.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:50:16.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:50:16.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:50:16.60$vck44/va=3,8 2006.201.15:50:16.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.15:50:16.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.15:50:16.60#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:16.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:16.61#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:50:16.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:16.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:16.66#ibcon#enter wrdev, iclass 27, count 2 2006.201.15:50:16.66#ibcon#first serial, iclass 27, count 2 2006.201.15:50:16.66#ibcon#enter sib2, iclass 27, count 2 2006.201.15:50:16.66#ibcon#flushed, iclass 27, count 2 2006.201.15:50:16.66#ibcon#about to write, iclass 27, count 2 2006.201.15:50:16.66#ibcon#wrote, iclass 27, count 2 2006.201.15:50:16.66#ibcon#about to read 3, iclass 27, count 2 2006.201.15:50:16.68#ibcon#read 3, iclass 27, count 2 2006.201.15:50:16.68#ibcon#about to read 4, iclass 27, count 2 2006.201.15:50:16.68#ibcon#read 4, iclass 27, count 2 2006.201.15:50:16.68#ibcon#about to read 5, iclass 27, count 2 2006.201.15:50:16.68#ibcon#read 5, iclass 27, count 2 2006.201.15:50:16.68#ibcon#about to read 6, iclass 27, count 2 2006.201.15:50:16.68#ibcon#read 6, iclass 27, count 2 2006.201.15:50:16.68#ibcon#end of sib2, iclass 27, count 2 2006.201.15:50:16.68#ibcon#*mode == 0, iclass 27, count 2 2006.201.15:50:16.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.15:50:16.68#ibcon#[25=AT03-08\r\n] 2006.201.15:50:16.68#ibcon#*before write, iclass 27, count 2 2006.201.15:50:16.68#ibcon#enter sib2, iclass 27, count 2 2006.201.15:50:16.68#ibcon#flushed, iclass 27, count 2 2006.201.15:50:16.68#ibcon#about to write, iclass 27, count 2 2006.201.15:50:16.68#ibcon#wrote, iclass 27, count 2 2006.201.15:50:16.68#ibcon#about to read 3, iclass 27, count 2 2006.201.15:50:16.71#ibcon#read 3, iclass 27, count 2 2006.201.15:50:16.71#ibcon#about to read 4, iclass 27, count 2 2006.201.15:50:16.71#ibcon#read 4, iclass 27, count 2 2006.201.15:50:16.71#ibcon#about to read 5, iclass 27, count 2 2006.201.15:50:16.71#ibcon#read 5, iclass 27, count 2 2006.201.15:50:16.71#ibcon#about to read 6, iclass 27, count 2 2006.201.15:50:16.71#ibcon#read 6, iclass 27, count 2 2006.201.15:50:16.71#ibcon#end of sib2, iclass 27, count 2 2006.201.15:50:16.71#ibcon#*after write, iclass 27, count 2 2006.201.15:50:16.71#ibcon#*before return 0, iclass 27, count 2 2006.201.15:50:16.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:16.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:16.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.15:50:16.71#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:16.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:16.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:16.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:16.83#ibcon#enter wrdev, iclass 27, count 0 2006.201.15:50:16.83#ibcon#first serial, iclass 27, count 0 2006.201.15:50:16.83#ibcon#enter sib2, iclass 27, count 0 2006.201.15:50:16.83#ibcon#flushed, iclass 27, count 0 2006.201.15:50:16.83#ibcon#about to write, iclass 27, count 0 2006.201.15:50:16.83#ibcon#wrote, iclass 27, count 0 2006.201.15:50:16.83#ibcon#about to read 3, iclass 27, count 0 2006.201.15:50:16.85#ibcon#read 3, iclass 27, count 0 2006.201.15:50:16.85#ibcon#about to read 4, iclass 27, count 0 2006.201.15:50:16.85#ibcon#read 4, iclass 27, count 0 2006.201.15:50:16.85#ibcon#about to read 5, iclass 27, count 0 2006.201.15:50:16.85#ibcon#read 5, iclass 27, count 0 2006.201.15:50:16.85#ibcon#about to read 6, iclass 27, count 0 2006.201.15:50:16.85#ibcon#read 6, iclass 27, count 0 2006.201.15:50:16.85#ibcon#end of sib2, iclass 27, count 0 2006.201.15:50:16.85#ibcon#*mode == 0, iclass 27, count 0 2006.201.15:50:16.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.15:50:16.85#ibcon#[25=USB\r\n] 2006.201.15:50:16.85#ibcon#*before write, iclass 27, count 0 2006.201.15:50:16.85#ibcon#enter sib2, iclass 27, count 0 2006.201.15:50:16.85#ibcon#flushed, iclass 27, count 0 2006.201.15:50:16.85#ibcon#about to write, iclass 27, count 0 2006.201.15:50:16.85#ibcon#wrote, iclass 27, count 0 2006.201.15:50:16.85#ibcon#about to read 3, iclass 27, count 0 2006.201.15:50:16.88#ibcon#read 3, iclass 27, count 0 2006.201.15:50:16.88#ibcon#about to read 4, iclass 27, count 0 2006.201.15:50:16.88#ibcon#read 4, iclass 27, count 0 2006.201.15:50:16.88#ibcon#about to read 5, iclass 27, count 0 2006.201.15:50:16.88#ibcon#read 5, iclass 27, count 0 2006.201.15:50:16.88#ibcon#about to read 6, iclass 27, count 0 2006.201.15:50:16.88#ibcon#read 6, iclass 27, count 0 2006.201.15:50:16.88#ibcon#end of sib2, iclass 27, count 0 2006.201.15:50:16.88#ibcon#*after write, iclass 27, count 0 2006.201.15:50:16.88#ibcon#*before return 0, iclass 27, count 0 2006.201.15:50:16.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:16.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:16.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.15:50:16.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.15:50:16.88$vck44/valo=4,624.99 2006.201.15:50:16.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.15:50:16.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.15:50:16.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:16.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:16.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:16.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:16.88#ibcon#enter wrdev, iclass 29, count 0 2006.201.15:50:16.88#ibcon#first serial, iclass 29, count 0 2006.201.15:50:16.88#ibcon#enter sib2, iclass 29, count 0 2006.201.15:50:16.88#ibcon#flushed, iclass 29, count 0 2006.201.15:50:16.88#ibcon#about to write, iclass 29, count 0 2006.201.15:50:16.88#ibcon#wrote, iclass 29, count 0 2006.201.15:50:16.88#ibcon#about to read 3, iclass 29, count 0 2006.201.15:50:16.90#ibcon#read 3, iclass 29, count 0 2006.201.15:50:16.90#ibcon#about to read 4, iclass 29, count 0 2006.201.15:50:16.90#ibcon#read 4, iclass 29, count 0 2006.201.15:50:16.90#ibcon#about to read 5, iclass 29, count 0 2006.201.15:50:16.90#ibcon#read 5, iclass 29, count 0 2006.201.15:50:16.90#ibcon#about to read 6, iclass 29, count 0 2006.201.15:50:16.90#ibcon#read 6, iclass 29, count 0 2006.201.15:50:16.90#ibcon#end of sib2, iclass 29, count 0 2006.201.15:50:16.90#ibcon#*mode == 0, iclass 29, count 0 2006.201.15:50:16.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.15:50:16.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:50:16.90#ibcon#*before write, iclass 29, count 0 2006.201.15:50:16.90#ibcon#enter sib2, iclass 29, count 0 2006.201.15:50:16.90#ibcon#flushed, iclass 29, count 0 2006.201.15:50:16.90#ibcon#about to write, iclass 29, count 0 2006.201.15:50:16.90#ibcon#wrote, iclass 29, count 0 2006.201.15:50:16.90#ibcon#about to read 3, iclass 29, count 0 2006.201.15:50:16.95#ibcon#read 3, iclass 29, count 0 2006.201.15:50:16.95#ibcon#about to read 4, iclass 29, count 0 2006.201.15:50:16.95#ibcon#read 4, iclass 29, count 0 2006.201.15:50:16.95#ibcon#about to read 5, iclass 29, count 0 2006.201.15:50:16.95#ibcon#read 5, iclass 29, count 0 2006.201.15:50:16.95#ibcon#about to read 6, iclass 29, count 0 2006.201.15:50:16.95#ibcon#read 6, iclass 29, count 0 2006.201.15:50:16.95#ibcon#end of sib2, iclass 29, count 0 2006.201.15:50:16.95#ibcon#*after write, iclass 29, count 0 2006.201.15:50:16.95#ibcon#*before return 0, iclass 29, count 0 2006.201.15:50:16.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:16.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:16.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.15:50:16.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.15:50:16.95$vck44/va=4,7 2006.201.15:50:16.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.15:50:16.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.15:50:16.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:16.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:17.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:17.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:17.00#ibcon#enter wrdev, iclass 31, count 2 2006.201.15:50:17.00#ibcon#first serial, iclass 31, count 2 2006.201.15:50:17.00#ibcon#enter sib2, iclass 31, count 2 2006.201.15:50:17.00#ibcon#flushed, iclass 31, count 2 2006.201.15:50:17.00#ibcon#about to write, iclass 31, count 2 2006.201.15:50:17.00#ibcon#wrote, iclass 31, count 2 2006.201.15:50:17.00#ibcon#about to read 3, iclass 31, count 2 2006.201.15:50:17.02#ibcon#read 3, iclass 31, count 2 2006.201.15:50:17.02#ibcon#about to read 4, iclass 31, count 2 2006.201.15:50:17.02#ibcon#read 4, iclass 31, count 2 2006.201.15:50:17.02#ibcon#about to read 5, iclass 31, count 2 2006.201.15:50:17.02#ibcon#read 5, iclass 31, count 2 2006.201.15:50:17.02#ibcon#about to read 6, iclass 31, count 2 2006.201.15:50:17.02#ibcon#read 6, iclass 31, count 2 2006.201.15:50:17.02#ibcon#end of sib2, iclass 31, count 2 2006.201.15:50:17.02#ibcon#*mode == 0, iclass 31, count 2 2006.201.15:50:17.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.15:50:17.02#ibcon#[25=AT04-07\r\n] 2006.201.15:50:17.02#ibcon#*before write, iclass 31, count 2 2006.201.15:50:17.02#ibcon#enter sib2, iclass 31, count 2 2006.201.15:50:17.02#ibcon#flushed, iclass 31, count 2 2006.201.15:50:17.02#ibcon#about to write, iclass 31, count 2 2006.201.15:50:17.02#ibcon#wrote, iclass 31, count 2 2006.201.15:50:17.02#ibcon#about to read 3, iclass 31, count 2 2006.201.15:50:17.05#ibcon#read 3, iclass 31, count 2 2006.201.15:50:17.05#ibcon#about to read 4, iclass 31, count 2 2006.201.15:50:17.05#ibcon#read 4, iclass 31, count 2 2006.201.15:50:17.05#ibcon#about to read 5, iclass 31, count 2 2006.201.15:50:17.05#ibcon#read 5, iclass 31, count 2 2006.201.15:50:17.05#ibcon#about to read 6, iclass 31, count 2 2006.201.15:50:17.05#ibcon#read 6, iclass 31, count 2 2006.201.15:50:17.05#ibcon#end of sib2, iclass 31, count 2 2006.201.15:50:17.05#ibcon#*after write, iclass 31, count 2 2006.201.15:50:17.05#ibcon#*before return 0, iclass 31, count 2 2006.201.15:50:17.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:17.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:17.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.15:50:17.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:17.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:17.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:17.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:17.17#ibcon#enter wrdev, iclass 31, count 0 2006.201.15:50:17.17#ibcon#first serial, iclass 31, count 0 2006.201.15:50:17.17#ibcon#enter sib2, iclass 31, count 0 2006.201.15:50:17.17#ibcon#flushed, iclass 31, count 0 2006.201.15:50:17.17#ibcon#about to write, iclass 31, count 0 2006.201.15:50:17.17#ibcon#wrote, iclass 31, count 0 2006.201.15:50:17.17#ibcon#about to read 3, iclass 31, count 0 2006.201.15:50:17.19#ibcon#read 3, iclass 31, count 0 2006.201.15:50:17.19#ibcon#about to read 4, iclass 31, count 0 2006.201.15:50:17.19#ibcon#read 4, iclass 31, count 0 2006.201.15:50:17.19#ibcon#about to read 5, iclass 31, count 0 2006.201.15:50:17.19#ibcon#read 5, iclass 31, count 0 2006.201.15:50:17.19#ibcon#about to read 6, iclass 31, count 0 2006.201.15:50:17.19#ibcon#read 6, iclass 31, count 0 2006.201.15:50:17.19#ibcon#end of sib2, iclass 31, count 0 2006.201.15:50:17.19#ibcon#*mode == 0, iclass 31, count 0 2006.201.15:50:17.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.15:50:17.19#ibcon#[25=USB\r\n] 2006.201.15:50:17.19#ibcon#*before write, iclass 31, count 0 2006.201.15:50:17.19#ibcon#enter sib2, iclass 31, count 0 2006.201.15:50:17.19#ibcon#flushed, iclass 31, count 0 2006.201.15:50:17.19#ibcon#about to write, iclass 31, count 0 2006.201.15:50:17.19#ibcon#wrote, iclass 31, count 0 2006.201.15:50:17.19#ibcon#about to read 3, iclass 31, count 0 2006.201.15:50:17.22#ibcon#read 3, iclass 31, count 0 2006.201.15:50:17.22#ibcon#about to read 4, iclass 31, count 0 2006.201.15:50:17.22#ibcon#read 4, iclass 31, count 0 2006.201.15:50:17.22#ibcon#about to read 5, iclass 31, count 0 2006.201.15:50:17.22#ibcon#read 5, iclass 31, count 0 2006.201.15:50:17.22#ibcon#about to read 6, iclass 31, count 0 2006.201.15:50:17.22#ibcon#read 6, iclass 31, count 0 2006.201.15:50:17.22#ibcon#end of sib2, iclass 31, count 0 2006.201.15:50:17.22#ibcon#*after write, iclass 31, count 0 2006.201.15:50:17.22#ibcon#*before return 0, iclass 31, count 0 2006.201.15:50:17.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:17.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:17.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.15:50:17.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.15:50:17.22$vck44/valo=5,734.99 2006.201.15:50:17.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.15:50:17.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.15:50:17.22#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:17.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:17.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:17.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:17.22#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:50:17.22#ibcon#first serial, iclass 33, count 0 2006.201.15:50:17.22#ibcon#enter sib2, iclass 33, count 0 2006.201.15:50:17.22#ibcon#flushed, iclass 33, count 0 2006.201.15:50:17.22#ibcon#about to write, iclass 33, count 0 2006.201.15:50:17.22#ibcon#wrote, iclass 33, count 0 2006.201.15:50:17.22#ibcon#about to read 3, iclass 33, count 0 2006.201.15:50:17.24#ibcon#read 3, iclass 33, count 0 2006.201.15:50:17.24#ibcon#about to read 4, iclass 33, count 0 2006.201.15:50:17.24#ibcon#read 4, iclass 33, count 0 2006.201.15:50:17.24#ibcon#about to read 5, iclass 33, count 0 2006.201.15:50:17.24#ibcon#read 5, iclass 33, count 0 2006.201.15:50:17.24#ibcon#about to read 6, iclass 33, count 0 2006.201.15:50:17.24#ibcon#read 6, iclass 33, count 0 2006.201.15:50:17.24#ibcon#end of sib2, iclass 33, count 0 2006.201.15:50:17.24#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:50:17.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:50:17.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:50:17.24#ibcon#*before write, iclass 33, count 0 2006.201.15:50:17.24#ibcon#enter sib2, iclass 33, count 0 2006.201.15:50:17.24#ibcon#flushed, iclass 33, count 0 2006.201.15:50:17.24#ibcon#about to write, iclass 33, count 0 2006.201.15:50:17.24#ibcon#wrote, iclass 33, count 0 2006.201.15:50:17.24#ibcon#about to read 3, iclass 33, count 0 2006.201.15:50:17.28#ibcon#read 3, iclass 33, count 0 2006.201.15:50:17.28#ibcon#about to read 4, iclass 33, count 0 2006.201.15:50:17.28#ibcon#read 4, iclass 33, count 0 2006.201.15:50:17.28#ibcon#about to read 5, iclass 33, count 0 2006.201.15:50:17.28#ibcon#read 5, iclass 33, count 0 2006.201.15:50:17.28#ibcon#about to read 6, iclass 33, count 0 2006.201.15:50:17.28#ibcon#read 6, iclass 33, count 0 2006.201.15:50:17.28#ibcon#end of sib2, iclass 33, count 0 2006.201.15:50:17.28#ibcon#*after write, iclass 33, count 0 2006.201.15:50:17.28#ibcon#*before return 0, iclass 33, count 0 2006.201.15:50:17.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:17.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:17.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:50:17.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:50:17.28$vck44/va=5,4 2006.201.15:50:17.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.15:50:17.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.15:50:17.28#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:17.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:17.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:17.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:17.34#ibcon#enter wrdev, iclass 35, count 2 2006.201.15:50:17.34#ibcon#first serial, iclass 35, count 2 2006.201.15:50:17.34#ibcon#enter sib2, iclass 35, count 2 2006.201.15:50:17.34#ibcon#flushed, iclass 35, count 2 2006.201.15:50:17.34#ibcon#about to write, iclass 35, count 2 2006.201.15:50:17.34#ibcon#wrote, iclass 35, count 2 2006.201.15:50:17.34#ibcon#about to read 3, iclass 35, count 2 2006.201.15:50:17.36#ibcon#read 3, iclass 35, count 2 2006.201.15:50:17.36#ibcon#about to read 4, iclass 35, count 2 2006.201.15:50:17.36#ibcon#read 4, iclass 35, count 2 2006.201.15:50:17.36#ibcon#about to read 5, iclass 35, count 2 2006.201.15:50:17.36#ibcon#read 5, iclass 35, count 2 2006.201.15:50:17.36#ibcon#about to read 6, iclass 35, count 2 2006.201.15:50:17.36#ibcon#read 6, iclass 35, count 2 2006.201.15:50:17.36#ibcon#end of sib2, iclass 35, count 2 2006.201.15:50:17.36#ibcon#*mode == 0, iclass 35, count 2 2006.201.15:50:17.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.15:50:17.36#ibcon#[25=AT05-04\r\n] 2006.201.15:50:17.36#ibcon#*before write, iclass 35, count 2 2006.201.15:50:17.36#ibcon#enter sib2, iclass 35, count 2 2006.201.15:50:17.36#ibcon#flushed, iclass 35, count 2 2006.201.15:50:17.36#ibcon#about to write, iclass 35, count 2 2006.201.15:50:17.36#ibcon#wrote, iclass 35, count 2 2006.201.15:50:17.36#ibcon#about to read 3, iclass 35, count 2 2006.201.15:50:17.39#ibcon#read 3, iclass 35, count 2 2006.201.15:50:17.39#ibcon#about to read 4, iclass 35, count 2 2006.201.15:50:17.39#ibcon#read 4, iclass 35, count 2 2006.201.15:50:17.39#ibcon#about to read 5, iclass 35, count 2 2006.201.15:50:17.39#ibcon#read 5, iclass 35, count 2 2006.201.15:50:17.39#ibcon#about to read 6, iclass 35, count 2 2006.201.15:50:17.39#ibcon#read 6, iclass 35, count 2 2006.201.15:50:17.39#ibcon#end of sib2, iclass 35, count 2 2006.201.15:50:17.39#ibcon#*after write, iclass 35, count 2 2006.201.15:50:17.39#ibcon#*before return 0, iclass 35, count 2 2006.201.15:50:17.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:17.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:17.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.15:50:17.39#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:17.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:17.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:17.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:17.51#ibcon#enter wrdev, iclass 35, count 0 2006.201.15:50:17.51#ibcon#first serial, iclass 35, count 0 2006.201.15:50:17.51#ibcon#enter sib2, iclass 35, count 0 2006.201.15:50:17.51#ibcon#flushed, iclass 35, count 0 2006.201.15:50:17.51#ibcon#about to write, iclass 35, count 0 2006.201.15:50:17.51#ibcon#wrote, iclass 35, count 0 2006.201.15:50:17.51#ibcon#about to read 3, iclass 35, count 0 2006.201.15:50:17.53#ibcon#read 3, iclass 35, count 0 2006.201.15:50:17.53#ibcon#about to read 4, iclass 35, count 0 2006.201.15:50:17.53#ibcon#read 4, iclass 35, count 0 2006.201.15:50:17.53#ibcon#about to read 5, iclass 35, count 0 2006.201.15:50:17.53#ibcon#read 5, iclass 35, count 0 2006.201.15:50:17.53#ibcon#about to read 6, iclass 35, count 0 2006.201.15:50:17.53#ibcon#read 6, iclass 35, count 0 2006.201.15:50:17.53#ibcon#end of sib2, iclass 35, count 0 2006.201.15:50:17.53#ibcon#*mode == 0, iclass 35, count 0 2006.201.15:50:17.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.15:50:17.53#ibcon#[25=USB\r\n] 2006.201.15:50:17.53#ibcon#*before write, iclass 35, count 0 2006.201.15:50:17.53#ibcon#enter sib2, iclass 35, count 0 2006.201.15:50:17.53#ibcon#flushed, iclass 35, count 0 2006.201.15:50:17.53#ibcon#about to write, iclass 35, count 0 2006.201.15:50:17.53#ibcon#wrote, iclass 35, count 0 2006.201.15:50:17.53#ibcon#about to read 3, iclass 35, count 0 2006.201.15:50:17.56#ibcon#read 3, iclass 35, count 0 2006.201.15:50:17.56#ibcon#about to read 4, iclass 35, count 0 2006.201.15:50:17.56#ibcon#read 4, iclass 35, count 0 2006.201.15:50:17.56#ibcon#about to read 5, iclass 35, count 0 2006.201.15:50:17.56#ibcon#read 5, iclass 35, count 0 2006.201.15:50:17.56#ibcon#about to read 6, iclass 35, count 0 2006.201.15:50:17.56#ibcon#read 6, iclass 35, count 0 2006.201.15:50:17.56#ibcon#end of sib2, iclass 35, count 0 2006.201.15:50:17.56#ibcon#*after write, iclass 35, count 0 2006.201.15:50:17.56#ibcon#*before return 0, iclass 35, count 0 2006.201.15:50:17.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:17.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:17.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.15:50:17.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.15:50:17.56$vck44/valo=6,814.99 2006.201.15:50:17.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.15:50:17.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.15:50:17.56#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:17.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:17.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:17.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:17.56#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:50:17.56#ibcon#first serial, iclass 37, count 0 2006.201.15:50:17.56#ibcon#enter sib2, iclass 37, count 0 2006.201.15:50:17.56#ibcon#flushed, iclass 37, count 0 2006.201.15:50:17.56#ibcon#about to write, iclass 37, count 0 2006.201.15:50:17.56#ibcon#wrote, iclass 37, count 0 2006.201.15:50:17.56#ibcon#about to read 3, iclass 37, count 0 2006.201.15:50:17.58#ibcon#read 3, iclass 37, count 0 2006.201.15:50:17.58#ibcon#about to read 4, iclass 37, count 0 2006.201.15:50:17.58#ibcon#read 4, iclass 37, count 0 2006.201.15:50:17.58#ibcon#about to read 5, iclass 37, count 0 2006.201.15:50:17.58#ibcon#read 5, iclass 37, count 0 2006.201.15:50:17.58#ibcon#about to read 6, iclass 37, count 0 2006.201.15:50:17.58#ibcon#read 6, iclass 37, count 0 2006.201.15:50:17.58#ibcon#end of sib2, iclass 37, count 0 2006.201.15:50:17.58#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:50:17.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:50:17.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:50:17.58#ibcon#*before write, iclass 37, count 0 2006.201.15:50:17.58#ibcon#enter sib2, iclass 37, count 0 2006.201.15:50:17.58#ibcon#flushed, iclass 37, count 0 2006.201.15:50:17.58#ibcon#about to write, iclass 37, count 0 2006.201.15:50:17.58#ibcon#wrote, iclass 37, count 0 2006.201.15:50:17.58#ibcon#about to read 3, iclass 37, count 0 2006.201.15:50:17.62#ibcon#read 3, iclass 37, count 0 2006.201.15:50:17.62#ibcon#about to read 4, iclass 37, count 0 2006.201.15:50:17.62#ibcon#read 4, iclass 37, count 0 2006.201.15:50:17.62#ibcon#about to read 5, iclass 37, count 0 2006.201.15:50:17.62#ibcon#read 5, iclass 37, count 0 2006.201.15:50:17.62#ibcon#about to read 6, iclass 37, count 0 2006.201.15:50:17.62#ibcon#read 6, iclass 37, count 0 2006.201.15:50:17.62#ibcon#end of sib2, iclass 37, count 0 2006.201.15:50:17.62#ibcon#*after write, iclass 37, count 0 2006.201.15:50:17.62#ibcon#*before return 0, iclass 37, count 0 2006.201.15:50:17.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:17.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:17.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:50:17.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:50:17.62$vck44/va=6,5 2006.201.15:50:17.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.15:50:17.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.15:50:17.62#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:17.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:17.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:17.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:17.68#ibcon#enter wrdev, iclass 39, count 2 2006.201.15:50:17.68#ibcon#first serial, iclass 39, count 2 2006.201.15:50:17.68#ibcon#enter sib2, iclass 39, count 2 2006.201.15:50:17.68#ibcon#flushed, iclass 39, count 2 2006.201.15:50:17.68#ibcon#about to write, iclass 39, count 2 2006.201.15:50:17.68#ibcon#wrote, iclass 39, count 2 2006.201.15:50:17.68#ibcon#about to read 3, iclass 39, count 2 2006.201.15:50:17.70#ibcon#read 3, iclass 39, count 2 2006.201.15:50:17.70#ibcon#about to read 4, iclass 39, count 2 2006.201.15:50:17.70#ibcon#read 4, iclass 39, count 2 2006.201.15:50:17.70#ibcon#about to read 5, iclass 39, count 2 2006.201.15:50:17.70#ibcon#read 5, iclass 39, count 2 2006.201.15:50:17.70#ibcon#about to read 6, iclass 39, count 2 2006.201.15:50:17.70#ibcon#read 6, iclass 39, count 2 2006.201.15:50:17.70#ibcon#end of sib2, iclass 39, count 2 2006.201.15:50:17.70#ibcon#*mode == 0, iclass 39, count 2 2006.201.15:50:17.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.15:50:17.70#ibcon#[25=AT06-05\r\n] 2006.201.15:50:17.70#ibcon#*before write, iclass 39, count 2 2006.201.15:50:17.70#ibcon#enter sib2, iclass 39, count 2 2006.201.15:50:17.70#ibcon#flushed, iclass 39, count 2 2006.201.15:50:17.70#ibcon#about to write, iclass 39, count 2 2006.201.15:50:17.70#ibcon#wrote, iclass 39, count 2 2006.201.15:50:17.70#ibcon#about to read 3, iclass 39, count 2 2006.201.15:50:17.73#ibcon#read 3, iclass 39, count 2 2006.201.15:50:17.73#ibcon#about to read 4, iclass 39, count 2 2006.201.15:50:17.73#ibcon#read 4, iclass 39, count 2 2006.201.15:50:17.73#ibcon#about to read 5, iclass 39, count 2 2006.201.15:50:17.73#ibcon#read 5, iclass 39, count 2 2006.201.15:50:17.73#ibcon#about to read 6, iclass 39, count 2 2006.201.15:50:17.73#ibcon#read 6, iclass 39, count 2 2006.201.15:50:17.73#ibcon#end of sib2, iclass 39, count 2 2006.201.15:50:17.73#ibcon#*after write, iclass 39, count 2 2006.201.15:50:17.73#ibcon#*before return 0, iclass 39, count 2 2006.201.15:50:17.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:17.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:17.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.15:50:17.73#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:17.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:17.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:17.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:17.85#ibcon#enter wrdev, iclass 39, count 0 2006.201.15:50:17.85#ibcon#first serial, iclass 39, count 0 2006.201.15:50:17.85#ibcon#enter sib2, iclass 39, count 0 2006.201.15:50:17.85#ibcon#flushed, iclass 39, count 0 2006.201.15:50:17.85#ibcon#about to write, iclass 39, count 0 2006.201.15:50:17.85#ibcon#wrote, iclass 39, count 0 2006.201.15:50:17.85#ibcon#about to read 3, iclass 39, count 0 2006.201.15:50:17.87#ibcon#read 3, iclass 39, count 0 2006.201.15:50:17.87#ibcon#about to read 4, iclass 39, count 0 2006.201.15:50:17.87#ibcon#read 4, iclass 39, count 0 2006.201.15:50:17.87#ibcon#about to read 5, iclass 39, count 0 2006.201.15:50:17.87#ibcon#read 5, iclass 39, count 0 2006.201.15:50:17.87#ibcon#about to read 6, iclass 39, count 0 2006.201.15:50:17.87#ibcon#read 6, iclass 39, count 0 2006.201.15:50:17.87#ibcon#end of sib2, iclass 39, count 0 2006.201.15:50:17.87#ibcon#*mode == 0, iclass 39, count 0 2006.201.15:50:17.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.15:50:17.87#ibcon#[25=USB\r\n] 2006.201.15:50:17.87#ibcon#*before write, iclass 39, count 0 2006.201.15:50:17.87#ibcon#enter sib2, iclass 39, count 0 2006.201.15:50:17.87#ibcon#flushed, iclass 39, count 0 2006.201.15:50:17.87#ibcon#about to write, iclass 39, count 0 2006.201.15:50:17.87#ibcon#wrote, iclass 39, count 0 2006.201.15:50:17.87#ibcon#about to read 3, iclass 39, count 0 2006.201.15:50:17.90#ibcon#read 3, iclass 39, count 0 2006.201.15:50:17.90#ibcon#about to read 4, iclass 39, count 0 2006.201.15:50:17.90#ibcon#read 4, iclass 39, count 0 2006.201.15:50:17.90#ibcon#about to read 5, iclass 39, count 0 2006.201.15:50:17.90#ibcon#read 5, iclass 39, count 0 2006.201.15:50:17.90#ibcon#about to read 6, iclass 39, count 0 2006.201.15:50:17.90#ibcon#read 6, iclass 39, count 0 2006.201.15:50:17.90#ibcon#end of sib2, iclass 39, count 0 2006.201.15:50:17.90#ibcon#*after write, iclass 39, count 0 2006.201.15:50:17.90#ibcon#*before return 0, iclass 39, count 0 2006.201.15:50:17.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:17.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:17.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.15:50:17.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.15:50:17.90$vck44/valo=7,864.99 2006.201.15:50:17.90#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.15:50:17.90#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.15:50:17.90#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:17.90#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:17.90#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:17.90#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:17.90#ibcon#enter wrdev, iclass 2, count 0 2006.201.15:50:17.90#ibcon#first serial, iclass 2, count 0 2006.201.15:50:17.90#ibcon#enter sib2, iclass 2, count 0 2006.201.15:50:17.90#ibcon#flushed, iclass 2, count 0 2006.201.15:50:17.90#ibcon#about to write, iclass 2, count 0 2006.201.15:50:17.90#ibcon#wrote, iclass 2, count 0 2006.201.15:50:17.90#ibcon#about to read 3, iclass 2, count 0 2006.201.15:50:17.92#ibcon#read 3, iclass 2, count 0 2006.201.15:50:17.92#ibcon#about to read 4, iclass 2, count 0 2006.201.15:50:17.92#ibcon#read 4, iclass 2, count 0 2006.201.15:50:17.92#ibcon#about to read 5, iclass 2, count 0 2006.201.15:50:17.92#ibcon#read 5, iclass 2, count 0 2006.201.15:50:17.92#ibcon#about to read 6, iclass 2, count 0 2006.201.15:50:17.92#ibcon#read 6, iclass 2, count 0 2006.201.15:50:17.92#ibcon#end of sib2, iclass 2, count 0 2006.201.15:50:17.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.15:50:17.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.15:50:17.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:50:17.92#ibcon#*before write, iclass 2, count 0 2006.201.15:50:17.92#ibcon#enter sib2, iclass 2, count 0 2006.201.15:50:17.92#ibcon#flushed, iclass 2, count 0 2006.201.15:50:17.92#ibcon#about to write, iclass 2, count 0 2006.201.15:50:17.92#ibcon#wrote, iclass 2, count 0 2006.201.15:50:17.92#ibcon#about to read 3, iclass 2, count 0 2006.201.15:50:17.96#ibcon#read 3, iclass 2, count 0 2006.201.15:50:17.96#ibcon#about to read 4, iclass 2, count 0 2006.201.15:50:17.96#ibcon#read 4, iclass 2, count 0 2006.201.15:50:17.96#ibcon#about to read 5, iclass 2, count 0 2006.201.15:50:17.96#ibcon#read 5, iclass 2, count 0 2006.201.15:50:17.96#ibcon#about to read 6, iclass 2, count 0 2006.201.15:50:17.96#ibcon#read 6, iclass 2, count 0 2006.201.15:50:17.96#ibcon#end of sib2, iclass 2, count 0 2006.201.15:50:17.96#ibcon#*after write, iclass 2, count 0 2006.201.15:50:17.96#ibcon#*before return 0, iclass 2, count 0 2006.201.15:50:17.96#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:17.96#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:17.96#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.15:50:17.96#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.15:50:17.96$vck44/va=7,5 2006.201.15:50:17.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.15:50:17.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.15:50:17.96#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:17.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:18.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:18.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:18.02#ibcon#enter wrdev, iclass 5, count 2 2006.201.15:50:18.02#ibcon#first serial, iclass 5, count 2 2006.201.15:50:18.02#ibcon#enter sib2, iclass 5, count 2 2006.201.15:50:18.02#ibcon#flushed, iclass 5, count 2 2006.201.15:50:18.02#ibcon#about to write, iclass 5, count 2 2006.201.15:50:18.02#ibcon#wrote, iclass 5, count 2 2006.201.15:50:18.02#ibcon#about to read 3, iclass 5, count 2 2006.201.15:50:18.04#ibcon#read 3, iclass 5, count 2 2006.201.15:50:18.04#ibcon#about to read 4, iclass 5, count 2 2006.201.15:50:18.04#ibcon#read 4, iclass 5, count 2 2006.201.15:50:18.04#ibcon#about to read 5, iclass 5, count 2 2006.201.15:50:18.04#ibcon#read 5, iclass 5, count 2 2006.201.15:50:18.04#ibcon#about to read 6, iclass 5, count 2 2006.201.15:50:18.04#ibcon#read 6, iclass 5, count 2 2006.201.15:50:18.04#ibcon#end of sib2, iclass 5, count 2 2006.201.15:50:18.04#ibcon#*mode == 0, iclass 5, count 2 2006.201.15:50:18.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.15:50:18.04#ibcon#[25=AT07-05\r\n] 2006.201.15:50:18.04#ibcon#*before write, iclass 5, count 2 2006.201.15:50:18.04#ibcon#enter sib2, iclass 5, count 2 2006.201.15:50:18.04#ibcon#flushed, iclass 5, count 2 2006.201.15:50:18.04#ibcon#about to write, iclass 5, count 2 2006.201.15:50:18.04#ibcon#wrote, iclass 5, count 2 2006.201.15:50:18.04#ibcon#about to read 3, iclass 5, count 2 2006.201.15:50:18.07#ibcon#read 3, iclass 5, count 2 2006.201.15:50:18.07#ibcon#about to read 4, iclass 5, count 2 2006.201.15:50:18.07#ibcon#read 4, iclass 5, count 2 2006.201.15:50:18.07#ibcon#about to read 5, iclass 5, count 2 2006.201.15:50:18.07#ibcon#read 5, iclass 5, count 2 2006.201.15:50:18.07#ibcon#about to read 6, iclass 5, count 2 2006.201.15:50:18.07#ibcon#read 6, iclass 5, count 2 2006.201.15:50:18.07#ibcon#end of sib2, iclass 5, count 2 2006.201.15:50:18.07#ibcon#*after write, iclass 5, count 2 2006.201.15:50:18.07#ibcon#*before return 0, iclass 5, count 2 2006.201.15:50:18.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:18.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:18.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.15:50:18.07#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:18.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:18.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:18.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:18.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.15:50:18.19#ibcon#first serial, iclass 5, count 0 2006.201.15:50:18.19#ibcon#enter sib2, iclass 5, count 0 2006.201.15:50:18.19#ibcon#flushed, iclass 5, count 0 2006.201.15:50:18.19#ibcon#about to write, iclass 5, count 0 2006.201.15:50:18.19#ibcon#wrote, iclass 5, count 0 2006.201.15:50:18.19#ibcon#about to read 3, iclass 5, count 0 2006.201.15:50:18.21#ibcon#read 3, iclass 5, count 0 2006.201.15:50:18.21#ibcon#about to read 4, iclass 5, count 0 2006.201.15:50:18.21#ibcon#read 4, iclass 5, count 0 2006.201.15:50:18.21#ibcon#about to read 5, iclass 5, count 0 2006.201.15:50:18.21#ibcon#read 5, iclass 5, count 0 2006.201.15:50:18.21#ibcon#about to read 6, iclass 5, count 0 2006.201.15:50:18.21#ibcon#read 6, iclass 5, count 0 2006.201.15:50:18.21#ibcon#end of sib2, iclass 5, count 0 2006.201.15:50:18.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.15:50:18.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.15:50:18.21#ibcon#[25=USB\r\n] 2006.201.15:50:18.21#ibcon#*before write, iclass 5, count 0 2006.201.15:50:18.21#ibcon#enter sib2, iclass 5, count 0 2006.201.15:50:18.21#ibcon#flushed, iclass 5, count 0 2006.201.15:50:18.21#ibcon#about to write, iclass 5, count 0 2006.201.15:50:18.21#ibcon#wrote, iclass 5, count 0 2006.201.15:50:18.21#ibcon#about to read 3, iclass 5, count 0 2006.201.15:50:18.24#ibcon#read 3, iclass 5, count 0 2006.201.15:50:18.24#ibcon#about to read 4, iclass 5, count 0 2006.201.15:50:18.24#ibcon#read 4, iclass 5, count 0 2006.201.15:50:18.24#ibcon#about to read 5, iclass 5, count 0 2006.201.15:50:18.24#ibcon#read 5, iclass 5, count 0 2006.201.15:50:18.24#ibcon#about to read 6, iclass 5, count 0 2006.201.15:50:18.24#ibcon#read 6, iclass 5, count 0 2006.201.15:50:18.24#ibcon#end of sib2, iclass 5, count 0 2006.201.15:50:18.24#ibcon#*after write, iclass 5, count 0 2006.201.15:50:18.24#ibcon#*before return 0, iclass 5, count 0 2006.201.15:50:18.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:18.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:18.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.15:50:18.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.15:50:18.24$vck44/valo=8,884.99 2006.201.15:50:18.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.15:50:18.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.15:50:18.24#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:18.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:18.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:18.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:18.24#ibcon#enter wrdev, iclass 7, count 0 2006.201.15:50:18.24#ibcon#first serial, iclass 7, count 0 2006.201.15:50:18.24#ibcon#enter sib2, iclass 7, count 0 2006.201.15:50:18.24#ibcon#flushed, iclass 7, count 0 2006.201.15:50:18.24#ibcon#about to write, iclass 7, count 0 2006.201.15:50:18.24#ibcon#wrote, iclass 7, count 0 2006.201.15:50:18.24#ibcon#about to read 3, iclass 7, count 0 2006.201.15:50:18.26#ibcon#read 3, iclass 7, count 0 2006.201.15:50:18.26#ibcon#about to read 4, iclass 7, count 0 2006.201.15:50:18.26#ibcon#read 4, iclass 7, count 0 2006.201.15:50:18.26#ibcon#about to read 5, iclass 7, count 0 2006.201.15:50:18.26#ibcon#read 5, iclass 7, count 0 2006.201.15:50:18.26#ibcon#about to read 6, iclass 7, count 0 2006.201.15:50:18.26#ibcon#read 6, iclass 7, count 0 2006.201.15:50:18.26#ibcon#end of sib2, iclass 7, count 0 2006.201.15:50:18.26#ibcon#*mode == 0, iclass 7, count 0 2006.201.15:50:18.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.15:50:18.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:50:18.26#ibcon#*before write, iclass 7, count 0 2006.201.15:50:18.26#ibcon#enter sib2, iclass 7, count 0 2006.201.15:50:18.26#ibcon#flushed, iclass 7, count 0 2006.201.15:50:18.26#ibcon#about to write, iclass 7, count 0 2006.201.15:50:18.26#ibcon#wrote, iclass 7, count 0 2006.201.15:50:18.26#ibcon#about to read 3, iclass 7, count 0 2006.201.15:50:18.30#ibcon#read 3, iclass 7, count 0 2006.201.15:50:18.30#ibcon#about to read 4, iclass 7, count 0 2006.201.15:50:18.30#ibcon#read 4, iclass 7, count 0 2006.201.15:50:18.30#ibcon#about to read 5, iclass 7, count 0 2006.201.15:50:18.30#ibcon#read 5, iclass 7, count 0 2006.201.15:50:18.30#ibcon#about to read 6, iclass 7, count 0 2006.201.15:50:18.30#ibcon#read 6, iclass 7, count 0 2006.201.15:50:18.30#ibcon#end of sib2, iclass 7, count 0 2006.201.15:50:18.30#ibcon#*after write, iclass 7, count 0 2006.201.15:50:18.30#ibcon#*before return 0, iclass 7, count 0 2006.201.15:50:18.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:18.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:18.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.15:50:18.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.15:50:18.30$vck44/va=8,4 2006.201.15:50:18.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.15:50:18.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.15:50:18.30#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:18.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:50:18.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:50:18.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:50:18.36#ibcon#enter wrdev, iclass 11, count 2 2006.201.15:50:18.36#ibcon#first serial, iclass 11, count 2 2006.201.15:50:18.36#ibcon#enter sib2, iclass 11, count 2 2006.201.15:50:18.36#ibcon#flushed, iclass 11, count 2 2006.201.15:50:18.36#ibcon#about to write, iclass 11, count 2 2006.201.15:50:18.36#ibcon#wrote, iclass 11, count 2 2006.201.15:50:18.36#ibcon#about to read 3, iclass 11, count 2 2006.201.15:50:18.38#ibcon#read 3, iclass 11, count 2 2006.201.15:50:18.38#ibcon#about to read 4, iclass 11, count 2 2006.201.15:50:18.38#ibcon#read 4, iclass 11, count 2 2006.201.15:50:18.38#ibcon#about to read 5, iclass 11, count 2 2006.201.15:50:18.38#ibcon#read 5, iclass 11, count 2 2006.201.15:50:18.38#ibcon#about to read 6, iclass 11, count 2 2006.201.15:50:18.38#ibcon#read 6, iclass 11, count 2 2006.201.15:50:18.38#ibcon#end of sib2, iclass 11, count 2 2006.201.15:50:18.38#ibcon#*mode == 0, iclass 11, count 2 2006.201.15:50:18.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.15:50:18.38#ibcon#[25=AT08-04\r\n] 2006.201.15:50:18.38#ibcon#*before write, iclass 11, count 2 2006.201.15:50:18.38#ibcon#enter sib2, iclass 11, count 2 2006.201.15:50:18.38#ibcon#flushed, iclass 11, count 2 2006.201.15:50:18.38#ibcon#about to write, iclass 11, count 2 2006.201.15:50:18.38#ibcon#wrote, iclass 11, count 2 2006.201.15:50:18.38#ibcon#about to read 3, iclass 11, count 2 2006.201.15:50:18.41#ibcon#read 3, iclass 11, count 2 2006.201.15:50:18.41#ibcon#about to read 4, iclass 11, count 2 2006.201.15:50:18.41#ibcon#read 4, iclass 11, count 2 2006.201.15:50:18.41#ibcon#about to read 5, iclass 11, count 2 2006.201.15:50:18.41#ibcon#read 5, iclass 11, count 2 2006.201.15:50:18.41#ibcon#about to read 6, iclass 11, count 2 2006.201.15:50:18.41#ibcon#read 6, iclass 11, count 2 2006.201.15:50:18.41#ibcon#end of sib2, iclass 11, count 2 2006.201.15:50:18.41#ibcon#*after write, iclass 11, count 2 2006.201.15:50:18.41#ibcon#*before return 0, iclass 11, count 2 2006.201.15:50:18.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:50:18.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.15:50:18.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.15:50:18.41#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:18.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:50:18.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:50:18.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:50:18.53#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:50:18.53#ibcon#first serial, iclass 11, count 0 2006.201.15:50:18.53#ibcon#enter sib2, iclass 11, count 0 2006.201.15:50:18.53#ibcon#flushed, iclass 11, count 0 2006.201.15:50:18.53#ibcon#about to write, iclass 11, count 0 2006.201.15:50:18.53#ibcon#wrote, iclass 11, count 0 2006.201.15:50:18.53#ibcon#about to read 3, iclass 11, count 0 2006.201.15:50:18.55#ibcon#read 3, iclass 11, count 0 2006.201.15:50:18.55#ibcon#about to read 4, iclass 11, count 0 2006.201.15:50:18.55#ibcon#read 4, iclass 11, count 0 2006.201.15:50:18.55#ibcon#about to read 5, iclass 11, count 0 2006.201.15:50:18.55#ibcon#read 5, iclass 11, count 0 2006.201.15:50:18.55#ibcon#about to read 6, iclass 11, count 0 2006.201.15:50:18.55#ibcon#read 6, iclass 11, count 0 2006.201.15:50:18.55#ibcon#end of sib2, iclass 11, count 0 2006.201.15:50:18.55#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:50:18.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:50:18.55#ibcon#[25=USB\r\n] 2006.201.15:50:18.55#ibcon#*before write, iclass 11, count 0 2006.201.15:50:18.55#ibcon#enter sib2, iclass 11, count 0 2006.201.15:50:18.55#ibcon#flushed, iclass 11, count 0 2006.201.15:50:18.55#ibcon#about to write, iclass 11, count 0 2006.201.15:50:18.55#ibcon#wrote, iclass 11, count 0 2006.201.15:50:18.55#ibcon#about to read 3, iclass 11, count 0 2006.201.15:50:18.58#ibcon#read 3, iclass 11, count 0 2006.201.15:50:18.58#ibcon#about to read 4, iclass 11, count 0 2006.201.15:50:18.58#ibcon#read 4, iclass 11, count 0 2006.201.15:50:18.58#ibcon#about to read 5, iclass 11, count 0 2006.201.15:50:18.58#ibcon#read 5, iclass 11, count 0 2006.201.15:50:18.58#ibcon#about to read 6, iclass 11, count 0 2006.201.15:50:18.58#ibcon#read 6, iclass 11, count 0 2006.201.15:50:18.58#ibcon#end of sib2, iclass 11, count 0 2006.201.15:50:18.58#ibcon#*after write, iclass 11, count 0 2006.201.15:50:18.58#ibcon#*before return 0, iclass 11, count 0 2006.201.15:50:18.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:50:18.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.15:50:18.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:50:18.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:50:18.58$vck44/vblo=1,629.99 2006.201.15:50:18.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.15:50:18.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.15:50:18.58#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:18.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:18.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:18.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:18.58#ibcon#enter wrdev, iclass 13, count 0 2006.201.15:50:18.58#ibcon#first serial, iclass 13, count 0 2006.201.15:50:18.58#ibcon#enter sib2, iclass 13, count 0 2006.201.15:50:18.58#ibcon#flushed, iclass 13, count 0 2006.201.15:50:18.58#ibcon#about to write, iclass 13, count 0 2006.201.15:50:18.58#ibcon#wrote, iclass 13, count 0 2006.201.15:50:18.58#ibcon#about to read 3, iclass 13, count 0 2006.201.15:50:18.60#ibcon#read 3, iclass 13, count 0 2006.201.15:50:18.60#ibcon#about to read 4, iclass 13, count 0 2006.201.15:50:18.60#ibcon#read 4, iclass 13, count 0 2006.201.15:50:18.60#ibcon#about to read 5, iclass 13, count 0 2006.201.15:50:18.60#ibcon#read 5, iclass 13, count 0 2006.201.15:50:18.60#ibcon#about to read 6, iclass 13, count 0 2006.201.15:50:18.60#ibcon#read 6, iclass 13, count 0 2006.201.15:50:18.60#ibcon#end of sib2, iclass 13, count 0 2006.201.15:50:18.60#ibcon#*mode == 0, iclass 13, count 0 2006.201.15:50:18.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.15:50:18.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:50:18.60#ibcon#*before write, iclass 13, count 0 2006.201.15:50:18.60#ibcon#enter sib2, iclass 13, count 0 2006.201.15:50:18.60#ibcon#flushed, iclass 13, count 0 2006.201.15:50:18.60#ibcon#about to write, iclass 13, count 0 2006.201.15:50:18.60#ibcon#wrote, iclass 13, count 0 2006.201.15:50:18.60#ibcon#about to read 3, iclass 13, count 0 2006.201.15:50:18.64#ibcon#read 3, iclass 13, count 0 2006.201.15:50:18.64#ibcon#about to read 4, iclass 13, count 0 2006.201.15:50:18.64#ibcon#read 4, iclass 13, count 0 2006.201.15:50:18.64#ibcon#about to read 5, iclass 13, count 0 2006.201.15:50:18.64#ibcon#read 5, iclass 13, count 0 2006.201.15:50:18.64#ibcon#about to read 6, iclass 13, count 0 2006.201.15:50:18.64#ibcon#read 6, iclass 13, count 0 2006.201.15:50:18.64#ibcon#end of sib2, iclass 13, count 0 2006.201.15:50:18.64#ibcon#*after write, iclass 13, count 0 2006.201.15:50:18.64#ibcon#*before return 0, iclass 13, count 0 2006.201.15:50:18.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:18.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.15:50:18.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.15:50:18.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.15:50:18.64$vck44/vb=1,4 2006.201.15:50:18.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.15:50:18.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.15:50:18.64#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:18.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:18.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:18.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:18.64#ibcon#enter wrdev, iclass 15, count 2 2006.201.15:50:18.64#ibcon#first serial, iclass 15, count 2 2006.201.15:50:18.64#ibcon#enter sib2, iclass 15, count 2 2006.201.15:50:18.64#ibcon#flushed, iclass 15, count 2 2006.201.15:50:18.64#ibcon#about to write, iclass 15, count 2 2006.201.15:50:18.64#ibcon#wrote, iclass 15, count 2 2006.201.15:50:18.64#ibcon#about to read 3, iclass 15, count 2 2006.201.15:50:18.66#ibcon#read 3, iclass 15, count 2 2006.201.15:50:18.66#ibcon#about to read 4, iclass 15, count 2 2006.201.15:50:18.66#ibcon#read 4, iclass 15, count 2 2006.201.15:50:18.66#ibcon#about to read 5, iclass 15, count 2 2006.201.15:50:18.66#ibcon#read 5, iclass 15, count 2 2006.201.15:50:18.66#ibcon#about to read 6, iclass 15, count 2 2006.201.15:50:18.66#ibcon#read 6, iclass 15, count 2 2006.201.15:50:18.66#ibcon#end of sib2, iclass 15, count 2 2006.201.15:50:18.66#ibcon#*mode == 0, iclass 15, count 2 2006.201.15:50:18.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.15:50:18.66#ibcon#[27=AT01-04\r\n] 2006.201.15:50:18.66#ibcon#*before write, iclass 15, count 2 2006.201.15:50:18.66#ibcon#enter sib2, iclass 15, count 2 2006.201.15:50:18.66#ibcon#flushed, iclass 15, count 2 2006.201.15:50:18.66#ibcon#about to write, iclass 15, count 2 2006.201.15:50:18.66#ibcon#wrote, iclass 15, count 2 2006.201.15:50:18.66#ibcon#about to read 3, iclass 15, count 2 2006.201.15:50:18.69#ibcon#read 3, iclass 15, count 2 2006.201.15:50:18.69#ibcon#about to read 4, iclass 15, count 2 2006.201.15:50:18.69#ibcon#read 4, iclass 15, count 2 2006.201.15:50:18.69#ibcon#about to read 5, iclass 15, count 2 2006.201.15:50:18.69#ibcon#read 5, iclass 15, count 2 2006.201.15:50:18.69#ibcon#about to read 6, iclass 15, count 2 2006.201.15:50:18.69#ibcon#read 6, iclass 15, count 2 2006.201.15:50:18.69#ibcon#end of sib2, iclass 15, count 2 2006.201.15:50:18.69#ibcon#*after write, iclass 15, count 2 2006.201.15:50:18.69#ibcon#*before return 0, iclass 15, count 2 2006.201.15:50:18.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:18.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.15:50:18.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.15:50:18.69#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:18.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:18.81#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:18.81#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:18.81#ibcon#enter wrdev, iclass 15, count 0 2006.201.15:50:18.81#ibcon#first serial, iclass 15, count 0 2006.201.15:50:18.81#ibcon#enter sib2, iclass 15, count 0 2006.201.15:50:18.81#ibcon#flushed, iclass 15, count 0 2006.201.15:50:18.81#ibcon#about to write, iclass 15, count 0 2006.201.15:50:18.81#ibcon#wrote, iclass 15, count 0 2006.201.15:50:18.81#ibcon#about to read 3, iclass 15, count 0 2006.201.15:50:18.83#ibcon#read 3, iclass 15, count 0 2006.201.15:50:18.83#ibcon#about to read 4, iclass 15, count 0 2006.201.15:50:18.83#ibcon#read 4, iclass 15, count 0 2006.201.15:50:18.83#ibcon#about to read 5, iclass 15, count 0 2006.201.15:50:18.83#ibcon#read 5, iclass 15, count 0 2006.201.15:50:18.83#ibcon#about to read 6, iclass 15, count 0 2006.201.15:50:18.83#ibcon#read 6, iclass 15, count 0 2006.201.15:50:18.83#ibcon#end of sib2, iclass 15, count 0 2006.201.15:50:18.83#ibcon#*mode == 0, iclass 15, count 0 2006.201.15:50:18.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.15:50:18.83#ibcon#[27=USB\r\n] 2006.201.15:50:18.83#ibcon#*before write, iclass 15, count 0 2006.201.15:50:18.83#ibcon#enter sib2, iclass 15, count 0 2006.201.15:50:18.83#ibcon#flushed, iclass 15, count 0 2006.201.15:50:18.83#ibcon#about to write, iclass 15, count 0 2006.201.15:50:18.83#ibcon#wrote, iclass 15, count 0 2006.201.15:50:18.83#ibcon#about to read 3, iclass 15, count 0 2006.201.15:50:18.86#ibcon#read 3, iclass 15, count 0 2006.201.15:50:18.86#ibcon#about to read 4, iclass 15, count 0 2006.201.15:50:18.86#ibcon#read 4, iclass 15, count 0 2006.201.15:50:18.86#ibcon#about to read 5, iclass 15, count 0 2006.201.15:50:18.86#ibcon#read 5, iclass 15, count 0 2006.201.15:50:18.86#ibcon#about to read 6, iclass 15, count 0 2006.201.15:50:18.86#ibcon#read 6, iclass 15, count 0 2006.201.15:50:18.86#ibcon#end of sib2, iclass 15, count 0 2006.201.15:50:18.86#ibcon#*after write, iclass 15, count 0 2006.201.15:50:18.86#ibcon#*before return 0, iclass 15, count 0 2006.201.15:50:18.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:18.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.15:50:18.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.15:50:18.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.15:50:18.86$vck44/vblo=2,634.99 2006.201.15:50:18.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.15:50:18.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.15:50:18.86#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:18.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:18.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:18.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:18.86#ibcon#enter wrdev, iclass 17, count 0 2006.201.15:50:18.86#ibcon#first serial, iclass 17, count 0 2006.201.15:50:18.86#ibcon#enter sib2, iclass 17, count 0 2006.201.15:50:18.86#ibcon#flushed, iclass 17, count 0 2006.201.15:50:18.86#ibcon#about to write, iclass 17, count 0 2006.201.15:50:18.86#ibcon#wrote, iclass 17, count 0 2006.201.15:50:18.86#ibcon#about to read 3, iclass 17, count 0 2006.201.15:50:18.88#ibcon#read 3, iclass 17, count 0 2006.201.15:50:18.88#ibcon#about to read 4, iclass 17, count 0 2006.201.15:50:18.88#ibcon#read 4, iclass 17, count 0 2006.201.15:50:18.88#ibcon#about to read 5, iclass 17, count 0 2006.201.15:50:18.88#ibcon#read 5, iclass 17, count 0 2006.201.15:50:18.88#ibcon#about to read 6, iclass 17, count 0 2006.201.15:50:18.88#ibcon#read 6, iclass 17, count 0 2006.201.15:50:18.88#ibcon#end of sib2, iclass 17, count 0 2006.201.15:50:18.88#ibcon#*mode == 0, iclass 17, count 0 2006.201.15:50:18.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.15:50:18.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:50:18.88#ibcon#*before write, iclass 17, count 0 2006.201.15:50:18.88#ibcon#enter sib2, iclass 17, count 0 2006.201.15:50:18.88#ibcon#flushed, iclass 17, count 0 2006.201.15:50:18.88#ibcon#about to write, iclass 17, count 0 2006.201.15:50:18.88#ibcon#wrote, iclass 17, count 0 2006.201.15:50:18.88#ibcon#about to read 3, iclass 17, count 0 2006.201.15:50:18.92#ibcon#read 3, iclass 17, count 0 2006.201.15:50:18.92#ibcon#about to read 4, iclass 17, count 0 2006.201.15:50:18.92#ibcon#read 4, iclass 17, count 0 2006.201.15:50:18.92#ibcon#about to read 5, iclass 17, count 0 2006.201.15:50:18.92#ibcon#read 5, iclass 17, count 0 2006.201.15:50:18.92#ibcon#about to read 6, iclass 17, count 0 2006.201.15:50:18.92#ibcon#read 6, iclass 17, count 0 2006.201.15:50:18.92#ibcon#end of sib2, iclass 17, count 0 2006.201.15:50:18.92#ibcon#*after write, iclass 17, count 0 2006.201.15:50:18.92#ibcon#*before return 0, iclass 17, count 0 2006.201.15:50:18.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:18.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.15:50:18.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.15:50:18.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.15:50:18.92$vck44/vb=2,5 2006.201.15:50:18.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.15:50:18.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.15:50:18.92#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:18.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:18.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:18.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:18.98#ibcon#enter wrdev, iclass 19, count 2 2006.201.15:50:18.98#ibcon#first serial, iclass 19, count 2 2006.201.15:50:18.98#ibcon#enter sib2, iclass 19, count 2 2006.201.15:50:18.98#ibcon#flushed, iclass 19, count 2 2006.201.15:50:18.98#ibcon#about to write, iclass 19, count 2 2006.201.15:50:18.98#ibcon#wrote, iclass 19, count 2 2006.201.15:50:18.98#ibcon#about to read 3, iclass 19, count 2 2006.201.15:50:19.00#ibcon#read 3, iclass 19, count 2 2006.201.15:50:19.00#ibcon#about to read 4, iclass 19, count 2 2006.201.15:50:19.00#ibcon#read 4, iclass 19, count 2 2006.201.15:50:19.00#ibcon#about to read 5, iclass 19, count 2 2006.201.15:50:19.00#ibcon#read 5, iclass 19, count 2 2006.201.15:50:19.00#ibcon#about to read 6, iclass 19, count 2 2006.201.15:50:19.00#ibcon#read 6, iclass 19, count 2 2006.201.15:50:19.00#ibcon#end of sib2, iclass 19, count 2 2006.201.15:50:19.00#ibcon#*mode == 0, iclass 19, count 2 2006.201.15:50:19.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.15:50:19.00#ibcon#[27=AT02-05\r\n] 2006.201.15:50:19.00#ibcon#*before write, iclass 19, count 2 2006.201.15:50:19.00#ibcon#enter sib2, iclass 19, count 2 2006.201.15:50:19.00#ibcon#flushed, iclass 19, count 2 2006.201.15:50:19.00#ibcon#about to write, iclass 19, count 2 2006.201.15:50:19.00#ibcon#wrote, iclass 19, count 2 2006.201.15:50:19.00#ibcon#about to read 3, iclass 19, count 2 2006.201.15:50:19.03#ibcon#read 3, iclass 19, count 2 2006.201.15:50:19.03#ibcon#about to read 4, iclass 19, count 2 2006.201.15:50:19.03#ibcon#read 4, iclass 19, count 2 2006.201.15:50:19.03#ibcon#about to read 5, iclass 19, count 2 2006.201.15:50:19.03#ibcon#read 5, iclass 19, count 2 2006.201.15:50:19.03#ibcon#about to read 6, iclass 19, count 2 2006.201.15:50:19.03#ibcon#read 6, iclass 19, count 2 2006.201.15:50:19.03#ibcon#end of sib2, iclass 19, count 2 2006.201.15:50:19.03#ibcon#*after write, iclass 19, count 2 2006.201.15:50:19.03#ibcon#*before return 0, iclass 19, count 2 2006.201.15:50:19.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:19.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.15:50:19.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.15:50:19.03#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:19.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:19.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:19.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:19.15#ibcon#enter wrdev, iclass 19, count 0 2006.201.15:50:19.15#ibcon#first serial, iclass 19, count 0 2006.201.15:50:19.15#ibcon#enter sib2, iclass 19, count 0 2006.201.15:50:19.15#ibcon#flushed, iclass 19, count 0 2006.201.15:50:19.15#ibcon#about to write, iclass 19, count 0 2006.201.15:50:19.15#ibcon#wrote, iclass 19, count 0 2006.201.15:50:19.15#ibcon#about to read 3, iclass 19, count 0 2006.201.15:50:19.17#ibcon#read 3, iclass 19, count 0 2006.201.15:50:19.17#ibcon#about to read 4, iclass 19, count 0 2006.201.15:50:19.17#ibcon#read 4, iclass 19, count 0 2006.201.15:50:19.17#ibcon#about to read 5, iclass 19, count 0 2006.201.15:50:19.17#ibcon#read 5, iclass 19, count 0 2006.201.15:50:19.17#ibcon#about to read 6, iclass 19, count 0 2006.201.15:50:19.17#ibcon#read 6, iclass 19, count 0 2006.201.15:50:19.17#ibcon#end of sib2, iclass 19, count 0 2006.201.15:50:19.17#ibcon#*mode == 0, iclass 19, count 0 2006.201.15:50:19.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.15:50:19.17#ibcon#[27=USB\r\n] 2006.201.15:50:19.17#ibcon#*before write, iclass 19, count 0 2006.201.15:50:19.17#ibcon#enter sib2, iclass 19, count 0 2006.201.15:50:19.17#ibcon#flushed, iclass 19, count 0 2006.201.15:50:19.17#ibcon#about to write, iclass 19, count 0 2006.201.15:50:19.17#ibcon#wrote, iclass 19, count 0 2006.201.15:50:19.17#ibcon#about to read 3, iclass 19, count 0 2006.201.15:50:19.20#ibcon#read 3, iclass 19, count 0 2006.201.15:50:19.20#ibcon#about to read 4, iclass 19, count 0 2006.201.15:50:19.20#ibcon#read 4, iclass 19, count 0 2006.201.15:50:19.20#ibcon#about to read 5, iclass 19, count 0 2006.201.15:50:19.20#ibcon#read 5, iclass 19, count 0 2006.201.15:50:19.20#ibcon#about to read 6, iclass 19, count 0 2006.201.15:50:19.20#ibcon#read 6, iclass 19, count 0 2006.201.15:50:19.20#ibcon#end of sib2, iclass 19, count 0 2006.201.15:50:19.20#ibcon#*after write, iclass 19, count 0 2006.201.15:50:19.20#ibcon#*before return 0, iclass 19, count 0 2006.201.15:50:19.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:19.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.15:50:19.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.15:50:19.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.15:50:19.20$vck44/vblo=3,649.99 2006.201.15:50:19.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.15:50:19.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.15:50:19.20#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:19.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:50:19.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:50:19.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:50:19.20#ibcon#enter wrdev, iclass 21, count 0 2006.201.15:50:19.20#ibcon#first serial, iclass 21, count 0 2006.201.15:50:19.20#ibcon#enter sib2, iclass 21, count 0 2006.201.15:50:19.20#ibcon#flushed, iclass 21, count 0 2006.201.15:50:19.20#ibcon#about to write, iclass 21, count 0 2006.201.15:50:19.20#ibcon#wrote, iclass 21, count 0 2006.201.15:50:19.20#ibcon#about to read 3, iclass 21, count 0 2006.201.15:50:19.22#ibcon#read 3, iclass 21, count 0 2006.201.15:50:19.22#ibcon#about to read 4, iclass 21, count 0 2006.201.15:50:19.22#ibcon#read 4, iclass 21, count 0 2006.201.15:50:19.22#ibcon#about to read 5, iclass 21, count 0 2006.201.15:50:19.22#ibcon#read 5, iclass 21, count 0 2006.201.15:50:19.22#ibcon#about to read 6, iclass 21, count 0 2006.201.15:50:19.22#ibcon#read 6, iclass 21, count 0 2006.201.15:50:19.22#ibcon#end of sib2, iclass 21, count 0 2006.201.15:50:19.22#ibcon#*mode == 0, iclass 21, count 0 2006.201.15:50:19.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.15:50:19.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:50:19.22#ibcon#*before write, iclass 21, count 0 2006.201.15:50:19.22#ibcon#enter sib2, iclass 21, count 0 2006.201.15:50:19.22#ibcon#flushed, iclass 21, count 0 2006.201.15:50:19.22#ibcon#about to write, iclass 21, count 0 2006.201.15:50:19.22#ibcon#wrote, iclass 21, count 0 2006.201.15:50:19.22#ibcon#about to read 3, iclass 21, count 0 2006.201.15:50:19.27#ibcon#read 3, iclass 21, count 0 2006.201.15:50:19.27#ibcon#about to read 4, iclass 21, count 0 2006.201.15:50:19.27#ibcon#read 4, iclass 21, count 0 2006.201.15:50:19.27#ibcon#about to read 5, iclass 21, count 0 2006.201.15:50:19.27#ibcon#read 5, iclass 21, count 0 2006.201.15:50:19.27#ibcon#about to read 6, iclass 21, count 0 2006.201.15:50:19.27#ibcon#read 6, iclass 21, count 0 2006.201.15:50:19.27#ibcon#end of sib2, iclass 21, count 0 2006.201.15:50:19.27#ibcon#*after write, iclass 21, count 0 2006.201.15:50:19.27#ibcon#*before return 0, iclass 21, count 0 2006.201.15:50:19.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:50:19.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.15:50:19.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.15:50:19.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.15:50:19.27$vck44/vb=3,4 2006.201.15:50:19.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.15:50:19.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.15:50:19.27#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:19.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:50:19.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:50:19.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:50:19.32#ibcon#enter wrdev, iclass 23, count 2 2006.201.15:50:19.32#ibcon#first serial, iclass 23, count 2 2006.201.15:50:19.32#ibcon#enter sib2, iclass 23, count 2 2006.201.15:50:19.32#ibcon#flushed, iclass 23, count 2 2006.201.15:50:19.32#ibcon#about to write, iclass 23, count 2 2006.201.15:50:19.32#ibcon#wrote, iclass 23, count 2 2006.201.15:50:19.32#ibcon#about to read 3, iclass 23, count 2 2006.201.15:50:19.34#ibcon#read 3, iclass 23, count 2 2006.201.15:50:19.34#ibcon#about to read 4, iclass 23, count 2 2006.201.15:50:19.34#ibcon#read 4, iclass 23, count 2 2006.201.15:50:19.34#ibcon#about to read 5, iclass 23, count 2 2006.201.15:50:19.34#ibcon#read 5, iclass 23, count 2 2006.201.15:50:19.34#ibcon#about to read 6, iclass 23, count 2 2006.201.15:50:19.34#ibcon#read 6, iclass 23, count 2 2006.201.15:50:19.34#ibcon#end of sib2, iclass 23, count 2 2006.201.15:50:19.34#ibcon#*mode == 0, iclass 23, count 2 2006.201.15:50:19.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.15:50:19.34#ibcon#[27=AT03-04\r\n] 2006.201.15:50:19.34#ibcon#*before write, iclass 23, count 2 2006.201.15:50:19.34#ibcon#enter sib2, iclass 23, count 2 2006.201.15:50:19.34#ibcon#flushed, iclass 23, count 2 2006.201.15:50:19.34#ibcon#about to write, iclass 23, count 2 2006.201.15:50:19.34#ibcon#wrote, iclass 23, count 2 2006.201.15:50:19.34#ibcon#about to read 3, iclass 23, count 2 2006.201.15:50:19.37#ibcon#read 3, iclass 23, count 2 2006.201.15:50:19.37#ibcon#about to read 4, iclass 23, count 2 2006.201.15:50:19.37#ibcon#read 4, iclass 23, count 2 2006.201.15:50:19.37#ibcon#about to read 5, iclass 23, count 2 2006.201.15:50:19.37#ibcon#read 5, iclass 23, count 2 2006.201.15:50:19.37#ibcon#about to read 6, iclass 23, count 2 2006.201.15:50:19.37#ibcon#read 6, iclass 23, count 2 2006.201.15:50:19.37#ibcon#end of sib2, iclass 23, count 2 2006.201.15:50:19.37#ibcon#*after write, iclass 23, count 2 2006.201.15:50:19.37#ibcon#*before return 0, iclass 23, count 2 2006.201.15:50:19.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:50:19.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.15:50:19.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.15:50:19.37#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:19.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:50:19.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:50:19.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:50:19.49#ibcon#enter wrdev, iclass 23, count 0 2006.201.15:50:19.49#ibcon#first serial, iclass 23, count 0 2006.201.15:50:19.49#ibcon#enter sib2, iclass 23, count 0 2006.201.15:50:19.49#ibcon#flushed, iclass 23, count 0 2006.201.15:50:19.49#ibcon#about to write, iclass 23, count 0 2006.201.15:50:19.49#ibcon#wrote, iclass 23, count 0 2006.201.15:50:19.49#ibcon#about to read 3, iclass 23, count 0 2006.201.15:50:19.51#ibcon#read 3, iclass 23, count 0 2006.201.15:50:19.51#ibcon#about to read 4, iclass 23, count 0 2006.201.15:50:19.51#ibcon#read 4, iclass 23, count 0 2006.201.15:50:19.51#ibcon#about to read 5, iclass 23, count 0 2006.201.15:50:19.51#ibcon#read 5, iclass 23, count 0 2006.201.15:50:19.51#ibcon#about to read 6, iclass 23, count 0 2006.201.15:50:19.51#ibcon#read 6, iclass 23, count 0 2006.201.15:50:19.51#ibcon#end of sib2, iclass 23, count 0 2006.201.15:50:19.51#ibcon#*mode == 0, iclass 23, count 0 2006.201.15:50:19.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.15:50:19.51#ibcon#[27=USB\r\n] 2006.201.15:50:19.51#ibcon#*before write, iclass 23, count 0 2006.201.15:50:19.51#ibcon#enter sib2, iclass 23, count 0 2006.201.15:50:19.51#ibcon#flushed, iclass 23, count 0 2006.201.15:50:19.51#ibcon#about to write, iclass 23, count 0 2006.201.15:50:19.51#ibcon#wrote, iclass 23, count 0 2006.201.15:50:19.51#ibcon#about to read 3, iclass 23, count 0 2006.201.15:50:19.54#ibcon#read 3, iclass 23, count 0 2006.201.15:50:19.54#ibcon#about to read 4, iclass 23, count 0 2006.201.15:50:19.54#ibcon#read 4, iclass 23, count 0 2006.201.15:50:19.54#ibcon#about to read 5, iclass 23, count 0 2006.201.15:50:19.54#ibcon#read 5, iclass 23, count 0 2006.201.15:50:19.54#ibcon#about to read 6, iclass 23, count 0 2006.201.15:50:19.54#ibcon#read 6, iclass 23, count 0 2006.201.15:50:19.54#ibcon#end of sib2, iclass 23, count 0 2006.201.15:50:19.54#ibcon#*after write, iclass 23, count 0 2006.201.15:50:19.54#ibcon#*before return 0, iclass 23, count 0 2006.201.15:50:19.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:50:19.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.15:50:19.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.15:50:19.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.15:50:19.54$vck44/vblo=4,679.99 2006.201.15:50:19.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.15:50:19.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.15:50:19.54#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:19.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:50:19.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:50:19.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:50:19.54#ibcon#enter wrdev, iclass 25, count 0 2006.201.15:50:19.54#ibcon#first serial, iclass 25, count 0 2006.201.15:50:19.54#ibcon#enter sib2, iclass 25, count 0 2006.201.15:50:19.54#ibcon#flushed, iclass 25, count 0 2006.201.15:50:19.54#ibcon#about to write, iclass 25, count 0 2006.201.15:50:19.54#ibcon#wrote, iclass 25, count 0 2006.201.15:50:19.54#ibcon#about to read 3, iclass 25, count 0 2006.201.15:50:19.56#ibcon#read 3, iclass 25, count 0 2006.201.15:50:19.56#ibcon#about to read 4, iclass 25, count 0 2006.201.15:50:19.56#ibcon#read 4, iclass 25, count 0 2006.201.15:50:19.56#ibcon#about to read 5, iclass 25, count 0 2006.201.15:50:19.56#ibcon#read 5, iclass 25, count 0 2006.201.15:50:19.56#ibcon#about to read 6, iclass 25, count 0 2006.201.15:50:19.56#ibcon#read 6, iclass 25, count 0 2006.201.15:50:19.56#ibcon#end of sib2, iclass 25, count 0 2006.201.15:50:19.56#ibcon#*mode == 0, iclass 25, count 0 2006.201.15:50:19.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.15:50:19.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:50:19.56#ibcon#*before write, iclass 25, count 0 2006.201.15:50:19.56#ibcon#enter sib2, iclass 25, count 0 2006.201.15:50:19.56#ibcon#flushed, iclass 25, count 0 2006.201.15:50:19.56#ibcon#about to write, iclass 25, count 0 2006.201.15:50:19.56#ibcon#wrote, iclass 25, count 0 2006.201.15:50:19.56#ibcon#about to read 3, iclass 25, count 0 2006.201.15:50:19.60#ibcon#read 3, iclass 25, count 0 2006.201.15:50:19.60#ibcon#about to read 4, iclass 25, count 0 2006.201.15:50:19.60#ibcon#read 4, iclass 25, count 0 2006.201.15:50:19.60#ibcon#about to read 5, iclass 25, count 0 2006.201.15:50:19.60#ibcon#read 5, iclass 25, count 0 2006.201.15:50:19.60#ibcon#about to read 6, iclass 25, count 0 2006.201.15:50:19.60#ibcon#read 6, iclass 25, count 0 2006.201.15:50:19.60#ibcon#end of sib2, iclass 25, count 0 2006.201.15:50:19.60#ibcon#*after write, iclass 25, count 0 2006.201.15:50:19.60#ibcon#*before return 0, iclass 25, count 0 2006.201.15:50:19.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:50:19.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.15:50:19.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.15:50:19.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.15:50:19.60$vck44/vb=4,5 2006.201.15:50:19.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.15:50:19.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.15:50:19.60#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:19.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:19.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:19.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:19.66#ibcon#enter wrdev, iclass 27, count 2 2006.201.15:50:19.66#ibcon#first serial, iclass 27, count 2 2006.201.15:50:19.66#ibcon#enter sib2, iclass 27, count 2 2006.201.15:50:19.66#ibcon#flushed, iclass 27, count 2 2006.201.15:50:19.66#ibcon#about to write, iclass 27, count 2 2006.201.15:50:19.66#ibcon#wrote, iclass 27, count 2 2006.201.15:50:19.66#ibcon#about to read 3, iclass 27, count 2 2006.201.15:50:19.68#ibcon#read 3, iclass 27, count 2 2006.201.15:50:19.68#ibcon#about to read 4, iclass 27, count 2 2006.201.15:50:19.68#ibcon#read 4, iclass 27, count 2 2006.201.15:50:19.68#ibcon#about to read 5, iclass 27, count 2 2006.201.15:50:19.68#ibcon#read 5, iclass 27, count 2 2006.201.15:50:19.68#ibcon#about to read 6, iclass 27, count 2 2006.201.15:50:19.68#ibcon#read 6, iclass 27, count 2 2006.201.15:50:19.68#ibcon#end of sib2, iclass 27, count 2 2006.201.15:50:19.68#ibcon#*mode == 0, iclass 27, count 2 2006.201.15:50:19.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.15:50:19.68#ibcon#[27=AT04-05\r\n] 2006.201.15:50:19.68#ibcon#*before write, iclass 27, count 2 2006.201.15:50:19.68#ibcon#enter sib2, iclass 27, count 2 2006.201.15:50:19.68#ibcon#flushed, iclass 27, count 2 2006.201.15:50:19.68#ibcon#about to write, iclass 27, count 2 2006.201.15:50:19.68#ibcon#wrote, iclass 27, count 2 2006.201.15:50:19.68#ibcon#about to read 3, iclass 27, count 2 2006.201.15:50:19.71#ibcon#read 3, iclass 27, count 2 2006.201.15:50:19.71#ibcon#about to read 4, iclass 27, count 2 2006.201.15:50:19.71#ibcon#read 4, iclass 27, count 2 2006.201.15:50:19.71#ibcon#about to read 5, iclass 27, count 2 2006.201.15:50:19.71#ibcon#read 5, iclass 27, count 2 2006.201.15:50:19.71#ibcon#about to read 6, iclass 27, count 2 2006.201.15:50:19.71#ibcon#read 6, iclass 27, count 2 2006.201.15:50:19.71#ibcon#end of sib2, iclass 27, count 2 2006.201.15:50:19.71#ibcon#*after write, iclass 27, count 2 2006.201.15:50:19.71#ibcon#*before return 0, iclass 27, count 2 2006.201.15:50:19.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:19.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.15:50:19.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.15:50:19.71#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:19.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:19.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:19.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:19.83#ibcon#enter wrdev, iclass 27, count 0 2006.201.15:50:19.83#ibcon#first serial, iclass 27, count 0 2006.201.15:50:19.83#ibcon#enter sib2, iclass 27, count 0 2006.201.15:50:19.83#ibcon#flushed, iclass 27, count 0 2006.201.15:50:19.83#ibcon#about to write, iclass 27, count 0 2006.201.15:50:19.83#ibcon#wrote, iclass 27, count 0 2006.201.15:50:19.83#ibcon#about to read 3, iclass 27, count 0 2006.201.15:50:19.85#ibcon#read 3, iclass 27, count 0 2006.201.15:50:19.85#ibcon#about to read 4, iclass 27, count 0 2006.201.15:50:19.85#ibcon#read 4, iclass 27, count 0 2006.201.15:50:19.85#ibcon#about to read 5, iclass 27, count 0 2006.201.15:50:19.85#ibcon#read 5, iclass 27, count 0 2006.201.15:50:19.85#ibcon#about to read 6, iclass 27, count 0 2006.201.15:50:19.85#ibcon#read 6, iclass 27, count 0 2006.201.15:50:19.85#ibcon#end of sib2, iclass 27, count 0 2006.201.15:50:19.85#ibcon#*mode == 0, iclass 27, count 0 2006.201.15:50:19.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.15:50:19.85#ibcon#[27=USB\r\n] 2006.201.15:50:19.85#ibcon#*before write, iclass 27, count 0 2006.201.15:50:19.85#ibcon#enter sib2, iclass 27, count 0 2006.201.15:50:19.85#ibcon#flushed, iclass 27, count 0 2006.201.15:50:19.85#ibcon#about to write, iclass 27, count 0 2006.201.15:50:19.85#ibcon#wrote, iclass 27, count 0 2006.201.15:50:19.85#ibcon#about to read 3, iclass 27, count 0 2006.201.15:50:19.88#ibcon#read 3, iclass 27, count 0 2006.201.15:50:19.88#ibcon#about to read 4, iclass 27, count 0 2006.201.15:50:19.88#ibcon#read 4, iclass 27, count 0 2006.201.15:50:19.88#ibcon#about to read 5, iclass 27, count 0 2006.201.15:50:19.88#ibcon#read 5, iclass 27, count 0 2006.201.15:50:19.88#ibcon#about to read 6, iclass 27, count 0 2006.201.15:50:19.88#ibcon#read 6, iclass 27, count 0 2006.201.15:50:19.88#ibcon#end of sib2, iclass 27, count 0 2006.201.15:50:19.88#ibcon#*after write, iclass 27, count 0 2006.201.15:50:19.88#ibcon#*before return 0, iclass 27, count 0 2006.201.15:50:19.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:19.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.15:50:19.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.15:50:19.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.15:50:19.88$vck44/vblo=5,709.99 2006.201.15:50:19.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.15:50:19.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.15:50:19.88#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:19.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:19.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:19.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:19.88#ibcon#enter wrdev, iclass 29, count 0 2006.201.15:50:19.88#ibcon#first serial, iclass 29, count 0 2006.201.15:50:19.88#ibcon#enter sib2, iclass 29, count 0 2006.201.15:50:19.88#ibcon#flushed, iclass 29, count 0 2006.201.15:50:19.88#ibcon#about to write, iclass 29, count 0 2006.201.15:50:19.88#ibcon#wrote, iclass 29, count 0 2006.201.15:50:19.88#ibcon#about to read 3, iclass 29, count 0 2006.201.15:50:19.90#ibcon#read 3, iclass 29, count 0 2006.201.15:50:19.90#ibcon#about to read 4, iclass 29, count 0 2006.201.15:50:19.90#ibcon#read 4, iclass 29, count 0 2006.201.15:50:19.90#ibcon#about to read 5, iclass 29, count 0 2006.201.15:50:19.90#ibcon#read 5, iclass 29, count 0 2006.201.15:50:19.90#ibcon#about to read 6, iclass 29, count 0 2006.201.15:50:19.90#ibcon#read 6, iclass 29, count 0 2006.201.15:50:19.90#ibcon#end of sib2, iclass 29, count 0 2006.201.15:50:19.90#ibcon#*mode == 0, iclass 29, count 0 2006.201.15:50:19.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.15:50:19.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:50:19.90#ibcon#*before write, iclass 29, count 0 2006.201.15:50:19.90#ibcon#enter sib2, iclass 29, count 0 2006.201.15:50:19.90#ibcon#flushed, iclass 29, count 0 2006.201.15:50:19.90#ibcon#about to write, iclass 29, count 0 2006.201.15:50:19.90#ibcon#wrote, iclass 29, count 0 2006.201.15:50:19.90#ibcon#about to read 3, iclass 29, count 0 2006.201.15:50:19.94#ibcon#read 3, iclass 29, count 0 2006.201.15:50:19.94#ibcon#about to read 4, iclass 29, count 0 2006.201.15:50:19.94#ibcon#read 4, iclass 29, count 0 2006.201.15:50:19.94#ibcon#about to read 5, iclass 29, count 0 2006.201.15:50:19.94#ibcon#read 5, iclass 29, count 0 2006.201.15:50:19.94#ibcon#about to read 6, iclass 29, count 0 2006.201.15:50:19.94#ibcon#read 6, iclass 29, count 0 2006.201.15:50:19.94#ibcon#end of sib2, iclass 29, count 0 2006.201.15:50:19.94#ibcon#*after write, iclass 29, count 0 2006.201.15:50:19.94#ibcon#*before return 0, iclass 29, count 0 2006.201.15:50:19.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:19.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.15:50:19.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.15:50:19.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.15:50:19.94$vck44/vb=5,4 2006.201.15:50:19.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.15:50:19.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.15:50:19.94#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:19.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:20.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:20.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:20.00#ibcon#enter wrdev, iclass 31, count 2 2006.201.15:50:20.00#ibcon#first serial, iclass 31, count 2 2006.201.15:50:20.00#ibcon#enter sib2, iclass 31, count 2 2006.201.15:50:20.00#ibcon#flushed, iclass 31, count 2 2006.201.15:50:20.00#ibcon#about to write, iclass 31, count 2 2006.201.15:50:20.00#ibcon#wrote, iclass 31, count 2 2006.201.15:50:20.00#ibcon#about to read 3, iclass 31, count 2 2006.201.15:50:20.02#ibcon#read 3, iclass 31, count 2 2006.201.15:50:20.02#ibcon#about to read 4, iclass 31, count 2 2006.201.15:50:20.02#ibcon#read 4, iclass 31, count 2 2006.201.15:50:20.02#ibcon#about to read 5, iclass 31, count 2 2006.201.15:50:20.02#ibcon#read 5, iclass 31, count 2 2006.201.15:50:20.02#ibcon#about to read 6, iclass 31, count 2 2006.201.15:50:20.02#ibcon#read 6, iclass 31, count 2 2006.201.15:50:20.02#ibcon#end of sib2, iclass 31, count 2 2006.201.15:50:20.02#ibcon#*mode == 0, iclass 31, count 2 2006.201.15:50:20.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.15:50:20.02#ibcon#[27=AT05-04\r\n] 2006.201.15:50:20.02#ibcon#*before write, iclass 31, count 2 2006.201.15:50:20.02#ibcon#enter sib2, iclass 31, count 2 2006.201.15:50:20.02#ibcon#flushed, iclass 31, count 2 2006.201.15:50:20.02#ibcon#about to write, iclass 31, count 2 2006.201.15:50:20.02#ibcon#wrote, iclass 31, count 2 2006.201.15:50:20.02#ibcon#about to read 3, iclass 31, count 2 2006.201.15:50:20.05#ibcon#read 3, iclass 31, count 2 2006.201.15:50:20.05#ibcon#about to read 4, iclass 31, count 2 2006.201.15:50:20.05#ibcon#read 4, iclass 31, count 2 2006.201.15:50:20.05#ibcon#about to read 5, iclass 31, count 2 2006.201.15:50:20.05#ibcon#read 5, iclass 31, count 2 2006.201.15:50:20.05#ibcon#about to read 6, iclass 31, count 2 2006.201.15:50:20.05#ibcon#read 6, iclass 31, count 2 2006.201.15:50:20.05#ibcon#end of sib2, iclass 31, count 2 2006.201.15:50:20.05#ibcon#*after write, iclass 31, count 2 2006.201.15:50:20.05#ibcon#*before return 0, iclass 31, count 2 2006.201.15:50:20.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:20.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.15:50:20.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.15:50:20.05#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:20.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:20.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:20.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:20.17#ibcon#enter wrdev, iclass 31, count 0 2006.201.15:50:20.17#ibcon#first serial, iclass 31, count 0 2006.201.15:50:20.17#ibcon#enter sib2, iclass 31, count 0 2006.201.15:50:20.17#ibcon#flushed, iclass 31, count 0 2006.201.15:50:20.17#ibcon#about to write, iclass 31, count 0 2006.201.15:50:20.17#ibcon#wrote, iclass 31, count 0 2006.201.15:50:20.17#ibcon#about to read 3, iclass 31, count 0 2006.201.15:50:20.19#ibcon#read 3, iclass 31, count 0 2006.201.15:50:20.19#ibcon#about to read 4, iclass 31, count 0 2006.201.15:50:20.19#ibcon#read 4, iclass 31, count 0 2006.201.15:50:20.19#ibcon#about to read 5, iclass 31, count 0 2006.201.15:50:20.19#ibcon#read 5, iclass 31, count 0 2006.201.15:50:20.19#ibcon#about to read 6, iclass 31, count 0 2006.201.15:50:20.19#ibcon#read 6, iclass 31, count 0 2006.201.15:50:20.19#ibcon#end of sib2, iclass 31, count 0 2006.201.15:50:20.19#ibcon#*mode == 0, iclass 31, count 0 2006.201.15:50:20.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.15:50:20.19#ibcon#[27=USB\r\n] 2006.201.15:50:20.19#ibcon#*before write, iclass 31, count 0 2006.201.15:50:20.19#ibcon#enter sib2, iclass 31, count 0 2006.201.15:50:20.19#ibcon#flushed, iclass 31, count 0 2006.201.15:50:20.19#ibcon#about to write, iclass 31, count 0 2006.201.15:50:20.19#ibcon#wrote, iclass 31, count 0 2006.201.15:50:20.19#ibcon#about to read 3, iclass 31, count 0 2006.201.15:50:20.22#ibcon#read 3, iclass 31, count 0 2006.201.15:50:20.22#ibcon#about to read 4, iclass 31, count 0 2006.201.15:50:20.22#ibcon#read 4, iclass 31, count 0 2006.201.15:50:20.22#ibcon#about to read 5, iclass 31, count 0 2006.201.15:50:20.22#ibcon#read 5, iclass 31, count 0 2006.201.15:50:20.22#ibcon#about to read 6, iclass 31, count 0 2006.201.15:50:20.22#ibcon#read 6, iclass 31, count 0 2006.201.15:50:20.22#ibcon#end of sib2, iclass 31, count 0 2006.201.15:50:20.22#ibcon#*after write, iclass 31, count 0 2006.201.15:50:20.22#ibcon#*before return 0, iclass 31, count 0 2006.201.15:50:20.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:20.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.15:50:20.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.15:50:20.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.15:50:20.22$vck44/vblo=6,719.99 2006.201.15:50:20.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.15:50:20.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.15:50:20.22#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:20.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:20.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:20.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:20.22#ibcon#enter wrdev, iclass 33, count 0 2006.201.15:50:20.22#ibcon#first serial, iclass 33, count 0 2006.201.15:50:20.22#ibcon#enter sib2, iclass 33, count 0 2006.201.15:50:20.22#ibcon#flushed, iclass 33, count 0 2006.201.15:50:20.22#ibcon#about to write, iclass 33, count 0 2006.201.15:50:20.22#ibcon#wrote, iclass 33, count 0 2006.201.15:50:20.22#ibcon#about to read 3, iclass 33, count 0 2006.201.15:50:20.24#ibcon#read 3, iclass 33, count 0 2006.201.15:50:20.24#ibcon#about to read 4, iclass 33, count 0 2006.201.15:50:20.24#ibcon#read 4, iclass 33, count 0 2006.201.15:50:20.24#ibcon#about to read 5, iclass 33, count 0 2006.201.15:50:20.24#ibcon#read 5, iclass 33, count 0 2006.201.15:50:20.24#ibcon#about to read 6, iclass 33, count 0 2006.201.15:50:20.24#ibcon#read 6, iclass 33, count 0 2006.201.15:50:20.24#ibcon#end of sib2, iclass 33, count 0 2006.201.15:50:20.24#ibcon#*mode == 0, iclass 33, count 0 2006.201.15:50:20.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.15:50:20.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:50:20.24#ibcon#*before write, iclass 33, count 0 2006.201.15:50:20.24#ibcon#enter sib2, iclass 33, count 0 2006.201.15:50:20.24#ibcon#flushed, iclass 33, count 0 2006.201.15:50:20.24#ibcon#about to write, iclass 33, count 0 2006.201.15:50:20.24#ibcon#wrote, iclass 33, count 0 2006.201.15:50:20.24#ibcon#about to read 3, iclass 33, count 0 2006.201.15:50:20.28#ibcon#read 3, iclass 33, count 0 2006.201.15:50:20.28#ibcon#about to read 4, iclass 33, count 0 2006.201.15:50:20.28#ibcon#read 4, iclass 33, count 0 2006.201.15:50:20.28#ibcon#about to read 5, iclass 33, count 0 2006.201.15:50:20.28#ibcon#read 5, iclass 33, count 0 2006.201.15:50:20.28#ibcon#about to read 6, iclass 33, count 0 2006.201.15:50:20.28#ibcon#read 6, iclass 33, count 0 2006.201.15:50:20.28#ibcon#end of sib2, iclass 33, count 0 2006.201.15:50:20.28#ibcon#*after write, iclass 33, count 0 2006.201.15:50:20.28#ibcon#*before return 0, iclass 33, count 0 2006.201.15:50:20.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:20.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.15:50:20.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.15:50:20.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.15:50:20.28$vck44/vb=6,4 2006.201.15:50:20.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.15:50:20.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.15:50:20.28#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:20.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:20.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:20.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:20.34#ibcon#enter wrdev, iclass 35, count 2 2006.201.15:50:20.34#ibcon#first serial, iclass 35, count 2 2006.201.15:50:20.34#ibcon#enter sib2, iclass 35, count 2 2006.201.15:50:20.34#ibcon#flushed, iclass 35, count 2 2006.201.15:50:20.34#ibcon#about to write, iclass 35, count 2 2006.201.15:50:20.34#ibcon#wrote, iclass 35, count 2 2006.201.15:50:20.34#ibcon#about to read 3, iclass 35, count 2 2006.201.15:50:20.36#ibcon#read 3, iclass 35, count 2 2006.201.15:50:20.36#ibcon#about to read 4, iclass 35, count 2 2006.201.15:50:20.36#ibcon#read 4, iclass 35, count 2 2006.201.15:50:20.36#ibcon#about to read 5, iclass 35, count 2 2006.201.15:50:20.36#ibcon#read 5, iclass 35, count 2 2006.201.15:50:20.36#ibcon#about to read 6, iclass 35, count 2 2006.201.15:50:20.36#ibcon#read 6, iclass 35, count 2 2006.201.15:50:20.36#ibcon#end of sib2, iclass 35, count 2 2006.201.15:50:20.36#ibcon#*mode == 0, iclass 35, count 2 2006.201.15:50:20.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.15:50:20.36#ibcon#[27=AT06-04\r\n] 2006.201.15:50:20.36#ibcon#*before write, iclass 35, count 2 2006.201.15:50:20.36#ibcon#enter sib2, iclass 35, count 2 2006.201.15:50:20.36#ibcon#flushed, iclass 35, count 2 2006.201.15:50:20.36#ibcon#about to write, iclass 35, count 2 2006.201.15:50:20.36#ibcon#wrote, iclass 35, count 2 2006.201.15:50:20.36#ibcon#about to read 3, iclass 35, count 2 2006.201.15:50:20.39#ibcon#read 3, iclass 35, count 2 2006.201.15:50:20.39#ibcon#about to read 4, iclass 35, count 2 2006.201.15:50:20.39#ibcon#read 4, iclass 35, count 2 2006.201.15:50:20.39#ibcon#about to read 5, iclass 35, count 2 2006.201.15:50:20.39#ibcon#read 5, iclass 35, count 2 2006.201.15:50:20.39#ibcon#about to read 6, iclass 35, count 2 2006.201.15:50:20.39#ibcon#read 6, iclass 35, count 2 2006.201.15:50:20.39#ibcon#end of sib2, iclass 35, count 2 2006.201.15:50:20.39#ibcon#*after write, iclass 35, count 2 2006.201.15:50:20.39#ibcon#*before return 0, iclass 35, count 2 2006.201.15:50:20.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:20.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.15:50:20.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.15:50:20.39#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:20.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:20.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:20.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:20.51#ibcon#enter wrdev, iclass 35, count 0 2006.201.15:50:20.51#ibcon#first serial, iclass 35, count 0 2006.201.15:50:20.51#ibcon#enter sib2, iclass 35, count 0 2006.201.15:50:20.51#ibcon#flushed, iclass 35, count 0 2006.201.15:50:20.51#ibcon#about to write, iclass 35, count 0 2006.201.15:50:20.51#ibcon#wrote, iclass 35, count 0 2006.201.15:50:20.51#ibcon#about to read 3, iclass 35, count 0 2006.201.15:50:20.53#ibcon#read 3, iclass 35, count 0 2006.201.15:50:20.53#ibcon#about to read 4, iclass 35, count 0 2006.201.15:50:20.53#ibcon#read 4, iclass 35, count 0 2006.201.15:50:20.53#ibcon#about to read 5, iclass 35, count 0 2006.201.15:50:20.53#ibcon#read 5, iclass 35, count 0 2006.201.15:50:20.53#ibcon#about to read 6, iclass 35, count 0 2006.201.15:50:20.53#ibcon#read 6, iclass 35, count 0 2006.201.15:50:20.53#ibcon#end of sib2, iclass 35, count 0 2006.201.15:50:20.53#ibcon#*mode == 0, iclass 35, count 0 2006.201.15:50:20.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.15:50:20.53#ibcon#[27=USB\r\n] 2006.201.15:50:20.53#ibcon#*before write, iclass 35, count 0 2006.201.15:50:20.53#ibcon#enter sib2, iclass 35, count 0 2006.201.15:50:20.53#ibcon#flushed, iclass 35, count 0 2006.201.15:50:20.53#ibcon#about to write, iclass 35, count 0 2006.201.15:50:20.53#ibcon#wrote, iclass 35, count 0 2006.201.15:50:20.53#ibcon#about to read 3, iclass 35, count 0 2006.201.15:50:20.56#ibcon#read 3, iclass 35, count 0 2006.201.15:50:20.56#ibcon#about to read 4, iclass 35, count 0 2006.201.15:50:20.56#ibcon#read 4, iclass 35, count 0 2006.201.15:50:20.56#ibcon#about to read 5, iclass 35, count 0 2006.201.15:50:20.56#ibcon#read 5, iclass 35, count 0 2006.201.15:50:20.56#ibcon#about to read 6, iclass 35, count 0 2006.201.15:50:20.56#ibcon#read 6, iclass 35, count 0 2006.201.15:50:20.56#ibcon#end of sib2, iclass 35, count 0 2006.201.15:50:20.56#ibcon#*after write, iclass 35, count 0 2006.201.15:50:20.56#ibcon#*before return 0, iclass 35, count 0 2006.201.15:50:20.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:20.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.15:50:20.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.15:50:20.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.15:50:20.56$vck44/vblo=7,734.99 2006.201.15:50:20.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.15:50:20.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.15:50:20.56#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:20.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:20.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:20.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:20.56#ibcon#enter wrdev, iclass 37, count 0 2006.201.15:50:20.56#ibcon#first serial, iclass 37, count 0 2006.201.15:50:20.56#ibcon#enter sib2, iclass 37, count 0 2006.201.15:50:20.56#ibcon#flushed, iclass 37, count 0 2006.201.15:50:20.56#ibcon#about to write, iclass 37, count 0 2006.201.15:50:20.56#ibcon#wrote, iclass 37, count 0 2006.201.15:50:20.56#ibcon#about to read 3, iclass 37, count 0 2006.201.15:50:20.58#ibcon#read 3, iclass 37, count 0 2006.201.15:50:20.58#ibcon#about to read 4, iclass 37, count 0 2006.201.15:50:20.58#ibcon#read 4, iclass 37, count 0 2006.201.15:50:20.58#ibcon#about to read 5, iclass 37, count 0 2006.201.15:50:20.58#ibcon#read 5, iclass 37, count 0 2006.201.15:50:20.58#ibcon#about to read 6, iclass 37, count 0 2006.201.15:50:20.58#ibcon#read 6, iclass 37, count 0 2006.201.15:50:20.58#ibcon#end of sib2, iclass 37, count 0 2006.201.15:50:20.58#ibcon#*mode == 0, iclass 37, count 0 2006.201.15:50:20.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.15:50:20.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:50:20.58#ibcon#*before write, iclass 37, count 0 2006.201.15:50:20.58#ibcon#enter sib2, iclass 37, count 0 2006.201.15:50:20.58#ibcon#flushed, iclass 37, count 0 2006.201.15:50:20.58#ibcon#about to write, iclass 37, count 0 2006.201.15:50:20.58#ibcon#wrote, iclass 37, count 0 2006.201.15:50:20.58#ibcon#about to read 3, iclass 37, count 0 2006.201.15:50:20.62#ibcon#read 3, iclass 37, count 0 2006.201.15:50:20.62#ibcon#about to read 4, iclass 37, count 0 2006.201.15:50:20.62#ibcon#read 4, iclass 37, count 0 2006.201.15:50:20.62#ibcon#about to read 5, iclass 37, count 0 2006.201.15:50:20.62#ibcon#read 5, iclass 37, count 0 2006.201.15:50:20.62#ibcon#about to read 6, iclass 37, count 0 2006.201.15:50:20.62#ibcon#read 6, iclass 37, count 0 2006.201.15:50:20.62#ibcon#end of sib2, iclass 37, count 0 2006.201.15:50:20.62#ibcon#*after write, iclass 37, count 0 2006.201.15:50:20.62#ibcon#*before return 0, iclass 37, count 0 2006.201.15:50:20.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:20.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.15:50:20.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.15:50:20.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.15:50:20.62$vck44/vb=7,4 2006.201.15:50:20.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.15:50:20.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.15:50:20.62#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:20.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:20.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:20.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:20.68#ibcon#enter wrdev, iclass 39, count 2 2006.201.15:50:20.68#ibcon#first serial, iclass 39, count 2 2006.201.15:50:20.68#ibcon#enter sib2, iclass 39, count 2 2006.201.15:50:20.68#ibcon#flushed, iclass 39, count 2 2006.201.15:50:20.68#ibcon#about to write, iclass 39, count 2 2006.201.15:50:20.68#ibcon#wrote, iclass 39, count 2 2006.201.15:50:20.68#ibcon#about to read 3, iclass 39, count 2 2006.201.15:50:20.70#ibcon#read 3, iclass 39, count 2 2006.201.15:50:20.70#ibcon#about to read 4, iclass 39, count 2 2006.201.15:50:20.70#ibcon#read 4, iclass 39, count 2 2006.201.15:50:20.70#ibcon#about to read 5, iclass 39, count 2 2006.201.15:50:20.70#ibcon#read 5, iclass 39, count 2 2006.201.15:50:20.70#ibcon#about to read 6, iclass 39, count 2 2006.201.15:50:20.70#ibcon#read 6, iclass 39, count 2 2006.201.15:50:20.70#ibcon#end of sib2, iclass 39, count 2 2006.201.15:50:20.70#ibcon#*mode == 0, iclass 39, count 2 2006.201.15:50:20.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.15:50:20.70#ibcon#[27=AT07-04\r\n] 2006.201.15:50:20.70#ibcon#*before write, iclass 39, count 2 2006.201.15:50:20.70#ibcon#enter sib2, iclass 39, count 2 2006.201.15:50:20.70#ibcon#flushed, iclass 39, count 2 2006.201.15:50:20.70#ibcon#about to write, iclass 39, count 2 2006.201.15:50:20.70#ibcon#wrote, iclass 39, count 2 2006.201.15:50:20.70#ibcon#about to read 3, iclass 39, count 2 2006.201.15:50:20.73#ibcon#read 3, iclass 39, count 2 2006.201.15:50:20.73#ibcon#about to read 4, iclass 39, count 2 2006.201.15:50:20.73#ibcon#read 4, iclass 39, count 2 2006.201.15:50:20.73#ibcon#about to read 5, iclass 39, count 2 2006.201.15:50:20.73#ibcon#read 5, iclass 39, count 2 2006.201.15:50:20.73#ibcon#about to read 6, iclass 39, count 2 2006.201.15:50:20.73#ibcon#read 6, iclass 39, count 2 2006.201.15:50:20.73#ibcon#end of sib2, iclass 39, count 2 2006.201.15:50:20.73#ibcon#*after write, iclass 39, count 2 2006.201.15:50:20.73#ibcon#*before return 0, iclass 39, count 2 2006.201.15:50:20.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:20.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.15:50:20.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.15:50:20.73#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:20.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:20.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:20.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:20.85#ibcon#enter wrdev, iclass 39, count 0 2006.201.15:50:20.85#ibcon#first serial, iclass 39, count 0 2006.201.15:50:20.85#ibcon#enter sib2, iclass 39, count 0 2006.201.15:50:20.85#ibcon#flushed, iclass 39, count 0 2006.201.15:50:20.85#ibcon#about to write, iclass 39, count 0 2006.201.15:50:20.85#ibcon#wrote, iclass 39, count 0 2006.201.15:50:20.85#ibcon#about to read 3, iclass 39, count 0 2006.201.15:50:20.87#ibcon#read 3, iclass 39, count 0 2006.201.15:50:20.87#ibcon#about to read 4, iclass 39, count 0 2006.201.15:50:20.87#ibcon#read 4, iclass 39, count 0 2006.201.15:50:20.87#ibcon#about to read 5, iclass 39, count 0 2006.201.15:50:20.87#ibcon#read 5, iclass 39, count 0 2006.201.15:50:20.87#ibcon#about to read 6, iclass 39, count 0 2006.201.15:50:20.87#ibcon#read 6, iclass 39, count 0 2006.201.15:50:20.87#ibcon#end of sib2, iclass 39, count 0 2006.201.15:50:20.87#ibcon#*mode == 0, iclass 39, count 0 2006.201.15:50:20.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.15:50:20.87#ibcon#[27=USB\r\n] 2006.201.15:50:20.87#ibcon#*before write, iclass 39, count 0 2006.201.15:50:20.87#ibcon#enter sib2, iclass 39, count 0 2006.201.15:50:20.87#ibcon#flushed, iclass 39, count 0 2006.201.15:50:20.87#ibcon#about to write, iclass 39, count 0 2006.201.15:50:20.87#ibcon#wrote, iclass 39, count 0 2006.201.15:50:20.87#ibcon#about to read 3, iclass 39, count 0 2006.201.15:50:20.90#ibcon#read 3, iclass 39, count 0 2006.201.15:50:20.90#ibcon#about to read 4, iclass 39, count 0 2006.201.15:50:20.90#ibcon#read 4, iclass 39, count 0 2006.201.15:50:20.90#ibcon#about to read 5, iclass 39, count 0 2006.201.15:50:20.90#ibcon#read 5, iclass 39, count 0 2006.201.15:50:20.90#ibcon#about to read 6, iclass 39, count 0 2006.201.15:50:20.90#ibcon#read 6, iclass 39, count 0 2006.201.15:50:20.90#ibcon#end of sib2, iclass 39, count 0 2006.201.15:50:20.90#ibcon#*after write, iclass 39, count 0 2006.201.15:50:20.90#ibcon#*before return 0, iclass 39, count 0 2006.201.15:50:20.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:20.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.15:50:20.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.15:50:20.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.15:50:20.90$vck44/vblo=8,744.99 2006.201.15:50:20.90#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.15:50:20.90#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.15:50:20.90#ibcon#ireg 17 cls_cnt 0 2006.201.15:50:20.90#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:20.90#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:20.90#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:20.90#ibcon#enter wrdev, iclass 2, count 0 2006.201.15:50:20.90#ibcon#first serial, iclass 2, count 0 2006.201.15:50:20.90#ibcon#enter sib2, iclass 2, count 0 2006.201.15:50:20.90#ibcon#flushed, iclass 2, count 0 2006.201.15:50:20.90#ibcon#about to write, iclass 2, count 0 2006.201.15:50:20.90#ibcon#wrote, iclass 2, count 0 2006.201.15:50:20.90#ibcon#about to read 3, iclass 2, count 0 2006.201.15:50:20.92#ibcon#read 3, iclass 2, count 0 2006.201.15:50:20.92#ibcon#about to read 4, iclass 2, count 0 2006.201.15:50:20.92#ibcon#read 4, iclass 2, count 0 2006.201.15:50:20.92#ibcon#about to read 5, iclass 2, count 0 2006.201.15:50:20.92#ibcon#read 5, iclass 2, count 0 2006.201.15:50:20.92#ibcon#about to read 6, iclass 2, count 0 2006.201.15:50:20.92#ibcon#read 6, iclass 2, count 0 2006.201.15:50:20.92#ibcon#end of sib2, iclass 2, count 0 2006.201.15:50:20.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.15:50:20.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.15:50:20.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:50:20.92#ibcon#*before write, iclass 2, count 0 2006.201.15:50:20.92#ibcon#enter sib2, iclass 2, count 0 2006.201.15:50:20.92#ibcon#flushed, iclass 2, count 0 2006.201.15:50:20.92#ibcon#about to write, iclass 2, count 0 2006.201.15:50:20.92#ibcon#wrote, iclass 2, count 0 2006.201.15:50:20.92#ibcon#about to read 3, iclass 2, count 0 2006.201.15:50:20.97#ibcon#read 3, iclass 2, count 0 2006.201.15:50:20.97#ibcon#about to read 4, iclass 2, count 0 2006.201.15:50:20.97#ibcon#read 4, iclass 2, count 0 2006.201.15:50:20.97#ibcon#about to read 5, iclass 2, count 0 2006.201.15:50:20.97#ibcon#read 5, iclass 2, count 0 2006.201.15:50:20.97#ibcon#about to read 6, iclass 2, count 0 2006.201.15:50:20.97#ibcon#read 6, iclass 2, count 0 2006.201.15:50:20.97#ibcon#end of sib2, iclass 2, count 0 2006.201.15:50:20.97#ibcon#*after write, iclass 2, count 0 2006.201.15:50:20.97#ibcon#*before return 0, iclass 2, count 0 2006.201.15:50:20.97#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:20.97#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.15:50:20.97#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.15:50:20.97#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.15:50:20.97$vck44/vb=8,4 2006.201.15:50:20.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.15:50:20.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.15:50:20.97#ibcon#ireg 11 cls_cnt 2 2006.201.15:50:20.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:21.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:21.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:21.02#ibcon#enter wrdev, iclass 5, count 2 2006.201.15:50:21.02#ibcon#first serial, iclass 5, count 2 2006.201.15:50:21.02#ibcon#enter sib2, iclass 5, count 2 2006.201.15:50:21.02#ibcon#flushed, iclass 5, count 2 2006.201.15:50:21.02#ibcon#about to write, iclass 5, count 2 2006.201.15:50:21.02#ibcon#wrote, iclass 5, count 2 2006.201.15:50:21.02#ibcon#about to read 3, iclass 5, count 2 2006.201.15:50:21.04#ibcon#read 3, iclass 5, count 2 2006.201.15:50:21.04#ibcon#about to read 4, iclass 5, count 2 2006.201.15:50:21.04#ibcon#read 4, iclass 5, count 2 2006.201.15:50:21.04#ibcon#about to read 5, iclass 5, count 2 2006.201.15:50:21.04#ibcon#read 5, iclass 5, count 2 2006.201.15:50:21.04#ibcon#about to read 6, iclass 5, count 2 2006.201.15:50:21.04#ibcon#read 6, iclass 5, count 2 2006.201.15:50:21.04#ibcon#end of sib2, iclass 5, count 2 2006.201.15:50:21.04#ibcon#*mode == 0, iclass 5, count 2 2006.201.15:50:21.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.15:50:21.04#ibcon#[27=AT08-04\r\n] 2006.201.15:50:21.04#ibcon#*before write, iclass 5, count 2 2006.201.15:50:21.04#ibcon#enter sib2, iclass 5, count 2 2006.201.15:50:21.04#ibcon#flushed, iclass 5, count 2 2006.201.15:50:21.04#ibcon#about to write, iclass 5, count 2 2006.201.15:50:21.04#ibcon#wrote, iclass 5, count 2 2006.201.15:50:21.04#ibcon#about to read 3, iclass 5, count 2 2006.201.15:50:21.07#ibcon#read 3, iclass 5, count 2 2006.201.15:50:21.07#ibcon#about to read 4, iclass 5, count 2 2006.201.15:50:21.07#ibcon#read 4, iclass 5, count 2 2006.201.15:50:21.07#ibcon#about to read 5, iclass 5, count 2 2006.201.15:50:21.07#ibcon#read 5, iclass 5, count 2 2006.201.15:50:21.07#ibcon#about to read 6, iclass 5, count 2 2006.201.15:50:21.07#ibcon#read 6, iclass 5, count 2 2006.201.15:50:21.07#ibcon#end of sib2, iclass 5, count 2 2006.201.15:50:21.07#ibcon#*after write, iclass 5, count 2 2006.201.15:50:21.07#ibcon#*before return 0, iclass 5, count 2 2006.201.15:50:21.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:21.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.15:50:21.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.15:50:21.07#ibcon#ireg 7 cls_cnt 0 2006.201.15:50:21.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:21.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:21.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:21.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.15:50:21.19#ibcon#first serial, iclass 5, count 0 2006.201.15:50:21.19#ibcon#enter sib2, iclass 5, count 0 2006.201.15:50:21.19#ibcon#flushed, iclass 5, count 0 2006.201.15:50:21.19#ibcon#about to write, iclass 5, count 0 2006.201.15:50:21.19#ibcon#wrote, iclass 5, count 0 2006.201.15:50:21.19#ibcon#about to read 3, iclass 5, count 0 2006.201.15:50:21.21#ibcon#read 3, iclass 5, count 0 2006.201.15:50:21.21#ibcon#about to read 4, iclass 5, count 0 2006.201.15:50:21.21#ibcon#read 4, iclass 5, count 0 2006.201.15:50:21.21#ibcon#about to read 5, iclass 5, count 0 2006.201.15:50:21.21#ibcon#read 5, iclass 5, count 0 2006.201.15:50:21.21#ibcon#about to read 6, iclass 5, count 0 2006.201.15:50:21.21#ibcon#read 6, iclass 5, count 0 2006.201.15:50:21.21#ibcon#end of sib2, iclass 5, count 0 2006.201.15:50:21.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.15:50:21.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.15:50:21.21#ibcon#[27=USB\r\n] 2006.201.15:50:21.21#ibcon#*before write, iclass 5, count 0 2006.201.15:50:21.21#ibcon#enter sib2, iclass 5, count 0 2006.201.15:50:21.21#ibcon#flushed, iclass 5, count 0 2006.201.15:50:21.21#ibcon#about to write, iclass 5, count 0 2006.201.15:50:21.21#ibcon#wrote, iclass 5, count 0 2006.201.15:50:21.21#ibcon#about to read 3, iclass 5, count 0 2006.201.15:50:21.24#ibcon#read 3, iclass 5, count 0 2006.201.15:50:21.24#ibcon#about to read 4, iclass 5, count 0 2006.201.15:50:21.24#ibcon#read 4, iclass 5, count 0 2006.201.15:50:21.24#ibcon#about to read 5, iclass 5, count 0 2006.201.15:50:21.24#ibcon#read 5, iclass 5, count 0 2006.201.15:50:21.24#ibcon#about to read 6, iclass 5, count 0 2006.201.15:50:21.24#ibcon#read 6, iclass 5, count 0 2006.201.15:50:21.24#ibcon#end of sib2, iclass 5, count 0 2006.201.15:50:21.24#ibcon#*after write, iclass 5, count 0 2006.201.15:50:21.24#ibcon#*before return 0, iclass 5, count 0 2006.201.15:50:21.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:21.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.15:50:21.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.15:50:21.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.15:50:21.24$vck44/vabw=wide 2006.201.15:50:21.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.15:50:21.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.15:50:21.24#ibcon#ireg 8 cls_cnt 0 2006.201.15:50:21.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:21.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:21.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:21.24#ibcon#enter wrdev, iclass 7, count 0 2006.201.15:50:21.24#ibcon#first serial, iclass 7, count 0 2006.201.15:50:21.24#ibcon#enter sib2, iclass 7, count 0 2006.201.15:50:21.24#ibcon#flushed, iclass 7, count 0 2006.201.15:50:21.24#ibcon#about to write, iclass 7, count 0 2006.201.15:50:21.24#ibcon#wrote, iclass 7, count 0 2006.201.15:50:21.24#ibcon#about to read 3, iclass 7, count 0 2006.201.15:50:21.26#ibcon#read 3, iclass 7, count 0 2006.201.15:50:21.26#ibcon#about to read 4, iclass 7, count 0 2006.201.15:50:21.26#ibcon#read 4, iclass 7, count 0 2006.201.15:50:21.26#ibcon#about to read 5, iclass 7, count 0 2006.201.15:50:21.26#ibcon#read 5, iclass 7, count 0 2006.201.15:50:21.26#ibcon#about to read 6, iclass 7, count 0 2006.201.15:50:21.26#ibcon#read 6, iclass 7, count 0 2006.201.15:50:21.26#ibcon#end of sib2, iclass 7, count 0 2006.201.15:50:21.26#ibcon#*mode == 0, iclass 7, count 0 2006.201.15:50:21.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.15:50:21.26#ibcon#[25=BW32\r\n] 2006.201.15:50:21.26#ibcon#*before write, iclass 7, count 0 2006.201.15:50:21.26#ibcon#enter sib2, iclass 7, count 0 2006.201.15:50:21.26#ibcon#flushed, iclass 7, count 0 2006.201.15:50:21.26#ibcon#about to write, iclass 7, count 0 2006.201.15:50:21.26#ibcon#wrote, iclass 7, count 0 2006.201.15:50:21.26#ibcon#about to read 3, iclass 7, count 0 2006.201.15:50:21.29#ibcon#read 3, iclass 7, count 0 2006.201.15:50:21.29#ibcon#about to read 4, iclass 7, count 0 2006.201.15:50:21.29#ibcon#read 4, iclass 7, count 0 2006.201.15:50:21.29#ibcon#about to read 5, iclass 7, count 0 2006.201.15:50:21.29#ibcon#read 5, iclass 7, count 0 2006.201.15:50:21.29#ibcon#about to read 6, iclass 7, count 0 2006.201.15:50:21.29#ibcon#read 6, iclass 7, count 0 2006.201.15:50:21.29#ibcon#end of sib2, iclass 7, count 0 2006.201.15:50:21.29#ibcon#*after write, iclass 7, count 0 2006.201.15:50:21.29#ibcon#*before return 0, iclass 7, count 0 2006.201.15:50:21.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:21.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.15:50:21.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.15:50:21.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.15:50:21.29$vck44/vbbw=wide 2006.201.15:50:21.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.15:50:21.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.15:50:21.29#ibcon#ireg 8 cls_cnt 0 2006.201.15:50:21.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:50:21.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:50:21.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:50:21.36#ibcon#enter wrdev, iclass 11, count 0 2006.201.15:50:21.36#ibcon#first serial, iclass 11, count 0 2006.201.15:50:21.36#ibcon#enter sib2, iclass 11, count 0 2006.201.15:50:21.36#ibcon#flushed, iclass 11, count 0 2006.201.15:50:21.36#ibcon#about to write, iclass 11, count 0 2006.201.15:50:21.36#ibcon#wrote, iclass 11, count 0 2006.201.15:50:21.36#ibcon#about to read 3, iclass 11, count 0 2006.201.15:50:21.38#ibcon#read 3, iclass 11, count 0 2006.201.15:50:21.38#ibcon#about to read 4, iclass 11, count 0 2006.201.15:50:21.38#ibcon#read 4, iclass 11, count 0 2006.201.15:50:21.38#ibcon#about to read 5, iclass 11, count 0 2006.201.15:50:21.38#ibcon#read 5, iclass 11, count 0 2006.201.15:50:21.38#ibcon#about to read 6, iclass 11, count 0 2006.201.15:50:21.38#ibcon#read 6, iclass 11, count 0 2006.201.15:50:21.38#ibcon#end of sib2, iclass 11, count 0 2006.201.15:50:21.38#ibcon#*mode == 0, iclass 11, count 0 2006.201.15:50:21.38#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.15:50:21.38#ibcon#[27=BW32\r\n] 2006.201.15:50:21.38#ibcon#*before write, iclass 11, count 0 2006.201.15:50:21.38#ibcon#enter sib2, iclass 11, count 0 2006.201.15:50:21.38#ibcon#flushed, iclass 11, count 0 2006.201.15:50:21.38#ibcon#about to write, iclass 11, count 0 2006.201.15:50:21.38#ibcon#wrote, iclass 11, count 0 2006.201.15:50:21.38#ibcon#about to read 3, iclass 11, count 0 2006.201.15:50:21.41#ibcon#read 3, iclass 11, count 0 2006.201.15:50:21.41#ibcon#about to read 4, iclass 11, count 0 2006.201.15:50:21.41#ibcon#read 4, iclass 11, count 0 2006.201.15:50:21.41#ibcon#about to read 5, iclass 11, count 0 2006.201.15:50:21.41#ibcon#read 5, iclass 11, count 0 2006.201.15:50:21.41#ibcon#about to read 6, iclass 11, count 0 2006.201.15:50:21.41#ibcon#read 6, iclass 11, count 0 2006.201.15:50:21.41#ibcon#end of sib2, iclass 11, count 0 2006.201.15:50:21.41#ibcon#*after write, iclass 11, count 0 2006.201.15:50:21.41#ibcon#*before return 0, iclass 11, count 0 2006.201.15:50:21.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:50:21.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.15:50:21.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.15:50:21.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.15:50:21.41$setupk4/ifdk4 2006.201.15:50:21.41$ifdk4/lo= 2006.201.15:50:21.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:50:21.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:50:21.41$ifdk4/patch= 2006.201.15:50:21.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:50:21.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:50:21.41$setupk4/!*+20s 2006.201.15:50:26.70#abcon#<5=/04 1.0 1.5 20.841001002.8\r\n> 2006.201.15:50:26.72#abcon#{5=INTERFACE CLEAR} 2006.201.15:50:26.78#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:50:29.14#trakl#Source acquired 2006.201.15:50:29.14#flagr#flagr/antenna,acquired 2006.201.15:50:35.89$setupk4/"tpicd 2006.201.15:50:35.89$setupk4/echo=off 2006.201.15:50:35.89$setupk4/xlog=off 2006.201.15:50:35.89:!2006.201.15:53:13 2006.201.15:53:13.00:preob 2006.201.15:53:13.14/onsource/TRACKING 2006.201.15:53:13.14:!2006.201.15:53:23 2006.201.15:53:23.00:"tape 2006.201.15:53:23.00:"st=record 2006.201.15:53:23.00:data_valid=on 2006.201.15:53:23.00:midob 2006.201.15:53:23.14/onsource/TRACKING 2006.201.15:53:23.14/wx/20.84,1002.8,100 2006.201.15:53:23.20/cable/+6.4759E-03 2006.201.15:53:24.29/va/01,08,usb,yes,30,32 2006.201.15:53:24.29/va/02,07,usb,yes,32,33 2006.201.15:53:24.29/va/03,08,usb,yes,29,30 2006.201.15:53:24.29/va/04,07,usb,yes,33,35 2006.201.15:53:24.29/va/05,04,usb,yes,29,30 2006.201.15:53:24.29/va/06,05,usb,yes,29,29 2006.201.15:53:24.29/va/07,05,usb,yes,28,30 2006.201.15:53:24.29/va/08,04,usb,yes,28,34 2006.201.15:53:24.52/valo/01,524.99,yes,locked 2006.201.15:53:24.52/valo/02,534.99,yes,locked 2006.201.15:53:24.52/valo/03,564.99,yes,locked 2006.201.15:53:24.52/valo/04,624.99,yes,locked 2006.201.15:53:24.52/valo/05,734.99,yes,locked 2006.201.15:53:24.52/valo/06,814.99,yes,locked 2006.201.15:53:24.52/valo/07,864.99,yes,locked 2006.201.15:53:24.52/valo/08,884.99,yes,locked 2006.201.15:53:25.61/vb/01,04,usb,yes,30,27 2006.201.15:53:25.61/vb/02,05,usb,yes,28,28 2006.201.15:53:25.61/vb/03,04,usb,yes,29,32 2006.201.15:53:25.61/vb/04,05,usb,yes,29,28 2006.201.15:53:25.61/vb/05,04,usb,yes,25,28 2006.201.15:53:25.61/vb/06,04,usb,yes,30,26 2006.201.15:53:25.61/vb/07,04,usb,yes,30,29 2006.201.15:53:25.61/vb/08,04,usb,yes,27,31 2006.201.15:53:25.84/vblo/01,629.99,yes,locked 2006.201.15:53:25.84/vblo/02,634.99,yes,locked 2006.201.15:53:25.84/vblo/03,649.99,yes,locked 2006.201.15:53:25.84/vblo/04,679.99,yes,locked 2006.201.15:53:25.84/vblo/05,709.99,yes,locked 2006.201.15:53:25.84/vblo/06,719.99,yes,locked 2006.201.15:53:25.84/vblo/07,734.99,yes,locked 2006.201.15:53:25.84/vblo/08,744.99,yes,locked 2006.201.15:53:25.99/vabw/8 2006.201.15:53:26.14/vbbw/8 2006.201.15:53:26.26/xfe/off,on,15.2 2006.201.15:53:26.64/ifatt/23,28,28,28 2006.201.15:53:27.06/fmout-gps/S +4.49E-07 2006.201.15:53:27.10:!2006.201.15:54:03 2006.201.15:54:03.00:data_valid=off 2006.201.15:54:03.00:"et 2006.201.15:54:03.00:!+3s 2006.201.15:54:06.02:"tape 2006.201.15:54:06.02:postob 2006.201.15:54:06.16/cable/+6.4783E-03 2006.201.15:54:06.16/wx/20.84,1002.8,100 2006.201.15:54:06.22/fmout-gps/S +4.51E-07 2006.201.15:54:06.22:scan_name=201-1555,jd0607,750 2006.201.15:54:06.22:source=1749+096,175132.82,093900.7,2000.0,cw 2006.201.15:54:08.14#flagr#flagr/antenna,new-source 2006.201.15:54:08.14:checkk5 2006.201.15:54:08.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.15:54:08.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.15:54:09.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.15:54:09.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.15:54:09.99/chk_obsdata//k5ts1/T2011553??a.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.15:54:10.36/chk_obsdata//k5ts2/T2011553??b.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.15:54:10.73/chk_obsdata//k5ts3/T2011553??c.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.15:54:11.10/chk_obsdata//k5ts4/T2011553??d.dat file size is correct (nominal:160MB, actual:160MB). 2006.201.15:54:11.78/k5log//k5ts1_log_newline 2006.201.15:54:12.47/k5log//k5ts2_log_newline 2006.201.15:54:13.15/k5log//k5ts3_log_newline 2006.201.15:54:13.83/k5log//k5ts4_log_newline 2006.201.15:54:13.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.15:54:13.86:setupk4=1 2006.201.15:54:13.86$setupk4/echo=on 2006.201.15:54:13.86$setupk4/pcalon 2006.201.15:54:13.86$pcalon/"no phase cal control is implemented here 2006.201.15:54:13.86$setupk4/"tpicd=stop 2006.201.15:54:13.86$setupk4/"rec=synch_on 2006.201.15:54:13.86$setupk4/"rec_mode=128 2006.201.15:54:13.86$setupk4/!* 2006.201.15:54:13.86$setupk4/recpk4 2006.201.15:54:13.86$recpk4/recpatch= 2006.201.15:54:13.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.15:54:13.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.15:54:13.87$setupk4/vck44 2006.201.15:54:13.87$vck44/valo=1,524.99 2006.201.15:54:13.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.15:54:13.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.15:54:13.87#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:13.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:13.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:13.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:13.87#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:54:13.87#ibcon#first serial, iclass 36, count 0 2006.201.15:54:13.87#ibcon#enter sib2, iclass 36, count 0 2006.201.15:54:13.87#ibcon#flushed, iclass 36, count 0 2006.201.15:54:13.87#ibcon#about to write, iclass 36, count 0 2006.201.15:54:13.87#ibcon#wrote, iclass 36, count 0 2006.201.15:54:13.87#ibcon#about to read 3, iclass 36, count 0 2006.201.15:54:13.90#ibcon#read 3, iclass 36, count 0 2006.201.15:54:13.90#ibcon#about to read 4, iclass 36, count 0 2006.201.15:54:13.90#ibcon#read 4, iclass 36, count 0 2006.201.15:54:13.90#ibcon#about to read 5, iclass 36, count 0 2006.201.15:54:13.90#ibcon#read 5, iclass 36, count 0 2006.201.15:54:13.90#ibcon#about to read 6, iclass 36, count 0 2006.201.15:54:13.90#ibcon#read 6, iclass 36, count 0 2006.201.15:54:13.90#ibcon#end of sib2, iclass 36, count 0 2006.201.15:54:13.90#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:54:13.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:54:13.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.15:54:13.90#ibcon#*before write, iclass 36, count 0 2006.201.15:54:13.90#ibcon#enter sib2, iclass 36, count 0 2006.201.15:54:13.90#ibcon#flushed, iclass 36, count 0 2006.201.15:54:13.90#ibcon#about to write, iclass 36, count 0 2006.201.15:54:13.90#ibcon#wrote, iclass 36, count 0 2006.201.15:54:13.90#ibcon#about to read 3, iclass 36, count 0 2006.201.15:54:13.95#ibcon#read 3, iclass 36, count 0 2006.201.15:54:13.95#ibcon#about to read 4, iclass 36, count 0 2006.201.15:54:13.95#ibcon#read 4, iclass 36, count 0 2006.201.15:54:13.95#ibcon#about to read 5, iclass 36, count 0 2006.201.15:54:13.95#ibcon#read 5, iclass 36, count 0 2006.201.15:54:13.95#ibcon#about to read 6, iclass 36, count 0 2006.201.15:54:13.95#ibcon#read 6, iclass 36, count 0 2006.201.15:54:13.95#ibcon#end of sib2, iclass 36, count 0 2006.201.15:54:13.95#ibcon#*after write, iclass 36, count 0 2006.201.15:54:13.95#ibcon#*before return 0, iclass 36, count 0 2006.201.15:54:13.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:13.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:13.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:54:13.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:54:13.95$vck44/va=1,8 2006.201.15:54:13.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.15:54:13.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.15:54:13.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:13.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:13.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:13.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:13.95#ibcon#enter wrdev, iclass 38, count 2 2006.201.15:54:13.95#ibcon#first serial, iclass 38, count 2 2006.201.15:54:13.95#ibcon#enter sib2, iclass 38, count 2 2006.201.15:54:13.95#ibcon#flushed, iclass 38, count 2 2006.201.15:54:13.95#ibcon#about to write, iclass 38, count 2 2006.201.15:54:13.95#ibcon#wrote, iclass 38, count 2 2006.201.15:54:13.95#ibcon#about to read 3, iclass 38, count 2 2006.201.15:54:13.97#ibcon#read 3, iclass 38, count 2 2006.201.15:54:13.97#ibcon#about to read 4, iclass 38, count 2 2006.201.15:54:13.97#ibcon#read 4, iclass 38, count 2 2006.201.15:54:13.97#ibcon#about to read 5, iclass 38, count 2 2006.201.15:54:13.97#ibcon#read 5, iclass 38, count 2 2006.201.15:54:13.97#ibcon#about to read 6, iclass 38, count 2 2006.201.15:54:13.97#ibcon#read 6, iclass 38, count 2 2006.201.15:54:13.97#ibcon#end of sib2, iclass 38, count 2 2006.201.15:54:13.97#ibcon#*mode == 0, iclass 38, count 2 2006.201.15:54:13.97#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.15:54:13.97#ibcon#[25=AT01-08\r\n] 2006.201.15:54:13.97#ibcon#*before write, iclass 38, count 2 2006.201.15:54:13.97#ibcon#enter sib2, iclass 38, count 2 2006.201.15:54:13.97#ibcon#flushed, iclass 38, count 2 2006.201.15:54:13.97#ibcon#about to write, iclass 38, count 2 2006.201.15:54:13.97#ibcon#wrote, iclass 38, count 2 2006.201.15:54:13.97#ibcon#about to read 3, iclass 38, count 2 2006.201.15:54:14.00#ibcon#read 3, iclass 38, count 2 2006.201.15:54:14.00#ibcon#about to read 4, iclass 38, count 2 2006.201.15:54:14.00#ibcon#read 4, iclass 38, count 2 2006.201.15:54:14.00#ibcon#about to read 5, iclass 38, count 2 2006.201.15:54:14.00#ibcon#read 5, iclass 38, count 2 2006.201.15:54:14.00#ibcon#about to read 6, iclass 38, count 2 2006.201.15:54:14.00#ibcon#read 6, iclass 38, count 2 2006.201.15:54:14.00#ibcon#end of sib2, iclass 38, count 2 2006.201.15:54:14.00#ibcon#*after write, iclass 38, count 2 2006.201.15:54:14.00#ibcon#*before return 0, iclass 38, count 2 2006.201.15:54:14.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:14.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:14.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.15:54:14.00#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:14.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:14.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:14.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:14.12#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:54:14.12#ibcon#first serial, iclass 38, count 0 2006.201.15:54:14.12#ibcon#enter sib2, iclass 38, count 0 2006.201.15:54:14.12#ibcon#flushed, iclass 38, count 0 2006.201.15:54:14.12#ibcon#about to write, iclass 38, count 0 2006.201.15:54:14.12#ibcon#wrote, iclass 38, count 0 2006.201.15:54:14.12#ibcon#about to read 3, iclass 38, count 0 2006.201.15:54:14.14#ibcon#read 3, iclass 38, count 0 2006.201.15:54:14.14#ibcon#about to read 4, iclass 38, count 0 2006.201.15:54:14.14#ibcon#read 4, iclass 38, count 0 2006.201.15:54:14.14#ibcon#about to read 5, iclass 38, count 0 2006.201.15:54:14.14#ibcon#read 5, iclass 38, count 0 2006.201.15:54:14.14#ibcon#about to read 6, iclass 38, count 0 2006.201.15:54:14.14#ibcon#read 6, iclass 38, count 0 2006.201.15:54:14.14#ibcon#end of sib2, iclass 38, count 0 2006.201.15:54:14.14#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:54:14.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:54:14.14#ibcon#[25=USB\r\n] 2006.201.15:54:14.14#ibcon#*before write, iclass 38, count 0 2006.201.15:54:14.14#ibcon#enter sib2, iclass 38, count 0 2006.201.15:54:14.14#ibcon#flushed, iclass 38, count 0 2006.201.15:54:14.14#ibcon#about to write, iclass 38, count 0 2006.201.15:54:14.14#ibcon#wrote, iclass 38, count 0 2006.201.15:54:14.14#ibcon#about to read 3, iclass 38, count 0 2006.201.15:54:14.17#ibcon#read 3, iclass 38, count 0 2006.201.15:54:14.17#ibcon#about to read 4, iclass 38, count 0 2006.201.15:54:14.17#ibcon#read 4, iclass 38, count 0 2006.201.15:54:14.17#ibcon#about to read 5, iclass 38, count 0 2006.201.15:54:14.17#ibcon#read 5, iclass 38, count 0 2006.201.15:54:14.17#ibcon#about to read 6, iclass 38, count 0 2006.201.15:54:14.17#ibcon#read 6, iclass 38, count 0 2006.201.15:54:14.17#ibcon#end of sib2, iclass 38, count 0 2006.201.15:54:14.17#ibcon#*after write, iclass 38, count 0 2006.201.15:54:14.17#ibcon#*before return 0, iclass 38, count 0 2006.201.15:54:14.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:14.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:14.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:54:14.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:54:14.17$vck44/valo=2,534.99 2006.201.15:54:14.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.15:54:14.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.15:54:14.17#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:14.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:14.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:14.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:14.17#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:54:14.17#ibcon#first serial, iclass 40, count 0 2006.201.15:54:14.17#ibcon#enter sib2, iclass 40, count 0 2006.201.15:54:14.17#ibcon#flushed, iclass 40, count 0 2006.201.15:54:14.17#ibcon#about to write, iclass 40, count 0 2006.201.15:54:14.17#ibcon#wrote, iclass 40, count 0 2006.201.15:54:14.17#ibcon#about to read 3, iclass 40, count 0 2006.201.15:54:14.19#ibcon#read 3, iclass 40, count 0 2006.201.15:54:14.19#ibcon#about to read 4, iclass 40, count 0 2006.201.15:54:14.19#ibcon#read 4, iclass 40, count 0 2006.201.15:54:14.19#ibcon#about to read 5, iclass 40, count 0 2006.201.15:54:14.19#ibcon#read 5, iclass 40, count 0 2006.201.15:54:14.19#ibcon#about to read 6, iclass 40, count 0 2006.201.15:54:14.19#ibcon#read 6, iclass 40, count 0 2006.201.15:54:14.19#ibcon#end of sib2, iclass 40, count 0 2006.201.15:54:14.19#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:54:14.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:54:14.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.15:54:14.19#ibcon#*before write, iclass 40, count 0 2006.201.15:54:14.19#ibcon#enter sib2, iclass 40, count 0 2006.201.15:54:14.19#ibcon#flushed, iclass 40, count 0 2006.201.15:54:14.19#ibcon#about to write, iclass 40, count 0 2006.201.15:54:14.19#ibcon#wrote, iclass 40, count 0 2006.201.15:54:14.19#ibcon#about to read 3, iclass 40, count 0 2006.201.15:54:14.23#ibcon#read 3, iclass 40, count 0 2006.201.15:54:14.23#ibcon#about to read 4, iclass 40, count 0 2006.201.15:54:14.23#ibcon#read 4, iclass 40, count 0 2006.201.15:54:14.23#ibcon#about to read 5, iclass 40, count 0 2006.201.15:54:14.23#ibcon#read 5, iclass 40, count 0 2006.201.15:54:14.23#ibcon#about to read 6, iclass 40, count 0 2006.201.15:54:14.23#ibcon#read 6, iclass 40, count 0 2006.201.15:54:14.23#ibcon#end of sib2, iclass 40, count 0 2006.201.15:54:14.23#ibcon#*after write, iclass 40, count 0 2006.201.15:54:14.23#ibcon#*before return 0, iclass 40, count 0 2006.201.15:54:14.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:14.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:14.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:54:14.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:54:14.23$vck44/va=2,7 2006.201.15:54:14.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.15:54:14.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.15:54:14.23#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:14.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:14.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:14.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:14.29#ibcon#enter wrdev, iclass 4, count 2 2006.201.15:54:14.29#ibcon#first serial, iclass 4, count 2 2006.201.15:54:14.29#ibcon#enter sib2, iclass 4, count 2 2006.201.15:54:14.29#ibcon#flushed, iclass 4, count 2 2006.201.15:54:14.29#ibcon#about to write, iclass 4, count 2 2006.201.15:54:14.29#ibcon#wrote, iclass 4, count 2 2006.201.15:54:14.29#ibcon#about to read 3, iclass 4, count 2 2006.201.15:54:14.31#ibcon#read 3, iclass 4, count 2 2006.201.15:54:14.31#ibcon#about to read 4, iclass 4, count 2 2006.201.15:54:14.31#ibcon#read 4, iclass 4, count 2 2006.201.15:54:14.31#ibcon#about to read 5, iclass 4, count 2 2006.201.15:54:14.31#ibcon#read 5, iclass 4, count 2 2006.201.15:54:14.31#ibcon#about to read 6, iclass 4, count 2 2006.201.15:54:14.31#ibcon#read 6, iclass 4, count 2 2006.201.15:54:14.31#ibcon#end of sib2, iclass 4, count 2 2006.201.15:54:14.31#ibcon#*mode == 0, iclass 4, count 2 2006.201.15:54:14.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.15:54:14.31#ibcon#[25=AT02-07\r\n] 2006.201.15:54:14.31#ibcon#*before write, iclass 4, count 2 2006.201.15:54:14.31#ibcon#enter sib2, iclass 4, count 2 2006.201.15:54:14.31#ibcon#flushed, iclass 4, count 2 2006.201.15:54:14.31#ibcon#about to write, iclass 4, count 2 2006.201.15:54:14.31#ibcon#wrote, iclass 4, count 2 2006.201.15:54:14.31#ibcon#about to read 3, iclass 4, count 2 2006.201.15:54:14.34#ibcon#read 3, iclass 4, count 2 2006.201.15:54:14.34#ibcon#about to read 4, iclass 4, count 2 2006.201.15:54:14.34#ibcon#read 4, iclass 4, count 2 2006.201.15:54:14.34#ibcon#about to read 5, iclass 4, count 2 2006.201.15:54:14.34#ibcon#read 5, iclass 4, count 2 2006.201.15:54:14.34#ibcon#about to read 6, iclass 4, count 2 2006.201.15:54:14.34#ibcon#read 6, iclass 4, count 2 2006.201.15:54:14.34#ibcon#end of sib2, iclass 4, count 2 2006.201.15:54:14.34#ibcon#*after write, iclass 4, count 2 2006.201.15:54:14.34#ibcon#*before return 0, iclass 4, count 2 2006.201.15:54:14.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:14.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:14.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.15:54:14.34#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:14.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:14.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:14.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:14.46#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:54:14.46#ibcon#first serial, iclass 4, count 0 2006.201.15:54:14.46#ibcon#enter sib2, iclass 4, count 0 2006.201.15:54:14.46#ibcon#flushed, iclass 4, count 0 2006.201.15:54:14.46#ibcon#about to write, iclass 4, count 0 2006.201.15:54:14.46#ibcon#wrote, iclass 4, count 0 2006.201.15:54:14.46#ibcon#about to read 3, iclass 4, count 0 2006.201.15:54:14.48#ibcon#read 3, iclass 4, count 0 2006.201.15:54:14.48#ibcon#about to read 4, iclass 4, count 0 2006.201.15:54:14.48#ibcon#read 4, iclass 4, count 0 2006.201.15:54:14.48#ibcon#about to read 5, iclass 4, count 0 2006.201.15:54:14.48#ibcon#read 5, iclass 4, count 0 2006.201.15:54:14.48#ibcon#about to read 6, iclass 4, count 0 2006.201.15:54:14.48#ibcon#read 6, iclass 4, count 0 2006.201.15:54:14.48#ibcon#end of sib2, iclass 4, count 0 2006.201.15:54:14.48#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:54:14.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:54:14.48#ibcon#[25=USB\r\n] 2006.201.15:54:14.48#ibcon#*before write, iclass 4, count 0 2006.201.15:54:14.48#ibcon#enter sib2, iclass 4, count 0 2006.201.15:54:14.48#ibcon#flushed, iclass 4, count 0 2006.201.15:54:14.48#ibcon#about to write, iclass 4, count 0 2006.201.15:54:14.48#ibcon#wrote, iclass 4, count 0 2006.201.15:54:14.48#ibcon#about to read 3, iclass 4, count 0 2006.201.15:54:14.51#ibcon#read 3, iclass 4, count 0 2006.201.15:54:14.51#ibcon#about to read 4, iclass 4, count 0 2006.201.15:54:14.51#ibcon#read 4, iclass 4, count 0 2006.201.15:54:14.51#ibcon#about to read 5, iclass 4, count 0 2006.201.15:54:14.51#ibcon#read 5, iclass 4, count 0 2006.201.15:54:14.51#ibcon#about to read 6, iclass 4, count 0 2006.201.15:54:14.51#ibcon#read 6, iclass 4, count 0 2006.201.15:54:14.51#ibcon#end of sib2, iclass 4, count 0 2006.201.15:54:14.51#ibcon#*after write, iclass 4, count 0 2006.201.15:54:14.51#ibcon#*before return 0, iclass 4, count 0 2006.201.15:54:14.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:14.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:14.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:54:14.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:54:14.51$vck44/valo=3,564.99 2006.201.15:54:14.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.15:54:14.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.15:54:14.51#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:14.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:14.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:14.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:14.51#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:54:14.51#ibcon#first serial, iclass 6, count 0 2006.201.15:54:14.51#ibcon#enter sib2, iclass 6, count 0 2006.201.15:54:14.51#ibcon#flushed, iclass 6, count 0 2006.201.15:54:14.51#ibcon#about to write, iclass 6, count 0 2006.201.15:54:14.51#ibcon#wrote, iclass 6, count 0 2006.201.15:54:14.51#ibcon#about to read 3, iclass 6, count 0 2006.201.15:54:14.53#ibcon#read 3, iclass 6, count 0 2006.201.15:54:14.53#ibcon#about to read 4, iclass 6, count 0 2006.201.15:54:14.53#ibcon#read 4, iclass 6, count 0 2006.201.15:54:14.53#ibcon#about to read 5, iclass 6, count 0 2006.201.15:54:14.53#ibcon#read 5, iclass 6, count 0 2006.201.15:54:14.53#ibcon#about to read 6, iclass 6, count 0 2006.201.15:54:14.53#ibcon#read 6, iclass 6, count 0 2006.201.15:54:14.53#ibcon#end of sib2, iclass 6, count 0 2006.201.15:54:14.53#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:54:14.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:54:14.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.15:54:14.53#ibcon#*before write, iclass 6, count 0 2006.201.15:54:14.53#ibcon#enter sib2, iclass 6, count 0 2006.201.15:54:14.53#ibcon#flushed, iclass 6, count 0 2006.201.15:54:14.53#ibcon#about to write, iclass 6, count 0 2006.201.15:54:14.53#ibcon#wrote, iclass 6, count 0 2006.201.15:54:14.53#ibcon#about to read 3, iclass 6, count 0 2006.201.15:54:14.58#ibcon#read 3, iclass 6, count 0 2006.201.15:54:14.58#ibcon#about to read 4, iclass 6, count 0 2006.201.15:54:14.58#ibcon#read 4, iclass 6, count 0 2006.201.15:54:14.58#ibcon#about to read 5, iclass 6, count 0 2006.201.15:54:14.58#ibcon#read 5, iclass 6, count 0 2006.201.15:54:14.58#ibcon#about to read 6, iclass 6, count 0 2006.201.15:54:14.58#ibcon#read 6, iclass 6, count 0 2006.201.15:54:14.58#ibcon#end of sib2, iclass 6, count 0 2006.201.15:54:14.58#ibcon#*after write, iclass 6, count 0 2006.201.15:54:14.58#ibcon#*before return 0, iclass 6, count 0 2006.201.15:54:14.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:14.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:14.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:54:14.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:54:14.58$vck44/va=3,8 2006.201.15:54:14.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.15:54:14.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.15:54:14.58#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:14.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:14.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:14.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:14.63#ibcon#enter wrdev, iclass 10, count 2 2006.201.15:54:14.63#ibcon#first serial, iclass 10, count 2 2006.201.15:54:14.63#ibcon#enter sib2, iclass 10, count 2 2006.201.15:54:14.63#ibcon#flushed, iclass 10, count 2 2006.201.15:54:14.63#ibcon#about to write, iclass 10, count 2 2006.201.15:54:14.63#ibcon#wrote, iclass 10, count 2 2006.201.15:54:14.63#ibcon#about to read 3, iclass 10, count 2 2006.201.15:54:14.65#ibcon#read 3, iclass 10, count 2 2006.201.15:54:14.65#ibcon#about to read 4, iclass 10, count 2 2006.201.15:54:14.65#ibcon#read 4, iclass 10, count 2 2006.201.15:54:14.65#ibcon#about to read 5, iclass 10, count 2 2006.201.15:54:14.65#ibcon#read 5, iclass 10, count 2 2006.201.15:54:14.65#ibcon#about to read 6, iclass 10, count 2 2006.201.15:54:14.65#ibcon#read 6, iclass 10, count 2 2006.201.15:54:14.65#ibcon#end of sib2, iclass 10, count 2 2006.201.15:54:14.65#ibcon#*mode == 0, iclass 10, count 2 2006.201.15:54:14.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.15:54:14.65#ibcon#[25=AT03-08\r\n] 2006.201.15:54:14.65#ibcon#*before write, iclass 10, count 2 2006.201.15:54:14.65#ibcon#enter sib2, iclass 10, count 2 2006.201.15:54:14.65#ibcon#flushed, iclass 10, count 2 2006.201.15:54:14.65#ibcon#about to write, iclass 10, count 2 2006.201.15:54:14.65#ibcon#wrote, iclass 10, count 2 2006.201.15:54:14.65#ibcon#about to read 3, iclass 10, count 2 2006.201.15:54:14.68#ibcon#read 3, iclass 10, count 2 2006.201.15:54:14.68#ibcon#about to read 4, iclass 10, count 2 2006.201.15:54:14.68#ibcon#read 4, iclass 10, count 2 2006.201.15:54:14.68#ibcon#about to read 5, iclass 10, count 2 2006.201.15:54:14.68#ibcon#read 5, iclass 10, count 2 2006.201.15:54:14.68#ibcon#about to read 6, iclass 10, count 2 2006.201.15:54:14.68#ibcon#read 6, iclass 10, count 2 2006.201.15:54:14.68#ibcon#end of sib2, iclass 10, count 2 2006.201.15:54:14.68#ibcon#*after write, iclass 10, count 2 2006.201.15:54:14.68#ibcon#*before return 0, iclass 10, count 2 2006.201.15:54:14.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:14.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:14.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.15:54:14.68#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:14.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:14.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:14.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:14.80#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:54:14.80#ibcon#first serial, iclass 10, count 0 2006.201.15:54:14.80#ibcon#enter sib2, iclass 10, count 0 2006.201.15:54:14.80#ibcon#flushed, iclass 10, count 0 2006.201.15:54:14.80#ibcon#about to write, iclass 10, count 0 2006.201.15:54:14.80#ibcon#wrote, iclass 10, count 0 2006.201.15:54:14.80#ibcon#about to read 3, iclass 10, count 0 2006.201.15:54:14.82#ibcon#read 3, iclass 10, count 0 2006.201.15:54:14.82#ibcon#about to read 4, iclass 10, count 0 2006.201.15:54:14.82#ibcon#read 4, iclass 10, count 0 2006.201.15:54:14.82#ibcon#about to read 5, iclass 10, count 0 2006.201.15:54:14.82#ibcon#read 5, iclass 10, count 0 2006.201.15:54:14.82#ibcon#about to read 6, iclass 10, count 0 2006.201.15:54:14.82#ibcon#read 6, iclass 10, count 0 2006.201.15:54:14.82#ibcon#end of sib2, iclass 10, count 0 2006.201.15:54:14.82#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:54:14.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:54:14.82#ibcon#[25=USB\r\n] 2006.201.15:54:14.82#ibcon#*before write, iclass 10, count 0 2006.201.15:54:14.82#ibcon#enter sib2, iclass 10, count 0 2006.201.15:54:14.82#ibcon#flushed, iclass 10, count 0 2006.201.15:54:14.82#ibcon#about to write, iclass 10, count 0 2006.201.15:54:14.82#ibcon#wrote, iclass 10, count 0 2006.201.15:54:14.82#ibcon#about to read 3, iclass 10, count 0 2006.201.15:54:14.85#ibcon#read 3, iclass 10, count 0 2006.201.15:54:14.85#ibcon#about to read 4, iclass 10, count 0 2006.201.15:54:14.85#ibcon#read 4, iclass 10, count 0 2006.201.15:54:14.85#ibcon#about to read 5, iclass 10, count 0 2006.201.15:54:14.85#ibcon#read 5, iclass 10, count 0 2006.201.15:54:14.85#ibcon#about to read 6, iclass 10, count 0 2006.201.15:54:14.85#ibcon#read 6, iclass 10, count 0 2006.201.15:54:14.85#ibcon#end of sib2, iclass 10, count 0 2006.201.15:54:14.85#ibcon#*after write, iclass 10, count 0 2006.201.15:54:14.85#ibcon#*before return 0, iclass 10, count 0 2006.201.15:54:14.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:14.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:14.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:54:14.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:54:14.85$vck44/valo=4,624.99 2006.201.15:54:14.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.15:54:14.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.15:54:14.85#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:14.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:14.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:14.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:14.85#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:54:14.85#ibcon#first serial, iclass 12, count 0 2006.201.15:54:14.85#ibcon#enter sib2, iclass 12, count 0 2006.201.15:54:14.85#ibcon#flushed, iclass 12, count 0 2006.201.15:54:14.85#ibcon#about to write, iclass 12, count 0 2006.201.15:54:14.85#ibcon#wrote, iclass 12, count 0 2006.201.15:54:14.85#ibcon#about to read 3, iclass 12, count 0 2006.201.15:54:14.87#ibcon#read 3, iclass 12, count 0 2006.201.15:54:14.87#ibcon#about to read 4, iclass 12, count 0 2006.201.15:54:14.87#ibcon#read 4, iclass 12, count 0 2006.201.15:54:14.87#ibcon#about to read 5, iclass 12, count 0 2006.201.15:54:14.87#ibcon#read 5, iclass 12, count 0 2006.201.15:54:14.87#ibcon#about to read 6, iclass 12, count 0 2006.201.15:54:14.87#ibcon#read 6, iclass 12, count 0 2006.201.15:54:14.87#ibcon#end of sib2, iclass 12, count 0 2006.201.15:54:14.87#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:54:14.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:54:14.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.15:54:14.87#ibcon#*before write, iclass 12, count 0 2006.201.15:54:14.87#ibcon#enter sib2, iclass 12, count 0 2006.201.15:54:14.87#ibcon#flushed, iclass 12, count 0 2006.201.15:54:14.87#ibcon#about to write, iclass 12, count 0 2006.201.15:54:14.87#ibcon#wrote, iclass 12, count 0 2006.201.15:54:14.87#ibcon#about to read 3, iclass 12, count 0 2006.201.15:54:14.91#ibcon#read 3, iclass 12, count 0 2006.201.15:54:14.91#ibcon#about to read 4, iclass 12, count 0 2006.201.15:54:14.91#ibcon#read 4, iclass 12, count 0 2006.201.15:54:14.91#ibcon#about to read 5, iclass 12, count 0 2006.201.15:54:14.91#ibcon#read 5, iclass 12, count 0 2006.201.15:54:14.91#ibcon#about to read 6, iclass 12, count 0 2006.201.15:54:14.91#ibcon#read 6, iclass 12, count 0 2006.201.15:54:14.91#ibcon#end of sib2, iclass 12, count 0 2006.201.15:54:14.91#ibcon#*after write, iclass 12, count 0 2006.201.15:54:14.91#ibcon#*before return 0, iclass 12, count 0 2006.201.15:54:14.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:14.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:14.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:54:14.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:54:14.91$vck44/va=4,7 2006.201.15:54:14.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.15:54:14.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.15:54:14.91#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:14.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:14.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:14.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:14.97#ibcon#enter wrdev, iclass 14, count 2 2006.201.15:54:14.97#ibcon#first serial, iclass 14, count 2 2006.201.15:54:14.97#ibcon#enter sib2, iclass 14, count 2 2006.201.15:54:14.97#ibcon#flushed, iclass 14, count 2 2006.201.15:54:14.97#ibcon#about to write, iclass 14, count 2 2006.201.15:54:14.97#ibcon#wrote, iclass 14, count 2 2006.201.15:54:14.97#ibcon#about to read 3, iclass 14, count 2 2006.201.15:54:14.99#ibcon#read 3, iclass 14, count 2 2006.201.15:54:14.99#ibcon#about to read 4, iclass 14, count 2 2006.201.15:54:14.99#ibcon#read 4, iclass 14, count 2 2006.201.15:54:14.99#ibcon#about to read 5, iclass 14, count 2 2006.201.15:54:14.99#ibcon#read 5, iclass 14, count 2 2006.201.15:54:14.99#ibcon#about to read 6, iclass 14, count 2 2006.201.15:54:14.99#ibcon#read 6, iclass 14, count 2 2006.201.15:54:14.99#ibcon#end of sib2, iclass 14, count 2 2006.201.15:54:14.99#ibcon#*mode == 0, iclass 14, count 2 2006.201.15:54:14.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.15:54:14.99#ibcon#[25=AT04-07\r\n] 2006.201.15:54:14.99#ibcon#*before write, iclass 14, count 2 2006.201.15:54:14.99#ibcon#enter sib2, iclass 14, count 2 2006.201.15:54:14.99#ibcon#flushed, iclass 14, count 2 2006.201.15:54:14.99#ibcon#about to write, iclass 14, count 2 2006.201.15:54:14.99#ibcon#wrote, iclass 14, count 2 2006.201.15:54:14.99#ibcon#about to read 3, iclass 14, count 2 2006.201.15:54:15.02#ibcon#read 3, iclass 14, count 2 2006.201.15:54:15.02#ibcon#about to read 4, iclass 14, count 2 2006.201.15:54:15.02#ibcon#read 4, iclass 14, count 2 2006.201.15:54:15.02#ibcon#about to read 5, iclass 14, count 2 2006.201.15:54:15.02#ibcon#read 5, iclass 14, count 2 2006.201.15:54:15.02#ibcon#about to read 6, iclass 14, count 2 2006.201.15:54:15.02#ibcon#read 6, iclass 14, count 2 2006.201.15:54:15.02#ibcon#end of sib2, iclass 14, count 2 2006.201.15:54:15.02#ibcon#*after write, iclass 14, count 2 2006.201.15:54:15.02#ibcon#*before return 0, iclass 14, count 2 2006.201.15:54:15.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:15.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:15.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.15:54:15.02#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:15.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:15.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:15.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:15.14#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:54:15.14#ibcon#first serial, iclass 14, count 0 2006.201.15:54:15.14#ibcon#enter sib2, iclass 14, count 0 2006.201.15:54:15.14#ibcon#flushed, iclass 14, count 0 2006.201.15:54:15.14#ibcon#about to write, iclass 14, count 0 2006.201.15:54:15.14#ibcon#wrote, iclass 14, count 0 2006.201.15:54:15.14#ibcon#about to read 3, iclass 14, count 0 2006.201.15:54:15.16#ibcon#read 3, iclass 14, count 0 2006.201.15:54:15.16#ibcon#about to read 4, iclass 14, count 0 2006.201.15:54:15.16#ibcon#read 4, iclass 14, count 0 2006.201.15:54:15.16#ibcon#about to read 5, iclass 14, count 0 2006.201.15:54:15.16#ibcon#read 5, iclass 14, count 0 2006.201.15:54:15.16#ibcon#about to read 6, iclass 14, count 0 2006.201.15:54:15.16#ibcon#read 6, iclass 14, count 0 2006.201.15:54:15.16#ibcon#end of sib2, iclass 14, count 0 2006.201.15:54:15.16#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:54:15.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:54:15.16#ibcon#[25=USB\r\n] 2006.201.15:54:15.16#ibcon#*before write, iclass 14, count 0 2006.201.15:54:15.16#ibcon#enter sib2, iclass 14, count 0 2006.201.15:54:15.16#ibcon#flushed, iclass 14, count 0 2006.201.15:54:15.16#ibcon#about to write, iclass 14, count 0 2006.201.15:54:15.16#ibcon#wrote, iclass 14, count 0 2006.201.15:54:15.16#ibcon#about to read 3, iclass 14, count 0 2006.201.15:54:15.19#ibcon#read 3, iclass 14, count 0 2006.201.15:54:15.19#ibcon#about to read 4, iclass 14, count 0 2006.201.15:54:15.19#ibcon#read 4, iclass 14, count 0 2006.201.15:54:15.19#ibcon#about to read 5, iclass 14, count 0 2006.201.15:54:15.19#ibcon#read 5, iclass 14, count 0 2006.201.15:54:15.19#ibcon#about to read 6, iclass 14, count 0 2006.201.15:54:15.19#ibcon#read 6, iclass 14, count 0 2006.201.15:54:15.19#ibcon#end of sib2, iclass 14, count 0 2006.201.15:54:15.19#ibcon#*after write, iclass 14, count 0 2006.201.15:54:15.19#ibcon#*before return 0, iclass 14, count 0 2006.201.15:54:15.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:15.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:15.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:54:15.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:54:15.19$vck44/valo=5,734.99 2006.201.15:54:15.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.15:54:15.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.15:54:15.19#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:15.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:15.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:15.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:15.19#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:54:15.19#ibcon#first serial, iclass 16, count 0 2006.201.15:54:15.19#ibcon#enter sib2, iclass 16, count 0 2006.201.15:54:15.19#ibcon#flushed, iclass 16, count 0 2006.201.15:54:15.19#ibcon#about to write, iclass 16, count 0 2006.201.15:54:15.19#ibcon#wrote, iclass 16, count 0 2006.201.15:54:15.19#ibcon#about to read 3, iclass 16, count 0 2006.201.15:54:15.21#ibcon#read 3, iclass 16, count 0 2006.201.15:54:15.21#ibcon#about to read 4, iclass 16, count 0 2006.201.15:54:15.21#ibcon#read 4, iclass 16, count 0 2006.201.15:54:15.21#ibcon#about to read 5, iclass 16, count 0 2006.201.15:54:15.21#ibcon#read 5, iclass 16, count 0 2006.201.15:54:15.21#ibcon#about to read 6, iclass 16, count 0 2006.201.15:54:15.21#ibcon#read 6, iclass 16, count 0 2006.201.15:54:15.21#ibcon#end of sib2, iclass 16, count 0 2006.201.15:54:15.21#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:54:15.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:54:15.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.15:54:15.21#ibcon#*before write, iclass 16, count 0 2006.201.15:54:15.21#ibcon#enter sib2, iclass 16, count 0 2006.201.15:54:15.21#ibcon#flushed, iclass 16, count 0 2006.201.15:54:15.21#ibcon#about to write, iclass 16, count 0 2006.201.15:54:15.21#ibcon#wrote, iclass 16, count 0 2006.201.15:54:15.21#ibcon#about to read 3, iclass 16, count 0 2006.201.15:54:15.25#ibcon#read 3, iclass 16, count 0 2006.201.15:54:15.25#ibcon#about to read 4, iclass 16, count 0 2006.201.15:54:15.25#ibcon#read 4, iclass 16, count 0 2006.201.15:54:15.25#ibcon#about to read 5, iclass 16, count 0 2006.201.15:54:15.25#ibcon#read 5, iclass 16, count 0 2006.201.15:54:15.25#ibcon#about to read 6, iclass 16, count 0 2006.201.15:54:15.25#ibcon#read 6, iclass 16, count 0 2006.201.15:54:15.25#ibcon#end of sib2, iclass 16, count 0 2006.201.15:54:15.25#ibcon#*after write, iclass 16, count 0 2006.201.15:54:15.25#ibcon#*before return 0, iclass 16, count 0 2006.201.15:54:15.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:15.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:15.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:54:15.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:54:15.25$vck44/va=5,4 2006.201.15:54:15.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.15:54:15.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.15:54:15.25#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:15.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:15.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:15.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:15.31#ibcon#enter wrdev, iclass 18, count 2 2006.201.15:54:15.31#ibcon#first serial, iclass 18, count 2 2006.201.15:54:15.31#ibcon#enter sib2, iclass 18, count 2 2006.201.15:54:15.31#ibcon#flushed, iclass 18, count 2 2006.201.15:54:15.31#ibcon#about to write, iclass 18, count 2 2006.201.15:54:15.31#ibcon#wrote, iclass 18, count 2 2006.201.15:54:15.31#ibcon#about to read 3, iclass 18, count 2 2006.201.15:54:15.33#ibcon#read 3, iclass 18, count 2 2006.201.15:54:15.33#ibcon#about to read 4, iclass 18, count 2 2006.201.15:54:15.33#ibcon#read 4, iclass 18, count 2 2006.201.15:54:15.33#ibcon#about to read 5, iclass 18, count 2 2006.201.15:54:15.33#ibcon#read 5, iclass 18, count 2 2006.201.15:54:15.33#ibcon#about to read 6, iclass 18, count 2 2006.201.15:54:15.33#ibcon#read 6, iclass 18, count 2 2006.201.15:54:15.33#ibcon#end of sib2, iclass 18, count 2 2006.201.15:54:15.33#ibcon#*mode == 0, iclass 18, count 2 2006.201.15:54:15.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.15:54:15.33#ibcon#[25=AT05-04\r\n] 2006.201.15:54:15.33#ibcon#*before write, iclass 18, count 2 2006.201.15:54:15.33#ibcon#enter sib2, iclass 18, count 2 2006.201.15:54:15.33#ibcon#flushed, iclass 18, count 2 2006.201.15:54:15.33#ibcon#about to write, iclass 18, count 2 2006.201.15:54:15.33#ibcon#wrote, iclass 18, count 2 2006.201.15:54:15.33#ibcon#about to read 3, iclass 18, count 2 2006.201.15:54:15.36#ibcon#read 3, iclass 18, count 2 2006.201.15:54:15.36#ibcon#about to read 4, iclass 18, count 2 2006.201.15:54:15.36#ibcon#read 4, iclass 18, count 2 2006.201.15:54:15.36#ibcon#about to read 5, iclass 18, count 2 2006.201.15:54:15.36#ibcon#read 5, iclass 18, count 2 2006.201.15:54:15.36#ibcon#about to read 6, iclass 18, count 2 2006.201.15:54:15.36#ibcon#read 6, iclass 18, count 2 2006.201.15:54:15.36#ibcon#end of sib2, iclass 18, count 2 2006.201.15:54:15.36#ibcon#*after write, iclass 18, count 2 2006.201.15:54:15.36#ibcon#*before return 0, iclass 18, count 2 2006.201.15:54:15.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:15.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:15.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.15:54:15.36#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:15.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:15.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:15.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:15.48#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:54:15.48#ibcon#first serial, iclass 18, count 0 2006.201.15:54:15.48#ibcon#enter sib2, iclass 18, count 0 2006.201.15:54:15.48#ibcon#flushed, iclass 18, count 0 2006.201.15:54:15.48#ibcon#about to write, iclass 18, count 0 2006.201.15:54:15.48#ibcon#wrote, iclass 18, count 0 2006.201.15:54:15.48#ibcon#about to read 3, iclass 18, count 0 2006.201.15:54:15.50#ibcon#read 3, iclass 18, count 0 2006.201.15:54:15.50#ibcon#about to read 4, iclass 18, count 0 2006.201.15:54:15.50#ibcon#read 4, iclass 18, count 0 2006.201.15:54:15.50#ibcon#about to read 5, iclass 18, count 0 2006.201.15:54:15.50#ibcon#read 5, iclass 18, count 0 2006.201.15:54:15.50#ibcon#about to read 6, iclass 18, count 0 2006.201.15:54:15.50#ibcon#read 6, iclass 18, count 0 2006.201.15:54:15.50#ibcon#end of sib2, iclass 18, count 0 2006.201.15:54:15.50#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:54:15.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:54:15.50#ibcon#[25=USB\r\n] 2006.201.15:54:15.50#ibcon#*before write, iclass 18, count 0 2006.201.15:54:15.50#ibcon#enter sib2, iclass 18, count 0 2006.201.15:54:15.50#ibcon#flushed, iclass 18, count 0 2006.201.15:54:15.50#ibcon#about to write, iclass 18, count 0 2006.201.15:54:15.50#ibcon#wrote, iclass 18, count 0 2006.201.15:54:15.50#ibcon#about to read 3, iclass 18, count 0 2006.201.15:54:15.53#ibcon#read 3, iclass 18, count 0 2006.201.15:54:15.53#ibcon#about to read 4, iclass 18, count 0 2006.201.15:54:15.53#ibcon#read 4, iclass 18, count 0 2006.201.15:54:15.53#ibcon#about to read 5, iclass 18, count 0 2006.201.15:54:15.53#ibcon#read 5, iclass 18, count 0 2006.201.15:54:15.53#ibcon#about to read 6, iclass 18, count 0 2006.201.15:54:15.53#ibcon#read 6, iclass 18, count 0 2006.201.15:54:15.53#ibcon#end of sib2, iclass 18, count 0 2006.201.15:54:15.53#ibcon#*after write, iclass 18, count 0 2006.201.15:54:15.53#ibcon#*before return 0, iclass 18, count 0 2006.201.15:54:15.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:15.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:15.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:54:15.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:54:15.53$vck44/valo=6,814.99 2006.201.15:54:15.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.15:54:15.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.15:54:15.53#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:15.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:15.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:15.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:15.53#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:54:15.53#ibcon#first serial, iclass 20, count 0 2006.201.15:54:15.53#ibcon#enter sib2, iclass 20, count 0 2006.201.15:54:15.53#ibcon#flushed, iclass 20, count 0 2006.201.15:54:15.53#ibcon#about to write, iclass 20, count 0 2006.201.15:54:15.53#ibcon#wrote, iclass 20, count 0 2006.201.15:54:15.53#ibcon#about to read 3, iclass 20, count 0 2006.201.15:54:15.55#ibcon#read 3, iclass 20, count 0 2006.201.15:54:15.55#ibcon#about to read 4, iclass 20, count 0 2006.201.15:54:15.55#ibcon#read 4, iclass 20, count 0 2006.201.15:54:15.55#ibcon#about to read 5, iclass 20, count 0 2006.201.15:54:15.55#ibcon#read 5, iclass 20, count 0 2006.201.15:54:15.55#ibcon#about to read 6, iclass 20, count 0 2006.201.15:54:15.55#ibcon#read 6, iclass 20, count 0 2006.201.15:54:15.55#ibcon#end of sib2, iclass 20, count 0 2006.201.15:54:15.55#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:54:15.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:54:15.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.15:54:15.55#ibcon#*before write, iclass 20, count 0 2006.201.15:54:15.55#ibcon#enter sib2, iclass 20, count 0 2006.201.15:54:15.55#ibcon#flushed, iclass 20, count 0 2006.201.15:54:15.55#ibcon#about to write, iclass 20, count 0 2006.201.15:54:15.55#ibcon#wrote, iclass 20, count 0 2006.201.15:54:15.55#ibcon#about to read 3, iclass 20, count 0 2006.201.15:54:15.59#ibcon#read 3, iclass 20, count 0 2006.201.15:54:15.59#ibcon#about to read 4, iclass 20, count 0 2006.201.15:54:15.59#ibcon#read 4, iclass 20, count 0 2006.201.15:54:15.59#ibcon#about to read 5, iclass 20, count 0 2006.201.15:54:15.59#ibcon#read 5, iclass 20, count 0 2006.201.15:54:15.59#ibcon#about to read 6, iclass 20, count 0 2006.201.15:54:15.59#ibcon#read 6, iclass 20, count 0 2006.201.15:54:15.59#ibcon#end of sib2, iclass 20, count 0 2006.201.15:54:15.59#ibcon#*after write, iclass 20, count 0 2006.201.15:54:15.59#ibcon#*before return 0, iclass 20, count 0 2006.201.15:54:15.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:15.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:15.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:54:15.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:54:15.59$vck44/va=6,5 2006.201.15:54:15.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.15:54:15.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.15:54:15.59#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:15.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:15.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:15.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:15.65#ibcon#enter wrdev, iclass 22, count 2 2006.201.15:54:15.65#ibcon#first serial, iclass 22, count 2 2006.201.15:54:15.65#ibcon#enter sib2, iclass 22, count 2 2006.201.15:54:15.65#ibcon#flushed, iclass 22, count 2 2006.201.15:54:15.65#ibcon#about to write, iclass 22, count 2 2006.201.15:54:15.65#ibcon#wrote, iclass 22, count 2 2006.201.15:54:15.65#ibcon#about to read 3, iclass 22, count 2 2006.201.15:54:15.67#ibcon#read 3, iclass 22, count 2 2006.201.15:54:15.67#ibcon#about to read 4, iclass 22, count 2 2006.201.15:54:15.67#ibcon#read 4, iclass 22, count 2 2006.201.15:54:15.67#ibcon#about to read 5, iclass 22, count 2 2006.201.15:54:15.67#ibcon#read 5, iclass 22, count 2 2006.201.15:54:15.67#ibcon#about to read 6, iclass 22, count 2 2006.201.15:54:15.67#ibcon#read 6, iclass 22, count 2 2006.201.15:54:15.67#ibcon#end of sib2, iclass 22, count 2 2006.201.15:54:15.67#ibcon#*mode == 0, iclass 22, count 2 2006.201.15:54:15.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.15:54:15.67#ibcon#[25=AT06-05\r\n] 2006.201.15:54:15.67#ibcon#*before write, iclass 22, count 2 2006.201.15:54:15.67#ibcon#enter sib2, iclass 22, count 2 2006.201.15:54:15.67#ibcon#flushed, iclass 22, count 2 2006.201.15:54:15.67#ibcon#about to write, iclass 22, count 2 2006.201.15:54:15.67#ibcon#wrote, iclass 22, count 2 2006.201.15:54:15.67#ibcon#about to read 3, iclass 22, count 2 2006.201.15:54:15.70#ibcon#read 3, iclass 22, count 2 2006.201.15:54:15.70#ibcon#about to read 4, iclass 22, count 2 2006.201.15:54:15.70#ibcon#read 4, iclass 22, count 2 2006.201.15:54:15.70#ibcon#about to read 5, iclass 22, count 2 2006.201.15:54:15.70#ibcon#read 5, iclass 22, count 2 2006.201.15:54:15.70#ibcon#about to read 6, iclass 22, count 2 2006.201.15:54:15.70#ibcon#read 6, iclass 22, count 2 2006.201.15:54:15.70#ibcon#end of sib2, iclass 22, count 2 2006.201.15:54:15.70#ibcon#*after write, iclass 22, count 2 2006.201.15:54:15.70#ibcon#*before return 0, iclass 22, count 2 2006.201.15:54:15.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:15.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:15.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.15:54:15.70#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:15.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:15.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:15.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:15.82#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:54:15.82#ibcon#first serial, iclass 22, count 0 2006.201.15:54:15.82#ibcon#enter sib2, iclass 22, count 0 2006.201.15:54:15.82#ibcon#flushed, iclass 22, count 0 2006.201.15:54:15.82#ibcon#about to write, iclass 22, count 0 2006.201.15:54:15.82#ibcon#wrote, iclass 22, count 0 2006.201.15:54:15.82#ibcon#about to read 3, iclass 22, count 0 2006.201.15:54:15.84#ibcon#read 3, iclass 22, count 0 2006.201.15:54:15.84#ibcon#about to read 4, iclass 22, count 0 2006.201.15:54:15.84#ibcon#read 4, iclass 22, count 0 2006.201.15:54:15.84#ibcon#about to read 5, iclass 22, count 0 2006.201.15:54:15.84#ibcon#read 5, iclass 22, count 0 2006.201.15:54:15.84#ibcon#about to read 6, iclass 22, count 0 2006.201.15:54:15.84#ibcon#read 6, iclass 22, count 0 2006.201.15:54:15.84#ibcon#end of sib2, iclass 22, count 0 2006.201.15:54:15.84#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:54:15.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:54:15.84#ibcon#[25=USB\r\n] 2006.201.15:54:15.84#ibcon#*before write, iclass 22, count 0 2006.201.15:54:15.84#ibcon#enter sib2, iclass 22, count 0 2006.201.15:54:15.84#ibcon#flushed, iclass 22, count 0 2006.201.15:54:15.84#ibcon#about to write, iclass 22, count 0 2006.201.15:54:15.84#ibcon#wrote, iclass 22, count 0 2006.201.15:54:15.84#ibcon#about to read 3, iclass 22, count 0 2006.201.15:54:15.87#ibcon#read 3, iclass 22, count 0 2006.201.15:54:15.87#ibcon#about to read 4, iclass 22, count 0 2006.201.15:54:15.87#ibcon#read 4, iclass 22, count 0 2006.201.15:54:15.87#ibcon#about to read 5, iclass 22, count 0 2006.201.15:54:15.87#ibcon#read 5, iclass 22, count 0 2006.201.15:54:15.87#ibcon#about to read 6, iclass 22, count 0 2006.201.15:54:15.87#ibcon#read 6, iclass 22, count 0 2006.201.15:54:15.87#ibcon#end of sib2, iclass 22, count 0 2006.201.15:54:15.87#ibcon#*after write, iclass 22, count 0 2006.201.15:54:15.87#ibcon#*before return 0, iclass 22, count 0 2006.201.15:54:15.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:15.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:15.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:54:15.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:54:15.87$vck44/valo=7,864.99 2006.201.15:54:15.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.15:54:15.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.15:54:15.87#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:15.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:15.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:15.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:15.87#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:54:15.87#ibcon#first serial, iclass 24, count 0 2006.201.15:54:15.87#ibcon#enter sib2, iclass 24, count 0 2006.201.15:54:15.87#ibcon#flushed, iclass 24, count 0 2006.201.15:54:15.87#ibcon#about to write, iclass 24, count 0 2006.201.15:54:15.87#ibcon#wrote, iclass 24, count 0 2006.201.15:54:15.87#ibcon#about to read 3, iclass 24, count 0 2006.201.15:54:15.89#ibcon#read 3, iclass 24, count 0 2006.201.15:54:15.89#ibcon#about to read 4, iclass 24, count 0 2006.201.15:54:15.89#ibcon#read 4, iclass 24, count 0 2006.201.15:54:15.89#ibcon#about to read 5, iclass 24, count 0 2006.201.15:54:15.89#ibcon#read 5, iclass 24, count 0 2006.201.15:54:15.89#ibcon#about to read 6, iclass 24, count 0 2006.201.15:54:15.89#ibcon#read 6, iclass 24, count 0 2006.201.15:54:15.89#ibcon#end of sib2, iclass 24, count 0 2006.201.15:54:15.89#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:54:15.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:54:15.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.15:54:15.89#ibcon#*before write, iclass 24, count 0 2006.201.15:54:15.89#ibcon#enter sib2, iclass 24, count 0 2006.201.15:54:15.89#ibcon#flushed, iclass 24, count 0 2006.201.15:54:15.89#ibcon#about to write, iclass 24, count 0 2006.201.15:54:15.89#ibcon#wrote, iclass 24, count 0 2006.201.15:54:15.89#ibcon#about to read 3, iclass 24, count 0 2006.201.15:54:15.93#ibcon#read 3, iclass 24, count 0 2006.201.15:54:15.93#ibcon#about to read 4, iclass 24, count 0 2006.201.15:54:15.93#ibcon#read 4, iclass 24, count 0 2006.201.15:54:15.93#ibcon#about to read 5, iclass 24, count 0 2006.201.15:54:15.93#ibcon#read 5, iclass 24, count 0 2006.201.15:54:15.93#ibcon#about to read 6, iclass 24, count 0 2006.201.15:54:15.93#ibcon#read 6, iclass 24, count 0 2006.201.15:54:15.93#ibcon#end of sib2, iclass 24, count 0 2006.201.15:54:15.93#ibcon#*after write, iclass 24, count 0 2006.201.15:54:15.93#ibcon#*before return 0, iclass 24, count 0 2006.201.15:54:15.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:15.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:15.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:54:15.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:54:15.93$vck44/va=7,5 2006.201.15:54:15.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.15:54:15.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.15:54:15.93#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:15.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:15.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:15.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:15.99#ibcon#enter wrdev, iclass 26, count 2 2006.201.15:54:15.99#ibcon#first serial, iclass 26, count 2 2006.201.15:54:15.99#ibcon#enter sib2, iclass 26, count 2 2006.201.15:54:15.99#ibcon#flushed, iclass 26, count 2 2006.201.15:54:15.99#ibcon#about to write, iclass 26, count 2 2006.201.15:54:15.99#ibcon#wrote, iclass 26, count 2 2006.201.15:54:15.99#ibcon#about to read 3, iclass 26, count 2 2006.201.15:54:16.01#ibcon#read 3, iclass 26, count 2 2006.201.15:54:16.01#ibcon#about to read 4, iclass 26, count 2 2006.201.15:54:16.01#ibcon#read 4, iclass 26, count 2 2006.201.15:54:16.01#ibcon#about to read 5, iclass 26, count 2 2006.201.15:54:16.01#ibcon#read 5, iclass 26, count 2 2006.201.15:54:16.01#ibcon#about to read 6, iclass 26, count 2 2006.201.15:54:16.01#ibcon#read 6, iclass 26, count 2 2006.201.15:54:16.01#ibcon#end of sib2, iclass 26, count 2 2006.201.15:54:16.01#ibcon#*mode == 0, iclass 26, count 2 2006.201.15:54:16.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.15:54:16.01#ibcon#[25=AT07-05\r\n] 2006.201.15:54:16.01#ibcon#*before write, iclass 26, count 2 2006.201.15:54:16.01#ibcon#enter sib2, iclass 26, count 2 2006.201.15:54:16.01#ibcon#flushed, iclass 26, count 2 2006.201.15:54:16.01#ibcon#about to write, iclass 26, count 2 2006.201.15:54:16.01#ibcon#wrote, iclass 26, count 2 2006.201.15:54:16.01#ibcon#about to read 3, iclass 26, count 2 2006.201.15:54:16.04#ibcon#read 3, iclass 26, count 2 2006.201.15:54:16.04#ibcon#about to read 4, iclass 26, count 2 2006.201.15:54:16.04#ibcon#read 4, iclass 26, count 2 2006.201.15:54:16.04#ibcon#about to read 5, iclass 26, count 2 2006.201.15:54:16.04#ibcon#read 5, iclass 26, count 2 2006.201.15:54:16.04#ibcon#about to read 6, iclass 26, count 2 2006.201.15:54:16.04#ibcon#read 6, iclass 26, count 2 2006.201.15:54:16.04#ibcon#end of sib2, iclass 26, count 2 2006.201.15:54:16.04#ibcon#*after write, iclass 26, count 2 2006.201.15:54:16.04#ibcon#*before return 0, iclass 26, count 2 2006.201.15:54:16.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:16.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:16.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.15:54:16.04#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:16.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:16.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:16.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:16.16#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:54:16.16#ibcon#first serial, iclass 26, count 0 2006.201.15:54:16.16#ibcon#enter sib2, iclass 26, count 0 2006.201.15:54:16.16#ibcon#flushed, iclass 26, count 0 2006.201.15:54:16.16#ibcon#about to write, iclass 26, count 0 2006.201.15:54:16.16#ibcon#wrote, iclass 26, count 0 2006.201.15:54:16.16#ibcon#about to read 3, iclass 26, count 0 2006.201.15:54:16.18#ibcon#read 3, iclass 26, count 0 2006.201.15:54:16.19#ibcon#about to read 4, iclass 26, count 0 2006.201.15:54:16.19#ibcon#read 4, iclass 26, count 0 2006.201.15:54:16.19#ibcon#about to read 5, iclass 26, count 0 2006.201.15:54:16.19#ibcon#read 5, iclass 26, count 0 2006.201.15:54:16.19#ibcon#about to read 6, iclass 26, count 0 2006.201.15:54:16.19#ibcon#read 6, iclass 26, count 0 2006.201.15:54:16.19#ibcon#end of sib2, iclass 26, count 0 2006.201.15:54:16.19#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:54:16.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:54:16.19#ibcon#[25=USB\r\n] 2006.201.15:54:16.19#ibcon#*before write, iclass 26, count 0 2006.201.15:54:16.19#ibcon#enter sib2, iclass 26, count 0 2006.201.15:54:16.19#ibcon#flushed, iclass 26, count 0 2006.201.15:54:16.19#ibcon#about to write, iclass 26, count 0 2006.201.15:54:16.19#ibcon#wrote, iclass 26, count 0 2006.201.15:54:16.19#ibcon#about to read 3, iclass 26, count 0 2006.201.15:54:16.22#ibcon#read 3, iclass 26, count 0 2006.201.15:54:16.22#ibcon#about to read 4, iclass 26, count 0 2006.201.15:54:16.22#ibcon#read 4, iclass 26, count 0 2006.201.15:54:16.22#ibcon#about to read 5, iclass 26, count 0 2006.201.15:54:16.22#ibcon#read 5, iclass 26, count 0 2006.201.15:54:16.22#ibcon#about to read 6, iclass 26, count 0 2006.201.15:54:16.22#ibcon#read 6, iclass 26, count 0 2006.201.15:54:16.22#ibcon#end of sib2, iclass 26, count 0 2006.201.15:54:16.22#ibcon#*after write, iclass 26, count 0 2006.201.15:54:16.22#ibcon#*before return 0, iclass 26, count 0 2006.201.15:54:16.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:16.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:16.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:54:16.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:54:16.22$vck44/valo=8,884.99 2006.201.15:54:16.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.15:54:16.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.15:54:16.22#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:16.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:16.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:16.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:16.22#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:54:16.22#ibcon#first serial, iclass 28, count 0 2006.201.15:54:16.22#ibcon#enter sib2, iclass 28, count 0 2006.201.15:54:16.22#ibcon#flushed, iclass 28, count 0 2006.201.15:54:16.22#ibcon#about to write, iclass 28, count 0 2006.201.15:54:16.22#ibcon#wrote, iclass 28, count 0 2006.201.15:54:16.22#ibcon#about to read 3, iclass 28, count 0 2006.201.15:54:16.24#ibcon#read 3, iclass 28, count 0 2006.201.15:54:16.24#ibcon#about to read 4, iclass 28, count 0 2006.201.15:54:16.24#ibcon#read 4, iclass 28, count 0 2006.201.15:54:16.24#ibcon#about to read 5, iclass 28, count 0 2006.201.15:54:16.24#ibcon#read 5, iclass 28, count 0 2006.201.15:54:16.24#ibcon#about to read 6, iclass 28, count 0 2006.201.15:54:16.24#ibcon#read 6, iclass 28, count 0 2006.201.15:54:16.24#ibcon#end of sib2, iclass 28, count 0 2006.201.15:54:16.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:54:16.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:54:16.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.15:54:16.24#ibcon#*before write, iclass 28, count 0 2006.201.15:54:16.24#ibcon#enter sib2, iclass 28, count 0 2006.201.15:54:16.24#ibcon#flushed, iclass 28, count 0 2006.201.15:54:16.24#ibcon#about to write, iclass 28, count 0 2006.201.15:54:16.24#ibcon#wrote, iclass 28, count 0 2006.201.15:54:16.24#ibcon#about to read 3, iclass 28, count 0 2006.201.15:54:16.28#ibcon#read 3, iclass 28, count 0 2006.201.15:54:16.28#ibcon#about to read 4, iclass 28, count 0 2006.201.15:54:16.28#ibcon#read 4, iclass 28, count 0 2006.201.15:54:16.28#ibcon#about to read 5, iclass 28, count 0 2006.201.15:54:16.28#ibcon#read 5, iclass 28, count 0 2006.201.15:54:16.28#ibcon#about to read 6, iclass 28, count 0 2006.201.15:54:16.28#ibcon#read 6, iclass 28, count 0 2006.201.15:54:16.28#ibcon#end of sib2, iclass 28, count 0 2006.201.15:54:16.28#ibcon#*after write, iclass 28, count 0 2006.201.15:54:16.28#ibcon#*before return 0, iclass 28, count 0 2006.201.15:54:16.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:16.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:16.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:54:16.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:54:16.28$vck44/va=8,4 2006.201.15:54:16.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.15:54:16.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.15:54:16.28#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:16.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:54:16.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:54:16.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:54:16.34#ibcon#enter wrdev, iclass 30, count 2 2006.201.15:54:16.34#ibcon#first serial, iclass 30, count 2 2006.201.15:54:16.34#ibcon#enter sib2, iclass 30, count 2 2006.201.15:54:16.34#ibcon#flushed, iclass 30, count 2 2006.201.15:54:16.34#ibcon#about to write, iclass 30, count 2 2006.201.15:54:16.34#ibcon#wrote, iclass 30, count 2 2006.201.15:54:16.34#ibcon#about to read 3, iclass 30, count 2 2006.201.15:54:16.36#ibcon#read 3, iclass 30, count 2 2006.201.15:54:16.36#ibcon#about to read 4, iclass 30, count 2 2006.201.15:54:16.36#ibcon#read 4, iclass 30, count 2 2006.201.15:54:16.36#ibcon#about to read 5, iclass 30, count 2 2006.201.15:54:16.36#ibcon#read 5, iclass 30, count 2 2006.201.15:54:16.36#ibcon#about to read 6, iclass 30, count 2 2006.201.15:54:16.36#ibcon#read 6, iclass 30, count 2 2006.201.15:54:16.36#ibcon#end of sib2, iclass 30, count 2 2006.201.15:54:16.36#ibcon#*mode == 0, iclass 30, count 2 2006.201.15:54:16.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.15:54:16.36#ibcon#[25=AT08-04\r\n] 2006.201.15:54:16.36#ibcon#*before write, iclass 30, count 2 2006.201.15:54:16.36#ibcon#enter sib2, iclass 30, count 2 2006.201.15:54:16.36#ibcon#flushed, iclass 30, count 2 2006.201.15:54:16.36#ibcon#about to write, iclass 30, count 2 2006.201.15:54:16.36#ibcon#wrote, iclass 30, count 2 2006.201.15:54:16.36#ibcon#about to read 3, iclass 30, count 2 2006.201.15:54:16.40#ibcon#read 3, iclass 30, count 2 2006.201.15:54:16.40#ibcon#about to read 4, iclass 30, count 2 2006.201.15:54:16.40#ibcon#read 4, iclass 30, count 2 2006.201.15:54:16.40#ibcon#about to read 5, iclass 30, count 2 2006.201.15:54:16.40#ibcon#read 5, iclass 30, count 2 2006.201.15:54:16.40#ibcon#about to read 6, iclass 30, count 2 2006.201.15:54:16.40#ibcon#read 6, iclass 30, count 2 2006.201.15:54:16.40#ibcon#end of sib2, iclass 30, count 2 2006.201.15:54:16.40#ibcon#*after write, iclass 30, count 2 2006.201.15:54:16.40#ibcon#*before return 0, iclass 30, count 2 2006.201.15:54:16.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:54:16.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.15:54:16.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.15:54:16.40#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:16.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:54:16.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:54:16.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:54:16.52#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:54:16.52#ibcon#first serial, iclass 30, count 0 2006.201.15:54:16.52#ibcon#enter sib2, iclass 30, count 0 2006.201.15:54:16.52#ibcon#flushed, iclass 30, count 0 2006.201.15:54:16.52#ibcon#about to write, iclass 30, count 0 2006.201.15:54:16.52#ibcon#wrote, iclass 30, count 0 2006.201.15:54:16.52#ibcon#about to read 3, iclass 30, count 0 2006.201.15:54:16.54#ibcon#read 3, iclass 30, count 0 2006.201.15:54:16.54#ibcon#about to read 4, iclass 30, count 0 2006.201.15:54:16.54#ibcon#read 4, iclass 30, count 0 2006.201.15:54:16.54#ibcon#about to read 5, iclass 30, count 0 2006.201.15:54:16.54#ibcon#read 5, iclass 30, count 0 2006.201.15:54:16.54#ibcon#about to read 6, iclass 30, count 0 2006.201.15:54:16.54#ibcon#read 6, iclass 30, count 0 2006.201.15:54:16.54#ibcon#end of sib2, iclass 30, count 0 2006.201.15:54:16.54#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:54:16.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:54:16.54#ibcon#[25=USB\r\n] 2006.201.15:54:16.54#ibcon#*before write, iclass 30, count 0 2006.201.15:54:16.54#ibcon#enter sib2, iclass 30, count 0 2006.201.15:54:16.54#ibcon#flushed, iclass 30, count 0 2006.201.15:54:16.54#ibcon#about to write, iclass 30, count 0 2006.201.15:54:16.54#ibcon#wrote, iclass 30, count 0 2006.201.15:54:16.54#ibcon#about to read 3, iclass 30, count 0 2006.201.15:54:16.57#ibcon#read 3, iclass 30, count 0 2006.201.15:54:16.57#ibcon#about to read 4, iclass 30, count 0 2006.201.15:54:16.57#ibcon#read 4, iclass 30, count 0 2006.201.15:54:16.57#ibcon#about to read 5, iclass 30, count 0 2006.201.15:54:16.57#ibcon#read 5, iclass 30, count 0 2006.201.15:54:16.57#ibcon#about to read 6, iclass 30, count 0 2006.201.15:54:16.57#ibcon#read 6, iclass 30, count 0 2006.201.15:54:16.57#ibcon#end of sib2, iclass 30, count 0 2006.201.15:54:16.57#ibcon#*after write, iclass 30, count 0 2006.201.15:54:16.57#ibcon#*before return 0, iclass 30, count 0 2006.201.15:54:16.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:54:16.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.15:54:16.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:54:16.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:54:16.57$vck44/vblo=1,629.99 2006.201.15:54:16.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.15:54:16.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.15:54:16.57#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:16.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:54:16.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:54:16.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:54:16.57#ibcon#enter wrdev, iclass 32, count 0 2006.201.15:54:16.57#ibcon#first serial, iclass 32, count 0 2006.201.15:54:16.57#ibcon#enter sib2, iclass 32, count 0 2006.201.15:54:16.57#ibcon#flushed, iclass 32, count 0 2006.201.15:54:16.57#ibcon#about to write, iclass 32, count 0 2006.201.15:54:16.57#ibcon#wrote, iclass 32, count 0 2006.201.15:54:16.57#ibcon#about to read 3, iclass 32, count 0 2006.201.15:54:16.59#ibcon#read 3, iclass 32, count 0 2006.201.15:54:16.59#ibcon#about to read 4, iclass 32, count 0 2006.201.15:54:16.59#ibcon#read 4, iclass 32, count 0 2006.201.15:54:16.59#ibcon#about to read 5, iclass 32, count 0 2006.201.15:54:16.59#ibcon#read 5, iclass 32, count 0 2006.201.15:54:16.59#ibcon#about to read 6, iclass 32, count 0 2006.201.15:54:16.59#ibcon#read 6, iclass 32, count 0 2006.201.15:54:16.59#ibcon#end of sib2, iclass 32, count 0 2006.201.15:54:16.59#ibcon#*mode == 0, iclass 32, count 0 2006.201.15:54:16.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.15:54:16.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.15:54:16.59#ibcon#*before write, iclass 32, count 0 2006.201.15:54:16.59#ibcon#enter sib2, iclass 32, count 0 2006.201.15:54:16.59#ibcon#flushed, iclass 32, count 0 2006.201.15:54:16.59#ibcon#about to write, iclass 32, count 0 2006.201.15:54:16.59#ibcon#wrote, iclass 32, count 0 2006.201.15:54:16.59#ibcon#about to read 3, iclass 32, count 0 2006.201.15:54:16.63#ibcon#read 3, iclass 32, count 0 2006.201.15:54:16.63#ibcon#about to read 4, iclass 32, count 0 2006.201.15:54:16.63#ibcon#read 4, iclass 32, count 0 2006.201.15:54:16.63#ibcon#about to read 5, iclass 32, count 0 2006.201.15:54:16.63#ibcon#read 5, iclass 32, count 0 2006.201.15:54:16.63#ibcon#about to read 6, iclass 32, count 0 2006.201.15:54:16.63#ibcon#read 6, iclass 32, count 0 2006.201.15:54:16.63#ibcon#end of sib2, iclass 32, count 0 2006.201.15:54:16.63#ibcon#*after write, iclass 32, count 0 2006.201.15:54:16.63#ibcon#*before return 0, iclass 32, count 0 2006.201.15:54:16.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:54:16.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.15:54:16.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.15:54:16.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.15:54:16.63$vck44/vb=1,4 2006.201.15:54:16.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.15:54:16.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.15:54:16.63#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:16.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:54:16.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:54:16.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:54:16.63#ibcon#enter wrdev, iclass 34, count 2 2006.201.15:54:16.63#ibcon#first serial, iclass 34, count 2 2006.201.15:54:16.63#ibcon#enter sib2, iclass 34, count 2 2006.201.15:54:16.63#ibcon#flushed, iclass 34, count 2 2006.201.15:54:16.63#ibcon#about to write, iclass 34, count 2 2006.201.15:54:16.63#ibcon#wrote, iclass 34, count 2 2006.201.15:54:16.63#ibcon#about to read 3, iclass 34, count 2 2006.201.15:54:16.65#ibcon#read 3, iclass 34, count 2 2006.201.15:54:16.65#ibcon#about to read 4, iclass 34, count 2 2006.201.15:54:16.65#ibcon#read 4, iclass 34, count 2 2006.201.15:54:16.65#ibcon#about to read 5, iclass 34, count 2 2006.201.15:54:16.65#ibcon#read 5, iclass 34, count 2 2006.201.15:54:16.65#ibcon#about to read 6, iclass 34, count 2 2006.201.15:54:16.65#ibcon#read 6, iclass 34, count 2 2006.201.15:54:16.65#ibcon#end of sib2, iclass 34, count 2 2006.201.15:54:16.65#ibcon#*mode == 0, iclass 34, count 2 2006.201.15:54:16.65#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.15:54:16.65#ibcon#[27=AT01-04\r\n] 2006.201.15:54:16.65#ibcon#*before write, iclass 34, count 2 2006.201.15:54:16.65#ibcon#enter sib2, iclass 34, count 2 2006.201.15:54:16.65#ibcon#flushed, iclass 34, count 2 2006.201.15:54:16.65#ibcon#about to write, iclass 34, count 2 2006.201.15:54:16.65#ibcon#wrote, iclass 34, count 2 2006.201.15:54:16.65#ibcon#about to read 3, iclass 34, count 2 2006.201.15:54:16.68#ibcon#read 3, iclass 34, count 2 2006.201.15:54:16.68#ibcon#about to read 4, iclass 34, count 2 2006.201.15:54:16.68#ibcon#read 4, iclass 34, count 2 2006.201.15:54:16.68#ibcon#about to read 5, iclass 34, count 2 2006.201.15:54:16.68#ibcon#read 5, iclass 34, count 2 2006.201.15:54:16.68#ibcon#about to read 6, iclass 34, count 2 2006.201.15:54:16.68#ibcon#read 6, iclass 34, count 2 2006.201.15:54:16.68#ibcon#end of sib2, iclass 34, count 2 2006.201.15:54:16.68#ibcon#*after write, iclass 34, count 2 2006.201.15:54:16.68#ibcon#*before return 0, iclass 34, count 2 2006.201.15:54:16.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:54:16.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.15:54:16.68#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.15:54:16.68#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:16.68#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:54:16.80#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:54:16.80#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:54:16.80#ibcon#enter wrdev, iclass 34, count 0 2006.201.15:54:16.80#ibcon#first serial, iclass 34, count 0 2006.201.15:54:16.80#ibcon#enter sib2, iclass 34, count 0 2006.201.15:54:16.80#ibcon#flushed, iclass 34, count 0 2006.201.15:54:16.80#ibcon#about to write, iclass 34, count 0 2006.201.15:54:16.80#ibcon#wrote, iclass 34, count 0 2006.201.15:54:16.80#ibcon#about to read 3, iclass 34, count 0 2006.201.15:54:16.82#ibcon#read 3, iclass 34, count 0 2006.201.15:54:16.82#ibcon#about to read 4, iclass 34, count 0 2006.201.15:54:16.82#ibcon#read 4, iclass 34, count 0 2006.201.15:54:16.82#ibcon#about to read 5, iclass 34, count 0 2006.201.15:54:16.82#ibcon#read 5, iclass 34, count 0 2006.201.15:54:16.82#ibcon#about to read 6, iclass 34, count 0 2006.201.15:54:16.82#ibcon#read 6, iclass 34, count 0 2006.201.15:54:16.82#ibcon#end of sib2, iclass 34, count 0 2006.201.15:54:16.82#ibcon#*mode == 0, iclass 34, count 0 2006.201.15:54:16.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.15:54:16.82#ibcon#[27=USB\r\n] 2006.201.15:54:16.82#ibcon#*before write, iclass 34, count 0 2006.201.15:54:16.82#ibcon#enter sib2, iclass 34, count 0 2006.201.15:54:16.82#ibcon#flushed, iclass 34, count 0 2006.201.15:54:16.82#ibcon#about to write, iclass 34, count 0 2006.201.15:54:16.82#ibcon#wrote, iclass 34, count 0 2006.201.15:54:16.82#ibcon#about to read 3, iclass 34, count 0 2006.201.15:54:16.85#ibcon#read 3, iclass 34, count 0 2006.201.15:54:16.85#ibcon#about to read 4, iclass 34, count 0 2006.201.15:54:16.85#ibcon#read 4, iclass 34, count 0 2006.201.15:54:16.85#ibcon#about to read 5, iclass 34, count 0 2006.201.15:54:16.85#ibcon#read 5, iclass 34, count 0 2006.201.15:54:16.85#ibcon#about to read 6, iclass 34, count 0 2006.201.15:54:16.85#ibcon#read 6, iclass 34, count 0 2006.201.15:54:16.85#ibcon#end of sib2, iclass 34, count 0 2006.201.15:54:16.85#ibcon#*after write, iclass 34, count 0 2006.201.15:54:16.85#ibcon#*before return 0, iclass 34, count 0 2006.201.15:54:16.85#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:54:16.85#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.15:54:16.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.15:54:16.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.15:54:16.85$vck44/vblo=2,634.99 2006.201.15:54:16.85#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.15:54:16.85#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.15:54:16.85#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:16.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:16.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:16.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:16.85#ibcon#enter wrdev, iclass 36, count 0 2006.201.15:54:16.85#ibcon#first serial, iclass 36, count 0 2006.201.15:54:16.85#ibcon#enter sib2, iclass 36, count 0 2006.201.15:54:16.85#ibcon#flushed, iclass 36, count 0 2006.201.15:54:16.85#ibcon#about to write, iclass 36, count 0 2006.201.15:54:16.85#ibcon#wrote, iclass 36, count 0 2006.201.15:54:16.85#ibcon#about to read 3, iclass 36, count 0 2006.201.15:54:16.87#ibcon#read 3, iclass 36, count 0 2006.201.15:54:16.87#ibcon#about to read 4, iclass 36, count 0 2006.201.15:54:16.87#ibcon#read 4, iclass 36, count 0 2006.201.15:54:16.87#ibcon#about to read 5, iclass 36, count 0 2006.201.15:54:16.87#ibcon#read 5, iclass 36, count 0 2006.201.15:54:16.87#ibcon#about to read 6, iclass 36, count 0 2006.201.15:54:16.87#ibcon#read 6, iclass 36, count 0 2006.201.15:54:16.87#ibcon#end of sib2, iclass 36, count 0 2006.201.15:54:16.87#ibcon#*mode == 0, iclass 36, count 0 2006.201.15:54:16.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.15:54:16.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.15:54:16.87#ibcon#*before write, iclass 36, count 0 2006.201.15:54:16.87#ibcon#enter sib2, iclass 36, count 0 2006.201.15:54:16.87#ibcon#flushed, iclass 36, count 0 2006.201.15:54:16.87#ibcon#about to write, iclass 36, count 0 2006.201.15:54:16.87#ibcon#wrote, iclass 36, count 0 2006.201.15:54:16.87#ibcon#about to read 3, iclass 36, count 0 2006.201.15:54:16.91#ibcon#read 3, iclass 36, count 0 2006.201.15:54:16.91#ibcon#about to read 4, iclass 36, count 0 2006.201.15:54:16.91#ibcon#read 4, iclass 36, count 0 2006.201.15:54:16.91#ibcon#about to read 5, iclass 36, count 0 2006.201.15:54:16.91#ibcon#read 5, iclass 36, count 0 2006.201.15:54:16.91#ibcon#about to read 6, iclass 36, count 0 2006.201.15:54:16.91#ibcon#read 6, iclass 36, count 0 2006.201.15:54:16.91#ibcon#end of sib2, iclass 36, count 0 2006.201.15:54:16.91#ibcon#*after write, iclass 36, count 0 2006.201.15:54:16.91#ibcon#*before return 0, iclass 36, count 0 2006.201.15:54:16.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:16.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.15:54:16.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.15:54:16.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.15:54:16.91$vck44/vb=2,5 2006.201.15:54:16.91#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.15:54:16.91#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.15:54:16.91#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:16.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:16.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:16.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:16.97#ibcon#enter wrdev, iclass 38, count 2 2006.201.15:54:16.97#ibcon#first serial, iclass 38, count 2 2006.201.15:54:16.97#ibcon#enter sib2, iclass 38, count 2 2006.201.15:54:16.97#ibcon#flushed, iclass 38, count 2 2006.201.15:54:16.97#ibcon#about to write, iclass 38, count 2 2006.201.15:54:16.97#ibcon#wrote, iclass 38, count 2 2006.201.15:54:16.97#ibcon#about to read 3, iclass 38, count 2 2006.201.15:54:16.99#ibcon#read 3, iclass 38, count 2 2006.201.15:54:16.99#ibcon#about to read 4, iclass 38, count 2 2006.201.15:54:16.99#ibcon#read 4, iclass 38, count 2 2006.201.15:54:16.99#ibcon#about to read 5, iclass 38, count 2 2006.201.15:54:16.99#ibcon#read 5, iclass 38, count 2 2006.201.15:54:16.99#ibcon#about to read 6, iclass 38, count 2 2006.201.15:54:16.99#ibcon#read 6, iclass 38, count 2 2006.201.15:54:16.99#ibcon#end of sib2, iclass 38, count 2 2006.201.15:54:16.99#ibcon#*mode == 0, iclass 38, count 2 2006.201.15:54:16.99#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.15:54:16.99#ibcon#[27=AT02-05\r\n] 2006.201.15:54:16.99#ibcon#*before write, iclass 38, count 2 2006.201.15:54:16.99#ibcon#enter sib2, iclass 38, count 2 2006.201.15:54:16.99#ibcon#flushed, iclass 38, count 2 2006.201.15:54:16.99#ibcon#about to write, iclass 38, count 2 2006.201.15:54:16.99#ibcon#wrote, iclass 38, count 2 2006.201.15:54:16.99#ibcon#about to read 3, iclass 38, count 2 2006.201.15:54:17.02#ibcon#read 3, iclass 38, count 2 2006.201.15:54:17.02#ibcon#about to read 4, iclass 38, count 2 2006.201.15:54:17.02#ibcon#read 4, iclass 38, count 2 2006.201.15:54:17.02#ibcon#about to read 5, iclass 38, count 2 2006.201.15:54:17.02#ibcon#read 5, iclass 38, count 2 2006.201.15:54:17.02#ibcon#about to read 6, iclass 38, count 2 2006.201.15:54:17.02#ibcon#read 6, iclass 38, count 2 2006.201.15:54:17.02#ibcon#end of sib2, iclass 38, count 2 2006.201.15:54:17.02#ibcon#*after write, iclass 38, count 2 2006.201.15:54:17.02#ibcon#*before return 0, iclass 38, count 2 2006.201.15:54:17.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:17.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.15:54:17.02#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.15:54:17.02#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:17.02#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:17.14#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:17.14#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:17.14#ibcon#enter wrdev, iclass 38, count 0 2006.201.15:54:17.14#ibcon#first serial, iclass 38, count 0 2006.201.15:54:17.14#ibcon#enter sib2, iclass 38, count 0 2006.201.15:54:17.14#ibcon#flushed, iclass 38, count 0 2006.201.15:54:17.14#ibcon#about to write, iclass 38, count 0 2006.201.15:54:17.14#ibcon#wrote, iclass 38, count 0 2006.201.15:54:17.14#ibcon#about to read 3, iclass 38, count 0 2006.201.15:54:17.16#ibcon#read 3, iclass 38, count 0 2006.201.15:54:17.16#ibcon#about to read 4, iclass 38, count 0 2006.201.15:54:17.16#ibcon#read 4, iclass 38, count 0 2006.201.15:54:17.16#ibcon#about to read 5, iclass 38, count 0 2006.201.15:54:17.16#ibcon#read 5, iclass 38, count 0 2006.201.15:54:17.16#ibcon#about to read 6, iclass 38, count 0 2006.201.15:54:17.16#ibcon#read 6, iclass 38, count 0 2006.201.15:54:17.16#ibcon#end of sib2, iclass 38, count 0 2006.201.15:54:17.16#ibcon#*mode == 0, iclass 38, count 0 2006.201.15:54:17.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.15:54:17.16#ibcon#[27=USB\r\n] 2006.201.15:54:17.16#ibcon#*before write, iclass 38, count 0 2006.201.15:54:17.16#ibcon#enter sib2, iclass 38, count 0 2006.201.15:54:17.16#ibcon#flushed, iclass 38, count 0 2006.201.15:54:17.16#ibcon#about to write, iclass 38, count 0 2006.201.15:54:17.16#ibcon#wrote, iclass 38, count 0 2006.201.15:54:17.16#ibcon#about to read 3, iclass 38, count 0 2006.201.15:54:17.19#ibcon#read 3, iclass 38, count 0 2006.201.15:54:17.19#ibcon#about to read 4, iclass 38, count 0 2006.201.15:54:17.19#ibcon#read 4, iclass 38, count 0 2006.201.15:54:17.19#ibcon#about to read 5, iclass 38, count 0 2006.201.15:54:17.19#ibcon#read 5, iclass 38, count 0 2006.201.15:54:17.19#ibcon#about to read 6, iclass 38, count 0 2006.201.15:54:17.19#ibcon#read 6, iclass 38, count 0 2006.201.15:54:17.19#ibcon#end of sib2, iclass 38, count 0 2006.201.15:54:17.19#ibcon#*after write, iclass 38, count 0 2006.201.15:54:17.19#ibcon#*before return 0, iclass 38, count 0 2006.201.15:54:17.19#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:17.19#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.15:54:17.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.15:54:17.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.15:54:17.19$vck44/vblo=3,649.99 2006.201.15:54:17.19#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.15:54:17.19#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.15:54:17.19#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:17.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:17.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:17.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:17.19#ibcon#enter wrdev, iclass 40, count 0 2006.201.15:54:17.19#ibcon#first serial, iclass 40, count 0 2006.201.15:54:17.19#ibcon#enter sib2, iclass 40, count 0 2006.201.15:54:17.19#ibcon#flushed, iclass 40, count 0 2006.201.15:54:17.19#ibcon#about to write, iclass 40, count 0 2006.201.15:54:17.19#ibcon#wrote, iclass 40, count 0 2006.201.15:54:17.19#ibcon#about to read 3, iclass 40, count 0 2006.201.15:54:17.21#ibcon#read 3, iclass 40, count 0 2006.201.15:54:17.21#ibcon#about to read 4, iclass 40, count 0 2006.201.15:54:17.21#ibcon#read 4, iclass 40, count 0 2006.201.15:54:17.21#ibcon#about to read 5, iclass 40, count 0 2006.201.15:54:17.21#ibcon#read 5, iclass 40, count 0 2006.201.15:54:17.21#ibcon#about to read 6, iclass 40, count 0 2006.201.15:54:17.21#ibcon#read 6, iclass 40, count 0 2006.201.15:54:17.21#ibcon#end of sib2, iclass 40, count 0 2006.201.15:54:17.21#ibcon#*mode == 0, iclass 40, count 0 2006.201.15:54:17.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.15:54:17.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.15:54:17.21#ibcon#*before write, iclass 40, count 0 2006.201.15:54:17.21#ibcon#enter sib2, iclass 40, count 0 2006.201.15:54:17.21#ibcon#flushed, iclass 40, count 0 2006.201.15:54:17.21#ibcon#about to write, iclass 40, count 0 2006.201.15:54:17.21#ibcon#wrote, iclass 40, count 0 2006.201.15:54:17.21#ibcon#about to read 3, iclass 40, count 0 2006.201.15:54:17.25#ibcon#read 3, iclass 40, count 0 2006.201.15:54:17.25#ibcon#about to read 4, iclass 40, count 0 2006.201.15:54:17.25#ibcon#read 4, iclass 40, count 0 2006.201.15:54:17.25#ibcon#about to read 5, iclass 40, count 0 2006.201.15:54:17.25#ibcon#read 5, iclass 40, count 0 2006.201.15:54:17.25#ibcon#about to read 6, iclass 40, count 0 2006.201.15:54:17.25#ibcon#read 6, iclass 40, count 0 2006.201.15:54:17.25#ibcon#end of sib2, iclass 40, count 0 2006.201.15:54:17.25#ibcon#*after write, iclass 40, count 0 2006.201.15:54:17.25#ibcon#*before return 0, iclass 40, count 0 2006.201.15:54:17.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:17.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.15:54:17.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.15:54:17.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.15:54:17.25$vck44/vb=3,4 2006.201.15:54:17.25#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.15:54:17.25#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.15:54:17.25#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:17.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:17.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:17.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:17.31#ibcon#enter wrdev, iclass 4, count 2 2006.201.15:54:17.31#ibcon#first serial, iclass 4, count 2 2006.201.15:54:17.31#ibcon#enter sib2, iclass 4, count 2 2006.201.15:54:17.31#ibcon#flushed, iclass 4, count 2 2006.201.15:54:17.31#ibcon#about to write, iclass 4, count 2 2006.201.15:54:17.31#ibcon#wrote, iclass 4, count 2 2006.201.15:54:17.31#ibcon#about to read 3, iclass 4, count 2 2006.201.15:54:17.33#ibcon#read 3, iclass 4, count 2 2006.201.15:54:17.33#ibcon#about to read 4, iclass 4, count 2 2006.201.15:54:17.33#ibcon#read 4, iclass 4, count 2 2006.201.15:54:17.33#ibcon#about to read 5, iclass 4, count 2 2006.201.15:54:17.33#ibcon#read 5, iclass 4, count 2 2006.201.15:54:17.33#ibcon#about to read 6, iclass 4, count 2 2006.201.15:54:17.33#ibcon#read 6, iclass 4, count 2 2006.201.15:54:17.33#ibcon#end of sib2, iclass 4, count 2 2006.201.15:54:17.33#ibcon#*mode == 0, iclass 4, count 2 2006.201.15:54:17.33#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.15:54:17.33#ibcon#[27=AT03-04\r\n] 2006.201.15:54:17.33#ibcon#*before write, iclass 4, count 2 2006.201.15:54:17.33#ibcon#enter sib2, iclass 4, count 2 2006.201.15:54:17.33#ibcon#flushed, iclass 4, count 2 2006.201.15:54:17.33#ibcon#about to write, iclass 4, count 2 2006.201.15:54:17.33#ibcon#wrote, iclass 4, count 2 2006.201.15:54:17.33#ibcon#about to read 3, iclass 4, count 2 2006.201.15:54:17.36#ibcon#read 3, iclass 4, count 2 2006.201.15:54:17.36#ibcon#about to read 4, iclass 4, count 2 2006.201.15:54:17.36#ibcon#read 4, iclass 4, count 2 2006.201.15:54:17.36#ibcon#about to read 5, iclass 4, count 2 2006.201.15:54:17.36#ibcon#read 5, iclass 4, count 2 2006.201.15:54:17.36#ibcon#about to read 6, iclass 4, count 2 2006.201.15:54:17.36#ibcon#read 6, iclass 4, count 2 2006.201.15:54:17.36#ibcon#end of sib2, iclass 4, count 2 2006.201.15:54:17.36#ibcon#*after write, iclass 4, count 2 2006.201.15:54:17.36#ibcon#*before return 0, iclass 4, count 2 2006.201.15:54:17.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:17.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.15:54:17.36#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.15:54:17.36#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:17.36#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:17.48#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:17.48#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:17.48#ibcon#enter wrdev, iclass 4, count 0 2006.201.15:54:17.48#ibcon#first serial, iclass 4, count 0 2006.201.15:54:17.48#ibcon#enter sib2, iclass 4, count 0 2006.201.15:54:17.48#ibcon#flushed, iclass 4, count 0 2006.201.15:54:17.48#ibcon#about to write, iclass 4, count 0 2006.201.15:54:17.48#ibcon#wrote, iclass 4, count 0 2006.201.15:54:17.48#ibcon#about to read 3, iclass 4, count 0 2006.201.15:54:17.50#ibcon#read 3, iclass 4, count 0 2006.201.15:54:17.50#ibcon#about to read 4, iclass 4, count 0 2006.201.15:54:17.50#ibcon#read 4, iclass 4, count 0 2006.201.15:54:17.50#ibcon#about to read 5, iclass 4, count 0 2006.201.15:54:17.50#ibcon#read 5, iclass 4, count 0 2006.201.15:54:17.50#ibcon#about to read 6, iclass 4, count 0 2006.201.15:54:17.50#ibcon#read 6, iclass 4, count 0 2006.201.15:54:17.50#ibcon#end of sib2, iclass 4, count 0 2006.201.15:54:17.50#ibcon#*mode == 0, iclass 4, count 0 2006.201.15:54:17.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.15:54:17.50#ibcon#[27=USB\r\n] 2006.201.15:54:17.50#ibcon#*before write, iclass 4, count 0 2006.201.15:54:17.50#ibcon#enter sib2, iclass 4, count 0 2006.201.15:54:17.50#ibcon#flushed, iclass 4, count 0 2006.201.15:54:17.50#ibcon#about to write, iclass 4, count 0 2006.201.15:54:17.50#ibcon#wrote, iclass 4, count 0 2006.201.15:54:17.50#ibcon#about to read 3, iclass 4, count 0 2006.201.15:54:17.53#ibcon#read 3, iclass 4, count 0 2006.201.15:54:17.53#ibcon#about to read 4, iclass 4, count 0 2006.201.15:54:17.53#ibcon#read 4, iclass 4, count 0 2006.201.15:54:17.53#ibcon#about to read 5, iclass 4, count 0 2006.201.15:54:17.53#ibcon#read 5, iclass 4, count 0 2006.201.15:54:17.53#ibcon#about to read 6, iclass 4, count 0 2006.201.15:54:17.53#ibcon#read 6, iclass 4, count 0 2006.201.15:54:17.53#ibcon#end of sib2, iclass 4, count 0 2006.201.15:54:17.53#ibcon#*after write, iclass 4, count 0 2006.201.15:54:17.53#ibcon#*before return 0, iclass 4, count 0 2006.201.15:54:17.53#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:17.53#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.15:54:17.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.15:54:17.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.15:54:17.53$vck44/vblo=4,679.99 2006.201.15:54:17.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.15:54:17.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.15:54:17.53#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:17.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:17.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:17.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:17.53#ibcon#enter wrdev, iclass 6, count 0 2006.201.15:54:17.53#ibcon#first serial, iclass 6, count 0 2006.201.15:54:17.53#ibcon#enter sib2, iclass 6, count 0 2006.201.15:54:17.53#ibcon#flushed, iclass 6, count 0 2006.201.15:54:17.53#ibcon#about to write, iclass 6, count 0 2006.201.15:54:17.53#ibcon#wrote, iclass 6, count 0 2006.201.15:54:17.53#ibcon#about to read 3, iclass 6, count 0 2006.201.15:54:17.55#ibcon#read 3, iclass 6, count 0 2006.201.15:54:17.55#ibcon#about to read 4, iclass 6, count 0 2006.201.15:54:17.55#ibcon#read 4, iclass 6, count 0 2006.201.15:54:17.55#ibcon#about to read 5, iclass 6, count 0 2006.201.15:54:17.55#ibcon#read 5, iclass 6, count 0 2006.201.15:54:17.55#ibcon#about to read 6, iclass 6, count 0 2006.201.15:54:17.55#ibcon#read 6, iclass 6, count 0 2006.201.15:54:17.55#ibcon#end of sib2, iclass 6, count 0 2006.201.15:54:17.55#ibcon#*mode == 0, iclass 6, count 0 2006.201.15:54:17.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.15:54:17.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.15:54:17.55#ibcon#*before write, iclass 6, count 0 2006.201.15:54:17.55#ibcon#enter sib2, iclass 6, count 0 2006.201.15:54:17.55#ibcon#flushed, iclass 6, count 0 2006.201.15:54:17.55#ibcon#about to write, iclass 6, count 0 2006.201.15:54:17.55#ibcon#wrote, iclass 6, count 0 2006.201.15:54:17.55#ibcon#about to read 3, iclass 6, count 0 2006.201.15:54:17.59#ibcon#read 3, iclass 6, count 0 2006.201.15:54:17.59#ibcon#about to read 4, iclass 6, count 0 2006.201.15:54:17.59#ibcon#read 4, iclass 6, count 0 2006.201.15:54:17.59#ibcon#about to read 5, iclass 6, count 0 2006.201.15:54:17.59#ibcon#read 5, iclass 6, count 0 2006.201.15:54:17.59#ibcon#about to read 6, iclass 6, count 0 2006.201.15:54:17.59#ibcon#read 6, iclass 6, count 0 2006.201.15:54:17.59#ibcon#end of sib2, iclass 6, count 0 2006.201.15:54:17.59#ibcon#*after write, iclass 6, count 0 2006.201.15:54:17.59#ibcon#*before return 0, iclass 6, count 0 2006.201.15:54:17.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:17.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.15:54:17.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.15:54:17.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.15:54:17.59$vck44/vb=4,5 2006.201.15:54:17.59#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.15:54:17.59#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.15:54:17.59#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:17.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:17.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:17.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:17.65#ibcon#enter wrdev, iclass 10, count 2 2006.201.15:54:17.65#ibcon#first serial, iclass 10, count 2 2006.201.15:54:17.65#ibcon#enter sib2, iclass 10, count 2 2006.201.15:54:17.65#ibcon#flushed, iclass 10, count 2 2006.201.15:54:17.65#ibcon#about to write, iclass 10, count 2 2006.201.15:54:17.65#ibcon#wrote, iclass 10, count 2 2006.201.15:54:17.65#ibcon#about to read 3, iclass 10, count 2 2006.201.15:54:17.67#ibcon#read 3, iclass 10, count 2 2006.201.15:54:17.67#ibcon#about to read 4, iclass 10, count 2 2006.201.15:54:17.67#ibcon#read 4, iclass 10, count 2 2006.201.15:54:17.67#ibcon#about to read 5, iclass 10, count 2 2006.201.15:54:17.67#ibcon#read 5, iclass 10, count 2 2006.201.15:54:17.67#ibcon#about to read 6, iclass 10, count 2 2006.201.15:54:17.67#ibcon#read 6, iclass 10, count 2 2006.201.15:54:17.67#ibcon#end of sib2, iclass 10, count 2 2006.201.15:54:17.67#ibcon#*mode == 0, iclass 10, count 2 2006.201.15:54:17.67#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.15:54:17.67#ibcon#[27=AT04-05\r\n] 2006.201.15:54:17.67#ibcon#*before write, iclass 10, count 2 2006.201.15:54:17.67#ibcon#enter sib2, iclass 10, count 2 2006.201.15:54:17.67#ibcon#flushed, iclass 10, count 2 2006.201.15:54:17.67#ibcon#about to write, iclass 10, count 2 2006.201.15:54:17.67#ibcon#wrote, iclass 10, count 2 2006.201.15:54:17.67#ibcon#about to read 3, iclass 10, count 2 2006.201.15:54:17.70#ibcon#read 3, iclass 10, count 2 2006.201.15:54:17.70#ibcon#about to read 4, iclass 10, count 2 2006.201.15:54:17.70#ibcon#read 4, iclass 10, count 2 2006.201.15:54:17.70#ibcon#about to read 5, iclass 10, count 2 2006.201.15:54:17.70#ibcon#read 5, iclass 10, count 2 2006.201.15:54:17.70#ibcon#about to read 6, iclass 10, count 2 2006.201.15:54:17.70#ibcon#read 6, iclass 10, count 2 2006.201.15:54:17.70#ibcon#end of sib2, iclass 10, count 2 2006.201.15:54:17.70#ibcon#*after write, iclass 10, count 2 2006.201.15:54:17.70#ibcon#*before return 0, iclass 10, count 2 2006.201.15:54:17.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:17.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.15:54:17.70#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.15:54:17.70#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:17.70#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:17.82#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:17.82#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:17.82#ibcon#enter wrdev, iclass 10, count 0 2006.201.15:54:17.82#ibcon#first serial, iclass 10, count 0 2006.201.15:54:17.82#ibcon#enter sib2, iclass 10, count 0 2006.201.15:54:17.82#ibcon#flushed, iclass 10, count 0 2006.201.15:54:17.82#ibcon#about to write, iclass 10, count 0 2006.201.15:54:17.82#ibcon#wrote, iclass 10, count 0 2006.201.15:54:17.82#ibcon#about to read 3, iclass 10, count 0 2006.201.15:54:17.84#ibcon#read 3, iclass 10, count 0 2006.201.15:54:17.84#ibcon#about to read 4, iclass 10, count 0 2006.201.15:54:17.84#ibcon#read 4, iclass 10, count 0 2006.201.15:54:17.84#ibcon#about to read 5, iclass 10, count 0 2006.201.15:54:17.84#ibcon#read 5, iclass 10, count 0 2006.201.15:54:17.84#ibcon#about to read 6, iclass 10, count 0 2006.201.15:54:17.84#ibcon#read 6, iclass 10, count 0 2006.201.15:54:17.84#ibcon#end of sib2, iclass 10, count 0 2006.201.15:54:17.84#ibcon#*mode == 0, iclass 10, count 0 2006.201.15:54:17.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.15:54:17.84#ibcon#[27=USB\r\n] 2006.201.15:54:17.84#ibcon#*before write, iclass 10, count 0 2006.201.15:54:17.84#ibcon#enter sib2, iclass 10, count 0 2006.201.15:54:17.84#ibcon#flushed, iclass 10, count 0 2006.201.15:54:17.84#ibcon#about to write, iclass 10, count 0 2006.201.15:54:17.84#ibcon#wrote, iclass 10, count 0 2006.201.15:54:17.84#ibcon#about to read 3, iclass 10, count 0 2006.201.15:54:17.87#ibcon#read 3, iclass 10, count 0 2006.201.15:54:17.87#ibcon#about to read 4, iclass 10, count 0 2006.201.15:54:17.87#ibcon#read 4, iclass 10, count 0 2006.201.15:54:17.87#ibcon#about to read 5, iclass 10, count 0 2006.201.15:54:17.87#ibcon#read 5, iclass 10, count 0 2006.201.15:54:17.87#ibcon#about to read 6, iclass 10, count 0 2006.201.15:54:17.87#ibcon#read 6, iclass 10, count 0 2006.201.15:54:17.87#ibcon#end of sib2, iclass 10, count 0 2006.201.15:54:17.87#ibcon#*after write, iclass 10, count 0 2006.201.15:54:17.87#ibcon#*before return 0, iclass 10, count 0 2006.201.15:54:17.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:17.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.15:54:17.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.15:54:17.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.15:54:17.87$vck44/vblo=5,709.99 2006.201.15:54:17.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.15:54:17.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.15:54:17.87#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:17.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:17.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:17.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:17.87#ibcon#enter wrdev, iclass 12, count 0 2006.201.15:54:17.87#ibcon#first serial, iclass 12, count 0 2006.201.15:54:17.87#ibcon#enter sib2, iclass 12, count 0 2006.201.15:54:17.87#ibcon#flushed, iclass 12, count 0 2006.201.15:54:17.87#ibcon#about to write, iclass 12, count 0 2006.201.15:54:17.87#ibcon#wrote, iclass 12, count 0 2006.201.15:54:17.87#ibcon#about to read 3, iclass 12, count 0 2006.201.15:54:17.89#ibcon#read 3, iclass 12, count 0 2006.201.15:54:17.89#ibcon#about to read 4, iclass 12, count 0 2006.201.15:54:17.89#ibcon#read 4, iclass 12, count 0 2006.201.15:54:17.89#ibcon#about to read 5, iclass 12, count 0 2006.201.15:54:17.89#ibcon#read 5, iclass 12, count 0 2006.201.15:54:17.89#ibcon#about to read 6, iclass 12, count 0 2006.201.15:54:17.89#ibcon#read 6, iclass 12, count 0 2006.201.15:54:17.89#ibcon#end of sib2, iclass 12, count 0 2006.201.15:54:17.89#ibcon#*mode == 0, iclass 12, count 0 2006.201.15:54:17.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.15:54:17.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.15:54:17.89#ibcon#*before write, iclass 12, count 0 2006.201.15:54:17.89#ibcon#enter sib2, iclass 12, count 0 2006.201.15:54:17.89#ibcon#flushed, iclass 12, count 0 2006.201.15:54:17.89#ibcon#about to write, iclass 12, count 0 2006.201.15:54:17.89#ibcon#wrote, iclass 12, count 0 2006.201.15:54:17.89#ibcon#about to read 3, iclass 12, count 0 2006.201.15:54:17.94#ibcon#read 3, iclass 12, count 0 2006.201.15:54:17.94#ibcon#about to read 4, iclass 12, count 0 2006.201.15:54:17.94#ibcon#read 4, iclass 12, count 0 2006.201.15:54:17.94#ibcon#about to read 5, iclass 12, count 0 2006.201.15:54:17.94#ibcon#read 5, iclass 12, count 0 2006.201.15:54:17.94#ibcon#about to read 6, iclass 12, count 0 2006.201.15:54:17.94#ibcon#read 6, iclass 12, count 0 2006.201.15:54:17.94#ibcon#end of sib2, iclass 12, count 0 2006.201.15:54:17.94#ibcon#*after write, iclass 12, count 0 2006.201.15:54:17.94#ibcon#*before return 0, iclass 12, count 0 2006.201.15:54:17.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:17.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.15:54:17.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.15:54:17.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.15:54:17.94$vck44/vb=5,4 2006.201.15:54:17.94#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.15:54:17.94#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.15:54:17.94#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:17.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:17.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:17.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:17.99#ibcon#enter wrdev, iclass 14, count 2 2006.201.15:54:17.99#ibcon#first serial, iclass 14, count 2 2006.201.15:54:17.99#ibcon#enter sib2, iclass 14, count 2 2006.201.15:54:17.99#ibcon#flushed, iclass 14, count 2 2006.201.15:54:17.99#ibcon#about to write, iclass 14, count 2 2006.201.15:54:17.99#ibcon#wrote, iclass 14, count 2 2006.201.15:54:17.99#ibcon#about to read 3, iclass 14, count 2 2006.201.15:54:18.01#ibcon#read 3, iclass 14, count 2 2006.201.15:54:18.01#ibcon#about to read 4, iclass 14, count 2 2006.201.15:54:18.01#ibcon#read 4, iclass 14, count 2 2006.201.15:54:18.01#ibcon#about to read 5, iclass 14, count 2 2006.201.15:54:18.01#ibcon#read 5, iclass 14, count 2 2006.201.15:54:18.01#ibcon#about to read 6, iclass 14, count 2 2006.201.15:54:18.01#ibcon#read 6, iclass 14, count 2 2006.201.15:54:18.01#ibcon#end of sib2, iclass 14, count 2 2006.201.15:54:18.01#ibcon#*mode == 0, iclass 14, count 2 2006.201.15:54:18.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.15:54:18.01#ibcon#[27=AT05-04\r\n] 2006.201.15:54:18.01#ibcon#*before write, iclass 14, count 2 2006.201.15:54:18.01#ibcon#enter sib2, iclass 14, count 2 2006.201.15:54:18.01#ibcon#flushed, iclass 14, count 2 2006.201.15:54:18.01#ibcon#about to write, iclass 14, count 2 2006.201.15:54:18.01#ibcon#wrote, iclass 14, count 2 2006.201.15:54:18.01#ibcon#about to read 3, iclass 14, count 2 2006.201.15:54:18.04#ibcon#read 3, iclass 14, count 2 2006.201.15:54:18.04#ibcon#about to read 4, iclass 14, count 2 2006.201.15:54:18.04#ibcon#read 4, iclass 14, count 2 2006.201.15:54:18.04#ibcon#about to read 5, iclass 14, count 2 2006.201.15:54:18.04#ibcon#read 5, iclass 14, count 2 2006.201.15:54:18.04#ibcon#about to read 6, iclass 14, count 2 2006.201.15:54:18.04#ibcon#read 6, iclass 14, count 2 2006.201.15:54:18.04#ibcon#end of sib2, iclass 14, count 2 2006.201.15:54:18.04#ibcon#*after write, iclass 14, count 2 2006.201.15:54:18.04#ibcon#*before return 0, iclass 14, count 2 2006.201.15:54:18.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:18.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.15:54:18.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.15:54:18.04#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:18.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:18.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:18.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:18.16#ibcon#enter wrdev, iclass 14, count 0 2006.201.15:54:18.16#ibcon#first serial, iclass 14, count 0 2006.201.15:54:18.16#ibcon#enter sib2, iclass 14, count 0 2006.201.15:54:18.16#ibcon#flushed, iclass 14, count 0 2006.201.15:54:18.16#ibcon#about to write, iclass 14, count 0 2006.201.15:54:18.16#ibcon#wrote, iclass 14, count 0 2006.201.15:54:18.16#ibcon#about to read 3, iclass 14, count 0 2006.201.15:54:18.18#ibcon#read 3, iclass 14, count 0 2006.201.15:54:18.18#ibcon#about to read 4, iclass 14, count 0 2006.201.15:54:18.18#ibcon#read 4, iclass 14, count 0 2006.201.15:54:18.18#ibcon#about to read 5, iclass 14, count 0 2006.201.15:54:18.18#ibcon#read 5, iclass 14, count 0 2006.201.15:54:18.18#ibcon#about to read 6, iclass 14, count 0 2006.201.15:54:18.18#ibcon#read 6, iclass 14, count 0 2006.201.15:54:18.18#ibcon#end of sib2, iclass 14, count 0 2006.201.15:54:18.18#ibcon#*mode == 0, iclass 14, count 0 2006.201.15:54:18.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.15:54:18.18#ibcon#[27=USB\r\n] 2006.201.15:54:18.18#ibcon#*before write, iclass 14, count 0 2006.201.15:54:18.18#ibcon#enter sib2, iclass 14, count 0 2006.201.15:54:18.18#ibcon#flushed, iclass 14, count 0 2006.201.15:54:18.18#ibcon#about to write, iclass 14, count 0 2006.201.15:54:18.18#ibcon#wrote, iclass 14, count 0 2006.201.15:54:18.18#ibcon#about to read 3, iclass 14, count 0 2006.201.15:54:18.21#ibcon#read 3, iclass 14, count 0 2006.201.15:54:18.21#ibcon#about to read 4, iclass 14, count 0 2006.201.15:54:18.21#ibcon#read 4, iclass 14, count 0 2006.201.15:54:18.21#ibcon#about to read 5, iclass 14, count 0 2006.201.15:54:18.21#ibcon#read 5, iclass 14, count 0 2006.201.15:54:18.21#ibcon#about to read 6, iclass 14, count 0 2006.201.15:54:18.21#ibcon#read 6, iclass 14, count 0 2006.201.15:54:18.21#ibcon#end of sib2, iclass 14, count 0 2006.201.15:54:18.21#ibcon#*after write, iclass 14, count 0 2006.201.15:54:18.21#ibcon#*before return 0, iclass 14, count 0 2006.201.15:54:18.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:18.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.15:54:18.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.15:54:18.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.15:54:18.21$vck44/vblo=6,719.99 2006.201.15:54:18.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.15:54:18.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.15:54:18.21#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:18.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:18.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:18.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:18.21#ibcon#enter wrdev, iclass 16, count 0 2006.201.15:54:18.21#ibcon#first serial, iclass 16, count 0 2006.201.15:54:18.21#ibcon#enter sib2, iclass 16, count 0 2006.201.15:54:18.21#ibcon#flushed, iclass 16, count 0 2006.201.15:54:18.21#ibcon#about to write, iclass 16, count 0 2006.201.15:54:18.21#ibcon#wrote, iclass 16, count 0 2006.201.15:54:18.21#ibcon#about to read 3, iclass 16, count 0 2006.201.15:54:18.23#ibcon#read 3, iclass 16, count 0 2006.201.15:54:18.23#ibcon#about to read 4, iclass 16, count 0 2006.201.15:54:18.23#ibcon#read 4, iclass 16, count 0 2006.201.15:54:18.23#ibcon#about to read 5, iclass 16, count 0 2006.201.15:54:18.23#ibcon#read 5, iclass 16, count 0 2006.201.15:54:18.23#ibcon#about to read 6, iclass 16, count 0 2006.201.15:54:18.23#ibcon#read 6, iclass 16, count 0 2006.201.15:54:18.23#ibcon#end of sib2, iclass 16, count 0 2006.201.15:54:18.23#ibcon#*mode == 0, iclass 16, count 0 2006.201.15:54:18.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.15:54:18.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.15:54:18.23#ibcon#*before write, iclass 16, count 0 2006.201.15:54:18.23#ibcon#enter sib2, iclass 16, count 0 2006.201.15:54:18.23#ibcon#flushed, iclass 16, count 0 2006.201.15:54:18.23#ibcon#about to write, iclass 16, count 0 2006.201.15:54:18.23#ibcon#wrote, iclass 16, count 0 2006.201.15:54:18.23#ibcon#about to read 3, iclass 16, count 0 2006.201.15:54:18.27#ibcon#read 3, iclass 16, count 0 2006.201.15:54:18.27#ibcon#about to read 4, iclass 16, count 0 2006.201.15:54:18.27#ibcon#read 4, iclass 16, count 0 2006.201.15:54:18.27#ibcon#about to read 5, iclass 16, count 0 2006.201.15:54:18.27#ibcon#read 5, iclass 16, count 0 2006.201.15:54:18.27#ibcon#about to read 6, iclass 16, count 0 2006.201.15:54:18.27#ibcon#read 6, iclass 16, count 0 2006.201.15:54:18.27#ibcon#end of sib2, iclass 16, count 0 2006.201.15:54:18.27#ibcon#*after write, iclass 16, count 0 2006.201.15:54:18.27#ibcon#*before return 0, iclass 16, count 0 2006.201.15:54:18.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:18.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.15:54:18.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.15:54:18.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.15:54:18.27$vck44/vb=6,4 2006.201.15:54:18.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.15:54:18.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.15:54:18.27#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:18.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:18.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:18.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:18.33#ibcon#enter wrdev, iclass 18, count 2 2006.201.15:54:18.33#ibcon#first serial, iclass 18, count 2 2006.201.15:54:18.33#ibcon#enter sib2, iclass 18, count 2 2006.201.15:54:18.33#ibcon#flushed, iclass 18, count 2 2006.201.15:54:18.33#ibcon#about to write, iclass 18, count 2 2006.201.15:54:18.33#ibcon#wrote, iclass 18, count 2 2006.201.15:54:18.33#ibcon#about to read 3, iclass 18, count 2 2006.201.15:54:18.35#ibcon#read 3, iclass 18, count 2 2006.201.15:54:18.35#ibcon#about to read 4, iclass 18, count 2 2006.201.15:54:18.35#ibcon#read 4, iclass 18, count 2 2006.201.15:54:18.35#ibcon#about to read 5, iclass 18, count 2 2006.201.15:54:18.35#ibcon#read 5, iclass 18, count 2 2006.201.15:54:18.35#ibcon#about to read 6, iclass 18, count 2 2006.201.15:54:18.35#ibcon#read 6, iclass 18, count 2 2006.201.15:54:18.35#ibcon#end of sib2, iclass 18, count 2 2006.201.15:54:18.35#ibcon#*mode == 0, iclass 18, count 2 2006.201.15:54:18.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.15:54:18.35#ibcon#[27=AT06-04\r\n] 2006.201.15:54:18.35#ibcon#*before write, iclass 18, count 2 2006.201.15:54:18.35#ibcon#enter sib2, iclass 18, count 2 2006.201.15:54:18.35#ibcon#flushed, iclass 18, count 2 2006.201.15:54:18.35#ibcon#about to write, iclass 18, count 2 2006.201.15:54:18.35#ibcon#wrote, iclass 18, count 2 2006.201.15:54:18.35#ibcon#about to read 3, iclass 18, count 2 2006.201.15:54:18.38#ibcon#read 3, iclass 18, count 2 2006.201.15:54:18.38#ibcon#about to read 4, iclass 18, count 2 2006.201.15:54:18.38#ibcon#read 4, iclass 18, count 2 2006.201.15:54:18.38#ibcon#about to read 5, iclass 18, count 2 2006.201.15:54:18.38#ibcon#read 5, iclass 18, count 2 2006.201.15:54:18.38#ibcon#about to read 6, iclass 18, count 2 2006.201.15:54:18.38#ibcon#read 6, iclass 18, count 2 2006.201.15:54:18.38#ibcon#end of sib2, iclass 18, count 2 2006.201.15:54:18.38#ibcon#*after write, iclass 18, count 2 2006.201.15:54:18.38#ibcon#*before return 0, iclass 18, count 2 2006.201.15:54:18.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:18.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.15:54:18.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.15:54:18.38#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:18.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:18.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:18.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:18.50#ibcon#enter wrdev, iclass 18, count 0 2006.201.15:54:18.50#ibcon#first serial, iclass 18, count 0 2006.201.15:54:18.50#ibcon#enter sib2, iclass 18, count 0 2006.201.15:54:18.50#ibcon#flushed, iclass 18, count 0 2006.201.15:54:18.50#ibcon#about to write, iclass 18, count 0 2006.201.15:54:18.50#ibcon#wrote, iclass 18, count 0 2006.201.15:54:18.50#ibcon#about to read 3, iclass 18, count 0 2006.201.15:54:18.52#ibcon#read 3, iclass 18, count 0 2006.201.15:54:18.52#ibcon#about to read 4, iclass 18, count 0 2006.201.15:54:18.52#ibcon#read 4, iclass 18, count 0 2006.201.15:54:18.52#ibcon#about to read 5, iclass 18, count 0 2006.201.15:54:18.52#ibcon#read 5, iclass 18, count 0 2006.201.15:54:18.52#ibcon#about to read 6, iclass 18, count 0 2006.201.15:54:18.52#ibcon#read 6, iclass 18, count 0 2006.201.15:54:18.52#ibcon#end of sib2, iclass 18, count 0 2006.201.15:54:18.52#ibcon#*mode == 0, iclass 18, count 0 2006.201.15:54:18.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.15:54:18.52#ibcon#[27=USB\r\n] 2006.201.15:54:18.52#ibcon#*before write, iclass 18, count 0 2006.201.15:54:18.52#ibcon#enter sib2, iclass 18, count 0 2006.201.15:54:18.52#ibcon#flushed, iclass 18, count 0 2006.201.15:54:18.52#ibcon#about to write, iclass 18, count 0 2006.201.15:54:18.52#ibcon#wrote, iclass 18, count 0 2006.201.15:54:18.52#ibcon#about to read 3, iclass 18, count 0 2006.201.15:54:18.55#ibcon#read 3, iclass 18, count 0 2006.201.15:54:18.55#ibcon#about to read 4, iclass 18, count 0 2006.201.15:54:18.55#ibcon#read 4, iclass 18, count 0 2006.201.15:54:18.55#ibcon#about to read 5, iclass 18, count 0 2006.201.15:54:18.55#ibcon#read 5, iclass 18, count 0 2006.201.15:54:18.55#ibcon#about to read 6, iclass 18, count 0 2006.201.15:54:18.55#ibcon#read 6, iclass 18, count 0 2006.201.15:54:18.55#ibcon#end of sib2, iclass 18, count 0 2006.201.15:54:18.55#ibcon#*after write, iclass 18, count 0 2006.201.15:54:18.55#ibcon#*before return 0, iclass 18, count 0 2006.201.15:54:18.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:18.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.15:54:18.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.15:54:18.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.15:54:18.55$vck44/vblo=7,734.99 2006.201.15:54:18.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.15:54:18.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.15:54:18.55#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:18.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:18.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:18.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:18.55#ibcon#enter wrdev, iclass 20, count 0 2006.201.15:54:18.55#ibcon#first serial, iclass 20, count 0 2006.201.15:54:18.55#ibcon#enter sib2, iclass 20, count 0 2006.201.15:54:18.55#ibcon#flushed, iclass 20, count 0 2006.201.15:54:18.55#ibcon#about to write, iclass 20, count 0 2006.201.15:54:18.55#ibcon#wrote, iclass 20, count 0 2006.201.15:54:18.55#ibcon#about to read 3, iclass 20, count 0 2006.201.15:54:18.57#ibcon#read 3, iclass 20, count 0 2006.201.15:54:18.57#ibcon#about to read 4, iclass 20, count 0 2006.201.15:54:18.57#ibcon#read 4, iclass 20, count 0 2006.201.15:54:18.57#ibcon#about to read 5, iclass 20, count 0 2006.201.15:54:18.57#ibcon#read 5, iclass 20, count 0 2006.201.15:54:18.57#ibcon#about to read 6, iclass 20, count 0 2006.201.15:54:18.57#ibcon#read 6, iclass 20, count 0 2006.201.15:54:18.57#ibcon#end of sib2, iclass 20, count 0 2006.201.15:54:18.57#ibcon#*mode == 0, iclass 20, count 0 2006.201.15:54:18.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.15:54:18.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.15:54:18.57#ibcon#*before write, iclass 20, count 0 2006.201.15:54:18.57#ibcon#enter sib2, iclass 20, count 0 2006.201.15:54:18.57#ibcon#flushed, iclass 20, count 0 2006.201.15:54:18.57#ibcon#about to write, iclass 20, count 0 2006.201.15:54:18.57#ibcon#wrote, iclass 20, count 0 2006.201.15:54:18.57#ibcon#about to read 3, iclass 20, count 0 2006.201.15:54:18.61#ibcon#read 3, iclass 20, count 0 2006.201.15:54:18.61#ibcon#about to read 4, iclass 20, count 0 2006.201.15:54:18.61#ibcon#read 4, iclass 20, count 0 2006.201.15:54:18.61#ibcon#about to read 5, iclass 20, count 0 2006.201.15:54:18.61#ibcon#read 5, iclass 20, count 0 2006.201.15:54:18.61#ibcon#about to read 6, iclass 20, count 0 2006.201.15:54:18.61#ibcon#read 6, iclass 20, count 0 2006.201.15:54:18.61#ibcon#end of sib2, iclass 20, count 0 2006.201.15:54:18.61#ibcon#*after write, iclass 20, count 0 2006.201.15:54:18.61#ibcon#*before return 0, iclass 20, count 0 2006.201.15:54:18.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:18.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.15:54:18.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.15:54:18.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.15:54:18.61$vck44/vb=7,4 2006.201.15:54:18.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.15:54:18.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.15:54:18.61#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:18.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:18.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:18.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:18.67#ibcon#enter wrdev, iclass 22, count 2 2006.201.15:54:18.67#ibcon#first serial, iclass 22, count 2 2006.201.15:54:18.67#ibcon#enter sib2, iclass 22, count 2 2006.201.15:54:18.67#ibcon#flushed, iclass 22, count 2 2006.201.15:54:18.67#ibcon#about to write, iclass 22, count 2 2006.201.15:54:18.67#ibcon#wrote, iclass 22, count 2 2006.201.15:54:18.67#ibcon#about to read 3, iclass 22, count 2 2006.201.15:54:18.69#ibcon#read 3, iclass 22, count 2 2006.201.15:54:18.69#ibcon#about to read 4, iclass 22, count 2 2006.201.15:54:18.69#ibcon#read 4, iclass 22, count 2 2006.201.15:54:18.69#ibcon#about to read 5, iclass 22, count 2 2006.201.15:54:18.69#ibcon#read 5, iclass 22, count 2 2006.201.15:54:18.69#ibcon#about to read 6, iclass 22, count 2 2006.201.15:54:18.69#ibcon#read 6, iclass 22, count 2 2006.201.15:54:18.69#ibcon#end of sib2, iclass 22, count 2 2006.201.15:54:18.69#ibcon#*mode == 0, iclass 22, count 2 2006.201.15:54:18.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.15:54:18.69#ibcon#[27=AT07-04\r\n] 2006.201.15:54:18.69#ibcon#*before write, iclass 22, count 2 2006.201.15:54:18.69#ibcon#enter sib2, iclass 22, count 2 2006.201.15:54:18.69#ibcon#flushed, iclass 22, count 2 2006.201.15:54:18.69#ibcon#about to write, iclass 22, count 2 2006.201.15:54:18.69#ibcon#wrote, iclass 22, count 2 2006.201.15:54:18.69#ibcon#about to read 3, iclass 22, count 2 2006.201.15:54:18.72#ibcon#read 3, iclass 22, count 2 2006.201.15:54:18.72#ibcon#about to read 4, iclass 22, count 2 2006.201.15:54:18.72#ibcon#read 4, iclass 22, count 2 2006.201.15:54:18.72#ibcon#about to read 5, iclass 22, count 2 2006.201.15:54:18.72#ibcon#read 5, iclass 22, count 2 2006.201.15:54:18.72#ibcon#about to read 6, iclass 22, count 2 2006.201.15:54:18.72#ibcon#read 6, iclass 22, count 2 2006.201.15:54:18.72#ibcon#end of sib2, iclass 22, count 2 2006.201.15:54:18.72#ibcon#*after write, iclass 22, count 2 2006.201.15:54:18.72#ibcon#*before return 0, iclass 22, count 2 2006.201.15:54:18.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:18.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.15:54:18.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.15:54:18.72#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:18.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:18.84#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:18.84#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:18.84#ibcon#enter wrdev, iclass 22, count 0 2006.201.15:54:18.84#ibcon#first serial, iclass 22, count 0 2006.201.15:54:18.84#ibcon#enter sib2, iclass 22, count 0 2006.201.15:54:18.84#ibcon#flushed, iclass 22, count 0 2006.201.15:54:18.84#ibcon#about to write, iclass 22, count 0 2006.201.15:54:18.84#ibcon#wrote, iclass 22, count 0 2006.201.15:54:18.84#ibcon#about to read 3, iclass 22, count 0 2006.201.15:54:18.86#ibcon#read 3, iclass 22, count 0 2006.201.15:54:18.86#ibcon#about to read 4, iclass 22, count 0 2006.201.15:54:18.86#ibcon#read 4, iclass 22, count 0 2006.201.15:54:18.86#ibcon#about to read 5, iclass 22, count 0 2006.201.15:54:18.86#ibcon#read 5, iclass 22, count 0 2006.201.15:54:18.86#ibcon#about to read 6, iclass 22, count 0 2006.201.15:54:18.86#ibcon#read 6, iclass 22, count 0 2006.201.15:54:18.86#ibcon#end of sib2, iclass 22, count 0 2006.201.15:54:18.86#ibcon#*mode == 0, iclass 22, count 0 2006.201.15:54:18.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.15:54:18.86#ibcon#[27=USB\r\n] 2006.201.15:54:18.86#ibcon#*before write, iclass 22, count 0 2006.201.15:54:18.86#ibcon#enter sib2, iclass 22, count 0 2006.201.15:54:18.86#ibcon#flushed, iclass 22, count 0 2006.201.15:54:18.86#ibcon#about to write, iclass 22, count 0 2006.201.15:54:18.86#ibcon#wrote, iclass 22, count 0 2006.201.15:54:18.86#ibcon#about to read 3, iclass 22, count 0 2006.201.15:54:18.89#ibcon#read 3, iclass 22, count 0 2006.201.15:54:18.89#ibcon#about to read 4, iclass 22, count 0 2006.201.15:54:18.89#ibcon#read 4, iclass 22, count 0 2006.201.15:54:18.89#ibcon#about to read 5, iclass 22, count 0 2006.201.15:54:18.89#ibcon#read 5, iclass 22, count 0 2006.201.15:54:18.89#ibcon#about to read 6, iclass 22, count 0 2006.201.15:54:18.89#ibcon#read 6, iclass 22, count 0 2006.201.15:54:18.89#ibcon#end of sib2, iclass 22, count 0 2006.201.15:54:18.89#ibcon#*after write, iclass 22, count 0 2006.201.15:54:18.89#ibcon#*before return 0, iclass 22, count 0 2006.201.15:54:18.89#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:18.89#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.15:54:18.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.15:54:18.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.15:54:18.89$vck44/vblo=8,744.99 2006.201.15:54:18.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.15:54:18.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.15:54:18.89#ibcon#ireg 17 cls_cnt 0 2006.201.15:54:18.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:18.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:18.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:18.89#ibcon#enter wrdev, iclass 24, count 0 2006.201.15:54:18.89#ibcon#first serial, iclass 24, count 0 2006.201.15:54:18.89#ibcon#enter sib2, iclass 24, count 0 2006.201.15:54:18.89#ibcon#flushed, iclass 24, count 0 2006.201.15:54:18.89#ibcon#about to write, iclass 24, count 0 2006.201.15:54:18.89#ibcon#wrote, iclass 24, count 0 2006.201.15:54:18.89#ibcon#about to read 3, iclass 24, count 0 2006.201.15:54:18.91#ibcon#read 3, iclass 24, count 0 2006.201.15:54:18.91#ibcon#about to read 4, iclass 24, count 0 2006.201.15:54:18.91#ibcon#read 4, iclass 24, count 0 2006.201.15:54:18.91#ibcon#about to read 5, iclass 24, count 0 2006.201.15:54:18.91#ibcon#read 5, iclass 24, count 0 2006.201.15:54:18.91#ibcon#about to read 6, iclass 24, count 0 2006.201.15:54:18.91#ibcon#read 6, iclass 24, count 0 2006.201.15:54:18.91#ibcon#end of sib2, iclass 24, count 0 2006.201.15:54:18.91#ibcon#*mode == 0, iclass 24, count 0 2006.201.15:54:18.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.15:54:18.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.15:54:18.91#ibcon#*before write, iclass 24, count 0 2006.201.15:54:18.91#ibcon#enter sib2, iclass 24, count 0 2006.201.15:54:18.91#ibcon#flushed, iclass 24, count 0 2006.201.15:54:18.91#ibcon#about to write, iclass 24, count 0 2006.201.15:54:18.91#ibcon#wrote, iclass 24, count 0 2006.201.15:54:18.91#ibcon#about to read 3, iclass 24, count 0 2006.201.15:54:18.95#ibcon#read 3, iclass 24, count 0 2006.201.15:54:18.95#ibcon#about to read 4, iclass 24, count 0 2006.201.15:54:18.95#ibcon#read 4, iclass 24, count 0 2006.201.15:54:18.95#ibcon#about to read 5, iclass 24, count 0 2006.201.15:54:18.95#ibcon#read 5, iclass 24, count 0 2006.201.15:54:18.95#ibcon#about to read 6, iclass 24, count 0 2006.201.15:54:18.95#ibcon#read 6, iclass 24, count 0 2006.201.15:54:18.95#ibcon#end of sib2, iclass 24, count 0 2006.201.15:54:18.95#ibcon#*after write, iclass 24, count 0 2006.201.15:54:18.95#ibcon#*before return 0, iclass 24, count 0 2006.201.15:54:18.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:18.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.15:54:18.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.15:54:18.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.15:54:18.95$vck44/vb=8,4 2006.201.15:54:18.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.15:54:18.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.15:54:18.95#ibcon#ireg 11 cls_cnt 2 2006.201.15:54:18.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:19.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:19.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:19.01#ibcon#enter wrdev, iclass 26, count 2 2006.201.15:54:19.01#ibcon#first serial, iclass 26, count 2 2006.201.15:54:19.01#ibcon#enter sib2, iclass 26, count 2 2006.201.15:54:19.01#ibcon#flushed, iclass 26, count 2 2006.201.15:54:19.01#ibcon#about to write, iclass 26, count 2 2006.201.15:54:19.01#ibcon#wrote, iclass 26, count 2 2006.201.15:54:19.01#ibcon#about to read 3, iclass 26, count 2 2006.201.15:54:19.03#ibcon#read 3, iclass 26, count 2 2006.201.15:54:19.03#ibcon#about to read 4, iclass 26, count 2 2006.201.15:54:19.03#ibcon#read 4, iclass 26, count 2 2006.201.15:54:19.03#ibcon#about to read 5, iclass 26, count 2 2006.201.15:54:19.03#ibcon#read 5, iclass 26, count 2 2006.201.15:54:19.03#ibcon#about to read 6, iclass 26, count 2 2006.201.15:54:19.03#ibcon#read 6, iclass 26, count 2 2006.201.15:54:19.03#ibcon#end of sib2, iclass 26, count 2 2006.201.15:54:19.03#ibcon#*mode == 0, iclass 26, count 2 2006.201.15:54:19.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.15:54:19.03#ibcon#[27=AT08-04\r\n] 2006.201.15:54:19.03#ibcon#*before write, iclass 26, count 2 2006.201.15:54:19.03#ibcon#enter sib2, iclass 26, count 2 2006.201.15:54:19.03#ibcon#flushed, iclass 26, count 2 2006.201.15:54:19.03#ibcon#about to write, iclass 26, count 2 2006.201.15:54:19.03#ibcon#wrote, iclass 26, count 2 2006.201.15:54:19.03#ibcon#about to read 3, iclass 26, count 2 2006.201.15:54:19.06#ibcon#read 3, iclass 26, count 2 2006.201.15:54:19.06#ibcon#about to read 4, iclass 26, count 2 2006.201.15:54:19.06#ibcon#read 4, iclass 26, count 2 2006.201.15:54:19.06#ibcon#about to read 5, iclass 26, count 2 2006.201.15:54:19.06#ibcon#read 5, iclass 26, count 2 2006.201.15:54:19.06#ibcon#about to read 6, iclass 26, count 2 2006.201.15:54:19.06#ibcon#read 6, iclass 26, count 2 2006.201.15:54:19.06#ibcon#end of sib2, iclass 26, count 2 2006.201.15:54:19.06#ibcon#*after write, iclass 26, count 2 2006.201.15:54:19.06#ibcon#*before return 0, iclass 26, count 2 2006.201.15:54:19.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:19.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.15:54:19.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.15:54:19.06#ibcon#ireg 7 cls_cnt 0 2006.201.15:54:19.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:19.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:19.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:19.18#ibcon#enter wrdev, iclass 26, count 0 2006.201.15:54:19.18#ibcon#first serial, iclass 26, count 0 2006.201.15:54:19.18#ibcon#enter sib2, iclass 26, count 0 2006.201.15:54:19.18#ibcon#flushed, iclass 26, count 0 2006.201.15:54:19.18#ibcon#about to write, iclass 26, count 0 2006.201.15:54:19.18#ibcon#wrote, iclass 26, count 0 2006.201.15:54:19.18#ibcon#about to read 3, iclass 26, count 0 2006.201.15:54:19.20#ibcon#read 3, iclass 26, count 0 2006.201.15:54:19.20#ibcon#about to read 4, iclass 26, count 0 2006.201.15:54:19.20#ibcon#read 4, iclass 26, count 0 2006.201.15:54:19.20#ibcon#about to read 5, iclass 26, count 0 2006.201.15:54:19.20#ibcon#read 5, iclass 26, count 0 2006.201.15:54:19.20#ibcon#about to read 6, iclass 26, count 0 2006.201.15:54:19.20#ibcon#read 6, iclass 26, count 0 2006.201.15:54:19.20#ibcon#end of sib2, iclass 26, count 0 2006.201.15:54:19.20#ibcon#*mode == 0, iclass 26, count 0 2006.201.15:54:19.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.15:54:19.20#ibcon#[27=USB\r\n] 2006.201.15:54:19.20#ibcon#*before write, iclass 26, count 0 2006.201.15:54:19.20#ibcon#enter sib2, iclass 26, count 0 2006.201.15:54:19.20#ibcon#flushed, iclass 26, count 0 2006.201.15:54:19.20#ibcon#about to write, iclass 26, count 0 2006.201.15:54:19.20#ibcon#wrote, iclass 26, count 0 2006.201.15:54:19.20#ibcon#about to read 3, iclass 26, count 0 2006.201.15:54:19.23#ibcon#read 3, iclass 26, count 0 2006.201.15:54:19.23#ibcon#about to read 4, iclass 26, count 0 2006.201.15:54:19.23#ibcon#read 4, iclass 26, count 0 2006.201.15:54:19.23#ibcon#about to read 5, iclass 26, count 0 2006.201.15:54:19.23#ibcon#read 5, iclass 26, count 0 2006.201.15:54:19.23#ibcon#about to read 6, iclass 26, count 0 2006.201.15:54:19.23#ibcon#read 6, iclass 26, count 0 2006.201.15:54:19.23#ibcon#end of sib2, iclass 26, count 0 2006.201.15:54:19.23#ibcon#*after write, iclass 26, count 0 2006.201.15:54:19.23#ibcon#*before return 0, iclass 26, count 0 2006.201.15:54:19.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:19.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.15:54:19.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.15:54:19.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.15:54:19.23$vck44/vabw=wide 2006.201.15:54:19.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.15:54:19.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.15:54:19.23#ibcon#ireg 8 cls_cnt 0 2006.201.15:54:19.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:19.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:19.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:19.23#ibcon#enter wrdev, iclass 28, count 0 2006.201.15:54:19.23#ibcon#first serial, iclass 28, count 0 2006.201.15:54:19.23#ibcon#enter sib2, iclass 28, count 0 2006.201.15:54:19.23#ibcon#flushed, iclass 28, count 0 2006.201.15:54:19.23#ibcon#about to write, iclass 28, count 0 2006.201.15:54:19.23#ibcon#wrote, iclass 28, count 0 2006.201.15:54:19.23#ibcon#about to read 3, iclass 28, count 0 2006.201.15:54:19.25#ibcon#read 3, iclass 28, count 0 2006.201.15:54:19.25#ibcon#about to read 4, iclass 28, count 0 2006.201.15:54:19.25#ibcon#read 4, iclass 28, count 0 2006.201.15:54:19.25#ibcon#about to read 5, iclass 28, count 0 2006.201.15:54:19.25#ibcon#read 5, iclass 28, count 0 2006.201.15:54:19.25#ibcon#about to read 6, iclass 28, count 0 2006.201.15:54:19.25#ibcon#read 6, iclass 28, count 0 2006.201.15:54:19.25#ibcon#end of sib2, iclass 28, count 0 2006.201.15:54:19.25#ibcon#*mode == 0, iclass 28, count 0 2006.201.15:54:19.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.15:54:19.25#ibcon#[25=BW32\r\n] 2006.201.15:54:19.25#ibcon#*before write, iclass 28, count 0 2006.201.15:54:19.25#ibcon#enter sib2, iclass 28, count 0 2006.201.15:54:19.25#ibcon#flushed, iclass 28, count 0 2006.201.15:54:19.25#ibcon#about to write, iclass 28, count 0 2006.201.15:54:19.25#ibcon#wrote, iclass 28, count 0 2006.201.15:54:19.25#ibcon#about to read 3, iclass 28, count 0 2006.201.15:54:19.28#ibcon#read 3, iclass 28, count 0 2006.201.15:54:19.28#ibcon#about to read 4, iclass 28, count 0 2006.201.15:54:19.28#ibcon#read 4, iclass 28, count 0 2006.201.15:54:19.28#ibcon#about to read 5, iclass 28, count 0 2006.201.15:54:19.28#ibcon#read 5, iclass 28, count 0 2006.201.15:54:19.28#ibcon#about to read 6, iclass 28, count 0 2006.201.15:54:19.28#ibcon#read 6, iclass 28, count 0 2006.201.15:54:19.28#ibcon#end of sib2, iclass 28, count 0 2006.201.15:54:19.28#ibcon#*after write, iclass 28, count 0 2006.201.15:54:19.28#ibcon#*before return 0, iclass 28, count 0 2006.201.15:54:19.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:19.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.15:54:19.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.15:54:19.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.15:54:19.28$vck44/vbbw=wide 2006.201.15:54:19.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.15:54:19.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.15:54:19.28#ibcon#ireg 8 cls_cnt 0 2006.201.15:54:19.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:54:19.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:54:19.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:54:19.35#ibcon#enter wrdev, iclass 30, count 0 2006.201.15:54:19.35#ibcon#first serial, iclass 30, count 0 2006.201.15:54:19.35#ibcon#enter sib2, iclass 30, count 0 2006.201.15:54:19.35#ibcon#flushed, iclass 30, count 0 2006.201.15:54:19.35#ibcon#about to write, iclass 30, count 0 2006.201.15:54:19.35#ibcon#wrote, iclass 30, count 0 2006.201.15:54:19.35#ibcon#about to read 3, iclass 30, count 0 2006.201.15:54:19.37#ibcon#read 3, iclass 30, count 0 2006.201.15:54:19.37#ibcon#about to read 4, iclass 30, count 0 2006.201.15:54:19.37#ibcon#read 4, iclass 30, count 0 2006.201.15:54:19.37#ibcon#about to read 5, iclass 30, count 0 2006.201.15:54:19.37#ibcon#read 5, iclass 30, count 0 2006.201.15:54:19.37#ibcon#about to read 6, iclass 30, count 0 2006.201.15:54:19.37#ibcon#read 6, iclass 30, count 0 2006.201.15:54:19.37#ibcon#end of sib2, iclass 30, count 0 2006.201.15:54:19.37#ibcon#*mode == 0, iclass 30, count 0 2006.201.15:54:19.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.15:54:19.37#ibcon#[27=BW32\r\n] 2006.201.15:54:19.37#ibcon#*before write, iclass 30, count 0 2006.201.15:54:19.37#ibcon#enter sib2, iclass 30, count 0 2006.201.15:54:19.37#ibcon#flushed, iclass 30, count 0 2006.201.15:54:19.37#ibcon#about to write, iclass 30, count 0 2006.201.15:54:19.37#ibcon#wrote, iclass 30, count 0 2006.201.15:54:19.37#ibcon#about to read 3, iclass 30, count 0 2006.201.15:54:19.41#ibcon#read 3, iclass 30, count 0 2006.201.15:54:19.41#ibcon#about to read 4, iclass 30, count 0 2006.201.15:54:19.41#ibcon#read 4, iclass 30, count 0 2006.201.15:54:19.41#ibcon#about to read 5, iclass 30, count 0 2006.201.15:54:19.41#ibcon#read 5, iclass 30, count 0 2006.201.15:54:19.41#ibcon#about to read 6, iclass 30, count 0 2006.201.15:54:19.41#ibcon#read 6, iclass 30, count 0 2006.201.15:54:19.41#ibcon#end of sib2, iclass 30, count 0 2006.201.15:54:19.41#ibcon#*after write, iclass 30, count 0 2006.201.15:54:19.41#ibcon#*before return 0, iclass 30, count 0 2006.201.15:54:19.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:54:19.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.15:54:19.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.15:54:19.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.15:54:19.41$setupk4/ifdk4 2006.201.15:54:19.41$ifdk4/lo= 2006.201.15:54:19.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.15:54:19.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.15:54:19.41$ifdk4/patch= 2006.201.15:54:19.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.15:54:19.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.15:54:19.41$setupk4/!*+20s 2006.201.15:54:20.63#abcon#<5=/04 0.9 1.5 20.841001002.8\r\n> 2006.201.15:54:20.65#abcon#{5=INTERFACE CLEAR} 2006.201.15:54:20.71#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:54:22.13#trakl#Source acquired 2006.201.15:54:24.13#flagr#flagr/antenna,acquired 2006.201.15:54:30.80#abcon#<5=/04 0.8 1.5 20.841001002.8\r\n> 2006.201.15:54:30.82#abcon#{5=INTERFACE CLEAR} 2006.201.15:54:30.88#abcon#[5=S1D000X0/0*\r\n] 2006.201.15:54:33.87$setupk4/"tpicd 2006.201.15:54:33.87$setupk4/echo=off 2006.201.15:54:33.87$setupk4/xlog=off 2006.201.15:54:33.87:!2006.201.15:55:20 2006.201.15:55:20.00:preob 2006.201.15:55:20.13/onsource/TRACKING 2006.201.15:55:20.13:!2006.201.15:55:30 2006.201.15:55:30.00:"tape 2006.201.15:55:30.00:"st=record 2006.201.15:55:30.00:data_valid=on 2006.201.15:55:30.00:midob 2006.201.15:55:30.13/onsource/TRACKING 2006.201.15:55:30.13/wx/20.85,1002.8,100 2006.201.15:55:30.29/cable/+6.4772E-03 2006.201.15:55:31.38/va/01,08,usb,yes,29,31 2006.201.15:55:31.38/va/02,07,usb,yes,31,32 2006.201.15:55:31.38/va/03,08,usb,yes,28,29 2006.201.15:55:31.38/va/04,07,usb,yes,32,34 2006.201.15:55:31.38/va/05,04,usb,yes,28,29 2006.201.15:55:31.38/va/06,05,usb,yes,28,28 2006.201.15:55:31.38/va/07,05,usb,yes,28,29 2006.201.15:55:31.38/va/08,04,usb,yes,27,33 2006.201.15:55:31.61/valo/01,524.99,yes,locked 2006.201.15:55:31.61/valo/02,534.99,yes,locked 2006.201.15:55:31.61/valo/03,564.99,yes,locked 2006.201.15:55:31.61/valo/04,624.99,yes,locked 2006.201.15:55:31.61/valo/05,734.99,yes,locked 2006.201.15:55:31.61/valo/06,814.99,yes,locked 2006.201.15:55:31.61/valo/07,864.99,yes,locked 2006.201.15:55:31.61/valo/08,884.99,yes,locked 2006.201.15:55:32.70/vb/01,04,usb,yes,28,26 2006.201.15:55:32.70/vb/02,05,usb,yes,27,27 2006.201.15:55:32.70/vb/03,04,usb,yes,28,31 2006.201.15:55:32.70/vb/04,05,usb,yes,28,27 2006.201.15:55:32.70/vb/05,04,usb,yes,25,27 2006.201.15:55:32.70/vb/06,04,usb,yes,29,25 2006.201.15:55:32.70/vb/07,04,usb,yes,29,28 2006.201.15:55:32.70/vb/08,04,usb,yes,26,30 2006.201.15:55:32.93/vblo/01,629.99,yes,locked 2006.201.15:55:32.93/vblo/02,634.99,yes,locked 2006.201.15:55:32.93/vblo/03,649.99,yes,locked 2006.201.15:55:32.93/vblo/04,679.99,yes,locked 2006.201.15:55:32.93/vblo/05,709.99,yes,locked 2006.201.15:55:32.93/vblo/06,719.99,yes,locked 2006.201.15:55:32.93/vblo/07,734.99,yes,locked 2006.201.15:55:32.93/vblo/08,744.99,yes,locked 2006.201.15:55:33.08/vabw/8 2006.201.15:55:33.24/vbbw/8 2006.201.15:55:33.42/xfe/off,on,15.2 2006.201.15:55:33.81/ifatt/23,28,28,28 2006.201.15:55:34.06/fmout-gps/S +4.52E-07 2006.201.15:55:34.11:!2006.201.16:08:00 2006.201.16:08:00.00:data_valid=off 2006.201.16:08:00.00:"et 2006.201.16:08:00.00:!+3s 2006.201.16:08:03.02:"tape 2006.201.16:08:03.02:postob 2006.201.16:08:03.16/cable/+6.4785E-03 2006.201.16:08:03.16/wx/20.84,1003.0,100 2006.201.16:08:03.22/fmout-gps/S +4.54E-07 2006.201.16:08:03.22:scan_name=201-1610,jd0607,120 2006.201.16:08:03.22:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.16:08:04.14#flagr#flagr/antenna,new-source 2006.201.16:08:04.14:checkk5 2006.201.16:08:04.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:08:04.93/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:08:05.32/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:08:05.72/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:08:06.40/chk_obsdata//k5ts1/T2011555??a.dat file size is correct (nominal:3000MB, actual:2996MB). 2006.201.16:08:07.08/chk_obsdata//k5ts2/T2011555??b.dat file size is correct (nominal:3000MB, actual:2996MB). 2006.201.16:08:07.75/chk_obsdata//k5ts3/T2011555??c.dat file size is correct (nominal:3000MB, actual:2996MB). 2006.201.16:08:08.43/chk_obsdata//k5ts4/T2011555??d.dat file size is correct (nominal:3000MB, actual:2996MB). 2006.201.16:08:09.11/k5log//k5ts1_log_newline 2006.201.16:08:09.80/k5log//k5ts2_log_newline 2006.201.16:08:10.50/k5log//k5ts3_log_newline 2006.201.16:08:11.21/k5log//k5ts4_log_newline 2006.201.16:08:11.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:08:11.23:setupk4=1 2006.201.16:08:11.23$setupk4/echo=on 2006.201.16:08:11.23$setupk4/pcalon 2006.201.16:08:11.23$pcalon/"no phase cal control is implemented here 2006.201.16:08:11.24$setupk4/"tpicd=stop 2006.201.16:08:11.24$setupk4/"rec=synch_on 2006.201.16:08:11.24$setupk4/"rec_mode=128 2006.201.16:08:11.24$setupk4/!* 2006.201.16:08:11.24$setupk4/recpk4 2006.201.16:08:11.24$recpk4/recpatch= 2006.201.16:08:11.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:08:11.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:08:11.24$setupk4/vck44 2006.201.16:08:11.24$vck44/valo=1,524.99 2006.201.16:08:11.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.16:08:11.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.16:08:11.24#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:11.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:11.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:11.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:11.24#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:08:11.24#ibcon#first serial, iclass 34, count 0 2006.201.16:08:11.24#ibcon#enter sib2, iclass 34, count 0 2006.201.16:08:11.24#ibcon#flushed, iclass 34, count 0 2006.201.16:08:11.24#ibcon#about to write, iclass 34, count 0 2006.201.16:08:11.24#ibcon#wrote, iclass 34, count 0 2006.201.16:08:11.24#ibcon#about to read 3, iclass 34, count 0 2006.201.16:08:11.28#ibcon#read 3, iclass 34, count 0 2006.201.16:08:11.28#ibcon#about to read 4, iclass 34, count 0 2006.201.16:08:11.28#ibcon#read 4, iclass 34, count 0 2006.201.16:08:11.28#ibcon#about to read 5, iclass 34, count 0 2006.201.16:08:11.28#ibcon#read 5, iclass 34, count 0 2006.201.16:08:11.28#ibcon#about to read 6, iclass 34, count 0 2006.201.16:08:11.28#ibcon#read 6, iclass 34, count 0 2006.201.16:08:11.28#ibcon#end of sib2, iclass 34, count 0 2006.201.16:08:11.28#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:08:11.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:08:11.28#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:08:11.28#ibcon#*before write, iclass 34, count 0 2006.201.16:08:11.28#ibcon#enter sib2, iclass 34, count 0 2006.201.16:08:11.28#ibcon#flushed, iclass 34, count 0 2006.201.16:08:11.28#ibcon#about to write, iclass 34, count 0 2006.201.16:08:11.28#ibcon#wrote, iclass 34, count 0 2006.201.16:08:11.28#ibcon#about to read 3, iclass 34, count 0 2006.201.16:08:11.33#ibcon#read 3, iclass 34, count 0 2006.201.16:08:11.33#ibcon#about to read 4, iclass 34, count 0 2006.201.16:08:11.33#ibcon#read 4, iclass 34, count 0 2006.201.16:08:11.33#ibcon#about to read 5, iclass 34, count 0 2006.201.16:08:11.33#ibcon#read 5, iclass 34, count 0 2006.201.16:08:11.33#ibcon#about to read 6, iclass 34, count 0 2006.201.16:08:11.33#ibcon#read 6, iclass 34, count 0 2006.201.16:08:11.33#ibcon#end of sib2, iclass 34, count 0 2006.201.16:08:11.33#ibcon#*after write, iclass 34, count 0 2006.201.16:08:11.33#ibcon#*before return 0, iclass 34, count 0 2006.201.16:08:11.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:11.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:11.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:08:11.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:08:11.33$vck44/va=1,8 2006.201.16:08:11.33#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.16:08:11.33#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.16:08:11.33#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:11.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:11.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:11.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:11.33#ibcon#enter wrdev, iclass 36, count 2 2006.201.16:08:11.33#ibcon#first serial, iclass 36, count 2 2006.201.16:08:11.33#ibcon#enter sib2, iclass 36, count 2 2006.201.16:08:11.33#ibcon#flushed, iclass 36, count 2 2006.201.16:08:11.33#ibcon#about to write, iclass 36, count 2 2006.201.16:08:11.33#ibcon#wrote, iclass 36, count 2 2006.201.16:08:11.33#ibcon#about to read 3, iclass 36, count 2 2006.201.16:08:11.35#ibcon#read 3, iclass 36, count 2 2006.201.16:08:11.35#ibcon#about to read 4, iclass 36, count 2 2006.201.16:08:11.35#ibcon#read 4, iclass 36, count 2 2006.201.16:08:11.35#ibcon#about to read 5, iclass 36, count 2 2006.201.16:08:11.35#ibcon#read 5, iclass 36, count 2 2006.201.16:08:11.35#ibcon#about to read 6, iclass 36, count 2 2006.201.16:08:11.35#ibcon#read 6, iclass 36, count 2 2006.201.16:08:11.35#ibcon#end of sib2, iclass 36, count 2 2006.201.16:08:11.35#ibcon#*mode == 0, iclass 36, count 2 2006.201.16:08:11.35#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.16:08:11.35#ibcon#[25=AT01-08\r\n] 2006.201.16:08:11.35#ibcon#*before write, iclass 36, count 2 2006.201.16:08:11.35#ibcon#enter sib2, iclass 36, count 2 2006.201.16:08:11.35#ibcon#flushed, iclass 36, count 2 2006.201.16:08:11.35#ibcon#about to write, iclass 36, count 2 2006.201.16:08:11.35#ibcon#wrote, iclass 36, count 2 2006.201.16:08:11.35#ibcon#about to read 3, iclass 36, count 2 2006.201.16:08:11.39#ibcon#read 3, iclass 36, count 2 2006.201.16:08:11.39#ibcon#about to read 4, iclass 36, count 2 2006.201.16:08:11.39#ibcon#read 4, iclass 36, count 2 2006.201.16:08:11.39#ibcon#about to read 5, iclass 36, count 2 2006.201.16:08:11.39#ibcon#read 5, iclass 36, count 2 2006.201.16:08:11.39#ibcon#about to read 6, iclass 36, count 2 2006.201.16:08:11.39#ibcon#read 6, iclass 36, count 2 2006.201.16:08:11.39#ibcon#end of sib2, iclass 36, count 2 2006.201.16:08:11.39#ibcon#*after write, iclass 36, count 2 2006.201.16:08:11.39#ibcon#*before return 0, iclass 36, count 2 2006.201.16:08:11.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:11.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:11.39#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.16:08:11.39#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:11.39#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:11.51#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:11.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:11.51#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:08:11.51#ibcon#first serial, iclass 36, count 0 2006.201.16:08:11.51#ibcon#enter sib2, iclass 36, count 0 2006.201.16:08:11.51#ibcon#flushed, iclass 36, count 0 2006.201.16:08:11.51#ibcon#about to write, iclass 36, count 0 2006.201.16:08:11.51#ibcon#wrote, iclass 36, count 0 2006.201.16:08:11.51#ibcon#about to read 3, iclass 36, count 0 2006.201.16:08:11.53#ibcon#read 3, iclass 36, count 0 2006.201.16:08:11.53#ibcon#about to read 4, iclass 36, count 0 2006.201.16:08:11.53#ibcon#read 4, iclass 36, count 0 2006.201.16:08:11.53#ibcon#about to read 5, iclass 36, count 0 2006.201.16:08:11.53#ibcon#read 5, iclass 36, count 0 2006.201.16:08:11.53#ibcon#about to read 6, iclass 36, count 0 2006.201.16:08:11.53#ibcon#read 6, iclass 36, count 0 2006.201.16:08:11.53#ibcon#end of sib2, iclass 36, count 0 2006.201.16:08:11.53#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:08:11.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:08:11.53#ibcon#[25=USB\r\n] 2006.201.16:08:11.53#ibcon#*before write, iclass 36, count 0 2006.201.16:08:11.53#ibcon#enter sib2, iclass 36, count 0 2006.201.16:08:11.53#ibcon#flushed, iclass 36, count 0 2006.201.16:08:11.53#ibcon#about to write, iclass 36, count 0 2006.201.16:08:11.53#ibcon#wrote, iclass 36, count 0 2006.201.16:08:11.53#ibcon#about to read 3, iclass 36, count 0 2006.201.16:08:11.56#ibcon#read 3, iclass 36, count 0 2006.201.16:08:11.56#ibcon#about to read 4, iclass 36, count 0 2006.201.16:08:11.56#ibcon#read 4, iclass 36, count 0 2006.201.16:08:11.56#ibcon#about to read 5, iclass 36, count 0 2006.201.16:08:11.56#ibcon#read 5, iclass 36, count 0 2006.201.16:08:11.56#ibcon#about to read 6, iclass 36, count 0 2006.201.16:08:11.56#ibcon#read 6, iclass 36, count 0 2006.201.16:08:11.56#ibcon#end of sib2, iclass 36, count 0 2006.201.16:08:11.56#ibcon#*after write, iclass 36, count 0 2006.201.16:08:11.56#ibcon#*before return 0, iclass 36, count 0 2006.201.16:08:11.56#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:11.56#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:11.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:08:11.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:08:11.56$vck44/valo=2,534.99 2006.201.16:08:11.56#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.16:08:11.56#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.16:08:11.56#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:11.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:11.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:11.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:11.56#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:08:11.56#ibcon#first serial, iclass 38, count 0 2006.201.16:08:11.56#ibcon#enter sib2, iclass 38, count 0 2006.201.16:08:11.56#ibcon#flushed, iclass 38, count 0 2006.201.16:08:11.56#ibcon#about to write, iclass 38, count 0 2006.201.16:08:11.56#ibcon#wrote, iclass 38, count 0 2006.201.16:08:11.56#ibcon#about to read 3, iclass 38, count 0 2006.201.16:08:11.58#ibcon#read 3, iclass 38, count 0 2006.201.16:08:11.58#ibcon#about to read 4, iclass 38, count 0 2006.201.16:08:11.58#ibcon#read 4, iclass 38, count 0 2006.201.16:08:11.58#ibcon#about to read 5, iclass 38, count 0 2006.201.16:08:11.58#ibcon#read 5, iclass 38, count 0 2006.201.16:08:11.58#ibcon#about to read 6, iclass 38, count 0 2006.201.16:08:11.58#ibcon#read 6, iclass 38, count 0 2006.201.16:08:11.58#ibcon#end of sib2, iclass 38, count 0 2006.201.16:08:11.58#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:08:11.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:08:11.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:08:11.58#ibcon#*before write, iclass 38, count 0 2006.201.16:08:11.58#ibcon#enter sib2, iclass 38, count 0 2006.201.16:08:11.58#ibcon#flushed, iclass 38, count 0 2006.201.16:08:11.58#ibcon#about to write, iclass 38, count 0 2006.201.16:08:11.58#ibcon#wrote, iclass 38, count 0 2006.201.16:08:11.58#ibcon#about to read 3, iclass 38, count 0 2006.201.16:08:11.62#ibcon#read 3, iclass 38, count 0 2006.201.16:08:11.62#ibcon#about to read 4, iclass 38, count 0 2006.201.16:08:11.62#ibcon#read 4, iclass 38, count 0 2006.201.16:08:11.62#ibcon#about to read 5, iclass 38, count 0 2006.201.16:08:11.62#ibcon#read 5, iclass 38, count 0 2006.201.16:08:11.62#ibcon#about to read 6, iclass 38, count 0 2006.201.16:08:11.62#ibcon#read 6, iclass 38, count 0 2006.201.16:08:11.62#ibcon#end of sib2, iclass 38, count 0 2006.201.16:08:11.62#ibcon#*after write, iclass 38, count 0 2006.201.16:08:11.62#ibcon#*before return 0, iclass 38, count 0 2006.201.16:08:11.62#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:11.62#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:11.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:08:11.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:08:11.62$vck44/va=2,7 2006.201.16:08:11.62#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.16:08:11.62#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.16:08:11.62#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:11.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:11.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:11.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:11.68#ibcon#enter wrdev, iclass 40, count 2 2006.201.16:08:11.68#ibcon#first serial, iclass 40, count 2 2006.201.16:08:11.68#ibcon#enter sib2, iclass 40, count 2 2006.201.16:08:11.68#ibcon#flushed, iclass 40, count 2 2006.201.16:08:11.68#ibcon#about to write, iclass 40, count 2 2006.201.16:08:11.68#ibcon#wrote, iclass 40, count 2 2006.201.16:08:11.68#ibcon#about to read 3, iclass 40, count 2 2006.201.16:08:11.70#ibcon#read 3, iclass 40, count 2 2006.201.16:08:11.70#ibcon#about to read 4, iclass 40, count 2 2006.201.16:08:11.70#ibcon#read 4, iclass 40, count 2 2006.201.16:08:11.70#ibcon#about to read 5, iclass 40, count 2 2006.201.16:08:11.70#ibcon#read 5, iclass 40, count 2 2006.201.16:08:11.70#ibcon#about to read 6, iclass 40, count 2 2006.201.16:08:11.70#ibcon#read 6, iclass 40, count 2 2006.201.16:08:11.70#ibcon#end of sib2, iclass 40, count 2 2006.201.16:08:11.70#ibcon#*mode == 0, iclass 40, count 2 2006.201.16:08:11.70#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.16:08:11.70#ibcon#[25=AT02-07\r\n] 2006.201.16:08:11.70#ibcon#*before write, iclass 40, count 2 2006.201.16:08:11.70#ibcon#enter sib2, iclass 40, count 2 2006.201.16:08:11.70#ibcon#flushed, iclass 40, count 2 2006.201.16:08:11.70#ibcon#about to write, iclass 40, count 2 2006.201.16:08:11.70#ibcon#wrote, iclass 40, count 2 2006.201.16:08:11.70#ibcon#about to read 3, iclass 40, count 2 2006.201.16:08:11.73#ibcon#read 3, iclass 40, count 2 2006.201.16:08:11.73#ibcon#about to read 4, iclass 40, count 2 2006.201.16:08:11.73#ibcon#read 4, iclass 40, count 2 2006.201.16:08:11.73#ibcon#about to read 5, iclass 40, count 2 2006.201.16:08:11.73#ibcon#read 5, iclass 40, count 2 2006.201.16:08:11.73#ibcon#about to read 6, iclass 40, count 2 2006.201.16:08:11.73#ibcon#read 6, iclass 40, count 2 2006.201.16:08:11.73#ibcon#end of sib2, iclass 40, count 2 2006.201.16:08:11.73#ibcon#*after write, iclass 40, count 2 2006.201.16:08:11.73#ibcon#*before return 0, iclass 40, count 2 2006.201.16:08:11.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:11.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:11.73#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.16:08:11.73#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:11.73#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:11.85#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:11.85#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:11.85#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:08:11.85#ibcon#first serial, iclass 40, count 0 2006.201.16:08:11.85#ibcon#enter sib2, iclass 40, count 0 2006.201.16:08:11.85#ibcon#flushed, iclass 40, count 0 2006.201.16:08:11.85#ibcon#about to write, iclass 40, count 0 2006.201.16:08:11.85#ibcon#wrote, iclass 40, count 0 2006.201.16:08:11.85#ibcon#about to read 3, iclass 40, count 0 2006.201.16:08:11.87#ibcon#read 3, iclass 40, count 0 2006.201.16:08:11.87#ibcon#about to read 4, iclass 40, count 0 2006.201.16:08:11.87#ibcon#read 4, iclass 40, count 0 2006.201.16:08:11.87#ibcon#about to read 5, iclass 40, count 0 2006.201.16:08:11.87#ibcon#read 5, iclass 40, count 0 2006.201.16:08:11.87#ibcon#about to read 6, iclass 40, count 0 2006.201.16:08:11.87#ibcon#read 6, iclass 40, count 0 2006.201.16:08:11.87#ibcon#end of sib2, iclass 40, count 0 2006.201.16:08:11.87#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:08:11.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:08:11.87#ibcon#[25=USB\r\n] 2006.201.16:08:11.87#ibcon#*before write, iclass 40, count 0 2006.201.16:08:11.87#ibcon#enter sib2, iclass 40, count 0 2006.201.16:08:11.87#ibcon#flushed, iclass 40, count 0 2006.201.16:08:11.87#ibcon#about to write, iclass 40, count 0 2006.201.16:08:11.87#ibcon#wrote, iclass 40, count 0 2006.201.16:08:11.87#ibcon#about to read 3, iclass 40, count 0 2006.201.16:08:11.90#ibcon#read 3, iclass 40, count 0 2006.201.16:08:11.90#ibcon#about to read 4, iclass 40, count 0 2006.201.16:08:11.90#ibcon#read 4, iclass 40, count 0 2006.201.16:08:11.90#ibcon#about to read 5, iclass 40, count 0 2006.201.16:08:11.90#ibcon#read 5, iclass 40, count 0 2006.201.16:08:11.90#ibcon#about to read 6, iclass 40, count 0 2006.201.16:08:11.90#ibcon#read 6, iclass 40, count 0 2006.201.16:08:11.90#ibcon#end of sib2, iclass 40, count 0 2006.201.16:08:11.90#ibcon#*after write, iclass 40, count 0 2006.201.16:08:11.90#ibcon#*before return 0, iclass 40, count 0 2006.201.16:08:11.90#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:11.90#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:11.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:08:11.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:08:11.90$vck44/valo=3,564.99 2006.201.16:08:11.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.16:08:11.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.16:08:11.90#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:11.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:11.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:11.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:11.90#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:08:11.90#ibcon#first serial, iclass 4, count 0 2006.201.16:08:11.90#ibcon#enter sib2, iclass 4, count 0 2006.201.16:08:11.90#ibcon#flushed, iclass 4, count 0 2006.201.16:08:11.90#ibcon#about to write, iclass 4, count 0 2006.201.16:08:11.90#ibcon#wrote, iclass 4, count 0 2006.201.16:08:11.90#ibcon#about to read 3, iclass 4, count 0 2006.201.16:08:11.92#ibcon#read 3, iclass 4, count 0 2006.201.16:08:11.92#ibcon#about to read 4, iclass 4, count 0 2006.201.16:08:11.92#ibcon#read 4, iclass 4, count 0 2006.201.16:08:11.92#ibcon#about to read 5, iclass 4, count 0 2006.201.16:08:11.92#ibcon#read 5, iclass 4, count 0 2006.201.16:08:11.92#ibcon#about to read 6, iclass 4, count 0 2006.201.16:08:11.92#ibcon#read 6, iclass 4, count 0 2006.201.16:08:11.92#ibcon#end of sib2, iclass 4, count 0 2006.201.16:08:11.92#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:08:11.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:08:11.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:08:11.92#ibcon#*before write, iclass 4, count 0 2006.201.16:08:11.92#ibcon#enter sib2, iclass 4, count 0 2006.201.16:08:11.92#ibcon#flushed, iclass 4, count 0 2006.201.16:08:11.92#ibcon#about to write, iclass 4, count 0 2006.201.16:08:11.92#ibcon#wrote, iclass 4, count 0 2006.201.16:08:11.92#ibcon#about to read 3, iclass 4, count 0 2006.201.16:08:11.97#ibcon#read 3, iclass 4, count 0 2006.201.16:08:11.97#ibcon#about to read 4, iclass 4, count 0 2006.201.16:08:11.97#ibcon#read 4, iclass 4, count 0 2006.201.16:08:11.97#ibcon#about to read 5, iclass 4, count 0 2006.201.16:08:11.97#ibcon#read 5, iclass 4, count 0 2006.201.16:08:11.97#ibcon#about to read 6, iclass 4, count 0 2006.201.16:08:11.97#ibcon#read 6, iclass 4, count 0 2006.201.16:08:11.97#ibcon#end of sib2, iclass 4, count 0 2006.201.16:08:11.97#ibcon#*after write, iclass 4, count 0 2006.201.16:08:11.97#ibcon#*before return 0, iclass 4, count 0 2006.201.16:08:11.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:11.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:11.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:08:11.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:08:11.97$vck44/va=3,8 2006.201.16:08:11.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.16:08:11.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.16:08:11.97#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:11.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:12.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:12.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:12.02#ibcon#enter wrdev, iclass 6, count 2 2006.201.16:08:12.02#ibcon#first serial, iclass 6, count 2 2006.201.16:08:12.02#ibcon#enter sib2, iclass 6, count 2 2006.201.16:08:12.02#ibcon#flushed, iclass 6, count 2 2006.201.16:08:12.02#ibcon#about to write, iclass 6, count 2 2006.201.16:08:12.02#ibcon#wrote, iclass 6, count 2 2006.201.16:08:12.02#ibcon#about to read 3, iclass 6, count 2 2006.201.16:08:12.04#ibcon#read 3, iclass 6, count 2 2006.201.16:08:12.04#ibcon#about to read 4, iclass 6, count 2 2006.201.16:08:12.04#ibcon#read 4, iclass 6, count 2 2006.201.16:08:12.04#ibcon#about to read 5, iclass 6, count 2 2006.201.16:08:12.04#ibcon#read 5, iclass 6, count 2 2006.201.16:08:12.04#ibcon#about to read 6, iclass 6, count 2 2006.201.16:08:12.04#ibcon#read 6, iclass 6, count 2 2006.201.16:08:12.04#ibcon#end of sib2, iclass 6, count 2 2006.201.16:08:12.04#ibcon#*mode == 0, iclass 6, count 2 2006.201.16:08:12.04#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.16:08:12.04#ibcon#[25=AT03-08\r\n] 2006.201.16:08:12.04#ibcon#*before write, iclass 6, count 2 2006.201.16:08:12.04#ibcon#enter sib2, iclass 6, count 2 2006.201.16:08:12.04#ibcon#flushed, iclass 6, count 2 2006.201.16:08:12.04#ibcon#about to write, iclass 6, count 2 2006.201.16:08:12.04#ibcon#wrote, iclass 6, count 2 2006.201.16:08:12.04#ibcon#about to read 3, iclass 6, count 2 2006.201.16:08:12.07#ibcon#read 3, iclass 6, count 2 2006.201.16:08:12.07#ibcon#about to read 4, iclass 6, count 2 2006.201.16:08:12.07#ibcon#read 4, iclass 6, count 2 2006.201.16:08:12.07#ibcon#about to read 5, iclass 6, count 2 2006.201.16:08:12.07#ibcon#read 5, iclass 6, count 2 2006.201.16:08:12.07#ibcon#about to read 6, iclass 6, count 2 2006.201.16:08:12.07#ibcon#read 6, iclass 6, count 2 2006.201.16:08:12.07#ibcon#end of sib2, iclass 6, count 2 2006.201.16:08:12.07#ibcon#*after write, iclass 6, count 2 2006.201.16:08:12.07#ibcon#*before return 0, iclass 6, count 2 2006.201.16:08:12.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:12.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:12.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.16:08:12.07#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:12.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:12.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:12.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:12.19#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:08:12.19#ibcon#first serial, iclass 6, count 0 2006.201.16:08:12.19#ibcon#enter sib2, iclass 6, count 0 2006.201.16:08:12.19#ibcon#flushed, iclass 6, count 0 2006.201.16:08:12.19#ibcon#about to write, iclass 6, count 0 2006.201.16:08:12.19#ibcon#wrote, iclass 6, count 0 2006.201.16:08:12.19#ibcon#about to read 3, iclass 6, count 0 2006.201.16:08:12.22#ibcon#read 3, iclass 6, count 0 2006.201.16:08:12.22#ibcon#about to read 4, iclass 6, count 0 2006.201.16:08:12.22#ibcon#read 4, iclass 6, count 0 2006.201.16:08:12.22#ibcon#about to read 5, iclass 6, count 0 2006.201.16:08:12.22#ibcon#read 5, iclass 6, count 0 2006.201.16:08:12.22#ibcon#about to read 6, iclass 6, count 0 2006.201.16:08:12.22#ibcon#read 6, iclass 6, count 0 2006.201.16:08:12.22#ibcon#end of sib2, iclass 6, count 0 2006.201.16:08:12.22#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:08:12.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:08:12.22#ibcon#[25=USB\r\n] 2006.201.16:08:12.22#ibcon#*before write, iclass 6, count 0 2006.201.16:08:12.22#ibcon#enter sib2, iclass 6, count 0 2006.201.16:08:12.22#ibcon#flushed, iclass 6, count 0 2006.201.16:08:12.22#ibcon#about to write, iclass 6, count 0 2006.201.16:08:12.22#ibcon#wrote, iclass 6, count 0 2006.201.16:08:12.22#ibcon#about to read 3, iclass 6, count 0 2006.201.16:08:12.25#ibcon#read 3, iclass 6, count 0 2006.201.16:08:12.25#ibcon#about to read 4, iclass 6, count 0 2006.201.16:08:12.25#ibcon#read 4, iclass 6, count 0 2006.201.16:08:12.25#ibcon#about to read 5, iclass 6, count 0 2006.201.16:08:12.25#ibcon#read 5, iclass 6, count 0 2006.201.16:08:12.25#ibcon#about to read 6, iclass 6, count 0 2006.201.16:08:12.25#ibcon#read 6, iclass 6, count 0 2006.201.16:08:12.25#ibcon#end of sib2, iclass 6, count 0 2006.201.16:08:12.25#ibcon#*after write, iclass 6, count 0 2006.201.16:08:12.25#ibcon#*before return 0, iclass 6, count 0 2006.201.16:08:12.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:12.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:12.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:08:12.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:08:12.25$vck44/valo=4,624.99 2006.201.16:08:12.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.16:08:12.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.16:08:12.25#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:12.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:12.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:12.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:12.25#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:08:12.25#ibcon#first serial, iclass 10, count 0 2006.201.16:08:12.25#ibcon#enter sib2, iclass 10, count 0 2006.201.16:08:12.25#ibcon#flushed, iclass 10, count 0 2006.201.16:08:12.25#ibcon#about to write, iclass 10, count 0 2006.201.16:08:12.25#ibcon#wrote, iclass 10, count 0 2006.201.16:08:12.25#ibcon#about to read 3, iclass 10, count 0 2006.201.16:08:12.27#ibcon#read 3, iclass 10, count 0 2006.201.16:08:12.27#ibcon#about to read 4, iclass 10, count 0 2006.201.16:08:12.27#ibcon#read 4, iclass 10, count 0 2006.201.16:08:12.27#ibcon#about to read 5, iclass 10, count 0 2006.201.16:08:12.27#ibcon#read 5, iclass 10, count 0 2006.201.16:08:12.27#ibcon#about to read 6, iclass 10, count 0 2006.201.16:08:12.27#ibcon#read 6, iclass 10, count 0 2006.201.16:08:12.27#ibcon#end of sib2, iclass 10, count 0 2006.201.16:08:12.27#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:08:12.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:08:12.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:08:12.27#ibcon#*before write, iclass 10, count 0 2006.201.16:08:12.27#ibcon#enter sib2, iclass 10, count 0 2006.201.16:08:12.27#ibcon#flushed, iclass 10, count 0 2006.201.16:08:12.27#ibcon#about to write, iclass 10, count 0 2006.201.16:08:12.27#ibcon#wrote, iclass 10, count 0 2006.201.16:08:12.27#ibcon#about to read 3, iclass 10, count 0 2006.201.16:08:12.31#ibcon#read 3, iclass 10, count 0 2006.201.16:08:12.31#ibcon#about to read 4, iclass 10, count 0 2006.201.16:08:12.31#ibcon#read 4, iclass 10, count 0 2006.201.16:08:12.31#ibcon#about to read 5, iclass 10, count 0 2006.201.16:08:12.31#ibcon#read 5, iclass 10, count 0 2006.201.16:08:12.31#ibcon#about to read 6, iclass 10, count 0 2006.201.16:08:12.31#ibcon#read 6, iclass 10, count 0 2006.201.16:08:12.31#ibcon#end of sib2, iclass 10, count 0 2006.201.16:08:12.31#ibcon#*after write, iclass 10, count 0 2006.201.16:08:12.31#ibcon#*before return 0, iclass 10, count 0 2006.201.16:08:12.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:12.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:12.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:08:12.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:08:12.31$vck44/va=4,7 2006.201.16:08:12.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.16:08:12.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.16:08:12.31#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:12.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:12.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:12.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:12.37#ibcon#enter wrdev, iclass 12, count 2 2006.201.16:08:12.37#ibcon#first serial, iclass 12, count 2 2006.201.16:08:12.37#ibcon#enter sib2, iclass 12, count 2 2006.201.16:08:12.37#ibcon#flushed, iclass 12, count 2 2006.201.16:08:12.37#ibcon#about to write, iclass 12, count 2 2006.201.16:08:12.37#ibcon#wrote, iclass 12, count 2 2006.201.16:08:12.37#ibcon#about to read 3, iclass 12, count 2 2006.201.16:08:12.39#ibcon#read 3, iclass 12, count 2 2006.201.16:08:12.39#ibcon#about to read 4, iclass 12, count 2 2006.201.16:08:12.39#ibcon#read 4, iclass 12, count 2 2006.201.16:08:12.39#ibcon#about to read 5, iclass 12, count 2 2006.201.16:08:12.39#ibcon#read 5, iclass 12, count 2 2006.201.16:08:12.39#ibcon#about to read 6, iclass 12, count 2 2006.201.16:08:12.39#ibcon#read 6, iclass 12, count 2 2006.201.16:08:12.39#ibcon#end of sib2, iclass 12, count 2 2006.201.16:08:12.39#ibcon#*mode == 0, iclass 12, count 2 2006.201.16:08:12.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.16:08:12.39#ibcon#[25=AT04-07\r\n] 2006.201.16:08:12.39#ibcon#*before write, iclass 12, count 2 2006.201.16:08:12.39#ibcon#enter sib2, iclass 12, count 2 2006.201.16:08:12.39#ibcon#flushed, iclass 12, count 2 2006.201.16:08:12.39#ibcon#about to write, iclass 12, count 2 2006.201.16:08:12.39#ibcon#wrote, iclass 12, count 2 2006.201.16:08:12.39#ibcon#about to read 3, iclass 12, count 2 2006.201.16:08:12.42#ibcon#read 3, iclass 12, count 2 2006.201.16:08:12.42#ibcon#about to read 4, iclass 12, count 2 2006.201.16:08:12.42#ibcon#read 4, iclass 12, count 2 2006.201.16:08:12.42#ibcon#about to read 5, iclass 12, count 2 2006.201.16:08:12.42#ibcon#read 5, iclass 12, count 2 2006.201.16:08:12.42#ibcon#about to read 6, iclass 12, count 2 2006.201.16:08:12.42#ibcon#read 6, iclass 12, count 2 2006.201.16:08:12.42#ibcon#end of sib2, iclass 12, count 2 2006.201.16:08:12.42#ibcon#*after write, iclass 12, count 2 2006.201.16:08:12.42#ibcon#*before return 0, iclass 12, count 2 2006.201.16:08:12.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:12.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:12.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.16:08:12.42#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:12.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:12.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:12.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:12.54#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:08:12.54#ibcon#first serial, iclass 12, count 0 2006.201.16:08:12.54#ibcon#enter sib2, iclass 12, count 0 2006.201.16:08:12.54#ibcon#flushed, iclass 12, count 0 2006.201.16:08:12.54#ibcon#about to write, iclass 12, count 0 2006.201.16:08:12.54#ibcon#wrote, iclass 12, count 0 2006.201.16:08:12.54#ibcon#about to read 3, iclass 12, count 0 2006.201.16:08:12.56#ibcon#read 3, iclass 12, count 0 2006.201.16:08:12.56#ibcon#about to read 4, iclass 12, count 0 2006.201.16:08:12.56#ibcon#read 4, iclass 12, count 0 2006.201.16:08:12.56#ibcon#about to read 5, iclass 12, count 0 2006.201.16:08:12.56#ibcon#read 5, iclass 12, count 0 2006.201.16:08:12.56#ibcon#about to read 6, iclass 12, count 0 2006.201.16:08:12.56#ibcon#read 6, iclass 12, count 0 2006.201.16:08:12.56#ibcon#end of sib2, iclass 12, count 0 2006.201.16:08:12.56#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:08:12.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:08:12.56#ibcon#[25=USB\r\n] 2006.201.16:08:12.56#ibcon#*before write, iclass 12, count 0 2006.201.16:08:12.56#ibcon#enter sib2, iclass 12, count 0 2006.201.16:08:12.56#ibcon#flushed, iclass 12, count 0 2006.201.16:08:12.56#ibcon#about to write, iclass 12, count 0 2006.201.16:08:12.56#ibcon#wrote, iclass 12, count 0 2006.201.16:08:12.56#ibcon#about to read 3, iclass 12, count 0 2006.201.16:08:12.59#ibcon#read 3, iclass 12, count 0 2006.201.16:08:12.59#ibcon#about to read 4, iclass 12, count 0 2006.201.16:08:12.59#ibcon#read 4, iclass 12, count 0 2006.201.16:08:12.59#ibcon#about to read 5, iclass 12, count 0 2006.201.16:08:12.59#ibcon#read 5, iclass 12, count 0 2006.201.16:08:12.59#ibcon#about to read 6, iclass 12, count 0 2006.201.16:08:12.59#ibcon#read 6, iclass 12, count 0 2006.201.16:08:12.59#ibcon#end of sib2, iclass 12, count 0 2006.201.16:08:12.59#ibcon#*after write, iclass 12, count 0 2006.201.16:08:12.59#ibcon#*before return 0, iclass 12, count 0 2006.201.16:08:12.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:12.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:12.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:08:12.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:08:12.59$vck44/valo=5,734.99 2006.201.16:08:12.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.16:08:12.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.16:08:12.59#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:12.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:12.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:12.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:12.59#ibcon#enter wrdev, iclass 14, count 0 2006.201.16:08:12.59#ibcon#first serial, iclass 14, count 0 2006.201.16:08:12.59#ibcon#enter sib2, iclass 14, count 0 2006.201.16:08:12.59#ibcon#flushed, iclass 14, count 0 2006.201.16:08:12.59#ibcon#about to write, iclass 14, count 0 2006.201.16:08:12.59#ibcon#wrote, iclass 14, count 0 2006.201.16:08:12.59#ibcon#about to read 3, iclass 14, count 0 2006.201.16:08:12.61#ibcon#read 3, iclass 14, count 0 2006.201.16:08:12.61#ibcon#about to read 4, iclass 14, count 0 2006.201.16:08:12.61#ibcon#read 4, iclass 14, count 0 2006.201.16:08:12.61#ibcon#about to read 5, iclass 14, count 0 2006.201.16:08:12.61#ibcon#read 5, iclass 14, count 0 2006.201.16:08:12.61#ibcon#about to read 6, iclass 14, count 0 2006.201.16:08:12.61#ibcon#read 6, iclass 14, count 0 2006.201.16:08:12.61#ibcon#end of sib2, iclass 14, count 0 2006.201.16:08:12.61#ibcon#*mode == 0, iclass 14, count 0 2006.201.16:08:12.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.16:08:12.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:08:12.61#ibcon#*before write, iclass 14, count 0 2006.201.16:08:12.61#ibcon#enter sib2, iclass 14, count 0 2006.201.16:08:12.61#ibcon#flushed, iclass 14, count 0 2006.201.16:08:12.61#ibcon#about to write, iclass 14, count 0 2006.201.16:08:12.61#ibcon#wrote, iclass 14, count 0 2006.201.16:08:12.61#ibcon#about to read 3, iclass 14, count 0 2006.201.16:08:12.65#ibcon#read 3, iclass 14, count 0 2006.201.16:08:12.65#ibcon#about to read 4, iclass 14, count 0 2006.201.16:08:12.65#ibcon#read 4, iclass 14, count 0 2006.201.16:08:12.65#ibcon#about to read 5, iclass 14, count 0 2006.201.16:08:12.65#ibcon#read 5, iclass 14, count 0 2006.201.16:08:12.65#ibcon#about to read 6, iclass 14, count 0 2006.201.16:08:12.65#ibcon#read 6, iclass 14, count 0 2006.201.16:08:12.65#ibcon#end of sib2, iclass 14, count 0 2006.201.16:08:12.65#ibcon#*after write, iclass 14, count 0 2006.201.16:08:12.65#ibcon#*before return 0, iclass 14, count 0 2006.201.16:08:12.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:12.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:12.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.16:08:12.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.16:08:12.65$vck44/va=5,4 2006.201.16:08:12.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.16:08:12.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.16:08:12.65#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:12.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:12.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:12.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:12.71#ibcon#enter wrdev, iclass 16, count 2 2006.201.16:08:12.71#ibcon#first serial, iclass 16, count 2 2006.201.16:08:12.71#ibcon#enter sib2, iclass 16, count 2 2006.201.16:08:12.71#ibcon#flushed, iclass 16, count 2 2006.201.16:08:12.71#ibcon#about to write, iclass 16, count 2 2006.201.16:08:12.71#ibcon#wrote, iclass 16, count 2 2006.201.16:08:12.71#ibcon#about to read 3, iclass 16, count 2 2006.201.16:08:12.73#ibcon#read 3, iclass 16, count 2 2006.201.16:08:12.73#ibcon#about to read 4, iclass 16, count 2 2006.201.16:08:12.73#ibcon#read 4, iclass 16, count 2 2006.201.16:08:12.73#ibcon#about to read 5, iclass 16, count 2 2006.201.16:08:12.73#ibcon#read 5, iclass 16, count 2 2006.201.16:08:12.73#ibcon#about to read 6, iclass 16, count 2 2006.201.16:08:12.73#ibcon#read 6, iclass 16, count 2 2006.201.16:08:12.73#ibcon#end of sib2, iclass 16, count 2 2006.201.16:08:12.73#ibcon#*mode == 0, iclass 16, count 2 2006.201.16:08:12.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.16:08:12.73#ibcon#[25=AT05-04\r\n] 2006.201.16:08:12.73#ibcon#*before write, iclass 16, count 2 2006.201.16:08:12.73#ibcon#enter sib2, iclass 16, count 2 2006.201.16:08:12.73#ibcon#flushed, iclass 16, count 2 2006.201.16:08:12.73#ibcon#about to write, iclass 16, count 2 2006.201.16:08:12.73#ibcon#wrote, iclass 16, count 2 2006.201.16:08:12.73#ibcon#about to read 3, iclass 16, count 2 2006.201.16:08:12.76#ibcon#read 3, iclass 16, count 2 2006.201.16:08:12.76#ibcon#about to read 4, iclass 16, count 2 2006.201.16:08:12.76#ibcon#read 4, iclass 16, count 2 2006.201.16:08:12.76#ibcon#about to read 5, iclass 16, count 2 2006.201.16:08:12.76#ibcon#read 5, iclass 16, count 2 2006.201.16:08:12.76#ibcon#about to read 6, iclass 16, count 2 2006.201.16:08:12.76#ibcon#read 6, iclass 16, count 2 2006.201.16:08:12.76#ibcon#end of sib2, iclass 16, count 2 2006.201.16:08:12.76#ibcon#*after write, iclass 16, count 2 2006.201.16:08:12.76#ibcon#*before return 0, iclass 16, count 2 2006.201.16:08:12.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:12.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:12.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.16:08:12.76#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:12.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:12.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:12.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:12.88#ibcon#enter wrdev, iclass 16, count 0 2006.201.16:08:12.88#ibcon#first serial, iclass 16, count 0 2006.201.16:08:12.88#ibcon#enter sib2, iclass 16, count 0 2006.201.16:08:12.88#ibcon#flushed, iclass 16, count 0 2006.201.16:08:12.88#ibcon#about to write, iclass 16, count 0 2006.201.16:08:12.88#ibcon#wrote, iclass 16, count 0 2006.201.16:08:12.88#ibcon#about to read 3, iclass 16, count 0 2006.201.16:08:12.90#ibcon#read 3, iclass 16, count 0 2006.201.16:08:12.90#ibcon#about to read 4, iclass 16, count 0 2006.201.16:08:12.90#ibcon#read 4, iclass 16, count 0 2006.201.16:08:12.90#ibcon#about to read 5, iclass 16, count 0 2006.201.16:08:12.90#ibcon#read 5, iclass 16, count 0 2006.201.16:08:12.90#ibcon#about to read 6, iclass 16, count 0 2006.201.16:08:12.90#ibcon#read 6, iclass 16, count 0 2006.201.16:08:12.90#ibcon#end of sib2, iclass 16, count 0 2006.201.16:08:12.90#ibcon#*mode == 0, iclass 16, count 0 2006.201.16:08:12.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.16:08:12.90#ibcon#[25=USB\r\n] 2006.201.16:08:12.90#ibcon#*before write, iclass 16, count 0 2006.201.16:08:12.90#ibcon#enter sib2, iclass 16, count 0 2006.201.16:08:12.90#ibcon#flushed, iclass 16, count 0 2006.201.16:08:12.90#ibcon#about to write, iclass 16, count 0 2006.201.16:08:12.90#ibcon#wrote, iclass 16, count 0 2006.201.16:08:12.90#ibcon#about to read 3, iclass 16, count 0 2006.201.16:08:12.93#ibcon#read 3, iclass 16, count 0 2006.201.16:08:12.93#ibcon#about to read 4, iclass 16, count 0 2006.201.16:08:12.93#ibcon#read 4, iclass 16, count 0 2006.201.16:08:12.93#ibcon#about to read 5, iclass 16, count 0 2006.201.16:08:12.93#ibcon#read 5, iclass 16, count 0 2006.201.16:08:12.93#ibcon#about to read 6, iclass 16, count 0 2006.201.16:08:12.93#ibcon#read 6, iclass 16, count 0 2006.201.16:08:12.93#ibcon#end of sib2, iclass 16, count 0 2006.201.16:08:12.93#ibcon#*after write, iclass 16, count 0 2006.201.16:08:12.93#ibcon#*before return 0, iclass 16, count 0 2006.201.16:08:12.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:12.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:12.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.16:08:12.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.16:08:12.93$vck44/valo=6,814.99 2006.201.16:08:12.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.16:08:12.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.16:08:12.93#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:12.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:12.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:12.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:12.93#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:08:12.93#ibcon#first serial, iclass 18, count 0 2006.201.16:08:12.93#ibcon#enter sib2, iclass 18, count 0 2006.201.16:08:12.93#ibcon#flushed, iclass 18, count 0 2006.201.16:08:12.93#ibcon#about to write, iclass 18, count 0 2006.201.16:08:12.93#ibcon#wrote, iclass 18, count 0 2006.201.16:08:12.93#ibcon#about to read 3, iclass 18, count 0 2006.201.16:08:12.95#ibcon#read 3, iclass 18, count 0 2006.201.16:08:12.95#ibcon#about to read 4, iclass 18, count 0 2006.201.16:08:12.95#ibcon#read 4, iclass 18, count 0 2006.201.16:08:12.95#ibcon#about to read 5, iclass 18, count 0 2006.201.16:08:12.95#ibcon#read 5, iclass 18, count 0 2006.201.16:08:12.95#ibcon#about to read 6, iclass 18, count 0 2006.201.16:08:12.95#ibcon#read 6, iclass 18, count 0 2006.201.16:08:12.95#ibcon#end of sib2, iclass 18, count 0 2006.201.16:08:12.95#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:08:12.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:08:12.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:08:12.95#ibcon#*before write, iclass 18, count 0 2006.201.16:08:12.95#ibcon#enter sib2, iclass 18, count 0 2006.201.16:08:12.95#ibcon#flushed, iclass 18, count 0 2006.201.16:08:12.95#ibcon#about to write, iclass 18, count 0 2006.201.16:08:12.95#ibcon#wrote, iclass 18, count 0 2006.201.16:08:12.95#ibcon#about to read 3, iclass 18, count 0 2006.201.16:08:13.00#ibcon#read 3, iclass 18, count 0 2006.201.16:08:13.00#ibcon#about to read 4, iclass 18, count 0 2006.201.16:08:13.00#ibcon#read 4, iclass 18, count 0 2006.201.16:08:13.00#ibcon#about to read 5, iclass 18, count 0 2006.201.16:08:13.00#ibcon#read 5, iclass 18, count 0 2006.201.16:08:13.00#ibcon#about to read 6, iclass 18, count 0 2006.201.16:08:13.00#ibcon#read 6, iclass 18, count 0 2006.201.16:08:13.00#ibcon#end of sib2, iclass 18, count 0 2006.201.16:08:13.00#ibcon#*after write, iclass 18, count 0 2006.201.16:08:13.00#ibcon#*before return 0, iclass 18, count 0 2006.201.16:08:13.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:13.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:13.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:08:13.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:08:13.00$vck44/va=6,5 2006.201.16:08:13.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.16:08:13.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.16:08:13.00#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:13.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:13.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:13.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:13.05#ibcon#enter wrdev, iclass 20, count 2 2006.201.16:08:13.05#ibcon#first serial, iclass 20, count 2 2006.201.16:08:13.05#ibcon#enter sib2, iclass 20, count 2 2006.201.16:08:13.05#ibcon#flushed, iclass 20, count 2 2006.201.16:08:13.05#ibcon#about to write, iclass 20, count 2 2006.201.16:08:13.05#ibcon#wrote, iclass 20, count 2 2006.201.16:08:13.05#ibcon#about to read 3, iclass 20, count 2 2006.201.16:08:13.07#ibcon#read 3, iclass 20, count 2 2006.201.16:08:13.07#ibcon#about to read 4, iclass 20, count 2 2006.201.16:08:13.07#ibcon#read 4, iclass 20, count 2 2006.201.16:08:13.07#ibcon#about to read 5, iclass 20, count 2 2006.201.16:08:13.07#ibcon#read 5, iclass 20, count 2 2006.201.16:08:13.07#ibcon#about to read 6, iclass 20, count 2 2006.201.16:08:13.07#ibcon#read 6, iclass 20, count 2 2006.201.16:08:13.07#ibcon#end of sib2, iclass 20, count 2 2006.201.16:08:13.07#ibcon#*mode == 0, iclass 20, count 2 2006.201.16:08:13.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.16:08:13.07#ibcon#[25=AT06-05\r\n] 2006.201.16:08:13.07#ibcon#*before write, iclass 20, count 2 2006.201.16:08:13.07#ibcon#enter sib2, iclass 20, count 2 2006.201.16:08:13.07#ibcon#flushed, iclass 20, count 2 2006.201.16:08:13.07#ibcon#about to write, iclass 20, count 2 2006.201.16:08:13.07#ibcon#wrote, iclass 20, count 2 2006.201.16:08:13.07#ibcon#about to read 3, iclass 20, count 2 2006.201.16:08:13.10#ibcon#read 3, iclass 20, count 2 2006.201.16:08:13.10#ibcon#about to read 4, iclass 20, count 2 2006.201.16:08:13.10#ibcon#read 4, iclass 20, count 2 2006.201.16:08:13.10#ibcon#about to read 5, iclass 20, count 2 2006.201.16:08:13.10#ibcon#read 5, iclass 20, count 2 2006.201.16:08:13.10#ibcon#about to read 6, iclass 20, count 2 2006.201.16:08:13.10#ibcon#read 6, iclass 20, count 2 2006.201.16:08:13.10#ibcon#end of sib2, iclass 20, count 2 2006.201.16:08:13.10#ibcon#*after write, iclass 20, count 2 2006.201.16:08:13.10#ibcon#*before return 0, iclass 20, count 2 2006.201.16:08:13.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:13.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:13.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.16:08:13.10#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:13.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:13.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:13.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:13.22#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:08:13.22#ibcon#first serial, iclass 20, count 0 2006.201.16:08:13.22#ibcon#enter sib2, iclass 20, count 0 2006.201.16:08:13.22#ibcon#flushed, iclass 20, count 0 2006.201.16:08:13.22#ibcon#about to write, iclass 20, count 0 2006.201.16:08:13.22#ibcon#wrote, iclass 20, count 0 2006.201.16:08:13.22#ibcon#about to read 3, iclass 20, count 0 2006.201.16:08:13.24#ibcon#read 3, iclass 20, count 0 2006.201.16:08:13.24#ibcon#about to read 4, iclass 20, count 0 2006.201.16:08:13.24#ibcon#read 4, iclass 20, count 0 2006.201.16:08:13.24#ibcon#about to read 5, iclass 20, count 0 2006.201.16:08:13.24#ibcon#read 5, iclass 20, count 0 2006.201.16:08:13.24#ibcon#about to read 6, iclass 20, count 0 2006.201.16:08:13.24#ibcon#read 6, iclass 20, count 0 2006.201.16:08:13.24#ibcon#end of sib2, iclass 20, count 0 2006.201.16:08:13.24#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:08:13.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:08:13.24#ibcon#[25=USB\r\n] 2006.201.16:08:13.24#ibcon#*before write, iclass 20, count 0 2006.201.16:08:13.24#ibcon#enter sib2, iclass 20, count 0 2006.201.16:08:13.24#ibcon#flushed, iclass 20, count 0 2006.201.16:08:13.24#ibcon#about to write, iclass 20, count 0 2006.201.16:08:13.24#ibcon#wrote, iclass 20, count 0 2006.201.16:08:13.24#ibcon#about to read 3, iclass 20, count 0 2006.201.16:08:13.27#ibcon#read 3, iclass 20, count 0 2006.201.16:08:13.27#ibcon#about to read 4, iclass 20, count 0 2006.201.16:08:13.27#ibcon#read 4, iclass 20, count 0 2006.201.16:08:13.27#ibcon#about to read 5, iclass 20, count 0 2006.201.16:08:13.27#ibcon#read 5, iclass 20, count 0 2006.201.16:08:13.27#ibcon#about to read 6, iclass 20, count 0 2006.201.16:08:13.27#ibcon#read 6, iclass 20, count 0 2006.201.16:08:13.27#ibcon#end of sib2, iclass 20, count 0 2006.201.16:08:13.27#ibcon#*after write, iclass 20, count 0 2006.201.16:08:13.27#ibcon#*before return 0, iclass 20, count 0 2006.201.16:08:13.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:13.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:13.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:08:13.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:08:13.27$vck44/valo=7,864.99 2006.201.16:08:13.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.16:08:13.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.16:08:13.27#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:13.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:13.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:13.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:13.27#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:08:13.27#ibcon#first serial, iclass 22, count 0 2006.201.16:08:13.27#ibcon#enter sib2, iclass 22, count 0 2006.201.16:08:13.27#ibcon#flushed, iclass 22, count 0 2006.201.16:08:13.27#ibcon#about to write, iclass 22, count 0 2006.201.16:08:13.27#ibcon#wrote, iclass 22, count 0 2006.201.16:08:13.27#ibcon#about to read 3, iclass 22, count 0 2006.201.16:08:13.29#ibcon#read 3, iclass 22, count 0 2006.201.16:08:13.29#ibcon#about to read 4, iclass 22, count 0 2006.201.16:08:13.29#ibcon#read 4, iclass 22, count 0 2006.201.16:08:13.29#ibcon#about to read 5, iclass 22, count 0 2006.201.16:08:13.29#ibcon#read 5, iclass 22, count 0 2006.201.16:08:13.29#ibcon#about to read 6, iclass 22, count 0 2006.201.16:08:13.29#ibcon#read 6, iclass 22, count 0 2006.201.16:08:13.29#ibcon#end of sib2, iclass 22, count 0 2006.201.16:08:13.29#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:08:13.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:08:13.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:08:13.29#ibcon#*before write, iclass 22, count 0 2006.201.16:08:13.29#ibcon#enter sib2, iclass 22, count 0 2006.201.16:08:13.29#ibcon#flushed, iclass 22, count 0 2006.201.16:08:13.29#ibcon#about to write, iclass 22, count 0 2006.201.16:08:13.29#ibcon#wrote, iclass 22, count 0 2006.201.16:08:13.29#ibcon#about to read 3, iclass 22, count 0 2006.201.16:08:13.33#ibcon#read 3, iclass 22, count 0 2006.201.16:08:13.33#ibcon#about to read 4, iclass 22, count 0 2006.201.16:08:13.33#ibcon#read 4, iclass 22, count 0 2006.201.16:08:13.33#ibcon#about to read 5, iclass 22, count 0 2006.201.16:08:13.33#ibcon#read 5, iclass 22, count 0 2006.201.16:08:13.33#ibcon#about to read 6, iclass 22, count 0 2006.201.16:08:13.33#ibcon#read 6, iclass 22, count 0 2006.201.16:08:13.33#ibcon#end of sib2, iclass 22, count 0 2006.201.16:08:13.33#ibcon#*after write, iclass 22, count 0 2006.201.16:08:13.33#ibcon#*before return 0, iclass 22, count 0 2006.201.16:08:13.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:13.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:13.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:08:13.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:08:13.33$vck44/va=7,5 2006.201.16:08:13.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.16:08:13.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.16:08:13.33#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:13.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:13.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:13.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:13.39#ibcon#enter wrdev, iclass 24, count 2 2006.201.16:08:13.39#ibcon#first serial, iclass 24, count 2 2006.201.16:08:13.39#ibcon#enter sib2, iclass 24, count 2 2006.201.16:08:13.39#ibcon#flushed, iclass 24, count 2 2006.201.16:08:13.39#ibcon#about to write, iclass 24, count 2 2006.201.16:08:13.39#ibcon#wrote, iclass 24, count 2 2006.201.16:08:13.39#ibcon#about to read 3, iclass 24, count 2 2006.201.16:08:13.41#ibcon#read 3, iclass 24, count 2 2006.201.16:08:13.41#ibcon#about to read 4, iclass 24, count 2 2006.201.16:08:13.41#ibcon#read 4, iclass 24, count 2 2006.201.16:08:13.41#ibcon#about to read 5, iclass 24, count 2 2006.201.16:08:13.41#ibcon#read 5, iclass 24, count 2 2006.201.16:08:13.41#ibcon#about to read 6, iclass 24, count 2 2006.201.16:08:13.41#ibcon#read 6, iclass 24, count 2 2006.201.16:08:13.41#ibcon#end of sib2, iclass 24, count 2 2006.201.16:08:13.41#ibcon#*mode == 0, iclass 24, count 2 2006.201.16:08:13.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.16:08:13.41#ibcon#[25=AT07-05\r\n] 2006.201.16:08:13.41#ibcon#*before write, iclass 24, count 2 2006.201.16:08:13.41#ibcon#enter sib2, iclass 24, count 2 2006.201.16:08:13.41#ibcon#flushed, iclass 24, count 2 2006.201.16:08:13.41#ibcon#about to write, iclass 24, count 2 2006.201.16:08:13.41#ibcon#wrote, iclass 24, count 2 2006.201.16:08:13.41#ibcon#about to read 3, iclass 24, count 2 2006.201.16:08:13.44#ibcon#read 3, iclass 24, count 2 2006.201.16:08:13.44#ibcon#about to read 4, iclass 24, count 2 2006.201.16:08:13.44#ibcon#read 4, iclass 24, count 2 2006.201.16:08:13.44#ibcon#about to read 5, iclass 24, count 2 2006.201.16:08:13.44#ibcon#read 5, iclass 24, count 2 2006.201.16:08:13.44#ibcon#about to read 6, iclass 24, count 2 2006.201.16:08:13.44#ibcon#read 6, iclass 24, count 2 2006.201.16:08:13.44#ibcon#end of sib2, iclass 24, count 2 2006.201.16:08:13.44#ibcon#*after write, iclass 24, count 2 2006.201.16:08:13.44#ibcon#*before return 0, iclass 24, count 2 2006.201.16:08:13.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:13.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:13.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.16:08:13.44#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:13.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:13.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:13.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:13.56#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:08:13.56#ibcon#first serial, iclass 24, count 0 2006.201.16:08:13.56#ibcon#enter sib2, iclass 24, count 0 2006.201.16:08:13.56#ibcon#flushed, iclass 24, count 0 2006.201.16:08:13.56#ibcon#about to write, iclass 24, count 0 2006.201.16:08:13.56#ibcon#wrote, iclass 24, count 0 2006.201.16:08:13.56#ibcon#about to read 3, iclass 24, count 0 2006.201.16:08:13.58#ibcon#read 3, iclass 24, count 0 2006.201.16:08:13.58#ibcon#about to read 4, iclass 24, count 0 2006.201.16:08:13.58#ibcon#read 4, iclass 24, count 0 2006.201.16:08:13.58#ibcon#about to read 5, iclass 24, count 0 2006.201.16:08:13.58#ibcon#read 5, iclass 24, count 0 2006.201.16:08:13.58#ibcon#about to read 6, iclass 24, count 0 2006.201.16:08:13.58#ibcon#read 6, iclass 24, count 0 2006.201.16:08:13.58#ibcon#end of sib2, iclass 24, count 0 2006.201.16:08:13.58#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:08:13.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:08:13.58#ibcon#[25=USB\r\n] 2006.201.16:08:13.58#ibcon#*before write, iclass 24, count 0 2006.201.16:08:13.58#ibcon#enter sib2, iclass 24, count 0 2006.201.16:08:13.58#ibcon#flushed, iclass 24, count 0 2006.201.16:08:13.58#ibcon#about to write, iclass 24, count 0 2006.201.16:08:13.58#ibcon#wrote, iclass 24, count 0 2006.201.16:08:13.58#ibcon#about to read 3, iclass 24, count 0 2006.201.16:08:13.61#ibcon#read 3, iclass 24, count 0 2006.201.16:08:13.61#ibcon#about to read 4, iclass 24, count 0 2006.201.16:08:13.61#ibcon#read 4, iclass 24, count 0 2006.201.16:08:13.61#ibcon#about to read 5, iclass 24, count 0 2006.201.16:08:13.61#ibcon#read 5, iclass 24, count 0 2006.201.16:08:13.61#ibcon#about to read 6, iclass 24, count 0 2006.201.16:08:13.61#ibcon#read 6, iclass 24, count 0 2006.201.16:08:13.61#ibcon#end of sib2, iclass 24, count 0 2006.201.16:08:13.61#ibcon#*after write, iclass 24, count 0 2006.201.16:08:13.61#ibcon#*before return 0, iclass 24, count 0 2006.201.16:08:13.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:13.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:13.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:08:13.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:08:13.61$vck44/valo=8,884.99 2006.201.16:08:13.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.16:08:13.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.16:08:13.61#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:13.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:13.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:13.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:13.61#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:08:13.61#ibcon#first serial, iclass 26, count 0 2006.201.16:08:13.61#ibcon#enter sib2, iclass 26, count 0 2006.201.16:08:13.61#ibcon#flushed, iclass 26, count 0 2006.201.16:08:13.61#ibcon#about to write, iclass 26, count 0 2006.201.16:08:13.61#ibcon#wrote, iclass 26, count 0 2006.201.16:08:13.61#ibcon#about to read 3, iclass 26, count 0 2006.201.16:08:13.63#ibcon#read 3, iclass 26, count 0 2006.201.16:08:13.63#ibcon#about to read 4, iclass 26, count 0 2006.201.16:08:13.63#ibcon#read 4, iclass 26, count 0 2006.201.16:08:13.63#ibcon#about to read 5, iclass 26, count 0 2006.201.16:08:13.63#ibcon#read 5, iclass 26, count 0 2006.201.16:08:13.63#ibcon#about to read 6, iclass 26, count 0 2006.201.16:08:13.63#ibcon#read 6, iclass 26, count 0 2006.201.16:08:13.63#ibcon#end of sib2, iclass 26, count 0 2006.201.16:08:13.63#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:08:13.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:08:13.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:08:13.63#ibcon#*before write, iclass 26, count 0 2006.201.16:08:13.63#ibcon#enter sib2, iclass 26, count 0 2006.201.16:08:13.63#ibcon#flushed, iclass 26, count 0 2006.201.16:08:13.63#ibcon#about to write, iclass 26, count 0 2006.201.16:08:13.63#ibcon#wrote, iclass 26, count 0 2006.201.16:08:13.63#ibcon#about to read 3, iclass 26, count 0 2006.201.16:08:13.67#ibcon#read 3, iclass 26, count 0 2006.201.16:08:13.67#ibcon#about to read 4, iclass 26, count 0 2006.201.16:08:13.67#ibcon#read 4, iclass 26, count 0 2006.201.16:08:13.67#ibcon#about to read 5, iclass 26, count 0 2006.201.16:08:13.67#ibcon#read 5, iclass 26, count 0 2006.201.16:08:13.67#ibcon#about to read 6, iclass 26, count 0 2006.201.16:08:13.67#ibcon#read 6, iclass 26, count 0 2006.201.16:08:13.67#ibcon#end of sib2, iclass 26, count 0 2006.201.16:08:13.67#ibcon#*after write, iclass 26, count 0 2006.201.16:08:13.67#ibcon#*before return 0, iclass 26, count 0 2006.201.16:08:13.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:13.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:13.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:08:13.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:08:13.67$vck44/va=8,4 2006.201.16:08:13.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.16:08:13.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.16:08:13.67#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:13.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:08:13.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:08:13.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:08:13.73#ibcon#enter wrdev, iclass 28, count 2 2006.201.16:08:13.73#ibcon#first serial, iclass 28, count 2 2006.201.16:08:13.73#ibcon#enter sib2, iclass 28, count 2 2006.201.16:08:13.73#ibcon#flushed, iclass 28, count 2 2006.201.16:08:13.73#ibcon#about to write, iclass 28, count 2 2006.201.16:08:13.73#ibcon#wrote, iclass 28, count 2 2006.201.16:08:13.73#ibcon#about to read 3, iclass 28, count 2 2006.201.16:08:13.75#ibcon#read 3, iclass 28, count 2 2006.201.16:08:13.75#ibcon#about to read 4, iclass 28, count 2 2006.201.16:08:13.75#ibcon#read 4, iclass 28, count 2 2006.201.16:08:13.75#ibcon#about to read 5, iclass 28, count 2 2006.201.16:08:13.75#ibcon#read 5, iclass 28, count 2 2006.201.16:08:13.75#ibcon#about to read 6, iclass 28, count 2 2006.201.16:08:13.75#ibcon#read 6, iclass 28, count 2 2006.201.16:08:13.75#ibcon#end of sib2, iclass 28, count 2 2006.201.16:08:13.75#ibcon#*mode == 0, iclass 28, count 2 2006.201.16:08:13.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.16:08:13.75#ibcon#[25=AT08-04\r\n] 2006.201.16:08:13.75#ibcon#*before write, iclass 28, count 2 2006.201.16:08:13.75#ibcon#enter sib2, iclass 28, count 2 2006.201.16:08:13.75#ibcon#flushed, iclass 28, count 2 2006.201.16:08:13.75#ibcon#about to write, iclass 28, count 2 2006.201.16:08:13.75#ibcon#wrote, iclass 28, count 2 2006.201.16:08:13.75#ibcon#about to read 3, iclass 28, count 2 2006.201.16:08:13.78#ibcon#read 3, iclass 28, count 2 2006.201.16:08:13.78#ibcon#about to read 4, iclass 28, count 2 2006.201.16:08:13.78#ibcon#read 4, iclass 28, count 2 2006.201.16:08:13.78#ibcon#about to read 5, iclass 28, count 2 2006.201.16:08:13.78#ibcon#read 5, iclass 28, count 2 2006.201.16:08:13.78#ibcon#about to read 6, iclass 28, count 2 2006.201.16:08:13.78#ibcon#read 6, iclass 28, count 2 2006.201.16:08:13.78#ibcon#end of sib2, iclass 28, count 2 2006.201.16:08:13.78#ibcon#*after write, iclass 28, count 2 2006.201.16:08:13.78#ibcon#*before return 0, iclass 28, count 2 2006.201.16:08:13.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:08:13.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:08:13.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.16:08:13.78#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:13.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:08:13.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:08:13.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:08:13.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:08:13.90#ibcon#first serial, iclass 28, count 0 2006.201.16:08:13.90#ibcon#enter sib2, iclass 28, count 0 2006.201.16:08:13.90#ibcon#flushed, iclass 28, count 0 2006.201.16:08:13.90#ibcon#about to write, iclass 28, count 0 2006.201.16:08:13.90#ibcon#wrote, iclass 28, count 0 2006.201.16:08:13.90#ibcon#about to read 3, iclass 28, count 0 2006.201.16:08:13.92#ibcon#read 3, iclass 28, count 0 2006.201.16:08:13.92#ibcon#about to read 4, iclass 28, count 0 2006.201.16:08:13.92#ibcon#read 4, iclass 28, count 0 2006.201.16:08:13.92#ibcon#about to read 5, iclass 28, count 0 2006.201.16:08:13.92#ibcon#read 5, iclass 28, count 0 2006.201.16:08:13.92#ibcon#about to read 6, iclass 28, count 0 2006.201.16:08:13.92#ibcon#read 6, iclass 28, count 0 2006.201.16:08:13.92#ibcon#end of sib2, iclass 28, count 0 2006.201.16:08:13.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:08:13.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:08:13.92#ibcon#[25=USB\r\n] 2006.201.16:08:13.92#ibcon#*before write, iclass 28, count 0 2006.201.16:08:13.92#ibcon#enter sib2, iclass 28, count 0 2006.201.16:08:13.92#ibcon#flushed, iclass 28, count 0 2006.201.16:08:13.92#ibcon#about to write, iclass 28, count 0 2006.201.16:08:13.92#ibcon#wrote, iclass 28, count 0 2006.201.16:08:13.92#ibcon#about to read 3, iclass 28, count 0 2006.201.16:08:13.95#ibcon#read 3, iclass 28, count 0 2006.201.16:08:13.95#ibcon#about to read 4, iclass 28, count 0 2006.201.16:08:13.95#ibcon#read 4, iclass 28, count 0 2006.201.16:08:13.95#ibcon#about to read 5, iclass 28, count 0 2006.201.16:08:13.95#ibcon#read 5, iclass 28, count 0 2006.201.16:08:13.95#ibcon#about to read 6, iclass 28, count 0 2006.201.16:08:13.95#ibcon#read 6, iclass 28, count 0 2006.201.16:08:13.95#ibcon#end of sib2, iclass 28, count 0 2006.201.16:08:13.95#ibcon#*after write, iclass 28, count 0 2006.201.16:08:13.95#ibcon#*before return 0, iclass 28, count 0 2006.201.16:08:13.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:08:13.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:08:13.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:08:13.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:08:13.95$vck44/vblo=1,629.99 2006.201.16:08:13.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.16:08:13.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.16:08:13.95#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:13.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:08:13.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:08:13.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:08:13.95#ibcon#enter wrdev, iclass 30, count 0 2006.201.16:08:13.95#ibcon#first serial, iclass 30, count 0 2006.201.16:08:13.95#ibcon#enter sib2, iclass 30, count 0 2006.201.16:08:13.95#ibcon#flushed, iclass 30, count 0 2006.201.16:08:13.95#ibcon#about to write, iclass 30, count 0 2006.201.16:08:13.95#ibcon#wrote, iclass 30, count 0 2006.201.16:08:13.95#ibcon#about to read 3, iclass 30, count 0 2006.201.16:08:13.97#ibcon#read 3, iclass 30, count 0 2006.201.16:08:13.97#ibcon#about to read 4, iclass 30, count 0 2006.201.16:08:13.97#ibcon#read 4, iclass 30, count 0 2006.201.16:08:13.97#ibcon#about to read 5, iclass 30, count 0 2006.201.16:08:13.97#ibcon#read 5, iclass 30, count 0 2006.201.16:08:13.97#ibcon#about to read 6, iclass 30, count 0 2006.201.16:08:13.97#ibcon#read 6, iclass 30, count 0 2006.201.16:08:13.97#ibcon#end of sib2, iclass 30, count 0 2006.201.16:08:13.97#ibcon#*mode == 0, iclass 30, count 0 2006.201.16:08:13.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.16:08:13.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:08:13.97#ibcon#*before write, iclass 30, count 0 2006.201.16:08:13.97#ibcon#enter sib2, iclass 30, count 0 2006.201.16:08:13.97#ibcon#flushed, iclass 30, count 0 2006.201.16:08:13.97#ibcon#about to write, iclass 30, count 0 2006.201.16:08:13.97#ibcon#wrote, iclass 30, count 0 2006.201.16:08:13.97#ibcon#about to read 3, iclass 30, count 0 2006.201.16:08:14.01#ibcon#read 3, iclass 30, count 0 2006.201.16:08:14.01#ibcon#about to read 4, iclass 30, count 0 2006.201.16:08:14.01#ibcon#read 4, iclass 30, count 0 2006.201.16:08:14.01#ibcon#about to read 5, iclass 30, count 0 2006.201.16:08:14.01#ibcon#read 5, iclass 30, count 0 2006.201.16:08:14.01#ibcon#about to read 6, iclass 30, count 0 2006.201.16:08:14.01#ibcon#read 6, iclass 30, count 0 2006.201.16:08:14.01#ibcon#end of sib2, iclass 30, count 0 2006.201.16:08:14.01#ibcon#*after write, iclass 30, count 0 2006.201.16:08:14.01#ibcon#*before return 0, iclass 30, count 0 2006.201.16:08:14.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:08:14.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:08:14.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.16:08:14.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.16:08:14.01$vck44/vb=1,4 2006.201.16:08:14.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.16:08:14.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.16:08:14.01#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:14.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:08:14.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:08:14.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:08:14.01#ibcon#enter wrdev, iclass 32, count 2 2006.201.16:08:14.01#ibcon#first serial, iclass 32, count 2 2006.201.16:08:14.01#ibcon#enter sib2, iclass 32, count 2 2006.201.16:08:14.01#ibcon#flushed, iclass 32, count 2 2006.201.16:08:14.01#ibcon#about to write, iclass 32, count 2 2006.201.16:08:14.01#ibcon#wrote, iclass 32, count 2 2006.201.16:08:14.01#ibcon#about to read 3, iclass 32, count 2 2006.201.16:08:14.03#ibcon#read 3, iclass 32, count 2 2006.201.16:08:14.03#ibcon#about to read 4, iclass 32, count 2 2006.201.16:08:14.03#ibcon#read 4, iclass 32, count 2 2006.201.16:08:14.03#ibcon#about to read 5, iclass 32, count 2 2006.201.16:08:14.03#ibcon#read 5, iclass 32, count 2 2006.201.16:08:14.03#ibcon#about to read 6, iclass 32, count 2 2006.201.16:08:14.03#ibcon#read 6, iclass 32, count 2 2006.201.16:08:14.03#ibcon#end of sib2, iclass 32, count 2 2006.201.16:08:14.03#ibcon#*mode == 0, iclass 32, count 2 2006.201.16:08:14.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.16:08:14.03#ibcon#[27=AT01-04\r\n] 2006.201.16:08:14.03#ibcon#*before write, iclass 32, count 2 2006.201.16:08:14.03#ibcon#enter sib2, iclass 32, count 2 2006.201.16:08:14.03#ibcon#flushed, iclass 32, count 2 2006.201.16:08:14.03#ibcon#about to write, iclass 32, count 2 2006.201.16:08:14.03#ibcon#wrote, iclass 32, count 2 2006.201.16:08:14.03#ibcon#about to read 3, iclass 32, count 2 2006.201.16:08:14.06#ibcon#read 3, iclass 32, count 2 2006.201.16:08:14.06#ibcon#about to read 4, iclass 32, count 2 2006.201.16:08:14.06#ibcon#read 4, iclass 32, count 2 2006.201.16:08:14.06#ibcon#about to read 5, iclass 32, count 2 2006.201.16:08:14.06#ibcon#read 5, iclass 32, count 2 2006.201.16:08:14.06#ibcon#about to read 6, iclass 32, count 2 2006.201.16:08:14.06#ibcon#read 6, iclass 32, count 2 2006.201.16:08:14.06#ibcon#end of sib2, iclass 32, count 2 2006.201.16:08:14.06#ibcon#*after write, iclass 32, count 2 2006.201.16:08:14.06#ibcon#*before return 0, iclass 32, count 2 2006.201.16:08:14.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:08:14.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:08:14.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.16:08:14.06#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:14.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:08:14.18#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:08:14.18#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:08:14.18#ibcon#enter wrdev, iclass 32, count 0 2006.201.16:08:14.18#ibcon#first serial, iclass 32, count 0 2006.201.16:08:14.18#ibcon#enter sib2, iclass 32, count 0 2006.201.16:08:14.18#ibcon#flushed, iclass 32, count 0 2006.201.16:08:14.18#ibcon#about to write, iclass 32, count 0 2006.201.16:08:14.18#ibcon#wrote, iclass 32, count 0 2006.201.16:08:14.18#ibcon#about to read 3, iclass 32, count 0 2006.201.16:08:14.20#ibcon#read 3, iclass 32, count 0 2006.201.16:08:14.20#ibcon#about to read 4, iclass 32, count 0 2006.201.16:08:14.20#ibcon#read 4, iclass 32, count 0 2006.201.16:08:14.20#ibcon#about to read 5, iclass 32, count 0 2006.201.16:08:14.20#ibcon#read 5, iclass 32, count 0 2006.201.16:08:14.20#ibcon#about to read 6, iclass 32, count 0 2006.201.16:08:14.20#ibcon#read 6, iclass 32, count 0 2006.201.16:08:14.20#ibcon#end of sib2, iclass 32, count 0 2006.201.16:08:14.20#ibcon#*mode == 0, iclass 32, count 0 2006.201.16:08:14.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.16:08:14.20#ibcon#[27=USB\r\n] 2006.201.16:08:14.20#ibcon#*before write, iclass 32, count 0 2006.201.16:08:14.20#ibcon#enter sib2, iclass 32, count 0 2006.201.16:08:14.20#ibcon#flushed, iclass 32, count 0 2006.201.16:08:14.20#ibcon#about to write, iclass 32, count 0 2006.201.16:08:14.20#ibcon#wrote, iclass 32, count 0 2006.201.16:08:14.20#ibcon#about to read 3, iclass 32, count 0 2006.201.16:08:14.23#ibcon#read 3, iclass 32, count 0 2006.201.16:08:14.23#ibcon#about to read 4, iclass 32, count 0 2006.201.16:08:14.23#ibcon#read 4, iclass 32, count 0 2006.201.16:08:14.23#ibcon#about to read 5, iclass 32, count 0 2006.201.16:08:14.23#ibcon#read 5, iclass 32, count 0 2006.201.16:08:14.23#ibcon#about to read 6, iclass 32, count 0 2006.201.16:08:14.23#ibcon#read 6, iclass 32, count 0 2006.201.16:08:14.23#ibcon#end of sib2, iclass 32, count 0 2006.201.16:08:14.23#ibcon#*after write, iclass 32, count 0 2006.201.16:08:14.23#ibcon#*before return 0, iclass 32, count 0 2006.201.16:08:14.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:08:14.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:08:14.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.16:08:14.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.16:08:14.23$vck44/vblo=2,634.99 2006.201.16:08:14.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.16:08:14.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.16:08:14.23#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:14.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:14.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:14.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:14.23#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:08:14.23#ibcon#first serial, iclass 34, count 0 2006.201.16:08:14.23#ibcon#enter sib2, iclass 34, count 0 2006.201.16:08:14.23#ibcon#flushed, iclass 34, count 0 2006.201.16:08:14.23#ibcon#about to write, iclass 34, count 0 2006.201.16:08:14.23#ibcon#wrote, iclass 34, count 0 2006.201.16:08:14.23#ibcon#about to read 3, iclass 34, count 0 2006.201.16:08:14.25#ibcon#read 3, iclass 34, count 0 2006.201.16:08:14.25#ibcon#about to read 4, iclass 34, count 0 2006.201.16:08:14.25#ibcon#read 4, iclass 34, count 0 2006.201.16:08:14.25#ibcon#about to read 5, iclass 34, count 0 2006.201.16:08:14.25#ibcon#read 5, iclass 34, count 0 2006.201.16:08:14.25#ibcon#about to read 6, iclass 34, count 0 2006.201.16:08:14.25#ibcon#read 6, iclass 34, count 0 2006.201.16:08:14.25#ibcon#end of sib2, iclass 34, count 0 2006.201.16:08:14.25#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:08:14.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:08:14.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:08:14.25#ibcon#*before write, iclass 34, count 0 2006.201.16:08:14.25#ibcon#enter sib2, iclass 34, count 0 2006.201.16:08:14.25#ibcon#flushed, iclass 34, count 0 2006.201.16:08:14.25#ibcon#about to write, iclass 34, count 0 2006.201.16:08:14.25#ibcon#wrote, iclass 34, count 0 2006.201.16:08:14.25#ibcon#about to read 3, iclass 34, count 0 2006.201.16:08:14.29#ibcon#read 3, iclass 34, count 0 2006.201.16:08:14.29#ibcon#about to read 4, iclass 34, count 0 2006.201.16:08:14.29#ibcon#read 4, iclass 34, count 0 2006.201.16:08:14.29#ibcon#about to read 5, iclass 34, count 0 2006.201.16:08:14.29#ibcon#read 5, iclass 34, count 0 2006.201.16:08:14.29#ibcon#about to read 6, iclass 34, count 0 2006.201.16:08:14.29#ibcon#read 6, iclass 34, count 0 2006.201.16:08:14.29#ibcon#end of sib2, iclass 34, count 0 2006.201.16:08:14.29#ibcon#*after write, iclass 34, count 0 2006.201.16:08:14.29#ibcon#*before return 0, iclass 34, count 0 2006.201.16:08:14.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:14.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:08:14.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:08:14.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:08:14.29$vck44/vb=2,5 2006.201.16:08:14.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.16:08:14.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.16:08:14.29#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:14.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:14.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:14.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:14.35#ibcon#enter wrdev, iclass 36, count 2 2006.201.16:08:14.35#ibcon#first serial, iclass 36, count 2 2006.201.16:08:14.35#ibcon#enter sib2, iclass 36, count 2 2006.201.16:08:14.35#ibcon#flushed, iclass 36, count 2 2006.201.16:08:14.35#ibcon#about to write, iclass 36, count 2 2006.201.16:08:14.35#ibcon#wrote, iclass 36, count 2 2006.201.16:08:14.35#ibcon#about to read 3, iclass 36, count 2 2006.201.16:08:14.37#ibcon#read 3, iclass 36, count 2 2006.201.16:08:14.37#ibcon#about to read 4, iclass 36, count 2 2006.201.16:08:14.37#ibcon#read 4, iclass 36, count 2 2006.201.16:08:14.37#ibcon#about to read 5, iclass 36, count 2 2006.201.16:08:14.37#ibcon#read 5, iclass 36, count 2 2006.201.16:08:14.37#ibcon#about to read 6, iclass 36, count 2 2006.201.16:08:14.37#ibcon#read 6, iclass 36, count 2 2006.201.16:08:14.37#ibcon#end of sib2, iclass 36, count 2 2006.201.16:08:14.37#ibcon#*mode == 0, iclass 36, count 2 2006.201.16:08:14.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.16:08:14.37#ibcon#[27=AT02-05\r\n] 2006.201.16:08:14.37#ibcon#*before write, iclass 36, count 2 2006.201.16:08:14.37#ibcon#enter sib2, iclass 36, count 2 2006.201.16:08:14.37#ibcon#flushed, iclass 36, count 2 2006.201.16:08:14.37#ibcon#about to write, iclass 36, count 2 2006.201.16:08:14.37#ibcon#wrote, iclass 36, count 2 2006.201.16:08:14.37#ibcon#about to read 3, iclass 36, count 2 2006.201.16:08:14.40#ibcon#read 3, iclass 36, count 2 2006.201.16:08:14.40#ibcon#about to read 4, iclass 36, count 2 2006.201.16:08:14.40#ibcon#read 4, iclass 36, count 2 2006.201.16:08:14.40#ibcon#about to read 5, iclass 36, count 2 2006.201.16:08:14.40#ibcon#read 5, iclass 36, count 2 2006.201.16:08:14.40#ibcon#about to read 6, iclass 36, count 2 2006.201.16:08:14.40#ibcon#read 6, iclass 36, count 2 2006.201.16:08:14.40#ibcon#end of sib2, iclass 36, count 2 2006.201.16:08:14.40#ibcon#*after write, iclass 36, count 2 2006.201.16:08:14.40#ibcon#*before return 0, iclass 36, count 2 2006.201.16:08:14.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:14.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:08:14.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.16:08:14.40#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:14.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:14.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:14.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:14.52#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:08:14.52#ibcon#first serial, iclass 36, count 0 2006.201.16:08:14.52#ibcon#enter sib2, iclass 36, count 0 2006.201.16:08:14.52#ibcon#flushed, iclass 36, count 0 2006.201.16:08:14.52#ibcon#about to write, iclass 36, count 0 2006.201.16:08:14.52#ibcon#wrote, iclass 36, count 0 2006.201.16:08:14.52#ibcon#about to read 3, iclass 36, count 0 2006.201.16:08:14.54#ibcon#read 3, iclass 36, count 0 2006.201.16:08:14.54#ibcon#about to read 4, iclass 36, count 0 2006.201.16:08:14.54#ibcon#read 4, iclass 36, count 0 2006.201.16:08:14.54#ibcon#about to read 5, iclass 36, count 0 2006.201.16:08:14.54#ibcon#read 5, iclass 36, count 0 2006.201.16:08:14.54#ibcon#about to read 6, iclass 36, count 0 2006.201.16:08:14.54#ibcon#read 6, iclass 36, count 0 2006.201.16:08:14.54#ibcon#end of sib2, iclass 36, count 0 2006.201.16:08:14.54#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:08:14.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:08:14.54#ibcon#[27=USB\r\n] 2006.201.16:08:14.54#ibcon#*before write, iclass 36, count 0 2006.201.16:08:14.54#ibcon#enter sib2, iclass 36, count 0 2006.201.16:08:14.54#ibcon#flushed, iclass 36, count 0 2006.201.16:08:14.54#ibcon#about to write, iclass 36, count 0 2006.201.16:08:14.54#ibcon#wrote, iclass 36, count 0 2006.201.16:08:14.54#ibcon#about to read 3, iclass 36, count 0 2006.201.16:08:14.57#ibcon#read 3, iclass 36, count 0 2006.201.16:08:14.57#ibcon#about to read 4, iclass 36, count 0 2006.201.16:08:14.57#ibcon#read 4, iclass 36, count 0 2006.201.16:08:14.57#ibcon#about to read 5, iclass 36, count 0 2006.201.16:08:14.57#ibcon#read 5, iclass 36, count 0 2006.201.16:08:14.57#ibcon#about to read 6, iclass 36, count 0 2006.201.16:08:14.57#ibcon#read 6, iclass 36, count 0 2006.201.16:08:14.57#ibcon#end of sib2, iclass 36, count 0 2006.201.16:08:14.57#ibcon#*after write, iclass 36, count 0 2006.201.16:08:14.57#ibcon#*before return 0, iclass 36, count 0 2006.201.16:08:14.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:14.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:08:14.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:08:14.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:08:14.57$vck44/vblo=3,649.99 2006.201.16:08:14.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.16:08:14.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.16:08:14.57#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:14.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:14.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:14.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:14.57#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:08:14.57#ibcon#first serial, iclass 38, count 0 2006.201.16:08:14.57#ibcon#enter sib2, iclass 38, count 0 2006.201.16:08:14.57#ibcon#flushed, iclass 38, count 0 2006.201.16:08:14.57#ibcon#about to write, iclass 38, count 0 2006.201.16:08:14.57#ibcon#wrote, iclass 38, count 0 2006.201.16:08:14.57#ibcon#about to read 3, iclass 38, count 0 2006.201.16:08:14.59#ibcon#read 3, iclass 38, count 0 2006.201.16:08:14.59#ibcon#about to read 4, iclass 38, count 0 2006.201.16:08:14.59#ibcon#read 4, iclass 38, count 0 2006.201.16:08:14.59#ibcon#about to read 5, iclass 38, count 0 2006.201.16:08:14.59#ibcon#read 5, iclass 38, count 0 2006.201.16:08:14.59#ibcon#about to read 6, iclass 38, count 0 2006.201.16:08:14.59#ibcon#read 6, iclass 38, count 0 2006.201.16:08:14.59#ibcon#end of sib2, iclass 38, count 0 2006.201.16:08:14.59#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:08:14.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:08:14.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:08:14.59#ibcon#*before write, iclass 38, count 0 2006.201.16:08:14.59#ibcon#enter sib2, iclass 38, count 0 2006.201.16:08:14.59#ibcon#flushed, iclass 38, count 0 2006.201.16:08:14.59#ibcon#about to write, iclass 38, count 0 2006.201.16:08:14.59#ibcon#wrote, iclass 38, count 0 2006.201.16:08:14.59#ibcon#about to read 3, iclass 38, count 0 2006.201.16:08:14.64#ibcon#read 3, iclass 38, count 0 2006.201.16:08:14.64#ibcon#about to read 4, iclass 38, count 0 2006.201.16:08:14.64#ibcon#read 4, iclass 38, count 0 2006.201.16:08:14.64#ibcon#about to read 5, iclass 38, count 0 2006.201.16:08:14.64#ibcon#read 5, iclass 38, count 0 2006.201.16:08:14.64#ibcon#about to read 6, iclass 38, count 0 2006.201.16:08:14.64#ibcon#read 6, iclass 38, count 0 2006.201.16:08:14.64#ibcon#end of sib2, iclass 38, count 0 2006.201.16:08:14.64#ibcon#*after write, iclass 38, count 0 2006.201.16:08:14.64#ibcon#*before return 0, iclass 38, count 0 2006.201.16:08:14.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:14.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:08:14.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:08:14.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:08:14.64$vck44/vb=3,4 2006.201.16:08:14.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.16:08:14.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.16:08:14.64#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:14.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:14.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:14.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:14.69#ibcon#enter wrdev, iclass 40, count 2 2006.201.16:08:14.69#ibcon#first serial, iclass 40, count 2 2006.201.16:08:14.69#ibcon#enter sib2, iclass 40, count 2 2006.201.16:08:14.69#ibcon#flushed, iclass 40, count 2 2006.201.16:08:14.69#ibcon#about to write, iclass 40, count 2 2006.201.16:08:14.69#ibcon#wrote, iclass 40, count 2 2006.201.16:08:14.69#ibcon#about to read 3, iclass 40, count 2 2006.201.16:08:14.71#ibcon#read 3, iclass 40, count 2 2006.201.16:08:14.71#ibcon#about to read 4, iclass 40, count 2 2006.201.16:08:14.71#ibcon#read 4, iclass 40, count 2 2006.201.16:08:14.71#ibcon#about to read 5, iclass 40, count 2 2006.201.16:08:14.71#ibcon#read 5, iclass 40, count 2 2006.201.16:08:14.71#ibcon#about to read 6, iclass 40, count 2 2006.201.16:08:14.71#ibcon#read 6, iclass 40, count 2 2006.201.16:08:14.71#ibcon#end of sib2, iclass 40, count 2 2006.201.16:08:14.71#ibcon#*mode == 0, iclass 40, count 2 2006.201.16:08:14.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.16:08:14.71#ibcon#[27=AT03-04\r\n] 2006.201.16:08:14.71#ibcon#*before write, iclass 40, count 2 2006.201.16:08:14.71#ibcon#enter sib2, iclass 40, count 2 2006.201.16:08:14.71#ibcon#flushed, iclass 40, count 2 2006.201.16:08:14.71#ibcon#about to write, iclass 40, count 2 2006.201.16:08:14.71#ibcon#wrote, iclass 40, count 2 2006.201.16:08:14.71#ibcon#about to read 3, iclass 40, count 2 2006.201.16:08:14.74#ibcon#read 3, iclass 40, count 2 2006.201.16:08:14.74#ibcon#about to read 4, iclass 40, count 2 2006.201.16:08:14.74#ibcon#read 4, iclass 40, count 2 2006.201.16:08:14.74#ibcon#about to read 5, iclass 40, count 2 2006.201.16:08:14.74#ibcon#read 5, iclass 40, count 2 2006.201.16:08:14.74#ibcon#about to read 6, iclass 40, count 2 2006.201.16:08:14.74#ibcon#read 6, iclass 40, count 2 2006.201.16:08:14.74#ibcon#end of sib2, iclass 40, count 2 2006.201.16:08:14.74#ibcon#*after write, iclass 40, count 2 2006.201.16:08:14.74#ibcon#*before return 0, iclass 40, count 2 2006.201.16:08:14.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:14.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:08:14.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.16:08:14.74#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:14.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:14.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:14.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:14.86#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:08:14.86#ibcon#first serial, iclass 40, count 0 2006.201.16:08:14.86#ibcon#enter sib2, iclass 40, count 0 2006.201.16:08:14.86#ibcon#flushed, iclass 40, count 0 2006.201.16:08:14.86#ibcon#about to write, iclass 40, count 0 2006.201.16:08:14.86#ibcon#wrote, iclass 40, count 0 2006.201.16:08:14.86#ibcon#about to read 3, iclass 40, count 0 2006.201.16:08:14.88#ibcon#read 3, iclass 40, count 0 2006.201.16:08:14.88#ibcon#about to read 4, iclass 40, count 0 2006.201.16:08:14.88#ibcon#read 4, iclass 40, count 0 2006.201.16:08:14.88#ibcon#about to read 5, iclass 40, count 0 2006.201.16:08:14.88#ibcon#read 5, iclass 40, count 0 2006.201.16:08:14.88#ibcon#about to read 6, iclass 40, count 0 2006.201.16:08:14.88#ibcon#read 6, iclass 40, count 0 2006.201.16:08:14.88#ibcon#end of sib2, iclass 40, count 0 2006.201.16:08:14.88#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:08:14.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:08:14.88#ibcon#[27=USB\r\n] 2006.201.16:08:14.88#ibcon#*before write, iclass 40, count 0 2006.201.16:08:14.88#ibcon#enter sib2, iclass 40, count 0 2006.201.16:08:14.88#ibcon#flushed, iclass 40, count 0 2006.201.16:08:14.88#ibcon#about to write, iclass 40, count 0 2006.201.16:08:14.88#ibcon#wrote, iclass 40, count 0 2006.201.16:08:14.88#ibcon#about to read 3, iclass 40, count 0 2006.201.16:08:14.91#ibcon#read 3, iclass 40, count 0 2006.201.16:08:14.91#ibcon#about to read 4, iclass 40, count 0 2006.201.16:08:14.91#ibcon#read 4, iclass 40, count 0 2006.201.16:08:14.91#ibcon#about to read 5, iclass 40, count 0 2006.201.16:08:14.91#ibcon#read 5, iclass 40, count 0 2006.201.16:08:14.91#ibcon#about to read 6, iclass 40, count 0 2006.201.16:08:14.91#ibcon#read 6, iclass 40, count 0 2006.201.16:08:14.91#ibcon#end of sib2, iclass 40, count 0 2006.201.16:08:14.91#ibcon#*after write, iclass 40, count 0 2006.201.16:08:14.91#ibcon#*before return 0, iclass 40, count 0 2006.201.16:08:14.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:14.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:08:14.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:08:14.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:08:14.91$vck44/vblo=4,679.99 2006.201.16:08:14.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.16:08:14.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.16:08:14.91#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:14.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:14.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:14.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:14.91#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:08:14.91#ibcon#first serial, iclass 4, count 0 2006.201.16:08:14.91#ibcon#enter sib2, iclass 4, count 0 2006.201.16:08:14.91#ibcon#flushed, iclass 4, count 0 2006.201.16:08:14.91#ibcon#about to write, iclass 4, count 0 2006.201.16:08:14.91#ibcon#wrote, iclass 4, count 0 2006.201.16:08:14.91#ibcon#about to read 3, iclass 4, count 0 2006.201.16:08:14.93#ibcon#read 3, iclass 4, count 0 2006.201.16:08:14.93#ibcon#about to read 4, iclass 4, count 0 2006.201.16:08:14.93#ibcon#read 4, iclass 4, count 0 2006.201.16:08:14.93#ibcon#about to read 5, iclass 4, count 0 2006.201.16:08:14.93#ibcon#read 5, iclass 4, count 0 2006.201.16:08:14.93#ibcon#about to read 6, iclass 4, count 0 2006.201.16:08:14.93#ibcon#read 6, iclass 4, count 0 2006.201.16:08:14.93#ibcon#end of sib2, iclass 4, count 0 2006.201.16:08:14.93#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:08:14.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:08:14.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:08:14.93#ibcon#*before write, iclass 4, count 0 2006.201.16:08:14.93#ibcon#enter sib2, iclass 4, count 0 2006.201.16:08:14.93#ibcon#flushed, iclass 4, count 0 2006.201.16:08:14.93#ibcon#about to write, iclass 4, count 0 2006.201.16:08:14.93#ibcon#wrote, iclass 4, count 0 2006.201.16:08:14.93#ibcon#about to read 3, iclass 4, count 0 2006.201.16:08:14.97#ibcon#read 3, iclass 4, count 0 2006.201.16:08:14.97#ibcon#about to read 4, iclass 4, count 0 2006.201.16:08:14.97#ibcon#read 4, iclass 4, count 0 2006.201.16:08:14.97#ibcon#about to read 5, iclass 4, count 0 2006.201.16:08:14.97#ibcon#read 5, iclass 4, count 0 2006.201.16:08:14.97#ibcon#about to read 6, iclass 4, count 0 2006.201.16:08:14.97#ibcon#read 6, iclass 4, count 0 2006.201.16:08:14.97#ibcon#end of sib2, iclass 4, count 0 2006.201.16:08:14.97#ibcon#*after write, iclass 4, count 0 2006.201.16:08:14.97#ibcon#*before return 0, iclass 4, count 0 2006.201.16:08:14.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:14.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:08:14.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:08:14.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:08:14.97$vck44/vb=4,5 2006.201.16:08:14.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.16:08:14.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.16:08:14.97#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:14.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:15.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:15.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:15.03#ibcon#enter wrdev, iclass 6, count 2 2006.201.16:08:15.03#ibcon#first serial, iclass 6, count 2 2006.201.16:08:15.03#ibcon#enter sib2, iclass 6, count 2 2006.201.16:08:15.03#ibcon#flushed, iclass 6, count 2 2006.201.16:08:15.03#ibcon#about to write, iclass 6, count 2 2006.201.16:08:15.03#ibcon#wrote, iclass 6, count 2 2006.201.16:08:15.03#ibcon#about to read 3, iclass 6, count 2 2006.201.16:08:15.05#ibcon#read 3, iclass 6, count 2 2006.201.16:08:15.05#ibcon#about to read 4, iclass 6, count 2 2006.201.16:08:15.05#ibcon#read 4, iclass 6, count 2 2006.201.16:08:15.05#ibcon#about to read 5, iclass 6, count 2 2006.201.16:08:15.05#ibcon#read 5, iclass 6, count 2 2006.201.16:08:15.05#ibcon#about to read 6, iclass 6, count 2 2006.201.16:08:15.05#ibcon#read 6, iclass 6, count 2 2006.201.16:08:15.05#ibcon#end of sib2, iclass 6, count 2 2006.201.16:08:15.05#ibcon#*mode == 0, iclass 6, count 2 2006.201.16:08:15.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.16:08:15.05#ibcon#[27=AT04-05\r\n] 2006.201.16:08:15.05#ibcon#*before write, iclass 6, count 2 2006.201.16:08:15.05#ibcon#enter sib2, iclass 6, count 2 2006.201.16:08:15.05#ibcon#flushed, iclass 6, count 2 2006.201.16:08:15.05#ibcon#about to write, iclass 6, count 2 2006.201.16:08:15.05#ibcon#wrote, iclass 6, count 2 2006.201.16:08:15.05#ibcon#about to read 3, iclass 6, count 2 2006.201.16:08:15.08#ibcon#read 3, iclass 6, count 2 2006.201.16:08:15.08#ibcon#about to read 4, iclass 6, count 2 2006.201.16:08:15.08#ibcon#read 4, iclass 6, count 2 2006.201.16:08:15.08#ibcon#about to read 5, iclass 6, count 2 2006.201.16:08:15.08#ibcon#read 5, iclass 6, count 2 2006.201.16:08:15.08#ibcon#about to read 6, iclass 6, count 2 2006.201.16:08:15.08#ibcon#read 6, iclass 6, count 2 2006.201.16:08:15.08#ibcon#end of sib2, iclass 6, count 2 2006.201.16:08:15.08#ibcon#*after write, iclass 6, count 2 2006.201.16:08:15.08#ibcon#*before return 0, iclass 6, count 2 2006.201.16:08:15.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:15.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:08:15.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.16:08:15.08#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:15.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:15.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:15.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:15.20#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:08:15.20#ibcon#first serial, iclass 6, count 0 2006.201.16:08:15.20#ibcon#enter sib2, iclass 6, count 0 2006.201.16:08:15.20#ibcon#flushed, iclass 6, count 0 2006.201.16:08:15.20#ibcon#about to write, iclass 6, count 0 2006.201.16:08:15.20#ibcon#wrote, iclass 6, count 0 2006.201.16:08:15.20#ibcon#about to read 3, iclass 6, count 0 2006.201.16:08:15.22#ibcon#read 3, iclass 6, count 0 2006.201.16:08:15.22#ibcon#about to read 4, iclass 6, count 0 2006.201.16:08:15.22#ibcon#read 4, iclass 6, count 0 2006.201.16:08:15.22#ibcon#about to read 5, iclass 6, count 0 2006.201.16:08:15.22#ibcon#read 5, iclass 6, count 0 2006.201.16:08:15.22#ibcon#about to read 6, iclass 6, count 0 2006.201.16:08:15.22#ibcon#read 6, iclass 6, count 0 2006.201.16:08:15.22#ibcon#end of sib2, iclass 6, count 0 2006.201.16:08:15.22#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:08:15.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:08:15.22#ibcon#[27=USB\r\n] 2006.201.16:08:15.22#ibcon#*before write, iclass 6, count 0 2006.201.16:08:15.22#ibcon#enter sib2, iclass 6, count 0 2006.201.16:08:15.22#ibcon#flushed, iclass 6, count 0 2006.201.16:08:15.22#ibcon#about to write, iclass 6, count 0 2006.201.16:08:15.22#ibcon#wrote, iclass 6, count 0 2006.201.16:08:15.22#ibcon#about to read 3, iclass 6, count 0 2006.201.16:08:15.25#ibcon#read 3, iclass 6, count 0 2006.201.16:08:15.25#ibcon#about to read 4, iclass 6, count 0 2006.201.16:08:15.25#ibcon#read 4, iclass 6, count 0 2006.201.16:08:15.25#ibcon#about to read 5, iclass 6, count 0 2006.201.16:08:15.25#ibcon#read 5, iclass 6, count 0 2006.201.16:08:15.25#ibcon#about to read 6, iclass 6, count 0 2006.201.16:08:15.25#ibcon#read 6, iclass 6, count 0 2006.201.16:08:15.25#ibcon#end of sib2, iclass 6, count 0 2006.201.16:08:15.25#ibcon#*after write, iclass 6, count 0 2006.201.16:08:15.25#ibcon#*before return 0, iclass 6, count 0 2006.201.16:08:15.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:15.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:08:15.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:08:15.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:08:15.25$vck44/vblo=5,709.99 2006.201.16:08:15.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.16:08:15.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.16:08:15.25#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:15.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:15.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:15.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:15.25#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:08:15.25#ibcon#first serial, iclass 10, count 0 2006.201.16:08:15.25#ibcon#enter sib2, iclass 10, count 0 2006.201.16:08:15.25#ibcon#flushed, iclass 10, count 0 2006.201.16:08:15.25#ibcon#about to write, iclass 10, count 0 2006.201.16:08:15.25#ibcon#wrote, iclass 10, count 0 2006.201.16:08:15.25#ibcon#about to read 3, iclass 10, count 0 2006.201.16:08:15.27#ibcon#read 3, iclass 10, count 0 2006.201.16:08:15.27#ibcon#about to read 4, iclass 10, count 0 2006.201.16:08:15.27#ibcon#read 4, iclass 10, count 0 2006.201.16:08:15.27#ibcon#about to read 5, iclass 10, count 0 2006.201.16:08:15.27#ibcon#read 5, iclass 10, count 0 2006.201.16:08:15.27#ibcon#about to read 6, iclass 10, count 0 2006.201.16:08:15.27#ibcon#read 6, iclass 10, count 0 2006.201.16:08:15.27#ibcon#end of sib2, iclass 10, count 0 2006.201.16:08:15.27#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:08:15.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:08:15.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:08:15.27#ibcon#*before write, iclass 10, count 0 2006.201.16:08:15.27#ibcon#enter sib2, iclass 10, count 0 2006.201.16:08:15.27#ibcon#flushed, iclass 10, count 0 2006.201.16:08:15.27#ibcon#about to write, iclass 10, count 0 2006.201.16:08:15.27#ibcon#wrote, iclass 10, count 0 2006.201.16:08:15.27#ibcon#about to read 3, iclass 10, count 0 2006.201.16:08:15.31#ibcon#read 3, iclass 10, count 0 2006.201.16:08:15.31#ibcon#about to read 4, iclass 10, count 0 2006.201.16:08:15.31#ibcon#read 4, iclass 10, count 0 2006.201.16:08:15.31#ibcon#about to read 5, iclass 10, count 0 2006.201.16:08:15.31#ibcon#read 5, iclass 10, count 0 2006.201.16:08:15.31#ibcon#about to read 6, iclass 10, count 0 2006.201.16:08:15.31#ibcon#read 6, iclass 10, count 0 2006.201.16:08:15.31#ibcon#end of sib2, iclass 10, count 0 2006.201.16:08:15.31#ibcon#*after write, iclass 10, count 0 2006.201.16:08:15.31#ibcon#*before return 0, iclass 10, count 0 2006.201.16:08:15.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:15.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:08:15.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:08:15.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:08:15.31$vck44/vb=5,4 2006.201.16:08:15.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.16:08:15.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.16:08:15.31#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:15.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:15.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:15.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:15.37#ibcon#enter wrdev, iclass 12, count 2 2006.201.16:08:15.37#ibcon#first serial, iclass 12, count 2 2006.201.16:08:15.37#ibcon#enter sib2, iclass 12, count 2 2006.201.16:08:15.37#ibcon#flushed, iclass 12, count 2 2006.201.16:08:15.37#ibcon#about to write, iclass 12, count 2 2006.201.16:08:15.37#ibcon#wrote, iclass 12, count 2 2006.201.16:08:15.37#ibcon#about to read 3, iclass 12, count 2 2006.201.16:08:15.39#ibcon#read 3, iclass 12, count 2 2006.201.16:08:15.39#ibcon#about to read 4, iclass 12, count 2 2006.201.16:08:15.39#ibcon#read 4, iclass 12, count 2 2006.201.16:08:15.39#ibcon#about to read 5, iclass 12, count 2 2006.201.16:08:15.39#ibcon#read 5, iclass 12, count 2 2006.201.16:08:15.39#ibcon#about to read 6, iclass 12, count 2 2006.201.16:08:15.39#ibcon#read 6, iclass 12, count 2 2006.201.16:08:15.39#ibcon#end of sib2, iclass 12, count 2 2006.201.16:08:15.39#ibcon#*mode == 0, iclass 12, count 2 2006.201.16:08:15.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.16:08:15.39#ibcon#[27=AT05-04\r\n] 2006.201.16:08:15.39#ibcon#*before write, iclass 12, count 2 2006.201.16:08:15.39#ibcon#enter sib2, iclass 12, count 2 2006.201.16:08:15.39#ibcon#flushed, iclass 12, count 2 2006.201.16:08:15.39#ibcon#about to write, iclass 12, count 2 2006.201.16:08:15.39#ibcon#wrote, iclass 12, count 2 2006.201.16:08:15.39#ibcon#about to read 3, iclass 12, count 2 2006.201.16:08:15.42#ibcon#read 3, iclass 12, count 2 2006.201.16:08:15.42#ibcon#about to read 4, iclass 12, count 2 2006.201.16:08:15.42#ibcon#read 4, iclass 12, count 2 2006.201.16:08:15.42#ibcon#about to read 5, iclass 12, count 2 2006.201.16:08:15.42#ibcon#read 5, iclass 12, count 2 2006.201.16:08:15.42#ibcon#about to read 6, iclass 12, count 2 2006.201.16:08:15.42#ibcon#read 6, iclass 12, count 2 2006.201.16:08:15.42#ibcon#end of sib2, iclass 12, count 2 2006.201.16:08:15.42#ibcon#*after write, iclass 12, count 2 2006.201.16:08:15.42#ibcon#*before return 0, iclass 12, count 2 2006.201.16:08:15.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:15.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:08:15.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.16:08:15.42#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:15.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:15.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:15.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:15.54#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:08:15.54#ibcon#first serial, iclass 12, count 0 2006.201.16:08:15.54#ibcon#enter sib2, iclass 12, count 0 2006.201.16:08:15.54#ibcon#flushed, iclass 12, count 0 2006.201.16:08:15.54#ibcon#about to write, iclass 12, count 0 2006.201.16:08:15.54#ibcon#wrote, iclass 12, count 0 2006.201.16:08:15.54#ibcon#about to read 3, iclass 12, count 0 2006.201.16:08:15.56#ibcon#read 3, iclass 12, count 0 2006.201.16:08:15.56#ibcon#about to read 4, iclass 12, count 0 2006.201.16:08:15.56#ibcon#read 4, iclass 12, count 0 2006.201.16:08:15.56#ibcon#about to read 5, iclass 12, count 0 2006.201.16:08:15.56#ibcon#read 5, iclass 12, count 0 2006.201.16:08:15.56#ibcon#about to read 6, iclass 12, count 0 2006.201.16:08:15.56#ibcon#read 6, iclass 12, count 0 2006.201.16:08:15.56#ibcon#end of sib2, iclass 12, count 0 2006.201.16:08:15.56#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:08:15.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:08:15.56#ibcon#[27=USB\r\n] 2006.201.16:08:15.56#ibcon#*before write, iclass 12, count 0 2006.201.16:08:15.56#ibcon#enter sib2, iclass 12, count 0 2006.201.16:08:15.56#ibcon#flushed, iclass 12, count 0 2006.201.16:08:15.56#ibcon#about to write, iclass 12, count 0 2006.201.16:08:15.56#ibcon#wrote, iclass 12, count 0 2006.201.16:08:15.56#ibcon#about to read 3, iclass 12, count 0 2006.201.16:08:15.59#ibcon#read 3, iclass 12, count 0 2006.201.16:08:15.59#ibcon#about to read 4, iclass 12, count 0 2006.201.16:08:15.59#ibcon#read 4, iclass 12, count 0 2006.201.16:08:15.59#ibcon#about to read 5, iclass 12, count 0 2006.201.16:08:15.59#ibcon#read 5, iclass 12, count 0 2006.201.16:08:15.59#ibcon#about to read 6, iclass 12, count 0 2006.201.16:08:15.59#ibcon#read 6, iclass 12, count 0 2006.201.16:08:15.59#ibcon#end of sib2, iclass 12, count 0 2006.201.16:08:15.59#ibcon#*after write, iclass 12, count 0 2006.201.16:08:15.59#ibcon#*before return 0, iclass 12, count 0 2006.201.16:08:15.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:15.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:08:15.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:08:15.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:08:15.59$vck44/vblo=6,719.99 2006.201.16:08:15.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.16:08:15.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.16:08:15.59#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:15.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:15.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:15.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:15.59#ibcon#enter wrdev, iclass 14, count 0 2006.201.16:08:15.59#ibcon#first serial, iclass 14, count 0 2006.201.16:08:15.59#ibcon#enter sib2, iclass 14, count 0 2006.201.16:08:15.59#ibcon#flushed, iclass 14, count 0 2006.201.16:08:15.59#ibcon#about to write, iclass 14, count 0 2006.201.16:08:15.59#ibcon#wrote, iclass 14, count 0 2006.201.16:08:15.59#ibcon#about to read 3, iclass 14, count 0 2006.201.16:08:15.61#ibcon#read 3, iclass 14, count 0 2006.201.16:08:15.61#ibcon#about to read 4, iclass 14, count 0 2006.201.16:08:15.61#ibcon#read 4, iclass 14, count 0 2006.201.16:08:15.61#ibcon#about to read 5, iclass 14, count 0 2006.201.16:08:15.61#ibcon#read 5, iclass 14, count 0 2006.201.16:08:15.61#ibcon#about to read 6, iclass 14, count 0 2006.201.16:08:15.61#ibcon#read 6, iclass 14, count 0 2006.201.16:08:15.61#ibcon#end of sib2, iclass 14, count 0 2006.201.16:08:15.61#ibcon#*mode == 0, iclass 14, count 0 2006.201.16:08:15.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.16:08:15.61#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:08:15.61#ibcon#*before write, iclass 14, count 0 2006.201.16:08:15.61#ibcon#enter sib2, iclass 14, count 0 2006.201.16:08:15.61#ibcon#flushed, iclass 14, count 0 2006.201.16:08:15.61#ibcon#about to write, iclass 14, count 0 2006.201.16:08:15.61#ibcon#wrote, iclass 14, count 0 2006.201.16:08:15.61#ibcon#about to read 3, iclass 14, count 0 2006.201.16:08:15.65#ibcon#read 3, iclass 14, count 0 2006.201.16:08:15.65#ibcon#about to read 4, iclass 14, count 0 2006.201.16:08:15.65#ibcon#read 4, iclass 14, count 0 2006.201.16:08:15.65#ibcon#about to read 5, iclass 14, count 0 2006.201.16:08:15.65#ibcon#read 5, iclass 14, count 0 2006.201.16:08:15.65#ibcon#about to read 6, iclass 14, count 0 2006.201.16:08:15.65#ibcon#read 6, iclass 14, count 0 2006.201.16:08:15.65#ibcon#end of sib2, iclass 14, count 0 2006.201.16:08:15.65#ibcon#*after write, iclass 14, count 0 2006.201.16:08:15.65#ibcon#*before return 0, iclass 14, count 0 2006.201.16:08:15.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:15.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:08:15.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.16:08:15.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.16:08:15.65$vck44/vb=6,4 2006.201.16:08:15.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.16:08:15.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.16:08:15.65#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:15.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:15.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:15.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:15.71#ibcon#enter wrdev, iclass 16, count 2 2006.201.16:08:15.71#ibcon#first serial, iclass 16, count 2 2006.201.16:08:15.71#ibcon#enter sib2, iclass 16, count 2 2006.201.16:08:15.71#ibcon#flushed, iclass 16, count 2 2006.201.16:08:15.71#ibcon#about to write, iclass 16, count 2 2006.201.16:08:15.71#ibcon#wrote, iclass 16, count 2 2006.201.16:08:15.71#ibcon#about to read 3, iclass 16, count 2 2006.201.16:08:15.73#ibcon#read 3, iclass 16, count 2 2006.201.16:08:15.73#ibcon#about to read 4, iclass 16, count 2 2006.201.16:08:15.73#ibcon#read 4, iclass 16, count 2 2006.201.16:08:15.73#ibcon#about to read 5, iclass 16, count 2 2006.201.16:08:15.73#ibcon#read 5, iclass 16, count 2 2006.201.16:08:15.73#ibcon#about to read 6, iclass 16, count 2 2006.201.16:08:15.73#ibcon#read 6, iclass 16, count 2 2006.201.16:08:15.73#ibcon#end of sib2, iclass 16, count 2 2006.201.16:08:15.73#ibcon#*mode == 0, iclass 16, count 2 2006.201.16:08:15.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.16:08:15.73#ibcon#[27=AT06-04\r\n] 2006.201.16:08:15.73#ibcon#*before write, iclass 16, count 2 2006.201.16:08:15.73#ibcon#enter sib2, iclass 16, count 2 2006.201.16:08:15.73#ibcon#flushed, iclass 16, count 2 2006.201.16:08:15.73#ibcon#about to write, iclass 16, count 2 2006.201.16:08:15.73#ibcon#wrote, iclass 16, count 2 2006.201.16:08:15.73#ibcon#about to read 3, iclass 16, count 2 2006.201.16:08:15.76#ibcon#read 3, iclass 16, count 2 2006.201.16:08:15.76#ibcon#about to read 4, iclass 16, count 2 2006.201.16:08:15.76#ibcon#read 4, iclass 16, count 2 2006.201.16:08:15.76#ibcon#about to read 5, iclass 16, count 2 2006.201.16:08:15.76#ibcon#read 5, iclass 16, count 2 2006.201.16:08:15.76#ibcon#about to read 6, iclass 16, count 2 2006.201.16:08:15.76#ibcon#read 6, iclass 16, count 2 2006.201.16:08:15.76#ibcon#end of sib2, iclass 16, count 2 2006.201.16:08:15.76#ibcon#*after write, iclass 16, count 2 2006.201.16:08:15.76#ibcon#*before return 0, iclass 16, count 2 2006.201.16:08:15.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:15.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:08:15.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.16:08:15.76#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:15.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:15.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:15.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:15.88#ibcon#enter wrdev, iclass 16, count 0 2006.201.16:08:15.88#ibcon#first serial, iclass 16, count 0 2006.201.16:08:15.88#ibcon#enter sib2, iclass 16, count 0 2006.201.16:08:15.88#ibcon#flushed, iclass 16, count 0 2006.201.16:08:15.88#ibcon#about to write, iclass 16, count 0 2006.201.16:08:15.88#ibcon#wrote, iclass 16, count 0 2006.201.16:08:15.88#ibcon#about to read 3, iclass 16, count 0 2006.201.16:08:15.90#ibcon#read 3, iclass 16, count 0 2006.201.16:08:15.90#ibcon#about to read 4, iclass 16, count 0 2006.201.16:08:15.90#ibcon#read 4, iclass 16, count 0 2006.201.16:08:15.90#ibcon#about to read 5, iclass 16, count 0 2006.201.16:08:15.90#ibcon#read 5, iclass 16, count 0 2006.201.16:08:15.90#ibcon#about to read 6, iclass 16, count 0 2006.201.16:08:15.90#ibcon#read 6, iclass 16, count 0 2006.201.16:08:15.90#ibcon#end of sib2, iclass 16, count 0 2006.201.16:08:15.90#ibcon#*mode == 0, iclass 16, count 0 2006.201.16:08:15.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.16:08:15.90#ibcon#[27=USB\r\n] 2006.201.16:08:15.90#ibcon#*before write, iclass 16, count 0 2006.201.16:08:15.90#ibcon#enter sib2, iclass 16, count 0 2006.201.16:08:15.90#ibcon#flushed, iclass 16, count 0 2006.201.16:08:15.90#ibcon#about to write, iclass 16, count 0 2006.201.16:08:15.90#ibcon#wrote, iclass 16, count 0 2006.201.16:08:15.90#ibcon#about to read 3, iclass 16, count 0 2006.201.16:08:15.93#ibcon#read 3, iclass 16, count 0 2006.201.16:08:15.93#ibcon#about to read 4, iclass 16, count 0 2006.201.16:08:15.93#ibcon#read 4, iclass 16, count 0 2006.201.16:08:15.93#ibcon#about to read 5, iclass 16, count 0 2006.201.16:08:15.93#ibcon#read 5, iclass 16, count 0 2006.201.16:08:15.93#ibcon#about to read 6, iclass 16, count 0 2006.201.16:08:15.93#ibcon#read 6, iclass 16, count 0 2006.201.16:08:15.93#ibcon#end of sib2, iclass 16, count 0 2006.201.16:08:15.93#ibcon#*after write, iclass 16, count 0 2006.201.16:08:15.93#ibcon#*before return 0, iclass 16, count 0 2006.201.16:08:15.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:15.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:08:15.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.16:08:15.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.16:08:15.93$vck44/vblo=7,734.99 2006.201.16:08:15.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.16:08:15.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.16:08:15.93#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:15.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:15.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:15.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:15.93#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:08:15.93#ibcon#first serial, iclass 18, count 0 2006.201.16:08:15.93#ibcon#enter sib2, iclass 18, count 0 2006.201.16:08:15.93#ibcon#flushed, iclass 18, count 0 2006.201.16:08:15.93#ibcon#about to write, iclass 18, count 0 2006.201.16:08:15.93#ibcon#wrote, iclass 18, count 0 2006.201.16:08:15.93#ibcon#about to read 3, iclass 18, count 0 2006.201.16:08:15.95#ibcon#read 3, iclass 18, count 0 2006.201.16:08:15.95#ibcon#about to read 4, iclass 18, count 0 2006.201.16:08:15.95#ibcon#read 4, iclass 18, count 0 2006.201.16:08:15.95#ibcon#about to read 5, iclass 18, count 0 2006.201.16:08:15.95#ibcon#read 5, iclass 18, count 0 2006.201.16:08:15.95#ibcon#about to read 6, iclass 18, count 0 2006.201.16:08:15.95#ibcon#read 6, iclass 18, count 0 2006.201.16:08:15.95#ibcon#end of sib2, iclass 18, count 0 2006.201.16:08:15.95#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:08:15.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:08:15.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:08:15.95#ibcon#*before write, iclass 18, count 0 2006.201.16:08:15.95#ibcon#enter sib2, iclass 18, count 0 2006.201.16:08:15.95#ibcon#flushed, iclass 18, count 0 2006.201.16:08:15.95#ibcon#about to write, iclass 18, count 0 2006.201.16:08:15.95#ibcon#wrote, iclass 18, count 0 2006.201.16:08:15.95#ibcon#about to read 3, iclass 18, count 0 2006.201.16:08:15.99#ibcon#read 3, iclass 18, count 0 2006.201.16:08:15.99#ibcon#about to read 4, iclass 18, count 0 2006.201.16:08:15.99#ibcon#read 4, iclass 18, count 0 2006.201.16:08:15.99#ibcon#about to read 5, iclass 18, count 0 2006.201.16:08:15.99#ibcon#read 5, iclass 18, count 0 2006.201.16:08:15.99#ibcon#about to read 6, iclass 18, count 0 2006.201.16:08:15.99#ibcon#read 6, iclass 18, count 0 2006.201.16:08:15.99#ibcon#end of sib2, iclass 18, count 0 2006.201.16:08:15.99#ibcon#*after write, iclass 18, count 0 2006.201.16:08:15.99#ibcon#*before return 0, iclass 18, count 0 2006.201.16:08:15.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:15.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:08:15.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:08:15.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:08:15.99$vck44/vb=7,4 2006.201.16:08:15.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.16:08:15.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.16:08:15.99#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:15.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:16.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:16.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:16.05#ibcon#enter wrdev, iclass 20, count 2 2006.201.16:08:16.05#ibcon#first serial, iclass 20, count 2 2006.201.16:08:16.05#ibcon#enter sib2, iclass 20, count 2 2006.201.16:08:16.05#ibcon#flushed, iclass 20, count 2 2006.201.16:08:16.05#ibcon#about to write, iclass 20, count 2 2006.201.16:08:16.05#ibcon#wrote, iclass 20, count 2 2006.201.16:08:16.05#ibcon#about to read 3, iclass 20, count 2 2006.201.16:08:16.07#ibcon#read 3, iclass 20, count 2 2006.201.16:08:16.07#ibcon#about to read 4, iclass 20, count 2 2006.201.16:08:16.07#ibcon#read 4, iclass 20, count 2 2006.201.16:08:16.07#ibcon#about to read 5, iclass 20, count 2 2006.201.16:08:16.07#ibcon#read 5, iclass 20, count 2 2006.201.16:08:16.07#ibcon#about to read 6, iclass 20, count 2 2006.201.16:08:16.07#ibcon#read 6, iclass 20, count 2 2006.201.16:08:16.07#ibcon#end of sib2, iclass 20, count 2 2006.201.16:08:16.07#ibcon#*mode == 0, iclass 20, count 2 2006.201.16:08:16.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.16:08:16.07#ibcon#[27=AT07-04\r\n] 2006.201.16:08:16.07#ibcon#*before write, iclass 20, count 2 2006.201.16:08:16.07#ibcon#enter sib2, iclass 20, count 2 2006.201.16:08:16.07#ibcon#flushed, iclass 20, count 2 2006.201.16:08:16.07#ibcon#about to write, iclass 20, count 2 2006.201.16:08:16.07#ibcon#wrote, iclass 20, count 2 2006.201.16:08:16.07#ibcon#about to read 3, iclass 20, count 2 2006.201.16:08:16.10#ibcon#read 3, iclass 20, count 2 2006.201.16:08:16.10#ibcon#about to read 4, iclass 20, count 2 2006.201.16:08:16.10#ibcon#read 4, iclass 20, count 2 2006.201.16:08:16.10#ibcon#about to read 5, iclass 20, count 2 2006.201.16:08:16.10#ibcon#read 5, iclass 20, count 2 2006.201.16:08:16.10#ibcon#about to read 6, iclass 20, count 2 2006.201.16:08:16.10#ibcon#read 6, iclass 20, count 2 2006.201.16:08:16.10#ibcon#end of sib2, iclass 20, count 2 2006.201.16:08:16.10#ibcon#*after write, iclass 20, count 2 2006.201.16:08:16.10#ibcon#*before return 0, iclass 20, count 2 2006.201.16:08:16.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:16.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:08:16.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.16:08:16.10#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:16.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:16.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:16.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:16.22#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:08:16.22#ibcon#first serial, iclass 20, count 0 2006.201.16:08:16.22#ibcon#enter sib2, iclass 20, count 0 2006.201.16:08:16.22#ibcon#flushed, iclass 20, count 0 2006.201.16:08:16.22#ibcon#about to write, iclass 20, count 0 2006.201.16:08:16.22#ibcon#wrote, iclass 20, count 0 2006.201.16:08:16.22#ibcon#about to read 3, iclass 20, count 0 2006.201.16:08:16.24#ibcon#read 3, iclass 20, count 0 2006.201.16:08:16.24#ibcon#about to read 4, iclass 20, count 0 2006.201.16:08:16.24#ibcon#read 4, iclass 20, count 0 2006.201.16:08:16.24#ibcon#about to read 5, iclass 20, count 0 2006.201.16:08:16.24#ibcon#read 5, iclass 20, count 0 2006.201.16:08:16.24#ibcon#about to read 6, iclass 20, count 0 2006.201.16:08:16.24#ibcon#read 6, iclass 20, count 0 2006.201.16:08:16.24#ibcon#end of sib2, iclass 20, count 0 2006.201.16:08:16.24#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:08:16.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:08:16.24#ibcon#[27=USB\r\n] 2006.201.16:08:16.24#ibcon#*before write, iclass 20, count 0 2006.201.16:08:16.24#ibcon#enter sib2, iclass 20, count 0 2006.201.16:08:16.24#ibcon#flushed, iclass 20, count 0 2006.201.16:08:16.24#ibcon#about to write, iclass 20, count 0 2006.201.16:08:16.24#ibcon#wrote, iclass 20, count 0 2006.201.16:08:16.24#ibcon#about to read 3, iclass 20, count 0 2006.201.16:08:16.27#ibcon#read 3, iclass 20, count 0 2006.201.16:08:16.27#ibcon#about to read 4, iclass 20, count 0 2006.201.16:08:16.27#ibcon#read 4, iclass 20, count 0 2006.201.16:08:16.27#ibcon#about to read 5, iclass 20, count 0 2006.201.16:08:16.27#ibcon#read 5, iclass 20, count 0 2006.201.16:08:16.27#ibcon#about to read 6, iclass 20, count 0 2006.201.16:08:16.27#ibcon#read 6, iclass 20, count 0 2006.201.16:08:16.27#ibcon#end of sib2, iclass 20, count 0 2006.201.16:08:16.27#ibcon#*after write, iclass 20, count 0 2006.201.16:08:16.27#ibcon#*before return 0, iclass 20, count 0 2006.201.16:08:16.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:16.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:08:16.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:08:16.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:08:16.27$vck44/vblo=8,744.99 2006.201.16:08:16.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.16:08:16.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.16:08:16.27#ibcon#ireg 17 cls_cnt 0 2006.201.16:08:16.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:16.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:16.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:16.27#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:08:16.27#ibcon#first serial, iclass 22, count 0 2006.201.16:08:16.27#ibcon#enter sib2, iclass 22, count 0 2006.201.16:08:16.27#ibcon#flushed, iclass 22, count 0 2006.201.16:08:16.27#ibcon#about to write, iclass 22, count 0 2006.201.16:08:16.27#ibcon#wrote, iclass 22, count 0 2006.201.16:08:16.27#ibcon#about to read 3, iclass 22, count 0 2006.201.16:08:16.29#ibcon#read 3, iclass 22, count 0 2006.201.16:08:16.29#ibcon#about to read 4, iclass 22, count 0 2006.201.16:08:16.29#ibcon#read 4, iclass 22, count 0 2006.201.16:08:16.29#ibcon#about to read 5, iclass 22, count 0 2006.201.16:08:16.29#ibcon#read 5, iclass 22, count 0 2006.201.16:08:16.29#ibcon#about to read 6, iclass 22, count 0 2006.201.16:08:16.29#ibcon#read 6, iclass 22, count 0 2006.201.16:08:16.29#ibcon#end of sib2, iclass 22, count 0 2006.201.16:08:16.29#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:08:16.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:08:16.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:08:16.29#ibcon#*before write, iclass 22, count 0 2006.201.16:08:16.29#ibcon#enter sib2, iclass 22, count 0 2006.201.16:08:16.29#ibcon#flushed, iclass 22, count 0 2006.201.16:08:16.29#ibcon#about to write, iclass 22, count 0 2006.201.16:08:16.29#ibcon#wrote, iclass 22, count 0 2006.201.16:08:16.29#ibcon#about to read 3, iclass 22, count 0 2006.201.16:08:16.33#ibcon#read 3, iclass 22, count 0 2006.201.16:08:16.33#ibcon#about to read 4, iclass 22, count 0 2006.201.16:08:16.33#ibcon#read 4, iclass 22, count 0 2006.201.16:08:16.33#ibcon#about to read 5, iclass 22, count 0 2006.201.16:08:16.33#ibcon#read 5, iclass 22, count 0 2006.201.16:08:16.33#ibcon#about to read 6, iclass 22, count 0 2006.201.16:08:16.33#ibcon#read 6, iclass 22, count 0 2006.201.16:08:16.33#ibcon#end of sib2, iclass 22, count 0 2006.201.16:08:16.33#ibcon#*after write, iclass 22, count 0 2006.201.16:08:16.33#ibcon#*before return 0, iclass 22, count 0 2006.201.16:08:16.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:16.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:08:16.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:08:16.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:08:16.33$vck44/vb=8,4 2006.201.16:08:16.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.16:08:16.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.16:08:16.33#ibcon#ireg 11 cls_cnt 2 2006.201.16:08:16.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:16.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:16.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:16.39#ibcon#enter wrdev, iclass 24, count 2 2006.201.16:08:16.39#ibcon#first serial, iclass 24, count 2 2006.201.16:08:16.39#ibcon#enter sib2, iclass 24, count 2 2006.201.16:08:16.39#ibcon#flushed, iclass 24, count 2 2006.201.16:08:16.39#ibcon#about to write, iclass 24, count 2 2006.201.16:08:16.39#ibcon#wrote, iclass 24, count 2 2006.201.16:08:16.39#ibcon#about to read 3, iclass 24, count 2 2006.201.16:08:16.41#ibcon#read 3, iclass 24, count 2 2006.201.16:08:16.41#ibcon#about to read 4, iclass 24, count 2 2006.201.16:08:16.41#ibcon#read 4, iclass 24, count 2 2006.201.16:08:16.41#ibcon#about to read 5, iclass 24, count 2 2006.201.16:08:16.41#ibcon#read 5, iclass 24, count 2 2006.201.16:08:16.41#ibcon#about to read 6, iclass 24, count 2 2006.201.16:08:16.41#ibcon#read 6, iclass 24, count 2 2006.201.16:08:16.41#ibcon#end of sib2, iclass 24, count 2 2006.201.16:08:16.41#ibcon#*mode == 0, iclass 24, count 2 2006.201.16:08:16.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.16:08:16.41#ibcon#[27=AT08-04\r\n] 2006.201.16:08:16.41#ibcon#*before write, iclass 24, count 2 2006.201.16:08:16.41#ibcon#enter sib2, iclass 24, count 2 2006.201.16:08:16.41#ibcon#flushed, iclass 24, count 2 2006.201.16:08:16.41#ibcon#about to write, iclass 24, count 2 2006.201.16:08:16.41#ibcon#wrote, iclass 24, count 2 2006.201.16:08:16.41#ibcon#about to read 3, iclass 24, count 2 2006.201.16:08:16.44#ibcon#read 3, iclass 24, count 2 2006.201.16:08:16.44#ibcon#about to read 4, iclass 24, count 2 2006.201.16:08:16.44#ibcon#read 4, iclass 24, count 2 2006.201.16:08:16.44#ibcon#about to read 5, iclass 24, count 2 2006.201.16:08:16.44#ibcon#read 5, iclass 24, count 2 2006.201.16:08:16.44#ibcon#about to read 6, iclass 24, count 2 2006.201.16:08:16.44#ibcon#read 6, iclass 24, count 2 2006.201.16:08:16.44#ibcon#end of sib2, iclass 24, count 2 2006.201.16:08:16.44#ibcon#*after write, iclass 24, count 2 2006.201.16:08:16.44#ibcon#*before return 0, iclass 24, count 2 2006.201.16:08:16.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:16.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:08:16.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.16:08:16.44#ibcon#ireg 7 cls_cnt 0 2006.201.16:08:16.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:16.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:16.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:16.56#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:08:16.56#ibcon#first serial, iclass 24, count 0 2006.201.16:08:16.56#ibcon#enter sib2, iclass 24, count 0 2006.201.16:08:16.56#ibcon#flushed, iclass 24, count 0 2006.201.16:08:16.56#ibcon#about to write, iclass 24, count 0 2006.201.16:08:16.56#ibcon#wrote, iclass 24, count 0 2006.201.16:08:16.56#ibcon#about to read 3, iclass 24, count 0 2006.201.16:08:16.58#ibcon#read 3, iclass 24, count 0 2006.201.16:08:16.58#ibcon#about to read 4, iclass 24, count 0 2006.201.16:08:16.58#ibcon#read 4, iclass 24, count 0 2006.201.16:08:16.58#ibcon#about to read 5, iclass 24, count 0 2006.201.16:08:16.58#ibcon#read 5, iclass 24, count 0 2006.201.16:08:16.58#ibcon#about to read 6, iclass 24, count 0 2006.201.16:08:16.58#ibcon#read 6, iclass 24, count 0 2006.201.16:08:16.58#ibcon#end of sib2, iclass 24, count 0 2006.201.16:08:16.58#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:08:16.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:08:16.58#ibcon#[27=USB\r\n] 2006.201.16:08:16.58#ibcon#*before write, iclass 24, count 0 2006.201.16:08:16.58#ibcon#enter sib2, iclass 24, count 0 2006.201.16:08:16.58#ibcon#flushed, iclass 24, count 0 2006.201.16:08:16.58#ibcon#about to write, iclass 24, count 0 2006.201.16:08:16.58#ibcon#wrote, iclass 24, count 0 2006.201.16:08:16.58#ibcon#about to read 3, iclass 24, count 0 2006.201.16:08:16.61#ibcon#read 3, iclass 24, count 0 2006.201.16:08:16.61#ibcon#about to read 4, iclass 24, count 0 2006.201.16:08:16.61#ibcon#read 4, iclass 24, count 0 2006.201.16:08:16.61#ibcon#about to read 5, iclass 24, count 0 2006.201.16:08:16.61#ibcon#read 5, iclass 24, count 0 2006.201.16:08:16.61#ibcon#about to read 6, iclass 24, count 0 2006.201.16:08:16.61#ibcon#read 6, iclass 24, count 0 2006.201.16:08:16.61#ibcon#end of sib2, iclass 24, count 0 2006.201.16:08:16.61#ibcon#*after write, iclass 24, count 0 2006.201.16:08:16.61#ibcon#*before return 0, iclass 24, count 0 2006.201.16:08:16.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:16.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:08:16.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:08:16.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:08:16.61$vck44/vabw=wide 2006.201.16:08:16.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.16:08:16.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.16:08:16.61#ibcon#ireg 8 cls_cnt 0 2006.201.16:08:16.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:16.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:16.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:16.61#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:08:16.61#ibcon#first serial, iclass 26, count 0 2006.201.16:08:16.61#ibcon#enter sib2, iclass 26, count 0 2006.201.16:08:16.61#ibcon#flushed, iclass 26, count 0 2006.201.16:08:16.61#ibcon#about to write, iclass 26, count 0 2006.201.16:08:16.61#ibcon#wrote, iclass 26, count 0 2006.201.16:08:16.61#ibcon#about to read 3, iclass 26, count 0 2006.201.16:08:16.63#ibcon#read 3, iclass 26, count 0 2006.201.16:08:16.63#ibcon#about to read 4, iclass 26, count 0 2006.201.16:08:16.63#ibcon#read 4, iclass 26, count 0 2006.201.16:08:16.63#ibcon#about to read 5, iclass 26, count 0 2006.201.16:08:16.63#ibcon#read 5, iclass 26, count 0 2006.201.16:08:16.63#ibcon#about to read 6, iclass 26, count 0 2006.201.16:08:16.63#ibcon#read 6, iclass 26, count 0 2006.201.16:08:16.63#ibcon#end of sib2, iclass 26, count 0 2006.201.16:08:16.63#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:08:16.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:08:16.63#ibcon#[25=BW32\r\n] 2006.201.16:08:16.63#ibcon#*before write, iclass 26, count 0 2006.201.16:08:16.63#ibcon#enter sib2, iclass 26, count 0 2006.201.16:08:16.63#ibcon#flushed, iclass 26, count 0 2006.201.16:08:16.63#ibcon#about to write, iclass 26, count 0 2006.201.16:08:16.63#ibcon#wrote, iclass 26, count 0 2006.201.16:08:16.63#ibcon#about to read 3, iclass 26, count 0 2006.201.16:08:16.66#ibcon#read 3, iclass 26, count 0 2006.201.16:08:16.66#ibcon#about to read 4, iclass 26, count 0 2006.201.16:08:16.66#ibcon#read 4, iclass 26, count 0 2006.201.16:08:16.66#ibcon#about to read 5, iclass 26, count 0 2006.201.16:08:16.66#ibcon#read 5, iclass 26, count 0 2006.201.16:08:16.66#ibcon#about to read 6, iclass 26, count 0 2006.201.16:08:16.66#ibcon#read 6, iclass 26, count 0 2006.201.16:08:16.66#ibcon#end of sib2, iclass 26, count 0 2006.201.16:08:16.66#ibcon#*after write, iclass 26, count 0 2006.201.16:08:16.66#ibcon#*before return 0, iclass 26, count 0 2006.201.16:08:16.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:16.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:08:16.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:08:16.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:08:16.66$vck44/vbbw=wide 2006.201.16:08:16.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.16:08:16.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.16:08:16.66#ibcon#ireg 8 cls_cnt 0 2006.201.16:08:16.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:08:16.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:08:16.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:08:16.73#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:08:16.73#ibcon#first serial, iclass 28, count 0 2006.201.16:08:16.73#ibcon#enter sib2, iclass 28, count 0 2006.201.16:08:16.73#ibcon#flushed, iclass 28, count 0 2006.201.16:08:16.73#ibcon#about to write, iclass 28, count 0 2006.201.16:08:16.73#ibcon#wrote, iclass 28, count 0 2006.201.16:08:16.73#ibcon#about to read 3, iclass 28, count 0 2006.201.16:08:16.75#ibcon#read 3, iclass 28, count 0 2006.201.16:08:16.75#ibcon#about to read 4, iclass 28, count 0 2006.201.16:08:16.75#ibcon#read 4, iclass 28, count 0 2006.201.16:08:16.75#ibcon#about to read 5, iclass 28, count 0 2006.201.16:08:16.75#ibcon#read 5, iclass 28, count 0 2006.201.16:08:16.75#ibcon#about to read 6, iclass 28, count 0 2006.201.16:08:16.75#ibcon#read 6, iclass 28, count 0 2006.201.16:08:16.75#ibcon#end of sib2, iclass 28, count 0 2006.201.16:08:16.75#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:08:16.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:08:16.75#ibcon#[27=BW32\r\n] 2006.201.16:08:16.75#ibcon#*before write, iclass 28, count 0 2006.201.16:08:16.75#ibcon#enter sib2, iclass 28, count 0 2006.201.16:08:16.75#ibcon#flushed, iclass 28, count 0 2006.201.16:08:16.75#ibcon#about to write, iclass 28, count 0 2006.201.16:08:16.75#ibcon#wrote, iclass 28, count 0 2006.201.16:08:16.75#ibcon#about to read 3, iclass 28, count 0 2006.201.16:08:16.78#ibcon#read 3, iclass 28, count 0 2006.201.16:08:16.78#ibcon#about to read 4, iclass 28, count 0 2006.201.16:08:16.78#ibcon#read 4, iclass 28, count 0 2006.201.16:08:16.78#ibcon#about to read 5, iclass 28, count 0 2006.201.16:08:16.78#ibcon#read 5, iclass 28, count 0 2006.201.16:08:16.78#ibcon#about to read 6, iclass 28, count 0 2006.201.16:08:16.78#ibcon#read 6, iclass 28, count 0 2006.201.16:08:16.78#ibcon#end of sib2, iclass 28, count 0 2006.201.16:08:16.78#ibcon#*after write, iclass 28, count 0 2006.201.16:08:16.78#ibcon#*before return 0, iclass 28, count 0 2006.201.16:08:16.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:08:16.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:08:16.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:08:16.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:08:16.78$setupk4/ifdk4 2006.201.16:08:16.78$ifdk4/lo= 2006.201.16:08:16.78$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:08:16.78$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:08:16.78$ifdk4/patch= 2006.201.16:08:16.78$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:08:16.78$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:08:16.78$setupk4/!*+20s 2006.201.16:08:17.56#abcon#<5=/00 0.2 0.5 20.841001003.0\r\n> 2006.201.16:08:17.58#abcon#{5=INTERFACE CLEAR} 2006.201.16:08:17.64#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:08:27.73#abcon#<5=/00 0.2 0.5 20.841001003.0\r\n> 2006.201.16:08:27.75#abcon#{5=INTERFACE CLEAR} 2006.201.16:08:27.81#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:08:31.25$setupk4/"tpicd 2006.201.16:08:31.25$setupk4/echo=off 2006.201.16:08:31.25$setupk4/xlog=off 2006.201.16:08:31.25:!2006.201.16:10:00 2006.201.16:08:57.14#trakl#Source acquired 2006.201.16:08:57.14#flagr#flagr/antenna,acquired 2006.201.16:10:00.00:preob 2006.201.16:10:01.14/onsource/TRACKING 2006.201.16:10:01.14:!2006.201.16:10:10 2006.201.16:10:10.00:"tape 2006.201.16:10:10.00:"st=record 2006.201.16:10:10.00:data_valid=on 2006.201.16:10:10.00:midob 2006.201.16:10:10.14/onsource/TRACKING 2006.201.16:10:10.14/wx/20.84,1003.0,100 2006.201.16:10:10.25/cable/+6.4744E-03 2006.201.16:10:11.34/va/01,08,usb,yes,28,30 2006.201.16:10:11.34/va/02,07,usb,yes,30,31 2006.201.16:10:11.34/va/03,08,usb,yes,27,28 2006.201.16:10:11.34/va/04,07,usb,yes,31,33 2006.201.16:10:11.34/va/05,04,usb,yes,28,28 2006.201.16:10:11.34/va/06,05,usb,yes,28,27 2006.201.16:10:11.34/va/07,05,usb,yes,27,28 2006.201.16:10:11.34/va/08,04,usb,yes,27,32 2006.201.16:10:11.57/valo/01,524.99,yes,locked 2006.201.16:10:11.57/valo/02,534.99,yes,locked 2006.201.16:10:11.57/valo/03,564.99,yes,locked 2006.201.16:10:11.57/valo/04,624.99,yes,locked 2006.201.16:10:11.57/valo/05,734.99,yes,locked 2006.201.16:10:11.57/valo/06,814.99,yes,locked 2006.201.16:10:11.57/valo/07,864.99,yes,locked 2006.201.16:10:11.57/valo/08,884.99,yes,locked 2006.201.16:10:12.66/vb/01,04,usb,yes,28,26 2006.201.16:10:12.66/vb/02,05,usb,yes,27,27 2006.201.16:10:12.66/vb/03,04,usb,yes,27,30 2006.201.16:10:12.66/vb/04,05,usb,yes,28,27 2006.201.16:10:12.66/vb/05,04,usb,yes,24,27 2006.201.16:10:12.66/vb/06,04,usb,yes,29,25 2006.201.16:10:12.66/vb/07,04,usb,yes,28,28 2006.201.16:10:12.66/vb/08,04,usb,yes,26,29 2006.201.16:10:12.90/vblo/01,629.99,yes,locked 2006.201.16:10:12.90/vblo/02,634.99,yes,locked 2006.201.16:10:12.90/vblo/03,649.99,yes,locked 2006.201.16:10:12.90/vblo/04,679.99,yes,locked 2006.201.16:10:12.90/vblo/05,709.99,yes,locked 2006.201.16:10:12.90/vblo/06,719.99,yes,locked 2006.201.16:10:12.90/vblo/07,734.99,yes,locked 2006.201.16:10:12.90/vblo/08,744.99,yes,locked 2006.201.16:10:13.05/vabw/8 2006.201.16:10:13.20/vbbw/8 2006.201.16:10:13.29/xfe/off,on,16.0 2006.201.16:10:13.67/ifatt/23,28,28,28 2006.201.16:10:14.06/fmout-gps/S +4.53E-07 2006.201.16:10:14.13:!2006.201.16:12:10 2006.201.16:12:10.00:data_valid=off 2006.201.16:12:10.00:"et 2006.201.16:12:10.00:!+3s 2006.201.16:12:13.02:"tape 2006.201.16:12:13.02:postob 2006.201.16:12:13.08/cable/+6.4764E-03 2006.201.16:12:13.08/wx/20.82,1003.0,100 2006.201.16:12:13.14/fmout-gps/S +4.52E-07 2006.201.16:12:13.14:scan_name=201-1617,jd0607,220 2006.201.16:12:13.14:source=0059+581,010245.76,582411.1,2000.0,cw 2006.201.16:12:14.13#flagr#flagr/antenna,new-source 2006.201.16:12:14.13:checkk5 2006.201.16:12:14.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:12:14.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:12:15.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:12:15.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:12:15.99/chk_obsdata//k5ts1/T2011610??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.16:12:16.36/chk_obsdata//k5ts2/T2011610??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.16:12:16.73/chk_obsdata//k5ts3/T2011610??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.16:12:17.09/chk_obsdata//k5ts4/T2011610??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.16:12:17.79/k5log//k5ts1_log_newline 2006.201.16:12:18.50/k5log//k5ts2_log_newline 2006.201.16:12:19.20/k5log//k5ts3_log_newline 2006.201.16:12:19.89/k5log//k5ts4_log_newline 2006.201.16:12:19.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:12:19.91:setupk4=1 2006.201.16:12:19.91$setupk4/echo=on 2006.201.16:12:19.91$setupk4/pcalon 2006.201.16:12:19.91$pcalon/"no phase cal control is implemented here 2006.201.16:12:19.91$setupk4/"tpicd=stop 2006.201.16:12:19.91$setupk4/"rec=synch_on 2006.201.16:12:19.91$setupk4/"rec_mode=128 2006.201.16:12:19.91$setupk4/!* 2006.201.16:12:19.92$setupk4/recpk4 2006.201.16:12:19.92$recpk4/recpatch= 2006.201.16:12:19.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:12:19.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:12:19.92$setupk4/vck44 2006.201.16:12:19.92$vck44/valo=1,524.99 2006.201.16:12:19.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.16:12:19.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.16:12:19.92#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:19.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:19.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:19.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:19.92#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:12:19.92#ibcon#first serial, iclass 21, count 0 2006.201.16:12:19.92#ibcon#enter sib2, iclass 21, count 0 2006.201.16:12:19.92#ibcon#flushed, iclass 21, count 0 2006.201.16:12:19.92#ibcon#about to write, iclass 21, count 0 2006.201.16:12:19.92#ibcon#wrote, iclass 21, count 0 2006.201.16:12:19.92#ibcon#about to read 3, iclass 21, count 0 2006.201.16:12:19.96#ibcon#read 3, iclass 21, count 0 2006.201.16:12:19.96#ibcon#about to read 4, iclass 21, count 0 2006.201.16:12:19.96#ibcon#read 4, iclass 21, count 0 2006.201.16:12:19.96#ibcon#about to read 5, iclass 21, count 0 2006.201.16:12:19.96#ibcon#read 5, iclass 21, count 0 2006.201.16:12:19.96#ibcon#about to read 6, iclass 21, count 0 2006.201.16:12:19.96#ibcon#read 6, iclass 21, count 0 2006.201.16:12:19.96#ibcon#end of sib2, iclass 21, count 0 2006.201.16:12:19.96#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:12:19.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:12:19.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:12:19.96#ibcon#*before write, iclass 21, count 0 2006.201.16:12:19.96#ibcon#enter sib2, iclass 21, count 0 2006.201.16:12:19.96#ibcon#flushed, iclass 21, count 0 2006.201.16:12:19.96#ibcon#about to write, iclass 21, count 0 2006.201.16:12:19.96#ibcon#wrote, iclass 21, count 0 2006.201.16:12:19.96#ibcon#about to read 3, iclass 21, count 0 2006.201.16:12:20.01#ibcon#read 3, iclass 21, count 0 2006.201.16:12:20.01#ibcon#about to read 4, iclass 21, count 0 2006.201.16:12:20.01#ibcon#read 4, iclass 21, count 0 2006.201.16:12:20.01#ibcon#about to read 5, iclass 21, count 0 2006.201.16:12:20.01#ibcon#read 5, iclass 21, count 0 2006.201.16:12:20.01#ibcon#about to read 6, iclass 21, count 0 2006.201.16:12:20.01#ibcon#read 6, iclass 21, count 0 2006.201.16:12:20.01#ibcon#end of sib2, iclass 21, count 0 2006.201.16:12:20.01#ibcon#*after write, iclass 21, count 0 2006.201.16:12:20.01#ibcon#*before return 0, iclass 21, count 0 2006.201.16:12:20.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:20.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:20.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:12:20.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:12:20.01$vck44/va=1,8 2006.201.16:12:20.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.16:12:20.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.16:12:20.01#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:20.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:20.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:20.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:20.01#ibcon#enter wrdev, iclass 23, count 2 2006.201.16:12:20.01#ibcon#first serial, iclass 23, count 2 2006.201.16:12:20.01#ibcon#enter sib2, iclass 23, count 2 2006.201.16:12:20.01#ibcon#flushed, iclass 23, count 2 2006.201.16:12:20.01#ibcon#about to write, iclass 23, count 2 2006.201.16:12:20.01#ibcon#wrote, iclass 23, count 2 2006.201.16:12:20.01#ibcon#about to read 3, iclass 23, count 2 2006.201.16:12:20.03#ibcon#read 3, iclass 23, count 2 2006.201.16:12:20.03#ibcon#about to read 4, iclass 23, count 2 2006.201.16:12:20.03#ibcon#read 4, iclass 23, count 2 2006.201.16:12:20.03#ibcon#about to read 5, iclass 23, count 2 2006.201.16:12:20.03#ibcon#read 5, iclass 23, count 2 2006.201.16:12:20.03#ibcon#about to read 6, iclass 23, count 2 2006.201.16:12:20.03#ibcon#read 6, iclass 23, count 2 2006.201.16:12:20.03#ibcon#end of sib2, iclass 23, count 2 2006.201.16:12:20.03#ibcon#*mode == 0, iclass 23, count 2 2006.201.16:12:20.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.16:12:20.03#ibcon#[25=AT01-08\r\n] 2006.201.16:12:20.03#ibcon#*before write, iclass 23, count 2 2006.201.16:12:20.03#ibcon#enter sib2, iclass 23, count 2 2006.201.16:12:20.03#ibcon#flushed, iclass 23, count 2 2006.201.16:12:20.03#ibcon#about to write, iclass 23, count 2 2006.201.16:12:20.03#ibcon#wrote, iclass 23, count 2 2006.201.16:12:20.03#ibcon#about to read 3, iclass 23, count 2 2006.201.16:12:20.07#ibcon#read 3, iclass 23, count 2 2006.201.16:12:20.07#ibcon#about to read 4, iclass 23, count 2 2006.201.16:12:20.07#ibcon#read 4, iclass 23, count 2 2006.201.16:12:20.07#ibcon#about to read 5, iclass 23, count 2 2006.201.16:12:20.07#ibcon#read 5, iclass 23, count 2 2006.201.16:12:20.07#ibcon#about to read 6, iclass 23, count 2 2006.201.16:12:20.07#ibcon#read 6, iclass 23, count 2 2006.201.16:12:20.07#ibcon#end of sib2, iclass 23, count 2 2006.201.16:12:20.07#ibcon#*after write, iclass 23, count 2 2006.201.16:12:20.07#ibcon#*before return 0, iclass 23, count 2 2006.201.16:12:20.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:20.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:20.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.16:12:20.07#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:20.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:20.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:20.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:20.19#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:12:20.19#ibcon#first serial, iclass 23, count 0 2006.201.16:12:20.19#ibcon#enter sib2, iclass 23, count 0 2006.201.16:12:20.19#ibcon#flushed, iclass 23, count 0 2006.201.16:12:20.19#ibcon#about to write, iclass 23, count 0 2006.201.16:12:20.19#ibcon#wrote, iclass 23, count 0 2006.201.16:12:20.19#ibcon#about to read 3, iclass 23, count 0 2006.201.16:12:20.22#ibcon#read 3, iclass 23, count 0 2006.201.16:12:20.22#ibcon#about to read 4, iclass 23, count 0 2006.201.16:12:20.22#ibcon#read 4, iclass 23, count 0 2006.201.16:12:20.22#ibcon#about to read 5, iclass 23, count 0 2006.201.16:12:20.22#ibcon#read 5, iclass 23, count 0 2006.201.16:12:20.22#ibcon#about to read 6, iclass 23, count 0 2006.201.16:12:20.22#ibcon#read 6, iclass 23, count 0 2006.201.16:12:20.22#ibcon#end of sib2, iclass 23, count 0 2006.201.16:12:20.22#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:12:20.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:12:20.22#ibcon#[25=USB\r\n] 2006.201.16:12:20.22#ibcon#*before write, iclass 23, count 0 2006.201.16:12:20.22#ibcon#enter sib2, iclass 23, count 0 2006.201.16:12:20.22#ibcon#flushed, iclass 23, count 0 2006.201.16:12:20.22#ibcon#about to write, iclass 23, count 0 2006.201.16:12:20.22#ibcon#wrote, iclass 23, count 0 2006.201.16:12:20.22#ibcon#about to read 3, iclass 23, count 0 2006.201.16:12:20.25#ibcon#read 3, iclass 23, count 0 2006.201.16:12:20.25#ibcon#about to read 4, iclass 23, count 0 2006.201.16:12:20.25#ibcon#read 4, iclass 23, count 0 2006.201.16:12:20.25#ibcon#about to read 5, iclass 23, count 0 2006.201.16:12:20.25#ibcon#read 5, iclass 23, count 0 2006.201.16:12:20.25#ibcon#about to read 6, iclass 23, count 0 2006.201.16:12:20.25#ibcon#read 6, iclass 23, count 0 2006.201.16:12:20.25#ibcon#end of sib2, iclass 23, count 0 2006.201.16:12:20.25#ibcon#*after write, iclass 23, count 0 2006.201.16:12:20.25#ibcon#*before return 0, iclass 23, count 0 2006.201.16:12:20.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:20.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:20.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:12:20.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:12:20.25$vck44/valo=2,534.99 2006.201.16:12:20.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.16:12:20.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.16:12:20.25#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:20.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:20.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:20.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:20.25#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:12:20.25#ibcon#first serial, iclass 25, count 0 2006.201.16:12:20.25#ibcon#enter sib2, iclass 25, count 0 2006.201.16:12:20.25#ibcon#flushed, iclass 25, count 0 2006.201.16:12:20.25#ibcon#about to write, iclass 25, count 0 2006.201.16:12:20.25#ibcon#wrote, iclass 25, count 0 2006.201.16:12:20.25#ibcon#about to read 3, iclass 25, count 0 2006.201.16:12:20.27#ibcon#read 3, iclass 25, count 0 2006.201.16:12:20.27#ibcon#about to read 4, iclass 25, count 0 2006.201.16:12:20.27#ibcon#read 4, iclass 25, count 0 2006.201.16:12:20.27#ibcon#about to read 5, iclass 25, count 0 2006.201.16:12:20.27#ibcon#read 5, iclass 25, count 0 2006.201.16:12:20.27#ibcon#about to read 6, iclass 25, count 0 2006.201.16:12:20.27#ibcon#read 6, iclass 25, count 0 2006.201.16:12:20.27#ibcon#end of sib2, iclass 25, count 0 2006.201.16:12:20.27#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:12:20.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:12:20.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:12:20.27#ibcon#*before write, iclass 25, count 0 2006.201.16:12:20.27#ibcon#enter sib2, iclass 25, count 0 2006.201.16:12:20.27#ibcon#flushed, iclass 25, count 0 2006.201.16:12:20.27#ibcon#about to write, iclass 25, count 0 2006.201.16:12:20.27#ibcon#wrote, iclass 25, count 0 2006.201.16:12:20.27#ibcon#about to read 3, iclass 25, count 0 2006.201.16:12:20.31#ibcon#read 3, iclass 25, count 0 2006.201.16:12:20.31#ibcon#about to read 4, iclass 25, count 0 2006.201.16:12:20.31#ibcon#read 4, iclass 25, count 0 2006.201.16:12:20.31#ibcon#about to read 5, iclass 25, count 0 2006.201.16:12:20.31#ibcon#read 5, iclass 25, count 0 2006.201.16:12:20.31#ibcon#about to read 6, iclass 25, count 0 2006.201.16:12:20.31#ibcon#read 6, iclass 25, count 0 2006.201.16:12:20.31#ibcon#end of sib2, iclass 25, count 0 2006.201.16:12:20.31#ibcon#*after write, iclass 25, count 0 2006.201.16:12:20.31#ibcon#*before return 0, iclass 25, count 0 2006.201.16:12:20.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:20.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:20.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:12:20.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:12:20.31$vck44/va=2,7 2006.201.16:12:20.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.16:12:20.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.16:12:20.31#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:20.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:20.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:20.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:20.37#ibcon#enter wrdev, iclass 27, count 2 2006.201.16:12:20.37#ibcon#first serial, iclass 27, count 2 2006.201.16:12:20.37#ibcon#enter sib2, iclass 27, count 2 2006.201.16:12:20.37#ibcon#flushed, iclass 27, count 2 2006.201.16:12:20.37#ibcon#about to write, iclass 27, count 2 2006.201.16:12:20.37#ibcon#wrote, iclass 27, count 2 2006.201.16:12:20.37#ibcon#about to read 3, iclass 27, count 2 2006.201.16:12:20.39#ibcon#read 3, iclass 27, count 2 2006.201.16:12:20.39#ibcon#about to read 4, iclass 27, count 2 2006.201.16:12:20.39#ibcon#read 4, iclass 27, count 2 2006.201.16:12:20.39#ibcon#about to read 5, iclass 27, count 2 2006.201.16:12:20.39#ibcon#read 5, iclass 27, count 2 2006.201.16:12:20.39#ibcon#about to read 6, iclass 27, count 2 2006.201.16:12:20.39#ibcon#read 6, iclass 27, count 2 2006.201.16:12:20.39#ibcon#end of sib2, iclass 27, count 2 2006.201.16:12:20.39#ibcon#*mode == 0, iclass 27, count 2 2006.201.16:12:20.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.16:12:20.39#ibcon#[25=AT02-07\r\n] 2006.201.16:12:20.39#ibcon#*before write, iclass 27, count 2 2006.201.16:12:20.39#ibcon#enter sib2, iclass 27, count 2 2006.201.16:12:20.39#ibcon#flushed, iclass 27, count 2 2006.201.16:12:20.39#ibcon#about to write, iclass 27, count 2 2006.201.16:12:20.39#ibcon#wrote, iclass 27, count 2 2006.201.16:12:20.39#ibcon#about to read 3, iclass 27, count 2 2006.201.16:12:20.42#ibcon#read 3, iclass 27, count 2 2006.201.16:12:20.42#ibcon#about to read 4, iclass 27, count 2 2006.201.16:12:20.42#ibcon#read 4, iclass 27, count 2 2006.201.16:12:20.42#ibcon#about to read 5, iclass 27, count 2 2006.201.16:12:20.42#ibcon#read 5, iclass 27, count 2 2006.201.16:12:20.42#ibcon#about to read 6, iclass 27, count 2 2006.201.16:12:20.42#ibcon#read 6, iclass 27, count 2 2006.201.16:12:20.42#ibcon#end of sib2, iclass 27, count 2 2006.201.16:12:20.42#ibcon#*after write, iclass 27, count 2 2006.201.16:12:20.42#ibcon#*before return 0, iclass 27, count 2 2006.201.16:12:20.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:20.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:20.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.16:12:20.42#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:20.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:20.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:20.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:20.54#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:12:20.54#ibcon#first serial, iclass 27, count 0 2006.201.16:12:20.54#ibcon#enter sib2, iclass 27, count 0 2006.201.16:12:20.54#ibcon#flushed, iclass 27, count 0 2006.201.16:12:20.54#ibcon#about to write, iclass 27, count 0 2006.201.16:12:20.54#ibcon#wrote, iclass 27, count 0 2006.201.16:12:20.54#ibcon#about to read 3, iclass 27, count 0 2006.201.16:12:20.56#ibcon#read 3, iclass 27, count 0 2006.201.16:12:20.56#ibcon#about to read 4, iclass 27, count 0 2006.201.16:12:20.56#ibcon#read 4, iclass 27, count 0 2006.201.16:12:20.56#ibcon#about to read 5, iclass 27, count 0 2006.201.16:12:20.56#ibcon#read 5, iclass 27, count 0 2006.201.16:12:20.56#ibcon#about to read 6, iclass 27, count 0 2006.201.16:12:20.56#ibcon#read 6, iclass 27, count 0 2006.201.16:12:20.56#ibcon#end of sib2, iclass 27, count 0 2006.201.16:12:20.56#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:12:20.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:12:20.56#ibcon#[25=USB\r\n] 2006.201.16:12:20.56#ibcon#*before write, iclass 27, count 0 2006.201.16:12:20.56#ibcon#enter sib2, iclass 27, count 0 2006.201.16:12:20.56#ibcon#flushed, iclass 27, count 0 2006.201.16:12:20.56#ibcon#about to write, iclass 27, count 0 2006.201.16:12:20.56#ibcon#wrote, iclass 27, count 0 2006.201.16:12:20.56#ibcon#about to read 3, iclass 27, count 0 2006.201.16:12:20.59#ibcon#read 3, iclass 27, count 0 2006.201.16:12:20.59#ibcon#about to read 4, iclass 27, count 0 2006.201.16:12:20.59#ibcon#read 4, iclass 27, count 0 2006.201.16:12:20.59#ibcon#about to read 5, iclass 27, count 0 2006.201.16:12:20.59#ibcon#read 5, iclass 27, count 0 2006.201.16:12:20.59#ibcon#about to read 6, iclass 27, count 0 2006.201.16:12:20.59#ibcon#read 6, iclass 27, count 0 2006.201.16:12:20.59#ibcon#end of sib2, iclass 27, count 0 2006.201.16:12:20.59#ibcon#*after write, iclass 27, count 0 2006.201.16:12:20.59#ibcon#*before return 0, iclass 27, count 0 2006.201.16:12:20.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:20.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:20.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:12:20.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:12:20.59$vck44/valo=3,564.99 2006.201.16:12:20.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.16:12:20.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.16:12:20.59#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:20.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:20.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:20.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:20.59#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:12:20.59#ibcon#first serial, iclass 29, count 0 2006.201.16:12:20.59#ibcon#enter sib2, iclass 29, count 0 2006.201.16:12:20.59#ibcon#flushed, iclass 29, count 0 2006.201.16:12:20.59#ibcon#about to write, iclass 29, count 0 2006.201.16:12:20.59#ibcon#wrote, iclass 29, count 0 2006.201.16:12:20.59#ibcon#about to read 3, iclass 29, count 0 2006.201.16:12:20.61#ibcon#read 3, iclass 29, count 0 2006.201.16:12:20.61#ibcon#about to read 4, iclass 29, count 0 2006.201.16:12:20.61#ibcon#read 4, iclass 29, count 0 2006.201.16:12:20.61#ibcon#about to read 5, iclass 29, count 0 2006.201.16:12:20.61#ibcon#read 5, iclass 29, count 0 2006.201.16:12:20.61#ibcon#about to read 6, iclass 29, count 0 2006.201.16:12:20.61#ibcon#read 6, iclass 29, count 0 2006.201.16:12:20.61#ibcon#end of sib2, iclass 29, count 0 2006.201.16:12:20.61#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:12:20.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:12:20.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:12:20.61#ibcon#*before write, iclass 29, count 0 2006.201.16:12:20.61#ibcon#enter sib2, iclass 29, count 0 2006.201.16:12:20.61#ibcon#flushed, iclass 29, count 0 2006.201.16:12:20.61#ibcon#about to write, iclass 29, count 0 2006.201.16:12:20.61#ibcon#wrote, iclass 29, count 0 2006.201.16:12:20.61#ibcon#about to read 3, iclass 29, count 0 2006.201.16:12:20.66#ibcon#read 3, iclass 29, count 0 2006.201.16:12:20.66#ibcon#about to read 4, iclass 29, count 0 2006.201.16:12:20.66#ibcon#read 4, iclass 29, count 0 2006.201.16:12:20.66#ibcon#about to read 5, iclass 29, count 0 2006.201.16:12:20.66#ibcon#read 5, iclass 29, count 0 2006.201.16:12:20.66#ibcon#about to read 6, iclass 29, count 0 2006.201.16:12:20.66#ibcon#read 6, iclass 29, count 0 2006.201.16:12:20.66#ibcon#end of sib2, iclass 29, count 0 2006.201.16:12:20.66#ibcon#*after write, iclass 29, count 0 2006.201.16:12:20.66#ibcon#*before return 0, iclass 29, count 0 2006.201.16:12:20.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:20.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:20.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:12:20.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:12:20.66$vck44/va=3,8 2006.201.16:12:20.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.16:12:20.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.16:12:20.66#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:20.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:20.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:20.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:20.71#ibcon#enter wrdev, iclass 31, count 2 2006.201.16:12:20.71#ibcon#first serial, iclass 31, count 2 2006.201.16:12:20.71#ibcon#enter sib2, iclass 31, count 2 2006.201.16:12:20.71#ibcon#flushed, iclass 31, count 2 2006.201.16:12:20.71#ibcon#about to write, iclass 31, count 2 2006.201.16:12:20.71#ibcon#wrote, iclass 31, count 2 2006.201.16:12:20.71#ibcon#about to read 3, iclass 31, count 2 2006.201.16:12:20.73#ibcon#read 3, iclass 31, count 2 2006.201.16:12:20.73#ibcon#about to read 4, iclass 31, count 2 2006.201.16:12:20.73#ibcon#read 4, iclass 31, count 2 2006.201.16:12:20.73#ibcon#about to read 5, iclass 31, count 2 2006.201.16:12:20.73#ibcon#read 5, iclass 31, count 2 2006.201.16:12:20.73#ibcon#about to read 6, iclass 31, count 2 2006.201.16:12:20.73#ibcon#read 6, iclass 31, count 2 2006.201.16:12:20.73#ibcon#end of sib2, iclass 31, count 2 2006.201.16:12:20.73#ibcon#*mode == 0, iclass 31, count 2 2006.201.16:12:20.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.16:12:20.73#ibcon#[25=AT03-08\r\n] 2006.201.16:12:20.73#ibcon#*before write, iclass 31, count 2 2006.201.16:12:20.73#ibcon#enter sib2, iclass 31, count 2 2006.201.16:12:20.73#ibcon#flushed, iclass 31, count 2 2006.201.16:12:20.73#ibcon#about to write, iclass 31, count 2 2006.201.16:12:20.73#ibcon#wrote, iclass 31, count 2 2006.201.16:12:20.73#ibcon#about to read 3, iclass 31, count 2 2006.201.16:12:20.76#ibcon#read 3, iclass 31, count 2 2006.201.16:12:20.76#ibcon#about to read 4, iclass 31, count 2 2006.201.16:12:20.76#ibcon#read 4, iclass 31, count 2 2006.201.16:12:20.76#ibcon#about to read 5, iclass 31, count 2 2006.201.16:12:20.76#ibcon#read 5, iclass 31, count 2 2006.201.16:12:20.76#ibcon#about to read 6, iclass 31, count 2 2006.201.16:12:20.76#ibcon#read 6, iclass 31, count 2 2006.201.16:12:20.76#ibcon#end of sib2, iclass 31, count 2 2006.201.16:12:20.76#ibcon#*after write, iclass 31, count 2 2006.201.16:12:20.76#ibcon#*before return 0, iclass 31, count 2 2006.201.16:12:20.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:20.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:20.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.16:12:20.76#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:20.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:20.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:20.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:20.88#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:12:20.88#ibcon#first serial, iclass 31, count 0 2006.201.16:12:20.88#ibcon#enter sib2, iclass 31, count 0 2006.201.16:12:20.88#ibcon#flushed, iclass 31, count 0 2006.201.16:12:20.88#ibcon#about to write, iclass 31, count 0 2006.201.16:12:20.88#ibcon#wrote, iclass 31, count 0 2006.201.16:12:20.88#ibcon#about to read 3, iclass 31, count 0 2006.201.16:12:20.90#ibcon#read 3, iclass 31, count 0 2006.201.16:12:20.90#ibcon#about to read 4, iclass 31, count 0 2006.201.16:12:20.90#ibcon#read 4, iclass 31, count 0 2006.201.16:12:20.90#ibcon#about to read 5, iclass 31, count 0 2006.201.16:12:20.90#ibcon#read 5, iclass 31, count 0 2006.201.16:12:20.90#ibcon#about to read 6, iclass 31, count 0 2006.201.16:12:20.90#ibcon#read 6, iclass 31, count 0 2006.201.16:12:20.90#ibcon#end of sib2, iclass 31, count 0 2006.201.16:12:20.90#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:12:20.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:12:20.90#ibcon#[25=USB\r\n] 2006.201.16:12:20.90#ibcon#*before write, iclass 31, count 0 2006.201.16:12:20.90#ibcon#enter sib2, iclass 31, count 0 2006.201.16:12:20.90#ibcon#flushed, iclass 31, count 0 2006.201.16:12:20.90#ibcon#about to write, iclass 31, count 0 2006.201.16:12:20.90#ibcon#wrote, iclass 31, count 0 2006.201.16:12:20.90#ibcon#about to read 3, iclass 31, count 0 2006.201.16:12:20.93#ibcon#read 3, iclass 31, count 0 2006.201.16:12:20.93#ibcon#about to read 4, iclass 31, count 0 2006.201.16:12:20.93#ibcon#read 4, iclass 31, count 0 2006.201.16:12:20.93#ibcon#about to read 5, iclass 31, count 0 2006.201.16:12:20.93#ibcon#read 5, iclass 31, count 0 2006.201.16:12:20.93#ibcon#about to read 6, iclass 31, count 0 2006.201.16:12:20.93#ibcon#read 6, iclass 31, count 0 2006.201.16:12:20.93#ibcon#end of sib2, iclass 31, count 0 2006.201.16:12:20.93#ibcon#*after write, iclass 31, count 0 2006.201.16:12:20.93#ibcon#*before return 0, iclass 31, count 0 2006.201.16:12:20.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:20.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:20.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:12:20.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:12:20.93$vck44/valo=4,624.99 2006.201.16:12:20.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.16:12:20.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.16:12:20.93#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:20.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:20.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:20.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:20.93#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:12:20.93#ibcon#first serial, iclass 33, count 0 2006.201.16:12:20.93#ibcon#enter sib2, iclass 33, count 0 2006.201.16:12:20.93#ibcon#flushed, iclass 33, count 0 2006.201.16:12:20.93#ibcon#about to write, iclass 33, count 0 2006.201.16:12:20.93#ibcon#wrote, iclass 33, count 0 2006.201.16:12:20.93#ibcon#about to read 3, iclass 33, count 0 2006.201.16:12:20.95#ibcon#read 3, iclass 33, count 0 2006.201.16:12:20.95#ibcon#about to read 4, iclass 33, count 0 2006.201.16:12:20.95#ibcon#read 4, iclass 33, count 0 2006.201.16:12:20.95#ibcon#about to read 5, iclass 33, count 0 2006.201.16:12:20.95#ibcon#read 5, iclass 33, count 0 2006.201.16:12:20.95#ibcon#about to read 6, iclass 33, count 0 2006.201.16:12:20.95#ibcon#read 6, iclass 33, count 0 2006.201.16:12:20.95#ibcon#end of sib2, iclass 33, count 0 2006.201.16:12:20.95#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:12:20.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:12:20.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:12:20.95#ibcon#*before write, iclass 33, count 0 2006.201.16:12:20.95#ibcon#enter sib2, iclass 33, count 0 2006.201.16:12:20.95#ibcon#flushed, iclass 33, count 0 2006.201.16:12:20.95#ibcon#about to write, iclass 33, count 0 2006.201.16:12:20.95#ibcon#wrote, iclass 33, count 0 2006.201.16:12:20.95#ibcon#about to read 3, iclass 33, count 0 2006.201.16:12:20.99#ibcon#read 3, iclass 33, count 0 2006.201.16:12:20.99#ibcon#about to read 4, iclass 33, count 0 2006.201.16:12:20.99#ibcon#read 4, iclass 33, count 0 2006.201.16:12:20.99#ibcon#about to read 5, iclass 33, count 0 2006.201.16:12:20.99#ibcon#read 5, iclass 33, count 0 2006.201.16:12:20.99#ibcon#about to read 6, iclass 33, count 0 2006.201.16:12:20.99#ibcon#read 6, iclass 33, count 0 2006.201.16:12:20.99#ibcon#end of sib2, iclass 33, count 0 2006.201.16:12:20.99#ibcon#*after write, iclass 33, count 0 2006.201.16:12:20.99#ibcon#*before return 0, iclass 33, count 0 2006.201.16:12:20.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:20.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:20.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:12:20.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:12:20.99$vck44/va=4,7 2006.201.16:12:20.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.16:12:20.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.16:12:20.99#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:20.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:21.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:21.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:21.05#ibcon#enter wrdev, iclass 35, count 2 2006.201.16:12:21.05#ibcon#first serial, iclass 35, count 2 2006.201.16:12:21.05#ibcon#enter sib2, iclass 35, count 2 2006.201.16:12:21.05#ibcon#flushed, iclass 35, count 2 2006.201.16:12:21.05#ibcon#about to write, iclass 35, count 2 2006.201.16:12:21.05#ibcon#wrote, iclass 35, count 2 2006.201.16:12:21.05#ibcon#about to read 3, iclass 35, count 2 2006.201.16:12:21.07#ibcon#read 3, iclass 35, count 2 2006.201.16:12:21.07#ibcon#about to read 4, iclass 35, count 2 2006.201.16:12:21.07#ibcon#read 4, iclass 35, count 2 2006.201.16:12:21.07#ibcon#about to read 5, iclass 35, count 2 2006.201.16:12:21.07#ibcon#read 5, iclass 35, count 2 2006.201.16:12:21.07#ibcon#about to read 6, iclass 35, count 2 2006.201.16:12:21.07#ibcon#read 6, iclass 35, count 2 2006.201.16:12:21.07#ibcon#end of sib2, iclass 35, count 2 2006.201.16:12:21.07#ibcon#*mode == 0, iclass 35, count 2 2006.201.16:12:21.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.16:12:21.07#ibcon#[25=AT04-07\r\n] 2006.201.16:12:21.07#ibcon#*before write, iclass 35, count 2 2006.201.16:12:21.07#ibcon#enter sib2, iclass 35, count 2 2006.201.16:12:21.07#ibcon#flushed, iclass 35, count 2 2006.201.16:12:21.07#ibcon#about to write, iclass 35, count 2 2006.201.16:12:21.07#ibcon#wrote, iclass 35, count 2 2006.201.16:12:21.07#ibcon#about to read 3, iclass 35, count 2 2006.201.16:12:21.10#ibcon#read 3, iclass 35, count 2 2006.201.16:12:21.10#ibcon#about to read 4, iclass 35, count 2 2006.201.16:12:21.10#ibcon#read 4, iclass 35, count 2 2006.201.16:12:21.10#ibcon#about to read 5, iclass 35, count 2 2006.201.16:12:21.10#ibcon#read 5, iclass 35, count 2 2006.201.16:12:21.10#ibcon#about to read 6, iclass 35, count 2 2006.201.16:12:21.10#ibcon#read 6, iclass 35, count 2 2006.201.16:12:21.10#ibcon#end of sib2, iclass 35, count 2 2006.201.16:12:21.10#ibcon#*after write, iclass 35, count 2 2006.201.16:12:21.10#ibcon#*before return 0, iclass 35, count 2 2006.201.16:12:21.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:21.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:21.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.16:12:21.10#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:21.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:21.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:21.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:21.22#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:12:21.22#ibcon#first serial, iclass 35, count 0 2006.201.16:12:21.22#ibcon#enter sib2, iclass 35, count 0 2006.201.16:12:21.22#ibcon#flushed, iclass 35, count 0 2006.201.16:12:21.22#ibcon#about to write, iclass 35, count 0 2006.201.16:12:21.22#ibcon#wrote, iclass 35, count 0 2006.201.16:12:21.22#ibcon#about to read 3, iclass 35, count 0 2006.201.16:12:21.24#ibcon#read 3, iclass 35, count 0 2006.201.16:12:21.24#ibcon#about to read 4, iclass 35, count 0 2006.201.16:12:21.24#ibcon#read 4, iclass 35, count 0 2006.201.16:12:21.24#ibcon#about to read 5, iclass 35, count 0 2006.201.16:12:21.24#ibcon#read 5, iclass 35, count 0 2006.201.16:12:21.24#ibcon#about to read 6, iclass 35, count 0 2006.201.16:12:21.24#ibcon#read 6, iclass 35, count 0 2006.201.16:12:21.24#ibcon#end of sib2, iclass 35, count 0 2006.201.16:12:21.24#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:12:21.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:12:21.24#ibcon#[25=USB\r\n] 2006.201.16:12:21.24#ibcon#*before write, iclass 35, count 0 2006.201.16:12:21.24#ibcon#enter sib2, iclass 35, count 0 2006.201.16:12:21.24#ibcon#flushed, iclass 35, count 0 2006.201.16:12:21.24#ibcon#about to write, iclass 35, count 0 2006.201.16:12:21.24#ibcon#wrote, iclass 35, count 0 2006.201.16:12:21.24#ibcon#about to read 3, iclass 35, count 0 2006.201.16:12:21.27#ibcon#read 3, iclass 35, count 0 2006.201.16:12:21.27#ibcon#about to read 4, iclass 35, count 0 2006.201.16:12:21.27#ibcon#read 4, iclass 35, count 0 2006.201.16:12:21.27#ibcon#about to read 5, iclass 35, count 0 2006.201.16:12:21.27#ibcon#read 5, iclass 35, count 0 2006.201.16:12:21.27#ibcon#about to read 6, iclass 35, count 0 2006.201.16:12:21.27#ibcon#read 6, iclass 35, count 0 2006.201.16:12:21.27#ibcon#end of sib2, iclass 35, count 0 2006.201.16:12:21.27#ibcon#*after write, iclass 35, count 0 2006.201.16:12:21.27#ibcon#*before return 0, iclass 35, count 0 2006.201.16:12:21.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:21.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:21.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:12:21.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:12:21.27$vck44/valo=5,734.99 2006.201.16:12:21.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.16:12:21.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.16:12:21.27#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:21.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:21.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:21.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:21.27#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:12:21.27#ibcon#first serial, iclass 37, count 0 2006.201.16:12:21.27#ibcon#enter sib2, iclass 37, count 0 2006.201.16:12:21.27#ibcon#flushed, iclass 37, count 0 2006.201.16:12:21.27#ibcon#about to write, iclass 37, count 0 2006.201.16:12:21.27#ibcon#wrote, iclass 37, count 0 2006.201.16:12:21.27#ibcon#about to read 3, iclass 37, count 0 2006.201.16:12:21.29#ibcon#read 3, iclass 37, count 0 2006.201.16:12:21.29#ibcon#about to read 4, iclass 37, count 0 2006.201.16:12:21.29#ibcon#read 4, iclass 37, count 0 2006.201.16:12:21.29#ibcon#about to read 5, iclass 37, count 0 2006.201.16:12:21.29#ibcon#read 5, iclass 37, count 0 2006.201.16:12:21.29#ibcon#about to read 6, iclass 37, count 0 2006.201.16:12:21.29#ibcon#read 6, iclass 37, count 0 2006.201.16:12:21.29#ibcon#end of sib2, iclass 37, count 0 2006.201.16:12:21.29#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:12:21.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:12:21.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:12:21.29#ibcon#*before write, iclass 37, count 0 2006.201.16:12:21.29#ibcon#enter sib2, iclass 37, count 0 2006.201.16:12:21.29#ibcon#flushed, iclass 37, count 0 2006.201.16:12:21.29#ibcon#about to write, iclass 37, count 0 2006.201.16:12:21.29#ibcon#wrote, iclass 37, count 0 2006.201.16:12:21.29#ibcon#about to read 3, iclass 37, count 0 2006.201.16:12:21.33#ibcon#read 3, iclass 37, count 0 2006.201.16:12:21.33#ibcon#about to read 4, iclass 37, count 0 2006.201.16:12:21.33#ibcon#read 4, iclass 37, count 0 2006.201.16:12:21.33#ibcon#about to read 5, iclass 37, count 0 2006.201.16:12:21.33#ibcon#read 5, iclass 37, count 0 2006.201.16:12:21.33#ibcon#about to read 6, iclass 37, count 0 2006.201.16:12:21.33#ibcon#read 6, iclass 37, count 0 2006.201.16:12:21.33#ibcon#end of sib2, iclass 37, count 0 2006.201.16:12:21.33#ibcon#*after write, iclass 37, count 0 2006.201.16:12:21.33#ibcon#*before return 0, iclass 37, count 0 2006.201.16:12:21.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:21.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:21.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:12:21.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:12:21.33$vck44/va=5,4 2006.201.16:12:21.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.16:12:21.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.16:12:21.33#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:21.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:21.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:21.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:21.39#ibcon#enter wrdev, iclass 39, count 2 2006.201.16:12:21.39#ibcon#first serial, iclass 39, count 2 2006.201.16:12:21.39#ibcon#enter sib2, iclass 39, count 2 2006.201.16:12:21.39#ibcon#flushed, iclass 39, count 2 2006.201.16:12:21.39#ibcon#about to write, iclass 39, count 2 2006.201.16:12:21.39#ibcon#wrote, iclass 39, count 2 2006.201.16:12:21.39#ibcon#about to read 3, iclass 39, count 2 2006.201.16:12:21.41#ibcon#read 3, iclass 39, count 2 2006.201.16:12:21.41#ibcon#about to read 4, iclass 39, count 2 2006.201.16:12:21.41#ibcon#read 4, iclass 39, count 2 2006.201.16:12:21.41#ibcon#about to read 5, iclass 39, count 2 2006.201.16:12:21.41#ibcon#read 5, iclass 39, count 2 2006.201.16:12:21.41#ibcon#about to read 6, iclass 39, count 2 2006.201.16:12:21.41#ibcon#read 6, iclass 39, count 2 2006.201.16:12:21.41#ibcon#end of sib2, iclass 39, count 2 2006.201.16:12:21.41#ibcon#*mode == 0, iclass 39, count 2 2006.201.16:12:21.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.16:12:21.41#ibcon#[25=AT05-04\r\n] 2006.201.16:12:21.41#ibcon#*before write, iclass 39, count 2 2006.201.16:12:21.41#ibcon#enter sib2, iclass 39, count 2 2006.201.16:12:21.41#ibcon#flushed, iclass 39, count 2 2006.201.16:12:21.41#ibcon#about to write, iclass 39, count 2 2006.201.16:12:21.41#ibcon#wrote, iclass 39, count 2 2006.201.16:12:21.41#ibcon#about to read 3, iclass 39, count 2 2006.201.16:12:21.44#ibcon#read 3, iclass 39, count 2 2006.201.16:12:21.44#ibcon#about to read 4, iclass 39, count 2 2006.201.16:12:21.44#ibcon#read 4, iclass 39, count 2 2006.201.16:12:21.44#ibcon#about to read 5, iclass 39, count 2 2006.201.16:12:21.44#ibcon#read 5, iclass 39, count 2 2006.201.16:12:21.44#ibcon#about to read 6, iclass 39, count 2 2006.201.16:12:21.44#ibcon#read 6, iclass 39, count 2 2006.201.16:12:21.44#ibcon#end of sib2, iclass 39, count 2 2006.201.16:12:21.44#ibcon#*after write, iclass 39, count 2 2006.201.16:12:21.44#ibcon#*before return 0, iclass 39, count 2 2006.201.16:12:21.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:21.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:21.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.16:12:21.44#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:21.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:21.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:21.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:21.56#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:12:21.56#ibcon#first serial, iclass 39, count 0 2006.201.16:12:21.56#ibcon#enter sib2, iclass 39, count 0 2006.201.16:12:21.56#ibcon#flushed, iclass 39, count 0 2006.201.16:12:21.56#ibcon#about to write, iclass 39, count 0 2006.201.16:12:21.56#ibcon#wrote, iclass 39, count 0 2006.201.16:12:21.56#ibcon#about to read 3, iclass 39, count 0 2006.201.16:12:21.58#ibcon#read 3, iclass 39, count 0 2006.201.16:12:21.58#ibcon#about to read 4, iclass 39, count 0 2006.201.16:12:21.58#ibcon#read 4, iclass 39, count 0 2006.201.16:12:21.58#ibcon#about to read 5, iclass 39, count 0 2006.201.16:12:21.58#ibcon#read 5, iclass 39, count 0 2006.201.16:12:21.58#ibcon#about to read 6, iclass 39, count 0 2006.201.16:12:21.58#ibcon#read 6, iclass 39, count 0 2006.201.16:12:21.58#ibcon#end of sib2, iclass 39, count 0 2006.201.16:12:21.58#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:12:21.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:12:21.58#ibcon#[25=USB\r\n] 2006.201.16:12:21.58#ibcon#*before write, iclass 39, count 0 2006.201.16:12:21.58#ibcon#enter sib2, iclass 39, count 0 2006.201.16:12:21.58#ibcon#flushed, iclass 39, count 0 2006.201.16:12:21.58#ibcon#about to write, iclass 39, count 0 2006.201.16:12:21.58#ibcon#wrote, iclass 39, count 0 2006.201.16:12:21.58#ibcon#about to read 3, iclass 39, count 0 2006.201.16:12:21.61#ibcon#read 3, iclass 39, count 0 2006.201.16:12:21.61#ibcon#about to read 4, iclass 39, count 0 2006.201.16:12:21.61#ibcon#read 4, iclass 39, count 0 2006.201.16:12:21.61#ibcon#about to read 5, iclass 39, count 0 2006.201.16:12:21.61#ibcon#read 5, iclass 39, count 0 2006.201.16:12:21.61#ibcon#about to read 6, iclass 39, count 0 2006.201.16:12:21.61#ibcon#read 6, iclass 39, count 0 2006.201.16:12:21.61#ibcon#end of sib2, iclass 39, count 0 2006.201.16:12:21.61#ibcon#*after write, iclass 39, count 0 2006.201.16:12:21.61#ibcon#*before return 0, iclass 39, count 0 2006.201.16:12:21.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:21.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:21.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:12:21.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:12:21.61$vck44/valo=6,814.99 2006.201.16:12:21.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.16:12:21.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.16:12:21.61#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:21.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:12:21.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:12:21.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:12:21.61#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:12:21.61#ibcon#first serial, iclass 4, count 0 2006.201.16:12:21.61#ibcon#enter sib2, iclass 4, count 0 2006.201.16:12:21.61#ibcon#flushed, iclass 4, count 0 2006.201.16:12:21.61#ibcon#about to write, iclass 4, count 0 2006.201.16:12:21.61#ibcon#wrote, iclass 4, count 0 2006.201.16:12:21.61#ibcon#about to read 3, iclass 4, count 0 2006.201.16:12:21.63#ibcon#read 3, iclass 4, count 0 2006.201.16:12:21.63#ibcon#about to read 4, iclass 4, count 0 2006.201.16:12:21.63#ibcon#read 4, iclass 4, count 0 2006.201.16:12:21.63#ibcon#about to read 5, iclass 4, count 0 2006.201.16:12:21.63#ibcon#read 5, iclass 4, count 0 2006.201.16:12:21.63#ibcon#about to read 6, iclass 4, count 0 2006.201.16:12:21.63#ibcon#read 6, iclass 4, count 0 2006.201.16:12:21.63#ibcon#end of sib2, iclass 4, count 0 2006.201.16:12:21.63#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:12:21.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:12:21.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:12:21.63#ibcon#*before write, iclass 4, count 0 2006.201.16:12:21.63#ibcon#enter sib2, iclass 4, count 0 2006.201.16:12:21.63#ibcon#flushed, iclass 4, count 0 2006.201.16:12:21.63#ibcon#about to write, iclass 4, count 0 2006.201.16:12:21.63#ibcon#wrote, iclass 4, count 0 2006.201.16:12:21.63#ibcon#about to read 3, iclass 4, count 0 2006.201.16:12:21.64#abcon#<5=/00 0.1 0.4 20.821001003.0\r\n> 2006.201.16:12:21.66#abcon#{5=INTERFACE CLEAR} 2006.201.16:12:21.67#ibcon#read 3, iclass 4, count 0 2006.201.16:12:21.67#ibcon#about to read 4, iclass 4, count 0 2006.201.16:12:21.67#ibcon#read 4, iclass 4, count 0 2006.201.16:12:21.67#ibcon#about to read 5, iclass 4, count 0 2006.201.16:12:21.67#ibcon#read 5, iclass 4, count 0 2006.201.16:12:21.67#ibcon#about to read 6, iclass 4, count 0 2006.201.16:12:21.67#ibcon#read 6, iclass 4, count 0 2006.201.16:12:21.67#ibcon#end of sib2, iclass 4, count 0 2006.201.16:12:21.67#ibcon#*after write, iclass 4, count 0 2006.201.16:12:21.67#ibcon#*before return 0, iclass 4, count 0 2006.201.16:12:21.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:12:21.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:12:21.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:12:21.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:12:21.67$vck44/va=6,5 2006.201.16:12:21.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.16:12:21.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.16:12:21.67#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:21.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:12:21.72#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:12:21.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:12:21.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:12:21.73#ibcon#enter wrdev, iclass 10, count 2 2006.201.16:12:21.73#ibcon#first serial, iclass 10, count 2 2006.201.16:12:21.73#ibcon#enter sib2, iclass 10, count 2 2006.201.16:12:21.73#ibcon#flushed, iclass 10, count 2 2006.201.16:12:21.73#ibcon#about to write, iclass 10, count 2 2006.201.16:12:21.73#ibcon#wrote, iclass 10, count 2 2006.201.16:12:21.73#ibcon#about to read 3, iclass 10, count 2 2006.201.16:12:21.75#ibcon#read 3, iclass 10, count 2 2006.201.16:12:21.75#ibcon#about to read 4, iclass 10, count 2 2006.201.16:12:21.75#ibcon#read 4, iclass 10, count 2 2006.201.16:12:21.75#ibcon#about to read 5, iclass 10, count 2 2006.201.16:12:21.75#ibcon#read 5, iclass 10, count 2 2006.201.16:12:21.75#ibcon#about to read 6, iclass 10, count 2 2006.201.16:12:21.75#ibcon#read 6, iclass 10, count 2 2006.201.16:12:21.75#ibcon#end of sib2, iclass 10, count 2 2006.201.16:12:21.75#ibcon#*mode == 0, iclass 10, count 2 2006.201.16:12:21.75#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.16:12:21.75#ibcon#[25=AT06-05\r\n] 2006.201.16:12:21.75#ibcon#*before write, iclass 10, count 2 2006.201.16:12:21.75#ibcon#enter sib2, iclass 10, count 2 2006.201.16:12:21.75#ibcon#flushed, iclass 10, count 2 2006.201.16:12:21.75#ibcon#about to write, iclass 10, count 2 2006.201.16:12:21.75#ibcon#wrote, iclass 10, count 2 2006.201.16:12:21.75#ibcon#about to read 3, iclass 10, count 2 2006.201.16:12:21.78#ibcon#read 3, iclass 10, count 2 2006.201.16:12:21.78#ibcon#about to read 4, iclass 10, count 2 2006.201.16:12:21.78#ibcon#read 4, iclass 10, count 2 2006.201.16:12:21.78#ibcon#about to read 5, iclass 10, count 2 2006.201.16:12:21.78#ibcon#read 5, iclass 10, count 2 2006.201.16:12:21.78#ibcon#about to read 6, iclass 10, count 2 2006.201.16:12:21.78#ibcon#read 6, iclass 10, count 2 2006.201.16:12:21.78#ibcon#end of sib2, iclass 10, count 2 2006.201.16:12:21.78#ibcon#*after write, iclass 10, count 2 2006.201.16:12:21.78#ibcon#*before return 0, iclass 10, count 2 2006.201.16:12:21.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:12:21.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:12:21.78#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.16:12:21.78#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:21.78#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:12:21.90#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:12:21.90#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:12:21.90#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:12:21.90#ibcon#first serial, iclass 10, count 0 2006.201.16:12:21.90#ibcon#enter sib2, iclass 10, count 0 2006.201.16:12:21.90#ibcon#flushed, iclass 10, count 0 2006.201.16:12:21.90#ibcon#about to write, iclass 10, count 0 2006.201.16:12:21.90#ibcon#wrote, iclass 10, count 0 2006.201.16:12:21.90#ibcon#about to read 3, iclass 10, count 0 2006.201.16:12:21.92#ibcon#read 3, iclass 10, count 0 2006.201.16:12:21.92#ibcon#about to read 4, iclass 10, count 0 2006.201.16:12:21.92#ibcon#read 4, iclass 10, count 0 2006.201.16:12:21.92#ibcon#about to read 5, iclass 10, count 0 2006.201.16:12:21.92#ibcon#read 5, iclass 10, count 0 2006.201.16:12:21.92#ibcon#about to read 6, iclass 10, count 0 2006.201.16:12:21.92#ibcon#read 6, iclass 10, count 0 2006.201.16:12:21.92#ibcon#end of sib2, iclass 10, count 0 2006.201.16:12:21.92#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:12:21.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:12:21.92#ibcon#[25=USB\r\n] 2006.201.16:12:21.92#ibcon#*before write, iclass 10, count 0 2006.201.16:12:21.92#ibcon#enter sib2, iclass 10, count 0 2006.201.16:12:21.92#ibcon#flushed, iclass 10, count 0 2006.201.16:12:21.92#ibcon#about to write, iclass 10, count 0 2006.201.16:12:21.92#ibcon#wrote, iclass 10, count 0 2006.201.16:12:21.92#ibcon#about to read 3, iclass 10, count 0 2006.201.16:12:21.95#ibcon#read 3, iclass 10, count 0 2006.201.16:12:21.95#ibcon#about to read 4, iclass 10, count 0 2006.201.16:12:21.95#ibcon#read 4, iclass 10, count 0 2006.201.16:12:21.95#ibcon#about to read 5, iclass 10, count 0 2006.201.16:12:21.95#ibcon#read 5, iclass 10, count 0 2006.201.16:12:21.95#ibcon#about to read 6, iclass 10, count 0 2006.201.16:12:21.95#ibcon#read 6, iclass 10, count 0 2006.201.16:12:21.95#ibcon#end of sib2, iclass 10, count 0 2006.201.16:12:21.95#ibcon#*after write, iclass 10, count 0 2006.201.16:12:21.95#ibcon#*before return 0, iclass 10, count 0 2006.201.16:12:21.95#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:12:21.95#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:12:21.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:12:21.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:12:21.95$vck44/valo=7,864.99 2006.201.16:12:21.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.16:12:21.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.16:12:21.95#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:21.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:21.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:21.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:21.95#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:12:21.95#ibcon#first serial, iclass 13, count 0 2006.201.16:12:21.95#ibcon#enter sib2, iclass 13, count 0 2006.201.16:12:21.95#ibcon#flushed, iclass 13, count 0 2006.201.16:12:21.95#ibcon#about to write, iclass 13, count 0 2006.201.16:12:21.95#ibcon#wrote, iclass 13, count 0 2006.201.16:12:21.95#ibcon#about to read 3, iclass 13, count 0 2006.201.16:12:21.97#ibcon#read 3, iclass 13, count 0 2006.201.16:12:21.97#ibcon#about to read 4, iclass 13, count 0 2006.201.16:12:21.97#ibcon#read 4, iclass 13, count 0 2006.201.16:12:21.97#ibcon#about to read 5, iclass 13, count 0 2006.201.16:12:21.97#ibcon#read 5, iclass 13, count 0 2006.201.16:12:21.97#ibcon#about to read 6, iclass 13, count 0 2006.201.16:12:21.97#ibcon#read 6, iclass 13, count 0 2006.201.16:12:21.97#ibcon#end of sib2, iclass 13, count 0 2006.201.16:12:21.97#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:12:21.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:12:21.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:12:21.97#ibcon#*before write, iclass 13, count 0 2006.201.16:12:21.97#ibcon#enter sib2, iclass 13, count 0 2006.201.16:12:21.97#ibcon#flushed, iclass 13, count 0 2006.201.16:12:21.97#ibcon#about to write, iclass 13, count 0 2006.201.16:12:21.97#ibcon#wrote, iclass 13, count 0 2006.201.16:12:21.97#ibcon#about to read 3, iclass 13, count 0 2006.201.16:12:22.01#ibcon#read 3, iclass 13, count 0 2006.201.16:12:22.01#ibcon#about to read 4, iclass 13, count 0 2006.201.16:12:22.01#ibcon#read 4, iclass 13, count 0 2006.201.16:12:22.01#ibcon#about to read 5, iclass 13, count 0 2006.201.16:12:22.01#ibcon#read 5, iclass 13, count 0 2006.201.16:12:22.01#ibcon#about to read 6, iclass 13, count 0 2006.201.16:12:22.01#ibcon#read 6, iclass 13, count 0 2006.201.16:12:22.01#ibcon#end of sib2, iclass 13, count 0 2006.201.16:12:22.01#ibcon#*after write, iclass 13, count 0 2006.201.16:12:22.01#ibcon#*before return 0, iclass 13, count 0 2006.201.16:12:22.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:22.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:22.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:12:22.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:12:22.01$vck44/va=7,5 2006.201.16:12:22.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.16:12:22.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.16:12:22.01#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:22.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:22.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:22.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:22.07#ibcon#enter wrdev, iclass 15, count 2 2006.201.16:12:22.07#ibcon#first serial, iclass 15, count 2 2006.201.16:12:22.07#ibcon#enter sib2, iclass 15, count 2 2006.201.16:12:22.07#ibcon#flushed, iclass 15, count 2 2006.201.16:12:22.07#ibcon#about to write, iclass 15, count 2 2006.201.16:12:22.07#ibcon#wrote, iclass 15, count 2 2006.201.16:12:22.07#ibcon#about to read 3, iclass 15, count 2 2006.201.16:12:22.09#ibcon#read 3, iclass 15, count 2 2006.201.16:12:22.09#ibcon#about to read 4, iclass 15, count 2 2006.201.16:12:22.09#ibcon#read 4, iclass 15, count 2 2006.201.16:12:22.09#ibcon#about to read 5, iclass 15, count 2 2006.201.16:12:22.09#ibcon#read 5, iclass 15, count 2 2006.201.16:12:22.09#ibcon#about to read 6, iclass 15, count 2 2006.201.16:12:22.09#ibcon#read 6, iclass 15, count 2 2006.201.16:12:22.09#ibcon#end of sib2, iclass 15, count 2 2006.201.16:12:22.09#ibcon#*mode == 0, iclass 15, count 2 2006.201.16:12:22.09#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.16:12:22.09#ibcon#[25=AT07-05\r\n] 2006.201.16:12:22.09#ibcon#*before write, iclass 15, count 2 2006.201.16:12:22.09#ibcon#enter sib2, iclass 15, count 2 2006.201.16:12:22.09#ibcon#flushed, iclass 15, count 2 2006.201.16:12:22.09#ibcon#about to write, iclass 15, count 2 2006.201.16:12:22.09#ibcon#wrote, iclass 15, count 2 2006.201.16:12:22.09#ibcon#about to read 3, iclass 15, count 2 2006.201.16:12:22.12#ibcon#read 3, iclass 15, count 2 2006.201.16:12:22.12#ibcon#about to read 4, iclass 15, count 2 2006.201.16:12:22.12#ibcon#read 4, iclass 15, count 2 2006.201.16:12:22.12#ibcon#about to read 5, iclass 15, count 2 2006.201.16:12:22.12#ibcon#read 5, iclass 15, count 2 2006.201.16:12:22.12#ibcon#about to read 6, iclass 15, count 2 2006.201.16:12:22.12#ibcon#read 6, iclass 15, count 2 2006.201.16:12:22.12#ibcon#end of sib2, iclass 15, count 2 2006.201.16:12:22.12#ibcon#*after write, iclass 15, count 2 2006.201.16:12:22.12#ibcon#*before return 0, iclass 15, count 2 2006.201.16:12:22.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:22.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:22.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.16:12:22.12#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:22.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:22.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:22.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:22.24#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:12:22.24#ibcon#first serial, iclass 15, count 0 2006.201.16:12:22.24#ibcon#enter sib2, iclass 15, count 0 2006.201.16:12:22.24#ibcon#flushed, iclass 15, count 0 2006.201.16:12:22.24#ibcon#about to write, iclass 15, count 0 2006.201.16:12:22.24#ibcon#wrote, iclass 15, count 0 2006.201.16:12:22.24#ibcon#about to read 3, iclass 15, count 0 2006.201.16:12:22.26#ibcon#read 3, iclass 15, count 0 2006.201.16:12:22.26#ibcon#about to read 4, iclass 15, count 0 2006.201.16:12:22.26#ibcon#read 4, iclass 15, count 0 2006.201.16:12:22.26#ibcon#about to read 5, iclass 15, count 0 2006.201.16:12:22.26#ibcon#read 5, iclass 15, count 0 2006.201.16:12:22.26#ibcon#about to read 6, iclass 15, count 0 2006.201.16:12:22.26#ibcon#read 6, iclass 15, count 0 2006.201.16:12:22.26#ibcon#end of sib2, iclass 15, count 0 2006.201.16:12:22.26#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:12:22.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:12:22.26#ibcon#[25=USB\r\n] 2006.201.16:12:22.26#ibcon#*before write, iclass 15, count 0 2006.201.16:12:22.26#ibcon#enter sib2, iclass 15, count 0 2006.201.16:12:22.26#ibcon#flushed, iclass 15, count 0 2006.201.16:12:22.26#ibcon#about to write, iclass 15, count 0 2006.201.16:12:22.26#ibcon#wrote, iclass 15, count 0 2006.201.16:12:22.26#ibcon#about to read 3, iclass 15, count 0 2006.201.16:12:22.29#ibcon#read 3, iclass 15, count 0 2006.201.16:12:22.29#ibcon#about to read 4, iclass 15, count 0 2006.201.16:12:22.29#ibcon#read 4, iclass 15, count 0 2006.201.16:12:22.29#ibcon#about to read 5, iclass 15, count 0 2006.201.16:12:22.29#ibcon#read 5, iclass 15, count 0 2006.201.16:12:22.29#ibcon#about to read 6, iclass 15, count 0 2006.201.16:12:22.29#ibcon#read 6, iclass 15, count 0 2006.201.16:12:22.29#ibcon#end of sib2, iclass 15, count 0 2006.201.16:12:22.29#ibcon#*after write, iclass 15, count 0 2006.201.16:12:22.29#ibcon#*before return 0, iclass 15, count 0 2006.201.16:12:22.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:22.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:22.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:12:22.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:12:22.29$vck44/valo=8,884.99 2006.201.16:12:22.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.16:12:22.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.16:12:22.29#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:22.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:22.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:22.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:22.29#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:12:22.29#ibcon#first serial, iclass 17, count 0 2006.201.16:12:22.29#ibcon#enter sib2, iclass 17, count 0 2006.201.16:12:22.29#ibcon#flushed, iclass 17, count 0 2006.201.16:12:22.29#ibcon#about to write, iclass 17, count 0 2006.201.16:12:22.29#ibcon#wrote, iclass 17, count 0 2006.201.16:12:22.29#ibcon#about to read 3, iclass 17, count 0 2006.201.16:12:22.31#ibcon#read 3, iclass 17, count 0 2006.201.16:12:22.31#ibcon#about to read 4, iclass 17, count 0 2006.201.16:12:22.31#ibcon#read 4, iclass 17, count 0 2006.201.16:12:22.31#ibcon#about to read 5, iclass 17, count 0 2006.201.16:12:22.31#ibcon#read 5, iclass 17, count 0 2006.201.16:12:22.31#ibcon#about to read 6, iclass 17, count 0 2006.201.16:12:22.31#ibcon#read 6, iclass 17, count 0 2006.201.16:12:22.31#ibcon#end of sib2, iclass 17, count 0 2006.201.16:12:22.31#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:12:22.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:12:22.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:12:22.31#ibcon#*before write, iclass 17, count 0 2006.201.16:12:22.31#ibcon#enter sib2, iclass 17, count 0 2006.201.16:12:22.31#ibcon#flushed, iclass 17, count 0 2006.201.16:12:22.31#ibcon#about to write, iclass 17, count 0 2006.201.16:12:22.31#ibcon#wrote, iclass 17, count 0 2006.201.16:12:22.31#ibcon#about to read 3, iclass 17, count 0 2006.201.16:12:22.35#ibcon#read 3, iclass 17, count 0 2006.201.16:12:22.35#ibcon#about to read 4, iclass 17, count 0 2006.201.16:12:22.35#ibcon#read 4, iclass 17, count 0 2006.201.16:12:22.35#ibcon#about to read 5, iclass 17, count 0 2006.201.16:12:22.35#ibcon#read 5, iclass 17, count 0 2006.201.16:12:22.35#ibcon#about to read 6, iclass 17, count 0 2006.201.16:12:22.35#ibcon#read 6, iclass 17, count 0 2006.201.16:12:22.35#ibcon#end of sib2, iclass 17, count 0 2006.201.16:12:22.35#ibcon#*after write, iclass 17, count 0 2006.201.16:12:22.35#ibcon#*before return 0, iclass 17, count 0 2006.201.16:12:22.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:22.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:22.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:12:22.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:12:22.35$vck44/va=8,4 2006.201.16:12:22.35#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.16:12:22.35#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.16:12:22.35#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:22.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:12:22.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:12:22.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:12:22.41#ibcon#enter wrdev, iclass 19, count 2 2006.201.16:12:22.41#ibcon#first serial, iclass 19, count 2 2006.201.16:12:22.41#ibcon#enter sib2, iclass 19, count 2 2006.201.16:12:22.41#ibcon#flushed, iclass 19, count 2 2006.201.16:12:22.41#ibcon#about to write, iclass 19, count 2 2006.201.16:12:22.41#ibcon#wrote, iclass 19, count 2 2006.201.16:12:22.41#ibcon#about to read 3, iclass 19, count 2 2006.201.16:12:22.43#ibcon#read 3, iclass 19, count 2 2006.201.16:12:22.43#ibcon#about to read 4, iclass 19, count 2 2006.201.16:12:22.43#ibcon#read 4, iclass 19, count 2 2006.201.16:12:22.43#ibcon#about to read 5, iclass 19, count 2 2006.201.16:12:22.43#ibcon#read 5, iclass 19, count 2 2006.201.16:12:22.43#ibcon#about to read 6, iclass 19, count 2 2006.201.16:12:22.43#ibcon#read 6, iclass 19, count 2 2006.201.16:12:22.43#ibcon#end of sib2, iclass 19, count 2 2006.201.16:12:22.43#ibcon#*mode == 0, iclass 19, count 2 2006.201.16:12:22.43#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.16:12:22.43#ibcon#[25=AT08-04\r\n] 2006.201.16:12:22.43#ibcon#*before write, iclass 19, count 2 2006.201.16:12:22.43#ibcon#enter sib2, iclass 19, count 2 2006.201.16:12:22.43#ibcon#flushed, iclass 19, count 2 2006.201.16:12:22.43#ibcon#about to write, iclass 19, count 2 2006.201.16:12:22.43#ibcon#wrote, iclass 19, count 2 2006.201.16:12:22.43#ibcon#about to read 3, iclass 19, count 2 2006.201.16:12:22.46#ibcon#read 3, iclass 19, count 2 2006.201.16:12:22.46#ibcon#about to read 4, iclass 19, count 2 2006.201.16:12:22.46#ibcon#read 4, iclass 19, count 2 2006.201.16:12:22.46#ibcon#about to read 5, iclass 19, count 2 2006.201.16:12:22.46#ibcon#read 5, iclass 19, count 2 2006.201.16:12:22.46#ibcon#about to read 6, iclass 19, count 2 2006.201.16:12:22.46#ibcon#read 6, iclass 19, count 2 2006.201.16:12:22.46#ibcon#end of sib2, iclass 19, count 2 2006.201.16:12:22.46#ibcon#*after write, iclass 19, count 2 2006.201.16:12:22.46#ibcon#*before return 0, iclass 19, count 2 2006.201.16:12:22.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:12:22.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:12:22.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.16:12:22.46#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:22.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:12:22.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:12:22.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:12:22.58#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:12:22.58#ibcon#first serial, iclass 19, count 0 2006.201.16:12:22.58#ibcon#enter sib2, iclass 19, count 0 2006.201.16:12:22.58#ibcon#flushed, iclass 19, count 0 2006.201.16:12:22.58#ibcon#about to write, iclass 19, count 0 2006.201.16:12:22.58#ibcon#wrote, iclass 19, count 0 2006.201.16:12:22.58#ibcon#about to read 3, iclass 19, count 0 2006.201.16:12:22.60#ibcon#read 3, iclass 19, count 0 2006.201.16:12:22.60#ibcon#about to read 4, iclass 19, count 0 2006.201.16:12:22.60#ibcon#read 4, iclass 19, count 0 2006.201.16:12:22.60#ibcon#about to read 5, iclass 19, count 0 2006.201.16:12:22.60#ibcon#read 5, iclass 19, count 0 2006.201.16:12:22.60#ibcon#about to read 6, iclass 19, count 0 2006.201.16:12:22.60#ibcon#read 6, iclass 19, count 0 2006.201.16:12:22.60#ibcon#end of sib2, iclass 19, count 0 2006.201.16:12:22.60#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:12:22.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:12:22.60#ibcon#[25=USB\r\n] 2006.201.16:12:22.60#ibcon#*before write, iclass 19, count 0 2006.201.16:12:22.60#ibcon#enter sib2, iclass 19, count 0 2006.201.16:12:22.60#ibcon#flushed, iclass 19, count 0 2006.201.16:12:22.60#ibcon#about to write, iclass 19, count 0 2006.201.16:12:22.60#ibcon#wrote, iclass 19, count 0 2006.201.16:12:22.60#ibcon#about to read 3, iclass 19, count 0 2006.201.16:12:22.63#ibcon#read 3, iclass 19, count 0 2006.201.16:12:22.63#ibcon#about to read 4, iclass 19, count 0 2006.201.16:12:22.63#ibcon#read 4, iclass 19, count 0 2006.201.16:12:22.63#ibcon#about to read 5, iclass 19, count 0 2006.201.16:12:22.63#ibcon#read 5, iclass 19, count 0 2006.201.16:12:22.63#ibcon#about to read 6, iclass 19, count 0 2006.201.16:12:22.63#ibcon#read 6, iclass 19, count 0 2006.201.16:12:22.63#ibcon#end of sib2, iclass 19, count 0 2006.201.16:12:22.63#ibcon#*after write, iclass 19, count 0 2006.201.16:12:22.63#ibcon#*before return 0, iclass 19, count 0 2006.201.16:12:22.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:12:22.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:12:22.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:12:22.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:12:22.63$vck44/vblo=1,629.99 2006.201.16:12:22.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.16:12:22.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.16:12:22.63#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:22.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:22.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:22.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:22.63#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:12:22.63#ibcon#first serial, iclass 21, count 0 2006.201.16:12:22.63#ibcon#enter sib2, iclass 21, count 0 2006.201.16:12:22.63#ibcon#flushed, iclass 21, count 0 2006.201.16:12:22.63#ibcon#about to write, iclass 21, count 0 2006.201.16:12:22.63#ibcon#wrote, iclass 21, count 0 2006.201.16:12:22.63#ibcon#about to read 3, iclass 21, count 0 2006.201.16:12:22.65#ibcon#read 3, iclass 21, count 0 2006.201.16:12:22.65#ibcon#about to read 4, iclass 21, count 0 2006.201.16:12:22.65#ibcon#read 4, iclass 21, count 0 2006.201.16:12:22.65#ibcon#about to read 5, iclass 21, count 0 2006.201.16:12:22.65#ibcon#read 5, iclass 21, count 0 2006.201.16:12:22.65#ibcon#about to read 6, iclass 21, count 0 2006.201.16:12:22.65#ibcon#read 6, iclass 21, count 0 2006.201.16:12:22.65#ibcon#end of sib2, iclass 21, count 0 2006.201.16:12:22.65#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:12:22.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:12:22.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:12:22.65#ibcon#*before write, iclass 21, count 0 2006.201.16:12:22.65#ibcon#enter sib2, iclass 21, count 0 2006.201.16:12:22.65#ibcon#flushed, iclass 21, count 0 2006.201.16:12:22.65#ibcon#about to write, iclass 21, count 0 2006.201.16:12:22.65#ibcon#wrote, iclass 21, count 0 2006.201.16:12:22.65#ibcon#about to read 3, iclass 21, count 0 2006.201.16:12:22.70#ibcon#read 3, iclass 21, count 0 2006.201.16:12:22.70#ibcon#about to read 4, iclass 21, count 0 2006.201.16:12:22.70#ibcon#read 4, iclass 21, count 0 2006.201.16:12:22.70#ibcon#about to read 5, iclass 21, count 0 2006.201.16:12:22.70#ibcon#read 5, iclass 21, count 0 2006.201.16:12:22.70#ibcon#about to read 6, iclass 21, count 0 2006.201.16:12:22.70#ibcon#read 6, iclass 21, count 0 2006.201.16:12:22.70#ibcon#end of sib2, iclass 21, count 0 2006.201.16:12:22.70#ibcon#*after write, iclass 21, count 0 2006.201.16:12:22.70#ibcon#*before return 0, iclass 21, count 0 2006.201.16:12:22.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:22.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:12:22.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:12:22.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:12:22.70$vck44/vb=1,4 2006.201.16:12:22.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.16:12:22.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.16:12:22.70#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:22.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:22.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:22.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:22.70#ibcon#enter wrdev, iclass 23, count 2 2006.201.16:12:22.70#ibcon#first serial, iclass 23, count 2 2006.201.16:12:22.70#ibcon#enter sib2, iclass 23, count 2 2006.201.16:12:22.70#ibcon#flushed, iclass 23, count 2 2006.201.16:12:22.70#ibcon#about to write, iclass 23, count 2 2006.201.16:12:22.70#ibcon#wrote, iclass 23, count 2 2006.201.16:12:22.70#ibcon#about to read 3, iclass 23, count 2 2006.201.16:12:22.72#ibcon#read 3, iclass 23, count 2 2006.201.16:12:22.72#ibcon#about to read 4, iclass 23, count 2 2006.201.16:12:22.72#ibcon#read 4, iclass 23, count 2 2006.201.16:12:22.72#ibcon#about to read 5, iclass 23, count 2 2006.201.16:12:22.72#ibcon#read 5, iclass 23, count 2 2006.201.16:12:22.72#ibcon#about to read 6, iclass 23, count 2 2006.201.16:12:22.72#ibcon#read 6, iclass 23, count 2 2006.201.16:12:22.72#ibcon#end of sib2, iclass 23, count 2 2006.201.16:12:22.72#ibcon#*mode == 0, iclass 23, count 2 2006.201.16:12:22.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.16:12:22.72#ibcon#[27=AT01-04\r\n] 2006.201.16:12:22.72#ibcon#*before write, iclass 23, count 2 2006.201.16:12:22.72#ibcon#enter sib2, iclass 23, count 2 2006.201.16:12:22.72#ibcon#flushed, iclass 23, count 2 2006.201.16:12:22.72#ibcon#about to write, iclass 23, count 2 2006.201.16:12:22.72#ibcon#wrote, iclass 23, count 2 2006.201.16:12:22.72#ibcon#about to read 3, iclass 23, count 2 2006.201.16:12:22.75#ibcon#read 3, iclass 23, count 2 2006.201.16:12:22.75#ibcon#about to read 4, iclass 23, count 2 2006.201.16:12:22.75#ibcon#read 4, iclass 23, count 2 2006.201.16:12:22.75#ibcon#about to read 5, iclass 23, count 2 2006.201.16:12:22.75#ibcon#read 5, iclass 23, count 2 2006.201.16:12:22.75#ibcon#about to read 6, iclass 23, count 2 2006.201.16:12:22.75#ibcon#read 6, iclass 23, count 2 2006.201.16:12:22.75#ibcon#end of sib2, iclass 23, count 2 2006.201.16:12:22.75#ibcon#*after write, iclass 23, count 2 2006.201.16:12:22.75#ibcon#*before return 0, iclass 23, count 2 2006.201.16:12:22.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:22.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:12:22.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.16:12:22.75#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:22.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:22.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:22.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:22.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:12:22.87#ibcon#first serial, iclass 23, count 0 2006.201.16:12:22.87#ibcon#enter sib2, iclass 23, count 0 2006.201.16:12:22.87#ibcon#flushed, iclass 23, count 0 2006.201.16:12:22.87#ibcon#about to write, iclass 23, count 0 2006.201.16:12:22.87#ibcon#wrote, iclass 23, count 0 2006.201.16:12:22.87#ibcon#about to read 3, iclass 23, count 0 2006.201.16:12:22.89#ibcon#read 3, iclass 23, count 0 2006.201.16:12:22.89#ibcon#about to read 4, iclass 23, count 0 2006.201.16:12:22.89#ibcon#read 4, iclass 23, count 0 2006.201.16:12:22.89#ibcon#about to read 5, iclass 23, count 0 2006.201.16:12:22.89#ibcon#read 5, iclass 23, count 0 2006.201.16:12:22.89#ibcon#about to read 6, iclass 23, count 0 2006.201.16:12:22.89#ibcon#read 6, iclass 23, count 0 2006.201.16:12:22.89#ibcon#end of sib2, iclass 23, count 0 2006.201.16:12:22.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:12:22.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:12:22.89#ibcon#[27=USB\r\n] 2006.201.16:12:22.89#ibcon#*before write, iclass 23, count 0 2006.201.16:12:22.89#ibcon#enter sib2, iclass 23, count 0 2006.201.16:12:22.89#ibcon#flushed, iclass 23, count 0 2006.201.16:12:22.89#ibcon#about to write, iclass 23, count 0 2006.201.16:12:22.89#ibcon#wrote, iclass 23, count 0 2006.201.16:12:22.89#ibcon#about to read 3, iclass 23, count 0 2006.201.16:12:22.92#ibcon#read 3, iclass 23, count 0 2006.201.16:12:22.92#ibcon#about to read 4, iclass 23, count 0 2006.201.16:12:22.92#ibcon#read 4, iclass 23, count 0 2006.201.16:12:22.92#ibcon#about to read 5, iclass 23, count 0 2006.201.16:12:22.92#ibcon#read 5, iclass 23, count 0 2006.201.16:12:22.92#ibcon#about to read 6, iclass 23, count 0 2006.201.16:12:22.92#ibcon#read 6, iclass 23, count 0 2006.201.16:12:22.92#ibcon#end of sib2, iclass 23, count 0 2006.201.16:12:22.92#ibcon#*after write, iclass 23, count 0 2006.201.16:12:22.92#ibcon#*before return 0, iclass 23, count 0 2006.201.16:12:22.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:22.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:12:22.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:12:22.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:12:22.92$vck44/vblo=2,634.99 2006.201.16:12:22.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.16:12:22.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.16:12:22.92#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:22.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:22.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:22.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:22.92#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:12:22.92#ibcon#first serial, iclass 25, count 0 2006.201.16:12:22.92#ibcon#enter sib2, iclass 25, count 0 2006.201.16:12:22.92#ibcon#flushed, iclass 25, count 0 2006.201.16:12:22.92#ibcon#about to write, iclass 25, count 0 2006.201.16:12:22.92#ibcon#wrote, iclass 25, count 0 2006.201.16:12:22.92#ibcon#about to read 3, iclass 25, count 0 2006.201.16:12:22.94#ibcon#read 3, iclass 25, count 0 2006.201.16:12:22.94#ibcon#about to read 4, iclass 25, count 0 2006.201.16:12:22.94#ibcon#read 4, iclass 25, count 0 2006.201.16:12:22.94#ibcon#about to read 5, iclass 25, count 0 2006.201.16:12:22.94#ibcon#read 5, iclass 25, count 0 2006.201.16:12:22.94#ibcon#about to read 6, iclass 25, count 0 2006.201.16:12:22.94#ibcon#read 6, iclass 25, count 0 2006.201.16:12:22.94#ibcon#end of sib2, iclass 25, count 0 2006.201.16:12:22.94#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:12:22.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:12:22.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:12:22.94#ibcon#*before write, iclass 25, count 0 2006.201.16:12:22.94#ibcon#enter sib2, iclass 25, count 0 2006.201.16:12:22.94#ibcon#flushed, iclass 25, count 0 2006.201.16:12:22.94#ibcon#about to write, iclass 25, count 0 2006.201.16:12:22.94#ibcon#wrote, iclass 25, count 0 2006.201.16:12:22.94#ibcon#about to read 3, iclass 25, count 0 2006.201.16:12:22.98#ibcon#read 3, iclass 25, count 0 2006.201.16:12:22.98#ibcon#about to read 4, iclass 25, count 0 2006.201.16:12:22.98#ibcon#read 4, iclass 25, count 0 2006.201.16:12:22.98#ibcon#about to read 5, iclass 25, count 0 2006.201.16:12:22.98#ibcon#read 5, iclass 25, count 0 2006.201.16:12:22.98#ibcon#about to read 6, iclass 25, count 0 2006.201.16:12:22.98#ibcon#read 6, iclass 25, count 0 2006.201.16:12:22.98#ibcon#end of sib2, iclass 25, count 0 2006.201.16:12:22.98#ibcon#*after write, iclass 25, count 0 2006.201.16:12:22.98#ibcon#*before return 0, iclass 25, count 0 2006.201.16:12:22.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:22.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:12:22.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:12:22.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:12:22.98$vck44/vb=2,5 2006.201.16:12:22.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.16:12:22.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.16:12:22.98#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:22.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:23.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:23.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:23.04#ibcon#enter wrdev, iclass 27, count 2 2006.201.16:12:23.04#ibcon#first serial, iclass 27, count 2 2006.201.16:12:23.04#ibcon#enter sib2, iclass 27, count 2 2006.201.16:12:23.04#ibcon#flushed, iclass 27, count 2 2006.201.16:12:23.04#ibcon#about to write, iclass 27, count 2 2006.201.16:12:23.04#ibcon#wrote, iclass 27, count 2 2006.201.16:12:23.04#ibcon#about to read 3, iclass 27, count 2 2006.201.16:12:23.06#ibcon#read 3, iclass 27, count 2 2006.201.16:12:23.06#ibcon#about to read 4, iclass 27, count 2 2006.201.16:12:23.06#ibcon#read 4, iclass 27, count 2 2006.201.16:12:23.06#ibcon#about to read 5, iclass 27, count 2 2006.201.16:12:23.06#ibcon#read 5, iclass 27, count 2 2006.201.16:12:23.06#ibcon#about to read 6, iclass 27, count 2 2006.201.16:12:23.06#ibcon#read 6, iclass 27, count 2 2006.201.16:12:23.06#ibcon#end of sib2, iclass 27, count 2 2006.201.16:12:23.06#ibcon#*mode == 0, iclass 27, count 2 2006.201.16:12:23.06#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.16:12:23.06#ibcon#[27=AT02-05\r\n] 2006.201.16:12:23.06#ibcon#*before write, iclass 27, count 2 2006.201.16:12:23.06#ibcon#enter sib2, iclass 27, count 2 2006.201.16:12:23.06#ibcon#flushed, iclass 27, count 2 2006.201.16:12:23.06#ibcon#about to write, iclass 27, count 2 2006.201.16:12:23.06#ibcon#wrote, iclass 27, count 2 2006.201.16:12:23.06#ibcon#about to read 3, iclass 27, count 2 2006.201.16:12:23.09#ibcon#read 3, iclass 27, count 2 2006.201.16:12:23.09#ibcon#about to read 4, iclass 27, count 2 2006.201.16:12:23.09#ibcon#read 4, iclass 27, count 2 2006.201.16:12:23.09#ibcon#about to read 5, iclass 27, count 2 2006.201.16:12:23.09#ibcon#read 5, iclass 27, count 2 2006.201.16:12:23.09#ibcon#about to read 6, iclass 27, count 2 2006.201.16:12:23.09#ibcon#read 6, iclass 27, count 2 2006.201.16:12:23.09#ibcon#end of sib2, iclass 27, count 2 2006.201.16:12:23.09#ibcon#*after write, iclass 27, count 2 2006.201.16:12:23.09#ibcon#*before return 0, iclass 27, count 2 2006.201.16:12:23.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:23.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:12:23.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.16:12:23.09#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:23.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:23.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:23.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:23.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:12:23.21#ibcon#first serial, iclass 27, count 0 2006.201.16:12:23.21#ibcon#enter sib2, iclass 27, count 0 2006.201.16:12:23.21#ibcon#flushed, iclass 27, count 0 2006.201.16:12:23.21#ibcon#about to write, iclass 27, count 0 2006.201.16:12:23.21#ibcon#wrote, iclass 27, count 0 2006.201.16:12:23.21#ibcon#about to read 3, iclass 27, count 0 2006.201.16:12:23.23#ibcon#read 3, iclass 27, count 0 2006.201.16:12:23.23#ibcon#about to read 4, iclass 27, count 0 2006.201.16:12:23.23#ibcon#read 4, iclass 27, count 0 2006.201.16:12:23.23#ibcon#about to read 5, iclass 27, count 0 2006.201.16:12:23.23#ibcon#read 5, iclass 27, count 0 2006.201.16:12:23.23#ibcon#about to read 6, iclass 27, count 0 2006.201.16:12:23.23#ibcon#read 6, iclass 27, count 0 2006.201.16:12:23.23#ibcon#end of sib2, iclass 27, count 0 2006.201.16:12:23.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:12:23.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:12:23.23#ibcon#[27=USB\r\n] 2006.201.16:12:23.23#ibcon#*before write, iclass 27, count 0 2006.201.16:12:23.23#ibcon#enter sib2, iclass 27, count 0 2006.201.16:12:23.23#ibcon#flushed, iclass 27, count 0 2006.201.16:12:23.23#ibcon#about to write, iclass 27, count 0 2006.201.16:12:23.23#ibcon#wrote, iclass 27, count 0 2006.201.16:12:23.23#ibcon#about to read 3, iclass 27, count 0 2006.201.16:12:23.26#ibcon#read 3, iclass 27, count 0 2006.201.16:12:23.26#ibcon#about to read 4, iclass 27, count 0 2006.201.16:12:23.26#ibcon#read 4, iclass 27, count 0 2006.201.16:12:23.26#ibcon#about to read 5, iclass 27, count 0 2006.201.16:12:23.26#ibcon#read 5, iclass 27, count 0 2006.201.16:12:23.26#ibcon#about to read 6, iclass 27, count 0 2006.201.16:12:23.26#ibcon#read 6, iclass 27, count 0 2006.201.16:12:23.26#ibcon#end of sib2, iclass 27, count 0 2006.201.16:12:23.26#ibcon#*after write, iclass 27, count 0 2006.201.16:12:23.26#ibcon#*before return 0, iclass 27, count 0 2006.201.16:12:23.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:23.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:12:23.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:12:23.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:12:23.26$vck44/vblo=3,649.99 2006.201.16:12:23.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.16:12:23.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.16:12:23.26#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:23.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:23.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:23.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:23.26#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:12:23.26#ibcon#first serial, iclass 29, count 0 2006.201.16:12:23.26#ibcon#enter sib2, iclass 29, count 0 2006.201.16:12:23.26#ibcon#flushed, iclass 29, count 0 2006.201.16:12:23.26#ibcon#about to write, iclass 29, count 0 2006.201.16:12:23.26#ibcon#wrote, iclass 29, count 0 2006.201.16:12:23.26#ibcon#about to read 3, iclass 29, count 0 2006.201.16:12:23.28#ibcon#read 3, iclass 29, count 0 2006.201.16:12:23.28#ibcon#about to read 4, iclass 29, count 0 2006.201.16:12:23.28#ibcon#read 4, iclass 29, count 0 2006.201.16:12:23.28#ibcon#about to read 5, iclass 29, count 0 2006.201.16:12:23.28#ibcon#read 5, iclass 29, count 0 2006.201.16:12:23.28#ibcon#about to read 6, iclass 29, count 0 2006.201.16:12:23.28#ibcon#read 6, iclass 29, count 0 2006.201.16:12:23.28#ibcon#end of sib2, iclass 29, count 0 2006.201.16:12:23.28#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:12:23.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:12:23.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:12:23.28#ibcon#*before write, iclass 29, count 0 2006.201.16:12:23.28#ibcon#enter sib2, iclass 29, count 0 2006.201.16:12:23.28#ibcon#flushed, iclass 29, count 0 2006.201.16:12:23.28#ibcon#about to write, iclass 29, count 0 2006.201.16:12:23.28#ibcon#wrote, iclass 29, count 0 2006.201.16:12:23.28#ibcon#about to read 3, iclass 29, count 0 2006.201.16:12:23.32#ibcon#read 3, iclass 29, count 0 2006.201.16:12:23.32#ibcon#about to read 4, iclass 29, count 0 2006.201.16:12:23.32#ibcon#read 4, iclass 29, count 0 2006.201.16:12:23.32#ibcon#about to read 5, iclass 29, count 0 2006.201.16:12:23.32#ibcon#read 5, iclass 29, count 0 2006.201.16:12:23.32#ibcon#about to read 6, iclass 29, count 0 2006.201.16:12:23.32#ibcon#read 6, iclass 29, count 0 2006.201.16:12:23.32#ibcon#end of sib2, iclass 29, count 0 2006.201.16:12:23.32#ibcon#*after write, iclass 29, count 0 2006.201.16:12:23.32#ibcon#*before return 0, iclass 29, count 0 2006.201.16:12:23.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:23.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:12:23.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:12:23.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:12:23.32$vck44/vb=3,4 2006.201.16:12:23.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.16:12:23.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.16:12:23.32#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:23.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:23.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:23.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:23.38#ibcon#enter wrdev, iclass 31, count 2 2006.201.16:12:23.38#ibcon#first serial, iclass 31, count 2 2006.201.16:12:23.38#ibcon#enter sib2, iclass 31, count 2 2006.201.16:12:23.38#ibcon#flushed, iclass 31, count 2 2006.201.16:12:23.38#ibcon#about to write, iclass 31, count 2 2006.201.16:12:23.38#ibcon#wrote, iclass 31, count 2 2006.201.16:12:23.38#ibcon#about to read 3, iclass 31, count 2 2006.201.16:12:23.40#ibcon#read 3, iclass 31, count 2 2006.201.16:12:23.40#ibcon#about to read 4, iclass 31, count 2 2006.201.16:12:23.40#ibcon#read 4, iclass 31, count 2 2006.201.16:12:23.40#ibcon#about to read 5, iclass 31, count 2 2006.201.16:12:23.40#ibcon#read 5, iclass 31, count 2 2006.201.16:12:23.40#ibcon#about to read 6, iclass 31, count 2 2006.201.16:12:23.40#ibcon#read 6, iclass 31, count 2 2006.201.16:12:23.40#ibcon#end of sib2, iclass 31, count 2 2006.201.16:12:23.40#ibcon#*mode == 0, iclass 31, count 2 2006.201.16:12:23.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.16:12:23.40#ibcon#[27=AT03-04\r\n] 2006.201.16:12:23.40#ibcon#*before write, iclass 31, count 2 2006.201.16:12:23.40#ibcon#enter sib2, iclass 31, count 2 2006.201.16:12:23.40#ibcon#flushed, iclass 31, count 2 2006.201.16:12:23.40#ibcon#about to write, iclass 31, count 2 2006.201.16:12:23.40#ibcon#wrote, iclass 31, count 2 2006.201.16:12:23.40#ibcon#about to read 3, iclass 31, count 2 2006.201.16:12:23.43#ibcon#read 3, iclass 31, count 2 2006.201.16:12:23.43#ibcon#about to read 4, iclass 31, count 2 2006.201.16:12:23.43#ibcon#read 4, iclass 31, count 2 2006.201.16:12:23.43#ibcon#about to read 5, iclass 31, count 2 2006.201.16:12:23.43#ibcon#read 5, iclass 31, count 2 2006.201.16:12:23.43#ibcon#about to read 6, iclass 31, count 2 2006.201.16:12:23.43#ibcon#read 6, iclass 31, count 2 2006.201.16:12:23.43#ibcon#end of sib2, iclass 31, count 2 2006.201.16:12:23.43#ibcon#*after write, iclass 31, count 2 2006.201.16:12:23.43#ibcon#*before return 0, iclass 31, count 2 2006.201.16:12:23.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:23.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:12:23.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.16:12:23.43#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:23.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:23.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:23.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:23.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:12:23.55#ibcon#first serial, iclass 31, count 0 2006.201.16:12:23.55#ibcon#enter sib2, iclass 31, count 0 2006.201.16:12:23.55#ibcon#flushed, iclass 31, count 0 2006.201.16:12:23.55#ibcon#about to write, iclass 31, count 0 2006.201.16:12:23.55#ibcon#wrote, iclass 31, count 0 2006.201.16:12:23.55#ibcon#about to read 3, iclass 31, count 0 2006.201.16:12:23.57#ibcon#read 3, iclass 31, count 0 2006.201.16:12:23.57#ibcon#about to read 4, iclass 31, count 0 2006.201.16:12:23.57#ibcon#read 4, iclass 31, count 0 2006.201.16:12:23.57#ibcon#about to read 5, iclass 31, count 0 2006.201.16:12:23.57#ibcon#read 5, iclass 31, count 0 2006.201.16:12:23.57#ibcon#about to read 6, iclass 31, count 0 2006.201.16:12:23.57#ibcon#read 6, iclass 31, count 0 2006.201.16:12:23.57#ibcon#end of sib2, iclass 31, count 0 2006.201.16:12:23.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:12:23.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:12:23.57#ibcon#[27=USB\r\n] 2006.201.16:12:23.57#ibcon#*before write, iclass 31, count 0 2006.201.16:12:23.57#ibcon#enter sib2, iclass 31, count 0 2006.201.16:12:23.57#ibcon#flushed, iclass 31, count 0 2006.201.16:12:23.57#ibcon#about to write, iclass 31, count 0 2006.201.16:12:23.57#ibcon#wrote, iclass 31, count 0 2006.201.16:12:23.57#ibcon#about to read 3, iclass 31, count 0 2006.201.16:12:23.60#ibcon#read 3, iclass 31, count 0 2006.201.16:12:23.60#ibcon#about to read 4, iclass 31, count 0 2006.201.16:12:23.60#ibcon#read 4, iclass 31, count 0 2006.201.16:12:23.60#ibcon#about to read 5, iclass 31, count 0 2006.201.16:12:23.60#ibcon#read 5, iclass 31, count 0 2006.201.16:12:23.60#ibcon#about to read 6, iclass 31, count 0 2006.201.16:12:23.60#ibcon#read 6, iclass 31, count 0 2006.201.16:12:23.60#ibcon#end of sib2, iclass 31, count 0 2006.201.16:12:23.60#ibcon#*after write, iclass 31, count 0 2006.201.16:12:23.60#ibcon#*before return 0, iclass 31, count 0 2006.201.16:12:23.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:23.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:12:23.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:12:23.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:12:23.60$vck44/vblo=4,679.99 2006.201.16:12:23.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.16:12:23.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.16:12:23.60#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:23.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:23.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:23.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:23.60#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:12:23.60#ibcon#first serial, iclass 33, count 0 2006.201.16:12:23.60#ibcon#enter sib2, iclass 33, count 0 2006.201.16:12:23.60#ibcon#flushed, iclass 33, count 0 2006.201.16:12:23.60#ibcon#about to write, iclass 33, count 0 2006.201.16:12:23.60#ibcon#wrote, iclass 33, count 0 2006.201.16:12:23.60#ibcon#about to read 3, iclass 33, count 0 2006.201.16:12:23.62#ibcon#read 3, iclass 33, count 0 2006.201.16:12:23.62#ibcon#about to read 4, iclass 33, count 0 2006.201.16:12:23.62#ibcon#read 4, iclass 33, count 0 2006.201.16:12:23.62#ibcon#about to read 5, iclass 33, count 0 2006.201.16:12:23.62#ibcon#read 5, iclass 33, count 0 2006.201.16:12:23.62#ibcon#about to read 6, iclass 33, count 0 2006.201.16:12:23.62#ibcon#read 6, iclass 33, count 0 2006.201.16:12:23.62#ibcon#end of sib2, iclass 33, count 0 2006.201.16:12:23.62#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:12:23.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:12:23.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:12:23.62#ibcon#*before write, iclass 33, count 0 2006.201.16:12:23.62#ibcon#enter sib2, iclass 33, count 0 2006.201.16:12:23.62#ibcon#flushed, iclass 33, count 0 2006.201.16:12:23.62#ibcon#about to write, iclass 33, count 0 2006.201.16:12:23.62#ibcon#wrote, iclass 33, count 0 2006.201.16:12:23.62#ibcon#about to read 3, iclass 33, count 0 2006.201.16:12:23.67#ibcon#read 3, iclass 33, count 0 2006.201.16:12:23.67#ibcon#about to read 4, iclass 33, count 0 2006.201.16:12:23.67#ibcon#read 4, iclass 33, count 0 2006.201.16:12:23.67#ibcon#about to read 5, iclass 33, count 0 2006.201.16:12:23.67#ibcon#read 5, iclass 33, count 0 2006.201.16:12:23.67#ibcon#about to read 6, iclass 33, count 0 2006.201.16:12:23.67#ibcon#read 6, iclass 33, count 0 2006.201.16:12:23.67#ibcon#end of sib2, iclass 33, count 0 2006.201.16:12:23.67#ibcon#*after write, iclass 33, count 0 2006.201.16:12:23.67#ibcon#*before return 0, iclass 33, count 0 2006.201.16:12:23.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:23.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:12:23.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:12:23.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:12:23.67$vck44/vb=4,5 2006.201.16:12:23.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.16:12:23.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.16:12:23.67#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:23.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:23.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:23.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:23.72#ibcon#enter wrdev, iclass 35, count 2 2006.201.16:12:23.72#ibcon#first serial, iclass 35, count 2 2006.201.16:12:23.72#ibcon#enter sib2, iclass 35, count 2 2006.201.16:12:23.72#ibcon#flushed, iclass 35, count 2 2006.201.16:12:23.72#ibcon#about to write, iclass 35, count 2 2006.201.16:12:23.72#ibcon#wrote, iclass 35, count 2 2006.201.16:12:23.72#ibcon#about to read 3, iclass 35, count 2 2006.201.16:12:23.74#ibcon#read 3, iclass 35, count 2 2006.201.16:12:23.74#ibcon#about to read 4, iclass 35, count 2 2006.201.16:12:23.74#ibcon#read 4, iclass 35, count 2 2006.201.16:12:23.74#ibcon#about to read 5, iclass 35, count 2 2006.201.16:12:23.74#ibcon#read 5, iclass 35, count 2 2006.201.16:12:23.74#ibcon#about to read 6, iclass 35, count 2 2006.201.16:12:23.74#ibcon#read 6, iclass 35, count 2 2006.201.16:12:23.74#ibcon#end of sib2, iclass 35, count 2 2006.201.16:12:23.74#ibcon#*mode == 0, iclass 35, count 2 2006.201.16:12:23.74#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.16:12:23.74#ibcon#[27=AT04-05\r\n] 2006.201.16:12:23.74#ibcon#*before write, iclass 35, count 2 2006.201.16:12:23.74#ibcon#enter sib2, iclass 35, count 2 2006.201.16:12:23.74#ibcon#flushed, iclass 35, count 2 2006.201.16:12:23.74#ibcon#about to write, iclass 35, count 2 2006.201.16:12:23.74#ibcon#wrote, iclass 35, count 2 2006.201.16:12:23.74#ibcon#about to read 3, iclass 35, count 2 2006.201.16:12:23.77#ibcon#read 3, iclass 35, count 2 2006.201.16:12:23.77#ibcon#about to read 4, iclass 35, count 2 2006.201.16:12:23.77#ibcon#read 4, iclass 35, count 2 2006.201.16:12:23.77#ibcon#about to read 5, iclass 35, count 2 2006.201.16:12:23.77#ibcon#read 5, iclass 35, count 2 2006.201.16:12:23.77#ibcon#about to read 6, iclass 35, count 2 2006.201.16:12:23.77#ibcon#read 6, iclass 35, count 2 2006.201.16:12:23.77#ibcon#end of sib2, iclass 35, count 2 2006.201.16:12:23.77#ibcon#*after write, iclass 35, count 2 2006.201.16:12:23.77#ibcon#*before return 0, iclass 35, count 2 2006.201.16:12:23.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:23.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:12:23.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.16:12:23.77#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:23.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:23.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:23.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:23.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:12:23.89#ibcon#first serial, iclass 35, count 0 2006.201.16:12:23.89#ibcon#enter sib2, iclass 35, count 0 2006.201.16:12:23.89#ibcon#flushed, iclass 35, count 0 2006.201.16:12:23.89#ibcon#about to write, iclass 35, count 0 2006.201.16:12:23.89#ibcon#wrote, iclass 35, count 0 2006.201.16:12:23.89#ibcon#about to read 3, iclass 35, count 0 2006.201.16:12:23.91#ibcon#read 3, iclass 35, count 0 2006.201.16:12:23.91#ibcon#about to read 4, iclass 35, count 0 2006.201.16:12:23.91#ibcon#read 4, iclass 35, count 0 2006.201.16:12:23.91#ibcon#about to read 5, iclass 35, count 0 2006.201.16:12:23.91#ibcon#read 5, iclass 35, count 0 2006.201.16:12:23.91#ibcon#about to read 6, iclass 35, count 0 2006.201.16:12:23.91#ibcon#read 6, iclass 35, count 0 2006.201.16:12:23.91#ibcon#end of sib2, iclass 35, count 0 2006.201.16:12:23.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:12:23.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:12:23.91#ibcon#[27=USB\r\n] 2006.201.16:12:23.91#ibcon#*before write, iclass 35, count 0 2006.201.16:12:23.91#ibcon#enter sib2, iclass 35, count 0 2006.201.16:12:23.91#ibcon#flushed, iclass 35, count 0 2006.201.16:12:23.91#ibcon#about to write, iclass 35, count 0 2006.201.16:12:23.91#ibcon#wrote, iclass 35, count 0 2006.201.16:12:23.91#ibcon#about to read 3, iclass 35, count 0 2006.201.16:12:23.94#ibcon#read 3, iclass 35, count 0 2006.201.16:12:23.94#ibcon#about to read 4, iclass 35, count 0 2006.201.16:12:23.94#ibcon#read 4, iclass 35, count 0 2006.201.16:12:23.94#ibcon#about to read 5, iclass 35, count 0 2006.201.16:12:23.94#ibcon#read 5, iclass 35, count 0 2006.201.16:12:23.94#ibcon#about to read 6, iclass 35, count 0 2006.201.16:12:23.94#ibcon#read 6, iclass 35, count 0 2006.201.16:12:23.94#ibcon#end of sib2, iclass 35, count 0 2006.201.16:12:23.94#ibcon#*after write, iclass 35, count 0 2006.201.16:12:23.94#ibcon#*before return 0, iclass 35, count 0 2006.201.16:12:23.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:23.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:12:23.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:12:23.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:12:23.94$vck44/vblo=5,709.99 2006.201.16:12:23.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.16:12:23.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.16:12:23.94#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:23.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:23.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:23.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:23.94#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:12:23.94#ibcon#first serial, iclass 37, count 0 2006.201.16:12:23.94#ibcon#enter sib2, iclass 37, count 0 2006.201.16:12:23.94#ibcon#flushed, iclass 37, count 0 2006.201.16:12:23.94#ibcon#about to write, iclass 37, count 0 2006.201.16:12:23.94#ibcon#wrote, iclass 37, count 0 2006.201.16:12:23.94#ibcon#about to read 3, iclass 37, count 0 2006.201.16:12:23.96#ibcon#read 3, iclass 37, count 0 2006.201.16:12:23.96#ibcon#about to read 4, iclass 37, count 0 2006.201.16:12:23.96#ibcon#read 4, iclass 37, count 0 2006.201.16:12:23.96#ibcon#about to read 5, iclass 37, count 0 2006.201.16:12:23.96#ibcon#read 5, iclass 37, count 0 2006.201.16:12:23.96#ibcon#about to read 6, iclass 37, count 0 2006.201.16:12:23.96#ibcon#read 6, iclass 37, count 0 2006.201.16:12:23.96#ibcon#end of sib2, iclass 37, count 0 2006.201.16:12:23.96#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:12:23.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:12:23.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:12:23.96#ibcon#*before write, iclass 37, count 0 2006.201.16:12:23.96#ibcon#enter sib2, iclass 37, count 0 2006.201.16:12:23.96#ibcon#flushed, iclass 37, count 0 2006.201.16:12:23.96#ibcon#about to write, iclass 37, count 0 2006.201.16:12:23.96#ibcon#wrote, iclass 37, count 0 2006.201.16:12:23.96#ibcon#about to read 3, iclass 37, count 0 2006.201.16:12:24.00#ibcon#read 3, iclass 37, count 0 2006.201.16:12:24.00#ibcon#about to read 4, iclass 37, count 0 2006.201.16:12:24.00#ibcon#read 4, iclass 37, count 0 2006.201.16:12:24.00#ibcon#about to read 5, iclass 37, count 0 2006.201.16:12:24.00#ibcon#read 5, iclass 37, count 0 2006.201.16:12:24.00#ibcon#about to read 6, iclass 37, count 0 2006.201.16:12:24.00#ibcon#read 6, iclass 37, count 0 2006.201.16:12:24.00#ibcon#end of sib2, iclass 37, count 0 2006.201.16:12:24.00#ibcon#*after write, iclass 37, count 0 2006.201.16:12:24.00#ibcon#*before return 0, iclass 37, count 0 2006.201.16:12:24.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:24.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:12:24.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:12:24.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:12:24.00$vck44/vb=5,4 2006.201.16:12:24.00#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.16:12:24.00#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.16:12:24.00#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:24.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:24.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:24.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:24.06#ibcon#enter wrdev, iclass 39, count 2 2006.201.16:12:24.06#ibcon#first serial, iclass 39, count 2 2006.201.16:12:24.06#ibcon#enter sib2, iclass 39, count 2 2006.201.16:12:24.06#ibcon#flushed, iclass 39, count 2 2006.201.16:12:24.06#ibcon#about to write, iclass 39, count 2 2006.201.16:12:24.06#ibcon#wrote, iclass 39, count 2 2006.201.16:12:24.06#ibcon#about to read 3, iclass 39, count 2 2006.201.16:12:24.08#ibcon#read 3, iclass 39, count 2 2006.201.16:12:24.08#ibcon#about to read 4, iclass 39, count 2 2006.201.16:12:24.08#ibcon#read 4, iclass 39, count 2 2006.201.16:12:24.08#ibcon#about to read 5, iclass 39, count 2 2006.201.16:12:24.08#ibcon#read 5, iclass 39, count 2 2006.201.16:12:24.08#ibcon#about to read 6, iclass 39, count 2 2006.201.16:12:24.08#ibcon#read 6, iclass 39, count 2 2006.201.16:12:24.08#ibcon#end of sib2, iclass 39, count 2 2006.201.16:12:24.08#ibcon#*mode == 0, iclass 39, count 2 2006.201.16:12:24.08#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.16:12:24.08#ibcon#[27=AT05-04\r\n] 2006.201.16:12:24.08#ibcon#*before write, iclass 39, count 2 2006.201.16:12:24.08#ibcon#enter sib2, iclass 39, count 2 2006.201.16:12:24.08#ibcon#flushed, iclass 39, count 2 2006.201.16:12:24.08#ibcon#about to write, iclass 39, count 2 2006.201.16:12:24.08#ibcon#wrote, iclass 39, count 2 2006.201.16:12:24.08#ibcon#about to read 3, iclass 39, count 2 2006.201.16:12:24.11#ibcon#read 3, iclass 39, count 2 2006.201.16:12:24.11#ibcon#about to read 4, iclass 39, count 2 2006.201.16:12:24.11#ibcon#read 4, iclass 39, count 2 2006.201.16:12:24.11#ibcon#about to read 5, iclass 39, count 2 2006.201.16:12:24.11#ibcon#read 5, iclass 39, count 2 2006.201.16:12:24.11#ibcon#about to read 6, iclass 39, count 2 2006.201.16:12:24.11#ibcon#read 6, iclass 39, count 2 2006.201.16:12:24.11#ibcon#end of sib2, iclass 39, count 2 2006.201.16:12:24.11#ibcon#*after write, iclass 39, count 2 2006.201.16:12:24.11#ibcon#*before return 0, iclass 39, count 2 2006.201.16:12:24.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:24.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:12:24.11#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.16:12:24.11#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:24.11#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:24.23#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:24.23#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:24.23#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:12:24.23#ibcon#first serial, iclass 39, count 0 2006.201.16:12:24.23#ibcon#enter sib2, iclass 39, count 0 2006.201.16:12:24.23#ibcon#flushed, iclass 39, count 0 2006.201.16:12:24.23#ibcon#about to write, iclass 39, count 0 2006.201.16:12:24.23#ibcon#wrote, iclass 39, count 0 2006.201.16:12:24.23#ibcon#about to read 3, iclass 39, count 0 2006.201.16:12:24.25#ibcon#read 3, iclass 39, count 0 2006.201.16:12:24.25#ibcon#about to read 4, iclass 39, count 0 2006.201.16:12:24.25#ibcon#read 4, iclass 39, count 0 2006.201.16:12:24.25#ibcon#about to read 5, iclass 39, count 0 2006.201.16:12:24.25#ibcon#read 5, iclass 39, count 0 2006.201.16:12:24.25#ibcon#about to read 6, iclass 39, count 0 2006.201.16:12:24.25#ibcon#read 6, iclass 39, count 0 2006.201.16:12:24.25#ibcon#end of sib2, iclass 39, count 0 2006.201.16:12:24.25#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:12:24.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:12:24.25#ibcon#[27=USB\r\n] 2006.201.16:12:24.25#ibcon#*before write, iclass 39, count 0 2006.201.16:12:24.25#ibcon#enter sib2, iclass 39, count 0 2006.201.16:12:24.25#ibcon#flushed, iclass 39, count 0 2006.201.16:12:24.25#ibcon#about to write, iclass 39, count 0 2006.201.16:12:24.25#ibcon#wrote, iclass 39, count 0 2006.201.16:12:24.25#ibcon#about to read 3, iclass 39, count 0 2006.201.16:12:24.28#ibcon#read 3, iclass 39, count 0 2006.201.16:12:24.28#ibcon#about to read 4, iclass 39, count 0 2006.201.16:12:24.28#ibcon#read 4, iclass 39, count 0 2006.201.16:12:24.28#ibcon#about to read 5, iclass 39, count 0 2006.201.16:12:24.28#ibcon#read 5, iclass 39, count 0 2006.201.16:12:24.28#ibcon#about to read 6, iclass 39, count 0 2006.201.16:12:24.28#ibcon#read 6, iclass 39, count 0 2006.201.16:12:24.28#ibcon#end of sib2, iclass 39, count 0 2006.201.16:12:24.28#ibcon#*after write, iclass 39, count 0 2006.201.16:12:24.28#ibcon#*before return 0, iclass 39, count 0 2006.201.16:12:24.28#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:24.28#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:12:24.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:12:24.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:12:24.28$vck44/vblo=6,719.99 2006.201.16:12:24.28#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.16:12:24.28#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.16:12:24.28#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:24.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:12:24.28#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:12:24.28#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:12:24.28#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:12:24.28#ibcon#first serial, iclass 2, count 0 2006.201.16:12:24.28#ibcon#enter sib2, iclass 2, count 0 2006.201.16:12:24.28#ibcon#flushed, iclass 2, count 0 2006.201.16:12:24.28#ibcon#about to write, iclass 2, count 0 2006.201.16:12:24.28#ibcon#wrote, iclass 2, count 0 2006.201.16:12:24.28#ibcon#about to read 3, iclass 2, count 0 2006.201.16:12:24.30#ibcon#read 3, iclass 2, count 0 2006.201.16:12:24.30#ibcon#about to read 4, iclass 2, count 0 2006.201.16:12:24.30#ibcon#read 4, iclass 2, count 0 2006.201.16:12:24.30#ibcon#about to read 5, iclass 2, count 0 2006.201.16:12:24.30#ibcon#read 5, iclass 2, count 0 2006.201.16:12:24.30#ibcon#about to read 6, iclass 2, count 0 2006.201.16:12:24.30#ibcon#read 6, iclass 2, count 0 2006.201.16:12:24.30#ibcon#end of sib2, iclass 2, count 0 2006.201.16:12:24.30#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:12:24.30#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:12:24.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:12:24.30#ibcon#*before write, iclass 2, count 0 2006.201.16:12:24.30#ibcon#enter sib2, iclass 2, count 0 2006.201.16:12:24.30#ibcon#flushed, iclass 2, count 0 2006.201.16:12:24.30#ibcon#about to write, iclass 2, count 0 2006.201.16:12:24.30#ibcon#wrote, iclass 2, count 0 2006.201.16:12:24.30#ibcon#about to read 3, iclass 2, count 0 2006.201.16:12:24.35#ibcon#read 3, iclass 2, count 0 2006.201.16:12:24.35#ibcon#about to read 4, iclass 2, count 0 2006.201.16:12:24.35#ibcon#read 4, iclass 2, count 0 2006.201.16:12:24.35#ibcon#about to read 5, iclass 2, count 0 2006.201.16:12:24.35#ibcon#read 5, iclass 2, count 0 2006.201.16:12:24.35#ibcon#about to read 6, iclass 2, count 0 2006.201.16:12:24.35#ibcon#read 6, iclass 2, count 0 2006.201.16:12:24.35#ibcon#end of sib2, iclass 2, count 0 2006.201.16:12:24.35#ibcon#*after write, iclass 2, count 0 2006.201.16:12:24.35#ibcon#*before return 0, iclass 2, count 0 2006.201.16:12:24.35#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:12:24.35#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:12:24.35#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:12:24.35#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:12:24.35$vck44/vb=6,4 2006.201.16:12:24.35#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.16:12:24.35#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.16:12:24.35#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:24.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:12:24.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:12:24.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:12:24.40#ibcon#enter wrdev, iclass 5, count 2 2006.201.16:12:24.40#ibcon#first serial, iclass 5, count 2 2006.201.16:12:24.40#ibcon#enter sib2, iclass 5, count 2 2006.201.16:12:24.40#ibcon#flushed, iclass 5, count 2 2006.201.16:12:24.40#ibcon#about to write, iclass 5, count 2 2006.201.16:12:24.40#ibcon#wrote, iclass 5, count 2 2006.201.16:12:24.40#ibcon#about to read 3, iclass 5, count 2 2006.201.16:12:24.42#ibcon#read 3, iclass 5, count 2 2006.201.16:12:24.42#ibcon#about to read 4, iclass 5, count 2 2006.201.16:12:24.42#ibcon#read 4, iclass 5, count 2 2006.201.16:12:24.42#ibcon#about to read 5, iclass 5, count 2 2006.201.16:12:24.42#ibcon#read 5, iclass 5, count 2 2006.201.16:12:24.42#ibcon#about to read 6, iclass 5, count 2 2006.201.16:12:24.42#ibcon#read 6, iclass 5, count 2 2006.201.16:12:24.42#ibcon#end of sib2, iclass 5, count 2 2006.201.16:12:24.42#ibcon#*mode == 0, iclass 5, count 2 2006.201.16:12:24.42#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.16:12:24.42#ibcon#[27=AT06-04\r\n] 2006.201.16:12:24.42#ibcon#*before write, iclass 5, count 2 2006.201.16:12:24.42#ibcon#enter sib2, iclass 5, count 2 2006.201.16:12:24.42#ibcon#flushed, iclass 5, count 2 2006.201.16:12:24.42#ibcon#about to write, iclass 5, count 2 2006.201.16:12:24.42#ibcon#wrote, iclass 5, count 2 2006.201.16:12:24.42#ibcon#about to read 3, iclass 5, count 2 2006.201.16:12:24.45#ibcon#read 3, iclass 5, count 2 2006.201.16:12:24.45#ibcon#about to read 4, iclass 5, count 2 2006.201.16:12:24.45#ibcon#read 4, iclass 5, count 2 2006.201.16:12:24.45#ibcon#about to read 5, iclass 5, count 2 2006.201.16:12:24.45#ibcon#read 5, iclass 5, count 2 2006.201.16:12:24.45#ibcon#about to read 6, iclass 5, count 2 2006.201.16:12:24.45#ibcon#read 6, iclass 5, count 2 2006.201.16:12:24.45#ibcon#end of sib2, iclass 5, count 2 2006.201.16:12:24.45#ibcon#*after write, iclass 5, count 2 2006.201.16:12:24.45#ibcon#*before return 0, iclass 5, count 2 2006.201.16:12:24.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:12:24.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:12:24.45#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.16:12:24.45#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:24.45#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:12:24.57#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:12:24.57#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:12:24.57#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:12:24.57#ibcon#first serial, iclass 5, count 0 2006.201.16:12:24.57#ibcon#enter sib2, iclass 5, count 0 2006.201.16:12:24.57#ibcon#flushed, iclass 5, count 0 2006.201.16:12:24.57#ibcon#about to write, iclass 5, count 0 2006.201.16:12:24.57#ibcon#wrote, iclass 5, count 0 2006.201.16:12:24.57#ibcon#about to read 3, iclass 5, count 0 2006.201.16:12:24.59#ibcon#read 3, iclass 5, count 0 2006.201.16:12:24.59#ibcon#about to read 4, iclass 5, count 0 2006.201.16:12:24.59#ibcon#read 4, iclass 5, count 0 2006.201.16:12:24.59#ibcon#about to read 5, iclass 5, count 0 2006.201.16:12:24.59#ibcon#read 5, iclass 5, count 0 2006.201.16:12:24.59#ibcon#about to read 6, iclass 5, count 0 2006.201.16:12:24.59#ibcon#read 6, iclass 5, count 0 2006.201.16:12:24.59#ibcon#end of sib2, iclass 5, count 0 2006.201.16:12:24.59#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:12:24.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:12:24.59#ibcon#[27=USB\r\n] 2006.201.16:12:24.59#ibcon#*before write, iclass 5, count 0 2006.201.16:12:24.59#ibcon#enter sib2, iclass 5, count 0 2006.201.16:12:24.59#ibcon#flushed, iclass 5, count 0 2006.201.16:12:24.59#ibcon#about to write, iclass 5, count 0 2006.201.16:12:24.59#ibcon#wrote, iclass 5, count 0 2006.201.16:12:24.59#ibcon#about to read 3, iclass 5, count 0 2006.201.16:12:24.62#ibcon#read 3, iclass 5, count 0 2006.201.16:12:24.62#ibcon#about to read 4, iclass 5, count 0 2006.201.16:12:24.62#ibcon#read 4, iclass 5, count 0 2006.201.16:12:24.62#ibcon#about to read 5, iclass 5, count 0 2006.201.16:12:24.62#ibcon#read 5, iclass 5, count 0 2006.201.16:12:24.62#ibcon#about to read 6, iclass 5, count 0 2006.201.16:12:24.62#ibcon#read 6, iclass 5, count 0 2006.201.16:12:24.62#ibcon#end of sib2, iclass 5, count 0 2006.201.16:12:24.62#ibcon#*after write, iclass 5, count 0 2006.201.16:12:24.62#ibcon#*before return 0, iclass 5, count 0 2006.201.16:12:24.62#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:12:24.62#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:12:24.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:12:24.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:12:24.62$vck44/vblo=7,734.99 2006.201.16:12:24.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.16:12:24.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.16:12:24.62#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:24.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:12:24.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:12:24.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:12:24.62#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:12:24.62#ibcon#first serial, iclass 7, count 0 2006.201.16:12:24.62#ibcon#enter sib2, iclass 7, count 0 2006.201.16:12:24.62#ibcon#flushed, iclass 7, count 0 2006.201.16:12:24.62#ibcon#about to write, iclass 7, count 0 2006.201.16:12:24.62#ibcon#wrote, iclass 7, count 0 2006.201.16:12:24.62#ibcon#about to read 3, iclass 7, count 0 2006.201.16:12:24.64#ibcon#read 3, iclass 7, count 0 2006.201.16:12:24.64#ibcon#about to read 4, iclass 7, count 0 2006.201.16:12:24.64#ibcon#read 4, iclass 7, count 0 2006.201.16:12:24.64#ibcon#about to read 5, iclass 7, count 0 2006.201.16:12:24.64#ibcon#read 5, iclass 7, count 0 2006.201.16:12:24.64#ibcon#about to read 6, iclass 7, count 0 2006.201.16:12:24.64#ibcon#read 6, iclass 7, count 0 2006.201.16:12:24.64#ibcon#end of sib2, iclass 7, count 0 2006.201.16:12:24.64#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:12:24.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:12:24.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:12:24.64#ibcon#*before write, iclass 7, count 0 2006.201.16:12:24.64#ibcon#enter sib2, iclass 7, count 0 2006.201.16:12:24.64#ibcon#flushed, iclass 7, count 0 2006.201.16:12:24.64#ibcon#about to write, iclass 7, count 0 2006.201.16:12:24.64#ibcon#wrote, iclass 7, count 0 2006.201.16:12:24.64#ibcon#about to read 3, iclass 7, count 0 2006.201.16:12:24.68#ibcon#read 3, iclass 7, count 0 2006.201.16:12:24.68#ibcon#about to read 4, iclass 7, count 0 2006.201.16:12:24.68#ibcon#read 4, iclass 7, count 0 2006.201.16:12:24.68#ibcon#about to read 5, iclass 7, count 0 2006.201.16:12:24.68#ibcon#read 5, iclass 7, count 0 2006.201.16:12:24.68#ibcon#about to read 6, iclass 7, count 0 2006.201.16:12:24.68#ibcon#read 6, iclass 7, count 0 2006.201.16:12:24.68#ibcon#end of sib2, iclass 7, count 0 2006.201.16:12:24.68#ibcon#*after write, iclass 7, count 0 2006.201.16:12:24.68#ibcon#*before return 0, iclass 7, count 0 2006.201.16:12:24.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:12:24.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:12:24.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:12:24.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:12:24.68$vck44/vb=7,4 2006.201.16:12:24.68#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.16:12:24.68#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.16:12:24.68#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:24.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:12:24.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:12:24.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:12:24.74#ibcon#enter wrdev, iclass 11, count 2 2006.201.16:12:24.74#ibcon#first serial, iclass 11, count 2 2006.201.16:12:24.74#ibcon#enter sib2, iclass 11, count 2 2006.201.16:12:24.74#ibcon#flushed, iclass 11, count 2 2006.201.16:12:24.74#ibcon#about to write, iclass 11, count 2 2006.201.16:12:24.74#ibcon#wrote, iclass 11, count 2 2006.201.16:12:24.74#ibcon#about to read 3, iclass 11, count 2 2006.201.16:12:24.76#ibcon#read 3, iclass 11, count 2 2006.201.16:12:24.76#ibcon#about to read 4, iclass 11, count 2 2006.201.16:12:24.76#ibcon#read 4, iclass 11, count 2 2006.201.16:12:24.76#ibcon#about to read 5, iclass 11, count 2 2006.201.16:12:24.76#ibcon#read 5, iclass 11, count 2 2006.201.16:12:24.76#ibcon#about to read 6, iclass 11, count 2 2006.201.16:12:24.76#ibcon#read 6, iclass 11, count 2 2006.201.16:12:24.76#ibcon#end of sib2, iclass 11, count 2 2006.201.16:12:24.76#ibcon#*mode == 0, iclass 11, count 2 2006.201.16:12:24.76#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.16:12:24.76#ibcon#[27=AT07-04\r\n] 2006.201.16:12:24.76#ibcon#*before write, iclass 11, count 2 2006.201.16:12:24.76#ibcon#enter sib2, iclass 11, count 2 2006.201.16:12:24.76#ibcon#flushed, iclass 11, count 2 2006.201.16:12:24.76#ibcon#about to write, iclass 11, count 2 2006.201.16:12:24.76#ibcon#wrote, iclass 11, count 2 2006.201.16:12:24.76#ibcon#about to read 3, iclass 11, count 2 2006.201.16:12:24.79#ibcon#read 3, iclass 11, count 2 2006.201.16:12:24.79#ibcon#about to read 4, iclass 11, count 2 2006.201.16:12:24.79#ibcon#read 4, iclass 11, count 2 2006.201.16:12:24.79#ibcon#about to read 5, iclass 11, count 2 2006.201.16:12:24.79#ibcon#read 5, iclass 11, count 2 2006.201.16:12:24.79#ibcon#about to read 6, iclass 11, count 2 2006.201.16:12:24.79#ibcon#read 6, iclass 11, count 2 2006.201.16:12:24.79#ibcon#end of sib2, iclass 11, count 2 2006.201.16:12:24.79#ibcon#*after write, iclass 11, count 2 2006.201.16:12:24.79#ibcon#*before return 0, iclass 11, count 2 2006.201.16:12:24.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:12:24.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:12:24.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.16:12:24.79#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:24.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:12:24.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:12:24.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:12:24.91#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:12:24.91#ibcon#first serial, iclass 11, count 0 2006.201.16:12:24.91#ibcon#enter sib2, iclass 11, count 0 2006.201.16:12:24.91#ibcon#flushed, iclass 11, count 0 2006.201.16:12:24.91#ibcon#about to write, iclass 11, count 0 2006.201.16:12:24.91#ibcon#wrote, iclass 11, count 0 2006.201.16:12:24.91#ibcon#about to read 3, iclass 11, count 0 2006.201.16:12:24.93#ibcon#read 3, iclass 11, count 0 2006.201.16:12:24.93#ibcon#about to read 4, iclass 11, count 0 2006.201.16:12:24.93#ibcon#read 4, iclass 11, count 0 2006.201.16:12:24.93#ibcon#about to read 5, iclass 11, count 0 2006.201.16:12:24.93#ibcon#read 5, iclass 11, count 0 2006.201.16:12:24.93#ibcon#about to read 6, iclass 11, count 0 2006.201.16:12:24.93#ibcon#read 6, iclass 11, count 0 2006.201.16:12:24.93#ibcon#end of sib2, iclass 11, count 0 2006.201.16:12:24.93#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:12:24.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:12:24.93#ibcon#[27=USB\r\n] 2006.201.16:12:24.93#ibcon#*before write, iclass 11, count 0 2006.201.16:12:24.93#ibcon#enter sib2, iclass 11, count 0 2006.201.16:12:24.93#ibcon#flushed, iclass 11, count 0 2006.201.16:12:24.93#ibcon#about to write, iclass 11, count 0 2006.201.16:12:24.93#ibcon#wrote, iclass 11, count 0 2006.201.16:12:24.93#ibcon#about to read 3, iclass 11, count 0 2006.201.16:12:24.96#ibcon#read 3, iclass 11, count 0 2006.201.16:12:24.96#ibcon#about to read 4, iclass 11, count 0 2006.201.16:12:24.96#ibcon#read 4, iclass 11, count 0 2006.201.16:12:24.96#ibcon#about to read 5, iclass 11, count 0 2006.201.16:12:24.96#ibcon#read 5, iclass 11, count 0 2006.201.16:12:24.96#ibcon#about to read 6, iclass 11, count 0 2006.201.16:12:24.96#ibcon#read 6, iclass 11, count 0 2006.201.16:12:24.96#ibcon#end of sib2, iclass 11, count 0 2006.201.16:12:24.96#ibcon#*after write, iclass 11, count 0 2006.201.16:12:24.96#ibcon#*before return 0, iclass 11, count 0 2006.201.16:12:24.96#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:12:24.96#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:12:24.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:12:24.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:12:24.96$vck44/vblo=8,744.99 2006.201.16:12:24.96#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.16:12:24.96#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.16:12:24.96#ibcon#ireg 17 cls_cnt 0 2006.201.16:12:24.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:24.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:24.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:24.96#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:12:24.96#ibcon#first serial, iclass 13, count 0 2006.201.16:12:24.96#ibcon#enter sib2, iclass 13, count 0 2006.201.16:12:24.96#ibcon#flushed, iclass 13, count 0 2006.201.16:12:24.96#ibcon#about to write, iclass 13, count 0 2006.201.16:12:24.96#ibcon#wrote, iclass 13, count 0 2006.201.16:12:24.96#ibcon#about to read 3, iclass 13, count 0 2006.201.16:12:24.98#ibcon#read 3, iclass 13, count 0 2006.201.16:12:24.98#ibcon#about to read 4, iclass 13, count 0 2006.201.16:12:24.98#ibcon#read 4, iclass 13, count 0 2006.201.16:12:24.98#ibcon#about to read 5, iclass 13, count 0 2006.201.16:12:24.98#ibcon#read 5, iclass 13, count 0 2006.201.16:12:24.98#ibcon#about to read 6, iclass 13, count 0 2006.201.16:12:24.98#ibcon#read 6, iclass 13, count 0 2006.201.16:12:24.98#ibcon#end of sib2, iclass 13, count 0 2006.201.16:12:24.98#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:12:24.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:12:24.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:12:24.98#ibcon#*before write, iclass 13, count 0 2006.201.16:12:24.98#ibcon#enter sib2, iclass 13, count 0 2006.201.16:12:24.98#ibcon#flushed, iclass 13, count 0 2006.201.16:12:24.98#ibcon#about to write, iclass 13, count 0 2006.201.16:12:24.98#ibcon#wrote, iclass 13, count 0 2006.201.16:12:24.98#ibcon#about to read 3, iclass 13, count 0 2006.201.16:12:25.03#ibcon#read 3, iclass 13, count 0 2006.201.16:12:25.03#ibcon#about to read 4, iclass 13, count 0 2006.201.16:12:25.03#ibcon#read 4, iclass 13, count 0 2006.201.16:12:25.03#ibcon#about to read 5, iclass 13, count 0 2006.201.16:12:25.03#ibcon#read 5, iclass 13, count 0 2006.201.16:12:25.03#ibcon#about to read 6, iclass 13, count 0 2006.201.16:12:25.03#ibcon#read 6, iclass 13, count 0 2006.201.16:12:25.03#ibcon#end of sib2, iclass 13, count 0 2006.201.16:12:25.03#ibcon#*after write, iclass 13, count 0 2006.201.16:12:25.03#ibcon#*before return 0, iclass 13, count 0 2006.201.16:12:25.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:25.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:12:25.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:12:25.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:12:25.03$vck44/vb=8,4 2006.201.16:12:25.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.16:12:25.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.16:12:25.03#ibcon#ireg 11 cls_cnt 2 2006.201.16:12:25.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:25.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:25.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:25.08#ibcon#enter wrdev, iclass 15, count 2 2006.201.16:12:25.08#ibcon#first serial, iclass 15, count 2 2006.201.16:12:25.08#ibcon#enter sib2, iclass 15, count 2 2006.201.16:12:25.08#ibcon#flushed, iclass 15, count 2 2006.201.16:12:25.08#ibcon#about to write, iclass 15, count 2 2006.201.16:12:25.08#ibcon#wrote, iclass 15, count 2 2006.201.16:12:25.08#ibcon#about to read 3, iclass 15, count 2 2006.201.16:12:25.10#ibcon#read 3, iclass 15, count 2 2006.201.16:12:25.10#ibcon#about to read 4, iclass 15, count 2 2006.201.16:12:25.10#ibcon#read 4, iclass 15, count 2 2006.201.16:12:25.10#ibcon#about to read 5, iclass 15, count 2 2006.201.16:12:25.10#ibcon#read 5, iclass 15, count 2 2006.201.16:12:25.10#ibcon#about to read 6, iclass 15, count 2 2006.201.16:12:25.10#ibcon#read 6, iclass 15, count 2 2006.201.16:12:25.10#ibcon#end of sib2, iclass 15, count 2 2006.201.16:12:25.10#ibcon#*mode == 0, iclass 15, count 2 2006.201.16:12:25.10#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.16:12:25.10#ibcon#[27=AT08-04\r\n] 2006.201.16:12:25.10#ibcon#*before write, iclass 15, count 2 2006.201.16:12:25.10#ibcon#enter sib2, iclass 15, count 2 2006.201.16:12:25.10#ibcon#flushed, iclass 15, count 2 2006.201.16:12:25.10#ibcon#about to write, iclass 15, count 2 2006.201.16:12:25.10#ibcon#wrote, iclass 15, count 2 2006.201.16:12:25.10#ibcon#about to read 3, iclass 15, count 2 2006.201.16:12:25.13#ibcon#read 3, iclass 15, count 2 2006.201.16:12:25.13#ibcon#about to read 4, iclass 15, count 2 2006.201.16:12:25.13#ibcon#read 4, iclass 15, count 2 2006.201.16:12:25.13#ibcon#about to read 5, iclass 15, count 2 2006.201.16:12:25.13#ibcon#read 5, iclass 15, count 2 2006.201.16:12:25.13#ibcon#about to read 6, iclass 15, count 2 2006.201.16:12:25.13#ibcon#read 6, iclass 15, count 2 2006.201.16:12:25.13#ibcon#end of sib2, iclass 15, count 2 2006.201.16:12:25.13#ibcon#*after write, iclass 15, count 2 2006.201.16:12:25.13#ibcon#*before return 0, iclass 15, count 2 2006.201.16:12:25.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:25.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:12:25.13#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.16:12:25.13#ibcon#ireg 7 cls_cnt 0 2006.201.16:12:25.13#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:25.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:25.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:25.25#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:12:25.25#ibcon#first serial, iclass 15, count 0 2006.201.16:12:25.25#ibcon#enter sib2, iclass 15, count 0 2006.201.16:12:25.25#ibcon#flushed, iclass 15, count 0 2006.201.16:12:25.25#ibcon#about to write, iclass 15, count 0 2006.201.16:12:25.25#ibcon#wrote, iclass 15, count 0 2006.201.16:12:25.25#ibcon#about to read 3, iclass 15, count 0 2006.201.16:12:25.27#ibcon#read 3, iclass 15, count 0 2006.201.16:12:25.27#ibcon#about to read 4, iclass 15, count 0 2006.201.16:12:25.27#ibcon#read 4, iclass 15, count 0 2006.201.16:12:25.27#ibcon#about to read 5, iclass 15, count 0 2006.201.16:12:25.27#ibcon#read 5, iclass 15, count 0 2006.201.16:12:25.27#ibcon#about to read 6, iclass 15, count 0 2006.201.16:12:25.27#ibcon#read 6, iclass 15, count 0 2006.201.16:12:25.27#ibcon#end of sib2, iclass 15, count 0 2006.201.16:12:25.27#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:12:25.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:12:25.27#ibcon#[27=USB\r\n] 2006.201.16:12:25.27#ibcon#*before write, iclass 15, count 0 2006.201.16:12:25.27#ibcon#enter sib2, iclass 15, count 0 2006.201.16:12:25.27#ibcon#flushed, iclass 15, count 0 2006.201.16:12:25.27#ibcon#about to write, iclass 15, count 0 2006.201.16:12:25.27#ibcon#wrote, iclass 15, count 0 2006.201.16:12:25.27#ibcon#about to read 3, iclass 15, count 0 2006.201.16:12:25.30#ibcon#read 3, iclass 15, count 0 2006.201.16:12:25.30#ibcon#about to read 4, iclass 15, count 0 2006.201.16:12:25.30#ibcon#read 4, iclass 15, count 0 2006.201.16:12:25.30#ibcon#about to read 5, iclass 15, count 0 2006.201.16:12:25.30#ibcon#read 5, iclass 15, count 0 2006.201.16:12:25.30#ibcon#about to read 6, iclass 15, count 0 2006.201.16:12:25.30#ibcon#read 6, iclass 15, count 0 2006.201.16:12:25.30#ibcon#end of sib2, iclass 15, count 0 2006.201.16:12:25.30#ibcon#*after write, iclass 15, count 0 2006.201.16:12:25.30#ibcon#*before return 0, iclass 15, count 0 2006.201.16:12:25.30#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:25.30#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:12:25.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:12:25.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:12:25.30$vck44/vabw=wide 2006.201.16:12:25.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.16:12:25.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.16:12:25.30#ibcon#ireg 8 cls_cnt 0 2006.201.16:12:25.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:25.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:25.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:25.30#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:12:25.30#ibcon#first serial, iclass 17, count 0 2006.201.16:12:25.30#ibcon#enter sib2, iclass 17, count 0 2006.201.16:12:25.30#ibcon#flushed, iclass 17, count 0 2006.201.16:12:25.30#ibcon#about to write, iclass 17, count 0 2006.201.16:12:25.30#ibcon#wrote, iclass 17, count 0 2006.201.16:12:25.30#ibcon#about to read 3, iclass 17, count 0 2006.201.16:12:25.32#ibcon#read 3, iclass 17, count 0 2006.201.16:12:25.32#ibcon#about to read 4, iclass 17, count 0 2006.201.16:12:25.32#ibcon#read 4, iclass 17, count 0 2006.201.16:12:25.32#ibcon#about to read 5, iclass 17, count 0 2006.201.16:12:25.32#ibcon#read 5, iclass 17, count 0 2006.201.16:12:25.32#ibcon#about to read 6, iclass 17, count 0 2006.201.16:12:25.32#ibcon#read 6, iclass 17, count 0 2006.201.16:12:25.32#ibcon#end of sib2, iclass 17, count 0 2006.201.16:12:25.32#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:12:25.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:12:25.32#ibcon#[25=BW32\r\n] 2006.201.16:12:25.32#ibcon#*before write, iclass 17, count 0 2006.201.16:12:25.32#ibcon#enter sib2, iclass 17, count 0 2006.201.16:12:25.32#ibcon#flushed, iclass 17, count 0 2006.201.16:12:25.32#ibcon#about to write, iclass 17, count 0 2006.201.16:12:25.32#ibcon#wrote, iclass 17, count 0 2006.201.16:12:25.32#ibcon#about to read 3, iclass 17, count 0 2006.201.16:12:25.36#ibcon#read 3, iclass 17, count 0 2006.201.16:12:25.36#ibcon#about to read 4, iclass 17, count 0 2006.201.16:12:25.36#ibcon#read 4, iclass 17, count 0 2006.201.16:12:25.36#ibcon#about to read 5, iclass 17, count 0 2006.201.16:12:25.36#ibcon#read 5, iclass 17, count 0 2006.201.16:12:25.36#ibcon#about to read 6, iclass 17, count 0 2006.201.16:12:25.36#ibcon#read 6, iclass 17, count 0 2006.201.16:12:25.36#ibcon#end of sib2, iclass 17, count 0 2006.201.16:12:25.36#ibcon#*after write, iclass 17, count 0 2006.201.16:12:25.36#ibcon#*before return 0, iclass 17, count 0 2006.201.16:12:25.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:25.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:12:25.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:12:25.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:12:25.36$vck44/vbbw=wide 2006.201.16:12:25.36#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.16:12:25.36#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.16:12:25.36#ibcon#ireg 8 cls_cnt 0 2006.201.16:12:25.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:12:25.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:12:25.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:12:25.42#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:12:25.42#ibcon#first serial, iclass 19, count 0 2006.201.16:12:25.42#ibcon#enter sib2, iclass 19, count 0 2006.201.16:12:25.42#ibcon#flushed, iclass 19, count 0 2006.201.16:12:25.42#ibcon#about to write, iclass 19, count 0 2006.201.16:12:25.42#ibcon#wrote, iclass 19, count 0 2006.201.16:12:25.42#ibcon#about to read 3, iclass 19, count 0 2006.201.16:12:25.44#ibcon#read 3, iclass 19, count 0 2006.201.16:12:25.44#ibcon#about to read 4, iclass 19, count 0 2006.201.16:12:25.44#ibcon#read 4, iclass 19, count 0 2006.201.16:12:25.44#ibcon#about to read 5, iclass 19, count 0 2006.201.16:12:25.44#ibcon#read 5, iclass 19, count 0 2006.201.16:12:25.44#ibcon#about to read 6, iclass 19, count 0 2006.201.16:12:25.44#ibcon#read 6, iclass 19, count 0 2006.201.16:12:25.44#ibcon#end of sib2, iclass 19, count 0 2006.201.16:12:25.44#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:12:25.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:12:25.44#ibcon#[27=BW32\r\n] 2006.201.16:12:25.44#ibcon#*before write, iclass 19, count 0 2006.201.16:12:25.44#ibcon#enter sib2, iclass 19, count 0 2006.201.16:12:25.44#ibcon#flushed, iclass 19, count 0 2006.201.16:12:25.44#ibcon#about to write, iclass 19, count 0 2006.201.16:12:25.44#ibcon#wrote, iclass 19, count 0 2006.201.16:12:25.44#ibcon#about to read 3, iclass 19, count 0 2006.201.16:12:25.47#ibcon#read 3, iclass 19, count 0 2006.201.16:12:25.47#ibcon#about to read 4, iclass 19, count 0 2006.201.16:12:25.47#ibcon#read 4, iclass 19, count 0 2006.201.16:12:25.47#ibcon#about to read 5, iclass 19, count 0 2006.201.16:12:25.47#ibcon#read 5, iclass 19, count 0 2006.201.16:12:25.47#ibcon#about to read 6, iclass 19, count 0 2006.201.16:12:25.47#ibcon#read 6, iclass 19, count 0 2006.201.16:12:25.47#ibcon#end of sib2, iclass 19, count 0 2006.201.16:12:25.47#ibcon#*after write, iclass 19, count 0 2006.201.16:12:25.47#ibcon#*before return 0, iclass 19, count 0 2006.201.16:12:25.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:12:25.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:12:25.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:12:25.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:12:25.47$setupk4/ifdk4 2006.201.16:12:25.47$ifdk4/lo= 2006.201.16:12:25.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:12:25.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:12:25.47$ifdk4/patch= 2006.201.16:12:25.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:12:25.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:12:25.47$setupk4/!*+20s 2006.201.16:12:31.82#abcon#<5=/00 0.1 0.4 20.821001003.0\r\n> 2006.201.16:12:31.84#abcon#{5=INTERFACE CLEAR} 2006.201.16:12:31.90#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:12:39.92$setupk4/"tpicd 2006.201.16:12:39.92$setupk4/echo=off 2006.201.16:12:39.92$setupk4/xlog=off 2006.201.16:12:39.92:!2006.201.16:17:27 2006.201.16:12:47.13#trakl#Source acquired 2006.201.16:12:49.13#flagr#flagr/antenna,acquired 2006.201.16:17:27.00:preob 2006.201.16:17:27.14/onsource/TRACKING 2006.201.16:17:27.14:!2006.201.16:17:37 2006.201.16:17:37.00:"tape 2006.201.16:17:37.00:"st=record 2006.201.16:17:37.00:data_valid=on 2006.201.16:17:37.00:midob 2006.201.16:17:37.14/onsource/TRACKING 2006.201.16:17:37.14/wx/20.80,1003.0,100 2006.201.16:17:37.26/cable/+6.4765E-03 2006.201.16:17:38.35/va/01,08,usb,yes,29,31 2006.201.16:17:38.35/va/02,07,usb,yes,31,32 2006.201.16:17:38.35/va/03,08,usb,yes,28,29 2006.201.16:17:38.35/va/04,07,usb,yes,32,34 2006.201.16:17:38.35/va/05,04,usb,yes,28,29 2006.201.16:17:38.35/va/06,05,usb,yes,28,28 2006.201.16:17:38.35/va/07,05,usb,yes,28,29 2006.201.16:17:38.35/va/08,04,usb,yes,27,33 2006.201.16:17:38.58/valo/01,524.99,yes,locked 2006.201.16:17:38.58/valo/02,534.99,yes,locked 2006.201.16:17:38.58/valo/03,564.99,yes,locked 2006.201.16:17:38.58/valo/04,624.99,yes,locked 2006.201.16:17:38.58/valo/05,734.99,yes,locked 2006.201.16:17:38.58/valo/06,814.99,yes,locked 2006.201.16:17:38.58/valo/07,864.99,yes,locked 2006.201.16:17:38.58/valo/08,884.99,yes,locked 2006.201.16:17:39.67/vb/01,04,usb,yes,28,26 2006.201.16:17:39.67/vb/02,05,usb,yes,27,27 2006.201.16:17:39.67/vb/03,04,usb,yes,28,31 2006.201.16:17:39.67/vb/04,05,usb,yes,28,27 2006.201.16:17:39.67/vb/05,04,usb,yes,25,27 2006.201.16:17:39.67/vb/06,04,usb,yes,29,25 2006.201.16:17:39.67/vb/07,04,usb,yes,29,29 2006.201.16:17:39.67/vb/08,04,usb,yes,27,30 2006.201.16:17:39.90/vblo/01,629.99,yes,locked 2006.201.16:17:39.90/vblo/02,634.99,yes,locked 2006.201.16:17:39.90/vblo/03,649.99,yes,locked 2006.201.16:17:39.90/vblo/04,679.99,yes,locked 2006.201.16:17:39.90/vblo/05,709.99,yes,locked 2006.201.16:17:39.90/vblo/06,719.99,yes,locked 2006.201.16:17:39.90/vblo/07,734.99,yes,locked 2006.201.16:17:39.90/vblo/08,744.99,yes,locked 2006.201.16:17:40.05/vabw/8 2006.201.16:17:40.20/vbbw/8 2006.201.16:17:40.29/xfe/off,on,15.5 2006.201.16:17:40.67/ifatt/23,28,28,28 2006.201.16:17:41.06/fmout-gps/S +4.52E-07 2006.201.16:17:41.13:!2006.201.16:21:17 2006.201.16:21:17.00:data_valid=off 2006.201.16:21:17.00:"et 2006.201.16:21:17.00:!+3s 2006.201.16:21:20.02:"tape 2006.201.16:21:20.02:postob 2006.201.16:21:20.21/cable/+6.4765E-03 2006.201.16:21:20.21/wx/20.79,1002.9,100 2006.201.16:21:20.29/fmout-gps/S +4.54E-07 2006.201.16:21:20.29:scan_name=201-1624,jd0607,260 2006.201.16:21:20.29:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.201.16:21:22.13#flagr#flagr/antenna,new-source 2006.201.16:21:22.13:checkk5 2006.201.16:21:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:21:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:21:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:21:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:21:24.00/chk_obsdata//k5ts1/T2011617??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.16:21:24.36/chk_obsdata//k5ts2/T2011617??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.16:21:24.73/chk_obsdata//k5ts3/T2011617??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.16:21:25.09/chk_obsdata//k5ts4/T2011617??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.16:21:25.78/k5log//k5ts1_log_newline 2006.201.16:21:26.48/k5log//k5ts2_log_newline 2006.201.16:21:27.18/k5log//k5ts3_log_newline 2006.201.16:21:27.88/k5log//k5ts4_log_newline 2006.201.16:21:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:21:27.90:setupk4=1 2006.201.16:21:27.90$setupk4/echo=on 2006.201.16:21:27.90$setupk4/pcalon 2006.201.16:21:27.90$pcalon/"no phase cal control is implemented here 2006.201.16:21:27.90$setupk4/"tpicd=stop 2006.201.16:21:27.90$setupk4/"rec=synch_on 2006.201.16:21:27.90$setupk4/"rec_mode=128 2006.201.16:21:27.90$setupk4/!* 2006.201.16:21:27.90$setupk4/recpk4 2006.201.16:21:27.90$recpk4/recpatch= 2006.201.16:21:27.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:21:27.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:21:27.91$setupk4/vck44 2006.201.16:21:27.91$vck44/valo=1,524.99 2006.201.16:21:27.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.16:21:27.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.16:21:27.91#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:27.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:27.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:27.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:27.91#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:21:27.91#ibcon#first serial, iclass 15, count 0 2006.201.16:21:27.91#ibcon#enter sib2, iclass 15, count 0 2006.201.16:21:27.91#ibcon#flushed, iclass 15, count 0 2006.201.16:21:27.91#ibcon#about to write, iclass 15, count 0 2006.201.16:21:27.91#ibcon#wrote, iclass 15, count 0 2006.201.16:21:27.91#ibcon#about to read 3, iclass 15, count 0 2006.201.16:21:27.94#ibcon#read 3, iclass 15, count 0 2006.201.16:21:27.94#ibcon#about to read 4, iclass 15, count 0 2006.201.16:21:27.94#ibcon#read 4, iclass 15, count 0 2006.201.16:21:27.94#ibcon#about to read 5, iclass 15, count 0 2006.201.16:21:27.94#ibcon#read 5, iclass 15, count 0 2006.201.16:21:27.94#ibcon#about to read 6, iclass 15, count 0 2006.201.16:21:27.94#ibcon#read 6, iclass 15, count 0 2006.201.16:21:27.94#ibcon#end of sib2, iclass 15, count 0 2006.201.16:21:27.94#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:21:27.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:21:27.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:21:27.94#ibcon#*before write, iclass 15, count 0 2006.201.16:21:27.94#ibcon#enter sib2, iclass 15, count 0 2006.201.16:21:27.94#ibcon#flushed, iclass 15, count 0 2006.201.16:21:27.94#ibcon#about to write, iclass 15, count 0 2006.201.16:21:27.94#ibcon#wrote, iclass 15, count 0 2006.201.16:21:27.94#ibcon#about to read 3, iclass 15, count 0 2006.201.16:21:28.00#ibcon#read 3, iclass 15, count 0 2006.201.16:21:28.00#ibcon#about to read 4, iclass 15, count 0 2006.201.16:21:28.00#ibcon#read 4, iclass 15, count 0 2006.201.16:21:28.00#ibcon#about to read 5, iclass 15, count 0 2006.201.16:21:28.00#ibcon#read 5, iclass 15, count 0 2006.201.16:21:28.00#ibcon#about to read 6, iclass 15, count 0 2006.201.16:21:28.00#ibcon#read 6, iclass 15, count 0 2006.201.16:21:28.00#ibcon#end of sib2, iclass 15, count 0 2006.201.16:21:28.00#ibcon#*after write, iclass 15, count 0 2006.201.16:21:28.00#ibcon#*before return 0, iclass 15, count 0 2006.201.16:21:28.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:28.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:28.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:21:28.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:21:28.00$vck44/va=1,8 2006.201.16:21:28.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.16:21:28.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.16:21:28.00#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:28.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:28.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:28.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:28.00#ibcon#enter wrdev, iclass 17, count 2 2006.201.16:21:28.00#ibcon#first serial, iclass 17, count 2 2006.201.16:21:28.00#ibcon#enter sib2, iclass 17, count 2 2006.201.16:21:28.00#ibcon#flushed, iclass 17, count 2 2006.201.16:21:28.00#ibcon#about to write, iclass 17, count 2 2006.201.16:21:28.00#ibcon#wrote, iclass 17, count 2 2006.201.16:21:28.00#ibcon#about to read 3, iclass 17, count 2 2006.201.16:21:28.02#ibcon#read 3, iclass 17, count 2 2006.201.16:21:28.02#ibcon#about to read 4, iclass 17, count 2 2006.201.16:21:28.02#ibcon#read 4, iclass 17, count 2 2006.201.16:21:28.02#ibcon#about to read 5, iclass 17, count 2 2006.201.16:21:28.02#ibcon#read 5, iclass 17, count 2 2006.201.16:21:28.02#ibcon#about to read 6, iclass 17, count 2 2006.201.16:21:28.02#ibcon#read 6, iclass 17, count 2 2006.201.16:21:28.02#ibcon#end of sib2, iclass 17, count 2 2006.201.16:21:28.02#ibcon#*mode == 0, iclass 17, count 2 2006.201.16:21:28.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.16:21:28.02#ibcon#[25=AT01-08\r\n] 2006.201.16:21:28.02#ibcon#*before write, iclass 17, count 2 2006.201.16:21:28.02#ibcon#enter sib2, iclass 17, count 2 2006.201.16:21:28.02#ibcon#flushed, iclass 17, count 2 2006.201.16:21:28.02#ibcon#about to write, iclass 17, count 2 2006.201.16:21:28.02#ibcon#wrote, iclass 17, count 2 2006.201.16:21:28.02#ibcon#about to read 3, iclass 17, count 2 2006.201.16:21:28.06#ibcon#read 3, iclass 17, count 2 2006.201.16:21:28.06#ibcon#about to read 4, iclass 17, count 2 2006.201.16:21:28.06#ibcon#read 4, iclass 17, count 2 2006.201.16:21:28.06#ibcon#about to read 5, iclass 17, count 2 2006.201.16:21:28.06#ibcon#read 5, iclass 17, count 2 2006.201.16:21:28.06#ibcon#about to read 6, iclass 17, count 2 2006.201.16:21:28.06#ibcon#read 6, iclass 17, count 2 2006.201.16:21:28.06#ibcon#end of sib2, iclass 17, count 2 2006.201.16:21:28.06#ibcon#*after write, iclass 17, count 2 2006.201.16:21:28.06#ibcon#*before return 0, iclass 17, count 2 2006.201.16:21:28.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:28.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:28.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.16:21:28.06#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:28.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:28.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:28.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:28.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:21:28.18#ibcon#first serial, iclass 17, count 0 2006.201.16:21:28.18#ibcon#enter sib2, iclass 17, count 0 2006.201.16:21:28.18#ibcon#flushed, iclass 17, count 0 2006.201.16:21:28.18#ibcon#about to write, iclass 17, count 0 2006.201.16:21:28.18#ibcon#wrote, iclass 17, count 0 2006.201.16:21:28.18#ibcon#about to read 3, iclass 17, count 0 2006.201.16:21:28.21#ibcon#read 3, iclass 17, count 0 2006.201.16:21:28.21#ibcon#about to read 4, iclass 17, count 0 2006.201.16:21:28.21#ibcon#read 4, iclass 17, count 0 2006.201.16:21:28.21#ibcon#about to read 5, iclass 17, count 0 2006.201.16:21:28.21#ibcon#read 5, iclass 17, count 0 2006.201.16:21:28.21#ibcon#about to read 6, iclass 17, count 0 2006.201.16:21:28.21#ibcon#read 6, iclass 17, count 0 2006.201.16:21:28.21#ibcon#end of sib2, iclass 17, count 0 2006.201.16:21:28.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:21:28.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:21:28.21#ibcon#[25=USB\r\n] 2006.201.16:21:28.21#ibcon#*before write, iclass 17, count 0 2006.201.16:21:28.21#ibcon#enter sib2, iclass 17, count 0 2006.201.16:21:28.21#ibcon#flushed, iclass 17, count 0 2006.201.16:21:28.21#ibcon#about to write, iclass 17, count 0 2006.201.16:21:28.21#ibcon#wrote, iclass 17, count 0 2006.201.16:21:28.21#ibcon#about to read 3, iclass 17, count 0 2006.201.16:21:28.24#ibcon#read 3, iclass 17, count 0 2006.201.16:21:28.24#ibcon#about to read 4, iclass 17, count 0 2006.201.16:21:28.24#ibcon#read 4, iclass 17, count 0 2006.201.16:21:28.24#ibcon#about to read 5, iclass 17, count 0 2006.201.16:21:28.24#ibcon#read 5, iclass 17, count 0 2006.201.16:21:28.24#ibcon#about to read 6, iclass 17, count 0 2006.201.16:21:28.24#ibcon#read 6, iclass 17, count 0 2006.201.16:21:28.24#ibcon#end of sib2, iclass 17, count 0 2006.201.16:21:28.24#ibcon#*after write, iclass 17, count 0 2006.201.16:21:28.24#ibcon#*before return 0, iclass 17, count 0 2006.201.16:21:28.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:28.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:28.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:21:28.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:21:28.24$vck44/valo=2,534.99 2006.201.16:21:28.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.16:21:28.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.16:21:28.24#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:28.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:28.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:28.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:28.24#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:21:28.24#ibcon#first serial, iclass 19, count 0 2006.201.16:21:28.24#ibcon#enter sib2, iclass 19, count 0 2006.201.16:21:28.24#ibcon#flushed, iclass 19, count 0 2006.201.16:21:28.24#ibcon#about to write, iclass 19, count 0 2006.201.16:21:28.24#ibcon#wrote, iclass 19, count 0 2006.201.16:21:28.24#ibcon#about to read 3, iclass 19, count 0 2006.201.16:21:28.26#ibcon#read 3, iclass 19, count 0 2006.201.16:21:28.26#ibcon#about to read 4, iclass 19, count 0 2006.201.16:21:28.26#ibcon#read 4, iclass 19, count 0 2006.201.16:21:28.26#ibcon#about to read 5, iclass 19, count 0 2006.201.16:21:28.26#ibcon#read 5, iclass 19, count 0 2006.201.16:21:28.26#ibcon#about to read 6, iclass 19, count 0 2006.201.16:21:28.26#ibcon#read 6, iclass 19, count 0 2006.201.16:21:28.26#ibcon#end of sib2, iclass 19, count 0 2006.201.16:21:28.26#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:21:28.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:21:28.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:21:28.26#ibcon#*before write, iclass 19, count 0 2006.201.16:21:28.26#ibcon#enter sib2, iclass 19, count 0 2006.201.16:21:28.26#ibcon#flushed, iclass 19, count 0 2006.201.16:21:28.26#ibcon#about to write, iclass 19, count 0 2006.201.16:21:28.26#ibcon#wrote, iclass 19, count 0 2006.201.16:21:28.26#ibcon#about to read 3, iclass 19, count 0 2006.201.16:21:28.30#ibcon#read 3, iclass 19, count 0 2006.201.16:21:28.30#ibcon#about to read 4, iclass 19, count 0 2006.201.16:21:28.30#ibcon#read 4, iclass 19, count 0 2006.201.16:21:28.30#ibcon#about to read 5, iclass 19, count 0 2006.201.16:21:28.30#ibcon#read 5, iclass 19, count 0 2006.201.16:21:28.30#ibcon#about to read 6, iclass 19, count 0 2006.201.16:21:28.30#ibcon#read 6, iclass 19, count 0 2006.201.16:21:28.30#ibcon#end of sib2, iclass 19, count 0 2006.201.16:21:28.30#ibcon#*after write, iclass 19, count 0 2006.201.16:21:28.30#ibcon#*before return 0, iclass 19, count 0 2006.201.16:21:28.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:28.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:28.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:21:28.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:21:28.30$vck44/va=2,7 2006.201.16:21:28.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.16:21:28.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.16:21:28.30#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:28.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:28.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:28.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:28.36#ibcon#enter wrdev, iclass 21, count 2 2006.201.16:21:28.36#ibcon#first serial, iclass 21, count 2 2006.201.16:21:28.36#ibcon#enter sib2, iclass 21, count 2 2006.201.16:21:28.36#ibcon#flushed, iclass 21, count 2 2006.201.16:21:28.36#ibcon#about to write, iclass 21, count 2 2006.201.16:21:28.36#ibcon#wrote, iclass 21, count 2 2006.201.16:21:28.36#ibcon#about to read 3, iclass 21, count 2 2006.201.16:21:28.38#ibcon#read 3, iclass 21, count 2 2006.201.16:21:28.38#ibcon#about to read 4, iclass 21, count 2 2006.201.16:21:28.38#ibcon#read 4, iclass 21, count 2 2006.201.16:21:28.38#ibcon#about to read 5, iclass 21, count 2 2006.201.16:21:28.38#ibcon#read 5, iclass 21, count 2 2006.201.16:21:28.38#ibcon#about to read 6, iclass 21, count 2 2006.201.16:21:28.38#ibcon#read 6, iclass 21, count 2 2006.201.16:21:28.38#ibcon#end of sib2, iclass 21, count 2 2006.201.16:21:28.38#ibcon#*mode == 0, iclass 21, count 2 2006.201.16:21:28.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.16:21:28.38#ibcon#[25=AT02-07\r\n] 2006.201.16:21:28.38#ibcon#*before write, iclass 21, count 2 2006.201.16:21:28.38#ibcon#enter sib2, iclass 21, count 2 2006.201.16:21:28.38#ibcon#flushed, iclass 21, count 2 2006.201.16:21:28.38#ibcon#about to write, iclass 21, count 2 2006.201.16:21:28.38#ibcon#wrote, iclass 21, count 2 2006.201.16:21:28.38#ibcon#about to read 3, iclass 21, count 2 2006.201.16:21:28.41#ibcon#read 3, iclass 21, count 2 2006.201.16:21:28.41#ibcon#about to read 4, iclass 21, count 2 2006.201.16:21:28.41#ibcon#read 4, iclass 21, count 2 2006.201.16:21:28.41#ibcon#about to read 5, iclass 21, count 2 2006.201.16:21:28.41#ibcon#read 5, iclass 21, count 2 2006.201.16:21:28.41#ibcon#about to read 6, iclass 21, count 2 2006.201.16:21:28.41#ibcon#read 6, iclass 21, count 2 2006.201.16:21:28.41#ibcon#end of sib2, iclass 21, count 2 2006.201.16:21:28.41#ibcon#*after write, iclass 21, count 2 2006.201.16:21:28.41#ibcon#*before return 0, iclass 21, count 2 2006.201.16:21:28.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:28.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:28.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.16:21:28.41#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:28.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:28.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:28.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:28.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:21:28.53#ibcon#first serial, iclass 21, count 0 2006.201.16:21:28.53#ibcon#enter sib2, iclass 21, count 0 2006.201.16:21:28.53#ibcon#flushed, iclass 21, count 0 2006.201.16:21:28.53#ibcon#about to write, iclass 21, count 0 2006.201.16:21:28.53#ibcon#wrote, iclass 21, count 0 2006.201.16:21:28.53#ibcon#about to read 3, iclass 21, count 0 2006.201.16:21:28.55#ibcon#read 3, iclass 21, count 0 2006.201.16:21:28.55#ibcon#about to read 4, iclass 21, count 0 2006.201.16:21:28.55#ibcon#read 4, iclass 21, count 0 2006.201.16:21:28.55#ibcon#about to read 5, iclass 21, count 0 2006.201.16:21:28.55#ibcon#read 5, iclass 21, count 0 2006.201.16:21:28.55#ibcon#about to read 6, iclass 21, count 0 2006.201.16:21:28.55#ibcon#read 6, iclass 21, count 0 2006.201.16:21:28.55#ibcon#end of sib2, iclass 21, count 0 2006.201.16:21:28.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:21:28.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:21:28.55#ibcon#[25=USB\r\n] 2006.201.16:21:28.55#ibcon#*before write, iclass 21, count 0 2006.201.16:21:28.55#ibcon#enter sib2, iclass 21, count 0 2006.201.16:21:28.55#ibcon#flushed, iclass 21, count 0 2006.201.16:21:28.55#ibcon#about to write, iclass 21, count 0 2006.201.16:21:28.55#ibcon#wrote, iclass 21, count 0 2006.201.16:21:28.55#ibcon#about to read 3, iclass 21, count 0 2006.201.16:21:28.58#ibcon#read 3, iclass 21, count 0 2006.201.16:21:28.58#ibcon#about to read 4, iclass 21, count 0 2006.201.16:21:28.58#ibcon#read 4, iclass 21, count 0 2006.201.16:21:28.58#ibcon#about to read 5, iclass 21, count 0 2006.201.16:21:28.58#ibcon#read 5, iclass 21, count 0 2006.201.16:21:28.58#ibcon#about to read 6, iclass 21, count 0 2006.201.16:21:28.58#ibcon#read 6, iclass 21, count 0 2006.201.16:21:28.58#ibcon#end of sib2, iclass 21, count 0 2006.201.16:21:28.58#ibcon#*after write, iclass 21, count 0 2006.201.16:21:28.58#ibcon#*before return 0, iclass 21, count 0 2006.201.16:21:28.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:28.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:28.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:21:28.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:21:28.58$vck44/valo=3,564.99 2006.201.16:21:28.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.16:21:28.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.16:21:28.58#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:28.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:28.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:28.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:28.58#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:21:28.58#ibcon#first serial, iclass 23, count 0 2006.201.16:21:28.58#ibcon#enter sib2, iclass 23, count 0 2006.201.16:21:28.58#ibcon#flushed, iclass 23, count 0 2006.201.16:21:28.58#ibcon#about to write, iclass 23, count 0 2006.201.16:21:28.58#ibcon#wrote, iclass 23, count 0 2006.201.16:21:28.58#ibcon#about to read 3, iclass 23, count 0 2006.201.16:21:28.60#ibcon#read 3, iclass 23, count 0 2006.201.16:21:28.60#ibcon#about to read 4, iclass 23, count 0 2006.201.16:21:28.60#ibcon#read 4, iclass 23, count 0 2006.201.16:21:28.60#ibcon#about to read 5, iclass 23, count 0 2006.201.16:21:28.60#ibcon#read 5, iclass 23, count 0 2006.201.16:21:28.60#ibcon#about to read 6, iclass 23, count 0 2006.201.16:21:28.60#ibcon#read 6, iclass 23, count 0 2006.201.16:21:28.60#ibcon#end of sib2, iclass 23, count 0 2006.201.16:21:28.60#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:21:28.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:21:28.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:21:28.60#ibcon#*before write, iclass 23, count 0 2006.201.16:21:28.60#ibcon#enter sib2, iclass 23, count 0 2006.201.16:21:28.60#ibcon#flushed, iclass 23, count 0 2006.201.16:21:28.60#ibcon#about to write, iclass 23, count 0 2006.201.16:21:28.60#ibcon#wrote, iclass 23, count 0 2006.201.16:21:28.60#ibcon#about to read 3, iclass 23, count 0 2006.201.16:21:28.65#ibcon#read 3, iclass 23, count 0 2006.201.16:21:28.65#ibcon#about to read 4, iclass 23, count 0 2006.201.16:21:28.65#ibcon#read 4, iclass 23, count 0 2006.201.16:21:28.65#ibcon#about to read 5, iclass 23, count 0 2006.201.16:21:28.65#ibcon#read 5, iclass 23, count 0 2006.201.16:21:28.65#ibcon#about to read 6, iclass 23, count 0 2006.201.16:21:28.65#ibcon#read 6, iclass 23, count 0 2006.201.16:21:28.65#ibcon#end of sib2, iclass 23, count 0 2006.201.16:21:28.65#ibcon#*after write, iclass 23, count 0 2006.201.16:21:28.65#ibcon#*before return 0, iclass 23, count 0 2006.201.16:21:28.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:28.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:28.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:21:28.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:21:28.65$vck44/va=3,8 2006.201.16:21:28.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.16:21:28.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.16:21:28.65#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:28.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:28.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:28.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:28.70#ibcon#enter wrdev, iclass 25, count 2 2006.201.16:21:28.70#ibcon#first serial, iclass 25, count 2 2006.201.16:21:28.70#ibcon#enter sib2, iclass 25, count 2 2006.201.16:21:28.70#ibcon#flushed, iclass 25, count 2 2006.201.16:21:28.70#ibcon#about to write, iclass 25, count 2 2006.201.16:21:28.70#ibcon#wrote, iclass 25, count 2 2006.201.16:21:28.70#ibcon#about to read 3, iclass 25, count 2 2006.201.16:21:28.72#ibcon#read 3, iclass 25, count 2 2006.201.16:21:28.72#ibcon#about to read 4, iclass 25, count 2 2006.201.16:21:28.72#ibcon#read 4, iclass 25, count 2 2006.201.16:21:28.72#ibcon#about to read 5, iclass 25, count 2 2006.201.16:21:28.72#ibcon#read 5, iclass 25, count 2 2006.201.16:21:28.72#ibcon#about to read 6, iclass 25, count 2 2006.201.16:21:28.72#ibcon#read 6, iclass 25, count 2 2006.201.16:21:28.72#ibcon#end of sib2, iclass 25, count 2 2006.201.16:21:28.72#ibcon#*mode == 0, iclass 25, count 2 2006.201.16:21:28.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.16:21:28.72#ibcon#[25=AT03-08\r\n] 2006.201.16:21:28.72#ibcon#*before write, iclass 25, count 2 2006.201.16:21:28.72#ibcon#enter sib2, iclass 25, count 2 2006.201.16:21:28.72#ibcon#flushed, iclass 25, count 2 2006.201.16:21:28.72#ibcon#about to write, iclass 25, count 2 2006.201.16:21:28.72#ibcon#wrote, iclass 25, count 2 2006.201.16:21:28.72#ibcon#about to read 3, iclass 25, count 2 2006.201.16:21:28.75#ibcon#read 3, iclass 25, count 2 2006.201.16:21:28.75#ibcon#about to read 4, iclass 25, count 2 2006.201.16:21:28.75#ibcon#read 4, iclass 25, count 2 2006.201.16:21:28.75#ibcon#about to read 5, iclass 25, count 2 2006.201.16:21:28.75#ibcon#read 5, iclass 25, count 2 2006.201.16:21:28.75#ibcon#about to read 6, iclass 25, count 2 2006.201.16:21:28.75#ibcon#read 6, iclass 25, count 2 2006.201.16:21:28.75#ibcon#end of sib2, iclass 25, count 2 2006.201.16:21:28.75#ibcon#*after write, iclass 25, count 2 2006.201.16:21:28.75#ibcon#*before return 0, iclass 25, count 2 2006.201.16:21:28.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:28.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:28.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.16:21:28.75#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:28.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:28.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:28.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:28.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:21:28.87#ibcon#first serial, iclass 25, count 0 2006.201.16:21:28.87#ibcon#enter sib2, iclass 25, count 0 2006.201.16:21:28.87#ibcon#flushed, iclass 25, count 0 2006.201.16:21:28.87#ibcon#about to write, iclass 25, count 0 2006.201.16:21:28.87#ibcon#wrote, iclass 25, count 0 2006.201.16:21:28.87#ibcon#about to read 3, iclass 25, count 0 2006.201.16:21:28.89#ibcon#read 3, iclass 25, count 0 2006.201.16:21:28.89#ibcon#about to read 4, iclass 25, count 0 2006.201.16:21:28.89#ibcon#read 4, iclass 25, count 0 2006.201.16:21:28.89#ibcon#about to read 5, iclass 25, count 0 2006.201.16:21:28.89#ibcon#read 5, iclass 25, count 0 2006.201.16:21:28.89#ibcon#about to read 6, iclass 25, count 0 2006.201.16:21:28.89#ibcon#read 6, iclass 25, count 0 2006.201.16:21:28.89#ibcon#end of sib2, iclass 25, count 0 2006.201.16:21:28.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:21:28.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:21:28.89#ibcon#[25=USB\r\n] 2006.201.16:21:28.89#ibcon#*before write, iclass 25, count 0 2006.201.16:21:28.89#ibcon#enter sib2, iclass 25, count 0 2006.201.16:21:28.89#ibcon#flushed, iclass 25, count 0 2006.201.16:21:28.89#ibcon#about to write, iclass 25, count 0 2006.201.16:21:28.89#ibcon#wrote, iclass 25, count 0 2006.201.16:21:28.89#ibcon#about to read 3, iclass 25, count 0 2006.201.16:21:28.92#ibcon#read 3, iclass 25, count 0 2006.201.16:21:28.92#ibcon#about to read 4, iclass 25, count 0 2006.201.16:21:28.92#ibcon#read 4, iclass 25, count 0 2006.201.16:21:28.92#ibcon#about to read 5, iclass 25, count 0 2006.201.16:21:28.92#ibcon#read 5, iclass 25, count 0 2006.201.16:21:28.92#ibcon#about to read 6, iclass 25, count 0 2006.201.16:21:28.92#ibcon#read 6, iclass 25, count 0 2006.201.16:21:28.92#ibcon#end of sib2, iclass 25, count 0 2006.201.16:21:28.92#ibcon#*after write, iclass 25, count 0 2006.201.16:21:28.92#ibcon#*before return 0, iclass 25, count 0 2006.201.16:21:28.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:28.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:28.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:21:28.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:21:28.92$vck44/valo=4,624.99 2006.201.16:21:28.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.16:21:28.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.16:21:28.92#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:28.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:28.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:28.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:28.92#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:21:28.92#ibcon#first serial, iclass 27, count 0 2006.201.16:21:28.92#ibcon#enter sib2, iclass 27, count 0 2006.201.16:21:28.92#ibcon#flushed, iclass 27, count 0 2006.201.16:21:28.92#ibcon#about to write, iclass 27, count 0 2006.201.16:21:28.92#ibcon#wrote, iclass 27, count 0 2006.201.16:21:28.92#ibcon#about to read 3, iclass 27, count 0 2006.201.16:21:28.94#ibcon#read 3, iclass 27, count 0 2006.201.16:21:28.94#ibcon#about to read 4, iclass 27, count 0 2006.201.16:21:28.94#ibcon#read 4, iclass 27, count 0 2006.201.16:21:28.94#ibcon#about to read 5, iclass 27, count 0 2006.201.16:21:28.94#ibcon#read 5, iclass 27, count 0 2006.201.16:21:28.94#ibcon#about to read 6, iclass 27, count 0 2006.201.16:21:28.94#ibcon#read 6, iclass 27, count 0 2006.201.16:21:28.94#ibcon#end of sib2, iclass 27, count 0 2006.201.16:21:28.94#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:21:28.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:21:28.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:21:28.94#ibcon#*before write, iclass 27, count 0 2006.201.16:21:28.94#ibcon#enter sib2, iclass 27, count 0 2006.201.16:21:28.94#ibcon#flushed, iclass 27, count 0 2006.201.16:21:28.94#ibcon#about to write, iclass 27, count 0 2006.201.16:21:28.94#ibcon#wrote, iclass 27, count 0 2006.201.16:21:28.94#ibcon#about to read 3, iclass 27, count 0 2006.201.16:21:28.99#ibcon#read 3, iclass 27, count 0 2006.201.16:21:28.99#ibcon#about to read 4, iclass 27, count 0 2006.201.16:21:28.99#ibcon#read 4, iclass 27, count 0 2006.201.16:21:28.99#ibcon#about to read 5, iclass 27, count 0 2006.201.16:21:28.99#ibcon#read 5, iclass 27, count 0 2006.201.16:21:28.99#ibcon#about to read 6, iclass 27, count 0 2006.201.16:21:28.99#ibcon#read 6, iclass 27, count 0 2006.201.16:21:28.99#ibcon#end of sib2, iclass 27, count 0 2006.201.16:21:28.99#ibcon#*after write, iclass 27, count 0 2006.201.16:21:28.99#ibcon#*before return 0, iclass 27, count 0 2006.201.16:21:28.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:28.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:28.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:21:28.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:21:28.99$vck44/va=4,7 2006.201.16:21:28.99#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.16:21:28.99#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.16:21:28.99#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:28.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:29.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:29.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:29.04#ibcon#enter wrdev, iclass 29, count 2 2006.201.16:21:29.04#ibcon#first serial, iclass 29, count 2 2006.201.16:21:29.04#ibcon#enter sib2, iclass 29, count 2 2006.201.16:21:29.04#ibcon#flushed, iclass 29, count 2 2006.201.16:21:29.04#ibcon#about to write, iclass 29, count 2 2006.201.16:21:29.04#ibcon#wrote, iclass 29, count 2 2006.201.16:21:29.04#ibcon#about to read 3, iclass 29, count 2 2006.201.16:21:29.06#ibcon#read 3, iclass 29, count 2 2006.201.16:21:29.06#ibcon#about to read 4, iclass 29, count 2 2006.201.16:21:29.06#ibcon#read 4, iclass 29, count 2 2006.201.16:21:29.06#ibcon#about to read 5, iclass 29, count 2 2006.201.16:21:29.06#ibcon#read 5, iclass 29, count 2 2006.201.16:21:29.06#ibcon#about to read 6, iclass 29, count 2 2006.201.16:21:29.06#ibcon#read 6, iclass 29, count 2 2006.201.16:21:29.06#ibcon#end of sib2, iclass 29, count 2 2006.201.16:21:29.06#ibcon#*mode == 0, iclass 29, count 2 2006.201.16:21:29.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.16:21:29.06#ibcon#[25=AT04-07\r\n] 2006.201.16:21:29.06#ibcon#*before write, iclass 29, count 2 2006.201.16:21:29.06#ibcon#enter sib2, iclass 29, count 2 2006.201.16:21:29.06#ibcon#flushed, iclass 29, count 2 2006.201.16:21:29.06#ibcon#about to write, iclass 29, count 2 2006.201.16:21:29.06#ibcon#wrote, iclass 29, count 2 2006.201.16:21:29.06#ibcon#about to read 3, iclass 29, count 2 2006.201.16:21:29.09#ibcon#read 3, iclass 29, count 2 2006.201.16:21:29.09#ibcon#about to read 4, iclass 29, count 2 2006.201.16:21:29.09#ibcon#read 4, iclass 29, count 2 2006.201.16:21:29.09#ibcon#about to read 5, iclass 29, count 2 2006.201.16:21:29.09#ibcon#read 5, iclass 29, count 2 2006.201.16:21:29.09#ibcon#about to read 6, iclass 29, count 2 2006.201.16:21:29.09#ibcon#read 6, iclass 29, count 2 2006.201.16:21:29.09#ibcon#end of sib2, iclass 29, count 2 2006.201.16:21:29.09#ibcon#*after write, iclass 29, count 2 2006.201.16:21:29.09#ibcon#*before return 0, iclass 29, count 2 2006.201.16:21:29.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:29.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:29.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.16:21:29.09#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:29.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:29.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:29.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:29.21#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:21:29.21#ibcon#first serial, iclass 29, count 0 2006.201.16:21:29.21#ibcon#enter sib2, iclass 29, count 0 2006.201.16:21:29.21#ibcon#flushed, iclass 29, count 0 2006.201.16:21:29.21#ibcon#about to write, iclass 29, count 0 2006.201.16:21:29.21#ibcon#wrote, iclass 29, count 0 2006.201.16:21:29.21#ibcon#about to read 3, iclass 29, count 0 2006.201.16:21:29.23#ibcon#read 3, iclass 29, count 0 2006.201.16:21:29.23#ibcon#about to read 4, iclass 29, count 0 2006.201.16:21:29.23#ibcon#read 4, iclass 29, count 0 2006.201.16:21:29.23#ibcon#about to read 5, iclass 29, count 0 2006.201.16:21:29.23#ibcon#read 5, iclass 29, count 0 2006.201.16:21:29.23#ibcon#about to read 6, iclass 29, count 0 2006.201.16:21:29.23#ibcon#read 6, iclass 29, count 0 2006.201.16:21:29.23#ibcon#end of sib2, iclass 29, count 0 2006.201.16:21:29.23#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:21:29.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:21:29.23#ibcon#[25=USB\r\n] 2006.201.16:21:29.23#ibcon#*before write, iclass 29, count 0 2006.201.16:21:29.23#ibcon#enter sib2, iclass 29, count 0 2006.201.16:21:29.23#ibcon#flushed, iclass 29, count 0 2006.201.16:21:29.23#ibcon#about to write, iclass 29, count 0 2006.201.16:21:29.23#ibcon#wrote, iclass 29, count 0 2006.201.16:21:29.23#ibcon#about to read 3, iclass 29, count 0 2006.201.16:21:29.26#ibcon#read 3, iclass 29, count 0 2006.201.16:21:29.26#ibcon#about to read 4, iclass 29, count 0 2006.201.16:21:29.26#ibcon#read 4, iclass 29, count 0 2006.201.16:21:29.26#ibcon#about to read 5, iclass 29, count 0 2006.201.16:21:29.26#ibcon#read 5, iclass 29, count 0 2006.201.16:21:29.26#ibcon#about to read 6, iclass 29, count 0 2006.201.16:21:29.26#ibcon#read 6, iclass 29, count 0 2006.201.16:21:29.26#ibcon#end of sib2, iclass 29, count 0 2006.201.16:21:29.26#ibcon#*after write, iclass 29, count 0 2006.201.16:21:29.26#ibcon#*before return 0, iclass 29, count 0 2006.201.16:21:29.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:29.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:29.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:21:29.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:21:29.26$vck44/valo=5,734.99 2006.201.16:21:29.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.16:21:29.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.16:21:29.26#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:29.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:29.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:29.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:29.26#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:21:29.26#ibcon#first serial, iclass 31, count 0 2006.201.16:21:29.26#ibcon#enter sib2, iclass 31, count 0 2006.201.16:21:29.26#ibcon#flushed, iclass 31, count 0 2006.201.16:21:29.26#ibcon#about to write, iclass 31, count 0 2006.201.16:21:29.26#ibcon#wrote, iclass 31, count 0 2006.201.16:21:29.26#ibcon#about to read 3, iclass 31, count 0 2006.201.16:21:29.28#ibcon#read 3, iclass 31, count 0 2006.201.16:21:29.28#ibcon#about to read 4, iclass 31, count 0 2006.201.16:21:29.28#ibcon#read 4, iclass 31, count 0 2006.201.16:21:29.28#ibcon#about to read 5, iclass 31, count 0 2006.201.16:21:29.28#ibcon#read 5, iclass 31, count 0 2006.201.16:21:29.28#ibcon#about to read 6, iclass 31, count 0 2006.201.16:21:29.28#ibcon#read 6, iclass 31, count 0 2006.201.16:21:29.28#ibcon#end of sib2, iclass 31, count 0 2006.201.16:21:29.28#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:21:29.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:21:29.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:21:29.28#ibcon#*before write, iclass 31, count 0 2006.201.16:21:29.28#ibcon#enter sib2, iclass 31, count 0 2006.201.16:21:29.28#ibcon#flushed, iclass 31, count 0 2006.201.16:21:29.28#ibcon#about to write, iclass 31, count 0 2006.201.16:21:29.28#ibcon#wrote, iclass 31, count 0 2006.201.16:21:29.28#ibcon#about to read 3, iclass 31, count 0 2006.201.16:21:29.32#ibcon#read 3, iclass 31, count 0 2006.201.16:21:29.32#ibcon#about to read 4, iclass 31, count 0 2006.201.16:21:29.32#ibcon#read 4, iclass 31, count 0 2006.201.16:21:29.32#ibcon#about to read 5, iclass 31, count 0 2006.201.16:21:29.32#ibcon#read 5, iclass 31, count 0 2006.201.16:21:29.32#ibcon#about to read 6, iclass 31, count 0 2006.201.16:21:29.32#ibcon#read 6, iclass 31, count 0 2006.201.16:21:29.32#ibcon#end of sib2, iclass 31, count 0 2006.201.16:21:29.32#ibcon#*after write, iclass 31, count 0 2006.201.16:21:29.32#ibcon#*before return 0, iclass 31, count 0 2006.201.16:21:29.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:29.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:29.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:21:29.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:21:29.32$vck44/va=5,4 2006.201.16:21:29.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.16:21:29.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.16:21:29.32#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:29.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:29.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:29.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:29.38#ibcon#enter wrdev, iclass 33, count 2 2006.201.16:21:29.38#ibcon#first serial, iclass 33, count 2 2006.201.16:21:29.38#ibcon#enter sib2, iclass 33, count 2 2006.201.16:21:29.38#ibcon#flushed, iclass 33, count 2 2006.201.16:21:29.38#ibcon#about to write, iclass 33, count 2 2006.201.16:21:29.38#ibcon#wrote, iclass 33, count 2 2006.201.16:21:29.38#ibcon#about to read 3, iclass 33, count 2 2006.201.16:21:29.40#ibcon#read 3, iclass 33, count 2 2006.201.16:21:29.40#ibcon#about to read 4, iclass 33, count 2 2006.201.16:21:29.40#ibcon#read 4, iclass 33, count 2 2006.201.16:21:29.40#ibcon#about to read 5, iclass 33, count 2 2006.201.16:21:29.40#ibcon#read 5, iclass 33, count 2 2006.201.16:21:29.40#ibcon#about to read 6, iclass 33, count 2 2006.201.16:21:29.40#ibcon#read 6, iclass 33, count 2 2006.201.16:21:29.40#ibcon#end of sib2, iclass 33, count 2 2006.201.16:21:29.40#ibcon#*mode == 0, iclass 33, count 2 2006.201.16:21:29.40#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.16:21:29.40#ibcon#[25=AT05-04\r\n] 2006.201.16:21:29.40#ibcon#*before write, iclass 33, count 2 2006.201.16:21:29.40#ibcon#enter sib2, iclass 33, count 2 2006.201.16:21:29.40#ibcon#flushed, iclass 33, count 2 2006.201.16:21:29.40#ibcon#about to write, iclass 33, count 2 2006.201.16:21:29.40#ibcon#wrote, iclass 33, count 2 2006.201.16:21:29.40#ibcon#about to read 3, iclass 33, count 2 2006.201.16:21:29.43#ibcon#read 3, iclass 33, count 2 2006.201.16:21:29.43#ibcon#about to read 4, iclass 33, count 2 2006.201.16:21:29.43#ibcon#read 4, iclass 33, count 2 2006.201.16:21:29.43#ibcon#about to read 5, iclass 33, count 2 2006.201.16:21:29.43#ibcon#read 5, iclass 33, count 2 2006.201.16:21:29.43#ibcon#about to read 6, iclass 33, count 2 2006.201.16:21:29.43#ibcon#read 6, iclass 33, count 2 2006.201.16:21:29.43#ibcon#end of sib2, iclass 33, count 2 2006.201.16:21:29.43#ibcon#*after write, iclass 33, count 2 2006.201.16:21:29.43#ibcon#*before return 0, iclass 33, count 2 2006.201.16:21:29.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:29.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:29.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.16:21:29.43#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:29.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:29.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:29.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:29.55#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:21:29.55#ibcon#first serial, iclass 33, count 0 2006.201.16:21:29.55#ibcon#enter sib2, iclass 33, count 0 2006.201.16:21:29.55#ibcon#flushed, iclass 33, count 0 2006.201.16:21:29.55#ibcon#about to write, iclass 33, count 0 2006.201.16:21:29.55#ibcon#wrote, iclass 33, count 0 2006.201.16:21:29.55#ibcon#about to read 3, iclass 33, count 0 2006.201.16:21:29.57#ibcon#read 3, iclass 33, count 0 2006.201.16:21:29.57#ibcon#about to read 4, iclass 33, count 0 2006.201.16:21:29.57#ibcon#read 4, iclass 33, count 0 2006.201.16:21:29.57#ibcon#about to read 5, iclass 33, count 0 2006.201.16:21:29.57#ibcon#read 5, iclass 33, count 0 2006.201.16:21:29.57#ibcon#about to read 6, iclass 33, count 0 2006.201.16:21:29.57#ibcon#read 6, iclass 33, count 0 2006.201.16:21:29.57#ibcon#end of sib2, iclass 33, count 0 2006.201.16:21:29.57#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:21:29.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:21:29.57#ibcon#[25=USB\r\n] 2006.201.16:21:29.57#ibcon#*before write, iclass 33, count 0 2006.201.16:21:29.57#ibcon#enter sib2, iclass 33, count 0 2006.201.16:21:29.57#ibcon#flushed, iclass 33, count 0 2006.201.16:21:29.57#ibcon#about to write, iclass 33, count 0 2006.201.16:21:29.57#ibcon#wrote, iclass 33, count 0 2006.201.16:21:29.57#ibcon#about to read 3, iclass 33, count 0 2006.201.16:21:29.60#ibcon#read 3, iclass 33, count 0 2006.201.16:21:29.60#ibcon#about to read 4, iclass 33, count 0 2006.201.16:21:29.60#ibcon#read 4, iclass 33, count 0 2006.201.16:21:29.60#ibcon#about to read 5, iclass 33, count 0 2006.201.16:21:29.60#ibcon#read 5, iclass 33, count 0 2006.201.16:21:29.60#ibcon#about to read 6, iclass 33, count 0 2006.201.16:21:29.60#ibcon#read 6, iclass 33, count 0 2006.201.16:21:29.60#ibcon#end of sib2, iclass 33, count 0 2006.201.16:21:29.60#ibcon#*after write, iclass 33, count 0 2006.201.16:21:29.60#ibcon#*before return 0, iclass 33, count 0 2006.201.16:21:29.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:29.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:29.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:21:29.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:21:29.60$vck44/valo=6,814.99 2006.201.16:21:29.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.16:21:29.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.16:21:29.60#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:29.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:29.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:29.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:29.60#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:21:29.60#ibcon#first serial, iclass 35, count 0 2006.201.16:21:29.60#ibcon#enter sib2, iclass 35, count 0 2006.201.16:21:29.60#ibcon#flushed, iclass 35, count 0 2006.201.16:21:29.60#ibcon#about to write, iclass 35, count 0 2006.201.16:21:29.60#ibcon#wrote, iclass 35, count 0 2006.201.16:21:29.60#ibcon#about to read 3, iclass 35, count 0 2006.201.16:21:29.62#ibcon#read 3, iclass 35, count 0 2006.201.16:21:29.62#ibcon#about to read 4, iclass 35, count 0 2006.201.16:21:29.62#ibcon#read 4, iclass 35, count 0 2006.201.16:21:29.62#ibcon#about to read 5, iclass 35, count 0 2006.201.16:21:29.62#ibcon#read 5, iclass 35, count 0 2006.201.16:21:29.62#ibcon#about to read 6, iclass 35, count 0 2006.201.16:21:29.62#ibcon#read 6, iclass 35, count 0 2006.201.16:21:29.62#ibcon#end of sib2, iclass 35, count 0 2006.201.16:21:29.62#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:21:29.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:21:29.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:21:29.62#ibcon#*before write, iclass 35, count 0 2006.201.16:21:29.62#ibcon#enter sib2, iclass 35, count 0 2006.201.16:21:29.62#ibcon#flushed, iclass 35, count 0 2006.201.16:21:29.62#ibcon#about to write, iclass 35, count 0 2006.201.16:21:29.62#ibcon#wrote, iclass 35, count 0 2006.201.16:21:29.62#ibcon#about to read 3, iclass 35, count 0 2006.201.16:21:29.67#ibcon#read 3, iclass 35, count 0 2006.201.16:21:29.67#ibcon#about to read 4, iclass 35, count 0 2006.201.16:21:29.67#ibcon#read 4, iclass 35, count 0 2006.201.16:21:29.67#ibcon#about to read 5, iclass 35, count 0 2006.201.16:21:29.67#ibcon#read 5, iclass 35, count 0 2006.201.16:21:29.67#ibcon#about to read 6, iclass 35, count 0 2006.201.16:21:29.67#ibcon#read 6, iclass 35, count 0 2006.201.16:21:29.67#ibcon#end of sib2, iclass 35, count 0 2006.201.16:21:29.67#ibcon#*after write, iclass 35, count 0 2006.201.16:21:29.67#ibcon#*before return 0, iclass 35, count 0 2006.201.16:21:29.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:29.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:29.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:21:29.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:21:29.67$vck44/va=6,5 2006.201.16:21:29.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.16:21:29.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.16:21:29.67#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:29.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:29.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:29.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:29.72#ibcon#enter wrdev, iclass 37, count 2 2006.201.16:21:29.72#ibcon#first serial, iclass 37, count 2 2006.201.16:21:29.72#ibcon#enter sib2, iclass 37, count 2 2006.201.16:21:29.72#ibcon#flushed, iclass 37, count 2 2006.201.16:21:29.72#ibcon#about to write, iclass 37, count 2 2006.201.16:21:29.72#ibcon#wrote, iclass 37, count 2 2006.201.16:21:29.72#ibcon#about to read 3, iclass 37, count 2 2006.201.16:21:29.74#ibcon#read 3, iclass 37, count 2 2006.201.16:21:29.74#ibcon#about to read 4, iclass 37, count 2 2006.201.16:21:29.74#ibcon#read 4, iclass 37, count 2 2006.201.16:21:29.74#ibcon#about to read 5, iclass 37, count 2 2006.201.16:21:29.74#ibcon#read 5, iclass 37, count 2 2006.201.16:21:29.74#ibcon#about to read 6, iclass 37, count 2 2006.201.16:21:29.74#ibcon#read 6, iclass 37, count 2 2006.201.16:21:29.74#ibcon#end of sib2, iclass 37, count 2 2006.201.16:21:29.74#ibcon#*mode == 0, iclass 37, count 2 2006.201.16:21:29.74#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.16:21:29.74#ibcon#[25=AT06-05\r\n] 2006.201.16:21:29.74#ibcon#*before write, iclass 37, count 2 2006.201.16:21:29.74#ibcon#enter sib2, iclass 37, count 2 2006.201.16:21:29.74#ibcon#flushed, iclass 37, count 2 2006.201.16:21:29.74#ibcon#about to write, iclass 37, count 2 2006.201.16:21:29.74#ibcon#wrote, iclass 37, count 2 2006.201.16:21:29.74#ibcon#about to read 3, iclass 37, count 2 2006.201.16:21:29.77#ibcon#read 3, iclass 37, count 2 2006.201.16:21:29.77#ibcon#about to read 4, iclass 37, count 2 2006.201.16:21:29.77#ibcon#read 4, iclass 37, count 2 2006.201.16:21:29.77#ibcon#about to read 5, iclass 37, count 2 2006.201.16:21:29.77#ibcon#read 5, iclass 37, count 2 2006.201.16:21:29.77#ibcon#about to read 6, iclass 37, count 2 2006.201.16:21:29.77#ibcon#read 6, iclass 37, count 2 2006.201.16:21:29.77#ibcon#end of sib2, iclass 37, count 2 2006.201.16:21:29.77#ibcon#*after write, iclass 37, count 2 2006.201.16:21:29.77#ibcon#*before return 0, iclass 37, count 2 2006.201.16:21:29.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:29.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:29.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.16:21:29.77#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:29.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:29.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:29.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:29.89#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:21:29.89#ibcon#first serial, iclass 37, count 0 2006.201.16:21:29.89#ibcon#enter sib2, iclass 37, count 0 2006.201.16:21:29.89#ibcon#flushed, iclass 37, count 0 2006.201.16:21:29.89#ibcon#about to write, iclass 37, count 0 2006.201.16:21:29.89#ibcon#wrote, iclass 37, count 0 2006.201.16:21:29.89#ibcon#about to read 3, iclass 37, count 0 2006.201.16:21:29.91#ibcon#read 3, iclass 37, count 0 2006.201.16:21:29.91#ibcon#about to read 4, iclass 37, count 0 2006.201.16:21:29.91#ibcon#read 4, iclass 37, count 0 2006.201.16:21:29.91#ibcon#about to read 5, iclass 37, count 0 2006.201.16:21:29.91#ibcon#read 5, iclass 37, count 0 2006.201.16:21:29.91#ibcon#about to read 6, iclass 37, count 0 2006.201.16:21:29.91#ibcon#read 6, iclass 37, count 0 2006.201.16:21:29.91#ibcon#end of sib2, iclass 37, count 0 2006.201.16:21:29.91#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:21:29.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:21:29.91#ibcon#[25=USB\r\n] 2006.201.16:21:29.91#ibcon#*before write, iclass 37, count 0 2006.201.16:21:29.91#ibcon#enter sib2, iclass 37, count 0 2006.201.16:21:29.91#ibcon#flushed, iclass 37, count 0 2006.201.16:21:29.91#ibcon#about to write, iclass 37, count 0 2006.201.16:21:29.91#ibcon#wrote, iclass 37, count 0 2006.201.16:21:29.91#ibcon#about to read 3, iclass 37, count 0 2006.201.16:21:29.94#ibcon#read 3, iclass 37, count 0 2006.201.16:21:29.94#ibcon#about to read 4, iclass 37, count 0 2006.201.16:21:29.94#ibcon#read 4, iclass 37, count 0 2006.201.16:21:29.94#ibcon#about to read 5, iclass 37, count 0 2006.201.16:21:29.94#ibcon#read 5, iclass 37, count 0 2006.201.16:21:29.94#ibcon#about to read 6, iclass 37, count 0 2006.201.16:21:29.94#ibcon#read 6, iclass 37, count 0 2006.201.16:21:29.94#ibcon#end of sib2, iclass 37, count 0 2006.201.16:21:29.94#ibcon#*after write, iclass 37, count 0 2006.201.16:21:29.94#ibcon#*before return 0, iclass 37, count 0 2006.201.16:21:29.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:29.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:29.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:21:29.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:21:29.94$vck44/valo=7,864.99 2006.201.16:21:29.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.16:21:29.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.16:21:29.94#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:29.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:29.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:29.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:29.94#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:21:29.94#ibcon#first serial, iclass 39, count 0 2006.201.16:21:29.94#ibcon#enter sib2, iclass 39, count 0 2006.201.16:21:29.94#ibcon#flushed, iclass 39, count 0 2006.201.16:21:29.94#ibcon#about to write, iclass 39, count 0 2006.201.16:21:29.94#ibcon#wrote, iclass 39, count 0 2006.201.16:21:29.94#ibcon#about to read 3, iclass 39, count 0 2006.201.16:21:29.96#ibcon#read 3, iclass 39, count 0 2006.201.16:21:29.96#ibcon#about to read 4, iclass 39, count 0 2006.201.16:21:29.96#ibcon#read 4, iclass 39, count 0 2006.201.16:21:29.96#ibcon#about to read 5, iclass 39, count 0 2006.201.16:21:29.96#ibcon#read 5, iclass 39, count 0 2006.201.16:21:29.96#ibcon#about to read 6, iclass 39, count 0 2006.201.16:21:29.96#ibcon#read 6, iclass 39, count 0 2006.201.16:21:29.96#ibcon#end of sib2, iclass 39, count 0 2006.201.16:21:29.96#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:21:29.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:21:29.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:21:29.96#ibcon#*before write, iclass 39, count 0 2006.201.16:21:29.96#ibcon#enter sib2, iclass 39, count 0 2006.201.16:21:29.96#ibcon#flushed, iclass 39, count 0 2006.201.16:21:29.96#ibcon#about to write, iclass 39, count 0 2006.201.16:21:29.96#ibcon#wrote, iclass 39, count 0 2006.201.16:21:29.96#ibcon#about to read 3, iclass 39, count 0 2006.201.16:21:30.00#ibcon#read 3, iclass 39, count 0 2006.201.16:21:30.00#ibcon#about to read 4, iclass 39, count 0 2006.201.16:21:30.00#ibcon#read 4, iclass 39, count 0 2006.201.16:21:30.00#ibcon#about to read 5, iclass 39, count 0 2006.201.16:21:30.00#ibcon#read 5, iclass 39, count 0 2006.201.16:21:30.00#ibcon#about to read 6, iclass 39, count 0 2006.201.16:21:30.00#ibcon#read 6, iclass 39, count 0 2006.201.16:21:30.00#ibcon#end of sib2, iclass 39, count 0 2006.201.16:21:30.00#ibcon#*after write, iclass 39, count 0 2006.201.16:21:30.00#ibcon#*before return 0, iclass 39, count 0 2006.201.16:21:30.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:30.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:30.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:21:30.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:21:30.00$vck44/va=7,5 2006.201.16:21:30.00#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.16:21:30.00#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.16:21:30.00#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:30.00#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:30.06#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:30.06#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:30.06#ibcon#enter wrdev, iclass 2, count 2 2006.201.16:21:30.06#ibcon#first serial, iclass 2, count 2 2006.201.16:21:30.06#ibcon#enter sib2, iclass 2, count 2 2006.201.16:21:30.06#ibcon#flushed, iclass 2, count 2 2006.201.16:21:30.06#ibcon#about to write, iclass 2, count 2 2006.201.16:21:30.06#ibcon#wrote, iclass 2, count 2 2006.201.16:21:30.06#ibcon#about to read 3, iclass 2, count 2 2006.201.16:21:30.08#ibcon#read 3, iclass 2, count 2 2006.201.16:21:30.08#ibcon#about to read 4, iclass 2, count 2 2006.201.16:21:30.08#ibcon#read 4, iclass 2, count 2 2006.201.16:21:30.08#ibcon#about to read 5, iclass 2, count 2 2006.201.16:21:30.08#ibcon#read 5, iclass 2, count 2 2006.201.16:21:30.08#ibcon#about to read 6, iclass 2, count 2 2006.201.16:21:30.08#ibcon#read 6, iclass 2, count 2 2006.201.16:21:30.08#ibcon#end of sib2, iclass 2, count 2 2006.201.16:21:30.08#ibcon#*mode == 0, iclass 2, count 2 2006.201.16:21:30.08#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.16:21:30.08#ibcon#[25=AT07-05\r\n] 2006.201.16:21:30.08#ibcon#*before write, iclass 2, count 2 2006.201.16:21:30.08#ibcon#enter sib2, iclass 2, count 2 2006.201.16:21:30.08#ibcon#flushed, iclass 2, count 2 2006.201.16:21:30.08#ibcon#about to write, iclass 2, count 2 2006.201.16:21:30.08#ibcon#wrote, iclass 2, count 2 2006.201.16:21:30.08#ibcon#about to read 3, iclass 2, count 2 2006.201.16:21:30.11#ibcon#read 3, iclass 2, count 2 2006.201.16:21:30.11#ibcon#about to read 4, iclass 2, count 2 2006.201.16:21:30.11#ibcon#read 4, iclass 2, count 2 2006.201.16:21:30.11#ibcon#about to read 5, iclass 2, count 2 2006.201.16:21:30.11#ibcon#read 5, iclass 2, count 2 2006.201.16:21:30.11#ibcon#about to read 6, iclass 2, count 2 2006.201.16:21:30.11#ibcon#read 6, iclass 2, count 2 2006.201.16:21:30.11#ibcon#end of sib2, iclass 2, count 2 2006.201.16:21:30.11#ibcon#*after write, iclass 2, count 2 2006.201.16:21:30.11#ibcon#*before return 0, iclass 2, count 2 2006.201.16:21:30.11#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:30.11#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:30.11#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.16:21:30.11#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:30.11#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:30.23#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:30.23#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:30.23#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:21:30.23#ibcon#first serial, iclass 2, count 0 2006.201.16:21:30.23#ibcon#enter sib2, iclass 2, count 0 2006.201.16:21:30.23#ibcon#flushed, iclass 2, count 0 2006.201.16:21:30.23#ibcon#about to write, iclass 2, count 0 2006.201.16:21:30.23#ibcon#wrote, iclass 2, count 0 2006.201.16:21:30.23#ibcon#about to read 3, iclass 2, count 0 2006.201.16:21:30.25#ibcon#read 3, iclass 2, count 0 2006.201.16:21:30.25#ibcon#about to read 4, iclass 2, count 0 2006.201.16:21:30.25#ibcon#read 4, iclass 2, count 0 2006.201.16:21:30.25#ibcon#about to read 5, iclass 2, count 0 2006.201.16:21:30.25#ibcon#read 5, iclass 2, count 0 2006.201.16:21:30.25#ibcon#about to read 6, iclass 2, count 0 2006.201.16:21:30.25#ibcon#read 6, iclass 2, count 0 2006.201.16:21:30.25#ibcon#end of sib2, iclass 2, count 0 2006.201.16:21:30.25#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:21:30.25#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:21:30.25#ibcon#[25=USB\r\n] 2006.201.16:21:30.25#ibcon#*before write, iclass 2, count 0 2006.201.16:21:30.25#ibcon#enter sib2, iclass 2, count 0 2006.201.16:21:30.25#ibcon#flushed, iclass 2, count 0 2006.201.16:21:30.25#ibcon#about to write, iclass 2, count 0 2006.201.16:21:30.25#ibcon#wrote, iclass 2, count 0 2006.201.16:21:30.25#ibcon#about to read 3, iclass 2, count 0 2006.201.16:21:30.28#ibcon#read 3, iclass 2, count 0 2006.201.16:21:30.28#ibcon#about to read 4, iclass 2, count 0 2006.201.16:21:30.28#ibcon#read 4, iclass 2, count 0 2006.201.16:21:30.28#ibcon#about to read 5, iclass 2, count 0 2006.201.16:21:30.28#ibcon#read 5, iclass 2, count 0 2006.201.16:21:30.28#ibcon#about to read 6, iclass 2, count 0 2006.201.16:21:30.28#ibcon#read 6, iclass 2, count 0 2006.201.16:21:30.28#ibcon#end of sib2, iclass 2, count 0 2006.201.16:21:30.28#ibcon#*after write, iclass 2, count 0 2006.201.16:21:30.28#ibcon#*before return 0, iclass 2, count 0 2006.201.16:21:30.28#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:30.28#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:30.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:21:30.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:21:30.28$vck44/valo=8,884.99 2006.201.16:21:30.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.16:21:30.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.16:21:30.28#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:30.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:30.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:30.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:30.28#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:21:30.28#ibcon#first serial, iclass 5, count 0 2006.201.16:21:30.28#ibcon#enter sib2, iclass 5, count 0 2006.201.16:21:30.28#ibcon#flushed, iclass 5, count 0 2006.201.16:21:30.28#ibcon#about to write, iclass 5, count 0 2006.201.16:21:30.28#ibcon#wrote, iclass 5, count 0 2006.201.16:21:30.28#ibcon#about to read 3, iclass 5, count 0 2006.201.16:21:30.30#ibcon#read 3, iclass 5, count 0 2006.201.16:21:30.30#ibcon#about to read 4, iclass 5, count 0 2006.201.16:21:30.30#ibcon#read 4, iclass 5, count 0 2006.201.16:21:30.30#ibcon#about to read 5, iclass 5, count 0 2006.201.16:21:30.30#ibcon#read 5, iclass 5, count 0 2006.201.16:21:30.30#ibcon#about to read 6, iclass 5, count 0 2006.201.16:21:30.30#ibcon#read 6, iclass 5, count 0 2006.201.16:21:30.30#ibcon#end of sib2, iclass 5, count 0 2006.201.16:21:30.30#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:21:30.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:21:30.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:21:30.30#ibcon#*before write, iclass 5, count 0 2006.201.16:21:30.30#ibcon#enter sib2, iclass 5, count 0 2006.201.16:21:30.30#ibcon#flushed, iclass 5, count 0 2006.201.16:21:30.30#ibcon#about to write, iclass 5, count 0 2006.201.16:21:30.30#ibcon#wrote, iclass 5, count 0 2006.201.16:21:30.30#ibcon#about to read 3, iclass 5, count 0 2006.201.16:21:30.34#ibcon#read 3, iclass 5, count 0 2006.201.16:21:30.34#ibcon#about to read 4, iclass 5, count 0 2006.201.16:21:30.34#ibcon#read 4, iclass 5, count 0 2006.201.16:21:30.34#ibcon#about to read 5, iclass 5, count 0 2006.201.16:21:30.34#ibcon#read 5, iclass 5, count 0 2006.201.16:21:30.34#ibcon#about to read 6, iclass 5, count 0 2006.201.16:21:30.34#ibcon#read 6, iclass 5, count 0 2006.201.16:21:30.34#ibcon#end of sib2, iclass 5, count 0 2006.201.16:21:30.34#ibcon#*after write, iclass 5, count 0 2006.201.16:21:30.34#ibcon#*before return 0, iclass 5, count 0 2006.201.16:21:30.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:30.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:30.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:21:30.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:21:30.34$vck44/va=8,4 2006.201.16:21:30.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.16:21:30.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.16:21:30.34#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:30.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:21:30.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:21:30.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:21:30.40#ibcon#enter wrdev, iclass 7, count 2 2006.201.16:21:30.40#ibcon#first serial, iclass 7, count 2 2006.201.16:21:30.40#ibcon#enter sib2, iclass 7, count 2 2006.201.16:21:30.40#ibcon#flushed, iclass 7, count 2 2006.201.16:21:30.40#ibcon#about to write, iclass 7, count 2 2006.201.16:21:30.40#ibcon#wrote, iclass 7, count 2 2006.201.16:21:30.40#ibcon#about to read 3, iclass 7, count 2 2006.201.16:21:30.42#ibcon#read 3, iclass 7, count 2 2006.201.16:21:30.42#ibcon#about to read 4, iclass 7, count 2 2006.201.16:21:30.42#ibcon#read 4, iclass 7, count 2 2006.201.16:21:30.42#ibcon#about to read 5, iclass 7, count 2 2006.201.16:21:30.42#ibcon#read 5, iclass 7, count 2 2006.201.16:21:30.42#ibcon#about to read 6, iclass 7, count 2 2006.201.16:21:30.42#ibcon#read 6, iclass 7, count 2 2006.201.16:21:30.42#ibcon#end of sib2, iclass 7, count 2 2006.201.16:21:30.42#ibcon#*mode == 0, iclass 7, count 2 2006.201.16:21:30.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.16:21:30.42#ibcon#[25=AT08-04\r\n] 2006.201.16:21:30.42#ibcon#*before write, iclass 7, count 2 2006.201.16:21:30.42#ibcon#enter sib2, iclass 7, count 2 2006.201.16:21:30.42#ibcon#flushed, iclass 7, count 2 2006.201.16:21:30.42#ibcon#about to write, iclass 7, count 2 2006.201.16:21:30.42#ibcon#wrote, iclass 7, count 2 2006.201.16:21:30.42#ibcon#about to read 3, iclass 7, count 2 2006.201.16:21:30.45#ibcon#read 3, iclass 7, count 2 2006.201.16:21:30.45#ibcon#about to read 4, iclass 7, count 2 2006.201.16:21:30.45#ibcon#read 4, iclass 7, count 2 2006.201.16:21:30.45#ibcon#about to read 5, iclass 7, count 2 2006.201.16:21:30.45#ibcon#read 5, iclass 7, count 2 2006.201.16:21:30.45#ibcon#about to read 6, iclass 7, count 2 2006.201.16:21:30.45#ibcon#read 6, iclass 7, count 2 2006.201.16:21:30.45#ibcon#end of sib2, iclass 7, count 2 2006.201.16:21:30.45#ibcon#*after write, iclass 7, count 2 2006.201.16:21:30.45#ibcon#*before return 0, iclass 7, count 2 2006.201.16:21:30.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:21:30.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:21:30.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.16:21:30.45#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:30.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:21:30.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:21:30.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:21:30.57#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:21:30.57#ibcon#first serial, iclass 7, count 0 2006.201.16:21:30.57#ibcon#enter sib2, iclass 7, count 0 2006.201.16:21:30.57#ibcon#flushed, iclass 7, count 0 2006.201.16:21:30.57#ibcon#about to write, iclass 7, count 0 2006.201.16:21:30.57#ibcon#wrote, iclass 7, count 0 2006.201.16:21:30.57#ibcon#about to read 3, iclass 7, count 0 2006.201.16:21:30.59#ibcon#read 3, iclass 7, count 0 2006.201.16:21:30.59#ibcon#about to read 4, iclass 7, count 0 2006.201.16:21:30.59#ibcon#read 4, iclass 7, count 0 2006.201.16:21:30.59#ibcon#about to read 5, iclass 7, count 0 2006.201.16:21:30.59#ibcon#read 5, iclass 7, count 0 2006.201.16:21:30.59#ibcon#about to read 6, iclass 7, count 0 2006.201.16:21:30.59#ibcon#read 6, iclass 7, count 0 2006.201.16:21:30.59#ibcon#end of sib2, iclass 7, count 0 2006.201.16:21:30.59#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:21:30.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:21:30.59#ibcon#[25=USB\r\n] 2006.201.16:21:30.59#ibcon#*before write, iclass 7, count 0 2006.201.16:21:30.59#ibcon#enter sib2, iclass 7, count 0 2006.201.16:21:30.59#ibcon#flushed, iclass 7, count 0 2006.201.16:21:30.59#ibcon#about to write, iclass 7, count 0 2006.201.16:21:30.59#ibcon#wrote, iclass 7, count 0 2006.201.16:21:30.59#ibcon#about to read 3, iclass 7, count 0 2006.201.16:21:30.62#ibcon#read 3, iclass 7, count 0 2006.201.16:21:30.62#ibcon#about to read 4, iclass 7, count 0 2006.201.16:21:30.62#ibcon#read 4, iclass 7, count 0 2006.201.16:21:30.62#ibcon#about to read 5, iclass 7, count 0 2006.201.16:21:30.62#ibcon#read 5, iclass 7, count 0 2006.201.16:21:30.62#ibcon#about to read 6, iclass 7, count 0 2006.201.16:21:30.62#ibcon#read 6, iclass 7, count 0 2006.201.16:21:30.62#ibcon#end of sib2, iclass 7, count 0 2006.201.16:21:30.62#ibcon#*after write, iclass 7, count 0 2006.201.16:21:30.62#ibcon#*before return 0, iclass 7, count 0 2006.201.16:21:30.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:21:30.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:21:30.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:21:30.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:21:30.62$vck44/vblo=1,629.99 2006.201.16:21:30.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.16:21:30.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.16:21:30.62#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:30.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:21:30.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:21:30.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:21:30.62#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:21:30.62#ibcon#first serial, iclass 11, count 0 2006.201.16:21:30.62#ibcon#enter sib2, iclass 11, count 0 2006.201.16:21:30.62#ibcon#flushed, iclass 11, count 0 2006.201.16:21:30.62#ibcon#about to write, iclass 11, count 0 2006.201.16:21:30.62#ibcon#wrote, iclass 11, count 0 2006.201.16:21:30.62#ibcon#about to read 3, iclass 11, count 0 2006.201.16:21:30.64#ibcon#read 3, iclass 11, count 0 2006.201.16:21:30.64#ibcon#about to read 4, iclass 11, count 0 2006.201.16:21:30.64#ibcon#read 4, iclass 11, count 0 2006.201.16:21:30.64#ibcon#about to read 5, iclass 11, count 0 2006.201.16:21:30.64#ibcon#read 5, iclass 11, count 0 2006.201.16:21:30.64#ibcon#about to read 6, iclass 11, count 0 2006.201.16:21:30.64#ibcon#read 6, iclass 11, count 0 2006.201.16:21:30.64#ibcon#end of sib2, iclass 11, count 0 2006.201.16:21:30.64#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:21:30.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:21:30.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:21:30.64#ibcon#*before write, iclass 11, count 0 2006.201.16:21:30.64#ibcon#enter sib2, iclass 11, count 0 2006.201.16:21:30.64#ibcon#flushed, iclass 11, count 0 2006.201.16:21:30.64#ibcon#about to write, iclass 11, count 0 2006.201.16:21:30.64#ibcon#wrote, iclass 11, count 0 2006.201.16:21:30.64#ibcon#about to read 3, iclass 11, count 0 2006.201.16:21:30.69#ibcon#read 3, iclass 11, count 0 2006.201.16:21:30.69#ibcon#about to read 4, iclass 11, count 0 2006.201.16:21:30.69#ibcon#read 4, iclass 11, count 0 2006.201.16:21:30.69#ibcon#about to read 5, iclass 11, count 0 2006.201.16:21:30.69#ibcon#read 5, iclass 11, count 0 2006.201.16:21:30.69#ibcon#about to read 6, iclass 11, count 0 2006.201.16:21:30.69#ibcon#read 6, iclass 11, count 0 2006.201.16:21:30.69#ibcon#end of sib2, iclass 11, count 0 2006.201.16:21:30.69#ibcon#*after write, iclass 11, count 0 2006.201.16:21:30.69#ibcon#*before return 0, iclass 11, count 0 2006.201.16:21:30.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:21:30.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:21:30.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:21:30.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:21:30.69$vck44/vb=1,4 2006.201.16:21:30.69#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.16:21:30.69#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.16:21:30.69#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:30.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:21:30.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:21:30.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:21:30.69#ibcon#enter wrdev, iclass 13, count 2 2006.201.16:21:30.69#ibcon#first serial, iclass 13, count 2 2006.201.16:21:30.69#ibcon#enter sib2, iclass 13, count 2 2006.201.16:21:30.69#ibcon#flushed, iclass 13, count 2 2006.201.16:21:30.69#ibcon#about to write, iclass 13, count 2 2006.201.16:21:30.69#ibcon#wrote, iclass 13, count 2 2006.201.16:21:30.69#ibcon#about to read 3, iclass 13, count 2 2006.201.16:21:30.71#ibcon#read 3, iclass 13, count 2 2006.201.16:21:30.71#ibcon#about to read 4, iclass 13, count 2 2006.201.16:21:30.71#ibcon#read 4, iclass 13, count 2 2006.201.16:21:30.71#ibcon#about to read 5, iclass 13, count 2 2006.201.16:21:30.71#ibcon#read 5, iclass 13, count 2 2006.201.16:21:30.71#ibcon#about to read 6, iclass 13, count 2 2006.201.16:21:30.71#ibcon#read 6, iclass 13, count 2 2006.201.16:21:30.71#ibcon#end of sib2, iclass 13, count 2 2006.201.16:21:30.71#ibcon#*mode == 0, iclass 13, count 2 2006.201.16:21:30.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.16:21:30.71#ibcon#[27=AT01-04\r\n] 2006.201.16:21:30.71#ibcon#*before write, iclass 13, count 2 2006.201.16:21:30.71#ibcon#enter sib2, iclass 13, count 2 2006.201.16:21:30.71#ibcon#flushed, iclass 13, count 2 2006.201.16:21:30.71#ibcon#about to write, iclass 13, count 2 2006.201.16:21:30.71#ibcon#wrote, iclass 13, count 2 2006.201.16:21:30.71#ibcon#about to read 3, iclass 13, count 2 2006.201.16:21:30.74#ibcon#read 3, iclass 13, count 2 2006.201.16:21:30.74#ibcon#about to read 4, iclass 13, count 2 2006.201.16:21:30.74#ibcon#read 4, iclass 13, count 2 2006.201.16:21:30.74#ibcon#about to read 5, iclass 13, count 2 2006.201.16:21:30.74#ibcon#read 5, iclass 13, count 2 2006.201.16:21:30.74#ibcon#about to read 6, iclass 13, count 2 2006.201.16:21:30.74#ibcon#read 6, iclass 13, count 2 2006.201.16:21:30.74#ibcon#end of sib2, iclass 13, count 2 2006.201.16:21:30.74#ibcon#*after write, iclass 13, count 2 2006.201.16:21:30.74#ibcon#*before return 0, iclass 13, count 2 2006.201.16:21:30.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:21:30.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:21:30.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.16:21:30.74#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:30.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:21:30.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:21:30.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:21:30.86#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:21:30.86#ibcon#first serial, iclass 13, count 0 2006.201.16:21:30.86#ibcon#enter sib2, iclass 13, count 0 2006.201.16:21:30.86#ibcon#flushed, iclass 13, count 0 2006.201.16:21:30.86#ibcon#about to write, iclass 13, count 0 2006.201.16:21:30.86#ibcon#wrote, iclass 13, count 0 2006.201.16:21:30.86#ibcon#about to read 3, iclass 13, count 0 2006.201.16:21:30.88#ibcon#read 3, iclass 13, count 0 2006.201.16:21:30.88#ibcon#about to read 4, iclass 13, count 0 2006.201.16:21:30.88#ibcon#read 4, iclass 13, count 0 2006.201.16:21:30.88#ibcon#about to read 5, iclass 13, count 0 2006.201.16:21:30.88#ibcon#read 5, iclass 13, count 0 2006.201.16:21:30.88#ibcon#about to read 6, iclass 13, count 0 2006.201.16:21:30.88#ibcon#read 6, iclass 13, count 0 2006.201.16:21:30.88#ibcon#end of sib2, iclass 13, count 0 2006.201.16:21:30.88#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:21:30.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:21:30.88#ibcon#[27=USB\r\n] 2006.201.16:21:30.88#ibcon#*before write, iclass 13, count 0 2006.201.16:21:30.88#ibcon#enter sib2, iclass 13, count 0 2006.201.16:21:30.88#ibcon#flushed, iclass 13, count 0 2006.201.16:21:30.88#ibcon#about to write, iclass 13, count 0 2006.201.16:21:30.88#ibcon#wrote, iclass 13, count 0 2006.201.16:21:30.88#ibcon#about to read 3, iclass 13, count 0 2006.201.16:21:30.91#ibcon#read 3, iclass 13, count 0 2006.201.16:21:30.91#ibcon#about to read 4, iclass 13, count 0 2006.201.16:21:30.91#ibcon#read 4, iclass 13, count 0 2006.201.16:21:30.91#ibcon#about to read 5, iclass 13, count 0 2006.201.16:21:30.91#ibcon#read 5, iclass 13, count 0 2006.201.16:21:30.91#ibcon#about to read 6, iclass 13, count 0 2006.201.16:21:30.91#ibcon#read 6, iclass 13, count 0 2006.201.16:21:30.91#ibcon#end of sib2, iclass 13, count 0 2006.201.16:21:30.91#ibcon#*after write, iclass 13, count 0 2006.201.16:21:30.91#ibcon#*before return 0, iclass 13, count 0 2006.201.16:21:30.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:21:30.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:21:30.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:21:30.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:21:30.91$vck44/vblo=2,634.99 2006.201.16:21:30.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.16:21:30.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.16:21:30.91#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:30.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:30.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:30.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:30.91#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:21:30.91#ibcon#first serial, iclass 15, count 0 2006.201.16:21:30.91#ibcon#enter sib2, iclass 15, count 0 2006.201.16:21:30.91#ibcon#flushed, iclass 15, count 0 2006.201.16:21:30.91#ibcon#about to write, iclass 15, count 0 2006.201.16:21:30.91#ibcon#wrote, iclass 15, count 0 2006.201.16:21:30.91#ibcon#about to read 3, iclass 15, count 0 2006.201.16:21:30.93#ibcon#read 3, iclass 15, count 0 2006.201.16:21:30.93#ibcon#about to read 4, iclass 15, count 0 2006.201.16:21:30.93#ibcon#read 4, iclass 15, count 0 2006.201.16:21:30.93#ibcon#about to read 5, iclass 15, count 0 2006.201.16:21:30.93#ibcon#read 5, iclass 15, count 0 2006.201.16:21:30.93#ibcon#about to read 6, iclass 15, count 0 2006.201.16:21:30.93#ibcon#read 6, iclass 15, count 0 2006.201.16:21:30.93#ibcon#end of sib2, iclass 15, count 0 2006.201.16:21:30.93#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:21:30.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:21:30.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:21:30.93#ibcon#*before write, iclass 15, count 0 2006.201.16:21:30.93#ibcon#enter sib2, iclass 15, count 0 2006.201.16:21:30.93#ibcon#flushed, iclass 15, count 0 2006.201.16:21:30.93#ibcon#about to write, iclass 15, count 0 2006.201.16:21:30.93#ibcon#wrote, iclass 15, count 0 2006.201.16:21:30.93#ibcon#about to read 3, iclass 15, count 0 2006.201.16:21:30.97#ibcon#read 3, iclass 15, count 0 2006.201.16:21:30.97#ibcon#about to read 4, iclass 15, count 0 2006.201.16:21:30.97#ibcon#read 4, iclass 15, count 0 2006.201.16:21:30.97#ibcon#about to read 5, iclass 15, count 0 2006.201.16:21:30.97#ibcon#read 5, iclass 15, count 0 2006.201.16:21:30.97#ibcon#about to read 6, iclass 15, count 0 2006.201.16:21:30.97#ibcon#read 6, iclass 15, count 0 2006.201.16:21:30.97#ibcon#end of sib2, iclass 15, count 0 2006.201.16:21:30.97#ibcon#*after write, iclass 15, count 0 2006.201.16:21:30.97#ibcon#*before return 0, iclass 15, count 0 2006.201.16:21:30.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:30.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:21:30.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:21:30.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:21:30.97$vck44/vb=2,5 2006.201.16:21:30.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.16:21:30.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.16:21:30.97#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:30.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:31.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:31.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:31.03#ibcon#enter wrdev, iclass 17, count 2 2006.201.16:21:31.03#ibcon#first serial, iclass 17, count 2 2006.201.16:21:31.03#ibcon#enter sib2, iclass 17, count 2 2006.201.16:21:31.03#ibcon#flushed, iclass 17, count 2 2006.201.16:21:31.03#ibcon#about to write, iclass 17, count 2 2006.201.16:21:31.03#ibcon#wrote, iclass 17, count 2 2006.201.16:21:31.03#ibcon#about to read 3, iclass 17, count 2 2006.201.16:21:31.05#ibcon#read 3, iclass 17, count 2 2006.201.16:21:31.05#ibcon#about to read 4, iclass 17, count 2 2006.201.16:21:31.05#ibcon#read 4, iclass 17, count 2 2006.201.16:21:31.05#ibcon#about to read 5, iclass 17, count 2 2006.201.16:21:31.05#ibcon#read 5, iclass 17, count 2 2006.201.16:21:31.05#ibcon#about to read 6, iclass 17, count 2 2006.201.16:21:31.05#ibcon#read 6, iclass 17, count 2 2006.201.16:21:31.05#ibcon#end of sib2, iclass 17, count 2 2006.201.16:21:31.05#ibcon#*mode == 0, iclass 17, count 2 2006.201.16:21:31.05#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.16:21:31.05#ibcon#[27=AT02-05\r\n] 2006.201.16:21:31.05#ibcon#*before write, iclass 17, count 2 2006.201.16:21:31.05#ibcon#enter sib2, iclass 17, count 2 2006.201.16:21:31.05#ibcon#flushed, iclass 17, count 2 2006.201.16:21:31.05#ibcon#about to write, iclass 17, count 2 2006.201.16:21:31.05#ibcon#wrote, iclass 17, count 2 2006.201.16:21:31.05#ibcon#about to read 3, iclass 17, count 2 2006.201.16:21:31.08#ibcon#read 3, iclass 17, count 2 2006.201.16:21:31.08#ibcon#about to read 4, iclass 17, count 2 2006.201.16:21:31.08#ibcon#read 4, iclass 17, count 2 2006.201.16:21:31.08#ibcon#about to read 5, iclass 17, count 2 2006.201.16:21:31.08#ibcon#read 5, iclass 17, count 2 2006.201.16:21:31.08#ibcon#about to read 6, iclass 17, count 2 2006.201.16:21:31.08#ibcon#read 6, iclass 17, count 2 2006.201.16:21:31.08#ibcon#end of sib2, iclass 17, count 2 2006.201.16:21:31.08#ibcon#*after write, iclass 17, count 2 2006.201.16:21:31.08#ibcon#*before return 0, iclass 17, count 2 2006.201.16:21:31.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:31.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:21:31.08#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.16:21:31.08#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:31.08#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:31.20#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:31.20#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:31.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:21:31.20#ibcon#first serial, iclass 17, count 0 2006.201.16:21:31.20#ibcon#enter sib2, iclass 17, count 0 2006.201.16:21:31.20#ibcon#flushed, iclass 17, count 0 2006.201.16:21:31.20#ibcon#about to write, iclass 17, count 0 2006.201.16:21:31.20#ibcon#wrote, iclass 17, count 0 2006.201.16:21:31.20#ibcon#about to read 3, iclass 17, count 0 2006.201.16:21:31.22#ibcon#read 3, iclass 17, count 0 2006.201.16:21:31.22#ibcon#about to read 4, iclass 17, count 0 2006.201.16:21:31.22#ibcon#read 4, iclass 17, count 0 2006.201.16:21:31.22#ibcon#about to read 5, iclass 17, count 0 2006.201.16:21:31.22#ibcon#read 5, iclass 17, count 0 2006.201.16:21:31.22#ibcon#about to read 6, iclass 17, count 0 2006.201.16:21:31.22#ibcon#read 6, iclass 17, count 0 2006.201.16:21:31.22#ibcon#end of sib2, iclass 17, count 0 2006.201.16:21:31.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:21:31.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:21:31.22#ibcon#[27=USB\r\n] 2006.201.16:21:31.22#ibcon#*before write, iclass 17, count 0 2006.201.16:21:31.22#ibcon#enter sib2, iclass 17, count 0 2006.201.16:21:31.22#ibcon#flushed, iclass 17, count 0 2006.201.16:21:31.22#ibcon#about to write, iclass 17, count 0 2006.201.16:21:31.22#ibcon#wrote, iclass 17, count 0 2006.201.16:21:31.22#ibcon#about to read 3, iclass 17, count 0 2006.201.16:21:31.25#ibcon#read 3, iclass 17, count 0 2006.201.16:21:31.25#ibcon#about to read 4, iclass 17, count 0 2006.201.16:21:31.25#ibcon#read 4, iclass 17, count 0 2006.201.16:21:31.25#ibcon#about to read 5, iclass 17, count 0 2006.201.16:21:31.25#ibcon#read 5, iclass 17, count 0 2006.201.16:21:31.25#ibcon#about to read 6, iclass 17, count 0 2006.201.16:21:31.25#ibcon#read 6, iclass 17, count 0 2006.201.16:21:31.25#ibcon#end of sib2, iclass 17, count 0 2006.201.16:21:31.25#ibcon#*after write, iclass 17, count 0 2006.201.16:21:31.25#ibcon#*before return 0, iclass 17, count 0 2006.201.16:21:31.25#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:31.25#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:21:31.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:21:31.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:21:31.25$vck44/vblo=3,649.99 2006.201.16:21:31.25#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.16:21:31.25#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.16:21:31.25#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:31.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:31.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:31.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:31.25#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:21:31.25#ibcon#first serial, iclass 19, count 0 2006.201.16:21:31.25#ibcon#enter sib2, iclass 19, count 0 2006.201.16:21:31.25#ibcon#flushed, iclass 19, count 0 2006.201.16:21:31.25#ibcon#about to write, iclass 19, count 0 2006.201.16:21:31.25#ibcon#wrote, iclass 19, count 0 2006.201.16:21:31.25#ibcon#about to read 3, iclass 19, count 0 2006.201.16:21:31.27#ibcon#read 3, iclass 19, count 0 2006.201.16:21:31.27#ibcon#about to read 4, iclass 19, count 0 2006.201.16:21:31.27#ibcon#read 4, iclass 19, count 0 2006.201.16:21:31.27#ibcon#about to read 5, iclass 19, count 0 2006.201.16:21:31.27#ibcon#read 5, iclass 19, count 0 2006.201.16:21:31.27#ibcon#about to read 6, iclass 19, count 0 2006.201.16:21:31.27#ibcon#read 6, iclass 19, count 0 2006.201.16:21:31.27#ibcon#end of sib2, iclass 19, count 0 2006.201.16:21:31.27#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:21:31.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:21:31.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:21:31.27#ibcon#*before write, iclass 19, count 0 2006.201.16:21:31.27#ibcon#enter sib2, iclass 19, count 0 2006.201.16:21:31.27#ibcon#flushed, iclass 19, count 0 2006.201.16:21:31.27#ibcon#about to write, iclass 19, count 0 2006.201.16:21:31.27#ibcon#wrote, iclass 19, count 0 2006.201.16:21:31.27#ibcon#about to read 3, iclass 19, count 0 2006.201.16:21:31.31#ibcon#read 3, iclass 19, count 0 2006.201.16:21:31.31#ibcon#about to read 4, iclass 19, count 0 2006.201.16:21:31.31#ibcon#read 4, iclass 19, count 0 2006.201.16:21:31.31#ibcon#about to read 5, iclass 19, count 0 2006.201.16:21:31.31#ibcon#read 5, iclass 19, count 0 2006.201.16:21:31.31#ibcon#about to read 6, iclass 19, count 0 2006.201.16:21:31.31#ibcon#read 6, iclass 19, count 0 2006.201.16:21:31.31#ibcon#end of sib2, iclass 19, count 0 2006.201.16:21:31.31#ibcon#*after write, iclass 19, count 0 2006.201.16:21:31.31#ibcon#*before return 0, iclass 19, count 0 2006.201.16:21:31.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:31.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:21:31.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:21:31.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:21:31.31$vck44/vb=3,4 2006.201.16:21:31.31#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.16:21:31.31#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.16:21:31.31#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:31.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:31.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:31.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:31.37#ibcon#enter wrdev, iclass 21, count 2 2006.201.16:21:31.37#ibcon#first serial, iclass 21, count 2 2006.201.16:21:31.37#ibcon#enter sib2, iclass 21, count 2 2006.201.16:21:31.37#ibcon#flushed, iclass 21, count 2 2006.201.16:21:31.37#ibcon#about to write, iclass 21, count 2 2006.201.16:21:31.37#ibcon#wrote, iclass 21, count 2 2006.201.16:21:31.37#ibcon#about to read 3, iclass 21, count 2 2006.201.16:21:31.39#ibcon#read 3, iclass 21, count 2 2006.201.16:21:31.39#ibcon#about to read 4, iclass 21, count 2 2006.201.16:21:31.39#ibcon#read 4, iclass 21, count 2 2006.201.16:21:31.39#ibcon#about to read 5, iclass 21, count 2 2006.201.16:21:31.39#ibcon#read 5, iclass 21, count 2 2006.201.16:21:31.39#ibcon#about to read 6, iclass 21, count 2 2006.201.16:21:31.39#ibcon#read 6, iclass 21, count 2 2006.201.16:21:31.39#ibcon#end of sib2, iclass 21, count 2 2006.201.16:21:31.39#ibcon#*mode == 0, iclass 21, count 2 2006.201.16:21:31.39#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.16:21:31.39#ibcon#[27=AT03-04\r\n] 2006.201.16:21:31.39#ibcon#*before write, iclass 21, count 2 2006.201.16:21:31.39#ibcon#enter sib2, iclass 21, count 2 2006.201.16:21:31.39#ibcon#flushed, iclass 21, count 2 2006.201.16:21:31.39#ibcon#about to write, iclass 21, count 2 2006.201.16:21:31.39#ibcon#wrote, iclass 21, count 2 2006.201.16:21:31.39#ibcon#about to read 3, iclass 21, count 2 2006.201.16:21:31.42#ibcon#read 3, iclass 21, count 2 2006.201.16:21:31.42#ibcon#about to read 4, iclass 21, count 2 2006.201.16:21:31.42#ibcon#read 4, iclass 21, count 2 2006.201.16:21:31.42#ibcon#about to read 5, iclass 21, count 2 2006.201.16:21:31.42#ibcon#read 5, iclass 21, count 2 2006.201.16:21:31.42#ibcon#about to read 6, iclass 21, count 2 2006.201.16:21:31.42#ibcon#read 6, iclass 21, count 2 2006.201.16:21:31.42#ibcon#end of sib2, iclass 21, count 2 2006.201.16:21:31.42#ibcon#*after write, iclass 21, count 2 2006.201.16:21:31.42#ibcon#*before return 0, iclass 21, count 2 2006.201.16:21:31.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:31.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:21:31.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.16:21:31.42#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:31.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:31.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:31.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:31.54#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:21:31.54#ibcon#first serial, iclass 21, count 0 2006.201.16:21:31.54#ibcon#enter sib2, iclass 21, count 0 2006.201.16:21:31.54#ibcon#flushed, iclass 21, count 0 2006.201.16:21:31.54#ibcon#about to write, iclass 21, count 0 2006.201.16:21:31.54#ibcon#wrote, iclass 21, count 0 2006.201.16:21:31.54#ibcon#about to read 3, iclass 21, count 0 2006.201.16:21:31.56#ibcon#read 3, iclass 21, count 0 2006.201.16:21:31.56#ibcon#about to read 4, iclass 21, count 0 2006.201.16:21:31.56#ibcon#read 4, iclass 21, count 0 2006.201.16:21:31.56#ibcon#about to read 5, iclass 21, count 0 2006.201.16:21:31.56#ibcon#read 5, iclass 21, count 0 2006.201.16:21:31.56#ibcon#about to read 6, iclass 21, count 0 2006.201.16:21:31.56#ibcon#read 6, iclass 21, count 0 2006.201.16:21:31.56#ibcon#end of sib2, iclass 21, count 0 2006.201.16:21:31.56#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:21:31.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:21:31.56#ibcon#[27=USB\r\n] 2006.201.16:21:31.56#ibcon#*before write, iclass 21, count 0 2006.201.16:21:31.56#ibcon#enter sib2, iclass 21, count 0 2006.201.16:21:31.56#ibcon#flushed, iclass 21, count 0 2006.201.16:21:31.56#ibcon#about to write, iclass 21, count 0 2006.201.16:21:31.56#ibcon#wrote, iclass 21, count 0 2006.201.16:21:31.56#ibcon#about to read 3, iclass 21, count 0 2006.201.16:21:31.59#ibcon#read 3, iclass 21, count 0 2006.201.16:21:31.59#ibcon#about to read 4, iclass 21, count 0 2006.201.16:21:31.59#ibcon#read 4, iclass 21, count 0 2006.201.16:21:31.59#ibcon#about to read 5, iclass 21, count 0 2006.201.16:21:31.59#ibcon#read 5, iclass 21, count 0 2006.201.16:21:31.59#ibcon#about to read 6, iclass 21, count 0 2006.201.16:21:31.59#ibcon#read 6, iclass 21, count 0 2006.201.16:21:31.59#ibcon#end of sib2, iclass 21, count 0 2006.201.16:21:31.59#ibcon#*after write, iclass 21, count 0 2006.201.16:21:31.59#ibcon#*before return 0, iclass 21, count 0 2006.201.16:21:31.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:31.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:21:31.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:21:31.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:21:31.59$vck44/vblo=4,679.99 2006.201.16:21:31.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.16:21:31.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.16:21:31.59#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:31.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:31.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:31.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:31.59#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:21:31.59#ibcon#first serial, iclass 23, count 0 2006.201.16:21:31.59#ibcon#enter sib2, iclass 23, count 0 2006.201.16:21:31.59#ibcon#flushed, iclass 23, count 0 2006.201.16:21:31.59#ibcon#about to write, iclass 23, count 0 2006.201.16:21:31.59#ibcon#wrote, iclass 23, count 0 2006.201.16:21:31.59#ibcon#about to read 3, iclass 23, count 0 2006.201.16:21:31.61#ibcon#read 3, iclass 23, count 0 2006.201.16:21:31.61#ibcon#about to read 4, iclass 23, count 0 2006.201.16:21:31.61#ibcon#read 4, iclass 23, count 0 2006.201.16:21:31.61#ibcon#about to read 5, iclass 23, count 0 2006.201.16:21:31.61#ibcon#read 5, iclass 23, count 0 2006.201.16:21:31.61#ibcon#about to read 6, iclass 23, count 0 2006.201.16:21:31.61#ibcon#read 6, iclass 23, count 0 2006.201.16:21:31.61#ibcon#end of sib2, iclass 23, count 0 2006.201.16:21:31.61#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:21:31.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:21:31.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:21:31.61#ibcon#*before write, iclass 23, count 0 2006.201.16:21:31.61#ibcon#enter sib2, iclass 23, count 0 2006.201.16:21:31.61#ibcon#flushed, iclass 23, count 0 2006.201.16:21:31.61#ibcon#about to write, iclass 23, count 0 2006.201.16:21:31.61#ibcon#wrote, iclass 23, count 0 2006.201.16:21:31.61#ibcon#about to read 3, iclass 23, count 0 2006.201.16:21:31.66#ibcon#read 3, iclass 23, count 0 2006.201.16:21:31.66#ibcon#about to read 4, iclass 23, count 0 2006.201.16:21:31.66#ibcon#read 4, iclass 23, count 0 2006.201.16:21:31.66#ibcon#about to read 5, iclass 23, count 0 2006.201.16:21:31.66#ibcon#read 5, iclass 23, count 0 2006.201.16:21:31.66#ibcon#about to read 6, iclass 23, count 0 2006.201.16:21:31.66#ibcon#read 6, iclass 23, count 0 2006.201.16:21:31.66#ibcon#end of sib2, iclass 23, count 0 2006.201.16:21:31.66#ibcon#*after write, iclass 23, count 0 2006.201.16:21:31.66#ibcon#*before return 0, iclass 23, count 0 2006.201.16:21:31.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:31.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:21:31.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:21:31.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:21:31.66$vck44/vb=4,5 2006.201.16:21:31.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.16:21:31.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.16:21:31.66#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:31.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:31.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:31.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:31.71#ibcon#enter wrdev, iclass 25, count 2 2006.201.16:21:31.71#ibcon#first serial, iclass 25, count 2 2006.201.16:21:31.71#ibcon#enter sib2, iclass 25, count 2 2006.201.16:21:31.71#ibcon#flushed, iclass 25, count 2 2006.201.16:21:31.71#ibcon#about to write, iclass 25, count 2 2006.201.16:21:31.71#ibcon#wrote, iclass 25, count 2 2006.201.16:21:31.71#ibcon#about to read 3, iclass 25, count 2 2006.201.16:21:31.73#ibcon#read 3, iclass 25, count 2 2006.201.16:21:31.73#ibcon#about to read 4, iclass 25, count 2 2006.201.16:21:31.73#ibcon#read 4, iclass 25, count 2 2006.201.16:21:31.73#ibcon#about to read 5, iclass 25, count 2 2006.201.16:21:31.73#ibcon#read 5, iclass 25, count 2 2006.201.16:21:31.73#ibcon#about to read 6, iclass 25, count 2 2006.201.16:21:31.73#ibcon#read 6, iclass 25, count 2 2006.201.16:21:31.73#ibcon#end of sib2, iclass 25, count 2 2006.201.16:21:31.73#ibcon#*mode == 0, iclass 25, count 2 2006.201.16:21:31.73#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.16:21:31.73#ibcon#[27=AT04-05\r\n] 2006.201.16:21:31.73#ibcon#*before write, iclass 25, count 2 2006.201.16:21:31.73#ibcon#enter sib2, iclass 25, count 2 2006.201.16:21:31.73#ibcon#flushed, iclass 25, count 2 2006.201.16:21:31.73#ibcon#about to write, iclass 25, count 2 2006.201.16:21:31.73#ibcon#wrote, iclass 25, count 2 2006.201.16:21:31.73#ibcon#about to read 3, iclass 25, count 2 2006.201.16:21:31.76#ibcon#read 3, iclass 25, count 2 2006.201.16:21:31.76#ibcon#about to read 4, iclass 25, count 2 2006.201.16:21:31.76#ibcon#read 4, iclass 25, count 2 2006.201.16:21:31.76#ibcon#about to read 5, iclass 25, count 2 2006.201.16:21:31.76#ibcon#read 5, iclass 25, count 2 2006.201.16:21:31.76#ibcon#about to read 6, iclass 25, count 2 2006.201.16:21:31.76#ibcon#read 6, iclass 25, count 2 2006.201.16:21:31.76#ibcon#end of sib2, iclass 25, count 2 2006.201.16:21:31.76#ibcon#*after write, iclass 25, count 2 2006.201.16:21:31.76#ibcon#*before return 0, iclass 25, count 2 2006.201.16:21:31.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:31.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:21:31.76#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.16:21:31.76#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:31.76#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:31.88#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:31.88#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:31.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:21:31.88#ibcon#first serial, iclass 25, count 0 2006.201.16:21:31.88#ibcon#enter sib2, iclass 25, count 0 2006.201.16:21:31.88#ibcon#flushed, iclass 25, count 0 2006.201.16:21:31.88#ibcon#about to write, iclass 25, count 0 2006.201.16:21:31.88#ibcon#wrote, iclass 25, count 0 2006.201.16:21:31.88#ibcon#about to read 3, iclass 25, count 0 2006.201.16:21:31.90#ibcon#read 3, iclass 25, count 0 2006.201.16:21:31.90#ibcon#about to read 4, iclass 25, count 0 2006.201.16:21:31.90#ibcon#read 4, iclass 25, count 0 2006.201.16:21:31.90#ibcon#about to read 5, iclass 25, count 0 2006.201.16:21:31.90#ibcon#read 5, iclass 25, count 0 2006.201.16:21:31.90#ibcon#about to read 6, iclass 25, count 0 2006.201.16:21:31.90#ibcon#read 6, iclass 25, count 0 2006.201.16:21:31.90#ibcon#end of sib2, iclass 25, count 0 2006.201.16:21:31.90#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:21:31.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:21:31.90#ibcon#[27=USB\r\n] 2006.201.16:21:31.90#ibcon#*before write, iclass 25, count 0 2006.201.16:21:31.90#ibcon#enter sib2, iclass 25, count 0 2006.201.16:21:31.90#ibcon#flushed, iclass 25, count 0 2006.201.16:21:31.90#ibcon#about to write, iclass 25, count 0 2006.201.16:21:31.90#ibcon#wrote, iclass 25, count 0 2006.201.16:21:31.90#ibcon#about to read 3, iclass 25, count 0 2006.201.16:21:31.93#ibcon#read 3, iclass 25, count 0 2006.201.16:21:31.93#ibcon#about to read 4, iclass 25, count 0 2006.201.16:21:31.93#ibcon#read 4, iclass 25, count 0 2006.201.16:21:31.93#ibcon#about to read 5, iclass 25, count 0 2006.201.16:21:31.93#ibcon#read 5, iclass 25, count 0 2006.201.16:21:31.93#ibcon#about to read 6, iclass 25, count 0 2006.201.16:21:31.93#ibcon#read 6, iclass 25, count 0 2006.201.16:21:31.93#ibcon#end of sib2, iclass 25, count 0 2006.201.16:21:31.93#ibcon#*after write, iclass 25, count 0 2006.201.16:21:31.93#ibcon#*before return 0, iclass 25, count 0 2006.201.16:21:31.93#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:31.93#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:21:31.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:21:31.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:21:31.93$vck44/vblo=5,709.99 2006.201.16:21:31.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.16:21:31.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.16:21:31.93#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:31.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:31.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:31.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:31.93#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:21:31.93#ibcon#first serial, iclass 27, count 0 2006.201.16:21:31.93#ibcon#enter sib2, iclass 27, count 0 2006.201.16:21:31.93#ibcon#flushed, iclass 27, count 0 2006.201.16:21:31.93#ibcon#about to write, iclass 27, count 0 2006.201.16:21:31.93#ibcon#wrote, iclass 27, count 0 2006.201.16:21:31.93#ibcon#about to read 3, iclass 27, count 0 2006.201.16:21:31.95#ibcon#read 3, iclass 27, count 0 2006.201.16:21:31.95#ibcon#about to read 4, iclass 27, count 0 2006.201.16:21:31.95#ibcon#read 4, iclass 27, count 0 2006.201.16:21:31.95#ibcon#about to read 5, iclass 27, count 0 2006.201.16:21:31.95#ibcon#read 5, iclass 27, count 0 2006.201.16:21:31.95#ibcon#about to read 6, iclass 27, count 0 2006.201.16:21:31.95#ibcon#read 6, iclass 27, count 0 2006.201.16:21:31.95#ibcon#end of sib2, iclass 27, count 0 2006.201.16:21:31.95#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:21:31.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:21:31.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:21:31.95#ibcon#*before write, iclass 27, count 0 2006.201.16:21:31.95#ibcon#enter sib2, iclass 27, count 0 2006.201.16:21:31.95#ibcon#flushed, iclass 27, count 0 2006.201.16:21:31.95#ibcon#about to write, iclass 27, count 0 2006.201.16:21:31.95#ibcon#wrote, iclass 27, count 0 2006.201.16:21:31.95#ibcon#about to read 3, iclass 27, count 0 2006.201.16:21:31.99#ibcon#read 3, iclass 27, count 0 2006.201.16:21:31.99#ibcon#about to read 4, iclass 27, count 0 2006.201.16:21:31.99#ibcon#read 4, iclass 27, count 0 2006.201.16:21:31.99#ibcon#about to read 5, iclass 27, count 0 2006.201.16:21:31.99#ibcon#read 5, iclass 27, count 0 2006.201.16:21:31.99#ibcon#about to read 6, iclass 27, count 0 2006.201.16:21:31.99#ibcon#read 6, iclass 27, count 0 2006.201.16:21:31.99#ibcon#end of sib2, iclass 27, count 0 2006.201.16:21:31.99#ibcon#*after write, iclass 27, count 0 2006.201.16:21:31.99#ibcon#*before return 0, iclass 27, count 0 2006.201.16:21:31.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:31.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:21:31.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:21:31.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:21:31.99$vck44/vb=5,4 2006.201.16:21:31.99#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.16:21:31.99#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.16:21:31.99#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:31.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:32.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:32.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:32.05#ibcon#enter wrdev, iclass 29, count 2 2006.201.16:21:32.05#ibcon#first serial, iclass 29, count 2 2006.201.16:21:32.05#ibcon#enter sib2, iclass 29, count 2 2006.201.16:21:32.05#ibcon#flushed, iclass 29, count 2 2006.201.16:21:32.05#ibcon#about to write, iclass 29, count 2 2006.201.16:21:32.05#ibcon#wrote, iclass 29, count 2 2006.201.16:21:32.05#ibcon#about to read 3, iclass 29, count 2 2006.201.16:21:32.07#ibcon#read 3, iclass 29, count 2 2006.201.16:21:32.07#ibcon#about to read 4, iclass 29, count 2 2006.201.16:21:32.07#ibcon#read 4, iclass 29, count 2 2006.201.16:21:32.07#ibcon#about to read 5, iclass 29, count 2 2006.201.16:21:32.07#ibcon#read 5, iclass 29, count 2 2006.201.16:21:32.07#ibcon#about to read 6, iclass 29, count 2 2006.201.16:21:32.07#ibcon#read 6, iclass 29, count 2 2006.201.16:21:32.07#ibcon#end of sib2, iclass 29, count 2 2006.201.16:21:32.07#ibcon#*mode == 0, iclass 29, count 2 2006.201.16:21:32.07#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.16:21:32.07#ibcon#[27=AT05-04\r\n] 2006.201.16:21:32.07#ibcon#*before write, iclass 29, count 2 2006.201.16:21:32.07#ibcon#enter sib2, iclass 29, count 2 2006.201.16:21:32.07#ibcon#flushed, iclass 29, count 2 2006.201.16:21:32.07#ibcon#about to write, iclass 29, count 2 2006.201.16:21:32.07#ibcon#wrote, iclass 29, count 2 2006.201.16:21:32.07#ibcon#about to read 3, iclass 29, count 2 2006.201.16:21:32.10#ibcon#read 3, iclass 29, count 2 2006.201.16:21:32.10#ibcon#about to read 4, iclass 29, count 2 2006.201.16:21:32.10#ibcon#read 4, iclass 29, count 2 2006.201.16:21:32.10#ibcon#about to read 5, iclass 29, count 2 2006.201.16:21:32.10#ibcon#read 5, iclass 29, count 2 2006.201.16:21:32.10#ibcon#about to read 6, iclass 29, count 2 2006.201.16:21:32.10#ibcon#read 6, iclass 29, count 2 2006.201.16:21:32.10#ibcon#end of sib2, iclass 29, count 2 2006.201.16:21:32.10#ibcon#*after write, iclass 29, count 2 2006.201.16:21:32.10#ibcon#*before return 0, iclass 29, count 2 2006.201.16:21:32.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:32.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:21:32.10#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.16:21:32.10#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:32.10#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:32.22#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:32.22#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:32.22#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:21:32.22#ibcon#first serial, iclass 29, count 0 2006.201.16:21:32.22#ibcon#enter sib2, iclass 29, count 0 2006.201.16:21:32.22#ibcon#flushed, iclass 29, count 0 2006.201.16:21:32.22#ibcon#about to write, iclass 29, count 0 2006.201.16:21:32.22#ibcon#wrote, iclass 29, count 0 2006.201.16:21:32.22#ibcon#about to read 3, iclass 29, count 0 2006.201.16:21:32.24#ibcon#read 3, iclass 29, count 0 2006.201.16:21:32.24#ibcon#about to read 4, iclass 29, count 0 2006.201.16:21:32.24#ibcon#read 4, iclass 29, count 0 2006.201.16:21:32.24#ibcon#about to read 5, iclass 29, count 0 2006.201.16:21:32.24#ibcon#read 5, iclass 29, count 0 2006.201.16:21:32.24#ibcon#about to read 6, iclass 29, count 0 2006.201.16:21:32.24#ibcon#read 6, iclass 29, count 0 2006.201.16:21:32.24#ibcon#end of sib2, iclass 29, count 0 2006.201.16:21:32.24#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:21:32.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:21:32.24#ibcon#[27=USB\r\n] 2006.201.16:21:32.24#ibcon#*before write, iclass 29, count 0 2006.201.16:21:32.24#ibcon#enter sib2, iclass 29, count 0 2006.201.16:21:32.24#ibcon#flushed, iclass 29, count 0 2006.201.16:21:32.24#ibcon#about to write, iclass 29, count 0 2006.201.16:21:32.24#ibcon#wrote, iclass 29, count 0 2006.201.16:21:32.24#ibcon#about to read 3, iclass 29, count 0 2006.201.16:21:32.27#ibcon#read 3, iclass 29, count 0 2006.201.16:21:32.27#ibcon#about to read 4, iclass 29, count 0 2006.201.16:21:32.27#ibcon#read 4, iclass 29, count 0 2006.201.16:21:32.27#ibcon#about to read 5, iclass 29, count 0 2006.201.16:21:32.27#ibcon#read 5, iclass 29, count 0 2006.201.16:21:32.27#ibcon#about to read 6, iclass 29, count 0 2006.201.16:21:32.27#ibcon#read 6, iclass 29, count 0 2006.201.16:21:32.27#ibcon#end of sib2, iclass 29, count 0 2006.201.16:21:32.27#ibcon#*after write, iclass 29, count 0 2006.201.16:21:32.27#ibcon#*before return 0, iclass 29, count 0 2006.201.16:21:32.27#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:32.27#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:21:32.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:21:32.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:21:32.27$vck44/vblo=6,719.99 2006.201.16:21:32.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.16:21:32.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.16:21:32.27#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:32.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:32.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:32.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:32.27#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:21:32.27#ibcon#first serial, iclass 31, count 0 2006.201.16:21:32.27#ibcon#enter sib2, iclass 31, count 0 2006.201.16:21:32.27#ibcon#flushed, iclass 31, count 0 2006.201.16:21:32.27#ibcon#about to write, iclass 31, count 0 2006.201.16:21:32.27#ibcon#wrote, iclass 31, count 0 2006.201.16:21:32.27#ibcon#about to read 3, iclass 31, count 0 2006.201.16:21:32.29#ibcon#read 3, iclass 31, count 0 2006.201.16:21:32.29#ibcon#about to read 4, iclass 31, count 0 2006.201.16:21:32.29#ibcon#read 4, iclass 31, count 0 2006.201.16:21:32.29#ibcon#about to read 5, iclass 31, count 0 2006.201.16:21:32.29#ibcon#read 5, iclass 31, count 0 2006.201.16:21:32.29#ibcon#about to read 6, iclass 31, count 0 2006.201.16:21:32.29#ibcon#read 6, iclass 31, count 0 2006.201.16:21:32.29#ibcon#end of sib2, iclass 31, count 0 2006.201.16:21:32.29#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:21:32.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:21:32.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:21:32.29#ibcon#*before write, iclass 31, count 0 2006.201.16:21:32.29#ibcon#enter sib2, iclass 31, count 0 2006.201.16:21:32.29#ibcon#flushed, iclass 31, count 0 2006.201.16:21:32.29#ibcon#about to write, iclass 31, count 0 2006.201.16:21:32.29#ibcon#wrote, iclass 31, count 0 2006.201.16:21:32.29#ibcon#about to read 3, iclass 31, count 0 2006.201.16:21:32.33#ibcon#read 3, iclass 31, count 0 2006.201.16:21:32.33#ibcon#about to read 4, iclass 31, count 0 2006.201.16:21:32.33#ibcon#read 4, iclass 31, count 0 2006.201.16:21:32.33#ibcon#about to read 5, iclass 31, count 0 2006.201.16:21:32.33#ibcon#read 5, iclass 31, count 0 2006.201.16:21:32.33#ibcon#about to read 6, iclass 31, count 0 2006.201.16:21:32.33#ibcon#read 6, iclass 31, count 0 2006.201.16:21:32.33#ibcon#end of sib2, iclass 31, count 0 2006.201.16:21:32.33#ibcon#*after write, iclass 31, count 0 2006.201.16:21:32.33#ibcon#*before return 0, iclass 31, count 0 2006.201.16:21:32.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:32.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:21:32.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:21:32.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:21:32.33$vck44/vb=6,4 2006.201.16:21:32.33#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.16:21:32.33#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.16:21:32.33#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:32.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:32.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:32.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:32.39#ibcon#enter wrdev, iclass 33, count 2 2006.201.16:21:32.39#ibcon#first serial, iclass 33, count 2 2006.201.16:21:32.39#ibcon#enter sib2, iclass 33, count 2 2006.201.16:21:32.39#ibcon#flushed, iclass 33, count 2 2006.201.16:21:32.39#ibcon#about to write, iclass 33, count 2 2006.201.16:21:32.39#ibcon#wrote, iclass 33, count 2 2006.201.16:21:32.39#ibcon#about to read 3, iclass 33, count 2 2006.201.16:21:32.41#ibcon#read 3, iclass 33, count 2 2006.201.16:21:32.41#ibcon#about to read 4, iclass 33, count 2 2006.201.16:21:32.41#ibcon#read 4, iclass 33, count 2 2006.201.16:21:32.41#ibcon#about to read 5, iclass 33, count 2 2006.201.16:21:32.41#ibcon#read 5, iclass 33, count 2 2006.201.16:21:32.41#ibcon#about to read 6, iclass 33, count 2 2006.201.16:21:32.41#ibcon#read 6, iclass 33, count 2 2006.201.16:21:32.41#ibcon#end of sib2, iclass 33, count 2 2006.201.16:21:32.41#ibcon#*mode == 0, iclass 33, count 2 2006.201.16:21:32.41#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.16:21:32.41#ibcon#[27=AT06-04\r\n] 2006.201.16:21:32.41#ibcon#*before write, iclass 33, count 2 2006.201.16:21:32.41#ibcon#enter sib2, iclass 33, count 2 2006.201.16:21:32.41#ibcon#flushed, iclass 33, count 2 2006.201.16:21:32.41#ibcon#about to write, iclass 33, count 2 2006.201.16:21:32.41#ibcon#wrote, iclass 33, count 2 2006.201.16:21:32.41#ibcon#about to read 3, iclass 33, count 2 2006.201.16:21:32.44#ibcon#read 3, iclass 33, count 2 2006.201.16:21:32.44#ibcon#about to read 4, iclass 33, count 2 2006.201.16:21:32.44#ibcon#read 4, iclass 33, count 2 2006.201.16:21:32.44#ibcon#about to read 5, iclass 33, count 2 2006.201.16:21:32.44#ibcon#read 5, iclass 33, count 2 2006.201.16:21:32.44#ibcon#about to read 6, iclass 33, count 2 2006.201.16:21:32.44#ibcon#read 6, iclass 33, count 2 2006.201.16:21:32.44#ibcon#end of sib2, iclass 33, count 2 2006.201.16:21:32.44#ibcon#*after write, iclass 33, count 2 2006.201.16:21:32.44#ibcon#*before return 0, iclass 33, count 2 2006.201.16:21:32.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:32.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:21:32.44#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.16:21:32.44#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:32.44#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:32.56#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:32.56#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:32.56#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:21:32.56#ibcon#first serial, iclass 33, count 0 2006.201.16:21:32.56#ibcon#enter sib2, iclass 33, count 0 2006.201.16:21:32.56#ibcon#flushed, iclass 33, count 0 2006.201.16:21:32.56#ibcon#about to write, iclass 33, count 0 2006.201.16:21:32.56#ibcon#wrote, iclass 33, count 0 2006.201.16:21:32.56#ibcon#about to read 3, iclass 33, count 0 2006.201.16:21:32.58#ibcon#read 3, iclass 33, count 0 2006.201.16:21:32.58#ibcon#about to read 4, iclass 33, count 0 2006.201.16:21:32.58#ibcon#read 4, iclass 33, count 0 2006.201.16:21:32.58#ibcon#about to read 5, iclass 33, count 0 2006.201.16:21:32.58#ibcon#read 5, iclass 33, count 0 2006.201.16:21:32.58#ibcon#about to read 6, iclass 33, count 0 2006.201.16:21:32.58#ibcon#read 6, iclass 33, count 0 2006.201.16:21:32.58#ibcon#end of sib2, iclass 33, count 0 2006.201.16:21:32.58#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:21:32.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:21:32.58#ibcon#[27=USB\r\n] 2006.201.16:21:32.58#ibcon#*before write, iclass 33, count 0 2006.201.16:21:32.58#ibcon#enter sib2, iclass 33, count 0 2006.201.16:21:32.58#ibcon#flushed, iclass 33, count 0 2006.201.16:21:32.58#ibcon#about to write, iclass 33, count 0 2006.201.16:21:32.58#ibcon#wrote, iclass 33, count 0 2006.201.16:21:32.58#ibcon#about to read 3, iclass 33, count 0 2006.201.16:21:32.61#ibcon#read 3, iclass 33, count 0 2006.201.16:21:32.61#ibcon#about to read 4, iclass 33, count 0 2006.201.16:21:32.61#ibcon#read 4, iclass 33, count 0 2006.201.16:21:32.61#ibcon#about to read 5, iclass 33, count 0 2006.201.16:21:32.61#ibcon#read 5, iclass 33, count 0 2006.201.16:21:32.61#ibcon#about to read 6, iclass 33, count 0 2006.201.16:21:32.61#ibcon#read 6, iclass 33, count 0 2006.201.16:21:32.61#ibcon#end of sib2, iclass 33, count 0 2006.201.16:21:32.61#ibcon#*after write, iclass 33, count 0 2006.201.16:21:32.61#ibcon#*before return 0, iclass 33, count 0 2006.201.16:21:32.61#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:32.61#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:21:32.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:21:32.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:21:32.61$vck44/vblo=7,734.99 2006.201.16:21:32.61#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.16:21:32.61#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.16:21:32.61#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:32.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:32.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:32.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:32.61#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:21:32.61#ibcon#first serial, iclass 35, count 0 2006.201.16:21:32.61#ibcon#enter sib2, iclass 35, count 0 2006.201.16:21:32.61#ibcon#flushed, iclass 35, count 0 2006.201.16:21:32.61#ibcon#about to write, iclass 35, count 0 2006.201.16:21:32.61#ibcon#wrote, iclass 35, count 0 2006.201.16:21:32.61#ibcon#about to read 3, iclass 35, count 0 2006.201.16:21:32.63#ibcon#read 3, iclass 35, count 0 2006.201.16:21:32.63#ibcon#about to read 4, iclass 35, count 0 2006.201.16:21:32.63#ibcon#read 4, iclass 35, count 0 2006.201.16:21:32.63#ibcon#about to read 5, iclass 35, count 0 2006.201.16:21:32.63#ibcon#read 5, iclass 35, count 0 2006.201.16:21:32.63#ibcon#about to read 6, iclass 35, count 0 2006.201.16:21:32.63#ibcon#read 6, iclass 35, count 0 2006.201.16:21:32.63#ibcon#end of sib2, iclass 35, count 0 2006.201.16:21:32.63#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:21:32.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:21:32.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:21:32.63#ibcon#*before write, iclass 35, count 0 2006.201.16:21:32.63#ibcon#enter sib2, iclass 35, count 0 2006.201.16:21:32.63#ibcon#flushed, iclass 35, count 0 2006.201.16:21:32.63#ibcon#about to write, iclass 35, count 0 2006.201.16:21:32.63#ibcon#wrote, iclass 35, count 0 2006.201.16:21:32.63#ibcon#about to read 3, iclass 35, count 0 2006.201.16:21:32.68#ibcon#read 3, iclass 35, count 0 2006.201.16:21:32.68#ibcon#about to read 4, iclass 35, count 0 2006.201.16:21:32.68#ibcon#read 4, iclass 35, count 0 2006.201.16:21:32.68#ibcon#about to read 5, iclass 35, count 0 2006.201.16:21:32.68#ibcon#read 5, iclass 35, count 0 2006.201.16:21:32.68#ibcon#about to read 6, iclass 35, count 0 2006.201.16:21:32.68#ibcon#read 6, iclass 35, count 0 2006.201.16:21:32.68#ibcon#end of sib2, iclass 35, count 0 2006.201.16:21:32.68#ibcon#*after write, iclass 35, count 0 2006.201.16:21:32.68#ibcon#*before return 0, iclass 35, count 0 2006.201.16:21:32.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:32.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:21:32.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:21:32.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:21:32.68$vck44/vb=7,4 2006.201.16:21:32.68#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.16:21:32.68#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.16:21:32.68#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:32.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:32.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:32.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:32.73#ibcon#enter wrdev, iclass 37, count 2 2006.201.16:21:32.73#ibcon#first serial, iclass 37, count 2 2006.201.16:21:32.73#ibcon#enter sib2, iclass 37, count 2 2006.201.16:21:32.73#ibcon#flushed, iclass 37, count 2 2006.201.16:21:32.73#ibcon#about to write, iclass 37, count 2 2006.201.16:21:32.73#ibcon#wrote, iclass 37, count 2 2006.201.16:21:32.73#ibcon#about to read 3, iclass 37, count 2 2006.201.16:21:32.75#ibcon#read 3, iclass 37, count 2 2006.201.16:21:32.75#ibcon#about to read 4, iclass 37, count 2 2006.201.16:21:32.75#ibcon#read 4, iclass 37, count 2 2006.201.16:21:32.75#ibcon#about to read 5, iclass 37, count 2 2006.201.16:21:32.75#ibcon#read 5, iclass 37, count 2 2006.201.16:21:32.75#ibcon#about to read 6, iclass 37, count 2 2006.201.16:21:32.75#ibcon#read 6, iclass 37, count 2 2006.201.16:21:32.75#ibcon#end of sib2, iclass 37, count 2 2006.201.16:21:32.75#ibcon#*mode == 0, iclass 37, count 2 2006.201.16:21:32.75#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.16:21:32.75#ibcon#[27=AT07-04\r\n] 2006.201.16:21:32.75#ibcon#*before write, iclass 37, count 2 2006.201.16:21:32.75#ibcon#enter sib2, iclass 37, count 2 2006.201.16:21:32.75#ibcon#flushed, iclass 37, count 2 2006.201.16:21:32.75#ibcon#about to write, iclass 37, count 2 2006.201.16:21:32.75#ibcon#wrote, iclass 37, count 2 2006.201.16:21:32.75#ibcon#about to read 3, iclass 37, count 2 2006.201.16:21:32.78#ibcon#read 3, iclass 37, count 2 2006.201.16:21:32.78#ibcon#about to read 4, iclass 37, count 2 2006.201.16:21:32.78#ibcon#read 4, iclass 37, count 2 2006.201.16:21:32.78#ibcon#about to read 5, iclass 37, count 2 2006.201.16:21:32.78#ibcon#read 5, iclass 37, count 2 2006.201.16:21:32.78#ibcon#about to read 6, iclass 37, count 2 2006.201.16:21:32.78#ibcon#read 6, iclass 37, count 2 2006.201.16:21:32.78#ibcon#end of sib2, iclass 37, count 2 2006.201.16:21:32.78#ibcon#*after write, iclass 37, count 2 2006.201.16:21:32.78#ibcon#*before return 0, iclass 37, count 2 2006.201.16:21:32.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:32.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:21:32.78#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.16:21:32.78#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:32.78#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:32.90#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:32.90#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:32.90#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:21:32.90#ibcon#first serial, iclass 37, count 0 2006.201.16:21:32.90#ibcon#enter sib2, iclass 37, count 0 2006.201.16:21:32.90#ibcon#flushed, iclass 37, count 0 2006.201.16:21:32.90#ibcon#about to write, iclass 37, count 0 2006.201.16:21:32.90#ibcon#wrote, iclass 37, count 0 2006.201.16:21:32.90#ibcon#about to read 3, iclass 37, count 0 2006.201.16:21:32.92#ibcon#read 3, iclass 37, count 0 2006.201.16:21:32.92#ibcon#about to read 4, iclass 37, count 0 2006.201.16:21:32.92#ibcon#read 4, iclass 37, count 0 2006.201.16:21:32.92#ibcon#about to read 5, iclass 37, count 0 2006.201.16:21:32.92#ibcon#read 5, iclass 37, count 0 2006.201.16:21:32.92#ibcon#about to read 6, iclass 37, count 0 2006.201.16:21:32.92#ibcon#read 6, iclass 37, count 0 2006.201.16:21:32.92#ibcon#end of sib2, iclass 37, count 0 2006.201.16:21:32.92#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:21:32.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:21:32.92#ibcon#[27=USB\r\n] 2006.201.16:21:32.92#ibcon#*before write, iclass 37, count 0 2006.201.16:21:32.92#ibcon#enter sib2, iclass 37, count 0 2006.201.16:21:32.92#ibcon#flushed, iclass 37, count 0 2006.201.16:21:32.92#ibcon#about to write, iclass 37, count 0 2006.201.16:21:32.92#ibcon#wrote, iclass 37, count 0 2006.201.16:21:32.92#ibcon#about to read 3, iclass 37, count 0 2006.201.16:21:32.95#ibcon#read 3, iclass 37, count 0 2006.201.16:21:32.95#ibcon#about to read 4, iclass 37, count 0 2006.201.16:21:32.95#ibcon#read 4, iclass 37, count 0 2006.201.16:21:32.95#ibcon#about to read 5, iclass 37, count 0 2006.201.16:21:32.95#ibcon#read 5, iclass 37, count 0 2006.201.16:21:32.95#ibcon#about to read 6, iclass 37, count 0 2006.201.16:21:32.95#ibcon#read 6, iclass 37, count 0 2006.201.16:21:32.95#ibcon#end of sib2, iclass 37, count 0 2006.201.16:21:32.95#ibcon#*after write, iclass 37, count 0 2006.201.16:21:32.95#ibcon#*before return 0, iclass 37, count 0 2006.201.16:21:32.95#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:32.95#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:21:32.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:21:32.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:21:32.95$vck44/vblo=8,744.99 2006.201.16:21:32.95#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.16:21:32.95#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.16:21:32.95#ibcon#ireg 17 cls_cnt 0 2006.201.16:21:32.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:32.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:32.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:32.95#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:21:32.95#ibcon#first serial, iclass 39, count 0 2006.201.16:21:32.95#ibcon#enter sib2, iclass 39, count 0 2006.201.16:21:32.95#ibcon#flushed, iclass 39, count 0 2006.201.16:21:32.95#ibcon#about to write, iclass 39, count 0 2006.201.16:21:32.95#ibcon#wrote, iclass 39, count 0 2006.201.16:21:32.95#ibcon#about to read 3, iclass 39, count 0 2006.201.16:21:32.97#ibcon#read 3, iclass 39, count 0 2006.201.16:21:32.97#ibcon#about to read 4, iclass 39, count 0 2006.201.16:21:32.97#ibcon#read 4, iclass 39, count 0 2006.201.16:21:32.97#ibcon#about to read 5, iclass 39, count 0 2006.201.16:21:32.97#ibcon#read 5, iclass 39, count 0 2006.201.16:21:32.97#ibcon#about to read 6, iclass 39, count 0 2006.201.16:21:32.97#ibcon#read 6, iclass 39, count 0 2006.201.16:21:32.97#ibcon#end of sib2, iclass 39, count 0 2006.201.16:21:32.97#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:21:32.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:21:32.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:21:32.97#ibcon#*before write, iclass 39, count 0 2006.201.16:21:32.97#ibcon#enter sib2, iclass 39, count 0 2006.201.16:21:32.97#ibcon#flushed, iclass 39, count 0 2006.201.16:21:32.97#ibcon#about to write, iclass 39, count 0 2006.201.16:21:32.97#ibcon#wrote, iclass 39, count 0 2006.201.16:21:32.97#ibcon#about to read 3, iclass 39, count 0 2006.201.16:21:33.01#ibcon#read 3, iclass 39, count 0 2006.201.16:21:33.01#ibcon#about to read 4, iclass 39, count 0 2006.201.16:21:33.01#ibcon#read 4, iclass 39, count 0 2006.201.16:21:33.01#ibcon#about to read 5, iclass 39, count 0 2006.201.16:21:33.01#ibcon#read 5, iclass 39, count 0 2006.201.16:21:33.01#ibcon#about to read 6, iclass 39, count 0 2006.201.16:21:33.01#ibcon#read 6, iclass 39, count 0 2006.201.16:21:33.01#ibcon#end of sib2, iclass 39, count 0 2006.201.16:21:33.01#ibcon#*after write, iclass 39, count 0 2006.201.16:21:33.01#ibcon#*before return 0, iclass 39, count 0 2006.201.16:21:33.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:33.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:21:33.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:21:33.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:21:33.01$vck44/vb=8,4 2006.201.16:21:33.01#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.16:21:33.01#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.16:21:33.01#ibcon#ireg 11 cls_cnt 2 2006.201.16:21:33.01#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:33.07#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:33.07#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:33.07#ibcon#enter wrdev, iclass 2, count 2 2006.201.16:21:33.07#ibcon#first serial, iclass 2, count 2 2006.201.16:21:33.07#ibcon#enter sib2, iclass 2, count 2 2006.201.16:21:33.07#ibcon#flushed, iclass 2, count 2 2006.201.16:21:33.07#ibcon#about to write, iclass 2, count 2 2006.201.16:21:33.07#ibcon#wrote, iclass 2, count 2 2006.201.16:21:33.07#ibcon#about to read 3, iclass 2, count 2 2006.201.16:21:33.09#ibcon#read 3, iclass 2, count 2 2006.201.16:21:33.09#ibcon#about to read 4, iclass 2, count 2 2006.201.16:21:33.09#ibcon#read 4, iclass 2, count 2 2006.201.16:21:33.09#ibcon#about to read 5, iclass 2, count 2 2006.201.16:21:33.09#ibcon#read 5, iclass 2, count 2 2006.201.16:21:33.09#ibcon#about to read 6, iclass 2, count 2 2006.201.16:21:33.09#ibcon#read 6, iclass 2, count 2 2006.201.16:21:33.09#ibcon#end of sib2, iclass 2, count 2 2006.201.16:21:33.09#ibcon#*mode == 0, iclass 2, count 2 2006.201.16:21:33.09#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.16:21:33.09#ibcon#[27=AT08-04\r\n] 2006.201.16:21:33.09#ibcon#*before write, iclass 2, count 2 2006.201.16:21:33.09#ibcon#enter sib2, iclass 2, count 2 2006.201.16:21:33.09#ibcon#flushed, iclass 2, count 2 2006.201.16:21:33.09#ibcon#about to write, iclass 2, count 2 2006.201.16:21:33.09#ibcon#wrote, iclass 2, count 2 2006.201.16:21:33.09#ibcon#about to read 3, iclass 2, count 2 2006.201.16:21:33.12#ibcon#read 3, iclass 2, count 2 2006.201.16:21:33.12#ibcon#about to read 4, iclass 2, count 2 2006.201.16:21:33.12#ibcon#read 4, iclass 2, count 2 2006.201.16:21:33.12#ibcon#about to read 5, iclass 2, count 2 2006.201.16:21:33.12#ibcon#read 5, iclass 2, count 2 2006.201.16:21:33.12#ibcon#about to read 6, iclass 2, count 2 2006.201.16:21:33.12#ibcon#read 6, iclass 2, count 2 2006.201.16:21:33.12#ibcon#end of sib2, iclass 2, count 2 2006.201.16:21:33.12#ibcon#*after write, iclass 2, count 2 2006.201.16:21:33.12#ibcon#*before return 0, iclass 2, count 2 2006.201.16:21:33.12#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:33.12#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:21:33.12#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.16:21:33.12#ibcon#ireg 7 cls_cnt 0 2006.201.16:21:33.12#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:33.24#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:33.24#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:33.24#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:21:33.24#ibcon#first serial, iclass 2, count 0 2006.201.16:21:33.24#ibcon#enter sib2, iclass 2, count 0 2006.201.16:21:33.24#ibcon#flushed, iclass 2, count 0 2006.201.16:21:33.24#ibcon#about to write, iclass 2, count 0 2006.201.16:21:33.24#ibcon#wrote, iclass 2, count 0 2006.201.16:21:33.24#ibcon#about to read 3, iclass 2, count 0 2006.201.16:21:33.26#ibcon#read 3, iclass 2, count 0 2006.201.16:21:33.26#ibcon#about to read 4, iclass 2, count 0 2006.201.16:21:33.26#ibcon#read 4, iclass 2, count 0 2006.201.16:21:33.26#ibcon#about to read 5, iclass 2, count 0 2006.201.16:21:33.26#ibcon#read 5, iclass 2, count 0 2006.201.16:21:33.26#ibcon#about to read 6, iclass 2, count 0 2006.201.16:21:33.26#ibcon#read 6, iclass 2, count 0 2006.201.16:21:33.26#ibcon#end of sib2, iclass 2, count 0 2006.201.16:21:33.26#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:21:33.26#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:21:33.26#ibcon#[27=USB\r\n] 2006.201.16:21:33.26#ibcon#*before write, iclass 2, count 0 2006.201.16:21:33.26#ibcon#enter sib2, iclass 2, count 0 2006.201.16:21:33.26#ibcon#flushed, iclass 2, count 0 2006.201.16:21:33.26#ibcon#about to write, iclass 2, count 0 2006.201.16:21:33.26#ibcon#wrote, iclass 2, count 0 2006.201.16:21:33.26#ibcon#about to read 3, iclass 2, count 0 2006.201.16:21:33.29#ibcon#read 3, iclass 2, count 0 2006.201.16:21:33.29#ibcon#about to read 4, iclass 2, count 0 2006.201.16:21:33.29#ibcon#read 4, iclass 2, count 0 2006.201.16:21:33.29#ibcon#about to read 5, iclass 2, count 0 2006.201.16:21:33.29#ibcon#read 5, iclass 2, count 0 2006.201.16:21:33.29#ibcon#about to read 6, iclass 2, count 0 2006.201.16:21:33.29#ibcon#read 6, iclass 2, count 0 2006.201.16:21:33.29#ibcon#end of sib2, iclass 2, count 0 2006.201.16:21:33.29#ibcon#*after write, iclass 2, count 0 2006.201.16:21:33.29#ibcon#*before return 0, iclass 2, count 0 2006.201.16:21:33.29#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:33.29#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:21:33.29#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:21:33.29#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:21:33.29$vck44/vabw=wide 2006.201.16:21:33.29#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.16:21:33.29#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.16:21:33.29#ibcon#ireg 8 cls_cnt 0 2006.201.16:21:33.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:33.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:33.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:33.29#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:21:33.29#ibcon#first serial, iclass 5, count 0 2006.201.16:21:33.29#ibcon#enter sib2, iclass 5, count 0 2006.201.16:21:33.29#ibcon#flushed, iclass 5, count 0 2006.201.16:21:33.29#ibcon#about to write, iclass 5, count 0 2006.201.16:21:33.29#ibcon#wrote, iclass 5, count 0 2006.201.16:21:33.29#ibcon#about to read 3, iclass 5, count 0 2006.201.16:21:33.31#ibcon#read 3, iclass 5, count 0 2006.201.16:21:33.31#ibcon#about to read 4, iclass 5, count 0 2006.201.16:21:33.31#ibcon#read 4, iclass 5, count 0 2006.201.16:21:33.31#ibcon#about to read 5, iclass 5, count 0 2006.201.16:21:33.31#ibcon#read 5, iclass 5, count 0 2006.201.16:21:33.31#ibcon#about to read 6, iclass 5, count 0 2006.201.16:21:33.31#ibcon#read 6, iclass 5, count 0 2006.201.16:21:33.31#ibcon#end of sib2, iclass 5, count 0 2006.201.16:21:33.31#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:21:33.31#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:21:33.31#ibcon#[25=BW32\r\n] 2006.201.16:21:33.31#ibcon#*before write, iclass 5, count 0 2006.201.16:21:33.31#ibcon#enter sib2, iclass 5, count 0 2006.201.16:21:33.31#ibcon#flushed, iclass 5, count 0 2006.201.16:21:33.31#ibcon#about to write, iclass 5, count 0 2006.201.16:21:33.31#ibcon#wrote, iclass 5, count 0 2006.201.16:21:33.31#ibcon#about to read 3, iclass 5, count 0 2006.201.16:21:33.35#ibcon#read 3, iclass 5, count 0 2006.201.16:21:33.35#ibcon#about to read 4, iclass 5, count 0 2006.201.16:21:33.35#ibcon#read 4, iclass 5, count 0 2006.201.16:21:33.35#ibcon#about to read 5, iclass 5, count 0 2006.201.16:21:33.35#ibcon#read 5, iclass 5, count 0 2006.201.16:21:33.35#ibcon#about to read 6, iclass 5, count 0 2006.201.16:21:33.35#ibcon#read 6, iclass 5, count 0 2006.201.16:21:33.35#ibcon#end of sib2, iclass 5, count 0 2006.201.16:21:33.35#ibcon#*after write, iclass 5, count 0 2006.201.16:21:33.35#ibcon#*before return 0, iclass 5, count 0 2006.201.16:21:33.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:33.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:21:33.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:21:33.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:21:33.35$vck44/vbbw=wide 2006.201.16:21:33.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.16:21:33.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.16:21:33.35#ibcon#ireg 8 cls_cnt 0 2006.201.16:21:33.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:21:33.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:21:33.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:21:33.41#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:21:33.41#ibcon#first serial, iclass 7, count 0 2006.201.16:21:33.41#ibcon#enter sib2, iclass 7, count 0 2006.201.16:21:33.41#ibcon#flushed, iclass 7, count 0 2006.201.16:21:33.41#ibcon#about to write, iclass 7, count 0 2006.201.16:21:33.41#ibcon#wrote, iclass 7, count 0 2006.201.16:21:33.41#ibcon#about to read 3, iclass 7, count 0 2006.201.16:21:33.43#ibcon#read 3, iclass 7, count 0 2006.201.16:21:33.43#ibcon#about to read 4, iclass 7, count 0 2006.201.16:21:33.43#ibcon#read 4, iclass 7, count 0 2006.201.16:21:33.43#ibcon#about to read 5, iclass 7, count 0 2006.201.16:21:33.43#ibcon#read 5, iclass 7, count 0 2006.201.16:21:33.43#ibcon#about to read 6, iclass 7, count 0 2006.201.16:21:33.43#ibcon#read 6, iclass 7, count 0 2006.201.16:21:33.43#ibcon#end of sib2, iclass 7, count 0 2006.201.16:21:33.43#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:21:33.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:21:33.43#ibcon#[27=BW32\r\n] 2006.201.16:21:33.43#ibcon#*before write, iclass 7, count 0 2006.201.16:21:33.43#ibcon#enter sib2, iclass 7, count 0 2006.201.16:21:33.43#ibcon#flushed, iclass 7, count 0 2006.201.16:21:33.43#ibcon#about to write, iclass 7, count 0 2006.201.16:21:33.43#ibcon#wrote, iclass 7, count 0 2006.201.16:21:33.43#ibcon#about to read 3, iclass 7, count 0 2006.201.16:21:33.46#ibcon#read 3, iclass 7, count 0 2006.201.16:21:33.46#ibcon#about to read 4, iclass 7, count 0 2006.201.16:21:33.46#ibcon#read 4, iclass 7, count 0 2006.201.16:21:33.46#ibcon#about to read 5, iclass 7, count 0 2006.201.16:21:33.46#ibcon#read 5, iclass 7, count 0 2006.201.16:21:33.46#ibcon#about to read 6, iclass 7, count 0 2006.201.16:21:33.46#ibcon#read 6, iclass 7, count 0 2006.201.16:21:33.46#ibcon#end of sib2, iclass 7, count 0 2006.201.16:21:33.46#ibcon#*after write, iclass 7, count 0 2006.201.16:21:33.46#ibcon#*before return 0, iclass 7, count 0 2006.201.16:21:33.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:21:33.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:21:33.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:21:33.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:21:33.46$setupk4/ifdk4 2006.201.16:21:33.46$ifdk4/lo= 2006.201.16:21:33.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:21:33.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:21:33.46$ifdk4/patch= 2006.201.16:21:33.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:21:33.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:21:33.46$setupk4/!*+20s 2006.201.16:21:33.78#abcon#<5=/00 0.2 0.4 20.781001002.9\r\n> 2006.201.16:21:33.80#abcon#{5=INTERFACE CLEAR} 2006.201.16:21:33.86#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:21:43.95#abcon#<5=/00 0.2 0.4 20.781001002.8\r\n> 2006.201.16:21:43.97#abcon#{5=INTERFACE CLEAR} 2006.201.16:21:44.03#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:21:46.13#trakl#Source acquired 2006.201.16:21:47.13#flagr#flagr/antenna,acquired 2006.201.16:21:47.91$setupk4/"tpicd 2006.201.16:21:47.91$setupk4/echo=off 2006.201.16:21:47.91$setupk4/xlog=off 2006.201.16:21:47.91:!2006.201.16:24:34 2006.201.16:24:34.00:preob 2006.201.16:24:34.14/onsource/TRACKING 2006.201.16:24:34.14:!2006.201.16:24:44 2006.201.16:24:44.00:"tape 2006.201.16:24:44.00:"st=record 2006.201.16:24:44.00:data_valid=on 2006.201.16:24:44.00:midob 2006.201.16:24:44.14/onsource/TRACKING 2006.201.16:24:44.14/wx/20.78,1002.7,100 2006.201.16:24:44.29/cable/+6.4764E-03 2006.201.16:24:45.38/va/01,08,usb,yes,34,36 2006.201.16:24:45.38/va/02,07,usb,yes,36,37 2006.201.16:24:45.38/va/03,08,usb,yes,33,34 2006.201.16:24:45.38/va/04,07,usb,yes,37,39 2006.201.16:24:45.38/va/05,04,usb,yes,33,34 2006.201.16:24:45.38/va/06,05,usb,yes,33,33 2006.201.16:24:45.38/va/07,05,usb,yes,32,34 2006.201.16:24:45.38/va/08,04,usb,yes,32,38 2006.201.16:24:45.61/valo/01,524.99,yes,locked 2006.201.16:24:45.61/valo/02,534.99,yes,locked 2006.201.16:24:45.61/valo/03,564.99,yes,locked 2006.201.16:24:45.61/valo/04,624.99,yes,locked 2006.201.16:24:45.61/valo/05,734.99,yes,locked 2006.201.16:24:45.61/valo/06,814.99,yes,locked 2006.201.16:24:45.61/valo/07,864.99,yes,locked 2006.201.16:24:45.61/valo/08,884.99,yes,locked 2006.201.16:24:46.70/vb/01,04,usb,yes,29,32 2006.201.16:24:46.70/vb/02,05,usb,yes,27,31 2006.201.16:24:46.70/vb/03,04,usb,yes,29,32 2006.201.16:24:46.70/vb/04,05,usb,yes,28,27 2006.201.16:24:46.70/vb/05,04,usb,yes,25,28 2006.201.16:24:46.70/vb/06,04,usb,yes,30,26 2006.201.16:24:46.70/vb/07,04,usb,yes,30,29 2006.201.16:24:46.70/vb/08,04,usb,yes,27,30 2006.201.16:24:46.93/vblo/01,629.99,yes,locked 2006.201.16:24:46.93/vblo/02,634.99,yes,locked 2006.201.16:24:46.93/vblo/03,649.99,yes,locked 2006.201.16:24:46.93/vblo/04,679.99,yes,locked 2006.201.16:24:46.93/vblo/05,709.99,yes,locked 2006.201.16:24:46.93/vblo/06,719.99,yes,locked 2006.201.16:24:46.93/vblo/07,734.99,yes,locked 2006.201.16:24:46.93/vblo/08,744.99,yes,locked 2006.201.16:24:47.08/vabw/8 2006.201.16:24:47.23/vbbw/8 2006.201.16:24:47.41/xfe/off,on,15.2 2006.201.16:24:47.83/ifatt/23,28,28,28 2006.201.16:24:48.06/fmout-gps/S +4.54E-07 2006.201.16:24:48.13:!2006.201.16:29:04 2006.201.16:29:04.00:data_valid=off 2006.201.16:29:04.00:"et 2006.201.16:29:04.00:!+3s 2006.201.16:29:07.02:"tape 2006.201.16:29:07.02:postob 2006.201.16:29:07.21/cable/+6.4743E-03 2006.201.16:29:07.21/wx/20.82,1002.6,100 2006.201.16:29:07.28/fmout-gps/S +4.56E-07 2006.201.16:29:07.28:scan_name=201-1632,jd0607,40 2006.201.16:29:07.28:source=2134+00,213638.59,004154.2,2000.0,ccw 2006.201.16:29:08.13#flagr#flagr/antenna,new-source 2006.201.16:29:08.13:checkk5 2006.201.16:29:08.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:29:08.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:29:09.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:29:09.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:29:10.01/chk_obsdata//k5ts1/T2011624??a.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.201.16:29:10.38/chk_obsdata//k5ts2/T2011624??b.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.201.16:29:10.74/chk_obsdata//k5ts3/T2011624??c.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.201.16:29:11.11/chk_obsdata//k5ts4/T2011624??d.dat file size is correct (nominal:1040MB, actual:1040MB). 2006.201.16:29:11.81/k5log//k5ts1_log_newline 2006.201.16:29:12.49/k5log//k5ts2_log_newline 2006.201.16:29:13.18/k5log//k5ts3_log_newline 2006.201.16:29:13.87/k5log//k5ts4_log_newline 2006.201.16:29:13.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:29:13.89:setupk4=1 2006.201.16:29:13.89$setupk4/echo=on 2006.201.16:29:13.89$setupk4/pcalon 2006.201.16:29:13.89$pcalon/"no phase cal control is implemented here 2006.201.16:29:13.89$setupk4/"tpicd=stop 2006.201.16:29:13.89$setupk4/"rec=synch_on 2006.201.16:29:13.89$setupk4/"rec_mode=128 2006.201.16:29:13.89$setupk4/!* 2006.201.16:29:13.89$setupk4/recpk4 2006.201.16:29:13.89$recpk4/recpatch= 2006.201.16:29:13.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:29:13.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:29:13.90$setupk4/vck44 2006.201.16:29:13.90$vck44/valo=1,524.99 2006.201.16:29:13.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.16:29:13.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.16:29:13.90#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:13.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:13.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:13.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:13.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:29:13.90#ibcon#first serial, iclass 18, count 0 2006.201.16:29:13.90#ibcon#enter sib2, iclass 18, count 0 2006.201.16:29:13.90#ibcon#flushed, iclass 18, count 0 2006.201.16:29:13.90#ibcon#about to write, iclass 18, count 0 2006.201.16:29:13.90#ibcon#wrote, iclass 18, count 0 2006.201.16:29:13.90#ibcon#about to read 3, iclass 18, count 0 2006.201.16:29:13.94#ibcon#read 3, iclass 18, count 0 2006.201.16:29:13.94#ibcon#about to read 4, iclass 18, count 0 2006.201.16:29:13.94#ibcon#read 4, iclass 18, count 0 2006.201.16:29:13.94#ibcon#about to read 5, iclass 18, count 0 2006.201.16:29:13.94#ibcon#read 5, iclass 18, count 0 2006.201.16:29:13.94#ibcon#about to read 6, iclass 18, count 0 2006.201.16:29:13.94#ibcon#read 6, iclass 18, count 0 2006.201.16:29:13.94#ibcon#end of sib2, iclass 18, count 0 2006.201.16:29:13.94#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:29:13.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:29:13.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:29:13.94#ibcon#*before write, iclass 18, count 0 2006.201.16:29:13.94#ibcon#enter sib2, iclass 18, count 0 2006.201.16:29:13.94#ibcon#flushed, iclass 18, count 0 2006.201.16:29:13.94#ibcon#about to write, iclass 18, count 0 2006.201.16:29:13.94#ibcon#wrote, iclass 18, count 0 2006.201.16:29:13.94#ibcon#about to read 3, iclass 18, count 0 2006.201.16:29:13.99#ibcon#read 3, iclass 18, count 0 2006.201.16:29:13.99#ibcon#about to read 4, iclass 18, count 0 2006.201.16:29:13.99#ibcon#read 4, iclass 18, count 0 2006.201.16:29:13.99#ibcon#about to read 5, iclass 18, count 0 2006.201.16:29:13.99#ibcon#read 5, iclass 18, count 0 2006.201.16:29:13.99#ibcon#about to read 6, iclass 18, count 0 2006.201.16:29:13.99#ibcon#read 6, iclass 18, count 0 2006.201.16:29:13.99#ibcon#end of sib2, iclass 18, count 0 2006.201.16:29:13.99#ibcon#*after write, iclass 18, count 0 2006.201.16:29:13.99#ibcon#*before return 0, iclass 18, count 0 2006.201.16:29:13.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:13.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:13.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:29:13.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:29:13.99$vck44/va=1,8 2006.201.16:29:13.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.16:29:13.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.16:29:13.99#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:13.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:13.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:13.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:13.99#ibcon#enter wrdev, iclass 20, count 2 2006.201.16:29:13.99#ibcon#first serial, iclass 20, count 2 2006.201.16:29:13.99#ibcon#enter sib2, iclass 20, count 2 2006.201.16:29:13.99#ibcon#flushed, iclass 20, count 2 2006.201.16:29:13.99#ibcon#about to write, iclass 20, count 2 2006.201.16:29:13.99#ibcon#wrote, iclass 20, count 2 2006.201.16:29:13.99#ibcon#about to read 3, iclass 20, count 2 2006.201.16:29:14.01#ibcon#read 3, iclass 20, count 2 2006.201.16:29:14.01#ibcon#about to read 4, iclass 20, count 2 2006.201.16:29:14.01#ibcon#read 4, iclass 20, count 2 2006.201.16:29:14.01#ibcon#about to read 5, iclass 20, count 2 2006.201.16:29:14.01#ibcon#read 5, iclass 20, count 2 2006.201.16:29:14.01#ibcon#about to read 6, iclass 20, count 2 2006.201.16:29:14.01#ibcon#read 6, iclass 20, count 2 2006.201.16:29:14.01#ibcon#end of sib2, iclass 20, count 2 2006.201.16:29:14.01#ibcon#*mode == 0, iclass 20, count 2 2006.201.16:29:14.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.16:29:14.01#ibcon#[25=AT01-08\r\n] 2006.201.16:29:14.01#ibcon#*before write, iclass 20, count 2 2006.201.16:29:14.01#ibcon#enter sib2, iclass 20, count 2 2006.201.16:29:14.01#ibcon#flushed, iclass 20, count 2 2006.201.16:29:14.01#ibcon#about to write, iclass 20, count 2 2006.201.16:29:14.01#ibcon#wrote, iclass 20, count 2 2006.201.16:29:14.01#ibcon#about to read 3, iclass 20, count 2 2006.201.16:29:14.05#ibcon#read 3, iclass 20, count 2 2006.201.16:29:14.05#ibcon#about to read 4, iclass 20, count 2 2006.201.16:29:14.05#ibcon#read 4, iclass 20, count 2 2006.201.16:29:14.05#ibcon#about to read 5, iclass 20, count 2 2006.201.16:29:14.05#ibcon#read 5, iclass 20, count 2 2006.201.16:29:14.05#ibcon#about to read 6, iclass 20, count 2 2006.201.16:29:14.05#ibcon#read 6, iclass 20, count 2 2006.201.16:29:14.05#ibcon#end of sib2, iclass 20, count 2 2006.201.16:29:14.05#ibcon#*after write, iclass 20, count 2 2006.201.16:29:14.05#ibcon#*before return 0, iclass 20, count 2 2006.201.16:29:14.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:14.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:14.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.16:29:14.05#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:14.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:14.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:14.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:14.17#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:29:14.17#ibcon#first serial, iclass 20, count 0 2006.201.16:29:14.17#ibcon#enter sib2, iclass 20, count 0 2006.201.16:29:14.17#ibcon#flushed, iclass 20, count 0 2006.201.16:29:14.17#ibcon#about to write, iclass 20, count 0 2006.201.16:29:14.17#ibcon#wrote, iclass 20, count 0 2006.201.16:29:14.17#ibcon#about to read 3, iclass 20, count 0 2006.201.16:29:14.19#ibcon#read 3, iclass 20, count 0 2006.201.16:29:14.19#ibcon#about to read 4, iclass 20, count 0 2006.201.16:29:14.19#ibcon#read 4, iclass 20, count 0 2006.201.16:29:14.19#ibcon#about to read 5, iclass 20, count 0 2006.201.16:29:14.19#ibcon#read 5, iclass 20, count 0 2006.201.16:29:14.19#ibcon#about to read 6, iclass 20, count 0 2006.201.16:29:14.19#ibcon#read 6, iclass 20, count 0 2006.201.16:29:14.19#ibcon#end of sib2, iclass 20, count 0 2006.201.16:29:14.19#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:29:14.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:29:14.19#ibcon#[25=USB\r\n] 2006.201.16:29:14.19#ibcon#*before write, iclass 20, count 0 2006.201.16:29:14.19#ibcon#enter sib2, iclass 20, count 0 2006.201.16:29:14.19#ibcon#flushed, iclass 20, count 0 2006.201.16:29:14.19#ibcon#about to write, iclass 20, count 0 2006.201.16:29:14.19#ibcon#wrote, iclass 20, count 0 2006.201.16:29:14.19#ibcon#about to read 3, iclass 20, count 0 2006.201.16:29:14.22#ibcon#read 3, iclass 20, count 0 2006.201.16:29:14.22#ibcon#about to read 4, iclass 20, count 0 2006.201.16:29:14.22#ibcon#read 4, iclass 20, count 0 2006.201.16:29:14.22#ibcon#about to read 5, iclass 20, count 0 2006.201.16:29:14.22#ibcon#read 5, iclass 20, count 0 2006.201.16:29:14.22#ibcon#about to read 6, iclass 20, count 0 2006.201.16:29:14.22#ibcon#read 6, iclass 20, count 0 2006.201.16:29:14.22#ibcon#end of sib2, iclass 20, count 0 2006.201.16:29:14.22#ibcon#*after write, iclass 20, count 0 2006.201.16:29:14.22#ibcon#*before return 0, iclass 20, count 0 2006.201.16:29:14.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:14.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:14.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:29:14.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:29:14.22$vck44/valo=2,534.99 2006.201.16:29:14.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.16:29:14.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.16:29:14.22#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:14.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:14.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:14.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:14.22#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:29:14.22#ibcon#first serial, iclass 22, count 0 2006.201.16:29:14.22#ibcon#enter sib2, iclass 22, count 0 2006.201.16:29:14.22#ibcon#flushed, iclass 22, count 0 2006.201.16:29:14.22#ibcon#about to write, iclass 22, count 0 2006.201.16:29:14.22#ibcon#wrote, iclass 22, count 0 2006.201.16:29:14.22#ibcon#about to read 3, iclass 22, count 0 2006.201.16:29:14.24#ibcon#read 3, iclass 22, count 0 2006.201.16:29:14.24#ibcon#about to read 4, iclass 22, count 0 2006.201.16:29:14.24#ibcon#read 4, iclass 22, count 0 2006.201.16:29:14.24#ibcon#about to read 5, iclass 22, count 0 2006.201.16:29:14.24#ibcon#read 5, iclass 22, count 0 2006.201.16:29:14.24#ibcon#about to read 6, iclass 22, count 0 2006.201.16:29:14.24#ibcon#read 6, iclass 22, count 0 2006.201.16:29:14.24#ibcon#end of sib2, iclass 22, count 0 2006.201.16:29:14.24#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:29:14.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:29:14.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:29:14.24#ibcon#*before write, iclass 22, count 0 2006.201.16:29:14.24#ibcon#enter sib2, iclass 22, count 0 2006.201.16:29:14.24#ibcon#flushed, iclass 22, count 0 2006.201.16:29:14.24#ibcon#about to write, iclass 22, count 0 2006.201.16:29:14.24#ibcon#wrote, iclass 22, count 0 2006.201.16:29:14.24#ibcon#about to read 3, iclass 22, count 0 2006.201.16:29:14.28#ibcon#read 3, iclass 22, count 0 2006.201.16:29:14.28#ibcon#about to read 4, iclass 22, count 0 2006.201.16:29:14.28#ibcon#read 4, iclass 22, count 0 2006.201.16:29:14.28#ibcon#about to read 5, iclass 22, count 0 2006.201.16:29:14.28#ibcon#read 5, iclass 22, count 0 2006.201.16:29:14.28#ibcon#about to read 6, iclass 22, count 0 2006.201.16:29:14.28#ibcon#read 6, iclass 22, count 0 2006.201.16:29:14.28#ibcon#end of sib2, iclass 22, count 0 2006.201.16:29:14.28#ibcon#*after write, iclass 22, count 0 2006.201.16:29:14.28#ibcon#*before return 0, iclass 22, count 0 2006.201.16:29:14.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:14.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:14.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:29:14.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:29:14.28$vck44/va=2,7 2006.201.16:29:14.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.16:29:14.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.16:29:14.28#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:14.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:14.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:14.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:14.34#ibcon#enter wrdev, iclass 24, count 2 2006.201.16:29:14.34#ibcon#first serial, iclass 24, count 2 2006.201.16:29:14.34#ibcon#enter sib2, iclass 24, count 2 2006.201.16:29:14.34#ibcon#flushed, iclass 24, count 2 2006.201.16:29:14.34#ibcon#about to write, iclass 24, count 2 2006.201.16:29:14.34#ibcon#wrote, iclass 24, count 2 2006.201.16:29:14.34#ibcon#about to read 3, iclass 24, count 2 2006.201.16:29:14.36#ibcon#read 3, iclass 24, count 2 2006.201.16:29:14.36#ibcon#about to read 4, iclass 24, count 2 2006.201.16:29:14.36#ibcon#read 4, iclass 24, count 2 2006.201.16:29:14.36#ibcon#about to read 5, iclass 24, count 2 2006.201.16:29:14.36#ibcon#read 5, iclass 24, count 2 2006.201.16:29:14.36#ibcon#about to read 6, iclass 24, count 2 2006.201.16:29:14.36#ibcon#read 6, iclass 24, count 2 2006.201.16:29:14.36#ibcon#end of sib2, iclass 24, count 2 2006.201.16:29:14.36#ibcon#*mode == 0, iclass 24, count 2 2006.201.16:29:14.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.16:29:14.36#ibcon#[25=AT02-07\r\n] 2006.201.16:29:14.36#ibcon#*before write, iclass 24, count 2 2006.201.16:29:14.36#ibcon#enter sib2, iclass 24, count 2 2006.201.16:29:14.36#ibcon#flushed, iclass 24, count 2 2006.201.16:29:14.36#ibcon#about to write, iclass 24, count 2 2006.201.16:29:14.36#ibcon#wrote, iclass 24, count 2 2006.201.16:29:14.36#ibcon#about to read 3, iclass 24, count 2 2006.201.16:29:14.39#ibcon#read 3, iclass 24, count 2 2006.201.16:29:14.39#ibcon#about to read 4, iclass 24, count 2 2006.201.16:29:14.39#ibcon#read 4, iclass 24, count 2 2006.201.16:29:14.39#ibcon#about to read 5, iclass 24, count 2 2006.201.16:29:14.39#ibcon#read 5, iclass 24, count 2 2006.201.16:29:14.39#ibcon#about to read 6, iclass 24, count 2 2006.201.16:29:14.39#ibcon#read 6, iclass 24, count 2 2006.201.16:29:14.39#ibcon#end of sib2, iclass 24, count 2 2006.201.16:29:14.39#ibcon#*after write, iclass 24, count 2 2006.201.16:29:14.39#ibcon#*before return 0, iclass 24, count 2 2006.201.16:29:14.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:14.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:14.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.16:29:14.39#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:14.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:14.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:14.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:14.51#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:29:14.51#ibcon#first serial, iclass 24, count 0 2006.201.16:29:14.51#ibcon#enter sib2, iclass 24, count 0 2006.201.16:29:14.51#ibcon#flushed, iclass 24, count 0 2006.201.16:29:14.51#ibcon#about to write, iclass 24, count 0 2006.201.16:29:14.51#ibcon#wrote, iclass 24, count 0 2006.201.16:29:14.51#ibcon#about to read 3, iclass 24, count 0 2006.201.16:29:14.53#ibcon#read 3, iclass 24, count 0 2006.201.16:29:14.53#ibcon#about to read 4, iclass 24, count 0 2006.201.16:29:14.53#ibcon#read 4, iclass 24, count 0 2006.201.16:29:14.53#ibcon#about to read 5, iclass 24, count 0 2006.201.16:29:14.53#ibcon#read 5, iclass 24, count 0 2006.201.16:29:14.53#ibcon#about to read 6, iclass 24, count 0 2006.201.16:29:14.53#ibcon#read 6, iclass 24, count 0 2006.201.16:29:14.53#ibcon#end of sib2, iclass 24, count 0 2006.201.16:29:14.53#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:29:14.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:29:14.53#ibcon#[25=USB\r\n] 2006.201.16:29:14.53#ibcon#*before write, iclass 24, count 0 2006.201.16:29:14.53#ibcon#enter sib2, iclass 24, count 0 2006.201.16:29:14.53#ibcon#flushed, iclass 24, count 0 2006.201.16:29:14.53#ibcon#about to write, iclass 24, count 0 2006.201.16:29:14.53#ibcon#wrote, iclass 24, count 0 2006.201.16:29:14.53#ibcon#about to read 3, iclass 24, count 0 2006.201.16:29:14.56#ibcon#read 3, iclass 24, count 0 2006.201.16:29:14.56#ibcon#about to read 4, iclass 24, count 0 2006.201.16:29:14.56#ibcon#read 4, iclass 24, count 0 2006.201.16:29:14.56#ibcon#about to read 5, iclass 24, count 0 2006.201.16:29:14.56#ibcon#read 5, iclass 24, count 0 2006.201.16:29:14.56#ibcon#about to read 6, iclass 24, count 0 2006.201.16:29:14.56#ibcon#read 6, iclass 24, count 0 2006.201.16:29:14.56#ibcon#end of sib2, iclass 24, count 0 2006.201.16:29:14.56#ibcon#*after write, iclass 24, count 0 2006.201.16:29:14.56#ibcon#*before return 0, iclass 24, count 0 2006.201.16:29:14.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:14.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:14.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:29:14.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:29:14.56$vck44/valo=3,564.99 2006.201.16:29:14.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.16:29:14.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.16:29:14.56#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:14.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:14.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:14.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:14.56#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:29:14.56#ibcon#first serial, iclass 26, count 0 2006.201.16:29:14.56#ibcon#enter sib2, iclass 26, count 0 2006.201.16:29:14.56#ibcon#flushed, iclass 26, count 0 2006.201.16:29:14.56#ibcon#about to write, iclass 26, count 0 2006.201.16:29:14.56#ibcon#wrote, iclass 26, count 0 2006.201.16:29:14.56#ibcon#about to read 3, iclass 26, count 0 2006.201.16:29:14.58#ibcon#read 3, iclass 26, count 0 2006.201.16:29:14.58#ibcon#about to read 4, iclass 26, count 0 2006.201.16:29:14.58#ibcon#read 4, iclass 26, count 0 2006.201.16:29:14.58#ibcon#about to read 5, iclass 26, count 0 2006.201.16:29:14.58#ibcon#read 5, iclass 26, count 0 2006.201.16:29:14.58#ibcon#about to read 6, iclass 26, count 0 2006.201.16:29:14.58#ibcon#read 6, iclass 26, count 0 2006.201.16:29:14.58#ibcon#end of sib2, iclass 26, count 0 2006.201.16:29:14.58#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:29:14.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:29:14.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:29:14.58#ibcon#*before write, iclass 26, count 0 2006.201.16:29:14.58#ibcon#enter sib2, iclass 26, count 0 2006.201.16:29:14.58#ibcon#flushed, iclass 26, count 0 2006.201.16:29:14.58#ibcon#about to write, iclass 26, count 0 2006.201.16:29:14.58#ibcon#wrote, iclass 26, count 0 2006.201.16:29:14.58#ibcon#about to read 3, iclass 26, count 0 2006.201.16:29:14.63#ibcon#read 3, iclass 26, count 0 2006.201.16:29:14.63#ibcon#about to read 4, iclass 26, count 0 2006.201.16:29:14.63#ibcon#read 4, iclass 26, count 0 2006.201.16:29:14.63#ibcon#about to read 5, iclass 26, count 0 2006.201.16:29:14.63#ibcon#read 5, iclass 26, count 0 2006.201.16:29:14.63#ibcon#about to read 6, iclass 26, count 0 2006.201.16:29:14.63#ibcon#read 6, iclass 26, count 0 2006.201.16:29:14.63#ibcon#end of sib2, iclass 26, count 0 2006.201.16:29:14.63#ibcon#*after write, iclass 26, count 0 2006.201.16:29:14.63#ibcon#*before return 0, iclass 26, count 0 2006.201.16:29:14.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:14.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:14.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:29:14.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:29:14.63$vck44/va=3,8 2006.201.16:29:14.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.16:29:14.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.16:29:14.63#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:14.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:14.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:14.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:14.68#ibcon#enter wrdev, iclass 28, count 2 2006.201.16:29:14.68#ibcon#first serial, iclass 28, count 2 2006.201.16:29:14.68#ibcon#enter sib2, iclass 28, count 2 2006.201.16:29:14.68#ibcon#flushed, iclass 28, count 2 2006.201.16:29:14.68#ibcon#about to write, iclass 28, count 2 2006.201.16:29:14.68#ibcon#wrote, iclass 28, count 2 2006.201.16:29:14.68#ibcon#about to read 3, iclass 28, count 2 2006.201.16:29:14.70#ibcon#read 3, iclass 28, count 2 2006.201.16:29:14.70#ibcon#about to read 4, iclass 28, count 2 2006.201.16:29:14.70#ibcon#read 4, iclass 28, count 2 2006.201.16:29:14.70#ibcon#about to read 5, iclass 28, count 2 2006.201.16:29:14.70#ibcon#read 5, iclass 28, count 2 2006.201.16:29:14.70#ibcon#about to read 6, iclass 28, count 2 2006.201.16:29:14.70#ibcon#read 6, iclass 28, count 2 2006.201.16:29:14.70#ibcon#end of sib2, iclass 28, count 2 2006.201.16:29:14.70#ibcon#*mode == 0, iclass 28, count 2 2006.201.16:29:14.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.16:29:14.70#ibcon#[25=AT03-08\r\n] 2006.201.16:29:14.70#ibcon#*before write, iclass 28, count 2 2006.201.16:29:14.70#ibcon#enter sib2, iclass 28, count 2 2006.201.16:29:14.70#ibcon#flushed, iclass 28, count 2 2006.201.16:29:14.70#ibcon#about to write, iclass 28, count 2 2006.201.16:29:14.70#ibcon#wrote, iclass 28, count 2 2006.201.16:29:14.70#ibcon#about to read 3, iclass 28, count 2 2006.201.16:29:14.73#ibcon#read 3, iclass 28, count 2 2006.201.16:29:14.73#ibcon#about to read 4, iclass 28, count 2 2006.201.16:29:14.73#ibcon#read 4, iclass 28, count 2 2006.201.16:29:14.73#ibcon#about to read 5, iclass 28, count 2 2006.201.16:29:14.73#ibcon#read 5, iclass 28, count 2 2006.201.16:29:14.73#ibcon#about to read 6, iclass 28, count 2 2006.201.16:29:14.73#ibcon#read 6, iclass 28, count 2 2006.201.16:29:14.73#ibcon#end of sib2, iclass 28, count 2 2006.201.16:29:14.73#ibcon#*after write, iclass 28, count 2 2006.201.16:29:14.73#ibcon#*before return 0, iclass 28, count 2 2006.201.16:29:14.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:14.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:14.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.16:29:14.73#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:14.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:14.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:14.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:14.85#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:29:14.85#ibcon#first serial, iclass 28, count 0 2006.201.16:29:14.85#ibcon#enter sib2, iclass 28, count 0 2006.201.16:29:14.85#ibcon#flushed, iclass 28, count 0 2006.201.16:29:14.85#ibcon#about to write, iclass 28, count 0 2006.201.16:29:14.85#ibcon#wrote, iclass 28, count 0 2006.201.16:29:14.85#ibcon#about to read 3, iclass 28, count 0 2006.201.16:29:14.87#ibcon#read 3, iclass 28, count 0 2006.201.16:29:14.87#ibcon#about to read 4, iclass 28, count 0 2006.201.16:29:14.87#ibcon#read 4, iclass 28, count 0 2006.201.16:29:14.87#ibcon#about to read 5, iclass 28, count 0 2006.201.16:29:14.87#ibcon#read 5, iclass 28, count 0 2006.201.16:29:14.87#ibcon#about to read 6, iclass 28, count 0 2006.201.16:29:14.87#ibcon#read 6, iclass 28, count 0 2006.201.16:29:14.87#ibcon#end of sib2, iclass 28, count 0 2006.201.16:29:14.87#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:29:14.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:29:14.87#ibcon#[25=USB\r\n] 2006.201.16:29:14.87#ibcon#*before write, iclass 28, count 0 2006.201.16:29:14.87#ibcon#enter sib2, iclass 28, count 0 2006.201.16:29:14.87#ibcon#flushed, iclass 28, count 0 2006.201.16:29:14.87#ibcon#about to write, iclass 28, count 0 2006.201.16:29:14.87#ibcon#wrote, iclass 28, count 0 2006.201.16:29:14.87#ibcon#about to read 3, iclass 28, count 0 2006.201.16:29:14.90#ibcon#read 3, iclass 28, count 0 2006.201.16:29:14.90#ibcon#about to read 4, iclass 28, count 0 2006.201.16:29:14.90#ibcon#read 4, iclass 28, count 0 2006.201.16:29:14.90#ibcon#about to read 5, iclass 28, count 0 2006.201.16:29:14.90#ibcon#read 5, iclass 28, count 0 2006.201.16:29:14.90#ibcon#about to read 6, iclass 28, count 0 2006.201.16:29:14.90#ibcon#read 6, iclass 28, count 0 2006.201.16:29:14.90#ibcon#end of sib2, iclass 28, count 0 2006.201.16:29:14.90#ibcon#*after write, iclass 28, count 0 2006.201.16:29:14.90#ibcon#*before return 0, iclass 28, count 0 2006.201.16:29:14.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:14.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:14.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:29:14.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:29:14.90$vck44/valo=4,624.99 2006.201.16:29:14.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.16:29:14.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.16:29:14.90#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:14.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:14.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:14.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:14.90#ibcon#enter wrdev, iclass 30, count 0 2006.201.16:29:14.90#ibcon#first serial, iclass 30, count 0 2006.201.16:29:14.90#ibcon#enter sib2, iclass 30, count 0 2006.201.16:29:14.90#ibcon#flushed, iclass 30, count 0 2006.201.16:29:14.90#ibcon#about to write, iclass 30, count 0 2006.201.16:29:14.90#ibcon#wrote, iclass 30, count 0 2006.201.16:29:14.90#ibcon#about to read 3, iclass 30, count 0 2006.201.16:29:14.92#ibcon#read 3, iclass 30, count 0 2006.201.16:29:14.92#ibcon#about to read 4, iclass 30, count 0 2006.201.16:29:14.92#ibcon#read 4, iclass 30, count 0 2006.201.16:29:14.92#ibcon#about to read 5, iclass 30, count 0 2006.201.16:29:14.92#ibcon#read 5, iclass 30, count 0 2006.201.16:29:14.92#ibcon#about to read 6, iclass 30, count 0 2006.201.16:29:14.92#ibcon#read 6, iclass 30, count 0 2006.201.16:29:14.92#ibcon#end of sib2, iclass 30, count 0 2006.201.16:29:14.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.16:29:14.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.16:29:14.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:29:14.92#ibcon#*before write, iclass 30, count 0 2006.201.16:29:14.92#ibcon#enter sib2, iclass 30, count 0 2006.201.16:29:14.92#ibcon#flushed, iclass 30, count 0 2006.201.16:29:14.92#ibcon#about to write, iclass 30, count 0 2006.201.16:29:14.92#ibcon#wrote, iclass 30, count 0 2006.201.16:29:14.92#ibcon#about to read 3, iclass 30, count 0 2006.201.16:29:14.96#ibcon#read 3, iclass 30, count 0 2006.201.16:29:14.96#ibcon#about to read 4, iclass 30, count 0 2006.201.16:29:14.96#ibcon#read 4, iclass 30, count 0 2006.201.16:29:14.96#ibcon#about to read 5, iclass 30, count 0 2006.201.16:29:14.96#ibcon#read 5, iclass 30, count 0 2006.201.16:29:14.96#ibcon#about to read 6, iclass 30, count 0 2006.201.16:29:14.96#ibcon#read 6, iclass 30, count 0 2006.201.16:29:14.96#ibcon#end of sib2, iclass 30, count 0 2006.201.16:29:14.96#ibcon#*after write, iclass 30, count 0 2006.201.16:29:14.96#ibcon#*before return 0, iclass 30, count 0 2006.201.16:29:14.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:14.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:14.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.16:29:14.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.16:29:14.96$vck44/va=4,7 2006.201.16:29:14.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.16:29:14.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.16:29:14.96#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:14.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:15.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:15.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:15.02#ibcon#enter wrdev, iclass 32, count 2 2006.201.16:29:15.02#ibcon#first serial, iclass 32, count 2 2006.201.16:29:15.02#ibcon#enter sib2, iclass 32, count 2 2006.201.16:29:15.02#ibcon#flushed, iclass 32, count 2 2006.201.16:29:15.02#ibcon#about to write, iclass 32, count 2 2006.201.16:29:15.02#ibcon#wrote, iclass 32, count 2 2006.201.16:29:15.02#ibcon#about to read 3, iclass 32, count 2 2006.201.16:29:15.04#ibcon#read 3, iclass 32, count 2 2006.201.16:29:15.04#ibcon#about to read 4, iclass 32, count 2 2006.201.16:29:15.04#ibcon#read 4, iclass 32, count 2 2006.201.16:29:15.04#ibcon#about to read 5, iclass 32, count 2 2006.201.16:29:15.04#ibcon#read 5, iclass 32, count 2 2006.201.16:29:15.04#ibcon#about to read 6, iclass 32, count 2 2006.201.16:29:15.04#ibcon#read 6, iclass 32, count 2 2006.201.16:29:15.04#ibcon#end of sib2, iclass 32, count 2 2006.201.16:29:15.04#ibcon#*mode == 0, iclass 32, count 2 2006.201.16:29:15.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.16:29:15.04#ibcon#[25=AT04-07\r\n] 2006.201.16:29:15.04#ibcon#*before write, iclass 32, count 2 2006.201.16:29:15.04#ibcon#enter sib2, iclass 32, count 2 2006.201.16:29:15.04#ibcon#flushed, iclass 32, count 2 2006.201.16:29:15.04#ibcon#about to write, iclass 32, count 2 2006.201.16:29:15.04#ibcon#wrote, iclass 32, count 2 2006.201.16:29:15.04#ibcon#about to read 3, iclass 32, count 2 2006.201.16:29:15.07#ibcon#read 3, iclass 32, count 2 2006.201.16:29:15.07#ibcon#about to read 4, iclass 32, count 2 2006.201.16:29:15.07#ibcon#read 4, iclass 32, count 2 2006.201.16:29:15.07#ibcon#about to read 5, iclass 32, count 2 2006.201.16:29:15.07#ibcon#read 5, iclass 32, count 2 2006.201.16:29:15.07#ibcon#about to read 6, iclass 32, count 2 2006.201.16:29:15.07#ibcon#read 6, iclass 32, count 2 2006.201.16:29:15.07#ibcon#end of sib2, iclass 32, count 2 2006.201.16:29:15.07#ibcon#*after write, iclass 32, count 2 2006.201.16:29:15.07#ibcon#*before return 0, iclass 32, count 2 2006.201.16:29:15.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:15.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:15.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.16:29:15.07#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:15.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:15.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:15.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:15.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.16:29:15.19#ibcon#first serial, iclass 32, count 0 2006.201.16:29:15.19#ibcon#enter sib2, iclass 32, count 0 2006.201.16:29:15.19#ibcon#flushed, iclass 32, count 0 2006.201.16:29:15.19#ibcon#about to write, iclass 32, count 0 2006.201.16:29:15.19#ibcon#wrote, iclass 32, count 0 2006.201.16:29:15.19#ibcon#about to read 3, iclass 32, count 0 2006.201.16:29:15.21#ibcon#read 3, iclass 32, count 0 2006.201.16:29:15.21#ibcon#about to read 4, iclass 32, count 0 2006.201.16:29:15.21#ibcon#read 4, iclass 32, count 0 2006.201.16:29:15.21#ibcon#about to read 5, iclass 32, count 0 2006.201.16:29:15.21#ibcon#read 5, iclass 32, count 0 2006.201.16:29:15.21#ibcon#about to read 6, iclass 32, count 0 2006.201.16:29:15.21#ibcon#read 6, iclass 32, count 0 2006.201.16:29:15.21#ibcon#end of sib2, iclass 32, count 0 2006.201.16:29:15.21#ibcon#*mode == 0, iclass 32, count 0 2006.201.16:29:15.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.16:29:15.21#ibcon#[25=USB\r\n] 2006.201.16:29:15.21#ibcon#*before write, iclass 32, count 0 2006.201.16:29:15.21#ibcon#enter sib2, iclass 32, count 0 2006.201.16:29:15.21#ibcon#flushed, iclass 32, count 0 2006.201.16:29:15.21#ibcon#about to write, iclass 32, count 0 2006.201.16:29:15.21#ibcon#wrote, iclass 32, count 0 2006.201.16:29:15.21#ibcon#about to read 3, iclass 32, count 0 2006.201.16:29:15.24#ibcon#read 3, iclass 32, count 0 2006.201.16:29:15.24#ibcon#about to read 4, iclass 32, count 0 2006.201.16:29:15.24#ibcon#read 4, iclass 32, count 0 2006.201.16:29:15.24#ibcon#about to read 5, iclass 32, count 0 2006.201.16:29:15.24#ibcon#read 5, iclass 32, count 0 2006.201.16:29:15.24#ibcon#about to read 6, iclass 32, count 0 2006.201.16:29:15.24#ibcon#read 6, iclass 32, count 0 2006.201.16:29:15.24#ibcon#end of sib2, iclass 32, count 0 2006.201.16:29:15.24#ibcon#*after write, iclass 32, count 0 2006.201.16:29:15.24#ibcon#*before return 0, iclass 32, count 0 2006.201.16:29:15.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:15.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:15.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.16:29:15.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.16:29:15.24$vck44/valo=5,734.99 2006.201.16:29:15.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.16:29:15.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.16:29:15.24#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:15.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:15.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:15.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:15.24#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:29:15.24#ibcon#first serial, iclass 34, count 0 2006.201.16:29:15.24#ibcon#enter sib2, iclass 34, count 0 2006.201.16:29:15.24#ibcon#flushed, iclass 34, count 0 2006.201.16:29:15.24#ibcon#about to write, iclass 34, count 0 2006.201.16:29:15.24#ibcon#wrote, iclass 34, count 0 2006.201.16:29:15.24#ibcon#about to read 3, iclass 34, count 0 2006.201.16:29:15.26#ibcon#read 3, iclass 34, count 0 2006.201.16:29:15.26#ibcon#about to read 4, iclass 34, count 0 2006.201.16:29:15.26#ibcon#read 4, iclass 34, count 0 2006.201.16:29:15.26#ibcon#about to read 5, iclass 34, count 0 2006.201.16:29:15.26#ibcon#read 5, iclass 34, count 0 2006.201.16:29:15.26#ibcon#about to read 6, iclass 34, count 0 2006.201.16:29:15.26#ibcon#read 6, iclass 34, count 0 2006.201.16:29:15.26#ibcon#end of sib2, iclass 34, count 0 2006.201.16:29:15.26#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:29:15.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:29:15.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:29:15.26#ibcon#*before write, iclass 34, count 0 2006.201.16:29:15.26#ibcon#enter sib2, iclass 34, count 0 2006.201.16:29:15.26#ibcon#flushed, iclass 34, count 0 2006.201.16:29:15.26#ibcon#about to write, iclass 34, count 0 2006.201.16:29:15.26#ibcon#wrote, iclass 34, count 0 2006.201.16:29:15.26#ibcon#about to read 3, iclass 34, count 0 2006.201.16:29:15.30#ibcon#read 3, iclass 34, count 0 2006.201.16:29:15.30#ibcon#about to read 4, iclass 34, count 0 2006.201.16:29:15.30#ibcon#read 4, iclass 34, count 0 2006.201.16:29:15.30#ibcon#about to read 5, iclass 34, count 0 2006.201.16:29:15.30#ibcon#read 5, iclass 34, count 0 2006.201.16:29:15.30#ibcon#about to read 6, iclass 34, count 0 2006.201.16:29:15.30#ibcon#read 6, iclass 34, count 0 2006.201.16:29:15.30#ibcon#end of sib2, iclass 34, count 0 2006.201.16:29:15.30#ibcon#*after write, iclass 34, count 0 2006.201.16:29:15.30#ibcon#*before return 0, iclass 34, count 0 2006.201.16:29:15.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:15.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:15.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:29:15.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:29:15.30$vck44/va=5,4 2006.201.16:29:15.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.16:29:15.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.16:29:15.30#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:15.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:15.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:15.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:15.36#ibcon#enter wrdev, iclass 36, count 2 2006.201.16:29:15.36#ibcon#first serial, iclass 36, count 2 2006.201.16:29:15.36#ibcon#enter sib2, iclass 36, count 2 2006.201.16:29:15.36#ibcon#flushed, iclass 36, count 2 2006.201.16:29:15.36#ibcon#about to write, iclass 36, count 2 2006.201.16:29:15.36#ibcon#wrote, iclass 36, count 2 2006.201.16:29:15.36#ibcon#about to read 3, iclass 36, count 2 2006.201.16:29:15.38#ibcon#read 3, iclass 36, count 2 2006.201.16:29:15.38#ibcon#about to read 4, iclass 36, count 2 2006.201.16:29:15.38#ibcon#read 4, iclass 36, count 2 2006.201.16:29:15.38#ibcon#about to read 5, iclass 36, count 2 2006.201.16:29:15.38#ibcon#read 5, iclass 36, count 2 2006.201.16:29:15.38#ibcon#about to read 6, iclass 36, count 2 2006.201.16:29:15.38#ibcon#read 6, iclass 36, count 2 2006.201.16:29:15.38#ibcon#end of sib2, iclass 36, count 2 2006.201.16:29:15.38#ibcon#*mode == 0, iclass 36, count 2 2006.201.16:29:15.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.16:29:15.38#ibcon#[25=AT05-04\r\n] 2006.201.16:29:15.38#ibcon#*before write, iclass 36, count 2 2006.201.16:29:15.38#ibcon#enter sib2, iclass 36, count 2 2006.201.16:29:15.38#ibcon#flushed, iclass 36, count 2 2006.201.16:29:15.38#ibcon#about to write, iclass 36, count 2 2006.201.16:29:15.38#ibcon#wrote, iclass 36, count 2 2006.201.16:29:15.38#ibcon#about to read 3, iclass 36, count 2 2006.201.16:29:15.41#ibcon#read 3, iclass 36, count 2 2006.201.16:29:15.41#ibcon#about to read 4, iclass 36, count 2 2006.201.16:29:15.41#ibcon#read 4, iclass 36, count 2 2006.201.16:29:15.41#ibcon#about to read 5, iclass 36, count 2 2006.201.16:29:15.41#ibcon#read 5, iclass 36, count 2 2006.201.16:29:15.41#ibcon#about to read 6, iclass 36, count 2 2006.201.16:29:15.41#ibcon#read 6, iclass 36, count 2 2006.201.16:29:15.41#ibcon#end of sib2, iclass 36, count 2 2006.201.16:29:15.41#ibcon#*after write, iclass 36, count 2 2006.201.16:29:15.41#ibcon#*before return 0, iclass 36, count 2 2006.201.16:29:15.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:15.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:15.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.16:29:15.41#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:15.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:15.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:15.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:15.53#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:29:15.53#ibcon#first serial, iclass 36, count 0 2006.201.16:29:15.53#ibcon#enter sib2, iclass 36, count 0 2006.201.16:29:15.53#ibcon#flushed, iclass 36, count 0 2006.201.16:29:15.53#ibcon#about to write, iclass 36, count 0 2006.201.16:29:15.53#ibcon#wrote, iclass 36, count 0 2006.201.16:29:15.53#ibcon#about to read 3, iclass 36, count 0 2006.201.16:29:15.55#ibcon#read 3, iclass 36, count 0 2006.201.16:29:15.55#ibcon#about to read 4, iclass 36, count 0 2006.201.16:29:15.55#ibcon#read 4, iclass 36, count 0 2006.201.16:29:15.55#ibcon#about to read 5, iclass 36, count 0 2006.201.16:29:15.55#ibcon#read 5, iclass 36, count 0 2006.201.16:29:15.55#ibcon#about to read 6, iclass 36, count 0 2006.201.16:29:15.55#ibcon#read 6, iclass 36, count 0 2006.201.16:29:15.55#ibcon#end of sib2, iclass 36, count 0 2006.201.16:29:15.55#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:29:15.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:29:15.55#ibcon#[25=USB\r\n] 2006.201.16:29:15.55#ibcon#*before write, iclass 36, count 0 2006.201.16:29:15.55#ibcon#enter sib2, iclass 36, count 0 2006.201.16:29:15.55#ibcon#flushed, iclass 36, count 0 2006.201.16:29:15.55#ibcon#about to write, iclass 36, count 0 2006.201.16:29:15.55#ibcon#wrote, iclass 36, count 0 2006.201.16:29:15.55#ibcon#about to read 3, iclass 36, count 0 2006.201.16:29:15.58#ibcon#read 3, iclass 36, count 0 2006.201.16:29:15.58#ibcon#about to read 4, iclass 36, count 0 2006.201.16:29:15.58#ibcon#read 4, iclass 36, count 0 2006.201.16:29:15.58#ibcon#about to read 5, iclass 36, count 0 2006.201.16:29:15.58#ibcon#read 5, iclass 36, count 0 2006.201.16:29:15.58#ibcon#about to read 6, iclass 36, count 0 2006.201.16:29:15.58#ibcon#read 6, iclass 36, count 0 2006.201.16:29:15.58#ibcon#end of sib2, iclass 36, count 0 2006.201.16:29:15.58#ibcon#*after write, iclass 36, count 0 2006.201.16:29:15.58#ibcon#*before return 0, iclass 36, count 0 2006.201.16:29:15.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:15.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:15.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:29:15.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:29:15.58$vck44/valo=6,814.99 2006.201.16:29:15.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.16:29:15.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.16:29:15.58#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:15.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:15.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:15.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:15.58#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:29:15.58#ibcon#first serial, iclass 38, count 0 2006.201.16:29:15.58#ibcon#enter sib2, iclass 38, count 0 2006.201.16:29:15.58#ibcon#flushed, iclass 38, count 0 2006.201.16:29:15.58#ibcon#about to write, iclass 38, count 0 2006.201.16:29:15.58#ibcon#wrote, iclass 38, count 0 2006.201.16:29:15.58#ibcon#about to read 3, iclass 38, count 0 2006.201.16:29:15.60#ibcon#read 3, iclass 38, count 0 2006.201.16:29:15.60#ibcon#about to read 4, iclass 38, count 0 2006.201.16:29:15.60#ibcon#read 4, iclass 38, count 0 2006.201.16:29:15.60#ibcon#about to read 5, iclass 38, count 0 2006.201.16:29:15.60#ibcon#read 5, iclass 38, count 0 2006.201.16:29:15.60#ibcon#about to read 6, iclass 38, count 0 2006.201.16:29:15.60#ibcon#read 6, iclass 38, count 0 2006.201.16:29:15.60#ibcon#end of sib2, iclass 38, count 0 2006.201.16:29:15.60#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:29:15.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:29:15.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:29:15.60#ibcon#*before write, iclass 38, count 0 2006.201.16:29:15.60#ibcon#enter sib2, iclass 38, count 0 2006.201.16:29:15.60#ibcon#flushed, iclass 38, count 0 2006.201.16:29:15.60#ibcon#about to write, iclass 38, count 0 2006.201.16:29:15.60#ibcon#wrote, iclass 38, count 0 2006.201.16:29:15.60#ibcon#about to read 3, iclass 38, count 0 2006.201.16:29:15.64#ibcon#read 3, iclass 38, count 0 2006.201.16:29:15.64#ibcon#about to read 4, iclass 38, count 0 2006.201.16:29:15.64#ibcon#read 4, iclass 38, count 0 2006.201.16:29:15.64#ibcon#about to read 5, iclass 38, count 0 2006.201.16:29:15.64#ibcon#read 5, iclass 38, count 0 2006.201.16:29:15.64#ibcon#about to read 6, iclass 38, count 0 2006.201.16:29:15.64#ibcon#read 6, iclass 38, count 0 2006.201.16:29:15.64#ibcon#end of sib2, iclass 38, count 0 2006.201.16:29:15.64#ibcon#*after write, iclass 38, count 0 2006.201.16:29:15.64#ibcon#*before return 0, iclass 38, count 0 2006.201.16:29:15.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:15.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:15.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:29:15.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:29:15.64$vck44/va=6,5 2006.201.16:29:15.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.16:29:15.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.16:29:15.64#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:15.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:15.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:15.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:15.70#ibcon#enter wrdev, iclass 40, count 2 2006.201.16:29:15.70#ibcon#first serial, iclass 40, count 2 2006.201.16:29:15.70#ibcon#enter sib2, iclass 40, count 2 2006.201.16:29:15.70#ibcon#flushed, iclass 40, count 2 2006.201.16:29:15.70#ibcon#about to write, iclass 40, count 2 2006.201.16:29:15.70#ibcon#wrote, iclass 40, count 2 2006.201.16:29:15.70#ibcon#about to read 3, iclass 40, count 2 2006.201.16:29:15.72#ibcon#read 3, iclass 40, count 2 2006.201.16:29:15.72#ibcon#about to read 4, iclass 40, count 2 2006.201.16:29:15.72#ibcon#read 4, iclass 40, count 2 2006.201.16:29:15.72#ibcon#about to read 5, iclass 40, count 2 2006.201.16:29:15.72#ibcon#read 5, iclass 40, count 2 2006.201.16:29:15.72#ibcon#about to read 6, iclass 40, count 2 2006.201.16:29:15.72#ibcon#read 6, iclass 40, count 2 2006.201.16:29:15.72#ibcon#end of sib2, iclass 40, count 2 2006.201.16:29:15.72#ibcon#*mode == 0, iclass 40, count 2 2006.201.16:29:15.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.16:29:15.72#ibcon#[25=AT06-05\r\n] 2006.201.16:29:15.72#ibcon#*before write, iclass 40, count 2 2006.201.16:29:15.72#ibcon#enter sib2, iclass 40, count 2 2006.201.16:29:15.72#ibcon#flushed, iclass 40, count 2 2006.201.16:29:15.72#ibcon#about to write, iclass 40, count 2 2006.201.16:29:15.72#ibcon#wrote, iclass 40, count 2 2006.201.16:29:15.72#ibcon#about to read 3, iclass 40, count 2 2006.201.16:29:15.75#ibcon#read 3, iclass 40, count 2 2006.201.16:29:15.75#ibcon#about to read 4, iclass 40, count 2 2006.201.16:29:15.75#ibcon#read 4, iclass 40, count 2 2006.201.16:29:15.75#ibcon#about to read 5, iclass 40, count 2 2006.201.16:29:15.75#ibcon#read 5, iclass 40, count 2 2006.201.16:29:15.75#ibcon#about to read 6, iclass 40, count 2 2006.201.16:29:15.75#ibcon#read 6, iclass 40, count 2 2006.201.16:29:15.75#ibcon#end of sib2, iclass 40, count 2 2006.201.16:29:15.75#ibcon#*after write, iclass 40, count 2 2006.201.16:29:15.75#ibcon#*before return 0, iclass 40, count 2 2006.201.16:29:15.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:15.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:15.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.16:29:15.75#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:15.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:15.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:15.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:15.87#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:29:15.87#ibcon#first serial, iclass 40, count 0 2006.201.16:29:15.87#ibcon#enter sib2, iclass 40, count 0 2006.201.16:29:15.87#ibcon#flushed, iclass 40, count 0 2006.201.16:29:15.87#ibcon#about to write, iclass 40, count 0 2006.201.16:29:15.87#ibcon#wrote, iclass 40, count 0 2006.201.16:29:15.87#ibcon#about to read 3, iclass 40, count 0 2006.201.16:29:15.89#ibcon#read 3, iclass 40, count 0 2006.201.16:29:15.89#ibcon#about to read 4, iclass 40, count 0 2006.201.16:29:15.89#ibcon#read 4, iclass 40, count 0 2006.201.16:29:15.89#ibcon#about to read 5, iclass 40, count 0 2006.201.16:29:15.89#ibcon#read 5, iclass 40, count 0 2006.201.16:29:15.89#ibcon#about to read 6, iclass 40, count 0 2006.201.16:29:15.89#ibcon#read 6, iclass 40, count 0 2006.201.16:29:15.89#ibcon#end of sib2, iclass 40, count 0 2006.201.16:29:15.89#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:29:15.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:29:15.89#ibcon#[25=USB\r\n] 2006.201.16:29:15.89#ibcon#*before write, iclass 40, count 0 2006.201.16:29:15.89#ibcon#enter sib2, iclass 40, count 0 2006.201.16:29:15.89#ibcon#flushed, iclass 40, count 0 2006.201.16:29:15.89#ibcon#about to write, iclass 40, count 0 2006.201.16:29:15.89#ibcon#wrote, iclass 40, count 0 2006.201.16:29:15.89#ibcon#about to read 3, iclass 40, count 0 2006.201.16:29:15.92#ibcon#read 3, iclass 40, count 0 2006.201.16:29:15.92#ibcon#about to read 4, iclass 40, count 0 2006.201.16:29:15.92#ibcon#read 4, iclass 40, count 0 2006.201.16:29:15.92#ibcon#about to read 5, iclass 40, count 0 2006.201.16:29:15.92#ibcon#read 5, iclass 40, count 0 2006.201.16:29:15.92#ibcon#about to read 6, iclass 40, count 0 2006.201.16:29:15.92#ibcon#read 6, iclass 40, count 0 2006.201.16:29:15.92#ibcon#end of sib2, iclass 40, count 0 2006.201.16:29:15.92#ibcon#*after write, iclass 40, count 0 2006.201.16:29:15.92#ibcon#*before return 0, iclass 40, count 0 2006.201.16:29:15.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:15.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:15.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:29:15.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:29:15.92$vck44/valo=7,864.99 2006.201.16:29:15.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.16:29:15.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.16:29:15.92#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:15.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:15.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:15.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:15.92#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:29:15.92#ibcon#first serial, iclass 4, count 0 2006.201.16:29:15.92#ibcon#enter sib2, iclass 4, count 0 2006.201.16:29:15.92#ibcon#flushed, iclass 4, count 0 2006.201.16:29:15.92#ibcon#about to write, iclass 4, count 0 2006.201.16:29:15.92#ibcon#wrote, iclass 4, count 0 2006.201.16:29:15.92#ibcon#about to read 3, iclass 4, count 0 2006.201.16:29:15.94#ibcon#read 3, iclass 4, count 0 2006.201.16:29:15.94#ibcon#about to read 4, iclass 4, count 0 2006.201.16:29:15.94#ibcon#read 4, iclass 4, count 0 2006.201.16:29:15.94#ibcon#about to read 5, iclass 4, count 0 2006.201.16:29:15.94#ibcon#read 5, iclass 4, count 0 2006.201.16:29:15.94#ibcon#about to read 6, iclass 4, count 0 2006.201.16:29:15.94#ibcon#read 6, iclass 4, count 0 2006.201.16:29:15.94#ibcon#end of sib2, iclass 4, count 0 2006.201.16:29:15.94#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:29:15.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:29:15.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:29:15.94#ibcon#*before write, iclass 4, count 0 2006.201.16:29:15.94#ibcon#enter sib2, iclass 4, count 0 2006.201.16:29:15.94#ibcon#flushed, iclass 4, count 0 2006.201.16:29:15.94#ibcon#about to write, iclass 4, count 0 2006.201.16:29:15.94#ibcon#wrote, iclass 4, count 0 2006.201.16:29:15.94#ibcon#about to read 3, iclass 4, count 0 2006.201.16:29:15.98#ibcon#read 3, iclass 4, count 0 2006.201.16:29:15.98#ibcon#about to read 4, iclass 4, count 0 2006.201.16:29:15.98#ibcon#read 4, iclass 4, count 0 2006.201.16:29:15.98#ibcon#about to read 5, iclass 4, count 0 2006.201.16:29:15.98#ibcon#read 5, iclass 4, count 0 2006.201.16:29:15.98#ibcon#about to read 6, iclass 4, count 0 2006.201.16:29:15.98#ibcon#read 6, iclass 4, count 0 2006.201.16:29:15.98#ibcon#end of sib2, iclass 4, count 0 2006.201.16:29:15.98#ibcon#*after write, iclass 4, count 0 2006.201.16:29:15.98#ibcon#*before return 0, iclass 4, count 0 2006.201.16:29:15.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:15.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:15.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:29:15.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:29:15.98$vck44/va=7,5 2006.201.16:29:15.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.16:29:15.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.16:29:15.98#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:15.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:16.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:16.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:16.04#ibcon#enter wrdev, iclass 6, count 2 2006.201.16:29:16.04#ibcon#first serial, iclass 6, count 2 2006.201.16:29:16.04#ibcon#enter sib2, iclass 6, count 2 2006.201.16:29:16.04#ibcon#flushed, iclass 6, count 2 2006.201.16:29:16.04#ibcon#about to write, iclass 6, count 2 2006.201.16:29:16.04#ibcon#wrote, iclass 6, count 2 2006.201.16:29:16.04#ibcon#about to read 3, iclass 6, count 2 2006.201.16:29:16.06#ibcon#read 3, iclass 6, count 2 2006.201.16:29:16.06#ibcon#about to read 4, iclass 6, count 2 2006.201.16:29:16.06#ibcon#read 4, iclass 6, count 2 2006.201.16:29:16.06#ibcon#about to read 5, iclass 6, count 2 2006.201.16:29:16.06#ibcon#read 5, iclass 6, count 2 2006.201.16:29:16.06#ibcon#about to read 6, iclass 6, count 2 2006.201.16:29:16.06#ibcon#read 6, iclass 6, count 2 2006.201.16:29:16.06#ibcon#end of sib2, iclass 6, count 2 2006.201.16:29:16.06#ibcon#*mode == 0, iclass 6, count 2 2006.201.16:29:16.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.16:29:16.06#ibcon#[25=AT07-05\r\n] 2006.201.16:29:16.06#ibcon#*before write, iclass 6, count 2 2006.201.16:29:16.06#ibcon#enter sib2, iclass 6, count 2 2006.201.16:29:16.06#ibcon#flushed, iclass 6, count 2 2006.201.16:29:16.06#ibcon#about to write, iclass 6, count 2 2006.201.16:29:16.06#ibcon#wrote, iclass 6, count 2 2006.201.16:29:16.06#ibcon#about to read 3, iclass 6, count 2 2006.201.16:29:16.09#ibcon#read 3, iclass 6, count 2 2006.201.16:29:16.09#ibcon#about to read 4, iclass 6, count 2 2006.201.16:29:16.09#ibcon#read 4, iclass 6, count 2 2006.201.16:29:16.09#ibcon#about to read 5, iclass 6, count 2 2006.201.16:29:16.09#ibcon#read 5, iclass 6, count 2 2006.201.16:29:16.09#ibcon#about to read 6, iclass 6, count 2 2006.201.16:29:16.09#ibcon#read 6, iclass 6, count 2 2006.201.16:29:16.09#ibcon#end of sib2, iclass 6, count 2 2006.201.16:29:16.09#ibcon#*after write, iclass 6, count 2 2006.201.16:29:16.09#ibcon#*before return 0, iclass 6, count 2 2006.201.16:29:16.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:16.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:16.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.16:29:16.09#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:16.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:16.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:16.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:16.21#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:29:16.21#ibcon#first serial, iclass 6, count 0 2006.201.16:29:16.21#ibcon#enter sib2, iclass 6, count 0 2006.201.16:29:16.21#ibcon#flushed, iclass 6, count 0 2006.201.16:29:16.21#ibcon#about to write, iclass 6, count 0 2006.201.16:29:16.21#ibcon#wrote, iclass 6, count 0 2006.201.16:29:16.21#ibcon#about to read 3, iclass 6, count 0 2006.201.16:29:16.23#ibcon#read 3, iclass 6, count 0 2006.201.16:29:16.23#ibcon#about to read 4, iclass 6, count 0 2006.201.16:29:16.23#ibcon#read 4, iclass 6, count 0 2006.201.16:29:16.23#ibcon#about to read 5, iclass 6, count 0 2006.201.16:29:16.23#ibcon#read 5, iclass 6, count 0 2006.201.16:29:16.23#ibcon#about to read 6, iclass 6, count 0 2006.201.16:29:16.23#ibcon#read 6, iclass 6, count 0 2006.201.16:29:16.23#ibcon#end of sib2, iclass 6, count 0 2006.201.16:29:16.23#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:29:16.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:29:16.23#ibcon#[25=USB\r\n] 2006.201.16:29:16.23#ibcon#*before write, iclass 6, count 0 2006.201.16:29:16.23#ibcon#enter sib2, iclass 6, count 0 2006.201.16:29:16.23#ibcon#flushed, iclass 6, count 0 2006.201.16:29:16.23#ibcon#about to write, iclass 6, count 0 2006.201.16:29:16.23#ibcon#wrote, iclass 6, count 0 2006.201.16:29:16.23#ibcon#about to read 3, iclass 6, count 0 2006.201.16:29:16.26#ibcon#read 3, iclass 6, count 0 2006.201.16:29:16.26#ibcon#about to read 4, iclass 6, count 0 2006.201.16:29:16.26#ibcon#read 4, iclass 6, count 0 2006.201.16:29:16.26#ibcon#about to read 5, iclass 6, count 0 2006.201.16:29:16.26#ibcon#read 5, iclass 6, count 0 2006.201.16:29:16.26#ibcon#about to read 6, iclass 6, count 0 2006.201.16:29:16.26#ibcon#read 6, iclass 6, count 0 2006.201.16:29:16.26#ibcon#end of sib2, iclass 6, count 0 2006.201.16:29:16.26#ibcon#*after write, iclass 6, count 0 2006.201.16:29:16.26#ibcon#*before return 0, iclass 6, count 0 2006.201.16:29:16.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:16.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:16.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:29:16.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:29:16.26$vck44/valo=8,884.99 2006.201.16:29:16.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.16:29:16.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.16:29:16.26#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:16.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:16.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:16.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:16.26#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:29:16.26#ibcon#first serial, iclass 10, count 0 2006.201.16:29:16.26#ibcon#enter sib2, iclass 10, count 0 2006.201.16:29:16.26#ibcon#flushed, iclass 10, count 0 2006.201.16:29:16.26#ibcon#about to write, iclass 10, count 0 2006.201.16:29:16.26#ibcon#wrote, iclass 10, count 0 2006.201.16:29:16.26#ibcon#about to read 3, iclass 10, count 0 2006.201.16:29:16.28#ibcon#read 3, iclass 10, count 0 2006.201.16:29:16.28#ibcon#about to read 4, iclass 10, count 0 2006.201.16:29:16.28#ibcon#read 4, iclass 10, count 0 2006.201.16:29:16.28#ibcon#about to read 5, iclass 10, count 0 2006.201.16:29:16.28#ibcon#read 5, iclass 10, count 0 2006.201.16:29:16.28#ibcon#about to read 6, iclass 10, count 0 2006.201.16:29:16.28#ibcon#read 6, iclass 10, count 0 2006.201.16:29:16.28#ibcon#end of sib2, iclass 10, count 0 2006.201.16:29:16.28#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:29:16.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:29:16.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:29:16.28#ibcon#*before write, iclass 10, count 0 2006.201.16:29:16.28#ibcon#enter sib2, iclass 10, count 0 2006.201.16:29:16.28#ibcon#flushed, iclass 10, count 0 2006.201.16:29:16.28#ibcon#about to write, iclass 10, count 0 2006.201.16:29:16.28#ibcon#wrote, iclass 10, count 0 2006.201.16:29:16.28#ibcon#about to read 3, iclass 10, count 0 2006.201.16:29:16.32#ibcon#read 3, iclass 10, count 0 2006.201.16:29:16.32#ibcon#about to read 4, iclass 10, count 0 2006.201.16:29:16.32#ibcon#read 4, iclass 10, count 0 2006.201.16:29:16.32#ibcon#about to read 5, iclass 10, count 0 2006.201.16:29:16.32#ibcon#read 5, iclass 10, count 0 2006.201.16:29:16.32#ibcon#about to read 6, iclass 10, count 0 2006.201.16:29:16.32#ibcon#read 6, iclass 10, count 0 2006.201.16:29:16.32#ibcon#end of sib2, iclass 10, count 0 2006.201.16:29:16.32#ibcon#*after write, iclass 10, count 0 2006.201.16:29:16.32#ibcon#*before return 0, iclass 10, count 0 2006.201.16:29:16.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:16.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:16.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:29:16.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:29:16.32$vck44/va=8,4 2006.201.16:29:16.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.16:29:16.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.16:29:16.32#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:16.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:29:16.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:29:16.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:29:16.38#ibcon#enter wrdev, iclass 12, count 2 2006.201.16:29:16.38#ibcon#first serial, iclass 12, count 2 2006.201.16:29:16.38#ibcon#enter sib2, iclass 12, count 2 2006.201.16:29:16.38#ibcon#flushed, iclass 12, count 2 2006.201.16:29:16.38#ibcon#about to write, iclass 12, count 2 2006.201.16:29:16.38#ibcon#wrote, iclass 12, count 2 2006.201.16:29:16.38#ibcon#about to read 3, iclass 12, count 2 2006.201.16:29:16.40#ibcon#read 3, iclass 12, count 2 2006.201.16:29:16.40#ibcon#about to read 4, iclass 12, count 2 2006.201.16:29:16.40#ibcon#read 4, iclass 12, count 2 2006.201.16:29:16.40#ibcon#about to read 5, iclass 12, count 2 2006.201.16:29:16.40#ibcon#read 5, iclass 12, count 2 2006.201.16:29:16.40#ibcon#about to read 6, iclass 12, count 2 2006.201.16:29:16.40#ibcon#read 6, iclass 12, count 2 2006.201.16:29:16.40#ibcon#end of sib2, iclass 12, count 2 2006.201.16:29:16.40#ibcon#*mode == 0, iclass 12, count 2 2006.201.16:29:16.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.16:29:16.40#ibcon#[25=AT08-04\r\n] 2006.201.16:29:16.40#ibcon#*before write, iclass 12, count 2 2006.201.16:29:16.40#ibcon#enter sib2, iclass 12, count 2 2006.201.16:29:16.40#ibcon#flushed, iclass 12, count 2 2006.201.16:29:16.40#ibcon#about to write, iclass 12, count 2 2006.201.16:29:16.40#ibcon#wrote, iclass 12, count 2 2006.201.16:29:16.40#ibcon#about to read 3, iclass 12, count 2 2006.201.16:29:16.43#ibcon#read 3, iclass 12, count 2 2006.201.16:29:16.43#ibcon#about to read 4, iclass 12, count 2 2006.201.16:29:16.43#ibcon#read 4, iclass 12, count 2 2006.201.16:29:16.43#ibcon#about to read 5, iclass 12, count 2 2006.201.16:29:16.43#ibcon#read 5, iclass 12, count 2 2006.201.16:29:16.43#ibcon#about to read 6, iclass 12, count 2 2006.201.16:29:16.43#ibcon#read 6, iclass 12, count 2 2006.201.16:29:16.43#ibcon#end of sib2, iclass 12, count 2 2006.201.16:29:16.43#ibcon#*after write, iclass 12, count 2 2006.201.16:29:16.43#ibcon#*before return 0, iclass 12, count 2 2006.201.16:29:16.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:29:16.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:29:16.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.16:29:16.43#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:16.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:29:16.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:29:16.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:29:16.55#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:29:16.55#ibcon#first serial, iclass 12, count 0 2006.201.16:29:16.55#ibcon#enter sib2, iclass 12, count 0 2006.201.16:29:16.55#ibcon#flushed, iclass 12, count 0 2006.201.16:29:16.55#ibcon#about to write, iclass 12, count 0 2006.201.16:29:16.55#ibcon#wrote, iclass 12, count 0 2006.201.16:29:16.55#ibcon#about to read 3, iclass 12, count 0 2006.201.16:29:16.57#ibcon#read 3, iclass 12, count 0 2006.201.16:29:16.57#ibcon#about to read 4, iclass 12, count 0 2006.201.16:29:16.57#ibcon#read 4, iclass 12, count 0 2006.201.16:29:16.57#ibcon#about to read 5, iclass 12, count 0 2006.201.16:29:16.57#ibcon#read 5, iclass 12, count 0 2006.201.16:29:16.57#ibcon#about to read 6, iclass 12, count 0 2006.201.16:29:16.57#ibcon#read 6, iclass 12, count 0 2006.201.16:29:16.57#ibcon#end of sib2, iclass 12, count 0 2006.201.16:29:16.57#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:29:16.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:29:16.57#ibcon#[25=USB\r\n] 2006.201.16:29:16.57#ibcon#*before write, iclass 12, count 0 2006.201.16:29:16.57#ibcon#enter sib2, iclass 12, count 0 2006.201.16:29:16.57#ibcon#flushed, iclass 12, count 0 2006.201.16:29:16.57#ibcon#about to write, iclass 12, count 0 2006.201.16:29:16.57#ibcon#wrote, iclass 12, count 0 2006.201.16:29:16.57#ibcon#about to read 3, iclass 12, count 0 2006.201.16:29:16.60#ibcon#read 3, iclass 12, count 0 2006.201.16:29:16.60#ibcon#about to read 4, iclass 12, count 0 2006.201.16:29:16.60#ibcon#read 4, iclass 12, count 0 2006.201.16:29:16.60#ibcon#about to read 5, iclass 12, count 0 2006.201.16:29:16.60#ibcon#read 5, iclass 12, count 0 2006.201.16:29:16.60#ibcon#about to read 6, iclass 12, count 0 2006.201.16:29:16.60#ibcon#read 6, iclass 12, count 0 2006.201.16:29:16.60#ibcon#end of sib2, iclass 12, count 0 2006.201.16:29:16.60#ibcon#*after write, iclass 12, count 0 2006.201.16:29:16.60#ibcon#*before return 0, iclass 12, count 0 2006.201.16:29:16.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:29:16.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:29:16.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:29:16.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:29:16.60$vck44/vblo=1,629.99 2006.201.16:29:16.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.16:29:16.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.16:29:16.60#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:16.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:29:16.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:29:16.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:29:16.60#ibcon#enter wrdev, iclass 14, count 0 2006.201.16:29:16.60#ibcon#first serial, iclass 14, count 0 2006.201.16:29:16.60#ibcon#enter sib2, iclass 14, count 0 2006.201.16:29:16.60#ibcon#flushed, iclass 14, count 0 2006.201.16:29:16.60#ibcon#about to write, iclass 14, count 0 2006.201.16:29:16.60#ibcon#wrote, iclass 14, count 0 2006.201.16:29:16.60#ibcon#about to read 3, iclass 14, count 0 2006.201.16:29:16.62#ibcon#read 3, iclass 14, count 0 2006.201.16:29:16.62#ibcon#about to read 4, iclass 14, count 0 2006.201.16:29:16.62#ibcon#read 4, iclass 14, count 0 2006.201.16:29:16.62#ibcon#about to read 5, iclass 14, count 0 2006.201.16:29:16.62#ibcon#read 5, iclass 14, count 0 2006.201.16:29:16.62#ibcon#about to read 6, iclass 14, count 0 2006.201.16:29:16.62#ibcon#read 6, iclass 14, count 0 2006.201.16:29:16.62#ibcon#end of sib2, iclass 14, count 0 2006.201.16:29:16.62#ibcon#*mode == 0, iclass 14, count 0 2006.201.16:29:16.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.16:29:16.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:29:16.62#ibcon#*before write, iclass 14, count 0 2006.201.16:29:16.62#ibcon#enter sib2, iclass 14, count 0 2006.201.16:29:16.62#ibcon#flushed, iclass 14, count 0 2006.201.16:29:16.62#ibcon#about to write, iclass 14, count 0 2006.201.16:29:16.62#ibcon#wrote, iclass 14, count 0 2006.201.16:29:16.62#ibcon#about to read 3, iclass 14, count 0 2006.201.16:29:16.67#ibcon#read 3, iclass 14, count 0 2006.201.16:29:16.67#ibcon#about to read 4, iclass 14, count 0 2006.201.16:29:16.67#ibcon#read 4, iclass 14, count 0 2006.201.16:29:16.67#ibcon#about to read 5, iclass 14, count 0 2006.201.16:29:16.67#ibcon#read 5, iclass 14, count 0 2006.201.16:29:16.67#ibcon#about to read 6, iclass 14, count 0 2006.201.16:29:16.67#ibcon#read 6, iclass 14, count 0 2006.201.16:29:16.67#ibcon#end of sib2, iclass 14, count 0 2006.201.16:29:16.67#ibcon#*after write, iclass 14, count 0 2006.201.16:29:16.67#ibcon#*before return 0, iclass 14, count 0 2006.201.16:29:16.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:29:16.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:29:16.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.16:29:16.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.16:29:16.67$vck44/vb=1,4 2006.201.16:29:16.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.16:29:16.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.16:29:16.67#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:16.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:29:16.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:29:16.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:29:16.67#ibcon#enter wrdev, iclass 16, count 2 2006.201.16:29:16.67#ibcon#first serial, iclass 16, count 2 2006.201.16:29:16.67#ibcon#enter sib2, iclass 16, count 2 2006.201.16:29:16.67#ibcon#flushed, iclass 16, count 2 2006.201.16:29:16.67#ibcon#about to write, iclass 16, count 2 2006.201.16:29:16.67#ibcon#wrote, iclass 16, count 2 2006.201.16:29:16.67#ibcon#about to read 3, iclass 16, count 2 2006.201.16:29:16.69#ibcon#read 3, iclass 16, count 2 2006.201.16:29:16.69#ibcon#about to read 4, iclass 16, count 2 2006.201.16:29:16.69#ibcon#read 4, iclass 16, count 2 2006.201.16:29:16.69#ibcon#about to read 5, iclass 16, count 2 2006.201.16:29:16.69#ibcon#read 5, iclass 16, count 2 2006.201.16:29:16.69#ibcon#about to read 6, iclass 16, count 2 2006.201.16:29:16.69#ibcon#read 6, iclass 16, count 2 2006.201.16:29:16.69#ibcon#end of sib2, iclass 16, count 2 2006.201.16:29:16.69#ibcon#*mode == 0, iclass 16, count 2 2006.201.16:29:16.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.16:29:16.69#ibcon#[27=AT01-04\r\n] 2006.201.16:29:16.69#ibcon#*before write, iclass 16, count 2 2006.201.16:29:16.69#ibcon#enter sib2, iclass 16, count 2 2006.201.16:29:16.69#ibcon#flushed, iclass 16, count 2 2006.201.16:29:16.69#ibcon#about to write, iclass 16, count 2 2006.201.16:29:16.69#ibcon#wrote, iclass 16, count 2 2006.201.16:29:16.69#ibcon#about to read 3, iclass 16, count 2 2006.201.16:29:16.72#ibcon#read 3, iclass 16, count 2 2006.201.16:29:16.72#ibcon#about to read 4, iclass 16, count 2 2006.201.16:29:16.72#ibcon#read 4, iclass 16, count 2 2006.201.16:29:16.72#ibcon#about to read 5, iclass 16, count 2 2006.201.16:29:16.72#ibcon#read 5, iclass 16, count 2 2006.201.16:29:16.72#ibcon#about to read 6, iclass 16, count 2 2006.201.16:29:16.72#ibcon#read 6, iclass 16, count 2 2006.201.16:29:16.72#ibcon#end of sib2, iclass 16, count 2 2006.201.16:29:16.72#ibcon#*after write, iclass 16, count 2 2006.201.16:29:16.72#ibcon#*before return 0, iclass 16, count 2 2006.201.16:29:16.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:29:16.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:29:16.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.16:29:16.72#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:16.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:29:16.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:29:16.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:29:16.84#ibcon#enter wrdev, iclass 16, count 0 2006.201.16:29:16.84#ibcon#first serial, iclass 16, count 0 2006.201.16:29:16.84#ibcon#enter sib2, iclass 16, count 0 2006.201.16:29:16.84#ibcon#flushed, iclass 16, count 0 2006.201.16:29:16.84#ibcon#about to write, iclass 16, count 0 2006.201.16:29:16.84#ibcon#wrote, iclass 16, count 0 2006.201.16:29:16.84#ibcon#about to read 3, iclass 16, count 0 2006.201.16:29:16.86#ibcon#read 3, iclass 16, count 0 2006.201.16:29:16.86#ibcon#about to read 4, iclass 16, count 0 2006.201.16:29:16.86#ibcon#read 4, iclass 16, count 0 2006.201.16:29:16.86#ibcon#about to read 5, iclass 16, count 0 2006.201.16:29:16.86#ibcon#read 5, iclass 16, count 0 2006.201.16:29:16.86#ibcon#about to read 6, iclass 16, count 0 2006.201.16:29:16.86#ibcon#read 6, iclass 16, count 0 2006.201.16:29:16.86#ibcon#end of sib2, iclass 16, count 0 2006.201.16:29:16.86#ibcon#*mode == 0, iclass 16, count 0 2006.201.16:29:16.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.16:29:16.86#ibcon#[27=USB\r\n] 2006.201.16:29:16.86#ibcon#*before write, iclass 16, count 0 2006.201.16:29:16.86#ibcon#enter sib2, iclass 16, count 0 2006.201.16:29:16.86#ibcon#flushed, iclass 16, count 0 2006.201.16:29:16.86#ibcon#about to write, iclass 16, count 0 2006.201.16:29:16.86#ibcon#wrote, iclass 16, count 0 2006.201.16:29:16.86#ibcon#about to read 3, iclass 16, count 0 2006.201.16:29:16.89#ibcon#read 3, iclass 16, count 0 2006.201.16:29:16.89#ibcon#about to read 4, iclass 16, count 0 2006.201.16:29:16.89#ibcon#read 4, iclass 16, count 0 2006.201.16:29:16.89#ibcon#about to read 5, iclass 16, count 0 2006.201.16:29:16.89#ibcon#read 5, iclass 16, count 0 2006.201.16:29:16.89#ibcon#about to read 6, iclass 16, count 0 2006.201.16:29:16.89#ibcon#read 6, iclass 16, count 0 2006.201.16:29:16.89#ibcon#end of sib2, iclass 16, count 0 2006.201.16:29:16.89#ibcon#*after write, iclass 16, count 0 2006.201.16:29:16.89#ibcon#*before return 0, iclass 16, count 0 2006.201.16:29:16.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:29:16.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:29:16.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.16:29:16.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.16:29:16.89$vck44/vblo=2,634.99 2006.201.16:29:16.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.16:29:16.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.16:29:16.89#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:16.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:16.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:16.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:16.89#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:29:16.89#ibcon#first serial, iclass 18, count 0 2006.201.16:29:16.89#ibcon#enter sib2, iclass 18, count 0 2006.201.16:29:16.89#ibcon#flushed, iclass 18, count 0 2006.201.16:29:16.89#ibcon#about to write, iclass 18, count 0 2006.201.16:29:16.89#ibcon#wrote, iclass 18, count 0 2006.201.16:29:16.89#ibcon#about to read 3, iclass 18, count 0 2006.201.16:29:16.91#ibcon#read 3, iclass 18, count 0 2006.201.16:29:16.91#ibcon#about to read 4, iclass 18, count 0 2006.201.16:29:16.91#ibcon#read 4, iclass 18, count 0 2006.201.16:29:16.91#ibcon#about to read 5, iclass 18, count 0 2006.201.16:29:16.91#ibcon#read 5, iclass 18, count 0 2006.201.16:29:16.91#ibcon#about to read 6, iclass 18, count 0 2006.201.16:29:16.91#ibcon#read 6, iclass 18, count 0 2006.201.16:29:16.91#ibcon#end of sib2, iclass 18, count 0 2006.201.16:29:16.91#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:29:16.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:29:16.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:29:16.91#ibcon#*before write, iclass 18, count 0 2006.201.16:29:16.91#ibcon#enter sib2, iclass 18, count 0 2006.201.16:29:16.91#ibcon#flushed, iclass 18, count 0 2006.201.16:29:16.91#ibcon#about to write, iclass 18, count 0 2006.201.16:29:16.91#ibcon#wrote, iclass 18, count 0 2006.201.16:29:16.91#ibcon#about to read 3, iclass 18, count 0 2006.201.16:29:16.95#ibcon#read 3, iclass 18, count 0 2006.201.16:29:16.95#ibcon#about to read 4, iclass 18, count 0 2006.201.16:29:16.95#ibcon#read 4, iclass 18, count 0 2006.201.16:29:16.95#ibcon#about to read 5, iclass 18, count 0 2006.201.16:29:16.95#ibcon#read 5, iclass 18, count 0 2006.201.16:29:16.95#ibcon#about to read 6, iclass 18, count 0 2006.201.16:29:16.95#ibcon#read 6, iclass 18, count 0 2006.201.16:29:16.95#ibcon#end of sib2, iclass 18, count 0 2006.201.16:29:16.95#ibcon#*after write, iclass 18, count 0 2006.201.16:29:16.95#ibcon#*before return 0, iclass 18, count 0 2006.201.16:29:16.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:16.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:29:16.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:29:16.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:29:16.95$vck44/vb=2,5 2006.201.16:29:16.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.16:29:16.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.16:29:16.95#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:16.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:17.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:17.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:17.01#ibcon#enter wrdev, iclass 20, count 2 2006.201.16:29:17.01#ibcon#first serial, iclass 20, count 2 2006.201.16:29:17.01#ibcon#enter sib2, iclass 20, count 2 2006.201.16:29:17.01#ibcon#flushed, iclass 20, count 2 2006.201.16:29:17.01#ibcon#about to write, iclass 20, count 2 2006.201.16:29:17.01#ibcon#wrote, iclass 20, count 2 2006.201.16:29:17.01#ibcon#about to read 3, iclass 20, count 2 2006.201.16:29:17.03#ibcon#read 3, iclass 20, count 2 2006.201.16:29:17.03#ibcon#about to read 4, iclass 20, count 2 2006.201.16:29:17.03#ibcon#read 4, iclass 20, count 2 2006.201.16:29:17.03#ibcon#about to read 5, iclass 20, count 2 2006.201.16:29:17.03#ibcon#read 5, iclass 20, count 2 2006.201.16:29:17.03#ibcon#about to read 6, iclass 20, count 2 2006.201.16:29:17.03#ibcon#read 6, iclass 20, count 2 2006.201.16:29:17.03#ibcon#end of sib2, iclass 20, count 2 2006.201.16:29:17.03#ibcon#*mode == 0, iclass 20, count 2 2006.201.16:29:17.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.16:29:17.03#ibcon#[27=AT02-05\r\n] 2006.201.16:29:17.03#ibcon#*before write, iclass 20, count 2 2006.201.16:29:17.03#ibcon#enter sib2, iclass 20, count 2 2006.201.16:29:17.03#ibcon#flushed, iclass 20, count 2 2006.201.16:29:17.03#ibcon#about to write, iclass 20, count 2 2006.201.16:29:17.03#ibcon#wrote, iclass 20, count 2 2006.201.16:29:17.03#ibcon#about to read 3, iclass 20, count 2 2006.201.16:29:17.06#ibcon#read 3, iclass 20, count 2 2006.201.16:29:17.06#ibcon#about to read 4, iclass 20, count 2 2006.201.16:29:17.06#ibcon#read 4, iclass 20, count 2 2006.201.16:29:17.06#ibcon#about to read 5, iclass 20, count 2 2006.201.16:29:17.06#ibcon#read 5, iclass 20, count 2 2006.201.16:29:17.06#ibcon#about to read 6, iclass 20, count 2 2006.201.16:29:17.06#ibcon#read 6, iclass 20, count 2 2006.201.16:29:17.06#ibcon#end of sib2, iclass 20, count 2 2006.201.16:29:17.06#ibcon#*after write, iclass 20, count 2 2006.201.16:29:17.06#ibcon#*before return 0, iclass 20, count 2 2006.201.16:29:17.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:17.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:29:17.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.16:29:17.06#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:17.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:17.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:17.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:17.18#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:29:17.18#ibcon#first serial, iclass 20, count 0 2006.201.16:29:17.18#ibcon#enter sib2, iclass 20, count 0 2006.201.16:29:17.18#ibcon#flushed, iclass 20, count 0 2006.201.16:29:17.18#ibcon#about to write, iclass 20, count 0 2006.201.16:29:17.18#ibcon#wrote, iclass 20, count 0 2006.201.16:29:17.18#ibcon#about to read 3, iclass 20, count 0 2006.201.16:29:17.20#ibcon#read 3, iclass 20, count 0 2006.201.16:29:17.20#ibcon#about to read 4, iclass 20, count 0 2006.201.16:29:17.20#ibcon#read 4, iclass 20, count 0 2006.201.16:29:17.20#ibcon#about to read 5, iclass 20, count 0 2006.201.16:29:17.20#ibcon#read 5, iclass 20, count 0 2006.201.16:29:17.20#ibcon#about to read 6, iclass 20, count 0 2006.201.16:29:17.20#ibcon#read 6, iclass 20, count 0 2006.201.16:29:17.20#ibcon#end of sib2, iclass 20, count 0 2006.201.16:29:17.20#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:29:17.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:29:17.20#ibcon#[27=USB\r\n] 2006.201.16:29:17.20#ibcon#*before write, iclass 20, count 0 2006.201.16:29:17.20#ibcon#enter sib2, iclass 20, count 0 2006.201.16:29:17.20#ibcon#flushed, iclass 20, count 0 2006.201.16:29:17.20#ibcon#about to write, iclass 20, count 0 2006.201.16:29:17.20#ibcon#wrote, iclass 20, count 0 2006.201.16:29:17.20#ibcon#about to read 3, iclass 20, count 0 2006.201.16:29:17.23#ibcon#read 3, iclass 20, count 0 2006.201.16:29:17.23#ibcon#about to read 4, iclass 20, count 0 2006.201.16:29:17.23#ibcon#read 4, iclass 20, count 0 2006.201.16:29:17.23#ibcon#about to read 5, iclass 20, count 0 2006.201.16:29:17.23#ibcon#read 5, iclass 20, count 0 2006.201.16:29:17.23#ibcon#about to read 6, iclass 20, count 0 2006.201.16:29:17.23#ibcon#read 6, iclass 20, count 0 2006.201.16:29:17.23#ibcon#end of sib2, iclass 20, count 0 2006.201.16:29:17.23#ibcon#*after write, iclass 20, count 0 2006.201.16:29:17.23#ibcon#*before return 0, iclass 20, count 0 2006.201.16:29:17.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:17.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:29:17.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:29:17.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:29:17.23$vck44/vblo=3,649.99 2006.201.16:29:17.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.16:29:17.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.16:29:17.23#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:17.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:17.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:17.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:17.23#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:29:17.23#ibcon#first serial, iclass 22, count 0 2006.201.16:29:17.23#ibcon#enter sib2, iclass 22, count 0 2006.201.16:29:17.23#ibcon#flushed, iclass 22, count 0 2006.201.16:29:17.23#ibcon#about to write, iclass 22, count 0 2006.201.16:29:17.23#ibcon#wrote, iclass 22, count 0 2006.201.16:29:17.23#ibcon#about to read 3, iclass 22, count 0 2006.201.16:29:17.25#ibcon#read 3, iclass 22, count 0 2006.201.16:29:17.25#ibcon#about to read 4, iclass 22, count 0 2006.201.16:29:17.25#ibcon#read 4, iclass 22, count 0 2006.201.16:29:17.25#ibcon#about to read 5, iclass 22, count 0 2006.201.16:29:17.25#ibcon#read 5, iclass 22, count 0 2006.201.16:29:17.25#ibcon#about to read 6, iclass 22, count 0 2006.201.16:29:17.25#ibcon#read 6, iclass 22, count 0 2006.201.16:29:17.25#ibcon#end of sib2, iclass 22, count 0 2006.201.16:29:17.25#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:29:17.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:29:17.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:29:17.25#ibcon#*before write, iclass 22, count 0 2006.201.16:29:17.25#ibcon#enter sib2, iclass 22, count 0 2006.201.16:29:17.25#ibcon#flushed, iclass 22, count 0 2006.201.16:29:17.25#ibcon#about to write, iclass 22, count 0 2006.201.16:29:17.25#ibcon#wrote, iclass 22, count 0 2006.201.16:29:17.25#ibcon#about to read 3, iclass 22, count 0 2006.201.16:29:17.30#ibcon#read 3, iclass 22, count 0 2006.201.16:29:17.30#ibcon#about to read 4, iclass 22, count 0 2006.201.16:29:17.30#ibcon#read 4, iclass 22, count 0 2006.201.16:29:17.30#ibcon#about to read 5, iclass 22, count 0 2006.201.16:29:17.30#ibcon#read 5, iclass 22, count 0 2006.201.16:29:17.30#ibcon#about to read 6, iclass 22, count 0 2006.201.16:29:17.30#ibcon#read 6, iclass 22, count 0 2006.201.16:29:17.30#ibcon#end of sib2, iclass 22, count 0 2006.201.16:29:17.30#ibcon#*after write, iclass 22, count 0 2006.201.16:29:17.30#ibcon#*before return 0, iclass 22, count 0 2006.201.16:29:17.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:17.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:29:17.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:29:17.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:29:17.30$vck44/vb=3,4 2006.201.16:29:17.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.16:29:17.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.16:29:17.30#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:17.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:17.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:17.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:17.35#ibcon#enter wrdev, iclass 24, count 2 2006.201.16:29:17.35#ibcon#first serial, iclass 24, count 2 2006.201.16:29:17.35#ibcon#enter sib2, iclass 24, count 2 2006.201.16:29:17.35#ibcon#flushed, iclass 24, count 2 2006.201.16:29:17.35#ibcon#about to write, iclass 24, count 2 2006.201.16:29:17.35#ibcon#wrote, iclass 24, count 2 2006.201.16:29:17.35#ibcon#about to read 3, iclass 24, count 2 2006.201.16:29:17.37#ibcon#read 3, iclass 24, count 2 2006.201.16:29:17.37#ibcon#about to read 4, iclass 24, count 2 2006.201.16:29:17.37#ibcon#read 4, iclass 24, count 2 2006.201.16:29:17.37#ibcon#about to read 5, iclass 24, count 2 2006.201.16:29:17.37#ibcon#read 5, iclass 24, count 2 2006.201.16:29:17.37#ibcon#about to read 6, iclass 24, count 2 2006.201.16:29:17.37#ibcon#read 6, iclass 24, count 2 2006.201.16:29:17.37#ibcon#end of sib2, iclass 24, count 2 2006.201.16:29:17.37#ibcon#*mode == 0, iclass 24, count 2 2006.201.16:29:17.37#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.16:29:17.37#ibcon#[27=AT03-04\r\n] 2006.201.16:29:17.37#ibcon#*before write, iclass 24, count 2 2006.201.16:29:17.37#ibcon#enter sib2, iclass 24, count 2 2006.201.16:29:17.37#ibcon#flushed, iclass 24, count 2 2006.201.16:29:17.37#ibcon#about to write, iclass 24, count 2 2006.201.16:29:17.37#ibcon#wrote, iclass 24, count 2 2006.201.16:29:17.37#ibcon#about to read 3, iclass 24, count 2 2006.201.16:29:17.40#ibcon#read 3, iclass 24, count 2 2006.201.16:29:17.40#ibcon#about to read 4, iclass 24, count 2 2006.201.16:29:17.40#ibcon#read 4, iclass 24, count 2 2006.201.16:29:17.40#ibcon#about to read 5, iclass 24, count 2 2006.201.16:29:17.40#ibcon#read 5, iclass 24, count 2 2006.201.16:29:17.40#ibcon#about to read 6, iclass 24, count 2 2006.201.16:29:17.40#ibcon#read 6, iclass 24, count 2 2006.201.16:29:17.40#ibcon#end of sib2, iclass 24, count 2 2006.201.16:29:17.40#ibcon#*after write, iclass 24, count 2 2006.201.16:29:17.40#ibcon#*before return 0, iclass 24, count 2 2006.201.16:29:17.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:17.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:29:17.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.16:29:17.40#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:17.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:17.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:17.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:17.52#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:29:17.52#ibcon#first serial, iclass 24, count 0 2006.201.16:29:17.52#ibcon#enter sib2, iclass 24, count 0 2006.201.16:29:17.52#ibcon#flushed, iclass 24, count 0 2006.201.16:29:17.52#ibcon#about to write, iclass 24, count 0 2006.201.16:29:17.52#ibcon#wrote, iclass 24, count 0 2006.201.16:29:17.52#ibcon#about to read 3, iclass 24, count 0 2006.201.16:29:17.54#ibcon#read 3, iclass 24, count 0 2006.201.16:29:17.54#ibcon#about to read 4, iclass 24, count 0 2006.201.16:29:17.54#ibcon#read 4, iclass 24, count 0 2006.201.16:29:17.54#ibcon#about to read 5, iclass 24, count 0 2006.201.16:29:17.54#ibcon#read 5, iclass 24, count 0 2006.201.16:29:17.54#ibcon#about to read 6, iclass 24, count 0 2006.201.16:29:17.54#ibcon#read 6, iclass 24, count 0 2006.201.16:29:17.54#ibcon#end of sib2, iclass 24, count 0 2006.201.16:29:17.54#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:29:17.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:29:17.54#ibcon#[27=USB\r\n] 2006.201.16:29:17.54#ibcon#*before write, iclass 24, count 0 2006.201.16:29:17.54#ibcon#enter sib2, iclass 24, count 0 2006.201.16:29:17.54#ibcon#flushed, iclass 24, count 0 2006.201.16:29:17.54#ibcon#about to write, iclass 24, count 0 2006.201.16:29:17.54#ibcon#wrote, iclass 24, count 0 2006.201.16:29:17.54#ibcon#about to read 3, iclass 24, count 0 2006.201.16:29:17.57#ibcon#read 3, iclass 24, count 0 2006.201.16:29:17.57#ibcon#about to read 4, iclass 24, count 0 2006.201.16:29:17.57#ibcon#read 4, iclass 24, count 0 2006.201.16:29:17.57#ibcon#about to read 5, iclass 24, count 0 2006.201.16:29:17.57#ibcon#read 5, iclass 24, count 0 2006.201.16:29:17.57#ibcon#about to read 6, iclass 24, count 0 2006.201.16:29:17.57#ibcon#read 6, iclass 24, count 0 2006.201.16:29:17.57#ibcon#end of sib2, iclass 24, count 0 2006.201.16:29:17.57#ibcon#*after write, iclass 24, count 0 2006.201.16:29:17.57#ibcon#*before return 0, iclass 24, count 0 2006.201.16:29:17.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:17.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:29:17.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:29:17.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:29:17.57$vck44/vblo=4,679.99 2006.201.16:29:17.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.16:29:17.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.16:29:17.57#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:17.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:17.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:17.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:17.57#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:29:17.57#ibcon#first serial, iclass 26, count 0 2006.201.16:29:17.57#ibcon#enter sib2, iclass 26, count 0 2006.201.16:29:17.57#ibcon#flushed, iclass 26, count 0 2006.201.16:29:17.57#ibcon#about to write, iclass 26, count 0 2006.201.16:29:17.57#ibcon#wrote, iclass 26, count 0 2006.201.16:29:17.57#ibcon#about to read 3, iclass 26, count 0 2006.201.16:29:17.59#ibcon#read 3, iclass 26, count 0 2006.201.16:29:17.59#ibcon#about to read 4, iclass 26, count 0 2006.201.16:29:17.59#ibcon#read 4, iclass 26, count 0 2006.201.16:29:17.59#ibcon#about to read 5, iclass 26, count 0 2006.201.16:29:17.59#ibcon#read 5, iclass 26, count 0 2006.201.16:29:17.59#ibcon#about to read 6, iclass 26, count 0 2006.201.16:29:17.59#ibcon#read 6, iclass 26, count 0 2006.201.16:29:17.59#ibcon#end of sib2, iclass 26, count 0 2006.201.16:29:17.59#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:29:17.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:29:17.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:29:17.59#ibcon#*before write, iclass 26, count 0 2006.201.16:29:17.59#ibcon#enter sib2, iclass 26, count 0 2006.201.16:29:17.59#ibcon#flushed, iclass 26, count 0 2006.201.16:29:17.59#ibcon#about to write, iclass 26, count 0 2006.201.16:29:17.59#ibcon#wrote, iclass 26, count 0 2006.201.16:29:17.59#ibcon#about to read 3, iclass 26, count 0 2006.201.16:29:17.63#ibcon#read 3, iclass 26, count 0 2006.201.16:29:17.63#ibcon#about to read 4, iclass 26, count 0 2006.201.16:29:17.63#ibcon#read 4, iclass 26, count 0 2006.201.16:29:17.63#ibcon#about to read 5, iclass 26, count 0 2006.201.16:29:17.63#ibcon#read 5, iclass 26, count 0 2006.201.16:29:17.63#ibcon#about to read 6, iclass 26, count 0 2006.201.16:29:17.63#ibcon#read 6, iclass 26, count 0 2006.201.16:29:17.63#ibcon#end of sib2, iclass 26, count 0 2006.201.16:29:17.63#ibcon#*after write, iclass 26, count 0 2006.201.16:29:17.63#ibcon#*before return 0, iclass 26, count 0 2006.201.16:29:17.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:17.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:29:17.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:29:17.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:29:17.63$vck44/vb=4,5 2006.201.16:29:17.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.16:29:17.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.16:29:17.63#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:17.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:17.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:17.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:17.69#ibcon#enter wrdev, iclass 28, count 2 2006.201.16:29:17.69#ibcon#first serial, iclass 28, count 2 2006.201.16:29:17.69#ibcon#enter sib2, iclass 28, count 2 2006.201.16:29:17.69#ibcon#flushed, iclass 28, count 2 2006.201.16:29:17.69#ibcon#about to write, iclass 28, count 2 2006.201.16:29:17.69#ibcon#wrote, iclass 28, count 2 2006.201.16:29:17.69#ibcon#about to read 3, iclass 28, count 2 2006.201.16:29:17.71#ibcon#read 3, iclass 28, count 2 2006.201.16:29:17.71#ibcon#about to read 4, iclass 28, count 2 2006.201.16:29:17.71#ibcon#read 4, iclass 28, count 2 2006.201.16:29:17.71#ibcon#about to read 5, iclass 28, count 2 2006.201.16:29:17.71#ibcon#read 5, iclass 28, count 2 2006.201.16:29:17.71#ibcon#about to read 6, iclass 28, count 2 2006.201.16:29:17.71#ibcon#read 6, iclass 28, count 2 2006.201.16:29:17.71#ibcon#end of sib2, iclass 28, count 2 2006.201.16:29:17.71#ibcon#*mode == 0, iclass 28, count 2 2006.201.16:29:17.71#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.16:29:17.71#ibcon#[27=AT04-05\r\n] 2006.201.16:29:17.71#ibcon#*before write, iclass 28, count 2 2006.201.16:29:17.71#ibcon#enter sib2, iclass 28, count 2 2006.201.16:29:17.71#ibcon#flushed, iclass 28, count 2 2006.201.16:29:17.71#ibcon#about to write, iclass 28, count 2 2006.201.16:29:17.71#ibcon#wrote, iclass 28, count 2 2006.201.16:29:17.71#ibcon#about to read 3, iclass 28, count 2 2006.201.16:29:17.74#ibcon#read 3, iclass 28, count 2 2006.201.16:29:17.74#ibcon#about to read 4, iclass 28, count 2 2006.201.16:29:17.74#ibcon#read 4, iclass 28, count 2 2006.201.16:29:17.74#ibcon#about to read 5, iclass 28, count 2 2006.201.16:29:17.74#ibcon#read 5, iclass 28, count 2 2006.201.16:29:17.74#ibcon#about to read 6, iclass 28, count 2 2006.201.16:29:17.74#ibcon#read 6, iclass 28, count 2 2006.201.16:29:17.74#ibcon#end of sib2, iclass 28, count 2 2006.201.16:29:17.74#ibcon#*after write, iclass 28, count 2 2006.201.16:29:17.74#ibcon#*before return 0, iclass 28, count 2 2006.201.16:29:17.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:17.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:29:17.74#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.16:29:17.74#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:17.74#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:17.86#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:17.86#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:17.86#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:29:17.86#ibcon#first serial, iclass 28, count 0 2006.201.16:29:17.86#ibcon#enter sib2, iclass 28, count 0 2006.201.16:29:17.86#ibcon#flushed, iclass 28, count 0 2006.201.16:29:17.86#ibcon#about to write, iclass 28, count 0 2006.201.16:29:17.86#ibcon#wrote, iclass 28, count 0 2006.201.16:29:17.86#ibcon#about to read 3, iclass 28, count 0 2006.201.16:29:17.88#ibcon#read 3, iclass 28, count 0 2006.201.16:29:17.88#ibcon#about to read 4, iclass 28, count 0 2006.201.16:29:17.88#ibcon#read 4, iclass 28, count 0 2006.201.16:29:17.88#ibcon#about to read 5, iclass 28, count 0 2006.201.16:29:17.88#ibcon#read 5, iclass 28, count 0 2006.201.16:29:17.88#ibcon#about to read 6, iclass 28, count 0 2006.201.16:29:17.88#ibcon#read 6, iclass 28, count 0 2006.201.16:29:17.88#ibcon#end of sib2, iclass 28, count 0 2006.201.16:29:17.88#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:29:17.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:29:17.88#ibcon#[27=USB\r\n] 2006.201.16:29:17.88#ibcon#*before write, iclass 28, count 0 2006.201.16:29:17.88#ibcon#enter sib2, iclass 28, count 0 2006.201.16:29:17.88#ibcon#flushed, iclass 28, count 0 2006.201.16:29:17.88#ibcon#about to write, iclass 28, count 0 2006.201.16:29:17.88#ibcon#wrote, iclass 28, count 0 2006.201.16:29:17.88#ibcon#about to read 3, iclass 28, count 0 2006.201.16:29:17.91#ibcon#read 3, iclass 28, count 0 2006.201.16:29:17.91#ibcon#about to read 4, iclass 28, count 0 2006.201.16:29:17.91#ibcon#read 4, iclass 28, count 0 2006.201.16:29:17.91#ibcon#about to read 5, iclass 28, count 0 2006.201.16:29:17.91#ibcon#read 5, iclass 28, count 0 2006.201.16:29:17.91#ibcon#about to read 6, iclass 28, count 0 2006.201.16:29:17.91#ibcon#read 6, iclass 28, count 0 2006.201.16:29:17.91#ibcon#end of sib2, iclass 28, count 0 2006.201.16:29:17.91#ibcon#*after write, iclass 28, count 0 2006.201.16:29:17.91#ibcon#*before return 0, iclass 28, count 0 2006.201.16:29:17.91#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:17.91#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:29:17.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:29:17.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:29:17.91$vck44/vblo=5,709.99 2006.201.16:29:17.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.16:29:17.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.16:29:17.91#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:17.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:17.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:17.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:17.91#ibcon#enter wrdev, iclass 30, count 0 2006.201.16:29:17.91#ibcon#first serial, iclass 30, count 0 2006.201.16:29:17.91#ibcon#enter sib2, iclass 30, count 0 2006.201.16:29:17.91#ibcon#flushed, iclass 30, count 0 2006.201.16:29:17.91#ibcon#about to write, iclass 30, count 0 2006.201.16:29:17.91#ibcon#wrote, iclass 30, count 0 2006.201.16:29:17.91#ibcon#about to read 3, iclass 30, count 0 2006.201.16:29:17.93#ibcon#read 3, iclass 30, count 0 2006.201.16:29:17.93#ibcon#about to read 4, iclass 30, count 0 2006.201.16:29:17.93#ibcon#read 4, iclass 30, count 0 2006.201.16:29:17.93#ibcon#about to read 5, iclass 30, count 0 2006.201.16:29:17.93#ibcon#read 5, iclass 30, count 0 2006.201.16:29:17.93#ibcon#about to read 6, iclass 30, count 0 2006.201.16:29:17.93#ibcon#read 6, iclass 30, count 0 2006.201.16:29:17.93#ibcon#end of sib2, iclass 30, count 0 2006.201.16:29:17.93#ibcon#*mode == 0, iclass 30, count 0 2006.201.16:29:17.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.16:29:17.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:29:17.93#ibcon#*before write, iclass 30, count 0 2006.201.16:29:17.93#ibcon#enter sib2, iclass 30, count 0 2006.201.16:29:17.93#ibcon#flushed, iclass 30, count 0 2006.201.16:29:17.93#ibcon#about to write, iclass 30, count 0 2006.201.16:29:17.93#ibcon#wrote, iclass 30, count 0 2006.201.16:29:17.93#ibcon#about to read 3, iclass 30, count 0 2006.201.16:29:17.97#ibcon#read 3, iclass 30, count 0 2006.201.16:29:17.97#ibcon#about to read 4, iclass 30, count 0 2006.201.16:29:17.97#ibcon#read 4, iclass 30, count 0 2006.201.16:29:17.97#ibcon#about to read 5, iclass 30, count 0 2006.201.16:29:17.97#ibcon#read 5, iclass 30, count 0 2006.201.16:29:17.97#ibcon#about to read 6, iclass 30, count 0 2006.201.16:29:17.97#ibcon#read 6, iclass 30, count 0 2006.201.16:29:17.97#ibcon#end of sib2, iclass 30, count 0 2006.201.16:29:17.97#ibcon#*after write, iclass 30, count 0 2006.201.16:29:17.97#ibcon#*before return 0, iclass 30, count 0 2006.201.16:29:17.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:17.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:29:17.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.16:29:17.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.16:29:17.97$vck44/vb=5,4 2006.201.16:29:17.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.16:29:17.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.16:29:17.97#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:17.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:18.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:18.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:18.03#ibcon#enter wrdev, iclass 32, count 2 2006.201.16:29:18.03#ibcon#first serial, iclass 32, count 2 2006.201.16:29:18.03#ibcon#enter sib2, iclass 32, count 2 2006.201.16:29:18.03#ibcon#flushed, iclass 32, count 2 2006.201.16:29:18.03#ibcon#about to write, iclass 32, count 2 2006.201.16:29:18.03#ibcon#wrote, iclass 32, count 2 2006.201.16:29:18.03#ibcon#about to read 3, iclass 32, count 2 2006.201.16:29:18.05#ibcon#read 3, iclass 32, count 2 2006.201.16:29:18.05#ibcon#about to read 4, iclass 32, count 2 2006.201.16:29:18.05#ibcon#read 4, iclass 32, count 2 2006.201.16:29:18.05#ibcon#about to read 5, iclass 32, count 2 2006.201.16:29:18.05#ibcon#read 5, iclass 32, count 2 2006.201.16:29:18.05#ibcon#about to read 6, iclass 32, count 2 2006.201.16:29:18.05#ibcon#read 6, iclass 32, count 2 2006.201.16:29:18.05#ibcon#end of sib2, iclass 32, count 2 2006.201.16:29:18.05#ibcon#*mode == 0, iclass 32, count 2 2006.201.16:29:18.05#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.16:29:18.05#ibcon#[27=AT05-04\r\n] 2006.201.16:29:18.05#ibcon#*before write, iclass 32, count 2 2006.201.16:29:18.05#ibcon#enter sib2, iclass 32, count 2 2006.201.16:29:18.05#ibcon#flushed, iclass 32, count 2 2006.201.16:29:18.05#ibcon#about to write, iclass 32, count 2 2006.201.16:29:18.05#ibcon#wrote, iclass 32, count 2 2006.201.16:29:18.05#ibcon#about to read 3, iclass 32, count 2 2006.201.16:29:18.08#ibcon#read 3, iclass 32, count 2 2006.201.16:29:18.08#ibcon#about to read 4, iclass 32, count 2 2006.201.16:29:18.08#ibcon#read 4, iclass 32, count 2 2006.201.16:29:18.08#ibcon#about to read 5, iclass 32, count 2 2006.201.16:29:18.08#ibcon#read 5, iclass 32, count 2 2006.201.16:29:18.08#ibcon#about to read 6, iclass 32, count 2 2006.201.16:29:18.08#ibcon#read 6, iclass 32, count 2 2006.201.16:29:18.08#ibcon#end of sib2, iclass 32, count 2 2006.201.16:29:18.08#ibcon#*after write, iclass 32, count 2 2006.201.16:29:18.08#ibcon#*before return 0, iclass 32, count 2 2006.201.16:29:18.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:18.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:29:18.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.16:29:18.08#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:18.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:18.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:18.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:18.20#ibcon#enter wrdev, iclass 32, count 0 2006.201.16:29:18.20#ibcon#first serial, iclass 32, count 0 2006.201.16:29:18.20#ibcon#enter sib2, iclass 32, count 0 2006.201.16:29:18.20#ibcon#flushed, iclass 32, count 0 2006.201.16:29:18.20#ibcon#about to write, iclass 32, count 0 2006.201.16:29:18.20#ibcon#wrote, iclass 32, count 0 2006.201.16:29:18.20#ibcon#about to read 3, iclass 32, count 0 2006.201.16:29:18.23#ibcon#read 3, iclass 32, count 0 2006.201.16:29:18.23#ibcon#about to read 4, iclass 32, count 0 2006.201.16:29:18.23#ibcon#read 4, iclass 32, count 0 2006.201.16:29:18.23#ibcon#about to read 5, iclass 32, count 0 2006.201.16:29:18.23#ibcon#read 5, iclass 32, count 0 2006.201.16:29:18.23#ibcon#about to read 6, iclass 32, count 0 2006.201.16:29:18.23#ibcon#read 6, iclass 32, count 0 2006.201.16:29:18.23#ibcon#end of sib2, iclass 32, count 0 2006.201.16:29:18.23#ibcon#*mode == 0, iclass 32, count 0 2006.201.16:29:18.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.16:29:18.23#ibcon#[27=USB\r\n] 2006.201.16:29:18.23#ibcon#*before write, iclass 32, count 0 2006.201.16:29:18.23#ibcon#enter sib2, iclass 32, count 0 2006.201.16:29:18.23#ibcon#flushed, iclass 32, count 0 2006.201.16:29:18.23#ibcon#about to write, iclass 32, count 0 2006.201.16:29:18.23#ibcon#wrote, iclass 32, count 0 2006.201.16:29:18.23#ibcon#about to read 3, iclass 32, count 0 2006.201.16:29:18.26#ibcon#read 3, iclass 32, count 0 2006.201.16:29:18.26#ibcon#about to read 4, iclass 32, count 0 2006.201.16:29:18.26#ibcon#read 4, iclass 32, count 0 2006.201.16:29:18.26#ibcon#about to read 5, iclass 32, count 0 2006.201.16:29:18.26#ibcon#read 5, iclass 32, count 0 2006.201.16:29:18.26#ibcon#about to read 6, iclass 32, count 0 2006.201.16:29:18.26#ibcon#read 6, iclass 32, count 0 2006.201.16:29:18.26#ibcon#end of sib2, iclass 32, count 0 2006.201.16:29:18.26#ibcon#*after write, iclass 32, count 0 2006.201.16:29:18.26#ibcon#*before return 0, iclass 32, count 0 2006.201.16:29:18.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:18.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:29:18.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.16:29:18.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.16:29:18.26$vck44/vblo=6,719.99 2006.201.16:29:18.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.16:29:18.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.16:29:18.26#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:18.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:18.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:18.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:18.26#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:29:18.26#ibcon#first serial, iclass 34, count 0 2006.201.16:29:18.26#ibcon#enter sib2, iclass 34, count 0 2006.201.16:29:18.26#ibcon#flushed, iclass 34, count 0 2006.201.16:29:18.26#ibcon#about to write, iclass 34, count 0 2006.201.16:29:18.26#ibcon#wrote, iclass 34, count 0 2006.201.16:29:18.26#ibcon#about to read 3, iclass 34, count 0 2006.201.16:29:18.28#ibcon#read 3, iclass 34, count 0 2006.201.16:29:18.28#ibcon#about to read 4, iclass 34, count 0 2006.201.16:29:18.28#ibcon#read 4, iclass 34, count 0 2006.201.16:29:18.28#ibcon#about to read 5, iclass 34, count 0 2006.201.16:29:18.28#ibcon#read 5, iclass 34, count 0 2006.201.16:29:18.28#ibcon#about to read 6, iclass 34, count 0 2006.201.16:29:18.28#ibcon#read 6, iclass 34, count 0 2006.201.16:29:18.28#ibcon#end of sib2, iclass 34, count 0 2006.201.16:29:18.28#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:29:18.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:29:18.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:29:18.28#ibcon#*before write, iclass 34, count 0 2006.201.16:29:18.28#ibcon#enter sib2, iclass 34, count 0 2006.201.16:29:18.28#ibcon#flushed, iclass 34, count 0 2006.201.16:29:18.28#ibcon#about to write, iclass 34, count 0 2006.201.16:29:18.28#ibcon#wrote, iclass 34, count 0 2006.201.16:29:18.28#ibcon#about to read 3, iclass 34, count 0 2006.201.16:29:18.32#ibcon#read 3, iclass 34, count 0 2006.201.16:29:18.32#ibcon#about to read 4, iclass 34, count 0 2006.201.16:29:18.32#ibcon#read 4, iclass 34, count 0 2006.201.16:29:18.32#ibcon#about to read 5, iclass 34, count 0 2006.201.16:29:18.32#ibcon#read 5, iclass 34, count 0 2006.201.16:29:18.32#ibcon#about to read 6, iclass 34, count 0 2006.201.16:29:18.32#ibcon#read 6, iclass 34, count 0 2006.201.16:29:18.32#ibcon#end of sib2, iclass 34, count 0 2006.201.16:29:18.32#ibcon#*after write, iclass 34, count 0 2006.201.16:29:18.32#ibcon#*before return 0, iclass 34, count 0 2006.201.16:29:18.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:18.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:29:18.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:29:18.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:29:18.32$vck44/vb=6,4 2006.201.16:29:18.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.16:29:18.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.16:29:18.32#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:18.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:18.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:18.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:18.38#ibcon#enter wrdev, iclass 36, count 2 2006.201.16:29:18.38#ibcon#first serial, iclass 36, count 2 2006.201.16:29:18.38#ibcon#enter sib2, iclass 36, count 2 2006.201.16:29:18.38#ibcon#flushed, iclass 36, count 2 2006.201.16:29:18.38#ibcon#about to write, iclass 36, count 2 2006.201.16:29:18.38#ibcon#wrote, iclass 36, count 2 2006.201.16:29:18.38#ibcon#about to read 3, iclass 36, count 2 2006.201.16:29:18.40#ibcon#read 3, iclass 36, count 2 2006.201.16:29:18.40#ibcon#about to read 4, iclass 36, count 2 2006.201.16:29:18.40#ibcon#read 4, iclass 36, count 2 2006.201.16:29:18.40#ibcon#about to read 5, iclass 36, count 2 2006.201.16:29:18.40#ibcon#read 5, iclass 36, count 2 2006.201.16:29:18.40#ibcon#about to read 6, iclass 36, count 2 2006.201.16:29:18.40#ibcon#read 6, iclass 36, count 2 2006.201.16:29:18.40#ibcon#end of sib2, iclass 36, count 2 2006.201.16:29:18.40#ibcon#*mode == 0, iclass 36, count 2 2006.201.16:29:18.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.16:29:18.40#ibcon#[27=AT06-04\r\n] 2006.201.16:29:18.40#ibcon#*before write, iclass 36, count 2 2006.201.16:29:18.40#ibcon#enter sib2, iclass 36, count 2 2006.201.16:29:18.40#ibcon#flushed, iclass 36, count 2 2006.201.16:29:18.40#ibcon#about to write, iclass 36, count 2 2006.201.16:29:18.40#ibcon#wrote, iclass 36, count 2 2006.201.16:29:18.40#ibcon#about to read 3, iclass 36, count 2 2006.201.16:29:18.43#ibcon#read 3, iclass 36, count 2 2006.201.16:29:18.43#ibcon#about to read 4, iclass 36, count 2 2006.201.16:29:18.43#ibcon#read 4, iclass 36, count 2 2006.201.16:29:18.43#ibcon#about to read 5, iclass 36, count 2 2006.201.16:29:18.43#ibcon#read 5, iclass 36, count 2 2006.201.16:29:18.43#ibcon#about to read 6, iclass 36, count 2 2006.201.16:29:18.43#ibcon#read 6, iclass 36, count 2 2006.201.16:29:18.43#ibcon#end of sib2, iclass 36, count 2 2006.201.16:29:18.43#ibcon#*after write, iclass 36, count 2 2006.201.16:29:18.43#ibcon#*before return 0, iclass 36, count 2 2006.201.16:29:18.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:18.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:29:18.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.16:29:18.43#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:18.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:18.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:18.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:18.55#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:29:18.55#ibcon#first serial, iclass 36, count 0 2006.201.16:29:18.55#ibcon#enter sib2, iclass 36, count 0 2006.201.16:29:18.55#ibcon#flushed, iclass 36, count 0 2006.201.16:29:18.55#ibcon#about to write, iclass 36, count 0 2006.201.16:29:18.55#ibcon#wrote, iclass 36, count 0 2006.201.16:29:18.55#ibcon#about to read 3, iclass 36, count 0 2006.201.16:29:18.57#ibcon#read 3, iclass 36, count 0 2006.201.16:29:18.57#ibcon#about to read 4, iclass 36, count 0 2006.201.16:29:18.57#ibcon#read 4, iclass 36, count 0 2006.201.16:29:18.57#ibcon#about to read 5, iclass 36, count 0 2006.201.16:29:18.57#ibcon#read 5, iclass 36, count 0 2006.201.16:29:18.57#ibcon#about to read 6, iclass 36, count 0 2006.201.16:29:18.57#ibcon#read 6, iclass 36, count 0 2006.201.16:29:18.57#ibcon#end of sib2, iclass 36, count 0 2006.201.16:29:18.57#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:29:18.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:29:18.57#ibcon#[27=USB\r\n] 2006.201.16:29:18.57#ibcon#*before write, iclass 36, count 0 2006.201.16:29:18.57#ibcon#enter sib2, iclass 36, count 0 2006.201.16:29:18.57#ibcon#flushed, iclass 36, count 0 2006.201.16:29:18.57#ibcon#about to write, iclass 36, count 0 2006.201.16:29:18.57#ibcon#wrote, iclass 36, count 0 2006.201.16:29:18.57#ibcon#about to read 3, iclass 36, count 0 2006.201.16:29:18.60#ibcon#read 3, iclass 36, count 0 2006.201.16:29:18.60#ibcon#about to read 4, iclass 36, count 0 2006.201.16:29:18.60#ibcon#read 4, iclass 36, count 0 2006.201.16:29:18.60#ibcon#about to read 5, iclass 36, count 0 2006.201.16:29:18.60#ibcon#read 5, iclass 36, count 0 2006.201.16:29:18.60#ibcon#about to read 6, iclass 36, count 0 2006.201.16:29:18.60#ibcon#read 6, iclass 36, count 0 2006.201.16:29:18.60#ibcon#end of sib2, iclass 36, count 0 2006.201.16:29:18.60#ibcon#*after write, iclass 36, count 0 2006.201.16:29:18.60#ibcon#*before return 0, iclass 36, count 0 2006.201.16:29:18.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:18.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:29:18.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:29:18.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:29:18.60$vck44/vblo=7,734.99 2006.201.16:29:18.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.16:29:18.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.16:29:18.60#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:18.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:18.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:18.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:18.60#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:29:18.60#ibcon#first serial, iclass 38, count 0 2006.201.16:29:18.60#ibcon#enter sib2, iclass 38, count 0 2006.201.16:29:18.60#ibcon#flushed, iclass 38, count 0 2006.201.16:29:18.60#ibcon#about to write, iclass 38, count 0 2006.201.16:29:18.60#ibcon#wrote, iclass 38, count 0 2006.201.16:29:18.60#ibcon#about to read 3, iclass 38, count 0 2006.201.16:29:18.62#ibcon#read 3, iclass 38, count 0 2006.201.16:29:18.62#ibcon#about to read 4, iclass 38, count 0 2006.201.16:29:18.62#ibcon#read 4, iclass 38, count 0 2006.201.16:29:18.62#ibcon#about to read 5, iclass 38, count 0 2006.201.16:29:18.62#ibcon#read 5, iclass 38, count 0 2006.201.16:29:18.62#ibcon#about to read 6, iclass 38, count 0 2006.201.16:29:18.62#ibcon#read 6, iclass 38, count 0 2006.201.16:29:18.62#ibcon#end of sib2, iclass 38, count 0 2006.201.16:29:18.62#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:29:18.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:29:18.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:29:18.62#ibcon#*before write, iclass 38, count 0 2006.201.16:29:18.62#ibcon#enter sib2, iclass 38, count 0 2006.201.16:29:18.62#ibcon#flushed, iclass 38, count 0 2006.201.16:29:18.62#ibcon#about to write, iclass 38, count 0 2006.201.16:29:18.62#ibcon#wrote, iclass 38, count 0 2006.201.16:29:18.62#ibcon#about to read 3, iclass 38, count 0 2006.201.16:29:18.66#ibcon#read 3, iclass 38, count 0 2006.201.16:29:18.66#ibcon#about to read 4, iclass 38, count 0 2006.201.16:29:18.66#ibcon#read 4, iclass 38, count 0 2006.201.16:29:18.66#ibcon#about to read 5, iclass 38, count 0 2006.201.16:29:18.66#ibcon#read 5, iclass 38, count 0 2006.201.16:29:18.66#ibcon#about to read 6, iclass 38, count 0 2006.201.16:29:18.66#ibcon#read 6, iclass 38, count 0 2006.201.16:29:18.66#ibcon#end of sib2, iclass 38, count 0 2006.201.16:29:18.66#ibcon#*after write, iclass 38, count 0 2006.201.16:29:18.66#ibcon#*before return 0, iclass 38, count 0 2006.201.16:29:18.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:18.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:29:18.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:29:18.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:29:18.66$vck44/vb=7,4 2006.201.16:29:18.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.16:29:18.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.16:29:18.66#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:18.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:18.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:18.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:18.72#ibcon#enter wrdev, iclass 40, count 2 2006.201.16:29:18.72#ibcon#first serial, iclass 40, count 2 2006.201.16:29:18.72#ibcon#enter sib2, iclass 40, count 2 2006.201.16:29:18.72#ibcon#flushed, iclass 40, count 2 2006.201.16:29:18.72#ibcon#about to write, iclass 40, count 2 2006.201.16:29:18.72#ibcon#wrote, iclass 40, count 2 2006.201.16:29:18.72#ibcon#about to read 3, iclass 40, count 2 2006.201.16:29:18.74#ibcon#read 3, iclass 40, count 2 2006.201.16:29:18.74#ibcon#about to read 4, iclass 40, count 2 2006.201.16:29:18.74#ibcon#read 4, iclass 40, count 2 2006.201.16:29:18.74#ibcon#about to read 5, iclass 40, count 2 2006.201.16:29:18.74#ibcon#read 5, iclass 40, count 2 2006.201.16:29:18.74#ibcon#about to read 6, iclass 40, count 2 2006.201.16:29:18.74#ibcon#read 6, iclass 40, count 2 2006.201.16:29:18.74#ibcon#end of sib2, iclass 40, count 2 2006.201.16:29:18.74#ibcon#*mode == 0, iclass 40, count 2 2006.201.16:29:18.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.16:29:18.74#ibcon#[27=AT07-04\r\n] 2006.201.16:29:18.74#ibcon#*before write, iclass 40, count 2 2006.201.16:29:18.74#ibcon#enter sib2, iclass 40, count 2 2006.201.16:29:18.74#ibcon#flushed, iclass 40, count 2 2006.201.16:29:18.74#ibcon#about to write, iclass 40, count 2 2006.201.16:29:18.74#ibcon#wrote, iclass 40, count 2 2006.201.16:29:18.74#ibcon#about to read 3, iclass 40, count 2 2006.201.16:29:18.77#ibcon#read 3, iclass 40, count 2 2006.201.16:29:18.77#ibcon#about to read 4, iclass 40, count 2 2006.201.16:29:18.77#ibcon#read 4, iclass 40, count 2 2006.201.16:29:18.77#ibcon#about to read 5, iclass 40, count 2 2006.201.16:29:18.77#ibcon#read 5, iclass 40, count 2 2006.201.16:29:18.77#ibcon#about to read 6, iclass 40, count 2 2006.201.16:29:18.77#ibcon#read 6, iclass 40, count 2 2006.201.16:29:18.77#ibcon#end of sib2, iclass 40, count 2 2006.201.16:29:18.77#ibcon#*after write, iclass 40, count 2 2006.201.16:29:18.77#ibcon#*before return 0, iclass 40, count 2 2006.201.16:29:18.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:18.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:29:18.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.16:29:18.77#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:18.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:18.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:18.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:18.89#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:29:18.89#ibcon#first serial, iclass 40, count 0 2006.201.16:29:18.89#ibcon#enter sib2, iclass 40, count 0 2006.201.16:29:18.89#ibcon#flushed, iclass 40, count 0 2006.201.16:29:18.89#ibcon#about to write, iclass 40, count 0 2006.201.16:29:18.89#ibcon#wrote, iclass 40, count 0 2006.201.16:29:18.89#ibcon#about to read 3, iclass 40, count 0 2006.201.16:29:18.91#ibcon#read 3, iclass 40, count 0 2006.201.16:29:18.91#ibcon#about to read 4, iclass 40, count 0 2006.201.16:29:18.91#ibcon#read 4, iclass 40, count 0 2006.201.16:29:18.91#ibcon#about to read 5, iclass 40, count 0 2006.201.16:29:18.91#ibcon#read 5, iclass 40, count 0 2006.201.16:29:18.91#ibcon#about to read 6, iclass 40, count 0 2006.201.16:29:18.91#ibcon#read 6, iclass 40, count 0 2006.201.16:29:18.91#ibcon#end of sib2, iclass 40, count 0 2006.201.16:29:18.91#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:29:18.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:29:18.91#ibcon#[27=USB\r\n] 2006.201.16:29:18.91#ibcon#*before write, iclass 40, count 0 2006.201.16:29:18.91#ibcon#enter sib2, iclass 40, count 0 2006.201.16:29:18.91#ibcon#flushed, iclass 40, count 0 2006.201.16:29:18.91#ibcon#about to write, iclass 40, count 0 2006.201.16:29:18.91#ibcon#wrote, iclass 40, count 0 2006.201.16:29:18.91#ibcon#about to read 3, iclass 40, count 0 2006.201.16:29:18.94#ibcon#read 3, iclass 40, count 0 2006.201.16:29:18.94#ibcon#about to read 4, iclass 40, count 0 2006.201.16:29:18.94#ibcon#read 4, iclass 40, count 0 2006.201.16:29:18.94#ibcon#about to read 5, iclass 40, count 0 2006.201.16:29:18.94#ibcon#read 5, iclass 40, count 0 2006.201.16:29:18.94#ibcon#about to read 6, iclass 40, count 0 2006.201.16:29:18.94#ibcon#read 6, iclass 40, count 0 2006.201.16:29:18.94#ibcon#end of sib2, iclass 40, count 0 2006.201.16:29:18.94#ibcon#*after write, iclass 40, count 0 2006.201.16:29:18.94#ibcon#*before return 0, iclass 40, count 0 2006.201.16:29:18.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:18.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:29:18.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:29:18.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:29:18.94$vck44/vblo=8,744.99 2006.201.16:29:18.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.16:29:18.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.16:29:18.94#ibcon#ireg 17 cls_cnt 0 2006.201.16:29:18.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:18.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:18.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:18.94#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:29:18.94#ibcon#first serial, iclass 4, count 0 2006.201.16:29:18.94#ibcon#enter sib2, iclass 4, count 0 2006.201.16:29:18.94#ibcon#flushed, iclass 4, count 0 2006.201.16:29:18.94#ibcon#about to write, iclass 4, count 0 2006.201.16:29:18.94#ibcon#wrote, iclass 4, count 0 2006.201.16:29:18.94#ibcon#about to read 3, iclass 4, count 0 2006.201.16:29:18.96#ibcon#read 3, iclass 4, count 0 2006.201.16:29:18.96#ibcon#about to read 4, iclass 4, count 0 2006.201.16:29:18.96#ibcon#read 4, iclass 4, count 0 2006.201.16:29:18.96#ibcon#about to read 5, iclass 4, count 0 2006.201.16:29:18.96#ibcon#read 5, iclass 4, count 0 2006.201.16:29:18.96#ibcon#about to read 6, iclass 4, count 0 2006.201.16:29:18.96#ibcon#read 6, iclass 4, count 0 2006.201.16:29:18.96#ibcon#end of sib2, iclass 4, count 0 2006.201.16:29:18.96#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:29:18.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:29:18.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:29:18.96#ibcon#*before write, iclass 4, count 0 2006.201.16:29:18.96#ibcon#enter sib2, iclass 4, count 0 2006.201.16:29:18.96#ibcon#flushed, iclass 4, count 0 2006.201.16:29:18.96#ibcon#about to write, iclass 4, count 0 2006.201.16:29:18.96#ibcon#wrote, iclass 4, count 0 2006.201.16:29:18.96#ibcon#about to read 3, iclass 4, count 0 2006.201.16:29:19.00#ibcon#read 3, iclass 4, count 0 2006.201.16:29:19.00#ibcon#about to read 4, iclass 4, count 0 2006.201.16:29:19.00#ibcon#read 4, iclass 4, count 0 2006.201.16:29:19.00#ibcon#about to read 5, iclass 4, count 0 2006.201.16:29:19.00#ibcon#read 5, iclass 4, count 0 2006.201.16:29:19.00#ibcon#about to read 6, iclass 4, count 0 2006.201.16:29:19.00#ibcon#read 6, iclass 4, count 0 2006.201.16:29:19.00#ibcon#end of sib2, iclass 4, count 0 2006.201.16:29:19.00#ibcon#*after write, iclass 4, count 0 2006.201.16:29:19.00#ibcon#*before return 0, iclass 4, count 0 2006.201.16:29:19.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:19.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:29:19.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:29:19.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:29:19.00$vck44/vb=8,4 2006.201.16:29:19.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.16:29:19.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.16:29:19.00#ibcon#ireg 11 cls_cnt 2 2006.201.16:29:19.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:19.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:19.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:19.06#ibcon#enter wrdev, iclass 6, count 2 2006.201.16:29:19.06#ibcon#first serial, iclass 6, count 2 2006.201.16:29:19.06#ibcon#enter sib2, iclass 6, count 2 2006.201.16:29:19.06#ibcon#flushed, iclass 6, count 2 2006.201.16:29:19.06#ibcon#about to write, iclass 6, count 2 2006.201.16:29:19.06#ibcon#wrote, iclass 6, count 2 2006.201.16:29:19.06#ibcon#about to read 3, iclass 6, count 2 2006.201.16:29:19.08#ibcon#read 3, iclass 6, count 2 2006.201.16:29:19.08#ibcon#about to read 4, iclass 6, count 2 2006.201.16:29:19.08#ibcon#read 4, iclass 6, count 2 2006.201.16:29:19.08#ibcon#about to read 5, iclass 6, count 2 2006.201.16:29:19.08#ibcon#read 5, iclass 6, count 2 2006.201.16:29:19.08#ibcon#about to read 6, iclass 6, count 2 2006.201.16:29:19.08#ibcon#read 6, iclass 6, count 2 2006.201.16:29:19.08#ibcon#end of sib2, iclass 6, count 2 2006.201.16:29:19.08#ibcon#*mode == 0, iclass 6, count 2 2006.201.16:29:19.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.16:29:19.08#ibcon#[27=AT08-04\r\n] 2006.201.16:29:19.08#ibcon#*before write, iclass 6, count 2 2006.201.16:29:19.08#ibcon#enter sib2, iclass 6, count 2 2006.201.16:29:19.08#ibcon#flushed, iclass 6, count 2 2006.201.16:29:19.08#ibcon#about to write, iclass 6, count 2 2006.201.16:29:19.08#ibcon#wrote, iclass 6, count 2 2006.201.16:29:19.08#ibcon#about to read 3, iclass 6, count 2 2006.201.16:29:19.11#ibcon#read 3, iclass 6, count 2 2006.201.16:29:19.11#ibcon#about to read 4, iclass 6, count 2 2006.201.16:29:19.11#ibcon#read 4, iclass 6, count 2 2006.201.16:29:19.11#ibcon#about to read 5, iclass 6, count 2 2006.201.16:29:19.11#ibcon#read 5, iclass 6, count 2 2006.201.16:29:19.11#ibcon#about to read 6, iclass 6, count 2 2006.201.16:29:19.11#ibcon#read 6, iclass 6, count 2 2006.201.16:29:19.11#ibcon#end of sib2, iclass 6, count 2 2006.201.16:29:19.11#ibcon#*after write, iclass 6, count 2 2006.201.16:29:19.11#ibcon#*before return 0, iclass 6, count 2 2006.201.16:29:19.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:19.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:29:19.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.16:29:19.11#ibcon#ireg 7 cls_cnt 0 2006.201.16:29:19.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:19.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:19.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:19.23#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:29:19.23#ibcon#first serial, iclass 6, count 0 2006.201.16:29:19.23#ibcon#enter sib2, iclass 6, count 0 2006.201.16:29:19.23#ibcon#flushed, iclass 6, count 0 2006.201.16:29:19.23#ibcon#about to write, iclass 6, count 0 2006.201.16:29:19.23#ibcon#wrote, iclass 6, count 0 2006.201.16:29:19.23#ibcon#about to read 3, iclass 6, count 0 2006.201.16:29:19.25#ibcon#read 3, iclass 6, count 0 2006.201.16:29:19.25#ibcon#about to read 4, iclass 6, count 0 2006.201.16:29:19.25#ibcon#read 4, iclass 6, count 0 2006.201.16:29:19.25#ibcon#about to read 5, iclass 6, count 0 2006.201.16:29:19.25#ibcon#read 5, iclass 6, count 0 2006.201.16:29:19.25#ibcon#about to read 6, iclass 6, count 0 2006.201.16:29:19.25#ibcon#read 6, iclass 6, count 0 2006.201.16:29:19.25#ibcon#end of sib2, iclass 6, count 0 2006.201.16:29:19.25#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:29:19.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:29:19.25#ibcon#[27=USB\r\n] 2006.201.16:29:19.25#ibcon#*before write, iclass 6, count 0 2006.201.16:29:19.25#ibcon#enter sib2, iclass 6, count 0 2006.201.16:29:19.25#ibcon#flushed, iclass 6, count 0 2006.201.16:29:19.25#ibcon#about to write, iclass 6, count 0 2006.201.16:29:19.25#ibcon#wrote, iclass 6, count 0 2006.201.16:29:19.25#ibcon#about to read 3, iclass 6, count 0 2006.201.16:29:19.28#ibcon#read 3, iclass 6, count 0 2006.201.16:29:19.28#ibcon#about to read 4, iclass 6, count 0 2006.201.16:29:19.28#ibcon#read 4, iclass 6, count 0 2006.201.16:29:19.28#ibcon#about to read 5, iclass 6, count 0 2006.201.16:29:19.28#ibcon#read 5, iclass 6, count 0 2006.201.16:29:19.28#ibcon#about to read 6, iclass 6, count 0 2006.201.16:29:19.28#ibcon#read 6, iclass 6, count 0 2006.201.16:29:19.28#ibcon#end of sib2, iclass 6, count 0 2006.201.16:29:19.28#ibcon#*after write, iclass 6, count 0 2006.201.16:29:19.28#ibcon#*before return 0, iclass 6, count 0 2006.201.16:29:19.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:19.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:29:19.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:29:19.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:29:19.28$vck44/vabw=wide 2006.201.16:29:19.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.16:29:19.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.16:29:19.28#ibcon#ireg 8 cls_cnt 0 2006.201.16:29:19.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:19.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:19.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:19.28#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:29:19.28#ibcon#first serial, iclass 10, count 0 2006.201.16:29:19.28#ibcon#enter sib2, iclass 10, count 0 2006.201.16:29:19.28#ibcon#flushed, iclass 10, count 0 2006.201.16:29:19.28#ibcon#about to write, iclass 10, count 0 2006.201.16:29:19.28#ibcon#wrote, iclass 10, count 0 2006.201.16:29:19.28#ibcon#about to read 3, iclass 10, count 0 2006.201.16:29:19.30#ibcon#read 3, iclass 10, count 0 2006.201.16:29:19.30#ibcon#about to read 4, iclass 10, count 0 2006.201.16:29:19.30#ibcon#read 4, iclass 10, count 0 2006.201.16:29:19.30#ibcon#about to read 5, iclass 10, count 0 2006.201.16:29:19.30#ibcon#read 5, iclass 10, count 0 2006.201.16:29:19.30#ibcon#about to read 6, iclass 10, count 0 2006.201.16:29:19.30#ibcon#read 6, iclass 10, count 0 2006.201.16:29:19.30#ibcon#end of sib2, iclass 10, count 0 2006.201.16:29:19.30#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:29:19.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:29:19.30#ibcon#[25=BW32\r\n] 2006.201.16:29:19.30#ibcon#*before write, iclass 10, count 0 2006.201.16:29:19.30#ibcon#enter sib2, iclass 10, count 0 2006.201.16:29:19.30#ibcon#flushed, iclass 10, count 0 2006.201.16:29:19.30#ibcon#about to write, iclass 10, count 0 2006.201.16:29:19.30#ibcon#wrote, iclass 10, count 0 2006.201.16:29:19.30#ibcon#about to read 3, iclass 10, count 0 2006.201.16:29:19.33#ibcon#read 3, iclass 10, count 0 2006.201.16:29:19.33#ibcon#about to read 4, iclass 10, count 0 2006.201.16:29:19.33#ibcon#read 4, iclass 10, count 0 2006.201.16:29:19.33#ibcon#about to read 5, iclass 10, count 0 2006.201.16:29:19.33#ibcon#read 5, iclass 10, count 0 2006.201.16:29:19.33#ibcon#about to read 6, iclass 10, count 0 2006.201.16:29:19.33#ibcon#read 6, iclass 10, count 0 2006.201.16:29:19.33#ibcon#end of sib2, iclass 10, count 0 2006.201.16:29:19.33#ibcon#*after write, iclass 10, count 0 2006.201.16:29:19.33#ibcon#*before return 0, iclass 10, count 0 2006.201.16:29:19.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:19.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:29:19.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:29:19.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:29:19.33$vck44/vbbw=wide 2006.201.16:29:19.33#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.16:29:19.33#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.16:29:19.33#ibcon#ireg 8 cls_cnt 0 2006.201.16:29:19.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:29:19.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:29:19.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:29:19.40#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:29:19.40#ibcon#first serial, iclass 12, count 0 2006.201.16:29:19.40#ibcon#enter sib2, iclass 12, count 0 2006.201.16:29:19.40#ibcon#flushed, iclass 12, count 0 2006.201.16:29:19.40#ibcon#about to write, iclass 12, count 0 2006.201.16:29:19.40#ibcon#wrote, iclass 12, count 0 2006.201.16:29:19.40#ibcon#about to read 3, iclass 12, count 0 2006.201.16:29:19.42#ibcon#read 3, iclass 12, count 0 2006.201.16:29:19.42#ibcon#about to read 4, iclass 12, count 0 2006.201.16:29:19.42#ibcon#read 4, iclass 12, count 0 2006.201.16:29:19.42#ibcon#about to read 5, iclass 12, count 0 2006.201.16:29:19.42#ibcon#read 5, iclass 12, count 0 2006.201.16:29:19.42#ibcon#about to read 6, iclass 12, count 0 2006.201.16:29:19.42#ibcon#read 6, iclass 12, count 0 2006.201.16:29:19.42#ibcon#end of sib2, iclass 12, count 0 2006.201.16:29:19.42#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:29:19.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:29:19.42#ibcon#[27=BW32\r\n] 2006.201.16:29:19.42#ibcon#*before write, iclass 12, count 0 2006.201.16:29:19.42#ibcon#enter sib2, iclass 12, count 0 2006.201.16:29:19.42#ibcon#flushed, iclass 12, count 0 2006.201.16:29:19.42#ibcon#about to write, iclass 12, count 0 2006.201.16:29:19.42#ibcon#wrote, iclass 12, count 0 2006.201.16:29:19.42#ibcon#about to read 3, iclass 12, count 0 2006.201.16:29:19.45#ibcon#read 3, iclass 12, count 0 2006.201.16:29:19.45#ibcon#about to read 4, iclass 12, count 0 2006.201.16:29:19.45#ibcon#read 4, iclass 12, count 0 2006.201.16:29:19.45#ibcon#about to read 5, iclass 12, count 0 2006.201.16:29:19.45#ibcon#read 5, iclass 12, count 0 2006.201.16:29:19.45#ibcon#about to read 6, iclass 12, count 0 2006.201.16:29:19.45#ibcon#read 6, iclass 12, count 0 2006.201.16:29:19.45#ibcon#end of sib2, iclass 12, count 0 2006.201.16:29:19.45#ibcon#*after write, iclass 12, count 0 2006.201.16:29:19.45#ibcon#*before return 0, iclass 12, count 0 2006.201.16:29:19.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:29:19.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:29:19.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:29:19.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:29:19.45$setupk4/ifdk4 2006.201.16:29:19.45$ifdk4/lo= 2006.201.16:29:19.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:29:19.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:29:19.45$ifdk4/patch= 2006.201.16:29:19.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:29:19.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:29:19.45$setupk4/!*+20s 2006.201.16:29:21.95#abcon#<5=/03 0.6 1.3 20.831001002.6\r\n> 2006.201.16:29:21.97#abcon#{5=INTERFACE CLEAR} 2006.201.16:29:22.03#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:29:32.12#abcon#<5=/04 0.7 1.3 20.831001002.6\r\n> 2006.201.16:29:32.14#abcon#{5=INTERFACE CLEAR} 2006.201.16:29:32.20#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:29:33.90$setupk4/"tpicd 2006.201.16:29:33.90$setupk4/echo=off 2006.201.16:29:33.90$setupk4/xlog=off 2006.201.16:29:33.90:!2006.201.16:32:10 2006.201.16:30:10.13#trakl#Source acquired 2006.201.16:30:12.13#flagr#flagr/antenna,acquired 2006.201.16:32:10.00:preob 2006.201.16:32:10.14/onsource/TRACKING 2006.201.16:32:10.14:!2006.201.16:32:20 2006.201.16:32:20.00:"tape 2006.201.16:32:20.00:"st=record 2006.201.16:32:20.00:data_valid=on 2006.201.16:32:20.00:midob 2006.201.16:32:21.14/onsource/TRACKING 2006.201.16:32:21.14/wx/20.82,1002.6,100 2006.201.16:32:21.32/cable/+6.4760E-03 2006.201.16:32:22.41/va/01,08,usb,yes,37,40 2006.201.16:32:22.41/va/02,07,usb,yes,40,41 2006.201.16:32:22.41/va/03,08,usb,yes,36,38 2006.201.16:32:22.41/va/04,07,usb,yes,41,43 2006.201.16:32:22.41/va/05,04,usb,yes,37,37 2006.201.16:32:22.41/va/06,05,usb,yes,37,37 2006.201.16:32:22.41/va/07,05,usb,yes,36,37 2006.201.16:32:22.41/va/08,04,usb,yes,36,42 2006.201.16:32:22.64/valo/01,524.99,yes,locked 2006.201.16:32:22.64/valo/02,534.99,yes,locked 2006.201.16:32:22.64/valo/03,564.99,yes,locked 2006.201.16:32:22.64/valo/04,624.99,yes,locked 2006.201.16:32:22.64/valo/05,734.99,yes,locked 2006.201.16:32:22.64/valo/06,814.99,yes,locked 2006.201.16:32:22.64/valo/07,864.99,yes,locked 2006.201.16:32:22.64/valo/08,884.99,yes,locked 2006.201.16:32:23.73/vb/01,04,usb,yes,29,27 2006.201.16:32:23.73/vb/02,05,usb,yes,28,27 2006.201.16:32:23.73/vb/03,04,usb,yes,28,31 2006.201.16:32:23.73/vb/04,05,usb,yes,29,28 2006.201.16:32:23.73/vb/05,04,usb,yes,25,28 2006.201.16:32:23.73/vb/06,04,usb,yes,30,26 2006.201.16:32:23.73/vb/07,04,usb,yes,29,29 2006.201.16:32:23.73/vb/08,04,usb,yes,27,30 2006.201.16:32:23.96/vblo/01,629.99,yes,locked 2006.201.16:32:23.96/vblo/02,634.99,yes,locked 2006.201.16:32:23.96/vblo/03,649.99,yes,locked 2006.201.16:32:23.96/vblo/04,679.99,yes,locked 2006.201.16:32:23.96/vblo/05,709.99,yes,locked 2006.201.16:32:23.96/vblo/06,719.99,yes,locked 2006.201.16:32:23.96/vblo/07,734.99,yes,locked 2006.201.16:32:23.96/vblo/08,744.99,yes,locked 2006.201.16:32:24.11/vabw/8 2006.201.16:32:24.26/vbbw/8 2006.201.16:32:24.35/xfe/off,on,15.2 2006.201.16:32:24.73/ifatt/23,28,28,28 2006.201.16:32:25.06/fmout-gps/S +4.56E-07 2006.201.16:32:25.13:!2006.201.16:33:00 2006.201.16:33:00.00:data_valid=off 2006.201.16:33:00.00:"et 2006.201.16:33:00.00:!+3s 2006.201.16:33:03.02:"tape 2006.201.16:33:03.02:postob 2006.201.16:33:03.08/cable/+6.4779E-03 2006.201.16:33:03.08/wx/20.82,1002.6,100 2006.201.16:33:03.14/fmout-gps/S +4.56E-07 2006.201.16:33:03.14:scan_name=201-1634,jd0607,80 2006.201.16:33:03.14:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.201.16:33:05.14#flagr#flagr/antenna,new-source 2006.201.16:33:05.14:checkk5 2006.201.16:33:05.48/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:33:05.86/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:33:06.22/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:33:06.60/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:33:06.96/chk_obsdata//k5ts1/T2011632??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:33:07.33/chk_obsdata//k5ts2/T2011632??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:33:07.69/chk_obsdata//k5ts3/T2011632??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:33:08.06/chk_obsdata//k5ts4/T2011632??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:33:08.75/k5log//k5ts1_log_newline 2006.201.16:33:09.44/k5log//k5ts2_log_newline 2006.201.16:33:10.13/k5log//k5ts3_log_newline 2006.201.16:33:10.81/k5log//k5ts4_log_newline 2006.201.16:33:10.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:33:10.84:setupk4=1 2006.201.16:33:10.84$setupk4/echo=on 2006.201.16:33:10.84$setupk4/pcalon 2006.201.16:33:10.84$pcalon/"no phase cal control is implemented here 2006.201.16:33:10.84$setupk4/"tpicd=stop 2006.201.16:33:10.84$setupk4/"rec=synch_on 2006.201.16:33:10.84$setupk4/"rec_mode=128 2006.201.16:33:10.84$setupk4/!* 2006.201.16:33:10.84$setupk4/recpk4 2006.201.16:33:10.84$recpk4/recpatch= 2006.201.16:33:10.84$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:33:10.84$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:33:10.84$setupk4/vck44 2006.201.16:33:10.84$vck44/valo=1,524.99 2006.201.16:33:10.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.16:33:10.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.16:33:10.84#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:10.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:10.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:10.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:10.84#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:33:10.84#ibcon#first serial, iclass 37, count 0 2006.201.16:33:10.84#ibcon#enter sib2, iclass 37, count 0 2006.201.16:33:10.84#ibcon#flushed, iclass 37, count 0 2006.201.16:33:10.84#ibcon#about to write, iclass 37, count 0 2006.201.16:33:10.84#ibcon#wrote, iclass 37, count 0 2006.201.16:33:10.84#ibcon#about to read 3, iclass 37, count 0 2006.201.16:33:10.88#ibcon#read 3, iclass 37, count 0 2006.201.16:33:10.88#ibcon#about to read 4, iclass 37, count 0 2006.201.16:33:10.88#ibcon#read 4, iclass 37, count 0 2006.201.16:33:10.88#ibcon#about to read 5, iclass 37, count 0 2006.201.16:33:10.88#ibcon#read 5, iclass 37, count 0 2006.201.16:33:10.88#ibcon#about to read 6, iclass 37, count 0 2006.201.16:33:10.88#ibcon#read 6, iclass 37, count 0 2006.201.16:33:10.88#ibcon#end of sib2, iclass 37, count 0 2006.201.16:33:10.88#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:33:10.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:33:10.88#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:33:10.88#ibcon#*before write, iclass 37, count 0 2006.201.16:33:10.88#ibcon#enter sib2, iclass 37, count 0 2006.201.16:33:10.88#ibcon#flushed, iclass 37, count 0 2006.201.16:33:10.88#ibcon#about to write, iclass 37, count 0 2006.201.16:33:10.88#ibcon#wrote, iclass 37, count 0 2006.201.16:33:10.88#ibcon#about to read 3, iclass 37, count 0 2006.201.16:33:10.93#ibcon#read 3, iclass 37, count 0 2006.201.16:33:10.93#ibcon#about to read 4, iclass 37, count 0 2006.201.16:33:10.93#ibcon#read 4, iclass 37, count 0 2006.201.16:33:10.93#ibcon#about to read 5, iclass 37, count 0 2006.201.16:33:10.93#ibcon#read 5, iclass 37, count 0 2006.201.16:33:10.93#ibcon#about to read 6, iclass 37, count 0 2006.201.16:33:10.93#ibcon#read 6, iclass 37, count 0 2006.201.16:33:10.93#ibcon#end of sib2, iclass 37, count 0 2006.201.16:33:10.93#ibcon#*after write, iclass 37, count 0 2006.201.16:33:10.93#ibcon#*before return 0, iclass 37, count 0 2006.201.16:33:10.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:10.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:10.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:33:10.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:33:10.93$vck44/va=1,8 2006.201.16:33:10.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.16:33:10.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.16:33:10.93#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:10.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:10.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:10.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:10.93#ibcon#enter wrdev, iclass 39, count 2 2006.201.16:33:10.93#ibcon#first serial, iclass 39, count 2 2006.201.16:33:10.93#ibcon#enter sib2, iclass 39, count 2 2006.201.16:33:10.93#ibcon#flushed, iclass 39, count 2 2006.201.16:33:10.93#ibcon#about to write, iclass 39, count 2 2006.201.16:33:10.93#ibcon#wrote, iclass 39, count 2 2006.201.16:33:10.93#ibcon#about to read 3, iclass 39, count 2 2006.201.16:33:10.95#ibcon#read 3, iclass 39, count 2 2006.201.16:33:10.95#ibcon#about to read 4, iclass 39, count 2 2006.201.16:33:10.95#ibcon#read 4, iclass 39, count 2 2006.201.16:33:10.95#ibcon#about to read 5, iclass 39, count 2 2006.201.16:33:10.95#ibcon#read 5, iclass 39, count 2 2006.201.16:33:10.95#ibcon#about to read 6, iclass 39, count 2 2006.201.16:33:10.95#ibcon#read 6, iclass 39, count 2 2006.201.16:33:10.95#ibcon#end of sib2, iclass 39, count 2 2006.201.16:33:10.95#ibcon#*mode == 0, iclass 39, count 2 2006.201.16:33:10.95#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.16:33:10.95#ibcon#[25=AT01-08\r\n] 2006.201.16:33:10.95#ibcon#*before write, iclass 39, count 2 2006.201.16:33:10.95#ibcon#enter sib2, iclass 39, count 2 2006.201.16:33:10.95#ibcon#flushed, iclass 39, count 2 2006.201.16:33:10.95#ibcon#about to write, iclass 39, count 2 2006.201.16:33:10.95#ibcon#wrote, iclass 39, count 2 2006.201.16:33:10.95#ibcon#about to read 3, iclass 39, count 2 2006.201.16:33:10.99#ibcon#read 3, iclass 39, count 2 2006.201.16:33:10.99#ibcon#about to read 4, iclass 39, count 2 2006.201.16:33:10.99#ibcon#read 4, iclass 39, count 2 2006.201.16:33:10.99#ibcon#about to read 5, iclass 39, count 2 2006.201.16:33:10.99#ibcon#read 5, iclass 39, count 2 2006.201.16:33:10.99#ibcon#about to read 6, iclass 39, count 2 2006.201.16:33:10.99#ibcon#read 6, iclass 39, count 2 2006.201.16:33:10.99#ibcon#end of sib2, iclass 39, count 2 2006.201.16:33:10.99#ibcon#*after write, iclass 39, count 2 2006.201.16:33:10.99#ibcon#*before return 0, iclass 39, count 2 2006.201.16:33:10.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:10.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:10.99#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.16:33:10.99#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:10.99#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:11.11#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:11.11#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:11.11#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:33:11.11#ibcon#first serial, iclass 39, count 0 2006.201.16:33:11.11#ibcon#enter sib2, iclass 39, count 0 2006.201.16:33:11.11#ibcon#flushed, iclass 39, count 0 2006.201.16:33:11.11#ibcon#about to write, iclass 39, count 0 2006.201.16:33:11.11#ibcon#wrote, iclass 39, count 0 2006.201.16:33:11.11#ibcon#about to read 3, iclass 39, count 0 2006.201.16:33:11.13#ibcon#read 3, iclass 39, count 0 2006.201.16:33:11.13#ibcon#about to read 4, iclass 39, count 0 2006.201.16:33:11.13#ibcon#read 4, iclass 39, count 0 2006.201.16:33:11.13#ibcon#about to read 5, iclass 39, count 0 2006.201.16:33:11.13#ibcon#read 5, iclass 39, count 0 2006.201.16:33:11.13#ibcon#about to read 6, iclass 39, count 0 2006.201.16:33:11.13#ibcon#read 6, iclass 39, count 0 2006.201.16:33:11.13#ibcon#end of sib2, iclass 39, count 0 2006.201.16:33:11.13#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:33:11.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:33:11.13#ibcon#[25=USB\r\n] 2006.201.16:33:11.13#ibcon#*before write, iclass 39, count 0 2006.201.16:33:11.13#ibcon#enter sib2, iclass 39, count 0 2006.201.16:33:11.13#ibcon#flushed, iclass 39, count 0 2006.201.16:33:11.13#ibcon#about to write, iclass 39, count 0 2006.201.16:33:11.13#ibcon#wrote, iclass 39, count 0 2006.201.16:33:11.13#ibcon#about to read 3, iclass 39, count 0 2006.201.16:33:11.16#ibcon#read 3, iclass 39, count 0 2006.201.16:33:11.16#ibcon#about to read 4, iclass 39, count 0 2006.201.16:33:11.16#ibcon#read 4, iclass 39, count 0 2006.201.16:33:11.16#ibcon#about to read 5, iclass 39, count 0 2006.201.16:33:11.16#ibcon#read 5, iclass 39, count 0 2006.201.16:33:11.16#ibcon#about to read 6, iclass 39, count 0 2006.201.16:33:11.16#ibcon#read 6, iclass 39, count 0 2006.201.16:33:11.16#ibcon#end of sib2, iclass 39, count 0 2006.201.16:33:11.16#ibcon#*after write, iclass 39, count 0 2006.201.16:33:11.16#ibcon#*before return 0, iclass 39, count 0 2006.201.16:33:11.16#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:11.16#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:11.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:33:11.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:33:11.16$vck44/valo=2,534.99 2006.201.16:33:11.16#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.16:33:11.16#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.16:33:11.16#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:11.16#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:11.16#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:11.16#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:11.16#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:33:11.16#ibcon#first serial, iclass 2, count 0 2006.201.16:33:11.16#ibcon#enter sib2, iclass 2, count 0 2006.201.16:33:11.16#ibcon#flushed, iclass 2, count 0 2006.201.16:33:11.16#ibcon#about to write, iclass 2, count 0 2006.201.16:33:11.16#ibcon#wrote, iclass 2, count 0 2006.201.16:33:11.16#ibcon#about to read 3, iclass 2, count 0 2006.201.16:33:11.18#ibcon#read 3, iclass 2, count 0 2006.201.16:33:11.18#ibcon#about to read 4, iclass 2, count 0 2006.201.16:33:11.18#ibcon#read 4, iclass 2, count 0 2006.201.16:33:11.18#ibcon#about to read 5, iclass 2, count 0 2006.201.16:33:11.18#ibcon#read 5, iclass 2, count 0 2006.201.16:33:11.18#ibcon#about to read 6, iclass 2, count 0 2006.201.16:33:11.18#ibcon#read 6, iclass 2, count 0 2006.201.16:33:11.18#ibcon#end of sib2, iclass 2, count 0 2006.201.16:33:11.18#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:33:11.18#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:33:11.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:33:11.18#ibcon#*before write, iclass 2, count 0 2006.201.16:33:11.18#ibcon#enter sib2, iclass 2, count 0 2006.201.16:33:11.18#ibcon#flushed, iclass 2, count 0 2006.201.16:33:11.18#ibcon#about to write, iclass 2, count 0 2006.201.16:33:11.18#ibcon#wrote, iclass 2, count 0 2006.201.16:33:11.18#ibcon#about to read 3, iclass 2, count 0 2006.201.16:33:11.22#ibcon#read 3, iclass 2, count 0 2006.201.16:33:11.22#ibcon#about to read 4, iclass 2, count 0 2006.201.16:33:11.22#ibcon#read 4, iclass 2, count 0 2006.201.16:33:11.22#ibcon#about to read 5, iclass 2, count 0 2006.201.16:33:11.22#ibcon#read 5, iclass 2, count 0 2006.201.16:33:11.22#ibcon#about to read 6, iclass 2, count 0 2006.201.16:33:11.22#ibcon#read 6, iclass 2, count 0 2006.201.16:33:11.22#ibcon#end of sib2, iclass 2, count 0 2006.201.16:33:11.22#ibcon#*after write, iclass 2, count 0 2006.201.16:33:11.22#ibcon#*before return 0, iclass 2, count 0 2006.201.16:33:11.22#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:11.22#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:11.22#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:33:11.22#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:33:11.22$vck44/va=2,7 2006.201.16:33:11.22#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.16:33:11.22#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.16:33:11.22#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:11.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:11.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:11.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:11.28#ibcon#enter wrdev, iclass 5, count 2 2006.201.16:33:11.28#ibcon#first serial, iclass 5, count 2 2006.201.16:33:11.28#ibcon#enter sib2, iclass 5, count 2 2006.201.16:33:11.28#ibcon#flushed, iclass 5, count 2 2006.201.16:33:11.28#ibcon#about to write, iclass 5, count 2 2006.201.16:33:11.28#ibcon#wrote, iclass 5, count 2 2006.201.16:33:11.28#ibcon#about to read 3, iclass 5, count 2 2006.201.16:33:11.30#ibcon#read 3, iclass 5, count 2 2006.201.16:33:11.30#ibcon#about to read 4, iclass 5, count 2 2006.201.16:33:11.30#ibcon#read 4, iclass 5, count 2 2006.201.16:33:11.30#ibcon#about to read 5, iclass 5, count 2 2006.201.16:33:11.30#ibcon#read 5, iclass 5, count 2 2006.201.16:33:11.30#ibcon#about to read 6, iclass 5, count 2 2006.201.16:33:11.30#ibcon#read 6, iclass 5, count 2 2006.201.16:33:11.30#ibcon#end of sib2, iclass 5, count 2 2006.201.16:33:11.30#ibcon#*mode == 0, iclass 5, count 2 2006.201.16:33:11.30#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.16:33:11.30#ibcon#[25=AT02-07\r\n] 2006.201.16:33:11.30#ibcon#*before write, iclass 5, count 2 2006.201.16:33:11.30#ibcon#enter sib2, iclass 5, count 2 2006.201.16:33:11.30#ibcon#flushed, iclass 5, count 2 2006.201.16:33:11.30#ibcon#about to write, iclass 5, count 2 2006.201.16:33:11.30#ibcon#wrote, iclass 5, count 2 2006.201.16:33:11.30#ibcon#about to read 3, iclass 5, count 2 2006.201.16:33:11.33#ibcon#read 3, iclass 5, count 2 2006.201.16:33:11.33#ibcon#about to read 4, iclass 5, count 2 2006.201.16:33:11.33#ibcon#read 4, iclass 5, count 2 2006.201.16:33:11.33#ibcon#about to read 5, iclass 5, count 2 2006.201.16:33:11.33#ibcon#read 5, iclass 5, count 2 2006.201.16:33:11.33#ibcon#about to read 6, iclass 5, count 2 2006.201.16:33:11.33#ibcon#read 6, iclass 5, count 2 2006.201.16:33:11.33#ibcon#end of sib2, iclass 5, count 2 2006.201.16:33:11.33#ibcon#*after write, iclass 5, count 2 2006.201.16:33:11.33#ibcon#*before return 0, iclass 5, count 2 2006.201.16:33:11.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:11.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:11.33#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.16:33:11.33#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:11.33#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:11.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:11.45#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:11.45#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:33:11.45#ibcon#first serial, iclass 5, count 0 2006.201.16:33:11.45#ibcon#enter sib2, iclass 5, count 0 2006.201.16:33:11.45#ibcon#flushed, iclass 5, count 0 2006.201.16:33:11.45#ibcon#about to write, iclass 5, count 0 2006.201.16:33:11.45#ibcon#wrote, iclass 5, count 0 2006.201.16:33:11.45#ibcon#about to read 3, iclass 5, count 0 2006.201.16:33:11.47#ibcon#read 3, iclass 5, count 0 2006.201.16:33:11.47#ibcon#about to read 4, iclass 5, count 0 2006.201.16:33:11.47#ibcon#read 4, iclass 5, count 0 2006.201.16:33:11.47#ibcon#about to read 5, iclass 5, count 0 2006.201.16:33:11.47#ibcon#read 5, iclass 5, count 0 2006.201.16:33:11.47#ibcon#about to read 6, iclass 5, count 0 2006.201.16:33:11.47#ibcon#read 6, iclass 5, count 0 2006.201.16:33:11.47#ibcon#end of sib2, iclass 5, count 0 2006.201.16:33:11.47#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:33:11.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:33:11.47#ibcon#[25=USB\r\n] 2006.201.16:33:11.47#ibcon#*before write, iclass 5, count 0 2006.201.16:33:11.47#ibcon#enter sib2, iclass 5, count 0 2006.201.16:33:11.47#ibcon#flushed, iclass 5, count 0 2006.201.16:33:11.47#ibcon#about to write, iclass 5, count 0 2006.201.16:33:11.47#ibcon#wrote, iclass 5, count 0 2006.201.16:33:11.47#ibcon#about to read 3, iclass 5, count 0 2006.201.16:33:11.50#ibcon#read 3, iclass 5, count 0 2006.201.16:33:11.50#ibcon#about to read 4, iclass 5, count 0 2006.201.16:33:11.50#ibcon#read 4, iclass 5, count 0 2006.201.16:33:11.50#ibcon#about to read 5, iclass 5, count 0 2006.201.16:33:11.50#ibcon#read 5, iclass 5, count 0 2006.201.16:33:11.50#ibcon#about to read 6, iclass 5, count 0 2006.201.16:33:11.50#ibcon#read 6, iclass 5, count 0 2006.201.16:33:11.50#ibcon#end of sib2, iclass 5, count 0 2006.201.16:33:11.50#ibcon#*after write, iclass 5, count 0 2006.201.16:33:11.50#ibcon#*before return 0, iclass 5, count 0 2006.201.16:33:11.50#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:11.50#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:11.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:33:11.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:33:11.50$vck44/valo=3,564.99 2006.201.16:33:11.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.16:33:11.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.16:33:11.50#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:11.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:11.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:11.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:11.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:33:11.50#ibcon#first serial, iclass 7, count 0 2006.201.16:33:11.50#ibcon#enter sib2, iclass 7, count 0 2006.201.16:33:11.50#ibcon#flushed, iclass 7, count 0 2006.201.16:33:11.50#ibcon#about to write, iclass 7, count 0 2006.201.16:33:11.50#ibcon#wrote, iclass 7, count 0 2006.201.16:33:11.50#ibcon#about to read 3, iclass 7, count 0 2006.201.16:33:11.52#ibcon#read 3, iclass 7, count 0 2006.201.16:33:11.52#ibcon#about to read 4, iclass 7, count 0 2006.201.16:33:11.52#ibcon#read 4, iclass 7, count 0 2006.201.16:33:11.52#ibcon#about to read 5, iclass 7, count 0 2006.201.16:33:11.52#ibcon#read 5, iclass 7, count 0 2006.201.16:33:11.52#ibcon#about to read 6, iclass 7, count 0 2006.201.16:33:11.52#ibcon#read 6, iclass 7, count 0 2006.201.16:33:11.52#ibcon#end of sib2, iclass 7, count 0 2006.201.16:33:11.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:33:11.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:33:11.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:33:11.52#ibcon#*before write, iclass 7, count 0 2006.201.16:33:11.52#ibcon#enter sib2, iclass 7, count 0 2006.201.16:33:11.52#ibcon#flushed, iclass 7, count 0 2006.201.16:33:11.52#ibcon#about to write, iclass 7, count 0 2006.201.16:33:11.52#ibcon#wrote, iclass 7, count 0 2006.201.16:33:11.52#ibcon#about to read 3, iclass 7, count 0 2006.201.16:33:11.57#ibcon#read 3, iclass 7, count 0 2006.201.16:33:11.57#ibcon#about to read 4, iclass 7, count 0 2006.201.16:33:11.57#ibcon#read 4, iclass 7, count 0 2006.201.16:33:11.57#ibcon#about to read 5, iclass 7, count 0 2006.201.16:33:11.57#ibcon#read 5, iclass 7, count 0 2006.201.16:33:11.57#ibcon#about to read 6, iclass 7, count 0 2006.201.16:33:11.57#ibcon#read 6, iclass 7, count 0 2006.201.16:33:11.57#ibcon#end of sib2, iclass 7, count 0 2006.201.16:33:11.57#ibcon#*after write, iclass 7, count 0 2006.201.16:33:11.57#ibcon#*before return 0, iclass 7, count 0 2006.201.16:33:11.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:11.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:11.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:33:11.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:33:11.57$vck44/va=3,8 2006.201.16:33:11.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.16:33:11.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.16:33:11.57#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:11.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:11.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:11.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:11.62#ibcon#enter wrdev, iclass 11, count 2 2006.201.16:33:11.62#ibcon#first serial, iclass 11, count 2 2006.201.16:33:11.62#ibcon#enter sib2, iclass 11, count 2 2006.201.16:33:11.62#ibcon#flushed, iclass 11, count 2 2006.201.16:33:11.62#ibcon#about to write, iclass 11, count 2 2006.201.16:33:11.62#ibcon#wrote, iclass 11, count 2 2006.201.16:33:11.62#ibcon#about to read 3, iclass 11, count 2 2006.201.16:33:11.64#ibcon#read 3, iclass 11, count 2 2006.201.16:33:11.64#ibcon#about to read 4, iclass 11, count 2 2006.201.16:33:11.64#ibcon#read 4, iclass 11, count 2 2006.201.16:33:11.64#ibcon#about to read 5, iclass 11, count 2 2006.201.16:33:11.64#ibcon#read 5, iclass 11, count 2 2006.201.16:33:11.64#ibcon#about to read 6, iclass 11, count 2 2006.201.16:33:11.64#ibcon#read 6, iclass 11, count 2 2006.201.16:33:11.64#ibcon#end of sib2, iclass 11, count 2 2006.201.16:33:11.64#ibcon#*mode == 0, iclass 11, count 2 2006.201.16:33:11.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.16:33:11.64#ibcon#[25=AT03-08\r\n] 2006.201.16:33:11.64#ibcon#*before write, iclass 11, count 2 2006.201.16:33:11.64#ibcon#enter sib2, iclass 11, count 2 2006.201.16:33:11.64#ibcon#flushed, iclass 11, count 2 2006.201.16:33:11.64#ibcon#about to write, iclass 11, count 2 2006.201.16:33:11.64#ibcon#wrote, iclass 11, count 2 2006.201.16:33:11.64#ibcon#about to read 3, iclass 11, count 2 2006.201.16:33:11.67#ibcon#read 3, iclass 11, count 2 2006.201.16:33:11.67#ibcon#about to read 4, iclass 11, count 2 2006.201.16:33:11.67#ibcon#read 4, iclass 11, count 2 2006.201.16:33:11.67#ibcon#about to read 5, iclass 11, count 2 2006.201.16:33:11.67#ibcon#read 5, iclass 11, count 2 2006.201.16:33:11.67#ibcon#about to read 6, iclass 11, count 2 2006.201.16:33:11.67#ibcon#read 6, iclass 11, count 2 2006.201.16:33:11.67#ibcon#end of sib2, iclass 11, count 2 2006.201.16:33:11.67#ibcon#*after write, iclass 11, count 2 2006.201.16:33:11.67#ibcon#*before return 0, iclass 11, count 2 2006.201.16:33:11.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:11.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:11.67#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.16:33:11.67#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:11.67#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:11.79#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:11.79#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:11.79#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:33:11.79#ibcon#first serial, iclass 11, count 0 2006.201.16:33:11.79#ibcon#enter sib2, iclass 11, count 0 2006.201.16:33:11.79#ibcon#flushed, iclass 11, count 0 2006.201.16:33:11.79#ibcon#about to write, iclass 11, count 0 2006.201.16:33:11.79#ibcon#wrote, iclass 11, count 0 2006.201.16:33:11.79#ibcon#about to read 3, iclass 11, count 0 2006.201.16:33:11.81#ibcon#read 3, iclass 11, count 0 2006.201.16:33:11.81#ibcon#about to read 4, iclass 11, count 0 2006.201.16:33:11.81#ibcon#read 4, iclass 11, count 0 2006.201.16:33:11.81#ibcon#about to read 5, iclass 11, count 0 2006.201.16:33:11.81#ibcon#read 5, iclass 11, count 0 2006.201.16:33:11.81#ibcon#about to read 6, iclass 11, count 0 2006.201.16:33:11.81#ibcon#read 6, iclass 11, count 0 2006.201.16:33:11.81#ibcon#end of sib2, iclass 11, count 0 2006.201.16:33:11.81#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:33:11.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:33:11.81#ibcon#[25=USB\r\n] 2006.201.16:33:11.81#ibcon#*before write, iclass 11, count 0 2006.201.16:33:11.81#ibcon#enter sib2, iclass 11, count 0 2006.201.16:33:11.81#ibcon#flushed, iclass 11, count 0 2006.201.16:33:11.81#ibcon#about to write, iclass 11, count 0 2006.201.16:33:11.81#ibcon#wrote, iclass 11, count 0 2006.201.16:33:11.81#ibcon#about to read 3, iclass 11, count 0 2006.201.16:33:11.84#ibcon#read 3, iclass 11, count 0 2006.201.16:33:11.84#ibcon#about to read 4, iclass 11, count 0 2006.201.16:33:11.84#ibcon#read 4, iclass 11, count 0 2006.201.16:33:11.84#ibcon#about to read 5, iclass 11, count 0 2006.201.16:33:11.84#ibcon#read 5, iclass 11, count 0 2006.201.16:33:11.84#ibcon#about to read 6, iclass 11, count 0 2006.201.16:33:11.84#ibcon#read 6, iclass 11, count 0 2006.201.16:33:11.84#ibcon#end of sib2, iclass 11, count 0 2006.201.16:33:11.84#ibcon#*after write, iclass 11, count 0 2006.201.16:33:11.84#ibcon#*before return 0, iclass 11, count 0 2006.201.16:33:11.84#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:11.84#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:11.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:33:11.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:33:11.84$vck44/valo=4,624.99 2006.201.16:33:11.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.16:33:11.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.16:33:11.84#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:11.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:11.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:11.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:11.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:33:11.84#ibcon#first serial, iclass 13, count 0 2006.201.16:33:11.84#ibcon#enter sib2, iclass 13, count 0 2006.201.16:33:11.84#ibcon#flushed, iclass 13, count 0 2006.201.16:33:11.84#ibcon#about to write, iclass 13, count 0 2006.201.16:33:11.84#ibcon#wrote, iclass 13, count 0 2006.201.16:33:11.84#ibcon#about to read 3, iclass 13, count 0 2006.201.16:33:11.86#ibcon#read 3, iclass 13, count 0 2006.201.16:33:11.86#ibcon#about to read 4, iclass 13, count 0 2006.201.16:33:11.86#ibcon#read 4, iclass 13, count 0 2006.201.16:33:11.86#ibcon#about to read 5, iclass 13, count 0 2006.201.16:33:11.86#ibcon#read 5, iclass 13, count 0 2006.201.16:33:11.86#ibcon#about to read 6, iclass 13, count 0 2006.201.16:33:11.86#ibcon#read 6, iclass 13, count 0 2006.201.16:33:11.86#ibcon#end of sib2, iclass 13, count 0 2006.201.16:33:11.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:33:11.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:33:11.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:33:11.86#ibcon#*before write, iclass 13, count 0 2006.201.16:33:11.86#ibcon#enter sib2, iclass 13, count 0 2006.201.16:33:11.86#ibcon#flushed, iclass 13, count 0 2006.201.16:33:11.86#ibcon#about to write, iclass 13, count 0 2006.201.16:33:11.86#ibcon#wrote, iclass 13, count 0 2006.201.16:33:11.86#ibcon#about to read 3, iclass 13, count 0 2006.201.16:33:11.90#ibcon#read 3, iclass 13, count 0 2006.201.16:33:11.90#ibcon#about to read 4, iclass 13, count 0 2006.201.16:33:11.90#ibcon#read 4, iclass 13, count 0 2006.201.16:33:11.90#ibcon#about to read 5, iclass 13, count 0 2006.201.16:33:11.90#ibcon#read 5, iclass 13, count 0 2006.201.16:33:11.90#ibcon#about to read 6, iclass 13, count 0 2006.201.16:33:11.90#ibcon#read 6, iclass 13, count 0 2006.201.16:33:11.90#ibcon#end of sib2, iclass 13, count 0 2006.201.16:33:11.90#ibcon#*after write, iclass 13, count 0 2006.201.16:33:11.90#ibcon#*before return 0, iclass 13, count 0 2006.201.16:33:11.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:11.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:11.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:33:11.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:33:11.90$vck44/va=4,7 2006.201.16:33:11.90#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.16:33:11.90#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.16:33:11.90#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:11.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:11.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:11.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:11.96#ibcon#enter wrdev, iclass 15, count 2 2006.201.16:33:11.96#ibcon#first serial, iclass 15, count 2 2006.201.16:33:11.96#ibcon#enter sib2, iclass 15, count 2 2006.201.16:33:11.96#ibcon#flushed, iclass 15, count 2 2006.201.16:33:11.96#ibcon#about to write, iclass 15, count 2 2006.201.16:33:11.96#ibcon#wrote, iclass 15, count 2 2006.201.16:33:11.96#ibcon#about to read 3, iclass 15, count 2 2006.201.16:33:11.98#ibcon#read 3, iclass 15, count 2 2006.201.16:33:11.98#ibcon#about to read 4, iclass 15, count 2 2006.201.16:33:11.98#ibcon#read 4, iclass 15, count 2 2006.201.16:33:11.98#ibcon#about to read 5, iclass 15, count 2 2006.201.16:33:11.98#ibcon#read 5, iclass 15, count 2 2006.201.16:33:11.98#ibcon#about to read 6, iclass 15, count 2 2006.201.16:33:11.98#ibcon#read 6, iclass 15, count 2 2006.201.16:33:11.98#ibcon#end of sib2, iclass 15, count 2 2006.201.16:33:11.98#ibcon#*mode == 0, iclass 15, count 2 2006.201.16:33:11.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.16:33:11.98#ibcon#[25=AT04-07\r\n] 2006.201.16:33:11.98#ibcon#*before write, iclass 15, count 2 2006.201.16:33:11.98#ibcon#enter sib2, iclass 15, count 2 2006.201.16:33:11.98#ibcon#flushed, iclass 15, count 2 2006.201.16:33:11.98#ibcon#about to write, iclass 15, count 2 2006.201.16:33:11.98#ibcon#wrote, iclass 15, count 2 2006.201.16:33:11.98#ibcon#about to read 3, iclass 15, count 2 2006.201.16:33:12.01#ibcon#read 3, iclass 15, count 2 2006.201.16:33:12.01#ibcon#about to read 4, iclass 15, count 2 2006.201.16:33:12.01#ibcon#read 4, iclass 15, count 2 2006.201.16:33:12.01#ibcon#about to read 5, iclass 15, count 2 2006.201.16:33:12.01#ibcon#read 5, iclass 15, count 2 2006.201.16:33:12.01#ibcon#about to read 6, iclass 15, count 2 2006.201.16:33:12.01#ibcon#read 6, iclass 15, count 2 2006.201.16:33:12.01#ibcon#end of sib2, iclass 15, count 2 2006.201.16:33:12.01#ibcon#*after write, iclass 15, count 2 2006.201.16:33:12.01#ibcon#*before return 0, iclass 15, count 2 2006.201.16:33:12.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:12.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:12.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.16:33:12.01#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:12.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:12.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:12.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:12.13#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:33:12.13#ibcon#first serial, iclass 15, count 0 2006.201.16:33:12.13#ibcon#enter sib2, iclass 15, count 0 2006.201.16:33:12.13#ibcon#flushed, iclass 15, count 0 2006.201.16:33:12.13#ibcon#about to write, iclass 15, count 0 2006.201.16:33:12.13#ibcon#wrote, iclass 15, count 0 2006.201.16:33:12.13#ibcon#about to read 3, iclass 15, count 0 2006.201.16:33:12.15#ibcon#read 3, iclass 15, count 0 2006.201.16:33:12.15#ibcon#about to read 4, iclass 15, count 0 2006.201.16:33:12.15#ibcon#read 4, iclass 15, count 0 2006.201.16:33:12.15#ibcon#about to read 5, iclass 15, count 0 2006.201.16:33:12.15#ibcon#read 5, iclass 15, count 0 2006.201.16:33:12.15#ibcon#about to read 6, iclass 15, count 0 2006.201.16:33:12.15#ibcon#read 6, iclass 15, count 0 2006.201.16:33:12.15#ibcon#end of sib2, iclass 15, count 0 2006.201.16:33:12.15#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:33:12.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:33:12.15#ibcon#[25=USB\r\n] 2006.201.16:33:12.15#ibcon#*before write, iclass 15, count 0 2006.201.16:33:12.15#ibcon#enter sib2, iclass 15, count 0 2006.201.16:33:12.15#ibcon#flushed, iclass 15, count 0 2006.201.16:33:12.15#ibcon#about to write, iclass 15, count 0 2006.201.16:33:12.15#ibcon#wrote, iclass 15, count 0 2006.201.16:33:12.15#ibcon#about to read 3, iclass 15, count 0 2006.201.16:33:12.18#ibcon#read 3, iclass 15, count 0 2006.201.16:33:12.18#ibcon#about to read 4, iclass 15, count 0 2006.201.16:33:12.18#ibcon#read 4, iclass 15, count 0 2006.201.16:33:12.18#ibcon#about to read 5, iclass 15, count 0 2006.201.16:33:12.18#ibcon#read 5, iclass 15, count 0 2006.201.16:33:12.18#ibcon#about to read 6, iclass 15, count 0 2006.201.16:33:12.18#ibcon#read 6, iclass 15, count 0 2006.201.16:33:12.18#ibcon#end of sib2, iclass 15, count 0 2006.201.16:33:12.18#ibcon#*after write, iclass 15, count 0 2006.201.16:33:12.18#ibcon#*before return 0, iclass 15, count 0 2006.201.16:33:12.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:12.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:12.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:33:12.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:33:12.18$vck44/valo=5,734.99 2006.201.16:33:12.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.16:33:12.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.16:33:12.18#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:12.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:12.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:12.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:12.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:33:12.18#ibcon#first serial, iclass 17, count 0 2006.201.16:33:12.18#ibcon#enter sib2, iclass 17, count 0 2006.201.16:33:12.18#ibcon#flushed, iclass 17, count 0 2006.201.16:33:12.18#ibcon#about to write, iclass 17, count 0 2006.201.16:33:12.18#ibcon#wrote, iclass 17, count 0 2006.201.16:33:12.18#ibcon#about to read 3, iclass 17, count 0 2006.201.16:33:12.20#ibcon#read 3, iclass 17, count 0 2006.201.16:33:12.20#ibcon#about to read 4, iclass 17, count 0 2006.201.16:33:12.20#ibcon#read 4, iclass 17, count 0 2006.201.16:33:12.20#ibcon#about to read 5, iclass 17, count 0 2006.201.16:33:12.20#ibcon#read 5, iclass 17, count 0 2006.201.16:33:12.20#ibcon#about to read 6, iclass 17, count 0 2006.201.16:33:12.20#ibcon#read 6, iclass 17, count 0 2006.201.16:33:12.20#ibcon#end of sib2, iclass 17, count 0 2006.201.16:33:12.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:33:12.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:33:12.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:33:12.20#ibcon#*before write, iclass 17, count 0 2006.201.16:33:12.20#ibcon#enter sib2, iclass 17, count 0 2006.201.16:33:12.20#ibcon#flushed, iclass 17, count 0 2006.201.16:33:12.20#ibcon#about to write, iclass 17, count 0 2006.201.16:33:12.20#ibcon#wrote, iclass 17, count 0 2006.201.16:33:12.20#ibcon#about to read 3, iclass 17, count 0 2006.201.16:33:12.24#ibcon#read 3, iclass 17, count 0 2006.201.16:33:12.24#ibcon#about to read 4, iclass 17, count 0 2006.201.16:33:12.24#ibcon#read 4, iclass 17, count 0 2006.201.16:33:12.24#ibcon#about to read 5, iclass 17, count 0 2006.201.16:33:12.24#ibcon#read 5, iclass 17, count 0 2006.201.16:33:12.24#ibcon#about to read 6, iclass 17, count 0 2006.201.16:33:12.24#ibcon#read 6, iclass 17, count 0 2006.201.16:33:12.24#ibcon#end of sib2, iclass 17, count 0 2006.201.16:33:12.24#ibcon#*after write, iclass 17, count 0 2006.201.16:33:12.24#ibcon#*before return 0, iclass 17, count 0 2006.201.16:33:12.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:12.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:12.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:33:12.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:33:12.24$vck44/va=5,4 2006.201.16:33:12.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.16:33:12.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.16:33:12.24#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:12.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:12.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:12.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:12.30#ibcon#enter wrdev, iclass 19, count 2 2006.201.16:33:12.30#ibcon#first serial, iclass 19, count 2 2006.201.16:33:12.30#ibcon#enter sib2, iclass 19, count 2 2006.201.16:33:12.30#ibcon#flushed, iclass 19, count 2 2006.201.16:33:12.30#ibcon#about to write, iclass 19, count 2 2006.201.16:33:12.30#ibcon#wrote, iclass 19, count 2 2006.201.16:33:12.30#ibcon#about to read 3, iclass 19, count 2 2006.201.16:33:12.32#ibcon#read 3, iclass 19, count 2 2006.201.16:33:12.32#ibcon#about to read 4, iclass 19, count 2 2006.201.16:33:12.32#ibcon#read 4, iclass 19, count 2 2006.201.16:33:12.32#ibcon#about to read 5, iclass 19, count 2 2006.201.16:33:12.32#ibcon#read 5, iclass 19, count 2 2006.201.16:33:12.32#ibcon#about to read 6, iclass 19, count 2 2006.201.16:33:12.32#ibcon#read 6, iclass 19, count 2 2006.201.16:33:12.32#ibcon#end of sib2, iclass 19, count 2 2006.201.16:33:12.32#ibcon#*mode == 0, iclass 19, count 2 2006.201.16:33:12.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.16:33:12.32#ibcon#[25=AT05-04\r\n] 2006.201.16:33:12.32#ibcon#*before write, iclass 19, count 2 2006.201.16:33:12.32#ibcon#enter sib2, iclass 19, count 2 2006.201.16:33:12.32#ibcon#flushed, iclass 19, count 2 2006.201.16:33:12.32#ibcon#about to write, iclass 19, count 2 2006.201.16:33:12.32#ibcon#wrote, iclass 19, count 2 2006.201.16:33:12.32#ibcon#about to read 3, iclass 19, count 2 2006.201.16:33:12.35#ibcon#read 3, iclass 19, count 2 2006.201.16:33:12.35#ibcon#about to read 4, iclass 19, count 2 2006.201.16:33:12.35#ibcon#read 4, iclass 19, count 2 2006.201.16:33:12.35#ibcon#about to read 5, iclass 19, count 2 2006.201.16:33:12.35#ibcon#read 5, iclass 19, count 2 2006.201.16:33:12.35#ibcon#about to read 6, iclass 19, count 2 2006.201.16:33:12.35#ibcon#read 6, iclass 19, count 2 2006.201.16:33:12.35#ibcon#end of sib2, iclass 19, count 2 2006.201.16:33:12.35#ibcon#*after write, iclass 19, count 2 2006.201.16:33:12.35#ibcon#*before return 0, iclass 19, count 2 2006.201.16:33:12.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:12.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:12.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.16:33:12.35#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:12.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:12.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:12.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:12.47#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:33:12.47#ibcon#first serial, iclass 19, count 0 2006.201.16:33:12.47#ibcon#enter sib2, iclass 19, count 0 2006.201.16:33:12.47#ibcon#flushed, iclass 19, count 0 2006.201.16:33:12.47#ibcon#about to write, iclass 19, count 0 2006.201.16:33:12.47#ibcon#wrote, iclass 19, count 0 2006.201.16:33:12.47#ibcon#about to read 3, iclass 19, count 0 2006.201.16:33:12.49#ibcon#read 3, iclass 19, count 0 2006.201.16:33:12.49#ibcon#about to read 4, iclass 19, count 0 2006.201.16:33:12.49#ibcon#read 4, iclass 19, count 0 2006.201.16:33:12.49#ibcon#about to read 5, iclass 19, count 0 2006.201.16:33:12.49#ibcon#read 5, iclass 19, count 0 2006.201.16:33:12.49#ibcon#about to read 6, iclass 19, count 0 2006.201.16:33:12.49#ibcon#read 6, iclass 19, count 0 2006.201.16:33:12.49#ibcon#end of sib2, iclass 19, count 0 2006.201.16:33:12.49#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:33:12.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:33:12.49#ibcon#[25=USB\r\n] 2006.201.16:33:12.49#ibcon#*before write, iclass 19, count 0 2006.201.16:33:12.49#ibcon#enter sib2, iclass 19, count 0 2006.201.16:33:12.49#ibcon#flushed, iclass 19, count 0 2006.201.16:33:12.49#ibcon#about to write, iclass 19, count 0 2006.201.16:33:12.49#ibcon#wrote, iclass 19, count 0 2006.201.16:33:12.49#ibcon#about to read 3, iclass 19, count 0 2006.201.16:33:12.52#ibcon#read 3, iclass 19, count 0 2006.201.16:33:12.52#ibcon#about to read 4, iclass 19, count 0 2006.201.16:33:12.52#ibcon#read 4, iclass 19, count 0 2006.201.16:33:12.52#ibcon#about to read 5, iclass 19, count 0 2006.201.16:33:12.52#ibcon#read 5, iclass 19, count 0 2006.201.16:33:12.52#ibcon#about to read 6, iclass 19, count 0 2006.201.16:33:12.52#ibcon#read 6, iclass 19, count 0 2006.201.16:33:12.52#ibcon#end of sib2, iclass 19, count 0 2006.201.16:33:12.52#ibcon#*after write, iclass 19, count 0 2006.201.16:33:12.52#ibcon#*before return 0, iclass 19, count 0 2006.201.16:33:12.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:12.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:12.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:33:12.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:33:12.52$vck44/valo=6,814.99 2006.201.16:33:12.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.16:33:12.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.16:33:12.52#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:12.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:12.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:12.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:12.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:33:12.52#ibcon#first serial, iclass 21, count 0 2006.201.16:33:12.52#ibcon#enter sib2, iclass 21, count 0 2006.201.16:33:12.52#ibcon#flushed, iclass 21, count 0 2006.201.16:33:12.52#ibcon#about to write, iclass 21, count 0 2006.201.16:33:12.52#ibcon#wrote, iclass 21, count 0 2006.201.16:33:12.52#ibcon#about to read 3, iclass 21, count 0 2006.201.16:33:12.54#ibcon#read 3, iclass 21, count 0 2006.201.16:33:12.54#ibcon#about to read 4, iclass 21, count 0 2006.201.16:33:12.54#ibcon#read 4, iclass 21, count 0 2006.201.16:33:12.54#ibcon#about to read 5, iclass 21, count 0 2006.201.16:33:12.54#ibcon#read 5, iclass 21, count 0 2006.201.16:33:12.54#ibcon#about to read 6, iclass 21, count 0 2006.201.16:33:12.54#ibcon#read 6, iclass 21, count 0 2006.201.16:33:12.54#ibcon#end of sib2, iclass 21, count 0 2006.201.16:33:12.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:33:12.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:33:12.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:33:12.54#ibcon#*before write, iclass 21, count 0 2006.201.16:33:12.54#ibcon#enter sib2, iclass 21, count 0 2006.201.16:33:12.54#ibcon#flushed, iclass 21, count 0 2006.201.16:33:12.54#ibcon#about to write, iclass 21, count 0 2006.201.16:33:12.54#ibcon#wrote, iclass 21, count 0 2006.201.16:33:12.54#ibcon#about to read 3, iclass 21, count 0 2006.201.16:33:12.58#ibcon#read 3, iclass 21, count 0 2006.201.16:33:12.58#ibcon#about to read 4, iclass 21, count 0 2006.201.16:33:12.58#ibcon#read 4, iclass 21, count 0 2006.201.16:33:12.58#ibcon#about to read 5, iclass 21, count 0 2006.201.16:33:12.58#ibcon#read 5, iclass 21, count 0 2006.201.16:33:12.58#ibcon#about to read 6, iclass 21, count 0 2006.201.16:33:12.58#ibcon#read 6, iclass 21, count 0 2006.201.16:33:12.58#ibcon#end of sib2, iclass 21, count 0 2006.201.16:33:12.58#ibcon#*after write, iclass 21, count 0 2006.201.16:33:12.58#ibcon#*before return 0, iclass 21, count 0 2006.201.16:33:12.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:12.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:12.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:33:12.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:33:12.58$vck44/va=6,5 2006.201.16:33:12.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.16:33:12.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.16:33:12.58#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:12.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:12.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:12.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:12.64#ibcon#enter wrdev, iclass 23, count 2 2006.201.16:33:12.64#ibcon#first serial, iclass 23, count 2 2006.201.16:33:12.64#ibcon#enter sib2, iclass 23, count 2 2006.201.16:33:12.64#ibcon#flushed, iclass 23, count 2 2006.201.16:33:12.64#ibcon#about to write, iclass 23, count 2 2006.201.16:33:12.64#ibcon#wrote, iclass 23, count 2 2006.201.16:33:12.64#ibcon#about to read 3, iclass 23, count 2 2006.201.16:33:12.66#ibcon#read 3, iclass 23, count 2 2006.201.16:33:12.66#ibcon#about to read 4, iclass 23, count 2 2006.201.16:33:12.66#ibcon#read 4, iclass 23, count 2 2006.201.16:33:12.66#ibcon#about to read 5, iclass 23, count 2 2006.201.16:33:12.66#ibcon#read 5, iclass 23, count 2 2006.201.16:33:12.66#ibcon#about to read 6, iclass 23, count 2 2006.201.16:33:12.66#ibcon#read 6, iclass 23, count 2 2006.201.16:33:12.66#ibcon#end of sib2, iclass 23, count 2 2006.201.16:33:12.66#ibcon#*mode == 0, iclass 23, count 2 2006.201.16:33:12.66#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.16:33:12.66#ibcon#[25=AT06-05\r\n] 2006.201.16:33:12.66#ibcon#*before write, iclass 23, count 2 2006.201.16:33:12.66#ibcon#enter sib2, iclass 23, count 2 2006.201.16:33:12.66#ibcon#flushed, iclass 23, count 2 2006.201.16:33:12.66#ibcon#about to write, iclass 23, count 2 2006.201.16:33:12.66#ibcon#wrote, iclass 23, count 2 2006.201.16:33:12.66#ibcon#about to read 3, iclass 23, count 2 2006.201.16:33:12.69#ibcon#read 3, iclass 23, count 2 2006.201.16:33:12.69#ibcon#about to read 4, iclass 23, count 2 2006.201.16:33:12.69#ibcon#read 4, iclass 23, count 2 2006.201.16:33:12.69#ibcon#about to read 5, iclass 23, count 2 2006.201.16:33:12.69#ibcon#read 5, iclass 23, count 2 2006.201.16:33:12.69#ibcon#about to read 6, iclass 23, count 2 2006.201.16:33:12.69#ibcon#read 6, iclass 23, count 2 2006.201.16:33:12.69#ibcon#end of sib2, iclass 23, count 2 2006.201.16:33:12.69#ibcon#*after write, iclass 23, count 2 2006.201.16:33:12.69#ibcon#*before return 0, iclass 23, count 2 2006.201.16:33:12.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:12.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:12.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.16:33:12.69#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:12.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:12.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:12.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:12.81#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:33:12.81#ibcon#first serial, iclass 23, count 0 2006.201.16:33:12.81#ibcon#enter sib2, iclass 23, count 0 2006.201.16:33:12.81#ibcon#flushed, iclass 23, count 0 2006.201.16:33:12.81#ibcon#about to write, iclass 23, count 0 2006.201.16:33:12.81#ibcon#wrote, iclass 23, count 0 2006.201.16:33:12.81#ibcon#about to read 3, iclass 23, count 0 2006.201.16:33:12.83#ibcon#read 3, iclass 23, count 0 2006.201.16:33:12.83#ibcon#about to read 4, iclass 23, count 0 2006.201.16:33:12.83#ibcon#read 4, iclass 23, count 0 2006.201.16:33:12.83#ibcon#about to read 5, iclass 23, count 0 2006.201.16:33:12.83#ibcon#read 5, iclass 23, count 0 2006.201.16:33:12.83#ibcon#about to read 6, iclass 23, count 0 2006.201.16:33:12.83#ibcon#read 6, iclass 23, count 0 2006.201.16:33:12.83#ibcon#end of sib2, iclass 23, count 0 2006.201.16:33:12.83#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:33:12.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:33:12.83#ibcon#[25=USB\r\n] 2006.201.16:33:12.83#ibcon#*before write, iclass 23, count 0 2006.201.16:33:12.83#ibcon#enter sib2, iclass 23, count 0 2006.201.16:33:12.83#ibcon#flushed, iclass 23, count 0 2006.201.16:33:12.83#ibcon#about to write, iclass 23, count 0 2006.201.16:33:12.83#ibcon#wrote, iclass 23, count 0 2006.201.16:33:12.83#ibcon#about to read 3, iclass 23, count 0 2006.201.16:33:12.86#ibcon#read 3, iclass 23, count 0 2006.201.16:33:12.86#ibcon#about to read 4, iclass 23, count 0 2006.201.16:33:12.86#ibcon#read 4, iclass 23, count 0 2006.201.16:33:12.86#ibcon#about to read 5, iclass 23, count 0 2006.201.16:33:12.86#ibcon#read 5, iclass 23, count 0 2006.201.16:33:12.86#ibcon#about to read 6, iclass 23, count 0 2006.201.16:33:12.86#ibcon#read 6, iclass 23, count 0 2006.201.16:33:12.86#ibcon#end of sib2, iclass 23, count 0 2006.201.16:33:12.86#ibcon#*after write, iclass 23, count 0 2006.201.16:33:12.86#ibcon#*before return 0, iclass 23, count 0 2006.201.16:33:12.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:12.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:12.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:33:12.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:33:12.86$vck44/valo=7,864.99 2006.201.16:33:12.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.16:33:12.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.16:33:12.86#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:12.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:12.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:12.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:12.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:33:12.86#ibcon#first serial, iclass 25, count 0 2006.201.16:33:12.86#ibcon#enter sib2, iclass 25, count 0 2006.201.16:33:12.86#ibcon#flushed, iclass 25, count 0 2006.201.16:33:12.86#ibcon#about to write, iclass 25, count 0 2006.201.16:33:12.86#ibcon#wrote, iclass 25, count 0 2006.201.16:33:12.86#ibcon#about to read 3, iclass 25, count 0 2006.201.16:33:12.88#ibcon#read 3, iclass 25, count 0 2006.201.16:33:12.88#ibcon#about to read 4, iclass 25, count 0 2006.201.16:33:12.88#ibcon#read 4, iclass 25, count 0 2006.201.16:33:12.88#ibcon#about to read 5, iclass 25, count 0 2006.201.16:33:12.88#ibcon#read 5, iclass 25, count 0 2006.201.16:33:12.88#ibcon#about to read 6, iclass 25, count 0 2006.201.16:33:12.88#ibcon#read 6, iclass 25, count 0 2006.201.16:33:12.88#ibcon#end of sib2, iclass 25, count 0 2006.201.16:33:12.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:33:12.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:33:12.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:33:12.88#ibcon#*before write, iclass 25, count 0 2006.201.16:33:12.88#ibcon#enter sib2, iclass 25, count 0 2006.201.16:33:12.88#ibcon#flushed, iclass 25, count 0 2006.201.16:33:12.88#ibcon#about to write, iclass 25, count 0 2006.201.16:33:12.88#ibcon#wrote, iclass 25, count 0 2006.201.16:33:12.88#ibcon#about to read 3, iclass 25, count 0 2006.201.16:33:12.92#ibcon#read 3, iclass 25, count 0 2006.201.16:33:12.92#ibcon#about to read 4, iclass 25, count 0 2006.201.16:33:12.92#ibcon#read 4, iclass 25, count 0 2006.201.16:33:12.92#ibcon#about to read 5, iclass 25, count 0 2006.201.16:33:12.92#ibcon#read 5, iclass 25, count 0 2006.201.16:33:12.92#ibcon#about to read 6, iclass 25, count 0 2006.201.16:33:12.92#ibcon#read 6, iclass 25, count 0 2006.201.16:33:12.92#ibcon#end of sib2, iclass 25, count 0 2006.201.16:33:12.92#ibcon#*after write, iclass 25, count 0 2006.201.16:33:12.92#ibcon#*before return 0, iclass 25, count 0 2006.201.16:33:12.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:12.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:12.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:33:12.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:33:12.92$vck44/va=7,5 2006.201.16:33:12.92#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.16:33:12.92#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.16:33:12.92#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:12.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:12.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:12.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:12.98#ibcon#enter wrdev, iclass 27, count 2 2006.201.16:33:12.98#ibcon#first serial, iclass 27, count 2 2006.201.16:33:12.98#ibcon#enter sib2, iclass 27, count 2 2006.201.16:33:12.98#ibcon#flushed, iclass 27, count 2 2006.201.16:33:12.98#ibcon#about to write, iclass 27, count 2 2006.201.16:33:12.98#ibcon#wrote, iclass 27, count 2 2006.201.16:33:12.98#ibcon#about to read 3, iclass 27, count 2 2006.201.16:33:13.00#ibcon#read 3, iclass 27, count 2 2006.201.16:33:13.00#ibcon#about to read 4, iclass 27, count 2 2006.201.16:33:13.00#ibcon#read 4, iclass 27, count 2 2006.201.16:33:13.00#ibcon#about to read 5, iclass 27, count 2 2006.201.16:33:13.00#ibcon#read 5, iclass 27, count 2 2006.201.16:33:13.00#ibcon#about to read 6, iclass 27, count 2 2006.201.16:33:13.00#ibcon#read 6, iclass 27, count 2 2006.201.16:33:13.00#ibcon#end of sib2, iclass 27, count 2 2006.201.16:33:13.00#ibcon#*mode == 0, iclass 27, count 2 2006.201.16:33:13.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.16:33:13.00#ibcon#[25=AT07-05\r\n] 2006.201.16:33:13.00#ibcon#*before write, iclass 27, count 2 2006.201.16:33:13.00#ibcon#enter sib2, iclass 27, count 2 2006.201.16:33:13.00#ibcon#flushed, iclass 27, count 2 2006.201.16:33:13.00#ibcon#about to write, iclass 27, count 2 2006.201.16:33:13.00#ibcon#wrote, iclass 27, count 2 2006.201.16:33:13.00#ibcon#about to read 3, iclass 27, count 2 2006.201.16:33:13.03#ibcon#read 3, iclass 27, count 2 2006.201.16:33:13.03#ibcon#about to read 4, iclass 27, count 2 2006.201.16:33:13.03#ibcon#read 4, iclass 27, count 2 2006.201.16:33:13.03#ibcon#about to read 5, iclass 27, count 2 2006.201.16:33:13.03#ibcon#read 5, iclass 27, count 2 2006.201.16:33:13.03#ibcon#about to read 6, iclass 27, count 2 2006.201.16:33:13.03#ibcon#read 6, iclass 27, count 2 2006.201.16:33:13.03#ibcon#end of sib2, iclass 27, count 2 2006.201.16:33:13.03#ibcon#*after write, iclass 27, count 2 2006.201.16:33:13.03#ibcon#*before return 0, iclass 27, count 2 2006.201.16:33:13.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:13.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:13.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.16:33:13.03#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:13.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:13.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:13.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:13.15#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:33:13.15#ibcon#first serial, iclass 27, count 0 2006.201.16:33:13.15#ibcon#enter sib2, iclass 27, count 0 2006.201.16:33:13.15#ibcon#flushed, iclass 27, count 0 2006.201.16:33:13.15#ibcon#about to write, iclass 27, count 0 2006.201.16:33:13.15#ibcon#wrote, iclass 27, count 0 2006.201.16:33:13.15#ibcon#about to read 3, iclass 27, count 0 2006.201.16:33:13.17#ibcon#read 3, iclass 27, count 0 2006.201.16:33:13.17#ibcon#about to read 4, iclass 27, count 0 2006.201.16:33:13.17#ibcon#read 4, iclass 27, count 0 2006.201.16:33:13.17#ibcon#about to read 5, iclass 27, count 0 2006.201.16:33:13.17#ibcon#read 5, iclass 27, count 0 2006.201.16:33:13.17#ibcon#about to read 6, iclass 27, count 0 2006.201.16:33:13.17#ibcon#read 6, iclass 27, count 0 2006.201.16:33:13.17#ibcon#end of sib2, iclass 27, count 0 2006.201.16:33:13.17#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:33:13.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:33:13.17#ibcon#[25=USB\r\n] 2006.201.16:33:13.17#ibcon#*before write, iclass 27, count 0 2006.201.16:33:13.17#ibcon#enter sib2, iclass 27, count 0 2006.201.16:33:13.17#ibcon#flushed, iclass 27, count 0 2006.201.16:33:13.17#ibcon#about to write, iclass 27, count 0 2006.201.16:33:13.17#ibcon#wrote, iclass 27, count 0 2006.201.16:33:13.17#ibcon#about to read 3, iclass 27, count 0 2006.201.16:33:13.20#ibcon#read 3, iclass 27, count 0 2006.201.16:33:13.20#ibcon#about to read 4, iclass 27, count 0 2006.201.16:33:13.20#ibcon#read 4, iclass 27, count 0 2006.201.16:33:13.20#ibcon#about to read 5, iclass 27, count 0 2006.201.16:33:13.20#ibcon#read 5, iclass 27, count 0 2006.201.16:33:13.20#ibcon#about to read 6, iclass 27, count 0 2006.201.16:33:13.20#ibcon#read 6, iclass 27, count 0 2006.201.16:33:13.20#ibcon#end of sib2, iclass 27, count 0 2006.201.16:33:13.20#ibcon#*after write, iclass 27, count 0 2006.201.16:33:13.20#ibcon#*before return 0, iclass 27, count 0 2006.201.16:33:13.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:13.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:13.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:33:13.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:33:13.20$vck44/valo=8,884.99 2006.201.16:33:13.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.16:33:13.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.16:33:13.20#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:13.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:33:13.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:33:13.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:33:13.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:33:13.20#ibcon#first serial, iclass 29, count 0 2006.201.16:33:13.20#ibcon#enter sib2, iclass 29, count 0 2006.201.16:33:13.20#ibcon#flushed, iclass 29, count 0 2006.201.16:33:13.20#ibcon#about to write, iclass 29, count 0 2006.201.16:33:13.20#ibcon#wrote, iclass 29, count 0 2006.201.16:33:13.20#ibcon#about to read 3, iclass 29, count 0 2006.201.16:33:13.22#ibcon#read 3, iclass 29, count 0 2006.201.16:33:13.22#ibcon#about to read 4, iclass 29, count 0 2006.201.16:33:13.22#ibcon#read 4, iclass 29, count 0 2006.201.16:33:13.22#ibcon#about to read 5, iclass 29, count 0 2006.201.16:33:13.22#ibcon#read 5, iclass 29, count 0 2006.201.16:33:13.22#ibcon#about to read 6, iclass 29, count 0 2006.201.16:33:13.22#ibcon#read 6, iclass 29, count 0 2006.201.16:33:13.22#ibcon#end of sib2, iclass 29, count 0 2006.201.16:33:13.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:33:13.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:33:13.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:33:13.22#ibcon#*before write, iclass 29, count 0 2006.201.16:33:13.22#ibcon#enter sib2, iclass 29, count 0 2006.201.16:33:13.22#ibcon#flushed, iclass 29, count 0 2006.201.16:33:13.22#ibcon#about to write, iclass 29, count 0 2006.201.16:33:13.22#ibcon#wrote, iclass 29, count 0 2006.201.16:33:13.22#ibcon#about to read 3, iclass 29, count 0 2006.201.16:33:13.26#ibcon#read 3, iclass 29, count 0 2006.201.16:33:13.26#ibcon#about to read 4, iclass 29, count 0 2006.201.16:33:13.26#ibcon#read 4, iclass 29, count 0 2006.201.16:33:13.26#ibcon#about to read 5, iclass 29, count 0 2006.201.16:33:13.26#ibcon#read 5, iclass 29, count 0 2006.201.16:33:13.26#ibcon#about to read 6, iclass 29, count 0 2006.201.16:33:13.26#ibcon#read 6, iclass 29, count 0 2006.201.16:33:13.26#ibcon#end of sib2, iclass 29, count 0 2006.201.16:33:13.26#ibcon#*after write, iclass 29, count 0 2006.201.16:33:13.26#ibcon#*before return 0, iclass 29, count 0 2006.201.16:33:13.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:33:13.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:33:13.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:33:13.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:33:13.26$vck44/va=8,4 2006.201.16:33:13.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.16:33:13.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.16:33:13.26#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:13.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:33:13.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:33:13.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:33:13.32#ibcon#enter wrdev, iclass 31, count 2 2006.201.16:33:13.32#ibcon#first serial, iclass 31, count 2 2006.201.16:33:13.32#ibcon#enter sib2, iclass 31, count 2 2006.201.16:33:13.32#ibcon#flushed, iclass 31, count 2 2006.201.16:33:13.32#ibcon#about to write, iclass 31, count 2 2006.201.16:33:13.32#ibcon#wrote, iclass 31, count 2 2006.201.16:33:13.32#ibcon#about to read 3, iclass 31, count 2 2006.201.16:33:13.34#ibcon#read 3, iclass 31, count 2 2006.201.16:33:13.34#ibcon#about to read 4, iclass 31, count 2 2006.201.16:33:13.34#ibcon#read 4, iclass 31, count 2 2006.201.16:33:13.34#ibcon#about to read 5, iclass 31, count 2 2006.201.16:33:13.34#ibcon#read 5, iclass 31, count 2 2006.201.16:33:13.34#ibcon#about to read 6, iclass 31, count 2 2006.201.16:33:13.34#ibcon#read 6, iclass 31, count 2 2006.201.16:33:13.34#ibcon#end of sib2, iclass 31, count 2 2006.201.16:33:13.34#ibcon#*mode == 0, iclass 31, count 2 2006.201.16:33:13.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.16:33:13.34#ibcon#[25=AT08-04\r\n] 2006.201.16:33:13.34#ibcon#*before write, iclass 31, count 2 2006.201.16:33:13.34#ibcon#enter sib2, iclass 31, count 2 2006.201.16:33:13.34#ibcon#flushed, iclass 31, count 2 2006.201.16:33:13.34#ibcon#about to write, iclass 31, count 2 2006.201.16:33:13.34#ibcon#wrote, iclass 31, count 2 2006.201.16:33:13.34#ibcon#about to read 3, iclass 31, count 2 2006.201.16:33:13.37#ibcon#read 3, iclass 31, count 2 2006.201.16:33:13.37#ibcon#about to read 4, iclass 31, count 2 2006.201.16:33:13.37#ibcon#read 4, iclass 31, count 2 2006.201.16:33:13.37#ibcon#about to read 5, iclass 31, count 2 2006.201.16:33:13.37#ibcon#read 5, iclass 31, count 2 2006.201.16:33:13.37#ibcon#about to read 6, iclass 31, count 2 2006.201.16:33:13.37#ibcon#read 6, iclass 31, count 2 2006.201.16:33:13.37#ibcon#end of sib2, iclass 31, count 2 2006.201.16:33:13.37#ibcon#*after write, iclass 31, count 2 2006.201.16:33:13.37#ibcon#*before return 0, iclass 31, count 2 2006.201.16:33:13.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:33:13.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:33:13.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.16:33:13.37#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:13.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:33:13.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:33:13.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:33:13.49#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:33:13.49#ibcon#first serial, iclass 31, count 0 2006.201.16:33:13.49#ibcon#enter sib2, iclass 31, count 0 2006.201.16:33:13.49#ibcon#flushed, iclass 31, count 0 2006.201.16:33:13.49#ibcon#about to write, iclass 31, count 0 2006.201.16:33:13.49#ibcon#wrote, iclass 31, count 0 2006.201.16:33:13.49#ibcon#about to read 3, iclass 31, count 0 2006.201.16:33:13.51#ibcon#read 3, iclass 31, count 0 2006.201.16:33:13.51#ibcon#about to read 4, iclass 31, count 0 2006.201.16:33:13.51#ibcon#read 4, iclass 31, count 0 2006.201.16:33:13.51#ibcon#about to read 5, iclass 31, count 0 2006.201.16:33:13.51#ibcon#read 5, iclass 31, count 0 2006.201.16:33:13.51#ibcon#about to read 6, iclass 31, count 0 2006.201.16:33:13.51#ibcon#read 6, iclass 31, count 0 2006.201.16:33:13.51#ibcon#end of sib2, iclass 31, count 0 2006.201.16:33:13.51#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:33:13.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:33:13.51#ibcon#[25=USB\r\n] 2006.201.16:33:13.51#ibcon#*before write, iclass 31, count 0 2006.201.16:33:13.51#ibcon#enter sib2, iclass 31, count 0 2006.201.16:33:13.51#ibcon#flushed, iclass 31, count 0 2006.201.16:33:13.51#ibcon#about to write, iclass 31, count 0 2006.201.16:33:13.51#ibcon#wrote, iclass 31, count 0 2006.201.16:33:13.51#ibcon#about to read 3, iclass 31, count 0 2006.201.16:33:13.54#ibcon#read 3, iclass 31, count 0 2006.201.16:33:13.54#ibcon#about to read 4, iclass 31, count 0 2006.201.16:33:13.54#ibcon#read 4, iclass 31, count 0 2006.201.16:33:13.54#ibcon#about to read 5, iclass 31, count 0 2006.201.16:33:13.54#ibcon#read 5, iclass 31, count 0 2006.201.16:33:13.54#ibcon#about to read 6, iclass 31, count 0 2006.201.16:33:13.54#ibcon#read 6, iclass 31, count 0 2006.201.16:33:13.54#ibcon#end of sib2, iclass 31, count 0 2006.201.16:33:13.54#ibcon#*after write, iclass 31, count 0 2006.201.16:33:13.54#ibcon#*before return 0, iclass 31, count 0 2006.201.16:33:13.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:33:13.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:33:13.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:33:13.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:33:13.54$vck44/vblo=1,629.99 2006.201.16:33:13.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.16:33:13.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.16:33:13.54#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:13.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:13.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:13.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:13.54#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:33:13.54#ibcon#first serial, iclass 33, count 0 2006.201.16:33:13.54#ibcon#enter sib2, iclass 33, count 0 2006.201.16:33:13.54#ibcon#flushed, iclass 33, count 0 2006.201.16:33:13.54#ibcon#about to write, iclass 33, count 0 2006.201.16:33:13.54#ibcon#wrote, iclass 33, count 0 2006.201.16:33:13.54#ibcon#about to read 3, iclass 33, count 0 2006.201.16:33:13.56#ibcon#read 3, iclass 33, count 0 2006.201.16:33:13.56#ibcon#about to read 4, iclass 33, count 0 2006.201.16:33:13.56#ibcon#read 4, iclass 33, count 0 2006.201.16:33:13.56#ibcon#about to read 5, iclass 33, count 0 2006.201.16:33:13.56#ibcon#read 5, iclass 33, count 0 2006.201.16:33:13.56#ibcon#about to read 6, iclass 33, count 0 2006.201.16:33:13.56#ibcon#read 6, iclass 33, count 0 2006.201.16:33:13.56#ibcon#end of sib2, iclass 33, count 0 2006.201.16:33:13.56#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:33:13.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:33:13.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:33:13.56#ibcon#*before write, iclass 33, count 0 2006.201.16:33:13.56#ibcon#enter sib2, iclass 33, count 0 2006.201.16:33:13.56#ibcon#flushed, iclass 33, count 0 2006.201.16:33:13.56#ibcon#about to write, iclass 33, count 0 2006.201.16:33:13.56#ibcon#wrote, iclass 33, count 0 2006.201.16:33:13.56#ibcon#about to read 3, iclass 33, count 0 2006.201.16:33:13.61#ibcon#read 3, iclass 33, count 0 2006.201.16:33:13.61#ibcon#about to read 4, iclass 33, count 0 2006.201.16:33:13.61#ibcon#read 4, iclass 33, count 0 2006.201.16:33:13.61#ibcon#about to read 5, iclass 33, count 0 2006.201.16:33:13.61#ibcon#read 5, iclass 33, count 0 2006.201.16:33:13.61#ibcon#about to read 6, iclass 33, count 0 2006.201.16:33:13.61#ibcon#read 6, iclass 33, count 0 2006.201.16:33:13.61#ibcon#end of sib2, iclass 33, count 0 2006.201.16:33:13.61#ibcon#*after write, iclass 33, count 0 2006.201.16:33:13.61#ibcon#*before return 0, iclass 33, count 0 2006.201.16:33:13.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:13.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:13.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:33:13.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:33:13.61$vck44/vb=1,4 2006.201.16:33:13.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.16:33:13.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.16:33:13.61#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:13.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:33:13.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:33:13.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:33:13.61#ibcon#enter wrdev, iclass 35, count 2 2006.201.16:33:13.61#ibcon#first serial, iclass 35, count 2 2006.201.16:33:13.61#ibcon#enter sib2, iclass 35, count 2 2006.201.16:33:13.61#ibcon#flushed, iclass 35, count 2 2006.201.16:33:13.61#ibcon#about to write, iclass 35, count 2 2006.201.16:33:13.61#ibcon#wrote, iclass 35, count 2 2006.201.16:33:13.61#ibcon#about to read 3, iclass 35, count 2 2006.201.16:33:13.63#ibcon#read 3, iclass 35, count 2 2006.201.16:33:13.63#ibcon#about to read 4, iclass 35, count 2 2006.201.16:33:13.63#ibcon#read 4, iclass 35, count 2 2006.201.16:33:13.63#ibcon#about to read 5, iclass 35, count 2 2006.201.16:33:13.63#ibcon#read 5, iclass 35, count 2 2006.201.16:33:13.63#ibcon#about to read 6, iclass 35, count 2 2006.201.16:33:13.63#ibcon#read 6, iclass 35, count 2 2006.201.16:33:13.63#ibcon#end of sib2, iclass 35, count 2 2006.201.16:33:13.63#ibcon#*mode == 0, iclass 35, count 2 2006.201.16:33:13.63#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.16:33:13.63#ibcon#[27=AT01-04\r\n] 2006.201.16:33:13.63#ibcon#*before write, iclass 35, count 2 2006.201.16:33:13.63#ibcon#enter sib2, iclass 35, count 2 2006.201.16:33:13.63#ibcon#flushed, iclass 35, count 2 2006.201.16:33:13.63#ibcon#about to write, iclass 35, count 2 2006.201.16:33:13.63#ibcon#wrote, iclass 35, count 2 2006.201.16:33:13.63#ibcon#about to read 3, iclass 35, count 2 2006.201.16:33:13.66#ibcon#read 3, iclass 35, count 2 2006.201.16:33:13.66#ibcon#about to read 4, iclass 35, count 2 2006.201.16:33:13.66#ibcon#read 4, iclass 35, count 2 2006.201.16:33:13.66#ibcon#about to read 5, iclass 35, count 2 2006.201.16:33:13.66#ibcon#read 5, iclass 35, count 2 2006.201.16:33:13.66#ibcon#about to read 6, iclass 35, count 2 2006.201.16:33:13.66#ibcon#read 6, iclass 35, count 2 2006.201.16:33:13.66#ibcon#end of sib2, iclass 35, count 2 2006.201.16:33:13.66#ibcon#*after write, iclass 35, count 2 2006.201.16:33:13.66#ibcon#*before return 0, iclass 35, count 2 2006.201.16:33:13.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:33:13.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:33:13.66#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.16:33:13.66#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:13.66#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:33:13.78#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:33:13.78#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:33:13.78#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:33:13.78#ibcon#first serial, iclass 35, count 0 2006.201.16:33:13.78#ibcon#enter sib2, iclass 35, count 0 2006.201.16:33:13.78#ibcon#flushed, iclass 35, count 0 2006.201.16:33:13.78#ibcon#about to write, iclass 35, count 0 2006.201.16:33:13.78#ibcon#wrote, iclass 35, count 0 2006.201.16:33:13.78#ibcon#about to read 3, iclass 35, count 0 2006.201.16:33:13.80#ibcon#read 3, iclass 35, count 0 2006.201.16:33:13.80#ibcon#about to read 4, iclass 35, count 0 2006.201.16:33:13.80#ibcon#read 4, iclass 35, count 0 2006.201.16:33:13.80#ibcon#about to read 5, iclass 35, count 0 2006.201.16:33:13.80#ibcon#read 5, iclass 35, count 0 2006.201.16:33:13.80#ibcon#about to read 6, iclass 35, count 0 2006.201.16:33:13.80#ibcon#read 6, iclass 35, count 0 2006.201.16:33:13.80#ibcon#end of sib2, iclass 35, count 0 2006.201.16:33:13.80#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:33:13.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:33:13.80#ibcon#[27=USB\r\n] 2006.201.16:33:13.80#ibcon#*before write, iclass 35, count 0 2006.201.16:33:13.80#ibcon#enter sib2, iclass 35, count 0 2006.201.16:33:13.80#ibcon#flushed, iclass 35, count 0 2006.201.16:33:13.80#ibcon#about to write, iclass 35, count 0 2006.201.16:33:13.80#ibcon#wrote, iclass 35, count 0 2006.201.16:33:13.80#ibcon#about to read 3, iclass 35, count 0 2006.201.16:33:13.83#ibcon#read 3, iclass 35, count 0 2006.201.16:33:13.83#ibcon#about to read 4, iclass 35, count 0 2006.201.16:33:13.83#ibcon#read 4, iclass 35, count 0 2006.201.16:33:13.83#ibcon#about to read 5, iclass 35, count 0 2006.201.16:33:13.83#ibcon#read 5, iclass 35, count 0 2006.201.16:33:13.83#ibcon#about to read 6, iclass 35, count 0 2006.201.16:33:13.83#ibcon#read 6, iclass 35, count 0 2006.201.16:33:13.83#ibcon#end of sib2, iclass 35, count 0 2006.201.16:33:13.83#ibcon#*after write, iclass 35, count 0 2006.201.16:33:13.83#ibcon#*before return 0, iclass 35, count 0 2006.201.16:33:13.83#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:33:13.83#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:33:13.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:33:13.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:33:13.83$vck44/vblo=2,634.99 2006.201.16:33:13.83#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.16:33:13.83#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.16:33:13.83#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:13.83#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:13.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:13.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:13.83#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:33:13.83#ibcon#first serial, iclass 37, count 0 2006.201.16:33:13.83#ibcon#enter sib2, iclass 37, count 0 2006.201.16:33:13.83#ibcon#flushed, iclass 37, count 0 2006.201.16:33:13.83#ibcon#about to write, iclass 37, count 0 2006.201.16:33:13.83#ibcon#wrote, iclass 37, count 0 2006.201.16:33:13.83#ibcon#about to read 3, iclass 37, count 0 2006.201.16:33:13.85#ibcon#read 3, iclass 37, count 0 2006.201.16:33:13.85#ibcon#about to read 4, iclass 37, count 0 2006.201.16:33:13.85#ibcon#read 4, iclass 37, count 0 2006.201.16:33:13.85#ibcon#about to read 5, iclass 37, count 0 2006.201.16:33:13.85#ibcon#read 5, iclass 37, count 0 2006.201.16:33:13.85#ibcon#about to read 6, iclass 37, count 0 2006.201.16:33:13.85#ibcon#read 6, iclass 37, count 0 2006.201.16:33:13.85#ibcon#end of sib2, iclass 37, count 0 2006.201.16:33:13.85#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:33:13.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:33:13.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:33:13.85#ibcon#*before write, iclass 37, count 0 2006.201.16:33:13.85#ibcon#enter sib2, iclass 37, count 0 2006.201.16:33:13.85#ibcon#flushed, iclass 37, count 0 2006.201.16:33:13.85#ibcon#about to write, iclass 37, count 0 2006.201.16:33:13.85#ibcon#wrote, iclass 37, count 0 2006.201.16:33:13.85#ibcon#about to read 3, iclass 37, count 0 2006.201.16:33:13.89#ibcon#read 3, iclass 37, count 0 2006.201.16:33:13.89#ibcon#about to read 4, iclass 37, count 0 2006.201.16:33:13.89#ibcon#read 4, iclass 37, count 0 2006.201.16:33:13.89#ibcon#about to read 5, iclass 37, count 0 2006.201.16:33:13.89#ibcon#read 5, iclass 37, count 0 2006.201.16:33:13.89#ibcon#about to read 6, iclass 37, count 0 2006.201.16:33:13.89#ibcon#read 6, iclass 37, count 0 2006.201.16:33:13.89#ibcon#end of sib2, iclass 37, count 0 2006.201.16:33:13.89#ibcon#*after write, iclass 37, count 0 2006.201.16:33:13.89#ibcon#*before return 0, iclass 37, count 0 2006.201.16:33:13.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:13.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:33:13.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:33:13.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:33:13.89$vck44/vb=2,5 2006.201.16:33:13.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.16:33:13.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.16:33:13.89#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:13.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:13.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:13.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:13.95#ibcon#enter wrdev, iclass 39, count 2 2006.201.16:33:13.95#ibcon#first serial, iclass 39, count 2 2006.201.16:33:13.95#ibcon#enter sib2, iclass 39, count 2 2006.201.16:33:13.95#ibcon#flushed, iclass 39, count 2 2006.201.16:33:13.95#ibcon#about to write, iclass 39, count 2 2006.201.16:33:13.95#ibcon#wrote, iclass 39, count 2 2006.201.16:33:13.95#ibcon#about to read 3, iclass 39, count 2 2006.201.16:33:13.97#ibcon#read 3, iclass 39, count 2 2006.201.16:33:13.97#ibcon#about to read 4, iclass 39, count 2 2006.201.16:33:13.97#ibcon#read 4, iclass 39, count 2 2006.201.16:33:13.97#ibcon#about to read 5, iclass 39, count 2 2006.201.16:33:13.97#ibcon#read 5, iclass 39, count 2 2006.201.16:33:13.97#ibcon#about to read 6, iclass 39, count 2 2006.201.16:33:13.97#ibcon#read 6, iclass 39, count 2 2006.201.16:33:13.97#ibcon#end of sib2, iclass 39, count 2 2006.201.16:33:13.97#ibcon#*mode == 0, iclass 39, count 2 2006.201.16:33:13.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.16:33:13.97#ibcon#[27=AT02-05\r\n] 2006.201.16:33:13.97#ibcon#*before write, iclass 39, count 2 2006.201.16:33:13.97#ibcon#enter sib2, iclass 39, count 2 2006.201.16:33:13.97#ibcon#flushed, iclass 39, count 2 2006.201.16:33:13.97#ibcon#about to write, iclass 39, count 2 2006.201.16:33:13.97#ibcon#wrote, iclass 39, count 2 2006.201.16:33:13.97#ibcon#about to read 3, iclass 39, count 2 2006.201.16:33:14.00#ibcon#read 3, iclass 39, count 2 2006.201.16:33:14.00#ibcon#about to read 4, iclass 39, count 2 2006.201.16:33:14.00#ibcon#read 4, iclass 39, count 2 2006.201.16:33:14.00#ibcon#about to read 5, iclass 39, count 2 2006.201.16:33:14.00#ibcon#read 5, iclass 39, count 2 2006.201.16:33:14.00#ibcon#about to read 6, iclass 39, count 2 2006.201.16:33:14.00#ibcon#read 6, iclass 39, count 2 2006.201.16:33:14.00#ibcon#end of sib2, iclass 39, count 2 2006.201.16:33:14.00#ibcon#*after write, iclass 39, count 2 2006.201.16:33:14.00#ibcon#*before return 0, iclass 39, count 2 2006.201.16:33:14.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:14.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:33:14.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.16:33:14.00#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:14.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:14.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:14.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:14.12#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:33:14.12#ibcon#first serial, iclass 39, count 0 2006.201.16:33:14.12#ibcon#enter sib2, iclass 39, count 0 2006.201.16:33:14.12#ibcon#flushed, iclass 39, count 0 2006.201.16:33:14.12#ibcon#about to write, iclass 39, count 0 2006.201.16:33:14.12#ibcon#wrote, iclass 39, count 0 2006.201.16:33:14.12#ibcon#about to read 3, iclass 39, count 0 2006.201.16:33:14.14#ibcon#read 3, iclass 39, count 0 2006.201.16:33:14.14#ibcon#about to read 4, iclass 39, count 0 2006.201.16:33:14.14#ibcon#read 4, iclass 39, count 0 2006.201.16:33:14.14#ibcon#about to read 5, iclass 39, count 0 2006.201.16:33:14.14#ibcon#read 5, iclass 39, count 0 2006.201.16:33:14.14#ibcon#about to read 6, iclass 39, count 0 2006.201.16:33:14.14#ibcon#read 6, iclass 39, count 0 2006.201.16:33:14.14#ibcon#end of sib2, iclass 39, count 0 2006.201.16:33:14.14#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:33:14.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:33:14.14#ibcon#[27=USB\r\n] 2006.201.16:33:14.14#ibcon#*before write, iclass 39, count 0 2006.201.16:33:14.14#ibcon#enter sib2, iclass 39, count 0 2006.201.16:33:14.14#ibcon#flushed, iclass 39, count 0 2006.201.16:33:14.14#ibcon#about to write, iclass 39, count 0 2006.201.16:33:14.14#ibcon#wrote, iclass 39, count 0 2006.201.16:33:14.14#ibcon#about to read 3, iclass 39, count 0 2006.201.16:33:14.17#ibcon#read 3, iclass 39, count 0 2006.201.16:33:14.17#ibcon#about to read 4, iclass 39, count 0 2006.201.16:33:14.17#ibcon#read 4, iclass 39, count 0 2006.201.16:33:14.17#ibcon#about to read 5, iclass 39, count 0 2006.201.16:33:14.17#ibcon#read 5, iclass 39, count 0 2006.201.16:33:14.17#ibcon#about to read 6, iclass 39, count 0 2006.201.16:33:14.17#ibcon#read 6, iclass 39, count 0 2006.201.16:33:14.17#ibcon#end of sib2, iclass 39, count 0 2006.201.16:33:14.17#ibcon#*after write, iclass 39, count 0 2006.201.16:33:14.17#ibcon#*before return 0, iclass 39, count 0 2006.201.16:33:14.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:14.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:33:14.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:33:14.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:33:14.17$vck44/vblo=3,649.99 2006.201.16:33:14.17#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.16:33:14.17#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.16:33:14.17#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:14.17#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:14.17#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:14.17#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:14.17#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:33:14.17#ibcon#first serial, iclass 2, count 0 2006.201.16:33:14.17#ibcon#enter sib2, iclass 2, count 0 2006.201.16:33:14.17#ibcon#flushed, iclass 2, count 0 2006.201.16:33:14.17#ibcon#about to write, iclass 2, count 0 2006.201.16:33:14.17#ibcon#wrote, iclass 2, count 0 2006.201.16:33:14.17#ibcon#about to read 3, iclass 2, count 0 2006.201.16:33:14.19#ibcon#read 3, iclass 2, count 0 2006.201.16:33:14.19#ibcon#about to read 4, iclass 2, count 0 2006.201.16:33:14.19#ibcon#read 4, iclass 2, count 0 2006.201.16:33:14.19#ibcon#about to read 5, iclass 2, count 0 2006.201.16:33:14.19#ibcon#read 5, iclass 2, count 0 2006.201.16:33:14.19#ibcon#about to read 6, iclass 2, count 0 2006.201.16:33:14.19#ibcon#read 6, iclass 2, count 0 2006.201.16:33:14.19#ibcon#end of sib2, iclass 2, count 0 2006.201.16:33:14.19#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:33:14.19#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:33:14.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:33:14.19#ibcon#*before write, iclass 2, count 0 2006.201.16:33:14.19#ibcon#enter sib2, iclass 2, count 0 2006.201.16:33:14.19#ibcon#flushed, iclass 2, count 0 2006.201.16:33:14.19#ibcon#about to write, iclass 2, count 0 2006.201.16:33:14.19#ibcon#wrote, iclass 2, count 0 2006.201.16:33:14.19#ibcon#about to read 3, iclass 2, count 0 2006.201.16:33:14.23#ibcon#read 3, iclass 2, count 0 2006.201.16:33:14.23#ibcon#about to read 4, iclass 2, count 0 2006.201.16:33:14.23#ibcon#read 4, iclass 2, count 0 2006.201.16:33:14.23#ibcon#about to read 5, iclass 2, count 0 2006.201.16:33:14.23#ibcon#read 5, iclass 2, count 0 2006.201.16:33:14.23#ibcon#about to read 6, iclass 2, count 0 2006.201.16:33:14.23#ibcon#read 6, iclass 2, count 0 2006.201.16:33:14.23#ibcon#end of sib2, iclass 2, count 0 2006.201.16:33:14.23#ibcon#*after write, iclass 2, count 0 2006.201.16:33:14.23#ibcon#*before return 0, iclass 2, count 0 2006.201.16:33:14.23#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:14.23#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:33:14.23#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:33:14.23#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:33:14.23$vck44/vb=3,4 2006.201.16:33:14.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.16:33:14.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.16:33:14.23#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:14.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:14.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:14.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:14.29#ibcon#enter wrdev, iclass 5, count 2 2006.201.16:33:14.29#ibcon#first serial, iclass 5, count 2 2006.201.16:33:14.29#ibcon#enter sib2, iclass 5, count 2 2006.201.16:33:14.29#ibcon#flushed, iclass 5, count 2 2006.201.16:33:14.29#ibcon#about to write, iclass 5, count 2 2006.201.16:33:14.29#ibcon#wrote, iclass 5, count 2 2006.201.16:33:14.29#ibcon#about to read 3, iclass 5, count 2 2006.201.16:33:14.31#ibcon#read 3, iclass 5, count 2 2006.201.16:33:14.31#ibcon#about to read 4, iclass 5, count 2 2006.201.16:33:14.31#ibcon#read 4, iclass 5, count 2 2006.201.16:33:14.31#ibcon#about to read 5, iclass 5, count 2 2006.201.16:33:14.31#ibcon#read 5, iclass 5, count 2 2006.201.16:33:14.31#ibcon#about to read 6, iclass 5, count 2 2006.201.16:33:14.31#ibcon#read 6, iclass 5, count 2 2006.201.16:33:14.31#ibcon#end of sib2, iclass 5, count 2 2006.201.16:33:14.31#ibcon#*mode == 0, iclass 5, count 2 2006.201.16:33:14.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.16:33:14.31#ibcon#[27=AT03-04\r\n] 2006.201.16:33:14.31#ibcon#*before write, iclass 5, count 2 2006.201.16:33:14.31#ibcon#enter sib2, iclass 5, count 2 2006.201.16:33:14.31#ibcon#flushed, iclass 5, count 2 2006.201.16:33:14.31#ibcon#about to write, iclass 5, count 2 2006.201.16:33:14.31#ibcon#wrote, iclass 5, count 2 2006.201.16:33:14.31#ibcon#about to read 3, iclass 5, count 2 2006.201.16:33:14.34#ibcon#read 3, iclass 5, count 2 2006.201.16:33:14.34#ibcon#about to read 4, iclass 5, count 2 2006.201.16:33:14.34#ibcon#read 4, iclass 5, count 2 2006.201.16:33:14.34#ibcon#about to read 5, iclass 5, count 2 2006.201.16:33:14.34#ibcon#read 5, iclass 5, count 2 2006.201.16:33:14.34#ibcon#about to read 6, iclass 5, count 2 2006.201.16:33:14.34#ibcon#read 6, iclass 5, count 2 2006.201.16:33:14.34#ibcon#end of sib2, iclass 5, count 2 2006.201.16:33:14.34#ibcon#*after write, iclass 5, count 2 2006.201.16:33:14.34#ibcon#*before return 0, iclass 5, count 2 2006.201.16:33:14.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:14.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:33:14.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.16:33:14.34#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:14.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:14.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:14.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:14.46#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:33:14.46#ibcon#first serial, iclass 5, count 0 2006.201.16:33:14.46#ibcon#enter sib2, iclass 5, count 0 2006.201.16:33:14.46#ibcon#flushed, iclass 5, count 0 2006.201.16:33:14.46#ibcon#about to write, iclass 5, count 0 2006.201.16:33:14.46#ibcon#wrote, iclass 5, count 0 2006.201.16:33:14.46#ibcon#about to read 3, iclass 5, count 0 2006.201.16:33:14.48#ibcon#read 3, iclass 5, count 0 2006.201.16:33:14.48#ibcon#about to read 4, iclass 5, count 0 2006.201.16:33:14.48#ibcon#read 4, iclass 5, count 0 2006.201.16:33:14.48#ibcon#about to read 5, iclass 5, count 0 2006.201.16:33:14.48#ibcon#read 5, iclass 5, count 0 2006.201.16:33:14.48#ibcon#about to read 6, iclass 5, count 0 2006.201.16:33:14.48#ibcon#read 6, iclass 5, count 0 2006.201.16:33:14.48#ibcon#end of sib2, iclass 5, count 0 2006.201.16:33:14.48#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:33:14.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:33:14.48#ibcon#[27=USB\r\n] 2006.201.16:33:14.48#ibcon#*before write, iclass 5, count 0 2006.201.16:33:14.48#ibcon#enter sib2, iclass 5, count 0 2006.201.16:33:14.48#ibcon#flushed, iclass 5, count 0 2006.201.16:33:14.48#ibcon#about to write, iclass 5, count 0 2006.201.16:33:14.48#ibcon#wrote, iclass 5, count 0 2006.201.16:33:14.48#ibcon#about to read 3, iclass 5, count 0 2006.201.16:33:14.51#ibcon#read 3, iclass 5, count 0 2006.201.16:33:14.51#ibcon#about to read 4, iclass 5, count 0 2006.201.16:33:14.51#ibcon#read 4, iclass 5, count 0 2006.201.16:33:14.51#ibcon#about to read 5, iclass 5, count 0 2006.201.16:33:14.51#ibcon#read 5, iclass 5, count 0 2006.201.16:33:14.51#ibcon#about to read 6, iclass 5, count 0 2006.201.16:33:14.51#ibcon#read 6, iclass 5, count 0 2006.201.16:33:14.51#ibcon#end of sib2, iclass 5, count 0 2006.201.16:33:14.51#ibcon#*after write, iclass 5, count 0 2006.201.16:33:14.51#ibcon#*before return 0, iclass 5, count 0 2006.201.16:33:14.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:14.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:33:14.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:33:14.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:33:14.51$vck44/vblo=4,679.99 2006.201.16:33:14.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.16:33:14.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.16:33:14.51#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:14.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:14.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:14.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:14.51#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:33:14.51#ibcon#first serial, iclass 7, count 0 2006.201.16:33:14.51#ibcon#enter sib2, iclass 7, count 0 2006.201.16:33:14.51#ibcon#flushed, iclass 7, count 0 2006.201.16:33:14.51#ibcon#about to write, iclass 7, count 0 2006.201.16:33:14.51#ibcon#wrote, iclass 7, count 0 2006.201.16:33:14.51#ibcon#about to read 3, iclass 7, count 0 2006.201.16:33:14.53#ibcon#read 3, iclass 7, count 0 2006.201.16:33:14.53#ibcon#about to read 4, iclass 7, count 0 2006.201.16:33:14.53#ibcon#read 4, iclass 7, count 0 2006.201.16:33:14.53#ibcon#about to read 5, iclass 7, count 0 2006.201.16:33:14.53#ibcon#read 5, iclass 7, count 0 2006.201.16:33:14.53#ibcon#about to read 6, iclass 7, count 0 2006.201.16:33:14.53#ibcon#read 6, iclass 7, count 0 2006.201.16:33:14.53#ibcon#end of sib2, iclass 7, count 0 2006.201.16:33:14.53#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:33:14.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:33:14.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:33:14.53#ibcon#*before write, iclass 7, count 0 2006.201.16:33:14.53#ibcon#enter sib2, iclass 7, count 0 2006.201.16:33:14.53#ibcon#flushed, iclass 7, count 0 2006.201.16:33:14.53#ibcon#about to write, iclass 7, count 0 2006.201.16:33:14.53#ibcon#wrote, iclass 7, count 0 2006.201.16:33:14.53#ibcon#about to read 3, iclass 7, count 0 2006.201.16:33:14.57#ibcon#read 3, iclass 7, count 0 2006.201.16:33:14.57#ibcon#about to read 4, iclass 7, count 0 2006.201.16:33:14.57#ibcon#read 4, iclass 7, count 0 2006.201.16:33:14.57#ibcon#about to read 5, iclass 7, count 0 2006.201.16:33:14.57#ibcon#read 5, iclass 7, count 0 2006.201.16:33:14.57#ibcon#about to read 6, iclass 7, count 0 2006.201.16:33:14.57#ibcon#read 6, iclass 7, count 0 2006.201.16:33:14.57#ibcon#end of sib2, iclass 7, count 0 2006.201.16:33:14.57#ibcon#*after write, iclass 7, count 0 2006.201.16:33:14.57#ibcon#*before return 0, iclass 7, count 0 2006.201.16:33:14.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:14.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:33:14.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:33:14.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:33:14.57$vck44/vb=4,5 2006.201.16:33:14.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.16:33:14.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.16:33:14.57#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:14.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:14.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:14.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:14.63#ibcon#enter wrdev, iclass 11, count 2 2006.201.16:33:14.63#ibcon#first serial, iclass 11, count 2 2006.201.16:33:14.63#ibcon#enter sib2, iclass 11, count 2 2006.201.16:33:14.63#ibcon#flushed, iclass 11, count 2 2006.201.16:33:14.63#ibcon#about to write, iclass 11, count 2 2006.201.16:33:14.63#ibcon#wrote, iclass 11, count 2 2006.201.16:33:14.63#ibcon#about to read 3, iclass 11, count 2 2006.201.16:33:14.65#ibcon#read 3, iclass 11, count 2 2006.201.16:33:14.65#ibcon#about to read 4, iclass 11, count 2 2006.201.16:33:14.65#ibcon#read 4, iclass 11, count 2 2006.201.16:33:14.65#ibcon#about to read 5, iclass 11, count 2 2006.201.16:33:14.65#ibcon#read 5, iclass 11, count 2 2006.201.16:33:14.65#ibcon#about to read 6, iclass 11, count 2 2006.201.16:33:14.65#ibcon#read 6, iclass 11, count 2 2006.201.16:33:14.65#ibcon#end of sib2, iclass 11, count 2 2006.201.16:33:14.65#ibcon#*mode == 0, iclass 11, count 2 2006.201.16:33:14.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.16:33:14.65#ibcon#[27=AT04-05\r\n] 2006.201.16:33:14.65#ibcon#*before write, iclass 11, count 2 2006.201.16:33:14.65#ibcon#enter sib2, iclass 11, count 2 2006.201.16:33:14.65#ibcon#flushed, iclass 11, count 2 2006.201.16:33:14.65#ibcon#about to write, iclass 11, count 2 2006.201.16:33:14.65#ibcon#wrote, iclass 11, count 2 2006.201.16:33:14.65#ibcon#about to read 3, iclass 11, count 2 2006.201.16:33:14.68#ibcon#read 3, iclass 11, count 2 2006.201.16:33:14.68#ibcon#about to read 4, iclass 11, count 2 2006.201.16:33:14.68#ibcon#read 4, iclass 11, count 2 2006.201.16:33:14.68#ibcon#about to read 5, iclass 11, count 2 2006.201.16:33:14.68#ibcon#read 5, iclass 11, count 2 2006.201.16:33:14.68#ibcon#about to read 6, iclass 11, count 2 2006.201.16:33:14.68#ibcon#read 6, iclass 11, count 2 2006.201.16:33:14.68#ibcon#end of sib2, iclass 11, count 2 2006.201.16:33:14.68#ibcon#*after write, iclass 11, count 2 2006.201.16:33:14.68#ibcon#*before return 0, iclass 11, count 2 2006.201.16:33:14.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:14.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:33:14.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.16:33:14.68#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:14.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:14.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:14.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:14.80#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:33:14.80#ibcon#first serial, iclass 11, count 0 2006.201.16:33:14.80#ibcon#enter sib2, iclass 11, count 0 2006.201.16:33:14.80#ibcon#flushed, iclass 11, count 0 2006.201.16:33:14.80#ibcon#about to write, iclass 11, count 0 2006.201.16:33:14.80#ibcon#wrote, iclass 11, count 0 2006.201.16:33:14.80#ibcon#about to read 3, iclass 11, count 0 2006.201.16:33:14.82#ibcon#read 3, iclass 11, count 0 2006.201.16:33:14.82#ibcon#about to read 4, iclass 11, count 0 2006.201.16:33:14.82#ibcon#read 4, iclass 11, count 0 2006.201.16:33:14.82#ibcon#about to read 5, iclass 11, count 0 2006.201.16:33:14.82#ibcon#read 5, iclass 11, count 0 2006.201.16:33:14.82#ibcon#about to read 6, iclass 11, count 0 2006.201.16:33:14.82#ibcon#read 6, iclass 11, count 0 2006.201.16:33:14.82#ibcon#end of sib2, iclass 11, count 0 2006.201.16:33:14.82#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:33:14.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:33:14.82#ibcon#[27=USB\r\n] 2006.201.16:33:14.82#ibcon#*before write, iclass 11, count 0 2006.201.16:33:14.82#ibcon#enter sib2, iclass 11, count 0 2006.201.16:33:14.82#ibcon#flushed, iclass 11, count 0 2006.201.16:33:14.82#ibcon#about to write, iclass 11, count 0 2006.201.16:33:14.82#ibcon#wrote, iclass 11, count 0 2006.201.16:33:14.82#ibcon#about to read 3, iclass 11, count 0 2006.201.16:33:14.85#ibcon#read 3, iclass 11, count 0 2006.201.16:33:14.85#ibcon#about to read 4, iclass 11, count 0 2006.201.16:33:14.85#ibcon#read 4, iclass 11, count 0 2006.201.16:33:14.85#ibcon#about to read 5, iclass 11, count 0 2006.201.16:33:14.85#ibcon#read 5, iclass 11, count 0 2006.201.16:33:14.85#ibcon#about to read 6, iclass 11, count 0 2006.201.16:33:14.85#ibcon#read 6, iclass 11, count 0 2006.201.16:33:14.85#ibcon#end of sib2, iclass 11, count 0 2006.201.16:33:14.85#ibcon#*after write, iclass 11, count 0 2006.201.16:33:14.85#ibcon#*before return 0, iclass 11, count 0 2006.201.16:33:14.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:14.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:33:14.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:33:14.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:33:14.85$vck44/vblo=5,709.99 2006.201.16:33:14.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.16:33:14.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.16:33:14.85#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:14.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:14.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:14.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:14.85#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:33:14.85#ibcon#first serial, iclass 13, count 0 2006.201.16:33:14.85#ibcon#enter sib2, iclass 13, count 0 2006.201.16:33:14.85#ibcon#flushed, iclass 13, count 0 2006.201.16:33:14.85#ibcon#about to write, iclass 13, count 0 2006.201.16:33:14.85#ibcon#wrote, iclass 13, count 0 2006.201.16:33:14.85#ibcon#about to read 3, iclass 13, count 0 2006.201.16:33:14.87#ibcon#read 3, iclass 13, count 0 2006.201.16:33:14.87#ibcon#about to read 4, iclass 13, count 0 2006.201.16:33:14.87#ibcon#read 4, iclass 13, count 0 2006.201.16:33:14.87#ibcon#about to read 5, iclass 13, count 0 2006.201.16:33:14.87#ibcon#read 5, iclass 13, count 0 2006.201.16:33:14.87#ibcon#about to read 6, iclass 13, count 0 2006.201.16:33:14.87#ibcon#read 6, iclass 13, count 0 2006.201.16:33:14.87#ibcon#end of sib2, iclass 13, count 0 2006.201.16:33:14.87#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:33:14.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:33:14.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:33:14.87#ibcon#*before write, iclass 13, count 0 2006.201.16:33:14.87#ibcon#enter sib2, iclass 13, count 0 2006.201.16:33:14.87#ibcon#flushed, iclass 13, count 0 2006.201.16:33:14.87#ibcon#about to write, iclass 13, count 0 2006.201.16:33:14.87#ibcon#wrote, iclass 13, count 0 2006.201.16:33:14.87#ibcon#about to read 3, iclass 13, count 0 2006.201.16:33:14.92#ibcon#read 3, iclass 13, count 0 2006.201.16:33:14.92#ibcon#about to read 4, iclass 13, count 0 2006.201.16:33:14.92#ibcon#read 4, iclass 13, count 0 2006.201.16:33:14.92#ibcon#about to read 5, iclass 13, count 0 2006.201.16:33:14.92#ibcon#read 5, iclass 13, count 0 2006.201.16:33:14.92#ibcon#about to read 6, iclass 13, count 0 2006.201.16:33:14.92#ibcon#read 6, iclass 13, count 0 2006.201.16:33:14.92#ibcon#end of sib2, iclass 13, count 0 2006.201.16:33:14.92#ibcon#*after write, iclass 13, count 0 2006.201.16:33:14.92#ibcon#*before return 0, iclass 13, count 0 2006.201.16:33:14.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:14.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:33:14.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:33:14.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:33:14.92$vck44/vb=5,4 2006.201.16:33:14.92#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.16:33:14.92#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.16:33:14.92#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:14.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:14.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:14.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:14.97#ibcon#enter wrdev, iclass 15, count 2 2006.201.16:33:14.97#ibcon#first serial, iclass 15, count 2 2006.201.16:33:14.97#ibcon#enter sib2, iclass 15, count 2 2006.201.16:33:14.97#ibcon#flushed, iclass 15, count 2 2006.201.16:33:14.97#ibcon#about to write, iclass 15, count 2 2006.201.16:33:14.97#ibcon#wrote, iclass 15, count 2 2006.201.16:33:14.97#ibcon#about to read 3, iclass 15, count 2 2006.201.16:33:14.99#ibcon#read 3, iclass 15, count 2 2006.201.16:33:14.99#ibcon#about to read 4, iclass 15, count 2 2006.201.16:33:14.99#ibcon#read 4, iclass 15, count 2 2006.201.16:33:14.99#ibcon#about to read 5, iclass 15, count 2 2006.201.16:33:14.99#ibcon#read 5, iclass 15, count 2 2006.201.16:33:14.99#ibcon#about to read 6, iclass 15, count 2 2006.201.16:33:14.99#ibcon#read 6, iclass 15, count 2 2006.201.16:33:14.99#ibcon#end of sib2, iclass 15, count 2 2006.201.16:33:14.99#ibcon#*mode == 0, iclass 15, count 2 2006.201.16:33:14.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.16:33:14.99#ibcon#[27=AT05-04\r\n] 2006.201.16:33:14.99#ibcon#*before write, iclass 15, count 2 2006.201.16:33:14.99#ibcon#enter sib2, iclass 15, count 2 2006.201.16:33:14.99#ibcon#flushed, iclass 15, count 2 2006.201.16:33:14.99#ibcon#about to write, iclass 15, count 2 2006.201.16:33:14.99#ibcon#wrote, iclass 15, count 2 2006.201.16:33:14.99#ibcon#about to read 3, iclass 15, count 2 2006.201.16:33:15.02#ibcon#read 3, iclass 15, count 2 2006.201.16:33:15.02#ibcon#about to read 4, iclass 15, count 2 2006.201.16:33:15.02#ibcon#read 4, iclass 15, count 2 2006.201.16:33:15.02#ibcon#about to read 5, iclass 15, count 2 2006.201.16:33:15.02#ibcon#read 5, iclass 15, count 2 2006.201.16:33:15.02#ibcon#about to read 6, iclass 15, count 2 2006.201.16:33:15.02#ibcon#read 6, iclass 15, count 2 2006.201.16:33:15.02#ibcon#end of sib2, iclass 15, count 2 2006.201.16:33:15.02#ibcon#*after write, iclass 15, count 2 2006.201.16:33:15.02#ibcon#*before return 0, iclass 15, count 2 2006.201.16:33:15.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:15.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:33:15.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.16:33:15.02#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:15.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:15.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:15.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:15.14#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:33:15.14#ibcon#first serial, iclass 15, count 0 2006.201.16:33:15.14#ibcon#enter sib2, iclass 15, count 0 2006.201.16:33:15.14#ibcon#flushed, iclass 15, count 0 2006.201.16:33:15.14#ibcon#about to write, iclass 15, count 0 2006.201.16:33:15.14#ibcon#wrote, iclass 15, count 0 2006.201.16:33:15.14#ibcon#about to read 3, iclass 15, count 0 2006.201.16:33:15.16#ibcon#read 3, iclass 15, count 0 2006.201.16:33:15.16#ibcon#about to read 4, iclass 15, count 0 2006.201.16:33:15.16#ibcon#read 4, iclass 15, count 0 2006.201.16:33:15.16#ibcon#about to read 5, iclass 15, count 0 2006.201.16:33:15.16#ibcon#read 5, iclass 15, count 0 2006.201.16:33:15.16#ibcon#about to read 6, iclass 15, count 0 2006.201.16:33:15.16#ibcon#read 6, iclass 15, count 0 2006.201.16:33:15.16#ibcon#end of sib2, iclass 15, count 0 2006.201.16:33:15.16#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:33:15.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:33:15.16#ibcon#[27=USB\r\n] 2006.201.16:33:15.16#ibcon#*before write, iclass 15, count 0 2006.201.16:33:15.16#ibcon#enter sib2, iclass 15, count 0 2006.201.16:33:15.16#ibcon#flushed, iclass 15, count 0 2006.201.16:33:15.16#ibcon#about to write, iclass 15, count 0 2006.201.16:33:15.16#ibcon#wrote, iclass 15, count 0 2006.201.16:33:15.16#ibcon#about to read 3, iclass 15, count 0 2006.201.16:33:15.19#ibcon#read 3, iclass 15, count 0 2006.201.16:33:15.19#ibcon#about to read 4, iclass 15, count 0 2006.201.16:33:15.19#ibcon#read 4, iclass 15, count 0 2006.201.16:33:15.19#ibcon#about to read 5, iclass 15, count 0 2006.201.16:33:15.19#ibcon#read 5, iclass 15, count 0 2006.201.16:33:15.19#ibcon#about to read 6, iclass 15, count 0 2006.201.16:33:15.19#ibcon#read 6, iclass 15, count 0 2006.201.16:33:15.19#ibcon#end of sib2, iclass 15, count 0 2006.201.16:33:15.19#ibcon#*after write, iclass 15, count 0 2006.201.16:33:15.19#ibcon#*before return 0, iclass 15, count 0 2006.201.16:33:15.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:15.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:33:15.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:33:15.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:33:15.19$vck44/vblo=6,719.99 2006.201.16:33:15.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.16:33:15.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.16:33:15.19#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:15.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:15.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:15.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:15.19#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:33:15.19#ibcon#first serial, iclass 17, count 0 2006.201.16:33:15.19#ibcon#enter sib2, iclass 17, count 0 2006.201.16:33:15.19#ibcon#flushed, iclass 17, count 0 2006.201.16:33:15.19#ibcon#about to write, iclass 17, count 0 2006.201.16:33:15.19#ibcon#wrote, iclass 17, count 0 2006.201.16:33:15.19#ibcon#about to read 3, iclass 17, count 0 2006.201.16:33:15.21#ibcon#read 3, iclass 17, count 0 2006.201.16:33:15.21#ibcon#about to read 4, iclass 17, count 0 2006.201.16:33:15.21#ibcon#read 4, iclass 17, count 0 2006.201.16:33:15.21#ibcon#about to read 5, iclass 17, count 0 2006.201.16:33:15.21#ibcon#read 5, iclass 17, count 0 2006.201.16:33:15.21#ibcon#about to read 6, iclass 17, count 0 2006.201.16:33:15.21#ibcon#read 6, iclass 17, count 0 2006.201.16:33:15.21#ibcon#end of sib2, iclass 17, count 0 2006.201.16:33:15.21#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:33:15.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:33:15.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:33:15.21#ibcon#*before write, iclass 17, count 0 2006.201.16:33:15.21#ibcon#enter sib2, iclass 17, count 0 2006.201.16:33:15.21#ibcon#flushed, iclass 17, count 0 2006.201.16:33:15.21#ibcon#about to write, iclass 17, count 0 2006.201.16:33:15.21#ibcon#wrote, iclass 17, count 0 2006.201.16:33:15.21#ibcon#about to read 3, iclass 17, count 0 2006.201.16:33:15.25#ibcon#read 3, iclass 17, count 0 2006.201.16:33:15.25#ibcon#about to read 4, iclass 17, count 0 2006.201.16:33:15.25#ibcon#read 4, iclass 17, count 0 2006.201.16:33:15.25#ibcon#about to read 5, iclass 17, count 0 2006.201.16:33:15.25#ibcon#read 5, iclass 17, count 0 2006.201.16:33:15.25#ibcon#about to read 6, iclass 17, count 0 2006.201.16:33:15.25#ibcon#read 6, iclass 17, count 0 2006.201.16:33:15.25#ibcon#end of sib2, iclass 17, count 0 2006.201.16:33:15.25#ibcon#*after write, iclass 17, count 0 2006.201.16:33:15.25#ibcon#*before return 0, iclass 17, count 0 2006.201.16:33:15.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:15.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:33:15.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:33:15.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:33:15.25$vck44/vb=6,4 2006.201.16:33:15.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.16:33:15.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.16:33:15.25#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:15.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:15.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:15.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:15.31#ibcon#enter wrdev, iclass 19, count 2 2006.201.16:33:15.31#ibcon#first serial, iclass 19, count 2 2006.201.16:33:15.31#ibcon#enter sib2, iclass 19, count 2 2006.201.16:33:15.31#ibcon#flushed, iclass 19, count 2 2006.201.16:33:15.31#ibcon#about to write, iclass 19, count 2 2006.201.16:33:15.31#ibcon#wrote, iclass 19, count 2 2006.201.16:33:15.31#ibcon#about to read 3, iclass 19, count 2 2006.201.16:33:15.33#ibcon#read 3, iclass 19, count 2 2006.201.16:33:15.33#ibcon#about to read 4, iclass 19, count 2 2006.201.16:33:15.33#ibcon#read 4, iclass 19, count 2 2006.201.16:33:15.33#ibcon#about to read 5, iclass 19, count 2 2006.201.16:33:15.33#ibcon#read 5, iclass 19, count 2 2006.201.16:33:15.33#ibcon#about to read 6, iclass 19, count 2 2006.201.16:33:15.33#ibcon#read 6, iclass 19, count 2 2006.201.16:33:15.33#ibcon#end of sib2, iclass 19, count 2 2006.201.16:33:15.33#ibcon#*mode == 0, iclass 19, count 2 2006.201.16:33:15.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.16:33:15.33#ibcon#[27=AT06-04\r\n] 2006.201.16:33:15.33#ibcon#*before write, iclass 19, count 2 2006.201.16:33:15.33#ibcon#enter sib2, iclass 19, count 2 2006.201.16:33:15.33#ibcon#flushed, iclass 19, count 2 2006.201.16:33:15.33#ibcon#about to write, iclass 19, count 2 2006.201.16:33:15.33#ibcon#wrote, iclass 19, count 2 2006.201.16:33:15.33#ibcon#about to read 3, iclass 19, count 2 2006.201.16:33:15.36#ibcon#read 3, iclass 19, count 2 2006.201.16:33:15.36#ibcon#about to read 4, iclass 19, count 2 2006.201.16:33:15.36#ibcon#read 4, iclass 19, count 2 2006.201.16:33:15.36#ibcon#about to read 5, iclass 19, count 2 2006.201.16:33:15.36#ibcon#read 5, iclass 19, count 2 2006.201.16:33:15.36#ibcon#about to read 6, iclass 19, count 2 2006.201.16:33:15.36#ibcon#read 6, iclass 19, count 2 2006.201.16:33:15.36#ibcon#end of sib2, iclass 19, count 2 2006.201.16:33:15.36#ibcon#*after write, iclass 19, count 2 2006.201.16:33:15.36#ibcon#*before return 0, iclass 19, count 2 2006.201.16:33:15.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:15.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:33:15.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.16:33:15.36#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:15.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:15.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:15.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:15.48#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:33:15.48#ibcon#first serial, iclass 19, count 0 2006.201.16:33:15.48#ibcon#enter sib2, iclass 19, count 0 2006.201.16:33:15.48#ibcon#flushed, iclass 19, count 0 2006.201.16:33:15.48#ibcon#about to write, iclass 19, count 0 2006.201.16:33:15.48#ibcon#wrote, iclass 19, count 0 2006.201.16:33:15.48#ibcon#about to read 3, iclass 19, count 0 2006.201.16:33:15.50#ibcon#read 3, iclass 19, count 0 2006.201.16:33:15.50#ibcon#about to read 4, iclass 19, count 0 2006.201.16:33:15.50#ibcon#read 4, iclass 19, count 0 2006.201.16:33:15.50#ibcon#about to read 5, iclass 19, count 0 2006.201.16:33:15.50#ibcon#read 5, iclass 19, count 0 2006.201.16:33:15.50#ibcon#about to read 6, iclass 19, count 0 2006.201.16:33:15.50#ibcon#read 6, iclass 19, count 0 2006.201.16:33:15.50#ibcon#end of sib2, iclass 19, count 0 2006.201.16:33:15.50#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:33:15.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:33:15.50#ibcon#[27=USB\r\n] 2006.201.16:33:15.50#ibcon#*before write, iclass 19, count 0 2006.201.16:33:15.50#ibcon#enter sib2, iclass 19, count 0 2006.201.16:33:15.50#ibcon#flushed, iclass 19, count 0 2006.201.16:33:15.50#ibcon#about to write, iclass 19, count 0 2006.201.16:33:15.50#ibcon#wrote, iclass 19, count 0 2006.201.16:33:15.50#ibcon#about to read 3, iclass 19, count 0 2006.201.16:33:15.53#ibcon#read 3, iclass 19, count 0 2006.201.16:33:15.53#ibcon#about to read 4, iclass 19, count 0 2006.201.16:33:15.53#ibcon#read 4, iclass 19, count 0 2006.201.16:33:15.53#ibcon#about to read 5, iclass 19, count 0 2006.201.16:33:15.53#ibcon#read 5, iclass 19, count 0 2006.201.16:33:15.53#ibcon#about to read 6, iclass 19, count 0 2006.201.16:33:15.53#ibcon#read 6, iclass 19, count 0 2006.201.16:33:15.53#ibcon#end of sib2, iclass 19, count 0 2006.201.16:33:15.53#ibcon#*after write, iclass 19, count 0 2006.201.16:33:15.53#ibcon#*before return 0, iclass 19, count 0 2006.201.16:33:15.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:15.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:33:15.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:33:15.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:33:15.53$vck44/vblo=7,734.99 2006.201.16:33:15.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.16:33:15.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.16:33:15.53#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:15.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:15.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:15.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:15.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:33:15.53#ibcon#first serial, iclass 21, count 0 2006.201.16:33:15.53#ibcon#enter sib2, iclass 21, count 0 2006.201.16:33:15.53#ibcon#flushed, iclass 21, count 0 2006.201.16:33:15.53#ibcon#about to write, iclass 21, count 0 2006.201.16:33:15.53#ibcon#wrote, iclass 21, count 0 2006.201.16:33:15.53#ibcon#about to read 3, iclass 21, count 0 2006.201.16:33:15.55#ibcon#read 3, iclass 21, count 0 2006.201.16:33:15.55#ibcon#about to read 4, iclass 21, count 0 2006.201.16:33:15.55#ibcon#read 4, iclass 21, count 0 2006.201.16:33:15.55#ibcon#about to read 5, iclass 21, count 0 2006.201.16:33:15.55#ibcon#read 5, iclass 21, count 0 2006.201.16:33:15.55#ibcon#about to read 6, iclass 21, count 0 2006.201.16:33:15.55#ibcon#read 6, iclass 21, count 0 2006.201.16:33:15.55#ibcon#end of sib2, iclass 21, count 0 2006.201.16:33:15.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:33:15.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:33:15.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:33:15.55#ibcon#*before write, iclass 21, count 0 2006.201.16:33:15.55#ibcon#enter sib2, iclass 21, count 0 2006.201.16:33:15.55#ibcon#flushed, iclass 21, count 0 2006.201.16:33:15.55#ibcon#about to write, iclass 21, count 0 2006.201.16:33:15.55#ibcon#wrote, iclass 21, count 0 2006.201.16:33:15.55#ibcon#about to read 3, iclass 21, count 0 2006.201.16:33:15.59#ibcon#read 3, iclass 21, count 0 2006.201.16:33:15.59#ibcon#about to read 4, iclass 21, count 0 2006.201.16:33:15.59#ibcon#read 4, iclass 21, count 0 2006.201.16:33:15.59#ibcon#about to read 5, iclass 21, count 0 2006.201.16:33:15.59#ibcon#read 5, iclass 21, count 0 2006.201.16:33:15.59#ibcon#about to read 6, iclass 21, count 0 2006.201.16:33:15.59#ibcon#read 6, iclass 21, count 0 2006.201.16:33:15.59#ibcon#end of sib2, iclass 21, count 0 2006.201.16:33:15.59#ibcon#*after write, iclass 21, count 0 2006.201.16:33:15.59#ibcon#*before return 0, iclass 21, count 0 2006.201.16:33:15.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:15.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:33:15.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:33:15.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:33:15.59$vck44/vb=7,4 2006.201.16:33:15.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.16:33:15.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.16:33:15.59#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:15.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:15.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:15.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:15.65#ibcon#enter wrdev, iclass 23, count 2 2006.201.16:33:15.65#ibcon#first serial, iclass 23, count 2 2006.201.16:33:15.65#ibcon#enter sib2, iclass 23, count 2 2006.201.16:33:15.65#ibcon#flushed, iclass 23, count 2 2006.201.16:33:15.65#ibcon#about to write, iclass 23, count 2 2006.201.16:33:15.65#ibcon#wrote, iclass 23, count 2 2006.201.16:33:15.65#ibcon#about to read 3, iclass 23, count 2 2006.201.16:33:15.67#ibcon#read 3, iclass 23, count 2 2006.201.16:33:15.67#ibcon#about to read 4, iclass 23, count 2 2006.201.16:33:15.67#ibcon#read 4, iclass 23, count 2 2006.201.16:33:15.67#ibcon#about to read 5, iclass 23, count 2 2006.201.16:33:15.67#ibcon#read 5, iclass 23, count 2 2006.201.16:33:15.67#ibcon#about to read 6, iclass 23, count 2 2006.201.16:33:15.67#ibcon#read 6, iclass 23, count 2 2006.201.16:33:15.67#ibcon#end of sib2, iclass 23, count 2 2006.201.16:33:15.67#ibcon#*mode == 0, iclass 23, count 2 2006.201.16:33:15.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.16:33:15.67#ibcon#[27=AT07-04\r\n] 2006.201.16:33:15.67#ibcon#*before write, iclass 23, count 2 2006.201.16:33:15.67#ibcon#enter sib2, iclass 23, count 2 2006.201.16:33:15.67#ibcon#flushed, iclass 23, count 2 2006.201.16:33:15.67#ibcon#about to write, iclass 23, count 2 2006.201.16:33:15.67#ibcon#wrote, iclass 23, count 2 2006.201.16:33:15.67#ibcon#about to read 3, iclass 23, count 2 2006.201.16:33:15.70#ibcon#read 3, iclass 23, count 2 2006.201.16:33:15.70#ibcon#about to read 4, iclass 23, count 2 2006.201.16:33:15.70#ibcon#read 4, iclass 23, count 2 2006.201.16:33:15.70#ibcon#about to read 5, iclass 23, count 2 2006.201.16:33:15.70#ibcon#read 5, iclass 23, count 2 2006.201.16:33:15.70#ibcon#about to read 6, iclass 23, count 2 2006.201.16:33:15.70#ibcon#read 6, iclass 23, count 2 2006.201.16:33:15.70#ibcon#end of sib2, iclass 23, count 2 2006.201.16:33:15.70#ibcon#*after write, iclass 23, count 2 2006.201.16:33:15.70#ibcon#*before return 0, iclass 23, count 2 2006.201.16:33:15.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:15.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:33:15.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.16:33:15.70#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:15.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:15.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:15.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:15.82#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:33:15.82#ibcon#first serial, iclass 23, count 0 2006.201.16:33:15.82#ibcon#enter sib2, iclass 23, count 0 2006.201.16:33:15.82#ibcon#flushed, iclass 23, count 0 2006.201.16:33:15.82#ibcon#about to write, iclass 23, count 0 2006.201.16:33:15.82#ibcon#wrote, iclass 23, count 0 2006.201.16:33:15.82#ibcon#about to read 3, iclass 23, count 0 2006.201.16:33:15.84#ibcon#read 3, iclass 23, count 0 2006.201.16:33:15.84#ibcon#about to read 4, iclass 23, count 0 2006.201.16:33:15.84#ibcon#read 4, iclass 23, count 0 2006.201.16:33:15.84#ibcon#about to read 5, iclass 23, count 0 2006.201.16:33:15.84#ibcon#read 5, iclass 23, count 0 2006.201.16:33:15.84#ibcon#about to read 6, iclass 23, count 0 2006.201.16:33:15.84#ibcon#read 6, iclass 23, count 0 2006.201.16:33:15.84#ibcon#end of sib2, iclass 23, count 0 2006.201.16:33:15.84#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:33:15.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:33:15.84#ibcon#[27=USB\r\n] 2006.201.16:33:15.84#ibcon#*before write, iclass 23, count 0 2006.201.16:33:15.84#ibcon#enter sib2, iclass 23, count 0 2006.201.16:33:15.84#ibcon#flushed, iclass 23, count 0 2006.201.16:33:15.84#ibcon#about to write, iclass 23, count 0 2006.201.16:33:15.84#ibcon#wrote, iclass 23, count 0 2006.201.16:33:15.84#ibcon#about to read 3, iclass 23, count 0 2006.201.16:33:15.87#ibcon#read 3, iclass 23, count 0 2006.201.16:33:15.87#ibcon#about to read 4, iclass 23, count 0 2006.201.16:33:15.87#ibcon#read 4, iclass 23, count 0 2006.201.16:33:15.87#ibcon#about to read 5, iclass 23, count 0 2006.201.16:33:15.87#ibcon#read 5, iclass 23, count 0 2006.201.16:33:15.87#ibcon#about to read 6, iclass 23, count 0 2006.201.16:33:15.87#ibcon#read 6, iclass 23, count 0 2006.201.16:33:15.87#ibcon#end of sib2, iclass 23, count 0 2006.201.16:33:15.87#ibcon#*after write, iclass 23, count 0 2006.201.16:33:15.87#ibcon#*before return 0, iclass 23, count 0 2006.201.16:33:15.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:15.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:33:15.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:33:15.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:33:15.87$vck44/vblo=8,744.99 2006.201.16:33:15.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.16:33:15.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.16:33:15.87#ibcon#ireg 17 cls_cnt 0 2006.201.16:33:15.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:15.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:15.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:15.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:33:15.87#ibcon#first serial, iclass 25, count 0 2006.201.16:33:15.87#ibcon#enter sib2, iclass 25, count 0 2006.201.16:33:15.87#ibcon#flushed, iclass 25, count 0 2006.201.16:33:15.87#ibcon#about to write, iclass 25, count 0 2006.201.16:33:15.87#ibcon#wrote, iclass 25, count 0 2006.201.16:33:15.87#ibcon#about to read 3, iclass 25, count 0 2006.201.16:33:15.89#ibcon#read 3, iclass 25, count 0 2006.201.16:33:15.89#ibcon#about to read 4, iclass 25, count 0 2006.201.16:33:15.89#ibcon#read 4, iclass 25, count 0 2006.201.16:33:15.89#ibcon#about to read 5, iclass 25, count 0 2006.201.16:33:15.89#ibcon#read 5, iclass 25, count 0 2006.201.16:33:15.89#ibcon#about to read 6, iclass 25, count 0 2006.201.16:33:15.89#ibcon#read 6, iclass 25, count 0 2006.201.16:33:15.89#ibcon#end of sib2, iclass 25, count 0 2006.201.16:33:15.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:33:15.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:33:15.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:33:15.89#ibcon#*before write, iclass 25, count 0 2006.201.16:33:15.89#ibcon#enter sib2, iclass 25, count 0 2006.201.16:33:15.89#ibcon#flushed, iclass 25, count 0 2006.201.16:33:15.89#ibcon#about to write, iclass 25, count 0 2006.201.16:33:15.89#ibcon#wrote, iclass 25, count 0 2006.201.16:33:15.89#ibcon#about to read 3, iclass 25, count 0 2006.201.16:33:15.94#ibcon#read 3, iclass 25, count 0 2006.201.16:33:15.94#ibcon#about to read 4, iclass 25, count 0 2006.201.16:33:15.94#ibcon#read 4, iclass 25, count 0 2006.201.16:33:15.94#ibcon#about to read 5, iclass 25, count 0 2006.201.16:33:15.94#ibcon#read 5, iclass 25, count 0 2006.201.16:33:15.94#ibcon#about to read 6, iclass 25, count 0 2006.201.16:33:15.94#ibcon#read 6, iclass 25, count 0 2006.201.16:33:15.94#ibcon#end of sib2, iclass 25, count 0 2006.201.16:33:15.94#ibcon#*after write, iclass 25, count 0 2006.201.16:33:15.94#ibcon#*before return 0, iclass 25, count 0 2006.201.16:33:15.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:15.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:33:15.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:33:15.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:33:15.94$vck44/vb=8,4 2006.201.16:33:15.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.16:33:15.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.16:33:15.94#ibcon#ireg 11 cls_cnt 2 2006.201.16:33:15.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:15.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:15.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:15.99#ibcon#enter wrdev, iclass 27, count 2 2006.201.16:33:15.99#ibcon#first serial, iclass 27, count 2 2006.201.16:33:15.99#ibcon#enter sib2, iclass 27, count 2 2006.201.16:33:15.99#ibcon#flushed, iclass 27, count 2 2006.201.16:33:15.99#ibcon#about to write, iclass 27, count 2 2006.201.16:33:15.99#ibcon#wrote, iclass 27, count 2 2006.201.16:33:15.99#ibcon#about to read 3, iclass 27, count 2 2006.201.16:33:16.01#ibcon#read 3, iclass 27, count 2 2006.201.16:33:16.01#ibcon#about to read 4, iclass 27, count 2 2006.201.16:33:16.01#ibcon#read 4, iclass 27, count 2 2006.201.16:33:16.01#ibcon#about to read 5, iclass 27, count 2 2006.201.16:33:16.01#ibcon#read 5, iclass 27, count 2 2006.201.16:33:16.01#ibcon#about to read 6, iclass 27, count 2 2006.201.16:33:16.01#ibcon#read 6, iclass 27, count 2 2006.201.16:33:16.01#ibcon#end of sib2, iclass 27, count 2 2006.201.16:33:16.01#ibcon#*mode == 0, iclass 27, count 2 2006.201.16:33:16.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.16:33:16.01#ibcon#[27=AT08-04\r\n] 2006.201.16:33:16.01#ibcon#*before write, iclass 27, count 2 2006.201.16:33:16.01#ibcon#enter sib2, iclass 27, count 2 2006.201.16:33:16.01#ibcon#flushed, iclass 27, count 2 2006.201.16:33:16.01#ibcon#about to write, iclass 27, count 2 2006.201.16:33:16.01#ibcon#wrote, iclass 27, count 2 2006.201.16:33:16.01#ibcon#about to read 3, iclass 27, count 2 2006.201.16:33:16.04#abcon#<5=/04 0.9 1.3 20.821001002.6\r\n> 2006.201.16:33:16.04#ibcon#read 3, iclass 27, count 2 2006.201.16:33:16.04#ibcon#about to read 4, iclass 27, count 2 2006.201.16:33:16.04#ibcon#read 4, iclass 27, count 2 2006.201.16:33:16.04#ibcon#about to read 5, iclass 27, count 2 2006.201.16:33:16.04#ibcon#read 5, iclass 27, count 2 2006.201.16:33:16.04#ibcon#about to read 6, iclass 27, count 2 2006.201.16:33:16.04#ibcon#read 6, iclass 27, count 2 2006.201.16:33:16.04#ibcon#end of sib2, iclass 27, count 2 2006.201.16:33:16.04#ibcon#*after write, iclass 27, count 2 2006.201.16:33:16.04#ibcon#*before return 0, iclass 27, count 2 2006.201.16:33:16.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:16.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:33:16.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.16:33:16.04#ibcon#ireg 7 cls_cnt 0 2006.201.16:33:16.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:16.06#abcon#{5=INTERFACE CLEAR} 2006.201.16:33:16.12#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:33:16.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:16.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:16.16#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:33:16.16#ibcon#first serial, iclass 27, count 0 2006.201.16:33:16.16#ibcon#enter sib2, iclass 27, count 0 2006.201.16:33:16.16#ibcon#flushed, iclass 27, count 0 2006.201.16:33:16.16#ibcon#about to write, iclass 27, count 0 2006.201.16:33:16.16#ibcon#wrote, iclass 27, count 0 2006.201.16:33:16.16#ibcon#about to read 3, iclass 27, count 0 2006.201.16:33:16.18#ibcon#read 3, iclass 27, count 0 2006.201.16:33:16.18#ibcon#about to read 4, iclass 27, count 0 2006.201.16:33:16.18#ibcon#read 4, iclass 27, count 0 2006.201.16:33:16.18#ibcon#about to read 5, iclass 27, count 0 2006.201.16:33:16.18#ibcon#read 5, iclass 27, count 0 2006.201.16:33:16.18#ibcon#about to read 6, iclass 27, count 0 2006.201.16:33:16.18#ibcon#read 6, iclass 27, count 0 2006.201.16:33:16.18#ibcon#end of sib2, iclass 27, count 0 2006.201.16:33:16.18#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:33:16.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:33:16.18#ibcon#[27=USB\r\n] 2006.201.16:33:16.18#ibcon#*before write, iclass 27, count 0 2006.201.16:33:16.18#ibcon#enter sib2, iclass 27, count 0 2006.201.16:33:16.18#ibcon#flushed, iclass 27, count 0 2006.201.16:33:16.18#ibcon#about to write, iclass 27, count 0 2006.201.16:33:16.18#ibcon#wrote, iclass 27, count 0 2006.201.16:33:16.18#ibcon#about to read 3, iclass 27, count 0 2006.201.16:33:16.21#ibcon#read 3, iclass 27, count 0 2006.201.16:33:16.21#ibcon#about to read 4, iclass 27, count 0 2006.201.16:33:16.21#ibcon#read 4, iclass 27, count 0 2006.201.16:33:16.21#ibcon#about to read 5, iclass 27, count 0 2006.201.16:33:16.21#ibcon#read 5, iclass 27, count 0 2006.201.16:33:16.21#ibcon#about to read 6, iclass 27, count 0 2006.201.16:33:16.21#ibcon#read 6, iclass 27, count 0 2006.201.16:33:16.21#ibcon#end of sib2, iclass 27, count 0 2006.201.16:33:16.21#ibcon#*after write, iclass 27, count 0 2006.201.16:33:16.21#ibcon#*before return 0, iclass 27, count 0 2006.201.16:33:16.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:16.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:33:16.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:33:16.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:33:16.21$vck44/vabw=wide 2006.201.16:33:16.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.16:33:16.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.16:33:16.21#ibcon#ireg 8 cls_cnt 0 2006.201.16:33:16.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:16.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:16.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:16.21#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:33:16.21#ibcon#first serial, iclass 33, count 0 2006.201.16:33:16.21#ibcon#enter sib2, iclass 33, count 0 2006.201.16:33:16.21#ibcon#flushed, iclass 33, count 0 2006.201.16:33:16.21#ibcon#about to write, iclass 33, count 0 2006.201.16:33:16.21#ibcon#wrote, iclass 33, count 0 2006.201.16:33:16.21#ibcon#about to read 3, iclass 33, count 0 2006.201.16:33:16.23#ibcon#read 3, iclass 33, count 0 2006.201.16:33:16.23#ibcon#about to read 4, iclass 33, count 0 2006.201.16:33:16.23#ibcon#read 4, iclass 33, count 0 2006.201.16:33:16.23#ibcon#about to read 5, iclass 33, count 0 2006.201.16:33:16.23#ibcon#read 5, iclass 33, count 0 2006.201.16:33:16.23#ibcon#about to read 6, iclass 33, count 0 2006.201.16:33:16.23#ibcon#read 6, iclass 33, count 0 2006.201.16:33:16.23#ibcon#end of sib2, iclass 33, count 0 2006.201.16:33:16.23#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:33:16.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:33:16.23#ibcon#[25=BW32\r\n] 2006.201.16:33:16.23#ibcon#*before write, iclass 33, count 0 2006.201.16:33:16.23#ibcon#enter sib2, iclass 33, count 0 2006.201.16:33:16.23#ibcon#flushed, iclass 33, count 0 2006.201.16:33:16.23#ibcon#about to write, iclass 33, count 0 2006.201.16:33:16.23#ibcon#wrote, iclass 33, count 0 2006.201.16:33:16.23#ibcon#about to read 3, iclass 33, count 0 2006.201.16:33:16.26#ibcon#read 3, iclass 33, count 0 2006.201.16:33:16.26#ibcon#about to read 4, iclass 33, count 0 2006.201.16:33:16.26#ibcon#read 4, iclass 33, count 0 2006.201.16:33:16.26#ibcon#about to read 5, iclass 33, count 0 2006.201.16:33:16.26#ibcon#read 5, iclass 33, count 0 2006.201.16:33:16.26#ibcon#about to read 6, iclass 33, count 0 2006.201.16:33:16.26#ibcon#read 6, iclass 33, count 0 2006.201.16:33:16.26#ibcon#end of sib2, iclass 33, count 0 2006.201.16:33:16.26#ibcon#*after write, iclass 33, count 0 2006.201.16:33:16.26#ibcon#*before return 0, iclass 33, count 0 2006.201.16:33:16.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:16.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:33:16.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:33:16.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:33:16.26$vck44/vbbw=wide 2006.201.16:33:16.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.16:33:16.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.16:33:16.26#ibcon#ireg 8 cls_cnt 0 2006.201.16:33:16.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:33:16.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:33:16.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:33:16.33#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:33:16.33#ibcon#first serial, iclass 35, count 0 2006.201.16:33:16.33#ibcon#enter sib2, iclass 35, count 0 2006.201.16:33:16.33#ibcon#flushed, iclass 35, count 0 2006.201.16:33:16.33#ibcon#about to write, iclass 35, count 0 2006.201.16:33:16.33#ibcon#wrote, iclass 35, count 0 2006.201.16:33:16.33#ibcon#about to read 3, iclass 35, count 0 2006.201.16:33:16.35#ibcon#read 3, iclass 35, count 0 2006.201.16:33:16.35#ibcon#about to read 4, iclass 35, count 0 2006.201.16:33:16.35#ibcon#read 4, iclass 35, count 0 2006.201.16:33:16.35#ibcon#about to read 5, iclass 35, count 0 2006.201.16:33:16.35#ibcon#read 5, iclass 35, count 0 2006.201.16:33:16.35#ibcon#about to read 6, iclass 35, count 0 2006.201.16:33:16.35#ibcon#read 6, iclass 35, count 0 2006.201.16:33:16.35#ibcon#end of sib2, iclass 35, count 0 2006.201.16:33:16.35#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:33:16.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:33:16.35#ibcon#[27=BW32\r\n] 2006.201.16:33:16.35#ibcon#*before write, iclass 35, count 0 2006.201.16:33:16.35#ibcon#enter sib2, iclass 35, count 0 2006.201.16:33:16.35#ibcon#flushed, iclass 35, count 0 2006.201.16:33:16.35#ibcon#about to write, iclass 35, count 0 2006.201.16:33:16.35#ibcon#wrote, iclass 35, count 0 2006.201.16:33:16.35#ibcon#about to read 3, iclass 35, count 0 2006.201.16:33:16.38#ibcon#read 3, iclass 35, count 0 2006.201.16:33:16.38#ibcon#about to read 4, iclass 35, count 0 2006.201.16:33:16.38#ibcon#read 4, iclass 35, count 0 2006.201.16:33:16.38#ibcon#about to read 5, iclass 35, count 0 2006.201.16:33:16.38#ibcon#read 5, iclass 35, count 0 2006.201.16:33:16.38#ibcon#about to read 6, iclass 35, count 0 2006.201.16:33:16.38#ibcon#read 6, iclass 35, count 0 2006.201.16:33:16.38#ibcon#end of sib2, iclass 35, count 0 2006.201.16:33:16.38#ibcon#*after write, iclass 35, count 0 2006.201.16:33:16.38#ibcon#*before return 0, iclass 35, count 0 2006.201.16:33:16.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:33:16.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:33:16.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:33:16.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:33:16.38$setupk4/ifdk4 2006.201.16:33:16.38$ifdk4/lo= 2006.201.16:33:16.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:33:16.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:33:16.38$ifdk4/patch= 2006.201.16:33:16.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:33:16.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:33:16.38$setupk4/!*+20s 2006.201.16:33:20.14#trakl#Source acquired 2006.201.16:33:21.14#flagr#flagr/antenna,acquired 2006.201.16:33:26.21#abcon#<5=/04 0.9 1.3 20.821001002.6\r\n> 2006.201.16:33:26.23#abcon#{5=INTERFACE CLEAR} 2006.201.16:33:26.29#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:33:30.85$setupk4/"tpicd 2006.201.16:33:30.85$setupk4/echo=off 2006.201.16:33:30.85$setupk4/xlog=off 2006.201.16:33:30.85:!2006.201.16:34:17 2006.201.16:34:17.00:preob 2006.201.16:34:17.14/onsource/TRACKING 2006.201.16:34:17.14:!2006.201.16:34:27 2006.201.16:34:27.00:"tape 2006.201.16:34:27.00:"st=record 2006.201.16:34:27.00:data_valid=on 2006.201.16:34:27.00:midob 2006.201.16:34:27.14/onsource/TRACKING 2006.201.16:34:27.14/wx/20.82,1002.6,100 2006.201.16:34:27.34/cable/+6.4767E-03 2006.201.16:34:28.43/va/01,08,usb,yes,39,41 2006.201.16:34:28.43/va/02,07,usb,yes,42,43 2006.201.16:34:28.43/va/03,08,usb,yes,38,39 2006.201.16:34:28.43/va/04,07,usb,yes,43,45 2006.201.16:34:28.43/va/05,04,usb,yes,38,39 2006.201.16:34:28.43/va/06,05,usb,yes,38,38 2006.201.16:34:28.43/va/07,05,usb,yes,37,39 2006.201.16:34:28.43/va/08,04,usb,yes,37,44 2006.201.16:34:28.66/valo/01,524.99,yes,locked 2006.201.16:34:28.66/valo/02,534.99,yes,locked 2006.201.16:34:28.66/valo/03,564.99,yes,locked 2006.201.16:34:28.66/valo/04,624.99,yes,locked 2006.201.16:34:28.66/valo/05,734.99,yes,locked 2006.201.16:34:28.66/valo/06,814.99,yes,locked 2006.201.16:34:28.66/valo/07,864.99,yes,locked 2006.201.16:34:28.66/valo/08,884.99,yes,locked 2006.201.16:34:29.75/vb/01,04,usb,yes,29,27 2006.201.16:34:29.75/vb/02,05,usb,yes,27,27 2006.201.16:34:29.75/vb/03,04,usb,yes,28,31 2006.201.16:34:29.75/vb/04,05,usb,yes,29,27 2006.201.16:34:29.75/vb/05,04,usb,yes,25,27 2006.201.16:34:29.75/vb/06,04,usb,yes,29,26 2006.201.16:34:29.75/vb/07,04,usb,yes,29,29 2006.201.16:34:29.75/vb/08,04,usb,yes,27,30 2006.201.16:34:29.99/vblo/01,629.99,yes,locked 2006.201.16:34:29.99/vblo/02,634.99,yes,locked 2006.201.16:34:29.99/vblo/03,649.99,yes,locked 2006.201.16:34:29.99/vblo/04,679.99,yes,locked 2006.201.16:34:29.99/vblo/05,709.99,yes,locked 2006.201.16:34:29.99/vblo/06,719.99,yes,locked 2006.201.16:34:29.99/vblo/07,734.99,yes,locked 2006.201.16:34:29.99/vblo/08,744.99,yes,locked 2006.201.16:34:30.14/vabw/8 2006.201.16:34:30.29/vbbw/8 2006.201.16:34:30.40/xfe/off,on,15.2 2006.201.16:34:30.77/ifatt/23,28,28,28 2006.201.16:34:31.06/fmout-gps/S +4.57E-07 2006.201.16:34:31.13:!2006.201.16:35:47 2006.201.16:35:47.00:data_valid=off 2006.201.16:35:47.00:"et 2006.201.16:35:47.00:!+3s 2006.201.16:35:50.02:"tape 2006.201.16:35:50.02:postob 2006.201.16:35:50.17/cable/+6.4757E-03 2006.201.16:35:50.17/wx/20.82,1002.6,100 2006.201.16:35:50.23/fmout-gps/S +4.57E-07 2006.201.16:35:50.23:scan_name=201-1639,jd0607,40 2006.201.16:35:50.23:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.201.16:35:51.14#flagr#flagr/antenna,new-source 2006.201.16:35:51.14:checkk5 2006.201.16:35:51.48/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:35:51.86/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:35:52.23/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:35:52.60/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:35:52.97/chk_obsdata//k5ts1/T2011634??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.16:35:53.33/chk_obsdata//k5ts2/T2011634??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.16:35:53.70/chk_obsdata//k5ts3/T2011634??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.16:35:54.06/chk_obsdata//k5ts4/T2011634??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.16:35:54.75/k5log//k5ts1_log_newline 2006.201.16:35:55.43/k5log//k5ts2_log_newline 2006.201.16:35:56.11/k5log//k5ts3_log_newline 2006.201.16:35:56.80/k5log//k5ts4_log_newline 2006.201.16:35:56.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:35:56.83:setupk4=1 2006.201.16:35:56.83$setupk4/echo=on 2006.201.16:35:56.83$setupk4/pcalon 2006.201.16:35:56.83$pcalon/"no phase cal control is implemented here 2006.201.16:35:56.83$setupk4/"tpicd=stop 2006.201.16:35:56.83$setupk4/"rec=synch_on 2006.201.16:35:56.83$setupk4/"rec_mode=128 2006.201.16:35:56.83$setupk4/!* 2006.201.16:35:56.83$setupk4/recpk4 2006.201.16:35:56.83$recpk4/recpatch= 2006.201.16:35:56.83$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:35:56.83$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:35:56.83$setupk4/vck44 2006.201.16:35:56.83$vck44/valo=1,524.99 2006.201.16:35:56.83#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.16:35:56.83#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.16:35:56.83#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:56.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:56.83#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:56.83#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:56.83#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:35:56.83#ibcon#first serial, iclass 28, count 0 2006.201.16:35:56.83#ibcon#enter sib2, iclass 28, count 0 2006.201.16:35:56.83#ibcon#flushed, iclass 28, count 0 2006.201.16:35:56.83#ibcon#about to write, iclass 28, count 0 2006.201.16:35:56.83#ibcon#wrote, iclass 28, count 0 2006.201.16:35:56.83#ibcon#about to read 3, iclass 28, count 0 2006.201.16:35:56.87#ibcon#read 3, iclass 28, count 0 2006.201.16:35:56.87#ibcon#about to read 4, iclass 28, count 0 2006.201.16:35:56.87#ibcon#read 4, iclass 28, count 0 2006.201.16:35:56.87#ibcon#about to read 5, iclass 28, count 0 2006.201.16:35:56.87#ibcon#read 5, iclass 28, count 0 2006.201.16:35:56.87#ibcon#about to read 6, iclass 28, count 0 2006.201.16:35:56.87#ibcon#read 6, iclass 28, count 0 2006.201.16:35:56.87#ibcon#end of sib2, iclass 28, count 0 2006.201.16:35:56.87#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:35:56.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:35:56.87#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:35:56.87#ibcon#*before write, iclass 28, count 0 2006.201.16:35:56.87#ibcon#enter sib2, iclass 28, count 0 2006.201.16:35:56.87#ibcon#flushed, iclass 28, count 0 2006.201.16:35:56.87#ibcon#about to write, iclass 28, count 0 2006.201.16:35:56.87#ibcon#wrote, iclass 28, count 0 2006.201.16:35:56.87#ibcon#about to read 3, iclass 28, count 0 2006.201.16:35:56.92#ibcon#read 3, iclass 28, count 0 2006.201.16:35:56.92#ibcon#about to read 4, iclass 28, count 0 2006.201.16:35:56.92#ibcon#read 4, iclass 28, count 0 2006.201.16:35:56.92#ibcon#about to read 5, iclass 28, count 0 2006.201.16:35:56.92#ibcon#read 5, iclass 28, count 0 2006.201.16:35:56.92#ibcon#about to read 6, iclass 28, count 0 2006.201.16:35:56.92#ibcon#read 6, iclass 28, count 0 2006.201.16:35:56.92#ibcon#end of sib2, iclass 28, count 0 2006.201.16:35:56.92#ibcon#*after write, iclass 28, count 0 2006.201.16:35:56.92#ibcon#*before return 0, iclass 28, count 0 2006.201.16:35:56.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:56.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:56.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:35:56.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:35:56.92$vck44/va=1,8 2006.201.16:35:56.92#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.16:35:56.92#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.16:35:56.92#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:56.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:56.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:56.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:56.92#ibcon#enter wrdev, iclass 30, count 2 2006.201.16:35:56.92#ibcon#first serial, iclass 30, count 2 2006.201.16:35:56.92#ibcon#enter sib2, iclass 30, count 2 2006.201.16:35:56.92#ibcon#flushed, iclass 30, count 2 2006.201.16:35:56.92#ibcon#about to write, iclass 30, count 2 2006.201.16:35:56.92#ibcon#wrote, iclass 30, count 2 2006.201.16:35:56.92#ibcon#about to read 3, iclass 30, count 2 2006.201.16:35:56.94#ibcon#read 3, iclass 30, count 2 2006.201.16:35:56.94#ibcon#about to read 4, iclass 30, count 2 2006.201.16:35:56.94#ibcon#read 4, iclass 30, count 2 2006.201.16:35:56.94#ibcon#about to read 5, iclass 30, count 2 2006.201.16:35:56.94#ibcon#read 5, iclass 30, count 2 2006.201.16:35:56.94#ibcon#about to read 6, iclass 30, count 2 2006.201.16:35:56.94#ibcon#read 6, iclass 30, count 2 2006.201.16:35:56.94#ibcon#end of sib2, iclass 30, count 2 2006.201.16:35:56.94#ibcon#*mode == 0, iclass 30, count 2 2006.201.16:35:56.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.16:35:56.94#ibcon#[25=AT01-08\r\n] 2006.201.16:35:56.94#ibcon#*before write, iclass 30, count 2 2006.201.16:35:56.94#ibcon#enter sib2, iclass 30, count 2 2006.201.16:35:56.94#ibcon#flushed, iclass 30, count 2 2006.201.16:35:56.94#ibcon#about to write, iclass 30, count 2 2006.201.16:35:56.94#ibcon#wrote, iclass 30, count 2 2006.201.16:35:56.94#ibcon#about to read 3, iclass 30, count 2 2006.201.16:35:56.97#ibcon#read 3, iclass 30, count 2 2006.201.16:35:56.97#ibcon#about to read 4, iclass 30, count 2 2006.201.16:35:56.97#ibcon#read 4, iclass 30, count 2 2006.201.16:35:56.97#ibcon#about to read 5, iclass 30, count 2 2006.201.16:35:56.97#ibcon#read 5, iclass 30, count 2 2006.201.16:35:56.97#ibcon#about to read 6, iclass 30, count 2 2006.201.16:35:56.97#ibcon#read 6, iclass 30, count 2 2006.201.16:35:56.97#ibcon#end of sib2, iclass 30, count 2 2006.201.16:35:56.97#ibcon#*after write, iclass 30, count 2 2006.201.16:35:56.97#ibcon#*before return 0, iclass 30, count 2 2006.201.16:35:56.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:56.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:56.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.16:35:56.97#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:56.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:57.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:57.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:57.09#ibcon#enter wrdev, iclass 30, count 0 2006.201.16:35:57.09#ibcon#first serial, iclass 30, count 0 2006.201.16:35:57.09#ibcon#enter sib2, iclass 30, count 0 2006.201.16:35:57.09#ibcon#flushed, iclass 30, count 0 2006.201.16:35:57.09#ibcon#about to write, iclass 30, count 0 2006.201.16:35:57.09#ibcon#wrote, iclass 30, count 0 2006.201.16:35:57.09#ibcon#about to read 3, iclass 30, count 0 2006.201.16:35:57.11#ibcon#read 3, iclass 30, count 0 2006.201.16:35:57.11#ibcon#about to read 4, iclass 30, count 0 2006.201.16:35:57.11#ibcon#read 4, iclass 30, count 0 2006.201.16:35:57.11#ibcon#about to read 5, iclass 30, count 0 2006.201.16:35:57.11#ibcon#read 5, iclass 30, count 0 2006.201.16:35:57.11#ibcon#about to read 6, iclass 30, count 0 2006.201.16:35:57.11#ibcon#read 6, iclass 30, count 0 2006.201.16:35:57.11#ibcon#end of sib2, iclass 30, count 0 2006.201.16:35:57.11#ibcon#*mode == 0, iclass 30, count 0 2006.201.16:35:57.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.16:35:57.11#ibcon#[25=USB\r\n] 2006.201.16:35:57.11#ibcon#*before write, iclass 30, count 0 2006.201.16:35:57.11#ibcon#enter sib2, iclass 30, count 0 2006.201.16:35:57.11#ibcon#flushed, iclass 30, count 0 2006.201.16:35:57.11#ibcon#about to write, iclass 30, count 0 2006.201.16:35:57.11#ibcon#wrote, iclass 30, count 0 2006.201.16:35:57.11#ibcon#about to read 3, iclass 30, count 0 2006.201.16:35:57.14#ibcon#read 3, iclass 30, count 0 2006.201.16:35:57.14#ibcon#about to read 4, iclass 30, count 0 2006.201.16:35:57.14#ibcon#read 4, iclass 30, count 0 2006.201.16:35:57.14#ibcon#about to read 5, iclass 30, count 0 2006.201.16:35:57.14#ibcon#read 5, iclass 30, count 0 2006.201.16:35:57.14#ibcon#about to read 6, iclass 30, count 0 2006.201.16:35:57.14#ibcon#read 6, iclass 30, count 0 2006.201.16:35:57.14#ibcon#end of sib2, iclass 30, count 0 2006.201.16:35:57.14#ibcon#*after write, iclass 30, count 0 2006.201.16:35:57.14#ibcon#*before return 0, iclass 30, count 0 2006.201.16:35:57.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:57.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:57.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.16:35:57.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.16:35:57.14$vck44/valo=2,534.99 2006.201.16:35:57.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.16:35:57.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.16:35:57.14#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:57.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:57.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:57.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:57.14#ibcon#enter wrdev, iclass 32, count 0 2006.201.16:35:57.14#ibcon#first serial, iclass 32, count 0 2006.201.16:35:57.14#ibcon#enter sib2, iclass 32, count 0 2006.201.16:35:57.14#ibcon#flushed, iclass 32, count 0 2006.201.16:35:57.14#ibcon#about to write, iclass 32, count 0 2006.201.16:35:57.14#ibcon#wrote, iclass 32, count 0 2006.201.16:35:57.14#ibcon#about to read 3, iclass 32, count 0 2006.201.16:35:57.16#ibcon#read 3, iclass 32, count 0 2006.201.16:35:57.16#ibcon#about to read 4, iclass 32, count 0 2006.201.16:35:57.16#ibcon#read 4, iclass 32, count 0 2006.201.16:35:57.16#ibcon#about to read 5, iclass 32, count 0 2006.201.16:35:57.16#ibcon#read 5, iclass 32, count 0 2006.201.16:35:57.16#ibcon#about to read 6, iclass 32, count 0 2006.201.16:35:57.16#ibcon#read 6, iclass 32, count 0 2006.201.16:35:57.16#ibcon#end of sib2, iclass 32, count 0 2006.201.16:35:57.16#ibcon#*mode == 0, iclass 32, count 0 2006.201.16:35:57.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.16:35:57.16#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:35:57.16#ibcon#*before write, iclass 32, count 0 2006.201.16:35:57.16#ibcon#enter sib2, iclass 32, count 0 2006.201.16:35:57.16#ibcon#flushed, iclass 32, count 0 2006.201.16:35:57.16#ibcon#about to write, iclass 32, count 0 2006.201.16:35:57.16#ibcon#wrote, iclass 32, count 0 2006.201.16:35:57.16#ibcon#about to read 3, iclass 32, count 0 2006.201.16:35:57.21#ibcon#read 3, iclass 32, count 0 2006.201.16:35:57.21#ibcon#about to read 4, iclass 32, count 0 2006.201.16:35:57.21#ibcon#read 4, iclass 32, count 0 2006.201.16:35:57.21#ibcon#about to read 5, iclass 32, count 0 2006.201.16:35:57.21#ibcon#read 5, iclass 32, count 0 2006.201.16:35:57.21#ibcon#about to read 6, iclass 32, count 0 2006.201.16:35:57.21#ibcon#read 6, iclass 32, count 0 2006.201.16:35:57.21#ibcon#end of sib2, iclass 32, count 0 2006.201.16:35:57.21#ibcon#*after write, iclass 32, count 0 2006.201.16:35:57.21#ibcon#*before return 0, iclass 32, count 0 2006.201.16:35:57.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:57.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:57.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.16:35:57.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.16:35:57.21$vck44/va=2,7 2006.201.16:35:57.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.16:35:57.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.16:35:57.21#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:57.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:57.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:57.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:57.26#ibcon#enter wrdev, iclass 34, count 2 2006.201.16:35:57.26#ibcon#first serial, iclass 34, count 2 2006.201.16:35:57.26#ibcon#enter sib2, iclass 34, count 2 2006.201.16:35:57.26#ibcon#flushed, iclass 34, count 2 2006.201.16:35:57.26#ibcon#about to write, iclass 34, count 2 2006.201.16:35:57.26#ibcon#wrote, iclass 34, count 2 2006.201.16:35:57.26#ibcon#about to read 3, iclass 34, count 2 2006.201.16:35:57.28#ibcon#read 3, iclass 34, count 2 2006.201.16:35:57.28#ibcon#about to read 4, iclass 34, count 2 2006.201.16:35:57.28#ibcon#read 4, iclass 34, count 2 2006.201.16:35:57.28#ibcon#about to read 5, iclass 34, count 2 2006.201.16:35:57.28#ibcon#read 5, iclass 34, count 2 2006.201.16:35:57.28#ibcon#about to read 6, iclass 34, count 2 2006.201.16:35:57.28#ibcon#read 6, iclass 34, count 2 2006.201.16:35:57.28#ibcon#end of sib2, iclass 34, count 2 2006.201.16:35:57.28#ibcon#*mode == 0, iclass 34, count 2 2006.201.16:35:57.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.16:35:57.28#ibcon#[25=AT02-07\r\n] 2006.201.16:35:57.28#ibcon#*before write, iclass 34, count 2 2006.201.16:35:57.28#ibcon#enter sib2, iclass 34, count 2 2006.201.16:35:57.28#ibcon#flushed, iclass 34, count 2 2006.201.16:35:57.28#ibcon#about to write, iclass 34, count 2 2006.201.16:35:57.28#ibcon#wrote, iclass 34, count 2 2006.201.16:35:57.28#ibcon#about to read 3, iclass 34, count 2 2006.201.16:35:57.31#ibcon#read 3, iclass 34, count 2 2006.201.16:35:57.31#ibcon#about to read 4, iclass 34, count 2 2006.201.16:35:57.31#ibcon#read 4, iclass 34, count 2 2006.201.16:35:57.31#ibcon#about to read 5, iclass 34, count 2 2006.201.16:35:57.31#ibcon#read 5, iclass 34, count 2 2006.201.16:35:57.31#ibcon#about to read 6, iclass 34, count 2 2006.201.16:35:57.31#ibcon#read 6, iclass 34, count 2 2006.201.16:35:57.31#ibcon#end of sib2, iclass 34, count 2 2006.201.16:35:57.31#ibcon#*after write, iclass 34, count 2 2006.201.16:35:57.31#ibcon#*before return 0, iclass 34, count 2 2006.201.16:35:57.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:57.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:57.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.16:35:57.31#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:57.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:35:57.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:35:57.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:35:57.43#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:35:57.43#ibcon#first serial, iclass 34, count 0 2006.201.16:35:57.43#ibcon#enter sib2, iclass 34, count 0 2006.201.16:35:57.43#ibcon#flushed, iclass 34, count 0 2006.201.16:35:57.43#ibcon#about to write, iclass 34, count 0 2006.201.16:35:57.43#ibcon#wrote, iclass 34, count 0 2006.201.16:35:57.43#ibcon#about to read 3, iclass 34, count 0 2006.201.16:35:57.45#ibcon#read 3, iclass 34, count 0 2006.201.16:35:57.45#ibcon#about to read 4, iclass 34, count 0 2006.201.16:35:57.45#ibcon#read 4, iclass 34, count 0 2006.201.16:35:57.45#ibcon#about to read 5, iclass 34, count 0 2006.201.16:35:57.45#ibcon#read 5, iclass 34, count 0 2006.201.16:35:57.45#ibcon#about to read 6, iclass 34, count 0 2006.201.16:35:57.45#ibcon#read 6, iclass 34, count 0 2006.201.16:35:57.45#ibcon#end of sib2, iclass 34, count 0 2006.201.16:35:57.45#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:35:57.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:35:57.45#ibcon#[25=USB\r\n] 2006.201.16:35:57.45#ibcon#*before write, iclass 34, count 0 2006.201.16:35:57.45#ibcon#enter sib2, iclass 34, count 0 2006.201.16:35:57.45#ibcon#flushed, iclass 34, count 0 2006.201.16:35:57.45#ibcon#about to write, iclass 34, count 0 2006.201.16:35:57.45#ibcon#wrote, iclass 34, count 0 2006.201.16:35:57.45#ibcon#about to read 3, iclass 34, count 0 2006.201.16:35:57.48#ibcon#read 3, iclass 34, count 0 2006.201.16:35:57.48#ibcon#about to read 4, iclass 34, count 0 2006.201.16:35:57.48#ibcon#read 4, iclass 34, count 0 2006.201.16:35:57.48#ibcon#about to read 5, iclass 34, count 0 2006.201.16:35:57.48#ibcon#read 5, iclass 34, count 0 2006.201.16:35:57.48#ibcon#about to read 6, iclass 34, count 0 2006.201.16:35:57.48#ibcon#read 6, iclass 34, count 0 2006.201.16:35:57.48#ibcon#end of sib2, iclass 34, count 0 2006.201.16:35:57.48#ibcon#*after write, iclass 34, count 0 2006.201.16:35:57.48#ibcon#*before return 0, iclass 34, count 0 2006.201.16:35:57.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:35:57.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:35:57.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:35:57.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:35:57.48$vck44/valo=3,564.99 2006.201.16:35:57.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.16:35:57.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.16:35:57.48#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:57.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:35:57.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:35:57.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:35:57.48#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:35:57.48#ibcon#first serial, iclass 36, count 0 2006.201.16:35:57.48#ibcon#enter sib2, iclass 36, count 0 2006.201.16:35:57.48#ibcon#flushed, iclass 36, count 0 2006.201.16:35:57.48#ibcon#about to write, iclass 36, count 0 2006.201.16:35:57.48#ibcon#wrote, iclass 36, count 0 2006.201.16:35:57.48#ibcon#about to read 3, iclass 36, count 0 2006.201.16:35:57.50#ibcon#read 3, iclass 36, count 0 2006.201.16:35:57.50#ibcon#about to read 4, iclass 36, count 0 2006.201.16:35:57.50#ibcon#read 4, iclass 36, count 0 2006.201.16:35:57.50#ibcon#about to read 5, iclass 36, count 0 2006.201.16:35:57.50#ibcon#read 5, iclass 36, count 0 2006.201.16:35:57.50#ibcon#about to read 6, iclass 36, count 0 2006.201.16:35:57.50#ibcon#read 6, iclass 36, count 0 2006.201.16:35:57.50#ibcon#end of sib2, iclass 36, count 0 2006.201.16:35:57.50#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:35:57.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:35:57.50#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:35:57.50#ibcon#*before write, iclass 36, count 0 2006.201.16:35:57.50#ibcon#enter sib2, iclass 36, count 0 2006.201.16:35:57.50#ibcon#flushed, iclass 36, count 0 2006.201.16:35:57.50#ibcon#about to write, iclass 36, count 0 2006.201.16:35:57.50#ibcon#wrote, iclass 36, count 0 2006.201.16:35:57.50#ibcon#about to read 3, iclass 36, count 0 2006.201.16:35:57.55#ibcon#read 3, iclass 36, count 0 2006.201.16:35:57.55#ibcon#about to read 4, iclass 36, count 0 2006.201.16:35:57.55#ibcon#read 4, iclass 36, count 0 2006.201.16:35:57.55#ibcon#about to read 5, iclass 36, count 0 2006.201.16:35:57.55#ibcon#read 5, iclass 36, count 0 2006.201.16:35:57.55#ibcon#about to read 6, iclass 36, count 0 2006.201.16:35:57.55#ibcon#read 6, iclass 36, count 0 2006.201.16:35:57.55#ibcon#end of sib2, iclass 36, count 0 2006.201.16:35:57.55#ibcon#*after write, iclass 36, count 0 2006.201.16:35:57.55#ibcon#*before return 0, iclass 36, count 0 2006.201.16:35:57.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:35:57.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:35:57.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:35:57.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:35:57.55$vck44/va=3,8 2006.201.16:35:57.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.16:35:57.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.16:35:57.55#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:57.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:35:57.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:35:57.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:35:57.60#ibcon#enter wrdev, iclass 38, count 2 2006.201.16:35:57.60#ibcon#first serial, iclass 38, count 2 2006.201.16:35:57.60#ibcon#enter sib2, iclass 38, count 2 2006.201.16:35:57.60#ibcon#flushed, iclass 38, count 2 2006.201.16:35:57.60#ibcon#about to write, iclass 38, count 2 2006.201.16:35:57.60#ibcon#wrote, iclass 38, count 2 2006.201.16:35:57.60#ibcon#about to read 3, iclass 38, count 2 2006.201.16:35:57.62#ibcon#read 3, iclass 38, count 2 2006.201.16:35:57.62#ibcon#about to read 4, iclass 38, count 2 2006.201.16:35:57.62#ibcon#read 4, iclass 38, count 2 2006.201.16:35:57.62#ibcon#about to read 5, iclass 38, count 2 2006.201.16:35:57.62#ibcon#read 5, iclass 38, count 2 2006.201.16:35:57.62#ibcon#about to read 6, iclass 38, count 2 2006.201.16:35:57.62#ibcon#read 6, iclass 38, count 2 2006.201.16:35:57.62#ibcon#end of sib2, iclass 38, count 2 2006.201.16:35:57.62#ibcon#*mode == 0, iclass 38, count 2 2006.201.16:35:57.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.16:35:57.62#ibcon#[25=AT03-08\r\n] 2006.201.16:35:57.62#ibcon#*before write, iclass 38, count 2 2006.201.16:35:57.62#ibcon#enter sib2, iclass 38, count 2 2006.201.16:35:57.62#ibcon#flushed, iclass 38, count 2 2006.201.16:35:57.62#ibcon#about to write, iclass 38, count 2 2006.201.16:35:57.62#ibcon#wrote, iclass 38, count 2 2006.201.16:35:57.62#ibcon#about to read 3, iclass 38, count 2 2006.201.16:35:57.65#ibcon#read 3, iclass 38, count 2 2006.201.16:35:57.65#ibcon#about to read 4, iclass 38, count 2 2006.201.16:35:57.65#ibcon#read 4, iclass 38, count 2 2006.201.16:35:57.65#ibcon#about to read 5, iclass 38, count 2 2006.201.16:35:57.65#ibcon#read 5, iclass 38, count 2 2006.201.16:35:57.65#ibcon#about to read 6, iclass 38, count 2 2006.201.16:35:57.65#ibcon#read 6, iclass 38, count 2 2006.201.16:35:57.65#ibcon#end of sib2, iclass 38, count 2 2006.201.16:35:57.65#ibcon#*after write, iclass 38, count 2 2006.201.16:35:57.65#ibcon#*before return 0, iclass 38, count 2 2006.201.16:35:57.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:35:57.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:35:57.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.16:35:57.65#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:57.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:35:57.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:35:57.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:35:57.77#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:35:57.77#ibcon#first serial, iclass 38, count 0 2006.201.16:35:57.77#ibcon#enter sib2, iclass 38, count 0 2006.201.16:35:57.77#ibcon#flushed, iclass 38, count 0 2006.201.16:35:57.77#ibcon#about to write, iclass 38, count 0 2006.201.16:35:57.77#ibcon#wrote, iclass 38, count 0 2006.201.16:35:57.77#ibcon#about to read 3, iclass 38, count 0 2006.201.16:35:57.79#ibcon#read 3, iclass 38, count 0 2006.201.16:35:57.79#ibcon#about to read 4, iclass 38, count 0 2006.201.16:35:57.79#ibcon#read 4, iclass 38, count 0 2006.201.16:35:57.79#ibcon#about to read 5, iclass 38, count 0 2006.201.16:35:57.79#ibcon#read 5, iclass 38, count 0 2006.201.16:35:57.79#ibcon#about to read 6, iclass 38, count 0 2006.201.16:35:57.79#ibcon#read 6, iclass 38, count 0 2006.201.16:35:57.79#ibcon#end of sib2, iclass 38, count 0 2006.201.16:35:57.79#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:35:57.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:35:57.79#ibcon#[25=USB\r\n] 2006.201.16:35:57.79#ibcon#*before write, iclass 38, count 0 2006.201.16:35:57.79#ibcon#enter sib2, iclass 38, count 0 2006.201.16:35:57.79#ibcon#flushed, iclass 38, count 0 2006.201.16:35:57.79#ibcon#about to write, iclass 38, count 0 2006.201.16:35:57.79#ibcon#wrote, iclass 38, count 0 2006.201.16:35:57.79#ibcon#about to read 3, iclass 38, count 0 2006.201.16:35:57.82#ibcon#read 3, iclass 38, count 0 2006.201.16:35:57.82#ibcon#about to read 4, iclass 38, count 0 2006.201.16:35:57.82#ibcon#read 4, iclass 38, count 0 2006.201.16:35:57.82#ibcon#about to read 5, iclass 38, count 0 2006.201.16:35:57.82#ibcon#read 5, iclass 38, count 0 2006.201.16:35:57.82#ibcon#about to read 6, iclass 38, count 0 2006.201.16:35:57.82#ibcon#read 6, iclass 38, count 0 2006.201.16:35:57.82#ibcon#end of sib2, iclass 38, count 0 2006.201.16:35:57.82#ibcon#*after write, iclass 38, count 0 2006.201.16:35:57.82#ibcon#*before return 0, iclass 38, count 0 2006.201.16:35:57.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:35:57.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:35:57.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:35:57.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:35:57.82$vck44/valo=4,624.99 2006.201.16:35:57.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.16:35:57.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.16:35:57.82#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:57.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:35:57.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:35:57.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:35:57.82#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:35:57.82#ibcon#first serial, iclass 40, count 0 2006.201.16:35:57.82#ibcon#enter sib2, iclass 40, count 0 2006.201.16:35:57.82#ibcon#flushed, iclass 40, count 0 2006.201.16:35:57.82#ibcon#about to write, iclass 40, count 0 2006.201.16:35:57.82#ibcon#wrote, iclass 40, count 0 2006.201.16:35:57.82#ibcon#about to read 3, iclass 40, count 0 2006.201.16:35:57.84#ibcon#read 3, iclass 40, count 0 2006.201.16:35:57.84#ibcon#about to read 4, iclass 40, count 0 2006.201.16:35:57.84#ibcon#read 4, iclass 40, count 0 2006.201.16:35:57.84#ibcon#about to read 5, iclass 40, count 0 2006.201.16:35:57.84#ibcon#read 5, iclass 40, count 0 2006.201.16:35:57.84#ibcon#about to read 6, iclass 40, count 0 2006.201.16:35:57.84#ibcon#read 6, iclass 40, count 0 2006.201.16:35:57.84#ibcon#end of sib2, iclass 40, count 0 2006.201.16:35:57.84#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:35:57.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:35:57.84#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:35:57.84#ibcon#*before write, iclass 40, count 0 2006.201.16:35:57.84#ibcon#enter sib2, iclass 40, count 0 2006.201.16:35:57.84#ibcon#flushed, iclass 40, count 0 2006.201.16:35:57.84#ibcon#about to write, iclass 40, count 0 2006.201.16:35:57.84#ibcon#wrote, iclass 40, count 0 2006.201.16:35:57.84#ibcon#about to read 3, iclass 40, count 0 2006.201.16:35:57.89#ibcon#read 3, iclass 40, count 0 2006.201.16:35:57.89#ibcon#about to read 4, iclass 40, count 0 2006.201.16:35:57.89#ibcon#read 4, iclass 40, count 0 2006.201.16:35:57.89#ibcon#about to read 5, iclass 40, count 0 2006.201.16:35:57.89#ibcon#read 5, iclass 40, count 0 2006.201.16:35:57.89#ibcon#about to read 6, iclass 40, count 0 2006.201.16:35:57.89#ibcon#read 6, iclass 40, count 0 2006.201.16:35:57.89#ibcon#end of sib2, iclass 40, count 0 2006.201.16:35:57.89#ibcon#*after write, iclass 40, count 0 2006.201.16:35:57.89#ibcon#*before return 0, iclass 40, count 0 2006.201.16:35:57.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:35:57.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:35:57.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:35:57.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:35:57.89$vck44/va=4,7 2006.201.16:35:57.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.16:35:57.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.16:35:57.89#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:57.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:35:57.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:35:57.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:35:57.94#ibcon#enter wrdev, iclass 4, count 2 2006.201.16:35:57.94#ibcon#first serial, iclass 4, count 2 2006.201.16:35:57.94#ibcon#enter sib2, iclass 4, count 2 2006.201.16:35:57.94#ibcon#flushed, iclass 4, count 2 2006.201.16:35:57.94#ibcon#about to write, iclass 4, count 2 2006.201.16:35:57.94#ibcon#wrote, iclass 4, count 2 2006.201.16:35:57.94#ibcon#about to read 3, iclass 4, count 2 2006.201.16:35:57.96#ibcon#read 3, iclass 4, count 2 2006.201.16:35:57.96#ibcon#about to read 4, iclass 4, count 2 2006.201.16:35:57.96#ibcon#read 4, iclass 4, count 2 2006.201.16:35:57.96#ibcon#about to read 5, iclass 4, count 2 2006.201.16:35:57.96#ibcon#read 5, iclass 4, count 2 2006.201.16:35:57.96#ibcon#about to read 6, iclass 4, count 2 2006.201.16:35:57.96#ibcon#read 6, iclass 4, count 2 2006.201.16:35:57.96#ibcon#end of sib2, iclass 4, count 2 2006.201.16:35:57.96#ibcon#*mode == 0, iclass 4, count 2 2006.201.16:35:57.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.16:35:57.96#ibcon#[25=AT04-07\r\n] 2006.201.16:35:57.96#ibcon#*before write, iclass 4, count 2 2006.201.16:35:57.96#ibcon#enter sib2, iclass 4, count 2 2006.201.16:35:57.96#ibcon#flushed, iclass 4, count 2 2006.201.16:35:57.96#ibcon#about to write, iclass 4, count 2 2006.201.16:35:57.96#ibcon#wrote, iclass 4, count 2 2006.201.16:35:57.96#ibcon#about to read 3, iclass 4, count 2 2006.201.16:35:57.99#ibcon#read 3, iclass 4, count 2 2006.201.16:35:57.99#ibcon#about to read 4, iclass 4, count 2 2006.201.16:35:57.99#ibcon#read 4, iclass 4, count 2 2006.201.16:35:57.99#ibcon#about to read 5, iclass 4, count 2 2006.201.16:35:57.99#ibcon#read 5, iclass 4, count 2 2006.201.16:35:57.99#ibcon#about to read 6, iclass 4, count 2 2006.201.16:35:57.99#ibcon#read 6, iclass 4, count 2 2006.201.16:35:57.99#ibcon#end of sib2, iclass 4, count 2 2006.201.16:35:57.99#ibcon#*after write, iclass 4, count 2 2006.201.16:35:57.99#ibcon#*before return 0, iclass 4, count 2 2006.201.16:35:57.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:35:57.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:35:57.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.16:35:57.99#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:57.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:35:58.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:35:58.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:35:58.11#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:35:58.11#ibcon#first serial, iclass 4, count 0 2006.201.16:35:58.11#ibcon#enter sib2, iclass 4, count 0 2006.201.16:35:58.11#ibcon#flushed, iclass 4, count 0 2006.201.16:35:58.11#ibcon#about to write, iclass 4, count 0 2006.201.16:35:58.11#ibcon#wrote, iclass 4, count 0 2006.201.16:35:58.11#ibcon#about to read 3, iclass 4, count 0 2006.201.16:35:58.13#ibcon#read 3, iclass 4, count 0 2006.201.16:35:58.13#ibcon#about to read 4, iclass 4, count 0 2006.201.16:35:58.13#ibcon#read 4, iclass 4, count 0 2006.201.16:35:58.13#ibcon#about to read 5, iclass 4, count 0 2006.201.16:35:58.13#ibcon#read 5, iclass 4, count 0 2006.201.16:35:58.13#ibcon#about to read 6, iclass 4, count 0 2006.201.16:35:58.13#ibcon#read 6, iclass 4, count 0 2006.201.16:35:58.13#ibcon#end of sib2, iclass 4, count 0 2006.201.16:35:58.13#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:35:58.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:35:58.13#ibcon#[25=USB\r\n] 2006.201.16:35:58.13#ibcon#*before write, iclass 4, count 0 2006.201.16:35:58.13#ibcon#enter sib2, iclass 4, count 0 2006.201.16:35:58.13#ibcon#flushed, iclass 4, count 0 2006.201.16:35:58.13#ibcon#about to write, iclass 4, count 0 2006.201.16:35:58.13#ibcon#wrote, iclass 4, count 0 2006.201.16:35:58.13#ibcon#about to read 3, iclass 4, count 0 2006.201.16:35:58.16#ibcon#read 3, iclass 4, count 0 2006.201.16:35:58.16#ibcon#about to read 4, iclass 4, count 0 2006.201.16:35:58.16#ibcon#read 4, iclass 4, count 0 2006.201.16:35:58.16#ibcon#about to read 5, iclass 4, count 0 2006.201.16:35:58.16#ibcon#read 5, iclass 4, count 0 2006.201.16:35:58.16#ibcon#about to read 6, iclass 4, count 0 2006.201.16:35:58.16#ibcon#read 6, iclass 4, count 0 2006.201.16:35:58.16#ibcon#end of sib2, iclass 4, count 0 2006.201.16:35:58.16#ibcon#*after write, iclass 4, count 0 2006.201.16:35:58.16#ibcon#*before return 0, iclass 4, count 0 2006.201.16:35:58.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:35:58.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:35:58.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:35:58.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:35:58.16$vck44/valo=5,734.99 2006.201.16:35:58.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.16:35:58.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.16:35:58.16#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:58.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:35:58.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:35:58.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:35:58.16#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:35:58.16#ibcon#first serial, iclass 6, count 0 2006.201.16:35:58.16#ibcon#enter sib2, iclass 6, count 0 2006.201.16:35:58.16#ibcon#flushed, iclass 6, count 0 2006.201.16:35:58.16#ibcon#about to write, iclass 6, count 0 2006.201.16:35:58.16#ibcon#wrote, iclass 6, count 0 2006.201.16:35:58.16#ibcon#about to read 3, iclass 6, count 0 2006.201.16:35:58.18#ibcon#read 3, iclass 6, count 0 2006.201.16:35:58.18#ibcon#about to read 4, iclass 6, count 0 2006.201.16:35:58.18#ibcon#read 4, iclass 6, count 0 2006.201.16:35:58.18#ibcon#about to read 5, iclass 6, count 0 2006.201.16:35:58.18#ibcon#read 5, iclass 6, count 0 2006.201.16:35:58.18#ibcon#about to read 6, iclass 6, count 0 2006.201.16:35:58.18#ibcon#read 6, iclass 6, count 0 2006.201.16:35:58.18#ibcon#end of sib2, iclass 6, count 0 2006.201.16:35:58.18#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:35:58.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:35:58.18#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:35:58.18#ibcon#*before write, iclass 6, count 0 2006.201.16:35:58.18#ibcon#enter sib2, iclass 6, count 0 2006.201.16:35:58.18#ibcon#flushed, iclass 6, count 0 2006.201.16:35:58.18#ibcon#about to write, iclass 6, count 0 2006.201.16:35:58.18#ibcon#wrote, iclass 6, count 0 2006.201.16:35:58.18#ibcon#about to read 3, iclass 6, count 0 2006.201.16:35:58.22#ibcon#read 3, iclass 6, count 0 2006.201.16:35:58.22#ibcon#about to read 4, iclass 6, count 0 2006.201.16:35:58.22#ibcon#read 4, iclass 6, count 0 2006.201.16:35:58.22#ibcon#about to read 5, iclass 6, count 0 2006.201.16:35:58.22#ibcon#read 5, iclass 6, count 0 2006.201.16:35:58.22#ibcon#about to read 6, iclass 6, count 0 2006.201.16:35:58.22#ibcon#read 6, iclass 6, count 0 2006.201.16:35:58.22#ibcon#end of sib2, iclass 6, count 0 2006.201.16:35:58.22#ibcon#*after write, iclass 6, count 0 2006.201.16:35:58.22#ibcon#*before return 0, iclass 6, count 0 2006.201.16:35:58.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:35:58.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:35:58.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:35:58.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:35:58.22$vck44/va=5,4 2006.201.16:35:58.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.16:35:58.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.16:35:58.22#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:58.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:35:58.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:35:58.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:35:58.28#ibcon#enter wrdev, iclass 10, count 2 2006.201.16:35:58.28#ibcon#first serial, iclass 10, count 2 2006.201.16:35:58.28#ibcon#enter sib2, iclass 10, count 2 2006.201.16:35:58.28#ibcon#flushed, iclass 10, count 2 2006.201.16:35:58.28#ibcon#about to write, iclass 10, count 2 2006.201.16:35:58.28#ibcon#wrote, iclass 10, count 2 2006.201.16:35:58.28#ibcon#about to read 3, iclass 10, count 2 2006.201.16:35:58.30#ibcon#read 3, iclass 10, count 2 2006.201.16:35:58.30#ibcon#about to read 4, iclass 10, count 2 2006.201.16:35:58.30#ibcon#read 4, iclass 10, count 2 2006.201.16:35:58.30#ibcon#about to read 5, iclass 10, count 2 2006.201.16:35:58.30#ibcon#read 5, iclass 10, count 2 2006.201.16:35:58.30#ibcon#about to read 6, iclass 10, count 2 2006.201.16:35:58.30#ibcon#read 6, iclass 10, count 2 2006.201.16:35:58.30#ibcon#end of sib2, iclass 10, count 2 2006.201.16:35:58.30#ibcon#*mode == 0, iclass 10, count 2 2006.201.16:35:58.30#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.16:35:58.30#ibcon#[25=AT05-04\r\n] 2006.201.16:35:58.30#ibcon#*before write, iclass 10, count 2 2006.201.16:35:58.30#ibcon#enter sib2, iclass 10, count 2 2006.201.16:35:58.30#ibcon#flushed, iclass 10, count 2 2006.201.16:35:58.30#ibcon#about to write, iclass 10, count 2 2006.201.16:35:58.30#ibcon#wrote, iclass 10, count 2 2006.201.16:35:58.30#ibcon#about to read 3, iclass 10, count 2 2006.201.16:35:58.33#ibcon#read 3, iclass 10, count 2 2006.201.16:35:58.33#ibcon#about to read 4, iclass 10, count 2 2006.201.16:35:58.33#ibcon#read 4, iclass 10, count 2 2006.201.16:35:58.33#ibcon#about to read 5, iclass 10, count 2 2006.201.16:35:58.33#ibcon#read 5, iclass 10, count 2 2006.201.16:35:58.33#ibcon#about to read 6, iclass 10, count 2 2006.201.16:35:58.33#ibcon#read 6, iclass 10, count 2 2006.201.16:35:58.33#ibcon#end of sib2, iclass 10, count 2 2006.201.16:35:58.33#ibcon#*after write, iclass 10, count 2 2006.201.16:35:58.33#ibcon#*before return 0, iclass 10, count 2 2006.201.16:35:58.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:35:58.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:35:58.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.16:35:58.33#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:58.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:35:58.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:35:58.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:35:58.45#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:35:58.45#ibcon#first serial, iclass 10, count 0 2006.201.16:35:58.45#ibcon#enter sib2, iclass 10, count 0 2006.201.16:35:58.45#ibcon#flushed, iclass 10, count 0 2006.201.16:35:58.45#ibcon#about to write, iclass 10, count 0 2006.201.16:35:58.45#ibcon#wrote, iclass 10, count 0 2006.201.16:35:58.45#ibcon#about to read 3, iclass 10, count 0 2006.201.16:35:58.47#ibcon#read 3, iclass 10, count 0 2006.201.16:35:58.47#ibcon#about to read 4, iclass 10, count 0 2006.201.16:35:58.47#ibcon#read 4, iclass 10, count 0 2006.201.16:35:58.47#ibcon#about to read 5, iclass 10, count 0 2006.201.16:35:58.47#ibcon#read 5, iclass 10, count 0 2006.201.16:35:58.47#ibcon#about to read 6, iclass 10, count 0 2006.201.16:35:58.47#ibcon#read 6, iclass 10, count 0 2006.201.16:35:58.47#ibcon#end of sib2, iclass 10, count 0 2006.201.16:35:58.47#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:35:58.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:35:58.47#ibcon#[25=USB\r\n] 2006.201.16:35:58.47#ibcon#*before write, iclass 10, count 0 2006.201.16:35:58.47#ibcon#enter sib2, iclass 10, count 0 2006.201.16:35:58.47#ibcon#flushed, iclass 10, count 0 2006.201.16:35:58.47#ibcon#about to write, iclass 10, count 0 2006.201.16:35:58.47#ibcon#wrote, iclass 10, count 0 2006.201.16:35:58.47#ibcon#about to read 3, iclass 10, count 0 2006.201.16:35:58.50#ibcon#read 3, iclass 10, count 0 2006.201.16:35:58.50#ibcon#about to read 4, iclass 10, count 0 2006.201.16:35:58.50#ibcon#read 4, iclass 10, count 0 2006.201.16:35:58.50#ibcon#about to read 5, iclass 10, count 0 2006.201.16:35:58.50#ibcon#read 5, iclass 10, count 0 2006.201.16:35:58.50#ibcon#about to read 6, iclass 10, count 0 2006.201.16:35:58.50#ibcon#read 6, iclass 10, count 0 2006.201.16:35:58.50#ibcon#end of sib2, iclass 10, count 0 2006.201.16:35:58.50#ibcon#*after write, iclass 10, count 0 2006.201.16:35:58.50#ibcon#*before return 0, iclass 10, count 0 2006.201.16:35:58.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:35:58.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:35:58.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:35:58.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:35:58.50$vck44/valo=6,814.99 2006.201.16:35:58.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.16:35:58.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.16:35:58.50#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:58.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:35:58.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:35:58.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:35:58.50#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:35:58.50#ibcon#first serial, iclass 12, count 0 2006.201.16:35:58.50#ibcon#enter sib2, iclass 12, count 0 2006.201.16:35:58.50#ibcon#flushed, iclass 12, count 0 2006.201.16:35:58.50#ibcon#about to write, iclass 12, count 0 2006.201.16:35:58.50#ibcon#wrote, iclass 12, count 0 2006.201.16:35:58.50#ibcon#about to read 3, iclass 12, count 0 2006.201.16:35:58.52#ibcon#read 3, iclass 12, count 0 2006.201.16:35:58.52#ibcon#about to read 4, iclass 12, count 0 2006.201.16:35:58.52#ibcon#read 4, iclass 12, count 0 2006.201.16:35:58.52#ibcon#about to read 5, iclass 12, count 0 2006.201.16:35:58.52#ibcon#read 5, iclass 12, count 0 2006.201.16:35:58.52#ibcon#about to read 6, iclass 12, count 0 2006.201.16:35:58.52#ibcon#read 6, iclass 12, count 0 2006.201.16:35:58.52#ibcon#end of sib2, iclass 12, count 0 2006.201.16:35:58.52#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:35:58.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:35:58.52#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:35:58.52#ibcon#*before write, iclass 12, count 0 2006.201.16:35:58.52#ibcon#enter sib2, iclass 12, count 0 2006.201.16:35:58.52#ibcon#flushed, iclass 12, count 0 2006.201.16:35:58.52#ibcon#about to write, iclass 12, count 0 2006.201.16:35:58.52#ibcon#wrote, iclass 12, count 0 2006.201.16:35:58.52#ibcon#about to read 3, iclass 12, count 0 2006.201.16:35:58.56#ibcon#read 3, iclass 12, count 0 2006.201.16:35:58.56#ibcon#about to read 4, iclass 12, count 0 2006.201.16:35:58.56#ibcon#read 4, iclass 12, count 0 2006.201.16:35:58.56#ibcon#about to read 5, iclass 12, count 0 2006.201.16:35:58.56#ibcon#read 5, iclass 12, count 0 2006.201.16:35:58.56#ibcon#about to read 6, iclass 12, count 0 2006.201.16:35:58.56#ibcon#read 6, iclass 12, count 0 2006.201.16:35:58.56#ibcon#end of sib2, iclass 12, count 0 2006.201.16:35:58.56#ibcon#*after write, iclass 12, count 0 2006.201.16:35:58.56#ibcon#*before return 0, iclass 12, count 0 2006.201.16:35:58.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:35:58.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:35:58.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:35:58.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:35:58.56$vck44/va=6,5 2006.201.16:35:58.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.16:35:58.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.16:35:58.56#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:58.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:35:58.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:35:58.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:35:58.62#ibcon#enter wrdev, iclass 14, count 2 2006.201.16:35:58.62#ibcon#first serial, iclass 14, count 2 2006.201.16:35:58.62#ibcon#enter sib2, iclass 14, count 2 2006.201.16:35:58.62#ibcon#flushed, iclass 14, count 2 2006.201.16:35:58.62#ibcon#about to write, iclass 14, count 2 2006.201.16:35:58.62#ibcon#wrote, iclass 14, count 2 2006.201.16:35:58.62#ibcon#about to read 3, iclass 14, count 2 2006.201.16:35:58.64#ibcon#read 3, iclass 14, count 2 2006.201.16:35:58.64#ibcon#about to read 4, iclass 14, count 2 2006.201.16:35:58.64#ibcon#read 4, iclass 14, count 2 2006.201.16:35:58.64#ibcon#about to read 5, iclass 14, count 2 2006.201.16:35:58.64#ibcon#read 5, iclass 14, count 2 2006.201.16:35:58.64#ibcon#about to read 6, iclass 14, count 2 2006.201.16:35:58.64#ibcon#read 6, iclass 14, count 2 2006.201.16:35:58.64#ibcon#end of sib2, iclass 14, count 2 2006.201.16:35:58.64#ibcon#*mode == 0, iclass 14, count 2 2006.201.16:35:58.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.16:35:58.64#ibcon#[25=AT06-05\r\n] 2006.201.16:35:58.64#ibcon#*before write, iclass 14, count 2 2006.201.16:35:58.64#ibcon#enter sib2, iclass 14, count 2 2006.201.16:35:58.64#ibcon#flushed, iclass 14, count 2 2006.201.16:35:58.64#ibcon#about to write, iclass 14, count 2 2006.201.16:35:58.64#ibcon#wrote, iclass 14, count 2 2006.201.16:35:58.64#ibcon#about to read 3, iclass 14, count 2 2006.201.16:35:58.67#ibcon#read 3, iclass 14, count 2 2006.201.16:35:58.67#ibcon#about to read 4, iclass 14, count 2 2006.201.16:35:58.67#ibcon#read 4, iclass 14, count 2 2006.201.16:35:58.67#ibcon#about to read 5, iclass 14, count 2 2006.201.16:35:58.67#ibcon#read 5, iclass 14, count 2 2006.201.16:35:58.67#ibcon#about to read 6, iclass 14, count 2 2006.201.16:35:58.67#ibcon#read 6, iclass 14, count 2 2006.201.16:35:58.67#ibcon#end of sib2, iclass 14, count 2 2006.201.16:35:58.67#ibcon#*after write, iclass 14, count 2 2006.201.16:35:58.67#ibcon#*before return 0, iclass 14, count 2 2006.201.16:35:58.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:35:58.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:35:58.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.16:35:58.67#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:58.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:35:58.76#abcon#<5=/04 0.9 1.3 20.821001002.6\r\n> 2006.201.16:35:58.78#abcon#{5=INTERFACE CLEAR} 2006.201.16:35:58.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:35:58.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:35:58.79#ibcon#enter wrdev, iclass 14, count 0 2006.201.16:35:58.79#ibcon#first serial, iclass 14, count 0 2006.201.16:35:58.79#ibcon#enter sib2, iclass 14, count 0 2006.201.16:35:58.79#ibcon#flushed, iclass 14, count 0 2006.201.16:35:58.79#ibcon#about to write, iclass 14, count 0 2006.201.16:35:58.79#ibcon#wrote, iclass 14, count 0 2006.201.16:35:58.79#ibcon#about to read 3, iclass 14, count 0 2006.201.16:35:58.81#ibcon#read 3, iclass 14, count 0 2006.201.16:35:58.81#ibcon#about to read 4, iclass 14, count 0 2006.201.16:35:58.81#ibcon#read 4, iclass 14, count 0 2006.201.16:35:58.81#ibcon#about to read 5, iclass 14, count 0 2006.201.16:35:58.81#ibcon#read 5, iclass 14, count 0 2006.201.16:35:58.81#ibcon#about to read 6, iclass 14, count 0 2006.201.16:35:58.81#ibcon#read 6, iclass 14, count 0 2006.201.16:35:58.81#ibcon#end of sib2, iclass 14, count 0 2006.201.16:35:58.81#ibcon#*mode == 0, iclass 14, count 0 2006.201.16:35:58.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.16:35:58.81#ibcon#[25=USB\r\n] 2006.201.16:35:58.81#ibcon#*before write, iclass 14, count 0 2006.201.16:35:58.81#ibcon#enter sib2, iclass 14, count 0 2006.201.16:35:58.81#ibcon#flushed, iclass 14, count 0 2006.201.16:35:58.81#ibcon#about to write, iclass 14, count 0 2006.201.16:35:58.81#ibcon#wrote, iclass 14, count 0 2006.201.16:35:58.81#ibcon#about to read 3, iclass 14, count 0 2006.201.16:35:58.84#ibcon#read 3, iclass 14, count 0 2006.201.16:35:58.84#ibcon#about to read 4, iclass 14, count 0 2006.201.16:35:58.84#ibcon#read 4, iclass 14, count 0 2006.201.16:35:58.84#ibcon#about to read 5, iclass 14, count 0 2006.201.16:35:58.84#ibcon#read 5, iclass 14, count 0 2006.201.16:35:58.84#ibcon#about to read 6, iclass 14, count 0 2006.201.16:35:58.84#ibcon#read 6, iclass 14, count 0 2006.201.16:35:58.84#ibcon#end of sib2, iclass 14, count 0 2006.201.16:35:58.84#ibcon#*after write, iclass 14, count 0 2006.201.16:35:58.84#ibcon#*before return 0, iclass 14, count 0 2006.201.16:35:58.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:35:58.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:35:58.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.16:35:58.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.16:35:58.84$vck44/valo=7,864.99 2006.201.16:35:58.84#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.16:35:58.84#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.16:35:58.84#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:58.84#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:35:58.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:35:58.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:35:58.84#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:35:58.84#ibcon#first serial, iclass 20, count 0 2006.201.16:35:58.84#ibcon#enter sib2, iclass 20, count 0 2006.201.16:35:58.84#ibcon#flushed, iclass 20, count 0 2006.201.16:35:58.84#ibcon#about to write, iclass 20, count 0 2006.201.16:35:58.84#ibcon#wrote, iclass 20, count 0 2006.201.16:35:58.84#ibcon#about to read 3, iclass 20, count 0 2006.201.16:35:58.85#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:35:58.86#ibcon#read 3, iclass 20, count 0 2006.201.16:35:58.86#ibcon#about to read 4, iclass 20, count 0 2006.201.16:35:58.86#ibcon#read 4, iclass 20, count 0 2006.201.16:35:58.86#ibcon#about to read 5, iclass 20, count 0 2006.201.16:35:58.86#ibcon#read 5, iclass 20, count 0 2006.201.16:35:58.86#ibcon#about to read 6, iclass 20, count 0 2006.201.16:35:58.86#ibcon#read 6, iclass 20, count 0 2006.201.16:35:58.86#ibcon#end of sib2, iclass 20, count 0 2006.201.16:35:58.86#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:35:58.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:35:58.86#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:35:58.86#ibcon#*before write, iclass 20, count 0 2006.201.16:35:58.86#ibcon#enter sib2, iclass 20, count 0 2006.201.16:35:58.86#ibcon#flushed, iclass 20, count 0 2006.201.16:35:58.86#ibcon#about to write, iclass 20, count 0 2006.201.16:35:58.86#ibcon#wrote, iclass 20, count 0 2006.201.16:35:58.86#ibcon#about to read 3, iclass 20, count 0 2006.201.16:35:58.90#ibcon#read 3, iclass 20, count 0 2006.201.16:35:58.90#ibcon#about to read 4, iclass 20, count 0 2006.201.16:35:58.90#ibcon#read 4, iclass 20, count 0 2006.201.16:35:58.90#ibcon#about to read 5, iclass 20, count 0 2006.201.16:35:58.90#ibcon#read 5, iclass 20, count 0 2006.201.16:35:58.90#ibcon#about to read 6, iclass 20, count 0 2006.201.16:35:58.90#ibcon#read 6, iclass 20, count 0 2006.201.16:35:58.90#ibcon#end of sib2, iclass 20, count 0 2006.201.16:35:58.90#ibcon#*after write, iclass 20, count 0 2006.201.16:35:58.90#ibcon#*before return 0, iclass 20, count 0 2006.201.16:35:58.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:35:58.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:35:58.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:35:58.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:35:58.90$vck44/va=7,5 2006.201.16:35:58.90#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.16:35:58.90#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.16:35:58.90#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:58.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:35:58.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:35:58.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:35:58.96#ibcon#enter wrdev, iclass 22, count 2 2006.201.16:35:58.96#ibcon#first serial, iclass 22, count 2 2006.201.16:35:58.96#ibcon#enter sib2, iclass 22, count 2 2006.201.16:35:58.96#ibcon#flushed, iclass 22, count 2 2006.201.16:35:58.96#ibcon#about to write, iclass 22, count 2 2006.201.16:35:58.96#ibcon#wrote, iclass 22, count 2 2006.201.16:35:58.96#ibcon#about to read 3, iclass 22, count 2 2006.201.16:35:58.98#ibcon#read 3, iclass 22, count 2 2006.201.16:35:58.98#ibcon#about to read 4, iclass 22, count 2 2006.201.16:35:58.98#ibcon#read 4, iclass 22, count 2 2006.201.16:35:58.98#ibcon#about to read 5, iclass 22, count 2 2006.201.16:35:58.98#ibcon#read 5, iclass 22, count 2 2006.201.16:35:58.98#ibcon#about to read 6, iclass 22, count 2 2006.201.16:35:58.98#ibcon#read 6, iclass 22, count 2 2006.201.16:35:58.98#ibcon#end of sib2, iclass 22, count 2 2006.201.16:35:58.98#ibcon#*mode == 0, iclass 22, count 2 2006.201.16:35:58.98#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.16:35:58.98#ibcon#[25=AT07-05\r\n] 2006.201.16:35:58.98#ibcon#*before write, iclass 22, count 2 2006.201.16:35:58.98#ibcon#enter sib2, iclass 22, count 2 2006.201.16:35:58.98#ibcon#flushed, iclass 22, count 2 2006.201.16:35:58.98#ibcon#about to write, iclass 22, count 2 2006.201.16:35:58.98#ibcon#wrote, iclass 22, count 2 2006.201.16:35:58.98#ibcon#about to read 3, iclass 22, count 2 2006.201.16:35:59.01#ibcon#read 3, iclass 22, count 2 2006.201.16:35:59.01#ibcon#about to read 4, iclass 22, count 2 2006.201.16:35:59.01#ibcon#read 4, iclass 22, count 2 2006.201.16:35:59.01#ibcon#about to read 5, iclass 22, count 2 2006.201.16:35:59.01#ibcon#read 5, iclass 22, count 2 2006.201.16:35:59.01#ibcon#about to read 6, iclass 22, count 2 2006.201.16:35:59.01#ibcon#read 6, iclass 22, count 2 2006.201.16:35:59.01#ibcon#end of sib2, iclass 22, count 2 2006.201.16:35:59.01#ibcon#*after write, iclass 22, count 2 2006.201.16:35:59.01#ibcon#*before return 0, iclass 22, count 2 2006.201.16:35:59.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:35:59.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:35:59.01#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.16:35:59.01#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:59.01#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:35:59.13#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:35:59.13#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:35:59.13#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:35:59.13#ibcon#first serial, iclass 22, count 0 2006.201.16:35:59.13#ibcon#enter sib2, iclass 22, count 0 2006.201.16:35:59.13#ibcon#flushed, iclass 22, count 0 2006.201.16:35:59.13#ibcon#about to write, iclass 22, count 0 2006.201.16:35:59.13#ibcon#wrote, iclass 22, count 0 2006.201.16:35:59.13#ibcon#about to read 3, iclass 22, count 0 2006.201.16:35:59.15#ibcon#read 3, iclass 22, count 0 2006.201.16:35:59.15#ibcon#about to read 4, iclass 22, count 0 2006.201.16:35:59.15#ibcon#read 4, iclass 22, count 0 2006.201.16:35:59.15#ibcon#about to read 5, iclass 22, count 0 2006.201.16:35:59.15#ibcon#read 5, iclass 22, count 0 2006.201.16:35:59.15#ibcon#about to read 6, iclass 22, count 0 2006.201.16:35:59.15#ibcon#read 6, iclass 22, count 0 2006.201.16:35:59.15#ibcon#end of sib2, iclass 22, count 0 2006.201.16:35:59.15#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:35:59.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:35:59.15#ibcon#[25=USB\r\n] 2006.201.16:35:59.15#ibcon#*before write, iclass 22, count 0 2006.201.16:35:59.15#ibcon#enter sib2, iclass 22, count 0 2006.201.16:35:59.15#ibcon#flushed, iclass 22, count 0 2006.201.16:35:59.15#ibcon#about to write, iclass 22, count 0 2006.201.16:35:59.15#ibcon#wrote, iclass 22, count 0 2006.201.16:35:59.15#ibcon#about to read 3, iclass 22, count 0 2006.201.16:35:59.18#ibcon#read 3, iclass 22, count 0 2006.201.16:35:59.18#ibcon#about to read 4, iclass 22, count 0 2006.201.16:35:59.18#ibcon#read 4, iclass 22, count 0 2006.201.16:35:59.18#ibcon#about to read 5, iclass 22, count 0 2006.201.16:35:59.18#ibcon#read 5, iclass 22, count 0 2006.201.16:35:59.18#ibcon#about to read 6, iclass 22, count 0 2006.201.16:35:59.18#ibcon#read 6, iclass 22, count 0 2006.201.16:35:59.18#ibcon#end of sib2, iclass 22, count 0 2006.201.16:35:59.18#ibcon#*after write, iclass 22, count 0 2006.201.16:35:59.18#ibcon#*before return 0, iclass 22, count 0 2006.201.16:35:59.18#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:35:59.18#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:35:59.18#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:35:59.18#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:35:59.18$vck44/valo=8,884.99 2006.201.16:35:59.18#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.16:35:59.18#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.16:35:59.18#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:59.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:35:59.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:35:59.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:35:59.18#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:35:59.18#ibcon#first serial, iclass 24, count 0 2006.201.16:35:59.18#ibcon#enter sib2, iclass 24, count 0 2006.201.16:35:59.18#ibcon#flushed, iclass 24, count 0 2006.201.16:35:59.18#ibcon#about to write, iclass 24, count 0 2006.201.16:35:59.18#ibcon#wrote, iclass 24, count 0 2006.201.16:35:59.18#ibcon#about to read 3, iclass 24, count 0 2006.201.16:35:59.20#ibcon#read 3, iclass 24, count 0 2006.201.16:35:59.20#ibcon#about to read 4, iclass 24, count 0 2006.201.16:35:59.20#ibcon#read 4, iclass 24, count 0 2006.201.16:35:59.20#ibcon#about to read 5, iclass 24, count 0 2006.201.16:35:59.20#ibcon#read 5, iclass 24, count 0 2006.201.16:35:59.20#ibcon#about to read 6, iclass 24, count 0 2006.201.16:35:59.20#ibcon#read 6, iclass 24, count 0 2006.201.16:35:59.20#ibcon#end of sib2, iclass 24, count 0 2006.201.16:35:59.20#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:35:59.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:35:59.20#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:35:59.20#ibcon#*before write, iclass 24, count 0 2006.201.16:35:59.20#ibcon#enter sib2, iclass 24, count 0 2006.201.16:35:59.20#ibcon#flushed, iclass 24, count 0 2006.201.16:35:59.20#ibcon#about to write, iclass 24, count 0 2006.201.16:35:59.20#ibcon#wrote, iclass 24, count 0 2006.201.16:35:59.20#ibcon#about to read 3, iclass 24, count 0 2006.201.16:35:59.24#ibcon#read 3, iclass 24, count 0 2006.201.16:35:59.24#ibcon#about to read 4, iclass 24, count 0 2006.201.16:35:59.24#ibcon#read 4, iclass 24, count 0 2006.201.16:35:59.24#ibcon#about to read 5, iclass 24, count 0 2006.201.16:35:59.24#ibcon#read 5, iclass 24, count 0 2006.201.16:35:59.24#ibcon#about to read 6, iclass 24, count 0 2006.201.16:35:59.24#ibcon#read 6, iclass 24, count 0 2006.201.16:35:59.24#ibcon#end of sib2, iclass 24, count 0 2006.201.16:35:59.24#ibcon#*after write, iclass 24, count 0 2006.201.16:35:59.24#ibcon#*before return 0, iclass 24, count 0 2006.201.16:35:59.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:35:59.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:35:59.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:35:59.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:35:59.24$vck44/va=8,4 2006.201.16:35:59.24#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.16:35:59.24#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.16:35:59.24#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:59.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:35:59.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:35:59.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:35:59.30#ibcon#enter wrdev, iclass 26, count 2 2006.201.16:35:59.30#ibcon#first serial, iclass 26, count 2 2006.201.16:35:59.30#ibcon#enter sib2, iclass 26, count 2 2006.201.16:35:59.30#ibcon#flushed, iclass 26, count 2 2006.201.16:35:59.30#ibcon#about to write, iclass 26, count 2 2006.201.16:35:59.30#ibcon#wrote, iclass 26, count 2 2006.201.16:35:59.30#ibcon#about to read 3, iclass 26, count 2 2006.201.16:35:59.32#ibcon#read 3, iclass 26, count 2 2006.201.16:35:59.32#ibcon#about to read 4, iclass 26, count 2 2006.201.16:35:59.32#ibcon#read 4, iclass 26, count 2 2006.201.16:35:59.32#ibcon#about to read 5, iclass 26, count 2 2006.201.16:35:59.32#ibcon#read 5, iclass 26, count 2 2006.201.16:35:59.32#ibcon#about to read 6, iclass 26, count 2 2006.201.16:35:59.32#ibcon#read 6, iclass 26, count 2 2006.201.16:35:59.32#ibcon#end of sib2, iclass 26, count 2 2006.201.16:35:59.32#ibcon#*mode == 0, iclass 26, count 2 2006.201.16:35:59.32#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.16:35:59.32#ibcon#[25=AT08-04\r\n] 2006.201.16:35:59.32#ibcon#*before write, iclass 26, count 2 2006.201.16:35:59.32#ibcon#enter sib2, iclass 26, count 2 2006.201.16:35:59.32#ibcon#flushed, iclass 26, count 2 2006.201.16:35:59.32#ibcon#about to write, iclass 26, count 2 2006.201.16:35:59.32#ibcon#wrote, iclass 26, count 2 2006.201.16:35:59.32#ibcon#about to read 3, iclass 26, count 2 2006.201.16:35:59.35#ibcon#read 3, iclass 26, count 2 2006.201.16:35:59.35#ibcon#about to read 4, iclass 26, count 2 2006.201.16:35:59.35#ibcon#read 4, iclass 26, count 2 2006.201.16:35:59.35#ibcon#about to read 5, iclass 26, count 2 2006.201.16:35:59.35#ibcon#read 5, iclass 26, count 2 2006.201.16:35:59.35#ibcon#about to read 6, iclass 26, count 2 2006.201.16:35:59.35#ibcon#read 6, iclass 26, count 2 2006.201.16:35:59.35#ibcon#end of sib2, iclass 26, count 2 2006.201.16:35:59.35#ibcon#*after write, iclass 26, count 2 2006.201.16:35:59.35#ibcon#*before return 0, iclass 26, count 2 2006.201.16:35:59.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:35:59.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:35:59.35#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.16:35:59.35#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:59.35#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:35:59.47#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:35:59.47#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:35:59.47#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:35:59.47#ibcon#first serial, iclass 26, count 0 2006.201.16:35:59.47#ibcon#enter sib2, iclass 26, count 0 2006.201.16:35:59.47#ibcon#flushed, iclass 26, count 0 2006.201.16:35:59.47#ibcon#about to write, iclass 26, count 0 2006.201.16:35:59.47#ibcon#wrote, iclass 26, count 0 2006.201.16:35:59.47#ibcon#about to read 3, iclass 26, count 0 2006.201.16:35:59.49#ibcon#read 3, iclass 26, count 0 2006.201.16:35:59.49#ibcon#about to read 4, iclass 26, count 0 2006.201.16:35:59.49#ibcon#read 4, iclass 26, count 0 2006.201.16:35:59.49#ibcon#about to read 5, iclass 26, count 0 2006.201.16:35:59.49#ibcon#read 5, iclass 26, count 0 2006.201.16:35:59.49#ibcon#about to read 6, iclass 26, count 0 2006.201.16:35:59.49#ibcon#read 6, iclass 26, count 0 2006.201.16:35:59.49#ibcon#end of sib2, iclass 26, count 0 2006.201.16:35:59.49#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:35:59.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:35:59.49#ibcon#[25=USB\r\n] 2006.201.16:35:59.49#ibcon#*before write, iclass 26, count 0 2006.201.16:35:59.49#ibcon#enter sib2, iclass 26, count 0 2006.201.16:35:59.49#ibcon#flushed, iclass 26, count 0 2006.201.16:35:59.49#ibcon#about to write, iclass 26, count 0 2006.201.16:35:59.49#ibcon#wrote, iclass 26, count 0 2006.201.16:35:59.49#ibcon#about to read 3, iclass 26, count 0 2006.201.16:35:59.52#ibcon#read 3, iclass 26, count 0 2006.201.16:35:59.52#ibcon#about to read 4, iclass 26, count 0 2006.201.16:35:59.52#ibcon#read 4, iclass 26, count 0 2006.201.16:35:59.52#ibcon#about to read 5, iclass 26, count 0 2006.201.16:35:59.52#ibcon#read 5, iclass 26, count 0 2006.201.16:35:59.52#ibcon#about to read 6, iclass 26, count 0 2006.201.16:35:59.52#ibcon#read 6, iclass 26, count 0 2006.201.16:35:59.52#ibcon#end of sib2, iclass 26, count 0 2006.201.16:35:59.52#ibcon#*after write, iclass 26, count 0 2006.201.16:35:59.52#ibcon#*before return 0, iclass 26, count 0 2006.201.16:35:59.52#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:35:59.52#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:35:59.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:35:59.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:35:59.52$vck44/vblo=1,629.99 2006.201.16:35:59.52#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.16:35:59.52#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.16:35:59.52#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:59.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:59.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:59.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:59.52#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:35:59.52#ibcon#first serial, iclass 28, count 0 2006.201.16:35:59.52#ibcon#enter sib2, iclass 28, count 0 2006.201.16:35:59.52#ibcon#flushed, iclass 28, count 0 2006.201.16:35:59.52#ibcon#about to write, iclass 28, count 0 2006.201.16:35:59.52#ibcon#wrote, iclass 28, count 0 2006.201.16:35:59.52#ibcon#about to read 3, iclass 28, count 0 2006.201.16:35:59.54#ibcon#read 3, iclass 28, count 0 2006.201.16:35:59.54#ibcon#about to read 4, iclass 28, count 0 2006.201.16:35:59.54#ibcon#read 4, iclass 28, count 0 2006.201.16:35:59.54#ibcon#about to read 5, iclass 28, count 0 2006.201.16:35:59.54#ibcon#read 5, iclass 28, count 0 2006.201.16:35:59.54#ibcon#about to read 6, iclass 28, count 0 2006.201.16:35:59.54#ibcon#read 6, iclass 28, count 0 2006.201.16:35:59.54#ibcon#end of sib2, iclass 28, count 0 2006.201.16:35:59.54#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:35:59.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:35:59.54#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:35:59.54#ibcon#*before write, iclass 28, count 0 2006.201.16:35:59.54#ibcon#enter sib2, iclass 28, count 0 2006.201.16:35:59.54#ibcon#flushed, iclass 28, count 0 2006.201.16:35:59.54#ibcon#about to write, iclass 28, count 0 2006.201.16:35:59.54#ibcon#wrote, iclass 28, count 0 2006.201.16:35:59.54#ibcon#about to read 3, iclass 28, count 0 2006.201.16:35:59.59#ibcon#read 3, iclass 28, count 0 2006.201.16:35:59.59#ibcon#about to read 4, iclass 28, count 0 2006.201.16:35:59.59#ibcon#read 4, iclass 28, count 0 2006.201.16:35:59.59#ibcon#about to read 5, iclass 28, count 0 2006.201.16:35:59.59#ibcon#read 5, iclass 28, count 0 2006.201.16:35:59.59#ibcon#about to read 6, iclass 28, count 0 2006.201.16:35:59.59#ibcon#read 6, iclass 28, count 0 2006.201.16:35:59.59#ibcon#end of sib2, iclass 28, count 0 2006.201.16:35:59.59#ibcon#*after write, iclass 28, count 0 2006.201.16:35:59.59#ibcon#*before return 0, iclass 28, count 0 2006.201.16:35:59.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:59.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:35:59.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:35:59.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:35:59.59$vck44/vb=1,4 2006.201.16:35:59.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.16:35:59.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.16:35:59.59#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:59.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:59.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:59.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:59.59#ibcon#enter wrdev, iclass 30, count 2 2006.201.16:35:59.59#ibcon#first serial, iclass 30, count 2 2006.201.16:35:59.59#ibcon#enter sib2, iclass 30, count 2 2006.201.16:35:59.59#ibcon#flushed, iclass 30, count 2 2006.201.16:35:59.59#ibcon#about to write, iclass 30, count 2 2006.201.16:35:59.59#ibcon#wrote, iclass 30, count 2 2006.201.16:35:59.59#ibcon#about to read 3, iclass 30, count 2 2006.201.16:35:59.61#ibcon#read 3, iclass 30, count 2 2006.201.16:35:59.61#ibcon#about to read 4, iclass 30, count 2 2006.201.16:35:59.61#ibcon#read 4, iclass 30, count 2 2006.201.16:35:59.61#ibcon#about to read 5, iclass 30, count 2 2006.201.16:35:59.61#ibcon#read 5, iclass 30, count 2 2006.201.16:35:59.61#ibcon#about to read 6, iclass 30, count 2 2006.201.16:35:59.61#ibcon#read 6, iclass 30, count 2 2006.201.16:35:59.61#ibcon#end of sib2, iclass 30, count 2 2006.201.16:35:59.61#ibcon#*mode == 0, iclass 30, count 2 2006.201.16:35:59.61#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.16:35:59.61#ibcon#[27=AT01-04\r\n] 2006.201.16:35:59.61#ibcon#*before write, iclass 30, count 2 2006.201.16:35:59.61#ibcon#enter sib2, iclass 30, count 2 2006.201.16:35:59.61#ibcon#flushed, iclass 30, count 2 2006.201.16:35:59.61#ibcon#about to write, iclass 30, count 2 2006.201.16:35:59.61#ibcon#wrote, iclass 30, count 2 2006.201.16:35:59.61#ibcon#about to read 3, iclass 30, count 2 2006.201.16:35:59.64#ibcon#read 3, iclass 30, count 2 2006.201.16:35:59.64#ibcon#about to read 4, iclass 30, count 2 2006.201.16:35:59.64#ibcon#read 4, iclass 30, count 2 2006.201.16:35:59.64#ibcon#about to read 5, iclass 30, count 2 2006.201.16:35:59.64#ibcon#read 5, iclass 30, count 2 2006.201.16:35:59.64#ibcon#about to read 6, iclass 30, count 2 2006.201.16:35:59.64#ibcon#read 6, iclass 30, count 2 2006.201.16:35:59.64#ibcon#end of sib2, iclass 30, count 2 2006.201.16:35:59.64#ibcon#*after write, iclass 30, count 2 2006.201.16:35:59.64#ibcon#*before return 0, iclass 30, count 2 2006.201.16:35:59.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:59.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:35:59.64#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.16:35:59.64#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:59.64#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:59.76#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:59.76#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:59.76#ibcon#enter wrdev, iclass 30, count 0 2006.201.16:35:59.76#ibcon#first serial, iclass 30, count 0 2006.201.16:35:59.76#ibcon#enter sib2, iclass 30, count 0 2006.201.16:35:59.76#ibcon#flushed, iclass 30, count 0 2006.201.16:35:59.76#ibcon#about to write, iclass 30, count 0 2006.201.16:35:59.76#ibcon#wrote, iclass 30, count 0 2006.201.16:35:59.76#ibcon#about to read 3, iclass 30, count 0 2006.201.16:35:59.78#ibcon#read 3, iclass 30, count 0 2006.201.16:35:59.78#ibcon#about to read 4, iclass 30, count 0 2006.201.16:35:59.78#ibcon#read 4, iclass 30, count 0 2006.201.16:35:59.78#ibcon#about to read 5, iclass 30, count 0 2006.201.16:35:59.78#ibcon#read 5, iclass 30, count 0 2006.201.16:35:59.78#ibcon#about to read 6, iclass 30, count 0 2006.201.16:35:59.78#ibcon#read 6, iclass 30, count 0 2006.201.16:35:59.78#ibcon#end of sib2, iclass 30, count 0 2006.201.16:35:59.78#ibcon#*mode == 0, iclass 30, count 0 2006.201.16:35:59.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.16:35:59.78#ibcon#[27=USB\r\n] 2006.201.16:35:59.78#ibcon#*before write, iclass 30, count 0 2006.201.16:35:59.78#ibcon#enter sib2, iclass 30, count 0 2006.201.16:35:59.78#ibcon#flushed, iclass 30, count 0 2006.201.16:35:59.78#ibcon#about to write, iclass 30, count 0 2006.201.16:35:59.78#ibcon#wrote, iclass 30, count 0 2006.201.16:35:59.78#ibcon#about to read 3, iclass 30, count 0 2006.201.16:35:59.81#ibcon#read 3, iclass 30, count 0 2006.201.16:35:59.81#ibcon#about to read 4, iclass 30, count 0 2006.201.16:35:59.81#ibcon#read 4, iclass 30, count 0 2006.201.16:35:59.81#ibcon#about to read 5, iclass 30, count 0 2006.201.16:35:59.81#ibcon#read 5, iclass 30, count 0 2006.201.16:35:59.81#ibcon#about to read 6, iclass 30, count 0 2006.201.16:35:59.81#ibcon#read 6, iclass 30, count 0 2006.201.16:35:59.81#ibcon#end of sib2, iclass 30, count 0 2006.201.16:35:59.81#ibcon#*after write, iclass 30, count 0 2006.201.16:35:59.81#ibcon#*before return 0, iclass 30, count 0 2006.201.16:35:59.81#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:59.81#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:35:59.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.16:35:59.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.16:35:59.81$vck44/vblo=2,634.99 2006.201.16:35:59.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.16:35:59.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.16:35:59.81#ibcon#ireg 17 cls_cnt 0 2006.201.16:35:59.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:59.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:59.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:59.81#ibcon#enter wrdev, iclass 32, count 0 2006.201.16:35:59.81#ibcon#first serial, iclass 32, count 0 2006.201.16:35:59.81#ibcon#enter sib2, iclass 32, count 0 2006.201.16:35:59.81#ibcon#flushed, iclass 32, count 0 2006.201.16:35:59.81#ibcon#about to write, iclass 32, count 0 2006.201.16:35:59.81#ibcon#wrote, iclass 32, count 0 2006.201.16:35:59.81#ibcon#about to read 3, iclass 32, count 0 2006.201.16:35:59.83#ibcon#read 3, iclass 32, count 0 2006.201.16:35:59.83#ibcon#about to read 4, iclass 32, count 0 2006.201.16:35:59.83#ibcon#read 4, iclass 32, count 0 2006.201.16:35:59.83#ibcon#about to read 5, iclass 32, count 0 2006.201.16:35:59.83#ibcon#read 5, iclass 32, count 0 2006.201.16:35:59.83#ibcon#about to read 6, iclass 32, count 0 2006.201.16:35:59.83#ibcon#read 6, iclass 32, count 0 2006.201.16:35:59.83#ibcon#end of sib2, iclass 32, count 0 2006.201.16:35:59.83#ibcon#*mode == 0, iclass 32, count 0 2006.201.16:35:59.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.16:35:59.83#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:35:59.83#ibcon#*before write, iclass 32, count 0 2006.201.16:35:59.83#ibcon#enter sib2, iclass 32, count 0 2006.201.16:35:59.83#ibcon#flushed, iclass 32, count 0 2006.201.16:35:59.83#ibcon#about to write, iclass 32, count 0 2006.201.16:35:59.83#ibcon#wrote, iclass 32, count 0 2006.201.16:35:59.83#ibcon#about to read 3, iclass 32, count 0 2006.201.16:35:59.87#ibcon#read 3, iclass 32, count 0 2006.201.16:35:59.87#ibcon#about to read 4, iclass 32, count 0 2006.201.16:35:59.87#ibcon#read 4, iclass 32, count 0 2006.201.16:35:59.87#ibcon#about to read 5, iclass 32, count 0 2006.201.16:35:59.87#ibcon#read 5, iclass 32, count 0 2006.201.16:35:59.87#ibcon#about to read 6, iclass 32, count 0 2006.201.16:35:59.87#ibcon#read 6, iclass 32, count 0 2006.201.16:35:59.87#ibcon#end of sib2, iclass 32, count 0 2006.201.16:35:59.87#ibcon#*after write, iclass 32, count 0 2006.201.16:35:59.87#ibcon#*before return 0, iclass 32, count 0 2006.201.16:35:59.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:59.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:35:59.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.16:35:59.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.16:35:59.87$vck44/vb=2,5 2006.201.16:35:59.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.16:35:59.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.16:35:59.87#ibcon#ireg 11 cls_cnt 2 2006.201.16:35:59.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:59.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:59.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:59.93#ibcon#enter wrdev, iclass 34, count 2 2006.201.16:35:59.93#ibcon#first serial, iclass 34, count 2 2006.201.16:35:59.93#ibcon#enter sib2, iclass 34, count 2 2006.201.16:35:59.93#ibcon#flushed, iclass 34, count 2 2006.201.16:35:59.93#ibcon#about to write, iclass 34, count 2 2006.201.16:35:59.93#ibcon#wrote, iclass 34, count 2 2006.201.16:35:59.93#ibcon#about to read 3, iclass 34, count 2 2006.201.16:35:59.95#ibcon#read 3, iclass 34, count 2 2006.201.16:35:59.95#ibcon#about to read 4, iclass 34, count 2 2006.201.16:35:59.95#ibcon#read 4, iclass 34, count 2 2006.201.16:35:59.95#ibcon#about to read 5, iclass 34, count 2 2006.201.16:35:59.95#ibcon#read 5, iclass 34, count 2 2006.201.16:35:59.95#ibcon#about to read 6, iclass 34, count 2 2006.201.16:35:59.95#ibcon#read 6, iclass 34, count 2 2006.201.16:35:59.95#ibcon#end of sib2, iclass 34, count 2 2006.201.16:35:59.95#ibcon#*mode == 0, iclass 34, count 2 2006.201.16:35:59.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.16:35:59.95#ibcon#[27=AT02-05\r\n] 2006.201.16:35:59.95#ibcon#*before write, iclass 34, count 2 2006.201.16:35:59.95#ibcon#enter sib2, iclass 34, count 2 2006.201.16:35:59.95#ibcon#flushed, iclass 34, count 2 2006.201.16:35:59.95#ibcon#about to write, iclass 34, count 2 2006.201.16:35:59.95#ibcon#wrote, iclass 34, count 2 2006.201.16:35:59.95#ibcon#about to read 3, iclass 34, count 2 2006.201.16:35:59.98#ibcon#read 3, iclass 34, count 2 2006.201.16:35:59.98#ibcon#about to read 4, iclass 34, count 2 2006.201.16:35:59.98#ibcon#read 4, iclass 34, count 2 2006.201.16:35:59.98#ibcon#about to read 5, iclass 34, count 2 2006.201.16:35:59.98#ibcon#read 5, iclass 34, count 2 2006.201.16:35:59.98#ibcon#about to read 6, iclass 34, count 2 2006.201.16:35:59.98#ibcon#read 6, iclass 34, count 2 2006.201.16:35:59.98#ibcon#end of sib2, iclass 34, count 2 2006.201.16:35:59.98#ibcon#*after write, iclass 34, count 2 2006.201.16:35:59.98#ibcon#*before return 0, iclass 34, count 2 2006.201.16:35:59.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:59.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:35:59.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.16:35:59.98#ibcon#ireg 7 cls_cnt 0 2006.201.16:35:59.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:36:00.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:36:00.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:36:00.10#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:36:00.10#ibcon#first serial, iclass 34, count 0 2006.201.16:36:00.10#ibcon#enter sib2, iclass 34, count 0 2006.201.16:36:00.10#ibcon#flushed, iclass 34, count 0 2006.201.16:36:00.10#ibcon#about to write, iclass 34, count 0 2006.201.16:36:00.10#ibcon#wrote, iclass 34, count 0 2006.201.16:36:00.10#ibcon#about to read 3, iclass 34, count 0 2006.201.16:36:00.12#ibcon#read 3, iclass 34, count 0 2006.201.16:36:00.12#ibcon#about to read 4, iclass 34, count 0 2006.201.16:36:00.12#ibcon#read 4, iclass 34, count 0 2006.201.16:36:00.12#ibcon#about to read 5, iclass 34, count 0 2006.201.16:36:00.12#ibcon#read 5, iclass 34, count 0 2006.201.16:36:00.12#ibcon#about to read 6, iclass 34, count 0 2006.201.16:36:00.12#ibcon#read 6, iclass 34, count 0 2006.201.16:36:00.12#ibcon#end of sib2, iclass 34, count 0 2006.201.16:36:00.12#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:36:00.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:36:00.12#ibcon#[27=USB\r\n] 2006.201.16:36:00.12#ibcon#*before write, iclass 34, count 0 2006.201.16:36:00.12#ibcon#enter sib2, iclass 34, count 0 2006.201.16:36:00.12#ibcon#flushed, iclass 34, count 0 2006.201.16:36:00.12#ibcon#about to write, iclass 34, count 0 2006.201.16:36:00.12#ibcon#wrote, iclass 34, count 0 2006.201.16:36:00.12#ibcon#about to read 3, iclass 34, count 0 2006.201.16:36:00.15#ibcon#read 3, iclass 34, count 0 2006.201.16:36:00.15#ibcon#about to read 4, iclass 34, count 0 2006.201.16:36:00.15#ibcon#read 4, iclass 34, count 0 2006.201.16:36:00.15#ibcon#about to read 5, iclass 34, count 0 2006.201.16:36:00.15#ibcon#read 5, iclass 34, count 0 2006.201.16:36:00.15#ibcon#about to read 6, iclass 34, count 0 2006.201.16:36:00.15#ibcon#read 6, iclass 34, count 0 2006.201.16:36:00.15#ibcon#end of sib2, iclass 34, count 0 2006.201.16:36:00.15#ibcon#*after write, iclass 34, count 0 2006.201.16:36:00.15#ibcon#*before return 0, iclass 34, count 0 2006.201.16:36:00.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:36:00.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:36:00.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:36:00.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:36:00.15$vck44/vblo=3,649.99 2006.201.16:36:00.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.16:36:00.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.16:36:00.15#ibcon#ireg 17 cls_cnt 0 2006.201.16:36:00.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:36:00.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:36:00.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:36:00.15#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:36:00.15#ibcon#first serial, iclass 36, count 0 2006.201.16:36:00.15#ibcon#enter sib2, iclass 36, count 0 2006.201.16:36:00.15#ibcon#flushed, iclass 36, count 0 2006.201.16:36:00.15#ibcon#about to write, iclass 36, count 0 2006.201.16:36:00.15#ibcon#wrote, iclass 36, count 0 2006.201.16:36:00.15#ibcon#about to read 3, iclass 36, count 0 2006.201.16:36:00.17#ibcon#read 3, iclass 36, count 0 2006.201.16:36:00.17#ibcon#about to read 4, iclass 36, count 0 2006.201.16:36:00.17#ibcon#read 4, iclass 36, count 0 2006.201.16:36:00.17#ibcon#about to read 5, iclass 36, count 0 2006.201.16:36:00.17#ibcon#read 5, iclass 36, count 0 2006.201.16:36:00.17#ibcon#about to read 6, iclass 36, count 0 2006.201.16:36:00.17#ibcon#read 6, iclass 36, count 0 2006.201.16:36:00.17#ibcon#end of sib2, iclass 36, count 0 2006.201.16:36:00.17#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:36:00.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:36:00.17#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:36:00.17#ibcon#*before write, iclass 36, count 0 2006.201.16:36:00.17#ibcon#enter sib2, iclass 36, count 0 2006.201.16:36:00.17#ibcon#flushed, iclass 36, count 0 2006.201.16:36:00.17#ibcon#about to write, iclass 36, count 0 2006.201.16:36:00.17#ibcon#wrote, iclass 36, count 0 2006.201.16:36:00.17#ibcon#about to read 3, iclass 36, count 0 2006.201.16:36:00.21#ibcon#read 3, iclass 36, count 0 2006.201.16:36:00.21#ibcon#about to read 4, iclass 36, count 0 2006.201.16:36:00.21#ibcon#read 4, iclass 36, count 0 2006.201.16:36:00.21#ibcon#about to read 5, iclass 36, count 0 2006.201.16:36:00.21#ibcon#read 5, iclass 36, count 0 2006.201.16:36:00.21#ibcon#about to read 6, iclass 36, count 0 2006.201.16:36:00.21#ibcon#read 6, iclass 36, count 0 2006.201.16:36:00.21#ibcon#end of sib2, iclass 36, count 0 2006.201.16:36:00.21#ibcon#*after write, iclass 36, count 0 2006.201.16:36:00.21#ibcon#*before return 0, iclass 36, count 0 2006.201.16:36:00.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:36:00.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:36:00.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:36:00.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:36:00.21$vck44/vb=3,4 2006.201.16:36:00.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.16:36:00.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.16:36:00.21#ibcon#ireg 11 cls_cnt 2 2006.201.16:36:00.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:36:00.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:36:00.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:36:00.27#ibcon#enter wrdev, iclass 38, count 2 2006.201.16:36:00.27#ibcon#first serial, iclass 38, count 2 2006.201.16:36:00.27#ibcon#enter sib2, iclass 38, count 2 2006.201.16:36:00.27#ibcon#flushed, iclass 38, count 2 2006.201.16:36:00.27#ibcon#about to write, iclass 38, count 2 2006.201.16:36:00.27#ibcon#wrote, iclass 38, count 2 2006.201.16:36:00.27#ibcon#about to read 3, iclass 38, count 2 2006.201.16:36:00.29#ibcon#read 3, iclass 38, count 2 2006.201.16:36:00.29#ibcon#about to read 4, iclass 38, count 2 2006.201.16:36:00.29#ibcon#read 4, iclass 38, count 2 2006.201.16:36:00.29#ibcon#about to read 5, iclass 38, count 2 2006.201.16:36:00.29#ibcon#read 5, iclass 38, count 2 2006.201.16:36:00.29#ibcon#about to read 6, iclass 38, count 2 2006.201.16:36:00.29#ibcon#read 6, iclass 38, count 2 2006.201.16:36:00.29#ibcon#end of sib2, iclass 38, count 2 2006.201.16:36:00.29#ibcon#*mode == 0, iclass 38, count 2 2006.201.16:36:00.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.16:36:00.29#ibcon#[27=AT03-04\r\n] 2006.201.16:36:00.29#ibcon#*before write, iclass 38, count 2 2006.201.16:36:00.29#ibcon#enter sib2, iclass 38, count 2 2006.201.16:36:00.29#ibcon#flushed, iclass 38, count 2 2006.201.16:36:00.29#ibcon#about to write, iclass 38, count 2 2006.201.16:36:00.29#ibcon#wrote, iclass 38, count 2 2006.201.16:36:00.29#ibcon#about to read 3, iclass 38, count 2 2006.201.16:36:00.32#ibcon#read 3, iclass 38, count 2 2006.201.16:36:00.32#ibcon#about to read 4, iclass 38, count 2 2006.201.16:36:00.32#ibcon#read 4, iclass 38, count 2 2006.201.16:36:00.32#ibcon#about to read 5, iclass 38, count 2 2006.201.16:36:00.32#ibcon#read 5, iclass 38, count 2 2006.201.16:36:00.32#ibcon#about to read 6, iclass 38, count 2 2006.201.16:36:00.32#ibcon#read 6, iclass 38, count 2 2006.201.16:36:00.32#ibcon#end of sib2, iclass 38, count 2 2006.201.16:36:00.32#ibcon#*after write, iclass 38, count 2 2006.201.16:36:00.32#ibcon#*before return 0, iclass 38, count 2 2006.201.16:36:00.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:36:00.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:36:00.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.16:36:00.32#ibcon#ireg 7 cls_cnt 0 2006.201.16:36:00.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:36:00.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:36:00.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:36:00.44#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:36:00.44#ibcon#first serial, iclass 38, count 0 2006.201.16:36:00.44#ibcon#enter sib2, iclass 38, count 0 2006.201.16:36:00.44#ibcon#flushed, iclass 38, count 0 2006.201.16:36:00.44#ibcon#about to write, iclass 38, count 0 2006.201.16:36:00.44#ibcon#wrote, iclass 38, count 0 2006.201.16:36:00.44#ibcon#about to read 3, iclass 38, count 0 2006.201.16:36:00.46#ibcon#read 3, iclass 38, count 0 2006.201.16:36:00.46#ibcon#about to read 4, iclass 38, count 0 2006.201.16:36:00.46#ibcon#read 4, iclass 38, count 0 2006.201.16:36:00.46#ibcon#about to read 5, iclass 38, count 0 2006.201.16:36:00.46#ibcon#read 5, iclass 38, count 0 2006.201.16:36:00.46#ibcon#about to read 6, iclass 38, count 0 2006.201.16:36:00.46#ibcon#read 6, iclass 38, count 0 2006.201.16:36:00.46#ibcon#end of sib2, iclass 38, count 0 2006.201.16:36:00.46#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:36:00.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:36:00.46#ibcon#[27=USB\r\n] 2006.201.16:36:00.46#ibcon#*before write, iclass 38, count 0 2006.201.16:36:00.46#ibcon#enter sib2, iclass 38, count 0 2006.201.16:36:00.46#ibcon#flushed, iclass 38, count 0 2006.201.16:36:00.46#ibcon#about to write, iclass 38, count 0 2006.201.16:36:00.46#ibcon#wrote, iclass 38, count 0 2006.201.16:36:00.46#ibcon#about to read 3, iclass 38, count 0 2006.201.16:36:00.49#ibcon#read 3, iclass 38, count 0 2006.201.16:36:00.49#ibcon#about to read 4, iclass 38, count 0 2006.201.16:36:00.49#ibcon#read 4, iclass 38, count 0 2006.201.16:36:00.49#ibcon#about to read 5, iclass 38, count 0 2006.201.16:36:00.49#ibcon#read 5, iclass 38, count 0 2006.201.16:36:00.49#ibcon#about to read 6, iclass 38, count 0 2006.201.16:36:00.49#ibcon#read 6, iclass 38, count 0 2006.201.16:36:00.49#ibcon#end of sib2, iclass 38, count 0 2006.201.16:36:00.49#ibcon#*after write, iclass 38, count 0 2006.201.16:36:00.49#ibcon#*before return 0, iclass 38, count 0 2006.201.16:36:00.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:36:00.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:36:00.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:36:00.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:36:00.49$vck44/vblo=4,679.99 2006.201.16:36:00.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.16:36:00.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.16:36:00.49#ibcon#ireg 17 cls_cnt 0 2006.201.16:36:00.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:36:00.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:36:00.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:36:00.49#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:36:00.49#ibcon#first serial, iclass 40, count 0 2006.201.16:36:00.49#ibcon#enter sib2, iclass 40, count 0 2006.201.16:36:00.49#ibcon#flushed, iclass 40, count 0 2006.201.16:36:00.49#ibcon#about to write, iclass 40, count 0 2006.201.16:36:00.49#ibcon#wrote, iclass 40, count 0 2006.201.16:36:00.49#ibcon#about to read 3, iclass 40, count 0 2006.201.16:36:00.51#ibcon#read 3, iclass 40, count 0 2006.201.16:36:00.51#ibcon#about to read 4, iclass 40, count 0 2006.201.16:36:00.51#ibcon#read 4, iclass 40, count 0 2006.201.16:36:00.51#ibcon#about to read 5, iclass 40, count 0 2006.201.16:36:00.51#ibcon#read 5, iclass 40, count 0 2006.201.16:36:00.51#ibcon#about to read 6, iclass 40, count 0 2006.201.16:36:00.51#ibcon#read 6, iclass 40, count 0 2006.201.16:36:00.51#ibcon#end of sib2, iclass 40, count 0 2006.201.16:36:00.51#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:36:00.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:36:00.51#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:36:00.51#ibcon#*before write, iclass 40, count 0 2006.201.16:36:00.51#ibcon#enter sib2, iclass 40, count 0 2006.201.16:36:00.51#ibcon#flushed, iclass 40, count 0 2006.201.16:36:00.51#ibcon#about to write, iclass 40, count 0 2006.201.16:36:00.51#ibcon#wrote, iclass 40, count 0 2006.201.16:36:00.51#ibcon#about to read 3, iclass 40, count 0 2006.201.16:36:00.56#ibcon#read 3, iclass 40, count 0 2006.201.16:36:00.56#ibcon#about to read 4, iclass 40, count 0 2006.201.16:36:00.56#ibcon#read 4, iclass 40, count 0 2006.201.16:36:00.56#ibcon#about to read 5, iclass 40, count 0 2006.201.16:36:00.56#ibcon#read 5, iclass 40, count 0 2006.201.16:36:00.56#ibcon#about to read 6, iclass 40, count 0 2006.201.16:36:00.56#ibcon#read 6, iclass 40, count 0 2006.201.16:36:00.56#ibcon#end of sib2, iclass 40, count 0 2006.201.16:36:00.56#ibcon#*after write, iclass 40, count 0 2006.201.16:36:00.56#ibcon#*before return 0, iclass 40, count 0 2006.201.16:36:00.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:36:00.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:36:00.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:36:00.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:36:00.56$vck44/vb=4,5 2006.201.16:36:00.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.16:36:00.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.16:36:00.56#ibcon#ireg 11 cls_cnt 2 2006.201.16:36:00.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:36:00.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:36:00.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:36:00.61#ibcon#enter wrdev, iclass 4, count 2 2006.201.16:36:00.61#ibcon#first serial, iclass 4, count 2 2006.201.16:36:00.61#ibcon#enter sib2, iclass 4, count 2 2006.201.16:36:00.61#ibcon#flushed, iclass 4, count 2 2006.201.16:36:00.61#ibcon#about to write, iclass 4, count 2 2006.201.16:36:00.61#ibcon#wrote, iclass 4, count 2 2006.201.16:36:00.61#ibcon#about to read 3, iclass 4, count 2 2006.201.16:36:00.63#ibcon#read 3, iclass 4, count 2 2006.201.16:36:00.63#ibcon#about to read 4, iclass 4, count 2 2006.201.16:36:00.63#ibcon#read 4, iclass 4, count 2 2006.201.16:36:00.63#ibcon#about to read 5, iclass 4, count 2 2006.201.16:36:00.63#ibcon#read 5, iclass 4, count 2 2006.201.16:36:00.63#ibcon#about to read 6, iclass 4, count 2 2006.201.16:36:00.63#ibcon#read 6, iclass 4, count 2 2006.201.16:36:00.63#ibcon#end of sib2, iclass 4, count 2 2006.201.16:36:00.63#ibcon#*mode == 0, iclass 4, count 2 2006.201.16:36:00.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.16:36:00.63#ibcon#[27=AT04-05\r\n] 2006.201.16:36:00.63#ibcon#*before write, iclass 4, count 2 2006.201.16:36:00.63#ibcon#enter sib2, iclass 4, count 2 2006.201.16:36:00.63#ibcon#flushed, iclass 4, count 2 2006.201.16:36:00.63#ibcon#about to write, iclass 4, count 2 2006.201.16:36:00.63#ibcon#wrote, iclass 4, count 2 2006.201.16:36:00.63#ibcon#about to read 3, iclass 4, count 2 2006.201.16:36:00.66#ibcon#read 3, iclass 4, count 2 2006.201.16:36:00.66#ibcon#about to read 4, iclass 4, count 2 2006.201.16:36:00.66#ibcon#read 4, iclass 4, count 2 2006.201.16:36:00.66#ibcon#about to read 5, iclass 4, count 2 2006.201.16:36:00.66#ibcon#read 5, iclass 4, count 2 2006.201.16:36:00.66#ibcon#about to read 6, iclass 4, count 2 2006.201.16:36:00.66#ibcon#read 6, iclass 4, count 2 2006.201.16:36:00.66#ibcon#end of sib2, iclass 4, count 2 2006.201.16:36:00.66#ibcon#*after write, iclass 4, count 2 2006.201.16:36:00.66#ibcon#*before return 0, iclass 4, count 2 2006.201.16:36:00.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:36:00.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:36:00.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.16:36:00.66#ibcon#ireg 7 cls_cnt 0 2006.201.16:36:00.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:36:00.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:36:00.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:36:00.78#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:36:00.78#ibcon#first serial, iclass 4, count 0 2006.201.16:36:00.78#ibcon#enter sib2, iclass 4, count 0 2006.201.16:36:00.78#ibcon#flushed, iclass 4, count 0 2006.201.16:36:00.78#ibcon#about to write, iclass 4, count 0 2006.201.16:36:00.78#ibcon#wrote, iclass 4, count 0 2006.201.16:36:00.78#ibcon#about to read 3, iclass 4, count 0 2006.201.16:36:00.80#ibcon#read 3, iclass 4, count 0 2006.201.16:36:00.80#ibcon#about to read 4, iclass 4, count 0 2006.201.16:36:00.80#ibcon#read 4, iclass 4, count 0 2006.201.16:36:00.80#ibcon#about to read 5, iclass 4, count 0 2006.201.16:36:00.80#ibcon#read 5, iclass 4, count 0 2006.201.16:36:00.80#ibcon#about to read 6, iclass 4, count 0 2006.201.16:36:00.80#ibcon#read 6, iclass 4, count 0 2006.201.16:36:00.80#ibcon#end of sib2, iclass 4, count 0 2006.201.16:36:00.80#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:36:00.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:36:00.80#ibcon#[27=USB\r\n] 2006.201.16:36:00.80#ibcon#*before write, iclass 4, count 0 2006.201.16:36:00.80#ibcon#enter sib2, iclass 4, count 0 2006.201.16:36:00.80#ibcon#flushed, iclass 4, count 0 2006.201.16:36:00.80#ibcon#about to write, iclass 4, count 0 2006.201.16:36:00.80#ibcon#wrote, iclass 4, count 0 2006.201.16:36:00.80#ibcon#about to read 3, iclass 4, count 0 2006.201.16:36:00.83#ibcon#read 3, iclass 4, count 0 2006.201.16:36:00.83#ibcon#about to read 4, iclass 4, count 0 2006.201.16:36:00.83#ibcon#read 4, iclass 4, count 0 2006.201.16:36:00.83#ibcon#about to read 5, iclass 4, count 0 2006.201.16:36:00.83#ibcon#read 5, iclass 4, count 0 2006.201.16:36:00.83#ibcon#about to read 6, iclass 4, count 0 2006.201.16:36:00.83#ibcon#read 6, iclass 4, count 0 2006.201.16:36:00.83#ibcon#end of sib2, iclass 4, count 0 2006.201.16:36:00.83#ibcon#*after write, iclass 4, count 0 2006.201.16:36:00.83#ibcon#*before return 0, iclass 4, count 0 2006.201.16:36:00.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:36:00.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:36:00.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:36:00.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:36:00.83$vck44/vblo=5,709.99 2006.201.16:36:00.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.16:36:00.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.16:36:00.83#ibcon#ireg 17 cls_cnt 0 2006.201.16:36:00.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:36:00.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:36:00.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:36:00.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:36:00.83#ibcon#first serial, iclass 6, count 0 2006.201.16:36:00.83#ibcon#enter sib2, iclass 6, count 0 2006.201.16:36:00.83#ibcon#flushed, iclass 6, count 0 2006.201.16:36:00.83#ibcon#about to write, iclass 6, count 0 2006.201.16:36:00.83#ibcon#wrote, iclass 6, count 0 2006.201.16:36:00.83#ibcon#about to read 3, iclass 6, count 0 2006.201.16:36:00.85#ibcon#read 3, iclass 6, count 0 2006.201.16:36:00.85#ibcon#about to read 4, iclass 6, count 0 2006.201.16:36:00.85#ibcon#read 4, iclass 6, count 0 2006.201.16:36:00.85#ibcon#about to read 5, iclass 6, count 0 2006.201.16:36:00.85#ibcon#read 5, iclass 6, count 0 2006.201.16:36:00.85#ibcon#about to read 6, iclass 6, count 0 2006.201.16:36:00.85#ibcon#read 6, iclass 6, count 0 2006.201.16:36:00.85#ibcon#end of sib2, iclass 6, count 0 2006.201.16:36:00.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:36:00.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:36:00.85#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:36:00.85#ibcon#*before write, iclass 6, count 0 2006.201.16:36:00.85#ibcon#enter sib2, iclass 6, count 0 2006.201.16:36:00.85#ibcon#flushed, iclass 6, count 0 2006.201.16:36:00.85#ibcon#about to write, iclass 6, count 0 2006.201.16:36:00.85#ibcon#wrote, iclass 6, count 0 2006.201.16:36:00.85#ibcon#about to read 3, iclass 6, count 0 2006.201.16:36:00.89#ibcon#read 3, iclass 6, count 0 2006.201.16:36:00.89#ibcon#about to read 4, iclass 6, count 0 2006.201.16:36:00.89#ibcon#read 4, iclass 6, count 0 2006.201.16:36:00.89#ibcon#about to read 5, iclass 6, count 0 2006.201.16:36:00.89#ibcon#read 5, iclass 6, count 0 2006.201.16:36:00.89#ibcon#about to read 6, iclass 6, count 0 2006.201.16:36:00.89#ibcon#read 6, iclass 6, count 0 2006.201.16:36:00.89#ibcon#end of sib2, iclass 6, count 0 2006.201.16:36:00.89#ibcon#*after write, iclass 6, count 0 2006.201.16:36:00.89#ibcon#*before return 0, iclass 6, count 0 2006.201.16:36:00.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:36:00.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:36:00.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:36:00.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:36:00.89$vck44/vb=5,4 2006.201.16:36:00.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.16:36:00.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.16:36:00.89#ibcon#ireg 11 cls_cnt 2 2006.201.16:36:00.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:36:00.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:36:00.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:36:00.95#ibcon#enter wrdev, iclass 10, count 2 2006.201.16:36:00.95#ibcon#first serial, iclass 10, count 2 2006.201.16:36:00.95#ibcon#enter sib2, iclass 10, count 2 2006.201.16:36:00.95#ibcon#flushed, iclass 10, count 2 2006.201.16:36:00.95#ibcon#about to write, iclass 10, count 2 2006.201.16:36:00.95#ibcon#wrote, iclass 10, count 2 2006.201.16:36:00.95#ibcon#about to read 3, iclass 10, count 2 2006.201.16:36:00.97#ibcon#read 3, iclass 10, count 2 2006.201.16:36:00.97#ibcon#about to read 4, iclass 10, count 2 2006.201.16:36:00.97#ibcon#read 4, iclass 10, count 2 2006.201.16:36:00.97#ibcon#about to read 5, iclass 10, count 2 2006.201.16:36:00.97#ibcon#read 5, iclass 10, count 2 2006.201.16:36:00.97#ibcon#about to read 6, iclass 10, count 2 2006.201.16:36:00.97#ibcon#read 6, iclass 10, count 2 2006.201.16:36:00.97#ibcon#end of sib2, iclass 10, count 2 2006.201.16:36:00.97#ibcon#*mode == 0, iclass 10, count 2 2006.201.16:36:00.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.16:36:00.97#ibcon#[27=AT05-04\r\n] 2006.201.16:36:00.97#ibcon#*before write, iclass 10, count 2 2006.201.16:36:00.97#ibcon#enter sib2, iclass 10, count 2 2006.201.16:36:00.97#ibcon#flushed, iclass 10, count 2 2006.201.16:36:00.97#ibcon#about to write, iclass 10, count 2 2006.201.16:36:00.97#ibcon#wrote, iclass 10, count 2 2006.201.16:36:00.97#ibcon#about to read 3, iclass 10, count 2 2006.201.16:36:01.00#ibcon#read 3, iclass 10, count 2 2006.201.16:36:01.00#ibcon#about to read 4, iclass 10, count 2 2006.201.16:36:01.00#ibcon#read 4, iclass 10, count 2 2006.201.16:36:01.00#ibcon#about to read 5, iclass 10, count 2 2006.201.16:36:01.00#ibcon#read 5, iclass 10, count 2 2006.201.16:36:01.00#ibcon#about to read 6, iclass 10, count 2 2006.201.16:36:01.00#ibcon#read 6, iclass 10, count 2 2006.201.16:36:01.00#ibcon#end of sib2, iclass 10, count 2 2006.201.16:36:01.00#ibcon#*after write, iclass 10, count 2 2006.201.16:36:01.00#ibcon#*before return 0, iclass 10, count 2 2006.201.16:36:01.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:36:01.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:36:01.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.16:36:01.00#ibcon#ireg 7 cls_cnt 0 2006.201.16:36:01.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:36:01.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:36:01.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:36:01.12#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:36:01.12#ibcon#first serial, iclass 10, count 0 2006.201.16:36:01.12#ibcon#enter sib2, iclass 10, count 0 2006.201.16:36:01.12#ibcon#flushed, iclass 10, count 0 2006.201.16:36:01.12#ibcon#about to write, iclass 10, count 0 2006.201.16:36:01.12#ibcon#wrote, iclass 10, count 0 2006.201.16:36:01.12#ibcon#about to read 3, iclass 10, count 0 2006.201.16:36:01.14#ibcon#read 3, iclass 10, count 0 2006.201.16:36:01.14#ibcon#about to read 4, iclass 10, count 0 2006.201.16:36:01.14#ibcon#read 4, iclass 10, count 0 2006.201.16:36:01.14#ibcon#about to read 5, iclass 10, count 0 2006.201.16:36:01.14#ibcon#read 5, iclass 10, count 0 2006.201.16:36:01.14#ibcon#about to read 6, iclass 10, count 0 2006.201.16:36:01.14#ibcon#read 6, iclass 10, count 0 2006.201.16:36:01.14#ibcon#end of sib2, iclass 10, count 0 2006.201.16:36:01.14#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:36:01.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:36:01.14#ibcon#[27=USB\r\n] 2006.201.16:36:01.14#ibcon#*before write, iclass 10, count 0 2006.201.16:36:01.14#ibcon#enter sib2, iclass 10, count 0 2006.201.16:36:01.14#ibcon#flushed, iclass 10, count 0 2006.201.16:36:01.14#ibcon#about to write, iclass 10, count 0 2006.201.16:36:01.14#ibcon#wrote, iclass 10, count 0 2006.201.16:36:01.14#ibcon#about to read 3, iclass 10, count 0 2006.201.16:36:01.17#ibcon#read 3, iclass 10, count 0 2006.201.16:36:01.17#ibcon#about to read 4, iclass 10, count 0 2006.201.16:36:01.17#ibcon#read 4, iclass 10, count 0 2006.201.16:36:01.17#ibcon#about to read 5, iclass 10, count 0 2006.201.16:36:01.17#ibcon#read 5, iclass 10, count 0 2006.201.16:36:01.17#ibcon#about to read 6, iclass 10, count 0 2006.201.16:36:01.17#ibcon#read 6, iclass 10, count 0 2006.201.16:36:01.17#ibcon#end of sib2, iclass 10, count 0 2006.201.16:36:01.17#ibcon#*after write, iclass 10, count 0 2006.201.16:36:01.17#ibcon#*before return 0, iclass 10, count 0 2006.201.16:36:01.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:36:01.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:36:01.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:36:01.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:36:01.17$vck44/vblo=6,719.99 2006.201.16:36:01.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.16:36:01.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.16:36:01.17#ibcon#ireg 17 cls_cnt 0 2006.201.16:36:01.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:36:01.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:36:01.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:36:01.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:36:01.17#ibcon#first serial, iclass 12, count 0 2006.201.16:36:01.17#ibcon#enter sib2, iclass 12, count 0 2006.201.16:36:01.17#ibcon#flushed, iclass 12, count 0 2006.201.16:36:01.17#ibcon#about to write, iclass 12, count 0 2006.201.16:36:01.17#ibcon#wrote, iclass 12, count 0 2006.201.16:36:01.17#ibcon#about to read 3, iclass 12, count 0 2006.201.16:36:01.19#ibcon#read 3, iclass 12, count 0 2006.201.16:36:01.19#ibcon#about to read 4, iclass 12, count 0 2006.201.16:36:01.19#ibcon#read 4, iclass 12, count 0 2006.201.16:36:01.19#ibcon#about to read 5, iclass 12, count 0 2006.201.16:36:01.19#ibcon#read 5, iclass 12, count 0 2006.201.16:36:01.19#ibcon#about to read 6, iclass 12, count 0 2006.201.16:36:01.19#ibcon#read 6, iclass 12, count 0 2006.201.16:36:01.19#ibcon#end of sib2, iclass 12, count 0 2006.201.16:36:01.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:36:01.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:36:01.19#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:36:01.19#ibcon#*before write, iclass 12, count 0 2006.201.16:36:01.19#ibcon#enter sib2, iclass 12, count 0 2006.201.16:36:01.19#ibcon#flushed, iclass 12, count 0 2006.201.16:36:01.19#ibcon#about to write, iclass 12, count 0 2006.201.16:36:01.19#ibcon#wrote, iclass 12, count 0 2006.201.16:36:01.19#ibcon#about to read 3, iclass 12, count 0 2006.201.16:36:01.23#ibcon#read 3, iclass 12, count 0 2006.201.16:36:01.23#ibcon#about to read 4, iclass 12, count 0 2006.201.16:36:01.23#ibcon#read 4, iclass 12, count 0 2006.201.16:36:01.23#ibcon#about to read 5, iclass 12, count 0 2006.201.16:36:01.23#ibcon#read 5, iclass 12, count 0 2006.201.16:36:01.23#ibcon#about to read 6, iclass 12, count 0 2006.201.16:36:01.23#ibcon#read 6, iclass 12, count 0 2006.201.16:36:01.23#ibcon#end of sib2, iclass 12, count 0 2006.201.16:36:01.23#ibcon#*after write, iclass 12, count 0 2006.201.16:36:01.23#ibcon#*before return 0, iclass 12, count 0 2006.201.16:36:01.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:36:01.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:36:01.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:36:01.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:36:01.23$vck44/vb=6,4 2006.201.16:36:01.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.16:36:01.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.16:36:01.23#ibcon#ireg 11 cls_cnt 2 2006.201.16:36:01.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:36:01.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:36:01.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:36:01.29#ibcon#enter wrdev, iclass 14, count 2 2006.201.16:36:01.29#ibcon#first serial, iclass 14, count 2 2006.201.16:36:01.29#ibcon#enter sib2, iclass 14, count 2 2006.201.16:36:01.29#ibcon#flushed, iclass 14, count 2 2006.201.16:36:01.29#ibcon#about to write, iclass 14, count 2 2006.201.16:36:01.29#ibcon#wrote, iclass 14, count 2 2006.201.16:36:01.29#ibcon#about to read 3, iclass 14, count 2 2006.201.16:36:01.31#ibcon#read 3, iclass 14, count 2 2006.201.16:36:01.31#ibcon#about to read 4, iclass 14, count 2 2006.201.16:36:01.31#ibcon#read 4, iclass 14, count 2 2006.201.16:36:01.31#ibcon#about to read 5, iclass 14, count 2 2006.201.16:36:01.31#ibcon#read 5, iclass 14, count 2 2006.201.16:36:01.31#ibcon#about to read 6, iclass 14, count 2 2006.201.16:36:01.31#ibcon#read 6, iclass 14, count 2 2006.201.16:36:01.31#ibcon#end of sib2, iclass 14, count 2 2006.201.16:36:01.31#ibcon#*mode == 0, iclass 14, count 2 2006.201.16:36:01.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.16:36:01.31#ibcon#[27=AT06-04\r\n] 2006.201.16:36:01.31#ibcon#*before write, iclass 14, count 2 2006.201.16:36:01.31#ibcon#enter sib2, iclass 14, count 2 2006.201.16:36:01.31#ibcon#flushed, iclass 14, count 2 2006.201.16:36:01.31#ibcon#about to write, iclass 14, count 2 2006.201.16:36:01.31#ibcon#wrote, iclass 14, count 2 2006.201.16:36:01.31#ibcon#about to read 3, iclass 14, count 2 2006.201.16:36:01.34#ibcon#read 3, iclass 14, count 2 2006.201.16:36:01.34#ibcon#about to read 4, iclass 14, count 2 2006.201.16:36:01.34#ibcon#read 4, iclass 14, count 2 2006.201.16:36:01.34#ibcon#about to read 5, iclass 14, count 2 2006.201.16:36:01.34#ibcon#read 5, iclass 14, count 2 2006.201.16:36:01.34#ibcon#about to read 6, iclass 14, count 2 2006.201.16:36:01.34#ibcon#read 6, iclass 14, count 2 2006.201.16:36:01.34#ibcon#end of sib2, iclass 14, count 2 2006.201.16:36:01.34#ibcon#*after write, iclass 14, count 2 2006.201.16:36:01.34#ibcon#*before return 0, iclass 14, count 2 2006.201.16:36:01.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:36:01.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:36:01.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.16:36:01.34#ibcon#ireg 7 cls_cnt 0 2006.201.16:36:01.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:36:01.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:36:01.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:36:01.46#ibcon#enter wrdev, iclass 14, count 0 2006.201.16:36:01.46#ibcon#first serial, iclass 14, count 0 2006.201.16:36:01.46#ibcon#enter sib2, iclass 14, count 0 2006.201.16:36:01.46#ibcon#flushed, iclass 14, count 0 2006.201.16:36:01.46#ibcon#about to write, iclass 14, count 0 2006.201.16:36:01.46#ibcon#wrote, iclass 14, count 0 2006.201.16:36:01.46#ibcon#about to read 3, iclass 14, count 0 2006.201.16:36:01.48#ibcon#read 3, iclass 14, count 0 2006.201.16:36:01.48#ibcon#about to read 4, iclass 14, count 0 2006.201.16:36:01.48#ibcon#read 4, iclass 14, count 0 2006.201.16:36:01.48#ibcon#about to read 5, iclass 14, count 0 2006.201.16:36:01.48#ibcon#read 5, iclass 14, count 0 2006.201.16:36:01.48#ibcon#about to read 6, iclass 14, count 0 2006.201.16:36:01.48#ibcon#read 6, iclass 14, count 0 2006.201.16:36:01.48#ibcon#end of sib2, iclass 14, count 0 2006.201.16:36:01.48#ibcon#*mode == 0, iclass 14, count 0 2006.201.16:36:01.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.16:36:01.48#ibcon#[27=USB\r\n] 2006.201.16:36:01.48#ibcon#*before write, iclass 14, count 0 2006.201.16:36:01.48#ibcon#enter sib2, iclass 14, count 0 2006.201.16:36:01.48#ibcon#flushed, iclass 14, count 0 2006.201.16:36:01.48#ibcon#about to write, iclass 14, count 0 2006.201.16:36:01.48#ibcon#wrote, iclass 14, count 0 2006.201.16:36:01.48#ibcon#about to read 3, iclass 14, count 0 2006.201.16:36:01.51#ibcon#read 3, iclass 14, count 0 2006.201.16:36:01.51#ibcon#about to read 4, iclass 14, count 0 2006.201.16:36:01.51#ibcon#read 4, iclass 14, count 0 2006.201.16:36:01.51#ibcon#about to read 5, iclass 14, count 0 2006.201.16:36:01.51#ibcon#read 5, iclass 14, count 0 2006.201.16:36:01.51#ibcon#about to read 6, iclass 14, count 0 2006.201.16:36:01.51#ibcon#read 6, iclass 14, count 0 2006.201.16:36:01.51#ibcon#end of sib2, iclass 14, count 0 2006.201.16:36:01.51#ibcon#*after write, iclass 14, count 0 2006.201.16:36:01.51#ibcon#*before return 0, iclass 14, count 0 2006.201.16:36:01.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:36:01.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:36:01.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.16:36:01.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.16:36:01.51$vck44/vblo=7,734.99 2006.201.16:36:01.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.16:36:01.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.16:36:01.51#ibcon#ireg 17 cls_cnt 0 2006.201.16:36:01.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:36:01.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:36:01.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:36:01.51#ibcon#enter wrdev, iclass 16, count 0 2006.201.16:36:01.51#ibcon#first serial, iclass 16, count 0 2006.201.16:36:01.51#ibcon#enter sib2, iclass 16, count 0 2006.201.16:36:01.51#ibcon#flushed, iclass 16, count 0 2006.201.16:36:01.51#ibcon#about to write, iclass 16, count 0 2006.201.16:36:01.51#ibcon#wrote, iclass 16, count 0 2006.201.16:36:01.51#ibcon#about to read 3, iclass 16, count 0 2006.201.16:36:01.53#ibcon#read 3, iclass 16, count 0 2006.201.16:36:01.53#ibcon#about to read 4, iclass 16, count 0 2006.201.16:36:01.53#ibcon#read 4, iclass 16, count 0 2006.201.16:36:01.53#ibcon#about to read 5, iclass 16, count 0 2006.201.16:36:01.53#ibcon#read 5, iclass 16, count 0 2006.201.16:36:01.53#ibcon#about to read 6, iclass 16, count 0 2006.201.16:36:01.53#ibcon#read 6, iclass 16, count 0 2006.201.16:36:01.53#ibcon#end of sib2, iclass 16, count 0 2006.201.16:36:01.53#ibcon#*mode == 0, iclass 16, count 0 2006.201.16:36:01.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.16:36:01.53#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:36:01.53#ibcon#*before write, iclass 16, count 0 2006.201.16:36:01.53#ibcon#enter sib2, iclass 16, count 0 2006.201.16:36:01.53#ibcon#flushed, iclass 16, count 0 2006.201.16:36:01.53#ibcon#about to write, iclass 16, count 0 2006.201.16:36:01.53#ibcon#wrote, iclass 16, count 0 2006.201.16:36:01.53#ibcon#about to read 3, iclass 16, count 0 2006.201.16:36:01.57#ibcon#read 3, iclass 16, count 0 2006.201.16:36:01.57#ibcon#about to read 4, iclass 16, count 0 2006.201.16:36:01.57#ibcon#read 4, iclass 16, count 0 2006.201.16:36:01.57#ibcon#about to read 5, iclass 16, count 0 2006.201.16:36:01.57#ibcon#read 5, iclass 16, count 0 2006.201.16:36:01.57#ibcon#about to read 6, iclass 16, count 0 2006.201.16:36:01.57#ibcon#read 6, iclass 16, count 0 2006.201.16:36:01.57#ibcon#end of sib2, iclass 16, count 0 2006.201.16:36:01.57#ibcon#*after write, iclass 16, count 0 2006.201.16:36:01.57#ibcon#*before return 0, iclass 16, count 0 2006.201.16:36:01.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:36:01.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:36:01.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.16:36:01.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.16:36:01.57$vck44/vb=7,4 2006.201.16:36:01.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.16:36:01.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.16:36:01.57#ibcon#ireg 11 cls_cnt 2 2006.201.16:36:01.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:36:01.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:36:01.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:36:01.63#ibcon#enter wrdev, iclass 18, count 2 2006.201.16:36:01.63#ibcon#first serial, iclass 18, count 2 2006.201.16:36:01.63#ibcon#enter sib2, iclass 18, count 2 2006.201.16:36:01.63#ibcon#flushed, iclass 18, count 2 2006.201.16:36:01.63#ibcon#about to write, iclass 18, count 2 2006.201.16:36:01.63#ibcon#wrote, iclass 18, count 2 2006.201.16:36:01.63#ibcon#about to read 3, iclass 18, count 2 2006.201.16:36:01.65#ibcon#read 3, iclass 18, count 2 2006.201.16:36:01.65#ibcon#about to read 4, iclass 18, count 2 2006.201.16:36:01.65#ibcon#read 4, iclass 18, count 2 2006.201.16:36:01.65#ibcon#about to read 5, iclass 18, count 2 2006.201.16:36:01.65#ibcon#read 5, iclass 18, count 2 2006.201.16:36:01.65#ibcon#about to read 6, iclass 18, count 2 2006.201.16:36:01.65#ibcon#read 6, iclass 18, count 2 2006.201.16:36:01.65#ibcon#end of sib2, iclass 18, count 2 2006.201.16:36:01.65#ibcon#*mode == 0, iclass 18, count 2 2006.201.16:36:01.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.16:36:01.65#ibcon#[27=AT07-04\r\n] 2006.201.16:36:01.65#ibcon#*before write, iclass 18, count 2 2006.201.16:36:01.65#ibcon#enter sib2, iclass 18, count 2 2006.201.16:36:01.65#ibcon#flushed, iclass 18, count 2 2006.201.16:36:01.65#ibcon#about to write, iclass 18, count 2 2006.201.16:36:01.65#ibcon#wrote, iclass 18, count 2 2006.201.16:36:01.65#ibcon#about to read 3, iclass 18, count 2 2006.201.16:36:01.68#ibcon#read 3, iclass 18, count 2 2006.201.16:36:01.68#ibcon#about to read 4, iclass 18, count 2 2006.201.16:36:01.68#ibcon#read 4, iclass 18, count 2 2006.201.16:36:01.68#ibcon#about to read 5, iclass 18, count 2 2006.201.16:36:01.68#ibcon#read 5, iclass 18, count 2 2006.201.16:36:01.68#ibcon#about to read 6, iclass 18, count 2 2006.201.16:36:01.68#ibcon#read 6, iclass 18, count 2 2006.201.16:36:01.68#ibcon#end of sib2, iclass 18, count 2 2006.201.16:36:01.68#ibcon#*after write, iclass 18, count 2 2006.201.16:36:01.68#ibcon#*before return 0, iclass 18, count 2 2006.201.16:36:01.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:36:01.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:36:01.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.16:36:01.68#ibcon#ireg 7 cls_cnt 0 2006.201.16:36:01.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:36:01.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:36:01.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:36:01.80#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:36:01.80#ibcon#first serial, iclass 18, count 0 2006.201.16:36:01.80#ibcon#enter sib2, iclass 18, count 0 2006.201.16:36:01.80#ibcon#flushed, iclass 18, count 0 2006.201.16:36:01.80#ibcon#about to write, iclass 18, count 0 2006.201.16:36:01.80#ibcon#wrote, iclass 18, count 0 2006.201.16:36:01.80#ibcon#about to read 3, iclass 18, count 0 2006.201.16:36:01.82#ibcon#read 3, iclass 18, count 0 2006.201.16:36:01.82#ibcon#about to read 4, iclass 18, count 0 2006.201.16:36:01.82#ibcon#read 4, iclass 18, count 0 2006.201.16:36:01.82#ibcon#about to read 5, iclass 18, count 0 2006.201.16:36:01.82#ibcon#read 5, iclass 18, count 0 2006.201.16:36:01.82#ibcon#about to read 6, iclass 18, count 0 2006.201.16:36:01.82#ibcon#read 6, iclass 18, count 0 2006.201.16:36:01.82#ibcon#end of sib2, iclass 18, count 0 2006.201.16:36:01.82#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:36:01.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:36:01.82#ibcon#[27=USB\r\n] 2006.201.16:36:01.82#ibcon#*before write, iclass 18, count 0 2006.201.16:36:01.82#ibcon#enter sib2, iclass 18, count 0 2006.201.16:36:01.82#ibcon#flushed, iclass 18, count 0 2006.201.16:36:01.82#ibcon#about to write, iclass 18, count 0 2006.201.16:36:01.82#ibcon#wrote, iclass 18, count 0 2006.201.16:36:01.82#ibcon#about to read 3, iclass 18, count 0 2006.201.16:36:01.85#ibcon#read 3, iclass 18, count 0 2006.201.16:36:01.85#ibcon#about to read 4, iclass 18, count 0 2006.201.16:36:01.85#ibcon#read 4, iclass 18, count 0 2006.201.16:36:01.85#ibcon#about to read 5, iclass 18, count 0 2006.201.16:36:01.85#ibcon#read 5, iclass 18, count 0 2006.201.16:36:01.85#ibcon#about to read 6, iclass 18, count 0 2006.201.16:36:01.85#ibcon#read 6, iclass 18, count 0 2006.201.16:36:01.85#ibcon#end of sib2, iclass 18, count 0 2006.201.16:36:01.85#ibcon#*after write, iclass 18, count 0 2006.201.16:36:01.85#ibcon#*before return 0, iclass 18, count 0 2006.201.16:36:01.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:36:01.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:36:01.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:36:01.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:36:01.85$vck44/vblo=8,744.99 2006.201.16:36:01.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.16:36:01.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.16:36:01.85#ibcon#ireg 17 cls_cnt 0 2006.201.16:36:01.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:36:01.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:36:01.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:36:01.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:36:01.85#ibcon#first serial, iclass 20, count 0 2006.201.16:36:01.85#ibcon#enter sib2, iclass 20, count 0 2006.201.16:36:01.85#ibcon#flushed, iclass 20, count 0 2006.201.16:36:01.85#ibcon#about to write, iclass 20, count 0 2006.201.16:36:01.85#ibcon#wrote, iclass 20, count 0 2006.201.16:36:01.85#ibcon#about to read 3, iclass 20, count 0 2006.201.16:36:01.87#ibcon#read 3, iclass 20, count 0 2006.201.16:36:01.87#ibcon#about to read 4, iclass 20, count 0 2006.201.16:36:01.87#ibcon#read 4, iclass 20, count 0 2006.201.16:36:01.87#ibcon#about to read 5, iclass 20, count 0 2006.201.16:36:01.87#ibcon#read 5, iclass 20, count 0 2006.201.16:36:01.87#ibcon#about to read 6, iclass 20, count 0 2006.201.16:36:01.87#ibcon#read 6, iclass 20, count 0 2006.201.16:36:01.87#ibcon#end of sib2, iclass 20, count 0 2006.201.16:36:01.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:36:01.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:36:01.87#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:36:01.87#ibcon#*before write, iclass 20, count 0 2006.201.16:36:01.87#ibcon#enter sib2, iclass 20, count 0 2006.201.16:36:01.87#ibcon#flushed, iclass 20, count 0 2006.201.16:36:01.87#ibcon#about to write, iclass 20, count 0 2006.201.16:36:01.87#ibcon#wrote, iclass 20, count 0 2006.201.16:36:01.87#ibcon#about to read 3, iclass 20, count 0 2006.201.16:36:01.91#ibcon#read 3, iclass 20, count 0 2006.201.16:36:01.91#ibcon#about to read 4, iclass 20, count 0 2006.201.16:36:01.91#ibcon#read 4, iclass 20, count 0 2006.201.16:36:01.91#ibcon#about to read 5, iclass 20, count 0 2006.201.16:36:01.91#ibcon#read 5, iclass 20, count 0 2006.201.16:36:01.91#ibcon#about to read 6, iclass 20, count 0 2006.201.16:36:01.91#ibcon#read 6, iclass 20, count 0 2006.201.16:36:01.91#ibcon#end of sib2, iclass 20, count 0 2006.201.16:36:01.91#ibcon#*after write, iclass 20, count 0 2006.201.16:36:01.91#ibcon#*before return 0, iclass 20, count 0 2006.201.16:36:01.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:36:01.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:36:01.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:36:01.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:36:01.91$vck44/vb=8,4 2006.201.16:36:01.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.16:36:01.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.16:36:01.91#ibcon#ireg 11 cls_cnt 2 2006.201.16:36:01.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:36:01.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:36:01.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:36:01.97#ibcon#enter wrdev, iclass 22, count 2 2006.201.16:36:01.97#ibcon#first serial, iclass 22, count 2 2006.201.16:36:01.97#ibcon#enter sib2, iclass 22, count 2 2006.201.16:36:01.97#ibcon#flushed, iclass 22, count 2 2006.201.16:36:01.97#ibcon#about to write, iclass 22, count 2 2006.201.16:36:01.97#ibcon#wrote, iclass 22, count 2 2006.201.16:36:01.97#ibcon#about to read 3, iclass 22, count 2 2006.201.16:36:01.99#ibcon#read 3, iclass 22, count 2 2006.201.16:36:01.99#ibcon#about to read 4, iclass 22, count 2 2006.201.16:36:01.99#ibcon#read 4, iclass 22, count 2 2006.201.16:36:01.99#ibcon#about to read 5, iclass 22, count 2 2006.201.16:36:01.99#ibcon#read 5, iclass 22, count 2 2006.201.16:36:01.99#ibcon#about to read 6, iclass 22, count 2 2006.201.16:36:01.99#ibcon#read 6, iclass 22, count 2 2006.201.16:36:01.99#ibcon#end of sib2, iclass 22, count 2 2006.201.16:36:01.99#ibcon#*mode == 0, iclass 22, count 2 2006.201.16:36:01.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.16:36:01.99#ibcon#[27=AT08-04\r\n] 2006.201.16:36:01.99#ibcon#*before write, iclass 22, count 2 2006.201.16:36:01.99#ibcon#enter sib2, iclass 22, count 2 2006.201.16:36:01.99#ibcon#flushed, iclass 22, count 2 2006.201.16:36:01.99#ibcon#about to write, iclass 22, count 2 2006.201.16:36:01.99#ibcon#wrote, iclass 22, count 2 2006.201.16:36:01.99#ibcon#about to read 3, iclass 22, count 2 2006.201.16:36:02.02#ibcon#read 3, iclass 22, count 2 2006.201.16:36:02.02#ibcon#about to read 4, iclass 22, count 2 2006.201.16:36:02.02#ibcon#read 4, iclass 22, count 2 2006.201.16:36:02.02#ibcon#about to read 5, iclass 22, count 2 2006.201.16:36:02.02#ibcon#read 5, iclass 22, count 2 2006.201.16:36:02.02#ibcon#about to read 6, iclass 22, count 2 2006.201.16:36:02.02#ibcon#read 6, iclass 22, count 2 2006.201.16:36:02.02#ibcon#end of sib2, iclass 22, count 2 2006.201.16:36:02.02#ibcon#*after write, iclass 22, count 2 2006.201.16:36:02.02#ibcon#*before return 0, iclass 22, count 2 2006.201.16:36:02.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:36:02.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:36:02.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.16:36:02.02#ibcon#ireg 7 cls_cnt 0 2006.201.16:36:02.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:36:02.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:36:02.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:36:02.14#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:36:02.14#ibcon#first serial, iclass 22, count 0 2006.201.16:36:02.14#ibcon#enter sib2, iclass 22, count 0 2006.201.16:36:02.14#ibcon#flushed, iclass 22, count 0 2006.201.16:36:02.14#ibcon#about to write, iclass 22, count 0 2006.201.16:36:02.14#ibcon#wrote, iclass 22, count 0 2006.201.16:36:02.14#ibcon#about to read 3, iclass 22, count 0 2006.201.16:36:02.16#ibcon#read 3, iclass 22, count 0 2006.201.16:36:02.16#ibcon#about to read 4, iclass 22, count 0 2006.201.16:36:02.16#ibcon#read 4, iclass 22, count 0 2006.201.16:36:02.16#ibcon#about to read 5, iclass 22, count 0 2006.201.16:36:02.16#ibcon#read 5, iclass 22, count 0 2006.201.16:36:02.16#ibcon#about to read 6, iclass 22, count 0 2006.201.16:36:02.16#ibcon#read 6, iclass 22, count 0 2006.201.16:36:02.16#ibcon#end of sib2, iclass 22, count 0 2006.201.16:36:02.16#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:36:02.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:36:02.16#ibcon#[27=USB\r\n] 2006.201.16:36:02.16#ibcon#*before write, iclass 22, count 0 2006.201.16:36:02.16#ibcon#enter sib2, iclass 22, count 0 2006.201.16:36:02.16#ibcon#flushed, iclass 22, count 0 2006.201.16:36:02.16#ibcon#about to write, iclass 22, count 0 2006.201.16:36:02.16#ibcon#wrote, iclass 22, count 0 2006.201.16:36:02.16#ibcon#about to read 3, iclass 22, count 0 2006.201.16:36:02.19#ibcon#read 3, iclass 22, count 0 2006.201.16:36:02.19#ibcon#about to read 4, iclass 22, count 0 2006.201.16:36:02.19#ibcon#read 4, iclass 22, count 0 2006.201.16:36:02.19#ibcon#about to read 5, iclass 22, count 0 2006.201.16:36:02.19#ibcon#read 5, iclass 22, count 0 2006.201.16:36:02.19#ibcon#about to read 6, iclass 22, count 0 2006.201.16:36:02.19#ibcon#read 6, iclass 22, count 0 2006.201.16:36:02.19#ibcon#end of sib2, iclass 22, count 0 2006.201.16:36:02.19#ibcon#*after write, iclass 22, count 0 2006.201.16:36:02.19#ibcon#*before return 0, iclass 22, count 0 2006.201.16:36:02.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:36:02.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:36:02.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:36:02.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:36:02.19$vck44/vabw=wide 2006.201.16:36:02.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.16:36:02.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.16:36:02.19#ibcon#ireg 8 cls_cnt 0 2006.201.16:36:02.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:36:02.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:36:02.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:36:02.19#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:36:02.19#ibcon#first serial, iclass 24, count 0 2006.201.16:36:02.19#ibcon#enter sib2, iclass 24, count 0 2006.201.16:36:02.19#ibcon#flushed, iclass 24, count 0 2006.201.16:36:02.19#ibcon#about to write, iclass 24, count 0 2006.201.16:36:02.19#ibcon#wrote, iclass 24, count 0 2006.201.16:36:02.19#ibcon#about to read 3, iclass 24, count 0 2006.201.16:36:02.21#ibcon#read 3, iclass 24, count 0 2006.201.16:36:02.21#ibcon#about to read 4, iclass 24, count 0 2006.201.16:36:02.21#ibcon#read 4, iclass 24, count 0 2006.201.16:36:02.21#ibcon#about to read 5, iclass 24, count 0 2006.201.16:36:02.21#ibcon#read 5, iclass 24, count 0 2006.201.16:36:02.21#ibcon#about to read 6, iclass 24, count 0 2006.201.16:36:02.21#ibcon#read 6, iclass 24, count 0 2006.201.16:36:02.21#ibcon#end of sib2, iclass 24, count 0 2006.201.16:36:02.21#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:36:02.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:36:02.21#ibcon#[25=BW32\r\n] 2006.201.16:36:02.21#ibcon#*before write, iclass 24, count 0 2006.201.16:36:02.21#ibcon#enter sib2, iclass 24, count 0 2006.201.16:36:02.21#ibcon#flushed, iclass 24, count 0 2006.201.16:36:02.21#ibcon#about to write, iclass 24, count 0 2006.201.16:36:02.21#ibcon#wrote, iclass 24, count 0 2006.201.16:36:02.21#ibcon#about to read 3, iclass 24, count 0 2006.201.16:36:02.24#ibcon#read 3, iclass 24, count 0 2006.201.16:36:02.24#ibcon#about to read 4, iclass 24, count 0 2006.201.16:36:02.24#ibcon#read 4, iclass 24, count 0 2006.201.16:36:02.24#ibcon#about to read 5, iclass 24, count 0 2006.201.16:36:02.24#ibcon#read 5, iclass 24, count 0 2006.201.16:36:02.24#ibcon#about to read 6, iclass 24, count 0 2006.201.16:36:02.24#ibcon#read 6, iclass 24, count 0 2006.201.16:36:02.24#ibcon#end of sib2, iclass 24, count 0 2006.201.16:36:02.24#ibcon#*after write, iclass 24, count 0 2006.201.16:36:02.24#ibcon#*before return 0, iclass 24, count 0 2006.201.16:36:02.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:36:02.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:36:02.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:36:02.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:36:02.24$vck44/vbbw=wide 2006.201.16:36:02.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.16:36:02.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.16:36:02.24#ibcon#ireg 8 cls_cnt 0 2006.201.16:36:02.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:36:02.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:36:02.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:36:02.31#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:36:02.31#ibcon#first serial, iclass 26, count 0 2006.201.16:36:02.31#ibcon#enter sib2, iclass 26, count 0 2006.201.16:36:02.31#ibcon#flushed, iclass 26, count 0 2006.201.16:36:02.31#ibcon#about to write, iclass 26, count 0 2006.201.16:36:02.31#ibcon#wrote, iclass 26, count 0 2006.201.16:36:02.31#ibcon#about to read 3, iclass 26, count 0 2006.201.16:36:02.33#ibcon#read 3, iclass 26, count 0 2006.201.16:36:02.33#ibcon#about to read 4, iclass 26, count 0 2006.201.16:36:02.33#ibcon#read 4, iclass 26, count 0 2006.201.16:36:02.33#ibcon#about to read 5, iclass 26, count 0 2006.201.16:36:02.33#ibcon#read 5, iclass 26, count 0 2006.201.16:36:02.33#ibcon#about to read 6, iclass 26, count 0 2006.201.16:36:02.33#ibcon#read 6, iclass 26, count 0 2006.201.16:36:02.33#ibcon#end of sib2, iclass 26, count 0 2006.201.16:36:02.33#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:36:02.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:36:02.33#ibcon#[27=BW32\r\n] 2006.201.16:36:02.33#ibcon#*before write, iclass 26, count 0 2006.201.16:36:02.33#ibcon#enter sib2, iclass 26, count 0 2006.201.16:36:02.33#ibcon#flushed, iclass 26, count 0 2006.201.16:36:02.33#ibcon#about to write, iclass 26, count 0 2006.201.16:36:02.33#ibcon#wrote, iclass 26, count 0 2006.201.16:36:02.33#ibcon#about to read 3, iclass 26, count 0 2006.201.16:36:02.36#ibcon#read 3, iclass 26, count 0 2006.201.16:36:02.36#ibcon#about to read 4, iclass 26, count 0 2006.201.16:36:02.36#ibcon#read 4, iclass 26, count 0 2006.201.16:36:02.36#ibcon#about to read 5, iclass 26, count 0 2006.201.16:36:02.36#ibcon#read 5, iclass 26, count 0 2006.201.16:36:02.36#ibcon#about to read 6, iclass 26, count 0 2006.201.16:36:02.36#ibcon#read 6, iclass 26, count 0 2006.201.16:36:02.36#ibcon#end of sib2, iclass 26, count 0 2006.201.16:36:02.36#ibcon#*after write, iclass 26, count 0 2006.201.16:36:02.36#ibcon#*before return 0, iclass 26, count 0 2006.201.16:36:02.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:36:02.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:36:02.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:36:02.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:36:02.36$setupk4/ifdk4 2006.201.16:36:02.36$ifdk4/lo= 2006.201.16:36:02.36$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:36:02.36$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:36:02.36$ifdk4/patch= 2006.201.16:36:02.36$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:36:02.36$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:36:02.36$setupk4/!*+20s 2006.201.16:36:08.94#abcon#<5=/04 0.9 1.3 20.821001002.6\r\n> 2006.201.16:36:08.96#abcon#{5=INTERFACE CLEAR} 2006.201.16:36:09.02#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:36:16.84$setupk4/"tpicd 2006.201.16:36:16.84$setupk4/echo=off 2006.201.16:36:16.84$setupk4/xlog=off 2006.201.16:36:16.84:!2006.201.16:39:32 2006.201.16:36:21.14#trakl#Source acquired 2006.201.16:36:22.14#flagr#flagr/antenna,acquired 2006.201.16:39:32.00:preob 2006.201.16:39:32.14/onsource/TRACKING 2006.201.16:39:32.14:!2006.201.16:39:42 2006.201.16:39:42.00:"tape 2006.201.16:39:42.00:"st=record 2006.201.16:39:42.00:data_valid=on 2006.201.16:39:42.00:midob 2006.201.16:39:43.14/onsource/TRACKING 2006.201.16:39:43.14/wx/20.84,1002.7,100 2006.201.16:39:43.36/cable/+6.4788E-03 2006.201.16:39:44.45/va/01,08,usb,yes,38,40 2006.201.16:39:44.45/va/02,07,usb,yes,41,42 2006.201.16:39:44.45/va/03,08,usb,yes,37,38 2006.201.16:39:44.45/va/04,07,usb,yes,42,44 2006.201.16:39:44.45/va/05,04,usb,yes,37,38 2006.201.16:39:44.45/va/06,05,usb,yes,37,37 2006.201.16:39:44.45/va/07,05,usb,yes,37,38 2006.201.16:39:44.45/va/08,04,usb,yes,36,43 2006.201.16:39:44.68/valo/01,524.99,yes,locked 2006.201.16:39:44.68/valo/02,534.99,yes,locked 2006.201.16:39:44.68/valo/03,564.99,yes,locked 2006.201.16:39:44.68/valo/04,624.99,yes,locked 2006.201.16:39:44.68/valo/05,734.99,yes,locked 2006.201.16:39:44.68/valo/06,814.99,yes,locked 2006.201.16:39:44.68/valo/07,864.99,yes,locked 2006.201.16:39:44.68/valo/08,884.99,yes,locked 2006.201.16:39:45.77/vb/01,04,usb,yes,31,28 2006.201.16:39:45.77/vb/02,05,usb,yes,29,29 2006.201.16:39:45.77/vb/03,04,usb,yes,30,33 2006.201.16:39:45.77/vb/04,05,usb,yes,30,29 2006.201.16:39:45.77/vb/05,04,usb,yes,27,29 2006.201.16:39:45.77/vb/06,04,usb,yes,31,27 2006.201.16:39:45.77/vb/07,04,usb,yes,31,31 2006.201.16:39:45.77/vb/08,04,usb,yes,29,32 2006.201.16:39:46.00/vblo/01,629.99,yes,locked 2006.201.16:39:46.00/vblo/02,634.99,yes,locked 2006.201.16:39:46.00/vblo/03,649.99,yes,locked 2006.201.16:39:46.00/vblo/04,679.99,yes,locked 2006.201.16:39:46.00/vblo/05,709.99,yes,locked 2006.201.16:39:46.00/vblo/06,719.99,yes,locked 2006.201.16:39:46.00/vblo/07,734.99,yes,locked 2006.201.16:39:46.00/vblo/08,744.99,yes,locked 2006.201.16:39:46.15/vabw/8 2006.201.16:39:46.30/vbbw/8 2006.201.16:39:46.39/xfe/off,on,15.2 2006.201.16:39:46.76/ifatt/23,28,28,28 2006.201.16:39:47.06/fmout-gps/S +4.60E-07 2006.201.16:39:47.13:!2006.201.16:40:22 2006.201.16:40:22.00:data_valid=off 2006.201.16:40:22.00:"et 2006.201.16:40:22.00:!+3s 2006.201.16:40:25.02:"tape 2006.201.16:40:25.02:postob 2006.201.16:40:25.21/cable/+6.4768E-03 2006.201.16:40:25.21/wx/20.84,1002.7,100 2006.201.16:40:25.28/fmout-gps/S +4.60E-07 2006.201.16:40:25.28:scan_name=201-1641,jd0607,80 2006.201.16:40:25.28:source=1908-201,191109.65,-200655.1,2000.0,ccw 2006.201.16:40:27.14#flagr#flagr/antenna,new-source 2006.201.16:40:27.14:checkk5 2006.201.16:40:27.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:40:27.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:40:28.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:40:28.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:40:29.00/chk_obsdata//k5ts1/T2011639??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:40:29.36/chk_obsdata//k5ts2/T2011639??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:40:29.73/chk_obsdata//k5ts3/T2011639??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:40:30.10/chk_obsdata//k5ts4/T2011639??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:40:30.78/k5log//k5ts1_log_newline 2006.201.16:40:31.47/k5log//k5ts2_log_newline 2006.201.16:40:32.17/k5log//k5ts3_log_newline 2006.201.16:40:32.86/k5log//k5ts4_log_newline 2006.201.16:40:32.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:40:32.89:setupk4=1 2006.201.16:40:32.89$setupk4/echo=on 2006.201.16:40:32.89$setupk4/pcalon 2006.201.16:40:32.89$pcalon/"no phase cal control is implemented here 2006.201.16:40:32.89$setupk4/"tpicd=stop 2006.201.16:40:32.89$setupk4/"rec=synch_on 2006.201.16:40:32.89$setupk4/"rec_mode=128 2006.201.16:40:32.89$setupk4/!* 2006.201.16:40:32.89$setupk4/recpk4 2006.201.16:40:32.89$recpk4/recpatch= 2006.201.16:40:32.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:40:32.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:40:32.89$setupk4/vck44 2006.201.16:40:32.89$vck44/valo=1,524.99 2006.201.16:40:32.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.16:40:32.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.16:40:32.89#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:32.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:32.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:32.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:32.89#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:40:32.89#ibcon#first serial, iclass 27, count 0 2006.201.16:40:32.89#ibcon#enter sib2, iclass 27, count 0 2006.201.16:40:32.89#ibcon#flushed, iclass 27, count 0 2006.201.16:40:32.89#ibcon#about to write, iclass 27, count 0 2006.201.16:40:32.89#ibcon#wrote, iclass 27, count 0 2006.201.16:40:32.89#ibcon#about to read 3, iclass 27, count 0 2006.201.16:40:32.91#ibcon#read 3, iclass 27, count 0 2006.201.16:40:32.91#ibcon#about to read 4, iclass 27, count 0 2006.201.16:40:32.91#ibcon#read 4, iclass 27, count 0 2006.201.16:40:32.91#ibcon#about to read 5, iclass 27, count 0 2006.201.16:40:32.91#ibcon#read 5, iclass 27, count 0 2006.201.16:40:32.91#ibcon#about to read 6, iclass 27, count 0 2006.201.16:40:32.91#ibcon#read 6, iclass 27, count 0 2006.201.16:40:32.91#ibcon#end of sib2, iclass 27, count 0 2006.201.16:40:32.91#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:40:32.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:40:32.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:40:32.91#ibcon#*before write, iclass 27, count 0 2006.201.16:40:32.91#ibcon#enter sib2, iclass 27, count 0 2006.201.16:40:32.91#ibcon#flushed, iclass 27, count 0 2006.201.16:40:32.91#ibcon#about to write, iclass 27, count 0 2006.201.16:40:32.91#ibcon#wrote, iclass 27, count 0 2006.201.16:40:32.91#ibcon#about to read 3, iclass 27, count 0 2006.201.16:40:32.96#ibcon#read 3, iclass 27, count 0 2006.201.16:40:32.96#ibcon#about to read 4, iclass 27, count 0 2006.201.16:40:32.96#ibcon#read 4, iclass 27, count 0 2006.201.16:40:32.96#ibcon#about to read 5, iclass 27, count 0 2006.201.16:40:32.96#ibcon#read 5, iclass 27, count 0 2006.201.16:40:32.96#ibcon#about to read 6, iclass 27, count 0 2006.201.16:40:32.96#ibcon#read 6, iclass 27, count 0 2006.201.16:40:32.96#ibcon#end of sib2, iclass 27, count 0 2006.201.16:40:32.96#ibcon#*after write, iclass 27, count 0 2006.201.16:40:32.96#ibcon#*before return 0, iclass 27, count 0 2006.201.16:40:32.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:32.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:32.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:40:32.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:40:32.96$vck44/va=1,8 2006.201.16:40:32.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.16:40:32.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.16:40:32.96#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:32.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:32.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:32.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:32.96#ibcon#enter wrdev, iclass 29, count 2 2006.201.16:40:32.96#ibcon#first serial, iclass 29, count 2 2006.201.16:40:32.96#ibcon#enter sib2, iclass 29, count 2 2006.201.16:40:32.96#ibcon#flushed, iclass 29, count 2 2006.201.16:40:32.96#ibcon#about to write, iclass 29, count 2 2006.201.16:40:32.96#ibcon#wrote, iclass 29, count 2 2006.201.16:40:32.96#ibcon#about to read 3, iclass 29, count 2 2006.201.16:40:32.98#ibcon#read 3, iclass 29, count 2 2006.201.16:40:32.98#ibcon#about to read 4, iclass 29, count 2 2006.201.16:40:32.98#ibcon#read 4, iclass 29, count 2 2006.201.16:40:32.98#ibcon#about to read 5, iclass 29, count 2 2006.201.16:40:32.98#ibcon#read 5, iclass 29, count 2 2006.201.16:40:32.98#ibcon#about to read 6, iclass 29, count 2 2006.201.16:40:32.98#ibcon#read 6, iclass 29, count 2 2006.201.16:40:32.98#ibcon#end of sib2, iclass 29, count 2 2006.201.16:40:32.98#ibcon#*mode == 0, iclass 29, count 2 2006.201.16:40:32.98#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.16:40:32.98#ibcon#[25=AT01-08\r\n] 2006.201.16:40:32.98#ibcon#*before write, iclass 29, count 2 2006.201.16:40:32.98#ibcon#enter sib2, iclass 29, count 2 2006.201.16:40:32.98#ibcon#flushed, iclass 29, count 2 2006.201.16:40:32.98#ibcon#about to write, iclass 29, count 2 2006.201.16:40:32.98#ibcon#wrote, iclass 29, count 2 2006.201.16:40:32.98#ibcon#about to read 3, iclass 29, count 2 2006.201.16:40:33.01#ibcon#read 3, iclass 29, count 2 2006.201.16:40:33.01#ibcon#about to read 4, iclass 29, count 2 2006.201.16:40:33.01#ibcon#read 4, iclass 29, count 2 2006.201.16:40:33.01#ibcon#about to read 5, iclass 29, count 2 2006.201.16:40:33.01#ibcon#read 5, iclass 29, count 2 2006.201.16:40:33.01#ibcon#about to read 6, iclass 29, count 2 2006.201.16:40:33.01#ibcon#read 6, iclass 29, count 2 2006.201.16:40:33.01#ibcon#end of sib2, iclass 29, count 2 2006.201.16:40:33.01#ibcon#*after write, iclass 29, count 2 2006.201.16:40:33.01#ibcon#*before return 0, iclass 29, count 2 2006.201.16:40:33.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:33.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:33.01#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.16:40:33.01#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:33.01#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:33.13#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:33.13#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:33.13#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:40:33.13#ibcon#first serial, iclass 29, count 0 2006.201.16:40:33.13#ibcon#enter sib2, iclass 29, count 0 2006.201.16:40:33.13#ibcon#flushed, iclass 29, count 0 2006.201.16:40:33.13#ibcon#about to write, iclass 29, count 0 2006.201.16:40:33.13#ibcon#wrote, iclass 29, count 0 2006.201.16:40:33.13#ibcon#about to read 3, iclass 29, count 0 2006.201.16:40:33.15#ibcon#read 3, iclass 29, count 0 2006.201.16:40:33.15#ibcon#about to read 4, iclass 29, count 0 2006.201.16:40:33.15#ibcon#read 4, iclass 29, count 0 2006.201.16:40:33.15#ibcon#about to read 5, iclass 29, count 0 2006.201.16:40:33.15#ibcon#read 5, iclass 29, count 0 2006.201.16:40:33.15#ibcon#about to read 6, iclass 29, count 0 2006.201.16:40:33.15#ibcon#read 6, iclass 29, count 0 2006.201.16:40:33.15#ibcon#end of sib2, iclass 29, count 0 2006.201.16:40:33.15#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:40:33.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:40:33.15#ibcon#[25=USB\r\n] 2006.201.16:40:33.15#ibcon#*before write, iclass 29, count 0 2006.201.16:40:33.15#ibcon#enter sib2, iclass 29, count 0 2006.201.16:40:33.15#ibcon#flushed, iclass 29, count 0 2006.201.16:40:33.15#ibcon#about to write, iclass 29, count 0 2006.201.16:40:33.15#ibcon#wrote, iclass 29, count 0 2006.201.16:40:33.15#ibcon#about to read 3, iclass 29, count 0 2006.201.16:40:33.18#ibcon#read 3, iclass 29, count 0 2006.201.16:40:33.18#ibcon#about to read 4, iclass 29, count 0 2006.201.16:40:33.18#ibcon#read 4, iclass 29, count 0 2006.201.16:40:33.18#ibcon#about to read 5, iclass 29, count 0 2006.201.16:40:33.18#ibcon#read 5, iclass 29, count 0 2006.201.16:40:33.18#ibcon#about to read 6, iclass 29, count 0 2006.201.16:40:33.18#ibcon#read 6, iclass 29, count 0 2006.201.16:40:33.18#ibcon#end of sib2, iclass 29, count 0 2006.201.16:40:33.18#ibcon#*after write, iclass 29, count 0 2006.201.16:40:33.18#ibcon#*before return 0, iclass 29, count 0 2006.201.16:40:33.18#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:33.18#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:33.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:40:33.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:40:33.18$vck44/valo=2,534.99 2006.201.16:40:33.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.16:40:33.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.16:40:33.18#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:33.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:33.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:33.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:33.18#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:40:33.18#ibcon#first serial, iclass 31, count 0 2006.201.16:40:33.18#ibcon#enter sib2, iclass 31, count 0 2006.201.16:40:33.18#ibcon#flushed, iclass 31, count 0 2006.201.16:40:33.18#ibcon#about to write, iclass 31, count 0 2006.201.16:40:33.18#ibcon#wrote, iclass 31, count 0 2006.201.16:40:33.18#ibcon#about to read 3, iclass 31, count 0 2006.201.16:40:33.20#ibcon#read 3, iclass 31, count 0 2006.201.16:40:33.20#ibcon#about to read 4, iclass 31, count 0 2006.201.16:40:33.20#ibcon#read 4, iclass 31, count 0 2006.201.16:40:33.20#ibcon#about to read 5, iclass 31, count 0 2006.201.16:40:33.20#ibcon#read 5, iclass 31, count 0 2006.201.16:40:33.20#ibcon#about to read 6, iclass 31, count 0 2006.201.16:40:33.20#ibcon#read 6, iclass 31, count 0 2006.201.16:40:33.20#ibcon#end of sib2, iclass 31, count 0 2006.201.16:40:33.20#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:40:33.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:40:33.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:40:33.20#ibcon#*before write, iclass 31, count 0 2006.201.16:40:33.20#ibcon#enter sib2, iclass 31, count 0 2006.201.16:40:33.20#ibcon#flushed, iclass 31, count 0 2006.201.16:40:33.20#ibcon#about to write, iclass 31, count 0 2006.201.16:40:33.20#ibcon#wrote, iclass 31, count 0 2006.201.16:40:33.20#ibcon#about to read 3, iclass 31, count 0 2006.201.16:40:33.24#ibcon#read 3, iclass 31, count 0 2006.201.16:40:33.24#ibcon#about to read 4, iclass 31, count 0 2006.201.16:40:33.24#ibcon#read 4, iclass 31, count 0 2006.201.16:40:33.24#ibcon#about to read 5, iclass 31, count 0 2006.201.16:40:33.24#ibcon#read 5, iclass 31, count 0 2006.201.16:40:33.24#ibcon#about to read 6, iclass 31, count 0 2006.201.16:40:33.24#ibcon#read 6, iclass 31, count 0 2006.201.16:40:33.24#ibcon#end of sib2, iclass 31, count 0 2006.201.16:40:33.24#ibcon#*after write, iclass 31, count 0 2006.201.16:40:33.24#ibcon#*before return 0, iclass 31, count 0 2006.201.16:40:33.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:33.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:33.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:40:33.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:40:33.24$vck44/va=2,7 2006.201.16:40:33.24#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.16:40:33.24#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.16:40:33.24#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:33.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:33.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:33.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:33.30#ibcon#enter wrdev, iclass 33, count 2 2006.201.16:40:33.30#ibcon#first serial, iclass 33, count 2 2006.201.16:40:33.30#ibcon#enter sib2, iclass 33, count 2 2006.201.16:40:33.30#ibcon#flushed, iclass 33, count 2 2006.201.16:40:33.30#ibcon#about to write, iclass 33, count 2 2006.201.16:40:33.30#ibcon#wrote, iclass 33, count 2 2006.201.16:40:33.30#ibcon#about to read 3, iclass 33, count 2 2006.201.16:40:33.32#ibcon#read 3, iclass 33, count 2 2006.201.16:40:33.32#ibcon#about to read 4, iclass 33, count 2 2006.201.16:40:33.32#ibcon#read 4, iclass 33, count 2 2006.201.16:40:33.32#ibcon#about to read 5, iclass 33, count 2 2006.201.16:40:33.32#ibcon#read 5, iclass 33, count 2 2006.201.16:40:33.32#ibcon#about to read 6, iclass 33, count 2 2006.201.16:40:33.32#ibcon#read 6, iclass 33, count 2 2006.201.16:40:33.32#ibcon#end of sib2, iclass 33, count 2 2006.201.16:40:33.32#ibcon#*mode == 0, iclass 33, count 2 2006.201.16:40:33.32#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.16:40:33.32#ibcon#[25=AT02-07\r\n] 2006.201.16:40:33.32#ibcon#*before write, iclass 33, count 2 2006.201.16:40:33.32#ibcon#enter sib2, iclass 33, count 2 2006.201.16:40:33.32#ibcon#flushed, iclass 33, count 2 2006.201.16:40:33.32#ibcon#about to write, iclass 33, count 2 2006.201.16:40:33.32#ibcon#wrote, iclass 33, count 2 2006.201.16:40:33.32#ibcon#about to read 3, iclass 33, count 2 2006.201.16:40:33.35#ibcon#read 3, iclass 33, count 2 2006.201.16:40:33.35#ibcon#about to read 4, iclass 33, count 2 2006.201.16:40:33.35#ibcon#read 4, iclass 33, count 2 2006.201.16:40:33.35#ibcon#about to read 5, iclass 33, count 2 2006.201.16:40:33.35#ibcon#read 5, iclass 33, count 2 2006.201.16:40:33.35#ibcon#about to read 6, iclass 33, count 2 2006.201.16:40:33.35#ibcon#read 6, iclass 33, count 2 2006.201.16:40:33.35#ibcon#end of sib2, iclass 33, count 2 2006.201.16:40:33.35#ibcon#*after write, iclass 33, count 2 2006.201.16:40:33.35#ibcon#*before return 0, iclass 33, count 2 2006.201.16:40:33.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:33.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:33.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.16:40:33.35#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:33.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:33.36#abcon#<5=/04 0.6 1.3 20.841001002.7\r\n> 2006.201.16:40:33.38#abcon#{5=INTERFACE CLEAR} 2006.201.16:40:33.44#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:40:33.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:33.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:33.47#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:40:33.47#ibcon#first serial, iclass 33, count 0 2006.201.16:40:33.47#ibcon#enter sib2, iclass 33, count 0 2006.201.16:40:33.47#ibcon#flushed, iclass 33, count 0 2006.201.16:40:33.47#ibcon#about to write, iclass 33, count 0 2006.201.16:40:33.47#ibcon#wrote, iclass 33, count 0 2006.201.16:40:33.47#ibcon#about to read 3, iclass 33, count 0 2006.201.16:40:33.49#ibcon#read 3, iclass 33, count 0 2006.201.16:40:33.49#ibcon#about to read 4, iclass 33, count 0 2006.201.16:40:33.49#ibcon#read 4, iclass 33, count 0 2006.201.16:40:33.49#ibcon#about to read 5, iclass 33, count 0 2006.201.16:40:33.49#ibcon#read 5, iclass 33, count 0 2006.201.16:40:33.49#ibcon#about to read 6, iclass 33, count 0 2006.201.16:40:33.49#ibcon#read 6, iclass 33, count 0 2006.201.16:40:33.49#ibcon#end of sib2, iclass 33, count 0 2006.201.16:40:33.49#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:40:33.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:40:33.49#ibcon#[25=USB\r\n] 2006.201.16:40:33.49#ibcon#*before write, iclass 33, count 0 2006.201.16:40:33.49#ibcon#enter sib2, iclass 33, count 0 2006.201.16:40:33.49#ibcon#flushed, iclass 33, count 0 2006.201.16:40:33.49#ibcon#about to write, iclass 33, count 0 2006.201.16:40:33.49#ibcon#wrote, iclass 33, count 0 2006.201.16:40:33.49#ibcon#about to read 3, iclass 33, count 0 2006.201.16:40:33.52#ibcon#read 3, iclass 33, count 0 2006.201.16:40:33.52#ibcon#about to read 4, iclass 33, count 0 2006.201.16:40:33.52#ibcon#read 4, iclass 33, count 0 2006.201.16:40:33.52#ibcon#about to read 5, iclass 33, count 0 2006.201.16:40:33.52#ibcon#read 5, iclass 33, count 0 2006.201.16:40:33.52#ibcon#about to read 6, iclass 33, count 0 2006.201.16:40:33.52#ibcon#read 6, iclass 33, count 0 2006.201.16:40:33.52#ibcon#end of sib2, iclass 33, count 0 2006.201.16:40:33.52#ibcon#*after write, iclass 33, count 0 2006.201.16:40:33.52#ibcon#*before return 0, iclass 33, count 0 2006.201.16:40:33.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:33.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:33.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:40:33.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:40:33.52$vck44/valo=3,564.99 2006.201.16:40:33.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.16:40:33.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.16:40:33.52#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:33.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:33.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:33.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:33.52#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:40:33.52#ibcon#first serial, iclass 39, count 0 2006.201.16:40:33.52#ibcon#enter sib2, iclass 39, count 0 2006.201.16:40:33.52#ibcon#flushed, iclass 39, count 0 2006.201.16:40:33.52#ibcon#about to write, iclass 39, count 0 2006.201.16:40:33.52#ibcon#wrote, iclass 39, count 0 2006.201.16:40:33.52#ibcon#about to read 3, iclass 39, count 0 2006.201.16:40:33.54#ibcon#read 3, iclass 39, count 0 2006.201.16:40:33.54#ibcon#about to read 4, iclass 39, count 0 2006.201.16:40:33.54#ibcon#read 4, iclass 39, count 0 2006.201.16:40:33.54#ibcon#about to read 5, iclass 39, count 0 2006.201.16:40:33.54#ibcon#read 5, iclass 39, count 0 2006.201.16:40:33.54#ibcon#about to read 6, iclass 39, count 0 2006.201.16:40:33.54#ibcon#read 6, iclass 39, count 0 2006.201.16:40:33.54#ibcon#end of sib2, iclass 39, count 0 2006.201.16:40:33.54#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:40:33.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:40:33.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:40:33.54#ibcon#*before write, iclass 39, count 0 2006.201.16:40:33.54#ibcon#enter sib2, iclass 39, count 0 2006.201.16:40:33.54#ibcon#flushed, iclass 39, count 0 2006.201.16:40:33.54#ibcon#about to write, iclass 39, count 0 2006.201.16:40:33.54#ibcon#wrote, iclass 39, count 0 2006.201.16:40:33.54#ibcon#about to read 3, iclass 39, count 0 2006.201.16:40:33.59#ibcon#read 3, iclass 39, count 0 2006.201.16:40:33.59#ibcon#about to read 4, iclass 39, count 0 2006.201.16:40:33.59#ibcon#read 4, iclass 39, count 0 2006.201.16:40:33.59#ibcon#about to read 5, iclass 39, count 0 2006.201.16:40:33.59#ibcon#read 5, iclass 39, count 0 2006.201.16:40:33.59#ibcon#about to read 6, iclass 39, count 0 2006.201.16:40:33.59#ibcon#read 6, iclass 39, count 0 2006.201.16:40:33.59#ibcon#end of sib2, iclass 39, count 0 2006.201.16:40:33.59#ibcon#*after write, iclass 39, count 0 2006.201.16:40:33.59#ibcon#*before return 0, iclass 39, count 0 2006.201.16:40:33.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:33.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:33.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:40:33.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:40:33.59$vck44/va=3,8 2006.201.16:40:33.59#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.16:40:33.59#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.16:40:33.59#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:33.59#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:33.64#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:33.64#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:33.64#ibcon#enter wrdev, iclass 2, count 2 2006.201.16:40:33.64#ibcon#first serial, iclass 2, count 2 2006.201.16:40:33.64#ibcon#enter sib2, iclass 2, count 2 2006.201.16:40:33.64#ibcon#flushed, iclass 2, count 2 2006.201.16:40:33.64#ibcon#about to write, iclass 2, count 2 2006.201.16:40:33.64#ibcon#wrote, iclass 2, count 2 2006.201.16:40:33.64#ibcon#about to read 3, iclass 2, count 2 2006.201.16:40:33.66#ibcon#read 3, iclass 2, count 2 2006.201.16:40:33.66#ibcon#about to read 4, iclass 2, count 2 2006.201.16:40:33.66#ibcon#read 4, iclass 2, count 2 2006.201.16:40:33.66#ibcon#about to read 5, iclass 2, count 2 2006.201.16:40:33.66#ibcon#read 5, iclass 2, count 2 2006.201.16:40:33.66#ibcon#about to read 6, iclass 2, count 2 2006.201.16:40:33.66#ibcon#read 6, iclass 2, count 2 2006.201.16:40:33.66#ibcon#end of sib2, iclass 2, count 2 2006.201.16:40:33.66#ibcon#*mode == 0, iclass 2, count 2 2006.201.16:40:33.66#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.16:40:33.66#ibcon#[25=AT03-08\r\n] 2006.201.16:40:33.66#ibcon#*before write, iclass 2, count 2 2006.201.16:40:33.66#ibcon#enter sib2, iclass 2, count 2 2006.201.16:40:33.66#ibcon#flushed, iclass 2, count 2 2006.201.16:40:33.66#ibcon#about to write, iclass 2, count 2 2006.201.16:40:33.66#ibcon#wrote, iclass 2, count 2 2006.201.16:40:33.66#ibcon#about to read 3, iclass 2, count 2 2006.201.16:40:33.69#ibcon#read 3, iclass 2, count 2 2006.201.16:40:33.69#ibcon#about to read 4, iclass 2, count 2 2006.201.16:40:33.69#ibcon#read 4, iclass 2, count 2 2006.201.16:40:33.69#ibcon#about to read 5, iclass 2, count 2 2006.201.16:40:33.69#ibcon#read 5, iclass 2, count 2 2006.201.16:40:33.69#ibcon#about to read 6, iclass 2, count 2 2006.201.16:40:33.69#ibcon#read 6, iclass 2, count 2 2006.201.16:40:33.69#ibcon#end of sib2, iclass 2, count 2 2006.201.16:40:33.69#ibcon#*after write, iclass 2, count 2 2006.201.16:40:33.69#ibcon#*before return 0, iclass 2, count 2 2006.201.16:40:33.69#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:33.69#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:33.69#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.16:40:33.69#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:33.69#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:33.81#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:33.81#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:33.81#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:40:33.81#ibcon#first serial, iclass 2, count 0 2006.201.16:40:33.81#ibcon#enter sib2, iclass 2, count 0 2006.201.16:40:33.81#ibcon#flushed, iclass 2, count 0 2006.201.16:40:33.81#ibcon#about to write, iclass 2, count 0 2006.201.16:40:33.81#ibcon#wrote, iclass 2, count 0 2006.201.16:40:33.81#ibcon#about to read 3, iclass 2, count 0 2006.201.16:40:33.83#ibcon#read 3, iclass 2, count 0 2006.201.16:40:33.83#ibcon#about to read 4, iclass 2, count 0 2006.201.16:40:33.83#ibcon#read 4, iclass 2, count 0 2006.201.16:40:33.83#ibcon#about to read 5, iclass 2, count 0 2006.201.16:40:33.83#ibcon#read 5, iclass 2, count 0 2006.201.16:40:33.83#ibcon#about to read 6, iclass 2, count 0 2006.201.16:40:33.83#ibcon#read 6, iclass 2, count 0 2006.201.16:40:33.83#ibcon#end of sib2, iclass 2, count 0 2006.201.16:40:33.83#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:40:33.83#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:40:33.83#ibcon#[25=USB\r\n] 2006.201.16:40:33.83#ibcon#*before write, iclass 2, count 0 2006.201.16:40:33.83#ibcon#enter sib2, iclass 2, count 0 2006.201.16:40:33.83#ibcon#flushed, iclass 2, count 0 2006.201.16:40:33.83#ibcon#about to write, iclass 2, count 0 2006.201.16:40:33.83#ibcon#wrote, iclass 2, count 0 2006.201.16:40:33.83#ibcon#about to read 3, iclass 2, count 0 2006.201.16:40:33.86#ibcon#read 3, iclass 2, count 0 2006.201.16:40:33.86#ibcon#about to read 4, iclass 2, count 0 2006.201.16:40:33.86#ibcon#read 4, iclass 2, count 0 2006.201.16:40:33.86#ibcon#about to read 5, iclass 2, count 0 2006.201.16:40:33.86#ibcon#read 5, iclass 2, count 0 2006.201.16:40:33.86#ibcon#about to read 6, iclass 2, count 0 2006.201.16:40:33.86#ibcon#read 6, iclass 2, count 0 2006.201.16:40:33.86#ibcon#end of sib2, iclass 2, count 0 2006.201.16:40:33.86#ibcon#*after write, iclass 2, count 0 2006.201.16:40:33.86#ibcon#*before return 0, iclass 2, count 0 2006.201.16:40:33.86#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:33.86#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:33.86#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:40:33.86#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:40:33.86$vck44/valo=4,624.99 2006.201.16:40:33.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.16:40:33.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.16:40:33.86#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:33.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:33.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:33.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:33.86#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:40:33.86#ibcon#first serial, iclass 5, count 0 2006.201.16:40:33.86#ibcon#enter sib2, iclass 5, count 0 2006.201.16:40:33.86#ibcon#flushed, iclass 5, count 0 2006.201.16:40:33.86#ibcon#about to write, iclass 5, count 0 2006.201.16:40:33.86#ibcon#wrote, iclass 5, count 0 2006.201.16:40:33.86#ibcon#about to read 3, iclass 5, count 0 2006.201.16:40:33.88#ibcon#read 3, iclass 5, count 0 2006.201.16:40:33.88#ibcon#about to read 4, iclass 5, count 0 2006.201.16:40:33.88#ibcon#read 4, iclass 5, count 0 2006.201.16:40:33.88#ibcon#about to read 5, iclass 5, count 0 2006.201.16:40:33.88#ibcon#read 5, iclass 5, count 0 2006.201.16:40:33.88#ibcon#about to read 6, iclass 5, count 0 2006.201.16:40:33.88#ibcon#read 6, iclass 5, count 0 2006.201.16:40:33.88#ibcon#end of sib2, iclass 5, count 0 2006.201.16:40:33.88#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:40:33.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:40:33.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:40:33.88#ibcon#*before write, iclass 5, count 0 2006.201.16:40:33.88#ibcon#enter sib2, iclass 5, count 0 2006.201.16:40:33.88#ibcon#flushed, iclass 5, count 0 2006.201.16:40:33.88#ibcon#about to write, iclass 5, count 0 2006.201.16:40:33.88#ibcon#wrote, iclass 5, count 0 2006.201.16:40:33.88#ibcon#about to read 3, iclass 5, count 0 2006.201.16:40:33.92#ibcon#read 3, iclass 5, count 0 2006.201.16:40:33.92#ibcon#about to read 4, iclass 5, count 0 2006.201.16:40:33.92#ibcon#read 4, iclass 5, count 0 2006.201.16:40:33.92#ibcon#about to read 5, iclass 5, count 0 2006.201.16:40:33.92#ibcon#read 5, iclass 5, count 0 2006.201.16:40:33.92#ibcon#about to read 6, iclass 5, count 0 2006.201.16:40:33.92#ibcon#read 6, iclass 5, count 0 2006.201.16:40:33.92#ibcon#end of sib2, iclass 5, count 0 2006.201.16:40:33.92#ibcon#*after write, iclass 5, count 0 2006.201.16:40:33.92#ibcon#*before return 0, iclass 5, count 0 2006.201.16:40:33.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:33.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:33.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:40:33.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:40:33.92$vck44/va=4,7 2006.201.16:40:33.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.16:40:33.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.16:40:33.92#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:33.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:33.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:33.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:33.98#ibcon#enter wrdev, iclass 7, count 2 2006.201.16:40:33.98#ibcon#first serial, iclass 7, count 2 2006.201.16:40:33.98#ibcon#enter sib2, iclass 7, count 2 2006.201.16:40:33.98#ibcon#flushed, iclass 7, count 2 2006.201.16:40:33.98#ibcon#about to write, iclass 7, count 2 2006.201.16:40:33.98#ibcon#wrote, iclass 7, count 2 2006.201.16:40:33.98#ibcon#about to read 3, iclass 7, count 2 2006.201.16:40:34.00#ibcon#read 3, iclass 7, count 2 2006.201.16:40:34.00#ibcon#about to read 4, iclass 7, count 2 2006.201.16:40:34.00#ibcon#read 4, iclass 7, count 2 2006.201.16:40:34.00#ibcon#about to read 5, iclass 7, count 2 2006.201.16:40:34.00#ibcon#read 5, iclass 7, count 2 2006.201.16:40:34.00#ibcon#about to read 6, iclass 7, count 2 2006.201.16:40:34.00#ibcon#read 6, iclass 7, count 2 2006.201.16:40:34.00#ibcon#end of sib2, iclass 7, count 2 2006.201.16:40:34.00#ibcon#*mode == 0, iclass 7, count 2 2006.201.16:40:34.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.16:40:34.00#ibcon#[25=AT04-07\r\n] 2006.201.16:40:34.00#ibcon#*before write, iclass 7, count 2 2006.201.16:40:34.00#ibcon#enter sib2, iclass 7, count 2 2006.201.16:40:34.00#ibcon#flushed, iclass 7, count 2 2006.201.16:40:34.00#ibcon#about to write, iclass 7, count 2 2006.201.16:40:34.00#ibcon#wrote, iclass 7, count 2 2006.201.16:40:34.00#ibcon#about to read 3, iclass 7, count 2 2006.201.16:40:34.04#ibcon#read 3, iclass 7, count 2 2006.201.16:40:34.04#ibcon#about to read 4, iclass 7, count 2 2006.201.16:40:34.04#ibcon#read 4, iclass 7, count 2 2006.201.16:40:34.04#ibcon#about to read 5, iclass 7, count 2 2006.201.16:40:34.04#ibcon#read 5, iclass 7, count 2 2006.201.16:40:34.04#ibcon#about to read 6, iclass 7, count 2 2006.201.16:40:34.04#ibcon#read 6, iclass 7, count 2 2006.201.16:40:34.04#ibcon#end of sib2, iclass 7, count 2 2006.201.16:40:34.04#ibcon#*after write, iclass 7, count 2 2006.201.16:40:34.04#ibcon#*before return 0, iclass 7, count 2 2006.201.16:40:34.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:34.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:34.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.16:40:34.04#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:34.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:34.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:34.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:34.16#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:40:34.16#ibcon#first serial, iclass 7, count 0 2006.201.16:40:34.16#ibcon#enter sib2, iclass 7, count 0 2006.201.16:40:34.16#ibcon#flushed, iclass 7, count 0 2006.201.16:40:34.16#ibcon#about to write, iclass 7, count 0 2006.201.16:40:34.16#ibcon#wrote, iclass 7, count 0 2006.201.16:40:34.16#ibcon#about to read 3, iclass 7, count 0 2006.201.16:40:34.18#ibcon#read 3, iclass 7, count 0 2006.201.16:40:34.18#ibcon#about to read 4, iclass 7, count 0 2006.201.16:40:34.18#ibcon#read 4, iclass 7, count 0 2006.201.16:40:34.18#ibcon#about to read 5, iclass 7, count 0 2006.201.16:40:34.18#ibcon#read 5, iclass 7, count 0 2006.201.16:40:34.18#ibcon#about to read 6, iclass 7, count 0 2006.201.16:40:34.18#ibcon#read 6, iclass 7, count 0 2006.201.16:40:34.18#ibcon#end of sib2, iclass 7, count 0 2006.201.16:40:34.18#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:40:34.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:40:34.18#ibcon#[25=USB\r\n] 2006.201.16:40:34.18#ibcon#*before write, iclass 7, count 0 2006.201.16:40:34.18#ibcon#enter sib2, iclass 7, count 0 2006.201.16:40:34.18#ibcon#flushed, iclass 7, count 0 2006.201.16:40:34.18#ibcon#about to write, iclass 7, count 0 2006.201.16:40:34.18#ibcon#wrote, iclass 7, count 0 2006.201.16:40:34.18#ibcon#about to read 3, iclass 7, count 0 2006.201.16:40:34.21#ibcon#read 3, iclass 7, count 0 2006.201.16:40:34.21#ibcon#about to read 4, iclass 7, count 0 2006.201.16:40:34.21#ibcon#read 4, iclass 7, count 0 2006.201.16:40:34.21#ibcon#about to read 5, iclass 7, count 0 2006.201.16:40:34.21#ibcon#read 5, iclass 7, count 0 2006.201.16:40:34.21#ibcon#about to read 6, iclass 7, count 0 2006.201.16:40:34.21#ibcon#read 6, iclass 7, count 0 2006.201.16:40:34.21#ibcon#end of sib2, iclass 7, count 0 2006.201.16:40:34.21#ibcon#*after write, iclass 7, count 0 2006.201.16:40:34.21#ibcon#*before return 0, iclass 7, count 0 2006.201.16:40:34.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:34.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:34.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:40:34.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:40:34.21$vck44/valo=5,734.99 2006.201.16:40:34.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.16:40:34.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.16:40:34.21#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:34.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:34.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:34.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:34.21#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:40:34.21#ibcon#first serial, iclass 11, count 0 2006.201.16:40:34.21#ibcon#enter sib2, iclass 11, count 0 2006.201.16:40:34.21#ibcon#flushed, iclass 11, count 0 2006.201.16:40:34.21#ibcon#about to write, iclass 11, count 0 2006.201.16:40:34.21#ibcon#wrote, iclass 11, count 0 2006.201.16:40:34.21#ibcon#about to read 3, iclass 11, count 0 2006.201.16:40:34.23#ibcon#read 3, iclass 11, count 0 2006.201.16:40:34.23#ibcon#about to read 4, iclass 11, count 0 2006.201.16:40:34.23#ibcon#read 4, iclass 11, count 0 2006.201.16:40:34.23#ibcon#about to read 5, iclass 11, count 0 2006.201.16:40:34.23#ibcon#read 5, iclass 11, count 0 2006.201.16:40:34.23#ibcon#about to read 6, iclass 11, count 0 2006.201.16:40:34.23#ibcon#read 6, iclass 11, count 0 2006.201.16:40:34.23#ibcon#end of sib2, iclass 11, count 0 2006.201.16:40:34.23#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:40:34.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:40:34.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:40:34.23#ibcon#*before write, iclass 11, count 0 2006.201.16:40:34.23#ibcon#enter sib2, iclass 11, count 0 2006.201.16:40:34.23#ibcon#flushed, iclass 11, count 0 2006.201.16:40:34.23#ibcon#about to write, iclass 11, count 0 2006.201.16:40:34.23#ibcon#wrote, iclass 11, count 0 2006.201.16:40:34.23#ibcon#about to read 3, iclass 11, count 0 2006.201.16:40:34.27#ibcon#read 3, iclass 11, count 0 2006.201.16:40:34.27#ibcon#about to read 4, iclass 11, count 0 2006.201.16:40:34.27#ibcon#read 4, iclass 11, count 0 2006.201.16:40:34.27#ibcon#about to read 5, iclass 11, count 0 2006.201.16:40:34.27#ibcon#read 5, iclass 11, count 0 2006.201.16:40:34.27#ibcon#about to read 6, iclass 11, count 0 2006.201.16:40:34.27#ibcon#read 6, iclass 11, count 0 2006.201.16:40:34.27#ibcon#end of sib2, iclass 11, count 0 2006.201.16:40:34.27#ibcon#*after write, iclass 11, count 0 2006.201.16:40:34.27#ibcon#*before return 0, iclass 11, count 0 2006.201.16:40:34.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:34.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:34.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:40:34.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:40:34.27$vck44/va=5,4 2006.201.16:40:34.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.16:40:34.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.16:40:34.27#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:34.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:34.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:34.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:34.33#ibcon#enter wrdev, iclass 13, count 2 2006.201.16:40:34.33#ibcon#first serial, iclass 13, count 2 2006.201.16:40:34.33#ibcon#enter sib2, iclass 13, count 2 2006.201.16:40:34.33#ibcon#flushed, iclass 13, count 2 2006.201.16:40:34.33#ibcon#about to write, iclass 13, count 2 2006.201.16:40:34.33#ibcon#wrote, iclass 13, count 2 2006.201.16:40:34.33#ibcon#about to read 3, iclass 13, count 2 2006.201.16:40:34.35#ibcon#read 3, iclass 13, count 2 2006.201.16:40:34.35#ibcon#about to read 4, iclass 13, count 2 2006.201.16:40:34.35#ibcon#read 4, iclass 13, count 2 2006.201.16:40:34.35#ibcon#about to read 5, iclass 13, count 2 2006.201.16:40:34.35#ibcon#read 5, iclass 13, count 2 2006.201.16:40:34.35#ibcon#about to read 6, iclass 13, count 2 2006.201.16:40:34.35#ibcon#read 6, iclass 13, count 2 2006.201.16:40:34.35#ibcon#end of sib2, iclass 13, count 2 2006.201.16:40:34.35#ibcon#*mode == 0, iclass 13, count 2 2006.201.16:40:34.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.16:40:34.35#ibcon#[25=AT05-04\r\n] 2006.201.16:40:34.35#ibcon#*before write, iclass 13, count 2 2006.201.16:40:34.35#ibcon#enter sib2, iclass 13, count 2 2006.201.16:40:34.35#ibcon#flushed, iclass 13, count 2 2006.201.16:40:34.35#ibcon#about to write, iclass 13, count 2 2006.201.16:40:34.35#ibcon#wrote, iclass 13, count 2 2006.201.16:40:34.35#ibcon#about to read 3, iclass 13, count 2 2006.201.16:40:34.38#ibcon#read 3, iclass 13, count 2 2006.201.16:40:34.38#ibcon#about to read 4, iclass 13, count 2 2006.201.16:40:34.38#ibcon#read 4, iclass 13, count 2 2006.201.16:40:34.38#ibcon#about to read 5, iclass 13, count 2 2006.201.16:40:34.38#ibcon#read 5, iclass 13, count 2 2006.201.16:40:34.38#ibcon#about to read 6, iclass 13, count 2 2006.201.16:40:34.38#ibcon#read 6, iclass 13, count 2 2006.201.16:40:34.38#ibcon#end of sib2, iclass 13, count 2 2006.201.16:40:34.38#ibcon#*after write, iclass 13, count 2 2006.201.16:40:34.38#ibcon#*before return 0, iclass 13, count 2 2006.201.16:40:34.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:34.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:34.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.16:40:34.38#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:34.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:34.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:34.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:34.50#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:40:34.50#ibcon#first serial, iclass 13, count 0 2006.201.16:40:34.50#ibcon#enter sib2, iclass 13, count 0 2006.201.16:40:34.50#ibcon#flushed, iclass 13, count 0 2006.201.16:40:34.50#ibcon#about to write, iclass 13, count 0 2006.201.16:40:34.50#ibcon#wrote, iclass 13, count 0 2006.201.16:40:34.50#ibcon#about to read 3, iclass 13, count 0 2006.201.16:40:34.52#ibcon#read 3, iclass 13, count 0 2006.201.16:40:34.52#ibcon#about to read 4, iclass 13, count 0 2006.201.16:40:34.52#ibcon#read 4, iclass 13, count 0 2006.201.16:40:34.52#ibcon#about to read 5, iclass 13, count 0 2006.201.16:40:34.52#ibcon#read 5, iclass 13, count 0 2006.201.16:40:34.52#ibcon#about to read 6, iclass 13, count 0 2006.201.16:40:34.52#ibcon#read 6, iclass 13, count 0 2006.201.16:40:34.52#ibcon#end of sib2, iclass 13, count 0 2006.201.16:40:34.52#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:40:34.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:40:34.52#ibcon#[25=USB\r\n] 2006.201.16:40:34.52#ibcon#*before write, iclass 13, count 0 2006.201.16:40:34.52#ibcon#enter sib2, iclass 13, count 0 2006.201.16:40:34.52#ibcon#flushed, iclass 13, count 0 2006.201.16:40:34.52#ibcon#about to write, iclass 13, count 0 2006.201.16:40:34.52#ibcon#wrote, iclass 13, count 0 2006.201.16:40:34.52#ibcon#about to read 3, iclass 13, count 0 2006.201.16:40:34.55#ibcon#read 3, iclass 13, count 0 2006.201.16:40:34.55#ibcon#about to read 4, iclass 13, count 0 2006.201.16:40:34.55#ibcon#read 4, iclass 13, count 0 2006.201.16:40:34.55#ibcon#about to read 5, iclass 13, count 0 2006.201.16:40:34.55#ibcon#read 5, iclass 13, count 0 2006.201.16:40:34.55#ibcon#about to read 6, iclass 13, count 0 2006.201.16:40:34.55#ibcon#read 6, iclass 13, count 0 2006.201.16:40:34.55#ibcon#end of sib2, iclass 13, count 0 2006.201.16:40:34.55#ibcon#*after write, iclass 13, count 0 2006.201.16:40:34.55#ibcon#*before return 0, iclass 13, count 0 2006.201.16:40:34.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:34.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:34.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:40:34.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:40:34.55$vck44/valo=6,814.99 2006.201.16:40:34.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.16:40:34.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.16:40:34.55#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:34.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:34.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:34.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:34.55#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:40:34.55#ibcon#first serial, iclass 15, count 0 2006.201.16:40:34.55#ibcon#enter sib2, iclass 15, count 0 2006.201.16:40:34.55#ibcon#flushed, iclass 15, count 0 2006.201.16:40:34.55#ibcon#about to write, iclass 15, count 0 2006.201.16:40:34.55#ibcon#wrote, iclass 15, count 0 2006.201.16:40:34.55#ibcon#about to read 3, iclass 15, count 0 2006.201.16:40:34.57#ibcon#read 3, iclass 15, count 0 2006.201.16:40:34.57#ibcon#about to read 4, iclass 15, count 0 2006.201.16:40:34.57#ibcon#read 4, iclass 15, count 0 2006.201.16:40:34.57#ibcon#about to read 5, iclass 15, count 0 2006.201.16:40:34.57#ibcon#read 5, iclass 15, count 0 2006.201.16:40:34.57#ibcon#about to read 6, iclass 15, count 0 2006.201.16:40:34.57#ibcon#read 6, iclass 15, count 0 2006.201.16:40:34.57#ibcon#end of sib2, iclass 15, count 0 2006.201.16:40:34.57#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:40:34.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:40:34.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:40:34.57#ibcon#*before write, iclass 15, count 0 2006.201.16:40:34.57#ibcon#enter sib2, iclass 15, count 0 2006.201.16:40:34.57#ibcon#flushed, iclass 15, count 0 2006.201.16:40:34.57#ibcon#about to write, iclass 15, count 0 2006.201.16:40:34.57#ibcon#wrote, iclass 15, count 0 2006.201.16:40:34.57#ibcon#about to read 3, iclass 15, count 0 2006.201.16:40:34.61#ibcon#read 3, iclass 15, count 0 2006.201.16:40:34.61#ibcon#about to read 4, iclass 15, count 0 2006.201.16:40:34.61#ibcon#read 4, iclass 15, count 0 2006.201.16:40:34.61#ibcon#about to read 5, iclass 15, count 0 2006.201.16:40:34.61#ibcon#read 5, iclass 15, count 0 2006.201.16:40:34.61#ibcon#about to read 6, iclass 15, count 0 2006.201.16:40:34.61#ibcon#read 6, iclass 15, count 0 2006.201.16:40:34.61#ibcon#end of sib2, iclass 15, count 0 2006.201.16:40:34.61#ibcon#*after write, iclass 15, count 0 2006.201.16:40:34.61#ibcon#*before return 0, iclass 15, count 0 2006.201.16:40:34.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:34.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:34.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:40:34.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:40:34.61$vck44/va=6,5 2006.201.16:40:34.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.16:40:34.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.16:40:34.61#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:34.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:34.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:34.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:34.67#ibcon#enter wrdev, iclass 17, count 2 2006.201.16:40:34.67#ibcon#first serial, iclass 17, count 2 2006.201.16:40:34.67#ibcon#enter sib2, iclass 17, count 2 2006.201.16:40:34.67#ibcon#flushed, iclass 17, count 2 2006.201.16:40:34.67#ibcon#about to write, iclass 17, count 2 2006.201.16:40:34.67#ibcon#wrote, iclass 17, count 2 2006.201.16:40:34.67#ibcon#about to read 3, iclass 17, count 2 2006.201.16:40:34.69#ibcon#read 3, iclass 17, count 2 2006.201.16:40:34.69#ibcon#about to read 4, iclass 17, count 2 2006.201.16:40:34.69#ibcon#read 4, iclass 17, count 2 2006.201.16:40:34.69#ibcon#about to read 5, iclass 17, count 2 2006.201.16:40:34.69#ibcon#read 5, iclass 17, count 2 2006.201.16:40:34.69#ibcon#about to read 6, iclass 17, count 2 2006.201.16:40:34.69#ibcon#read 6, iclass 17, count 2 2006.201.16:40:34.69#ibcon#end of sib2, iclass 17, count 2 2006.201.16:40:34.69#ibcon#*mode == 0, iclass 17, count 2 2006.201.16:40:34.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.16:40:34.69#ibcon#[25=AT06-05\r\n] 2006.201.16:40:34.69#ibcon#*before write, iclass 17, count 2 2006.201.16:40:34.69#ibcon#enter sib2, iclass 17, count 2 2006.201.16:40:34.69#ibcon#flushed, iclass 17, count 2 2006.201.16:40:34.69#ibcon#about to write, iclass 17, count 2 2006.201.16:40:34.69#ibcon#wrote, iclass 17, count 2 2006.201.16:40:34.69#ibcon#about to read 3, iclass 17, count 2 2006.201.16:40:34.72#ibcon#read 3, iclass 17, count 2 2006.201.16:40:34.72#ibcon#about to read 4, iclass 17, count 2 2006.201.16:40:34.72#ibcon#read 4, iclass 17, count 2 2006.201.16:40:34.72#ibcon#about to read 5, iclass 17, count 2 2006.201.16:40:34.72#ibcon#read 5, iclass 17, count 2 2006.201.16:40:34.72#ibcon#about to read 6, iclass 17, count 2 2006.201.16:40:34.72#ibcon#read 6, iclass 17, count 2 2006.201.16:40:34.72#ibcon#end of sib2, iclass 17, count 2 2006.201.16:40:34.72#ibcon#*after write, iclass 17, count 2 2006.201.16:40:34.72#ibcon#*before return 0, iclass 17, count 2 2006.201.16:40:34.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:34.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:34.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.16:40:34.72#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:34.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:34.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:34.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:34.84#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:40:34.84#ibcon#first serial, iclass 17, count 0 2006.201.16:40:34.84#ibcon#enter sib2, iclass 17, count 0 2006.201.16:40:34.84#ibcon#flushed, iclass 17, count 0 2006.201.16:40:34.84#ibcon#about to write, iclass 17, count 0 2006.201.16:40:34.84#ibcon#wrote, iclass 17, count 0 2006.201.16:40:34.84#ibcon#about to read 3, iclass 17, count 0 2006.201.16:40:34.86#ibcon#read 3, iclass 17, count 0 2006.201.16:40:34.86#ibcon#about to read 4, iclass 17, count 0 2006.201.16:40:34.86#ibcon#read 4, iclass 17, count 0 2006.201.16:40:34.86#ibcon#about to read 5, iclass 17, count 0 2006.201.16:40:34.86#ibcon#read 5, iclass 17, count 0 2006.201.16:40:34.86#ibcon#about to read 6, iclass 17, count 0 2006.201.16:40:34.86#ibcon#read 6, iclass 17, count 0 2006.201.16:40:34.86#ibcon#end of sib2, iclass 17, count 0 2006.201.16:40:34.86#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:40:34.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:40:34.86#ibcon#[25=USB\r\n] 2006.201.16:40:34.86#ibcon#*before write, iclass 17, count 0 2006.201.16:40:34.86#ibcon#enter sib2, iclass 17, count 0 2006.201.16:40:34.86#ibcon#flushed, iclass 17, count 0 2006.201.16:40:34.86#ibcon#about to write, iclass 17, count 0 2006.201.16:40:34.86#ibcon#wrote, iclass 17, count 0 2006.201.16:40:34.86#ibcon#about to read 3, iclass 17, count 0 2006.201.16:40:34.89#ibcon#read 3, iclass 17, count 0 2006.201.16:40:34.89#ibcon#about to read 4, iclass 17, count 0 2006.201.16:40:34.89#ibcon#read 4, iclass 17, count 0 2006.201.16:40:34.89#ibcon#about to read 5, iclass 17, count 0 2006.201.16:40:34.89#ibcon#read 5, iclass 17, count 0 2006.201.16:40:34.89#ibcon#about to read 6, iclass 17, count 0 2006.201.16:40:34.89#ibcon#read 6, iclass 17, count 0 2006.201.16:40:34.89#ibcon#end of sib2, iclass 17, count 0 2006.201.16:40:34.89#ibcon#*after write, iclass 17, count 0 2006.201.16:40:34.89#ibcon#*before return 0, iclass 17, count 0 2006.201.16:40:34.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:34.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:34.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:40:34.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:40:34.89$vck44/valo=7,864.99 2006.201.16:40:34.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.16:40:34.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.16:40:34.89#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:34.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:34.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:34.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:34.89#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:40:34.89#ibcon#first serial, iclass 19, count 0 2006.201.16:40:34.89#ibcon#enter sib2, iclass 19, count 0 2006.201.16:40:34.89#ibcon#flushed, iclass 19, count 0 2006.201.16:40:34.89#ibcon#about to write, iclass 19, count 0 2006.201.16:40:34.89#ibcon#wrote, iclass 19, count 0 2006.201.16:40:34.89#ibcon#about to read 3, iclass 19, count 0 2006.201.16:40:34.91#ibcon#read 3, iclass 19, count 0 2006.201.16:40:34.91#ibcon#about to read 4, iclass 19, count 0 2006.201.16:40:34.91#ibcon#read 4, iclass 19, count 0 2006.201.16:40:34.91#ibcon#about to read 5, iclass 19, count 0 2006.201.16:40:34.91#ibcon#read 5, iclass 19, count 0 2006.201.16:40:34.91#ibcon#about to read 6, iclass 19, count 0 2006.201.16:40:34.91#ibcon#read 6, iclass 19, count 0 2006.201.16:40:34.91#ibcon#end of sib2, iclass 19, count 0 2006.201.16:40:34.91#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:40:34.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:40:34.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:40:34.91#ibcon#*before write, iclass 19, count 0 2006.201.16:40:34.91#ibcon#enter sib2, iclass 19, count 0 2006.201.16:40:34.91#ibcon#flushed, iclass 19, count 0 2006.201.16:40:34.91#ibcon#about to write, iclass 19, count 0 2006.201.16:40:34.91#ibcon#wrote, iclass 19, count 0 2006.201.16:40:34.91#ibcon#about to read 3, iclass 19, count 0 2006.201.16:40:34.95#ibcon#read 3, iclass 19, count 0 2006.201.16:40:34.95#ibcon#about to read 4, iclass 19, count 0 2006.201.16:40:34.95#ibcon#read 4, iclass 19, count 0 2006.201.16:40:34.95#ibcon#about to read 5, iclass 19, count 0 2006.201.16:40:34.95#ibcon#read 5, iclass 19, count 0 2006.201.16:40:34.95#ibcon#about to read 6, iclass 19, count 0 2006.201.16:40:34.95#ibcon#read 6, iclass 19, count 0 2006.201.16:40:34.95#ibcon#end of sib2, iclass 19, count 0 2006.201.16:40:34.95#ibcon#*after write, iclass 19, count 0 2006.201.16:40:34.95#ibcon#*before return 0, iclass 19, count 0 2006.201.16:40:34.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:34.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:34.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:40:34.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:40:34.95$vck44/va=7,5 2006.201.16:40:34.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.16:40:34.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.16:40:34.95#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:34.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:35.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:35.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:35.01#ibcon#enter wrdev, iclass 21, count 2 2006.201.16:40:35.01#ibcon#first serial, iclass 21, count 2 2006.201.16:40:35.01#ibcon#enter sib2, iclass 21, count 2 2006.201.16:40:35.01#ibcon#flushed, iclass 21, count 2 2006.201.16:40:35.01#ibcon#about to write, iclass 21, count 2 2006.201.16:40:35.01#ibcon#wrote, iclass 21, count 2 2006.201.16:40:35.01#ibcon#about to read 3, iclass 21, count 2 2006.201.16:40:35.03#ibcon#read 3, iclass 21, count 2 2006.201.16:40:35.03#ibcon#about to read 4, iclass 21, count 2 2006.201.16:40:35.03#ibcon#read 4, iclass 21, count 2 2006.201.16:40:35.03#ibcon#about to read 5, iclass 21, count 2 2006.201.16:40:35.03#ibcon#read 5, iclass 21, count 2 2006.201.16:40:35.03#ibcon#about to read 6, iclass 21, count 2 2006.201.16:40:35.03#ibcon#read 6, iclass 21, count 2 2006.201.16:40:35.03#ibcon#end of sib2, iclass 21, count 2 2006.201.16:40:35.03#ibcon#*mode == 0, iclass 21, count 2 2006.201.16:40:35.03#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.16:40:35.03#ibcon#[25=AT07-05\r\n] 2006.201.16:40:35.03#ibcon#*before write, iclass 21, count 2 2006.201.16:40:35.03#ibcon#enter sib2, iclass 21, count 2 2006.201.16:40:35.03#ibcon#flushed, iclass 21, count 2 2006.201.16:40:35.03#ibcon#about to write, iclass 21, count 2 2006.201.16:40:35.03#ibcon#wrote, iclass 21, count 2 2006.201.16:40:35.03#ibcon#about to read 3, iclass 21, count 2 2006.201.16:40:35.06#ibcon#read 3, iclass 21, count 2 2006.201.16:40:35.06#ibcon#about to read 4, iclass 21, count 2 2006.201.16:40:35.06#ibcon#read 4, iclass 21, count 2 2006.201.16:40:35.06#ibcon#about to read 5, iclass 21, count 2 2006.201.16:40:35.06#ibcon#read 5, iclass 21, count 2 2006.201.16:40:35.06#ibcon#about to read 6, iclass 21, count 2 2006.201.16:40:35.06#ibcon#read 6, iclass 21, count 2 2006.201.16:40:35.06#ibcon#end of sib2, iclass 21, count 2 2006.201.16:40:35.06#ibcon#*after write, iclass 21, count 2 2006.201.16:40:35.06#ibcon#*before return 0, iclass 21, count 2 2006.201.16:40:35.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:35.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:35.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.16:40:35.06#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:35.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:35.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:35.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:35.18#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:40:35.18#ibcon#first serial, iclass 21, count 0 2006.201.16:40:35.18#ibcon#enter sib2, iclass 21, count 0 2006.201.16:40:35.18#ibcon#flushed, iclass 21, count 0 2006.201.16:40:35.18#ibcon#about to write, iclass 21, count 0 2006.201.16:40:35.18#ibcon#wrote, iclass 21, count 0 2006.201.16:40:35.18#ibcon#about to read 3, iclass 21, count 0 2006.201.16:40:35.21#ibcon#read 3, iclass 21, count 0 2006.201.16:40:35.21#ibcon#about to read 4, iclass 21, count 0 2006.201.16:40:35.21#ibcon#read 4, iclass 21, count 0 2006.201.16:40:35.21#ibcon#about to read 5, iclass 21, count 0 2006.201.16:40:35.21#ibcon#read 5, iclass 21, count 0 2006.201.16:40:35.21#ibcon#about to read 6, iclass 21, count 0 2006.201.16:40:35.21#ibcon#read 6, iclass 21, count 0 2006.201.16:40:35.21#ibcon#end of sib2, iclass 21, count 0 2006.201.16:40:35.21#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:40:35.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:40:35.21#ibcon#[25=USB\r\n] 2006.201.16:40:35.21#ibcon#*before write, iclass 21, count 0 2006.201.16:40:35.21#ibcon#enter sib2, iclass 21, count 0 2006.201.16:40:35.21#ibcon#flushed, iclass 21, count 0 2006.201.16:40:35.21#ibcon#about to write, iclass 21, count 0 2006.201.16:40:35.21#ibcon#wrote, iclass 21, count 0 2006.201.16:40:35.21#ibcon#about to read 3, iclass 21, count 0 2006.201.16:40:35.24#ibcon#read 3, iclass 21, count 0 2006.201.16:40:35.24#ibcon#about to read 4, iclass 21, count 0 2006.201.16:40:35.24#ibcon#read 4, iclass 21, count 0 2006.201.16:40:35.24#ibcon#about to read 5, iclass 21, count 0 2006.201.16:40:35.24#ibcon#read 5, iclass 21, count 0 2006.201.16:40:35.24#ibcon#about to read 6, iclass 21, count 0 2006.201.16:40:35.24#ibcon#read 6, iclass 21, count 0 2006.201.16:40:35.24#ibcon#end of sib2, iclass 21, count 0 2006.201.16:40:35.24#ibcon#*after write, iclass 21, count 0 2006.201.16:40:35.24#ibcon#*before return 0, iclass 21, count 0 2006.201.16:40:35.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:35.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:35.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:40:35.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:40:35.24$vck44/valo=8,884.99 2006.201.16:40:35.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.16:40:35.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.16:40:35.24#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:35.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:35.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:35.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:35.24#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:40:35.24#ibcon#first serial, iclass 23, count 0 2006.201.16:40:35.24#ibcon#enter sib2, iclass 23, count 0 2006.201.16:40:35.24#ibcon#flushed, iclass 23, count 0 2006.201.16:40:35.24#ibcon#about to write, iclass 23, count 0 2006.201.16:40:35.24#ibcon#wrote, iclass 23, count 0 2006.201.16:40:35.24#ibcon#about to read 3, iclass 23, count 0 2006.201.16:40:35.26#ibcon#read 3, iclass 23, count 0 2006.201.16:40:35.26#ibcon#about to read 4, iclass 23, count 0 2006.201.16:40:35.26#ibcon#read 4, iclass 23, count 0 2006.201.16:40:35.26#ibcon#about to read 5, iclass 23, count 0 2006.201.16:40:35.26#ibcon#read 5, iclass 23, count 0 2006.201.16:40:35.26#ibcon#about to read 6, iclass 23, count 0 2006.201.16:40:35.26#ibcon#read 6, iclass 23, count 0 2006.201.16:40:35.26#ibcon#end of sib2, iclass 23, count 0 2006.201.16:40:35.26#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:40:35.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:40:35.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:40:35.26#ibcon#*before write, iclass 23, count 0 2006.201.16:40:35.26#ibcon#enter sib2, iclass 23, count 0 2006.201.16:40:35.26#ibcon#flushed, iclass 23, count 0 2006.201.16:40:35.26#ibcon#about to write, iclass 23, count 0 2006.201.16:40:35.26#ibcon#wrote, iclass 23, count 0 2006.201.16:40:35.26#ibcon#about to read 3, iclass 23, count 0 2006.201.16:40:35.30#ibcon#read 3, iclass 23, count 0 2006.201.16:40:35.30#ibcon#about to read 4, iclass 23, count 0 2006.201.16:40:35.30#ibcon#read 4, iclass 23, count 0 2006.201.16:40:35.30#ibcon#about to read 5, iclass 23, count 0 2006.201.16:40:35.30#ibcon#read 5, iclass 23, count 0 2006.201.16:40:35.30#ibcon#about to read 6, iclass 23, count 0 2006.201.16:40:35.30#ibcon#read 6, iclass 23, count 0 2006.201.16:40:35.30#ibcon#end of sib2, iclass 23, count 0 2006.201.16:40:35.30#ibcon#*after write, iclass 23, count 0 2006.201.16:40:35.30#ibcon#*before return 0, iclass 23, count 0 2006.201.16:40:35.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:35.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:35.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:40:35.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:40:35.30$vck44/va=8,4 2006.201.16:40:35.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.16:40:35.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.16:40:35.30#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:35.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:40:35.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:40:35.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:40:35.36#ibcon#enter wrdev, iclass 25, count 2 2006.201.16:40:35.36#ibcon#first serial, iclass 25, count 2 2006.201.16:40:35.36#ibcon#enter sib2, iclass 25, count 2 2006.201.16:40:35.36#ibcon#flushed, iclass 25, count 2 2006.201.16:40:35.36#ibcon#about to write, iclass 25, count 2 2006.201.16:40:35.36#ibcon#wrote, iclass 25, count 2 2006.201.16:40:35.36#ibcon#about to read 3, iclass 25, count 2 2006.201.16:40:35.38#ibcon#read 3, iclass 25, count 2 2006.201.16:40:35.38#ibcon#about to read 4, iclass 25, count 2 2006.201.16:40:35.38#ibcon#read 4, iclass 25, count 2 2006.201.16:40:35.38#ibcon#about to read 5, iclass 25, count 2 2006.201.16:40:35.38#ibcon#read 5, iclass 25, count 2 2006.201.16:40:35.38#ibcon#about to read 6, iclass 25, count 2 2006.201.16:40:35.38#ibcon#read 6, iclass 25, count 2 2006.201.16:40:35.38#ibcon#end of sib2, iclass 25, count 2 2006.201.16:40:35.38#ibcon#*mode == 0, iclass 25, count 2 2006.201.16:40:35.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.16:40:35.38#ibcon#[25=AT08-04\r\n] 2006.201.16:40:35.38#ibcon#*before write, iclass 25, count 2 2006.201.16:40:35.38#ibcon#enter sib2, iclass 25, count 2 2006.201.16:40:35.38#ibcon#flushed, iclass 25, count 2 2006.201.16:40:35.38#ibcon#about to write, iclass 25, count 2 2006.201.16:40:35.38#ibcon#wrote, iclass 25, count 2 2006.201.16:40:35.38#ibcon#about to read 3, iclass 25, count 2 2006.201.16:40:35.41#ibcon#read 3, iclass 25, count 2 2006.201.16:40:35.41#ibcon#about to read 4, iclass 25, count 2 2006.201.16:40:35.41#ibcon#read 4, iclass 25, count 2 2006.201.16:40:35.41#ibcon#about to read 5, iclass 25, count 2 2006.201.16:40:35.41#ibcon#read 5, iclass 25, count 2 2006.201.16:40:35.41#ibcon#about to read 6, iclass 25, count 2 2006.201.16:40:35.41#ibcon#read 6, iclass 25, count 2 2006.201.16:40:35.41#ibcon#end of sib2, iclass 25, count 2 2006.201.16:40:35.41#ibcon#*after write, iclass 25, count 2 2006.201.16:40:35.41#ibcon#*before return 0, iclass 25, count 2 2006.201.16:40:35.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:40:35.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:40:35.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.16:40:35.41#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:35.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:40:35.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:40:35.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:40:35.53#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:40:35.53#ibcon#first serial, iclass 25, count 0 2006.201.16:40:35.53#ibcon#enter sib2, iclass 25, count 0 2006.201.16:40:35.53#ibcon#flushed, iclass 25, count 0 2006.201.16:40:35.53#ibcon#about to write, iclass 25, count 0 2006.201.16:40:35.53#ibcon#wrote, iclass 25, count 0 2006.201.16:40:35.53#ibcon#about to read 3, iclass 25, count 0 2006.201.16:40:35.55#ibcon#read 3, iclass 25, count 0 2006.201.16:40:35.55#ibcon#about to read 4, iclass 25, count 0 2006.201.16:40:35.55#ibcon#read 4, iclass 25, count 0 2006.201.16:40:35.55#ibcon#about to read 5, iclass 25, count 0 2006.201.16:40:35.55#ibcon#read 5, iclass 25, count 0 2006.201.16:40:35.55#ibcon#about to read 6, iclass 25, count 0 2006.201.16:40:35.55#ibcon#read 6, iclass 25, count 0 2006.201.16:40:35.55#ibcon#end of sib2, iclass 25, count 0 2006.201.16:40:35.55#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:40:35.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:40:35.55#ibcon#[25=USB\r\n] 2006.201.16:40:35.55#ibcon#*before write, iclass 25, count 0 2006.201.16:40:35.55#ibcon#enter sib2, iclass 25, count 0 2006.201.16:40:35.55#ibcon#flushed, iclass 25, count 0 2006.201.16:40:35.55#ibcon#about to write, iclass 25, count 0 2006.201.16:40:35.55#ibcon#wrote, iclass 25, count 0 2006.201.16:40:35.55#ibcon#about to read 3, iclass 25, count 0 2006.201.16:40:35.58#ibcon#read 3, iclass 25, count 0 2006.201.16:40:35.58#ibcon#about to read 4, iclass 25, count 0 2006.201.16:40:35.58#ibcon#read 4, iclass 25, count 0 2006.201.16:40:35.58#ibcon#about to read 5, iclass 25, count 0 2006.201.16:40:35.58#ibcon#read 5, iclass 25, count 0 2006.201.16:40:35.58#ibcon#about to read 6, iclass 25, count 0 2006.201.16:40:35.58#ibcon#read 6, iclass 25, count 0 2006.201.16:40:35.58#ibcon#end of sib2, iclass 25, count 0 2006.201.16:40:35.58#ibcon#*after write, iclass 25, count 0 2006.201.16:40:35.58#ibcon#*before return 0, iclass 25, count 0 2006.201.16:40:35.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:40:35.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:40:35.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:40:35.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:40:35.58$vck44/vblo=1,629.99 2006.201.16:40:35.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.16:40:35.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.16:40:35.58#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:35.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:35.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:35.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:35.58#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:40:35.58#ibcon#first serial, iclass 27, count 0 2006.201.16:40:35.58#ibcon#enter sib2, iclass 27, count 0 2006.201.16:40:35.58#ibcon#flushed, iclass 27, count 0 2006.201.16:40:35.58#ibcon#about to write, iclass 27, count 0 2006.201.16:40:35.58#ibcon#wrote, iclass 27, count 0 2006.201.16:40:35.58#ibcon#about to read 3, iclass 27, count 0 2006.201.16:40:35.60#ibcon#read 3, iclass 27, count 0 2006.201.16:40:35.60#ibcon#about to read 4, iclass 27, count 0 2006.201.16:40:35.60#ibcon#read 4, iclass 27, count 0 2006.201.16:40:35.60#ibcon#about to read 5, iclass 27, count 0 2006.201.16:40:35.60#ibcon#read 5, iclass 27, count 0 2006.201.16:40:35.60#ibcon#about to read 6, iclass 27, count 0 2006.201.16:40:35.60#ibcon#read 6, iclass 27, count 0 2006.201.16:40:35.60#ibcon#end of sib2, iclass 27, count 0 2006.201.16:40:35.60#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:40:35.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:40:35.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:40:35.60#ibcon#*before write, iclass 27, count 0 2006.201.16:40:35.60#ibcon#enter sib2, iclass 27, count 0 2006.201.16:40:35.60#ibcon#flushed, iclass 27, count 0 2006.201.16:40:35.60#ibcon#about to write, iclass 27, count 0 2006.201.16:40:35.60#ibcon#wrote, iclass 27, count 0 2006.201.16:40:35.60#ibcon#about to read 3, iclass 27, count 0 2006.201.16:40:35.64#ibcon#read 3, iclass 27, count 0 2006.201.16:40:35.64#ibcon#about to read 4, iclass 27, count 0 2006.201.16:40:35.64#ibcon#read 4, iclass 27, count 0 2006.201.16:40:35.64#ibcon#about to read 5, iclass 27, count 0 2006.201.16:40:35.64#ibcon#read 5, iclass 27, count 0 2006.201.16:40:35.64#ibcon#about to read 6, iclass 27, count 0 2006.201.16:40:35.64#ibcon#read 6, iclass 27, count 0 2006.201.16:40:35.64#ibcon#end of sib2, iclass 27, count 0 2006.201.16:40:35.64#ibcon#*after write, iclass 27, count 0 2006.201.16:40:35.64#ibcon#*before return 0, iclass 27, count 0 2006.201.16:40:35.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:35.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:40:35.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:40:35.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:40:35.64$vck44/vb=1,4 2006.201.16:40:35.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.16:40:35.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.16:40:35.64#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:35.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:35.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:35.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:35.64#ibcon#enter wrdev, iclass 29, count 2 2006.201.16:40:35.64#ibcon#first serial, iclass 29, count 2 2006.201.16:40:35.64#ibcon#enter sib2, iclass 29, count 2 2006.201.16:40:35.64#ibcon#flushed, iclass 29, count 2 2006.201.16:40:35.64#ibcon#about to write, iclass 29, count 2 2006.201.16:40:35.64#ibcon#wrote, iclass 29, count 2 2006.201.16:40:35.64#ibcon#about to read 3, iclass 29, count 2 2006.201.16:40:35.66#ibcon#read 3, iclass 29, count 2 2006.201.16:40:35.66#ibcon#about to read 4, iclass 29, count 2 2006.201.16:40:35.66#ibcon#read 4, iclass 29, count 2 2006.201.16:40:35.66#ibcon#about to read 5, iclass 29, count 2 2006.201.16:40:35.66#ibcon#read 5, iclass 29, count 2 2006.201.16:40:35.66#ibcon#about to read 6, iclass 29, count 2 2006.201.16:40:35.66#ibcon#read 6, iclass 29, count 2 2006.201.16:40:35.66#ibcon#end of sib2, iclass 29, count 2 2006.201.16:40:35.66#ibcon#*mode == 0, iclass 29, count 2 2006.201.16:40:35.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.16:40:35.66#ibcon#[27=AT01-04\r\n] 2006.201.16:40:35.66#ibcon#*before write, iclass 29, count 2 2006.201.16:40:35.66#ibcon#enter sib2, iclass 29, count 2 2006.201.16:40:35.66#ibcon#flushed, iclass 29, count 2 2006.201.16:40:35.66#ibcon#about to write, iclass 29, count 2 2006.201.16:40:35.66#ibcon#wrote, iclass 29, count 2 2006.201.16:40:35.66#ibcon#about to read 3, iclass 29, count 2 2006.201.16:40:35.69#ibcon#read 3, iclass 29, count 2 2006.201.16:40:35.69#ibcon#about to read 4, iclass 29, count 2 2006.201.16:40:35.69#ibcon#read 4, iclass 29, count 2 2006.201.16:40:35.69#ibcon#about to read 5, iclass 29, count 2 2006.201.16:40:35.69#ibcon#read 5, iclass 29, count 2 2006.201.16:40:35.69#ibcon#about to read 6, iclass 29, count 2 2006.201.16:40:35.69#ibcon#read 6, iclass 29, count 2 2006.201.16:40:35.69#ibcon#end of sib2, iclass 29, count 2 2006.201.16:40:35.69#ibcon#*after write, iclass 29, count 2 2006.201.16:40:35.69#ibcon#*before return 0, iclass 29, count 2 2006.201.16:40:35.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:35.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:40:35.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.16:40:35.69#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:35.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:35.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:35.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:35.81#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:40:35.81#ibcon#first serial, iclass 29, count 0 2006.201.16:40:35.81#ibcon#enter sib2, iclass 29, count 0 2006.201.16:40:35.81#ibcon#flushed, iclass 29, count 0 2006.201.16:40:35.81#ibcon#about to write, iclass 29, count 0 2006.201.16:40:35.81#ibcon#wrote, iclass 29, count 0 2006.201.16:40:35.81#ibcon#about to read 3, iclass 29, count 0 2006.201.16:40:35.83#ibcon#read 3, iclass 29, count 0 2006.201.16:40:35.83#ibcon#about to read 4, iclass 29, count 0 2006.201.16:40:35.83#ibcon#read 4, iclass 29, count 0 2006.201.16:40:35.83#ibcon#about to read 5, iclass 29, count 0 2006.201.16:40:35.83#ibcon#read 5, iclass 29, count 0 2006.201.16:40:35.83#ibcon#about to read 6, iclass 29, count 0 2006.201.16:40:35.83#ibcon#read 6, iclass 29, count 0 2006.201.16:40:35.83#ibcon#end of sib2, iclass 29, count 0 2006.201.16:40:35.83#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:40:35.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:40:35.83#ibcon#[27=USB\r\n] 2006.201.16:40:35.83#ibcon#*before write, iclass 29, count 0 2006.201.16:40:35.83#ibcon#enter sib2, iclass 29, count 0 2006.201.16:40:35.83#ibcon#flushed, iclass 29, count 0 2006.201.16:40:35.83#ibcon#about to write, iclass 29, count 0 2006.201.16:40:35.83#ibcon#wrote, iclass 29, count 0 2006.201.16:40:35.83#ibcon#about to read 3, iclass 29, count 0 2006.201.16:40:35.86#ibcon#read 3, iclass 29, count 0 2006.201.16:40:35.86#ibcon#about to read 4, iclass 29, count 0 2006.201.16:40:35.86#ibcon#read 4, iclass 29, count 0 2006.201.16:40:35.86#ibcon#about to read 5, iclass 29, count 0 2006.201.16:40:35.86#ibcon#read 5, iclass 29, count 0 2006.201.16:40:35.86#ibcon#about to read 6, iclass 29, count 0 2006.201.16:40:35.86#ibcon#read 6, iclass 29, count 0 2006.201.16:40:35.86#ibcon#end of sib2, iclass 29, count 0 2006.201.16:40:35.86#ibcon#*after write, iclass 29, count 0 2006.201.16:40:35.86#ibcon#*before return 0, iclass 29, count 0 2006.201.16:40:35.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:35.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:40:35.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:40:35.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:40:35.86$vck44/vblo=2,634.99 2006.201.16:40:35.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.16:40:35.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.16:40:35.86#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:35.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:35.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:35.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:35.86#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:40:35.86#ibcon#first serial, iclass 31, count 0 2006.201.16:40:35.86#ibcon#enter sib2, iclass 31, count 0 2006.201.16:40:35.86#ibcon#flushed, iclass 31, count 0 2006.201.16:40:35.86#ibcon#about to write, iclass 31, count 0 2006.201.16:40:35.86#ibcon#wrote, iclass 31, count 0 2006.201.16:40:35.86#ibcon#about to read 3, iclass 31, count 0 2006.201.16:40:35.88#ibcon#read 3, iclass 31, count 0 2006.201.16:40:35.88#ibcon#about to read 4, iclass 31, count 0 2006.201.16:40:35.88#ibcon#read 4, iclass 31, count 0 2006.201.16:40:35.88#ibcon#about to read 5, iclass 31, count 0 2006.201.16:40:35.88#ibcon#read 5, iclass 31, count 0 2006.201.16:40:35.88#ibcon#about to read 6, iclass 31, count 0 2006.201.16:40:35.88#ibcon#read 6, iclass 31, count 0 2006.201.16:40:35.88#ibcon#end of sib2, iclass 31, count 0 2006.201.16:40:35.88#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:40:35.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:40:35.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:40:35.88#ibcon#*before write, iclass 31, count 0 2006.201.16:40:35.88#ibcon#enter sib2, iclass 31, count 0 2006.201.16:40:35.88#ibcon#flushed, iclass 31, count 0 2006.201.16:40:35.88#ibcon#about to write, iclass 31, count 0 2006.201.16:40:35.88#ibcon#wrote, iclass 31, count 0 2006.201.16:40:35.88#ibcon#about to read 3, iclass 31, count 0 2006.201.16:40:35.92#ibcon#read 3, iclass 31, count 0 2006.201.16:40:35.92#ibcon#about to read 4, iclass 31, count 0 2006.201.16:40:35.92#ibcon#read 4, iclass 31, count 0 2006.201.16:40:35.92#ibcon#about to read 5, iclass 31, count 0 2006.201.16:40:35.92#ibcon#read 5, iclass 31, count 0 2006.201.16:40:35.92#ibcon#about to read 6, iclass 31, count 0 2006.201.16:40:35.92#ibcon#read 6, iclass 31, count 0 2006.201.16:40:35.92#ibcon#end of sib2, iclass 31, count 0 2006.201.16:40:35.92#ibcon#*after write, iclass 31, count 0 2006.201.16:40:35.92#ibcon#*before return 0, iclass 31, count 0 2006.201.16:40:35.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:35.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:40:35.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:40:35.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:40:35.92$vck44/vb=2,5 2006.201.16:40:35.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.16:40:35.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.16:40:35.92#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:35.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:35.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:35.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:35.98#ibcon#enter wrdev, iclass 33, count 2 2006.201.16:40:35.98#ibcon#first serial, iclass 33, count 2 2006.201.16:40:35.98#ibcon#enter sib2, iclass 33, count 2 2006.201.16:40:35.98#ibcon#flushed, iclass 33, count 2 2006.201.16:40:35.98#ibcon#about to write, iclass 33, count 2 2006.201.16:40:35.98#ibcon#wrote, iclass 33, count 2 2006.201.16:40:35.98#ibcon#about to read 3, iclass 33, count 2 2006.201.16:40:36.00#ibcon#read 3, iclass 33, count 2 2006.201.16:40:36.00#ibcon#about to read 4, iclass 33, count 2 2006.201.16:40:36.00#ibcon#read 4, iclass 33, count 2 2006.201.16:40:36.00#ibcon#about to read 5, iclass 33, count 2 2006.201.16:40:36.00#ibcon#read 5, iclass 33, count 2 2006.201.16:40:36.00#ibcon#about to read 6, iclass 33, count 2 2006.201.16:40:36.00#ibcon#read 6, iclass 33, count 2 2006.201.16:40:36.00#ibcon#end of sib2, iclass 33, count 2 2006.201.16:40:36.00#ibcon#*mode == 0, iclass 33, count 2 2006.201.16:40:36.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.16:40:36.00#ibcon#[27=AT02-05\r\n] 2006.201.16:40:36.00#ibcon#*before write, iclass 33, count 2 2006.201.16:40:36.00#ibcon#enter sib2, iclass 33, count 2 2006.201.16:40:36.00#ibcon#flushed, iclass 33, count 2 2006.201.16:40:36.00#ibcon#about to write, iclass 33, count 2 2006.201.16:40:36.00#ibcon#wrote, iclass 33, count 2 2006.201.16:40:36.00#ibcon#about to read 3, iclass 33, count 2 2006.201.16:40:36.03#ibcon#read 3, iclass 33, count 2 2006.201.16:40:36.03#ibcon#about to read 4, iclass 33, count 2 2006.201.16:40:36.03#ibcon#read 4, iclass 33, count 2 2006.201.16:40:36.03#ibcon#about to read 5, iclass 33, count 2 2006.201.16:40:36.03#ibcon#read 5, iclass 33, count 2 2006.201.16:40:36.03#ibcon#about to read 6, iclass 33, count 2 2006.201.16:40:36.03#ibcon#read 6, iclass 33, count 2 2006.201.16:40:36.03#ibcon#end of sib2, iclass 33, count 2 2006.201.16:40:36.03#ibcon#*after write, iclass 33, count 2 2006.201.16:40:36.03#ibcon#*before return 0, iclass 33, count 2 2006.201.16:40:36.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:36.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:40:36.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.16:40:36.03#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:36.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:36.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:36.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:36.15#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:40:36.15#ibcon#first serial, iclass 33, count 0 2006.201.16:40:36.15#ibcon#enter sib2, iclass 33, count 0 2006.201.16:40:36.15#ibcon#flushed, iclass 33, count 0 2006.201.16:40:36.15#ibcon#about to write, iclass 33, count 0 2006.201.16:40:36.15#ibcon#wrote, iclass 33, count 0 2006.201.16:40:36.15#ibcon#about to read 3, iclass 33, count 0 2006.201.16:40:36.17#ibcon#read 3, iclass 33, count 0 2006.201.16:40:36.17#ibcon#about to read 4, iclass 33, count 0 2006.201.16:40:36.17#ibcon#read 4, iclass 33, count 0 2006.201.16:40:36.17#ibcon#about to read 5, iclass 33, count 0 2006.201.16:40:36.17#ibcon#read 5, iclass 33, count 0 2006.201.16:40:36.17#ibcon#about to read 6, iclass 33, count 0 2006.201.16:40:36.17#ibcon#read 6, iclass 33, count 0 2006.201.16:40:36.17#ibcon#end of sib2, iclass 33, count 0 2006.201.16:40:36.17#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:40:36.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:40:36.17#ibcon#[27=USB\r\n] 2006.201.16:40:36.17#ibcon#*before write, iclass 33, count 0 2006.201.16:40:36.17#ibcon#enter sib2, iclass 33, count 0 2006.201.16:40:36.17#ibcon#flushed, iclass 33, count 0 2006.201.16:40:36.17#ibcon#about to write, iclass 33, count 0 2006.201.16:40:36.17#ibcon#wrote, iclass 33, count 0 2006.201.16:40:36.17#ibcon#about to read 3, iclass 33, count 0 2006.201.16:40:36.20#ibcon#read 3, iclass 33, count 0 2006.201.16:40:36.20#ibcon#about to read 4, iclass 33, count 0 2006.201.16:40:36.20#ibcon#read 4, iclass 33, count 0 2006.201.16:40:36.20#ibcon#about to read 5, iclass 33, count 0 2006.201.16:40:36.20#ibcon#read 5, iclass 33, count 0 2006.201.16:40:36.20#ibcon#about to read 6, iclass 33, count 0 2006.201.16:40:36.20#ibcon#read 6, iclass 33, count 0 2006.201.16:40:36.20#ibcon#end of sib2, iclass 33, count 0 2006.201.16:40:36.20#ibcon#*after write, iclass 33, count 0 2006.201.16:40:36.20#ibcon#*before return 0, iclass 33, count 0 2006.201.16:40:36.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:36.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:40:36.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:40:36.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:40:36.20$vck44/vblo=3,649.99 2006.201.16:40:36.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.16:40:36.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.16:40:36.20#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:36.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:40:36.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:40:36.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:40:36.20#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:40:36.20#ibcon#first serial, iclass 35, count 0 2006.201.16:40:36.20#ibcon#enter sib2, iclass 35, count 0 2006.201.16:40:36.20#ibcon#flushed, iclass 35, count 0 2006.201.16:40:36.20#ibcon#about to write, iclass 35, count 0 2006.201.16:40:36.20#ibcon#wrote, iclass 35, count 0 2006.201.16:40:36.20#ibcon#about to read 3, iclass 35, count 0 2006.201.16:40:36.22#ibcon#read 3, iclass 35, count 0 2006.201.16:40:36.22#ibcon#about to read 4, iclass 35, count 0 2006.201.16:40:36.22#ibcon#read 4, iclass 35, count 0 2006.201.16:40:36.22#ibcon#about to read 5, iclass 35, count 0 2006.201.16:40:36.22#ibcon#read 5, iclass 35, count 0 2006.201.16:40:36.22#ibcon#about to read 6, iclass 35, count 0 2006.201.16:40:36.22#ibcon#read 6, iclass 35, count 0 2006.201.16:40:36.22#ibcon#end of sib2, iclass 35, count 0 2006.201.16:40:36.22#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:40:36.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:40:36.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:40:36.22#ibcon#*before write, iclass 35, count 0 2006.201.16:40:36.22#ibcon#enter sib2, iclass 35, count 0 2006.201.16:40:36.22#ibcon#flushed, iclass 35, count 0 2006.201.16:40:36.22#ibcon#about to write, iclass 35, count 0 2006.201.16:40:36.22#ibcon#wrote, iclass 35, count 0 2006.201.16:40:36.22#ibcon#about to read 3, iclass 35, count 0 2006.201.16:40:36.27#ibcon#read 3, iclass 35, count 0 2006.201.16:40:36.27#ibcon#about to read 4, iclass 35, count 0 2006.201.16:40:36.27#ibcon#read 4, iclass 35, count 0 2006.201.16:40:36.27#ibcon#about to read 5, iclass 35, count 0 2006.201.16:40:36.27#ibcon#read 5, iclass 35, count 0 2006.201.16:40:36.27#ibcon#about to read 6, iclass 35, count 0 2006.201.16:40:36.27#ibcon#read 6, iclass 35, count 0 2006.201.16:40:36.27#ibcon#end of sib2, iclass 35, count 0 2006.201.16:40:36.27#ibcon#*after write, iclass 35, count 0 2006.201.16:40:36.27#ibcon#*before return 0, iclass 35, count 0 2006.201.16:40:36.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:40:36.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:40:36.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:40:36.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:40:36.27$vck44/vb=3,4 2006.201.16:40:36.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.16:40:36.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.16:40:36.27#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:36.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:40:36.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:40:36.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:40:36.32#ibcon#enter wrdev, iclass 37, count 2 2006.201.16:40:36.32#ibcon#first serial, iclass 37, count 2 2006.201.16:40:36.32#ibcon#enter sib2, iclass 37, count 2 2006.201.16:40:36.32#ibcon#flushed, iclass 37, count 2 2006.201.16:40:36.32#ibcon#about to write, iclass 37, count 2 2006.201.16:40:36.32#ibcon#wrote, iclass 37, count 2 2006.201.16:40:36.32#ibcon#about to read 3, iclass 37, count 2 2006.201.16:40:36.34#ibcon#read 3, iclass 37, count 2 2006.201.16:40:36.34#ibcon#about to read 4, iclass 37, count 2 2006.201.16:40:36.34#ibcon#read 4, iclass 37, count 2 2006.201.16:40:36.34#ibcon#about to read 5, iclass 37, count 2 2006.201.16:40:36.34#ibcon#read 5, iclass 37, count 2 2006.201.16:40:36.34#ibcon#about to read 6, iclass 37, count 2 2006.201.16:40:36.34#ibcon#read 6, iclass 37, count 2 2006.201.16:40:36.34#ibcon#end of sib2, iclass 37, count 2 2006.201.16:40:36.34#ibcon#*mode == 0, iclass 37, count 2 2006.201.16:40:36.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.16:40:36.34#ibcon#[27=AT03-04\r\n] 2006.201.16:40:36.34#ibcon#*before write, iclass 37, count 2 2006.201.16:40:36.34#ibcon#enter sib2, iclass 37, count 2 2006.201.16:40:36.34#ibcon#flushed, iclass 37, count 2 2006.201.16:40:36.34#ibcon#about to write, iclass 37, count 2 2006.201.16:40:36.34#ibcon#wrote, iclass 37, count 2 2006.201.16:40:36.34#ibcon#about to read 3, iclass 37, count 2 2006.201.16:40:36.37#ibcon#read 3, iclass 37, count 2 2006.201.16:40:36.37#ibcon#about to read 4, iclass 37, count 2 2006.201.16:40:36.37#ibcon#read 4, iclass 37, count 2 2006.201.16:40:36.37#ibcon#about to read 5, iclass 37, count 2 2006.201.16:40:36.37#ibcon#read 5, iclass 37, count 2 2006.201.16:40:36.37#ibcon#about to read 6, iclass 37, count 2 2006.201.16:40:36.37#ibcon#read 6, iclass 37, count 2 2006.201.16:40:36.37#ibcon#end of sib2, iclass 37, count 2 2006.201.16:40:36.37#ibcon#*after write, iclass 37, count 2 2006.201.16:40:36.37#ibcon#*before return 0, iclass 37, count 2 2006.201.16:40:36.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:40:36.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:40:36.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.16:40:36.37#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:36.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:40:36.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:40:36.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:40:36.49#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:40:36.49#ibcon#first serial, iclass 37, count 0 2006.201.16:40:36.49#ibcon#enter sib2, iclass 37, count 0 2006.201.16:40:36.49#ibcon#flushed, iclass 37, count 0 2006.201.16:40:36.49#ibcon#about to write, iclass 37, count 0 2006.201.16:40:36.49#ibcon#wrote, iclass 37, count 0 2006.201.16:40:36.49#ibcon#about to read 3, iclass 37, count 0 2006.201.16:40:36.51#ibcon#read 3, iclass 37, count 0 2006.201.16:40:36.51#ibcon#about to read 4, iclass 37, count 0 2006.201.16:40:36.51#ibcon#read 4, iclass 37, count 0 2006.201.16:40:36.51#ibcon#about to read 5, iclass 37, count 0 2006.201.16:40:36.51#ibcon#read 5, iclass 37, count 0 2006.201.16:40:36.51#ibcon#about to read 6, iclass 37, count 0 2006.201.16:40:36.51#ibcon#read 6, iclass 37, count 0 2006.201.16:40:36.51#ibcon#end of sib2, iclass 37, count 0 2006.201.16:40:36.51#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:40:36.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:40:36.51#ibcon#[27=USB\r\n] 2006.201.16:40:36.51#ibcon#*before write, iclass 37, count 0 2006.201.16:40:36.51#ibcon#enter sib2, iclass 37, count 0 2006.201.16:40:36.51#ibcon#flushed, iclass 37, count 0 2006.201.16:40:36.51#ibcon#about to write, iclass 37, count 0 2006.201.16:40:36.51#ibcon#wrote, iclass 37, count 0 2006.201.16:40:36.51#ibcon#about to read 3, iclass 37, count 0 2006.201.16:40:36.54#ibcon#read 3, iclass 37, count 0 2006.201.16:40:36.54#ibcon#about to read 4, iclass 37, count 0 2006.201.16:40:36.54#ibcon#read 4, iclass 37, count 0 2006.201.16:40:36.54#ibcon#about to read 5, iclass 37, count 0 2006.201.16:40:36.54#ibcon#read 5, iclass 37, count 0 2006.201.16:40:36.54#ibcon#about to read 6, iclass 37, count 0 2006.201.16:40:36.54#ibcon#read 6, iclass 37, count 0 2006.201.16:40:36.54#ibcon#end of sib2, iclass 37, count 0 2006.201.16:40:36.54#ibcon#*after write, iclass 37, count 0 2006.201.16:40:36.54#ibcon#*before return 0, iclass 37, count 0 2006.201.16:40:36.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:40:36.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:40:36.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:40:36.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:40:36.54$vck44/vblo=4,679.99 2006.201.16:40:36.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.16:40:36.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.16:40:36.54#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:36.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:36.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:36.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:36.54#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:40:36.54#ibcon#first serial, iclass 39, count 0 2006.201.16:40:36.54#ibcon#enter sib2, iclass 39, count 0 2006.201.16:40:36.54#ibcon#flushed, iclass 39, count 0 2006.201.16:40:36.54#ibcon#about to write, iclass 39, count 0 2006.201.16:40:36.54#ibcon#wrote, iclass 39, count 0 2006.201.16:40:36.54#ibcon#about to read 3, iclass 39, count 0 2006.201.16:40:36.56#ibcon#read 3, iclass 39, count 0 2006.201.16:40:36.56#ibcon#about to read 4, iclass 39, count 0 2006.201.16:40:36.56#ibcon#read 4, iclass 39, count 0 2006.201.16:40:36.56#ibcon#about to read 5, iclass 39, count 0 2006.201.16:40:36.56#ibcon#read 5, iclass 39, count 0 2006.201.16:40:36.56#ibcon#about to read 6, iclass 39, count 0 2006.201.16:40:36.56#ibcon#read 6, iclass 39, count 0 2006.201.16:40:36.56#ibcon#end of sib2, iclass 39, count 0 2006.201.16:40:36.56#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:40:36.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:40:36.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:40:36.56#ibcon#*before write, iclass 39, count 0 2006.201.16:40:36.56#ibcon#enter sib2, iclass 39, count 0 2006.201.16:40:36.56#ibcon#flushed, iclass 39, count 0 2006.201.16:40:36.56#ibcon#about to write, iclass 39, count 0 2006.201.16:40:36.56#ibcon#wrote, iclass 39, count 0 2006.201.16:40:36.56#ibcon#about to read 3, iclass 39, count 0 2006.201.16:40:36.60#ibcon#read 3, iclass 39, count 0 2006.201.16:40:36.60#ibcon#about to read 4, iclass 39, count 0 2006.201.16:40:36.60#ibcon#read 4, iclass 39, count 0 2006.201.16:40:36.60#ibcon#about to read 5, iclass 39, count 0 2006.201.16:40:36.60#ibcon#read 5, iclass 39, count 0 2006.201.16:40:36.60#ibcon#about to read 6, iclass 39, count 0 2006.201.16:40:36.60#ibcon#read 6, iclass 39, count 0 2006.201.16:40:36.60#ibcon#end of sib2, iclass 39, count 0 2006.201.16:40:36.60#ibcon#*after write, iclass 39, count 0 2006.201.16:40:36.60#ibcon#*before return 0, iclass 39, count 0 2006.201.16:40:36.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:36.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:40:36.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:40:36.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:40:36.60$vck44/vb=4,5 2006.201.16:40:36.60#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.16:40:36.60#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.16:40:36.60#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:36.60#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:36.66#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:36.66#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:36.66#ibcon#enter wrdev, iclass 2, count 2 2006.201.16:40:36.66#ibcon#first serial, iclass 2, count 2 2006.201.16:40:36.66#ibcon#enter sib2, iclass 2, count 2 2006.201.16:40:36.66#ibcon#flushed, iclass 2, count 2 2006.201.16:40:36.66#ibcon#about to write, iclass 2, count 2 2006.201.16:40:36.66#ibcon#wrote, iclass 2, count 2 2006.201.16:40:36.66#ibcon#about to read 3, iclass 2, count 2 2006.201.16:40:36.68#ibcon#read 3, iclass 2, count 2 2006.201.16:40:36.68#ibcon#about to read 4, iclass 2, count 2 2006.201.16:40:36.68#ibcon#read 4, iclass 2, count 2 2006.201.16:40:36.68#ibcon#about to read 5, iclass 2, count 2 2006.201.16:40:36.68#ibcon#read 5, iclass 2, count 2 2006.201.16:40:36.68#ibcon#about to read 6, iclass 2, count 2 2006.201.16:40:36.68#ibcon#read 6, iclass 2, count 2 2006.201.16:40:36.68#ibcon#end of sib2, iclass 2, count 2 2006.201.16:40:36.68#ibcon#*mode == 0, iclass 2, count 2 2006.201.16:40:36.68#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.16:40:36.68#ibcon#[27=AT04-05\r\n] 2006.201.16:40:36.68#ibcon#*before write, iclass 2, count 2 2006.201.16:40:36.68#ibcon#enter sib2, iclass 2, count 2 2006.201.16:40:36.68#ibcon#flushed, iclass 2, count 2 2006.201.16:40:36.68#ibcon#about to write, iclass 2, count 2 2006.201.16:40:36.68#ibcon#wrote, iclass 2, count 2 2006.201.16:40:36.68#ibcon#about to read 3, iclass 2, count 2 2006.201.16:40:36.71#ibcon#read 3, iclass 2, count 2 2006.201.16:40:36.71#ibcon#about to read 4, iclass 2, count 2 2006.201.16:40:36.71#ibcon#read 4, iclass 2, count 2 2006.201.16:40:36.71#ibcon#about to read 5, iclass 2, count 2 2006.201.16:40:36.71#ibcon#read 5, iclass 2, count 2 2006.201.16:40:36.71#ibcon#about to read 6, iclass 2, count 2 2006.201.16:40:36.71#ibcon#read 6, iclass 2, count 2 2006.201.16:40:36.71#ibcon#end of sib2, iclass 2, count 2 2006.201.16:40:36.71#ibcon#*after write, iclass 2, count 2 2006.201.16:40:36.71#ibcon#*before return 0, iclass 2, count 2 2006.201.16:40:36.71#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:36.71#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:40:36.71#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.16:40:36.71#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:36.71#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:36.83#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:36.83#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:36.83#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:40:36.83#ibcon#first serial, iclass 2, count 0 2006.201.16:40:36.83#ibcon#enter sib2, iclass 2, count 0 2006.201.16:40:36.83#ibcon#flushed, iclass 2, count 0 2006.201.16:40:36.83#ibcon#about to write, iclass 2, count 0 2006.201.16:40:36.83#ibcon#wrote, iclass 2, count 0 2006.201.16:40:36.83#ibcon#about to read 3, iclass 2, count 0 2006.201.16:40:36.85#ibcon#read 3, iclass 2, count 0 2006.201.16:40:36.85#ibcon#about to read 4, iclass 2, count 0 2006.201.16:40:36.85#ibcon#read 4, iclass 2, count 0 2006.201.16:40:36.85#ibcon#about to read 5, iclass 2, count 0 2006.201.16:40:36.85#ibcon#read 5, iclass 2, count 0 2006.201.16:40:36.85#ibcon#about to read 6, iclass 2, count 0 2006.201.16:40:36.85#ibcon#read 6, iclass 2, count 0 2006.201.16:40:36.85#ibcon#end of sib2, iclass 2, count 0 2006.201.16:40:36.85#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:40:36.85#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:40:36.85#ibcon#[27=USB\r\n] 2006.201.16:40:36.85#ibcon#*before write, iclass 2, count 0 2006.201.16:40:36.85#ibcon#enter sib2, iclass 2, count 0 2006.201.16:40:36.85#ibcon#flushed, iclass 2, count 0 2006.201.16:40:36.85#ibcon#about to write, iclass 2, count 0 2006.201.16:40:36.85#ibcon#wrote, iclass 2, count 0 2006.201.16:40:36.85#ibcon#about to read 3, iclass 2, count 0 2006.201.16:40:36.88#ibcon#read 3, iclass 2, count 0 2006.201.16:40:36.88#ibcon#about to read 4, iclass 2, count 0 2006.201.16:40:36.88#ibcon#read 4, iclass 2, count 0 2006.201.16:40:36.88#ibcon#about to read 5, iclass 2, count 0 2006.201.16:40:36.88#ibcon#read 5, iclass 2, count 0 2006.201.16:40:36.88#ibcon#about to read 6, iclass 2, count 0 2006.201.16:40:36.88#ibcon#read 6, iclass 2, count 0 2006.201.16:40:36.88#ibcon#end of sib2, iclass 2, count 0 2006.201.16:40:36.88#ibcon#*after write, iclass 2, count 0 2006.201.16:40:36.88#ibcon#*before return 0, iclass 2, count 0 2006.201.16:40:36.88#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:36.88#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:40:36.88#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:40:36.88#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:40:36.88$vck44/vblo=5,709.99 2006.201.16:40:36.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.16:40:36.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.16:40:36.88#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:36.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:36.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:36.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:36.88#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:40:36.88#ibcon#first serial, iclass 5, count 0 2006.201.16:40:36.88#ibcon#enter sib2, iclass 5, count 0 2006.201.16:40:36.88#ibcon#flushed, iclass 5, count 0 2006.201.16:40:36.88#ibcon#about to write, iclass 5, count 0 2006.201.16:40:36.88#ibcon#wrote, iclass 5, count 0 2006.201.16:40:36.88#ibcon#about to read 3, iclass 5, count 0 2006.201.16:40:36.90#ibcon#read 3, iclass 5, count 0 2006.201.16:40:36.90#ibcon#about to read 4, iclass 5, count 0 2006.201.16:40:36.90#ibcon#read 4, iclass 5, count 0 2006.201.16:40:36.90#ibcon#about to read 5, iclass 5, count 0 2006.201.16:40:36.90#ibcon#read 5, iclass 5, count 0 2006.201.16:40:36.90#ibcon#about to read 6, iclass 5, count 0 2006.201.16:40:36.90#ibcon#read 6, iclass 5, count 0 2006.201.16:40:36.90#ibcon#end of sib2, iclass 5, count 0 2006.201.16:40:36.90#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:40:36.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:40:36.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:40:36.90#ibcon#*before write, iclass 5, count 0 2006.201.16:40:36.90#ibcon#enter sib2, iclass 5, count 0 2006.201.16:40:36.90#ibcon#flushed, iclass 5, count 0 2006.201.16:40:36.90#ibcon#about to write, iclass 5, count 0 2006.201.16:40:36.90#ibcon#wrote, iclass 5, count 0 2006.201.16:40:36.90#ibcon#about to read 3, iclass 5, count 0 2006.201.16:40:36.94#ibcon#read 3, iclass 5, count 0 2006.201.16:40:36.94#ibcon#about to read 4, iclass 5, count 0 2006.201.16:40:36.94#ibcon#read 4, iclass 5, count 0 2006.201.16:40:36.94#ibcon#about to read 5, iclass 5, count 0 2006.201.16:40:36.94#ibcon#read 5, iclass 5, count 0 2006.201.16:40:36.94#ibcon#about to read 6, iclass 5, count 0 2006.201.16:40:36.94#ibcon#read 6, iclass 5, count 0 2006.201.16:40:36.94#ibcon#end of sib2, iclass 5, count 0 2006.201.16:40:36.94#ibcon#*after write, iclass 5, count 0 2006.201.16:40:36.94#ibcon#*before return 0, iclass 5, count 0 2006.201.16:40:36.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:36.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:40:36.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:40:36.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:40:36.94$vck44/vb=5,4 2006.201.16:40:36.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.16:40:36.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.16:40:36.94#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:36.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:37.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:37.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:37.00#ibcon#enter wrdev, iclass 7, count 2 2006.201.16:40:37.00#ibcon#first serial, iclass 7, count 2 2006.201.16:40:37.00#ibcon#enter sib2, iclass 7, count 2 2006.201.16:40:37.00#ibcon#flushed, iclass 7, count 2 2006.201.16:40:37.00#ibcon#about to write, iclass 7, count 2 2006.201.16:40:37.00#ibcon#wrote, iclass 7, count 2 2006.201.16:40:37.00#ibcon#about to read 3, iclass 7, count 2 2006.201.16:40:37.02#ibcon#read 3, iclass 7, count 2 2006.201.16:40:37.02#ibcon#about to read 4, iclass 7, count 2 2006.201.16:40:37.02#ibcon#read 4, iclass 7, count 2 2006.201.16:40:37.02#ibcon#about to read 5, iclass 7, count 2 2006.201.16:40:37.02#ibcon#read 5, iclass 7, count 2 2006.201.16:40:37.02#ibcon#about to read 6, iclass 7, count 2 2006.201.16:40:37.02#ibcon#read 6, iclass 7, count 2 2006.201.16:40:37.02#ibcon#end of sib2, iclass 7, count 2 2006.201.16:40:37.02#ibcon#*mode == 0, iclass 7, count 2 2006.201.16:40:37.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.16:40:37.02#ibcon#[27=AT05-04\r\n] 2006.201.16:40:37.02#ibcon#*before write, iclass 7, count 2 2006.201.16:40:37.02#ibcon#enter sib2, iclass 7, count 2 2006.201.16:40:37.02#ibcon#flushed, iclass 7, count 2 2006.201.16:40:37.02#ibcon#about to write, iclass 7, count 2 2006.201.16:40:37.02#ibcon#wrote, iclass 7, count 2 2006.201.16:40:37.02#ibcon#about to read 3, iclass 7, count 2 2006.201.16:40:37.05#ibcon#read 3, iclass 7, count 2 2006.201.16:40:37.05#ibcon#about to read 4, iclass 7, count 2 2006.201.16:40:37.05#ibcon#read 4, iclass 7, count 2 2006.201.16:40:37.05#ibcon#about to read 5, iclass 7, count 2 2006.201.16:40:37.05#ibcon#read 5, iclass 7, count 2 2006.201.16:40:37.05#ibcon#about to read 6, iclass 7, count 2 2006.201.16:40:37.05#ibcon#read 6, iclass 7, count 2 2006.201.16:40:37.05#ibcon#end of sib2, iclass 7, count 2 2006.201.16:40:37.05#ibcon#*after write, iclass 7, count 2 2006.201.16:40:37.05#ibcon#*before return 0, iclass 7, count 2 2006.201.16:40:37.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:37.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:40:37.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.16:40:37.05#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:37.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:37.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:37.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:37.17#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:40:37.17#ibcon#first serial, iclass 7, count 0 2006.201.16:40:37.17#ibcon#enter sib2, iclass 7, count 0 2006.201.16:40:37.17#ibcon#flushed, iclass 7, count 0 2006.201.16:40:37.17#ibcon#about to write, iclass 7, count 0 2006.201.16:40:37.17#ibcon#wrote, iclass 7, count 0 2006.201.16:40:37.17#ibcon#about to read 3, iclass 7, count 0 2006.201.16:40:37.19#ibcon#read 3, iclass 7, count 0 2006.201.16:40:37.19#ibcon#about to read 4, iclass 7, count 0 2006.201.16:40:37.19#ibcon#read 4, iclass 7, count 0 2006.201.16:40:37.19#ibcon#about to read 5, iclass 7, count 0 2006.201.16:40:37.19#ibcon#read 5, iclass 7, count 0 2006.201.16:40:37.19#ibcon#about to read 6, iclass 7, count 0 2006.201.16:40:37.19#ibcon#read 6, iclass 7, count 0 2006.201.16:40:37.19#ibcon#end of sib2, iclass 7, count 0 2006.201.16:40:37.19#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:40:37.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:40:37.19#ibcon#[27=USB\r\n] 2006.201.16:40:37.19#ibcon#*before write, iclass 7, count 0 2006.201.16:40:37.19#ibcon#enter sib2, iclass 7, count 0 2006.201.16:40:37.19#ibcon#flushed, iclass 7, count 0 2006.201.16:40:37.19#ibcon#about to write, iclass 7, count 0 2006.201.16:40:37.19#ibcon#wrote, iclass 7, count 0 2006.201.16:40:37.19#ibcon#about to read 3, iclass 7, count 0 2006.201.16:40:37.22#ibcon#read 3, iclass 7, count 0 2006.201.16:40:37.22#ibcon#about to read 4, iclass 7, count 0 2006.201.16:40:37.22#ibcon#read 4, iclass 7, count 0 2006.201.16:40:37.22#ibcon#about to read 5, iclass 7, count 0 2006.201.16:40:37.22#ibcon#read 5, iclass 7, count 0 2006.201.16:40:37.22#ibcon#about to read 6, iclass 7, count 0 2006.201.16:40:37.22#ibcon#read 6, iclass 7, count 0 2006.201.16:40:37.22#ibcon#end of sib2, iclass 7, count 0 2006.201.16:40:37.22#ibcon#*after write, iclass 7, count 0 2006.201.16:40:37.22#ibcon#*before return 0, iclass 7, count 0 2006.201.16:40:37.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:37.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:40:37.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:40:37.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:40:37.22$vck44/vblo=6,719.99 2006.201.16:40:37.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.16:40:37.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.16:40:37.22#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:37.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:37.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:37.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:37.22#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:40:37.22#ibcon#first serial, iclass 11, count 0 2006.201.16:40:37.22#ibcon#enter sib2, iclass 11, count 0 2006.201.16:40:37.22#ibcon#flushed, iclass 11, count 0 2006.201.16:40:37.22#ibcon#about to write, iclass 11, count 0 2006.201.16:40:37.22#ibcon#wrote, iclass 11, count 0 2006.201.16:40:37.22#ibcon#about to read 3, iclass 11, count 0 2006.201.16:40:37.24#ibcon#read 3, iclass 11, count 0 2006.201.16:40:37.24#ibcon#about to read 4, iclass 11, count 0 2006.201.16:40:37.24#ibcon#read 4, iclass 11, count 0 2006.201.16:40:37.24#ibcon#about to read 5, iclass 11, count 0 2006.201.16:40:37.24#ibcon#read 5, iclass 11, count 0 2006.201.16:40:37.24#ibcon#about to read 6, iclass 11, count 0 2006.201.16:40:37.24#ibcon#read 6, iclass 11, count 0 2006.201.16:40:37.24#ibcon#end of sib2, iclass 11, count 0 2006.201.16:40:37.24#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:40:37.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:40:37.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:40:37.24#ibcon#*before write, iclass 11, count 0 2006.201.16:40:37.24#ibcon#enter sib2, iclass 11, count 0 2006.201.16:40:37.24#ibcon#flushed, iclass 11, count 0 2006.201.16:40:37.24#ibcon#about to write, iclass 11, count 0 2006.201.16:40:37.24#ibcon#wrote, iclass 11, count 0 2006.201.16:40:37.24#ibcon#about to read 3, iclass 11, count 0 2006.201.16:40:37.28#ibcon#read 3, iclass 11, count 0 2006.201.16:40:37.28#ibcon#about to read 4, iclass 11, count 0 2006.201.16:40:37.28#ibcon#read 4, iclass 11, count 0 2006.201.16:40:37.28#ibcon#about to read 5, iclass 11, count 0 2006.201.16:40:37.28#ibcon#read 5, iclass 11, count 0 2006.201.16:40:37.28#ibcon#about to read 6, iclass 11, count 0 2006.201.16:40:37.28#ibcon#read 6, iclass 11, count 0 2006.201.16:40:37.28#ibcon#end of sib2, iclass 11, count 0 2006.201.16:40:37.28#ibcon#*after write, iclass 11, count 0 2006.201.16:40:37.28#ibcon#*before return 0, iclass 11, count 0 2006.201.16:40:37.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:37.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:40:37.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:40:37.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:40:37.28$vck44/vb=6,4 2006.201.16:40:37.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.16:40:37.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.16:40:37.28#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:37.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:37.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:37.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:37.34#ibcon#enter wrdev, iclass 13, count 2 2006.201.16:40:37.34#ibcon#first serial, iclass 13, count 2 2006.201.16:40:37.34#ibcon#enter sib2, iclass 13, count 2 2006.201.16:40:37.34#ibcon#flushed, iclass 13, count 2 2006.201.16:40:37.34#ibcon#about to write, iclass 13, count 2 2006.201.16:40:37.34#ibcon#wrote, iclass 13, count 2 2006.201.16:40:37.34#ibcon#about to read 3, iclass 13, count 2 2006.201.16:40:37.36#ibcon#read 3, iclass 13, count 2 2006.201.16:40:37.36#ibcon#about to read 4, iclass 13, count 2 2006.201.16:40:37.36#ibcon#read 4, iclass 13, count 2 2006.201.16:40:37.36#ibcon#about to read 5, iclass 13, count 2 2006.201.16:40:37.36#ibcon#read 5, iclass 13, count 2 2006.201.16:40:37.36#ibcon#about to read 6, iclass 13, count 2 2006.201.16:40:37.36#ibcon#read 6, iclass 13, count 2 2006.201.16:40:37.36#ibcon#end of sib2, iclass 13, count 2 2006.201.16:40:37.36#ibcon#*mode == 0, iclass 13, count 2 2006.201.16:40:37.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.16:40:37.36#ibcon#[27=AT06-04\r\n] 2006.201.16:40:37.36#ibcon#*before write, iclass 13, count 2 2006.201.16:40:37.36#ibcon#enter sib2, iclass 13, count 2 2006.201.16:40:37.36#ibcon#flushed, iclass 13, count 2 2006.201.16:40:37.36#ibcon#about to write, iclass 13, count 2 2006.201.16:40:37.36#ibcon#wrote, iclass 13, count 2 2006.201.16:40:37.36#ibcon#about to read 3, iclass 13, count 2 2006.201.16:40:37.39#ibcon#read 3, iclass 13, count 2 2006.201.16:40:37.39#ibcon#about to read 4, iclass 13, count 2 2006.201.16:40:37.39#ibcon#read 4, iclass 13, count 2 2006.201.16:40:37.39#ibcon#about to read 5, iclass 13, count 2 2006.201.16:40:37.39#ibcon#read 5, iclass 13, count 2 2006.201.16:40:37.39#ibcon#about to read 6, iclass 13, count 2 2006.201.16:40:37.39#ibcon#read 6, iclass 13, count 2 2006.201.16:40:37.39#ibcon#end of sib2, iclass 13, count 2 2006.201.16:40:37.39#ibcon#*after write, iclass 13, count 2 2006.201.16:40:37.39#ibcon#*before return 0, iclass 13, count 2 2006.201.16:40:37.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:37.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:40:37.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.16:40:37.39#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:37.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:37.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:37.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:37.51#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:40:37.51#ibcon#first serial, iclass 13, count 0 2006.201.16:40:37.51#ibcon#enter sib2, iclass 13, count 0 2006.201.16:40:37.51#ibcon#flushed, iclass 13, count 0 2006.201.16:40:37.51#ibcon#about to write, iclass 13, count 0 2006.201.16:40:37.51#ibcon#wrote, iclass 13, count 0 2006.201.16:40:37.51#ibcon#about to read 3, iclass 13, count 0 2006.201.16:40:37.53#ibcon#read 3, iclass 13, count 0 2006.201.16:40:37.53#ibcon#about to read 4, iclass 13, count 0 2006.201.16:40:37.53#ibcon#read 4, iclass 13, count 0 2006.201.16:40:37.53#ibcon#about to read 5, iclass 13, count 0 2006.201.16:40:37.53#ibcon#read 5, iclass 13, count 0 2006.201.16:40:37.53#ibcon#about to read 6, iclass 13, count 0 2006.201.16:40:37.53#ibcon#read 6, iclass 13, count 0 2006.201.16:40:37.53#ibcon#end of sib2, iclass 13, count 0 2006.201.16:40:37.53#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:40:37.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:40:37.53#ibcon#[27=USB\r\n] 2006.201.16:40:37.53#ibcon#*before write, iclass 13, count 0 2006.201.16:40:37.53#ibcon#enter sib2, iclass 13, count 0 2006.201.16:40:37.53#ibcon#flushed, iclass 13, count 0 2006.201.16:40:37.53#ibcon#about to write, iclass 13, count 0 2006.201.16:40:37.53#ibcon#wrote, iclass 13, count 0 2006.201.16:40:37.53#ibcon#about to read 3, iclass 13, count 0 2006.201.16:40:37.56#ibcon#read 3, iclass 13, count 0 2006.201.16:40:37.56#ibcon#about to read 4, iclass 13, count 0 2006.201.16:40:37.56#ibcon#read 4, iclass 13, count 0 2006.201.16:40:37.56#ibcon#about to read 5, iclass 13, count 0 2006.201.16:40:37.56#ibcon#read 5, iclass 13, count 0 2006.201.16:40:37.56#ibcon#about to read 6, iclass 13, count 0 2006.201.16:40:37.56#ibcon#read 6, iclass 13, count 0 2006.201.16:40:37.56#ibcon#end of sib2, iclass 13, count 0 2006.201.16:40:37.56#ibcon#*after write, iclass 13, count 0 2006.201.16:40:37.56#ibcon#*before return 0, iclass 13, count 0 2006.201.16:40:37.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:37.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:40:37.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:40:37.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:40:37.56$vck44/vblo=7,734.99 2006.201.16:40:37.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.16:40:37.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.16:40:37.56#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:37.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:37.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:37.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:37.56#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:40:37.56#ibcon#first serial, iclass 15, count 0 2006.201.16:40:37.56#ibcon#enter sib2, iclass 15, count 0 2006.201.16:40:37.56#ibcon#flushed, iclass 15, count 0 2006.201.16:40:37.56#ibcon#about to write, iclass 15, count 0 2006.201.16:40:37.56#ibcon#wrote, iclass 15, count 0 2006.201.16:40:37.56#ibcon#about to read 3, iclass 15, count 0 2006.201.16:40:37.58#ibcon#read 3, iclass 15, count 0 2006.201.16:40:37.58#ibcon#about to read 4, iclass 15, count 0 2006.201.16:40:37.58#ibcon#read 4, iclass 15, count 0 2006.201.16:40:37.58#ibcon#about to read 5, iclass 15, count 0 2006.201.16:40:37.58#ibcon#read 5, iclass 15, count 0 2006.201.16:40:37.58#ibcon#about to read 6, iclass 15, count 0 2006.201.16:40:37.58#ibcon#read 6, iclass 15, count 0 2006.201.16:40:37.58#ibcon#end of sib2, iclass 15, count 0 2006.201.16:40:37.58#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:40:37.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:40:37.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:40:37.58#ibcon#*before write, iclass 15, count 0 2006.201.16:40:37.58#ibcon#enter sib2, iclass 15, count 0 2006.201.16:40:37.58#ibcon#flushed, iclass 15, count 0 2006.201.16:40:37.58#ibcon#about to write, iclass 15, count 0 2006.201.16:40:37.58#ibcon#wrote, iclass 15, count 0 2006.201.16:40:37.58#ibcon#about to read 3, iclass 15, count 0 2006.201.16:40:37.62#ibcon#read 3, iclass 15, count 0 2006.201.16:40:37.62#ibcon#about to read 4, iclass 15, count 0 2006.201.16:40:37.62#ibcon#read 4, iclass 15, count 0 2006.201.16:40:37.62#ibcon#about to read 5, iclass 15, count 0 2006.201.16:40:37.62#ibcon#read 5, iclass 15, count 0 2006.201.16:40:37.62#ibcon#about to read 6, iclass 15, count 0 2006.201.16:40:37.62#ibcon#read 6, iclass 15, count 0 2006.201.16:40:37.62#ibcon#end of sib2, iclass 15, count 0 2006.201.16:40:37.62#ibcon#*after write, iclass 15, count 0 2006.201.16:40:37.62#ibcon#*before return 0, iclass 15, count 0 2006.201.16:40:37.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:37.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:40:37.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:40:37.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:40:37.62$vck44/vb=7,4 2006.201.16:40:37.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.16:40:37.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.16:40:37.62#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:37.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:37.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:37.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:37.68#ibcon#enter wrdev, iclass 17, count 2 2006.201.16:40:37.68#ibcon#first serial, iclass 17, count 2 2006.201.16:40:37.68#ibcon#enter sib2, iclass 17, count 2 2006.201.16:40:37.68#ibcon#flushed, iclass 17, count 2 2006.201.16:40:37.68#ibcon#about to write, iclass 17, count 2 2006.201.16:40:37.68#ibcon#wrote, iclass 17, count 2 2006.201.16:40:37.68#ibcon#about to read 3, iclass 17, count 2 2006.201.16:40:37.70#ibcon#read 3, iclass 17, count 2 2006.201.16:40:37.70#ibcon#about to read 4, iclass 17, count 2 2006.201.16:40:37.70#ibcon#read 4, iclass 17, count 2 2006.201.16:40:37.70#ibcon#about to read 5, iclass 17, count 2 2006.201.16:40:37.70#ibcon#read 5, iclass 17, count 2 2006.201.16:40:37.70#ibcon#about to read 6, iclass 17, count 2 2006.201.16:40:37.70#ibcon#read 6, iclass 17, count 2 2006.201.16:40:37.70#ibcon#end of sib2, iclass 17, count 2 2006.201.16:40:37.70#ibcon#*mode == 0, iclass 17, count 2 2006.201.16:40:37.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.16:40:37.70#ibcon#[27=AT07-04\r\n] 2006.201.16:40:37.70#ibcon#*before write, iclass 17, count 2 2006.201.16:40:37.70#ibcon#enter sib2, iclass 17, count 2 2006.201.16:40:37.70#ibcon#flushed, iclass 17, count 2 2006.201.16:40:37.70#ibcon#about to write, iclass 17, count 2 2006.201.16:40:37.70#ibcon#wrote, iclass 17, count 2 2006.201.16:40:37.70#ibcon#about to read 3, iclass 17, count 2 2006.201.16:40:37.73#ibcon#read 3, iclass 17, count 2 2006.201.16:40:37.73#ibcon#about to read 4, iclass 17, count 2 2006.201.16:40:37.73#ibcon#read 4, iclass 17, count 2 2006.201.16:40:37.73#ibcon#about to read 5, iclass 17, count 2 2006.201.16:40:37.73#ibcon#read 5, iclass 17, count 2 2006.201.16:40:37.73#ibcon#about to read 6, iclass 17, count 2 2006.201.16:40:37.73#ibcon#read 6, iclass 17, count 2 2006.201.16:40:37.73#ibcon#end of sib2, iclass 17, count 2 2006.201.16:40:37.73#ibcon#*after write, iclass 17, count 2 2006.201.16:40:37.73#ibcon#*before return 0, iclass 17, count 2 2006.201.16:40:37.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:37.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:40:37.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.16:40:37.73#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:37.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:37.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:37.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:37.85#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:40:37.85#ibcon#first serial, iclass 17, count 0 2006.201.16:40:37.85#ibcon#enter sib2, iclass 17, count 0 2006.201.16:40:37.85#ibcon#flushed, iclass 17, count 0 2006.201.16:40:37.85#ibcon#about to write, iclass 17, count 0 2006.201.16:40:37.85#ibcon#wrote, iclass 17, count 0 2006.201.16:40:37.85#ibcon#about to read 3, iclass 17, count 0 2006.201.16:40:37.87#ibcon#read 3, iclass 17, count 0 2006.201.16:40:37.87#ibcon#about to read 4, iclass 17, count 0 2006.201.16:40:37.87#ibcon#read 4, iclass 17, count 0 2006.201.16:40:37.87#ibcon#about to read 5, iclass 17, count 0 2006.201.16:40:37.87#ibcon#read 5, iclass 17, count 0 2006.201.16:40:37.87#ibcon#about to read 6, iclass 17, count 0 2006.201.16:40:37.87#ibcon#read 6, iclass 17, count 0 2006.201.16:40:37.87#ibcon#end of sib2, iclass 17, count 0 2006.201.16:40:37.87#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:40:37.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:40:37.87#ibcon#[27=USB\r\n] 2006.201.16:40:37.87#ibcon#*before write, iclass 17, count 0 2006.201.16:40:37.87#ibcon#enter sib2, iclass 17, count 0 2006.201.16:40:37.87#ibcon#flushed, iclass 17, count 0 2006.201.16:40:37.87#ibcon#about to write, iclass 17, count 0 2006.201.16:40:37.87#ibcon#wrote, iclass 17, count 0 2006.201.16:40:37.87#ibcon#about to read 3, iclass 17, count 0 2006.201.16:40:37.90#ibcon#read 3, iclass 17, count 0 2006.201.16:40:37.90#ibcon#about to read 4, iclass 17, count 0 2006.201.16:40:37.90#ibcon#read 4, iclass 17, count 0 2006.201.16:40:37.90#ibcon#about to read 5, iclass 17, count 0 2006.201.16:40:37.90#ibcon#read 5, iclass 17, count 0 2006.201.16:40:37.90#ibcon#about to read 6, iclass 17, count 0 2006.201.16:40:37.90#ibcon#read 6, iclass 17, count 0 2006.201.16:40:37.90#ibcon#end of sib2, iclass 17, count 0 2006.201.16:40:37.90#ibcon#*after write, iclass 17, count 0 2006.201.16:40:37.90#ibcon#*before return 0, iclass 17, count 0 2006.201.16:40:37.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:37.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:40:37.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:40:37.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:40:37.90$vck44/vblo=8,744.99 2006.201.16:40:37.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.16:40:37.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.16:40:37.90#ibcon#ireg 17 cls_cnt 0 2006.201.16:40:37.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:37.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:37.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:37.90#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:40:37.90#ibcon#first serial, iclass 19, count 0 2006.201.16:40:37.90#ibcon#enter sib2, iclass 19, count 0 2006.201.16:40:37.90#ibcon#flushed, iclass 19, count 0 2006.201.16:40:37.90#ibcon#about to write, iclass 19, count 0 2006.201.16:40:37.90#ibcon#wrote, iclass 19, count 0 2006.201.16:40:37.90#ibcon#about to read 3, iclass 19, count 0 2006.201.16:40:37.92#ibcon#read 3, iclass 19, count 0 2006.201.16:40:37.92#ibcon#about to read 4, iclass 19, count 0 2006.201.16:40:37.92#ibcon#read 4, iclass 19, count 0 2006.201.16:40:37.92#ibcon#about to read 5, iclass 19, count 0 2006.201.16:40:37.92#ibcon#read 5, iclass 19, count 0 2006.201.16:40:37.92#ibcon#about to read 6, iclass 19, count 0 2006.201.16:40:37.92#ibcon#read 6, iclass 19, count 0 2006.201.16:40:37.92#ibcon#end of sib2, iclass 19, count 0 2006.201.16:40:37.92#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:40:37.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:40:37.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:40:37.92#ibcon#*before write, iclass 19, count 0 2006.201.16:40:37.92#ibcon#enter sib2, iclass 19, count 0 2006.201.16:40:37.92#ibcon#flushed, iclass 19, count 0 2006.201.16:40:37.92#ibcon#about to write, iclass 19, count 0 2006.201.16:40:37.92#ibcon#wrote, iclass 19, count 0 2006.201.16:40:37.92#ibcon#about to read 3, iclass 19, count 0 2006.201.16:40:37.97#ibcon#read 3, iclass 19, count 0 2006.201.16:40:37.97#ibcon#about to read 4, iclass 19, count 0 2006.201.16:40:37.97#ibcon#read 4, iclass 19, count 0 2006.201.16:40:37.97#ibcon#about to read 5, iclass 19, count 0 2006.201.16:40:37.97#ibcon#read 5, iclass 19, count 0 2006.201.16:40:37.97#ibcon#about to read 6, iclass 19, count 0 2006.201.16:40:37.97#ibcon#read 6, iclass 19, count 0 2006.201.16:40:37.97#ibcon#end of sib2, iclass 19, count 0 2006.201.16:40:37.97#ibcon#*after write, iclass 19, count 0 2006.201.16:40:37.97#ibcon#*before return 0, iclass 19, count 0 2006.201.16:40:37.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:37.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:40:37.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:40:37.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:40:37.97$vck44/vb=8,4 2006.201.16:40:37.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.16:40:37.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.16:40:37.97#ibcon#ireg 11 cls_cnt 2 2006.201.16:40:37.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:38.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:38.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:38.02#ibcon#enter wrdev, iclass 21, count 2 2006.201.16:40:38.02#ibcon#first serial, iclass 21, count 2 2006.201.16:40:38.02#ibcon#enter sib2, iclass 21, count 2 2006.201.16:40:38.02#ibcon#flushed, iclass 21, count 2 2006.201.16:40:38.02#ibcon#about to write, iclass 21, count 2 2006.201.16:40:38.02#ibcon#wrote, iclass 21, count 2 2006.201.16:40:38.02#ibcon#about to read 3, iclass 21, count 2 2006.201.16:40:38.04#ibcon#read 3, iclass 21, count 2 2006.201.16:40:38.04#ibcon#about to read 4, iclass 21, count 2 2006.201.16:40:38.04#ibcon#read 4, iclass 21, count 2 2006.201.16:40:38.04#ibcon#about to read 5, iclass 21, count 2 2006.201.16:40:38.04#ibcon#read 5, iclass 21, count 2 2006.201.16:40:38.04#ibcon#about to read 6, iclass 21, count 2 2006.201.16:40:38.04#ibcon#read 6, iclass 21, count 2 2006.201.16:40:38.04#ibcon#end of sib2, iclass 21, count 2 2006.201.16:40:38.04#ibcon#*mode == 0, iclass 21, count 2 2006.201.16:40:38.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.16:40:38.04#ibcon#[27=AT08-04\r\n] 2006.201.16:40:38.04#ibcon#*before write, iclass 21, count 2 2006.201.16:40:38.04#ibcon#enter sib2, iclass 21, count 2 2006.201.16:40:38.04#ibcon#flushed, iclass 21, count 2 2006.201.16:40:38.04#ibcon#about to write, iclass 21, count 2 2006.201.16:40:38.04#ibcon#wrote, iclass 21, count 2 2006.201.16:40:38.04#ibcon#about to read 3, iclass 21, count 2 2006.201.16:40:38.07#ibcon#read 3, iclass 21, count 2 2006.201.16:40:38.07#ibcon#about to read 4, iclass 21, count 2 2006.201.16:40:38.07#ibcon#read 4, iclass 21, count 2 2006.201.16:40:38.07#ibcon#about to read 5, iclass 21, count 2 2006.201.16:40:38.07#ibcon#read 5, iclass 21, count 2 2006.201.16:40:38.07#ibcon#about to read 6, iclass 21, count 2 2006.201.16:40:38.07#ibcon#read 6, iclass 21, count 2 2006.201.16:40:38.07#ibcon#end of sib2, iclass 21, count 2 2006.201.16:40:38.07#ibcon#*after write, iclass 21, count 2 2006.201.16:40:38.07#ibcon#*before return 0, iclass 21, count 2 2006.201.16:40:38.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:38.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:40:38.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.16:40:38.07#ibcon#ireg 7 cls_cnt 0 2006.201.16:40:38.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:38.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:38.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:38.19#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:40:38.19#ibcon#first serial, iclass 21, count 0 2006.201.16:40:38.19#ibcon#enter sib2, iclass 21, count 0 2006.201.16:40:38.19#ibcon#flushed, iclass 21, count 0 2006.201.16:40:38.19#ibcon#about to write, iclass 21, count 0 2006.201.16:40:38.19#ibcon#wrote, iclass 21, count 0 2006.201.16:40:38.19#ibcon#about to read 3, iclass 21, count 0 2006.201.16:40:38.21#ibcon#read 3, iclass 21, count 0 2006.201.16:40:38.21#ibcon#about to read 4, iclass 21, count 0 2006.201.16:40:38.21#ibcon#read 4, iclass 21, count 0 2006.201.16:40:38.21#ibcon#about to read 5, iclass 21, count 0 2006.201.16:40:38.21#ibcon#read 5, iclass 21, count 0 2006.201.16:40:38.21#ibcon#about to read 6, iclass 21, count 0 2006.201.16:40:38.21#ibcon#read 6, iclass 21, count 0 2006.201.16:40:38.21#ibcon#end of sib2, iclass 21, count 0 2006.201.16:40:38.21#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:40:38.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:40:38.21#ibcon#[27=USB\r\n] 2006.201.16:40:38.21#ibcon#*before write, iclass 21, count 0 2006.201.16:40:38.21#ibcon#enter sib2, iclass 21, count 0 2006.201.16:40:38.21#ibcon#flushed, iclass 21, count 0 2006.201.16:40:38.21#ibcon#about to write, iclass 21, count 0 2006.201.16:40:38.21#ibcon#wrote, iclass 21, count 0 2006.201.16:40:38.21#ibcon#about to read 3, iclass 21, count 0 2006.201.16:40:38.24#ibcon#read 3, iclass 21, count 0 2006.201.16:40:38.24#ibcon#about to read 4, iclass 21, count 0 2006.201.16:40:38.24#ibcon#read 4, iclass 21, count 0 2006.201.16:40:38.24#ibcon#about to read 5, iclass 21, count 0 2006.201.16:40:38.24#ibcon#read 5, iclass 21, count 0 2006.201.16:40:38.24#ibcon#about to read 6, iclass 21, count 0 2006.201.16:40:38.24#ibcon#read 6, iclass 21, count 0 2006.201.16:40:38.24#ibcon#end of sib2, iclass 21, count 0 2006.201.16:40:38.24#ibcon#*after write, iclass 21, count 0 2006.201.16:40:38.24#ibcon#*before return 0, iclass 21, count 0 2006.201.16:40:38.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:38.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:40:38.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:40:38.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:40:38.24$vck44/vabw=wide 2006.201.16:40:38.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.16:40:38.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.16:40:38.24#ibcon#ireg 8 cls_cnt 0 2006.201.16:40:38.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:38.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:38.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:38.24#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:40:38.24#ibcon#first serial, iclass 23, count 0 2006.201.16:40:38.24#ibcon#enter sib2, iclass 23, count 0 2006.201.16:40:38.24#ibcon#flushed, iclass 23, count 0 2006.201.16:40:38.24#ibcon#about to write, iclass 23, count 0 2006.201.16:40:38.24#ibcon#wrote, iclass 23, count 0 2006.201.16:40:38.24#ibcon#about to read 3, iclass 23, count 0 2006.201.16:40:38.26#ibcon#read 3, iclass 23, count 0 2006.201.16:40:38.26#ibcon#about to read 4, iclass 23, count 0 2006.201.16:40:38.26#ibcon#read 4, iclass 23, count 0 2006.201.16:40:38.26#ibcon#about to read 5, iclass 23, count 0 2006.201.16:40:38.26#ibcon#read 5, iclass 23, count 0 2006.201.16:40:38.26#ibcon#about to read 6, iclass 23, count 0 2006.201.16:40:38.26#ibcon#read 6, iclass 23, count 0 2006.201.16:40:38.26#ibcon#end of sib2, iclass 23, count 0 2006.201.16:40:38.26#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:40:38.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:40:38.26#ibcon#[25=BW32\r\n] 2006.201.16:40:38.26#ibcon#*before write, iclass 23, count 0 2006.201.16:40:38.26#ibcon#enter sib2, iclass 23, count 0 2006.201.16:40:38.26#ibcon#flushed, iclass 23, count 0 2006.201.16:40:38.26#ibcon#about to write, iclass 23, count 0 2006.201.16:40:38.26#ibcon#wrote, iclass 23, count 0 2006.201.16:40:38.26#ibcon#about to read 3, iclass 23, count 0 2006.201.16:40:38.29#ibcon#read 3, iclass 23, count 0 2006.201.16:40:38.29#ibcon#about to read 4, iclass 23, count 0 2006.201.16:40:38.29#ibcon#read 4, iclass 23, count 0 2006.201.16:40:38.29#ibcon#about to read 5, iclass 23, count 0 2006.201.16:40:38.29#ibcon#read 5, iclass 23, count 0 2006.201.16:40:38.29#ibcon#about to read 6, iclass 23, count 0 2006.201.16:40:38.29#ibcon#read 6, iclass 23, count 0 2006.201.16:40:38.29#ibcon#end of sib2, iclass 23, count 0 2006.201.16:40:38.29#ibcon#*after write, iclass 23, count 0 2006.201.16:40:38.29#ibcon#*before return 0, iclass 23, count 0 2006.201.16:40:38.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:38.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:40:38.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:40:38.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:40:38.29$vck44/vbbw=wide 2006.201.16:40:38.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.16:40:38.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.16:40:38.29#ibcon#ireg 8 cls_cnt 0 2006.201.16:40:38.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:40:38.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:40:38.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:40:38.36#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:40:38.36#ibcon#first serial, iclass 25, count 0 2006.201.16:40:38.36#ibcon#enter sib2, iclass 25, count 0 2006.201.16:40:38.36#ibcon#flushed, iclass 25, count 0 2006.201.16:40:38.36#ibcon#about to write, iclass 25, count 0 2006.201.16:40:38.36#ibcon#wrote, iclass 25, count 0 2006.201.16:40:38.36#ibcon#about to read 3, iclass 25, count 0 2006.201.16:40:38.38#ibcon#read 3, iclass 25, count 0 2006.201.16:40:38.38#ibcon#about to read 4, iclass 25, count 0 2006.201.16:40:38.38#ibcon#read 4, iclass 25, count 0 2006.201.16:40:38.38#ibcon#about to read 5, iclass 25, count 0 2006.201.16:40:38.38#ibcon#read 5, iclass 25, count 0 2006.201.16:40:38.38#ibcon#about to read 6, iclass 25, count 0 2006.201.16:40:38.38#ibcon#read 6, iclass 25, count 0 2006.201.16:40:38.38#ibcon#end of sib2, iclass 25, count 0 2006.201.16:40:38.38#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:40:38.38#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:40:38.38#ibcon#[27=BW32\r\n] 2006.201.16:40:38.38#ibcon#*before write, iclass 25, count 0 2006.201.16:40:38.38#ibcon#enter sib2, iclass 25, count 0 2006.201.16:40:38.38#ibcon#flushed, iclass 25, count 0 2006.201.16:40:38.38#ibcon#about to write, iclass 25, count 0 2006.201.16:40:38.38#ibcon#wrote, iclass 25, count 0 2006.201.16:40:38.38#ibcon#about to read 3, iclass 25, count 0 2006.201.16:40:38.41#ibcon#read 3, iclass 25, count 0 2006.201.16:40:38.41#ibcon#about to read 4, iclass 25, count 0 2006.201.16:40:38.41#ibcon#read 4, iclass 25, count 0 2006.201.16:40:38.41#ibcon#about to read 5, iclass 25, count 0 2006.201.16:40:38.41#ibcon#read 5, iclass 25, count 0 2006.201.16:40:38.41#ibcon#about to read 6, iclass 25, count 0 2006.201.16:40:38.41#ibcon#read 6, iclass 25, count 0 2006.201.16:40:38.41#ibcon#end of sib2, iclass 25, count 0 2006.201.16:40:38.41#ibcon#*after write, iclass 25, count 0 2006.201.16:40:38.41#ibcon#*before return 0, iclass 25, count 0 2006.201.16:40:38.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:40:38.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:40:38.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:40:38.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:40:38.41$setupk4/ifdk4 2006.201.16:40:38.41$ifdk4/lo= 2006.201.16:40:38.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:40:38.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:40:38.41$ifdk4/patch= 2006.201.16:40:38.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:40:38.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:40:38.41$setupk4/!*+20s 2006.201.16:40:43.54#abcon#<5=/04 0.6 1.3 20.841001002.7\r\n> 2006.201.16:40:43.56#abcon#{5=INTERFACE CLEAR} 2006.201.16:40:43.62#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:40:48.14#trakl#Source acquired 2006.201.16:40:49.14#flagr#flagr/antenna,acquired 2006.201.16:40:52.90$setupk4/"tpicd 2006.201.16:40:52.90$setupk4/echo=off 2006.201.16:40:52.90$setupk4/xlog=off 2006.201.16:40:52.90:!2006.201.16:41:49 2006.201.16:41:49.00:preob 2006.201.16:41:50.14/onsource/TRACKING 2006.201.16:41:50.14:!2006.201.16:41:59 2006.201.16:41:59.00:"tape 2006.201.16:41:59.00:"st=record 2006.201.16:41:59.00:data_valid=on 2006.201.16:41:59.00:midob 2006.201.16:41:59.14/onsource/TRACKING 2006.201.16:41:59.14/wx/20.84,1002.7,100 2006.201.16:41:59.33/cable/+6.4769E-03 2006.201.16:42:00.42/va/01,08,usb,yes,36,39 2006.201.16:42:00.42/va/02,07,usb,yes,39,40 2006.201.16:42:00.42/va/03,08,usb,yes,35,37 2006.201.16:42:00.42/va/04,07,usb,yes,40,43 2006.201.16:42:00.42/va/05,04,usb,yes,36,37 2006.201.16:42:00.42/va/06,05,usb,yes,36,36 2006.201.16:42:00.42/va/07,05,usb,yes,35,36 2006.201.16:42:00.42/va/08,04,usb,yes,35,42 2006.201.16:42:00.65/valo/01,524.99,yes,locked 2006.201.16:42:00.65/valo/02,534.99,yes,locked 2006.201.16:42:00.65/valo/03,564.99,yes,locked 2006.201.16:42:00.65/valo/04,624.99,yes,locked 2006.201.16:42:00.65/valo/05,734.99,yes,locked 2006.201.16:42:00.65/valo/06,814.99,yes,locked 2006.201.16:42:00.65/valo/07,864.99,yes,locked 2006.201.16:42:00.65/valo/08,884.99,yes,locked 2006.201.16:42:01.74/vb/01,04,usb,yes,30,28 2006.201.16:42:01.74/vb/02,05,usb,yes,28,28 2006.201.16:42:01.74/vb/03,04,usb,yes,29,32 2006.201.16:42:01.74/vb/04,05,usb,yes,30,29 2006.201.16:42:01.74/vb/05,04,usb,yes,26,29 2006.201.16:42:01.74/vb/06,04,usb,yes,30,27 2006.201.16:42:01.74/vb/07,04,usb,yes,30,30 2006.201.16:42:01.74/vb/08,04,usb,yes,28,31 2006.201.16:42:01.98/vblo/01,629.99,yes,locked 2006.201.16:42:01.98/vblo/02,634.99,yes,locked 2006.201.16:42:01.98/vblo/03,649.99,yes,locked 2006.201.16:42:01.98/vblo/04,679.99,yes,locked 2006.201.16:42:01.98/vblo/05,709.99,yes,locked 2006.201.16:42:01.98/vblo/06,719.99,yes,locked 2006.201.16:42:01.98/vblo/07,734.99,yes,locked 2006.201.16:42:01.98/vblo/08,744.99,yes,locked 2006.201.16:42:02.13/vabw/8 2006.201.16:42:02.28/vbbw/8 2006.201.16:42:02.37/xfe/off,on,15.2 2006.201.16:42:02.74/ifatt/23,28,28,28 2006.201.16:42:03.06/fmout-gps/S +4.60E-07 2006.201.16:42:03.13:!2006.201.16:43:19 2006.201.16:43:19.00:data_valid=off 2006.201.16:43:19.00:"et 2006.201.16:43:19.00:!+3s 2006.201.16:43:22.02:"tape 2006.201.16:43:22.02:postob 2006.201.16:43:22.21/cable/+6.4780E-03 2006.201.16:43:22.21/wx/20.83,1002.7,100 2006.201.16:43:22.27/fmout-gps/S +4.61E-07 2006.201.16:43:22.27:scan_name=201-1647,jd0607,40 2006.201.16:43:22.27:source=1954-388,195800.00,-384506.4,2000.0,ccw 2006.201.16:43:23.14#flagr#flagr/antenna,new-source 2006.201.16:43:23.14:checkk5 2006.201.16:43:23.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:43:23.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:43:24.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:43:24.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:43:25.00/chk_obsdata//k5ts1/T2011641??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.16:43:25.36/chk_obsdata//k5ts2/T2011641??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.16:43:25.73/chk_obsdata//k5ts3/T2011641??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.16:43:26.10/chk_obsdata//k5ts4/T2011641??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.16:43:26.78/k5log//k5ts1_log_newline 2006.201.16:43:27.46/k5log//k5ts2_log_newline 2006.201.16:43:28.16/k5log//k5ts3_log_newline 2006.201.16:43:28.85/k5log//k5ts4_log_newline 2006.201.16:43:28.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:43:28.87:setupk4=1 2006.201.16:43:28.87$setupk4/echo=on 2006.201.16:43:28.87$setupk4/pcalon 2006.201.16:43:28.87$pcalon/"no phase cal control is implemented here 2006.201.16:43:28.87$setupk4/"tpicd=stop 2006.201.16:43:28.87$setupk4/"rec=synch_on 2006.201.16:43:28.87$setupk4/"rec_mode=128 2006.201.16:43:28.87$setupk4/!* 2006.201.16:43:28.87$setupk4/recpk4 2006.201.16:43:28.87$recpk4/recpatch= 2006.201.16:43:28.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:43:28.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:43:28.88$setupk4/vck44 2006.201.16:43:28.88$vck44/valo=1,524.99 2006.201.16:43:28.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.16:43:28.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.16:43:28.88#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:28.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:28.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:28.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:28.88#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:43:28.88#ibcon#first serial, iclass 17, count 0 2006.201.16:43:28.88#ibcon#enter sib2, iclass 17, count 0 2006.201.16:43:28.88#ibcon#flushed, iclass 17, count 0 2006.201.16:43:28.88#ibcon#about to write, iclass 17, count 0 2006.201.16:43:28.88#ibcon#wrote, iclass 17, count 0 2006.201.16:43:28.88#ibcon#about to read 3, iclass 17, count 0 2006.201.16:43:28.91#ibcon#read 3, iclass 17, count 0 2006.201.16:43:28.91#ibcon#about to read 4, iclass 17, count 0 2006.201.16:43:28.91#ibcon#read 4, iclass 17, count 0 2006.201.16:43:28.91#ibcon#about to read 5, iclass 17, count 0 2006.201.16:43:28.91#ibcon#read 5, iclass 17, count 0 2006.201.16:43:28.91#ibcon#about to read 6, iclass 17, count 0 2006.201.16:43:28.91#ibcon#read 6, iclass 17, count 0 2006.201.16:43:28.91#ibcon#end of sib2, iclass 17, count 0 2006.201.16:43:28.91#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:43:28.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:43:28.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:43:28.91#ibcon#*before write, iclass 17, count 0 2006.201.16:43:28.91#ibcon#enter sib2, iclass 17, count 0 2006.201.16:43:28.91#ibcon#flushed, iclass 17, count 0 2006.201.16:43:28.91#ibcon#about to write, iclass 17, count 0 2006.201.16:43:28.91#ibcon#wrote, iclass 17, count 0 2006.201.16:43:28.91#ibcon#about to read 3, iclass 17, count 0 2006.201.16:43:28.96#ibcon#read 3, iclass 17, count 0 2006.201.16:43:28.96#ibcon#about to read 4, iclass 17, count 0 2006.201.16:43:28.96#ibcon#read 4, iclass 17, count 0 2006.201.16:43:28.96#ibcon#about to read 5, iclass 17, count 0 2006.201.16:43:28.96#ibcon#read 5, iclass 17, count 0 2006.201.16:43:28.96#ibcon#about to read 6, iclass 17, count 0 2006.201.16:43:28.96#ibcon#read 6, iclass 17, count 0 2006.201.16:43:28.96#ibcon#end of sib2, iclass 17, count 0 2006.201.16:43:28.96#ibcon#*after write, iclass 17, count 0 2006.201.16:43:28.96#ibcon#*before return 0, iclass 17, count 0 2006.201.16:43:28.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:28.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:28.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:43:28.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:43:28.96$vck44/va=1,8 2006.201.16:43:28.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.16:43:28.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.16:43:28.96#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:28.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:28.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:28.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:28.96#ibcon#enter wrdev, iclass 19, count 2 2006.201.16:43:28.96#ibcon#first serial, iclass 19, count 2 2006.201.16:43:28.96#ibcon#enter sib2, iclass 19, count 2 2006.201.16:43:28.96#ibcon#flushed, iclass 19, count 2 2006.201.16:43:28.96#ibcon#about to write, iclass 19, count 2 2006.201.16:43:28.96#ibcon#wrote, iclass 19, count 2 2006.201.16:43:28.96#ibcon#about to read 3, iclass 19, count 2 2006.201.16:43:28.98#ibcon#read 3, iclass 19, count 2 2006.201.16:43:28.98#ibcon#about to read 4, iclass 19, count 2 2006.201.16:43:28.98#ibcon#read 4, iclass 19, count 2 2006.201.16:43:28.98#ibcon#about to read 5, iclass 19, count 2 2006.201.16:43:28.98#ibcon#read 5, iclass 19, count 2 2006.201.16:43:28.98#ibcon#about to read 6, iclass 19, count 2 2006.201.16:43:28.98#ibcon#read 6, iclass 19, count 2 2006.201.16:43:28.98#ibcon#end of sib2, iclass 19, count 2 2006.201.16:43:28.98#ibcon#*mode == 0, iclass 19, count 2 2006.201.16:43:28.98#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.16:43:28.98#ibcon#[25=AT01-08\r\n] 2006.201.16:43:28.98#ibcon#*before write, iclass 19, count 2 2006.201.16:43:28.98#ibcon#enter sib2, iclass 19, count 2 2006.201.16:43:28.98#ibcon#flushed, iclass 19, count 2 2006.201.16:43:28.98#ibcon#about to write, iclass 19, count 2 2006.201.16:43:28.98#ibcon#wrote, iclass 19, count 2 2006.201.16:43:28.98#ibcon#about to read 3, iclass 19, count 2 2006.201.16:43:29.01#ibcon#read 3, iclass 19, count 2 2006.201.16:43:29.01#ibcon#about to read 4, iclass 19, count 2 2006.201.16:43:29.01#ibcon#read 4, iclass 19, count 2 2006.201.16:43:29.01#ibcon#about to read 5, iclass 19, count 2 2006.201.16:43:29.01#ibcon#read 5, iclass 19, count 2 2006.201.16:43:29.01#ibcon#about to read 6, iclass 19, count 2 2006.201.16:43:29.01#ibcon#read 6, iclass 19, count 2 2006.201.16:43:29.01#ibcon#end of sib2, iclass 19, count 2 2006.201.16:43:29.01#ibcon#*after write, iclass 19, count 2 2006.201.16:43:29.01#ibcon#*before return 0, iclass 19, count 2 2006.201.16:43:29.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:29.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:29.01#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.16:43:29.01#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:29.01#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:29.09#abcon#<5=/04 0.4 1.1 20.831001002.6\r\n> 2006.201.16:43:29.11#abcon#{5=INTERFACE CLEAR} 2006.201.16:43:29.13#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:29.13#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:29.13#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:43:29.13#ibcon#first serial, iclass 19, count 0 2006.201.16:43:29.13#ibcon#enter sib2, iclass 19, count 0 2006.201.16:43:29.13#ibcon#flushed, iclass 19, count 0 2006.201.16:43:29.13#ibcon#about to write, iclass 19, count 0 2006.201.16:43:29.13#ibcon#wrote, iclass 19, count 0 2006.201.16:43:29.13#ibcon#about to read 3, iclass 19, count 0 2006.201.16:43:29.15#ibcon#read 3, iclass 19, count 0 2006.201.16:43:29.15#ibcon#about to read 4, iclass 19, count 0 2006.201.16:43:29.15#ibcon#read 4, iclass 19, count 0 2006.201.16:43:29.15#ibcon#about to read 5, iclass 19, count 0 2006.201.16:43:29.15#ibcon#read 5, iclass 19, count 0 2006.201.16:43:29.15#ibcon#about to read 6, iclass 19, count 0 2006.201.16:43:29.15#ibcon#read 6, iclass 19, count 0 2006.201.16:43:29.15#ibcon#end of sib2, iclass 19, count 0 2006.201.16:43:29.15#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:43:29.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:43:29.15#ibcon#[25=USB\r\n] 2006.201.16:43:29.15#ibcon#*before write, iclass 19, count 0 2006.201.16:43:29.15#ibcon#enter sib2, iclass 19, count 0 2006.201.16:43:29.15#ibcon#flushed, iclass 19, count 0 2006.201.16:43:29.15#ibcon#about to write, iclass 19, count 0 2006.201.16:43:29.15#ibcon#wrote, iclass 19, count 0 2006.201.16:43:29.15#ibcon#about to read 3, iclass 19, count 0 2006.201.16:43:29.17#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:43:29.18#ibcon#read 3, iclass 19, count 0 2006.201.16:43:29.18#ibcon#about to read 4, iclass 19, count 0 2006.201.16:43:29.18#ibcon#read 4, iclass 19, count 0 2006.201.16:43:29.18#ibcon#about to read 5, iclass 19, count 0 2006.201.16:43:29.18#ibcon#read 5, iclass 19, count 0 2006.201.16:43:29.18#ibcon#about to read 6, iclass 19, count 0 2006.201.16:43:29.18#ibcon#read 6, iclass 19, count 0 2006.201.16:43:29.18#ibcon#end of sib2, iclass 19, count 0 2006.201.16:43:29.18#ibcon#*after write, iclass 19, count 0 2006.201.16:43:29.18#ibcon#*before return 0, iclass 19, count 0 2006.201.16:43:29.18#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:29.18#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:29.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:43:29.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:43:29.18$vck44/valo=2,534.99 2006.201.16:43:29.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.16:43:29.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.16:43:29.18#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:29.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:29.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:29.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:29.18#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:43:29.18#ibcon#first serial, iclass 25, count 0 2006.201.16:43:29.18#ibcon#enter sib2, iclass 25, count 0 2006.201.16:43:29.18#ibcon#flushed, iclass 25, count 0 2006.201.16:43:29.18#ibcon#about to write, iclass 25, count 0 2006.201.16:43:29.18#ibcon#wrote, iclass 25, count 0 2006.201.16:43:29.18#ibcon#about to read 3, iclass 25, count 0 2006.201.16:43:29.20#ibcon#read 3, iclass 25, count 0 2006.201.16:43:29.20#ibcon#about to read 4, iclass 25, count 0 2006.201.16:43:29.20#ibcon#read 4, iclass 25, count 0 2006.201.16:43:29.20#ibcon#about to read 5, iclass 25, count 0 2006.201.16:43:29.20#ibcon#read 5, iclass 25, count 0 2006.201.16:43:29.20#ibcon#about to read 6, iclass 25, count 0 2006.201.16:43:29.20#ibcon#read 6, iclass 25, count 0 2006.201.16:43:29.20#ibcon#end of sib2, iclass 25, count 0 2006.201.16:43:29.20#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:43:29.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:43:29.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:43:29.20#ibcon#*before write, iclass 25, count 0 2006.201.16:43:29.20#ibcon#enter sib2, iclass 25, count 0 2006.201.16:43:29.20#ibcon#flushed, iclass 25, count 0 2006.201.16:43:29.20#ibcon#about to write, iclass 25, count 0 2006.201.16:43:29.20#ibcon#wrote, iclass 25, count 0 2006.201.16:43:29.20#ibcon#about to read 3, iclass 25, count 0 2006.201.16:43:29.24#ibcon#read 3, iclass 25, count 0 2006.201.16:43:29.24#ibcon#about to read 4, iclass 25, count 0 2006.201.16:43:29.24#ibcon#read 4, iclass 25, count 0 2006.201.16:43:29.24#ibcon#about to read 5, iclass 25, count 0 2006.201.16:43:29.24#ibcon#read 5, iclass 25, count 0 2006.201.16:43:29.24#ibcon#about to read 6, iclass 25, count 0 2006.201.16:43:29.24#ibcon#read 6, iclass 25, count 0 2006.201.16:43:29.24#ibcon#end of sib2, iclass 25, count 0 2006.201.16:43:29.24#ibcon#*after write, iclass 25, count 0 2006.201.16:43:29.24#ibcon#*before return 0, iclass 25, count 0 2006.201.16:43:29.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:29.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:29.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:43:29.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:43:29.24$vck44/va=2,7 2006.201.16:43:29.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.16:43:29.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.16:43:29.24#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:29.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:29.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:29.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:29.30#ibcon#enter wrdev, iclass 27, count 2 2006.201.16:43:29.30#ibcon#first serial, iclass 27, count 2 2006.201.16:43:29.30#ibcon#enter sib2, iclass 27, count 2 2006.201.16:43:29.30#ibcon#flushed, iclass 27, count 2 2006.201.16:43:29.30#ibcon#about to write, iclass 27, count 2 2006.201.16:43:29.30#ibcon#wrote, iclass 27, count 2 2006.201.16:43:29.30#ibcon#about to read 3, iclass 27, count 2 2006.201.16:43:29.32#ibcon#read 3, iclass 27, count 2 2006.201.16:43:29.32#ibcon#about to read 4, iclass 27, count 2 2006.201.16:43:29.32#ibcon#read 4, iclass 27, count 2 2006.201.16:43:29.32#ibcon#about to read 5, iclass 27, count 2 2006.201.16:43:29.32#ibcon#read 5, iclass 27, count 2 2006.201.16:43:29.32#ibcon#about to read 6, iclass 27, count 2 2006.201.16:43:29.32#ibcon#read 6, iclass 27, count 2 2006.201.16:43:29.32#ibcon#end of sib2, iclass 27, count 2 2006.201.16:43:29.32#ibcon#*mode == 0, iclass 27, count 2 2006.201.16:43:29.32#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.16:43:29.32#ibcon#[25=AT02-07\r\n] 2006.201.16:43:29.32#ibcon#*before write, iclass 27, count 2 2006.201.16:43:29.32#ibcon#enter sib2, iclass 27, count 2 2006.201.16:43:29.32#ibcon#flushed, iclass 27, count 2 2006.201.16:43:29.32#ibcon#about to write, iclass 27, count 2 2006.201.16:43:29.32#ibcon#wrote, iclass 27, count 2 2006.201.16:43:29.32#ibcon#about to read 3, iclass 27, count 2 2006.201.16:43:29.35#ibcon#read 3, iclass 27, count 2 2006.201.16:43:29.35#ibcon#about to read 4, iclass 27, count 2 2006.201.16:43:29.35#ibcon#read 4, iclass 27, count 2 2006.201.16:43:29.35#ibcon#about to read 5, iclass 27, count 2 2006.201.16:43:29.35#ibcon#read 5, iclass 27, count 2 2006.201.16:43:29.35#ibcon#about to read 6, iclass 27, count 2 2006.201.16:43:29.35#ibcon#read 6, iclass 27, count 2 2006.201.16:43:29.35#ibcon#end of sib2, iclass 27, count 2 2006.201.16:43:29.35#ibcon#*after write, iclass 27, count 2 2006.201.16:43:29.35#ibcon#*before return 0, iclass 27, count 2 2006.201.16:43:29.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:29.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:29.35#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.16:43:29.35#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:29.35#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:29.47#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:29.47#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:29.47#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:43:29.47#ibcon#first serial, iclass 27, count 0 2006.201.16:43:29.47#ibcon#enter sib2, iclass 27, count 0 2006.201.16:43:29.47#ibcon#flushed, iclass 27, count 0 2006.201.16:43:29.47#ibcon#about to write, iclass 27, count 0 2006.201.16:43:29.47#ibcon#wrote, iclass 27, count 0 2006.201.16:43:29.47#ibcon#about to read 3, iclass 27, count 0 2006.201.16:43:29.49#ibcon#read 3, iclass 27, count 0 2006.201.16:43:29.49#ibcon#about to read 4, iclass 27, count 0 2006.201.16:43:29.49#ibcon#read 4, iclass 27, count 0 2006.201.16:43:29.49#ibcon#about to read 5, iclass 27, count 0 2006.201.16:43:29.49#ibcon#read 5, iclass 27, count 0 2006.201.16:43:29.49#ibcon#about to read 6, iclass 27, count 0 2006.201.16:43:29.49#ibcon#read 6, iclass 27, count 0 2006.201.16:43:29.49#ibcon#end of sib2, iclass 27, count 0 2006.201.16:43:29.49#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:43:29.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:43:29.49#ibcon#[25=USB\r\n] 2006.201.16:43:29.49#ibcon#*before write, iclass 27, count 0 2006.201.16:43:29.49#ibcon#enter sib2, iclass 27, count 0 2006.201.16:43:29.49#ibcon#flushed, iclass 27, count 0 2006.201.16:43:29.49#ibcon#about to write, iclass 27, count 0 2006.201.16:43:29.49#ibcon#wrote, iclass 27, count 0 2006.201.16:43:29.49#ibcon#about to read 3, iclass 27, count 0 2006.201.16:43:29.52#ibcon#read 3, iclass 27, count 0 2006.201.16:43:29.52#ibcon#about to read 4, iclass 27, count 0 2006.201.16:43:29.52#ibcon#read 4, iclass 27, count 0 2006.201.16:43:29.52#ibcon#about to read 5, iclass 27, count 0 2006.201.16:43:29.52#ibcon#read 5, iclass 27, count 0 2006.201.16:43:29.52#ibcon#about to read 6, iclass 27, count 0 2006.201.16:43:29.52#ibcon#read 6, iclass 27, count 0 2006.201.16:43:29.52#ibcon#end of sib2, iclass 27, count 0 2006.201.16:43:29.52#ibcon#*after write, iclass 27, count 0 2006.201.16:43:29.52#ibcon#*before return 0, iclass 27, count 0 2006.201.16:43:29.52#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:29.52#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:29.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:43:29.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:43:29.52$vck44/valo=3,564.99 2006.201.16:43:29.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.16:43:29.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.16:43:29.52#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:29.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:29.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:29.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:29.52#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:43:29.52#ibcon#first serial, iclass 29, count 0 2006.201.16:43:29.52#ibcon#enter sib2, iclass 29, count 0 2006.201.16:43:29.52#ibcon#flushed, iclass 29, count 0 2006.201.16:43:29.52#ibcon#about to write, iclass 29, count 0 2006.201.16:43:29.52#ibcon#wrote, iclass 29, count 0 2006.201.16:43:29.52#ibcon#about to read 3, iclass 29, count 0 2006.201.16:43:29.54#ibcon#read 3, iclass 29, count 0 2006.201.16:43:29.54#ibcon#about to read 4, iclass 29, count 0 2006.201.16:43:29.54#ibcon#read 4, iclass 29, count 0 2006.201.16:43:29.54#ibcon#about to read 5, iclass 29, count 0 2006.201.16:43:29.54#ibcon#read 5, iclass 29, count 0 2006.201.16:43:29.54#ibcon#about to read 6, iclass 29, count 0 2006.201.16:43:29.54#ibcon#read 6, iclass 29, count 0 2006.201.16:43:29.54#ibcon#end of sib2, iclass 29, count 0 2006.201.16:43:29.54#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:43:29.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:43:29.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:43:29.54#ibcon#*before write, iclass 29, count 0 2006.201.16:43:29.54#ibcon#enter sib2, iclass 29, count 0 2006.201.16:43:29.54#ibcon#flushed, iclass 29, count 0 2006.201.16:43:29.54#ibcon#about to write, iclass 29, count 0 2006.201.16:43:29.54#ibcon#wrote, iclass 29, count 0 2006.201.16:43:29.54#ibcon#about to read 3, iclass 29, count 0 2006.201.16:43:29.59#ibcon#read 3, iclass 29, count 0 2006.201.16:43:29.59#ibcon#about to read 4, iclass 29, count 0 2006.201.16:43:29.59#ibcon#read 4, iclass 29, count 0 2006.201.16:43:29.59#ibcon#about to read 5, iclass 29, count 0 2006.201.16:43:29.59#ibcon#read 5, iclass 29, count 0 2006.201.16:43:29.59#ibcon#about to read 6, iclass 29, count 0 2006.201.16:43:29.59#ibcon#read 6, iclass 29, count 0 2006.201.16:43:29.59#ibcon#end of sib2, iclass 29, count 0 2006.201.16:43:29.59#ibcon#*after write, iclass 29, count 0 2006.201.16:43:29.59#ibcon#*before return 0, iclass 29, count 0 2006.201.16:43:29.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:29.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:29.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:43:29.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:43:29.59$vck44/va=3,8 2006.201.16:43:29.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.16:43:29.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.16:43:29.59#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:29.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:29.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:29.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:29.64#ibcon#enter wrdev, iclass 31, count 2 2006.201.16:43:29.64#ibcon#first serial, iclass 31, count 2 2006.201.16:43:29.64#ibcon#enter sib2, iclass 31, count 2 2006.201.16:43:29.64#ibcon#flushed, iclass 31, count 2 2006.201.16:43:29.64#ibcon#about to write, iclass 31, count 2 2006.201.16:43:29.64#ibcon#wrote, iclass 31, count 2 2006.201.16:43:29.64#ibcon#about to read 3, iclass 31, count 2 2006.201.16:43:29.66#ibcon#read 3, iclass 31, count 2 2006.201.16:43:29.66#ibcon#about to read 4, iclass 31, count 2 2006.201.16:43:29.66#ibcon#read 4, iclass 31, count 2 2006.201.16:43:29.66#ibcon#about to read 5, iclass 31, count 2 2006.201.16:43:29.66#ibcon#read 5, iclass 31, count 2 2006.201.16:43:29.66#ibcon#about to read 6, iclass 31, count 2 2006.201.16:43:29.66#ibcon#read 6, iclass 31, count 2 2006.201.16:43:29.66#ibcon#end of sib2, iclass 31, count 2 2006.201.16:43:29.66#ibcon#*mode == 0, iclass 31, count 2 2006.201.16:43:29.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.16:43:29.66#ibcon#[25=AT03-08\r\n] 2006.201.16:43:29.66#ibcon#*before write, iclass 31, count 2 2006.201.16:43:29.66#ibcon#enter sib2, iclass 31, count 2 2006.201.16:43:29.66#ibcon#flushed, iclass 31, count 2 2006.201.16:43:29.66#ibcon#about to write, iclass 31, count 2 2006.201.16:43:29.66#ibcon#wrote, iclass 31, count 2 2006.201.16:43:29.66#ibcon#about to read 3, iclass 31, count 2 2006.201.16:43:29.69#ibcon#read 3, iclass 31, count 2 2006.201.16:43:29.69#ibcon#about to read 4, iclass 31, count 2 2006.201.16:43:29.69#ibcon#read 4, iclass 31, count 2 2006.201.16:43:29.69#ibcon#about to read 5, iclass 31, count 2 2006.201.16:43:29.69#ibcon#read 5, iclass 31, count 2 2006.201.16:43:29.69#ibcon#about to read 6, iclass 31, count 2 2006.201.16:43:29.69#ibcon#read 6, iclass 31, count 2 2006.201.16:43:29.69#ibcon#end of sib2, iclass 31, count 2 2006.201.16:43:29.69#ibcon#*after write, iclass 31, count 2 2006.201.16:43:29.69#ibcon#*before return 0, iclass 31, count 2 2006.201.16:43:29.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:29.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:29.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.16:43:29.69#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:29.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:29.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:29.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:29.81#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:43:29.81#ibcon#first serial, iclass 31, count 0 2006.201.16:43:29.81#ibcon#enter sib2, iclass 31, count 0 2006.201.16:43:29.81#ibcon#flushed, iclass 31, count 0 2006.201.16:43:29.81#ibcon#about to write, iclass 31, count 0 2006.201.16:43:29.81#ibcon#wrote, iclass 31, count 0 2006.201.16:43:29.81#ibcon#about to read 3, iclass 31, count 0 2006.201.16:43:29.83#ibcon#read 3, iclass 31, count 0 2006.201.16:43:29.83#ibcon#about to read 4, iclass 31, count 0 2006.201.16:43:29.83#ibcon#read 4, iclass 31, count 0 2006.201.16:43:29.83#ibcon#about to read 5, iclass 31, count 0 2006.201.16:43:29.83#ibcon#read 5, iclass 31, count 0 2006.201.16:43:29.83#ibcon#about to read 6, iclass 31, count 0 2006.201.16:43:29.83#ibcon#read 6, iclass 31, count 0 2006.201.16:43:29.83#ibcon#end of sib2, iclass 31, count 0 2006.201.16:43:29.83#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:43:29.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:43:29.83#ibcon#[25=USB\r\n] 2006.201.16:43:29.83#ibcon#*before write, iclass 31, count 0 2006.201.16:43:29.83#ibcon#enter sib2, iclass 31, count 0 2006.201.16:43:29.83#ibcon#flushed, iclass 31, count 0 2006.201.16:43:29.83#ibcon#about to write, iclass 31, count 0 2006.201.16:43:29.83#ibcon#wrote, iclass 31, count 0 2006.201.16:43:29.83#ibcon#about to read 3, iclass 31, count 0 2006.201.16:43:29.86#ibcon#read 3, iclass 31, count 0 2006.201.16:43:29.86#ibcon#about to read 4, iclass 31, count 0 2006.201.16:43:29.86#ibcon#read 4, iclass 31, count 0 2006.201.16:43:29.86#ibcon#about to read 5, iclass 31, count 0 2006.201.16:43:29.86#ibcon#read 5, iclass 31, count 0 2006.201.16:43:29.86#ibcon#about to read 6, iclass 31, count 0 2006.201.16:43:29.86#ibcon#read 6, iclass 31, count 0 2006.201.16:43:29.86#ibcon#end of sib2, iclass 31, count 0 2006.201.16:43:29.86#ibcon#*after write, iclass 31, count 0 2006.201.16:43:29.86#ibcon#*before return 0, iclass 31, count 0 2006.201.16:43:29.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:29.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:29.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:43:29.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:43:29.86$vck44/valo=4,624.99 2006.201.16:43:29.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.16:43:29.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.16:43:29.86#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:29.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:29.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:29.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:29.86#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:43:29.86#ibcon#first serial, iclass 33, count 0 2006.201.16:43:29.86#ibcon#enter sib2, iclass 33, count 0 2006.201.16:43:29.86#ibcon#flushed, iclass 33, count 0 2006.201.16:43:29.86#ibcon#about to write, iclass 33, count 0 2006.201.16:43:29.86#ibcon#wrote, iclass 33, count 0 2006.201.16:43:29.86#ibcon#about to read 3, iclass 33, count 0 2006.201.16:43:29.88#ibcon#read 3, iclass 33, count 0 2006.201.16:43:29.88#ibcon#about to read 4, iclass 33, count 0 2006.201.16:43:29.88#ibcon#read 4, iclass 33, count 0 2006.201.16:43:29.88#ibcon#about to read 5, iclass 33, count 0 2006.201.16:43:29.88#ibcon#read 5, iclass 33, count 0 2006.201.16:43:29.88#ibcon#about to read 6, iclass 33, count 0 2006.201.16:43:29.88#ibcon#read 6, iclass 33, count 0 2006.201.16:43:29.88#ibcon#end of sib2, iclass 33, count 0 2006.201.16:43:29.88#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:43:29.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:43:29.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:43:29.88#ibcon#*before write, iclass 33, count 0 2006.201.16:43:29.88#ibcon#enter sib2, iclass 33, count 0 2006.201.16:43:29.88#ibcon#flushed, iclass 33, count 0 2006.201.16:43:29.88#ibcon#about to write, iclass 33, count 0 2006.201.16:43:29.88#ibcon#wrote, iclass 33, count 0 2006.201.16:43:29.88#ibcon#about to read 3, iclass 33, count 0 2006.201.16:43:29.93#ibcon#read 3, iclass 33, count 0 2006.201.16:43:29.93#ibcon#about to read 4, iclass 33, count 0 2006.201.16:43:29.93#ibcon#read 4, iclass 33, count 0 2006.201.16:43:29.93#ibcon#about to read 5, iclass 33, count 0 2006.201.16:43:29.93#ibcon#read 5, iclass 33, count 0 2006.201.16:43:29.93#ibcon#about to read 6, iclass 33, count 0 2006.201.16:43:29.93#ibcon#read 6, iclass 33, count 0 2006.201.16:43:29.93#ibcon#end of sib2, iclass 33, count 0 2006.201.16:43:29.93#ibcon#*after write, iclass 33, count 0 2006.201.16:43:29.93#ibcon#*before return 0, iclass 33, count 0 2006.201.16:43:29.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:29.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:29.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:43:29.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:43:29.93$vck44/va=4,7 2006.201.16:43:29.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.16:43:29.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.16:43:29.93#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:29.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:29.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:29.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:29.98#ibcon#enter wrdev, iclass 35, count 2 2006.201.16:43:29.98#ibcon#first serial, iclass 35, count 2 2006.201.16:43:29.98#ibcon#enter sib2, iclass 35, count 2 2006.201.16:43:29.98#ibcon#flushed, iclass 35, count 2 2006.201.16:43:29.98#ibcon#about to write, iclass 35, count 2 2006.201.16:43:29.98#ibcon#wrote, iclass 35, count 2 2006.201.16:43:29.98#ibcon#about to read 3, iclass 35, count 2 2006.201.16:43:30.00#ibcon#read 3, iclass 35, count 2 2006.201.16:43:30.00#ibcon#about to read 4, iclass 35, count 2 2006.201.16:43:30.00#ibcon#read 4, iclass 35, count 2 2006.201.16:43:30.00#ibcon#about to read 5, iclass 35, count 2 2006.201.16:43:30.00#ibcon#read 5, iclass 35, count 2 2006.201.16:43:30.00#ibcon#about to read 6, iclass 35, count 2 2006.201.16:43:30.00#ibcon#read 6, iclass 35, count 2 2006.201.16:43:30.00#ibcon#end of sib2, iclass 35, count 2 2006.201.16:43:30.00#ibcon#*mode == 0, iclass 35, count 2 2006.201.16:43:30.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.16:43:30.00#ibcon#[25=AT04-07\r\n] 2006.201.16:43:30.00#ibcon#*before write, iclass 35, count 2 2006.201.16:43:30.00#ibcon#enter sib2, iclass 35, count 2 2006.201.16:43:30.00#ibcon#flushed, iclass 35, count 2 2006.201.16:43:30.00#ibcon#about to write, iclass 35, count 2 2006.201.16:43:30.00#ibcon#wrote, iclass 35, count 2 2006.201.16:43:30.00#ibcon#about to read 3, iclass 35, count 2 2006.201.16:43:30.03#ibcon#read 3, iclass 35, count 2 2006.201.16:43:30.03#ibcon#about to read 4, iclass 35, count 2 2006.201.16:43:30.03#ibcon#read 4, iclass 35, count 2 2006.201.16:43:30.03#ibcon#about to read 5, iclass 35, count 2 2006.201.16:43:30.03#ibcon#read 5, iclass 35, count 2 2006.201.16:43:30.03#ibcon#about to read 6, iclass 35, count 2 2006.201.16:43:30.03#ibcon#read 6, iclass 35, count 2 2006.201.16:43:30.03#ibcon#end of sib2, iclass 35, count 2 2006.201.16:43:30.03#ibcon#*after write, iclass 35, count 2 2006.201.16:43:30.03#ibcon#*before return 0, iclass 35, count 2 2006.201.16:43:30.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:30.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:30.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.16:43:30.03#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:30.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:30.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:30.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:30.15#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:43:30.15#ibcon#first serial, iclass 35, count 0 2006.201.16:43:30.15#ibcon#enter sib2, iclass 35, count 0 2006.201.16:43:30.15#ibcon#flushed, iclass 35, count 0 2006.201.16:43:30.15#ibcon#about to write, iclass 35, count 0 2006.201.16:43:30.15#ibcon#wrote, iclass 35, count 0 2006.201.16:43:30.15#ibcon#about to read 3, iclass 35, count 0 2006.201.16:43:30.17#ibcon#read 3, iclass 35, count 0 2006.201.16:43:30.17#ibcon#about to read 4, iclass 35, count 0 2006.201.16:43:30.17#ibcon#read 4, iclass 35, count 0 2006.201.16:43:30.17#ibcon#about to read 5, iclass 35, count 0 2006.201.16:43:30.17#ibcon#read 5, iclass 35, count 0 2006.201.16:43:30.17#ibcon#about to read 6, iclass 35, count 0 2006.201.16:43:30.17#ibcon#read 6, iclass 35, count 0 2006.201.16:43:30.17#ibcon#end of sib2, iclass 35, count 0 2006.201.16:43:30.17#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:43:30.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:43:30.17#ibcon#[25=USB\r\n] 2006.201.16:43:30.17#ibcon#*before write, iclass 35, count 0 2006.201.16:43:30.17#ibcon#enter sib2, iclass 35, count 0 2006.201.16:43:30.17#ibcon#flushed, iclass 35, count 0 2006.201.16:43:30.17#ibcon#about to write, iclass 35, count 0 2006.201.16:43:30.17#ibcon#wrote, iclass 35, count 0 2006.201.16:43:30.17#ibcon#about to read 3, iclass 35, count 0 2006.201.16:43:30.20#ibcon#read 3, iclass 35, count 0 2006.201.16:43:30.20#ibcon#about to read 4, iclass 35, count 0 2006.201.16:43:30.20#ibcon#read 4, iclass 35, count 0 2006.201.16:43:30.20#ibcon#about to read 5, iclass 35, count 0 2006.201.16:43:30.20#ibcon#read 5, iclass 35, count 0 2006.201.16:43:30.20#ibcon#about to read 6, iclass 35, count 0 2006.201.16:43:30.20#ibcon#read 6, iclass 35, count 0 2006.201.16:43:30.20#ibcon#end of sib2, iclass 35, count 0 2006.201.16:43:30.20#ibcon#*after write, iclass 35, count 0 2006.201.16:43:30.20#ibcon#*before return 0, iclass 35, count 0 2006.201.16:43:30.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:30.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:30.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:43:30.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:43:30.20$vck44/valo=5,734.99 2006.201.16:43:30.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.16:43:30.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.16:43:30.20#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:30.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:30.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:30.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:30.20#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:43:30.20#ibcon#first serial, iclass 37, count 0 2006.201.16:43:30.20#ibcon#enter sib2, iclass 37, count 0 2006.201.16:43:30.20#ibcon#flushed, iclass 37, count 0 2006.201.16:43:30.20#ibcon#about to write, iclass 37, count 0 2006.201.16:43:30.20#ibcon#wrote, iclass 37, count 0 2006.201.16:43:30.20#ibcon#about to read 3, iclass 37, count 0 2006.201.16:43:30.22#ibcon#read 3, iclass 37, count 0 2006.201.16:43:30.22#ibcon#about to read 4, iclass 37, count 0 2006.201.16:43:30.22#ibcon#read 4, iclass 37, count 0 2006.201.16:43:30.22#ibcon#about to read 5, iclass 37, count 0 2006.201.16:43:30.22#ibcon#read 5, iclass 37, count 0 2006.201.16:43:30.22#ibcon#about to read 6, iclass 37, count 0 2006.201.16:43:30.22#ibcon#read 6, iclass 37, count 0 2006.201.16:43:30.22#ibcon#end of sib2, iclass 37, count 0 2006.201.16:43:30.22#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:43:30.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:43:30.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:43:30.22#ibcon#*before write, iclass 37, count 0 2006.201.16:43:30.22#ibcon#enter sib2, iclass 37, count 0 2006.201.16:43:30.22#ibcon#flushed, iclass 37, count 0 2006.201.16:43:30.22#ibcon#about to write, iclass 37, count 0 2006.201.16:43:30.22#ibcon#wrote, iclass 37, count 0 2006.201.16:43:30.22#ibcon#about to read 3, iclass 37, count 0 2006.201.16:43:30.26#ibcon#read 3, iclass 37, count 0 2006.201.16:43:30.26#ibcon#about to read 4, iclass 37, count 0 2006.201.16:43:30.26#ibcon#read 4, iclass 37, count 0 2006.201.16:43:30.26#ibcon#about to read 5, iclass 37, count 0 2006.201.16:43:30.26#ibcon#read 5, iclass 37, count 0 2006.201.16:43:30.26#ibcon#about to read 6, iclass 37, count 0 2006.201.16:43:30.26#ibcon#read 6, iclass 37, count 0 2006.201.16:43:30.26#ibcon#end of sib2, iclass 37, count 0 2006.201.16:43:30.26#ibcon#*after write, iclass 37, count 0 2006.201.16:43:30.26#ibcon#*before return 0, iclass 37, count 0 2006.201.16:43:30.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:30.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:30.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:43:30.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:43:30.26$vck44/va=5,4 2006.201.16:43:30.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.16:43:30.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.16:43:30.26#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:30.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:30.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:30.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:30.32#ibcon#enter wrdev, iclass 39, count 2 2006.201.16:43:30.32#ibcon#first serial, iclass 39, count 2 2006.201.16:43:30.32#ibcon#enter sib2, iclass 39, count 2 2006.201.16:43:30.32#ibcon#flushed, iclass 39, count 2 2006.201.16:43:30.32#ibcon#about to write, iclass 39, count 2 2006.201.16:43:30.32#ibcon#wrote, iclass 39, count 2 2006.201.16:43:30.32#ibcon#about to read 3, iclass 39, count 2 2006.201.16:43:30.34#ibcon#read 3, iclass 39, count 2 2006.201.16:43:30.34#ibcon#about to read 4, iclass 39, count 2 2006.201.16:43:30.34#ibcon#read 4, iclass 39, count 2 2006.201.16:43:30.34#ibcon#about to read 5, iclass 39, count 2 2006.201.16:43:30.34#ibcon#read 5, iclass 39, count 2 2006.201.16:43:30.34#ibcon#about to read 6, iclass 39, count 2 2006.201.16:43:30.34#ibcon#read 6, iclass 39, count 2 2006.201.16:43:30.34#ibcon#end of sib2, iclass 39, count 2 2006.201.16:43:30.34#ibcon#*mode == 0, iclass 39, count 2 2006.201.16:43:30.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.16:43:30.34#ibcon#[25=AT05-04\r\n] 2006.201.16:43:30.34#ibcon#*before write, iclass 39, count 2 2006.201.16:43:30.34#ibcon#enter sib2, iclass 39, count 2 2006.201.16:43:30.34#ibcon#flushed, iclass 39, count 2 2006.201.16:43:30.34#ibcon#about to write, iclass 39, count 2 2006.201.16:43:30.34#ibcon#wrote, iclass 39, count 2 2006.201.16:43:30.34#ibcon#about to read 3, iclass 39, count 2 2006.201.16:43:30.37#ibcon#read 3, iclass 39, count 2 2006.201.16:43:30.37#ibcon#about to read 4, iclass 39, count 2 2006.201.16:43:30.37#ibcon#read 4, iclass 39, count 2 2006.201.16:43:30.37#ibcon#about to read 5, iclass 39, count 2 2006.201.16:43:30.37#ibcon#read 5, iclass 39, count 2 2006.201.16:43:30.37#ibcon#about to read 6, iclass 39, count 2 2006.201.16:43:30.37#ibcon#read 6, iclass 39, count 2 2006.201.16:43:30.37#ibcon#end of sib2, iclass 39, count 2 2006.201.16:43:30.37#ibcon#*after write, iclass 39, count 2 2006.201.16:43:30.37#ibcon#*before return 0, iclass 39, count 2 2006.201.16:43:30.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:30.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:30.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.16:43:30.37#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:30.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:30.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:30.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:30.49#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:43:30.49#ibcon#first serial, iclass 39, count 0 2006.201.16:43:30.49#ibcon#enter sib2, iclass 39, count 0 2006.201.16:43:30.49#ibcon#flushed, iclass 39, count 0 2006.201.16:43:30.49#ibcon#about to write, iclass 39, count 0 2006.201.16:43:30.49#ibcon#wrote, iclass 39, count 0 2006.201.16:43:30.49#ibcon#about to read 3, iclass 39, count 0 2006.201.16:43:30.51#ibcon#read 3, iclass 39, count 0 2006.201.16:43:30.51#ibcon#about to read 4, iclass 39, count 0 2006.201.16:43:30.51#ibcon#read 4, iclass 39, count 0 2006.201.16:43:30.51#ibcon#about to read 5, iclass 39, count 0 2006.201.16:43:30.51#ibcon#read 5, iclass 39, count 0 2006.201.16:43:30.51#ibcon#about to read 6, iclass 39, count 0 2006.201.16:43:30.51#ibcon#read 6, iclass 39, count 0 2006.201.16:43:30.51#ibcon#end of sib2, iclass 39, count 0 2006.201.16:43:30.51#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:43:30.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:43:30.51#ibcon#[25=USB\r\n] 2006.201.16:43:30.51#ibcon#*before write, iclass 39, count 0 2006.201.16:43:30.51#ibcon#enter sib2, iclass 39, count 0 2006.201.16:43:30.51#ibcon#flushed, iclass 39, count 0 2006.201.16:43:30.51#ibcon#about to write, iclass 39, count 0 2006.201.16:43:30.51#ibcon#wrote, iclass 39, count 0 2006.201.16:43:30.51#ibcon#about to read 3, iclass 39, count 0 2006.201.16:43:30.54#ibcon#read 3, iclass 39, count 0 2006.201.16:43:30.54#ibcon#about to read 4, iclass 39, count 0 2006.201.16:43:30.54#ibcon#read 4, iclass 39, count 0 2006.201.16:43:30.54#ibcon#about to read 5, iclass 39, count 0 2006.201.16:43:30.54#ibcon#read 5, iclass 39, count 0 2006.201.16:43:30.54#ibcon#about to read 6, iclass 39, count 0 2006.201.16:43:30.54#ibcon#read 6, iclass 39, count 0 2006.201.16:43:30.54#ibcon#end of sib2, iclass 39, count 0 2006.201.16:43:30.54#ibcon#*after write, iclass 39, count 0 2006.201.16:43:30.54#ibcon#*before return 0, iclass 39, count 0 2006.201.16:43:30.54#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:30.54#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:30.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:43:30.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:43:30.54$vck44/valo=6,814.99 2006.201.16:43:30.54#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.16:43:30.54#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.16:43:30.54#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:30.54#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:30.54#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:30.54#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:30.54#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:43:30.54#ibcon#first serial, iclass 2, count 0 2006.201.16:43:30.54#ibcon#enter sib2, iclass 2, count 0 2006.201.16:43:30.54#ibcon#flushed, iclass 2, count 0 2006.201.16:43:30.54#ibcon#about to write, iclass 2, count 0 2006.201.16:43:30.54#ibcon#wrote, iclass 2, count 0 2006.201.16:43:30.54#ibcon#about to read 3, iclass 2, count 0 2006.201.16:43:30.56#ibcon#read 3, iclass 2, count 0 2006.201.16:43:30.56#ibcon#about to read 4, iclass 2, count 0 2006.201.16:43:30.56#ibcon#read 4, iclass 2, count 0 2006.201.16:43:30.56#ibcon#about to read 5, iclass 2, count 0 2006.201.16:43:30.56#ibcon#read 5, iclass 2, count 0 2006.201.16:43:30.56#ibcon#about to read 6, iclass 2, count 0 2006.201.16:43:30.56#ibcon#read 6, iclass 2, count 0 2006.201.16:43:30.56#ibcon#end of sib2, iclass 2, count 0 2006.201.16:43:30.56#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:43:30.56#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:43:30.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:43:30.56#ibcon#*before write, iclass 2, count 0 2006.201.16:43:30.56#ibcon#enter sib2, iclass 2, count 0 2006.201.16:43:30.56#ibcon#flushed, iclass 2, count 0 2006.201.16:43:30.56#ibcon#about to write, iclass 2, count 0 2006.201.16:43:30.56#ibcon#wrote, iclass 2, count 0 2006.201.16:43:30.56#ibcon#about to read 3, iclass 2, count 0 2006.201.16:43:30.61#ibcon#read 3, iclass 2, count 0 2006.201.16:43:30.61#ibcon#about to read 4, iclass 2, count 0 2006.201.16:43:30.61#ibcon#read 4, iclass 2, count 0 2006.201.16:43:30.61#ibcon#about to read 5, iclass 2, count 0 2006.201.16:43:30.61#ibcon#read 5, iclass 2, count 0 2006.201.16:43:30.61#ibcon#about to read 6, iclass 2, count 0 2006.201.16:43:30.61#ibcon#read 6, iclass 2, count 0 2006.201.16:43:30.61#ibcon#end of sib2, iclass 2, count 0 2006.201.16:43:30.61#ibcon#*after write, iclass 2, count 0 2006.201.16:43:30.61#ibcon#*before return 0, iclass 2, count 0 2006.201.16:43:30.61#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:30.61#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:30.61#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:43:30.61#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:43:30.61$vck44/va=6,5 2006.201.16:43:30.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.16:43:30.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.16:43:30.61#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:30.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:30.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:30.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:30.66#ibcon#enter wrdev, iclass 5, count 2 2006.201.16:43:30.66#ibcon#first serial, iclass 5, count 2 2006.201.16:43:30.66#ibcon#enter sib2, iclass 5, count 2 2006.201.16:43:30.66#ibcon#flushed, iclass 5, count 2 2006.201.16:43:30.66#ibcon#about to write, iclass 5, count 2 2006.201.16:43:30.66#ibcon#wrote, iclass 5, count 2 2006.201.16:43:30.66#ibcon#about to read 3, iclass 5, count 2 2006.201.16:43:30.68#ibcon#read 3, iclass 5, count 2 2006.201.16:43:30.68#ibcon#about to read 4, iclass 5, count 2 2006.201.16:43:30.68#ibcon#read 4, iclass 5, count 2 2006.201.16:43:30.68#ibcon#about to read 5, iclass 5, count 2 2006.201.16:43:30.68#ibcon#read 5, iclass 5, count 2 2006.201.16:43:30.68#ibcon#about to read 6, iclass 5, count 2 2006.201.16:43:30.68#ibcon#read 6, iclass 5, count 2 2006.201.16:43:30.68#ibcon#end of sib2, iclass 5, count 2 2006.201.16:43:30.68#ibcon#*mode == 0, iclass 5, count 2 2006.201.16:43:30.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.16:43:30.68#ibcon#[25=AT06-05\r\n] 2006.201.16:43:30.68#ibcon#*before write, iclass 5, count 2 2006.201.16:43:30.68#ibcon#enter sib2, iclass 5, count 2 2006.201.16:43:30.68#ibcon#flushed, iclass 5, count 2 2006.201.16:43:30.68#ibcon#about to write, iclass 5, count 2 2006.201.16:43:30.68#ibcon#wrote, iclass 5, count 2 2006.201.16:43:30.68#ibcon#about to read 3, iclass 5, count 2 2006.201.16:43:30.71#ibcon#read 3, iclass 5, count 2 2006.201.16:43:30.71#ibcon#about to read 4, iclass 5, count 2 2006.201.16:43:30.71#ibcon#read 4, iclass 5, count 2 2006.201.16:43:30.71#ibcon#about to read 5, iclass 5, count 2 2006.201.16:43:30.71#ibcon#read 5, iclass 5, count 2 2006.201.16:43:30.71#ibcon#about to read 6, iclass 5, count 2 2006.201.16:43:30.71#ibcon#read 6, iclass 5, count 2 2006.201.16:43:30.71#ibcon#end of sib2, iclass 5, count 2 2006.201.16:43:30.71#ibcon#*after write, iclass 5, count 2 2006.201.16:43:30.71#ibcon#*before return 0, iclass 5, count 2 2006.201.16:43:30.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:30.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:30.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.16:43:30.71#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:30.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:30.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:30.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:30.83#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:43:30.83#ibcon#first serial, iclass 5, count 0 2006.201.16:43:30.83#ibcon#enter sib2, iclass 5, count 0 2006.201.16:43:30.83#ibcon#flushed, iclass 5, count 0 2006.201.16:43:30.83#ibcon#about to write, iclass 5, count 0 2006.201.16:43:30.83#ibcon#wrote, iclass 5, count 0 2006.201.16:43:30.83#ibcon#about to read 3, iclass 5, count 0 2006.201.16:43:30.85#ibcon#read 3, iclass 5, count 0 2006.201.16:43:30.85#ibcon#about to read 4, iclass 5, count 0 2006.201.16:43:30.85#ibcon#read 4, iclass 5, count 0 2006.201.16:43:30.85#ibcon#about to read 5, iclass 5, count 0 2006.201.16:43:30.85#ibcon#read 5, iclass 5, count 0 2006.201.16:43:30.85#ibcon#about to read 6, iclass 5, count 0 2006.201.16:43:30.85#ibcon#read 6, iclass 5, count 0 2006.201.16:43:30.85#ibcon#end of sib2, iclass 5, count 0 2006.201.16:43:30.85#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:43:30.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:43:30.85#ibcon#[25=USB\r\n] 2006.201.16:43:30.85#ibcon#*before write, iclass 5, count 0 2006.201.16:43:30.85#ibcon#enter sib2, iclass 5, count 0 2006.201.16:43:30.85#ibcon#flushed, iclass 5, count 0 2006.201.16:43:30.85#ibcon#about to write, iclass 5, count 0 2006.201.16:43:30.85#ibcon#wrote, iclass 5, count 0 2006.201.16:43:30.85#ibcon#about to read 3, iclass 5, count 0 2006.201.16:43:30.88#ibcon#read 3, iclass 5, count 0 2006.201.16:43:30.88#ibcon#about to read 4, iclass 5, count 0 2006.201.16:43:30.88#ibcon#read 4, iclass 5, count 0 2006.201.16:43:30.88#ibcon#about to read 5, iclass 5, count 0 2006.201.16:43:30.88#ibcon#read 5, iclass 5, count 0 2006.201.16:43:30.88#ibcon#about to read 6, iclass 5, count 0 2006.201.16:43:30.88#ibcon#read 6, iclass 5, count 0 2006.201.16:43:30.88#ibcon#end of sib2, iclass 5, count 0 2006.201.16:43:30.88#ibcon#*after write, iclass 5, count 0 2006.201.16:43:30.88#ibcon#*before return 0, iclass 5, count 0 2006.201.16:43:30.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:30.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:30.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:43:30.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:43:30.88$vck44/valo=7,864.99 2006.201.16:43:30.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.16:43:30.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.16:43:30.88#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:30.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:30.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:30.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:30.88#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:43:30.88#ibcon#first serial, iclass 7, count 0 2006.201.16:43:30.88#ibcon#enter sib2, iclass 7, count 0 2006.201.16:43:30.88#ibcon#flushed, iclass 7, count 0 2006.201.16:43:30.88#ibcon#about to write, iclass 7, count 0 2006.201.16:43:30.88#ibcon#wrote, iclass 7, count 0 2006.201.16:43:30.88#ibcon#about to read 3, iclass 7, count 0 2006.201.16:43:30.90#ibcon#read 3, iclass 7, count 0 2006.201.16:43:30.90#ibcon#about to read 4, iclass 7, count 0 2006.201.16:43:30.90#ibcon#read 4, iclass 7, count 0 2006.201.16:43:30.90#ibcon#about to read 5, iclass 7, count 0 2006.201.16:43:30.90#ibcon#read 5, iclass 7, count 0 2006.201.16:43:30.90#ibcon#about to read 6, iclass 7, count 0 2006.201.16:43:30.90#ibcon#read 6, iclass 7, count 0 2006.201.16:43:30.90#ibcon#end of sib2, iclass 7, count 0 2006.201.16:43:30.90#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:43:30.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:43:30.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:43:30.90#ibcon#*before write, iclass 7, count 0 2006.201.16:43:30.90#ibcon#enter sib2, iclass 7, count 0 2006.201.16:43:30.90#ibcon#flushed, iclass 7, count 0 2006.201.16:43:30.90#ibcon#about to write, iclass 7, count 0 2006.201.16:43:30.90#ibcon#wrote, iclass 7, count 0 2006.201.16:43:30.90#ibcon#about to read 3, iclass 7, count 0 2006.201.16:43:30.94#ibcon#read 3, iclass 7, count 0 2006.201.16:43:30.94#ibcon#about to read 4, iclass 7, count 0 2006.201.16:43:30.94#ibcon#read 4, iclass 7, count 0 2006.201.16:43:30.94#ibcon#about to read 5, iclass 7, count 0 2006.201.16:43:30.94#ibcon#read 5, iclass 7, count 0 2006.201.16:43:30.94#ibcon#about to read 6, iclass 7, count 0 2006.201.16:43:30.94#ibcon#read 6, iclass 7, count 0 2006.201.16:43:30.94#ibcon#end of sib2, iclass 7, count 0 2006.201.16:43:30.94#ibcon#*after write, iclass 7, count 0 2006.201.16:43:30.94#ibcon#*before return 0, iclass 7, count 0 2006.201.16:43:30.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:30.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:30.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:43:30.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:43:30.94$vck44/va=7,5 2006.201.16:43:30.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.16:43:30.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.16:43:30.94#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:30.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:31.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:31.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:31.00#ibcon#enter wrdev, iclass 11, count 2 2006.201.16:43:31.00#ibcon#first serial, iclass 11, count 2 2006.201.16:43:31.00#ibcon#enter sib2, iclass 11, count 2 2006.201.16:43:31.00#ibcon#flushed, iclass 11, count 2 2006.201.16:43:31.00#ibcon#about to write, iclass 11, count 2 2006.201.16:43:31.00#ibcon#wrote, iclass 11, count 2 2006.201.16:43:31.00#ibcon#about to read 3, iclass 11, count 2 2006.201.16:43:31.02#ibcon#read 3, iclass 11, count 2 2006.201.16:43:31.02#ibcon#about to read 4, iclass 11, count 2 2006.201.16:43:31.02#ibcon#read 4, iclass 11, count 2 2006.201.16:43:31.02#ibcon#about to read 5, iclass 11, count 2 2006.201.16:43:31.02#ibcon#read 5, iclass 11, count 2 2006.201.16:43:31.02#ibcon#about to read 6, iclass 11, count 2 2006.201.16:43:31.02#ibcon#read 6, iclass 11, count 2 2006.201.16:43:31.02#ibcon#end of sib2, iclass 11, count 2 2006.201.16:43:31.02#ibcon#*mode == 0, iclass 11, count 2 2006.201.16:43:31.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.16:43:31.02#ibcon#[25=AT07-05\r\n] 2006.201.16:43:31.02#ibcon#*before write, iclass 11, count 2 2006.201.16:43:31.02#ibcon#enter sib2, iclass 11, count 2 2006.201.16:43:31.02#ibcon#flushed, iclass 11, count 2 2006.201.16:43:31.02#ibcon#about to write, iclass 11, count 2 2006.201.16:43:31.02#ibcon#wrote, iclass 11, count 2 2006.201.16:43:31.02#ibcon#about to read 3, iclass 11, count 2 2006.201.16:43:31.05#ibcon#read 3, iclass 11, count 2 2006.201.16:43:31.05#ibcon#about to read 4, iclass 11, count 2 2006.201.16:43:31.05#ibcon#read 4, iclass 11, count 2 2006.201.16:43:31.05#ibcon#about to read 5, iclass 11, count 2 2006.201.16:43:31.05#ibcon#read 5, iclass 11, count 2 2006.201.16:43:31.05#ibcon#about to read 6, iclass 11, count 2 2006.201.16:43:31.05#ibcon#read 6, iclass 11, count 2 2006.201.16:43:31.05#ibcon#end of sib2, iclass 11, count 2 2006.201.16:43:31.05#ibcon#*after write, iclass 11, count 2 2006.201.16:43:31.05#ibcon#*before return 0, iclass 11, count 2 2006.201.16:43:31.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:31.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:31.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.16:43:31.05#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:31.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:31.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:31.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:31.17#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:43:31.17#ibcon#first serial, iclass 11, count 0 2006.201.16:43:31.17#ibcon#enter sib2, iclass 11, count 0 2006.201.16:43:31.17#ibcon#flushed, iclass 11, count 0 2006.201.16:43:31.17#ibcon#about to write, iclass 11, count 0 2006.201.16:43:31.17#ibcon#wrote, iclass 11, count 0 2006.201.16:43:31.17#ibcon#about to read 3, iclass 11, count 0 2006.201.16:43:31.19#ibcon#read 3, iclass 11, count 0 2006.201.16:43:31.19#ibcon#about to read 4, iclass 11, count 0 2006.201.16:43:31.19#ibcon#read 4, iclass 11, count 0 2006.201.16:43:31.19#ibcon#about to read 5, iclass 11, count 0 2006.201.16:43:31.19#ibcon#read 5, iclass 11, count 0 2006.201.16:43:31.19#ibcon#about to read 6, iclass 11, count 0 2006.201.16:43:31.19#ibcon#read 6, iclass 11, count 0 2006.201.16:43:31.19#ibcon#end of sib2, iclass 11, count 0 2006.201.16:43:31.19#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:43:31.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:43:31.19#ibcon#[25=USB\r\n] 2006.201.16:43:31.19#ibcon#*before write, iclass 11, count 0 2006.201.16:43:31.19#ibcon#enter sib2, iclass 11, count 0 2006.201.16:43:31.19#ibcon#flushed, iclass 11, count 0 2006.201.16:43:31.19#ibcon#about to write, iclass 11, count 0 2006.201.16:43:31.19#ibcon#wrote, iclass 11, count 0 2006.201.16:43:31.19#ibcon#about to read 3, iclass 11, count 0 2006.201.16:43:31.22#ibcon#read 3, iclass 11, count 0 2006.201.16:43:31.22#ibcon#about to read 4, iclass 11, count 0 2006.201.16:43:31.22#ibcon#read 4, iclass 11, count 0 2006.201.16:43:31.22#ibcon#about to read 5, iclass 11, count 0 2006.201.16:43:31.22#ibcon#read 5, iclass 11, count 0 2006.201.16:43:31.22#ibcon#about to read 6, iclass 11, count 0 2006.201.16:43:31.22#ibcon#read 6, iclass 11, count 0 2006.201.16:43:31.22#ibcon#end of sib2, iclass 11, count 0 2006.201.16:43:31.22#ibcon#*after write, iclass 11, count 0 2006.201.16:43:31.22#ibcon#*before return 0, iclass 11, count 0 2006.201.16:43:31.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:31.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:31.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:43:31.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:43:31.22$vck44/valo=8,884.99 2006.201.16:43:31.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.16:43:31.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.16:43:31.22#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:31.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:31.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:31.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:31.22#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:43:31.22#ibcon#first serial, iclass 13, count 0 2006.201.16:43:31.22#ibcon#enter sib2, iclass 13, count 0 2006.201.16:43:31.22#ibcon#flushed, iclass 13, count 0 2006.201.16:43:31.22#ibcon#about to write, iclass 13, count 0 2006.201.16:43:31.22#ibcon#wrote, iclass 13, count 0 2006.201.16:43:31.22#ibcon#about to read 3, iclass 13, count 0 2006.201.16:43:31.24#ibcon#read 3, iclass 13, count 0 2006.201.16:43:31.24#ibcon#about to read 4, iclass 13, count 0 2006.201.16:43:31.24#ibcon#read 4, iclass 13, count 0 2006.201.16:43:31.24#ibcon#about to read 5, iclass 13, count 0 2006.201.16:43:31.24#ibcon#read 5, iclass 13, count 0 2006.201.16:43:31.24#ibcon#about to read 6, iclass 13, count 0 2006.201.16:43:31.24#ibcon#read 6, iclass 13, count 0 2006.201.16:43:31.24#ibcon#end of sib2, iclass 13, count 0 2006.201.16:43:31.24#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:43:31.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:43:31.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:43:31.24#ibcon#*before write, iclass 13, count 0 2006.201.16:43:31.24#ibcon#enter sib2, iclass 13, count 0 2006.201.16:43:31.24#ibcon#flushed, iclass 13, count 0 2006.201.16:43:31.24#ibcon#about to write, iclass 13, count 0 2006.201.16:43:31.24#ibcon#wrote, iclass 13, count 0 2006.201.16:43:31.24#ibcon#about to read 3, iclass 13, count 0 2006.201.16:43:31.28#ibcon#read 3, iclass 13, count 0 2006.201.16:43:31.28#ibcon#about to read 4, iclass 13, count 0 2006.201.16:43:31.28#ibcon#read 4, iclass 13, count 0 2006.201.16:43:31.28#ibcon#about to read 5, iclass 13, count 0 2006.201.16:43:31.28#ibcon#read 5, iclass 13, count 0 2006.201.16:43:31.28#ibcon#about to read 6, iclass 13, count 0 2006.201.16:43:31.28#ibcon#read 6, iclass 13, count 0 2006.201.16:43:31.28#ibcon#end of sib2, iclass 13, count 0 2006.201.16:43:31.28#ibcon#*after write, iclass 13, count 0 2006.201.16:43:31.28#ibcon#*before return 0, iclass 13, count 0 2006.201.16:43:31.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:31.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:31.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:43:31.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:43:31.28$vck44/va=8,4 2006.201.16:43:31.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.16:43:31.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.16:43:31.28#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:31.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:43:31.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:43:31.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:43:31.34#ibcon#enter wrdev, iclass 15, count 2 2006.201.16:43:31.34#ibcon#first serial, iclass 15, count 2 2006.201.16:43:31.34#ibcon#enter sib2, iclass 15, count 2 2006.201.16:43:31.34#ibcon#flushed, iclass 15, count 2 2006.201.16:43:31.34#ibcon#about to write, iclass 15, count 2 2006.201.16:43:31.34#ibcon#wrote, iclass 15, count 2 2006.201.16:43:31.34#ibcon#about to read 3, iclass 15, count 2 2006.201.16:43:31.36#ibcon#read 3, iclass 15, count 2 2006.201.16:43:31.36#ibcon#about to read 4, iclass 15, count 2 2006.201.16:43:31.36#ibcon#read 4, iclass 15, count 2 2006.201.16:43:31.36#ibcon#about to read 5, iclass 15, count 2 2006.201.16:43:31.36#ibcon#read 5, iclass 15, count 2 2006.201.16:43:31.36#ibcon#about to read 6, iclass 15, count 2 2006.201.16:43:31.36#ibcon#read 6, iclass 15, count 2 2006.201.16:43:31.36#ibcon#end of sib2, iclass 15, count 2 2006.201.16:43:31.36#ibcon#*mode == 0, iclass 15, count 2 2006.201.16:43:31.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.16:43:31.36#ibcon#[25=AT08-04\r\n] 2006.201.16:43:31.36#ibcon#*before write, iclass 15, count 2 2006.201.16:43:31.36#ibcon#enter sib2, iclass 15, count 2 2006.201.16:43:31.36#ibcon#flushed, iclass 15, count 2 2006.201.16:43:31.36#ibcon#about to write, iclass 15, count 2 2006.201.16:43:31.36#ibcon#wrote, iclass 15, count 2 2006.201.16:43:31.36#ibcon#about to read 3, iclass 15, count 2 2006.201.16:43:31.39#ibcon#read 3, iclass 15, count 2 2006.201.16:43:31.39#ibcon#about to read 4, iclass 15, count 2 2006.201.16:43:31.39#ibcon#read 4, iclass 15, count 2 2006.201.16:43:31.39#ibcon#about to read 5, iclass 15, count 2 2006.201.16:43:31.39#ibcon#read 5, iclass 15, count 2 2006.201.16:43:31.39#ibcon#about to read 6, iclass 15, count 2 2006.201.16:43:31.39#ibcon#read 6, iclass 15, count 2 2006.201.16:43:31.39#ibcon#end of sib2, iclass 15, count 2 2006.201.16:43:31.39#ibcon#*after write, iclass 15, count 2 2006.201.16:43:31.39#ibcon#*before return 0, iclass 15, count 2 2006.201.16:43:31.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:43:31.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.16:43:31.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.16:43:31.39#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:31.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:43:31.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:43:31.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:43:31.51#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:43:31.51#ibcon#first serial, iclass 15, count 0 2006.201.16:43:31.51#ibcon#enter sib2, iclass 15, count 0 2006.201.16:43:31.51#ibcon#flushed, iclass 15, count 0 2006.201.16:43:31.51#ibcon#about to write, iclass 15, count 0 2006.201.16:43:31.51#ibcon#wrote, iclass 15, count 0 2006.201.16:43:31.51#ibcon#about to read 3, iclass 15, count 0 2006.201.16:43:31.53#ibcon#read 3, iclass 15, count 0 2006.201.16:43:31.53#ibcon#about to read 4, iclass 15, count 0 2006.201.16:43:31.53#ibcon#read 4, iclass 15, count 0 2006.201.16:43:31.53#ibcon#about to read 5, iclass 15, count 0 2006.201.16:43:31.53#ibcon#read 5, iclass 15, count 0 2006.201.16:43:31.53#ibcon#about to read 6, iclass 15, count 0 2006.201.16:43:31.53#ibcon#read 6, iclass 15, count 0 2006.201.16:43:31.53#ibcon#end of sib2, iclass 15, count 0 2006.201.16:43:31.53#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:43:31.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:43:31.53#ibcon#[25=USB\r\n] 2006.201.16:43:31.53#ibcon#*before write, iclass 15, count 0 2006.201.16:43:31.53#ibcon#enter sib2, iclass 15, count 0 2006.201.16:43:31.53#ibcon#flushed, iclass 15, count 0 2006.201.16:43:31.53#ibcon#about to write, iclass 15, count 0 2006.201.16:43:31.53#ibcon#wrote, iclass 15, count 0 2006.201.16:43:31.53#ibcon#about to read 3, iclass 15, count 0 2006.201.16:43:31.56#ibcon#read 3, iclass 15, count 0 2006.201.16:43:31.56#ibcon#about to read 4, iclass 15, count 0 2006.201.16:43:31.56#ibcon#read 4, iclass 15, count 0 2006.201.16:43:31.56#ibcon#about to read 5, iclass 15, count 0 2006.201.16:43:31.56#ibcon#read 5, iclass 15, count 0 2006.201.16:43:31.56#ibcon#about to read 6, iclass 15, count 0 2006.201.16:43:31.56#ibcon#read 6, iclass 15, count 0 2006.201.16:43:31.56#ibcon#end of sib2, iclass 15, count 0 2006.201.16:43:31.56#ibcon#*after write, iclass 15, count 0 2006.201.16:43:31.56#ibcon#*before return 0, iclass 15, count 0 2006.201.16:43:31.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:43:31.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.16:43:31.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:43:31.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:43:31.56$vck44/vblo=1,629.99 2006.201.16:43:31.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.16:43:31.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.16:43:31.56#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:31.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:31.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:31.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:31.56#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:43:31.56#ibcon#first serial, iclass 17, count 0 2006.201.16:43:31.56#ibcon#enter sib2, iclass 17, count 0 2006.201.16:43:31.56#ibcon#flushed, iclass 17, count 0 2006.201.16:43:31.56#ibcon#about to write, iclass 17, count 0 2006.201.16:43:31.56#ibcon#wrote, iclass 17, count 0 2006.201.16:43:31.56#ibcon#about to read 3, iclass 17, count 0 2006.201.16:43:31.58#ibcon#read 3, iclass 17, count 0 2006.201.16:43:31.58#ibcon#about to read 4, iclass 17, count 0 2006.201.16:43:31.58#ibcon#read 4, iclass 17, count 0 2006.201.16:43:31.58#ibcon#about to read 5, iclass 17, count 0 2006.201.16:43:31.58#ibcon#read 5, iclass 17, count 0 2006.201.16:43:31.58#ibcon#about to read 6, iclass 17, count 0 2006.201.16:43:31.58#ibcon#read 6, iclass 17, count 0 2006.201.16:43:31.58#ibcon#end of sib2, iclass 17, count 0 2006.201.16:43:31.58#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:43:31.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:43:31.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:43:31.58#ibcon#*before write, iclass 17, count 0 2006.201.16:43:31.58#ibcon#enter sib2, iclass 17, count 0 2006.201.16:43:31.58#ibcon#flushed, iclass 17, count 0 2006.201.16:43:31.58#ibcon#about to write, iclass 17, count 0 2006.201.16:43:31.58#ibcon#wrote, iclass 17, count 0 2006.201.16:43:31.58#ibcon#about to read 3, iclass 17, count 0 2006.201.16:43:31.63#ibcon#read 3, iclass 17, count 0 2006.201.16:43:31.63#ibcon#about to read 4, iclass 17, count 0 2006.201.16:43:31.63#ibcon#read 4, iclass 17, count 0 2006.201.16:43:31.63#ibcon#about to read 5, iclass 17, count 0 2006.201.16:43:31.63#ibcon#read 5, iclass 17, count 0 2006.201.16:43:31.63#ibcon#about to read 6, iclass 17, count 0 2006.201.16:43:31.63#ibcon#read 6, iclass 17, count 0 2006.201.16:43:31.63#ibcon#end of sib2, iclass 17, count 0 2006.201.16:43:31.63#ibcon#*after write, iclass 17, count 0 2006.201.16:43:31.63#ibcon#*before return 0, iclass 17, count 0 2006.201.16:43:31.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:31.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.16:43:31.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:43:31.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:43:31.63$vck44/vb=1,4 2006.201.16:43:31.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.16:43:31.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.16:43:31.63#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:31.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:31.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:31.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:31.63#ibcon#enter wrdev, iclass 19, count 2 2006.201.16:43:31.63#ibcon#first serial, iclass 19, count 2 2006.201.16:43:31.63#ibcon#enter sib2, iclass 19, count 2 2006.201.16:43:31.63#ibcon#flushed, iclass 19, count 2 2006.201.16:43:31.63#ibcon#about to write, iclass 19, count 2 2006.201.16:43:31.63#ibcon#wrote, iclass 19, count 2 2006.201.16:43:31.63#ibcon#about to read 3, iclass 19, count 2 2006.201.16:43:31.65#ibcon#read 3, iclass 19, count 2 2006.201.16:43:31.65#ibcon#about to read 4, iclass 19, count 2 2006.201.16:43:31.65#ibcon#read 4, iclass 19, count 2 2006.201.16:43:31.65#ibcon#about to read 5, iclass 19, count 2 2006.201.16:43:31.65#ibcon#read 5, iclass 19, count 2 2006.201.16:43:31.65#ibcon#about to read 6, iclass 19, count 2 2006.201.16:43:31.65#ibcon#read 6, iclass 19, count 2 2006.201.16:43:31.65#ibcon#end of sib2, iclass 19, count 2 2006.201.16:43:31.65#ibcon#*mode == 0, iclass 19, count 2 2006.201.16:43:31.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.16:43:31.65#ibcon#[27=AT01-04\r\n] 2006.201.16:43:31.65#ibcon#*before write, iclass 19, count 2 2006.201.16:43:31.65#ibcon#enter sib2, iclass 19, count 2 2006.201.16:43:31.65#ibcon#flushed, iclass 19, count 2 2006.201.16:43:31.65#ibcon#about to write, iclass 19, count 2 2006.201.16:43:31.65#ibcon#wrote, iclass 19, count 2 2006.201.16:43:31.65#ibcon#about to read 3, iclass 19, count 2 2006.201.16:43:31.68#ibcon#read 3, iclass 19, count 2 2006.201.16:43:31.68#ibcon#about to read 4, iclass 19, count 2 2006.201.16:43:31.68#ibcon#read 4, iclass 19, count 2 2006.201.16:43:31.68#ibcon#about to read 5, iclass 19, count 2 2006.201.16:43:31.68#ibcon#read 5, iclass 19, count 2 2006.201.16:43:31.68#ibcon#about to read 6, iclass 19, count 2 2006.201.16:43:31.68#ibcon#read 6, iclass 19, count 2 2006.201.16:43:31.68#ibcon#end of sib2, iclass 19, count 2 2006.201.16:43:31.68#ibcon#*after write, iclass 19, count 2 2006.201.16:43:31.68#ibcon#*before return 0, iclass 19, count 2 2006.201.16:43:31.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:31.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.16:43:31.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.16:43:31.68#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:31.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:31.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:31.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:31.80#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:43:31.80#ibcon#first serial, iclass 19, count 0 2006.201.16:43:31.80#ibcon#enter sib2, iclass 19, count 0 2006.201.16:43:31.80#ibcon#flushed, iclass 19, count 0 2006.201.16:43:31.80#ibcon#about to write, iclass 19, count 0 2006.201.16:43:31.80#ibcon#wrote, iclass 19, count 0 2006.201.16:43:31.80#ibcon#about to read 3, iclass 19, count 0 2006.201.16:43:31.82#ibcon#read 3, iclass 19, count 0 2006.201.16:43:31.82#ibcon#about to read 4, iclass 19, count 0 2006.201.16:43:31.82#ibcon#read 4, iclass 19, count 0 2006.201.16:43:31.82#ibcon#about to read 5, iclass 19, count 0 2006.201.16:43:31.82#ibcon#read 5, iclass 19, count 0 2006.201.16:43:31.82#ibcon#about to read 6, iclass 19, count 0 2006.201.16:43:31.82#ibcon#read 6, iclass 19, count 0 2006.201.16:43:31.82#ibcon#end of sib2, iclass 19, count 0 2006.201.16:43:31.82#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:43:31.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:43:31.82#ibcon#[27=USB\r\n] 2006.201.16:43:31.82#ibcon#*before write, iclass 19, count 0 2006.201.16:43:31.82#ibcon#enter sib2, iclass 19, count 0 2006.201.16:43:31.82#ibcon#flushed, iclass 19, count 0 2006.201.16:43:31.82#ibcon#about to write, iclass 19, count 0 2006.201.16:43:31.82#ibcon#wrote, iclass 19, count 0 2006.201.16:43:31.82#ibcon#about to read 3, iclass 19, count 0 2006.201.16:43:31.85#ibcon#read 3, iclass 19, count 0 2006.201.16:43:31.85#ibcon#about to read 4, iclass 19, count 0 2006.201.16:43:31.85#ibcon#read 4, iclass 19, count 0 2006.201.16:43:31.85#ibcon#about to read 5, iclass 19, count 0 2006.201.16:43:31.85#ibcon#read 5, iclass 19, count 0 2006.201.16:43:31.85#ibcon#about to read 6, iclass 19, count 0 2006.201.16:43:31.85#ibcon#read 6, iclass 19, count 0 2006.201.16:43:31.85#ibcon#end of sib2, iclass 19, count 0 2006.201.16:43:31.85#ibcon#*after write, iclass 19, count 0 2006.201.16:43:31.85#ibcon#*before return 0, iclass 19, count 0 2006.201.16:43:31.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:31.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.16:43:31.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:43:31.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:43:31.85$vck44/vblo=2,634.99 2006.201.16:43:31.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.16:43:31.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.16:43:31.85#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:31.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:43:31.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:43:31.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:43:31.85#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:43:31.85#ibcon#first serial, iclass 21, count 0 2006.201.16:43:31.85#ibcon#enter sib2, iclass 21, count 0 2006.201.16:43:31.85#ibcon#flushed, iclass 21, count 0 2006.201.16:43:31.85#ibcon#about to write, iclass 21, count 0 2006.201.16:43:31.85#ibcon#wrote, iclass 21, count 0 2006.201.16:43:31.85#ibcon#about to read 3, iclass 21, count 0 2006.201.16:43:31.87#ibcon#read 3, iclass 21, count 0 2006.201.16:43:31.87#ibcon#about to read 4, iclass 21, count 0 2006.201.16:43:31.87#ibcon#read 4, iclass 21, count 0 2006.201.16:43:31.87#ibcon#about to read 5, iclass 21, count 0 2006.201.16:43:31.87#ibcon#read 5, iclass 21, count 0 2006.201.16:43:31.87#ibcon#about to read 6, iclass 21, count 0 2006.201.16:43:31.87#ibcon#read 6, iclass 21, count 0 2006.201.16:43:31.87#ibcon#end of sib2, iclass 21, count 0 2006.201.16:43:31.87#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:43:31.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:43:31.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:43:31.87#ibcon#*before write, iclass 21, count 0 2006.201.16:43:31.87#ibcon#enter sib2, iclass 21, count 0 2006.201.16:43:31.87#ibcon#flushed, iclass 21, count 0 2006.201.16:43:31.87#ibcon#about to write, iclass 21, count 0 2006.201.16:43:31.87#ibcon#wrote, iclass 21, count 0 2006.201.16:43:31.87#ibcon#about to read 3, iclass 21, count 0 2006.201.16:43:31.91#ibcon#read 3, iclass 21, count 0 2006.201.16:43:31.91#ibcon#about to read 4, iclass 21, count 0 2006.201.16:43:31.91#ibcon#read 4, iclass 21, count 0 2006.201.16:43:31.91#ibcon#about to read 5, iclass 21, count 0 2006.201.16:43:31.91#ibcon#read 5, iclass 21, count 0 2006.201.16:43:31.91#ibcon#about to read 6, iclass 21, count 0 2006.201.16:43:31.91#ibcon#read 6, iclass 21, count 0 2006.201.16:43:31.91#ibcon#end of sib2, iclass 21, count 0 2006.201.16:43:31.91#ibcon#*after write, iclass 21, count 0 2006.201.16:43:31.91#ibcon#*before return 0, iclass 21, count 0 2006.201.16:43:31.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:43:31.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.16:43:31.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:43:31.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:43:31.91$vck44/vb=2,5 2006.201.16:43:31.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.16:43:31.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.16:43:31.91#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:31.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:43:31.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:43:31.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:43:31.97#ibcon#enter wrdev, iclass 23, count 2 2006.201.16:43:31.97#ibcon#first serial, iclass 23, count 2 2006.201.16:43:31.97#ibcon#enter sib2, iclass 23, count 2 2006.201.16:43:31.97#ibcon#flushed, iclass 23, count 2 2006.201.16:43:31.97#ibcon#about to write, iclass 23, count 2 2006.201.16:43:31.97#ibcon#wrote, iclass 23, count 2 2006.201.16:43:31.97#ibcon#about to read 3, iclass 23, count 2 2006.201.16:43:31.99#ibcon#read 3, iclass 23, count 2 2006.201.16:43:31.99#ibcon#about to read 4, iclass 23, count 2 2006.201.16:43:31.99#ibcon#read 4, iclass 23, count 2 2006.201.16:43:31.99#ibcon#about to read 5, iclass 23, count 2 2006.201.16:43:31.99#ibcon#read 5, iclass 23, count 2 2006.201.16:43:31.99#ibcon#about to read 6, iclass 23, count 2 2006.201.16:43:31.99#ibcon#read 6, iclass 23, count 2 2006.201.16:43:31.99#ibcon#end of sib2, iclass 23, count 2 2006.201.16:43:31.99#ibcon#*mode == 0, iclass 23, count 2 2006.201.16:43:31.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.16:43:31.99#ibcon#[27=AT02-05\r\n] 2006.201.16:43:31.99#ibcon#*before write, iclass 23, count 2 2006.201.16:43:31.99#ibcon#enter sib2, iclass 23, count 2 2006.201.16:43:31.99#ibcon#flushed, iclass 23, count 2 2006.201.16:43:31.99#ibcon#about to write, iclass 23, count 2 2006.201.16:43:31.99#ibcon#wrote, iclass 23, count 2 2006.201.16:43:31.99#ibcon#about to read 3, iclass 23, count 2 2006.201.16:43:32.02#ibcon#read 3, iclass 23, count 2 2006.201.16:43:32.02#ibcon#about to read 4, iclass 23, count 2 2006.201.16:43:32.02#ibcon#read 4, iclass 23, count 2 2006.201.16:43:32.02#ibcon#about to read 5, iclass 23, count 2 2006.201.16:43:32.02#ibcon#read 5, iclass 23, count 2 2006.201.16:43:32.02#ibcon#about to read 6, iclass 23, count 2 2006.201.16:43:32.02#ibcon#read 6, iclass 23, count 2 2006.201.16:43:32.02#ibcon#end of sib2, iclass 23, count 2 2006.201.16:43:32.02#ibcon#*after write, iclass 23, count 2 2006.201.16:43:32.02#ibcon#*before return 0, iclass 23, count 2 2006.201.16:43:32.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:43:32.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.16:43:32.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.16:43:32.02#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:32.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:43:32.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:43:32.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:43:32.14#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:43:32.14#ibcon#first serial, iclass 23, count 0 2006.201.16:43:32.14#ibcon#enter sib2, iclass 23, count 0 2006.201.16:43:32.14#ibcon#flushed, iclass 23, count 0 2006.201.16:43:32.14#ibcon#about to write, iclass 23, count 0 2006.201.16:43:32.14#ibcon#wrote, iclass 23, count 0 2006.201.16:43:32.14#ibcon#about to read 3, iclass 23, count 0 2006.201.16:43:32.16#ibcon#read 3, iclass 23, count 0 2006.201.16:43:32.16#ibcon#about to read 4, iclass 23, count 0 2006.201.16:43:32.16#ibcon#read 4, iclass 23, count 0 2006.201.16:43:32.16#ibcon#about to read 5, iclass 23, count 0 2006.201.16:43:32.16#ibcon#read 5, iclass 23, count 0 2006.201.16:43:32.16#ibcon#about to read 6, iclass 23, count 0 2006.201.16:43:32.16#ibcon#read 6, iclass 23, count 0 2006.201.16:43:32.16#ibcon#end of sib2, iclass 23, count 0 2006.201.16:43:32.16#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:43:32.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:43:32.16#ibcon#[27=USB\r\n] 2006.201.16:43:32.16#ibcon#*before write, iclass 23, count 0 2006.201.16:43:32.16#ibcon#enter sib2, iclass 23, count 0 2006.201.16:43:32.16#ibcon#flushed, iclass 23, count 0 2006.201.16:43:32.16#ibcon#about to write, iclass 23, count 0 2006.201.16:43:32.16#ibcon#wrote, iclass 23, count 0 2006.201.16:43:32.16#ibcon#about to read 3, iclass 23, count 0 2006.201.16:43:32.19#ibcon#read 3, iclass 23, count 0 2006.201.16:43:32.19#ibcon#about to read 4, iclass 23, count 0 2006.201.16:43:32.19#ibcon#read 4, iclass 23, count 0 2006.201.16:43:32.19#ibcon#about to read 5, iclass 23, count 0 2006.201.16:43:32.19#ibcon#read 5, iclass 23, count 0 2006.201.16:43:32.19#ibcon#about to read 6, iclass 23, count 0 2006.201.16:43:32.19#ibcon#read 6, iclass 23, count 0 2006.201.16:43:32.19#ibcon#end of sib2, iclass 23, count 0 2006.201.16:43:32.19#ibcon#*after write, iclass 23, count 0 2006.201.16:43:32.19#ibcon#*before return 0, iclass 23, count 0 2006.201.16:43:32.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:43:32.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.16:43:32.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:43:32.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:43:32.19$vck44/vblo=3,649.99 2006.201.16:43:32.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.16:43:32.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.16:43:32.19#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:32.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:32.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:32.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:32.19#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:43:32.19#ibcon#first serial, iclass 25, count 0 2006.201.16:43:32.19#ibcon#enter sib2, iclass 25, count 0 2006.201.16:43:32.19#ibcon#flushed, iclass 25, count 0 2006.201.16:43:32.19#ibcon#about to write, iclass 25, count 0 2006.201.16:43:32.19#ibcon#wrote, iclass 25, count 0 2006.201.16:43:32.19#ibcon#about to read 3, iclass 25, count 0 2006.201.16:43:32.21#ibcon#read 3, iclass 25, count 0 2006.201.16:43:32.21#ibcon#about to read 4, iclass 25, count 0 2006.201.16:43:32.21#ibcon#read 4, iclass 25, count 0 2006.201.16:43:32.21#ibcon#about to read 5, iclass 25, count 0 2006.201.16:43:32.21#ibcon#read 5, iclass 25, count 0 2006.201.16:43:32.21#ibcon#about to read 6, iclass 25, count 0 2006.201.16:43:32.21#ibcon#read 6, iclass 25, count 0 2006.201.16:43:32.21#ibcon#end of sib2, iclass 25, count 0 2006.201.16:43:32.21#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:43:32.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:43:32.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:43:32.21#ibcon#*before write, iclass 25, count 0 2006.201.16:43:32.21#ibcon#enter sib2, iclass 25, count 0 2006.201.16:43:32.21#ibcon#flushed, iclass 25, count 0 2006.201.16:43:32.21#ibcon#about to write, iclass 25, count 0 2006.201.16:43:32.21#ibcon#wrote, iclass 25, count 0 2006.201.16:43:32.21#ibcon#about to read 3, iclass 25, count 0 2006.201.16:43:32.26#ibcon#read 3, iclass 25, count 0 2006.201.16:43:32.26#ibcon#about to read 4, iclass 25, count 0 2006.201.16:43:32.26#ibcon#read 4, iclass 25, count 0 2006.201.16:43:32.26#ibcon#about to read 5, iclass 25, count 0 2006.201.16:43:32.26#ibcon#read 5, iclass 25, count 0 2006.201.16:43:32.26#ibcon#about to read 6, iclass 25, count 0 2006.201.16:43:32.26#ibcon#read 6, iclass 25, count 0 2006.201.16:43:32.26#ibcon#end of sib2, iclass 25, count 0 2006.201.16:43:32.26#ibcon#*after write, iclass 25, count 0 2006.201.16:43:32.26#ibcon#*before return 0, iclass 25, count 0 2006.201.16:43:32.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:32.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:43:32.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:43:32.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:43:32.26$vck44/vb=3,4 2006.201.16:43:32.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.16:43:32.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.16:43:32.26#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:32.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:32.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:32.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:32.31#ibcon#enter wrdev, iclass 27, count 2 2006.201.16:43:32.31#ibcon#first serial, iclass 27, count 2 2006.201.16:43:32.31#ibcon#enter sib2, iclass 27, count 2 2006.201.16:43:32.31#ibcon#flushed, iclass 27, count 2 2006.201.16:43:32.31#ibcon#about to write, iclass 27, count 2 2006.201.16:43:32.31#ibcon#wrote, iclass 27, count 2 2006.201.16:43:32.31#ibcon#about to read 3, iclass 27, count 2 2006.201.16:43:32.33#ibcon#read 3, iclass 27, count 2 2006.201.16:43:32.33#ibcon#about to read 4, iclass 27, count 2 2006.201.16:43:32.33#ibcon#read 4, iclass 27, count 2 2006.201.16:43:32.33#ibcon#about to read 5, iclass 27, count 2 2006.201.16:43:32.33#ibcon#read 5, iclass 27, count 2 2006.201.16:43:32.33#ibcon#about to read 6, iclass 27, count 2 2006.201.16:43:32.33#ibcon#read 6, iclass 27, count 2 2006.201.16:43:32.33#ibcon#end of sib2, iclass 27, count 2 2006.201.16:43:32.33#ibcon#*mode == 0, iclass 27, count 2 2006.201.16:43:32.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.16:43:32.33#ibcon#[27=AT03-04\r\n] 2006.201.16:43:32.33#ibcon#*before write, iclass 27, count 2 2006.201.16:43:32.33#ibcon#enter sib2, iclass 27, count 2 2006.201.16:43:32.33#ibcon#flushed, iclass 27, count 2 2006.201.16:43:32.33#ibcon#about to write, iclass 27, count 2 2006.201.16:43:32.33#ibcon#wrote, iclass 27, count 2 2006.201.16:43:32.33#ibcon#about to read 3, iclass 27, count 2 2006.201.16:43:32.36#ibcon#read 3, iclass 27, count 2 2006.201.16:43:32.36#ibcon#about to read 4, iclass 27, count 2 2006.201.16:43:32.36#ibcon#read 4, iclass 27, count 2 2006.201.16:43:32.36#ibcon#about to read 5, iclass 27, count 2 2006.201.16:43:32.36#ibcon#read 5, iclass 27, count 2 2006.201.16:43:32.36#ibcon#about to read 6, iclass 27, count 2 2006.201.16:43:32.36#ibcon#read 6, iclass 27, count 2 2006.201.16:43:32.36#ibcon#end of sib2, iclass 27, count 2 2006.201.16:43:32.36#ibcon#*after write, iclass 27, count 2 2006.201.16:43:32.36#ibcon#*before return 0, iclass 27, count 2 2006.201.16:43:32.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:32.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.16:43:32.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.16:43:32.36#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:32.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:32.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:32.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:32.48#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:43:32.48#ibcon#first serial, iclass 27, count 0 2006.201.16:43:32.48#ibcon#enter sib2, iclass 27, count 0 2006.201.16:43:32.48#ibcon#flushed, iclass 27, count 0 2006.201.16:43:32.48#ibcon#about to write, iclass 27, count 0 2006.201.16:43:32.48#ibcon#wrote, iclass 27, count 0 2006.201.16:43:32.48#ibcon#about to read 3, iclass 27, count 0 2006.201.16:43:32.50#ibcon#read 3, iclass 27, count 0 2006.201.16:43:32.50#ibcon#about to read 4, iclass 27, count 0 2006.201.16:43:32.50#ibcon#read 4, iclass 27, count 0 2006.201.16:43:32.50#ibcon#about to read 5, iclass 27, count 0 2006.201.16:43:32.50#ibcon#read 5, iclass 27, count 0 2006.201.16:43:32.50#ibcon#about to read 6, iclass 27, count 0 2006.201.16:43:32.50#ibcon#read 6, iclass 27, count 0 2006.201.16:43:32.50#ibcon#end of sib2, iclass 27, count 0 2006.201.16:43:32.50#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:43:32.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:43:32.50#ibcon#[27=USB\r\n] 2006.201.16:43:32.50#ibcon#*before write, iclass 27, count 0 2006.201.16:43:32.50#ibcon#enter sib2, iclass 27, count 0 2006.201.16:43:32.50#ibcon#flushed, iclass 27, count 0 2006.201.16:43:32.50#ibcon#about to write, iclass 27, count 0 2006.201.16:43:32.50#ibcon#wrote, iclass 27, count 0 2006.201.16:43:32.50#ibcon#about to read 3, iclass 27, count 0 2006.201.16:43:32.53#ibcon#read 3, iclass 27, count 0 2006.201.16:43:32.53#ibcon#about to read 4, iclass 27, count 0 2006.201.16:43:32.53#ibcon#read 4, iclass 27, count 0 2006.201.16:43:32.53#ibcon#about to read 5, iclass 27, count 0 2006.201.16:43:32.53#ibcon#read 5, iclass 27, count 0 2006.201.16:43:32.53#ibcon#about to read 6, iclass 27, count 0 2006.201.16:43:32.53#ibcon#read 6, iclass 27, count 0 2006.201.16:43:32.53#ibcon#end of sib2, iclass 27, count 0 2006.201.16:43:32.53#ibcon#*after write, iclass 27, count 0 2006.201.16:43:32.53#ibcon#*before return 0, iclass 27, count 0 2006.201.16:43:32.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:32.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.16:43:32.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:43:32.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:43:32.53$vck44/vblo=4,679.99 2006.201.16:43:32.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.16:43:32.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.16:43:32.53#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:32.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:32.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:32.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:32.53#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:43:32.53#ibcon#first serial, iclass 29, count 0 2006.201.16:43:32.53#ibcon#enter sib2, iclass 29, count 0 2006.201.16:43:32.53#ibcon#flushed, iclass 29, count 0 2006.201.16:43:32.53#ibcon#about to write, iclass 29, count 0 2006.201.16:43:32.53#ibcon#wrote, iclass 29, count 0 2006.201.16:43:32.53#ibcon#about to read 3, iclass 29, count 0 2006.201.16:43:32.55#ibcon#read 3, iclass 29, count 0 2006.201.16:43:32.55#ibcon#about to read 4, iclass 29, count 0 2006.201.16:43:32.55#ibcon#read 4, iclass 29, count 0 2006.201.16:43:32.55#ibcon#about to read 5, iclass 29, count 0 2006.201.16:43:32.55#ibcon#read 5, iclass 29, count 0 2006.201.16:43:32.55#ibcon#about to read 6, iclass 29, count 0 2006.201.16:43:32.55#ibcon#read 6, iclass 29, count 0 2006.201.16:43:32.55#ibcon#end of sib2, iclass 29, count 0 2006.201.16:43:32.55#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:43:32.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:43:32.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:43:32.55#ibcon#*before write, iclass 29, count 0 2006.201.16:43:32.55#ibcon#enter sib2, iclass 29, count 0 2006.201.16:43:32.55#ibcon#flushed, iclass 29, count 0 2006.201.16:43:32.55#ibcon#about to write, iclass 29, count 0 2006.201.16:43:32.55#ibcon#wrote, iclass 29, count 0 2006.201.16:43:32.55#ibcon#about to read 3, iclass 29, count 0 2006.201.16:43:32.59#ibcon#read 3, iclass 29, count 0 2006.201.16:43:32.59#ibcon#about to read 4, iclass 29, count 0 2006.201.16:43:32.59#ibcon#read 4, iclass 29, count 0 2006.201.16:43:32.59#ibcon#about to read 5, iclass 29, count 0 2006.201.16:43:32.59#ibcon#read 5, iclass 29, count 0 2006.201.16:43:32.59#ibcon#about to read 6, iclass 29, count 0 2006.201.16:43:32.59#ibcon#read 6, iclass 29, count 0 2006.201.16:43:32.59#ibcon#end of sib2, iclass 29, count 0 2006.201.16:43:32.59#ibcon#*after write, iclass 29, count 0 2006.201.16:43:32.59#ibcon#*before return 0, iclass 29, count 0 2006.201.16:43:32.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:32.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.16:43:32.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:43:32.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:43:32.59$vck44/vb=4,5 2006.201.16:43:32.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.16:43:32.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.16:43:32.59#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:32.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:32.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:32.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:32.65#ibcon#enter wrdev, iclass 31, count 2 2006.201.16:43:32.65#ibcon#first serial, iclass 31, count 2 2006.201.16:43:32.65#ibcon#enter sib2, iclass 31, count 2 2006.201.16:43:32.65#ibcon#flushed, iclass 31, count 2 2006.201.16:43:32.65#ibcon#about to write, iclass 31, count 2 2006.201.16:43:32.65#ibcon#wrote, iclass 31, count 2 2006.201.16:43:32.65#ibcon#about to read 3, iclass 31, count 2 2006.201.16:43:32.67#ibcon#read 3, iclass 31, count 2 2006.201.16:43:32.67#ibcon#about to read 4, iclass 31, count 2 2006.201.16:43:32.67#ibcon#read 4, iclass 31, count 2 2006.201.16:43:32.67#ibcon#about to read 5, iclass 31, count 2 2006.201.16:43:32.67#ibcon#read 5, iclass 31, count 2 2006.201.16:43:32.67#ibcon#about to read 6, iclass 31, count 2 2006.201.16:43:32.67#ibcon#read 6, iclass 31, count 2 2006.201.16:43:32.67#ibcon#end of sib2, iclass 31, count 2 2006.201.16:43:32.67#ibcon#*mode == 0, iclass 31, count 2 2006.201.16:43:32.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.16:43:32.67#ibcon#[27=AT04-05\r\n] 2006.201.16:43:32.67#ibcon#*before write, iclass 31, count 2 2006.201.16:43:32.67#ibcon#enter sib2, iclass 31, count 2 2006.201.16:43:32.67#ibcon#flushed, iclass 31, count 2 2006.201.16:43:32.67#ibcon#about to write, iclass 31, count 2 2006.201.16:43:32.67#ibcon#wrote, iclass 31, count 2 2006.201.16:43:32.67#ibcon#about to read 3, iclass 31, count 2 2006.201.16:43:32.70#ibcon#read 3, iclass 31, count 2 2006.201.16:43:32.70#ibcon#about to read 4, iclass 31, count 2 2006.201.16:43:32.70#ibcon#read 4, iclass 31, count 2 2006.201.16:43:32.70#ibcon#about to read 5, iclass 31, count 2 2006.201.16:43:32.70#ibcon#read 5, iclass 31, count 2 2006.201.16:43:32.70#ibcon#about to read 6, iclass 31, count 2 2006.201.16:43:32.70#ibcon#read 6, iclass 31, count 2 2006.201.16:43:32.70#ibcon#end of sib2, iclass 31, count 2 2006.201.16:43:32.70#ibcon#*after write, iclass 31, count 2 2006.201.16:43:32.70#ibcon#*before return 0, iclass 31, count 2 2006.201.16:43:32.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:32.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.16:43:32.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.16:43:32.70#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:32.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:32.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:32.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:32.82#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:43:32.82#ibcon#first serial, iclass 31, count 0 2006.201.16:43:32.82#ibcon#enter sib2, iclass 31, count 0 2006.201.16:43:32.82#ibcon#flushed, iclass 31, count 0 2006.201.16:43:32.82#ibcon#about to write, iclass 31, count 0 2006.201.16:43:32.82#ibcon#wrote, iclass 31, count 0 2006.201.16:43:32.82#ibcon#about to read 3, iclass 31, count 0 2006.201.16:43:32.84#ibcon#read 3, iclass 31, count 0 2006.201.16:43:32.84#ibcon#about to read 4, iclass 31, count 0 2006.201.16:43:32.84#ibcon#read 4, iclass 31, count 0 2006.201.16:43:32.84#ibcon#about to read 5, iclass 31, count 0 2006.201.16:43:32.84#ibcon#read 5, iclass 31, count 0 2006.201.16:43:32.84#ibcon#about to read 6, iclass 31, count 0 2006.201.16:43:32.84#ibcon#read 6, iclass 31, count 0 2006.201.16:43:32.84#ibcon#end of sib2, iclass 31, count 0 2006.201.16:43:32.84#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:43:32.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:43:32.84#ibcon#[27=USB\r\n] 2006.201.16:43:32.84#ibcon#*before write, iclass 31, count 0 2006.201.16:43:32.84#ibcon#enter sib2, iclass 31, count 0 2006.201.16:43:32.84#ibcon#flushed, iclass 31, count 0 2006.201.16:43:32.84#ibcon#about to write, iclass 31, count 0 2006.201.16:43:32.84#ibcon#wrote, iclass 31, count 0 2006.201.16:43:32.84#ibcon#about to read 3, iclass 31, count 0 2006.201.16:43:32.87#ibcon#read 3, iclass 31, count 0 2006.201.16:43:32.87#ibcon#about to read 4, iclass 31, count 0 2006.201.16:43:32.87#ibcon#read 4, iclass 31, count 0 2006.201.16:43:32.87#ibcon#about to read 5, iclass 31, count 0 2006.201.16:43:32.87#ibcon#read 5, iclass 31, count 0 2006.201.16:43:32.87#ibcon#about to read 6, iclass 31, count 0 2006.201.16:43:32.87#ibcon#read 6, iclass 31, count 0 2006.201.16:43:32.87#ibcon#end of sib2, iclass 31, count 0 2006.201.16:43:32.87#ibcon#*after write, iclass 31, count 0 2006.201.16:43:32.87#ibcon#*before return 0, iclass 31, count 0 2006.201.16:43:32.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:32.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.16:43:32.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:43:32.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:43:32.87$vck44/vblo=5,709.99 2006.201.16:43:32.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.16:43:32.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.16:43:32.87#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:32.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:32.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:32.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:32.87#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:43:32.87#ibcon#first serial, iclass 33, count 0 2006.201.16:43:32.87#ibcon#enter sib2, iclass 33, count 0 2006.201.16:43:32.87#ibcon#flushed, iclass 33, count 0 2006.201.16:43:32.87#ibcon#about to write, iclass 33, count 0 2006.201.16:43:32.87#ibcon#wrote, iclass 33, count 0 2006.201.16:43:32.87#ibcon#about to read 3, iclass 33, count 0 2006.201.16:43:32.89#ibcon#read 3, iclass 33, count 0 2006.201.16:43:32.89#ibcon#about to read 4, iclass 33, count 0 2006.201.16:43:32.89#ibcon#read 4, iclass 33, count 0 2006.201.16:43:32.89#ibcon#about to read 5, iclass 33, count 0 2006.201.16:43:32.89#ibcon#read 5, iclass 33, count 0 2006.201.16:43:32.89#ibcon#about to read 6, iclass 33, count 0 2006.201.16:43:32.89#ibcon#read 6, iclass 33, count 0 2006.201.16:43:32.89#ibcon#end of sib2, iclass 33, count 0 2006.201.16:43:32.89#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:43:32.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:43:32.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:43:32.89#ibcon#*before write, iclass 33, count 0 2006.201.16:43:32.89#ibcon#enter sib2, iclass 33, count 0 2006.201.16:43:32.89#ibcon#flushed, iclass 33, count 0 2006.201.16:43:32.89#ibcon#about to write, iclass 33, count 0 2006.201.16:43:32.89#ibcon#wrote, iclass 33, count 0 2006.201.16:43:32.89#ibcon#about to read 3, iclass 33, count 0 2006.201.16:43:32.93#ibcon#read 3, iclass 33, count 0 2006.201.16:43:32.93#ibcon#about to read 4, iclass 33, count 0 2006.201.16:43:32.93#ibcon#read 4, iclass 33, count 0 2006.201.16:43:32.93#ibcon#about to read 5, iclass 33, count 0 2006.201.16:43:32.93#ibcon#read 5, iclass 33, count 0 2006.201.16:43:32.93#ibcon#about to read 6, iclass 33, count 0 2006.201.16:43:32.93#ibcon#read 6, iclass 33, count 0 2006.201.16:43:32.93#ibcon#end of sib2, iclass 33, count 0 2006.201.16:43:32.93#ibcon#*after write, iclass 33, count 0 2006.201.16:43:32.93#ibcon#*before return 0, iclass 33, count 0 2006.201.16:43:32.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:32.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.16:43:32.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:43:32.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:43:32.93$vck44/vb=5,4 2006.201.16:43:32.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.16:43:32.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.16:43:32.93#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:32.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:32.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:32.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:32.99#ibcon#enter wrdev, iclass 35, count 2 2006.201.16:43:32.99#ibcon#first serial, iclass 35, count 2 2006.201.16:43:32.99#ibcon#enter sib2, iclass 35, count 2 2006.201.16:43:32.99#ibcon#flushed, iclass 35, count 2 2006.201.16:43:32.99#ibcon#about to write, iclass 35, count 2 2006.201.16:43:32.99#ibcon#wrote, iclass 35, count 2 2006.201.16:43:32.99#ibcon#about to read 3, iclass 35, count 2 2006.201.16:43:33.01#ibcon#read 3, iclass 35, count 2 2006.201.16:43:33.01#ibcon#about to read 4, iclass 35, count 2 2006.201.16:43:33.01#ibcon#read 4, iclass 35, count 2 2006.201.16:43:33.01#ibcon#about to read 5, iclass 35, count 2 2006.201.16:43:33.01#ibcon#read 5, iclass 35, count 2 2006.201.16:43:33.01#ibcon#about to read 6, iclass 35, count 2 2006.201.16:43:33.01#ibcon#read 6, iclass 35, count 2 2006.201.16:43:33.01#ibcon#end of sib2, iclass 35, count 2 2006.201.16:43:33.01#ibcon#*mode == 0, iclass 35, count 2 2006.201.16:43:33.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.16:43:33.01#ibcon#[27=AT05-04\r\n] 2006.201.16:43:33.01#ibcon#*before write, iclass 35, count 2 2006.201.16:43:33.01#ibcon#enter sib2, iclass 35, count 2 2006.201.16:43:33.01#ibcon#flushed, iclass 35, count 2 2006.201.16:43:33.01#ibcon#about to write, iclass 35, count 2 2006.201.16:43:33.01#ibcon#wrote, iclass 35, count 2 2006.201.16:43:33.01#ibcon#about to read 3, iclass 35, count 2 2006.201.16:43:33.04#ibcon#read 3, iclass 35, count 2 2006.201.16:43:33.04#ibcon#about to read 4, iclass 35, count 2 2006.201.16:43:33.04#ibcon#read 4, iclass 35, count 2 2006.201.16:43:33.04#ibcon#about to read 5, iclass 35, count 2 2006.201.16:43:33.04#ibcon#read 5, iclass 35, count 2 2006.201.16:43:33.04#ibcon#about to read 6, iclass 35, count 2 2006.201.16:43:33.04#ibcon#read 6, iclass 35, count 2 2006.201.16:43:33.04#ibcon#end of sib2, iclass 35, count 2 2006.201.16:43:33.04#ibcon#*after write, iclass 35, count 2 2006.201.16:43:33.04#ibcon#*before return 0, iclass 35, count 2 2006.201.16:43:33.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:33.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:43:33.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.16:43:33.04#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:33.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:33.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:33.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:33.16#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:43:33.16#ibcon#first serial, iclass 35, count 0 2006.201.16:43:33.16#ibcon#enter sib2, iclass 35, count 0 2006.201.16:43:33.16#ibcon#flushed, iclass 35, count 0 2006.201.16:43:33.16#ibcon#about to write, iclass 35, count 0 2006.201.16:43:33.16#ibcon#wrote, iclass 35, count 0 2006.201.16:43:33.16#ibcon#about to read 3, iclass 35, count 0 2006.201.16:43:33.18#ibcon#read 3, iclass 35, count 0 2006.201.16:43:33.18#ibcon#about to read 4, iclass 35, count 0 2006.201.16:43:33.18#ibcon#read 4, iclass 35, count 0 2006.201.16:43:33.18#ibcon#about to read 5, iclass 35, count 0 2006.201.16:43:33.18#ibcon#read 5, iclass 35, count 0 2006.201.16:43:33.18#ibcon#about to read 6, iclass 35, count 0 2006.201.16:43:33.18#ibcon#read 6, iclass 35, count 0 2006.201.16:43:33.18#ibcon#end of sib2, iclass 35, count 0 2006.201.16:43:33.18#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:43:33.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:43:33.18#ibcon#[27=USB\r\n] 2006.201.16:43:33.18#ibcon#*before write, iclass 35, count 0 2006.201.16:43:33.18#ibcon#enter sib2, iclass 35, count 0 2006.201.16:43:33.18#ibcon#flushed, iclass 35, count 0 2006.201.16:43:33.18#ibcon#about to write, iclass 35, count 0 2006.201.16:43:33.18#ibcon#wrote, iclass 35, count 0 2006.201.16:43:33.18#ibcon#about to read 3, iclass 35, count 0 2006.201.16:43:33.21#ibcon#read 3, iclass 35, count 0 2006.201.16:43:33.21#ibcon#about to read 4, iclass 35, count 0 2006.201.16:43:33.21#ibcon#read 4, iclass 35, count 0 2006.201.16:43:33.21#ibcon#about to read 5, iclass 35, count 0 2006.201.16:43:33.21#ibcon#read 5, iclass 35, count 0 2006.201.16:43:33.21#ibcon#about to read 6, iclass 35, count 0 2006.201.16:43:33.21#ibcon#read 6, iclass 35, count 0 2006.201.16:43:33.21#ibcon#end of sib2, iclass 35, count 0 2006.201.16:43:33.21#ibcon#*after write, iclass 35, count 0 2006.201.16:43:33.21#ibcon#*before return 0, iclass 35, count 0 2006.201.16:43:33.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:33.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:43:33.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:43:33.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:43:33.21$vck44/vblo=6,719.99 2006.201.16:43:33.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.16:43:33.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.16:43:33.21#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:33.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:33.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:33.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:33.21#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:43:33.21#ibcon#first serial, iclass 37, count 0 2006.201.16:43:33.21#ibcon#enter sib2, iclass 37, count 0 2006.201.16:43:33.21#ibcon#flushed, iclass 37, count 0 2006.201.16:43:33.21#ibcon#about to write, iclass 37, count 0 2006.201.16:43:33.21#ibcon#wrote, iclass 37, count 0 2006.201.16:43:33.21#ibcon#about to read 3, iclass 37, count 0 2006.201.16:43:33.23#ibcon#read 3, iclass 37, count 0 2006.201.16:43:33.23#ibcon#about to read 4, iclass 37, count 0 2006.201.16:43:33.23#ibcon#read 4, iclass 37, count 0 2006.201.16:43:33.23#ibcon#about to read 5, iclass 37, count 0 2006.201.16:43:33.23#ibcon#read 5, iclass 37, count 0 2006.201.16:43:33.23#ibcon#about to read 6, iclass 37, count 0 2006.201.16:43:33.23#ibcon#read 6, iclass 37, count 0 2006.201.16:43:33.23#ibcon#end of sib2, iclass 37, count 0 2006.201.16:43:33.23#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:43:33.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:43:33.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:43:33.23#ibcon#*before write, iclass 37, count 0 2006.201.16:43:33.23#ibcon#enter sib2, iclass 37, count 0 2006.201.16:43:33.23#ibcon#flushed, iclass 37, count 0 2006.201.16:43:33.23#ibcon#about to write, iclass 37, count 0 2006.201.16:43:33.23#ibcon#wrote, iclass 37, count 0 2006.201.16:43:33.23#ibcon#about to read 3, iclass 37, count 0 2006.201.16:43:33.27#ibcon#read 3, iclass 37, count 0 2006.201.16:43:33.27#ibcon#about to read 4, iclass 37, count 0 2006.201.16:43:33.27#ibcon#read 4, iclass 37, count 0 2006.201.16:43:33.27#ibcon#about to read 5, iclass 37, count 0 2006.201.16:43:33.27#ibcon#read 5, iclass 37, count 0 2006.201.16:43:33.27#ibcon#about to read 6, iclass 37, count 0 2006.201.16:43:33.27#ibcon#read 6, iclass 37, count 0 2006.201.16:43:33.27#ibcon#end of sib2, iclass 37, count 0 2006.201.16:43:33.27#ibcon#*after write, iclass 37, count 0 2006.201.16:43:33.27#ibcon#*before return 0, iclass 37, count 0 2006.201.16:43:33.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:33.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.16:43:33.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:43:33.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:43:33.27$vck44/vb=6,4 2006.201.16:43:33.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.16:43:33.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.16:43:33.27#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:33.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:33.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:33.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:33.33#ibcon#enter wrdev, iclass 39, count 2 2006.201.16:43:33.33#ibcon#first serial, iclass 39, count 2 2006.201.16:43:33.33#ibcon#enter sib2, iclass 39, count 2 2006.201.16:43:33.33#ibcon#flushed, iclass 39, count 2 2006.201.16:43:33.33#ibcon#about to write, iclass 39, count 2 2006.201.16:43:33.33#ibcon#wrote, iclass 39, count 2 2006.201.16:43:33.33#ibcon#about to read 3, iclass 39, count 2 2006.201.16:43:33.35#ibcon#read 3, iclass 39, count 2 2006.201.16:43:33.35#ibcon#about to read 4, iclass 39, count 2 2006.201.16:43:33.35#ibcon#read 4, iclass 39, count 2 2006.201.16:43:33.35#ibcon#about to read 5, iclass 39, count 2 2006.201.16:43:33.35#ibcon#read 5, iclass 39, count 2 2006.201.16:43:33.35#ibcon#about to read 6, iclass 39, count 2 2006.201.16:43:33.35#ibcon#read 6, iclass 39, count 2 2006.201.16:43:33.35#ibcon#end of sib2, iclass 39, count 2 2006.201.16:43:33.35#ibcon#*mode == 0, iclass 39, count 2 2006.201.16:43:33.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.16:43:33.35#ibcon#[27=AT06-04\r\n] 2006.201.16:43:33.35#ibcon#*before write, iclass 39, count 2 2006.201.16:43:33.35#ibcon#enter sib2, iclass 39, count 2 2006.201.16:43:33.35#ibcon#flushed, iclass 39, count 2 2006.201.16:43:33.35#ibcon#about to write, iclass 39, count 2 2006.201.16:43:33.35#ibcon#wrote, iclass 39, count 2 2006.201.16:43:33.35#ibcon#about to read 3, iclass 39, count 2 2006.201.16:43:33.38#ibcon#read 3, iclass 39, count 2 2006.201.16:43:33.38#ibcon#about to read 4, iclass 39, count 2 2006.201.16:43:33.38#ibcon#read 4, iclass 39, count 2 2006.201.16:43:33.38#ibcon#about to read 5, iclass 39, count 2 2006.201.16:43:33.38#ibcon#read 5, iclass 39, count 2 2006.201.16:43:33.38#ibcon#about to read 6, iclass 39, count 2 2006.201.16:43:33.38#ibcon#read 6, iclass 39, count 2 2006.201.16:43:33.38#ibcon#end of sib2, iclass 39, count 2 2006.201.16:43:33.38#ibcon#*after write, iclass 39, count 2 2006.201.16:43:33.38#ibcon#*before return 0, iclass 39, count 2 2006.201.16:43:33.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:33.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.16:43:33.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.16:43:33.38#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:33.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:33.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:33.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:33.50#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:43:33.50#ibcon#first serial, iclass 39, count 0 2006.201.16:43:33.50#ibcon#enter sib2, iclass 39, count 0 2006.201.16:43:33.50#ibcon#flushed, iclass 39, count 0 2006.201.16:43:33.50#ibcon#about to write, iclass 39, count 0 2006.201.16:43:33.50#ibcon#wrote, iclass 39, count 0 2006.201.16:43:33.50#ibcon#about to read 3, iclass 39, count 0 2006.201.16:43:33.52#ibcon#read 3, iclass 39, count 0 2006.201.16:43:33.52#ibcon#about to read 4, iclass 39, count 0 2006.201.16:43:33.52#ibcon#read 4, iclass 39, count 0 2006.201.16:43:33.52#ibcon#about to read 5, iclass 39, count 0 2006.201.16:43:33.52#ibcon#read 5, iclass 39, count 0 2006.201.16:43:33.52#ibcon#about to read 6, iclass 39, count 0 2006.201.16:43:33.52#ibcon#read 6, iclass 39, count 0 2006.201.16:43:33.52#ibcon#end of sib2, iclass 39, count 0 2006.201.16:43:33.52#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:43:33.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:43:33.52#ibcon#[27=USB\r\n] 2006.201.16:43:33.52#ibcon#*before write, iclass 39, count 0 2006.201.16:43:33.52#ibcon#enter sib2, iclass 39, count 0 2006.201.16:43:33.52#ibcon#flushed, iclass 39, count 0 2006.201.16:43:33.52#ibcon#about to write, iclass 39, count 0 2006.201.16:43:33.52#ibcon#wrote, iclass 39, count 0 2006.201.16:43:33.52#ibcon#about to read 3, iclass 39, count 0 2006.201.16:43:33.55#ibcon#read 3, iclass 39, count 0 2006.201.16:43:33.55#ibcon#about to read 4, iclass 39, count 0 2006.201.16:43:33.55#ibcon#read 4, iclass 39, count 0 2006.201.16:43:33.55#ibcon#about to read 5, iclass 39, count 0 2006.201.16:43:33.55#ibcon#read 5, iclass 39, count 0 2006.201.16:43:33.55#ibcon#about to read 6, iclass 39, count 0 2006.201.16:43:33.55#ibcon#read 6, iclass 39, count 0 2006.201.16:43:33.55#ibcon#end of sib2, iclass 39, count 0 2006.201.16:43:33.55#ibcon#*after write, iclass 39, count 0 2006.201.16:43:33.55#ibcon#*before return 0, iclass 39, count 0 2006.201.16:43:33.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:33.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.16:43:33.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:43:33.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:43:33.55$vck44/vblo=7,734.99 2006.201.16:43:33.55#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.16:43:33.55#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.16:43:33.55#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:33.55#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:33.55#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:33.55#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:33.55#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:43:33.55#ibcon#first serial, iclass 2, count 0 2006.201.16:43:33.55#ibcon#enter sib2, iclass 2, count 0 2006.201.16:43:33.55#ibcon#flushed, iclass 2, count 0 2006.201.16:43:33.55#ibcon#about to write, iclass 2, count 0 2006.201.16:43:33.55#ibcon#wrote, iclass 2, count 0 2006.201.16:43:33.55#ibcon#about to read 3, iclass 2, count 0 2006.201.16:43:33.57#ibcon#read 3, iclass 2, count 0 2006.201.16:43:33.57#ibcon#about to read 4, iclass 2, count 0 2006.201.16:43:33.57#ibcon#read 4, iclass 2, count 0 2006.201.16:43:33.57#ibcon#about to read 5, iclass 2, count 0 2006.201.16:43:33.57#ibcon#read 5, iclass 2, count 0 2006.201.16:43:33.57#ibcon#about to read 6, iclass 2, count 0 2006.201.16:43:33.57#ibcon#read 6, iclass 2, count 0 2006.201.16:43:33.57#ibcon#end of sib2, iclass 2, count 0 2006.201.16:43:33.57#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:43:33.57#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:43:33.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:43:33.57#ibcon#*before write, iclass 2, count 0 2006.201.16:43:33.57#ibcon#enter sib2, iclass 2, count 0 2006.201.16:43:33.57#ibcon#flushed, iclass 2, count 0 2006.201.16:43:33.57#ibcon#about to write, iclass 2, count 0 2006.201.16:43:33.57#ibcon#wrote, iclass 2, count 0 2006.201.16:43:33.57#ibcon#about to read 3, iclass 2, count 0 2006.201.16:43:33.61#ibcon#read 3, iclass 2, count 0 2006.201.16:43:33.61#ibcon#about to read 4, iclass 2, count 0 2006.201.16:43:33.61#ibcon#read 4, iclass 2, count 0 2006.201.16:43:33.61#ibcon#about to read 5, iclass 2, count 0 2006.201.16:43:33.61#ibcon#read 5, iclass 2, count 0 2006.201.16:43:33.61#ibcon#about to read 6, iclass 2, count 0 2006.201.16:43:33.61#ibcon#read 6, iclass 2, count 0 2006.201.16:43:33.61#ibcon#end of sib2, iclass 2, count 0 2006.201.16:43:33.61#ibcon#*after write, iclass 2, count 0 2006.201.16:43:33.61#ibcon#*before return 0, iclass 2, count 0 2006.201.16:43:33.61#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:33.61#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.16:43:33.61#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:43:33.61#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:43:33.61$vck44/vb=7,4 2006.201.16:43:33.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.16:43:33.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.16:43:33.61#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:33.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:33.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:33.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:33.67#ibcon#enter wrdev, iclass 5, count 2 2006.201.16:43:33.67#ibcon#first serial, iclass 5, count 2 2006.201.16:43:33.67#ibcon#enter sib2, iclass 5, count 2 2006.201.16:43:33.67#ibcon#flushed, iclass 5, count 2 2006.201.16:43:33.67#ibcon#about to write, iclass 5, count 2 2006.201.16:43:33.67#ibcon#wrote, iclass 5, count 2 2006.201.16:43:33.67#ibcon#about to read 3, iclass 5, count 2 2006.201.16:43:33.69#ibcon#read 3, iclass 5, count 2 2006.201.16:43:33.69#ibcon#about to read 4, iclass 5, count 2 2006.201.16:43:33.69#ibcon#read 4, iclass 5, count 2 2006.201.16:43:33.69#ibcon#about to read 5, iclass 5, count 2 2006.201.16:43:33.69#ibcon#read 5, iclass 5, count 2 2006.201.16:43:33.69#ibcon#about to read 6, iclass 5, count 2 2006.201.16:43:33.69#ibcon#read 6, iclass 5, count 2 2006.201.16:43:33.69#ibcon#end of sib2, iclass 5, count 2 2006.201.16:43:33.69#ibcon#*mode == 0, iclass 5, count 2 2006.201.16:43:33.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.16:43:33.69#ibcon#[27=AT07-04\r\n] 2006.201.16:43:33.69#ibcon#*before write, iclass 5, count 2 2006.201.16:43:33.69#ibcon#enter sib2, iclass 5, count 2 2006.201.16:43:33.69#ibcon#flushed, iclass 5, count 2 2006.201.16:43:33.69#ibcon#about to write, iclass 5, count 2 2006.201.16:43:33.69#ibcon#wrote, iclass 5, count 2 2006.201.16:43:33.69#ibcon#about to read 3, iclass 5, count 2 2006.201.16:43:33.72#ibcon#read 3, iclass 5, count 2 2006.201.16:43:33.72#ibcon#about to read 4, iclass 5, count 2 2006.201.16:43:33.72#ibcon#read 4, iclass 5, count 2 2006.201.16:43:33.72#ibcon#about to read 5, iclass 5, count 2 2006.201.16:43:33.72#ibcon#read 5, iclass 5, count 2 2006.201.16:43:33.72#ibcon#about to read 6, iclass 5, count 2 2006.201.16:43:33.72#ibcon#read 6, iclass 5, count 2 2006.201.16:43:33.72#ibcon#end of sib2, iclass 5, count 2 2006.201.16:43:33.72#ibcon#*after write, iclass 5, count 2 2006.201.16:43:33.72#ibcon#*before return 0, iclass 5, count 2 2006.201.16:43:33.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:33.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.16:43:33.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.16:43:33.72#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:33.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:33.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:33.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:33.84#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:43:33.84#ibcon#first serial, iclass 5, count 0 2006.201.16:43:33.84#ibcon#enter sib2, iclass 5, count 0 2006.201.16:43:33.84#ibcon#flushed, iclass 5, count 0 2006.201.16:43:33.84#ibcon#about to write, iclass 5, count 0 2006.201.16:43:33.84#ibcon#wrote, iclass 5, count 0 2006.201.16:43:33.84#ibcon#about to read 3, iclass 5, count 0 2006.201.16:43:33.86#ibcon#read 3, iclass 5, count 0 2006.201.16:43:33.86#ibcon#about to read 4, iclass 5, count 0 2006.201.16:43:33.86#ibcon#read 4, iclass 5, count 0 2006.201.16:43:33.86#ibcon#about to read 5, iclass 5, count 0 2006.201.16:43:33.86#ibcon#read 5, iclass 5, count 0 2006.201.16:43:33.86#ibcon#about to read 6, iclass 5, count 0 2006.201.16:43:33.86#ibcon#read 6, iclass 5, count 0 2006.201.16:43:33.86#ibcon#end of sib2, iclass 5, count 0 2006.201.16:43:33.86#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:43:33.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:43:33.86#ibcon#[27=USB\r\n] 2006.201.16:43:33.86#ibcon#*before write, iclass 5, count 0 2006.201.16:43:33.86#ibcon#enter sib2, iclass 5, count 0 2006.201.16:43:33.86#ibcon#flushed, iclass 5, count 0 2006.201.16:43:33.86#ibcon#about to write, iclass 5, count 0 2006.201.16:43:33.86#ibcon#wrote, iclass 5, count 0 2006.201.16:43:33.86#ibcon#about to read 3, iclass 5, count 0 2006.201.16:43:33.89#ibcon#read 3, iclass 5, count 0 2006.201.16:43:33.89#ibcon#about to read 4, iclass 5, count 0 2006.201.16:43:33.89#ibcon#read 4, iclass 5, count 0 2006.201.16:43:33.89#ibcon#about to read 5, iclass 5, count 0 2006.201.16:43:33.89#ibcon#read 5, iclass 5, count 0 2006.201.16:43:33.89#ibcon#about to read 6, iclass 5, count 0 2006.201.16:43:33.89#ibcon#read 6, iclass 5, count 0 2006.201.16:43:33.89#ibcon#end of sib2, iclass 5, count 0 2006.201.16:43:33.89#ibcon#*after write, iclass 5, count 0 2006.201.16:43:33.89#ibcon#*before return 0, iclass 5, count 0 2006.201.16:43:33.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:33.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.16:43:33.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:43:33.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:43:33.89$vck44/vblo=8,744.99 2006.201.16:43:33.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.16:43:33.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.16:43:33.89#ibcon#ireg 17 cls_cnt 0 2006.201.16:43:33.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:33.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:33.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:33.89#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:43:33.89#ibcon#first serial, iclass 7, count 0 2006.201.16:43:33.89#ibcon#enter sib2, iclass 7, count 0 2006.201.16:43:33.89#ibcon#flushed, iclass 7, count 0 2006.201.16:43:33.89#ibcon#about to write, iclass 7, count 0 2006.201.16:43:33.89#ibcon#wrote, iclass 7, count 0 2006.201.16:43:33.89#ibcon#about to read 3, iclass 7, count 0 2006.201.16:43:33.91#ibcon#read 3, iclass 7, count 0 2006.201.16:43:33.91#ibcon#about to read 4, iclass 7, count 0 2006.201.16:43:33.91#ibcon#read 4, iclass 7, count 0 2006.201.16:43:33.91#ibcon#about to read 5, iclass 7, count 0 2006.201.16:43:33.91#ibcon#read 5, iclass 7, count 0 2006.201.16:43:33.91#ibcon#about to read 6, iclass 7, count 0 2006.201.16:43:33.91#ibcon#read 6, iclass 7, count 0 2006.201.16:43:33.91#ibcon#end of sib2, iclass 7, count 0 2006.201.16:43:33.91#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:43:33.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:43:33.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:43:33.91#ibcon#*before write, iclass 7, count 0 2006.201.16:43:33.91#ibcon#enter sib2, iclass 7, count 0 2006.201.16:43:33.91#ibcon#flushed, iclass 7, count 0 2006.201.16:43:33.91#ibcon#about to write, iclass 7, count 0 2006.201.16:43:33.91#ibcon#wrote, iclass 7, count 0 2006.201.16:43:33.91#ibcon#about to read 3, iclass 7, count 0 2006.201.16:43:33.95#ibcon#read 3, iclass 7, count 0 2006.201.16:43:33.95#ibcon#about to read 4, iclass 7, count 0 2006.201.16:43:33.95#ibcon#read 4, iclass 7, count 0 2006.201.16:43:33.95#ibcon#about to read 5, iclass 7, count 0 2006.201.16:43:33.95#ibcon#read 5, iclass 7, count 0 2006.201.16:43:33.95#ibcon#about to read 6, iclass 7, count 0 2006.201.16:43:33.95#ibcon#read 6, iclass 7, count 0 2006.201.16:43:33.95#ibcon#end of sib2, iclass 7, count 0 2006.201.16:43:33.95#ibcon#*after write, iclass 7, count 0 2006.201.16:43:33.95#ibcon#*before return 0, iclass 7, count 0 2006.201.16:43:33.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:33.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.16:43:33.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:43:33.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:43:33.95$vck44/vb=8,4 2006.201.16:43:33.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.16:43:33.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.16:43:33.95#ibcon#ireg 11 cls_cnt 2 2006.201.16:43:33.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:34.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:34.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:34.01#ibcon#enter wrdev, iclass 11, count 2 2006.201.16:43:34.01#ibcon#first serial, iclass 11, count 2 2006.201.16:43:34.01#ibcon#enter sib2, iclass 11, count 2 2006.201.16:43:34.01#ibcon#flushed, iclass 11, count 2 2006.201.16:43:34.01#ibcon#about to write, iclass 11, count 2 2006.201.16:43:34.01#ibcon#wrote, iclass 11, count 2 2006.201.16:43:34.01#ibcon#about to read 3, iclass 11, count 2 2006.201.16:43:34.03#ibcon#read 3, iclass 11, count 2 2006.201.16:43:34.03#ibcon#about to read 4, iclass 11, count 2 2006.201.16:43:34.03#ibcon#read 4, iclass 11, count 2 2006.201.16:43:34.03#ibcon#about to read 5, iclass 11, count 2 2006.201.16:43:34.03#ibcon#read 5, iclass 11, count 2 2006.201.16:43:34.03#ibcon#about to read 6, iclass 11, count 2 2006.201.16:43:34.03#ibcon#read 6, iclass 11, count 2 2006.201.16:43:34.03#ibcon#end of sib2, iclass 11, count 2 2006.201.16:43:34.03#ibcon#*mode == 0, iclass 11, count 2 2006.201.16:43:34.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.16:43:34.03#ibcon#[27=AT08-04\r\n] 2006.201.16:43:34.03#ibcon#*before write, iclass 11, count 2 2006.201.16:43:34.03#ibcon#enter sib2, iclass 11, count 2 2006.201.16:43:34.03#ibcon#flushed, iclass 11, count 2 2006.201.16:43:34.03#ibcon#about to write, iclass 11, count 2 2006.201.16:43:34.03#ibcon#wrote, iclass 11, count 2 2006.201.16:43:34.03#ibcon#about to read 3, iclass 11, count 2 2006.201.16:43:34.06#ibcon#read 3, iclass 11, count 2 2006.201.16:43:34.06#ibcon#about to read 4, iclass 11, count 2 2006.201.16:43:34.06#ibcon#read 4, iclass 11, count 2 2006.201.16:43:34.06#ibcon#about to read 5, iclass 11, count 2 2006.201.16:43:34.06#ibcon#read 5, iclass 11, count 2 2006.201.16:43:34.06#ibcon#about to read 6, iclass 11, count 2 2006.201.16:43:34.06#ibcon#read 6, iclass 11, count 2 2006.201.16:43:34.06#ibcon#end of sib2, iclass 11, count 2 2006.201.16:43:34.06#ibcon#*after write, iclass 11, count 2 2006.201.16:43:34.06#ibcon#*before return 0, iclass 11, count 2 2006.201.16:43:34.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:34.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.16:43:34.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.16:43:34.06#ibcon#ireg 7 cls_cnt 0 2006.201.16:43:34.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:34.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:34.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:34.18#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:43:34.18#ibcon#first serial, iclass 11, count 0 2006.201.16:43:34.18#ibcon#enter sib2, iclass 11, count 0 2006.201.16:43:34.18#ibcon#flushed, iclass 11, count 0 2006.201.16:43:34.18#ibcon#about to write, iclass 11, count 0 2006.201.16:43:34.18#ibcon#wrote, iclass 11, count 0 2006.201.16:43:34.18#ibcon#about to read 3, iclass 11, count 0 2006.201.16:43:34.20#ibcon#read 3, iclass 11, count 0 2006.201.16:43:34.20#ibcon#about to read 4, iclass 11, count 0 2006.201.16:43:34.20#ibcon#read 4, iclass 11, count 0 2006.201.16:43:34.20#ibcon#about to read 5, iclass 11, count 0 2006.201.16:43:34.20#ibcon#read 5, iclass 11, count 0 2006.201.16:43:34.20#ibcon#about to read 6, iclass 11, count 0 2006.201.16:43:34.20#ibcon#read 6, iclass 11, count 0 2006.201.16:43:34.20#ibcon#end of sib2, iclass 11, count 0 2006.201.16:43:34.20#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:43:34.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:43:34.20#ibcon#[27=USB\r\n] 2006.201.16:43:34.20#ibcon#*before write, iclass 11, count 0 2006.201.16:43:34.20#ibcon#enter sib2, iclass 11, count 0 2006.201.16:43:34.20#ibcon#flushed, iclass 11, count 0 2006.201.16:43:34.20#ibcon#about to write, iclass 11, count 0 2006.201.16:43:34.20#ibcon#wrote, iclass 11, count 0 2006.201.16:43:34.20#ibcon#about to read 3, iclass 11, count 0 2006.201.16:43:34.23#ibcon#read 3, iclass 11, count 0 2006.201.16:43:34.23#ibcon#about to read 4, iclass 11, count 0 2006.201.16:43:34.23#ibcon#read 4, iclass 11, count 0 2006.201.16:43:34.23#ibcon#about to read 5, iclass 11, count 0 2006.201.16:43:34.23#ibcon#read 5, iclass 11, count 0 2006.201.16:43:34.23#ibcon#about to read 6, iclass 11, count 0 2006.201.16:43:34.23#ibcon#read 6, iclass 11, count 0 2006.201.16:43:34.23#ibcon#end of sib2, iclass 11, count 0 2006.201.16:43:34.23#ibcon#*after write, iclass 11, count 0 2006.201.16:43:34.23#ibcon#*before return 0, iclass 11, count 0 2006.201.16:43:34.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:34.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.16:43:34.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:43:34.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:43:34.23$vck44/vabw=wide 2006.201.16:43:34.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.16:43:34.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.16:43:34.23#ibcon#ireg 8 cls_cnt 0 2006.201.16:43:34.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:34.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:34.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:34.23#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:43:34.23#ibcon#first serial, iclass 13, count 0 2006.201.16:43:34.23#ibcon#enter sib2, iclass 13, count 0 2006.201.16:43:34.23#ibcon#flushed, iclass 13, count 0 2006.201.16:43:34.23#ibcon#about to write, iclass 13, count 0 2006.201.16:43:34.23#ibcon#wrote, iclass 13, count 0 2006.201.16:43:34.23#ibcon#about to read 3, iclass 13, count 0 2006.201.16:43:34.25#ibcon#read 3, iclass 13, count 0 2006.201.16:43:34.25#ibcon#about to read 4, iclass 13, count 0 2006.201.16:43:34.25#ibcon#read 4, iclass 13, count 0 2006.201.16:43:34.25#ibcon#about to read 5, iclass 13, count 0 2006.201.16:43:34.25#ibcon#read 5, iclass 13, count 0 2006.201.16:43:34.25#ibcon#about to read 6, iclass 13, count 0 2006.201.16:43:34.25#ibcon#read 6, iclass 13, count 0 2006.201.16:43:34.25#ibcon#end of sib2, iclass 13, count 0 2006.201.16:43:34.25#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:43:34.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:43:34.25#ibcon#[25=BW32\r\n] 2006.201.16:43:34.25#ibcon#*before write, iclass 13, count 0 2006.201.16:43:34.25#ibcon#enter sib2, iclass 13, count 0 2006.201.16:43:34.25#ibcon#flushed, iclass 13, count 0 2006.201.16:43:34.25#ibcon#about to write, iclass 13, count 0 2006.201.16:43:34.25#ibcon#wrote, iclass 13, count 0 2006.201.16:43:34.25#ibcon#about to read 3, iclass 13, count 0 2006.201.16:43:34.28#ibcon#read 3, iclass 13, count 0 2006.201.16:43:34.28#ibcon#about to read 4, iclass 13, count 0 2006.201.16:43:34.28#ibcon#read 4, iclass 13, count 0 2006.201.16:43:34.28#ibcon#about to read 5, iclass 13, count 0 2006.201.16:43:34.28#ibcon#read 5, iclass 13, count 0 2006.201.16:43:34.28#ibcon#about to read 6, iclass 13, count 0 2006.201.16:43:34.28#ibcon#read 6, iclass 13, count 0 2006.201.16:43:34.28#ibcon#end of sib2, iclass 13, count 0 2006.201.16:43:34.28#ibcon#*after write, iclass 13, count 0 2006.201.16:43:34.28#ibcon#*before return 0, iclass 13, count 0 2006.201.16:43:34.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:34.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.16:43:34.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:43:34.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:43:34.28$vck44/vbbw=wide 2006.201.16:43:34.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.16:43:34.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.16:43:34.28#ibcon#ireg 8 cls_cnt 0 2006.201.16:43:34.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:43:34.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:43:34.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:43:34.35#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:43:34.35#ibcon#first serial, iclass 15, count 0 2006.201.16:43:34.35#ibcon#enter sib2, iclass 15, count 0 2006.201.16:43:34.35#ibcon#flushed, iclass 15, count 0 2006.201.16:43:34.35#ibcon#about to write, iclass 15, count 0 2006.201.16:43:34.35#ibcon#wrote, iclass 15, count 0 2006.201.16:43:34.35#ibcon#about to read 3, iclass 15, count 0 2006.201.16:43:34.37#ibcon#read 3, iclass 15, count 0 2006.201.16:43:34.37#ibcon#about to read 4, iclass 15, count 0 2006.201.16:43:34.37#ibcon#read 4, iclass 15, count 0 2006.201.16:43:34.37#ibcon#about to read 5, iclass 15, count 0 2006.201.16:43:34.37#ibcon#read 5, iclass 15, count 0 2006.201.16:43:34.37#ibcon#about to read 6, iclass 15, count 0 2006.201.16:43:34.37#ibcon#read 6, iclass 15, count 0 2006.201.16:43:34.37#ibcon#end of sib2, iclass 15, count 0 2006.201.16:43:34.37#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:43:34.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:43:34.37#ibcon#[27=BW32\r\n] 2006.201.16:43:34.37#ibcon#*before write, iclass 15, count 0 2006.201.16:43:34.37#ibcon#enter sib2, iclass 15, count 0 2006.201.16:43:34.37#ibcon#flushed, iclass 15, count 0 2006.201.16:43:34.37#ibcon#about to write, iclass 15, count 0 2006.201.16:43:34.37#ibcon#wrote, iclass 15, count 0 2006.201.16:43:34.37#ibcon#about to read 3, iclass 15, count 0 2006.201.16:43:34.40#ibcon#read 3, iclass 15, count 0 2006.201.16:43:34.40#ibcon#about to read 4, iclass 15, count 0 2006.201.16:43:34.40#ibcon#read 4, iclass 15, count 0 2006.201.16:43:34.40#ibcon#about to read 5, iclass 15, count 0 2006.201.16:43:34.40#ibcon#read 5, iclass 15, count 0 2006.201.16:43:34.40#ibcon#about to read 6, iclass 15, count 0 2006.201.16:43:34.40#ibcon#read 6, iclass 15, count 0 2006.201.16:43:34.40#ibcon#end of sib2, iclass 15, count 0 2006.201.16:43:34.40#ibcon#*after write, iclass 15, count 0 2006.201.16:43:34.40#ibcon#*before return 0, iclass 15, count 0 2006.201.16:43:34.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:43:34.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:43:34.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:43:34.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:43:34.40$setupk4/ifdk4 2006.201.16:43:34.40$ifdk4/lo= 2006.201.16:43:34.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:43:34.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:43:34.40$ifdk4/patch= 2006.201.16:43:34.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:43:34.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:43:34.40$setupk4/!*+20s 2006.201.16:43:39.14#trakl#Source acquired 2006.201.16:43:39.14#flagr#flagr/antenna,acquired 2006.201.16:43:39.26#abcon#<5=/04 0.5 1.0 20.821001002.7\r\n> 2006.201.16:43:39.28#abcon#{5=INTERFACE CLEAR} 2006.201.16:43:39.34#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:43:48.88$setupk4/"tpicd 2006.201.16:43:48.88$setupk4/echo=off 2006.201.16:43:48.88$setupk4/xlog=off 2006.201.16:43:48.88:!2006.201.16:46:56 2006.201.16:46:56.00:preob 2006.201.16:46:56.13/onsource/TRACKING 2006.201.16:46:56.13:!2006.201.16:47:06 2006.201.16:47:06.00:"tape 2006.201.16:47:06.00:"st=record 2006.201.16:47:06.00:data_valid=on 2006.201.16:47:06.00:midob 2006.201.16:47:06.13/onsource/TRACKING 2006.201.16:47:06.13/wx/20.81,1002.6,100 2006.201.16:47:06.21/cable/+6.4791E-03 2006.201.16:47:07.30/va/01,08,usb,yes,40,42 2006.201.16:47:07.30/va/02,07,usb,yes,43,44 2006.201.16:47:07.30/va/03,08,usb,yes,39,40 2006.201.16:47:07.30/va/04,07,usb,yes,44,46 2006.201.16:47:07.30/va/05,04,usb,yes,39,40 2006.201.16:47:07.30/va/06,05,usb,yes,39,39 2006.201.16:47:07.30/va/07,05,usb,yes,38,40 2006.201.16:47:07.30/va/08,04,usb,yes,38,45 2006.201.16:47:07.53/valo/01,524.99,yes,locked 2006.201.16:47:07.53/valo/02,534.99,yes,locked 2006.201.16:47:07.53/valo/03,564.99,yes,locked 2006.201.16:47:07.53/valo/04,624.99,yes,locked 2006.201.16:47:07.53/valo/05,734.99,yes,locked 2006.201.16:47:07.53/valo/06,814.99,yes,locked 2006.201.16:47:07.53/valo/07,864.99,yes,locked 2006.201.16:47:07.53/valo/08,884.99,yes,locked 2006.201.16:47:08.62/vb/01,04,usb,yes,32,30 2006.201.16:47:08.62/vb/02,05,usb,yes,30,30 2006.201.16:47:08.62/vb/03,04,usb,yes,31,35 2006.201.16:47:08.62/vb/04,05,usb,yes,32,31 2006.201.16:47:08.62/vb/05,04,usb,yes,28,31 2006.201.16:47:08.62/vb/06,04,usb,yes,33,29 2006.201.16:47:08.62/vb/07,04,usb,yes,33,32 2006.201.16:47:08.62/vb/08,04,usb,yes,30,34 2006.201.16:47:08.85/vblo/01,629.99,yes,locked 2006.201.16:47:08.85/vblo/02,634.99,yes,locked 2006.201.16:47:08.85/vblo/03,649.99,yes,locked 2006.201.16:47:08.85/vblo/04,679.99,yes,locked 2006.201.16:47:08.85/vblo/05,709.99,yes,locked 2006.201.16:47:08.85/vblo/06,719.99,yes,locked 2006.201.16:47:08.85/vblo/07,734.99,yes,locked 2006.201.16:47:08.85/vblo/08,744.99,yes,locked 2006.201.16:47:09.00/vabw/8 2006.201.16:47:09.15/vbbw/8 2006.201.16:47:09.24/xfe/off,on,15.2 2006.201.16:47:09.63/ifatt/23,28,28,28 2006.201.16:47:10.06/fmout-gps/S +4.63E-07 2006.201.16:47:10.10:!2006.201.16:47:46 2006.201.16:47:46.00:data_valid=off 2006.201.16:47:46.00:"et 2006.201.16:47:46.00:!+3s 2006.201.16:47:49.02:"tape 2006.201.16:47:49.02:postob 2006.201.16:47:49.09/cable/+6.4789E-03 2006.201.16:47:49.09/wx/20.81,1002.6,100 2006.201.16:47:49.16/fmout-gps/S +4.63E-07 2006.201.16:47:49.16:scan_name=201-1653,jd0607,70 2006.201.16:47:49.17:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.201.16:47:51.14#flagr#flagr/antenna,new-source 2006.201.16:47:51.14:checkk5 2006.201.16:47:51.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:47:51.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:47:52.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:47:52.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:47:53.02/chk_obsdata//k5ts1/T2011647??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:47:53.39/chk_obsdata//k5ts2/T2011647??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:47:53.75/chk_obsdata//k5ts3/T2011647??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:47:54.12/chk_obsdata//k5ts4/T2011647??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.16:47:54.81/k5log//k5ts1_log_newline 2006.201.16:47:55.50/k5log//k5ts2_log_newline 2006.201.16:47:56.18/k5log//k5ts3_log_newline 2006.201.16:47:56.87/k5log//k5ts4_log_newline 2006.201.16:47:56.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:47:56.89:setupk4=1 2006.201.16:47:56.89$setupk4/echo=on 2006.201.16:47:56.89$setupk4/pcalon 2006.201.16:47:56.89$pcalon/"no phase cal control is implemented here 2006.201.16:47:56.89$setupk4/"tpicd=stop 2006.201.16:47:56.89$setupk4/"rec=synch_on 2006.201.16:47:56.89$setupk4/"rec_mode=128 2006.201.16:47:56.89$setupk4/!* 2006.201.16:47:56.89$setupk4/recpk4 2006.201.16:47:56.89$recpk4/recpatch= 2006.201.16:47:56.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:47:56.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:47:56.90$setupk4/vck44 2006.201.16:47:56.90$vck44/valo=1,524.99 2006.201.16:47:56.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.16:47:56.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.16:47:56.90#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:56.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:56.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:56.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:56.90#ibcon#enter wrdev, iclass 16, count 0 2006.201.16:47:56.90#ibcon#first serial, iclass 16, count 0 2006.201.16:47:56.90#ibcon#enter sib2, iclass 16, count 0 2006.201.16:47:56.90#ibcon#flushed, iclass 16, count 0 2006.201.16:47:56.90#ibcon#about to write, iclass 16, count 0 2006.201.16:47:56.90#ibcon#wrote, iclass 16, count 0 2006.201.16:47:56.90#ibcon#about to read 3, iclass 16, count 0 2006.201.16:47:56.93#ibcon#read 3, iclass 16, count 0 2006.201.16:47:56.93#ibcon#about to read 4, iclass 16, count 0 2006.201.16:47:56.93#ibcon#read 4, iclass 16, count 0 2006.201.16:47:56.93#ibcon#about to read 5, iclass 16, count 0 2006.201.16:47:56.93#ibcon#read 5, iclass 16, count 0 2006.201.16:47:56.93#ibcon#about to read 6, iclass 16, count 0 2006.201.16:47:56.93#ibcon#read 6, iclass 16, count 0 2006.201.16:47:56.93#ibcon#end of sib2, iclass 16, count 0 2006.201.16:47:56.93#ibcon#*mode == 0, iclass 16, count 0 2006.201.16:47:56.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.16:47:56.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:47:56.93#ibcon#*before write, iclass 16, count 0 2006.201.16:47:56.93#ibcon#enter sib2, iclass 16, count 0 2006.201.16:47:56.93#ibcon#flushed, iclass 16, count 0 2006.201.16:47:56.93#ibcon#about to write, iclass 16, count 0 2006.201.16:47:56.93#ibcon#wrote, iclass 16, count 0 2006.201.16:47:56.93#ibcon#about to read 3, iclass 16, count 0 2006.201.16:47:56.98#ibcon#read 3, iclass 16, count 0 2006.201.16:47:56.98#ibcon#about to read 4, iclass 16, count 0 2006.201.16:47:56.98#ibcon#read 4, iclass 16, count 0 2006.201.16:47:56.98#ibcon#about to read 5, iclass 16, count 0 2006.201.16:47:56.98#ibcon#read 5, iclass 16, count 0 2006.201.16:47:56.98#ibcon#about to read 6, iclass 16, count 0 2006.201.16:47:56.98#ibcon#read 6, iclass 16, count 0 2006.201.16:47:56.98#ibcon#end of sib2, iclass 16, count 0 2006.201.16:47:56.98#ibcon#*after write, iclass 16, count 0 2006.201.16:47:56.98#ibcon#*before return 0, iclass 16, count 0 2006.201.16:47:56.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:56.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:56.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.16:47:56.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.16:47:56.98$vck44/va=1,8 2006.201.16:47:56.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.16:47:56.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.16:47:56.98#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:56.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:47:56.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:47:56.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:47:56.98#ibcon#enter wrdev, iclass 18, count 2 2006.201.16:47:56.98#ibcon#first serial, iclass 18, count 2 2006.201.16:47:56.98#ibcon#enter sib2, iclass 18, count 2 2006.201.16:47:56.98#ibcon#flushed, iclass 18, count 2 2006.201.16:47:56.98#ibcon#about to write, iclass 18, count 2 2006.201.16:47:56.98#ibcon#wrote, iclass 18, count 2 2006.201.16:47:56.98#ibcon#about to read 3, iclass 18, count 2 2006.201.16:47:57.00#ibcon#read 3, iclass 18, count 2 2006.201.16:47:57.00#ibcon#about to read 4, iclass 18, count 2 2006.201.16:47:57.00#ibcon#read 4, iclass 18, count 2 2006.201.16:47:57.00#ibcon#about to read 5, iclass 18, count 2 2006.201.16:47:57.00#ibcon#read 5, iclass 18, count 2 2006.201.16:47:57.00#ibcon#about to read 6, iclass 18, count 2 2006.201.16:47:57.00#ibcon#read 6, iclass 18, count 2 2006.201.16:47:57.00#ibcon#end of sib2, iclass 18, count 2 2006.201.16:47:57.00#ibcon#*mode == 0, iclass 18, count 2 2006.201.16:47:57.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.16:47:57.00#ibcon#[25=AT01-08\r\n] 2006.201.16:47:57.00#ibcon#*before write, iclass 18, count 2 2006.201.16:47:57.00#ibcon#enter sib2, iclass 18, count 2 2006.201.16:47:57.00#ibcon#flushed, iclass 18, count 2 2006.201.16:47:57.00#ibcon#about to write, iclass 18, count 2 2006.201.16:47:57.00#ibcon#wrote, iclass 18, count 2 2006.201.16:47:57.00#ibcon#about to read 3, iclass 18, count 2 2006.201.16:47:57.03#ibcon#read 3, iclass 18, count 2 2006.201.16:47:57.03#ibcon#about to read 4, iclass 18, count 2 2006.201.16:47:57.03#ibcon#read 4, iclass 18, count 2 2006.201.16:47:57.03#ibcon#about to read 5, iclass 18, count 2 2006.201.16:47:57.03#ibcon#read 5, iclass 18, count 2 2006.201.16:47:57.03#ibcon#about to read 6, iclass 18, count 2 2006.201.16:47:57.03#ibcon#read 6, iclass 18, count 2 2006.201.16:47:57.03#ibcon#end of sib2, iclass 18, count 2 2006.201.16:47:57.03#ibcon#*after write, iclass 18, count 2 2006.201.16:47:57.03#ibcon#*before return 0, iclass 18, count 2 2006.201.16:47:57.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:47:57.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:47:57.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.16:47:57.03#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:57.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:47:57.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:47:57.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:47:57.15#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:47:57.15#ibcon#first serial, iclass 18, count 0 2006.201.16:47:57.15#ibcon#enter sib2, iclass 18, count 0 2006.201.16:47:57.15#ibcon#flushed, iclass 18, count 0 2006.201.16:47:57.15#ibcon#about to write, iclass 18, count 0 2006.201.16:47:57.15#ibcon#wrote, iclass 18, count 0 2006.201.16:47:57.15#ibcon#about to read 3, iclass 18, count 0 2006.201.16:47:57.17#ibcon#read 3, iclass 18, count 0 2006.201.16:47:57.17#ibcon#about to read 4, iclass 18, count 0 2006.201.16:47:57.17#ibcon#read 4, iclass 18, count 0 2006.201.16:47:57.17#ibcon#about to read 5, iclass 18, count 0 2006.201.16:47:57.17#ibcon#read 5, iclass 18, count 0 2006.201.16:47:57.17#ibcon#about to read 6, iclass 18, count 0 2006.201.16:47:57.17#ibcon#read 6, iclass 18, count 0 2006.201.16:47:57.17#ibcon#end of sib2, iclass 18, count 0 2006.201.16:47:57.17#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:47:57.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:47:57.17#ibcon#[25=USB\r\n] 2006.201.16:47:57.17#ibcon#*before write, iclass 18, count 0 2006.201.16:47:57.17#ibcon#enter sib2, iclass 18, count 0 2006.201.16:47:57.17#ibcon#flushed, iclass 18, count 0 2006.201.16:47:57.17#ibcon#about to write, iclass 18, count 0 2006.201.16:47:57.17#ibcon#wrote, iclass 18, count 0 2006.201.16:47:57.17#ibcon#about to read 3, iclass 18, count 0 2006.201.16:47:57.20#ibcon#read 3, iclass 18, count 0 2006.201.16:47:57.20#ibcon#about to read 4, iclass 18, count 0 2006.201.16:47:57.20#ibcon#read 4, iclass 18, count 0 2006.201.16:47:57.20#ibcon#about to read 5, iclass 18, count 0 2006.201.16:47:57.20#ibcon#read 5, iclass 18, count 0 2006.201.16:47:57.20#ibcon#about to read 6, iclass 18, count 0 2006.201.16:47:57.20#ibcon#read 6, iclass 18, count 0 2006.201.16:47:57.20#ibcon#end of sib2, iclass 18, count 0 2006.201.16:47:57.20#ibcon#*after write, iclass 18, count 0 2006.201.16:47:57.20#ibcon#*before return 0, iclass 18, count 0 2006.201.16:47:57.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:47:57.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:47:57.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:47:57.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:47:57.20$vck44/valo=2,534.99 2006.201.16:47:57.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.16:47:57.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.16:47:57.20#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:57.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:47:57.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:47:57.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:47:57.20#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:47:57.20#ibcon#first serial, iclass 20, count 0 2006.201.16:47:57.20#ibcon#enter sib2, iclass 20, count 0 2006.201.16:47:57.20#ibcon#flushed, iclass 20, count 0 2006.201.16:47:57.20#ibcon#about to write, iclass 20, count 0 2006.201.16:47:57.20#ibcon#wrote, iclass 20, count 0 2006.201.16:47:57.20#ibcon#about to read 3, iclass 20, count 0 2006.201.16:47:57.22#ibcon#read 3, iclass 20, count 0 2006.201.16:47:57.22#ibcon#about to read 4, iclass 20, count 0 2006.201.16:47:57.22#ibcon#read 4, iclass 20, count 0 2006.201.16:47:57.22#ibcon#about to read 5, iclass 20, count 0 2006.201.16:47:57.22#ibcon#read 5, iclass 20, count 0 2006.201.16:47:57.22#ibcon#about to read 6, iclass 20, count 0 2006.201.16:47:57.22#ibcon#read 6, iclass 20, count 0 2006.201.16:47:57.22#ibcon#end of sib2, iclass 20, count 0 2006.201.16:47:57.22#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:47:57.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:47:57.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:47:57.22#ibcon#*before write, iclass 20, count 0 2006.201.16:47:57.22#ibcon#enter sib2, iclass 20, count 0 2006.201.16:47:57.22#ibcon#flushed, iclass 20, count 0 2006.201.16:47:57.22#ibcon#about to write, iclass 20, count 0 2006.201.16:47:57.22#ibcon#wrote, iclass 20, count 0 2006.201.16:47:57.22#ibcon#about to read 3, iclass 20, count 0 2006.201.16:47:57.27#ibcon#read 3, iclass 20, count 0 2006.201.16:47:57.27#ibcon#about to read 4, iclass 20, count 0 2006.201.16:47:57.27#ibcon#read 4, iclass 20, count 0 2006.201.16:47:57.27#ibcon#about to read 5, iclass 20, count 0 2006.201.16:47:57.27#ibcon#read 5, iclass 20, count 0 2006.201.16:47:57.27#ibcon#about to read 6, iclass 20, count 0 2006.201.16:47:57.27#ibcon#read 6, iclass 20, count 0 2006.201.16:47:57.27#ibcon#end of sib2, iclass 20, count 0 2006.201.16:47:57.27#ibcon#*after write, iclass 20, count 0 2006.201.16:47:57.27#ibcon#*before return 0, iclass 20, count 0 2006.201.16:47:57.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:47:57.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:47:57.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:47:57.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:47:57.27$vck44/va=2,7 2006.201.16:47:57.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.16:47:57.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.16:47:57.27#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:57.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:47:57.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:47:57.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:47:57.32#ibcon#enter wrdev, iclass 22, count 2 2006.201.16:47:57.32#ibcon#first serial, iclass 22, count 2 2006.201.16:47:57.32#ibcon#enter sib2, iclass 22, count 2 2006.201.16:47:57.32#ibcon#flushed, iclass 22, count 2 2006.201.16:47:57.32#ibcon#about to write, iclass 22, count 2 2006.201.16:47:57.32#ibcon#wrote, iclass 22, count 2 2006.201.16:47:57.32#ibcon#about to read 3, iclass 22, count 2 2006.201.16:47:57.34#ibcon#read 3, iclass 22, count 2 2006.201.16:47:57.34#ibcon#about to read 4, iclass 22, count 2 2006.201.16:47:57.34#ibcon#read 4, iclass 22, count 2 2006.201.16:47:57.34#ibcon#about to read 5, iclass 22, count 2 2006.201.16:47:57.34#ibcon#read 5, iclass 22, count 2 2006.201.16:47:57.34#ibcon#about to read 6, iclass 22, count 2 2006.201.16:47:57.34#ibcon#read 6, iclass 22, count 2 2006.201.16:47:57.34#ibcon#end of sib2, iclass 22, count 2 2006.201.16:47:57.34#ibcon#*mode == 0, iclass 22, count 2 2006.201.16:47:57.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.16:47:57.34#ibcon#[25=AT02-07\r\n] 2006.201.16:47:57.34#ibcon#*before write, iclass 22, count 2 2006.201.16:47:57.34#ibcon#enter sib2, iclass 22, count 2 2006.201.16:47:57.34#ibcon#flushed, iclass 22, count 2 2006.201.16:47:57.34#ibcon#about to write, iclass 22, count 2 2006.201.16:47:57.34#ibcon#wrote, iclass 22, count 2 2006.201.16:47:57.34#ibcon#about to read 3, iclass 22, count 2 2006.201.16:47:57.37#ibcon#read 3, iclass 22, count 2 2006.201.16:47:57.37#ibcon#about to read 4, iclass 22, count 2 2006.201.16:47:57.37#ibcon#read 4, iclass 22, count 2 2006.201.16:47:57.37#ibcon#about to read 5, iclass 22, count 2 2006.201.16:47:57.37#ibcon#read 5, iclass 22, count 2 2006.201.16:47:57.37#ibcon#about to read 6, iclass 22, count 2 2006.201.16:47:57.37#ibcon#read 6, iclass 22, count 2 2006.201.16:47:57.37#ibcon#end of sib2, iclass 22, count 2 2006.201.16:47:57.37#ibcon#*after write, iclass 22, count 2 2006.201.16:47:57.37#ibcon#*before return 0, iclass 22, count 2 2006.201.16:47:57.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:47:57.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:47:57.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.16:47:57.37#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:57.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:47:57.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:47:57.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:47:57.49#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:47:57.49#ibcon#first serial, iclass 22, count 0 2006.201.16:47:57.49#ibcon#enter sib2, iclass 22, count 0 2006.201.16:47:57.49#ibcon#flushed, iclass 22, count 0 2006.201.16:47:57.49#ibcon#about to write, iclass 22, count 0 2006.201.16:47:57.49#ibcon#wrote, iclass 22, count 0 2006.201.16:47:57.49#ibcon#about to read 3, iclass 22, count 0 2006.201.16:47:57.51#ibcon#read 3, iclass 22, count 0 2006.201.16:47:57.51#ibcon#about to read 4, iclass 22, count 0 2006.201.16:47:57.51#ibcon#read 4, iclass 22, count 0 2006.201.16:47:57.51#ibcon#about to read 5, iclass 22, count 0 2006.201.16:47:57.51#ibcon#read 5, iclass 22, count 0 2006.201.16:47:57.51#ibcon#about to read 6, iclass 22, count 0 2006.201.16:47:57.51#ibcon#read 6, iclass 22, count 0 2006.201.16:47:57.51#ibcon#end of sib2, iclass 22, count 0 2006.201.16:47:57.51#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:47:57.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:47:57.51#ibcon#[25=USB\r\n] 2006.201.16:47:57.51#ibcon#*before write, iclass 22, count 0 2006.201.16:47:57.51#ibcon#enter sib2, iclass 22, count 0 2006.201.16:47:57.51#ibcon#flushed, iclass 22, count 0 2006.201.16:47:57.51#ibcon#about to write, iclass 22, count 0 2006.201.16:47:57.51#ibcon#wrote, iclass 22, count 0 2006.201.16:47:57.51#ibcon#about to read 3, iclass 22, count 0 2006.201.16:47:57.54#ibcon#read 3, iclass 22, count 0 2006.201.16:47:57.54#ibcon#about to read 4, iclass 22, count 0 2006.201.16:47:57.54#ibcon#read 4, iclass 22, count 0 2006.201.16:47:57.54#ibcon#about to read 5, iclass 22, count 0 2006.201.16:47:57.54#ibcon#read 5, iclass 22, count 0 2006.201.16:47:57.54#ibcon#about to read 6, iclass 22, count 0 2006.201.16:47:57.54#ibcon#read 6, iclass 22, count 0 2006.201.16:47:57.54#ibcon#end of sib2, iclass 22, count 0 2006.201.16:47:57.54#ibcon#*after write, iclass 22, count 0 2006.201.16:47:57.54#ibcon#*before return 0, iclass 22, count 0 2006.201.16:47:57.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:47:57.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:47:57.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:47:57.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:47:57.54$vck44/valo=3,564.99 2006.201.16:47:57.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.16:47:57.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.16:47:57.54#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:57.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:47:57.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:47:57.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:47:57.54#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:47:57.54#ibcon#first serial, iclass 24, count 0 2006.201.16:47:57.54#ibcon#enter sib2, iclass 24, count 0 2006.201.16:47:57.54#ibcon#flushed, iclass 24, count 0 2006.201.16:47:57.54#ibcon#about to write, iclass 24, count 0 2006.201.16:47:57.54#ibcon#wrote, iclass 24, count 0 2006.201.16:47:57.54#ibcon#about to read 3, iclass 24, count 0 2006.201.16:47:57.56#ibcon#read 3, iclass 24, count 0 2006.201.16:47:57.56#ibcon#about to read 4, iclass 24, count 0 2006.201.16:47:57.56#ibcon#read 4, iclass 24, count 0 2006.201.16:47:57.56#ibcon#about to read 5, iclass 24, count 0 2006.201.16:47:57.56#ibcon#read 5, iclass 24, count 0 2006.201.16:47:57.56#ibcon#about to read 6, iclass 24, count 0 2006.201.16:47:57.56#ibcon#read 6, iclass 24, count 0 2006.201.16:47:57.56#ibcon#end of sib2, iclass 24, count 0 2006.201.16:47:57.56#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:47:57.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:47:57.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:47:57.56#ibcon#*before write, iclass 24, count 0 2006.201.16:47:57.56#ibcon#enter sib2, iclass 24, count 0 2006.201.16:47:57.56#ibcon#flushed, iclass 24, count 0 2006.201.16:47:57.56#ibcon#about to write, iclass 24, count 0 2006.201.16:47:57.56#ibcon#wrote, iclass 24, count 0 2006.201.16:47:57.56#ibcon#about to read 3, iclass 24, count 0 2006.201.16:47:57.60#ibcon#read 3, iclass 24, count 0 2006.201.16:47:57.60#ibcon#about to read 4, iclass 24, count 0 2006.201.16:47:57.60#ibcon#read 4, iclass 24, count 0 2006.201.16:47:57.60#ibcon#about to read 5, iclass 24, count 0 2006.201.16:47:57.60#ibcon#read 5, iclass 24, count 0 2006.201.16:47:57.60#ibcon#about to read 6, iclass 24, count 0 2006.201.16:47:57.60#ibcon#read 6, iclass 24, count 0 2006.201.16:47:57.60#ibcon#end of sib2, iclass 24, count 0 2006.201.16:47:57.60#ibcon#*after write, iclass 24, count 0 2006.201.16:47:57.60#ibcon#*before return 0, iclass 24, count 0 2006.201.16:47:57.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:47:57.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:47:57.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:47:57.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:47:57.60$vck44/va=3,8 2006.201.16:47:57.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.16:47:57.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.16:47:57.60#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:57.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:47:57.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:47:57.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:47:57.66#ibcon#enter wrdev, iclass 26, count 2 2006.201.16:47:57.66#ibcon#first serial, iclass 26, count 2 2006.201.16:47:57.66#ibcon#enter sib2, iclass 26, count 2 2006.201.16:47:57.66#ibcon#flushed, iclass 26, count 2 2006.201.16:47:57.66#ibcon#about to write, iclass 26, count 2 2006.201.16:47:57.66#ibcon#wrote, iclass 26, count 2 2006.201.16:47:57.66#ibcon#about to read 3, iclass 26, count 2 2006.201.16:47:57.68#ibcon#read 3, iclass 26, count 2 2006.201.16:47:57.68#ibcon#about to read 4, iclass 26, count 2 2006.201.16:47:57.68#ibcon#read 4, iclass 26, count 2 2006.201.16:47:57.68#ibcon#about to read 5, iclass 26, count 2 2006.201.16:47:57.68#ibcon#read 5, iclass 26, count 2 2006.201.16:47:57.68#ibcon#about to read 6, iclass 26, count 2 2006.201.16:47:57.68#ibcon#read 6, iclass 26, count 2 2006.201.16:47:57.68#ibcon#end of sib2, iclass 26, count 2 2006.201.16:47:57.68#ibcon#*mode == 0, iclass 26, count 2 2006.201.16:47:57.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.16:47:57.68#ibcon#[25=AT03-08\r\n] 2006.201.16:47:57.68#ibcon#*before write, iclass 26, count 2 2006.201.16:47:57.68#ibcon#enter sib2, iclass 26, count 2 2006.201.16:47:57.68#ibcon#flushed, iclass 26, count 2 2006.201.16:47:57.68#ibcon#about to write, iclass 26, count 2 2006.201.16:47:57.68#ibcon#wrote, iclass 26, count 2 2006.201.16:47:57.68#ibcon#about to read 3, iclass 26, count 2 2006.201.16:47:57.71#ibcon#read 3, iclass 26, count 2 2006.201.16:47:57.71#ibcon#about to read 4, iclass 26, count 2 2006.201.16:47:57.71#ibcon#read 4, iclass 26, count 2 2006.201.16:47:57.71#ibcon#about to read 5, iclass 26, count 2 2006.201.16:47:57.71#ibcon#read 5, iclass 26, count 2 2006.201.16:47:57.71#ibcon#about to read 6, iclass 26, count 2 2006.201.16:47:57.71#ibcon#read 6, iclass 26, count 2 2006.201.16:47:57.71#ibcon#end of sib2, iclass 26, count 2 2006.201.16:47:57.71#ibcon#*after write, iclass 26, count 2 2006.201.16:47:57.71#ibcon#*before return 0, iclass 26, count 2 2006.201.16:47:57.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:47:57.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:47:57.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.16:47:57.71#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:57.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:47:57.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:47:57.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:47:57.83#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:47:57.83#ibcon#first serial, iclass 26, count 0 2006.201.16:47:57.83#ibcon#enter sib2, iclass 26, count 0 2006.201.16:47:57.83#ibcon#flushed, iclass 26, count 0 2006.201.16:47:57.83#ibcon#about to write, iclass 26, count 0 2006.201.16:47:57.83#ibcon#wrote, iclass 26, count 0 2006.201.16:47:57.83#ibcon#about to read 3, iclass 26, count 0 2006.201.16:47:57.85#ibcon#read 3, iclass 26, count 0 2006.201.16:47:57.85#ibcon#about to read 4, iclass 26, count 0 2006.201.16:47:57.85#ibcon#read 4, iclass 26, count 0 2006.201.16:47:57.85#ibcon#about to read 5, iclass 26, count 0 2006.201.16:47:57.85#ibcon#read 5, iclass 26, count 0 2006.201.16:47:57.85#ibcon#about to read 6, iclass 26, count 0 2006.201.16:47:57.85#ibcon#read 6, iclass 26, count 0 2006.201.16:47:57.85#ibcon#end of sib2, iclass 26, count 0 2006.201.16:47:57.85#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:47:57.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:47:57.85#ibcon#[25=USB\r\n] 2006.201.16:47:57.85#ibcon#*before write, iclass 26, count 0 2006.201.16:47:57.85#ibcon#enter sib2, iclass 26, count 0 2006.201.16:47:57.85#ibcon#flushed, iclass 26, count 0 2006.201.16:47:57.85#ibcon#about to write, iclass 26, count 0 2006.201.16:47:57.85#ibcon#wrote, iclass 26, count 0 2006.201.16:47:57.85#ibcon#about to read 3, iclass 26, count 0 2006.201.16:47:57.88#ibcon#read 3, iclass 26, count 0 2006.201.16:47:57.88#ibcon#about to read 4, iclass 26, count 0 2006.201.16:47:57.88#ibcon#read 4, iclass 26, count 0 2006.201.16:47:57.88#ibcon#about to read 5, iclass 26, count 0 2006.201.16:47:57.88#ibcon#read 5, iclass 26, count 0 2006.201.16:47:57.88#ibcon#about to read 6, iclass 26, count 0 2006.201.16:47:57.88#ibcon#read 6, iclass 26, count 0 2006.201.16:47:57.88#ibcon#end of sib2, iclass 26, count 0 2006.201.16:47:57.88#ibcon#*after write, iclass 26, count 0 2006.201.16:47:57.88#ibcon#*before return 0, iclass 26, count 0 2006.201.16:47:57.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:47:57.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:47:57.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:47:57.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:47:57.88$vck44/valo=4,624.99 2006.201.16:47:57.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.16:47:57.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.16:47:57.88#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:57.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:47:57.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:47:57.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:47:57.88#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:47:57.88#ibcon#first serial, iclass 28, count 0 2006.201.16:47:57.88#ibcon#enter sib2, iclass 28, count 0 2006.201.16:47:57.88#ibcon#flushed, iclass 28, count 0 2006.201.16:47:57.88#ibcon#about to write, iclass 28, count 0 2006.201.16:47:57.88#ibcon#wrote, iclass 28, count 0 2006.201.16:47:57.88#ibcon#about to read 3, iclass 28, count 0 2006.201.16:47:57.90#ibcon#read 3, iclass 28, count 0 2006.201.16:47:57.90#ibcon#about to read 4, iclass 28, count 0 2006.201.16:47:57.90#ibcon#read 4, iclass 28, count 0 2006.201.16:47:57.90#ibcon#about to read 5, iclass 28, count 0 2006.201.16:47:57.90#ibcon#read 5, iclass 28, count 0 2006.201.16:47:57.90#ibcon#about to read 6, iclass 28, count 0 2006.201.16:47:57.90#ibcon#read 6, iclass 28, count 0 2006.201.16:47:57.90#ibcon#end of sib2, iclass 28, count 0 2006.201.16:47:57.90#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:47:57.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:47:57.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:47:57.90#ibcon#*before write, iclass 28, count 0 2006.201.16:47:57.90#ibcon#enter sib2, iclass 28, count 0 2006.201.16:47:57.90#ibcon#flushed, iclass 28, count 0 2006.201.16:47:57.90#ibcon#about to write, iclass 28, count 0 2006.201.16:47:57.90#ibcon#wrote, iclass 28, count 0 2006.201.16:47:57.90#ibcon#about to read 3, iclass 28, count 0 2006.201.16:47:57.94#ibcon#read 3, iclass 28, count 0 2006.201.16:47:57.94#ibcon#about to read 4, iclass 28, count 0 2006.201.16:47:57.94#ibcon#read 4, iclass 28, count 0 2006.201.16:47:57.94#ibcon#about to read 5, iclass 28, count 0 2006.201.16:47:57.94#ibcon#read 5, iclass 28, count 0 2006.201.16:47:57.94#ibcon#about to read 6, iclass 28, count 0 2006.201.16:47:57.94#ibcon#read 6, iclass 28, count 0 2006.201.16:47:57.94#ibcon#end of sib2, iclass 28, count 0 2006.201.16:47:57.94#ibcon#*after write, iclass 28, count 0 2006.201.16:47:57.94#ibcon#*before return 0, iclass 28, count 0 2006.201.16:47:57.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:47:57.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:47:57.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:47:57.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:47:57.94$vck44/va=4,7 2006.201.16:47:57.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.16:47:57.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.16:47:57.94#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:57.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:47:58.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:47:58.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:47:58.00#ibcon#enter wrdev, iclass 30, count 2 2006.201.16:47:58.00#ibcon#first serial, iclass 30, count 2 2006.201.16:47:58.00#ibcon#enter sib2, iclass 30, count 2 2006.201.16:47:58.00#ibcon#flushed, iclass 30, count 2 2006.201.16:47:58.00#ibcon#about to write, iclass 30, count 2 2006.201.16:47:58.00#ibcon#wrote, iclass 30, count 2 2006.201.16:47:58.00#ibcon#about to read 3, iclass 30, count 2 2006.201.16:47:58.02#ibcon#read 3, iclass 30, count 2 2006.201.16:47:58.02#ibcon#about to read 4, iclass 30, count 2 2006.201.16:47:58.02#ibcon#read 4, iclass 30, count 2 2006.201.16:47:58.02#ibcon#about to read 5, iclass 30, count 2 2006.201.16:47:58.02#ibcon#read 5, iclass 30, count 2 2006.201.16:47:58.02#ibcon#about to read 6, iclass 30, count 2 2006.201.16:47:58.02#ibcon#read 6, iclass 30, count 2 2006.201.16:47:58.02#ibcon#end of sib2, iclass 30, count 2 2006.201.16:47:58.02#ibcon#*mode == 0, iclass 30, count 2 2006.201.16:47:58.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.16:47:58.02#ibcon#[25=AT04-07\r\n] 2006.201.16:47:58.02#ibcon#*before write, iclass 30, count 2 2006.201.16:47:58.02#ibcon#enter sib2, iclass 30, count 2 2006.201.16:47:58.02#ibcon#flushed, iclass 30, count 2 2006.201.16:47:58.02#ibcon#about to write, iclass 30, count 2 2006.201.16:47:58.02#ibcon#wrote, iclass 30, count 2 2006.201.16:47:58.02#ibcon#about to read 3, iclass 30, count 2 2006.201.16:47:58.05#ibcon#read 3, iclass 30, count 2 2006.201.16:47:58.05#ibcon#about to read 4, iclass 30, count 2 2006.201.16:47:58.05#ibcon#read 4, iclass 30, count 2 2006.201.16:47:58.05#ibcon#about to read 5, iclass 30, count 2 2006.201.16:47:58.05#ibcon#read 5, iclass 30, count 2 2006.201.16:47:58.05#ibcon#about to read 6, iclass 30, count 2 2006.201.16:47:58.05#ibcon#read 6, iclass 30, count 2 2006.201.16:47:58.05#ibcon#end of sib2, iclass 30, count 2 2006.201.16:47:58.05#ibcon#*after write, iclass 30, count 2 2006.201.16:47:58.05#ibcon#*before return 0, iclass 30, count 2 2006.201.16:47:58.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:47:58.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:47:58.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.16:47:58.05#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:58.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:47:58.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:47:58.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:47:58.17#ibcon#enter wrdev, iclass 30, count 0 2006.201.16:47:58.17#ibcon#first serial, iclass 30, count 0 2006.201.16:47:58.17#ibcon#enter sib2, iclass 30, count 0 2006.201.16:47:58.17#ibcon#flushed, iclass 30, count 0 2006.201.16:47:58.17#ibcon#about to write, iclass 30, count 0 2006.201.16:47:58.17#ibcon#wrote, iclass 30, count 0 2006.201.16:47:58.17#ibcon#about to read 3, iclass 30, count 0 2006.201.16:47:58.19#ibcon#read 3, iclass 30, count 0 2006.201.16:47:58.19#ibcon#about to read 4, iclass 30, count 0 2006.201.16:47:58.19#ibcon#read 4, iclass 30, count 0 2006.201.16:47:58.19#ibcon#about to read 5, iclass 30, count 0 2006.201.16:47:58.19#ibcon#read 5, iclass 30, count 0 2006.201.16:47:58.19#ibcon#about to read 6, iclass 30, count 0 2006.201.16:47:58.19#ibcon#read 6, iclass 30, count 0 2006.201.16:47:58.19#ibcon#end of sib2, iclass 30, count 0 2006.201.16:47:58.19#ibcon#*mode == 0, iclass 30, count 0 2006.201.16:47:58.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.16:47:58.19#ibcon#[25=USB\r\n] 2006.201.16:47:58.19#ibcon#*before write, iclass 30, count 0 2006.201.16:47:58.19#ibcon#enter sib2, iclass 30, count 0 2006.201.16:47:58.19#ibcon#flushed, iclass 30, count 0 2006.201.16:47:58.19#ibcon#about to write, iclass 30, count 0 2006.201.16:47:58.19#ibcon#wrote, iclass 30, count 0 2006.201.16:47:58.19#ibcon#about to read 3, iclass 30, count 0 2006.201.16:47:58.22#ibcon#read 3, iclass 30, count 0 2006.201.16:47:58.22#ibcon#about to read 4, iclass 30, count 0 2006.201.16:47:58.22#ibcon#read 4, iclass 30, count 0 2006.201.16:47:58.22#ibcon#about to read 5, iclass 30, count 0 2006.201.16:47:58.22#ibcon#read 5, iclass 30, count 0 2006.201.16:47:58.22#ibcon#about to read 6, iclass 30, count 0 2006.201.16:47:58.22#ibcon#read 6, iclass 30, count 0 2006.201.16:47:58.22#ibcon#end of sib2, iclass 30, count 0 2006.201.16:47:58.22#ibcon#*after write, iclass 30, count 0 2006.201.16:47:58.22#ibcon#*before return 0, iclass 30, count 0 2006.201.16:47:58.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:47:58.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:47:58.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.16:47:58.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.16:47:58.22$vck44/valo=5,734.99 2006.201.16:47:58.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.16:47:58.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.16:47:58.22#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:58.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:47:58.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:47:58.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:47:58.22#ibcon#enter wrdev, iclass 32, count 0 2006.201.16:47:58.22#ibcon#first serial, iclass 32, count 0 2006.201.16:47:58.22#ibcon#enter sib2, iclass 32, count 0 2006.201.16:47:58.22#ibcon#flushed, iclass 32, count 0 2006.201.16:47:58.22#ibcon#about to write, iclass 32, count 0 2006.201.16:47:58.22#ibcon#wrote, iclass 32, count 0 2006.201.16:47:58.22#ibcon#about to read 3, iclass 32, count 0 2006.201.16:47:58.24#ibcon#read 3, iclass 32, count 0 2006.201.16:47:58.24#ibcon#about to read 4, iclass 32, count 0 2006.201.16:47:58.24#ibcon#read 4, iclass 32, count 0 2006.201.16:47:58.24#ibcon#about to read 5, iclass 32, count 0 2006.201.16:47:58.24#ibcon#read 5, iclass 32, count 0 2006.201.16:47:58.24#ibcon#about to read 6, iclass 32, count 0 2006.201.16:47:58.24#ibcon#read 6, iclass 32, count 0 2006.201.16:47:58.24#ibcon#end of sib2, iclass 32, count 0 2006.201.16:47:58.24#ibcon#*mode == 0, iclass 32, count 0 2006.201.16:47:58.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.16:47:58.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:47:58.24#ibcon#*before write, iclass 32, count 0 2006.201.16:47:58.24#ibcon#enter sib2, iclass 32, count 0 2006.201.16:47:58.24#ibcon#flushed, iclass 32, count 0 2006.201.16:47:58.24#ibcon#about to write, iclass 32, count 0 2006.201.16:47:58.24#ibcon#wrote, iclass 32, count 0 2006.201.16:47:58.24#ibcon#about to read 3, iclass 32, count 0 2006.201.16:47:58.28#ibcon#read 3, iclass 32, count 0 2006.201.16:47:58.28#ibcon#about to read 4, iclass 32, count 0 2006.201.16:47:58.28#ibcon#read 4, iclass 32, count 0 2006.201.16:47:58.28#ibcon#about to read 5, iclass 32, count 0 2006.201.16:47:58.28#ibcon#read 5, iclass 32, count 0 2006.201.16:47:58.28#ibcon#about to read 6, iclass 32, count 0 2006.201.16:47:58.28#ibcon#read 6, iclass 32, count 0 2006.201.16:47:58.28#ibcon#end of sib2, iclass 32, count 0 2006.201.16:47:58.28#ibcon#*after write, iclass 32, count 0 2006.201.16:47:58.28#ibcon#*before return 0, iclass 32, count 0 2006.201.16:47:58.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:47:58.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:47:58.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.16:47:58.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.16:47:58.28$vck44/va=5,4 2006.201.16:47:58.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.16:47:58.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.16:47:58.28#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:58.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:47:58.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:47:58.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:47:58.34#ibcon#enter wrdev, iclass 34, count 2 2006.201.16:47:58.34#ibcon#first serial, iclass 34, count 2 2006.201.16:47:58.34#ibcon#enter sib2, iclass 34, count 2 2006.201.16:47:58.34#ibcon#flushed, iclass 34, count 2 2006.201.16:47:58.34#ibcon#about to write, iclass 34, count 2 2006.201.16:47:58.34#ibcon#wrote, iclass 34, count 2 2006.201.16:47:58.34#ibcon#about to read 3, iclass 34, count 2 2006.201.16:47:58.36#ibcon#read 3, iclass 34, count 2 2006.201.16:47:58.36#ibcon#about to read 4, iclass 34, count 2 2006.201.16:47:58.36#ibcon#read 4, iclass 34, count 2 2006.201.16:47:58.36#ibcon#about to read 5, iclass 34, count 2 2006.201.16:47:58.36#ibcon#read 5, iclass 34, count 2 2006.201.16:47:58.36#ibcon#about to read 6, iclass 34, count 2 2006.201.16:47:58.36#ibcon#read 6, iclass 34, count 2 2006.201.16:47:58.36#ibcon#end of sib2, iclass 34, count 2 2006.201.16:47:58.36#ibcon#*mode == 0, iclass 34, count 2 2006.201.16:47:58.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.16:47:58.36#ibcon#[25=AT05-04\r\n] 2006.201.16:47:58.36#ibcon#*before write, iclass 34, count 2 2006.201.16:47:58.36#ibcon#enter sib2, iclass 34, count 2 2006.201.16:47:58.36#ibcon#flushed, iclass 34, count 2 2006.201.16:47:58.36#ibcon#about to write, iclass 34, count 2 2006.201.16:47:58.36#ibcon#wrote, iclass 34, count 2 2006.201.16:47:58.36#ibcon#about to read 3, iclass 34, count 2 2006.201.16:47:58.39#ibcon#read 3, iclass 34, count 2 2006.201.16:47:58.39#ibcon#about to read 4, iclass 34, count 2 2006.201.16:47:58.39#ibcon#read 4, iclass 34, count 2 2006.201.16:47:58.39#ibcon#about to read 5, iclass 34, count 2 2006.201.16:47:58.39#ibcon#read 5, iclass 34, count 2 2006.201.16:47:58.39#ibcon#about to read 6, iclass 34, count 2 2006.201.16:47:58.39#ibcon#read 6, iclass 34, count 2 2006.201.16:47:58.39#ibcon#end of sib2, iclass 34, count 2 2006.201.16:47:58.39#ibcon#*after write, iclass 34, count 2 2006.201.16:47:58.39#ibcon#*before return 0, iclass 34, count 2 2006.201.16:47:58.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:47:58.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:47:58.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.16:47:58.39#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:58.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:47:58.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:47:58.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:47:58.51#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:47:58.51#ibcon#first serial, iclass 34, count 0 2006.201.16:47:58.51#ibcon#enter sib2, iclass 34, count 0 2006.201.16:47:58.51#ibcon#flushed, iclass 34, count 0 2006.201.16:47:58.51#ibcon#about to write, iclass 34, count 0 2006.201.16:47:58.51#ibcon#wrote, iclass 34, count 0 2006.201.16:47:58.51#ibcon#about to read 3, iclass 34, count 0 2006.201.16:47:58.53#ibcon#read 3, iclass 34, count 0 2006.201.16:47:58.53#ibcon#about to read 4, iclass 34, count 0 2006.201.16:47:58.53#ibcon#read 4, iclass 34, count 0 2006.201.16:47:58.53#ibcon#about to read 5, iclass 34, count 0 2006.201.16:47:58.53#ibcon#read 5, iclass 34, count 0 2006.201.16:47:58.53#ibcon#about to read 6, iclass 34, count 0 2006.201.16:47:58.53#ibcon#read 6, iclass 34, count 0 2006.201.16:47:58.53#ibcon#end of sib2, iclass 34, count 0 2006.201.16:47:58.53#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:47:58.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:47:58.53#ibcon#[25=USB\r\n] 2006.201.16:47:58.53#ibcon#*before write, iclass 34, count 0 2006.201.16:47:58.53#ibcon#enter sib2, iclass 34, count 0 2006.201.16:47:58.53#ibcon#flushed, iclass 34, count 0 2006.201.16:47:58.53#ibcon#about to write, iclass 34, count 0 2006.201.16:47:58.53#ibcon#wrote, iclass 34, count 0 2006.201.16:47:58.53#ibcon#about to read 3, iclass 34, count 0 2006.201.16:47:58.56#ibcon#read 3, iclass 34, count 0 2006.201.16:47:58.56#ibcon#about to read 4, iclass 34, count 0 2006.201.16:47:58.56#ibcon#read 4, iclass 34, count 0 2006.201.16:47:58.56#ibcon#about to read 5, iclass 34, count 0 2006.201.16:47:58.56#ibcon#read 5, iclass 34, count 0 2006.201.16:47:58.56#ibcon#about to read 6, iclass 34, count 0 2006.201.16:47:58.56#ibcon#read 6, iclass 34, count 0 2006.201.16:47:58.56#ibcon#end of sib2, iclass 34, count 0 2006.201.16:47:58.56#ibcon#*after write, iclass 34, count 0 2006.201.16:47:58.56#ibcon#*before return 0, iclass 34, count 0 2006.201.16:47:58.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:47:58.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:47:58.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:47:58.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:47:58.56$vck44/valo=6,814.99 2006.201.16:47:58.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.16:47:58.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.16:47:58.56#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:58.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:47:58.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:47:58.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:47:58.56#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:47:58.56#ibcon#first serial, iclass 36, count 0 2006.201.16:47:58.56#ibcon#enter sib2, iclass 36, count 0 2006.201.16:47:58.56#ibcon#flushed, iclass 36, count 0 2006.201.16:47:58.56#ibcon#about to write, iclass 36, count 0 2006.201.16:47:58.56#ibcon#wrote, iclass 36, count 0 2006.201.16:47:58.56#ibcon#about to read 3, iclass 36, count 0 2006.201.16:47:58.58#ibcon#read 3, iclass 36, count 0 2006.201.16:47:58.58#ibcon#about to read 4, iclass 36, count 0 2006.201.16:47:58.58#ibcon#read 4, iclass 36, count 0 2006.201.16:47:58.58#ibcon#about to read 5, iclass 36, count 0 2006.201.16:47:58.58#ibcon#read 5, iclass 36, count 0 2006.201.16:47:58.58#ibcon#about to read 6, iclass 36, count 0 2006.201.16:47:58.58#ibcon#read 6, iclass 36, count 0 2006.201.16:47:58.58#ibcon#end of sib2, iclass 36, count 0 2006.201.16:47:58.58#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:47:58.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:47:58.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:47:58.58#ibcon#*before write, iclass 36, count 0 2006.201.16:47:58.58#ibcon#enter sib2, iclass 36, count 0 2006.201.16:47:58.58#ibcon#flushed, iclass 36, count 0 2006.201.16:47:58.58#ibcon#about to write, iclass 36, count 0 2006.201.16:47:58.58#ibcon#wrote, iclass 36, count 0 2006.201.16:47:58.58#ibcon#about to read 3, iclass 36, count 0 2006.201.16:47:58.63#ibcon#read 3, iclass 36, count 0 2006.201.16:47:58.63#ibcon#about to read 4, iclass 36, count 0 2006.201.16:47:58.63#ibcon#read 4, iclass 36, count 0 2006.201.16:47:58.63#ibcon#about to read 5, iclass 36, count 0 2006.201.16:47:58.63#ibcon#read 5, iclass 36, count 0 2006.201.16:47:58.63#ibcon#about to read 6, iclass 36, count 0 2006.201.16:47:58.63#ibcon#read 6, iclass 36, count 0 2006.201.16:47:58.63#ibcon#end of sib2, iclass 36, count 0 2006.201.16:47:58.63#ibcon#*after write, iclass 36, count 0 2006.201.16:47:58.63#ibcon#*before return 0, iclass 36, count 0 2006.201.16:47:58.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:47:58.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:47:58.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:47:58.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:47:58.63$vck44/va=6,5 2006.201.16:47:58.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.16:47:58.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.16:47:58.63#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:58.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:47:58.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:47:58.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:47:58.68#ibcon#enter wrdev, iclass 38, count 2 2006.201.16:47:58.68#ibcon#first serial, iclass 38, count 2 2006.201.16:47:58.68#ibcon#enter sib2, iclass 38, count 2 2006.201.16:47:58.68#ibcon#flushed, iclass 38, count 2 2006.201.16:47:58.68#ibcon#about to write, iclass 38, count 2 2006.201.16:47:58.68#ibcon#wrote, iclass 38, count 2 2006.201.16:47:58.68#ibcon#about to read 3, iclass 38, count 2 2006.201.16:47:58.70#ibcon#read 3, iclass 38, count 2 2006.201.16:47:58.70#ibcon#about to read 4, iclass 38, count 2 2006.201.16:47:58.70#ibcon#read 4, iclass 38, count 2 2006.201.16:47:58.70#ibcon#about to read 5, iclass 38, count 2 2006.201.16:47:58.70#ibcon#read 5, iclass 38, count 2 2006.201.16:47:58.70#ibcon#about to read 6, iclass 38, count 2 2006.201.16:47:58.70#ibcon#read 6, iclass 38, count 2 2006.201.16:47:58.70#ibcon#end of sib2, iclass 38, count 2 2006.201.16:47:58.70#ibcon#*mode == 0, iclass 38, count 2 2006.201.16:47:58.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.16:47:58.70#ibcon#[25=AT06-05\r\n] 2006.201.16:47:58.70#ibcon#*before write, iclass 38, count 2 2006.201.16:47:58.70#ibcon#enter sib2, iclass 38, count 2 2006.201.16:47:58.70#ibcon#flushed, iclass 38, count 2 2006.201.16:47:58.70#ibcon#about to write, iclass 38, count 2 2006.201.16:47:58.70#ibcon#wrote, iclass 38, count 2 2006.201.16:47:58.70#ibcon#about to read 3, iclass 38, count 2 2006.201.16:47:58.73#ibcon#read 3, iclass 38, count 2 2006.201.16:47:58.73#ibcon#about to read 4, iclass 38, count 2 2006.201.16:47:58.73#ibcon#read 4, iclass 38, count 2 2006.201.16:47:58.73#ibcon#about to read 5, iclass 38, count 2 2006.201.16:47:58.73#ibcon#read 5, iclass 38, count 2 2006.201.16:47:58.73#ibcon#about to read 6, iclass 38, count 2 2006.201.16:47:58.73#ibcon#read 6, iclass 38, count 2 2006.201.16:47:58.73#ibcon#end of sib2, iclass 38, count 2 2006.201.16:47:58.73#ibcon#*after write, iclass 38, count 2 2006.201.16:47:58.73#ibcon#*before return 0, iclass 38, count 2 2006.201.16:47:58.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:47:58.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:47:58.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.16:47:58.73#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:58.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:47:58.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:47:58.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:47:58.85#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:47:58.85#ibcon#first serial, iclass 38, count 0 2006.201.16:47:58.85#ibcon#enter sib2, iclass 38, count 0 2006.201.16:47:58.85#ibcon#flushed, iclass 38, count 0 2006.201.16:47:58.85#ibcon#about to write, iclass 38, count 0 2006.201.16:47:58.85#ibcon#wrote, iclass 38, count 0 2006.201.16:47:58.85#ibcon#about to read 3, iclass 38, count 0 2006.201.16:47:58.87#ibcon#read 3, iclass 38, count 0 2006.201.16:47:58.87#ibcon#about to read 4, iclass 38, count 0 2006.201.16:47:58.87#ibcon#read 4, iclass 38, count 0 2006.201.16:47:58.87#ibcon#about to read 5, iclass 38, count 0 2006.201.16:47:58.87#ibcon#read 5, iclass 38, count 0 2006.201.16:47:58.87#ibcon#about to read 6, iclass 38, count 0 2006.201.16:47:58.87#ibcon#read 6, iclass 38, count 0 2006.201.16:47:58.87#ibcon#end of sib2, iclass 38, count 0 2006.201.16:47:58.87#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:47:58.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:47:58.87#ibcon#[25=USB\r\n] 2006.201.16:47:58.87#ibcon#*before write, iclass 38, count 0 2006.201.16:47:58.87#ibcon#enter sib2, iclass 38, count 0 2006.201.16:47:58.87#ibcon#flushed, iclass 38, count 0 2006.201.16:47:58.87#ibcon#about to write, iclass 38, count 0 2006.201.16:47:58.87#ibcon#wrote, iclass 38, count 0 2006.201.16:47:58.87#ibcon#about to read 3, iclass 38, count 0 2006.201.16:47:58.90#ibcon#read 3, iclass 38, count 0 2006.201.16:47:58.90#ibcon#about to read 4, iclass 38, count 0 2006.201.16:47:58.90#ibcon#read 4, iclass 38, count 0 2006.201.16:47:58.90#ibcon#about to read 5, iclass 38, count 0 2006.201.16:47:58.90#ibcon#read 5, iclass 38, count 0 2006.201.16:47:58.90#ibcon#about to read 6, iclass 38, count 0 2006.201.16:47:58.90#ibcon#read 6, iclass 38, count 0 2006.201.16:47:58.90#ibcon#end of sib2, iclass 38, count 0 2006.201.16:47:58.90#ibcon#*after write, iclass 38, count 0 2006.201.16:47:58.90#ibcon#*before return 0, iclass 38, count 0 2006.201.16:47:58.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:47:58.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:47:58.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:47:58.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:47:58.90$vck44/valo=7,864.99 2006.201.16:47:58.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.16:47:58.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.16:47:58.90#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:58.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:47:58.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:47:58.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:47:58.90#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:47:58.90#ibcon#first serial, iclass 40, count 0 2006.201.16:47:58.90#ibcon#enter sib2, iclass 40, count 0 2006.201.16:47:58.90#ibcon#flushed, iclass 40, count 0 2006.201.16:47:58.90#ibcon#about to write, iclass 40, count 0 2006.201.16:47:58.90#ibcon#wrote, iclass 40, count 0 2006.201.16:47:58.90#ibcon#about to read 3, iclass 40, count 0 2006.201.16:47:58.92#ibcon#read 3, iclass 40, count 0 2006.201.16:47:58.92#ibcon#about to read 4, iclass 40, count 0 2006.201.16:47:58.92#ibcon#read 4, iclass 40, count 0 2006.201.16:47:58.92#ibcon#about to read 5, iclass 40, count 0 2006.201.16:47:58.92#ibcon#read 5, iclass 40, count 0 2006.201.16:47:58.92#ibcon#about to read 6, iclass 40, count 0 2006.201.16:47:58.92#ibcon#read 6, iclass 40, count 0 2006.201.16:47:58.92#ibcon#end of sib2, iclass 40, count 0 2006.201.16:47:58.92#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:47:58.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:47:58.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:47:58.92#ibcon#*before write, iclass 40, count 0 2006.201.16:47:58.92#ibcon#enter sib2, iclass 40, count 0 2006.201.16:47:58.92#ibcon#flushed, iclass 40, count 0 2006.201.16:47:58.92#ibcon#about to write, iclass 40, count 0 2006.201.16:47:58.92#ibcon#wrote, iclass 40, count 0 2006.201.16:47:58.92#ibcon#about to read 3, iclass 40, count 0 2006.201.16:47:58.96#ibcon#read 3, iclass 40, count 0 2006.201.16:47:58.96#ibcon#about to read 4, iclass 40, count 0 2006.201.16:47:58.96#ibcon#read 4, iclass 40, count 0 2006.201.16:47:58.96#ibcon#about to read 5, iclass 40, count 0 2006.201.16:47:58.96#ibcon#read 5, iclass 40, count 0 2006.201.16:47:58.96#ibcon#about to read 6, iclass 40, count 0 2006.201.16:47:58.96#ibcon#read 6, iclass 40, count 0 2006.201.16:47:58.96#ibcon#end of sib2, iclass 40, count 0 2006.201.16:47:58.96#ibcon#*after write, iclass 40, count 0 2006.201.16:47:58.96#ibcon#*before return 0, iclass 40, count 0 2006.201.16:47:58.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:47:58.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:47:58.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:47:58.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:47:58.96$vck44/va=7,5 2006.201.16:47:58.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.16:47:58.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.16:47:58.96#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:58.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:47:59.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:47:59.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:47:59.02#ibcon#enter wrdev, iclass 4, count 2 2006.201.16:47:59.02#ibcon#first serial, iclass 4, count 2 2006.201.16:47:59.02#ibcon#enter sib2, iclass 4, count 2 2006.201.16:47:59.02#ibcon#flushed, iclass 4, count 2 2006.201.16:47:59.02#ibcon#about to write, iclass 4, count 2 2006.201.16:47:59.02#ibcon#wrote, iclass 4, count 2 2006.201.16:47:59.02#ibcon#about to read 3, iclass 4, count 2 2006.201.16:47:59.04#ibcon#read 3, iclass 4, count 2 2006.201.16:47:59.04#ibcon#about to read 4, iclass 4, count 2 2006.201.16:47:59.04#ibcon#read 4, iclass 4, count 2 2006.201.16:47:59.04#ibcon#about to read 5, iclass 4, count 2 2006.201.16:47:59.04#ibcon#read 5, iclass 4, count 2 2006.201.16:47:59.04#ibcon#about to read 6, iclass 4, count 2 2006.201.16:47:59.04#ibcon#read 6, iclass 4, count 2 2006.201.16:47:59.04#ibcon#end of sib2, iclass 4, count 2 2006.201.16:47:59.04#ibcon#*mode == 0, iclass 4, count 2 2006.201.16:47:59.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.16:47:59.04#ibcon#[25=AT07-05\r\n] 2006.201.16:47:59.04#ibcon#*before write, iclass 4, count 2 2006.201.16:47:59.04#ibcon#enter sib2, iclass 4, count 2 2006.201.16:47:59.04#ibcon#flushed, iclass 4, count 2 2006.201.16:47:59.04#ibcon#about to write, iclass 4, count 2 2006.201.16:47:59.04#ibcon#wrote, iclass 4, count 2 2006.201.16:47:59.04#ibcon#about to read 3, iclass 4, count 2 2006.201.16:47:59.07#ibcon#read 3, iclass 4, count 2 2006.201.16:47:59.07#ibcon#about to read 4, iclass 4, count 2 2006.201.16:47:59.07#ibcon#read 4, iclass 4, count 2 2006.201.16:47:59.07#ibcon#about to read 5, iclass 4, count 2 2006.201.16:47:59.07#ibcon#read 5, iclass 4, count 2 2006.201.16:47:59.07#ibcon#about to read 6, iclass 4, count 2 2006.201.16:47:59.07#ibcon#read 6, iclass 4, count 2 2006.201.16:47:59.07#ibcon#end of sib2, iclass 4, count 2 2006.201.16:47:59.07#ibcon#*after write, iclass 4, count 2 2006.201.16:47:59.07#ibcon#*before return 0, iclass 4, count 2 2006.201.16:47:59.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:47:59.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:47:59.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.16:47:59.07#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:59.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:47:59.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:47:59.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:47:59.19#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:47:59.19#ibcon#first serial, iclass 4, count 0 2006.201.16:47:59.19#ibcon#enter sib2, iclass 4, count 0 2006.201.16:47:59.19#ibcon#flushed, iclass 4, count 0 2006.201.16:47:59.19#ibcon#about to write, iclass 4, count 0 2006.201.16:47:59.19#ibcon#wrote, iclass 4, count 0 2006.201.16:47:59.19#ibcon#about to read 3, iclass 4, count 0 2006.201.16:47:59.21#ibcon#read 3, iclass 4, count 0 2006.201.16:47:59.21#ibcon#about to read 4, iclass 4, count 0 2006.201.16:47:59.21#ibcon#read 4, iclass 4, count 0 2006.201.16:47:59.21#ibcon#about to read 5, iclass 4, count 0 2006.201.16:47:59.21#ibcon#read 5, iclass 4, count 0 2006.201.16:47:59.21#ibcon#about to read 6, iclass 4, count 0 2006.201.16:47:59.21#ibcon#read 6, iclass 4, count 0 2006.201.16:47:59.21#ibcon#end of sib2, iclass 4, count 0 2006.201.16:47:59.21#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:47:59.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:47:59.21#ibcon#[25=USB\r\n] 2006.201.16:47:59.21#ibcon#*before write, iclass 4, count 0 2006.201.16:47:59.21#ibcon#enter sib2, iclass 4, count 0 2006.201.16:47:59.21#ibcon#flushed, iclass 4, count 0 2006.201.16:47:59.21#ibcon#about to write, iclass 4, count 0 2006.201.16:47:59.21#ibcon#wrote, iclass 4, count 0 2006.201.16:47:59.21#ibcon#about to read 3, iclass 4, count 0 2006.201.16:47:59.24#ibcon#read 3, iclass 4, count 0 2006.201.16:47:59.24#ibcon#about to read 4, iclass 4, count 0 2006.201.16:47:59.24#ibcon#read 4, iclass 4, count 0 2006.201.16:47:59.24#ibcon#about to read 5, iclass 4, count 0 2006.201.16:47:59.24#ibcon#read 5, iclass 4, count 0 2006.201.16:47:59.24#ibcon#about to read 6, iclass 4, count 0 2006.201.16:47:59.24#ibcon#read 6, iclass 4, count 0 2006.201.16:47:59.24#ibcon#end of sib2, iclass 4, count 0 2006.201.16:47:59.24#ibcon#*after write, iclass 4, count 0 2006.201.16:47:59.24#ibcon#*before return 0, iclass 4, count 0 2006.201.16:47:59.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:47:59.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:47:59.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:47:59.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:47:59.24$vck44/valo=8,884.99 2006.201.16:47:59.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.16:47:59.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.16:47:59.24#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:59.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:47:59.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:47:59.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:47:59.24#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:47:59.24#ibcon#first serial, iclass 6, count 0 2006.201.16:47:59.24#ibcon#enter sib2, iclass 6, count 0 2006.201.16:47:59.24#ibcon#flushed, iclass 6, count 0 2006.201.16:47:59.24#ibcon#about to write, iclass 6, count 0 2006.201.16:47:59.24#ibcon#wrote, iclass 6, count 0 2006.201.16:47:59.24#ibcon#about to read 3, iclass 6, count 0 2006.201.16:47:59.26#ibcon#read 3, iclass 6, count 0 2006.201.16:47:59.26#ibcon#about to read 4, iclass 6, count 0 2006.201.16:47:59.26#ibcon#read 4, iclass 6, count 0 2006.201.16:47:59.26#ibcon#about to read 5, iclass 6, count 0 2006.201.16:47:59.26#ibcon#read 5, iclass 6, count 0 2006.201.16:47:59.26#ibcon#about to read 6, iclass 6, count 0 2006.201.16:47:59.26#ibcon#read 6, iclass 6, count 0 2006.201.16:47:59.26#ibcon#end of sib2, iclass 6, count 0 2006.201.16:47:59.26#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:47:59.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:47:59.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:47:59.26#ibcon#*before write, iclass 6, count 0 2006.201.16:47:59.26#ibcon#enter sib2, iclass 6, count 0 2006.201.16:47:59.26#ibcon#flushed, iclass 6, count 0 2006.201.16:47:59.26#ibcon#about to write, iclass 6, count 0 2006.201.16:47:59.26#ibcon#wrote, iclass 6, count 0 2006.201.16:47:59.26#ibcon#about to read 3, iclass 6, count 0 2006.201.16:47:59.30#ibcon#read 3, iclass 6, count 0 2006.201.16:47:59.30#ibcon#about to read 4, iclass 6, count 0 2006.201.16:47:59.30#ibcon#read 4, iclass 6, count 0 2006.201.16:47:59.30#ibcon#about to read 5, iclass 6, count 0 2006.201.16:47:59.30#ibcon#read 5, iclass 6, count 0 2006.201.16:47:59.30#ibcon#about to read 6, iclass 6, count 0 2006.201.16:47:59.30#ibcon#read 6, iclass 6, count 0 2006.201.16:47:59.30#ibcon#end of sib2, iclass 6, count 0 2006.201.16:47:59.30#ibcon#*after write, iclass 6, count 0 2006.201.16:47:59.30#ibcon#*before return 0, iclass 6, count 0 2006.201.16:47:59.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:47:59.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:47:59.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:47:59.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:47:59.30$vck44/va=8,4 2006.201.16:47:59.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.16:47:59.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.16:47:59.30#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:59.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:47:59.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:47:59.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:47:59.36#ibcon#enter wrdev, iclass 10, count 2 2006.201.16:47:59.36#ibcon#first serial, iclass 10, count 2 2006.201.16:47:59.36#ibcon#enter sib2, iclass 10, count 2 2006.201.16:47:59.36#ibcon#flushed, iclass 10, count 2 2006.201.16:47:59.36#ibcon#about to write, iclass 10, count 2 2006.201.16:47:59.36#ibcon#wrote, iclass 10, count 2 2006.201.16:47:59.36#ibcon#about to read 3, iclass 10, count 2 2006.201.16:47:59.38#ibcon#read 3, iclass 10, count 2 2006.201.16:47:59.38#ibcon#about to read 4, iclass 10, count 2 2006.201.16:47:59.38#ibcon#read 4, iclass 10, count 2 2006.201.16:47:59.38#ibcon#about to read 5, iclass 10, count 2 2006.201.16:47:59.38#ibcon#read 5, iclass 10, count 2 2006.201.16:47:59.38#ibcon#about to read 6, iclass 10, count 2 2006.201.16:47:59.38#ibcon#read 6, iclass 10, count 2 2006.201.16:47:59.38#ibcon#end of sib2, iclass 10, count 2 2006.201.16:47:59.38#ibcon#*mode == 0, iclass 10, count 2 2006.201.16:47:59.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.16:47:59.38#ibcon#[25=AT08-04\r\n] 2006.201.16:47:59.38#ibcon#*before write, iclass 10, count 2 2006.201.16:47:59.38#ibcon#enter sib2, iclass 10, count 2 2006.201.16:47:59.38#ibcon#flushed, iclass 10, count 2 2006.201.16:47:59.38#ibcon#about to write, iclass 10, count 2 2006.201.16:47:59.38#ibcon#wrote, iclass 10, count 2 2006.201.16:47:59.38#ibcon#about to read 3, iclass 10, count 2 2006.201.16:47:59.41#ibcon#read 3, iclass 10, count 2 2006.201.16:47:59.41#ibcon#about to read 4, iclass 10, count 2 2006.201.16:47:59.41#ibcon#read 4, iclass 10, count 2 2006.201.16:47:59.41#ibcon#about to read 5, iclass 10, count 2 2006.201.16:47:59.41#ibcon#read 5, iclass 10, count 2 2006.201.16:47:59.41#ibcon#about to read 6, iclass 10, count 2 2006.201.16:47:59.41#ibcon#read 6, iclass 10, count 2 2006.201.16:47:59.41#ibcon#end of sib2, iclass 10, count 2 2006.201.16:47:59.41#ibcon#*after write, iclass 10, count 2 2006.201.16:47:59.41#ibcon#*before return 0, iclass 10, count 2 2006.201.16:47:59.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:47:59.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.16:47:59.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.16:47:59.41#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:59.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:47:59.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:47:59.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:47:59.53#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:47:59.53#ibcon#first serial, iclass 10, count 0 2006.201.16:47:59.53#ibcon#enter sib2, iclass 10, count 0 2006.201.16:47:59.53#ibcon#flushed, iclass 10, count 0 2006.201.16:47:59.53#ibcon#about to write, iclass 10, count 0 2006.201.16:47:59.53#ibcon#wrote, iclass 10, count 0 2006.201.16:47:59.53#ibcon#about to read 3, iclass 10, count 0 2006.201.16:47:59.55#ibcon#read 3, iclass 10, count 0 2006.201.16:47:59.55#ibcon#about to read 4, iclass 10, count 0 2006.201.16:47:59.55#ibcon#read 4, iclass 10, count 0 2006.201.16:47:59.55#ibcon#about to read 5, iclass 10, count 0 2006.201.16:47:59.55#ibcon#read 5, iclass 10, count 0 2006.201.16:47:59.55#ibcon#about to read 6, iclass 10, count 0 2006.201.16:47:59.55#ibcon#read 6, iclass 10, count 0 2006.201.16:47:59.55#ibcon#end of sib2, iclass 10, count 0 2006.201.16:47:59.55#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:47:59.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:47:59.55#ibcon#[25=USB\r\n] 2006.201.16:47:59.55#ibcon#*before write, iclass 10, count 0 2006.201.16:47:59.55#ibcon#enter sib2, iclass 10, count 0 2006.201.16:47:59.55#ibcon#flushed, iclass 10, count 0 2006.201.16:47:59.55#ibcon#about to write, iclass 10, count 0 2006.201.16:47:59.55#ibcon#wrote, iclass 10, count 0 2006.201.16:47:59.55#ibcon#about to read 3, iclass 10, count 0 2006.201.16:47:59.58#ibcon#read 3, iclass 10, count 0 2006.201.16:47:59.58#ibcon#about to read 4, iclass 10, count 0 2006.201.16:47:59.58#ibcon#read 4, iclass 10, count 0 2006.201.16:47:59.58#ibcon#about to read 5, iclass 10, count 0 2006.201.16:47:59.58#ibcon#read 5, iclass 10, count 0 2006.201.16:47:59.58#ibcon#about to read 6, iclass 10, count 0 2006.201.16:47:59.58#ibcon#read 6, iclass 10, count 0 2006.201.16:47:59.58#ibcon#end of sib2, iclass 10, count 0 2006.201.16:47:59.58#ibcon#*after write, iclass 10, count 0 2006.201.16:47:59.58#ibcon#*before return 0, iclass 10, count 0 2006.201.16:47:59.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:47:59.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.16:47:59.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:47:59.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:47:59.58$vck44/vblo=1,629.99 2006.201.16:47:59.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.16:47:59.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.16:47:59.58#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:59.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:47:59.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:47:59.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:47:59.58#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:47:59.58#ibcon#first serial, iclass 12, count 0 2006.201.16:47:59.58#ibcon#enter sib2, iclass 12, count 0 2006.201.16:47:59.58#ibcon#flushed, iclass 12, count 0 2006.201.16:47:59.58#ibcon#about to write, iclass 12, count 0 2006.201.16:47:59.58#ibcon#wrote, iclass 12, count 0 2006.201.16:47:59.58#ibcon#about to read 3, iclass 12, count 0 2006.201.16:47:59.60#ibcon#read 3, iclass 12, count 0 2006.201.16:47:59.60#ibcon#about to read 4, iclass 12, count 0 2006.201.16:47:59.60#ibcon#read 4, iclass 12, count 0 2006.201.16:47:59.60#ibcon#about to read 5, iclass 12, count 0 2006.201.16:47:59.60#ibcon#read 5, iclass 12, count 0 2006.201.16:47:59.60#ibcon#about to read 6, iclass 12, count 0 2006.201.16:47:59.60#ibcon#read 6, iclass 12, count 0 2006.201.16:47:59.60#ibcon#end of sib2, iclass 12, count 0 2006.201.16:47:59.60#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:47:59.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:47:59.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:47:59.60#ibcon#*before write, iclass 12, count 0 2006.201.16:47:59.60#ibcon#enter sib2, iclass 12, count 0 2006.201.16:47:59.60#ibcon#flushed, iclass 12, count 0 2006.201.16:47:59.60#ibcon#about to write, iclass 12, count 0 2006.201.16:47:59.60#ibcon#wrote, iclass 12, count 0 2006.201.16:47:59.60#ibcon#about to read 3, iclass 12, count 0 2006.201.16:47:59.65#ibcon#read 3, iclass 12, count 0 2006.201.16:47:59.65#ibcon#about to read 4, iclass 12, count 0 2006.201.16:47:59.65#ibcon#read 4, iclass 12, count 0 2006.201.16:47:59.65#ibcon#about to read 5, iclass 12, count 0 2006.201.16:47:59.65#ibcon#read 5, iclass 12, count 0 2006.201.16:47:59.65#ibcon#about to read 6, iclass 12, count 0 2006.201.16:47:59.65#ibcon#read 6, iclass 12, count 0 2006.201.16:47:59.65#ibcon#end of sib2, iclass 12, count 0 2006.201.16:47:59.65#ibcon#*after write, iclass 12, count 0 2006.201.16:47:59.65#ibcon#*before return 0, iclass 12, count 0 2006.201.16:47:59.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:47:59.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:47:59.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:47:59.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:47:59.65$vck44/vb=1,4 2006.201.16:47:59.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.16:47:59.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.16:47:59.65#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:59.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:47:59.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:47:59.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:47:59.65#ibcon#enter wrdev, iclass 14, count 2 2006.201.16:47:59.65#ibcon#first serial, iclass 14, count 2 2006.201.16:47:59.65#ibcon#enter sib2, iclass 14, count 2 2006.201.16:47:59.65#ibcon#flushed, iclass 14, count 2 2006.201.16:47:59.65#ibcon#about to write, iclass 14, count 2 2006.201.16:47:59.65#ibcon#wrote, iclass 14, count 2 2006.201.16:47:59.65#ibcon#about to read 3, iclass 14, count 2 2006.201.16:47:59.67#ibcon#read 3, iclass 14, count 2 2006.201.16:47:59.67#ibcon#about to read 4, iclass 14, count 2 2006.201.16:47:59.67#ibcon#read 4, iclass 14, count 2 2006.201.16:47:59.67#ibcon#about to read 5, iclass 14, count 2 2006.201.16:47:59.67#ibcon#read 5, iclass 14, count 2 2006.201.16:47:59.67#ibcon#about to read 6, iclass 14, count 2 2006.201.16:47:59.67#ibcon#read 6, iclass 14, count 2 2006.201.16:47:59.67#ibcon#end of sib2, iclass 14, count 2 2006.201.16:47:59.67#ibcon#*mode == 0, iclass 14, count 2 2006.201.16:47:59.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.16:47:59.67#ibcon#[27=AT01-04\r\n] 2006.201.16:47:59.67#ibcon#*before write, iclass 14, count 2 2006.201.16:47:59.67#ibcon#enter sib2, iclass 14, count 2 2006.201.16:47:59.67#ibcon#flushed, iclass 14, count 2 2006.201.16:47:59.67#ibcon#about to write, iclass 14, count 2 2006.201.16:47:59.67#ibcon#wrote, iclass 14, count 2 2006.201.16:47:59.67#ibcon#about to read 3, iclass 14, count 2 2006.201.16:47:59.70#ibcon#read 3, iclass 14, count 2 2006.201.16:47:59.70#ibcon#about to read 4, iclass 14, count 2 2006.201.16:47:59.70#ibcon#read 4, iclass 14, count 2 2006.201.16:47:59.70#ibcon#about to read 5, iclass 14, count 2 2006.201.16:47:59.70#ibcon#read 5, iclass 14, count 2 2006.201.16:47:59.70#ibcon#about to read 6, iclass 14, count 2 2006.201.16:47:59.70#ibcon#read 6, iclass 14, count 2 2006.201.16:47:59.70#ibcon#end of sib2, iclass 14, count 2 2006.201.16:47:59.70#ibcon#*after write, iclass 14, count 2 2006.201.16:47:59.70#ibcon#*before return 0, iclass 14, count 2 2006.201.16:47:59.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:47:59.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.16:47:59.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.16:47:59.70#ibcon#ireg 7 cls_cnt 0 2006.201.16:47:59.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:47:59.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:47:59.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:47:59.82#ibcon#enter wrdev, iclass 14, count 0 2006.201.16:47:59.82#ibcon#first serial, iclass 14, count 0 2006.201.16:47:59.82#ibcon#enter sib2, iclass 14, count 0 2006.201.16:47:59.82#ibcon#flushed, iclass 14, count 0 2006.201.16:47:59.82#ibcon#about to write, iclass 14, count 0 2006.201.16:47:59.82#ibcon#wrote, iclass 14, count 0 2006.201.16:47:59.82#ibcon#about to read 3, iclass 14, count 0 2006.201.16:47:59.84#ibcon#read 3, iclass 14, count 0 2006.201.16:47:59.84#ibcon#about to read 4, iclass 14, count 0 2006.201.16:47:59.84#ibcon#read 4, iclass 14, count 0 2006.201.16:47:59.84#ibcon#about to read 5, iclass 14, count 0 2006.201.16:47:59.84#ibcon#read 5, iclass 14, count 0 2006.201.16:47:59.84#ibcon#about to read 6, iclass 14, count 0 2006.201.16:47:59.84#ibcon#read 6, iclass 14, count 0 2006.201.16:47:59.84#ibcon#end of sib2, iclass 14, count 0 2006.201.16:47:59.84#ibcon#*mode == 0, iclass 14, count 0 2006.201.16:47:59.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.16:47:59.84#ibcon#[27=USB\r\n] 2006.201.16:47:59.84#ibcon#*before write, iclass 14, count 0 2006.201.16:47:59.84#ibcon#enter sib2, iclass 14, count 0 2006.201.16:47:59.84#ibcon#flushed, iclass 14, count 0 2006.201.16:47:59.84#ibcon#about to write, iclass 14, count 0 2006.201.16:47:59.84#ibcon#wrote, iclass 14, count 0 2006.201.16:47:59.84#ibcon#about to read 3, iclass 14, count 0 2006.201.16:47:59.87#ibcon#read 3, iclass 14, count 0 2006.201.16:47:59.87#ibcon#about to read 4, iclass 14, count 0 2006.201.16:47:59.87#ibcon#read 4, iclass 14, count 0 2006.201.16:47:59.87#ibcon#about to read 5, iclass 14, count 0 2006.201.16:47:59.87#ibcon#read 5, iclass 14, count 0 2006.201.16:47:59.87#ibcon#about to read 6, iclass 14, count 0 2006.201.16:47:59.87#ibcon#read 6, iclass 14, count 0 2006.201.16:47:59.87#ibcon#end of sib2, iclass 14, count 0 2006.201.16:47:59.87#ibcon#*after write, iclass 14, count 0 2006.201.16:47:59.87#ibcon#*before return 0, iclass 14, count 0 2006.201.16:47:59.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:47:59.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.16:47:59.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.16:47:59.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.16:47:59.87$vck44/vblo=2,634.99 2006.201.16:47:59.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.16:47:59.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.16:47:59.87#ibcon#ireg 17 cls_cnt 0 2006.201.16:47:59.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:59.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:59.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:59.87#ibcon#enter wrdev, iclass 16, count 0 2006.201.16:47:59.87#ibcon#first serial, iclass 16, count 0 2006.201.16:47:59.87#ibcon#enter sib2, iclass 16, count 0 2006.201.16:47:59.87#ibcon#flushed, iclass 16, count 0 2006.201.16:47:59.87#ibcon#about to write, iclass 16, count 0 2006.201.16:47:59.87#ibcon#wrote, iclass 16, count 0 2006.201.16:47:59.87#ibcon#about to read 3, iclass 16, count 0 2006.201.16:47:59.89#ibcon#read 3, iclass 16, count 0 2006.201.16:47:59.89#ibcon#about to read 4, iclass 16, count 0 2006.201.16:47:59.89#ibcon#read 4, iclass 16, count 0 2006.201.16:47:59.89#ibcon#about to read 5, iclass 16, count 0 2006.201.16:47:59.89#ibcon#read 5, iclass 16, count 0 2006.201.16:47:59.89#ibcon#about to read 6, iclass 16, count 0 2006.201.16:47:59.89#ibcon#read 6, iclass 16, count 0 2006.201.16:47:59.89#ibcon#end of sib2, iclass 16, count 0 2006.201.16:47:59.89#ibcon#*mode == 0, iclass 16, count 0 2006.201.16:47:59.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.16:47:59.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:47:59.89#ibcon#*before write, iclass 16, count 0 2006.201.16:47:59.89#ibcon#enter sib2, iclass 16, count 0 2006.201.16:47:59.89#ibcon#flushed, iclass 16, count 0 2006.201.16:47:59.89#ibcon#about to write, iclass 16, count 0 2006.201.16:47:59.89#ibcon#wrote, iclass 16, count 0 2006.201.16:47:59.89#ibcon#about to read 3, iclass 16, count 0 2006.201.16:47:59.93#ibcon#read 3, iclass 16, count 0 2006.201.16:47:59.93#ibcon#about to read 4, iclass 16, count 0 2006.201.16:47:59.93#ibcon#read 4, iclass 16, count 0 2006.201.16:47:59.93#ibcon#about to read 5, iclass 16, count 0 2006.201.16:47:59.93#ibcon#read 5, iclass 16, count 0 2006.201.16:47:59.93#ibcon#about to read 6, iclass 16, count 0 2006.201.16:47:59.93#ibcon#read 6, iclass 16, count 0 2006.201.16:47:59.93#ibcon#end of sib2, iclass 16, count 0 2006.201.16:47:59.93#ibcon#*after write, iclass 16, count 0 2006.201.16:47:59.93#ibcon#*before return 0, iclass 16, count 0 2006.201.16:47:59.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:59.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.16:47:59.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.16:47:59.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.16:47:59.93$vck44/vb=2,5 2006.201.16:47:59.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.16:47:59.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.16:47:59.93#ibcon#ireg 11 cls_cnt 2 2006.201.16:47:59.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:47:59.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:47:59.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:47:59.99#ibcon#enter wrdev, iclass 18, count 2 2006.201.16:47:59.99#ibcon#first serial, iclass 18, count 2 2006.201.16:47:59.99#ibcon#enter sib2, iclass 18, count 2 2006.201.16:47:59.99#ibcon#flushed, iclass 18, count 2 2006.201.16:47:59.99#ibcon#about to write, iclass 18, count 2 2006.201.16:47:59.99#ibcon#wrote, iclass 18, count 2 2006.201.16:47:59.99#ibcon#about to read 3, iclass 18, count 2 2006.201.16:48:00.01#ibcon#read 3, iclass 18, count 2 2006.201.16:48:00.01#ibcon#about to read 4, iclass 18, count 2 2006.201.16:48:00.01#ibcon#read 4, iclass 18, count 2 2006.201.16:48:00.01#ibcon#about to read 5, iclass 18, count 2 2006.201.16:48:00.01#ibcon#read 5, iclass 18, count 2 2006.201.16:48:00.01#ibcon#about to read 6, iclass 18, count 2 2006.201.16:48:00.01#ibcon#read 6, iclass 18, count 2 2006.201.16:48:00.01#ibcon#end of sib2, iclass 18, count 2 2006.201.16:48:00.01#ibcon#*mode == 0, iclass 18, count 2 2006.201.16:48:00.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.16:48:00.01#ibcon#[27=AT02-05\r\n] 2006.201.16:48:00.01#ibcon#*before write, iclass 18, count 2 2006.201.16:48:00.01#ibcon#enter sib2, iclass 18, count 2 2006.201.16:48:00.01#ibcon#flushed, iclass 18, count 2 2006.201.16:48:00.01#ibcon#about to write, iclass 18, count 2 2006.201.16:48:00.01#ibcon#wrote, iclass 18, count 2 2006.201.16:48:00.01#ibcon#about to read 3, iclass 18, count 2 2006.201.16:48:00.04#ibcon#read 3, iclass 18, count 2 2006.201.16:48:00.04#ibcon#about to read 4, iclass 18, count 2 2006.201.16:48:00.04#ibcon#read 4, iclass 18, count 2 2006.201.16:48:00.04#ibcon#about to read 5, iclass 18, count 2 2006.201.16:48:00.04#ibcon#read 5, iclass 18, count 2 2006.201.16:48:00.04#ibcon#about to read 6, iclass 18, count 2 2006.201.16:48:00.04#ibcon#read 6, iclass 18, count 2 2006.201.16:48:00.04#ibcon#end of sib2, iclass 18, count 2 2006.201.16:48:00.04#ibcon#*after write, iclass 18, count 2 2006.201.16:48:00.04#ibcon#*before return 0, iclass 18, count 2 2006.201.16:48:00.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:48:00.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.16:48:00.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.16:48:00.04#ibcon#ireg 7 cls_cnt 0 2006.201.16:48:00.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:48:00.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:48:00.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:48:00.16#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:48:00.16#ibcon#first serial, iclass 18, count 0 2006.201.16:48:00.16#ibcon#enter sib2, iclass 18, count 0 2006.201.16:48:00.16#ibcon#flushed, iclass 18, count 0 2006.201.16:48:00.16#ibcon#about to write, iclass 18, count 0 2006.201.16:48:00.16#ibcon#wrote, iclass 18, count 0 2006.201.16:48:00.16#ibcon#about to read 3, iclass 18, count 0 2006.201.16:48:00.18#ibcon#read 3, iclass 18, count 0 2006.201.16:48:00.18#ibcon#about to read 4, iclass 18, count 0 2006.201.16:48:00.18#ibcon#read 4, iclass 18, count 0 2006.201.16:48:00.18#ibcon#about to read 5, iclass 18, count 0 2006.201.16:48:00.18#ibcon#read 5, iclass 18, count 0 2006.201.16:48:00.18#ibcon#about to read 6, iclass 18, count 0 2006.201.16:48:00.18#ibcon#read 6, iclass 18, count 0 2006.201.16:48:00.18#ibcon#end of sib2, iclass 18, count 0 2006.201.16:48:00.18#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:48:00.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:48:00.18#ibcon#[27=USB\r\n] 2006.201.16:48:00.18#ibcon#*before write, iclass 18, count 0 2006.201.16:48:00.18#ibcon#enter sib2, iclass 18, count 0 2006.201.16:48:00.18#ibcon#flushed, iclass 18, count 0 2006.201.16:48:00.18#ibcon#about to write, iclass 18, count 0 2006.201.16:48:00.18#ibcon#wrote, iclass 18, count 0 2006.201.16:48:00.18#ibcon#about to read 3, iclass 18, count 0 2006.201.16:48:00.21#ibcon#read 3, iclass 18, count 0 2006.201.16:48:00.21#ibcon#about to read 4, iclass 18, count 0 2006.201.16:48:00.21#ibcon#read 4, iclass 18, count 0 2006.201.16:48:00.21#ibcon#about to read 5, iclass 18, count 0 2006.201.16:48:00.21#ibcon#read 5, iclass 18, count 0 2006.201.16:48:00.21#ibcon#about to read 6, iclass 18, count 0 2006.201.16:48:00.21#ibcon#read 6, iclass 18, count 0 2006.201.16:48:00.21#ibcon#end of sib2, iclass 18, count 0 2006.201.16:48:00.21#ibcon#*after write, iclass 18, count 0 2006.201.16:48:00.21#ibcon#*before return 0, iclass 18, count 0 2006.201.16:48:00.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:48:00.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.16:48:00.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:48:00.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:48:00.21$vck44/vblo=3,649.99 2006.201.16:48:00.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.16:48:00.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.16:48:00.21#ibcon#ireg 17 cls_cnt 0 2006.201.16:48:00.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:48:00.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:48:00.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:48:00.21#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:48:00.21#ibcon#first serial, iclass 20, count 0 2006.201.16:48:00.21#ibcon#enter sib2, iclass 20, count 0 2006.201.16:48:00.21#ibcon#flushed, iclass 20, count 0 2006.201.16:48:00.21#ibcon#about to write, iclass 20, count 0 2006.201.16:48:00.21#ibcon#wrote, iclass 20, count 0 2006.201.16:48:00.21#ibcon#about to read 3, iclass 20, count 0 2006.201.16:48:00.23#ibcon#read 3, iclass 20, count 0 2006.201.16:48:00.23#ibcon#about to read 4, iclass 20, count 0 2006.201.16:48:00.23#ibcon#read 4, iclass 20, count 0 2006.201.16:48:00.23#ibcon#about to read 5, iclass 20, count 0 2006.201.16:48:00.23#ibcon#read 5, iclass 20, count 0 2006.201.16:48:00.23#ibcon#about to read 6, iclass 20, count 0 2006.201.16:48:00.23#ibcon#read 6, iclass 20, count 0 2006.201.16:48:00.23#ibcon#end of sib2, iclass 20, count 0 2006.201.16:48:00.23#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:48:00.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:48:00.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:48:00.23#ibcon#*before write, iclass 20, count 0 2006.201.16:48:00.23#ibcon#enter sib2, iclass 20, count 0 2006.201.16:48:00.23#ibcon#flushed, iclass 20, count 0 2006.201.16:48:00.23#ibcon#about to write, iclass 20, count 0 2006.201.16:48:00.23#ibcon#wrote, iclass 20, count 0 2006.201.16:48:00.23#ibcon#about to read 3, iclass 20, count 0 2006.201.16:48:00.28#ibcon#read 3, iclass 20, count 0 2006.201.16:48:00.28#ibcon#about to read 4, iclass 20, count 0 2006.201.16:48:00.28#ibcon#read 4, iclass 20, count 0 2006.201.16:48:00.28#ibcon#about to read 5, iclass 20, count 0 2006.201.16:48:00.28#ibcon#read 5, iclass 20, count 0 2006.201.16:48:00.28#ibcon#about to read 6, iclass 20, count 0 2006.201.16:48:00.28#ibcon#read 6, iclass 20, count 0 2006.201.16:48:00.28#ibcon#end of sib2, iclass 20, count 0 2006.201.16:48:00.28#ibcon#*after write, iclass 20, count 0 2006.201.16:48:00.28#ibcon#*before return 0, iclass 20, count 0 2006.201.16:48:00.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:48:00.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.16:48:00.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:48:00.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:48:00.28$vck44/vb=3,4 2006.201.16:48:00.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.16:48:00.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.16:48:00.28#ibcon#ireg 11 cls_cnt 2 2006.201.16:48:00.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:48:00.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:48:00.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:48:00.33#ibcon#enter wrdev, iclass 22, count 2 2006.201.16:48:00.33#ibcon#first serial, iclass 22, count 2 2006.201.16:48:00.33#ibcon#enter sib2, iclass 22, count 2 2006.201.16:48:00.33#ibcon#flushed, iclass 22, count 2 2006.201.16:48:00.33#ibcon#about to write, iclass 22, count 2 2006.201.16:48:00.33#ibcon#wrote, iclass 22, count 2 2006.201.16:48:00.33#ibcon#about to read 3, iclass 22, count 2 2006.201.16:48:00.35#ibcon#read 3, iclass 22, count 2 2006.201.16:48:00.35#ibcon#about to read 4, iclass 22, count 2 2006.201.16:48:00.35#ibcon#read 4, iclass 22, count 2 2006.201.16:48:00.35#ibcon#about to read 5, iclass 22, count 2 2006.201.16:48:00.35#ibcon#read 5, iclass 22, count 2 2006.201.16:48:00.35#ibcon#about to read 6, iclass 22, count 2 2006.201.16:48:00.35#ibcon#read 6, iclass 22, count 2 2006.201.16:48:00.35#ibcon#end of sib2, iclass 22, count 2 2006.201.16:48:00.35#ibcon#*mode == 0, iclass 22, count 2 2006.201.16:48:00.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.16:48:00.35#ibcon#[27=AT03-04\r\n] 2006.201.16:48:00.35#ibcon#*before write, iclass 22, count 2 2006.201.16:48:00.35#ibcon#enter sib2, iclass 22, count 2 2006.201.16:48:00.35#ibcon#flushed, iclass 22, count 2 2006.201.16:48:00.35#ibcon#about to write, iclass 22, count 2 2006.201.16:48:00.35#ibcon#wrote, iclass 22, count 2 2006.201.16:48:00.35#ibcon#about to read 3, iclass 22, count 2 2006.201.16:48:00.38#ibcon#read 3, iclass 22, count 2 2006.201.16:48:00.38#ibcon#about to read 4, iclass 22, count 2 2006.201.16:48:00.38#ibcon#read 4, iclass 22, count 2 2006.201.16:48:00.38#ibcon#about to read 5, iclass 22, count 2 2006.201.16:48:00.38#ibcon#read 5, iclass 22, count 2 2006.201.16:48:00.38#ibcon#about to read 6, iclass 22, count 2 2006.201.16:48:00.38#ibcon#read 6, iclass 22, count 2 2006.201.16:48:00.38#ibcon#end of sib2, iclass 22, count 2 2006.201.16:48:00.38#ibcon#*after write, iclass 22, count 2 2006.201.16:48:00.38#ibcon#*before return 0, iclass 22, count 2 2006.201.16:48:00.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:48:00.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.16:48:00.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.16:48:00.38#ibcon#ireg 7 cls_cnt 0 2006.201.16:48:00.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:48:00.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:48:00.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:48:00.50#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:48:00.50#ibcon#first serial, iclass 22, count 0 2006.201.16:48:00.50#ibcon#enter sib2, iclass 22, count 0 2006.201.16:48:00.50#ibcon#flushed, iclass 22, count 0 2006.201.16:48:00.50#ibcon#about to write, iclass 22, count 0 2006.201.16:48:00.50#ibcon#wrote, iclass 22, count 0 2006.201.16:48:00.50#ibcon#about to read 3, iclass 22, count 0 2006.201.16:48:00.52#ibcon#read 3, iclass 22, count 0 2006.201.16:48:00.52#ibcon#about to read 4, iclass 22, count 0 2006.201.16:48:00.52#ibcon#read 4, iclass 22, count 0 2006.201.16:48:00.52#ibcon#about to read 5, iclass 22, count 0 2006.201.16:48:00.52#ibcon#read 5, iclass 22, count 0 2006.201.16:48:00.52#ibcon#about to read 6, iclass 22, count 0 2006.201.16:48:00.52#ibcon#read 6, iclass 22, count 0 2006.201.16:48:00.52#ibcon#end of sib2, iclass 22, count 0 2006.201.16:48:00.52#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:48:00.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:48:00.52#ibcon#[27=USB\r\n] 2006.201.16:48:00.52#ibcon#*before write, iclass 22, count 0 2006.201.16:48:00.52#ibcon#enter sib2, iclass 22, count 0 2006.201.16:48:00.52#ibcon#flushed, iclass 22, count 0 2006.201.16:48:00.52#ibcon#about to write, iclass 22, count 0 2006.201.16:48:00.52#ibcon#wrote, iclass 22, count 0 2006.201.16:48:00.52#ibcon#about to read 3, iclass 22, count 0 2006.201.16:48:00.55#ibcon#read 3, iclass 22, count 0 2006.201.16:48:00.55#ibcon#about to read 4, iclass 22, count 0 2006.201.16:48:00.55#ibcon#read 4, iclass 22, count 0 2006.201.16:48:00.55#ibcon#about to read 5, iclass 22, count 0 2006.201.16:48:00.55#ibcon#read 5, iclass 22, count 0 2006.201.16:48:00.55#ibcon#about to read 6, iclass 22, count 0 2006.201.16:48:00.55#ibcon#read 6, iclass 22, count 0 2006.201.16:48:00.55#ibcon#end of sib2, iclass 22, count 0 2006.201.16:48:00.55#ibcon#*after write, iclass 22, count 0 2006.201.16:48:00.55#ibcon#*before return 0, iclass 22, count 0 2006.201.16:48:00.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:48:00.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.16:48:00.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:48:00.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:48:00.55$vck44/vblo=4,679.99 2006.201.16:48:00.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.16:48:00.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.16:48:00.55#ibcon#ireg 17 cls_cnt 0 2006.201.16:48:00.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:48:00.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:48:00.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:48:00.55#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:48:00.55#ibcon#first serial, iclass 24, count 0 2006.201.16:48:00.55#ibcon#enter sib2, iclass 24, count 0 2006.201.16:48:00.55#ibcon#flushed, iclass 24, count 0 2006.201.16:48:00.55#ibcon#about to write, iclass 24, count 0 2006.201.16:48:00.55#ibcon#wrote, iclass 24, count 0 2006.201.16:48:00.55#ibcon#about to read 3, iclass 24, count 0 2006.201.16:48:00.57#ibcon#read 3, iclass 24, count 0 2006.201.16:48:00.57#ibcon#about to read 4, iclass 24, count 0 2006.201.16:48:00.57#ibcon#read 4, iclass 24, count 0 2006.201.16:48:00.57#ibcon#about to read 5, iclass 24, count 0 2006.201.16:48:00.57#ibcon#read 5, iclass 24, count 0 2006.201.16:48:00.57#ibcon#about to read 6, iclass 24, count 0 2006.201.16:48:00.57#ibcon#read 6, iclass 24, count 0 2006.201.16:48:00.57#ibcon#end of sib2, iclass 24, count 0 2006.201.16:48:00.57#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:48:00.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:48:00.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:48:00.57#ibcon#*before write, iclass 24, count 0 2006.201.16:48:00.57#ibcon#enter sib2, iclass 24, count 0 2006.201.16:48:00.57#ibcon#flushed, iclass 24, count 0 2006.201.16:48:00.57#ibcon#about to write, iclass 24, count 0 2006.201.16:48:00.57#ibcon#wrote, iclass 24, count 0 2006.201.16:48:00.57#ibcon#about to read 3, iclass 24, count 0 2006.201.16:48:00.61#ibcon#read 3, iclass 24, count 0 2006.201.16:48:00.61#ibcon#about to read 4, iclass 24, count 0 2006.201.16:48:00.61#ibcon#read 4, iclass 24, count 0 2006.201.16:48:00.61#ibcon#about to read 5, iclass 24, count 0 2006.201.16:48:00.61#ibcon#read 5, iclass 24, count 0 2006.201.16:48:00.61#ibcon#about to read 6, iclass 24, count 0 2006.201.16:48:00.61#ibcon#read 6, iclass 24, count 0 2006.201.16:48:00.61#ibcon#end of sib2, iclass 24, count 0 2006.201.16:48:00.61#ibcon#*after write, iclass 24, count 0 2006.201.16:48:00.61#ibcon#*before return 0, iclass 24, count 0 2006.201.16:48:00.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:48:00.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.16:48:00.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:48:00.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:48:00.61$vck44/vb=4,5 2006.201.16:48:00.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.16:48:00.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.16:48:00.61#ibcon#ireg 11 cls_cnt 2 2006.201.16:48:00.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:48:00.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:48:00.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:48:00.67#ibcon#enter wrdev, iclass 26, count 2 2006.201.16:48:00.67#ibcon#first serial, iclass 26, count 2 2006.201.16:48:00.67#ibcon#enter sib2, iclass 26, count 2 2006.201.16:48:00.67#ibcon#flushed, iclass 26, count 2 2006.201.16:48:00.67#ibcon#about to write, iclass 26, count 2 2006.201.16:48:00.67#ibcon#wrote, iclass 26, count 2 2006.201.16:48:00.67#ibcon#about to read 3, iclass 26, count 2 2006.201.16:48:00.69#ibcon#read 3, iclass 26, count 2 2006.201.16:48:00.69#ibcon#about to read 4, iclass 26, count 2 2006.201.16:48:00.69#ibcon#read 4, iclass 26, count 2 2006.201.16:48:00.69#ibcon#about to read 5, iclass 26, count 2 2006.201.16:48:00.69#ibcon#read 5, iclass 26, count 2 2006.201.16:48:00.69#ibcon#about to read 6, iclass 26, count 2 2006.201.16:48:00.69#ibcon#read 6, iclass 26, count 2 2006.201.16:48:00.69#ibcon#end of sib2, iclass 26, count 2 2006.201.16:48:00.69#ibcon#*mode == 0, iclass 26, count 2 2006.201.16:48:00.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.16:48:00.69#ibcon#[27=AT04-05\r\n] 2006.201.16:48:00.69#ibcon#*before write, iclass 26, count 2 2006.201.16:48:00.69#ibcon#enter sib2, iclass 26, count 2 2006.201.16:48:00.69#ibcon#flushed, iclass 26, count 2 2006.201.16:48:00.69#ibcon#about to write, iclass 26, count 2 2006.201.16:48:00.69#ibcon#wrote, iclass 26, count 2 2006.201.16:48:00.69#ibcon#about to read 3, iclass 26, count 2 2006.201.16:48:00.72#ibcon#read 3, iclass 26, count 2 2006.201.16:48:00.72#ibcon#about to read 4, iclass 26, count 2 2006.201.16:48:00.72#ibcon#read 4, iclass 26, count 2 2006.201.16:48:00.72#ibcon#about to read 5, iclass 26, count 2 2006.201.16:48:00.72#ibcon#read 5, iclass 26, count 2 2006.201.16:48:00.72#ibcon#about to read 6, iclass 26, count 2 2006.201.16:48:00.72#ibcon#read 6, iclass 26, count 2 2006.201.16:48:00.72#ibcon#end of sib2, iclass 26, count 2 2006.201.16:48:00.72#ibcon#*after write, iclass 26, count 2 2006.201.16:48:00.72#ibcon#*before return 0, iclass 26, count 2 2006.201.16:48:00.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:48:00.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.16:48:00.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.16:48:00.72#ibcon#ireg 7 cls_cnt 0 2006.201.16:48:00.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:48:00.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:48:00.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:48:00.84#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:48:00.84#ibcon#first serial, iclass 26, count 0 2006.201.16:48:00.84#ibcon#enter sib2, iclass 26, count 0 2006.201.16:48:00.84#ibcon#flushed, iclass 26, count 0 2006.201.16:48:00.84#ibcon#about to write, iclass 26, count 0 2006.201.16:48:00.84#ibcon#wrote, iclass 26, count 0 2006.201.16:48:00.84#ibcon#about to read 3, iclass 26, count 0 2006.201.16:48:00.86#ibcon#read 3, iclass 26, count 0 2006.201.16:48:00.86#ibcon#about to read 4, iclass 26, count 0 2006.201.16:48:00.86#ibcon#read 4, iclass 26, count 0 2006.201.16:48:00.86#ibcon#about to read 5, iclass 26, count 0 2006.201.16:48:00.86#ibcon#read 5, iclass 26, count 0 2006.201.16:48:00.86#ibcon#about to read 6, iclass 26, count 0 2006.201.16:48:00.86#ibcon#read 6, iclass 26, count 0 2006.201.16:48:00.86#ibcon#end of sib2, iclass 26, count 0 2006.201.16:48:00.86#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:48:00.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:48:00.86#ibcon#[27=USB\r\n] 2006.201.16:48:00.86#ibcon#*before write, iclass 26, count 0 2006.201.16:48:00.86#ibcon#enter sib2, iclass 26, count 0 2006.201.16:48:00.86#ibcon#flushed, iclass 26, count 0 2006.201.16:48:00.86#ibcon#about to write, iclass 26, count 0 2006.201.16:48:00.86#ibcon#wrote, iclass 26, count 0 2006.201.16:48:00.86#ibcon#about to read 3, iclass 26, count 0 2006.201.16:48:00.89#ibcon#read 3, iclass 26, count 0 2006.201.16:48:00.89#ibcon#about to read 4, iclass 26, count 0 2006.201.16:48:00.89#ibcon#read 4, iclass 26, count 0 2006.201.16:48:00.89#ibcon#about to read 5, iclass 26, count 0 2006.201.16:48:00.89#ibcon#read 5, iclass 26, count 0 2006.201.16:48:00.89#ibcon#about to read 6, iclass 26, count 0 2006.201.16:48:00.89#ibcon#read 6, iclass 26, count 0 2006.201.16:48:00.89#ibcon#end of sib2, iclass 26, count 0 2006.201.16:48:00.89#ibcon#*after write, iclass 26, count 0 2006.201.16:48:00.89#ibcon#*before return 0, iclass 26, count 0 2006.201.16:48:00.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:48:00.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.16:48:00.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:48:00.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:48:00.89$vck44/vblo=5,709.99 2006.201.16:48:00.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.16:48:00.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.16:48:00.89#ibcon#ireg 17 cls_cnt 0 2006.201.16:48:00.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:48:00.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:48:00.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:48:00.89#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:48:00.89#ibcon#first serial, iclass 28, count 0 2006.201.16:48:00.89#ibcon#enter sib2, iclass 28, count 0 2006.201.16:48:00.89#ibcon#flushed, iclass 28, count 0 2006.201.16:48:00.89#ibcon#about to write, iclass 28, count 0 2006.201.16:48:00.89#ibcon#wrote, iclass 28, count 0 2006.201.16:48:00.89#ibcon#about to read 3, iclass 28, count 0 2006.201.16:48:00.91#ibcon#read 3, iclass 28, count 0 2006.201.16:48:00.91#ibcon#about to read 4, iclass 28, count 0 2006.201.16:48:00.91#ibcon#read 4, iclass 28, count 0 2006.201.16:48:00.91#ibcon#about to read 5, iclass 28, count 0 2006.201.16:48:00.91#ibcon#read 5, iclass 28, count 0 2006.201.16:48:00.91#ibcon#about to read 6, iclass 28, count 0 2006.201.16:48:00.91#ibcon#read 6, iclass 28, count 0 2006.201.16:48:00.91#ibcon#end of sib2, iclass 28, count 0 2006.201.16:48:00.91#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:48:00.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:48:00.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:48:00.91#ibcon#*before write, iclass 28, count 0 2006.201.16:48:00.91#ibcon#enter sib2, iclass 28, count 0 2006.201.16:48:00.91#ibcon#flushed, iclass 28, count 0 2006.201.16:48:00.91#ibcon#about to write, iclass 28, count 0 2006.201.16:48:00.91#ibcon#wrote, iclass 28, count 0 2006.201.16:48:00.91#ibcon#about to read 3, iclass 28, count 0 2006.201.16:48:00.96#ibcon#read 3, iclass 28, count 0 2006.201.16:48:00.96#ibcon#about to read 4, iclass 28, count 0 2006.201.16:48:00.96#ibcon#read 4, iclass 28, count 0 2006.201.16:48:00.96#ibcon#about to read 5, iclass 28, count 0 2006.201.16:48:00.96#ibcon#read 5, iclass 28, count 0 2006.201.16:48:00.96#ibcon#about to read 6, iclass 28, count 0 2006.201.16:48:00.96#ibcon#read 6, iclass 28, count 0 2006.201.16:48:00.96#ibcon#end of sib2, iclass 28, count 0 2006.201.16:48:00.96#ibcon#*after write, iclass 28, count 0 2006.201.16:48:00.96#ibcon#*before return 0, iclass 28, count 0 2006.201.16:48:00.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:48:00.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.16:48:00.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:48:00.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:48:00.96$vck44/vb=5,4 2006.201.16:48:00.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.16:48:00.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.16:48:00.96#ibcon#ireg 11 cls_cnt 2 2006.201.16:48:00.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:48:01.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:48:01.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:48:01.01#ibcon#enter wrdev, iclass 30, count 2 2006.201.16:48:01.01#ibcon#first serial, iclass 30, count 2 2006.201.16:48:01.01#ibcon#enter sib2, iclass 30, count 2 2006.201.16:48:01.01#ibcon#flushed, iclass 30, count 2 2006.201.16:48:01.01#ibcon#about to write, iclass 30, count 2 2006.201.16:48:01.01#ibcon#wrote, iclass 30, count 2 2006.201.16:48:01.01#ibcon#about to read 3, iclass 30, count 2 2006.201.16:48:01.03#ibcon#read 3, iclass 30, count 2 2006.201.16:48:01.03#ibcon#about to read 4, iclass 30, count 2 2006.201.16:48:01.03#ibcon#read 4, iclass 30, count 2 2006.201.16:48:01.03#ibcon#about to read 5, iclass 30, count 2 2006.201.16:48:01.03#ibcon#read 5, iclass 30, count 2 2006.201.16:48:01.03#ibcon#about to read 6, iclass 30, count 2 2006.201.16:48:01.03#ibcon#read 6, iclass 30, count 2 2006.201.16:48:01.03#ibcon#end of sib2, iclass 30, count 2 2006.201.16:48:01.03#ibcon#*mode == 0, iclass 30, count 2 2006.201.16:48:01.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.16:48:01.03#ibcon#[27=AT05-04\r\n] 2006.201.16:48:01.03#ibcon#*before write, iclass 30, count 2 2006.201.16:48:01.03#ibcon#enter sib2, iclass 30, count 2 2006.201.16:48:01.03#ibcon#flushed, iclass 30, count 2 2006.201.16:48:01.03#ibcon#about to write, iclass 30, count 2 2006.201.16:48:01.03#ibcon#wrote, iclass 30, count 2 2006.201.16:48:01.03#ibcon#about to read 3, iclass 30, count 2 2006.201.16:48:01.06#ibcon#read 3, iclass 30, count 2 2006.201.16:48:01.06#ibcon#about to read 4, iclass 30, count 2 2006.201.16:48:01.06#ibcon#read 4, iclass 30, count 2 2006.201.16:48:01.06#ibcon#about to read 5, iclass 30, count 2 2006.201.16:48:01.06#ibcon#read 5, iclass 30, count 2 2006.201.16:48:01.06#ibcon#about to read 6, iclass 30, count 2 2006.201.16:48:01.06#ibcon#read 6, iclass 30, count 2 2006.201.16:48:01.06#ibcon#end of sib2, iclass 30, count 2 2006.201.16:48:01.06#ibcon#*after write, iclass 30, count 2 2006.201.16:48:01.06#ibcon#*before return 0, iclass 30, count 2 2006.201.16:48:01.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:48:01.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.16:48:01.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.16:48:01.06#ibcon#ireg 7 cls_cnt 0 2006.201.16:48:01.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:48:01.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:48:01.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:48:01.18#ibcon#enter wrdev, iclass 30, count 0 2006.201.16:48:01.18#ibcon#first serial, iclass 30, count 0 2006.201.16:48:01.18#ibcon#enter sib2, iclass 30, count 0 2006.201.16:48:01.18#ibcon#flushed, iclass 30, count 0 2006.201.16:48:01.18#ibcon#about to write, iclass 30, count 0 2006.201.16:48:01.18#ibcon#wrote, iclass 30, count 0 2006.201.16:48:01.18#ibcon#about to read 3, iclass 30, count 0 2006.201.16:48:01.20#ibcon#read 3, iclass 30, count 0 2006.201.16:48:01.20#ibcon#about to read 4, iclass 30, count 0 2006.201.16:48:01.20#ibcon#read 4, iclass 30, count 0 2006.201.16:48:01.20#ibcon#about to read 5, iclass 30, count 0 2006.201.16:48:01.20#ibcon#read 5, iclass 30, count 0 2006.201.16:48:01.20#ibcon#about to read 6, iclass 30, count 0 2006.201.16:48:01.20#ibcon#read 6, iclass 30, count 0 2006.201.16:48:01.20#ibcon#end of sib2, iclass 30, count 0 2006.201.16:48:01.20#ibcon#*mode == 0, iclass 30, count 0 2006.201.16:48:01.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.16:48:01.20#ibcon#[27=USB\r\n] 2006.201.16:48:01.20#ibcon#*before write, iclass 30, count 0 2006.201.16:48:01.20#ibcon#enter sib2, iclass 30, count 0 2006.201.16:48:01.20#ibcon#flushed, iclass 30, count 0 2006.201.16:48:01.20#ibcon#about to write, iclass 30, count 0 2006.201.16:48:01.20#ibcon#wrote, iclass 30, count 0 2006.201.16:48:01.20#ibcon#about to read 3, iclass 30, count 0 2006.201.16:48:01.23#ibcon#read 3, iclass 30, count 0 2006.201.16:48:01.23#ibcon#about to read 4, iclass 30, count 0 2006.201.16:48:01.23#ibcon#read 4, iclass 30, count 0 2006.201.16:48:01.23#ibcon#about to read 5, iclass 30, count 0 2006.201.16:48:01.23#ibcon#read 5, iclass 30, count 0 2006.201.16:48:01.23#ibcon#about to read 6, iclass 30, count 0 2006.201.16:48:01.23#ibcon#read 6, iclass 30, count 0 2006.201.16:48:01.23#ibcon#end of sib2, iclass 30, count 0 2006.201.16:48:01.23#ibcon#*after write, iclass 30, count 0 2006.201.16:48:01.23#ibcon#*before return 0, iclass 30, count 0 2006.201.16:48:01.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:48:01.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.16:48:01.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.16:48:01.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.16:48:01.23$vck44/vblo=6,719.99 2006.201.16:48:01.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.16:48:01.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.16:48:01.23#ibcon#ireg 17 cls_cnt 0 2006.201.16:48:01.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:48:01.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:48:01.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:48:01.23#ibcon#enter wrdev, iclass 32, count 0 2006.201.16:48:01.23#ibcon#first serial, iclass 32, count 0 2006.201.16:48:01.23#ibcon#enter sib2, iclass 32, count 0 2006.201.16:48:01.23#ibcon#flushed, iclass 32, count 0 2006.201.16:48:01.23#ibcon#about to write, iclass 32, count 0 2006.201.16:48:01.23#ibcon#wrote, iclass 32, count 0 2006.201.16:48:01.23#ibcon#about to read 3, iclass 32, count 0 2006.201.16:48:01.25#ibcon#read 3, iclass 32, count 0 2006.201.16:48:01.25#ibcon#about to read 4, iclass 32, count 0 2006.201.16:48:01.25#ibcon#read 4, iclass 32, count 0 2006.201.16:48:01.25#ibcon#about to read 5, iclass 32, count 0 2006.201.16:48:01.25#ibcon#read 5, iclass 32, count 0 2006.201.16:48:01.25#ibcon#about to read 6, iclass 32, count 0 2006.201.16:48:01.25#ibcon#read 6, iclass 32, count 0 2006.201.16:48:01.25#ibcon#end of sib2, iclass 32, count 0 2006.201.16:48:01.25#ibcon#*mode == 0, iclass 32, count 0 2006.201.16:48:01.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.16:48:01.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:48:01.25#ibcon#*before write, iclass 32, count 0 2006.201.16:48:01.25#ibcon#enter sib2, iclass 32, count 0 2006.201.16:48:01.25#ibcon#flushed, iclass 32, count 0 2006.201.16:48:01.25#ibcon#about to write, iclass 32, count 0 2006.201.16:48:01.25#ibcon#wrote, iclass 32, count 0 2006.201.16:48:01.25#ibcon#about to read 3, iclass 32, count 0 2006.201.16:48:01.29#ibcon#read 3, iclass 32, count 0 2006.201.16:48:01.29#ibcon#about to read 4, iclass 32, count 0 2006.201.16:48:01.29#ibcon#read 4, iclass 32, count 0 2006.201.16:48:01.29#ibcon#about to read 5, iclass 32, count 0 2006.201.16:48:01.29#ibcon#read 5, iclass 32, count 0 2006.201.16:48:01.29#ibcon#about to read 6, iclass 32, count 0 2006.201.16:48:01.29#ibcon#read 6, iclass 32, count 0 2006.201.16:48:01.29#ibcon#end of sib2, iclass 32, count 0 2006.201.16:48:01.29#ibcon#*after write, iclass 32, count 0 2006.201.16:48:01.29#ibcon#*before return 0, iclass 32, count 0 2006.201.16:48:01.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:48:01.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.16:48:01.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.16:48:01.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.16:48:01.29$vck44/vb=6,4 2006.201.16:48:01.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.16:48:01.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.16:48:01.29#ibcon#ireg 11 cls_cnt 2 2006.201.16:48:01.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:48:01.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:48:01.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:48:01.35#ibcon#enter wrdev, iclass 34, count 2 2006.201.16:48:01.35#ibcon#first serial, iclass 34, count 2 2006.201.16:48:01.35#ibcon#enter sib2, iclass 34, count 2 2006.201.16:48:01.35#ibcon#flushed, iclass 34, count 2 2006.201.16:48:01.35#ibcon#about to write, iclass 34, count 2 2006.201.16:48:01.35#ibcon#wrote, iclass 34, count 2 2006.201.16:48:01.35#ibcon#about to read 3, iclass 34, count 2 2006.201.16:48:01.37#ibcon#read 3, iclass 34, count 2 2006.201.16:48:01.37#ibcon#about to read 4, iclass 34, count 2 2006.201.16:48:01.37#ibcon#read 4, iclass 34, count 2 2006.201.16:48:01.37#ibcon#about to read 5, iclass 34, count 2 2006.201.16:48:01.37#ibcon#read 5, iclass 34, count 2 2006.201.16:48:01.37#ibcon#about to read 6, iclass 34, count 2 2006.201.16:48:01.37#ibcon#read 6, iclass 34, count 2 2006.201.16:48:01.37#ibcon#end of sib2, iclass 34, count 2 2006.201.16:48:01.37#ibcon#*mode == 0, iclass 34, count 2 2006.201.16:48:01.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.16:48:01.37#ibcon#[27=AT06-04\r\n] 2006.201.16:48:01.37#ibcon#*before write, iclass 34, count 2 2006.201.16:48:01.37#ibcon#enter sib2, iclass 34, count 2 2006.201.16:48:01.37#ibcon#flushed, iclass 34, count 2 2006.201.16:48:01.37#ibcon#about to write, iclass 34, count 2 2006.201.16:48:01.37#ibcon#wrote, iclass 34, count 2 2006.201.16:48:01.37#ibcon#about to read 3, iclass 34, count 2 2006.201.16:48:01.40#ibcon#read 3, iclass 34, count 2 2006.201.16:48:01.40#ibcon#about to read 4, iclass 34, count 2 2006.201.16:48:01.40#ibcon#read 4, iclass 34, count 2 2006.201.16:48:01.40#ibcon#about to read 5, iclass 34, count 2 2006.201.16:48:01.40#ibcon#read 5, iclass 34, count 2 2006.201.16:48:01.40#ibcon#about to read 6, iclass 34, count 2 2006.201.16:48:01.40#ibcon#read 6, iclass 34, count 2 2006.201.16:48:01.40#ibcon#end of sib2, iclass 34, count 2 2006.201.16:48:01.40#ibcon#*after write, iclass 34, count 2 2006.201.16:48:01.40#ibcon#*before return 0, iclass 34, count 2 2006.201.16:48:01.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:48:01.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.16:48:01.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.16:48:01.40#ibcon#ireg 7 cls_cnt 0 2006.201.16:48:01.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:48:01.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:48:01.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:48:01.52#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:48:01.52#ibcon#first serial, iclass 34, count 0 2006.201.16:48:01.52#ibcon#enter sib2, iclass 34, count 0 2006.201.16:48:01.52#ibcon#flushed, iclass 34, count 0 2006.201.16:48:01.52#ibcon#about to write, iclass 34, count 0 2006.201.16:48:01.52#ibcon#wrote, iclass 34, count 0 2006.201.16:48:01.52#ibcon#about to read 3, iclass 34, count 0 2006.201.16:48:01.54#ibcon#read 3, iclass 34, count 0 2006.201.16:48:01.54#ibcon#about to read 4, iclass 34, count 0 2006.201.16:48:01.54#ibcon#read 4, iclass 34, count 0 2006.201.16:48:01.54#ibcon#about to read 5, iclass 34, count 0 2006.201.16:48:01.54#ibcon#read 5, iclass 34, count 0 2006.201.16:48:01.54#ibcon#about to read 6, iclass 34, count 0 2006.201.16:48:01.54#ibcon#read 6, iclass 34, count 0 2006.201.16:48:01.54#ibcon#end of sib2, iclass 34, count 0 2006.201.16:48:01.54#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:48:01.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:48:01.54#ibcon#[27=USB\r\n] 2006.201.16:48:01.54#ibcon#*before write, iclass 34, count 0 2006.201.16:48:01.54#ibcon#enter sib2, iclass 34, count 0 2006.201.16:48:01.54#ibcon#flushed, iclass 34, count 0 2006.201.16:48:01.54#ibcon#about to write, iclass 34, count 0 2006.201.16:48:01.54#ibcon#wrote, iclass 34, count 0 2006.201.16:48:01.54#ibcon#about to read 3, iclass 34, count 0 2006.201.16:48:01.57#ibcon#read 3, iclass 34, count 0 2006.201.16:48:01.57#ibcon#about to read 4, iclass 34, count 0 2006.201.16:48:01.57#ibcon#read 4, iclass 34, count 0 2006.201.16:48:01.57#ibcon#about to read 5, iclass 34, count 0 2006.201.16:48:01.57#ibcon#read 5, iclass 34, count 0 2006.201.16:48:01.57#ibcon#about to read 6, iclass 34, count 0 2006.201.16:48:01.57#ibcon#read 6, iclass 34, count 0 2006.201.16:48:01.57#ibcon#end of sib2, iclass 34, count 0 2006.201.16:48:01.57#ibcon#*after write, iclass 34, count 0 2006.201.16:48:01.57#ibcon#*before return 0, iclass 34, count 0 2006.201.16:48:01.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:48:01.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.16:48:01.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:48:01.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:48:01.57$vck44/vblo=7,734.99 2006.201.16:48:01.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.16:48:01.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.16:48:01.57#ibcon#ireg 17 cls_cnt 0 2006.201.16:48:01.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:48:01.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:48:01.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:48:01.57#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:48:01.57#ibcon#first serial, iclass 36, count 0 2006.201.16:48:01.57#ibcon#enter sib2, iclass 36, count 0 2006.201.16:48:01.57#ibcon#flushed, iclass 36, count 0 2006.201.16:48:01.57#ibcon#about to write, iclass 36, count 0 2006.201.16:48:01.57#ibcon#wrote, iclass 36, count 0 2006.201.16:48:01.57#ibcon#about to read 3, iclass 36, count 0 2006.201.16:48:01.59#ibcon#read 3, iclass 36, count 0 2006.201.16:48:01.59#ibcon#about to read 4, iclass 36, count 0 2006.201.16:48:01.59#ibcon#read 4, iclass 36, count 0 2006.201.16:48:01.59#ibcon#about to read 5, iclass 36, count 0 2006.201.16:48:01.59#ibcon#read 5, iclass 36, count 0 2006.201.16:48:01.59#ibcon#about to read 6, iclass 36, count 0 2006.201.16:48:01.59#ibcon#read 6, iclass 36, count 0 2006.201.16:48:01.59#ibcon#end of sib2, iclass 36, count 0 2006.201.16:48:01.59#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:48:01.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:48:01.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:48:01.59#ibcon#*before write, iclass 36, count 0 2006.201.16:48:01.59#ibcon#enter sib2, iclass 36, count 0 2006.201.16:48:01.59#ibcon#flushed, iclass 36, count 0 2006.201.16:48:01.59#ibcon#about to write, iclass 36, count 0 2006.201.16:48:01.59#ibcon#wrote, iclass 36, count 0 2006.201.16:48:01.59#ibcon#about to read 3, iclass 36, count 0 2006.201.16:48:01.63#ibcon#read 3, iclass 36, count 0 2006.201.16:48:01.63#ibcon#about to read 4, iclass 36, count 0 2006.201.16:48:01.63#ibcon#read 4, iclass 36, count 0 2006.201.16:48:01.63#ibcon#about to read 5, iclass 36, count 0 2006.201.16:48:01.63#ibcon#read 5, iclass 36, count 0 2006.201.16:48:01.63#ibcon#about to read 6, iclass 36, count 0 2006.201.16:48:01.63#ibcon#read 6, iclass 36, count 0 2006.201.16:48:01.63#ibcon#end of sib2, iclass 36, count 0 2006.201.16:48:01.63#ibcon#*after write, iclass 36, count 0 2006.201.16:48:01.63#ibcon#*before return 0, iclass 36, count 0 2006.201.16:48:01.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:48:01.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.16:48:01.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:48:01.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:48:01.63$vck44/vb=7,4 2006.201.16:48:01.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.16:48:01.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.16:48:01.63#ibcon#ireg 11 cls_cnt 2 2006.201.16:48:01.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:48:01.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:48:01.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:48:01.69#ibcon#enter wrdev, iclass 38, count 2 2006.201.16:48:01.69#ibcon#first serial, iclass 38, count 2 2006.201.16:48:01.69#ibcon#enter sib2, iclass 38, count 2 2006.201.16:48:01.69#ibcon#flushed, iclass 38, count 2 2006.201.16:48:01.69#ibcon#about to write, iclass 38, count 2 2006.201.16:48:01.69#ibcon#wrote, iclass 38, count 2 2006.201.16:48:01.69#ibcon#about to read 3, iclass 38, count 2 2006.201.16:48:01.71#ibcon#read 3, iclass 38, count 2 2006.201.16:48:01.71#ibcon#about to read 4, iclass 38, count 2 2006.201.16:48:01.71#ibcon#read 4, iclass 38, count 2 2006.201.16:48:01.71#ibcon#about to read 5, iclass 38, count 2 2006.201.16:48:01.71#ibcon#read 5, iclass 38, count 2 2006.201.16:48:01.71#ibcon#about to read 6, iclass 38, count 2 2006.201.16:48:01.71#ibcon#read 6, iclass 38, count 2 2006.201.16:48:01.71#ibcon#end of sib2, iclass 38, count 2 2006.201.16:48:01.71#ibcon#*mode == 0, iclass 38, count 2 2006.201.16:48:01.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.16:48:01.71#ibcon#[27=AT07-04\r\n] 2006.201.16:48:01.71#ibcon#*before write, iclass 38, count 2 2006.201.16:48:01.71#ibcon#enter sib2, iclass 38, count 2 2006.201.16:48:01.71#ibcon#flushed, iclass 38, count 2 2006.201.16:48:01.71#ibcon#about to write, iclass 38, count 2 2006.201.16:48:01.71#ibcon#wrote, iclass 38, count 2 2006.201.16:48:01.71#ibcon#about to read 3, iclass 38, count 2 2006.201.16:48:01.74#ibcon#read 3, iclass 38, count 2 2006.201.16:48:01.74#ibcon#about to read 4, iclass 38, count 2 2006.201.16:48:01.74#ibcon#read 4, iclass 38, count 2 2006.201.16:48:01.74#ibcon#about to read 5, iclass 38, count 2 2006.201.16:48:01.74#ibcon#read 5, iclass 38, count 2 2006.201.16:48:01.74#ibcon#about to read 6, iclass 38, count 2 2006.201.16:48:01.74#ibcon#read 6, iclass 38, count 2 2006.201.16:48:01.74#ibcon#end of sib2, iclass 38, count 2 2006.201.16:48:01.74#ibcon#*after write, iclass 38, count 2 2006.201.16:48:01.74#ibcon#*before return 0, iclass 38, count 2 2006.201.16:48:01.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:48:01.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.16:48:01.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.16:48:01.74#ibcon#ireg 7 cls_cnt 0 2006.201.16:48:01.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:48:01.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:48:01.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:48:01.86#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:48:01.86#ibcon#first serial, iclass 38, count 0 2006.201.16:48:01.86#ibcon#enter sib2, iclass 38, count 0 2006.201.16:48:01.86#ibcon#flushed, iclass 38, count 0 2006.201.16:48:01.86#ibcon#about to write, iclass 38, count 0 2006.201.16:48:01.86#ibcon#wrote, iclass 38, count 0 2006.201.16:48:01.86#ibcon#about to read 3, iclass 38, count 0 2006.201.16:48:01.88#ibcon#read 3, iclass 38, count 0 2006.201.16:48:01.88#ibcon#about to read 4, iclass 38, count 0 2006.201.16:48:01.88#ibcon#read 4, iclass 38, count 0 2006.201.16:48:01.88#ibcon#about to read 5, iclass 38, count 0 2006.201.16:48:01.88#ibcon#read 5, iclass 38, count 0 2006.201.16:48:01.88#ibcon#about to read 6, iclass 38, count 0 2006.201.16:48:01.88#ibcon#read 6, iclass 38, count 0 2006.201.16:48:01.88#ibcon#end of sib2, iclass 38, count 0 2006.201.16:48:01.88#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:48:01.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:48:01.88#ibcon#[27=USB\r\n] 2006.201.16:48:01.88#ibcon#*before write, iclass 38, count 0 2006.201.16:48:01.88#ibcon#enter sib2, iclass 38, count 0 2006.201.16:48:01.88#ibcon#flushed, iclass 38, count 0 2006.201.16:48:01.88#ibcon#about to write, iclass 38, count 0 2006.201.16:48:01.88#ibcon#wrote, iclass 38, count 0 2006.201.16:48:01.88#ibcon#about to read 3, iclass 38, count 0 2006.201.16:48:01.91#ibcon#read 3, iclass 38, count 0 2006.201.16:48:01.91#ibcon#about to read 4, iclass 38, count 0 2006.201.16:48:01.91#ibcon#read 4, iclass 38, count 0 2006.201.16:48:01.91#ibcon#about to read 5, iclass 38, count 0 2006.201.16:48:01.91#ibcon#read 5, iclass 38, count 0 2006.201.16:48:01.91#ibcon#about to read 6, iclass 38, count 0 2006.201.16:48:01.91#ibcon#read 6, iclass 38, count 0 2006.201.16:48:01.91#ibcon#end of sib2, iclass 38, count 0 2006.201.16:48:01.91#ibcon#*after write, iclass 38, count 0 2006.201.16:48:01.91#ibcon#*before return 0, iclass 38, count 0 2006.201.16:48:01.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:48:01.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.16:48:01.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:48:01.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:48:01.91$vck44/vblo=8,744.99 2006.201.16:48:01.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.16:48:01.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.16:48:01.91#ibcon#ireg 17 cls_cnt 0 2006.201.16:48:01.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:48:01.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:48:01.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:48:01.91#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:48:01.91#ibcon#first serial, iclass 40, count 0 2006.201.16:48:01.91#ibcon#enter sib2, iclass 40, count 0 2006.201.16:48:01.91#ibcon#flushed, iclass 40, count 0 2006.201.16:48:01.91#ibcon#about to write, iclass 40, count 0 2006.201.16:48:01.91#ibcon#wrote, iclass 40, count 0 2006.201.16:48:01.91#ibcon#about to read 3, iclass 40, count 0 2006.201.16:48:01.93#ibcon#read 3, iclass 40, count 0 2006.201.16:48:01.93#ibcon#about to read 4, iclass 40, count 0 2006.201.16:48:01.93#ibcon#read 4, iclass 40, count 0 2006.201.16:48:01.93#ibcon#about to read 5, iclass 40, count 0 2006.201.16:48:01.93#ibcon#read 5, iclass 40, count 0 2006.201.16:48:01.93#ibcon#about to read 6, iclass 40, count 0 2006.201.16:48:01.93#ibcon#read 6, iclass 40, count 0 2006.201.16:48:01.93#ibcon#end of sib2, iclass 40, count 0 2006.201.16:48:01.93#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:48:01.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:48:01.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:48:01.93#ibcon#*before write, iclass 40, count 0 2006.201.16:48:01.93#ibcon#enter sib2, iclass 40, count 0 2006.201.16:48:01.93#ibcon#flushed, iclass 40, count 0 2006.201.16:48:01.93#ibcon#about to write, iclass 40, count 0 2006.201.16:48:01.93#ibcon#wrote, iclass 40, count 0 2006.201.16:48:01.93#ibcon#about to read 3, iclass 40, count 0 2006.201.16:48:01.98#ibcon#read 3, iclass 40, count 0 2006.201.16:48:01.98#ibcon#about to read 4, iclass 40, count 0 2006.201.16:48:01.98#ibcon#read 4, iclass 40, count 0 2006.201.16:48:01.98#ibcon#about to read 5, iclass 40, count 0 2006.201.16:48:01.98#ibcon#read 5, iclass 40, count 0 2006.201.16:48:01.98#ibcon#about to read 6, iclass 40, count 0 2006.201.16:48:01.98#ibcon#read 6, iclass 40, count 0 2006.201.16:48:01.98#ibcon#end of sib2, iclass 40, count 0 2006.201.16:48:01.98#ibcon#*after write, iclass 40, count 0 2006.201.16:48:01.98#ibcon#*before return 0, iclass 40, count 0 2006.201.16:48:01.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:48:01.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.16:48:01.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:48:01.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:48:01.98$vck44/vb=8,4 2006.201.16:48:01.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.16:48:01.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.16:48:01.98#ibcon#ireg 11 cls_cnt 2 2006.201.16:48:01.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:48:02.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:48:02.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:48:02.03#ibcon#enter wrdev, iclass 4, count 2 2006.201.16:48:02.03#ibcon#first serial, iclass 4, count 2 2006.201.16:48:02.03#ibcon#enter sib2, iclass 4, count 2 2006.201.16:48:02.03#ibcon#flushed, iclass 4, count 2 2006.201.16:48:02.03#ibcon#about to write, iclass 4, count 2 2006.201.16:48:02.03#ibcon#wrote, iclass 4, count 2 2006.201.16:48:02.03#ibcon#about to read 3, iclass 4, count 2 2006.201.16:48:02.05#ibcon#read 3, iclass 4, count 2 2006.201.16:48:02.05#ibcon#about to read 4, iclass 4, count 2 2006.201.16:48:02.05#ibcon#read 4, iclass 4, count 2 2006.201.16:48:02.05#ibcon#about to read 5, iclass 4, count 2 2006.201.16:48:02.05#ibcon#read 5, iclass 4, count 2 2006.201.16:48:02.05#ibcon#about to read 6, iclass 4, count 2 2006.201.16:48:02.05#ibcon#read 6, iclass 4, count 2 2006.201.16:48:02.05#ibcon#end of sib2, iclass 4, count 2 2006.201.16:48:02.05#ibcon#*mode == 0, iclass 4, count 2 2006.201.16:48:02.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.16:48:02.05#ibcon#[27=AT08-04\r\n] 2006.201.16:48:02.05#ibcon#*before write, iclass 4, count 2 2006.201.16:48:02.05#ibcon#enter sib2, iclass 4, count 2 2006.201.16:48:02.05#ibcon#flushed, iclass 4, count 2 2006.201.16:48:02.05#ibcon#about to write, iclass 4, count 2 2006.201.16:48:02.05#ibcon#wrote, iclass 4, count 2 2006.201.16:48:02.05#ibcon#about to read 3, iclass 4, count 2 2006.201.16:48:02.08#ibcon#read 3, iclass 4, count 2 2006.201.16:48:02.08#ibcon#about to read 4, iclass 4, count 2 2006.201.16:48:02.08#ibcon#read 4, iclass 4, count 2 2006.201.16:48:02.08#ibcon#about to read 5, iclass 4, count 2 2006.201.16:48:02.08#ibcon#read 5, iclass 4, count 2 2006.201.16:48:02.08#ibcon#about to read 6, iclass 4, count 2 2006.201.16:48:02.08#ibcon#read 6, iclass 4, count 2 2006.201.16:48:02.08#ibcon#end of sib2, iclass 4, count 2 2006.201.16:48:02.08#ibcon#*after write, iclass 4, count 2 2006.201.16:48:02.08#ibcon#*before return 0, iclass 4, count 2 2006.201.16:48:02.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:48:02.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.16:48:02.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.16:48:02.08#ibcon#ireg 7 cls_cnt 0 2006.201.16:48:02.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:48:02.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:48:02.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:48:02.20#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:48:02.20#ibcon#first serial, iclass 4, count 0 2006.201.16:48:02.20#ibcon#enter sib2, iclass 4, count 0 2006.201.16:48:02.20#ibcon#flushed, iclass 4, count 0 2006.201.16:48:02.20#ibcon#about to write, iclass 4, count 0 2006.201.16:48:02.20#ibcon#wrote, iclass 4, count 0 2006.201.16:48:02.20#ibcon#about to read 3, iclass 4, count 0 2006.201.16:48:02.22#ibcon#read 3, iclass 4, count 0 2006.201.16:48:02.22#ibcon#about to read 4, iclass 4, count 0 2006.201.16:48:02.22#ibcon#read 4, iclass 4, count 0 2006.201.16:48:02.22#ibcon#about to read 5, iclass 4, count 0 2006.201.16:48:02.22#ibcon#read 5, iclass 4, count 0 2006.201.16:48:02.22#ibcon#about to read 6, iclass 4, count 0 2006.201.16:48:02.22#ibcon#read 6, iclass 4, count 0 2006.201.16:48:02.22#ibcon#end of sib2, iclass 4, count 0 2006.201.16:48:02.22#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:48:02.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:48:02.22#ibcon#[27=USB\r\n] 2006.201.16:48:02.22#ibcon#*before write, iclass 4, count 0 2006.201.16:48:02.22#ibcon#enter sib2, iclass 4, count 0 2006.201.16:48:02.22#ibcon#flushed, iclass 4, count 0 2006.201.16:48:02.22#ibcon#about to write, iclass 4, count 0 2006.201.16:48:02.22#ibcon#wrote, iclass 4, count 0 2006.201.16:48:02.22#ibcon#about to read 3, iclass 4, count 0 2006.201.16:48:02.25#ibcon#read 3, iclass 4, count 0 2006.201.16:48:02.25#ibcon#about to read 4, iclass 4, count 0 2006.201.16:48:02.25#ibcon#read 4, iclass 4, count 0 2006.201.16:48:02.25#ibcon#about to read 5, iclass 4, count 0 2006.201.16:48:02.25#ibcon#read 5, iclass 4, count 0 2006.201.16:48:02.25#ibcon#about to read 6, iclass 4, count 0 2006.201.16:48:02.25#ibcon#read 6, iclass 4, count 0 2006.201.16:48:02.25#ibcon#end of sib2, iclass 4, count 0 2006.201.16:48:02.25#ibcon#*after write, iclass 4, count 0 2006.201.16:48:02.25#ibcon#*before return 0, iclass 4, count 0 2006.201.16:48:02.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:48:02.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.16:48:02.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:48:02.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:48:02.25$vck44/vabw=wide 2006.201.16:48:02.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.16:48:02.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.16:48:02.25#ibcon#ireg 8 cls_cnt 0 2006.201.16:48:02.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:48:02.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:48:02.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:48:02.25#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:48:02.25#ibcon#first serial, iclass 6, count 0 2006.201.16:48:02.25#ibcon#enter sib2, iclass 6, count 0 2006.201.16:48:02.25#ibcon#flushed, iclass 6, count 0 2006.201.16:48:02.25#ibcon#about to write, iclass 6, count 0 2006.201.16:48:02.25#ibcon#wrote, iclass 6, count 0 2006.201.16:48:02.25#ibcon#about to read 3, iclass 6, count 0 2006.201.16:48:02.27#ibcon#read 3, iclass 6, count 0 2006.201.16:48:02.27#ibcon#about to read 4, iclass 6, count 0 2006.201.16:48:02.27#ibcon#read 4, iclass 6, count 0 2006.201.16:48:02.27#ibcon#about to read 5, iclass 6, count 0 2006.201.16:48:02.27#ibcon#read 5, iclass 6, count 0 2006.201.16:48:02.27#ibcon#about to read 6, iclass 6, count 0 2006.201.16:48:02.27#ibcon#read 6, iclass 6, count 0 2006.201.16:48:02.27#ibcon#end of sib2, iclass 6, count 0 2006.201.16:48:02.27#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:48:02.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:48:02.27#ibcon#[25=BW32\r\n] 2006.201.16:48:02.27#ibcon#*before write, iclass 6, count 0 2006.201.16:48:02.27#ibcon#enter sib2, iclass 6, count 0 2006.201.16:48:02.27#ibcon#flushed, iclass 6, count 0 2006.201.16:48:02.27#ibcon#about to write, iclass 6, count 0 2006.201.16:48:02.27#ibcon#wrote, iclass 6, count 0 2006.201.16:48:02.27#ibcon#about to read 3, iclass 6, count 0 2006.201.16:48:02.30#ibcon#read 3, iclass 6, count 0 2006.201.16:48:02.30#ibcon#about to read 4, iclass 6, count 0 2006.201.16:48:02.30#ibcon#read 4, iclass 6, count 0 2006.201.16:48:02.30#ibcon#about to read 5, iclass 6, count 0 2006.201.16:48:02.30#ibcon#read 5, iclass 6, count 0 2006.201.16:48:02.30#ibcon#about to read 6, iclass 6, count 0 2006.201.16:48:02.30#ibcon#read 6, iclass 6, count 0 2006.201.16:48:02.30#ibcon#end of sib2, iclass 6, count 0 2006.201.16:48:02.30#ibcon#*after write, iclass 6, count 0 2006.201.16:48:02.30#ibcon#*before return 0, iclass 6, count 0 2006.201.16:48:02.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:48:02.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.16:48:02.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:48:02.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:48:02.30$vck44/vbbw=wide 2006.201.16:48:02.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.16:48:02.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.16:48:02.30#ibcon#ireg 8 cls_cnt 0 2006.201.16:48:02.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:48:02.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:48:02.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:48:02.37#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:48:02.37#ibcon#first serial, iclass 10, count 0 2006.201.16:48:02.37#ibcon#enter sib2, iclass 10, count 0 2006.201.16:48:02.37#ibcon#flushed, iclass 10, count 0 2006.201.16:48:02.37#ibcon#about to write, iclass 10, count 0 2006.201.16:48:02.37#ibcon#wrote, iclass 10, count 0 2006.201.16:48:02.37#ibcon#about to read 3, iclass 10, count 0 2006.201.16:48:02.39#ibcon#read 3, iclass 10, count 0 2006.201.16:48:02.39#ibcon#about to read 4, iclass 10, count 0 2006.201.16:48:02.39#ibcon#read 4, iclass 10, count 0 2006.201.16:48:02.39#ibcon#about to read 5, iclass 10, count 0 2006.201.16:48:02.39#ibcon#read 5, iclass 10, count 0 2006.201.16:48:02.39#ibcon#about to read 6, iclass 10, count 0 2006.201.16:48:02.39#ibcon#read 6, iclass 10, count 0 2006.201.16:48:02.39#ibcon#end of sib2, iclass 10, count 0 2006.201.16:48:02.39#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:48:02.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:48:02.39#ibcon#[27=BW32\r\n] 2006.201.16:48:02.39#ibcon#*before write, iclass 10, count 0 2006.201.16:48:02.39#ibcon#enter sib2, iclass 10, count 0 2006.201.16:48:02.39#ibcon#flushed, iclass 10, count 0 2006.201.16:48:02.39#ibcon#about to write, iclass 10, count 0 2006.201.16:48:02.39#ibcon#wrote, iclass 10, count 0 2006.201.16:48:02.39#ibcon#about to read 3, iclass 10, count 0 2006.201.16:48:02.42#ibcon#read 3, iclass 10, count 0 2006.201.16:48:02.42#ibcon#about to read 4, iclass 10, count 0 2006.201.16:48:02.42#ibcon#read 4, iclass 10, count 0 2006.201.16:48:02.42#ibcon#about to read 5, iclass 10, count 0 2006.201.16:48:02.42#ibcon#read 5, iclass 10, count 0 2006.201.16:48:02.42#ibcon#about to read 6, iclass 10, count 0 2006.201.16:48:02.42#ibcon#read 6, iclass 10, count 0 2006.201.16:48:02.42#ibcon#end of sib2, iclass 10, count 0 2006.201.16:48:02.42#ibcon#*after write, iclass 10, count 0 2006.201.16:48:02.42#ibcon#*before return 0, iclass 10, count 0 2006.201.16:48:02.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:48:02.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:48:02.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:48:02.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:48:02.42$setupk4/ifdk4 2006.201.16:48:02.42$ifdk4/lo= 2006.201.16:48:02.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:48:02.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:48:02.42$ifdk4/patch= 2006.201.16:48:02.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:48:02.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:48:02.42$setupk4/!*+20s 2006.201.16:48:03.78#abcon#<5=/03 0.3 0.9 20.811001002.6\r\n> 2006.201.16:48:03.80#abcon#{5=INTERFACE CLEAR} 2006.201.16:48:03.86#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:48:14.04#abcon#<5=/03 0.3 0.9 20.811001002.6\r\n> 2006.201.16:48:14.06#abcon#{5=INTERFACE CLEAR} 2006.201.16:48:14.12#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:48:16.90$setupk4/"tpicd 2006.201.16:48:16.90$setupk4/echo=off 2006.201.16:48:16.90$setupk4/xlog=off 2006.201.16:48:16.90:!2006.201.16:53:05 2006.201.16:48:29.14#trakl#Source acquired 2006.201.16:48:31.14#flagr#flagr/antenna,acquired 2006.201.16:53:05.00:preob 2006.201.16:53:05.14/onsource/TRACKING 2006.201.16:53:05.14:!2006.201.16:53:15 2006.201.16:53:15.00:"tape 2006.201.16:53:15.00:"st=record 2006.201.16:53:15.00:data_valid=on 2006.201.16:53:15.00:midob 2006.201.16:53:16.14/onsource/TRACKING 2006.201.16:53:16.14/wx/20.82,1002.6,100 2006.201.16:53:16.29/cable/+6.4780E-03 2006.201.16:53:17.38/va/01,08,usb,yes,36,39 2006.201.16:53:17.38/va/02,07,usb,yes,39,40 2006.201.16:53:17.38/va/03,08,usb,yes,36,37 2006.201.16:53:17.38/va/04,07,usb,yes,41,43 2006.201.16:53:17.38/va/05,04,usb,yes,36,37 2006.201.16:53:17.38/va/06,05,usb,yes,36,36 2006.201.16:53:17.38/va/07,05,usb,yes,35,37 2006.201.16:53:17.38/va/08,04,usb,yes,35,42 2006.201.16:53:17.61/valo/01,524.99,yes,locked 2006.201.16:53:17.61/valo/02,534.99,yes,locked 2006.201.16:53:17.61/valo/03,564.99,yes,locked 2006.201.16:53:17.61/valo/04,624.99,yes,locked 2006.201.16:53:17.61/valo/05,734.99,yes,locked 2006.201.16:53:17.61/valo/06,814.99,yes,locked 2006.201.16:53:17.61/valo/07,864.99,yes,locked 2006.201.16:53:17.61/valo/08,884.99,yes,locked 2006.201.16:53:18.70/vb/01,04,usb,yes,30,28 2006.201.16:53:18.70/vb/02,05,usb,yes,29,28 2006.201.16:53:18.70/vb/03,04,usb,yes,30,33 2006.201.16:53:18.70/vb/04,05,usb,yes,30,29 2006.201.16:53:18.70/vb/05,04,usb,yes,26,29 2006.201.16:53:18.70/vb/06,04,usb,yes,31,27 2006.201.16:53:18.70/vb/07,04,usb,yes,31,31 2006.201.16:53:18.70/vb/08,04,usb,yes,28,32 2006.201.16:53:18.94/vblo/01,629.99,yes,locked 2006.201.16:53:18.94/vblo/02,634.99,yes,locked 2006.201.16:53:18.94/vblo/03,649.99,yes,locked 2006.201.16:53:18.94/vblo/04,679.99,yes,locked 2006.201.16:53:18.94/vblo/05,709.99,yes,locked 2006.201.16:53:18.94/vblo/06,719.99,yes,locked 2006.201.16:53:18.94/vblo/07,734.99,yes,locked 2006.201.16:53:18.94/vblo/08,744.99,yes,locked 2006.201.16:53:19.09/vabw/8 2006.201.16:53:19.24/vbbw/8 2006.201.16:53:19.34/xfe/off,on,15.2 2006.201.16:53:19.73/ifatt/23,28,28,28 2006.201.16:53:20.06/fmout-gps/S +4.59E-07 2006.201.16:53:20.13:!2006.201.16:54:25 2006.201.16:54:25.00:data_valid=off 2006.201.16:54:25.00:"et 2006.201.16:54:25.00:!+3s 2006.201.16:54:28.02:"tape 2006.201.16:54:28.02:postob 2006.201.16:54:28.09/cable/+6.4796E-03 2006.201.16:54:28.09/wx/20.83,1002.6,100 2006.201.16:54:28.16/fmout-gps/S +4.58E-07 2006.201.16:54:28.16:scan_name=201-1656,jd0607,110 2006.201.16:54:28.17:source=0552+398,055530.81,394849.2,2000.0,cw 2006.201.16:54:30.13#flagr#flagr/antenna,new-source 2006.201.16:54:30.13:checkk5 2006.201.16:54:30.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:54:30.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:54:31.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:54:31.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:54:31.96/chk_obsdata//k5ts1/T2011653??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.16:54:32.33/chk_obsdata//k5ts2/T2011653??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.16:54:32.71/chk_obsdata//k5ts3/T2011653??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.16:54:33.07/chk_obsdata//k5ts4/T2011653??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.16:54:33.77/k5log//k5ts1_log_newline 2006.201.16:54:34.45/k5log//k5ts2_log_newline 2006.201.16:54:35.14/k5log//k5ts3_log_newline 2006.201.16:54:35.82/k5log//k5ts4_log_newline 2006.201.16:54:35.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:54:35.85:setupk4=1 2006.201.16:54:35.85$setupk4/echo=on 2006.201.16:54:35.85$setupk4/pcalon 2006.201.16:54:35.85$pcalon/"no phase cal control is implemented here 2006.201.16:54:35.85$setupk4/"tpicd=stop 2006.201.16:54:35.85$setupk4/"rec=synch_on 2006.201.16:54:35.85$setupk4/"rec_mode=128 2006.201.16:54:35.85$setupk4/!* 2006.201.16:54:35.85$setupk4/recpk4 2006.201.16:54:35.85$recpk4/recpatch= 2006.201.16:54:35.85$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:54:35.85$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:54:35.85$setupk4/vck44 2006.201.16:54:35.85$vck44/valo=1,524.99 2006.201.16:54:35.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.16:54:35.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.16:54:35.85#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:35.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:35.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:35.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:35.85#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:54:35.85#ibcon#first serial, iclass 27, count 0 2006.201.16:54:35.85#ibcon#enter sib2, iclass 27, count 0 2006.201.16:54:35.85#ibcon#flushed, iclass 27, count 0 2006.201.16:54:35.85#ibcon#about to write, iclass 27, count 0 2006.201.16:54:35.85#ibcon#wrote, iclass 27, count 0 2006.201.16:54:35.85#ibcon#about to read 3, iclass 27, count 0 2006.201.16:54:35.89#ibcon#read 3, iclass 27, count 0 2006.201.16:54:35.89#ibcon#about to read 4, iclass 27, count 0 2006.201.16:54:35.89#ibcon#read 4, iclass 27, count 0 2006.201.16:54:35.89#ibcon#about to read 5, iclass 27, count 0 2006.201.16:54:35.89#ibcon#read 5, iclass 27, count 0 2006.201.16:54:35.89#ibcon#about to read 6, iclass 27, count 0 2006.201.16:54:35.89#ibcon#read 6, iclass 27, count 0 2006.201.16:54:35.89#ibcon#end of sib2, iclass 27, count 0 2006.201.16:54:35.89#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:54:35.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:54:35.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:54:35.89#ibcon#*before write, iclass 27, count 0 2006.201.16:54:35.89#ibcon#enter sib2, iclass 27, count 0 2006.201.16:54:35.89#ibcon#flushed, iclass 27, count 0 2006.201.16:54:35.89#ibcon#about to write, iclass 27, count 0 2006.201.16:54:35.89#ibcon#wrote, iclass 27, count 0 2006.201.16:54:35.89#ibcon#about to read 3, iclass 27, count 0 2006.201.16:54:35.94#ibcon#read 3, iclass 27, count 0 2006.201.16:54:35.94#ibcon#about to read 4, iclass 27, count 0 2006.201.16:54:35.94#ibcon#read 4, iclass 27, count 0 2006.201.16:54:35.94#ibcon#about to read 5, iclass 27, count 0 2006.201.16:54:35.94#ibcon#read 5, iclass 27, count 0 2006.201.16:54:35.94#ibcon#about to read 6, iclass 27, count 0 2006.201.16:54:35.94#ibcon#read 6, iclass 27, count 0 2006.201.16:54:35.94#ibcon#end of sib2, iclass 27, count 0 2006.201.16:54:35.94#ibcon#*after write, iclass 27, count 0 2006.201.16:54:35.94#ibcon#*before return 0, iclass 27, count 0 2006.201.16:54:35.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:35.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:35.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:54:35.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:54:35.94$vck44/va=1,8 2006.201.16:54:35.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.16:54:35.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.16:54:35.94#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:35.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:35.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:35.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:35.94#ibcon#enter wrdev, iclass 29, count 2 2006.201.16:54:35.94#ibcon#first serial, iclass 29, count 2 2006.201.16:54:35.94#ibcon#enter sib2, iclass 29, count 2 2006.201.16:54:35.94#ibcon#flushed, iclass 29, count 2 2006.201.16:54:35.94#ibcon#about to write, iclass 29, count 2 2006.201.16:54:35.94#ibcon#wrote, iclass 29, count 2 2006.201.16:54:35.94#ibcon#about to read 3, iclass 29, count 2 2006.201.16:54:35.96#ibcon#read 3, iclass 29, count 2 2006.201.16:54:35.96#ibcon#about to read 4, iclass 29, count 2 2006.201.16:54:35.96#ibcon#read 4, iclass 29, count 2 2006.201.16:54:35.96#ibcon#about to read 5, iclass 29, count 2 2006.201.16:54:35.96#ibcon#read 5, iclass 29, count 2 2006.201.16:54:35.96#ibcon#about to read 6, iclass 29, count 2 2006.201.16:54:35.96#ibcon#read 6, iclass 29, count 2 2006.201.16:54:35.96#ibcon#end of sib2, iclass 29, count 2 2006.201.16:54:35.96#ibcon#*mode == 0, iclass 29, count 2 2006.201.16:54:35.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.16:54:35.96#ibcon#[25=AT01-08\r\n] 2006.201.16:54:35.96#ibcon#*before write, iclass 29, count 2 2006.201.16:54:35.96#ibcon#enter sib2, iclass 29, count 2 2006.201.16:54:35.96#ibcon#flushed, iclass 29, count 2 2006.201.16:54:35.96#ibcon#about to write, iclass 29, count 2 2006.201.16:54:35.96#ibcon#wrote, iclass 29, count 2 2006.201.16:54:35.96#ibcon#about to read 3, iclass 29, count 2 2006.201.16:54:35.99#ibcon#read 3, iclass 29, count 2 2006.201.16:54:35.99#ibcon#about to read 4, iclass 29, count 2 2006.201.16:54:35.99#ibcon#read 4, iclass 29, count 2 2006.201.16:54:35.99#ibcon#about to read 5, iclass 29, count 2 2006.201.16:54:35.99#ibcon#read 5, iclass 29, count 2 2006.201.16:54:35.99#ibcon#about to read 6, iclass 29, count 2 2006.201.16:54:35.99#ibcon#read 6, iclass 29, count 2 2006.201.16:54:35.99#ibcon#end of sib2, iclass 29, count 2 2006.201.16:54:35.99#ibcon#*after write, iclass 29, count 2 2006.201.16:54:35.99#ibcon#*before return 0, iclass 29, count 2 2006.201.16:54:35.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:35.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:35.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.16:54:35.99#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:35.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:36.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:36.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:36.11#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:54:36.11#ibcon#first serial, iclass 29, count 0 2006.201.16:54:36.11#ibcon#enter sib2, iclass 29, count 0 2006.201.16:54:36.11#ibcon#flushed, iclass 29, count 0 2006.201.16:54:36.11#ibcon#about to write, iclass 29, count 0 2006.201.16:54:36.11#ibcon#wrote, iclass 29, count 0 2006.201.16:54:36.11#ibcon#about to read 3, iclass 29, count 0 2006.201.16:54:36.13#ibcon#read 3, iclass 29, count 0 2006.201.16:54:36.13#ibcon#about to read 4, iclass 29, count 0 2006.201.16:54:36.13#ibcon#read 4, iclass 29, count 0 2006.201.16:54:36.13#ibcon#about to read 5, iclass 29, count 0 2006.201.16:54:36.13#ibcon#read 5, iclass 29, count 0 2006.201.16:54:36.13#ibcon#about to read 6, iclass 29, count 0 2006.201.16:54:36.13#ibcon#read 6, iclass 29, count 0 2006.201.16:54:36.13#ibcon#end of sib2, iclass 29, count 0 2006.201.16:54:36.13#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:54:36.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:54:36.13#ibcon#[25=USB\r\n] 2006.201.16:54:36.13#ibcon#*before write, iclass 29, count 0 2006.201.16:54:36.13#ibcon#enter sib2, iclass 29, count 0 2006.201.16:54:36.13#ibcon#flushed, iclass 29, count 0 2006.201.16:54:36.13#ibcon#about to write, iclass 29, count 0 2006.201.16:54:36.13#ibcon#wrote, iclass 29, count 0 2006.201.16:54:36.13#ibcon#about to read 3, iclass 29, count 0 2006.201.16:54:36.16#ibcon#read 3, iclass 29, count 0 2006.201.16:54:36.16#ibcon#about to read 4, iclass 29, count 0 2006.201.16:54:36.16#ibcon#read 4, iclass 29, count 0 2006.201.16:54:36.16#ibcon#about to read 5, iclass 29, count 0 2006.201.16:54:36.16#ibcon#read 5, iclass 29, count 0 2006.201.16:54:36.16#ibcon#about to read 6, iclass 29, count 0 2006.201.16:54:36.16#ibcon#read 6, iclass 29, count 0 2006.201.16:54:36.16#ibcon#end of sib2, iclass 29, count 0 2006.201.16:54:36.16#ibcon#*after write, iclass 29, count 0 2006.201.16:54:36.16#ibcon#*before return 0, iclass 29, count 0 2006.201.16:54:36.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:36.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:36.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:54:36.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:54:36.16$vck44/valo=2,534.99 2006.201.16:54:36.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.16:54:36.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.16:54:36.16#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:36.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:36.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:36.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:36.16#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:54:36.16#ibcon#first serial, iclass 31, count 0 2006.201.16:54:36.16#ibcon#enter sib2, iclass 31, count 0 2006.201.16:54:36.16#ibcon#flushed, iclass 31, count 0 2006.201.16:54:36.16#ibcon#about to write, iclass 31, count 0 2006.201.16:54:36.16#ibcon#wrote, iclass 31, count 0 2006.201.16:54:36.16#ibcon#about to read 3, iclass 31, count 0 2006.201.16:54:36.18#ibcon#read 3, iclass 31, count 0 2006.201.16:54:36.18#ibcon#about to read 4, iclass 31, count 0 2006.201.16:54:36.18#ibcon#read 4, iclass 31, count 0 2006.201.16:54:36.18#ibcon#about to read 5, iclass 31, count 0 2006.201.16:54:36.18#ibcon#read 5, iclass 31, count 0 2006.201.16:54:36.18#ibcon#about to read 6, iclass 31, count 0 2006.201.16:54:36.18#ibcon#read 6, iclass 31, count 0 2006.201.16:54:36.18#ibcon#end of sib2, iclass 31, count 0 2006.201.16:54:36.18#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:54:36.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:54:36.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:54:36.18#ibcon#*before write, iclass 31, count 0 2006.201.16:54:36.18#ibcon#enter sib2, iclass 31, count 0 2006.201.16:54:36.18#ibcon#flushed, iclass 31, count 0 2006.201.16:54:36.18#ibcon#about to write, iclass 31, count 0 2006.201.16:54:36.18#ibcon#wrote, iclass 31, count 0 2006.201.16:54:36.18#ibcon#about to read 3, iclass 31, count 0 2006.201.16:54:36.22#ibcon#read 3, iclass 31, count 0 2006.201.16:54:36.22#ibcon#about to read 4, iclass 31, count 0 2006.201.16:54:36.22#ibcon#read 4, iclass 31, count 0 2006.201.16:54:36.22#ibcon#about to read 5, iclass 31, count 0 2006.201.16:54:36.22#ibcon#read 5, iclass 31, count 0 2006.201.16:54:36.22#ibcon#about to read 6, iclass 31, count 0 2006.201.16:54:36.22#ibcon#read 6, iclass 31, count 0 2006.201.16:54:36.22#ibcon#end of sib2, iclass 31, count 0 2006.201.16:54:36.22#ibcon#*after write, iclass 31, count 0 2006.201.16:54:36.22#ibcon#*before return 0, iclass 31, count 0 2006.201.16:54:36.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:36.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:36.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:54:36.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:54:36.22$vck44/va=2,7 2006.201.16:54:36.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.16:54:36.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.16:54:36.22#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:36.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:36.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:36.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:36.28#ibcon#enter wrdev, iclass 33, count 2 2006.201.16:54:36.28#ibcon#first serial, iclass 33, count 2 2006.201.16:54:36.28#ibcon#enter sib2, iclass 33, count 2 2006.201.16:54:36.28#ibcon#flushed, iclass 33, count 2 2006.201.16:54:36.28#ibcon#about to write, iclass 33, count 2 2006.201.16:54:36.28#ibcon#wrote, iclass 33, count 2 2006.201.16:54:36.28#ibcon#about to read 3, iclass 33, count 2 2006.201.16:54:36.30#ibcon#read 3, iclass 33, count 2 2006.201.16:54:36.30#ibcon#about to read 4, iclass 33, count 2 2006.201.16:54:36.30#ibcon#read 4, iclass 33, count 2 2006.201.16:54:36.30#ibcon#about to read 5, iclass 33, count 2 2006.201.16:54:36.30#ibcon#read 5, iclass 33, count 2 2006.201.16:54:36.30#ibcon#about to read 6, iclass 33, count 2 2006.201.16:54:36.30#ibcon#read 6, iclass 33, count 2 2006.201.16:54:36.30#ibcon#end of sib2, iclass 33, count 2 2006.201.16:54:36.30#ibcon#*mode == 0, iclass 33, count 2 2006.201.16:54:36.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.16:54:36.30#ibcon#[25=AT02-07\r\n] 2006.201.16:54:36.30#ibcon#*before write, iclass 33, count 2 2006.201.16:54:36.30#ibcon#enter sib2, iclass 33, count 2 2006.201.16:54:36.30#ibcon#flushed, iclass 33, count 2 2006.201.16:54:36.30#ibcon#about to write, iclass 33, count 2 2006.201.16:54:36.30#ibcon#wrote, iclass 33, count 2 2006.201.16:54:36.30#ibcon#about to read 3, iclass 33, count 2 2006.201.16:54:36.33#ibcon#read 3, iclass 33, count 2 2006.201.16:54:36.33#ibcon#about to read 4, iclass 33, count 2 2006.201.16:54:36.33#ibcon#read 4, iclass 33, count 2 2006.201.16:54:36.33#ibcon#about to read 5, iclass 33, count 2 2006.201.16:54:36.33#ibcon#read 5, iclass 33, count 2 2006.201.16:54:36.33#ibcon#about to read 6, iclass 33, count 2 2006.201.16:54:36.33#ibcon#read 6, iclass 33, count 2 2006.201.16:54:36.33#ibcon#end of sib2, iclass 33, count 2 2006.201.16:54:36.33#ibcon#*after write, iclass 33, count 2 2006.201.16:54:36.33#ibcon#*before return 0, iclass 33, count 2 2006.201.16:54:36.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:36.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:36.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.16:54:36.33#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:36.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:36.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:36.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:36.45#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:54:36.45#ibcon#first serial, iclass 33, count 0 2006.201.16:54:36.45#ibcon#enter sib2, iclass 33, count 0 2006.201.16:54:36.45#ibcon#flushed, iclass 33, count 0 2006.201.16:54:36.45#ibcon#about to write, iclass 33, count 0 2006.201.16:54:36.45#ibcon#wrote, iclass 33, count 0 2006.201.16:54:36.45#ibcon#about to read 3, iclass 33, count 0 2006.201.16:54:36.47#ibcon#read 3, iclass 33, count 0 2006.201.16:54:36.47#ibcon#about to read 4, iclass 33, count 0 2006.201.16:54:36.47#ibcon#read 4, iclass 33, count 0 2006.201.16:54:36.47#ibcon#about to read 5, iclass 33, count 0 2006.201.16:54:36.47#ibcon#read 5, iclass 33, count 0 2006.201.16:54:36.47#ibcon#about to read 6, iclass 33, count 0 2006.201.16:54:36.47#ibcon#read 6, iclass 33, count 0 2006.201.16:54:36.47#ibcon#end of sib2, iclass 33, count 0 2006.201.16:54:36.47#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:54:36.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:54:36.47#ibcon#[25=USB\r\n] 2006.201.16:54:36.47#ibcon#*before write, iclass 33, count 0 2006.201.16:54:36.47#ibcon#enter sib2, iclass 33, count 0 2006.201.16:54:36.47#ibcon#flushed, iclass 33, count 0 2006.201.16:54:36.47#ibcon#about to write, iclass 33, count 0 2006.201.16:54:36.47#ibcon#wrote, iclass 33, count 0 2006.201.16:54:36.47#ibcon#about to read 3, iclass 33, count 0 2006.201.16:54:36.50#ibcon#read 3, iclass 33, count 0 2006.201.16:54:36.50#ibcon#about to read 4, iclass 33, count 0 2006.201.16:54:36.50#ibcon#read 4, iclass 33, count 0 2006.201.16:54:36.50#ibcon#about to read 5, iclass 33, count 0 2006.201.16:54:36.50#ibcon#read 5, iclass 33, count 0 2006.201.16:54:36.50#ibcon#about to read 6, iclass 33, count 0 2006.201.16:54:36.50#ibcon#read 6, iclass 33, count 0 2006.201.16:54:36.50#ibcon#end of sib2, iclass 33, count 0 2006.201.16:54:36.50#ibcon#*after write, iclass 33, count 0 2006.201.16:54:36.50#ibcon#*before return 0, iclass 33, count 0 2006.201.16:54:36.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:36.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:36.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:54:36.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:54:36.50$vck44/valo=3,564.99 2006.201.16:54:36.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.16:54:36.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.16:54:36.50#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:36.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:36.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:36.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:36.50#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:54:36.50#ibcon#first serial, iclass 35, count 0 2006.201.16:54:36.50#ibcon#enter sib2, iclass 35, count 0 2006.201.16:54:36.50#ibcon#flushed, iclass 35, count 0 2006.201.16:54:36.50#ibcon#about to write, iclass 35, count 0 2006.201.16:54:36.50#ibcon#wrote, iclass 35, count 0 2006.201.16:54:36.50#ibcon#about to read 3, iclass 35, count 0 2006.201.16:54:36.52#ibcon#read 3, iclass 35, count 0 2006.201.16:54:36.52#ibcon#about to read 4, iclass 35, count 0 2006.201.16:54:36.52#ibcon#read 4, iclass 35, count 0 2006.201.16:54:36.52#ibcon#about to read 5, iclass 35, count 0 2006.201.16:54:36.52#ibcon#read 5, iclass 35, count 0 2006.201.16:54:36.52#ibcon#about to read 6, iclass 35, count 0 2006.201.16:54:36.52#ibcon#read 6, iclass 35, count 0 2006.201.16:54:36.52#ibcon#end of sib2, iclass 35, count 0 2006.201.16:54:36.52#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:54:36.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:54:36.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:54:36.52#ibcon#*before write, iclass 35, count 0 2006.201.16:54:36.52#ibcon#enter sib2, iclass 35, count 0 2006.201.16:54:36.52#ibcon#flushed, iclass 35, count 0 2006.201.16:54:36.52#ibcon#about to write, iclass 35, count 0 2006.201.16:54:36.52#ibcon#wrote, iclass 35, count 0 2006.201.16:54:36.52#ibcon#about to read 3, iclass 35, count 0 2006.201.16:54:36.56#ibcon#read 3, iclass 35, count 0 2006.201.16:54:36.56#ibcon#about to read 4, iclass 35, count 0 2006.201.16:54:36.56#ibcon#read 4, iclass 35, count 0 2006.201.16:54:36.56#ibcon#about to read 5, iclass 35, count 0 2006.201.16:54:36.56#ibcon#read 5, iclass 35, count 0 2006.201.16:54:36.56#ibcon#about to read 6, iclass 35, count 0 2006.201.16:54:36.56#ibcon#read 6, iclass 35, count 0 2006.201.16:54:36.56#ibcon#end of sib2, iclass 35, count 0 2006.201.16:54:36.56#ibcon#*after write, iclass 35, count 0 2006.201.16:54:36.56#ibcon#*before return 0, iclass 35, count 0 2006.201.16:54:36.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:36.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:36.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:54:36.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:54:36.56$vck44/va=3,8 2006.201.16:54:36.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.16:54:36.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.16:54:36.56#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:36.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:36.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:36.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:36.62#ibcon#enter wrdev, iclass 37, count 2 2006.201.16:54:36.62#ibcon#first serial, iclass 37, count 2 2006.201.16:54:36.62#ibcon#enter sib2, iclass 37, count 2 2006.201.16:54:36.62#ibcon#flushed, iclass 37, count 2 2006.201.16:54:36.62#ibcon#about to write, iclass 37, count 2 2006.201.16:54:36.62#ibcon#wrote, iclass 37, count 2 2006.201.16:54:36.62#ibcon#about to read 3, iclass 37, count 2 2006.201.16:54:36.64#ibcon#read 3, iclass 37, count 2 2006.201.16:54:36.64#ibcon#about to read 4, iclass 37, count 2 2006.201.16:54:36.64#ibcon#read 4, iclass 37, count 2 2006.201.16:54:36.64#ibcon#about to read 5, iclass 37, count 2 2006.201.16:54:36.64#ibcon#read 5, iclass 37, count 2 2006.201.16:54:36.64#ibcon#about to read 6, iclass 37, count 2 2006.201.16:54:36.64#ibcon#read 6, iclass 37, count 2 2006.201.16:54:36.64#ibcon#end of sib2, iclass 37, count 2 2006.201.16:54:36.64#ibcon#*mode == 0, iclass 37, count 2 2006.201.16:54:36.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.16:54:36.64#ibcon#[25=AT03-08\r\n] 2006.201.16:54:36.64#ibcon#*before write, iclass 37, count 2 2006.201.16:54:36.64#ibcon#enter sib2, iclass 37, count 2 2006.201.16:54:36.64#ibcon#flushed, iclass 37, count 2 2006.201.16:54:36.64#ibcon#about to write, iclass 37, count 2 2006.201.16:54:36.64#ibcon#wrote, iclass 37, count 2 2006.201.16:54:36.64#ibcon#about to read 3, iclass 37, count 2 2006.201.16:54:36.67#ibcon#read 3, iclass 37, count 2 2006.201.16:54:36.67#ibcon#about to read 4, iclass 37, count 2 2006.201.16:54:36.67#ibcon#read 4, iclass 37, count 2 2006.201.16:54:36.67#ibcon#about to read 5, iclass 37, count 2 2006.201.16:54:36.67#ibcon#read 5, iclass 37, count 2 2006.201.16:54:36.67#ibcon#about to read 6, iclass 37, count 2 2006.201.16:54:36.67#ibcon#read 6, iclass 37, count 2 2006.201.16:54:36.67#ibcon#end of sib2, iclass 37, count 2 2006.201.16:54:36.67#ibcon#*after write, iclass 37, count 2 2006.201.16:54:36.67#ibcon#*before return 0, iclass 37, count 2 2006.201.16:54:36.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:36.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:36.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.16:54:36.67#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:36.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:36.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:36.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:36.79#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:54:36.79#ibcon#first serial, iclass 37, count 0 2006.201.16:54:36.79#ibcon#enter sib2, iclass 37, count 0 2006.201.16:54:36.79#ibcon#flushed, iclass 37, count 0 2006.201.16:54:36.79#ibcon#about to write, iclass 37, count 0 2006.201.16:54:36.79#ibcon#wrote, iclass 37, count 0 2006.201.16:54:36.79#ibcon#about to read 3, iclass 37, count 0 2006.201.16:54:36.81#ibcon#read 3, iclass 37, count 0 2006.201.16:54:36.81#ibcon#about to read 4, iclass 37, count 0 2006.201.16:54:36.81#ibcon#read 4, iclass 37, count 0 2006.201.16:54:36.81#ibcon#about to read 5, iclass 37, count 0 2006.201.16:54:36.81#ibcon#read 5, iclass 37, count 0 2006.201.16:54:36.81#ibcon#about to read 6, iclass 37, count 0 2006.201.16:54:36.81#ibcon#read 6, iclass 37, count 0 2006.201.16:54:36.81#ibcon#end of sib2, iclass 37, count 0 2006.201.16:54:36.81#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:54:36.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:54:36.81#ibcon#[25=USB\r\n] 2006.201.16:54:36.81#ibcon#*before write, iclass 37, count 0 2006.201.16:54:36.81#ibcon#enter sib2, iclass 37, count 0 2006.201.16:54:36.81#ibcon#flushed, iclass 37, count 0 2006.201.16:54:36.81#ibcon#about to write, iclass 37, count 0 2006.201.16:54:36.81#ibcon#wrote, iclass 37, count 0 2006.201.16:54:36.81#ibcon#about to read 3, iclass 37, count 0 2006.201.16:54:36.84#ibcon#read 3, iclass 37, count 0 2006.201.16:54:36.84#ibcon#about to read 4, iclass 37, count 0 2006.201.16:54:36.84#ibcon#read 4, iclass 37, count 0 2006.201.16:54:36.84#ibcon#about to read 5, iclass 37, count 0 2006.201.16:54:36.84#ibcon#read 5, iclass 37, count 0 2006.201.16:54:36.84#ibcon#about to read 6, iclass 37, count 0 2006.201.16:54:36.84#ibcon#read 6, iclass 37, count 0 2006.201.16:54:36.84#ibcon#end of sib2, iclass 37, count 0 2006.201.16:54:36.84#ibcon#*after write, iclass 37, count 0 2006.201.16:54:36.84#ibcon#*before return 0, iclass 37, count 0 2006.201.16:54:36.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:36.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:36.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:54:36.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:54:36.84$vck44/valo=4,624.99 2006.201.16:54:36.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.16:54:36.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.16:54:36.84#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:36.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:36.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:36.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:36.84#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:54:36.84#ibcon#first serial, iclass 39, count 0 2006.201.16:54:36.84#ibcon#enter sib2, iclass 39, count 0 2006.201.16:54:36.84#ibcon#flushed, iclass 39, count 0 2006.201.16:54:36.84#ibcon#about to write, iclass 39, count 0 2006.201.16:54:36.84#ibcon#wrote, iclass 39, count 0 2006.201.16:54:36.84#ibcon#about to read 3, iclass 39, count 0 2006.201.16:54:36.86#ibcon#read 3, iclass 39, count 0 2006.201.16:54:36.86#ibcon#about to read 4, iclass 39, count 0 2006.201.16:54:36.86#ibcon#read 4, iclass 39, count 0 2006.201.16:54:36.86#ibcon#about to read 5, iclass 39, count 0 2006.201.16:54:36.86#ibcon#read 5, iclass 39, count 0 2006.201.16:54:36.86#ibcon#about to read 6, iclass 39, count 0 2006.201.16:54:36.86#ibcon#read 6, iclass 39, count 0 2006.201.16:54:36.86#ibcon#end of sib2, iclass 39, count 0 2006.201.16:54:36.86#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:54:36.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:54:36.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:54:36.86#ibcon#*before write, iclass 39, count 0 2006.201.16:54:36.86#ibcon#enter sib2, iclass 39, count 0 2006.201.16:54:36.86#ibcon#flushed, iclass 39, count 0 2006.201.16:54:36.86#ibcon#about to write, iclass 39, count 0 2006.201.16:54:36.86#ibcon#wrote, iclass 39, count 0 2006.201.16:54:36.86#ibcon#about to read 3, iclass 39, count 0 2006.201.16:54:36.91#ibcon#read 3, iclass 39, count 0 2006.201.16:54:36.91#ibcon#about to read 4, iclass 39, count 0 2006.201.16:54:36.91#ibcon#read 4, iclass 39, count 0 2006.201.16:54:36.91#ibcon#about to read 5, iclass 39, count 0 2006.201.16:54:36.91#ibcon#read 5, iclass 39, count 0 2006.201.16:54:36.91#ibcon#about to read 6, iclass 39, count 0 2006.201.16:54:36.91#ibcon#read 6, iclass 39, count 0 2006.201.16:54:36.91#ibcon#end of sib2, iclass 39, count 0 2006.201.16:54:36.91#ibcon#*after write, iclass 39, count 0 2006.201.16:54:36.91#ibcon#*before return 0, iclass 39, count 0 2006.201.16:54:36.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:36.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:36.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:54:36.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:54:36.91$vck44/va=4,7 2006.201.16:54:36.91#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.16:54:36.91#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.16:54:36.91#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:36.91#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:36.96#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:36.96#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:36.96#ibcon#enter wrdev, iclass 2, count 2 2006.201.16:54:36.96#ibcon#first serial, iclass 2, count 2 2006.201.16:54:36.96#ibcon#enter sib2, iclass 2, count 2 2006.201.16:54:36.96#ibcon#flushed, iclass 2, count 2 2006.201.16:54:36.96#ibcon#about to write, iclass 2, count 2 2006.201.16:54:36.96#ibcon#wrote, iclass 2, count 2 2006.201.16:54:36.96#ibcon#about to read 3, iclass 2, count 2 2006.201.16:54:36.98#ibcon#read 3, iclass 2, count 2 2006.201.16:54:36.98#ibcon#about to read 4, iclass 2, count 2 2006.201.16:54:36.98#ibcon#read 4, iclass 2, count 2 2006.201.16:54:36.98#ibcon#about to read 5, iclass 2, count 2 2006.201.16:54:36.98#ibcon#read 5, iclass 2, count 2 2006.201.16:54:36.98#ibcon#about to read 6, iclass 2, count 2 2006.201.16:54:36.98#ibcon#read 6, iclass 2, count 2 2006.201.16:54:36.98#ibcon#end of sib2, iclass 2, count 2 2006.201.16:54:36.98#ibcon#*mode == 0, iclass 2, count 2 2006.201.16:54:36.98#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.16:54:36.98#ibcon#[25=AT04-07\r\n] 2006.201.16:54:36.98#ibcon#*before write, iclass 2, count 2 2006.201.16:54:36.98#ibcon#enter sib2, iclass 2, count 2 2006.201.16:54:36.98#ibcon#flushed, iclass 2, count 2 2006.201.16:54:36.98#ibcon#about to write, iclass 2, count 2 2006.201.16:54:36.98#ibcon#wrote, iclass 2, count 2 2006.201.16:54:36.98#ibcon#about to read 3, iclass 2, count 2 2006.201.16:54:37.01#ibcon#read 3, iclass 2, count 2 2006.201.16:54:37.01#ibcon#about to read 4, iclass 2, count 2 2006.201.16:54:37.01#ibcon#read 4, iclass 2, count 2 2006.201.16:54:37.01#ibcon#about to read 5, iclass 2, count 2 2006.201.16:54:37.01#ibcon#read 5, iclass 2, count 2 2006.201.16:54:37.01#ibcon#about to read 6, iclass 2, count 2 2006.201.16:54:37.01#ibcon#read 6, iclass 2, count 2 2006.201.16:54:37.01#ibcon#end of sib2, iclass 2, count 2 2006.201.16:54:37.01#ibcon#*after write, iclass 2, count 2 2006.201.16:54:37.01#ibcon#*before return 0, iclass 2, count 2 2006.201.16:54:37.01#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:37.01#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:37.01#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.16:54:37.01#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:37.01#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:37.13#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:37.13#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:37.13#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:54:37.13#ibcon#first serial, iclass 2, count 0 2006.201.16:54:37.13#ibcon#enter sib2, iclass 2, count 0 2006.201.16:54:37.13#ibcon#flushed, iclass 2, count 0 2006.201.16:54:37.13#ibcon#about to write, iclass 2, count 0 2006.201.16:54:37.13#ibcon#wrote, iclass 2, count 0 2006.201.16:54:37.13#ibcon#about to read 3, iclass 2, count 0 2006.201.16:54:37.15#ibcon#read 3, iclass 2, count 0 2006.201.16:54:37.15#ibcon#about to read 4, iclass 2, count 0 2006.201.16:54:37.15#ibcon#read 4, iclass 2, count 0 2006.201.16:54:37.15#ibcon#about to read 5, iclass 2, count 0 2006.201.16:54:37.15#ibcon#read 5, iclass 2, count 0 2006.201.16:54:37.15#ibcon#about to read 6, iclass 2, count 0 2006.201.16:54:37.15#ibcon#read 6, iclass 2, count 0 2006.201.16:54:37.15#ibcon#end of sib2, iclass 2, count 0 2006.201.16:54:37.15#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:54:37.15#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:54:37.15#ibcon#[25=USB\r\n] 2006.201.16:54:37.15#ibcon#*before write, iclass 2, count 0 2006.201.16:54:37.15#ibcon#enter sib2, iclass 2, count 0 2006.201.16:54:37.15#ibcon#flushed, iclass 2, count 0 2006.201.16:54:37.15#ibcon#about to write, iclass 2, count 0 2006.201.16:54:37.15#ibcon#wrote, iclass 2, count 0 2006.201.16:54:37.15#ibcon#about to read 3, iclass 2, count 0 2006.201.16:54:37.18#ibcon#read 3, iclass 2, count 0 2006.201.16:54:37.18#ibcon#about to read 4, iclass 2, count 0 2006.201.16:54:37.18#ibcon#read 4, iclass 2, count 0 2006.201.16:54:37.18#ibcon#about to read 5, iclass 2, count 0 2006.201.16:54:37.18#ibcon#read 5, iclass 2, count 0 2006.201.16:54:37.18#ibcon#about to read 6, iclass 2, count 0 2006.201.16:54:37.18#ibcon#read 6, iclass 2, count 0 2006.201.16:54:37.18#ibcon#end of sib2, iclass 2, count 0 2006.201.16:54:37.18#ibcon#*after write, iclass 2, count 0 2006.201.16:54:37.18#ibcon#*before return 0, iclass 2, count 0 2006.201.16:54:37.18#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:37.18#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:37.18#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:54:37.18#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:54:37.18$vck44/valo=5,734.99 2006.201.16:54:37.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.16:54:37.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.16:54:37.18#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:37.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:37.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:37.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:37.18#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:54:37.18#ibcon#first serial, iclass 5, count 0 2006.201.16:54:37.18#ibcon#enter sib2, iclass 5, count 0 2006.201.16:54:37.18#ibcon#flushed, iclass 5, count 0 2006.201.16:54:37.18#ibcon#about to write, iclass 5, count 0 2006.201.16:54:37.18#ibcon#wrote, iclass 5, count 0 2006.201.16:54:37.18#ibcon#about to read 3, iclass 5, count 0 2006.201.16:54:37.20#ibcon#read 3, iclass 5, count 0 2006.201.16:54:37.20#ibcon#about to read 4, iclass 5, count 0 2006.201.16:54:37.20#ibcon#read 4, iclass 5, count 0 2006.201.16:54:37.20#ibcon#about to read 5, iclass 5, count 0 2006.201.16:54:37.20#ibcon#read 5, iclass 5, count 0 2006.201.16:54:37.20#ibcon#about to read 6, iclass 5, count 0 2006.201.16:54:37.20#ibcon#read 6, iclass 5, count 0 2006.201.16:54:37.20#ibcon#end of sib2, iclass 5, count 0 2006.201.16:54:37.20#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:54:37.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:54:37.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:54:37.20#ibcon#*before write, iclass 5, count 0 2006.201.16:54:37.20#ibcon#enter sib2, iclass 5, count 0 2006.201.16:54:37.20#ibcon#flushed, iclass 5, count 0 2006.201.16:54:37.20#ibcon#about to write, iclass 5, count 0 2006.201.16:54:37.20#ibcon#wrote, iclass 5, count 0 2006.201.16:54:37.20#ibcon#about to read 3, iclass 5, count 0 2006.201.16:54:37.24#ibcon#read 3, iclass 5, count 0 2006.201.16:54:37.24#ibcon#about to read 4, iclass 5, count 0 2006.201.16:54:37.24#ibcon#read 4, iclass 5, count 0 2006.201.16:54:37.24#ibcon#about to read 5, iclass 5, count 0 2006.201.16:54:37.24#ibcon#read 5, iclass 5, count 0 2006.201.16:54:37.24#ibcon#about to read 6, iclass 5, count 0 2006.201.16:54:37.24#ibcon#read 6, iclass 5, count 0 2006.201.16:54:37.24#ibcon#end of sib2, iclass 5, count 0 2006.201.16:54:37.24#ibcon#*after write, iclass 5, count 0 2006.201.16:54:37.24#ibcon#*before return 0, iclass 5, count 0 2006.201.16:54:37.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:37.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:37.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:54:37.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:54:37.24$vck44/va=5,4 2006.201.16:54:37.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.16:54:37.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.16:54:37.24#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:37.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:37.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:37.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:37.30#ibcon#enter wrdev, iclass 7, count 2 2006.201.16:54:37.30#ibcon#first serial, iclass 7, count 2 2006.201.16:54:37.30#ibcon#enter sib2, iclass 7, count 2 2006.201.16:54:37.30#ibcon#flushed, iclass 7, count 2 2006.201.16:54:37.30#ibcon#about to write, iclass 7, count 2 2006.201.16:54:37.30#ibcon#wrote, iclass 7, count 2 2006.201.16:54:37.30#ibcon#about to read 3, iclass 7, count 2 2006.201.16:54:37.32#ibcon#read 3, iclass 7, count 2 2006.201.16:54:37.32#ibcon#about to read 4, iclass 7, count 2 2006.201.16:54:37.32#ibcon#read 4, iclass 7, count 2 2006.201.16:54:37.32#ibcon#about to read 5, iclass 7, count 2 2006.201.16:54:37.32#ibcon#read 5, iclass 7, count 2 2006.201.16:54:37.32#ibcon#about to read 6, iclass 7, count 2 2006.201.16:54:37.32#ibcon#read 6, iclass 7, count 2 2006.201.16:54:37.32#ibcon#end of sib2, iclass 7, count 2 2006.201.16:54:37.32#ibcon#*mode == 0, iclass 7, count 2 2006.201.16:54:37.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.16:54:37.32#ibcon#[25=AT05-04\r\n] 2006.201.16:54:37.32#ibcon#*before write, iclass 7, count 2 2006.201.16:54:37.32#ibcon#enter sib2, iclass 7, count 2 2006.201.16:54:37.32#ibcon#flushed, iclass 7, count 2 2006.201.16:54:37.32#ibcon#about to write, iclass 7, count 2 2006.201.16:54:37.32#ibcon#wrote, iclass 7, count 2 2006.201.16:54:37.32#ibcon#about to read 3, iclass 7, count 2 2006.201.16:54:37.35#ibcon#read 3, iclass 7, count 2 2006.201.16:54:37.35#ibcon#about to read 4, iclass 7, count 2 2006.201.16:54:37.35#ibcon#read 4, iclass 7, count 2 2006.201.16:54:37.35#ibcon#about to read 5, iclass 7, count 2 2006.201.16:54:37.35#ibcon#read 5, iclass 7, count 2 2006.201.16:54:37.35#ibcon#about to read 6, iclass 7, count 2 2006.201.16:54:37.35#ibcon#read 6, iclass 7, count 2 2006.201.16:54:37.35#ibcon#end of sib2, iclass 7, count 2 2006.201.16:54:37.35#ibcon#*after write, iclass 7, count 2 2006.201.16:54:37.35#ibcon#*before return 0, iclass 7, count 2 2006.201.16:54:37.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:37.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:37.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.16:54:37.35#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:37.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:37.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:37.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:37.47#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:54:37.47#ibcon#first serial, iclass 7, count 0 2006.201.16:54:37.47#ibcon#enter sib2, iclass 7, count 0 2006.201.16:54:37.47#ibcon#flushed, iclass 7, count 0 2006.201.16:54:37.47#ibcon#about to write, iclass 7, count 0 2006.201.16:54:37.47#ibcon#wrote, iclass 7, count 0 2006.201.16:54:37.47#ibcon#about to read 3, iclass 7, count 0 2006.201.16:54:37.49#ibcon#read 3, iclass 7, count 0 2006.201.16:54:37.49#ibcon#about to read 4, iclass 7, count 0 2006.201.16:54:37.49#ibcon#read 4, iclass 7, count 0 2006.201.16:54:37.49#ibcon#about to read 5, iclass 7, count 0 2006.201.16:54:37.49#ibcon#read 5, iclass 7, count 0 2006.201.16:54:37.49#ibcon#about to read 6, iclass 7, count 0 2006.201.16:54:37.49#ibcon#read 6, iclass 7, count 0 2006.201.16:54:37.49#ibcon#end of sib2, iclass 7, count 0 2006.201.16:54:37.49#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:54:37.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:54:37.49#ibcon#[25=USB\r\n] 2006.201.16:54:37.49#ibcon#*before write, iclass 7, count 0 2006.201.16:54:37.49#ibcon#enter sib2, iclass 7, count 0 2006.201.16:54:37.49#ibcon#flushed, iclass 7, count 0 2006.201.16:54:37.49#ibcon#about to write, iclass 7, count 0 2006.201.16:54:37.49#ibcon#wrote, iclass 7, count 0 2006.201.16:54:37.49#ibcon#about to read 3, iclass 7, count 0 2006.201.16:54:37.52#ibcon#read 3, iclass 7, count 0 2006.201.16:54:37.52#ibcon#about to read 4, iclass 7, count 0 2006.201.16:54:37.52#ibcon#read 4, iclass 7, count 0 2006.201.16:54:37.52#ibcon#about to read 5, iclass 7, count 0 2006.201.16:54:37.52#ibcon#read 5, iclass 7, count 0 2006.201.16:54:37.52#ibcon#about to read 6, iclass 7, count 0 2006.201.16:54:37.52#ibcon#read 6, iclass 7, count 0 2006.201.16:54:37.52#ibcon#end of sib2, iclass 7, count 0 2006.201.16:54:37.52#ibcon#*after write, iclass 7, count 0 2006.201.16:54:37.52#ibcon#*before return 0, iclass 7, count 0 2006.201.16:54:37.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:37.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:37.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:54:37.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:54:37.52$vck44/valo=6,814.99 2006.201.16:54:37.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.16:54:37.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.16:54:37.52#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:37.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:37.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:37.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:37.52#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:54:37.52#ibcon#first serial, iclass 11, count 0 2006.201.16:54:37.52#ibcon#enter sib2, iclass 11, count 0 2006.201.16:54:37.52#ibcon#flushed, iclass 11, count 0 2006.201.16:54:37.52#ibcon#about to write, iclass 11, count 0 2006.201.16:54:37.52#ibcon#wrote, iclass 11, count 0 2006.201.16:54:37.52#ibcon#about to read 3, iclass 11, count 0 2006.201.16:54:37.54#ibcon#read 3, iclass 11, count 0 2006.201.16:54:37.54#ibcon#about to read 4, iclass 11, count 0 2006.201.16:54:37.54#ibcon#read 4, iclass 11, count 0 2006.201.16:54:37.54#ibcon#about to read 5, iclass 11, count 0 2006.201.16:54:37.54#ibcon#read 5, iclass 11, count 0 2006.201.16:54:37.54#ibcon#about to read 6, iclass 11, count 0 2006.201.16:54:37.54#ibcon#read 6, iclass 11, count 0 2006.201.16:54:37.54#ibcon#end of sib2, iclass 11, count 0 2006.201.16:54:37.54#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:54:37.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:54:37.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:54:37.54#ibcon#*before write, iclass 11, count 0 2006.201.16:54:37.54#ibcon#enter sib2, iclass 11, count 0 2006.201.16:54:37.54#ibcon#flushed, iclass 11, count 0 2006.201.16:54:37.54#ibcon#about to write, iclass 11, count 0 2006.201.16:54:37.54#ibcon#wrote, iclass 11, count 0 2006.201.16:54:37.54#ibcon#about to read 3, iclass 11, count 0 2006.201.16:54:37.58#ibcon#read 3, iclass 11, count 0 2006.201.16:54:37.58#ibcon#about to read 4, iclass 11, count 0 2006.201.16:54:37.58#ibcon#read 4, iclass 11, count 0 2006.201.16:54:37.58#ibcon#about to read 5, iclass 11, count 0 2006.201.16:54:37.58#ibcon#read 5, iclass 11, count 0 2006.201.16:54:37.58#ibcon#about to read 6, iclass 11, count 0 2006.201.16:54:37.58#ibcon#read 6, iclass 11, count 0 2006.201.16:54:37.58#ibcon#end of sib2, iclass 11, count 0 2006.201.16:54:37.58#ibcon#*after write, iclass 11, count 0 2006.201.16:54:37.58#ibcon#*before return 0, iclass 11, count 0 2006.201.16:54:37.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:37.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:37.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:54:37.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:54:37.58$vck44/va=6,5 2006.201.16:54:37.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.16:54:37.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.16:54:37.58#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:37.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:37.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:37.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:37.64#ibcon#enter wrdev, iclass 13, count 2 2006.201.16:54:37.64#ibcon#first serial, iclass 13, count 2 2006.201.16:54:37.64#ibcon#enter sib2, iclass 13, count 2 2006.201.16:54:37.64#ibcon#flushed, iclass 13, count 2 2006.201.16:54:37.64#ibcon#about to write, iclass 13, count 2 2006.201.16:54:37.64#ibcon#wrote, iclass 13, count 2 2006.201.16:54:37.64#ibcon#about to read 3, iclass 13, count 2 2006.201.16:54:37.66#ibcon#read 3, iclass 13, count 2 2006.201.16:54:37.66#ibcon#about to read 4, iclass 13, count 2 2006.201.16:54:37.66#ibcon#read 4, iclass 13, count 2 2006.201.16:54:37.66#ibcon#about to read 5, iclass 13, count 2 2006.201.16:54:37.66#ibcon#read 5, iclass 13, count 2 2006.201.16:54:37.66#ibcon#about to read 6, iclass 13, count 2 2006.201.16:54:37.66#ibcon#read 6, iclass 13, count 2 2006.201.16:54:37.66#ibcon#end of sib2, iclass 13, count 2 2006.201.16:54:37.66#ibcon#*mode == 0, iclass 13, count 2 2006.201.16:54:37.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.16:54:37.66#ibcon#[25=AT06-05\r\n] 2006.201.16:54:37.66#ibcon#*before write, iclass 13, count 2 2006.201.16:54:37.66#ibcon#enter sib2, iclass 13, count 2 2006.201.16:54:37.66#ibcon#flushed, iclass 13, count 2 2006.201.16:54:37.66#ibcon#about to write, iclass 13, count 2 2006.201.16:54:37.66#ibcon#wrote, iclass 13, count 2 2006.201.16:54:37.66#ibcon#about to read 3, iclass 13, count 2 2006.201.16:54:37.69#ibcon#read 3, iclass 13, count 2 2006.201.16:54:37.69#ibcon#about to read 4, iclass 13, count 2 2006.201.16:54:37.69#ibcon#read 4, iclass 13, count 2 2006.201.16:54:37.69#ibcon#about to read 5, iclass 13, count 2 2006.201.16:54:37.69#ibcon#read 5, iclass 13, count 2 2006.201.16:54:37.69#ibcon#about to read 6, iclass 13, count 2 2006.201.16:54:37.69#ibcon#read 6, iclass 13, count 2 2006.201.16:54:37.69#ibcon#end of sib2, iclass 13, count 2 2006.201.16:54:37.69#ibcon#*after write, iclass 13, count 2 2006.201.16:54:37.69#ibcon#*before return 0, iclass 13, count 2 2006.201.16:54:37.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:37.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:37.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.16:54:37.69#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:37.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:37.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:37.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:37.81#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:54:37.81#ibcon#first serial, iclass 13, count 0 2006.201.16:54:37.81#ibcon#enter sib2, iclass 13, count 0 2006.201.16:54:37.81#ibcon#flushed, iclass 13, count 0 2006.201.16:54:37.81#ibcon#about to write, iclass 13, count 0 2006.201.16:54:37.81#ibcon#wrote, iclass 13, count 0 2006.201.16:54:37.81#ibcon#about to read 3, iclass 13, count 0 2006.201.16:54:37.83#ibcon#read 3, iclass 13, count 0 2006.201.16:54:37.83#ibcon#about to read 4, iclass 13, count 0 2006.201.16:54:37.83#ibcon#read 4, iclass 13, count 0 2006.201.16:54:37.83#ibcon#about to read 5, iclass 13, count 0 2006.201.16:54:37.83#ibcon#read 5, iclass 13, count 0 2006.201.16:54:37.83#ibcon#about to read 6, iclass 13, count 0 2006.201.16:54:37.83#ibcon#read 6, iclass 13, count 0 2006.201.16:54:37.83#ibcon#end of sib2, iclass 13, count 0 2006.201.16:54:37.83#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:54:37.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:54:37.83#ibcon#[25=USB\r\n] 2006.201.16:54:37.83#ibcon#*before write, iclass 13, count 0 2006.201.16:54:37.83#ibcon#enter sib2, iclass 13, count 0 2006.201.16:54:37.83#ibcon#flushed, iclass 13, count 0 2006.201.16:54:37.83#ibcon#about to write, iclass 13, count 0 2006.201.16:54:37.83#ibcon#wrote, iclass 13, count 0 2006.201.16:54:37.83#ibcon#about to read 3, iclass 13, count 0 2006.201.16:54:37.86#ibcon#read 3, iclass 13, count 0 2006.201.16:54:37.86#ibcon#about to read 4, iclass 13, count 0 2006.201.16:54:37.86#ibcon#read 4, iclass 13, count 0 2006.201.16:54:37.86#ibcon#about to read 5, iclass 13, count 0 2006.201.16:54:37.86#ibcon#read 5, iclass 13, count 0 2006.201.16:54:37.86#ibcon#about to read 6, iclass 13, count 0 2006.201.16:54:37.86#ibcon#read 6, iclass 13, count 0 2006.201.16:54:37.86#ibcon#end of sib2, iclass 13, count 0 2006.201.16:54:37.86#ibcon#*after write, iclass 13, count 0 2006.201.16:54:37.86#ibcon#*before return 0, iclass 13, count 0 2006.201.16:54:37.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:37.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:37.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:54:37.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:54:37.86$vck44/valo=7,864.99 2006.201.16:54:37.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.16:54:37.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.16:54:37.86#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:37.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:37.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:37.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:37.86#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:54:37.86#ibcon#first serial, iclass 15, count 0 2006.201.16:54:37.86#ibcon#enter sib2, iclass 15, count 0 2006.201.16:54:37.86#ibcon#flushed, iclass 15, count 0 2006.201.16:54:37.86#ibcon#about to write, iclass 15, count 0 2006.201.16:54:37.86#ibcon#wrote, iclass 15, count 0 2006.201.16:54:37.86#ibcon#about to read 3, iclass 15, count 0 2006.201.16:54:37.88#ibcon#read 3, iclass 15, count 0 2006.201.16:54:37.88#ibcon#about to read 4, iclass 15, count 0 2006.201.16:54:37.88#ibcon#read 4, iclass 15, count 0 2006.201.16:54:37.88#ibcon#about to read 5, iclass 15, count 0 2006.201.16:54:37.88#ibcon#read 5, iclass 15, count 0 2006.201.16:54:37.88#ibcon#about to read 6, iclass 15, count 0 2006.201.16:54:37.88#ibcon#read 6, iclass 15, count 0 2006.201.16:54:37.88#ibcon#end of sib2, iclass 15, count 0 2006.201.16:54:37.88#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:54:37.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:54:37.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:54:37.88#ibcon#*before write, iclass 15, count 0 2006.201.16:54:37.88#ibcon#enter sib2, iclass 15, count 0 2006.201.16:54:37.88#ibcon#flushed, iclass 15, count 0 2006.201.16:54:37.88#ibcon#about to write, iclass 15, count 0 2006.201.16:54:37.88#ibcon#wrote, iclass 15, count 0 2006.201.16:54:37.88#ibcon#about to read 3, iclass 15, count 0 2006.201.16:54:37.92#ibcon#read 3, iclass 15, count 0 2006.201.16:54:37.92#ibcon#about to read 4, iclass 15, count 0 2006.201.16:54:37.92#ibcon#read 4, iclass 15, count 0 2006.201.16:54:37.92#ibcon#about to read 5, iclass 15, count 0 2006.201.16:54:37.92#ibcon#read 5, iclass 15, count 0 2006.201.16:54:37.92#ibcon#about to read 6, iclass 15, count 0 2006.201.16:54:37.92#ibcon#read 6, iclass 15, count 0 2006.201.16:54:37.92#ibcon#end of sib2, iclass 15, count 0 2006.201.16:54:37.92#ibcon#*after write, iclass 15, count 0 2006.201.16:54:37.92#ibcon#*before return 0, iclass 15, count 0 2006.201.16:54:37.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:37.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:37.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:54:37.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:54:37.92$vck44/va=7,5 2006.201.16:54:37.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.16:54:37.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.16:54:37.92#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:37.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:37.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:37.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:37.98#ibcon#enter wrdev, iclass 17, count 2 2006.201.16:54:37.98#ibcon#first serial, iclass 17, count 2 2006.201.16:54:37.98#ibcon#enter sib2, iclass 17, count 2 2006.201.16:54:37.98#ibcon#flushed, iclass 17, count 2 2006.201.16:54:37.98#ibcon#about to write, iclass 17, count 2 2006.201.16:54:37.98#ibcon#wrote, iclass 17, count 2 2006.201.16:54:37.98#ibcon#about to read 3, iclass 17, count 2 2006.201.16:54:38.00#ibcon#read 3, iclass 17, count 2 2006.201.16:54:38.00#ibcon#about to read 4, iclass 17, count 2 2006.201.16:54:38.00#ibcon#read 4, iclass 17, count 2 2006.201.16:54:38.00#ibcon#about to read 5, iclass 17, count 2 2006.201.16:54:38.00#ibcon#read 5, iclass 17, count 2 2006.201.16:54:38.00#ibcon#about to read 6, iclass 17, count 2 2006.201.16:54:38.00#ibcon#read 6, iclass 17, count 2 2006.201.16:54:38.00#ibcon#end of sib2, iclass 17, count 2 2006.201.16:54:38.00#ibcon#*mode == 0, iclass 17, count 2 2006.201.16:54:38.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.16:54:38.00#ibcon#[25=AT07-05\r\n] 2006.201.16:54:38.00#ibcon#*before write, iclass 17, count 2 2006.201.16:54:38.00#ibcon#enter sib2, iclass 17, count 2 2006.201.16:54:38.00#ibcon#flushed, iclass 17, count 2 2006.201.16:54:38.00#ibcon#about to write, iclass 17, count 2 2006.201.16:54:38.00#ibcon#wrote, iclass 17, count 2 2006.201.16:54:38.00#ibcon#about to read 3, iclass 17, count 2 2006.201.16:54:38.03#ibcon#read 3, iclass 17, count 2 2006.201.16:54:38.03#ibcon#about to read 4, iclass 17, count 2 2006.201.16:54:38.03#ibcon#read 4, iclass 17, count 2 2006.201.16:54:38.03#ibcon#about to read 5, iclass 17, count 2 2006.201.16:54:38.03#ibcon#read 5, iclass 17, count 2 2006.201.16:54:38.03#ibcon#about to read 6, iclass 17, count 2 2006.201.16:54:38.03#ibcon#read 6, iclass 17, count 2 2006.201.16:54:38.03#ibcon#end of sib2, iclass 17, count 2 2006.201.16:54:38.03#ibcon#*after write, iclass 17, count 2 2006.201.16:54:38.03#ibcon#*before return 0, iclass 17, count 2 2006.201.16:54:38.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:38.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:38.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.16:54:38.03#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:38.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:38.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:38.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:38.15#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:54:38.15#ibcon#first serial, iclass 17, count 0 2006.201.16:54:38.15#ibcon#enter sib2, iclass 17, count 0 2006.201.16:54:38.15#ibcon#flushed, iclass 17, count 0 2006.201.16:54:38.15#ibcon#about to write, iclass 17, count 0 2006.201.16:54:38.15#ibcon#wrote, iclass 17, count 0 2006.201.16:54:38.15#ibcon#about to read 3, iclass 17, count 0 2006.201.16:54:38.17#ibcon#read 3, iclass 17, count 0 2006.201.16:54:38.17#ibcon#about to read 4, iclass 17, count 0 2006.201.16:54:38.17#ibcon#read 4, iclass 17, count 0 2006.201.16:54:38.17#ibcon#about to read 5, iclass 17, count 0 2006.201.16:54:38.17#ibcon#read 5, iclass 17, count 0 2006.201.16:54:38.17#ibcon#about to read 6, iclass 17, count 0 2006.201.16:54:38.17#ibcon#read 6, iclass 17, count 0 2006.201.16:54:38.17#ibcon#end of sib2, iclass 17, count 0 2006.201.16:54:38.17#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:54:38.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:54:38.17#ibcon#[25=USB\r\n] 2006.201.16:54:38.17#ibcon#*before write, iclass 17, count 0 2006.201.16:54:38.17#ibcon#enter sib2, iclass 17, count 0 2006.201.16:54:38.17#ibcon#flushed, iclass 17, count 0 2006.201.16:54:38.17#ibcon#about to write, iclass 17, count 0 2006.201.16:54:38.17#ibcon#wrote, iclass 17, count 0 2006.201.16:54:38.17#ibcon#about to read 3, iclass 17, count 0 2006.201.16:54:38.20#ibcon#read 3, iclass 17, count 0 2006.201.16:54:38.20#ibcon#about to read 4, iclass 17, count 0 2006.201.16:54:38.20#ibcon#read 4, iclass 17, count 0 2006.201.16:54:38.20#ibcon#about to read 5, iclass 17, count 0 2006.201.16:54:38.20#ibcon#read 5, iclass 17, count 0 2006.201.16:54:38.20#ibcon#about to read 6, iclass 17, count 0 2006.201.16:54:38.20#ibcon#read 6, iclass 17, count 0 2006.201.16:54:38.20#ibcon#end of sib2, iclass 17, count 0 2006.201.16:54:38.20#ibcon#*after write, iclass 17, count 0 2006.201.16:54:38.20#ibcon#*before return 0, iclass 17, count 0 2006.201.16:54:38.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:38.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:38.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:54:38.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:54:38.20$vck44/valo=8,884.99 2006.201.16:54:38.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.16:54:38.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.16:54:38.20#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:38.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:54:38.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:54:38.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:54:38.20#ibcon#enter wrdev, iclass 19, count 0 2006.201.16:54:38.20#ibcon#first serial, iclass 19, count 0 2006.201.16:54:38.20#ibcon#enter sib2, iclass 19, count 0 2006.201.16:54:38.20#ibcon#flushed, iclass 19, count 0 2006.201.16:54:38.20#ibcon#about to write, iclass 19, count 0 2006.201.16:54:38.20#ibcon#wrote, iclass 19, count 0 2006.201.16:54:38.20#ibcon#about to read 3, iclass 19, count 0 2006.201.16:54:38.22#ibcon#read 3, iclass 19, count 0 2006.201.16:54:38.22#ibcon#about to read 4, iclass 19, count 0 2006.201.16:54:38.22#ibcon#read 4, iclass 19, count 0 2006.201.16:54:38.22#ibcon#about to read 5, iclass 19, count 0 2006.201.16:54:38.22#ibcon#read 5, iclass 19, count 0 2006.201.16:54:38.22#ibcon#about to read 6, iclass 19, count 0 2006.201.16:54:38.22#ibcon#read 6, iclass 19, count 0 2006.201.16:54:38.22#ibcon#end of sib2, iclass 19, count 0 2006.201.16:54:38.22#ibcon#*mode == 0, iclass 19, count 0 2006.201.16:54:38.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.16:54:38.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:54:38.22#ibcon#*before write, iclass 19, count 0 2006.201.16:54:38.22#ibcon#enter sib2, iclass 19, count 0 2006.201.16:54:38.22#ibcon#flushed, iclass 19, count 0 2006.201.16:54:38.22#ibcon#about to write, iclass 19, count 0 2006.201.16:54:38.22#ibcon#wrote, iclass 19, count 0 2006.201.16:54:38.22#ibcon#about to read 3, iclass 19, count 0 2006.201.16:54:38.26#ibcon#read 3, iclass 19, count 0 2006.201.16:54:38.26#ibcon#about to read 4, iclass 19, count 0 2006.201.16:54:38.26#ibcon#read 4, iclass 19, count 0 2006.201.16:54:38.26#ibcon#about to read 5, iclass 19, count 0 2006.201.16:54:38.26#ibcon#read 5, iclass 19, count 0 2006.201.16:54:38.26#ibcon#about to read 6, iclass 19, count 0 2006.201.16:54:38.26#ibcon#read 6, iclass 19, count 0 2006.201.16:54:38.26#ibcon#end of sib2, iclass 19, count 0 2006.201.16:54:38.26#ibcon#*after write, iclass 19, count 0 2006.201.16:54:38.26#ibcon#*before return 0, iclass 19, count 0 2006.201.16:54:38.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:54:38.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.16:54:38.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.16:54:38.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.16:54:38.26$vck44/va=8,4 2006.201.16:54:38.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.16:54:38.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.16:54:38.26#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:38.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:54:38.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:54:38.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:54:38.32#ibcon#enter wrdev, iclass 21, count 2 2006.201.16:54:38.32#ibcon#first serial, iclass 21, count 2 2006.201.16:54:38.32#ibcon#enter sib2, iclass 21, count 2 2006.201.16:54:38.32#ibcon#flushed, iclass 21, count 2 2006.201.16:54:38.32#ibcon#about to write, iclass 21, count 2 2006.201.16:54:38.32#ibcon#wrote, iclass 21, count 2 2006.201.16:54:38.32#ibcon#about to read 3, iclass 21, count 2 2006.201.16:54:38.34#ibcon#read 3, iclass 21, count 2 2006.201.16:54:38.34#ibcon#about to read 4, iclass 21, count 2 2006.201.16:54:38.34#ibcon#read 4, iclass 21, count 2 2006.201.16:54:38.34#ibcon#about to read 5, iclass 21, count 2 2006.201.16:54:38.34#ibcon#read 5, iclass 21, count 2 2006.201.16:54:38.34#ibcon#about to read 6, iclass 21, count 2 2006.201.16:54:38.34#ibcon#read 6, iclass 21, count 2 2006.201.16:54:38.34#ibcon#end of sib2, iclass 21, count 2 2006.201.16:54:38.34#ibcon#*mode == 0, iclass 21, count 2 2006.201.16:54:38.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.16:54:38.34#ibcon#[25=AT08-04\r\n] 2006.201.16:54:38.34#ibcon#*before write, iclass 21, count 2 2006.201.16:54:38.34#ibcon#enter sib2, iclass 21, count 2 2006.201.16:54:38.34#ibcon#flushed, iclass 21, count 2 2006.201.16:54:38.34#ibcon#about to write, iclass 21, count 2 2006.201.16:54:38.34#ibcon#wrote, iclass 21, count 2 2006.201.16:54:38.34#ibcon#about to read 3, iclass 21, count 2 2006.201.16:54:38.37#ibcon#read 3, iclass 21, count 2 2006.201.16:54:38.37#ibcon#about to read 4, iclass 21, count 2 2006.201.16:54:38.37#ibcon#read 4, iclass 21, count 2 2006.201.16:54:38.37#ibcon#about to read 5, iclass 21, count 2 2006.201.16:54:38.37#ibcon#read 5, iclass 21, count 2 2006.201.16:54:38.37#ibcon#about to read 6, iclass 21, count 2 2006.201.16:54:38.37#ibcon#read 6, iclass 21, count 2 2006.201.16:54:38.37#ibcon#end of sib2, iclass 21, count 2 2006.201.16:54:38.37#ibcon#*after write, iclass 21, count 2 2006.201.16:54:38.37#ibcon#*before return 0, iclass 21, count 2 2006.201.16:54:38.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:54:38.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.16:54:38.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.16:54:38.37#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:38.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:54:38.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:54:38.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:54:38.49#ibcon#enter wrdev, iclass 21, count 0 2006.201.16:54:38.49#ibcon#first serial, iclass 21, count 0 2006.201.16:54:38.49#ibcon#enter sib2, iclass 21, count 0 2006.201.16:54:38.49#ibcon#flushed, iclass 21, count 0 2006.201.16:54:38.49#ibcon#about to write, iclass 21, count 0 2006.201.16:54:38.49#ibcon#wrote, iclass 21, count 0 2006.201.16:54:38.49#ibcon#about to read 3, iclass 21, count 0 2006.201.16:54:38.51#ibcon#read 3, iclass 21, count 0 2006.201.16:54:38.51#ibcon#about to read 4, iclass 21, count 0 2006.201.16:54:38.51#ibcon#read 4, iclass 21, count 0 2006.201.16:54:38.51#ibcon#about to read 5, iclass 21, count 0 2006.201.16:54:38.51#ibcon#read 5, iclass 21, count 0 2006.201.16:54:38.51#ibcon#about to read 6, iclass 21, count 0 2006.201.16:54:38.51#ibcon#read 6, iclass 21, count 0 2006.201.16:54:38.51#ibcon#end of sib2, iclass 21, count 0 2006.201.16:54:38.51#ibcon#*mode == 0, iclass 21, count 0 2006.201.16:54:38.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.16:54:38.51#ibcon#[25=USB\r\n] 2006.201.16:54:38.51#ibcon#*before write, iclass 21, count 0 2006.201.16:54:38.51#ibcon#enter sib2, iclass 21, count 0 2006.201.16:54:38.51#ibcon#flushed, iclass 21, count 0 2006.201.16:54:38.51#ibcon#about to write, iclass 21, count 0 2006.201.16:54:38.51#ibcon#wrote, iclass 21, count 0 2006.201.16:54:38.51#ibcon#about to read 3, iclass 21, count 0 2006.201.16:54:38.54#ibcon#read 3, iclass 21, count 0 2006.201.16:54:38.54#ibcon#about to read 4, iclass 21, count 0 2006.201.16:54:38.54#ibcon#read 4, iclass 21, count 0 2006.201.16:54:38.54#ibcon#about to read 5, iclass 21, count 0 2006.201.16:54:38.54#ibcon#read 5, iclass 21, count 0 2006.201.16:54:38.54#ibcon#about to read 6, iclass 21, count 0 2006.201.16:54:38.54#ibcon#read 6, iclass 21, count 0 2006.201.16:54:38.54#ibcon#end of sib2, iclass 21, count 0 2006.201.16:54:38.54#ibcon#*after write, iclass 21, count 0 2006.201.16:54:38.54#ibcon#*before return 0, iclass 21, count 0 2006.201.16:54:38.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:54:38.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.16:54:38.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.16:54:38.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.16:54:38.54$vck44/vblo=1,629.99 2006.201.16:54:38.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.16:54:38.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.16:54:38.54#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:38.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:38.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:38.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:38.54#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:54:38.54#ibcon#first serial, iclass 23, count 0 2006.201.16:54:38.54#ibcon#enter sib2, iclass 23, count 0 2006.201.16:54:38.54#ibcon#flushed, iclass 23, count 0 2006.201.16:54:38.54#ibcon#about to write, iclass 23, count 0 2006.201.16:54:38.54#ibcon#wrote, iclass 23, count 0 2006.201.16:54:38.54#ibcon#about to read 3, iclass 23, count 0 2006.201.16:54:38.56#ibcon#read 3, iclass 23, count 0 2006.201.16:54:38.56#ibcon#about to read 4, iclass 23, count 0 2006.201.16:54:38.56#ibcon#read 4, iclass 23, count 0 2006.201.16:54:38.56#ibcon#about to read 5, iclass 23, count 0 2006.201.16:54:38.56#ibcon#read 5, iclass 23, count 0 2006.201.16:54:38.56#ibcon#about to read 6, iclass 23, count 0 2006.201.16:54:38.56#ibcon#read 6, iclass 23, count 0 2006.201.16:54:38.56#ibcon#end of sib2, iclass 23, count 0 2006.201.16:54:38.56#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:54:38.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:54:38.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:54:38.56#ibcon#*before write, iclass 23, count 0 2006.201.16:54:38.56#ibcon#enter sib2, iclass 23, count 0 2006.201.16:54:38.56#ibcon#flushed, iclass 23, count 0 2006.201.16:54:38.56#ibcon#about to write, iclass 23, count 0 2006.201.16:54:38.56#ibcon#wrote, iclass 23, count 0 2006.201.16:54:38.56#ibcon#about to read 3, iclass 23, count 0 2006.201.16:54:38.60#ibcon#read 3, iclass 23, count 0 2006.201.16:54:38.60#ibcon#about to read 4, iclass 23, count 0 2006.201.16:54:38.60#ibcon#read 4, iclass 23, count 0 2006.201.16:54:38.60#ibcon#about to read 5, iclass 23, count 0 2006.201.16:54:38.60#ibcon#read 5, iclass 23, count 0 2006.201.16:54:38.60#ibcon#about to read 6, iclass 23, count 0 2006.201.16:54:38.60#ibcon#read 6, iclass 23, count 0 2006.201.16:54:38.60#ibcon#end of sib2, iclass 23, count 0 2006.201.16:54:38.60#ibcon#*after write, iclass 23, count 0 2006.201.16:54:38.60#ibcon#*before return 0, iclass 23, count 0 2006.201.16:54:38.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:38.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:38.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:54:38.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:54:38.60$vck44/vb=1,4 2006.201.16:54:38.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.16:54:38.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.16:54:38.60#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:38.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:54:38.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:54:38.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:54:38.60#ibcon#enter wrdev, iclass 25, count 2 2006.201.16:54:38.60#ibcon#first serial, iclass 25, count 2 2006.201.16:54:38.60#ibcon#enter sib2, iclass 25, count 2 2006.201.16:54:38.60#ibcon#flushed, iclass 25, count 2 2006.201.16:54:38.60#ibcon#about to write, iclass 25, count 2 2006.201.16:54:38.60#ibcon#wrote, iclass 25, count 2 2006.201.16:54:38.60#ibcon#about to read 3, iclass 25, count 2 2006.201.16:54:38.62#ibcon#read 3, iclass 25, count 2 2006.201.16:54:38.62#ibcon#about to read 4, iclass 25, count 2 2006.201.16:54:38.62#ibcon#read 4, iclass 25, count 2 2006.201.16:54:38.62#ibcon#about to read 5, iclass 25, count 2 2006.201.16:54:38.62#ibcon#read 5, iclass 25, count 2 2006.201.16:54:38.62#ibcon#about to read 6, iclass 25, count 2 2006.201.16:54:38.62#ibcon#read 6, iclass 25, count 2 2006.201.16:54:38.62#ibcon#end of sib2, iclass 25, count 2 2006.201.16:54:38.62#ibcon#*mode == 0, iclass 25, count 2 2006.201.16:54:38.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.16:54:38.62#ibcon#[27=AT01-04\r\n] 2006.201.16:54:38.62#ibcon#*before write, iclass 25, count 2 2006.201.16:54:38.62#ibcon#enter sib2, iclass 25, count 2 2006.201.16:54:38.62#ibcon#flushed, iclass 25, count 2 2006.201.16:54:38.62#ibcon#about to write, iclass 25, count 2 2006.201.16:54:38.62#ibcon#wrote, iclass 25, count 2 2006.201.16:54:38.62#ibcon#about to read 3, iclass 25, count 2 2006.201.16:54:38.65#ibcon#read 3, iclass 25, count 2 2006.201.16:54:38.65#ibcon#about to read 4, iclass 25, count 2 2006.201.16:54:38.65#ibcon#read 4, iclass 25, count 2 2006.201.16:54:38.65#ibcon#about to read 5, iclass 25, count 2 2006.201.16:54:38.65#ibcon#read 5, iclass 25, count 2 2006.201.16:54:38.65#ibcon#about to read 6, iclass 25, count 2 2006.201.16:54:38.65#ibcon#read 6, iclass 25, count 2 2006.201.16:54:38.65#ibcon#end of sib2, iclass 25, count 2 2006.201.16:54:38.65#ibcon#*after write, iclass 25, count 2 2006.201.16:54:38.65#ibcon#*before return 0, iclass 25, count 2 2006.201.16:54:38.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:54:38.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.16:54:38.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.16:54:38.65#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:38.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:54:38.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:54:38.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:54:38.77#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:54:38.77#ibcon#first serial, iclass 25, count 0 2006.201.16:54:38.77#ibcon#enter sib2, iclass 25, count 0 2006.201.16:54:38.77#ibcon#flushed, iclass 25, count 0 2006.201.16:54:38.77#ibcon#about to write, iclass 25, count 0 2006.201.16:54:38.77#ibcon#wrote, iclass 25, count 0 2006.201.16:54:38.77#ibcon#about to read 3, iclass 25, count 0 2006.201.16:54:38.79#ibcon#read 3, iclass 25, count 0 2006.201.16:54:38.79#ibcon#about to read 4, iclass 25, count 0 2006.201.16:54:38.79#ibcon#read 4, iclass 25, count 0 2006.201.16:54:38.79#ibcon#about to read 5, iclass 25, count 0 2006.201.16:54:38.79#ibcon#read 5, iclass 25, count 0 2006.201.16:54:38.79#ibcon#about to read 6, iclass 25, count 0 2006.201.16:54:38.79#ibcon#read 6, iclass 25, count 0 2006.201.16:54:38.79#ibcon#end of sib2, iclass 25, count 0 2006.201.16:54:38.79#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:54:38.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:54:38.79#ibcon#[27=USB\r\n] 2006.201.16:54:38.79#ibcon#*before write, iclass 25, count 0 2006.201.16:54:38.79#ibcon#enter sib2, iclass 25, count 0 2006.201.16:54:38.79#ibcon#flushed, iclass 25, count 0 2006.201.16:54:38.79#ibcon#about to write, iclass 25, count 0 2006.201.16:54:38.79#ibcon#wrote, iclass 25, count 0 2006.201.16:54:38.79#ibcon#about to read 3, iclass 25, count 0 2006.201.16:54:38.82#ibcon#read 3, iclass 25, count 0 2006.201.16:54:38.82#ibcon#about to read 4, iclass 25, count 0 2006.201.16:54:38.82#ibcon#read 4, iclass 25, count 0 2006.201.16:54:38.82#ibcon#about to read 5, iclass 25, count 0 2006.201.16:54:38.82#ibcon#read 5, iclass 25, count 0 2006.201.16:54:38.82#ibcon#about to read 6, iclass 25, count 0 2006.201.16:54:38.82#ibcon#read 6, iclass 25, count 0 2006.201.16:54:38.82#ibcon#end of sib2, iclass 25, count 0 2006.201.16:54:38.82#ibcon#*after write, iclass 25, count 0 2006.201.16:54:38.82#ibcon#*before return 0, iclass 25, count 0 2006.201.16:54:38.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:54:38.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.16:54:38.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:54:38.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:54:38.82$vck44/vblo=2,634.99 2006.201.16:54:38.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.16:54:38.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.16:54:38.82#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:38.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:38.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:38.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:38.82#ibcon#enter wrdev, iclass 27, count 0 2006.201.16:54:38.82#ibcon#first serial, iclass 27, count 0 2006.201.16:54:38.82#ibcon#enter sib2, iclass 27, count 0 2006.201.16:54:38.82#ibcon#flushed, iclass 27, count 0 2006.201.16:54:38.82#ibcon#about to write, iclass 27, count 0 2006.201.16:54:38.82#ibcon#wrote, iclass 27, count 0 2006.201.16:54:38.82#ibcon#about to read 3, iclass 27, count 0 2006.201.16:54:38.84#ibcon#read 3, iclass 27, count 0 2006.201.16:54:38.84#ibcon#about to read 4, iclass 27, count 0 2006.201.16:54:38.84#ibcon#read 4, iclass 27, count 0 2006.201.16:54:38.84#ibcon#about to read 5, iclass 27, count 0 2006.201.16:54:38.84#ibcon#read 5, iclass 27, count 0 2006.201.16:54:38.84#ibcon#about to read 6, iclass 27, count 0 2006.201.16:54:38.84#ibcon#read 6, iclass 27, count 0 2006.201.16:54:38.84#ibcon#end of sib2, iclass 27, count 0 2006.201.16:54:38.84#ibcon#*mode == 0, iclass 27, count 0 2006.201.16:54:38.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.16:54:38.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:54:38.84#ibcon#*before write, iclass 27, count 0 2006.201.16:54:38.84#ibcon#enter sib2, iclass 27, count 0 2006.201.16:54:38.84#ibcon#flushed, iclass 27, count 0 2006.201.16:54:38.84#ibcon#about to write, iclass 27, count 0 2006.201.16:54:38.84#ibcon#wrote, iclass 27, count 0 2006.201.16:54:38.84#ibcon#about to read 3, iclass 27, count 0 2006.201.16:54:38.88#ibcon#read 3, iclass 27, count 0 2006.201.16:54:38.88#ibcon#about to read 4, iclass 27, count 0 2006.201.16:54:38.88#ibcon#read 4, iclass 27, count 0 2006.201.16:54:38.88#ibcon#about to read 5, iclass 27, count 0 2006.201.16:54:38.88#ibcon#read 5, iclass 27, count 0 2006.201.16:54:38.88#ibcon#about to read 6, iclass 27, count 0 2006.201.16:54:38.88#ibcon#read 6, iclass 27, count 0 2006.201.16:54:38.88#ibcon#end of sib2, iclass 27, count 0 2006.201.16:54:38.88#ibcon#*after write, iclass 27, count 0 2006.201.16:54:38.88#ibcon#*before return 0, iclass 27, count 0 2006.201.16:54:38.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:38.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.16:54:38.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.16:54:38.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.16:54:38.88$vck44/vb=2,5 2006.201.16:54:38.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.16:54:38.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.16:54:38.88#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:38.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:38.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:38.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:38.94#ibcon#enter wrdev, iclass 29, count 2 2006.201.16:54:38.94#ibcon#first serial, iclass 29, count 2 2006.201.16:54:38.94#ibcon#enter sib2, iclass 29, count 2 2006.201.16:54:38.94#ibcon#flushed, iclass 29, count 2 2006.201.16:54:38.94#ibcon#about to write, iclass 29, count 2 2006.201.16:54:38.94#ibcon#wrote, iclass 29, count 2 2006.201.16:54:38.94#ibcon#about to read 3, iclass 29, count 2 2006.201.16:54:38.96#ibcon#read 3, iclass 29, count 2 2006.201.16:54:38.96#ibcon#about to read 4, iclass 29, count 2 2006.201.16:54:38.96#ibcon#read 4, iclass 29, count 2 2006.201.16:54:38.96#ibcon#about to read 5, iclass 29, count 2 2006.201.16:54:38.96#ibcon#read 5, iclass 29, count 2 2006.201.16:54:38.96#ibcon#about to read 6, iclass 29, count 2 2006.201.16:54:38.96#ibcon#read 6, iclass 29, count 2 2006.201.16:54:38.96#ibcon#end of sib2, iclass 29, count 2 2006.201.16:54:38.96#ibcon#*mode == 0, iclass 29, count 2 2006.201.16:54:38.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.16:54:38.96#ibcon#[27=AT02-05\r\n] 2006.201.16:54:38.96#ibcon#*before write, iclass 29, count 2 2006.201.16:54:38.96#ibcon#enter sib2, iclass 29, count 2 2006.201.16:54:38.96#ibcon#flushed, iclass 29, count 2 2006.201.16:54:38.96#ibcon#about to write, iclass 29, count 2 2006.201.16:54:38.96#ibcon#wrote, iclass 29, count 2 2006.201.16:54:38.96#ibcon#about to read 3, iclass 29, count 2 2006.201.16:54:38.99#ibcon#read 3, iclass 29, count 2 2006.201.16:54:38.99#ibcon#about to read 4, iclass 29, count 2 2006.201.16:54:38.99#ibcon#read 4, iclass 29, count 2 2006.201.16:54:38.99#ibcon#about to read 5, iclass 29, count 2 2006.201.16:54:38.99#ibcon#read 5, iclass 29, count 2 2006.201.16:54:38.99#ibcon#about to read 6, iclass 29, count 2 2006.201.16:54:38.99#ibcon#read 6, iclass 29, count 2 2006.201.16:54:38.99#ibcon#end of sib2, iclass 29, count 2 2006.201.16:54:38.99#ibcon#*after write, iclass 29, count 2 2006.201.16:54:38.99#ibcon#*before return 0, iclass 29, count 2 2006.201.16:54:38.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:38.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.16:54:38.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.16:54:38.99#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:38.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:39.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:39.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:39.11#ibcon#enter wrdev, iclass 29, count 0 2006.201.16:54:39.11#ibcon#first serial, iclass 29, count 0 2006.201.16:54:39.11#ibcon#enter sib2, iclass 29, count 0 2006.201.16:54:39.11#ibcon#flushed, iclass 29, count 0 2006.201.16:54:39.11#ibcon#about to write, iclass 29, count 0 2006.201.16:54:39.11#ibcon#wrote, iclass 29, count 0 2006.201.16:54:39.11#ibcon#about to read 3, iclass 29, count 0 2006.201.16:54:39.13#ibcon#read 3, iclass 29, count 0 2006.201.16:54:39.13#ibcon#about to read 4, iclass 29, count 0 2006.201.16:54:39.13#ibcon#read 4, iclass 29, count 0 2006.201.16:54:39.13#ibcon#about to read 5, iclass 29, count 0 2006.201.16:54:39.13#ibcon#read 5, iclass 29, count 0 2006.201.16:54:39.13#ibcon#about to read 6, iclass 29, count 0 2006.201.16:54:39.13#ibcon#read 6, iclass 29, count 0 2006.201.16:54:39.13#ibcon#end of sib2, iclass 29, count 0 2006.201.16:54:39.13#ibcon#*mode == 0, iclass 29, count 0 2006.201.16:54:39.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.16:54:39.13#ibcon#[27=USB\r\n] 2006.201.16:54:39.13#ibcon#*before write, iclass 29, count 0 2006.201.16:54:39.13#ibcon#enter sib2, iclass 29, count 0 2006.201.16:54:39.13#ibcon#flushed, iclass 29, count 0 2006.201.16:54:39.13#ibcon#about to write, iclass 29, count 0 2006.201.16:54:39.13#ibcon#wrote, iclass 29, count 0 2006.201.16:54:39.13#ibcon#about to read 3, iclass 29, count 0 2006.201.16:54:39.16#ibcon#read 3, iclass 29, count 0 2006.201.16:54:39.16#ibcon#about to read 4, iclass 29, count 0 2006.201.16:54:39.16#ibcon#read 4, iclass 29, count 0 2006.201.16:54:39.16#ibcon#about to read 5, iclass 29, count 0 2006.201.16:54:39.16#ibcon#read 5, iclass 29, count 0 2006.201.16:54:39.16#ibcon#about to read 6, iclass 29, count 0 2006.201.16:54:39.16#ibcon#read 6, iclass 29, count 0 2006.201.16:54:39.16#ibcon#end of sib2, iclass 29, count 0 2006.201.16:54:39.16#ibcon#*after write, iclass 29, count 0 2006.201.16:54:39.16#ibcon#*before return 0, iclass 29, count 0 2006.201.16:54:39.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:39.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.16:54:39.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.16:54:39.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.16:54:39.16$vck44/vblo=3,649.99 2006.201.16:54:39.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.16:54:39.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.16:54:39.16#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:39.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:39.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:39.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:39.16#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:54:39.16#ibcon#first serial, iclass 31, count 0 2006.201.16:54:39.16#ibcon#enter sib2, iclass 31, count 0 2006.201.16:54:39.16#ibcon#flushed, iclass 31, count 0 2006.201.16:54:39.16#ibcon#about to write, iclass 31, count 0 2006.201.16:54:39.16#ibcon#wrote, iclass 31, count 0 2006.201.16:54:39.16#ibcon#about to read 3, iclass 31, count 0 2006.201.16:54:39.18#ibcon#read 3, iclass 31, count 0 2006.201.16:54:39.18#ibcon#about to read 4, iclass 31, count 0 2006.201.16:54:39.18#ibcon#read 4, iclass 31, count 0 2006.201.16:54:39.18#ibcon#about to read 5, iclass 31, count 0 2006.201.16:54:39.18#ibcon#read 5, iclass 31, count 0 2006.201.16:54:39.18#ibcon#about to read 6, iclass 31, count 0 2006.201.16:54:39.18#ibcon#read 6, iclass 31, count 0 2006.201.16:54:39.18#ibcon#end of sib2, iclass 31, count 0 2006.201.16:54:39.18#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:54:39.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:54:39.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:54:39.18#ibcon#*before write, iclass 31, count 0 2006.201.16:54:39.18#ibcon#enter sib2, iclass 31, count 0 2006.201.16:54:39.18#ibcon#flushed, iclass 31, count 0 2006.201.16:54:39.18#ibcon#about to write, iclass 31, count 0 2006.201.16:54:39.18#ibcon#wrote, iclass 31, count 0 2006.201.16:54:39.18#ibcon#about to read 3, iclass 31, count 0 2006.201.16:54:39.22#ibcon#read 3, iclass 31, count 0 2006.201.16:54:39.22#ibcon#about to read 4, iclass 31, count 0 2006.201.16:54:39.22#ibcon#read 4, iclass 31, count 0 2006.201.16:54:39.22#ibcon#about to read 5, iclass 31, count 0 2006.201.16:54:39.22#ibcon#read 5, iclass 31, count 0 2006.201.16:54:39.22#ibcon#about to read 6, iclass 31, count 0 2006.201.16:54:39.22#ibcon#read 6, iclass 31, count 0 2006.201.16:54:39.22#ibcon#end of sib2, iclass 31, count 0 2006.201.16:54:39.22#ibcon#*after write, iclass 31, count 0 2006.201.16:54:39.22#ibcon#*before return 0, iclass 31, count 0 2006.201.16:54:39.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:39.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:54:39.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:54:39.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:54:39.22$vck44/vb=3,4 2006.201.16:54:39.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.16:54:39.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.16:54:39.22#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:39.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:39.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:39.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:39.28#ibcon#enter wrdev, iclass 33, count 2 2006.201.16:54:39.28#ibcon#first serial, iclass 33, count 2 2006.201.16:54:39.28#ibcon#enter sib2, iclass 33, count 2 2006.201.16:54:39.28#ibcon#flushed, iclass 33, count 2 2006.201.16:54:39.28#ibcon#about to write, iclass 33, count 2 2006.201.16:54:39.28#ibcon#wrote, iclass 33, count 2 2006.201.16:54:39.28#ibcon#about to read 3, iclass 33, count 2 2006.201.16:54:39.30#ibcon#read 3, iclass 33, count 2 2006.201.16:54:39.30#ibcon#about to read 4, iclass 33, count 2 2006.201.16:54:39.30#ibcon#read 4, iclass 33, count 2 2006.201.16:54:39.30#ibcon#about to read 5, iclass 33, count 2 2006.201.16:54:39.30#ibcon#read 5, iclass 33, count 2 2006.201.16:54:39.30#ibcon#about to read 6, iclass 33, count 2 2006.201.16:54:39.30#ibcon#read 6, iclass 33, count 2 2006.201.16:54:39.30#ibcon#end of sib2, iclass 33, count 2 2006.201.16:54:39.30#ibcon#*mode == 0, iclass 33, count 2 2006.201.16:54:39.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.16:54:39.30#ibcon#[27=AT03-04\r\n] 2006.201.16:54:39.30#ibcon#*before write, iclass 33, count 2 2006.201.16:54:39.30#ibcon#enter sib2, iclass 33, count 2 2006.201.16:54:39.30#ibcon#flushed, iclass 33, count 2 2006.201.16:54:39.30#ibcon#about to write, iclass 33, count 2 2006.201.16:54:39.30#ibcon#wrote, iclass 33, count 2 2006.201.16:54:39.30#ibcon#about to read 3, iclass 33, count 2 2006.201.16:54:39.33#ibcon#read 3, iclass 33, count 2 2006.201.16:54:39.33#ibcon#about to read 4, iclass 33, count 2 2006.201.16:54:39.33#ibcon#read 4, iclass 33, count 2 2006.201.16:54:39.33#ibcon#about to read 5, iclass 33, count 2 2006.201.16:54:39.33#ibcon#read 5, iclass 33, count 2 2006.201.16:54:39.33#ibcon#about to read 6, iclass 33, count 2 2006.201.16:54:39.33#ibcon#read 6, iclass 33, count 2 2006.201.16:54:39.33#ibcon#end of sib2, iclass 33, count 2 2006.201.16:54:39.33#ibcon#*after write, iclass 33, count 2 2006.201.16:54:39.33#ibcon#*before return 0, iclass 33, count 2 2006.201.16:54:39.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:39.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.16:54:39.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.16:54:39.33#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:39.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:39.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:39.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:39.45#ibcon#enter wrdev, iclass 33, count 0 2006.201.16:54:39.45#ibcon#first serial, iclass 33, count 0 2006.201.16:54:39.45#ibcon#enter sib2, iclass 33, count 0 2006.201.16:54:39.45#ibcon#flushed, iclass 33, count 0 2006.201.16:54:39.45#ibcon#about to write, iclass 33, count 0 2006.201.16:54:39.45#ibcon#wrote, iclass 33, count 0 2006.201.16:54:39.45#ibcon#about to read 3, iclass 33, count 0 2006.201.16:54:39.47#ibcon#read 3, iclass 33, count 0 2006.201.16:54:39.47#ibcon#about to read 4, iclass 33, count 0 2006.201.16:54:39.47#ibcon#read 4, iclass 33, count 0 2006.201.16:54:39.47#ibcon#about to read 5, iclass 33, count 0 2006.201.16:54:39.47#ibcon#read 5, iclass 33, count 0 2006.201.16:54:39.47#ibcon#about to read 6, iclass 33, count 0 2006.201.16:54:39.47#ibcon#read 6, iclass 33, count 0 2006.201.16:54:39.47#ibcon#end of sib2, iclass 33, count 0 2006.201.16:54:39.47#ibcon#*mode == 0, iclass 33, count 0 2006.201.16:54:39.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.16:54:39.47#ibcon#[27=USB\r\n] 2006.201.16:54:39.47#ibcon#*before write, iclass 33, count 0 2006.201.16:54:39.47#ibcon#enter sib2, iclass 33, count 0 2006.201.16:54:39.47#ibcon#flushed, iclass 33, count 0 2006.201.16:54:39.47#ibcon#about to write, iclass 33, count 0 2006.201.16:54:39.47#ibcon#wrote, iclass 33, count 0 2006.201.16:54:39.47#ibcon#about to read 3, iclass 33, count 0 2006.201.16:54:39.50#ibcon#read 3, iclass 33, count 0 2006.201.16:54:39.50#ibcon#about to read 4, iclass 33, count 0 2006.201.16:54:39.50#ibcon#read 4, iclass 33, count 0 2006.201.16:54:39.50#ibcon#about to read 5, iclass 33, count 0 2006.201.16:54:39.50#ibcon#read 5, iclass 33, count 0 2006.201.16:54:39.50#ibcon#about to read 6, iclass 33, count 0 2006.201.16:54:39.50#ibcon#read 6, iclass 33, count 0 2006.201.16:54:39.50#ibcon#end of sib2, iclass 33, count 0 2006.201.16:54:39.50#ibcon#*after write, iclass 33, count 0 2006.201.16:54:39.50#ibcon#*before return 0, iclass 33, count 0 2006.201.16:54:39.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:39.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.16:54:39.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.16:54:39.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.16:54:39.50$vck44/vblo=4,679.99 2006.201.16:54:39.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.16:54:39.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.16:54:39.50#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:39.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:39.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:39.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:39.50#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:54:39.50#ibcon#first serial, iclass 35, count 0 2006.201.16:54:39.50#ibcon#enter sib2, iclass 35, count 0 2006.201.16:54:39.50#ibcon#flushed, iclass 35, count 0 2006.201.16:54:39.50#ibcon#about to write, iclass 35, count 0 2006.201.16:54:39.50#ibcon#wrote, iclass 35, count 0 2006.201.16:54:39.50#ibcon#about to read 3, iclass 35, count 0 2006.201.16:54:39.52#ibcon#read 3, iclass 35, count 0 2006.201.16:54:39.52#ibcon#about to read 4, iclass 35, count 0 2006.201.16:54:39.52#ibcon#read 4, iclass 35, count 0 2006.201.16:54:39.52#ibcon#about to read 5, iclass 35, count 0 2006.201.16:54:39.52#ibcon#read 5, iclass 35, count 0 2006.201.16:54:39.52#ibcon#about to read 6, iclass 35, count 0 2006.201.16:54:39.52#ibcon#read 6, iclass 35, count 0 2006.201.16:54:39.52#ibcon#end of sib2, iclass 35, count 0 2006.201.16:54:39.52#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:54:39.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:54:39.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:54:39.52#ibcon#*before write, iclass 35, count 0 2006.201.16:54:39.52#ibcon#enter sib2, iclass 35, count 0 2006.201.16:54:39.52#ibcon#flushed, iclass 35, count 0 2006.201.16:54:39.52#ibcon#about to write, iclass 35, count 0 2006.201.16:54:39.52#ibcon#wrote, iclass 35, count 0 2006.201.16:54:39.52#ibcon#about to read 3, iclass 35, count 0 2006.201.16:54:39.56#ibcon#read 3, iclass 35, count 0 2006.201.16:54:39.56#ibcon#about to read 4, iclass 35, count 0 2006.201.16:54:39.56#ibcon#read 4, iclass 35, count 0 2006.201.16:54:39.56#ibcon#about to read 5, iclass 35, count 0 2006.201.16:54:39.56#ibcon#read 5, iclass 35, count 0 2006.201.16:54:39.56#ibcon#about to read 6, iclass 35, count 0 2006.201.16:54:39.56#ibcon#read 6, iclass 35, count 0 2006.201.16:54:39.56#ibcon#end of sib2, iclass 35, count 0 2006.201.16:54:39.56#ibcon#*after write, iclass 35, count 0 2006.201.16:54:39.56#ibcon#*before return 0, iclass 35, count 0 2006.201.16:54:39.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:39.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.16:54:39.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:54:39.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:54:39.56$vck44/vb=4,5 2006.201.16:54:39.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.16:54:39.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.16:54:39.56#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:39.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:39.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:39.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:39.62#ibcon#enter wrdev, iclass 37, count 2 2006.201.16:54:39.62#ibcon#first serial, iclass 37, count 2 2006.201.16:54:39.62#ibcon#enter sib2, iclass 37, count 2 2006.201.16:54:39.62#ibcon#flushed, iclass 37, count 2 2006.201.16:54:39.62#ibcon#about to write, iclass 37, count 2 2006.201.16:54:39.62#ibcon#wrote, iclass 37, count 2 2006.201.16:54:39.62#ibcon#about to read 3, iclass 37, count 2 2006.201.16:54:39.64#ibcon#read 3, iclass 37, count 2 2006.201.16:54:39.64#ibcon#about to read 4, iclass 37, count 2 2006.201.16:54:39.64#ibcon#read 4, iclass 37, count 2 2006.201.16:54:39.64#ibcon#about to read 5, iclass 37, count 2 2006.201.16:54:39.64#ibcon#read 5, iclass 37, count 2 2006.201.16:54:39.64#ibcon#about to read 6, iclass 37, count 2 2006.201.16:54:39.64#ibcon#read 6, iclass 37, count 2 2006.201.16:54:39.64#ibcon#end of sib2, iclass 37, count 2 2006.201.16:54:39.64#ibcon#*mode == 0, iclass 37, count 2 2006.201.16:54:39.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.16:54:39.64#ibcon#[27=AT04-05\r\n] 2006.201.16:54:39.64#ibcon#*before write, iclass 37, count 2 2006.201.16:54:39.64#ibcon#enter sib2, iclass 37, count 2 2006.201.16:54:39.64#ibcon#flushed, iclass 37, count 2 2006.201.16:54:39.64#ibcon#about to write, iclass 37, count 2 2006.201.16:54:39.64#ibcon#wrote, iclass 37, count 2 2006.201.16:54:39.64#ibcon#about to read 3, iclass 37, count 2 2006.201.16:54:39.67#ibcon#read 3, iclass 37, count 2 2006.201.16:54:39.67#ibcon#about to read 4, iclass 37, count 2 2006.201.16:54:39.67#ibcon#read 4, iclass 37, count 2 2006.201.16:54:39.67#ibcon#about to read 5, iclass 37, count 2 2006.201.16:54:39.67#ibcon#read 5, iclass 37, count 2 2006.201.16:54:39.67#ibcon#about to read 6, iclass 37, count 2 2006.201.16:54:39.67#ibcon#read 6, iclass 37, count 2 2006.201.16:54:39.67#ibcon#end of sib2, iclass 37, count 2 2006.201.16:54:39.67#ibcon#*after write, iclass 37, count 2 2006.201.16:54:39.67#ibcon#*before return 0, iclass 37, count 2 2006.201.16:54:39.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:39.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.16:54:39.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.16:54:39.67#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:39.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:39.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:39.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:39.79#ibcon#enter wrdev, iclass 37, count 0 2006.201.16:54:39.79#ibcon#first serial, iclass 37, count 0 2006.201.16:54:39.79#ibcon#enter sib2, iclass 37, count 0 2006.201.16:54:39.79#ibcon#flushed, iclass 37, count 0 2006.201.16:54:39.79#ibcon#about to write, iclass 37, count 0 2006.201.16:54:39.79#ibcon#wrote, iclass 37, count 0 2006.201.16:54:39.79#ibcon#about to read 3, iclass 37, count 0 2006.201.16:54:39.81#ibcon#read 3, iclass 37, count 0 2006.201.16:54:39.81#ibcon#about to read 4, iclass 37, count 0 2006.201.16:54:39.81#ibcon#read 4, iclass 37, count 0 2006.201.16:54:39.81#ibcon#about to read 5, iclass 37, count 0 2006.201.16:54:39.81#ibcon#read 5, iclass 37, count 0 2006.201.16:54:39.81#ibcon#about to read 6, iclass 37, count 0 2006.201.16:54:39.81#ibcon#read 6, iclass 37, count 0 2006.201.16:54:39.81#ibcon#end of sib2, iclass 37, count 0 2006.201.16:54:39.81#ibcon#*mode == 0, iclass 37, count 0 2006.201.16:54:39.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.16:54:39.81#ibcon#[27=USB\r\n] 2006.201.16:54:39.81#ibcon#*before write, iclass 37, count 0 2006.201.16:54:39.81#ibcon#enter sib2, iclass 37, count 0 2006.201.16:54:39.81#ibcon#flushed, iclass 37, count 0 2006.201.16:54:39.81#ibcon#about to write, iclass 37, count 0 2006.201.16:54:39.81#ibcon#wrote, iclass 37, count 0 2006.201.16:54:39.81#ibcon#about to read 3, iclass 37, count 0 2006.201.16:54:39.84#ibcon#read 3, iclass 37, count 0 2006.201.16:54:39.84#ibcon#about to read 4, iclass 37, count 0 2006.201.16:54:39.84#ibcon#read 4, iclass 37, count 0 2006.201.16:54:39.84#ibcon#about to read 5, iclass 37, count 0 2006.201.16:54:39.84#ibcon#read 5, iclass 37, count 0 2006.201.16:54:39.84#ibcon#about to read 6, iclass 37, count 0 2006.201.16:54:39.84#ibcon#read 6, iclass 37, count 0 2006.201.16:54:39.84#ibcon#end of sib2, iclass 37, count 0 2006.201.16:54:39.84#ibcon#*after write, iclass 37, count 0 2006.201.16:54:39.84#ibcon#*before return 0, iclass 37, count 0 2006.201.16:54:39.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:39.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.16:54:39.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.16:54:39.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.16:54:39.84$vck44/vblo=5,709.99 2006.201.16:54:39.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.16:54:39.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.16:54:39.84#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:39.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:39.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:39.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:39.84#ibcon#enter wrdev, iclass 39, count 0 2006.201.16:54:39.84#ibcon#first serial, iclass 39, count 0 2006.201.16:54:39.84#ibcon#enter sib2, iclass 39, count 0 2006.201.16:54:39.84#ibcon#flushed, iclass 39, count 0 2006.201.16:54:39.84#ibcon#about to write, iclass 39, count 0 2006.201.16:54:39.84#ibcon#wrote, iclass 39, count 0 2006.201.16:54:39.84#ibcon#about to read 3, iclass 39, count 0 2006.201.16:54:39.86#ibcon#read 3, iclass 39, count 0 2006.201.16:54:39.86#ibcon#about to read 4, iclass 39, count 0 2006.201.16:54:39.86#ibcon#read 4, iclass 39, count 0 2006.201.16:54:39.86#ibcon#about to read 5, iclass 39, count 0 2006.201.16:54:39.86#ibcon#read 5, iclass 39, count 0 2006.201.16:54:39.86#ibcon#about to read 6, iclass 39, count 0 2006.201.16:54:39.86#ibcon#read 6, iclass 39, count 0 2006.201.16:54:39.86#ibcon#end of sib2, iclass 39, count 0 2006.201.16:54:39.86#ibcon#*mode == 0, iclass 39, count 0 2006.201.16:54:39.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.16:54:39.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:54:39.86#ibcon#*before write, iclass 39, count 0 2006.201.16:54:39.86#ibcon#enter sib2, iclass 39, count 0 2006.201.16:54:39.86#ibcon#flushed, iclass 39, count 0 2006.201.16:54:39.86#ibcon#about to write, iclass 39, count 0 2006.201.16:54:39.86#ibcon#wrote, iclass 39, count 0 2006.201.16:54:39.86#ibcon#about to read 3, iclass 39, count 0 2006.201.16:54:39.91#ibcon#read 3, iclass 39, count 0 2006.201.16:54:39.91#ibcon#about to read 4, iclass 39, count 0 2006.201.16:54:39.91#ibcon#read 4, iclass 39, count 0 2006.201.16:54:39.91#ibcon#about to read 5, iclass 39, count 0 2006.201.16:54:39.91#ibcon#read 5, iclass 39, count 0 2006.201.16:54:39.91#ibcon#about to read 6, iclass 39, count 0 2006.201.16:54:39.91#ibcon#read 6, iclass 39, count 0 2006.201.16:54:39.91#ibcon#end of sib2, iclass 39, count 0 2006.201.16:54:39.91#ibcon#*after write, iclass 39, count 0 2006.201.16:54:39.91#ibcon#*before return 0, iclass 39, count 0 2006.201.16:54:39.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:39.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.16:54:39.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.16:54:39.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.16:54:39.91$vck44/vb=5,4 2006.201.16:54:39.91#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.16:54:39.91#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.16:54:39.91#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:39.91#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:39.96#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:39.96#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:39.96#ibcon#enter wrdev, iclass 2, count 2 2006.201.16:54:39.96#ibcon#first serial, iclass 2, count 2 2006.201.16:54:39.96#ibcon#enter sib2, iclass 2, count 2 2006.201.16:54:39.96#ibcon#flushed, iclass 2, count 2 2006.201.16:54:39.96#ibcon#about to write, iclass 2, count 2 2006.201.16:54:39.96#ibcon#wrote, iclass 2, count 2 2006.201.16:54:39.96#ibcon#about to read 3, iclass 2, count 2 2006.201.16:54:39.98#ibcon#read 3, iclass 2, count 2 2006.201.16:54:39.98#ibcon#about to read 4, iclass 2, count 2 2006.201.16:54:39.98#ibcon#read 4, iclass 2, count 2 2006.201.16:54:39.98#ibcon#about to read 5, iclass 2, count 2 2006.201.16:54:39.98#ibcon#read 5, iclass 2, count 2 2006.201.16:54:39.98#ibcon#about to read 6, iclass 2, count 2 2006.201.16:54:39.98#ibcon#read 6, iclass 2, count 2 2006.201.16:54:39.98#ibcon#end of sib2, iclass 2, count 2 2006.201.16:54:39.98#ibcon#*mode == 0, iclass 2, count 2 2006.201.16:54:39.98#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.16:54:39.98#ibcon#[27=AT05-04\r\n] 2006.201.16:54:39.98#ibcon#*before write, iclass 2, count 2 2006.201.16:54:39.98#ibcon#enter sib2, iclass 2, count 2 2006.201.16:54:39.98#ibcon#flushed, iclass 2, count 2 2006.201.16:54:39.98#ibcon#about to write, iclass 2, count 2 2006.201.16:54:39.98#ibcon#wrote, iclass 2, count 2 2006.201.16:54:39.98#ibcon#about to read 3, iclass 2, count 2 2006.201.16:54:40.01#ibcon#read 3, iclass 2, count 2 2006.201.16:54:40.01#ibcon#about to read 4, iclass 2, count 2 2006.201.16:54:40.01#ibcon#read 4, iclass 2, count 2 2006.201.16:54:40.01#ibcon#about to read 5, iclass 2, count 2 2006.201.16:54:40.01#ibcon#read 5, iclass 2, count 2 2006.201.16:54:40.01#ibcon#about to read 6, iclass 2, count 2 2006.201.16:54:40.01#ibcon#read 6, iclass 2, count 2 2006.201.16:54:40.01#ibcon#end of sib2, iclass 2, count 2 2006.201.16:54:40.01#ibcon#*after write, iclass 2, count 2 2006.201.16:54:40.01#ibcon#*before return 0, iclass 2, count 2 2006.201.16:54:40.01#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:40.01#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.16:54:40.01#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.16:54:40.01#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:40.01#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:40.13#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:40.13#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:40.13#ibcon#enter wrdev, iclass 2, count 0 2006.201.16:54:40.13#ibcon#first serial, iclass 2, count 0 2006.201.16:54:40.13#ibcon#enter sib2, iclass 2, count 0 2006.201.16:54:40.13#ibcon#flushed, iclass 2, count 0 2006.201.16:54:40.13#ibcon#about to write, iclass 2, count 0 2006.201.16:54:40.13#ibcon#wrote, iclass 2, count 0 2006.201.16:54:40.13#ibcon#about to read 3, iclass 2, count 0 2006.201.16:54:40.15#ibcon#read 3, iclass 2, count 0 2006.201.16:54:40.15#ibcon#about to read 4, iclass 2, count 0 2006.201.16:54:40.15#ibcon#read 4, iclass 2, count 0 2006.201.16:54:40.15#ibcon#about to read 5, iclass 2, count 0 2006.201.16:54:40.15#ibcon#read 5, iclass 2, count 0 2006.201.16:54:40.15#ibcon#about to read 6, iclass 2, count 0 2006.201.16:54:40.15#ibcon#read 6, iclass 2, count 0 2006.201.16:54:40.15#ibcon#end of sib2, iclass 2, count 0 2006.201.16:54:40.15#ibcon#*mode == 0, iclass 2, count 0 2006.201.16:54:40.15#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.16:54:40.15#ibcon#[27=USB\r\n] 2006.201.16:54:40.15#ibcon#*before write, iclass 2, count 0 2006.201.16:54:40.15#ibcon#enter sib2, iclass 2, count 0 2006.201.16:54:40.15#ibcon#flushed, iclass 2, count 0 2006.201.16:54:40.15#ibcon#about to write, iclass 2, count 0 2006.201.16:54:40.15#ibcon#wrote, iclass 2, count 0 2006.201.16:54:40.15#ibcon#about to read 3, iclass 2, count 0 2006.201.16:54:40.18#ibcon#read 3, iclass 2, count 0 2006.201.16:54:40.18#ibcon#about to read 4, iclass 2, count 0 2006.201.16:54:40.18#ibcon#read 4, iclass 2, count 0 2006.201.16:54:40.18#ibcon#about to read 5, iclass 2, count 0 2006.201.16:54:40.18#ibcon#read 5, iclass 2, count 0 2006.201.16:54:40.18#ibcon#about to read 6, iclass 2, count 0 2006.201.16:54:40.18#ibcon#read 6, iclass 2, count 0 2006.201.16:54:40.18#ibcon#end of sib2, iclass 2, count 0 2006.201.16:54:40.18#ibcon#*after write, iclass 2, count 0 2006.201.16:54:40.18#ibcon#*before return 0, iclass 2, count 0 2006.201.16:54:40.18#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:40.18#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.16:54:40.18#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.16:54:40.18#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.16:54:40.18$vck44/vblo=6,719.99 2006.201.16:54:40.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.16:54:40.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.16:54:40.18#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:40.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:40.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:40.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:40.18#ibcon#enter wrdev, iclass 5, count 0 2006.201.16:54:40.18#ibcon#first serial, iclass 5, count 0 2006.201.16:54:40.18#ibcon#enter sib2, iclass 5, count 0 2006.201.16:54:40.18#ibcon#flushed, iclass 5, count 0 2006.201.16:54:40.18#ibcon#about to write, iclass 5, count 0 2006.201.16:54:40.18#ibcon#wrote, iclass 5, count 0 2006.201.16:54:40.18#ibcon#about to read 3, iclass 5, count 0 2006.201.16:54:40.20#ibcon#read 3, iclass 5, count 0 2006.201.16:54:40.20#ibcon#about to read 4, iclass 5, count 0 2006.201.16:54:40.20#ibcon#read 4, iclass 5, count 0 2006.201.16:54:40.20#ibcon#about to read 5, iclass 5, count 0 2006.201.16:54:40.20#ibcon#read 5, iclass 5, count 0 2006.201.16:54:40.20#ibcon#about to read 6, iclass 5, count 0 2006.201.16:54:40.20#ibcon#read 6, iclass 5, count 0 2006.201.16:54:40.20#ibcon#end of sib2, iclass 5, count 0 2006.201.16:54:40.20#ibcon#*mode == 0, iclass 5, count 0 2006.201.16:54:40.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.16:54:40.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:54:40.20#ibcon#*before write, iclass 5, count 0 2006.201.16:54:40.20#ibcon#enter sib2, iclass 5, count 0 2006.201.16:54:40.20#ibcon#flushed, iclass 5, count 0 2006.201.16:54:40.20#ibcon#about to write, iclass 5, count 0 2006.201.16:54:40.20#ibcon#wrote, iclass 5, count 0 2006.201.16:54:40.20#ibcon#about to read 3, iclass 5, count 0 2006.201.16:54:40.25#ibcon#read 3, iclass 5, count 0 2006.201.16:54:40.25#ibcon#about to read 4, iclass 5, count 0 2006.201.16:54:40.25#ibcon#read 4, iclass 5, count 0 2006.201.16:54:40.25#ibcon#about to read 5, iclass 5, count 0 2006.201.16:54:40.25#ibcon#read 5, iclass 5, count 0 2006.201.16:54:40.25#ibcon#about to read 6, iclass 5, count 0 2006.201.16:54:40.25#ibcon#read 6, iclass 5, count 0 2006.201.16:54:40.25#ibcon#end of sib2, iclass 5, count 0 2006.201.16:54:40.25#ibcon#*after write, iclass 5, count 0 2006.201.16:54:40.25#ibcon#*before return 0, iclass 5, count 0 2006.201.16:54:40.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:40.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.16:54:40.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.16:54:40.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.16:54:40.25$vck44/vb=6,4 2006.201.16:54:40.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.16:54:40.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.16:54:40.25#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:40.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:40.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:40.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:40.30#ibcon#enter wrdev, iclass 7, count 2 2006.201.16:54:40.30#ibcon#first serial, iclass 7, count 2 2006.201.16:54:40.30#ibcon#enter sib2, iclass 7, count 2 2006.201.16:54:40.30#ibcon#flushed, iclass 7, count 2 2006.201.16:54:40.30#ibcon#about to write, iclass 7, count 2 2006.201.16:54:40.30#ibcon#wrote, iclass 7, count 2 2006.201.16:54:40.30#ibcon#about to read 3, iclass 7, count 2 2006.201.16:54:40.32#ibcon#read 3, iclass 7, count 2 2006.201.16:54:40.32#ibcon#about to read 4, iclass 7, count 2 2006.201.16:54:40.32#ibcon#read 4, iclass 7, count 2 2006.201.16:54:40.32#ibcon#about to read 5, iclass 7, count 2 2006.201.16:54:40.32#ibcon#read 5, iclass 7, count 2 2006.201.16:54:40.32#ibcon#about to read 6, iclass 7, count 2 2006.201.16:54:40.32#ibcon#read 6, iclass 7, count 2 2006.201.16:54:40.32#ibcon#end of sib2, iclass 7, count 2 2006.201.16:54:40.32#ibcon#*mode == 0, iclass 7, count 2 2006.201.16:54:40.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.16:54:40.32#ibcon#[27=AT06-04\r\n] 2006.201.16:54:40.32#ibcon#*before write, iclass 7, count 2 2006.201.16:54:40.32#ibcon#enter sib2, iclass 7, count 2 2006.201.16:54:40.32#ibcon#flushed, iclass 7, count 2 2006.201.16:54:40.32#ibcon#about to write, iclass 7, count 2 2006.201.16:54:40.32#ibcon#wrote, iclass 7, count 2 2006.201.16:54:40.32#ibcon#about to read 3, iclass 7, count 2 2006.201.16:54:40.35#ibcon#read 3, iclass 7, count 2 2006.201.16:54:40.35#ibcon#about to read 4, iclass 7, count 2 2006.201.16:54:40.35#ibcon#read 4, iclass 7, count 2 2006.201.16:54:40.35#ibcon#about to read 5, iclass 7, count 2 2006.201.16:54:40.35#ibcon#read 5, iclass 7, count 2 2006.201.16:54:40.35#ibcon#about to read 6, iclass 7, count 2 2006.201.16:54:40.35#ibcon#read 6, iclass 7, count 2 2006.201.16:54:40.35#ibcon#end of sib2, iclass 7, count 2 2006.201.16:54:40.35#ibcon#*after write, iclass 7, count 2 2006.201.16:54:40.35#ibcon#*before return 0, iclass 7, count 2 2006.201.16:54:40.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:40.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.16:54:40.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.16:54:40.35#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:40.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:40.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:40.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:40.47#ibcon#enter wrdev, iclass 7, count 0 2006.201.16:54:40.47#ibcon#first serial, iclass 7, count 0 2006.201.16:54:40.47#ibcon#enter sib2, iclass 7, count 0 2006.201.16:54:40.47#ibcon#flushed, iclass 7, count 0 2006.201.16:54:40.47#ibcon#about to write, iclass 7, count 0 2006.201.16:54:40.47#ibcon#wrote, iclass 7, count 0 2006.201.16:54:40.47#ibcon#about to read 3, iclass 7, count 0 2006.201.16:54:40.49#ibcon#read 3, iclass 7, count 0 2006.201.16:54:40.49#ibcon#about to read 4, iclass 7, count 0 2006.201.16:54:40.49#ibcon#read 4, iclass 7, count 0 2006.201.16:54:40.49#ibcon#about to read 5, iclass 7, count 0 2006.201.16:54:40.49#ibcon#read 5, iclass 7, count 0 2006.201.16:54:40.49#ibcon#about to read 6, iclass 7, count 0 2006.201.16:54:40.49#ibcon#read 6, iclass 7, count 0 2006.201.16:54:40.49#ibcon#end of sib2, iclass 7, count 0 2006.201.16:54:40.49#ibcon#*mode == 0, iclass 7, count 0 2006.201.16:54:40.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.16:54:40.49#ibcon#[27=USB\r\n] 2006.201.16:54:40.49#ibcon#*before write, iclass 7, count 0 2006.201.16:54:40.49#ibcon#enter sib2, iclass 7, count 0 2006.201.16:54:40.49#ibcon#flushed, iclass 7, count 0 2006.201.16:54:40.49#ibcon#about to write, iclass 7, count 0 2006.201.16:54:40.49#ibcon#wrote, iclass 7, count 0 2006.201.16:54:40.49#ibcon#about to read 3, iclass 7, count 0 2006.201.16:54:40.52#ibcon#read 3, iclass 7, count 0 2006.201.16:54:40.52#ibcon#about to read 4, iclass 7, count 0 2006.201.16:54:40.52#ibcon#read 4, iclass 7, count 0 2006.201.16:54:40.52#ibcon#about to read 5, iclass 7, count 0 2006.201.16:54:40.52#ibcon#read 5, iclass 7, count 0 2006.201.16:54:40.52#ibcon#about to read 6, iclass 7, count 0 2006.201.16:54:40.52#ibcon#read 6, iclass 7, count 0 2006.201.16:54:40.52#ibcon#end of sib2, iclass 7, count 0 2006.201.16:54:40.52#ibcon#*after write, iclass 7, count 0 2006.201.16:54:40.52#ibcon#*before return 0, iclass 7, count 0 2006.201.16:54:40.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:40.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.16:54:40.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.16:54:40.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.16:54:40.52$vck44/vblo=7,734.99 2006.201.16:54:40.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.16:54:40.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.16:54:40.52#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:40.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:40.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:40.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:40.52#ibcon#enter wrdev, iclass 11, count 0 2006.201.16:54:40.52#ibcon#first serial, iclass 11, count 0 2006.201.16:54:40.52#ibcon#enter sib2, iclass 11, count 0 2006.201.16:54:40.52#ibcon#flushed, iclass 11, count 0 2006.201.16:54:40.52#ibcon#about to write, iclass 11, count 0 2006.201.16:54:40.52#ibcon#wrote, iclass 11, count 0 2006.201.16:54:40.52#ibcon#about to read 3, iclass 11, count 0 2006.201.16:54:40.54#ibcon#read 3, iclass 11, count 0 2006.201.16:54:40.54#ibcon#about to read 4, iclass 11, count 0 2006.201.16:54:40.54#ibcon#read 4, iclass 11, count 0 2006.201.16:54:40.54#ibcon#about to read 5, iclass 11, count 0 2006.201.16:54:40.54#ibcon#read 5, iclass 11, count 0 2006.201.16:54:40.54#ibcon#about to read 6, iclass 11, count 0 2006.201.16:54:40.54#ibcon#read 6, iclass 11, count 0 2006.201.16:54:40.54#ibcon#end of sib2, iclass 11, count 0 2006.201.16:54:40.54#ibcon#*mode == 0, iclass 11, count 0 2006.201.16:54:40.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.16:54:40.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:54:40.54#ibcon#*before write, iclass 11, count 0 2006.201.16:54:40.54#ibcon#enter sib2, iclass 11, count 0 2006.201.16:54:40.54#ibcon#flushed, iclass 11, count 0 2006.201.16:54:40.54#ibcon#about to write, iclass 11, count 0 2006.201.16:54:40.54#ibcon#wrote, iclass 11, count 0 2006.201.16:54:40.54#ibcon#about to read 3, iclass 11, count 0 2006.201.16:54:40.58#ibcon#read 3, iclass 11, count 0 2006.201.16:54:40.58#ibcon#about to read 4, iclass 11, count 0 2006.201.16:54:40.58#ibcon#read 4, iclass 11, count 0 2006.201.16:54:40.58#ibcon#about to read 5, iclass 11, count 0 2006.201.16:54:40.58#ibcon#read 5, iclass 11, count 0 2006.201.16:54:40.58#ibcon#about to read 6, iclass 11, count 0 2006.201.16:54:40.58#ibcon#read 6, iclass 11, count 0 2006.201.16:54:40.58#ibcon#end of sib2, iclass 11, count 0 2006.201.16:54:40.58#ibcon#*after write, iclass 11, count 0 2006.201.16:54:40.58#ibcon#*before return 0, iclass 11, count 0 2006.201.16:54:40.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:40.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.16:54:40.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.16:54:40.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.16:54:40.58$vck44/vb=7,4 2006.201.16:54:40.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.16:54:40.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.16:54:40.58#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:40.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:40.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:40.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:40.64#ibcon#enter wrdev, iclass 13, count 2 2006.201.16:54:40.64#ibcon#first serial, iclass 13, count 2 2006.201.16:54:40.64#ibcon#enter sib2, iclass 13, count 2 2006.201.16:54:40.64#ibcon#flushed, iclass 13, count 2 2006.201.16:54:40.64#ibcon#about to write, iclass 13, count 2 2006.201.16:54:40.64#ibcon#wrote, iclass 13, count 2 2006.201.16:54:40.64#ibcon#about to read 3, iclass 13, count 2 2006.201.16:54:40.66#ibcon#read 3, iclass 13, count 2 2006.201.16:54:40.66#ibcon#about to read 4, iclass 13, count 2 2006.201.16:54:40.66#ibcon#read 4, iclass 13, count 2 2006.201.16:54:40.66#ibcon#about to read 5, iclass 13, count 2 2006.201.16:54:40.66#ibcon#read 5, iclass 13, count 2 2006.201.16:54:40.66#ibcon#about to read 6, iclass 13, count 2 2006.201.16:54:40.66#ibcon#read 6, iclass 13, count 2 2006.201.16:54:40.66#ibcon#end of sib2, iclass 13, count 2 2006.201.16:54:40.66#ibcon#*mode == 0, iclass 13, count 2 2006.201.16:54:40.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.16:54:40.66#ibcon#[27=AT07-04\r\n] 2006.201.16:54:40.66#ibcon#*before write, iclass 13, count 2 2006.201.16:54:40.66#ibcon#enter sib2, iclass 13, count 2 2006.201.16:54:40.66#ibcon#flushed, iclass 13, count 2 2006.201.16:54:40.66#ibcon#about to write, iclass 13, count 2 2006.201.16:54:40.66#ibcon#wrote, iclass 13, count 2 2006.201.16:54:40.66#ibcon#about to read 3, iclass 13, count 2 2006.201.16:54:40.69#ibcon#read 3, iclass 13, count 2 2006.201.16:54:40.69#ibcon#about to read 4, iclass 13, count 2 2006.201.16:54:40.69#ibcon#read 4, iclass 13, count 2 2006.201.16:54:40.69#ibcon#about to read 5, iclass 13, count 2 2006.201.16:54:40.69#ibcon#read 5, iclass 13, count 2 2006.201.16:54:40.69#ibcon#about to read 6, iclass 13, count 2 2006.201.16:54:40.69#ibcon#read 6, iclass 13, count 2 2006.201.16:54:40.69#ibcon#end of sib2, iclass 13, count 2 2006.201.16:54:40.69#ibcon#*after write, iclass 13, count 2 2006.201.16:54:40.69#ibcon#*before return 0, iclass 13, count 2 2006.201.16:54:40.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:40.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.16:54:40.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.16:54:40.69#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:40.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:40.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:40.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:40.81#ibcon#enter wrdev, iclass 13, count 0 2006.201.16:54:40.81#ibcon#first serial, iclass 13, count 0 2006.201.16:54:40.81#ibcon#enter sib2, iclass 13, count 0 2006.201.16:54:40.81#ibcon#flushed, iclass 13, count 0 2006.201.16:54:40.81#ibcon#about to write, iclass 13, count 0 2006.201.16:54:40.81#ibcon#wrote, iclass 13, count 0 2006.201.16:54:40.81#ibcon#about to read 3, iclass 13, count 0 2006.201.16:54:40.83#ibcon#read 3, iclass 13, count 0 2006.201.16:54:40.83#ibcon#about to read 4, iclass 13, count 0 2006.201.16:54:40.83#ibcon#read 4, iclass 13, count 0 2006.201.16:54:40.83#ibcon#about to read 5, iclass 13, count 0 2006.201.16:54:40.83#ibcon#read 5, iclass 13, count 0 2006.201.16:54:40.83#ibcon#about to read 6, iclass 13, count 0 2006.201.16:54:40.83#ibcon#read 6, iclass 13, count 0 2006.201.16:54:40.83#ibcon#end of sib2, iclass 13, count 0 2006.201.16:54:40.83#ibcon#*mode == 0, iclass 13, count 0 2006.201.16:54:40.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.16:54:40.83#ibcon#[27=USB\r\n] 2006.201.16:54:40.83#ibcon#*before write, iclass 13, count 0 2006.201.16:54:40.83#ibcon#enter sib2, iclass 13, count 0 2006.201.16:54:40.83#ibcon#flushed, iclass 13, count 0 2006.201.16:54:40.83#ibcon#about to write, iclass 13, count 0 2006.201.16:54:40.83#ibcon#wrote, iclass 13, count 0 2006.201.16:54:40.83#ibcon#about to read 3, iclass 13, count 0 2006.201.16:54:40.86#ibcon#read 3, iclass 13, count 0 2006.201.16:54:40.86#ibcon#about to read 4, iclass 13, count 0 2006.201.16:54:40.86#ibcon#read 4, iclass 13, count 0 2006.201.16:54:40.86#ibcon#about to read 5, iclass 13, count 0 2006.201.16:54:40.86#ibcon#read 5, iclass 13, count 0 2006.201.16:54:40.86#ibcon#about to read 6, iclass 13, count 0 2006.201.16:54:40.86#ibcon#read 6, iclass 13, count 0 2006.201.16:54:40.86#ibcon#end of sib2, iclass 13, count 0 2006.201.16:54:40.86#ibcon#*after write, iclass 13, count 0 2006.201.16:54:40.86#ibcon#*before return 0, iclass 13, count 0 2006.201.16:54:40.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:40.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.16:54:40.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.16:54:40.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.16:54:40.86$vck44/vblo=8,744.99 2006.201.16:54:40.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.16:54:40.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.16:54:40.86#ibcon#ireg 17 cls_cnt 0 2006.201.16:54:40.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:40.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:40.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:40.86#ibcon#enter wrdev, iclass 15, count 0 2006.201.16:54:40.86#ibcon#first serial, iclass 15, count 0 2006.201.16:54:40.86#ibcon#enter sib2, iclass 15, count 0 2006.201.16:54:40.86#ibcon#flushed, iclass 15, count 0 2006.201.16:54:40.86#ibcon#about to write, iclass 15, count 0 2006.201.16:54:40.86#ibcon#wrote, iclass 15, count 0 2006.201.16:54:40.86#ibcon#about to read 3, iclass 15, count 0 2006.201.16:54:40.88#ibcon#read 3, iclass 15, count 0 2006.201.16:54:40.88#ibcon#about to read 4, iclass 15, count 0 2006.201.16:54:40.88#ibcon#read 4, iclass 15, count 0 2006.201.16:54:40.88#ibcon#about to read 5, iclass 15, count 0 2006.201.16:54:40.88#ibcon#read 5, iclass 15, count 0 2006.201.16:54:40.88#ibcon#about to read 6, iclass 15, count 0 2006.201.16:54:40.88#ibcon#read 6, iclass 15, count 0 2006.201.16:54:40.88#ibcon#end of sib2, iclass 15, count 0 2006.201.16:54:40.88#ibcon#*mode == 0, iclass 15, count 0 2006.201.16:54:40.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.16:54:40.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:54:40.88#ibcon#*before write, iclass 15, count 0 2006.201.16:54:40.88#ibcon#enter sib2, iclass 15, count 0 2006.201.16:54:40.88#ibcon#flushed, iclass 15, count 0 2006.201.16:54:40.88#ibcon#about to write, iclass 15, count 0 2006.201.16:54:40.88#ibcon#wrote, iclass 15, count 0 2006.201.16:54:40.88#ibcon#about to read 3, iclass 15, count 0 2006.201.16:54:40.93#ibcon#read 3, iclass 15, count 0 2006.201.16:54:40.93#ibcon#about to read 4, iclass 15, count 0 2006.201.16:54:40.93#ibcon#read 4, iclass 15, count 0 2006.201.16:54:40.93#ibcon#about to read 5, iclass 15, count 0 2006.201.16:54:40.93#ibcon#read 5, iclass 15, count 0 2006.201.16:54:40.93#ibcon#about to read 6, iclass 15, count 0 2006.201.16:54:40.93#ibcon#read 6, iclass 15, count 0 2006.201.16:54:40.93#ibcon#end of sib2, iclass 15, count 0 2006.201.16:54:40.93#ibcon#*after write, iclass 15, count 0 2006.201.16:54:40.93#ibcon#*before return 0, iclass 15, count 0 2006.201.16:54:40.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:40.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.16:54:40.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.16:54:40.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.16:54:40.93$vck44/vb=8,4 2006.201.16:54:40.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.16:54:40.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.16:54:40.93#ibcon#ireg 11 cls_cnt 2 2006.201.16:54:40.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:40.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:40.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:40.98#ibcon#enter wrdev, iclass 17, count 2 2006.201.16:54:40.98#ibcon#first serial, iclass 17, count 2 2006.201.16:54:40.98#ibcon#enter sib2, iclass 17, count 2 2006.201.16:54:40.98#ibcon#flushed, iclass 17, count 2 2006.201.16:54:40.98#ibcon#about to write, iclass 17, count 2 2006.201.16:54:40.98#ibcon#wrote, iclass 17, count 2 2006.201.16:54:40.98#ibcon#about to read 3, iclass 17, count 2 2006.201.16:54:41.00#ibcon#read 3, iclass 17, count 2 2006.201.16:54:41.00#ibcon#about to read 4, iclass 17, count 2 2006.201.16:54:41.00#ibcon#read 4, iclass 17, count 2 2006.201.16:54:41.00#ibcon#about to read 5, iclass 17, count 2 2006.201.16:54:41.00#ibcon#read 5, iclass 17, count 2 2006.201.16:54:41.00#ibcon#about to read 6, iclass 17, count 2 2006.201.16:54:41.00#ibcon#read 6, iclass 17, count 2 2006.201.16:54:41.00#ibcon#end of sib2, iclass 17, count 2 2006.201.16:54:41.00#ibcon#*mode == 0, iclass 17, count 2 2006.201.16:54:41.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.16:54:41.00#ibcon#[27=AT08-04\r\n] 2006.201.16:54:41.00#ibcon#*before write, iclass 17, count 2 2006.201.16:54:41.00#ibcon#enter sib2, iclass 17, count 2 2006.201.16:54:41.00#ibcon#flushed, iclass 17, count 2 2006.201.16:54:41.00#ibcon#about to write, iclass 17, count 2 2006.201.16:54:41.00#ibcon#wrote, iclass 17, count 2 2006.201.16:54:41.00#ibcon#about to read 3, iclass 17, count 2 2006.201.16:54:41.03#ibcon#read 3, iclass 17, count 2 2006.201.16:54:41.03#ibcon#about to read 4, iclass 17, count 2 2006.201.16:54:41.03#ibcon#read 4, iclass 17, count 2 2006.201.16:54:41.03#ibcon#about to read 5, iclass 17, count 2 2006.201.16:54:41.03#ibcon#read 5, iclass 17, count 2 2006.201.16:54:41.03#ibcon#about to read 6, iclass 17, count 2 2006.201.16:54:41.03#ibcon#read 6, iclass 17, count 2 2006.201.16:54:41.03#ibcon#end of sib2, iclass 17, count 2 2006.201.16:54:41.03#ibcon#*after write, iclass 17, count 2 2006.201.16:54:41.03#ibcon#*before return 0, iclass 17, count 2 2006.201.16:54:41.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:41.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.16:54:41.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.16:54:41.03#ibcon#ireg 7 cls_cnt 0 2006.201.16:54:41.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:41.05#abcon#<5=/03 0.4 1.2 20.831001002.6\r\n> 2006.201.16:54:41.07#abcon#{5=INTERFACE CLEAR} 2006.201.16:54:41.13#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:54:41.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:41.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:41.15#ibcon#enter wrdev, iclass 17, count 0 2006.201.16:54:41.15#ibcon#first serial, iclass 17, count 0 2006.201.16:54:41.15#ibcon#enter sib2, iclass 17, count 0 2006.201.16:54:41.15#ibcon#flushed, iclass 17, count 0 2006.201.16:54:41.15#ibcon#about to write, iclass 17, count 0 2006.201.16:54:41.15#ibcon#wrote, iclass 17, count 0 2006.201.16:54:41.15#ibcon#about to read 3, iclass 17, count 0 2006.201.16:54:41.17#ibcon#read 3, iclass 17, count 0 2006.201.16:54:41.17#ibcon#about to read 4, iclass 17, count 0 2006.201.16:54:41.17#ibcon#read 4, iclass 17, count 0 2006.201.16:54:41.17#ibcon#about to read 5, iclass 17, count 0 2006.201.16:54:41.17#ibcon#read 5, iclass 17, count 0 2006.201.16:54:41.17#ibcon#about to read 6, iclass 17, count 0 2006.201.16:54:41.17#ibcon#read 6, iclass 17, count 0 2006.201.16:54:41.17#ibcon#end of sib2, iclass 17, count 0 2006.201.16:54:41.17#ibcon#*mode == 0, iclass 17, count 0 2006.201.16:54:41.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.16:54:41.17#ibcon#[27=USB\r\n] 2006.201.16:54:41.17#ibcon#*before write, iclass 17, count 0 2006.201.16:54:41.17#ibcon#enter sib2, iclass 17, count 0 2006.201.16:54:41.17#ibcon#flushed, iclass 17, count 0 2006.201.16:54:41.17#ibcon#about to write, iclass 17, count 0 2006.201.16:54:41.17#ibcon#wrote, iclass 17, count 0 2006.201.16:54:41.17#ibcon#about to read 3, iclass 17, count 0 2006.201.16:54:41.20#ibcon#read 3, iclass 17, count 0 2006.201.16:54:41.20#ibcon#about to read 4, iclass 17, count 0 2006.201.16:54:41.20#ibcon#read 4, iclass 17, count 0 2006.201.16:54:41.20#ibcon#about to read 5, iclass 17, count 0 2006.201.16:54:41.20#ibcon#read 5, iclass 17, count 0 2006.201.16:54:41.20#ibcon#about to read 6, iclass 17, count 0 2006.201.16:54:41.20#ibcon#read 6, iclass 17, count 0 2006.201.16:54:41.20#ibcon#end of sib2, iclass 17, count 0 2006.201.16:54:41.20#ibcon#*after write, iclass 17, count 0 2006.201.16:54:41.20#ibcon#*before return 0, iclass 17, count 0 2006.201.16:54:41.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:41.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.16:54:41.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.16:54:41.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.16:54:41.20$vck44/vabw=wide 2006.201.16:54:41.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.16:54:41.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.16:54:41.20#ibcon#ireg 8 cls_cnt 0 2006.201.16:54:41.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:41.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:41.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:41.20#ibcon#enter wrdev, iclass 23, count 0 2006.201.16:54:41.20#ibcon#first serial, iclass 23, count 0 2006.201.16:54:41.20#ibcon#enter sib2, iclass 23, count 0 2006.201.16:54:41.20#ibcon#flushed, iclass 23, count 0 2006.201.16:54:41.20#ibcon#about to write, iclass 23, count 0 2006.201.16:54:41.20#ibcon#wrote, iclass 23, count 0 2006.201.16:54:41.20#ibcon#about to read 3, iclass 23, count 0 2006.201.16:54:41.22#ibcon#read 3, iclass 23, count 0 2006.201.16:54:41.22#ibcon#about to read 4, iclass 23, count 0 2006.201.16:54:41.22#ibcon#read 4, iclass 23, count 0 2006.201.16:54:41.22#ibcon#about to read 5, iclass 23, count 0 2006.201.16:54:41.22#ibcon#read 5, iclass 23, count 0 2006.201.16:54:41.22#ibcon#about to read 6, iclass 23, count 0 2006.201.16:54:41.22#ibcon#read 6, iclass 23, count 0 2006.201.16:54:41.22#ibcon#end of sib2, iclass 23, count 0 2006.201.16:54:41.22#ibcon#*mode == 0, iclass 23, count 0 2006.201.16:54:41.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.16:54:41.22#ibcon#[25=BW32\r\n] 2006.201.16:54:41.22#ibcon#*before write, iclass 23, count 0 2006.201.16:54:41.22#ibcon#enter sib2, iclass 23, count 0 2006.201.16:54:41.22#ibcon#flushed, iclass 23, count 0 2006.201.16:54:41.22#ibcon#about to write, iclass 23, count 0 2006.201.16:54:41.22#ibcon#wrote, iclass 23, count 0 2006.201.16:54:41.22#ibcon#about to read 3, iclass 23, count 0 2006.201.16:54:41.25#ibcon#read 3, iclass 23, count 0 2006.201.16:54:41.25#ibcon#about to read 4, iclass 23, count 0 2006.201.16:54:41.25#ibcon#read 4, iclass 23, count 0 2006.201.16:54:41.25#ibcon#about to read 5, iclass 23, count 0 2006.201.16:54:41.25#ibcon#read 5, iclass 23, count 0 2006.201.16:54:41.25#ibcon#about to read 6, iclass 23, count 0 2006.201.16:54:41.25#ibcon#read 6, iclass 23, count 0 2006.201.16:54:41.25#ibcon#end of sib2, iclass 23, count 0 2006.201.16:54:41.25#ibcon#*after write, iclass 23, count 0 2006.201.16:54:41.25#ibcon#*before return 0, iclass 23, count 0 2006.201.16:54:41.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:41.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.16:54:41.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.16:54:41.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.16:54:41.25$vck44/vbbw=wide 2006.201.16:54:41.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.16:54:41.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.16:54:41.25#ibcon#ireg 8 cls_cnt 0 2006.201.16:54:41.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:54:41.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:54:41.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:54:41.32#ibcon#enter wrdev, iclass 25, count 0 2006.201.16:54:41.32#ibcon#first serial, iclass 25, count 0 2006.201.16:54:41.32#ibcon#enter sib2, iclass 25, count 0 2006.201.16:54:41.32#ibcon#flushed, iclass 25, count 0 2006.201.16:54:41.32#ibcon#about to write, iclass 25, count 0 2006.201.16:54:41.32#ibcon#wrote, iclass 25, count 0 2006.201.16:54:41.32#ibcon#about to read 3, iclass 25, count 0 2006.201.16:54:41.34#ibcon#read 3, iclass 25, count 0 2006.201.16:54:41.34#ibcon#about to read 4, iclass 25, count 0 2006.201.16:54:41.34#ibcon#read 4, iclass 25, count 0 2006.201.16:54:41.34#ibcon#about to read 5, iclass 25, count 0 2006.201.16:54:41.34#ibcon#read 5, iclass 25, count 0 2006.201.16:54:41.34#ibcon#about to read 6, iclass 25, count 0 2006.201.16:54:41.34#ibcon#read 6, iclass 25, count 0 2006.201.16:54:41.34#ibcon#end of sib2, iclass 25, count 0 2006.201.16:54:41.34#ibcon#*mode == 0, iclass 25, count 0 2006.201.16:54:41.34#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.16:54:41.34#ibcon#[27=BW32\r\n] 2006.201.16:54:41.34#ibcon#*before write, iclass 25, count 0 2006.201.16:54:41.34#ibcon#enter sib2, iclass 25, count 0 2006.201.16:54:41.34#ibcon#flushed, iclass 25, count 0 2006.201.16:54:41.34#ibcon#about to write, iclass 25, count 0 2006.201.16:54:41.34#ibcon#wrote, iclass 25, count 0 2006.201.16:54:41.34#ibcon#about to read 3, iclass 25, count 0 2006.201.16:54:41.37#ibcon#read 3, iclass 25, count 0 2006.201.16:54:41.37#ibcon#about to read 4, iclass 25, count 0 2006.201.16:54:41.37#ibcon#read 4, iclass 25, count 0 2006.201.16:54:41.37#ibcon#about to read 5, iclass 25, count 0 2006.201.16:54:41.37#ibcon#read 5, iclass 25, count 0 2006.201.16:54:41.37#ibcon#about to read 6, iclass 25, count 0 2006.201.16:54:41.37#ibcon#read 6, iclass 25, count 0 2006.201.16:54:41.37#ibcon#end of sib2, iclass 25, count 0 2006.201.16:54:41.37#ibcon#*after write, iclass 25, count 0 2006.201.16:54:41.37#ibcon#*before return 0, iclass 25, count 0 2006.201.16:54:41.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:54:41.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.16:54:41.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.16:54:41.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.16:54:41.37$setupk4/ifdk4 2006.201.16:54:41.37$ifdk4/lo= 2006.201.16:54:41.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:54:41.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:54:41.37$ifdk4/patch= 2006.201.16:54:41.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:54:41.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:54:41.37$setupk4/!*+20s 2006.201.16:54:51.22#abcon#<5=/03 0.4 1.2 20.831001002.6\r\n> 2006.201.16:54:51.24#abcon#{5=INTERFACE CLEAR} 2006.201.16:54:51.30#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:54:55.86$setupk4/"tpicd 2006.201.16:54:55.86$setupk4/echo=off 2006.201.16:54:55.86$setupk4/xlog=off 2006.201.16:54:55.86:!2006.201.16:56:31 2006.201.16:55:13.13#trakl#Source acquired 2006.201.16:55:13.13#flagr#flagr/antenna,acquired 2006.201.16:56:31.00:preob 2006.201.16:56:32.14/onsource/TRACKING 2006.201.16:56:32.14:!2006.201.16:56:41 2006.201.16:56:41.00:"tape 2006.201.16:56:41.00:"st=record 2006.201.16:56:41.00:data_valid=on 2006.201.16:56:41.00:midob 2006.201.16:56:41.14/onsource/TRACKING 2006.201.16:56:41.14/wx/20.82,1002.6,100 2006.201.16:56:41.20/cable/+6.4765E-03 2006.201.16:56:42.29/va/01,08,usb,yes,45,48 2006.201.16:56:42.29/va/02,07,usb,yes,48,49 2006.201.16:56:42.29/va/03,08,usb,yes,44,46 2006.201.16:56:42.29/va/04,07,usb,yes,50,52 2006.201.16:56:42.29/va/05,04,usb,yes,44,45 2006.201.16:56:42.29/va/06,05,usb,yes,44,44 2006.201.16:56:42.29/va/07,05,usb,yes,43,45 2006.201.16:56:42.29/va/08,04,usb,yes,43,51 2006.201.16:56:42.52/valo/01,524.99,yes,locked 2006.201.16:56:42.52/valo/02,534.99,yes,locked 2006.201.16:56:42.52/valo/03,564.99,yes,locked 2006.201.16:56:42.52/valo/04,624.99,yes,locked 2006.201.16:56:42.52/valo/05,734.99,yes,locked 2006.201.16:56:42.52/valo/06,814.99,yes,locked 2006.201.16:56:42.52/valo/07,864.99,yes,locked 2006.201.16:56:42.52/valo/08,884.99,yes,locked 2006.201.16:56:43.61/vb/01,04,usb,yes,34,32 2006.201.16:56:43.61/vb/02,05,usb,yes,32,32 2006.201.16:56:43.61/vb/03,04,usb,yes,33,37 2006.201.16:56:43.61/vb/04,05,usb,yes,34,33 2006.201.16:56:43.61/vb/05,04,usb,yes,30,33 2006.201.16:56:43.61/vb/06,04,usb,yes,35,31 2006.201.16:56:43.61/vb/07,04,usb,yes,35,35 2006.201.16:56:43.61/vb/08,04,usb,yes,32,36 2006.201.16:56:43.85/vblo/01,629.99,yes,locked 2006.201.16:56:43.85/vblo/02,634.99,yes,locked 2006.201.16:56:43.85/vblo/03,649.99,yes,locked 2006.201.16:56:43.85/vblo/04,679.99,yes,locked 2006.201.16:56:43.85/vblo/05,709.99,yes,locked 2006.201.16:56:43.85/vblo/06,719.99,yes,locked 2006.201.16:56:43.85/vblo/07,734.99,yes,locked 2006.201.16:56:43.85/vblo/08,744.99,yes,locked 2006.201.16:56:44.00/vabw/8 2006.201.16:56:44.15/vbbw/8 2006.201.16:56:44.24/xfe/off,on,15.2 2006.201.16:56:44.62/ifatt/23,28,28,28 2006.201.16:56:45.07/fmout-gps/S +4.57E-07 2006.201.16:56:45.11:!2006.201.16:58:31 2006.201.16:58:31.00:data_valid=off 2006.201.16:58:31.00:"et 2006.201.16:58:31.00:!+3s 2006.201.16:58:34.02:"tape 2006.201.16:58:34.02:postob 2006.201.16:58:34.21/cable/+6.4764E-03 2006.201.16:58:34.21/wx/20.80,1002.6,100 2006.201.16:58:34.28/fmout-gps/S +4.55E-07 2006.201.16:58:34.28:scan_name=201-1659,jd0607,140 2006.201.16:58:34.28:source=cta26,033930.94,-014635.8,2000.0,cw 2006.201.16:58:35.14#flagr#flagr/antenna,new-source 2006.201.16:58:35.14:checkk5 2006.201.16:58:35.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.16:58:35.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.16:58:36.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.16:58:36.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.16:58:37.02/chk_obsdata//k5ts1/T2011656??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.16:58:37.38/chk_obsdata//k5ts2/T2011656??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.16:58:37.75/chk_obsdata//k5ts3/T2011656??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.16:58:38.11/chk_obsdata//k5ts4/T2011656??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.16:58:38.82/k5log//k5ts1_log_newline 2006.201.16:58:39.51/k5log//k5ts2_log_newline 2006.201.16:58:40.20/k5log//k5ts3_log_newline 2006.201.16:58:40.88/k5log//k5ts4_log_newline 2006.201.16:58:40.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.16:58:40.91:setupk4=1 2006.201.16:58:40.91$setupk4/echo=on 2006.201.16:58:40.91$setupk4/pcalon 2006.201.16:58:40.91$pcalon/"no phase cal control is implemented here 2006.201.16:58:40.91$setupk4/"tpicd=stop 2006.201.16:58:40.91$setupk4/"rec=synch_on 2006.201.16:58:40.91$setupk4/"rec_mode=128 2006.201.16:58:40.91$setupk4/!* 2006.201.16:58:40.91$setupk4/recpk4 2006.201.16:58:40.91$recpk4/recpatch= 2006.201.16:58:40.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.16:58:40.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.16:58:40.91$setupk4/vck44 2006.201.16:58:40.91$vck44/valo=1,524.99 2006.201.16:58:40.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.16:58:40.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.16:58:40.91#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:40.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:40.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:40.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:40.91#ibcon#enter wrdev, iclass 14, count 0 2006.201.16:58:40.91#ibcon#first serial, iclass 14, count 0 2006.201.16:58:40.91#ibcon#enter sib2, iclass 14, count 0 2006.201.16:58:40.91#ibcon#flushed, iclass 14, count 0 2006.201.16:58:40.91#ibcon#about to write, iclass 14, count 0 2006.201.16:58:40.91#ibcon#wrote, iclass 14, count 0 2006.201.16:58:40.91#ibcon#about to read 3, iclass 14, count 0 2006.201.16:58:40.95#ibcon#read 3, iclass 14, count 0 2006.201.16:58:40.95#ibcon#about to read 4, iclass 14, count 0 2006.201.16:58:40.95#ibcon#read 4, iclass 14, count 0 2006.201.16:58:40.95#ibcon#about to read 5, iclass 14, count 0 2006.201.16:58:40.95#ibcon#read 5, iclass 14, count 0 2006.201.16:58:40.95#ibcon#about to read 6, iclass 14, count 0 2006.201.16:58:40.95#ibcon#read 6, iclass 14, count 0 2006.201.16:58:40.95#ibcon#end of sib2, iclass 14, count 0 2006.201.16:58:40.95#ibcon#*mode == 0, iclass 14, count 0 2006.201.16:58:40.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.16:58:40.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.16:58:40.95#ibcon#*before write, iclass 14, count 0 2006.201.16:58:40.95#ibcon#enter sib2, iclass 14, count 0 2006.201.16:58:40.95#ibcon#flushed, iclass 14, count 0 2006.201.16:58:40.95#ibcon#about to write, iclass 14, count 0 2006.201.16:58:40.95#ibcon#wrote, iclass 14, count 0 2006.201.16:58:40.95#ibcon#about to read 3, iclass 14, count 0 2006.201.16:58:41.00#ibcon#read 3, iclass 14, count 0 2006.201.16:58:41.00#ibcon#about to read 4, iclass 14, count 0 2006.201.16:58:41.00#ibcon#read 4, iclass 14, count 0 2006.201.16:58:41.00#ibcon#about to read 5, iclass 14, count 0 2006.201.16:58:41.00#ibcon#read 5, iclass 14, count 0 2006.201.16:58:41.00#ibcon#about to read 6, iclass 14, count 0 2006.201.16:58:41.00#ibcon#read 6, iclass 14, count 0 2006.201.16:58:41.00#ibcon#end of sib2, iclass 14, count 0 2006.201.16:58:41.00#ibcon#*after write, iclass 14, count 0 2006.201.16:58:41.00#ibcon#*before return 0, iclass 14, count 0 2006.201.16:58:41.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:41.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:41.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.16:58:41.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.16:58:41.00$vck44/va=1,8 2006.201.16:58:41.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.16:58:41.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.16:58:41.00#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:41.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:41.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:41.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:41.00#ibcon#enter wrdev, iclass 16, count 2 2006.201.16:58:41.00#ibcon#first serial, iclass 16, count 2 2006.201.16:58:41.00#ibcon#enter sib2, iclass 16, count 2 2006.201.16:58:41.00#ibcon#flushed, iclass 16, count 2 2006.201.16:58:41.00#ibcon#about to write, iclass 16, count 2 2006.201.16:58:41.00#ibcon#wrote, iclass 16, count 2 2006.201.16:58:41.00#ibcon#about to read 3, iclass 16, count 2 2006.201.16:58:41.02#ibcon#read 3, iclass 16, count 2 2006.201.16:58:41.02#ibcon#about to read 4, iclass 16, count 2 2006.201.16:58:41.02#ibcon#read 4, iclass 16, count 2 2006.201.16:58:41.02#ibcon#about to read 5, iclass 16, count 2 2006.201.16:58:41.02#ibcon#read 5, iclass 16, count 2 2006.201.16:58:41.02#ibcon#about to read 6, iclass 16, count 2 2006.201.16:58:41.02#ibcon#read 6, iclass 16, count 2 2006.201.16:58:41.02#ibcon#end of sib2, iclass 16, count 2 2006.201.16:58:41.02#ibcon#*mode == 0, iclass 16, count 2 2006.201.16:58:41.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.16:58:41.02#ibcon#[25=AT01-08\r\n] 2006.201.16:58:41.02#ibcon#*before write, iclass 16, count 2 2006.201.16:58:41.02#ibcon#enter sib2, iclass 16, count 2 2006.201.16:58:41.02#ibcon#flushed, iclass 16, count 2 2006.201.16:58:41.02#ibcon#about to write, iclass 16, count 2 2006.201.16:58:41.02#ibcon#wrote, iclass 16, count 2 2006.201.16:58:41.02#ibcon#about to read 3, iclass 16, count 2 2006.201.16:58:41.06#ibcon#read 3, iclass 16, count 2 2006.201.16:58:41.06#ibcon#about to read 4, iclass 16, count 2 2006.201.16:58:41.06#ibcon#read 4, iclass 16, count 2 2006.201.16:58:41.06#ibcon#about to read 5, iclass 16, count 2 2006.201.16:58:41.06#ibcon#read 5, iclass 16, count 2 2006.201.16:58:41.06#ibcon#about to read 6, iclass 16, count 2 2006.201.16:58:41.06#ibcon#read 6, iclass 16, count 2 2006.201.16:58:41.06#ibcon#end of sib2, iclass 16, count 2 2006.201.16:58:41.06#ibcon#*after write, iclass 16, count 2 2006.201.16:58:41.06#ibcon#*before return 0, iclass 16, count 2 2006.201.16:58:41.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:41.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:41.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.16:58:41.06#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:41.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:41.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:41.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:41.18#ibcon#enter wrdev, iclass 16, count 0 2006.201.16:58:41.18#ibcon#first serial, iclass 16, count 0 2006.201.16:58:41.18#ibcon#enter sib2, iclass 16, count 0 2006.201.16:58:41.18#ibcon#flushed, iclass 16, count 0 2006.201.16:58:41.18#ibcon#about to write, iclass 16, count 0 2006.201.16:58:41.18#ibcon#wrote, iclass 16, count 0 2006.201.16:58:41.18#ibcon#about to read 3, iclass 16, count 0 2006.201.16:58:41.21#ibcon#read 3, iclass 16, count 0 2006.201.16:58:41.21#ibcon#about to read 4, iclass 16, count 0 2006.201.16:58:41.21#ibcon#read 4, iclass 16, count 0 2006.201.16:58:41.21#ibcon#about to read 5, iclass 16, count 0 2006.201.16:58:41.21#ibcon#read 5, iclass 16, count 0 2006.201.16:58:41.21#ibcon#about to read 6, iclass 16, count 0 2006.201.16:58:41.21#ibcon#read 6, iclass 16, count 0 2006.201.16:58:41.21#ibcon#end of sib2, iclass 16, count 0 2006.201.16:58:41.21#ibcon#*mode == 0, iclass 16, count 0 2006.201.16:58:41.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.16:58:41.21#ibcon#[25=USB\r\n] 2006.201.16:58:41.21#ibcon#*before write, iclass 16, count 0 2006.201.16:58:41.21#ibcon#enter sib2, iclass 16, count 0 2006.201.16:58:41.21#ibcon#flushed, iclass 16, count 0 2006.201.16:58:41.21#ibcon#about to write, iclass 16, count 0 2006.201.16:58:41.21#ibcon#wrote, iclass 16, count 0 2006.201.16:58:41.21#ibcon#about to read 3, iclass 16, count 0 2006.201.16:58:41.24#ibcon#read 3, iclass 16, count 0 2006.201.16:58:41.24#ibcon#about to read 4, iclass 16, count 0 2006.201.16:58:41.24#ibcon#read 4, iclass 16, count 0 2006.201.16:58:41.24#ibcon#about to read 5, iclass 16, count 0 2006.201.16:58:41.24#ibcon#read 5, iclass 16, count 0 2006.201.16:58:41.24#ibcon#about to read 6, iclass 16, count 0 2006.201.16:58:41.24#ibcon#read 6, iclass 16, count 0 2006.201.16:58:41.24#ibcon#end of sib2, iclass 16, count 0 2006.201.16:58:41.24#ibcon#*after write, iclass 16, count 0 2006.201.16:58:41.24#ibcon#*before return 0, iclass 16, count 0 2006.201.16:58:41.24#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:41.24#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:41.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.16:58:41.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.16:58:41.24$vck44/valo=2,534.99 2006.201.16:58:41.24#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.16:58:41.24#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.16:58:41.24#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:41.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:41.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:41.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:41.24#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:58:41.24#ibcon#first serial, iclass 18, count 0 2006.201.16:58:41.24#ibcon#enter sib2, iclass 18, count 0 2006.201.16:58:41.24#ibcon#flushed, iclass 18, count 0 2006.201.16:58:41.24#ibcon#about to write, iclass 18, count 0 2006.201.16:58:41.24#ibcon#wrote, iclass 18, count 0 2006.201.16:58:41.24#ibcon#about to read 3, iclass 18, count 0 2006.201.16:58:41.26#ibcon#read 3, iclass 18, count 0 2006.201.16:58:41.26#ibcon#about to read 4, iclass 18, count 0 2006.201.16:58:41.26#ibcon#read 4, iclass 18, count 0 2006.201.16:58:41.26#ibcon#about to read 5, iclass 18, count 0 2006.201.16:58:41.26#ibcon#read 5, iclass 18, count 0 2006.201.16:58:41.26#ibcon#about to read 6, iclass 18, count 0 2006.201.16:58:41.26#ibcon#read 6, iclass 18, count 0 2006.201.16:58:41.26#ibcon#end of sib2, iclass 18, count 0 2006.201.16:58:41.26#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:58:41.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:58:41.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.16:58:41.26#ibcon#*before write, iclass 18, count 0 2006.201.16:58:41.26#ibcon#enter sib2, iclass 18, count 0 2006.201.16:58:41.26#ibcon#flushed, iclass 18, count 0 2006.201.16:58:41.26#ibcon#about to write, iclass 18, count 0 2006.201.16:58:41.26#ibcon#wrote, iclass 18, count 0 2006.201.16:58:41.26#ibcon#about to read 3, iclass 18, count 0 2006.201.16:58:41.30#ibcon#read 3, iclass 18, count 0 2006.201.16:58:41.30#ibcon#about to read 4, iclass 18, count 0 2006.201.16:58:41.30#ibcon#read 4, iclass 18, count 0 2006.201.16:58:41.30#ibcon#about to read 5, iclass 18, count 0 2006.201.16:58:41.30#ibcon#read 5, iclass 18, count 0 2006.201.16:58:41.30#ibcon#about to read 6, iclass 18, count 0 2006.201.16:58:41.30#ibcon#read 6, iclass 18, count 0 2006.201.16:58:41.30#ibcon#end of sib2, iclass 18, count 0 2006.201.16:58:41.30#ibcon#*after write, iclass 18, count 0 2006.201.16:58:41.30#ibcon#*before return 0, iclass 18, count 0 2006.201.16:58:41.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:41.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:41.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:58:41.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:58:41.30$vck44/va=2,7 2006.201.16:58:41.30#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.16:58:41.30#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.16:58:41.30#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:41.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:41.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:41.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:41.36#ibcon#enter wrdev, iclass 20, count 2 2006.201.16:58:41.36#ibcon#first serial, iclass 20, count 2 2006.201.16:58:41.36#ibcon#enter sib2, iclass 20, count 2 2006.201.16:58:41.36#ibcon#flushed, iclass 20, count 2 2006.201.16:58:41.36#ibcon#about to write, iclass 20, count 2 2006.201.16:58:41.36#ibcon#wrote, iclass 20, count 2 2006.201.16:58:41.36#ibcon#about to read 3, iclass 20, count 2 2006.201.16:58:41.38#ibcon#read 3, iclass 20, count 2 2006.201.16:58:41.38#ibcon#about to read 4, iclass 20, count 2 2006.201.16:58:41.38#ibcon#read 4, iclass 20, count 2 2006.201.16:58:41.38#ibcon#about to read 5, iclass 20, count 2 2006.201.16:58:41.38#ibcon#read 5, iclass 20, count 2 2006.201.16:58:41.38#ibcon#about to read 6, iclass 20, count 2 2006.201.16:58:41.38#ibcon#read 6, iclass 20, count 2 2006.201.16:58:41.38#ibcon#end of sib2, iclass 20, count 2 2006.201.16:58:41.38#ibcon#*mode == 0, iclass 20, count 2 2006.201.16:58:41.38#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.16:58:41.38#ibcon#[25=AT02-07\r\n] 2006.201.16:58:41.38#ibcon#*before write, iclass 20, count 2 2006.201.16:58:41.38#ibcon#enter sib2, iclass 20, count 2 2006.201.16:58:41.38#ibcon#flushed, iclass 20, count 2 2006.201.16:58:41.38#ibcon#about to write, iclass 20, count 2 2006.201.16:58:41.38#ibcon#wrote, iclass 20, count 2 2006.201.16:58:41.38#ibcon#about to read 3, iclass 20, count 2 2006.201.16:58:41.41#ibcon#read 3, iclass 20, count 2 2006.201.16:58:41.41#ibcon#about to read 4, iclass 20, count 2 2006.201.16:58:41.41#ibcon#read 4, iclass 20, count 2 2006.201.16:58:41.41#ibcon#about to read 5, iclass 20, count 2 2006.201.16:58:41.41#ibcon#read 5, iclass 20, count 2 2006.201.16:58:41.41#ibcon#about to read 6, iclass 20, count 2 2006.201.16:58:41.41#ibcon#read 6, iclass 20, count 2 2006.201.16:58:41.41#ibcon#end of sib2, iclass 20, count 2 2006.201.16:58:41.41#ibcon#*after write, iclass 20, count 2 2006.201.16:58:41.41#ibcon#*before return 0, iclass 20, count 2 2006.201.16:58:41.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:41.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:41.41#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.16:58:41.41#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:41.41#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:41.53#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:41.53#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:41.53#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:58:41.53#ibcon#first serial, iclass 20, count 0 2006.201.16:58:41.53#ibcon#enter sib2, iclass 20, count 0 2006.201.16:58:41.53#ibcon#flushed, iclass 20, count 0 2006.201.16:58:41.53#ibcon#about to write, iclass 20, count 0 2006.201.16:58:41.53#ibcon#wrote, iclass 20, count 0 2006.201.16:58:41.53#ibcon#about to read 3, iclass 20, count 0 2006.201.16:58:41.55#ibcon#read 3, iclass 20, count 0 2006.201.16:58:41.55#ibcon#about to read 4, iclass 20, count 0 2006.201.16:58:41.55#ibcon#read 4, iclass 20, count 0 2006.201.16:58:41.55#ibcon#about to read 5, iclass 20, count 0 2006.201.16:58:41.55#ibcon#read 5, iclass 20, count 0 2006.201.16:58:41.55#ibcon#about to read 6, iclass 20, count 0 2006.201.16:58:41.55#ibcon#read 6, iclass 20, count 0 2006.201.16:58:41.55#ibcon#end of sib2, iclass 20, count 0 2006.201.16:58:41.55#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:58:41.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:58:41.55#ibcon#[25=USB\r\n] 2006.201.16:58:41.55#ibcon#*before write, iclass 20, count 0 2006.201.16:58:41.55#ibcon#enter sib2, iclass 20, count 0 2006.201.16:58:41.55#ibcon#flushed, iclass 20, count 0 2006.201.16:58:41.55#ibcon#about to write, iclass 20, count 0 2006.201.16:58:41.55#ibcon#wrote, iclass 20, count 0 2006.201.16:58:41.55#ibcon#about to read 3, iclass 20, count 0 2006.201.16:58:41.58#ibcon#read 3, iclass 20, count 0 2006.201.16:58:41.58#ibcon#about to read 4, iclass 20, count 0 2006.201.16:58:41.58#ibcon#read 4, iclass 20, count 0 2006.201.16:58:41.58#ibcon#about to read 5, iclass 20, count 0 2006.201.16:58:41.58#ibcon#read 5, iclass 20, count 0 2006.201.16:58:41.58#ibcon#about to read 6, iclass 20, count 0 2006.201.16:58:41.58#ibcon#read 6, iclass 20, count 0 2006.201.16:58:41.58#ibcon#end of sib2, iclass 20, count 0 2006.201.16:58:41.58#ibcon#*after write, iclass 20, count 0 2006.201.16:58:41.58#ibcon#*before return 0, iclass 20, count 0 2006.201.16:58:41.58#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:41.58#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:41.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:58:41.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:58:41.58$vck44/valo=3,564.99 2006.201.16:58:41.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.16:58:41.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.16:58:41.58#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:41.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:41.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:41.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:41.58#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:58:41.58#ibcon#first serial, iclass 22, count 0 2006.201.16:58:41.58#ibcon#enter sib2, iclass 22, count 0 2006.201.16:58:41.58#ibcon#flushed, iclass 22, count 0 2006.201.16:58:41.58#ibcon#about to write, iclass 22, count 0 2006.201.16:58:41.58#ibcon#wrote, iclass 22, count 0 2006.201.16:58:41.58#ibcon#about to read 3, iclass 22, count 0 2006.201.16:58:41.60#ibcon#read 3, iclass 22, count 0 2006.201.16:58:41.60#ibcon#about to read 4, iclass 22, count 0 2006.201.16:58:41.60#ibcon#read 4, iclass 22, count 0 2006.201.16:58:41.60#ibcon#about to read 5, iclass 22, count 0 2006.201.16:58:41.60#ibcon#read 5, iclass 22, count 0 2006.201.16:58:41.60#ibcon#about to read 6, iclass 22, count 0 2006.201.16:58:41.60#ibcon#read 6, iclass 22, count 0 2006.201.16:58:41.60#ibcon#end of sib2, iclass 22, count 0 2006.201.16:58:41.60#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:58:41.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:58:41.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.16:58:41.60#ibcon#*before write, iclass 22, count 0 2006.201.16:58:41.60#ibcon#enter sib2, iclass 22, count 0 2006.201.16:58:41.60#ibcon#flushed, iclass 22, count 0 2006.201.16:58:41.60#ibcon#about to write, iclass 22, count 0 2006.201.16:58:41.60#ibcon#wrote, iclass 22, count 0 2006.201.16:58:41.60#ibcon#about to read 3, iclass 22, count 0 2006.201.16:58:41.64#ibcon#read 3, iclass 22, count 0 2006.201.16:58:41.64#ibcon#about to read 4, iclass 22, count 0 2006.201.16:58:41.64#ibcon#read 4, iclass 22, count 0 2006.201.16:58:41.64#ibcon#about to read 5, iclass 22, count 0 2006.201.16:58:41.64#ibcon#read 5, iclass 22, count 0 2006.201.16:58:41.64#ibcon#about to read 6, iclass 22, count 0 2006.201.16:58:41.64#ibcon#read 6, iclass 22, count 0 2006.201.16:58:41.64#ibcon#end of sib2, iclass 22, count 0 2006.201.16:58:41.64#ibcon#*after write, iclass 22, count 0 2006.201.16:58:41.64#ibcon#*before return 0, iclass 22, count 0 2006.201.16:58:41.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:41.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:41.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:58:41.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:58:41.64$vck44/va=3,8 2006.201.16:58:41.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.16:58:41.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.16:58:41.64#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:41.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:41.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:41.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:41.70#ibcon#enter wrdev, iclass 24, count 2 2006.201.16:58:41.70#ibcon#first serial, iclass 24, count 2 2006.201.16:58:41.70#ibcon#enter sib2, iclass 24, count 2 2006.201.16:58:41.70#ibcon#flushed, iclass 24, count 2 2006.201.16:58:41.70#ibcon#about to write, iclass 24, count 2 2006.201.16:58:41.70#ibcon#wrote, iclass 24, count 2 2006.201.16:58:41.70#ibcon#about to read 3, iclass 24, count 2 2006.201.16:58:41.72#ibcon#read 3, iclass 24, count 2 2006.201.16:58:41.72#ibcon#about to read 4, iclass 24, count 2 2006.201.16:58:41.72#ibcon#read 4, iclass 24, count 2 2006.201.16:58:41.72#ibcon#about to read 5, iclass 24, count 2 2006.201.16:58:41.72#ibcon#read 5, iclass 24, count 2 2006.201.16:58:41.72#ibcon#about to read 6, iclass 24, count 2 2006.201.16:58:41.72#ibcon#read 6, iclass 24, count 2 2006.201.16:58:41.72#ibcon#end of sib2, iclass 24, count 2 2006.201.16:58:41.72#ibcon#*mode == 0, iclass 24, count 2 2006.201.16:58:41.72#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.16:58:41.72#ibcon#[25=AT03-08\r\n] 2006.201.16:58:41.72#ibcon#*before write, iclass 24, count 2 2006.201.16:58:41.72#ibcon#enter sib2, iclass 24, count 2 2006.201.16:58:41.72#ibcon#flushed, iclass 24, count 2 2006.201.16:58:41.72#ibcon#about to write, iclass 24, count 2 2006.201.16:58:41.72#ibcon#wrote, iclass 24, count 2 2006.201.16:58:41.72#ibcon#about to read 3, iclass 24, count 2 2006.201.16:58:41.75#ibcon#read 3, iclass 24, count 2 2006.201.16:58:41.75#ibcon#about to read 4, iclass 24, count 2 2006.201.16:58:41.75#ibcon#read 4, iclass 24, count 2 2006.201.16:58:41.75#ibcon#about to read 5, iclass 24, count 2 2006.201.16:58:41.75#ibcon#read 5, iclass 24, count 2 2006.201.16:58:41.75#ibcon#about to read 6, iclass 24, count 2 2006.201.16:58:41.75#ibcon#read 6, iclass 24, count 2 2006.201.16:58:41.75#ibcon#end of sib2, iclass 24, count 2 2006.201.16:58:41.75#ibcon#*after write, iclass 24, count 2 2006.201.16:58:41.75#ibcon#*before return 0, iclass 24, count 2 2006.201.16:58:41.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:41.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:41.75#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.16:58:41.75#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:41.75#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:41.87#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:41.87#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:41.87#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:58:41.87#ibcon#first serial, iclass 24, count 0 2006.201.16:58:41.87#ibcon#enter sib2, iclass 24, count 0 2006.201.16:58:41.87#ibcon#flushed, iclass 24, count 0 2006.201.16:58:41.87#ibcon#about to write, iclass 24, count 0 2006.201.16:58:41.87#ibcon#wrote, iclass 24, count 0 2006.201.16:58:41.87#ibcon#about to read 3, iclass 24, count 0 2006.201.16:58:41.89#ibcon#read 3, iclass 24, count 0 2006.201.16:58:41.89#ibcon#about to read 4, iclass 24, count 0 2006.201.16:58:41.89#ibcon#read 4, iclass 24, count 0 2006.201.16:58:41.89#ibcon#about to read 5, iclass 24, count 0 2006.201.16:58:41.89#ibcon#read 5, iclass 24, count 0 2006.201.16:58:41.89#ibcon#about to read 6, iclass 24, count 0 2006.201.16:58:41.89#ibcon#read 6, iclass 24, count 0 2006.201.16:58:41.89#ibcon#end of sib2, iclass 24, count 0 2006.201.16:58:41.89#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:58:41.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:58:41.89#ibcon#[25=USB\r\n] 2006.201.16:58:41.89#ibcon#*before write, iclass 24, count 0 2006.201.16:58:41.89#ibcon#enter sib2, iclass 24, count 0 2006.201.16:58:41.89#ibcon#flushed, iclass 24, count 0 2006.201.16:58:41.89#ibcon#about to write, iclass 24, count 0 2006.201.16:58:41.89#ibcon#wrote, iclass 24, count 0 2006.201.16:58:41.89#ibcon#about to read 3, iclass 24, count 0 2006.201.16:58:41.92#ibcon#read 3, iclass 24, count 0 2006.201.16:58:41.92#ibcon#about to read 4, iclass 24, count 0 2006.201.16:58:41.92#ibcon#read 4, iclass 24, count 0 2006.201.16:58:41.92#ibcon#about to read 5, iclass 24, count 0 2006.201.16:58:41.92#ibcon#read 5, iclass 24, count 0 2006.201.16:58:41.92#ibcon#about to read 6, iclass 24, count 0 2006.201.16:58:41.92#ibcon#read 6, iclass 24, count 0 2006.201.16:58:41.92#ibcon#end of sib2, iclass 24, count 0 2006.201.16:58:41.92#ibcon#*after write, iclass 24, count 0 2006.201.16:58:41.92#ibcon#*before return 0, iclass 24, count 0 2006.201.16:58:41.92#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:41.92#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:41.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:58:41.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:58:41.92$vck44/valo=4,624.99 2006.201.16:58:41.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.16:58:41.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.16:58:41.92#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:41.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:41.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:41.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:41.92#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:58:41.92#ibcon#first serial, iclass 26, count 0 2006.201.16:58:41.92#ibcon#enter sib2, iclass 26, count 0 2006.201.16:58:41.92#ibcon#flushed, iclass 26, count 0 2006.201.16:58:41.92#ibcon#about to write, iclass 26, count 0 2006.201.16:58:41.92#ibcon#wrote, iclass 26, count 0 2006.201.16:58:41.92#ibcon#about to read 3, iclass 26, count 0 2006.201.16:58:41.94#ibcon#read 3, iclass 26, count 0 2006.201.16:58:41.94#ibcon#about to read 4, iclass 26, count 0 2006.201.16:58:41.94#ibcon#read 4, iclass 26, count 0 2006.201.16:58:41.94#ibcon#about to read 5, iclass 26, count 0 2006.201.16:58:41.94#ibcon#read 5, iclass 26, count 0 2006.201.16:58:41.94#ibcon#about to read 6, iclass 26, count 0 2006.201.16:58:41.94#ibcon#read 6, iclass 26, count 0 2006.201.16:58:41.94#ibcon#end of sib2, iclass 26, count 0 2006.201.16:58:41.94#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:58:41.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:58:41.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.16:58:41.94#ibcon#*before write, iclass 26, count 0 2006.201.16:58:41.94#ibcon#enter sib2, iclass 26, count 0 2006.201.16:58:41.94#ibcon#flushed, iclass 26, count 0 2006.201.16:58:41.94#ibcon#about to write, iclass 26, count 0 2006.201.16:58:41.94#ibcon#wrote, iclass 26, count 0 2006.201.16:58:41.94#ibcon#about to read 3, iclass 26, count 0 2006.201.16:58:41.98#ibcon#read 3, iclass 26, count 0 2006.201.16:58:41.98#ibcon#about to read 4, iclass 26, count 0 2006.201.16:58:41.98#ibcon#read 4, iclass 26, count 0 2006.201.16:58:41.98#ibcon#about to read 5, iclass 26, count 0 2006.201.16:58:41.98#ibcon#read 5, iclass 26, count 0 2006.201.16:58:41.98#ibcon#about to read 6, iclass 26, count 0 2006.201.16:58:41.98#ibcon#read 6, iclass 26, count 0 2006.201.16:58:41.98#ibcon#end of sib2, iclass 26, count 0 2006.201.16:58:41.98#ibcon#*after write, iclass 26, count 0 2006.201.16:58:41.98#ibcon#*before return 0, iclass 26, count 0 2006.201.16:58:41.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:41.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:41.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:58:41.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:58:41.98$vck44/va=4,7 2006.201.16:58:41.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.16:58:41.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.16:58:41.98#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:41.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:42.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:42.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:42.04#ibcon#enter wrdev, iclass 28, count 2 2006.201.16:58:42.04#ibcon#first serial, iclass 28, count 2 2006.201.16:58:42.04#ibcon#enter sib2, iclass 28, count 2 2006.201.16:58:42.04#ibcon#flushed, iclass 28, count 2 2006.201.16:58:42.04#ibcon#about to write, iclass 28, count 2 2006.201.16:58:42.04#ibcon#wrote, iclass 28, count 2 2006.201.16:58:42.04#ibcon#about to read 3, iclass 28, count 2 2006.201.16:58:42.06#ibcon#read 3, iclass 28, count 2 2006.201.16:58:42.06#ibcon#about to read 4, iclass 28, count 2 2006.201.16:58:42.06#ibcon#read 4, iclass 28, count 2 2006.201.16:58:42.06#ibcon#about to read 5, iclass 28, count 2 2006.201.16:58:42.06#ibcon#read 5, iclass 28, count 2 2006.201.16:58:42.06#ibcon#about to read 6, iclass 28, count 2 2006.201.16:58:42.06#ibcon#read 6, iclass 28, count 2 2006.201.16:58:42.06#ibcon#end of sib2, iclass 28, count 2 2006.201.16:58:42.06#ibcon#*mode == 0, iclass 28, count 2 2006.201.16:58:42.06#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.16:58:42.06#ibcon#[25=AT04-07\r\n] 2006.201.16:58:42.06#ibcon#*before write, iclass 28, count 2 2006.201.16:58:42.06#ibcon#enter sib2, iclass 28, count 2 2006.201.16:58:42.06#ibcon#flushed, iclass 28, count 2 2006.201.16:58:42.06#ibcon#about to write, iclass 28, count 2 2006.201.16:58:42.06#ibcon#wrote, iclass 28, count 2 2006.201.16:58:42.06#ibcon#about to read 3, iclass 28, count 2 2006.201.16:58:42.09#ibcon#read 3, iclass 28, count 2 2006.201.16:58:42.09#ibcon#about to read 4, iclass 28, count 2 2006.201.16:58:42.09#ibcon#read 4, iclass 28, count 2 2006.201.16:58:42.09#ibcon#about to read 5, iclass 28, count 2 2006.201.16:58:42.09#ibcon#read 5, iclass 28, count 2 2006.201.16:58:42.09#ibcon#about to read 6, iclass 28, count 2 2006.201.16:58:42.09#ibcon#read 6, iclass 28, count 2 2006.201.16:58:42.09#ibcon#end of sib2, iclass 28, count 2 2006.201.16:58:42.09#ibcon#*after write, iclass 28, count 2 2006.201.16:58:42.09#ibcon#*before return 0, iclass 28, count 2 2006.201.16:58:42.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:42.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:42.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.16:58:42.09#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:42.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:42.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:42.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:42.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:58:42.21#ibcon#first serial, iclass 28, count 0 2006.201.16:58:42.21#ibcon#enter sib2, iclass 28, count 0 2006.201.16:58:42.21#ibcon#flushed, iclass 28, count 0 2006.201.16:58:42.21#ibcon#about to write, iclass 28, count 0 2006.201.16:58:42.21#ibcon#wrote, iclass 28, count 0 2006.201.16:58:42.21#ibcon#about to read 3, iclass 28, count 0 2006.201.16:58:42.23#ibcon#read 3, iclass 28, count 0 2006.201.16:58:42.23#ibcon#about to read 4, iclass 28, count 0 2006.201.16:58:42.23#ibcon#read 4, iclass 28, count 0 2006.201.16:58:42.23#ibcon#about to read 5, iclass 28, count 0 2006.201.16:58:42.23#ibcon#read 5, iclass 28, count 0 2006.201.16:58:42.23#ibcon#about to read 6, iclass 28, count 0 2006.201.16:58:42.23#ibcon#read 6, iclass 28, count 0 2006.201.16:58:42.23#ibcon#end of sib2, iclass 28, count 0 2006.201.16:58:42.23#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:58:42.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:58:42.23#ibcon#[25=USB\r\n] 2006.201.16:58:42.23#ibcon#*before write, iclass 28, count 0 2006.201.16:58:42.23#ibcon#enter sib2, iclass 28, count 0 2006.201.16:58:42.23#ibcon#flushed, iclass 28, count 0 2006.201.16:58:42.23#ibcon#about to write, iclass 28, count 0 2006.201.16:58:42.23#ibcon#wrote, iclass 28, count 0 2006.201.16:58:42.23#ibcon#about to read 3, iclass 28, count 0 2006.201.16:58:42.26#ibcon#read 3, iclass 28, count 0 2006.201.16:58:42.26#ibcon#about to read 4, iclass 28, count 0 2006.201.16:58:42.26#ibcon#read 4, iclass 28, count 0 2006.201.16:58:42.26#ibcon#about to read 5, iclass 28, count 0 2006.201.16:58:42.26#ibcon#read 5, iclass 28, count 0 2006.201.16:58:42.26#ibcon#about to read 6, iclass 28, count 0 2006.201.16:58:42.26#ibcon#read 6, iclass 28, count 0 2006.201.16:58:42.26#ibcon#end of sib2, iclass 28, count 0 2006.201.16:58:42.26#ibcon#*after write, iclass 28, count 0 2006.201.16:58:42.26#ibcon#*before return 0, iclass 28, count 0 2006.201.16:58:42.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:42.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:42.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:58:42.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:58:42.26$vck44/valo=5,734.99 2006.201.16:58:42.26#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.16:58:42.26#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.16:58:42.26#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:42.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:58:42.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:58:42.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:58:42.26#ibcon#enter wrdev, iclass 30, count 0 2006.201.16:58:42.26#ibcon#first serial, iclass 30, count 0 2006.201.16:58:42.26#ibcon#enter sib2, iclass 30, count 0 2006.201.16:58:42.26#ibcon#flushed, iclass 30, count 0 2006.201.16:58:42.26#ibcon#about to write, iclass 30, count 0 2006.201.16:58:42.26#ibcon#wrote, iclass 30, count 0 2006.201.16:58:42.26#ibcon#about to read 3, iclass 30, count 0 2006.201.16:58:42.28#ibcon#read 3, iclass 30, count 0 2006.201.16:58:42.28#ibcon#about to read 4, iclass 30, count 0 2006.201.16:58:42.28#ibcon#read 4, iclass 30, count 0 2006.201.16:58:42.28#ibcon#about to read 5, iclass 30, count 0 2006.201.16:58:42.28#ibcon#read 5, iclass 30, count 0 2006.201.16:58:42.28#ibcon#about to read 6, iclass 30, count 0 2006.201.16:58:42.28#ibcon#read 6, iclass 30, count 0 2006.201.16:58:42.28#ibcon#end of sib2, iclass 30, count 0 2006.201.16:58:42.28#ibcon#*mode == 0, iclass 30, count 0 2006.201.16:58:42.28#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.16:58:42.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.16:58:42.28#ibcon#*before write, iclass 30, count 0 2006.201.16:58:42.28#ibcon#enter sib2, iclass 30, count 0 2006.201.16:58:42.28#ibcon#flushed, iclass 30, count 0 2006.201.16:58:42.28#ibcon#about to write, iclass 30, count 0 2006.201.16:58:42.28#ibcon#wrote, iclass 30, count 0 2006.201.16:58:42.28#ibcon#about to read 3, iclass 30, count 0 2006.201.16:58:42.32#ibcon#read 3, iclass 30, count 0 2006.201.16:58:42.32#ibcon#about to read 4, iclass 30, count 0 2006.201.16:58:42.32#ibcon#read 4, iclass 30, count 0 2006.201.16:58:42.32#ibcon#about to read 5, iclass 30, count 0 2006.201.16:58:42.32#ibcon#read 5, iclass 30, count 0 2006.201.16:58:42.32#ibcon#about to read 6, iclass 30, count 0 2006.201.16:58:42.32#ibcon#read 6, iclass 30, count 0 2006.201.16:58:42.32#ibcon#end of sib2, iclass 30, count 0 2006.201.16:58:42.32#ibcon#*after write, iclass 30, count 0 2006.201.16:58:42.32#ibcon#*before return 0, iclass 30, count 0 2006.201.16:58:42.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:58:42.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.16:58:42.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.16:58:42.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.16:58:42.32$vck44/va=5,4 2006.201.16:58:42.32#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.16:58:42.32#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.16:58:42.32#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:42.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:58:42.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:58:42.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:58:42.38#ibcon#enter wrdev, iclass 32, count 2 2006.201.16:58:42.38#ibcon#first serial, iclass 32, count 2 2006.201.16:58:42.38#ibcon#enter sib2, iclass 32, count 2 2006.201.16:58:42.38#ibcon#flushed, iclass 32, count 2 2006.201.16:58:42.38#ibcon#about to write, iclass 32, count 2 2006.201.16:58:42.38#ibcon#wrote, iclass 32, count 2 2006.201.16:58:42.38#ibcon#about to read 3, iclass 32, count 2 2006.201.16:58:42.40#ibcon#read 3, iclass 32, count 2 2006.201.16:58:42.40#ibcon#about to read 4, iclass 32, count 2 2006.201.16:58:42.40#ibcon#read 4, iclass 32, count 2 2006.201.16:58:42.40#ibcon#about to read 5, iclass 32, count 2 2006.201.16:58:42.40#ibcon#read 5, iclass 32, count 2 2006.201.16:58:42.40#ibcon#about to read 6, iclass 32, count 2 2006.201.16:58:42.40#ibcon#read 6, iclass 32, count 2 2006.201.16:58:42.40#ibcon#end of sib2, iclass 32, count 2 2006.201.16:58:42.40#ibcon#*mode == 0, iclass 32, count 2 2006.201.16:58:42.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.16:58:42.40#ibcon#[25=AT05-04\r\n] 2006.201.16:58:42.40#ibcon#*before write, iclass 32, count 2 2006.201.16:58:42.40#ibcon#enter sib2, iclass 32, count 2 2006.201.16:58:42.40#ibcon#flushed, iclass 32, count 2 2006.201.16:58:42.40#ibcon#about to write, iclass 32, count 2 2006.201.16:58:42.40#ibcon#wrote, iclass 32, count 2 2006.201.16:58:42.40#ibcon#about to read 3, iclass 32, count 2 2006.201.16:58:42.43#ibcon#read 3, iclass 32, count 2 2006.201.16:58:42.43#ibcon#about to read 4, iclass 32, count 2 2006.201.16:58:42.43#ibcon#read 4, iclass 32, count 2 2006.201.16:58:42.43#ibcon#about to read 5, iclass 32, count 2 2006.201.16:58:42.43#ibcon#read 5, iclass 32, count 2 2006.201.16:58:42.43#ibcon#about to read 6, iclass 32, count 2 2006.201.16:58:42.43#ibcon#read 6, iclass 32, count 2 2006.201.16:58:42.43#ibcon#end of sib2, iclass 32, count 2 2006.201.16:58:42.43#ibcon#*after write, iclass 32, count 2 2006.201.16:58:42.43#ibcon#*before return 0, iclass 32, count 2 2006.201.16:58:42.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:58:42.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.16:58:42.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.16:58:42.43#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:42.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:58:42.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:58:42.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:58:42.55#ibcon#enter wrdev, iclass 32, count 0 2006.201.16:58:42.55#ibcon#first serial, iclass 32, count 0 2006.201.16:58:42.55#ibcon#enter sib2, iclass 32, count 0 2006.201.16:58:42.55#ibcon#flushed, iclass 32, count 0 2006.201.16:58:42.55#ibcon#about to write, iclass 32, count 0 2006.201.16:58:42.55#ibcon#wrote, iclass 32, count 0 2006.201.16:58:42.55#ibcon#about to read 3, iclass 32, count 0 2006.201.16:58:42.57#ibcon#read 3, iclass 32, count 0 2006.201.16:58:42.57#ibcon#about to read 4, iclass 32, count 0 2006.201.16:58:42.57#ibcon#read 4, iclass 32, count 0 2006.201.16:58:42.57#ibcon#about to read 5, iclass 32, count 0 2006.201.16:58:42.57#ibcon#read 5, iclass 32, count 0 2006.201.16:58:42.57#ibcon#about to read 6, iclass 32, count 0 2006.201.16:58:42.57#ibcon#read 6, iclass 32, count 0 2006.201.16:58:42.57#ibcon#end of sib2, iclass 32, count 0 2006.201.16:58:42.57#ibcon#*mode == 0, iclass 32, count 0 2006.201.16:58:42.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.16:58:42.57#ibcon#[25=USB\r\n] 2006.201.16:58:42.57#ibcon#*before write, iclass 32, count 0 2006.201.16:58:42.57#ibcon#enter sib2, iclass 32, count 0 2006.201.16:58:42.57#ibcon#flushed, iclass 32, count 0 2006.201.16:58:42.57#ibcon#about to write, iclass 32, count 0 2006.201.16:58:42.57#ibcon#wrote, iclass 32, count 0 2006.201.16:58:42.57#ibcon#about to read 3, iclass 32, count 0 2006.201.16:58:42.60#ibcon#read 3, iclass 32, count 0 2006.201.16:58:42.60#ibcon#about to read 4, iclass 32, count 0 2006.201.16:58:42.60#ibcon#read 4, iclass 32, count 0 2006.201.16:58:42.60#ibcon#about to read 5, iclass 32, count 0 2006.201.16:58:42.60#ibcon#read 5, iclass 32, count 0 2006.201.16:58:42.60#ibcon#about to read 6, iclass 32, count 0 2006.201.16:58:42.60#ibcon#read 6, iclass 32, count 0 2006.201.16:58:42.60#ibcon#end of sib2, iclass 32, count 0 2006.201.16:58:42.60#ibcon#*after write, iclass 32, count 0 2006.201.16:58:42.60#ibcon#*before return 0, iclass 32, count 0 2006.201.16:58:42.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:58:42.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.16:58:42.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.16:58:42.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.16:58:42.60$vck44/valo=6,814.99 2006.201.16:58:42.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.16:58:42.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.16:58:42.60#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:42.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:58:42.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:58:42.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:58:42.60#ibcon#enter wrdev, iclass 34, count 0 2006.201.16:58:42.60#ibcon#first serial, iclass 34, count 0 2006.201.16:58:42.60#ibcon#enter sib2, iclass 34, count 0 2006.201.16:58:42.60#ibcon#flushed, iclass 34, count 0 2006.201.16:58:42.60#ibcon#about to write, iclass 34, count 0 2006.201.16:58:42.60#ibcon#wrote, iclass 34, count 0 2006.201.16:58:42.60#ibcon#about to read 3, iclass 34, count 0 2006.201.16:58:42.62#ibcon#read 3, iclass 34, count 0 2006.201.16:58:42.62#ibcon#about to read 4, iclass 34, count 0 2006.201.16:58:42.62#ibcon#read 4, iclass 34, count 0 2006.201.16:58:42.62#ibcon#about to read 5, iclass 34, count 0 2006.201.16:58:42.62#ibcon#read 5, iclass 34, count 0 2006.201.16:58:42.62#ibcon#about to read 6, iclass 34, count 0 2006.201.16:58:42.62#ibcon#read 6, iclass 34, count 0 2006.201.16:58:42.62#ibcon#end of sib2, iclass 34, count 0 2006.201.16:58:42.62#ibcon#*mode == 0, iclass 34, count 0 2006.201.16:58:42.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.16:58:42.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.16:58:42.62#ibcon#*before write, iclass 34, count 0 2006.201.16:58:42.62#ibcon#enter sib2, iclass 34, count 0 2006.201.16:58:42.62#ibcon#flushed, iclass 34, count 0 2006.201.16:58:42.62#ibcon#about to write, iclass 34, count 0 2006.201.16:58:42.62#ibcon#wrote, iclass 34, count 0 2006.201.16:58:42.62#ibcon#about to read 3, iclass 34, count 0 2006.201.16:58:42.67#ibcon#read 3, iclass 34, count 0 2006.201.16:58:42.67#ibcon#about to read 4, iclass 34, count 0 2006.201.16:58:42.67#ibcon#read 4, iclass 34, count 0 2006.201.16:58:42.67#ibcon#about to read 5, iclass 34, count 0 2006.201.16:58:42.67#ibcon#read 5, iclass 34, count 0 2006.201.16:58:42.67#ibcon#about to read 6, iclass 34, count 0 2006.201.16:58:42.67#ibcon#read 6, iclass 34, count 0 2006.201.16:58:42.67#ibcon#end of sib2, iclass 34, count 0 2006.201.16:58:42.67#ibcon#*after write, iclass 34, count 0 2006.201.16:58:42.67#ibcon#*before return 0, iclass 34, count 0 2006.201.16:58:42.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:58:42.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.16:58:42.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.16:58:42.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.16:58:42.67$vck44/va=6,5 2006.201.16:58:42.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.16:58:42.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.16:58:42.67#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:42.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:58:42.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:58:42.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:58:42.72#ibcon#enter wrdev, iclass 36, count 2 2006.201.16:58:42.72#ibcon#first serial, iclass 36, count 2 2006.201.16:58:42.72#ibcon#enter sib2, iclass 36, count 2 2006.201.16:58:42.72#ibcon#flushed, iclass 36, count 2 2006.201.16:58:42.72#ibcon#about to write, iclass 36, count 2 2006.201.16:58:42.72#ibcon#wrote, iclass 36, count 2 2006.201.16:58:42.72#ibcon#about to read 3, iclass 36, count 2 2006.201.16:58:42.74#ibcon#read 3, iclass 36, count 2 2006.201.16:58:42.74#ibcon#about to read 4, iclass 36, count 2 2006.201.16:58:42.74#ibcon#read 4, iclass 36, count 2 2006.201.16:58:42.74#ibcon#about to read 5, iclass 36, count 2 2006.201.16:58:42.74#ibcon#read 5, iclass 36, count 2 2006.201.16:58:42.74#ibcon#about to read 6, iclass 36, count 2 2006.201.16:58:42.74#ibcon#read 6, iclass 36, count 2 2006.201.16:58:42.74#ibcon#end of sib2, iclass 36, count 2 2006.201.16:58:42.74#ibcon#*mode == 0, iclass 36, count 2 2006.201.16:58:42.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.16:58:42.74#ibcon#[25=AT06-05\r\n] 2006.201.16:58:42.74#ibcon#*before write, iclass 36, count 2 2006.201.16:58:42.74#ibcon#enter sib2, iclass 36, count 2 2006.201.16:58:42.74#ibcon#flushed, iclass 36, count 2 2006.201.16:58:42.74#ibcon#about to write, iclass 36, count 2 2006.201.16:58:42.74#ibcon#wrote, iclass 36, count 2 2006.201.16:58:42.74#ibcon#about to read 3, iclass 36, count 2 2006.201.16:58:42.77#ibcon#read 3, iclass 36, count 2 2006.201.16:58:42.77#ibcon#about to read 4, iclass 36, count 2 2006.201.16:58:42.77#ibcon#read 4, iclass 36, count 2 2006.201.16:58:42.77#ibcon#about to read 5, iclass 36, count 2 2006.201.16:58:42.77#ibcon#read 5, iclass 36, count 2 2006.201.16:58:42.77#ibcon#about to read 6, iclass 36, count 2 2006.201.16:58:42.77#ibcon#read 6, iclass 36, count 2 2006.201.16:58:42.77#ibcon#end of sib2, iclass 36, count 2 2006.201.16:58:42.77#ibcon#*after write, iclass 36, count 2 2006.201.16:58:42.77#ibcon#*before return 0, iclass 36, count 2 2006.201.16:58:42.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:58:42.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.16:58:42.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.16:58:42.77#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:42.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:58:42.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:58:42.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:58:42.89#ibcon#enter wrdev, iclass 36, count 0 2006.201.16:58:42.89#ibcon#first serial, iclass 36, count 0 2006.201.16:58:42.89#ibcon#enter sib2, iclass 36, count 0 2006.201.16:58:42.89#ibcon#flushed, iclass 36, count 0 2006.201.16:58:42.89#ibcon#about to write, iclass 36, count 0 2006.201.16:58:42.89#ibcon#wrote, iclass 36, count 0 2006.201.16:58:42.89#ibcon#about to read 3, iclass 36, count 0 2006.201.16:58:42.91#ibcon#read 3, iclass 36, count 0 2006.201.16:58:42.91#ibcon#about to read 4, iclass 36, count 0 2006.201.16:58:42.91#ibcon#read 4, iclass 36, count 0 2006.201.16:58:42.91#ibcon#about to read 5, iclass 36, count 0 2006.201.16:58:42.91#ibcon#read 5, iclass 36, count 0 2006.201.16:58:42.91#ibcon#about to read 6, iclass 36, count 0 2006.201.16:58:42.91#ibcon#read 6, iclass 36, count 0 2006.201.16:58:42.91#ibcon#end of sib2, iclass 36, count 0 2006.201.16:58:42.91#ibcon#*mode == 0, iclass 36, count 0 2006.201.16:58:42.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.16:58:42.91#ibcon#[25=USB\r\n] 2006.201.16:58:42.91#ibcon#*before write, iclass 36, count 0 2006.201.16:58:42.91#ibcon#enter sib2, iclass 36, count 0 2006.201.16:58:42.91#ibcon#flushed, iclass 36, count 0 2006.201.16:58:42.91#ibcon#about to write, iclass 36, count 0 2006.201.16:58:42.91#ibcon#wrote, iclass 36, count 0 2006.201.16:58:42.91#ibcon#about to read 3, iclass 36, count 0 2006.201.16:58:42.94#ibcon#read 3, iclass 36, count 0 2006.201.16:58:42.94#ibcon#about to read 4, iclass 36, count 0 2006.201.16:58:42.94#ibcon#read 4, iclass 36, count 0 2006.201.16:58:42.94#ibcon#about to read 5, iclass 36, count 0 2006.201.16:58:42.94#ibcon#read 5, iclass 36, count 0 2006.201.16:58:42.94#ibcon#about to read 6, iclass 36, count 0 2006.201.16:58:42.94#ibcon#read 6, iclass 36, count 0 2006.201.16:58:42.94#ibcon#end of sib2, iclass 36, count 0 2006.201.16:58:42.94#ibcon#*after write, iclass 36, count 0 2006.201.16:58:42.94#ibcon#*before return 0, iclass 36, count 0 2006.201.16:58:42.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:58:42.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.16:58:42.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.16:58:42.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.16:58:42.94$vck44/valo=7,864.99 2006.201.16:58:42.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.16:58:42.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.16:58:42.94#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:42.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:42.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:42.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:42.94#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:58:42.94#ibcon#first serial, iclass 38, count 0 2006.201.16:58:42.94#ibcon#enter sib2, iclass 38, count 0 2006.201.16:58:42.94#ibcon#flushed, iclass 38, count 0 2006.201.16:58:42.94#ibcon#about to write, iclass 38, count 0 2006.201.16:58:42.94#ibcon#wrote, iclass 38, count 0 2006.201.16:58:42.94#ibcon#about to read 3, iclass 38, count 0 2006.201.16:58:42.96#ibcon#read 3, iclass 38, count 0 2006.201.16:58:42.96#ibcon#about to read 4, iclass 38, count 0 2006.201.16:58:42.96#ibcon#read 4, iclass 38, count 0 2006.201.16:58:42.96#ibcon#about to read 5, iclass 38, count 0 2006.201.16:58:42.96#ibcon#read 5, iclass 38, count 0 2006.201.16:58:42.96#ibcon#about to read 6, iclass 38, count 0 2006.201.16:58:42.96#ibcon#read 6, iclass 38, count 0 2006.201.16:58:42.96#ibcon#end of sib2, iclass 38, count 0 2006.201.16:58:42.96#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:58:42.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:58:42.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.16:58:42.96#ibcon#*before write, iclass 38, count 0 2006.201.16:58:42.96#ibcon#enter sib2, iclass 38, count 0 2006.201.16:58:42.96#ibcon#flushed, iclass 38, count 0 2006.201.16:58:42.96#ibcon#about to write, iclass 38, count 0 2006.201.16:58:42.96#ibcon#wrote, iclass 38, count 0 2006.201.16:58:42.96#ibcon#about to read 3, iclass 38, count 0 2006.201.16:58:43.00#ibcon#read 3, iclass 38, count 0 2006.201.16:58:43.00#ibcon#about to read 4, iclass 38, count 0 2006.201.16:58:43.00#ibcon#read 4, iclass 38, count 0 2006.201.16:58:43.00#ibcon#about to read 5, iclass 38, count 0 2006.201.16:58:43.00#ibcon#read 5, iclass 38, count 0 2006.201.16:58:43.00#ibcon#about to read 6, iclass 38, count 0 2006.201.16:58:43.00#ibcon#read 6, iclass 38, count 0 2006.201.16:58:43.00#ibcon#end of sib2, iclass 38, count 0 2006.201.16:58:43.00#ibcon#*after write, iclass 38, count 0 2006.201.16:58:43.00#ibcon#*before return 0, iclass 38, count 0 2006.201.16:58:43.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:43.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:43.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:58:43.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:58:43.00$vck44/va=7,5 2006.201.16:58:43.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.16:58:43.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.16:58:43.00#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:43.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:43.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:43.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:43.06#ibcon#enter wrdev, iclass 40, count 2 2006.201.16:58:43.06#ibcon#first serial, iclass 40, count 2 2006.201.16:58:43.06#ibcon#enter sib2, iclass 40, count 2 2006.201.16:58:43.06#ibcon#flushed, iclass 40, count 2 2006.201.16:58:43.06#ibcon#about to write, iclass 40, count 2 2006.201.16:58:43.06#ibcon#wrote, iclass 40, count 2 2006.201.16:58:43.06#ibcon#about to read 3, iclass 40, count 2 2006.201.16:58:43.08#ibcon#read 3, iclass 40, count 2 2006.201.16:58:43.08#ibcon#about to read 4, iclass 40, count 2 2006.201.16:58:43.08#ibcon#read 4, iclass 40, count 2 2006.201.16:58:43.08#ibcon#about to read 5, iclass 40, count 2 2006.201.16:58:43.08#ibcon#read 5, iclass 40, count 2 2006.201.16:58:43.08#ibcon#about to read 6, iclass 40, count 2 2006.201.16:58:43.08#ibcon#read 6, iclass 40, count 2 2006.201.16:58:43.08#ibcon#end of sib2, iclass 40, count 2 2006.201.16:58:43.08#ibcon#*mode == 0, iclass 40, count 2 2006.201.16:58:43.08#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.16:58:43.08#ibcon#[25=AT07-05\r\n] 2006.201.16:58:43.08#ibcon#*before write, iclass 40, count 2 2006.201.16:58:43.08#ibcon#enter sib2, iclass 40, count 2 2006.201.16:58:43.08#ibcon#flushed, iclass 40, count 2 2006.201.16:58:43.08#ibcon#about to write, iclass 40, count 2 2006.201.16:58:43.08#ibcon#wrote, iclass 40, count 2 2006.201.16:58:43.08#ibcon#about to read 3, iclass 40, count 2 2006.201.16:58:43.11#ibcon#read 3, iclass 40, count 2 2006.201.16:58:43.11#ibcon#about to read 4, iclass 40, count 2 2006.201.16:58:43.11#ibcon#read 4, iclass 40, count 2 2006.201.16:58:43.11#ibcon#about to read 5, iclass 40, count 2 2006.201.16:58:43.11#ibcon#read 5, iclass 40, count 2 2006.201.16:58:43.11#ibcon#about to read 6, iclass 40, count 2 2006.201.16:58:43.11#ibcon#read 6, iclass 40, count 2 2006.201.16:58:43.11#ibcon#end of sib2, iclass 40, count 2 2006.201.16:58:43.11#ibcon#*after write, iclass 40, count 2 2006.201.16:58:43.11#ibcon#*before return 0, iclass 40, count 2 2006.201.16:58:43.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:43.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:43.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.16:58:43.11#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:43.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:43.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:43.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:43.23#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:58:43.23#ibcon#first serial, iclass 40, count 0 2006.201.16:58:43.23#ibcon#enter sib2, iclass 40, count 0 2006.201.16:58:43.23#ibcon#flushed, iclass 40, count 0 2006.201.16:58:43.23#ibcon#about to write, iclass 40, count 0 2006.201.16:58:43.23#ibcon#wrote, iclass 40, count 0 2006.201.16:58:43.23#ibcon#about to read 3, iclass 40, count 0 2006.201.16:58:43.25#ibcon#read 3, iclass 40, count 0 2006.201.16:58:43.25#ibcon#about to read 4, iclass 40, count 0 2006.201.16:58:43.25#ibcon#read 4, iclass 40, count 0 2006.201.16:58:43.25#ibcon#about to read 5, iclass 40, count 0 2006.201.16:58:43.25#ibcon#read 5, iclass 40, count 0 2006.201.16:58:43.25#ibcon#about to read 6, iclass 40, count 0 2006.201.16:58:43.25#ibcon#read 6, iclass 40, count 0 2006.201.16:58:43.25#ibcon#end of sib2, iclass 40, count 0 2006.201.16:58:43.25#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:58:43.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:58:43.25#ibcon#[25=USB\r\n] 2006.201.16:58:43.25#ibcon#*before write, iclass 40, count 0 2006.201.16:58:43.25#ibcon#enter sib2, iclass 40, count 0 2006.201.16:58:43.25#ibcon#flushed, iclass 40, count 0 2006.201.16:58:43.25#ibcon#about to write, iclass 40, count 0 2006.201.16:58:43.25#ibcon#wrote, iclass 40, count 0 2006.201.16:58:43.25#ibcon#about to read 3, iclass 40, count 0 2006.201.16:58:43.28#ibcon#read 3, iclass 40, count 0 2006.201.16:58:43.28#ibcon#about to read 4, iclass 40, count 0 2006.201.16:58:43.28#ibcon#read 4, iclass 40, count 0 2006.201.16:58:43.28#ibcon#about to read 5, iclass 40, count 0 2006.201.16:58:43.28#ibcon#read 5, iclass 40, count 0 2006.201.16:58:43.28#ibcon#about to read 6, iclass 40, count 0 2006.201.16:58:43.28#ibcon#read 6, iclass 40, count 0 2006.201.16:58:43.28#ibcon#end of sib2, iclass 40, count 0 2006.201.16:58:43.28#ibcon#*after write, iclass 40, count 0 2006.201.16:58:43.28#ibcon#*before return 0, iclass 40, count 0 2006.201.16:58:43.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:43.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:43.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:58:43.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:58:43.28$vck44/valo=8,884.99 2006.201.16:58:43.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.16:58:43.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.16:58:43.28#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:43.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:43.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:43.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:43.28#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:58:43.28#ibcon#first serial, iclass 4, count 0 2006.201.16:58:43.28#ibcon#enter sib2, iclass 4, count 0 2006.201.16:58:43.28#ibcon#flushed, iclass 4, count 0 2006.201.16:58:43.28#ibcon#about to write, iclass 4, count 0 2006.201.16:58:43.28#ibcon#wrote, iclass 4, count 0 2006.201.16:58:43.28#ibcon#about to read 3, iclass 4, count 0 2006.201.16:58:43.30#ibcon#read 3, iclass 4, count 0 2006.201.16:58:43.30#ibcon#about to read 4, iclass 4, count 0 2006.201.16:58:43.30#ibcon#read 4, iclass 4, count 0 2006.201.16:58:43.30#ibcon#about to read 5, iclass 4, count 0 2006.201.16:58:43.30#ibcon#read 5, iclass 4, count 0 2006.201.16:58:43.30#ibcon#about to read 6, iclass 4, count 0 2006.201.16:58:43.30#ibcon#read 6, iclass 4, count 0 2006.201.16:58:43.30#ibcon#end of sib2, iclass 4, count 0 2006.201.16:58:43.30#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:58:43.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:58:43.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.16:58:43.30#ibcon#*before write, iclass 4, count 0 2006.201.16:58:43.30#ibcon#enter sib2, iclass 4, count 0 2006.201.16:58:43.30#ibcon#flushed, iclass 4, count 0 2006.201.16:58:43.30#ibcon#about to write, iclass 4, count 0 2006.201.16:58:43.30#ibcon#wrote, iclass 4, count 0 2006.201.16:58:43.30#ibcon#about to read 3, iclass 4, count 0 2006.201.16:58:43.34#ibcon#read 3, iclass 4, count 0 2006.201.16:58:43.34#ibcon#about to read 4, iclass 4, count 0 2006.201.16:58:43.34#ibcon#read 4, iclass 4, count 0 2006.201.16:58:43.34#ibcon#about to read 5, iclass 4, count 0 2006.201.16:58:43.34#ibcon#read 5, iclass 4, count 0 2006.201.16:58:43.34#ibcon#about to read 6, iclass 4, count 0 2006.201.16:58:43.34#ibcon#read 6, iclass 4, count 0 2006.201.16:58:43.34#ibcon#end of sib2, iclass 4, count 0 2006.201.16:58:43.34#ibcon#*after write, iclass 4, count 0 2006.201.16:58:43.34#ibcon#*before return 0, iclass 4, count 0 2006.201.16:58:43.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:43.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:43.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:58:43.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:58:43.34$vck44/va=8,4 2006.201.16:58:43.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.16:58:43.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.16:58:43.34#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:43.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:43.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:43.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:43.40#ibcon#enter wrdev, iclass 6, count 2 2006.201.16:58:43.40#ibcon#first serial, iclass 6, count 2 2006.201.16:58:43.40#ibcon#enter sib2, iclass 6, count 2 2006.201.16:58:43.40#ibcon#flushed, iclass 6, count 2 2006.201.16:58:43.40#ibcon#about to write, iclass 6, count 2 2006.201.16:58:43.40#ibcon#wrote, iclass 6, count 2 2006.201.16:58:43.40#ibcon#about to read 3, iclass 6, count 2 2006.201.16:58:43.42#ibcon#read 3, iclass 6, count 2 2006.201.16:58:43.42#ibcon#about to read 4, iclass 6, count 2 2006.201.16:58:43.42#ibcon#read 4, iclass 6, count 2 2006.201.16:58:43.42#ibcon#about to read 5, iclass 6, count 2 2006.201.16:58:43.42#ibcon#read 5, iclass 6, count 2 2006.201.16:58:43.42#ibcon#about to read 6, iclass 6, count 2 2006.201.16:58:43.42#ibcon#read 6, iclass 6, count 2 2006.201.16:58:43.42#ibcon#end of sib2, iclass 6, count 2 2006.201.16:58:43.42#ibcon#*mode == 0, iclass 6, count 2 2006.201.16:58:43.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.16:58:43.42#ibcon#[25=AT08-04\r\n] 2006.201.16:58:43.42#ibcon#*before write, iclass 6, count 2 2006.201.16:58:43.42#ibcon#enter sib2, iclass 6, count 2 2006.201.16:58:43.42#ibcon#flushed, iclass 6, count 2 2006.201.16:58:43.42#ibcon#about to write, iclass 6, count 2 2006.201.16:58:43.42#ibcon#wrote, iclass 6, count 2 2006.201.16:58:43.42#ibcon#about to read 3, iclass 6, count 2 2006.201.16:58:43.45#ibcon#read 3, iclass 6, count 2 2006.201.16:58:43.45#ibcon#about to read 4, iclass 6, count 2 2006.201.16:58:43.45#ibcon#read 4, iclass 6, count 2 2006.201.16:58:43.45#ibcon#about to read 5, iclass 6, count 2 2006.201.16:58:43.45#ibcon#read 5, iclass 6, count 2 2006.201.16:58:43.45#ibcon#about to read 6, iclass 6, count 2 2006.201.16:58:43.45#ibcon#read 6, iclass 6, count 2 2006.201.16:58:43.45#ibcon#end of sib2, iclass 6, count 2 2006.201.16:58:43.45#ibcon#*after write, iclass 6, count 2 2006.201.16:58:43.45#ibcon#*before return 0, iclass 6, count 2 2006.201.16:58:43.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:43.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:43.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.16:58:43.45#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:43.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:43.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:43.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:43.57#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:58:43.57#ibcon#first serial, iclass 6, count 0 2006.201.16:58:43.57#ibcon#enter sib2, iclass 6, count 0 2006.201.16:58:43.57#ibcon#flushed, iclass 6, count 0 2006.201.16:58:43.57#ibcon#about to write, iclass 6, count 0 2006.201.16:58:43.57#ibcon#wrote, iclass 6, count 0 2006.201.16:58:43.57#ibcon#about to read 3, iclass 6, count 0 2006.201.16:58:43.59#ibcon#read 3, iclass 6, count 0 2006.201.16:58:43.59#ibcon#about to read 4, iclass 6, count 0 2006.201.16:58:43.59#ibcon#read 4, iclass 6, count 0 2006.201.16:58:43.59#ibcon#about to read 5, iclass 6, count 0 2006.201.16:58:43.59#ibcon#read 5, iclass 6, count 0 2006.201.16:58:43.59#ibcon#about to read 6, iclass 6, count 0 2006.201.16:58:43.59#ibcon#read 6, iclass 6, count 0 2006.201.16:58:43.59#ibcon#end of sib2, iclass 6, count 0 2006.201.16:58:43.59#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:58:43.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:58:43.59#ibcon#[25=USB\r\n] 2006.201.16:58:43.59#ibcon#*before write, iclass 6, count 0 2006.201.16:58:43.59#ibcon#enter sib2, iclass 6, count 0 2006.201.16:58:43.59#ibcon#flushed, iclass 6, count 0 2006.201.16:58:43.59#ibcon#about to write, iclass 6, count 0 2006.201.16:58:43.59#ibcon#wrote, iclass 6, count 0 2006.201.16:58:43.59#ibcon#about to read 3, iclass 6, count 0 2006.201.16:58:43.62#ibcon#read 3, iclass 6, count 0 2006.201.16:58:43.62#ibcon#about to read 4, iclass 6, count 0 2006.201.16:58:43.62#ibcon#read 4, iclass 6, count 0 2006.201.16:58:43.62#ibcon#about to read 5, iclass 6, count 0 2006.201.16:58:43.62#ibcon#read 5, iclass 6, count 0 2006.201.16:58:43.62#ibcon#about to read 6, iclass 6, count 0 2006.201.16:58:43.62#ibcon#read 6, iclass 6, count 0 2006.201.16:58:43.62#ibcon#end of sib2, iclass 6, count 0 2006.201.16:58:43.62#ibcon#*after write, iclass 6, count 0 2006.201.16:58:43.62#ibcon#*before return 0, iclass 6, count 0 2006.201.16:58:43.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:43.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:43.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:58:43.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:58:43.62$vck44/vblo=1,629.99 2006.201.16:58:43.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.16:58:43.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.16:58:43.62#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:43.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:43.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:43.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:43.62#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:58:43.62#ibcon#first serial, iclass 10, count 0 2006.201.16:58:43.62#ibcon#enter sib2, iclass 10, count 0 2006.201.16:58:43.62#ibcon#flushed, iclass 10, count 0 2006.201.16:58:43.62#ibcon#about to write, iclass 10, count 0 2006.201.16:58:43.62#ibcon#wrote, iclass 10, count 0 2006.201.16:58:43.62#ibcon#about to read 3, iclass 10, count 0 2006.201.16:58:43.64#ibcon#read 3, iclass 10, count 0 2006.201.16:58:43.64#ibcon#about to read 4, iclass 10, count 0 2006.201.16:58:43.64#ibcon#read 4, iclass 10, count 0 2006.201.16:58:43.64#ibcon#about to read 5, iclass 10, count 0 2006.201.16:58:43.64#ibcon#read 5, iclass 10, count 0 2006.201.16:58:43.64#ibcon#about to read 6, iclass 10, count 0 2006.201.16:58:43.64#ibcon#read 6, iclass 10, count 0 2006.201.16:58:43.64#ibcon#end of sib2, iclass 10, count 0 2006.201.16:58:43.64#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:58:43.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:58:43.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.16:58:43.64#ibcon#*before write, iclass 10, count 0 2006.201.16:58:43.64#ibcon#enter sib2, iclass 10, count 0 2006.201.16:58:43.64#ibcon#flushed, iclass 10, count 0 2006.201.16:58:43.64#ibcon#about to write, iclass 10, count 0 2006.201.16:58:43.64#ibcon#wrote, iclass 10, count 0 2006.201.16:58:43.64#ibcon#about to read 3, iclass 10, count 0 2006.201.16:58:43.68#ibcon#read 3, iclass 10, count 0 2006.201.16:58:43.68#ibcon#about to read 4, iclass 10, count 0 2006.201.16:58:43.68#ibcon#read 4, iclass 10, count 0 2006.201.16:58:43.68#ibcon#about to read 5, iclass 10, count 0 2006.201.16:58:43.68#ibcon#read 5, iclass 10, count 0 2006.201.16:58:43.68#ibcon#about to read 6, iclass 10, count 0 2006.201.16:58:43.68#ibcon#read 6, iclass 10, count 0 2006.201.16:58:43.68#ibcon#end of sib2, iclass 10, count 0 2006.201.16:58:43.68#ibcon#*after write, iclass 10, count 0 2006.201.16:58:43.68#ibcon#*before return 0, iclass 10, count 0 2006.201.16:58:43.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:43.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:43.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:58:43.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:58:43.68$vck44/vb=1,4 2006.201.16:58:43.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.16:58:43.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.16:58:43.68#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:43.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:58:43.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:58:43.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:58:43.68#ibcon#enter wrdev, iclass 12, count 2 2006.201.16:58:43.68#ibcon#first serial, iclass 12, count 2 2006.201.16:58:43.68#ibcon#enter sib2, iclass 12, count 2 2006.201.16:58:43.68#ibcon#flushed, iclass 12, count 2 2006.201.16:58:43.68#ibcon#about to write, iclass 12, count 2 2006.201.16:58:43.68#ibcon#wrote, iclass 12, count 2 2006.201.16:58:43.68#ibcon#about to read 3, iclass 12, count 2 2006.201.16:58:43.70#ibcon#read 3, iclass 12, count 2 2006.201.16:58:43.70#ibcon#about to read 4, iclass 12, count 2 2006.201.16:58:43.70#ibcon#read 4, iclass 12, count 2 2006.201.16:58:43.70#ibcon#about to read 5, iclass 12, count 2 2006.201.16:58:43.70#ibcon#read 5, iclass 12, count 2 2006.201.16:58:43.70#ibcon#about to read 6, iclass 12, count 2 2006.201.16:58:43.70#ibcon#read 6, iclass 12, count 2 2006.201.16:58:43.70#ibcon#end of sib2, iclass 12, count 2 2006.201.16:58:43.70#ibcon#*mode == 0, iclass 12, count 2 2006.201.16:58:43.70#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.16:58:43.70#ibcon#[27=AT01-04\r\n] 2006.201.16:58:43.70#ibcon#*before write, iclass 12, count 2 2006.201.16:58:43.70#ibcon#enter sib2, iclass 12, count 2 2006.201.16:58:43.70#ibcon#flushed, iclass 12, count 2 2006.201.16:58:43.70#ibcon#about to write, iclass 12, count 2 2006.201.16:58:43.70#ibcon#wrote, iclass 12, count 2 2006.201.16:58:43.70#ibcon#about to read 3, iclass 12, count 2 2006.201.16:58:43.73#ibcon#read 3, iclass 12, count 2 2006.201.16:58:43.73#ibcon#about to read 4, iclass 12, count 2 2006.201.16:58:43.73#ibcon#read 4, iclass 12, count 2 2006.201.16:58:43.73#ibcon#about to read 5, iclass 12, count 2 2006.201.16:58:43.73#ibcon#read 5, iclass 12, count 2 2006.201.16:58:43.73#ibcon#about to read 6, iclass 12, count 2 2006.201.16:58:43.73#ibcon#read 6, iclass 12, count 2 2006.201.16:58:43.73#ibcon#end of sib2, iclass 12, count 2 2006.201.16:58:43.73#ibcon#*after write, iclass 12, count 2 2006.201.16:58:43.73#ibcon#*before return 0, iclass 12, count 2 2006.201.16:58:43.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:58:43.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.16:58:43.73#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.16:58:43.73#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:43.73#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:58:43.85#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:58:43.85#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:58:43.85#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:58:43.85#ibcon#first serial, iclass 12, count 0 2006.201.16:58:43.85#ibcon#enter sib2, iclass 12, count 0 2006.201.16:58:43.85#ibcon#flushed, iclass 12, count 0 2006.201.16:58:43.85#ibcon#about to write, iclass 12, count 0 2006.201.16:58:43.85#ibcon#wrote, iclass 12, count 0 2006.201.16:58:43.85#ibcon#about to read 3, iclass 12, count 0 2006.201.16:58:43.87#ibcon#read 3, iclass 12, count 0 2006.201.16:58:43.87#ibcon#about to read 4, iclass 12, count 0 2006.201.16:58:43.87#ibcon#read 4, iclass 12, count 0 2006.201.16:58:43.87#ibcon#about to read 5, iclass 12, count 0 2006.201.16:58:43.87#ibcon#read 5, iclass 12, count 0 2006.201.16:58:43.87#ibcon#about to read 6, iclass 12, count 0 2006.201.16:58:43.87#ibcon#read 6, iclass 12, count 0 2006.201.16:58:43.87#ibcon#end of sib2, iclass 12, count 0 2006.201.16:58:43.87#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:58:43.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:58:43.87#ibcon#[27=USB\r\n] 2006.201.16:58:43.87#ibcon#*before write, iclass 12, count 0 2006.201.16:58:43.87#ibcon#enter sib2, iclass 12, count 0 2006.201.16:58:43.87#ibcon#flushed, iclass 12, count 0 2006.201.16:58:43.87#ibcon#about to write, iclass 12, count 0 2006.201.16:58:43.87#ibcon#wrote, iclass 12, count 0 2006.201.16:58:43.87#ibcon#about to read 3, iclass 12, count 0 2006.201.16:58:43.90#ibcon#read 3, iclass 12, count 0 2006.201.16:58:43.90#ibcon#about to read 4, iclass 12, count 0 2006.201.16:58:43.90#ibcon#read 4, iclass 12, count 0 2006.201.16:58:43.90#ibcon#about to read 5, iclass 12, count 0 2006.201.16:58:43.90#ibcon#read 5, iclass 12, count 0 2006.201.16:58:43.90#ibcon#about to read 6, iclass 12, count 0 2006.201.16:58:43.90#ibcon#read 6, iclass 12, count 0 2006.201.16:58:43.90#ibcon#end of sib2, iclass 12, count 0 2006.201.16:58:43.90#ibcon#*after write, iclass 12, count 0 2006.201.16:58:43.90#ibcon#*before return 0, iclass 12, count 0 2006.201.16:58:43.90#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:58:43.90#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.16:58:43.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:58:43.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:58:43.90$vck44/vblo=2,634.99 2006.201.16:58:43.90#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.16:58:43.90#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.16:58:43.90#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:43.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:43.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:43.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:43.90#ibcon#enter wrdev, iclass 14, count 0 2006.201.16:58:43.90#ibcon#first serial, iclass 14, count 0 2006.201.16:58:43.90#ibcon#enter sib2, iclass 14, count 0 2006.201.16:58:43.90#ibcon#flushed, iclass 14, count 0 2006.201.16:58:43.90#ibcon#about to write, iclass 14, count 0 2006.201.16:58:43.90#ibcon#wrote, iclass 14, count 0 2006.201.16:58:43.90#ibcon#about to read 3, iclass 14, count 0 2006.201.16:58:43.92#ibcon#read 3, iclass 14, count 0 2006.201.16:58:43.92#ibcon#about to read 4, iclass 14, count 0 2006.201.16:58:43.92#ibcon#read 4, iclass 14, count 0 2006.201.16:58:43.92#ibcon#about to read 5, iclass 14, count 0 2006.201.16:58:43.92#ibcon#read 5, iclass 14, count 0 2006.201.16:58:43.92#ibcon#about to read 6, iclass 14, count 0 2006.201.16:58:43.92#ibcon#read 6, iclass 14, count 0 2006.201.16:58:43.92#ibcon#end of sib2, iclass 14, count 0 2006.201.16:58:43.92#ibcon#*mode == 0, iclass 14, count 0 2006.201.16:58:43.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.16:58:43.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.16:58:43.92#ibcon#*before write, iclass 14, count 0 2006.201.16:58:43.92#ibcon#enter sib2, iclass 14, count 0 2006.201.16:58:43.92#ibcon#flushed, iclass 14, count 0 2006.201.16:58:43.92#ibcon#about to write, iclass 14, count 0 2006.201.16:58:43.92#ibcon#wrote, iclass 14, count 0 2006.201.16:58:43.92#ibcon#about to read 3, iclass 14, count 0 2006.201.16:58:43.96#ibcon#read 3, iclass 14, count 0 2006.201.16:58:43.96#ibcon#about to read 4, iclass 14, count 0 2006.201.16:58:43.96#ibcon#read 4, iclass 14, count 0 2006.201.16:58:43.96#ibcon#about to read 5, iclass 14, count 0 2006.201.16:58:43.96#ibcon#read 5, iclass 14, count 0 2006.201.16:58:43.96#ibcon#about to read 6, iclass 14, count 0 2006.201.16:58:43.96#ibcon#read 6, iclass 14, count 0 2006.201.16:58:43.96#ibcon#end of sib2, iclass 14, count 0 2006.201.16:58:43.96#ibcon#*after write, iclass 14, count 0 2006.201.16:58:43.96#ibcon#*before return 0, iclass 14, count 0 2006.201.16:58:43.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:43.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.16:58:43.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.16:58:43.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.16:58:43.96$vck44/vb=2,5 2006.201.16:58:43.96#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.16:58:43.96#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.16:58:43.96#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:43.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:44.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:44.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:44.02#ibcon#enter wrdev, iclass 16, count 2 2006.201.16:58:44.02#ibcon#first serial, iclass 16, count 2 2006.201.16:58:44.02#ibcon#enter sib2, iclass 16, count 2 2006.201.16:58:44.02#ibcon#flushed, iclass 16, count 2 2006.201.16:58:44.02#ibcon#about to write, iclass 16, count 2 2006.201.16:58:44.02#ibcon#wrote, iclass 16, count 2 2006.201.16:58:44.02#ibcon#about to read 3, iclass 16, count 2 2006.201.16:58:44.04#ibcon#read 3, iclass 16, count 2 2006.201.16:58:44.04#ibcon#about to read 4, iclass 16, count 2 2006.201.16:58:44.04#ibcon#read 4, iclass 16, count 2 2006.201.16:58:44.04#ibcon#about to read 5, iclass 16, count 2 2006.201.16:58:44.04#ibcon#read 5, iclass 16, count 2 2006.201.16:58:44.04#ibcon#about to read 6, iclass 16, count 2 2006.201.16:58:44.04#ibcon#read 6, iclass 16, count 2 2006.201.16:58:44.04#ibcon#end of sib2, iclass 16, count 2 2006.201.16:58:44.04#ibcon#*mode == 0, iclass 16, count 2 2006.201.16:58:44.04#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.16:58:44.04#ibcon#[27=AT02-05\r\n] 2006.201.16:58:44.04#ibcon#*before write, iclass 16, count 2 2006.201.16:58:44.04#ibcon#enter sib2, iclass 16, count 2 2006.201.16:58:44.04#ibcon#flushed, iclass 16, count 2 2006.201.16:58:44.04#ibcon#about to write, iclass 16, count 2 2006.201.16:58:44.04#ibcon#wrote, iclass 16, count 2 2006.201.16:58:44.04#ibcon#about to read 3, iclass 16, count 2 2006.201.16:58:44.07#ibcon#read 3, iclass 16, count 2 2006.201.16:58:44.07#ibcon#about to read 4, iclass 16, count 2 2006.201.16:58:44.07#ibcon#read 4, iclass 16, count 2 2006.201.16:58:44.07#ibcon#about to read 5, iclass 16, count 2 2006.201.16:58:44.07#ibcon#read 5, iclass 16, count 2 2006.201.16:58:44.07#ibcon#about to read 6, iclass 16, count 2 2006.201.16:58:44.07#ibcon#read 6, iclass 16, count 2 2006.201.16:58:44.07#ibcon#end of sib2, iclass 16, count 2 2006.201.16:58:44.07#ibcon#*after write, iclass 16, count 2 2006.201.16:58:44.07#ibcon#*before return 0, iclass 16, count 2 2006.201.16:58:44.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:44.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.16:58:44.07#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.16:58:44.07#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:44.07#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:44.19#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:44.19#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:44.19#ibcon#enter wrdev, iclass 16, count 0 2006.201.16:58:44.19#ibcon#first serial, iclass 16, count 0 2006.201.16:58:44.19#ibcon#enter sib2, iclass 16, count 0 2006.201.16:58:44.19#ibcon#flushed, iclass 16, count 0 2006.201.16:58:44.19#ibcon#about to write, iclass 16, count 0 2006.201.16:58:44.19#ibcon#wrote, iclass 16, count 0 2006.201.16:58:44.19#ibcon#about to read 3, iclass 16, count 0 2006.201.16:58:44.21#ibcon#read 3, iclass 16, count 0 2006.201.16:58:44.21#ibcon#about to read 4, iclass 16, count 0 2006.201.16:58:44.21#ibcon#read 4, iclass 16, count 0 2006.201.16:58:44.21#ibcon#about to read 5, iclass 16, count 0 2006.201.16:58:44.21#ibcon#read 5, iclass 16, count 0 2006.201.16:58:44.21#ibcon#about to read 6, iclass 16, count 0 2006.201.16:58:44.21#ibcon#read 6, iclass 16, count 0 2006.201.16:58:44.21#ibcon#end of sib2, iclass 16, count 0 2006.201.16:58:44.21#ibcon#*mode == 0, iclass 16, count 0 2006.201.16:58:44.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.16:58:44.21#ibcon#[27=USB\r\n] 2006.201.16:58:44.21#ibcon#*before write, iclass 16, count 0 2006.201.16:58:44.21#ibcon#enter sib2, iclass 16, count 0 2006.201.16:58:44.21#ibcon#flushed, iclass 16, count 0 2006.201.16:58:44.21#ibcon#about to write, iclass 16, count 0 2006.201.16:58:44.21#ibcon#wrote, iclass 16, count 0 2006.201.16:58:44.21#ibcon#about to read 3, iclass 16, count 0 2006.201.16:58:44.24#ibcon#read 3, iclass 16, count 0 2006.201.16:58:44.24#ibcon#about to read 4, iclass 16, count 0 2006.201.16:58:44.24#ibcon#read 4, iclass 16, count 0 2006.201.16:58:44.24#ibcon#about to read 5, iclass 16, count 0 2006.201.16:58:44.24#ibcon#read 5, iclass 16, count 0 2006.201.16:58:44.24#ibcon#about to read 6, iclass 16, count 0 2006.201.16:58:44.24#ibcon#read 6, iclass 16, count 0 2006.201.16:58:44.24#ibcon#end of sib2, iclass 16, count 0 2006.201.16:58:44.24#ibcon#*after write, iclass 16, count 0 2006.201.16:58:44.24#ibcon#*before return 0, iclass 16, count 0 2006.201.16:58:44.24#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:44.24#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.16:58:44.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.16:58:44.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.16:58:44.24$vck44/vblo=3,649.99 2006.201.16:58:44.24#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.16:58:44.24#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.16:58:44.24#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:44.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:44.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:44.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:44.24#ibcon#enter wrdev, iclass 18, count 0 2006.201.16:58:44.24#ibcon#first serial, iclass 18, count 0 2006.201.16:58:44.24#ibcon#enter sib2, iclass 18, count 0 2006.201.16:58:44.24#ibcon#flushed, iclass 18, count 0 2006.201.16:58:44.24#ibcon#about to write, iclass 18, count 0 2006.201.16:58:44.24#ibcon#wrote, iclass 18, count 0 2006.201.16:58:44.24#ibcon#about to read 3, iclass 18, count 0 2006.201.16:58:44.26#ibcon#read 3, iclass 18, count 0 2006.201.16:58:44.26#ibcon#about to read 4, iclass 18, count 0 2006.201.16:58:44.26#ibcon#read 4, iclass 18, count 0 2006.201.16:58:44.26#ibcon#about to read 5, iclass 18, count 0 2006.201.16:58:44.26#ibcon#read 5, iclass 18, count 0 2006.201.16:58:44.26#ibcon#about to read 6, iclass 18, count 0 2006.201.16:58:44.26#ibcon#read 6, iclass 18, count 0 2006.201.16:58:44.26#ibcon#end of sib2, iclass 18, count 0 2006.201.16:58:44.26#ibcon#*mode == 0, iclass 18, count 0 2006.201.16:58:44.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.16:58:44.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.16:58:44.26#ibcon#*before write, iclass 18, count 0 2006.201.16:58:44.26#ibcon#enter sib2, iclass 18, count 0 2006.201.16:58:44.26#ibcon#flushed, iclass 18, count 0 2006.201.16:58:44.26#ibcon#about to write, iclass 18, count 0 2006.201.16:58:44.26#ibcon#wrote, iclass 18, count 0 2006.201.16:58:44.26#ibcon#about to read 3, iclass 18, count 0 2006.201.16:58:44.31#ibcon#read 3, iclass 18, count 0 2006.201.16:58:44.31#ibcon#about to read 4, iclass 18, count 0 2006.201.16:58:44.31#ibcon#read 4, iclass 18, count 0 2006.201.16:58:44.31#ibcon#about to read 5, iclass 18, count 0 2006.201.16:58:44.31#ibcon#read 5, iclass 18, count 0 2006.201.16:58:44.31#ibcon#about to read 6, iclass 18, count 0 2006.201.16:58:44.31#ibcon#read 6, iclass 18, count 0 2006.201.16:58:44.31#ibcon#end of sib2, iclass 18, count 0 2006.201.16:58:44.31#ibcon#*after write, iclass 18, count 0 2006.201.16:58:44.31#ibcon#*before return 0, iclass 18, count 0 2006.201.16:58:44.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:44.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.16:58:44.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.16:58:44.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.16:58:44.31$vck44/vb=3,4 2006.201.16:58:44.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.16:58:44.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.16:58:44.31#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:44.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:44.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:44.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:44.36#ibcon#enter wrdev, iclass 20, count 2 2006.201.16:58:44.36#ibcon#first serial, iclass 20, count 2 2006.201.16:58:44.36#ibcon#enter sib2, iclass 20, count 2 2006.201.16:58:44.36#ibcon#flushed, iclass 20, count 2 2006.201.16:58:44.36#ibcon#about to write, iclass 20, count 2 2006.201.16:58:44.36#ibcon#wrote, iclass 20, count 2 2006.201.16:58:44.36#ibcon#about to read 3, iclass 20, count 2 2006.201.16:58:44.38#ibcon#read 3, iclass 20, count 2 2006.201.16:58:44.38#ibcon#about to read 4, iclass 20, count 2 2006.201.16:58:44.38#ibcon#read 4, iclass 20, count 2 2006.201.16:58:44.38#ibcon#about to read 5, iclass 20, count 2 2006.201.16:58:44.38#ibcon#read 5, iclass 20, count 2 2006.201.16:58:44.38#ibcon#about to read 6, iclass 20, count 2 2006.201.16:58:44.38#ibcon#read 6, iclass 20, count 2 2006.201.16:58:44.38#ibcon#end of sib2, iclass 20, count 2 2006.201.16:58:44.38#ibcon#*mode == 0, iclass 20, count 2 2006.201.16:58:44.38#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.16:58:44.38#ibcon#[27=AT03-04\r\n] 2006.201.16:58:44.38#ibcon#*before write, iclass 20, count 2 2006.201.16:58:44.38#ibcon#enter sib2, iclass 20, count 2 2006.201.16:58:44.38#ibcon#flushed, iclass 20, count 2 2006.201.16:58:44.38#ibcon#about to write, iclass 20, count 2 2006.201.16:58:44.38#ibcon#wrote, iclass 20, count 2 2006.201.16:58:44.38#ibcon#about to read 3, iclass 20, count 2 2006.201.16:58:44.41#ibcon#read 3, iclass 20, count 2 2006.201.16:58:44.41#ibcon#about to read 4, iclass 20, count 2 2006.201.16:58:44.41#ibcon#read 4, iclass 20, count 2 2006.201.16:58:44.41#ibcon#about to read 5, iclass 20, count 2 2006.201.16:58:44.41#ibcon#read 5, iclass 20, count 2 2006.201.16:58:44.41#ibcon#about to read 6, iclass 20, count 2 2006.201.16:58:44.41#ibcon#read 6, iclass 20, count 2 2006.201.16:58:44.41#ibcon#end of sib2, iclass 20, count 2 2006.201.16:58:44.41#ibcon#*after write, iclass 20, count 2 2006.201.16:58:44.41#ibcon#*before return 0, iclass 20, count 2 2006.201.16:58:44.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:44.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.16:58:44.41#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.16:58:44.41#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:44.41#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:44.53#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:44.53#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:44.53#ibcon#enter wrdev, iclass 20, count 0 2006.201.16:58:44.53#ibcon#first serial, iclass 20, count 0 2006.201.16:58:44.53#ibcon#enter sib2, iclass 20, count 0 2006.201.16:58:44.53#ibcon#flushed, iclass 20, count 0 2006.201.16:58:44.53#ibcon#about to write, iclass 20, count 0 2006.201.16:58:44.53#ibcon#wrote, iclass 20, count 0 2006.201.16:58:44.53#ibcon#about to read 3, iclass 20, count 0 2006.201.16:58:44.55#ibcon#read 3, iclass 20, count 0 2006.201.16:58:44.55#ibcon#about to read 4, iclass 20, count 0 2006.201.16:58:44.55#ibcon#read 4, iclass 20, count 0 2006.201.16:58:44.55#ibcon#about to read 5, iclass 20, count 0 2006.201.16:58:44.55#ibcon#read 5, iclass 20, count 0 2006.201.16:58:44.55#ibcon#about to read 6, iclass 20, count 0 2006.201.16:58:44.55#ibcon#read 6, iclass 20, count 0 2006.201.16:58:44.55#ibcon#end of sib2, iclass 20, count 0 2006.201.16:58:44.55#ibcon#*mode == 0, iclass 20, count 0 2006.201.16:58:44.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.16:58:44.55#ibcon#[27=USB\r\n] 2006.201.16:58:44.55#ibcon#*before write, iclass 20, count 0 2006.201.16:58:44.55#ibcon#enter sib2, iclass 20, count 0 2006.201.16:58:44.55#ibcon#flushed, iclass 20, count 0 2006.201.16:58:44.55#ibcon#about to write, iclass 20, count 0 2006.201.16:58:44.55#ibcon#wrote, iclass 20, count 0 2006.201.16:58:44.55#ibcon#about to read 3, iclass 20, count 0 2006.201.16:58:44.58#ibcon#read 3, iclass 20, count 0 2006.201.16:58:44.58#ibcon#about to read 4, iclass 20, count 0 2006.201.16:58:44.58#ibcon#read 4, iclass 20, count 0 2006.201.16:58:44.58#ibcon#about to read 5, iclass 20, count 0 2006.201.16:58:44.58#ibcon#read 5, iclass 20, count 0 2006.201.16:58:44.58#ibcon#about to read 6, iclass 20, count 0 2006.201.16:58:44.58#ibcon#read 6, iclass 20, count 0 2006.201.16:58:44.58#ibcon#end of sib2, iclass 20, count 0 2006.201.16:58:44.58#ibcon#*after write, iclass 20, count 0 2006.201.16:58:44.58#ibcon#*before return 0, iclass 20, count 0 2006.201.16:58:44.58#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:44.58#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.16:58:44.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.16:58:44.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.16:58:44.58$vck44/vblo=4,679.99 2006.201.16:58:44.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.16:58:44.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.16:58:44.58#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:44.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:44.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:44.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:44.58#ibcon#enter wrdev, iclass 22, count 0 2006.201.16:58:44.58#ibcon#first serial, iclass 22, count 0 2006.201.16:58:44.58#ibcon#enter sib2, iclass 22, count 0 2006.201.16:58:44.58#ibcon#flushed, iclass 22, count 0 2006.201.16:58:44.58#ibcon#about to write, iclass 22, count 0 2006.201.16:58:44.58#ibcon#wrote, iclass 22, count 0 2006.201.16:58:44.58#ibcon#about to read 3, iclass 22, count 0 2006.201.16:58:44.60#ibcon#read 3, iclass 22, count 0 2006.201.16:58:44.60#ibcon#about to read 4, iclass 22, count 0 2006.201.16:58:44.60#ibcon#read 4, iclass 22, count 0 2006.201.16:58:44.60#ibcon#about to read 5, iclass 22, count 0 2006.201.16:58:44.60#ibcon#read 5, iclass 22, count 0 2006.201.16:58:44.60#ibcon#about to read 6, iclass 22, count 0 2006.201.16:58:44.60#ibcon#read 6, iclass 22, count 0 2006.201.16:58:44.60#ibcon#end of sib2, iclass 22, count 0 2006.201.16:58:44.60#ibcon#*mode == 0, iclass 22, count 0 2006.201.16:58:44.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.16:58:44.60#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.16:58:44.60#ibcon#*before write, iclass 22, count 0 2006.201.16:58:44.60#ibcon#enter sib2, iclass 22, count 0 2006.201.16:58:44.60#ibcon#flushed, iclass 22, count 0 2006.201.16:58:44.60#ibcon#about to write, iclass 22, count 0 2006.201.16:58:44.60#ibcon#wrote, iclass 22, count 0 2006.201.16:58:44.60#ibcon#about to read 3, iclass 22, count 0 2006.201.16:58:44.64#ibcon#read 3, iclass 22, count 0 2006.201.16:58:44.64#ibcon#about to read 4, iclass 22, count 0 2006.201.16:58:44.64#ibcon#read 4, iclass 22, count 0 2006.201.16:58:44.64#ibcon#about to read 5, iclass 22, count 0 2006.201.16:58:44.64#ibcon#read 5, iclass 22, count 0 2006.201.16:58:44.64#ibcon#about to read 6, iclass 22, count 0 2006.201.16:58:44.64#ibcon#read 6, iclass 22, count 0 2006.201.16:58:44.64#ibcon#end of sib2, iclass 22, count 0 2006.201.16:58:44.64#ibcon#*after write, iclass 22, count 0 2006.201.16:58:44.64#ibcon#*before return 0, iclass 22, count 0 2006.201.16:58:44.64#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:44.64#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.16:58:44.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.16:58:44.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.16:58:44.64$vck44/vb=4,5 2006.201.16:58:44.64#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.16:58:44.64#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.16:58:44.64#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:44.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:44.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:44.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:44.70#ibcon#enter wrdev, iclass 24, count 2 2006.201.16:58:44.70#ibcon#first serial, iclass 24, count 2 2006.201.16:58:44.70#ibcon#enter sib2, iclass 24, count 2 2006.201.16:58:44.70#ibcon#flushed, iclass 24, count 2 2006.201.16:58:44.70#ibcon#about to write, iclass 24, count 2 2006.201.16:58:44.70#ibcon#wrote, iclass 24, count 2 2006.201.16:58:44.70#ibcon#about to read 3, iclass 24, count 2 2006.201.16:58:44.72#ibcon#read 3, iclass 24, count 2 2006.201.16:58:44.72#ibcon#about to read 4, iclass 24, count 2 2006.201.16:58:44.72#ibcon#read 4, iclass 24, count 2 2006.201.16:58:44.72#ibcon#about to read 5, iclass 24, count 2 2006.201.16:58:44.72#ibcon#read 5, iclass 24, count 2 2006.201.16:58:44.72#ibcon#about to read 6, iclass 24, count 2 2006.201.16:58:44.72#ibcon#read 6, iclass 24, count 2 2006.201.16:58:44.72#ibcon#end of sib2, iclass 24, count 2 2006.201.16:58:44.72#ibcon#*mode == 0, iclass 24, count 2 2006.201.16:58:44.72#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.16:58:44.72#ibcon#[27=AT04-05\r\n] 2006.201.16:58:44.72#ibcon#*before write, iclass 24, count 2 2006.201.16:58:44.72#ibcon#enter sib2, iclass 24, count 2 2006.201.16:58:44.72#ibcon#flushed, iclass 24, count 2 2006.201.16:58:44.72#ibcon#about to write, iclass 24, count 2 2006.201.16:58:44.72#ibcon#wrote, iclass 24, count 2 2006.201.16:58:44.72#ibcon#about to read 3, iclass 24, count 2 2006.201.16:58:44.75#ibcon#read 3, iclass 24, count 2 2006.201.16:58:44.75#ibcon#about to read 4, iclass 24, count 2 2006.201.16:58:44.75#ibcon#read 4, iclass 24, count 2 2006.201.16:58:44.75#ibcon#about to read 5, iclass 24, count 2 2006.201.16:58:44.75#ibcon#read 5, iclass 24, count 2 2006.201.16:58:44.75#ibcon#about to read 6, iclass 24, count 2 2006.201.16:58:44.75#ibcon#read 6, iclass 24, count 2 2006.201.16:58:44.75#ibcon#end of sib2, iclass 24, count 2 2006.201.16:58:44.75#ibcon#*after write, iclass 24, count 2 2006.201.16:58:44.75#ibcon#*before return 0, iclass 24, count 2 2006.201.16:58:44.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:44.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.16:58:44.75#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.16:58:44.75#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:44.75#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:44.87#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:44.87#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:44.87#ibcon#enter wrdev, iclass 24, count 0 2006.201.16:58:44.87#ibcon#first serial, iclass 24, count 0 2006.201.16:58:44.87#ibcon#enter sib2, iclass 24, count 0 2006.201.16:58:44.87#ibcon#flushed, iclass 24, count 0 2006.201.16:58:44.87#ibcon#about to write, iclass 24, count 0 2006.201.16:58:44.87#ibcon#wrote, iclass 24, count 0 2006.201.16:58:44.87#ibcon#about to read 3, iclass 24, count 0 2006.201.16:58:44.89#ibcon#read 3, iclass 24, count 0 2006.201.16:58:44.89#ibcon#about to read 4, iclass 24, count 0 2006.201.16:58:44.89#ibcon#read 4, iclass 24, count 0 2006.201.16:58:44.89#ibcon#about to read 5, iclass 24, count 0 2006.201.16:58:44.89#ibcon#read 5, iclass 24, count 0 2006.201.16:58:44.89#ibcon#about to read 6, iclass 24, count 0 2006.201.16:58:44.89#ibcon#read 6, iclass 24, count 0 2006.201.16:58:44.89#ibcon#end of sib2, iclass 24, count 0 2006.201.16:58:44.89#ibcon#*mode == 0, iclass 24, count 0 2006.201.16:58:44.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.16:58:44.89#ibcon#[27=USB\r\n] 2006.201.16:58:44.89#ibcon#*before write, iclass 24, count 0 2006.201.16:58:44.89#ibcon#enter sib2, iclass 24, count 0 2006.201.16:58:44.89#ibcon#flushed, iclass 24, count 0 2006.201.16:58:44.89#ibcon#about to write, iclass 24, count 0 2006.201.16:58:44.89#ibcon#wrote, iclass 24, count 0 2006.201.16:58:44.89#ibcon#about to read 3, iclass 24, count 0 2006.201.16:58:44.92#ibcon#read 3, iclass 24, count 0 2006.201.16:58:44.92#ibcon#about to read 4, iclass 24, count 0 2006.201.16:58:44.92#ibcon#read 4, iclass 24, count 0 2006.201.16:58:44.92#ibcon#about to read 5, iclass 24, count 0 2006.201.16:58:44.92#ibcon#read 5, iclass 24, count 0 2006.201.16:58:44.92#ibcon#about to read 6, iclass 24, count 0 2006.201.16:58:44.92#ibcon#read 6, iclass 24, count 0 2006.201.16:58:44.92#ibcon#end of sib2, iclass 24, count 0 2006.201.16:58:44.92#ibcon#*after write, iclass 24, count 0 2006.201.16:58:44.92#ibcon#*before return 0, iclass 24, count 0 2006.201.16:58:44.92#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:44.92#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.16:58:44.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.16:58:44.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.16:58:44.92$vck44/vblo=5,709.99 2006.201.16:58:44.92#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.16:58:44.92#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.16:58:44.92#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:44.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:44.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:44.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:44.92#ibcon#enter wrdev, iclass 26, count 0 2006.201.16:58:44.92#ibcon#first serial, iclass 26, count 0 2006.201.16:58:44.92#ibcon#enter sib2, iclass 26, count 0 2006.201.16:58:44.92#ibcon#flushed, iclass 26, count 0 2006.201.16:58:44.92#ibcon#about to write, iclass 26, count 0 2006.201.16:58:44.92#ibcon#wrote, iclass 26, count 0 2006.201.16:58:44.92#ibcon#about to read 3, iclass 26, count 0 2006.201.16:58:44.94#ibcon#read 3, iclass 26, count 0 2006.201.16:58:44.94#ibcon#about to read 4, iclass 26, count 0 2006.201.16:58:44.94#ibcon#read 4, iclass 26, count 0 2006.201.16:58:44.94#ibcon#about to read 5, iclass 26, count 0 2006.201.16:58:44.94#ibcon#read 5, iclass 26, count 0 2006.201.16:58:44.94#ibcon#about to read 6, iclass 26, count 0 2006.201.16:58:44.94#ibcon#read 6, iclass 26, count 0 2006.201.16:58:44.94#ibcon#end of sib2, iclass 26, count 0 2006.201.16:58:44.94#ibcon#*mode == 0, iclass 26, count 0 2006.201.16:58:44.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.16:58:44.94#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.16:58:44.94#ibcon#*before write, iclass 26, count 0 2006.201.16:58:44.94#ibcon#enter sib2, iclass 26, count 0 2006.201.16:58:44.94#ibcon#flushed, iclass 26, count 0 2006.201.16:58:44.94#ibcon#about to write, iclass 26, count 0 2006.201.16:58:44.94#ibcon#wrote, iclass 26, count 0 2006.201.16:58:44.94#ibcon#about to read 3, iclass 26, count 0 2006.201.16:58:44.98#ibcon#read 3, iclass 26, count 0 2006.201.16:58:44.98#ibcon#about to read 4, iclass 26, count 0 2006.201.16:58:44.98#ibcon#read 4, iclass 26, count 0 2006.201.16:58:44.98#ibcon#about to read 5, iclass 26, count 0 2006.201.16:58:44.98#ibcon#read 5, iclass 26, count 0 2006.201.16:58:44.98#ibcon#about to read 6, iclass 26, count 0 2006.201.16:58:44.98#ibcon#read 6, iclass 26, count 0 2006.201.16:58:44.98#ibcon#end of sib2, iclass 26, count 0 2006.201.16:58:44.98#ibcon#*after write, iclass 26, count 0 2006.201.16:58:44.98#ibcon#*before return 0, iclass 26, count 0 2006.201.16:58:44.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:44.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.16:58:44.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.16:58:44.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.16:58:44.98$vck44/vb=5,4 2006.201.16:58:44.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.16:58:44.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.16:58:44.98#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:44.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:45.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:45.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:45.04#ibcon#enter wrdev, iclass 28, count 2 2006.201.16:58:45.04#ibcon#first serial, iclass 28, count 2 2006.201.16:58:45.04#ibcon#enter sib2, iclass 28, count 2 2006.201.16:58:45.04#ibcon#flushed, iclass 28, count 2 2006.201.16:58:45.04#ibcon#about to write, iclass 28, count 2 2006.201.16:58:45.04#ibcon#wrote, iclass 28, count 2 2006.201.16:58:45.04#ibcon#about to read 3, iclass 28, count 2 2006.201.16:58:45.06#ibcon#read 3, iclass 28, count 2 2006.201.16:58:45.06#ibcon#about to read 4, iclass 28, count 2 2006.201.16:58:45.06#ibcon#read 4, iclass 28, count 2 2006.201.16:58:45.06#ibcon#about to read 5, iclass 28, count 2 2006.201.16:58:45.06#ibcon#read 5, iclass 28, count 2 2006.201.16:58:45.06#ibcon#about to read 6, iclass 28, count 2 2006.201.16:58:45.06#ibcon#read 6, iclass 28, count 2 2006.201.16:58:45.06#ibcon#end of sib2, iclass 28, count 2 2006.201.16:58:45.06#ibcon#*mode == 0, iclass 28, count 2 2006.201.16:58:45.06#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.16:58:45.06#ibcon#[27=AT05-04\r\n] 2006.201.16:58:45.06#ibcon#*before write, iclass 28, count 2 2006.201.16:58:45.06#ibcon#enter sib2, iclass 28, count 2 2006.201.16:58:45.06#ibcon#flushed, iclass 28, count 2 2006.201.16:58:45.06#ibcon#about to write, iclass 28, count 2 2006.201.16:58:45.06#ibcon#wrote, iclass 28, count 2 2006.201.16:58:45.06#ibcon#about to read 3, iclass 28, count 2 2006.201.16:58:45.09#ibcon#read 3, iclass 28, count 2 2006.201.16:58:45.09#ibcon#about to read 4, iclass 28, count 2 2006.201.16:58:45.09#ibcon#read 4, iclass 28, count 2 2006.201.16:58:45.09#ibcon#about to read 5, iclass 28, count 2 2006.201.16:58:45.09#ibcon#read 5, iclass 28, count 2 2006.201.16:58:45.09#ibcon#about to read 6, iclass 28, count 2 2006.201.16:58:45.09#ibcon#read 6, iclass 28, count 2 2006.201.16:58:45.09#ibcon#end of sib2, iclass 28, count 2 2006.201.16:58:45.09#ibcon#*after write, iclass 28, count 2 2006.201.16:58:45.09#ibcon#*before return 0, iclass 28, count 2 2006.201.16:58:45.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:45.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.16:58:45.09#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.16:58:45.09#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:45.09#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:45.21#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:45.21#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:45.21#ibcon#enter wrdev, iclass 28, count 0 2006.201.16:58:45.21#ibcon#first serial, iclass 28, count 0 2006.201.16:58:45.21#ibcon#enter sib2, iclass 28, count 0 2006.201.16:58:45.21#ibcon#flushed, iclass 28, count 0 2006.201.16:58:45.21#ibcon#about to write, iclass 28, count 0 2006.201.16:58:45.21#ibcon#wrote, iclass 28, count 0 2006.201.16:58:45.21#ibcon#about to read 3, iclass 28, count 0 2006.201.16:58:45.23#ibcon#read 3, iclass 28, count 0 2006.201.16:58:45.23#ibcon#about to read 4, iclass 28, count 0 2006.201.16:58:45.23#ibcon#read 4, iclass 28, count 0 2006.201.16:58:45.23#ibcon#about to read 5, iclass 28, count 0 2006.201.16:58:45.23#ibcon#read 5, iclass 28, count 0 2006.201.16:58:45.23#ibcon#about to read 6, iclass 28, count 0 2006.201.16:58:45.23#ibcon#read 6, iclass 28, count 0 2006.201.16:58:45.23#ibcon#end of sib2, iclass 28, count 0 2006.201.16:58:45.23#ibcon#*mode == 0, iclass 28, count 0 2006.201.16:58:45.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.16:58:45.23#ibcon#[27=USB\r\n] 2006.201.16:58:45.23#ibcon#*before write, iclass 28, count 0 2006.201.16:58:45.23#ibcon#enter sib2, iclass 28, count 0 2006.201.16:58:45.23#ibcon#flushed, iclass 28, count 0 2006.201.16:58:45.23#ibcon#about to write, iclass 28, count 0 2006.201.16:58:45.23#ibcon#wrote, iclass 28, count 0 2006.201.16:58:45.23#ibcon#about to read 3, iclass 28, count 0 2006.201.16:58:45.26#ibcon#read 3, iclass 28, count 0 2006.201.16:58:45.26#ibcon#about to read 4, iclass 28, count 0 2006.201.16:58:45.26#ibcon#read 4, iclass 28, count 0 2006.201.16:58:45.26#ibcon#about to read 5, iclass 28, count 0 2006.201.16:58:45.26#ibcon#read 5, iclass 28, count 0 2006.201.16:58:45.26#ibcon#about to read 6, iclass 28, count 0 2006.201.16:58:45.26#ibcon#read 6, iclass 28, count 0 2006.201.16:58:45.26#ibcon#end of sib2, iclass 28, count 0 2006.201.16:58:45.26#ibcon#*after write, iclass 28, count 0 2006.201.16:58:45.26#ibcon#*before return 0, iclass 28, count 0 2006.201.16:58:45.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:45.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.16:58:45.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.16:58:45.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.16:58:45.26$vck44/vblo=6,719.99 2006.201.16:58:45.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.16:58:45.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.16:58:45.26#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:45.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:58:45.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:58:45.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:58:45.26#ibcon#enter wrdev, iclass 31, count 0 2006.201.16:58:45.26#ibcon#first serial, iclass 31, count 0 2006.201.16:58:45.26#ibcon#enter sib2, iclass 31, count 0 2006.201.16:58:45.26#ibcon#flushed, iclass 31, count 0 2006.201.16:58:45.26#ibcon#about to write, iclass 31, count 0 2006.201.16:58:45.26#ibcon#wrote, iclass 31, count 0 2006.201.16:58:45.26#ibcon#about to read 3, iclass 31, count 0 2006.201.16:58:45.27#abcon#<5=/03 0.4 1.2 20.801001002.6\r\n> 2006.201.16:58:45.28#ibcon#read 3, iclass 31, count 0 2006.201.16:58:45.28#ibcon#about to read 4, iclass 31, count 0 2006.201.16:58:45.28#ibcon#read 4, iclass 31, count 0 2006.201.16:58:45.28#ibcon#about to read 5, iclass 31, count 0 2006.201.16:58:45.28#ibcon#read 5, iclass 31, count 0 2006.201.16:58:45.28#ibcon#about to read 6, iclass 31, count 0 2006.201.16:58:45.28#ibcon#read 6, iclass 31, count 0 2006.201.16:58:45.28#ibcon#end of sib2, iclass 31, count 0 2006.201.16:58:45.28#ibcon#*mode == 0, iclass 31, count 0 2006.201.16:58:45.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.16:58:45.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.16:58:45.28#ibcon#*before write, iclass 31, count 0 2006.201.16:58:45.28#ibcon#enter sib2, iclass 31, count 0 2006.201.16:58:45.28#ibcon#flushed, iclass 31, count 0 2006.201.16:58:45.28#ibcon#about to write, iclass 31, count 0 2006.201.16:58:45.28#ibcon#wrote, iclass 31, count 0 2006.201.16:58:45.28#ibcon#about to read 3, iclass 31, count 0 2006.201.16:58:45.29#abcon#{5=INTERFACE CLEAR} 2006.201.16:58:45.32#ibcon#read 3, iclass 31, count 0 2006.201.16:58:45.32#ibcon#about to read 4, iclass 31, count 0 2006.201.16:58:45.32#ibcon#read 4, iclass 31, count 0 2006.201.16:58:45.32#ibcon#about to read 5, iclass 31, count 0 2006.201.16:58:45.32#ibcon#read 5, iclass 31, count 0 2006.201.16:58:45.32#ibcon#about to read 6, iclass 31, count 0 2006.201.16:58:45.32#ibcon#read 6, iclass 31, count 0 2006.201.16:58:45.32#ibcon#end of sib2, iclass 31, count 0 2006.201.16:58:45.32#ibcon#*after write, iclass 31, count 0 2006.201.16:58:45.32#ibcon#*before return 0, iclass 31, count 0 2006.201.16:58:45.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:58:45.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.16:58:45.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.16:58:45.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.16:58:45.32$vck44/vb=6,4 2006.201.16:58:45.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.16:58:45.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.16:58:45.32#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:45.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:58:45.35#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:58:45.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:58:45.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:58:45.38#ibcon#enter wrdev, iclass 35, count 2 2006.201.16:58:45.38#ibcon#first serial, iclass 35, count 2 2006.201.16:58:45.38#ibcon#enter sib2, iclass 35, count 2 2006.201.16:58:45.38#ibcon#flushed, iclass 35, count 2 2006.201.16:58:45.38#ibcon#about to write, iclass 35, count 2 2006.201.16:58:45.38#ibcon#wrote, iclass 35, count 2 2006.201.16:58:45.38#ibcon#about to read 3, iclass 35, count 2 2006.201.16:58:45.40#ibcon#read 3, iclass 35, count 2 2006.201.16:58:45.40#ibcon#about to read 4, iclass 35, count 2 2006.201.16:58:45.40#ibcon#read 4, iclass 35, count 2 2006.201.16:58:45.40#ibcon#about to read 5, iclass 35, count 2 2006.201.16:58:45.40#ibcon#read 5, iclass 35, count 2 2006.201.16:58:45.40#ibcon#about to read 6, iclass 35, count 2 2006.201.16:58:45.40#ibcon#read 6, iclass 35, count 2 2006.201.16:58:45.40#ibcon#end of sib2, iclass 35, count 2 2006.201.16:58:45.40#ibcon#*mode == 0, iclass 35, count 2 2006.201.16:58:45.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.16:58:45.40#ibcon#[27=AT06-04\r\n] 2006.201.16:58:45.40#ibcon#*before write, iclass 35, count 2 2006.201.16:58:45.40#ibcon#enter sib2, iclass 35, count 2 2006.201.16:58:45.40#ibcon#flushed, iclass 35, count 2 2006.201.16:58:45.40#ibcon#about to write, iclass 35, count 2 2006.201.16:58:45.40#ibcon#wrote, iclass 35, count 2 2006.201.16:58:45.40#ibcon#about to read 3, iclass 35, count 2 2006.201.16:58:45.43#ibcon#read 3, iclass 35, count 2 2006.201.16:58:45.43#ibcon#about to read 4, iclass 35, count 2 2006.201.16:58:45.43#ibcon#read 4, iclass 35, count 2 2006.201.16:58:45.43#ibcon#about to read 5, iclass 35, count 2 2006.201.16:58:45.43#ibcon#read 5, iclass 35, count 2 2006.201.16:58:45.43#ibcon#about to read 6, iclass 35, count 2 2006.201.16:58:45.43#ibcon#read 6, iclass 35, count 2 2006.201.16:58:45.43#ibcon#end of sib2, iclass 35, count 2 2006.201.16:58:45.43#ibcon#*after write, iclass 35, count 2 2006.201.16:58:45.43#ibcon#*before return 0, iclass 35, count 2 2006.201.16:58:45.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:58:45.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.16:58:45.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.16:58:45.43#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:45.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:58:45.55#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:58:45.55#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:58:45.55#ibcon#enter wrdev, iclass 35, count 0 2006.201.16:58:45.55#ibcon#first serial, iclass 35, count 0 2006.201.16:58:45.55#ibcon#enter sib2, iclass 35, count 0 2006.201.16:58:45.55#ibcon#flushed, iclass 35, count 0 2006.201.16:58:45.55#ibcon#about to write, iclass 35, count 0 2006.201.16:58:45.55#ibcon#wrote, iclass 35, count 0 2006.201.16:58:45.55#ibcon#about to read 3, iclass 35, count 0 2006.201.16:58:45.57#ibcon#read 3, iclass 35, count 0 2006.201.16:58:45.57#ibcon#about to read 4, iclass 35, count 0 2006.201.16:58:45.57#ibcon#read 4, iclass 35, count 0 2006.201.16:58:45.57#ibcon#about to read 5, iclass 35, count 0 2006.201.16:58:45.57#ibcon#read 5, iclass 35, count 0 2006.201.16:58:45.57#ibcon#about to read 6, iclass 35, count 0 2006.201.16:58:45.57#ibcon#read 6, iclass 35, count 0 2006.201.16:58:45.57#ibcon#end of sib2, iclass 35, count 0 2006.201.16:58:45.57#ibcon#*mode == 0, iclass 35, count 0 2006.201.16:58:45.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.16:58:45.57#ibcon#[27=USB\r\n] 2006.201.16:58:45.57#ibcon#*before write, iclass 35, count 0 2006.201.16:58:45.57#ibcon#enter sib2, iclass 35, count 0 2006.201.16:58:45.57#ibcon#flushed, iclass 35, count 0 2006.201.16:58:45.57#ibcon#about to write, iclass 35, count 0 2006.201.16:58:45.57#ibcon#wrote, iclass 35, count 0 2006.201.16:58:45.57#ibcon#about to read 3, iclass 35, count 0 2006.201.16:58:45.60#ibcon#read 3, iclass 35, count 0 2006.201.16:58:45.60#ibcon#about to read 4, iclass 35, count 0 2006.201.16:58:45.60#ibcon#read 4, iclass 35, count 0 2006.201.16:58:45.60#ibcon#about to read 5, iclass 35, count 0 2006.201.16:58:45.60#ibcon#read 5, iclass 35, count 0 2006.201.16:58:45.60#ibcon#about to read 6, iclass 35, count 0 2006.201.16:58:45.60#ibcon#read 6, iclass 35, count 0 2006.201.16:58:45.60#ibcon#end of sib2, iclass 35, count 0 2006.201.16:58:45.60#ibcon#*after write, iclass 35, count 0 2006.201.16:58:45.60#ibcon#*before return 0, iclass 35, count 0 2006.201.16:58:45.60#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:58:45.60#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.16:58:45.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.16:58:45.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.16:58:45.60$vck44/vblo=7,734.99 2006.201.16:58:45.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.16:58:45.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.16:58:45.60#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:45.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:45.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:45.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:45.60#ibcon#enter wrdev, iclass 38, count 0 2006.201.16:58:45.60#ibcon#first serial, iclass 38, count 0 2006.201.16:58:45.60#ibcon#enter sib2, iclass 38, count 0 2006.201.16:58:45.60#ibcon#flushed, iclass 38, count 0 2006.201.16:58:45.60#ibcon#about to write, iclass 38, count 0 2006.201.16:58:45.60#ibcon#wrote, iclass 38, count 0 2006.201.16:58:45.60#ibcon#about to read 3, iclass 38, count 0 2006.201.16:58:45.62#ibcon#read 3, iclass 38, count 0 2006.201.16:58:45.62#ibcon#about to read 4, iclass 38, count 0 2006.201.16:58:45.62#ibcon#read 4, iclass 38, count 0 2006.201.16:58:45.62#ibcon#about to read 5, iclass 38, count 0 2006.201.16:58:45.62#ibcon#read 5, iclass 38, count 0 2006.201.16:58:45.62#ibcon#about to read 6, iclass 38, count 0 2006.201.16:58:45.62#ibcon#read 6, iclass 38, count 0 2006.201.16:58:45.62#ibcon#end of sib2, iclass 38, count 0 2006.201.16:58:45.62#ibcon#*mode == 0, iclass 38, count 0 2006.201.16:58:45.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.16:58:45.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.16:58:45.62#ibcon#*before write, iclass 38, count 0 2006.201.16:58:45.62#ibcon#enter sib2, iclass 38, count 0 2006.201.16:58:45.62#ibcon#flushed, iclass 38, count 0 2006.201.16:58:45.62#ibcon#about to write, iclass 38, count 0 2006.201.16:58:45.62#ibcon#wrote, iclass 38, count 0 2006.201.16:58:45.62#ibcon#about to read 3, iclass 38, count 0 2006.201.16:58:45.66#ibcon#read 3, iclass 38, count 0 2006.201.16:58:45.66#ibcon#about to read 4, iclass 38, count 0 2006.201.16:58:45.66#ibcon#read 4, iclass 38, count 0 2006.201.16:58:45.66#ibcon#about to read 5, iclass 38, count 0 2006.201.16:58:45.66#ibcon#read 5, iclass 38, count 0 2006.201.16:58:45.66#ibcon#about to read 6, iclass 38, count 0 2006.201.16:58:45.66#ibcon#read 6, iclass 38, count 0 2006.201.16:58:45.66#ibcon#end of sib2, iclass 38, count 0 2006.201.16:58:45.66#ibcon#*after write, iclass 38, count 0 2006.201.16:58:45.66#ibcon#*before return 0, iclass 38, count 0 2006.201.16:58:45.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:45.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.16:58:45.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.16:58:45.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.16:58:45.66$vck44/vb=7,4 2006.201.16:58:45.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.16:58:45.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.16:58:45.66#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:45.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:45.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:45.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:45.72#ibcon#enter wrdev, iclass 40, count 2 2006.201.16:58:45.72#ibcon#first serial, iclass 40, count 2 2006.201.16:58:45.72#ibcon#enter sib2, iclass 40, count 2 2006.201.16:58:45.72#ibcon#flushed, iclass 40, count 2 2006.201.16:58:45.72#ibcon#about to write, iclass 40, count 2 2006.201.16:58:45.72#ibcon#wrote, iclass 40, count 2 2006.201.16:58:45.72#ibcon#about to read 3, iclass 40, count 2 2006.201.16:58:45.74#ibcon#read 3, iclass 40, count 2 2006.201.16:58:45.74#ibcon#about to read 4, iclass 40, count 2 2006.201.16:58:45.74#ibcon#read 4, iclass 40, count 2 2006.201.16:58:45.74#ibcon#about to read 5, iclass 40, count 2 2006.201.16:58:45.74#ibcon#read 5, iclass 40, count 2 2006.201.16:58:45.74#ibcon#about to read 6, iclass 40, count 2 2006.201.16:58:45.74#ibcon#read 6, iclass 40, count 2 2006.201.16:58:45.74#ibcon#end of sib2, iclass 40, count 2 2006.201.16:58:45.74#ibcon#*mode == 0, iclass 40, count 2 2006.201.16:58:45.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.16:58:45.74#ibcon#[27=AT07-04\r\n] 2006.201.16:58:45.74#ibcon#*before write, iclass 40, count 2 2006.201.16:58:45.74#ibcon#enter sib2, iclass 40, count 2 2006.201.16:58:45.74#ibcon#flushed, iclass 40, count 2 2006.201.16:58:45.74#ibcon#about to write, iclass 40, count 2 2006.201.16:58:45.74#ibcon#wrote, iclass 40, count 2 2006.201.16:58:45.74#ibcon#about to read 3, iclass 40, count 2 2006.201.16:58:45.77#ibcon#read 3, iclass 40, count 2 2006.201.16:58:45.77#ibcon#about to read 4, iclass 40, count 2 2006.201.16:58:45.77#ibcon#read 4, iclass 40, count 2 2006.201.16:58:45.77#ibcon#about to read 5, iclass 40, count 2 2006.201.16:58:45.77#ibcon#read 5, iclass 40, count 2 2006.201.16:58:45.77#ibcon#about to read 6, iclass 40, count 2 2006.201.16:58:45.77#ibcon#read 6, iclass 40, count 2 2006.201.16:58:45.77#ibcon#end of sib2, iclass 40, count 2 2006.201.16:58:45.77#ibcon#*after write, iclass 40, count 2 2006.201.16:58:45.77#ibcon#*before return 0, iclass 40, count 2 2006.201.16:58:45.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:45.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.16:58:45.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.16:58:45.77#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:45.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:45.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:45.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:45.89#ibcon#enter wrdev, iclass 40, count 0 2006.201.16:58:45.89#ibcon#first serial, iclass 40, count 0 2006.201.16:58:45.89#ibcon#enter sib2, iclass 40, count 0 2006.201.16:58:45.89#ibcon#flushed, iclass 40, count 0 2006.201.16:58:45.89#ibcon#about to write, iclass 40, count 0 2006.201.16:58:45.89#ibcon#wrote, iclass 40, count 0 2006.201.16:58:45.89#ibcon#about to read 3, iclass 40, count 0 2006.201.16:58:45.91#ibcon#read 3, iclass 40, count 0 2006.201.16:58:45.91#ibcon#about to read 4, iclass 40, count 0 2006.201.16:58:45.91#ibcon#read 4, iclass 40, count 0 2006.201.16:58:45.91#ibcon#about to read 5, iclass 40, count 0 2006.201.16:58:45.91#ibcon#read 5, iclass 40, count 0 2006.201.16:58:45.91#ibcon#about to read 6, iclass 40, count 0 2006.201.16:58:45.91#ibcon#read 6, iclass 40, count 0 2006.201.16:58:45.91#ibcon#end of sib2, iclass 40, count 0 2006.201.16:58:45.91#ibcon#*mode == 0, iclass 40, count 0 2006.201.16:58:45.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.16:58:45.91#ibcon#[27=USB\r\n] 2006.201.16:58:45.91#ibcon#*before write, iclass 40, count 0 2006.201.16:58:45.91#ibcon#enter sib2, iclass 40, count 0 2006.201.16:58:45.91#ibcon#flushed, iclass 40, count 0 2006.201.16:58:45.91#ibcon#about to write, iclass 40, count 0 2006.201.16:58:45.91#ibcon#wrote, iclass 40, count 0 2006.201.16:58:45.91#ibcon#about to read 3, iclass 40, count 0 2006.201.16:58:45.94#ibcon#read 3, iclass 40, count 0 2006.201.16:58:45.94#ibcon#about to read 4, iclass 40, count 0 2006.201.16:58:45.94#ibcon#read 4, iclass 40, count 0 2006.201.16:58:45.94#ibcon#about to read 5, iclass 40, count 0 2006.201.16:58:45.94#ibcon#read 5, iclass 40, count 0 2006.201.16:58:45.94#ibcon#about to read 6, iclass 40, count 0 2006.201.16:58:45.94#ibcon#read 6, iclass 40, count 0 2006.201.16:58:45.94#ibcon#end of sib2, iclass 40, count 0 2006.201.16:58:45.94#ibcon#*after write, iclass 40, count 0 2006.201.16:58:45.94#ibcon#*before return 0, iclass 40, count 0 2006.201.16:58:45.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:45.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.16:58:45.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.16:58:45.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.16:58:45.94$vck44/vblo=8,744.99 2006.201.16:58:45.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.16:58:45.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.16:58:45.94#ibcon#ireg 17 cls_cnt 0 2006.201.16:58:45.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:45.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:45.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:45.94#ibcon#enter wrdev, iclass 4, count 0 2006.201.16:58:45.94#ibcon#first serial, iclass 4, count 0 2006.201.16:58:45.94#ibcon#enter sib2, iclass 4, count 0 2006.201.16:58:45.94#ibcon#flushed, iclass 4, count 0 2006.201.16:58:45.94#ibcon#about to write, iclass 4, count 0 2006.201.16:58:45.94#ibcon#wrote, iclass 4, count 0 2006.201.16:58:45.94#ibcon#about to read 3, iclass 4, count 0 2006.201.16:58:45.96#ibcon#read 3, iclass 4, count 0 2006.201.16:58:45.96#ibcon#about to read 4, iclass 4, count 0 2006.201.16:58:45.96#ibcon#read 4, iclass 4, count 0 2006.201.16:58:45.96#ibcon#about to read 5, iclass 4, count 0 2006.201.16:58:45.96#ibcon#read 5, iclass 4, count 0 2006.201.16:58:45.96#ibcon#about to read 6, iclass 4, count 0 2006.201.16:58:45.96#ibcon#read 6, iclass 4, count 0 2006.201.16:58:45.96#ibcon#end of sib2, iclass 4, count 0 2006.201.16:58:45.96#ibcon#*mode == 0, iclass 4, count 0 2006.201.16:58:45.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.16:58:45.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.16:58:45.96#ibcon#*before write, iclass 4, count 0 2006.201.16:58:45.96#ibcon#enter sib2, iclass 4, count 0 2006.201.16:58:45.96#ibcon#flushed, iclass 4, count 0 2006.201.16:58:45.96#ibcon#about to write, iclass 4, count 0 2006.201.16:58:45.96#ibcon#wrote, iclass 4, count 0 2006.201.16:58:45.96#ibcon#about to read 3, iclass 4, count 0 2006.201.16:58:46.00#ibcon#read 3, iclass 4, count 0 2006.201.16:58:46.00#ibcon#about to read 4, iclass 4, count 0 2006.201.16:58:46.00#ibcon#read 4, iclass 4, count 0 2006.201.16:58:46.00#ibcon#about to read 5, iclass 4, count 0 2006.201.16:58:46.00#ibcon#read 5, iclass 4, count 0 2006.201.16:58:46.00#ibcon#about to read 6, iclass 4, count 0 2006.201.16:58:46.00#ibcon#read 6, iclass 4, count 0 2006.201.16:58:46.00#ibcon#end of sib2, iclass 4, count 0 2006.201.16:58:46.00#ibcon#*after write, iclass 4, count 0 2006.201.16:58:46.00#ibcon#*before return 0, iclass 4, count 0 2006.201.16:58:46.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:46.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.16:58:46.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.16:58:46.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.16:58:46.00$vck44/vb=8,4 2006.201.16:58:46.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.16:58:46.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.16:58:46.00#ibcon#ireg 11 cls_cnt 2 2006.201.16:58:46.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:46.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:46.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:46.06#ibcon#enter wrdev, iclass 6, count 2 2006.201.16:58:46.06#ibcon#first serial, iclass 6, count 2 2006.201.16:58:46.06#ibcon#enter sib2, iclass 6, count 2 2006.201.16:58:46.06#ibcon#flushed, iclass 6, count 2 2006.201.16:58:46.06#ibcon#about to write, iclass 6, count 2 2006.201.16:58:46.06#ibcon#wrote, iclass 6, count 2 2006.201.16:58:46.06#ibcon#about to read 3, iclass 6, count 2 2006.201.16:58:46.08#ibcon#read 3, iclass 6, count 2 2006.201.16:58:46.08#ibcon#about to read 4, iclass 6, count 2 2006.201.16:58:46.08#ibcon#read 4, iclass 6, count 2 2006.201.16:58:46.08#ibcon#about to read 5, iclass 6, count 2 2006.201.16:58:46.08#ibcon#read 5, iclass 6, count 2 2006.201.16:58:46.08#ibcon#about to read 6, iclass 6, count 2 2006.201.16:58:46.08#ibcon#read 6, iclass 6, count 2 2006.201.16:58:46.08#ibcon#end of sib2, iclass 6, count 2 2006.201.16:58:46.08#ibcon#*mode == 0, iclass 6, count 2 2006.201.16:58:46.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.16:58:46.08#ibcon#[27=AT08-04\r\n] 2006.201.16:58:46.08#ibcon#*before write, iclass 6, count 2 2006.201.16:58:46.08#ibcon#enter sib2, iclass 6, count 2 2006.201.16:58:46.08#ibcon#flushed, iclass 6, count 2 2006.201.16:58:46.08#ibcon#about to write, iclass 6, count 2 2006.201.16:58:46.08#ibcon#wrote, iclass 6, count 2 2006.201.16:58:46.08#ibcon#about to read 3, iclass 6, count 2 2006.201.16:58:46.11#ibcon#read 3, iclass 6, count 2 2006.201.16:58:46.11#ibcon#about to read 4, iclass 6, count 2 2006.201.16:58:46.11#ibcon#read 4, iclass 6, count 2 2006.201.16:58:46.11#ibcon#about to read 5, iclass 6, count 2 2006.201.16:58:46.11#ibcon#read 5, iclass 6, count 2 2006.201.16:58:46.11#ibcon#about to read 6, iclass 6, count 2 2006.201.16:58:46.11#ibcon#read 6, iclass 6, count 2 2006.201.16:58:46.11#ibcon#end of sib2, iclass 6, count 2 2006.201.16:58:46.11#ibcon#*after write, iclass 6, count 2 2006.201.16:58:46.11#ibcon#*before return 0, iclass 6, count 2 2006.201.16:58:46.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:46.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.16:58:46.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.16:58:46.11#ibcon#ireg 7 cls_cnt 0 2006.201.16:58:46.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:46.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:46.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:46.23#ibcon#enter wrdev, iclass 6, count 0 2006.201.16:58:46.23#ibcon#first serial, iclass 6, count 0 2006.201.16:58:46.23#ibcon#enter sib2, iclass 6, count 0 2006.201.16:58:46.23#ibcon#flushed, iclass 6, count 0 2006.201.16:58:46.23#ibcon#about to write, iclass 6, count 0 2006.201.16:58:46.23#ibcon#wrote, iclass 6, count 0 2006.201.16:58:46.23#ibcon#about to read 3, iclass 6, count 0 2006.201.16:58:46.25#ibcon#read 3, iclass 6, count 0 2006.201.16:58:46.25#ibcon#about to read 4, iclass 6, count 0 2006.201.16:58:46.25#ibcon#read 4, iclass 6, count 0 2006.201.16:58:46.25#ibcon#about to read 5, iclass 6, count 0 2006.201.16:58:46.25#ibcon#read 5, iclass 6, count 0 2006.201.16:58:46.25#ibcon#about to read 6, iclass 6, count 0 2006.201.16:58:46.25#ibcon#read 6, iclass 6, count 0 2006.201.16:58:46.25#ibcon#end of sib2, iclass 6, count 0 2006.201.16:58:46.25#ibcon#*mode == 0, iclass 6, count 0 2006.201.16:58:46.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.16:58:46.25#ibcon#[27=USB\r\n] 2006.201.16:58:46.25#ibcon#*before write, iclass 6, count 0 2006.201.16:58:46.25#ibcon#enter sib2, iclass 6, count 0 2006.201.16:58:46.25#ibcon#flushed, iclass 6, count 0 2006.201.16:58:46.25#ibcon#about to write, iclass 6, count 0 2006.201.16:58:46.25#ibcon#wrote, iclass 6, count 0 2006.201.16:58:46.25#ibcon#about to read 3, iclass 6, count 0 2006.201.16:58:46.28#ibcon#read 3, iclass 6, count 0 2006.201.16:58:46.28#ibcon#about to read 4, iclass 6, count 0 2006.201.16:58:46.28#ibcon#read 4, iclass 6, count 0 2006.201.16:58:46.28#ibcon#about to read 5, iclass 6, count 0 2006.201.16:58:46.28#ibcon#read 5, iclass 6, count 0 2006.201.16:58:46.28#ibcon#about to read 6, iclass 6, count 0 2006.201.16:58:46.28#ibcon#read 6, iclass 6, count 0 2006.201.16:58:46.28#ibcon#end of sib2, iclass 6, count 0 2006.201.16:58:46.28#ibcon#*after write, iclass 6, count 0 2006.201.16:58:46.28#ibcon#*before return 0, iclass 6, count 0 2006.201.16:58:46.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:46.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.16:58:46.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.16:58:46.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.16:58:46.28$vck44/vabw=wide 2006.201.16:58:46.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.16:58:46.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.16:58:46.28#ibcon#ireg 8 cls_cnt 0 2006.201.16:58:46.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:46.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:46.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:46.28#ibcon#enter wrdev, iclass 10, count 0 2006.201.16:58:46.28#ibcon#first serial, iclass 10, count 0 2006.201.16:58:46.28#ibcon#enter sib2, iclass 10, count 0 2006.201.16:58:46.28#ibcon#flushed, iclass 10, count 0 2006.201.16:58:46.28#ibcon#about to write, iclass 10, count 0 2006.201.16:58:46.28#ibcon#wrote, iclass 10, count 0 2006.201.16:58:46.28#ibcon#about to read 3, iclass 10, count 0 2006.201.16:58:46.30#ibcon#read 3, iclass 10, count 0 2006.201.16:58:46.30#ibcon#about to read 4, iclass 10, count 0 2006.201.16:58:46.30#ibcon#read 4, iclass 10, count 0 2006.201.16:58:46.30#ibcon#about to read 5, iclass 10, count 0 2006.201.16:58:46.30#ibcon#read 5, iclass 10, count 0 2006.201.16:58:46.30#ibcon#about to read 6, iclass 10, count 0 2006.201.16:58:46.30#ibcon#read 6, iclass 10, count 0 2006.201.16:58:46.30#ibcon#end of sib2, iclass 10, count 0 2006.201.16:58:46.30#ibcon#*mode == 0, iclass 10, count 0 2006.201.16:58:46.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.16:58:46.30#ibcon#[25=BW32\r\n] 2006.201.16:58:46.30#ibcon#*before write, iclass 10, count 0 2006.201.16:58:46.30#ibcon#enter sib2, iclass 10, count 0 2006.201.16:58:46.30#ibcon#flushed, iclass 10, count 0 2006.201.16:58:46.30#ibcon#about to write, iclass 10, count 0 2006.201.16:58:46.30#ibcon#wrote, iclass 10, count 0 2006.201.16:58:46.30#ibcon#about to read 3, iclass 10, count 0 2006.201.16:58:46.33#ibcon#read 3, iclass 10, count 0 2006.201.16:58:46.33#ibcon#about to read 4, iclass 10, count 0 2006.201.16:58:46.33#ibcon#read 4, iclass 10, count 0 2006.201.16:58:46.33#ibcon#about to read 5, iclass 10, count 0 2006.201.16:58:46.33#ibcon#read 5, iclass 10, count 0 2006.201.16:58:46.33#ibcon#about to read 6, iclass 10, count 0 2006.201.16:58:46.33#ibcon#read 6, iclass 10, count 0 2006.201.16:58:46.33#ibcon#end of sib2, iclass 10, count 0 2006.201.16:58:46.33#ibcon#*after write, iclass 10, count 0 2006.201.16:58:46.33#ibcon#*before return 0, iclass 10, count 0 2006.201.16:58:46.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:46.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.16:58:46.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.16:58:46.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.16:58:46.33$vck44/vbbw=wide 2006.201.16:58:46.33#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.16:58:46.33#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.16:58:46.33#ibcon#ireg 8 cls_cnt 0 2006.201.16:58:46.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:58:46.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:58:46.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:58:46.40#ibcon#enter wrdev, iclass 12, count 0 2006.201.16:58:46.40#ibcon#first serial, iclass 12, count 0 2006.201.16:58:46.40#ibcon#enter sib2, iclass 12, count 0 2006.201.16:58:46.40#ibcon#flushed, iclass 12, count 0 2006.201.16:58:46.40#ibcon#about to write, iclass 12, count 0 2006.201.16:58:46.40#ibcon#wrote, iclass 12, count 0 2006.201.16:58:46.40#ibcon#about to read 3, iclass 12, count 0 2006.201.16:58:46.42#ibcon#read 3, iclass 12, count 0 2006.201.16:58:46.42#ibcon#about to read 4, iclass 12, count 0 2006.201.16:58:46.42#ibcon#read 4, iclass 12, count 0 2006.201.16:58:46.42#ibcon#about to read 5, iclass 12, count 0 2006.201.16:58:46.42#ibcon#read 5, iclass 12, count 0 2006.201.16:58:46.42#ibcon#about to read 6, iclass 12, count 0 2006.201.16:58:46.42#ibcon#read 6, iclass 12, count 0 2006.201.16:58:46.42#ibcon#end of sib2, iclass 12, count 0 2006.201.16:58:46.42#ibcon#*mode == 0, iclass 12, count 0 2006.201.16:58:46.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.16:58:46.42#ibcon#[27=BW32\r\n] 2006.201.16:58:46.42#ibcon#*before write, iclass 12, count 0 2006.201.16:58:46.42#ibcon#enter sib2, iclass 12, count 0 2006.201.16:58:46.42#ibcon#flushed, iclass 12, count 0 2006.201.16:58:46.42#ibcon#about to write, iclass 12, count 0 2006.201.16:58:46.42#ibcon#wrote, iclass 12, count 0 2006.201.16:58:46.42#ibcon#about to read 3, iclass 12, count 0 2006.201.16:58:46.45#ibcon#read 3, iclass 12, count 0 2006.201.16:58:46.45#ibcon#about to read 4, iclass 12, count 0 2006.201.16:58:46.45#ibcon#read 4, iclass 12, count 0 2006.201.16:58:46.45#ibcon#about to read 5, iclass 12, count 0 2006.201.16:58:46.45#ibcon#read 5, iclass 12, count 0 2006.201.16:58:46.45#ibcon#about to read 6, iclass 12, count 0 2006.201.16:58:46.45#ibcon#read 6, iclass 12, count 0 2006.201.16:58:46.45#ibcon#end of sib2, iclass 12, count 0 2006.201.16:58:46.45#ibcon#*after write, iclass 12, count 0 2006.201.16:58:46.45#ibcon#*before return 0, iclass 12, count 0 2006.201.16:58:46.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:58:46.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.16:58:46.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.16:58:46.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.16:58:46.45$setupk4/ifdk4 2006.201.16:58:46.45$ifdk4/lo= 2006.201.16:58:46.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.16:58:46.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.16:58:46.45$ifdk4/patch= 2006.201.16:58:46.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.16:58:46.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.16:58:46.45$setupk4/!*+20s 2006.201.16:58:55.44#abcon#<5=/03 0.4 1.2 20.801001002.6\r\n> 2006.201.16:58:55.46#abcon#{5=INTERFACE CLEAR} 2006.201.16:58:55.52#abcon#[5=S1D000X0/0*\r\n] 2006.201.16:59:00.92$setupk4/"tpicd 2006.201.16:59:00.92$setupk4/echo=off 2006.201.16:59:00.92$setupk4/xlog=off 2006.201.16:59:00.92:!2006.201.16:59:30 2006.201.16:59:01.14#trakl#Source acquired 2006.201.16:59:03.14#flagr#flagr/antenna,acquired 2006.201.16:59:30.00:preob 2006.201.16:59:31.14/onsource/TRACKING 2006.201.16:59:31.14:!2006.201.16:59:40 2006.201.16:59:40.00:"tape 2006.201.16:59:40.00:"st=record 2006.201.16:59:40.00:data_valid=on 2006.201.16:59:40.00:midob 2006.201.16:59:40.14/onsource/TRACKING 2006.201.16:59:40.14/wx/20.79,1002.6,100 2006.201.16:59:40.34/cable/+6.4771E-03 2006.201.16:59:41.43/va/01,08,usb,yes,43,46 2006.201.16:59:41.43/va/02,07,usb,yes,46,48 2006.201.16:59:41.43/va/03,08,usb,yes,42,44 2006.201.16:59:41.43/va/04,07,usb,yes,48,50 2006.201.16:59:41.43/va/05,04,usb,yes,43,44 2006.201.16:59:41.43/va/06,05,usb,yes,43,43 2006.201.16:59:41.43/va/07,05,usb,yes,42,43 2006.201.16:59:41.43/va/08,04,usb,yes,42,49 2006.201.16:59:41.66/valo/01,524.99,yes,locked 2006.201.16:59:41.66/valo/02,534.99,yes,locked 2006.201.16:59:41.66/valo/03,564.99,yes,locked 2006.201.16:59:41.66/valo/04,624.99,yes,locked 2006.201.16:59:41.66/valo/05,734.99,yes,locked 2006.201.16:59:41.66/valo/06,814.99,yes,locked 2006.201.16:59:41.66/valo/07,864.99,yes,locked 2006.201.16:59:41.66/valo/08,884.99,yes,locked 2006.201.16:59:42.75/vb/01,04,usb,yes,33,38 2006.201.16:59:42.75/vb/02,05,usb,yes,31,37 2006.201.16:59:42.75/vb/03,04,usb,yes,33,37 2006.201.16:59:42.75/vb/04,05,usb,yes,32,31 2006.201.16:59:42.75/vb/05,04,usb,yes,29,32 2006.201.16:59:42.75/vb/06,04,usb,yes,35,30 2006.201.16:59:42.75/vb/07,04,usb,yes,34,34 2006.201.16:59:42.75/vb/08,04,usb,yes,31,35 2006.201.16:59:42.98/vblo/01,629.99,yes,locked 2006.201.16:59:42.98/vblo/02,634.99,yes,locked 2006.201.16:59:42.98/vblo/03,649.99,yes,locked 2006.201.16:59:42.98/vblo/04,679.99,yes,locked 2006.201.16:59:42.98/vblo/05,709.99,yes,locked 2006.201.16:59:42.98/vblo/06,719.99,yes,locked 2006.201.16:59:42.98/vblo/07,734.99,yes,locked 2006.201.16:59:42.98/vblo/08,744.99,yes,locked 2006.201.16:59:43.13/vabw/8 2006.201.16:59:43.28/vbbw/8 2006.201.16:59:43.48/xfe/off,on,15.2 2006.201.16:59:43.86/ifatt/23,28,28,28 2006.201.16:59:44.07/fmout-gps/S +4.55E-07 2006.201.16:59:44.14:!2006.201.17:02:00 2006.201.17:02:00.00:data_valid=off 2006.201.17:02:00.00:"et 2006.201.17:02:00.00:!+3s 2006.201.17:02:03.02:"tape 2006.201.17:02:03.02:postob 2006.201.17:02:03.21/cable/+6.4779E-03 2006.201.17:02:03.21/wx/20.79,1002.6,100 2006.201.17:02:03.28/fmout-gps/S +4.50E-07 2006.201.17:02:03.28:scan_name=201-1703,jd0607,120 2006.201.17:02:03.28:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.17:02:04.13#flagr#flagr/antenna,new-source 2006.201.17:02:04.13:checkk5 2006.201.17:02:04.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.17:02:04.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.17:02:05.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.17:02:05.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.17:02:05.99/chk_obsdata//k5ts1/T2011659??a.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.17:02:06.37/chk_obsdata//k5ts2/T2011659??b.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.17:02:06.74/chk_obsdata//k5ts3/T2011659??c.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.17:02:07.11/chk_obsdata//k5ts4/T2011659??d.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.17:02:07.79/k5log//k5ts1_log_newline 2006.201.17:02:08.47/k5log//k5ts2_log_newline 2006.201.17:02:09.16/k5log//k5ts3_log_newline 2006.201.17:02:09.85/k5log//k5ts4_log_newline 2006.201.17:02:09.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.17:02:09.88:setupk4=1 2006.201.17:02:09.88$setupk4/echo=on 2006.201.17:02:09.88$setupk4/pcalon 2006.201.17:02:09.88$pcalon/"no phase cal control is implemented here 2006.201.17:02:09.88$setupk4/"tpicd=stop 2006.201.17:02:09.88$setupk4/"rec=synch_on 2006.201.17:02:09.88$setupk4/"rec_mode=128 2006.201.17:02:09.88$setupk4/!* 2006.201.17:02:09.88$setupk4/recpk4 2006.201.17:02:09.88$recpk4/recpatch= 2006.201.17:02:09.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.17:02:09.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.17:02:09.88$setupk4/vck44 2006.201.17:02:09.88$vck44/valo=1,524.99 2006.201.17:02:09.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.17:02:09.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.17:02:09.88#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:09.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:09.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:09.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:09.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:02:09.88#ibcon#first serial, iclass 25, count 0 2006.201.17:02:09.88#ibcon#enter sib2, iclass 25, count 0 2006.201.17:02:09.88#ibcon#flushed, iclass 25, count 0 2006.201.17:02:09.88#ibcon#about to write, iclass 25, count 0 2006.201.17:02:09.88#ibcon#wrote, iclass 25, count 0 2006.201.17:02:09.88#ibcon#about to read 3, iclass 25, count 0 2006.201.17:02:09.92#ibcon#read 3, iclass 25, count 0 2006.201.17:02:09.92#ibcon#about to read 4, iclass 25, count 0 2006.201.17:02:09.92#ibcon#read 4, iclass 25, count 0 2006.201.17:02:09.92#ibcon#about to read 5, iclass 25, count 0 2006.201.17:02:09.92#ibcon#read 5, iclass 25, count 0 2006.201.17:02:09.92#ibcon#about to read 6, iclass 25, count 0 2006.201.17:02:09.92#ibcon#read 6, iclass 25, count 0 2006.201.17:02:09.92#ibcon#end of sib2, iclass 25, count 0 2006.201.17:02:09.92#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:02:09.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:02:09.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.17:02:09.92#ibcon#*before write, iclass 25, count 0 2006.201.17:02:09.92#ibcon#enter sib2, iclass 25, count 0 2006.201.17:02:09.92#ibcon#flushed, iclass 25, count 0 2006.201.17:02:09.92#ibcon#about to write, iclass 25, count 0 2006.201.17:02:09.92#ibcon#wrote, iclass 25, count 0 2006.201.17:02:09.92#ibcon#about to read 3, iclass 25, count 0 2006.201.17:02:09.97#ibcon#read 3, iclass 25, count 0 2006.201.17:02:09.97#ibcon#about to read 4, iclass 25, count 0 2006.201.17:02:09.97#ibcon#read 4, iclass 25, count 0 2006.201.17:02:09.97#ibcon#about to read 5, iclass 25, count 0 2006.201.17:02:09.97#ibcon#read 5, iclass 25, count 0 2006.201.17:02:09.97#ibcon#about to read 6, iclass 25, count 0 2006.201.17:02:09.97#ibcon#read 6, iclass 25, count 0 2006.201.17:02:09.97#ibcon#end of sib2, iclass 25, count 0 2006.201.17:02:09.97#ibcon#*after write, iclass 25, count 0 2006.201.17:02:09.97#ibcon#*before return 0, iclass 25, count 0 2006.201.17:02:09.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:09.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:09.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:02:09.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:02:09.97$vck44/va=1,8 2006.201.17:02:09.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.17:02:09.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.17:02:09.97#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:09.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:09.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:09.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:09.97#ibcon#enter wrdev, iclass 27, count 2 2006.201.17:02:09.97#ibcon#first serial, iclass 27, count 2 2006.201.17:02:09.97#ibcon#enter sib2, iclass 27, count 2 2006.201.17:02:09.97#ibcon#flushed, iclass 27, count 2 2006.201.17:02:09.97#ibcon#about to write, iclass 27, count 2 2006.201.17:02:09.97#ibcon#wrote, iclass 27, count 2 2006.201.17:02:09.97#ibcon#about to read 3, iclass 27, count 2 2006.201.17:02:09.99#ibcon#read 3, iclass 27, count 2 2006.201.17:02:09.99#ibcon#about to read 4, iclass 27, count 2 2006.201.17:02:09.99#ibcon#read 4, iclass 27, count 2 2006.201.17:02:09.99#ibcon#about to read 5, iclass 27, count 2 2006.201.17:02:09.99#ibcon#read 5, iclass 27, count 2 2006.201.17:02:09.99#ibcon#about to read 6, iclass 27, count 2 2006.201.17:02:09.99#ibcon#read 6, iclass 27, count 2 2006.201.17:02:09.99#ibcon#end of sib2, iclass 27, count 2 2006.201.17:02:09.99#ibcon#*mode == 0, iclass 27, count 2 2006.201.17:02:09.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.17:02:09.99#ibcon#[25=AT01-08\r\n] 2006.201.17:02:09.99#ibcon#*before write, iclass 27, count 2 2006.201.17:02:09.99#ibcon#enter sib2, iclass 27, count 2 2006.201.17:02:09.99#ibcon#flushed, iclass 27, count 2 2006.201.17:02:09.99#ibcon#about to write, iclass 27, count 2 2006.201.17:02:09.99#ibcon#wrote, iclass 27, count 2 2006.201.17:02:09.99#ibcon#about to read 3, iclass 27, count 2 2006.201.17:02:10.03#ibcon#read 3, iclass 27, count 2 2006.201.17:02:10.03#ibcon#about to read 4, iclass 27, count 2 2006.201.17:02:10.03#ibcon#read 4, iclass 27, count 2 2006.201.17:02:10.03#ibcon#about to read 5, iclass 27, count 2 2006.201.17:02:10.03#ibcon#read 5, iclass 27, count 2 2006.201.17:02:10.03#ibcon#about to read 6, iclass 27, count 2 2006.201.17:02:10.03#ibcon#read 6, iclass 27, count 2 2006.201.17:02:10.03#ibcon#end of sib2, iclass 27, count 2 2006.201.17:02:10.03#ibcon#*after write, iclass 27, count 2 2006.201.17:02:10.03#ibcon#*before return 0, iclass 27, count 2 2006.201.17:02:10.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:10.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:10.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.17:02:10.03#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:10.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:10.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:10.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:10.15#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:02:10.15#ibcon#first serial, iclass 27, count 0 2006.201.17:02:10.15#ibcon#enter sib2, iclass 27, count 0 2006.201.17:02:10.15#ibcon#flushed, iclass 27, count 0 2006.201.17:02:10.15#ibcon#about to write, iclass 27, count 0 2006.201.17:02:10.15#ibcon#wrote, iclass 27, count 0 2006.201.17:02:10.15#ibcon#about to read 3, iclass 27, count 0 2006.201.17:02:10.17#ibcon#read 3, iclass 27, count 0 2006.201.17:02:10.17#ibcon#about to read 4, iclass 27, count 0 2006.201.17:02:10.17#ibcon#read 4, iclass 27, count 0 2006.201.17:02:10.17#ibcon#about to read 5, iclass 27, count 0 2006.201.17:02:10.17#ibcon#read 5, iclass 27, count 0 2006.201.17:02:10.17#ibcon#about to read 6, iclass 27, count 0 2006.201.17:02:10.17#ibcon#read 6, iclass 27, count 0 2006.201.17:02:10.17#ibcon#end of sib2, iclass 27, count 0 2006.201.17:02:10.17#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:02:10.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:02:10.17#ibcon#[25=USB\r\n] 2006.201.17:02:10.17#ibcon#*before write, iclass 27, count 0 2006.201.17:02:10.17#ibcon#enter sib2, iclass 27, count 0 2006.201.17:02:10.17#ibcon#flushed, iclass 27, count 0 2006.201.17:02:10.17#ibcon#about to write, iclass 27, count 0 2006.201.17:02:10.17#ibcon#wrote, iclass 27, count 0 2006.201.17:02:10.17#ibcon#about to read 3, iclass 27, count 0 2006.201.17:02:10.20#ibcon#read 3, iclass 27, count 0 2006.201.17:02:10.20#ibcon#about to read 4, iclass 27, count 0 2006.201.17:02:10.20#ibcon#read 4, iclass 27, count 0 2006.201.17:02:10.20#ibcon#about to read 5, iclass 27, count 0 2006.201.17:02:10.20#ibcon#read 5, iclass 27, count 0 2006.201.17:02:10.20#ibcon#about to read 6, iclass 27, count 0 2006.201.17:02:10.20#ibcon#read 6, iclass 27, count 0 2006.201.17:02:10.20#ibcon#end of sib2, iclass 27, count 0 2006.201.17:02:10.20#ibcon#*after write, iclass 27, count 0 2006.201.17:02:10.20#ibcon#*before return 0, iclass 27, count 0 2006.201.17:02:10.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:10.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:10.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:02:10.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:02:10.20$vck44/valo=2,534.99 2006.201.17:02:10.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.17:02:10.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.17:02:10.20#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:10.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:10.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:10.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:10.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:02:10.20#ibcon#first serial, iclass 29, count 0 2006.201.17:02:10.20#ibcon#enter sib2, iclass 29, count 0 2006.201.17:02:10.20#ibcon#flushed, iclass 29, count 0 2006.201.17:02:10.20#ibcon#about to write, iclass 29, count 0 2006.201.17:02:10.20#ibcon#wrote, iclass 29, count 0 2006.201.17:02:10.20#ibcon#about to read 3, iclass 29, count 0 2006.201.17:02:10.22#ibcon#read 3, iclass 29, count 0 2006.201.17:02:10.22#ibcon#about to read 4, iclass 29, count 0 2006.201.17:02:10.22#ibcon#read 4, iclass 29, count 0 2006.201.17:02:10.22#ibcon#about to read 5, iclass 29, count 0 2006.201.17:02:10.22#ibcon#read 5, iclass 29, count 0 2006.201.17:02:10.22#ibcon#about to read 6, iclass 29, count 0 2006.201.17:02:10.22#ibcon#read 6, iclass 29, count 0 2006.201.17:02:10.22#ibcon#end of sib2, iclass 29, count 0 2006.201.17:02:10.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:02:10.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:02:10.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.17:02:10.22#ibcon#*before write, iclass 29, count 0 2006.201.17:02:10.22#ibcon#enter sib2, iclass 29, count 0 2006.201.17:02:10.22#ibcon#flushed, iclass 29, count 0 2006.201.17:02:10.22#ibcon#about to write, iclass 29, count 0 2006.201.17:02:10.22#ibcon#wrote, iclass 29, count 0 2006.201.17:02:10.22#ibcon#about to read 3, iclass 29, count 0 2006.201.17:02:10.26#ibcon#read 3, iclass 29, count 0 2006.201.17:02:10.26#ibcon#about to read 4, iclass 29, count 0 2006.201.17:02:10.26#ibcon#read 4, iclass 29, count 0 2006.201.17:02:10.26#ibcon#about to read 5, iclass 29, count 0 2006.201.17:02:10.26#ibcon#read 5, iclass 29, count 0 2006.201.17:02:10.26#ibcon#about to read 6, iclass 29, count 0 2006.201.17:02:10.26#ibcon#read 6, iclass 29, count 0 2006.201.17:02:10.26#ibcon#end of sib2, iclass 29, count 0 2006.201.17:02:10.26#ibcon#*after write, iclass 29, count 0 2006.201.17:02:10.26#ibcon#*before return 0, iclass 29, count 0 2006.201.17:02:10.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:10.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:10.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:02:10.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:02:10.26$vck44/va=2,7 2006.201.17:02:10.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.17:02:10.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.17:02:10.26#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:10.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:10.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:10.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:10.32#ibcon#enter wrdev, iclass 31, count 2 2006.201.17:02:10.32#ibcon#first serial, iclass 31, count 2 2006.201.17:02:10.32#ibcon#enter sib2, iclass 31, count 2 2006.201.17:02:10.32#ibcon#flushed, iclass 31, count 2 2006.201.17:02:10.32#ibcon#about to write, iclass 31, count 2 2006.201.17:02:10.32#ibcon#wrote, iclass 31, count 2 2006.201.17:02:10.32#ibcon#about to read 3, iclass 31, count 2 2006.201.17:02:10.34#ibcon#read 3, iclass 31, count 2 2006.201.17:02:10.34#ibcon#about to read 4, iclass 31, count 2 2006.201.17:02:10.34#ibcon#read 4, iclass 31, count 2 2006.201.17:02:10.34#ibcon#about to read 5, iclass 31, count 2 2006.201.17:02:10.34#ibcon#read 5, iclass 31, count 2 2006.201.17:02:10.34#ibcon#about to read 6, iclass 31, count 2 2006.201.17:02:10.34#ibcon#read 6, iclass 31, count 2 2006.201.17:02:10.34#ibcon#end of sib2, iclass 31, count 2 2006.201.17:02:10.34#ibcon#*mode == 0, iclass 31, count 2 2006.201.17:02:10.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.17:02:10.34#ibcon#[25=AT02-07\r\n] 2006.201.17:02:10.34#ibcon#*before write, iclass 31, count 2 2006.201.17:02:10.34#ibcon#enter sib2, iclass 31, count 2 2006.201.17:02:10.34#ibcon#flushed, iclass 31, count 2 2006.201.17:02:10.34#ibcon#about to write, iclass 31, count 2 2006.201.17:02:10.34#ibcon#wrote, iclass 31, count 2 2006.201.17:02:10.34#ibcon#about to read 3, iclass 31, count 2 2006.201.17:02:10.37#ibcon#read 3, iclass 31, count 2 2006.201.17:02:10.37#ibcon#about to read 4, iclass 31, count 2 2006.201.17:02:10.37#ibcon#read 4, iclass 31, count 2 2006.201.17:02:10.37#ibcon#about to read 5, iclass 31, count 2 2006.201.17:02:10.37#ibcon#read 5, iclass 31, count 2 2006.201.17:02:10.37#ibcon#about to read 6, iclass 31, count 2 2006.201.17:02:10.37#ibcon#read 6, iclass 31, count 2 2006.201.17:02:10.37#ibcon#end of sib2, iclass 31, count 2 2006.201.17:02:10.37#ibcon#*after write, iclass 31, count 2 2006.201.17:02:10.37#ibcon#*before return 0, iclass 31, count 2 2006.201.17:02:10.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:10.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:10.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.17:02:10.37#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:10.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:10.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:10.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:10.49#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:02:10.49#ibcon#first serial, iclass 31, count 0 2006.201.17:02:10.49#ibcon#enter sib2, iclass 31, count 0 2006.201.17:02:10.49#ibcon#flushed, iclass 31, count 0 2006.201.17:02:10.49#ibcon#about to write, iclass 31, count 0 2006.201.17:02:10.49#ibcon#wrote, iclass 31, count 0 2006.201.17:02:10.49#ibcon#about to read 3, iclass 31, count 0 2006.201.17:02:10.51#ibcon#read 3, iclass 31, count 0 2006.201.17:02:10.51#ibcon#about to read 4, iclass 31, count 0 2006.201.17:02:10.51#ibcon#read 4, iclass 31, count 0 2006.201.17:02:10.51#ibcon#about to read 5, iclass 31, count 0 2006.201.17:02:10.51#ibcon#read 5, iclass 31, count 0 2006.201.17:02:10.51#ibcon#about to read 6, iclass 31, count 0 2006.201.17:02:10.51#ibcon#read 6, iclass 31, count 0 2006.201.17:02:10.51#ibcon#end of sib2, iclass 31, count 0 2006.201.17:02:10.51#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:02:10.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:02:10.51#ibcon#[25=USB\r\n] 2006.201.17:02:10.51#ibcon#*before write, iclass 31, count 0 2006.201.17:02:10.51#ibcon#enter sib2, iclass 31, count 0 2006.201.17:02:10.51#ibcon#flushed, iclass 31, count 0 2006.201.17:02:10.51#ibcon#about to write, iclass 31, count 0 2006.201.17:02:10.51#ibcon#wrote, iclass 31, count 0 2006.201.17:02:10.51#ibcon#about to read 3, iclass 31, count 0 2006.201.17:02:10.54#ibcon#read 3, iclass 31, count 0 2006.201.17:02:10.54#ibcon#about to read 4, iclass 31, count 0 2006.201.17:02:10.54#ibcon#read 4, iclass 31, count 0 2006.201.17:02:10.54#ibcon#about to read 5, iclass 31, count 0 2006.201.17:02:10.54#ibcon#read 5, iclass 31, count 0 2006.201.17:02:10.54#ibcon#about to read 6, iclass 31, count 0 2006.201.17:02:10.54#ibcon#read 6, iclass 31, count 0 2006.201.17:02:10.54#ibcon#end of sib2, iclass 31, count 0 2006.201.17:02:10.54#ibcon#*after write, iclass 31, count 0 2006.201.17:02:10.54#ibcon#*before return 0, iclass 31, count 0 2006.201.17:02:10.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:10.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:10.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:02:10.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:02:10.54$vck44/valo=3,564.99 2006.201.17:02:10.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.17:02:10.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.17:02:10.54#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:10.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:10.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:10.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:10.54#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:02:10.54#ibcon#first serial, iclass 33, count 0 2006.201.17:02:10.54#ibcon#enter sib2, iclass 33, count 0 2006.201.17:02:10.54#ibcon#flushed, iclass 33, count 0 2006.201.17:02:10.54#ibcon#about to write, iclass 33, count 0 2006.201.17:02:10.54#ibcon#wrote, iclass 33, count 0 2006.201.17:02:10.54#ibcon#about to read 3, iclass 33, count 0 2006.201.17:02:10.56#ibcon#read 3, iclass 33, count 0 2006.201.17:02:10.56#ibcon#about to read 4, iclass 33, count 0 2006.201.17:02:10.56#ibcon#read 4, iclass 33, count 0 2006.201.17:02:10.56#ibcon#about to read 5, iclass 33, count 0 2006.201.17:02:10.56#ibcon#read 5, iclass 33, count 0 2006.201.17:02:10.56#ibcon#about to read 6, iclass 33, count 0 2006.201.17:02:10.56#ibcon#read 6, iclass 33, count 0 2006.201.17:02:10.56#ibcon#end of sib2, iclass 33, count 0 2006.201.17:02:10.56#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:02:10.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:02:10.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.17:02:10.56#ibcon#*before write, iclass 33, count 0 2006.201.17:02:10.56#ibcon#enter sib2, iclass 33, count 0 2006.201.17:02:10.56#ibcon#flushed, iclass 33, count 0 2006.201.17:02:10.56#ibcon#about to write, iclass 33, count 0 2006.201.17:02:10.56#ibcon#wrote, iclass 33, count 0 2006.201.17:02:10.56#ibcon#about to read 3, iclass 33, count 0 2006.201.17:02:10.60#ibcon#read 3, iclass 33, count 0 2006.201.17:02:10.60#ibcon#about to read 4, iclass 33, count 0 2006.201.17:02:10.60#ibcon#read 4, iclass 33, count 0 2006.201.17:02:10.60#ibcon#about to read 5, iclass 33, count 0 2006.201.17:02:10.60#ibcon#read 5, iclass 33, count 0 2006.201.17:02:10.60#ibcon#about to read 6, iclass 33, count 0 2006.201.17:02:10.60#ibcon#read 6, iclass 33, count 0 2006.201.17:02:10.60#ibcon#end of sib2, iclass 33, count 0 2006.201.17:02:10.60#ibcon#*after write, iclass 33, count 0 2006.201.17:02:10.60#ibcon#*before return 0, iclass 33, count 0 2006.201.17:02:10.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:10.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:10.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:02:10.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:02:10.60$vck44/va=3,8 2006.201.17:02:10.60#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.17:02:10.60#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.17:02:10.60#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:10.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:10.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:10.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:10.66#ibcon#enter wrdev, iclass 35, count 2 2006.201.17:02:10.66#ibcon#first serial, iclass 35, count 2 2006.201.17:02:10.66#ibcon#enter sib2, iclass 35, count 2 2006.201.17:02:10.66#ibcon#flushed, iclass 35, count 2 2006.201.17:02:10.66#ibcon#about to write, iclass 35, count 2 2006.201.17:02:10.66#ibcon#wrote, iclass 35, count 2 2006.201.17:02:10.66#ibcon#about to read 3, iclass 35, count 2 2006.201.17:02:10.68#ibcon#read 3, iclass 35, count 2 2006.201.17:02:10.68#ibcon#about to read 4, iclass 35, count 2 2006.201.17:02:10.68#ibcon#read 4, iclass 35, count 2 2006.201.17:02:10.68#ibcon#about to read 5, iclass 35, count 2 2006.201.17:02:10.68#ibcon#read 5, iclass 35, count 2 2006.201.17:02:10.68#ibcon#about to read 6, iclass 35, count 2 2006.201.17:02:10.68#ibcon#read 6, iclass 35, count 2 2006.201.17:02:10.68#ibcon#end of sib2, iclass 35, count 2 2006.201.17:02:10.68#ibcon#*mode == 0, iclass 35, count 2 2006.201.17:02:10.68#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.17:02:10.68#ibcon#[25=AT03-08\r\n] 2006.201.17:02:10.68#ibcon#*before write, iclass 35, count 2 2006.201.17:02:10.68#ibcon#enter sib2, iclass 35, count 2 2006.201.17:02:10.68#ibcon#flushed, iclass 35, count 2 2006.201.17:02:10.68#ibcon#about to write, iclass 35, count 2 2006.201.17:02:10.68#ibcon#wrote, iclass 35, count 2 2006.201.17:02:10.68#ibcon#about to read 3, iclass 35, count 2 2006.201.17:02:10.71#ibcon#read 3, iclass 35, count 2 2006.201.17:02:10.71#ibcon#about to read 4, iclass 35, count 2 2006.201.17:02:10.71#ibcon#read 4, iclass 35, count 2 2006.201.17:02:10.71#ibcon#about to read 5, iclass 35, count 2 2006.201.17:02:10.71#ibcon#read 5, iclass 35, count 2 2006.201.17:02:10.71#ibcon#about to read 6, iclass 35, count 2 2006.201.17:02:10.71#ibcon#read 6, iclass 35, count 2 2006.201.17:02:10.71#ibcon#end of sib2, iclass 35, count 2 2006.201.17:02:10.71#ibcon#*after write, iclass 35, count 2 2006.201.17:02:10.71#ibcon#*before return 0, iclass 35, count 2 2006.201.17:02:10.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:10.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:10.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.17:02:10.71#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:10.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:10.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:10.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:10.83#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:02:10.83#ibcon#first serial, iclass 35, count 0 2006.201.17:02:10.83#ibcon#enter sib2, iclass 35, count 0 2006.201.17:02:10.83#ibcon#flushed, iclass 35, count 0 2006.201.17:02:10.83#ibcon#about to write, iclass 35, count 0 2006.201.17:02:10.83#ibcon#wrote, iclass 35, count 0 2006.201.17:02:10.83#ibcon#about to read 3, iclass 35, count 0 2006.201.17:02:10.85#ibcon#read 3, iclass 35, count 0 2006.201.17:02:10.85#ibcon#about to read 4, iclass 35, count 0 2006.201.17:02:10.85#ibcon#read 4, iclass 35, count 0 2006.201.17:02:10.85#ibcon#about to read 5, iclass 35, count 0 2006.201.17:02:10.85#ibcon#read 5, iclass 35, count 0 2006.201.17:02:10.85#ibcon#about to read 6, iclass 35, count 0 2006.201.17:02:10.85#ibcon#read 6, iclass 35, count 0 2006.201.17:02:10.85#ibcon#end of sib2, iclass 35, count 0 2006.201.17:02:10.85#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:02:10.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:02:10.85#ibcon#[25=USB\r\n] 2006.201.17:02:10.85#ibcon#*before write, iclass 35, count 0 2006.201.17:02:10.85#ibcon#enter sib2, iclass 35, count 0 2006.201.17:02:10.85#ibcon#flushed, iclass 35, count 0 2006.201.17:02:10.85#ibcon#about to write, iclass 35, count 0 2006.201.17:02:10.85#ibcon#wrote, iclass 35, count 0 2006.201.17:02:10.85#ibcon#about to read 3, iclass 35, count 0 2006.201.17:02:10.88#ibcon#read 3, iclass 35, count 0 2006.201.17:02:10.88#ibcon#about to read 4, iclass 35, count 0 2006.201.17:02:10.88#ibcon#read 4, iclass 35, count 0 2006.201.17:02:10.88#ibcon#about to read 5, iclass 35, count 0 2006.201.17:02:10.88#ibcon#read 5, iclass 35, count 0 2006.201.17:02:10.88#ibcon#about to read 6, iclass 35, count 0 2006.201.17:02:10.88#ibcon#read 6, iclass 35, count 0 2006.201.17:02:10.88#ibcon#end of sib2, iclass 35, count 0 2006.201.17:02:10.88#ibcon#*after write, iclass 35, count 0 2006.201.17:02:10.88#ibcon#*before return 0, iclass 35, count 0 2006.201.17:02:10.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:10.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:10.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:02:10.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:02:10.88$vck44/valo=4,624.99 2006.201.17:02:10.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.17:02:10.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.17:02:10.88#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:10.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:10.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:10.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:10.88#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:02:10.88#ibcon#first serial, iclass 37, count 0 2006.201.17:02:10.88#ibcon#enter sib2, iclass 37, count 0 2006.201.17:02:10.88#ibcon#flushed, iclass 37, count 0 2006.201.17:02:10.88#ibcon#about to write, iclass 37, count 0 2006.201.17:02:10.88#ibcon#wrote, iclass 37, count 0 2006.201.17:02:10.88#ibcon#about to read 3, iclass 37, count 0 2006.201.17:02:10.90#ibcon#read 3, iclass 37, count 0 2006.201.17:02:10.90#ibcon#about to read 4, iclass 37, count 0 2006.201.17:02:10.90#ibcon#read 4, iclass 37, count 0 2006.201.17:02:10.90#ibcon#about to read 5, iclass 37, count 0 2006.201.17:02:10.90#ibcon#read 5, iclass 37, count 0 2006.201.17:02:10.90#ibcon#about to read 6, iclass 37, count 0 2006.201.17:02:10.90#ibcon#read 6, iclass 37, count 0 2006.201.17:02:10.90#ibcon#end of sib2, iclass 37, count 0 2006.201.17:02:10.90#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:02:10.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:02:10.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.17:02:10.90#ibcon#*before write, iclass 37, count 0 2006.201.17:02:10.90#ibcon#enter sib2, iclass 37, count 0 2006.201.17:02:10.90#ibcon#flushed, iclass 37, count 0 2006.201.17:02:10.90#ibcon#about to write, iclass 37, count 0 2006.201.17:02:10.90#ibcon#wrote, iclass 37, count 0 2006.201.17:02:10.90#ibcon#about to read 3, iclass 37, count 0 2006.201.17:02:10.94#ibcon#read 3, iclass 37, count 0 2006.201.17:02:10.94#ibcon#about to read 4, iclass 37, count 0 2006.201.17:02:10.94#ibcon#read 4, iclass 37, count 0 2006.201.17:02:10.94#ibcon#about to read 5, iclass 37, count 0 2006.201.17:02:10.94#ibcon#read 5, iclass 37, count 0 2006.201.17:02:10.94#ibcon#about to read 6, iclass 37, count 0 2006.201.17:02:10.94#ibcon#read 6, iclass 37, count 0 2006.201.17:02:10.94#ibcon#end of sib2, iclass 37, count 0 2006.201.17:02:10.94#ibcon#*after write, iclass 37, count 0 2006.201.17:02:10.94#ibcon#*before return 0, iclass 37, count 0 2006.201.17:02:10.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:10.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:10.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:02:10.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:02:10.94$vck44/va=4,7 2006.201.17:02:10.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.17:02:10.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.17:02:10.94#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:10.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:11.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:11.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:11.00#ibcon#enter wrdev, iclass 39, count 2 2006.201.17:02:11.00#ibcon#first serial, iclass 39, count 2 2006.201.17:02:11.00#ibcon#enter sib2, iclass 39, count 2 2006.201.17:02:11.00#ibcon#flushed, iclass 39, count 2 2006.201.17:02:11.00#ibcon#about to write, iclass 39, count 2 2006.201.17:02:11.00#ibcon#wrote, iclass 39, count 2 2006.201.17:02:11.00#ibcon#about to read 3, iclass 39, count 2 2006.201.17:02:11.02#ibcon#read 3, iclass 39, count 2 2006.201.17:02:11.02#ibcon#about to read 4, iclass 39, count 2 2006.201.17:02:11.02#ibcon#read 4, iclass 39, count 2 2006.201.17:02:11.02#ibcon#about to read 5, iclass 39, count 2 2006.201.17:02:11.02#ibcon#read 5, iclass 39, count 2 2006.201.17:02:11.02#ibcon#about to read 6, iclass 39, count 2 2006.201.17:02:11.02#ibcon#read 6, iclass 39, count 2 2006.201.17:02:11.02#ibcon#end of sib2, iclass 39, count 2 2006.201.17:02:11.02#ibcon#*mode == 0, iclass 39, count 2 2006.201.17:02:11.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.17:02:11.02#ibcon#[25=AT04-07\r\n] 2006.201.17:02:11.02#ibcon#*before write, iclass 39, count 2 2006.201.17:02:11.02#ibcon#enter sib2, iclass 39, count 2 2006.201.17:02:11.02#ibcon#flushed, iclass 39, count 2 2006.201.17:02:11.02#ibcon#about to write, iclass 39, count 2 2006.201.17:02:11.02#ibcon#wrote, iclass 39, count 2 2006.201.17:02:11.02#ibcon#about to read 3, iclass 39, count 2 2006.201.17:02:11.05#ibcon#read 3, iclass 39, count 2 2006.201.17:02:11.05#ibcon#about to read 4, iclass 39, count 2 2006.201.17:02:11.05#ibcon#read 4, iclass 39, count 2 2006.201.17:02:11.05#ibcon#about to read 5, iclass 39, count 2 2006.201.17:02:11.05#ibcon#read 5, iclass 39, count 2 2006.201.17:02:11.05#ibcon#about to read 6, iclass 39, count 2 2006.201.17:02:11.05#ibcon#read 6, iclass 39, count 2 2006.201.17:02:11.05#ibcon#end of sib2, iclass 39, count 2 2006.201.17:02:11.05#ibcon#*after write, iclass 39, count 2 2006.201.17:02:11.05#ibcon#*before return 0, iclass 39, count 2 2006.201.17:02:11.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:11.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:11.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.17:02:11.05#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:11.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:11.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:11.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:11.17#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:02:11.17#ibcon#first serial, iclass 39, count 0 2006.201.17:02:11.17#ibcon#enter sib2, iclass 39, count 0 2006.201.17:02:11.17#ibcon#flushed, iclass 39, count 0 2006.201.17:02:11.17#ibcon#about to write, iclass 39, count 0 2006.201.17:02:11.17#ibcon#wrote, iclass 39, count 0 2006.201.17:02:11.17#ibcon#about to read 3, iclass 39, count 0 2006.201.17:02:11.19#ibcon#read 3, iclass 39, count 0 2006.201.17:02:11.19#ibcon#about to read 4, iclass 39, count 0 2006.201.17:02:11.19#ibcon#read 4, iclass 39, count 0 2006.201.17:02:11.19#ibcon#about to read 5, iclass 39, count 0 2006.201.17:02:11.19#ibcon#read 5, iclass 39, count 0 2006.201.17:02:11.19#ibcon#about to read 6, iclass 39, count 0 2006.201.17:02:11.19#ibcon#read 6, iclass 39, count 0 2006.201.17:02:11.19#ibcon#end of sib2, iclass 39, count 0 2006.201.17:02:11.19#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:02:11.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:02:11.19#ibcon#[25=USB\r\n] 2006.201.17:02:11.19#ibcon#*before write, iclass 39, count 0 2006.201.17:02:11.19#ibcon#enter sib2, iclass 39, count 0 2006.201.17:02:11.19#ibcon#flushed, iclass 39, count 0 2006.201.17:02:11.19#ibcon#about to write, iclass 39, count 0 2006.201.17:02:11.19#ibcon#wrote, iclass 39, count 0 2006.201.17:02:11.19#ibcon#about to read 3, iclass 39, count 0 2006.201.17:02:11.22#ibcon#read 3, iclass 39, count 0 2006.201.17:02:11.22#ibcon#about to read 4, iclass 39, count 0 2006.201.17:02:11.22#ibcon#read 4, iclass 39, count 0 2006.201.17:02:11.22#ibcon#about to read 5, iclass 39, count 0 2006.201.17:02:11.22#ibcon#read 5, iclass 39, count 0 2006.201.17:02:11.22#ibcon#about to read 6, iclass 39, count 0 2006.201.17:02:11.22#ibcon#read 6, iclass 39, count 0 2006.201.17:02:11.22#ibcon#end of sib2, iclass 39, count 0 2006.201.17:02:11.22#ibcon#*after write, iclass 39, count 0 2006.201.17:02:11.22#ibcon#*before return 0, iclass 39, count 0 2006.201.17:02:11.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:11.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:11.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:02:11.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:02:11.22$vck44/valo=5,734.99 2006.201.17:02:11.22#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.17:02:11.22#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.17:02:11.22#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:11.22#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:11.22#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:11.22#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:11.22#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:02:11.22#ibcon#first serial, iclass 2, count 0 2006.201.17:02:11.22#ibcon#enter sib2, iclass 2, count 0 2006.201.17:02:11.22#ibcon#flushed, iclass 2, count 0 2006.201.17:02:11.22#ibcon#about to write, iclass 2, count 0 2006.201.17:02:11.22#ibcon#wrote, iclass 2, count 0 2006.201.17:02:11.22#ibcon#about to read 3, iclass 2, count 0 2006.201.17:02:11.24#ibcon#read 3, iclass 2, count 0 2006.201.17:02:11.24#ibcon#about to read 4, iclass 2, count 0 2006.201.17:02:11.24#ibcon#read 4, iclass 2, count 0 2006.201.17:02:11.24#ibcon#about to read 5, iclass 2, count 0 2006.201.17:02:11.24#ibcon#read 5, iclass 2, count 0 2006.201.17:02:11.24#ibcon#about to read 6, iclass 2, count 0 2006.201.17:02:11.24#ibcon#read 6, iclass 2, count 0 2006.201.17:02:11.24#ibcon#end of sib2, iclass 2, count 0 2006.201.17:02:11.24#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:02:11.24#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:02:11.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.17:02:11.24#ibcon#*before write, iclass 2, count 0 2006.201.17:02:11.24#ibcon#enter sib2, iclass 2, count 0 2006.201.17:02:11.24#ibcon#flushed, iclass 2, count 0 2006.201.17:02:11.24#ibcon#about to write, iclass 2, count 0 2006.201.17:02:11.24#ibcon#wrote, iclass 2, count 0 2006.201.17:02:11.24#ibcon#about to read 3, iclass 2, count 0 2006.201.17:02:11.28#ibcon#read 3, iclass 2, count 0 2006.201.17:02:11.28#ibcon#about to read 4, iclass 2, count 0 2006.201.17:02:11.28#ibcon#read 4, iclass 2, count 0 2006.201.17:02:11.28#ibcon#about to read 5, iclass 2, count 0 2006.201.17:02:11.28#ibcon#read 5, iclass 2, count 0 2006.201.17:02:11.28#ibcon#about to read 6, iclass 2, count 0 2006.201.17:02:11.28#ibcon#read 6, iclass 2, count 0 2006.201.17:02:11.28#ibcon#end of sib2, iclass 2, count 0 2006.201.17:02:11.28#ibcon#*after write, iclass 2, count 0 2006.201.17:02:11.28#ibcon#*before return 0, iclass 2, count 0 2006.201.17:02:11.28#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:11.28#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:11.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:02:11.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:02:11.28$vck44/va=5,4 2006.201.17:02:11.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.17:02:11.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.17:02:11.28#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:11.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:11.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:11.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:11.34#ibcon#enter wrdev, iclass 5, count 2 2006.201.17:02:11.34#ibcon#first serial, iclass 5, count 2 2006.201.17:02:11.34#ibcon#enter sib2, iclass 5, count 2 2006.201.17:02:11.34#ibcon#flushed, iclass 5, count 2 2006.201.17:02:11.34#ibcon#about to write, iclass 5, count 2 2006.201.17:02:11.34#ibcon#wrote, iclass 5, count 2 2006.201.17:02:11.34#ibcon#about to read 3, iclass 5, count 2 2006.201.17:02:11.36#ibcon#read 3, iclass 5, count 2 2006.201.17:02:11.36#ibcon#about to read 4, iclass 5, count 2 2006.201.17:02:11.36#ibcon#read 4, iclass 5, count 2 2006.201.17:02:11.36#ibcon#about to read 5, iclass 5, count 2 2006.201.17:02:11.36#ibcon#read 5, iclass 5, count 2 2006.201.17:02:11.36#ibcon#about to read 6, iclass 5, count 2 2006.201.17:02:11.36#ibcon#read 6, iclass 5, count 2 2006.201.17:02:11.36#ibcon#end of sib2, iclass 5, count 2 2006.201.17:02:11.36#ibcon#*mode == 0, iclass 5, count 2 2006.201.17:02:11.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.17:02:11.36#ibcon#[25=AT05-04\r\n] 2006.201.17:02:11.36#ibcon#*before write, iclass 5, count 2 2006.201.17:02:11.36#ibcon#enter sib2, iclass 5, count 2 2006.201.17:02:11.36#ibcon#flushed, iclass 5, count 2 2006.201.17:02:11.36#ibcon#about to write, iclass 5, count 2 2006.201.17:02:11.36#ibcon#wrote, iclass 5, count 2 2006.201.17:02:11.36#ibcon#about to read 3, iclass 5, count 2 2006.201.17:02:11.39#ibcon#read 3, iclass 5, count 2 2006.201.17:02:11.39#ibcon#about to read 4, iclass 5, count 2 2006.201.17:02:11.39#ibcon#read 4, iclass 5, count 2 2006.201.17:02:11.39#ibcon#about to read 5, iclass 5, count 2 2006.201.17:02:11.39#ibcon#read 5, iclass 5, count 2 2006.201.17:02:11.39#ibcon#about to read 6, iclass 5, count 2 2006.201.17:02:11.39#ibcon#read 6, iclass 5, count 2 2006.201.17:02:11.39#ibcon#end of sib2, iclass 5, count 2 2006.201.17:02:11.39#ibcon#*after write, iclass 5, count 2 2006.201.17:02:11.39#ibcon#*before return 0, iclass 5, count 2 2006.201.17:02:11.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:11.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:11.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.17:02:11.39#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:11.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:11.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:11.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:11.51#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:02:11.51#ibcon#first serial, iclass 5, count 0 2006.201.17:02:11.51#ibcon#enter sib2, iclass 5, count 0 2006.201.17:02:11.51#ibcon#flushed, iclass 5, count 0 2006.201.17:02:11.51#ibcon#about to write, iclass 5, count 0 2006.201.17:02:11.51#ibcon#wrote, iclass 5, count 0 2006.201.17:02:11.51#ibcon#about to read 3, iclass 5, count 0 2006.201.17:02:11.53#ibcon#read 3, iclass 5, count 0 2006.201.17:02:11.53#ibcon#about to read 4, iclass 5, count 0 2006.201.17:02:11.53#ibcon#read 4, iclass 5, count 0 2006.201.17:02:11.53#ibcon#about to read 5, iclass 5, count 0 2006.201.17:02:11.53#ibcon#read 5, iclass 5, count 0 2006.201.17:02:11.53#ibcon#about to read 6, iclass 5, count 0 2006.201.17:02:11.53#ibcon#read 6, iclass 5, count 0 2006.201.17:02:11.53#ibcon#end of sib2, iclass 5, count 0 2006.201.17:02:11.53#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:02:11.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:02:11.53#ibcon#[25=USB\r\n] 2006.201.17:02:11.53#ibcon#*before write, iclass 5, count 0 2006.201.17:02:11.53#ibcon#enter sib2, iclass 5, count 0 2006.201.17:02:11.53#ibcon#flushed, iclass 5, count 0 2006.201.17:02:11.53#ibcon#about to write, iclass 5, count 0 2006.201.17:02:11.53#ibcon#wrote, iclass 5, count 0 2006.201.17:02:11.53#ibcon#about to read 3, iclass 5, count 0 2006.201.17:02:11.56#ibcon#read 3, iclass 5, count 0 2006.201.17:02:11.56#ibcon#about to read 4, iclass 5, count 0 2006.201.17:02:11.56#ibcon#read 4, iclass 5, count 0 2006.201.17:02:11.56#ibcon#about to read 5, iclass 5, count 0 2006.201.17:02:11.56#ibcon#read 5, iclass 5, count 0 2006.201.17:02:11.56#ibcon#about to read 6, iclass 5, count 0 2006.201.17:02:11.56#ibcon#read 6, iclass 5, count 0 2006.201.17:02:11.56#ibcon#end of sib2, iclass 5, count 0 2006.201.17:02:11.56#ibcon#*after write, iclass 5, count 0 2006.201.17:02:11.56#ibcon#*before return 0, iclass 5, count 0 2006.201.17:02:11.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:11.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:11.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:02:11.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:02:11.56$vck44/valo=6,814.99 2006.201.17:02:11.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.17:02:11.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.17:02:11.56#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:11.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:11.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:11.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:11.56#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:02:11.56#ibcon#first serial, iclass 7, count 0 2006.201.17:02:11.56#ibcon#enter sib2, iclass 7, count 0 2006.201.17:02:11.56#ibcon#flushed, iclass 7, count 0 2006.201.17:02:11.56#ibcon#about to write, iclass 7, count 0 2006.201.17:02:11.56#ibcon#wrote, iclass 7, count 0 2006.201.17:02:11.56#ibcon#about to read 3, iclass 7, count 0 2006.201.17:02:11.58#ibcon#read 3, iclass 7, count 0 2006.201.17:02:11.58#ibcon#about to read 4, iclass 7, count 0 2006.201.17:02:11.58#ibcon#read 4, iclass 7, count 0 2006.201.17:02:11.58#ibcon#about to read 5, iclass 7, count 0 2006.201.17:02:11.58#ibcon#read 5, iclass 7, count 0 2006.201.17:02:11.58#ibcon#about to read 6, iclass 7, count 0 2006.201.17:02:11.58#ibcon#read 6, iclass 7, count 0 2006.201.17:02:11.58#ibcon#end of sib2, iclass 7, count 0 2006.201.17:02:11.58#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:02:11.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:02:11.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.17:02:11.58#ibcon#*before write, iclass 7, count 0 2006.201.17:02:11.58#ibcon#enter sib2, iclass 7, count 0 2006.201.17:02:11.58#ibcon#flushed, iclass 7, count 0 2006.201.17:02:11.58#ibcon#about to write, iclass 7, count 0 2006.201.17:02:11.58#ibcon#wrote, iclass 7, count 0 2006.201.17:02:11.58#ibcon#about to read 3, iclass 7, count 0 2006.201.17:02:11.62#ibcon#read 3, iclass 7, count 0 2006.201.17:02:11.62#ibcon#about to read 4, iclass 7, count 0 2006.201.17:02:11.62#ibcon#read 4, iclass 7, count 0 2006.201.17:02:11.62#ibcon#about to read 5, iclass 7, count 0 2006.201.17:02:11.62#ibcon#read 5, iclass 7, count 0 2006.201.17:02:11.62#ibcon#about to read 6, iclass 7, count 0 2006.201.17:02:11.62#ibcon#read 6, iclass 7, count 0 2006.201.17:02:11.62#ibcon#end of sib2, iclass 7, count 0 2006.201.17:02:11.62#ibcon#*after write, iclass 7, count 0 2006.201.17:02:11.62#ibcon#*before return 0, iclass 7, count 0 2006.201.17:02:11.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:11.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:11.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:02:11.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:02:11.62$vck44/va=6,5 2006.201.17:02:11.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.17:02:11.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.17:02:11.62#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:11.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:11.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:11.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:11.68#ibcon#enter wrdev, iclass 11, count 2 2006.201.17:02:11.68#ibcon#first serial, iclass 11, count 2 2006.201.17:02:11.68#ibcon#enter sib2, iclass 11, count 2 2006.201.17:02:11.68#ibcon#flushed, iclass 11, count 2 2006.201.17:02:11.68#ibcon#about to write, iclass 11, count 2 2006.201.17:02:11.68#ibcon#wrote, iclass 11, count 2 2006.201.17:02:11.68#ibcon#about to read 3, iclass 11, count 2 2006.201.17:02:11.70#ibcon#read 3, iclass 11, count 2 2006.201.17:02:11.70#ibcon#about to read 4, iclass 11, count 2 2006.201.17:02:11.70#ibcon#read 4, iclass 11, count 2 2006.201.17:02:11.70#ibcon#about to read 5, iclass 11, count 2 2006.201.17:02:11.70#ibcon#read 5, iclass 11, count 2 2006.201.17:02:11.70#ibcon#about to read 6, iclass 11, count 2 2006.201.17:02:11.70#ibcon#read 6, iclass 11, count 2 2006.201.17:02:11.70#ibcon#end of sib2, iclass 11, count 2 2006.201.17:02:11.70#ibcon#*mode == 0, iclass 11, count 2 2006.201.17:02:11.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.17:02:11.70#ibcon#[25=AT06-05\r\n] 2006.201.17:02:11.70#ibcon#*before write, iclass 11, count 2 2006.201.17:02:11.70#ibcon#enter sib2, iclass 11, count 2 2006.201.17:02:11.70#ibcon#flushed, iclass 11, count 2 2006.201.17:02:11.70#ibcon#about to write, iclass 11, count 2 2006.201.17:02:11.70#ibcon#wrote, iclass 11, count 2 2006.201.17:02:11.70#ibcon#about to read 3, iclass 11, count 2 2006.201.17:02:11.73#ibcon#read 3, iclass 11, count 2 2006.201.17:02:11.73#ibcon#about to read 4, iclass 11, count 2 2006.201.17:02:11.73#ibcon#read 4, iclass 11, count 2 2006.201.17:02:11.73#ibcon#about to read 5, iclass 11, count 2 2006.201.17:02:11.73#ibcon#read 5, iclass 11, count 2 2006.201.17:02:11.73#ibcon#about to read 6, iclass 11, count 2 2006.201.17:02:11.73#ibcon#read 6, iclass 11, count 2 2006.201.17:02:11.73#ibcon#end of sib2, iclass 11, count 2 2006.201.17:02:11.73#ibcon#*after write, iclass 11, count 2 2006.201.17:02:11.73#ibcon#*before return 0, iclass 11, count 2 2006.201.17:02:11.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:11.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:11.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.17:02:11.73#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:11.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:11.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:11.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:11.85#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:02:11.85#ibcon#first serial, iclass 11, count 0 2006.201.17:02:11.85#ibcon#enter sib2, iclass 11, count 0 2006.201.17:02:11.85#ibcon#flushed, iclass 11, count 0 2006.201.17:02:11.85#ibcon#about to write, iclass 11, count 0 2006.201.17:02:11.85#ibcon#wrote, iclass 11, count 0 2006.201.17:02:11.85#ibcon#about to read 3, iclass 11, count 0 2006.201.17:02:11.87#ibcon#read 3, iclass 11, count 0 2006.201.17:02:11.87#ibcon#about to read 4, iclass 11, count 0 2006.201.17:02:11.87#ibcon#read 4, iclass 11, count 0 2006.201.17:02:11.87#ibcon#about to read 5, iclass 11, count 0 2006.201.17:02:11.87#ibcon#read 5, iclass 11, count 0 2006.201.17:02:11.87#ibcon#about to read 6, iclass 11, count 0 2006.201.17:02:11.87#ibcon#read 6, iclass 11, count 0 2006.201.17:02:11.87#ibcon#end of sib2, iclass 11, count 0 2006.201.17:02:11.87#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:02:11.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:02:11.87#ibcon#[25=USB\r\n] 2006.201.17:02:11.87#ibcon#*before write, iclass 11, count 0 2006.201.17:02:11.87#ibcon#enter sib2, iclass 11, count 0 2006.201.17:02:11.87#ibcon#flushed, iclass 11, count 0 2006.201.17:02:11.87#ibcon#about to write, iclass 11, count 0 2006.201.17:02:11.87#ibcon#wrote, iclass 11, count 0 2006.201.17:02:11.87#ibcon#about to read 3, iclass 11, count 0 2006.201.17:02:11.90#ibcon#read 3, iclass 11, count 0 2006.201.17:02:11.90#ibcon#about to read 4, iclass 11, count 0 2006.201.17:02:11.90#ibcon#read 4, iclass 11, count 0 2006.201.17:02:11.90#ibcon#about to read 5, iclass 11, count 0 2006.201.17:02:11.90#ibcon#read 5, iclass 11, count 0 2006.201.17:02:11.90#ibcon#about to read 6, iclass 11, count 0 2006.201.17:02:11.90#ibcon#read 6, iclass 11, count 0 2006.201.17:02:11.90#ibcon#end of sib2, iclass 11, count 0 2006.201.17:02:11.90#ibcon#*after write, iclass 11, count 0 2006.201.17:02:11.90#ibcon#*before return 0, iclass 11, count 0 2006.201.17:02:11.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:11.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:11.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:02:11.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:02:11.90$vck44/valo=7,864.99 2006.201.17:02:11.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.17:02:11.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.17:02:11.90#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:11.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:11.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:11.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:11.90#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:02:11.90#ibcon#first serial, iclass 13, count 0 2006.201.17:02:11.90#ibcon#enter sib2, iclass 13, count 0 2006.201.17:02:11.90#ibcon#flushed, iclass 13, count 0 2006.201.17:02:11.90#ibcon#about to write, iclass 13, count 0 2006.201.17:02:11.90#ibcon#wrote, iclass 13, count 0 2006.201.17:02:11.90#ibcon#about to read 3, iclass 13, count 0 2006.201.17:02:11.92#ibcon#read 3, iclass 13, count 0 2006.201.17:02:11.92#ibcon#about to read 4, iclass 13, count 0 2006.201.17:02:11.92#ibcon#read 4, iclass 13, count 0 2006.201.17:02:11.92#ibcon#about to read 5, iclass 13, count 0 2006.201.17:02:11.92#ibcon#read 5, iclass 13, count 0 2006.201.17:02:11.92#ibcon#about to read 6, iclass 13, count 0 2006.201.17:02:11.92#ibcon#read 6, iclass 13, count 0 2006.201.17:02:11.92#ibcon#end of sib2, iclass 13, count 0 2006.201.17:02:11.92#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:02:11.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:02:11.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.17:02:11.92#ibcon#*before write, iclass 13, count 0 2006.201.17:02:11.92#ibcon#enter sib2, iclass 13, count 0 2006.201.17:02:11.92#ibcon#flushed, iclass 13, count 0 2006.201.17:02:11.92#ibcon#about to write, iclass 13, count 0 2006.201.17:02:11.92#ibcon#wrote, iclass 13, count 0 2006.201.17:02:11.92#ibcon#about to read 3, iclass 13, count 0 2006.201.17:02:11.96#ibcon#read 3, iclass 13, count 0 2006.201.17:02:11.96#ibcon#about to read 4, iclass 13, count 0 2006.201.17:02:11.96#ibcon#read 4, iclass 13, count 0 2006.201.17:02:11.96#ibcon#about to read 5, iclass 13, count 0 2006.201.17:02:11.96#ibcon#read 5, iclass 13, count 0 2006.201.17:02:11.96#ibcon#about to read 6, iclass 13, count 0 2006.201.17:02:11.96#ibcon#read 6, iclass 13, count 0 2006.201.17:02:11.96#ibcon#end of sib2, iclass 13, count 0 2006.201.17:02:11.96#ibcon#*after write, iclass 13, count 0 2006.201.17:02:11.96#ibcon#*before return 0, iclass 13, count 0 2006.201.17:02:11.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:11.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:11.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:02:11.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:02:11.96$vck44/va=7,5 2006.201.17:02:11.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.17:02:11.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.17:02:11.96#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:11.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:12.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:12.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:12.02#ibcon#enter wrdev, iclass 15, count 2 2006.201.17:02:12.02#ibcon#first serial, iclass 15, count 2 2006.201.17:02:12.02#ibcon#enter sib2, iclass 15, count 2 2006.201.17:02:12.02#ibcon#flushed, iclass 15, count 2 2006.201.17:02:12.02#ibcon#about to write, iclass 15, count 2 2006.201.17:02:12.02#ibcon#wrote, iclass 15, count 2 2006.201.17:02:12.02#ibcon#about to read 3, iclass 15, count 2 2006.201.17:02:12.04#ibcon#read 3, iclass 15, count 2 2006.201.17:02:12.04#ibcon#about to read 4, iclass 15, count 2 2006.201.17:02:12.04#ibcon#read 4, iclass 15, count 2 2006.201.17:02:12.04#ibcon#about to read 5, iclass 15, count 2 2006.201.17:02:12.04#ibcon#read 5, iclass 15, count 2 2006.201.17:02:12.04#ibcon#about to read 6, iclass 15, count 2 2006.201.17:02:12.04#ibcon#read 6, iclass 15, count 2 2006.201.17:02:12.04#ibcon#end of sib2, iclass 15, count 2 2006.201.17:02:12.04#ibcon#*mode == 0, iclass 15, count 2 2006.201.17:02:12.04#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.17:02:12.04#ibcon#[25=AT07-05\r\n] 2006.201.17:02:12.04#ibcon#*before write, iclass 15, count 2 2006.201.17:02:12.04#ibcon#enter sib2, iclass 15, count 2 2006.201.17:02:12.04#ibcon#flushed, iclass 15, count 2 2006.201.17:02:12.04#ibcon#about to write, iclass 15, count 2 2006.201.17:02:12.04#ibcon#wrote, iclass 15, count 2 2006.201.17:02:12.04#ibcon#about to read 3, iclass 15, count 2 2006.201.17:02:12.07#ibcon#read 3, iclass 15, count 2 2006.201.17:02:12.07#ibcon#about to read 4, iclass 15, count 2 2006.201.17:02:12.07#ibcon#read 4, iclass 15, count 2 2006.201.17:02:12.07#ibcon#about to read 5, iclass 15, count 2 2006.201.17:02:12.07#ibcon#read 5, iclass 15, count 2 2006.201.17:02:12.07#ibcon#about to read 6, iclass 15, count 2 2006.201.17:02:12.07#ibcon#read 6, iclass 15, count 2 2006.201.17:02:12.07#ibcon#end of sib2, iclass 15, count 2 2006.201.17:02:12.07#ibcon#*after write, iclass 15, count 2 2006.201.17:02:12.07#ibcon#*before return 0, iclass 15, count 2 2006.201.17:02:12.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:12.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:12.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.17:02:12.07#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:12.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:12.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:12.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:12.19#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:02:12.19#ibcon#first serial, iclass 15, count 0 2006.201.17:02:12.19#ibcon#enter sib2, iclass 15, count 0 2006.201.17:02:12.19#ibcon#flushed, iclass 15, count 0 2006.201.17:02:12.19#ibcon#about to write, iclass 15, count 0 2006.201.17:02:12.19#ibcon#wrote, iclass 15, count 0 2006.201.17:02:12.19#ibcon#about to read 3, iclass 15, count 0 2006.201.17:02:12.21#ibcon#read 3, iclass 15, count 0 2006.201.17:02:12.21#ibcon#about to read 4, iclass 15, count 0 2006.201.17:02:12.21#ibcon#read 4, iclass 15, count 0 2006.201.17:02:12.21#ibcon#about to read 5, iclass 15, count 0 2006.201.17:02:12.21#ibcon#read 5, iclass 15, count 0 2006.201.17:02:12.21#ibcon#about to read 6, iclass 15, count 0 2006.201.17:02:12.21#ibcon#read 6, iclass 15, count 0 2006.201.17:02:12.21#ibcon#end of sib2, iclass 15, count 0 2006.201.17:02:12.21#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:02:12.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:02:12.21#ibcon#[25=USB\r\n] 2006.201.17:02:12.21#ibcon#*before write, iclass 15, count 0 2006.201.17:02:12.21#ibcon#enter sib2, iclass 15, count 0 2006.201.17:02:12.21#ibcon#flushed, iclass 15, count 0 2006.201.17:02:12.21#ibcon#about to write, iclass 15, count 0 2006.201.17:02:12.21#ibcon#wrote, iclass 15, count 0 2006.201.17:02:12.21#ibcon#about to read 3, iclass 15, count 0 2006.201.17:02:12.24#ibcon#read 3, iclass 15, count 0 2006.201.17:02:12.24#ibcon#about to read 4, iclass 15, count 0 2006.201.17:02:12.24#ibcon#read 4, iclass 15, count 0 2006.201.17:02:12.24#ibcon#about to read 5, iclass 15, count 0 2006.201.17:02:12.24#ibcon#read 5, iclass 15, count 0 2006.201.17:02:12.24#ibcon#about to read 6, iclass 15, count 0 2006.201.17:02:12.24#ibcon#read 6, iclass 15, count 0 2006.201.17:02:12.24#ibcon#end of sib2, iclass 15, count 0 2006.201.17:02:12.24#ibcon#*after write, iclass 15, count 0 2006.201.17:02:12.24#ibcon#*before return 0, iclass 15, count 0 2006.201.17:02:12.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:12.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:12.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:02:12.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:02:12.24$vck44/valo=8,884.99 2006.201.17:02:12.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.17:02:12.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.17:02:12.24#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:12.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:12.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:12.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:12.24#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:02:12.24#ibcon#first serial, iclass 17, count 0 2006.201.17:02:12.24#ibcon#enter sib2, iclass 17, count 0 2006.201.17:02:12.24#ibcon#flushed, iclass 17, count 0 2006.201.17:02:12.24#ibcon#about to write, iclass 17, count 0 2006.201.17:02:12.24#ibcon#wrote, iclass 17, count 0 2006.201.17:02:12.24#ibcon#about to read 3, iclass 17, count 0 2006.201.17:02:12.26#ibcon#read 3, iclass 17, count 0 2006.201.17:02:12.26#ibcon#about to read 4, iclass 17, count 0 2006.201.17:02:12.26#ibcon#read 4, iclass 17, count 0 2006.201.17:02:12.26#ibcon#about to read 5, iclass 17, count 0 2006.201.17:02:12.26#ibcon#read 5, iclass 17, count 0 2006.201.17:02:12.26#ibcon#about to read 6, iclass 17, count 0 2006.201.17:02:12.26#ibcon#read 6, iclass 17, count 0 2006.201.17:02:12.26#ibcon#end of sib2, iclass 17, count 0 2006.201.17:02:12.26#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:02:12.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:02:12.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.17:02:12.26#ibcon#*before write, iclass 17, count 0 2006.201.17:02:12.26#ibcon#enter sib2, iclass 17, count 0 2006.201.17:02:12.26#ibcon#flushed, iclass 17, count 0 2006.201.17:02:12.26#ibcon#about to write, iclass 17, count 0 2006.201.17:02:12.26#ibcon#wrote, iclass 17, count 0 2006.201.17:02:12.26#ibcon#about to read 3, iclass 17, count 0 2006.201.17:02:12.30#ibcon#read 3, iclass 17, count 0 2006.201.17:02:12.30#ibcon#about to read 4, iclass 17, count 0 2006.201.17:02:12.30#ibcon#read 4, iclass 17, count 0 2006.201.17:02:12.30#ibcon#about to read 5, iclass 17, count 0 2006.201.17:02:12.30#ibcon#read 5, iclass 17, count 0 2006.201.17:02:12.30#ibcon#about to read 6, iclass 17, count 0 2006.201.17:02:12.30#ibcon#read 6, iclass 17, count 0 2006.201.17:02:12.30#ibcon#end of sib2, iclass 17, count 0 2006.201.17:02:12.30#ibcon#*after write, iclass 17, count 0 2006.201.17:02:12.30#ibcon#*before return 0, iclass 17, count 0 2006.201.17:02:12.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:12.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:12.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:02:12.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:02:12.30$vck44/va=8,4 2006.201.17:02:12.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.17:02:12.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.17:02:12.30#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:12.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:02:12.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:02:12.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:02:12.36#ibcon#enter wrdev, iclass 19, count 2 2006.201.17:02:12.36#ibcon#first serial, iclass 19, count 2 2006.201.17:02:12.36#ibcon#enter sib2, iclass 19, count 2 2006.201.17:02:12.36#ibcon#flushed, iclass 19, count 2 2006.201.17:02:12.36#ibcon#about to write, iclass 19, count 2 2006.201.17:02:12.36#ibcon#wrote, iclass 19, count 2 2006.201.17:02:12.36#ibcon#about to read 3, iclass 19, count 2 2006.201.17:02:12.38#ibcon#read 3, iclass 19, count 2 2006.201.17:02:12.38#ibcon#about to read 4, iclass 19, count 2 2006.201.17:02:12.38#ibcon#read 4, iclass 19, count 2 2006.201.17:02:12.38#ibcon#about to read 5, iclass 19, count 2 2006.201.17:02:12.38#ibcon#read 5, iclass 19, count 2 2006.201.17:02:12.38#ibcon#about to read 6, iclass 19, count 2 2006.201.17:02:12.38#ibcon#read 6, iclass 19, count 2 2006.201.17:02:12.38#ibcon#end of sib2, iclass 19, count 2 2006.201.17:02:12.38#ibcon#*mode == 0, iclass 19, count 2 2006.201.17:02:12.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.17:02:12.38#ibcon#[25=AT08-04\r\n] 2006.201.17:02:12.38#ibcon#*before write, iclass 19, count 2 2006.201.17:02:12.38#ibcon#enter sib2, iclass 19, count 2 2006.201.17:02:12.38#ibcon#flushed, iclass 19, count 2 2006.201.17:02:12.38#ibcon#about to write, iclass 19, count 2 2006.201.17:02:12.38#ibcon#wrote, iclass 19, count 2 2006.201.17:02:12.38#ibcon#about to read 3, iclass 19, count 2 2006.201.17:02:12.41#ibcon#read 3, iclass 19, count 2 2006.201.17:02:12.41#ibcon#about to read 4, iclass 19, count 2 2006.201.17:02:12.41#ibcon#read 4, iclass 19, count 2 2006.201.17:02:12.41#ibcon#about to read 5, iclass 19, count 2 2006.201.17:02:12.41#ibcon#read 5, iclass 19, count 2 2006.201.17:02:12.41#ibcon#about to read 6, iclass 19, count 2 2006.201.17:02:12.41#ibcon#read 6, iclass 19, count 2 2006.201.17:02:12.41#ibcon#end of sib2, iclass 19, count 2 2006.201.17:02:12.41#ibcon#*after write, iclass 19, count 2 2006.201.17:02:12.41#ibcon#*before return 0, iclass 19, count 2 2006.201.17:02:12.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:02:12.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:02:12.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.17:02:12.41#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:12.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:02:12.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:02:12.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:02:12.53#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:02:12.53#ibcon#first serial, iclass 19, count 0 2006.201.17:02:12.53#ibcon#enter sib2, iclass 19, count 0 2006.201.17:02:12.53#ibcon#flushed, iclass 19, count 0 2006.201.17:02:12.53#ibcon#about to write, iclass 19, count 0 2006.201.17:02:12.53#ibcon#wrote, iclass 19, count 0 2006.201.17:02:12.53#ibcon#about to read 3, iclass 19, count 0 2006.201.17:02:12.55#ibcon#read 3, iclass 19, count 0 2006.201.17:02:12.55#ibcon#about to read 4, iclass 19, count 0 2006.201.17:02:12.55#ibcon#read 4, iclass 19, count 0 2006.201.17:02:12.55#ibcon#about to read 5, iclass 19, count 0 2006.201.17:02:12.55#ibcon#read 5, iclass 19, count 0 2006.201.17:02:12.55#ibcon#about to read 6, iclass 19, count 0 2006.201.17:02:12.55#ibcon#read 6, iclass 19, count 0 2006.201.17:02:12.55#ibcon#end of sib2, iclass 19, count 0 2006.201.17:02:12.55#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:02:12.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:02:12.55#ibcon#[25=USB\r\n] 2006.201.17:02:12.55#ibcon#*before write, iclass 19, count 0 2006.201.17:02:12.55#ibcon#enter sib2, iclass 19, count 0 2006.201.17:02:12.55#ibcon#flushed, iclass 19, count 0 2006.201.17:02:12.55#ibcon#about to write, iclass 19, count 0 2006.201.17:02:12.55#ibcon#wrote, iclass 19, count 0 2006.201.17:02:12.55#ibcon#about to read 3, iclass 19, count 0 2006.201.17:02:12.58#ibcon#read 3, iclass 19, count 0 2006.201.17:02:12.58#ibcon#about to read 4, iclass 19, count 0 2006.201.17:02:12.58#ibcon#read 4, iclass 19, count 0 2006.201.17:02:12.58#ibcon#about to read 5, iclass 19, count 0 2006.201.17:02:12.58#ibcon#read 5, iclass 19, count 0 2006.201.17:02:12.58#ibcon#about to read 6, iclass 19, count 0 2006.201.17:02:12.58#ibcon#read 6, iclass 19, count 0 2006.201.17:02:12.58#ibcon#end of sib2, iclass 19, count 0 2006.201.17:02:12.58#ibcon#*after write, iclass 19, count 0 2006.201.17:02:12.58#ibcon#*before return 0, iclass 19, count 0 2006.201.17:02:12.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:02:12.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:02:12.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:02:12.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:02:12.58$vck44/vblo=1,629.99 2006.201.17:02:12.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.17:02:12.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.17:02:12.58#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:12.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:02:12.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:02:12.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:02:12.58#ibcon#enter wrdev, iclass 21, count 0 2006.201.17:02:12.58#ibcon#first serial, iclass 21, count 0 2006.201.17:02:12.58#ibcon#enter sib2, iclass 21, count 0 2006.201.17:02:12.58#ibcon#flushed, iclass 21, count 0 2006.201.17:02:12.58#ibcon#about to write, iclass 21, count 0 2006.201.17:02:12.58#ibcon#wrote, iclass 21, count 0 2006.201.17:02:12.58#ibcon#about to read 3, iclass 21, count 0 2006.201.17:02:12.60#ibcon#read 3, iclass 21, count 0 2006.201.17:02:12.60#ibcon#about to read 4, iclass 21, count 0 2006.201.17:02:12.60#ibcon#read 4, iclass 21, count 0 2006.201.17:02:12.60#ibcon#about to read 5, iclass 21, count 0 2006.201.17:02:12.60#ibcon#read 5, iclass 21, count 0 2006.201.17:02:12.60#ibcon#about to read 6, iclass 21, count 0 2006.201.17:02:12.60#ibcon#read 6, iclass 21, count 0 2006.201.17:02:12.60#ibcon#end of sib2, iclass 21, count 0 2006.201.17:02:12.60#ibcon#*mode == 0, iclass 21, count 0 2006.201.17:02:12.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.17:02:12.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.17:02:12.60#ibcon#*before write, iclass 21, count 0 2006.201.17:02:12.60#ibcon#enter sib2, iclass 21, count 0 2006.201.17:02:12.60#ibcon#flushed, iclass 21, count 0 2006.201.17:02:12.60#ibcon#about to write, iclass 21, count 0 2006.201.17:02:12.60#ibcon#wrote, iclass 21, count 0 2006.201.17:02:12.60#ibcon#about to read 3, iclass 21, count 0 2006.201.17:02:12.65#ibcon#read 3, iclass 21, count 0 2006.201.17:02:12.65#ibcon#about to read 4, iclass 21, count 0 2006.201.17:02:12.65#ibcon#read 4, iclass 21, count 0 2006.201.17:02:12.65#ibcon#about to read 5, iclass 21, count 0 2006.201.17:02:12.65#ibcon#read 5, iclass 21, count 0 2006.201.17:02:12.65#ibcon#about to read 6, iclass 21, count 0 2006.201.17:02:12.65#ibcon#read 6, iclass 21, count 0 2006.201.17:02:12.65#ibcon#end of sib2, iclass 21, count 0 2006.201.17:02:12.65#ibcon#*after write, iclass 21, count 0 2006.201.17:02:12.65#ibcon#*before return 0, iclass 21, count 0 2006.201.17:02:12.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:02:12.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:02:12.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.17:02:12.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.17:02:12.65$vck44/vb=1,4 2006.201.17:02:12.65#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.17:02:12.65#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.17:02:12.65#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:12.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:02:12.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:02:12.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:02:12.65#ibcon#enter wrdev, iclass 23, count 2 2006.201.17:02:12.65#ibcon#first serial, iclass 23, count 2 2006.201.17:02:12.65#ibcon#enter sib2, iclass 23, count 2 2006.201.17:02:12.65#ibcon#flushed, iclass 23, count 2 2006.201.17:02:12.65#ibcon#about to write, iclass 23, count 2 2006.201.17:02:12.65#ibcon#wrote, iclass 23, count 2 2006.201.17:02:12.65#ibcon#about to read 3, iclass 23, count 2 2006.201.17:02:12.67#ibcon#read 3, iclass 23, count 2 2006.201.17:02:12.67#ibcon#about to read 4, iclass 23, count 2 2006.201.17:02:12.67#ibcon#read 4, iclass 23, count 2 2006.201.17:02:12.67#ibcon#about to read 5, iclass 23, count 2 2006.201.17:02:12.67#ibcon#read 5, iclass 23, count 2 2006.201.17:02:12.67#ibcon#about to read 6, iclass 23, count 2 2006.201.17:02:12.67#ibcon#read 6, iclass 23, count 2 2006.201.17:02:12.67#ibcon#end of sib2, iclass 23, count 2 2006.201.17:02:12.67#ibcon#*mode == 0, iclass 23, count 2 2006.201.17:02:12.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.17:02:12.67#ibcon#[27=AT01-04\r\n] 2006.201.17:02:12.67#ibcon#*before write, iclass 23, count 2 2006.201.17:02:12.67#ibcon#enter sib2, iclass 23, count 2 2006.201.17:02:12.67#ibcon#flushed, iclass 23, count 2 2006.201.17:02:12.67#ibcon#about to write, iclass 23, count 2 2006.201.17:02:12.67#ibcon#wrote, iclass 23, count 2 2006.201.17:02:12.67#ibcon#about to read 3, iclass 23, count 2 2006.201.17:02:12.70#ibcon#read 3, iclass 23, count 2 2006.201.17:02:12.70#ibcon#about to read 4, iclass 23, count 2 2006.201.17:02:12.70#ibcon#read 4, iclass 23, count 2 2006.201.17:02:12.70#ibcon#about to read 5, iclass 23, count 2 2006.201.17:02:12.70#ibcon#read 5, iclass 23, count 2 2006.201.17:02:12.70#ibcon#about to read 6, iclass 23, count 2 2006.201.17:02:12.70#ibcon#read 6, iclass 23, count 2 2006.201.17:02:12.70#ibcon#end of sib2, iclass 23, count 2 2006.201.17:02:12.70#ibcon#*after write, iclass 23, count 2 2006.201.17:02:12.70#ibcon#*before return 0, iclass 23, count 2 2006.201.17:02:12.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:02:12.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:02:12.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.17:02:12.70#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:12.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:02:12.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:02:12.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:02:12.82#ibcon#enter wrdev, iclass 23, count 0 2006.201.17:02:12.82#ibcon#first serial, iclass 23, count 0 2006.201.17:02:12.82#ibcon#enter sib2, iclass 23, count 0 2006.201.17:02:12.82#ibcon#flushed, iclass 23, count 0 2006.201.17:02:12.82#ibcon#about to write, iclass 23, count 0 2006.201.17:02:12.82#ibcon#wrote, iclass 23, count 0 2006.201.17:02:12.82#ibcon#about to read 3, iclass 23, count 0 2006.201.17:02:12.84#ibcon#read 3, iclass 23, count 0 2006.201.17:02:12.84#ibcon#about to read 4, iclass 23, count 0 2006.201.17:02:12.84#ibcon#read 4, iclass 23, count 0 2006.201.17:02:12.84#ibcon#about to read 5, iclass 23, count 0 2006.201.17:02:12.84#ibcon#read 5, iclass 23, count 0 2006.201.17:02:12.84#ibcon#about to read 6, iclass 23, count 0 2006.201.17:02:12.84#ibcon#read 6, iclass 23, count 0 2006.201.17:02:12.84#ibcon#end of sib2, iclass 23, count 0 2006.201.17:02:12.84#ibcon#*mode == 0, iclass 23, count 0 2006.201.17:02:12.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.17:02:12.84#ibcon#[27=USB\r\n] 2006.201.17:02:12.84#ibcon#*before write, iclass 23, count 0 2006.201.17:02:12.84#ibcon#enter sib2, iclass 23, count 0 2006.201.17:02:12.84#ibcon#flushed, iclass 23, count 0 2006.201.17:02:12.84#ibcon#about to write, iclass 23, count 0 2006.201.17:02:12.84#ibcon#wrote, iclass 23, count 0 2006.201.17:02:12.84#ibcon#about to read 3, iclass 23, count 0 2006.201.17:02:12.87#ibcon#read 3, iclass 23, count 0 2006.201.17:02:12.87#ibcon#about to read 4, iclass 23, count 0 2006.201.17:02:12.87#ibcon#read 4, iclass 23, count 0 2006.201.17:02:12.87#ibcon#about to read 5, iclass 23, count 0 2006.201.17:02:12.87#ibcon#read 5, iclass 23, count 0 2006.201.17:02:12.87#ibcon#about to read 6, iclass 23, count 0 2006.201.17:02:12.87#ibcon#read 6, iclass 23, count 0 2006.201.17:02:12.87#ibcon#end of sib2, iclass 23, count 0 2006.201.17:02:12.87#ibcon#*after write, iclass 23, count 0 2006.201.17:02:12.87#ibcon#*before return 0, iclass 23, count 0 2006.201.17:02:12.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:02:12.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:02:12.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.17:02:12.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.17:02:12.87$vck44/vblo=2,634.99 2006.201.17:02:12.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.17:02:12.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.17:02:12.87#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:12.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:12.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:12.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:12.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:02:12.87#ibcon#first serial, iclass 25, count 0 2006.201.17:02:12.87#ibcon#enter sib2, iclass 25, count 0 2006.201.17:02:12.87#ibcon#flushed, iclass 25, count 0 2006.201.17:02:12.87#ibcon#about to write, iclass 25, count 0 2006.201.17:02:12.87#ibcon#wrote, iclass 25, count 0 2006.201.17:02:12.87#ibcon#about to read 3, iclass 25, count 0 2006.201.17:02:12.89#ibcon#read 3, iclass 25, count 0 2006.201.17:02:12.89#ibcon#about to read 4, iclass 25, count 0 2006.201.17:02:12.89#ibcon#read 4, iclass 25, count 0 2006.201.17:02:12.89#ibcon#about to read 5, iclass 25, count 0 2006.201.17:02:12.89#ibcon#read 5, iclass 25, count 0 2006.201.17:02:12.89#ibcon#about to read 6, iclass 25, count 0 2006.201.17:02:12.89#ibcon#read 6, iclass 25, count 0 2006.201.17:02:12.89#ibcon#end of sib2, iclass 25, count 0 2006.201.17:02:12.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:02:12.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:02:12.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.17:02:12.89#ibcon#*before write, iclass 25, count 0 2006.201.17:02:12.89#ibcon#enter sib2, iclass 25, count 0 2006.201.17:02:12.89#ibcon#flushed, iclass 25, count 0 2006.201.17:02:12.89#ibcon#about to write, iclass 25, count 0 2006.201.17:02:12.89#ibcon#wrote, iclass 25, count 0 2006.201.17:02:12.89#ibcon#about to read 3, iclass 25, count 0 2006.201.17:02:12.93#ibcon#read 3, iclass 25, count 0 2006.201.17:02:12.93#ibcon#about to read 4, iclass 25, count 0 2006.201.17:02:12.93#ibcon#read 4, iclass 25, count 0 2006.201.17:02:12.93#ibcon#about to read 5, iclass 25, count 0 2006.201.17:02:12.93#ibcon#read 5, iclass 25, count 0 2006.201.17:02:12.93#ibcon#about to read 6, iclass 25, count 0 2006.201.17:02:12.93#ibcon#read 6, iclass 25, count 0 2006.201.17:02:12.93#ibcon#end of sib2, iclass 25, count 0 2006.201.17:02:12.93#ibcon#*after write, iclass 25, count 0 2006.201.17:02:12.93#ibcon#*before return 0, iclass 25, count 0 2006.201.17:02:12.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:12.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:02:12.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:02:12.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:02:12.93$vck44/vb=2,5 2006.201.17:02:12.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.17:02:12.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.17:02:12.93#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:12.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:12.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:12.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:12.99#ibcon#enter wrdev, iclass 27, count 2 2006.201.17:02:12.99#ibcon#first serial, iclass 27, count 2 2006.201.17:02:12.99#ibcon#enter sib2, iclass 27, count 2 2006.201.17:02:12.99#ibcon#flushed, iclass 27, count 2 2006.201.17:02:12.99#ibcon#about to write, iclass 27, count 2 2006.201.17:02:12.99#ibcon#wrote, iclass 27, count 2 2006.201.17:02:12.99#ibcon#about to read 3, iclass 27, count 2 2006.201.17:02:13.01#ibcon#read 3, iclass 27, count 2 2006.201.17:02:13.01#ibcon#about to read 4, iclass 27, count 2 2006.201.17:02:13.01#ibcon#read 4, iclass 27, count 2 2006.201.17:02:13.01#ibcon#about to read 5, iclass 27, count 2 2006.201.17:02:13.01#ibcon#read 5, iclass 27, count 2 2006.201.17:02:13.01#ibcon#about to read 6, iclass 27, count 2 2006.201.17:02:13.01#ibcon#read 6, iclass 27, count 2 2006.201.17:02:13.01#ibcon#end of sib2, iclass 27, count 2 2006.201.17:02:13.01#ibcon#*mode == 0, iclass 27, count 2 2006.201.17:02:13.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.17:02:13.01#ibcon#[27=AT02-05\r\n] 2006.201.17:02:13.01#ibcon#*before write, iclass 27, count 2 2006.201.17:02:13.01#ibcon#enter sib2, iclass 27, count 2 2006.201.17:02:13.01#ibcon#flushed, iclass 27, count 2 2006.201.17:02:13.01#ibcon#about to write, iclass 27, count 2 2006.201.17:02:13.01#ibcon#wrote, iclass 27, count 2 2006.201.17:02:13.01#ibcon#about to read 3, iclass 27, count 2 2006.201.17:02:13.04#ibcon#read 3, iclass 27, count 2 2006.201.17:02:13.04#ibcon#about to read 4, iclass 27, count 2 2006.201.17:02:13.04#ibcon#read 4, iclass 27, count 2 2006.201.17:02:13.04#ibcon#about to read 5, iclass 27, count 2 2006.201.17:02:13.04#ibcon#read 5, iclass 27, count 2 2006.201.17:02:13.04#ibcon#about to read 6, iclass 27, count 2 2006.201.17:02:13.04#ibcon#read 6, iclass 27, count 2 2006.201.17:02:13.04#ibcon#end of sib2, iclass 27, count 2 2006.201.17:02:13.04#ibcon#*after write, iclass 27, count 2 2006.201.17:02:13.04#ibcon#*before return 0, iclass 27, count 2 2006.201.17:02:13.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:13.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:02:13.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.17:02:13.04#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:13.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:13.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:13.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:13.16#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:02:13.16#ibcon#first serial, iclass 27, count 0 2006.201.17:02:13.16#ibcon#enter sib2, iclass 27, count 0 2006.201.17:02:13.16#ibcon#flushed, iclass 27, count 0 2006.201.17:02:13.16#ibcon#about to write, iclass 27, count 0 2006.201.17:02:13.16#ibcon#wrote, iclass 27, count 0 2006.201.17:02:13.16#ibcon#about to read 3, iclass 27, count 0 2006.201.17:02:13.18#ibcon#read 3, iclass 27, count 0 2006.201.17:02:13.18#ibcon#about to read 4, iclass 27, count 0 2006.201.17:02:13.18#ibcon#read 4, iclass 27, count 0 2006.201.17:02:13.18#ibcon#about to read 5, iclass 27, count 0 2006.201.17:02:13.18#ibcon#read 5, iclass 27, count 0 2006.201.17:02:13.18#ibcon#about to read 6, iclass 27, count 0 2006.201.17:02:13.18#ibcon#read 6, iclass 27, count 0 2006.201.17:02:13.18#ibcon#end of sib2, iclass 27, count 0 2006.201.17:02:13.18#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:02:13.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:02:13.18#ibcon#[27=USB\r\n] 2006.201.17:02:13.18#ibcon#*before write, iclass 27, count 0 2006.201.17:02:13.18#ibcon#enter sib2, iclass 27, count 0 2006.201.17:02:13.18#ibcon#flushed, iclass 27, count 0 2006.201.17:02:13.18#ibcon#about to write, iclass 27, count 0 2006.201.17:02:13.18#ibcon#wrote, iclass 27, count 0 2006.201.17:02:13.18#ibcon#about to read 3, iclass 27, count 0 2006.201.17:02:13.21#ibcon#read 3, iclass 27, count 0 2006.201.17:02:13.21#ibcon#about to read 4, iclass 27, count 0 2006.201.17:02:13.21#ibcon#read 4, iclass 27, count 0 2006.201.17:02:13.21#ibcon#about to read 5, iclass 27, count 0 2006.201.17:02:13.21#ibcon#read 5, iclass 27, count 0 2006.201.17:02:13.21#ibcon#about to read 6, iclass 27, count 0 2006.201.17:02:13.21#ibcon#read 6, iclass 27, count 0 2006.201.17:02:13.21#ibcon#end of sib2, iclass 27, count 0 2006.201.17:02:13.21#ibcon#*after write, iclass 27, count 0 2006.201.17:02:13.21#ibcon#*before return 0, iclass 27, count 0 2006.201.17:02:13.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:13.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:02:13.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:02:13.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:02:13.21$vck44/vblo=3,649.99 2006.201.17:02:13.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.17:02:13.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.17:02:13.21#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:13.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:13.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:13.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:13.21#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:02:13.21#ibcon#first serial, iclass 29, count 0 2006.201.17:02:13.21#ibcon#enter sib2, iclass 29, count 0 2006.201.17:02:13.21#ibcon#flushed, iclass 29, count 0 2006.201.17:02:13.21#ibcon#about to write, iclass 29, count 0 2006.201.17:02:13.21#ibcon#wrote, iclass 29, count 0 2006.201.17:02:13.21#ibcon#about to read 3, iclass 29, count 0 2006.201.17:02:13.23#ibcon#read 3, iclass 29, count 0 2006.201.17:02:13.23#ibcon#about to read 4, iclass 29, count 0 2006.201.17:02:13.23#ibcon#read 4, iclass 29, count 0 2006.201.17:02:13.23#ibcon#about to read 5, iclass 29, count 0 2006.201.17:02:13.23#ibcon#read 5, iclass 29, count 0 2006.201.17:02:13.23#ibcon#about to read 6, iclass 29, count 0 2006.201.17:02:13.23#ibcon#read 6, iclass 29, count 0 2006.201.17:02:13.23#ibcon#end of sib2, iclass 29, count 0 2006.201.17:02:13.23#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:02:13.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:02:13.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.17:02:13.23#ibcon#*before write, iclass 29, count 0 2006.201.17:02:13.23#ibcon#enter sib2, iclass 29, count 0 2006.201.17:02:13.23#ibcon#flushed, iclass 29, count 0 2006.201.17:02:13.23#ibcon#about to write, iclass 29, count 0 2006.201.17:02:13.23#ibcon#wrote, iclass 29, count 0 2006.201.17:02:13.23#ibcon#about to read 3, iclass 29, count 0 2006.201.17:02:13.28#ibcon#read 3, iclass 29, count 0 2006.201.17:02:13.28#ibcon#about to read 4, iclass 29, count 0 2006.201.17:02:13.28#ibcon#read 4, iclass 29, count 0 2006.201.17:02:13.28#ibcon#about to read 5, iclass 29, count 0 2006.201.17:02:13.28#ibcon#read 5, iclass 29, count 0 2006.201.17:02:13.28#ibcon#about to read 6, iclass 29, count 0 2006.201.17:02:13.28#ibcon#read 6, iclass 29, count 0 2006.201.17:02:13.28#ibcon#end of sib2, iclass 29, count 0 2006.201.17:02:13.28#ibcon#*after write, iclass 29, count 0 2006.201.17:02:13.28#ibcon#*before return 0, iclass 29, count 0 2006.201.17:02:13.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:13.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:02:13.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:02:13.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:02:13.28$vck44/vb=3,4 2006.201.17:02:13.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.17:02:13.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.17:02:13.28#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:13.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:13.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:13.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:13.33#ibcon#enter wrdev, iclass 31, count 2 2006.201.17:02:13.33#ibcon#first serial, iclass 31, count 2 2006.201.17:02:13.33#ibcon#enter sib2, iclass 31, count 2 2006.201.17:02:13.33#ibcon#flushed, iclass 31, count 2 2006.201.17:02:13.33#ibcon#about to write, iclass 31, count 2 2006.201.17:02:13.33#ibcon#wrote, iclass 31, count 2 2006.201.17:02:13.33#ibcon#about to read 3, iclass 31, count 2 2006.201.17:02:13.35#ibcon#read 3, iclass 31, count 2 2006.201.17:02:13.35#ibcon#about to read 4, iclass 31, count 2 2006.201.17:02:13.35#ibcon#read 4, iclass 31, count 2 2006.201.17:02:13.35#ibcon#about to read 5, iclass 31, count 2 2006.201.17:02:13.35#ibcon#read 5, iclass 31, count 2 2006.201.17:02:13.35#ibcon#about to read 6, iclass 31, count 2 2006.201.17:02:13.35#ibcon#read 6, iclass 31, count 2 2006.201.17:02:13.35#ibcon#end of sib2, iclass 31, count 2 2006.201.17:02:13.35#ibcon#*mode == 0, iclass 31, count 2 2006.201.17:02:13.35#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.17:02:13.35#ibcon#[27=AT03-04\r\n] 2006.201.17:02:13.35#ibcon#*before write, iclass 31, count 2 2006.201.17:02:13.35#ibcon#enter sib2, iclass 31, count 2 2006.201.17:02:13.35#ibcon#flushed, iclass 31, count 2 2006.201.17:02:13.35#ibcon#about to write, iclass 31, count 2 2006.201.17:02:13.35#ibcon#wrote, iclass 31, count 2 2006.201.17:02:13.35#ibcon#about to read 3, iclass 31, count 2 2006.201.17:02:13.38#ibcon#read 3, iclass 31, count 2 2006.201.17:02:13.38#ibcon#about to read 4, iclass 31, count 2 2006.201.17:02:13.38#ibcon#read 4, iclass 31, count 2 2006.201.17:02:13.38#ibcon#about to read 5, iclass 31, count 2 2006.201.17:02:13.38#ibcon#read 5, iclass 31, count 2 2006.201.17:02:13.38#ibcon#about to read 6, iclass 31, count 2 2006.201.17:02:13.38#ibcon#read 6, iclass 31, count 2 2006.201.17:02:13.38#ibcon#end of sib2, iclass 31, count 2 2006.201.17:02:13.38#ibcon#*after write, iclass 31, count 2 2006.201.17:02:13.38#ibcon#*before return 0, iclass 31, count 2 2006.201.17:02:13.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:13.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:02:13.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.17:02:13.38#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:13.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:13.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:13.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:13.50#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:02:13.50#ibcon#first serial, iclass 31, count 0 2006.201.17:02:13.50#ibcon#enter sib2, iclass 31, count 0 2006.201.17:02:13.50#ibcon#flushed, iclass 31, count 0 2006.201.17:02:13.50#ibcon#about to write, iclass 31, count 0 2006.201.17:02:13.50#ibcon#wrote, iclass 31, count 0 2006.201.17:02:13.50#ibcon#about to read 3, iclass 31, count 0 2006.201.17:02:13.52#ibcon#read 3, iclass 31, count 0 2006.201.17:02:13.52#ibcon#about to read 4, iclass 31, count 0 2006.201.17:02:13.52#ibcon#read 4, iclass 31, count 0 2006.201.17:02:13.52#ibcon#about to read 5, iclass 31, count 0 2006.201.17:02:13.52#ibcon#read 5, iclass 31, count 0 2006.201.17:02:13.52#ibcon#about to read 6, iclass 31, count 0 2006.201.17:02:13.52#ibcon#read 6, iclass 31, count 0 2006.201.17:02:13.52#ibcon#end of sib2, iclass 31, count 0 2006.201.17:02:13.52#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:02:13.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:02:13.52#ibcon#[27=USB\r\n] 2006.201.17:02:13.52#ibcon#*before write, iclass 31, count 0 2006.201.17:02:13.52#ibcon#enter sib2, iclass 31, count 0 2006.201.17:02:13.52#ibcon#flushed, iclass 31, count 0 2006.201.17:02:13.52#ibcon#about to write, iclass 31, count 0 2006.201.17:02:13.52#ibcon#wrote, iclass 31, count 0 2006.201.17:02:13.52#ibcon#about to read 3, iclass 31, count 0 2006.201.17:02:13.55#ibcon#read 3, iclass 31, count 0 2006.201.17:02:13.55#ibcon#about to read 4, iclass 31, count 0 2006.201.17:02:13.55#ibcon#read 4, iclass 31, count 0 2006.201.17:02:13.55#ibcon#about to read 5, iclass 31, count 0 2006.201.17:02:13.55#ibcon#read 5, iclass 31, count 0 2006.201.17:02:13.55#ibcon#about to read 6, iclass 31, count 0 2006.201.17:02:13.55#ibcon#read 6, iclass 31, count 0 2006.201.17:02:13.55#ibcon#end of sib2, iclass 31, count 0 2006.201.17:02:13.55#ibcon#*after write, iclass 31, count 0 2006.201.17:02:13.55#ibcon#*before return 0, iclass 31, count 0 2006.201.17:02:13.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:13.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:02:13.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:02:13.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:02:13.55$vck44/vblo=4,679.99 2006.201.17:02:13.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.17:02:13.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.17:02:13.55#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:13.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:13.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:13.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:13.55#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:02:13.55#ibcon#first serial, iclass 33, count 0 2006.201.17:02:13.55#ibcon#enter sib2, iclass 33, count 0 2006.201.17:02:13.55#ibcon#flushed, iclass 33, count 0 2006.201.17:02:13.55#ibcon#about to write, iclass 33, count 0 2006.201.17:02:13.55#ibcon#wrote, iclass 33, count 0 2006.201.17:02:13.55#ibcon#about to read 3, iclass 33, count 0 2006.201.17:02:13.57#ibcon#read 3, iclass 33, count 0 2006.201.17:02:13.57#ibcon#about to read 4, iclass 33, count 0 2006.201.17:02:13.57#ibcon#read 4, iclass 33, count 0 2006.201.17:02:13.57#ibcon#about to read 5, iclass 33, count 0 2006.201.17:02:13.57#ibcon#read 5, iclass 33, count 0 2006.201.17:02:13.57#ibcon#about to read 6, iclass 33, count 0 2006.201.17:02:13.57#ibcon#read 6, iclass 33, count 0 2006.201.17:02:13.57#ibcon#end of sib2, iclass 33, count 0 2006.201.17:02:13.57#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:02:13.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:02:13.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.17:02:13.57#ibcon#*before write, iclass 33, count 0 2006.201.17:02:13.57#ibcon#enter sib2, iclass 33, count 0 2006.201.17:02:13.57#ibcon#flushed, iclass 33, count 0 2006.201.17:02:13.57#ibcon#about to write, iclass 33, count 0 2006.201.17:02:13.57#ibcon#wrote, iclass 33, count 0 2006.201.17:02:13.57#ibcon#about to read 3, iclass 33, count 0 2006.201.17:02:13.61#ibcon#read 3, iclass 33, count 0 2006.201.17:02:13.61#ibcon#about to read 4, iclass 33, count 0 2006.201.17:02:13.61#ibcon#read 4, iclass 33, count 0 2006.201.17:02:13.61#ibcon#about to read 5, iclass 33, count 0 2006.201.17:02:13.61#ibcon#read 5, iclass 33, count 0 2006.201.17:02:13.61#ibcon#about to read 6, iclass 33, count 0 2006.201.17:02:13.61#ibcon#read 6, iclass 33, count 0 2006.201.17:02:13.61#ibcon#end of sib2, iclass 33, count 0 2006.201.17:02:13.61#ibcon#*after write, iclass 33, count 0 2006.201.17:02:13.61#ibcon#*before return 0, iclass 33, count 0 2006.201.17:02:13.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:13.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:02:13.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:02:13.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:02:13.61$vck44/vb=4,5 2006.201.17:02:13.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.17:02:13.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.17:02:13.61#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:13.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:13.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:13.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:13.67#ibcon#enter wrdev, iclass 35, count 2 2006.201.17:02:13.67#ibcon#first serial, iclass 35, count 2 2006.201.17:02:13.67#ibcon#enter sib2, iclass 35, count 2 2006.201.17:02:13.67#ibcon#flushed, iclass 35, count 2 2006.201.17:02:13.67#ibcon#about to write, iclass 35, count 2 2006.201.17:02:13.67#ibcon#wrote, iclass 35, count 2 2006.201.17:02:13.67#ibcon#about to read 3, iclass 35, count 2 2006.201.17:02:13.69#ibcon#read 3, iclass 35, count 2 2006.201.17:02:13.69#ibcon#about to read 4, iclass 35, count 2 2006.201.17:02:13.69#ibcon#read 4, iclass 35, count 2 2006.201.17:02:13.69#ibcon#about to read 5, iclass 35, count 2 2006.201.17:02:13.69#ibcon#read 5, iclass 35, count 2 2006.201.17:02:13.69#ibcon#about to read 6, iclass 35, count 2 2006.201.17:02:13.69#ibcon#read 6, iclass 35, count 2 2006.201.17:02:13.69#ibcon#end of sib2, iclass 35, count 2 2006.201.17:02:13.69#ibcon#*mode == 0, iclass 35, count 2 2006.201.17:02:13.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.17:02:13.69#ibcon#[27=AT04-05\r\n] 2006.201.17:02:13.69#ibcon#*before write, iclass 35, count 2 2006.201.17:02:13.69#ibcon#enter sib2, iclass 35, count 2 2006.201.17:02:13.69#ibcon#flushed, iclass 35, count 2 2006.201.17:02:13.69#ibcon#about to write, iclass 35, count 2 2006.201.17:02:13.69#ibcon#wrote, iclass 35, count 2 2006.201.17:02:13.69#ibcon#about to read 3, iclass 35, count 2 2006.201.17:02:13.72#ibcon#read 3, iclass 35, count 2 2006.201.17:02:13.72#ibcon#about to read 4, iclass 35, count 2 2006.201.17:02:13.72#ibcon#read 4, iclass 35, count 2 2006.201.17:02:13.72#ibcon#about to read 5, iclass 35, count 2 2006.201.17:02:13.72#ibcon#read 5, iclass 35, count 2 2006.201.17:02:13.72#ibcon#about to read 6, iclass 35, count 2 2006.201.17:02:13.72#ibcon#read 6, iclass 35, count 2 2006.201.17:02:13.72#ibcon#end of sib2, iclass 35, count 2 2006.201.17:02:13.72#ibcon#*after write, iclass 35, count 2 2006.201.17:02:13.72#ibcon#*before return 0, iclass 35, count 2 2006.201.17:02:13.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:13.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:02:13.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.17:02:13.72#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:13.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:13.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:13.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:13.84#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:02:13.84#ibcon#first serial, iclass 35, count 0 2006.201.17:02:13.84#ibcon#enter sib2, iclass 35, count 0 2006.201.17:02:13.84#ibcon#flushed, iclass 35, count 0 2006.201.17:02:13.84#ibcon#about to write, iclass 35, count 0 2006.201.17:02:13.84#ibcon#wrote, iclass 35, count 0 2006.201.17:02:13.84#ibcon#about to read 3, iclass 35, count 0 2006.201.17:02:13.86#ibcon#read 3, iclass 35, count 0 2006.201.17:02:13.86#ibcon#about to read 4, iclass 35, count 0 2006.201.17:02:13.86#ibcon#read 4, iclass 35, count 0 2006.201.17:02:13.86#ibcon#about to read 5, iclass 35, count 0 2006.201.17:02:13.86#ibcon#read 5, iclass 35, count 0 2006.201.17:02:13.86#ibcon#about to read 6, iclass 35, count 0 2006.201.17:02:13.86#ibcon#read 6, iclass 35, count 0 2006.201.17:02:13.86#ibcon#end of sib2, iclass 35, count 0 2006.201.17:02:13.86#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:02:13.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:02:13.86#ibcon#[27=USB\r\n] 2006.201.17:02:13.86#ibcon#*before write, iclass 35, count 0 2006.201.17:02:13.86#ibcon#enter sib2, iclass 35, count 0 2006.201.17:02:13.86#ibcon#flushed, iclass 35, count 0 2006.201.17:02:13.86#ibcon#about to write, iclass 35, count 0 2006.201.17:02:13.86#ibcon#wrote, iclass 35, count 0 2006.201.17:02:13.86#ibcon#about to read 3, iclass 35, count 0 2006.201.17:02:13.89#ibcon#read 3, iclass 35, count 0 2006.201.17:02:13.89#ibcon#about to read 4, iclass 35, count 0 2006.201.17:02:13.89#ibcon#read 4, iclass 35, count 0 2006.201.17:02:13.89#ibcon#about to read 5, iclass 35, count 0 2006.201.17:02:13.89#ibcon#read 5, iclass 35, count 0 2006.201.17:02:13.89#ibcon#about to read 6, iclass 35, count 0 2006.201.17:02:13.89#ibcon#read 6, iclass 35, count 0 2006.201.17:02:13.89#ibcon#end of sib2, iclass 35, count 0 2006.201.17:02:13.89#ibcon#*after write, iclass 35, count 0 2006.201.17:02:13.89#ibcon#*before return 0, iclass 35, count 0 2006.201.17:02:13.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:13.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:02:13.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:02:13.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:02:13.89$vck44/vblo=5,709.99 2006.201.17:02:13.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.17:02:13.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.17:02:13.89#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:13.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:13.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:13.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:13.89#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:02:13.89#ibcon#first serial, iclass 37, count 0 2006.201.17:02:13.89#ibcon#enter sib2, iclass 37, count 0 2006.201.17:02:13.89#ibcon#flushed, iclass 37, count 0 2006.201.17:02:13.89#ibcon#about to write, iclass 37, count 0 2006.201.17:02:13.89#ibcon#wrote, iclass 37, count 0 2006.201.17:02:13.89#ibcon#about to read 3, iclass 37, count 0 2006.201.17:02:13.91#ibcon#read 3, iclass 37, count 0 2006.201.17:02:13.91#ibcon#about to read 4, iclass 37, count 0 2006.201.17:02:13.91#ibcon#read 4, iclass 37, count 0 2006.201.17:02:13.91#ibcon#about to read 5, iclass 37, count 0 2006.201.17:02:13.91#ibcon#read 5, iclass 37, count 0 2006.201.17:02:13.91#ibcon#about to read 6, iclass 37, count 0 2006.201.17:02:13.91#ibcon#read 6, iclass 37, count 0 2006.201.17:02:13.91#ibcon#end of sib2, iclass 37, count 0 2006.201.17:02:13.91#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:02:13.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:02:13.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.17:02:13.91#ibcon#*before write, iclass 37, count 0 2006.201.17:02:13.91#ibcon#enter sib2, iclass 37, count 0 2006.201.17:02:13.91#ibcon#flushed, iclass 37, count 0 2006.201.17:02:13.91#ibcon#about to write, iclass 37, count 0 2006.201.17:02:13.91#ibcon#wrote, iclass 37, count 0 2006.201.17:02:13.91#ibcon#about to read 3, iclass 37, count 0 2006.201.17:02:13.95#ibcon#read 3, iclass 37, count 0 2006.201.17:02:13.95#ibcon#about to read 4, iclass 37, count 0 2006.201.17:02:13.95#ibcon#read 4, iclass 37, count 0 2006.201.17:02:13.95#ibcon#about to read 5, iclass 37, count 0 2006.201.17:02:13.95#ibcon#read 5, iclass 37, count 0 2006.201.17:02:13.95#ibcon#about to read 6, iclass 37, count 0 2006.201.17:02:13.95#ibcon#read 6, iclass 37, count 0 2006.201.17:02:13.95#ibcon#end of sib2, iclass 37, count 0 2006.201.17:02:13.95#ibcon#*after write, iclass 37, count 0 2006.201.17:02:13.95#ibcon#*before return 0, iclass 37, count 0 2006.201.17:02:13.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:13.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:02:13.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:02:13.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:02:13.95$vck44/vb=5,4 2006.201.17:02:13.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.17:02:13.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.17:02:13.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:13.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:14.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:14.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:14.01#ibcon#enter wrdev, iclass 39, count 2 2006.201.17:02:14.01#ibcon#first serial, iclass 39, count 2 2006.201.17:02:14.01#ibcon#enter sib2, iclass 39, count 2 2006.201.17:02:14.01#ibcon#flushed, iclass 39, count 2 2006.201.17:02:14.01#ibcon#about to write, iclass 39, count 2 2006.201.17:02:14.01#ibcon#wrote, iclass 39, count 2 2006.201.17:02:14.01#ibcon#about to read 3, iclass 39, count 2 2006.201.17:02:14.03#ibcon#read 3, iclass 39, count 2 2006.201.17:02:14.03#ibcon#about to read 4, iclass 39, count 2 2006.201.17:02:14.03#ibcon#read 4, iclass 39, count 2 2006.201.17:02:14.03#ibcon#about to read 5, iclass 39, count 2 2006.201.17:02:14.03#ibcon#read 5, iclass 39, count 2 2006.201.17:02:14.03#ibcon#about to read 6, iclass 39, count 2 2006.201.17:02:14.03#ibcon#read 6, iclass 39, count 2 2006.201.17:02:14.03#ibcon#end of sib2, iclass 39, count 2 2006.201.17:02:14.03#ibcon#*mode == 0, iclass 39, count 2 2006.201.17:02:14.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.17:02:14.03#ibcon#[27=AT05-04\r\n] 2006.201.17:02:14.03#ibcon#*before write, iclass 39, count 2 2006.201.17:02:14.03#ibcon#enter sib2, iclass 39, count 2 2006.201.17:02:14.03#ibcon#flushed, iclass 39, count 2 2006.201.17:02:14.03#ibcon#about to write, iclass 39, count 2 2006.201.17:02:14.03#ibcon#wrote, iclass 39, count 2 2006.201.17:02:14.03#ibcon#about to read 3, iclass 39, count 2 2006.201.17:02:14.06#ibcon#read 3, iclass 39, count 2 2006.201.17:02:14.06#ibcon#about to read 4, iclass 39, count 2 2006.201.17:02:14.06#ibcon#read 4, iclass 39, count 2 2006.201.17:02:14.06#ibcon#about to read 5, iclass 39, count 2 2006.201.17:02:14.06#ibcon#read 5, iclass 39, count 2 2006.201.17:02:14.06#ibcon#about to read 6, iclass 39, count 2 2006.201.17:02:14.06#ibcon#read 6, iclass 39, count 2 2006.201.17:02:14.06#ibcon#end of sib2, iclass 39, count 2 2006.201.17:02:14.06#ibcon#*after write, iclass 39, count 2 2006.201.17:02:14.06#ibcon#*before return 0, iclass 39, count 2 2006.201.17:02:14.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:14.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:02:14.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.17:02:14.06#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:14.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:14.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:14.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:14.18#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:02:14.18#ibcon#first serial, iclass 39, count 0 2006.201.17:02:14.18#ibcon#enter sib2, iclass 39, count 0 2006.201.17:02:14.18#ibcon#flushed, iclass 39, count 0 2006.201.17:02:14.18#ibcon#about to write, iclass 39, count 0 2006.201.17:02:14.18#ibcon#wrote, iclass 39, count 0 2006.201.17:02:14.18#ibcon#about to read 3, iclass 39, count 0 2006.201.17:02:14.21#ibcon#read 3, iclass 39, count 0 2006.201.17:02:14.21#ibcon#about to read 4, iclass 39, count 0 2006.201.17:02:14.21#ibcon#read 4, iclass 39, count 0 2006.201.17:02:14.21#ibcon#about to read 5, iclass 39, count 0 2006.201.17:02:14.21#ibcon#read 5, iclass 39, count 0 2006.201.17:02:14.21#ibcon#about to read 6, iclass 39, count 0 2006.201.17:02:14.21#ibcon#read 6, iclass 39, count 0 2006.201.17:02:14.21#ibcon#end of sib2, iclass 39, count 0 2006.201.17:02:14.21#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:02:14.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:02:14.21#ibcon#[27=USB\r\n] 2006.201.17:02:14.21#ibcon#*before write, iclass 39, count 0 2006.201.17:02:14.21#ibcon#enter sib2, iclass 39, count 0 2006.201.17:02:14.21#ibcon#flushed, iclass 39, count 0 2006.201.17:02:14.21#ibcon#about to write, iclass 39, count 0 2006.201.17:02:14.21#ibcon#wrote, iclass 39, count 0 2006.201.17:02:14.21#ibcon#about to read 3, iclass 39, count 0 2006.201.17:02:14.24#ibcon#read 3, iclass 39, count 0 2006.201.17:02:14.24#ibcon#about to read 4, iclass 39, count 0 2006.201.17:02:14.24#ibcon#read 4, iclass 39, count 0 2006.201.17:02:14.24#ibcon#about to read 5, iclass 39, count 0 2006.201.17:02:14.24#ibcon#read 5, iclass 39, count 0 2006.201.17:02:14.24#ibcon#about to read 6, iclass 39, count 0 2006.201.17:02:14.24#ibcon#read 6, iclass 39, count 0 2006.201.17:02:14.24#ibcon#end of sib2, iclass 39, count 0 2006.201.17:02:14.24#ibcon#*after write, iclass 39, count 0 2006.201.17:02:14.24#ibcon#*before return 0, iclass 39, count 0 2006.201.17:02:14.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:14.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:02:14.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:02:14.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:02:14.24$vck44/vblo=6,719.99 2006.201.17:02:14.24#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.17:02:14.24#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.17:02:14.24#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:14.24#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:14.24#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:14.24#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:14.24#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:02:14.24#ibcon#first serial, iclass 2, count 0 2006.201.17:02:14.24#ibcon#enter sib2, iclass 2, count 0 2006.201.17:02:14.24#ibcon#flushed, iclass 2, count 0 2006.201.17:02:14.24#ibcon#about to write, iclass 2, count 0 2006.201.17:02:14.24#ibcon#wrote, iclass 2, count 0 2006.201.17:02:14.24#ibcon#about to read 3, iclass 2, count 0 2006.201.17:02:14.26#ibcon#read 3, iclass 2, count 0 2006.201.17:02:14.26#ibcon#about to read 4, iclass 2, count 0 2006.201.17:02:14.26#ibcon#read 4, iclass 2, count 0 2006.201.17:02:14.26#ibcon#about to read 5, iclass 2, count 0 2006.201.17:02:14.26#ibcon#read 5, iclass 2, count 0 2006.201.17:02:14.26#ibcon#about to read 6, iclass 2, count 0 2006.201.17:02:14.26#ibcon#read 6, iclass 2, count 0 2006.201.17:02:14.26#ibcon#end of sib2, iclass 2, count 0 2006.201.17:02:14.26#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:02:14.26#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:02:14.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.17:02:14.26#ibcon#*before write, iclass 2, count 0 2006.201.17:02:14.26#ibcon#enter sib2, iclass 2, count 0 2006.201.17:02:14.26#ibcon#flushed, iclass 2, count 0 2006.201.17:02:14.26#ibcon#about to write, iclass 2, count 0 2006.201.17:02:14.26#ibcon#wrote, iclass 2, count 0 2006.201.17:02:14.26#ibcon#about to read 3, iclass 2, count 0 2006.201.17:02:14.30#ibcon#read 3, iclass 2, count 0 2006.201.17:02:14.30#ibcon#about to read 4, iclass 2, count 0 2006.201.17:02:14.30#ibcon#read 4, iclass 2, count 0 2006.201.17:02:14.30#ibcon#about to read 5, iclass 2, count 0 2006.201.17:02:14.30#ibcon#read 5, iclass 2, count 0 2006.201.17:02:14.30#ibcon#about to read 6, iclass 2, count 0 2006.201.17:02:14.30#ibcon#read 6, iclass 2, count 0 2006.201.17:02:14.30#ibcon#end of sib2, iclass 2, count 0 2006.201.17:02:14.30#ibcon#*after write, iclass 2, count 0 2006.201.17:02:14.30#ibcon#*before return 0, iclass 2, count 0 2006.201.17:02:14.30#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:14.30#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:02:14.30#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:02:14.30#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:02:14.30$vck44/vb=6,4 2006.201.17:02:14.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.17:02:14.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.17:02:14.30#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:14.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:14.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:14.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:14.36#ibcon#enter wrdev, iclass 5, count 2 2006.201.17:02:14.36#ibcon#first serial, iclass 5, count 2 2006.201.17:02:14.36#ibcon#enter sib2, iclass 5, count 2 2006.201.17:02:14.36#ibcon#flushed, iclass 5, count 2 2006.201.17:02:14.36#ibcon#about to write, iclass 5, count 2 2006.201.17:02:14.36#ibcon#wrote, iclass 5, count 2 2006.201.17:02:14.36#ibcon#about to read 3, iclass 5, count 2 2006.201.17:02:14.38#ibcon#read 3, iclass 5, count 2 2006.201.17:02:14.38#ibcon#about to read 4, iclass 5, count 2 2006.201.17:02:14.38#ibcon#read 4, iclass 5, count 2 2006.201.17:02:14.38#ibcon#about to read 5, iclass 5, count 2 2006.201.17:02:14.38#ibcon#read 5, iclass 5, count 2 2006.201.17:02:14.38#ibcon#about to read 6, iclass 5, count 2 2006.201.17:02:14.38#ibcon#read 6, iclass 5, count 2 2006.201.17:02:14.38#ibcon#end of sib2, iclass 5, count 2 2006.201.17:02:14.38#ibcon#*mode == 0, iclass 5, count 2 2006.201.17:02:14.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.17:02:14.38#ibcon#[27=AT06-04\r\n] 2006.201.17:02:14.38#ibcon#*before write, iclass 5, count 2 2006.201.17:02:14.38#ibcon#enter sib2, iclass 5, count 2 2006.201.17:02:14.38#ibcon#flushed, iclass 5, count 2 2006.201.17:02:14.38#ibcon#about to write, iclass 5, count 2 2006.201.17:02:14.38#ibcon#wrote, iclass 5, count 2 2006.201.17:02:14.38#ibcon#about to read 3, iclass 5, count 2 2006.201.17:02:14.41#ibcon#read 3, iclass 5, count 2 2006.201.17:02:14.41#ibcon#about to read 4, iclass 5, count 2 2006.201.17:02:14.41#ibcon#read 4, iclass 5, count 2 2006.201.17:02:14.41#ibcon#about to read 5, iclass 5, count 2 2006.201.17:02:14.41#ibcon#read 5, iclass 5, count 2 2006.201.17:02:14.41#ibcon#about to read 6, iclass 5, count 2 2006.201.17:02:14.41#ibcon#read 6, iclass 5, count 2 2006.201.17:02:14.41#ibcon#end of sib2, iclass 5, count 2 2006.201.17:02:14.41#ibcon#*after write, iclass 5, count 2 2006.201.17:02:14.41#ibcon#*before return 0, iclass 5, count 2 2006.201.17:02:14.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:14.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:02:14.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.17:02:14.41#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:14.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:14.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:14.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:14.53#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:02:14.53#ibcon#first serial, iclass 5, count 0 2006.201.17:02:14.53#ibcon#enter sib2, iclass 5, count 0 2006.201.17:02:14.53#ibcon#flushed, iclass 5, count 0 2006.201.17:02:14.53#ibcon#about to write, iclass 5, count 0 2006.201.17:02:14.53#ibcon#wrote, iclass 5, count 0 2006.201.17:02:14.53#ibcon#about to read 3, iclass 5, count 0 2006.201.17:02:14.55#ibcon#read 3, iclass 5, count 0 2006.201.17:02:14.55#ibcon#about to read 4, iclass 5, count 0 2006.201.17:02:14.55#ibcon#read 4, iclass 5, count 0 2006.201.17:02:14.55#ibcon#about to read 5, iclass 5, count 0 2006.201.17:02:14.55#ibcon#read 5, iclass 5, count 0 2006.201.17:02:14.55#ibcon#about to read 6, iclass 5, count 0 2006.201.17:02:14.55#ibcon#read 6, iclass 5, count 0 2006.201.17:02:14.55#ibcon#end of sib2, iclass 5, count 0 2006.201.17:02:14.55#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:02:14.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:02:14.55#ibcon#[27=USB\r\n] 2006.201.17:02:14.55#ibcon#*before write, iclass 5, count 0 2006.201.17:02:14.55#ibcon#enter sib2, iclass 5, count 0 2006.201.17:02:14.55#ibcon#flushed, iclass 5, count 0 2006.201.17:02:14.55#ibcon#about to write, iclass 5, count 0 2006.201.17:02:14.55#ibcon#wrote, iclass 5, count 0 2006.201.17:02:14.55#ibcon#about to read 3, iclass 5, count 0 2006.201.17:02:14.58#ibcon#read 3, iclass 5, count 0 2006.201.17:02:14.58#ibcon#about to read 4, iclass 5, count 0 2006.201.17:02:14.58#ibcon#read 4, iclass 5, count 0 2006.201.17:02:14.58#ibcon#about to read 5, iclass 5, count 0 2006.201.17:02:14.58#ibcon#read 5, iclass 5, count 0 2006.201.17:02:14.58#ibcon#about to read 6, iclass 5, count 0 2006.201.17:02:14.58#ibcon#read 6, iclass 5, count 0 2006.201.17:02:14.58#ibcon#end of sib2, iclass 5, count 0 2006.201.17:02:14.58#ibcon#*after write, iclass 5, count 0 2006.201.17:02:14.58#ibcon#*before return 0, iclass 5, count 0 2006.201.17:02:14.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:14.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:02:14.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:02:14.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:02:14.58$vck44/vblo=7,734.99 2006.201.17:02:14.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.17:02:14.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.17:02:14.58#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:14.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:14.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:14.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:14.58#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:02:14.58#ibcon#first serial, iclass 7, count 0 2006.201.17:02:14.58#ibcon#enter sib2, iclass 7, count 0 2006.201.17:02:14.58#ibcon#flushed, iclass 7, count 0 2006.201.17:02:14.58#ibcon#about to write, iclass 7, count 0 2006.201.17:02:14.58#ibcon#wrote, iclass 7, count 0 2006.201.17:02:14.58#ibcon#about to read 3, iclass 7, count 0 2006.201.17:02:14.60#ibcon#read 3, iclass 7, count 0 2006.201.17:02:14.60#ibcon#about to read 4, iclass 7, count 0 2006.201.17:02:14.60#ibcon#read 4, iclass 7, count 0 2006.201.17:02:14.60#ibcon#about to read 5, iclass 7, count 0 2006.201.17:02:14.60#ibcon#read 5, iclass 7, count 0 2006.201.17:02:14.60#ibcon#about to read 6, iclass 7, count 0 2006.201.17:02:14.60#ibcon#read 6, iclass 7, count 0 2006.201.17:02:14.60#ibcon#end of sib2, iclass 7, count 0 2006.201.17:02:14.60#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:02:14.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:02:14.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.17:02:14.60#ibcon#*before write, iclass 7, count 0 2006.201.17:02:14.60#ibcon#enter sib2, iclass 7, count 0 2006.201.17:02:14.60#ibcon#flushed, iclass 7, count 0 2006.201.17:02:14.60#ibcon#about to write, iclass 7, count 0 2006.201.17:02:14.60#ibcon#wrote, iclass 7, count 0 2006.201.17:02:14.60#ibcon#about to read 3, iclass 7, count 0 2006.201.17:02:14.64#ibcon#read 3, iclass 7, count 0 2006.201.17:02:14.64#ibcon#about to read 4, iclass 7, count 0 2006.201.17:02:14.64#ibcon#read 4, iclass 7, count 0 2006.201.17:02:14.64#ibcon#about to read 5, iclass 7, count 0 2006.201.17:02:14.64#ibcon#read 5, iclass 7, count 0 2006.201.17:02:14.64#ibcon#about to read 6, iclass 7, count 0 2006.201.17:02:14.64#ibcon#read 6, iclass 7, count 0 2006.201.17:02:14.64#ibcon#end of sib2, iclass 7, count 0 2006.201.17:02:14.64#ibcon#*after write, iclass 7, count 0 2006.201.17:02:14.64#ibcon#*before return 0, iclass 7, count 0 2006.201.17:02:14.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:14.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:02:14.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:02:14.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:02:14.64$vck44/vb=7,4 2006.201.17:02:14.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.17:02:14.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.17:02:14.64#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:14.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:14.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:14.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:14.70#ibcon#enter wrdev, iclass 11, count 2 2006.201.17:02:14.70#ibcon#first serial, iclass 11, count 2 2006.201.17:02:14.70#ibcon#enter sib2, iclass 11, count 2 2006.201.17:02:14.70#ibcon#flushed, iclass 11, count 2 2006.201.17:02:14.70#ibcon#about to write, iclass 11, count 2 2006.201.17:02:14.70#ibcon#wrote, iclass 11, count 2 2006.201.17:02:14.70#ibcon#about to read 3, iclass 11, count 2 2006.201.17:02:14.72#ibcon#read 3, iclass 11, count 2 2006.201.17:02:14.72#ibcon#about to read 4, iclass 11, count 2 2006.201.17:02:14.72#ibcon#read 4, iclass 11, count 2 2006.201.17:02:14.72#ibcon#about to read 5, iclass 11, count 2 2006.201.17:02:14.72#ibcon#read 5, iclass 11, count 2 2006.201.17:02:14.72#ibcon#about to read 6, iclass 11, count 2 2006.201.17:02:14.72#ibcon#read 6, iclass 11, count 2 2006.201.17:02:14.72#ibcon#end of sib2, iclass 11, count 2 2006.201.17:02:14.72#ibcon#*mode == 0, iclass 11, count 2 2006.201.17:02:14.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.17:02:14.72#ibcon#[27=AT07-04\r\n] 2006.201.17:02:14.72#ibcon#*before write, iclass 11, count 2 2006.201.17:02:14.72#ibcon#enter sib2, iclass 11, count 2 2006.201.17:02:14.72#ibcon#flushed, iclass 11, count 2 2006.201.17:02:14.72#ibcon#about to write, iclass 11, count 2 2006.201.17:02:14.72#ibcon#wrote, iclass 11, count 2 2006.201.17:02:14.72#ibcon#about to read 3, iclass 11, count 2 2006.201.17:02:14.75#ibcon#read 3, iclass 11, count 2 2006.201.17:02:14.75#ibcon#about to read 4, iclass 11, count 2 2006.201.17:02:14.75#ibcon#read 4, iclass 11, count 2 2006.201.17:02:14.75#ibcon#about to read 5, iclass 11, count 2 2006.201.17:02:14.75#ibcon#read 5, iclass 11, count 2 2006.201.17:02:14.75#ibcon#about to read 6, iclass 11, count 2 2006.201.17:02:14.75#ibcon#read 6, iclass 11, count 2 2006.201.17:02:14.75#ibcon#end of sib2, iclass 11, count 2 2006.201.17:02:14.75#ibcon#*after write, iclass 11, count 2 2006.201.17:02:14.75#ibcon#*before return 0, iclass 11, count 2 2006.201.17:02:14.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:14.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:02:14.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.17:02:14.75#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:14.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:14.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:14.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:14.87#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:02:14.87#ibcon#first serial, iclass 11, count 0 2006.201.17:02:14.87#ibcon#enter sib2, iclass 11, count 0 2006.201.17:02:14.87#ibcon#flushed, iclass 11, count 0 2006.201.17:02:14.87#ibcon#about to write, iclass 11, count 0 2006.201.17:02:14.87#ibcon#wrote, iclass 11, count 0 2006.201.17:02:14.87#ibcon#about to read 3, iclass 11, count 0 2006.201.17:02:14.89#ibcon#read 3, iclass 11, count 0 2006.201.17:02:14.89#ibcon#about to read 4, iclass 11, count 0 2006.201.17:02:14.89#ibcon#read 4, iclass 11, count 0 2006.201.17:02:14.89#ibcon#about to read 5, iclass 11, count 0 2006.201.17:02:14.89#ibcon#read 5, iclass 11, count 0 2006.201.17:02:14.89#ibcon#about to read 6, iclass 11, count 0 2006.201.17:02:14.89#ibcon#read 6, iclass 11, count 0 2006.201.17:02:14.89#ibcon#end of sib2, iclass 11, count 0 2006.201.17:02:14.89#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:02:14.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:02:14.89#ibcon#[27=USB\r\n] 2006.201.17:02:14.89#ibcon#*before write, iclass 11, count 0 2006.201.17:02:14.89#ibcon#enter sib2, iclass 11, count 0 2006.201.17:02:14.89#ibcon#flushed, iclass 11, count 0 2006.201.17:02:14.89#ibcon#about to write, iclass 11, count 0 2006.201.17:02:14.89#ibcon#wrote, iclass 11, count 0 2006.201.17:02:14.89#ibcon#about to read 3, iclass 11, count 0 2006.201.17:02:14.92#ibcon#read 3, iclass 11, count 0 2006.201.17:02:14.92#ibcon#about to read 4, iclass 11, count 0 2006.201.17:02:14.92#ibcon#read 4, iclass 11, count 0 2006.201.17:02:14.92#ibcon#about to read 5, iclass 11, count 0 2006.201.17:02:14.92#ibcon#read 5, iclass 11, count 0 2006.201.17:02:14.92#ibcon#about to read 6, iclass 11, count 0 2006.201.17:02:14.92#ibcon#read 6, iclass 11, count 0 2006.201.17:02:14.92#ibcon#end of sib2, iclass 11, count 0 2006.201.17:02:14.92#ibcon#*after write, iclass 11, count 0 2006.201.17:02:14.92#ibcon#*before return 0, iclass 11, count 0 2006.201.17:02:14.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:14.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:02:14.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:02:14.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:02:14.92$vck44/vblo=8,744.99 2006.201.17:02:14.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.17:02:14.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.17:02:14.92#ibcon#ireg 17 cls_cnt 0 2006.201.17:02:14.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:14.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:14.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:14.92#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:02:14.92#ibcon#first serial, iclass 13, count 0 2006.201.17:02:14.92#ibcon#enter sib2, iclass 13, count 0 2006.201.17:02:14.92#ibcon#flushed, iclass 13, count 0 2006.201.17:02:14.92#ibcon#about to write, iclass 13, count 0 2006.201.17:02:14.92#ibcon#wrote, iclass 13, count 0 2006.201.17:02:14.92#ibcon#about to read 3, iclass 13, count 0 2006.201.17:02:14.94#ibcon#read 3, iclass 13, count 0 2006.201.17:02:14.94#ibcon#about to read 4, iclass 13, count 0 2006.201.17:02:14.94#ibcon#read 4, iclass 13, count 0 2006.201.17:02:14.94#ibcon#about to read 5, iclass 13, count 0 2006.201.17:02:14.94#ibcon#read 5, iclass 13, count 0 2006.201.17:02:14.94#ibcon#about to read 6, iclass 13, count 0 2006.201.17:02:14.94#ibcon#read 6, iclass 13, count 0 2006.201.17:02:14.94#ibcon#end of sib2, iclass 13, count 0 2006.201.17:02:14.94#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:02:14.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:02:14.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.17:02:14.94#ibcon#*before write, iclass 13, count 0 2006.201.17:02:14.94#ibcon#enter sib2, iclass 13, count 0 2006.201.17:02:14.94#ibcon#flushed, iclass 13, count 0 2006.201.17:02:14.94#ibcon#about to write, iclass 13, count 0 2006.201.17:02:14.94#ibcon#wrote, iclass 13, count 0 2006.201.17:02:14.94#ibcon#about to read 3, iclass 13, count 0 2006.201.17:02:14.98#ibcon#read 3, iclass 13, count 0 2006.201.17:02:14.98#ibcon#about to read 4, iclass 13, count 0 2006.201.17:02:14.98#ibcon#read 4, iclass 13, count 0 2006.201.17:02:14.98#ibcon#about to read 5, iclass 13, count 0 2006.201.17:02:14.98#ibcon#read 5, iclass 13, count 0 2006.201.17:02:14.98#ibcon#about to read 6, iclass 13, count 0 2006.201.17:02:14.98#ibcon#read 6, iclass 13, count 0 2006.201.17:02:14.98#ibcon#end of sib2, iclass 13, count 0 2006.201.17:02:14.98#ibcon#*after write, iclass 13, count 0 2006.201.17:02:14.98#ibcon#*before return 0, iclass 13, count 0 2006.201.17:02:14.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:14.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:02:14.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:02:14.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:02:14.98$vck44/vb=8,4 2006.201.17:02:14.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.17:02:14.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.17:02:14.98#ibcon#ireg 11 cls_cnt 2 2006.201.17:02:14.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:15.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:15.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:15.04#ibcon#enter wrdev, iclass 15, count 2 2006.201.17:02:15.04#ibcon#first serial, iclass 15, count 2 2006.201.17:02:15.04#ibcon#enter sib2, iclass 15, count 2 2006.201.17:02:15.04#ibcon#flushed, iclass 15, count 2 2006.201.17:02:15.04#ibcon#about to write, iclass 15, count 2 2006.201.17:02:15.04#ibcon#wrote, iclass 15, count 2 2006.201.17:02:15.04#ibcon#about to read 3, iclass 15, count 2 2006.201.17:02:15.06#ibcon#read 3, iclass 15, count 2 2006.201.17:02:15.06#ibcon#about to read 4, iclass 15, count 2 2006.201.17:02:15.06#ibcon#read 4, iclass 15, count 2 2006.201.17:02:15.06#ibcon#about to read 5, iclass 15, count 2 2006.201.17:02:15.06#ibcon#read 5, iclass 15, count 2 2006.201.17:02:15.06#ibcon#about to read 6, iclass 15, count 2 2006.201.17:02:15.06#ibcon#read 6, iclass 15, count 2 2006.201.17:02:15.06#ibcon#end of sib2, iclass 15, count 2 2006.201.17:02:15.06#ibcon#*mode == 0, iclass 15, count 2 2006.201.17:02:15.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.17:02:15.06#ibcon#[27=AT08-04\r\n] 2006.201.17:02:15.06#ibcon#*before write, iclass 15, count 2 2006.201.17:02:15.06#ibcon#enter sib2, iclass 15, count 2 2006.201.17:02:15.06#ibcon#flushed, iclass 15, count 2 2006.201.17:02:15.06#ibcon#about to write, iclass 15, count 2 2006.201.17:02:15.06#ibcon#wrote, iclass 15, count 2 2006.201.17:02:15.06#ibcon#about to read 3, iclass 15, count 2 2006.201.17:02:15.09#ibcon#read 3, iclass 15, count 2 2006.201.17:02:15.09#ibcon#about to read 4, iclass 15, count 2 2006.201.17:02:15.09#ibcon#read 4, iclass 15, count 2 2006.201.17:02:15.09#ibcon#about to read 5, iclass 15, count 2 2006.201.17:02:15.09#ibcon#read 5, iclass 15, count 2 2006.201.17:02:15.09#ibcon#about to read 6, iclass 15, count 2 2006.201.17:02:15.09#ibcon#read 6, iclass 15, count 2 2006.201.17:02:15.09#ibcon#end of sib2, iclass 15, count 2 2006.201.17:02:15.09#ibcon#*after write, iclass 15, count 2 2006.201.17:02:15.09#ibcon#*before return 0, iclass 15, count 2 2006.201.17:02:15.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:15.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:02:15.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.17:02:15.09#ibcon#ireg 7 cls_cnt 0 2006.201.17:02:15.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:15.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:15.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:15.21#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:02:15.21#ibcon#first serial, iclass 15, count 0 2006.201.17:02:15.21#ibcon#enter sib2, iclass 15, count 0 2006.201.17:02:15.21#ibcon#flushed, iclass 15, count 0 2006.201.17:02:15.21#ibcon#about to write, iclass 15, count 0 2006.201.17:02:15.21#ibcon#wrote, iclass 15, count 0 2006.201.17:02:15.21#ibcon#about to read 3, iclass 15, count 0 2006.201.17:02:15.24#ibcon#read 3, iclass 15, count 0 2006.201.17:02:15.24#ibcon#about to read 4, iclass 15, count 0 2006.201.17:02:15.24#ibcon#read 4, iclass 15, count 0 2006.201.17:02:15.24#ibcon#about to read 5, iclass 15, count 0 2006.201.17:02:15.24#ibcon#read 5, iclass 15, count 0 2006.201.17:02:15.24#ibcon#about to read 6, iclass 15, count 0 2006.201.17:02:15.24#ibcon#read 6, iclass 15, count 0 2006.201.17:02:15.24#ibcon#end of sib2, iclass 15, count 0 2006.201.17:02:15.24#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:02:15.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:02:15.24#ibcon#[27=USB\r\n] 2006.201.17:02:15.24#ibcon#*before write, iclass 15, count 0 2006.201.17:02:15.24#ibcon#enter sib2, iclass 15, count 0 2006.201.17:02:15.24#ibcon#flushed, iclass 15, count 0 2006.201.17:02:15.24#ibcon#about to write, iclass 15, count 0 2006.201.17:02:15.24#ibcon#wrote, iclass 15, count 0 2006.201.17:02:15.24#ibcon#about to read 3, iclass 15, count 0 2006.201.17:02:15.27#ibcon#read 3, iclass 15, count 0 2006.201.17:02:15.27#ibcon#about to read 4, iclass 15, count 0 2006.201.17:02:15.27#ibcon#read 4, iclass 15, count 0 2006.201.17:02:15.27#ibcon#about to read 5, iclass 15, count 0 2006.201.17:02:15.27#ibcon#read 5, iclass 15, count 0 2006.201.17:02:15.27#ibcon#about to read 6, iclass 15, count 0 2006.201.17:02:15.27#ibcon#read 6, iclass 15, count 0 2006.201.17:02:15.27#ibcon#end of sib2, iclass 15, count 0 2006.201.17:02:15.27#ibcon#*after write, iclass 15, count 0 2006.201.17:02:15.27#ibcon#*before return 0, iclass 15, count 0 2006.201.17:02:15.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:15.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:02:15.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:02:15.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:02:15.27$vck44/vabw=wide 2006.201.17:02:15.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.17:02:15.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.17:02:15.27#ibcon#ireg 8 cls_cnt 0 2006.201.17:02:15.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:15.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:15.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:15.27#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:02:15.27#ibcon#first serial, iclass 17, count 0 2006.201.17:02:15.27#ibcon#enter sib2, iclass 17, count 0 2006.201.17:02:15.27#ibcon#flushed, iclass 17, count 0 2006.201.17:02:15.27#ibcon#about to write, iclass 17, count 0 2006.201.17:02:15.27#ibcon#wrote, iclass 17, count 0 2006.201.17:02:15.27#ibcon#about to read 3, iclass 17, count 0 2006.201.17:02:15.29#ibcon#read 3, iclass 17, count 0 2006.201.17:02:15.29#ibcon#about to read 4, iclass 17, count 0 2006.201.17:02:15.29#ibcon#read 4, iclass 17, count 0 2006.201.17:02:15.29#ibcon#about to read 5, iclass 17, count 0 2006.201.17:02:15.29#ibcon#read 5, iclass 17, count 0 2006.201.17:02:15.29#ibcon#about to read 6, iclass 17, count 0 2006.201.17:02:15.29#ibcon#read 6, iclass 17, count 0 2006.201.17:02:15.29#ibcon#end of sib2, iclass 17, count 0 2006.201.17:02:15.29#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:02:15.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:02:15.29#ibcon#[25=BW32\r\n] 2006.201.17:02:15.29#ibcon#*before write, iclass 17, count 0 2006.201.17:02:15.29#ibcon#enter sib2, iclass 17, count 0 2006.201.17:02:15.29#ibcon#flushed, iclass 17, count 0 2006.201.17:02:15.29#ibcon#about to write, iclass 17, count 0 2006.201.17:02:15.29#ibcon#wrote, iclass 17, count 0 2006.201.17:02:15.29#ibcon#about to read 3, iclass 17, count 0 2006.201.17:02:15.32#ibcon#read 3, iclass 17, count 0 2006.201.17:02:15.32#ibcon#about to read 4, iclass 17, count 0 2006.201.17:02:15.32#ibcon#read 4, iclass 17, count 0 2006.201.17:02:15.32#ibcon#about to read 5, iclass 17, count 0 2006.201.17:02:15.32#ibcon#read 5, iclass 17, count 0 2006.201.17:02:15.32#ibcon#about to read 6, iclass 17, count 0 2006.201.17:02:15.32#ibcon#read 6, iclass 17, count 0 2006.201.17:02:15.32#ibcon#end of sib2, iclass 17, count 0 2006.201.17:02:15.32#ibcon#*after write, iclass 17, count 0 2006.201.17:02:15.32#ibcon#*before return 0, iclass 17, count 0 2006.201.17:02:15.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:15.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:02:15.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:02:15.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:02:15.32$vck44/vbbw=wide 2006.201.17:02:15.32#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.17:02:15.32#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.17:02:15.32#ibcon#ireg 8 cls_cnt 0 2006.201.17:02:15.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:02:15.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:02:15.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:02:15.39#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:02:15.39#ibcon#first serial, iclass 19, count 0 2006.201.17:02:15.39#ibcon#enter sib2, iclass 19, count 0 2006.201.17:02:15.39#ibcon#flushed, iclass 19, count 0 2006.201.17:02:15.39#ibcon#about to write, iclass 19, count 0 2006.201.17:02:15.39#ibcon#wrote, iclass 19, count 0 2006.201.17:02:15.39#ibcon#about to read 3, iclass 19, count 0 2006.201.17:02:15.41#ibcon#read 3, iclass 19, count 0 2006.201.17:02:15.41#ibcon#about to read 4, iclass 19, count 0 2006.201.17:02:15.41#ibcon#read 4, iclass 19, count 0 2006.201.17:02:15.41#ibcon#about to read 5, iclass 19, count 0 2006.201.17:02:15.41#ibcon#read 5, iclass 19, count 0 2006.201.17:02:15.41#ibcon#about to read 6, iclass 19, count 0 2006.201.17:02:15.41#ibcon#read 6, iclass 19, count 0 2006.201.17:02:15.41#ibcon#end of sib2, iclass 19, count 0 2006.201.17:02:15.41#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:02:15.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:02:15.41#ibcon#[27=BW32\r\n] 2006.201.17:02:15.41#ibcon#*before write, iclass 19, count 0 2006.201.17:02:15.41#ibcon#enter sib2, iclass 19, count 0 2006.201.17:02:15.41#ibcon#flushed, iclass 19, count 0 2006.201.17:02:15.41#ibcon#about to write, iclass 19, count 0 2006.201.17:02:15.41#ibcon#wrote, iclass 19, count 0 2006.201.17:02:15.41#ibcon#about to read 3, iclass 19, count 0 2006.201.17:02:15.44#ibcon#read 3, iclass 19, count 0 2006.201.17:02:15.44#ibcon#about to read 4, iclass 19, count 0 2006.201.17:02:15.44#ibcon#read 4, iclass 19, count 0 2006.201.17:02:15.44#ibcon#about to read 5, iclass 19, count 0 2006.201.17:02:15.44#ibcon#read 5, iclass 19, count 0 2006.201.17:02:15.44#ibcon#about to read 6, iclass 19, count 0 2006.201.17:02:15.44#ibcon#read 6, iclass 19, count 0 2006.201.17:02:15.44#ibcon#end of sib2, iclass 19, count 0 2006.201.17:02:15.44#ibcon#*after write, iclass 19, count 0 2006.201.17:02:15.44#ibcon#*before return 0, iclass 19, count 0 2006.201.17:02:15.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:02:15.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:02:15.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:02:15.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:02:15.44$setupk4/ifdk4 2006.201.17:02:15.44$ifdk4/lo= 2006.201.17:02:15.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.17:02:15.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.17:02:15.44$ifdk4/patch= 2006.201.17:02:15.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.17:02:15.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.17:02:15.44$setupk4/!*+20s 2006.201.17:02:18.84#abcon#<5=/00 0.2 0.6 20.791001002.6\r\n> 2006.201.17:02:18.86#abcon#{5=INTERFACE CLEAR} 2006.201.17:02:18.92#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:02:29.01#abcon#<5=/00 0.2 0.6 20.791001002.6\r\n> 2006.201.17:02:29.03#abcon#{5=INTERFACE CLEAR} 2006.201.17:02:29.09#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:02:29.89$setupk4/"tpicd 2006.201.17:02:29.89$setupk4/echo=off 2006.201.17:02:29.89$setupk4/xlog=off 2006.201.17:02:29.89:!2006.201.17:03:09 2006.201.17:02:49.13#trakl#Source acquired 2006.201.17:02:50.13#flagr#flagr/antenna,acquired 2006.201.17:03:09.00:preob 2006.201.17:03:09.13/onsource/TRACKING 2006.201.17:03:09.13:!2006.201.17:03:19 2006.201.17:03:19.00:"tape 2006.201.17:03:19.00:"st=record 2006.201.17:03:19.00:data_valid=on 2006.201.17:03:19.00:midob 2006.201.17:03:20.13/onsource/TRACKING 2006.201.17:03:20.13/wx/20.79,1002.6,100 2006.201.17:03:20.36/cable/+6.4773E-03 2006.201.17:03:21.45/va/01,08,usb,yes,33,35 2006.201.17:03:21.45/va/02,07,usb,yes,35,36 2006.201.17:03:21.45/va/03,08,usb,yes,32,33 2006.201.17:03:21.45/va/04,07,usb,yes,37,38 2006.201.17:03:21.45/va/05,04,usb,yes,32,33 2006.201.17:03:21.45/va/06,05,usb,yes,32,32 2006.201.17:03:21.45/va/07,05,usb,yes,32,33 2006.201.17:03:21.45/va/08,04,usb,yes,31,37 2006.201.17:03:21.68/valo/01,524.99,yes,locked 2006.201.17:03:21.68/valo/02,534.99,yes,locked 2006.201.17:03:21.68/valo/03,564.99,yes,locked 2006.201.17:03:21.68/valo/04,624.99,yes,locked 2006.201.17:03:21.68/valo/05,734.99,yes,locked 2006.201.17:03:21.68/valo/06,814.99,yes,locked 2006.201.17:03:21.68/valo/07,864.99,yes,locked 2006.201.17:03:21.68/valo/08,884.99,yes,locked 2006.201.17:03:22.77/vb/01,04,usb,yes,29,27 2006.201.17:03:22.77/vb/02,05,usb,yes,27,27 2006.201.17:03:22.77/vb/03,04,usb,yes,28,31 2006.201.17:03:22.77/vb/04,05,usb,yes,28,27 2006.201.17:03:22.77/vb/05,04,usb,yes,25,27 2006.201.17:03:22.77/vb/06,04,usb,yes,29,25 2006.201.17:03:22.77/vb/07,04,usb,yes,29,29 2006.201.17:03:22.77/vb/08,04,usb,yes,27,30 2006.201.17:03:23.01/vblo/01,629.99,yes,locked 2006.201.17:03:23.01/vblo/02,634.99,yes,locked 2006.201.17:03:23.01/vblo/03,649.99,yes,locked 2006.201.17:03:23.01/vblo/04,679.99,yes,locked 2006.201.17:03:23.01/vblo/05,709.99,yes,locked 2006.201.17:03:23.01/vblo/06,719.99,yes,locked 2006.201.17:03:23.01/vblo/07,734.99,yes,locked 2006.201.17:03:23.01/vblo/08,744.99,yes,locked 2006.201.17:03:23.16/vabw/8 2006.201.17:03:23.31/vbbw/8 2006.201.17:03:23.40/xfe/off,on,15.5 2006.201.17:03:23.78/ifatt/23,28,28,28 2006.201.17:03:24.05/fmout-gps/S +4.49E-07 2006.201.17:03:24.12:!2006.201.17:05:19 2006.201.17:05:19.00:data_valid=off 2006.201.17:05:19.00:"et 2006.201.17:05:19.00:!+3s 2006.201.17:05:22.02:"tape 2006.201.17:05:22.02:postob 2006.201.17:05:22.21/cable/+6.4776E-03 2006.201.17:05:22.21/wx/20.77,1002.6,100 2006.201.17:05:22.27/fmout-gps/S +4.50E-07 2006.201.17:05:22.27:scan_name=201-1710,jd0607,570 2006.201.17:05:22.27:source=0133+476,013658.59,475129.1,2000.0,cw 2006.201.17:05:23.14#flagr#flagr/antenna,new-source 2006.201.17:05:23.14:checkk5 2006.201.17:05:23.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.17:05:23.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.17:05:24.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.17:05:24.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.17:05:25.00/chk_obsdata//k5ts1/T2011703??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.17:05:25.37/chk_obsdata//k5ts2/T2011703??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.17:05:25.73/chk_obsdata//k5ts3/T2011703??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.17:05:26.10/chk_obsdata//k5ts4/T2011703??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.17:05:26.78/k5log//k5ts1_log_newline 2006.201.17:05:27.48/k5log//k5ts2_log_newline 2006.201.17:05:28.17/k5log//k5ts3_log_newline 2006.201.17:05:28.86/k5log//k5ts4_log_newline 2006.201.17:05:28.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.17:05:28.88:setupk4=1 2006.201.17:05:28.88$setupk4/echo=on 2006.201.17:05:28.88$setupk4/pcalon 2006.201.17:05:28.88$pcalon/"no phase cal control is implemented here 2006.201.17:05:28.88$setupk4/"tpicd=stop 2006.201.17:05:28.88$setupk4/"rec=synch_on 2006.201.17:05:28.88$setupk4/"rec_mode=128 2006.201.17:05:28.88$setupk4/!* 2006.201.17:05:28.88$setupk4/recpk4 2006.201.17:05:28.88$recpk4/recpatch= 2006.201.17:05:28.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.17:05:28.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.17:05:28.89$setupk4/vck44 2006.201.17:05:28.89$vck44/valo=1,524.99 2006.201.17:05:28.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.17:05:28.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.17:05:28.89#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:28.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:28.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:28.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:28.89#ibcon#enter wrdev, iclass 28, count 0 2006.201.17:05:28.89#ibcon#first serial, iclass 28, count 0 2006.201.17:05:28.89#ibcon#enter sib2, iclass 28, count 0 2006.201.17:05:28.89#ibcon#flushed, iclass 28, count 0 2006.201.17:05:28.89#ibcon#about to write, iclass 28, count 0 2006.201.17:05:28.89#ibcon#wrote, iclass 28, count 0 2006.201.17:05:28.89#ibcon#about to read 3, iclass 28, count 0 2006.201.17:05:28.92#ibcon#read 3, iclass 28, count 0 2006.201.17:05:28.92#ibcon#about to read 4, iclass 28, count 0 2006.201.17:05:28.92#ibcon#read 4, iclass 28, count 0 2006.201.17:05:28.92#ibcon#about to read 5, iclass 28, count 0 2006.201.17:05:28.92#ibcon#read 5, iclass 28, count 0 2006.201.17:05:28.92#ibcon#about to read 6, iclass 28, count 0 2006.201.17:05:28.92#ibcon#read 6, iclass 28, count 0 2006.201.17:05:28.92#ibcon#end of sib2, iclass 28, count 0 2006.201.17:05:28.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.17:05:28.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.17:05:28.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.17:05:28.92#ibcon#*before write, iclass 28, count 0 2006.201.17:05:28.92#ibcon#enter sib2, iclass 28, count 0 2006.201.17:05:28.92#ibcon#flushed, iclass 28, count 0 2006.201.17:05:28.92#ibcon#about to write, iclass 28, count 0 2006.201.17:05:28.92#ibcon#wrote, iclass 28, count 0 2006.201.17:05:28.92#ibcon#about to read 3, iclass 28, count 0 2006.201.17:05:28.97#ibcon#read 3, iclass 28, count 0 2006.201.17:05:28.97#ibcon#about to read 4, iclass 28, count 0 2006.201.17:05:28.97#ibcon#read 4, iclass 28, count 0 2006.201.17:05:28.97#ibcon#about to read 5, iclass 28, count 0 2006.201.17:05:28.97#ibcon#read 5, iclass 28, count 0 2006.201.17:05:28.97#ibcon#about to read 6, iclass 28, count 0 2006.201.17:05:28.97#ibcon#read 6, iclass 28, count 0 2006.201.17:05:28.97#ibcon#end of sib2, iclass 28, count 0 2006.201.17:05:28.97#ibcon#*after write, iclass 28, count 0 2006.201.17:05:28.97#ibcon#*before return 0, iclass 28, count 0 2006.201.17:05:28.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:28.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:28.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.17:05:28.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.17:05:28.97$vck44/va=1,8 2006.201.17:05:28.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.17:05:28.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.17:05:28.97#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:28.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:28.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:28.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:28.97#ibcon#enter wrdev, iclass 30, count 2 2006.201.17:05:28.97#ibcon#first serial, iclass 30, count 2 2006.201.17:05:28.97#ibcon#enter sib2, iclass 30, count 2 2006.201.17:05:28.97#ibcon#flushed, iclass 30, count 2 2006.201.17:05:28.97#ibcon#about to write, iclass 30, count 2 2006.201.17:05:28.97#ibcon#wrote, iclass 30, count 2 2006.201.17:05:28.97#ibcon#about to read 3, iclass 30, count 2 2006.201.17:05:28.99#ibcon#read 3, iclass 30, count 2 2006.201.17:05:28.99#ibcon#about to read 4, iclass 30, count 2 2006.201.17:05:28.99#ibcon#read 4, iclass 30, count 2 2006.201.17:05:28.99#ibcon#about to read 5, iclass 30, count 2 2006.201.17:05:28.99#ibcon#read 5, iclass 30, count 2 2006.201.17:05:28.99#ibcon#about to read 6, iclass 30, count 2 2006.201.17:05:28.99#ibcon#read 6, iclass 30, count 2 2006.201.17:05:28.99#ibcon#end of sib2, iclass 30, count 2 2006.201.17:05:28.99#ibcon#*mode == 0, iclass 30, count 2 2006.201.17:05:28.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.17:05:28.99#ibcon#[25=AT01-08\r\n] 2006.201.17:05:28.99#ibcon#*before write, iclass 30, count 2 2006.201.17:05:28.99#ibcon#enter sib2, iclass 30, count 2 2006.201.17:05:28.99#ibcon#flushed, iclass 30, count 2 2006.201.17:05:28.99#ibcon#about to write, iclass 30, count 2 2006.201.17:05:28.99#ibcon#wrote, iclass 30, count 2 2006.201.17:05:28.99#ibcon#about to read 3, iclass 30, count 2 2006.201.17:05:29.02#ibcon#read 3, iclass 30, count 2 2006.201.17:05:29.02#ibcon#about to read 4, iclass 30, count 2 2006.201.17:05:29.02#ibcon#read 4, iclass 30, count 2 2006.201.17:05:29.02#ibcon#about to read 5, iclass 30, count 2 2006.201.17:05:29.02#ibcon#read 5, iclass 30, count 2 2006.201.17:05:29.02#ibcon#about to read 6, iclass 30, count 2 2006.201.17:05:29.02#ibcon#read 6, iclass 30, count 2 2006.201.17:05:29.02#ibcon#end of sib2, iclass 30, count 2 2006.201.17:05:29.02#ibcon#*after write, iclass 30, count 2 2006.201.17:05:29.02#ibcon#*before return 0, iclass 30, count 2 2006.201.17:05:29.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:29.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:29.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.17:05:29.02#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:29.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:29.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:29.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:29.14#ibcon#enter wrdev, iclass 30, count 0 2006.201.17:05:29.14#ibcon#first serial, iclass 30, count 0 2006.201.17:05:29.14#ibcon#enter sib2, iclass 30, count 0 2006.201.17:05:29.14#ibcon#flushed, iclass 30, count 0 2006.201.17:05:29.14#ibcon#about to write, iclass 30, count 0 2006.201.17:05:29.14#ibcon#wrote, iclass 30, count 0 2006.201.17:05:29.14#ibcon#about to read 3, iclass 30, count 0 2006.201.17:05:29.16#ibcon#read 3, iclass 30, count 0 2006.201.17:05:29.16#ibcon#about to read 4, iclass 30, count 0 2006.201.17:05:29.16#ibcon#read 4, iclass 30, count 0 2006.201.17:05:29.16#ibcon#about to read 5, iclass 30, count 0 2006.201.17:05:29.16#ibcon#read 5, iclass 30, count 0 2006.201.17:05:29.16#ibcon#about to read 6, iclass 30, count 0 2006.201.17:05:29.16#ibcon#read 6, iclass 30, count 0 2006.201.17:05:29.16#ibcon#end of sib2, iclass 30, count 0 2006.201.17:05:29.16#ibcon#*mode == 0, iclass 30, count 0 2006.201.17:05:29.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.17:05:29.16#ibcon#[25=USB\r\n] 2006.201.17:05:29.16#ibcon#*before write, iclass 30, count 0 2006.201.17:05:29.16#ibcon#enter sib2, iclass 30, count 0 2006.201.17:05:29.16#ibcon#flushed, iclass 30, count 0 2006.201.17:05:29.16#ibcon#about to write, iclass 30, count 0 2006.201.17:05:29.16#ibcon#wrote, iclass 30, count 0 2006.201.17:05:29.16#ibcon#about to read 3, iclass 30, count 0 2006.201.17:05:29.19#ibcon#read 3, iclass 30, count 0 2006.201.17:05:29.19#ibcon#about to read 4, iclass 30, count 0 2006.201.17:05:29.19#ibcon#read 4, iclass 30, count 0 2006.201.17:05:29.19#ibcon#about to read 5, iclass 30, count 0 2006.201.17:05:29.19#ibcon#read 5, iclass 30, count 0 2006.201.17:05:29.19#ibcon#about to read 6, iclass 30, count 0 2006.201.17:05:29.19#ibcon#read 6, iclass 30, count 0 2006.201.17:05:29.19#ibcon#end of sib2, iclass 30, count 0 2006.201.17:05:29.19#ibcon#*after write, iclass 30, count 0 2006.201.17:05:29.19#ibcon#*before return 0, iclass 30, count 0 2006.201.17:05:29.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:29.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:29.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.17:05:29.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.17:05:29.19$vck44/valo=2,534.99 2006.201.17:05:29.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.17:05:29.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.17:05:29.19#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:29.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:05:29.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:05:29.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:05:29.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.17:05:29.19#ibcon#first serial, iclass 32, count 0 2006.201.17:05:29.19#ibcon#enter sib2, iclass 32, count 0 2006.201.17:05:29.19#ibcon#flushed, iclass 32, count 0 2006.201.17:05:29.19#ibcon#about to write, iclass 32, count 0 2006.201.17:05:29.19#ibcon#wrote, iclass 32, count 0 2006.201.17:05:29.19#ibcon#about to read 3, iclass 32, count 0 2006.201.17:05:29.21#ibcon#read 3, iclass 32, count 0 2006.201.17:05:29.21#ibcon#about to read 4, iclass 32, count 0 2006.201.17:05:29.21#ibcon#read 4, iclass 32, count 0 2006.201.17:05:29.21#ibcon#about to read 5, iclass 32, count 0 2006.201.17:05:29.21#ibcon#read 5, iclass 32, count 0 2006.201.17:05:29.21#ibcon#about to read 6, iclass 32, count 0 2006.201.17:05:29.21#ibcon#read 6, iclass 32, count 0 2006.201.17:05:29.21#ibcon#end of sib2, iclass 32, count 0 2006.201.17:05:29.21#ibcon#*mode == 0, iclass 32, count 0 2006.201.17:05:29.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.17:05:29.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.17:05:29.21#ibcon#*before write, iclass 32, count 0 2006.201.17:05:29.21#ibcon#enter sib2, iclass 32, count 0 2006.201.17:05:29.21#ibcon#flushed, iclass 32, count 0 2006.201.17:05:29.21#ibcon#about to write, iclass 32, count 0 2006.201.17:05:29.21#ibcon#wrote, iclass 32, count 0 2006.201.17:05:29.21#ibcon#about to read 3, iclass 32, count 0 2006.201.17:05:29.26#ibcon#read 3, iclass 32, count 0 2006.201.17:05:29.26#ibcon#about to read 4, iclass 32, count 0 2006.201.17:05:29.26#ibcon#read 4, iclass 32, count 0 2006.201.17:05:29.26#ibcon#about to read 5, iclass 32, count 0 2006.201.17:05:29.26#ibcon#read 5, iclass 32, count 0 2006.201.17:05:29.26#ibcon#about to read 6, iclass 32, count 0 2006.201.17:05:29.26#ibcon#read 6, iclass 32, count 0 2006.201.17:05:29.26#ibcon#end of sib2, iclass 32, count 0 2006.201.17:05:29.26#ibcon#*after write, iclass 32, count 0 2006.201.17:05:29.26#ibcon#*before return 0, iclass 32, count 0 2006.201.17:05:29.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:05:29.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:05:29.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.17:05:29.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.17:05:29.26$vck44/va=2,7 2006.201.17:05:29.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.17:05:29.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.17:05:29.26#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:29.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:05:29.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:05:29.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:05:29.31#ibcon#enter wrdev, iclass 34, count 2 2006.201.17:05:29.31#ibcon#first serial, iclass 34, count 2 2006.201.17:05:29.31#ibcon#enter sib2, iclass 34, count 2 2006.201.17:05:29.31#ibcon#flushed, iclass 34, count 2 2006.201.17:05:29.31#ibcon#about to write, iclass 34, count 2 2006.201.17:05:29.31#ibcon#wrote, iclass 34, count 2 2006.201.17:05:29.31#ibcon#about to read 3, iclass 34, count 2 2006.201.17:05:29.33#ibcon#read 3, iclass 34, count 2 2006.201.17:05:29.33#ibcon#about to read 4, iclass 34, count 2 2006.201.17:05:29.33#ibcon#read 4, iclass 34, count 2 2006.201.17:05:29.33#ibcon#about to read 5, iclass 34, count 2 2006.201.17:05:29.33#ibcon#read 5, iclass 34, count 2 2006.201.17:05:29.33#ibcon#about to read 6, iclass 34, count 2 2006.201.17:05:29.33#ibcon#read 6, iclass 34, count 2 2006.201.17:05:29.33#ibcon#end of sib2, iclass 34, count 2 2006.201.17:05:29.33#ibcon#*mode == 0, iclass 34, count 2 2006.201.17:05:29.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.17:05:29.33#ibcon#[25=AT02-07\r\n] 2006.201.17:05:29.33#ibcon#*before write, iclass 34, count 2 2006.201.17:05:29.33#ibcon#enter sib2, iclass 34, count 2 2006.201.17:05:29.33#ibcon#flushed, iclass 34, count 2 2006.201.17:05:29.33#ibcon#about to write, iclass 34, count 2 2006.201.17:05:29.33#ibcon#wrote, iclass 34, count 2 2006.201.17:05:29.33#ibcon#about to read 3, iclass 34, count 2 2006.201.17:05:29.36#ibcon#read 3, iclass 34, count 2 2006.201.17:05:29.36#ibcon#about to read 4, iclass 34, count 2 2006.201.17:05:29.36#ibcon#read 4, iclass 34, count 2 2006.201.17:05:29.36#ibcon#about to read 5, iclass 34, count 2 2006.201.17:05:29.36#ibcon#read 5, iclass 34, count 2 2006.201.17:05:29.36#ibcon#about to read 6, iclass 34, count 2 2006.201.17:05:29.36#ibcon#read 6, iclass 34, count 2 2006.201.17:05:29.36#ibcon#end of sib2, iclass 34, count 2 2006.201.17:05:29.36#ibcon#*after write, iclass 34, count 2 2006.201.17:05:29.36#ibcon#*before return 0, iclass 34, count 2 2006.201.17:05:29.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:05:29.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:05:29.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.17:05:29.36#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:29.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:05:29.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:05:29.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:05:29.48#ibcon#enter wrdev, iclass 34, count 0 2006.201.17:05:29.48#ibcon#first serial, iclass 34, count 0 2006.201.17:05:29.48#ibcon#enter sib2, iclass 34, count 0 2006.201.17:05:29.48#ibcon#flushed, iclass 34, count 0 2006.201.17:05:29.48#ibcon#about to write, iclass 34, count 0 2006.201.17:05:29.48#ibcon#wrote, iclass 34, count 0 2006.201.17:05:29.48#ibcon#about to read 3, iclass 34, count 0 2006.201.17:05:29.50#ibcon#read 3, iclass 34, count 0 2006.201.17:05:29.50#ibcon#about to read 4, iclass 34, count 0 2006.201.17:05:29.50#ibcon#read 4, iclass 34, count 0 2006.201.17:05:29.50#ibcon#about to read 5, iclass 34, count 0 2006.201.17:05:29.50#ibcon#read 5, iclass 34, count 0 2006.201.17:05:29.50#ibcon#about to read 6, iclass 34, count 0 2006.201.17:05:29.50#ibcon#read 6, iclass 34, count 0 2006.201.17:05:29.50#ibcon#end of sib2, iclass 34, count 0 2006.201.17:05:29.50#ibcon#*mode == 0, iclass 34, count 0 2006.201.17:05:29.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.17:05:29.50#ibcon#[25=USB\r\n] 2006.201.17:05:29.50#ibcon#*before write, iclass 34, count 0 2006.201.17:05:29.50#ibcon#enter sib2, iclass 34, count 0 2006.201.17:05:29.50#ibcon#flushed, iclass 34, count 0 2006.201.17:05:29.50#ibcon#about to write, iclass 34, count 0 2006.201.17:05:29.50#ibcon#wrote, iclass 34, count 0 2006.201.17:05:29.50#ibcon#about to read 3, iclass 34, count 0 2006.201.17:05:29.53#ibcon#read 3, iclass 34, count 0 2006.201.17:05:29.53#ibcon#about to read 4, iclass 34, count 0 2006.201.17:05:29.53#ibcon#read 4, iclass 34, count 0 2006.201.17:05:29.53#ibcon#about to read 5, iclass 34, count 0 2006.201.17:05:29.53#ibcon#read 5, iclass 34, count 0 2006.201.17:05:29.53#ibcon#about to read 6, iclass 34, count 0 2006.201.17:05:29.53#ibcon#read 6, iclass 34, count 0 2006.201.17:05:29.53#ibcon#end of sib2, iclass 34, count 0 2006.201.17:05:29.53#ibcon#*after write, iclass 34, count 0 2006.201.17:05:29.53#ibcon#*before return 0, iclass 34, count 0 2006.201.17:05:29.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:05:29.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:05:29.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.17:05:29.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.17:05:29.53$vck44/valo=3,564.99 2006.201.17:05:29.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.17:05:29.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.17:05:29.53#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:29.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:29.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:29.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:29.53#ibcon#enter wrdev, iclass 36, count 0 2006.201.17:05:29.53#ibcon#first serial, iclass 36, count 0 2006.201.17:05:29.53#ibcon#enter sib2, iclass 36, count 0 2006.201.17:05:29.53#ibcon#flushed, iclass 36, count 0 2006.201.17:05:29.53#ibcon#about to write, iclass 36, count 0 2006.201.17:05:29.53#ibcon#wrote, iclass 36, count 0 2006.201.17:05:29.53#ibcon#about to read 3, iclass 36, count 0 2006.201.17:05:29.55#ibcon#read 3, iclass 36, count 0 2006.201.17:05:29.55#ibcon#about to read 4, iclass 36, count 0 2006.201.17:05:29.55#ibcon#read 4, iclass 36, count 0 2006.201.17:05:29.55#ibcon#about to read 5, iclass 36, count 0 2006.201.17:05:29.55#ibcon#read 5, iclass 36, count 0 2006.201.17:05:29.55#ibcon#about to read 6, iclass 36, count 0 2006.201.17:05:29.55#ibcon#read 6, iclass 36, count 0 2006.201.17:05:29.55#ibcon#end of sib2, iclass 36, count 0 2006.201.17:05:29.55#ibcon#*mode == 0, iclass 36, count 0 2006.201.17:05:29.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.17:05:29.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.17:05:29.55#ibcon#*before write, iclass 36, count 0 2006.201.17:05:29.55#ibcon#enter sib2, iclass 36, count 0 2006.201.17:05:29.55#ibcon#flushed, iclass 36, count 0 2006.201.17:05:29.55#ibcon#about to write, iclass 36, count 0 2006.201.17:05:29.55#ibcon#wrote, iclass 36, count 0 2006.201.17:05:29.55#ibcon#about to read 3, iclass 36, count 0 2006.201.17:05:29.60#ibcon#read 3, iclass 36, count 0 2006.201.17:05:29.60#ibcon#about to read 4, iclass 36, count 0 2006.201.17:05:29.60#ibcon#read 4, iclass 36, count 0 2006.201.17:05:29.60#ibcon#about to read 5, iclass 36, count 0 2006.201.17:05:29.60#ibcon#read 5, iclass 36, count 0 2006.201.17:05:29.60#ibcon#about to read 6, iclass 36, count 0 2006.201.17:05:29.60#ibcon#read 6, iclass 36, count 0 2006.201.17:05:29.60#ibcon#end of sib2, iclass 36, count 0 2006.201.17:05:29.60#ibcon#*after write, iclass 36, count 0 2006.201.17:05:29.60#ibcon#*before return 0, iclass 36, count 0 2006.201.17:05:29.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:29.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:29.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.17:05:29.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.17:05:29.60$vck44/va=3,8 2006.201.17:05:29.60#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.17:05:29.60#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.17:05:29.60#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:29.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:29.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:29.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:29.65#ibcon#enter wrdev, iclass 38, count 2 2006.201.17:05:29.65#ibcon#first serial, iclass 38, count 2 2006.201.17:05:29.65#ibcon#enter sib2, iclass 38, count 2 2006.201.17:05:29.65#ibcon#flushed, iclass 38, count 2 2006.201.17:05:29.65#ibcon#about to write, iclass 38, count 2 2006.201.17:05:29.65#ibcon#wrote, iclass 38, count 2 2006.201.17:05:29.65#ibcon#about to read 3, iclass 38, count 2 2006.201.17:05:29.67#ibcon#read 3, iclass 38, count 2 2006.201.17:05:29.67#ibcon#about to read 4, iclass 38, count 2 2006.201.17:05:29.67#ibcon#read 4, iclass 38, count 2 2006.201.17:05:29.67#ibcon#about to read 5, iclass 38, count 2 2006.201.17:05:29.67#ibcon#read 5, iclass 38, count 2 2006.201.17:05:29.67#ibcon#about to read 6, iclass 38, count 2 2006.201.17:05:29.67#ibcon#read 6, iclass 38, count 2 2006.201.17:05:29.67#ibcon#end of sib2, iclass 38, count 2 2006.201.17:05:29.67#ibcon#*mode == 0, iclass 38, count 2 2006.201.17:05:29.67#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.17:05:29.67#ibcon#[25=AT03-08\r\n] 2006.201.17:05:29.67#ibcon#*before write, iclass 38, count 2 2006.201.17:05:29.67#ibcon#enter sib2, iclass 38, count 2 2006.201.17:05:29.67#ibcon#flushed, iclass 38, count 2 2006.201.17:05:29.67#ibcon#about to write, iclass 38, count 2 2006.201.17:05:29.67#ibcon#wrote, iclass 38, count 2 2006.201.17:05:29.67#ibcon#about to read 3, iclass 38, count 2 2006.201.17:05:29.70#ibcon#read 3, iclass 38, count 2 2006.201.17:05:29.70#ibcon#about to read 4, iclass 38, count 2 2006.201.17:05:29.70#ibcon#read 4, iclass 38, count 2 2006.201.17:05:29.70#ibcon#about to read 5, iclass 38, count 2 2006.201.17:05:29.70#ibcon#read 5, iclass 38, count 2 2006.201.17:05:29.70#ibcon#about to read 6, iclass 38, count 2 2006.201.17:05:29.70#ibcon#read 6, iclass 38, count 2 2006.201.17:05:29.70#ibcon#end of sib2, iclass 38, count 2 2006.201.17:05:29.70#ibcon#*after write, iclass 38, count 2 2006.201.17:05:29.70#ibcon#*before return 0, iclass 38, count 2 2006.201.17:05:29.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:29.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:29.70#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.17:05:29.70#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:29.70#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:29.82#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:29.82#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:29.82#ibcon#enter wrdev, iclass 38, count 0 2006.201.17:05:29.82#ibcon#first serial, iclass 38, count 0 2006.201.17:05:29.82#ibcon#enter sib2, iclass 38, count 0 2006.201.17:05:29.82#ibcon#flushed, iclass 38, count 0 2006.201.17:05:29.82#ibcon#about to write, iclass 38, count 0 2006.201.17:05:29.82#ibcon#wrote, iclass 38, count 0 2006.201.17:05:29.82#ibcon#about to read 3, iclass 38, count 0 2006.201.17:05:29.84#ibcon#read 3, iclass 38, count 0 2006.201.17:05:29.84#ibcon#about to read 4, iclass 38, count 0 2006.201.17:05:29.84#ibcon#read 4, iclass 38, count 0 2006.201.17:05:29.84#ibcon#about to read 5, iclass 38, count 0 2006.201.17:05:29.84#ibcon#read 5, iclass 38, count 0 2006.201.17:05:29.84#ibcon#about to read 6, iclass 38, count 0 2006.201.17:05:29.84#ibcon#read 6, iclass 38, count 0 2006.201.17:05:29.84#ibcon#end of sib2, iclass 38, count 0 2006.201.17:05:29.84#ibcon#*mode == 0, iclass 38, count 0 2006.201.17:05:29.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.17:05:29.84#ibcon#[25=USB\r\n] 2006.201.17:05:29.84#ibcon#*before write, iclass 38, count 0 2006.201.17:05:29.84#ibcon#enter sib2, iclass 38, count 0 2006.201.17:05:29.84#ibcon#flushed, iclass 38, count 0 2006.201.17:05:29.84#ibcon#about to write, iclass 38, count 0 2006.201.17:05:29.84#ibcon#wrote, iclass 38, count 0 2006.201.17:05:29.84#ibcon#about to read 3, iclass 38, count 0 2006.201.17:05:29.87#ibcon#read 3, iclass 38, count 0 2006.201.17:05:29.87#ibcon#about to read 4, iclass 38, count 0 2006.201.17:05:29.87#ibcon#read 4, iclass 38, count 0 2006.201.17:05:29.87#ibcon#about to read 5, iclass 38, count 0 2006.201.17:05:29.87#ibcon#read 5, iclass 38, count 0 2006.201.17:05:29.87#ibcon#about to read 6, iclass 38, count 0 2006.201.17:05:29.87#ibcon#read 6, iclass 38, count 0 2006.201.17:05:29.87#ibcon#end of sib2, iclass 38, count 0 2006.201.17:05:29.87#ibcon#*after write, iclass 38, count 0 2006.201.17:05:29.87#ibcon#*before return 0, iclass 38, count 0 2006.201.17:05:29.87#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:29.87#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:29.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.17:05:29.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.17:05:29.87$vck44/valo=4,624.99 2006.201.17:05:29.87#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.17:05:29.87#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.17:05:29.87#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:29.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:29.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:29.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:29.87#ibcon#enter wrdev, iclass 40, count 0 2006.201.17:05:29.87#ibcon#first serial, iclass 40, count 0 2006.201.17:05:29.87#ibcon#enter sib2, iclass 40, count 0 2006.201.17:05:29.87#ibcon#flushed, iclass 40, count 0 2006.201.17:05:29.87#ibcon#about to write, iclass 40, count 0 2006.201.17:05:29.87#ibcon#wrote, iclass 40, count 0 2006.201.17:05:29.87#ibcon#about to read 3, iclass 40, count 0 2006.201.17:05:29.89#ibcon#read 3, iclass 40, count 0 2006.201.17:05:29.89#ibcon#about to read 4, iclass 40, count 0 2006.201.17:05:29.89#ibcon#read 4, iclass 40, count 0 2006.201.17:05:29.89#ibcon#about to read 5, iclass 40, count 0 2006.201.17:05:29.89#ibcon#read 5, iclass 40, count 0 2006.201.17:05:29.89#ibcon#about to read 6, iclass 40, count 0 2006.201.17:05:29.89#ibcon#read 6, iclass 40, count 0 2006.201.17:05:29.89#ibcon#end of sib2, iclass 40, count 0 2006.201.17:05:29.89#ibcon#*mode == 0, iclass 40, count 0 2006.201.17:05:29.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.17:05:29.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.17:05:29.89#ibcon#*before write, iclass 40, count 0 2006.201.17:05:29.89#ibcon#enter sib2, iclass 40, count 0 2006.201.17:05:29.89#ibcon#flushed, iclass 40, count 0 2006.201.17:05:29.89#ibcon#about to write, iclass 40, count 0 2006.201.17:05:29.89#ibcon#wrote, iclass 40, count 0 2006.201.17:05:29.89#ibcon#about to read 3, iclass 40, count 0 2006.201.17:05:29.93#ibcon#read 3, iclass 40, count 0 2006.201.17:05:29.93#ibcon#about to read 4, iclass 40, count 0 2006.201.17:05:29.93#ibcon#read 4, iclass 40, count 0 2006.201.17:05:29.93#ibcon#about to read 5, iclass 40, count 0 2006.201.17:05:29.93#ibcon#read 5, iclass 40, count 0 2006.201.17:05:29.93#ibcon#about to read 6, iclass 40, count 0 2006.201.17:05:29.93#ibcon#read 6, iclass 40, count 0 2006.201.17:05:29.93#ibcon#end of sib2, iclass 40, count 0 2006.201.17:05:29.93#ibcon#*after write, iclass 40, count 0 2006.201.17:05:29.93#ibcon#*before return 0, iclass 40, count 0 2006.201.17:05:29.93#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:29.93#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:29.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.17:05:29.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.17:05:29.93$vck44/va=4,7 2006.201.17:05:29.93#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.17:05:29.93#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.17:05:29.93#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:29.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:29.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:29.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:29.99#ibcon#enter wrdev, iclass 4, count 2 2006.201.17:05:29.99#ibcon#first serial, iclass 4, count 2 2006.201.17:05:29.99#ibcon#enter sib2, iclass 4, count 2 2006.201.17:05:29.99#ibcon#flushed, iclass 4, count 2 2006.201.17:05:29.99#ibcon#about to write, iclass 4, count 2 2006.201.17:05:29.99#ibcon#wrote, iclass 4, count 2 2006.201.17:05:29.99#ibcon#about to read 3, iclass 4, count 2 2006.201.17:05:30.01#ibcon#read 3, iclass 4, count 2 2006.201.17:05:30.01#ibcon#about to read 4, iclass 4, count 2 2006.201.17:05:30.01#ibcon#read 4, iclass 4, count 2 2006.201.17:05:30.01#ibcon#about to read 5, iclass 4, count 2 2006.201.17:05:30.01#ibcon#read 5, iclass 4, count 2 2006.201.17:05:30.01#ibcon#about to read 6, iclass 4, count 2 2006.201.17:05:30.01#ibcon#read 6, iclass 4, count 2 2006.201.17:05:30.01#ibcon#end of sib2, iclass 4, count 2 2006.201.17:05:30.01#ibcon#*mode == 0, iclass 4, count 2 2006.201.17:05:30.01#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.17:05:30.01#ibcon#[25=AT04-07\r\n] 2006.201.17:05:30.01#ibcon#*before write, iclass 4, count 2 2006.201.17:05:30.01#ibcon#enter sib2, iclass 4, count 2 2006.201.17:05:30.01#ibcon#flushed, iclass 4, count 2 2006.201.17:05:30.01#ibcon#about to write, iclass 4, count 2 2006.201.17:05:30.01#ibcon#wrote, iclass 4, count 2 2006.201.17:05:30.01#ibcon#about to read 3, iclass 4, count 2 2006.201.17:05:30.04#ibcon#read 3, iclass 4, count 2 2006.201.17:05:30.04#ibcon#about to read 4, iclass 4, count 2 2006.201.17:05:30.04#ibcon#read 4, iclass 4, count 2 2006.201.17:05:30.04#ibcon#about to read 5, iclass 4, count 2 2006.201.17:05:30.04#ibcon#read 5, iclass 4, count 2 2006.201.17:05:30.04#ibcon#about to read 6, iclass 4, count 2 2006.201.17:05:30.04#ibcon#read 6, iclass 4, count 2 2006.201.17:05:30.04#ibcon#end of sib2, iclass 4, count 2 2006.201.17:05:30.04#ibcon#*after write, iclass 4, count 2 2006.201.17:05:30.04#ibcon#*before return 0, iclass 4, count 2 2006.201.17:05:30.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:30.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:30.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.17:05:30.04#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:30.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:30.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:30.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:30.16#ibcon#enter wrdev, iclass 4, count 0 2006.201.17:05:30.16#ibcon#first serial, iclass 4, count 0 2006.201.17:05:30.16#ibcon#enter sib2, iclass 4, count 0 2006.201.17:05:30.16#ibcon#flushed, iclass 4, count 0 2006.201.17:05:30.16#ibcon#about to write, iclass 4, count 0 2006.201.17:05:30.16#ibcon#wrote, iclass 4, count 0 2006.201.17:05:30.16#ibcon#about to read 3, iclass 4, count 0 2006.201.17:05:30.18#ibcon#read 3, iclass 4, count 0 2006.201.17:05:30.18#ibcon#about to read 4, iclass 4, count 0 2006.201.17:05:30.18#ibcon#read 4, iclass 4, count 0 2006.201.17:05:30.18#ibcon#about to read 5, iclass 4, count 0 2006.201.17:05:30.18#ibcon#read 5, iclass 4, count 0 2006.201.17:05:30.18#ibcon#about to read 6, iclass 4, count 0 2006.201.17:05:30.18#ibcon#read 6, iclass 4, count 0 2006.201.17:05:30.18#ibcon#end of sib2, iclass 4, count 0 2006.201.17:05:30.18#ibcon#*mode == 0, iclass 4, count 0 2006.201.17:05:30.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.17:05:30.18#ibcon#[25=USB\r\n] 2006.201.17:05:30.18#ibcon#*before write, iclass 4, count 0 2006.201.17:05:30.18#ibcon#enter sib2, iclass 4, count 0 2006.201.17:05:30.18#ibcon#flushed, iclass 4, count 0 2006.201.17:05:30.18#ibcon#about to write, iclass 4, count 0 2006.201.17:05:30.18#ibcon#wrote, iclass 4, count 0 2006.201.17:05:30.18#ibcon#about to read 3, iclass 4, count 0 2006.201.17:05:30.21#ibcon#read 3, iclass 4, count 0 2006.201.17:05:30.21#ibcon#about to read 4, iclass 4, count 0 2006.201.17:05:30.21#ibcon#read 4, iclass 4, count 0 2006.201.17:05:30.21#ibcon#about to read 5, iclass 4, count 0 2006.201.17:05:30.21#ibcon#read 5, iclass 4, count 0 2006.201.17:05:30.21#ibcon#about to read 6, iclass 4, count 0 2006.201.17:05:30.21#ibcon#read 6, iclass 4, count 0 2006.201.17:05:30.21#ibcon#end of sib2, iclass 4, count 0 2006.201.17:05:30.21#ibcon#*after write, iclass 4, count 0 2006.201.17:05:30.21#ibcon#*before return 0, iclass 4, count 0 2006.201.17:05:30.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:30.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:30.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.17:05:30.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.17:05:30.21$vck44/valo=5,734.99 2006.201.17:05:30.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.17:05:30.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.17:05:30.21#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:30.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:30.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:30.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:30.21#ibcon#enter wrdev, iclass 6, count 0 2006.201.17:05:30.21#ibcon#first serial, iclass 6, count 0 2006.201.17:05:30.21#ibcon#enter sib2, iclass 6, count 0 2006.201.17:05:30.21#ibcon#flushed, iclass 6, count 0 2006.201.17:05:30.21#ibcon#about to write, iclass 6, count 0 2006.201.17:05:30.21#ibcon#wrote, iclass 6, count 0 2006.201.17:05:30.21#ibcon#about to read 3, iclass 6, count 0 2006.201.17:05:30.23#ibcon#read 3, iclass 6, count 0 2006.201.17:05:30.23#ibcon#about to read 4, iclass 6, count 0 2006.201.17:05:30.23#ibcon#read 4, iclass 6, count 0 2006.201.17:05:30.23#ibcon#about to read 5, iclass 6, count 0 2006.201.17:05:30.23#ibcon#read 5, iclass 6, count 0 2006.201.17:05:30.23#ibcon#about to read 6, iclass 6, count 0 2006.201.17:05:30.23#ibcon#read 6, iclass 6, count 0 2006.201.17:05:30.23#ibcon#end of sib2, iclass 6, count 0 2006.201.17:05:30.23#ibcon#*mode == 0, iclass 6, count 0 2006.201.17:05:30.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.17:05:30.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.17:05:30.23#ibcon#*before write, iclass 6, count 0 2006.201.17:05:30.23#ibcon#enter sib2, iclass 6, count 0 2006.201.17:05:30.23#ibcon#flushed, iclass 6, count 0 2006.201.17:05:30.23#ibcon#about to write, iclass 6, count 0 2006.201.17:05:30.23#ibcon#wrote, iclass 6, count 0 2006.201.17:05:30.23#ibcon#about to read 3, iclass 6, count 0 2006.201.17:05:30.27#ibcon#read 3, iclass 6, count 0 2006.201.17:05:30.27#ibcon#about to read 4, iclass 6, count 0 2006.201.17:05:30.27#ibcon#read 4, iclass 6, count 0 2006.201.17:05:30.27#ibcon#about to read 5, iclass 6, count 0 2006.201.17:05:30.27#ibcon#read 5, iclass 6, count 0 2006.201.17:05:30.27#ibcon#about to read 6, iclass 6, count 0 2006.201.17:05:30.27#ibcon#read 6, iclass 6, count 0 2006.201.17:05:30.27#ibcon#end of sib2, iclass 6, count 0 2006.201.17:05:30.27#ibcon#*after write, iclass 6, count 0 2006.201.17:05:30.27#ibcon#*before return 0, iclass 6, count 0 2006.201.17:05:30.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:30.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:30.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.17:05:30.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.17:05:30.27$vck44/va=5,4 2006.201.17:05:30.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.17:05:30.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.17:05:30.27#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:30.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:30.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:30.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:30.33#ibcon#enter wrdev, iclass 10, count 2 2006.201.17:05:30.33#ibcon#first serial, iclass 10, count 2 2006.201.17:05:30.33#ibcon#enter sib2, iclass 10, count 2 2006.201.17:05:30.33#ibcon#flushed, iclass 10, count 2 2006.201.17:05:30.33#ibcon#about to write, iclass 10, count 2 2006.201.17:05:30.33#ibcon#wrote, iclass 10, count 2 2006.201.17:05:30.33#ibcon#about to read 3, iclass 10, count 2 2006.201.17:05:30.35#ibcon#read 3, iclass 10, count 2 2006.201.17:05:30.35#ibcon#about to read 4, iclass 10, count 2 2006.201.17:05:30.35#ibcon#read 4, iclass 10, count 2 2006.201.17:05:30.35#ibcon#about to read 5, iclass 10, count 2 2006.201.17:05:30.35#ibcon#read 5, iclass 10, count 2 2006.201.17:05:30.35#ibcon#about to read 6, iclass 10, count 2 2006.201.17:05:30.35#ibcon#read 6, iclass 10, count 2 2006.201.17:05:30.35#ibcon#end of sib2, iclass 10, count 2 2006.201.17:05:30.35#ibcon#*mode == 0, iclass 10, count 2 2006.201.17:05:30.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.17:05:30.35#ibcon#[25=AT05-04\r\n] 2006.201.17:05:30.35#ibcon#*before write, iclass 10, count 2 2006.201.17:05:30.35#ibcon#enter sib2, iclass 10, count 2 2006.201.17:05:30.35#ibcon#flushed, iclass 10, count 2 2006.201.17:05:30.35#ibcon#about to write, iclass 10, count 2 2006.201.17:05:30.35#ibcon#wrote, iclass 10, count 2 2006.201.17:05:30.35#ibcon#about to read 3, iclass 10, count 2 2006.201.17:05:30.38#ibcon#read 3, iclass 10, count 2 2006.201.17:05:30.38#ibcon#about to read 4, iclass 10, count 2 2006.201.17:05:30.38#ibcon#read 4, iclass 10, count 2 2006.201.17:05:30.38#ibcon#about to read 5, iclass 10, count 2 2006.201.17:05:30.38#ibcon#read 5, iclass 10, count 2 2006.201.17:05:30.38#ibcon#about to read 6, iclass 10, count 2 2006.201.17:05:30.38#ibcon#read 6, iclass 10, count 2 2006.201.17:05:30.38#ibcon#end of sib2, iclass 10, count 2 2006.201.17:05:30.38#ibcon#*after write, iclass 10, count 2 2006.201.17:05:30.38#ibcon#*before return 0, iclass 10, count 2 2006.201.17:05:30.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:30.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:30.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.17:05:30.38#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:30.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:30.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:30.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:30.50#ibcon#enter wrdev, iclass 10, count 0 2006.201.17:05:30.50#ibcon#first serial, iclass 10, count 0 2006.201.17:05:30.50#ibcon#enter sib2, iclass 10, count 0 2006.201.17:05:30.50#ibcon#flushed, iclass 10, count 0 2006.201.17:05:30.50#ibcon#about to write, iclass 10, count 0 2006.201.17:05:30.50#ibcon#wrote, iclass 10, count 0 2006.201.17:05:30.50#ibcon#about to read 3, iclass 10, count 0 2006.201.17:05:30.52#ibcon#read 3, iclass 10, count 0 2006.201.17:05:30.52#ibcon#about to read 4, iclass 10, count 0 2006.201.17:05:30.52#ibcon#read 4, iclass 10, count 0 2006.201.17:05:30.52#ibcon#about to read 5, iclass 10, count 0 2006.201.17:05:30.52#ibcon#read 5, iclass 10, count 0 2006.201.17:05:30.52#ibcon#about to read 6, iclass 10, count 0 2006.201.17:05:30.52#ibcon#read 6, iclass 10, count 0 2006.201.17:05:30.52#ibcon#end of sib2, iclass 10, count 0 2006.201.17:05:30.52#ibcon#*mode == 0, iclass 10, count 0 2006.201.17:05:30.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.17:05:30.52#ibcon#[25=USB\r\n] 2006.201.17:05:30.52#ibcon#*before write, iclass 10, count 0 2006.201.17:05:30.52#ibcon#enter sib2, iclass 10, count 0 2006.201.17:05:30.52#ibcon#flushed, iclass 10, count 0 2006.201.17:05:30.52#ibcon#about to write, iclass 10, count 0 2006.201.17:05:30.52#ibcon#wrote, iclass 10, count 0 2006.201.17:05:30.52#ibcon#about to read 3, iclass 10, count 0 2006.201.17:05:30.55#ibcon#read 3, iclass 10, count 0 2006.201.17:05:30.55#ibcon#about to read 4, iclass 10, count 0 2006.201.17:05:30.55#ibcon#read 4, iclass 10, count 0 2006.201.17:05:30.55#ibcon#about to read 5, iclass 10, count 0 2006.201.17:05:30.55#ibcon#read 5, iclass 10, count 0 2006.201.17:05:30.55#ibcon#about to read 6, iclass 10, count 0 2006.201.17:05:30.55#ibcon#read 6, iclass 10, count 0 2006.201.17:05:30.55#ibcon#end of sib2, iclass 10, count 0 2006.201.17:05:30.55#ibcon#*after write, iclass 10, count 0 2006.201.17:05:30.55#ibcon#*before return 0, iclass 10, count 0 2006.201.17:05:30.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:30.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:30.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.17:05:30.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.17:05:30.55$vck44/valo=6,814.99 2006.201.17:05:30.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.17:05:30.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.17:05:30.55#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:30.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:30.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:30.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:30.55#ibcon#enter wrdev, iclass 12, count 0 2006.201.17:05:30.55#ibcon#first serial, iclass 12, count 0 2006.201.17:05:30.55#ibcon#enter sib2, iclass 12, count 0 2006.201.17:05:30.55#ibcon#flushed, iclass 12, count 0 2006.201.17:05:30.55#ibcon#about to write, iclass 12, count 0 2006.201.17:05:30.55#ibcon#wrote, iclass 12, count 0 2006.201.17:05:30.55#ibcon#about to read 3, iclass 12, count 0 2006.201.17:05:30.57#ibcon#read 3, iclass 12, count 0 2006.201.17:05:30.57#ibcon#about to read 4, iclass 12, count 0 2006.201.17:05:30.57#ibcon#read 4, iclass 12, count 0 2006.201.17:05:30.57#ibcon#about to read 5, iclass 12, count 0 2006.201.17:05:30.57#ibcon#read 5, iclass 12, count 0 2006.201.17:05:30.57#ibcon#about to read 6, iclass 12, count 0 2006.201.17:05:30.57#ibcon#read 6, iclass 12, count 0 2006.201.17:05:30.57#ibcon#end of sib2, iclass 12, count 0 2006.201.17:05:30.57#ibcon#*mode == 0, iclass 12, count 0 2006.201.17:05:30.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.17:05:30.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.17:05:30.57#ibcon#*before write, iclass 12, count 0 2006.201.17:05:30.57#ibcon#enter sib2, iclass 12, count 0 2006.201.17:05:30.57#ibcon#flushed, iclass 12, count 0 2006.201.17:05:30.57#ibcon#about to write, iclass 12, count 0 2006.201.17:05:30.57#ibcon#wrote, iclass 12, count 0 2006.201.17:05:30.57#ibcon#about to read 3, iclass 12, count 0 2006.201.17:05:30.61#ibcon#read 3, iclass 12, count 0 2006.201.17:05:30.61#ibcon#about to read 4, iclass 12, count 0 2006.201.17:05:30.61#ibcon#read 4, iclass 12, count 0 2006.201.17:05:30.61#ibcon#about to read 5, iclass 12, count 0 2006.201.17:05:30.61#ibcon#read 5, iclass 12, count 0 2006.201.17:05:30.61#ibcon#about to read 6, iclass 12, count 0 2006.201.17:05:30.61#ibcon#read 6, iclass 12, count 0 2006.201.17:05:30.61#ibcon#end of sib2, iclass 12, count 0 2006.201.17:05:30.61#ibcon#*after write, iclass 12, count 0 2006.201.17:05:30.61#ibcon#*before return 0, iclass 12, count 0 2006.201.17:05:30.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:30.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:30.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.17:05:30.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.17:05:30.61$vck44/va=6,5 2006.201.17:05:30.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.17:05:30.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.17:05:30.61#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:30.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:30.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:30.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:30.67#ibcon#enter wrdev, iclass 14, count 2 2006.201.17:05:30.67#ibcon#first serial, iclass 14, count 2 2006.201.17:05:30.67#ibcon#enter sib2, iclass 14, count 2 2006.201.17:05:30.67#ibcon#flushed, iclass 14, count 2 2006.201.17:05:30.67#ibcon#about to write, iclass 14, count 2 2006.201.17:05:30.67#ibcon#wrote, iclass 14, count 2 2006.201.17:05:30.67#ibcon#about to read 3, iclass 14, count 2 2006.201.17:05:30.69#ibcon#read 3, iclass 14, count 2 2006.201.17:05:30.69#ibcon#about to read 4, iclass 14, count 2 2006.201.17:05:30.69#ibcon#read 4, iclass 14, count 2 2006.201.17:05:30.69#ibcon#about to read 5, iclass 14, count 2 2006.201.17:05:30.69#ibcon#read 5, iclass 14, count 2 2006.201.17:05:30.69#ibcon#about to read 6, iclass 14, count 2 2006.201.17:05:30.69#ibcon#read 6, iclass 14, count 2 2006.201.17:05:30.69#ibcon#end of sib2, iclass 14, count 2 2006.201.17:05:30.69#ibcon#*mode == 0, iclass 14, count 2 2006.201.17:05:30.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.17:05:30.69#ibcon#[25=AT06-05\r\n] 2006.201.17:05:30.69#ibcon#*before write, iclass 14, count 2 2006.201.17:05:30.69#ibcon#enter sib2, iclass 14, count 2 2006.201.17:05:30.69#ibcon#flushed, iclass 14, count 2 2006.201.17:05:30.69#ibcon#about to write, iclass 14, count 2 2006.201.17:05:30.69#ibcon#wrote, iclass 14, count 2 2006.201.17:05:30.69#ibcon#about to read 3, iclass 14, count 2 2006.201.17:05:30.72#ibcon#read 3, iclass 14, count 2 2006.201.17:05:30.72#ibcon#about to read 4, iclass 14, count 2 2006.201.17:05:30.72#ibcon#read 4, iclass 14, count 2 2006.201.17:05:30.72#ibcon#about to read 5, iclass 14, count 2 2006.201.17:05:30.72#ibcon#read 5, iclass 14, count 2 2006.201.17:05:30.72#ibcon#about to read 6, iclass 14, count 2 2006.201.17:05:30.72#ibcon#read 6, iclass 14, count 2 2006.201.17:05:30.72#ibcon#end of sib2, iclass 14, count 2 2006.201.17:05:30.72#ibcon#*after write, iclass 14, count 2 2006.201.17:05:30.72#ibcon#*before return 0, iclass 14, count 2 2006.201.17:05:30.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:30.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:30.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.17:05:30.72#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:30.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:30.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:30.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:30.84#ibcon#enter wrdev, iclass 14, count 0 2006.201.17:05:30.84#ibcon#first serial, iclass 14, count 0 2006.201.17:05:30.84#ibcon#enter sib2, iclass 14, count 0 2006.201.17:05:30.84#ibcon#flushed, iclass 14, count 0 2006.201.17:05:30.84#ibcon#about to write, iclass 14, count 0 2006.201.17:05:30.84#ibcon#wrote, iclass 14, count 0 2006.201.17:05:30.84#ibcon#about to read 3, iclass 14, count 0 2006.201.17:05:30.86#ibcon#read 3, iclass 14, count 0 2006.201.17:05:30.86#ibcon#about to read 4, iclass 14, count 0 2006.201.17:05:30.86#ibcon#read 4, iclass 14, count 0 2006.201.17:05:30.86#ibcon#about to read 5, iclass 14, count 0 2006.201.17:05:30.86#ibcon#read 5, iclass 14, count 0 2006.201.17:05:30.86#ibcon#about to read 6, iclass 14, count 0 2006.201.17:05:30.86#ibcon#read 6, iclass 14, count 0 2006.201.17:05:30.86#ibcon#end of sib2, iclass 14, count 0 2006.201.17:05:30.86#ibcon#*mode == 0, iclass 14, count 0 2006.201.17:05:30.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.17:05:30.86#ibcon#[25=USB\r\n] 2006.201.17:05:30.86#ibcon#*before write, iclass 14, count 0 2006.201.17:05:30.86#ibcon#enter sib2, iclass 14, count 0 2006.201.17:05:30.86#ibcon#flushed, iclass 14, count 0 2006.201.17:05:30.86#ibcon#about to write, iclass 14, count 0 2006.201.17:05:30.86#ibcon#wrote, iclass 14, count 0 2006.201.17:05:30.86#ibcon#about to read 3, iclass 14, count 0 2006.201.17:05:30.89#ibcon#read 3, iclass 14, count 0 2006.201.17:05:30.89#ibcon#about to read 4, iclass 14, count 0 2006.201.17:05:30.89#ibcon#read 4, iclass 14, count 0 2006.201.17:05:30.89#ibcon#about to read 5, iclass 14, count 0 2006.201.17:05:30.89#ibcon#read 5, iclass 14, count 0 2006.201.17:05:30.89#ibcon#about to read 6, iclass 14, count 0 2006.201.17:05:30.89#ibcon#read 6, iclass 14, count 0 2006.201.17:05:30.89#ibcon#end of sib2, iclass 14, count 0 2006.201.17:05:30.89#ibcon#*after write, iclass 14, count 0 2006.201.17:05:30.89#ibcon#*before return 0, iclass 14, count 0 2006.201.17:05:30.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:30.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:30.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.17:05:30.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.17:05:30.89$vck44/valo=7,864.99 2006.201.17:05:30.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.17:05:30.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.17:05:30.89#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:30.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:30.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:30.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:30.89#ibcon#enter wrdev, iclass 16, count 0 2006.201.17:05:30.89#ibcon#first serial, iclass 16, count 0 2006.201.17:05:30.89#ibcon#enter sib2, iclass 16, count 0 2006.201.17:05:30.89#ibcon#flushed, iclass 16, count 0 2006.201.17:05:30.89#ibcon#about to write, iclass 16, count 0 2006.201.17:05:30.89#ibcon#wrote, iclass 16, count 0 2006.201.17:05:30.89#ibcon#about to read 3, iclass 16, count 0 2006.201.17:05:30.91#ibcon#read 3, iclass 16, count 0 2006.201.17:05:30.91#ibcon#about to read 4, iclass 16, count 0 2006.201.17:05:30.91#ibcon#read 4, iclass 16, count 0 2006.201.17:05:30.91#ibcon#about to read 5, iclass 16, count 0 2006.201.17:05:30.91#ibcon#read 5, iclass 16, count 0 2006.201.17:05:30.91#ibcon#about to read 6, iclass 16, count 0 2006.201.17:05:30.91#ibcon#read 6, iclass 16, count 0 2006.201.17:05:30.91#ibcon#end of sib2, iclass 16, count 0 2006.201.17:05:30.91#ibcon#*mode == 0, iclass 16, count 0 2006.201.17:05:30.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.17:05:30.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.17:05:30.91#ibcon#*before write, iclass 16, count 0 2006.201.17:05:30.91#ibcon#enter sib2, iclass 16, count 0 2006.201.17:05:30.91#ibcon#flushed, iclass 16, count 0 2006.201.17:05:30.91#ibcon#about to write, iclass 16, count 0 2006.201.17:05:30.91#ibcon#wrote, iclass 16, count 0 2006.201.17:05:30.91#ibcon#about to read 3, iclass 16, count 0 2006.201.17:05:30.95#ibcon#read 3, iclass 16, count 0 2006.201.17:05:30.95#ibcon#about to read 4, iclass 16, count 0 2006.201.17:05:30.95#ibcon#read 4, iclass 16, count 0 2006.201.17:05:30.95#ibcon#about to read 5, iclass 16, count 0 2006.201.17:05:30.95#ibcon#read 5, iclass 16, count 0 2006.201.17:05:30.95#ibcon#about to read 6, iclass 16, count 0 2006.201.17:05:30.95#ibcon#read 6, iclass 16, count 0 2006.201.17:05:30.95#ibcon#end of sib2, iclass 16, count 0 2006.201.17:05:30.95#ibcon#*after write, iclass 16, count 0 2006.201.17:05:30.95#ibcon#*before return 0, iclass 16, count 0 2006.201.17:05:30.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:30.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:30.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.17:05:30.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.17:05:30.95$vck44/va=7,5 2006.201.17:05:30.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.17:05:30.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.17:05:30.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:30.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:31.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:31.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:31.01#ibcon#enter wrdev, iclass 18, count 2 2006.201.17:05:31.01#ibcon#first serial, iclass 18, count 2 2006.201.17:05:31.01#ibcon#enter sib2, iclass 18, count 2 2006.201.17:05:31.01#ibcon#flushed, iclass 18, count 2 2006.201.17:05:31.01#ibcon#about to write, iclass 18, count 2 2006.201.17:05:31.01#ibcon#wrote, iclass 18, count 2 2006.201.17:05:31.01#ibcon#about to read 3, iclass 18, count 2 2006.201.17:05:31.03#ibcon#read 3, iclass 18, count 2 2006.201.17:05:31.03#ibcon#about to read 4, iclass 18, count 2 2006.201.17:05:31.03#ibcon#read 4, iclass 18, count 2 2006.201.17:05:31.03#ibcon#about to read 5, iclass 18, count 2 2006.201.17:05:31.03#ibcon#read 5, iclass 18, count 2 2006.201.17:05:31.03#ibcon#about to read 6, iclass 18, count 2 2006.201.17:05:31.03#ibcon#read 6, iclass 18, count 2 2006.201.17:05:31.03#ibcon#end of sib2, iclass 18, count 2 2006.201.17:05:31.03#ibcon#*mode == 0, iclass 18, count 2 2006.201.17:05:31.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.17:05:31.03#ibcon#[25=AT07-05\r\n] 2006.201.17:05:31.03#ibcon#*before write, iclass 18, count 2 2006.201.17:05:31.03#ibcon#enter sib2, iclass 18, count 2 2006.201.17:05:31.03#ibcon#flushed, iclass 18, count 2 2006.201.17:05:31.03#ibcon#about to write, iclass 18, count 2 2006.201.17:05:31.03#ibcon#wrote, iclass 18, count 2 2006.201.17:05:31.03#ibcon#about to read 3, iclass 18, count 2 2006.201.17:05:31.06#ibcon#read 3, iclass 18, count 2 2006.201.17:05:31.06#ibcon#about to read 4, iclass 18, count 2 2006.201.17:05:31.06#ibcon#read 4, iclass 18, count 2 2006.201.17:05:31.06#ibcon#about to read 5, iclass 18, count 2 2006.201.17:05:31.06#ibcon#read 5, iclass 18, count 2 2006.201.17:05:31.06#ibcon#about to read 6, iclass 18, count 2 2006.201.17:05:31.06#ibcon#read 6, iclass 18, count 2 2006.201.17:05:31.06#ibcon#end of sib2, iclass 18, count 2 2006.201.17:05:31.06#ibcon#*after write, iclass 18, count 2 2006.201.17:05:31.06#ibcon#*before return 0, iclass 18, count 2 2006.201.17:05:31.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:31.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:31.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.17:05:31.06#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:31.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:31.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:31.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:31.18#ibcon#enter wrdev, iclass 18, count 0 2006.201.17:05:31.18#ibcon#first serial, iclass 18, count 0 2006.201.17:05:31.18#ibcon#enter sib2, iclass 18, count 0 2006.201.17:05:31.18#ibcon#flushed, iclass 18, count 0 2006.201.17:05:31.18#ibcon#about to write, iclass 18, count 0 2006.201.17:05:31.18#ibcon#wrote, iclass 18, count 0 2006.201.17:05:31.18#ibcon#about to read 3, iclass 18, count 0 2006.201.17:05:31.20#ibcon#read 3, iclass 18, count 0 2006.201.17:05:31.20#ibcon#about to read 4, iclass 18, count 0 2006.201.17:05:31.20#ibcon#read 4, iclass 18, count 0 2006.201.17:05:31.20#ibcon#about to read 5, iclass 18, count 0 2006.201.17:05:31.20#ibcon#read 5, iclass 18, count 0 2006.201.17:05:31.20#ibcon#about to read 6, iclass 18, count 0 2006.201.17:05:31.20#ibcon#read 6, iclass 18, count 0 2006.201.17:05:31.20#ibcon#end of sib2, iclass 18, count 0 2006.201.17:05:31.20#ibcon#*mode == 0, iclass 18, count 0 2006.201.17:05:31.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.17:05:31.20#ibcon#[25=USB\r\n] 2006.201.17:05:31.20#ibcon#*before write, iclass 18, count 0 2006.201.17:05:31.20#ibcon#enter sib2, iclass 18, count 0 2006.201.17:05:31.20#ibcon#flushed, iclass 18, count 0 2006.201.17:05:31.20#ibcon#about to write, iclass 18, count 0 2006.201.17:05:31.20#ibcon#wrote, iclass 18, count 0 2006.201.17:05:31.20#ibcon#about to read 3, iclass 18, count 0 2006.201.17:05:31.23#ibcon#read 3, iclass 18, count 0 2006.201.17:05:31.23#ibcon#about to read 4, iclass 18, count 0 2006.201.17:05:31.23#ibcon#read 4, iclass 18, count 0 2006.201.17:05:31.23#ibcon#about to read 5, iclass 18, count 0 2006.201.17:05:31.23#ibcon#read 5, iclass 18, count 0 2006.201.17:05:31.23#ibcon#about to read 6, iclass 18, count 0 2006.201.17:05:31.23#ibcon#read 6, iclass 18, count 0 2006.201.17:05:31.23#ibcon#end of sib2, iclass 18, count 0 2006.201.17:05:31.23#ibcon#*after write, iclass 18, count 0 2006.201.17:05:31.23#ibcon#*before return 0, iclass 18, count 0 2006.201.17:05:31.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:31.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:31.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.17:05:31.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.17:05:31.23$vck44/valo=8,884.99 2006.201.17:05:31.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.17:05:31.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.17:05:31.23#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:31.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:31.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:31.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:31.23#ibcon#enter wrdev, iclass 20, count 0 2006.201.17:05:31.23#ibcon#first serial, iclass 20, count 0 2006.201.17:05:31.23#ibcon#enter sib2, iclass 20, count 0 2006.201.17:05:31.23#ibcon#flushed, iclass 20, count 0 2006.201.17:05:31.23#ibcon#about to write, iclass 20, count 0 2006.201.17:05:31.23#ibcon#wrote, iclass 20, count 0 2006.201.17:05:31.23#ibcon#about to read 3, iclass 20, count 0 2006.201.17:05:31.25#ibcon#read 3, iclass 20, count 0 2006.201.17:05:31.25#ibcon#about to read 4, iclass 20, count 0 2006.201.17:05:31.25#ibcon#read 4, iclass 20, count 0 2006.201.17:05:31.25#ibcon#about to read 5, iclass 20, count 0 2006.201.17:05:31.25#ibcon#read 5, iclass 20, count 0 2006.201.17:05:31.25#ibcon#about to read 6, iclass 20, count 0 2006.201.17:05:31.25#ibcon#read 6, iclass 20, count 0 2006.201.17:05:31.25#ibcon#end of sib2, iclass 20, count 0 2006.201.17:05:31.25#ibcon#*mode == 0, iclass 20, count 0 2006.201.17:05:31.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.17:05:31.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.17:05:31.25#ibcon#*before write, iclass 20, count 0 2006.201.17:05:31.25#ibcon#enter sib2, iclass 20, count 0 2006.201.17:05:31.25#ibcon#flushed, iclass 20, count 0 2006.201.17:05:31.25#ibcon#about to write, iclass 20, count 0 2006.201.17:05:31.25#ibcon#wrote, iclass 20, count 0 2006.201.17:05:31.25#ibcon#about to read 3, iclass 20, count 0 2006.201.17:05:31.29#ibcon#read 3, iclass 20, count 0 2006.201.17:05:31.29#ibcon#about to read 4, iclass 20, count 0 2006.201.17:05:31.29#ibcon#read 4, iclass 20, count 0 2006.201.17:05:31.29#ibcon#about to read 5, iclass 20, count 0 2006.201.17:05:31.29#ibcon#read 5, iclass 20, count 0 2006.201.17:05:31.29#ibcon#about to read 6, iclass 20, count 0 2006.201.17:05:31.29#ibcon#read 6, iclass 20, count 0 2006.201.17:05:31.29#ibcon#end of sib2, iclass 20, count 0 2006.201.17:05:31.29#ibcon#*after write, iclass 20, count 0 2006.201.17:05:31.29#ibcon#*before return 0, iclass 20, count 0 2006.201.17:05:31.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:31.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:31.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.17:05:31.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.17:05:31.29$vck44/va=8,4 2006.201.17:05:31.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.17:05:31.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.17:05:31.29#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:31.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:31.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:31.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:31.35#ibcon#enter wrdev, iclass 22, count 2 2006.201.17:05:31.35#ibcon#first serial, iclass 22, count 2 2006.201.17:05:31.35#ibcon#enter sib2, iclass 22, count 2 2006.201.17:05:31.35#ibcon#flushed, iclass 22, count 2 2006.201.17:05:31.35#ibcon#about to write, iclass 22, count 2 2006.201.17:05:31.35#ibcon#wrote, iclass 22, count 2 2006.201.17:05:31.35#ibcon#about to read 3, iclass 22, count 2 2006.201.17:05:31.37#ibcon#read 3, iclass 22, count 2 2006.201.17:05:31.37#ibcon#about to read 4, iclass 22, count 2 2006.201.17:05:31.37#ibcon#read 4, iclass 22, count 2 2006.201.17:05:31.37#ibcon#about to read 5, iclass 22, count 2 2006.201.17:05:31.37#ibcon#read 5, iclass 22, count 2 2006.201.17:05:31.37#ibcon#about to read 6, iclass 22, count 2 2006.201.17:05:31.37#ibcon#read 6, iclass 22, count 2 2006.201.17:05:31.37#ibcon#end of sib2, iclass 22, count 2 2006.201.17:05:31.37#ibcon#*mode == 0, iclass 22, count 2 2006.201.17:05:31.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.17:05:31.37#ibcon#[25=AT08-04\r\n] 2006.201.17:05:31.37#ibcon#*before write, iclass 22, count 2 2006.201.17:05:31.37#ibcon#enter sib2, iclass 22, count 2 2006.201.17:05:31.37#ibcon#flushed, iclass 22, count 2 2006.201.17:05:31.37#ibcon#about to write, iclass 22, count 2 2006.201.17:05:31.37#ibcon#wrote, iclass 22, count 2 2006.201.17:05:31.37#ibcon#about to read 3, iclass 22, count 2 2006.201.17:05:31.40#ibcon#read 3, iclass 22, count 2 2006.201.17:05:31.40#ibcon#about to read 4, iclass 22, count 2 2006.201.17:05:31.40#ibcon#read 4, iclass 22, count 2 2006.201.17:05:31.40#ibcon#about to read 5, iclass 22, count 2 2006.201.17:05:31.40#ibcon#read 5, iclass 22, count 2 2006.201.17:05:31.40#ibcon#about to read 6, iclass 22, count 2 2006.201.17:05:31.40#ibcon#read 6, iclass 22, count 2 2006.201.17:05:31.40#ibcon#end of sib2, iclass 22, count 2 2006.201.17:05:31.40#ibcon#*after write, iclass 22, count 2 2006.201.17:05:31.40#ibcon#*before return 0, iclass 22, count 2 2006.201.17:05:31.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:31.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:31.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.17:05:31.40#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:31.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:31.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:31.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:31.52#ibcon#enter wrdev, iclass 22, count 0 2006.201.17:05:31.52#ibcon#first serial, iclass 22, count 0 2006.201.17:05:31.52#ibcon#enter sib2, iclass 22, count 0 2006.201.17:05:31.52#ibcon#flushed, iclass 22, count 0 2006.201.17:05:31.52#ibcon#about to write, iclass 22, count 0 2006.201.17:05:31.52#ibcon#wrote, iclass 22, count 0 2006.201.17:05:31.52#ibcon#about to read 3, iclass 22, count 0 2006.201.17:05:31.54#ibcon#read 3, iclass 22, count 0 2006.201.17:05:31.54#ibcon#about to read 4, iclass 22, count 0 2006.201.17:05:31.54#ibcon#read 4, iclass 22, count 0 2006.201.17:05:31.54#ibcon#about to read 5, iclass 22, count 0 2006.201.17:05:31.54#ibcon#read 5, iclass 22, count 0 2006.201.17:05:31.54#ibcon#about to read 6, iclass 22, count 0 2006.201.17:05:31.54#ibcon#read 6, iclass 22, count 0 2006.201.17:05:31.54#ibcon#end of sib2, iclass 22, count 0 2006.201.17:05:31.54#ibcon#*mode == 0, iclass 22, count 0 2006.201.17:05:31.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.17:05:31.54#ibcon#[25=USB\r\n] 2006.201.17:05:31.54#ibcon#*before write, iclass 22, count 0 2006.201.17:05:31.54#ibcon#enter sib2, iclass 22, count 0 2006.201.17:05:31.54#ibcon#flushed, iclass 22, count 0 2006.201.17:05:31.54#ibcon#about to write, iclass 22, count 0 2006.201.17:05:31.54#ibcon#wrote, iclass 22, count 0 2006.201.17:05:31.54#ibcon#about to read 3, iclass 22, count 0 2006.201.17:05:31.57#ibcon#read 3, iclass 22, count 0 2006.201.17:05:31.57#ibcon#about to read 4, iclass 22, count 0 2006.201.17:05:31.57#ibcon#read 4, iclass 22, count 0 2006.201.17:05:31.57#ibcon#about to read 5, iclass 22, count 0 2006.201.17:05:31.57#ibcon#read 5, iclass 22, count 0 2006.201.17:05:31.57#ibcon#about to read 6, iclass 22, count 0 2006.201.17:05:31.57#ibcon#read 6, iclass 22, count 0 2006.201.17:05:31.57#ibcon#end of sib2, iclass 22, count 0 2006.201.17:05:31.57#ibcon#*after write, iclass 22, count 0 2006.201.17:05:31.57#ibcon#*before return 0, iclass 22, count 0 2006.201.17:05:31.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:31.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:31.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.17:05:31.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.17:05:31.57$vck44/vblo=1,629.99 2006.201.17:05:31.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.17:05:31.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.17:05:31.57#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:31.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:31.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:31.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:31.57#ibcon#enter wrdev, iclass 24, count 0 2006.201.17:05:31.57#ibcon#first serial, iclass 24, count 0 2006.201.17:05:31.57#ibcon#enter sib2, iclass 24, count 0 2006.201.17:05:31.57#ibcon#flushed, iclass 24, count 0 2006.201.17:05:31.57#ibcon#about to write, iclass 24, count 0 2006.201.17:05:31.57#ibcon#wrote, iclass 24, count 0 2006.201.17:05:31.57#ibcon#about to read 3, iclass 24, count 0 2006.201.17:05:31.59#ibcon#read 3, iclass 24, count 0 2006.201.17:05:31.59#ibcon#about to read 4, iclass 24, count 0 2006.201.17:05:31.59#ibcon#read 4, iclass 24, count 0 2006.201.17:05:31.59#ibcon#about to read 5, iclass 24, count 0 2006.201.17:05:31.59#ibcon#read 5, iclass 24, count 0 2006.201.17:05:31.59#ibcon#about to read 6, iclass 24, count 0 2006.201.17:05:31.59#ibcon#read 6, iclass 24, count 0 2006.201.17:05:31.59#ibcon#end of sib2, iclass 24, count 0 2006.201.17:05:31.59#ibcon#*mode == 0, iclass 24, count 0 2006.201.17:05:31.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.17:05:31.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.17:05:31.59#ibcon#*before write, iclass 24, count 0 2006.201.17:05:31.59#ibcon#enter sib2, iclass 24, count 0 2006.201.17:05:31.59#ibcon#flushed, iclass 24, count 0 2006.201.17:05:31.59#ibcon#about to write, iclass 24, count 0 2006.201.17:05:31.59#ibcon#wrote, iclass 24, count 0 2006.201.17:05:31.59#ibcon#about to read 3, iclass 24, count 0 2006.201.17:05:31.63#ibcon#read 3, iclass 24, count 0 2006.201.17:05:31.63#ibcon#about to read 4, iclass 24, count 0 2006.201.17:05:31.63#ibcon#read 4, iclass 24, count 0 2006.201.17:05:31.63#ibcon#about to read 5, iclass 24, count 0 2006.201.17:05:31.63#ibcon#read 5, iclass 24, count 0 2006.201.17:05:31.63#ibcon#about to read 6, iclass 24, count 0 2006.201.17:05:31.63#ibcon#read 6, iclass 24, count 0 2006.201.17:05:31.63#ibcon#end of sib2, iclass 24, count 0 2006.201.17:05:31.63#ibcon#*after write, iclass 24, count 0 2006.201.17:05:31.63#ibcon#*before return 0, iclass 24, count 0 2006.201.17:05:31.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:31.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:31.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.17:05:31.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.17:05:31.63$vck44/vb=1,4 2006.201.17:05:31.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.17:05:31.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.17:05:31.63#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:31.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:05:31.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:05:31.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:05:31.63#ibcon#enter wrdev, iclass 26, count 2 2006.201.17:05:31.63#ibcon#first serial, iclass 26, count 2 2006.201.17:05:31.63#ibcon#enter sib2, iclass 26, count 2 2006.201.17:05:31.63#ibcon#flushed, iclass 26, count 2 2006.201.17:05:31.63#ibcon#about to write, iclass 26, count 2 2006.201.17:05:31.63#ibcon#wrote, iclass 26, count 2 2006.201.17:05:31.63#ibcon#about to read 3, iclass 26, count 2 2006.201.17:05:31.65#ibcon#read 3, iclass 26, count 2 2006.201.17:05:31.65#ibcon#about to read 4, iclass 26, count 2 2006.201.17:05:31.65#ibcon#read 4, iclass 26, count 2 2006.201.17:05:31.65#ibcon#about to read 5, iclass 26, count 2 2006.201.17:05:31.65#ibcon#read 5, iclass 26, count 2 2006.201.17:05:31.65#ibcon#about to read 6, iclass 26, count 2 2006.201.17:05:31.65#ibcon#read 6, iclass 26, count 2 2006.201.17:05:31.65#ibcon#end of sib2, iclass 26, count 2 2006.201.17:05:31.65#ibcon#*mode == 0, iclass 26, count 2 2006.201.17:05:31.65#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.17:05:31.65#ibcon#[27=AT01-04\r\n] 2006.201.17:05:31.65#ibcon#*before write, iclass 26, count 2 2006.201.17:05:31.65#ibcon#enter sib2, iclass 26, count 2 2006.201.17:05:31.65#ibcon#flushed, iclass 26, count 2 2006.201.17:05:31.65#ibcon#about to write, iclass 26, count 2 2006.201.17:05:31.65#ibcon#wrote, iclass 26, count 2 2006.201.17:05:31.65#ibcon#about to read 3, iclass 26, count 2 2006.201.17:05:31.68#ibcon#read 3, iclass 26, count 2 2006.201.17:05:31.68#ibcon#about to read 4, iclass 26, count 2 2006.201.17:05:31.68#ibcon#read 4, iclass 26, count 2 2006.201.17:05:31.68#ibcon#about to read 5, iclass 26, count 2 2006.201.17:05:31.68#ibcon#read 5, iclass 26, count 2 2006.201.17:05:31.68#ibcon#about to read 6, iclass 26, count 2 2006.201.17:05:31.68#ibcon#read 6, iclass 26, count 2 2006.201.17:05:31.68#ibcon#end of sib2, iclass 26, count 2 2006.201.17:05:31.68#ibcon#*after write, iclass 26, count 2 2006.201.17:05:31.68#ibcon#*before return 0, iclass 26, count 2 2006.201.17:05:31.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:05:31.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:05:31.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.17:05:31.68#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:31.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:05:31.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:05:31.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:05:31.80#ibcon#enter wrdev, iclass 26, count 0 2006.201.17:05:31.80#ibcon#first serial, iclass 26, count 0 2006.201.17:05:31.80#ibcon#enter sib2, iclass 26, count 0 2006.201.17:05:31.80#ibcon#flushed, iclass 26, count 0 2006.201.17:05:31.80#ibcon#about to write, iclass 26, count 0 2006.201.17:05:31.80#ibcon#wrote, iclass 26, count 0 2006.201.17:05:31.80#ibcon#about to read 3, iclass 26, count 0 2006.201.17:05:31.82#ibcon#read 3, iclass 26, count 0 2006.201.17:05:31.82#ibcon#about to read 4, iclass 26, count 0 2006.201.17:05:31.82#ibcon#read 4, iclass 26, count 0 2006.201.17:05:31.82#ibcon#about to read 5, iclass 26, count 0 2006.201.17:05:31.82#ibcon#read 5, iclass 26, count 0 2006.201.17:05:31.82#ibcon#about to read 6, iclass 26, count 0 2006.201.17:05:31.82#ibcon#read 6, iclass 26, count 0 2006.201.17:05:31.82#ibcon#end of sib2, iclass 26, count 0 2006.201.17:05:31.82#ibcon#*mode == 0, iclass 26, count 0 2006.201.17:05:31.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.17:05:31.82#ibcon#[27=USB\r\n] 2006.201.17:05:31.82#ibcon#*before write, iclass 26, count 0 2006.201.17:05:31.82#ibcon#enter sib2, iclass 26, count 0 2006.201.17:05:31.82#ibcon#flushed, iclass 26, count 0 2006.201.17:05:31.82#ibcon#about to write, iclass 26, count 0 2006.201.17:05:31.82#ibcon#wrote, iclass 26, count 0 2006.201.17:05:31.82#ibcon#about to read 3, iclass 26, count 0 2006.201.17:05:31.85#ibcon#read 3, iclass 26, count 0 2006.201.17:05:31.85#ibcon#about to read 4, iclass 26, count 0 2006.201.17:05:31.85#ibcon#read 4, iclass 26, count 0 2006.201.17:05:31.85#ibcon#about to read 5, iclass 26, count 0 2006.201.17:05:31.85#ibcon#read 5, iclass 26, count 0 2006.201.17:05:31.85#ibcon#about to read 6, iclass 26, count 0 2006.201.17:05:31.85#ibcon#read 6, iclass 26, count 0 2006.201.17:05:31.85#ibcon#end of sib2, iclass 26, count 0 2006.201.17:05:31.85#ibcon#*after write, iclass 26, count 0 2006.201.17:05:31.85#ibcon#*before return 0, iclass 26, count 0 2006.201.17:05:31.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:05:31.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:05:31.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.17:05:31.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.17:05:31.85$vck44/vblo=2,634.99 2006.201.17:05:31.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.17:05:31.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.17:05:31.85#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:31.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:31.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:31.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:31.85#ibcon#enter wrdev, iclass 28, count 0 2006.201.17:05:31.85#ibcon#first serial, iclass 28, count 0 2006.201.17:05:31.85#ibcon#enter sib2, iclass 28, count 0 2006.201.17:05:31.85#ibcon#flushed, iclass 28, count 0 2006.201.17:05:31.85#ibcon#about to write, iclass 28, count 0 2006.201.17:05:31.85#ibcon#wrote, iclass 28, count 0 2006.201.17:05:31.85#ibcon#about to read 3, iclass 28, count 0 2006.201.17:05:31.87#ibcon#read 3, iclass 28, count 0 2006.201.17:05:31.87#ibcon#about to read 4, iclass 28, count 0 2006.201.17:05:31.87#ibcon#read 4, iclass 28, count 0 2006.201.17:05:31.87#ibcon#about to read 5, iclass 28, count 0 2006.201.17:05:31.87#ibcon#read 5, iclass 28, count 0 2006.201.17:05:31.87#ibcon#about to read 6, iclass 28, count 0 2006.201.17:05:31.87#ibcon#read 6, iclass 28, count 0 2006.201.17:05:31.87#ibcon#end of sib2, iclass 28, count 0 2006.201.17:05:31.87#ibcon#*mode == 0, iclass 28, count 0 2006.201.17:05:31.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.17:05:31.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.17:05:31.87#ibcon#*before write, iclass 28, count 0 2006.201.17:05:31.87#ibcon#enter sib2, iclass 28, count 0 2006.201.17:05:31.87#ibcon#flushed, iclass 28, count 0 2006.201.17:05:31.87#ibcon#about to write, iclass 28, count 0 2006.201.17:05:31.87#ibcon#wrote, iclass 28, count 0 2006.201.17:05:31.87#ibcon#about to read 3, iclass 28, count 0 2006.201.17:05:31.91#ibcon#read 3, iclass 28, count 0 2006.201.17:05:31.91#ibcon#about to read 4, iclass 28, count 0 2006.201.17:05:31.91#ibcon#read 4, iclass 28, count 0 2006.201.17:05:31.91#ibcon#about to read 5, iclass 28, count 0 2006.201.17:05:31.91#ibcon#read 5, iclass 28, count 0 2006.201.17:05:31.91#ibcon#about to read 6, iclass 28, count 0 2006.201.17:05:31.91#ibcon#read 6, iclass 28, count 0 2006.201.17:05:31.91#ibcon#end of sib2, iclass 28, count 0 2006.201.17:05:31.91#ibcon#*after write, iclass 28, count 0 2006.201.17:05:31.91#ibcon#*before return 0, iclass 28, count 0 2006.201.17:05:31.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:31.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:05:31.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.17:05:31.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.17:05:31.91$vck44/vb=2,5 2006.201.17:05:31.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.17:05:31.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.17:05:31.91#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:31.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:31.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:31.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:31.97#ibcon#enter wrdev, iclass 30, count 2 2006.201.17:05:31.97#ibcon#first serial, iclass 30, count 2 2006.201.17:05:31.97#ibcon#enter sib2, iclass 30, count 2 2006.201.17:05:31.97#ibcon#flushed, iclass 30, count 2 2006.201.17:05:31.97#ibcon#about to write, iclass 30, count 2 2006.201.17:05:31.97#ibcon#wrote, iclass 30, count 2 2006.201.17:05:31.97#ibcon#about to read 3, iclass 30, count 2 2006.201.17:05:31.99#ibcon#read 3, iclass 30, count 2 2006.201.17:05:31.99#ibcon#about to read 4, iclass 30, count 2 2006.201.17:05:31.99#ibcon#read 4, iclass 30, count 2 2006.201.17:05:31.99#ibcon#about to read 5, iclass 30, count 2 2006.201.17:05:31.99#ibcon#read 5, iclass 30, count 2 2006.201.17:05:31.99#ibcon#about to read 6, iclass 30, count 2 2006.201.17:05:31.99#ibcon#read 6, iclass 30, count 2 2006.201.17:05:31.99#ibcon#end of sib2, iclass 30, count 2 2006.201.17:05:31.99#ibcon#*mode == 0, iclass 30, count 2 2006.201.17:05:31.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.17:05:31.99#ibcon#[27=AT02-05\r\n] 2006.201.17:05:31.99#ibcon#*before write, iclass 30, count 2 2006.201.17:05:31.99#ibcon#enter sib2, iclass 30, count 2 2006.201.17:05:31.99#ibcon#flushed, iclass 30, count 2 2006.201.17:05:31.99#ibcon#about to write, iclass 30, count 2 2006.201.17:05:31.99#ibcon#wrote, iclass 30, count 2 2006.201.17:05:31.99#ibcon#about to read 3, iclass 30, count 2 2006.201.17:05:32.02#ibcon#read 3, iclass 30, count 2 2006.201.17:05:32.02#ibcon#about to read 4, iclass 30, count 2 2006.201.17:05:32.02#ibcon#read 4, iclass 30, count 2 2006.201.17:05:32.02#ibcon#about to read 5, iclass 30, count 2 2006.201.17:05:32.02#ibcon#read 5, iclass 30, count 2 2006.201.17:05:32.02#ibcon#about to read 6, iclass 30, count 2 2006.201.17:05:32.02#ibcon#read 6, iclass 30, count 2 2006.201.17:05:32.02#ibcon#end of sib2, iclass 30, count 2 2006.201.17:05:32.02#ibcon#*after write, iclass 30, count 2 2006.201.17:05:32.02#ibcon#*before return 0, iclass 30, count 2 2006.201.17:05:32.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:32.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:05:32.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.17:05:32.02#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:32.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:32.06#abcon#<5=/00 0.2 0.6 20.771001002.6\r\n> 2006.201.17:05:32.08#abcon#{5=INTERFACE CLEAR} 2006.201.17:05:32.14#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:05:32.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:32.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:32.14#ibcon#enter wrdev, iclass 30, count 0 2006.201.17:05:32.14#ibcon#first serial, iclass 30, count 0 2006.201.17:05:32.14#ibcon#enter sib2, iclass 30, count 0 2006.201.17:05:32.14#ibcon#flushed, iclass 30, count 0 2006.201.17:05:32.14#ibcon#about to write, iclass 30, count 0 2006.201.17:05:32.14#ibcon#wrote, iclass 30, count 0 2006.201.17:05:32.14#ibcon#about to read 3, iclass 30, count 0 2006.201.17:05:32.16#ibcon#read 3, iclass 30, count 0 2006.201.17:05:32.16#ibcon#about to read 4, iclass 30, count 0 2006.201.17:05:32.16#ibcon#read 4, iclass 30, count 0 2006.201.17:05:32.16#ibcon#about to read 5, iclass 30, count 0 2006.201.17:05:32.16#ibcon#read 5, iclass 30, count 0 2006.201.17:05:32.16#ibcon#about to read 6, iclass 30, count 0 2006.201.17:05:32.16#ibcon#read 6, iclass 30, count 0 2006.201.17:05:32.16#ibcon#end of sib2, iclass 30, count 0 2006.201.17:05:32.16#ibcon#*mode == 0, iclass 30, count 0 2006.201.17:05:32.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.17:05:32.16#ibcon#[27=USB\r\n] 2006.201.17:05:32.16#ibcon#*before write, iclass 30, count 0 2006.201.17:05:32.16#ibcon#enter sib2, iclass 30, count 0 2006.201.17:05:32.16#ibcon#flushed, iclass 30, count 0 2006.201.17:05:32.16#ibcon#about to write, iclass 30, count 0 2006.201.17:05:32.16#ibcon#wrote, iclass 30, count 0 2006.201.17:05:32.16#ibcon#about to read 3, iclass 30, count 0 2006.201.17:05:32.19#ibcon#read 3, iclass 30, count 0 2006.201.17:05:32.19#ibcon#about to read 4, iclass 30, count 0 2006.201.17:05:32.19#ibcon#read 4, iclass 30, count 0 2006.201.17:05:32.19#ibcon#about to read 5, iclass 30, count 0 2006.201.17:05:32.19#ibcon#read 5, iclass 30, count 0 2006.201.17:05:32.19#ibcon#about to read 6, iclass 30, count 0 2006.201.17:05:32.19#ibcon#read 6, iclass 30, count 0 2006.201.17:05:32.19#ibcon#end of sib2, iclass 30, count 0 2006.201.17:05:32.19#ibcon#*after write, iclass 30, count 0 2006.201.17:05:32.19#ibcon#*before return 0, iclass 30, count 0 2006.201.17:05:32.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:32.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:05:32.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.17:05:32.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.17:05:32.19$vck44/vblo=3,649.99 2006.201.17:05:32.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.17:05:32.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.17:05:32.19#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:32.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:32.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:32.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:32.19#ibcon#enter wrdev, iclass 36, count 0 2006.201.17:05:32.19#ibcon#first serial, iclass 36, count 0 2006.201.17:05:32.19#ibcon#enter sib2, iclass 36, count 0 2006.201.17:05:32.19#ibcon#flushed, iclass 36, count 0 2006.201.17:05:32.19#ibcon#about to write, iclass 36, count 0 2006.201.17:05:32.19#ibcon#wrote, iclass 36, count 0 2006.201.17:05:32.19#ibcon#about to read 3, iclass 36, count 0 2006.201.17:05:32.21#ibcon#read 3, iclass 36, count 0 2006.201.17:05:32.21#ibcon#about to read 4, iclass 36, count 0 2006.201.17:05:32.21#ibcon#read 4, iclass 36, count 0 2006.201.17:05:32.21#ibcon#about to read 5, iclass 36, count 0 2006.201.17:05:32.21#ibcon#read 5, iclass 36, count 0 2006.201.17:05:32.21#ibcon#about to read 6, iclass 36, count 0 2006.201.17:05:32.21#ibcon#read 6, iclass 36, count 0 2006.201.17:05:32.21#ibcon#end of sib2, iclass 36, count 0 2006.201.17:05:32.21#ibcon#*mode == 0, iclass 36, count 0 2006.201.17:05:32.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.17:05:32.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.17:05:32.21#ibcon#*before write, iclass 36, count 0 2006.201.17:05:32.21#ibcon#enter sib2, iclass 36, count 0 2006.201.17:05:32.21#ibcon#flushed, iclass 36, count 0 2006.201.17:05:32.21#ibcon#about to write, iclass 36, count 0 2006.201.17:05:32.21#ibcon#wrote, iclass 36, count 0 2006.201.17:05:32.21#ibcon#about to read 3, iclass 36, count 0 2006.201.17:05:32.25#ibcon#read 3, iclass 36, count 0 2006.201.17:05:32.25#ibcon#about to read 4, iclass 36, count 0 2006.201.17:05:32.25#ibcon#read 4, iclass 36, count 0 2006.201.17:05:32.25#ibcon#about to read 5, iclass 36, count 0 2006.201.17:05:32.25#ibcon#read 5, iclass 36, count 0 2006.201.17:05:32.25#ibcon#about to read 6, iclass 36, count 0 2006.201.17:05:32.25#ibcon#read 6, iclass 36, count 0 2006.201.17:05:32.25#ibcon#end of sib2, iclass 36, count 0 2006.201.17:05:32.25#ibcon#*after write, iclass 36, count 0 2006.201.17:05:32.25#ibcon#*before return 0, iclass 36, count 0 2006.201.17:05:32.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:32.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:05:32.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.17:05:32.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.17:05:32.25$vck44/vb=3,4 2006.201.17:05:32.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.17:05:32.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.17:05:32.25#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:32.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:32.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:32.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:32.31#ibcon#enter wrdev, iclass 38, count 2 2006.201.17:05:32.31#ibcon#first serial, iclass 38, count 2 2006.201.17:05:32.31#ibcon#enter sib2, iclass 38, count 2 2006.201.17:05:32.31#ibcon#flushed, iclass 38, count 2 2006.201.17:05:32.31#ibcon#about to write, iclass 38, count 2 2006.201.17:05:32.31#ibcon#wrote, iclass 38, count 2 2006.201.17:05:32.31#ibcon#about to read 3, iclass 38, count 2 2006.201.17:05:32.33#ibcon#read 3, iclass 38, count 2 2006.201.17:05:32.33#ibcon#about to read 4, iclass 38, count 2 2006.201.17:05:32.33#ibcon#read 4, iclass 38, count 2 2006.201.17:05:32.33#ibcon#about to read 5, iclass 38, count 2 2006.201.17:05:32.33#ibcon#read 5, iclass 38, count 2 2006.201.17:05:32.33#ibcon#about to read 6, iclass 38, count 2 2006.201.17:05:32.33#ibcon#read 6, iclass 38, count 2 2006.201.17:05:32.33#ibcon#end of sib2, iclass 38, count 2 2006.201.17:05:32.33#ibcon#*mode == 0, iclass 38, count 2 2006.201.17:05:32.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.17:05:32.33#ibcon#[27=AT03-04\r\n] 2006.201.17:05:32.33#ibcon#*before write, iclass 38, count 2 2006.201.17:05:32.33#ibcon#enter sib2, iclass 38, count 2 2006.201.17:05:32.33#ibcon#flushed, iclass 38, count 2 2006.201.17:05:32.33#ibcon#about to write, iclass 38, count 2 2006.201.17:05:32.33#ibcon#wrote, iclass 38, count 2 2006.201.17:05:32.33#ibcon#about to read 3, iclass 38, count 2 2006.201.17:05:32.36#ibcon#read 3, iclass 38, count 2 2006.201.17:05:32.36#ibcon#about to read 4, iclass 38, count 2 2006.201.17:05:32.36#ibcon#read 4, iclass 38, count 2 2006.201.17:05:32.36#ibcon#about to read 5, iclass 38, count 2 2006.201.17:05:32.36#ibcon#read 5, iclass 38, count 2 2006.201.17:05:32.36#ibcon#about to read 6, iclass 38, count 2 2006.201.17:05:32.36#ibcon#read 6, iclass 38, count 2 2006.201.17:05:32.36#ibcon#end of sib2, iclass 38, count 2 2006.201.17:05:32.36#ibcon#*after write, iclass 38, count 2 2006.201.17:05:32.36#ibcon#*before return 0, iclass 38, count 2 2006.201.17:05:32.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:32.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:05:32.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.17:05:32.36#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:32.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:32.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:32.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:32.48#ibcon#enter wrdev, iclass 38, count 0 2006.201.17:05:32.48#ibcon#first serial, iclass 38, count 0 2006.201.17:05:32.48#ibcon#enter sib2, iclass 38, count 0 2006.201.17:05:32.48#ibcon#flushed, iclass 38, count 0 2006.201.17:05:32.48#ibcon#about to write, iclass 38, count 0 2006.201.17:05:32.48#ibcon#wrote, iclass 38, count 0 2006.201.17:05:32.48#ibcon#about to read 3, iclass 38, count 0 2006.201.17:05:32.50#ibcon#read 3, iclass 38, count 0 2006.201.17:05:32.50#ibcon#about to read 4, iclass 38, count 0 2006.201.17:05:32.50#ibcon#read 4, iclass 38, count 0 2006.201.17:05:32.50#ibcon#about to read 5, iclass 38, count 0 2006.201.17:05:32.50#ibcon#read 5, iclass 38, count 0 2006.201.17:05:32.50#ibcon#about to read 6, iclass 38, count 0 2006.201.17:05:32.50#ibcon#read 6, iclass 38, count 0 2006.201.17:05:32.50#ibcon#end of sib2, iclass 38, count 0 2006.201.17:05:32.50#ibcon#*mode == 0, iclass 38, count 0 2006.201.17:05:32.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.17:05:32.50#ibcon#[27=USB\r\n] 2006.201.17:05:32.50#ibcon#*before write, iclass 38, count 0 2006.201.17:05:32.50#ibcon#enter sib2, iclass 38, count 0 2006.201.17:05:32.50#ibcon#flushed, iclass 38, count 0 2006.201.17:05:32.50#ibcon#about to write, iclass 38, count 0 2006.201.17:05:32.50#ibcon#wrote, iclass 38, count 0 2006.201.17:05:32.50#ibcon#about to read 3, iclass 38, count 0 2006.201.17:05:32.53#ibcon#read 3, iclass 38, count 0 2006.201.17:05:32.53#ibcon#about to read 4, iclass 38, count 0 2006.201.17:05:32.53#ibcon#read 4, iclass 38, count 0 2006.201.17:05:32.53#ibcon#about to read 5, iclass 38, count 0 2006.201.17:05:32.53#ibcon#read 5, iclass 38, count 0 2006.201.17:05:32.53#ibcon#about to read 6, iclass 38, count 0 2006.201.17:05:32.53#ibcon#read 6, iclass 38, count 0 2006.201.17:05:32.53#ibcon#end of sib2, iclass 38, count 0 2006.201.17:05:32.53#ibcon#*after write, iclass 38, count 0 2006.201.17:05:32.53#ibcon#*before return 0, iclass 38, count 0 2006.201.17:05:32.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:32.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:05:32.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.17:05:32.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.17:05:32.53$vck44/vblo=4,679.99 2006.201.17:05:32.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.17:05:32.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.17:05:32.53#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:32.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:32.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:32.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:32.53#ibcon#enter wrdev, iclass 40, count 0 2006.201.17:05:32.53#ibcon#first serial, iclass 40, count 0 2006.201.17:05:32.53#ibcon#enter sib2, iclass 40, count 0 2006.201.17:05:32.53#ibcon#flushed, iclass 40, count 0 2006.201.17:05:32.53#ibcon#about to write, iclass 40, count 0 2006.201.17:05:32.53#ibcon#wrote, iclass 40, count 0 2006.201.17:05:32.53#ibcon#about to read 3, iclass 40, count 0 2006.201.17:05:32.55#ibcon#read 3, iclass 40, count 0 2006.201.17:05:32.55#ibcon#about to read 4, iclass 40, count 0 2006.201.17:05:32.55#ibcon#read 4, iclass 40, count 0 2006.201.17:05:32.55#ibcon#about to read 5, iclass 40, count 0 2006.201.17:05:32.55#ibcon#read 5, iclass 40, count 0 2006.201.17:05:32.55#ibcon#about to read 6, iclass 40, count 0 2006.201.17:05:32.55#ibcon#read 6, iclass 40, count 0 2006.201.17:05:32.55#ibcon#end of sib2, iclass 40, count 0 2006.201.17:05:32.55#ibcon#*mode == 0, iclass 40, count 0 2006.201.17:05:32.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.17:05:32.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.17:05:32.55#ibcon#*before write, iclass 40, count 0 2006.201.17:05:32.55#ibcon#enter sib2, iclass 40, count 0 2006.201.17:05:32.55#ibcon#flushed, iclass 40, count 0 2006.201.17:05:32.55#ibcon#about to write, iclass 40, count 0 2006.201.17:05:32.55#ibcon#wrote, iclass 40, count 0 2006.201.17:05:32.55#ibcon#about to read 3, iclass 40, count 0 2006.201.17:05:32.59#ibcon#read 3, iclass 40, count 0 2006.201.17:05:32.59#ibcon#about to read 4, iclass 40, count 0 2006.201.17:05:32.59#ibcon#read 4, iclass 40, count 0 2006.201.17:05:32.59#ibcon#about to read 5, iclass 40, count 0 2006.201.17:05:32.59#ibcon#read 5, iclass 40, count 0 2006.201.17:05:32.59#ibcon#about to read 6, iclass 40, count 0 2006.201.17:05:32.59#ibcon#read 6, iclass 40, count 0 2006.201.17:05:32.59#ibcon#end of sib2, iclass 40, count 0 2006.201.17:05:32.59#ibcon#*after write, iclass 40, count 0 2006.201.17:05:32.59#ibcon#*before return 0, iclass 40, count 0 2006.201.17:05:32.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:32.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:05:32.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.17:05:32.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.17:05:32.59$vck44/vb=4,5 2006.201.17:05:32.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.17:05:32.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.17:05:32.59#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:32.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:32.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:32.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:32.65#ibcon#enter wrdev, iclass 4, count 2 2006.201.17:05:32.65#ibcon#first serial, iclass 4, count 2 2006.201.17:05:32.65#ibcon#enter sib2, iclass 4, count 2 2006.201.17:05:32.65#ibcon#flushed, iclass 4, count 2 2006.201.17:05:32.65#ibcon#about to write, iclass 4, count 2 2006.201.17:05:32.65#ibcon#wrote, iclass 4, count 2 2006.201.17:05:32.65#ibcon#about to read 3, iclass 4, count 2 2006.201.17:05:32.67#ibcon#read 3, iclass 4, count 2 2006.201.17:05:32.67#ibcon#about to read 4, iclass 4, count 2 2006.201.17:05:32.67#ibcon#read 4, iclass 4, count 2 2006.201.17:05:32.67#ibcon#about to read 5, iclass 4, count 2 2006.201.17:05:32.67#ibcon#read 5, iclass 4, count 2 2006.201.17:05:32.67#ibcon#about to read 6, iclass 4, count 2 2006.201.17:05:32.67#ibcon#read 6, iclass 4, count 2 2006.201.17:05:32.67#ibcon#end of sib2, iclass 4, count 2 2006.201.17:05:32.67#ibcon#*mode == 0, iclass 4, count 2 2006.201.17:05:32.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.17:05:32.67#ibcon#[27=AT04-05\r\n] 2006.201.17:05:32.67#ibcon#*before write, iclass 4, count 2 2006.201.17:05:32.67#ibcon#enter sib2, iclass 4, count 2 2006.201.17:05:32.67#ibcon#flushed, iclass 4, count 2 2006.201.17:05:32.67#ibcon#about to write, iclass 4, count 2 2006.201.17:05:32.67#ibcon#wrote, iclass 4, count 2 2006.201.17:05:32.67#ibcon#about to read 3, iclass 4, count 2 2006.201.17:05:32.70#ibcon#read 3, iclass 4, count 2 2006.201.17:05:32.70#ibcon#about to read 4, iclass 4, count 2 2006.201.17:05:32.70#ibcon#read 4, iclass 4, count 2 2006.201.17:05:32.70#ibcon#about to read 5, iclass 4, count 2 2006.201.17:05:32.70#ibcon#read 5, iclass 4, count 2 2006.201.17:05:32.70#ibcon#about to read 6, iclass 4, count 2 2006.201.17:05:32.70#ibcon#read 6, iclass 4, count 2 2006.201.17:05:32.70#ibcon#end of sib2, iclass 4, count 2 2006.201.17:05:32.70#ibcon#*after write, iclass 4, count 2 2006.201.17:05:32.70#ibcon#*before return 0, iclass 4, count 2 2006.201.17:05:32.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:32.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:05:32.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.17:05:32.70#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:32.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:32.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:32.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:32.82#ibcon#enter wrdev, iclass 4, count 0 2006.201.17:05:32.82#ibcon#first serial, iclass 4, count 0 2006.201.17:05:32.82#ibcon#enter sib2, iclass 4, count 0 2006.201.17:05:32.82#ibcon#flushed, iclass 4, count 0 2006.201.17:05:32.82#ibcon#about to write, iclass 4, count 0 2006.201.17:05:32.82#ibcon#wrote, iclass 4, count 0 2006.201.17:05:32.82#ibcon#about to read 3, iclass 4, count 0 2006.201.17:05:32.84#ibcon#read 3, iclass 4, count 0 2006.201.17:05:32.84#ibcon#about to read 4, iclass 4, count 0 2006.201.17:05:32.84#ibcon#read 4, iclass 4, count 0 2006.201.17:05:32.84#ibcon#about to read 5, iclass 4, count 0 2006.201.17:05:32.84#ibcon#read 5, iclass 4, count 0 2006.201.17:05:32.84#ibcon#about to read 6, iclass 4, count 0 2006.201.17:05:32.84#ibcon#read 6, iclass 4, count 0 2006.201.17:05:32.84#ibcon#end of sib2, iclass 4, count 0 2006.201.17:05:32.84#ibcon#*mode == 0, iclass 4, count 0 2006.201.17:05:32.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.17:05:32.84#ibcon#[27=USB\r\n] 2006.201.17:05:32.84#ibcon#*before write, iclass 4, count 0 2006.201.17:05:32.84#ibcon#enter sib2, iclass 4, count 0 2006.201.17:05:32.84#ibcon#flushed, iclass 4, count 0 2006.201.17:05:32.84#ibcon#about to write, iclass 4, count 0 2006.201.17:05:32.84#ibcon#wrote, iclass 4, count 0 2006.201.17:05:32.84#ibcon#about to read 3, iclass 4, count 0 2006.201.17:05:32.87#ibcon#read 3, iclass 4, count 0 2006.201.17:05:32.87#ibcon#about to read 4, iclass 4, count 0 2006.201.17:05:32.87#ibcon#read 4, iclass 4, count 0 2006.201.17:05:32.87#ibcon#about to read 5, iclass 4, count 0 2006.201.17:05:32.87#ibcon#read 5, iclass 4, count 0 2006.201.17:05:32.87#ibcon#about to read 6, iclass 4, count 0 2006.201.17:05:32.87#ibcon#read 6, iclass 4, count 0 2006.201.17:05:32.87#ibcon#end of sib2, iclass 4, count 0 2006.201.17:05:32.87#ibcon#*after write, iclass 4, count 0 2006.201.17:05:32.87#ibcon#*before return 0, iclass 4, count 0 2006.201.17:05:32.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:32.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:05:32.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.17:05:32.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.17:05:32.87$vck44/vblo=5,709.99 2006.201.17:05:32.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.17:05:32.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.17:05:32.87#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:32.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:32.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:32.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:32.87#ibcon#enter wrdev, iclass 6, count 0 2006.201.17:05:32.87#ibcon#first serial, iclass 6, count 0 2006.201.17:05:32.87#ibcon#enter sib2, iclass 6, count 0 2006.201.17:05:32.87#ibcon#flushed, iclass 6, count 0 2006.201.17:05:32.87#ibcon#about to write, iclass 6, count 0 2006.201.17:05:32.87#ibcon#wrote, iclass 6, count 0 2006.201.17:05:32.87#ibcon#about to read 3, iclass 6, count 0 2006.201.17:05:32.89#ibcon#read 3, iclass 6, count 0 2006.201.17:05:32.89#ibcon#about to read 4, iclass 6, count 0 2006.201.17:05:32.89#ibcon#read 4, iclass 6, count 0 2006.201.17:05:32.89#ibcon#about to read 5, iclass 6, count 0 2006.201.17:05:32.89#ibcon#read 5, iclass 6, count 0 2006.201.17:05:32.89#ibcon#about to read 6, iclass 6, count 0 2006.201.17:05:32.89#ibcon#read 6, iclass 6, count 0 2006.201.17:05:32.89#ibcon#end of sib2, iclass 6, count 0 2006.201.17:05:32.89#ibcon#*mode == 0, iclass 6, count 0 2006.201.17:05:32.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.17:05:32.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.17:05:32.89#ibcon#*before write, iclass 6, count 0 2006.201.17:05:32.89#ibcon#enter sib2, iclass 6, count 0 2006.201.17:05:32.89#ibcon#flushed, iclass 6, count 0 2006.201.17:05:32.89#ibcon#about to write, iclass 6, count 0 2006.201.17:05:32.89#ibcon#wrote, iclass 6, count 0 2006.201.17:05:32.89#ibcon#about to read 3, iclass 6, count 0 2006.201.17:05:32.93#ibcon#read 3, iclass 6, count 0 2006.201.17:05:32.93#ibcon#about to read 4, iclass 6, count 0 2006.201.17:05:32.93#ibcon#read 4, iclass 6, count 0 2006.201.17:05:32.93#ibcon#about to read 5, iclass 6, count 0 2006.201.17:05:32.93#ibcon#read 5, iclass 6, count 0 2006.201.17:05:32.93#ibcon#about to read 6, iclass 6, count 0 2006.201.17:05:32.93#ibcon#read 6, iclass 6, count 0 2006.201.17:05:32.93#ibcon#end of sib2, iclass 6, count 0 2006.201.17:05:32.93#ibcon#*after write, iclass 6, count 0 2006.201.17:05:32.93#ibcon#*before return 0, iclass 6, count 0 2006.201.17:05:32.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:32.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:05:32.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.17:05:32.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.17:05:32.93$vck44/vb=5,4 2006.201.17:05:32.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.17:05:32.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.17:05:32.93#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:32.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:32.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:32.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:32.99#ibcon#enter wrdev, iclass 10, count 2 2006.201.17:05:32.99#ibcon#first serial, iclass 10, count 2 2006.201.17:05:32.99#ibcon#enter sib2, iclass 10, count 2 2006.201.17:05:32.99#ibcon#flushed, iclass 10, count 2 2006.201.17:05:32.99#ibcon#about to write, iclass 10, count 2 2006.201.17:05:32.99#ibcon#wrote, iclass 10, count 2 2006.201.17:05:32.99#ibcon#about to read 3, iclass 10, count 2 2006.201.17:05:33.01#ibcon#read 3, iclass 10, count 2 2006.201.17:05:33.01#ibcon#about to read 4, iclass 10, count 2 2006.201.17:05:33.01#ibcon#read 4, iclass 10, count 2 2006.201.17:05:33.01#ibcon#about to read 5, iclass 10, count 2 2006.201.17:05:33.01#ibcon#read 5, iclass 10, count 2 2006.201.17:05:33.01#ibcon#about to read 6, iclass 10, count 2 2006.201.17:05:33.01#ibcon#read 6, iclass 10, count 2 2006.201.17:05:33.01#ibcon#end of sib2, iclass 10, count 2 2006.201.17:05:33.01#ibcon#*mode == 0, iclass 10, count 2 2006.201.17:05:33.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.17:05:33.01#ibcon#[27=AT05-04\r\n] 2006.201.17:05:33.01#ibcon#*before write, iclass 10, count 2 2006.201.17:05:33.01#ibcon#enter sib2, iclass 10, count 2 2006.201.17:05:33.01#ibcon#flushed, iclass 10, count 2 2006.201.17:05:33.01#ibcon#about to write, iclass 10, count 2 2006.201.17:05:33.01#ibcon#wrote, iclass 10, count 2 2006.201.17:05:33.01#ibcon#about to read 3, iclass 10, count 2 2006.201.17:05:33.04#ibcon#read 3, iclass 10, count 2 2006.201.17:05:33.04#ibcon#about to read 4, iclass 10, count 2 2006.201.17:05:33.04#ibcon#read 4, iclass 10, count 2 2006.201.17:05:33.04#ibcon#about to read 5, iclass 10, count 2 2006.201.17:05:33.04#ibcon#read 5, iclass 10, count 2 2006.201.17:05:33.04#ibcon#about to read 6, iclass 10, count 2 2006.201.17:05:33.04#ibcon#read 6, iclass 10, count 2 2006.201.17:05:33.04#ibcon#end of sib2, iclass 10, count 2 2006.201.17:05:33.04#ibcon#*after write, iclass 10, count 2 2006.201.17:05:33.04#ibcon#*before return 0, iclass 10, count 2 2006.201.17:05:33.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:33.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:05:33.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.17:05:33.04#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:33.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:33.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:33.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:33.16#ibcon#enter wrdev, iclass 10, count 0 2006.201.17:05:33.16#ibcon#first serial, iclass 10, count 0 2006.201.17:05:33.16#ibcon#enter sib2, iclass 10, count 0 2006.201.17:05:33.16#ibcon#flushed, iclass 10, count 0 2006.201.17:05:33.16#ibcon#about to write, iclass 10, count 0 2006.201.17:05:33.16#ibcon#wrote, iclass 10, count 0 2006.201.17:05:33.16#ibcon#about to read 3, iclass 10, count 0 2006.201.17:05:33.18#ibcon#read 3, iclass 10, count 0 2006.201.17:05:33.18#ibcon#about to read 4, iclass 10, count 0 2006.201.17:05:33.18#ibcon#read 4, iclass 10, count 0 2006.201.17:05:33.18#ibcon#about to read 5, iclass 10, count 0 2006.201.17:05:33.18#ibcon#read 5, iclass 10, count 0 2006.201.17:05:33.18#ibcon#about to read 6, iclass 10, count 0 2006.201.17:05:33.18#ibcon#read 6, iclass 10, count 0 2006.201.17:05:33.18#ibcon#end of sib2, iclass 10, count 0 2006.201.17:05:33.18#ibcon#*mode == 0, iclass 10, count 0 2006.201.17:05:33.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.17:05:33.18#ibcon#[27=USB\r\n] 2006.201.17:05:33.18#ibcon#*before write, iclass 10, count 0 2006.201.17:05:33.18#ibcon#enter sib2, iclass 10, count 0 2006.201.17:05:33.18#ibcon#flushed, iclass 10, count 0 2006.201.17:05:33.18#ibcon#about to write, iclass 10, count 0 2006.201.17:05:33.18#ibcon#wrote, iclass 10, count 0 2006.201.17:05:33.18#ibcon#about to read 3, iclass 10, count 0 2006.201.17:05:33.21#ibcon#read 3, iclass 10, count 0 2006.201.17:05:33.21#ibcon#about to read 4, iclass 10, count 0 2006.201.17:05:33.21#ibcon#read 4, iclass 10, count 0 2006.201.17:05:33.21#ibcon#about to read 5, iclass 10, count 0 2006.201.17:05:33.21#ibcon#read 5, iclass 10, count 0 2006.201.17:05:33.21#ibcon#about to read 6, iclass 10, count 0 2006.201.17:05:33.21#ibcon#read 6, iclass 10, count 0 2006.201.17:05:33.21#ibcon#end of sib2, iclass 10, count 0 2006.201.17:05:33.21#ibcon#*after write, iclass 10, count 0 2006.201.17:05:33.21#ibcon#*before return 0, iclass 10, count 0 2006.201.17:05:33.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:33.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:05:33.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.17:05:33.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.17:05:33.21$vck44/vblo=6,719.99 2006.201.17:05:33.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.17:05:33.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.17:05:33.21#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:33.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:33.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:33.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:33.21#ibcon#enter wrdev, iclass 12, count 0 2006.201.17:05:33.21#ibcon#first serial, iclass 12, count 0 2006.201.17:05:33.21#ibcon#enter sib2, iclass 12, count 0 2006.201.17:05:33.21#ibcon#flushed, iclass 12, count 0 2006.201.17:05:33.21#ibcon#about to write, iclass 12, count 0 2006.201.17:05:33.21#ibcon#wrote, iclass 12, count 0 2006.201.17:05:33.21#ibcon#about to read 3, iclass 12, count 0 2006.201.17:05:33.23#ibcon#read 3, iclass 12, count 0 2006.201.17:05:33.23#ibcon#about to read 4, iclass 12, count 0 2006.201.17:05:33.23#ibcon#read 4, iclass 12, count 0 2006.201.17:05:33.23#ibcon#about to read 5, iclass 12, count 0 2006.201.17:05:33.23#ibcon#read 5, iclass 12, count 0 2006.201.17:05:33.23#ibcon#about to read 6, iclass 12, count 0 2006.201.17:05:33.23#ibcon#read 6, iclass 12, count 0 2006.201.17:05:33.23#ibcon#end of sib2, iclass 12, count 0 2006.201.17:05:33.23#ibcon#*mode == 0, iclass 12, count 0 2006.201.17:05:33.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.17:05:33.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.17:05:33.23#ibcon#*before write, iclass 12, count 0 2006.201.17:05:33.23#ibcon#enter sib2, iclass 12, count 0 2006.201.17:05:33.23#ibcon#flushed, iclass 12, count 0 2006.201.17:05:33.23#ibcon#about to write, iclass 12, count 0 2006.201.17:05:33.23#ibcon#wrote, iclass 12, count 0 2006.201.17:05:33.23#ibcon#about to read 3, iclass 12, count 0 2006.201.17:05:33.27#ibcon#read 3, iclass 12, count 0 2006.201.17:05:33.27#ibcon#about to read 4, iclass 12, count 0 2006.201.17:05:33.27#ibcon#read 4, iclass 12, count 0 2006.201.17:05:33.27#ibcon#about to read 5, iclass 12, count 0 2006.201.17:05:33.27#ibcon#read 5, iclass 12, count 0 2006.201.17:05:33.27#ibcon#about to read 6, iclass 12, count 0 2006.201.17:05:33.27#ibcon#read 6, iclass 12, count 0 2006.201.17:05:33.27#ibcon#end of sib2, iclass 12, count 0 2006.201.17:05:33.27#ibcon#*after write, iclass 12, count 0 2006.201.17:05:33.27#ibcon#*before return 0, iclass 12, count 0 2006.201.17:05:33.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:33.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:05:33.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.17:05:33.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.17:05:33.27$vck44/vb=6,4 2006.201.17:05:33.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.17:05:33.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.17:05:33.27#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:33.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:33.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:33.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:33.33#ibcon#enter wrdev, iclass 14, count 2 2006.201.17:05:33.33#ibcon#first serial, iclass 14, count 2 2006.201.17:05:33.33#ibcon#enter sib2, iclass 14, count 2 2006.201.17:05:33.33#ibcon#flushed, iclass 14, count 2 2006.201.17:05:33.33#ibcon#about to write, iclass 14, count 2 2006.201.17:05:33.33#ibcon#wrote, iclass 14, count 2 2006.201.17:05:33.33#ibcon#about to read 3, iclass 14, count 2 2006.201.17:05:33.35#ibcon#read 3, iclass 14, count 2 2006.201.17:05:33.35#ibcon#about to read 4, iclass 14, count 2 2006.201.17:05:33.35#ibcon#read 4, iclass 14, count 2 2006.201.17:05:33.35#ibcon#about to read 5, iclass 14, count 2 2006.201.17:05:33.35#ibcon#read 5, iclass 14, count 2 2006.201.17:05:33.35#ibcon#about to read 6, iclass 14, count 2 2006.201.17:05:33.35#ibcon#read 6, iclass 14, count 2 2006.201.17:05:33.35#ibcon#end of sib2, iclass 14, count 2 2006.201.17:05:33.35#ibcon#*mode == 0, iclass 14, count 2 2006.201.17:05:33.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.17:05:33.35#ibcon#[27=AT06-04\r\n] 2006.201.17:05:33.35#ibcon#*before write, iclass 14, count 2 2006.201.17:05:33.35#ibcon#enter sib2, iclass 14, count 2 2006.201.17:05:33.35#ibcon#flushed, iclass 14, count 2 2006.201.17:05:33.35#ibcon#about to write, iclass 14, count 2 2006.201.17:05:33.35#ibcon#wrote, iclass 14, count 2 2006.201.17:05:33.35#ibcon#about to read 3, iclass 14, count 2 2006.201.17:05:33.38#ibcon#read 3, iclass 14, count 2 2006.201.17:05:33.38#ibcon#about to read 4, iclass 14, count 2 2006.201.17:05:33.38#ibcon#read 4, iclass 14, count 2 2006.201.17:05:33.38#ibcon#about to read 5, iclass 14, count 2 2006.201.17:05:33.38#ibcon#read 5, iclass 14, count 2 2006.201.17:05:33.38#ibcon#about to read 6, iclass 14, count 2 2006.201.17:05:33.38#ibcon#read 6, iclass 14, count 2 2006.201.17:05:33.38#ibcon#end of sib2, iclass 14, count 2 2006.201.17:05:33.38#ibcon#*after write, iclass 14, count 2 2006.201.17:05:33.38#ibcon#*before return 0, iclass 14, count 2 2006.201.17:05:33.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:33.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:05:33.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.17:05:33.38#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:33.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:33.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:33.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:33.50#ibcon#enter wrdev, iclass 14, count 0 2006.201.17:05:33.50#ibcon#first serial, iclass 14, count 0 2006.201.17:05:33.50#ibcon#enter sib2, iclass 14, count 0 2006.201.17:05:33.50#ibcon#flushed, iclass 14, count 0 2006.201.17:05:33.50#ibcon#about to write, iclass 14, count 0 2006.201.17:05:33.50#ibcon#wrote, iclass 14, count 0 2006.201.17:05:33.50#ibcon#about to read 3, iclass 14, count 0 2006.201.17:05:33.52#ibcon#read 3, iclass 14, count 0 2006.201.17:05:33.52#ibcon#about to read 4, iclass 14, count 0 2006.201.17:05:33.52#ibcon#read 4, iclass 14, count 0 2006.201.17:05:33.52#ibcon#about to read 5, iclass 14, count 0 2006.201.17:05:33.52#ibcon#read 5, iclass 14, count 0 2006.201.17:05:33.52#ibcon#about to read 6, iclass 14, count 0 2006.201.17:05:33.52#ibcon#read 6, iclass 14, count 0 2006.201.17:05:33.52#ibcon#end of sib2, iclass 14, count 0 2006.201.17:05:33.52#ibcon#*mode == 0, iclass 14, count 0 2006.201.17:05:33.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.17:05:33.52#ibcon#[27=USB\r\n] 2006.201.17:05:33.52#ibcon#*before write, iclass 14, count 0 2006.201.17:05:33.52#ibcon#enter sib2, iclass 14, count 0 2006.201.17:05:33.52#ibcon#flushed, iclass 14, count 0 2006.201.17:05:33.52#ibcon#about to write, iclass 14, count 0 2006.201.17:05:33.52#ibcon#wrote, iclass 14, count 0 2006.201.17:05:33.52#ibcon#about to read 3, iclass 14, count 0 2006.201.17:05:33.55#ibcon#read 3, iclass 14, count 0 2006.201.17:05:33.55#ibcon#about to read 4, iclass 14, count 0 2006.201.17:05:33.55#ibcon#read 4, iclass 14, count 0 2006.201.17:05:33.55#ibcon#about to read 5, iclass 14, count 0 2006.201.17:05:33.55#ibcon#read 5, iclass 14, count 0 2006.201.17:05:33.55#ibcon#about to read 6, iclass 14, count 0 2006.201.17:05:33.55#ibcon#read 6, iclass 14, count 0 2006.201.17:05:33.55#ibcon#end of sib2, iclass 14, count 0 2006.201.17:05:33.55#ibcon#*after write, iclass 14, count 0 2006.201.17:05:33.55#ibcon#*before return 0, iclass 14, count 0 2006.201.17:05:33.55#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:33.55#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:05:33.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.17:05:33.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.17:05:33.55$vck44/vblo=7,734.99 2006.201.17:05:33.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.17:05:33.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.17:05:33.55#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:33.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:33.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:33.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:33.55#ibcon#enter wrdev, iclass 16, count 0 2006.201.17:05:33.55#ibcon#first serial, iclass 16, count 0 2006.201.17:05:33.55#ibcon#enter sib2, iclass 16, count 0 2006.201.17:05:33.55#ibcon#flushed, iclass 16, count 0 2006.201.17:05:33.55#ibcon#about to write, iclass 16, count 0 2006.201.17:05:33.55#ibcon#wrote, iclass 16, count 0 2006.201.17:05:33.55#ibcon#about to read 3, iclass 16, count 0 2006.201.17:05:33.57#ibcon#read 3, iclass 16, count 0 2006.201.17:05:33.57#ibcon#about to read 4, iclass 16, count 0 2006.201.17:05:33.57#ibcon#read 4, iclass 16, count 0 2006.201.17:05:33.57#ibcon#about to read 5, iclass 16, count 0 2006.201.17:05:33.57#ibcon#read 5, iclass 16, count 0 2006.201.17:05:33.57#ibcon#about to read 6, iclass 16, count 0 2006.201.17:05:33.57#ibcon#read 6, iclass 16, count 0 2006.201.17:05:33.57#ibcon#end of sib2, iclass 16, count 0 2006.201.17:05:33.57#ibcon#*mode == 0, iclass 16, count 0 2006.201.17:05:33.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.17:05:33.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.17:05:33.57#ibcon#*before write, iclass 16, count 0 2006.201.17:05:33.57#ibcon#enter sib2, iclass 16, count 0 2006.201.17:05:33.57#ibcon#flushed, iclass 16, count 0 2006.201.17:05:33.57#ibcon#about to write, iclass 16, count 0 2006.201.17:05:33.57#ibcon#wrote, iclass 16, count 0 2006.201.17:05:33.57#ibcon#about to read 3, iclass 16, count 0 2006.201.17:05:33.61#ibcon#read 3, iclass 16, count 0 2006.201.17:05:33.61#ibcon#about to read 4, iclass 16, count 0 2006.201.17:05:33.61#ibcon#read 4, iclass 16, count 0 2006.201.17:05:33.61#ibcon#about to read 5, iclass 16, count 0 2006.201.17:05:33.61#ibcon#read 5, iclass 16, count 0 2006.201.17:05:33.61#ibcon#about to read 6, iclass 16, count 0 2006.201.17:05:33.61#ibcon#read 6, iclass 16, count 0 2006.201.17:05:33.61#ibcon#end of sib2, iclass 16, count 0 2006.201.17:05:33.61#ibcon#*after write, iclass 16, count 0 2006.201.17:05:33.61#ibcon#*before return 0, iclass 16, count 0 2006.201.17:05:33.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:33.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:05:33.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.17:05:33.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.17:05:33.61$vck44/vb=7,4 2006.201.17:05:33.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.17:05:33.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.17:05:33.61#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:33.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:33.67#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:33.67#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:33.67#ibcon#enter wrdev, iclass 18, count 2 2006.201.17:05:33.67#ibcon#first serial, iclass 18, count 2 2006.201.17:05:33.67#ibcon#enter sib2, iclass 18, count 2 2006.201.17:05:33.67#ibcon#flushed, iclass 18, count 2 2006.201.17:05:33.67#ibcon#about to write, iclass 18, count 2 2006.201.17:05:33.67#ibcon#wrote, iclass 18, count 2 2006.201.17:05:33.67#ibcon#about to read 3, iclass 18, count 2 2006.201.17:05:33.69#ibcon#read 3, iclass 18, count 2 2006.201.17:05:33.69#ibcon#about to read 4, iclass 18, count 2 2006.201.17:05:33.69#ibcon#read 4, iclass 18, count 2 2006.201.17:05:33.69#ibcon#about to read 5, iclass 18, count 2 2006.201.17:05:33.69#ibcon#read 5, iclass 18, count 2 2006.201.17:05:33.69#ibcon#about to read 6, iclass 18, count 2 2006.201.17:05:33.69#ibcon#read 6, iclass 18, count 2 2006.201.17:05:33.69#ibcon#end of sib2, iclass 18, count 2 2006.201.17:05:33.69#ibcon#*mode == 0, iclass 18, count 2 2006.201.17:05:33.69#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.17:05:33.69#ibcon#[27=AT07-04\r\n] 2006.201.17:05:33.69#ibcon#*before write, iclass 18, count 2 2006.201.17:05:33.69#ibcon#enter sib2, iclass 18, count 2 2006.201.17:05:33.69#ibcon#flushed, iclass 18, count 2 2006.201.17:05:33.69#ibcon#about to write, iclass 18, count 2 2006.201.17:05:33.69#ibcon#wrote, iclass 18, count 2 2006.201.17:05:33.69#ibcon#about to read 3, iclass 18, count 2 2006.201.17:05:33.72#ibcon#read 3, iclass 18, count 2 2006.201.17:05:33.72#ibcon#about to read 4, iclass 18, count 2 2006.201.17:05:33.72#ibcon#read 4, iclass 18, count 2 2006.201.17:05:33.72#ibcon#about to read 5, iclass 18, count 2 2006.201.17:05:33.72#ibcon#read 5, iclass 18, count 2 2006.201.17:05:33.72#ibcon#about to read 6, iclass 18, count 2 2006.201.17:05:33.72#ibcon#read 6, iclass 18, count 2 2006.201.17:05:33.72#ibcon#end of sib2, iclass 18, count 2 2006.201.17:05:33.72#ibcon#*after write, iclass 18, count 2 2006.201.17:05:33.72#ibcon#*before return 0, iclass 18, count 2 2006.201.17:05:33.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:33.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:05:33.72#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.17:05:33.72#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:33.72#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:33.84#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:33.84#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:33.84#ibcon#enter wrdev, iclass 18, count 0 2006.201.17:05:33.84#ibcon#first serial, iclass 18, count 0 2006.201.17:05:33.84#ibcon#enter sib2, iclass 18, count 0 2006.201.17:05:33.84#ibcon#flushed, iclass 18, count 0 2006.201.17:05:33.84#ibcon#about to write, iclass 18, count 0 2006.201.17:05:33.84#ibcon#wrote, iclass 18, count 0 2006.201.17:05:33.84#ibcon#about to read 3, iclass 18, count 0 2006.201.17:05:33.86#ibcon#read 3, iclass 18, count 0 2006.201.17:05:33.86#ibcon#about to read 4, iclass 18, count 0 2006.201.17:05:33.86#ibcon#read 4, iclass 18, count 0 2006.201.17:05:33.86#ibcon#about to read 5, iclass 18, count 0 2006.201.17:05:33.86#ibcon#read 5, iclass 18, count 0 2006.201.17:05:33.86#ibcon#about to read 6, iclass 18, count 0 2006.201.17:05:33.86#ibcon#read 6, iclass 18, count 0 2006.201.17:05:33.86#ibcon#end of sib2, iclass 18, count 0 2006.201.17:05:33.86#ibcon#*mode == 0, iclass 18, count 0 2006.201.17:05:33.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.17:05:33.86#ibcon#[27=USB\r\n] 2006.201.17:05:33.86#ibcon#*before write, iclass 18, count 0 2006.201.17:05:33.86#ibcon#enter sib2, iclass 18, count 0 2006.201.17:05:33.86#ibcon#flushed, iclass 18, count 0 2006.201.17:05:33.86#ibcon#about to write, iclass 18, count 0 2006.201.17:05:33.86#ibcon#wrote, iclass 18, count 0 2006.201.17:05:33.86#ibcon#about to read 3, iclass 18, count 0 2006.201.17:05:33.89#ibcon#read 3, iclass 18, count 0 2006.201.17:05:33.89#ibcon#about to read 4, iclass 18, count 0 2006.201.17:05:33.89#ibcon#read 4, iclass 18, count 0 2006.201.17:05:33.89#ibcon#about to read 5, iclass 18, count 0 2006.201.17:05:33.89#ibcon#read 5, iclass 18, count 0 2006.201.17:05:33.89#ibcon#about to read 6, iclass 18, count 0 2006.201.17:05:33.89#ibcon#read 6, iclass 18, count 0 2006.201.17:05:33.89#ibcon#end of sib2, iclass 18, count 0 2006.201.17:05:33.89#ibcon#*after write, iclass 18, count 0 2006.201.17:05:33.89#ibcon#*before return 0, iclass 18, count 0 2006.201.17:05:33.89#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:33.89#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:05:33.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.17:05:33.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.17:05:33.89$vck44/vblo=8,744.99 2006.201.17:05:33.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.17:05:33.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.17:05:33.89#ibcon#ireg 17 cls_cnt 0 2006.201.17:05:33.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:33.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:33.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:33.89#ibcon#enter wrdev, iclass 20, count 0 2006.201.17:05:33.89#ibcon#first serial, iclass 20, count 0 2006.201.17:05:33.89#ibcon#enter sib2, iclass 20, count 0 2006.201.17:05:33.89#ibcon#flushed, iclass 20, count 0 2006.201.17:05:33.89#ibcon#about to write, iclass 20, count 0 2006.201.17:05:33.89#ibcon#wrote, iclass 20, count 0 2006.201.17:05:33.89#ibcon#about to read 3, iclass 20, count 0 2006.201.17:05:33.91#ibcon#read 3, iclass 20, count 0 2006.201.17:05:33.91#ibcon#about to read 4, iclass 20, count 0 2006.201.17:05:33.91#ibcon#read 4, iclass 20, count 0 2006.201.17:05:33.91#ibcon#about to read 5, iclass 20, count 0 2006.201.17:05:33.91#ibcon#read 5, iclass 20, count 0 2006.201.17:05:33.91#ibcon#about to read 6, iclass 20, count 0 2006.201.17:05:33.91#ibcon#read 6, iclass 20, count 0 2006.201.17:05:33.91#ibcon#end of sib2, iclass 20, count 0 2006.201.17:05:33.91#ibcon#*mode == 0, iclass 20, count 0 2006.201.17:05:33.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.17:05:33.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.17:05:33.91#ibcon#*before write, iclass 20, count 0 2006.201.17:05:33.91#ibcon#enter sib2, iclass 20, count 0 2006.201.17:05:33.91#ibcon#flushed, iclass 20, count 0 2006.201.17:05:33.91#ibcon#about to write, iclass 20, count 0 2006.201.17:05:33.91#ibcon#wrote, iclass 20, count 0 2006.201.17:05:33.91#ibcon#about to read 3, iclass 20, count 0 2006.201.17:05:33.95#ibcon#read 3, iclass 20, count 0 2006.201.17:05:33.95#ibcon#about to read 4, iclass 20, count 0 2006.201.17:05:33.95#ibcon#read 4, iclass 20, count 0 2006.201.17:05:33.95#ibcon#about to read 5, iclass 20, count 0 2006.201.17:05:33.95#ibcon#read 5, iclass 20, count 0 2006.201.17:05:33.95#ibcon#about to read 6, iclass 20, count 0 2006.201.17:05:33.95#ibcon#read 6, iclass 20, count 0 2006.201.17:05:33.95#ibcon#end of sib2, iclass 20, count 0 2006.201.17:05:33.95#ibcon#*after write, iclass 20, count 0 2006.201.17:05:33.95#ibcon#*before return 0, iclass 20, count 0 2006.201.17:05:33.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:33.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:05:33.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.17:05:33.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.17:05:33.95$vck44/vb=8,4 2006.201.17:05:33.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.17:05:33.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.17:05:33.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:05:33.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:34.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:34.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:34.01#ibcon#enter wrdev, iclass 22, count 2 2006.201.17:05:34.01#ibcon#first serial, iclass 22, count 2 2006.201.17:05:34.01#ibcon#enter sib2, iclass 22, count 2 2006.201.17:05:34.01#ibcon#flushed, iclass 22, count 2 2006.201.17:05:34.01#ibcon#about to write, iclass 22, count 2 2006.201.17:05:34.01#ibcon#wrote, iclass 22, count 2 2006.201.17:05:34.01#ibcon#about to read 3, iclass 22, count 2 2006.201.17:05:34.03#ibcon#read 3, iclass 22, count 2 2006.201.17:05:34.03#ibcon#about to read 4, iclass 22, count 2 2006.201.17:05:34.03#ibcon#read 4, iclass 22, count 2 2006.201.17:05:34.03#ibcon#about to read 5, iclass 22, count 2 2006.201.17:05:34.03#ibcon#read 5, iclass 22, count 2 2006.201.17:05:34.03#ibcon#about to read 6, iclass 22, count 2 2006.201.17:05:34.03#ibcon#read 6, iclass 22, count 2 2006.201.17:05:34.03#ibcon#end of sib2, iclass 22, count 2 2006.201.17:05:34.03#ibcon#*mode == 0, iclass 22, count 2 2006.201.17:05:34.03#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.17:05:34.03#ibcon#[27=AT08-04\r\n] 2006.201.17:05:34.03#ibcon#*before write, iclass 22, count 2 2006.201.17:05:34.03#ibcon#enter sib2, iclass 22, count 2 2006.201.17:05:34.03#ibcon#flushed, iclass 22, count 2 2006.201.17:05:34.03#ibcon#about to write, iclass 22, count 2 2006.201.17:05:34.03#ibcon#wrote, iclass 22, count 2 2006.201.17:05:34.03#ibcon#about to read 3, iclass 22, count 2 2006.201.17:05:34.06#ibcon#read 3, iclass 22, count 2 2006.201.17:05:34.06#ibcon#about to read 4, iclass 22, count 2 2006.201.17:05:34.06#ibcon#read 4, iclass 22, count 2 2006.201.17:05:34.06#ibcon#about to read 5, iclass 22, count 2 2006.201.17:05:34.06#ibcon#read 5, iclass 22, count 2 2006.201.17:05:34.06#ibcon#about to read 6, iclass 22, count 2 2006.201.17:05:34.06#ibcon#read 6, iclass 22, count 2 2006.201.17:05:34.06#ibcon#end of sib2, iclass 22, count 2 2006.201.17:05:34.06#ibcon#*after write, iclass 22, count 2 2006.201.17:05:34.06#ibcon#*before return 0, iclass 22, count 2 2006.201.17:05:34.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:34.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:05:34.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.17:05:34.06#ibcon#ireg 7 cls_cnt 0 2006.201.17:05:34.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:34.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:34.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:34.18#ibcon#enter wrdev, iclass 22, count 0 2006.201.17:05:34.18#ibcon#first serial, iclass 22, count 0 2006.201.17:05:34.18#ibcon#enter sib2, iclass 22, count 0 2006.201.17:05:34.18#ibcon#flushed, iclass 22, count 0 2006.201.17:05:34.18#ibcon#about to write, iclass 22, count 0 2006.201.17:05:34.18#ibcon#wrote, iclass 22, count 0 2006.201.17:05:34.18#ibcon#about to read 3, iclass 22, count 0 2006.201.17:05:34.20#ibcon#read 3, iclass 22, count 0 2006.201.17:05:34.20#ibcon#about to read 4, iclass 22, count 0 2006.201.17:05:34.20#ibcon#read 4, iclass 22, count 0 2006.201.17:05:34.20#ibcon#about to read 5, iclass 22, count 0 2006.201.17:05:34.20#ibcon#read 5, iclass 22, count 0 2006.201.17:05:34.20#ibcon#about to read 6, iclass 22, count 0 2006.201.17:05:34.20#ibcon#read 6, iclass 22, count 0 2006.201.17:05:34.20#ibcon#end of sib2, iclass 22, count 0 2006.201.17:05:34.20#ibcon#*mode == 0, iclass 22, count 0 2006.201.17:05:34.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.17:05:34.20#ibcon#[27=USB\r\n] 2006.201.17:05:34.20#ibcon#*before write, iclass 22, count 0 2006.201.17:05:34.20#ibcon#enter sib2, iclass 22, count 0 2006.201.17:05:34.20#ibcon#flushed, iclass 22, count 0 2006.201.17:05:34.20#ibcon#about to write, iclass 22, count 0 2006.201.17:05:34.20#ibcon#wrote, iclass 22, count 0 2006.201.17:05:34.20#ibcon#about to read 3, iclass 22, count 0 2006.201.17:05:34.23#ibcon#read 3, iclass 22, count 0 2006.201.17:05:34.23#ibcon#about to read 4, iclass 22, count 0 2006.201.17:05:34.23#ibcon#read 4, iclass 22, count 0 2006.201.17:05:34.23#ibcon#about to read 5, iclass 22, count 0 2006.201.17:05:34.23#ibcon#read 5, iclass 22, count 0 2006.201.17:05:34.23#ibcon#about to read 6, iclass 22, count 0 2006.201.17:05:34.23#ibcon#read 6, iclass 22, count 0 2006.201.17:05:34.23#ibcon#end of sib2, iclass 22, count 0 2006.201.17:05:34.23#ibcon#*after write, iclass 22, count 0 2006.201.17:05:34.23#ibcon#*before return 0, iclass 22, count 0 2006.201.17:05:34.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:34.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:05:34.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.17:05:34.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.17:05:34.23$vck44/vabw=wide 2006.201.17:05:34.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.17:05:34.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.17:05:34.23#ibcon#ireg 8 cls_cnt 0 2006.201.17:05:34.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:34.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:34.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:34.23#ibcon#enter wrdev, iclass 24, count 0 2006.201.17:05:34.23#ibcon#first serial, iclass 24, count 0 2006.201.17:05:34.23#ibcon#enter sib2, iclass 24, count 0 2006.201.17:05:34.23#ibcon#flushed, iclass 24, count 0 2006.201.17:05:34.23#ibcon#about to write, iclass 24, count 0 2006.201.17:05:34.23#ibcon#wrote, iclass 24, count 0 2006.201.17:05:34.23#ibcon#about to read 3, iclass 24, count 0 2006.201.17:05:34.25#ibcon#read 3, iclass 24, count 0 2006.201.17:05:34.25#ibcon#about to read 4, iclass 24, count 0 2006.201.17:05:34.25#ibcon#read 4, iclass 24, count 0 2006.201.17:05:34.25#ibcon#about to read 5, iclass 24, count 0 2006.201.17:05:34.25#ibcon#read 5, iclass 24, count 0 2006.201.17:05:34.25#ibcon#about to read 6, iclass 24, count 0 2006.201.17:05:34.25#ibcon#read 6, iclass 24, count 0 2006.201.17:05:34.25#ibcon#end of sib2, iclass 24, count 0 2006.201.17:05:34.25#ibcon#*mode == 0, iclass 24, count 0 2006.201.17:05:34.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.17:05:34.25#ibcon#[25=BW32\r\n] 2006.201.17:05:34.25#ibcon#*before write, iclass 24, count 0 2006.201.17:05:34.25#ibcon#enter sib2, iclass 24, count 0 2006.201.17:05:34.25#ibcon#flushed, iclass 24, count 0 2006.201.17:05:34.25#ibcon#about to write, iclass 24, count 0 2006.201.17:05:34.25#ibcon#wrote, iclass 24, count 0 2006.201.17:05:34.25#ibcon#about to read 3, iclass 24, count 0 2006.201.17:05:34.29#ibcon#read 3, iclass 24, count 0 2006.201.17:05:34.29#ibcon#about to read 4, iclass 24, count 0 2006.201.17:05:34.29#ibcon#read 4, iclass 24, count 0 2006.201.17:05:34.29#ibcon#about to read 5, iclass 24, count 0 2006.201.17:05:34.29#ibcon#read 5, iclass 24, count 0 2006.201.17:05:34.29#ibcon#about to read 6, iclass 24, count 0 2006.201.17:05:34.29#ibcon#read 6, iclass 24, count 0 2006.201.17:05:34.29#ibcon#end of sib2, iclass 24, count 0 2006.201.17:05:34.29#ibcon#*after write, iclass 24, count 0 2006.201.17:05:34.29#ibcon#*before return 0, iclass 24, count 0 2006.201.17:05:34.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:34.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:05:34.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.17:05:34.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.17:05:34.29$vck44/vbbw=wide 2006.201.17:05:34.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.17:05:34.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.17:05:34.29#ibcon#ireg 8 cls_cnt 0 2006.201.17:05:34.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:05:34.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:05:34.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:05:34.35#ibcon#enter wrdev, iclass 26, count 0 2006.201.17:05:34.35#ibcon#first serial, iclass 26, count 0 2006.201.17:05:34.35#ibcon#enter sib2, iclass 26, count 0 2006.201.17:05:34.35#ibcon#flushed, iclass 26, count 0 2006.201.17:05:34.35#ibcon#about to write, iclass 26, count 0 2006.201.17:05:34.35#ibcon#wrote, iclass 26, count 0 2006.201.17:05:34.35#ibcon#about to read 3, iclass 26, count 0 2006.201.17:05:34.37#ibcon#read 3, iclass 26, count 0 2006.201.17:05:34.37#ibcon#about to read 4, iclass 26, count 0 2006.201.17:05:34.37#ibcon#read 4, iclass 26, count 0 2006.201.17:05:34.37#ibcon#about to read 5, iclass 26, count 0 2006.201.17:05:34.37#ibcon#read 5, iclass 26, count 0 2006.201.17:05:34.37#ibcon#about to read 6, iclass 26, count 0 2006.201.17:05:34.37#ibcon#read 6, iclass 26, count 0 2006.201.17:05:34.37#ibcon#end of sib2, iclass 26, count 0 2006.201.17:05:34.37#ibcon#*mode == 0, iclass 26, count 0 2006.201.17:05:34.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.17:05:34.37#ibcon#[27=BW32\r\n] 2006.201.17:05:34.37#ibcon#*before write, iclass 26, count 0 2006.201.17:05:34.37#ibcon#enter sib2, iclass 26, count 0 2006.201.17:05:34.37#ibcon#flushed, iclass 26, count 0 2006.201.17:05:34.37#ibcon#about to write, iclass 26, count 0 2006.201.17:05:34.37#ibcon#wrote, iclass 26, count 0 2006.201.17:05:34.37#ibcon#about to read 3, iclass 26, count 0 2006.201.17:05:34.41#ibcon#read 3, iclass 26, count 0 2006.201.17:05:34.41#ibcon#about to read 4, iclass 26, count 0 2006.201.17:05:34.41#ibcon#read 4, iclass 26, count 0 2006.201.17:05:34.41#ibcon#about to read 5, iclass 26, count 0 2006.201.17:05:34.41#ibcon#read 5, iclass 26, count 0 2006.201.17:05:34.41#ibcon#about to read 6, iclass 26, count 0 2006.201.17:05:34.41#ibcon#read 6, iclass 26, count 0 2006.201.17:05:34.41#ibcon#end of sib2, iclass 26, count 0 2006.201.17:05:34.41#ibcon#*after write, iclass 26, count 0 2006.201.17:05:34.41#ibcon#*before return 0, iclass 26, count 0 2006.201.17:05:34.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:05:34.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:05:34.41#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.17:05:34.41#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.17:05:34.41$setupk4/ifdk4 2006.201.17:05:34.41$ifdk4/lo= 2006.201.17:05:34.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.17:05:34.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.17:05:34.41$ifdk4/patch= 2006.201.17:05:34.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.17:05:34.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.17:05:34.41$setupk4/!*+20s 2006.201.17:05:42.23#abcon#<5=/00 0.2 0.6 20.771001002.6\r\n> 2006.201.17:05:42.25#abcon#{5=INTERFACE CLEAR} 2006.201.17:05:42.31#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:05:48.89$setupk4/"tpicd 2006.201.17:05:48.89$setupk4/echo=off 2006.201.17:05:48.89$setupk4/xlog=off 2006.201.17:05:48.89:!2006.201.17:10:48 2006.201.17:06:22.14#trakl#Source acquired 2006.201.17:06:22.14#flagr#flagr/antenna,acquired 2006.201.17:10:48.00:preob 2006.201.17:10:48.13/onsource/TRACKING 2006.201.17:10:48.13:!2006.201.17:10:58 2006.201.17:10:58.00:"tape 2006.201.17:10:58.00:"st=record 2006.201.17:10:58.00:data_valid=on 2006.201.17:10:58.00:midob 2006.201.17:10:58.13/onsource/TRACKING 2006.201.17:10:58.13/wx/20.77,1002.7,100 2006.201.17:10:58.28/cable/+6.4766E-03 2006.201.17:10:59.37/va/01,08,usb,yes,34,36 2006.201.17:10:59.37/va/02,07,usb,yes,36,37 2006.201.17:10:59.37/va/03,08,usb,yes,33,34 2006.201.17:10:59.37/va/04,07,usb,yes,38,39 2006.201.17:10:59.37/va/05,04,usb,yes,33,34 2006.201.17:10:59.37/va/06,05,usb,yes,33,33 2006.201.17:10:59.37/va/07,05,usb,yes,33,34 2006.201.17:10:59.37/va/08,04,usb,yes,32,39 2006.201.17:10:59.60/valo/01,524.99,yes,locked 2006.201.17:10:59.60/valo/02,534.99,yes,locked 2006.201.17:10:59.60/valo/03,564.99,yes,locked 2006.201.17:10:59.60/valo/04,624.99,yes,locked 2006.201.17:10:59.60/valo/05,734.99,yes,locked 2006.201.17:10:59.60/valo/06,814.99,yes,locked 2006.201.17:10:59.60/valo/07,864.99,yes,locked 2006.201.17:10:59.60/valo/08,884.99,yes,locked 2006.201.17:11:00.69/vb/01,04,usb,yes,28,26 2006.201.17:11:00.69/vb/02,05,usb,yes,27,27 2006.201.17:11:00.69/vb/03,04,usb,yes,28,31 2006.201.17:11:00.69/vb/04,05,usb,yes,28,27 2006.201.17:11:00.69/vb/05,04,usb,yes,25,27 2006.201.17:11:00.69/vb/06,04,usb,yes,29,25 2006.201.17:11:00.69/vb/07,04,usb,yes,29,29 2006.201.17:11:00.69/vb/08,04,usb,yes,27,30 2006.201.17:11:00.92/vblo/01,629.99,yes,locked 2006.201.17:11:00.92/vblo/02,634.99,yes,locked 2006.201.17:11:00.92/vblo/03,649.99,yes,locked 2006.201.17:11:00.92/vblo/04,679.99,yes,locked 2006.201.17:11:00.92/vblo/05,709.99,yes,locked 2006.201.17:11:00.92/vblo/06,719.99,yes,locked 2006.201.17:11:00.92/vblo/07,734.99,yes,locked 2006.201.17:11:00.92/vblo/08,744.99,yes,locked 2006.201.17:11:01.07/vabw/8 2006.201.17:11:01.22/vbbw/8 2006.201.17:11:01.39/xfe/off,on,15.2 2006.201.17:11:01.76/ifatt/23,28,28,28 2006.201.17:11:02.06/fmout-gps/S +4.51E-07 2006.201.17:11:02.13:!2006.201.17:20:28 2006.201.17:20:28.00:data_valid=off 2006.201.17:20:28.00:"et 2006.201.17:20:28.00:!+3s 2006.201.17:20:31.02:"tape 2006.201.17:20:31.02:postob 2006.201.17:20:31.12/cable/+6.4769E-03 2006.201.17:20:31.12/wx/20.73,1002.6,100 2006.201.17:20:31.20/fmout-gps/S +4.50E-07 2006.201.17:20:31.20:scan_name=201-1724,jd0607,280 2006.201.17:20:31.20:source=1803+784,180045.68,782804.0,2000.0,ccw 2006.201.17:20:32.13#flagr#flagr/antenna,new-source 2006.201.17:20:32.13:checkk5 2006.201.17:20:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.17:20:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.17:20:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.17:20:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.17:20:34.32/chk_obsdata//k5ts1/T2011710??a.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.201.17:20:35.01/chk_obsdata//k5ts2/T2011710??b.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.201.17:20:35.68/chk_obsdata//k5ts3/T2011710??c.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.201.17:20:36.35/chk_obsdata//k5ts4/T2011710??d.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.201.17:20:37.03/k5log//k5ts1_log_newline 2006.201.17:20:37.72/k5log//k5ts2_log_newline 2006.201.17:20:38.41/k5log//k5ts3_log_newline 2006.201.17:20:39.09/k5log//k5ts4_log_newline 2006.201.17:20:39.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.17:20:39.12:setupk4=1 2006.201.17:20:39.12$setupk4/echo=on 2006.201.17:20:39.12$setupk4/pcalon 2006.201.17:20:39.12$pcalon/"no phase cal control is implemented here 2006.201.17:20:39.12$setupk4/"tpicd=stop 2006.201.17:20:39.12$setupk4/"rec=synch_on 2006.201.17:20:39.12$setupk4/"rec_mode=128 2006.201.17:20:39.12$setupk4/!* 2006.201.17:20:39.12$setupk4/recpk4 2006.201.17:20:39.12$recpk4/recpatch= 2006.201.17:20:39.12$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.17:20:39.12$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.17:20:39.12$setupk4/vck44 2006.201.17:20:39.12$vck44/valo=1,524.99 2006.201.17:20:39.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.17:20:39.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.17:20:39.12#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:39.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:39.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:39.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:39.12#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:20:39.12#ibcon#first serial, iclass 27, count 0 2006.201.17:20:39.12#ibcon#enter sib2, iclass 27, count 0 2006.201.17:20:39.12#ibcon#flushed, iclass 27, count 0 2006.201.17:20:39.12#ibcon#about to write, iclass 27, count 0 2006.201.17:20:39.12#ibcon#wrote, iclass 27, count 0 2006.201.17:20:39.12#ibcon#about to read 3, iclass 27, count 0 2006.201.17:20:39.16#ibcon#read 3, iclass 27, count 0 2006.201.17:20:39.16#ibcon#about to read 4, iclass 27, count 0 2006.201.17:20:39.16#ibcon#read 4, iclass 27, count 0 2006.201.17:20:39.16#ibcon#about to read 5, iclass 27, count 0 2006.201.17:20:39.16#ibcon#read 5, iclass 27, count 0 2006.201.17:20:39.16#ibcon#about to read 6, iclass 27, count 0 2006.201.17:20:39.16#ibcon#read 6, iclass 27, count 0 2006.201.17:20:39.16#ibcon#end of sib2, iclass 27, count 0 2006.201.17:20:39.16#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:20:39.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:20:39.16#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.17:20:39.16#ibcon#*before write, iclass 27, count 0 2006.201.17:20:39.16#ibcon#enter sib2, iclass 27, count 0 2006.201.17:20:39.16#ibcon#flushed, iclass 27, count 0 2006.201.17:20:39.16#ibcon#about to write, iclass 27, count 0 2006.201.17:20:39.16#ibcon#wrote, iclass 27, count 0 2006.201.17:20:39.16#ibcon#about to read 3, iclass 27, count 0 2006.201.17:20:39.21#ibcon#read 3, iclass 27, count 0 2006.201.17:20:39.21#ibcon#about to read 4, iclass 27, count 0 2006.201.17:20:39.21#ibcon#read 4, iclass 27, count 0 2006.201.17:20:39.21#ibcon#about to read 5, iclass 27, count 0 2006.201.17:20:39.21#ibcon#read 5, iclass 27, count 0 2006.201.17:20:39.21#ibcon#about to read 6, iclass 27, count 0 2006.201.17:20:39.21#ibcon#read 6, iclass 27, count 0 2006.201.17:20:39.21#ibcon#end of sib2, iclass 27, count 0 2006.201.17:20:39.21#ibcon#*after write, iclass 27, count 0 2006.201.17:20:39.21#ibcon#*before return 0, iclass 27, count 0 2006.201.17:20:39.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:39.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:39.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:20:39.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:20:39.21$vck44/va=1,8 2006.201.17:20:39.21#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.17:20:39.21#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.17:20:39.21#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:39.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:39.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:39.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:39.21#ibcon#enter wrdev, iclass 29, count 2 2006.201.17:20:39.21#ibcon#first serial, iclass 29, count 2 2006.201.17:20:39.21#ibcon#enter sib2, iclass 29, count 2 2006.201.17:20:39.21#ibcon#flushed, iclass 29, count 2 2006.201.17:20:39.21#ibcon#about to write, iclass 29, count 2 2006.201.17:20:39.21#ibcon#wrote, iclass 29, count 2 2006.201.17:20:39.21#ibcon#about to read 3, iclass 29, count 2 2006.201.17:20:39.23#ibcon#read 3, iclass 29, count 2 2006.201.17:20:39.23#ibcon#about to read 4, iclass 29, count 2 2006.201.17:20:39.23#ibcon#read 4, iclass 29, count 2 2006.201.17:20:39.23#ibcon#about to read 5, iclass 29, count 2 2006.201.17:20:39.23#ibcon#read 5, iclass 29, count 2 2006.201.17:20:39.23#ibcon#about to read 6, iclass 29, count 2 2006.201.17:20:39.23#ibcon#read 6, iclass 29, count 2 2006.201.17:20:39.23#ibcon#end of sib2, iclass 29, count 2 2006.201.17:20:39.23#ibcon#*mode == 0, iclass 29, count 2 2006.201.17:20:39.23#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.17:20:39.23#ibcon#[25=AT01-08\r\n] 2006.201.17:20:39.23#ibcon#*before write, iclass 29, count 2 2006.201.17:20:39.23#ibcon#enter sib2, iclass 29, count 2 2006.201.17:20:39.23#ibcon#flushed, iclass 29, count 2 2006.201.17:20:39.23#ibcon#about to write, iclass 29, count 2 2006.201.17:20:39.23#ibcon#wrote, iclass 29, count 2 2006.201.17:20:39.23#ibcon#about to read 3, iclass 29, count 2 2006.201.17:20:39.26#ibcon#read 3, iclass 29, count 2 2006.201.17:20:39.26#ibcon#about to read 4, iclass 29, count 2 2006.201.17:20:39.26#ibcon#read 4, iclass 29, count 2 2006.201.17:20:39.26#ibcon#about to read 5, iclass 29, count 2 2006.201.17:20:39.26#ibcon#read 5, iclass 29, count 2 2006.201.17:20:39.26#ibcon#about to read 6, iclass 29, count 2 2006.201.17:20:39.26#ibcon#read 6, iclass 29, count 2 2006.201.17:20:39.26#ibcon#end of sib2, iclass 29, count 2 2006.201.17:20:39.26#ibcon#*after write, iclass 29, count 2 2006.201.17:20:39.26#ibcon#*before return 0, iclass 29, count 2 2006.201.17:20:39.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:39.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:39.26#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.17:20:39.26#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:39.26#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:39.38#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:39.38#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:39.38#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:20:39.38#ibcon#first serial, iclass 29, count 0 2006.201.17:20:39.38#ibcon#enter sib2, iclass 29, count 0 2006.201.17:20:39.38#ibcon#flushed, iclass 29, count 0 2006.201.17:20:39.38#ibcon#about to write, iclass 29, count 0 2006.201.17:20:39.38#ibcon#wrote, iclass 29, count 0 2006.201.17:20:39.38#ibcon#about to read 3, iclass 29, count 0 2006.201.17:20:39.40#ibcon#read 3, iclass 29, count 0 2006.201.17:20:39.40#ibcon#about to read 4, iclass 29, count 0 2006.201.17:20:39.40#ibcon#read 4, iclass 29, count 0 2006.201.17:20:39.40#ibcon#about to read 5, iclass 29, count 0 2006.201.17:20:39.40#ibcon#read 5, iclass 29, count 0 2006.201.17:20:39.40#ibcon#about to read 6, iclass 29, count 0 2006.201.17:20:39.40#ibcon#read 6, iclass 29, count 0 2006.201.17:20:39.40#ibcon#end of sib2, iclass 29, count 0 2006.201.17:20:39.40#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:20:39.40#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:20:39.40#ibcon#[25=USB\r\n] 2006.201.17:20:39.40#ibcon#*before write, iclass 29, count 0 2006.201.17:20:39.40#ibcon#enter sib2, iclass 29, count 0 2006.201.17:20:39.40#ibcon#flushed, iclass 29, count 0 2006.201.17:20:39.40#ibcon#about to write, iclass 29, count 0 2006.201.17:20:39.40#ibcon#wrote, iclass 29, count 0 2006.201.17:20:39.40#ibcon#about to read 3, iclass 29, count 0 2006.201.17:20:39.43#ibcon#read 3, iclass 29, count 0 2006.201.17:20:39.43#ibcon#about to read 4, iclass 29, count 0 2006.201.17:20:39.43#ibcon#read 4, iclass 29, count 0 2006.201.17:20:39.43#ibcon#about to read 5, iclass 29, count 0 2006.201.17:20:39.43#ibcon#read 5, iclass 29, count 0 2006.201.17:20:39.43#ibcon#about to read 6, iclass 29, count 0 2006.201.17:20:39.43#ibcon#read 6, iclass 29, count 0 2006.201.17:20:39.43#ibcon#end of sib2, iclass 29, count 0 2006.201.17:20:39.43#ibcon#*after write, iclass 29, count 0 2006.201.17:20:39.43#ibcon#*before return 0, iclass 29, count 0 2006.201.17:20:39.43#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:39.43#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:39.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:20:39.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:20:39.43$vck44/valo=2,534.99 2006.201.17:20:39.43#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.17:20:39.43#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.17:20:39.43#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:39.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:39.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:39.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:39.43#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:20:39.43#ibcon#first serial, iclass 31, count 0 2006.201.17:20:39.43#ibcon#enter sib2, iclass 31, count 0 2006.201.17:20:39.43#ibcon#flushed, iclass 31, count 0 2006.201.17:20:39.43#ibcon#about to write, iclass 31, count 0 2006.201.17:20:39.43#ibcon#wrote, iclass 31, count 0 2006.201.17:20:39.43#ibcon#about to read 3, iclass 31, count 0 2006.201.17:20:39.45#ibcon#read 3, iclass 31, count 0 2006.201.17:20:39.45#ibcon#about to read 4, iclass 31, count 0 2006.201.17:20:39.45#ibcon#read 4, iclass 31, count 0 2006.201.17:20:39.45#ibcon#about to read 5, iclass 31, count 0 2006.201.17:20:39.45#ibcon#read 5, iclass 31, count 0 2006.201.17:20:39.45#ibcon#about to read 6, iclass 31, count 0 2006.201.17:20:39.45#ibcon#read 6, iclass 31, count 0 2006.201.17:20:39.45#ibcon#end of sib2, iclass 31, count 0 2006.201.17:20:39.45#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:20:39.45#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:20:39.45#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.17:20:39.45#ibcon#*before write, iclass 31, count 0 2006.201.17:20:39.45#ibcon#enter sib2, iclass 31, count 0 2006.201.17:20:39.45#ibcon#flushed, iclass 31, count 0 2006.201.17:20:39.45#ibcon#about to write, iclass 31, count 0 2006.201.17:20:39.45#ibcon#wrote, iclass 31, count 0 2006.201.17:20:39.45#ibcon#about to read 3, iclass 31, count 0 2006.201.17:20:39.50#ibcon#read 3, iclass 31, count 0 2006.201.17:20:39.50#ibcon#about to read 4, iclass 31, count 0 2006.201.17:20:39.50#ibcon#read 4, iclass 31, count 0 2006.201.17:20:39.50#ibcon#about to read 5, iclass 31, count 0 2006.201.17:20:39.50#ibcon#read 5, iclass 31, count 0 2006.201.17:20:39.50#ibcon#about to read 6, iclass 31, count 0 2006.201.17:20:39.50#ibcon#read 6, iclass 31, count 0 2006.201.17:20:39.50#ibcon#end of sib2, iclass 31, count 0 2006.201.17:20:39.50#ibcon#*after write, iclass 31, count 0 2006.201.17:20:39.50#ibcon#*before return 0, iclass 31, count 0 2006.201.17:20:39.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:39.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:39.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:20:39.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:20:39.50$vck44/va=2,7 2006.201.17:20:39.50#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.17:20:39.50#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.17:20:39.50#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:39.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:39.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:39.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:39.55#ibcon#enter wrdev, iclass 33, count 2 2006.201.17:20:39.55#ibcon#first serial, iclass 33, count 2 2006.201.17:20:39.55#ibcon#enter sib2, iclass 33, count 2 2006.201.17:20:39.55#ibcon#flushed, iclass 33, count 2 2006.201.17:20:39.55#ibcon#about to write, iclass 33, count 2 2006.201.17:20:39.55#ibcon#wrote, iclass 33, count 2 2006.201.17:20:39.55#ibcon#about to read 3, iclass 33, count 2 2006.201.17:20:39.57#ibcon#read 3, iclass 33, count 2 2006.201.17:20:39.57#ibcon#about to read 4, iclass 33, count 2 2006.201.17:20:39.57#ibcon#read 4, iclass 33, count 2 2006.201.17:20:39.57#ibcon#about to read 5, iclass 33, count 2 2006.201.17:20:39.57#ibcon#read 5, iclass 33, count 2 2006.201.17:20:39.57#ibcon#about to read 6, iclass 33, count 2 2006.201.17:20:39.57#ibcon#read 6, iclass 33, count 2 2006.201.17:20:39.57#ibcon#end of sib2, iclass 33, count 2 2006.201.17:20:39.57#ibcon#*mode == 0, iclass 33, count 2 2006.201.17:20:39.57#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.17:20:39.57#ibcon#[25=AT02-07\r\n] 2006.201.17:20:39.57#ibcon#*before write, iclass 33, count 2 2006.201.17:20:39.57#ibcon#enter sib2, iclass 33, count 2 2006.201.17:20:39.57#ibcon#flushed, iclass 33, count 2 2006.201.17:20:39.57#ibcon#about to write, iclass 33, count 2 2006.201.17:20:39.57#ibcon#wrote, iclass 33, count 2 2006.201.17:20:39.57#ibcon#about to read 3, iclass 33, count 2 2006.201.17:20:39.60#ibcon#read 3, iclass 33, count 2 2006.201.17:20:39.60#ibcon#about to read 4, iclass 33, count 2 2006.201.17:20:39.60#ibcon#read 4, iclass 33, count 2 2006.201.17:20:39.60#ibcon#about to read 5, iclass 33, count 2 2006.201.17:20:39.60#ibcon#read 5, iclass 33, count 2 2006.201.17:20:39.60#ibcon#about to read 6, iclass 33, count 2 2006.201.17:20:39.60#ibcon#read 6, iclass 33, count 2 2006.201.17:20:39.60#ibcon#end of sib2, iclass 33, count 2 2006.201.17:20:39.60#ibcon#*after write, iclass 33, count 2 2006.201.17:20:39.60#ibcon#*before return 0, iclass 33, count 2 2006.201.17:20:39.60#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:39.60#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:39.60#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.17:20:39.60#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:39.60#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:39.72#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:39.72#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:39.72#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:20:39.72#ibcon#first serial, iclass 33, count 0 2006.201.17:20:39.72#ibcon#enter sib2, iclass 33, count 0 2006.201.17:20:39.72#ibcon#flushed, iclass 33, count 0 2006.201.17:20:39.72#ibcon#about to write, iclass 33, count 0 2006.201.17:20:39.72#ibcon#wrote, iclass 33, count 0 2006.201.17:20:39.72#ibcon#about to read 3, iclass 33, count 0 2006.201.17:20:39.74#ibcon#read 3, iclass 33, count 0 2006.201.17:20:39.74#ibcon#about to read 4, iclass 33, count 0 2006.201.17:20:39.74#ibcon#read 4, iclass 33, count 0 2006.201.17:20:39.74#ibcon#about to read 5, iclass 33, count 0 2006.201.17:20:39.74#ibcon#read 5, iclass 33, count 0 2006.201.17:20:39.74#ibcon#about to read 6, iclass 33, count 0 2006.201.17:20:39.74#ibcon#read 6, iclass 33, count 0 2006.201.17:20:39.74#ibcon#end of sib2, iclass 33, count 0 2006.201.17:20:39.74#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:20:39.74#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:20:39.74#ibcon#[25=USB\r\n] 2006.201.17:20:39.74#ibcon#*before write, iclass 33, count 0 2006.201.17:20:39.74#ibcon#enter sib2, iclass 33, count 0 2006.201.17:20:39.74#ibcon#flushed, iclass 33, count 0 2006.201.17:20:39.74#ibcon#about to write, iclass 33, count 0 2006.201.17:20:39.74#ibcon#wrote, iclass 33, count 0 2006.201.17:20:39.74#ibcon#about to read 3, iclass 33, count 0 2006.201.17:20:39.77#ibcon#read 3, iclass 33, count 0 2006.201.17:20:39.77#ibcon#about to read 4, iclass 33, count 0 2006.201.17:20:39.77#ibcon#read 4, iclass 33, count 0 2006.201.17:20:39.77#ibcon#about to read 5, iclass 33, count 0 2006.201.17:20:39.77#ibcon#read 5, iclass 33, count 0 2006.201.17:20:39.77#ibcon#about to read 6, iclass 33, count 0 2006.201.17:20:39.77#ibcon#read 6, iclass 33, count 0 2006.201.17:20:39.77#ibcon#end of sib2, iclass 33, count 0 2006.201.17:20:39.77#ibcon#*after write, iclass 33, count 0 2006.201.17:20:39.77#ibcon#*before return 0, iclass 33, count 0 2006.201.17:20:39.77#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:39.77#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:39.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:20:39.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:20:39.77$vck44/valo=3,564.99 2006.201.17:20:39.77#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.17:20:39.77#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.17:20:39.77#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:39.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:39.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:39.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:39.77#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:20:39.77#ibcon#first serial, iclass 35, count 0 2006.201.17:20:39.77#ibcon#enter sib2, iclass 35, count 0 2006.201.17:20:39.77#ibcon#flushed, iclass 35, count 0 2006.201.17:20:39.77#ibcon#about to write, iclass 35, count 0 2006.201.17:20:39.77#ibcon#wrote, iclass 35, count 0 2006.201.17:20:39.77#ibcon#about to read 3, iclass 35, count 0 2006.201.17:20:39.79#ibcon#read 3, iclass 35, count 0 2006.201.17:20:39.79#ibcon#about to read 4, iclass 35, count 0 2006.201.17:20:39.79#ibcon#read 4, iclass 35, count 0 2006.201.17:20:39.79#ibcon#about to read 5, iclass 35, count 0 2006.201.17:20:39.79#ibcon#read 5, iclass 35, count 0 2006.201.17:20:39.79#ibcon#about to read 6, iclass 35, count 0 2006.201.17:20:39.79#ibcon#read 6, iclass 35, count 0 2006.201.17:20:39.79#ibcon#end of sib2, iclass 35, count 0 2006.201.17:20:39.79#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:20:39.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:20:39.79#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.17:20:39.79#ibcon#*before write, iclass 35, count 0 2006.201.17:20:39.79#ibcon#enter sib2, iclass 35, count 0 2006.201.17:20:39.79#ibcon#flushed, iclass 35, count 0 2006.201.17:20:39.79#ibcon#about to write, iclass 35, count 0 2006.201.17:20:39.79#ibcon#wrote, iclass 35, count 0 2006.201.17:20:39.79#ibcon#about to read 3, iclass 35, count 0 2006.201.17:20:39.84#ibcon#read 3, iclass 35, count 0 2006.201.17:20:39.84#ibcon#about to read 4, iclass 35, count 0 2006.201.17:20:39.84#ibcon#read 4, iclass 35, count 0 2006.201.17:20:39.84#ibcon#about to read 5, iclass 35, count 0 2006.201.17:20:39.84#ibcon#read 5, iclass 35, count 0 2006.201.17:20:39.84#ibcon#about to read 6, iclass 35, count 0 2006.201.17:20:39.84#ibcon#read 6, iclass 35, count 0 2006.201.17:20:39.84#ibcon#end of sib2, iclass 35, count 0 2006.201.17:20:39.84#ibcon#*after write, iclass 35, count 0 2006.201.17:20:39.84#ibcon#*before return 0, iclass 35, count 0 2006.201.17:20:39.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:39.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:39.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:20:39.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:20:39.84$vck44/va=3,8 2006.201.17:20:39.84#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.17:20:39.84#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.17:20:39.84#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:39.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:39.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:39.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:39.89#ibcon#enter wrdev, iclass 37, count 2 2006.201.17:20:39.89#ibcon#first serial, iclass 37, count 2 2006.201.17:20:39.89#ibcon#enter sib2, iclass 37, count 2 2006.201.17:20:39.89#ibcon#flushed, iclass 37, count 2 2006.201.17:20:39.89#ibcon#about to write, iclass 37, count 2 2006.201.17:20:39.89#ibcon#wrote, iclass 37, count 2 2006.201.17:20:39.89#ibcon#about to read 3, iclass 37, count 2 2006.201.17:20:39.91#ibcon#read 3, iclass 37, count 2 2006.201.17:20:39.91#ibcon#about to read 4, iclass 37, count 2 2006.201.17:20:39.91#ibcon#read 4, iclass 37, count 2 2006.201.17:20:39.91#ibcon#about to read 5, iclass 37, count 2 2006.201.17:20:39.91#ibcon#read 5, iclass 37, count 2 2006.201.17:20:39.91#ibcon#about to read 6, iclass 37, count 2 2006.201.17:20:39.91#ibcon#read 6, iclass 37, count 2 2006.201.17:20:39.91#ibcon#end of sib2, iclass 37, count 2 2006.201.17:20:39.91#ibcon#*mode == 0, iclass 37, count 2 2006.201.17:20:39.91#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.17:20:39.91#ibcon#[25=AT03-08\r\n] 2006.201.17:20:39.91#ibcon#*before write, iclass 37, count 2 2006.201.17:20:39.91#ibcon#enter sib2, iclass 37, count 2 2006.201.17:20:39.91#ibcon#flushed, iclass 37, count 2 2006.201.17:20:39.91#ibcon#about to write, iclass 37, count 2 2006.201.17:20:39.91#ibcon#wrote, iclass 37, count 2 2006.201.17:20:39.91#ibcon#about to read 3, iclass 37, count 2 2006.201.17:20:39.94#ibcon#read 3, iclass 37, count 2 2006.201.17:20:39.94#ibcon#about to read 4, iclass 37, count 2 2006.201.17:20:39.94#ibcon#read 4, iclass 37, count 2 2006.201.17:20:39.94#ibcon#about to read 5, iclass 37, count 2 2006.201.17:20:39.94#ibcon#read 5, iclass 37, count 2 2006.201.17:20:39.94#ibcon#about to read 6, iclass 37, count 2 2006.201.17:20:39.94#ibcon#read 6, iclass 37, count 2 2006.201.17:20:39.94#ibcon#end of sib2, iclass 37, count 2 2006.201.17:20:39.94#ibcon#*after write, iclass 37, count 2 2006.201.17:20:39.94#ibcon#*before return 0, iclass 37, count 2 2006.201.17:20:39.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:39.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:39.94#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.17:20:39.94#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:39.94#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:40.06#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:40.06#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:40.06#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:20:40.06#ibcon#first serial, iclass 37, count 0 2006.201.17:20:40.06#ibcon#enter sib2, iclass 37, count 0 2006.201.17:20:40.06#ibcon#flushed, iclass 37, count 0 2006.201.17:20:40.06#ibcon#about to write, iclass 37, count 0 2006.201.17:20:40.06#ibcon#wrote, iclass 37, count 0 2006.201.17:20:40.06#ibcon#about to read 3, iclass 37, count 0 2006.201.17:20:40.09#ibcon#read 3, iclass 37, count 0 2006.201.17:20:40.09#ibcon#about to read 4, iclass 37, count 0 2006.201.17:20:40.09#ibcon#read 4, iclass 37, count 0 2006.201.17:20:40.09#ibcon#about to read 5, iclass 37, count 0 2006.201.17:20:40.09#ibcon#read 5, iclass 37, count 0 2006.201.17:20:40.09#ibcon#about to read 6, iclass 37, count 0 2006.201.17:20:40.09#ibcon#read 6, iclass 37, count 0 2006.201.17:20:40.09#ibcon#end of sib2, iclass 37, count 0 2006.201.17:20:40.09#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:20:40.09#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:20:40.09#ibcon#[25=USB\r\n] 2006.201.17:20:40.09#ibcon#*before write, iclass 37, count 0 2006.201.17:20:40.09#ibcon#enter sib2, iclass 37, count 0 2006.201.17:20:40.09#ibcon#flushed, iclass 37, count 0 2006.201.17:20:40.09#ibcon#about to write, iclass 37, count 0 2006.201.17:20:40.09#ibcon#wrote, iclass 37, count 0 2006.201.17:20:40.09#ibcon#about to read 3, iclass 37, count 0 2006.201.17:20:40.12#ibcon#read 3, iclass 37, count 0 2006.201.17:20:40.12#ibcon#about to read 4, iclass 37, count 0 2006.201.17:20:40.12#ibcon#read 4, iclass 37, count 0 2006.201.17:20:40.12#ibcon#about to read 5, iclass 37, count 0 2006.201.17:20:40.12#ibcon#read 5, iclass 37, count 0 2006.201.17:20:40.12#ibcon#about to read 6, iclass 37, count 0 2006.201.17:20:40.12#ibcon#read 6, iclass 37, count 0 2006.201.17:20:40.12#ibcon#end of sib2, iclass 37, count 0 2006.201.17:20:40.12#ibcon#*after write, iclass 37, count 0 2006.201.17:20:40.12#ibcon#*before return 0, iclass 37, count 0 2006.201.17:20:40.12#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:40.12#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:40.12#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:20:40.12#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:20:40.12$vck44/valo=4,624.99 2006.201.17:20:40.12#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.17:20:40.12#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.17:20:40.12#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:40.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:40.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:40.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:40.12#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:20:40.12#ibcon#first serial, iclass 39, count 0 2006.201.17:20:40.12#ibcon#enter sib2, iclass 39, count 0 2006.201.17:20:40.12#ibcon#flushed, iclass 39, count 0 2006.201.17:20:40.12#ibcon#about to write, iclass 39, count 0 2006.201.17:20:40.12#ibcon#wrote, iclass 39, count 0 2006.201.17:20:40.12#ibcon#about to read 3, iclass 39, count 0 2006.201.17:20:40.14#ibcon#read 3, iclass 39, count 0 2006.201.17:20:40.14#ibcon#about to read 4, iclass 39, count 0 2006.201.17:20:40.14#ibcon#read 4, iclass 39, count 0 2006.201.17:20:40.14#ibcon#about to read 5, iclass 39, count 0 2006.201.17:20:40.14#ibcon#read 5, iclass 39, count 0 2006.201.17:20:40.14#ibcon#about to read 6, iclass 39, count 0 2006.201.17:20:40.14#ibcon#read 6, iclass 39, count 0 2006.201.17:20:40.14#ibcon#end of sib2, iclass 39, count 0 2006.201.17:20:40.14#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:20:40.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:20:40.14#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.17:20:40.14#ibcon#*before write, iclass 39, count 0 2006.201.17:20:40.14#ibcon#enter sib2, iclass 39, count 0 2006.201.17:20:40.14#ibcon#flushed, iclass 39, count 0 2006.201.17:20:40.14#ibcon#about to write, iclass 39, count 0 2006.201.17:20:40.14#ibcon#wrote, iclass 39, count 0 2006.201.17:20:40.14#ibcon#about to read 3, iclass 39, count 0 2006.201.17:20:40.18#ibcon#read 3, iclass 39, count 0 2006.201.17:20:40.18#ibcon#about to read 4, iclass 39, count 0 2006.201.17:20:40.18#ibcon#read 4, iclass 39, count 0 2006.201.17:20:40.18#ibcon#about to read 5, iclass 39, count 0 2006.201.17:20:40.18#ibcon#read 5, iclass 39, count 0 2006.201.17:20:40.18#ibcon#about to read 6, iclass 39, count 0 2006.201.17:20:40.18#ibcon#read 6, iclass 39, count 0 2006.201.17:20:40.18#ibcon#end of sib2, iclass 39, count 0 2006.201.17:20:40.18#ibcon#*after write, iclass 39, count 0 2006.201.17:20:40.18#ibcon#*before return 0, iclass 39, count 0 2006.201.17:20:40.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:40.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:40.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:20:40.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:20:40.18$vck44/va=4,7 2006.201.17:20:40.18#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.17:20:40.18#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.17:20:40.18#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:40.18#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:40.24#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:40.24#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:40.24#ibcon#enter wrdev, iclass 2, count 2 2006.201.17:20:40.24#ibcon#first serial, iclass 2, count 2 2006.201.17:20:40.24#ibcon#enter sib2, iclass 2, count 2 2006.201.17:20:40.24#ibcon#flushed, iclass 2, count 2 2006.201.17:20:40.24#ibcon#about to write, iclass 2, count 2 2006.201.17:20:40.24#ibcon#wrote, iclass 2, count 2 2006.201.17:20:40.24#ibcon#about to read 3, iclass 2, count 2 2006.201.17:20:40.26#ibcon#read 3, iclass 2, count 2 2006.201.17:20:40.26#ibcon#about to read 4, iclass 2, count 2 2006.201.17:20:40.26#ibcon#read 4, iclass 2, count 2 2006.201.17:20:40.26#ibcon#about to read 5, iclass 2, count 2 2006.201.17:20:40.26#ibcon#read 5, iclass 2, count 2 2006.201.17:20:40.26#ibcon#about to read 6, iclass 2, count 2 2006.201.17:20:40.26#ibcon#read 6, iclass 2, count 2 2006.201.17:20:40.26#ibcon#end of sib2, iclass 2, count 2 2006.201.17:20:40.26#ibcon#*mode == 0, iclass 2, count 2 2006.201.17:20:40.26#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.17:20:40.26#ibcon#[25=AT04-07\r\n] 2006.201.17:20:40.26#ibcon#*before write, iclass 2, count 2 2006.201.17:20:40.26#ibcon#enter sib2, iclass 2, count 2 2006.201.17:20:40.26#ibcon#flushed, iclass 2, count 2 2006.201.17:20:40.26#ibcon#about to write, iclass 2, count 2 2006.201.17:20:40.26#ibcon#wrote, iclass 2, count 2 2006.201.17:20:40.26#ibcon#about to read 3, iclass 2, count 2 2006.201.17:20:40.29#ibcon#read 3, iclass 2, count 2 2006.201.17:20:40.29#ibcon#about to read 4, iclass 2, count 2 2006.201.17:20:40.29#ibcon#read 4, iclass 2, count 2 2006.201.17:20:40.29#ibcon#about to read 5, iclass 2, count 2 2006.201.17:20:40.29#ibcon#read 5, iclass 2, count 2 2006.201.17:20:40.29#ibcon#about to read 6, iclass 2, count 2 2006.201.17:20:40.29#ibcon#read 6, iclass 2, count 2 2006.201.17:20:40.29#ibcon#end of sib2, iclass 2, count 2 2006.201.17:20:40.29#ibcon#*after write, iclass 2, count 2 2006.201.17:20:40.29#ibcon#*before return 0, iclass 2, count 2 2006.201.17:20:40.29#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:40.29#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:40.29#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.17:20:40.29#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:40.29#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:40.41#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:40.41#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:40.41#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:20:40.41#ibcon#first serial, iclass 2, count 0 2006.201.17:20:40.41#ibcon#enter sib2, iclass 2, count 0 2006.201.17:20:40.41#ibcon#flushed, iclass 2, count 0 2006.201.17:20:40.41#ibcon#about to write, iclass 2, count 0 2006.201.17:20:40.41#ibcon#wrote, iclass 2, count 0 2006.201.17:20:40.41#ibcon#about to read 3, iclass 2, count 0 2006.201.17:20:40.43#ibcon#read 3, iclass 2, count 0 2006.201.17:20:40.43#ibcon#about to read 4, iclass 2, count 0 2006.201.17:20:40.43#ibcon#read 4, iclass 2, count 0 2006.201.17:20:40.43#ibcon#about to read 5, iclass 2, count 0 2006.201.17:20:40.43#ibcon#read 5, iclass 2, count 0 2006.201.17:20:40.43#ibcon#about to read 6, iclass 2, count 0 2006.201.17:20:40.43#ibcon#read 6, iclass 2, count 0 2006.201.17:20:40.43#ibcon#end of sib2, iclass 2, count 0 2006.201.17:20:40.43#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:20:40.43#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:20:40.43#ibcon#[25=USB\r\n] 2006.201.17:20:40.43#ibcon#*before write, iclass 2, count 0 2006.201.17:20:40.43#ibcon#enter sib2, iclass 2, count 0 2006.201.17:20:40.43#ibcon#flushed, iclass 2, count 0 2006.201.17:20:40.43#ibcon#about to write, iclass 2, count 0 2006.201.17:20:40.43#ibcon#wrote, iclass 2, count 0 2006.201.17:20:40.43#ibcon#about to read 3, iclass 2, count 0 2006.201.17:20:40.46#ibcon#read 3, iclass 2, count 0 2006.201.17:20:40.46#ibcon#about to read 4, iclass 2, count 0 2006.201.17:20:40.46#ibcon#read 4, iclass 2, count 0 2006.201.17:20:40.46#ibcon#about to read 5, iclass 2, count 0 2006.201.17:20:40.46#ibcon#read 5, iclass 2, count 0 2006.201.17:20:40.46#ibcon#about to read 6, iclass 2, count 0 2006.201.17:20:40.46#ibcon#read 6, iclass 2, count 0 2006.201.17:20:40.46#ibcon#end of sib2, iclass 2, count 0 2006.201.17:20:40.46#ibcon#*after write, iclass 2, count 0 2006.201.17:20:40.46#ibcon#*before return 0, iclass 2, count 0 2006.201.17:20:40.46#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:40.46#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:40.46#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:20:40.46#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:20:40.46$vck44/valo=5,734.99 2006.201.17:20:40.46#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.17:20:40.46#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.17:20:40.46#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:40.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:40.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:40.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:40.46#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:20:40.46#ibcon#first serial, iclass 5, count 0 2006.201.17:20:40.46#ibcon#enter sib2, iclass 5, count 0 2006.201.17:20:40.46#ibcon#flushed, iclass 5, count 0 2006.201.17:20:40.46#ibcon#about to write, iclass 5, count 0 2006.201.17:20:40.46#ibcon#wrote, iclass 5, count 0 2006.201.17:20:40.46#ibcon#about to read 3, iclass 5, count 0 2006.201.17:20:40.48#ibcon#read 3, iclass 5, count 0 2006.201.17:20:40.48#ibcon#about to read 4, iclass 5, count 0 2006.201.17:20:40.48#ibcon#read 4, iclass 5, count 0 2006.201.17:20:40.48#ibcon#about to read 5, iclass 5, count 0 2006.201.17:20:40.48#ibcon#read 5, iclass 5, count 0 2006.201.17:20:40.48#ibcon#about to read 6, iclass 5, count 0 2006.201.17:20:40.48#ibcon#read 6, iclass 5, count 0 2006.201.17:20:40.48#ibcon#end of sib2, iclass 5, count 0 2006.201.17:20:40.48#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:20:40.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:20:40.48#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.17:20:40.48#ibcon#*before write, iclass 5, count 0 2006.201.17:20:40.48#ibcon#enter sib2, iclass 5, count 0 2006.201.17:20:40.48#ibcon#flushed, iclass 5, count 0 2006.201.17:20:40.48#ibcon#about to write, iclass 5, count 0 2006.201.17:20:40.48#ibcon#wrote, iclass 5, count 0 2006.201.17:20:40.48#ibcon#about to read 3, iclass 5, count 0 2006.201.17:20:40.52#ibcon#read 3, iclass 5, count 0 2006.201.17:20:40.52#ibcon#about to read 4, iclass 5, count 0 2006.201.17:20:40.52#ibcon#read 4, iclass 5, count 0 2006.201.17:20:40.52#ibcon#about to read 5, iclass 5, count 0 2006.201.17:20:40.52#ibcon#read 5, iclass 5, count 0 2006.201.17:20:40.52#ibcon#about to read 6, iclass 5, count 0 2006.201.17:20:40.52#ibcon#read 6, iclass 5, count 0 2006.201.17:20:40.52#ibcon#end of sib2, iclass 5, count 0 2006.201.17:20:40.52#ibcon#*after write, iclass 5, count 0 2006.201.17:20:40.52#ibcon#*before return 0, iclass 5, count 0 2006.201.17:20:40.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:40.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:40.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:20:40.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:20:40.52$vck44/va=5,4 2006.201.17:20:40.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.17:20:40.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.17:20:40.52#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:40.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:40.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:40.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:40.58#ibcon#enter wrdev, iclass 7, count 2 2006.201.17:20:40.58#ibcon#first serial, iclass 7, count 2 2006.201.17:20:40.58#ibcon#enter sib2, iclass 7, count 2 2006.201.17:20:40.58#ibcon#flushed, iclass 7, count 2 2006.201.17:20:40.58#ibcon#about to write, iclass 7, count 2 2006.201.17:20:40.58#ibcon#wrote, iclass 7, count 2 2006.201.17:20:40.58#ibcon#about to read 3, iclass 7, count 2 2006.201.17:20:40.60#ibcon#read 3, iclass 7, count 2 2006.201.17:20:40.60#ibcon#about to read 4, iclass 7, count 2 2006.201.17:20:40.60#ibcon#read 4, iclass 7, count 2 2006.201.17:20:40.60#ibcon#about to read 5, iclass 7, count 2 2006.201.17:20:40.60#ibcon#read 5, iclass 7, count 2 2006.201.17:20:40.60#ibcon#about to read 6, iclass 7, count 2 2006.201.17:20:40.60#ibcon#read 6, iclass 7, count 2 2006.201.17:20:40.60#ibcon#end of sib2, iclass 7, count 2 2006.201.17:20:40.60#ibcon#*mode == 0, iclass 7, count 2 2006.201.17:20:40.60#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.17:20:40.60#ibcon#[25=AT05-04\r\n] 2006.201.17:20:40.60#ibcon#*before write, iclass 7, count 2 2006.201.17:20:40.60#ibcon#enter sib2, iclass 7, count 2 2006.201.17:20:40.60#ibcon#flushed, iclass 7, count 2 2006.201.17:20:40.60#ibcon#about to write, iclass 7, count 2 2006.201.17:20:40.60#ibcon#wrote, iclass 7, count 2 2006.201.17:20:40.60#ibcon#about to read 3, iclass 7, count 2 2006.201.17:20:40.63#ibcon#read 3, iclass 7, count 2 2006.201.17:20:40.63#ibcon#about to read 4, iclass 7, count 2 2006.201.17:20:40.63#ibcon#read 4, iclass 7, count 2 2006.201.17:20:40.63#ibcon#about to read 5, iclass 7, count 2 2006.201.17:20:40.63#ibcon#read 5, iclass 7, count 2 2006.201.17:20:40.63#ibcon#about to read 6, iclass 7, count 2 2006.201.17:20:40.63#ibcon#read 6, iclass 7, count 2 2006.201.17:20:40.63#ibcon#end of sib2, iclass 7, count 2 2006.201.17:20:40.63#ibcon#*after write, iclass 7, count 2 2006.201.17:20:40.63#ibcon#*before return 0, iclass 7, count 2 2006.201.17:20:40.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:40.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:40.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.17:20:40.63#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:40.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:40.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:40.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:40.75#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:20:40.75#ibcon#first serial, iclass 7, count 0 2006.201.17:20:40.75#ibcon#enter sib2, iclass 7, count 0 2006.201.17:20:40.75#ibcon#flushed, iclass 7, count 0 2006.201.17:20:40.75#ibcon#about to write, iclass 7, count 0 2006.201.17:20:40.75#ibcon#wrote, iclass 7, count 0 2006.201.17:20:40.75#ibcon#about to read 3, iclass 7, count 0 2006.201.17:20:40.77#ibcon#read 3, iclass 7, count 0 2006.201.17:20:40.77#ibcon#about to read 4, iclass 7, count 0 2006.201.17:20:40.77#ibcon#read 4, iclass 7, count 0 2006.201.17:20:40.77#ibcon#about to read 5, iclass 7, count 0 2006.201.17:20:40.77#ibcon#read 5, iclass 7, count 0 2006.201.17:20:40.77#ibcon#about to read 6, iclass 7, count 0 2006.201.17:20:40.77#ibcon#read 6, iclass 7, count 0 2006.201.17:20:40.77#ibcon#end of sib2, iclass 7, count 0 2006.201.17:20:40.77#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:20:40.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:20:40.77#ibcon#[25=USB\r\n] 2006.201.17:20:40.77#ibcon#*before write, iclass 7, count 0 2006.201.17:20:40.77#ibcon#enter sib2, iclass 7, count 0 2006.201.17:20:40.77#ibcon#flushed, iclass 7, count 0 2006.201.17:20:40.77#ibcon#about to write, iclass 7, count 0 2006.201.17:20:40.77#ibcon#wrote, iclass 7, count 0 2006.201.17:20:40.77#ibcon#about to read 3, iclass 7, count 0 2006.201.17:20:40.80#ibcon#read 3, iclass 7, count 0 2006.201.17:20:40.80#ibcon#about to read 4, iclass 7, count 0 2006.201.17:20:40.80#ibcon#read 4, iclass 7, count 0 2006.201.17:20:40.80#ibcon#about to read 5, iclass 7, count 0 2006.201.17:20:40.80#ibcon#read 5, iclass 7, count 0 2006.201.17:20:40.80#ibcon#about to read 6, iclass 7, count 0 2006.201.17:20:40.80#ibcon#read 6, iclass 7, count 0 2006.201.17:20:40.80#ibcon#end of sib2, iclass 7, count 0 2006.201.17:20:40.80#ibcon#*after write, iclass 7, count 0 2006.201.17:20:40.80#ibcon#*before return 0, iclass 7, count 0 2006.201.17:20:40.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:40.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:40.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:20:40.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:20:40.80$vck44/valo=6,814.99 2006.201.17:20:40.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.17:20:40.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.17:20:40.80#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:40.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:40.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:40.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:40.80#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:20:40.80#ibcon#first serial, iclass 11, count 0 2006.201.17:20:40.80#ibcon#enter sib2, iclass 11, count 0 2006.201.17:20:40.80#ibcon#flushed, iclass 11, count 0 2006.201.17:20:40.80#ibcon#about to write, iclass 11, count 0 2006.201.17:20:40.80#ibcon#wrote, iclass 11, count 0 2006.201.17:20:40.80#ibcon#about to read 3, iclass 11, count 0 2006.201.17:20:40.82#ibcon#read 3, iclass 11, count 0 2006.201.17:20:40.82#ibcon#about to read 4, iclass 11, count 0 2006.201.17:20:40.82#ibcon#read 4, iclass 11, count 0 2006.201.17:20:40.82#ibcon#about to read 5, iclass 11, count 0 2006.201.17:20:40.82#ibcon#read 5, iclass 11, count 0 2006.201.17:20:40.82#ibcon#about to read 6, iclass 11, count 0 2006.201.17:20:40.82#ibcon#read 6, iclass 11, count 0 2006.201.17:20:40.82#ibcon#end of sib2, iclass 11, count 0 2006.201.17:20:40.82#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:20:40.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:20:40.82#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.17:20:40.82#ibcon#*before write, iclass 11, count 0 2006.201.17:20:40.82#ibcon#enter sib2, iclass 11, count 0 2006.201.17:20:40.82#ibcon#flushed, iclass 11, count 0 2006.201.17:20:40.82#ibcon#about to write, iclass 11, count 0 2006.201.17:20:40.82#ibcon#wrote, iclass 11, count 0 2006.201.17:20:40.82#ibcon#about to read 3, iclass 11, count 0 2006.201.17:20:40.87#ibcon#read 3, iclass 11, count 0 2006.201.17:20:40.87#ibcon#about to read 4, iclass 11, count 0 2006.201.17:20:40.87#ibcon#read 4, iclass 11, count 0 2006.201.17:20:40.87#ibcon#about to read 5, iclass 11, count 0 2006.201.17:20:40.87#ibcon#read 5, iclass 11, count 0 2006.201.17:20:40.87#ibcon#about to read 6, iclass 11, count 0 2006.201.17:20:40.87#ibcon#read 6, iclass 11, count 0 2006.201.17:20:40.87#ibcon#end of sib2, iclass 11, count 0 2006.201.17:20:40.87#ibcon#*after write, iclass 11, count 0 2006.201.17:20:40.87#ibcon#*before return 0, iclass 11, count 0 2006.201.17:20:40.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:40.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:40.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:20:40.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:20:40.87$vck44/va=6,5 2006.201.17:20:40.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.17:20:40.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.17:20:40.87#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:40.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:40.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:40.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:40.92#ibcon#enter wrdev, iclass 13, count 2 2006.201.17:20:40.92#ibcon#first serial, iclass 13, count 2 2006.201.17:20:40.92#ibcon#enter sib2, iclass 13, count 2 2006.201.17:20:40.92#ibcon#flushed, iclass 13, count 2 2006.201.17:20:40.92#ibcon#about to write, iclass 13, count 2 2006.201.17:20:40.92#ibcon#wrote, iclass 13, count 2 2006.201.17:20:40.92#ibcon#about to read 3, iclass 13, count 2 2006.201.17:20:40.94#ibcon#read 3, iclass 13, count 2 2006.201.17:20:40.94#ibcon#about to read 4, iclass 13, count 2 2006.201.17:20:40.94#ibcon#read 4, iclass 13, count 2 2006.201.17:20:40.94#ibcon#about to read 5, iclass 13, count 2 2006.201.17:20:40.94#ibcon#read 5, iclass 13, count 2 2006.201.17:20:40.94#ibcon#about to read 6, iclass 13, count 2 2006.201.17:20:40.94#ibcon#read 6, iclass 13, count 2 2006.201.17:20:40.94#ibcon#end of sib2, iclass 13, count 2 2006.201.17:20:40.94#ibcon#*mode == 0, iclass 13, count 2 2006.201.17:20:40.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.17:20:40.94#ibcon#[25=AT06-05\r\n] 2006.201.17:20:40.94#ibcon#*before write, iclass 13, count 2 2006.201.17:20:40.94#ibcon#enter sib2, iclass 13, count 2 2006.201.17:20:40.94#ibcon#flushed, iclass 13, count 2 2006.201.17:20:40.94#ibcon#about to write, iclass 13, count 2 2006.201.17:20:40.94#ibcon#wrote, iclass 13, count 2 2006.201.17:20:40.94#ibcon#about to read 3, iclass 13, count 2 2006.201.17:20:40.97#ibcon#read 3, iclass 13, count 2 2006.201.17:20:40.97#ibcon#about to read 4, iclass 13, count 2 2006.201.17:20:40.97#ibcon#read 4, iclass 13, count 2 2006.201.17:20:40.97#ibcon#about to read 5, iclass 13, count 2 2006.201.17:20:40.97#ibcon#read 5, iclass 13, count 2 2006.201.17:20:40.97#ibcon#about to read 6, iclass 13, count 2 2006.201.17:20:40.97#ibcon#read 6, iclass 13, count 2 2006.201.17:20:40.97#ibcon#end of sib2, iclass 13, count 2 2006.201.17:20:40.97#ibcon#*after write, iclass 13, count 2 2006.201.17:20:40.97#ibcon#*before return 0, iclass 13, count 2 2006.201.17:20:40.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:40.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:40.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.17:20:40.97#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:40.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:41.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:41.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:41.09#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:20:41.09#ibcon#first serial, iclass 13, count 0 2006.201.17:20:41.09#ibcon#enter sib2, iclass 13, count 0 2006.201.17:20:41.09#ibcon#flushed, iclass 13, count 0 2006.201.17:20:41.09#ibcon#about to write, iclass 13, count 0 2006.201.17:20:41.09#ibcon#wrote, iclass 13, count 0 2006.201.17:20:41.09#ibcon#about to read 3, iclass 13, count 0 2006.201.17:20:41.11#ibcon#read 3, iclass 13, count 0 2006.201.17:20:41.11#ibcon#about to read 4, iclass 13, count 0 2006.201.17:20:41.11#ibcon#read 4, iclass 13, count 0 2006.201.17:20:41.11#ibcon#about to read 5, iclass 13, count 0 2006.201.17:20:41.11#ibcon#read 5, iclass 13, count 0 2006.201.17:20:41.11#ibcon#about to read 6, iclass 13, count 0 2006.201.17:20:41.11#ibcon#read 6, iclass 13, count 0 2006.201.17:20:41.11#ibcon#end of sib2, iclass 13, count 0 2006.201.17:20:41.11#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:20:41.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:20:41.11#ibcon#[25=USB\r\n] 2006.201.17:20:41.11#ibcon#*before write, iclass 13, count 0 2006.201.17:20:41.11#ibcon#enter sib2, iclass 13, count 0 2006.201.17:20:41.11#ibcon#flushed, iclass 13, count 0 2006.201.17:20:41.11#ibcon#about to write, iclass 13, count 0 2006.201.17:20:41.11#ibcon#wrote, iclass 13, count 0 2006.201.17:20:41.11#ibcon#about to read 3, iclass 13, count 0 2006.201.17:20:41.14#ibcon#read 3, iclass 13, count 0 2006.201.17:20:41.14#ibcon#about to read 4, iclass 13, count 0 2006.201.17:20:41.14#ibcon#read 4, iclass 13, count 0 2006.201.17:20:41.14#ibcon#about to read 5, iclass 13, count 0 2006.201.17:20:41.14#ibcon#read 5, iclass 13, count 0 2006.201.17:20:41.14#ibcon#about to read 6, iclass 13, count 0 2006.201.17:20:41.14#ibcon#read 6, iclass 13, count 0 2006.201.17:20:41.14#ibcon#end of sib2, iclass 13, count 0 2006.201.17:20:41.14#ibcon#*after write, iclass 13, count 0 2006.201.17:20:41.14#ibcon#*before return 0, iclass 13, count 0 2006.201.17:20:41.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:41.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:41.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:20:41.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:20:41.14$vck44/valo=7,864.99 2006.201.17:20:41.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.17:20:41.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.17:20:41.14#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:41.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:41.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:41.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:41.14#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:20:41.14#ibcon#first serial, iclass 15, count 0 2006.201.17:20:41.14#ibcon#enter sib2, iclass 15, count 0 2006.201.17:20:41.14#ibcon#flushed, iclass 15, count 0 2006.201.17:20:41.14#ibcon#about to write, iclass 15, count 0 2006.201.17:20:41.14#ibcon#wrote, iclass 15, count 0 2006.201.17:20:41.14#ibcon#about to read 3, iclass 15, count 0 2006.201.17:20:41.16#ibcon#read 3, iclass 15, count 0 2006.201.17:20:41.16#ibcon#about to read 4, iclass 15, count 0 2006.201.17:20:41.16#ibcon#read 4, iclass 15, count 0 2006.201.17:20:41.16#ibcon#about to read 5, iclass 15, count 0 2006.201.17:20:41.16#ibcon#read 5, iclass 15, count 0 2006.201.17:20:41.16#ibcon#about to read 6, iclass 15, count 0 2006.201.17:20:41.16#ibcon#read 6, iclass 15, count 0 2006.201.17:20:41.16#ibcon#end of sib2, iclass 15, count 0 2006.201.17:20:41.16#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:20:41.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:20:41.16#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.17:20:41.16#ibcon#*before write, iclass 15, count 0 2006.201.17:20:41.16#ibcon#enter sib2, iclass 15, count 0 2006.201.17:20:41.16#ibcon#flushed, iclass 15, count 0 2006.201.17:20:41.16#ibcon#about to write, iclass 15, count 0 2006.201.17:20:41.16#ibcon#wrote, iclass 15, count 0 2006.201.17:20:41.16#ibcon#about to read 3, iclass 15, count 0 2006.201.17:20:41.20#ibcon#read 3, iclass 15, count 0 2006.201.17:20:41.20#ibcon#about to read 4, iclass 15, count 0 2006.201.17:20:41.20#ibcon#read 4, iclass 15, count 0 2006.201.17:20:41.20#ibcon#about to read 5, iclass 15, count 0 2006.201.17:20:41.20#ibcon#read 5, iclass 15, count 0 2006.201.17:20:41.20#ibcon#about to read 6, iclass 15, count 0 2006.201.17:20:41.20#ibcon#read 6, iclass 15, count 0 2006.201.17:20:41.20#ibcon#end of sib2, iclass 15, count 0 2006.201.17:20:41.20#ibcon#*after write, iclass 15, count 0 2006.201.17:20:41.20#ibcon#*before return 0, iclass 15, count 0 2006.201.17:20:41.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:41.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:41.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:20:41.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:20:41.20$vck44/va=7,5 2006.201.17:20:41.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.17:20:41.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.17:20:41.20#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:41.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:41.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:41.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:41.26#ibcon#enter wrdev, iclass 17, count 2 2006.201.17:20:41.26#ibcon#first serial, iclass 17, count 2 2006.201.17:20:41.26#ibcon#enter sib2, iclass 17, count 2 2006.201.17:20:41.26#ibcon#flushed, iclass 17, count 2 2006.201.17:20:41.26#ibcon#about to write, iclass 17, count 2 2006.201.17:20:41.26#ibcon#wrote, iclass 17, count 2 2006.201.17:20:41.26#ibcon#about to read 3, iclass 17, count 2 2006.201.17:20:41.28#ibcon#read 3, iclass 17, count 2 2006.201.17:20:41.28#ibcon#about to read 4, iclass 17, count 2 2006.201.17:20:41.28#ibcon#read 4, iclass 17, count 2 2006.201.17:20:41.28#ibcon#about to read 5, iclass 17, count 2 2006.201.17:20:41.28#ibcon#read 5, iclass 17, count 2 2006.201.17:20:41.28#ibcon#about to read 6, iclass 17, count 2 2006.201.17:20:41.28#ibcon#read 6, iclass 17, count 2 2006.201.17:20:41.28#ibcon#end of sib2, iclass 17, count 2 2006.201.17:20:41.28#ibcon#*mode == 0, iclass 17, count 2 2006.201.17:20:41.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.17:20:41.28#ibcon#[25=AT07-05\r\n] 2006.201.17:20:41.28#ibcon#*before write, iclass 17, count 2 2006.201.17:20:41.28#ibcon#enter sib2, iclass 17, count 2 2006.201.17:20:41.28#ibcon#flushed, iclass 17, count 2 2006.201.17:20:41.28#ibcon#about to write, iclass 17, count 2 2006.201.17:20:41.28#ibcon#wrote, iclass 17, count 2 2006.201.17:20:41.28#ibcon#about to read 3, iclass 17, count 2 2006.201.17:20:41.31#ibcon#read 3, iclass 17, count 2 2006.201.17:20:41.31#ibcon#about to read 4, iclass 17, count 2 2006.201.17:20:41.31#ibcon#read 4, iclass 17, count 2 2006.201.17:20:41.31#ibcon#about to read 5, iclass 17, count 2 2006.201.17:20:41.31#ibcon#read 5, iclass 17, count 2 2006.201.17:20:41.31#ibcon#about to read 6, iclass 17, count 2 2006.201.17:20:41.31#ibcon#read 6, iclass 17, count 2 2006.201.17:20:41.31#ibcon#end of sib2, iclass 17, count 2 2006.201.17:20:41.31#ibcon#*after write, iclass 17, count 2 2006.201.17:20:41.31#ibcon#*before return 0, iclass 17, count 2 2006.201.17:20:41.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:41.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:41.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.17:20:41.31#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:41.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:41.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:41.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:41.43#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:20:41.43#ibcon#first serial, iclass 17, count 0 2006.201.17:20:41.43#ibcon#enter sib2, iclass 17, count 0 2006.201.17:20:41.43#ibcon#flushed, iclass 17, count 0 2006.201.17:20:41.43#ibcon#about to write, iclass 17, count 0 2006.201.17:20:41.43#ibcon#wrote, iclass 17, count 0 2006.201.17:20:41.43#ibcon#about to read 3, iclass 17, count 0 2006.201.17:20:41.45#ibcon#read 3, iclass 17, count 0 2006.201.17:20:41.45#ibcon#about to read 4, iclass 17, count 0 2006.201.17:20:41.45#ibcon#read 4, iclass 17, count 0 2006.201.17:20:41.45#ibcon#about to read 5, iclass 17, count 0 2006.201.17:20:41.45#ibcon#read 5, iclass 17, count 0 2006.201.17:20:41.45#ibcon#about to read 6, iclass 17, count 0 2006.201.17:20:41.45#ibcon#read 6, iclass 17, count 0 2006.201.17:20:41.45#ibcon#end of sib2, iclass 17, count 0 2006.201.17:20:41.45#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:20:41.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:20:41.45#ibcon#[25=USB\r\n] 2006.201.17:20:41.45#ibcon#*before write, iclass 17, count 0 2006.201.17:20:41.45#ibcon#enter sib2, iclass 17, count 0 2006.201.17:20:41.45#ibcon#flushed, iclass 17, count 0 2006.201.17:20:41.45#ibcon#about to write, iclass 17, count 0 2006.201.17:20:41.45#ibcon#wrote, iclass 17, count 0 2006.201.17:20:41.45#ibcon#about to read 3, iclass 17, count 0 2006.201.17:20:41.48#ibcon#read 3, iclass 17, count 0 2006.201.17:20:41.48#ibcon#about to read 4, iclass 17, count 0 2006.201.17:20:41.48#ibcon#read 4, iclass 17, count 0 2006.201.17:20:41.48#ibcon#about to read 5, iclass 17, count 0 2006.201.17:20:41.48#ibcon#read 5, iclass 17, count 0 2006.201.17:20:41.48#ibcon#about to read 6, iclass 17, count 0 2006.201.17:20:41.48#ibcon#read 6, iclass 17, count 0 2006.201.17:20:41.48#ibcon#end of sib2, iclass 17, count 0 2006.201.17:20:41.48#ibcon#*after write, iclass 17, count 0 2006.201.17:20:41.48#ibcon#*before return 0, iclass 17, count 0 2006.201.17:20:41.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:41.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:41.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:20:41.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:20:41.48$vck44/valo=8,884.99 2006.201.17:20:41.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.17:20:41.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.17:20:41.48#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:41.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:41.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:41.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:41.48#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:20:41.48#ibcon#first serial, iclass 19, count 0 2006.201.17:20:41.48#ibcon#enter sib2, iclass 19, count 0 2006.201.17:20:41.48#ibcon#flushed, iclass 19, count 0 2006.201.17:20:41.48#ibcon#about to write, iclass 19, count 0 2006.201.17:20:41.48#ibcon#wrote, iclass 19, count 0 2006.201.17:20:41.48#ibcon#about to read 3, iclass 19, count 0 2006.201.17:20:41.50#ibcon#read 3, iclass 19, count 0 2006.201.17:20:41.50#ibcon#about to read 4, iclass 19, count 0 2006.201.17:20:41.50#ibcon#read 4, iclass 19, count 0 2006.201.17:20:41.50#ibcon#about to read 5, iclass 19, count 0 2006.201.17:20:41.50#ibcon#read 5, iclass 19, count 0 2006.201.17:20:41.50#ibcon#about to read 6, iclass 19, count 0 2006.201.17:20:41.50#ibcon#read 6, iclass 19, count 0 2006.201.17:20:41.50#ibcon#end of sib2, iclass 19, count 0 2006.201.17:20:41.50#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:20:41.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:20:41.50#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.17:20:41.50#ibcon#*before write, iclass 19, count 0 2006.201.17:20:41.50#ibcon#enter sib2, iclass 19, count 0 2006.201.17:20:41.50#ibcon#flushed, iclass 19, count 0 2006.201.17:20:41.50#ibcon#about to write, iclass 19, count 0 2006.201.17:20:41.50#ibcon#wrote, iclass 19, count 0 2006.201.17:20:41.50#ibcon#about to read 3, iclass 19, count 0 2006.201.17:20:41.54#ibcon#read 3, iclass 19, count 0 2006.201.17:20:41.54#ibcon#about to read 4, iclass 19, count 0 2006.201.17:20:41.54#ibcon#read 4, iclass 19, count 0 2006.201.17:20:41.54#ibcon#about to read 5, iclass 19, count 0 2006.201.17:20:41.54#ibcon#read 5, iclass 19, count 0 2006.201.17:20:41.54#ibcon#about to read 6, iclass 19, count 0 2006.201.17:20:41.54#ibcon#read 6, iclass 19, count 0 2006.201.17:20:41.54#ibcon#end of sib2, iclass 19, count 0 2006.201.17:20:41.54#ibcon#*after write, iclass 19, count 0 2006.201.17:20:41.54#ibcon#*before return 0, iclass 19, count 0 2006.201.17:20:41.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:41.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:41.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:20:41.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:20:41.54$vck44/va=8,4 2006.201.17:20:41.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.17:20:41.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.17:20:41.54#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:41.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:20:41.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:20:41.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:20:41.60#ibcon#enter wrdev, iclass 21, count 2 2006.201.17:20:41.60#ibcon#first serial, iclass 21, count 2 2006.201.17:20:41.60#ibcon#enter sib2, iclass 21, count 2 2006.201.17:20:41.60#ibcon#flushed, iclass 21, count 2 2006.201.17:20:41.60#ibcon#about to write, iclass 21, count 2 2006.201.17:20:41.60#ibcon#wrote, iclass 21, count 2 2006.201.17:20:41.60#ibcon#about to read 3, iclass 21, count 2 2006.201.17:20:41.62#ibcon#read 3, iclass 21, count 2 2006.201.17:20:41.62#ibcon#about to read 4, iclass 21, count 2 2006.201.17:20:41.62#ibcon#read 4, iclass 21, count 2 2006.201.17:20:41.62#ibcon#about to read 5, iclass 21, count 2 2006.201.17:20:41.62#ibcon#read 5, iclass 21, count 2 2006.201.17:20:41.62#ibcon#about to read 6, iclass 21, count 2 2006.201.17:20:41.62#ibcon#read 6, iclass 21, count 2 2006.201.17:20:41.62#ibcon#end of sib2, iclass 21, count 2 2006.201.17:20:41.62#ibcon#*mode == 0, iclass 21, count 2 2006.201.17:20:41.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.17:20:41.62#ibcon#[25=AT08-04\r\n] 2006.201.17:20:41.62#ibcon#*before write, iclass 21, count 2 2006.201.17:20:41.62#ibcon#enter sib2, iclass 21, count 2 2006.201.17:20:41.62#ibcon#flushed, iclass 21, count 2 2006.201.17:20:41.62#ibcon#about to write, iclass 21, count 2 2006.201.17:20:41.62#ibcon#wrote, iclass 21, count 2 2006.201.17:20:41.62#ibcon#about to read 3, iclass 21, count 2 2006.201.17:20:41.65#ibcon#read 3, iclass 21, count 2 2006.201.17:20:41.65#ibcon#about to read 4, iclass 21, count 2 2006.201.17:20:41.65#ibcon#read 4, iclass 21, count 2 2006.201.17:20:41.65#ibcon#about to read 5, iclass 21, count 2 2006.201.17:20:41.65#ibcon#read 5, iclass 21, count 2 2006.201.17:20:41.65#ibcon#about to read 6, iclass 21, count 2 2006.201.17:20:41.65#ibcon#read 6, iclass 21, count 2 2006.201.17:20:41.65#ibcon#end of sib2, iclass 21, count 2 2006.201.17:20:41.65#ibcon#*after write, iclass 21, count 2 2006.201.17:20:41.65#ibcon#*before return 0, iclass 21, count 2 2006.201.17:20:41.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:20:41.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:20:41.65#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.17:20:41.65#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:41.65#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:20:41.77#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:20:41.77#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:20:41.77#ibcon#enter wrdev, iclass 21, count 0 2006.201.17:20:41.77#ibcon#first serial, iclass 21, count 0 2006.201.17:20:41.77#ibcon#enter sib2, iclass 21, count 0 2006.201.17:20:41.77#ibcon#flushed, iclass 21, count 0 2006.201.17:20:41.77#ibcon#about to write, iclass 21, count 0 2006.201.17:20:41.77#ibcon#wrote, iclass 21, count 0 2006.201.17:20:41.77#ibcon#about to read 3, iclass 21, count 0 2006.201.17:20:41.79#ibcon#read 3, iclass 21, count 0 2006.201.17:20:41.79#ibcon#about to read 4, iclass 21, count 0 2006.201.17:20:41.79#ibcon#read 4, iclass 21, count 0 2006.201.17:20:41.79#ibcon#about to read 5, iclass 21, count 0 2006.201.17:20:41.79#ibcon#read 5, iclass 21, count 0 2006.201.17:20:41.79#ibcon#about to read 6, iclass 21, count 0 2006.201.17:20:41.79#ibcon#read 6, iclass 21, count 0 2006.201.17:20:41.79#ibcon#end of sib2, iclass 21, count 0 2006.201.17:20:41.79#ibcon#*mode == 0, iclass 21, count 0 2006.201.17:20:41.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.17:20:41.79#ibcon#[25=USB\r\n] 2006.201.17:20:41.79#ibcon#*before write, iclass 21, count 0 2006.201.17:20:41.79#ibcon#enter sib2, iclass 21, count 0 2006.201.17:20:41.79#ibcon#flushed, iclass 21, count 0 2006.201.17:20:41.79#ibcon#about to write, iclass 21, count 0 2006.201.17:20:41.79#ibcon#wrote, iclass 21, count 0 2006.201.17:20:41.79#ibcon#about to read 3, iclass 21, count 0 2006.201.17:20:41.82#ibcon#read 3, iclass 21, count 0 2006.201.17:20:41.82#ibcon#about to read 4, iclass 21, count 0 2006.201.17:20:41.82#ibcon#read 4, iclass 21, count 0 2006.201.17:20:41.82#ibcon#about to read 5, iclass 21, count 0 2006.201.17:20:41.82#ibcon#read 5, iclass 21, count 0 2006.201.17:20:41.82#ibcon#about to read 6, iclass 21, count 0 2006.201.17:20:41.82#ibcon#read 6, iclass 21, count 0 2006.201.17:20:41.82#ibcon#end of sib2, iclass 21, count 0 2006.201.17:20:41.82#ibcon#*after write, iclass 21, count 0 2006.201.17:20:41.82#ibcon#*before return 0, iclass 21, count 0 2006.201.17:20:41.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:20:41.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:20:41.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.17:20:41.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.17:20:41.82$vck44/vblo=1,629.99 2006.201.17:20:41.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.17:20:41.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.17:20:41.82#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:41.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:20:41.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:20:41.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:20:41.82#ibcon#enter wrdev, iclass 23, count 0 2006.201.17:20:41.82#ibcon#first serial, iclass 23, count 0 2006.201.17:20:41.82#ibcon#enter sib2, iclass 23, count 0 2006.201.17:20:41.82#ibcon#flushed, iclass 23, count 0 2006.201.17:20:41.82#ibcon#about to write, iclass 23, count 0 2006.201.17:20:41.82#ibcon#wrote, iclass 23, count 0 2006.201.17:20:41.82#ibcon#about to read 3, iclass 23, count 0 2006.201.17:20:41.84#ibcon#read 3, iclass 23, count 0 2006.201.17:20:41.84#ibcon#about to read 4, iclass 23, count 0 2006.201.17:20:41.84#ibcon#read 4, iclass 23, count 0 2006.201.17:20:41.84#ibcon#about to read 5, iclass 23, count 0 2006.201.17:20:41.84#ibcon#read 5, iclass 23, count 0 2006.201.17:20:41.84#ibcon#about to read 6, iclass 23, count 0 2006.201.17:20:41.84#ibcon#read 6, iclass 23, count 0 2006.201.17:20:41.84#ibcon#end of sib2, iclass 23, count 0 2006.201.17:20:41.84#ibcon#*mode == 0, iclass 23, count 0 2006.201.17:20:41.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.17:20:41.84#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.17:20:41.84#ibcon#*before write, iclass 23, count 0 2006.201.17:20:41.84#ibcon#enter sib2, iclass 23, count 0 2006.201.17:20:41.84#ibcon#flushed, iclass 23, count 0 2006.201.17:20:41.84#ibcon#about to write, iclass 23, count 0 2006.201.17:20:41.84#ibcon#wrote, iclass 23, count 0 2006.201.17:20:41.84#ibcon#about to read 3, iclass 23, count 0 2006.201.17:20:41.89#ibcon#read 3, iclass 23, count 0 2006.201.17:20:41.89#ibcon#about to read 4, iclass 23, count 0 2006.201.17:20:41.89#ibcon#read 4, iclass 23, count 0 2006.201.17:20:41.89#ibcon#about to read 5, iclass 23, count 0 2006.201.17:20:41.89#ibcon#read 5, iclass 23, count 0 2006.201.17:20:41.89#ibcon#about to read 6, iclass 23, count 0 2006.201.17:20:41.89#ibcon#read 6, iclass 23, count 0 2006.201.17:20:41.89#ibcon#end of sib2, iclass 23, count 0 2006.201.17:20:41.89#ibcon#*after write, iclass 23, count 0 2006.201.17:20:41.89#ibcon#*before return 0, iclass 23, count 0 2006.201.17:20:41.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:20:41.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:20:41.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.17:20:41.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.17:20:41.89$vck44/vb=1,4 2006.201.17:20:41.89#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.17:20:41.89#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.17:20:41.89#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:41.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:20:41.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:20:41.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:20:41.89#ibcon#enter wrdev, iclass 25, count 2 2006.201.17:20:41.89#ibcon#first serial, iclass 25, count 2 2006.201.17:20:41.89#ibcon#enter sib2, iclass 25, count 2 2006.201.17:20:41.89#ibcon#flushed, iclass 25, count 2 2006.201.17:20:41.89#ibcon#about to write, iclass 25, count 2 2006.201.17:20:41.89#ibcon#wrote, iclass 25, count 2 2006.201.17:20:41.89#ibcon#about to read 3, iclass 25, count 2 2006.201.17:20:41.91#ibcon#read 3, iclass 25, count 2 2006.201.17:20:41.91#ibcon#about to read 4, iclass 25, count 2 2006.201.17:20:41.91#ibcon#read 4, iclass 25, count 2 2006.201.17:20:41.91#ibcon#about to read 5, iclass 25, count 2 2006.201.17:20:41.91#ibcon#read 5, iclass 25, count 2 2006.201.17:20:41.91#ibcon#about to read 6, iclass 25, count 2 2006.201.17:20:41.91#ibcon#read 6, iclass 25, count 2 2006.201.17:20:41.91#ibcon#end of sib2, iclass 25, count 2 2006.201.17:20:41.91#ibcon#*mode == 0, iclass 25, count 2 2006.201.17:20:41.91#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.17:20:41.91#ibcon#[27=AT01-04\r\n] 2006.201.17:20:41.91#ibcon#*before write, iclass 25, count 2 2006.201.17:20:41.91#ibcon#enter sib2, iclass 25, count 2 2006.201.17:20:41.91#ibcon#flushed, iclass 25, count 2 2006.201.17:20:41.91#ibcon#about to write, iclass 25, count 2 2006.201.17:20:41.91#ibcon#wrote, iclass 25, count 2 2006.201.17:20:41.91#ibcon#about to read 3, iclass 25, count 2 2006.201.17:20:41.94#ibcon#read 3, iclass 25, count 2 2006.201.17:20:41.94#ibcon#about to read 4, iclass 25, count 2 2006.201.17:20:41.94#ibcon#read 4, iclass 25, count 2 2006.201.17:20:41.94#ibcon#about to read 5, iclass 25, count 2 2006.201.17:20:41.94#ibcon#read 5, iclass 25, count 2 2006.201.17:20:41.94#ibcon#about to read 6, iclass 25, count 2 2006.201.17:20:41.94#ibcon#read 6, iclass 25, count 2 2006.201.17:20:41.94#ibcon#end of sib2, iclass 25, count 2 2006.201.17:20:41.94#ibcon#*after write, iclass 25, count 2 2006.201.17:20:41.94#ibcon#*before return 0, iclass 25, count 2 2006.201.17:20:41.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:20:41.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:20:41.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.17:20:41.94#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:41.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:20:42.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:20:42.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:20:42.06#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:20:42.06#ibcon#first serial, iclass 25, count 0 2006.201.17:20:42.06#ibcon#enter sib2, iclass 25, count 0 2006.201.17:20:42.06#ibcon#flushed, iclass 25, count 0 2006.201.17:20:42.06#ibcon#about to write, iclass 25, count 0 2006.201.17:20:42.06#ibcon#wrote, iclass 25, count 0 2006.201.17:20:42.06#ibcon#about to read 3, iclass 25, count 0 2006.201.17:20:42.08#ibcon#read 3, iclass 25, count 0 2006.201.17:20:42.08#ibcon#about to read 4, iclass 25, count 0 2006.201.17:20:42.08#ibcon#read 4, iclass 25, count 0 2006.201.17:20:42.08#ibcon#about to read 5, iclass 25, count 0 2006.201.17:20:42.08#ibcon#read 5, iclass 25, count 0 2006.201.17:20:42.08#ibcon#about to read 6, iclass 25, count 0 2006.201.17:20:42.08#ibcon#read 6, iclass 25, count 0 2006.201.17:20:42.08#ibcon#end of sib2, iclass 25, count 0 2006.201.17:20:42.08#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:20:42.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:20:42.08#ibcon#[27=USB\r\n] 2006.201.17:20:42.08#ibcon#*before write, iclass 25, count 0 2006.201.17:20:42.08#ibcon#enter sib2, iclass 25, count 0 2006.201.17:20:42.08#ibcon#flushed, iclass 25, count 0 2006.201.17:20:42.08#ibcon#about to write, iclass 25, count 0 2006.201.17:20:42.08#ibcon#wrote, iclass 25, count 0 2006.201.17:20:42.08#ibcon#about to read 3, iclass 25, count 0 2006.201.17:20:42.11#ibcon#read 3, iclass 25, count 0 2006.201.17:20:42.11#ibcon#about to read 4, iclass 25, count 0 2006.201.17:20:42.11#ibcon#read 4, iclass 25, count 0 2006.201.17:20:42.11#ibcon#about to read 5, iclass 25, count 0 2006.201.17:20:42.11#ibcon#read 5, iclass 25, count 0 2006.201.17:20:42.11#ibcon#about to read 6, iclass 25, count 0 2006.201.17:20:42.11#ibcon#read 6, iclass 25, count 0 2006.201.17:20:42.11#ibcon#end of sib2, iclass 25, count 0 2006.201.17:20:42.11#ibcon#*after write, iclass 25, count 0 2006.201.17:20:42.11#ibcon#*before return 0, iclass 25, count 0 2006.201.17:20:42.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:20:42.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:20:42.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:20:42.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:20:42.11$vck44/vblo=2,634.99 2006.201.17:20:42.11#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.17:20:42.11#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.17:20:42.11#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:42.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:42.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:42.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:42.11#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:20:42.11#ibcon#first serial, iclass 27, count 0 2006.201.17:20:42.11#ibcon#enter sib2, iclass 27, count 0 2006.201.17:20:42.11#ibcon#flushed, iclass 27, count 0 2006.201.17:20:42.11#ibcon#about to write, iclass 27, count 0 2006.201.17:20:42.11#ibcon#wrote, iclass 27, count 0 2006.201.17:20:42.11#ibcon#about to read 3, iclass 27, count 0 2006.201.17:20:42.13#ibcon#read 3, iclass 27, count 0 2006.201.17:20:42.13#ibcon#about to read 4, iclass 27, count 0 2006.201.17:20:42.13#ibcon#read 4, iclass 27, count 0 2006.201.17:20:42.13#ibcon#about to read 5, iclass 27, count 0 2006.201.17:20:42.13#ibcon#read 5, iclass 27, count 0 2006.201.17:20:42.13#ibcon#about to read 6, iclass 27, count 0 2006.201.17:20:42.13#ibcon#read 6, iclass 27, count 0 2006.201.17:20:42.13#ibcon#end of sib2, iclass 27, count 0 2006.201.17:20:42.13#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:20:42.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:20:42.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.17:20:42.13#ibcon#*before write, iclass 27, count 0 2006.201.17:20:42.13#ibcon#enter sib2, iclass 27, count 0 2006.201.17:20:42.13#ibcon#flushed, iclass 27, count 0 2006.201.17:20:42.13#ibcon#about to write, iclass 27, count 0 2006.201.17:20:42.13#ibcon#wrote, iclass 27, count 0 2006.201.17:20:42.13#ibcon#about to read 3, iclass 27, count 0 2006.201.17:20:42.17#ibcon#read 3, iclass 27, count 0 2006.201.17:20:42.17#ibcon#about to read 4, iclass 27, count 0 2006.201.17:20:42.17#ibcon#read 4, iclass 27, count 0 2006.201.17:20:42.17#ibcon#about to read 5, iclass 27, count 0 2006.201.17:20:42.17#ibcon#read 5, iclass 27, count 0 2006.201.17:20:42.17#ibcon#about to read 6, iclass 27, count 0 2006.201.17:20:42.17#ibcon#read 6, iclass 27, count 0 2006.201.17:20:42.17#ibcon#end of sib2, iclass 27, count 0 2006.201.17:20:42.17#ibcon#*after write, iclass 27, count 0 2006.201.17:20:42.17#ibcon#*before return 0, iclass 27, count 0 2006.201.17:20:42.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:42.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:20:42.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:20:42.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:20:42.17$vck44/vb=2,5 2006.201.17:20:42.17#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.17:20:42.17#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.17:20:42.17#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:42.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:42.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:42.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:42.23#ibcon#enter wrdev, iclass 29, count 2 2006.201.17:20:42.23#ibcon#first serial, iclass 29, count 2 2006.201.17:20:42.23#ibcon#enter sib2, iclass 29, count 2 2006.201.17:20:42.23#ibcon#flushed, iclass 29, count 2 2006.201.17:20:42.23#ibcon#about to write, iclass 29, count 2 2006.201.17:20:42.23#ibcon#wrote, iclass 29, count 2 2006.201.17:20:42.23#ibcon#about to read 3, iclass 29, count 2 2006.201.17:20:42.25#ibcon#read 3, iclass 29, count 2 2006.201.17:20:42.25#ibcon#about to read 4, iclass 29, count 2 2006.201.17:20:42.25#ibcon#read 4, iclass 29, count 2 2006.201.17:20:42.25#ibcon#about to read 5, iclass 29, count 2 2006.201.17:20:42.25#ibcon#read 5, iclass 29, count 2 2006.201.17:20:42.25#ibcon#about to read 6, iclass 29, count 2 2006.201.17:20:42.25#ibcon#read 6, iclass 29, count 2 2006.201.17:20:42.25#ibcon#end of sib2, iclass 29, count 2 2006.201.17:20:42.25#ibcon#*mode == 0, iclass 29, count 2 2006.201.17:20:42.25#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.17:20:42.25#ibcon#[27=AT02-05\r\n] 2006.201.17:20:42.25#ibcon#*before write, iclass 29, count 2 2006.201.17:20:42.25#ibcon#enter sib2, iclass 29, count 2 2006.201.17:20:42.25#ibcon#flushed, iclass 29, count 2 2006.201.17:20:42.25#ibcon#about to write, iclass 29, count 2 2006.201.17:20:42.25#ibcon#wrote, iclass 29, count 2 2006.201.17:20:42.25#ibcon#about to read 3, iclass 29, count 2 2006.201.17:20:42.28#ibcon#read 3, iclass 29, count 2 2006.201.17:20:42.28#ibcon#about to read 4, iclass 29, count 2 2006.201.17:20:42.28#ibcon#read 4, iclass 29, count 2 2006.201.17:20:42.28#ibcon#about to read 5, iclass 29, count 2 2006.201.17:20:42.28#ibcon#read 5, iclass 29, count 2 2006.201.17:20:42.28#ibcon#about to read 6, iclass 29, count 2 2006.201.17:20:42.28#ibcon#read 6, iclass 29, count 2 2006.201.17:20:42.28#ibcon#end of sib2, iclass 29, count 2 2006.201.17:20:42.28#ibcon#*after write, iclass 29, count 2 2006.201.17:20:42.28#ibcon#*before return 0, iclass 29, count 2 2006.201.17:20:42.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:42.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:20:42.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.17:20:42.28#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:42.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:42.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:42.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:42.40#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:20:42.40#ibcon#first serial, iclass 29, count 0 2006.201.17:20:42.40#ibcon#enter sib2, iclass 29, count 0 2006.201.17:20:42.40#ibcon#flushed, iclass 29, count 0 2006.201.17:20:42.40#ibcon#about to write, iclass 29, count 0 2006.201.17:20:42.40#ibcon#wrote, iclass 29, count 0 2006.201.17:20:42.40#ibcon#about to read 3, iclass 29, count 0 2006.201.17:20:42.42#ibcon#read 3, iclass 29, count 0 2006.201.17:20:42.42#ibcon#about to read 4, iclass 29, count 0 2006.201.17:20:42.42#ibcon#read 4, iclass 29, count 0 2006.201.17:20:42.42#ibcon#about to read 5, iclass 29, count 0 2006.201.17:20:42.42#ibcon#read 5, iclass 29, count 0 2006.201.17:20:42.42#ibcon#about to read 6, iclass 29, count 0 2006.201.17:20:42.42#ibcon#read 6, iclass 29, count 0 2006.201.17:20:42.42#ibcon#end of sib2, iclass 29, count 0 2006.201.17:20:42.42#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:20:42.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:20:42.42#ibcon#[27=USB\r\n] 2006.201.17:20:42.42#ibcon#*before write, iclass 29, count 0 2006.201.17:20:42.42#ibcon#enter sib2, iclass 29, count 0 2006.201.17:20:42.42#ibcon#flushed, iclass 29, count 0 2006.201.17:20:42.42#ibcon#about to write, iclass 29, count 0 2006.201.17:20:42.42#ibcon#wrote, iclass 29, count 0 2006.201.17:20:42.42#ibcon#about to read 3, iclass 29, count 0 2006.201.17:20:42.45#ibcon#read 3, iclass 29, count 0 2006.201.17:20:42.45#ibcon#about to read 4, iclass 29, count 0 2006.201.17:20:42.45#ibcon#read 4, iclass 29, count 0 2006.201.17:20:42.45#ibcon#about to read 5, iclass 29, count 0 2006.201.17:20:42.45#ibcon#read 5, iclass 29, count 0 2006.201.17:20:42.45#ibcon#about to read 6, iclass 29, count 0 2006.201.17:20:42.45#ibcon#read 6, iclass 29, count 0 2006.201.17:20:42.45#ibcon#end of sib2, iclass 29, count 0 2006.201.17:20:42.45#ibcon#*after write, iclass 29, count 0 2006.201.17:20:42.45#ibcon#*before return 0, iclass 29, count 0 2006.201.17:20:42.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:42.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:20:42.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:20:42.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:20:42.45$vck44/vblo=3,649.99 2006.201.17:20:42.45#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.17:20:42.45#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.17:20:42.45#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:42.45#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:42.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:42.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:42.45#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:20:42.45#ibcon#first serial, iclass 31, count 0 2006.201.17:20:42.45#ibcon#enter sib2, iclass 31, count 0 2006.201.17:20:42.45#ibcon#flushed, iclass 31, count 0 2006.201.17:20:42.45#ibcon#about to write, iclass 31, count 0 2006.201.17:20:42.45#ibcon#wrote, iclass 31, count 0 2006.201.17:20:42.45#ibcon#about to read 3, iclass 31, count 0 2006.201.17:20:42.47#ibcon#read 3, iclass 31, count 0 2006.201.17:20:42.47#ibcon#about to read 4, iclass 31, count 0 2006.201.17:20:42.47#ibcon#read 4, iclass 31, count 0 2006.201.17:20:42.47#ibcon#about to read 5, iclass 31, count 0 2006.201.17:20:42.47#ibcon#read 5, iclass 31, count 0 2006.201.17:20:42.47#ibcon#about to read 6, iclass 31, count 0 2006.201.17:20:42.47#ibcon#read 6, iclass 31, count 0 2006.201.17:20:42.47#ibcon#end of sib2, iclass 31, count 0 2006.201.17:20:42.47#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:20:42.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:20:42.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.17:20:42.47#ibcon#*before write, iclass 31, count 0 2006.201.17:20:42.47#ibcon#enter sib2, iclass 31, count 0 2006.201.17:20:42.47#ibcon#flushed, iclass 31, count 0 2006.201.17:20:42.47#ibcon#about to write, iclass 31, count 0 2006.201.17:20:42.47#ibcon#wrote, iclass 31, count 0 2006.201.17:20:42.47#ibcon#about to read 3, iclass 31, count 0 2006.201.17:20:42.51#ibcon#read 3, iclass 31, count 0 2006.201.17:20:42.51#ibcon#about to read 4, iclass 31, count 0 2006.201.17:20:42.51#ibcon#read 4, iclass 31, count 0 2006.201.17:20:42.51#ibcon#about to read 5, iclass 31, count 0 2006.201.17:20:42.51#ibcon#read 5, iclass 31, count 0 2006.201.17:20:42.51#ibcon#about to read 6, iclass 31, count 0 2006.201.17:20:42.51#ibcon#read 6, iclass 31, count 0 2006.201.17:20:42.51#ibcon#end of sib2, iclass 31, count 0 2006.201.17:20:42.51#ibcon#*after write, iclass 31, count 0 2006.201.17:20:42.51#ibcon#*before return 0, iclass 31, count 0 2006.201.17:20:42.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:42.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:20:42.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:20:42.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:20:42.51$vck44/vb=3,4 2006.201.17:20:42.51#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.17:20:42.51#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.17:20:42.51#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:42.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:42.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:42.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:42.57#ibcon#enter wrdev, iclass 33, count 2 2006.201.17:20:42.57#ibcon#first serial, iclass 33, count 2 2006.201.17:20:42.57#ibcon#enter sib2, iclass 33, count 2 2006.201.17:20:42.57#ibcon#flushed, iclass 33, count 2 2006.201.17:20:42.57#ibcon#about to write, iclass 33, count 2 2006.201.17:20:42.57#ibcon#wrote, iclass 33, count 2 2006.201.17:20:42.57#ibcon#about to read 3, iclass 33, count 2 2006.201.17:20:42.59#ibcon#read 3, iclass 33, count 2 2006.201.17:20:42.59#ibcon#about to read 4, iclass 33, count 2 2006.201.17:20:42.59#ibcon#read 4, iclass 33, count 2 2006.201.17:20:42.59#ibcon#about to read 5, iclass 33, count 2 2006.201.17:20:42.59#ibcon#read 5, iclass 33, count 2 2006.201.17:20:42.59#ibcon#about to read 6, iclass 33, count 2 2006.201.17:20:42.59#ibcon#read 6, iclass 33, count 2 2006.201.17:20:42.59#ibcon#end of sib2, iclass 33, count 2 2006.201.17:20:42.59#ibcon#*mode == 0, iclass 33, count 2 2006.201.17:20:42.59#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.17:20:42.59#ibcon#[27=AT03-04\r\n] 2006.201.17:20:42.59#ibcon#*before write, iclass 33, count 2 2006.201.17:20:42.59#ibcon#enter sib2, iclass 33, count 2 2006.201.17:20:42.59#ibcon#flushed, iclass 33, count 2 2006.201.17:20:42.59#ibcon#about to write, iclass 33, count 2 2006.201.17:20:42.59#ibcon#wrote, iclass 33, count 2 2006.201.17:20:42.59#ibcon#about to read 3, iclass 33, count 2 2006.201.17:20:42.62#ibcon#read 3, iclass 33, count 2 2006.201.17:20:42.62#ibcon#about to read 4, iclass 33, count 2 2006.201.17:20:42.62#ibcon#read 4, iclass 33, count 2 2006.201.17:20:42.62#ibcon#about to read 5, iclass 33, count 2 2006.201.17:20:42.62#ibcon#read 5, iclass 33, count 2 2006.201.17:20:42.62#ibcon#about to read 6, iclass 33, count 2 2006.201.17:20:42.62#ibcon#read 6, iclass 33, count 2 2006.201.17:20:42.62#ibcon#end of sib2, iclass 33, count 2 2006.201.17:20:42.62#ibcon#*after write, iclass 33, count 2 2006.201.17:20:42.62#ibcon#*before return 0, iclass 33, count 2 2006.201.17:20:42.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:42.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:20:42.62#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.17:20:42.62#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:42.62#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:42.74#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:42.74#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:42.74#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:20:42.74#ibcon#first serial, iclass 33, count 0 2006.201.17:20:42.74#ibcon#enter sib2, iclass 33, count 0 2006.201.17:20:42.74#ibcon#flushed, iclass 33, count 0 2006.201.17:20:42.74#ibcon#about to write, iclass 33, count 0 2006.201.17:20:42.74#ibcon#wrote, iclass 33, count 0 2006.201.17:20:42.74#ibcon#about to read 3, iclass 33, count 0 2006.201.17:20:42.76#ibcon#read 3, iclass 33, count 0 2006.201.17:20:42.76#ibcon#about to read 4, iclass 33, count 0 2006.201.17:20:42.76#ibcon#read 4, iclass 33, count 0 2006.201.17:20:42.76#ibcon#about to read 5, iclass 33, count 0 2006.201.17:20:42.76#ibcon#read 5, iclass 33, count 0 2006.201.17:20:42.76#ibcon#about to read 6, iclass 33, count 0 2006.201.17:20:42.76#ibcon#read 6, iclass 33, count 0 2006.201.17:20:42.76#ibcon#end of sib2, iclass 33, count 0 2006.201.17:20:42.76#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:20:42.76#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:20:42.76#ibcon#[27=USB\r\n] 2006.201.17:20:42.76#ibcon#*before write, iclass 33, count 0 2006.201.17:20:42.76#ibcon#enter sib2, iclass 33, count 0 2006.201.17:20:42.76#ibcon#flushed, iclass 33, count 0 2006.201.17:20:42.76#ibcon#about to write, iclass 33, count 0 2006.201.17:20:42.76#ibcon#wrote, iclass 33, count 0 2006.201.17:20:42.76#ibcon#about to read 3, iclass 33, count 0 2006.201.17:20:42.79#ibcon#read 3, iclass 33, count 0 2006.201.17:20:42.79#ibcon#about to read 4, iclass 33, count 0 2006.201.17:20:42.79#ibcon#read 4, iclass 33, count 0 2006.201.17:20:42.79#ibcon#about to read 5, iclass 33, count 0 2006.201.17:20:42.79#ibcon#read 5, iclass 33, count 0 2006.201.17:20:42.79#ibcon#about to read 6, iclass 33, count 0 2006.201.17:20:42.79#ibcon#read 6, iclass 33, count 0 2006.201.17:20:42.79#ibcon#end of sib2, iclass 33, count 0 2006.201.17:20:42.79#ibcon#*after write, iclass 33, count 0 2006.201.17:20:42.79#ibcon#*before return 0, iclass 33, count 0 2006.201.17:20:42.79#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:42.79#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:20:42.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:20:42.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:20:42.79$vck44/vblo=4,679.99 2006.201.17:20:42.79#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.17:20:42.79#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.17:20:42.79#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:42.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:42.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:42.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:42.79#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:20:42.79#ibcon#first serial, iclass 35, count 0 2006.201.17:20:42.79#ibcon#enter sib2, iclass 35, count 0 2006.201.17:20:42.79#ibcon#flushed, iclass 35, count 0 2006.201.17:20:42.79#ibcon#about to write, iclass 35, count 0 2006.201.17:20:42.79#ibcon#wrote, iclass 35, count 0 2006.201.17:20:42.79#ibcon#about to read 3, iclass 35, count 0 2006.201.17:20:42.81#ibcon#read 3, iclass 35, count 0 2006.201.17:20:42.81#ibcon#about to read 4, iclass 35, count 0 2006.201.17:20:42.81#ibcon#read 4, iclass 35, count 0 2006.201.17:20:42.81#ibcon#about to read 5, iclass 35, count 0 2006.201.17:20:42.81#ibcon#read 5, iclass 35, count 0 2006.201.17:20:42.81#ibcon#about to read 6, iclass 35, count 0 2006.201.17:20:42.81#ibcon#read 6, iclass 35, count 0 2006.201.17:20:42.81#ibcon#end of sib2, iclass 35, count 0 2006.201.17:20:42.81#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:20:42.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:20:42.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.17:20:42.81#ibcon#*before write, iclass 35, count 0 2006.201.17:20:42.81#ibcon#enter sib2, iclass 35, count 0 2006.201.17:20:42.81#ibcon#flushed, iclass 35, count 0 2006.201.17:20:42.81#ibcon#about to write, iclass 35, count 0 2006.201.17:20:42.81#ibcon#wrote, iclass 35, count 0 2006.201.17:20:42.81#ibcon#about to read 3, iclass 35, count 0 2006.201.17:20:42.86#ibcon#read 3, iclass 35, count 0 2006.201.17:20:42.86#ibcon#about to read 4, iclass 35, count 0 2006.201.17:20:42.86#ibcon#read 4, iclass 35, count 0 2006.201.17:20:42.86#ibcon#about to read 5, iclass 35, count 0 2006.201.17:20:42.86#ibcon#read 5, iclass 35, count 0 2006.201.17:20:42.86#ibcon#about to read 6, iclass 35, count 0 2006.201.17:20:42.86#ibcon#read 6, iclass 35, count 0 2006.201.17:20:42.86#ibcon#end of sib2, iclass 35, count 0 2006.201.17:20:42.86#ibcon#*after write, iclass 35, count 0 2006.201.17:20:42.86#ibcon#*before return 0, iclass 35, count 0 2006.201.17:20:42.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:42.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:20:42.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:20:42.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:20:42.86$vck44/vb=4,5 2006.201.17:20:42.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.17:20:42.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.17:20:42.86#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:42.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:42.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:42.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:42.91#ibcon#enter wrdev, iclass 37, count 2 2006.201.17:20:42.91#ibcon#first serial, iclass 37, count 2 2006.201.17:20:42.91#ibcon#enter sib2, iclass 37, count 2 2006.201.17:20:42.91#ibcon#flushed, iclass 37, count 2 2006.201.17:20:42.91#ibcon#about to write, iclass 37, count 2 2006.201.17:20:42.91#ibcon#wrote, iclass 37, count 2 2006.201.17:20:42.91#ibcon#about to read 3, iclass 37, count 2 2006.201.17:20:42.93#ibcon#read 3, iclass 37, count 2 2006.201.17:20:42.93#ibcon#about to read 4, iclass 37, count 2 2006.201.17:20:42.93#ibcon#read 4, iclass 37, count 2 2006.201.17:20:42.93#ibcon#about to read 5, iclass 37, count 2 2006.201.17:20:42.93#ibcon#read 5, iclass 37, count 2 2006.201.17:20:42.93#ibcon#about to read 6, iclass 37, count 2 2006.201.17:20:42.93#ibcon#read 6, iclass 37, count 2 2006.201.17:20:42.93#ibcon#end of sib2, iclass 37, count 2 2006.201.17:20:42.93#ibcon#*mode == 0, iclass 37, count 2 2006.201.17:20:42.93#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.17:20:42.93#ibcon#[27=AT04-05\r\n] 2006.201.17:20:42.93#ibcon#*before write, iclass 37, count 2 2006.201.17:20:42.93#ibcon#enter sib2, iclass 37, count 2 2006.201.17:20:42.93#ibcon#flushed, iclass 37, count 2 2006.201.17:20:42.93#ibcon#about to write, iclass 37, count 2 2006.201.17:20:42.93#ibcon#wrote, iclass 37, count 2 2006.201.17:20:42.93#ibcon#about to read 3, iclass 37, count 2 2006.201.17:20:42.96#ibcon#read 3, iclass 37, count 2 2006.201.17:20:42.96#ibcon#about to read 4, iclass 37, count 2 2006.201.17:20:42.96#ibcon#read 4, iclass 37, count 2 2006.201.17:20:42.96#ibcon#about to read 5, iclass 37, count 2 2006.201.17:20:42.96#ibcon#read 5, iclass 37, count 2 2006.201.17:20:42.96#ibcon#about to read 6, iclass 37, count 2 2006.201.17:20:42.96#ibcon#read 6, iclass 37, count 2 2006.201.17:20:42.96#ibcon#end of sib2, iclass 37, count 2 2006.201.17:20:42.96#ibcon#*after write, iclass 37, count 2 2006.201.17:20:42.96#ibcon#*before return 0, iclass 37, count 2 2006.201.17:20:42.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:42.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:20:42.96#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.17:20:42.96#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:42.96#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:43.08#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:43.08#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:43.08#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:20:43.08#ibcon#first serial, iclass 37, count 0 2006.201.17:20:43.08#ibcon#enter sib2, iclass 37, count 0 2006.201.17:20:43.08#ibcon#flushed, iclass 37, count 0 2006.201.17:20:43.08#ibcon#about to write, iclass 37, count 0 2006.201.17:20:43.08#ibcon#wrote, iclass 37, count 0 2006.201.17:20:43.08#ibcon#about to read 3, iclass 37, count 0 2006.201.17:20:43.10#ibcon#read 3, iclass 37, count 0 2006.201.17:20:43.10#ibcon#about to read 4, iclass 37, count 0 2006.201.17:20:43.10#ibcon#read 4, iclass 37, count 0 2006.201.17:20:43.10#ibcon#about to read 5, iclass 37, count 0 2006.201.17:20:43.10#ibcon#read 5, iclass 37, count 0 2006.201.17:20:43.10#ibcon#about to read 6, iclass 37, count 0 2006.201.17:20:43.10#ibcon#read 6, iclass 37, count 0 2006.201.17:20:43.10#ibcon#end of sib2, iclass 37, count 0 2006.201.17:20:43.10#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:20:43.10#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:20:43.10#ibcon#[27=USB\r\n] 2006.201.17:20:43.10#ibcon#*before write, iclass 37, count 0 2006.201.17:20:43.10#ibcon#enter sib2, iclass 37, count 0 2006.201.17:20:43.10#ibcon#flushed, iclass 37, count 0 2006.201.17:20:43.10#ibcon#about to write, iclass 37, count 0 2006.201.17:20:43.10#ibcon#wrote, iclass 37, count 0 2006.201.17:20:43.10#ibcon#about to read 3, iclass 37, count 0 2006.201.17:20:43.13#ibcon#read 3, iclass 37, count 0 2006.201.17:20:43.13#ibcon#about to read 4, iclass 37, count 0 2006.201.17:20:43.13#ibcon#read 4, iclass 37, count 0 2006.201.17:20:43.13#ibcon#about to read 5, iclass 37, count 0 2006.201.17:20:43.13#ibcon#read 5, iclass 37, count 0 2006.201.17:20:43.13#ibcon#about to read 6, iclass 37, count 0 2006.201.17:20:43.13#ibcon#read 6, iclass 37, count 0 2006.201.17:20:43.13#ibcon#end of sib2, iclass 37, count 0 2006.201.17:20:43.13#ibcon#*after write, iclass 37, count 0 2006.201.17:20:43.13#ibcon#*before return 0, iclass 37, count 0 2006.201.17:20:43.13#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:43.13#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:20:43.13#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:20:43.13#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:20:43.13$vck44/vblo=5,709.99 2006.201.17:20:43.13#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.17:20:43.13#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.17:20:43.13#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:43.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:43.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:43.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:43.13#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:20:43.13#ibcon#first serial, iclass 39, count 0 2006.201.17:20:43.13#ibcon#enter sib2, iclass 39, count 0 2006.201.17:20:43.13#ibcon#flushed, iclass 39, count 0 2006.201.17:20:43.13#ibcon#about to write, iclass 39, count 0 2006.201.17:20:43.13#ibcon#wrote, iclass 39, count 0 2006.201.17:20:43.13#ibcon#about to read 3, iclass 39, count 0 2006.201.17:20:43.15#ibcon#read 3, iclass 39, count 0 2006.201.17:20:43.15#ibcon#about to read 4, iclass 39, count 0 2006.201.17:20:43.15#ibcon#read 4, iclass 39, count 0 2006.201.17:20:43.15#ibcon#about to read 5, iclass 39, count 0 2006.201.17:20:43.15#ibcon#read 5, iclass 39, count 0 2006.201.17:20:43.15#ibcon#about to read 6, iclass 39, count 0 2006.201.17:20:43.15#ibcon#read 6, iclass 39, count 0 2006.201.17:20:43.15#ibcon#end of sib2, iclass 39, count 0 2006.201.17:20:43.15#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:20:43.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:20:43.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.17:20:43.15#ibcon#*before write, iclass 39, count 0 2006.201.17:20:43.15#ibcon#enter sib2, iclass 39, count 0 2006.201.17:20:43.15#ibcon#flushed, iclass 39, count 0 2006.201.17:20:43.15#ibcon#about to write, iclass 39, count 0 2006.201.17:20:43.15#ibcon#wrote, iclass 39, count 0 2006.201.17:20:43.15#ibcon#about to read 3, iclass 39, count 0 2006.201.17:20:43.19#ibcon#read 3, iclass 39, count 0 2006.201.17:20:43.19#ibcon#about to read 4, iclass 39, count 0 2006.201.17:20:43.19#ibcon#read 4, iclass 39, count 0 2006.201.17:20:43.19#ibcon#about to read 5, iclass 39, count 0 2006.201.17:20:43.19#ibcon#read 5, iclass 39, count 0 2006.201.17:20:43.19#ibcon#about to read 6, iclass 39, count 0 2006.201.17:20:43.19#ibcon#read 6, iclass 39, count 0 2006.201.17:20:43.19#ibcon#end of sib2, iclass 39, count 0 2006.201.17:20:43.19#ibcon#*after write, iclass 39, count 0 2006.201.17:20:43.19#ibcon#*before return 0, iclass 39, count 0 2006.201.17:20:43.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:43.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:20:43.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:20:43.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:20:43.19$vck44/vb=5,4 2006.201.17:20:43.19#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.17:20:43.19#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.17:20:43.19#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:43.19#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:43.25#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:43.25#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:43.25#ibcon#enter wrdev, iclass 2, count 2 2006.201.17:20:43.25#ibcon#first serial, iclass 2, count 2 2006.201.17:20:43.25#ibcon#enter sib2, iclass 2, count 2 2006.201.17:20:43.25#ibcon#flushed, iclass 2, count 2 2006.201.17:20:43.25#ibcon#about to write, iclass 2, count 2 2006.201.17:20:43.25#ibcon#wrote, iclass 2, count 2 2006.201.17:20:43.25#ibcon#about to read 3, iclass 2, count 2 2006.201.17:20:43.27#ibcon#read 3, iclass 2, count 2 2006.201.17:20:43.27#ibcon#about to read 4, iclass 2, count 2 2006.201.17:20:43.27#ibcon#read 4, iclass 2, count 2 2006.201.17:20:43.27#ibcon#about to read 5, iclass 2, count 2 2006.201.17:20:43.27#ibcon#read 5, iclass 2, count 2 2006.201.17:20:43.27#ibcon#about to read 6, iclass 2, count 2 2006.201.17:20:43.27#ibcon#read 6, iclass 2, count 2 2006.201.17:20:43.27#ibcon#end of sib2, iclass 2, count 2 2006.201.17:20:43.27#ibcon#*mode == 0, iclass 2, count 2 2006.201.17:20:43.27#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.17:20:43.27#ibcon#[27=AT05-04\r\n] 2006.201.17:20:43.27#ibcon#*before write, iclass 2, count 2 2006.201.17:20:43.27#ibcon#enter sib2, iclass 2, count 2 2006.201.17:20:43.27#ibcon#flushed, iclass 2, count 2 2006.201.17:20:43.27#ibcon#about to write, iclass 2, count 2 2006.201.17:20:43.27#ibcon#wrote, iclass 2, count 2 2006.201.17:20:43.27#ibcon#about to read 3, iclass 2, count 2 2006.201.17:20:43.30#ibcon#read 3, iclass 2, count 2 2006.201.17:20:43.30#ibcon#about to read 4, iclass 2, count 2 2006.201.17:20:43.30#ibcon#read 4, iclass 2, count 2 2006.201.17:20:43.30#ibcon#about to read 5, iclass 2, count 2 2006.201.17:20:43.30#ibcon#read 5, iclass 2, count 2 2006.201.17:20:43.30#ibcon#about to read 6, iclass 2, count 2 2006.201.17:20:43.30#ibcon#read 6, iclass 2, count 2 2006.201.17:20:43.30#ibcon#end of sib2, iclass 2, count 2 2006.201.17:20:43.30#ibcon#*after write, iclass 2, count 2 2006.201.17:20:43.30#ibcon#*before return 0, iclass 2, count 2 2006.201.17:20:43.30#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:43.30#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:20:43.30#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.17:20:43.30#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:43.30#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:43.42#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:43.42#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:43.42#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:20:43.42#ibcon#first serial, iclass 2, count 0 2006.201.17:20:43.42#ibcon#enter sib2, iclass 2, count 0 2006.201.17:20:43.42#ibcon#flushed, iclass 2, count 0 2006.201.17:20:43.42#ibcon#about to write, iclass 2, count 0 2006.201.17:20:43.42#ibcon#wrote, iclass 2, count 0 2006.201.17:20:43.42#ibcon#about to read 3, iclass 2, count 0 2006.201.17:20:43.44#ibcon#read 3, iclass 2, count 0 2006.201.17:20:43.44#ibcon#about to read 4, iclass 2, count 0 2006.201.17:20:43.44#ibcon#read 4, iclass 2, count 0 2006.201.17:20:43.44#ibcon#about to read 5, iclass 2, count 0 2006.201.17:20:43.44#ibcon#read 5, iclass 2, count 0 2006.201.17:20:43.44#ibcon#about to read 6, iclass 2, count 0 2006.201.17:20:43.44#ibcon#read 6, iclass 2, count 0 2006.201.17:20:43.44#ibcon#end of sib2, iclass 2, count 0 2006.201.17:20:43.44#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:20:43.44#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:20:43.44#ibcon#[27=USB\r\n] 2006.201.17:20:43.44#ibcon#*before write, iclass 2, count 0 2006.201.17:20:43.44#ibcon#enter sib2, iclass 2, count 0 2006.201.17:20:43.44#ibcon#flushed, iclass 2, count 0 2006.201.17:20:43.44#ibcon#about to write, iclass 2, count 0 2006.201.17:20:43.44#ibcon#wrote, iclass 2, count 0 2006.201.17:20:43.44#ibcon#about to read 3, iclass 2, count 0 2006.201.17:20:43.47#ibcon#read 3, iclass 2, count 0 2006.201.17:20:43.47#ibcon#about to read 4, iclass 2, count 0 2006.201.17:20:43.47#ibcon#read 4, iclass 2, count 0 2006.201.17:20:43.47#ibcon#about to read 5, iclass 2, count 0 2006.201.17:20:43.47#ibcon#read 5, iclass 2, count 0 2006.201.17:20:43.47#ibcon#about to read 6, iclass 2, count 0 2006.201.17:20:43.47#ibcon#read 6, iclass 2, count 0 2006.201.17:20:43.47#ibcon#end of sib2, iclass 2, count 0 2006.201.17:20:43.47#ibcon#*after write, iclass 2, count 0 2006.201.17:20:43.47#ibcon#*before return 0, iclass 2, count 0 2006.201.17:20:43.47#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:43.47#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:20:43.47#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:20:43.47#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:20:43.47$vck44/vblo=6,719.99 2006.201.17:20:43.47#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.17:20:43.47#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.17:20:43.47#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:43.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:43.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:43.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:43.47#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:20:43.47#ibcon#first serial, iclass 5, count 0 2006.201.17:20:43.47#ibcon#enter sib2, iclass 5, count 0 2006.201.17:20:43.47#ibcon#flushed, iclass 5, count 0 2006.201.17:20:43.47#ibcon#about to write, iclass 5, count 0 2006.201.17:20:43.47#ibcon#wrote, iclass 5, count 0 2006.201.17:20:43.47#ibcon#about to read 3, iclass 5, count 0 2006.201.17:20:43.49#ibcon#read 3, iclass 5, count 0 2006.201.17:20:43.49#ibcon#about to read 4, iclass 5, count 0 2006.201.17:20:43.49#ibcon#read 4, iclass 5, count 0 2006.201.17:20:43.49#ibcon#about to read 5, iclass 5, count 0 2006.201.17:20:43.49#ibcon#read 5, iclass 5, count 0 2006.201.17:20:43.49#ibcon#about to read 6, iclass 5, count 0 2006.201.17:20:43.49#ibcon#read 6, iclass 5, count 0 2006.201.17:20:43.49#ibcon#end of sib2, iclass 5, count 0 2006.201.17:20:43.49#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:20:43.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:20:43.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.17:20:43.49#ibcon#*before write, iclass 5, count 0 2006.201.17:20:43.49#ibcon#enter sib2, iclass 5, count 0 2006.201.17:20:43.49#ibcon#flushed, iclass 5, count 0 2006.201.17:20:43.49#ibcon#about to write, iclass 5, count 0 2006.201.17:20:43.49#ibcon#wrote, iclass 5, count 0 2006.201.17:20:43.49#ibcon#about to read 3, iclass 5, count 0 2006.201.17:20:43.53#ibcon#read 3, iclass 5, count 0 2006.201.17:20:43.53#ibcon#about to read 4, iclass 5, count 0 2006.201.17:20:43.53#ibcon#read 4, iclass 5, count 0 2006.201.17:20:43.53#ibcon#about to read 5, iclass 5, count 0 2006.201.17:20:43.53#ibcon#read 5, iclass 5, count 0 2006.201.17:20:43.53#ibcon#about to read 6, iclass 5, count 0 2006.201.17:20:43.53#ibcon#read 6, iclass 5, count 0 2006.201.17:20:43.53#ibcon#end of sib2, iclass 5, count 0 2006.201.17:20:43.53#ibcon#*after write, iclass 5, count 0 2006.201.17:20:43.53#ibcon#*before return 0, iclass 5, count 0 2006.201.17:20:43.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:43.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:20:43.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:20:43.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:20:43.53$vck44/vb=6,4 2006.201.17:20:43.53#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.17:20:43.53#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.17:20:43.53#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:43.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:43.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:43.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:43.59#ibcon#enter wrdev, iclass 7, count 2 2006.201.17:20:43.59#ibcon#first serial, iclass 7, count 2 2006.201.17:20:43.59#ibcon#enter sib2, iclass 7, count 2 2006.201.17:20:43.59#ibcon#flushed, iclass 7, count 2 2006.201.17:20:43.59#ibcon#about to write, iclass 7, count 2 2006.201.17:20:43.59#ibcon#wrote, iclass 7, count 2 2006.201.17:20:43.59#ibcon#about to read 3, iclass 7, count 2 2006.201.17:20:43.61#ibcon#read 3, iclass 7, count 2 2006.201.17:20:43.61#ibcon#about to read 4, iclass 7, count 2 2006.201.17:20:43.61#ibcon#read 4, iclass 7, count 2 2006.201.17:20:43.61#ibcon#about to read 5, iclass 7, count 2 2006.201.17:20:43.61#ibcon#read 5, iclass 7, count 2 2006.201.17:20:43.61#ibcon#about to read 6, iclass 7, count 2 2006.201.17:20:43.61#ibcon#read 6, iclass 7, count 2 2006.201.17:20:43.61#ibcon#end of sib2, iclass 7, count 2 2006.201.17:20:43.61#ibcon#*mode == 0, iclass 7, count 2 2006.201.17:20:43.61#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.17:20:43.61#ibcon#[27=AT06-04\r\n] 2006.201.17:20:43.61#ibcon#*before write, iclass 7, count 2 2006.201.17:20:43.61#ibcon#enter sib2, iclass 7, count 2 2006.201.17:20:43.61#ibcon#flushed, iclass 7, count 2 2006.201.17:20:43.61#ibcon#about to write, iclass 7, count 2 2006.201.17:20:43.61#ibcon#wrote, iclass 7, count 2 2006.201.17:20:43.61#ibcon#about to read 3, iclass 7, count 2 2006.201.17:20:43.64#ibcon#read 3, iclass 7, count 2 2006.201.17:20:43.64#ibcon#about to read 4, iclass 7, count 2 2006.201.17:20:43.64#ibcon#read 4, iclass 7, count 2 2006.201.17:20:43.64#ibcon#about to read 5, iclass 7, count 2 2006.201.17:20:43.64#ibcon#read 5, iclass 7, count 2 2006.201.17:20:43.64#ibcon#about to read 6, iclass 7, count 2 2006.201.17:20:43.64#ibcon#read 6, iclass 7, count 2 2006.201.17:20:43.64#ibcon#end of sib2, iclass 7, count 2 2006.201.17:20:43.64#ibcon#*after write, iclass 7, count 2 2006.201.17:20:43.64#ibcon#*before return 0, iclass 7, count 2 2006.201.17:20:43.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:43.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:20:43.64#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.17:20:43.64#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:43.64#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:43.76#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:43.76#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:43.76#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:20:43.76#ibcon#first serial, iclass 7, count 0 2006.201.17:20:43.76#ibcon#enter sib2, iclass 7, count 0 2006.201.17:20:43.76#ibcon#flushed, iclass 7, count 0 2006.201.17:20:43.76#ibcon#about to write, iclass 7, count 0 2006.201.17:20:43.76#ibcon#wrote, iclass 7, count 0 2006.201.17:20:43.76#ibcon#about to read 3, iclass 7, count 0 2006.201.17:20:43.78#ibcon#read 3, iclass 7, count 0 2006.201.17:20:43.78#ibcon#about to read 4, iclass 7, count 0 2006.201.17:20:43.78#ibcon#read 4, iclass 7, count 0 2006.201.17:20:43.78#ibcon#about to read 5, iclass 7, count 0 2006.201.17:20:43.78#ibcon#read 5, iclass 7, count 0 2006.201.17:20:43.78#ibcon#about to read 6, iclass 7, count 0 2006.201.17:20:43.78#ibcon#read 6, iclass 7, count 0 2006.201.17:20:43.78#ibcon#end of sib2, iclass 7, count 0 2006.201.17:20:43.78#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:20:43.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:20:43.78#ibcon#[27=USB\r\n] 2006.201.17:20:43.78#ibcon#*before write, iclass 7, count 0 2006.201.17:20:43.78#ibcon#enter sib2, iclass 7, count 0 2006.201.17:20:43.78#ibcon#flushed, iclass 7, count 0 2006.201.17:20:43.78#ibcon#about to write, iclass 7, count 0 2006.201.17:20:43.78#ibcon#wrote, iclass 7, count 0 2006.201.17:20:43.78#ibcon#about to read 3, iclass 7, count 0 2006.201.17:20:43.81#ibcon#read 3, iclass 7, count 0 2006.201.17:20:43.81#ibcon#about to read 4, iclass 7, count 0 2006.201.17:20:43.81#ibcon#read 4, iclass 7, count 0 2006.201.17:20:43.81#ibcon#about to read 5, iclass 7, count 0 2006.201.17:20:43.81#ibcon#read 5, iclass 7, count 0 2006.201.17:20:43.81#ibcon#about to read 6, iclass 7, count 0 2006.201.17:20:43.81#ibcon#read 6, iclass 7, count 0 2006.201.17:20:43.81#ibcon#end of sib2, iclass 7, count 0 2006.201.17:20:43.81#ibcon#*after write, iclass 7, count 0 2006.201.17:20:43.81#ibcon#*before return 0, iclass 7, count 0 2006.201.17:20:43.81#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:43.81#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:20:43.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:20:43.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:20:43.81$vck44/vblo=7,734.99 2006.201.17:20:43.81#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.17:20:43.81#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.17:20:43.81#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:43.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:43.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:43.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:43.81#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:20:43.81#ibcon#first serial, iclass 11, count 0 2006.201.17:20:43.81#ibcon#enter sib2, iclass 11, count 0 2006.201.17:20:43.81#ibcon#flushed, iclass 11, count 0 2006.201.17:20:43.81#ibcon#about to write, iclass 11, count 0 2006.201.17:20:43.81#ibcon#wrote, iclass 11, count 0 2006.201.17:20:43.81#ibcon#about to read 3, iclass 11, count 0 2006.201.17:20:43.83#ibcon#read 3, iclass 11, count 0 2006.201.17:20:43.83#ibcon#about to read 4, iclass 11, count 0 2006.201.17:20:43.83#ibcon#read 4, iclass 11, count 0 2006.201.17:20:43.83#ibcon#about to read 5, iclass 11, count 0 2006.201.17:20:43.83#ibcon#read 5, iclass 11, count 0 2006.201.17:20:43.83#ibcon#about to read 6, iclass 11, count 0 2006.201.17:20:43.83#ibcon#read 6, iclass 11, count 0 2006.201.17:20:43.83#ibcon#end of sib2, iclass 11, count 0 2006.201.17:20:43.83#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:20:43.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:20:43.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.17:20:43.83#ibcon#*before write, iclass 11, count 0 2006.201.17:20:43.83#ibcon#enter sib2, iclass 11, count 0 2006.201.17:20:43.83#ibcon#flushed, iclass 11, count 0 2006.201.17:20:43.83#ibcon#about to write, iclass 11, count 0 2006.201.17:20:43.83#ibcon#wrote, iclass 11, count 0 2006.201.17:20:43.83#ibcon#about to read 3, iclass 11, count 0 2006.201.17:20:43.88#ibcon#read 3, iclass 11, count 0 2006.201.17:20:43.88#ibcon#about to read 4, iclass 11, count 0 2006.201.17:20:43.88#ibcon#read 4, iclass 11, count 0 2006.201.17:20:43.88#ibcon#about to read 5, iclass 11, count 0 2006.201.17:20:43.88#ibcon#read 5, iclass 11, count 0 2006.201.17:20:43.88#ibcon#about to read 6, iclass 11, count 0 2006.201.17:20:43.88#ibcon#read 6, iclass 11, count 0 2006.201.17:20:43.88#ibcon#end of sib2, iclass 11, count 0 2006.201.17:20:43.88#ibcon#*after write, iclass 11, count 0 2006.201.17:20:43.88#ibcon#*before return 0, iclass 11, count 0 2006.201.17:20:43.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:43.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:20:43.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:20:43.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:20:43.88$vck44/vb=7,4 2006.201.17:20:43.88#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.17:20:43.88#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.17:20:43.88#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:43.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:43.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:43.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:43.93#ibcon#enter wrdev, iclass 13, count 2 2006.201.17:20:43.93#ibcon#first serial, iclass 13, count 2 2006.201.17:20:43.93#ibcon#enter sib2, iclass 13, count 2 2006.201.17:20:43.93#ibcon#flushed, iclass 13, count 2 2006.201.17:20:43.93#ibcon#about to write, iclass 13, count 2 2006.201.17:20:43.93#ibcon#wrote, iclass 13, count 2 2006.201.17:20:43.93#ibcon#about to read 3, iclass 13, count 2 2006.201.17:20:43.95#ibcon#read 3, iclass 13, count 2 2006.201.17:20:43.95#ibcon#about to read 4, iclass 13, count 2 2006.201.17:20:43.95#ibcon#read 4, iclass 13, count 2 2006.201.17:20:43.95#ibcon#about to read 5, iclass 13, count 2 2006.201.17:20:43.95#ibcon#read 5, iclass 13, count 2 2006.201.17:20:43.95#ibcon#about to read 6, iclass 13, count 2 2006.201.17:20:43.95#ibcon#read 6, iclass 13, count 2 2006.201.17:20:43.95#ibcon#end of sib2, iclass 13, count 2 2006.201.17:20:43.95#ibcon#*mode == 0, iclass 13, count 2 2006.201.17:20:43.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.17:20:43.95#ibcon#[27=AT07-04\r\n] 2006.201.17:20:43.95#ibcon#*before write, iclass 13, count 2 2006.201.17:20:43.95#ibcon#enter sib2, iclass 13, count 2 2006.201.17:20:43.95#ibcon#flushed, iclass 13, count 2 2006.201.17:20:43.95#ibcon#about to write, iclass 13, count 2 2006.201.17:20:43.95#ibcon#wrote, iclass 13, count 2 2006.201.17:20:43.95#ibcon#about to read 3, iclass 13, count 2 2006.201.17:20:43.98#ibcon#read 3, iclass 13, count 2 2006.201.17:20:43.98#ibcon#about to read 4, iclass 13, count 2 2006.201.17:20:43.98#ibcon#read 4, iclass 13, count 2 2006.201.17:20:43.98#ibcon#about to read 5, iclass 13, count 2 2006.201.17:20:43.98#ibcon#read 5, iclass 13, count 2 2006.201.17:20:43.98#ibcon#about to read 6, iclass 13, count 2 2006.201.17:20:43.98#ibcon#read 6, iclass 13, count 2 2006.201.17:20:43.98#ibcon#end of sib2, iclass 13, count 2 2006.201.17:20:43.98#ibcon#*after write, iclass 13, count 2 2006.201.17:20:43.98#ibcon#*before return 0, iclass 13, count 2 2006.201.17:20:43.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:43.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:20:43.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.17:20:43.98#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:43.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:44.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:44.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:44.10#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:20:44.10#ibcon#first serial, iclass 13, count 0 2006.201.17:20:44.10#ibcon#enter sib2, iclass 13, count 0 2006.201.17:20:44.10#ibcon#flushed, iclass 13, count 0 2006.201.17:20:44.10#ibcon#about to write, iclass 13, count 0 2006.201.17:20:44.10#ibcon#wrote, iclass 13, count 0 2006.201.17:20:44.10#ibcon#about to read 3, iclass 13, count 0 2006.201.17:20:44.12#ibcon#read 3, iclass 13, count 0 2006.201.17:20:44.12#ibcon#about to read 4, iclass 13, count 0 2006.201.17:20:44.12#ibcon#read 4, iclass 13, count 0 2006.201.17:20:44.12#ibcon#about to read 5, iclass 13, count 0 2006.201.17:20:44.12#ibcon#read 5, iclass 13, count 0 2006.201.17:20:44.12#ibcon#about to read 6, iclass 13, count 0 2006.201.17:20:44.12#ibcon#read 6, iclass 13, count 0 2006.201.17:20:44.12#ibcon#end of sib2, iclass 13, count 0 2006.201.17:20:44.12#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:20:44.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:20:44.12#ibcon#[27=USB\r\n] 2006.201.17:20:44.12#ibcon#*before write, iclass 13, count 0 2006.201.17:20:44.12#ibcon#enter sib2, iclass 13, count 0 2006.201.17:20:44.12#ibcon#flushed, iclass 13, count 0 2006.201.17:20:44.12#ibcon#about to write, iclass 13, count 0 2006.201.17:20:44.12#ibcon#wrote, iclass 13, count 0 2006.201.17:20:44.12#ibcon#about to read 3, iclass 13, count 0 2006.201.17:20:44.15#ibcon#read 3, iclass 13, count 0 2006.201.17:20:44.15#ibcon#about to read 4, iclass 13, count 0 2006.201.17:20:44.15#ibcon#read 4, iclass 13, count 0 2006.201.17:20:44.15#ibcon#about to read 5, iclass 13, count 0 2006.201.17:20:44.15#ibcon#read 5, iclass 13, count 0 2006.201.17:20:44.15#ibcon#about to read 6, iclass 13, count 0 2006.201.17:20:44.15#ibcon#read 6, iclass 13, count 0 2006.201.17:20:44.15#ibcon#end of sib2, iclass 13, count 0 2006.201.17:20:44.15#ibcon#*after write, iclass 13, count 0 2006.201.17:20:44.15#ibcon#*before return 0, iclass 13, count 0 2006.201.17:20:44.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:44.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:20:44.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:20:44.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:20:44.15$vck44/vblo=8,744.99 2006.201.17:20:44.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.17:20:44.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.17:20:44.15#ibcon#ireg 17 cls_cnt 0 2006.201.17:20:44.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:44.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:44.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:44.15#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:20:44.15#ibcon#first serial, iclass 15, count 0 2006.201.17:20:44.15#ibcon#enter sib2, iclass 15, count 0 2006.201.17:20:44.15#ibcon#flushed, iclass 15, count 0 2006.201.17:20:44.15#ibcon#about to write, iclass 15, count 0 2006.201.17:20:44.15#ibcon#wrote, iclass 15, count 0 2006.201.17:20:44.15#ibcon#about to read 3, iclass 15, count 0 2006.201.17:20:44.17#ibcon#read 3, iclass 15, count 0 2006.201.17:20:44.17#ibcon#about to read 4, iclass 15, count 0 2006.201.17:20:44.17#ibcon#read 4, iclass 15, count 0 2006.201.17:20:44.17#ibcon#about to read 5, iclass 15, count 0 2006.201.17:20:44.17#ibcon#read 5, iclass 15, count 0 2006.201.17:20:44.17#ibcon#about to read 6, iclass 15, count 0 2006.201.17:20:44.17#ibcon#read 6, iclass 15, count 0 2006.201.17:20:44.17#ibcon#end of sib2, iclass 15, count 0 2006.201.17:20:44.17#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:20:44.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:20:44.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.17:20:44.17#ibcon#*before write, iclass 15, count 0 2006.201.17:20:44.17#ibcon#enter sib2, iclass 15, count 0 2006.201.17:20:44.17#ibcon#flushed, iclass 15, count 0 2006.201.17:20:44.17#ibcon#about to write, iclass 15, count 0 2006.201.17:20:44.17#ibcon#wrote, iclass 15, count 0 2006.201.17:20:44.17#ibcon#about to read 3, iclass 15, count 0 2006.201.17:20:44.21#ibcon#read 3, iclass 15, count 0 2006.201.17:20:44.21#ibcon#about to read 4, iclass 15, count 0 2006.201.17:20:44.21#ibcon#read 4, iclass 15, count 0 2006.201.17:20:44.21#ibcon#about to read 5, iclass 15, count 0 2006.201.17:20:44.21#ibcon#read 5, iclass 15, count 0 2006.201.17:20:44.21#ibcon#about to read 6, iclass 15, count 0 2006.201.17:20:44.21#ibcon#read 6, iclass 15, count 0 2006.201.17:20:44.21#ibcon#end of sib2, iclass 15, count 0 2006.201.17:20:44.21#ibcon#*after write, iclass 15, count 0 2006.201.17:20:44.21#ibcon#*before return 0, iclass 15, count 0 2006.201.17:20:44.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:44.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:20:44.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:20:44.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:20:44.21$vck44/vb=8,4 2006.201.17:20:44.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.17:20:44.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.17:20:44.21#ibcon#ireg 11 cls_cnt 2 2006.201.17:20:44.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:44.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:44.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:44.27#ibcon#enter wrdev, iclass 17, count 2 2006.201.17:20:44.27#ibcon#first serial, iclass 17, count 2 2006.201.17:20:44.27#ibcon#enter sib2, iclass 17, count 2 2006.201.17:20:44.27#ibcon#flushed, iclass 17, count 2 2006.201.17:20:44.27#ibcon#about to write, iclass 17, count 2 2006.201.17:20:44.27#ibcon#wrote, iclass 17, count 2 2006.201.17:20:44.27#ibcon#about to read 3, iclass 17, count 2 2006.201.17:20:44.29#ibcon#read 3, iclass 17, count 2 2006.201.17:20:44.29#ibcon#about to read 4, iclass 17, count 2 2006.201.17:20:44.29#ibcon#read 4, iclass 17, count 2 2006.201.17:20:44.29#ibcon#about to read 5, iclass 17, count 2 2006.201.17:20:44.29#ibcon#read 5, iclass 17, count 2 2006.201.17:20:44.29#ibcon#about to read 6, iclass 17, count 2 2006.201.17:20:44.29#ibcon#read 6, iclass 17, count 2 2006.201.17:20:44.29#ibcon#end of sib2, iclass 17, count 2 2006.201.17:20:44.29#ibcon#*mode == 0, iclass 17, count 2 2006.201.17:20:44.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.17:20:44.29#ibcon#[27=AT08-04\r\n] 2006.201.17:20:44.29#ibcon#*before write, iclass 17, count 2 2006.201.17:20:44.29#ibcon#enter sib2, iclass 17, count 2 2006.201.17:20:44.29#ibcon#flushed, iclass 17, count 2 2006.201.17:20:44.29#ibcon#about to write, iclass 17, count 2 2006.201.17:20:44.29#ibcon#wrote, iclass 17, count 2 2006.201.17:20:44.29#ibcon#about to read 3, iclass 17, count 2 2006.201.17:20:44.32#ibcon#read 3, iclass 17, count 2 2006.201.17:20:44.32#ibcon#about to read 4, iclass 17, count 2 2006.201.17:20:44.32#ibcon#read 4, iclass 17, count 2 2006.201.17:20:44.32#ibcon#about to read 5, iclass 17, count 2 2006.201.17:20:44.32#ibcon#read 5, iclass 17, count 2 2006.201.17:20:44.32#ibcon#about to read 6, iclass 17, count 2 2006.201.17:20:44.32#ibcon#read 6, iclass 17, count 2 2006.201.17:20:44.32#ibcon#end of sib2, iclass 17, count 2 2006.201.17:20:44.32#ibcon#*after write, iclass 17, count 2 2006.201.17:20:44.32#ibcon#*before return 0, iclass 17, count 2 2006.201.17:20:44.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:44.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:20:44.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.17:20:44.32#ibcon#ireg 7 cls_cnt 0 2006.201.17:20:44.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:44.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:44.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:44.44#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:20:44.44#ibcon#first serial, iclass 17, count 0 2006.201.17:20:44.44#ibcon#enter sib2, iclass 17, count 0 2006.201.17:20:44.44#ibcon#flushed, iclass 17, count 0 2006.201.17:20:44.44#ibcon#about to write, iclass 17, count 0 2006.201.17:20:44.44#ibcon#wrote, iclass 17, count 0 2006.201.17:20:44.44#ibcon#about to read 3, iclass 17, count 0 2006.201.17:20:44.46#ibcon#read 3, iclass 17, count 0 2006.201.17:20:44.46#ibcon#about to read 4, iclass 17, count 0 2006.201.17:20:44.46#ibcon#read 4, iclass 17, count 0 2006.201.17:20:44.46#ibcon#about to read 5, iclass 17, count 0 2006.201.17:20:44.46#ibcon#read 5, iclass 17, count 0 2006.201.17:20:44.46#ibcon#about to read 6, iclass 17, count 0 2006.201.17:20:44.46#ibcon#read 6, iclass 17, count 0 2006.201.17:20:44.46#ibcon#end of sib2, iclass 17, count 0 2006.201.17:20:44.46#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:20:44.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:20:44.46#ibcon#[27=USB\r\n] 2006.201.17:20:44.46#ibcon#*before write, iclass 17, count 0 2006.201.17:20:44.46#ibcon#enter sib2, iclass 17, count 0 2006.201.17:20:44.46#ibcon#flushed, iclass 17, count 0 2006.201.17:20:44.46#ibcon#about to write, iclass 17, count 0 2006.201.17:20:44.46#ibcon#wrote, iclass 17, count 0 2006.201.17:20:44.46#ibcon#about to read 3, iclass 17, count 0 2006.201.17:20:44.49#ibcon#read 3, iclass 17, count 0 2006.201.17:20:44.49#ibcon#about to read 4, iclass 17, count 0 2006.201.17:20:44.49#ibcon#read 4, iclass 17, count 0 2006.201.17:20:44.49#ibcon#about to read 5, iclass 17, count 0 2006.201.17:20:44.49#ibcon#read 5, iclass 17, count 0 2006.201.17:20:44.49#ibcon#about to read 6, iclass 17, count 0 2006.201.17:20:44.49#ibcon#read 6, iclass 17, count 0 2006.201.17:20:44.49#ibcon#end of sib2, iclass 17, count 0 2006.201.17:20:44.49#ibcon#*after write, iclass 17, count 0 2006.201.17:20:44.49#ibcon#*before return 0, iclass 17, count 0 2006.201.17:20:44.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:44.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:20:44.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:20:44.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:20:44.49$vck44/vabw=wide 2006.201.17:20:44.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.17:20:44.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.17:20:44.49#ibcon#ireg 8 cls_cnt 0 2006.201.17:20:44.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:44.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:44.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:44.49#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:20:44.49#ibcon#first serial, iclass 19, count 0 2006.201.17:20:44.49#ibcon#enter sib2, iclass 19, count 0 2006.201.17:20:44.49#ibcon#flushed, iclass 19, count 0 2006.201.17:20:44.49#ibcon#about to write, iclass 19, count 0 2006.201.17:20:44.49#ibcon#wrote, iclass 19, count 0 2006.201.17:20:44.49#ibcon#about to read 3, iclass 19, count 0 2006.201.17:20:44.51#ibcon#read 3, iclass 19, count 0 2006.201.17:20:44.51#ibcon#about to read 4, iclass 19, count 0 2006.201.17:20:44.51#ibcon#read 4, iclass 19, count 0 2006.201.17:20:44.51#ibcon#about to read 5, iclass 19, count 0 2006.201.17:20:44.51#ibcon#read 5, iclass 19, count 0 2006.201.17:20:44.51#ibcon#about to read 6, iclass 19, count 0 2006.201.17:20:44.51#ibcon#read 6, iclass 19, count 0 2006.201.17:20:44.51#ibcon#end of sib2, iclass 19, count 0 2006.201.17:20:44.51#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:20:44.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:20:44.51#ibcon#[25=BW32\r\n] 2006.201.17:20:44.51#ibcon#*before write, iclass 19, count 0 2006.201.17:20:44.51#ibcon#enter sib2, iclass 19, count 0 2006.201.17:20:44.51#ibcon#flushed, iclass 19, count 0 2006.201.17:20:44.51#ibcon#about to write, iclass 19, count 0 2006.201.17:20:44.51#ibcon#wrote, iclass 19, count 0 2006.201.17:20:44.51#ibcon#about to read 3, iclass 19, count 0 2006.201.17:20:44.55#ibcon#read 3, iclass 19, count 0 2006.201.17:20:44.55#ibcon#about to read 4, iclass 19, count 0 2006.201.17:20:44.55#ibcon#read 4, iclass 19, count 0 2006.201.17:20:44.55#ibcon#about to read 5, iclass 19, count 0 2006.201.17:20:44.55#ibcon#read 5, iclass 19, count 0 2006.201.17:20:44.55#ibcon#about to read 6, iclass 19, count 0 2006.201.17:20:44.55#ibcon#read 6, iclass 19, count 0 2006.201.17:20:44.55#ibcon#end of sib2, iclass 19, count 0 2006.201.17:20:44.55#ibcon#*after write, iclass 19, count 0 2006.201.17:20:44.55#ibcon#*before return 0, iclass 19, count 0 2006.201.17:20:44.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:44.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:20:44.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:20:44.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:20:44.55$vck44/vbbw=wide 2006.201.17:20:44.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.17:20:44.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.17:20:44.55#ibcon#ireg 8 cls_cnt 0 2006.201.17:20:44.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:20:44.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:20:44.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:20:44.61#ibcon#enter wrdev, iclass 21, count 0 2006.201.17:20:44.61#ibcon#first serial, iclass 21, count 0 2006.201.17:20:44.61#ibcon#enter sib2, iclass 21, count 0 2006.201.17:20:44.61#ibcon#flushed, iclass 21, count 0 2006.201.17:20:44.61#ibcon#about to write, iclass 21, count 0 2006.201.17:20:44.61#ibcon#wrote, iclass 21, count 0 2006.201.17:20:44.61#ibcon#about to read 3, iclass 21, count 0 2006.201.17:20:44.63#ibcon#read 3, iclass 21, count 0 2006.201.17:20:44.63#ibcon#about to read 4, iclass 21, count 0 2006.201.17:20:44.63#ibcon#read 4, iclass 21, count 0 2006.201.17:20:44.63#ibcon#about to read 5, iclass 21, count 0 2006.201.17:20:44.63#ibcon#read 5, iclass 21, count 0 2006.201.17:20:44.63#ibcon#about to read 6, iclass 21, count 0 2006.201.17:20:44.63#ibcon#read 6, iclass 21, count 0 2006.201.17:20:44.63#ibcon#end of sib2, iclass 21, count 0 2006.201.17:20:44.63#ibcon#*mode == 0, iclass 21, count 0 2006.201.17:20:44.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.17:20:44.63#ibcon#[27=BW32\r\n] 2006.201.17:20:44.63#ibcon#*before write, iclass 21, count 0 2006.201.17:20:44.63#ibcon#enter sib2, iclass 21, count 0 2006.201.17:20:44.63#ibcon#flushed, iclass 21, count 0 2006.201.17:20:44.63#ibcon#about to write, iclass 21, count 0 2006.201.17:20:44.63#ibcon#wrote, iclass 21, count 0 2006.201.17:20:44.63#ibcon#about to read 3, iclass 21, count 0 2006.201.17:20:44.66#ibcon#read 3, iclass 21, count 0 2006.201.17:20:44.66#ibcon#about to read 4, iclass 21, count 0 2006.201.17:20:44.66#ibcon#read 4, iclass 21, count 0 2006.201.17:20:44.66#ibcon#about to read 5, iclass 21, count 0 2006.201.17:20:44.66#ibcon#read 5, iclass 21, count 0 2006.201.17:20:44.66#ibcon#about to read 6, iclass 21, count 0 2006.201.17:20:44.66#ibcon#read 6, iclass 21, count 0 2006.201.17:20:44.66#ibcon#end of sib2, iclass 21, count 0 2006.201.17:20:44.66#ibcon#*after write, iclass 21, count 0 2006.201.17:20:44.66#ibcon#*before return 0, iclass 21, count 0 2006.201.17:20:44.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:20:44.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:20:44.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.17:20:44.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.17:20:44.66$setupk4/ifdk4 2006.201.17:20:44.66$ifdk4/lo= 2006.201.17:20:44.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.17:20:44.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.17:20:44.66$ifdk4/patch= 2006.201.17:20:44.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.17:20:44.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.17:20:44.66$setupk4/!*+20s 2006.201.17:20:47.72#abcon#<5=/16 0.3 0.6 20.731001002.6\r\n> 2006.201.17:20:47.74#abcon#{5=INTERFACE CLEAR} 2006.201.17:20:47.80#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:20:57.89#abcon#<5=/16 0.3 0.6 20.731001002.7\r\n> 2006.201.17:20:57.91#abcon#{5=INTERFACE CLEAR} 2006.201.17:20:57.97#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:20:59.13$setupk4/"tpicd 2006.201.17:20:59.13$setupk4/echo=off 2006.201.17:20:59.13$setupk4/xlog=off 2006.201.17:20:59.13:!2006.201.17:24:40 2006.201.17:21:03.13#trakl#Source acquired 2006.201.17:21:04.13#flagr#flagr/antenna,acquired 2006.201.17:24:40.00:preob 2006.201.17:24:41.14/onsource/TRACKING 2006.201.17:24:41.14:!2006.201.17:24:50 2006.201.17:24:50.00:"tape 2006.201.17:24:50.00:"st=record 2006.201.17:24:50.00:data_valid=on 2006.201.17:24:50.00:midob 2006.201.17:24:50.14/onsource/TRACKING 2006.201.17:24:50.14/wx/20.73,1002.6,100 2006.201.17:24:50.37/cable/+6.4769E-03 2006.201.17:24:51.46/va/01,08,usb,yes,51,54 2006.201.17:24:51.46/va/02,07,usb,yes,55,56 2006.201.17:24:51.46/va/03,08,usb,yes,50,52 2006.201.17:24:51.46/va/04,07,usb,yes,57,60 2006.201.17:24:51.46/va/05,04,usb,yes,51,52 2006.201.17:24:51.46/va/06,05,usb,yes,51,51 2006.201.17:24:51.46/va/07,05,usb,yes,50,52 2006.201.17:24:51.46/va/08,04,usb,yes,49,58 2006.201.17:24:51.69/valo/01,524.99,yes,locked 2006.201.17:24:51.69/valo/02,534.99,yes,locked 2006.201.17:24:51.69/valo/03,564.99,yes,locked 2006.201.17:24:51.69/valo/04,624.99,yes,locked 2006.201.17:24:51.69/valo/05,734.99,yes,locked 2006.201.17:24:51.69/valo/06,814.99,yes,locked 2006.201.17:24:51.69/valo/07,864.99,yes,locked 2006.201.17:24:51.69/valo/08,884.99,yes,locked 2006.201.17:24:52.78/vb/01,04,usb,yes,31,29 2006.201.17:24:52.78/vb/02,05,usb,yes,30,29 2006.201.17:24:52.78/vb/03,04,usb,yes,31,34 2006.201.17:24:52.78/vb/04,05,usb,yes,31,30 2006.201.17:24:52.78/vb/05,04,usb,yes,27,30 2006.201.17:24:52.78/vb/06,04,usb,yes,32,28 2006.201.17:24:52.78/vb/07,04,usb,yes,32,32 2006.201.17:24:52.78/vb/08,04,usb,yes,29,33 2006.201.17:24:53.02/vblo/01,629.99,yes,locked 2006.201.17:24:53.02/vblo/02,634.99,yes,locked 2006.201.17:24:53.02/vblo/03,649.99,yes,locked 2006.201.17:24:53.02/vblo/04,679.99,yes,locked 2006.201.17:24:53.02/vblo/05,709.99,yes,locked 2006.201.17:24:53.02/vblo/06,719.99,yes,locked 2006.201.17:24:53.02/vblo/07,734.99,yes,locked 2006.201.17:24:53.02/vblo/08,744.99,yes,locked 2006.201.17:24:53.17/vabw/8 2006.201.17:24:53.32/vbbw/8 2006.201.17:24:53.41/xfe/off,on,15.2 2006.201.17:24:53.79/ifatt/23,28,28,28 2006.201.17:24:54.06/fmout-gps/S +4.52E-07 2006.201.17:24:54.13:!2006.201.17:29:30 2006.201.17:29:30.00:data_valid=off 2006.201.17:29:30.00:"et 2006.201.17:29:30.00:!+3s 2006.201.17:29:33.02:"tape 2006.201.17:29:33.02:postob 2006.201.17:29:33.17/cable/+6.4776E-03 2006.201.17:29:33.20/wx/20.73,1002.6,100 2006.201.17:29:33.26/fmout-gps/S +4.51E-07 2006.201.17:29:33.26:scan_name=201-1738,jd0607,220 2006.201.17:29:33.26:source=0014+813,001708.47,813508.1,2000.0,neutral 2006.201.17:29:35.13#flagr#flagr/antenna,new-source 2006.201.17:29:35.13:checkk5 2006.201.17:29:35.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.17:29:35.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.17:29:36.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.17:29:36.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.17:29:37.01/chk_obsdata//k5ts1/T2011724??a.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.201.17:29:37.37/chk_obsdata//k5ts2/T2011724??b.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.201.17:29:37.74/chk_obsdata//k5ts3/T2011724??c.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.201.17:29:38.11/chk_obsdata//k5ts4/T2011724??d.dat file size is correct (nominal:1120MB, actual:1120MB). 2006.201.17:29:38.79/k5log//k5ts1_log_newline 2006.201.17:29:39.49/k5log//k5ts2_log_newline 2006.201.17:29:40.18/k5log//k5ts3_log_newline 2006.201.17:29:40.87/k5log//k5ts4_log_newline 2006.201.17:29:40.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.17:29:40.89:setupk4=1 2006.201.17:29:40.89$setupk4/echo=on 2006.201.17:29:40.89$setupk4/pcalon 2006.201.17:29:40.89$pcalon/"no phase cal control is implemented here 2006.201.17:29:40.89$setupk4/"tpicd=stop 2006.201.17:29:40.89$setupk4/"rec=synch_on 2006.201.17:29:40.89$setupk4/"rec_mode=128 2006.201.17:29:40.89$setupk4/!* 2006.201.17:29:40.89$setupk4/recpk4 2006.201.17:29:40.89$recpk4/recpatch= 2006.201.17:29:40.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.17:29:40.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.17:29:40.90$setupk4/vck44 2006.201.17:29:40.90$vck44/valo=1,524.99 2006.201.17:29:40.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.17:29:40.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.17:29:40.90#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:40.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:40.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:40.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:40.90#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:29:40.90#ibcon#first serial, iclass 17, count 0 2006.201.17:29:40.90#ibcon#enter sib2, iclass 17, count 0 2006.201.17:29:40.90#ibcon#flushed, iclass 17, count 0 2006.201.17:29:40.90#ibcon#about to write, iclass 17, count 0 2006.201.17:29:40.90#ibcon#wrote, iclass 17, count 0 2006.201.17:29:40.90#ibcon#about to read 3, iclass 17, count 0 2006.201.17:29:40.93#ibcon#read 3, iclass 17, count 0 2006.201.17:29:40.93#ibcon#about to read 4, iclass 17, count 0 2006.201.17:29:40.93#ibcon#read 4, iclass 17, count 0 2006.201.17:29:40.93#ibcon#about to read 5, iclass 17, count 0 2006.201.17:29:40.93#ibcon#read 5, iclass 17, count 0 2006.201.17:29:40.93#ibcon#about to read 6, iclass 17, count 0 2006.201.17:29:40.93#ibcon#read 6, iclass 17, count 0 2006.201.17:29:40.93#ibcon#end of sib2, iclass 17, count 0 2006.201.17:29:40.93#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:29:40.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:29:40.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.17:29:40.93#ibcon#*before write, iclass 17, count 0 2006.201.17:29:40.93#ibcon#enter sib2, iclass 17, count 0 2006.201.17:29:40.93#ibcon#flushed, iclass 17, count 0 2006.201.17:29:40.93#ibcon#about to write, iclass 17, count 0 2006.201.17:29:40.93#ibcon#wrote, iclass 17, count 0 2006.201.17:29:40.93#ibcon#about to read 3, iclass 17, count 0 2006.201.17:29:40.98#ibcon#read 3, iclass 17, count 0 2006.201.17:29:40.98#ibcon#about to read 4, iclass 17, count 0 2006.201.17:29:40.98#ibcon#read 4, iclass 17, count 0 2006.201.17:29:40.98#ibcon#about to read 5, iclass 17, count 0 2006.201.17:29:40.98#ibcon#read 5, iclass 17, count 0 2006.201.17:29:40.98#ibcon#about to read 6, iclass 17, count 0 2006.201.17:29:40.98#ibcon#read 6, iclass 17, count 0 2006.201.17:29:40.98#ibcon#end of sib2, iclass 17, count 0 2006.201.17:29:40.98#ibcon#*after write, iclass 17, count 0 2006.201.17:29:40.98#ibcon#*before return 0, iclass 17, count 0 2006.201.17:29:40.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:40.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:40.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:29:40.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:29:40.98$vck44/va=1,8 2006.201.17:29:40.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.17:29:40.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.17:29:40.98#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:40.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:40.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:40.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:40.98#ibcon#enter wrdev, iclass 19, count 2 2006.201.17:29:40.98#ibcon#first serial, iclass 19, count 2 2006.201.17:29:40.98#ibcon#enter sib2, iclass 19, count 2 2006.201.17:29:40.98#ibcon#flushed, iclass 19, count 2 2006.201.17:29:40.98#ibcon#about to write, iclass 19, count 2 2006.201.17:29:40.98#ibcon#wrote, iclass 19, count 2 2006.201.17:29:40.98#ibcon#about to read 3, iclass 19, count 2 2006.201.17:29:41.00#ibcon#read 3, iclass 19, count 2 2006.201.17:29:41.00#ibcon#about to read 4, iclass 19, count 2 2006.201.17:29:41.00#ibcon#read 4, iclass 19, count 2 2006.201.17:29:41.00#ibcon#about to read 5, iclass 19, count 2 2006.201.17:29:41.00#ibcon#read 5, iclass 19, count 2 2006.201.17:29:41.00#ibcon#about to read 6, iclass 19, count 2 2006.201.17:29:41.00#ibcon#read 6, iclass 19, count 2 2006.201.17:29:41.00#ibcon#end of sib2, iclass 19, count 2 2006.201.17:29:41.00#ibcon#*mode == 0, iclass 19, count 2 2006.201.17:29:41.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.17:29:41.00#ibcon#[25=AT01-08\r\n] 2006.201.17:29:41.00#ibcon#*before write, iclass 19, count 2 2006.201.17:29:41.00#ibcon#enter sib2, iclass 19, count 2 2006.201.17:29:41.00#ibcon#flushed, iclass 19, count 2 2006.201.17:29:41.00#ibcon#about to write, iclass 19, count 2 2006.201.17:29:41.00#ibcon#wrote, iclass 19, count 2 2006.201.17:29:41.00#ibcon#about to read 3, iclass 19, count 2 2006.201.17:29:41.03#ibcon#read 3, iclass 19, count 2 2006.201.17:29:41.03#ibcon#about to read 4, iclass 19, count 2 2006.201.17:29:41.03#ibcon#read 4, iclass 19, count 2 2006.201.17:29:41.03#ibcon#about to read 5, iclass 19, count 2 2006.201.17:29:41.03#ibcon#read 5, iclass 19, count 2 2006.201.17:29:41.03#ibcon#about to read 6, iclass 19, count 2 2006.201.17:29:41.03#ibcon#read 6, iclass 19, count 2 2006.201.17:29:41.03#ibcon#end of sib2, iclass 19, count 2 2006.201.17:29:41.03#ibcon#*after write, iclass 19, count 2 2006.201.17:29:41.03#ibcon#*before return 0, iclass 19, count 2 2006.201.17:29:41.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:41.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:41.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.17:29:41.03#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:41.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:41.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:41.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:41.15#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:29:41.15#ibcon#first serial, iclass 19, count 0 2006.201.17:29:41.15#ibcon#enter sib2, iclass 19, count 0 2006.201.17:29:41.15#ibcon#flushed, iclass 19, count 0 2006.201.17:29:41.15#ibcon#about to write, iclass 19, count 0 2006.201.17:29:41.15#ibcon#wrote, iclass 19, count 0 2006.201.17:29:41.15#ibcon#about to read 3, iclass 19, count 0 2006.201.17:29:41.17#ibcon#read 3, iclass 19, count 0 2006.201.17:29:41.17#ibcon#about to read 4, iclass 19, count 0 2006.201.17:29:41.17#ibcon#read 4, iclass 19, count 0 2006.201.17:29:41.17#ibcon#about to read 5, iclass 19, count 0 2006.201.17:29:41.17#ibcon#read 5, iclass 19, count 0 2006.201.17:29:41.17#ibcon#about to read 6, iclass 19, count 0 2006.201.17:29:41.17#ibcon#read 6, iclass 19, count 0 2006.201.17:29:41.17#ibcon#end of sib2, iclass 19, count 0 2006.201.17:29:41.17#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:29:41.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:29:41.17#ibcon#[25=USB\r\n] 2006.201.17:29:41.17#ibcon#*before write, iclass 19, count 0 2006.201.17:29:41.17#ibcon#enter sib2, iclass 19, count 0 2006.201.17:29:41.17#ibcon#flushed, iclass 19, count 0 2006.201.17:29:41.17#ibcon#about to write, iclass 19, count 0 2006.201.17:29:41.17#ibcon#wrote, iclass 19, count 0 2006.201.17:29:41.17#ibcon#about to read 3, iclass 19, count 0 2006.201.17:29:41.20#ibcon#read 3, iclass 19, count 0 2006.201.17:29:41.20#ibcon#about to read 4, iclass 19, count 0 2006.201.17:29:41.20#ibcon#read 4, iclass 19, count 0 2006.201.17:29:41.20#ibcon#about to read 5, iclass 19, count 0 2006.201.17:29:41.20#ibcon#read 5, iclass 19, count 0 2006.201.17:29:41.20#ibcon#about to read 6, iclass 19, count 0 2006.201.17:29:41.20#ibcon#read 6, iclass 19, count 0 2006.201.17:29:41.20#ibcon#end of sib2, iclass 19, count 0 2006.201.17:29:41.20#ibcon#*after write, iclass 19, count 0 2006.201.17:29:41.20#ibcon#*before return 0, iclass 19, count 0 2006.201.17:29:41.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:41.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:41.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:29:41.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:29:41.20$vck44/valo=2,534.99 2006.201.17:29:41.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.17:29:41.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.17:29:41.20#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:41.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:41.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:41.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:41.20#ibcon#enter wrdev, iclass 21, count 0 2006.201.17:29:41.20#ibcon#first serial, iclass 21, count 0 2006.201.17:29:41.20#ibcon#enter sib2, iclass 21, count 0 2006.201.17:29:41.20#ibcon#flushed, iclass 21, count 0 2006.201.17:29:41.20#ibcon#about to write, iclass 21, count 0 2006.201.17:29:41.20#ibcon#wrote, iclass 21, count 0 2006.201.17:29:41.20#ibcon#about to read 3, iclass 21, count 0 2006.201.17:29:41.22#ibcon#read 3, iclass 21, count 0 2006.201.17:29:41.22#ibcon#about to read 4, iclass 21, count 0 2006.201.17:29:41.22#ibcon#read 4, iclass 21, count 0 2006.201.17:29:41.22#ibcon#about to read 5, iclass 21, count 0 2006.201.17:29:41.22#ibcon#read 5, iclass 21, count 0 2006.201.17:29:41.22#ibcon#about to read 6, iclass 21, count 0 2006.201.17:29:41.22#ibcon#read 6, iclass 21, count 0 2006.201.17:29:41.22#ibcon#end of sib2, iclass 21, count 0 2006.201.17:29:41.22#ibcon#*mode == 0, iclass 21, count 0 2006.201.17:29:41.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.17:29:41.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.17:29:41.22#ibcon#*before write, iclass 21, count 0 2006.201.17:29:41.22#ibcon#enter sib2, iclass 21, count 0 2006.201.17:29:41.22#ibcon#flushed, iclass 21, count 0 2006.201.17:29:41.22#ibcon#about to write, iclass 21, count 0 2006.201.17:29:41.22#ibcon#wrote, iclass 21, count 0 2006.201.17:29:41.22#ibcon#about to read 3, iclass 21, count 0 2006.201.17:29:41.26#ibcon#read 3, iclass 21, count 0 2006.201.17:29:41.26#ibcon#about to read 4, iclass 21, count 0 2006.201.17:29:41.26#ibcon#read 4, iclass 21, count 0 2006.201.17:29:41.26#ibcon#about to read 5, iclass 21, count 0 2006.201.17:29:41.26#ibcon#read 5, iclass 21, count 0 2006.201.17:29:41.26#ibcon#about to read 6, iclass 21, count 0 2006.201.17:29:41.26#ibcon#read 6, iclass 21, count 0 2006.201.17:29:41.26#ibcon#end of sib2, iclass 21, count 0 2006.201.17:29:41.26#ibcon#*after write, iclass 21, count 0 2006.201.17:29:41.26#ibcon#*before return 0, iclass 21, count 0 2006.201.17:29:41.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:41.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:41.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.17:29:41.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.17:29:41.26$vck44/va=2,7 2006.201.17:29:41.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.17:29:41.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.17:29:41.26#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:41.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:41.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:41.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:41.32#ibcon#enter wrdev, iclass 23, count 2 2006.201.17:29:41.32#ibcon#first serial, iclass 23, count 2 2006.201.17:29:41.32#ibcon#enter sib2, iclass 23, count 2 2006.201.17:29:41.32#ibcon#flushed, iclass 23, count 2 2006.201.17:29:41.32#ibcon#about to write, iclass 23, count 2 2006.201.17:29:41.32#ibcon#wrote, iclass 23, count 2 2006.201.17:29:41.32#ibcon#about to read 3, iclass 23, count 2 2006.201.17:29:41.34#ibcon#read 3, iclass 23, count 2 2006.201.17:29:41.34#ibcon#about to read 4, iclass 23, count 2 2006.201.17:29:41.34#ibcon#read 4, iclass 23, count 2 2006.201.17:29:41.34#ibcon#about to read 5, iclass 23, count 2 2006.201.17:29:41.34#ibcon#read 5, iclass 23, count 2 2006.201.17:29:41.34#ibcon#about to read 6, iclass 23, count 2 2006.201.17:29:41.34#ibcon#read 6, iclass 23, count 2 2006.201.17:29:41.34#ibcon#end of sib2, iclass 23, count 2 2006.201.17:29:41.34#ibcon#*mode == 0, iclass 23, count 2 2006.201.17:29:41.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.17:29:41.34#ibcon#[25=AT02-07\r\n] 2006.201.17:29:41.34#ibcon#*before write, iclass 23, count 2 2006.201.17:29:41.34#ibcon#enter sib2, iclass 23, count 2 2006.201.17:29:41.34#ibcon#flushed, iclass 23, count 2 2006.201.17:29:41.34#ibcon#about to write, iclass 23, count 2 2006.201.17:29:41.34#ibcon#wrote, iclass 23, count 2 2006.201.17:29:41.34#ibcon#about to read 3, iclass 23, count 2 2006.201.17:29:41.37#ibcon#read 3, iclass 23, count 2 2006.201.17:29:41.37#ibcon#about to read 4, iclass 23, count 2 2006.201.17:29:41.37#ibcon#read 4, iclass 23, count 2 2006.201.17:29:41.37#ibcon#about to read 5, iclass 23, count 2 2006.201.17:29:41.37#ibcon#read 5, iclass 23, count 2 2006.201.17:29:41.37#ibcon#about to read 6, iclass 23, count 2 2006.201.17:29:41.37#ibcon#read 6, iclass 23, count 2 2006.201.17:29:41.37#ibcon#end of sib2, iclass 23, count 2 2006.201.17:29:41.37#ibcon#*after write, iclass 23, count 2 2006.201.17:29:41.37#ibcon#*before return 0, iclass 23, count 2 2006.201.17:29:41.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:41.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:41.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.17:29:41.37#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:41.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:41.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:41.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:41.49#ibcon#enter wrdev, iclass 23, count 0 2006.201.17:29:41.49#ibcon#first serial, iclass 23, count 0 2006.201.17:29:41.49#ibcon#enter sib2, iclass 23, count 0 2006.201.17:29:41.49#ibcon#flushed, iclass 23, count 0 2006.201.17:29:41.49#ibcon#about to write, iclass 23, count 0 2006.201.17:29:41.49#ibcon#wrote, iclass 23, count 0 2006.201.17:29:41.49#ibcon#about to read 3, iclass 23, count 0 2006.201.17:29:41.51#ibcon#read 3, iclass 23, count 0 2006.201.17:29:41.51#ibcon#about to read 4, iclass 23, count 0 2006.201.17:29:41.51#ibcon#read 4, iclass 23, count 0 2006.201.17:29:41.51#ibcon#about to read 5, iclass 23, count 0 2006.201.17:29:41.51#ibcon#read 5, iclass 23, count 0 2006.201.17:29:41.51#ibcon#about to read 6, iclass 23, count 0 2006.201.17:29:41.51#ibcon#read 6, iclass 23, count 0 2006.201.17:29:41.51#ibcon#end of sib2, iclass 23, count 0 2006.201.17:29:41.51#ibcon#*mode == 0, iclass 23, count 0 2006.201.17:29:41.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.17:29:41.51#ibcon#[25=USB\r\n] 2006.201.17:29:41.51#ibcon#*before write, iclass 23, count 0 2006.201.17:29:41.51#ibcon#enter sib2, iclass 23, count 0 2006.201.17:29:41.51#ibcon#flushed, iclass 23, count 0 2006.201.17:29:41.51#ibcon#about to write, iclass 23, count 0 2006.201.17:29:41.51#ibcon#wrote, iclass 23, count 0 2006.201.17:29:41.51#ibcon#about to read 3, iclass 23, count 0 2006.201.17:29:41.54#ibcon#read 3, iclass 23, count 0 2006.201.17:29:41.54#ibcon#about to read 4, iclass 23, count 0 2006.201.17:29:41.54#ibcon#read 4, iclass 23, count 0 2006.201.17:29:41.54#ibcon#about to read 5, iclass 23, count 0 2006.201.17:29:41.54#ibcon#read 5, iclass 23, count 0 2006.201.17:29:41.54#ibcon#about to read 6, iclass 23, count 0 2006.201.17:29:41.54#ibcon#read 6, iclass 23, count 0 2006.201.17:29:41.54#ibcon#end of sib2, iclass 23, count 0 2006.201.17:29:41.54#ibcon#*after write, iclass 23, count 0 2006.201.17:29:41.54#ibcon#*before return 0, iclass 23, count 0 2006.201.17:29:41.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:41.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:41.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.17:29:41.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.17:29:41.54$vck44/valo=3,564.99 2006.201.17:29:41.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.17:29:41.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.17:29:41.54#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:41.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:41.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:41.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:41.54#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:29:41.54#ibcon#first serial, iclass 25, count 0 2006.201.17:29:41.54#ibcon#enter sib2, iclass 25, count 0 2006.201.17:29:41.54#ibcon#flushed, iclass 25, count 0 2006.201.17:29:41.54#ibcon#about to write, iclass 25, count 0 2006.201.17:29:41.54#ibcon#wrote, iclass 25, count 0 2006.201.17:29:41.54#ibcon#about to read 3, iclass 25, count 0 2006.201.17:29:41.56#ibcon#read 3, iclass 25, count 0 2006.201.17:29:41.56#ibcon#about to read 4, iclass 25, count 0 2006.201.17:29:41.56#ibcon#read 4, iclass 25, count 0 2006.201.17:29:41.56#ibcon#about to read 5, iclass 25, count 0 2006.201.17:29:41.56#ibcon#read 5, iclass 25, count 0 2006.201.17:29:41.56#ibcon#about to read 6, iclass 25, count 0 2006.201.17:29:41.56#ibcon#read 6, iclass 25, count 0 2006.201.17:29:41.56#ibcon#end of sib2, iclass 25, count 0 2006.201.17:29:41.56#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:29:41.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:29:41.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.17:29:41.56#ibcon#*before write, iclass 25, count 0 2006.201.17:29:41.56#ibcon#enter sib2, iclass 25, count 0 2006.201.17:29:41.56#ibcon#flushed, iclass 25, count 0 2006.201.17:29:41.56#ibcon#about to write, iclass 25, count 0 2006.201.17:29:41.56#ibcon#wrote, iclass 25, count 0 2006.201.17:29:41.56#ibcon#about to read 3, iclass 25, count 0 2006.201.17:29:41.61#ibcon#read 3, iclass 25, count 0 2006.201.17:29:41.61#ibcon#about to read 4, iclass 25, count 0 2006.201.17:29:41.61#ibcon#read 4, iclass 25, count 0 2006.201.17:29:41.61#ibcon#about to read 5, iclass 25, count 0 2006.201.17:29:41.61#ibcon#read 5, iclass 25, count 0 2006.201.17:29:41.61#ibcon#about to read 6, iclass 25, count 0 2006.201.17:29:41.61#ibcon#read 6, iclass 25, count 0 2006.201.17:29:41.61#ibcon#end of sib2, iclass 25, count 0 2006.201.17:29:41.61#ibcon#*after write, iclass 25, count 0 2006.201.17:29:41.61#ibcon#*before return 0, iclass 25, count 0 2006.201.17:29:41.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:41.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:41.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:29:41.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:29:41.61$vck44/va=3,8 2006.201.17:29:41.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.17:29:41.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.17:29:41.61#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:41.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:41.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:41.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:41.66#ibcon#enter wrdev, iclass 27, count 2 2006.201.17:29:41.66#ibcon#first serial, iclass 27, count 2 2006.201.17:29:41.66#ibcon#enter sib2, iclass 27, count 2 2006.201.17:29:41.66#ibcon#flushed, iclass 27, count 2 2006.201.17:29:41.66#ibcon#about to write, iclass 27, count 2 2006.201.17:29:41.66#ibcon#wrote, iclass 27, count 2 2006.201.17:29:41.66#ibcon#about to read 3, iclass 27, count 2 2006.201.17:29:41.68#ibcon#read 3, iclass 27, count 2 2006.201.17:29:41.68#ibcon#about to read 4, iclass 27, count 2 2006.201.17:29:41.68#ibcon#read 4, iclass 27, count 2 2006.201.17:29:41.68#ibcon#about to read 5, iclass 27, count 2 2006.201.17:29:41.68#ibcon#read 5, iclass 27, count 2 2006.201.17:29:41.68#ibcon#about to read 6, iclass 27, count 2 2006.201.17:29:41.68#ibcon#read 6, iclass 27, count 2 2006.201.17:29:41.68#ibcon#end of sib2, iclass 27, count 2 2006.201.17:29:41.68#ibcon#*mode == 0, iclass 27, count 2 2006.201.17:29:41.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.17:29:41.68#ibcon#[25=AT03-08\r\n] 2006.201.17:29:41.68#ibcon#*before write, iclass 27, count 2 2006.201.17:29:41.68#ibcon#enter sib2, iclass 27, count 2 2006.201.17:29:41.68#ibcon#flushed, iclass 27, count 2 2006.201.17:29:41.68#ibcon#about to write, iclass 27, count 2 2006.201.17:29:41.68#ibcon#wrote, iclass 27, count 2 2006.201.17:29:41.68#ibcon#about to read 3, iclass 27, count 2 2006.201.17:29:41.71#ibcon#read 3, iclass 27, count 2 2006.201.17:29:41.71#ibcon#about to read 4, iclass 27, count 2 2006.201.17:29:41.71#ibcon#read 4, iclass 27, count 2 2006.201.17:29:41.71#ibcon#about to read 5, iclass 27, count 2 2006.201.17:29:41.71#ibcon#read 5, iclass 27, count 2 2006.201.17:29:41.71#ibcon#about to read 6, iclass 27, count 2 2006.201.17:29:41.71#ibcon#read 6, iclass 27, count 2 2006.201.17:29:41.71#ibcon#end of sib2, iclass 27, count 2 2006.201.17:29:41.71#ibcon#*after write, iclass 27, count 2 2006.201.17:29:41.71#ibcon#*before return 0, iclass 27, count 2 2006.201.17:29:41.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:41.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:41.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.17:29:41.71#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:41.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:41.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:41.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:41.83#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:29:41.83#ibcon#first serial, iclass 27, count 0 2006.201.17:29:41.83#ibcon#enter sib2, iclass 27, count 0 2006.201.17:29:41.83#ibcon#flushed, iclass 27, count 0 2006.201.17:29:41.83#ibcon#about to write, iclass 27, count 0 2006.201.17:29:41.83#ibcon#wrote, iclass 27, count 0 2006.201.17:29:41.83#ibcon#about to read 3, iclass 27, count 0 2006.201.17:29:41.85#ibcon#read 3, iclass 27, count 0 2006.201.17:29:41.85#ibcon#about to read 4, iclass 27, count 0 2006.201.17:29:41.85#ibcon#read 4, iclass 27, count 0 2006.201.17:29:41.85#ibcon#about to read 5, iclass 27, count 0 2006.201.17:29:41.85#ibcon#read 5, iclass 27, count 0 2006.201.17:29:41.85#ibcon#about to read 6, iclass 27, count 0 2006.201.17:29:41.85#ibcon#read 6, iclass 27, count 0 2006.201.17:29:41.85#ibcon#end of sib2, iclass 27, count 0 2006.201.17:29:41.85#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:29:41.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:29:41.85#ibcon#[25=USB\r\n] 2006.201.17:29:41.85#ibcon#*before write, iclass 27, count 0 2006.201.17:29:41.85#ibcon#enter sib2, iclass 27, count 0 2006.201.17:29:41.85#ibcon#flushed, iclass 27, count 0 2006.201.17:29:41.85#ibcon#about to write, iclass 27, count 0 2006.201.17:29:41.85#ibcon#wrote, iclass 27, count 0 2006.201.17:29:41.85#ibcon#about to read 3, iclass 27, count 0 2006.201.17:29:41.88#ibcon#read 3, iclass 27, count 0 2006.201.17:29:41.88#ibcon#about to read 4, iclass 27, count 0 2006.201.17:29:41.88#ibcon#read 4, iclass 27, count 0 2006.201.17:29:41.88#ibcon#about to read 5, iclass 27, count 0 2006.201.17:29:41.88#ibcon#read 5, iclass 27, count 0 2006.201.17:29:41.88#ibcon#about to read 6, iclass 27, count 0 2006.201.17:29:41.88#ibcon#read 6, iclass 27, count 0 2006.201.17:29:41.88#ibcon#end of sib2, iclass 27, count 0 2006.201.17:29:41.88#ibcon#*after write, iclass 27, count 0 2006.201.17:29:41.88#ibcon#*before return 0, iclass 27, count 0 2006.201.17:29:41.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:41.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:41.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:29:41.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:29:41.88$vck44/valo=4,624.99 2006.201.17:29:41.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.17:29:41.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.17:29:41.88#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:41.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:41.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:41.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:41.88#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:29:41.88#ibcon#first serial, iclass 29, count 0 2006.201.17:29:41.88#ibcon#enter sib2, iclass 29, count 0 2006.201.17:29:41.88#ibcon#flushed, iclass 29, count 0 2006.201.17:29:41.88#ibcon#about to write, iclass 29, count 0 2006.201.17:29:41.88#ibcon#wrote, iclass 29, count 0 2006.201.17:29:41.88#ibcon#about to read 3, iclass 29, count 0 2006.201.17:29:41.90#ibcon#read 3, iclass 29, count 0 2006.201.17:29:41.90#ibcon#about to read 4, iclass 29, count 0 2006.201.17:29:41.90#ibcon#read 4, iclass 29, count 0 2006.201.17:29:41.90#ibcon#about to read 5, iclass 29, count 0 2006.201.17:29:41.90#ibcon#read 5, iclass 29, count 0 2006.201.17:29:41.90#ibcon#about to read 6, iclass 29, count 0 2006.201.17:29:41.90#ibcon#read 6, iclass 29, count 0 2006.201.17:29:41.90#ibcon#end of sib2, iclass 29, count 0 2006.201.17:29:41.90#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:29:41.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:29:41.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.17:29:41.90#ibcon#*before write, iclass 29, count 0 2006.201.17:29:41.90#ibcon#enter sib2, iclass 29, count 0 2006.201.17:29:41.90#ibcon#flushed, iclass 29, count 0 2006.201.17:29:41.90#ibcon#about to write, iclass 29, count 0 2006.201.17:29:41.90#ibcon#wrote, iclass 29, count 0 2006.201.17:29:41.90#ibcon#about to read 3, iclass 29, count 0 2006.201.17:29:41.94#ibcon#read 3, iclass 29, count 0 2006.201.17:29:41.94#ibcon#about to read 4, iclass 29, count 0 2006.201.17:29:41.94#ibcon#read 4, iclass 29, count 0 2006.201.17:29:41.94#ibcon#about to read 5, iclass 29, count 0 2006.201.17:29:41.94#ibcon#read 5, iclass 29, count 0 2006.201.17:29:41.94#ibcon#about to read 6, iclass 29, count 0 2006.201.17:29:41.94#ibcon#read 6, iclass 29, count 0 2006.201.17:29:41.94#ibcon#end of sib2, iclass 29, count 0 2006.201.17:29:41.94#ibcon#*after write, iclass 29, count 0 2006.201.17:29:41.94#ibcon#*before return 0, iclass 29, count 0 2006.201.17:29:41.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:41.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:41.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:29:41.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:29:41.94$vck44/va=4,7 2006.201.17:29:41.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.17:29:41.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.17:29:41.94#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:41.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:42.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:42.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:42.00#ibcon#enter wrdev, iclass 31, count 2 2006.201.17:29:42.00#ibcon#first serial, iclass 31, count 2 2006.201.17:29:42.00#ibcon#enter sib2, iclass 31, count 2 2006.201.17:29:42.00#ibcon#flushed, iclass 31, count 2 2006.201.17:29:42.00#ibcon#about to write, iclass 31, count 2 2006.201.17:29:42.00#ibcon#wrote, iclass 31, count 2 2006.201.17:29:42.00#ibcon#about to read 3, iclass 31, count 2 2006.201.17:29:42.02#ibcon#read 3, iclass 31, count 2 2006.201.17:29:42.02#ibcon#about to read 4, iclass 31, count 2 2006.201.17:29:42.02#ibcon#read 4, iclass 31, count 2 2006.201.17:29:42.02#ibcon#about to read 5, iclass 31, count 2 2006.201.17:29:42.02#ibcon#read 5, iclass 31, count 2 2006.201.17:29:42.02#ibcon#about to read 6, iclass 31, count 2 2006.201.17:29:42.02#ibcon#read 6, iclass 31, count 2 2006.201.17:29:42.02#ibcon#end of sib2, iclass 31, count 2 2006.201.17:29:42.02#ibcon#*mode == 0, iclass 31, count 2 2006.201.17:29:42.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.17:29:42.02#ibcon#[25=AT04-07\r\n] 2006.201.17:29:42.02#ibcon#*before write, iclass 31, count 2 2006.201.17:29:42.02#ibcon#enter sib2, iclass 31, count 2 2006.201.17:29:42.02#ibcon#flushed, iclass 31, count 2 2006.201.17:29:42.02#ibcon#about to write, iclass 31, count 2 2006.201.17:29:42.02#ibcon#wrote, iclass 31, count 2 2006.201.17:29:42.02#ibcon#about to read 3, iclass 31, count 2 2006.201.17:29:42.05#ibcon#read 3, iclass 31, count 2 2006.201.17:29:42.05#ibcon#about to read 4, iclass 31, count 2 2006.201.17:29:42.05#ibcon#read 4, iclass 31, count 2 2006.201.17:29:42.05#ibcon#about to read 5, iclass 31, count 2 2006.201.17:29:42.05#ibcon#read 5, iclass 31, count 2 2006.201.17:29:42.05#ibcon#about to read 6, iclass 31, count 2 2006.201.17:29:42.05#ibcon#read 6, iclass 31, count 2 2006.201.17:29:42.05#ibcon#end of sib2, iclass 31, count 2 2006.201.17:29:42.05#ibcon#*after write, iclass 31, count 2 2006.201.17:29:42.05#ibcon#*before return 0, iclass 31, count 2 2006.201.17:29:42.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:42.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:42.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.17:29:42.05#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:42.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:42.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:42.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:42.17#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:29:42.17#ibcon#first serial, iclass 31, count 0 2006.201.17:29:42.17#ibcon#enter sib2, iclass 31, count 0 2006.201.17:29:42.17#ibcon#flushed, iclass 31, count 0 2006.201.17:29:42.17#ibcon#about to write, iclass 31, count 0 2006.201.17:29:42.17#ibcon#wrote, iclass 31, count 0 2006.201.17:29:42.17#ibcon#about to read 3, iclass 31, count 0 2006.201.17:29:42.19#ibcon#read 3, iclass 31, count 0 2006.201.17:29:42.19#ibcon#about to read 4, iclass 31, count 0 2006.201.17:29:42.19#ibcon#read 4, iclass 31, count 0 2006.201.17:29:42.19#ibcon#about to read 5, iclass 31, count 0 2006.201.17:29:42.19#ibcon#read 5, iclass 31, count 0 2006.201.17:29:42.19#ibcon#about to read 6, iclass 31, count 0 2006.201.17:29:42.19#ibcon#read 6, iclass 31, count 0 2006.201.17:29:42.19#ibcon#end of sib2, iclass 31, count 0 2006.201.17:29:42.19#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:29:42.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:29:42.19#ibcon#[25=USB\r\n] 2006.201.17:29:42.19#ibcon#*before write, iclass 31, count 0 2006.201.17:29:42.19#ibcon#enter sib2, iclass 31, count 0 2006.201.17:29:42.19#ibcon#flushed, iclass 31, count 0 2006.201.17:29:42.19#ibcon#about to write, iclass 31, count 0 2006.201.17:29:42.19#ibcon#wrote, iclass 31, count 0 2006.201.17:29:42.19#ibcon#about to read 3, iclass 31, count 0 2006.201.17:29:42.22#ibcon#read 3, iclass 31, count 0 2006.201.17:29:42.22#ibcon#about to read 4, iclass 31, count 0 2006.201.17:29:42.22#ibcon#read 4, iclass 31, count 0 2006.201.17:29:42.22#ibcon#about to read 5, iclass 31, count 0 2006.201.17:29:42.22#ibcon#read 5, iclass 31, count 0 2006.201.17:29:42.22#ibcon#about to read 6, iclass 31, count 0 2006.201.17:29:42.22#ibcon#read 6, iclass 31, count 0 2006.201.17:29:42.22#ibcon#end of sib2, iclass 31, count 0 2006.201.17:29:42.22#ibcon#*after write, iclass 31, count 0 2006.201.17:29:42.22#ibcon#*before return 0, iclass 31, count 0 2006.201.17:29:42.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:42.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:42.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:29:42.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:29:42.22$vck44/valo=5,734.99 2006.201.17:29:42.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.17:29:42.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.17:29:42.22#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:42.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:42.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:42.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:42.22#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:29:42.22#ibcon#first serial, iclass 33, count 0 2006.201.17:29:42.22#ibcon#enter sib2, iclass 33, count 0 2006.201.17:29:42.22#ibcon#flushed, iclass 33, count 0 2006.201.17:29:42.22#ibcon#about to write, iclass 33, count 0 2006.201.17:29:42.22#ibcon#wrote, iclass 33, count 0 2006.201.17:29:42.22#ibcon#about to read 3, iclass 33, count 0 2006.201.17:29:42.24#ibcon#read 3, iclass 33, count 0 2006.201.17:29:42.24#ibcon#about to read 4, iclass 33, count 0 2006.201.17:29:42.24#ibcon#read 4, iclass 33, count 0 2006.201.17:29:42.24#ibcon#about to read 5, iclass 33, count 0 2006.201.17:29:42.24#ibcon#read 5, iclass 33, count 0 2006.201.17:29:42.24#ibcon#about to read 6, iclass 33, count 0 2006.201.17:29:42.24#ibcon#read 6, iclass 33, count 0 2006.201.17:29:42.24#ibcon#end of sib2, iclass 33, count 0 2006.201.17:29:42.24#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:29:42.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:29:42.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.17:29:42.24#ibcon#*before write, iclass 33, count 0 2006.201.17:29:42.24#ibcon#enter sib2, iclass 33, count 0 2006.201.17:29:42.24#ibcon#flushed, iclass 33, count 0 2006.201.17:29:42.24#ibcon#about to write, iclass 33, count 0 2006.201.17:29:42.24#ibcon#wrote, iclass 33, count 0 2006.201.17:29:42.24#ibcon#about to read 3, iclass 33, count 0 2006.201.17:29:42.28#ibcon#read 3, iclass 33, count 0 2006.201.17:29:42.28#ibcon#about to read 4, iclass 33, count 0 2006.201.17:29:42.28#ibcon#read 4, iclass 33, count 0 2006.201.17:29:42.28#ibcon#about to read 5, iclass 33, count 0 2006.201.17:29:42.28#ibcon#read 5, iclass 33, count 0 2006.201.17:29:42.28#ibcon#about to read 6, iclass 33, count 0 2006.201.17:29:42.28#ibcon#read 6, iclass 33, count 0 2006.201.17:29:42.28#ibcon#end of sib2, iclass 33, count 0 2006.201.17:29:42.28#ibcon#*after write, iclass 33, count 0 2006.201.17:29:42.28#ibcon#*before return 0, iclass 33, count 0 2006.201.17:29:42.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:42.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:42.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:29:42.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:29:42.28$vck44/va=5,4 2006.201.17:29:42.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.17:29:42.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.17:29:42.28#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:42.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:42.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:42.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:42.34#ibcon#enter wrdev, iclass 35, count 2 2006.201.17:29:42.34#ibcon#first serial, iclass 35, count 2 2006.201.17:29:42.34#ibcon#enter sib2, iclass 35, count 2 2006.201.17:29:42.34#ibcon#flushed, iclass 35, count 2 2006.201.17:29:42.34#ibcon#about to write, iclass 35, count 2 2006.201.17:29:42.34#ibcon#wrote, iclass 35, count 2 2006.201.17:29:42.34#ibcon#about to read 3, iclass 35, count 2 2006.201.17:29:42.36#ibcon#read 3, iclass 35, count 2 2006.201.17:29:42.36#ibcon#about to read 4, iclass 35, count 2 2006.201.17:29:42.36#ibcon#read 4, iclass 35, count 2 2006.201.17:29:42.36#ibcon#about to read 5, iclass 35, count 2 2006.201.17:29:42.36#ibcon#read 5, iclass 35, count 2 2006.201.17:29:42.36#ibcon#about to read 6, iclass 35, count 2 2006.201.17:29:42.36#ibcon#read 6, iclass 35, count 2 2006.201.17:29:42.36#ibcon#end of sib2, iclass 35, count 2 2006.201.17:29:42.36#ibcon#*mode == 0, iclass 35, count 2 2006.201.17:29:42.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.17:29:42.36#ibcon#[25=AT05-04\r\n] 2006.201.17:29:42.36#ibcon#*before write, iclass 35, count 2 2006.201.17:29:42.36#ibcon#enter sib2, iclass 35, count 2 2006.201.17:29:42.36#ibcon#flushed, iclass 35, count 2 2006.201.17:29:42.36#ibcon#about to write, iclass 35, count 2 2006.201.17:29:42.36#ibcon#wrote, iclass 35, count 2 2006.201.17:29:42.36#ibcon#about to read 3, iclass 35, count 2 2006.201.17:29:42.39#ibcon#read 3, iclass 35, count 2 2006.201.17:29:42.39#ibcon#about to read 4, iclass 35, count 2 2006.201.17:29:42.39#ibcon#read 4, iclass 35, count 2 2006.201.17:29:42.39#ibcon#about to read 5, iclass 35, count 2 2006.201.17:29:42.39#ibcon#read 5, iclass 35, count 2 2006.201.17:29:42.39#ibcon#about to read 6, iclass 35, count 2 2006.201.17:29:42.39#ibcon#read 6, iclass 35, count 2 2006.201.17:29:42.39#ibcon#end of sib2, iclass 35, count 2 2006.201.17:29:42.39#ibcon#*after write, iclass 35, count 2 2006.201.17:29:42.39#ibcon#*before return 0, iclass 35, count 2 2006.201.17:29:42.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:42.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:42.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.17:29:42.39#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:42.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:42.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:42.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:42.51#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:29:42.51#ibcon#first serial, iclass 35, count 0 2006.201.17:29:42.51#ibcon#enter sib2, iclass 35, count 0 2006.201.17:29:42.51#ibcon#flushed, iclass 35, count 0 2006.201.17:29:42.51#ibcon#about to write, iclass 35, count 0 2006.201.17:29:42.51#ibcon#wrote, iclass 35, count 0 2006.201.17:29:42.51#ibcon#about to read 3, iclass 35, count 0 2006.201.17:29:42.53#ibcon#read 3, iclass 35, count 0 2006.201.17:29:42.53#ibcon#about to read 4, iclass 35, count 0 2006.201.17:29:42.53#ibcon#read 4, iclass 35, count 0 2006.201.17:29:42.53#ibcon#about to read 5, iclass 35, count 0 2006.201.17:29:42.53#ibcon#read 5, iclass 35, count 0 2006.201.17:29:42.53#ibcon#about to read 6, iclass 35, count 0 2006.201.17:29:42.53#ibcon#read 6, iclass 35, count 0 2006.201.17:29:42.53#ibcon#end of sib2, iclass 35, count 0 2006.201.17:29:42.53#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:29:42.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:29:42.53#ibcon#[25=USB\r\n] 2006.201.17:29:42.53#ibcon#*before write, iclass 35, count 0 2006.201.17:29:42.53#ibcon#enter sib2, iclass 35, count 0 2006.201.17:29:42.53#ibcon#flushed, iclass 35, count 0 2006.201.17:29:42.53#ibcon#about to write, iclass 35, count 0 2006.201.17:29:42.53#ibcon#wrote, iclass 35, count 0 2006.201.17:29:42.53#ibcon#about to read 3, iclass 35, count 0 2006.201.17:29:42.56#ibcon#read 3, iclass 35, count 0 2006.201.17:29:42.56#ibcon#about to read 4, iclass 35, count 0 2006.201.17:29:42.56#ibcon#read 4, iclass 35, count 0 2006.201.17:29:42.56#ibcon#about to read 5, iclass 35, count 0 2006.201.17:29:42.56#ibcon#read 5, iclass 35, count 0 2006.201.17:29:42.56#ibcon#about to read 6, iclass 35, count 0 2006.201.17:29:42.56#ibcon#read 6, iclass 35, count 0 2006.201.17:29:42.56#ibcon#end of sib2, iclass 35, count 0 2006.201.17:29:42.56#ibcon#*after write, iclass 35, count 0 2006.201.17:29:42.56#ibcon#*before return 0, iclass 35, count 0 2006.201.17:29:42.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:42.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:42.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:29:42.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:29:42.56$vck44/valo=6,814.99 2006.201.17:29:42.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.17:29:42.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.17:29:42.56#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:42.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:42.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:42.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:42.56#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:29:42.56#ibcon#first serial, iclass 37, count 0 2006.201.17:29:42.56#ibcon#enter sib2, iclass 37, count 0 2006.201.17:29:42.56#ibcon#flushed, iclass 37, count 0 2006.201.17:29:42.56#ibcon#about to write, iclass 37, count 0 2006.201.17:29:42.56#ibcon#wrote, iclass 37, count 0 2006.201.17:29:42.56#ibcon#about to read 3, iclass 37, count 0 2006.201.17:29:42.58#ibcon#read 3, iclass 37, count 0 2006.201.17:29:42.58#ibcon#about to read 4, iclass 37, count 0 2006.201.17:29:42.58#ibcon#read 4, iclass 37, count 0 2006.201.17:29:42.58#ibcon#about to read 5, iclass 37, count 0 2006.201.17:29:42.58#ibcon#read 5, iclass 37, count 0 2006.201.17:29:42.58#ibcon#about to read 6, iclass 37, count 0 2006.201.17:29:42.58#ibcon#read 6, iclass 37, count 0 2006.201.17:29:42.58#ibcon#end of sib2, iclass 37, count 0 2006.201.17:29:42.58#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:29:42.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:29:42.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.17:29:42.58#ibcon#*before write, iclass 37, count 0 2006.201.17:29:42.58#ibcon#enter sib2, iclass 37, count 0 2006.201.17:29:42.58#ibcon#flushed, iclass 37, count 0 2006.201.17:29:42.58#ibcon#about to write, iclass 37, count 0 2006.201.17:29:42.58#ibcon#wrote, iclass 37, count 0 2006.201.17:29:42.58#ibcon#about to read 3, iclass 37, count 0 2006.201.17:29:42.62#ibcon#read 3, iclass 37, count 0 2006.201.17:29:42.62#ibcon#about to read 4, iclass 37, count 0 2006.201.17:29:42.62#ibcon#read 4, iclass 37, count 0 2006.201.17:29:42.62#ibcon#about to read 5, iclass 37, count 0 2006.201.17:29:42.62#ibcon#read 5, iclass 37, count 0 2006.201.17:29:42.62#ibcon#about to read 6, iclass 37, count 0 2006.201.17:29:42.62#ibcon#read 6, iclass 37, count 0 2006.201.17:29:42.62#ibcon#end of sib2, iclass 37, count 0 2006.201.17:29:42.62#ibcon#*after write, iclass 37, count 0 2006.201.17:29:42.62#ibcon#*before return 0, iclass 37, count 0 2006.201.17:29:42.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:42.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:42.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:29:42.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:29:42.62$vck44/va=6,5 2006.201.17:29:42.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.17:29:42.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.17:29:42.62#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:42.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:42.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:42.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:42.68#ibcon#enter wrdev, iclass 39, count 2 2006.201.17:29:42.68#ibcon#first serial, iclass 39, count 2 2006.201.17:29:42.68#ibcon#enter sib2, iclass 39, count 2 2006.201.17:29:42.68#ibcon#flushed, iclass 39, count 2 2006.201.17:29:42.68#ibcon#about to write, iclass 39, count 2 2006.201.17:29:42.68#ibcon#wrote, iclass 39, count 2 2006.201.17:29:42.68#ibcon#about to read 3, iclass 39, count 2 2006.201.17:29:42.70#ibcon#read 3, iclass 39, count 2 2006.201.17:29:42.70#ibcon#about to read 4, iclass 39, count 2 2006.201.17:29:42.70#ibcon#read 4, iclass 39, count 2 2006.201.17:29:42.70#ibcon#about to read 5, iclass 39, count 2 2006.201.17:29:42.70#ibcon#read 5, iclass 39, count 2 2006.201.17:29:42.70#ibcon#about to read 6, iclass 39, count 2 2006.201.17:29:42.70#ibcon#read 6, iclass 39, count 2 2006.201.17:29:42.70#ibcon#end of sib2, iclass 39, count 2 2006.201.17:29:42.70#ibcon#*mode == 0, iclass 39, count 2 2006.201.17:29:42.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.17:29:42.70#ibcon#[25=AT06-05\r\n] 2006.201.17:29:42.70#ibcon#*before write, iclass 39, count 2 2006.201.17:29:42.70#ibcon#enter sib2, iclass 39, count 2 2006.201.17:29:42.70#ibcon#flushed, iclass 39, count 2 2006.201.17:29:42.70#ibcon#about to write, iclass 39, count 2 2006.201.17:29:42.70#ibcon#wrote, iclass 39, count 2 2006.201.17:29:42.70#ibcon#about to read 3, iclass 39, count 2 2006.201.17:29:42.73#ibcon#read 3, iclass 39, count 2 2006.201.17:29:42.73#ibcon#about to read 4, iclass 39, count 2 2006.201.17:29:42.73#ibcon#read 4, iclass 39, count 2 2006.201.17:29:42.73#ibcon#about to read 5, iclass 39, count 2 2006.201.17:29:42.73#ibcon#read 5, iclass 39, count 2 2006.201.17:29:42.73#ibcon#about to read 6, iclass 39, count 2 2006.201.17:29:42.73#ibcon#read 6, iclass 39, count 2 2006.201.17:29:42.73#ibcon#end of sib2, iclass 39, count 2 2006.201.17:29:42.73#ibcon#*after write, iclass 39, count 2 2006.201.17:29:42.73#ibcon#*before return 0, iclass 39, count 2 2006.201.17:29:42.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:42.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:42.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.17:29:42.73#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:42.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:42.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:42.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:42.85#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:29:42.85#ibcon#first serial, iclass 39, count 0 2006.201.17:29:42.85#ibcon#enter sib2, iclass 39, count 0 2006.201.17:29:42.85#ibcon#flushed, iclass 39, count 0 2006.201.17:29:42.85#ibcon#about to write, iclass 39, count 0 2006.201.17:29:42.85#ibcon#wrote, iclass 39, count 0 2006.201.17:29:42.85#ibcon#about to read 3, iclass 39, count 0 2006.201.17:29:42.87#ibcon#read 3, iclass 39, count 0 2006.201.17:29:42.87#ibcon#about to read 4, iclass 39, count 0 2006.201.17:29:42.87#ibcon#read 4, iclass 39, count 0 2006.201.17:29:42.87#ibcon#about to read 5, iclass 39, count 0 2006.201.17:29:42.87#ibcon#read 5, iclass 39, count 0 2006.201.17:29:42.87#ibcon#about to read 6, iclass 39, count 0 2006.201.17:29:42.87#ibcon#read 6, iclass 39, count 0 2006.201.17:29:42.87#ibcon#end of sib2, iclass 39, count 0 2006.201.17:29:42.87#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:29:42.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:29:42.87#ibcon#[25=USB\r\n] 2006.201.17:29:42.87#ibcon#*before write, iclass 39, count 0 2006.201.17:29:42.87#ibcon#enter sib2, iclass 39, count 0 2006.201.17:29:42.87#ibcon#flushed, iclass 39, count 0 2006.201.17:29:42.87#ibcon#about to write, iclass 39, count 0 2006.201.17:29:42.87#ibcon#wrote, iclass 39, count 0 2006.201.17:29:42.87#ibcon#about to read 3, iclass 39, count 0 2006.201.17:29:42.90#ibcon#read 3, iclass 39, count 0 2006.201.17:29:42.90#ibcon#about to read 4, iclass 39, count 0 2006.201.17:29:42.90#ibcon#read 4, iclass 39, count 0 2006.201.17:29:42.90#ibcon#about to read 5, iclass 39, count 0 2006.201.17:29:42.90#ibcon#read 5, iclass 39, count 0 2006.201.17:29:42.90#ibcon#about to read 6, iclass 39, count 0 2006.201.17:29:42.90#ibcon#read 6, iclass 39, count 0 2006.201.17:29:42.90#ibcon#end of sib2, iclass 39, count 0 2006.201.17:29:42.90#ibcon#*after write, iclass 39, count 0 2006.201.17:29:42.90#ibcon#*before return 0, iclass 39, count 0 2006.201.17:29:42.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:42.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:42.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:29:42.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:29:42.90$vck44/valo=7,864.99 2006.201.17:29:42.90#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.17:29:42.90#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.17:29:42.90#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:42.90#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:42.90#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:42.90#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:42.90#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:29:42.90#ibcon#first serial, iclass 2, count 0 2006.201.17:29:42.90#ibcon#enter sib2, iclass 2, count 0 2006.201.17:29:42.90#ibcon#flushed, iclass 2, count 0 2006.201.17:29:42.90#ibcon#about to write, iclass 2, count 0 2006.201.17:29:42.90#ibcon#wrote, iclass 2, count 0 2006.201.17:29:42.90#ibcon#about to read 3, iclass 2, count 0 2006.201.17:29:42.92#ibcon#read 3, iclass 2, count 0 2006.201.17:29:42.92#ibcon#about to read 4, iclass 2, count 0 2006.201.17:29:42.92#ibcon#read 4, iclass 2, count 0 2006.201.17:29:42.92#ibcon#about to read 5, iclass 2, count 0 2006.201.17:29:42.92#ibcon#read 5, iclass 2, count 0 2006.201.17:29:42.92#ibcon#about to read 6, iclass 2, count 0 2006.201.17:29:42.92#ibcon#read 6, iclass 2, count 0 2006.201.17:29:42.92#ibcon#end of sib2, iclass 2, count 0 2006.201.17:29:42.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:29:42.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:29:42.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.17:29:42.92#ibcon#*before write, iclass 2, count 0 2006.201.17:29:42.92#ibcon#enter sib2, iclass 2, count 0 2006.201.17:29:42.92#ibcon#flushed, iclass 2, count 0 2006.201.17:29:42.92#ibcon#about to write, iclass 2, count 0 2006.201.17:29:42.92#ibcon#wrote, iclass 2, count 0 2006.201.17:29:42.92#ibcon#about to read 3, iclass 2, count 0 2006.201.17:29:42.96#ibcon#read 3, iclass 2, count 0 2006.201.17:29:42.96#ibcon#about to read 4, iclass 2, count 0 2006.201.17:29:42.96#ibcon#read 4, iclass 2, count 0 2006.201.17:29:42.96#ibcon#about to read 5, iclass 2, count 0 2006.201.17:29:42.96#ibcon#read 5, iclass 2, count 0 2006.201.17:29:42.96#ibcon#about to read 6, iclass 2, count 0 2006.201.17:29:42.96#ibcon#read 6, iclass 2, count 0 2006.201.17:29:42.96#ibcon#end of sib2, iclass 2, count 0 2006.201.17:29:42.96#ibcon#*after write, iclass 2, count 0 2006.201.17:29:42.96#ibcon#*before return 0, iclass 2, count 0 2006.201.17:29:42.96#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:42.96#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:42.96#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:29:42.96#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:29:42.96$vck44/va=7,5 2006.201.17:29:42.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.17:29:42.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.17:29:42.96#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:42.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:43.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:43.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:43.02#ibcon#enter wrdev, iclass 5, count 2 2006.201.17:29:43.02#ibcon#first serial, iclass 5, count 2 2006.201.17:29:43.02#ibcon#enter sib2, iclass 5, count 2 2006.201.17:29:43.02#ibcon#flushed, iclass 5, count 2 2006.201.17:29:43.02#ibcon#about to write, iclass 5, count 2 2006.201.17:29:43.02#ibcon#wrote, iclass 5, count 2 2006.201.17:29:43.02#ibcon#about to read 3, iclass 5, count 2 2006.201.17:29:43.04#ibcon#read 3, iclass 5, count 2 2006.201.17:29:43.04#ibcon#about to read 4, iclass 5, count 2 2006.201.17:29:43.04#ibcon#read 4, iclass 5, count 2 2006.201.17:29:43.04#ibcon#about to read 5, iclass 5, count 2 2006.201.17:29:43.04#ibcon#read 5, iclass 5, count 2 2006.201.17:29:43.04#ibcon#about to read 6, iclass 5, count 2 2006.201.17:29:43.04#ibcon#read 6, iclass 5, count 2 2006.201.17:29:43.04#ibcon#end of sib2, iclass 5, count 2 2006.201.17:29:43.04#ibcon#*mode == 0, iclass 5, count 2 2006.201.17:29:43.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.17:29:43.04#ibcon#[25=AT07-05\r\n] 2006.201.17:29:43.04#ibcon#*before write, iclass 5, count 2 2006.201.17:29:43.04#ibcon#enter sib2, iclass 5, count 2 2006.201.17:29:43.04#ibcon#flushed, iclass 5, count 2 2006.201.17:29:43.04#ibcon#about to write, iclass 5, count 2 2006.201.17:29:43.04#ibcon#wrote, iclass 5, count 2 2006.201.17:29:43.04#ibcon#about to read 3, iclass 5, count 2 2006.201.17:29:43.07#ibcon#read 3, iclass 5, count 2 2006.201.17:29:43.07#ibcon#about to read 4, iclass 5, count 2 2006.201.17:29:43.07#ibcon#read 4, iclass 5, count 2 2006.201.17:29:43.07#ibcon#about to read 5, iclass 5, count 2 2006.201.17:29:43.07#ibcon#read 5, iclass 5, count 2 2006.201.17:29:43.07#ibcon#about to read 6, iclass 5, count 2 2006.201.17:29:43.07#ibcon#read 6, iclass 5, count 2 2006.201.17:29:43.07#ibcon#end of sib2, iclass 5, count 2 2006.201.17:29:43.07#ibcon#*after write, iclass 5, count 2 2006.201.17:29:43.07#ibcon#*before return 0, iclass 5, count 2 2006.201.17:29:43.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:43.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:43.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.17:29:43.07#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:43.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:43.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:43.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:43.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:29:43.19#ibcon#first serial, iclass 5, count 0 2006.201.17:29:43.19#ibcon#enter sib2, iclass 5, count 0 2006.201.17:29:43.19#ibcon#flushed, iclass 5, count 0 2006.201.17:29:43.19#ibcon#about to write, iclass 5, count 0 2006.201.17:29:43.19#ibcon#wrote, iclass 5, count 0 2006.201.17:29:43.19#ibcon#about to read 3, iclass 5, count 0 2006.201.17:29:43.21#ibcon#read 3, iclass 5, count 0 2006.201.17:29:43.21#ibcon#about to read 4, iclass 5, count 0 2006.201.17:29:43.21#ibcon#read 4, iclass 5, count 0 2006.201.17:29:43.21#ibcon#about to read 5, iclass 5, count 0 2006.201.17:29:43.21#ibcon#read 5, iclass 5, count 0 2006.201.17:29:43.21#ibcon#about to read 6, iclass 5, count 0 2006.201.17:29:43.21#ibcon#read 6, iclass 5, count 0 2006.201.17:29:43.21#ibcon#end of sib2, iclass 5, count 0 2006.201.17:29:43.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:29:43.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:29:43.21#ibcon#[25=USB\r\n] 2006.201.17:29:43.21#ibcon#*before write, iclass 5, count 0 2006.201.17:29:43.21#ibcon#enter sib2, iclass 5, count 0 2006.201.17:29:43.21#ibcon#flushed, iclass 5, count 0 2006.201.17:29:43.21#ibcon#about to write, iclass 5, count 0 2006.201.17:29:43.21#ibcon#wrote, iclass 5, count 0 2006.201.17:29:43.21#ibcon#about to read 3, iclass 5, count 0 2006.201.17:29:43.24#ibcon#read 3, iclass 5, count 0 2006.201.17:29:43.24#ibcon#about to read 4, iclass 5, count 0 2006.201.17:29:43.24#ibcon#read 4, iclass 5, count 0 2006.201.17:29:43.24#ibcon#about to read 5, iclass 5, count 0 2006.201.17:29:43.24#ibcon#read 5, iclass 5, count 0 2006.201.17:29:43.24#ibcon#about to read 6, iclass 5, count 0 2006.201.17:29:43.24#ibcon#read 6, iclass 5, count 0 2006.201.17:29:43.24#ibcon#end of sib2, iclass 5, count 0 2006.201.17:29:43.24#ibcon#*after write, iclass 5, count 0 2006.201.17:29:43.24#ibcon#*before return 0, iclass 5, count 0 2006.201.17:29:43.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:43.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:43.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:29:43.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:29:43.24$vck44/valo=8,884.99 2006.201.17:29:43.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.17:29:43.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.17:29:43.24#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:43.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:43.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:43.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:43.24#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:29:43.24#ibcon#first serial, iclass 7, count 0 2006.201.17:29:43.24#ibcon#enter sib2, iclass 7, count 0 2006.201.17:29:43.24#ibcon#flushed, iclass 7, count 0 2006.201.17:29:43.24#ibcon#about to write, iclass 7, count 0 2006.201.17:29:43.24#ibcon#wrote, iclass 7, count 0 2006.201.17:29:43.24#ibcon#about to read 3, iclass 7, count 0 2006.201.17:29:43.26#ibcon#read 3, iclass 7, count 0 2006.201.17:29:43.26#ibcon#about to read 4, iclass 7, count 0 2006.201.17:29:43.26#ibcon#read 4, iclass 7, count 0 2006.201.17:29:43.26#ibcon#about to read 5, iclass 7, count 0 2006.201.17:29:43.26#ibcon#read 5, iclass 7, count 0 2006.201.17:29:43.26#ibcon#about to read 6, iclass 7, count 0 2006.201.17:29:43.26#ibcon#read 6, iclass 7, count 0 2006.201.17:29:43.26#ibcon#end of sib2, iclass 7, count 0 2006.201.17:29:43.26#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:29:43.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:29:43.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.17:29:43.26#ibcon#*before write, iclass 7, count 0 2006.201.17:29:43.26#ibcon#enter sib2, iclass 7, count 0 2006.201.17:29:43.26#ibcon#flushed, iclass 7, count 0 2006.201.17:29:43.26#ibcon#about to write, iclass 7, count 0 2006.201.17:29:43.26#ibcon#wrote, iclass 7, count 0 2006.201.17:29:43.26#ibcon#about to read 3, iclass 7, count 0 2006.201.17:29:43.30#ibcon#read 3, iclass 7, count 0 2006.201.17:29:43.30#ibcon#about to read 4, iclass 7, count 0 2006.201.17:29:43.30#ibcon#read 4, iclass 7, count 0 2006.201.17:29:43.30#ibcon#about to read 5, iclass 7, count 0 2006.201.17:29:43.30#ibcon#read 5, iclass 7, count 0 2006.201.17:29:43.30#ibcon#about to read 6, iclass 7, count 0 2006.201.17:29:43.30#ibcon#read 6, iclass 7, count 0 2006.201.17:29:43.30#ibcon#end of sib2, iclass 7, count 0 2006.201.17:29:43.30#ibcon#*after write, iclass 7, count 0 2006.201.17:29:43.30#ibcon#*before return 0, iclass 7, count 0 2006.201.17:29:43.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:43.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:43.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:29:43.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:29:43.30$vck44/va=8,4 2006.201.17:29:43.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.17:29:43.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.17:29:43.30#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:43.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:29:43.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:29:43.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:29:43.36#ibcon#enter wrdev, iclass 11, count 2 2006.201.17:29:43.36#ibcon#first serial, iclass 11, count 2 2006.201.17:29:43.36#ibcon#enter sib2, iclass 11, count 2 2006.201.17:29:43.36#ibcon#flushed, iclass 11, count 2 2006.201.17:29:43.36#ibcon#about to write, iclass 11, count 2 2006.201.17:29:43.36#ibcon#wrote, iclass 11, count 2 2006.201.17:29:43.36#ibcon#about to read 3, iclass 11, count 2 2006.201.17:29:43.38#ibcon#read 3, iclass 11, count 2 2006.201.17:29:43.38#ibcon#about to read 4, iclass 11, count 2 2006.201.17:29:43.38#ibcon#read 4, iclass 11, count 2 2006.201.17:29:43.38#ibcon#about to read 5, iclass 11, count 2 2006.201.17:29:43.38#ibcon#read 5, iclass 11, count 2 2006.201.17:29:43.38#ibcon#about to read 6, iclass 11, count 2 2006.201.17:29:43.38#ibcon#read 6, iclass 11, count 2 2006.201.17:29:43.38#ibcon#end of sib2, iclass 11, count 2 2006.201.17:29:43.38#ibcon#*mode == 0, iclass 11, count 2 2006.201.17:29:43.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.17:29:43.38#ibcon#[25=AT08-04\r\n] 2006.201.17:29:43.38#ibcon#*before write, iclass 11, count 2 2006.201.17:29:43.38#ibcon#enter sib2, iclass 11, count 2 2006.201.17:29:43.38#ibcon#flushed, iclass 11, count 2 2006.201.17:29:43.38#ibcon#about to write, iclass 11, count 2 2006.201.17:29:43.38#ibcon#wrote, iclass 11, count 2 2006.201.17:29:43.38#ibcon#about to read 3, iclass 11, count 2 2006.201.17:29:43.41#ibcon#read 3, iclass 11, count 2 2006.201.17:29:43.41#ibcon#about to read 4, iclass 11, count 2 2006.201.17:29:43.41#ibcon#read 4, iclass 11, count 2 2006.201.17:29:43.41#ibcon#about to read 5, iclass 11, count 2 2006.201.17:29:43.41#ibcon#read 5, iclass 11, count 2 2006.201.17:29:43.41#ibcon#about to read 6, iclass 11, count 2 2006.201.17:29:43.41#ibcon#read 6, iclass 11, count 2 2006.201.17:29:43.41#ibcon#end of sib2, iclass 11, count 2 2006.201.17:29:43.41#ibcon#*after write, iclass 11, count 2 2006.201.17:29:43.41#ibcon#*before return 0, iclass 11, count 2 2006.201.17:29:43.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:29:43.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:29:43.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.17:29:43.41#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:43.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:29:43.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:29:43.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:29:43.53#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:29:43.53#ibcon#first serial, iclass 11, count 0 2006.201.17:29:43.53#ibcon#enter sib2, iclass 11, count 0 2006.201.17:29:43.53#ibcon#flushed, iclass 11, count 0 2006.201.17:29:43.53#ibcon#about to write, iclass 11, count 0 2006.201.17:29:43.53#ibcon#wrote, iclass 11, count 0 2006.201.17:29:43.53#ibcon#about to read 3, iclass 11, count 0 2006.201.17:29:43.55#ibcon#read 3, iclass 11, count 0 2006.201.17:29:43.55#ibcon#about to read 4, iclass 11, count 0 2006.201.17:29:43.55#ibcon#read 4, iclass 11, count 0 2006.201.17:29:43.55#ibcon#about to read 5, iclass 11, count 0 2006.201.17:29:43.55#ibcon#read 5, iclass 11, count 0 2006.201.17:29:43.55#ibcon#about to read 6, iclass 11, count 0 2006.201.17:29:43.55#ibcon#read 6, iclass 11, count 0 2006.201.17:29:43.55#ibcon#end of sib2, iclass 11, count 0 2006.201.17:29:43.55#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:29:43.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:29:43.55#ibcon#[25=USB\r\n] 2006.201.17:29:43.55#ibcon#*before write, iclass 11, count 0 2006.201.17:29:43.55#ibcon#enter sib2, iclass 11, count 0 2006.201.17:29:43.55#ibcon#flushed, iclass 11, count 0 2006.201.17:29:43.55#ibcon#about to write, iclass 11, count 0 2006.201.17:29:43.55#ibcon#wrote, iclass 11, count 0 2006.201.17:29:43.55#ibcon#about to read 3, iclass 11, count 0 2006.201.17:29:43.58#ibcon#read 3, iclass 11, count 0 2006.201.17:29:43.58#ibcon#about to read 4, iclass 11, count 0 2006.201.17:29:43.58#ibcon#read 4, iclass 11, count 0 2006.201.17:29:43.58#ibcon#about to read 5, iclass 11, count 0 2006.201.17:29:43.58#ibcon#read 5, iclass 11, count 0 2006.201.17:29:43.58#ibcon#about to read 6, iclass 11, count 0 2006.201.17:29:43.58#ibcon#read 6, iclass 11, count 0 2006.201.17:29:43.58#ibcon#end of sib2, iclass 11, count 0 2006.201.17:29:43.58#ibcon#*after write, iclass 11, count 0 2006.201.17:29:43.58#ibcon#*before return 0, iclass 11, count 0 2006.201.17:29:43.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:29:43.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:29:43.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:29:43.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:29:43.58$vck44/vblo=1,629.99 2006.201.17:29:43.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.17:29:43.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.17:29:43.58#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:43.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:29:43.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:29:43.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:29:43.58#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:29:43.58#ibcon#first serial, iclass 13, count 0 2006.201.17:29:43.58#ibcon#enter sib2, iclass 13, count 0 2006.201.17:29:43.58#ibcon#flushed, iclass 13, count 0 2006.201.17:29:43.58#ibcon#about to write, iclass 13, count 0 2006.201.17:29:43.58#ibcon#wrote, iclass 13, count 0 2006.201.17:29:43.58#ibcon#about to read 3, iclass 13, count 0 2006.201.17:29:43.60#ibcon#read 3, iclass 13, count 0 2006.201.17:29:43.60#ibcon#about to read 4, iclass 13, count 0 2006.201.17:29:43.60#ibcon#read 4, iclass 13, count 0 2006.201.17:29:43.60#ibcon#about to read 5, iclass 13, count 0 2006.201.17:29:43.60#ibcon#read 5, iclass 13, count 0 2006.201.17:29:43.60#ibcon#about to read 6, iclass 13, count 0 2006.201.17:29:43.60#ibcon#read 6, iclass 13, count 0 2006.201.17:29:43.60#ibcon#end of sib2, iclass 13, count 0 2006.201.17:29:43.60#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:29:43.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:29:43.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.17:29:43.60#ibcon#*before write, iclass 13, count 0 2006.201.17:29:43.60#ibcon#enter sib2, iclass 13, count 0 2006.201.17:29:43.60#ibcon#flushed, iclass 13, count 0 2006.201.17:29:43.60#ibcon#about to write, iclass 13, count 0 2006.201.17:29:43.60#ibcon#wrote, iclass 13, count 0 2006.201.17:29:43.60#ibcon#about to read 3, iclass 13, count 0 2006.201.17:29:43.65#ibcon#read 3, iclass 13, count 0 2006.201.17:29:43.65#ibcon#about to read 4, iclass 13, count 0 2006.201.17:29:43.65#ibcon#read 4, iclass 13, count 0 2006.201.17:29:43.65#ibcon#about to read 5, iclass 13, count 0 2006.201.17:29:43.65#ibcon#read 5, iclass 13, count 0 2006.201.17:29:43.65#ibcon#about to read 6, iclass 13, count 0 2006.201.17:29:43.65#ibcon#read 6, iclass 13, count 0 2006.201.17:29:43.65#ibcon#end of sib2, iclass 13, count 0 2006.201.17:29:43.65#ibcon#*after write, iclass 13, count 0 2006.201.17:29:43.65#ibcon#*before return 0, iclass 13, count 0 2006.201.17:29:43.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:29:43.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:29:43.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:29:43.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:29:43.65$vck44/vb=1,4 2006.201.17:29:43.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.17:29:43.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.17:29:43.65#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:43.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:29:43.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:29:43.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:29:43.65#ibcon#enter wrdev, iclass 15, count 2 2006.201.17:29:43.65#ibcon#first serial, iclass 15, count 2 2006.201.17:29:43.65#ibcon#enter sib2, iclass 15, count 2 2006.201.17:29:43.65#ibcon#flushed, iclass 15, count 2 2006.201.17:29:43.65#ibcon#about to write, iclass 15, count 2 2006.201.17:29:43.65#ibcon#wrote, iclass 15, count 2 2006.201.17:29:43.65#ibcon#about to read 3, iclass 15, count 2 2006.201.17:29:43.67#ibcon#read 3, iclass 15, count 2 2006.201.17:29:43.67#ibcon#about to read 4, iclass 15, count 2 2006.201.17:29:43.67#ibcon#read 4, iclass 15, count 2 2006.201.17:29:43.67#ibcon#about to read 5, iclass 15, count 2 2006.201.17:29:43.67#ibcon#read 5, iclass 15, count 2 2006.201.17:29:43.67#ibcon#about to read 6, iclass 15, count 2 2006.201.17:29:43.67#ibcon#read 6, iclass 15, count 2 2006.201.17:29:43.67#ibcon#end of sib2, iclass 15, count 2 2006.201.17:29:43.67#ibcon#*mode == 0, iclass 15, count 2 2006.201.17:29:43.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.17:29:43.67#ibcon#[27=AT01-04\r\n] 2006.201.17:29:43.67#ibcon#*before write, iclass 15, count 2 2006.201.17:29:43.67#ibcon#enter sib2, iclass 15, count 2 2006.201.17:29:43.67#ibcon#flushed, iclass 15, count 2 2006.201.17:29:43.67#ibcon#about to write, iclass 15, count 2 2006.201.17:29:43.67#ibcon#wrote, iclass 15, count 2 2006.201.17:29:43.67#ibcon#about to read 3, iclass 15, count 2 2006.201.17:29:43.70#ibcon#read 3, iclass 15, count 2 2006.201.17:29:43.70#ibcon#about to read 4, iclass 15, count 2 2006.201.17:29:43.70#ibcon#read 4, iclass 15, count 2 2006.201.17:29:43.70#ibcon#about to read 5, iclass 15, count 2 2006.201.17:29:43.70#ibcon#read 5, iclass 15, count 2 2006.201.17:29:43.70#ibcon#about to read 6, iclass 15, count 2 2006.201.17:29:43.70#ibcon#read 6, iclass 15, count 2 2006.201.17:29:43.70#ibcon#end of sib2, iclass 15, count 2 2006.201.17:29:43.70#ibcon#*after write, iclass 15, count 2 2006.201.17:29:43.70#ibcon#*before return 0, iclass 15, count 2 2006.201.17:29:43.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:29:43.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:29:43.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.17:29:43.70#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:43.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:29:43.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:29:43.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:29:43.82#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:29:43.82#ibcon#first serial, iclass 15, count 0 2006.201.17:29:43.82#ibcon#enter sib2, iclass 15, count 0 2006.201.17:29:43.82#ibcon#flushed, iclass 15, count 0 2006.201.17:29:43.82#ibcon#about to write, iclass 15, count 0 2006.201.17:29:43.82#ibcon#wrote, iclass 15, count 0 2006.201.17:29:43.82#ibcon#about to read 3, iclass 15, count 0 2006.201.17:29:43.84#ibcon#read 3, iclass 15, count 0 2006.201.17:29:43.84#ibcon#about to read 4, iclass 15, count 0 2006.201.17:29:43.84#ibcon#read 4, iclass 15, count 0 2006.201.17:29:43.84#ibcon#about to read 5, iclass 15, count 0 2006.201.17:29:43.84#ibcon#read 5, iclass 15, count 0 2006.201.17:29:43.84#ibcon#about to read 6, iclass 15, count 0 2006.201.17:29:43.84#ibcon#read 6, iclass 15, count 0 2006.201.17:29:43.84#ibcon#end of sib2, iclass 15, count 0 2006.201.17:29:43.84#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:29:43.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:29:43.84#ibcon#[27=USB\r\n] 2006.201.17:29:43.84#ibcon#*before write, iclass 15, count 0 2006.201.17:29:43.84#ibcon#enter sib2, iclass 15, count 0 2006.201.17:29:43.84#ibcon#flushed, iclass 15, count 0 2006.201.17:29:43.84#ibcon#about to write, iclass 15, count 0 2006.201.17:29:43.84#ibcon#wrote, iclass 15, count 0 2006.201.17:29:43.84#ibcon#about to read 3, iclass 15, count 0 2006.201.17:29:43.87#ibcon#read 3, iclass 15, count 0 2006.201.17:29:43.87#ibcon#about to read 4, iclass 15, count 0 2006.201.17:29:43.87#ibcon#read 4, iclass 15, count 0 2006.201.17:29:43.87#ibcon#about to read 5, iclass 15, count 0 2006.201.17:29:43.87#ibcon#read 5, iclass 15, count 0 2006.201.17:29:43.87#ibcon#about to read 6, iclass 15, count 0 2006.201.17:29:43.87#ibcon#read 6, iclass 15, count 0 2006.201.17:29:43.87#ibcon#end of sib2, iclass 15, count 0 2006.201.17:29:43.87#ibcon#*after write, iclass 15, count 0 2006.201.17:29:43.87#ibcon#*before return 0, iclass 15, count 0 2006.201.17:29:43.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:29:43.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:29:43.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:29:43.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:29:43.87$vck44/vblo=2,634.99 2006.201.17:29:43.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.17:29:43.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.17:29:43.87#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:43.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:43.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:43.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:43.87#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:29:43.87#ibcon#first serial, iclass 17, count 0 2006.201.17:29:43.87#ibcon#enter sib2, iclass 17, count 0 2006.201.17:29:43.87#ibcon#flushed, iclass 17, count 0 2006.201.17:29:43.87#ibcon#about to write, iclass 17, count 0 2006.201.17:29:43.87#ibcon#wrote, iclass 17, count 0 2006.201.17:29:43.87#ibcon#about to read 3, iclass 17, count 0 2006.201.17:29:43.89#ibcon#read 3, iclass 17, count 0 2006.201.17:29:43.89#ibcon#about to read 4, iclass 17, count 0 2006.201.17:29:43.89#ibcon#read 4, iclass 17, count 0 2006.201.17:29:43.89#ibcon#about to read 5, iclass 17, count 0 2006.201.17:29:43.89#ibcon#read 5, iclass 17, count 0 2006.201.17:29:43.89#ibcon#about to read 6, iclass 17, count 0 2006.201.17:29:43.89#ibcon#read 6, iclass 17, count 0 2006.201.17:29:43.89#ibcon#end of sib2, iclass 17, count 0 2006.201.17:29:43.89#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:29:43.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:29:43.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.17:29:43.89#ibcon#*before write, iclass 17, count 0 2006.201.17:29:43.89#ibcon#enter sib2, iclass 17, count 0 2006.201.17:29:43.89#ibcon#flushed, iclass 17, count 0 2006.201.17:29:43.89#ibcon#about to write, iclass 17, count 0 2006.201.17:29:43.89#ibcon#wrote, iclass 17, count 0 2006.201.17:29:43.89#ibcon#about to read 3, iclass 17, count 0 2006.201.17:29:43.93#ibcon#read 3, iclass 17, count 0 2006.201.17:29:43.93#ibcon#about to read 4, iclass 17, count 0 2006.201.17:29:43.93#ibcon#read 4, iclass 17, count 0 2006.201.17:29:43.93#ibcon#about to read 5, iclass 17, count 0 2006.201.17:29:43.93#ibcon#read 5, iclass 17, count 0 2006.201.17:29:43.93#ibcon#about to read 6, iclass 17, count 0 2006.201.17:29:43.93#ibcon#read 6, iclass 17, count 0 2006.201.17:29:43.93#ibcon#end of sib2, iclass 17, count 0 2006.201.17:29:43.93#ibcon#*after write, iclass 17, count 0 2006.201.17:29:43.93#ibcon#*before return 0, iclass 17, count 0 2006.201.17:29:43.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:43.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:29:43.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:29:43.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:29:43.93$vck44/vb=2,5 2006.201.17:29:43.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.17:29:43.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.17:29:43.93#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:43.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:43.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:43.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:43.99#ibcon#enter wrdev, iclass 19, count 2 2006.201.17:29:43.99#ibcon#first serial, iclass 19, count 2 2006.201.17:29:43.99#ibcon#enter sib2, iclass 19, count 2 2006.201.17:29:43.99#ibcon#flushed, iclass 19, count 2 2006.201.17:29:43.99#ibcon#about to write, iclass 19, count 2 2006.201.17:29:43.99#ibcon#wrote, iclass 19, count 2 2006.201.17:29:43.99#ibcon#about to read 3, iclass 19, count 2 2006.201.17:29:44.01#ibcon#read 3, iclass 19, count 2 2006.201.17:29:44.01#ibcon#about to read 4, iclass 19, count 2 2006.201.17:29:44.01#ibcon#read 4, iclass 19, count 2 2006.201.17:29:44.01#ibcon#about to read 5, iclass 19, count 2 2006.201.17:29:44.01#ibcon#read 5, iclass 19, count 2 2006.201.17:29:44.01#ibcon#about to read 6, iclass 19, count 2 2006.201.17:29:44.01#ibcon#read 6, iclass 19, count 2 2006.201.17:29:44.01#ibcon#end of sib2, iclass 19, count 2 2006.201.17:29:44.01#ibcon#*mode == 0, iclass 19, count 2 2006.201.17:29:44.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.17:29:44.01#ibcon#[27=AT02-05\r\n] 2006.201.17:29:44.01#ibcon#*before write, iclass 19, count 2 2006.201.17:29:44.01#ibcon#enter sib2, iclass 19, count 2 2006.201.17:29:44.01#ibcon#flushed, iclass 19, count 2 2006.201.17:29:44.01#ibcon#about to write, iclass 19, count 2 2006.201.17:29:44.01#ibcon#wrote, iclass 19, count 2 2006.201.17:29:44.01#ibcon#about to read 3, iclass 19, count 2 2006.201.17:29:44.04#ibcon#read 3, iclass 19, count 2 2006.201.17:29:44.04#ibcon#about to read 4, iclass 19, count 2 2006.201.17:29:44.04#ibcon#read 4, iclass 19, count 2 2006.201.17:29:44.04#ibcon#about to read 5, iclass 19, count 2 2006.201.17:29:44.04#ibcon#read 5, iclass 19, count 2 2006.201.17:29:44.04#ibcon#about to read 6, iclass 19, count 2 2006.201.17:29:44.04#ibcon#read 6, iclass 19, count 2 2006.201.17:29:44.04#ibcon#end of sib2, iclass 19, count 2 2006.201.17:29:44.04#ibcon#*after write, iclass 19, count 2 2006.201.17:29:44.04#ibcon#*before return 0, iclass 19, count 2 2006.201.17:29:44.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:44.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:29:44.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.17:29:44.04#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:44.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:44.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:44.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:44.16#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:29:44.16#ibcon#first serial, iclass 19, count 0 2006.201.17:29:44.16#ibcon#enter sib2, iclass 19, count 0 2006.201.17:29:44.16#ibcon#flushed, iclass 19, count 0 2006.201.17:29:44.16#ibcon#about to write, iclass 19, count 0 2006.201.17:29:44.16#ibcon#wrote, iclass 19, count 0 2006.201.17:29:44.16#ibcon#about to read 3, iclass 19, count 0 2006.201.17:29:44.18#ibcon#read 3, iclass 19, count 0 2006.201.17:29:44.18#ibcon#about to read 4, iclass 19, count 0 2006.201.17:29:44.18#ibcon#read 4, iclass 19, count 0 2006.201.17:29:44.18#ibcon#about to read 5, iclass 19, count 0 2006.201.17:29:44.18#ibcon#read 5, iclass 19, count 0 2006.201.17:29:44.18#ibcon#about to read 6, iclass 19, count 0 2006.201.17:29:44.18#ibcon#read 6, iclass 19, count 0 2006.201.17:29:44.18#ibcon#end of sib2, iclass 19, count 0 2006.201.17:29:44.18#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:29:44.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:29:44.18#ibcon#[27=USB\r\n] 2006.201.17:29:44.18#ibcon#*before write, iclass 19, count 0 2006.201.17:29:44.18#ibcon#enter sib2, iclass 19, count 0 2006.201.17:29:44.18#ibcon#flushed, iclass 19, count 0 2006.201.17:29:44.18#ibcon#about to write, iclass 19, count 0 2006.201.17:29:44.18#ibcon#wrote, iclass 19, count 0 2006.201.17:29:44.18#ibcon#about to read 3, iclass 19, count 0 2006.201.17:29:44.21#ibcon#read 3, iclass 19, count 0 2006.201.17:29:44.21#ibcon#about to read 4, iclass 19, count 0 2006.201.17:29:44.21#ibcon#read 4, iclass 19, count 0 2006.201.17:29:44.21#ibcon#about to read 5, iclass 19, count 0 2006.201.17:29:44.21#ibcon#read 5, iclass 19, count 0 2006.201.17:29:44.21#ibcon#about to read 6, iclass 19, count 0 2006.201.17:29:44.21#ibcon#read 6, iclass 19, count 0 2006.201.17:29:44.21#ibcon#end of sib2, iclass 19, count 0 2006.201.17:29:44.21#ibcon#*after write, iclass 19, count 0 2006.201.17:29:44.21#ibcon#*before return 0, iclass 19, count 0 2006.201.17:29:44.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:44.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:29:44.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:29:44.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:29:44.21$vck44/vblo=3,649.99 2006.201.17:29:44.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.17:29:44.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.17:29:44.21#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:44.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:44.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:44.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:44.21#ibcon#enter wrdev, iclass 21, count 0 2006.201.17:29:44.21#ibcon#first serial, iclass 21, count 0 2006.201.17:29:44.21#ibcon#enter sib2, iclass 21, count 0 2006.201.17:29:44.21#ibcon#flushed, iclass 21, count 0 2006.201.17:29:44.21#ibcon#about to write, iclass 21, count 0 2006.201.17:29:44.21#ibcon#wrote, iclass 21, count 0 2006.201.17:29:44.21#ibcon#about to read 3, iclass 21, count 0 2006.201.17:29:44.23#ibcon#read 3, iclass 21, count 0 2006.201.17:29:44.23#ibcon#about to read 4, iclass 21, count 0 2006.201.17:29:44.23#ibcon#read 4, iclass 21, count 0 2006.201.17:29:44.23#ibcon#about to read 5, iclass 21, count 0 2006.201.17:29:44.23#ibcon#read 5, iclass 21, count 0 2006.201.17:29:44.23#ibcon#about to read 6, iclass 21, count 0 2006.201.17:29:44.23#ibcon#read 6, iclass 21, count 0 2006.201.17:29:44.23#ibcon#end of sib2, iclass 21, count 0 2006.201.17:29:44.23#ibcon#*mode == 0, iclass 21, count 0 2006.201.17:29:44.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.17:29:44.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.17:29:44.23#ibcon#*before write, iclass 21, count 0 2006.201.17:29:44.23#ibcon#enter sib2, iclass 21, count 0 2006.201.17:29:44.23#ibcon#flushed, iclass 21, count 0 2006.201.17:29:44.23#ibcon#about to write, iclass 21, count 0 2006.201.17:29:44.23#ibcon#wrote, iclass 21, count 0 2006.201.17:29:44.23#ibcon#about to read 3, iclass 21, count 0 2006.201.17:29:44.27#ibcon#read 3, iclass 21, count 0 2006.201.17:29:44.27#ibcon#about to read 4, iclass 21, count 0 2006.201.17:29:44.27#ibcon#read 4, iclass 21, count 0 2006.201.17:29:44.27#ibcon#about to read 5, iclass 21, count 0 2006.201.17:29:44.27#ibcon#read 5, iclass 21, count 0 2006.201.17:29:44.27#ibcon#about to read 6, iclass 21, count 0 2006.201.17:29:44.27#ibcon#read 6, iclass 21, count 0 2006.201.17:29:44.27#ibcon#end of sib2, iclass 21, count 0 2006.201.17:29:44.27#ibcon#*after write, iclass 21, count 0 2006.201.17:29:44.27#ibcon#*before return 0, iclass 21, count 0 2006.201.17:29:44.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:44.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:29:44.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.17:29:44.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.17:29:44.27$vck44/vb=3,4 2006.201.17:29:44.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.17:29:44.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.17:29:44.27#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:44.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:44.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:44.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:44.33#ibcon#enter wrdev, iclass 23, count 2 2006.201.17:29:44.33#ibcon#first serial, iclass 23, count 2 2006.201.17:29:44.33#ibcon#enter sib2, iclass 23, count 2 2006.201.17:29:44.33#ibcon#flushed, iclass 23, count 2 2006.201.17:29:44.33#ibcon#about to write, iclass 23, count 2 2006.201.17:29:44.33#ibcon#wrote, iclass 23, count 2 2006.201.17:29:44.33#ibcon#about to read 3, iclass 23, count 2 2006.201.17:29:44.35#ibcon#read 3, iclass 23, count 2 2006.201.17:29:44.35#ibcon#about to read 4, iclass 23, count 2 2006.201.17:29:44.35#ibcon#read 4, iclass 23, count 2 2006.201.17:29:44.35#ibcon#about to read 5, iclass 23, count 2 2006.201.17:29:44.35#ibcon#read 5, iclass 23, count 2 2006.201.17:29:44.35#ibcon#about to read 6, iclass 23, count 2 2006.201.17:29:44.35#ibcon#read 6, iclass 23, count 2 2006.201.17:29:44.35#ibcon#end of sib2, iclass 23, count 2 2006.201.17:29:44.35#ibcon#*mode == 0, iclass 23, count 2 2006.201.17:29:44.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.17:29:44.35#ibcon#[27=AT03-04\r\n] 2006.201.17:29:44.35#ibcon#*before write, iclass 23, count 2 2006.201.17:29:44.35#ibcon#enter sib2, iclass 23, count 2 2006.201.17:29:44.35#ibcon#flushed, iclass 23, count 2 2006.201.17:29:44.35#ibcon#about to write, iclass 23, count 2 2006.201.17:29:44.35#ibcon#wrote, iclass 23, count 2 2006.201.17:29:44.35#ibcon#about to read 3, iclass 23, count 2 2006.201.17:29:44.38#ibcon#read 3, iclass 23, count 2 2006.201.17:29:44.38#ibcon#about to read 4, iclass 23, count 2 2006.201.17:29:44.38#ibcon#read 4, iclass 23, count 2 2006.201.17:29:44.38#ibcon#about to read 5, iclass 23, count 2 2006.201.17:29:44.38#ibcon#read 5, iclass 23, count 2 2006.201.17:29:44.38#ibcon#about to read 6, iclass 23, count 2 2006.201.17:29:44.38#ibcon#read 6, iclass 23, count 2 2006.201.17:29:44.38#ibcon#end of sib2, iclass 23, count 2 2006.201.17:29:44.38#ibcon#*after write, iclass 23, count 2 2006.201.17:29:44.38#ibcon#*before return 0, iclass 23, count 2 2006.201.17:29:44.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:44.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:29:44.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.17:29:44.38#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:44.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:44.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:44.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:44.50#ibcon#enter wrdev, iclass 23, count 0 2006.201.17:29:44.50#ibcon#first serial, iclass 23, count 0 2006.201.17:29:44.50#ibcon#enter sib2, iclass 23, count 0 2006.201.17:29:44.50#ibcon#flushed, iclass 23, count 0 2006.201.17:29:44.50#ibcon#about to write, iclass 23, count 0 2006.201.17:29:44.50#ibcon#wrote, iclass 23, count 0 2006.201.17:29:44.50#ibcon#about to read 3, iclass 23, count 0 2006.201.17:29:44.52#ibcon#read 3, iclass 23, count 0 2006.201.17:29:44.52#ibcon#about to read 4, iclass 23, count 0 2006.201.17:29:44.52#ibcon#read 4, iclass 23, count 0 2006.201.17:29:44.52#ibcon#about to read 5, iclass 23, count 0 2006.201.17:29:44.52#ibcon#read 5, iclass 23, count 0 2006.201.17:29:44.52#ibcon#about to read 6, iclass 23, count 0 2006.201.17:29:44.52#ibcon#read 6, iclass 23, count 0 2006.201.17:29:44.52#ibcon#end of sib2, iclass 23, count 0 2006.201.17:29:44.52#ibcon#*mode == 0, iclass 23, count 0 2006.201.17:29:44.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.17:29:44.52#ibcon#[27=USB\r\n] 2006.201.17:29:44.52#ibcon#*before write, iclass 23, count 0 2006.201.17:29:44.52#ibcon#enter sib2, iclass 23, count 0 2006.201.17:29:44.52#ibcon#flushed, iclass 23, count 0 2006.201.17:29:44.52#ibcon#about to write, iclass 23, count 0 2006.201.17:29:44.52#ibcon#wrote, iclass 23, count 0 2006.201.17:29:44.52#ibcon#about to read 3, iclass 23, count 0 2006.201.17:29:44.55#ibcon#read 3, iclass 23, count 0 2006.201.17:29:44.55#ibcon#about to read 4, iclass 23, count 0 2006.201.17:29:44.55#ibcon#read 4, iclass 23, count 0 2006.201.17:29:44.55#ibcon#about to read 5, iclass 23, count 0 2006.201.17:29:44.55#ibcon#read 5, iclass 23, count 0 2006.201.17:29:44.55#ibcon#about to read 6, iclass 23, count 0 2006.201.17:29:44.55#ibcon#read 6, iclass 23, count 0 2006.201.17:29:44.55#ibcon#end of sib2, iclass 23, count 0 2006.201.17:29:44.55#ibcon#*after write, iclass 23, count 0 2006.201.17:29:44.55#ibcon#*before return 0, iclass 23, count 0 2006.201.17:29:44.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:44.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:29:44.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.17:29:44.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.17:29:44.55$vck44/vblo=4,679.99 2006.201.17:29:44.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.17:29:44.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.17:29:44.55#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:44.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:44.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:44.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:44.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:29:44.55#ibcon#first serial, iclass 25, count 0 2006.201.17:29:44.55#ibcon#enter sib2, iclass 25, count 0 2006.201.17:29:44.55#ibcon#flushed, iclass 25, count 0 2006.201.17:29:44.55#ibcon#about to write, iclass 25, count 0 2006.201.17:29:44.55#ibcon#wrote, iclass 25, count 0 2006.201.17:29:44.55#ibcon#about to read 3, iclass 25, count 0 2006.201.17:29:44.57#ibcon#read 3, iclass 25, count 0 2006.201.17:29:44.57#ibcon#about to read 4, iclass 25, count 0 2006.201.17:29:44.57#ibcon#read 4, iclass 25, count 0 2006.201.17:29:44.57#ibcon#about to read 5, iclass 25, count 0 2006.201.17:29:44.57#ibcon#read 5, iclass 25, count 0 2006.201.17:29:44.57#ibcon#about to read 6, iclass 25, count 0 2006.201.17:29:44.57#ibcon#read 6, iclass 25, count 0 2006.201.17:29:44.57#ibcon#end of sib2, iclass 25, count 0 2006.201.17:29:44.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:29:44.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:29:44.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.17:29:44.57#ibcon#*before write, iclass 25, count 0 2006.201.17:29:44.57#ibcon#enter sib2, iclass 25, count 0 2006.201.17:29:44.57#ibcon#flushed, iclass 25, count 0 2006.201.17:29:44.57#ibcon#about to write, iclass 25, count 0 2006.201.17:29:44.57#ibcon#wrote, iclass 25, count 0 2006.201.17:29:44.57#ibcon#about to read 3, iclass 25, count 0 2006.201.17:29:44.62#ibcon#read 3, iclass 25, count 0 2006.201.17:29:44.62#ibcon#about to read 4, iclass 25, count 0 2006.201.17:29:44.62#ibcon#read 4, iclass 25, count 0 2006.201.17:29:44.62#ibcon#about to read 5, iclass 25, count 0 2006.201.17:29:44.62#ibcon#read 5, iclass 25, count 0 2006.201.17:29:44.62#ibcon#about to read 6, iclass 25, count 0 2006.201.17:29:44.62#ibcon#read 6, iclass 25, count 0 2006.201.17:29:44.62#ibcon#end of sib2, iclass 25, count 0 2006.201.17:29:44.62#ibcon#*after write, iclass 25, count 0 2006.201.17:29:44.62#ibcon#*before return 0, iclass 25, count 0 2006.201.17:29:44.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:44.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:29:44.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:29:44.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:29:44.62$vck44/vb=4,5 2006.201.17:29:44.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.17:29:44.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.17:29:44.62#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:44.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:44.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:44.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:44.67#ibcon#enter wrdev, iclass 27, count 2 2006.201.17:29:44.67#ibcon#first serial, iclass 27, count 2 2006.201.17:29:44.67#ibcon#enter sib2, iclass 27, count 2 2006.201.17:29:44.67#ibcon#flushed, iclass 27, count 2 2006.201.17:29:44.67#ibcon#about to write, iclass 27, count 2 2006.201.17:29:44.67#ibcon#wrote, iclass 27, count 2 2006.201.17:29:44.67#ibcon#about to read 3, iclass 27, count 2 2006.201.17:29:44.69#ibcon#read 3, iclass 27, count 2 2006.201.17:29:44.69#ibcon#about to read 4, iclass 27, count 2 2006.201.17:29:44.69#ibcon#read 4, iclass 27, count 2 2006.201.17:29:44.69#ibcon#about to read 5, iclass 27, count 2 2006.201.17:29:44.69#ibcon#read 5, iclass 27, count 2 2006.201.17:29:44.69#ibcon#about to read 6, iclass 27, count 2 2006.201.17:29:44.69#ibcon#read 6, iclass 27, count 2 2006.201.17:29:44.69#ibcon#end of sib2, iclass 27, count 2 2006.201.17:29:44.69#ibcon#*mode == 0, iclass 27, count 2 2006.201.17:29:44.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.17:29:44.69#ibcon#[27=AT04-05\r\n] 2006.201.17:29:44.69#ibcon#*before write, iclass 27, count 2 2006.201.17:29:44.69#ibcon#enter sib2, iclass 27, count 2 2006.201.17:29:44.69#ibcon#flushed, iclass 27, count 2 2006.201.17:29:44.69#ibcon#about to write, iclass 27, count 2 2006.201.17:29:44.69#ibcon#wrote, iclass 27, count 2 2006.201.17:29:44.69#ibcon#about to read 3, iclass 27, count 2 2006.201.17:29:44.72#ibcon#read 3, iclass 27, count 2 2006.201.17:29:44.72#ibcon#about to read 4, iclass 27, count 2 2006.201.17:29:44.72#ibcon#read 4, iclass 27, count 2 2006.201.17:29:44.72#ibcon#about to read 5, iclass 27, count 2 2006.201.17:29:44.72#ibcon#read 5, iclass 27, count 2 2006.201.17:29:44.72#ibcon#about to read 6, iclass 27, count 2 2006.201.17:29:44.72#ibcon#read 6, iclass 27, count 2 2006.201.17:29:44.72#ibcon#end of sib2, iclass 27, count 2 2006.201.17:29:44.72#ibcon#*after write, iclass 27, count 2 2006.201.17:29:44.72#ibcon#*before return 0, iclass 27, count 2 2006.201.17:29:44.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:44.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:29:44.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.17:29:44.72#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:44.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:44.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:44.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:44.84#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:29:44.84#ibcon#first serial, iclass 27, count 0 2006.201.17:29:44.84#ibcon#enter sib2, iclass 27, count 0 2006.201.17:29:44.84#ibcon#flushed, iclass 27, count 0 2006.201.17:29:44.84#ibcon#about to write, iclass 27, count 0 2006.201.17:29:44.84#ibcon#wrote, iclass 27, count 0 2006.201.17:29:44.84#ibcon#about to read 3, iclass 27, count 0 2006.201.17:29:44.86#ibcon#read 3, iclass 27, count 0 2006.201.17:29:44.86#ibcon#about to read 4, iclass 27, count 0 2006.201.17:29:44.86#ibcon#read 4, iclass 27, count 0 2006.201.17:29:44.86#ibcon#about to read 5, iclass 27, count 0 2006.201.17:29:44.86#ibcon#read 5, iclass 27, count 0 2006.201.17:29:44.86#ibcon#about to read 6, iclass 27, count 0 2006.201.17:29:44.86#ibcon#read 6, iclass 27, count 0 2006.201.17:29:44.86#ibcon#end of sib2, iclass 27, count 0 2006.201.17:29:44.86#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:29:44.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:29:44.86#ibcon#[27=USB\r\n] 2006.201.17:29:44.86#ibcon#*before write, iclass 27, count 0 2006.201.17:29:44.86#ibcon#enter sib2, iclass 27, count 0 2006.201.17:29:44.86#ibcon#flushed, iclass 27, count 0 2006.201.17:29:44.86#ibcon#about to write, iclass 27, count 0 2006.201.17:29:44.86#ibcon#wrote, iclass 27, count 0 2006.201.17:29:44.86#ibcon#about to read 3, iclass 27, count 0 2006.201.17:29:44.89#ibcon#read 3, iclass 27, count 0 2006.201.17:29:44.89#ibcon#about to read 4, iclass 27, count 0 2006.201.17:29:44.89#ibcon#read 4, iclass 27, count 0 2006.201.17:29:44.89#ibcon#about to read 5, iclass 27, count 0 2006.201.17:29:44.89#ibcon#read 5, iclass 27, count 0 2006.201.17:29:44.89#ibcon#about to read 6, iclass 27, count 0 2006.201.17:29:44.89#ibcon#read 6, iclass 27, count 0 2006.201.17:29:44.89#ibcon#end of sib2, iclass 27, count 0 2006.201.17:29:44.89#ibcon#*after write, iclass 27, count 0 2006.201.17:29:44.89#ibcon#*before return 0, iclass 27, count 0 2006.201.17:29:44.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:44.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:29:44.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:29:44.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:29:44.89$vck44/vblo=5,709.99 2006.201.17:29:44.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.17:29:44.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.17:29:44.89#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:44.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:44.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:44.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:44.89#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:29:44.89#ibcon#first serial, iclass 29, count 0 2006.201.17:29:44.89#ibcon#enter sib2, iclass 29, count 0 2006.201.17:29:44.89#ibcon#flushed, iclass 29, count 0 2006.201.17:29:44.89#ibcon#about to write, iclass 29, count 0 2006.201.17:29:44.89#ibcon#wrote, iclass 29, count 0 2006.201.17:29:44.89#ibcon#about to read 3, iclass 29, count 0 2006.201.17:29:44.91#ibcon#read 3, iclass 29, count 0 2006.201.17:29:44.91#ibcon#about to read 4, iclass 29, count 0 2006.201.17:29:44.91#ibcon#read 4, iclass 29, count 0 2006.201.17:29:44.91#ibcon#about to read 5, iclass 29, count 0 2006.201.17:29:44.91#ibcon#read 5, iclass 29, count 0 2006.201.17:29:44.91#ibcon#about to read 6, iclass 29, count 0 2006.201.17:29:44.91#ibcon#read 6, iclass 29, count 0 2006.201.17:29:44.91#ibcon#end of sib2, iclass 29, count 0 2006.201.17:29:44.91#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:29:44.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:29:44.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.17:29:44.91#ibcon#*before write, iclass 29, count 0 2006.201.17:29:44.91#ibcon#enter sib2, iclass 29, count 0 2006.201.17:29:44.91#ibcon#flushed, iclass 29, count 0 2006.201.17:29:44.91#ibcon#about to write, iclass 29, count 0 2006.201.17:29:44.91#ibcon#wrote, iclass 29, count 0 2006.201.17:29:44.91#ibcon#about to read 3, iclass 29, count 0 2006.201.17:29:44.95#ibcon#read 3, iclass 29, count 0 2006.201.17:29:44.95#ibcon#about to read 4, iclass 29, count 0 2006.201.17:29:44.95#ibcon#read 4, iclass 29, count 0 2006.201.17:29:44.95#ibcon#about to read 5, iclass 29, count 0 2006.201.17:29:44.95#ibcon#read 5, iclass 29, count 0 2006.201.17:29:44.95#ibcon#about to read 6, iclass 29, count 0 2006.201.17:29:44.95#ibcon#read 6, iclass 29, count 0 2006.201.17:29:44.95#ibcon#end of sib2, iclass 29, count 0 2006.201.17:29:44.95#ibcon#*after write, iclass 29, count 0 2006.201.17:29:44.95#ibcon#*before return 0, iclass 29, count 0 2006.201.17:29:44.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:44.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:29:44.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:29:44.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:29:44.95$vck44/vb=5,4 2006.201.17:29:44.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.17:29:44.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.17:29:44.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:44.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:45.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:45.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:45.01#ibcon#enter wrdev, iclass 31, count 2 2006.201.17:29:45.01#ibcon#first serial, iclass 31, count 2 2006.201.17:29:45.01#ibcon#enter sib2, iclass 31, count 2 2006.201.17:29:45.01#ibcon#flushed, iclass 31, count 2 2006.201.17:29:45.01#ibcon#about to write, iclass 31, count 2 2006.201.17:29:45.01#ibcon#wrote, iclass 31, count 2 2006.201.17:29:45.01#ibcon#about to read 3, iclass 31, count 2 2006.201.17:29:45.03#ibcon#read 3, iclass 31, count 2 2006.201.17:29:45.03#ibcon#about to read 4, iclass 31, count 2 2006.201.17:29:45.03#ibcon#read 4, iclass 31, count 2 2006.201.17:29:45.03#ibcon#about to read 5, iclass 31, count 2 2006.201.17:29:45.03#ibcon#read 5, iclass 31, count 2 2006.201.17:29:45.03#ibcon#about to read 6, iclass 31, count 2 2006.201.17:29:45.03#ibcon#read 6, iclass 31, count 2 2006.201.17:29:45.03#ibcon#end of sib2, iclass 31, count 2 2006.201.17:29:45.03#ibcon#*mode == 0, iclass 31, count 2 2006.201.17:29:45.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.17:29:45.03#ibcon#[27=AT05-04\r\n] 2006.201.17:29:45.03#ibcon#*before write, iclass 31, count 2 2006.201.17:29:45.03#ibcon#enter sib2, iclass 31, count 2 2006.201.17:29:45.03#ibcon#flushed, iclass 31, count 2 2006.201.17:29:45.03#ibcon#about to write, iclass 31, count 2 2006.201.17:29:45.03#ibcon#wrote, iclass 31, count 2 2006.201.17:29:45.03#ibcon#about to read 3, iclass 31, count 2 2006.201.17:29:45.06#ibcon#read 3, iclass 31, count 2 2006.201.17:29:45.06#ibcon#about to read 4, iclass 31, count 2 2006.201.17:29:45.06#ibcon#read 4, iclass 31, count 2 2006.201.17:29:45.06#ibcon#about to read 5, iclass 31, count 2 2006.201.17:29:45.06#ibcon#read 5, iclass 31, count 2 2006.201.17:29:45.06#ibcon#about to read 6, iclass 31, count 2 2006.201.17:29:45.06#ibcon#read 6, iclass 31, count 2 2006.201.17:29:45.06#ibcon#end of sib2, iclass 31, count 2 2006.201.17:29:45.06#ibcon#*after write, iclass 31, count 2 2006.201.17:29:45.06#ibcon#*before return 0, iclass 31, count 2 2006.201.17:29:45.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:45.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:29:45.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.17:29:45.06#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:45.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:45.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:45.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:45.18#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:29:45.18#ibcon#first serial, iclass 31, count 0 2006.201.17:29:45.18#ibcon#enter sib2, iclass 31, count 0 2006.201.17:29:45.18#ibcon#flushed, iclass 31, count 0 2006.201.17:29:45.18#ibcon#about to write, iclass 31, count 0 2006.201.17:29:45.18#ibcon#wrote, iclass 31, count 0 2006.201.17:29:45.18#ibcon#about to read 3, iclass 31, count 0 2006.201.17:29:45.20#ibcon#read 3, iclass 31, count 0 2006.201.17:29:45.20#ibcon#about to read 4, iclass 31, count 0 2006.201.17:29:45.20#ibcon#read 4, iclass 31, count 0 2006.201.17:29:45.20#ibcon#about to read 5, iclass 31, count 0 2006.201.17:29:45.20#ibcon#read 5, iclass 31, count 0 2006.201.17:29:45.20#ibcon#about to read 6, iclass 31, count 0 2006.201.17:29:45.20#ibcon#read 6, iclass 31, count 0 2006.201.17:29:45.20#ibcon#end of sib2, iclass 31, count 0 2006.201.17:29:45.20#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:29:45.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:29:45.20#ibcon#[27=USB\r\n] 2006.201.17:29:45.20#ibcon#*before write, iclass 31, count 0 2006.201.17:29:45.20#ibcon#enter sib2, iclass 31, count 0 2006.201.17:29:45.20#ibcon#flushed, iclass 31, count 0 2006.201.17:29:45.20#ibcon#about to write, iclass 31, count 0 2006.201.17:29:45.20#ibcon#wrote, iclass 31, count 0 2006.201.17:29:45.20#ibcon#about to read 3, iclass 31, count 0 2006.201.17:29:45.23#ibcon#read 3, iclass 31, count 0 2006.201.17:29:45.23#ibcon#about to read 4, iclass 31, count 0 2006.201.17:29:45.23#ibcon#read 4, iclass 31, count 0 2006.201.17:29:45.23#ibcon#about to read 5, iclass 31, count 0 2006.201.17:29:45.23#ibcon#read 5, iclass 31, count 0 2006.201.17:29:45.23#ibcon#about to read 6, iclass 31, count 0 2006.201.17:29:45.23#ibcon#read 6, iclass 31, count 0 2006.201.17:29:45.23#ibcon#end of sib2, iclass 31, count 0 2006.201.17:29:45.23#ibcon#*after write, iclass 31, count 0 2006.201.17:29:45.23#ibcon#*before return 0, iclass 31, count 0 2006.201.17:29:45.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:45.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:29:45.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:29:45.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:29:45.23$vck44/vblo=6,719.99 2006.201.17:29:45.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.17:29:45.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.17:29:45.23#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:45.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:45.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:45.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:45.23#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:29:45.23#ibcon#first serial, iclass 33, count 0 2006.201.17:29:45.23#ibcon#enter sib2, iclass 33, count 0 2006.201.17:29:45.23#ibcon#flushed, iclass 33, count 0 2006.201.17:29:45.23#ibcon#about to write, iclass 33, count 0 2006.201.17:29:45.23#ibcon#wrote, iclass 33, count 0 2006.201.17:29:45.23#ibcon#about to read 3, iclass 33, count 0 2006.201.17:29:45.25#ibcon#read 3, iclass 33, count 0 2006.201.17:29:45.25#ibcon#about to read 4, iclass 33, count 0 2006.201.17:29:45.25#ibcon#read 4, iclass 33, count 0 2006.201.17:29:45.25#ibcon#about to read 5, iclass 33, count 0 2006.201.17:29:45.25#ibcon#read 5, iclass 33, count 0 2006.201.17:29:45.25#ibcon#about to read 6, iclass 33, count 0 2006.201.17:29:45.25#ibcon#read 6, iclass 33, count 0 2006.201.17:29:45.25#ibcon#end of sib2, iclass 33, count 0 2006.201.17:29:45.25#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:29:45.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:29:45.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.17:29:45.25#ibcon#*before write, iclass 33, count 0 2006.201.17:29:45.25#ibcon#enter sib2, iclass 33, count 0 2006.201.17:29:45.25#ibcon#flushed, iclass 33, count 0 2006.201.17:29:45.25#ibcon#about to write, iclass 33, count 0 2006.201.17:29:45.25#ibcon#wrote, iclass 33, count 0 2006.201.17:29:45.25#ibcon#about to read 3, iclass 33, count 0 2006.201.17:29:45.29#ibcon#read 3, iclass 33, count 0 2006.201.17:29:45.29#ibcon#about to read 4, iclass 33, count 0 2006.201.17:29:45.29#ibcon#read 4, iclass 33, count 0 2006.201.17:29:45.29#ibcon#about to read 5, iclass 33, count 0 2006.201.17:29:45.29#ibcon#read 5, iclass 33, count 0 2006.201.17:29:45.29#ibcon#about to read 6, iclass 33, count 0 2006.201.17:29:45.29#ibcon#read 6, iclass 33, count 0 2006.201.17:29:45.29#ibcon#end of sib2, iclass 33, count 0 2006.201.17:29:45.29#ibcon#*after write, iclass 33, count 0 2006.201.17:29:45.29#ibcon#*before return 0, iclass 33, count 0 2006.201.17:29:45.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:45.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:29:45.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:29:45.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:29:45.29$vck44/vb=6,4 2006.201.17:29:45.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.17:29:45.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.17:29:45.29#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:45.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:45.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:45.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:45.35#ibcon#enter wrdev, iclass 35, count 2 2006.201.17:29:45.35#ibcon#first serial, iclass 35, count 2 2006.201.17:29:45.35#ibcon#enter sib2, iclass 35, count 2 2006.201.17:29:45.35#ibcon#flushed, iclass 35, count 2 2006.201.17:29:45.35#ibcon#about to write, iclass 35, count 2 2006.201.17:29:45.35#ibcon#wrote, iclass 35, count 2 2006.201.17:29:45.35#ibcon#about to read 3, iclass 35, count 2 2006.201.17:29:45.37#ibcon#read 3, iclass 35, count 2 2006.201.17:29:45.37#ibcon#about to read 4, iclass 35, count 2 2006.201.17:29:45.37#ibcon#read 4, iclass 35, count 2 2006.201.17:29:45.37#ibcon#about to read 5, iclass 35, count 2 2006.201.17:29:45.37#ibcon#read 5, iclass 35, count 2 2006.201.17:29:45.37#ibcon#about to read 6, iclass 35, count 2 2006.201.17:29:45.37#ibcon#read 6, iclass 35, count 2 2006.201.17:29:45.37#ibcon#end of sib2, iclass 35, count 2 2006.201.17:29:45.37#ibcon#*mode == 0, iclass 35, count 2 2006.201.17:29:45.37#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.17:29:45.37#ibcon#[27=AT06-04\r\n] 2006.201.17:29:45.37#ibcon#*before write, iclass 35, count 2 2006.201.17:29:45.37#ibcon#enter sib2, iclass 35, count 2 2006.201.17:29:45.37#ibcon#flushed, iclass 35, count 2 2006.201.17:29:45.37#ibcon#about to write, iclass 35, count 2 2006.201.17:29:45.37#ibcon#wrote, iclass 35, count 2 2006.201.17:29:45.37#ibcon#about to read 3, iclass 35, count 2 2006.201.17:29:45.40#ibcon#read 3, iclass 35, count 2 2006.201.17:29:45.40#ibcon#about to read 4, iclass 35, count 2 2006.201.17:29:45.40#ibcon#read 4, iclass 35, count 2 2006.201.17:29:45.40#ibcon#about to read 5, iclass 35, count 2 2006.201.17:29:45.40#ibcon#read 5, iclass 35, count 2 2006.201.17:29:45.40#ibcon#about to read 6, iclass 35, count 2 2006.201.17:29:45.40#ibcon#read 6, iclass 35, count 2 2006.201.17:29:45.40#ibcon#end of sib2, iclass 35, count 2 2006.201.17:29:45.40#ibcon#*after write, iclass 35, count 2 2006.201.17:29:45.40#ibcon#*before return 0, iclass 35, count 2 2006.201.17:29:45.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:45.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:29:45.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.17:29:45.40#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:45.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:45.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:45.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:45.52#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:29:45.52#ibcon#first serial, iclass 35, count 0 2006.201.17:29:45.52#ibcon#enter sib2, iclass 35, count 0 2006.201.17:29:45.52#ibcon#flushed, iclass 35, count 0 2006.201.17:29:45.52#ibcon#about to write, iclass 35, count 0 2006.201.17:29:45.52#ibcon#wrote, iclass 35, count 0 2006.201.17:29:45.52#ibcon#about to read 3, iclass 35, count 0 2006.201.17:29:45.54#ibcon#read 3, iclass 35, count 0 2006.201.17:29:45.54#ibcon#about to read 4, iclass 35, count 0 2006.201.17:29:45.54#ibcon#read 4, iclass 35, count 0 2006.201.17:29:45.54#ibcon#about to read 5, iclass 35, count 0 2006.201.17:29:45.54#ibcon#read 5, iclass 35, count 0 2006.201.17:29:45.54#ibcon#about to read 6, iclass 35, count 0 2006.201.17:29:45.54#ibcon#read 6, iclass 35, count 0 2006.201.17:29:45.54#ibcon#end of sib2, iclass 35, count 0 2006.201.17:29:45.54#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:29:45.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:29:45.54#ibcon#[27=USB\r\n] 2006.201.17:29:45.54#ibcon#*before write, iclass 35, count 0 2006.201.17:29:45.54#ibcon#enter sib2, iclass 35, count 0 2006.201.17:29:45.54#ibcon#flushed, iclass 35, count 0 2006.201.17:29:45.54#ibcon#about to write, iclass 35, count 0 2006.201.17:29:45.54#ibcon#wrote, iclass 35, count 0 2006.201.17:29:45.54#ibcon#about to read 3, iclass 35, count 0 2006.201.17:29:45.57#ibcon#read 3, iclass 35, count 0 2006.201.17:29:45.57#ibcon#about to read 4, iclass 35, count 0 2006.201.17:29:45.57#ibcon#read 4, iclass 35, count 0 2006.201.17:29:45.57#ibcon#about to read 5, iclass 35, count 0 2006.201.17:29:45.57#ibcon#read 5, iclass 35, count 0 2006.201.17:29:45.57#ibcon#about to read 6, iclass 35, count 0 2006.201.17:29:45.57#ibcon#read 6, iclass 35, count 0 2006.201.17:29:45.57#ibcon#end of sib2, iclass 35, count 0 2006.201.17:29:45.57#ibcon#*after write, iclass 35, count 0 2006.201.17:29:45.57#ibcon#*before return 0, iclass 35, count 0 2006.201.17:29:45.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:45.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:29:45.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:29:45.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:29:45.57$vck44/vblo=7,734.99 2006.201.17:29:45.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.17:29:45.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.17:29:45.57#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:45.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:45.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:45.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:45.57#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:29:45.57#ibcon#first serial, iclass 37, count 0 2006.201.17:29:45.57#ibcon#enter sib2, iclass 37, count 0 2006.201.17:29:45.57#ibcon#flushed, iclass 37, count 0 2006.201.17:29:45.57#ibcon#about to write, iclass 37, count 0 2006.201.17:29:45.57#ibcon#wrote, iclass 37, count 0 2006.201.17:29:45.57#ibcon#about to read 3, iclass 37, count 0 2006.201.17:29:45.59#ibcon#read 3, iclass 37, count 0 2006.201.17:29:45.59#ibcon#about to read 4, iclass 37, count 0 2006.201.17:29:45.59#ibcon#read 4, iclass 37, count 0 2006.201.17:29:45.59#ibcon#about to read 5, iclass 37, count 0 2006.201.17:29:45.59#ibcon#read 5, iclass 37, count 0 2006.201.17:29:45.59#ibcon#about to read 6, iclass 37, count 0 2006.201.17:29:45.59#ibcon#read 6, iclass 37, count 0 2006.201.17:29:45.59#ibcon#end of sib2, iclass 37, count 0 2006.201.17:29:45.59#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:29:45.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:29:45.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.17:29:45.59#ibcon#*before write, iclass 37, count 0 2006.201.17:29:45.59#ibcon#enter sib2, iclass 37, count 0 2006.201.17:29:45.59#ibcon#flushed, iclass 37, count 0 2006.201.17:29:45.59#ibcon#about to write, iclass 37, count 0 2006.201.17:29:45.59#ibcon#wrote, iclass 37, count 0 2006.201.17:29:45.59#ibcon#about to read 3, iclass 37, count 0 2006.201.17:29:45.64#ibcon#read 3, iclass 37, count 0 2006.201.17:29:45.64#ibcon#about to read 4, iclass 37, count 0 2006.201.17:29:45.64#ibcon#read 4, iclass 37, count 0 2006.201.17:29:45.64#ibcon#about to read 5, iclass 37, count 0 2006.201.17:29:45.64#ibcon#read 5, iclass 37, count 0 2006.201.17:29:45.64#ibcon#about to read 6, iclass 37, count 0 2006.201.17:29:45.64#ibcon#read 6, iclass 37, count 0 2006.201.17:29:45.64#ibcon#end of sib2, iclass 37, count 0 2006.201.17:29:45.64#ibcon#*after write, iclass 37, count 0 2006.201.17:29:45.64#ibcon#*before return 0, iclass 37, count 0 2006.201.17:29:45.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:45.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:29:45.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:29:45.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:29:45.64$vck44/vb=7,4 2006.201.17:29:45.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.17:29:45.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.17:29:45.64#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:45.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:45.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:45.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:45.69#ibcon#enter wrdev, iclass 39, count 2 2006.201.17:29:45.69#ibcon#first serial, iclass 39, count 2 2006.201.17:29:45.69#ibcon#enter sib2, iclass 39, count 2 2006.201.17:29:45.69#ibcon#flushed, iclass 39, count 2 2006.201.17:29:45.69#ibcon#about to write, iclass 39, count 2 2006.201.17:29:45.69#ibcon#wrote, iclass 39, count 2 2006.201.17:29:45.69#ibcon#about to read 3, iclass 39, count 2 2006.201.17:29:45.71#ibcon#read 3, iclass 39, count 2 2006.201.17:29:45.71#ibcon#about to read 4, iclass 39, count 2 2006.201.17:29:45.71#ibcon#read 4, iclass 39, count 2 2006.201.17:29:45.71#ibcon#about to read 5, iclass 39, count 2 2006.201.17:29:45.71#ibcon#read 5, iclass 39, count 2 2006.201.17:29:45.71#ibcon#about to read 6, iclass 39, count 2 2006.201.17:29:45.71#ibcon#read 6, iclass 39, count 2 2006.201.17:29:45.71#ibcon#end of sib2, iclass 39, count 2 2006.201.17:29:45.71#ibcon#*mode == 0, iclass 39, count 2 2006.201.17:29:45.71#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.17:29:45.71#ibcon#[27=AT07-04\r\n] 2006.201.17:29:45.71#ibcon#*before write, iclass 39, count 2 2006.201.17:29:45.71#ibcon#enter sib2, iclass 39, count 2 2006.201.17:29:45.71#ibcon#flushed, iclass 39, count 2 2006.201.17:29:45.71#ibcon#about to write, iclass 39, count 2 2006.201.17:29:45.71#ibcon#wrote, iclass 39, count 2 2006.201.17:29:45.71#ibcon#about to read 3, iclass 39, count 2 2006.201.17:29:45.74#ibcon#read 3, iclass 39, count 2 2006.201.17:29:45.74#ibcon#about to read 4, iclass 39, count 2 2006.201.17:29:45.74#ibcon#read 4, iclass 39, count 2 2006.201.17:29:45.74#ibcon#about to read 5, iclass 39, count 2 2006.201.17:29:45.74#ibcon#read 5, iclass 39, count 2 2006.201.17:29:45.74#ibcon#about to read 6, iclass 39, count 2 2006.201.17:29:45.74#ibcon#read 6, iclass 39, count 2 2006.201.17:29:45.74#ibcon#end of sib2, iclass 39, count 2 2006.201.17:29:45.74#ibcon#*after write, iclass 39, count 2 2006.201.17:29:45.74#ibcon#*before return 0, iclass 39, count 2 2006.201.17:29:45.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:45.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:29:45.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.17:29:45.74#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:45.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:45.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:45.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:45.86#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:29:45.86#ibcon#first serial, iclass 39, count 0 2006.201.17:29:45.86#ibcon#enter sib2, iclass 39, count 0 2006.201.17:29:45.86#ibcon#flushed, iclass 39, count 0 2006.201.17:29:45.86#ibcon#about to write, iclass 39, count 0 2006.201.17:29:45.86#ibcon#wrote, iclass 39, count 0 2006.201.17:29:45.86#ibcon#about to read 3, iclass 39, count 0 2006.201.17:29:45.88#ibcon#read 3, iclass 39, count 0 2006.201.17:29:45.88#ibcon#about to read 4, iclass 39, count 0 2006.201.17:29:45.88#ibcon#read 4, iclass 39, count 0 2006.201.17:29:45.88#ibcon#about to read 5, iclass 39, count 0 2006.201.17:29:45.88#ibcon#read 5, iclass 39, count 0 2006.201.17:29:45.88#ibcon#about to read 6, iclass 39, count 0 2006.201.17:29:45.88#ibcon#read 6, iclass 39, count 0 2006.201.17:29:45.88#ibcon#end of sib2, iclass 39, count 0 2006.201.17:29:45.88#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:29:45.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:29:45.88#ibcon#[27=USB\r\n] 2006.201.17:29:45.88#ibcon#*before write, iclass 39, count 0 2006.201.17:29:45.88#ibcon#enter sib2, iclass 39, count 0 2006.201.17:29:45.88#ibcon#flushed, iclass 39, count 0 2006.201.17:29:45.88#ibcon#about to write, iclass 39, count 0 2006.201.17:29:45.88#ibcon#wrote, iclass 39, count 0 2006.201.17:29:45.88#ibcon#about to read 3, iclass 39, count 0 2006.201.17:29:45.91#ibcon#read 3, iclass 39, count 0 2006.201.17:29:45.91#ibcon#about to read 4, iclass 39, count 0 2006.201.17:29:45.91#ibcon#read 4, iclass 39, count 0 2006.201.17:29:45.91#ibcon#about to read 5, iclass 39, count 0 2006.201.17:29:45.91#ibcon#read 5, iclass 39, count 0 2006.201.17:29:45.91#ibcon#about to read 6, iclass 39, count 0 2006.201.17:29:45.91#ibcon#read 6, iclass 39, count 0 2006.201.17:29:45.91#ibcon#end of sib2, iclass 39, count 0 2006.201.17:29:45.91#ibcon#*after write, iclass 39, count 0 2006.201.17:29:45.91#ibcon#*before return 0, iclass 39, count 0 2006.201.17:29:45.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:45.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:29:45.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:29:45.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:29:45.91$vck44/vblo=8,744.99 2006.201.17:29:45.91#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.17:29:45.91#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.17:29:45.91#ibcon#ireg 17 cls_cnt 0 2006.201.17:29:45.91#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:45.91#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:45.91#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:45.91#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:29:45.91#ibcon#first serial, iclass 2, count 0 2006.201.17:29:45.91#ibcon#enter sib2, iclass 2, count 0 2006.201.17:29:45.91#ibcon#flushed, iclass 2, count 0 2006.201.17:29:45.91#ibcon#about to write, iclass 2, count 0 2006.201.17:29:45.91#ibcon#wrote, iclass 2, count 0 2006.201.17:29:45.91#ibcon#about to read 3, iclass 2, count 0 2006.201.17:29:45.93#ibcon#read 3, iclass 2, count 0 2006.201.17:29:45.93#ibcon#about to read 4, iclass 2, count 0 2006.201.17:29:45.93#ibcon#read 4, iclass 2, count 0 2006.201.17:29:45.93#ibcon#about to read 5, iclass 2, count 0 2006.201.17:29:45.93#ibcon#read 5, iclass 2, count 0 2006.201.17:29:45.93#ibcon#about to read 6, iclass 2, count 0 2006.201.17:29:45.93#ibcon#read 6, iclass 2, count 0 2006.201.17:29:45.93#ibcon#end of sib2, iclass 2, count 0 2006.201.17:29:45.93#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:29:45.93#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:29:45.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.17:29:45.93#ibcon#*before write, iclass 2, count 0 2006.201.17:29:45.93#ibcon#enter sib2, iclass 2, count 0 2006.201.17:29:45.93#ibcon#flushed, iclass 2, count 0 2006.201.17:29:45.93#ibcon#about to write, iclass 2, count 0 2006.201.17:29:45.93#ibcon#wrote, iclass 2, count 0 2006.201.17:29:45.93#ibcon#about to read 3, iclass 2, count 0 2006.201.17:29:45.97#ibcon#read 3, iclass 2, count 0 2006.201.17:29:45.97#ibcon#about to read 4, iclass 2, count 0 2006.201.17:29:45.97#ibcon#read 4, iclass 2, count 0 2006.201.17:29:45.97#ibcon#about to read 5, iclass 2, count 0 2006.201.17:29:45.97#ibcon#read 5, iclass 2, count 0 2006.201.17:29:45.97#ibcon#about to read 6, iclass 2, count 0 2006.201.17:29:45.97#ibcon#read 6, iclass 2, count 0 2006.201.17:29:45.97#ibcon#end of sib2, iclass 2, count 0 2006.201.17:29:45.97#ibcon#*after write, iclass 2, count 0 2006.201.17:29:45.97#ibcon#*before return 0, iclass 2, count 0 2006.201.17:29:45.97#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:45.97#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:29:45.97#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:29:45.97#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:29:45.97$vck44/vb=8,4 2006.201.17:29:45.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.17:29:45.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.17:29:45.97#ibcon#ireg 11 cls_cnt 2 2006.201.17:29:45.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:46.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:46.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:46.03#ibcon#enter wrdev, iclass 5, count 2 2006.201.17:29:46.03#ibcon#first serial, iclass 5, count 2 2006.201.17:29:46.03#ibcon#enter sib2, iclass 5, count 2 2006.201.17:29:46.03#ibcon#flushed, iclass 5, count 2 2006.201.17:29:46.03#ibcon#about to write, iclass 5, count 2 2006.201.17:29:46.03#ibcon#wrote, iclass 5, count 2 2006.201.17:29:46.03#ibcon#about to read 3, iclass 5, count 2 2006.201.17:29:46.05#ibcon#read 3, iclass 5, count 2 2006.201.17:29:46.05#ibcon#about to read 4, iclass 5, count 2 2006.201.17:29:46.05#ibcon#read 4, iclass 5, count 2 2006.201.17:29:46.05#ibcon#about to read 5, iclass 5, count 2 2006.201.17:29:46.05#ibcon#read 5, iclass 5, count 2 2006.201.17:29:46.05#ibcon#about to read 6, iclass 5, count 2 2006.201.17:29:46.05#ibcon#read 6, iclass 5, count 2 2006.201.17:29:46.05#ibcon#end of sib2, iclass 5, count 2 2006.201.17:29:46.05#ibcon#*mode == 0, iclass 5, count 2 2006.201.17:29:46.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.17:29:46.05#ibcon#[27=AT08-04\r\n] 2006.201.17:29:46.05#ibcon#*before write, iclass 5, count 2 2006.201.17:29:46.05#ibcon#enter sib2, iclass 5, count 2 2006.201.17:29:46.05#ibcon#flushed, iclass 5, count 2 2006.201.17:29:46.05#ibcon#about to write, iclass 5, count 2 2006.201.17:29:46.05#ibcon#wrote, iclass 5, count 2 2006.201.17:29:46.05#ibcon#about to read 3, iclass 5, count 2 2006.201.17:29:46.08#ibcon#read 3, iclass 5, count 2 2006.201.17:29:46.08#ibcon#about to read 4, iclass 5, count 2 2006.201.17:29:46.08#ibcon#read 4, iclass 5, count 2 2006.201.17:29:46.08#ibcon#about to read 5, iclass 5, count 2 2006.201.17:29:46.08#ibcon#read 5, iclass 5, count 2 2006.201.17:29:46.08#ibcon#about to read 6, iclass 5, count 2 2006.201.17:29:46.08#ibcon#read 6, iclass 5, count 2 2006.201.17:29:46.08#ibcon#end of sib2, iclass 5, count 2 2006.201.17:29:46.08#ibcon#*after write, iclass 5, count 2 2006.201.17:29:46.08#ibcon#*before return 0, iclass 5, count 2 2006.201.17:29:46.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:46.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:29:46.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.17:29:46.08#ibcon#ireg 7 cls_cnt 0 2006.201.17:29:46.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:46.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:46.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:46.20#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:29:46.20#ibcon#first serial, iclass 5, count 0 2006.201.17:29:46.20#ibcon#enter sib2, iclass 5, count 0 2006.201.17:29:46.20#ibcon#flushed, iclass 5, count 0 2006.201.17:29:46.20#ibcon#about to write, iclass 5, count 0 2006.201.17:29:46.20#ibcon#wrote, iclass 5, count 0 2006.201.17:29:46.20#ibcon#about to read 3, iclass 5, count 0 2006.201.17:29:46.22#ibcon#read 3, iclass 5, count 0 2006.201.17:29:46.22#ibcon#about to read 4, iclass 5, count 0 2006.201.17:29:46.22#ibcon#read 4, iclass 5, count 0 2006.201.17:29:46.22#ibcon#about to read 5, iclass 5, count 0 2006.201.17:29:46.22#ibcon#read 5, iclass 5, count 0 2006.201.17:29:46.22#ibcon#about to read 6, iclass 5, count 0 2006.201.17:29:46.22#ibcon#read 6, iclass 5, count 0 2006.201.17:29:46.22#ibcon#end of sib2, iclass 5, count 0 2006.201.17:29:46.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:29:46.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:29:46.22#ibcon#[27=USB\r\n] 2006.201.17:29:46.22#ibcon#*before write, iclass 5, count 0 2006.201.17:29:46.22#ibcon#enter sib2, iclass 5, count 0 2006.201.17:29:46.22#ibcon#flushed, iclass 5, count 0 2006.201.17:29:46.22#ibcon#about to write, iclass 5, count 0 2006.201.17:29:46.22#ibcon#wrote, iclass 5, count 0 2006.201.17:29:46.22#ibcon#about to read 3, iclass 5, count 0 2006.201.17:29:46.25#ibcon#read 3, iclass 5, count 0 2006.201.17:29:46.25#ibcon#about to read 4, iclass 5, count 0 2006.201.17:29:46.25#ibcon#read 4, iclass 5, count 0 2006.201.17:29:46.25#ibcon#about to read 5, iclass 5, count 0 2006.201.17:29:46.25#ibcon#read 5, iclass 5, count 0 2006.201.17:29:46.25#ibcon#about to read 6, iclass 5, count 0 2006.201.17:29:46.25#ibcon#read 6, iclass 5, count 0 2006.201.17:29:46.25#ibcon#end of sib2, iclass 5, count 0 2006.201.17:29:46.25#ibcon#*after write, iclass 5, count 0 2006.201.17:29:46.25#ibcon#*before return 0, iclass 5, count 0 2006.201.17:29:46.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:46.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:29:46.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:29:46.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:29:46.25$vck44/vabw=wide 2006.201.17:29:46.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.17:29:46.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.17:29:46.25#ibcon#ireg 8 cls_cnt 0 2006.201.17:29:46.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:46.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:46.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:46.25#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:29:46.25#ibcon#first serial, iclass 7, count 0 2006.201.17:29:46.25#ibcon#enter sib2, iclass 7, count 0 2006.201.17:29:46.25#ibcon#flushed, iclass 7, count 0 2006.201.17:29:46.25#ibcon#about to write, iclass 7, count 0 2006.201.17:29:46.25#ibcon#wrote, iclass 7, count 0 2006.201.17:29:46.25#ibcon#about to read 3, iclass 7, count 0 2006.201.17:29:46.27#ibcon#read 3, iclass 7, count 0 2006.201.17:29:46.27#ibcon#about to read 4, iclass 7, count 0 2006.201.17:29:46.27#ibcon#read 4, iclass 7, count 0 2006.201.17:29:46.27#ibcon#about to read 5, iclass 7, count 0 2006.201.17:29:46.27#ibcon#read 5, iclass 7, count 0 2006.201.17:29:46.27#ibcon#about to read 6, iclass 7, count 0 2006.201.17:29:46.27#ibcon#read 6, iclass 7, count 0 2006.201.17:29:46.27#ibcon#end of sib2, iclass 7, count 0 2006.201.17:29:46.27#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:29:46.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:29:46.27#ibcon#[25=BW32\r\n] 2006.201.17:29:46.27#ibcon#*before write, iclass 7, count 0 2006.201.17:29:46.27#ibcon#enter sib2, iclass 7, count 0 2006.201.17:29:46.27#ibcon#flushed, iclass 7, count 0 2006.201.17:29:46.27#ibcon#about to write, iclass 7, count 0 2006.201.17:29:46.27#ibcon#wrote, iclass 7, count 0 2006.201.17:29:46.27#ibcon#about to read 3, iclass 7, count 0 2006.201.17:29:46.30#ibcon#read 3, iclass 7, count 0 2006.201.17:29:46.30#ibcon#about to read 4, iclass 7, count 0 2006.201.17:29:46.30#ibcon#read 4, iclass 7, count 0 2006.201.17:29:46.30#ibcon#about to read 5, iclass 7, count 0 2006.201.17:29:46.30#ibcon#read 5, iclass 7, count 0 2006.201.17:29:46.30#ibcon#about to read 6, iclass 7, count 0 2006.201.17:29:46.30#ibcon#read 6, iclass 7, count 0 2006.201.17:29:46.30#ibcon#end of sib2, iclass 7, count 0 2006.201.17:29:46.30#ibcon#*after write, iclass 7, count 0 2006.201.17:29:46.30#ibcon#*before return 0, iclass 7, count 0 2006.201.17:29:46.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:46.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:29:46.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:29:46.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:29:46.30$vck44/vbbw=wide 2006.201.17:29:46.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.17:29:46.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.17:29:46.30#ibcon#ireg 8 cls_cnt 0 2006.201.17:29:46.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:29:46.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:29:46.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:29:46.37#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:29:46.37#ibcon#first serial, iclass 11, count 0 2006.201.17:29:46.37#ibcon#enter sib2, iclass 11, count 0 2006.201.17:29:46.37#ibcon#flushed, iclass 11, count 0 2006.201.17:29:46.37#ibcon#about to write, iclass 11, count 0 2006.201.17:29:46.37#ibcon#wrote, iclass 11, count 0 2006.201.17:29:46.37#ibcon#about to read 3, iclass 11, count 0 2006.201.17:29:46.39#ibcon#read 3, iclass 11, count 0 2006.201.17:29:46.39#ibcon#about to read 4, iclass 11, count 0 2006.201.17:29:46.39#ibcon#read 4, iclass 11, count 0 2006.201.17:29:46.39#ibcon#about to read 5, iclass 11, count 0 2006.201.17:29:46.39#ibcon#read 5, iclass 11, count 0 2006.201.17:29:46.39#ibcon#about to read 6, iclass 11, count 0 2006.201.17:29:46.39#ibcon#read 6, iclass 11, count 0 2006.201.17:29:46.39#ibcon#end of sib2, iclass 11, count 0 2006.201.17:29:46.39#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:29:46.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:29:46.39#ibcon#[27=BW32\r\n] 2006.201.17:29:46.39#ibcon#*before write, iclass 11, count 0 2006.201.17:29:46.39#ibcon#enter sib2, iclass 11, count 0 2006.201.17:29:46.39#ibcon#flushed, iclass 11, count 0 2006.201.17:29:46.39#ibcon#about to write, iclass 11, count 0 2006.201.17:29:46.39#ibcon#wrote, iclass 11, count 0 2006.201.17:29:46.39#ibcon#about to read 3, iclass 11, count 0 2006.201.17:29:46.42#ibcon#read 3, iclass 11, count 0 2006.201.17:29:46.42#ibcon#about to read 4, iclass 11, count 0 2006.201.17:29:46.42#ibcon#read 4, iclass 11, count 0 2006.201.17:29:46.42#ibcon#about to read 5, iclass 11, count 0 2006.201.17:29:46.42#ibcon#read 5, iclass 11, count 0 2006.201.17:29:46.42#ibcon#about to read 6, iclass 11, count 0 2006.201.17:29:46.42#ibcon#read 6, iclass 11, count 0 2006.201.17:29:46.42#ibcon#end of sib2, iclass 11, count 0 2006.201.17:29:46.42#ibcon#*after write, iclass 11, count 0 2006.201.17:29:46.42#ibcon#*before return 0, iclass 11, count 0 2006.201.17:29:46.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:29:46.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:29:46.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:29:46.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:29:46.42$setupk4/ifdk4 2006.201.17:29:46.42$ifdk4/lo= 2006.201.17:29:46.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.17:29:46.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.17:29:46.42$ifdk4/patch= 2006.201.17:29:46.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.17:29:46.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.17:29:46.42$setupk4/!*+20s 2006.201.17:29:49.56#abcon#<5=/00 0.2 0.5 20.731001002.6\r\n> 2006.201.17:29:49.58#abcon#{5=INTERFACE CLEAR} 2006.201.17:29:49.64#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:29:50.14#trakl#Source acquired 2006.201.17:29:51.14#flagr#flagr/antenna,acquired 2006.201.17:29:59.73#abcon#<5=/00 0.2 0.5 20.721001002.6\r\n> 2006.201.17:29:59.75#abcon#{5=INTERFACE CLEAR} 2006.201.17:29:59.81#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:30:00.90$setupk4/"tpicd 2006.201.17:30:00.90$setupk4/echo=off 2006.201.17:30:00.90$setupk4/xlog=off 2006.201.17:30:00.90:!2006.201.17:38:31 2006.201.17:38:31.00:preob 2006.201.17:38:31.14/onsource/TRACKING 2006.201.17:38:31.14:!2006.201.17:38:41 2006.201.17:38:41.00:"tape 2006.201.17:38:41.00:"st=record 2006.201.17:38:41.00:data_valid=on 2006.201.17:38:41.00:midob 2006.201.17:38:42.14/onsource/TRACKING 2006.201.17:38:42.14/wx/20.68,1002.5,100 2006.201.17:38:42.33/cable/+6.4775E-03 2006.201.17:38:43.42/va/01,08,usb,yes,56,60 2006.201.17:38:43.42/va/02,07,usb,yes,60,61 2006.201.17:38:43.42/va/03,08,usb,yes,55,57 2006.201.17:38:43.42/va/04,07,usb,yes,62,65 2006.201.17:38:43.42/va/05,04,usb,yes,55,57 2006.201.17:38:43.42/va/06,05,usb,yes,56,56 2006.201.17:38:43.42/va/07,05,usb,yes,55,56 2006.201.17:38:43.42/va/08,04,usb,yes,54,64 2006.201.17:38:43.65/valo/01,524.99,yes,locked 2006.201.17:38:43.65/valo/02,534.99,yes,locked 2006.201.17:38:43.65/valo/03,564.99,yes,locked 2006.201.17:38:43.65/valo/04,624.99,yes,locked 2006.201.17:38:43.65/valo/05,734.99,yes,locked 2006.201.17:38:43.65/valo/06,814.99,yes,locked 2006.201.17:38:43.65/valo/07,864.99,yes,locked 2006.201.17:38:43.65/valo/08,884.99,yes,locked 2006.201.17:38:44.74/vb/01,04,usb,yes,32,29 2006.201.17:38:44.74/vb/02,05,usb,yes,30,30 2006.201.17:38:44.74/vb/03,04,usb,yes,31,34 2006.201.17:38:44.74/vb/04,05,usb,yes,32,30 2006.201.17:38:44.74/vb/05,04,usb,yes,28,31 2006.201.17:38:44.74/vb/06,04,usb,yes,33,29 2006.201.17:38:44.74/vb/07,04,usb,yes,33,32 2006.201.17:38:44.74/vb/08,04,usb,yes,30,33 2006.201.17:38:44.97/vblo/01,629.99,yes,locked 2006.201.17:38:44.97/vblo/02,634.99,yes,locked 2006.201.17:38:44.97/vblo/03,649.99,yes,locked 2006.201.17:38:44.97/vblo/04,679.99,yes,locked 2006.201.17:38:44.97/vblo/05,709.99,yes,locked 2006.201.17:38:44.97/vblo/06,719.99,yes,locked 2006.201.17:38:44.97/vblo/07,734.99,yes,locked 2006.201.17:38:44.97/vblo/08,744.99,yes,locked 2006.201.17:38:45.12/vabw/8 2006.201.17:38:45.27/vbbw/8 2006.201.17:38:45.36/xfe/off,on,14.7 2006.201.17:38:45.74/ifatt/23,28,28,28 2006.201.17:38:46.07/fmout-gps/S +4.50E-07 2006.201.17:38:46.11:!2006.201.17:42:21 2006.201.17:42:21.00:data_valid=off 2006.201.17:42:21.00:"et 2006.201.17:42:21.00:!+3s 2006.201.17:42:24.02:"tape 2006.201.17:42:24.02:postob 2006.201.17:42:24.22/cable/+6.4775E-03 2006.201.17:42:24.22/wx/20.66,1002.5,100 2006.201.17:42:24.29/fmout-gps/S +4.53E-07 2006.201.17:42:24.29:scan_name=201-1752,jd0607,40 2006.201.17:42:24.29:source=1741-038,174358.86,-035004.6,2000.0,ccw 2006.201.17:42:26.14#flagr#flagr/antenna,new-source 2006.201.17:42:26.14:checkk5 2006.201.17:42:26.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.17:42:26.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.17:42:27.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.17:42:27.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.17:42:28.02/chk_obsdata//k5ts1/T2011738??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.17:42:28.39/chk_obsdata//k5ts2/T2011738??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.17:42:28.76/chk_obsdata//k5ts3/T2011738??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.17:42:29.12/chk_obsdata//k5ts4/T2011738??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.17:42:29.81/k5log//k5ts1_log_newline 2006.201.17:42:30.50/k5log//k5ts2_log_newline 2006.201.17:42:31.19/k5log//k5ts3_log_newline 2006.201.17:42:31.87/k5log//k5ts4_log_newline 2006.201.17:42:31.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.17:42:31.90:setupk4=1 2006.201.17:42:31.90$setupk4/echo=on 2006.201.17:42:31.90$setupk4/pcalon 2006.201.17:42:31.90$pcalon/"no phase cal control is implemented here 2006.201.17:42:31.90$setupk4/"tpicd=stop 2006.201.17:42:31.90$setupk4/"rec=synch_on 2006.201.17:42:31.90$setupk4/"rec_mode=128 2006.201.17:42:31.90$setupk4/!* 2006.201.17:42:31.90$setupk4/recpk4 2006.201.17:42:31.90$recpk4/recpatch= 2006.201.17:42:31.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.17:42:31.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.17:42:31.90$setupk4/vck44 2006.201.17:42:31.90$vck44/valo=1,524.99 2006.201.17:42:31.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.17:42:31.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.17:42:31.90#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:31.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:31.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:31.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:31.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.17:42:31.90#ibcon#first serial, iclass 28, count 0 2006.201.17:42:31.90#ibcon#enter sib2, iclass 28, count 0 2006.201.17:42:31.90#ibcon#flushed, iclass 28, count 0 2006.201.17:42:31.90#ibcon#about to write, iclass 28, count 0 2006.201.17:42:31.90#ibcon#wrote, iclass 28, count 0 2006.201.17:42:31.90#ibcon#about to read 3, iclass 28, count 0 2006.201.17:42:31.94#ibcon#read 3, iclass 28, count 0 2006.201.17:42:31.94#ibcon#about to read 4, iclass 28, count 0 2006.201.17:42:31.94#ibcon#read 4, iclass 28, count 0 2006.201.17:42:31.94#ibcon#about to read 5, iclass 28, count 0 2006.201.17:42:31.94#ibcon#read 5, iclass 28, count 0 2006.201.17:42:31.94#ibcon#about to read 6, iclass 28, count 0 2006.201.17:42:31.94#ibcon#read 6, iclass 28, count 0 2006.201.17:42:31.94#ibcon#end of sib2, iclass 28, count 0 2006.201.17:42:31.94#ibcon#*mode == 0, iclass 28, count 0 2006.201.17:42:31.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.17:42:31.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.17:42:31.94#ibcon#*before write, iclass 28, count 0 2006.201.17:42:31.94#ibcon#enter sib2, iclass 28, count 0 2006.201.17:42:31.94#ibcon#flushed, iclass 28, count 0 2006.201.17:42:31.94#ibcon#about to write, iclass 28, count 0 2006.201.17:42:31.94#ibcon#wrote, iclass 28, count 0 2006.201.17:42:31.94#ibcon#about to read 3, iclass 28, count 0 2006.201.17:42:31.99#ibcon#read 3, iclass 28, count 0 2006.201.17:42:31.99#ibcon#about to read 4, iclass 28, count 0 2006.201.17:42:31.99#ibcon#read 4, iclass 28, count 0 2006.201.17:42:31.99#ibcon#about to read 5, iclass 28, count 0 2006.201.17:42:31.99#ibcon#read 5, iclass 28, count 0 2006.201.17:42:31.99#ibcon#about to read 6, iclass 28, count 0 2006.201.17:42:31.99#ibcon#read 6, iclass 28, count 0 2006.201.17:42:31.99#ibcon#end of sib2, iclass 28, count 0 2006.201.17:42:31.99#ibcon#*after write, iclass 28, count 0 2006.201.17:42:31.99#ibcon#*before return 0, iclass 28, count 0 2006.201.17:42:31.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:31.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:31.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.17:42:31.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.17:42:31.99$vck44/va=1,8 2006.201.17:42:31.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.17:42:31.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.17:42:31.99#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:31.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:31.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:31.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:31.99#ibcon#enter wrdev, iclass 30, count 2 2006.201.17:42:31.99#ibcon#first serial, iclass 30, count 2 2006.201.17:42:31.99#ibcon#enter sib2, iclass 30, count 2 2006.201.17:42:31.99#ibcon#flushed, iclass 30, count 2 2006.201.17:42:31.99#ibcon#about to write, iclass 30, count 2 2006.201.17:42:31.99#ibcon#wrote, iclass 30, count 2 2006.201.17:42:31.99#ibcon#about to read 3, iclass 30, count 2 2006.201.17:42:32.01#ibcon#read 3, iclass 30, count 2 2006.201.17:42:32.01#ibcon#about to read 4, iclass 30, count 2 2006.201.17:42:32.01#ibcon#read 4, iclass 30, count 2 2006.201.17:42:32.01#ibcon#about to read 5, iclass 30, count 2 2006.201.17:42:32.01#ibcon#read 5, iclass 30, count 2 2006.201.17:42:32.01#ibcon#about to read 6, iclass 30, count 2 2006.201.17:42:32.01#ibcon#read 6, iclass 30, count 2 2006.201.17:42:32.01#ibcon#end of sib2, iclass 30, count 2 2006.201.17:42:32.01#ibcon#*mode == 0, iclass 30, count 2 2006.201.17:42:32.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.17:42:32.01#ibcon#[25=AT01-08\r\n] 2006.201.17:42:32.01#ibcon#*before write, iclass 30, count 2 2006.201.17:42:32.01#ibcon#enter sib2, iclass 30, count 2 2006.201.17:42:32.01#ibcon#flushed, iclass 30, count 2 2006.201.17:42:32.01#ibcon#about to write, iclass 30, count 2 2006.201.17:42:32.01#ibcon#wrote, iclass 30, count 2 2006.201.17:42:32.01#ibcon#about to read 3, iclass 30, count 2 2006.201.17:42:32.05#ibcon#read 3, iclass 30, count 2 2006.201.17:42:32.05#ibcon#about to read 4, iclass 30, count 2 2006.201.17:42:32.05#ibcon#read 4, iclass 30, count 2 2006.201.17:42:32.05#ibcon#about to read 5, iclass 30, count 2 2006.201.17:42:32.05#ibcon#read 5, iclass 30, count 2 2006.201.17:42:32.05#ibcon#about to read 6, iclass 30, count 2 2006.201.17:42:32.05#ibcon#read 6, iclass 30, count 2 2006.201.17:42:32.05#ibcon#end of sib2, iclass 30, count 2 2006.201.17:42:32.05#ibcon#*after write, iclass 30, count 2 2006.201.17:42:32.05#ibcon#*before return 0, iclass 30, count 2 2006.201.17:42:32.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:32.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:32.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.17:42:32.05#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:32.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:32.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:32.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:32.17#ibcon#enter wrdev, iclass 30, count 0 2006.201.17:42:32.17#ibcon#first serial, iclass 30, count 0 2006.201.17:42:32.17#ibcon#enter sib2, iclass 30, count 0 2006.201.17:42:32.17#ibcon#flushed, iclass 30, count 0 2006.201.17:42:32.17#ibcon#about to write, iclass 30, count 0 2006.201.17:42:32.17#ibcon#wrote, iclass 30, count 0 2006.201.17:42:32.17#ibcon#about to read 3, iclass 30, count 0 2006.201.17:42:32.20#ibcon#read 3, iclass 30, count 0 2006.201.17:42:32.20#ibcon#about to read 4, iclass 30, count 0 2006.201.17:42:32.20#ibcon#read 4, iclass 30, count 0 2006.201.17:42:32.20#ibcon#about to read 5, iclass 30, count 0 2006.201.17:42:32.20#ibcon#read 5, iclass 30, count 0 2006.201.17:42:32.20#ibcon#about to read 6, iclass 30, count 0 2006.201.17:42:32.20#ibcon#read 6, iclass 30, count 0 2006.201.17:42:32.20#ibcon#end of sib2, iclass 30, count 0 2006.201.17:42:32.20#ibcon#*mode == 0, iclass 30, count 0 2006.201.17:42:32.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.17:42:32.20#ibcon#[25=USB\r\n] 2006.201.17:42:32.20#ibcon#*before write, iclass 30, count 0 2006.201.17:42:32.20#ibcon#enter sib2, iclass 30, count 0 2006.201.17:42:32.20#ibcon#flushed, iclass 30, count 0 2006.201.17:42:32.20#ibcon#about to write, iclass 30, count 0 2006.201.17:42:32.20#ibcon#wrote, iclass 30, count 0 2006.201.17:42:32.20#ibcon#about to read 3, iclass 30, count 0 2006.201.17:42:32.23#ibcon#read 3, iclass 30, count 0 2006.201.17:42:32.23#ibcon#about to read 4, iclass 30, count 0 2006.201.17:42:32.23#ibcon#read 4, iclass 30, count 0 2006.201.17:42:32.23#ibcon#about to read 5, iclass 30, count 0 2006.201.17:42:32.23#ibcon#read 5, iclass 30, count 0 2006.201.17:42:32.23#ibcon#about to read 6, iclass 30, count 0 2006.201.17:42:32.23#ibcon#read 6, iclass 30, count 0 2006.201.17:42:32.23#ibcon#end of sib2, iclass 30, count 0 2006.201.17:42:32.23#ibcon#*after write, iclass 30, count 0 2006.201.17:42:32.23#ibcon#*before return 0, iclass 30, count 0 2006.201.17:42:32.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:32.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:32.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.17:42:32.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.17:42:32.23$vck44/valo=2,534.99 2006.201.17:42:32.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.17:42:32.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.17:42:32.23#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:32.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:32.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:32.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:32.23#ibcon#enter wrdev, iclass 32, count 0 2006.201.17:42:32.23#ibcon#first serial, iclass 32, count 0 2006.201.17:42:32.23#ibcon#enter sib2, iclass 32, count 0 2006.201.17:42:32.23#ibcon#flushed, iclass 32, count 0 2006.201.17:42:32.23#ibcon#about to write, iclass 32, count 0 2006.201.17:42:32.23#ibcon#wrote, iclass 32, count 0 2006.201.17:42:32.23#ibcon#about to read 3, iclass 32, count 0 2006.201.17:42:32.25#ibcon#read 3, iclass 32, count 0 2006.201.17:42:32.25#ibcon#about to read 4, iclass 32, count 0 2006.201.17:42:32.25#ibcon#read 4, iclass 32, count 0 2006.201.17:42:32.25#ibcon#about to read 5, iclass 32, count 0 2006.201.17:42:32.25#ibcon#read 5, iclass 32, count 0 2006.201.17:42:32.25#ibcon#about to read 6, iclass 32, count 0 2006.201.17:42:32.25#ibcon#read 6, iclass 32, count 0 2006.201.17:42:32.25#ibcon#end of sib2, iclass 32, count 0 2006.201.17:42:32.25#ibcon#*mode == 0, iclass 32, count 0 2006.201.17:42:32.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.17:42:32.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.17:42:32.25#ibcon#*before write, iclass 32, count 0 2006.201.17:42:32.25#ibcon#enter sib2, iclass 32, count 0 2006.201.17:42:32.25#ibcon#flushed, iclass 32, count 0 2006.201.17:42:32.25#ibcon#about to write, iclass 32, count 0 2006.201.17:42:32.25#ibcon#wrote, iclass 32, count 0 2006.201.17:42:32.25#ibcon#about to read 3, iclass 32, count 0 2006.201.17:42:32.29#ibcon#read 3, iclass 32, count 0 2006.201.17:42:32.29#ibcon#about to read 4, iclass 32, count 0 2006.201.17:42:32.29#ibcon#read 4, iclass 32, count 0 2006.201.17:42:32.29#ibcon#about to read 5, iclass 32, count 0 2006.201.17:42:32.29#ibcon#read 5, iclass 32, count 0 2006.201.17:42:32.29#ibcon#about to read 6, iclass 32, count 0 2006.201.17:42:32.29#ibcon#read 6, iclass 32, count 0 2006.201.17:42:32.29#ibcon#end of sib2, iclass 32, count 0 2006.201.17:42:32.29#ibcon#*after write, iclass 32, count 0 2006.201.17:42:32.29#ibcon#*before return 0, iclass 32, count 0 2006.201.17:42:32.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:32.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:32.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.17:42:32.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.17:42:32.29$vck44/va=2,7 2006.201.17:42:32.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.17:42:32.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.17:42:32.29#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:32.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:32.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:32.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:32.35#ibcon#enter wrdev, iclass 34, count 2 2006.201.17:42:32.35#ibcon#first serial, iclass 34, count 2 2006.201.17:42:32.35#ibcon#enter sib2, iclass 34, count 2 2006.201.17:42:32.35#ibcon#flushed, iclass 34, count 2 2006.201.17:42:32.35#ibcon#about to write, iclass 34, count 2 2006.201.17:42:32.35#ibcon#wrote, iclass 34, count 2 2006.201.17:42:32.35#ibcon#about to read 3, iclass 34, count 2 2006.201.17:42:32.37#ibcon#read 3, iclass 34, count 2 2006.201.17:42:32.37#ibcon#about to read 4, iclass 34, count 2 2006.201.17:42:32.37#ibcon#read 4, iclass 34, count 2 2006.201.17:42:32.37#ibcon#about to read 5, iclass 34, count 2 2006.201.17:42:32.37#ibcon#read 5, iclass 34, count 2 2006.201.17:42:32.37#ibcon#about to read 6, iclass 34, count 2 2006.201.17:42:32.37#ibcon#read 6, iclass 34, count 2 2006.201.17:42:32.37#ibcon#end of sib2, iclass 34, count 2 2006.201.17:42:32.37#ibcon#*mode == 0, iclass 34, count 2 2006.201.17:42:32.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.17:42:32.37#ibcon#[25=AT02-07\r\n] 2006.201.17:42:32.37#ibcon#*before write, iclass 34, count 2 2006.201.17:42:32.37#ibcon#enter sib2, iclass 34, count 2 2006.201.17:42:32.37#ibcon#flushed, iclass 34, count 2 2006.201.17:42:32.37#ibcon#about to write, iclass 34, count 2 2006.201.17:42:32.37#ibcon#wrote, iclass 34, count 2 2006.201.17:42:32.37#ibcon#about to read 3, iclass 34, count 2 2006.201.17:42:32.40#ibcon#read 3, iclass 34, count 2 2006.201.17:42:32.40#ibcon#about to read 4, iclass 34, count 2 2006.201.17:42:32.40#ibcon#read 4, iclass 34, count 2 2006.201.17:42:32.40#ibcon#about to read 5, iclass 34, count 2 2006.201.17:42:32.40#ibcon#read 5, iclass 34, count 2 2006.201.17:42:32.40#ibcon#about to read 6, iclass 34, count 2 2006.201.17:42:32.40#ibcon#read 6, iclass 34, count 2 2006.201.17:42:32.40#ibcon#end of sib2, iclass 34, count 2 2006.201.17:42:32.40#ibcon#*after write, iclass 34, count 2 2006.201.17:42:32.40#ibcon#*before return 0, iclass 34, count 2 2006.201.17:42:32.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:32.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:32.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.17:42:32.40#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:32.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:32.47#abcon#<5=/16 0.6 1.3 20.661001002.5\r\n> 2006.201.17:42:32.49#abcon#{5=INTERFACE CLEAR} 2006.201.17:42:32.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:32.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:32.52#ibcon#enter wrdev, iclass 34, count 0 2006.201.17:42:32.52#ibcon#first serial, iclass 34, count 0 2006.201.17:42:32.52#ibcon#enter sib2, iclass 34, count 0 2006.201.17:42:32.52#ibcon#flushed, iclass 34, count 0 2006.201.17:42:32.52#ibcon#about to write, iclass 34, count 0 2006.201.17:42:32.52#ibcon#wrote, iclass 34, count 0 2006.201.17:42:32.52#ibcon#about to read 3, iclass 34, count 0 2006.201.17:42:32.54#ibcon#read 3, iclass 34, count 0 2006.201.17:42:32.54#ibcon#about to read 4, iclass 34, count 0 2006.201.17:42:32.54#ibcon#read 4, iclass 34, count 0 2006.201.17:42:32.54#ibcon#about to read 5, iclass 34, count 0 2006.201.17:42:32.54#ibcon#read 5, iclass 34, count 0 2006.201.17:42:32.54#ibcon#about to read 6, iclass 34, count 0 2006.201.17:42:32.54#ibcon#read 6, iclass 34, count 0 2006.201.17:42:32.54#ibcon#end of sib2, iclass 34, count 0 2006.201.17:42:32.54#ibcon#*mode == 0, iclass 34, count 0 2006.201.17:42:32.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.17:42:32.54#ibcon#[25=USB\r\n] 2006.201.17:42:32.54#ibcon#*before write, iclass 34, count 0 2006.201.17:42:32.54#ibcon#enter sib2, iclass 34, count 0 2006.201.17:42:32.54#ibcon#flushed, iclass 34, count 0 2006.201.17:42:32.54#ibcon#about to write, iclass 34, count 0 2006.201.17:42:32.54#ibcon#wrote, iclass 34, count 0 2006.201.17:42:32.54#ibcon#about to read 3, iclass 34, count 0 2006.201.17:42:32.55#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:42:32.58#ibcon#read 3, iclass 34, count 0 2006.201.17:42:32.58#ibcon#about to read 4, iclass 34, count 0 2006.201.17:42:32.58#ibcon#read 4, iclass 34, count 0 2006.201.17:42:32.58#ibcon#about to read 5, iclass 34, count 0 2006.201.17:42:32.58#ibcon#read 5, iclass 34, count 0 2006.201.17:42:32.58#ibcon#about to read 6, iclass 34, count 0 2006.201.17:42:32.58#ibcon#read 6, iclass 34, count 0 2006.201.17:42:32.58#ibcon#end of sib2, iclass 34, count 0 2006.201.17:42:32.58#ibcon#*after write, iclass 34, count 0 2006.201.17:42:32.58#ibcon#*before return 0, iclass 34, count 0 2006.201.17:42:32.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:32.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:32.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.17:42:32.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.17:42:32.58$vck44/valo=3,564.99 2006.201.17:42:32.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.17:42:32.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.17:42:32.58#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:32.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:32.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:32.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:32.58#ibcon#enter wrdev, iclass 40, count 0 2006.201.17:42:32.58#ibcon#first serial, iclass 40, count 0 2006.201.17:42:32.58#ibcon#enter sib2, iclass 40, count 0 2006.201.17:42:32.58#ibcon#flushed, iclass 40, count 0 2006.201.17:42:32.58#ibcon#about to write, iclass 40, count 0 2006.201.17:42:32.58#ibcon#wrote, iclass 40, count 0 2006.201.17:42:32.58#ibcon#about to read 3, iclass 40, count 0 2006.201.17:42:32.60#ibcon#read 3, iclass 40, count 0 2006.201.17:42:32.60#ibcon#about to read 4, iclass 40, count 0 2006.201.17:42:32.60#ibcon#read 4, iclass 40, count 0 2006.201.17:42:32.60#ibcon#about to read 5, iclass 40, count 0 2006.201.17:42:32.60#ibcon#read 5, iclass 40, count 0 2006.201.17:42:32.60#ibcon#about to read 6, iclass 40, count 0 2006.201.17:42:32.60#ibcon#read 6, iclass 40, count 0 2006.201.17:42:32.60#ibcon#end of sib2, iclass 40, count 0 2006.201.17:42:32.60#ibcon#*mode == 0, iclass 40, count 0 2006.201.17:42:32.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.17:42:32.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.17:42:32.60#ibcon#*before write, iclass 40, count 0 2006.201.17:42:32.60#ibcon#enter sib2, iclass 40, count 0 2006.201.17:42:32.60#ibcon#flushed, iclass 40, count 0 2006.201.17:42:32.60#ibcon#about to write, iclass 40, count 0 2006.201.17:42:32.60#ibcon#wrote, iclass 40, count 0 2006.201.17:42:32.60#ibcon#about to read 3, iclass 40, count 0 2006.201.17:42:32.64#ibcon#read 3, iclass 40, count 0 2006.201.17:42:32.64#ibcon#about to read 4, iclass 40, count 0 2006.201.17:42:32.64#ibcon#read 4, iclass 40, count 0 2006.201.17:42:32.64#ibcon#about to read 5, iclass 40, count 0 2006.201.17:42:32.64#ibcon#read 5, iclass 40, count 0 2006.201.17:42:32.64#ibcon#about to read 6, iclass 40, count 0 2006.201.17:42:32.64#ibcon#read 6, iclass 40, count 0 2006.201.17:42:32.64#ibcon#end of sib2, iclass 40, count 0 2006.201.17:42:32.64#ibcon#*after write, iclass 40, count 0 2006.201.17:42:32.64#ibcon#*before return 0, iclass 40, count 0 2006.201.17:42:32.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:32.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:32.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.17:42:32.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.17:42:32.64$vck44/va=3,8 2006.201.17:42:32.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.17:42:32.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.17:42:32.64#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:32.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:32.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:32.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:32.70#ibcon#enter wrdev, iclass 4, count 2 2006.201.17:42:32.70#ibcon#first serial, iclass 4, count 2 2006.201.17:42:32.70#ibcon#enter sib2, iclass 4, count 2 2006.201.17:42:32.70#ibcon#flushed, iclass 4, count 2 2006.201.17:42:32.70#ibcon#about to write, iclass 4, count 2 2006.201.17:42:32.70#ibcon#wrote, iclass 4, count 2 2006.201.17:42:32.70#ibcon#about to read 3, iclass 4, count 2 2006.201.17:42:32.72#ibcon#read 3, iclass 4, count 2 2006.201.17:42:32.72#ibcon#about to read 4, iclass 4, count 2 2006.201.17:42:32.72#ibcon#read 4, iclass 4, count 2 2006.201.17:42:32.72#ibcon#about to read 5, iclass 4, count 2 2006.201.17:42:32.72#ibcon#read 5, iclass 4, count 2 2006.201.17:42:32.72#ibcon#about to read 6, iclass 4, count 2 2006.201.17:42:32.72#ibcon#read 6, iclass 4, count 2 2006.201.17:42:32.72#ibcon#end of sib2, iclass 4, count 2 2006.201.17:42:32.72#ibcon#*mode == 0, iclass 4, count 2 2006.201.17:42:32.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.17:42:32.72#ibcon#[25=AT03-08\r\n] 2006.201.17:42:32.72#ibcon#*before write, iclass 4, count 2 2006.201.17:42:32.72#ibcon#enter sib2, iclass 4, count 2 2006.201.17:42:32.72#ibcon#flushed, iclass 4, count 2 2006.201.17:42:32.72#ibcon#about to write, iclass 4, count 2 2006.201.17:42:32.72#ibcon#wrote, iclass 4, count 2 2006.201.17:42:32.72#ibcon#about to read 3, iclass 4, count 2 2006.201.17:42:32.75#ibcon#read 3, iclass 4, count 2 2006.201.17:42:32.75#ibcon#about to read 4, iclass 4, count 2 2006.201.17:42:32.75#ibcon#read 4, iclass 4, count 2 2006.201.17:42:32.75#ibcon#about to read 5, iclass 4, count 2 2006.201.17:42:32.75#ibcon#read 5, iclass 4, count 2 2006.201.17:42:32.75#ibcon#about to read 6, iclass 4, count 2 2006.201.17:42:32.75#ibcon#read 6, iclass 4, count 2 2006.201.17:42:32.75#ibcon#end of sib2, iclass 4, count 2 2006.201.17:42:32.75#ibcon#*after write, iclass 4, count 2 2006.201.17:42:32.75#ibcon#*before return 0, iclass 4, count 2 2006.201.17:42:32.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:32.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:32.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.17:42:32.75#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:32.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:32.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:32.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:32.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.17:42:32.87#ibcon#first serial, iclass 4, count 0 2006.201.17:42:32.87#ibcon#enter sib2, iclass 4, count 0 2006.201.17:42:32.87#ibcon#flushed, iclass 4, count 0 2006.201.17:42:32.87#ibcon#about to write, iclass 4, count 0 2006.201.17:42:32.87#ibcon#wrote, iclass 4, count 0 2006.201.17:42:32.87#ibcon#about to read 3, iclass 4, count 0 2006.201.17:42:32.89#ibcon#read 3, iclass 4, count 0 2006.201.17:42:32.89#ibcon#about to read 4, iclass 4, count 0 2006.201.17:42:32.89#ibcon#read 4, iclass 4, count 0 2006.201.17:42:32.89#ibcon#about to read 5, iclass 4, count 0 2006.201.17:42:32.89#ibcon#read 5, iclass 4, count 0 2006.201.17:42:32.89#ibcon#about to read 6, iclass 4, count 0 2006.201.17:42:32.89#ibcon#read 6, iclass 4, count 0 2006.201.17:42:32.89#ibcon#end of sib2, iclass 4, count 0 2006.201.17:42:32.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.17:42:32.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.17:42:32.89#ibcon#[25=USB\r\n] 2006.201.17:42:32.89#ibcon#*before write, iclass 4, count 0 2006.201.17:42:32.89#ibcon#enter sib2, iclass 4, count 0 2006.201.17:42:32.89#ibcon#flushed, iclass 4, count 0 2006.201.17:42:32.89#ibcon#about to write, iclass 4, count 0 2006.201.17:42:32.89#ibcon#wrote, iclass 4, count 0 2006.201.17:42:32.89#ibcon#about to read 3, iclass 4, count 0 2006.201.17:42:32.92#ibcon#read 3, iclass 4, count 0 2006.201.17:42:32.92#ibcon#about to read 4, iclass 4, count 0 2006.201.17:42:32.92#ibcon#read 4, iclass 4, count 0 2006.201.17:42:32.92#ibcon#about to read 5, iclass 4, count 0 2006.201.17:42:32.92#ibcon#read 5, iclass 4, count 0 2006.201.17:42:32.92#ibcon#about to read 6, iclass 4, count 0 2006.201.17:42:32.92#ibcon#read 6, iclass 4, count 0 2006.201.17:42:32.92#ibcon#end of sib2, iclass 4, count 0 2006.201.17:42:32.92#ibcon#*after write, iclass 4, count 0 2006.201.17:42:32.92#ibcon#*before return 0, iclass 4, count 0 2006.201.17:42:32.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:32.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:32.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.17:42:32.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.17:42:32.92$vck44/valo=4,624.99 2006.201.17:42:32.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.17:42:32.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.17:42:32.92#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:32.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:32.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:32.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:32.92#ibcon#enter wrdev, iclass 6, count 0 2006.201.17:42:32.92#ibcon#first serial, iclass 6, count 0 2006.201.17:42:32.92#ibcon#enter sib2, iclass 6, count 0 2006.201.17:42:32.92#ibcon#flushed, iclass 6, count 0 2006.201.17:42:32.92#ibcon#about to write, iclass 6, count 0 2006.201.17:42:32.92#ibcon#wrote, iclass 6, count 0 2006.201.17:42:32.92#ibcon#about to read 3, iclass 6, count 0 2006.201.17:42:32.94#ibcon#read 3, iclass 6, count 0 2006.201.17:42:32.94#ibcon#about to read 4, iclass 6, count 0 2006.201.17:42:32.94#ibcon#read 4, iclass 6, count 0 2006.201.17:42:32.94#ibcon#about to read 5, iclass 6, count 0 2006.201.17:42:32.94#ibcon#read 5, iclass 6, count 0 2006.201.17:42:32.94#ibcon#about to read 6, iclass 6, count 0 2006.201.17:42:32.94#ibcon#read 6, iclass 6, count 0 2006.201.17:42:32.94#ibcon#end of sib2, iclass 6, count 0 2006.201.17:42:32.94#ibcon#*mode == 0, iclass 6, count 0 2006.201.17:42:32.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.17:42:32.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.17:42:32.94#ibcon#*before write, iclass 6, count 0 2006.201.17:42:32.94#ibcon#enter sib2, iclass 6, count 0 2006.201.17:42:32.94#ibcon#flushed, iclass 6, count 0 2006.201.17:42:32.94#ibcon#about to write, iclass 6, count 0 2006.201.17:42:32.94#ibcon#wrote, iclass 6, count 0 2006.201.17:42:32.94#ibcon#about to read 3, iclass 6, count 0 2006.201.17:42:32.98#ibcon#read 3, iclass 6, count 0 2006.201.17:42:32.98#ibcon#about to read 4, iclass 6, count 0 2006.201.17:42:32.98#ibcon#read 4, iclass 6, count 0 2006.201.17:42:32.98#ibcon#about to read 5, iclass 6, count 0 2006.201.17:42:32.98#ibcon#read 5, iclass 6, count 0 2006.201.17:42:32.98#ibcon#about to read 6, iclass 6, count 0 2006.201.17:42:32.98#ibcon#read 6, iclass 6, count 0 2006.201.17:42:32.98#ibcon#end of sib2, iclass 6, count 0 2006.201.17:42:32.98#ibcon#*after write, iclass 6, count 0 2006.201.17:42:32.98#ibcon#*before return 0, iclass 6, count 0 2006.201.17:42:32.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:32.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:32.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.17:42:32.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.17:42:32.98$vck44/va=4,7 2006.201.17:42:32.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.17:42:32.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.17:42:32.98#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:32.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:33.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:33.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:33.04#ibcon#enter wrdev, iclass 10, count 2 2006.201.17:42:33.04#ibcon#first serial, iclass 10, count 2 2006.201.17:42:33.04#ibcon#enter sib2, iclass 10, count 2 2006.201.17:42:33.04#ibcon#flushed, iclass 10, count 2 2006.201.17:42:33.04#ibcon#about to write, iclass 10, count 2 2006.201.17:42:33.04#ibcon#wrote, iclass 10, count 2 2006.201.17:42:33.04#ibcon#about to read 3, iclass 10, count 2 2006.201.17:42:33.06#ibcon#read 3, iclass 10, count 2 2006.201.17:42:33.06#ibcon#about to read 4, iclass 10, count 2 2006.201.17:42:33.06#ibcon#read 4, iclass 10, count 2 2006.201.17:42:33.06#ibcon#about to read 5, iclass 10, count 2 2006.201.17:42:33.06#ibcon#read 5, iclass 10, count 2 2006.201.17:42:33.06#ibcon#about to read 6, iclass 10, count 2 2006.201.17:42:33.06#ibcon#read 6, iclass 10, count 2 2006.201.17:42:33.06#ibcon#end of sib2, iclass 10, count 2 2006.201.17:42:33.06#ibcon#*mode == 0, iclass 10, count 2 2006.201.17:42:33.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.17:42:33.06#ibcon#[25=AT04-07\r\n] 2006.201.17:42:33.06#ibcon#*before write, iclass 10, count 2 2006.201.17:42:33.06#ibcon#enter sib2, iclass 10, count 2 2006.201.17:42:33.06#ibcon#flushed, iclass 10, count 2 2006.201.17:42:33.06#ibcon#about to write, iclass 10, count 2 2006.201.17:42:33.06#ibcon#wrote, iclass 10, count 2 2006.201.17:42:33.06#ibcon#about to read 3, iclass 10, count 2 2006.201.17:42:33.09#ibcon#read 3, iclass 10, count 2 2006.201.17:42:33.09#ibcon#about to read 4, iclass 10, count 2 2006.201.17:42:33.09#ibcon#read 4, iclass 10, count 2 2006.201.17:42:33.09#ibcon#about to read 5, iclass 10, count 2 2006.201.17:42:33.09#ibcon#read 5, iclass 10, count 2 2006.201.17:42:33.09#ibcon#about to read 6, iclass 10, count 2 2006.201.17:42:33.09#ibcon#read 6, iclass 10, count 2 2006.201.17:42:33.09#ibcon#end of sib2, iclass 10, count 2 2006.201.17:42:33.09#ibcon#*after write, iclass 10, count 2 2006.201.17:42:33.09#ibcon#*before return 0, iclass 10, count 2 2006.201.17:42:33.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:33.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:33.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.17:42:33.09#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:33.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:33.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:33.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:33.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.17:42:33.21#ibcon#first serial, iclass 10, count 0 2006.201.17:42:33.21#ibcon#enter sib2, iclass 10, count 0 2006.201.17:42:33.21#ibcon#flushed, iclass 10, count 0 2006.201.17:42:33.21#ibcon#about to write, iclass 10, count 0 2006.201.17:42:33.21#ibcon#wrote, iclass 10, count 0 2006.201.17:42:33.21#ibcon#about to read 3, iclass 10, count 0 2006.201.17:42:33.23#ibcon#read 3, iclass 10, count 0 2006.201.17:42:33.23#ibcon#about to read 4, iclass 10, count 0 2006.201.17:42:33.23#ibcon#read 4, iclass 10, count 0 2006.201.17:42:33.23#ibcon#about to read 5, iclass 10, count 0 2006.201.17:42:33.23#ibcon#read 5, iclass 10, count 0 2006.201.17:42:33.23#ibcon#about to read 6, iclass 10, count 0 2006.201.17:42:33.23#ibcon#read 6, iclass 10, count 0 2006.201.17:42:33.23#ibcon#end of sib2, iclass 10, count 0 2006.201.17:42:33.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.17:42:33.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.17:42:33.23#ibcon#[25=USB\r\n] 2006.201.17:42:33.23#ibcon#*before write, iclass 10, count 0 2006.201.17:42:33.23#ibcon#enter sib2, iclass 10, count 0 2006.201.17:42:33.23#ibcon#flushed, iclass 10, count 0 2006.201.17:42:33.23#ibcon#about to write, iclass 10, count 0 2006.201.17:42:33.23#ibcon#wrote, iclass 10, count 0 2006.201.17:42:33.23#ibcon#about to read 3, iclass 10, count 0 2006.201.17:42:33.26#ibcon#read 3, iclass 10, count 0 2006.201.17:42:33.26#ibcon#about to read 4, iclass 10, count 0 2006.201.17:42:33.26#ibcon#read 4, iclass 10, count 0 2006.201.17:42:33.26#ibcon#about to read 5, iclass 10, count 0 2006.201.17:42:33.26#ibcon#read 5, iclass 10, count 0 2006.201.17:42:33.26#ibcon#about to read 6, iclass 10, count 0 2006.201.17:42:33.26#ibcon#read 6, iclass 10, count 0 2006.201.17:42:33.26#ibcon#end of sib2, iclass 10, count 0 2006.201.17:42:33.26#ibcon#*after write, iclass 10, count 0 2006.201.17:42:33.26#ibcon#*before return 0, iclass 10, count 0 2006.201.17:42:33.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:33.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:33.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.17:42:33.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.17:42:33.26$vck44/valo=5,734.99 2006.201.17:42:33.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.17:42:33.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.17:42:33.26#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:33.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:33.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:33.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:33.26#ibcon#enter wrdev, iclass 12, count 0 2006.201.17:42:33.26#ibcon#first serial, iclass 12, count 0 2006.201.17:42:33.26#ibcon#enter sib2, iclass 12, count 0 2006.201.17:42:33.26#ibcon#flushed, iclass 12, count 0 2006.201.17:42:33.26#ibcon#about to write, iclass 12, count 0 2006.201.17:42:33.26#ibcon#wrote, iclass 12, count 0 2006.201.17:42:33.26#ibcon#about to read 3, iclass 12, count 0 2006.201.17:42:33.28#ibcon#read 3, iclass 12, count 0 2006.201.17:42:33.28#ibcon#about to read 4, iclass 12, count 0 2006.201.17:42:33.28#ibcon#read 4, iclass 12, count 0 2006.201.17:42:33.28#ibcon#about to read 5, iclass 12, count 0 2006.201.17:42:33.28#ibcon#read 5, iclass 12, count 0 2006.201.17:42:33.28#ibcon#about to read 6, iclass 12, count 0 2006.201.17:42:33.28#ibcon#read 6, iclass 12, count 0 2006.201.17:42:33.28#ibcon#end of sib2, iclass 12, count 0 2006.201.17:42:33.28#ibcon#*mode == 0, iclass 12, count 0 2006.201.17:42:33.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.17:42:33.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.17:42:33.28#ibcon#*before write, iclass 12, count 0 2006.201.17:42:33.28#ibcon#enter sib2, iclass 12, count 0 2006.201.17:42:33.28#ibcon#flushed, iclass 12, count 0 2006.201.17:42:33.28#ibcon#about to write, iclass 12, count 0 2006.201.17:42:33.28#ibcon#wrote, iclass 12, count 0 2006.201.17:42:33.28#ibcon#about to read 3, iclass 12, count 0 2006.201.17:42:33.32#ibcon#read 3, iclass 12, count 0 2006.201.17:42:33.32#ibcon#about to read 4, iclass 12, count 0 2006.201.17:42:33.32#ibcon#read 4, iclass 12, count 0 2006.201.17:42:33.32#ibcon#about to read 5, iclass 12, count 0 2006.201.17:42:33.32#ibcon#read 5, iclass 12, count 0 2006.201.17:42:33.32#ibcon#about to read 6, iclass 12, count 0 2006.201.17:42:33.32#ibcon#read 6, iclass 12, count 0 2006.201.17:42:33.32#ibcon#end of sib2, iclass 12, count 0 2006.201.17:42:33.32#ibcon#*after write, iclass 12, count 0 2006.201.17:42:33.32#ibcon#*before return 0, iclass 12, count 0 2006.201.17:42:33.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:33.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:33.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.17:42:33.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.17:42:33.32$vck44/va=5,4 2006.201.17:42:33.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.17:42:33.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.17:42:33.32#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:33.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:33.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:33.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:33.38#ibcon#enter wrdev, iclass 14, count 2 2006.201.17:42:33.38#ibcon#first serial, iclass 14, count 2 2006.201.17:42:33.38#ibcon#enter sib2, iclass 14, count 2 2006.201.17:42:33.38#ibcon#flushed, iclass 14, count 2 2006.201.17:42:33.38#ibcon#about to write, iclass 14, count 2 2006.201.17:42:33.38#ibcon#wrote, iclass 14, count 2 2006.201.17:42:33.38#ibcon#about to read 3, iclass 14, count 2 2006.201.17:42:33.40#ibcon#read 3, iclass 14, count 2 2006.201.17:42:33.40#ibcon#about to read 4, iclass 14, count 2 2006.201.17:42:33.40#ibcon#read 4, iclass 14, count 2 2006.201.17:42:33.40#ibcon#about to read 5, iclass 14, count 2 2006.201.17:42:33.40#ibcon#read 5, iclass 14, count 2 2006.201.17:42:33.40#ibcon#about to read 6, iclass 14, count 2 2006.201.17:42:33.40#ibcon#read 6, iclass 14, count 2 2006.201.17:42:33.40#ibcon#end of sib2, iclass 14, count 2 2006.201.17:42:33.40#ibcon#*mode == 0, iclass 14, count 2 2006.201.17:42:33.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.17:42:33.40#ibcon#[25=AT05-04\r\n] 2006.201.17:42:33.40#ibcon#*before write, iclass 14, count 2 2006.201.17:42:33.40#ibcon#enter sib2, iclass 14, count 2 2006.201.17:42:33.40#ibcon#flushed, iclass 14, count 2 2006.201.17:42:33.40#ibcon#about to write, iclass 14, count 2 2006.201.17:42:33.40#ibcon#wrote, iclass 14, count 2 2006.201.17:42:33.40#ibcon#about to read 3, iclass 14, count 2 2006.201.17:42:33.43#ibcon#read 3, iclass 14, count 2 2006.201.17:42:33.43#ibcon#about to read 4, iclass 14, count 2 2006.201.17:42:33.43#ibcon#read 4, iclass 14, count 2 2006.201.17:42:33.43#ibcon#about to read 5, iclass 14, count 2 2006.201.17:42:33.43#ibcon#read 5, iclass 14, count 2 2006.201.17:42:33.43#ibcon#about to read 6, iclass 14, count 2 2006.201.17:42:33.43#ibcon#read 6, iclass 14, count 2 2006.201.17:42:33.43#ibcon#end of sib2, iclass 14, count 2 2006.201.17:42:33.43#ibcon#*after write, iclass 14, count 2 2006.201.17:42:33.43#ibcon#*before return 0, iclass 14, count 2 2006.201.17:42:33.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:33.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:33.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.17:42:33.43#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:33.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:33.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:33.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:33.55#ibcon#enter wrdev, iclass 14, count 0 2006.201.17:42:33.55#ibcon#first serial, iclass 14, count 0 2006.201.17:42:33.55#ibcon#enter sib2, iclass 14, count 0 2006.201.17:42:33.55#ibcon#flushed, iclass 14, count 0 2006.201.17:42:33.55#ibcon#about to write, iclass 14, count 0 2006.201.17:42:33.55#ibcon#wrote, iclass 14, count 0 2006.201.17:42:33.55#ibcon#about to read 3, iclass 14, count 0 2006.201.17:42:33.57#ibcon#read 3, iclass 14, count 0 2006.201.17:42:33.57#ibcon#about to read 4, iclass 14, count 0 2006.201.17:42:33.57#ibcon#read 4, iclass 14, count 0 2006.201.17:42:33.57#ibcon#about to read 5, iclass 14, count 0 2006.201.17:42:33.57#ibcon#read 5, iclass 14, count 0 2006.201.17:42:33.57#ibcon#about to read 6, iclass 14, count 0 2006.201.17:42:33.57#ibcon#read 6, iclass 14, count 0 2006.201.17:42:33.57#ibcon#end of sib2, iclass 14, count 0 2006.201.17:42:33.57#ibcon#*mode == 0, iclass 14, count 0 2006.201.17:42:33.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.17:42:33.57#ibcon#[25=USB\r\n] 2006.201.17:42:33.57#ibcon#*before write, iclass 14, count 0 2006.201.17:42:33.57#ibcon#enter sib2, iclass 14, count 0 2006.201.17:42:33.57#ibcon#flushed, iclass 14, count 0 2006.201.17:42:33.57#ibcon#about to write, iclass 14, count 0 2006.201.17:42:33.57#ibcon#wrote, iclass 14, count 0 2006.201.17:42:33.57#ibcon#about to read 3, iclass 14, count 0 2006.201.17:42:33.60#ibcon#read 3, iclass 14, count 0 2006.201.17:42:33.60#ibcon#about to read 4, iclass 14, count 0 2006.201.17:42:33.60#ibcon#read 4, iclass 14, count 0 2006.201.17:42:33.60#ibcon#about to read 5, iclass 14, count 0 2006.201.17:42:33.60#ibcon#read 5, iclass 14, count 0 2006.201.17:42:33.60#ibcon#about to read 6, iclass 14, count 0 2006.201.17:42:33.60#ibcon#read 6, iclass 14, count 0 2006.201.17:42:33.60#ibcon#end of sib2, iclass 14, count 0 2006.201.17:42:33.60#ibcon#*after write, iclass 14, count 0 2006.201.17:42:33.60#ibcon#*before return 0, iclass 14, count 0 2006.201.17:42:33.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:33.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:33.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.17:42:33.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.17:42:33.60$vck44/valo=6,814.99 2006.201.17:42:33.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.17:42:33.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.17:42:33.60#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:33.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:33.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:33.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:33.60#ibcon#enter wrdev, iclass 16, count 0 2006.201.17:42:33.60#ibcon#first serial, iclass 16, count 0 2006.201.17:42:33.60#ibcon#enter sib2, iclass 16, count 0 2006.201.17:42:33.60#ibcon#flushed, iclass 16, count 0 2006.201.17:42:33.60#ibcon#about to write, iclass 16, count 0 2006.201.17:42:33.60#ibcon#wrote, iclass 16, count 0 2006.201.17:42:33.60#ibcon#about to read 3, iclass 16, count 0 2006.201.17:42:33.62#ibcon#read 3, iclass 16, count 0 2006.201.17:42:33.62#ibcon#about to read 4, iclass 16, count 0 2006.201.17:42:33.62#ibcon#read 4, iclass 16, count 0 2006.201.17:42:33.62#ibcon#about to read 5, iclass 16, count 0 2006.201.17:42:33.62#ibcon#read 5, iclass 16, count 0 2006.201.17:42:33.62#ibcon#about to read 6, iclass 16, count 0 2006.201.17:42:33.62#ibcon#read 6, iclass 16, count 0 2006.201.17:42:33.62#ibcon#end of sib2, iclass 16, count 0 2006.201.17:42:33.62#ibcon#*mode == 0, iclass 16, count 0 2006.201.17:42:33.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.17:42:33.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.17:42:33.62#ibcon#*before write, iclass 16, count 0 2006.201.17:42:33.62#ibcon#enter sib2, iclass 16, count 0 2006.201.17:42:33.62#ibcon#flushed, iclass 16, count 0 2006.201.17:42:33.62#ibcon#about to write, iclass 16, count 0 2006.201.17:42:33.62#ibcon#wrote, iclass 16, count 0 2006.201.17:42:33.62#ibcon#about to read 3, iclass 16, count 0 2006.201.17:42:33.66#ibcon#read 3, iclass 16, count 0 2006.201.17:42:33.66#ibcon#about to read 4, iclass 16, count 0 2006.201.17:42:33.66#ibcon#read 4, iclass 16, count 0 2006.201.17:42:33.66#ibcon#about to read 5, iclass 16, count 0 2006.201.17:42:33.66#ibcon#read 5, iclass 16, count 0 2006.201.17:42:33.66#ibcon#about to read 6, iclass 16, count 0 2006.201.17:42:33.66#ibcon#read 6, iclass 16, count 0 2006.201.17:42:33.66#ibcon#end of sib2, iclass 16, count 0 2006.201.17:42:33.66#ibcon#*after write, iclass 16, count 0 2006.201.17:42:33.66#ibcon#*before return 0, iclass 16, count 0 2006.201.17:42:33.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:33.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:33.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.17:42:33.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.17:42:33.66$vck44/va=6,5 2006.201.17:42:33.66#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.17:42:33.66#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.17:42:33.66#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:33.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:33.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:33.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:33.72#ibcon#enter wrdev, iclass 18, count 2 2006.201.17:42:33.72#ibcon#first serial, iclass 18, count 2 2006.201.17:42:33.72#ibcon#enter sib2, iclass 18, count 2 2006.201.17:42:33.72#ibcon#flushed, iclass 18, count 2 2006.201.17:42:33.72#ibcon#about to write, iclass 18, count 2 2006.201.17:42:33.72#ibcon#wrote, iclass 18, count 2 2006.201.17:42:33.72#ibcon#about to read 3, iclass 18, count 2 2006.201.17:42:33.74#ibcon#read 3, iclass 18, count 2 2006.201.17:42:33.74#ibcon#about to read 4, iclass 18, count 2 2006.201.17:42:33.74#ibcon#read 4, iclass 18, count 2 2006.201.17:42:33.74#ibcon#about to read 5, iclass 18, count 2 2006.201.17:42:33.74#ibcon#read 5, iclass 18, count 2 2006.201.17:42:33.74#ibcon#about to read 6, iclass 18, count 2 2006.201.17:42:33.74#ibcon#read 6, iclass 18, count 2 2006.201.17:42:33.74#ibcon#end of sib2, iclass 18, count 2 2006.201.17:42:33.74#ibcon#*mode == 0, iclass 18, count 2 2006.201.17:42:33.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.17:42:33.74#ibcon#[25=AT06-05\r\n] 2006.201.17:42:33.74#ibcon#*before write, iclass 18, count 2 2006.201.17:42:33.74#ibcon#enter sib2, iclass 18, count 2 2006.201.17:42:33.74#ibcon#flushed, iclass 18, count 2 2006.201.17:42:33.74#ibcon#about to write, iclass 18, count 2 2006.201.17:42:33.74#ibcon#wrote, iclass 18, count 2 2006.201.17:42:33.74#ibcon#about to read 3, iclass 18, count 2 2006.201.17:42:33.77#ibcon#read 3, iclass 18, count 2 2006.201.17:42:33.77#ibcon#about to read 4, iclass 18, count 2 2006.201.17:42:33.77#ibcon#read 4, iclass 18, count 2 2006.201.17:42:33.77#ibcon#about to read 5, iclass 18, count 2 2006.201.17:42:33.77#ibcon#read 5, iclass 18, count 2 2006.201.17:42:33.77#ibcon#about to read 6, iclass 18, count 2 2006.201.17:42:33.77#ibcon#read 6, iclass 18, count 2 2006.201.17:42:33.77#ibcon#end of sib2, iclass 18, count 2 2006.201.17:42:33.77#ibcon#*after write, iclass 18, count 2 2006.201.17:42:33.77#ibcon#*before return 0, iclass 18, count 2 2006.201.17:42:33.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:33.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:33.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.17:42:33.77#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:33.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:33.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:33.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:33.89#ibcon#enter wrdev, iclass 18, count 0 2006.201.17:42:33.89#ibcon#first serial, iclass 18, count 0 2006.201.17:42:33.89#ibcon#enter sib2, iclass 18, count 0 2006.201.17:42:33.89#ibcon#flushed, iclass 18, count 0 2006.201.17:42:33.89#ibcon#about to write, iclass 18, count 0 2006.201.17:42:33.89#ibcon#wrote, iclass 18, count 0 2006.201.17:42:33.89#ibcon#about to read 3, iclass 18, count 0 2006.201.17:42:33.91#ibcon#read 3, iclass 18, count 0 2006.201.17:42:33.91#ibcon#about to read 4, iclass 18, count 0 2006.201.17:42:33.91#ibcon#read 4, iclass 18, count 0 2006.201.17:42:33.91#ibcon#about to read 5, iclass 18, count 0 2006.201.17:42:33.91#ibcon#read 5, iclass 18, count 0 2006.201.17:42:33.91#ibcon#about to read 6, iclass 18, count 0 2006.201.17:42:33.91#ibcon#read 6, iclass 18, count 0 2006.201.17:42:33.91#ibcon#end of sib2, iclass 18, count 0 2006.201.17:42:33.91#ibcon#*mode == 0, iclass 18, count 0 2006.201.17:42:33.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.17:42:33.91#ibcon#[25=USB\r\n] 2006.201.17:42:33.91#ibcon#*before write, iclass 18, count 0 2006.201.17:42:33.91#ibcon#enter sib2, iclass 18, count 0 2006.201.17:42:33.91#ibcon#flushed, iclass 18, count 0 2006.201.17:42:33.91#ibcon#about to write, iclass 18, count 0 2006.201.17:42:33.91#ibcon#wrote, iclass 18, count 0 2006.201.17:42:33.91#ibcon#about to read 3, iclass 18, count 0 2006.201.17:42:33.94#ibcon#read 3, iclass 18, count 0 2006.201.17:42:33.94#ibcon#about to read 4, iclass 18, count 0 2006.201.17:42:33.94#ibcon#read 4, iclass 18, count 0 2006.201.17:42:33.94#ibcon#about to read 5, iclass 18, count 0 2006.201.17:42:33.94#ibcon#read 5, iclass 18, count 0 2006.201.17:42:33.94#ibcon#about to read 6, iclass 18, count 0 2006.201.17:42:33.94#ibcon#read 6, iclass 18, count 0 2006.201.17:42:33.94#ibcon#end of sib2, iclass 18, count 0 2006.201.17:42:33.94#ibcon#*after write, iclass 18, count 0 2006.201.17:42:33.94#ibcon#*before return 0, iclass 18, count 0 2006.201.17:42:33.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:33.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:33.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.17:42:33.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.17:42:33.94$vck44/valo=7,864.99 2006.201.17:42:33.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.17:42:33.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.17:42:33.94#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:33.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:33.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:33.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:33.94#ibcon#enter wrdev, iclass 20, count 0 2006.201.17:42:33.94#ibcon#first serial, iclass 20, count 0 2006.201.17:42:33.94#ibcon#enter sib2, iclass 20, count 0 2006.201.17:42:33.94#ibcon#flushed, iclass 20, count 0 2006.201.17:42:33.94#ibcon#about to write, iclass 20, count 0 2006.201.17:42:33.94#ibcon#wrote, iclass 20, count 0 2006.201.17:42:33.94#ibcon#about to read 3, iclass 20, count 0 2006.201.17:42:33.96#ibcon#read 3, iclass 20, count 0 2006.201.17:42:33.96#ibcon#about to read 4, iclass 20, count 0 2006.201.17:42:33.96#ibcon#read 4, iclass 20, count 0 2006.201.17:42:33.96#ibcon#about to read 5, iclass 20, count 0 2006.201.17:42:33.96#ibcon#read 5, iclass 20, count 0 2006.201.17:42:33.96#ibcon#about to read 6, iclass 20, count 0 2006.201.17:42:33.96#ibcon#read 6, iclass 20, count 0 2006.201.17:42:33.96#ibcon#end of sib2, iclass 20, count 0 2006.201.17:42:33.96#ibcon#*mode == 0, iclass 20, count 0 2006.201.17:42:33.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.17:42:33.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.17:42:33.96#ibcon#*before write, iclass 20, count 0 2006.201.17:42:33.96#ibcon#enter sib2, iclass 20, count 0 2006.201.17:42:33.96#ibcon#flushed, iclass 20, count 0 2006.201.17:42:33.96#ibcon#about to write, iclass 20, count 0 2006.201.17:42:33.96#ibcon#wrote, iclass 20, count 0 2006.201.17:42:33.96#ibcon#about to read 3, iclass 20, count 0 2006.201.17:42:34.00#ibcon#read 3, iclass 20, count 0 2006.201.17:42:34.00#ibcon#about to read 4, iclass 20, count 0 2006.201.17:42:34.00#ibcon#read 4, iclass 20, count 0 2006.201.17:42:34.00#ibcon#about to read 5, iclass 20, count 0 2006.201.17:42:34.00#ibcon#read 5, iclass 20, count 0 2006.201.17:42:34.00#ibcon#about to read 6, iclass 20, count 0 2006.201.17:42:34.00#ibcon#read 6, iclass 20, count 0 2006.201.17:42:34.00#ibcon#end of sib2, iclass 20, count 0 2006.201.17:42:34.00#ibcon#*after write, iclass 20, count 0 2006.201.17:42:34.00#ibcon#*before return 0, iclass 20, count 0 2006.201.17:42:34.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:34.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:34.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.17:42:34.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.17:42:34.00$vck44/va=7,5 2006.201.17:42:34.00#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.17:42:34.00#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.17:42:34.00#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:34.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:34.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:34.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:34.06#ibcon#enter wrdev, iclass 22, count 2 2006.201.17:42:34.06#ibcon#first serial, iclass 22, count 2 2006.201.17:42:34.06#ibcon#enter sib2, iclass 22, count 2 2006.201.17:42:34.06#ibcon#flushed, iclass 22, count 2 2006.201.17:42:34.06#ibcon#about to write, iclass 22, count 2 2006.201.17:42:34.06#ibcon#wrote, iclass 22, count 2 2006.201.17:42:34.06#ibcon#about to read 3, iclass 22, count 2 2006.201.17:42:34.08#ibcon#read 3, iclass 22, count 2 2006.201.17:42:34.08#ibcon#about to read 4, iclass 22, count 2 2006.201.17:42:34.08#ibcon#read 4, iclass 22, count 2 2006.201.17:42:34.08#ibcon#about to read 5, iclass 22, count 2 2006.201.17:42:34.08#ibcon#read 5, iclass 22, count 2 2006.201.17:42:34.08#ibcon#about to read 6, iclass 22, count 2 2006.201.17:42:34.08#ibcon#read 6, iclass 22, count 2 2006.201.17:42:34.08#ibcon#end of sib2, iclass 22, count 2 2006.201.17:42:34.08#ibcon#*mode == 0, iclass 22, count 2 2006.201.17:42:34.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.17:42:34.08#ibcon#[25=AT07-05\r\n] 2006.201.17:42:34.08#ibcon#*before write, iclass 22, count 2 2006.201.17:42:34.08#ibcon#enter sib2, iclass 22, count 2 2006.201.17:42:34.08#ibcon#flushed, iclass 22, count 2 2006.201.17:42:34.08#ibcon#about to write, iclass 22, count 2 2006.201.17:42:34.08#ibcon#wrote, iclass 22, count 2 2006.201.17:42:34.08#ibcon#about to read 3, iclass 22, count 2 2006.201.17:42:34.11#ibcon#read 3, iclass 22, count 2 2006.201.17:42:34.11#ibcon#about to read 4, iclass 22, count 2 2006.201.17:42:34.11#ibcon#read 4, iclass 22, count 2 2006.201.17:42:34.11#ibcon#about to read 5, iclass 22, count 2 2006.201.17:42:34.11#ibcon#read 5, iclass 22, count 2 2006.201.17:42:34.11#ibcon#about to read 6, iclass 22, count 2 2006.201.17:42:34.11#ibcon#read 6, iclass 22, count 2 2006.201.17:42:34.11#ibcon#end of sib2, iclass 22, count 2 2006.201.17:42:34.11#ibcon#*after write, iclass 22, count 2 2006.201.17:42:34.11#ibcon#*before return 0, iclass 22, count 2 2006.201.17:42:34.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:34.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:34.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.17:42:34.11#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:34.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:34.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:34.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:34.23#ibcon#enter wrdev, iclass 22, count 0 2006.201.17:42:34.23#ibcon#first serial, iclass 22, count 0 2006.201.17:42:34.23#ibcon#enter sib2, iclass 22, count 0 2006.201.17:42:34.23#ibcon#flushed, iclass 22, count 0 2006.201.17:42:34.23#ibcon#about to write, iclass 22, count 0 2006.201.17:42:34.23#ibcon#wrote, iclass 22, count 0 2006.201.17:42:34.23#ibcon#about to read 3, iclass 22, count 0 2006.201.17:42:34.25#ibcon#read 3, iclass 22, count 0 2006.201.17:42:34.25#ibcon#about to read 4, iclass 22, count 0 2006.201.17:42:34.25#ibcon#read 4, iclass 22, count 0 2006.201.17:42:34.25#ibcon#about to read 5, iclass 22, count 0 2006.201.17:42:34.25#ibcon#read 5, iclass 22, count 0 2006.201.17:42:34.25#ibcon#about to read 6, iclass 22, count 0 2006.201.17:42:34.25#ibcon#read 6, iclass 22, count 0 2006.201.17:42:34.25#ibcon#end of sib2, iclass 22, count 0 2006.201.17:42:34.25#ibcon#*mode == 0, iclass 22, count 0 2006.201.17:42:34.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.17:42:34.25#ibcon#[25=USB\r\n] 2006.201.17:42:34.25#ibcon#*before write, iclass 22, count 0 2006.201.17:42:34.25#ibcon#enter sib2, iclass 22, count 0 2006.201.17:42:34.25#ibcon#flushed, iclass 22, count 0 2006.201.17:42:34.25#ibcon#about to write, iclass 22, count 0 2006.201.17:42:34.25#ibcon#wrote, iclass 22, count 0 2006.201.17:42:34.25#ibcon#about to read 3, iclass 22, count 0 2006.201.17:42:34.28#ibcon#read 3, iclass 22, count 0 2006.201.17:42:34.28#ibcon#about to read 4, iclass 22, count 0 2006.201.17:42:34.28#ibcon#read 4, iclass 22, count 0 2006.201.17:42:34.28#ibcon#about to read 5, iclass 22, count 0 2006.201.17:42:34.28#ibcon#read 5, iclass 22, count 0 2006.201.17:42:34.28#ibcon#about to read 6, iclass 22, count 0 2006.201.17:42:34.28#ibcon#read 6, iclass 22, count 0 2006.201.17:42:34.28#ibcon#end of sib2, iclass 22, count 0 2006.201.17:42:34.28#ibcon#*after write, iclass 22, count 0 2006.201.17:42:34.28#ibcon#*before return 0, iclass 22, count 0 2006.201.17:42:34.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:34.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:34.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.17:42:34.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.17:42:34.28$vck44/valo=8,884.99 2006.201.17:42:34.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.17:42:34.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.17:42:34.28#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:34.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:34.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:34.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:34.28#ibcon#enter wrdev, iclass 24, count 0 2006.201.17:42:34.28#ibcon#first serial, iclass 24, count 0 2006.201.17:42:34.28#ibcon#enter sib2, iclass 24, count 0 2006.201.17:42:34.28#ibcon#flushed, iclass 24, count 0 2006.201.17:42:34.28#ibcon#about to write, iclass 24, count 0 2006.201.17:42:34.28#ibcon#wrote, iclass 24, count 0 2006.201.17:42:34.28#ibcon#about to read 3, iclass 24, count 0 2006.201.17:42:34.30#ibcon#read 3, iclass 24, count 0 2006.201.17:42:34.30#ibcon#about to read 4, iclass 24, count 0 2006.201.17:42:34.30#ibcon#read 4, iclass 24, count 0 2006.201.17:42:34.30#ibcon#about to read 5, iclass 24, count 0 2006.201.17:42:34.30#ibcon#read 5, iclass 24, count 0 2006.201.17:42:34.30#ibcon#about to read 6, iclass 24, count 0 2006.201.17:42:34.30#ibcon#read 6, iclass 24, count 0 2006.201.17:42:34.30#ibcon#end of sib2, iclass 24, count 0 2006.201.17:42:34.30#ibcon#*mode == 0, iclass 24, count 0 2006.201.17:42:34.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.17:42:34.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.17:42:34.30#ibcon#*before write, iclass 24, count 0 2006.201.17:42:34.30#ibcon#enter sib2, iclass 24, count 0 2006.201.17:42:34.30#ibcon#flushed, iclass 24, count 0 2006.201.17:42:34.30#ibcon#about to write, iclass 24, count 0 2006.201.17:42:34.30#ibcon#wrote, iclass 24, count 0 2006.201.17:42:34.30#ibcon#about to read 3, iclass 24, count 0 2006.201.17:42:34.34#ibcon#read 3, iclass 24, count 0 2006.201.17:42:34.34#ibcon#about to read 4, iclass 24, count 0 2006.201.17:42:34.34#ibcon#read 4, iclass 24, count 0 2006.201.17:42:34.34#ibcon#about to read 5, iclass 24, count 0 2006.201.17:42:34.34#ibcon#read 5, iclass 24, count 0 2006.201.17:42:34.34#ibcon#about to read 6, iclass 24, count 0 2006.201.17:42:34.34#ibcon#read 6, iclass 24, count 0 2006.201.17:42:34.34#ibcon#end of sib2, iclass 24, count 0 2006.201.17:42:34.34#ibcon#*after write, iclass 24, count 0 2006.201.17:42:34.34#ibcon#*before return 0, iclass 24, count 0 2006.201.17:42:34.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:34.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:34.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.17:42:34.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.17:42:34.34$vck44/va=8,4 2006.201.17:42:34.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.17:42:34.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.17:42:34.34#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:34.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:42:34.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:42:34.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:42:34.40#ibcon#enter wrdev, iclass 26, count 2 2006.201.17:42:34.40#ibcon#first serial, iclass 26, count 2 2006.201.17:42:34.40#ibcon#enter sib2, iclass 26, count 2 2006.201.17:42:34.40#ibcon#flushed, iclass 26, count 2 2006.201.17:42:34.40#ibcon#about to write, iclass 26, count 2 2006.201.17:42:34.40#ibcon#wrote, iclass 26, count 2 2006.201.17:42:34.40#ibcon#about to read 3, iclass 26, count 2 2006.201.17:42:34.42#ibcon#read 3, iclass 26, count 2 2006.201.17:42:34.42#ibcon#about to read 4, iclass 26, count 2 2006.201.17:42:34.42#ibcon#read 4, iclass 26, count 2 2006.201.17:42:34.42#ibcon#about to read 5, iclass 26, count 2 2006.201.17:42:34.42#ibcon#read 5, iclass 26, count 2 2006.201.17:42:34.42#ibcon#about to read 6, iclass 26, count 2 2006.201.17:42:34.42#ibcon#read 6, iclass 26, count 2 2006.201.17:42:34.42#ibcon#end of sib2, iclass 26, count 2 2006.201.17:42:34.42#ibcon#*mode == 0, iclass 26, count 2 2006.201.17:42:34.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.17:42:34.42#ibcon#[25=AT08-04\r\n] 2006.201.17:42:34.42#ibcon#*before write, iclass 26, count 2 2006.201.17:42:34.42#ibcon#enter sib2, iclass 26, count 2 2006.201.17:42:34.42#ibcon#flushed, iclass 26, count 2 2006.201.17:42:34.42#ibcon#about to write, iclass 26, count 2 2006.201.17:42:34.42#ibcon#wrote, iclass 26, count 2 2006.201.17:42:34.42#ibcon#about to read 3, iclass 26, count 2 2006.201.17:42:34.45#ibcon#read 3, iclass 26, count 2 2006.201.17:42:34.45#ibcon#about to read 4, iclass 26, count 2 2006.201.17:42:34.45#ibcon#read 4, iclass 26, count 2 2006.201.17:42:34.45#ibcon#about to read 5, iclass 26, count 2 2006.201.17:42:34.45#ibcon#read 5, iclass 26, count 2 2006.201.17:42:34.45#ibcon#about to read 6, iclass 26, count 2 2006.201.17:42:34.45#ibcon#read 6, iclass 26, count 2 2006.201.17:42:34.45#ibcon#end of sib2, iclass 26, count 2 2006.201.17:42:34.45#ibcon#*after write, iclass 26, count 2 2006.201.17:42:34.45#ibcon#*before return 0, iclass 26, count 2 2006.201.17:42:34.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:42:34.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.17:42:34.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.17:42:34.45#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:34.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:42:34.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:42:34.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:42:34.57#ibcon#enter wrdev, iclass 26, count 0 2006.201.17:42:34.57#ibcon#first serial, iclass 26, count 0 2006.201.17:42:34.57#ibcon#enter sib2, iclass 26, count 0 2006.201.17:42:34.57#ibcon#flushed, iclass 26, count 0 2006.201.17:42:34.57#ibcon#about to write, iclass 26, count 0 2006.201.17:42:34.57#ibcon#wrote, iclass 26, count 0 2006.201.17:42:34.57#ibcon#about to read 3, iclass 26, count 0 2006.201.17:42:34.59#ibcon#read 3, iclass 26, count 0 2006.201.17:42:34.59#ibcon#about to read 4, iclass 26, count 0 2006.201.17:42:34.59#ibcon#read 4, iclass 26, count 0 2006.201.17:42:34.59#ibcon#about to read 5, iclass 26, count 0 2006.201.17:42:34.59#ibcon#read 5, iclass 26, count 0 2006.201.17:42:34.59#ibcon#about to read 6, iclass 26, count 0 2006.201.17:42:34.59#ibcon#read 6, iclass 26, count 0 2006.201.17:42:34.59#ibcon#end of sib2, iclass 26, count 0 2006.201.17:42:34.59#ibcon#*mode == 0, iclass 26, count 0 2006.201.17:42:34.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.17:42:34.59#ibcon#[25=USB\r\n] 2006.201.17:42:34.59#ibcon#*before write, iclass 26, count 0 2006.201.17:42:34.59#ibcon#enter sib2, iclass 26, count 0 2006.201.17:42:34.59#ibcon#flushed, iclass 26, count 0 2006.201.17:42:34.59#ibcon#about to write, iclass 26, count 0 2006.201.17:42:34.59#ibcon#wrote, iclass 26, count 0 2006.201.17:42:34.59#ibcon#about to read 3, iclass 26, count 0 2006.201.17:42:34.62#ibcon#read 3, iclass 26, count 0 2006.201.17:42:34.62#ibcon#about to read 4, iclass 26, count 0 2006.201.17:42:34.62#ibcon#read 4, iclass 26, count 0 2006.201.17:42:34.62#ibcon#about to read 5, iclass 26, count 0 2006.201.17:42:34.62#ibcon#read 5, iclass 26, count 0 2006.201.17:42:34.62#ibcon#about to read 6, iclass 26, count 0 2006.201.17:42:34.62#ibcon#read 6, iclass 26, count 0 2006.201.17:42:34.62#ibcon#end of sib2, iclass 26, count 0 2006.201.17:42:34.62#ibcon#*after write, iclass 26, count 0 2006.201.17:42:34.62#ibcon#*before return 0, iclass 26, count 0 2006.201.17:42:34.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:42:34.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.17:42:34.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.17:42:34.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.17:42:34.62$vck44/vblo=1,629.99 2006.201.17:42:34.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.17:42:34.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.17:42:34.62#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:34.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:34.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:34.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:34.62#ibcon#enter wrdev, iclass 28, count 0 2006.201.17:42:34.62#ibcon#first serial, iclass 28, count 0 2006.201.17:42:34.62#ibcon#enter sib2, iclass 28, count 0 2006.201.17:42:34.62#ibcon#flushed, iclass 28, count 0 2006.201.17:42:34.62#ibcon#about to write, iclass 28, count 0 2006.201.17:42:34.62#ibcon#wrote, iclass 28, count 0 2006.201.17:42:34.62#ibcon#about to read 3, iclass 28, count 0 2006.201.17:42:34.64#ibcon#read 3, iclass 28, count 0 2006.201.17:42:34.64#ibcon#about to read 4, iclass 28, count 0 2006.201.17:42:34.64#ibcon#read 4, iclass 28, count 0 2006.201.17:42:34.64#ibcon#about to read 5, iclass 28, count 0 2006.201.17:42:34.64#ibcon#read 5, iclass 28, count 0 2006.201.17:42:34.64#ibcon#about to read 6, iclass 28, count 0 2006.201.17:42:34.64#ibcon#read 6, iclass 28, count 0 2006.201.17:42:34.64#ibcon#end of sib2, iclass 28, count 0 2006.201.17:42:34.64#ibcon#*mode == 0, iclass 28, count 0 2006.201.17:42:34.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.17:42:34.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.17:42:34.64#ibcon#*before write, iclass 28, count 0 2006.201.17:42:34.64#ibcon#enter sib2, iclass 28, count 0 2006.201.17:42:34.64#ibcon#flushed, iclass 28, count 0 2006.201.17:42:34.64#ibcon#about to write, iclass 28, count 0 2006.201.17:42:34.64#ibcon#wrote, iclass 28, count 0 2006.201.17:42:34.64#ibcon#about to read 3, iclass 28, count 0 2006.201.17:42:34.69#ibcon#read 3, iclass 28, count 0 2006.201.17:42:34.69#ibcon#about to read 4, iclass 28, count 0 2006.201.17:42:34.69#ibcon#read 4, iclass 28, count 0 2006.201.17:42:34.69#ibcon#about to read 5, iclass 28, count 0 2006.201.17:42:34.69#ibcon#read 5, iclass 28, count 0 2006.201.17:42:34.69#ibcon#about to read 6, iclass 28, count 0 2006.201.17:42:34.69#ibcon#read 6, iclass 28, count 0 2006.201.17:42:34.69#ibcon#end of sib2, iclass 28, count 0 2006.201.17:42:34.69#ibcon#*after write, iclass 28, count 0 2006.201.17:42:34.69#ibcon#*before return 0, iclass 28, count 0 2006.201.17:42:34.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:34.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.17:42:34.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.17:42:34.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.17:42:34.69$vck44/vb=1,4 2006.201.17:42:34.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.17:42:34.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.17:42:34.69#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:34.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:34.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:34.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:34.69#ibcon#enter wrdev, iclass 30, count 2 2006.201.17:42:34.69#ibcon#first serial, iclass 30, count 2 2006.201.17:42:34.69#ibcon#enter sib2, iclass 30, count 2 2006.201.17:42:34.69#ibcon#flushed, iclass 30, count 2 2006.201.17:42:34.69#ibcon#about to write, iclass 30, count 2 2006.201.17:42:34.69#ibcon#wrote, iclass 30, count 2 2006.201.17:42:34.69#ibcon#about to read 3, iclass 30, count 2 2006.201.17:42:34.71#ibcon#read 3, iclass 30, count 2 2006.201.17:42:34.71#ibcon#about to read 4, iclass 30, count 2 2006.201.17:42:34.71#ibcon#read 4, iclass 30, count 2 2006.201.17:42:34.71#ibcon#about to read 5, iclass 30, count 2 2006.201.17:42:34.71#ibcon#read 5, iclass 30, count 2 2006.201.17:42:34.71#ibcon#about to read 6, iclass 30, count 2 2006.201.17:42:34.71#ibcon#read 6, iclass 30, count 2 2006.201.17:42:34.71#ibcon#end of sib2, iclass 30, count 2 2006.201.17:42:34.71#ibcon#*mode == 0, iclass 30, count 2 2006.201.17:42:34.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.17:42:34.71#ibcon#[27=AT01-04\r\n] 2006.201.17:42:34.71#ibcon#*before write, iclass 30, count 2 2006.201.17:42:34.71#ibcon#enter sib2, iclass 30, count 2 2006.201.17:42:34.71#ibcon#flushed, iclass 30, count 2 2006.201.17:42:34.71#ibcon#about to write, iclass 30, count 2 2006.201.17:42:34.71#ibcon#wrote, iclass 30, count 2 2006.201.17:42:34.71#ibcon#about to read 3, iclass 30, count 2 2006.201.17:42:34.74#ibcon#read 3, iclass 30, count 2 2006.201.17:42:34.74#ibcon#about to read 4, iclass 30, count 2 2006.201.17:42:34.74#ibcon#read 4, iclass 30, count 2 2006.201.17:42:34.74#ibcon#about to read 5, iclass 30, count 2 2006.201.17:42:34.74#ibcon#read 5, iclass 30, count 2 2006.201.17:42:34.74#ibcon#about to read 6, iclass 30, count 2 2006.201.17:42:34.74#ibcon#read 6, iclass 30, count 2 2006.201.17:42:34.74#ibcon#end of sib2, iclass 30, count 2 2006.201.17:42:34.74#ibcon#*after write, iclass 30, count 2 2006.201.17:42:34.74#ibcon#*before return 0, iclass 30, count 2 2006.201.17:42:34.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:34.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.17:42:34.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.17:42:34.74#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:34.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:34.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:34.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:34.86#ibcon#enter wrdev, iclass 30, count 0 2006.201.17:42:34.86#ibcon#first serial, iclass 30, count 0 2006.201.17:42:34.86#ibcon#enter sib2, iclass 30, count 0 2006.201.17:42:34.86#ibcon#flushed, iclass 30, count 0 2006.201.17:42:34.86#ibcon#about to write, iclass 30, count 0 2006.201.17:42:34.86#ibcon#wrote, iclass 30, count 0 2006.201.17:42:34.86#ibcon#about to read 3, iclass 30, count 0 2006.201.17:42:34.88#ibcon#read 3, iclass 30, count 0 2006.201.17:42:34.88#ibcon#about to read 4, iclass 30, count 0 2006.201.17:42:34.88#ibcon#read 4, iclass 30, count 0 2006.201.17:42:34.88#ibcon#about to read 5, iclass 30, count 0 2006.201.17:42:34.88#ibcon#read 5, iclass 30, count 0 2006.201.17:42:34.88#ibcon#about to read 6, iclass 30, count 0 2006.201.17:42:34.88#ibcon#read 6, iclass 30, count 0 2006.201.17:42:34.88#ibcon#end of sib2, iclass 30, count 0 2006.201.17:42:34.88#ibcon#*mode == 0, iclass 30, count 0 2006.201.17:42:34.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.17:42:34.88#ibcon#[27=USB\r\n] 2006.201.17:42:34.88#ibcon#*before write, iclass 30, count 0 2006.201.17:42:34.88#ibcon#enter sib2, iclass 30, count 0 2006.201.17:42:34.88#ibcon#flushed, iclass 30, count 0 2006.201.17:42:34.88#ibcon#about to write, iclass 30, count 0 2006.201.17:42:34.88#ibcon#wrote, iclass 30, count 0 2006.201.17:42:34.88#ibcon#about to read 3, iclass 30, count 0 2006.201.17:42:34.91#ibcon#read 3, iclass 30, count 0 2006.201.17:42:34.91#ibcon#about to read 4, iclass 30, count 0 2006.201.17:42:34.91#ibcon#read 4, iclass 30, count 0 2006.201.17:42:34.91#ibcon#about to read 5, iclass 30, count 0 2006.201.17:42:34.91#ibcon#read 5, iclass 30, count 0 2006.201.17:42:34.91#ibcon#about to read 6, iclass 30, count 0 2006.201.17:42:34.91#ibcon#read 6, iclass 30, count 0 2006.201.17:42:34.91#ibcon#end of sib2, iclass 30, count 0 2006.201.17:42:34.91#ibcon#*after write, iclass 30, count 0 2006.201.17:42:34.91#ibcon#*before return 0, iclass 30, count 0 2006.201.17:42:34.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:34.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.17:42:34.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.17:42:34.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.17:42:34.91$vck44/vblo=2,634.99 2006.201.17:42:34.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.17:42:34.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.17:42:34.91#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:34.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:34.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:34.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:34.91#ibcon#enter wrdev, iclass 32, count 0 2006.201.17:42:34.91#ibcon#first serial, iclass 32, count 0 2006.201.17:42:34.91#ibcon#enter sib2, iclass 32, count 0 2006.201.17:42:34.91#ibcon#flushed, iclass 32, count 0 2006.201.17:42:34.91#ibcon#about to write, iclass 32, count 0 2006.201.17:42:34.91#ibcon#wrote, iclass 32, count 0 2006.201.17:42:34.91#ibcon#about to read 3, iclass 32, count 0 2006.201.17:42:34.93#ibcon#read 3, iclass 32, count 0 2006.201.17:42:34.93#ibcon#about to read 4, iclass 32, count 0 2006.201.17:42:34.93#ibcon#read 4, iclass 32, count 0 2006.201.17:42:34.93#ibcon#about to read 5, iclass 32, count 0 2006.201.17:42:34.93#ibcon#read 5, iclass 32, count 0 2006.201.17:42:34.93#ibcon#about to read 6, iclass 32, count 0 2006.201.17:42:34.93#ibcon#read 6, iclass 32, count 0 2006.201.17:42:34.93#ibcon#end of sib2, iclass 32, count 0 2006.201.17:42:34.93#ibcon#*mode == 0, iclass 32, count 0 2006.201.17:42:34.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.17:42:34.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.17:42:34.93#ibcon#*before write, iclass 32, count 0 2006.201.17:42:34.93#ibcon#enter sib2, iclass 32, count 0 2006.201.17:42:34.93#ibcon#flushed, iclass 32, count 0 2006.201.17:42:34.93#ibcon#about to write, iclass 32, count 0 2006.201.17:42:34.93#ibcon#wrote, iclass 32, count 0 2006.201.17:42:34.93#ibcon#about to read 3, iclass 32, count 0 2006.201.17:42:34.97#ibcon#read 3, iclass 32, count 0 2006.201.17:42:34.97#ibcon#about to read 4, iclass 32, count 0 2006.201.17:42:34.97#ibcon#read 4, iclass 32, count 0 2006.201.17:42:34.97#ibcon#about to read 5, iclass 32, count 0 2006.201.17:42:34.97#ibcon#read 5, iclass 32, count 0 2006.201.17:42:34.97#ibcon#about to read 6, iclass 32, count 0 2006.201.17:42:34.97#ibcon#read 6, iclass 32, count 0 2006.201.17:42:34.97#ibcon#end of sib2, iclass 32, count 0 2006.201.17:42:34.97#ibcon#*after write, iclass 32, count 0 2006.201.17:42:34.97#ibcon#*before return 0, iclass 32, count 0 2006.201.17:42:34.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:34.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.17:42:34.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.17:42:34.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.17:42:34.97$vck44/vb=2,5 2006.201.17:42:34.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.17:42:34.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.17:42:34.97#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:34.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:35.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:35.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:35.03#ibcon#enter wrdev, iclass 34, count 2 2006.201.17:42:35.03#ibcon#first serial, iclass 34, count 2 2006.201.17:42:35.03#ibcon#enter sib2, iclass 34, count 2 2006.201.17:42:35.03#ibcon#flushed, iclass 34, count 2 2006.201.17:42:35.03#ibcon#about to write, iclass 34, count 2 2006.201.17:42:35.03#ibcon#wrote, iclass 34, count 2 2006.201.17:42:35.03#ibcon#about to read 3, iclass 34, count 2 2006.201.17:42:35.05#ibcon#read 3, iclass 34, count 2 2006.201.17:42:35.05#ibcon#about to read 4, iclass 34, count 2 2006.201.17:42:35.05#ibcon#read 4, iclass 34, count 2 2006.201.17:42:35.05#ibcon#about to read 5, iclass 34, count 2 2006.201.17:42:35.05#ibcon#read 5, iclass 34, count 2 2006.201.17:42:35.05#ibcon#about to read 6, iclass 34, count 2 2006.201.17:42:35.05#ibcon#read 6, iclass 34, count 2 2006.201.17:42:35.05#ibcon#end of sib2, iclass 34, count 2 2006.201.17:42:35.05#ibcon#*mode == 0, iclass 34, count 2 2006.201.17:42:35.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.17:42:35.05#ibcon#[27=AT02-05\r\n] 2006.201.17:42:35.05#ibcon#*before write, iclass 34, count 2 2006.201.17:42:35.05#ibcon#enter sib2, iclass 34, count 2 2006.201.17:42:35.05#ibcon#flushed, iclass 34, count 2 2006.201.17:42:35.05#ibcon#about to write, iclass 34, count 2 2006.201.17:42:35.05#ibcon#wrote, iclass 34, count 2 2006.201.17:42:35.05#ibcon#about to read 3, iclass 34, count 2 2006.201.17:42:35.08#ibcon#read 3, iclass 34, count 2 2006.201.17:42:35.08#ibcon#about to read 4, iclass 34, count 2 2006.201.17:42:35.08#ibcon#read 4, iclass 34, count 2 2006.201.17:42:35.08#ibcon#about to read 5, iclass 34, count 2 2006.201.17:42:35.08#ibcon#read 5, iclass 34, count 2 2006.201.17:42:35.08#ibcon#about to read 6, iclass 34, count 2 2006.201.17:42:35.08#ibcon#read 6, iclass 34, count 2 2006.201.17:42:35.08#ibcon#end of sib2, iclass 34, count 2 2006.201.17:42:35.08#ibcon#*after write, iclass 34, count 2 2006.201.17:42:35.08#ibcon#*before return 0, iclass 34, count 2 2006.201.17:42:35.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:35.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.17:42:35.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.17:42:35.08#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:35.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:35.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:35.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:35.20#ibcon#enter wrdev, iclass 34, count 0 2006.201.17:42:35.20#ibcon#first serial, iclass 34, count 0 2006.201.17:42:35.20#ibcon#enter sib2, iclass 34, count 0 2006.201.17:42:35.20#ibcon#flushed, iclass 34, count 0 2006.201.17:42:35.20#ibcon#about to write, iclass 34, count 0 2006.201.17:42:35.20#ibcon#wrote, iclass 34, count 0 2006.201.17:42:35.20#ibcon#about to read 3, iclass 34, count 0 2006.201.17:42:35.22#ibcon#read 3, iclass 34, count 0 2006.201.17:42:35.22#ibcon#about to read 4, iclass 34, count 0 2006.201.17:42:35.22#ibcon#read 4, iclass 34, count 0 2006.201.17:42:35.22#ibcon#about to read 5, iclass 34, count 0 2006.201.17:42:35.22#ibcon#read 5, iclass 34, count 0 2006.201.17:42:35.22#ibcon#about to read 6, iclass 34, count 0 2006.201.17:42:35.22#ibcon#read 6, iclass 34, count 0 2006.201.17:42:35.22#ibcon#end of sib2, iclass 34, count 0 2006.201.17:42:35.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.17:42:35.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.17:42:35.22#ibcon#[27=USB\r\n] 2006.201.17:42:35.22#ibcon#*before write, iclass 34, count 0 2006.201.17:42:35.22#ibcon#enter sib2, iclass 34, count 0 2006.201.17:42:35.22#ibcon#flushed, iclass 34, count 0 2006.201.17:42:35.22#ibcon#about to write, iclass 34, count 0 2006.201.17:42:35.22#ibcon#wrote, iclass 34, count 0 2006.201.17:42:35.22#ibcon#about to read 3, iclass 34, count 0 2006.201.17:42:35.25#ibcon#read 3, iclass 34, count 0 2006.201.17:42:35.25#ibcon#about to read 4, iclass 34, count 0 2006.201.17:42:35.25#ibcon#read 4, iclass 34, count 0 2006.201.17:42:35.25#ibcon#about to read 5, iclass 34, count 0 2006.201.17:42:35.25#ibcon#read 5, iclass 34, count 0 2006.201.17:42:35.25#ibcon#about to read 6, iclass 34, count 0 2006.201.17:42:35.25#ibcon#read 6, iclass 34, count 0 2006.201.17:42:35.25#ibcon#end of sib2, iclass 34, count 0 2006.201.17:42:35.25#ibcon#*after write, iclass 34, count 0 2006.201.17:42:35.25#ibcon#*before return 0, iclass 34, count 0 2006.201.17:42:35.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:35.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.17:42:35.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.17:42:35.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.17:42:35.25$vck44/vblo=3,649.99 2006.201.17:42:35.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.17:42:35.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.17:42:35.25#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:35.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:42:35.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:42:35.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:42:35.25#ibcon#enter wrdev, iclass 36, count 0 2006.201.17:42:35.25#ibcon#first serial, iclass 36, count 0 2006.201.17:42:35.25#ibcon#enter sib2, iclass 36, count 0 2006.201.17:42:35.25#ibcon#flushed, iclass 36, count 0 2006.201.17:42:35.25#ibcon#about to write, iclass 36, count 0 2006.201.17:42:35.25#ibcon#wrote, iclass 36, count 0 2006.201.17:42:35.25#ibcon#about to read 3, iclass 36, count 0 2006.201.17:42:35.27#ibcon#read 3, iclass 36, count 0 2006.201.17:42:35.27#ibcon#about to read 4, iclass 36, count 0 2006.201.17:42:35.27#ibcon#read 4, iclass 36, count 0 2006.201.17:42:35.27#ibcon#about to read 5, iclass 36, count 0 2006.201.17:42:35.27#ibcon#read 5, iclass 36, count 0 2006.201.17:42:35.27#ibcon#about to read 6, iclass 36, count 0 2006.201.17:42:35.27#ibcon#read 6, iclass 36, count 0 2006.201.17:42:35.27#ibcon#end of sib2, iclass 36, count 0 2006.201.17:42:35.27#ibcon#*mode == 0, iclass 36, count 0 2006.201.17:42:35.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.17:42:35.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.17:42:35.27#ibcon#*before write, iclass 36, count 0 2006.201.17:42:35.27#ibcon#enter sib2, iclass 36, count 0 2006.201.17:42:35.27#ibcon#flushed, iclass 36, count 0 2006.201.17:42:35.27#ibcon#about to write, iclass 36, count 0 2006.201.17:42:35.27#ibcon#wrote, iclass 36, count 0 2006.201.17:42:35.27#ibcon#about to read 3, iclass 36, count 0 2006.201.17:42:35.32#ibcon#read 3, iclass 36, count 0 2006.201.17:42:35.32#ibcon#about to read 4, iclass 36, count 0 2006.201.17:42:35.32#ibcon#read 4, iclass 36, count 0 2006.201.17:42:35.32#ibcon#about to read 5, iclass 36, count 0 2006.201.17:42:35.32#ibcon#read 5, iclass 36, count 0 2006.201.17:42:35.32#ibcon#about to read 6, iclass 36, count 0 2006.201.17:42:35.32#ibcon#read 6, iclass 36, count 0 2006.201.17:42:35.32#ibcon#end of sib2, iclass 36, count 0 2006.201.17:42:35.32#ibcon#*after write, iclass 36, count 0 2006.201.17:42:35.32#ibcon#*before return 0, iclass 36, count 0 2006.201.17:42:35.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:42:35.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:42:35.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.17:42:35.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.17:42:35.32$vck44/vb=3,4 2006.201.17:42:35.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.17:42:35.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.17:42:35.32#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:35.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:42:35.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:42:35.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:42:35.37#ibcon#enter wrdev, iclass 38, count 2 2006.201.17:42:35.37#ibcon#first serial, iclass 38, count 2 2006.201.17:42:35.37#ibcon#enter sib2, iclass 38, count 2 2006.201.17:42:35.37#ibcon#flushed, iclass 38, count 2 2006.201.17:42:35.37#ibcon#about to write, iclass 38, count 2 2006.201.17:42:35.37#ibcon#wrote, iclass 38, count 2 2006.201.17:42:35.37#ibcon#about to read 3, iclass 38, count 2 2006.201.17:42:35.39#ibcon#read 3, iclass 38, count 2 2006.201.17:42:35.39#ibcon#about to read 4, iclass 38, count 2 2006.201.17:42:35.39#ibcon#read 4, iclass 38, count 2 2006.201.17:42:35.39#ibcon#about to read 5, iclass 38, count 2 2006.201.17:42:35.39#ibcon#read 5, iclass 38, count 2 2006.201.17:42:35.39#ibcon#about to read 6, iclass 38, count 2 2006.201.17:42:35.39#ibcon#read 6, iclass 38, count 2 2006.201.17:42:35.39#ibcon#end of sib2, iclass 38, count 2 2006.201.17:42:35.39#ibcon#*mode == 0, iclass 38, count 2 2006.201.17:42:35.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.17:42:35.39#ibcon#[27=AT03-04\r\n] 2006.201.17:42:35.39#ibcon#*before write, iclass 38, count 2 2006.201.17:42:35.39#ibcon#enter sib2, iclass 38, count 2 2006.201.17:42:35.39#ibcon#flushed, iclass 38, count 2 2006.201.17:42:35.39#ibcon#about to write, iclass 38, count 2 2006.201.17:42:35.39#ibcon#wrote, iclass 38, count 2 2006.201.17:42:35.39#ibcon#about to read 3, iclass 38, count 2 2006.201.17:42:35.42#ibcon#read 3, iclass 38, count 2 2006.201.17:42:35.42#ibcon#about to read 4, iclass 38, count 2 2006.201.17:42:35.42#ibcon#read 4, iclass 38, count 2 2006.201.17:42:35.42#ibcon#about to read 5, iclass 38, count 2 2006.201.17:42:35.42#ibcon#read 5, iclass 38, count 2 2006.201.17:42:35.42#ibcon#about to read 6, iclass 38, count 2 2006.201.17:42:35.42#ibcon#read 6, iclass 38, count 2 2006.201.17:42:35.42#ibcon#end of sib2, iclass 38, count 2 2006.201.17:42:35.42#ibcon#*after write, iclass 38, count 2 2006.201.17:42:35.42#ibcon#*before return 0, iclass 38, count 2 2006.201.17:42:35.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:42:35.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.17:42:35.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.17:42:35.42#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:35.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:42:35.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:42:35.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:42:35.54#ibcon#enter wrdev, iclass 38, count 0 2006.201.17:42:35.54#ibcon#first serial, iclass 38, count 0 2006.201.17:42:35.54#ibcon#enter sib2, iclass 38, count 0 2006.201.17:42:35.54#ibcon#flushed, iclass 38, count 0 2006.201.17:42:35.54#ibcon#about to write, iclass 38, count 0 2006.201.17:42:35.54#ibcon#wrote, iclass 38, count 0 2006.201.17:42:35.54#ibcon#about to read 3, iclass 38, count 0 2006.201.17:42:35.56#ibcon#read 3, iclass 38, count 0 2006.201.17:42:35.56#ibcon#about to read 4, iclass 38, count 0 2006.201.17:42:35.56#ibcon#read 4, iclass 38, count 0 2006.201.17:42:35.56#ibcon#about to read 5, iclass 38, count 0 2006.201.17:42:35.56#ibcon#read 5, iclass 38, count 0 2006.201.17:42:35.56#ibcon#about to read 6, iclass 38, count 0 2006.201.17:42:35.56#ibcon#read 6, iclass 38, count 0 2006.201.17:42:35.56#ibcon#end of sib2, iclass 38, count 0 2006.201.17:42:35.56#ibcon#*mode == 0, iclass 38, count 0 2006.201.17:42:35.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.17:42:35.56#ibcon#[27=USB\r\n] 2006.201.17:42:35.56#ibcon#*before write, iclass 38, count 0 2006.201.17:42:35.56#ibcon#enter sib2, iclass 38, count 0 2006.201.17:42:35.56#ibcon#flushed, iclass 38, count 0 2006.201.17:42:35.56#ibcon#about to write, iclass 38, count 0 2006.201.17:42:35.56#ibcon#wrote, iclass 38, count 0 2006.201.17:42:35.56#ibcon#about to read 3, iclass 38, count 0 2006.201.17:42:35.59#ibcon#read 3, iclass 38, count 0 2006.201.17:42:35.59#ibcon#about to read 4, iclass 38, count 0 2006.201.17:42:35.59#ibcon#read 4, iclass 38, count 0 2006.201.17:42:35.59#ibcon#about to read 5, iclass 38, count 0 2006.201.17:42:35.59#ibcon#read 5, iclass 38, count 0 2006.201.17:42:35.59#ibcon#about to read 6, iclass 38, count 0 2006.201.17:42:35.59#ibcon#read 6, iclass 38, count 0 2006.201.17:42:35.59#ibcon#end of sib2, iclass 38, count 0 2006.201.17:42:35.59#ibcon#*after write, iclass 38, count 0 2006.201.17:42:35.59#ibcon#*before return 0, iclass 38, count 0 2006.201.17:42:35.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:42:35.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.17:42:35.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.17:42:35.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.17:42:35.59$vck44/vblo=4,679.99 2006.201.17:42:35.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.17:42:35.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.17:42:35.59#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:35.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:35.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:35.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:35.59#ibcon#enter wrdev, iclass 40, count 0 2006.201.17:42:35.59#ibcon#first serial, iclass 40, count 0 2006.201.17:42:35.59#ibcon#enter sib2, iclass 40, count 0 2006.201.17:42:35.59#ibcon#flushed, iclass 40, count 0 2006.201.17:42:35.59#ibcon#about to write, iclass 40, count 0 2006.201.17:42:35.59#ibcon#wrote, iclass 40, count 0 2006.201.17:42:35.59#ibcon#about to read 3, iclass 40, count 0 2006.201.17:42:35.61#ibcon#read 3, iclass 40, count 0 2006.201.17:42:35.61#ibcon#about to read 4, iclass 40, count 0 2006.201.17:42:35.61#ibcon#read 4, iclass 40, count 0 2006.201.17:42:35.61#ibcon#about to read 5, iclass 40, count 0 2006.201.17:42:35.61#ibcon#read 5, iclass 40, count 0 2006.201.17:42:35.61#ibcon#about to read 6, iclass 40, count 0 2006.201.17:42:35.61#ibcon#read 6, iclass 40, count 0 2006.201.17:42:35.61#ibcon#end of sib2, iclass 40, count 0 2006.201.17:42:35.61#ibcon#*mode == 0, iclass 40, count 0 2006.201.17:42:35.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.17:42:35.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.17:42:35.61#ibcon#*before write, iclass 40, count 0 2006.201.17:42:35.61#ibcon#enter sib2, iclass 40, count 0 2006.201.17:42:35.61#ibcon#flushed, iclass 40, count 0 2006.201.17:42:35.61#ibcon#about to write, iclass 40, count 0 2006.201.17:42:35.61#ibcon#wrote, iclass 40, count 0 2006.201.17:42:35.61#ibcon#about to read 3, iclass 40, count 0 2006.201.17:42:35.65#ibcon#read 3, iclass 40, count 0 2006.201.17:42:35.65#ibcon#about to read 4, iclass 40, count 0 2006.201.17:42:35.65#ibcon#read 4, iclass 40, count 0 2006.201.17:42:35.65#ibcon#about to read 5, iclass 40, count 0 2006.201.17:42:35.65#ibcon#read 5, iclass 40, count 0 2006.201.17:42:35.65#ibcon#about to read 6, iclass 40, count 0 2006.201.17:42:35.65#ibcon#read 6, iclass 40, count 0 2006.201.17:42:35.65#ibcon#end of sib2, iclass 40, count 0 2006.201.17:42:35.65#ibcon#*after write, iclass 40, count 0 2006.201.17:42:35.65#ibcon#*before return 0, iclass 40, count 0 2006.201.17:42:35.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:35.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.17:42:35.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.17:42:35.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.17:42:35.65$vck44/vb=4,5 2006.201.17:42:35.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.17:42:35.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.17:42:35.65#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:35.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:35.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:35.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:35.71#ibcon#enter wrdev, iclass 4, count 2 2006.201.17:42:35.71#ibcon#first serial, iclass 4, count 2 2006.201.17:42:35.71#ibcon#enter sib2, iclass 4, count 2 2006.201.17:42:35.71#ibcon#flushed, iclass 4, count 2 2006.201.17:42:35.71#ibcon#about to write, iclass 4, count 2 2006.201.17:42:35.71#ibcon#wrote, iclass 4, count 2 2006.201.17:42:35.71#ibcon#about to read 3, iclass 4, count 2 2006.201.17:42:35.73#ibcon#read 3, iclass 4, count 2 2006.201.17:42:35.73#ibcon#about to read 4, iclass 4, count 2 2006.201.17:42:35.73#ibcon#read 4, iclass 4, count 2 2006.201.17:42:35.73#ibcon#about to read 5, iclass 4, count 2 2006.201.17:42:35.73#ibcon#read 5, iclass 4, count 2 2006.201.17:42:35.73#ibcon#about to read 6, iclass 4, count 2 2006.201.17:42:35.73#ibcon#read 6, iclass 4, count 2 2006.201.17:42:35.73#ibcon#end of sib2, iclass 4, count 2 2006.201.17:42:35.73#ibcon#*mode == 0, iclass 4, count 2 2006.201.17:42:35.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.17:42:35.73#ibcon#[27=AT04-05\r\n] 2006.201.17:42:35.73#ibcon#*before write, iclass 4, count 2 2006.201.17:42:35.73#ibcon#enter sib2, iclass 4, count 2 2006.201.17:42:35.73#ibcon#flushed, iclass 4, count 2 2006.201.17:42:35.73#ibcon#about to write, iclass 4, count 2 2006.201.17:42:35.73#ibcon#wrote, iclass 4, count 2 2006.201.17:42:35.73#ibcon#about to read 3, iclass 4, count 2 2006.201.17:42:35.76#ibcon#read 3, iclass 4, count 2 2006.201.17:42:35.76#ibcon#about to read 4, iclass 4, count 2 2006.201.17:42:35.76#ibcon#read 4, iclass 4, count 2 2006.201.17:42:35.76#ibcon#about to read 5, iclass 4, count 2 2006.201.17:42:35.76#ibcon#read 5, iclass 4, count 2 2006.201.17:42:35.76#ibcon#about to read 6, iclass 4, count 2 2006.201.17:42:35.76#ibcon#read 6, iclass 4, count 2 2006.201.17:42:35.76#ibcon#end of sib2, iclass 4, count 2 2006.201.17:42:35.76#ibcon#*after write, iclass 4, count 2 2006.201.17:42:35.76#ibcon#*before return 0, iclass 4, count 2 2006.201.17:42:35.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:35.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.17:42:35.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.17:42:35.76#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:35.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:35.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:35.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:35.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.17:42:35.88#ibcon#first serial, iclass 4, count 0 2006.201.17:42:35.88#ibcon#enter sib2, iclass 4, count 0 2006.201.17:42:35.88#ibcon#flushed, iclass 4, count 0 2006.201.17:42:35.88#ibcon#about to write, iclass 4, count 0 2006.201.17:42:35.88#ibcon#wrote, iclass 4, count 0 2006.201.17:42:35.88#ibcon#about to read 3, iclass 4, count 0 2006.201.17:42:35.90#ibcon#read 3, iclass 4, count 0 2006.201.17:42:35.90#ibcon#about to read 4, iclass 4, count 0 2006.201.17:42:35.90#ibcon#read 4, iclass 4, count 0 2006.201.17:42:35.90#ibcon#about to read 5, iclass 4, count 0 2006.201.17:42:35.90#ibcon#read 5, iclass 4, count 0 2006.201.17:42:35.90#ibcon#about to read 6, iclass 4, count 0 2006.201.17:42:35.90#ibcon#read 6, iclass 4, count 0 2006.201.17:42:35.90#ibcon#end of sib2, iclass 4, count 0 2006.201.17:42:35.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.17:42:35.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.17:42:35.90#ibcon#[27=USB\r\n] 2006.201.17:42:35.90#ibcon#*before write, iclass 4, count 0 2006.201.17:42:35.90#ibcon#enter sib2, iclass 4, count 0 2006.201.17:42:35.90#ibcon#flushed, iclass 4, count 0 2006.201.17:42:35.90#ibcon#about to write, iclass 4, count 0 2006.201.17:42:35.90#ibcon#wrote, iclass 4, count 0 2006.201.17:42:35.90#ibcon#about to read 3, iclass 4, count 0 2006.201.17:42:35.93#ibcon#read 3, iclass 4, count 0 2006.201.17:42:35.93#ibcon#about to read 4, iclass 4, count 0 2006.201.17:42:35.93#ibcon#read 4, iclass 4, count 0 2006.201.17:42:35.93#ibcon#about to read 5, iclass 4, count 0 2006.201.17:42:35.93#ibcon#read 5, iclass 4, count 0 2006.201.17:42:35.93#ibcon#about to read 6, iclass 4, count 0 2006.201.17:42:35.93#ibcon#read 6, iclass 4, count 0 2006.201.17:42:35.93#ibcon#end of sib2, iclass 4, count 0 2006.201.17:42:35.93#ibcon#*after write, iclass 4, count 0 2006.201.17:42:35.93#ibcon#*before return 0, iclass 4, count 0 2006.201.17:42:35.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:35.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.17:42:35.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.17:42:35.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.17:42:35.93$vck44/vblo=5,709.99 2006.201.17:42:35.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.17:42:35.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.17:42:35.93#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:35.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:35.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:35.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:35.93#ibcon#enter wrdev, iclass 6, count 0 2006.201.17:42:35.93#ibcon#first serial, iclass 6, count 0 2006.201.17:42:35.93#ibcon#enter sib2, iclass 6, count 0 2006.201.17:42:35.93#ibcon#flushed, iclass 6, count 0 2006.201.17:42:35.93#ibcon#about to write, iclass 6, count 0 2006.201.17:42:35.93#ibcon#wrote, iclass 6, count 0 2006.201.17:42:35.93#ibcon#about to read 3, iclass 6, count 0 2006.201.17:42:35.95#ibcon#read 3, iclass 6, count 0 2006.201.17:42:35.95#ibcon#about to read 4, iclass 6, count 0 2006.201.17:42:35.95#ibcon#read 4, iclass 6, count 0 2006.201.17:42:35.95#ibcon#about to read 5, iclass 6, count 0 2006.201.17:42:35.95#ibcon#read 5, iclass 6, count 0 2006.201.17:42:35.95#ibcon#about to read 6, iclass 6, count 0 2006.201.17:42:35.95#ibcon#read 6, iclass 6, count 0 2006.201.17:42:35.95#ibcon#end of sib2, iclass 6, count 0 2006.201.17:42:35.95#ibcon#*mode == 0, iclass 6, count 0 2006.201.17:42:35.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.17:42:35.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.17:42:35.95#ibcon#*before write, iclass 6, count 0 2006.201.17:42:35.95#ibcon#enter sib2, iclass 6, count 0 2006.201.17:42:35.95#ibcon#flushed, iclass 6, count 0 2006.201.17:42:35.95#ibcon#about to write, iclass 6, count 0 2006.201.17:42:35.95#ibcon#wrote, iclass 6, count 0 2006.201.17:42:35.95#ibcon#about to read 3, iclass 6, count 0 2006.201.17:42:35.99#ibcon#read 3, iclass 6, count 0 2006.201.17:42:35.99#ibcon#about to read 4, iclass 6, count 0 2006.201.17:42:35.99#ibcon#read 4, iclass 6, count 0 2006.201.17:42:35.99#ibcon#about to read 5, iclass 6, count 0 2006.201.17:42:35.99#ibcon#read 5, iclass 6, count 0 2006.201.17:42:35.99#ibcon#about to read 6, iclass 6, count 0 2006.201.17:42:35.99#ibcon#read 6, iclass 6, count 0 2006.201.17:42:35.99#ibcon#end of sib2, iclass 6, count 0 2006.201.17:42:35.99#ibcon#*after write, iclass 6, count 0 2006.201.17:42:35.99#ibcon#*before return 0, iclass 6, count 0 2006.201.17:42:35.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:35.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.17:42:35.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.17:42:35.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.17:42:35.99$vck44/vb=5,4 2006.201.17:42:35.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.17:42:35.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.17:42:35.99#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:35.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:36.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:36.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:36.05#ibcon#enter wrdev, iclass 10, count 2 2006.201.17:42:36.05#ibcon#first serial, iclass 10, count 2 2006.201.17:42:36.05#ibcon#enter sib2, iclass 10, count 2 2006.201.17:42:36.05#ibcon#flushed, iclass 10, count 2 2006.201.17:42:36.05#ibcon#about to write, iclass 10, count 2 2006.201.17:42:36.05#ibcon#wrote, iclass 10, count 2 2006.201.17:42:36.05#ibcon#about to read 3, iclass 10, count 2 2006.201.17:42:36.07#ibcon#read 3, iclass 10, count 2 2006.201.17:42:36.07#ibcon#about to read 4, iclass 10, count 2 2006.201.17:42:36.07#ibcon#read 4, iclass 10, count 2 2006.201.17:42:36.07#ibcon#about to read 5, iclass 10, count 2 2006.201.17:42:36.07#ibcon#read 5, iclass 10, count 2 2006.201.17:42:36.07#ibcon#about to read 6, iclass 10, count 2 2006.201.17:42:36.07#ibcon#read 6, iclass 10, count 2 2006.201.17:42:36.07#ibcon#end of sib2, iclass 10, count 2 2006.201.17:42:36.07#ibcon#*mode == 0, iclass 10, count 2 2006.201.17:42:36.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.17:42:36.07#ibcon#[27=AT05-04\r\n] 2006.201.17:42:36.07#ibcon#*before write, iclass 10, count 2 2006.201.17:42:36.07#ibcon#enter sib2, iclass 10, count 2 2006.201.17:42:36.07#ibcon#flushed, iclass 10, count 2 2006.201.17:42:36.07#ibcon#about to write, iclass 10, count 2 2006.201.17:42:36.07#ibcon#wrote, iclass 10, count 2 2006.201.17:42:36.07#ibcon#about to read 3, iclass 10, count 2 2006.201.17:42:36.10#ibcon#read 3, iclass 10, count 2 2006.201.17:42:36.10#ibcon#about to read 4, iclass 10, count 2 2006.201.17:42:36.10#ibcon#read 4, iclass 10, count 2 2006.201.17:42:36.10#ibcon#about to read 5, iclass 10, count 2 2006.201.17:42:36.10#ibcon#read 5, iclass 10, count 2 2006.201.17:42:36.10#ibcon#about to read 6, iclass 10, count 2 2006.201.17:42:36.10#ibcon#read 6, iclass 10, count 2 2006.201.17:42:36.10#ibcon#end of sib2, iclass 10, count 2 2006.201.17:42:36.10#ibcon#*after write, iclass 10, count 2 2006.201.17:42:36.10#ibcon#*before return 0, iclass 10, count 2 2006.201.17:42:36.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:36.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.17:42:36.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.17:42:36.10#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:36.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:36.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:36.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:36.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.17:42:36.22#ibcon#first serial, iclass 10, count 0 2006.201.17:42:36.22#ibcon#enter sib2, iclass 10, count 0 2006.201.17:42:36.22#ibcon#flushed, iclass 10, count 0 2006.201.17:42:36.22#ibcon#about to write, iclass 10, count 0 2006.201.17:42:36.22#ibcon#wrote, iclass 10, count 0 2006.201.17:42:36.22#ibcon#about to read 3, iclass 10, count 0 2006.201.17:42:36.24#ibcon#read 3, iclass 10, count 0 2006.201.17:42:36.24#ibcon#about to read 4, iclass 10, count 0 2006.201.17:42:36.24#ibcon#read 4, iclass 10, count 0 2006.201.17:42:36.24#ibcon#about to read 5, iclass 10, count 0 2006.201.17:42:36.24#ibcon#read 5, iclass 10, count 0 2006.201.17:42:36.24#ibcon#about to read 6, iclass 10, count 0 2006.201.17:42:36.24#ibcon#read 6, iclass 10, count 0 2006.201.17:42:36.24#ibcon#end of sib2, iclass 10, count 0 2006.201.17:42:36.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.17:42:36.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.17:42:36.24#ibcon#[27=USB\r\n] 2006.201.17:42:36.24#ibcon#*before write, iclass 10, count 0 2006.201.17:42:36.24#ibcon#enter sib2, iclass 10, count 0 2006.201.17:42:36.24#ibcon#flushed, iclass 10, count 0 2006.201.17:42:36.24#ibcon#about to write, iclass 10, count 0 2006.201.17:42:36.24#ibcon#wrote, iclass 10, count 0 2006.201.17:42:36.24#ibcon#about to read 3, iclass 10, count 0 2006.201.17:42:36.27#ibcon#read 3, iclass 10, count 0 2006.201.17:42:36.27#ibcon#about to read 4, iclass 10, count 0 2006.201.17:42:36.27#ibcon#read 4, iclass 10, count 0 2006.201.17:42:36.27#ibcon#about to read 5, iclass 10, count 0 2006.201.17:42:36.27#ibcon#read 5, iclass 10, count 0 2006.201.17:42:36.27#ibcon#about to read 6, iclass 10, count 0 2006.201.17:42:36.27#ibcon#read 6, iclass 10, count 0 2006.201.17:42:36.27#ibcon#end of sib2, iclass 10, count 0 2006.201.17:42:36.27#ibcon#*after write, iclass 10, count 0 2006.201.17:42:36.27#ibcon#*before return 0, iclass 10, count 0 2006.201.17:42:36.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:36.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.17:42:36.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.17:42:36.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.17:42:36.27$vck44/vblo=6,719.99 2006.201.17:42:36.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.17:42:36.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.17:42:36.27#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:36.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:36.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:36.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:36.27#ibcon#enter wrdev, iclass 12, count 0 2006.201.17:42:36.27#ibcon#first serial, iclass 12, count 0 2006.201.17:42:36.27#ibcon#enter sib2, iclass 12, count 0 2006.201.17:42:36.27#ibcon#flushed, iclass 12, count 0 2006.201.17:42:36.27#ibcon#about to write, iclass 12, count 0 2006.201.17:42:36.27#ibcon#wrote, iclass 12, count 0 2006.201.17:42:36.27#ibcon#about to read 3, iclass 12, count 0 2006.201.17:42:36.29#ibcon#read 3, iclass 12, count 0 2006.201.17:42:36.29#ibcon#about to read 4, iclass 12, count 0 2006.201.17:42:36.29#ibcon#read 4, iclass 12, count 0 2006.201.17:42:36.29#ibcon#about to read 5, iclass 12, count 0 2006.201.17:42:36.29#ibcon#read 5, iclass 12, count 0 2006.201.17:42:36.29#ibcon#about to read 6, iclass 12, count 0 2006.201.17:42:36.29#ibcon#read 6, iclass 12, count 0 2006.201.17:42:36.29#ibcon#end of sib2, iclass 12, count 0 2006.201.17:42:36.29#ibcon#*mode == 0, iclass 12, count 0 2006.201.17:42:36.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.17:42:36.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.17:42:36.29#ibcon#*before write, iclass 12, count 0 2006.201.17:42:36.29#ibcon#enter sib2, iclass 12, count 0 2006.201.17:42:36.29#ibcon#flushed, iclass 12, count 0 2006.201.17:42:36.29#ibcon#about to write, iclass 12, count 0 2006.201.17:42:36.29#ibcon#wrote, iclass 12, count 0 2006.201.17:42:36.29#ibcon#about to read 3, iclass 12, count 0 2006.201.17:42:36.33#ibcon#read 3, iclass 12, count 0 2006.201.17:42:36.33#ibcon#about to read 4, iclass 12, count 0 2006.201.17:42:36.33#ibcon#read 4, iclass 12, count 0 2006.201.17:42:36.33#ibcon#about to read 5, iclass 12, count 0 2006.201.17:42:36.33#ibcon#read 5, iclass 12, count 0 2006.201.17:42:36.33#ibcon#about to read 6, iclass 12, count 0 2006.201.17:42:36.33#ibcon#read 6, iclass 12, count 0 2006.201.17:42:36.33#ibcon#end of sib2, iclass 12, count 0 2006.201.17:42:36.33#ibcon#*after write, iclass 12, count 0 2006.201.17:42:36.33#ibcon#*before return 0, iclass 12, count 0 2006.201.17:42:36.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:36.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.17:42:36.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.17:42:36.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.17:42:36.33$vck44/vb=6,4 2006.201.17:42:36.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.17:42:36.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.17:42:36.33#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:36.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:36.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:36.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:36.39#ibcon#enter wrdev, iclass 14, count 2 2006.201.17:42:36.39#ibcon#first serial, iclass 14, count 2 2006.201.17:42:36.39#ibcon#enter sib2, iclass 14, count 2 2006.201.17:42:36.39#ibcon#flushed, iclass 14, count 2 2006.201.17:42:36.39#ibcon#about to write, iclass 14, count 2 2006.201.17:42:36.39#ibcon#wrote, iclass 14, count 2 2006.201.17:42:36.39#ibcon#about to read 3, iclass 14, count 2 2006.201.17:42:36.41#ibcon#read 3, iclass 14, count 2 2006.201.17:42:36.41#ibcon#about to read 4, iclass 14, count 2 2006.201.17:42:36.41#ibcon#read 4, iclass 14, count 2 2006.201.17:42:36.41#ibcon#about to read 5, iclass 14, count 2 2006.201.17:42:36.41#ibcon#read 5, iclass 14, count 2 2006.201.17:42:36.41#ibcon#about to read 6, iclass 14, count 2 2006.201.17:42:36.41#ibcon#read 6, iclass 14, count 2 2006.201.17:42:36.41#ibcon#end of sib2, iclass 14, count 2 2006.201.17:42:36.41#ibcon#*mode == 0, iclass 14, count 2 2006.201.17:42:36.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.17:42:36.41#ibcon#[27=AT06-04\r\n] 2006.201.17:42:36.41#ibcon#*before write, iclass 14, count 2 2006.201.17:42:36.41#ibcon#enter sib2, iclass 14, count 2 2006.201.17:42:36.41#ibcon#flushed, iclass 14, count 2 2006.201.17:42:36.41#ibcon#about to write, iclass 14, count 2 2006.201.17:42:36.41#ibcon#wrote, iclass 14, count 2 2006.201.17:42:36.41#ibcon#about to read 3, iclass 14, count 2 2006.201.17:42:36.44#ibcon#read 3, iclass 14, count 2 2006.201.17:42:36.44#ibcon#about to read 4, iclass 14, count 2 2006.201.17:42:36.44#ibcon#read 4, iclass 14, count 2 2006.201.17:42:36.44#ibcon#about to read 5, iclass 14, count 2 2006.201.17:42:36.44#ibcon#read 5, iclass 14, count 2 2006.201.17:42:36.44#ibcon#about to read 6, iclass 14, count 2 2006.201.17:42:36.44#ibcon#read 6, iclass 14, count 2 2006.201.17:42:36.44#ibcon#end of sib2, iclass 14, count 2 2006.201.17:42:36.44#ibcon#*after write, iclass 14, count 2 2006.201.17:42:36.44#ibcon#*before return 0, iclass 14, count 2 2006.201.17:42:36.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:36.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.17:42:36.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.17:42:36.44#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:36.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:36.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:36.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:36.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.17:42:36.56#ibcon#first serial, iclass 14, count 0 2006.201.17:42:36.56#ibcon#enter sib2, iclass 14, count 0 2006.201.17:42:36.56#ibcon#flushed, iclass 14, count 0 2006.201.17:42:36.56#ibcon#about to write, iclass 14, count 0 2006.201.17:42:36.56#ibcon#wrote, iclass 14, count 0 2006.201.17:42:36.56#ibcon#about to read 3, iclass 14, count 0 2006.201.17:42:36.58#ibcon#read 3, iclass 14, count 0 2006.201.17:42:36.58#ibcon#about to read 4, iclass 14, count 0 2006.201.17:42:36.58#ibcon#read 4, iclass 14, count 0 2006.201.17:42:36.58#ibcon#about to read 5, iclass 14, count 0 2006.201.17:42:36.58#ibcon#read 5, iclass 14, count 0 2006.201.17:42:36.58#ibcon#about to read 6, iclass 14, count 0 2006.201.17:42:36.58#ibcon#read 6, iclass 14, count 0 2006.201.17:42:36.58#ibcon#end of sib2, iclass 14, count 0 2006.201.17:42:36.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.17:42:36.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.17:42:36.58#ibcon#[27=USB\r\n] 2006.201.17:42:36.58#ibcon#*before write, iclass 14, count 0 2006.201.17:42:36.58#ibcon#enter sib2, iclass 14, count 0 2006.201.17:42:36.58#ibcon#flushed, iclass 14, count 0 2006.201.17:42:36.58#ibcon#about to write, iclass 14, count 0 2006.201.17:42:36.58#ibcon#wrote, iclass 14, count 0 2006.201.17:42:36.58#ibcon#about to read 3, iclass 14, count 0 2006.201.17:42:36.61#ibcon#read 3, iclass 14, count 0 2006.201.17:42:36.61#ibcon#about to read 4, iclass 14, count 0 2006.201.17:42:36.61#ibcon#read 4, iclass 14, count 0 2006.201.17:42:36.61#ibcon#about to read 5, iclass 14, count 0 2006.201.17:42:36.61#ibcon#read 5, iclass 14, count 0 2006.201.17:42:36.61#ibcon#about to read 6, iclass 14, count 0 2006.201.17:42:36.61#ibcon#read 6, iclass 14, count 0 2006.201.17:42:36.61#ibcon#end of sib2, iclass 14, count 0 2006.201.17:42:36.61#ibcon#*after write, iclass 14, count 0 2006.201.17:42:36.61#ibcon#*before return 0, iclass 14, count 0 2006.201.17:42:36.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:36.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.17:42:36.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.17:42:36.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.17:42:36.61$vck44/vblo=7,734.99 2006.201.17:42:36.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.17:42:36.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.17:42:36.61#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:36.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:36.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:36.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:36.61#ibcon#enter wrdev, iclass 16, count 0 2006.201.17:42:36.61#ibcon#first serial, iclass 16, count 0 2006.201.17:42:36.61#ibcon#enter sib2, iclass 16, count 0 2006.201.17:42:36.61#ibcon#flushed, iclass 16, count 0 2006.201.17:42:36.61#ibcon#about to write, iclass 16, count 0 2006.201.17:42:36.61#ibcon#wrote, iclass 16, count 0 2006.201.17:42:36.61#ibcon#about to read 3, iclass 16, count 0 2006.201.17:42:36.63#ibcon#read 3, iclass 16, count 0 2006.201.17:42:36.63#ibcon#about to read 4, iclass 16, count 0 2006.201.17:42:36.63#ibcon#read 4, iclass 16, count 0 2006.201.17:42:36.63#ibcon#about to read 5, iclass 16, count 0 2006.201.17:42:36.63#ibcon#read 5, iclass 16, count 0 2006.201.17:42:36.63#ibcon#about to read 6, iclass 16, count 0 2006.201.17:42:36.63#ibcon#read 6, iclass 16, count 0 2006.201.17:42:36.63#ibcon#end of sib2, iclass 16, count 0 2006.201.17:42:36.63#ibcon#*mode == 0, iclass 16, count 0 2006.201.17:42:36.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.17:42:36.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.17:42:36.63#ibcon#*before write, iclass 16, count 0 2006.201.17:42:36.63#ibcon#enter sib2, iclass 16, count 0 2006.201.17:42:36.63#ibcon#flushed, iclass 16, count 0 2006.201.17:42:36.63#ibcon#about to write, iclass 16, count 0 2006.201.17:42:36.63#ibcon#wrote, iclass 16, count 0 2006.201.17:42:36.63#ibcon#about to read 3, iclass 16, count 0 2006.201.17:42:36.67#ibcon#read 3, iclass 16, count 0 2006.201.17:42:36.67#ibcon#about to read 4, iclass 16, count 0 2006.201.17:42:36.67#ibcon#read 4, iclass 16, count 0 2006.201.17:42:36.67#ibcon#about to read 5, iclass 16, count 0 2006.201.17:42:36.67#ibcon#read 5, iclass 16, count 0 2006.201.17:42:36.67#ibcon#about to read 6, iclass 16, count 0 2006.201.17:42:36.67#ibcon#read 6, iclass 16, count 0 2006.201.17:42:36.67#ibcon#end of sib2, iclass 16, count 0 2006.201.17:42:36.67#ibcon#*after write, iclass 16, count 0 2006.201.17:42:36.67#ibcon#*before return 0, iclass 16, count 0 2006.201.17:42:36.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:36.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.17:42:36.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.17:42:36.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.17:42:36.67$vck44/vb=7,4 2006.201.17:42:36.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.17:42:36.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.17:42:36.67#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:36.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:36.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:36.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:36.73#ibcon#enter wrdev, iclass 18, count 2 2006.201.17:42:36.73#ibcon#first serial, iclass 18, count 2 2006.201.17:42:36.73#ibcon#enter sib2, iclass 18, count 2 2006.201.17:42:36.73#ibcon#flushed, iclass 18, count 2 2006.201.17:42:36.73#ibcon#about to write, iclass 18, count 2 2006.201.17:42:36.73#ibcon#wrote, iclass 18, count 2 2006.201.17:42:36.73#ibcon#about to read 3, iclass 18, count 2 2006.201.17:42:36.75#ibcon#read 3, iclass 18, count 2 2006.201.17:42:36.75#ibcon#about to read 4, iclass 18, count 2 2006.201.17:42:36.75#ibcon#read 4, iclass 18, count 2 2006.201.17:42:36.75#ibcon#about to read 5, iclass 18, count 2 2006.201.17:42:36.75#ibcon#read 5, iclass 18, count 2 2006.201.17:42:36.75#ibcon#about to read 6, iclass 18, count 2 2006.201.17:42:36.75#ibcon#read 6, iclass 18, count 2 2006.201.17:42:36.75#ibcon#end of sib2, iclass 18, count 2 2006.201.17:42:36.75#ibcon#*mode == 0, iclass 18, count 2 2006.201.17:42:36.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.17:42:36.75#ibcon#[27=AT07-04\r\n] 2006.201.17:42:36.75#ibcon#*before write, iclass 18, count 2 2006.201.17:42:36.75#ibcon#enter sib2, iclass 18, count 2 2006.201.17:42:36.75#ibcon#flushed, iclass 18, count 2 2006.201.17:42:36.75#ibcon#about to write, iclass 18, count 2 2006.201.17:42:36.75#ibcon#wrote, iclass 18, count 2 2006.201.17:42:36.75#ibcon#about to read 3, iclass 18, count 2 2006.201.17:42:36.78#ibcon#read 3, iclass 18, count 2 2006.201.17:42:36.78#ibcon#about to read 4, iclass 18, count 2 2006.201.17:42:36.78#ibcon#read 4, iclass 18, count 2 2006.201.17:42:36.78#ibcon#about to read 5, iclass 18, count 2 2006.201.17:42:36.78#ibcon#read 5, iclass 18, count 2 2006.201.17:42:36.78#ibcon#about to read 6, iclass 18, count 2 2006.201.17:42:36.78#ibcon#read 6, iclass 18, count 2 2006.201.17:42:36.78#ibcon#end of sib2, iclass 18, count 2 2006.201.17:42:36.78#ibcon#*after write, iclass 18, count 2 2006.201.17:42:36.78#ibcon#*before return 0, iclass 18, count 2 2006.201.17:42:36.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:36.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.17:42:36.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.17:42:36.78#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:36.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:36.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:36.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:36.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.17:42:36.90#ibcon#first serial, iclass 18, count 0 2006.201.17:42:36.90#ibcon#enter sib2, iclass 18, count 0 2006.201.17:42:36.90#ibcon#flushed, iclass 18, count 0 2006.201.17:42:36.90#ibcon#about to write, iclass 18, count 0 2006.201.17:42:36.90#ibcon#wrote, iclass 18, count 0 2006.201.17:42:36.90#ibcon#about to read 3, iclass 18, count 0 2006.201.17:42:36.92#ibcon#read 3, iclass 18, count 0 2006.201.17:42:36.92#ibcon#about to read 4, iclass 18, count 0 2006.201.17:42:36.92#ibcon#read 4, iclass 18, count 0 2006.201.17:42:36.92#ibcon#about to read 5, iclass 18, count 0 2006.201.17:42:36.92#ibcon#read 5, iclass 18, count 0 2006.201.17:42:36.92#ibcon#about to read 6, iclass 18, count 0 2006.201.17:42:36.92#ibcon#read 6, iclass 18, count 0 2006.201.17:42:36.92#ibcon#end of sib2, iclass 18, count 0 2006.201.17:42:36.92#ibcon#*mode == 0, iclass 18, count 0 2006.201.17:42:36.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.17:42:36.92#ibcon#[27=USB\r\n] 2006.201.17:42:36.92#ibcon#*before write, iclass 18, count 0 2006.201.17:42:36.92#ibcon#enter sib2, iclass 18, count 0 2006.201.17:42:36.92#ibcon#flushed, iclass 18, count 0 2006.201.17:42:36.92#ibcon#about to write, iclass 18, count 0 2006.201.17:42:36.92#ibcon#wrote, iclass 18, count 0 2006.201.17:42:36.92#ibcon#about to read 3, iclass 18, count 0 2006.201.17:42:36.95#ibcon#read 3, iclass 18, count 0 2006.201.17:42:36.95#ibcon#about to read 4, iclass 18, count 0 2006.201.17:42:36.95#ibcon#read 4, iclass 18, count 0 2006.201.17:42:36.95#ibcon#about to read 5, iclass 18, count 0 2006.201.17:42:36.95#ibcon#read 5, iclass 18, count 0 2006.201.17:42:36.95#ibcon#about to read 6, iclass 18, count 0 2006.201.17:42:36.95#ibcon#read 6, iclass 18, count 0 2006.201.17:42:36.95#ibcon#end of sib2, iclass 18, count 0 2006.201.17:42:36.95#ibcon#*after write, iclass 18, count 0 2006.201.17:42:36.95#ibcon#*before return 0, iclass 18, count 0 2006.201.17:42:36.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:36.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.17:42:36.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.17:42:36.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.17:42:36.95$vck44/vblo=8,744.99 2006.201.17:42:36.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.17:42:36.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.17:42:36.95#ibcon#ireg 17 cls_cnt 0 2006.201.17:42:36.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:36.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:36.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:36.95#ibcon#enter wrdev, iclass 20, count 0 2006.201.17:42:36.95#ibcon#first serial, iclass 20, count 0 2006.201.17:42:36.95#ibcon#enter sib2, iclass 20, count 0 2006.201.17:42:36.95#ibcon#flushed, iclass 20, count 0 2006.201.17:42:36.95#ibcon#about to write, iclass 20, count 0 2006.201.17:42:36.95#ibcon#wrote, iclass 20, count 0 2006.201.17:42:36.95#ibcon#about to read 3, iclass 20, count 0 2006.201.17:42:36.97#ibcon#read 3, iclass 20, count 0 2006.201.17:42:36.97#ibcon#about to read 4, iclass 20, count 0 2006.201.17:42:36.97#ibcon#read 4, iclass 20, count 0 2006.201.17:42:36.97#ibcon#about to read 5, iclass 20, count 0 2006.201.17:42:36.97#ibcon#read 5, iclass 20, count 0 2006.201.17:42:36.97#ibcon#about to read 6, iclass 20, count 0 2006.201.17:42:36.97#ibcon#read 6, iclass 20, count 0 2006.201.17:42:36.97#ibcon#end of sib2, iclass 20, count 0 2006.201.17:42:36.97#ibcon#*mode == 0, iclass 20, count 0 2006.201.17:42:36.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.17:42:36.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.17:42:36.97#ibcon#*before write, iclass 20, count 0 2006.201.17:42:36.97#ibcon#enter sib2, iclass 20, count 0 2006.201.17:42:36.97#ibcon#flushed, iclass 20, count 0 2006.201.17:42:36.97#ibcon#about to write, iclass 20, count 0 2006.201.17:42:36.97#ibcon#wrote, iclass 20, count 0 2006.201.17:42:36.97#ibcon#about to read 3, iclass 20, count 0 2006.201.17:42:37.01#ibcon#read 3, iclass 20, count 0 2006.201.17:42:37.01#ibcon#about to read 4, iclass 20, count 0 2006.201.17:42:37.01#ibcon#read 4, iclass 20, count 0 2006.201.17:42:37.01#ibcon#about to read 5, iclass 20, count 0 2006.201.17:42:37.01#ibcon#read 5, iclass 20, count 0 2006.201.17:42:37.01#ibcon#about to read 6, iclass 20, count 0 2006.201.17:42:37.01#ibcon#read 6, iclass 20, count 0 2006.201.17:42:37.01#ibcon#end of sib2, iclass 20, count 0 2006.201.17:42:37.01#ibcon#*after write, iclass 20, count 0 2006.201.17:42:37.01#ibcon#*before return 0, iclass 20, count 0 2006.201.17:42:37.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:37.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.17:42:37.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.17:42:37.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.17:42:37.01$vck44/vb=8,4 2006.201.17:42:37.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.17:42:37.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.17:42:37.01#ibcon#ireg 11 cls_cnt 2 2006.201.17:42:37.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:37.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:37.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:37.07#ibcon#enter wrdev, iclass 22, count 2 2006.201.17:42:37.07#ibcon#first serial, iclass 22, count 2 2006.201.17:42:37.07#ibcon#enter sib2, iclass 22, count 2 2006.201.17:42:37.07#ibcon#flushed, iclass 22, count 2 2006.201.17:42:37.07#ibcon#about to write, iclass 22, count 2 2006.201.17:42:37.07#ibcon#wrote, iclass 22, count 2 2006.201.17:42:37.07#ibcon#about to read 3, iclass 22, count 2 2006.201.17:42:37.09#ibcon#read 3, iclass 22, count 2 2006.201.17:42:37.09#ibcon#about to read 4, iclass 22, count 2 2006.201.17:42:37.09#ibcon#read 4, iclass 22, count 2 2006.201.17:42:37.09#ibcon#about to read 5, iclass 22, count 2 2006.201.17:42:37.09#ibcon#read 5, iclass 22, count 2 2006.201.17:42:37.09#ibcon#about to read 6, iclass 22, count 2 2006.201.17:42:37.09#ibcon#read 6, iclass 22, count 2 2006.201.17:42:37.09#ibcon#end of sib2, iclass 22, count 2 2006.201.17:42:37.09#ibcon#*mode == 0, iclass 22, count 2 2006.201.17:42:37.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.17:42:37.09#ibcon#[27=AT08-04\r\n] 2006.201.17:42:37.09#ibcon#*before write, iclass 22, count 2 2006.201.17:42:37.09#ibcon#enter sib2, iclass 22, count 2 2006.201.17:42:37.09#ibcon#flushed, iclass 22, count 2 2006.201.17:42:37.09#ibcon#about to write, iclass 22, count 2 2006.201.17:42:37.09#ibcon#wrote, iclass 22, count 2 2006.201.17:42:37.09#ibcon#about to read 3, iclass 22, count 2 2006.201.17:42:37.12#ibcon#read 3, iclass 22, count 2 2006.201.17:42:37.12#ibcon#about to read 4, iclass 22, count 2 2006.201.17:42:37.12#ibcon#read 4, iclass 22, count 2 2006.201.17:42:37.12#ibcon#about to read 5, iclass 22, count 2 2006.201.17:42:37.12#ibcon#read 5, iclass 22, count 2 2006.201.17:42:37.12#ibcon#about to read 6, iclass 22, count 2 2006.201.17:42:37.12#ibcon#read 6, iclass 22, count 2 2006.201.17:42:37.12#ibcon#end of sib2, iclass 22, count 2 2006.201.17:42:37.12#ibcon#*after write, iclass 22, count 2 2006.201.17:42:37.12#ibcon#*before return 0, iclass 22, count 2 2006.201.17:42:37.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:37.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.17:42:37.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.17:42:37.12#ibcon#ireg 7 cls_cnt 0 2006.201.17:42:37.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:37.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:37.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:37.24#ibcon#enter wrdev, iclass 22, count 0 2006.201.17:42:37.24#ibcon#first serial, iclass 22, count 0 2006.201.17:42:37.24#ibcon#enter sib2, iclass 22, count 0 2006.201.17:42:37.24#ibcon#flushed, iclass 22, count 0 2006.201.17:42:37.24#ibcon#about to write, iclass 22, count 0 2006.201.17:42:37.24#ibcon#wrote, iclass 22, count 0 2006.201.17:42:37.24#ibcon#about to read 3, iclass 22, count 0 2006.201.17:42:37.26#ibcon#read 3, iclass 22, count 0 2006.201.17:42:37.26#ibcon#about to read 4, iclass 22, count 0 2006.201.17:42:37.26#ibcon#read 4, iclass 22, count 0 2006.201.17:42:37.26#ibcon#about to read 5, iclass 22, count 0 2006.201.17:42:37.26#ibcon#read 5, iclass 22, count 0 2006.201.17:42:37.26#ibcon#about to read 6, iclass 22, count 0 2006.201.17:42:37.26#ibcon#read 6, iclass 22, count 0 2006.201.17:42:37.26#ibcon#end of sib2, iclass 22, count 0 2006.201.17:42:37.26#ibcon#*mode == 0, iclass 22, count 0 2006.201.17:42:37.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.17:42:37.26#ibcon#[27=USB\r\n] 2006.201.17:42:37.26#ibcon#*before write, iclass 22, count 0 2006.201.17:42:37.26#ibcon#enter sib2, iclass 22, count 0 2006.201.17:42:37.26#ibcon#flushed, iclass 22, count 0 2006.201.17:42:37.26#ibcon#about to write, iclass 22, count 0 2006.201.17:42:37.26#ibcon#wrote, iclass 22, count 0 2006.201.17:42:37.26#ibcon#about to read 3, iclass 22, count 0 2006.201.17:42:37.29#ibcon#read 3, iclass 22, count 0 2006.201.17:42:37.29#ibcon#about to read 4, iclass 22, count 0 2006.201.17:42:37.29#ibcon#read 4, iclass 22, count 0 2006.201.17:42:37.29#ibcon#about to read 5, iclass 22, count 0 2006.201.17:42:37.29#ibcon#read 5, iclass 22, count 0 2006.201.17:42:37.29#ibcon#about to read 6, iclass 22, count 0 2006.201.17:42:37.29#ibcon#read 6, iclass 22, count 0 2006.201.17:42:37.29#ibcon#end of sib2, iclass 22, count 0 2006.201.17:42:37.29#ibcon#*after write, iclass 22, count 0 2006.201.17:42:37.29#ibcon#*before return 0, iclass 22, count 0 2006.201.17:42:37.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:37.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.17:42:37.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.17:42:37.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.17:42:37.29$vck44/vabw=wide 2006.201.17:42:37.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.17:42:37.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.17:42:37.29#ibcon#ireg 8 cls_cnt 0 2006.201.17:42:37.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:37.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:37.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:37.29#ibcon#enter wrdev, iclass 24, count 0 2006.201.17:42:37.29#ibcon#first serial, iclass 24, count 0 2006.201.17:42:37.29#ibcon#enter sib2, iclass 24, count 0 2006.201.17:42:37.29#ibcon#flushed, iclass 24, count 0 2006.201.17:42:37.29#ibcon#about to write, iclass 24, count 0 2006.201.17:42:37.29#ibcon#wrote, iclass 24, count 0 2006.201.17:42:37.29#ibcon#about to read 3, iclass 24, count 0 2006.201.17:42:37.31#ibcon#read 3, iclass 24, count 0 2006.201.17:42:37.31#ibcon#about to read 4, iclass 24, count 0 2006.201.17:42:37.31#ibcon#read 4, iclass 24, count 0 2006.201.17:42:37.31#ibcon#about to read 5, iclass 24, count 0 2006.201.17:42:37.31#ibcon#read 5, iclass 24, count 0 2006.201.17:42:37.31#ibcon#about to read 6, iclass 24, count 0 2006.201.17:42:37.31#ibcon#read 6, iclass 24, count 0 2006.201.17:42:37.31#ibcon#end of sib2, iclass 24, count 0 2006.201.17:42:37.31#ibcon#*mode == 0, iclass 24, count 0 2006.201.17:42:37.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.17:42:37.31#ibcon#[25=BW32\r\n] 2006.201.17:42:37.31#ibcon#*before write, iclass 24, count 0 2006.201.17:42:37.31#ibcon#enter sib2, iclass 24, count 0 2006.201.17:42:37.31#ibcon#flushed, iclass 24, count 0 2006.201.17:42:37.31#ibcon#about to write, iclass 24, count 0 2006.201.17:42:37.31#ibcon#wrote, iclass 24, count 0 2006.201.17:42:37.31#ibcon#about to read 3, iclass 24, count 0 2006.201.17:42:37.35#ibcon#read 3, iclass 24, count 0 2006.201.17:42:37.35#ibcon#about to read 4, iclass 24, count 0 2006.201.17:42:37.35#ibcon#read 4, iclass 24, count 0 2006.201.17:42:37.35#ibcon#about to read 5, iclass 24, count 0 2006.201.17:42:37.35#ibcon#read 5, iclass 24, count 0 2006.201.17:42:37.35#ibcon#about to read 6, iclass 24, count 0 2006.201.17:42:37.35#ibcon#read 6, iclass 24, count 0 2006.201.17:42:37.35#ibcon#end of sib2, iclass 24, count 0 2006.201.17:42:37.35#ibcon#*after write, iclass 24, count 0 2006.201.17:42:37.35#ibcon#*before return 0, iclass 24, count 0 2006.201.17:42:37.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:37.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.17:42:37.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.17:42:37.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.17:42:37.35$vck44/vbbw=wide 2006.201.17:42:37.35#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.17:42:37.35#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.17:42:37.35#ibcon#ireg 8 cls_cnt 0 2006.201.17:42:37.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:42:37.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:42:37.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:42:37.41#ibcon#enter wrdev, iclass 26, count 0 2006.201.17:42:37.41#ibcon#first serial, iclass 26, count 0 2006.201.17:42:37.41#ibcon#enter sib2, iclass 26, count 0 2006.201.17:42:37.41#ibcon#flushed, iclass 26, count 0 2006.201.17:42:37.41#ibcon#about to write, iclass 26, count 0 2006.201.17:42:37.41#ibcon#wrote, iclass 26, count 0 2006.201.17:42:37.41#ibcon#about to read 3, iclass 26, count 0 2006.201.17:42:37.43#ibcon#read 3, iclass 26, count 0 2006.201.17:42:37.43#ibcon#about to read 4, iclass 26, count 0 2006.201.17:42:37.43#ibcon#read 4, iclass 26, count 0 2006.201.17:42:37.43#ibcon#about to read 5, iclass 26, count 0 2006.201.17:42:37.43#ibcon#read 5, iclass 26, count 0 2006.201.17:42:37.43#ibcon#about to read 6, iclass 26, count 0 2006.201.17:42:37.43#ibcon#read 6, iclass 26, count 0 2006.201.17:42:37.43#ibcon#end of sib2, iclass 26, count 0 2006.201.17:42:37.43#ibcon#*mode == 0, iclass 26, count 0 2006.201.17:42:37.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.17:42:37.43#ibcon#[27=BW32\r\n] 2006.201.17:42:37.43#ibcon#*before write, iclass 26, count 0 2006.201.17:42:37.43#ibcon#enter sib2, iclass 26, count 0 2006.201.17:42:37.43#ibcon#flushed, iclass 26, count 0 2006.201.17:42:37.43#ibcon#about to write, iclass 26, count 0 2006.201.17:42:37.43#ibcon#wrote, iclass 26, count 0 2006.201.17:42:37.43#ibcon#about to read 3, iclass 26, count 0 2006.201.17:42:37.46#ibcon#read 3, iclass 26, count 0 2006.201.17:42:37.46#ibcon#about to read 4, iclass 26, count 0 2006.201.17:42:37.46#ibcon#read 4, iclass 26, count 0 2006.201.17:42:37.46#ibcon#about to read 5, iclass 26, count 0 2006.201.17:42:37.46#ibcon#read 5, iclass 26, count 0 2006.201.17:42:37.46#ibcon#about to read 6, iclass 26, count 0 2006.201.17:42:37.46#ibcon#read 6, iclass 26, count 0 2006.201.17:42:37.46#ibcon#end of sib2, iclass 26, count 0 2006.201.17:42:37.46#ibcon#*after write, iclass 26, count 0 2006.201.17:42:37.46#ibcon#*before return 0, iclass 26, count 0 2006.201.17:42:37.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:42:37.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:42:37.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.17:42:37.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.17:42:37.46$setupk4/ifdk4 2006.201.17:42:37.46$ifdk4/lo= 2006.201.17:42:37.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.17:42:37.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.17:42:37.46$ifdk4/patch= 2006.201.17:42:37.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.17:42:37.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.17:42:37.46$setupk4/!*+20s 2006.201.17:42:42.64#abcon#<5=/16 0.6 1.3 20.661001002.5\r\n> 2006.201.17:42:42.66#abcon#{5=INTERFACE CLEAR} 2006.201.17:42:42.72#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:42:51.91$setupk4/"tpicd 2006.201.17:42:51.91$setupk4/echo=off 2006.201.17:42:51.91$setupk4/xlog=off 2006.201.17:42:51.91:!2006.201.17:52:38 2006.201.17:43:10.14#trakl#Source acquired 2006.201.17:43:12.14#flagr#flagr/antenna,acquired 2006.201.17:52:38.00:preob 2006.201.17:52:38.14/onsource/TRACKING 2006.201.17:52:38.14:!2006.201.17:52:48 2006.201.17:52:48.00:"tape 2006.201.17:52:48.00:"st=record 2006.201.17:52:48.00:data_valid=on 2006.201.17:52:48.00:midob 2006.201.17:52:48.14/onsource/TRACKING 2006.201.17:52:48.14/wx/20.60,1002.3,100 2006.201.17:52:48.25/cable/+6.4764E-03 2006.201.17:52:49.34/va/01,08,usb,yes,47,50 2006.201.17:52:49.34/va/02,07,usb,yes,51,52 2006.201.17:52:49.34/va/03,08,usb,yes,46,48 2006.201.17:52:49.34/va/04,07,usb,yes,52,55 2006.201.17:52:49.34/va/05,04,usb,yes,46,47 2006.201.17:52:49.34/va/06,05,usb,yes,46,47 2006.201.17:52:49.34/va/07,05,usb,yes,46,47 2006.201.17:52:49.34/va/08,04,usb,yes,45,53 2006.201.17:52:49.57/valo/01,524.99,yes,locked 2006.201.17:52:49.57/valo/02,534.99,yes,locked 2006.201.17:52:49.57/valo/03,564.99,yes,locked 2006.201.17:52:49.57/valo/04,624.99,yes,locked 2006.201.17:52:49.57/valo/05,734.99,yes,locked 2006.201.17:52:49.57/valo/06,814.99,yes,locked 2006.201.17:52:49.57/valo/07,864.99,yes,locked 2006.201.17:52:49.57/valo/08,884.99,yes,locked 2006.201.17:52:50.66/vb/01,04,usb,yes,33,30 2006.201.17:52:50.66/vb/02,05,usb,yes,31,31 2006.201.17:52:50.66/vb/03,04,usb,yes,32,35 2006.201.17:52:50.66/vb/04,05,usb,yes,33,31 2006.201.17:52:50.66/vb/05,04,usb,yes,29,32 2006.201.17:52:50.66/vb/06,04,usb,yes,34,30 2006.201.17:52:50.66/vb/07,04,usb,yes,34,33 2006.201.17:52:50.66/vb/08,04,usb,yes,31,35 2006.201.17:52:50.90/vblo/01,629.99,yes,locked 2006.201.17:52:50.90/vblo/02,634.99,yes,locked 2006.201.17:52:50.90/vblo/03,649.99,yes,locked 2006.201.17:52:50.90/vblo/04,679.99,yes,locked 2006.201.17:52:50.90/vblo/05,709.99,yes,locked 2006.201.17:52:50.90/vblo/06,719.99,yes,locked 2006.201.17:52:50.90/vblo/07,734.99,yes,locked 2006.201.17:52:50.90/vblo/08,744.99,yes,locked 2006.201.17:52:51.05/vabw/8 2006.201.17:52:51.20/vbbw/8 2006.201.17:52:51.29/xfe/off,on,14.7 2006.201.17:52:51.67/ifatt/23,28,28,28 2006.201.17:52:52.06/fmout-gps/S +4.57E-07 2006.201.17:52:52.10:!2006.201.17:53:28 2006.201.17:53:28.00:data_valid=off 2006.201.17:53:28.00:"et 2006.201.17:53:28.00:!+3s 2006.201.17:53:31.02:"tape 2006.201.17:53:31.02:postob 2006.201.17:53:31.13/cable/+6.4787E-03 2006.201.17:53:31.13/wx/20.59,1002.4,100 2006.201.17:53:31.20/fmout-gps/S +4.58E-07 2006.201.17:53:31.20:scan_name=201-1754,jd0607,40 2006.201.17:53:31.20:source=1921-293,192451.06,-291430.1,2000.0,ccw 2006.201.17:53:33.13#flagr#flagr/antenna,new-source 2006.201.17:53:33.13:checkk5 2006.201.17:53:33.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.17:53:33.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.17:53:34.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.17:53:34.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.17:53:35.02/chk_obsdata//k5ts1/T2011752??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.17:53:35.39/chk_obsdata//k5ts2/T2011752??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.17:53:35.76/chk_obsdata//k5ts3/T2011752??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.17:53:36.13/chk_obsdata//k5ts4/T2011752??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.17:53:36.81/k5log//k5ts1_log_newline 2006.201.17:53:37.50/k5log//k5ts2_log_newline 2006.201.17:53:38.19/k5log//k5ts3_log_newline 2006.201.17:53:38.89/k5log//k5ts4_log_newline 2006.201.17:53:38.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.17:53:38.92:setupk4=1 2006.201.17:53:38.92$setupk4/echo=on 2006.201.17:53:38.92$setupk4/pcalon 2006.201.17:53:38.92$pcalon/"no phase cal control is implemented here 2006.201.17:53:38.92$setupk4/"tpicd=stop 2006.201.17:53:38.92$setupk4/"rec=synch_on 2006.201.17:53:38.92$setupk4/"rec_mode=128 2006.201.17:53:38.92$setupk4/!* 2006.201.17:53:38.92$setupk4/recpk4 2006.201.17:53:38.92$recpk4/recpatch= 2006.201.17:53:38.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.17:53:38.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.17:53:38.92$setupk4/vck44 2006.201.17:53:38.92$vck44/valo=1,524.99 2006.201.17:53:38.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.17:53:38.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.17:53:38.92#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:38.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:38.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:38.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:38.92#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:53:38.92#ibcon#first serial, iclass 39, count 0 2006.201.17:53:38.92#ibcon#enter sib2, iclass 39, count 0 2006.201.17:53:38.92#ibcon#flushed, iclass 39, count 0 2006.201.17:53:38.92#ibcon#about to write, iclass 39, count 0 2006.201.17:53:38.92#ibcon#wrote, iclass 39, count 0 2006.201.17:53:38.92#ibcon#about to read 3, iclass 39, count 0 2006.201.17:53:38.94#ibcon#read 3, iclass 39, count 0 2006.201.17:53:38.94#ibcon#about to read 4, iclass 39, count 0 2006.201.17:53:38.94#ibcon#read 4, iclass 39, count 0 2006.201.17:53:38.94#ibcon#about to read 5, iclass 39, count 0 2006.201.17:53:38.94#ibcon#read 5, iclass 39, count 0 2006.201.17:53:38.94#ibcon#about to read 6, iclass 39, count 0 2006.201.17:53:38.94#ibcon#read 6, iclass 39, count 0 2006.201.17:53:38.94#ibcon#end of sib2, iclass 39, count 0 2006.201.17:53:38.94#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:53:38.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:53:38.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.17:53:38.94#ibcon#*before write, iclass 39, count 0 2006.201.17:53:38.94#ibcon#enter sib2, iclass 39, count 0 2006.201.17:53:38.94#ibcon#flushed, iclass 39, count 0 2006.201.17:53:38.94#ibcon#about to write, iclass 39, count 0 2006.201.17:53:38.94#ibcon#wrote, iclass 39, count 0 2006.201.17:53:38.94#ibcon#about to read 3, iclass 39, count 0 2006.201.17:53:38.99#ibcon#read 3, iclass 39, count 0 2006.201.17:53:38.99#ibcon#about to read 4, iclass 39, count 0 2006.201.17:53:38.99#ibcon#read 4, iclass 39, count 0 2006.201.17:53:38.99#ibcon#about to read 5, iclass 39, count 0 2006.201.17:53:38.99#ibcon#read 5, iclass 39, count 0 2006.201.17:53:38.99#ibcon#about to read 6, iclass 39, count 0 2006.201.17:53:38.99#ibcon#read 6, iclass 39, count 0 2006.201.17:53:38.99#ibcon#end of sib2, iclass 39, count 0 2006.201.17:53:38.99#ibcon#*after write, iclass 39, count 0 2006.201.17:53:38.99#ibcon#*before return 0, iclass 39, count 0 2006.201.17:53:38.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:38.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:38.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:53:38.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:53:38.99$vck44/va=1,8 2006.201.17:53:38.99#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.17:53:38.99#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.17:53:38.99#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:38.99#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:38.99#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:38.99#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:38.99#ibcon#enter wrdev, iclass 2, count 2 2006.201.17:53:38.99#ibcon#first serial, iclass 2, count 2 2006.201.17:53:38.99#ibcon#enter sib2, iclass 2, count 2 2006.201.17:53:38.99#ibcon#flushed, iclass 2, count 2 2006.201.17:53:38.99#ibcon#about to write, iclass 2, count 2 2006.201.17:53:38.99#ibcon#wrote, iclass 2, count 2 2006.201.17:53:38.99#ibcon#about to read 3, iclass 2, count 2 2006.201.17:53:39.01#ibcon#read 3, iclass 2, count 2 2006.201.17:53:39.01#ibcon#about to read 4, iclass 2, count 2 2006.201.17:53:39.01#ibcon#read 4, iclass 2, count 2 2006.201.17:53:39.01#ibcon#about to read 5, iclass 2, count 2 2006.201.17:53:39.01#ibcon#read 5, iclass 2, count 2 2006.201.17:53:39.01#ibcon#about to read 6, iclass 2, count 2 2006.201.17:53:39.01#ibcon#read 6, iclass 2, count 2 2006.201.17:53:39.01#ibcon#end of sib2, iclass 2, count 2 2006.201.17:53:39.01#ibcon#*mode == 0, iclass 2, count 2 2006.201.17:53:39.01#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.17:53:39.01#ibcon#[25=AT01-08\r\n] 2006.201.17:53:39.01#ibcon#*before write, iclass 2, count 2 2006.201.17:53:39.01#ibcon#enter sib2, iclass 2, count 2 2006.201.17:53:39.01#ibcon#flushed, iclass 2, count 2 2006.201.17:53:39.01#ibcon#about to write, iclass 2, count 2 2006.201.17:53:39.01#ibcon#wrote, iclass 2, count 2 2006.201.17:53:39.01#ibcon#about to read 3, iclass 2, count 2 2006.201.17:53:39.04#ibcon#read 3, iclass 2, count 2 2006.201.17:53:39.04#ibcon#about to read 4, iclass 2, count 2 2006.201.17:53:39.04#ibcon#read 4, iclass 2, count 2 2006.201.17:53:39.04#ibcon#about to read 5, iclass 2, count 2 2006.201.17:53:39.04#ibcon#read 5, iclass 2, count 2 2006.201.17:53:39.04#ibcon#about to read 6, iclass 2, count 2 2006.201.17:53:39.04#ibcon#read 6, iclass 2, count 2 2006.201.17:53:39.04#ibcon#end of sib2, iclass 2, count 2 2006.201.17:53:39.04#ibcon#*after write, iclass 2, count 2 2006.201.17:53:39.04#ibcon#*before return 0, iclass 2, count 2 2006.201.17:53:39.04#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:39.04#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:39.04#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.17:53:39.04#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:39.04#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:39.16#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:39.16#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:39.16#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:53:39.16#ibcon#first serial, iclass 2, count 0 2006.201.17:53:39.16#ibcon#enter sib2, iclass 2, count 0 2006.201.17:53:39.16#ibcon#flushed, iclass 2, count 0 2006.201.17:53:39.16#ibcon#about to write, iclass 2, count 0 2006.201.17:53:39.16#ibcon#wrote, iclass 2, count 0 2006.201.17:53:39.16#ibcon#about to read 3, iclass 2, count 0 2006.201.17:53:39.18#ibcon#read 3, iclass 2, count 0 2006.201.17:53:39.18#ibcon#about to read 4, iclass 2, count 0 2006.201.17:53:39.18#ibcon#read 4, iclass 2, count 0 2006.201.17:53:39.18#ibcon#about to read 5, iclass 2, count 0 2006.201.17:53:39.18#ibcon#read 5, iclass 2, count 0 2006.201.17:53:39.18#ibcon#about to read 6, iclass 2, count 0 2006.201.17:53:39.18#ibcon#read 6, iclass 2, count 0 2006.201.17:53:39.18#ibcon#end of sib2, iclass 2, count 0 2006.201.17:53:39.18#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:53:39.18#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:53:39.18#ibcon#[25=USB\r\n] 2006.201.17:53:39.18#ibcon#*before write, iclass 2, count 0 2006.201.17:53:39.18#ibcon#enter sib2, iclass 2, count 0 2006.201.17:53:39.18#ibcon#flushed, iclass 2, count 0 2006.201.17:53:39.18#ibcon#about to write, iclass 2, count 0 2006.201.17:53:39.18#ibcon#wrote, iclass 2, count 0 2006.201.17:53:39.18#ibcon#about to read 3, iclass 2, count 0 2006.201.17:53:39.21#ibcon#read 3, iclass 2, count 0 2006.201.17:53:39.21#ibcon#about to read 4, iclass 2, count 0 2006.201.17:53:39.21#ibcon#read 4, iclass 2, count 0 2006.201.17:53:39.21#ibcon#about to read 5, iclass 2, count 0 2006.201.17:53:39.21#ibcon#read 5, iclass 2, count 0 2006.201.17:53:39.21#ibcon#about to read 6, iclass 2, count 0 2006.201.17:53:39.21#ibcon#read 6, iclass 2, count 0 2006.201.17:53:39.21#ibcon#end of sib2, iclass 2, count 0 2006.201.17:53:39.21#ibcon#*after write, iclass 2, count 0 2006.201.17:53:39.21#ibcon#*before return 0, iclass 2, count 0 2006.201.17:53:39.21#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:39.21#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:39.21#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:53:39.21#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:53:39.21$vck44/valo=2,534.99 2006.201.17:53:39.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.17:53:39.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.17:53:39.21#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:39.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:39.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:39.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:39.21#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:53:39.21#ibcon#first serial, iclass 5, count 0 2006.201.17:53:39.21#ibcon#enter sib2, iclass 5, count 0 2006.201.17:53:39.21#ibcon#flushed, iclass 5, count 0 2006.201.17:53:39.21#ibcon#about to write, iclass 5, count 0 2006.201.17:53:39.21#ibcon#wrote, iclass 5, count 0 2006.201.17:53:39.21#ibcon#about to read 3, iclass 5, count 0 2006.201.17:53:39.23#ibcon#read 3, iclass 5, count 0 2006.201.17:53:39.23#ibcon#about to read 4, iclass 5, count 0 2006.201.17:53:39.23#ibcon#read 4, iclass 5, count 0 2006.201.17:53:39.23#ibcon#about to read 5, iclass 5, count 0 2006.201.17:53:39.23#ibcon#read 5, iclass 5, count 0 2006.201.17:53:39.23#ibcon#about to read 6, iclass 5, count 0 2006.201.17:53:39.23#ibcon#read 6, iclass 5, count 0 2006.201.17:53:39.23#ibcon#end of sib2, iclass 5, count 0 2006.201.17:53:39.23#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:53:39.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:53:39.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.17:53:39.23#ibcon#*before write, iclass 5, count 0 2006.201.17:53:39.23#ibcon#enter sib2, iclass 5, count 0 2006.201.17:53:39.23#ibcon#flushed, iclass 5, count 0 2006.201.17:53:39.23#ibcon#about to write, iclass 5, count 0 2006.201.17:53:39.23#ibcon#wrote, iclass 5, count 0 2006.201.17:53:39.23#ibcon#about to read 3, iclass 5, count 0 2006.201.17:53:39.27#ibcon#read 3, iclass 5, count 0 2006.201.17:53:39.27#ibcon#about to read 4, iclass 5, count 0 2006.201.17:53:39.27#ibcon#read 4, iclass 5, count 0 2006.201.17:53:39.27#ibcon#about to read 5, iclass 5, count 0 2006.201.17:53:39.27#ibcon#read 5, iclass 5, count 0 2006.201.17:53:39.27#ibcon#about to read 6, iclass 5, count 0 2006.201.17:53:39.27#ibcon#read 6, iclass 5, count 0 2006.201.17:53:39.27#ibcon#end of sib2, iclass 5, count 0 2006.201.17:53:39.27#ibcon#*after write, iclass 5, count 0 2006.201.17:53:39.27#ibcon#*before return 0, iclass 5, count 0 2006.201.17:53:39.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:39.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:39.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:53:39.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:53:39.27$vck44/va=2,7 2006.201.17:53:39.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.17:53:39.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.17:53:39.27#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:39.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:39.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:39.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:39.33#ibcon#enter wrdev, iclass 7, count 2 2006.201.17:53:39.33#ibcon#first serial, iclass 7, count 2 2006.201.17:53:39.33#ibcon#enter sib2, iclass 7, count 2 2006.201.17:53:39.33#ibcon#flushed, iclass 7, count 2 2006.201.17:53:39.33#ibcon#about to write, iclass 7, count 2 2006.201.17:53:39.33#ibcon#wrote, iclass 7, count 2 2006.201.17:53:39.33#ibcon#about to read 3, iclass 7, count 2 2006.201.17:53:39.35#ibcon#read 3, iclass 7, count 2 2006.201.17:53:39.35#ibcon#about to read 4, iclass 7, count 2 2006.201.17:53:39.35#ibcon#read 4, iclass 7, count 2 2006.201.17:53:39.35#ibcon#about to read 5, iclass 7, count 2 2006.201.17:53:39.35#ibcon#read 5, iclass 7, count 2 2006.201.17:53:39.35#ibcon#about to read 6, iclass 7, count 2 2006.201.17:53:39.35#ibcon#read 6, iclass 7, count 2 2006.201.17:53:39.35#ibcon#end of sib2, iclass 7, count 2 2006.201.17:53:39.35#ibcon#*mode == 0, iclass 7, count 2 2006.201.17:53:39.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.17:53:39.35#ibcon#[25=AT02-07\r\n] 2006.201.17:53:39.35#ibcon#*before write, iclass 7, count 2 2006.201.17:53:39.35#ibcon#enter sib2, iclass 7, count 2 2006.201.17:53:39.35#ibcon#flushed, iclass 7, count 2 2006.201.17:53:39.35#ibcon#about to write, iclass 7, count 2 2006.201.17:53:39.35#ibcon#wrote, iclass 7, count 2 2006.201.17:53:39.35#ibcon#about to read 3, iclass 7, count 2 2006.201.17:53:39.38#ibcon#read 3, iclass 7, count 2 2006.201.17:53:39.38#ibcon#about to read 4, iclass 7, count 2 2006.201.17:53:39.38#ibcon#read 4, iclass 7, count 2 2006.201.17:53:39.38#ibcon#about to read 5, iclass 7, count 2 2006.201.17:53:39.38#ibcon#read 5, iclass 7, count 2 2006.201.17:53:39.38#ibcon#about to read 6, iclass 7, count 2 2006.201.17:53:39.38#ibcon#read 6, iclass 7, count 2 2006.201.17:53:39.38#ibcon#end of sib2, iclass 7, count 2 2006.201.17:53:39.38#ibcon#*after write, iclass 7, count 2 2006.201.17:53:39.38#ibcon#*before return 0, iclass 7, count 2 2006.201.17:53:39.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:39.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:39.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.17:53:39.38#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:39.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:39.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:39.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:39.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:53:39.50#ibcon#first serial, iclass 7, count 0 2006.201.17:53:39.50#ibcon#enter sib2, iclass 7, count 0 2006.201.17:53:39.50#ibcon#flushed, iclass 7, count 0 2006.201.17:53:39.50#ibcon#about to write, iclass 7, count 0 2006.201.17:53:39.50#ibcon#wrote, iclass 7, count 0 2006.201.17:53:39.50#ibcon#about to read 3, iclass 7, count 0 2006.201.17:53:39.52#ibcon#read 3, iclass 7, count 0 2006.201.17:53:39.52#ibcon#about to read 4, iclass 7, count 0 2006.201.17:53:39.52#ibcon#read 4, iclass 7, count 0 2006.201.17:53:39.52#ibcon#about to read 5, iclass 7, count 0 2006.201.17:53:39.52#ibcon#read 5, iclass 7, count 0 2006.201.17:53:39.52#ibcon#about to read 6, iclass 7, count 0 2006.201.17:53:39.52#ibcon#read 6, iclass 7, count 0 2006.201.17:53:39.52#ibcon#end of sib2, iclass 7, count 0 2006.201.17:53:39.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:53:39.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:53:39.52#ibcon#[25=USB\r\n] 2006.201.17:53:39.52#ibcon#*before write, iclass 7, count 0 2006.201.17:53:39.52#ibcon#enter sib2, iclass 7, count 0 2006.201.17:53:39.52#ibcon#flushed, iclass 7, count 0 2006.201.17:53:39.52#ibcon#about to write, iclass 7, count 0 2006.201.17:53:39.52#ibcon#wrote, iclass 7, count 0 2006.201.17:53:39.52#ibcon#about to read 3, iclass 7, count 0 2006.201.17:53:39.55#ibcon#read 3, iclass 7, count 0 2006.201.17:53:39.55#ibcon#about to read 4, iclass 7, count 0 2006.201.17:53:39.55#ibcon#read 4, iclass 7, count 0 2006.201.17:53:39.55#ibcon#about to read 5, iclass 7, count 0 2006.201.17:53:39.55#ibcon#read 5, iclass 7, count 0 2006.201.17:53:39.55#ibcon#about to read 6, iclass 7, count 0 2006.201.17:53:39.55#ibcon#read 6, iclass 7, count 0 2006.201.17:53:39.55#ibcon#end of sib2, iclass 7, count 0 2006.201.17:53:39.55#ibcon#*after write, iclass 7, count 0 2006.201.17:53:39.55#ibcon#*before return 0, iclass 7, count 0 2006.201.17:53:39.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:39.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:39.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:53:39.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:53:39.55$vck44/valo=3,564.99 2006.201.17:53:39.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.17:53:39.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.17:53:39.55#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:39.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:39.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:39.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:39.55#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:53:39.55#ibcon#first serial, iclass 11, count 0 2006.201.17:53:39.55#ibcon#enter sib2, iclass 11, count 0 2006.201.17:53:39.55#ibcon#flushed, iclass 11, count 0 2006.201.17:53:39.55#ibcon#about to write, iclass 11, count 0 2006.201.17:53:39.55#ibcon#wrote, iclass 11, count 0 2006.201.17:53:39.55#ibcon#about to read 3, iclass 11, count 0 2006.201.17:53:39.57#ibcon#read 3, iclass 11, count 0 2006.201.17:53:39.57#ibcon#about to read 4, iclass 11, count 0 2006.201.17:53:39.57#ibcon#read 4, iclass 11, count 0 2006.201.17:53:39.57#ibcon#about to read 5, iclass 11, count 0 2006.201.17:53:39.57#ibcon#read 5, iclass 11, count 0 2006.201.17:53:39.57#ibcon#about to read 6, iclass 11, count 0 2006.201.17:53:39.57#ibcon#read 6, iclass 11, count 0 2006.201.17:53:39.57#ibcon#end of sib2, iclass 11, count 0 2006.201.17:53:39.57#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:53:39.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:53:39.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.17:53:39.57#ibcon#*before write, iclass 11, count 0 2006.201.17:53:39.57#ibcon#enter sib2, iclass 11, count 0 2006.201.17:53:39.57#ibcon#flushed, iclass 11, count 0 2006.201.17:53:39.57#ibcon#about to write, iclass 11, count 0 2006.201.17:53:39.57#ibcon#wrote, iclass 11, count 0 2006.201.17:53:39.57#ibcon#about to read 3, iclass 11, count 0 2006.201.17:53:39.62#ibcon#read 3, iclass 11, count 0 2006.201.17:53:39.62#ibcon#about to read 4, iclass 11, count 0 2006.201.17:53:39.62#ibcon#read 4, iclass 11, count 0 2006.201.17:53:39.62#ibcon#about to read 5, iclass 11, count 0 2006.201.17:53:39.62#ibcon#read 5, iclass 11, count 0 2006.201.17:53:39.62#ibcon#about to read 6, iclass 11, count 0 2006.201.17:53:39.62#ibcon#read 6, iclass 11, count 0 2006.201.17:53:39.62#ibcon#end of sib2, iclass 11, count 0 2006.201.17:53:39.62#ibcon#*after write, iclass 11, count 0 2006.201.17:53:39.62#ibcon#*before return 0, iclass 11, count 0 2006.201.17:53:39.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:39.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:39.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:53:39.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:53:39.62$vck44/va=3,8 2006.201.17:53:39.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.17:53:39.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.17:53:39.62#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:39.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:39.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:39.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:39.67#ibcon#enter wrdev, iclass 13, count 2 2006.201.17:53:39.67#ibcon#first serial, iclass 13, count 2 2006.201.17:53:39.67#ibcon#enter sib2, iclass 13, count 2 2006.201.17:53:39.67#ibcon#flushed, iclass 13, count 2 2006.201.17:53:39.67#ibcon#about to write, iclass 13, count 2 2006.201.17:53:39.67#ibcon#wrote, iclass 13, count 2 2006.201.17:53:39.67#ibcon#about to read 3, iclass 13, count 2 2006.201.17:53:39.69#ibcon#read 3, iclass 13, count 2 2006.201.17:53:39.69#ibcon#about to read 4, iclass 13, count 2 2006.201.17:53:39.69#ibcon#read 4, iclass 13, count 2 2006.201.17:53:39.69#ibcon#about to read 5, iclass 13, count 2 2006.201.17:53:39.69#ibcon#read 5, iclass 13, count 2 2006.201.17:53:39.69#ibcon#about to read 6, iclass 13, count 2 2006.201.17:53:39.69#ibcon#read 6, iclass 13, count 2 2006.201.17:53:39.69#ibcon#end of sib2, iclass 13, count 2 2006.201.17:53:39.69#ibcon#*mode == 0, iclass 13, count 2 2006.201.17:53:39.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.17:53:39.69#ibcon#[25=AT03-08\r\n] 2006.201.17:53:39.69#ibcon#*before write, iclass 13, count 2 2006.201.17:53:39.69#ibcon#enter sib2, iclass 13, count 2 2006.201.17:53:39.69#ibcon#flushed, iclass 13, count 2 2006.201.17:53:39.69#ibcon#about to write, iclass 13, count 2 2006.201.17:53:39.69#ibcon#wrote, iclass 13, count 2 2006.201.17:53:39.69#ibcon#about to read 3, iclass 13, count 2 2006.201.17:53:39.72#ibcon#read 3, iclass 13, count 2 2006.201.17:53:39.72#ibcon#about to read 4, iclass 13, count 2 2006.201.17:53:39.72#ibcon#read 4, iclass 13, count 2 2006.201.17:53:39.72#ibcon#about to read 5, iclass 13, count 2 2006.201.17:53:39.72#ibcon#read 5, iclass 13, count 2 2006.201.17:53:39.72#ibcon#about to read 6, iclass 13, count 2 2006.201.17:53:39.72#ibcon#read 6, iclass 13, count 2 2006.201.17:53:39.72#ibcon#end of sib2, iclass 13, count 2 2006.201.17:53:39.72#ibcon#*after write, iclass 13, count 2 2006.201.17:53:39.72#ibcon#*before return 0, iclass 13, count 2 2006.201.17:53:39.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:39.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:39.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.17:53:39.72#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:39.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:39.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:39.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:39.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:53:39.84#ibcon#first serial, iclass 13, count 0 2006.201.17:53:39.84#ibcon#enter sib2, iclass 13, count 0 2006.201.17:53:39.84#ibcon#flushed, iclass 13, count 0 2006.201.17:53:39.84#ibcon#about to write, iclass 13, count 0 2006.201.17:53:39.84#ibcon#wrote, iclass 13, count 0 2006.201.17:53:39.84#ibcon#about to read 3, iclass 13, count 0 2006.201.17:53:39.86#ibcon#read 3, iclass 13, count 0 2006.201.17:53:39.86#ibcon#about to read 4, iclass 13, count 0 2006.201.17:53:39.86#ibcon#read 4, iclass 13, count 0 2006.201.17:53:39.86#ibcon#about to read 5, iclass 13, count 0 2006.201.17:53:39.86#ibcon#read 5, iclass 13, count 0 2006.201.17:53:39.86#ibcon#about to read 6, iclass 13, count 0 2006.201.17:53:39.86#ibcon#read 6, iclass 13, count 0 2006.201.17:53:39.86#ibcon#end of sib2, iclass 13, count 0 2006.201.17:53:39.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:53:39.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:53:39.86#ibcon#[25=USB\r\n] 2006.201.17:53:39.86#ibcon#*before write, iclass 13, count 0 2006.201.17:53:39.86#ibcon#enter sib2, iclass 13, count 0 2006.201.17:53:39.86#ibcon#flushed, iclass 13, count 0 2006.201.17:53:39.86#ibcon#about to write, iclass 13, count 0 2006.201.17:53:39.86#ibcon#wrote, iclass 13, count 0 2006.201.17:53:39.86#ibcon#about to read 3, iclass 13, count 0 2006.201.17:53:39.89#ibcon#read 3, iclass 13, count 0 2006.201.17:53:39.89#ibcon#about to read 4, iclass 13, count 0 2006.201.17:53:39.89#ibcon#read 4, iclass 13, count 0 2006.201.17:53:39.89#ibcon#about to read 5, iclass 13, count 0 2006.201.17:53:39.89#ibcon#read 5, iclass 13, count 0 2006.201.17:53:39.89#ibcon#about to read 6, iclass 13, count 0 2006.201.17:53:39.89#ibcon#read 6, iclass 13, count 0 2006.201.17:53:39.89#ibcon#end of sib2, iclass 13, count 0 2006.201.17:53:39.89#ibcon#*after write, iclass 13, count 0 2006.201.17:53:39.89#ibcon#*before return 0, iclass 13, count 0 2006.201.17:53:39.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:39.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:39.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:53:39.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:53:39.89$vck44/valo=4,624.99 2006.201.17:53:39.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.17:53:39.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.17:53:39.89#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:39.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:39.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:39.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:39.89#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:53:39.89#ibcon#first serial, iclass 15, count 0 2006.201.17:53:39.89#ibcon#enter sib2, iclass 15, count 0 2006.201.17:53:39.89#ibcon#flushed, iclass 15, count 0 2006.201.17:53:39.89#ibcon#about to write, iclass 15, count 0 2006.201.17:53:39.89#ibcon#wrote, iclass 15, count 0 2006.201.17:53:39.89#ibcon#about to read 3, iclass 15, count 0 2006.201.17:53:39.91#ibcon#read 3, iclass 15, count 0 2006.201.17:53:39.91#ibcon#about to read 4, iclass 15, count 0 2006.201.17:53:39.91#ibcon#read 4, iclass 15, count 0 2006.201.17:53:39.91#ibcon#about to read 5, iclass 15, count 0 2006.201.17:53:39.91#ibcon#read 5, iclass 15, count 0 2006.201.17:53:39.91#ibcon#about to read 6, iclass 15, count 0 2006.201.17:53:39.91#ibcon#read 6, iclass 15, count 0 2006.201.17:53:39.91#ibcon#end of sib2, iclass 15, count 0 2006.201.17:53:39.91#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:53:39.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:53:39.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.17:53:39.91#ibcon#*before write, iclass 15, count 0 2006.201.17:53:39.91#ibcon#enter sib2, iclass 15, count 0 2006.201.17:53:39.91#ibcon#flushed, iclass 15, count 0 2006.201.17:53:39.91#ibcon#about to write, iclass 15, count 0 2006.201.17:53:39.91#ibcon#wrote, iclass 15, count 0 2006.201.17:53:39.91#ibcon#about to read 3, iclass 15, count 0 2006.201.17:53:39.95#ibcon#read 3, iclass 15, count 0 2006.201.17:53:39.95#ibcon#about to read 4, iclass 15, count 0 2006.201.17:53:39.95#ibcon#read 4, iclass 15, count 0 2006.201.17:53:39.95#ibcon#about to read 5, iclass 15, count 0 2006.201.17:53:39.95#ibcon#read 5, iclass 15, count 0 2006.201.17:53:39.95#ibcon#about to read 6, iclass 15, count 0 2006.201.17:53:39.95#ibcon#read 6, iclass 15, count 0 2006.201.17:53:39.95#ibcon#end of sib2, iclass 15, count 0 2006.201.17:53:39.95#ibcon#*after write, iclass 15, count 0 2006.201.17:53:39.95#ibcon#*before return 0, iclass 15, count 0 2006.201.17:53:39.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:39.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:39.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:53:39.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:53:39.95$vck44/va=4,7 2006.201.17:53:39.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.17:53:39.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.17:53:39.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:39.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:40.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:40.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:40.01#ibcon#enter wrdev, iclass 17, count 2 2006.201.17:53:40.01#ibcon#first serial, iclass 17, count 2 2006.201.17:53:40.01#ibcon#enter sib2, iclass 17, count 2 2006.201.17:53:40.01#ibcon#flushed, iclass 17, count 2 2006.201.17:53:40.01#ibcon#about to write, iclass 17, count 2 2006.201.17:53:40.01#ibcon#wrote, iclass 17, count 2 2006.201.17:53:40.01#ibcon#about to read 3, iclass 17, count 2 2006.201.17:53:40.03#ibcon#read 3, iclass 17, count 2 2006.201.17:53:40.03#ibcon#about to read 4, iclass 17, count 2 2006.201.17:53:40.03#ibcon#read 4, iclass 17, count 2 2006.201.17:53:40.03#ibcon#about to read 5, iclass 17, count 2 2006.201.17:53:40.03#ibcon#read 5, iclass 17, count 2 2006.201.17:53:40.03#ibcon#about to read 6, iclass 17, count 2 2006.201.17:53:40.03#ibcon#read 6, iclass 17, count 2 2006.201.17:53:40.03#ibcon#end of sib2, iclass 17, count 2 2006.201.17:53:40.03#ibcon#*mode == 0, iclass 17, count 2 2006.201.17:53:40.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.17:53:40.03#ibcon#[25=AT04-07\r\n] 2006.201.17:53:40.03#ibcon#*before write, iclass 17, count 2 2006.201.17:53:40.03#ibcon#enter sib2, iclass 17, count 2 2006.201.17:53:40.03#ibcon#flushed, iclass 17, count 2 2006.201.17:53:40.03#ibcon#about to write, iclass 17, count 2 2006.201.17:53:40.03#ibcon#wrote, iclass 17, count 2 2006.201.17:53:40.03#ibcon#about to read 3, iclass 17, count 2 2006.201.17:53:40.06#ibcon#read 3, iclass 17, count 2 2006.201.17:53:40.06#ibcon#about to read 4, iclass 17, count 2 2006.201.17:53:40.06#ibcon#read 4, iclass 17, count 2 2006.201.17:53:40.06#ibcon#about to read 5, iclass 17, count 2 2006.201.17:53:40.06#ibcon#read 5, iclass 17, count 2 2006.201.17:53:40.06#ibcon#about to read 6, iclass 17, count 2 2006.201.17:53:40.06#ibcon#read 6, iclass 17, count 2 2006.201.17:53:40.06#ibcon#end of sib2, iclass 17, count 2 2006.201.17:53:40.06#ibcon#*after write, iclass 17, count 2 2006.201.17:53:40.06#ibcon#*before return 0, iclass 17, count 2 2006.201.17:53:40.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:40.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:40.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.17:53:40.06#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:40.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:40.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:40.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:40.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:53:40.18#ibcon#first serial, iclass 17, count 0 2006.201.17:53:40.18#ibcon#enter sib2, iclass 17, count 0 2006.201.17:53:40.18#ibcon#flushed, iclass 17, count 0 2006.201.17:53:40.18#ibcon#about to write, iclass 17, count 0 2006.201.17:53:40.18#ibcon#wrote, iclass 17, count 0 2006.201.17:53:40.18#ibcon#about to read 3, iclass 17, count 0 2006.201.17:53:40.20#ibcon#read 3, iclass 17, count 0 2006.201.17:53:40.20#ibcon#about to read 4, iclass 17, count 0 2006.201.17:53:40.20#ibcon#read 4, iclass 17, count 0 2006.201.17:53:40.20#ibcon#about to read 5, iclass 17, count 0 2006.201.17:53:40.20#ibcon#read 5, iclass 17, count 0 2006.201.17:53:40.20#ibcon#about to read 6, iclass 17, count 0 2006.201.17:53:40.20#ibcon#read 6, iclass 17, count 0 2006.201.17:53:40.20#ibcon#end of sib2, iclass 17, count 0 2006.201.17:53:40.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:53:40.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:53:40.20#ibcon#[25=USB\r\n] 2006.201.17:53:40.20#ibcon#*before write, iclass 17, count 0 2006.201.17:53:40.20#ibcon#enter sib2, iclass 17, count 0 2006.201.17:53:40.20#ibcon#flushed, iclass 17, count 0 2006.201.17:53:40.20#ibcon#about to write, iclass 17, count 0 2006.201.17:53:40.20#ibcon#wrote, iclass 17, count 0 2006.201.17:53:40.20#ibcon#about to read 3, iclass 17, count 0 2006.201.17:53:40.23#ibcon#read 3, iclass 17, count 0 2006.201.17:53:40.23#ibcon#about to read 4, iclass 17, count 0 2006.201.17:53:40.23#ibcon#read 4, iclass 17, count 0 2006.201.17:53:40.23#ibcon#about to read 5, iclass 17, count 0 2006.201.17:53:40.23#ibcon#read 5, iclass 17, count 0 2006.201.17:53:40.23#ibcon#about to read 6, iclass 17, count 0 2006.201.17:53:40.23#ibcon#read 6, iclass 17, count 0 2006.201.17:53:40.23#ibcon#end of sib2, iclass 17, count 0 2006.201.17:53:40.23#ibcon#*after write, iclass 17, count 0 2006.201.17:53:40.23#ibcon#*before return 0, iclass 17, count 0 2006.201.17:53:40.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:40.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:40.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:53:40.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:53:40.23$vck44/valo=5,734.99 2006.201.17:53:40.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.17:53:40.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.17:53:40.23#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:40.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:40.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:40.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:40.23#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:53:40.23#ibcon#first serial, iclass 19, count 0 2006.201.17:53:40.23#ibcon#enter sib2, iclass 19, count 0 2006.201.17:53:40.23#ibcon#flushed, iclass 19, count 0 2006.201.17:53:40.23#ibcon#about to write, iclass 19, count 0 2006.201.17:53:40.23#ibcon#wrote, iclass 19, count 0 2006.201.17:53:40.23#ibcon#about to read 3, iclass 19, count 0 2006.201.17:53:40.25#ibcon#read 3, iclass 19, count 0 2006.201.17:53:40.25#ibcon#about to read 4, iclass 19, count 0 2006.201.17:53:40.25#ibcon#read 4, iclass 19, count 0 2006.201.17:53:40.25#ibcon#about to read 5, iclass 19, count 0 2006.201.17:53:40.25#ibcon#read 5, iclass 19, count 0 2006.201.17:53:40.25#ibcon#about to read 6, iclass 19, count 0 2006.201.17:53:40.25#ibcon#read 6, iclass 19, count 0 2006.201.17:53:40.25#ibcon#end of sib2, iclass 19, count 0 2006.201.17:53:40.25#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:53:40.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:53:40.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.17:53:40.25#ibcon#*before write, iclass 19, count 0 2006.201.17:53:40.25#ibcon#enter sib2, iclass 19, count 0 2006.201.17:53:40.25#ibcon#flushed, iclass 19, count 0 2006.201.17:53:40.25#ibcon#about to write, iclass 19, count 0 2006.201.17:53:40.25#ibcon#wrote, iclass 19, count 0 2006.201.17:53:40.25#ibcon#about to read 3, iclass 19, count 0 2006.201.17:53:40.29#ibcon#read 3, iclass 19, count 0 2006.201.17:53:40.29#ibcon#about to read 4, iclass 19, count 0 2006.201.17:53:40.29#ibcon#read 4, iclass 19, count 0 2006.201.17:53:40.29#ibcon#about to read 5, iclass 19, count 0 2006.201.17:53:40.29#ibcon#read 5, iclass 19, count 0 2006.201.17:53:40.29#ibcon#about to read 6, iclass 19, count 0 2006.201.17:53:40.29#ibcon#read 6, iclass 19, count 0 2006.201.17:53:40.29#ibcon#end of sib2, iclass 19, count 0 2006.201.17:53:40.29#ibcon#*after write, iclass 19, count 0 2006.201.17:53:40.29#ibcon#*before return 0, iclass 19, count 0 2006.201.17:53:40.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:40.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:40.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:53:40.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:53:40.29$vck44/va=5,4 2006.201.17:53:40.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.17:53:40.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.17:53:40.29#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:40.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:40.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:40.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:40.35#ibcon#enter wrdev, iclass 21, count 2 2006.201.17:53:40.35#ibcon#first serial, iclass 21, count 2 2006.201.17:53:40.35#ibcon#enter sib2, iclass 21, count 2 2006.201.17:53:40.35#ibcon#flushed, iclass 21, count 2 2006.201.17:53:40.35#ibcon#about to write, iclass 21, count 2 2006.201.17:53:40.35#ibcon#wrote, iclass 21, count 2 2006.201.17:53:40.35#ibcon#about to read 3, iclass 21, count 2 2006.201.17:53:40.37#ibcon#read 3, iclass 21, count 2 2006.201.17:53:40.37#ibcon#about to read 4, iclass 21, count 2 2006.201.17:53:40.37#ibcon#read 4, iclass 21, count 2 2006.201.17:53:40.37#ibcon#about to read 5, iclass 21, count 2 2006.201.17:53:40.37#ibcon#read 5, iclass 21, count 2 2006.201.17:53:40.37#ibcon#about to read 6, iclass 21, count 2 2006.201.17:53:40.37#ibcon#read 6, iclass 21, count 2 2006.201.17:53:40.37#ibcon#end of sib2, iclass 21, count 2 2006.201.17:53:40.37#ibcon#*mode == 0, iclass 21, count 2 2006.201.17:53:40.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.17:53:40.37#ibcon#[25=AT05-04\r\n] 2006.201.17:53:40.37#ibcon#*before write, iclass 21, count 2 2006.201.17:53:40.37#ibcon#enter sib2, iclass 21, count 2 2006.201.17:53:40.37#ibcon#flushed, iclass 21, count 2 2006.201.17:53:40.37#ibcon#about to write, iclass 21, count 2 2006.201.17:53:40.37#ibcon#wrote, iclass 21, count 2 2006.201.17:53:40.37#ibcon#about to read 3, iclass 21, count 2 2006.201.17:53:40.40#ibcon#read 3, iclass 21, count 2 2006.201.17:53:40.40#ibcon#about to read 4, iclass 21, count 2 2006.201.17:53:40.40#ibcon#read 4, iclass 21, count 2 2006.201.17:53:40.40#ibcon#about to read 5, iclass 21, count 2 2006.201.17:53:40.40#ibcon#read 5, iclass 21, count 2 2006.201.17:53:40.40#ibcon#about to read 6, iclass 21, count 2 2006.201.17:53:40.40#ibcon#read 6, iclass 21, count 2 2006.201.17:53:40.40#ibcon#end of sib2, iclass 21, count 2 2006.201.17:53:40.40#ibcon#*after write, iclass 21, count 2 2006.201.17:53:40.40#ibcon#*before return 0, iclass 21, count 2 2006.201.17:53:40.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:40.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:40.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.17:53:40.40#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:40.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:40.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:40.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:40.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.17:53:40.52#ibcon#first serial, iclass 21, count 0 2006.201.17:53:40.52#ibcon#enter sib2, iclass 21, count 0 2006.201.17:53:40.52#ibcon#flushed, iclass 21, count 0 2006.201.17:53:40.52#ibcon#about to write, iclass 21, count 0 2006.201.17:53:40.52#ibcon#wrote, iclass 21, count 0 2006.201.17:53:40.52#ibcon#about to read 3, iclass 21, count 0 2006.201.17:53:40.54#ibcon#read 3, iclass 21, count 0 2006.201.17:53:40.54#ibcon#about to read 4, iclass 21, count 0 2006.201.17:53:40.54#ibcon#read 4, iclass 21, count 0 2006.201.17:53:40.54#ibcon#about to read 5, iclass 21, count 0 2006.201.17:53:40.54#ibcon#read 5, iclass 21, count 0 2006.201.17:53:40.54#ibcon#about to read 6, iclass 21, count 0 2006.201.17:53:40.54#ibcon#read 6, iclass 21, count 0 2006.201.17:53:40.54#ibcon#end of sib2, iclass 21, count 0 2006.201.17:53:40.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.17:53:40.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.17:53:40.54#ibcon#[25=USB\r\n] 2006.201.17:53:40.54#ibcon#*before write, iclass 21, count 0 2006.201.17:53:40.54#ibcon#enter sib2, iclass 21, count 0 2006.201.17:53:40.54#ibcon#flushed, iclass 21, count 0 2006.201.17:53:40.54#ibcon#about to write, iclass 21, count 0 2006.201.17:53:40.54#ibcon#wrote, iclass 21, count 0 2006.201.17:53:40.54#ibcon#about to read 3, iclass 21, count 0 2006.201.17:53:40.57#ibcon#read 3, iclass 21, count 0 2006.201.17:53:40.57#ibcon#about to read 4, iclass 21, count 0 2006.201.17:53:40.57#ibcon#read 4, iclass 21, count 0 2006.201.17:53:40.57#ibcon#about to read 5, iclass 21, count 0 2006.201.17:53:40.57#ibcon#read 5, iclass 21, count 0 2006.201.17:53:40.57#ibcon#about to read 6, iclass 21, count 0 2006.201.17:53:40.57#ibcon#read 6, iclass 21, count 0 2006.201.17:53:40.57#ibcon#end of sib2, iclass 21, count 0 2006.201.17:53:40.57#ibcon#*after write, iclass 21, count 0 2006.201.17:53:40.57#ibcon#*before return 0, iclass 21, count 0 2006.201.17:53:40.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:40.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:40.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.17:53:40.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.17:53:40.57$vck44/valo=6,814.99 2006.201.17:53:40.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.17:53:40.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.17:53:40.57#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:40.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:40.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:40.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:40.57#ibcon#enter wrdev, iclass 23, count 0 2006.201.17:53:40.57#ibcon#first serial, iclass 23, count 0 2006.201.17:53:40.57#ibcon#enter sib2, iclass 23, count 0 2006.201.17:53:40.57#ibcon#flushed, iclass 23, count 0 2006.201.17:53:40.57#ibcon#about to write, iclass 23, count 0 2006.201.17:53:40.57#ibcon#wrote, iclass 23, count 0 2006.201.17:53:40.57#ibcon#about to read 3, iclass 23, count 0 2006.201.17:53:40.59#ibcon#read 3, iclass 23, count 0 2006.201.17:53:40.59#ibcon#about to read 4, iclass 23, count 0 2006.201.17:53:40.59#ibcon#read 4, iclass 23, count 0 2006.201.17:53:40.59#ibcon#about to read 5, iclass 23, count 0 2006.201.17:53:40.59#ibcon#read 5, iclass 23, count 0 2006.201.17:53:40.59#ibcon#about to read 6, iclass 23, count 0 2006.201.17:53:40.59#ibcon#read 6, iclass 23, count 0 2006.201.17:53:40.59#ibcon#end of sib2, iclass 23, count 0 2006.201.17:53:40.59#ibcon#*mode == 0, iclass 23, count 0 2006.201.17:53:40.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.17:53:40.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.17:53:40.59#ibcon#*before write, iclass 23, count 0 2006.201.17:53:40.59#ibcon#enter sib2, iclass 23, count 0 2006.201.17:53:40.59#ibcon#flushed, iclass 23, count 0 2006.201.17:53:40.59#ibcon#about to write, iclass 23, count 0 2006.201.17:53:40.59#ibcon#wrote, iclass 23, count 0 2006.201.17:53:40.59#ibcon#about to read 3, iclass 23, count 0 2006.201.17:53:40.63#ibcon#read 3, iclass 23, count 0 2006.201.17:53:40.63#ibcon#about to read 4, iclass 23, count 0 2006.201.17:53:40.63#ibcon#read 4, iclass 23, count 0 2006.201.17:53:40.63#ibcon#about to read 5, iclass 23, count 0 2006.201.17:53:40.63#ibcon#read 5, iclass 23, count 0 2006.201.17:53:40.63#ibcon#about to read 6, iclass 23, count 0 2006.201.17:53:40.63#ibcon#read 6, iclass 23, count 0 2006.201.17:53:40.63#ibcon#end of sib2, iclass 23, count 0 2006.201.17:53:40.63#ibcon#*after write, iclass 23, count 0 2006.201.17:53:40.63#ibcon#*before return 0, iclass 23, count 0 2006.201.17:53:40.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:40.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:40.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.17:53:40.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.17:53:40.63$vck44/va=6,5 2006.201.17:53:40.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.17:53:40.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.17:53:40.63#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:40.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:40.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:40.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:40.69#ibcon#enter wrdev, iclass 25, count 2 2006.201.17:53:40.69#ibcon#first serial, iclass 25, count 2 2006.201.17:53:40.69#ibcon#enter sib2, iclass 25, count 2 2006.201.17:53:40.69#ibcon#flushed, iclass 25, count 2 2006.201.17:53:40.69#ibcon#about to write, iclass 25, count 2 2006.201.17:53:40.69#ibcon#wrote, iclass 25, count 2 2006.201.17:53:40.69#ibcon#about to read 3, iclass 25, count 2 2006.201.17:53:40.71#ibcon#read 3, iclass 25, count 2 2006.201.17:53:40.71#ibcon#about to read 4, iclass 25, count 2 2006.201.17:53:40.71#ibcon#read 4, iclass 25, count 2 2006.201.17:53:40.71#ibcon#about to read 5, iclass 25, count 2 2006.201.17:53:40.71#ibcon#read 5, iclass 25, count 2 2006.201.17:53:40.71#ibcon#about to read 6, iclass 25, count 2 2006.201.17:53:40.71#ibcon#read 6, iclass 25, count 2 2006.201.17:53:40.71#ibcon#end of sib2, iclass 25, count 2 2006.201.17:53:40.71#ibcon#*mode == 0, iclass 25, count 2 2006.201.17:53:40.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.17:53:40.71#ibcon#[25=AT06-05\r\n] 2006.201.17:53:40.71#ibcon#*before write, iclass 25, count 2 2006.201.17:53:40.71#ibcon#enter sib2, iclass 25, count 2 2006.201.17:53:40.71#ibcon#flushed, iclass 25, count 2 2006.201.17:53:40.71#ibcon#about to write, iclass 25, count 2 2006.201.17:53:40.71#ibcon#wrote, iclass 25, count 2 2006.201.17:53:40.71#ibcon#about to read 3, iclass 25, count 2 2006.201.17:53:40.74#ibcon#read 3, iclass 25, count 2 2006.201.17:53:40.74#ibcon#about to read 4, iclass 25, count 2 2006.201.17:53:40.74#ibcon#read 4, iclass 25, count 2 2006.201.17:53:40.74#ibcon#about to read 5, iclass 25, count 2 2006.201.17:53:40.74#ibcon#read 5, iclass 25, count 2 2006.201.17:53:40.74#ibcon#about to read 6, iclass 25, count 2 2006.201.17:53:40.74#ibcon#read 6, iclass 25, count 2 2006.201.17:53:40.74#ibcon#end of sib2, iclass 25, count 2 2006.201.17:53:40.74#ibcon#*after write, iclass 25, count 2 2006.201.17:53:40.74#ibcon#*before return 0, iclass 25, count 2 2006.201.17:53:40.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:40.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:40.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.17:53:40.74#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:40.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:40.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:40.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:40.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:53:40.86#ibcon#first serial, iclass 25, count 0 2006.201.17:53:40.86#ibcon#enter sib2, iclass 25, count 0 2006.201.17:53:40.86#ibcon#flushed, iclass 25, count 0 2006.201.17:53:40.86#ibcon#about to write, iclass 25, count 0 2006.201.17:53:40.86#ibcon#wrote, iclass 25, count 0 2006.201.17:53:40.86#ibcon#about to read 3, iclass 25, count 0 2006.201.17:53:40.88#ibcon#read 3, iclass 25, count 0 2006.201.17:53:40.88#ibcon#about to read 4, iclass 25, count 0 2006.201.17:53:40.88#ibcon#read 4, iclass 25, count 0 2006.201.17:53:40.88#ibcon#about to read 5, iclass 25, count 0 2006.201.17:53:40.88#ibcon#read 5, iclass 25, count 0 2006.201.17:53:40.88#ibcon#about to read 6, iclass 25, count 0 2006.201.17:53:40.88#ibcon#read 6, iclass 25, count 0 2006.201.17:53:40.88#ibcon#end of sib2, iclass 25, count 0 2006.201.17:53:40.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:53:40.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:53:40.88#ibcon#[25=USB\r\n] 2006.201.17:53:40.88#ibcon#*before write, iclass 25, count 0 2006.201.17:53:40.88#ibcon#enter sib2, iclass 25, count 0 2006.201.17:53:40.88#ibcon#flushed, iclass 25, count 0 2006.201.17:53:40.88#ibcon#about to write, iclass 25, count 0 2006.201.17:53:40.88#ibcon#wrote, iclass 25, count 0 2006.201.17:53:40.88#ibcon#about to read 3, iclass 25, count 0 2006.201.17:53:40.91#ibcon#read 3, iclass 25, count 0 2006.201.17:53:40.91#ibcon#about to read 4, iclass 25, count 0 2006.201.17:53:40.91#ibcon#read 4, iclass 25, count 0 2006.201.17:53:40.91#ibcon#about to read 5, iclass 25, count 0 2006.201.17:53:40.91#ibcon#read 5, iclass 25, count 0 2006.201.17:53:40.91#ibcon#about to read 6, iclass 25, count 0 2006.201.17:53:40.91#ibcon#read 6, iclass 25, count 0 2006.201.17:53:40.91#ibcon#end of sib2, iclass 25, count 0 2006.201.17:53:40.91#ibcon#*after write, iclass 25, count 0 2006.201.17:53:40.91#ibcon#*before return 0, iclass 25, count 0 2006.201.17:53:40.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:40.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:40.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:53:40.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:53:40.91$vck44/valo=7,864.99 2006.201.17:53:40.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.17:53:40.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.17:53:40.91#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:40.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:40.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:40.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:40.91#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:53:40.91#ibcon#first serial, iclass 27, count 0 2006.201.17:53:40.91#ibcon#enter sib2, iclass 27, count 0 2006.201.17:53:40.91#ibcon#flushed, iclass 27, count 0 2006.201.17:53:40.91#ibcon#about to write, iclass 27, count 0 2006.201.17:53:40.91#ibcon#wrote, iclass 27, count 0 2006.201.17:53:40.91#ibcon#about to read 3, iclass 27, count 0 2006.201.17:53:40.93#ibcon#read 3, iclass 27, count 0 2006.201.17:53:40.93#ibcon#about to read 4, iclass 27, count 0 2006.201.17:53:40.93#ibcon#read 4, iclass 27, count 0 2006.201.17:53:40.93#ibcon#about to read 5, iclass 27, count 0 2006.201.17:53:40.93#ibcon#read 5, iclass 27, count 0 2006.201.17:53:40.93#ibcon#about to read 6, iclass 27, count 0 2006.201.17:53:40.93#ibcon#read 6, iclass 27, count 0 2006.201.17:53:40.93#ibcon#end of sib2, iclass 27, count 0 2006.201.17:53:40.93#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:53:40.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:53:40.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.17:53:40.93#ibcon#*before write, iclass 27, count 0 2006.201.17:53:40.93#ibcon#enter sib2, iclass 27, count 0 2006.201.17:53:40.93#ibcon#flushed, iclass 27, count 0 2006.201.17:53:40.93#ibcon#about to write, iclass 27, count 0 2006.201.17:53:40.93#ibcon#wrote, iclass 27, count 0 2006.201.17:53:40.93#ibcon#about to read 3, iclass 27, count 0 2006.201.17:53:40.98#ibcon#read 3, iclass 27, count 0 2006.201.17:53:40.98#ibcon#about to read 4, iclass 27, count 0 2006.201.17:53:40.98#ibcon#read 4, iclass 27, count 0 2006.201.17:53:40.98#ibcon#about to read 5, iclass 27, count 0 2006.201.17:53:40.98#ibcon#read 5, iclass 27, count 0 2006.201.17:53:40.98#ibcon#about to read 6, iclass 27, count 0 2006.201.17:53:40.98#ibcon#read 6, iclass 27, count 0 2006.201.17:53:40.98#ibcon#end of sib2, iclass 27, count 0 2006.201.17:53:40.98#ibcon#*after write, iclass 27, count 0 2006.201.17:53:40.98#ibcon#*before return 0, iclass 27, count 0 2006.201.17:53:40.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:40.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:40.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:53:40.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:53:40.98$vck44/va=7,5 2006.201.17:53:40.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.17:53:40.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.17:53:40.98#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:40.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:41.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:41.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:41.03#ibcon#enter wrdev, iclass 29, count 2 2006.201.17:53:41.03#ibcon#first serial, iclass 29, count 2 2006.201.17:53:41.03#ibcon#enter sib2, iclass 29, count 2 2006.201.17:53:41.03#ibcon#flushed, iclass 29, count 2 2006.201.17:53:41.03#ibcon#about to write, iclass 29, count 2 2006.201.17:53:41.03#ibcon#wrote, iclass 29, count 2 2006.201.17:53:41.03#ibcon#about to read 3, iclass 29, count 2 2006.201.17:53:41.05#ibcon#read 3, iclass 29, count 2 2006.201.17:53:41.05#ibcon#about to read 4, iclass 29, count 2 2006.201.17:53:41.05#ibcon#read 4, iclass 29, count 2 2006.201.17:53:41.05#ibcon#about to read 5, iclass 29, count 2 2006.201.17:53:41.05#ibcon#read 5, iclass 29, count 2 2006.201.17:53:41.05#ibcon#about to read 6, iclass 29, count 2 2006.201.17:53:41.05#ibcon#read 6, iclass 29, count 2 2006.201.17:53:41.05#ibcon#end of sib2, iclass 29, count 2 2006.201.17:53:41.05#ibcon#*mode == 0, iclass 29, count 2 2006.201.17:53:41.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.17:53:41.05#ibcon#[25=AT07-05\r\n] 2006.201.17:53:41.05#ibcon#*before write, iclass 29, count 2 2006.201.17:53:41.05#ibcon#enter sib2, iclass 29, count 2 2006.201.17:53:41.05#ibcon#flushed, iclass 29, count 2 2006.201.17:53:41.05#ibcon#about to write, iclass 29, count 2 2006.201.17:53:41.05#ibcon#wrote, iclass 29, count 2 2006.201.17:53:41.05#ibcon#about to read 3, iclass 29, count 2 2006.201.17:53:41.08#ibcon#read 3, iclass 29, count 2 2006.201.17:53:41.08#ibcon#about to read 4, iclass 29, count 2 2006.201.17:53:41.08#ibcon#read 4, iclass 29, count 2 2006.201.17:53:41.08#ibcon#about to read 5, iclass 29, count 2 2006.201.17:53:41.08#ibcon#read 5, iclass 29, count 2 2006.201.17:53:41.08#ibcon#about to read 6, iclass 29, count 2 2006.201.17:53:41.08#ibcon#read 6, iclass 29, count 2 2006.201.17:53:41.08#ibcon#end of sib2, iclass 29, count 2 2006.201.17:53:41.08#ibcon#*after write, iclass 29, count 2 2006.201.17:53:41.08#ibcon#*before return 0, iclass 29, count 2 2006.201.17:53:41.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:41.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:41.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.17:53:41.08#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:41.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:41.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:41.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:41.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:53:41.20#ibcon#first serial, iclass 29, count 0 2006.201.17:53:41.20#ibcon#enter sib2, iclass 29, count 0 2006.201.17:53:41.20#ibcon#flushed, iclass 29, count 0 2006.201.17:53:41.20#ibcon#about to write, iclass 29, count 0 2006.201.17:53:41.20#ibcon#wrote, iclass 29, count 0 2006.201.17:53:41.20#ibcon#about to read 3, iclass 29, count 0 2006.201.17:53:41.22#ibcon#read 3, iclass 29, count 0 2006.201.17:53:41.22#ibcon#about to read 4, iclass 29, count 0 2006.201.17:53:41.22#ibcon#read 4, iclass 29, count 0 2006.201.17:53:41.22#ibcon#about to read 5, iclass 29, count 0 2006.201.17:53:41.22#ibcon#read 5, iclass 29, count 0 2006.201.17:53:41.22#ibcon#about to read 6, iclass 29, count 0 2006.201.17:53:41.22#ibcon#read 6, iclass 29, count 0 2006.201.17:53:41.22#ibcon#end of sib2, iclass 29, count 0 2006.201.17:53:41.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:53:41.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:53:41.22#ibcon#[25=USB\r\n] 2006.201.17:53:41.22#ibcon#*before write, iclass 29, count 0 2006.201.17:53:41.22#ibcon#enter sib2, iclass 29, count 0 2006.201.17:53:41.22#ibcon#flushed, iclass 29, count 0 2006.201.17:53:41.22#ibcon#about to write, iclass 29, count 0 2006.201.17:53:41.22#ibcon#wrote, iclass 29, count 0 2006.201.17:53:41.22#ibcon#about to read 3, iclass 29, count 0 2006.201.17:53:41.25#ibcon#read 3, iclass 29, count 0 2006.201.17:53:41.25#ibcon#about to read 4, iclass 29, count 0 2006.201.17:53:41.25#ibcon#read 4, iclass 29, count 0 2006.201.17:53:41.25#ibcon#about to read 5, iclass 29, count 0 2006.201.17:53:41.25#ibcon#read 5, iclass 29, count 0 2006.201.17:53:41.25#ibcon#about to read 6, iclass 29, count 0 2006.201.17:53:41.25#ibcon#read 6, iclass 29, count 0 2006.201.17:53:41.25#ibcon#end of sib2, iclass 29, count 0 2006.201.17:53:41.25#ibcon#*after write, iclass 29, count 0 2006.201.17:53:41.25#ibcon#*before return 0, iclass 29, count 0 2006.201.17:53:41.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:41.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:41.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:53:41.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:53:41.25$vck44/valo=8,884.99 2006.201.17:53:41.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.17:53:41.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.17:53:41.25#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:41.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:53:41.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:53:41.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:53:41.25#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:53:41.25#ibcon#first serial, iclass 31, count 0 2006.201.17:53:41.25#ibcon#enter sib2, iclass 31, count 0 2006.201.17:53:41.25#ibcon#flushed, iclass 31, count 0 2006.201.17:53:41.25#ibcon#about to write, iclass 31, count 0 2006.201.17:53:41.25#ibcon#wrote, iclass 31, count 0 2006.201.17:53:41.25#ibcon#about to read 3, iclass 31, count 0 2006.201.17:53:41.27#ibcon#read 3, iclass 31, count 0 2006.201.17:53:41.27#ibcon#about to read 4, iclass 31, count 0 2006.201.17:53:41.27#ibcon#read 4, iclass 31, count 0 2006.201.17:53:41.27#ibcon#about to read 5, iclass 31, count 0 2006.201.17:53:41.27#ibcon#read 5, iclass 31, count 0 2006.201.17:53:41.27#ibcon#about to read 6, iclass 31, count 0 2006.201.17:53:41.27#ibcon#read 6, iclass 31, count 0 2006.201.17:53:41.27#ibcon#end of sib2, iclass 31, count 0 2006.201.17:53:41.27#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:53:41.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:53:41.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.17:53:41.27#ibcon#*before write, iclass 31, count 0 2006.201.17:53:41.27#ibcon#enter sib2, iclass 31, count 0 2006.201.17:53:41.27#ibcon#flushed, iclass 31, count 0 2006.201.17:53:41.27#ibcon#about to write, iclass 31, count 0 2006.201.17:53:41.27#ibcon#wrote, iclass 31, count 0 2006.201.17:53:41.27#ibcon#about to read 3, iclass 31, count 0 2006.201.17:53:41.31#ibcon#read 3, iclass 31, count 0 2006.201.17:53:41.31#ibcon#about to read 4, iclass 31, count 0 2006.201.17:53:41.31#ibcon#read 4, iclass 31, count 0 2006.201.17:53:41.31#ibcon#about to read 5, iclass 31, count 0 2006.201.17:53:41.31#ibcon#read 5, iclass 31, count 0 2006.201.17:53:41.31#ibcon#about to read 6, iclass 31, count 0 2006.201.17:53:41.31#ibcon#read 6, iclass 31, count 0 2006.201.17:53:41.31#ibcon#end of sib2, iclass 31, count 0 2006.201.17:53:41.31#ibcon#*after write, iclass 31, count 0 2006.201.17:53:41.31#ibcon#*before return 0, iclass 31, count 0 2006.201.17:53:41.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:53:41.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:53:41.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:53:41.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:53:41.31$vck44/va=8,4 2006.201.17:53:41.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.17:53:41.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.17:53:41.31#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:41.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:53:41.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:53:41.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:53:41.37#ibcon#enter wrdev, iclass 33, count 2 2006.201.17:53:41.37#ibcon#first serial, iclass 33, count 2 2006.201.17:53:41.37#ibcon#enter sib2, iclass 33, count 2 2006.201.17:53:41.37#ibcon#flushed, iclass 33, count 2 2006.201.17:53:41.37#ibcon#about to write, iclass 33, count 2 2006.201.17:53:41.37#ibcon#wrote, iclass 33, count 2 2006.201.17:53:41.37#ibcon#about to read 3, iclass 33, count 2 2006.201.17:53:41.39#ibcon#read 3, iclass 33, count 2 2006.201.17:53:41.39#ibcon#about to read 4, iclass 33, count 2 2006.201.17:53:41.39#ibcon#read 4, iclass 33, count 2 2006.201.17:53:41.39#ibcon#about to read 5, iclass 33, count 2 2006.201.17:53:41.39#ibcon#read 5, iclass 33, count 2 2006.201.17:53:41.39#ibcon#about to read 6, iclass 33, count 2 2006.201.17:53:41.39#ibcon#read 6, iclass 33, count 2 2006.201.17:53:41.39#ibcon#end of sib2, iclass 33, count 2 2006.201.17:53:41.39#ibcon#*mode == 0, iclass 33, count 2 2006.201.17:53:41.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.17:53:41.39#ibcon#[25=AT08-04\r\n] 2006.201.17:53:41.39#ibcon#*before write, iclass 33, count 2 2006.201.17:53:41.39#ibcon#enter sib2, iclass 33, count 2 2006.201.17:53:41.39#ibcon#flushed, iclass 33, count 2 2006.201.17:53:41.39#ibcon#about to write, iclass 33, count 2 2006.201.17:53:41.39#ibcon#wrote, iclass 33, count 2 2006.201.17:53:41.39#ibcon#about to read 3, iclass 33, count 2 2006.201.17:53:41.42#ibcon#read 3, iclass 33, count 2 2006.201.17:53:41.42#ibcon#about to read 4, iclass 33, count 2 2006.201.17:53:41.42#ibcon#read 4, iclass 33, count 2 2006.201.17:53:41.42#ibcon#about to read 5, iclass 33, count 2 2006.201.17:53:41.42#ibcon#read 5, iclass 33, count 2 2006.201.17:53:41.42#ibcon#about to read 6, iclass 33, count 2 2006.201.17:53:41.42#ibcon#read 6, iclass 33, count 2 2006.201.17:53:41.42#ibcon#end of sib2, iclass 33, count 2 2006.201.17:53:41.42#ibcon#*after write, iclass 33, count 2 2006.201.17:53:41.42#ibcon#*before return 0, iclass 33, count 2 2006.201.17:53:41.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:53:41.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.17:53:41.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.17:53:41.42#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:41.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:53:41.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:53:41.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:53:41.54#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:53:41.54#ibcon#first serial, iclass 33, count 0 2006.201.17:53:41.54#ibcon#enter sib2, iclass 33, count 0 2006.201.17:53:41.54#ibcon#flushed, iclass 33, count 0 2006.201.17:53:41.54#ibcon#about to write, iclass 33, count 0 2006.201.17:53:41.54#ibcon#wrote, iclass 33, count 0 2006.201.17:53:41.54#ibcon#about to read 3, iclass 33, count 0 2006.201.17:53:41.56#ibcon#read 3, iclass 33, count 0 2006.201.17:53:41.56#ibcon#about to read 4, iclass 33, count 0 2006.201.17:53:41.56#ibcon#read 4, iclass 33, count 0 2006.201.17:53:41.56#ibcon#about to read 5, iclass 33, count 0 2006.201.17:53:41.56#ibcon#read 5, iclass 33, count 0 2006.201.17:53:41.56#ibcon#about to read 6, iclass 33, count 0 2006.201.17:53:41.56#ibcon#read 6, iclass 33, count 0 2006.201.17:53:41.56#ibcon#end of sib2, iclass 33, count 0 2006.201.17:53:41.56#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:53:41.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:53:41.56#ibcon#[25=USB\r\n] 2006.201.17:53:41.56#ibcon#*before write, iclass 33, count 0 2006.201.17:53:41.56#ibcon#enter sib2, iclass 33, count 0 2006.201.17:53:41.56#ibcon#flushed, iclass 33, count 0 2006.201.17:53:41.56#ibcon#about to write, iclass 33, count 0 2006.201.17:53:41.56#ibcon#wrote, iclass 33, count 0 2006.201.17:53:41.56#ibcon#about to read 3, iclass 33, count 0 2006.201.17:53:41.59#ibcon#read 3, iclass 33, count 0 2006.201.17:53:41.59#ibcon#about to read 4, iclass 33, count 0 2006.201.17:53:41.59#ibcon#read 4, iclass 33, count 0 2006.201.17:53:41.59#ibcon#about to read 5, iclass 33, count 0 2006.201.17:53:41.59#ibcon#read 5, iclass 33, count 0 2006.201.17:53:41.59#ibcon#about to read 6, iclass 33, count 0 2006.201.17:53:41.59#ibcon#read 6, iclass 33, count 0 2006.201.17:53:41.59#ibcon#end of sib2, iclass 33, count 0 2006.201.17:53:41.59#ibcon#*after write, iclass 33, count 0 2006.201.17:53:41.59#ibcon#*before return 0, iclass 33, count 0 2006.201.17:53:41.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:53:41.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.17:53:41.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:53:41.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:53:41.59$vck44/vblo=1,629.99 2006.201.17:53:41.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.17:53:41.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.17:53:41.59#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:41.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:41.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:41.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:41.59#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:53:41.59#ibcon#first serial, iclass 35, count 0 2006.201.17:53:41.59#ibcon#enter sib2, iclass 35, count 0 2006.201.17:53:41.59#ibcon#flushed, iclass 35, count 0 2006.201.17:53:41.59#ibcon#about to write, iclass 35, count 0 2006.201.17:53:41.59#ibcon#wrote, iclass 35, count 0 2006.201.17:53:41.59#ibcon#about to read 3, iclass 35, count 0 2006.201.17:53:41.61#ibcon#read 3, iclass 35, count 0 2006.201.17:53:41.61#ibcon#about to read 4, iclass 35, count 0 2006.201.17:53:41.61#ibcon#read 4, iclass 35, count 0 2006.201.17:53:41.61#ibcon#about to read 5, iclass 35, count 0 2006.201.17:53:41.61#ibcon#read 5, iclass 35, count 0 2006.201.17:53:41.61#ibcon#about to read 6, iclass 35, count 0 2006.201.17:53:41.61#ibcon#read 6, iclass 35, count 0 2006.201.17:53:41.61#ibcon#end of sib2, iclass 35, count 0 2006.201.17:53:41.61#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:53:41.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:53:41.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.17:53:41.61#ibcon#*before write, iclass 35, count 0 2006.201.17:53:41.61#ibcon#enter sib2, iclass 35, count 0 2006.201.17:53:41.61#ibcon#flushed, iclass 35, count 0 2006.201.17:53:41.61#ibcon#about to write, iclass 35, count 0 2006.201.17:53:41.61#ibcon#wrote, iclass 35, count 0 2006.201.17:53:41.61#ibcon#about to read 3, iclass 35, count 0 2006.201.17:53:41.65#ibcon#read 3, iclass 35, count 0 2006.201.17:53:41.65#ibcon#about to read 4, iclass 35, count 0 2006.201.17:53:41.65#ibcon#read 4, iclass 35, count 0 2006.201.17:53:41.65#ibcon#about to read 5, iclass 35, count 0 2006.201.17:53:41.65#ibcon#read 5, iclass 35, count 0 2006.201.17:53:41.65#ibcon#about to read 6, iclass 35, count 0 2006.201.17:53:41.65#ibcon#read 6, iclass 35, count 0 2006.201.17:53:41.65#ibcon#end of sib2, iclass 35, count 0 2006.201.17:53:41.65#ibcon#*after write, iclass 35, count 0 2006.201.17:53:41.65#ibcon#*before return 0, iclass 35, count 0 2006.201.17:53:41.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:41.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:41.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:53:41.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:53:41.65$vck44/vb=1,4 2006.201.17:53:41.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.17:53:41.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.17:53:41.65#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:41.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:53:41.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:53:41.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:53:41.65#ibcon#enter wrdev, iclass 37, count 2 2006.201.17:53:41.65#ibcon#first serial, iclass 37, count 2 2006.201.17:53:41.65#ibcon#enter sib2, iclass 37, count 2 2006.201.17:53:41.65#ibcon#flushed, iclass 37, count 2 2006.201.17:53:41.65#ibcon#about to write, iclass 37, count 2 2006.201.17:53:41.65#ibcon#wrote, iclass 37, count 2 2006.201.17:53:41.65#ibcon#about to read 3, iclass 37, count 2 2006.201.17:53:41.67#ibcon#read 3, iclass 37, count 2 2006.201.17:53:41.67#ibcon#about to read 4, iclass 37, count 2 2006.201.17:53:41.67#ibcon#read 4, iclass 37, count 2 2006.201.17:53:41.67#ibcon#about to read 5, iclass 37, count 2 2006.201.17:53:41.67#ibcon#read 5, iclass 37, count 2 2006.201.17:53:41.67#ibcon#about to read 6, iclass 37, count 2 2006.201.17:53:41.67#ibcon#read 6, iclass 37, count 2 2006.201.17:53:41.67#ibcon#end of sib2, iclass 37, count 2 2006.201.17:53:41.67#ibcon#*mode == 0, iclass 37, count 2 2006.201.17:53:41.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.17:53:41.67#ibcon#[27=AT01-04\r\n] 2006.201.17:53:41.67#ibcon#*before write, iclass 37, count 2 2006.201.17:53:41.67#ibcon#enter sib2, iclass 37, count 2 2006.201.17:53:41.67#ibcon#flushed, iclass 37, count 2 2006.201.17:53:41.67#ibcon#about to write, iclass 37, count 2 2006.201.17:53:41.67#ibcon#wrote, iclass 37, count 2 2006.201.17:53:41.67#ibcon#about to read 3, iclass 37, count 2 2006.201.17:53:41.70#ibcon#read 3, iclass 37, count 2 2006.201.17:53:41.70#ibcon#about to read 4, iclass 37, count 2 2006.201.17:53:41.70#ibcon#read 4, iclass 37, count 2 2006.201.17:53:41.70#ibcon#about to read 5, iclass 37, count 2 2006.201.17:53:41.70#ibcon#read 5, iclass 37, count 2 2006.201.17:53:41.70#ibcon#about to read 6, iclass 37, count 2 2006.201.17:53:41.70#ibcon#read 6, iclass 37, count 2 2006.201.17:53:41.70#ibcon#end of sib2, iclass 37, count 2 2006.201.17:53:41.70#ibcon#*after write, iclass 37, count 2 2006.201.17:53:41.70#ibcon#*before return 0, iclass 37, count 2 2006.201.17:53:41.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:53:41.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.17:53:41.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.17:53:41.70#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:41.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:53:41.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:53:41.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:53:41.82#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:53:41.82#ibcon#first serial, iclass 37, count 0 2006.201.17:53:41.82#ibcon#enter sib2, iclass 37, count 0 2006.201.17:53:41.82#ibcon#flushed, iclass 37, count 0 2006.201.17:53:41.82#ibcon#about to write, iclass 37, count 0 2006.201.17:53:41.82#ibcon#wrote, iclass 37, count 0 2006.201.17:53:41.82#ibcon#about to read 3, iclass 37, count 0 2006.201.17:53:41.84#ibcon#read 3, iclass 37, count 0 2006.201.17:53:41.84#ibcon#about to read 4, iclass 37, count 0 2006.201.17:53:41.84#ibcon#read 4, iclass 37, count 0 2006.201.17:53:41.84#ibcon#about to read 5, iclass 37, count 0 2006.201.17:53:41.84#ibcon#read 5, iclass 37, count 0 2006.201.17:53:41.84#ibcon#about to read 6, iclass 37, count 0 2006.201.17:53:41.84#ibcon#read 6, iclass 37, count 0 2006.201.17:53:41.84#ibcon#end of sib2, iclass 37, count 0 2006.201.17:53:41.84#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:53:41.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:53:41.84#ibcon#[27=USB\r\n] 2006.201.17:53:41.84#ibcon#*before write, iclass 37, count 0 2006.201.17:53:41.84#ibcon#enter sib2, iclass 37, count 0 2006.201.17:53:41.84#ibcon#flushed, iclass 37, count 0 2006.201.17:53:41.84#ibcon#about to write, iclass 37, count 0 2006.201.17:53:41.84#ibcon#wrote, iclass 37, count 0 2006.201.17:53:41.84#ibcon#about to read 3, iclass 37, count 0 2006.201.17:53:41.87#ibcon#read 3, iclass 37, count 0 2006.201.17:53:41.87#ibcon#about to read 4, iclass 37, count 0 2006.201.17:53:41.87#ibcon#read 4, iclass 37, count 0 2006.201.17:53:41.87#ibcon#about to read 5, iclass 37, count 0 2006.201.17:53:41.87#ibcon#read 5, iclass 37, count 0 2006.201.17:53:41.87#ibcon#about to read 6, iclass 37, count 0 2006.201.17:53:41.87#ibcon#read 6, iclass 37, count 0 2006.201.17:53:41.87#ibcon#end of sib2, iclass 37, count 0 2006.201.17:53:41.87#ibcon#*after write, iclass 37, count 0 2006.201.17:53:41.87#ibcon#*before return 0, iclass 37, count 0 2006.201.17:53:41.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:53:41.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.17:53:41.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:53:41.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:53:41.87$vck44/vblo=2,634.99 2006.201.17:53:41.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.17:53:41.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.17:53:41.87#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:41.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:41.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:41.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:41.87#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:53:41.87#ibcon#first serial, iclass 39, count 0 2006.201.17:53:41.87#ibcon#enter sib2, iclass 39, count 0 2006.201.17:53:41.87#ibcon#flushed, iclass 39, count 0 2006.201.17:53:41.87#ibcon#about to write, iclass 39, count 0 2006.201.17:53:41.87#ibcon#wrote, iclass 39, count 0 2006.201.17:53:41.87#ibcon#about to read 3, iclass 39, count 0 2006.201.17:53:41.89#ibcon#read 3, iclass 39, count 0 2006.201.17:53:41.89#ibcon#about to read 4, iclass 39, count 0 2006.201.17:53:41.89#ibcon#read 4, iclass 39, count 0 2006.201.17:53:41.89#ibcon#about to read 5, iclass 39, count 0 2006.201.17:53:41.89#ibcon#read 5, iclass 39, count 0 2006.201.17:53:41.89#ibcon#about to read 6, iclass 39, count 0 2006.201.17:53:41.89#ibcon#read 6, iclass 39, count 0 2006.201.17:53:41.89#ibcon#end of sib2, iclass 39, count 0 2006.201.17:53:41.89#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:53:41.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:53:41.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.17:53:41.89#ibcon#*before write, iclass 39, count 0 2006.201.17:53:41.89#ibcon#enter sib2, iclass 39, count 0 2006.201.17:53:41.89#ibcon#flushed, iclass 39, count 0 2006.201.17:53:41.89#ibcon#about to write, iclass 39, count 0 2006.201.17:53:41.89#ibcon#wrote, iclass 39, count 0 2006.201.17:53:41.89#ibcon#about to read 3, iclass 39, count 0 2006.201.17:53:41.93#ibcon#read 3, iclass 39, count 0 2006.201.17:53:41.93#ibcon#about to read 4, iclass 39, count 0 2006.201.17:53:41.93#ibcon#read 4, iclass 39, count 0 2006.201.17:53:41.93#ibcon#about to read 5, iclass 39, count 0 2006.201.17:53:41.93#ibcon#read 5, iclass 39, count 0 2006.201.17:53:41.93#ibcon#about to read 6, iclass 39, count 0 2006.201.17:53:41.93#ibcon#read 6, iclass 39, count 0 2006.201.17:53:41.93#ibcon#end of sib2, iclass 39, count 0 2006.201.17:53:41.93#ibcon#*after write, iclass 39, count 0 2006.201.17:53:41.93#ibcon#*before return 0, iclass 39, count 0 2006.201.17:53:41.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:41.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.17:53:41.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:53:41.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:53:41.93$vck44/vb=2,5 2006.201.17:53:41.93#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.17:53:41.93#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.17:53:41.93#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:41.93#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:41.99#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:41.99#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:41.99#ibcon#enter wrdev, iclass 2, count 2 2006.201.17:53:41.99#ibcon#first serial, iclass 2, count 2 2006.201.17:53:41.99#ibcon#enter sib2, iclass 2, count 2 2006.201.17:53:41.99#ibcon#flushed, iclass 2, count 2 2006.201.17:53:41.99#ibcon#about to write, iclass 2, count 2 2006.201.17:53:41.99#ibcon#wrote, iclass 2, count 2 2006.201.17:53:41.99#ibcon#about to read 3, iclass 2, count 2 2006.201.17:53:42.01#ibcon#read 3, iclass 2, count 2 2006.201.17:53:42.01#ibcon#about to read 4, iclass 2, count 2 2006.201.17:53:42.01#ibcon#read 4, iclass 2, count 2 2006.201.17:53:42.01#ibcon#about to read 5, iclass 2, count 2 2006.201.17:53:42.01#ibcon#read 5, iclass 2, count 2 2006.201.17:53:42.01#ibcon#about to read 6, iclass 2, count 2 2006.201.17:53:42.01#ibcon#read 6, iclass 2, count 2 2006.201.17:53:42.01#ibcon#end of sib2, iclass 2, count 2 2006.201.17:53:42.01#ibcon#*mode == 0, iclass 2, count 2 2006.201.17:53:42.01#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.17:53:42.01#ibcon#[27=AT02-05\r\n] 2006.201.17:53:42.01#ibcon#*before write, iclass 2, count 2 2006.201.17:53:42.01#ibcon#enter sib2, iclass 2, count 2 2006.201.17:53:42.01#ibcon#flushed, iclass 2, count 2 2006.201.17:53:42.01#ibcon#about to write, iclass 2, count 2 2006.201.17:53:42.01#ibcon#wrote, iclass 2, count 2 2006.201.17:53:42.01#ibcon#about to read 3, iclass 2, count 2 2006.201.17:53:42.04#ibcon#read 3, iclass 2, count 2 2006.201.17:53:42.04#ibcon#about to read 4, iclass 2, count 2 2006.201.17:53:42.04#ibcon#read 4, iclass 2, count 2 2006.201.17:53:42.04#ibcon#about to read 5, iclass 2, count 2 2006.201.17:53:42.04#ibcon#read 5, iclass 2, count 2 2006.201.17:53:42.04#ibcon#about to read 6, iclass 2, count 2 2006.201.17:53:42.04#ibcon#read 6, iclass 2, count 2 2006.201.17:53:42.04#ibcon#end of sib2, iclass 2, count 2 2006.201.17:53:42.04#ibcon#*after write, iclass 2, count 2 2006.201.17:53:42.04#ibcon#*before return 0, iclass 2, count 2 2006.201.17:53:42.04#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:42.04#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.17:53:42.04#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.17:53:42.04#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:42.04#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:42.16#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:42.16#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:42.16#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:53:42.16#ibcon#first serial, iclass 2, count 0 2006.201.17:53:42.16#ibcon#enter sib2, iclass 2, count 0 2006.201.17:53:42.16#ibcon#flushed, iclass 2, count 0 2006.201.17:53:42.16#ibcon#about to write, iclass 2, count 0 2006.201.17:53:42.16#ibcon#wrote, iclass 2, count 0 2006.201.17:53:42.16#ibcon#about to read 3, iclass 2, count 0 2006.201.17:53:42.18#ibcon#read 3, iclass 2, count 0 2006.201.17:53:42.18#ibcon#about to read 4, iclass 2, count 0 2006.201.17:53:42.18#ibcon#read 4, iclass 2, count 0 2006.201.17:53:42.18#ibcon#about to read 5, iclass 2, count 0 2006.201.17:53:42.18#ibcon#read 5, iclass 2, count 0 2006.201.17:53:42.18#ibcon#about to read 6, iclass 2, count 0 2006.201.17:53:42.18#ibcon#read 6, iclass 2, count 0 2006.201.17:53:42.18#ibcon#end of sib2, iclass 2, count 0 2006.201.17:53:42.18#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:53:42.18#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:53:42.18#ibcon#[27=USB\r\n] 2006.201.17:53:42.18#ibcon#*before write, iclass 2, count 0 2006.201.17:53:42.18#ibcon#enter sib2, iclass 2, count 0 2006.201.17:53:42.18#ibcon#flushed, iclass 2, count 0 2006.201.17:53:42.18#ibcon#about to write, iclass 2, count 0 2006.201.17:53:42.18#ibcon#wrote, iclass 2, count 0 2006.201.17:53:42.18#ibcon#about to read 3, iclass 2, count 0 2006.201.17:53:42.21#ibcon#read 3, iclass 2, count 0 2006.201.17:53:42.21#ibcon#about to read 4, iclass 2, count 0 2006.201.17:53:42.21#ibcon#read 4, iclass 2, count 0 2006.201.17:53:42.21#ibcon#about to read 5, iclass 2, count 0 2006.201.17:53:42.21#ibcon#read 5, iclass 2, count 0 2006.201.17:53:42.21#ibcon#about to read 6, iclass 2, count 0 2006.201.17:53:42.21#ibcon#read 6, iclass 2, count 0 2006.201.17:53:42.21#ibcon#end of sib2, iclass 2, count 0 2006.201.17:53:42.21#ibcon#*after write, iclass 2, count 0 2006.201.17:53:42.21#ibcon#*before return 0, iclass 2, count 0 2006.201.17:53:42.21#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:42.21#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.17:53:42.21#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:53:42.21#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:53:42.21$vck44/vblo=3,649.99 2006.201.17:53:42.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.17:53:42.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.17:53:42.21#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:42.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:42.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:42.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:42.21#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:53:42.21#ibcon#first serial, iclass 5, count 0 2006.201.17:53:42.21#ibcon#enter sib2, iclass 5, count 0 2006.201.17:53:42.21#ibcon#flushed, iclass 5, count 0 2006.201.17:53:42.21#ibcon#about to write, iclass 5, count 0 2006.201.17:53:42.21#ibcon#wrote, iclass 5, count 0 2006.201.17:53:42.21#ibcon#about to read 3, iclass 5, count 0 2006.201.17:53:42.23#ibcon#read 3, iclass 5, count 0 2006.201.17:53:42.23#ibcon#about to read 4, iclass 5, count 0 2006.201.17:53:42.23#ibcon#read 4, iclass 5, count 0 2006.201.17:53:42.23#ibcon#about to read 5, iclass 5, count 0 2006.201.17:53:42.23#ibcon#read 5, iclass 5, count 0 2006.201.17:53:42.23#ibcon#about to read 6, iclass 5, count 0 2006.201.17:53:42.23#ibcon#read 6, iclass 5, count 0 2006.201.17:53:42.23#ibcon#end of sib2, iclass 5, count 0 2006.201.17:53:42.23#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:53:42.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:53:42.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.17:53:42.23#ibcon#*before write, iclass 5, count 0 2006.201.17:53:42.23#ibcon#enter sib2, iclass 5, count 0 2006.201.17:53:42.23#ibcon#flushed, iclass 5, count 0 2006.201.17:53:42.23#ibcon#about to write, iclass 5, count 0 2006.201.17:53:42.23#ibcon#wrote, iclass 5, count 0 2006.201.17:53:42.23#ibcon#about to read 3, iclass 5, count 0 2006.201.17:53:42.27#ibcon#read 3, iclass 5, count 0 2006.201.17:53:42.27#ibcon#about to read 4, iclass 5, count 0 2006.201.17:53:42.27#ibcon#read 4, iclass 5, count 0 2006.201.17:53:42.27#ibcon#about to read 5, iclass 5, count 0 2006.201.17:53:42.27#ibcon#read 5, iclass 5, count 0 2006.201.17:53:42.27#ibcon#about to read 6, iclass 5, count 0 2006.201.17:53:42.27#ibcon#read 6, iclass 5, count 0 2006.201.17:53:42.27#ibcon#end of sib2, iclass 5, count 0 2006.201.17:53:42.27#ibcon#*after write, iclass 5, count 0 2006.201.17:53:42.27#ibcon#*before return 0, iclass 5, count 0 2006.201.17:53:42.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:42.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.17:53:42.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:53:42.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:53:42.27$vck44/vb=3,4 2006.201.17:53:42.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.17:53:42.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.17:53:42.27#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:42.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:42.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:42.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:42.33#ibcon#enter wrdev, iclass 7, count 2 2006.201.17:53:42.33#ibcon#first serial, iclass 7, count 2 2006.201.17:53:42.33#ibcon#enter sib2, iclass 7, count 2 2006.201.17:53:42.33#ibcon#flushed, iclass 7, count 2 2006.201.17:53:42.33#ibcon#about to write, iclass 7, count 2 2006.201.17:53:42.33#ibcon#wrote, iclass 7, count 2 2006.201.17:53:42.33#ibcon#about to read 3, iclass 7, count 2 2006.201.17:53:42.35#ibcon#read 3, iclass 7, count 2 2006.201.17:53:42.35#ibcon#about to read 4, iclass 7, count 2 2006.201.17:53:42.35#ibcon#read 4, iclass 7, count 2 2006.201.17:53:42.35#ibcon#about to read 5, iclass 7, count 2 2006.201.17:53:42.35#ibcon#read 5, iclass 7, count 2 2006.201.17:53:42.35#ibcon#about to read 6, iclass 7, count 2 2006.201.17:53:42.35#ibcon#read 6, iclass 7, count 2 2006.201.17:53:42.35#ibcon#end of sib2, iclass 7, count 2 2006.201.17:53:42.35#ibcon#*mode == 0, iclass 7, count 2 2006.201.17:53:42.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.17:53:42.35#ibcon#[27=AT03-04\r\n] 2006.201.17:53:42.35#ibcon#*before write, iclass 7, count 2 2006.201.17:53:42.35#ibcon#enter sib2, iclass 7, count 2 2006.201.17:53:42.35#ibcon#flushed, iclass 7, count 2 2006.201.17:53:42.35#ibcon#about to write, iclass 7, count 2 2006.201.17:53:42.35#ibcon#wrote, iclass 7, count 2 2006.201.17:53:42.35#ibcon#about to read 3, iclass 7, count 2 2006.201.17:53:42.38#ibcon#read 3, iclass 7, count 2 2006.201.17:53:42.38#ibcon#about to read 4, iclass 7, count 2 2006.201.17:53:42.38#ibcon#read 4, iclass 7, count 2 2006.201.17:53:42.38#ibcon#about to read 5, iclass 7, count 2 2006.201.17:53:42.38#ibcon#read 5, iclass 7, count 2 2006.201.17:53:42.38#ibcon#about to read 6, iclass 7, count 2 2006.201.17:53:42.38#ibcon#read 6, iclass 7, count 2 2006.201.17:53:42.38#ibcon#end of sib2, iclass 7, count 2 2006.201.17:53:42.38#ibcon#*after write, iclass 7, count 2 2006.201.17:53:42.38#ibcon#*before return 0, iclass 7, count 2 2006.201.17:53:42.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:42.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.17:53:42.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.17:53:42.38#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:42.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:42.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:42.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:42.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:53:42.50#ibcon#first serial, iclass 7, count 0 2006.201.17:53:42.50#ibcon#enter sib2, iclass 7, count 0 2006.201.17:53:42.50#ibcon#flushed, iclass 7, count 0 2006.201.17:53:42.50#ibcon#about to write, iclass 7, count 0 2006.201.17:53:42.50#ibcon#wrote, iclass 7, count 0 2006.201.17:53:42.50#ibcon#about to read 3, iclass 7, count 0 2006.201.17:53:42.52#ibcon#read 3, iclass 7, count 0 2006.201.17:53:42.52#ibcon#about to read 4, iclass 7, count 0 2006.201.17:53:42.52#ibcon#read 4, iclass 7, count 0 2006.201.17:53:42.52#ibcon#about to read 5, iclass 7, count 0 2006.201.17:53:42.52#ibcon#read 5, iclass 7, count 0 2006.201.17:53:42.52#ibcon#about to read 6, iclass 7, count 0 2006.201.17:53:42.52#ibcon#read 6, iclass 7, count 0 2006.201.17:53:42.52#ibcon#end of sib2, iclass 7, count 0 2006.201.17:53:42.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:53:42.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:53:42.52#ibcon#[27=USB\r\n] 2006.201.17:53:42.52#ibcon#*before write, iclass 7, count 0 2006.201.17:53:42.52#ibcon#enter sib2, iclass 7, count 0 2006.201.17:53:42.52#ibcon#flushed, iclass 7, count 0 2006.201.17:53:42.52#ibcon#about to write, iclass 7, count 0 2006.201.17:53:42.52#ibcon#wrote, iclass 7, count 0 2006.201.17:53:42.52#ibcon#about to read 3, iclass 7, count 0 2006.201.17:53:42.55#ibcon#read 3, iclass 7, count 0 2006.201.17:53:42.55#ibcon#about to read 4, iclass 7, count 0 2006.201.17:53:42.55#ibcon#read 4, iclass 7, count 0 2006.201.17:53:42.55#ibcon#about to read 5, iclass 7, count 0 2006.201.17:53:42.55#ibcon#read 5, iclass 7, count 0 2006.201.17:53:42.55#ibcon#about to read 6, iclass 7, count 0 2006.201.17:53:42.55#ibcon#read 6, iclass 7, count 0 2006.201.17:53:42.55#ibcon#end of sib2, iclass 7, count 0 2006.201.17:53:42.55#ibcon#*after write, iclass 7, count 0 2006.201.17:53:42.55#ibcon#*before return 0, iclass 7, count 0 2006.201.17:53:42.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:42.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.17:53:42.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:53:42.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:53:42.55$vck44/vblo=4,679.99 2006.201.17:53:42.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.17:53:42.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.17:53:42.55#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:42.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:42.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:42.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:42.55#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:53:42.55#ibcon#first serial, iclass 11, count 0 2006.201.17:53:42.55#ibcon#enter sib2, iclass 11, count 0 2006.201.17:53:42.55#ibcon#flushed, iclass 11, count 0 2006.201.17:53:42.55#ibcon#about to write, iclass 11, count 0 2006.201.17:53:42.55#ibcon#wrote, iclass 11, count 0 2006.201.17:53:42.55#ibcon#about to read 3, iclass 11, count 0 2006.201.17:53:42.57#ibcon#read 3, iclass 11, count 0 2006.201.17:53:42.57#ibcon#about to read 4, iclass 11, count 0 2006.201.17:53:42.57#ibcon#read 4, iclass 11, count 0 2006.201.17:53:42.57#ibcon#about to read 5, iclass 11, count 0 2006.201.17:53:42.57#ibcon#read 5, iclass 11, count 0 2006.201.17:53:42.57#ibcon#about to read 6, iclass 11, count 0 2006.201.17:53:42.57#ibcon#read 6, iclass 11, count 0 2006.201.17:53:42.57#ibcon#end of sib2, iclass 11, count 0 2006.201.17:53:42.57#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:53:42.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:53:42.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.17:53:42.57#ibcon#*before write, iclass 11, count 0 2006.201.17:53:42.57#ibcon#enter sib2, iclass 11, count 0 2006.201.17:53:42.57#ibcon#flushed, iclass 11, count 0 2006.201.17:53:42.57#ibcon#about to write, iclass 11, count 0 2006.201.17:53:42.57#ibcon#wrote, iclass 11, count 0 2006.201.17:53:42.57#ibcon#about to read 3, iclass 11, count 0 2006.201.17:53:42.61#ibcon#read 3, iclass 11, count 0 2006.201.17:53:42.61#ibcon#about to read 4, iclass 11, count 0 2006.201.17:53:42.61#ibcon#read 4, iclass 11, count 0 2006.201.17:53:42.61#ibcon#about to read 5, iclass 11, count 0 2006.201.17:53:42.61#ibcon#read 5, iclass 11, count 0 2006.201.17:53:42.61#ibcon#about to read 6, iclass 11, count 0 2006.201.17:53:42.61#ibcon#read 6, iclass 11, count 0 2006.201.17:53:42.61#ibcon#end of sib2, iclass 11, count 0 2006.201.17:53:42.61#ibcon#*after write, iclass 11, count 0 2006.201.17:53:42.61#ibcon#*before return 0, iclass 11, count 0 2006.201.17:53:42.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:42.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.17:53:42.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:53:42.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:53:42.61$vck44/vb=4,5 2006.201.17:53:42.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.17:53:42.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.17:53:42.61#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:42.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:42.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:42.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:42.67#ibcon#enter wrdev, iclass 13, count 2 2006.201.17:53:42.67#ibcon#first serial, iclass 13, count 2 2006.201.17:53:42.67#ibcon#enter sib2, iclass 13, count 2 2006.201.17:53:42.67#ibcon#flushed, iclass 13, count 2 2006.201.17:53:42.67#ibcon#about to write, iclass 13, count 2 2006.201.17:53:42.67#ibcon#wrote, iclass 13, count 2 2006.201.17:53:42.67#ibcon#about to read 3, iclass 13, count 2 2006.201.17:53:42.69#ibcon#read 3, iclass 13, count 2 2006.201.17:53:42.69#ibcon#about to read 4, iclass 13, count 2 2006.201.17:53:42.69#ibcon#read 4, iclass 13, count 2 2006.201.17:53:42.69#ibcon#about to read 5, iclass 13, count 2 2006.201.17:53:42.69#ibcon#read 5, iclass 13, count 2 2006.201.17:53:42.69#ibcon#about to read 6, iclass 13, count 2 2006.201.17:53:42.69#ibcon#read 6, iclass 13, count 2 2006.201.17:53:42.69#ibcon#end of sib2, iclass 13, count 2 2006.201.17:53:42.69#ibcon#*mode == 0, iclass 13, count 2 2006.201.17:53:42.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.17:53:42.69#ibcon#[27=AT04-05\r\n] 2006.201.17:53:42.69#ibcon#*before write, iclass 13, count 2 2006.201.17:53:42.69#ibcon#enter sib2, iclass 13, count 2 2006.201.17:53:42.69#ibcon#flushed, iclass 13, count 2 2006.201.17:53:42.69#ibcon#about to write, iclass 13, count 2 2006.201.17:53:42.69#ibcon#wrote, iclass 13, count 2 2006.201.17:53:42.69#ibcon#about to read 3, iclass 13, count 2 2006.201.17:53:42.72#ibcon#read 3, iclass 13, count 2 2006.201.17:53:42.72#ibcon#about to read 4, iclass 13, count 2 2006.201.17:53:42.72#ibcon#read 4, iclass 13, count 2 2006.201.17:53:42.72#ibcon#about to read 5, iclass 13, count 2 2006.201.17:53:42.72#ibcon#read 5, iclass 13, count 2 2006.201.17:53:42.72#ibcon#about to read 6, iclass 13, count 2 2006.201.17:53:42.72#ibcon#read 6, iclass 13, count 2 2006.201.17:53:42.72#ibcon#end of sib2, iclass 13, count 2 2006.201.17:53:42.72#ibcon#*after write, iclass 13, count 2 2006.201.17:53:42.72#ibcon#*before return 0, iclass 13, count 2 2006.201.17:53:42.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:42.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.17:53:42.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.17:53:42.72#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:42.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:42.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:42.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:42.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:53:42.84#ibcon#first serial, iclass 13, count 0 2006.201.17:53:42.84#ibcon#enter sib2, iclass 13, count 0 2006.201.17:53:42.84#ibcon#flushed, iclass 13, count 0 2006.201.17:53:42.84#ibcon#about to write, iclass 13, count 0 2006.201.17:53:42.84#ibcon#wrote, iclass 13, count 0 2006.201.17:53:42.84#ibcon#about to read 3, iclass 13, count 0 2006.201.17:53:42.86#ibcon#read 3, iclass 13, count 0 2006.201.17:53:42.86#ibcon#about to read 4, iclass 13, count 0 2006.201.17:53:42.86#ibcon#read 4, iclass 13, count 0 2006.201.17:53:42.86#ibcon#about to read 5, iclass 13, count 0 2006.201.17:53:42.86#ibcon#read 5, iclass 13, count 0 2006.201.17:53:42.86#ibcon#about to read 6, iclass 13, count 0 2006.201.17:53:42.86#ibcon#read 6, iclass 13, count 0 2006.201.17:53:42.86#ibcon#end of sib2, iclass 13, count 0 2006.201.17:53:42.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:53:42.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:53:42.86#ibcon#[27=USB\r\n] 2006.201.17:53:42.86#ibcon#*before write, iclass 13, count 0 2006.201.17:53:42.86#ibcon#enter sib2, iclass 13, count 0 2006.201.17:53:42.86#ibcon#flushed, iclass 13, count 0 2006.201.17:53:42.86#ibcon#about to write, iclass 13, count 0 2006.201.17:53:42.86#ibcon#wrote, iclass 13, count 0 2006.201.17:53:42.86#ibcon#about to read 3, iclass 13, count 0 2006.201.17:53:42.89#ibcon#read 3, iclass 13, count 0 2006.201.17:53:42.89#ibcon#about to read 4, iclass 13, count 0 2006.201.17:53:42.89#ibcon#read 4, iclass 13, count 0 2006.201.17:53:42.89#ibcon#about to read 5, iclass 13, count 0 2006.201.17:53:42.89#ibcon#read 5, iclass 13, count 0 2006.201.17:53:42.89#ibcon#about to read 6, iclass 13, count 0 2006.201.17:53:42.89#ibcon#read 6, iclass 13, count 0 2006.201.17:53:42.89#ibcon#end of sib2, iclass 13, count 0 2006.201.17:53:42.89#ibcon#*after write, iclass 13, count 0 2006.201.17:53:42.89#ibcon#*before return 0, iclass 13, count 0 2006.201.17:53:42.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:42.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.17:53:42.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:53:42.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:53:42.89$vck44/vblo=5,709.99 2006.201.17:53:42.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.17:53:42.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.17:53:42.89#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:42.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:42.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:42.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:42.89#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:53:42.89#ibcon#first serial, iclass 15, count 0 2006.201.17:53:42.89#ibcon#enter sib2, iclass 15, count 0 2006.201.17:53:42.89#ibcon#flushed, iclass 15, count 0 2006.201.17:53:42.89#ibcon#about to write, iclass 15, count 0 2006.201.17:53:42.89#ibcon#wrote, iclass 15, count 0 2006.201.17:53:42.89#ibcon#about to read 3, iclass 15, count 0 2006.201.17:53:42.91#ibcon#read 3, iclass 15, count 0 2006.201.17:53:42.91#ibcon#about to read 4, iclass 15, count 0 2006.201.17:53:42.91#ibcon#read 4, iclass 15, count 0 2006.201.17:53:42.91#ibcon#about to read 5, iclass 15, count 0 2006.201.17:53:42.91#ibcon#read 5, iclass 15, count 0 2006.201.17:53:42.91#ibcon#about to read 6, iclass 15, count 0 2006.201.17:53:42.91#ibcon#read 6, iclass 15, count 0 2006.201.17:53:42.91#ibcon#end of sib2, iclass 15, count 0 2006.201.17:53:42.91#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:53:42.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:53:42.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.17:53:42.91#ibcon#*before write, iclass 15, count 0 2006.201.17:53:42.91#ibcon#enter sib2, iclass 15, count 0 2006.201.17:53:42.91#ibcon#flushed, iclass 15, count 0 2006.201.17:53:42.91#ibcon#about to write, iclass 15, count 0 2006.201.17:53:42.91#ibcon#wrote, iclass 15, count 0 2006.201.17:53:42.91#ibcon#about to read 3, iclass 15, count 0 2006.201.17:53:42.95#ibcon#read 3, iclass 15, count 0 2006.201.17:53:42.95#ibcon#about to read 4, iclass 15, count 0 2006.201.17:53:42.95#ibcon#read 4, iclass 15, count 0 2006.201.17:53:42.95#ibcon#about to read 5, iclass 15, count 0 2006.201.17:53:42.95#ibcon#read 5, iclass 15, count 0 2006.201.17:53:42.95#ibcon#about to read 6, iclass 15, count 0 2006.201.17:53:42.95#ibcon#read 6, iclass 15, count 0 2006.201.17:53:42.95#ibcon#end of sib2, iclass 15, count 0 2006.201.17:53:42.95#ibcon#*after write, iclass 15, count 0 2006.201.17:53:42.95#ibcon#*before return 0, iclass 15, count 0 2006.201.17:53:42.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:42.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.17:53:42.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:53:42.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:53:42.95$vck44/vb=5,4 2006.201.17:53:42.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.17:53:42.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.17:53:42.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:42.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:43.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:43.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:43.01#ibcon#enter wrdev, iclass 17, count 2 2006.201.17:53:43.01#ibcon#first serial, iclass 17, count 2 2006.201.17:53:43.01#ibcon#enter sib2, iclass 17, count 2 2006.201.17:53:43.01#ibcon#flushed, iclass 17, count 2 2006.201.17:53:43.01#ibcon#about to write, iclass 17, count 2 2006.201.17:53:43.01#ibcon#wrote, iclass 17, count 2 2006.201.17:53:43.01#ibcon#about to read 3, iclass 17, count 2 2006.201.17:53:43.03#ibcon#read 3, iclass 17, count 2 2006.201.17:53:43.03#ibcon#about to read 4, iclass 17, count 2 2006.201.17:53:43.03#ibcon#read 4, iclass 17, count 2 2006.201.17:53:43.03#ibcon#about to read 5, iclass 17, count 2 2006.201.17:53:43.03#ibcon#read 5, iclass 17, count 2 2006.201.17:53:43.03#ibcon#about to read 6, iclass 17, count 2 2006.201.17:53:43.03#ibcon#read 6, iclass 17, count 2 2006.201.17:53:43.03#ibcon#end of sib2, iclass 17, count 2 2006.201.17:53:43.03#ibcon#*mode == 0, iclass 17, count 2 2006.201.17:53:43.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.17:53:43.03#ibcon#[27=AT05-04\r\n] 2006.201.17:53:43.03#ibcon#*before write, iclass 17, count 2 2006.201.17:53:43.03#ibcon#enter sib2, iclass 17, count 2 2006.201.17:53:43.03#ibcon#flushed, iclass 17, count 2 2006.201.17:53:43.03#ibcon#about to write, iclass 17, count 2 2006.201.17:53:43.03#ibcon#wrote, iclass 17, count 2 2006.201.17:53:43.03#ibcon#about to read 3, iclass 17, count 2 2006.201.17:53:43.06#ibcon#read 3, iclass 17, count 2 2006.201.17:53:43.06#ibcon#about to read 4, iclass 17, count 2 2006.201.17:53:43.06#ibcon#read 4, iclass 17, count 2 2006.201.17:53:43.06#ibcon#about to read 5, iclass 17, count 2 2006.201.17:53:43.06#ibcon#read 5, iclass 17, count 2 2006.201.17:53:43.06#ibcon#about to read 6, iclass 17, count 2 2006.201.17:53:43.06#ibcon#read 6, iclass 17, count 2 2006.201.17:53:43.06#ibcon#end of sib2, iclass 17, count 2 2006.201.17:53:43.06#ibcon#*after write, iclass 17, count 2 2006.201.17:53:43.06#ibcon#*before return 0, iclass 17, count 2 2006.201.17:53:43.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:43.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.17:53:43.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.17:53:43.06#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:43.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:43.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:43.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:43.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:53:43.18#ibcon#first serial, iclass 17, count 0 2006.201.17:53:43.18#ibcon#enter sib2, iclass 17, count 0 2006.201.17:53:43.18#ibcon#flushed, iclass 17, count 0 2006.201.17:53:43.18#ibcon#about to write, iclass 17, count 0 2006.201.17:53:43.18#ibcon#wrote, iclass 17, count 0 2006.201.17:53:43.18#ibcon#about to read 3, iclass 17, count 0 2006.201.17:53:43.20#ibcon#read 3, iclass 17, count 0 2006.201.17:53:43.20#ibcon#about to read 4, iclass 17, count 0 2006.201.17:53:43.20#ibcon#read 4, iclass 17, count 0 2006.201.17:53:43.20#ibcon#about to read 5, iclass 17, count 0 2006.201.17:53:43.20#ibcon#read 5, iclass 17, count 0 2006.201.17:53:43.20#ibcon#about to read 6, iclass 17, count 0 2006.201.17:53:43.20#ibcon#read 6, iclass 17, count 0 2006.201.17:53:43.20#ibcon#end of sib2, iclass 17, count 0 2006.201.17:53:43.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:53:43.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:53:43.20#ibcon#[27=USB\r\n] 2006.201.17:53:43.20#ibcon#*before write, iclass 17, count 0 2006.201.17:53:43.20#ibcon#enter sib2, iclass 17, count 0 2006.201.17:53:43.20#ibcon#flushed, iclass 17, count 0 2006.201.17:53:43.20#ibcon#about to write, iclass 17, count 0 2006.201.17:53:43.20#ibcon#wrote, iclass 17, count 0 2006.201.17:53:43.20#ibcon#about to read 3, iclass 17, count 0 2006.201.17:53:43.23#ibcon#read 3, iclass 17, count 0 2006.201.17:53:43.23#ibcon#about to read 4, iclass 17, count 0 2006.201.17:53:43.23#ibcon#read 4, iclass 17, count 0 2006.201.17:53:43.23#ibcon#about to read 5, iclass 17, count 0 2006.201.17:53:43.23#ibcon#read 5, iclass 17, count 0 2006.201.17:53:43.23#ibcon#about to read 6, iclass 17, count 0 2006.201.17:53:43.23#ibcon#read 6, iclass 17, count 0 2006.201.17:53:43.23#ibcon#end of sib2, iclass 17, count 0 2006.201.17:53:43.23#ibcon#*after write, iclass 17, count 0 2006.201.17:53:43.23#ibcon#*before return 0, iclass 17, count 0 2006.201.17:53:43.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:43.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.17:53:43.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:53:43.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:53:43.23$vck44/vblo=6,719.99 2006.201.17:53:43.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.17:53:43.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.17:53:43.23#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:43.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:43.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:43.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:43.23#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:53:43.23#ibcon#first serial, iclass 19, count 0 2006.201.17:53:43.23#ibcon#enter sib2, iclass 19, count 0 2006.201.17:53:43.23#ibcon#flushed, iclass 19, count 0 2006.201.17:53:43.23#ibcon#about to write, iclass 19, count 0 2006.201.17:53:43.23#ibcon#wrote, iclass 19, count 0 2006.201.17:53:43.23#ibcon#about to read 3, iclass 19, count 0 2006.201.17:53:43.25#ibcon#read 3, iclass 19, count 0 2006.201.17:53:43.25#ibcon#about to read 4, iclass 19, count 0 2006.201.17:53:43.25#ibcon#read 4, iclass 19, count 0 2006.201.17:53:43.25#ibcon#about to read 5, iclass 19, count 0 2006.201.17:53:43.25#ibcon#read 5, iclass 19, count 0 2006.201.17:53:43.25#ibcon#about to read 6, iclass 19, count 0 2006.201.17:53:43.25#ibcon#read 6, iclass 19, count 0 2006.201.17:53:43.25#ibcon#end of sib2, iclass 19, count 0 2006.201.17:53:43.25#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:53:43.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:53:43.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.17:53:43.25#ibcon#*before write, iclass 19, count 0 2006.201.17:53:43.25#ibcon#enter sib2, iclass 19, count 0 2006.201.17:53:43.25#ibcon#flushed, iclass 19, count 0 2006.201.17:53:43.25#ibcon#about to write, iclass 19, count 0 2006.201.17:53:43.25#ibcon#wrote, iclass 19, count 0 2006.201.17:53:43.25#ibcon#about to read 3, iclass 19, count 0 2006.201.17:53:43.29#ibcon#read 3, iclass 19, count 0 2006.201.17:53:43.29#ibcon#about to read 4, iclass 19, count 0 2006.201.17:53:43.29#ibcon#read 4, iclass 19, count 0 2006.201.17:53:43.29#ibcon#about to read 5, iclass 19, count 0 2006.201.17:53:43.29#ibcon#read 5, iclass 19, count 0 2006.201.17:53:43.29#ibcon#about to read 6, iclass 19, count 0 2006.201.17:53:43.29#ibcon#read 6, iclass 19, count 0 2006.201.17:53:43.29#ibcon#end of sib2, iclass 19, count 0 2006.201.17:53:43.29#ibcon#*after write, iclass 19, count 0 2006.201.17:53:43.29#ibcon#*before return 0, iclass 19, count 0 2006.201.17:53:43.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:43.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.17:53:43.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:53:43.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:53:43.29$vck44/vb=6,4 2006.201.17:53:43.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.17:53:43.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.17:53:43.29#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:43.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:43.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:43.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:43.35#ibcon#enter wrdev, iclass 21, count 2 2006.201.17:53:43.35#ibcon#first serial, iclass 21, count 2 2006.201.17:53:43.35#ibcon#enter sib2, iclass 21, count 2 2006.201.17:53:43.35#ibcon#flushed, iclass 21, count 2 2006.201.17:53:43.35#ibcon#about to write, iclass 21, count 2 2006.201.17:53:43.35#ibcon#wrote, iclass 21, count 2 2006.201.17:53:43.35#ibcon#about to read 3, iclass 21, count 2 2006.201.17:53:43.37#ibcon#read 3, iclass 21, count 2 2006.201.17:53:43.37#ibcon#about to read 4, iclass 21, count 2 2006.201.17:53:43.37#ibcon#read 4, iclass 21, count 2 2006.201.17:53:43.37#ibcon#about to read 5, iclass 21, count 2 2006.201.17:53:43.37#ibcon#read 5, iclass 21, count 2 2006.201.17:53:43.37#ibcon#about to read 6, iclass 21, count 2 2006.201.17:53:43.37#ibcon#read 6, iclass 21, count 2 2006.201.17:53:43.37#ibcon#end of sib2, iclass 21, count 2 2006.201.17:53:43.37#ibcon#*mode == 0, iclass 21, count 2 2006.201.17:53:43.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.17:53:43.37#ibcon#[27=AT06-04\r\n] 2006.201.17:53:43.37#ibcon#*before write, iclass 21, count 2 2006.201.17:53:43.37#ibcon#enter sib2, iclass 21, count 2 2006.201.17:53:43.37#ibcon#flushed, iclass 21, count 2 2006.201.17:53:43.37#ibcon#about to write, iclass 21, count 2 2006.201.17:53:43.37#ibcon#wrote, iclass 21, count 2 2006.201.17:53:43.37#ibcon#about to read 3, iclass 21, count 2 2006.201.17:53:43.41#ibcon#read 3, iclass 21, count 2 2006.201.17:53:43.41#ibcon#about to read 4, iclass 21, count 2 2006.201.17:53:43.41#ibcon#read 4, iclass 21, count 2 2006.201.17:53:43.41#ibcon#about to read 5, iclass 21, count 2 2006.201.17:53:43.41#ibcon#read 5, iclass 21, count 2 2006.201.17:53:43.41#ibcon#about to read 6, iclass 21, count 2 2006.201.17:53:43.41#ibcon#read 6, iclass 21, count 2 2006.201.17:53:43.41#ibcon#end of sib2, iclass 21, count 2 2006.201.17:53:43.41#ibcon#*after write, iclass 21, count 2 2006.201.17:53:43.41#ibcon#*before return 0, iclass 21, count 2 2006.201.17:53:43.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:43.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.17:53:43.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.17:53:43.41#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:43.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:43.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:43.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:43.53#ibcon#enter wrdev, iclass 21, count 0 2006.201.17:53:43.53#ibcon#first serial, iclass 21, count 0 2006.201.17:53:43.53#ibcon#enter sib2, iclass 21, count 0 2006.201.17:53:43.53#ibcon#flushed, iclass 21, count 0 2006.201.17:53:43.53#ibcon#about to write, iclass 21, count 0 2006.201.17:53:43.53#ibcon#wrote, iclass 21, count 0 2006.201.17:53:43.53#ibcon#about to read 3, iclass 21, count 0 2006.201.17:53:43.55#ibcon#read 3, iclass 21, count 0 2006.201.17:53:43.55#ibcon#about to read 4, iclass 21, count 0 2006.201.17:53:43.55#ibcon#read 4, iclass 21, count 0 2006.201.17:53:43.55#ibcon#about to read 5, iclass 21, count 0 2006.201.17:53:43.55#ibcon#read 5, iclass 21, count 0 2006.201.17:53:43.55#ibcon#about to read 6, iclass 21, count 0 2006.201.17:53:43.55#ibcon#read 6, iclass 21, count 0 2006.201.17:53:43.55#ibcon#end of sib2, iclass 21, count 0 2006.201.17:53:43.55#ibcon#*mode == 0, iclass 21, count 0 2006.201.17:53:43.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.17:53:43.55#ibcon#[27=USB\r\n] 2006.201.17:53:43.55#ibcon#*before write, iclass 21, count 0 2006.201.17:53:43.55#ibcon#enter sib2, iclass 21, count 0 2006.201.17:53:43.55#ibcon#flushed, iclass 21, count 0 2006.201.17:53:43.55#ibcon#about to write, iclass 21, count 0 2006.201.17:53:43.55#ibcon#wrote, iclass 21, count 0 2006.201.17:53:43.55#ibcon#about to read 3, iclass 21, count 0 2006.201.17:53:43.58#ibcon#read 3, iclass 21, count 0 2006.201.17:53:43.58#ibcon#about to read 4, iclass 21, count 0 2006.201.17:53:43.58#ibcon#read 4, iclass 21, count 0 2006.201.17:53:43.58#ibcon#about to read 5, iclass 21, count 0 2006.201.17:53:43.58#ibcon#read 5, iclass 21, count 0 2006.201.17:53:43.58#ibcon#about to read 6, iclass 21, count 0 2006.201.17:53:43.58#ibcon#read 6, iclass 21, count 0 2006.201.17:53:43.58#ibcon#end of sib2, iclass 21, count 0 2006.201.17:53:43.58#ibcon#*after write, iclass 21, count 0 2006.201.17:53:43.58#ibcon#*before return 0, iclass 21, count 0 2006.201.17:53:43.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:43.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.17:53:43.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.17:53:43.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.17:53:43.58$vck44/vblo=7,734.99 2006.201.17:53:43.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.17:53:43.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.17:53:43.58#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:43.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:43.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:43.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:43.58#ibcon#enter wrdev, iclass 23, count 0 2006.201.17:53:43.58#ibcon#first serial, iclass 23, count 0 2006.201.17:53:43.58#ibcon#enter sib2, iclass 23, count 0 2006.201.17:53:43.58#ibcon#flushed, iclass 23, count 0 2006.201.17:53:43.58#ibcon#about to write, iclass 23, count 0 2006.201.17:53:43.58#ibcon#wrote, iclass 23, count 0 2006.201.17:53:43.58#ibcon#about to read 3, iclass 23, count 0 2006.201.17:53:43.60#ibcon#read 3, iclass 23, count 0 2006.201.17:53:43.60#ibcon#about to read 4, iclass 23, count 0 2006.201.17:53:43.60#ibcon#read 4, iclass 23, count 0 2006.201.17:53:43.60#ibcon#about to read 5, iclass 23, count 0 2006.201.17:53:43.60#ibcon#read 5, iclass 23, count 0 2006.201.17:53:43.60#ibcon#about to read 6, iclass 23, count 0 2006.201.17:53:43.60#ibcon#read 6, iclass 23, count 0 2006.201.17:53:43.60#ibcon#end of sib2, iclass 23, count 0 2006.201.17:53:43.60#ibcon#*mode == 0, iclass 23, count 0 2006.201.17:53:43.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.17:53:43.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.17:53:43.60#ibcon#*before write, iclass 23, count 0 2006.201.17:53:43.60#ibcon#enter sib2, iclass 23, count 0 2006.201.17:53:43.60#ibcon#flushed, iclass 23, count 0 2006.201.17:53:43.60#ibcon#about to write, iclass 23, count 0 2006.201.17:53:43.60#ibcon#wrote, iclass 23, count 0 2006.201.17:53:43.60#ibcon#about to read 3, iclass 23, count 0 2006.201.17:53:43.64#ibcon#read 3, iclass 23, count 0 2006.201.17:53:43.64#ibcon#about to read 4, iclass 23, count 0 2006.201.17:53:43.64#ibcon#read 4, iclass 23, count 0 2006.201.17:53:43.64#ibcon#about to read 5, iclass 23, count 0 2006.201.17:53:43.64#ibcon#read 5, iclass 23, count 0 2006.201.17:53:43.64#ibcon#about to read 6, iclass 23, count 0 2006.201.17:53:43.64#ibcon#read 6, iclass 23, count 0 2006.201.17:53:43.64#ibcon#end of sib2, iclass 23, count 0 2006.201.17:53:43.64#ibcon#*after write, iclass 23, count 0 2006.201.17:53:43.64#ibcon#*before return 0, iclass 23, count 0 2006.201.17:53:43.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:43.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.17:53:43.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.17:53:43.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.17:53:43.64$vck44/vb=7,4 2006.201.17:53:43.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.17:53:43.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.17:53:43.64#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:43.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:43.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:43.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:43.70#ibcon#enter wrdev, iclass 25, count 2 2006.201.17:53:43.70#ibcon#first serial, iclass 25, count 2 2006.201.17:53:43.70#ibcon#enter sib2, iclass 25, count 2 2006.201.17:53:43.70#ibcon#flushed, iclass 25, count 2 2006.201.17:53:43.70#ibcon#about to write, iclass 25, count 2 2006.201.17:53:43.70#ibcon#wrote, iclass 25, count 2 2006.201.17:53:43.70#ibcon#about to read 3, iclass 25, count 2 2006.201.17:53:43.72#ibcon#read 3, iclass 25, count 2 2006.201.17:53:43.72#ibcon#about to read 4, iclass 25, count 2 2006.201.17:53:43.72#ibcon#read 4, iclass 25, count 2 2006.201.17:53:43.72#ibcon#about to read 5, iclass 25, count 2 2006.201.17:53:43.72#ibcon#read 5, iclass 25, count 2 2006.201.17:53:43.72#ibcon#about to read 6, iclass 25, count 2 2006.201.17:53:43.72#ibcon#read 6, iclass 25, count 2 2006.201.17:53:43.72#ibcon#end of sib2, iclass 25, count 2 2006.201.17:53:43.72#ibcon#*mode == 0, iclass 25, count 2 2006.201.17:53:43.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.17:53:43.72#ibcon#[27=AT07-04\r\n] 2006.201.17:53:43.72#ibcon#*before write, iclass 25, count 2 2006.201.17:53:43.72#ibcon#enter sib2, iclass 25, count 2 2006.201.17:53:43.72#ibcon#flushed, iclass 25, count 2 2006.201.17:53:43.72#ibcon#about to write, iclass 25, count 2 2006.201.17:53:43.72#ibcon#wrote, iclass 25, count 2 2006.201.17:53:43.72#ibcon#about to read 3, iclass 25, count 2 2006.201.17:53:43.75#ibcon#read 3, iclass 25, count 2 2006.201.17:53:43.75#ibcon#about to read 4, iclass 25, count 2 2006.201.17:53:43.75#ibcon#read 4, iclass 25, count 2 2006.201.17:53:43.75#ibcon#about to read 5, iclass 25, count 2 2006.201.17:53:43.75#ibcon#read 5, iclass 25, count 2 2006.201.17:53:43.75#ibcon#about to read 6, iclass 25, count 2 2006.201.17:53:43.75#ibcon#read 6, iclass 25, count 2 2006.201.17:53:43.75#ibcon#end of sib2, iclass 25, count 2 2006.201.17:53:43.75#ibcon#*after write, iclass 25, count 2 2006.201.17:53:43.75#ibcon#*before return 0, iclass 25, count 2 2006.201.17:53:43.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:43.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.17:53:43.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.17:53:43.75#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:43.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:43.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:43.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:43.87#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:53:43.87#ibcon#first serial, iclass 25, count 0 2006.201.17:53:43.87#ibcon#enter sib2, iclass 25, count 0 2006.201.17:53:43.87#ibcon#flushed, iclass 25, count 0 2006.201.17:53:43.87#ibcon#about to write, iclass 25, count 0 2006.201.17:53:43.87#ibcon#wrote, iclass 25, count 0 2006.201.17:53:43.87#ibcon#about to read 3, iclass 25, count 0 2006.201.17:53:43.89#ibcon#read 3, iclass 25, count 0 2006.201.17:53:43.89#ibcon#about to read 4, iclass 25, count 0 2006.201.17:53:43.89#ibcon#read 4, iclass 25, count 0 2006.201.17:53:43.89#ibcon#about to read 5, iclass 25, count 0 2006.201.17:53:43.89#ibcon#read 5, iclass 25, count 0 2006.201.17:53:43.89#ibcon#about to read 6, iclass 25, count 0 2006.201.17:53:43.89#ibcon#read 6, iclass 25, count 0 2006.201.17:53:43.89#ibcon#end of sib2, iclass 25, count 0 2006.201.17:53:43.89#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:53:43.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:53:43.89#ibcon#[27=USB\r\n] 2006.201.17:53:43.89#ibcon#*before write, iclass 25, count 0 2006.201.17:53:43.89#ibcon#enter sib2, iclass 25, count 0 2006.201.17:53:43.89#ibcon#flushed, iclass 25, count 0 2006.201.17:53:43.89#ibcon#about to write, iclass 25, count 0 2006.201.17:53:43.89#ibcon#wrote, iclass 25, count 0 2006.201.17:53:43.89#ibcon#about to read 3, iclass 25, count 0 2006.201.17:53:43.92#ibcon#read 3, iclass 25, count 0 2006.201.17:53:43.92#ibcon#about to read 4, iclass 25, count 0 2006.201.17:53:43.92#ibcon#read 4, iclass 25, count 0 2006.201.17:53:43.92#ibcon#about to read 5, iclass 25, count 0 2006.201.17:53:43.92#ibcon#read 5, iclass 25, count 0 2006.201.17:53:43.92#ibcon#about to read 6, iclass 25, count 0 2006.201.17:53:43.92#ibcon#read 6, iclass 25, count 0 2006.201.17:53:43.92#ibcon#end of sib2, iclass 25, count 0 2006.201.17:53:43.92#ibcon#*after write, iclass 25, count 0 2006.201.17:53:43.92#ibcon#*before return 0, iclass 25, count 0 2006.201.17:53:43.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:43.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.17:53:43.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:53:43.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:53:43.92$vck44/vblo=8,744.99 2006.201.17:53:43.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.17:53:43.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.17:53:43.92#ibcon#ireg 17 cls_cnt 0 2006.201.17:53:43.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:43.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:43.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:43.92#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:53:43.92#ibcon#first serial, iclass 27, count 0 2006.201.17:53:43.92#ibcon#enter sib2, iclass 27, count 0 2006.201.17:53:43.92#ibcon#flushed, iclass 27, count 0 2006.201.17:53:43.92#ibcon#about to write, iclass 27, count 0 2006.201.17:53:43.92#ibcon#wrote, iclass 27, count 0 2006.201.17:53:43.92#ibcon#about to read 3, iclass 27, count 0 2006.201.17:53:43.94#ibcon#read 3, iclass 27, count 0 2006.201.17:53:43.94#ibcon#about to read 4, iclass 27, count 0 2006.201.17:53:43.94#ibcon#read 4, iclass 27, count 0 2006.201.17:53:43.94#ibcon#about to read 5, iclass 27, count 0 2006.201.17:53:43.94#ibcon#read 5, iclass 27, count 0 2006.201.17:53:43.94#ibcon#about to read 6, iclass 27, count 0 2006.201.17:53:43.94#ibcon#read 6, iclass 27, count 0 2006.201.17:53:43.94#ibcon#end of sib2, iclass 27, count 0 2006.201.17:53:43.94#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:53:43.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:53:43.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.17:53:43.94#ibcon#*before write, iclass 27, count 0 2006.201.17:53:43.94#ibcon#enter sib2, iclass 27, count 0 2006.201.17:53:43.94#ibcon#flushed, iclass 27, count 0 2006.201.17:53:43.94#ibcon#about to write, iclass 27, count 0 2006.201.17:53:43.94#ibcon#wrote, iclass 27, count 0 2006.201.17:53:43.94#ibcon#about to read 3, iclass 27, count 0 2006.201.17:53:43.98#ibcon#read 3, iclass 27, count 0 2006.201.17:53:43.98#ibcon#about to read 4, iclass 27, count 0 2006.201.17:53:43.98#ibcon#read 4, iclass 27, count 0 2006.201.17:53:43.98#ibcon#about to read 5, iclass 27, count 0 2006.201.17:53:43.98#ibcon#read 5, iclass 27, count 0 2006.201.17:53:43.98#ibcon#about to read 6, iclass 27, count 0 2006.201.17:53:43.98#ibcon#read 6, iclass 27, count 0 2006.201.17:53:43.98#ibcon#end of sib2, iclass 27, count 0 2006.201.17:53:43.98#ibcon#*after write, iclass 27, count 0 2006.201.17:53:43.98#ibcon#*before return 0, iclass 27, count 0 2006.201.17:53:43.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:43.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.17:53:43.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:53:43.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:53:43.98$vck44/vb=8,4 2006.201.17:53:43.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.17:53:43.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.17:53:43.98#ibcon#ireg 11 cls_cnt 2 2006.201.17:53:43.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:44.04#abcon#<5=/16 0.7 1.4 20.591001002.3\r\n> 2006.201.17:53:44.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:44.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:44.04#ibcon#enter wrdev, iclass 29, count 2 2006.201.17:53:44.04#ibcon#first serial, iclass 29, count 2 2006.201.17:53:44.04#ibcon#enter sib2, iclass 29, count 2 2006.201.17:53:44.04#ibcon#flushed, iclass 29, count 2 2006.201.17:53:44.04#ibcon#about to write, iclass 29, count 2 2006.201.17:53:44.04#ibcon#wrote, iclass 29, count 2 2006.201.17:53:44.04#ibcon#about to read 3, iclass 29, count 2 2006.201.17:53:44.06#abcon#{5=INTERFACE CLEAR} 2006.201.17:53:44.06#ibcon#read 3, iclass 29, count 2 2006.201.17:53:44.06#ibcon#about to read 4, iclass 29, count 2 2006.201.17:53:44.06#ibcon#read 4, iclass 29, count 2 2006.201.17:53:44.06#ibcon#about to read 5, iclass 29, count 2 2006.201.17:53:44.06#ibcon#read 5, iclass 29, count 2 2006.201.17:53:44.06#ibcon#about to read 6, iclass 29, count 2 2006.201.17:53:44.06#ibcon#read 6, iclass 29, count 2 2006.201.17:53:44.06#ibcon#end of sib2, iclass 29, count 2 2006.201.17:53:44.06#ibcon#*mode == 0, iclass 29, count 2 2006.201.17:53:44.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.17:53:44.06#ibcon#[27=AT08-04\r\n] 2006.201.17:53:44.06#ibcon#*before write, iclass 29, count 2 2006.201.17:53:44.06#ibcon#enter sib2, iclass 29, count 2 2006.201.17:53:44.06#ibcon#flushed, iclass 29, count 2 2006.201.17:53:44.06#ibcon#about to write, iclass 29, count 2 2006.201.17:53:44.06#ibcon#wrote, iclass 29, count 2 2006.201.17:53:44.06#ibcon#about to read 3, iclass 29, count 2 2006.201.17:53:44.09#ibcon#read 3, iclass 29, count 2 2006.201.17:53:44.09#ibcon#about to read 4, iclass 29, count 2 2006.201.17:53:44.09#ibcon#read 4, iclass 29, count 2 2006.201.17:53:44.09#ibcon#about to read 5, iclass 29, count 2 2006.201.17:53:44.09#ibcon#read 5, iclass 29, count 2 2006.201.17:53:44.09#ibcon#about to read 6, iclass 29, count 2 2006.201.17:53:44.09#ibcon#read 6, iclass 29, count 2 2006.201.17:53:44.09#ibcon#end of sib2, iclass 29, count 2 2006.201.17:53:44.09#ibcon#*after write, iclass 29, count 2 2006.201.17:53:44.09#ibcon#*before return 0, iclass 29, count 2 2006.201.17:53:44.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:44.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.17:53:44.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.17:53:44.09#ibcon#ireg 7 cls_cnt 0 2006.201.17:53:44.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:44.12#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:53:44.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:44.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:44.21#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:53:44.21#ibcon#first serial, iclass 29, count 0 2006.201.17:53:44.21#ibcon#enter sib2, iclass 29, count 0 2006.201.17:53:44.21#ibcon#flushed, iclass 29, count 0 2006.201.17:53:44.21#ibcon#about to write, iclass 29, count 0 2006.201.17:53:44.21#ibcon#wrote, iclass 29, count 0 2006.201.17:53:44.21#ibcon#about to read 3, iclass 29, count 0 2006.201.17:53:44.24#ibcon#read 3, iclass 29, count 0 2006.201.17:53:44.24#ibcon#about to read 4, iclass 29, count 0 2006.201.17:53:44.24#ibcon#read 4, iclass 29, count 0 2006.201.17:53:44.24#ibcon#about to read 5, iclass 29, count 0 2006.201.17:53:44.24#ibcon#read 5, iclass 29, count 0 2006.201.17:53:44.24#ibcon#about to read 6, iclass 29, count 0 2006.201.17:53:44.24#ibcon#read 6, iclass 29, count 0 2006.201.17:53:44.24#ibcon#end of sib2, iclass 29, count 0 2006.201.17:53:44.24#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:53:44.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:53:44.24#ibcon#[27=USB\r\n] 2006.201.17:53:44.24#ibcon#*before write, iclass 29, count 0 2006.201.17:53:44.24#ibcon#enter sib2, iclass 29, count 0 2006.201.17:53:44.24#ibcon#flushed, iclass 29, count 0 2006.201.17:53:44.24#ibcon#about to write, iclass 29, count 0 2006.201.17:53:44.24#ibcon#wrote, iclass 29, count 0 2006.201.17:53:44.24#ibcon#about to read 3, iclass 29, count 0 2006.201.17:53:44.27#ibcon#read 3, iclass 29, count 0 2006.201.17:53:44.27#ibcon#about to read 4, iclass 29, count 0 2006.201.17:53:44.27#ibcon#read 4, iclass 29, count 0 2006.201.17:53:44.27#ibcon#about to read 5, iclass 29, count 0 2006.201.17:53:44.27#ibcon#read 5, iclass 29, count 0 2006.201.17:53:44.27#ibcon#about to read 6, iclass 29, count 0 2006.201.17:53:44.27#ibcon#read 6, iclass 29, count 0 2006.201.17:53:44.27#ibcon#end of sib2, iclass 29, count 0 2006.201.17:53:44.27#ibcon#*after write, iclass 29, count 0 2006.201.17:53:44.27#ibcon#*before return 0, iclass 29, count 0 2006.201.17:53:44.27#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:44.27#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.17:53:44.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:53:44.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:53:44.27$vck44/vabw=wide 2006.201.17:53:44.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.17:53:44.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.17:53:44.27#ibcon#ireg 8 cls_cnt 0 2006.201.17:53:44.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:44.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:44.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:44.27#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:53:44.27#ibcon#first serial, iclass 35, count 0 2006.201.17:53:44.27#ibcon#enter sib2, iclass 35, count 0 2006.201.17:53:44.27#ibcon#flushed, iclass 35, count 0 2006.201.17:53:44.27#ibcon#about to write, iclass 35, count 0 2006.201.17:53:44.27#ibcon#wrote, iclass 35, count 0 2006.201.17:53:44.27#ibcon#about to read 3, iclass 35, count 0 2006.201.17:53:44.29#ibcon#read 3, iclass 35, count 0 2006.201.17:53:44.29#ibcon#about to read 4, iclass 35, count 0 2006.201.17:53:44.29#ibcon#read 4, iclass 35, count 0 2006.201.17:53:44.29#ibcon#about to read 5, iclass 35, count 0 2006.201.17:53:44.29#ibcon#read 5, iclass 35, count 0 2006.201.17:53:44.29#ibcon#about to read 6, iclass 35, count 0 2006.201.17:53:44.29#ibcon#read 6, iclass 35, count 0 2006.201.17:53:44.29#ibcon#end of sib2, iclass 35, count 0 2006.201.17:53:44.29#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:53:44.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:53:44.29#ibcon#[25=BW32\r\n] 2006.201.17:53:44.29#ibcon#*before write, iclass 35, count 0 2006.201.17:53:44.29#ibcon#enter sib2, iclass 35, count 0 2006.201.17:53:44.29#ibcon#flushed, iclass 35, count 0 2006.201.17:53:44.29#ibcon#about to write, iclass 35, count 0 2006.201.17:53:44.29#ibcon#wrote, iclass 35, count 0 2006.201.17:53:44.29#ibcon#about to read 3, iclass 35, count 0 2006.201.17:53:44.32#ibcon#read 3, iclass 35, count 0 2006.201.17:53:44.32#ibcon#about to read 4, iclass 35, count 0 2006.201.17:53:44.32#ibcon#read 4, iclass 35, count 0 2006.201.17:53:44.32#ibcon#about to read 5, iclass 35, count 0 2006.201.17:53:44.32#ibcon#read 5, iclass 35, count 0 2006.201.17:53:44.32#ibcon#about to read 6, iclass 35, count 0 2006.201.17:53:44.32#ibcon#read 6, iclass 35, count 0 2006.201.17:53:44.32#ibcon#end of sib2, iclass 35, count 0 2006.201.17:53:44.32#ibcon#*after write, iclass 35, count 0 2006.201.17:53:44.32#ibcon#*before return 0, iclass 35, count 0 2006.201.17:53:44.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:44.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.17:53:44.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:53:44.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:53:44.32$vck44/vbbw=wide 2006.201.17:53:44.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.17:53:44.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.17:53:44.32#ibcon#ireg 8 cls_cnt 0 2006.201.17:53:44.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:53:44.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:53:44.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:53:44.39#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:53:44.39#ibcon#first serial, iclass 37, count 0 2006.201.17:53:44.39#ibcon#enter sib2, iclass 37, count 0 2006.201.17:53:44.39#ibcon#flushed, iclass 37, count 0 2006.201.17:53:44.39#ibcon#about to write, iclass 37, count 0 2006.201.17:53:44.39#ibcon#wrote, iclass 37, count 0 2006.201.17:53:44.39#ibcon#about to read 3, iclass 37, count 0 2006.201.17:53:44.41#ibcon#read 3, iclass 37, count 0 2006.201.17:53:44.41#ibcon#about to read 4, iclass 37, count 0 2006.201.17:53:44.41#ibcon#read 4, iclass 37, count 0 2006.201.17:53:44.41#ibcon#about to read 5, iclass 37, count 0 2006.201.17:53:44.41#ibcon#read 5, iclass 37, count 0 2006.201.17:53:44.41#ibcon#about to read 6, iclass 37, count 0 2006.201.17:53:44.41#ibcon#read 6, iclass 37, count 0 2006.201.17:53:44.41#ibcon#end of sib2, iclass 37, count 0 2006.201.17:53:44.41#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:53:44.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:53:44.41#ibcon#[27=BW32\r\n] 2006.201.17:53:44.41#ibcon#*before write, iclass 37, count 0 2006.201.17:53:44.41#ibcon#enter sib2, iclass 37, count 0 2006.201.17:53:44.41#ibcon#flushed, iclass 37, count 0 2006.201.17:53:44.41#ibcon#about to write, iclass 37, count 0 2006.201.17:53:44.41#ibcon#wrote, iclass 37, count 0 2006.201.17:53:44.41#ibcon#about to read 3, iclass 37, count 0 2006.201.17:53:44.44#ibcon#read 3, iclass 37, count 0 2006.201.17:53:44.44#ibcon#about to read 4, iclass 37, count 0 2006.201.17:53:44.44#ibcon#read 4, iclass 37, count 0 2006.201.17:53:44.44#ibcon#about to read 5, iclass 37, count 0 2006.201.17:53:44.44#ibcon#read 5, iclass 37, count 0 2006.201.17:53:44.44#ibcon#about to read 6, iclass 37, count 0 2006.201.17:53:44.44#ibcon#read 6, iclass 37, count 0 2006.201.17:53:44.44#ibcon#end of sib2, iclass 37, count 0 2006.201.17:53:44.44#ibcon#*after write, iclass 37, count 0 2006.201.17:53:44.44#ibcon#*before return 0, iclass 37, count 0 2006.201.17:53:44.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:53:44.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:53:44.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:53:44.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:53:44.44$setupk4/ifdk4 2006.201.17:53:44.44$ifdk4/lo= 2006.201.17:53:44.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.17:53:44.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.17:53:44.44$ifdk4/patch= 2006.201.17:53:44.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.17:53:44.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.17:53:44.44$setupk4/!*+20s 2006.201.17:53:54.21#abcon#<5=/16 0.6 1.4 20.591001002.4\r\n> 2006.201.17:53:54.23#abcon#{5=INTERFACE CLEAR} 2006.201.17:53:54.29#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:53:56.13#trakl#Source acquired 2006.201.17:53:58.13#flagr#flagr/antenna,acquired 2006.201.17:53:58.93$setupk4/"tpicd 2006.201.17:53:58.93$setupk4/echo=off 2006.201.17:53:58.93$setupk4/xlog=off 2006.201.17:53:58.93:!2006.201.17:54:10 2006.201.17:54:10.00:preob 2006.201.17:54:11.13/onsource/TRACKING 2006.201.17:54:11.13:!2006.201.17:54:20 2006.201.17:54:20.00:"tape 2006.201.17:54:20.00:"st=record 2006.201.17:54:20.00:data_valid=on 2006.201.17:54:20.00:midob 2006.201.17:54:20.13/onsource/TRACKING 2006.201.17:54:20.13/wx/20.58,1002.4,100 2006.201.17:54:20.29/cable/+6.4766E-03 2006.201.17:54:21.38/va/01,08,usb,yes,49,52 2006.201.17:54:21.38/va/02,07,usb,yes,53,54 2006.201.17:54:21.38/va/03,08,usb,yes,48,50 2006.201.17:54:21.38/va/04,07,usb,yes,54,56 2006.201.17:54:21.38/va/05,04,usb,yes,48,49 2006.201.17:54:21.38/va/06,05,usb,yes,48,48 2006.201.17:54:21.38/va/07,05,usb,yes,47,49 2006.201.17:54:21.38/va/08,04,usb,yes,47,55 2006.201.17:54:21.61/valo/01,524.99,yes,locked 2006.201.17:54:21.61/valo/02,534.99,yes,locked 2006.201.17:54:21.61/valo/03,564.99,yes,locked 2006.201.17:54:21.61/valo/04,624.99,yes,locked 2006.201.17:54:21.61/valo/05,734.99,yes,locked 2006.201.17:54:21.61/valo/06,814.99,yes,locked 2006.201.17:54:21.61/valo/07,864.99,yes,locked 2006.201.17:54:21.61/valo/08,884.99,yes,locked 2006.201.17:54:22.70/vb/01,04,usb,yes,35,32 2006.201.17:54:22.70/vb/02,05,usb,yes,33,33 2006.201.17:54:22.70/vb/03,04,usb,yes,34,38 2006.201.17:54:22.70/vb/04,05,usb,yes,35,34 2006.201.17:54:22.70/vb/05,04,usb,yes,31,34 2006.201.17:54:22.70/vb/06,04,usb,yes,36,32 2006.201.17:54:22.70/vb/07,04,usb,yes,36,36 2006.201.17:54:22.70/vb/08,04,usb,yes,33,37 2006.201.17:54:22.93/vblo/01,629.99,yes,locked 2006.201.17:54:22.93/vblo/02,634.99,yes,locked 2006.201.17:54:22.93/vblo/03,649.99,yes,locked 2006.201.17:54:22.93/vblo/04,679.99,yes,locked 2006.201.17:54:22.93/vblo/05,709.99,yes,locked 2006.201.17:54:22.93/vblo/06,719.99,yes,locked 2006.201.17:54:22.93/vblo/07,734.99,yes,locked 2006.201.17:54:22.93/vblo/08,744.99,yes,locked 2006.201.17:54:23.08/vabw/8 2006.201.17:54:23.23/vbbw/8 2006.201.17:54:23.32/xfe/off,on,14.5 2006.201.17:54:23.69/ifatt/23,28,28,28 2006.201.17:54:24.06/fmout-gps/S +4.59E-07 2006.201.17:54:24.10:!2006.201.17:55:00 2006.201.17:55:00.00:data_valid=off 2006.201.17:55:00.00:"et 2006.201.17:55:00.00:!+3s 2006.201.17:55:03.02:"tape 2006.201.17:55:03.02:postob 2006.201.17:55:03.16/cable/+6.4791E-03 2006.201.17:55:03.16/wx/20.58,1002.4,100 2006.201.17:55:03.22/fmout-gps/S +4.59E-07 2006.201.17:55:03.22:scan_name=201-1756,jd0607,110 2006.201.17:55:03.22:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.201.17:55:05.14#flagr#flagr/antenna,new-source 2006.201.17:55:05.14:checkk5 2006.201.17:55:05.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.17:55:05.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.17:55:06.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.17:55:06.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.17:55:07.00/chk_obsdata//k5ts1/T2011754??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.17:55:07.37/chk_obsdata//k5ts2/T2011754??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.17:55:07.74/chk_obsdata//k5ts3/T2011754??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.17:55:08.11/chk_obsdata//k5ts4/T2011754??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.17:55:08.79/k5log//k5ts1_log_newline 2006.201.17:55:09.49/k5log//k5ts2_log_newline 2006.201.17:55:10.18/k5log//k5ts3_log_newline 2006.201.17:55:10.87/k5log//k5ts4_log_newline 2006.201.17:55:10.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.17:55:10.89:setupk4=1 2006.201.17:55:10.89$setupk4/echo=on 2006.201.17:55:10.89$setupk4/pcalon 2006.201.17:55:10.89$pcalon/"no phase cal control is implemented here 2006.201.17:55:10.89$setupk4/"tpicd=stop 2006.201.17:55:10.89$setupk4/"rec=synch_on 2006.201.17:55:10.89$setupk4/"rec_mode=128 2006.201.17:55:10.89$setupk4/!* 2006.201.17:55:10.89$setupk4/recpk4 2006.201.17:55:10.89$recpk4/recpatch= 2006.201.17:55:10.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.17:55:10.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.17:55:10.90$setupk4/vck44 2006.201.17:55:10.90$vck44/valo=1,524.99 2006.201.17:55:10.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.17:55:10.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.17:55:10.90#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:10.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:10.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:10.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:10.90#ibcon#enter wrdev, iclass 38, count 0 2006.201.17:55:10.90#ibcon#first serial, iclass 38, count 0 2006.201.17:55:10.90#ibcon#enter sib2, iclass 38, count 0 2006.201.17:55:10.90#ibcon#flushed, iclass 38, count 0 2006.201.17:55:10.90#ibcon#about to write, iclass 38, count 0 2006.201.17:55:10.90#ibcon#wrote, iclass 38, count 0 2006.201.17:55:10.90#ibcon#about to read 3, iclass 38, count 0 2006.201.17:55:10.93#ibcon#read 3, iclass 38, count 0 2006.201.17:55:10.93#ibcon#about to read 4, iclass 38, count 0 2006.201.17:55:10.93#ibcon#read 4, iclass 38, count 0 2006.201.17:55:10.93#ibcon#about to read 5, iclass 38, count 0 2006.201.17:55:10.93#ibcon#read 5, iclass 38, count 0 2006.201.17:55:10.93#ibcon#about to read 6, iclass 38, count 0 2006.201.17:55:10.93#ibcon#read 6, iclass 38, count 0 2006.201.17:55:10.93#ibcon#end of sib2, iclass 38, count 0 2006.201.17:55:10.93#ibcon#*mode == 0, iclass 38, count 0 2006.201.17:55:10.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.17:55:10.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.17:55:10.93#ibcon#*before write, iclass 38, count 0 2006.201.17:55:10.93#ibcon#enter sib2, iclass 38, count 0 2006.201.17:55:10.93#ibcon#flushed, iclass 38, count 0 2006.201.17:55:10.93#ibcon#about to write, iclass 38, count 0 2006.201.17:55:10.93#ibcon#wrote, iclass 38, count 0 2006.201.17:55:10.93#ibcon#about to read 3, iclass 38, count 0 2006.201.17:55:10.98#ibcon#read 3, iclass 38, count 0 2006.201.17:55:10.98#ibcon#about to read 4, iclass 38, count 0 2006.201.17:55:10.98#ibcon#read 4, iclass 38, count 0 2006.201.17:55:10.98#ibcon#about to read 5, iclass 38, count 0 2006.201.17:55:10.98#ibcon#read 5, iclass 38, count 0 2006.201.17:55:10.98#ibcon#about to read 6, iclass 38, count 0 2006.201.17:55:10.98#ibcon#read 6, iclass 38, count 0 2006.201.17:55:10.98#ibcon#end of sib2, iclass 38, count 0 2006.201.17:55:10.98#ibcon#*after write, iclass 38, count 0 2006.201.17:55:10.98#ibcon#*before return 0, iclass 38, count 0 2006.201.17:55:10.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:10.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:10.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.17:55:10.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.17:55:10.98$vck44/va=1,8 2006.201.17:55:10.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.17:55:10.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.17:55:10.98#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:10.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:10.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:10.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:10.98#ibcon#enter wrdev, iclass 40, count 2 2006.201.17:55:10.98#ibcon#first serial, iclass 40, count 2 2006.201.17:55:10.98#ibcon#enter sib2, iclass 40, count 2 2006.201.17:55:10.98#ibcon#flushed, iclass 40, count 2 2006.201.17:55:10.98#ibcon#about to write, iclass 40, count 2 2006.201.17:55:10.98#ibcon#wrote, iclass 40, count 2 2006.201.17:55:10.98#ibcon#about to read 3, iclass 40, count 2 2006.201.17:55:11.00#ibcon#read 3, iclass 40, count 2 2006.201.17:55:11.00#ibcon#about to read 4, iclass 40, count 2 2006.201.17:55:11.00#ibcon#read 4, iclass 40, count 2 2006.201.17:55:11.00#ibcon#about to read 5, iclass 40, count 2 2006.201.17:55:11.00#ibcon#read 5, iclass 40, count 2 2006.201.17:55:11.00#ibcon#about to read 6, iclass 40, count 2 2006.201.17:55:11.00#ibcon#read 6, iclass 40, count 2 2006.201.17:55:11.00#ibcon#end of sib2, iclass 40, count 2 2006.201.17:55:11.00#ibcon#*mode == 0, iclass 40, count 2 2006.201.17:55:11.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.17:55:11.00#ibcon#[25=AT01-08\r\n] 2006.201.17:55:11.00#ibcon#*before write, iclass 40, count 2 2006.201.17:55:11.00#ibcon#enter sib2, iclass 40, count 2 2006.201.17:55:11.00#ibcon#flushed, iclass 40, count 2 2006.201.17:55:11.00#ibcon#about to write, iclass 40, count 2 2006.201.17:55:11.00#ibcon#wrote, iclass 40, count 2 2006.201.17:55:11.00#ibcon#about to read 3, iclass 40, count 2 2006.201.17:55:11.03#ibcon#read 3, iclass 40, count 2 2006.201.17:55:11.03#ibcon#about to read 4, iclass 40, count 2 2006.201.17:55:11.03#ibcon#read 4, iclass 40, count 2 2006.201.17:55:11.03#ibcon#about to read 5, iclass 40, count 2 2006.201.17:55:11.03#ibcon#read 5, iclass 40, count 2 2006.201.17:55:11.03#ibcon#about to read 6, iclass 40, count 2 2006.201.17:55:11.03#ibcon#read 6, iclass 40, count 2 2006.201.17:55:11.03#ibcon#end of sib2, iclass 40, count 2 2006.201.17:55:11.03#ibcon#*after write, iclass 40, count 2 2006.201.17:55:11.03#ibcon#*before return 0, iclass 40, count 2 2006.201.17:55:11.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:11.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:11.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.17:55:11.03#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:11.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:11.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:11.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:11.15#ibcon#enter wrdev, iclass 40, count 0 2006.201.17:55:11.15#ibcon#first serial, iclass 40, count 0 2006.201.17:55:11.15#ibcon#enter sib2, iclass 40, count 0 2006.201.17:55:11.15#ibcon#flushed, iclass 40, count 0 2006.201.17:55:11.15#ibcon#about to write, iclass 40, count 0 2006.201.17:55:11.15#ibcon#wrote, iclass 40, count 0 2006.201.17:55:11.15#ibcon#about to read 3, iclass 40, count 0 2006.201.17:55:11.17#ibcon#read 3, iclass 40, count 0 2006.201.17:55:11.17#ibcon#about to read 4, iclass 40, count 0 2006.201.17:55:11.17#ibcon#read 4, iclass 40, count 0 2006.201.17:55:11.17#ibcon#about to read 5, iclass 40, count 0 2006.201.17:55:11.17#ibcon#read 5, iclass 40, count 0 2006.201.17:55:11.17#ibcon#about to read 6, iclass 40, count 0 2006.201.17:55:11.17#ibcon#read 6, iclass 40, count 0 2006.201.17:55:11.17#ibcon#end of sib2, iclass 40, count 0 2006.201.17:55:11.17#ibcon#*mode == 0, iclass 40, count 0 2006.201.17:55:11.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.17:55:11.17#ibcon#[25=USB\r\n] 2006.201.17:55:11.17#ibcon#*before write, iclass 40, count 0 2006.201.17:55:11.17#ibcon#enter sib2, iclass 40, count 0 2006.201.17:55:11.17#ibcon#flushed, iclass 40, count 0 2006.201.17:55:11.17#ibcon#about to write, iclass 40, count 0 2006.201.17:55:11.17#ibcon#wrote, iclass 40, count 0 2006.201.17:55:11.17#ibcon#about to read 3, iclass 40, count 0 2006.201.17:55:11.20#ibcon#read 3, iclass 40, count 0 2006.201.17:55:11.20#ibcon#about to read 4, iclass 40, count 0 2006.201.17:55:11.20#ibcon#read 4, iclass 40, count 0 2006.201.17:55:11.20#ibcon#about to read 5, iclass 40, count 0 2006.201.17:55:11.20#ibcon#read 5, iclass 40, count 0 2006.201.17:55:11.20#ibcon#about to read 6, iclass 40, count 0 2006.201.17:55:11.20#ibcon#read 6, iclass 40, count 0 2006.201.17:55:11.20#ibcon#end of sib2, iclass 40, count 0 2006.201.17:55:11.20#ibcon#*after write, iclass 40, count 0 2006.201.17:55:11.20#ibcon#*before return 0, iclass 40, count 0 2006.201.17:55:11.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:11.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:11.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.17:55:11.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.17:55:11.20$vck44/valo=2,534.99 2006.201.17:55:11.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.17:55:11.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.17:55:11.20#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:11.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:11.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:11.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:11.20#ibcon#enter wrdev, iclass 4, count 0 2006.201.17:55:11.20#ibcon#first serial, iclass 4, count 0 2006.201.17:55:11.20#ibcon#enter sib2, iclass 4, count 0 2006.201.17:55:11.20#ibcon#flushed, iclass 4, count 0 2006.201.17:55:11.20#ibcon#about to write, iclass 4, count 0 2006.201.17:55:11.20#ibcon#wrote, iclass 4, count 0 2006.201.17:55:11.20#ibcon#about to read 3, iclass 4, count 0 2006.201.17:55:11.22#ibcon#read 3, iclass 4, count 0 2006.201.17:55:11.22#ibcon#about to read 4, iclass 4, count 0 2006.201.17:55:11.22#ibcon#read 4, iclass 4, count 0 2006.201.17:55:11.22#ibcon#about to read 5, iclass 4, count 0 2006.201.17:55:11.22#ibcon#read 5, iclass 4, count 0 2006.201.17:55:11.22#ibcon#about to read 6, iclass 4, count 0 2006.201.17:55:11.22#ibcon#read 6, iclass 4, count 0 2006.201.17:55:11.22#ibcon#end of sib2, iclass 4, count 0 2006.201.17:55:11.22#ibcon#*mode == 0, iclass 4, count 0 2006.201.17:55:11.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.17:55:11.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.17:55:11.22#ibcon#*before write, iclass 4, count 0 2006.201.17:55:11.22#ibcon#enter sib2, iclass 4, count 0 2006.201.17:55:11.22#ibcon#flushed, iclass 4, count 0 2006.201.17:55:11.22#ibcon#about to write, iclass 4, count 0 2006.201.17:55:11.22#ibcon#wrote, iclass 4, count 0 2006.201.17:55:11.22#ibcon#about to read 3, iclass 4, count 0 2006.201.17:55:11.26#ibcon#read 3, iclass 4, count 0 2006.201.17:55:11.26#ibcon#about to read 4, iclass 4, count 0 2006.201.17:55:11.26#ibcon#read 4, iclass 4, count 0 2006.201.17:55:11.26#ibcon#about to read 5, iclass 4, count 0 2006.201.17:55:11.26#ibcon#read 5, iclass 4, count 0 2006.201.17:55:11.26#ibcon#about to read 6, iclass 4, count 0 2006.201.17:55:11.26#ibcon#read 6, iclass 4, count 0 2006.201.17:55:11.26#ibcon#end of sib2, iclass 4, count 0 2006.201.17:55:11.26#ibcon#*after write, iclass 4, count 0 2006.201.17:55:11.26#ibcon#*before return 0, iclass 4, count 0 2006.201.17:55:11.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:11.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:11.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.17:55:11.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.17:55:11.26$vck44/va=2,7 2006.201.17:55:11.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.17:55:11.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.17:55:11.26#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:11.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:11.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:11.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:11.32#ibcon#enter wrdev, iclass 6, count 2 2006.201.17:55:11.32#ibcon#first serial, iclass 6, count 2 2006.201.17:55:11.32#ibcon#enter sib2, iclass 6, count 2 2006.201.17:55:11.32#ibcon#flushed, iclass 6, count 2 2006.201.17:55:11.32#ibcon#about to write, iclass 6, count 2 2006.201.17:55:11.32#ibcon#wrote, iclass 6, count 2 2006.201.17:55:11.32#ibcon#about to read 3, iclass 6, count 2 2006.201.17:55:11.34#ibcon#read 3, iclass 6, count 2 2006.201.17:55:11.34#ibcon#about to read 4, iclass 6, count 2 2006.201.17:55:11.34#ibcon#read 4, iclass 6, count 2 2006.201.17:55:11.34#ibcon#about to read 5, iclass 6, count 2 2006.201.17:55:11.34#ibcon#read 5, iclass 6, count 2 2006.201.17:55:11.34#ibcon#about to read 6, iclass 6, count 2 2006.201.17:55:11.34#ibcon#read 6, iclass 6, count 2 2006.201.17:55:11.34#ibcon#end of sib2, iclass 6, count 2 2006.201.17:55:11.34#ibcon#*mode == 0, iclass 6, count 2 2006.201.17:55:11.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.17:55:11.34#ibcon#[25=AT02-07\r\n] 2006.201.17:55:11.34#ibcon#*before write, iclass 6, count 2 2006.201.17:55:11.34#ibcon#enter sib2, iclass 6, count 2 2006.201.17:55:11.34#ibcon#flushed, iclass 6, count 2 2006.201.17:55:11.34#ibcon#about to write, iclass 6, count 2 2006.201.17:55:11.34#ibcon#wrote, iclass 6, count 2 2006.201.17:55:11.34#ibcon#about to read 3, iclass 6, count 2 2006.201.17:55:11.37#ibcon#read 3, iclass 6, count 2 2006.201.17:55:11.37#ibcon#about to read 4, iclass 6, count 2 2006.201.17:55:11.37#ibcon#read 4, iclass 6, count 2 2006.201.17:55:11.37#ibcon#about to read 5, iclass 6, count 2 2006.201.17:55:11.37#ibcon#read 5, iclass 6, count 2 2006.201.17:55:11.37#ibcon#about to read 6, iclass 6, count 2 2006.201.17:55:11.37#ibcon#read 6, iclass 6, count 2 2006.201.17:55:11.37#ibcon#end of sib2, iclass 6, count 2 2006.201.17:55:11.37#ibcon#*after write, iclass 6, count 2 2006.201.17:55:11.37#ibcon#*before return 0, iclass 6, count 2 2006.201.17:55:11.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:11.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:11.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.17:55:11.37#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:11.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:11.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:11.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:11.49#ibcon#enter wrdev, iclass 6, count 0 2006.201.17:55:11.49#ibcon#first serial, iclass 6, count 0 2006.201.17:55:11.49#ibcon#enter sib2, iclass 6, count 0 2006.201.17:55:11.49#ibcon#flushed, iclass 6, count 0 2006.201.17:55:11.49#ibcon#about to write, iclass 6, count 0 2006.201.17:55:11.49#ibcon#wrote, iclass 6, count 0 2006.201.17:55:11.49#ibcon#about to read 3, iclass 6, count 0 2006.201.17:55:11.51#ibcon#read 3, iclass 6, count 0 2006.201.17:55:11.51#ibcon#about to read 4, iclass 6, count 0 2006.201.17:55:11.51#ibcon#read 4, iclass 6, count 0 2006.201.17:55:11.51#ibcon#about to read 5, iclass 6, count 0 2006.201.17:55:11.51#ibcon#read 5, iclass 6, count 0 2006.201.17:55:11.51#ibcon#about to read 6, iclass 6, count 0 2006.201.17:55:11.51#ibcon#read 6, iclass 6, count 0 2006.201.17:55:11.51#ibcon#end of sib2, iclass 6, count 0 2006.201.17:55:11.51#ibcon#*mode == 0, iclass 6, count 0 2006.201.17:55:11.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.17:55:11.51#ibcon#[25=USB\r\n] 2006.201.17:55:11.51#ibcon#*before write, iclass 6, count 0 2006.201.17:55:11.51#ibcon#enter sib2, iclass 6, count 0 2006.201.17:55:11.51#ibcon#flushed, iclass 6, count 0 2006.201.17:55:11.51#ibcon#about to write, iclass 6, count 0 2006.201.17:55:11.51#ibcon#wrote, iclass 6, count 0 2006.201.17:55:11.51#ibcon#about to read 3, iclass 6, count 0 2006.201.17:55:11.54#ibcon#read 3, iclass 6, count 0 2006.201.17:55:11.54#ibcon#about to read 4, iclass 6, count 0 2006.201.17:55:11.54#ibcon#read 4, iclass 6, count 0 2006.201.17:55:11.54#ibcon#about to read 5, iclass 6, count 0 2006.201.17:55:11.54#ibcon#read 5, iclass 6, count 0 2006.201.17:55:11.54#ibcon#about to read 6, iclass 6, count 0 2006.201.17:55:11.54#ibcon#read 6, iclass 6, count 0 2006.201.17:55:11.54#ibcon#end of sib2, iclass 6, count 0 2006.201.17:55:11.54#ibcon#*after write, iclass 6, count 0 2006.201.17:55:11.54#ibcon#*before return 0, iclass 6, count 0 2006.201.17:55:11.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:11.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:11.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.17:55:11.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.17:55:11.54$vck44/valo=3,564.99 2006.201.17:55:11.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.17:55:11.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.17:55:11.54#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:11.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:11.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:11.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:11.54#ibcon#enter wrdev, iclass 10, count 0 2006.201.17:55:11.54#ibcon#first serial, iclass 10, count 0 2006.201.17:55:11.54#ibcon#enter sib2, iclass 10, count 0 2006.201.17:55:11.54#ibcon#flushed, iclass 10, count 0 2006.201.17:55:11.54#ibcon#about to write, iclass 10, count 0 2006.201.17:55:11.54#ibcon#wrote, iclass 10, count 0 2006.201.17:55:11.54#ibcon#about to read 3, iclass 10, count 0 2006.201.17:55:11.56#ibcon#read 3, iclass 10, count 0 2006.201.17:55:11.56#ibcon#about to read 4, iclass 10, count 0 2006.201.17:55:11.56#ibcon#read 4, iclass 10, count 0 2006.201.17:55:11.56#ibcon#about to read 5, iclass 10, count 0 2006.201.17:55:11.56#ibcon#read 5, iclass 10, count 0 2006.201.17:55:11.56#ibcon#about to read 6, iclass 10, count 0 2006.201.17:55:11.56#ibcon#read 6, iclass 10, count 0 2006.201.17:55:11.56#ibcon#end of sib2, iclass 10, count 0 2006.201.17:55:11.56#ibcon#*mode == 0, iclass 10, count 0 2006.201.17:55:11.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.17:55:11.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.17:55:11.56#ibcon#*before write, iclass 10, count 0 2006.201.17:55:11.56#ibcon#enter sib2, iclass 10, count 0 2006.201.17:55:11.56#ibcon#flushed, iclass 10, count 0 2006.201.17:55:11.56#ibcon#about to write, iclass 10, count 0 2006.201.17:55:11.56#ibcon#wrote, iclass 10, count 0 2006.201.17:55:11.56#ibcon#about to read 3, iclass 10, count 0 2006.201.17:55:11.61#ibcon#read 3, iclass 10, count 0 2006.201.17:55:11.61#ibcon#about to read 4, iclass 10, count 0 2006.201.17:55:11.61#ibcon#read 4, iclass 10, count 0 2006.201.17:55:11.61#ibcon#about to read 5, iclass 10, count 0 2006.201.17:55:11.61#ibcon#read 5, iclass 10, count 0 2006.201.17:55:11.61#ibcon#about to read 6, iclass 10, count 0 2006.201.17:55:11.61#ibcon#read 6, iclass 10, count 0 2006.201.17:55:11.61#ibcon#end of sib2, iclass 10, count 0 2006.201.17:55:11.61#ibcon#*after write, iclass 10, count 0 2006.201.17:55:11.61#ibcon#*before return 0, iclass 10, count 0 2006.201.17:55:11.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:11.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:11.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.17:55:11.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.17:55:11.61$vck44/va=3,8 2006.201.17:55:11.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.17:55:11.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.17:55:11.61#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:11.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:11.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:11.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:11.66#ibcon#enter wrdev, iclass 12, count 2 2006.201.17:55:11.66#ibcon#first serial, iclass 12, count 2 2006.201.17:55:11.66#ibcon#enter sib2, iclass 12, count 2 2006.201.17:55:11.66#ibcon#flushed, iclass 12, count 2 2006.201.17:55:11.66#ibcon#about to write, iclass 12, count 2 2006.201.17:55:11.66#ibcon#wrote, iclass 12, count 2 2006.201.17:55:11.66#ibcon#about to read 3, iclass 12, count 2 2006.201.17:55:11.68#ibcon#read 3, iclass 12, count 2 2006.201.17:55:11.68#ibcon#about to read 4, iclass 12, count 2 2006.201.17:55:11.68#ibcon#read 4, iclass 12, count 2 2006.201.17:55:11.68#ibcon#about to read 5, iclass 12, count 2 2006.201.17:55:11.68#ibcon#read 5, iclass 12, count 2 2006.201.17:55:11.68#ibcon#about to read 6, iclass 12, count 2 2006.201.17:55:11.68#ibcon#read 6, iclass 12, count 2 2006.201.17:55:11.68#ibcon#end of sib2, iclass 12, count 2 2006.201.17:55:11.68#ibcon#*mode == 0, iclass 12, count 2 2006.201.17:55:11.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.17:55:11.68#ibcon#[25=AT03-08\r\n] 2006.201.17:55:11.68#ibcon#*before write, iclass 12, count 2 2006.201.17:55:11.68#ibcon#enter sib2, iclass 12, count 2 2006.201.17:55:11.68#ibcon#flushed, iclass 12, count 2 2006.201.17:55:11.68#ibcon#about to write, iclass 12, count 2 2006.201.17:55:11.68#ibcon#wrote, iclass 12, count 2 2006.201.17:55:11.68#ibcon#about to read 3, iclass 12, count 2 2006.201.17:55:11.71#ibcon#read 3, iclass 12, count 2 2006.201.17:55:11.71#ibcon#about to read 4, iclass 12, count 2 2006.201.17:55:11.71#ibcon#read 4, iclass 12, count 2 2006.201.17:55:11.71#ibcon#about to read 5, iclass 12, count 2 2006.201.17:55:11.71#ibcon#read 5, iclass 12, count 2 2006.201.17:55:11.71#ibcon#about to read 6, iclass 12, count 2 2006.201.17:55:11.71#ibcon#read 6, iclass 12, count 2 2006.201.17:55:11.71#ibcon#end of sib2, iclass 12, count 2 2006.201.17:55:11.71#ibcon#*after write, iclass 12, count 2 2006.201.17:55:11.71#ibcon#*before return 0, iclass 12, count 2 2006.201.17:55:11.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:11.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:11.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.17:55:11.71#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:11.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:11.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:11.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:11.83#ibcon#enter wrdev, iclass 12, count 0 2006.201.17:55:11.83#ibcon#first serial, iclass 12, count 0 2006.201.17:55:11.83#ibcon#enter sib2, iclass 12, count 0 2006.201.17:55:11.83#ibcon#flushed, iclass 12, count 0 2006.201.17:55:11.83#ibcon#about to write, iclass 12, count 0 2006.201.17:55:11.83#ibcon#wrote, iclass 12, count 0 2006.201.17:55:11.83#ibcon#about to read 3, iclass 12, count 0 2006.201.17:55:11.85#ibcon#read 3, iclass 12, count 0 2006.201.17:55:11.85#ibcon#about to read 4, iclass 12, count 0 2006.201.17:55:11.85#ibcon#read 4, iclass 12, count 0 2006.201.17:55:11.85#ibcon#about to read 5, iclass 12, count 0 2006.201.17:55:11.85#ibcon#read 5, iclass 12, count 0 2006.201.17:55:11.85#ibcon#about to read 6, iclass 12, count 0 2006.201.17:55:11.85#ibcon#read 6, iclass 12, count 0 2006.201.17:55:11.85#ibcon#end of sib2, iclass 12, count 0 2006.201.17:55:11.85#ibcon#*mode == 0, iclass 12, count 0 2006.201.17:55:11.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.17:55:11.85#ibcon#[25=USB\r\n] 2006.201.17:55:11.85#ibcon#*before write, iclass 12, count 0 2006.201.17:55:11.85#ibcon#enter sib2, iclass 12, count 0 2006.201.17:55:11.85#ibcon#flushed, iclass 12, count 0 2006.201.17:55:11.85#ibcon#about to write, iclass 12, count 0 2006.201.17:55:11.85#ibcon#wrote, iclass 12, count 0 2006.201.17:55:11.85#ibcon#about to read 3, iclass 12, count 0 2006.201.17:55:11.88#ibcon#read 3, iclass 12, count 0 2006.201.17:55:11.88#ibcon#about to read 4, iclass 12, count 0 2006.201.17:55:11.88#ibcon#read 4, iclass 12, count 0 2006.201.17:55:11.88#ibcon#about to read 5, iclass 12, count 0 2006.201.17:55:11.88#ibcon#read 5, iclass 12, count 0 2006.201.17:55:11.88#ibcon#about to read 6, iclass 12, count 0 2006.201.17:55:11.88#ibcon#read 6, iclass 12, count 0 2006.201.17:55:11.88#ibcon#end of sib2, iclass 12, count 0 2006.201.17:55:11.88#ibcon#*after write, iclass 12, count 0 2006.201.17:55:11.88#ibcon#*before return 0, iclass 12, count 0 2006.201.17:55:11.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:11.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:11.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.17:55:11.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.17:55:11.88$vck44/valo=4,624.99 2006.201.17:55:11.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.17:55:11.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.17:55:11.88#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:11.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:11.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:11.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:11.88#ibcon#enter wrdev, iclass 14, count 0 2006.201.17:55:11.88#ibcon#first serial, iclass 14, count 0 2006.201.17:55:11.88#ibcon#enter sib2, iclass 14, count 0 2006.201.17:55:11.88#ibcon#flushed, iclass 14, count 0 2006.201.17:55:11.88#ibcon#about to write, iclass 14, count 0 2006.201.17:55:11.88#ibcon#wrote, iclass 14, count 0 2006.201.17:55:11.88#ibcon#about to read 3, iclass 14, count 0 2006.201.17:55:11.90#ibcon#read 3, iclass 14, count 0 2006.201.17:55:11.90#ibcon#about to read 4, iclass 14, count 0 2006.201.17:55:11.90#ibcon#read 4, iclass 14, count 0 2006.201.17:55:11.90#ibcon#about to read 5, iclass 14, count 0 2006.201.17:55:11.90#ibcon#read 5, iclass 14, count 0 2006.201.17:55:11.90#ibcon#about to read 6, iclass 14, count 0 2006.201.17:55:11.90#ibcon#read 6, iclass 14, count 0 2006.201.17:55:11.90#ibcon#end of sib2, iclass 14, count 0 2006.201.17:55:11.90#ibcon#*mode == 0, iclass 14, count 0 2006.201.17:55:11.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.17:55:11.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.17:55:11.90#ibcon#*before write, iclass 14, count 0 2006.201.17:55:11.90#ibcon#enter sib2, iclass 14, count 0 2006.201.17:55:11.90#ibcon#flushed, iclass 14, count 0 2006.201.17:55:11.90#ibcon#about to write, iclass 14, count 0 2006.201.17:55:11.90#ibcon#wrote, iclass 14, count 0 2006.201.17:55:11.90#ibcon#about to read 3, iclass 14, count 0 2006.201.17:55:11.95#ibcon#read 3, iclass 14, count 0 2006.201.17:55:11.95#ibcon#about to read 4, iclass 14, count 0 2006.201.17:55:11.95#ibcon#read 4, iclass 14, count 0 2006.201.17:55:11.95#ibcon#about to read 5, iclass 14, count 0 2006.201.17:55:11.95#ibcon#read 5, iclass 14, count 0 2006.201.17:55:11.95#ibcon#about to read 6, iclass 14, count 0 2006.201.17:55:11.95#ibcon#read 6, iclass 14, count 0 2006.201.17:55:11.95#ibcon#end of sib2, iclass 14, count 0 2006.201.17:55:11.95#ibcon#*after write, iclass 14, count 0 2006.201.17:55:11.95#ibcon#*before return 0, iclass 14, count 0 2006.201.17:55:11.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:11.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:11.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.17:55:11.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.17:55:11.95$vck44/va=4,7 2006.201.17:55:11.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.17:55:11.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.17:55:11.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:11.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:12.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:12.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:12.00#ibcon#enter wrdev, iclass 16, count 2 2006.201.17:55:12.00#ibcon#first serial, iclass 16, count 2 2006.201.17:55:12.00#ibcon#enter sib2, iclass 16, count 2 2006.201.17:55:12.00#ibcon#flushed, iclass 16, count 2 2006.201.17:55:12.00#ibcon#about to write, iclass 16, count 2 2006.201.17:55:12.00#ibcon#wrote, iclass 16, count 2 2006.201.17:55:12.00#ibcon#about to read 3, iclass 16, count 2 2006.201.17:55:12.02#ibcon#read 3, iclass 16, count 2 2006.201.17:55:12.02#ibcon#about to read 4, iclass 16, count 2 2006.201.17:55:12.02#ibcon#read 4, iclass 16, count 2 2006.201.17:55:12.02#ibcon#about to read 5, iclass 16, count 2 2006.201.17:55:12.02#ibcon#read 5, iclass 16, count 2 2006.201.17:55:12.02#ibcon#about to read 6, iclass 16, count 2 2006.201.17:55:12.02#ibcon#read 6, iclass 16, count 2 2006.201.17:55:12.02#ibcon#end of sib2, iclass 16, count 2 2006.201.17:55:12.02#ibcon#*mode == 0, iclass 16, count 2 2006.201.17:55:12.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.17:55:12.02#ibcon#[25=AT04-07\r\n] 2006.201.17:55:12.02#ibcon#*before write, iclass 16, count 2 2006.201.17:55:12.02#ibcon#enter sib2, iclass 16, count 2 2006.201.17:55:12.02#ibcon#flushed, iclass 16, count 2 2006.201.17:55:12.02#ibcon#about to write, iclass 16, count 2 2006.201.17:55:12.02#ibcon#wrote, iclass 16, count 2 2006.201.17:55:12.02#ibcon#about to read 3, iclass 16, count 2 2006.201.17:55:12.05#ibcon#read 3, iclass 16, count 2 2006.201.17:55:12.05#ibcon#about to read 4, iclass 16, count 2 2006.201.17:55:12.05#ibcon#read 4, iclass 16, count 2 2006.201.17:55:12.05#ibcon#about to read 5, iclass 16, count 2 2006.201.17:55:12.05#ibcon#read 5, iclass 16, count 2 2006.201.17:55:12.05#ibcon#about to read 6, iclass 16, count 2 2006.201.17:55:12.05#ibcon#read 6, iclass 16, count 2 2006.201.17:55:12.05#ibcon#end of sib2, iclass 16, count 2 2006.201.17:55:12.05#ibcon#*after write, iclass 16, count 2 2006.201.17:55:12.05#ibcon#*before return 0, iclass 16, count 2 2006.201.17:55:12.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:12.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:12.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.17:55:12.05#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:12.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:12.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:12.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:12.17#ibcon#enter wrdev, iclass 16, count 0 2006.201.17:55:12.17#ibcon#first serial, iclass 16, count 0 2006.201.17:55:12.17#ibcon#enter sib2, iclass 16, count 0 2006.201.17:55:12.17#ibcon#flushed, iclass 16, count 0 2006.201.17:55:12.17#ibcon#about to write, iclass 16, count 0 2006.201.17:55:12.17#ibcon#wrote, iclass 16, count 0 2006.201.17:55:12.17#ibcon#about to read 3, iclass 16, count 0 2006.201.17:55:12.19#ibcon#read 3, iclass 16, count 0 2006.201.17:55:12.19#ibcon#about to read 4, iclass 16, count 0 2006.201.17:55:12.19#ibcon#read 4, iclass 16, count 0 2006.201.17:55:12.19#ibcon#about to read 5, iclass 16, count 0 2006.201.17:55:12.19#ibcon#read 5, iclass 16, count 0 2006.201.17:55:12.19#ibcon#about to read 6, iclass 16, count 0 2006.201.17:55:12.19#ibcon#read 6, iclass 16, count 0 2006.201.17:55:12.19#ibcon#end of sib2, iclass 16, count 0 2006.201.17:55:12.19#ibcon#*mode == 0, iclass 16, count 0 2006.201.17:55:12.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.17:55:12.19#ibcon#[25=USB\r\n] 2006.201.17:55:12.19#ibcon#*before write, iclass 16, count 0 2006.201.17:55:12.19#ibcon#enter sib2, iclass 16, count 0 2006.201.17:55:12.19#ibcon#flushed, iclass 16, count 0 2006.201.17:55:12.19#ibcon#about to write, iclass 16, count 0 2006.201.17:55:12.19#ibcon#wrote, iclass 16, count 0 2006.201.17:55:12.19#ibcon#about to read 3, iclass 16, count 0 2006.201.17:55:12.22#ibcon#read 3, iclass 16, count 0 2006.201.17:55:12.22#ibcon#about to read 4, iclass 16, count 0 2006.201.17:55:12.22#ibcon#read 4, iclass 16, count 0 2006.201.17:55:12.22#ibcon#about to read 5, iclass 16, count 0 2006.201.17:55:12.22#ibcon#read 5, iclass 16, count 0 2006.201.17:55:12.22#ibcon#about to read 6, iclass 16, count 0 2006.201.17:55:12.22#ibcon#read 6, iclass 16, count 0 2006.201.17:55:12.22#ibcon#end of sib2, iclass 16, count 0 2006.201.17:55:12.22#ibcon#*after write, iclass 16, count 0 2006.201.17:55:12.22#ibcon#*before return 0, iclass 16, count 0 2006.201.17:55:12.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:12.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:12.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.17:55:12.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.17:55:12.22$vck44/valo=5,734.99 2006.201.17:55:12.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.17:55:12.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.17:55:12.22#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:12.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:12.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:12.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:12.22#ibcon#enter wrdev, iclass 18, count 0 2006.201.17:55:12.22#ibcon#first serial, iclass 18, count 0 2006.201.17:55:12.22#ibcon#enter sib2, iclass 18, count 0 2006.201.17:55:12.22#ibcon#flushed, iclass 18, count 0 2006.201.17:55:12.22#ibcon#about to write, iclass 18, count 0 2006.201.17:55:12.22#ibcon#wrote, iclass 18, count 0 2006.201.17:55:12.22#ibcon#about to read 3, iclass 18, count 0 2006.201.17:55:12.24#ibcon#read 3, iclass 18, count 0 2006.201.17:55:12.24#ibcon#about to read 4, iclass 18, count 0 2006.201.17:55:12.24#ibcon#read 4, iclass 18, count 0 2006.201.17:55:12.24#ibcon#about to read 5, iclass 18, count 0 2006.201.17:55:12.24#ibcon#read 5, iclass 18, count 0 2006.201.17:55:12.24#ibcon#about to read 6, iclass 18, count 0 2006.201.17:55:12.24#ibcon#read 6, iclass 18, count 0 2006.201.17:55:12.24#ibcon#end of sib2, iclass 18, count 0 2006.201.17:55:12.24#ibcon#*mode == 0, iclass 18, count 0 2006.201.17:55:12.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.17:55:12.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.17:55:12.24#ibcon#*before write, iclass 18, count 0 2006.201.17:55:12.24#ibcon#enter sib2, iclass 18, count 0 2006.201.17:55:12.24#ibcon#flushed, iclass 18, count 0 2006.201.17:55:12.24#ibcon#about to write, iclass 18, count 0 2006.201.17:55:12.24#ibcon#wrote, iclass 18, count 0 2006.201.17:55:12.24#ibcon#about to read 3, iclass 18, count 0 2006.201.17:55:12.28#ibcon#read 3, iclass 18, count 0 2006.201.17:55:12.28#ibcon#about to read 4, iclass 18, count 0 2006.201.17:55:12.28#ibcon#read 4, iclass 18, count 0 2006.201.17:55:12.28#ibcon#about to read 5, iclass 18, count 0 2006.201.17:55:12.28#ibcon#read 5, iclass 18, count 0 2006.201.17:55:12.28#ibcon#about to read 6, iclass 18, count 0 2006.201.17:55:12.28#ibcon#read 6, iclass 18, count 0 2006.201.17:55:12.28#ibcon#end of sib2, iclass 18, count 0 2006.201.17:55:12.28#ibcon#*after write, iclass 18, count 0 2006.201.17:55:12.28#ibcon#*before return 0, iclass 18, count 0 2006.201.17:55:12.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:12.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:12.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.17:55:12.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.17:55:12.28$vck44/va=5,4 2006.201.17:55:12.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.17:55:12.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.17:55:12.28#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:12.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:12.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:12.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:12.34#ibcon#enter wrdev, iclass 20, count 2 2006.201.17:55:12.34#ibcon#first serial, iclass 20, count 2 2006.201.17:55:12.34#ibcon#enter sib2, iclass 20, count 2 2006.201.17:55:12.34#ibcon#flushed, iclass 20, count 2 2006.201.17:55:12.34#ibcon#about to write, iclass 20, count 2 2006.201.17:55:12.34#ibcon#wrote, iclass 20, count 2 2006.201.17:55:12.34#ibcon#about to read 3, iclass 20, count 2 2006.201.17:55:12.36#ibcon#read 3, iclass 20, count 2 2006.201.17:55:12.36#ibcon#about to read 4, iclass 20, count 2 2006.201.17:55:12.36#ibcon#read 4, iclass 20, count 2 2006.201.17:55:12.36#ibcon#about to read 5, iclass 20, count 2 2006.201.17:55:12.36#ibcon#read 5, iclass 20, count 2 2006.201.17:55:12.36#ibcon#about to read 6, iclass 20, count 2 2006.201.17:55:12.36#ibcon#read 6, iclass 20, count 2 2006.201.17:55:12.36#ibcon#end of sib2, iclass 20, count 2 2006.201.17:55:12.36#ibcon#*mode == 0, iclass 20, count 2 2006.201.17:55:12.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.17:55:12.36#ibcon#[25=AT05-04\r\n] 2006.201.17:55:12.36#ibcon#*before write, iclass 20, count 2 2006.201.17:55:12.36#ibcon#enter sib2, iclass 20, count 2 2006.201.17:55:12.36#ibcon#flushed, iclass 20, count 2 2006.201.17:55:12.36#ibcon#about to write, iclass 20, count 2 2006.201.17:55:12.36#ibcon#wrote, iclass 20, count 2 2006.201.17:55:12.36#ibcon#about to read 3, iclass 20, count 2 2006.201.17:55:12.39#ibcon#read 3, iclass 20, count 2 2006.201.17:55:12.39#ibcon#about to read 4, iclass 20, count 2 2006.201.17:55:12.39#ibcon#read 4, iclass 20, count 2 2006.201.17:55:12.39#ibcon#about to read 5, iclass 20, count 2 2006.201.17:55:12.39#ibcon#read 5, iclass 20, count 2 2006.201.17:55:12.39#ibcon#about to read 6, iclass 20, count 2 2006.201.17:55:12.39#ibcon#read 6, iclass 20, count 2 2006.201.17:55:12.39#ibcon#end of sib2, iclass 20, count 2 2006.201.17:55:12.39#ibcon#*after write, iclass 20, count 2 2006.201.17:55:12.39#ibcon#*before return 0, iclass 20, count 2 2006.201.17:55:12.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:12.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:12.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.17:55:12.39#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:12.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:12.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:12.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:12.51#ibcon#enter wrdev, iclass 20, count 0 2006.201.17:55:12.51#ibcon#first serial, iclass 20, count 0 2006.201.17:55:12.51#ibcon#enter sib2, iclass 20, count 0 2006.201.17:55:12.51#ibcon#flushed, iclass 20, count 0 2006.201.17:55:12.51#ibcon#about to write, iclass 20, count 0 2006.201.17:55:12.51#ibcon#wrote, iclass 20, count 0 2006.201.17:55:12.51#ibcon#about to read 3, iclass 20, count 0 2006.201.17:55:12.53#ibcon#read 3, iclass 20, count 0 2006.201.17:55:12.53#ibcon#about to read 4, iclass 20, count 0 2006.201.17:55:12.53#ibcon#read 4, iclass 20, count 0 2006.201.17:55:12.53#ibcon#about to read 5, iclass 20, count 0 2006.201.17:55:12.53#ibcon#read 5, iclass 20, count 0 2006.201.17:55:12.53#ibcon#about to read 6, iclass 20, count 0 2006.201.17:55:12.53#ibcon#read 6, iclass 20, count 0 2006.201.17:55:12.53#ibcon#end of sib2, iclass 20, count 0 2006.201.17:55:12.53#ibcon#*mode == 0, iclass 20, count 0 2006.201.17:55:12.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.17:55:12.53#ibcon#[25=USB\r\n] 2006.201.17:55:12.53#ibcon#*before write, iclass 20, count 0 2006.201.17:55:12.53#ibcon#enter sib2, iclass 20, count 0 2006.201.17:55:12.53#ibcon#flushed, iclass 20, count 0 2006.201.17:55:12.53#ibcon#about to write, iclass 20, count 0 2006.201.17:55:12.53#ibcon#wrote, iclass 20, count 0 2006.201.17:55:12.53#ibcon#about to read 3, iclass 20, count 0 2006.201.17:55:12.56#ibcon#read 3, iclass 20, count 0 2006.201.17:55:12.56#ibcon#about to read 4, iclass 20, count 0 2006.201.17:55:12.56#ibcon#read 4, iclass 20, count 0 2006.201.17:55:12.56#ibcon#about to read 5, iclass 20, count 0 2006.201.17:55:12.56#ibcon#read 5, iclass 20, count 0 2006.201.17:55:12.56#ibcon#about to read 6, iclass 20, count 0 2006.201.17:55:12.56#ibcon#read 6, iclass 20, count 0 2006.201.17:55:12.56#ibcon#end of sib2, iclass 20, count 0 2006.201.17:55:12.56#ibcon#*after write, iclass 20, count 0 2006.201.17:55:12.56#ibcon#*before return 0, iclass 20, count 0 2006.201.17:55:12.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:12.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:12.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.17:55:12.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.17:55:12.56$vck44/valo=6,814.99 2006.201.17:55:12.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.17:55:12.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.17:55:12.56#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:12.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:12.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:12.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:12.56#ibcon#enter wrdev, iclass 22, count 0 2006.201.17:55:12.56#ibcon#first serial, iclass 22, count 0 2006.201.17:55:12.56#ibcon#enter sib2, iclass 22, count 0 2006.201.17:55:12.56#ibcon#flushed, iclass 22, count 0 2006.201.17:55:12.56#ibcon#about to write, iclass 22, count 0 2006.201.17:55:12.56#ibcon#wrote, iclass 22, count 0 2006.201.17:55:12.56#ibcon#about to read 3, iclass 22, count 0 2006.201.17:55:12.58#ibcon#read 3, iclass 22, count 0 2006.201.17:55:12.58#ibcon#about to read 4, iclass 22, count 0 2006.201.17:55:12.58#ibcon#read 4, iclass 22, count 0 2006.201.17:55:12.58#ibcon#about to read 5, iclass 22, count 0 2006.201.17:55:12.58#ibcon#read 5, iclass 22, count 0 2006.201.17:55:12.58#ibcon#about to read 6, iclass 22, count 0 2006.201.17:55:12.58#ibcon#read 6, iclass 22, count 0 2006.201.17:55:12.58#ibcon#end of sib2, iclass 22, count 0 2006.201.17:55:12.58#ibcon#*mode == 0, iclass 22, count 0 2006.201.17:55:12.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.17:55:12.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.17:55:12.58#ibcon#*before write, iclass 22, count 0 2006.201.17:55:12.58#ibcon#enter sib2, iclass 22, count 0 2006.201.17:55:12.58#ibcon#flushed, iclass 22, count 0 2006.201.17:55:12.58#ibcon#about to write, iclass 22, count 0 2006.201.17:55:12.58#ibcon#wrote, iclass 22, count 0 2006.201.17:55:12.58#ibcon#about to read 3, iclass 22, count 0 2006.201.17:55:12.62#ibcon#read 3, iclass 22, count 0 2006.201.17:55:12.62#ibcon#about to read 4, iclass 22, count 0 2006.201.17:55:12.62#ibcon#read 4, iclass 22, count 0 2006.201.17:55:12.62#ibcon#about to read 5, iclass 22, count 0 2006.201.17:55:12.62#ibcon#read 5, iclass 22, count 0 2006.201.17:55:12.62#ibcon#about to read 6, iclass 22, count 0 2006.201.17:55:12.62#ibcon#read 6, iclass 22, count 0 2006.201.17:55:12.62#ibcon#end of sib2, iclass 22, count 0 2006.201.17:55:12.62#ibcon#*after write, iclass 22, count 0 2006.201.17:55:12.62#ibcon#*before return 0, iclass 22, count 0 2006.201.17:55:12.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:12.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:12.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.17:55:12.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.17:55:12.62$vck44/va=6,5 2006.201.17:55:12.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.17:55:12.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.17:55:12.62#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:12.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:12.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:12.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:12.68#ibcon#enter wrdev, iclass 24, count 2 2006.201.17:55:12.68#ibcon#first serial, iclass 24, count 2 2006.201.17:55:12.68#ibcon#enter sib2, iclass 24, count 2 2006.201.17:55:12.68#ibcon#flushed, iclass 24, count 2 2006.201.17:55:12.68#ibcon#about to write, iclass 24, count 2 2006.201.17:55:12.68#ibcon#wrote, iclass 24, count 2 2006.201.17:55:12.68#ibcon#about to read 3, iclass 24, count 2 2006.201.17:55:12.70#ibcon#read 3, iclass 24, count 2 2006.201.17:55:12.70#ibcon#about to read 4, iclass 24, count 2 2006.201.17:55:12.70#ibcon#read 4, iclass 24, count 2 2006.201.17:55:12.70#ibcon#about to read 5, iclass 24, count 2 2006.201.17:55:12.70#ibcon#read 5, iclass 24, count 2 2006.201.17:55:12.70#ibcon#about to read 6, iclass 24, count 2 2006.201.17:55:12.70#ibcon#read 6, iclass 24, count 2 2006.201.17:55:12.70#ibcon#end of sib2, iclass 24, count 2 2006.201.17:55:12.70#ibcon#*mode == 0, iclass 24, count 2 2006.201.17:55:12.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.17:55:12.70#ibcon#[25=AT06-05\r\n] 2006.201.17:55:12.70#ibcon#*before write, iclass 24, count 2 2006.201.17:55:12.70#ibcon#enter sib2, iclass 24, count 2 2006.201.17:55:12.70#ibcon#flushed, iclass 24, count 2 2006.201.17:55:12.70#ibcon#about to write, iclass 24, count 2 2006.201.17:55:12.70#ibcon#wrote, iclass 24, count 2 2006.201.17:55:12.70#ibcon#about to read 3, iclass 24, count 2 2006.201.17:55:12.73#ibcon#read 3, iclass 24, count 2 2006.201.17:55:12.73#ibcon#about to read 4, iclass 24, count 2 2006.201.17:55:12.73#ibcon#read 4, iclass 24, count 2 2006.201.17:55:12.73#ibcon#about to read 5, iclass 24, count 2 2006.201.17:55:12.73#ibcon#read 5, iclass 24, count 2 2006.201.17:55:12.73#ibcon#about to read 6, iclass 24, count 2 2006.201.17:55:12.73#ibcon#read 6, iclass 24, count 2 2006.201.17:55:12.73#ibcon#end of sib2, iclass 24, count 2 2006.201.17:55:12.73#ibcon#*after write, iclass 24, count 2 2006.201.17:55:12.73#ibcon#*before return 0, iclass 24, count 2 2006.201.17:55:12.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:12.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:12.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.17:55:12.73#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:12.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:12.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:12.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:12.85#ibcon#enter wrdev, iclass 24, count 0 2006.201.17:55:12.85#ibcon#first serial, iclass 24, count 0 2006.201.17:55:12.85#ibcon#enter sib2, iclass 24, count 0 2006.201.17:55:12.85#ibcon#flushed, iclass 24, count 0 2006.201.17:55:12.85#ibcon#about to write, iclass 24, count 0 2006.201.17:55:12.85#ibcon#wrote, iclass 24, count 0 2006.201.17:55:12.85#ibcon#about to read 3, iclass 24, count 0 2006.201.17:55:12.87#ibcon#read 3, iclass 24, count 0 2006.201.17:55:12.87#ibcon#about to read 4, iclass 24, count 0 2006.201.17:55:12.87#ibcon#read 4, iclass 24, count 0 2006.201.17:55:12.87#ibcon#about to read 5, iclass 24, count 0 2006.201.17:55:12.87#ibcon#read 5, iclass 24, count 0 2006.201.17:55:12.87#ibcon#about to read 6, iclass 24, count 0 2006.201.17:55:12.87#ibcon#read 6, iclass 24, count 0 2006.201.17:55:12.87#ibcon#end of sib2, iclass 24, count 0 2006.201.17:55:12.87#ibcon#*mode == 0, iclass 24, count 0 2006.201.17:55:12.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.17:55:12.87#ibcon#[25=USB\r\n] 2006.201.17:55:12.87#ibcon#*before write, iclass 24, count 0 2006.201.17:55:12.87#ibcon#enter sib2, iclass 24, count 0 2006.201.17:55:12.87#ibcon#flushed, iclass 24, count 0 2006.201.17:55:12.87#ibcon#about to write, iclass 24, count 0 2006.201.17:55:12.87#ibcon#wrote, iclass 24, count 0 2006.201.17:55:12.87#ibcon#about to read 3, iclass 24, count 0 2006.201.17:55:12.90#ibcon#read 3, iclass 24, count 0 2006.201.17:55:12.90#ibcon#about to read 4, iclass 24, count 0 2006.201.17:55:12.90#ibcon#read 4, iclass 24, count 0 2006.201.17:55:12.90#ibcon#about to read 5, iclass 24, count 0 2006.201.17:55:12.90#ibcon#read 5, iclass 24, count 0 2006.201.17:55:12.90#ibcon#about to read 6, iclass 24, count 0 2006.201.17:55:12.90#ibcon#read 6, iclass 24, count 0 2006.201.17:55:12.90#ibcon#end of sib2, iclass 24, count 0 2006.201.17:55:12.90#ibcon#*after write, iclass 24, count 0 2006.201.17:55:12.90#ibcon#*before return 0, iclass 24, count 0 2006.201.17:55:12.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:12.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:12.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.17:55:12.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.17:55:12.90$vck44/valo=7,864.99 2006.201.17:55:12.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.17:55:12.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.17:55:12.90#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:12.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:55:12.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:55:12.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:55:12.90#ibcon#enter wrdev, iclass 26, count 0 2006.201.17:55:12.90#ibcon#first serial, iclass 26, count 0 2006.201.17:55:12.90#ibcon#enter sib2, iclass 26, count 0 2006.201.17:55:12.90#ibcon#flushed, iclass 26, count 0 2006.201.17:55:12.90#ibcon#about to write, iclass 26, count 0 2006.201.17:55:12.90#ibcon#wrote, iclass 26, count 0 2006.201.17:55:12.90#ibcon#about to read 3, iclass 26, count 0 2006.201.17:55:12.92#ibcon#read 3, iclass 26, count 0 2006.201.17:55:12.92#ibcon#about to read 4, iclass 26, count 0 2006.201.17:55:12.92#ibcon#read 4, iclass 26, count 0 2006.201.17:55:12.92#ibcon#about to read 5, iclass 26, count 0 2006.201.17:55:12.92#ibcon#read 5, iclass 26, count 0 2006.201.17:55:12.92#ibcon#about to read 6, iclass 26, count 0 2006.201.17:55:12.92#ibcon#read 6, iclass 26, count 0 2006.201.17:55:12.92#ibcon#end of sib2, iclass 26, count 0 2006.201.17:55:12.92#ibcon#*mode == 0, iclass 26, count 0 2006.201.17:55:12.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.17:55:12.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.17:55:12.92#ibcon#*before write, iclass 26, count 0 2006.201.17:55:12.92#ibcon#enter sib2, iclass 26, count 0 2006.201.17:55:12.92#ibcon#flushed, iclass 26, count 0 2006.201.17:55:12.92#ibcon#about to write, iclass 26, count 0 2006.201.17:55:12.92#ibcon#wrote, iclass 26, count 0 2006.201.17:55:12.92#ibcon#about to read 3, iclass 26, count 0 2006.201.17:55:12.97#ibcon#read 3, iclass 26, count 0 2006.201.17:55:12.97#ibcon#about to read 4, iclass 26, count 0 2006.201.17:55:12.97#ibcon#read 4, iclass 26, count 0 2006.201.17:55:12.97#ibcon#about to read 5, iclass 26, count 0 2006.201.17:55:12.97#ibcon#read 5, iclass 26, count 0 2006.201.17:55:12.97#ibcon#about to read 6, iclass 26, count 0 2006.201.17:55:12.97#ibcon#read 6, iclass 26, count 0 2006.201.17:55:12.97#ibcon#end of sib2, iclass 26, count 0 2006.201.17:55:12.97#ibcon#*after write, iclass 26, count 0 2006.201.17:55:12.97#ibcon#*before return 0, iclass 26, count 0 2006.201.17:55:12.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:55:12.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.17:55:12.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.17:55:12.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.17:55:12.97$vck44/va=7,5 2006.201.17:55:12.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.17:55:12.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.17:55:12.97#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:12.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.17:55:13.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.17:55:13.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.17:55:13.02#ibcon#enter wrdev, iclass 28, count 2 2006.201.17:55:13.02#ibcon#first serial, iclass 28, count 2 2006.201.17:55:13.02#ibcon#enter sib2, iclass 28, count 2 2006.201.17:55:13.02#ibcon#flushed, iclass 28, count 2 2006.201.17:55:13.02#ibcon#about to write, iclass 28, count 2 2006.201.17:55:13.02#ibcon#wrote, iclass 28, count 2 2006.201.17:55:13.02#ibcon#about to read 3, iclass 28, count 2 2006.201.17:55:13.04#ibcon#read 3, iclass 28, count 2 2006.201.17:55:13.04#ibcon#about to read 4, iclass 28, count 2 2006.201.17:55:13.04#ibcon#read 4, iclass 28, count 2 2006.201.17:55:13.04#ibcon#about to read 5, iclass 28, count 2 2006.201.17:55:13.04#ibcon#read 5, iclass 28, count 2 2006.201.17:55:13.04#ibcon#about to read 6, iclass 28, count 2 2006.201.17:55:13.04#ibcon#read 6, iclass 28, count 2 2006.201.17:55:13.04#ibcon#end of sib2, iclass 28, count 2 2006.201.17:55:13.04#ibcon#*mode == 0, iclass 28, count 2 2006.201.17:55:13.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.17:55:13.04#ibcon#[25=AT07-05\r\n] 2006.201.17:55:13.04#ibcon#*before write, iclass 28, count 2 2006.201.17:55:13.04#ibcon#enter sib2, iclass 28, count 2 2006.201.17:55:13.04#ibcon#flushed, iclass 28, count 2 2006.201.17:55:13.04#ibcon#about to write, iclass 28, count 2 2006.201.17:55:13.04#ibcon#wrote, iclass 28, count 2 2006.201.17:55:13.04#ibcon#about to read 3, iclass 28, count 2 2006.201.17:55:13.07#ibcon#read 3, iclass 28, count 2 2006.201.17:55:13.07#ibcon#about to read 4, iclass 28, count 2 2006.201.17:55:13.07#ibcon#read 4, iclass 28, count 2 2006.201.17:55:13.07#ibcon#about to read 5, iclass 28, count 2 2006.201.17:55:13.07#ibcon#read 5, iclass 28, count 2 2006.201.17:55:13.07#ibcon#about to read 6, iclass 28, count 2 2006.201.17:55:13.07#ibcon#read 6, iclass 28, count 2 2006.201.17:55:13.07#ibcon#end of sib2, iclass 28, count 2 2006.201.17:55:13.07#ibcon#*after write, iclass 28, count 2 2006.201.17:55:13.07#ibcon#*before return 0, iclass 28, count 2 2006.201.17:55:13.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.17:55:13.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.17:55:13.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.17:55:13.07#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:13.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.17:55:13.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.17:55:13.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.17:55:13.19#ibcon#enter wrdev, iclass 28, count 0 2006.201.17:55:13.19#ibcon#first serial, iclass 28, count 0 2006.201.17:55:13.19#ibcon#enter sib2, iclass 28, count 0 2006.201.17:55:13.19#ibcon#flushed, iclass 28, count 0 2006.201.17:55:13.19#ibcon#about to write, iclass 28, count 0 2006.201.17:55:13.19#ibcon#wrote, iclass 28, count 0 2006.201.17:55:13.19#ibcon#about to read 3, iclass 28, count 0 2006.201.17:55:13.21#ibcon#read 3, iclass 28, count 0 2006.201.17:55:13.21#ibcon#about to read 4, iclass 28, count 0 2006.201.17:55:13.21#ibcon#read 4, iclass 28, count 0 2006.201.17:55:13.21#ibcon#about to read 5, iclass 28, count 0 2006.201.17:55:13.21#ibcon#read 5, iclass 28, count 0 2006.201.17:55:13.21#ibcon#about to read 6, iclass 28, count 0 2006.201.17:55:13.21#ibcon#read 6, iclass 28, count 0 2006.201.17:55:13.21#ibcon#end of sib2, iclass 28, count 0 2006.201.17:55:13.21#ibcon#*mode == 0, iclass 28, count 0 2006.201.17:55:13.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.17:55:13.21#ibcon#[25=USB\r\n] 2006.201.17:55:13.21#ibcon#*before write, iclass 28, count 0 2006.201.17:55:13.21#ibcon#enter sib2, iclass 28, count 0 2006.201.17:55:13.21#ibcon#flushed, iclass 28, count 0 2006.201.17:55:13.21#ibcon#about to write, iclass 28, count 0 2006.201.17:55:13.21#ibcon#wrote, iclass 28, count 0 2006.201.17:55:13.21#ibcon#about to read 3, iclass 28, count 0 2006.201.17:55:13.24#ibcon#read 3, iclass 28, count 0 2006.201.17:55:13.24#ibcon#about to read 4, iclass 28, count 0 2006.201.17:55:13.24#ibcon#read 4, iclass 28, count 0 2006.201.17:55:13.24#ibcon#about to read 5, iclass 28, count 0 2006.201.17:55:13.24#ibcon#read 5, iclass 28, count 0 2006.201.17:55:13.24#ibcon#about to read 6, iclass 28, count 0 2006.201.17:55:13.24#ibcon#read 6, iclass 28, count 0 2006.201.17:55:13.24#ibcon#end of sib2, iclass 28, count 0 2006.201.17:55:13.24#ibcon#*after write, iclass 28, count 0 2006.201.17:55:13.24#ibcon#*before return 0, iclass 28, count 0 2006.201.17:55:13.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.17:55:13.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.17:55:13.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.17:55:13.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.17:55:13.24$vck44/valo=8,884.99 2006.201.17:55:13.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.17:55:13.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.17:55:13.24#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:13.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:13.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:13.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:13.24#ibcon#enter wrdev, iclass 30, count 0 2006.201.17:55:13.24#ibcon#first serial, iclass 30, count 0 2006.201.17:55:13.24#ibcon#enter sib2, iclass 30, count 0 2006.201.17:55:13.24#ibcon#flushed, iclass 30, count 0 2006.201.17:55:13.24#ibcon#about to write, iclass 30, count 0 2006.201.17:55:13.24#ibcon#wrote, iclass 30, count 0 2006.201.17:55:13.24#ibcon#about to read 3, iclass 30, count 0 2006.201.17:55:13.26#ibcon#read 3, iclass 30, count 0 2006.201.17:55:13.26#ibcon#about to read 4, iclass 30, count 0 2006.201.17:55:13.26#ibcon#read 4, iclass 30, count 0 2006.201.17:55:13.26#ibcon#about to read 5, iclass 30, count 0 2006.201.17:55:13.26#ibcon#read 5, iclass 30, count 0 2006.201.17:55:13.26#ibcon#about to read 6, iclass 30, count 0 2006.201.17:55:13.26#ibcon#read 6, iclass 30, count 0 2006.201.17:55:13.26#ibcon#end of sib2, iclass 30, count 0 2006.201.17:55:13.26#ibcon#*mode == 0, iclass 30, count 0 2006.201.17:55:13.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.17:55:13.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.17:55:13.26#ibcon#*before write, iclass 30, count 0 2006.201.17:55:13.26#ibcon#enter sib2, iclass 30, count 0 2006.201.17:55:13.26#ibcon#flushed, iclass 30, count 0 2006.201.17:55:13.26#ibcon#about to write, iclass 30, count 0 2006.201.17:55:13.26#ibcon#wrote, iclass 30, count 0 2006.201.17:55:13.26#ibcon#about to read 3, iclass 30, count 0 2006.201.17:55:13.30#ibcon#read 3, iclass 30, count 0 2006.201.17:55:13.30#ibcon#about to read 4, iclass 30, count 0 2006.201.17:55:13.30#ibcon#read 4, iclass 30, count 0 2006.201.17:55:13.30#ibcon#about to read 5, iclass 30, count 0 2006.201.17:55:13.30#ibcon#read 5, iclass 30, count 0 2006.201.17:55:13.30#ibcon#about to read 6, iclass 30, count 0 2006.201.17:55:13.30#ibcon#read 6, iclass 30, count 0 2006.201.17:55:13.30#ibcon#end of sib2, iclass 30, count 0 2006.201.17:55:13.30#ibcon#*after write, iclass 30, count 0 2006.201.17:55:13.30#ibcon#*before return 0, iclass 30, count 0 2006.201.17:55:13.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:13.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:13.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.17:55:13.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.17:55:13.30$vck44/va=8,4 2006.201.17:55:13.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.17:55:13.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.17:55:13.30#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:13.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:13.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:13.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:13.36#ibcon#enter wrdev, iclass 32, count 2 2006.201.17:55:13.36#ibcon#first serial, iclass 32, count 2 2006.201.17:55:13.36#ibcon#enter sib2, iclass 32, count 2 2006.201.17:55:13.36#ibcon#flushed, iclass 32, count 2 2006.201.17:55:13.36#ibcon#about to write, iclass 32, count 2 2006.201.17:55:13.36#ibcon#wrote, iclass 32, count 2 2006.201.17:55:13.36#ibcon#about to read 3, iclass 32, count 2 2006.201.17:55:13.38#ibcon#read 3, iclass 32, count 2 2006.201.17:55:13.38#ibcon#about to read 4, iclass 32, count 2 2006.201.17:55:13.38#ibcon#read 4, iclass 32, count 2 2006.201.17:55:13.38#ibcon#about to read 5, iclass 32, count 2 2006.201.17:55:13.38#ibcon#read 5, iclass 32, count 2 2006.201.17:55:13.38#ibcon#about to read 6, iclass 32, count 2 2006.201.17:55:13.38#ibcon#read 6, iclass 32, count 2 2006.201.17:55:13.38#ibcon#end of sib2, iclass 32, count 2 2006.201.17:55:13.38#ibcon#*mode == 0, iclass 32, count 2 2006.201.17:55:13.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.17:55:13.38#ibcon#[25=AT08-04\r\n] 2006.201.17:55:13.38#ibcon#*before write, iclass 32, count 2 2006.201.17:55:13.38#ibcon#enter sib2, iclass 32, count 2 2006.201.17:55:13.38#ibcon#flushed, iclass 32, count 2 2006.201.17:55:13.38#ibcon#about to write, iclass 32, count 2 2006.201.17:55:13.38#ibcon#wrote, iclass 32, count 2 2006.201.17:55:13.38#ibcon#about to read 3, iclass 32, count 2 2006.201.17:55:13.41#ibcon#read 3, iclass 32, count 2 2006.201.17:55:13.41#ibcon#about to read 4, iclass 32, count 2 2006.201.17:55:13.41#ibcon#read 4, iclass 32, count 2 2006.201.17:55:13.41#ibcon#about to read 5, iclass 32, count 2 2006.201.17:55:13.41#ibcon#read 5, iclass 32, count 2 2006.201.17:55:13.41#ibcon#about to read 6, iclass 32, count 2 2006.201.17:55:13.41#ibcon#read 6, iclass 32, count 2 2006.201.17:55:13.41#ibcon#end of sib2, iclass 32, count 2 2006.201.17:55:13.41#ibcon#*after write, iclass 32, count 2 2006.201.17:55:13.41#ibcon#*before return 0, iclass 32, count 2 2006.201.17:55:13.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:13.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:13.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.17:55:13.41#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:13.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:13.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:13.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:13.53#ibcon#enter wrdev, iclass 32, count 0 2006.201.17:55:13.53#ibcon#first serial, iclass 32, count 0 2006.201.17:55:13.53#ibcon#enter sib2, iclass 32, count 0 2006.201.17:55:13.53#ibcon#flushed, iclass 32, count 0 2006.201.17:55:13.53#ibcon#about to write, iclass 32, count 0 2006.201.17:55:13.53#ibcon#wrote, iclass 32, count 0 2006.201.17:55:13.53#ibcon#about to read 3, iclass 32, count 0 2006.201.17:55:13.55#ibcon#read 3, iclass 32, count 0 2006.201.17:55:13.55#ibcon#about to read 4, iclass 32, count 0 2006.201.17:55:13.55#ibcon#read 4, iclass 32, count 0 2006.201.17:55:13.55#ibcon#about to read 5, iclass 32, count 0 2006.201.17:55:13.55#ibcon#read 5, iclass 32, count 0 2006.201.17:55:13.55#ibcon#about to read 6, iclass 32, count 0 2006.201.17:55:13.55#ibcon#read 6, iclass 32, count 0 2006.201.17:55:13.55#ibcon#end of sib2, iclass 32, count 0 2006.201.17:55:13.55#ibcon#*mode == 0, iclass 32, count 0 2006.201.17:55:13.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.17:55:13.55#ibcon#[25=USB\r\n] 2006.201.17:55:13.55#ibcon#*before write, iclass 32, count 0 2006.201.17:55:13.55#ibcon#enter sib2, iclass 32, count 0 2006.201.17:55:13.55#ibcon#flushed, iclass 32, count 0 2006.201.17:55:13.55#ibcon#about to write, iclass 32, count 0 2006.201.17:55:13.55#ibcon#wrote, iclass 32, count 0 2006.201.17:55:13.55#ibcon#about to read 3, iclass 32, count 0 2006.201.17:55:13.58#ibcon#read 3, iclass 32, count 0 2006.201.17:55:13.58#ibcon#about to read 4, iclass 32, count 0 2006.201.17:55:13.58#ibcon#read 4, iclass 32, count 0 2006.201.17:55:13.58#ibcon#about to read 5, iclass 32, count 0 2006.201.17:55:13.58#ibcon#read 5, iclass 32, count 0 2006.201.17:55:13.58#ibcon#about to read 6, iclass 32, count 0 2006.201.17:55:13.58#ibcon#read 6, iclass 32, count 0 2006.201.17:55:13.58#ibcon#end of sib2, iclass 32, count 0 2006.201.17:55:13.58#ibcon#*after write, iclass 32, count 0 2006.201.17:55:13.58#ibcon#*before return 0, iclass 32, count 0 2006.201.17:55:13.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:13.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:13.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.17:55:13.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.17:55:13.58$vck44/vblo=1,629.99 2006.201.17:55:13.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.17:55:13.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.17:55:13.58#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:13.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:13.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:13.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:13.58#ibcon#enter wrdev, iclass 34, count 0 2006.201.17:55:13.58#ibcon#first serial, iclass 34, count 0 2006.201.17:55:13.58#ibcon#enter sib2, iclass 34, count 0 2006.201.17:55:13.58#ibcon#flushed, iclass 34, count 0 2006.201.17:55:13.58#ibcon#about to write, iclass 34, count 0 2006.201.17:55:13.58#ibcon#wrote, iclass 34, count 0 2006.201.17:55:13.58#ibcon#about to read 3, iclass 34, count 0 2006.201.17:55:13.60#ibcon#read 3, iclass 34, count 0 2006.201.17:55:13.60#ibcon#about to read 4, iclass 34, count 0 2006.201.17:55:13.60#ibcon#read 4, iclass 34, count 0 2006.201.17:55:13.60#ibcon#about to read 5, iclass 34, count 0 2006.201.17:55:13.60#ibcon#read 5, iclass 34, count 0 2006.201.17:55:13.60#ibcon#about to read 6, iclass 34, count 0 2006.201.17:55:13.60#ibcon#read 6, iclass 34, count 0 2006.201.17:55:13.60#ibcon#end of sib2, iclass 34, count 0 2006.201.17:55:13.60#ibcon#*mode == 0, iclass 34, count 0 2006.201.17:55:13.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.17:55:13.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.17:55:13.60#ibcon#*before write, iclass 34, count 0 2006.201.17:55:13.60#ibcon#enter sib2, iclass 34, count 0 2006.201.17:55:13.60#ibcon#flushed, iclass 34, count 0 2006.201.17:55:13.60#ibcon#about to write, iclass 34, count 0 2006.201.17:55:13.60#ibcon#wrote, iclass 34, count 0 2006.201.17:55:13.60#ibcon#about to read 3, iclass 34, count 0 2006.201.17:55:13.64#ibcon#read 3, iclass 34, count 0 2006.201.17:55:13.64#ibcon#about to read 4, iclass 34, count 0 2006.201.17:55:13.64#ibcon#read 4, iclass 34, count 0 2006.201.17:55:13.64#ibcon#about to read 5, iclass 34, count 0 2006.201.17:55:13.64#ibcon#read 5, iclass 34, count 0 2006.201.17:55:13.64#ibcon#about to read 6, iclass 34, count 0 2006.201.17:55:13.64#ibcon#read 6, iclass 34, count 0 2006.201.17:55:13.64#ibcon#end of sib2, iclass 34, count 0 2006.201.17:55:13.64#ibcon#*after write, iclass 34, count 0 2006.201.17:55:13.64#ibcon#*before return 0, iclass 34, count 0 2006.201.17:55:13.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:13.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:13.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.17:55:13.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.17:55:13.64$vck44/vb=1,4 2006.201.17:55:13.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.17:55:13.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.17:55:13.64#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:13.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.17:55:13.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.17:55:13.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.17:55:13.64#ibcon#enter wrdev, iclass 36, count 2 2006.201.17:55:13.64#ibcon#first serial, iclass 36, count 2 2006.201.17:55:13.64#ibcon#enter sib2, iclass 36, count 2 2006.201.17:55:13.64#ibcon#flushed, iclass 36, count 2 2006.201.17:55:13.64#ibcon#about to write, iclass 36, count 2 2006.201.17:55:13.64#ibcon#wrote, iclass 36, count 2 2006.201.17:55:13.64#ibcon#about to read 3, iclass 36, count 2 2006.201.17:55:13.66#ibcon#read 3, iclass 36, count 2 2006.201.17:55:13.66#ibcon#about to read 4, iclass 36, count 2 2006.201.17:55:13.66#ibcon#read 4, iclass 36, count 2 2006.201.17:55:13.66#ibcon#about to read 5, iclass 36, count 2 2006.201.17:55:13.66#ibcon#read 5, iclass 36, count 2 2006.201.17:55:13.66#ibcon#about to read 6, iclass 36, count 2 2006.201.17:55:13.66#ibcon#read 6, iclass 36, count 2 2006.201.17:55:13.66#ibcon#end of sib2, iclass 36, count 2 2006.201.17:55:13.66#ibcon#*mode == 0, iclass 36, count 2 2006.201.17:55:13.66#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.17:55:13.66#ibcon#[27=AT01-04\r\n] 2006.201.17:55:13.66#ibcon#*before write, iclass 36, count 2 2006.201.17:55:13.66#ibcon#enter sib2, iclass 36, count 2 2006.201.17:55:13.66#ibcon#flushed, iclass 36, count 2 2006.201.17:55:13.66#ibcon#about to write, iclass 36, count 2 2006.201.17:55:13.66#ibcon#wrote, iclass 36, count 2 2006.201.17:55:13.66#ibcon#about to read 3, iclass 36, count 2 2006.201.17:55:13.69#ibcon#read 3, iclass 36, count 2 2006.201.17:55:13.69#ibcon#about to read 4, iclass 36, count 2 2006.201.17:55:13.69#ibcon#read 4, iclass 36, count 2 2006.201.17:55:13.69#ibcon#about to read 5, iclass 36, count 2 2006.201.17:55:13.69#ibcon#read 5, iclass 36, count 2 2006.201.17:55:13.69#ibcon#about to read 6, iclass 36, count 2 2006.201.17:55:13.69#ibcon#read 6, iclass 36, count 2 2006.201.17:55:13.69#ibcon#end of sib2, iclass 36, count 2 2006.201.17:55:13.69#ibcon#*after write, iclass 36, count 2 2006.201.17:55:13.69#ibcon#*before return 0, iclass 36, count 2 2006.201.17:55:13.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.17:55:13.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.17:55:13.69#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.17:55:13.69#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:13.69#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.17:55:13.81#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.17:55:13.81#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.17:55:13.81#ibcon#enter wrdev, iclass 36, count 0 2006.201.17:55:13.81#ibcon#first serial, iclass 36, count 0 2006.201.17:55:13.81#ibcon#enter sib2, iclass 36, count 0 2006.201.17:55:13.81#ibcon#flushed, iclass 36, count 0 2006.201.17:55:13.81#ibcon#about to write, iclass 36, count 0 2006.201.17:55:13.81#ibcon#wrote, iclass 36, count 0 2006.201.17:55:13.81#ibcon#about to read 3, iclass 36, count 0 2006.201.17:55:13.83#ibcon#read 3, iclass 36, count 0 2006.201.17:55:13.83#ibcon#about to read 4, iclass 36, count 0 2006.201.17:55:13.83#ibcon#read 4, iclass 36, count 0 2006.201.17:55:13.83#ibcon#about to read 5, iclass 36, count 0 2006.201.17:55:13.83#ibcon#read 5, iclass 36, count 0 2006.201.17:55:13.83#ibcon#about to read 6, iclass 36, count 0 2006.201.17:55:13.83#ibcon#read 6, iclass 36, count 0 2006.201.17:55:13.83#ibcon#end of sib2, iclass 36, count 0 2006.201.17:55:13.83#ibcon#*mode == 0, iclass 36, count 0 2006.201.17:55:13.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.17:55:13.83#ibcon#[27=USB\r\n] 2006.201.17:55:13.83#ibcon#*before write, iclass 36, count 0 2006.201.17:55:13.83#ibcon#enter sib2, iclass 36, count 0 2006.201.17:55:13.83#ibcon#flushed, iclass 36, count 0 2006.201.17:55:13.83#ibcon#about to write, iclass 36, count 0 2006.201.17:55:13.83#ibcon#wrote, iclass 36, count 0 2006.201.17:55:13.83#ibcon#about to read 3, iclass 36, count 0 2006.201.17:55:13.86#ibcon#read 3, iclass 36, count 0 2006.201.17:55:13.86#ibcon#about to read 4, iclass 36, count 0 2006.201.17:55:13.86#ibcon#read 4, iclass 36, count 0 2006.201.17:55:13.86#ibcon#about to read 5, iclass 36, count 0 2006.201.17:55:13.86#ibcon#read 5, iclass 36, count 0 2006.201.17:55:13.86#ibcon#about to read 6, iclass 36, count 0 2006.201.17:55:13.86#ibcon#read 6, iclass 36, count 0 2006.201.17:55:13.86#ibcon#end of sib2, iclass 36, count 0 2006.201.17:55:13.86#ibcon#*after write, iclass 36, count 0 2006.201.17:55:13.86#ibcon#*before return 0, iclass 36, count 0 2006.201.17:55:13.86#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.17:55:13.86#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.17:55:13.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.17:55:13.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.17:55:13.86$vck44/vblo=2,634.99 2006.201.17:55:13.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.17:55:13.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.17:55:13.86#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:13.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:13.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:13.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:13.86#ibcon#enter wrdev, iclass 38, count 0 2006.201.17:55:13.86#ibcon#first serial, iclass 38, count 0 2006.201.17:55:13.86#ibcon#enter sib2, iclass 38, count 0 2006.201.17:55:13.86#ibcon#flushed, iclass 38, count 0 2006.201.17:55:13.86#ibcon#about to write, iclass 38, count 0 2006.201.17:55:13.86#ibcon#wrote, iclass 38, count 0 2006.201.17:55:13.86#ibcon#about to read 3, iclass 38, count 0 2006.201.17:55:13.88#ibcon#read 3, iclass 38, count 0 2006.201.17:55:13.88#ibcon#about to read 4, iclass 38, count 0 2006.201.17:55:13.88#ibcon#read 4, iclass 38, count 0 2006.201.17:55:13.88#ibcon#about to read 5, iclass 38, count 0 2006.201.17:55:13.88#ibcon#read 5, iclass 38, count 0 2006.201.17:55:13.88#ibcon#about to read 6, iclass 38, count 0 2006.201.17:55:13.88#ibcon#read 6, iclass 38, count 0 2006.201.17:55:13.88#ibcon#end of sib2, iclass 38, count 0 2006.201.17:55:13.88#ibcon#*mode == 0, iclass 38, count 0 2006.201.17:55:13.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.17:55:13.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.17:55:13.88#ibcon#*before write, iclass 38, count 0 2006.201.17:55:13.88#ibcon#enter sib2, iclass 38, count 0 2006.201.17:55:13.88#ibcon#flushed, iclass 38, count 0 2006.201.17:55:13.88#ibcon#about to write, iclass 38, count 0 2006.201.17:55:13.88#ibcon#wrote, iclass 38, count 0 2006.201.17:55:13.88#ibcon#about to read 3, iclass 38, count 0 2006.201.17:55:13.93#ibcon#read 3, iclass 38, count 0 2006.201.17:55:13.93#ibcon#about to read 4, iclass 38, count 0 2006.201.17:55:13.93#ibcon#read 4, iclass 38, count 0 2006.201.17:55:13.93#ibcon#about to read 5, iclass 38, count 0 2006.201.17:55:13.93#ibcon#read 5, iclass 38, count 0 2006.201.17:55:13.93#ibcon#about to read 6, iclass 38, count 0 2006.201.17:55:13.93#ibcon#read 6, iclass 38, count 0 2006.201.17:55:13.93#ibcon#end of sib2, iclass 38, count 0 2006.201.17:55:13.93#ibcon#*after write, iclass 38, count 0 2006.201.17:55:13.93#ibcon#*before return 0, iclass 38, count 0 2006.201.17:55:13.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:13.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.17:55:13.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.17:55:13.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.17:55:13.93$vck44/vb=2,5 2006.201.17:55:13.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.17:55:13.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.17:55:13.93#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:13.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:13.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:13.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:13.98#ibcon#enter wrdev, iclass 40, count 2 2006.201.17:55:13.98#ibcon#first serial, iclass 40, count 2 2006.201.17:55:13.98#ibcon#enter sib2, iclass 40, count 2 2006.201.17:55:13.98#ibcon#flushed, iclass 40, count 2 2006.201.17:55:13.98#ibcon#about to write, iclass 40, count 2 2006.201.17:55:13.98#ibcon#wrote, iclass 40, count 2 2006.201.17:55:13.98#ibcon#about to read 3, iclass 40, count 2 2006.201.17:55:14.00#ibcon#read 3, iclass 40, count 2 2006.201.17:55:14.00#ibcon#about to read 4, iclass 40, count 2 2006.201.17:55:14.00#ibcon#read 4, iclass 40, count 2 2006.201.17:55:14.00#ibcon#about to read 5, iclass 40, count 2 2006.201.17:55:14.00#ibcon#read 5, iclass 40, count 2 2006.201.17:55:14.00#ibcon#about to read 6, iclass 40, count 2 2006.201.17:55:14.00#ibcon#read 6, iclass 40, count 2 2006.201.17:55:14.00#ibcon#end of sib2, iclass 40, count 2 2006.201.17:55:14.00#ibcon#*mode == 0, iclass 40, count 2 2006.201.17:55:14.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.17:55:14.00#ibcon#[27=AT02-05\r\n] 2006.201.17:55:14.00#ibcon#*before write, iclass 40, count 2 2006.201.17:55:14.00#ibcon#enter sib2, iclass 40, count 2 2006.201.17:55:14.00#ibcon#flushed, iclass 40, count 2 2006.201.17:55:14.00#ibcon#about to write, iclass 40, count 2 2006.201.17:55:14.00#ibcon#wrote, iclass 40, count 2 2006.201.17:55:14.00#ibcon#about to read 3, iclass 40, count 2 2006.201.17:55:14.03#ibcon#read 3, iclass 40, count 2 2006.201.17:55:14.03#ibcon#about to read 4, iclass 40, count 2 2006.201.17:55:14.03#ibcon#read 4, iclass 40, count 2 2006.201.17:55:14.03#ibcon#about to read 5, iclass 40, count 2 2006.201.17:55:14.03#ibcon#read 5, iclass 40, count 2 2006.201.17:55:14.03#ibcon#about to read 6, iclass 40, count 2 2006.201.17:55:14.03#ibcon#read 6, iclass 40, count 2 2006.201.17:55:14.03#ibcon#end of sib2, iclass 40, count 2 2006.201.17:55:14.03#ibcon#*after write, iclass 40, count 2 2006.201.17:55:14.03#ibcon#*before return 0, iclass 40, count 2 2006.201.17:55:14.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:14.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.17:55:14.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.17:55:14.03#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:14.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:14.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:14.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:14.15#ibcon#enter wrdev, iclass 40, count 0 2006.201.17:55:14.15#ibcon#first serial, iclass 40, count 0 2006.201.17:55:14.15#ibcon#enter sib2, iclass 40, count 0 2006.201.17:55:14.15#ibcon#flushed, iclass 40, count 0 2006.201.17:55:14.15#ibcon#about to write, iclass 40, count 0 2006.201.17:55:14.15#ibcon#wrote, iclass 40, count 0 2006.201.17:55:14.15#ibcon#about to read 3, iclass 40, count 0 2006.201.17:55:14.17#ibcon#read 3, iclass 40, count 0 2006.201.17:55:14.17#ibcon#about to read 4, iclass 40, count 0 2006.201.17:55:14.17#ibcon#read 4, iclass 40, count 0 2006.201.17:55:14.17#ibcon#about to read 5, iclass 40, count 0 2006.201.17:55:14.17#ibcon#read 5, iclass 40, count 0 2006.201.17:55:14.17#ibcon#about to read 6, iclass 40, count 0 2006.201.17:55:14.17#ibcon#read 6, iclass 40, count 0 2006.201.17:55:14.17#ibcon#end of sib2, iclass 40, count 0 2006.201.17:55:14.17#ibcon#*mode == 0, iclass 40, count 0 2006.201.17:55:14.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.17:55:14.17#ibcon#[27=USB\r\n] 2006.201.17:55:14.17#ibcon#*before write, iclass 40, count 0 2006.201.17:55:14.17#ibcon#enter sib2, iclass 40, count 0 2006.201.17:55:14.17#ibcon#flushed, iclass 40, count 0 2006.201.17:55:14.17#ibcon#about to write, iclass 40, count 0 2006.201.17:55:14.17#ibcon#wrote, iclass 40, count 0 2006.201.17:55:14.17#ibcon#about to read 3, iclass 40, count 0 2006.201.17:55:14.20#ibcon#read 3, iclass 40, count 0 2006.201.17:55:14.20#ibcon#about to read 4, iclass 40, count 0 2006.201.17:55:14.20#ibcon#read 4, iclass 40, count 0 2006.201.17:55:14.20#ibcon#about to read 5, iclass 40, count 0 2006.201.17:55:14.20#ibcon#read 5, iclass 40, count 0 2006.201.17:55:14.20#ibcon#about to read 6, iclass 40, count 0 2006.201.17:55:14.20#ibcon#read 6, iclass 40, count 0 2006.201.17:55:14.20#ibcon#end of sib2, iclass 40, count 0 2006.201.17:55:14.20#ibcon#*after write, iclass 40, count 0 2006.201.17:55:14.20#ibcon#*before return 0, iclass 40, count 0 2006.201.17:55:14.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:14.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.17:55:14.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.17:55:14.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.17:55:14.20$vck44/vblo=3,649.99 2006.201.17:55:14.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.17:55:14.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.17:55:14.20#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:14.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:14.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:14.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:14.20#ibcon#enter wrdev, iclass 4, count 0 2006.201.17:55:14.20#ibcon#first serial, iclass 4, count 0 2006.201.17:55:14.20#ibcon#enter sib2, iclass 4, count 0 2006.201.17:55:14.20#ibcon#flushed, iclass 4, count 0 2006.201.17:55:14.20#ibcon#about to write, iclass 4, count 0 2006.201.17:55:14.20#ibcon#wrote, iclass 4, count 0 2006.201.17:55:14.20#ibcon#about to read 3, iclass 4, count 0 2006.201.17:55:14.22#ibcon#read 3, iclass 4, count 0 2006.201.17:55:14.22#ibcon#about to read 4, iclass 4, count 0 2006.201.17:55:14.22#ibcon#read 4, iclass 4, count 0 2006.201.17:55:14.22#ibcon#about to read 5, iclass 4, count 0 2006.201.17:55:14.22#ibcon#read 5, iclass 4, count 0 2006.201.17:55:14.22#ibcon#about to read 6, iclass 4, count 0 2006.201.17:55:14.22#ibcon#read 6, iclass 4, count 0 2006.201.17:55:14.22#ibcon#end of sib2, iclass 4, count 0 2006.201.17:55:14.22#ibcon#*mode == 0, iclass 4, count 0 2006.201.17:55:14.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.17:55:14.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.17:55:14.22#ibcon#*before write, iclass 4, count 0 2006.201.17:55:14.22#ibcon#enter sib2, iclass 4, count 0 2006.201.17:55:14.22#ibcon#flushed, iclass 4, count 0 2006.201.17:55:14.22#ibcon#about to write, iclass 4, count 0 2006.201.17:55:14.22#ibcon#wrote, iclass 4, count 0 2006.201.17:55:14.22#ibcon#about to read 3, iclass 4, count 0 2006.201.17:55:14.26#ibcon#read 3, iclass 4, count 0 2006.201.17:55:14.26#ibcon#about to read 4, iclass 4, count 0 2006.201.17:55:14.26#ibcon#read 4, iclass 4, count 0 2006.201.17:55:14.26#ibcon#about to read 5, iclass 4, count 0 2006.201.17:55:14.26#ibcon#read 5, iclass 4, count 0 2006.201.17:55:14.26#ibcon#about to read 6, iclass 4, count 0 2006.201.17:55:14.26#ibcon#read 6, iclass 4, count 0 2006.201.17:55:14.26#ibcon#end of sib2, iclass 4, count 0 2006.201.17:55:14.26#ibcon#*after write, iclass 4, count 0 2006.201.17:55:14.26#ibcon#*before return 0, iclass 4, count 0 2006.201.17:55:14.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:14.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.17:55:14.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.17:55:14.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.17:55:14.26$vck44/vb=3,4 2006.201.17:55:14.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.17:55:14.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.17:55:14.26#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:14.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:14.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:14.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:14.32#ibcon#enter wrdev, iclass 6, count 2 2006.201.17:55:14.32#ibcon#first serial, iclass 6, count 2 2006.201.17:55:14.32#ibcon#enter sib2, iclass 6, count 2 2006.201.17:55:14.32#ibcon#flushed, iclass 6, count 2 2006.201.17:55:14.32#ibcon#about to write, iclass 6, count 2 2006.201.17:55:14.32#ibcon#wrote, iclass 6, count 2 2006.201.17:55:14.32#ibcon#about to read 3, iclass 6, count 2 2006.201.17:55:14.34#ibcon#read 3, iclass 6, count 2 2006.201.17:55:14.34#ibcon#about to read 4, iclass 6, count 2 2006.201.17:55:14.34#ibcon#read 4, iclass 6, count 2 2006.201.17:55:14.34#ibcon#about to read 5, iclass 6, count 2 2006.201.17:55:14.34#ibcon#read 5, iclass 6, count 2 2006.201.17:55:14.34#ibcon#about to read 6, iclass 6, count 2 2006.201.17:55:14.34#ibcon#read 6, iclass 6, count 2 2006.201.17:55:14.34#ibcon#end of sib2, iclass 6, count 2 2006.201.17:55:14.34#ibcon#*mode == 0, iclass 6, count 2 2006.201.17:55:14.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.17:55:14.34#ibcon#[27=AT03-04\r\n] 2006.201.17:55:14.34#ibcon#*before write, iclass 6, count 2 2006.201.17:55:14.34#ibcon#enter sib2, iclass 6, count 2 2006.201.17:55:14.34#ibcon#flushed, iclass 6, count 2 2006.201.17:55:14.34#ibcon#about to write, iclass 6, count 2 2006.201.17:55:14.34#ibcon#wrote, iclass 6, count 2 2006.201.17:55:14.34#ibcon#about to read 3, iclass 6, count 2 2006.201.17:55:14.37#ibcon#read 3, iclass 6, count 2 2006.201.17:55:14.37#ibcon#about to read 4, iclass 6, count 2 2006.201.17:55:14.37#ibcon#read 4, iclass 6, count 2 2006.201.17:55:14.37#ibcon#about to read 5, iclass 6, count 2 2006.201.17:55:14.37#ibcon#read 5, iclass 6, count 2 2006.201.17:55:14.37#ibcon#about to read 6, iclass 6, count 2 2006.201.17:55:14.37#ibcon#read 6, iclass 6, count 2 2006.201.17:55:14.37#ibcon#end of sib2, iclass 6, count 2 2006.201.17:55:14.37#ibcon#*after write, iclass 6, count 2 2006.201.17:55:14.37#ibcon#*before return 0, iclass 6, count 2 2006.201.17:55:14.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:14.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.17:55:14.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.17:55:14.37#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:14.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:14.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:14.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:14.49#ibcon#enter wrdev, iclass 6, count 0 2006.201.17:55:14.49#ibcon#first serial, iclass 6, count 0 2006.201.17:55:14.49#ibcon#enter sib2, iclass 6, count 0 2006.201.17:55:14.49#ibcon#flushed, iclass 6, count 0 2006.201.17:55:14.49#ibcon#about to write, iclass 6, count 0 2006.201.17:55:14.49#ibcon#wrote, iclass 6, count 0 2006.201.17:55:14.49#ibcon#about to read 3, iclass 6, count 0 2006.201.17:55:14.51#ibcon#read 3, iclass 6, count 0 2006.201.17:55:14.51#ibcon#about to read 4, iclass 6, count 0 2006.201.17:55:14.51#ibcon#read 4, iclass 6, count 0 2006.201.17:55:14.51#ibcon#about to read 5, iclass 6, count 0 2006.201.17:55:14.51#ibcon#read 5, iclass 6, count 0 2006.201.17:55:14.51#ibcon#about to read 6, iclass 6, count 0 2006.201.17:55:14.51#ibcon#read 6, iclass 6, count 0 2006.201.17:55:14.51#ibcon#end of sib2, iclass 6, count 0 2006.201.17:55:14.51#ibcon#*mode == 0, iclass 6, count 0 2006.201.17:55:14.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.17:55:14.51#ibcon#[27=USB\r\n] 2006.201.17:55:14.51#ibcon#*before write, iclass 6, count 0 2006.201.17:55:14.51#ibcon#enter sib2, iclass 6, count 0 2006.201.17:55:14.51#ibcon#flushed, iclass 6, count 0 2006.201.17:55:14.51#ibcon#about to write, iclass 6, count 0 2006.201.17:55:14.51#ibcon#wrote, iclass 6, count 0 2006.201.17:55:14.51#ibcon#about to read 3, iclass 6, count 0 2006.201.17:55:14.54#ibcon#read 3, iclass 6, count 0 2006.201.17:55:14.54#ibcon#about to read 4, iclass 6, count 0 2006.201.17:55:14.54#ibcon#read 4, iclass 6, count 0 2006.201.17:55:14.54#ibcon#about to read 5, iclass 6, count 0 2006.201.17:55:14.54#ibcon#read 5, iclass 6, count 0 2006.201.17:55:14.54#ibcon#about to read 6, iclass 6, count 0 2006.201.17:55:14.54#ibcon#read 6, iclass 6, count 0 2006.201.17:55:14.54#ibcon#end of sib2, iclass 6, count 0 2006.201.17:55:14.54#ibcon#*after write, iclass 6, count 0 2006.201.17:55:14.54#ibcon#*before return 0, iclass 6, count 0 2006.201.17:55:14.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:14.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.17:55:14.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.17:55:14.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.17:55:14.54$vck44/vblo=4,679.99 2006.201.17:55:14.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.17:55:14.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.17:55:14.54#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:14.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:14.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:14.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:14.54#ibcon#enter wrdev, iclass 10, count 0 2006.201.17:55:14.54#ibcon#first serial, iclass 10, count 0 2006.201.17:55:14.54#ibcon#enter sib2, iclass 10, count 0 2006.201.17:55:14.54#ibcon#flushed, iclass 10, count 0 2006.201.17:55:14.54#ibcon#about to write, iclass 10, count 0 2006.201.17:55:14.54#ibcon#wrote, iclass 10, count 0 2006.201.17:55:14.54#ibcon#about to read 3, iclass 10, count 0 2006.201.17:55:14.56#ibcon#read 3, iclass 10, count 0 2006.201.17:55:14.56#ibcon#about to read 4, iclass 10, count 0 2006.201.17:55:14.56#ibcon#read 4, iclass 10, count 0 2006.201.17:55:14.56#ibcon#about to read 5, iclass 10, count 0 2006.201.17:55:14.56#ibcon#read 5, iclass 10, count 0 2006.201.17:55:14.56#ibcon#about to read 6, iclass 10, count 0 2006.201.17:55:14.56#ibcon#read 6, iclass 10, count 0 2006.201.17:55:14.56#ibcon#end of sib2, iclass 10, count 0 2006.201.17:55:14.56#ibcon#*mode == 0, iclass 10, count 0 2006.201.17:55:14.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.17:55:14.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.17:55:14.56#ibcon#*before write, iclass 10, count 0 2006.201.17:55:14.56#ibcon#enter sib2, iclass 10, count 0 2006.201.17:55:14.56#ibcon#flushed, iclass 10, count 0 2006.201.17:55:14.56#ibcon#about to write, iclass 10, count 0 2006.201.17:55:14.56#ibcon#wrote, iclass 10, count 0 2006.201.17:55:14.56#ibcon#about to read 3, iclass 10, count 0 2006.201.17:55:14.61#ibcon#read 3, iclass 10, count 0 2006.201.17:55:14.61#ibcon#about to read 4, iclass 10, count 0 2006.201.17:55:14.61#ibcon#read 4, iclass 10, count 0 2006.201.17:55:14.61#ibcon#about to read 5, iclass 10, count 0 2006.201.17:55:14.61#ibcon#read 5, iclass 10, count 0 2006.201.17:55:14.61#ibcon#about to read 6, iclass 10, count 0 2006.201.17:55:14.61#ibcon#read 6, iclass 10, count 0 2006.201.17:55:14.61#ibcon#end of sib2, iclass 10, count 0 2006.201.17:55:14.61#ibcon#*after write, iclass 10, count 0 2006.201.17:55:14.61#ibcon#*before return 0, iclass 10, count 0 2006.201.17:55:14.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:14.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.17:55:14.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.17:55:14.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.17:55:14.61$vck44/vb=4,5 2006.201.17:55:14.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.17:55:14.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.17:55:14.61#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:14.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:14.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:14.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:14.66#ibcon#enter wrdev, iclass 12, count 2 2006.201.17:55:14.66#ibcon#first serial, iclass 12, count 2 2006.201.17:55:14.66#ibcon#enter sib2, iclass 12, count 2 2006.201.17:55:14.66#ibcon#flushed, iclass 12, count 2 2006.201.17:55:14.66#ibcon#about to write, iclass 12, count 2 2006.201.17:55:14.66#ibcon#wrote, iclass 12, count 2 2006.201.17:55:14.66#ibcon#about to read 3, iclass 12, count 2 2006.201.17:55:14.68#ibcon#read 3, iclass 12, count 2 2006.201.17:55:14.68#ibcon#about to read 4, iclass 12, count 2 2006.201.17:55:14.68#ibcon#read 4, iclass 12, count 2 2006.201.17:55:14.68#ibcon#about to read 5, iclass 12, count 2 2006.201.17:55:14.68#ibcon#read 5, iclass 12, count 2 2006.201.17:55:14.68#ibcon#about to read 6, iclass 12, count 2 2006.201.17:55:14.68#ibcon#read 6, iclass 12, count 2 2006.201.17:55:14.68#ibcon#end of sib2, iclass 12, count 2 2006.201.17:55:14.68#ibcon#*mode == 0, iclass 12, count 2 2006.201.17:55:14.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.17:55:14.68#ibcon#[27=AT04-05\r\n] 2006.201.17:55:14.68#ibcon#*before write, iclass 12, count 2 2006.201.17:55:14.68#ibcon#enter sib2, iclass 12, count 2 2006.201.17:55:14.68#ibcon#flushed, iclass 12, count 2 2006.201.17:55:14.68#ibcon#about to write, iclass 12, count 2 2006.201.17:55:14.68#ibcon#wrote, iclass 12, count 2 2006.201.17:55:14.68#ibcon#about to read 3, iclass 12, count 2 2006.201.17:55:14.71#ibcon#read 3, iclass 12, count 2 2006.201.17:55:14.71#ibcon#about to read 4, iclass 12, count 2 2006.201.17:55:14.71#ibcon#read 4, iclass 12, count 2 2006.201.17:55:14.71#ibcon#about to read 5, iclass 12, count 2 2006.201.17:55:14.71#ibcon#read 5, iclass 12, count 2 2006.201.17:55:14.71#ibcon#about to read 6, iclass 12, count 2 2006.201.17:55:14.71#ibcon#read 6, iclass 12, count 2 2006.201.17:55:14.71#ibcon#end of sib2, iclass 12, count 2 2006.201.17:55:14.71#ibcon#*after write, iclass 12, count 2 2006.201.17:55:14.71#ibcon#*before return 0, iclass 12, count 2 2006.201.17:55:14.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:14.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.17:55:14.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.17:55:14.71#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:14.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:14.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:14.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:14.83#ibcon#enter wrdev, iclass 12, count 0 2006.201.17:55:14.83#ibcon#first serial, iclass 12, count 0 2006.201.17:55:14.83#ibcon#enter sib2, iclass 12, count 0 2006.201.17:55:14.83#ibcon#flushed, iclass 12, count 0 2006.201.17:55:14.83#ibcon#about to write, iclass 12, count 0 2006.201.17:55:14.83#ibcon#wrote, iclass 12, count 0 2006.201.17:55:14.83#ibcon#about to read 3, iclass 12, count 0 2006.201.17:55:14.85#ibcon#read 3, iclass 12, count 0 2006.201.17:55:14.85#ibcon#about to read 4, iclass 12, count 0 2006.201.17:55:14.85#ibcon#read 4, iclass 12, count 0 2006.201.17:55:14.85#ibcon#about to read 5, iclass 12, count 0 2006.201.17:55:14.85#ibcon#read 5, iclass 12, count 0 2006.201.17:55:14.85#ibcon#about to read 6, iclass 12, count 0 2006.201.17:55:14.85#ibcon#read 6, iclass 12, count 0 2006.201.17:55:14.85#ibcon#end of sib2, iclass 12, count 0 2006.201.17:55:14.85#ibcon#*mode == 0, iclass 12, count 0 2006.201.17:55:14.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.17:55:14.85#ibcon#[27=USB\r\n] 2006.201.17:55:14.85#ibcon#*before write, iclass 12, count 0 2006.201.17:55:14.85#ibcon#enter sib2, iclass 12, count 0 2006.201.17:55:14.85#ibcon#flushed, iclass 12, count 0 2006.201.17:55:14.85#ibcon#about to write, iclass 12, count 0 2006.201.17:55:14.85#ibcon#wrote, iclass 12, count 0 2006.201.17:55:14.85#ibcon#about to read 3, iclass 12, count 0 2006.201.17:55:14.88#ibcon#read 3, iclass 12, count 0 2006.201.17:55:14.88#ibcon#about to read 4, iclass 12, count 0 2006.201.17:55:14.88#ibcon#read 4, iclass 12, count 0 2006.201.17:55:14.88#ibcon#about to read 5, iclass 12, count 0 2006.201.17:55:14.88#ibcon#read 5, iclass 12, count 0 2006.201.17:55:14.88#ibcon#about to read 6, iclass 12, count 0 2006.201.17:55:14.88#ibcon#read 6, iclass 12, count 0 2006.201.17:55:14.88#ibcon#end of sib2, iclass 12, count 0 2006.201.17:55:14.88#ibcon#*after write, iclass 12, count 0 2006.201.17:55:14.88#ibcon#*before return 0, iclass 12, count 0 2006.201.17:55:14.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:14.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.17:55:14.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.17:55:14.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.17:55:14.88$vck44/vblo=5,709.99 2006.201.17:55:14.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.17:55:14.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.17:55:14.88#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:14.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:14.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:14.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:14.88#ibcon#enter wrdev, iclass 14, count 0 2006.201.17:55:14.88#ibcon#first serial, iclass 14, count 0 2006.201.17:55:14.88#ibcon#enter sib2, iclass 14, count 0 2006.201.17:55:14.88#ibcon#flushed, iclass 14, count 0 2006.201.17:55:14.88#ibcon#about to write, iclass 14, count 0 2006.201.17:55:14.88#ibcon#wrote, iclass 14, count 0 2006.201.17:55:14.88#ibcon#about to read 3, iclass 14, count 0 2006.201.17:55:14.90#ibcon#read 3, iclass 14, count 0 2006.201.17:55:14.90#ibcon#about to read 4, iclass 14, count 0 2006.201.17:55:14.90#ibcon#read 4, iclass 14, count 0 2006.201.17:55:14.90#ibcon#about to read 5, iclass 14, count 0 2006.201.17:55:14.90#ibcon#read 5, iclass 14, count 0 2006.201.17:55:14.90#ibcon#about to read 6, iclass 14, count 0 2006.201.17:55:14.90#ibcon#read 6, iclass 14, count 0 2006.201.17:55:14.90#ibcon#end of sib2, iclass 14, count 0 2006.201.17:55:14.90#ibcon#*mode == 0, iclass 14, count 0 2006.201.17:55:14.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.17:55:14.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.17:55:14.90#ibcon#*before write, iclass 14, count 0 2006.201.17:55:14.90#ibcon#enter sib2, iclass 14, count 0 2006.201.17:55:14.90#ibcon#flushed, iclass 14, count 0 2006.201.17:55:14.90#ibcon#about to write, iclass 14, count 0 2006.201.17:55:14.90#ibcon#wrote, iclass 14, count 0 2006.201.17:55:14.90#ibcon#about to read 3, iclass 14, count 0 2006.201.17:55:14.95#ibcon#read 3, iclass 14, count 0 2006.201.17:55:14.95#ibcon#about to read 4, iclass 14, count 0 2006.201.17:55:14.95#ibcon#read 4, iclass 14, count 0 2006.201.17:55:14.95#ibcon#about to read 5, iclass 14, count 0 2006.201.17:55:14.95#ibcon#read 5, iclass 14, count 0 2006.201.17:55:14.95#ibcon#about to read 6, iclass 14, count 0 2006.201.17:55:14.95#ibcon#read 6, iclass 14, count 0 2006.201.17:55:14.95#ibcon#end of sib2, iclass 14, count 0 2006.201.17:55:14.95#ibcon#*after write, iclass 14, count 0 2006.201.17:55:14.95#ibcon#*before return 0, iclass 14, count 0 2006.201.17:55:14.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:14.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.17:55:14.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.17:55:14.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.17:55:14.95$vck44/vb=5,4 2006.201.17:55:14.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.17:55:14.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.17:55:14.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:14.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:15.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:15.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:15.00#ibcon#enter wrdev, iclass 16, count 2 2006.201.17:55:15.00#ibcon#first serial, iclass 16, count 2 2006.201.17:55:15.00#ibcon#enter sib2, iclass 16, count 2 2006.201.17:55:15.00#ibcon#flushed, iclass 16, count 2 2006.201.17:55:15.00#ibcon#about to write, iclass 16, count 2 2006.201.17:55:15.00#ibcon#wrote, iclass 16, count 2 2006.201.17:55:15.00#ibcon#about to read 3, iclass 16, count 2 2006.201.17:55:15.02#ibcon#read 3, iclass 16, count 2 2006.201.17:55:15.02#ibcon#about to read 4, iclass 16, count 2 2006.201.17:55:15.02#ibcon#read 4, iclass 16, count 2 2006.201.17:55:15.02#ibcon#about to read 5, iclass 16, count 2 2006.201.17:55:15.02#ibcon#read 5, iclass 16, count 2 2006.201.17:55:15.02#ibcon#about to read 6, iclass 16, count 2 2006.201.17:55:15.02#ibcon#read 6, iclass 16, count 2 2006.201.17:55:15.02#ibcon#end of sib2, iclass 16, count 2 2006.201.17:55:15.02#ibcon#*mode == 0, iclass 16, count 2 2006.201.17:55:15.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.17:55:15.02#ibcon#[27=AT05-04\r\n] 2006.201.17:55:15.02#ibcon#*before write, iclass 16, count 2 2006.201.17:55:15.02#ibcon#enter sib2, iclass 16, count 2 2006.201.17:55:15.02#ibcon#flushed, iclass 16, count 2 2006.201.17:55:15.02#ibcon#about to write, iclass 16, count 2 2006.201.17:55:15.02#ibcon#wrote, iclass 16, count 2 2006.201.17:55:15.02#ibcon#about to read 3, iclass 16, count 2 2006.201.17:55:15.05#ibcon#read 3, iclass 16, count 2 2006.201.17:55:15.05#ibcon#about to read 4, iclass 16, count 2 2006.201.17:55:15.05#ibcon#read 4, iclass 16, count 2 2006.201.17:55:15.05#ibcon#about to read 5, iclass 16, count 2 2006.201.17:55:15.05#ibcon#read 5, iclass 16, count 2 2006.201.17:55:15.05#ibcon#about to read 6, iclass 16, count 2 2006.201.17:55:15.05#ibcon#read 6, iclass 16, count 2 2006.201.17:55:15.05#ibcon#end of sib2, iclass 16, count 2 2006.201.17:55:15.05#ibcon#*after write, iclass 16, count 2 2006.201.17:55:15.05#ibcon#*before return 0, iclass 16, count 2 2006.201.17:55:15.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:15.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.17:55:15.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.17:55:15.05#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:15.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:15.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:15.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:15.17#ibcon#enter wrdev, iclass 16, count 0 2006.201.17:55:15.17#ibcon#first serial, iclass 16, count 0 2006.201.17:55:15.17#ibcon#enter sib2, iclass 16, count 0 2006.201.17:55:15.17#ibcon#flushed, iclass 16, count 0 2006.201.17:55:15.17#ibcon#about to write, iclass 16, count 0 2006.201.17:55:15.17#ibcon#wrote, iclass 16, count 0 2006.201.17:55:15.17#ibcon#about to read 3, iclass 16, count 0 2006.201.17:55:15.19#ibcon#read 3, iclass 16, count 0 2006.201.17:55:15.19#ibcon#about to read 4, iclass 16, count 0 2006.201.17:55:15.19#ibcon#read 4, iclass 16, count 0 2006.201.17:55:15.19#ibcon#about to read 5, iclass 16, count 0 2006.201.17:55:15.19#ibcon#read 5, iclass 16, count 0 2006.201.17:55:15.19#ibcon#about to read 6, iclass 16, count 0 2006.201.17:55:15.19#ibcon#read 6, iclass 16, count 0 2006.201.17:55:15.19#ibcon#end of sib2, iclass 16, count 0 2006.201.17:55:15.19#ibcon#*mode == 0, iclass 16, count 0 2006.201.17:55:15.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.17:55:15.19#ibcon#[27=USB\r\n] 2006.201.17:55:15.19#ibcon#*before write, iclass 16, count 0 2006.201.17:55:15.19#ibcon#enter sib2, iclass 16, count 0 2006.201.17:55:15.19#ibcon#flushed, iclass 16, count 0 2006.201.17:55:15.19#ibcon#about to write, iclass 16, count 0 2006.201.17:55:15.19#ibcon#wrote, iclass 16, count 0 2006.201.17:55:15.19#ibcon#about to read 3, iclass 16, count 0 2006.201.17:55:15.22#ibcon#read 3, iclass 16, count 0 2006.201.17:55:15.22#ibcon#about to read 4, iclass 16, count 0 2006.201.17:55:15.22#ibcon#read 4, iclass 16, count 0 2006.201.17:55:15.22#ibcon#about to read 5, iclass 16, count 0 2006.201.17:55:15.22#ibcon#read 5, iclass 16, count 0 2006.201.17:55:15.22#ibcon#about to read 6, iclass 16, count 0 2006.201.17:55:15.22#ibcon#read 6, iclass 16, count 0 2006.201.17:55:15.22#ibcon#end of sib2, iclass 16, count 0 2006.201.17:55:15.22#ibcon#*after write, iclass 16, count 0 2006.201.17:55:15.22#ibcon#*before return 0, iclass 16, count 0 2006.201.17:55:15.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:15.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.17:55:15.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.17:55:15.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.17:55:15.22$vck44/vblo=6,719.99 2006.201.17:55:15.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.17:55:15.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.17:55:15.22#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:15.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:15.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:15.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:15.22#ibcon#enter wrdev, iclass 18, count 0 2006.201.17:55:15.22#ibcon#first serial, iclass 18, count 0 2006.201.17:55:15.22#ibcon#enter sib2, iclass 18, count 0 2006.201.17:55:15.22#ibcon#flushed, iclass 18, count 0 2006.201.17:55:15.22#ibcon#about to write, iclass 18, count 0 2006.201.17:55:15.22#ibcon#wrote, iclass 18, count 0 2006.201.17:55:15.22#ibcon#about to read 3, iclass 18, count 0 2006.201.17:55:15.24#ibcon#read 3, iclass 18, count 0 2006.201.17:55:15.24#ibcon#about to read 4, iclass 18, count 0 2006.201.17:55:15.24#ibcon#read 4, iclass 18, count 0 2006.201.17:55:15.24#ibcon#about to read 5, iclass 18, count 0 2006.201.17:55:15.24#ibcon#read 5, iclass 18, count 0 2006.201.17:55:15.24#ibcon#about to read 6, iclass 18, count 0 2006.201.17:55:15.24#ibcon#read 6, iclass 18, count 0 2006.201.17:55:15.24#ibcon#end of sib2, iclass 18, count 0 2006.201.17:55:15.24#ibcon#*mode == 0, iclass 18, count 0 2006.201.17:55:15.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.17:55:15.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.17:55:15.24#ibcon#*before write, iclass 18, count 0 2006.201.17:55:15.24#ibcon#enter sib2, iclass 18, count 0 2006.201.17:55:15.24#ibcon#flushed, iclass 18, count 0 2006.201.17:55:15.24#ibcon#about to write, iclass 18, count 0 2006.201.17:55:15.24#ibcon#wrote, iclass 18, count 0 2006.201.17:55:15.24#ibcon#about to read 3, iclass 18, count 0 2006.201.17:55:15.28#ibcon#read 3, iclass 18, count 0 2006.201.17:55:15.28#ibcon#about to read 4, iclass 18, count 0 2006.201.17:55:15.28#ibcon#read 4, iclass 18, count 0 2006.201.17:55:15.28#ibcon#about to read 5, iclass 18, count 0 2006.201.17:55:15.28#ibcon#read 5, iclass 18, count 0 2006.201.17:55:15.28#ibcon#about to read 6, iclass 18, count 0 2006.201.17:55:15.28#ibcon#read 6, iclass 18, count 0 2006.201.17:55:15.28#ibcon#end of sib2, iclass 18, count 0 2006.201.17:55:15.28#ibcon#*after write, iclass 18, count 0 2006.201.17:55:15.28#ibcon#*before return 0, iclass 18, count 0 2006.201.17:55:15.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:15.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.17:55:15.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.17:55:15.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.17:55:15.28$vck44/vb=6,4 2006.201.17:55:15.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.17:55:15.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.17:55:15.28#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:15.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:15.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:15.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:15.34#ibcon#enter wrdev, iclass 20, count 2 2006.201.17:55:15.34#ibcon#first serial, iclass 20, count 2 2006.201.17:55:15.34#ibcon#enter sib2, iclass 20, count 2 2006.201.17:55:15.34#ibcon#flushed, iclass 20, count 2 2006.201.17:55:15.34#ibcon#about to write, iclass 20, count 2 2006.201.17:55:15.34#ibcon#wrote, iclass 20, count 2 2006.201.17:55:15.34#ibcon#about to read 3, iclass 20, count 2 2006.201.17:55:15.36#ibcon#read 3, iclass 20, count 2 2006.201.17:55:15.36#ibcon#about to read 4, iclass 20, count 2 2006.201.17:55:15.36#ibcon#read 4, iclass 20, count 2 2006.201.17:55:15.36#ibcon#about to read 5, iclass 20, count 2 2006.201.17:55:15.36#ibcon#read 5, iclass 20, count 2 2006.201.17:55:15.36#ibcon#about to read 6, iclass 20, count 2 2006.201.17:55:15.36#ibcon#read 6, iclass 20, count 2 2006.201.17:55:15.36#ibcon#end of sib2, iclass 20, count 2 2006.201.17:55:15.36#ibcon#*mode == 0, iclass 20, count 2 2006.201.17:55:15.36#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.17:55:15.36#ibcon#[27=AT06-04\r\n] 2006.201.17:55:15.36#ibcon#*before write, iclass 20, count 2 2006.201.17:55:15.36#ibcon#enter sib2, iclass 20, count 2 2006.201.17:55:15.36#ibcon#flushed, iclass 20, count 2 2006.201.17:55:15.36#ibcon#about to write, iclass 20, count 2 2006.201.17:55:15.36#ibcon#wrote, iclass 20, count 2 2006.201.17:55:15.36#ibcon#about to read 3, iclass 20, count 2 2006.201.17:55:15.39#ibcon#read 3, iclass 20, count 2 2006.201.17:55:15.39#ibcon#about to read 4, iclass 20, count 2 2006.201.17:55:15.39#ibcon#read 4, iclass 20, count 2 2006.201.17:55:15.39#ibcon#about to read 5, iclass 20, count 2 2006.201.17:55:15.39#ibcon#read 5, iclass 20, count 2 2006.201.17:55:15.39#ibcon#about to read 6, iclass 20, count 2 2006.201.17:55:15.39#ibcon#read 6, iclass 20, count 2 2006.201.17:55:15.39#ibcon#end of sib2, iclass 20, count 2 2006.201.17:55:15.39#ibcon#*after write, iclass 20, count 2 2006.201.17:55:15.39#ibcon#*before return 0, iclass 20, count 2 2006.201.17:55:15.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:15.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:55:15.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.17:55:15.39#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:15.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:15.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:15.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:15.51#ibcon#enter wrdev, iclass 20, count 0 2006.201.17:55:15.51#ibcon#first serial, iclass 20, count 0 2006.201.17:55:15.51#ibcon#enter sib2, iclass 20, count 0 2006.201.17:55:15.51#ibcon#flushed, iclass 20, count 0 2006.201.17:55:15.51#ibcon#about to write, iclass 20, count 0 2006.201.17:55:15.51#ibcon#wrote, iclass 20, count 0 2006.201.17:55:15.51#ibcon#about to read 3, iclass 20, count 0 2006.201.17:55:15.53#ibcon#read 3, iclass 20, count 0 2006.201.17:55:15.53#ibcon#about to read 4, iclass 20, count 0 2006.201.17:55:15.53#ibcon#read 4, iclass 20, count 0 2006.201.17:55:15.53#ibcon#about to read 5, iclass 20, count 0 2006.201.17:55:15.53#ibcon#read 5, iclass 20, count 0 2006.201.17:55:15.53#ibcon#about to read 6, iclass 20, count 0 2006.201.17:55:15.53#ibcon#read 6, iclass 20, count 0 2006.201.17:55:15.53#ibcon#end of sib2, iclass 20, count 0 2006.201.17:55:15.53#ibcon#*mode == 0, iclass 20, count 0 2006.201.17:55:15.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.17:55:15.53#ibcon#[27=USB\r\n] 2006.201.17:55:15.53#ibcon#*before write, iclass 20, count 0 2006.201.17:55:15.53#ibcon#enter sib2, iclass 20, count 0 2006.201.17:55:15.53#ibcon#flushed, iclass 20, count 0 2006.201.17:55:15.53#ibcon#about to write, iclass 20, count 0 2006.201.17:55:15.53#ibcon#wrote, iclass 20, count 0 2006.201.17:55:15.53#ibcon#about to read 3, iclass 20, count 0 2006.201.17:55:15.56#ibcon#read 3, iclass 20, count 0 2006.201.17:55:15.56#ibcon#about to read 4, iclass 20, count 0 2006.201.17:55:15.56#ibcon#read 4, iclass 20, count 0 2006.201.17:55:15.56#ibcon#about to read 5, iclass 20, count 0 2006.201.17:55:15.56#ibcon#read 5, iclass 20, count 0 2006.201.17:55:15.56#ibcon#about to read 6, iclass 20, count 0 2006.201.17:55:15.56#ibcon#read 6, iclass 20, count 0 2006.201.17:55:15.56#ibcon#end of sib2, iclass 20, count 0 2006.201.17:55:15.56#ibcon#*after write, iclass 20, count 0 2006.201.17:55:15.56#ibcon#*before return 0, iclass 20, count 0 2006.201.17:55:15.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:15.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:55:15.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.17:55:15.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.17:55:15.56$vck44/vblo=7,734.99 2006.201.17:55:15.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.17:55:15.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.17:55:15.56#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:15.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:15.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:15.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:15.56#ibcon#enter wrdev, iclass 22, count 0 2006.201.17:55:15.56#ibcon#first serial, iclass 22, count 0 2006.201.17:55:15.56#ibcon#enter sib2, iclass 22, count 0 2006.201.17:55:15.56#ibcon#flushed, iclass 22, count 0 2006.201.17:55:15.56#ibcon#about to write, iclass 22, count 0 2006.201.17:55:15.56#ibcon#wrote, iclass 22, count 0 2006.201.17:55:15.56#ibcon#about to read 3, iclass 22, count 0 2006.201.17:55:15.58#ibcon#read 3, iclass 22, count 0 2006.201.17:55:15.58#ibcon#about to read 4, iclass 22, count 0 2006.201.17:55:15.58#ibcon#read 4, iclass 22, count 0 2006.201.17:55:15.58#ibcon#about to read 5, iclass 22, count 0 2006.201.17:55:15.58#ibcon#read 5, iclass 22, count 0 2006.201.17:55:15.58#ibcon#about to read 6, iclass 22, count 0 2006.201.17:55:15.58#ibcon#read 6, iclass 22, count 0 2006.201.17:55:15.58#ibcon#end of sib2, iclass 22, count 0 2006.201.17:55:15.58#ibcon#*mode == 0, iclass 22, count 0 2006.201.17:55:15.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.17:55:15.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.17:55:15.58#ibcon#*before write, iclass 22, count 0 2006.201.17:55:15.58#ibcon#enter sib2, iclass 22, count 0 2006.201.17:55:15.58#ibcon#flushed, iclass 22, count 0 2006.201.17:55:15.58#ibcon#about to write, iclass 22, count 0 2006.201.17:55:15.58#ibcon#wrote, iclass 22, count 0 2006.201.17:55:15.58#ibcon#about to read 3, iclass 22, count 0 2006.201.17:55:15.63#ibcon#read 3, iclass 22, count 0 2006.201.17:55:15.63#ibcon#about to read 4, iclass 22, count 0 2006.201.17:55:15.63#ibcon#read 4, iclass 22, count 0 2006.201.17:55:15.63#ibcon#about to read 5, iclass 22, count 0 2006.201.17:55:15.63#ibcon#read 5, iclass 22, count 0 2006.201.17:55:15.63#ibcon#about to read 6, iclass 22, count 0 2006.201.17:55:15.63#ibcon#read 6, iclass 22, count 0 2006.201.17:55:15.63#ibcon#end of sib2, iclass 22, count 0 2006.201.17:55:15.63#ibcon#*after write, iclass 22, count 0 2006.201.17:55:15.63#ibcon#*before return 0, iclass 22, count 0 2006.201.17:55:15.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:15.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.17:55:15.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.17:55:15.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.17:55:15.63$vck44/vb=7,4 2006.201.17:55:15.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.17:55:15.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.17:55:15.63#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:15.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:15.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:15.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:15.68#ibcon#enter wrdev, iclass 24, count 2 2006.201.17:55:15.68#ibcon#first serial, iclass 24, count 2 2006.201.17:55:15.68#ibcon#enter sib2, iclass 24, count 2 2006.201.17:55:15.68#ibcon#flushed, iclass 24, count 2 2006.201.17:55:15.68#ibcon#about to write, iclass 24, count 2 2006.201.17:55:15.68#ibcon#wrote, iclass 24, count 2 2006.201.17:55:15.68#ibcon#about to read 3, iclass 24, count 2 2006.201.17:55:15.69#abcon#<5=/16 0.6 1.4 20.581001002.4\r\n> 2006.201.17:55:15.70#ibcon#read 3, iclass 24, count 2 2006.201.17:55:15.70#ibcon#about to read 4, iclass 24, count 2 2006.201.17:55:15.70#ibcon#read 4, iclass 24, count 2 2006.201.17:55:15.70#ibcon#about to read 5, iclass 24, count 2 2006.201.17:55:15.70#ibcon#read 5, iclass 24, count 2 2006.201.17:55:15.70#ibcon#about to read 6, iclass 24, count 2 2006.201.17:55:15.70#ibcon#read 6, iclass 24, count 2 2006.201.17:55:15.70#ibcon#end of sib2, iclass 24, count 2 2006.201.17:55:15.70#ibcon#*mode == 0, iclass 24, count 2 2006.201.17:55:15.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.17:55:15.70#ibcon#[27=AT07-04\r\n] 2006.201.17:55:15.70#ibcon#*before write, iclass 24, count 2 2006.201.17:55:15.70#ibcon#enter sib2, iclass 24, count 2 2006.201.17:55:15.70#ibcon#flushed, iclass 24, count 2 2006.201.17:55:15.70#ibcon#about to write, iclass 24, count 2 2006.201.17:55:15.70#ibcon#wrote, iclass 24, count 2 2006.201.17:55:15.70#ibcon#about to read 3, iclass 24, count 2 2006.201.17:55:15.71#abcon#{5=INTERFACE CLEAR} 2006.201.17:55:15.73#ibcon#read 3, iclass 24, count 2 2006.201.17:55:15.73#ibcon#about to read 4, iclass 24, count 2 2006.201.17:55:15.73#ibcon#read 4, iclass 24, count 2 2006.201.17:55:15.73#ibcon#about to read 5, iclass 24, count 2 2006.201.17:55:15.73#ibcon#read 5, iclass 24, count 2 2006.201.17:55:15.73#ibcon#about to read 6, iclass 24, count 2 2006.201.17:55:15.73#ibcon#read 6, iclass 24, count 2 2006.201.17:55:15.73#ibcon#end of sib2, iclass 24, count 2 2006.201.17:55:15.73#ibcon#*after write, iclass 24, count 2 2006.201.17:55:15.73#ibcon#*before return 0, iclass 24, count 2 2006.201.17:55:15.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:15.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.17:55:15.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.17:55:15.73#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:15.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:15.77#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:55:15.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:15.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:15.85#ibcon#enter wrdev, iclass 24, count 0 2006.201.17:55:15.85#ibcon#first serial, iclass 24, count 0 2006.201.17:55:15.85#ibcon#enter sib2, iclass 24, count 0 2006.201.17:55:15.85#ibcon#flushed, iclass 24, count 0 2006.201.17:55:15.85#ibcon#about to write, iclass 24, count 0 2006.201.17:55:15.85#ibcon#wrote, iclass 24, count 0 2006.201.17:55:15.85#ibcon#about to read 3, iclass 24, count 0 2006.201.17:55:15.87#ibcon#read 3, iclass 24, count 0 2006.201.17:55:15.87#ibcon#about to read 4, iclass 24, count 0 2006.201.17:55:15.87#ibcon#read 4, iclass 24, count 0 2006.201.17:55:15.87#ibcon#about to read 5, iclass 24, count 0 2006.201.17:55:15.87#ibcon#read 5, iclass 24, count 0 2006.201.17:55:15.87#ibcon#about to read 6, iclass 24, count 0 2006.201.17:55:15.87#ibcon#read 6, iclass 24, count 0 2006.201.17:55:15.87#ibcon#end of sib2, iclass 24, count 0 2006.201.17:55:15.87#ibcon#*mode == 0, iclass 24, count 0 2006.201.17:55:15.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.17:55:15.87#ibcon#[27=USB\r\n] 2006.201.17:55:15.87#ibcon#*before write, iclass 24, count 0 2006.201.17:55:15.87#ibcon#enter sib2, iclass 24, count 0 2006.201.17:55:15.87#ibcon#flushed, iclass 24, count 0 2006.201.17:55:15.87#ibcon#about to write, iclass 24, count 0 2006.201.17:55:15.87#ibcon#wrote, iclass 24, count 0 2006.201.17:55:15.87#ibcon#about to read 3, iclass 24, count 0 2006.201.17:55:15.90#ibcon#read 3, iclass 24, count 0 2006.201.17:55:15.90#ibcon#about to read 4, iclass 24, count 0 2006.201.17:55:15.90#ibcon#read 4, iclass 24, count 0 2006.201.17:55:15.90#ibcon#about to read 5, iclass 24, count 0 2006.201.17:55:15.90#ibcon#read 5, iclass 24, count 0 2006.201.17:55:15.90#ibcon#about to read 6, iclass 24, count 0 2006.201.17:55:15.90#ibcon#read 6, iclass 24, count 0 2006.201.17:55:15.90#ibcon#end of sib2, iclass 24, count 0 2006.201.17:55:15.90#ibcon#*after write, iclass 24, count 0 2006.201.17:55:15.90#ibcon#*before return 0, iclass 24, count 0 2006.201.17:55:15.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:15.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.17:55:15.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.17:55:15.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.17:55:15.90$vck44/vblo=8,744.99 2006.201.17:55:15.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.17:55:15.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.17:55:15.90#ibcon#ireg 17 cls_cnt 0 2006.201.17:55:15.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:15.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:15.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:15.90#ibcon#enter wrdev, iclass 30, count 0 2006.201.17:55:15.90#ibcon#first serial, iclass 30, count 0 2006.201.17:55:15.90#ibcon#enter sib2, iclass 30, count 0 2006.201.17:55:15.90#ibcon#flushed, iclass 30, count 0 2006.201.17:55:15.90#ibcon#about to write, iclass 30, count 0 2006.201.17:55:15.90#ibcon#wrote, iclass 30, count 0 2006.201.17:55:15.90#ibcon#about to read 3, iclass 30, count 0 2006.201.17:55:15.92#ibcon#read 3, iclass 30, count 0 2006.201.17:55:15.92#ibcon#about to read 4, iclass 30, count 0 2006.201.17:55:15.92#ibcon#read 4, iclass 30, count 0 2006.201.17:55:15.92#ibcon#about to read 5, iclass 30, count 0 2006.201.17:55:15.92#ibcon#read 5, iclass 30, count 0 2006.201.17:55:15.92#ibcon#about to read 6, iclass 30, count 0 2006.201.17:55:15.92#ibcon#read 6, iclass 30, count 0 2006.201.17:55:15.92#ibcon#end of sib2, iclass 30, count 0 2006.201.17:55:15.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.17:55:15.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.17:55:15.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.17:55:15.92#ibcon#*before write, iclass 30, count 0 2006.201.17:55:15.92#ibcon#enter sib2, iclass 30, count 0 2006.201.17:55:15.92#ibcon#flushed, iclass 30, count 0 2006.201.17:55:15.92#ibcon#about to write, iclass 30, count 0 2006.201.17:55:15.92#ibcon#wrote, iclass 30, count 0 2006.201.17:55:15.92#ibcon#about to read 3, iclass 30, count 0 2006.201.17:55:15.96#ibcon#read 3, iclass 30, count 0 2006.201.17:55:15.96#ibcon#about to read 4, iclass 30, count 0 2006.201.17:55:15.96#ibcon#read 4, iclass 30, count 0 2006.201.17:55:15.96#ibcon#about to read 5, iclass 30, count 0 2006.201.17:55:15.96#ibcon#read 5, iclass 30, count 0 2006.201.17:55:15.96#ibcon#about to read 6, iclass 30, count 0 2006.201.17:55:15.96#ibcon#read 6, iclass 30, count 0 2006.201.17:55:15.96#ibcon#end of sib2, iclass 30, count 0 2006.201.17:55:15.96#ibcon#*after write, iclass 30, count 0 2006.201.17:55:15.96#ibcon#*before return 0, iclass 30, count 0 2006.201.17:55:15.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:15.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.17:55:15.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.17:55:15.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.17:55:15.96$vck44/vb=8,4 2006.201.17:55:15.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.17:55:15.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.17:55:15.96#ibcon#ireg 11 cls_cnt 2 2006.201.17:55:15.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:16.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:16.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:16.02#ibcon#enter wrdev, iclass 32, count 2 2006.201.17:55:16.02#ibcon#first serial, iclass 32, count 2 2006.201.17:55:16.02#ibcon#enter sib2, iclass 32, count 2 2006.201.17:55:16.02#ibcon#flushed, iclass 32, count 2 2006.201.17:55:16.02#ibcon#about to write, iclass 32, count 2 2006.201.17:55:16.02#ibcon#wrote, iclass 32, count 2 2006.201.17:55:16.02#ibcon#about to read 3, iclass 32, count 2 2006.201.17:55:16.04#ibcon#read 3, iclass 32, count 2 2006.201.17:55:16.04#ibcon#about to read 4, iclass 32, count 2 2006.201.17:55:16.04#ibcon#read 4, iclass 32, count 2 2006.201.17:55:16.04#ibcon#about to read 5, iclass 32, count 2 2006.201.17:55:16.04#ibcon#read 5, iclass 32, count 2 2006.201.17:55:16.04#ibcon#about to read 6, iclass 32, count 2 2006.201.17:55:16.04#ibcon#read 6, iclass 32, count 2 2006.201.17:55:16.04#ibcon#end of sib2, iclass 32, count 2 2006.201.17:55:16.04#ibcon#*mode == 0, iclass 32, count 2 2006.201.17:55:16.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.17:55:16.04#ibcon#[27=AT08-04\r\n] 2006.201.17:55:16.04#ibcon#*before write, iclass 32, count 2 2006.201.17:55:16.04#ibcon#enter sib2, iclass 32, count 2 2006.201.17:55:16.04#ibcon#flushed, iclass 32, count 2 2006.201.17:55:16.04#ibcon#about to write, iclass 32, count 2 2006.201.17:55:16.04#ibcon#wrote, iclass 32, count 2 2006.201.17:55:16.04#ibcon#about to read 3, iclass 32, count 2 2006.201.17:55:16.07#ibcon#read 3, iclass 32, count 2 2006.201.17:55:16.07#ibcon#about to read 4, iclass 32, count 2 2006.201.17:55:16.07#ibcon#read 4, iclass 32, count 2 2006.201.17:55:16.07#ibcon#about to read 5, iclass 32, count 2 2006.201.17:55:16.07#ibcon#read 5, iclass 32, count 2 2006.201.17:55:16.07#ibcon#about to read 6, iclass 32, count 2 2006.201.17:55:16.07#ibcon#read 6, iclass 32, count 2 2006.201.17:55:16.07#ibcon#end of sib2, iclass 32, count 2 2006.201.17:55:16.07#ibcon#*after write, iclass 32, count 2 2006.201.17:55:16.07#ibcon#*before return 0, iclass 32, count 2 2006.201.17:55:16.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:16.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.17:55:16.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.17:55:16.07#ibcon#ireg 7 cls_cnt 0 2006.201.17:55:16.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:16.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:16.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:16.19#ibcon#enter wrdev, iclass 32, count 0 2006.201.17:55:16.19#ibcon#first serial, iclass 32, count 0 2006.201.17:55:16.19#ibcon#enter sib2, iclass 32, count 0 2006.201.17:55:16.19#ibcon#flushed, iclass 32, count 0 2006.201.17:55:16.19#ibcon#about to write, iclass 32, count 0 2006.201.17:55:16.19#ibcon#wrote, iclass 32, count 0 2006.201.17:55:16.19#ibcon#about to read 3, iclass 32, count 0 2006.201.17:55:16.21#ibcon#read 3, iclass 32, count 0 2006.201.17:55:16.21#ibcon#about to read 4, iclass 32, count 0 2006.201.17:55:16.21#ibcon#read 4, iclass 32, count 0 2006.201.17:55:16.21#ibcon#about to read 5, iclass 32, count 0 2006.201.17:55:16.21#ibcon#read 5, iclass 32, count 0 2006.201.17:55:16.21#ibcon#about to read 6, iclass 32, count 0 2006.201.17:55:16.21#ibcon#read 6, iclass 32, count 0 2006.201.17:55:16.21#ibcon#end of sib2, iclass 32, count 0 2006.201.17:55:16.21#ibcon#*mode == 0, iclass 32, count 0 2006.201.17:55:16.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.17:55:16.21#ibcon#[27=USB\r\n] 2006.201.17:55:16.21#ibcon#*before write, iclass 32, count 0 2006.201.17:55:16.21#ibcon#enter sib2, iclass 32, count 0 2006.201.17:55:16.21#ibcon#flushed, iclass 32, count 0 2006.201.17:55:16.21#ibcon#about to write, iclass 32, count 0 2006.201.17:55:16.21#ibcon#wrote, iclass 32, count 0 2006.201.17:55:16.21#ibcon#about to read 3, iclass 32, count 0 2006.201.17:55:16.24#ibcon#read 3, iclass 32, count 0 2006.201.17:55:16.24#ibcon#about to read 4, iclass 32, count 0 2006.201.17:55:16.24#ibcon#read 4, iclass 32, count 0 2006.201.17:55:16.24#ibcon#about to read 5, iclass 32, count 0 2006.201.17:55:16.24#ibcon#read 5, iclass 32, count 0 2006.201.17:55:16.24#ibcon#about to read 6, iclass 32, count 0 2006.201.17:55:16.24#ibcon#read 6, iclass 32, count 0 2006.201.17:55:16.24#ibcon#end of sib2, iclass 32, count 0 2006.201.17:55:16.24#ibcon#*after write, iclass 32, count 0 2006.201.17:55:16.24#ibcon#*before return 0, iclass 32, count 0 2006.201.17:55:16.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:16.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.17:55:16.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.17:55:16.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.17:55:16.24$vck44/vabw=wide 2006.201.17:55:16.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.17:55:16.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.17:55:16.24#ibcon#ireg 8 cls_cnt 0 2006.201.17:55:16.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:16.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:16.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:16.24#ibcon#enter wrdev, iclass 34, count 0 2006.201.17:55:16.24#ibcon#first serial, iclass 34, count 0 2006.201.17:55:16.24#ibcon#enter sib2, iclass 34, count 0 2006.201.17:55:16.24#ibcon#flushed, iclass 34, count 0 2006.201.17:55:16.24#ibcon#about to write, iclass 34, count 0 2006.201.17:55:16.24#ibcon#wrote, iclass 34, count 0 2006.201.17:55:16.24#ibcon#about to read 3, iclass 34, count 0 2006.201.17:55:16.26#ibcon#read 3, iclass 34, count 0 2006.201.17:55:16.26#ibcon#about to read 4, iclass 34, count 0 2006.201.17:55:16.26#ibcon#read 4, iclass 34, count 0 2006.201.17:55:16.26#ibcon#about to read 5, iclass 34, count 0 2006.201.17:55:16.26#ibcon#read 5, iclass 34, count 0 2006.201.17:55:16.26#ibcon#about to read 6, iclass 34, count 0 2006.201.17:55:16.26#ibcon#read 6, iclass 34, count 0 2006.201.17:55:16.26#ibcon#end of sib2, iclass 34, count 0 2006.201.17:55:16.26#ibcon#*mode == 0, iclass 34, count 0 2006.201.17:55:16.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.17:55:16.26#ibcon#[25=BW32\r\n] 2006.201.17:55:16.26#ibcon#*before write, iclass 34, count 0 2006.201.17:55:16.26#ibcon#enter sib2, iclass 34, count 0 2006.201.17:55:16.26#ibcon#flushed, iclass 34, count 0 2006.201.17:55:16.26#ibcon#about to write, iclass 34, count 0 2006.201.17:55:16.26#ibcon#wrote, iclass 34, count 0 2006.201.17:55:16.26#ibcon#about to read 3, iclass 34, count 0 2006.201.17:55:16.29#ibcon#read 3, iclass 34, count 0 2006.201.17:55:16.29#ibcon#about to read 4, iclass 34, count 0 2006.201.17:55:16.29#ibcon#read 4, iclass 34, count 0 2006.201.17:55:16.29#ibcon#about to read 5, iclass 34, count 0 2006.201.17:55:16.29#ibcon#read 5, iclass 34, count 0 2006.201.17:55:16.29#ibcon#about to read 6, iclass 34, count 0 2006.201.17:55:16.29#ibcon#read 6, iclass 34, count 0 2006.201.17:55:16.29#ibcon#end of sib2, iclass 34, count 0 2006.201.17:55:16.29#ibcon#*after write, iclass 34, count 0 2006.201.17:55:16.29#ibcon#*before return 0, iclass 34, count 0 2006.201.17:55:16.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:16.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.17:55:16.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.17:55:16.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.17:55:16.29$vck44/vbbw=wide 2006.201.17:55:16.29#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.17:55:16.29#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.17:55:16.29#ibcon#ireg 8 cls_cnt 0 2006.201.17:55:16.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:55:16.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:55:16.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:55:16.36#ibcon#enter wrdev, iclass 36, count 0 2006.201.17:55:16.36#ibcon#first serial, iclass 36, count 0 2006.201.17:55:16.36#ibcon#enter sib2, iclass 36, count 0 2006.201.17:55:16.36#ibcon#flushed, iclass 36, count 0 2006.201.17:55:16.36#ibcon#about to write, iclass 36, count 0 2006.201.17:55:16.36#ibcon#wrote, iclass 36, count 0 2006.201.17:55:16.36#ibcon#about to read 3, iclass 36, count 0 2006.201.17:55:16.38#ibcon#read 3, iclass 36, count 0 2006.201.17:55:16.38#ibcon#about to read 4, iclass 36, count 0 2006.201.17:55:16.38#ibcon#read 4, iclass 36, count 0 2006.201.17:55:16.38#ibcon#about to read 5, iclass 36, count 0 2006.201.17:55:16.38#ibcon#read 5, iclass 36, count 0 2006.201.17:55:16.38#ibcon#about to read 6, iclass 36, count 0 2006.201.17:55:16.38#ibcon#read 6, iclass 36, count 0 2006.201.17:55:16.38#ibcon#end of sib2, iclass 36, count 0 2006.201.17:55:16.38#ibcon#*mode == 0, iclass 36, count 0 2006.201.17:55:16.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.17:55:16.38#ibcon#[27=BW32\r\n] 2006.201.17:55:16.38#ibcon#*before write, iclass 36, count 0 2006.201.17:55:16.38#ibcon#enter sib2, iclass 36, count 0 2006.201.17:55:16.38#ibcon#flushed, iclass 36, count 0 2006.201.17:55:16.38#ibcon#about to write, iclass 36, count 0 2006.201.17:55:16.38#ibcon#wrote, iclass 36, count 0 2006.201.17:55:16.38#ibcon#about to read 3, iclass 36, count 0 2006.201.17:55:16.41#ibcon#read 3, iclass 36, count 0 2006.201.17:55:16.41#ibcon#about to read 4, iclass 36, count 0 2006.201.17:55:16.41#ibcon#read 4, iclass 36, count 0 2006.201.17:55:16.41#ibcon#about to read 5, iclass 36, count 0 2006.201.17:55:16.41#ibcon#read 5, iclass 36, count 0 2006.201.17:55:16.41#ibcon#about to read 6, iclass 36, count 0 2006.201.17:55:16.41#ibcon#read 6, iclass 36, count 0 2006.201.17:55:16.41#ibcon#end of sib2, iclass 36, count 0 2006.201.17:55:16.41#ibcon#*after write, iclass 36, count 0 2006.201.17:55:16.41#ibcon#*before return 0, iclass 36, count 0 2006.201.17:55:16.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:55:16.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.17:55:16.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.17:55:16.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.17:55:16.41$setupk4/ifdk4 2006.201.17:55:16.41$ifdk4/lo= 2006.201.17:55:16.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.17:55:16.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.17:55:16.41$ifdk4/patch= 2006.201.17:55:16.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.17:55:16.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.17:55:16.41$setupk4/!*+20s 2006.201.17:55:25.86#abcon#<5=/16 0.6 1.4 20.581001002.4\r\n> 2006.201.17:55:25.88#abcon#{5=INTERFACE CLEAR} 2006.201.17:55:25.94#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:55:30.90$setupk4/"tpicd 2006.201.17:55:30.90$setupk4/echo=off 2006.201.17:55:30.90$setupk4/xlog=off 2006.201.17:55:30.90:!2006.201.17:55:57 2006.201.17:55:40.14#trakl#Source acquired 2006.201.17:55:42.14#flagr#flagr/antenna,acquired 2006.201.17:55:57.00:preob 2006.201.17:55:58.14/onsource/TRACKING 2006.201.17:55:58.14:!2006.201.17:56:07 2006.201.17:56:07.00:"tape 2006.201.17:56:07.00:"st=record 2006.201.17:56:07.00:data_valid=on 2006.201.17:56:07.00:midob 2006.201.17:56:07.14/onsource/TRACKING 2006.201.17:56:07.14/wx/20.57,1002.4,100 2006.201.17:56:07.32/cable/+6.4761E-03 2006.201.17:56:08.41/va/01,08,usb,yes,48,51 2006.201.17:56:08.41/va/02,07,usb,yes,51,52 2006.201.17:56:08.41/va/03,08,usb,yes,47,49 2006.201.17:56:08.41/va/04,07,usb,yes,53,56 2006.201.17:56:08.41/va/05,04,usb,yes,48,49 2006.201.17:56:08.41/va/06,05,usb,yes,48,48 2006.201.17:56:08.41/va/07,05,usb,yes,46,48 2006.201.17:56:08.41/va/08,04,usb,yes,46,54 2006.201.17:56:08.64/valo/01,524.99,yes,locked 2006.201.17:56:08.64/valo/02,534.99,yes,locked 2006.201.17:56:08.64/valo/03,564.99,yes,locked 2006.201.17:56:08.64/valo/04,624.99,yes,locked 2006.201.17:56:08.64/valo/05,734.99,yes,locked 2006.201.17:56:08.64/valo/06,814.99,yes,locked 2006.201.17:56:08.64/valo/07,864.99,yes,locked 2006.201.17:56:08.64/valo/08,884.99,yes,locked 2006.201.17:56:09.73/vb/01,04,usb,yes,38,35 2006.201.17:56:09.73/vb/02,05,usb,yes,36,35 2006.201.17:56:09.73/vb/03,04,usb,yes,37,41 2006.201.17:56:09.73/vb/04,05,usb,yes,37,36 2006.201.17:56:09.73/vb/05,04,usb,yes,34,36 2006.201.17:56:09.73/vb/06,04,usb,yes,39,34 2006.201.17:56:09.73/vb/07,04,usb,yes,39,39 2006.201.17:56:09.73/vb/08,04,usb,yes,35,40 2006.201.17:56:09.97/vblo/01,629.99,yes,locked 2006.201.17:56:09.97/vblo/02,634.99,yes,locked 2006.201.17:56:09.97/vblo/03,649.99,yes,locked 2006.201.17:56:09.97/vblo/04,679.99,yes,locked 2006.201.17:56:09.97/vblo/05,709.99,yes,locked 2006.201.17:56:09.97/vblo/06,719.99,yes,locked 2006.201.17:56:09.97/vblo/07,734.99,yes,locked 2006.201.17:56:09.97/vblo/08,744.99,yes,locked 2006.201.17:56:10.12/vabw/8 2006.201.17:56:10.27/vbbw/8 2006.201.17:56:10.40/xfe/off,on,14.7 2006.201.17:56:10.77/ifatt/23,28,28,28 2006.201.17:56:11.06/fmout-gps/S +4.59E-07 2006.201.17:56:11.13:!2006.201.17:57:57 2006.201.17:57:57.00:data_valid=off 2006.201.17:57:57.00:"et 2006.201.17:57:57.00:!+3s 2006.201.17:58:00.02:"tape 2006.201.17:58:00.02:postob 2006.201.17:58:00.08/cable/+6.4782E-03 2006.201.17:58:00.08/wx/20.56,1002.3,100 2006.201.17:58:00.16/fmout-gps/S +4.60E-07 2006.201.17:58:00.16:scan_name=201-1759,jd0607,120 2006.201.17:58:00.17:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.201.17:58:01.14#flagr#flagr/antenna,new-source 2006.201.17:58:01.14:checkk5 2006.201.17:58:01.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.17:58:01.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.17:58:02.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.17:58:02.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.17:58:02.99/chk_obsdata//k5ts1/T2011756??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.17:58:03.36/chk_obsdata//k5ts2/T2011756??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.17:58:03.75/chk_obsdata//k5ts3/T2011756??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.17:58:04.12/chk_obsdata//k5ts4/T2011756??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.17:58:04.81/k5log//k5ts1_log_newline 2006.201.17:58:05.52/k5log//k5ts2_log_newline 2006.201.17:58:06.20/k5log//k5ts3_log_newline 2006.201.17:58:06.89/k5log//k5ts4_log_newline 2006.201.17:58:06.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.17:58:06.91:setupk4=1 2006.201.17:58:06.91$setupk4/echo=on 2006.201.17:58:06.91$setupk4/pcalon 2006.201.17:58:06.91$pcalon/"no phase cal control is implemented here 2006.201.17:58:06.91$setupk4/"tpicd=stop 2006.201.17:58:06.91$setupk4/"rec=synch_on 2006.201.17:58:06.91$setupk4/"rec_mode=128 2006.201.17:58:06.91$setupk4/!* 2006.201.17:58:06.91$setupk4/recpk4 2006.201.17:58:06.91$recpk4/recpatch= 2006.201.17:58:06.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.17:58:06.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.17:58:06.92$setupk4/vck44 2006.201.17:58:06.92$vck44/valo=1,524.99 2006.201.17:58:06.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.17:58:06.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.17:58:06.92#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:06.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:06.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:06.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:06.92#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:58:06.92#ibcon#first serial, iclass 33, count 0 2006.201.17:58:06.92#ibcon#enter sib2, iclass 33, count 0 2006.201.17:58:06.92#ibcon#flushed, iclass 33, count 0 2006.201.17:58:06.92#ibcon#about to write, iclass 33, count 0 2006.201.17:58:06.92#ibcon#wrote, iclass 33, count 0 2006.201.17:58:06.92#ibcon#about to read 3, iclass 33, count 0 2006.201.17:58:06.95#ibcon#read 3, iclass 33, count 0 2006.201.17:58:06.95#ibcon#about to read 4, iclass 33, count 0 2006.201.17:58:06.95#ibcon#read 4, iclass 33, count 0 2006.201.17:58:06.95#ibcon#about to read 5, iclass 33, count 0 2006.201.17:58:06.95#ibcon#read 5, iclass 33, count 0 2006.201.17:58:06.95#ibcon#about to read 6, iclass 33, count 0 2006.201.17:58:06.95#ibcon#read 6, iclass 33, count 0 2006.201.17:58:06.95#ibcon#end of sib2, iclass 33, count 0 2006.201.17:58:06.95#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:58:06.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:58:06.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.17:58:06.95#ibcon#*before write, iclass 33, count 0 2006.201.17:58:06.95#ibcon#enter sib2, iclass 33, count 0 2006.201.17:58:06.95#ibcon#flushed, iclass 33, count 0 2006.201.17:58:06.95#ibcon#about to write, iclass 33, count 0 2006.201.17:58:06.95#ibcon#wrote, iclass 33, count 0 2006.201.17:58:06.95#ibcon#about to read 3, iclass 33, count 0 2006.201.17:58:07.00#ibcon#read 3, iclass 33, count 0 2006.201.17:58:07.00#ibcon#about to read 4, iclass 33, count 0 2006.201.17:58:07.00#ibcon#read 4, iclass 33, count 0 2006.201.17:58:07.00#ibcon#about to read 5, iclass 33, count 0 2006.201.17:58:07.00#ibcon#read 5, iclass 33, count 0 2006.201.17:58:07.00#ibcon#about to read 6, iclass 33, count 0 2006.201.17:58:07.00#ibcon#read 6, iclass 33, count 0 2006.201.17:58:07.00#ibcon#end of sib2, iclass 33, count 0 2006.201.17:58:07.00#ibcon#*after write, iclass 33, count 0 2006.201.17:58:07.00#ibcon#*before return 0, iclass 33, count 0 2006.201.17:58:07.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:07.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:07.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:58:07.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:58:07.00$vck44/va=1,8 2006.201.17:58:07.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.17:58:07.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.17:58:07.00#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:07.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:07.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:07.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:07.00#ibcon#enter wrdev, iclass 35, count 2 2006.201.17:58:07.00#ibcon#first serial, iclass 35, count 2 2006.201.17:58:07.00#ibcon#enter sib2, iclass 35, count 2 2006.201.17:58:07.00#ibcon#flushed, iclass 35, count 2 2006.201.17:58:07.00#ibcon#about to write, iclass 35, count 2 2006.201.17:58:07.00#ibcon#wrote, iclass 35, count 2 2006.201.17:58:07.00#ibcon#about to read 3, iclass 35, count 2 2006.201.17:58:07.02#ibcon#read 3, iclass 35, count 2 2006.201.17:58:07.02#ibcon#about to read 4, iclass 35, count 2 2006.201.17:58:07.02#ibcon#read 4, iclass 35, count 2 2006.201.17:58:07.02#ibcon#about to read 5, iclass 35, count 2 2006.201.17:58:07.02#ibcon#read 5, iclass 35, count 2 2006.201.17:58:07.02#ibcon#about to read 6, iclass 35, count 2 2006.201.17:58:07.02#ibcon#read 6, iclass 35, count 2 2006.201.17:58:07.02#ibcon#end of sib2, iclass 35, count 2 2006.201.17:58:07.02#ibcon#*mode == 0, iclass 35, count 2 2006.201.17:58:07.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.17:58:07.02#ibcon#[25=AT01-08\r\n] 2006.201.17:58:07.02#ibcon#*before write, iclass 35, count 2 2006.201.17:58:07.02#ibcon#enter sib2, iclass 35, count 2 2006.201.17:58:07.02#ibcon#flushed, iclass 35, count 2 2006.201.17:58:07.02#ibcon#about to write, iclass 35, count 2 2006.201.17:58:07.02#ibcon#wrote, iclass 35, count 2 2006.201.17:58:07.02#ibcon#about to read 3, iclass 35, count 2 2006.201.17:58:07.05#ibcon#read 3, iclass 35, count 2 2006.201.17:58:07.05#ibcon#about to read 4, iclass 35, count 2 2006.201.17:58:07.05#ibcon#read 4, iclass 35, count 2 2006.201.17:58:07.05#ibcon#about to read 5, iclass 35, count 2 2006.201.17:58:07.05#ibcon#read 5, iclass 35, count 2 2006.201.17:58:07.05#ibcon#about to read 6, iclass 35, count 2 2006.201.17:58:07.05#ibcon#read 6, iclass 35, count 2 2006.201.17:58:07.05#ibcon#end of sib2, iclass 35, count 2 2006.201.17:58:07.05#ibcon#*after write, iclass 35, count 2 2006.201.17:58:07.05#ibcon#*before return 0, iclass 35, count 2 2006.201.17:58:07.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:07.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:07.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.17:58:07.05#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:07.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:07.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:07.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:07.17#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:58:07.17#ibcon#first serial, iclass 35, count 0 2006.201.17:58:07.17#ibcon#enter sib2, iclass 35, count 0 2006.201.17:58:07.17#ibcon#flushed, iclass 35, count 0 2006.201.17:58:07.17#ibcon#about to write, iclass 35, count 0 2006.201.17:58:07.17#ibcon#wrote, iclass 35, count 0 2006.201.17:58:07.17#ibcon#about to read 3, iclass 35, count 0 2006.201.17:58:07.19#ibcon#read 3, iclass 35, count 0 2006.201.17:58:07.19#ibcon#about to read 4, iclass 35, count 0 2006.201.17:58:07.19#ibcon#read 4, iclass 35, count 0 2006.201.17:58:07.19#ibcon#about to read 5, iclass 35, count 0 2006.201.17:58:07.19#ibcon#read 5, iclass 35, count 0 2006.201.17:58:07.19#ibcon#about to read 6, iclass 35, count 0 2006.201.17:58:07.19#ibcon#read 6, iclass 35, count 0 2006.201.17:58:07.19#ibcon#end of sib2, iclass 35, count 0 2006.201.17:58:07.19#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:58:07.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:58:07.19#ibcon#[25=USB\r\n] 2006.201.17:58:07.19#ibcon#*before write, iclass 35, count 0 2006.201.17:58:07.19#ibcon#enter sib2, iclass 35, count 0 2006.201.17:58:07.19#ibcon#flushed, iclass 35, count 0 2006.201.17:58:07.19#ibcon#about to write, iclass 35, count 0 2006.201.17:58:07.19#ibcon#wrote, iclass 35, count 0 2006.201.17:58:07.19#ibcon#about to read 3, iclass 35, count 0 2006.201.17:58:07.22#ibcon#read 3, iclass 35, count 0 2006.201.17:58:07.22#ibcon#about to read 4, iclass 35, count 0 2006.201.17:58:07.22#ibcon#read 4, iclass 35, count 0 2006.201.17:58:07.22#ibcon#about to read 5, iclass 35, count 0 2006.201.17:58:07.22#ibcon#read 5, iclass 35, count 0 2006.201.17:58:07.22#ibcon#about to read 6, iclass 35, count 0 2006.201.17:58:07.22#ibcon#read 6, iclass 35, count 0 2006.201.17:58:07.22#ibcon#end of sib2, iclass 35, count 0 2006.201.17:58:07.22#ibcon#*after write, iclass 35, count 0 2006.201.17:58:07.22#ibcon#*before return 0, iclass 35, count 0 2006.201.17:58:07.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:07.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:07.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:58:07.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:58:07.22$vck44/valo=2,534.99 2006.201.17:58:07.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.17:58:07.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.17:58:07.22#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:07.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:07.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:07.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:07.22#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:58:07.22#ibcon#first serial, iclass 37, count 0 2006.201.17:58:07.22#ibcon#enter sib2, iclass 37, count 0 2006.201.17:58:07.22#ibcon#flushed, iclass 37, count 0 2006.201.17:58:07.22#ibcon#about to write, iclass 37, count 0 2006.201.17:58:07.22#ibcon#wrote, iclass 37, count 0 2006.201.17:58:07.22#ibcon#about to read 3, iclass 37, count 0 2006.201.17:58:07.24#ibcon#read 3, iclass 37, count 0 2006.201.17:58:07.24#ibcon#about to read 4, iclass 37, count 0 2006.201.17:58:07.24#ibcon#read 4, iclass 37, count 0 2006.201.17:58:07.24#ibcon#about to read 5, iclass 37, count 0 2006.201.17:58:07.24#ibcon#read 5, iclass 37, count 0 2006.201.17:58:07.24#ibcon#about to read 6, iclass 37, count 0 2006.201.17:58:07.24#ibcon#read 6, iclass 37, count 0 2006.201.17:58:07.24#ibcon#end of sib2, iclass 37, count 0 2006.201.17:58:07.24#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:58:07.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:58:07.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.17:58:07.24#ibcon#*before write, iclass 37, count 0 2006.201.17:58:07.24#ibcon#enter sib2, iclass 37, count 0 2006.201.17:58:07.24#ibcon#flushed, iclass 37, count 0 2006.201.17:58:07.24#ibcon#about to write, iclass 37, count 0 2006.201.17:58:07.24#ibcon#wrote, iclass 37, count 0 2006.201.17:58:07.24#ibcon#about to read 3, iclass 37, count 0 2006.201.17:58:07.28#ibcon#read 3, iclass 37, count 0 2006.201.17:58:07.28#ibcon#about to read 4, iclass 37, count 0 2006.201.17:58:07.28#ibcon#read 4, iclass 37, count 0 2006.201.17:58:07.28#ibcon#about to read 5, iclass 37, count 0 2006.201.17:58:07.28#ibcon#read 5, iclass 37, count 0 2006.201.17:58:07.28#ibcon#about to read 6, iclass 37, count 0 2006.201.17:58:07.28#ibcon#read 6, iclass 37, count 0 2006.201.17:58:07.28#ibcon#end of sib2, iclass 37, count 0 2006.201.17:58:07.28#ibcon#*after write, iclass 37, count 0 2006.201.17:58:07.28#ibcon#*before return 0, iclass 37, count 0 2006.201.17:58:07.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:07.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:07.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:58:07.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:58:07.28$vck44/va=2,7 2006.201.17:58:07.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.17:58:07.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.17:58:07.28#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:07.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:07.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:07.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:07.34#ibcon#enter wrdev, iclass 39, count 2 2006.201.17:58:07.34#ibcon#first serial, iclass 39, count 2 2006.201.17:58:07.34#ibcon#enter sib2, iclass 39, count 2 2006.201.17:58:07.34#ibcon#flushed, iclass 39, count 2 2006.201.17:58:07.34#ibcon#about to write, iclass 39, count 2 2006.201.17:58:07.34#ibcon#wrote, iclass 39, count 2 2006.201.17:58:07.34#ibcon#about to read 3, iclass 39, count 2 2006.201.17:58:07.36#ibcon#read 3, iclass 39, count 2 2006.201.17:58:07.36#ibcon#about to read 4, iclass 39, count 2 2006.201.17:58:07.36#ibcon#read 4, iclass 39, count 2 2006.201.17:58:07.36#ibcon#about to read 5, iclass 39, count 2 2006.201.17:58:07.36#ibcon#read 5, iclass 39, count 2 2006.201.17:58:07.36#ibcon#about to read 6, iclass 39, count 2 2006.201.17:58:07.36#ibcon#read 6, iclass 39, count 2 2006.201.17:58:07.36#ibcon#end of sib2, iclass 39, count 2 2006.201.17:58:07.36#ibcon#*mode == 0, iclass 39, count 2 2006.201.17:58:07.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.17:58:07.36#ibcon#[25=AT02-07\r\n] 2006.201.17:58:07.36#ibcon#*before write, iclass 39, count 2 2006.201.17:58:07.36#ibcon#enter sib2, iclass 39, count 2 2006.201.17:58:07.36#ibcon#flushed, iclass 39, count 2 2006.201.17:58:07.36#ibcon#about to write, iclass 39, count 2 2006.201.17:58:07.36#ibcon#wrote, iclass 39, count 2 2006.201.17:58:07.36#ibcon#about to read 3, iclass 39, count 2 2006.201.17:58:07.39#ibcon#read 3, iclass 39, count 2 2006.201.17:58:07.39#ibcon#about to read 4, iclass 39, count 2 2006.201.17:58:07.39#ibcon#read 4, iclass 39, count 2 2006.201.17:58:07.39#ibcon#about to read 5, iclass 39, count 2 2006.201.17:58:07.39#ibcon#read 5, iclass 39, count 2 2006.201.17:58:07.39#ibcon#about to read 6, iclass 39, count 2 2006.201.17:58:07.39#ibcon#read 6, iclass 39, count 2 2006.201.17:58:07.39#ibcon#end of sib2, iclass 39, count 2 2006.201.17:58:07.39#ibcon#*after write, iclass 39, count 2 2006.201.17:58:07.39#ibcon#*before return 0, iclass 39, count 2 2006.201.17:58:07.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:07.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:07.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.17:58:07.39#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:07.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:07.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:07.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:07.51#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:58:07.51#ibcon#first serial, iclass 39, count 0 2006.201.17:58:07.51#ibcon#enter sib2, iclass 39, count 0 2006.201.17:58:07.51#ibcon#flushed, iclass 39, count 0 2006.201.17:58:07.51#ibcon#about to write, iclass 39, count 0 2006.201.17:58:07.51#ibcon#wrote, iclass 39, count 0 2006.201.17:58:07.51#ibcon#about to read 3, iclass 39, count 0 2006.201.17:58:07.53#ibcon#read 3, iclass 39, count 0 2006.201.17:58:07.53#ibcon#about to read 4, iclass 39, count 0 2006.201.17:58:07.53#ibcon#read 4, iclass 39, count 0 2006.201.17:58:07.53#ibcon#about to read 5, iclass 39, count 0 2006.201.17:58:07.53#ibcon#read 5, iclass 39, count 0 2006.201.17:58:07.53#ibcon#about to read 6, iclass 39, count 0 2006.201.17:58:07.53#ibcon#read 6, iclass 39, count 0 2006.201.17:58:07.53#ibcon#end of sib2, iclass 39, count 0 2006.201.17:58:07.53#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:58:07.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:58:07.53#ibcon#[25=USB\r\n] 2006.201.17:58:07.53#ibcon#*before write, iclass 39, count 0 2006.201.17:58:07.53#ibcon#enter sib2, iclass 39, count 0 2006.201.17:58:07.53#ibcon#flushed, iclass 39, count 0 2006.201.17:58:07.53#ibcon#about to write, iclass 39, count 0 2006.201.17:58:07.53#ibcon#wrote, iclass 39, count 0 2006.201.17:58:07.53#ibcon#about to read 3, iclass 39, count 0 2006.201.17:58:07.56#ibcon#read 3, iclass 39, count 0 2006.201.17:58:07.56#ibcon#about to read 4, iclass 39, count 0 2006.201.17:58:07.56#ibcon#read 4, iclass 39, count 0 2006.201.17:58:07.56#ibcon#about to read 5, iclass 39, count 0 2006.201.17:58:07.56#ibcon#read 5, iclass 39, count 0 2006.201.17:58:07.56#ibcon#about to read 6, iclass 39, count 0 2006.201.17:58:07.56#ibcon#read 6, iclass 39, count 0 2006.201.17:58:07.56#ibcon#end of sib2, iclass 39, count 0 2006.201.17:58:07.56#ibcon#*after write, iclass 39, count 0 2006.201.17:58:07.56#ibcon#*before return 0, iclass 39, count 0 2006.201.17:58:07.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:07.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:07.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:58:07.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:58:07.56$vck44/valo=3,564.99 2006.201.17:58:07.56#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.17:58:07.56#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.17:58:07.56#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:07.56#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:07.56#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:07.56#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:07.56#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:58:07.56#ibcon#first serial, iclass 2, count 0 2006.201.17:58:07.56#ibcon#enter sib2, iclass 2, count 0 2006.201.17:58:07.56#ibcon#flushed, iclass 2, count 0 2006.201.17:58:07.56#ibcon#about to write, iclass 2, count 0 2006.201.17:58:07.56#ibcon#wrote, iclass 2, count 0 2006.201.17:58:07.56#ibcon#about to read 3, iclass 2, count 0 2006.201.17:58:07.58#ibcon#read 3, iclass 2, count 0 2006.201.17:58:07.58#ibcon#about to read 4, iclass 2, count 0 2006.201.17:58:07.58#ibcon#read 4, iclass 2, count 0 2006.201.17:58:07.58#ibcon#about to read 5, iclass 2, count 0 2006.201.17:58:07.58#ibcon#read 5, iclass 2, count 0 2006.201.17:58:07.58#ibcon#about to read 6, iclass 2, count 0 2006.201.17:58:07.58#ibcon#read 6, iclass 2, count 0 2006.201.17:58:07.58#ibcon#end of sib2, iclass 2, count 0 2006.201.17:58:07.58#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:58:07.58#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:58:07.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.17:58:07.58#ibcon#*before write, iclass 2, count 0 2006.201.17:58:07.58#ibcon#enter sib2, iclass 2, count 0 2006.201.17:58:07.58#ibcon#flushed, iclass 2, count 0 2006.201.17:58:07.58#ibcon#about to write, iclass 2, count 0 2006.201.17:58:07.58#ibcon#wrote, iclass 2, count 0 2006.201.17:58:07.58#ibcon#about to read 3, iclass 2, count 0 2006.201.17:58:07.63#ibcon#read 3, iclass 2, count 0 2006.201.17:58:07.63#ibcon#about to read 4, iclass 2, count 0 2006.201.17:58:07.63#ibcon#read 4, iclass 2, count 0 2006.201.17:58:07.63#ibcon#about to read 5, iclass 2, count 0 2006.201.17:58:07.63#ibcon#read 5, iclass 2, count 0 2006.201.17:58:07.63#ibcon#about to read 6, iclass 2, count 0 2006.201.17:58:07.63#ibcon#read 6, iclass 2, count 0 2006.201.17:58:07.63#ibcon#end of sib2, iclass 2, count 0 2006.201.17:58:07.63#ibcon#*after write, iclass 2, count 0 2006.201.17:58:07.63#ibcon#*before return 0, iclass 2, count 0 2006.201.17:58:07.63#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:07.63#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:07.63#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:58:07.63#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:58:07.63$vck44/va=3,8 2006.201.17:58:07.63#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.17:58:07.63#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.17:58:07.63#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:07.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:07.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:07.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:07.68#ibcon#enter wrdev, iclass 5, count 2 2006.201.17:58:07.68#ibcon#first serial, iclass 5, count 2 2006.201.17:58:07.68#ibcon#enter sib2, iclass 5, count 2 2006.201.17:58:07.68#ibcon#flushed, iclass 5, count 2 2006.201.17:58:07.68#ibcon#about to write, iclass 5, count 2 2006.201.17:58:07.68#ibcon#wrote, iclass 5, count 2 2006.201.17:58:07.68#ibcon#about to read 3, iclass 5, count 2 2006.201.17:58:07.70#ibcon#read 3, iclass 5, count 2 2006.201.17:58:07.70#ibcon#about to read 4, iclass 5, count 2 2006.201.17:58:07.70#ibcon#read 4, iclass 5, count 2 2006.201.17:58:07.70#ibcon#about to read 5, iclass 5, count 2 2006.201.17:58:07.70#ibcon#read 5, iclass 5, count 2 2006.201.17:58:07.70#ibcon#about to read 6, iclass 5, count 2 2006.201.17:58:07.70#ibcon#read 6, iclass 5, count 2 2006.201.17:58:07.70#ibcon#end of sib2, iclass 5, count 2 2006.201.17:58:07.70#ibcon#*mode == 0, iclass 5, count 2 2006.201.17:58:07.70#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.17:58:07.70#ibcon#[25=AT03-08\r\n] 2006.201.17:58:07.70#ibcon#*before write, iclass 5, count 2 2006.201.17:58:07.70#ibcon#enter sib2, iclass 5, count 2 2006.201.17:58:07.70#ibcon#flushed, iclass 5, count 2 2006.201.17:58:07.70#ibcon#about to write, iclass 5, count 2 2006.201.17:58:07.70#ibcon#wrote, iclass 5, count 2 2006.201.17:58:07.70#ibcon#about to read 3, iclass 5, count 2 2006.201.17:58:07.73#ibcon#read 3, iclass 5, count 2 2006.201.17:58:07.73#ibcon#about to read 4, iclass 5, count 2 2006.201.17:58:07.73#ibcon#read 4, iclass 5, count 2 2006.201.17:58:07.73#ibcon#about to read 5, iclass 5, count 2 2006.201.17:58:07.73#ibcon#read 5, iclass 5, count 2 2006.201.17:58:07.73#ibcon#about to read 6, iclass 5, count 2 2006.201.17:58:07.73#ibcon#read 6, iclass 5, count 2 2006.201.17:58:07.73#ibcon#end of sib2, iclass 5, count 2 2006.201.17:58:07.73#ibcon#*after write, iclass 5, count 2 2006.201.17:58:07.73#ibcon#*before return 0, iclass 5, count 2 2006.201.17:58:07.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:07.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:07.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.17:58:07.73#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:07.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:07.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:07.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:07.85#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:58:07.85#ibcon#first serial, iclass 5, count 0 2006.201.17:58:07.85#ibcon#enter sib2, iclass 5, count 0 2006.201.17:58:07.85#ibcon#flushed, iclass 5, count 0 2006.201.17:58:07.85#ibcon#about to write, iclass 5, count 0 2006.201.17:58:07.85#ibcon#wrote, iclass 5, count 0 2006.201.17:58:07.85#ibcon#about to read 3, iclass 5, count 0 2006.201.17:58:07.87#ibcon#read 3, iclass 5, count 0 2006.201.17:58:07.87#ibcon#about to read 4, iclass 5, count 0 2006.201.17:58:07.87#ibcon#read 4, iclass 5, count 0 2006.201.17:58:07.87#ibcon#about to read 5, iclass 5, count 0 2006.201.17:58:07.87#ibcon#read 5, iclass 5, count 0 2006.201.17:58:07.87#ibcon#about to read 6, iclass 5, count 0 2006.201.17:58:07.87#ibcon#read 6, iclass 5, count 0 2006.201.17:58:07.87#ibcon#end of sib2, iclass 5, count 0 2006.201.17:58:07.87#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:58:07.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:58:07.87#ibcon#[25=USB\r\n] 2006.201.17:58:07.87#ibcon#*before write, iclass 5, count 0 2006.201.17:58:07.87#ibcon#enter sib2, iclass 5, count 0 2006.201.17:58:07.87#ibcon#flushed, iclass 5, count 0 2006.201.17:58:07.87#ibcon#about to write, iclass 5, count 0 2006.201.17:58:07.87#ibcon#wrote, iclass 5, count 0 2006.201.17:58:07.87#ibcon#about to read 3, iclass 5, count 0 2006.201.17:58:07.90#ibcon#read 3, iclass 5, count 0 2006.201.17:58:07.90#ibcon#about to read 4, iclass 5, count 0 2006.201.17:58:07.90#ibcon#read 4, iclass 5, count 0 2006.201.17:58:07.90#ibcon#about to read 5, iclass 5, count 0 2006.201.17:58:07.90#ibcon#read 5, iclass 5, count 0 2006.201.17:58:07.90#ibcon#about to read 6, iclass 5, count 0 2006.201.17:58:07.90#ibcon#read 6, iclass 5, count 0 2006.201.17:58:07.90#ibcon#end of sib2, iclass 5, count 0 2006.201.17:58:07.90#ibcon#*after write, iclass 5, count 0 2006.201.17:58:07.90#ibcon#*before return 0, iclass 5, count 0 2006.201.17:58:07.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:07.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:07.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:58:07.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:58:07.90$vck44/valo=4,624.99 2006.201.17:58:07.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.17:58:07.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.17:58:07.90#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:07.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:07.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:07.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:07.90#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:58:07.90#ibcon#first serial, iclass 7, count 0 2006.201.17:58:07.90#ibcon#enter sib2, iclass 7, count 0 2006.201.17:58:07.90#ibcon#flushed, iclass 7, count 0 2006.201.17:58:07.90#ibcon#about to write, iclass 7, count 0 2006.201.17:58:07.90#ibcon#wrote, iclass 7, count 0 2006.201.17:58:07.90#ibcon#about to read 3, iclass 7, count 0 2006.201.17:58:07.92#ibcon#read 3, iclass 7, count 0 2006.201.17:58:07.92#ibcon#about to read 4, iclass 7, count 0 2006.201.17:58:07.92#ibcon#read 4, iclass 7, count 0 2006.201.17:58:07.92#ibcon#about to read 5, iclass 7, count 0 2006.201.17:58:07.92#ibcon#read 5, iclass 7, count 0 2006.201.17:58:07.92#ibcon#about to read 6, iclass 7, count 0 2006.201.17:58:07.92#ibcon#read 6, iclass 7, count 0 2006.201.17:58:07.92#ibcon#end of sib2, iclass 7, count 0 2006.201.17:58:07.92#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:58:07.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:58:07.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.17:58:07.92#ibcon#*before write, iclass 7, count 0 2006.201.17:58:07.92#ibcon#enter sib2, iclass 7, count 0 2006.201.17:58:07.92#ibcon#flushed, iclass 7, count 0 2006.201.17:58:07.92#ibcon#about to write, iclass 7, count 0 2006.201.17:58:07.92#ibcon#wrote, iclass 7, count 0 2006.201.17:58:07.92#ibcon#about to read 3, iclass 7, count 0 2006.201.17:58:07.97#ibcon#read 3, iclass 7, count 0 2006.201.17:58:07.97#ibcon#about to read 4, iclass 7, count 0 2006.201.17:58:07.97#ibcon#read 4, iclass 7, count 0 2006.201.17:58:07.97#ibcon#about to read 5, iclass 7, count 0 2006.201.17:58:07.97#ibcon#read 5, iclass 7, count 0 2006.201.17:58:07.97#ibcon#about to read 6, iclass 7, count 0 2006.201.17:58:07.97#ibcon#read 6, iclass 7, count 0 2006.201.17:58:07.97#ibcon#end of sib2, iclass 7, count 0 2006.201.17:58:07.97#ibcon#*after write, iclass 7, count 0 2006.201.17:58:07.97#ibcon#*before return 0, iclass 7, count 0 2006.201.17:58:07.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:07.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:07.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:58:07.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:58:07.97$vck44/va=4,7 2006.201.17:58:07.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.17:58:07.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.17:58:07.97#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:07.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:08.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:08.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:08.02#ibcon#enter wrdev, iclass 11, count 2 2006.201.17:58:08.02#ibcon#first serial, iclass 11, count 2 2006.201.17:58:08.02#ibcon#enter sib2, iclass 11, count 2 2006.201.17:58:08.02#ibcon#flushed, iclass 11, count 2 2006.201.17:58:08.02#ibcon#about to write, iclass 11, count 2 2006.201.17:58:08.02#ibcon#wrote, iclass 11, count 2 2006.201.17:58:08.02#ibcon#about to read 3, iclass 11, count 2 2006.201.17:58:08.04#ibcon#read 3, iclass 11, count 2 2006.201.17:58:08.04#ibcon#about to read 4, iclass 11, count 2 2006.201.17:58:08.04#ibcon#read 4, iclass 11, count 2 2006.201.17:58:08.04#ibcon#about to read 5, iclass 11, count 2 2006.201.17:58:08.04#ibcon#read 5, iclass 11, count 2 2006.201.17:58:08.04#ibcon#about to read 6, iclass 11, count 2 2006.201.17:58:08.04#ibcon#read 6, iclass 11, count 2 2006.201.17:58:08.04#ibcon#end of sib2, iclass 11, count 2 2006.201.17:58:08.04#ibcon#*mode == 0, iclass 11, count 2 2006.201.17:58:08.04#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.17:58:08.04#ibcon#[25=AT04-07\r\n] 2006.201.17:58:08.04#ibcon#*before write, iclass 11, count 2 2006.201.17:58:08.04#ibcon#enter sib2, iclass 11, count 2 2006.201.17:58:08.04#ibcon#flushed, iclass 11, count 2 2006.201.17:58:08.04#ibcon#about to write, iclass 11, count 2 2006.201.17:58:08.04#ibcon#wrote, iclass 11, count 2 2006.201.17:58:08.04#ibcon#about to read 3, iclass 11, count 2 2006.201.17:58:08.07#ibcon#read 3, iclass 11, count 2 2006.201.17:58:08.07#ibcon#about to read 4, iclass 11, count 2 2006.201.17:58:08.07#ibcon#read 4, iclass 11, count 2 2006.201.17:58:08.07#ibcon#about to read 5, iclass 11, count 2 2006.201.17:58:08.07#ibcon#read 5, iclass 11, count 2 2006.201.17:58:08.07#ibcon#about to read 6, iclass 11, count 2 2006.201.17:58:08.07#ibcon#read 6, iclass 11, count 2 2006.201.17:58:08.07#ibcon#end of sib2, iclass 11, count 2 2006.201.17:58:08.07#ibcon#*after write, iclass 11, count 2 2006.201.17:58:08.07#ibcon#*before return 0, iclass 11, count 2 2006.201.17:58:08.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:08.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:08.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.17:58:08.07#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:08.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:08.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:08.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:08.19#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:58:08.19#ibcon#first serial, iclass 11, count 0 2006.201.17:58:08.19#ibcon#enter sib2, iclass 11, count 0 2006.201.17:58:08.19#ibcon#flushed, iclass 11, count 0 2006.201.17:58:08.19#ibcon#about to write, iclass 11, count 0 2006.201.17:58:08.19#ibcon#wrote, iclass 11, count 0 2006.201.17:58:08.19#ibcon#about to read 3, iclass 11, count 0 2006.201.17:58:08.21#ibcon#read 3, iclass 11, count 0 2006.201.17:58:08.21#ibcon#about to read 4, iclass 11, count 0 2006.201.17:58:08.21#ibcon#read 4, iclass 11, count 0 2006.201.17:58:08.21#ibcon#about to read 5, iclass 11, count 0 2006.201.17:58:08.21#ibcon#read 5, iclass 11, count 0 2006.201.17:58:08.21#ibcon#about to read 6, iclass 11, count 0 2006.201.17:58:08.21#ibcon#read 6, iclass 11, count 0 2006.201.17:58:08.21#ibcon#end of sib2, iclass 11, count 0 2006.201.17:58:08.21#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:58:08.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:58:08.21#ibcon#[25=USB\r\n] 2006.201.17:58:08.21#ibcon#*before write, iclass 11, count 0 2006.201.17:58:08.21#ibcon#enter sib2, iclass 11, count 0 2006.201.17:58:08.21#ibcon#flushed, iclass 11, count 0 2006.201.17:58:08.21#ibcon#about to write, iclass 11, count 0 2006.201.17:58:08.21#ibcon#wrote, iclass 11, count 0 2006.201.17:58:08.21#ibcon#about to read 3, iclass 11, count 0 2006.201.17:58:08.24#ibcon#read 3, iclass 11, count 0 2006.201.17:58:08.24#ibcon#about to read 4, iclass 11, count 0 2006.201.17:58:08.24#ibcon#read 4, iclass 11, count 0 2006.201.17:58:08.24#ibcon#about to read 5, iclass 11, count 0 2006.201.17:58:08.24#ibcon#read 5, iclass 11, count 0 2006.201.17:58:08.24#ibcon#about to read 6, iclass 11, count 0 2006.201.17:58:08.24#ibcon#read 6, iclass 11, count 0 2006.201.17:58:08.24#ibcon#end of sib2, iclass 11, count 0 2006.201.17:58:08.24#ibcon#*after write, iclass 11, count 0 2006.201.17:58:08.24#ibcon#*before return 0, iclass 11, count 0 2006.201.17:58:08.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:08.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:08.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:58:08.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:58:08.24$vck44/valo=5,734.99 2006.201.17:58:08.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.17:58:08.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.17:58:08.24#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:08.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:08.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:08.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:08.24#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:58:08.24#ibcon#first serial, iclass 13, count 0 2006.201.17:58:08.24#ibcon#enter sib2, iclass 13, count 0 2006.201.17:58:08.24#ibcon#flushed, iclass 13, count 0 2006.201.17:58:08.24#ibcon#about to write, iclass 13, count 0 2006.201.17:58:08.24#ibcon#wrote, iclass 13, count 0 2006.201.17:58:08.24#ibcon#about to read 3, iclass 13, count 0 2006.201.17:58:08.26#ibcon#read 3, iclass 13, count 0 2006.201.17:58:08.26#ibcon#about to read 4, iclass 13, count 0 2006.201.17:58:08.26#ibcon#read 4, iclass 13, count 0 2006.201.17:58:08.26#ibcon#about to read 5, iclass 13, count 0 2006.201.17:58:08.26#ibcon#read 5, iclass 13, count 0 2006.201.17:58:08.26#ibcon#about to read 6, iclass 13, count 0 2006.201.17:58:08.26#ibcon#read 6, iclass 13, count 0 2006.201.17:58:08.26#ibcon#end of sib2, iclass 13, count 0 2006.201.17:58:08.26#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:58:08.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:58:08.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.17:58:08.26#ibcon#*before write, iclass 13, count 0 2006.201.17:58:08.26#ibcon#enter sib2, iclass 13, count 0 2006.201.17:58:08.26#ibcon#flushed, iclass 13, count 0 2006.201.17:58:08.26#ibcon#about to write, iclass 13, count 0 2006.201.17:58:08.26#ibcon#wrote, iclass 13, count 0 2006.201.17:58:08.26#ibcon#about to read 3, iclass 13, count 0 2006.201.17:58:08.30#ibcon#read 3, iclass 13, count 0 2006.201.17:58:08.30#ibcon#about to read 4, iclass 13, count 0 2006.201.17:58:08.30#ibcon#read 4, iclass 13, count 0 2006.201.17:58:08.30#ibcon#about to read 5, iclass 13, count 0 2006.201.17:58:08.30#ibcon#read 5, iclass 13, count 0 2006.201.17:58:08.30#ibcon#about to read 6, iclass 13, count 0 2006.201.17:58:08.30#ibcon#read 6, iclass 13, count 0 2006.201.17:58:08.30#ibcon#end of sib2, iclass 13, count 0 2006.201.17:58:08.30#ibcon#*after write, iclass 13, count 0 2006.201.17:58:08.30#ibcon#*before return 0, iclass 13, count 0 2006.201.17:58:08.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:08.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:08.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:58:08.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:58:08.30$vck44/va=5,4 2006.201.17:58:08.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.17:58:08.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.17:58:08.30#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:08.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:08.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:08.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:08.36#ibcon#enter wrdev, iclass 15, count 2 2006.201.17:58:08.36#ibcon#first serial, iclass 15, count 2 2006.201.17:58:08.36#ibcon#enter sib2, iclass 15, count 2 2006.201.17:58:08.36#ibcon#flushed, iclass 15, count 2 2006.201.17:58:08.36#ibcon#about to write, iclass 15, count 2 2006.201.17:58:08.36#ibcon#wrote, iclass 15, count 2 2006.201.17:58:08.36#ibcon#about to read 3, iclass 15, count 2 2006.201.17:58:08.38#ibcon#read 3, iclass 15, count 2 2006.201.17:58:08.38#ibcon#about to read 4, iclass 15, count 2 2006.201.17:58:08.38#ibcon#read 4, iclass 15, count 2 2006.201.17:58:08.38#ibcon#about to read 5, iclass 15, count 2 2006.201.17:58:08.38#ibcon#read 5, iclass 15, count 2 2006.201.17:58:08.38#ibcon#about to read 6, iclass 15, count 2 2006.201.17:58:08.38#ibcon#read 6, iclass 15, count 2 2006.201.17:58:08.38#ibcon#end of sib2, iclass 15, count 2 2006.201.17:58:08.38#ibcon#*mode == 0, iclass 15, count 2 2006.201.17:58:08.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.17:58:08.38#ibcon#[25=AT05-04\r\n] 2006.201.17:58:08.38#ibcon#*before write, iclass 15, count 2 2006.201.17:58:08.38#ibcon#enter sib2, iclass 15, count 2 2006.201.17:58:08.38#ibcon#flushed, iclass 15, count 2 2006.201.17:58:08.38#ibcon#about to write, iclass 15, count 2 2006.201.17:58:08.38#ibcon#wrote, iclass 15, count 2 2006.201.17:58:08.38#ibcon#about to read 3, iclass 15, count 2 2006.201.17:58:08.41#ibcon#read 3, iclass 15, count 2 2006.201.17:58:08.41#ibcon#about to read 4, iclass 15, count 2 2006.201.17:58:08.41#ibcon#read 4, iclass 15, count 2 2006.201.17:58:08.41#ibcon#about to read 5, iclass 15, count 2 2006.201.17:58:08.41#ibcon#read 5, iclass 15, count 2 2006.201.17:58:08.41#ibcon#about to read 6, iclass 15, count 2 2006.201.17:58:08.41#ibcon#read 6, iclass 15, count 2 2006.201.17:58:08.41#ibcon#end of sib2, iclass 15, count 2 2006.201.17:58:08.41#ibcon#*after write, iclass 15, count 2 2006.201.17:58:08.41#ibcon#*before return 0, iclass 15, count 2 2006.201.17:58:08.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:08.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:08.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.17:58:08.41#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:08.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:08.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:08.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:08.53#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:58:08.53#ibcon#first serial, iclass 15, count 0 2006.201.17:58:08.53#ibcon#enter sib2, iclass 15, count 0 2006.201.17:58:08.53#ibcon#flushed, iclass 15, count 0 2006.201.17:58:08.53#ibcon#about to write, iclass 15, count 0 2006.201.17:58:08.53#ibcon#wrote, iclass 15, count 0 2006.201.17:58:08.53#ibcon#about to read 3, iclass 15, count 0 2006.201.17:58:08.55#ibcon#read 3, iclass 15, count 0 2006.201.17:58:08.55#ibcon#about to read 4, iclass 15, count 0 2006.201.17:58:08.55#ibcon#read 4, iclass 15, count 0 2006.201.17:58:08.55#ibcon#about to read 5, iclass 15, count 0 2006.201.17:58:08.55#ibcon#read 5, iclass 15, count 0 2006.201.17:58:08.55#ibcon#about to read 6, iclass 15, count 0 2006.201.17:58:08.55#ibcon#read 6, iclass 15, count 0 2006.201.17:58:08.55#ibcon#end of sib2, iclass 15, count 0 2006.201.17:58:08.55#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:58:08.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:58:08.55#ibcon#[25=USB\r\n] 2006.201.17:58:08.55#ibcon#*before write, iclass 15, count 0 2006.201.17:58:08.55#ibcon#enter sib2, iclass 15, count 0 2006.201.17:58:08.55#ibcon#flushed, iclass 15, count 0 2006.201.17:58:08.55#ibcon#about to write, iclass 15, count 0 2006.201.17:58:08.55#ibcon#wrote, iclass 15, count 0 2006.201.17:58:08.55#ibcon#about to read 3, iclass 15, count 0 2006.201.17:58:08.58#ibcon#read 3, iclass 15, count 0 2006.201.17:58:08.58#ibcon#about to read 4, iclass 15, count 0 2006.201.17:58:08.58#ibcon#read 4, iclass 15, count 0 2006.201.17:58:08.58#ibcon#about to read 5, iclass 15, count 0 2006.201.17:58:08.58#ibcon#read 5, iclass 15, count 0 2006.201.17:58:08.58#ibcon#about to read 6, iclass 15, count 0 2006.201.17:58:08.58#ibcon#read 6, iclass 15, count 0 2006.201.17:58:08.58#ibcon#end of sib2, iclass 15, count 0 2006.201.17:58:08.58#ibcon#*after write, iclass 15, count 0 2006.201.17:58:08.58#ibcon#*before return 0, iclass 15, count 0 2006.201.17:58:08.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:08.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:08.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:58:08.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:58:08.58$vck44/valo=6,814.99 2006.201.17:58:08.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.17:58:08.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.17:58:08.58#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:08.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:08.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:08.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:08.58#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:58:08.58#ibcon#first serial, iclass 17, count 0 2006.201.17:58:08.58#ibcon#enter sib2, iclass 17, count 0 2006.201.17:58:08.58#ibcon#flushed, iclass 17, count 0 2006.201.17:58:08.58#ibcon#about to write, iclass 17, count 0 2006.201.17:58:08.58#ibcon#wrote, iclass 17, count 0 2006.201.17:58:08.58#ibcon#about to read 3, iclass 17, count 0 2006.201.17:58:08.60#ibcon#read 3, iclass 17, count 0 2006.201.17:58:08.60#ibcon#about to read 4, iclass 17, count 0 2006.201.17:58:08.60#ibcon#read 4, iclass 17, count 0 2006.201.17:58:08.60#ibcon#about to read 5, iclass 17, count 0 2006.201.17:58:08.60#ibcon#read 5, iclass 17, count 0 2006.201.17:58:08.60#ibcon#about to read 6, iclass 17, count 0 2006.201.17:58:08.60#ibcon#read 6, iclass 17, count 0 2006.201.17:58:08.60#ibcon#end of sib2, iclass 17, count 0 2006.201.17:58:08.60#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:58:08.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:58:08.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.17:58:08.60#ibcon#*before write, iclass 17, count 0 2006.201.17:58:08.60#ibcon#enter sib2, iclass 17, count 0 2006.201.17:58:08.60#ibcon#flushed, iclass 17, count 0 2006.201.17:58:08.60#ibcon#about to write, iclass 17, count 0 2006.201.17:58:08.60#ibcon#wrote, iclass 17, count 0 2006.201.17:58:08.60#ibcon#about to read 3, iclass 17, count 0 2006.201.17:58:08.65#ibcon#read 3, iclass 17, count 0 2006.201.17:58:08.65#ibcon#about to read 4, iclass 17, count 0 2006.201.17:58:08.65#ibcon#read 4, iclass 17, count 0 2006.201.17:58:08.65#ibcon#about to read 5, iclass 17, count 0 2006.201.17:58:08.65#ibcon#read 5, iclass 17, count 0 2006.201.17:58:08.65#ibcon#about to read 6, iclass 17, count 0 2006.201.17:58:08.65#ibcon#read 6, iclass 17, count 0 2006.201.17:58:08.65#ibcon#end of sib2, iclass 17, count 0 2006.201.17:58:08.65#ibcon#*after write, iclass 17, count 0 2006.201.17:58:08.65#ibcon#*before return 0, iclass 17, count 0 2006.201.17:58:08.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:08.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:08.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:58:08.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:58:08.65$vck44/va=6,5 2006.201.17:58:08.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.17:58:08.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.17:58:08.65#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:08.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:58:08.67#abcon#<5=/16 0.6 1.2 20.561001002.3\r\n> 2006.201.17:58:08.69#abcon#{5=INTERFACE CLEAR} 2006.201.17:58:08.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:58:08.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:58:08.70#ibcon#enter wrdev, iclass 20, count 2 2006.201.17:58:08.70#ibcon#first serial, iclass 20, count 2 2006.201.17:58:08.70#ibcon#enter sib2, iclass 20, count 2 2006.201.17:58:08.70#ibcon#flushed, iclass 20, count 2 2006.201.17:58:08.70#ibcon#about to write, iclass 20, count 2 2006.201.17:58:08.70#ibcon#wrote, iclass 20, count 2 2006.201.17:58:08.70#ibcon#about to read 3, iclass 20, count 2 2006.201.17:58:08.72#ibcon#read 3, iclass 20, count 2 2006.201.17:58:08.72#ibcon#about to read 4, iclass 20, count 2 2006.201.17:58:08.72#ibcon#read 4, iclass 20, count 2 2006.201.17:58:08.72#ibcon#about to read 5, iclass 20, count 2 2006.201.17:58:08.72#ibcon#read 5, iclass 20, count 2 2006.201.17:58:08.72#ibcon#about to read 6, iclass 20, count 2 2006.201.17:58:08.72#ibcon#read 6, iclass 20, count 2 2006.201.17:58:08.72#ibcon#end of sib2, iclass 20, count 2 2006.201.17:58:08.72#ibcon#*mode == 0, iclass 20, count 2 2006.201.17:58:08.72#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.17:58:08.72#ibcon#[25=AT06-05\r\n] 2006.201.17:58:08.72#ibcon#*before write, iclass 20, count 2 2006.201.17:58:08.72#ibcon#enter sib2, iclass 20, count 2 2006.201.17:58:08.72#ibcon#flushed, iclass 20, count 2 2006.201.17:58:08.72#ibcon#about to write, iclass 20, count 2 2006.201.17:58:08.72#ibcon#wrote, iclass 20, count 2 2006.201.17:58:08.72#ibcon#about to read 3, iclass 20, count 2 2006.201.17:58:08.75#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:58:08.75#ibcon#read 3, iclass 20, count 2 2006.201.17:58:08.75#ibcon#about to read 4, iclass 20, count 2 2006.201.17:58:08.75#ibcon#read 4, iclass 20, count 2 2006.201.17:58:08.75#ibcon#about to read 5, iclass 20, count 2 2006.201.17:58:08.75#ibcon#read 5, iclass 20, count 2 2006.201.17:58:08.75#ibcon#about to read 6, iclass 20, count 2 2006.201.17:58:08.75#ibcon#read 6, iclass 20, count 2 2006.201.17:58:08.75#ibcon#end of sib2, iclass 20, count 2 2006.201.17:58:08.75#ibcon#*after write, iclass 20, count 2 2006.201.17:58:08.75#ibcon#*before return 0, iclass 20, count 2 2006.201.17:58:08.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:58:08.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.17:58:08.75#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.17:58:08.75#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:08.75#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:58:08.87#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:58:08.87#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:58:08.87#ibcon#enter wrdev, iclass 20, count 0 2006.201.17:58:08.87#ibcon#first serial, iclass 20, count 0 2006.201.17:58:08.87#ibcon#enter sib2, iclass 20, count 0 2006.201.17:58:08.87#ibcon#flushed, iclass 20, count 0 2006.201.17:58:08.87#ibcon#about to write, iclass 20, count 0 2006.201.17:58:08.87#ibcon#wrote, iclass 20, count 0 2006.201.17:58:08.87#ibcon#about to read 3, iclass 20, count 0 2006.201.17:58:08.89#ibcon#read 3, iclass 20, count 0 2006.201.17:58:08.89#ibcon#about to read 4, iclass 20, count 0 2006.201.17:58:08.89#ibcon#read 4, iclass 20, count 0 2006.201.17:58:08.89#ibcon#about to read 5, iclass 20, count 0 2006.201.17:58:08.89#ibcon#read 5, iclass 20, count 0 2006.201.17:58:08.89#ibcon#about to read 6, iclass 20, count 0 2006.201.17:58:08.89#ibcon#read 6, iclass 20, count 0 2006.201.17:58:08.89#ibcon#end of sib2, iclass 20, count 0 2006.201.17:58:08.89#ibcon#*mode == 0, iclass 20, count 0 2006.201.17:58:08.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.17:58:08.89#ibcon#[25=USB\r\n] 2006.201.17:58:08.89#ibcon#*before write, iclass 20, count 0 2006.201.17:58:08.89#ibcon#enter sib2, iclass 20, count 0 2006.201.17:58:08.89#ibcon#flushed, iclass 20, count 0 2006.201.17:58:08.89#ibcon#about to write, iclass 20, count 0 2006.201.17:58:08.89#ibcon#wrote, iclass 20, count 0 2006.201.17:58:08.89#ibcon#about to read 3, iclass 20, count 0 2006.201.17:58:08.92#ibcon#read 3, iclass 20, count 0 2006.201.17:58:08.92#ibcon#about to read 4, iclass 20, count 0 2006.201.17:58:08.92#ibcon#read 4, iclass 20, count 0 2006.201.17:58:08.92#ibcon#about to read 5, iclass 20, count 0 2006.201.17:58:08.92#ibcon#read 5, iclass 20, count 0 2006.201.17:58:08.92#ibcon#about to read 6, iclass 20, count 0 2006.201.17:58:08.92#ibcon#read 6, iclass 20, count 0 2006.201.17:58:08.92#ibcon#end of sib2, iclass 20, count 0 2006.201.17:58:08.92#ibcon#*after write, iclass 20, count 0 2006.201.17:58:08.92#ibcon#*before return 0, iclass 20, count 0 2006.201.17:58:08.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:58:08.92#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.17:58:08.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.17:58:08.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.17:58:08.92$vck44/valo=7,864.99 2006.201.17:58:08.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.17:58:08.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.17:58:08.92#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:08.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:08.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:08.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:08.92#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:58:08.92#ibcon#first serial, iclass 25, count 0 2006.201.17:58:08.92#ibcon#enter sib2, iclass 25, count 0 2006.201.17:58:08.92#ibcon#flushed, iclass 25, count 0 2006.201.17:58:08.92#ibcon#about to write, iclass 25, count 0 2006.201.17:58:08.92#ibcon#wrote, iclass 25, count 0 2006.201.17:58:08.92#ibcon#about to read 3, iclass 25, count 0 2006.201.17:58:08.94#ibcon#read 3, iclass 25, count 0 2006.201.17:58:08.94#ibcon#about to read 4, iclass 25, count 0 2006.201.17:58:08.94#ibcon#read 4, iclass 25, count 0 2006.201.17:58:08.94#ibcon#about to read 5, iclass 25, count 0 2006.201.17:58:08.94#ibcon#read 5, iclass 25, count 0 2006.201.17:58:08.94#ibcon#about to read 6, iclass 25, count 0 2006.201.17:58:08.94#ibcon#read 6, iclass 25, count 0 2006.201.17:58:08.94#ibcon#end of sib2, iclass 25, count 0 2006.201.17:58:08.94#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:58:08.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:58:08.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.17:58:08.94#ibcon#*before write, iclass 25, count 0 2006.201.17:58:08.94#ibcon#enter sib2, iclass 25, count 0 2006.201.17:58:08.94#ibcon#flushed, iclass 25, count 0 2006.201.17:58:08.94#ibcon#about to write, iclass 25, count 0 2006.201.17:58:08.94#ibcon#wrote, iclass 25, count 0 2006.201.17:58:08.94#ibcon#about to read 3, iclass 25, count 0 2006.201.17:58:08.98#ibcon#read 3, iclass 25, count 0 2006.201.17:58:08.98#ibcon#about to read 4, iclass 25, count 0 2006.201.17:58:08.98#ibcon#read 4, iclass 25, count 0 2006.201.17:58:08.98#ibcon#about to read 5, iclass 25, count 0 2006.201.17:58:08.98#ibcon#read 5, iclass 25, count 0 2006.201.17:58:08.98#ibcon#about to read 6, iclass 25, count 0 2006.201.17:58:08.98#ibcon#read 6, iclass 25, count 0 2006.201.17:58:08.98#ibcon#end of sib2, iclass 25, count 0 2006.201.17:58:08.98#ibcon#*after write, iclass 25, count 0 2006.201.17:58:08.98#ibcon#*before return 0, iclass 25, count 0 2006.201.17:58:08.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:08.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:08.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:58:08.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:58:08.98$vck44/va=7,5 2006.201.17:58:08.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.17:58:08.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.17:58:08.98#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:08.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:09.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:09.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:09.04#ibcon#enter wrdev, iclass 27, count 2 2006.201.17:58:09.04#ibcon#first serial, iclass 27, count 2 2006.201.17:58:09.04#ibcon#enter sib2, iclass 27, count 2 2006.201.17:58:09.04#ibcon#flushed, iclass 27, count 2 2006.201.17:58:09.04#ibcon#about to write, iclass 27, count 2 2006.201.17:58:09.04#ibcon#wrote, iclass 27, count 2 2006.201.17:58:09.04#ibcon#about to read 3, iclass 27, count 2 2006.201.17:58:09.06#ibcon#read 3, iclass 27, count 2 2006.201.17:58:09.06#ibcon#about to read 4, iclass 27, count 2 2006.201.17:58:09.06#ibcon#read 4, iclass 27, count 2 2006.201.17:58:09.06#ibcon#about to read 5, iclass 27, count 2 2006.201.17:58:09.06#ibcon#read 5, iclass 27, count 2 2006.201.17:58:09.06#ibcon#about to read 6, iclass 27, count 2 2006.201.17:58:09.06#ibcon#read 6, iclass 27, count 2 2006.201.17:58:09.06#ibcon#end of sib2, iclass 27, count 2 2006.201.17:58:09.06#ibcon#*mode == 0, iclass 27, count 2 2006.201.17:58:09.06#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.17:58:09.06#ibcon#[25=AT07-05\r\n] 2006.201.17:58:09.06#ibcon#*before write, iclass 27, count 2 2006.201.17:58:09.06#ibcon#enter sib2, iclass 27, count 2 2006.201.17:58:09.06#ibcon#flushed, iclass 27, count 2 2006.201.17:58:09.06#ibcon#about to write, iclass 27, count 2 2006.201.17:58:09.06#ibcon#wrote, iclass 27, count 2 2006.201.17:58:09.06#ibcon#about to read 3, iclass 27, count 2 2006.201.17:58:09.09#ibcon#read 3, iclass 27, count 2 2006.201.17:58:09.09#ibcon#about to read 4, iclass 27, count 2 2006.201.17:58:09.09#ibcon#read 4, iclass 27, count 2 2006.201.17:58:09.09#ibcon#about to read 5, iclass 27, count 2 2006.201.17:58:09.09#ibcon#read 5, iclass 27, count 2 2006.201.17:58:09.09#ibcon#about to read 6, iclass 27, count 2 2006.201.17:58:09.09#ibcon#read 6, iclass 27, count 2 2006.201.17:58:09.09#ibcon#end of sib2, iclass 27, count 2 2006.201.17:58:09.09#ibcon#*after write, iclass 27, count 2 2006.201.17:58:09.09#ibcon#*before return 0, iclass 27, count 2 2006.201.17:58:09.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:09.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:09.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.17:58:09.09#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:09.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:09.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:09.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:09.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:58:09.21#ibcon#first serial, iclass 27, count 0 2006.201.17:58:09.21#ibcon#enter sib2, iclass 27, count 0 2006.201.17:58:09.21#ibcon#flushed, iclass 27, count 0 2006.201.17:58:09.21#ibcon#about to write, iclass 27, count 0 2006.201.17:58:09.21#ibcon#wrote, iclass 27, count 0 2006.201.17:58:09.21#ibcon#about to read 3, iclass 27, count 0 2006.201.17:58:09.23#ibcon#read 3, iclass 27, count 0 2006.201.17:58:09.23#ibcon#about to read 4, iclass 27, count 0 2006.201.17:58:09.23#ibcon#read 4, iclass 27, count 0 2006.201.17:58:09.23#ibcon#about to read 5, iclass 27, count 0 2006.201.17:58:09.23#ibcon#read 5, iclass 27, count 0 2006.201.17:58:09.23#ibcon#about to read 6, iclass 27, count 0 2006.201.17:58:09.23#ibcon#read 6, iclass 27, count 0 2006.201.17:58:09.23#ibcon#end of sib2, iclass 27, count 0 2006.201.17:58:09.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:58:09.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:58:09.23#ibcon#[25=USB\r\n] 2006.201.17:58:09.23#ibcon#*before write, iclass 27, count 0 2006.201.17:58:09.23#ibcon#enter sib2, iclass 27, count 0 2006.201.17:58:09.23#ibcon#flushed, iclass 27, count 0 2006.201.17:58:09.23#ibcon#about to write, iclass 27, count 0 2006.201.17:58:09.23#ibcon#wrote, iclass 27, count 0 2006.201.17:58:09.23#ibcon#about to read 3, iclass 27, count 0 2006.201.17:58:09.26#ibcon#read 3, iclass 27, count 0 2006.201.17:58:09.26#ibcon#about to read 4, iclass 27, count 0 2006.201.17:58:09.26#ibcon#read 4, iclass 27, count 0 2006.201.17:58:09.26#ibcon#about to read 5, iclass 27, count 0 2006.201.17:58:09.26#ibcon#read 5, iclass 27, count 0 2006.201.17:58:09.26#ibcon#about to read 6, iclass 27, count 0 2006.201.17:58:09.26#ibcon#read 6, iclass 27, count 0 2006.201.17:58:09.26#ibcon#end of sib2, iclass 27, count 0 2006.201.17:58:09.26#ibcon#*after write, iclass 27, count 0 2006.201.17:58:09.26#ibcon#*before return 0, iclass 27, count 0 2006.201.17:58:09.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:09.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:09.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:58:09.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:58:09.26$vck44/valo=8,884.99 2006.201.17:58:09.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.17:58:09.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.17:58:09.26#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:09.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:09.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:09.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:09.26#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:58:09.26#ibcon#first serial, iclass 29, count 0 2006.201.17:58:09.26#ibcon#enter sib2, iclass 29, count 0 2006.201.17:58:09.26#ibcon#flushed, iclass 29, count 0 2006.201.17:58:09.26#ibcon#about to write, iclass 29, count 0 2006.201.17:58:09.26#ibcon#wrote, iclass 29, count 0 2006.201.17:58:09.26#ibcon#about to read 3, iclass 29, count 0 2006.201.17:58:09.28#ibcon#read 3, iclass 29, count 0 2006.201.17:58:09.28#ibcon#about to read 4, iclass 29, count 0 2006.201.17:58:09.28#ibcon#read 4, iclass 29, count 0 2006.201.17:58:09.28#ibcon#about to read 5, iclass 29, count 0 2006.201.17:58:09.28#ibcon#read 5, iclass 29, count 0 2006.201.17:58:09.28#ibcon#about to read 6, iclass 29, count 0 2006.201.17:58:09.28#ibcon#read 6, iclass 29, count 0 2006.201.17:58:09.28#ibcon#end of sib2, iclass 29, count 0 2006.201.17:58:09.28#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:58:09.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:58:09.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.17:58:09.28#ibcon#*before write, iclass 29, count 0 2006.201.17:58:09.28#ibcon#enter sib2, iclass 29, count 0 2006.201.17:58:09.28#ibcon#flushed, iclass 29, count 0 2006.201.17:58:09.28#ibcon#about to write, iclass 29, count 0 2006.201.17:58:09.28#ibcon#wrote, iclass 29, count 0 2006.201.17:58:09.28#ibcon#about to read 3, iclass 29, count 0 2006.201.17:58:09.32#ibcon#read 3, iclass 29, count 0 2006.201.17:58:09.32#ibcon#about to read 4, iclass 29, count 0 2006.201.17:58:09.32#ibcon#read 4, iclass 29, count 0 2006.201.17:58:09.32#ibcon#about to read 5, iclass 29, count 0 2006.201.17:58:09.32#ibcon#read 5, iclass 29, count 0 2006.201.17:58:09.32#ibcon#about to read 6, iclass 29, count 0 2006.201.17:58:09.32#ibcon#read 6, iclass 29, count 0 2006.201.17:58:09.32#ibcon#end of sib2, iclass 29, count 0 2006.201.17:58:09.32#ibcon#*after write, iclass 29, count 0 2006.201.17:58:09.32#ibcon#*before return 0, iclass 29, count 0 2006.201.17:58:09.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:09.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:09.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:58:09.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:58:09.32$vck44/va=8,4 2006.201.17:58:09.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.17:58:09.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.17:58:09.32#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:09.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:58:09.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:58:09.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:58:09.38#ibcon#enter wrdev, iclass 31, count 2 2006.201.17:58:09.38#ibcon#first serial, iclass 31, count 2 2006.201.17:58:09.38#ibcon#enter sib2, iclass 31, count 2 2006.201.17:58:09.38#ibcon#flushed, iclass 31, count 2 2006.201.17:58:09.38#ibcon#about to write, iclass 31, count 2 2006.201.17:58:09.38#ibcon#wrote, iclass 31, count 2 2006.201.17:58:09.38#ibcon#about to read 3, iclass 31, count 2 2006.201.17:58:09.40#ibcon#read 3, iclass 31, count 2 2006.201.17:58:09.40#ibcon#about to read 4, iclass 31, count 2 2006.201.17:58:09.40#ibcon#read 4, iclass 31, count 2 2006.201.17:58:09.40#ibcon#about to read 5, iclass 31, count 2 2006.201.17:58:09.40#ibcon#read 5, iclass 31, count 2 2006.201.17:58:09.40#ibcon#about to read 6, iclass 31, count 2 2006.201.17:58:09.40#ibcon#read 6, iclass 31, count 2 2006.201.17:58:09.40#ibcon#end of sib2, iclass 31, count 2 2006.201.17:58:09.40#ibcon#*mode == 0, iclass 31, count 2 2006.201.17:58:09.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.17:58:09.40#ibcon#[25=AT08-04\r\n] 2006.201.17:58:09.40#ibcon#*before write, iclass 31, count 2 2006.201.17:58:09.40#ibcon#enter sib2, iclass 31, count 2 2006.201.17:58:09.40#ibcon#flushed, iclass 31, count 2 2006.201.17:58:09.40#ibcon#about to write, iclass 31, count 2 2006.201.17:58:09.40#ibcon#wrote, iclass 31, count 2 2006.201.17:58:09.40#ibcon#about to read 3, iclass 31, count 2 2006.201.17:58:09.43#ibcon#read 3, iclass 31, count 2 2006.201.17:58:09.43#ibcon#about to read 4, iclass 31, count 2 2006.201.17:58:09.43#ibcon#read 4, iclass 31, count 2 2006.201.17:58:09.43#ibcon#about to read 5, iclass 31, count 2 2006.201.17:58:09.43#ibcon#read 5, iclass 31, count 2 2006.201.17:58:09.43#ibcon#about to read 6, iclass 31, count 2 2006.201.17:58:09.43#ibcon#read 6, iclass 31, count 2 2006.201.17:58:09.43#ibcon#end of sib2, iclass 31, count 2 2006.201.17:58:09.43#ibcon#*after write, iclass 31, count 2 2006.201.17:58:09.43#ibcon#*before return 0, iclass 31, count 2 2006.201.17:58:09.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:58:09.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.17:58:09.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.17:58:09.43#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:09.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:58:09.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:58:09.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:58:09.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:58:09.55#ibcon#first serial, iclass 31, count 0 2006.201.17:58:09.55#ibcon#enter sib2, iclass 31, count 0 2006.201.17:58:09.55#ibcon#flushed, iclass 31, count 0 2006.201.17:58:09.55#ibcon#about to write, iclass 31, count 0 2006.201.17:58:09.55#ibcon#wrote, iclass 31, count 0 2006.201.17:58:09.55#ibcon#about to read 3, iclass 31, count 0 2006.201.17:58:09.57#ibcon#read 3, iclass 31, count 0 2006.201.17:58:09.57#ibcon#about to read 4, iclass 31, count 0 2006.201.17:58:09.57#ibcon#read 4, iclass 31, count 0 2006.201.17:58:09.57#ibcon#about to read 5, iclass 31, count 0 2006.201.17:58:09.57#ibcon#read 5, iclass 31, count 0 2006.201.17:58:09.57#ibcon#about to read 6, iclass 31, count 0 2006.201.17:58:09.57#ibcon#read 6, iclass 31, count 0 2006.201.17:58:09.57#ibcon#end of sib2, iclass 31, count 0 2006.201.17:58:09.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:58:09.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:58:09.57#ibcon#[25=USB\r\n] 2006.201.17:58:09.57#ibcon#*before write, iclass 31, count 0 2006.201.17:58:09.57#ibcon#enter sib2, iclass 31, count 0 2006.201.17:58:09.57#ibcon#flushed, iclass 31, count 0 2006.201.17:58:09.57#ibcon#about to write, iclass 31, count 0 2006.201.17:58:09.57#ibcon#wrote, iclass 31, count 0 2006.201.17:58:09.57#ibcon#about to read 3, iclass 31, count 0 2006.201.17:58:09.60#ibcon#read 3, iclass 31, count 0 2006.201.17:58:09.60#ibcon#about to read 4, iclass 31, count 0 2006.201.17:58:09.60#ibcon#read 4, iclass 31, count 0 2006.201.17:58:09.60#ibcon#about to read 5, iclass 31, count 0 2006.201.17:58:09.60#ibcon#read 5, iclass 31, count 0 2006.201.17:58:09.60#ibcon#about to read 6, iclass 31, count 0 2006.201.17:58:09.60#ibcon#read 6, iclass 31, count 0 2006.201.17:58:09.60#ibcon#end of sib2, iclass 31, count 0 2006.201.17:58:09.60#ibcon#*after write, iclass 31, count 0 2006.201.17:58:09.60#ibcon#*before return 0, iclass 31, count 0 2006.201.17:58:09.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:58:09.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.17:58:09.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:58:09.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:58:09.60$vck44/vblo=1,629.99 2006.201.17:58:09.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.17:58:09.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.17:58:09.60#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:09.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:09.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:09.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:09.60#ibcon#enter wrdev, iclass 33, count 0 2006.201.17:58:09.60#ibcon#first serial, iclass 33, count 0 2006.201.17:58:09.60#ibcon#enter sib2, iclass 33, count 0 2006.201.17:58:09.60#ibcon#flushed, iclass 33, count 0 2006.201.17:58:09.60#ibcon#about to write, iclass 33, count 0 2006.201.17:58:09.60#ibcon#wrote, iclass 33, count 0 2006.201.17:58:09.60#ibcon#about to read 3, iclass 33, count 0 2006.201.17:58:09.62#ibcon#read 3, iclass 33, count 0 2006.201.17:58:09.62#ibcon#about to read 4, iclass 33, count 0 2006.201.17:58:09.62#ibcon#read 4, iclass 33, count 0 2006.201.17:58:09.62#ibcon#about to read 5, iclass 33, count 0 2006.201.17:58:09.62#ibcon#read 5, iclass 33, count 0 2006.201.17:58:09.62#ibcon#about to read 6, iclass 33, count 0 2006.201.17:58:09.62#ibcon#read 6, iclass 33, count 0 2006.201.17:58:09.62#ibcon#end of sib2, iclass 33, count 0 2006.201.17:58:09.62#ibcon#*mode == 0, iclass 33, count 0 2006.201.17:58:09.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.17:58:09.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.17:58:09.62#ibcon#*before write, iclass 33, count 0 2006.201.17:58:09.62#ibcon#enter sib2, iclass 33, count 0 2006.201.17:58:09.62#ibcon#flushed, iclass 33, count 0 2006.201.17:58:09.62#ibcon#about to write, iclass 33, count 0 2006.201.17:58:09.62#ibcon#wrote, iclass 33, count 0 2006.201.17:58:09.62#ibcon#about to read 3, iclass 33, count 0 2006.201.17:58:09.67#ibcon#read 3, iclass 33, count 0 2006.201.17:58:09.67#ibcon#about to read 4, iclass 33, count 0 2006.201.17:58:09.67#ibcon#read 4, iclass 33, count 0 2006.201.17:58:09.67#ibcon#about to read 5, iclass 33, count 0 2006.201.17:58:09.67#ibcon#read 5, iclass 33, count 0 2006.201.17:58:09.67#ibcon#about to read 6, iclass 33, count 0 2006.201.17:58:09.67#ibcon#read 6, iclass 33, count 0 2006.201.17:58:09.67#ibcon#end of sib2, iclass 33, count 0 2006.201.17:58:09.67#ibcon#*after write, iclass 33, count 0 2006.201.17:58:09.67#ibcon#*before return 0, iclass 33, count 0 2006.201.17:58:09.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:09.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.17:58:09.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.17:58:09.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.17:58:09.67$vck44/vb=1,4 2006.201.17:58:09.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.17:58:09.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.17:58:09.67#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:09.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:09.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:09.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:09.67#ibcon#enter wrdev, iclass 35, count 2 2006.201.17:58:09.67#ibcon#first serial, iclass 35, count 2 2006.201.17:58:09.67#ibcon#enter sib2, iclass 35, count 2 2006.201.17:58:09.67#ibcon#flushed, iclass 35, count 2 2006.201.17:58:09.67#ibcon#about to write, iclass 35, count 2 2006.201.17:58:09.67#ibcon#wrote, iclass 35, count 2 2006.201.17:58:09.67#ibcon#about to read 3, iclass 35, count 2 2006.201.17:58:09.69#ibcon#read 3, iclass 35, count 2 2006.201.17:58:09.69#ibcon#about to read 4, iclass 35, count 2 2006.201.17:58:09.69#ibcon#read 4, iclass 35, count 2 2006.201.17:58:09.69#ibcon#about to read 5, iclass 35, count 2 2006.201.17:58:09.69#ibcon#read 5, iclass 35, count 2 2006.201.17:58:09.69#ibcon#about to read 6, iclass 35, count 2 2006.201.17:58:09.69#ibcon#read 6, iclass 35, count 2 2006.201.17:58:09.69#ibcon#end of sib2, iclass 35, count 2 2006.201.17:58:09.69#ibcon#*mode == 0, iclass 35, count 2 2006.201.17:58:09.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.17:58:09.69#ibcon#[27=AT01-04\r\n] 2006.201.17:58:09.69#ibcon#*before write, iclass 35, count 2 2006.201.17:58:09.69#ibcon#enter sib2, iclass 35, count 2 2006.201.17:58:09.69#ibcon#flushed, iclass 35, count 2 2006.201.17:58:09.69#ibcon#about to write, iclass 35, count 2 2006.201.17:58:09.69#ibcon#wrote, iclass 35, count 2 2006.201.17:58:09.69#ibcon#about to read 3, iclass 35, count 2 2006.201.17:58:09.72#ibcon#read 3, iclass 35, count 2 2006.201.17:58:09.72#ibcon#about to read 4, iclass 35, count 2 2006.201.17:58:09.72#ibcon#read 4, iclass 35, count 2 2006.201.17:58:09.72#ibcon#about to read 5, iclass 35, count 2 2006.201.17:58:09.72#ibcon#read 5, iclass 35, count 2 2006.201.17:58:09.72#ibcon#about to read 6, iclass 35, count 2 2006.201.17:58:09.72#ibcon#read 6, iclass 35, count 2 2006.201.17:58:09.72#ibcon#end of sib2, iclass 35, count 2 2006.201.17:58:09.72#ibcon#*after write, iclass 35, count 2 2006.201.17:58:09.72#ibcon#*before return 0, iclass 35, count 2 2006.201.17:58:09.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:09.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.17:58:09.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.17:58:09.72#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:09.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:09.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:09.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:09.84#ibcon#enter wrdev, iclass 35, count 0 2006.201.17:58:09.84#ibcon#first serial, iclass 35, count 0 2006.201.17:58:09.84#ibcon#enter sib2, iclass 35, count 0 2006.201.17:58:09.84#ibcon#flushed, iclass 35, count 0 2006.201.17:58:09.84#ibcon#about to write, iclass 35, count 0 2006.201.17:58:09.84#ibcon#wrote, iclass 35, count 0 2006.201.17:58:09.84#ibcon#about to read 3, iclass 35, count 0 2006.201.17:58:09.86#ibcon#read 3, iclass 35, count 0 2006.201.17:58:09.86#ibcon#about to read 4, iclass 35, count 0 2006.201.17:58:09.86#ibcon#read 4, iclass 35, count 0 2006.201.17:58:09.86#ibcon#about to read 5, iclass 35, count 0 2006.201.17:58:09.86#ibcon#read 5, iclass 35, count 0 2006.201.17:58:09.86#ibcon#about to read 6, iclass 35, count 0 2006.201.17:58:09.86#ibcon#read 6, iclass 35, count 0 2006.201.17:58:09.86#ibcon#end of sib2, iclass 35, count 0 2006.201.17:58:09.86#ibcon#*mode == 0, iclass 35, count 0 2006.201.17:58:09.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.17:58:09.86#ibcon#[27=USB\r\n] 2006.201.17:58:09.86#ibcon#*before write, iclass 35, count 0 2006.201.17:58:09.86#ibcon#enter sib2, iclass 35, count 0 2006.201.17:58:09.86#ibcon#flushed, iclass 35, count 0 2006.201.17:58:09.86#ibcon#about to write, iclass 35, count 0 2006.201.17:58:09.86#ibcon#wrote, iclass 35, count 0 2006.201.17:58:09.86#ibcon#about to read 3, iclass 35, count 0 2006.201.17:58:09.89#ibcon#read 3, iclass 35, count 0 2006.201.17:58:09.89#ibcon#about to read 4, iclass 35, count 0 2006.201.17:58:09.89#ibcon#read 4, iclass 35, count 0 2006.201.17:58:09.89#ibcon#about to read 5, iclass 35, count 0 2006.201.17:58:09.89#ibcon#read 5, iclass 35, count 0 2006.201.17:58:09.89#ibcon#about to read 6, iclass 35, count 0 2006.201.17:58:09.89#ibcon#read 6, iclass 35, count 0 2006.201.17:58:09.89#ibcon#end of sib2, iclass 35, count 0 2006.201.17:58:09.89#ibcon#*after write, iclass 35, count 0 2006.201.17:58:09.89#ibcon#*before return 0, iclass 35, count 0 2006.201.17:58:09.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:09.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.17:58:09.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.17:58:09.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.17:58:09.89$vck44/vblo=2,634.99 2006.201.17:58:09.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.17:58:09.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.17:58:09.89#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:09.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:09.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:09.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:09.89#ibcon#enter wrdev, iclass 37, count 0 2006.201.17:58:09.89#ibcon#first serial, iclass 37, count 0 2006.201.17:58:09.89#ibcon#enter sib2, iclass 37, count 0 2006.201.17:58:09.89#ibcon#flushed, iclass 37, count 0 2006.201.17:58:09.89#ibcon#about to write, iclass 37, count 0 2006.201.17:58:09.89#ibcon#wrote, iclass 37, count 0 2006.201.17:58:09.89#ibcon#about to read 3, iclass 37, count 0 2006.201.17:58:09.91#ibcon#read 3, iclass 37, count 0 2006.201.17:58:09.91#ibcon#about to read 4, iclass 37, count 0 2006.201.17:58:09.91#ibcon#read 4, iclass 37, count 0 2006.201.17:58:09.91#ibcon#about to read 5, iclass 37, count 0 2006.201.17:58:09.91#ibcon#read 5, iclass 37, count 0 2006.201.17:58:09.91#ibcon#about to read 6, iclass 37, count 0 2006.201.17:58:09.91#ibcon#read 6, iclass 37, count 0 2006.201.17:58:09.91#ibcon#end of sib2, iclass 37, count 0 2006.201.17:58:09.91#ibcon#*mode == 0, iclass 37, count 0 2006.201.17:58:09.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.17:58:09.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.17:58:09.91#ibcon#*before write, iclass 37, count 0 2006.201.17:58:09.91#ibcon#enter sib2, iclass 37, count 0 2006.201.17:58:09.91#ibcon#flushed, iclass 37, count 0 2006.201.17:58:09.91#ibcon#about to write, iclass 37, count 0 2006.201.17:58:09.91#ibcon#wrote, iclass 37, count 0 2006.201.17:58:09.91#ibcon#about to read 3, iclass 37, count 0 2006.201.17:58:09.95#ibcon#read 3, iclass 37, count 0 2006.201.17:58:09.95#ibcon#about to read 4, iclass 37, count 0 2006.201.17:58:09.95#ibcon#read 4, iclass 37, count 0 2006.201.17:58:09.95#ibcon#about to read 5, iclass 37, count 0 2006.201.17:58:09.95#ibcon#read 5, iclass 37, count 0 2006.201.17:58:09.95#ibcon#about to read 6, iclass 37, count 0 2006.201.17:58:09.95#ibcon#read 6, iclass 37, count 0 2006.201.17:58:09.95#ibcon#end of sib2, iclass 37, count 0 2006.201.17:58:09.95#ibcon#*after write, iclass 37, count 0 2006.201.17:58:09.95#ibcon#*before return 0, iclass 37, count 0 2006.201.17:58:09.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:09.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.17:58:09.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.17:58:09.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.17:58:09.95$vck44/vb=2,5 2006.201.17:58:09.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.17:58:09.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.17:58:09.95#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:09.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:10.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:10.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:10.01#ibcon#enter wrdev, iclass 39, count 2 2006.201.17:58:10.01#ibcon#first serial, iclass 39, count 2 2006.201.17:58:10.01#ibcon#enter sib2, iclass 39, count 2 2006.201.17:58:10.01#ibcon#flushed, iclass 39, count 2 2006.201.17:58:10.01#ibcon#about to write, iclass 39, count 2 2006.201.17:58:10.01#ibcon#wrote, iclass 39, count 2 2006.201.17:58:10.01#ibcon#about to read 3, iclass 39, count 2 2006.201.17:58:10.03#ibcon#read 3, iclass 39, count 2 2006.201.17:58:10.03#ibcon#about to read 4, iclass 39, count 2 2006.201.17:58:10.03#ibcon#read 4, iclass 39, count 2 2006.201.17:58:10.03#ibcon#about to read 5, iclass 39, count 2 2006.201.17:58:10.03#ibcon#read 5, iclass 39, count 2 2006.201.17:58:10.03#ibcon#about to read 6, iclass 39, count 2 2006.201.17:58:10.03#ibcon#read 6, iclass 39, count 2 2006.201.17:58:10.03#ibcon#end of sib2, iclass 39, count 2 2006.201.17:58:10.03#ibcon#*mode == 0, iclass 39, count 2 2006.201.17:58:10.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.17:58:10.03#ibcon#[27=AT02-05\r\n] 2006.201.17:58:10.03#ibcon#*before write, iclass 39, count 2 2006.201.17:58:10.03#ibcon#enter sib2, iclass 39, count 2 2006.201.17:58:10.03#ibcon#flushed, iclass 39, count 2 2006.201.17:58:10.03#ibcon#about to write, iclass 39, count 2 2006.201.17:58:10.03#ibcon#wrote, iclass 39, count 2 2006.201.17:58:10.03#ibcon#about to read 3, iclass 39, count 2 2006.201.17:58:10.06#ibcon#read 3, iclass 39, count 2 2006.201.17:58:10.06#ibcon#about to read 4, iclass 39, count 2 2006.201.17:58:10.06#ibcon#read 4, iclass 39, count 2 2006.201.17:58:10.06#ibcon#about to read 5, iclass 39, count 2 2006.201.17:58:10.06#ibcon#read 5, iclass 39, count 2 2006.201.17:58:10.06#ibcon#about to read 6, iclass 39, count 2 2006.201.17:58:10.06#ibcon#read 6, iclass 39, count 2 2006.201.17:58:10.06#ibcon#end of sib2, iclass 39, count 2 2006.201.17:58:10.06#ibcon#*after write, iclass 39, count 2 2006.201.17:58:10.06#ibcon#*before return 0, iclass 39, count 2 2006.201.17:58:10.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:10.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.17:58:10.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.17:58:10.06#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:10.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:10.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:10.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:10.18#ibcon#enter wrdev, iclass 39, count 0 2006.201.17:58:10.18#ibcon#first serial, iclass 39, count 0 2006.201.17:58:10.18#ibcon#enter sib2, iclass 39, count 0 2006.201.17:58:10.18#ibcon#flushed, iclass 39, count 0 2006.201.17:58:10.18#ibcon#about to write, iclass 39, count 0 2006.201.17:58:10.18#ibcon#wrote, iclass 39, count 0 2006.201.17:58:10.18#ibcon#about to read 3, iclass 39, count 0 2006.201.17:58:10.20#ibcon#read 3, iclass 39, count 0 2006.201.17:58:10.20#ibcon#about to read 4, iclass 39, count 0 2006.201.17:58:10.20#ibcon#read 4, iclass 39, count 0 2006.201.17:58:10.20#ibcon#about to read 5, iclass 39, count 0 2006.201.17:58:10.20#ibcon#read 5, iclass 39, count 0 2006.201.17:58:10.20#ibcon#about to read 6, iclass 39, count 0 2006.201.17:58:10.20#ibcon#read 6, iclass 39, count 0 2006.201.17:58:10.20#ibcon#end of sib2, iclass 39, count 0 2006.201.17:58:10.20#ibcon#*mode == 0, iclass 39, count 0 2006.201.17:58:10.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.17:58:10.20#ibcon#[27=USB\r\n] 2006.201.17:58:10.20#ibcon#*before write, iclass 39, count 0 2006.201.17:58:10.20#ibcon#enter sib2, iclass 39, count 0 2006.201.17:58:10.20#ibcon#flushed, iclass 39, count 0 2006.201.17:58:10.20#ibcon#about to write, iclass 39, count 0 2006.201.17:58:10.20#ibcon#wrote, iclass 39, count 0 2006.201.17:58:10.20#ibcon#about to read 3, iclass 39, count 0 2006.201.17:58:10.23#ibcon#read 3, iclass 39, count 0 2006.201.17:58:10.23#ibcon#about to read 4, iclass 39, count 0 2006.201.17:58:10.23#ibcon#read 4, iclass 39, count 0 2006.201.17:58:10.23#ibcon#about to read 5, iclass 39, count 0 2006.201.17:58:10.23#ibcon#read 5, iclass 39, count 0 2006.201.17:58:10.23#ibcon#about to read 6, iclass 39, count 0 2006.201.17:58:10.23#ibcon#read 6, iclass 39, count 0 2006.201.17:58:10.23#ibcon#end of sib2, iclass 39, count 0 2006.201.17:58:10.23#ibcon#*after write, iclass 39, count 0 2006.201.17:58:10.23#ibcon#*before return 0, iclass 39, count 0 2006.201.17:58:10.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:10.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.17:58:10.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.17:58:10.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.17:58:10.23$vck44/vblo=3,649.99 2006.201.17:58:10.23#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.17:58:10.23#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.17:58:10.23#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:10.23#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:10.23#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:10.23#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:10.23#ibcon#enter wrdev, iclass 2, count 0 2006.201.17:58:10.23#ibcon#first serial, iclass 2, count 0 2006.201.17:58:10.23#ibcon#enter sib2, iclass 2, count 0 2006.201.17:58:10.23#ibcon#flushed, iclass 2, count 0 2006.201.17:58:10.23#ibcon#about to write, iclass 2, count 0 2006.201.17:58:10.23#ibcon#wrote, iclass 2, count 0 2006.201.17:58:10.23#ibcon#about to read 3, iclass 2, count 0 2006.201.17:58:10.25#ibcon#read 3, iclass 2, count 0 2006.201.17:58:10.25#ibcon#about to read 4, iclass 2, count 0 2006.201.17:58:10.25#ibcon#read 4, iclass 2, count 0 2006.201.17:58:10.25#ibcon#about to read 5, iclass 2, count 0 2006.201.17:58:10.25#ibcon#read 5, iclass 2, count 0 2006.201.17:58:10.25#ibcon#about to read 6, iclass 2, count 0 2006.201.17:58:10.25#ibcon#read 6, iclass 2, count 0 2006.201.17:58:10.25#ibcon#end of sib2, iclass 2, count 0 2006.201.17:58:10.25#ibcon#*mode == 0, iclass 2, count 0 2006.201.17:58:10.25#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.17:58:10.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.17:58:10.25#ibcon#*before write, iclass 2, count 0 2006.201.17:58:10.25#ibcon#enter sib2, iclass 2, count 0 2006.201.17:58:10.25#ibcon#flushed, iclass 2, count 0 2006.201.17:58:10.25#ibcon#about to write, iclass 2, count 0 2006.201.17:58:10.25#ibcon#wrote, iclass 2, count 0 2006.201.17:58:10.25#ibcon#about to read 3, iclass 2, count 0 2006.201.17:58:10.29#ibcon#read 3, iclass 2, count 0 2006.201.17:58:10.29#ibcon#about to read 4, iclass 2, count 0 2006.201.17:58:10.29#ibcon#read 4, iclass 2, count 0 2006.201.17:58:10.29#ibcon#about to read 5, iclass 2, count 0 2006.201.17:58:10.29#ibcon#read 5, iclass 2, count 0 2006.201.17:58:10.29#ibcon#about to read 6, iclass 2, count 0 2006.201.17:58:10.29#ibcon#read 6, iclass 2, count 0 2006.201.17:58:10.29#ibcon#end of sib2, iclass 2, count 0 2006.201.17:58:10.29#ibcon#*after write, iclass 2, count 0 2006.201.17:58:10.29#ibcon#*before return 0, iclass 2, count 0 2006.201.17:58:10.29#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:10.29#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.17:58:10.29#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.17:58:10.29#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.17:58:10.29$vck44/vb=3,4 2006.201.17:58:10.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.17:58:10.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.17:58:10.29#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:10.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:10.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:10.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:10.35#ibcon#enter wrdev, iclass 5, count 2 2006.201.17:58:10.35#ibcon#first serial, iclass 5, count 2 2006.201.17:58:10.35#ibcon#enter sib2, iclass 5, count 2 2006.201.17:58:10.35#ibcon#flushed, iclass 5, count 2 2006.201.17:58:10.35#ibcon#about to write, iclass 5, count 2 2006.201.17:58:10.35#ibcon#wrote, iclass 5, count 2 2006.201.17:58:10.35#ibcon#about to read 3, iclass 5, count 2 2006.201.17:58:10.37#ibcon#read 3, iclass 5, count 2 2006.201.17:58:10.37#ibcon#about to read 4, iclass 5, count 2 2006.201.17:58:10.37#ibcon#read 4, iclass 5, count 2 2006.201.17:58:10.37#ibcon#about to read 5, iclass 5, count 2 2006.201.17:58:10.37#ibcon#read 5, iclass 5, count 2 2006.201.17:58:10.37#ibcon#about to read 6, iclass 5, count 2 2006.201.17:58:10.37#ibcon#read 6, iclass 5, count 2 2006.201.17:58:10.37#ibcon#end of sib2, iclass 5, count 2 2006.201.17:58:10.37#ibcon#*mode == 0, iclass 5, count 2 2006.201.17:58:10.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.17:58:10.37#ibcon#[27=AT03-04\r\n] 2006.201.17:58:10.37#ibcon#*before write, iclass 5, count 2 2006.201.17:58:10.37#ibcon#enter sib2, iclass 5, count 2 2006.201.17:58:10.37#ibcon#flushed, iclass 5, count 2 2006.201.17:58:10.37#ibcon#about to write, iclass 5, count 2 2006.201.17:58:10.37#ibcon#wrote, iclass 5, count 2 2006.201.17:58:10.37#ibcon#about to read 3, iclass 5, count 2 2006.201.17:58:10.40#ibcon#read 3, iclass 5, count 2 2006.201.17:58:10.40#ibcon#about to read 4, iclass 5, count 2 2006.201.17:58:10.40#ibcon#read 4, iclass 5, count 2 2006.201.17:58:10.40#ibcon#about to read 5, iclass 5, count 2 2006.201.17:58:10.40#ibcon#read 5, iclass 5, count 2 2006.201.17:58:10.40#ibcon#about to read 6, iclass 5, count 2 2006.201.17:58:10.40#ibcon#read 6, iclass 5, count 2 2006.201.17:58:10.40#ibcon#end of sib2, iclass 5, count 2 2006.201.17:58:10.40#ibcon#*after write, iclass 5, count 2 2006.201.17:58:10.40#ibcon#*before return 0, iclass 5, count 2 2006.201.17:58:10.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:10.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.17:58:10.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.17:58:10.40#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:10.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:10.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:10.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:10.52#ibcon#enter wrdev, iclass 5, count 0 2006.201.17:58:10.52#ibcon#first serial, iclass 5, count 0 2006.201.17:58:10.52#ibcon#enter sib2, iclass 5, count 0 2006.201.17:58:10.52#ibcon#flushed, iclass 5, count 0 2006.201.17:58:10.52#ibcon#about to write, iclass 5, count 0 2006.201.17:58:10.52#ibcon#wrote, iclass 5, count 0 2006.201.17:58:10.52#ibcon#about to read 3, iclass 5, count 0 2006.201.17:58:10.54#ibcon#read 3, iclass 5, count 0 2006.201.17:58:10.54#ibcon#about to read 4, iclass 5, count 0 2006.201.17:58:10.54#ibcon#read 4, iclass 5, count 0 2006.201.17:58:10.54#ibcon#about to read 5, iclass 5, count 0 2006.201.17:58:10.54#ibcon#read 5, iclass 5, count 0 2006.201.17:58:10.54#ibcon#about to read 6, iclass 5, count 0 2006.201.17:58:10.54#ibcon#read 6, iclass 5, count 0 2006.201.17:58:10.54#ibcon#end of sib2, iclass 5, count 0 2006.201.17:58:10.54#ibcon#*mode == 0, iclass 5, count 0 2006.201.17:58:10.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.17:58:10.54#ibcon#[27=USB\r\n] 2006.201.17:58:10.54#ibcon#*before write, iclass 5, count 0 2006.201.17:58:10.54#ibcon#enter sib2, iclass 5, count 0 2006.201.17:58:10.54#ibcon#flushed, iclass 5, count 0 2006.201.17:58:10.54#ibcon#about to write, iclass 5, count 0 2006.201.17:58:10.54#ibcon#wrote, iclass 5, count 0 2006.201.17:58:10.54#ibcon#about to read 3, iclass 5, count 0 2006.201.17:58:10.57#ibcon#read 3, iclass 5, count 0 2006.201.17:58:10.57#ibcon#about to read 4, iclass 5, count 0 2006.201.17:58:10.57#ibcon#read 4, iclass 5, count 0 2006.201.17:58:10.57#ibcon#about to read 5, iclass 5, count 0 2006.201.17:58:10.57#ibcon#read 5, iclass 5, count 0 2006.201.17:58:10.57#ibcon#about to read 6, iclass 5, count 0 2006.201.17:58:10.57#ibcon#read 6, iclass 5, count 0 2006.201.17:58:10.57#ibcon#end of sib2, iclass 5, count 0 2006.201.17:58:10.57#ibcon#*after write, iclass 5, count 0 2006.201.17:58:10.57#ibcon#*before return 0, iclass 5, count 0 2006.201.17:58:10.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:10.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.17:58:10.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.17:58:10.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.17:58:10.57$vck44/vblo=4,679.99 2006.201.17:58:10.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.17:58:10.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.17:58:10.57#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:10.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:10.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:10.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:10.57#ibcon#enter wrdev, iclass 7, count 0 2006.201.17:58:10.57#ibcon#first serial, iclass 7, count 0 2006.201.17:58:10.57#ibcon#enter sib2, iclass 7, count 0 2006.201.17:58:10.57#ibcon#flushed, iclass 7, count 0 2006.201.17:58:10.57#ibcon#about to write, iclass 7, count 0 2006.201.17:58:10.57#ibcon#wrote, iclass 7, count 0 2006.201.17:58:10.57#ibcon#about to read 3, iclass 7, count 0 2006.201.17:58:10.59#ibcon#read 3, iclass 7, count 0 2006.201.17:58:10.59#ibcon#about to read 4, iclass 7, count 0 2006.201.17:58:10.59#ibcon#read 4, iclass 7, count 0 2006.201.17:58:10.59#ibcon#about to read 5, iclass 7, count 0 2006.201.17:58:10.59#ibcon#read 5, iclass 7, count 0 2006.201.17:58:10.59#ibcon#about to read 6, iclass 7, count 0 2006.201.17:58:10.59#ibcon#read 6, iclass 7, count 0 2006.201.17:58:10.59#ibcon#end of sib2, iclass 7, count 0 2006.201.17:58:10.59#ibcon#*mode == 0, iclass 7, count 0 2006.201.17:58:10.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.17:58:10.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.17:58:10.59#ibcon#*before write, iclass 7, count 0 2006.201.17:58:10.59#ibcon#enter sib2, iclass 7, count 0 2006.201.17:58:10.59#ibcon#flushed, iclass 7, count 0 2006.201.17:58:10.59#ibcon#about to write, iclass 7, count 0 2006.201.17:58:10.59#ibcon#wrote, iclass 7, count 0 2006.201.17:58:10.59#ibcon#about to read 3, iclass 7, count 0 2006.201.17:58:10.63#ibcon#read 3, iclass 7, count 0 2006.201.17:58:10.63#ibcon#about to read 4, iclass 7, count 0 2006.201.17:58:10.63#ibcon#read 4, iclass 7, count 0 2006.201.17:58:10.63#ibcon#about to read 5, iclass 7, count 0 2006.201.17:58:10.63#ibcon#read 5, iclass 7, count 0 2006.201.17:58:10.63#ibcon#about to read 6, iclass 7, count 0 2006.201.17:58:10.63#ibcon#read 6, iclass 7, count 0 2006.201.17:58:10.63#ibcon#end of sib2, iclass 7, count 0 2006.201.17:58:10.63#ibcon#*after write, iclass 7, count 0 2006.201.17:58:10.63#ibcon#*before return 0, iclass 7, count 0 2006.201.17:58:10.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:10.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.17:58:10.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.17:58:10.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.17:58:10.63$vck44/vb=4,5 2006.201.17:58:10.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.17:58:10.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.17:58:10.63#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:10.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:10.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:10.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:10.69#ibcon#enter wrdev, iclass 11, count 2 2006.201.17:58:10.69#ibcon#first serial, iclass 11, count 2 2006.201.17:58:10.69#ibcon#enter sib2, iclass 11, count 2 2006.201.17:58:10.69#ibcon#flushed, iclass 11, count 2 2006.201.17:58:10.69#ibcon#about to write, iclass 11, count 2 2006.201.17:58:10.69#ibcon#wrote, iclass 11, count 2 2006.201.17:58:10.69#ibcon#about to read 3, iclass 11, count 2 2006.201.17:58:10.71#ibcon#read 3, iclass 11, count 2 2006.201.17:58:10.71#ibcon#about to read 4, iclass 11, count 2 2006.201.17:58:10.71#ibcon#read 4, iclass 11, count 2 2006.201.17:58:10.71#ibcon#about to read 5, iclass 11, count 2 2006.201.17:58:10.71#ibcon#read 5, iclass 11, count 2 2006.201.17:58:10.71#ibcon#about to read 6, iclass 11, count 2 2006.201.17:58:10.71#ibcon#read 6, iclass 11, count 2 2006.201.17:58:10.71#ibcon#end of sib2, iclass 11, count 2 2006.201.17:58:10.71#ibcon#*mode == 0, iclass 11, count 2 2006.201.17:58:10.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.17:58:10.71#ibcon#[27=AT04-05\r\n] 2006.201.17:58:10.71#ibcon#*before write, iclass 11, count 2 2006.201.17:58:10.71#ibcon#enter sib2, iclass 11, count 2 2006.201.17:58:10.71#ibcon#flushed, iclass 11, count 2 2006.201.17:58:10.71#ibcon#about to write, iclass 11, count 2 2006.201.17:58:10.71#ibcon#wrote, iclass 11, count 2 2006.201.17:58:10.71#ibcon#about to read 3, iclass 11, count 2 2006.201.17:58:10.74#ibcon#read 3, iclass 11, count 2 2006.201.17:58:10.74#ibcon#about to read 4, iclass 11, count 2 2006.201.17:58:10.74#ibcon#read 4, iclass 11, count 2 2006.201.17:58:10.74#ibcon#about to read 5, iclass 11, count 2 2006.201.17:58:10.74#ibcon#read 5, iclass 11, count 2 2006.201.17:58:10.74#ibcon#about to read 6, iclass 11, count 2 2006.201.17:58:10.74#ibcon#read 6, iclass 11, count 2 2006.201.17:58:10.74#ibcon#end of sib2, iclass 11, count 2 2006.201.17:58:10.74#ibcon#*after write, iclass 11, count 2 2006.201.17:58:10.74#ibcon#*before return 0, iclass 11, count 2 2006.201.17:58:10.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:10.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.17:58:10.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.17:58:10.74#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:10.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:10.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:10.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:10.86#ibcon#enter wrdev, iclass 11, count 0 2006.201.17:58:10.86#ibcon#first serial, iclass 11, count 0 2006.201.17:58:10.86#ibcon#enter sib2, iclass 11, count 0 2006.201.17:58:10.86#ibcon#flushed, iclass 11, count 0 2006.201.17:58:10.86#ibcon#about to write, iclass 11, count 0 2006.201.17:58:10.86#ibcon#wrote, iclass 11, count 0 2006.201.17:58:10.86#ibcon#about to read 3, iclass 11, count 0 2006.201.17:58:10.88#ibcon#read 3, iclass 11, count 0 2006.201.17:58:10.88#ibcon#about to read 4, iclass 11, count 0 2006.201.17:58:10.88#ibcon#read 4, iclass 11, count 0 2006.201.17:58:10.88#ibcon#about to read 5, iclass 11, count 0 2006.201.17:58:10.88#ibcon#read 5, iclass 11, count 0 2006.201.17:58:10.88#ibcon#about to read 6, iclass 11, count 0 2006.201.17:58:10.88#ibcon#read 6, iclass 11, count 0 2006.201.17:58:10.88#ibcon#end of sib2, iclass 11, count 0 2006.201.17:58:10.88#ibcon#*mode == 0, iclass 11, count 0 2006.201.17:58:10.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.17:58:10.88#ibcon#[27=USB\r\n] 2006.201.17:58:10.88#ibcon#*before write, iclass 11, count 0 2006.201.17:58:10.88#ibcon#enter sib2, iclass 11, count 0 2006.201.17:58:10.88#ibcon#flushed, iclass 11, count 0 2006.201.17:58:10.88#ibcon#about to write, iclass 11, count 0 2006.201.17:58:10.88#ibcon#wrote, iclass 11, count 0 2006.201.17:58:10.88#ibcon#about to read 3, iclass 11, count 0 2006.201.17:58:10.91#ibcon#read 3, iclass 11, count 0 2006.201.17:58:10.91#ibcon#about to read 4, iclass 11, count 0 2006.201.17:58:10.91#ibcon#read 4, iclass 11, count 0 2006.201.17:58:10.91#ibcon#about to read 5, iclass 11, count 0 2006.201.17:58:10.91#ibcon#read 5, iclass 11, count 0 2006.201.17:58:10.91#ibcon#about to read 6, iclass 11, count 0 2006.201.17:58:10.91#ibcon#read 6, iclass 11, count 0 2006.201.17:58:10.91#ibcon#end of sib2, iclass 11, count 0 2006.201.17:58:10.91#ibcon#*after write, iclass 11, count 0 2006.201.17:58:10.91#ibcon#*before return 0, iclass 11, count 0 2006.201.17:58:10.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:10.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.17:58:10.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.17:58:10.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.17:58:10.91$vck44/vblo=5,709.99 2006.201.17:58:10.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.17:58:10.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.17:58:10.91#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:10.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:10.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:10.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:10.91#ibcon#enter wrdev, iclass 13, count 0 2006.201.17:58:10.91#ibcon#first serial, iclass 13, count 0 2006.201.17:58:10.91#ibcon#enter sib2, iclass 13, count 0 2006.201.17:58:10.91#ibcon#flushed, iclass 13, count 0 2006.201.17:58:10.91#ibcon#about to write, iclass 13, count 0 2006.201.17:58:10.91#ibcon#wrote, iclass 13, count 0 2006.201.17:58:10.91#ibcon#about to read 3, iclass 13, count 0 2006.201.17:58:10.93#ibcon#read 3, iclass 13, count 0 2006.201.17:58:10.93#ibcon#about to read 4, iclass 13, count 0 2006.201.17:58:10.93#ibcon#read 4, iclass 13, count 0 2006.201.17:58:10.93#ibcon#about to read 5, iclass 13, count 0 2006.201.17:58:10.93#ibcon#read 5, iclass 13, count 0 2006.201.17:58:10.93#ibcon#about to read 6, iclass 13, count 0 2006.201.17:58:10.93#ibcon#read 6, iclass 13, count 0 2006.201.17:58:10.93#ibcon#end of sib2, iclass 13, count 0 2006.201.17:58:10.93#ibcon#*mode == 0, iclass 13, count 0 2006.201.17:58:10.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.17:58:10.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.17:58:10.93#ibcon#*before write, iclass 13, count 0 2006.201.17:58:10.93#ibcon#enter sib2, iclass 13, count 0 2006.201.17:58:10.93#ibcon#flushed, iclass 13, count 0 2006.201.17:58:10.93#ibcon#about to write, iclass 13, count 0 2006.201.17:58:10.93#ibcon#wrote, iclass 13, count 0 2006.201.17:58:10.93#ibcon#about to read 3, iclass 13, count 0 2006.201.17:58:10.97#ibcon#read 3, iclass 13, count 0 2006.201.17:58:10.97#ibcon#about to read 4, iclass 13, count 0 2006.201.17:58:10.97#ibcon#read 4, iclass 13, count 0 2006.201.17:58:10.97#ibcon#about to read 5, iclass 13, count 0 2006.201.17:58:10.97#ibcon#read 5, iclass 13, count 0 2006.201.17:58:10.97#ibcon#about to read 6, iclass 13, count 0 2006.201.17:58:10.97#ibcon#read 6, iclass 13, count 0 2006.201.17:58:10.97#ibcon#end of sib2, iclass 13, count 0 2006.201.17:58:10.97#ibcon#*after write, iclass 13, count 0 2006.201.17:58:10.97#ibcon#*before return 0, iclass 13, count 0 2006.201.17:58:10.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:10.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.17:58:10.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.17:58:10.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.17:58:10.97$vck44/vb=5,4 2006.201.17:58:10.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.17:58:10.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.17:58:10.97#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:10.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:11.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:11.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:11.03#ibcon#enter wrdev, iclass 15, count 2 2006.201.17:58:11.03#ibcon#first serial, iclass 15, count 2 2006.201.17:58:11.03#ibcon#enter sib2, iclass 15, count 2 2006.201.17:58:11.03#ibcon#flushed, iclass 15, count 2 2006.201.17:58:11.03#ibcon#about to write, iclass 15, count 2 2006.201.17:58:11.03#ibcon#wrote, iclass 15, count 2 2006.201.17:58:11.03#ibcon#about to read 3, iclass 15, count 2 2006.201.17:58:11.05#ibcon#read 3, iclass 15, count 2 2006.201.17:58:11.05#ibcon#about to read 4, iclass 15, count 2 2006.201.17:58:11.05#ibcon#read 4, iclass 15, count 2 2006.201.17:58:11.05#ibcon#about to read 5, iclass 15, count 2 2006.201.17:58:11.05#ibcon#read 5, iclass 15, count 2 2006.201.17:58:11.05#ibcon#about to read 6, iclass 15, count 2 2006.201.17:58:11.05#ibcon#read 6, iclass 15, count 2 2006.201.17:58:11.05#ibcon#end of sib2, iclass 15, count 2 2006.201.17:58:11.05#ibcon#*mode == 0, iclass 15, count 2 2006.201.17:58:11.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.17:58:11.05#ibcon#[27=AT05-04\r\n] 2006.201.17:58:11.05#ibcon#*before write, iclass 15, count 2 2006.201.17:58:11.05#ibcon#enter sib2, iclass 15, count 2 2006.201.17:58:11.05#ibcon#flushed, iclass 15, count 2 2006.201.17:58:11.05#ibcon#about to write, iclass 15, count 2 2006.201.17:58:11.05#ibcon#wrote, iclass 15, count 2 2006.201.17:58:11.05#ibcon#about to read 3, iclass 15, count 2 2006.201.17:58:11.08#ibcon#read 3, iclass 15, count 2 2006.201.17:58:11.08#ibcon#about to read 4, iclass 15, count 2 2006.201.17:58:11.08#ibcon#read 4, iclass 15, count 2 2006.201.17:58:11.08#ibcon#about to read 5, iclass 15, count 2 2006.201.17:58:11.08#ibcon#read 5, iclass 15, count 2 2006.201.17:58:11.08#ibcon#about to read 6, iclass 15, count 2 2006.201.17:58:11.08#ibcon#read 6, iclass 15, count 2 2006.201.17:58:11.08#ibcon#end of sib2, iclass 15, count 2 2006.201.17:58:11.08#ibcon#*after write, iclass 15, count 2 2006.201.17:58:11.08#ibcon#*before return 0, iclass 15, count 2 2006.201.17:58:11.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:11.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.17:58:11.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.17:58:11.08#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:11.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:11.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:11.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:11.20#ibcon#enter wrdev, iclass 15, count 0 2006.201.17:58:11.20#ibcon#first serial, iclass 15, count 0 2006.201.17:58:11.20#ibcon#enter sib2, iclass 15, count 0 2006.201.17:58:11.20#ibcon#flushed, iclass 15, count 0 2006.201.17:58:11.20#ibcon#about to write, iclass 15, count 0 2006.201.17:58:11.20#ibcon#wrote, iclass 15, count 0 2006.201.17:58:11.20#ibcon#about to read 3, iclass 15, count 0 2006.201.17:58:11.22#ibcon#read 3, iclass 15, count 0 2006.201.17:58:11.22#ibcon#about to read 4, iclass 15, count 0 2006.201.17:58:11.22#ibcon#read 4, iclass 15, count 0 2006.201.17:58:11.22#ibcon#about to read 5, iclass 15, count 0 2006.201.17:58:11.22#ibcon#read 5, iclass 15, count 0 2006.201.17:58:11.22#ibcon#about to read 6, iclass 15, count 0 2006.201.17:58:11.22#ibcon#read 6, iclass 15, count 0 2006.201.17:58:11.22#ibcon#end of sib2, iclass 15, count 0 2006.201.17:58:11.22#ibcon#*mode == 0, iclass 15, count 0 2006.201.17:58:11.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.17:58:11.22#ibcon#[27=USB\r\n] 2006.201.17:58:11.22#ibcon#*before write, iclass 15, count 0 2006.201.17:58:11.22#ibcon#enter sib2, iclass 15, count 0 2006.201.17:58:11.22#ibcon#flushed, iclass 15, count 0 2006.201.17:58:11.22#ibcon#about to write, iclass 15, count 0 2006.201.17:58:11.22#ibcon#wrote, iclass 15, count 0 2006.201.17:58:11.22#ibcon#about to read 3, iclass 15, count 0 2006.201.17:58:11.25#ibcon#read 3, iclass 15, count 0 2006.201.17:58:11.25#ibcon#about to read 4, iclass 15, count 0 2006.201.17:58:11.25#ibcon#read 4, iclass 15, count 0 2006.201.17:58:11.25#ibcon#about to read 5, iclass 15, count 0 2006.201.17:58:11.25#ibcon#read 5, iclass 15, count 0 2006.201.17:58:11.25#ibcon#about to read 6, iclass 15, count 0 2006.201.17:58:11.25#ibcon#read 6, iclass 15, count 0 2006.201.17:58:11.25#ibcon#end of sib2, iclass 15, count 0 2006.201.17:58:11.25#ibcon#*after write, iclass 15, count 0 2006.201.17:58:11.25#ibcon#*before return 0, iclass 15, count 0 2006.201.17:58:11.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:11.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.17:58:11.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.17:58:11.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.17:58:11.25$vck44/vblo=6,719.99 2006.201.17:58:11.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.17:58:11.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.17:58:11.25#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:11.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:11.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:11.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:11.25#ibcon#enter wrdev, iclass 17, count 0 2006.201.17:58:11.25#ibcon#first serial, iclass 17, count 0 2006.201.17:58:11.25#ibcon#enter sib2, iclass 17, count 0 2006.201.17:58:11.25#ibcon#flushed, iclass 17, count 0 2006.201.17:58:11.25#ibcon#about to write, iclass 17, count 0 2006.201.17:58:11.25#ibcon#wrote, iclass 17, count 0 2006.201.17:58:11.25#ibcon#about to read 3, iclass 17, count 0 2006.201.17:58:11.27#ibcon#read 3, iclass 17, count 0 2006.201.17:58:11.27#ibcon#about to read 4, iclass 17, count 0 2006.201.17:58:11.27#ibcon#read 4, iclass 17, count 0 2006.201.17:58:11.27#ibcon#about to read 5, iclass 17, count 0 2006.201.17:58:11.27#ibcon#read 5, iclass 17, count 0 2006.201.17:58:11.27#ibcon#about to read 6, iclass 17, count 0 2006.201.17:58:11.27#ibcon#read 6, iclass 17, count 0 2006.201.17:58:11.27#ibcon#end of sib2, iclass 17, count 0 2006.201.17:58:11.27#ibcon#*mode == 0, iclass 17, count 0 2006.201.17:58:11.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.17:58:11.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.17:58:11.27#ibcon#*before write, iclass 17, count 0 2006.201.17:58:11.27#ibcon#enter sib2, iclass 17, count 0 2006.201.17:58:11.27#ibcon#flushed, iclass 17, count 0 2006.201.17:58:11.27#ibcon#about to write, iclass 17, count 0 2006.201.17:58:11.27#ibcon#wrote, iclass 17, count 0 2006.201.17:58:11.27#ibcon#about to read 3, iclass 17, count 0 2006.201.17:58:11.31#ibcon#read 3, iclass 17, count 0 2006.201.17:58:11.31#ibcon#about to read 4, iclass 17, count 0 2006.201.17:58:11.31#ibcon#read 4, iclass 17, count 0 2006.201.17:58:11.31#ibcon#about to read 5, iclass 17, count 0 2006.201.17:58:11.31#ibcon#read 5, iclass 17, count 0 2006.201.17:58:11.31#ibcon#about to read 6, iclass 17, count 0 2006.201.17:58:11.31#ibcon#read 6, iclass 17, count 0 2006.201.17:58:11.31#ibcon#end of sib2, iclass 17, count 0 2006.201.17:58:11.31#ibcon#*after write, iclass 17, count 0 2006.201.17:58:11.31#ibcon#*before return 0, iclass 17, count 0 2006.201.17:58:11.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:11.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.17:58:11.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.17:58:11.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.17:58:11.31$vck44/vb=6,4 2006.201.17:58:11.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.17:58:11.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.17:58:11.31#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:11.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:58:11.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:58:11.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:58:11.37#ibcon#enter wrdev, iclass 19, count 2 2006.201.17:58:11.37#ibcon#first serial, iclass 19, count 2 2006.201.17:58:11.37#ibcon#enter sib2, iclass 19, count 2 2006.201.17:58:11.37#ibcon#flushed, iclass 19, count 2 2006.201.17:58:11.37#ibcon#about to write, iclass 19, count 2 2006.201.17:58:11.37#ibcon#wrote, iclass 19, count 2 2006.201.17:58:11.37#ibcon#about to read 3, iclass 19, count 2 2006.201.17:58:11.39#ibcon#read 3, iclass 19, count 2 2006.201.17:58:11.39#ibcon#about to read 4, iclass 19, count 2 2006.201.17:58:11.39#ibcon#read 4, iclass 19, count 2 2006.201.17:58:11.39#ibcon#about to read 5, iclass 19, count 2 2006.201.17:58:11.39#ibcon#read 5, iclass 19, count 2 2006.201.17:58:11.39#ibcon#about to read 6, iclass 19, count 2 2006.201.17:58:11.39#ibcon#read 6, iclass 19, count 2 2006.201.17:58:11.39#ibcon#end of sib2, iclass 19, count 2 2006.201.17:58:11.39#ibcon#*mode == 0, iclass 19, count 2 2006.201.17:58:11.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.17:58:11.39#ibcon#[27=AT06-04\r\n] 2006.201.17:58:11.39#ibcon#*before write, iclass 19, count 2 2006.201.17:58:11.39#ibcon#enter sib2, iclass 19, count 2 2006.201.17:58:11.39#ibcon#flushed, iclass 19, count 2 2006.201.17:58:11.39#ibcon#about to write, iclass 19, count 2 2006.201.17:58:11.39#ibcon#wrote, iclass 19, count 2 2006.201.17:58:11.39#ibcon#about to read 3, iclass 19, count 2 2006.201.17:58:11.42#ibcon#read 3, iclass 19, count 2 2006.201.17:58:11.42#ibcon#about to read 4, iclass 19, count 2 2006.201.17:58:11.42#ibcon#read 4, iclass 19, count 2 2006.201.17:58:11.42#ibcon#about to read 5, iclass 19, count 2 2006.201.17:58:11.42#ibcon#read 5, iclass 19, count 2 2006.201.17:58:11.42#ibcon#about to read 6, iclass 19, count 2 2006.201.17:58:11.42#ibcon#read 6, iclass 19, count 2 2006.201.17:58:11.42#ibcon#end of sib2, iclass 19, count 2 2006.201.17:58:11.42#ibcon#*after write, iclass 19, count 2 2006.201.17:58:11.42#ibcon#*before return 0, iclass 19, count 2 2006.201.17:58:11.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:58:11.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.17:58:11.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.17:58:11.42#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:11.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:58:11.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:58:11.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:58:11.54#ibcon#enter wrdev, iclass 19, count 0 2006.201.17:58:11.54#ibcon#first serial, iclass 19, count 0 2006.201.17:58:11.54#ibcon#enter sib2, iclass 19, count 0 2006.201.17:58:11.54#ibcon#flushed, iclass 19, count 0 2006.201.17:58:11.54#ibcon#about to write, iclass 19, count 0 2006.201.17:58:11.54#ibcon#wrote, iclass 19, count 0 2006.201.17:58:11.54#ibcon#about to read 3, iclass 19, count 0 2006.201.17:58:11.56#ibcon#read 3, iclass 19, count 0 2006.201.17:58:11.56#ibcon#about to read 4, iclass 19, count 0 2006.201.17:58:11.56#ibcon#read 4, iclass 19, count 0 2006.201.17:58:11.56#ibcon#about to read 5, iclass 19, count 0 2006.201.17:58:11.56#ibcon#read 5, iclass 19, count 0 2006.201.17:58:11.56#ibcon#about to read 6, iclass 19, count 0 2006.201.17:58:11.56#ibcon#read 6, iclass 19, count 0 2006.201.17:58:11.56#ibcon#end of sib2, iclass 19, count 0 2006.201.17:58:11.56#ibcon#*mode == 0, iclass 19, count 0 2006.201.17:58:11.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.17:58:11.56#ibcon#[27=USB\r\n] 2006.201.17:58:11.56#ibcon#*before write, iclass 19, count 0 2006.201.17:58:11.56#ibcon#enter sib2, iclass 19, count 0 2006.201.17:58:11.56#ibcon#flushed, iclass 19, count 0 2006.201.17:58:11.56#ibcon#about to write, iclass 19, count 0 2006.201.17:58:11.56#ibcon#wrote, iclass 19, count 0 2006.201.17:58:11.56#ibcon#about to read 3, iclass 19, count 0 2006.201.17:58:11.59#ibcon#read 3, iclass 19, count 0 2006.201.17:58:11.59#ibcon#about to read 4, iclass 19, count 0 2006.201.17:58:11.59#ibcon#read 4, iclass 19, count 0 2006.201.17:58:11.59#ibcon#about to read 5, iclass 19, count 0 2006.201.17:58:11.59#ibcon#read 5, iclass 19, count 0 2006.201.17:58:11.59#ibcon#about to read 6, iclass 19, count 0 2006.201.17:58:11.59#ibcon#read 6, iclass 19, count 0 2006.201.17:58:11.59#ibcon#end of sib2, iclass 19, count 0 2006.201.17:58:11.59#ibcon#*after write, iclass 19, count 0 2006.201.17:58:11.59#ibcon#*before return 0, iclass 19, count 0 2006.201.17:58:11.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:58:11.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.17:58:11.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.17:58:11.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.17:58:11.59$vck44/vblo=7,734.99 2006.201.17:58:11.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.17:58:11.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.17:58:11.59#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:11.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:58:11.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:58:11.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:58:11.59#ibcon#enter wrdev, iclass 21, count 0 2006.201.17:58:11.59#ibcon#first serial, iclass 21, count 0 2006.201.17:58:11.59#ibcon#enter sib2, iclass 21, count 0 2006.201.17:58:11.59#ibcon#flushed, iclass 21, count 0 2006.201.17:58:11.59#ibcon#about to write, iclass 21, count 0 2006.201.17:58:11.59#ibcon#wrote, iclass 21, count 0 2006.201.17:58:11.59#ibcon#about to read 3, iclass 21, count 0 2006.201.17:58:11.61#ibcon#read 3, iclass 21, count 0 2006.201.17:58:11.61#ibcon#about to read 4, iclass 21, count 0 2006.201.17:58:11.61#ibcon#read 4, iclass 21, count 0 2006.201.17:58:11.61#ibcon#about to read 5, iclass 21, count 0 2006.201.17:58:11.61#ibcon#read 5, iclass 21, count 0 2006.201.17:58:11.61#ibcon#about to read 6, iclass 21, count 0 2006.201.17:58:11.61#ibcon#read 6, iclass 21, count 0 2006.201.17:58:11.61#ibcon#end of sib2, iclass 21, count 0 2006.201.17:58:11.61#ibcon#*mode == 0, iclass 21, count 0 2006.201.17:58:11.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.17:58:11.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.17:58:11.61#ibcon#*before write, iclass 21, count 0 2006.201.17:58:11.61#ibcon#enter sib2, iclass 21, count 0 2006.201.17:58:11.61#ibcon#flushed, iclass 21, count 0 2006.201.17:58:11.61#ibcon#about to write, iclass 21, count 0 2006.201.17:58:11.61#ibcon#wrote, iclass 21, count 0 2006.201.17:58:11.61#ibcon#about to read 3, iclass 21, count 0 2006.201.17:58:11.66#ibcon#read 3, iclass 21, count 0 2006.201.17:58:11.66#ibcon#about to read 4, iclass 21, count 0 2006.201.17:58:11.66#ibcon#read 4, iclass 21, count 0 2006.201.17:58:11.66#ibcon#about to read 5, iclass 21, count 0 2006.201.17:58:11.66#ibcon#read 5, iclass 21, count 0 2006.201.17:58:11.66#ibcon#about to read 6, iclass 21, count 0 2006.201.17:58:11.66#ibcon#read 6, iclass 21, count 0 2006.201.17:58:11.66#ibcon#end of sib2, iclass 21, count 0 2006.201.17:58:11.66#ibcon#*after write, iclass 21, count 0 2006.201.17:58:11.66#ibcon#*before return 0, iclass 21, count 0 2006.201.17:58:11.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:58:11.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.17:58:11.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.17:58:11.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.17:58:11.66$vck44/vb=7,4 2006.201.17:58:11.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.17:58:11.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.17:58:11.66#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:11.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:58:11.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:58:11.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:58:11.71#ibcon#enter wrdev, iclass 23, count 2 2006.201.17:58:11.71#ibcon#first serial, iclass 23, count 2 2006.201.17:58:11.71#ibcon#enter sib2, iclass 23, count 2 2006.201.17:58:11.71#ibcon#flushed, iclass 23, count 2 2006.201.17:58:11.71#ibcon#about to write, iclass 23, count 2 2006.201.17:58:11.71#ibcon#wrote, iclass 23, count 2 2006.201.17:58:11.71#ibcon#about to read 3, iclass 23, count 2 2006.201.17:58:11.73#ibcon#read 3, iclass 23, count 2 2006.201.17:58:11.73#ibcon#about to read 4, iclass 23, count 2 2006.201.17:58:11.73#ibcon#read 4, iclass 23, count 2 2006.201.17:58:11.73#ibcon#about to read 5, iclass 23, count 2 2006.201.17:58:11.73#ibcon#read 5, iclass 23, count 2 2006.201.17:58:11.73#ibcon#about to read 6, iclass 23, count 2 2006.201.17:58:11.73#ibcon#read 6, iclass 23, count 2 2006.201.17:58:11.73#ibcon#end of sib2, iclass 23, count 2 2006.201.17:58:11.73#ibcon#*mode == 0, iclass 23, count 2 2006.201.17:58:11.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.17:58:11.73#ibcon#[27=AT07-04\r\n] 2006.201.17:58:11.73#ibcon#*before write, iclass 23, count 2 2006.201.17:58:11.73#ibcon#enter sib2, iclass 23, count 2 2006.201.17:58:11.73#ibcon#flushed, iclass 23, count 2 2006.201.17:58:11.73#ibcon#about to write, iclass 23, count 2 2006.201.17:58:11.73#ibcon#wrote, iclass 23, count 2 2006.201.17:58:11.73#ibcon#about to read 3, iclass 23, count 2 2006.201.17:58:11.76#ibcon#read 3, iclass 23, count 2 2006.201.17:58:11.76#ibcon#about to read 4, iclass 23, count 2 2006.201.17:58:11.76#ibcon#read 4, iclass 23, count 2 2006.201.17:58:11.76#ibcon#about to read 5, iclass 23, count 2 2006.201.17:58:11.76#ibcon#read 5, iclass 23, count 2 2006.201.17:58:11.76#ibcon#about to read 6, iclass 23, count 2 2006.201.17:58:11.76#ibcon#read 6, iclass 23, count 2 2006.201.17:58:11.76#ibcon#end of sib2, iclass 23, count 2 2006.201.17:58:11.76#ibcon#*after write, iclass 23, count 2 2006.201.17:58:11.76#ibcon#*before return 0, iclass 23, count 2 2006.201.17:58:11.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:58:11.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.17:58:11.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.17:58:11.76#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:11.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:58:11.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:58:11.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:58:11.88#ibcon#enter wrdev, iclass 23, count 0 2006.201.17:58:11.88#ibcon#first serial, iclass 23, count 0 2006.201.17:58:11.88#ibcon#enter sib2, iclass 23, count 0 2006.201.17:58:11.88#ibcon#flushed, iclass 23, count 0 2006.201.17:58:11.88#ibcon#about to write, iclass 23, count 0 2006.201.17:58:11.88#ibcon#wrote, iclass 23, count 0 2006.201.17:58:11.88#ibcon#about to read 3, iclass 23, count 0 2006.201.17:58:11.90#ibcon#read 3, iclass 23, count 0 2006.201.17:58:11.90#ibcon#about to read 4, iclass 23, count 0 2006.201.17:58:11.90#ibcon#read 4, iclass 23, count 0 2006.201.17:58:11.90#ibcon#about to read 5, iclass 23, count 0 2006.201.17:58:11.90#ibcon#read 5, iclass 23, count 0 2006.201.17:58:11.90#ibcon#about to read 6, iclass 23, count 0 2006.201.17:58:11.90#ibcon#read 6, iclass 23, count 0 2006.201.17:58:11.90#ibcon#end of sib2, iclass 23, count 0 2006.201.17:58:11.90#ibcon#*mode == 0, iclass 23, count 0 2006.201.17:58:11.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.17:58:11.90#ibcon#[27=USB\r\n] 2006.201.17:58:11.90#ibcon#*before write, iclass 23, count 0 2006.201.17:58:11.90#ibcon#enter sib2, iclass 23, count 0 2006.201.17:58:11.90#ibcon#flushed, iclass 23, count 0 2006.201.17:58:11.90#ibcon#about to write, iclass 23, count 0 2006.201.17:58:11.90#ibcon#wrote, iclass 23, count 0 2006.201.17:58:11.90#ibcon#about to read 3, iclass 23, count 0 2006.201.17:58:11.93#ibcon#read 3, iclass 23, count 0 2006.201.17:58:11.93#ibcon#about to read 4, iclass 23, count 0 2006.201.17:58:11.93#ibcon#read 4, iclass 23, count 0 2006.201.17:58:11.93#ibcon#about to read 5, iclass 23, count 0 2006.201.17:58:11.93#ibcon#read 5, iclass 23, count 0 2006.201.17:58:11.93#ibcon#about to read 6, iclass 23, count 0 2006.201.17:58:11.93#ibcon#read 6, iclass 23, count 0 2006.201.17:58:11.93#ibcon#end of sib2, iclass 23, count 0 2006.201.17:58:11.93#ibcon#*after write, iclass 23, count 0 2006.201.17:58:11.93#ibcon#*before return 0, iclass 23, count 0 2006.201.17:58:11.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:58:11.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.17:58:11.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.17:58:11.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.17:58:11.93$vck44/vblo=8,744.99 2006.201.17:58:11.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.17:58:11.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.17:58:11.93#ibcon#ireg 17 cls_cnt 0 2006.201.17:58:11.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:11.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:11.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:11.93#ibcon#enter wrdev, iclass 25, count 0 2006.201.17:58:11.93#ibcon#first serial, iclass 25, count 0 2006.201.17:58:11.93#ibcon#enter sib2, iclass 25, count 0 2006.201.17:58:11.93#ibcon#flushed, iclass 25, count 0 2006.201.17:58:11.93#ibcon#about to write, iclass 25, count 0 2006.201.17:58:11.93#ibcon#wrote, iclass 25, count 0 2006.201.17:58:11.93#ibcon#about to read 3, iclass 25, count 0 2006.201.17:58:11.95#ibcon#read 3, iclass 25, count 0 2006.201.17:58:11.95#ibcon#about to read 4, iclass 25, count 0 2006.201.17:58:11.95#ibcon#read 4, iclass 25, count 0 2006.201.17:58:11.95#ibcon#about to read 5, iclass 25, count 0 2006.201.17:58:11.95#ibcon#read 5, iclass 25, count 0 2006.201.17:58:11.95#ibcon#about to read 6, iclass 25, count 0 2006.201.17:58:11.95#ibcon#read 6, iclass 25, count 0 2006.201.17:58:11.95#ibcon#end of sib2, iclass 25, count 0 2006.201.17:58:11.95#ibcon#*mode == 0, iclass 25, count 0 2006.201.17:58:11.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.17:58:11.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.17:58:11.95#ibcon#*before write, iclass 25, count 0 2006.201.17:58:11.95#ibcon#enter sib2, iclass 25, count 0 2006.201.17:58:11.95#ibcon#flushed, iclass 25, count 0 2006.201.17:58:11.95#ibcon#about to write, iclass 25, count 0 2006.201.17:58:11.95#ibcon#wrote, iclass 25, count 0 2006.201.17:58:11.95#ibcon#about to read 3, iclass 25, count 0 2006.201.17:58:11.99#ibcon#read 3, iclass 25, count 0 2006.201.17:58:11.99#ibcon#about to read 4, iclass 25, count 0 2006.201.17:58:11.99#ibcon#read 4, iclass 25, count 0 2006.201.17:58:11.99#ibcon#about to read 5, iclass 25, count 0 2006.201.17:58:11.99#ibcon#read 5, iclass 25, count 0 2006.201.17:58:11.99#ibcon#about to read 6, iclass 25, count 0 2006.201.17:58:11.99#ibcon#read 6, iclass 25, count 0 2006.201.17:58:11.99#ibcon#end of sib2, iclass 25, count 0 2006.201.17:58:11.99#ibcon#*after write, iclass 25, count 0 2006.201.17:58:11.99#ibcon#*before return 0, iclass 25, count 0 2006.201.17:58:11.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:11.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.17:58:11.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.17:58:11.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.17:58:11.99$vck44/vb=8,4 2006.201.17:58:11.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.17:58:11.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.17:58:11.99#ibcon#ireg 11 cls_cnt 2 2006.201.17:58:11.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:12.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:12.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:12.05#ibcon#enter wrdev, iclass 27, count 2 2006.201.17:58:12.05#ibcon#first serial, iclass 27, count 2 2006.201.17:58:12.05#ibcon#enter sib2, iclass 27, count 2 2006.201.17:58:12.05#ibcon#flushed, iclass 27, count 2 2006.201.17:58:12.05#ibcon#about to write, iclass 27, count 2 2006.201.17:58:12.05#ibcon#wrote, iclass 27, count 2 2006.201.17:58:12.05#ibcon#about to read 3, iclass 27, count 2 2006.201.17:58:12.07#ibcon#read 3, iclass 27, count 2 2006.201.17:58:12.07#ibcon#about to read 4, iclass 27, count 2 2006.201.17:58:12.07#ibcon#read 4, iclass 27, count 2 2006.201.17:58:12.07#ibcon#about to read 5, iclass 27, count 2 2006.201.17:58:12.07#ibcon#read 5, iclass 27, count 2 2006.201.17:58:12.07#ibcon#about to read 6, iclass 27, count 2 2006.201.17:58:12.07#ibcon#read 6, iclass 27, count 2 2006.201.17:58:12.07#ibcon#end of sib2, iclass 27, count 2 2006.201.17:58:12.07#ibcon#*mode == 0, iclass 27, count 2 2006.201.17:58:12.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.17:58:12.07#ibcon#[27=AT08-04\r\n] 2006.201.17:58:12.07#ibcon#*before write, iclass 27, count 2 2006.201.17:58:12.07#ibcon#enter sib2, iclass 27, count 2 2006.201.17:58:12.07#ibcon#flushed, iclass 27, count 2 2006.201.17:58:12.07#ibcon#about to write, iclass 27, count 2 2006.201.17:58:12.07#ibcon#wrote, iclass 27, count 2 2006.201.17:58:12.07#ibcon#about to read 3, iclass 27, count 2 2006.201.17:58:12.10#ibcon#read 3, iclass 27, count 2 2006.201.17:58:12.10#ibcon#about to read 4, iclass 27, count 2 2006.201.17:58:12.10#ibcon#read 4, iclass 27, count 2 2006.201.17:58:12.10#ibcon#about to read 5, iclass 27, count 2 2006.201.17:58:12.10#ibcon#read 5, iclass 27, count 2 2006.201.17:58:12.10#ibcon#about to read 6, iclass 27, count 2 2006.201.17:58:12.10#ibcon#read 6, iclass 27, count 2 2006.201.17:58:12.10#ibcon#end of sib2, iclass 27, count 2 2006.201.17:58:12.10#ibcon#*after write, iclass 27, count 2 2006.201.17:58:12.10#ibcon#*before return 0, iclass 27, count 2 2006.201.17:58:12.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:12.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.17:58:12.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.17:58:12.10#ibcon#ireg 7 cls_cnt 0 2006.201.17:58:12.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:12.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:12.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:12.22#ibcon#enter wrdev, iclass 27, count 0 2006.201.17:58:12.22#ibcon#first serial, iclass 27, count 0 2006.201.17:58:12.22#ibcon#enter sib2, iclass 27, count 0 2006.201.17:58:12.22#ibcon#flushed, iclass 27, count 0 2006.201.17:58:12.22#ibcon#about to write, iclass 27, count 0 2006.201.17:58:12.22#ibcon#wrote, iclass 27, count 0 2006.201.17:58:12.22#ibcon#about to read 3, iclass 27, count 0 2006.201.17:58:12.24#ibcon#read 3, iclass 27, count 0 2006.201.17:58:12.24#ibcon#about to read 4, iclass 27, count 0 2006.201.17:58:12.24#ibcon#read 4, iclass 27, count 0 2006.201.17:58:12.24#ibcon#about to read 5, iclass 27, count 0 2006.201.17:58:12.24#ibcon#read 5, iclass 27, count 0 2006.201.17:58:12.24#ibcon#about to read 6, iclass 27, count 0 2006.201.17:58:12.24#ibcon#read 6, iclass 27, count 0 2006.201.17:58:12.24#ibcon#end of sib2, iclass 27, count 0 2006.201.17:58:12.24#ibcon#*mode == 0, iclass 27, count 0 2006.201.17:58:12.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.17:58:12.24#ibcon#[27=USB\r\n] 2006.201.17:58:12.24#ibcon#*before write, iclass 27, count 0 2006.201.17:58:12.24#ibcon#enter sib2, iclass 27, count 0 2006.201.17:58:12.24#ibcon#flushed, iclass 27, count 0 2006.201.17:58:12.24#ibcon#about to write, iclass 27, count 0 2006.201.17:58:12.24#ibcon#wrote, iclass 27, count 0 2006.201.17:58:12.24#ibcon#about to read 3, iclass 27, count 0 2006.201.17:58:12.27#ibcon#read 3, iclass 27, count 0 2006.201.17:58:12.27#ibcon#about to read 4, iclass 27, count 0 2006.201.17:58:12.27#ibcon#read 4, iclass 27, count 0 2006.201.17:58:12.27#ibcon#about to read 5, iclass 27, count 0 2006.201.17:58:12.27#ibcon#read 5, iclass 27, count 0 2006.201.17:58:12.27#ibcon#about to read 6, iclass 27, count 0 2006.201.17:58:12.27#ibcon#read 6, iclass 27, count 0 2006.201.17:58:12.27#ibcon#end of sib2, iclass 27, count 0 2006.201.17:58:12.27#ibcon#*after write, iclass 27, count 0 2006.201.17:58:12.27#ibcon#*before return 0, iclass 27, count 0 2006.201.17:58:12.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:12.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.17:58:12.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.17:58:12.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.17:58:12.27$vck44/vabw=wide 2006.201.17:58:12.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.17:58:12.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.17:58:12.27#ibcon#ireg 8 cls_cnt 0 2006.201.17:58:12.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:12.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:12.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:12.27#ibcon#enter wrdev, iclass 29, count 0 2006.201.17:58:12.27#ibcon#first serial, iclass 29, count 0 2006.201.17:58:12.27#ibcon#enter sib2, iclass 29, count 0 2006.201.17:58:12.27#ibcon#flushed, iclass 29, count 0 2006.201.17:58:12.27#ibcon#about to write, iclass 29, count 0 2006.201.17:58:12.27#ibcon#wrote, iclass 29, count 0 2006.201.17:58:12.27#ibcon#about to read 3, iclass 29, count 0 2006.201.17:58:12.29#ibcon#read 3, iclass 29, count 0 2006.201.17:58:12.29#ibcon#about to read 4, iclass 29, count 0 2006.201.17:58:12.29#ibcon#read 4, iclass 29, count 0 2006.201.17:58:12.29#ibcon#about to read 5, iclass 29, count 0 2006.201.17:58:12.29#ibcon#read 5, iclass 29, count 0 2006.201.17:58:12.29#ibcon#about to read 6, iclass 29, count 0 2006.201.17:58:12.29#ibcon#read 6, iclass 29, count 0 2006.201.17:58:12.29#ibcon#end of sib2, iclass 29, count 0 2006.201.17:58:12.29#ibcon#*mode == 0, iclass 29, count 0 2006.201.17:58:12.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.17:58:12.29#ibcon#[25=BW32\r\n] 2006.201.17:58:12.29#ibcon#*before write, iclass 29, count 0 2006.201.17:58:12.29#ibcon#enter sib2, iclass 29, count 0 2006.201.17:58:12.29#ibcon#flushed, iclass 29, count 0 2006.201.17:58:12.29#ibcon#about to write, iclass 29, count 0 2006.201.17:58:12.29#ibcon#wrote, iclass 29, count 0 2006.201.17:58:12.29#ibcon#about to read 3, iclass 29, count 0 2006.201.17:58:12.32#ibcon#read 3, iclass 29, count 0 2006.201.17:58:12.32#ibcon#about to read 4, iclass 29, count 0 2006.201.17:58:12.32#ibcon#read 4, iclass 29, count 0 2006.201.17:58:12.32#ibcon#about to read 5, iclass 29, count 0 2006.201.17:58:12.32#ibcon#read 5, iclass 29, count 0 2006.201.17:58:12.32#ibcon#about to read 6, iclass 29, count 0 2006.201.17:58:12.32#ibcon#read 6, iclass 29, count 0 2006.201.17:58:12.32#ibcon#end of sib2, iclass 29, count 0 2006.201.17:58:12.32#ibcon#*after write, iclass 29, count 0 2006.201.17:58:12.32#ibcon#*before return 0, iclass 29, count 0 2006.201.17:58:12.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:12.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.17:58:12.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.17:58:12.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.17:58:12.32$vck44/vbbw=wide 2006.201.17:58:12.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.17:58:12.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.17:58:12.32#ibcon#ireg 8 cls_cnt 0 2006.201.17:58:12.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:58:12.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:58:12.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:58:12.39#ibcon#enter wrdev, iclass 31, count 0 2006.201.17:58:12.39#ibcon#first serial, iclass 31, count 0 2006.201.17:58:12.39#ibcon#enter sib2, iclass 31, count 0 2006.201.17:58:12.39#ibcon#flushed, iclass 31, count 0 2006.201.17:58:12.39#ibcon#about to write, iclass 31, count 0 2006.201.17:58:12.39#ibcon#wrote, iclass 31, count 0 2006.201.17:58:12.39#ibcon#about to read 3, iclass 31, count 0 2006.201.17:58:12.41#ibcon#read 3, iclass 31, count 0 2006.201.17:58:12.41#ibcon#about to read 4, iclass 31, count 0 2006.201.17:58:12.41#ibcon#read 4, iclass 31, count 0 2006.201.17:58:12.41#ibcon#about to read 5, iclass 31, count 0 2006.201.17:58:12.41#ibcon#read 5, iclass 31, count 0 2006.201.17:58:12.41#ibcon#about to read 6, iclass 31, count 0 2006.201.17:58:12.41#ibcon#read 6, iclass 31, count 0 2006.201.17:58:12.41#ibcon#end of sib2, iclass 31, count 0 2006.201.17:58:12.41#ibcon#*mode == 0, iclass 31, count 0 2006.201.17:58:12.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.17:58:12.41#ibcon#[27=BW32\r\n] 2006.201.17:58:12.41#ibcon#*before write, iclass 31, count 0 2006.201.17:58:12.41#ibcon#enter sib2, iclass 31, count 0 2006.201.17:58:12.41#ibcon#flushed, iclass 31, count 0 2006.201.17:58:12.41#ibcon#about to write, iclass 31, count 0 2006.201.17:58:12.41#ibcon#wrote, iclass 31, count 0 2006.201.17:58:12.41#ibcon#about to read 3, iclass 31, count 0 2006.201.17:58:12.44#ibcon#read 3, iclass 31, count 0 2006.201.17:58:12.44#ibcon#about to read 4, iclass 31, count 0 2006.201.17:58:12.44#ibcon#read 4, iclass 31, count 0 2006.201.17:58:12.44#ibcon#about to read 5, iclass 31, count 0 2006.201.17:58:12.44#ibcon#read 5, iclass 31, count 0 2006.201.17:58:12.44#ibcon#about to read 6, iclass 31, count 0 2006.201.17:58:12.44#ibcon#read 6, iclass 31, count 0 2006.201.17:58:12.44#ibcon#end of sib2, iclass 31, count 0 2006.201.17:58:12.44#ibcon#*after write, iclass 31, count 0 2006.201.17:58:12.44#ibcon#*before return 0, iclass 31, count 0 2006.201.17:58:12.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:58:12.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.17:58:12.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.17:58:12.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.17:58:12.44$setupk4/ifdk4 2006.201.17:58:12.44$ifdk4/lo= 2006.201.17:58:12.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.17:58:12.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.17:58:12.44$ifdk4/patch= 2006.201.17:58:12.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.17:58:12.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.17:58:12.44$setupk4/!*+20s 2006.201.17:58:18.84#abcon#<5=/16 0.6 1.2 20.561001002.3\r\n> 2006.201.17:58:18.86#abcon#{5=INTERFACE CLEAR} 2006.201.17:58:18.93#abcon#[5=S1D000X0/0*\r\n] 2006.201.17:58:26.92$setupk4/"tpicd 2006.201.17:58:26.92$setupk4/echo=off 2006.201.17:58:26.92$setupk4/xlog=off 2006.201.17:58:26.92:!2006.201.17:59:21 2006.201.17:58:32.14#trakl#Source acquired 2006.201.17:58:32.14#flagr#flagr/antenna,acquired 2006.201.17:59:21.00:preob 2006.201.17:59:21.14/onsource/TRACKING 2006.201.17:59:21.14:!2006.201.17:59:31 2006.201.17:59:31.00:"tape 2006.201.17:59:31.00:"st=record 2006.201.17:59:31.00:data_valid=on 2006.201.17:59:31.00:midob 2006.201.17:59:32.14/onsource/TRACKING 2006.201.17:59:32.14/wx/20.56,1002.3,100 2006.201.17:59:32.21/cable/+6.4789E-03 2006.201.17:59:33.30/va/01,08,usb,yes,37,40 2006.201.17:59:33.30/va/02,07,usb,yes,40,41 2006.201.17:59:33.30/va/03,08,usb,yes,36,38 2006.201.17:59:33.30/va/04,07,usb,yes,41,43 2006.201.17:59:33.30/va/05,04,usb,yes,37,37 2006.201.17:59:33.30/va/06,05,usb,yes,37,37 2006.201.17:59:33.30/va/07,05,usb,yes,36,37 2006.201.17:59:33.30/va/08,04,usb,yes,36,42 2006.201.17:59:33.53/valo/01,524.99,yes,locked 2006.201.17:59:33.53/valo/02,534.99,yes,locked 2006.201.17:59:33.53/valo/03,564.99,yes,locked 2006.201.17:59:33.53/valo/04,624.99,yes,locked 2006.201.17:59:33.53/valo/05,734.99,yes,locked 2006.201.17:59:33.53/valo/06,814.99,yes,locked 2006.201.17:59:33.53/valo/07,864.99,yes,locked 2006.201.17:59:33.53/valo/08,884.99,yes,locked 2006.201.17:59:34.62/vb/01,04,usb,yes,29,27 2006.201.17:59:34.62/vb/02,05,usb,yes,28,27 2006.201.17:59:34.62/vb/03,04,usb,yes,28,31 2006.201.17:59:34.62/vb/04,05,usb,yes,29,28 2006.201.17:59:34.62/vb/05,04,usb,yes,25,28 2006.201.17:59:34.62/vb/06,04,usb,yes,30,26 2006.201.17:59:34.62/vb/07,04,usb,yes,29,29 2006.201.17:59:34.62/vb/08,04,usb,yes,27,30 2006.201.17:59:34.86/vblo/01,629.99,yes,locked 2006.201.17:59:34.86/vblo/02,634.99,yes,locked 2006.201.17:59:34.86/vblo/03,649.99,yes,locked 2006.201.17:59:34.86/vblo/04,679.99,yes,locked 2006.201.17:59:34.86/vblo/05,709.99,yes,locked 2006.201.17:59:34.86/vblo/06,719.99,yes,locked 2006.201.17:59:34.86/vblo/07,734.99,yes,locked 2006.201.17:59:34.86/vblo/08,744.99,yes,locked 2006.201.17:59:35.01/vabw/8 2006.201.17:59:35.16/vbbw/8 2006.201.17:59:35.25/xfe/off,on,14.7 2006.201.17:59:35.62/ifatt/23,28,28,28 2006.201.17:59:36.06/fmout-gps/S +4.59E-07 2006.201.17:59:36.13:!2006.201.18:01:31 2006.201.18:01:31.00:data_valid=off 2006.201.18:01:31.00:"et 2006.201.18:01:31.00:!+3s 2006.201.18:01:34.02:"tape 2006.201.18:01:34.02:postob 2006.201.18:01:34.20/cable/+6.4776E-03 2006.201.18:01:34.20/wx/20.54,1002.3,100 2006.201.18:01:34.27/fmout-gps/S +4.58E-07 2006.201.18:01:34.27:scan_name=201-1807,jd0607,60 2006.201.18:01:34.27:source=0552+398,055530.81,394849.2,2000.0,cw 2006.201.18:01:35.13#flagr#flagr/antenna,new-source 2006.201.18:01:35.13:checkk5 2006.201.18:01:35.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:01:35.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:01:36.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:01:36.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:01:37.02/chk_obsdata//k5ts1/T2011759??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.18:01:37.39/chk_obsdata//k5ts2/T2011759??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.18:01:37.76/chk_obsdata//k5ts3/T2011759??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.18:01:38.12/chk_obsdata//k5ts4/T2011759??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.18:01:38.81/k5log//k5ts1_log_newline 2006.201.18:01:39.49/k5log//k5ts2_log_newline 2006.201.18:01:40.18/k5log//k5ts3_log_newline 2006.201.18:01:40.87/k5log//k5ts4_log_newline 2006.201.18:01:40.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:01:40.89:setupk4=1 2006.201.18:01:40.89$setupk4/echo=on 2006.201.18:01:40.89$setupk4/pcalon 2006.201.18:01:40.89$pcalon/"no phase cal control is implemented here 2006.201.18:01:40.89$setupk4/"tpicd=stop 2006.201.18:01:40.89$setupk4/"rec=synch_on 2006.201.18:01:40.89$setupk4/"rec_mode=128 2006.201.18:01:40.89$setupk4/!* 2006.201.18:01:40.89$setupk4/recpk4 2006.201.18:01:40.89$recpk4/recpatch= 2006.201.18:01:40.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:01:40.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:01:40.90$setupk4/vck44 2006.201.18:01:40.90$vck44/valo=1,524.99 2006.201.18:01:40.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.18:01:40.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.18:01:40.90#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:40.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:40.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:40.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:40.90#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:01:40.90#ibcon#first serial, iclass 6, count 0 2006.201.18:01:40.90#ibcon#enter sib2, iclass 6, count 0 2006.201.18:01:40.90#ibcon#flushed, iclass 6, count 0 2006.201.18:01:40.90#ibcon#about to write, iclass 6, count 0 2006.201.18:01:40.90#ibcon#wrote, iclass 6, count 0 2006.201.18:01:40.90#ibcon#about to read 3, iclass 6, count 0 2006.201.18:01:40.93#ibcon#read 3, iclass 6, count 0 2006.201.18:01:40.93#ibcon#about to read 4, iclass 6, count 0 2006.201.18:01:40.93#ibcon#read 4, iclass 6, count 0 2006.201.18:01:40.93#ibcon#about to read 5, iclass 6, count 0 2006.201.18:01:40.93#ibcon#read 5, iclass 6, count 0 2006.201.18:01:40.93#ibcon#about to read 6, iclass 6, count 0 2006.201.18:01:40.93#ibcon#read 6, iclass 6, count 0 2006.201.18:01:40.93#ibcon#end of sib2, iclass 6, count 0 2006.201.18:01:40.93#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:01:40.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:01:40.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:01:40.93#ibcon#*before write, iclass 6, count 0 2006.201.18:01:40.93#ibcon#enter sib2, iclass 6, count 0 2006.201.18:01:40.93#ibcon#flushed, iclass 6, count 0 2006.201.18:01:40.93#ibcon#about to write, iclass 6, count 0 2006.201.18:01:40.93#ibcon#wrote, iclass 6, count 0 2006.201.18:01:40.93#ibcon#about to read 3, iclass 6, count 0 2006.201.18:01:40.99#ibcon#read 3, iclass 6, count 0 2006.201.18:01:40.99#ibcon#about to read 4, iclass 6, count 0 2006.201.18:01:40.99#ibcon#read 4, iclass 6, count 0 2006.201.18:01:40.99#ibcon#about to read 5, iclass 6, count 0 2006.201.18:01:40.99#ibcon#read 5, iclass 6, count 0 2006.201.18:01:40.99#ibcon#about to read 6, iclass 6, count 0 2006.201.18:01:40.99#ibcon#read 6, iclass 6, count 0 2006.201.18:01:40.99#ibcon#end of sib2, iclass 6, count 0 2006.201.18:01:40.99#ibcon#*after write, iclass 6, count 0 2006.201.18:01:40.99#ibcon#*before return 0, iclass 6, count 0 2006.201.18:01:40.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:40.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:40.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:01:40.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:01:40.99$vck44/va=1,8 2006.201.18:01:40.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.18:01:40.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.18:01:40.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:40.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:40.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:40.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:40.99#ibcon#enter wrdev, iclass 10, count 2 2006.201.18:01:40.99#ibcon#first serial, iclass 10, count 2 2006.201.18:01:40.99#ibcon#enter sib2, iclass 10, count 2 2006.201.18:01:40.99#ibcon#flushed, iclass 10, count 2 2006.201.18:01:40.99#ibcon#about to write, iclass 10, count 2 2006.201.18:01:40.99#ibcon#wrote, iclass 10, count 2 2006.201.18:01:40.99#ibcon#about to read 3, iclass 10, count 2 2006.201.18:01:41.01#ibcon#read 3, iclass 10, count 2 2006.201.18:01:41.01#ibcon#about to read 4, iclass 10, count 2 2006.201.18:01:41.01#ibcon#read 4, iclass 10, count 2 2006.201.18:01:41.01#ibcon#about to read 5, iclass 10, count 2 2006.201.18:01:41.01#ibcon#read 5, iclass 10, count 2 2006.201.18:01:41.01#ibcon#about to read 6, iclass 10, count 2 2006.201.18:01:41.01#ibcon#read 6, iclass 10, count 2 2006.201.18:01:41.01#ibcon#end of sib2, iclass 10, count 2 2006.201.18:01:41.01#ibcon#*mode == 0, iclass 10, count 2 2006.201.18:01:41.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.18:01:41.01#ibcon#[25=AT01-08\r\n] 2006.201.18:01:41.01#ibcon#*before write, iclass 10, count 2 2006.201.18:01:41.01#ibcon#enter sib2, iclass 10, count 2 2006.201.18:01:41.01#ibcon#flushed, iclass 10, count 2 2006.201.18:01:41.01#ibcon#about to write, iclass 10, count 2 2006.201.18:01:41.01#ibcon#wrote, iclass 10, count 2 2006.201.18:01:41.01#ibcon#about to read 3, iclass 10, count 2 2006.201.18:01:41.05#ibcon#read 3, iclass 10, count 2 2006.201.18:01:41.05#ibcon#about to read 4, iclass 10, count 2 2006.201.18:01:41.05#ibcon#read 4, iclass 10, count 2 2006.201.18:01:41.05#ibcon#about to read 5, iclass 10, count 2 2006.201.18:01:41.05#ibcon#read 5, iclass 10, count 2 2006.201.18:01:41.05#ibcon#about to read 6, iclass 10, count 2 2006.201.18:01:41.05#ibcon#read 6, iclass 10, count 2 2006.201.18:01:41.05#ibcon#end of sib2, iclass 10, count 2 2006.201.18:01:41.05#ibcon#*after write, iclass 10, count 2 2006.201.18:01:41.05#ibcon#*before return 0, iclass 10, count 2 2006.201.18:01:41.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:41.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:41.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.18:01:41.05#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:41.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:41.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:41.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:41.17#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:01:41.17#ibcon#first serial, iclass 10, count 0 2006.201.18:01:41.17#ibcon#enter sib2, iclass 10, count 0 2006.201.18:01:41.17#ibcon#flushed, iclass 10, count 0 2006.201.18:01:41.17#ibcon#about to write, iclass 10, count 0 2006.201.18:01:41.17#ibcon#wrote, iclass 10, count 0 2006.201.18:01:41.17#ibcon#about to read 3, iclass 10, count 0 2006.201.18:01:41.20#ibcon#read 3, iclass 10, count 0 2006.201.18:01:41.20#ibcon#about to read 4, iclass 10, count 0 2006.201.18:01:41.20#ibcon#read 4, iclass 10, count 0 2006.201.18:01:41.20#ibcon#about to read 5, iclass 10, count 0 2006.201.18:01:41.20#ibcon#read 5, iclass 10, count 0 2006.201.18:01:41.20#ibcon#about to read 6, iclass 10, count 0 2006.201.18:01:41.20#ibcon#read 6, iclass 10, count 0 2006.201.18:01:41.20#ibcon#end of sib2, iclass 10, count 0 2006.201.18:01:41.20#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:01:41.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:01:41.20#ibcon#[25=USB\r\n] 2006.201.18:01:41.20#ibcon#*before write, iclass 10, count 0 2006.201.18:01:41.20#ibcon#enter sib2, iclass 10, count 0 2006.201.18:01:41.20#ibcon#flushed, iclass 10, count 0 2006.201.18:01:41.20#ibcon#about to write, iclass 10, count 0 2006.201.18:01:41.20#ibcon#wrote, iclass 10, count 0 2006.201.18:01:41.20#ibcon#about to read 3, iclass 10, count 0 2006.201.18:01:41.23#ibcon#read 3, iclass 10, count 0 2006.201.18:01:41.23#ibcon#about to read 4, iclass 10, count 0 2006.201.18:01:41.23#ibcon#read 4, iclass 10, count 0 2006.201.18:01:41.23#ibcon#about to read 5, iclass 10, count 0 2006.201.18:01:41.23#ibcon#read 5, iclass 10, count 0 2006.201.18:01:41.23#ibcon#about to read 6, iclass 10, count 0 2006.201.18:01:41.23#ibcon#read 6, iclass 10, count 0 2006.201.18:01:41.23#ibcon#end of sib2, iclass 10, count 0 2006.201.18:01:41.23#ibcon#*after write, iclass 10, count 0 2006.201.18:01:41.23#ibcon#*before return 0, iclass 10, count 0 2006.201.18:01:41.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:41.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:41.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:01:41.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:01:41.23$vck44/valo=2,534.99 2006.201.18:01:41.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.18:01:41.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.18:01:41.23#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:41.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:41.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:41.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:41.23#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:01:41.23#ibcon#first serial, iclass 12, count 0 2006.201.18:01:41.23#ibcon#enter sib2, iclass 12, count 0 2006.201.18:01:41.23#ibcon#flushed, iclass 12, count 0 2006.201.18:01:41.23#ibcon#about to write, iclass 12, count 0 2006.201.18:01:41.23#ibcon#wrote, iclass 12, count 0 2006.201.18:01:41.23#ibcon#about to read 3, iclass 12, count 0 2006.201.18:01:41.25#ibcon#read 3, iclass 12, count 0 2006.201.18:01:41.25#ibcon#about to read 4, iclass 12, count 0 2006.201.18:01:41.25#ibcon#read 4, iclass 12, count 0 2006.201.18:01:41.25#ibcon#about to read 5, iclass 12, count 0 2006.201.18:01:41.25#ibcon#read 5, iclass 12, count 0 2006.201.18:01:41.25#ibcon#about to read 6, iclass 12, count 0 2006.201.18:01:41.25#ibcon#read 6, iclass 12, count 0 2006.201.18:01:41.25#ibcon#end of sib2, iclass 12, count 0 2006.201.18:01:41.25#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:01:41.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:01:41.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:01:41.25#ibcon#*before write, iclass 12, count 0 2006.201.18:01:41.25#ibcon#enter sib2, iclass 12, count 0 2006.201.18:01:41.25#ibcon#flushed, iclass 12, count 0 2006.201.18:01:41.25#ibcon#about to write, iclass 12, count 0 2006.201.18:01:41.25#ibcon#wrote, iclass 12, count 0 2006.201.18:01:41.25#ibcon#about to read 3, iclass 12, count 0 2006.201.18:01:41.29#ibcon#read 3, iclass 12, count 0 2006.201.18:01:41.29#ibcon#about to read 4, iclass 12, count 0 2006.201.18:01:41.29#ibcon#read 4, iclass 12, count 0 2006.201.18:01:41.29#ibcon#about to read 5, iclass 12, count 0 2006.201.18:01:41.29#ibcon#read 5, iclass 12, count 0 2006.201.18:01:41.29#ibcon#about to read 6, iclass 12, count 0 2006.201.18:01:41.29#ibcon#read 6, iclass 12, count 0 2006.201.18:01:41.29#ibcon#end of sib2, iclass 12, count 0 2006.201.18:01:41.29#ibcon#*after write, iclass 12, count 0 2006.201.18:01:41.29#ibcon#*before return 0, iclass 12, count 0 2006.201.18:01:41.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:41.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:41.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:01:41.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:01:41.29$vck44/va=2,7 2006.201.18:01:41.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.18:01:41.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.18:01:41.29#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:41.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:41.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:41.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:41.35#ibcon#enter wrdev, iclass 14, count 2 2006.201.18:01:41.35#ibcon#first serial, iclass 14, count 2 2006.201.18:01:41.35#ibcon#enter sib2, iclass 14, count 2 2006.201.18:01:41.35#ibcon#flushed, iclass 14, count 2 2006.201.18:01:41.35#ibcon#about to write, iclass 14, count 2 2006.201.18:01:41.35#ibcon#wrote, iclass 14, count 2 2006.201.18:01:41.35#ibcon#about to read 3, iclass 14, count 2 2006.201.18:01:41.37#ibcon#read 3, iclass 14, count 2 2006.201.18:01:41.37#ibcon#about to read 4, iclass 14, count 2 2006.201.18:01:41.37#ibcon#read 4, iclass 14, count 2 2006.201.18:01:41.37#ibcon#about to read 5, iclass 14, count 2 2006.201.18:01:41.37#ibcon#read 5, iclass 14, count 2 2006.201.18:01:41.37#ibcon#about to read 6, iclass 14, count 2 2006.201.18:01:41.37#ibcon#read 6, iclass 14, count 2 2006.201.18:01:41.37#ibcon#end of sib2, iclass 14, count 2 2006.201.18:01:41.37#ibcon#*mode == 0, iclass 14, count 2 2006.201.18:01:41.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.18:01:41.37#ibcon#[25=AT02-07\r\n] 2006.201.18:01:41.37#ibcon#*before write, iclass 14, count 2 2006.201.18:01:41.37#ibcon#enter sib2, iclass 14, count 2 2006.201.18:01:41.37#ibcon#flushed, iclass 14, count 2 2006.201.18:01:41.37#ibcon#about to write, iclass 14, count 2 2006.201.18:01:41.37#ibcon#wrote, iclass 14, count 2 2006.201.18:01:41.37#ibcon#about to read 3, iclass 14, count 2 2006.201.18:01:41.41#ibcon#read 3, iclass 14, count 2 2006.201.18:01:41.41#ibcon#about to read 4, iclass 14, count 2 2006.201.18:01:41.41#ibcon#read 4, iclass 14, count 2 2006.201.18:01:41.41#ibcon#about to read 5, iclass 14, count 2 2006.201.18:01:41.41#ibcon#read 5, iclass 14, count 2 2006.201.18:01:41.41#ibcon#about to read 6, iclass 14, count 2 2006.201.18:01:41.41#ibcon#read 6, iclass 14, count 2 2006.201.18:01:41.41#ibcon#end of sib2, iclass 14, count 2 2006.201.18:01:41.41#ibcon#*after write, iclass 14, count 2 2006.201.18:01:41.41#ibcon#*before return 0, iclass 14, count 2 2006.201.18:01:41.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:41.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:41.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.18:01:41.41#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:41.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:41.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:41.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:41.53#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:01:41.53#ibcon#first serial, iclass 14, count 0 2006.201.18:01:41.53#ibcon#enter sib2, iclass 14, count 0 2006.201.18:01:41.53#ibcon#flushed, iclass 14, count 0 2006.201.18:01:41.53#ibcon#about to write, iclass 14, count 0 2006.201.18:01:41.53#ibcon#wrote, iclass 14, count 0 2006.201.18:01:41.53#ibcon#about to read 3, iclass 14, count 0 2006.201.18:01:41.55#ibcon#read 3, iclass 14, count 0 2006.201.18:01:41.55#ibcon#about to read 4, iclass 14, count 0 2006.201.18:01:41.55#ibcon#read 4, iclass 14, count 0 2006.201.18:01:41.55#ibcon#about to read 5, iclass 14, count 0 2006.201.18:01:41.55#ibcon#read 5, iclass 14, count 0 2006.201.18:01:41.55#ibcon#about to read 6, iclass 14, count 0 2006.201.18:01:41.55#ibcon#read 6, iclass 14, count 0 2006.201.18:01:41.55#ibcon#end of sib2, iclass 14, count 0 2006.201.18:01:41.55#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:01:41.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:01:41.55#ibcon#[25=USB\r\n] 2006.201.18:01:41.55#ibcon#*before write, iclass 14, count 0 2006.201.18:01:41.55#ibcon#enter sib2, iclass 14, count 0 2006.201.18:01:41.55#ibcon#flushed, iclass 14, count 0 2006.201.18:01:41.55#ibcon#about to write, iclass 14, count 0 2006.201.18:01:41.55#ibcon#wrote, iclass 14, count 0 2006.201.18:01:41.55#ibcon#about to read 3, iclass 14, count 0 2006.201.18:01:41.58#ibcon#read 3, iclass 14, count 0 2006.201.18:01:41.58#ibcon#about to read 4, iclass 14, count 0 2006.201.18:01:41.58#ibcon#read 4, iclass 14, count 0 2006.201.18:01:41.58#ibcon#about to read 5, iclass 14, count 0 2006.201.18:01:41.58#ibcon#read 5, iclass 14, count 0 2006.201.18:01:41.58#ibcon#about to read 6, iclass 14, count 0 2006.201.18:01:41.58#ibcon#read 6, iclass 14, count 0 2006.201.18:01:41.58#ibcon#end of sib2, iclass 14, count 0 2006.201.18:01:41.58#ibcon#*after write, iclass 14, count 0 2006.201.18:01:41.58#ibcon#*before return 0, iclass 14, count 0 2006.201.18:01:41.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:41.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:41.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:01:41.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:01:41.58$vck44/valo=3,564.99 2006.201.18:01:41.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.18:01:41.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.18:01:41.58#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:41.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:41.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:41.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:41.58#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:01:41.58#ibcon#first serial, iclass 16, count 0 2006.201.18:01:41.58#ibcon#enter sib2, iclass 16, count 0 2006.201.18:01:41.58#ibcon#flushed, iclass 16, count 0 2006.201.18:01:41.58#ibcon#about to write, iclass 16, count 0 2006.201.18:01:41.58#ibcon#wrote, iclass 16, count 0 2006.201.18:01:41.58#ibcon#about to read 3, iclass 16, count 0 2006.201.18:01:41.60#ibcon#read 3, iclass 16, count 0 2006.201.18:01:41.60#ibcon#about to read 4, iclass 16, count 0 2006.201.18:01:41.60#ibcon#read 4, iclass 16, count 0 2006.201.18:01:41.60#ibcon#about to read 5, iclass 16, count 0 2006.201.18:01:41.60#ibcon#read 5, iclass 16, count 0 2006.201.18:01:41.60#ibcon#about to read 6, iclass 16, count 0 2006.201.18:01:41.60#ibcon#read 6, iclass 16, count 0 2006.201.18:01:41.60#ibcon#end of sib2, iclass 16, count 0 2006.201.18:01:41.60#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:01:41.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:01:41.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:01:41.60#ibcon#*before write, iclass 16, count 0 2006.201.18:01:41.60#ibcon#enter sib2, iclass 16, count 0 2006.201.18:01:41.60#ibcon#flushed, iclass 16, count 0 2006.201.18:01:41.60#ibcon#about to write, iclass 16, count 0 2006.201.18:01:41.60#ibcon#wrote, iclass 16, count 0 2006.201.18:01:41.60#ibcon#about to read 3, iclass 16, count 0 2006.201.18:01:41.65#ibcon#read 3, iclass 16, count 0 2006.201.18:01:41.65#ibcon#about to read 4, iclass 16, count 0 2006.201.18:01:41.65#ibcon#read 4, iclass 16, count 0 2006.201.18:01:41.65#ibcon#about to read 5, iclass 16, count 0 2006.201.18:01:41.65#ibcon#read 5, iclass 16, count 0 2006.201.18:01:41.65#ibcon#about to read 6, iclass 16, count 0 2006.201.18:01:41.65#ibcon#read 6, iclass 16, count 0 2006.201.18:01:41.65#ibcon#end of sib2, iclass 16, count 0 2006.201.18:01:41.65#ibcon#*after write, iclass 16, count 0 2006.201.18:01:41.65#ibcon#*before return 0, iclass 16, count 0 2006.201.18:01:41.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:41.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:41.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:01:41.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:01:41.65$vck44/va=3,8 2006.201.18:01:41.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.18:01:41.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.18:01:41.65#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:41.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:41.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:41.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:41.70#ibcon#enter wrdev, iclass 18, count 2 2006.201.18:01:41.70#ibcon#first serial, iclass 18, count 2 2006.201.18:01:41.70#ibcon#enter sib2, iclass 18, count 2 2006.201.18:01:41.70#ibcon#flushed, iclass 18, count 2 2006.201.18:01:41.70#ibcon#about to write, iclass 18, count 2 2006.201.18:01:41.70#ibcon#wrote, iclass 18, count 2 2006.201.18:01:41.70#ibcon#about to read 3, iclass 18, count 2 2006.201.18:01:41.72#ibcon#read 3, iclass 18, count 2 2006.201.18:01:41.72#ibcon#about to read 4, iclass 18, count 2 2006.201.18:01:41.72#ibcon#read 4, iclass 18, count 2 2006.201.18:01:41.72#ibcon#about to read 5, iclass 18, count 2 2006.201.18:01:41.72#ibcon#read 5, iclass 18, count 2 2006.201.18:01:41.72#ibcon#about to read 6, iclass 18, count 2 2006.201.18:01:41.72#ibcon#read 6, iclass 18, count 2 2006.201.18:01:41.72#ibcon#end of sib2, iclass 18, count 2 2006.201.18:01:41.72#ibcon#*mode == 0, iclass 18, count 2 2006.201.18:01:41.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.18:01:41.72#ibcon#[25=AT03-08\r\n] 2006.201.18:01:41.72#ibcon#*before write, iclass 18, count 2 2006.201.18:01:41.72#ibcon#enter sib2, iclass 18, count 2 2006.201.18:01:41.72#ibcon#flushed, iclass 18, count 2 2006.201.18:01:41.72#ibcon#about to write, iclass 18, count 2 2006.201.18:01:41.72#ibcon#wrote, iclass 18, count 2 2006.201.18:01:41.72#ibcon#about to read 3, iclass 18, count 2 2006.201.18:01:41.75#ibcon#read 3, iclass 18, count 2 2006.201.18:01:41.75#ibcon#about to read 4, iclass 18, count 2 2006.201.18:01:41.75#ibcon#read 4, iclass 18, count 2 2006.201.18:01:41.75#ibcon#about to read 5, iclass 18, count 2 2006.201.18:01:41.75#ibcon#read 5, iclass 18, count 2 2006.201.18:01:41.75#ibcon#about to read 6, iclass 18, count 2 2006.201.18:01:41.75#ibcon#read 6, iclass 18, count 2 2006.201.18:01:41.75#ibcon#end of sib2, iclass 18, count 2 2006.201.18:01:41.75#ibcon#*after write, iclass 18, count 2 2006.201.18:01:41.75#ibcon#*before return 0, iclass 18, count 2 2006.201.18:01:41.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:41.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:41.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.18:01:41.75#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:41.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:41.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:41.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:41.87#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:01:41.87#ibcon#first serial, iclass 18, count 0 2006.201.18:01:41.87#ibcon#enter sib2, iclass 18, count 0 2006.201.18:01:41.87#ibcon#flushed, iclass 18, count 0 2006.201.18:01:41.87#ibcon#about to write, iclass 18, count 0 2006.201.18:01:41.87#ibcon#wrote, iclass 18, count 0 2006.201.18:01:41.87#ibcon#about to read 3, iclass 18, count 0 2006.201.18:01:41.89#ibcon#read 3, iclass 18, count 0 2006.201.18:01:41.89#ibcon#about to read 4, iclass 18, count 0 2006.201.18:01:41.89#ibcon#read 4, iclass 18, count 0 2006.201.18:01:41.89#ibcon#about to read 5, iclass 18, count 0 2006.201.18:01:41.89#ibcon#read 5, iclass 18, count 0 2006.201.18:01:41.89#ibcon#about to read 6, iclass 18, count 0 2006.201.18:01:41.89#ibcon#read 6, iclass 18, count 0 2006.201.18:01:41.89#ibcon#end of sib2, iclass 18, count 0 2006.201.18:01:41.89#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:01:41.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:01:41.89#ibcon#[25=USB\r\n] 2006.201.18:01:41.89#ibcon#*before write, iclass 18, count 0 2006.201.18:01:41.89#ibcon#enter sib2, iclass 18, count 0 2006.201.18:01:41.89#ibcon#flushed, iclass 18, count 0 2006.201.18:01:41.89#ibcon#about to write, iclass 18, count 0 2006.201.18:01:41.89#ibcon#wrote, iclass 18, count 0 2006.201.18:01:41.89#ibcon#about to read 3, iclass 18, count 0 2006.201.18:01:41.92#ibcon#read 3, iclass 18, count 0 2006.201.18:01:41.92#ibcon#about to read 4, iclass 18, count 0 2006.201.18:01:41.92#ibcon#read 4, iclass 18, count 0 2006.201.18:01:41.92#ibcon#about to read 5, iclass 18, count 0 2006.201.18:01:41.92#ibcon#read 5, iclass 18, count 0 2006.201.18:01:41.92#ibcon#about to read 6, iclass 18, count 0 2006.201.18:01:41.92#ibcon#read 6, iclass 18, count 0 2006.201.18:01:41.92#ibcon#end of sib2, iclass 18, count 0 2006.201.18:01:41.92#ibcon#*after write, iclass 18, count 0 2006.201.18:01:41.92#ibcon#*before return 0, iclass 18, count 0 2006.201.18:01:41.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:41.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:41.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:01:41.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:01:41.92$vck44/valo=4,624.99 2006.201.18:01:41.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.18:01:41.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.18:01:41.92#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:41.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:41.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:41.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:41.92#ibcon#enter wrdev, iclass 20, count 0 2006.201.18:01:41.92#ibcon#first serial, iclass 20, count 0 2006.201.18:01:41.92#ibcon#enter sib2, iclass 20, count 0 2006.201.18:01:41.92#ibcon#flushed, iclass 20, count 0 2006.201.18:01:41.92#ibcon#about to write, iclass 20, count 0 2006.201.18:01:41.92#ibcon#wrote, iclass 20, count 0 2006.201.18:01:41.92#ibcon#about to read 3, iclass 20, count 0 2006.201.18:01:41.94#ibcon#read 3, iclass 20, count 0 2006.201.18:01:41.94#ibcon#about to read 4, iclass 20, count 0 2006.201.18:01:41.94#ibcon#read 4, iclass 20, count 0 2006.201.18:01:41.94#ibcon#about to read 5, iclass 20, count 0 2006.201.18:01:41.94#ibcon#read 5, iclass 20, count 0 2006.201.18:01:41.94#ibcon#about to read 6, iclass 20, count 0 2006.201.18:01:41.94#ibcon#read 6, iclass 20, count 0 2006.201.18:01:41.94#ibcon#end of sib2, iclass 20, count 0 2006.201.18:01:41.94#ibcon#*mode == 0, iclass 20, count 0 2006.201.18:01:41.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.18:01:41.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:01:41.94#ibcon#*before write, iclass 20, count 0 2006.201.18:01:41.94#ibcon#enter sib2, iclass 20, count 0 2006.201.18:01:41.94#ibcon#flushed, iclass 20, count 0 2006.201.18:01:41.94#ibcon#about to write, iclass 20, count 0 2006.201.18:01:41.94#ibcon#wrote, iclass 20, count 0 2006.201.18:01:41.94#ibcon#about to read 3, iclass 20, count 0 2006.201.18:01:41.99#ibcon#read 3, iclass 20, count 0 2006.201.18:01:41.99#ibcon#about to read 4, iclass 20, count 0 2006.201.18:01:41.99#ibcon#read 4, iclass 20, count 0 2006.201.18:01:41.99#ibcon#about to read 5, iclass 20, count 0 2006.201.18:01:41.99#ibcon#read 5, iclass 20, count 0 2006.201.18:01:41.99#ibcon#about to read 6, iclass 20, count 0 2006.201.18:01:41.99#ibcon#read 6, iclass 20, count 0 2006.201.18:01:41.99#ibcon#end of sib2, iclass 20, count 0 2006.201.18:01:41.99#ibcon#*after write, iclass 20, count 0 2006.201.18:01:41.99#ibcon#*before return 0, iclass 20, count 0 2006.201.18:01:41.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:41.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:41.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.18:01:41.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.18:01:41.99$vck44/va=4,7 2006.201.18:01:41.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.18:01:41.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.18:01:41.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:41.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:42.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:42.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:42.04#ibcon#enter wrdev, iclass 22, count 2 2006.201.18:01:42.04#ibcon#first serial, iclass 22, count 2 2006.201.18:01:42.04#ibcon#enter sib2, iclass 22, count 2 2006.201.18:01:42.04#ibcon#flushed, iclass 22, count 2 2006.201.18:01:42.04#ibcon#about to write, iclass 22, count 2 2006.201.18:01:42.04#ibcon#wrote, iclass 22, count 2 2006.201.18:01:42.04#ibcon#about to read 3, iclass 22, count 2 2006.201.18:01:42.06#ibcon#read 3, iclass 22, count 2 2006.201.18:01:42.06#ibcon#about to read 4, iclass 22, count 2 2006.201.18:01:42.06#ibcon#read 4, iclass 22, count 2 2006.201.18:01:42.06#ibcon#about to read 5, iclass 22, count 2 2006.201.18:01:42.06#ibcon#read 5, iclass 22, count 2 2006.201.18:01:42.06#ibcon#about to read 6, iclass 22, count 2 2006.201.18:01:42.06#ibcon#read 6, iclass 22, count 2 2006.201.18:01:42.06#ibcon#end of sib2, iclass 22, count 2 2006.201.18:01:42.06#ibcon#*mode == 0, iclass 22, count 2 2006.201.18:01:42.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.18:01:42.06#ibcon#[25=AT04-07\r\n] 2006.201.18:01:42.06#ibcon#*before write, iclass 22, count 2 2006.201.18:01:42.06#ibcon#enter sib2, iclass 22, count 2 2006.201.18:01:42.06#ibcon#flushed, iclass 22, count 2 2006.201.18:01:42.06#ibcon#about to write, iclass 22, count 2 2006.201.18:01:42.06#ibcon#wrote, iclass 22, count 2 2006.201.18:01:42.06#ibcon#about to read 3, iclass 22, count 2 2006.201.18:01:42.09#ibcon#read 3, iclass 22, count 2 2006.201.18:01:42.09#ibcon#about to read 4, iclass 22, count 2 2006.201.18:01:42.09#ibcon#read 4, iclass 22, count 2 2006.201.18:01:42.09#ibcon#about to read 5, iclass 22, count 2 2006.201.18:01:42.09#ibcon#read 5, iclass 22, count 2 2006.201.18:01:42.09#ibcon#about to read 6, iclass 22, count 2 2006.201.18:01:42.09#ibcon#read 6, iclass 22, count 2 2006.201.18:01:42.09#ibcon#end of sib2, iclass 22, count 2 2006.201.18:01:42.09#ibcon#*after write, iclass 22, count 2 2006.201.18:01:42.09#ibcon#*before return 0, iclass 22, count 2 2006.201.18:01:42.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:42.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:42.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.18:01:42.09#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:42.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:42.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:42.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:42.21#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:01:42.21#ibcon#first serial, iclass 22, count 0 2006.201.18:01:42.21#ibcon#enter sib2, iclass 22, count 0 2006.201.18:01:42.21#ibcon#flushed, iclass 22, count 0 2006.201.18:01:42.21#ibcon#about to write, iclass 22, count 0 2006.201.18:01:42.21#ibcon#wrote, iclass 22, count 0 2006.201.18:01:42.21#ibcon#about to read 3, iclass 22, count 0 2006.201.18:01:42.23#ibcon#read 3, iclass 22, count 0 2006.201.18:01:42.23#ibcon#about to read 4, iclass 22, count 0 2006.201.18:01:42.23#ibcon#read 4, iclass 22, count 0 2006.201.18:01:42.23#ibcon#about to read 5, iclass 22, count 0 2006.201.18:01:42.23#ibcon#read 5, iclass 22, count 0 2006.201.18:01:42.23#ibcon#about to read 6, iclass 22, count 0 2006.201.18:01:42.23#ibcon#read 6, iclass 22, count 0 2006.201.18:01:42.23#ibcon#end of sib2, iclass 22, count 0 2006.201.18:01:42.23#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:01:42.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:01:42.23#ibcon#[25=USB\r\n] 2006.201.18:01:42.23#ibcon#*before write, iclass 22, count 0 2006.201.18:01:42.23#ibcon#enter sib2, iclass 22, count 0 2006.201.18:01:42.23#ibcon#flushed, iclass 22, count 0 2006.201.18:01:42.23#ibcon#about to write, iclass 22, count 0 2006.201.18:01:42.23#ibcon#wrote, iclass 22, count 0 2006.201.18:01:42.23#ibcon#about to read 3, iclass 22, count 0 2006.201.18:01:42.25#abcon#<5=/16 0.6 1.1 20.541001002.2\r\n> 2006.201.18:01:42.26#ibcon#read 3, iclass 22, count 0 2006.201.18:01:42.26#ibcon#about to read 4, iclass 22, count 0 2006.201.18:01:42.26#ibcon#read 4, iclass 22, count 0 2006.201.18:01:42.26#ibcon#about to read 5, iclass 22, count 0 2006.201.18:01:42.26#ibcon#read 5, iclass 22, count 0 2006.201.18:01:42.26#ibcon#about to read 6, iclass 22, count 0 2006.201.18:01:42.26#ibcon#read 6, iclass 22, count 0 2006.201.18:01:42.26#ibcon#end of sib2, iclass 22, count 0 2006.201.18:01:42.26#ibcon#*after write, iclass 22, count 0 2006.201.18:01:42.26#ibcon#*before return 0, iclass 22, count 0 2006.201.18:01:42.26#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:42.26#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:42.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:01:42.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:01:42.26$vck44/valo=5,734.99 2006.201.18:01:42.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.18:01:42.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.18:01:42.26#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:42.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:01:42.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:01:42.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:01:42.26#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:01:42.26#ibcon#first serial, iclass 27, count 0 2006.201.18:01:42.26#ibcon#enter sib2, iclass 27, count 0 2006.201.18:01:42.26#ibcon#flushed, iclass 27, count 0 2006.201.18:01:42.26#ibcon#about to write, iclass 27, count 0 2006.201.18:01:42.26#ibcon#wrote, iclass 27, count 0 2006.201.18:01:42.26#ibcon#about to read 3, iclass 27, count 0 2006.201.18:01:42.27#abcon#{5=INTERFACE CLEAR} 2006.201.18:01:42.28#ibcon#read 3, iclass 27, count 0 2006.201.18:01:42.28#ibcon#about to read 4, iclass 27, count 0 2006.201.18:01:42.28#ibcon#read 4, iclass 27, count 0 2006.201.18:01:42.28#ibcon#about to read 5, iclass 27, count 0 2006.201.18:01:42.28#ibcon#read 5, iclass 27, count 0 2006.201.18:01:42.28#ibcon#about to read 6, iclass 27, count 0 2006.201.18:01:42.28#ibcon#read 6, iclass 27, count 0 2006.201.18:01:42.28#ibcon#end of sib2, iclass 27, count 0 2006.201.18:01:42.28#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:01:42.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:01:42.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:01:42.28#ibcon#*before write, iclass 27, count 0 2006.201.18:01:42.28#ibcon#enter sib2, iclass 27, count 0 2006.201.18:01:42.28#ibcon#flushed, iclass 27, count 0 2006.201.18:01:42.28#ibcon#about to write, iclass 27, count 0 2006.201.18:01:42.28#ibcon#wrote, iclass 27, count 0 2006.201.18:01:42.28#ibcon#about to read 3, iclass 27, count 0 2006.201.18:01:42.32#ibcon#read 3, iclass 27, count 0 2006.201.18:01:42.32#ibcon#about to read 4, iclass 27, count 0 2006.201.18:01:42.32#ibcon#read 4, iclass 27, count 0 2006.201.18:01:42.32#ibcon#about to read 5, iclass 27, count 0 2006.201.18:01:42.32#ibcon#read 5, iclass 27, count 0 2006.201.18:01:42.32#ibcon#about to read 6, iclass 27, count 0 2006.201.18:01:42.32#ibcon#read 6, iclass 27, count 0 2006.201.18:01:42.32#ibcon#end of sib2, iclass 27, count 0 2006.201.18:01:42.32#ibcon#*after write, iclass 27, count 0 2006.201.18:01:42.32#ibcon#*before return 0, iclass 27, count 0 2006.201.18:01:42.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:01:42.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:01:42.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:01:42.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:01:42.32$vck44/va=5,4 2006.201.18:01:42.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.18:01:42.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.18:01:42.32#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:42.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:42.33#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:01:42.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:42.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:42.38#ibcon#enter wrdev, iclass 30, count 2 2006.201.18:01:42.38#ibcon#first serial, iclass 30, count 2 2006.201.18:01:42.38#ibcon#enter sib2, iclass 30, count 2 2006.201.18:01:42.38#ibcon#flushed, iclass 30, count 2 2006.201.18:01:42.38#ibcon#about to write, iclass 30, count 2 2006.201.18:01:42.38#ibcon#wrote, iclass 30, count 2 2006.201.18:01:42.38#ibcon#about to read 3, iclass 30, count 2 2006.201.18:01:42.40#ibcon#read 3, iclass 30, count 2 2006.201.18:01:42.40#ibcon#about to read 4, iclass 30, count 2 2006.201.18:01:42.40#ibcon#read 4, iclass 30, count 2 2006.201.18:01:42.40#ibcon#about to read 5, iclass 30, count 2 2006.201.18:01:42.40#ibcon#read 5, iclass 30, count 2 2006.201.18:01:42.40#ibcon#about to read 6, iclass 30, count 2 2006.201.18:01:42.40#ibcon#read 6, iclass 30, count 2 2006.201.18:01:42.40#ibcon#end of sib2, iclass 30, count 2 2006.201.18:01:42.40#ibcon#*mode == 0, iclass 30, count 2 2006.201.18:01:42.40#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.18:01:42.40#ibcon#[25=AT05-04\r\n] 2006.201.18:01:42.40#ibcon#*before write, iclass 30, count 2 2006.201.18:01:42.40#ibcon#enter sib2, iclass 30, count 2 2006.201.18:01:42.40#ibcon#flushed, iclass 30, count 2 2006.201.18:01:42.40#ibcon#about to write, iclass 30, count 2 2006.201.18:01:42.40#ibcon#wrote, iclass 30, count 2 2006.201.18:01:42.40#ibcon#about to read 3, iclass 30, count 2 2006.201.18:01:42.43#ibcon#read 3, iclass 30, count 2 2006.201.18:01:42.43#ibcon#about to read 4, iclass 30, count 2 2006.201.18:01:42.43#ibcon#read 4, iclass 30, count 2 2006.201.18:01:42.43#ibcon#about to read 5, iclass 30, count 2 2006.201.18:01:42.43#ibcon#read 5, iclass 30, count 2 2006.201.18:01:42.43#ibcon#about to read 6, iclass 30, count 2 2006.201.18:01:42.43#ibcon#read 6, iclass 30, count 2 2006.201.18:01:42.43#ibcon#end of sib2, iclass 30, count 2 2006.201.18:01:42.43#ibcon#*after write, iclass 30, count 2 2006.201.18:01:42.43#ibcon#*before return 0, iclass 30, count 2 2006.201.18:01:42.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:42.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:42.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.18:01:42.43#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:42.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:42.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:42.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:42.55#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:01:42.55#ibcon#first serial, iclass 30, count 0 2006.201.18:01:42.55#ibcon#enter sib2, iclass 30, count 0 2006.201.18:01:42.55#ibcon#flushed, iclass 30, count 0 2006.201.18:01:42.55#ibcon#about to write, iclass 30, count 0 2006.201.18:01:42.55#ibcon#wrote, iclass 30, count 0 2006.201.18:01:42.55#ibcon#about to read 3, iclass 30, count 0 2006.201.18:01:42.57#ibcon#read 3, iclass 30, count 0 2006.201.18:01:42.57#ibcon#about to read 4, iclass 30, count 0 2006.201.18:01:42.57#ibcon#read 4, iclass 30, count 0 2006.201.18:01:42.57#ibcon#about to read 5, iclass 30, count 0 2006.201.18:01:42.57#ibcon#read 5, iclass 30, count 0 2006.201.18:01:42.57#ibcon#about to read 6, iclass 30, count 0 2006.201.18:01:42.57#ibcon#read 6, iclass 30, count 0 2006.201.18:01:42.57#ibcon#end of sib2, iclass 30, count 0 2006.201.18:01:42.57#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:01:42.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:01:42.57#ibcon#[25=USB\r\n] 2006.201.18:01:42.57#ibcon#*before write, iclass 30, count 0 2006.201.18:01:42.57#ibcon#enter sib2, iclass 30, count 0 2006.201.18:01:42.57#ibcon#flushed, iclass 30, count 0 2006.201.18:01:42.57#ibcon#about to write, iclass 30, count 0 2006.201.18:01:42.57#ibcon#wrote, iclass 30, count 0 2006.201.18:01:42.57#ibcon#about to read 3, iclass 30, count 0 2006.201.18:01:42.60#ibcon#read 3, iclass 30, count 0 2006.201.18:01:42.60#ibcon#about to read 4, iclass 30, count 0 2006.201.18:01:42.60#ibcon#read 4, iclass 30, count 0 2006.201.18:01:42.60#ibcon#about to read 5, iclass 30, count 0 2006.201.18:01:42.60#ibcon#read 5, iclass 30, count 0 2006.201.18:01:42.60#ibcon#about to read 6, iclass 30, count 0 2006.201.18:01:42.60#ibcon#read 6, iclass 30, count 0 2006.201.18:01:42.60#ibcon#end of sib2, iclass 30, count 0 2006.201.18:01:42.60#ibcon#*after write, iclass 30, count 0 2006.201.18:01:42.60#ibcon#*before return 0, iclass 30, count 0 2006.201.18:01:42.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:42.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:42.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:01:42.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:01:42.60$vck44/valo=6,814.99 2006.201.18:01:42.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.18:01:42.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.18:01:42.60#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:42.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:42.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:42.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:42.60#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:01:42.60#ibcon#first serial, iclass 32, count 0 2006.201.18:01:42.60#ibcon#enter sib2, iclass 32, count 0 2006.201.18:01:42.60#ibcon#flushed, iclass 32, count 0 2006.201.18:01:42.60#ibcon#about to write, iclass 32, count 0 2006.201.18:01:42.60#ibcon#wrote, iclass 32, count 0 2006.201.18:01:42.60#ibcon#about to read 3, iclass 32, count 0 2006.201.18:01:42.62#ibcon#read 3, iclass 32, count 0 2006.201.18:01:42.62#ibcon#about to read 4, iclass 32, count 0 2006.201.18:01:42.62#ibcon#read 4, iclass 32, count 0 2006.201.18:01:42.62#ibcon#about to read 5, iclass 32, count 0 2006.201.18:01:42.62#ibcon#read 5, iclass 32, count 0 2006.201.18:01:42.62#ibcon#about to read 6, iclass 32, count 0 2006.201.18:01:42.62#ibcon#read 6, iclass 32, count 0 2006.201.18:01:42.62#ibcon#end of sib2, iclass 32, count 0 2006.201.18:01:42.62#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:01:42.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:01:42.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:01:42.62#ibcon#*before write, iclass 32, count 0 2006.201.18:01:42.62#ibcon#enter sib2, iclass 32, count 0 2006.201.18:01:42.62#ibcon#flushed, iclass 32, count 0 2006.201.18:01:42.62#ibcon#about to write, iclass 32, count 0 2006.201.18:01:42.62#ibcon#wrote, iclass 32, count 0 2006.201.18:01:42.62#ibcon#about to read 3, iclass 32, count 0 2006.201.18:01:42.67#ibcon#read 3, iclass 32, count 0 2006.201.18:01:42.67#ibcon#about to read 4, iclass 32, count 0 2006.201.18:01:42.67#ibcon#read 4, iclass 32, count 0 2006.201.18:01:42.67#ibcon#about to read 5, iclass 32, count 0 2006.201.18:01:42.67#ibcon#read 5, iclass 32, count 0 2006.201.18:01:42.67#ibcon#about to read 6, iclass 32, count 0 2006.201.18:01:42.67#ibcon#read 6, iclass 32, count 0 2006.201.18:01:42.67#ibcon#end of sib2, iclass 32, count 0 2006.201.18:01:42.67#ibcon#*after write, iclass 32, count 0 2006.201.18:01:42.67#ibcon#*before return 0, iclass 32, count 0 2006.201.18:01:42.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:42.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:42.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:01:42.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:01:42.67$vck44/va=6,5 2006.201.18:01:42.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.18:01:42.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.18:01:42.67#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:42.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:42.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:42.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:42.72#ibcon#enter wrdev, iclass 34, count 2 2006.201.18:01:42.72#ibcon#first serial, iclass 34, count 2 2006.201.18:01:42.72#ibcon#enter sib2, iclass 34, count 2 2006.201.18:01:42.72#ibcon#flushed, iclass 34, count 2 2006.201.18:01:42.72#ibcon#about to write, iclass 34, count 2 2006.201.18:01:42.72#ibcon#wrote, iclass 34, count 2 2006.201.18:01:42.72#ibcon#about to read 3, iclass 34, count 2 2006.201.18:01:42.74#ibcon#read 3, iclass 34, count 2 2006.201.18:01:42.74#ibcon#about to read 4, iclass 34, count 2 2006.201.18:01:42.74#ibcon#read 4, iclass 34, count 2 2006.201.18:01:42.74#ibcon#about to read 5, iclass 34, count 2 2006.201.18:01:42.74#ibcon#read 5, iclass 34, count 2 2006.201.18:01:42.74#ibcon#about to read 6, iclass 34, count 2 2006.201.18:01:42.74#ibcon#read 6, iclass 34, count 2 2006.201.18:01:42.74#ibcon#end of sib2, iclass 34, count 2 2006.201.18:01:42.74#ibcon#*mode == 0, iclass 34, count 2 2006.201.18:01:42.74#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.18:01:42.74#ibcon#[25=AT06-05\r\n] 2006.201.18:01:42.74#ibcon#*before write, iclass 34, count 2 2006.201.18:01:42.74#ibcon#enter sib2, iclass 34, count 2 2006.201.18:01:42.74#ibcon#flushed, iclass 34, count 2 2006.201.18:01:42.74#ibcon#about to write, iclass 34, count 2 2006.201.18:01:42.74#ibcon#wrote, iclass 34, count 2 2006.201.18:01:42.74#ibcon#about to read 3, iclass 34, count 2 2006.201.18:01:42.77#ibcon#read 3, iclass 34, count 2 2006.201.18:01:42.77#ibcon#about to read 4, iclass 34, count 2 2006.201.18:01:42.77#ibcon#read 4, iclass 34, count 2 2006.201.18:01:42.77#ibcon#about to read 5, iclass 34, count 2 2006.201.18:01:42.77#ibcon#read 5, iclass 34, count 2 2006.201.18:01:42.77#ibcon#about to read 6, iclass 34, count 2 2006.201.18:01:42.77#ibcon#read 6, iclass 34, count 2 2006.201.18:01:42.77#ibcon#end of sib2, iclass 34, count 2 2006.201.18:01:42.77#ibcon#*after write, iclass 34, count 2 2006.201.18:01:42.77#ibcon#*before return 0, iclass 34, count 2 2006.201.18:01:42.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:42.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:42.77#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.18:01:42.77#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:42.77#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:42.89#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:42.89#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:42.89#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:01:42.89#ibcon#first serial, iclass 34, count 0 2006.201.18:01:42.89#ibcon#enter sib2, iclass 34, count 0 2006.201.18:01:42.89#ibcon#flushed, iclass 34, count 0 2006.201.18:01:42.89#ibcon#about to write, iclass 34, count 0 2006.201.18:01:42.89#ibcon#wrote, iclass 34, count 0 2006.201.18:01:42.89#ibcon#about to read 3, iclass 34, count 0 2006.201.18:01:42.91#ibcon#read 3, iclass 34, count 0 2006.201.18:01:42.91#ibcon#about to read 4, iclass 34, count 0 2006.201.18:01:42.91#ibcon#read 4, iclass 34, count 0 2006.201.18:01:42.91#ibcon#about to read 5, iclass 34, count 0 2006.201.18:01:42.91#ibcon#read 5, iclass 34, count 0 2006.201.18:01:42.91#ibcon#about to read 6, iclass 34, count 0 2006.201.18:01:42.91#ibcon#read 6, iclass 34, count 0 2006.201.18:01:42.91#ibcon#end of sib2, iclass 34, count 0 2006.201.18:01:42.91#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:01:42.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:01:42.91#ibcon#[25=USB\r\n] 2006.201.18:01:42.91#ibcon#*before write, iclass 34, count 0 2006.201.18:01:42.91#ibcon#enter sib2, iclass 34, count 0 2006.201.18:01:42.91#ibcon#flushed, iclass 34, count 0 2006.201.18:01:42.91#ibcon#about to write, iclass 34, count 0 2006.201.18:01:42.91#ibcon#wrote, iclass 34, count 0 2006.201.18:01:42.91#ibcon#about to read 3, iclass 34, count 0 2006.201.18:01:42.94#ibcon#read 3, iclass 34, count 0 2006.201.18:01:42.94#ibcon#about to read 4, iclass 34, count 0 2006.201.18:01:42.94#ibcon#read 4, iclass 34, count 0 2006.201.18:01:42.94#ibcon#about to read 5, iclass 34, count 0 2006.201.18:01:42.94#ibcon#read 5, iclass 34, count 0 2006.201.18:01:42.94#ibcon#about to read 6, iclass 34, count 0 2006.201.18:01:42.94#ibcon#read 6, iclass 34, count 0 2006.201.18:01:42.94#ibcon#end of sib2, iclass 34, count 0 2006.201.18:01:42.94#ibcon#*after write, iclass 34, count 0 2006.201.18:01:42.94#ibcon#*before return 0, iclass 34, count 0 2006.201.18:01:42.94#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:42.94#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:42.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:01:42.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:01:42.94$vck44/valo=7,864.99 2006.201.18:01:42.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.18:01:42.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.18:01:42.94#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:42.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:42.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:42.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:42.94#ibcon#enter wrdev, iclass 36, count 0 2006.201.18:01:42.94#ibcon#first serial, iclass 36, count 0 2006.201.18:01:42.94#ibcon#enter sib2, iclass 36, count 0 2006.201.18:01:42.94#ibcon#flushed, iclass 36, count 0 2006.201.18:01:42.94#ibcon#about to write, iclass 36, count 0 2006.201.18:01:42.94#ibcon#wrote, iclass 36, count 0 2006.201.18:01:42.94#ibcon#about to read 3, iclass 36, count 0 2006.201.18:01:42.96#ibcon#read 3, iclass 36, count 0 2006.201.18:01:42.96#ibcon#about to read 4, iclass 36, count 0 2006.201.18:01:42.96#ibcon#read 4, iclass 36, count 0 2006.201.18:01:42.96#ibcon#about to read 5, iclass 36, count 0 2006.201.18:01:42.96#ibcon#read 5, iclass 36, count 0 2006.201.18:01:42.96#ibcon#about to read 6, iclass 36, count 0 2006.201.18:01:42.96#ibcon#read 6, iclass 36, count 0 2006.201.18:01:42.96#ibcon#end of sib2, iclass 36, count 0 2006.201.18:01:42.96#ibcon#*mode == 0, iclass 36, count 0 2006.201.18:01:42.96#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.18:01:42.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:01:42.96#ibcon#*before write, iclass 36, count 0 2006.201.18:01:42.96#ibcon#enter sib2, iclass 36, count 0 2006.201.18:01:42.96#ibcon#flushed, iclass 36, count 0 2006.201.18:01:42.96#ibcon#about to write, iclass 36, count 0 2006.201.18:01:42.96#ibcon#wrote, iclass 36, count 0 2006.201.18:01:42.96#ibcon#about to read 3, iclass 36, count 0 2006.201.18:01:43.00#ibcon#read 3, iclass 36, count 0 2006.201.18:01:43.00#ibcon#about to read 4, iclass 36, count 0 2006.201.18:01:43.00#ibcon#read 4, iclass 36, count 0 2006.201.18:01:43.00#ibcon#about to read 5, iclass 36, count 0 2006.201.18:01:43.00#ibcon#read 5, iclass 36, count 0 2006.201.18:01:43.00#ibcon#about to read 6, iclass 36, count 0 2006.201.18:01:43.00#ibcon#read 6, iclass 36, count 0 2006.201.18:01:43.00#ibcon#end of sib2, iclass 36, count 0 2006.201.18:01:43.00#ibcon#*after write, iclass 36, count 0 2006.201.18:01:43.00#ibcon#*before return 0, iclass 36, count 0 2006.201.18:01:43.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:43.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:43.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.18:01:43.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.18:01:43.00$vck44/va=7,5 2006.201.18:01:43.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.18:01:43.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.18:01:43.00#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:43.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:43.06#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:43.06#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:43.06#ibcon#enter wrdev, iclass 38, count 2 2006.201.18:01:43.06#ibcon#first serial, iclass 38, count 2 2006.201.18:01:43.06#ibcon#enter sib2, iclass 38, count 2 2006.201.18:01:43.06#ibcon#flushed, iclass 38, count 2 2006.201.18:01:43.06#ibcon#about to write, iclass 38, count 2 2006.201.18:01:43.06#ibcon#wrote, iclass 38, count 2 2006.201.18:01:43.06#ibcon#about to read 3, iclass 38, count 2 2006.201.18:01:43.08#ibcon#read 3, iclass 38, count 2 2006.201.18:01:43.08#ibcon#about to read 4, iclass 38, count 2 2006.201.18:01:43.08#ibcon#read 4, iclass 38, count 2 2006.201.18:01:43.08#ibcon#about to read 5, iclass 38, count 2 2006.201.18:01:43.08#ibcon#read 5, iclass 38, count 2 2006.201.18:01:43.08#ibcon#about to read 6, iclass 38, count 2 2006.201.18:01:43.08#ibcon#read 6, iclass 38, count 2 2006.201.18:01:43.08#ibcon#end of sib2, iclass 38, count 2 2006.201.18:01:43.08#ibcon#*mode == 0, iclass 38, count 2 2006.201.18:01:43.08#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.18:01:43.08#ibcon#[25=AT07-05\r\n] 2006.201.18:01:43.08#ibcon#*before write, iclass 38, count 2 2006.201.18:01:43.08#ibcon#enter sib2, iclass 38, count 2 2006.201.18:01:43.08#ibcon#flushed, iclass 38, count 2 2006.201.18:01:43.08#ibcon#about to write, iclass 38, count 2 2006.201.18:01:43.08#ibcon#wrote, iclass 38, count 2 2006.201.18:01:43.08#ibcon#about to read 3, iclass 38, count 2 2006.201.18:01:43.11#ibcon#read 3, iclass 38, count 2 2006.201.18:01:43.11#ibcon#about to read 4, iclass 38, count 2 2006.201.18:01:43.11#ibcon#read 4, iclass 38, count 2 2006.201.18:01:43.11#ibcon#about to read 5, iclass 38, count 2 2006.201.18:01:43.11#ibcon#read 5, iclass 38, count 2 2006.201.18:01:43.11#ibcon#about to read 6, iclass 38, count 2 2006.201.18:01:43.11#ibcon#read 6, iclass 38, count 2 2006.201.18:01:43.11#ibcon#end of sib2, iclass 38, count 2 2006.201.18:01:43.11#ibcon#*after write, iclass 38, count 2 2006.201.18:01:43.11#ibcon#*before return 0, iclass 38, count 2 2006.201.18:01:43.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:43.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:43.11#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.18:01:43.11#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:43.11#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:43.23#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:43.23#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:43.23#ibcon#enter wrdev, iclass 38, count 0 2006.201.18:01:43.23#ibcon#first serial, iclass 38, count 0 2006.201.18:01:43.23#ibcon#enter sib2, iclass 38, count 0 2006.201.18:01:43.23#ibcon#flushed, iclass 38, count 0 2006.201.18:01:43.23#ibcon#about to write, iclass 38, count 0 2006.201.18:01:43.23#ibcon#wrote, iclass 38, count 0 2006.201.18:01:43.23#ibcon#about to read 3, iclass 38, count 0 2006.201.18:01:43.25#ibcon#read 3, iclass 38, count 0 2006.201.18:01:43.25#ibcon#about to read 4, iclass 38, count 0 2006.201.18:01:43.25#ibcon#read 4, iclass 38, count 0 2006.201.18:01:43.25#ibcon#about to read 5, iclass 38, count 0 2006.201.18:01:43.25#ibcon#read 5, iclass 38, count 0 2006.201.18:01:43.25#ibcon#about to read 6, iclass 38, count 0 2006.201.18:01:43.25#ibcon#read 6, iclass 38, count 0 2006.201.18:01:43.25#ibcon#end of sib2, iclass 38, count 0 2006.201.18:01:43.25#ibcon#*mode == 0, iclass 38, count 0 2006.201.18:01:43.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.18:01:43.25#ibcon#[25=USB\r\n] 2006.201.18:01:43.25#ibcon#*before write, iclass 38, count 0 2006.201.18:01:43.25#ibcon#enter sib2, iclass 38, count 0 2006.201.18:01:43.25#ibcon#flushed, iclass 38, count 0 2006.201.18:01:43.25#ibcon#about to write, iclass 38, count 0 2006.201.18:01:43.25#ibcon#wrote, iclass 38, count 0 2006.201.18:01:43.25#ibcon#about to read 3, iclass 38, count 0 2006.201.18:01:43.28#ibcon#read 3, iclass 38, count 0 2006.201.18:01:43.28#ibcon#about to read 4, iclass 38, count 0 2006.201.18:01:43.28#ibcon#read 4, iclass 38, count 0 2006.201.18:01:43.28#ibcon#about to read 5, iclass 38, count 0 2006.201.18:01:43.28#ibcon#read 5, iclass 38, count 0 2006.201.18:01:43.28#ibcon#about to read 6, iclass 38, count 0 2006.201.18:01:43.28#ibcon#read 6, iclass 38, count 0 2006.201.18:01:43.28#ibcon#end of sib2, iclass 38, count 0 2006.201.18:01:43.28#ibcon#*after write, iclass 38, count 0 2006.201.18:01:43.28#ibcon#*before return 0, iclass 38, count 0 2006.201.18:01:43.28#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:43.28#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:43.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.18:01:43.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.18:01:43.28$vck44/valo=8,884.99 2006.201.18:01:43.28#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.18:01:43.28#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.18:01:43.28#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:43.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:43.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:43.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:43.28#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:01:43.28#ibcon#first serial, iclass 40, count 0 2006.201.18:01:43.28#ibcon#enter sib2, iclass 40, count 0 2006.201.18:01:43.28#ibcon#flushed, iclass 40, count 0 2006.201.18:01:43.28#ibcon#about to write, iclass 40, count 0 2006.201.18:01:43.28#ibcon#wrote, iclass 40, count 0 2006.201.18:01:43.28#ibcon#about to read 3, iclass 40, count 0 2006.201.18:01:43.30#ibcon#read 3, iclass 40, count 0 2006.201.18:01:43.30#ibcon#about to read 4, iclass 40, count 0 2006.201.18:01:43.30#ibcon#read 4, iclass 40, count 0 2006.201.18:01:43.30#ibcon#about to read 5, iclass 40, count 0 2006.201.18:01:43.30#ibcon#read 5, iclass 40, count 0 2006.201.18:01:43.30#ibcon#about to read 6, iclass 40, count 0 2006.201.18:01:43.30#ibcon#read 6, iclass 40, count 0 2006.201.18:01:43.30#ibcon#end of sib2, iclass 40, count 0 2006.201.18:01:43.30#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:01:43.30#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:01:43.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:01:43.30#ibcon#*before write, iclass 40, count 0 2006.201.18:01:43.30#ibcon#enter sib2, iclass 40, count 0 2006.201.18:01:43.30#ibcon#flushed, iclass 40, count 0 2006.201.18:01:43.30#ibcon#about to write, iclass 40, count 0 2006.201.18:01:43.30#ibcon#wrote, iclass 40, count 0 2006.201.18:01:43.30#ibcon#about to read 3, iclass 40, count 0 2006.201.18:01:43.34#ibcon#read 3, iclass 40, count 0 2006.201.18:01:43.34#ibcon#about to read 4, iclass 40, count 0 2006.201.18:01:43.34#ibcon#read 4, iclass 40, count 0 2006.201.18:01:43.34#ibcon#about to read 5, iclass 40, count 0 2006.201.18:01:43.34#ibcon#read 5, iclass 40, count 0 2006.201.18:01:43.34#ibcon#about to read 6, iclass 40, count 0 2006.201.18:01:43.34#ibcon#read 6, iclass 40, count 0 2006.201.18:01:43.34#ibcon#end of sib2, iclass 40, count 0 2006.201.18:01:43.34#ibcon#*after write, iclass 40, count 0 2006.201.18:01:43.34#ibcon#*before return 0, iclass 40, count 0 2006.201.18:01:43.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:43.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:43.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:01:43.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:01:43.34$vck44/va=8,4 2006.201.18:01:43.34#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.18:01:43.34#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.18:01:43.34#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:43.34#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:01:43.40#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:01:43.40#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:01:43.40#ibcon#enter wrdev, iclass 4, count 2 2006.201.18:01:43.40#ibcon#first serial, iclass 4, count 2 2006.201.18:01:43.40#ibcon#enter sib2, iclass 4, count 2 2006.201.18:01:43.40#ibcon#flushed, iclass 4, count 2 2006.201.18:01:43.40#ibcon#about to write, iclass 4, count 2 2006.201.18:01:43.40#ibcon#wrote, iclass 4, count 2 2006.201.18:01:43.40#ibcon#about to read 3, iclass 4, count 2 2006.201.18:01:43.42#ibcon#read 3, iclass 4, count 2 2006.201.18:01:43.42#ibcon#about to read 4, iclass 4, count 2 2006.201.18:01:43.42#ibcon#read 4, iclass 4, count 2 2006.201.18:01:43.42#ibcon#about to read 5, iclass 4, count 2 2006.201.18:01:43.42#ibcon#read 5, iclass 4, count 2 2006.201.18:01:43.42#ibcon#about to read 6, iclass 4, count 2 2006.201.18:01:43.42#ibcon#read 6, iclass 4, count 2 2006.201.18:01:43.42#ibcon#end of sib2, iclass 4, count 2 2006.201.18:01:43.42#ibcon#*mode == 0, iclass 4, count 2 2006.201.18:01:43.42#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.18:01:43.42#ibcon#[25=AT08-04\r\n] 2006.201.18:01:43.42#ibcon#*before write, iclass 4, count 2 2006.201.18:01:43.42#ibcon#enter sib2, iclass 4, count 2 2006.201.18:01:43.42#ibcon#flushed, iclass 4, count 2 2006.201.18:01:43.42#ibcon#about to write, iclass 4, count 2 2006.201.18:01:43.42#ibcon#wrote, iclass 4, count 2 2006.201.18:01:43.42#ibcon#about to read 3, iclass 4, count 2 2006.201.18:01:43.45#ibcon#read 3, iclass 4, count 2 2006.201.18:01:43.45#ibcon#about to read 4, iclass 4, count 2 2006.201.18:01:43.45#ibcon#read 4, iclass 4, count 2 2006.201.18:01:43.45#ibcon#about to read 5, iclass 4, count 2 2006.201.18:01:43.45#ibcon#read 5, iclass 4, count 2 2006.201.18:01:43.45#ibcon#about to read 6, iclass 4, count 2 2006.201.18:01:43.45#ibcon#read 6, iclass 4, count 2 2006.201.18:01:43.45#ibcon#end of sib2, iclass 4, count 2 2006.201.18:01:43.45#ibcon#*after write, iclass 4, count 2 2006.201.18:01:43.45#ibcon#*before return 0, iclass 4, count 2 2006.201.18:01:43.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:01:43.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:01:43.45#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.18:01:43.45#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:43.45#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:01:43.57#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:01:43.57#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:01:43.57#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:01:43.57#ibcon#first serial, iclass 4, count 0 2006.201.18:01:43.57#ibcon#enter sib2, iclass 4, count 0 2006.201.18:01:43.57#ibcon#flushed, iclass 4, count 0 2006.201.18:01:43.57#ibcon#about to write, iclass 4, count 0 2006.201.18:01:43.57#ibcon#wrote, iclass 4, count 0 2006.201.18:01:43.57#ibcon#about to read 3, iclass 4, count 0 2006.201.18:01:43.59#ibcon#read 3, iclass 4, count 0 2006.201.18:01:43.59#ibcon#about to read 4, iclass 4, count 0 2006.201.18:01:43.59#ibcon#read 4, iclass 4, count 0 2006.201.18:01:43.59#ibcon#about to read 5, iclass 4, count 0 2006.201.18:01:43.59#ibcon#read 5, iclass 4, count 0 2006.201.18:01:43.59#ibcon#about to read 6, iclass 4, count 0 2006.201.18:01:43.59#ibcon#read 6, iclass 4, count 0 2006.201.18:01:43.59#ibcon#end of sib2, iclass 4, count 0 2006.201.18:01:43.59#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:01:43.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:01:43.59#ibcon#[25=USB\r\n] 2006.201.18:01:43.59#ibcon#*before write, iclass 4, count 0 2006.201.18:01:43.59#ibcon#enter sib2, iclass 4, count 0 2006.201.18:01:43.59#ibcon#flushed, iclass 4, count 0 2006.201.18:01:43.59#ibcon#about to write, iclass 4, count 0 2006.201.18:01:43.59#ibcon#wrote, iclass 4, count 0 2006.201.18:01:43.59#ibcon#about to read 3, iclass 4, count 0 2006.201.18:01:43.62#ibcon#read 3, iclass 4, count 0 2006.201.18:01:43.62#ibcon#about to read 4, iclass 4, count 0 2006.201.18:01:43.62#ibcon#read 4, iclass 4, count 0 2006.201.18:01:43.62#ibcon#about to read 5, iclass 4, count 0 2006.201.18:01:43.62#ibcon#read 5, iclass 4, count 0 2006.201.18:01:43.62#ibcon#about to read 6, iclass 4, count 0 2006.201.18:01:43.62#ibcon#read 6, iclass 4, count 0 2006.201.18:01:43.62#ibcon#end of sib2, iclass 4, count 0 2006.201.18:01:43.62#ibcon#*after write, iclass 4, count 0 2006.201.18:01:43.62#ibcon#*before return 0, iclass 4, count 0 2006.201.18:01:43.62#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:01:43.62#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:01:43.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:01:43.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:01:43.62$vck44/vblo=1,629.99 2006.201.18:01:43.62#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.18:01:43.62#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.18:01:43.62#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:43.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:43.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:43.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:43.62#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:01:43.62#ibcon#first serial, iclass 6, count 0 2006.201.18:01:43.62#ibcon#enter sib2, iclass 6, count 0 2006.201.18:01:43.62#ibcon#flushed, iclass 6, count 0 2006.201.18:01:43.62#ibcon#about to write, iclass 6, count 0 2006.201.18:01:43.62#ibcon#wrote, iclass 6, count 0 2006.201.18:01:43.62#ibcon#about to read 3, iclass 6, count 0 2006.201.18:01:43.64#ibcon#read 3, iclass 6, count 0 2006.201.18:01:43.64#ibcon#about to read 4, iclass 6, count 0 2006.201.18:01:43.64#ibcon#read 4, iclass 6, count 0 2006.201.18:01:43.64#ibcon#about to read 5, iclass 6, count 0 2006.201.18:01:43.64#ibcon#read 5, iclass 6, count 0 2006.201.18:01:43.64#ibcon#about to read 6, iclass 6, count 0 2006.201.18:01:43.64#ibcon#read 6, iclass 6, count 0 2006.201.18:01:43.64#ibcon#end of sib2, iclass 6, count 0 2006.201.18:01:43.64#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:01:43.64#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:01:43.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:01:43.64#ibcon#*before write, iclass 6, count 0 2006.201.18:01:43.64#ibcon#enter sib2, iclass 6, count 0 2006.201.18:01:43.64#ibcon#flushed, iclass 6, count 0 2006.201.18:01:43.64#ibcon#about to write, iclass 6, count 0 2006.201.18:01:43.64#ibcon#wrote, iclass 6, count 0 2006.201.18:01:43.64#ibcon#about to read 3, iclass 6, count 0 2006.201.18:01:43.68#ibcon#read 3, iclass 6, count 0 2006.201.18:01:43.68#ibcon#about to read 4, iclass 6, count 0 2006.201.18:01:43.68#ibcon#read 4, iclass 6, count 0 2006.201.18:01:43.68#ibcon#about to read 5, iclass 6, count 0 2006.201.18:01:43.68#ibcon#read 5, iclass 6, count 0 2006.201.18:01:43.68#ibcon#about to read 6, iclass 6, count 0 2006.201.18:01:43.68#ibcon#read 6, iclass 6, count 0 2006.201.18:01:43.68#ibcon#end of sib2, iclass 6, count 0 2006.201.18:01:43.68#ibcon#*after write, iclass 6, count 0 2006.201.18:01:43.68#ibcon#*before return 0, iclass 6, count 0 2006.201.18:01:43.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:43.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:01:43.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:01:43.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:01:43.68$vck44/vb=1,4 2006.201.18:01:43.68#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.18:01:43.68#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.18:01:43.68#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:43.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:43.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:43.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:43.68#ibcon#enter wrdev, iclass 10, count 2 2006.201.18:01:43.68#ibcon#first serial, iclass 10, count 2 2006.201.18:01:43.68#ibcon#enter sib2, iclass 10, count 2 2006.201.18:01:43.68#ibcon#flushed, iclass 10, count 2 2006.201.18:01:43.68#ibcon#about to write, iclass 10, count 2 2006.201.18:01:43.68#ibcon#wrote, iclass 10, count 2 2006.201.18:01:43.68#ibcon#about to read 3, iclass 10, count 2 2006.201.18:01:43.70#ibcon#read 3, iclass 10, count 2 2006.201.18:01:43.70#ibcon#about to read 4, iclass 10, count 2 2006.201.18:01:43.70#ibcon#read 4, iclass 10, count 2 2006.201.18:01:43.70#ibcon#about to read 5, iclass 10, count 2 2006.201.18:01:43.70#ibcon#read 5, iclass 10, count 2 2006.201.18:01:43.70#ibcon#about to read 6, iclass 10, count 2 2006.201.18:01:43.70#ibcon#read 6, iclass 10, count 2 2006.201.18:01:43.70#ibcon#end of sib2, iclass 10, count 2 2006.201.18:01:43.70#ibcon#*mode == 0, iclass 10, count 2 2006.201.18:01:43.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.18:01:43.70#ibcon#[27=AT01-04\r\n] 2006.201.18:01:43.70#ibcon#*before write, iclass 10, count 2 2006.201.18:01:43.70#ibcon#enter sib2, iclass 10, count 2 2006.201.18:01:43.70#ibcon#flushed, iclass 10, count 2 2006.201.18:01:43.70#ibcon#about to write, iclass 10, count 2 2006.201.18:01:43.70#ibcon#wrote, iclass 10, count 2 2006.201.18:01:43.70#ibcon#about to read 3, iclass 10, count 2 2006.201.18:01:43.73#ibcon#read 3, iclass 10, count 2 2006.201.18:01:43.73#ibcon#about to read 4, iclass 10, count 2 2006.201.18:01:43.73#ibcon#read 4, iclass 10, count 2 2006.201.18:01:43.73#ibcon#about to read 5, iclass 10, count 2 2006.201.18:01:43.73#ibcon#read 5, iclass 10, count 2 2006.201.18:01:43.73#ibcon#about to read 6, iclass 10, count 2 2006.201.18:01:43.73#ibcon#read 6, iclass 10, count 2 2006.201.18:01:43.73#ibcon#end of sib2, iclass 10, count 2 2006.201.18:01:43.73#ibcon#*after write, iclass 10, count 2 2006.201.18:01:43.73#ibcon#*before return 0, iclass 10, count 2 2006.201.18:01:43.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:43.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:01:43.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.18:01:43.73#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:43.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:43.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:43.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:43.85#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:01:43.85#ibcon#first serial, iclass 10, count 0 2006.201.18:01:43.85#ibcon#enter sib2, iclass 10, count 0 2006.201.18:01:43.85#ibcon#flushed, iclass 10, count 0 2006.201.18:01:43.85#ibcon#about to write, iclass 10, count 0 2006.201.18:01:43.85#ibcon#wrote, iclass 10, count 0 2006.201.18:01:43.85#ibcon#about to read 3, iclass 10, count 0 2006.201.18:01:43.87#ibcon#read 3, iclass 10, count 0 2006.201.18:01:43.87#ibcon#about to read 4, iclass 10, count 0 2006.201.18:01:43.87#ibcon#read 4, iclass 10, count 0 2006.201.18:01:43.87#ibcon#about to read 5, iclass 10, count 0 2006.201.18:01:43.87#ibcon#read 5, iclass 10, count 0 2006.201.18:01:43.87#ibcon#about to read 6, iclass 10, count 0 2006.201.18:01:43.87#ibcon#read 6, iclass 10, count 0 2006.201.18:01:43.87#ibcon#end of sib2, iclass 10, count 0 2006.201.18:01:43.87#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:01:43.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:01:43.87#ibcon#[27=USB\r\n] 2006.201.18:01:43.87#ibcon#*before write, iclass 10, count 0 2006.201.18:01:43.87#ibcon#enter sib2, iclass 10, count 0 2006.201.18:01:43.87#ibcon#flushed, iclass 10, count 0 2006.201.18:01:43.87#ibcon#about to write, iclass 10, count 0 2006.201.18:01:43.87#ibcon#wrote, iclass 10, count 0 2006.201.18:01:43.87#ibcon#about to read 3, iclass 10, count 0 2006.201.18:01:43.90#ibcon#read 3, iclass 10, count 0 2006.201.18:01:43.90#ibcon#about to read 4, iclass 10, count 0 2006.201.18:01:43.90#ibcon#read 4, iclass 10, count 0 2006.201.18:01:43.90#ibcon#about to read 5, iclass 10, count 0 2006.201.18:01:43.90#ibcon#read 5, iclass 10, count 0 2006.201.18:01:43.90#ibcon#about to read 6, iclass 10, count 0 2006.201.18:01:43.90#ibcon#read 6, iclass 10, count 0 2006.201.18:01:43.90#ibcon#end of sib2, iclass 10, count 0 2006.201.18:01:43.90#ibcon#*after write, iclass 10, count 0 2006.201.18:01:43.90#ibcon#*before return 0, iclass 10, count 0 2006.201.18:01:43.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:43.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:01:43.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:01:43.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:01:43.90$vck44/vblo=2,634.99 2006.201.18:01:43.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.18:01:43.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.18:01:43.90#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:43.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:43.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:43.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:43.90#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:01:43.90#ibcon#first serial, iclass 12, count 0 2006.201.18:01:43.90#ibcon#enter sib2, iclass 12, count 0 2006.201.18:01:43.90#ibcon#flushed, iclass 12, count 0 2006.201.18:01:43.90#ibcon#about to write, iclass 12, count 0 2006.201.18:01:43.90#ibcon#wrote, iclass 12, count 0 2006.201.18:01:43.90#ibcon#about to read 3, iclass 12, count 0 2006.201.18:01:43.92#ibcon#read 3, iclass 12, count 0 2006.201.18:01:43.92#ibcon#about to read 4, iclass 12, count 0 2006.201.18:01:43.92#ibcon#read 4, iclass 12, count 0 2006.201.18:01:43.92#ibcon#about to read 5, iclass 12, count 0 2006.201.18:01:43.92#ibcon#read 5, iclass 12, count 0 2006.201.18:01:43.92#ibcon#about to read 6, iclass 12, count 0 2006.201.18:01:43.92#ibcon#read 6, iclass 12, count 0 2006.201.18:01:43.92#ibcon#end of sib2, iclass 12, count 0 2006.201.18:01:43.92#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:01:43.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:01:43.92#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:01:43.92#ibcon#*before write, iclass 12, count 0 2006.201.18:01:43.92#ibcon#enter sib2, iclass 12, count 0 2006.201.18:01:43.92#ibcon#flushed, iclass 12, count 0 2006.201.18:01:43.92#ibcon#about to write, iclass 12, count 0 2006.201.18:01:43.92#ibcon#wrote, iclass 12, count 0 2006.201.18:01:43.92#ibcon#about to read 3, iclass 12, count 0 2006.201.18:01:43.96#ibcon#read 3, iclass 12, count 0 2006.201.18:01:43.96#ibcon#about to read 4, iclass 12, count 0 2006.201.18:01:43.96#ibcon#read 4, iclass 12, count 0 2006.201.18:01:43.96#ibcon#about to read 5, iclass 12, count 0 2006.201.18:01:43.96#ibcon#read 5, iclass 12, count 0 2006.201.18:01:43.96#ibcon#about to read 6, iclass 12, count 0 2006.201.18:01:43.96#ibcon#read 6, iclass 12, count 0 2006.201.18:01:43.96#ibcon#end of sib2, iclass 12, count 0 2006.201.18:01:43.96#ibcon#*after write, iclass 12, count 0 2006.201.18:01:43.96#ibcon#*before return 0, iclass 12, count 0 2006.201.18:01:43.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:43.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:01:43.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:01:43.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:01:43.96$vck44/vb=2,5 2006.201.18:01:43.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.18:01:43.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.18:01:43.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:43.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:44.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:44.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:44.02#ibcon#enter wrdev, iclass 14, count 2 2006.201.18:01:44.02#ibcon#first serial, iclass 14, count 2 2006.201.18:01:44.02#ibcon#enter sib2, iclass 14, count 2 2006.201.18:01:44.02#ibcon#flushed, iclass 14, count 2 2006.201.18:01:44.02#ibcon#about to write, iclass 14, count 2 2006.201.18:01:44.02#ibcon#wrote, iclass 14, count 2 2006.201.18:01:44.02#ibcon#about to read 3, iclass 14, count 2 2006.201.18:01:44.04#ibcon#read 3, iclass 14, count 2 2006.201.18:01:44.04#ibcon#about to read 4, iclass 14, count 2 2006.201.18:01:44.04#ibcon#read 4, iclass 14, count 2 2006.201.18:01:44.04#ibcon#about to read 5, iclass 14, count 2 2006.201.18:01:44.04#ibcon#read 5, iclass 14, count 2 2006.201.18:01:44.04#ibcon#about to read 6, iclass 14, count 2 2006.201.18:01:44.04#ibcon#read 6, iclass 14, count 2 2006.201.18:01:44.04#ibcon#end of sib2, iclass 14, count 2 2006.201.18:01:44.04#ibcon#*mode == 0, iclass 14, count 2 2006.201.18:01:44.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.18:01:44.04#ibcon#[27=AT02-05\r\n] 2006.201.18:01:44.04#ibcon#*before write, iclass 14, count 2 2006.201.18:01:44.04#ibcon#enter sib2, iclass 14, count 2 2006.201.18:01:44.04#ibcon#flushed, iclass 14, count 2 2006.201.18:01:44.04#ibcon#about to write, iclass 14, count 2 2006.201.18:01:44.04#ibcon#wrote, iclass 14, count 2 2006.201.18:01:44.04#ibcon#about to read 3, iclass 14, count 2 2006.201.18:01:44.07#ibcon#read 3, iclass 14, count 2 2006.201.18:01:44.07#ibcon#about to read 4, iclass 14, count 2 2006.201.18:01:44.07#ibcon#read 4, iclass 14, count 2 2006.201.18:01:44.07#ibcon#about to read 5, iclass 14, count 2 2006.201.18:01:44.07#ibcon#read 5, iclass 14, count 2 2006.201.18:01:44.07#ibcon#about to read 6, iclass 14, count 2 2006.201.18:01:44.07#ibcon#read 6, iclass 14, count 2 2006.201.18:01:44.07#ibcon#end of sib2, iclass 14, count 2 2006.201.18:01:44.07#ibcon#*after write, iclass 14, count 2 2006.201.18:01:44.07#ibcon#*before return 0, iclass 14, count 2 2006.201.18:01:44.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:44.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:01:44.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.18:01:44.07#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:44.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:44.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:44.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:44.19#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:01:44.19#ibcon#first serial, iclass 14, count 0 2006.201.18:01:44.19#ibcon#enter sib2, iclass 14, count 0 2006.201.18:01:44.19#ibcon#flushed, iclass 14, count 0 2006.201.18:01:44.19#ibcon#about to write, iclass 14, count 0 2006.201.18:01:44.19#ibcon#wrote, iclass 14, count 0 2006.201.18:01:44.19#ibcon#about to read 3, iclass 14, count 0 2006.201.18:01:44.21#ibcon#read 3, iclass 14, count 0 2006.201.18:01:44.21#ibcon#about to read 4, iclass 14, count 0 2006.201.18:01:44.21#ibcon#read 4, iclass 14, count 0 2006.201.18:01:44.21#ibcon#about to read 5, iclass 14, count 0 2006.201.18:01:44.21#ibcon#read 5, iclass 14, count 0 2006.201.18:01:44.21#ibcon#about to read 6, iclass 14, count 0 2006.201.18:01:44.21#ibcon#read 6, iclass 14, count 0 2006.201.18:01:44.21#ibcon#end of sib2, iclass 14, count 0 2006.201.18:01:44.21#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:01:44.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:01:44.21#ibcon#[27=USB\r\n] 2006.201.18:01:44.21#ibcon#*before write, iclass 14, count 0 2006.201.18:01:44.21#ibcon#enter sib2, iclass 14, count 0 2006.201.18:01:44.21#ibcon#flushed, iclass 14, count 0 2006.201.18:01:44.21#ibcon#about to write, iclass 14, count 0 2006.201.18:01:44.21#ibcon#wrote, iclass 14, count 0 2006.201.18:01:44.21#ibcon#about to read 3, iclass 14, count 0 2006.201.18:01:44.24#ibcon#read 3, iclass 14, count 0 2006.201.18:01:44.24#ibcon#about to read 4, iclass 14, count 0 2006.201.18:01:44.24#ibcon#read 4, iclass 14, count 0 2006.201.18:01:44.24#ibcon#about to read 5, iclass 14, count 0 2006.201.18:01:44.24#ibcon#read 5, iclass 14, count 0 2006.201.18:01:44.24#ibcon#about to read 6, iclass 14, count 0 2006.201.18:01:44.24#ibcon#read 6, iclass 14, count 0 2006.201.18:01:44.24#ibcon#end of sib2, iclass 14, count 0 2006.201.18:01:44.24#ibcon#*after write, iclass 14, count 0 2006.201.18:01:44.24#ibcon#*before return 0, iclass 14, count 0 2006.201.18:01:44.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:44.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:01:44.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:01:44.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:01:44.24$vck44/vblo=3,649.99 2006.201.18:01:44.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.18:01:44.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.18:01:44.24#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:44.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:44.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:44.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:44.24#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:01:44.24#ibcon#first serial, iclass 16, count 0 2006.201.18:01:44.24#ibcon#enter sib2, iclass 16, count 0 2006.201.18:01:44.24#ibcon#flushed, iclass 16, count 0 2006.201.18:01:44.24#ibcon#about to write, iclass 16, count 0 2006.201.18:01:44.24#ibcon#wrote, iclass 16, count 0 2006.201.18:01:44.24#ibcon#about to read 3, iclass 16, count 0 2006.201.18:01:44.26#ibcon#read 3, iclass 16, count 0 2006.201.18:01:44.26#ibcon#about to read 4, iclass 16, count 0 2006.201.18:01:44.26#ibcon#read 4, iclass 16, count 0 2006.201.18:01:44.26#ibcon#about to read 5, iclass 16, count 0 2006.201.18:01:44.26#ibcon#read 5, iclass 16, count 0 2006.201.18:01:44.26#ibcon#about to read 6, iclass 16, count 0 2006.201.18:01:44.26#ibcon#read 6, iclass 16, count 0 2006.201.18:01:44.26#ibcon#end of sib2, iclass 16, count 0 2006.201.18:01:44.26#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:01:44.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:01:44.26#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:01:44.26#ibcon#*before write, iclass 16, count 0 2006.201.18:01:44.26#ibcon#enter sib2, iclass 16, count 0 2006.201.18:01:44.26#ibcon#flushed, iclass 16, count 0 2006.201.18:01:44.26#ibcon#about to write, iclass 16, count 0 2006.201.18:01:44.26#ibcon#wrote, iclass 16, count 0 2006.201.18:01:44.26#ibcon#about to read 3, iclass 16, count 0 2006.201.18:01:44.30#ibcon#read 3, iclass 16, count 0 2006.201.18:01:44.30#ibcon#about to read 4, iclass 16, count 0 2006.201.18:01:44.30#ibcon#read 4, iclass 16, count 0 2006.201.18:01:44.30#ibcon#about to read 5, iclass 16, count 0 2006.201.18:01:44.30#ibcon#read 5, iclass 16, count 0 2006.201.18:01:44.30#ibcon#about to read 6, iclass 16, count 0 2006.201.18:01:44.30#ibcon#read 6, iclass 16, count 0 2006.201.18:01:44.30#ibcon#end of sib2, iclass 16, count 0 2006.201.18:01:44.30#ibcon#*after write, iclass 16, count 0 2006.201.18:01:44.30#ibcon#*before return 0, iclass 16, count 0 2006.201.18:01:44.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:44.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:01:44.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:01:44.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:01:44.30$vck44/vb=3,4 2006.201.18:01:44.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.18:01:44.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.18:01:44.30#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:44.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:44.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:44.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:44.36#ibcon#enter wrdev, iclass 18, count 2 2006.201.18:01:44.36#ibcon#first serial, iclass 18, count 2 2006.201.18:01:44.36#ibcon#enter sib2, iclass 18, count 2 2006.201.18:01:44.36#ibcon#flushed, iclass 18, count 2 2006.201.18:01:44.36#ibcon#about to write, iclass 18, count 2 2006.201.18:01:44.36#ibcon#wrote, iclass 18, count 2 2006.201.18:01:44.36#ibcon#about to read 3, iclass 18, count 2 2006.201.18:01:44.38#ibcon#read 3, iclass 18, count 2 2006.201.18:01:44.38#ibcon#about to read 4, iclass 18, count 2 2006.201.18:01:44.38#ibcon#read 4, iclass 18, count 2 2006.201.18:01:44.38#ibcon#about to read 5, iclass 18, count 2 2006.201.18:01:44.38#ibcon#read 5, iclass 18, count 2 2006.201.18:01:44.38#ibcon#about to read 6, iclass 18, count 2 2006.201.18:01:44.38#ibcon#read 6, iclass 18, count 2 2006.201.18:01:44.38#ibcon#end of sib2, iclass 18, count 2 2006.201.18:01:44.38#ibcon#*mode == 0, iclass 18, count 2 2006.201.18:01:44.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.18:01:44.38#ibcon#[27=AT03-04\r\n] 2006.201.18:01:44.38#ibcon#*before write, iclass 18, count 2 2006.201.18:01:44.38#ibcon#enter sib2, iclass 18, count 2 2006.201.18:01:44.38#ibcon#flushed, iclass 18, count 2 2006.201.18:01:44.38#ibcon#about to write, iclass 18, count 2 2006.201.18:01:44.38#ibcon#wrote, iclass 18, count 2 2006.201.18:01:44.38#ibcon#about to read 3, iclass 18, count 2 2006.201.18:01:44.42#ibcon#read 3, iclass 18, count 2 2006.201.18:01:44.42#ibcon#about to read 4, iclass 18, count 2 2006.201.18:01:44.42#ibcon#read 4, iclass 18, count 2 2006.201.18:01:44.42#ibcon#about to read 5, iclass 18, count 2 2006.201.18:01:44.42#ibcon#read 5, iclass 18, count 2 2006.201.18:01:44.42#ibcon#about to read 6, iclass 18, count 2 2006.201.18:01:44.42#ibcon#read 6, iclass 18, count 2 2006.201.18:01:44.42#ibcon#end of sib2, iclass 18, count 2 2006.201.18:01:44.42#ibcon#*after write, iclass 18, count 2 2006.201.18:01:44.42#ibcon#*before return 0, iclass 18, count 2 2006.201.18:01:44.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:44.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:01:44.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.18:01:44.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:44.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:44.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:44.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:44.54#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:01:44.54#ibcon#first serial, iclass 18, count 0 2006.201.18:01:44.54#ibcon#enter sib2, iclass 18, count 0 2006.201.18:01:44.54#ibcon#flushed, iclass 18, count 0 2006.201.18:01:44.54#ibcon#about to write, iclass 18, count 0 2006.201.18:01:44.54#ibcon#wrote, iclass 18, count 0 2006.201.18:01:44.54#ibcon#about to read 3, iclass 18, count 0 2006.201.18:01:44.56#ibcon#read 3, iclass 18, count 0 2006.201.18:01:44.56#ibcon#about to read 4, iclass 18, count 0 2006.201.18:01:44.56#ibcon#read 4, iclass 18, count 0 2006.201.18:01:44.56#ibcon#about to read 5, iclass 18, count 0 2006.201.18:01:44.56#ibcon#read 5, iclass 18, count 0 2006.201.18:01:44.56#ibcon#about to read 6, iclass 18, count 0 2006.201.18:01:44.56#ibcon#read 6, iclass 18, count 0 2006.201.18:01:44.56#ibcon#end of sib2, iclass 18, count 0 2006.201.18:01:44.56#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:01:44.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:01:44.56#ibcon#[27=USB\r\n] 2006.201.18:01:44.56#ibcon#*before write, iclass 18, count 0 2006.201.18:01:44.56#ibcon#enter sib2, iclass 18, count 0 2006.201.18:01:44.56#ibcon#flushed, iclass 18, count 0 2006.201.18:01:44.56#ibcon#about to write, iclass 18, count 0 2006.201.18:01:44.56#ibcon#wrote, iclass 18, count 0 2006.201.18:01:44.56#ibcon#about to read 3, iclass 18, count 0 2006.201.18:01:44.59#ibcon#read 3, iclass 18, count 0 2006.201.18:01:44.59#ibcon#about to read 4, iclass 18, count 0 2006.201.18:01:44.59#ibcon#read 4, iclass 18, count 0 2006.201.18:01:44.59#ibcon#about to read 5, iclass 18, count 0 2006.201.18:01:44.59#ibcon#read 5, iclass 18, count 0 2006.201.18:01:44.59#ibcon#about to read 6, iclass 18, count 0 2006.201.18:01:44.59#ibcon#read 6, iclass 18, count 0 2006.201.18:01:44.59#ibcon#end of sib2, iclass 18, count 0 2006.201.18:01:44.59#ibcon#*after write, iclass 18, count 0 2006.201.18:01:44.59#ibcon#*before return 0, iclass 18, count 0 2006.201.18:01:44.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:44.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:01:44.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:01:44.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:01:44.59$vck44/vblo=4,679.99 2006.201.18:01:44.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.18:01:44.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.18:01:44.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:44.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:44.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:44.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:44.59#ibcon#enter wrdev, iclass 20, count 0 2006.201.18:01:44.59#ibcon#first serial, iclass 20, count 0 2006.201.18:01:44.59#ibcon#enter sib2, iclass 20, count 0 2006.201.18:01:44.59#ibcon#flushed, iclass 20, count 0 2006.201.18:01:44.59#ibcon#about to write, iclass 20, count 0 2006.201.18:01:44.59#ibcon#wrote, iclass 20, count 0 2006.201.18:01:44.59#ibcon#about to read 3, iclass 20, count 0 2006.201.18:01:44.61#ibcon#read 3, iclass 20, count 0 2006.201.18:01:44.61#ibcon#about to read 4, iclass 20, count 0 2006.201.18:01:44.61#ibcon#read 4, iclass 20, count 0 2006.201.18:01:44.61#ibcon#about to read 5, iclass 20, count 0 2006.201.18:01:44.61#ibcon#read 5, iclass 20, count 0 2006.201.18:01:44.61#ibcon#about to read 6, iclass 20, count 0 2006.201.18:01:44.61#ibcon#read 6, iclass 20, count 0 2006.201.18:01:44.61#ibcon#end of sib2, iclass 20, count 0 2006.201.18:01:44.61#ibcon#*mode == 0, iclass 20, count 0 2006.201.18:01:44.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.18:01:44.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:01:44.61#ibcon#*before write, iclass 20, count 0 2006.201.18:01:44.61#ibcon#enter sib2, iclass 20, count 0 2006.201.18:01:44.61#ibcon#flushed, iclass 20, count 0 2006.201.18:01:44.61#ibcon#about to write, iclass 20, count 0 2006.201.18:01:44.61#ibcon#wrote, iclass 20, count 0 2006.201.18:01:44.61#ibcon#about to read 3, iclass 20, count 0 2006.201.18:01:44.65#ibcon#read 3, iclass 20, count 0 2006.201.18:01:44.65#ibcon#about to read 4, iclass 20, count 0 2006.201.18:01:44.65#ibcon#read 4, iclass 20, count 0 2006.201.18:01:44.65#ibcon#about to read 5, iclass 20, count 0 2006.201.18:01:44.65#ibcon#read 5, iclass 20, count 0 2006.201.18:01:44.65#ibcon#about to read 6, iclass 20, count 0 2006.201.18:01:44.65#ibcon#read 6, iclass 20, count 0 2006.201.18:01:44.65#ibcon#end of sib2, iclass 20, count 0 2006.201.18:01:44.65#ibcon#*after write, iclass 20, count 0 2006.201.18:01:44.65#ibcon#*before return 0, iclass 20, count 0 2006.201.18:01:44.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:44.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:01:44.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.18:01:44.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.18:01:44.65$vck44/vb=4,5 2006.201.18:01:44.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.18:01:44.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.18:01:44.65#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:44.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:44.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:44.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:44.71#ibcon#enter wrdev, iclass 22, count 2 2006.201.18:01:44.71#ibcon#first serial, iclass 22, count 2 2006.201.18:01:44.71#ibcon#enter sib2, iclass 22, count 2 2006.201.18:01:44.71#ibcon#flushed, iclass 22, count 2 2006.201.18:01:44.71#ibcon#about to write, iclass 22, count 2 2006.201.18:01:44.71#ibcon#wrote, iclass 22, count 2 2006.201.18:01:44.71#ibcon#about to read 3, iclass 22, count 2 2006.201.18:01:44.73#ibcon#read 3, iclass 22, count 2 2006.201.18:01:44.73#ibcon#about to read 4, iclass 22, count 2 2006.201.18:01:44.73#ibcon#read 4, iclass 22, count 2 2006.201.18:01:44.73#ibcon#about to read 5, iclass 22, count 2 2006.201.18:01:44.73#ibcon#read 5, iclass 22, count 2 2006.201.18:01:44.73#ibcon#about to read 6, iclass 22, count 2 2006.201.18:01:44.73#ibcon#read 6, iclass 22, count 2 2006.201.18:01:44.73#ibcon#end of sib2, iclass 22, count 2 2006.201.18:01:44.73#ibcon#*mode == 0, iclass 22, count 2 2006.201.18:01:44.73#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.18:01:44.73#ibcon#[27=AT04-05\r\n] 2006.201.18:01:44.73#ibcon#*before write, iclass 22, count 2 2006.201.18:01:44.73#ibcon#enter sib2, iclass 22, count 2 2006.201.18:01:44.73#ibcon#flushed, iclass 22, count 2 2006.201.18:01:44.73#ibcon#about to write, iclass 22, count 2 2006.201.18:01:44.73#ibcon#wrote, iclass 22, count 2 2006.201.18:01:44.73#ibcon#about to read 3, iclass 22, count 2 2006.201.18:01:44.76#ibcon#read 3, iclass 22, count 2 2006.201.18:01:44.76#ibcon#about to read 4, iclass 22, count 2 2006.201.18:01:44.76#ibcon#read 4, iclass 22, count 2 2006.201.18:01:44.76#ibcon#about to read 5, iclass 22, count 2 2006.201.18:01:44.76#ibcon#read 5, iclass 22, count 2 2006.201.18:01:44.76#ibcon#about to read 6, iclass 22, count 2 2006.201.18:01:44.76#ibcon#read 6, iclass 22, count 2 2006.201.18:01:44.76#ibcon#end of sib2, iclass 22, count 2 2006.201.18:01:44.76#ibcon#*after write, iclass 22, count 2 2006.201.18:01:44.76#ibcon#*before return 0, iclass 22, count 2 2006.201.18:01:44.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:44.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:01:44.76#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.18:01:44.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:44.76#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:44.88#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:44.88#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:44.88#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:01:44.88#ibcon#first serial, iclass 22, count 0 2006.201.18:01:44.88#ibcon#enter sib2, iclass 22, count 0 2006.201.18:01:44.88#ibcon#flushed, iclass 22, count 0 2006.201.18:01:44.88#ibcon#about to write, iclass 22, count 0 2006.201.18:01:44.88#ibcon#wrote, iclass 22, count 0 2006.201.18:01:44.88#ibcon#about to read 3, iclass 22, count 0 2006.201.18:01:44.90#ibcon#read 3, iclass 22, count 0 2006.201.18:01:44.90#ibcon#about to read 4, iclass 22, count 0 2006.201.18:01:44.90#ibcon#read 4, iclass 22, count 0 2006.201.18:01:44.90#ibcon#about to read 5, iclass 22, count 0 2006.201.18:01:44.90#ibcon#read 5, iclass 22, count 0 2006.201.18:01:44.90#ibcon#about to read 6, iclass 22, count 0 2006.201.18:01:44.90#ibcon#read 6, iclass 22, count 0 2006.201.18:01:44.90#ibcon#end of sib2, iclass 22, count 0 2006.201.18:01:44.90#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:01:44.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:01:44.90#ibcon#[27=USB\r\n] 2006.201.18:01:44.90#ibcon#*before write, iclass 22, count 0 2006.201.18:01:44.90#ibcon#enter sib2, iclass 22, count 0 2006.201.18:01:44.90#ibcon#flushed, iclass 22, count 0 2006.201.18:01:44.90#ibcon#about to write, iclass 22, count 0 2006.201.18:01:44.90#ibcon#wrote, iclass 22, count 0 2006.201.18:01:44.90#ibcon#about to read 3, iclass 22, count 0 2006.201.18:01:44.93#ibcon#read 3, iclass 22, count 0 2006.201.18:01:44.93#ibcon#about to read 4, iclass 22, count 0 2006.201.18:01:44.93#ibcon#read 4, iclass 22, count 0 2006.201.18:01:44.93#ibcon#about to read 5, iclass 22, count 0 2006.201.18:01:44.93#ibcon#read 5, iclass 22, count 0 2006.201.18:01:44.93#ibcon#about to read 6, iclass 22, count 0 2006.201.18:01:44.93#ibcon#read 6, iclass 22, count 0 2006.201.18:01:44.93#ibcon#end of sib2, iclass 22, count 0 2006.201.18:01:44.93#ibcon#*after write, iclass 22, count 0 2006.201.18:01:44.93#ibcon#*before return 0, iclass 22, count 0 2006.201.18:01:44.93#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:44.93#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:01:44.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:01:44.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:01:44.93$vck44/vblo=5,709.99 2006.201.18:01:44.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.18:01:44.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.18:01:44.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:44.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:01:44.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:01:44.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:01:44.93#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:01:44.93#ibcon#first serial, iclass 24, count 0 2006.201.18:01:44.93#ibcon#enter sib2, iclass 24, count 0 2006.201.18:01:44.93#ibcon#flushed, iclass 24, count 0 2006.201.18:01:44.93#ibcon#about to write, iclass 24, count 0 2006.201.18:01:44.93#ibcon#wrote, iclass 24, count 0 2006.201.18:01:44.93#ibcon#about to read 3, iclass 24, count 0 2006.201.18:01:44.95#ibcon#read 3, iclass 24, count 0 2006.201.18:01:44.95#ibcon#about to read 4, iclass 24, count 0 2006.201.18:01:44.95#ibcon#read 4, iclass 24, count 0 2006.201.18:01:44.95#ibcon#about to read 5, iclass 24, count 0 2006.201.18:01:44.95#ibcon#read 5, iclass 24, count 0 2006.201.18:01:44.95#ibcon#about to read 6, iclass 24, count 0 2006.201.18:01:44.95#ibcon#read 6, iclass 24, count 0 2006.201.18:01:44.95#ibcon#end of sib2, iclass 24, count 0 2006.201.18:01:44.95#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:01:44.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:01:44.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:01:44.95#ibcon#*before write, iclass 24, count 0 2006.201.18:01:44.95#ibcon#enter sib2, iclass 24, count 0 2006.201.18:01:44.95#ibcon#flushed, iclass 24, count 0 2006.201.18:01:44.95#ibcon#about to write, iclass 24, count 0 2006.201.18:01:44.95#ibcon#wrote, iclass 24, count 0 2006.201.18:01:44.95#ibcon#about to read 3, iclass 24, count 0 2006.201.18:01:44.99#ibcon#read 3, iclass 24, count 0 2006.201.18:01:44.99#ibcon#about to read 4, iclass 24, count 0 2006.201.18:01:44.99#ibcon#read 4, iclass 24, count 0 2006.201.18:01:44.99#ibcon#about to read 5, iclass 24, count 0 2006.201.18:01:44.99#ibcon#read 5, iclass 24, count 0 2006.201.18:01:44.99#ibcon#about to read 6, iclass 24, count 0 2006.201.18:01:44.99#ibcon#read 6, iclass 24, count 0 2006.201.18:01:44.99#ibcon#end of sib2, iclass 24, count 0 2006.201.18:01:44.99#ibcon#*after write, iclass 24, count 0 2006.201.18:01:44.99#ibcon#*before return 0, iclass 24, count 0 2006.201.18:01:44.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:01:44.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:01:44.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:01:44.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:01:44.99$vck44/vb=5,4 2006.201.18:01:44.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.18:01:44.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.18:01:44.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:44.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:01:45.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:01:45.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:01:45.05#ibcon#enter wrdev, iclass 26, count 2 2006.201.18:01:45.05#ibcon#first serial, iclass 26, count 2 2006.201.18:01:45.05#ibcon#enter sib2, iclass 26, count 2 2006.201.18:01:45.05#ibcon#flushed, iclass 26, count 2 2006.201.18:01:45.05#ibcon#about to write, iclass 26, count 2 2006.201.18:01:45.05#ibcon#wrote, iclass 26, count 2 2006.201.18:01:45.05#ibcon#about to read 3, iclass 26, count 2 2006.201.18:01:45.07#ibcon#read 3, iclass 26, count 2 2006.201.18:01:45.07#ibcon#about to read 4, iclass 26, count 2 2006.201.18:01:45.07#ibcon#read 4, iclass 26, count 2 2006.201.18:01:45.07#ibcon#about to read 5, iclass 26, count 2 2006.201.18:01:45.07#ibcon#read 5, iclass 26, count 2 2006.201.18:01:45.07#ibcon#about to read 6, iclass 26, count 2 2006.201.18:01:45.07#ibcon#read 6, iclass 26, count 2 2006.201.18:01:45.07#ibcon#end of sib2, iclass 26, count 2 2006.201.18:01:45.07#ibcon#*mode == 0, iclass 26, count 2 2006.201.18:01:45.07#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.18:01:45.07#ibcon#[27=AT05-04\r\n] 2006.201.18:01:45.07#ibcon#*before write, iclass 26, count 2 2006.201.18:01:45.07#ibcon#enter sib2, iclass 26, count 2 2006.201.18:01:45.07#ibcon#flushed, iclass 26, count 2 2006.201.18:01:45.07#ibcon#about to write, iclass 26, count 2 2006.201.18:01:45.07#ibcon#wrote, iclass 26, count 2 2006.201.18:01:45.07#ibcon#about to read 3, iclass 26, count 2 2006.201.18:01:45.10#ibcon#read 3, iclass 26, count 2 2006.201.18:01:45.10#ibcon#about to read 4, iclass 26, count 2 2006.201.18:01:45.10#ibcon#read 4, iclass 26, count 2 2006.201.18:01:45.10#ibcon#about to read 5, iclass 26, count 2 2006.201.18:01:45.10#ibcon#read 5, iclass 26, count 2 2006.201.18:01:45.10#ibcon#about to read 6, iclass 26, count 2 2006.201.18:01:45.10#ibcon#read 6, iclass 26, count 2 2006.201.18:01:45.10#ibcon#end of sib2, iclass 26, count 2 2006.201.18:01:45.10#ibcon#*after write, iclass 26, count 2 2006.201.18:01:45.10#ibcon#*before return 0, iclass 26, count 2 2006.201.18:01:45.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:01:45.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:01:45.10#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.18:01:45.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:45.10#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:01:45.22#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:01:45.22#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:01:45.22#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:01:45.22#ibcon#first serial, iclass 26, count 0 2006.201.18:01:45.22#ibcon#enter sib2, iclass 26, count 0 2006.201.18:01:45.22#ibcon#flushed, iclass 26, count 0 2006.201.18:01:45.22#ibcon#about to write, iclass 26, count 0 2006.201.18:01:45.22#ibcon#wrote, iclass 26, count 0 2006.201.18:01:45.22#ibcon#about to read 3, iclass 26, count 0 2006.201.18:01:45.24#ibcon#read 3, iclass 26, count 0 2006.201.18:01:45.24#ibcon#about to read 4, iclass 26, count 0 2006.201.18:01:45.24#ibcon#read 4, iclass 26, count 0 2006.201.18:01:45.24#ibcon#about to read 5, iclass 26, count 0 2006.201.18:01:45.24#ibcon#read 5, iclass 26, count 0 2006.201.18:01:45.24#ibcon#about to read 6, iclass 26, count 0 2006.201.18:01:45.24#ibcon#read 6, iclass 26, count 0 2006.201.18:01:45.24#ibcon#end of sib2, iclass 26, count 0 2006.201.18:01:45.24#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:01:45.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:01:45.24#ibcon#[27=USB\r\n] 2006.201.18:01:45.24#ibcon#*before write, iclass 26, count 0 2006.201.18:01:45.24#ibcon#enter sib2, iclass 26, count 0 2006.201.18:01:45.24#ibcon#flushed, iclass 26, count 0 2006.201.18:01:45.24#ibcon#about to write, iclass 26, count 0 2006.201.18:01:45.24#ibcon#wrote, iclass 26, count 0 2006.201.18:01:45.24#ibcon#about to read 3, iclass 26, count 0 2006.201.18:01:45.27#ibcon#read 3, iclass 26, count 0 2006.201.18:01:45.27#ibcon#about to read 4, iclass 26, count 0 2006.201.18:01:45.27#ibcon#read 4, iclass 26, count 0 2006.201.18:01:45.27#ibcon#about to read 5, iclass 26, count 0 2006.201.18:01:45.27#ibcon#read 5, iclass 26, count 0 2006.201.18:01:45.27#ibcon#about to read 6, iclass 26, count 0 2006.201.18:01:45.27#ibcon#read 6, iclass 26, count 0 2006.201.18:01:45.27#ibcon#end of sib2, iclass 26, count 0 2006.201.18:01:45.27#ibcon#*after write, iclass 26, count 0 2006.201.18:01:45.27#ibcon#*before return 0, iclass 26, count 0 2006.201.18:01:45.27#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:01:45.27#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:01:45.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:01:45.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:01:45.27$vck44/vblo=6,719.99 2006.201.18:01:45.27#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.18:01:45.27#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.18:01:45.27#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:45.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:01:45.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:01:45.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:01:45.27#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:01:45.27#ibcon#first serial, iclass 28, count 0 2006.201.18:01:45.27#ibcon#enter sib2, iclass 28, count 0 2006.201.18:01:45.27#ibcon#flushed, iclass 28, count 0 2006.201.18:01:45.27#ibcon#about to write, iclass 28, count 0 2006.201.18:01:45.27#ibcon#wrote, iclass 28, count 0 2006.201.18:01:45.27#ibcon#about to read 3, iclass 28, count 0 2006.201.18:01:45.29#ibcon#read 3, iclass 28, count 0 2006.201.18:01:45.29#ibcon#about to read 4, iclass 28, count 0 2006.201.18:01:45.29#ibcon#read 4, iclass 28, count 0 2006.201.18:01:45.29#ibcon#about to read 5, iclass 28, count 0 2006.201.18:01:45.29#ibcon#read 5, iclass 28, count 0 2006.201.18:01:45.29#ibcon#about to read 6, iclass 28, count 0 2006.201.18:01:45.29#ibcon#read 6, iclass 28, count 0 2006.201.18:01:45.29#ibcon#end of sib2, iclass 28, count 0 2006.201.18:01:45.29#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:01:45.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:01:45.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:01:45.29#ibcon#*before write, iclass 28, count 0 2006.201.18:01:45.29#ibcon#enter sib2, iclass 28, count 0 2006.201.18:01:45.29#ibcon#flushed, iclass 28, count 0 2006.201.18:01:45.29#ibcon#about to write, iclass 28, count 0 2006.201.18:01:45.29#ibcon#wrote, iclass 28, count 0 2006.201.18:01:45.29#ibcon#about to read 3, iclass 28, count 0 2006.201.18:01:45.34#ibcon#read 3, iclass 28, count 0 2006.201.18:01:45.34#ibcon#about to read 4, iclass 28, count 0 2006.201.18:01:45.34#ibcon#read 4, iclass 28, count 0 2006.201.18:01:45.34#ibcon#about to read 5, iclass 28, count 0 2006.201.18:01:45.34#ibcon#read 5, iclass 28, count 0 2006.201.18:01:45.34#ibcon#about to read 6, iclass 28, count 0 2006.201.18:01:45.34#ibcon#read 6, iclass 28, count 0 2006.201.18:01:45.34#ibcon#end of sib2, iclass 28, count 0 2006.201.18:01:45.34#ibcon#*after write, iclass 28, count 0 2006.201.18:01:45.34#ibcon#*before return 0, iclass 28, count 0 2006.201.18:01:45.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:01:45.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:01:45.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:01:45.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:01:45.34$vck44/vb=6,4 2006.201.18:01:45.34#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.18:01:45.34#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.18:01:45.34#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:45.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:45.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:45.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:45.39#ibcon#enter wrdev, iclass 30, count 2 2006.201.18:01:45.39#ibcon#first serial, iclass 30, count 2 2006.201.18:01:45.39#ibcon#enter sib2, iclass 30, count 2 2006.201.18:01:45.39#ibcon#flushed, iclass 30, count 2 2006.201.18:01:45.39#ibcon#about to write, iclass 30, count 2 2006.201.18:01:45.39#ibcon#wrote, iclass 30, count 2 2006.201.18:01:45.39#ibcon#about to read 3, iclass 30, count 2 2006.201.18:01:45.41#ibcon#read 3, iclass 30, count 2 2006.201.18:01:45.41#ibcon#about to read 4, iclass 30, count 2 2006.201.18:01:45.41#ibcon#read 4, iclass 30, count 2 2006.201.18:01:45.41#ibcon#about to read 5, iclass 30, count 2 2006.201.18:01:45.41#ibcon#read 5, iclass 30, count 2 2006.201.18:01:45.41#ibcon#about to read 6, iclass 30, count 2 2006.201.18:01:45.41#ibcon#read 6, iclass 30, count 2 2006.201.18:01:45.41#ibcon#end of sib2, iclass 30, count 2 2006.201.18:01:45.41#ibcon#*mode == 0, iclass 30, count 2 2006.201.18:01:45.41#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.18:01:45.41#ibcon#[27=AT06-04\r\n] 2006.201.18:01:45.41#ibcon#*before write, iclass 30, count 2 2006.201.18:01:45.41#ibcon#enter sib2, iclass 30, count 2 2006.201.18:01:45.41#ibcon#flushed, iclass 30, count 2 2006.201.18:01:45.41#ibcon#about to write, iclass 30, count 2 2006.201.18:01:45.41#ibcon#wrote, iclass 30, count 2 2006.201.18:01:45.41#ibcon#about to read 3, iclass 30, count 2 2006.201.18:01:45.44#ibcon#read 3, iclass 30, count 2 2006.201.18:01:45.44#ibcon#about to read 4, iclass 30, count 2 2006.201.18:01:45.44#ibcon#read 4, iclass 30, count 2 2006.201.18:01:45.44#ibcon#about to read 5, iclass 30, count 2 2006.201.18:01:45.44#ibcon#read 5, iclass 30, count 2 2006.201.18:01:45.44#ibcon#about to read 6, iclass 30, count 2 2006.201.18:01:45.44#ibcon#read 6, iclass 30, count 2 2006.201.18:01:45.44#ibcon#end of sib2, iclass 30, count 2 2006.201.18:01:45.44#ibcon#*after write, iclass 30, count 2 2006.201.18:01:45.44#ibcon#*before return 0, iclass 30, count 2 2006.201.18:01:45.44#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:45.44#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:01:45.44#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.18:01:45.44#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:45.44#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:45.56#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:45.56#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:45.56#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:01:45.56#ibcon#first serial, iclass 30, count 0 2006.201.18:01:45.56#ibcon#enter sib2, iclass 30, count 0 2006.201.18:01:45.56#ibcon#flushed, iclass 30, count 0 2006.201.18:01:45.56#ibcon#about to write, iclass 30, count 0 2006.201.18:01:45.56#ibcon#wrote, iclass 30, count 0 2006.201.18:01:45.56#ibcon#about to read 3, iclass 30, count 0 2006.201.18:01:45.58#ibcon#read 3, iclass 30, count 0 2006.201.18:01:45.58#ibcon#about to read 4, iclass 30, count 0 2006.201.18:01:45.58#ibcon#read 4, iclass 30, count 0 2006.201.18:01:45.58#ibcon#about to read 5, iclass 30, count 0 2006.201.18:01:45.58#ibcon#read 5, iclass 30, count 0 2006.201.18:01:45.58#ibcon#about to read 6, iclass 30, count 0 2006.201.18:01:45.58#ibcon#read 6, iclass 30, count 0 2006.201.18:01:45.58#ibcon#end of sib2, iclass 30, count 0 2006.201.18:01:45.58#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:01:45.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:01:45.58#ibcon#[27=USB\r\n] 2006.201.18:01:45.58#ibcon#*before write, iclass 30, count 0 2006.201.18:01:45.58#ibcon#enter sib2, iclass 30, count 0 2006.201.18:01:45.58#ibcon#flushed, iclass 30, count 0 2006.201.18:01:45.58#ibcon#about to write, iclass 30, count 0 2006.201.18:01:45.58#ibcon#wrote, iclass 30, count 0 2006.201.18:01:45.58#ibcon#about to read 3, iclass 30, count 0 2006.201.18:01:45.61#ibcon#read 3, iclass 30, count 0 2006.201.18:01:45.61#ibcon#about to read 4, iclass 30, count 0 2006.201.18:01:45.61#ibcon#read 4, iclass 30, count 0 2006.201.18:01:45.61#ibcon#about to read 5, iclass 30, count 0 2006.201.18:01:45.61#ibcon#read 5, iclass 30, count 0 2006.201.18:01:45.61#ibcon#about to read 6, iclass 30, count 0 2006.201.18:01:45.61#ibcon#read 6, iclass 30, count 0 2006.201.18:01:45.61#ibcon#end of sib2, iclass 30, count 0 2006.201.18:01:45.61#ibcon#*after write, iclass 30, count 0 2006.201.18:01:45.61#ibcon#*before return 0, iclass 30, count 0 2006.201.18:01:45.61#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:45.61#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:01:45.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:01:45.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:01:45.61$vck44/vblo=7,734.99 2006.201.18:01:45.61#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.18:01:45.61#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.18:01:45.61#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:45.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:45.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:45.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:45.61#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:01:45.61#ibcon#first serial, iclass 32, count 0 2006.201.18:01:45.61#ibcon#enter sib2, iclass 32, count 0 2006.201.18:01:45.61#ibcon#flushed, iclass 32, count 0 2006.201.18:01:45.61#ibcon#about to write, iclass 32, count 0 2006.201.18:01:45.61#ibcon#wrote, iclass 32, count 0 2006.201.18:01:45.61#ibcon#about to read 3, iclass 32, count 0 2006.201.18:01:45.63#ibcon#read 3, iclass 32, count 0 2006.201.18:01:45.63#ibcon#about to read 4, iclass 32, count 0 2006.201.18:01:45.63#ibcon#read 4, iclass 32, count 0 2006.201.18:01:45.63#ibcon#about to read 5, iclass 32, count 0 2006.201.18:01:45.63#ibcon#read 5, iclass 32, count 0 2006.201.18:01:45.63#ibcon#about to read 6, iclass 32, count 0 2006.201.18:01:45.63#ibcon#read 6, iclass 32, count 0 2006.201.18:01:45.63#ibcon#end of sib2, iclass 32, count 0 2006.201.18:01:45.63#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:01:45.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:01:45.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:01:45.63#ibcon#*before write, iclass 32, count 0 2006.201.18:01:45.63#ibcon#enter sib2, iclass 32, count 0 2006.201.18:01:45.63#ibcon#flushed, iclass 32, count 0 2006.201.18:01:45.63#ibcon#about to write, iclass 32, count 0 2006.201.18:01:45.63#ibcon#wrote, iclass 32, count 0 2006.201.18:01:45.63#ibcon#about to read 3, iclass 32, count 0 2006.201.18:01:45.67#ibcon#read 3, iclass 32, count 0 2006.201.18:01:45.67#ibcon#about to read 4, iclass 32, count 0 2006.201.18:01:45.67#ibcon#read 4, iclass 32, count 0 2006.201.18:01:45.67#ibcon#about to read 5, iclass 32, count 0 2006.201.18:01:45.67#ibcon#read 5, iclass 32, count 0 2006.201.18:01:45.67#ibcon#about to read 6, iclass 32, count 0 2006.201.18:01:45.67#ibcon#read 6, iclass 32, count 0 2006.201.18:01:45.67#ibcon#end of sib2, iclass 32, count 0 2006.201.18:01:45.67#ibcon#*after write, iclass 32, count 0 2006.201.18:01:45.67#ibcon#*before return 0, iclass 32, count 0 2006.201.18:01:45.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:45.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:01:45.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:01:45.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:01:45.67$vck44/vb=7,4 2006.201.18:01:45.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.18:01:45.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.18:01:45.67#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:45.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:45.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:45.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:45.73#ibcon#enter wrdev, iclass 34, count 2 2006.201.18:01:45.73#ibcon#first serial, iclass 34, count 2 2006.201.18:01:45.73#ibcon#enter sib2, iclass 34, count 2 2006.201.18:01:45.73#ibcon#flushed, iclass 34, count 2 2006.201.18:01:45.73#ibcon#about to write, iclass 34, count 2 2006.201.18:01:45.73#ibcon#wrote, iclass 34, count 2 2006.201.18:01:45.73#ibcon#about to read 3, iclass 34, count 2 2006.201.18:01:45.75#ibcon#read 3, iclass 34, count 2 2006.201.18:01:45.75#ibcon#about to read 4, iclass 34, count 2 2006.201.18:01:45.75#ibcon#read 4, iclass 34, count 2 2006.201.18:01:45.75#ibcon#about to read 5, iclass 34, count 2 2006.201.18:01:45.75#ibcon#read 5, iclass 34, count 2 2006.201.18:01:45.75#ibcon#about to read 6, iclass 34, count 2 2006.201.18:01:45.75#ibcon#read 6, iclass 34, count 2 2006.201.18:01:45.75#ibcon#end of sib2, iclass 34, count 2 2006.201.18:01:45.75#ibcon#*mode == 0, iclass 34, count 2 2006.201.18:01:45.75#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.18:01:45.75#ibcon#[27=AT07-04\r\n] 2006.201.18:01:45.75#ibcon#*before write, iclass 34, count 2 2006.201.18:01:45.75#ibcon#enter sib2, iclass 34, count 2 2006.201.18:01:45.75#ibcon#flushed, iclass 34, count 2 2006.201.18:01:45.75#ibcon#about to write, iclass 34, count 2 2006.201.18:01:45.75#ibcon#wrote, iclass 34, count 2 2006.201.18:01:45.75#ibcon#about to read 3, iclass 34, count 2 2006.201.18:01:45.78#ibcon#read 3, iclass 34, count 2 2006.201.18:01:45.78#ibcon#about to read 4, iclass 34, count 2 2006.201.18:01:45.78#ibcon#read 4, iclass 34, count 2 2006.201.18:01:45.78#ibcon#about to read 5, iclass 34, count 2 2006.201.18:01:45.78#ibcon#read 5, iclass 34, count 2 2006.201.18:01:45.78#ibcon#about to read 6, iclass 34, count 2 2006.201.18:01:45.78#ibcon#read 6, iclass 34, count 2 2006.201.18:01:45.78#ibcon#end of sib2, iclass 34, count 2 2006.201.18:01:45.78#ibcon#*after write, iclass 34, count 2 2006.201.18:01:45.78#ibcon#*before return 0, iclass 34, count 2 2006.201.18:01:45.78#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:45.78#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:01:45.78#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.18:01:45.78#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:45.78#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:45.90#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:45.90#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:45.90#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:01:45.90#ibcon#first serial, iclass 34, count 0 2006.201.18:01:45.90#ibcon#enter sib2, iclass 34, count 0 2006.201.18:01:45.90#ibcon#flushed, iclass 34, count 0 2006.201.18:01:45.90#ibcon#about to write, iclass 34, count 0 2006.201.18:01:45.90#ibcon#wrote, iclass 34, count 0 2006.201.18:01:45.90#ibcon#about to read 3, iclass 34, count 0 2006.201.18:01:45.92#ibcon#read 3, iclass 34, count 0 2006.201.18:01:45.92#ibcon#about to read 4, iclass 34, count 0 2006.201.18:01:45.92#ibcon#read 4, iclass 34, count 0 2006.201.18:01:45.92#ibcon#about to read 5, iclass 34, count 0 2006.201.18:01:45.92#ibcon#read 5, iclass 34, count 0 2006.201.18:01:45.92#ibcon#about to read 6, iclass 34, count 0 2006.201.18:01:45.92#ibcon#read 6, iclass 34, count 0 2006.201.18:01:45.92#ibcon#end of sib2, iclass 34, count 0 2006.201.18:01:45.92#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:01:45.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:01:45.92#ibcon#[27=USB\r\n] 2006.201.18:01:45.92#ibcon#*before write, iclass 34, count 0 2006.201.18:01:45.92#ibcon#enter sib2, iclass 34, count 0 2006.201.18:01:45.92#ibcon#flushed, iclass 34, count 0 2006.201.18:01:45.92#ibcon#about to write, iclass 34, count 0 2006.201.18:01:45.92#ibcon#wrote, iclass 34, count 0 2006.201.18:01:45.92#ibcon#about to read 3, iclass 34, count 0 2006.201.18:01:45.95#ibcon#read 3, iclass 34, count 0 2006.201.18:01:45.95#ibcon#about to read 4, iclass 34, count 0 2006.201.18:01:45.95#ibcon#read 4, iclass 34, count 0 2006.201.18:01:45.95#ibcon#about to read 5, iclass 34, count 0 2006.201.18:01:45.95#ibcon#read 5, iclass 34, count 0 2006.201.18:01:45.95#ibcon#about to read 6, iclass 34, count 0 2006.201.18:01:45.95#ibcon#read 6, iclass 34, count 0 2006.201.18:01:45.95#ibcon#end of sib2, iclass 34, count 0 2006.201.18:01:45.95#ibcon#*after write, iclass 34, count 0 2006.201.18:01:45.95#ibcon#*before return 0, iclass 34, count 0 2006.201.18:01:45.95#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:45.95#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:01:45.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:01:45.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:01:45.95$vck44/vblo=8,744.99 2006.201.18:01:45.95#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.18:01:45.95#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.18:01:45.95#ibcon#ireg 17 cls_cnt 0 2006.201.18:01:45.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:45.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:45.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:45.95#ibcon#enter wrdev, iclass 36, count 0 2006.201.18:01:45.95#ibcon#first serial, iclass 36, count 0 2006.201.18:01:45.95#ibcon#enter sib2, iclass 36, count 0 2006.201.18:01:45.95#ibcon#flushed, iclass 36, count 0 2006.201.18:01:45.95#ibcon#about to write, iclass 36, count 0 2006.201.18:01:45.95#ibcon#wrote, iclass 36, count 0 2006.201.18:01:45.95#ibcon#about to read 3, iclass 36, count 0 2006.201.18:01:45.97#ibcon#read 3, iclass 36, count 0 2006.201.18:01:45.97#ibcon#about to read 4, iclass 36, count 0 2006.201.18:01:45.97#ibcon#read 4, iclass 36, count 0 2006.201.18:01:45.97#ibcon#about to read 5, iclass 36, count 0 2006.201.18:01:45.97#ibcon#read 5, iclass 36, count 0 2006.201.18:01:45.97#ibcon#about to read 6, iclass 36, count 0 2006.201.18:01:45.97#ibcon#read 6, iclass 36, count 0 2006.201.18:01:45.97#ibcon#end of sib2, iclass 36, count 0 2006.201.18:01:45.97#ibcon#*mode == 0, iclass 36, count 0 2006.201.18:01:45.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.18:01:45.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:01:45.97#ibcon#*before write, iclass 36, count 0 2006.201.18:01:45.97#ibcon#enter sib2, iclass 36, count 0 2006.201.18:01:45.97#ibcon#flushed, iclass 36, count 0 2006.201.18:01:45.97#ibcon#about to write, iclass 36, count 0 2006.201.18:01:45.97#ibcon#wrote, iclass 36, count 0 2006.201.18:01:45.97#ibcon#about to read 3, iclass 36, count 0 2006.201.18:01:46.01#ibcon#read 3, iclass 36, count 0 2006.201.18:01:46.01#ibcon#about to read 4, iclass 36, count 0 2006.201.18:01:46.01#ibcon#read 4, iclass 36, count 0 2006.201.18:01:46.01#ibcon#about to read 5, iclass 36, count 0 2006.201.18:01:46.01#ibcon#read 5, iclass 36, count 0 2006.201.18:01:46.01#ibcon#about to read 6, iclass 36, count 0 2006.201.18:01:46.01#ibcon#read 6, iclass 36, count 0 2006.201.18:01:46.01#ibcon#end of sib2, iclass 36, count 0 2006.201.18:01:46.01#ibcon#*after write, iclass 36, count 0 2006.201.18:01:46.01#ibcon#*before return 0, iclass 36, count 0 2006.201.18:01:46.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:46.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:01:46.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.18:01:46.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.18:01:46.01$vck44/vb=8,4 2006.201.18:01:46.01#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.18:01:46.01#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.18:01:46.01#ibcon#ireg 11 cls_cnt 2 2006.201.18:01:46.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:46.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:46.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:46.07#ibcon#enter wrdev, iclass 38, count 2 2006.201.18:01:46.07#ibcon#first serial, iclass 38, count 2 2006.201.18:01:46.07#ibcon#enter sib2, iclass 38, count 2 2006.201.18:01:46.07#ibcon#flushed, iclass 38, count 2 2006.201.18:01:46.07#ibcon#about to write, iclass 38, count 2 2006.201.18:01:46.07#ibcon#wrote, iclass 38, count 2 2006.201.18:01:46.07#ibcon#about to read 3, iclass 38, count 2 2006.201.18:01:46.09#ibcon#read 3, iclass 38, count 2 2006.201.18:01:46.09#ibcon#about to read 4, iclass 38, count 2 2006.201.18:01:46.09#ibcon#read 4, iclass 38, count 2 2006.201.18:01:46.09#ibcon#about to read 5, iclass 38, count 2 2006.201.18:01:46.09#ibcon#read 5, iclass 38, count 2 2006.201.18:01:46.09#ibcon#about to read 6, iclass 38, count 2 2006.201.18:01:46.09#ibcon#read 6, iclass 38, count 2 2006.201.18:01:46.09#ibcon#end of sib2, iclass 38, count 2 2006.201.18:01:46.09#ibcon#*mode == 0, iclass 38, count 2 2006.201.18:01:46.09#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.18:01:46.09#ibcon#[27=AT08-04\r\n] 2006.201.18:01:46.09#ibcon#*before write, iclass 38, count 2 2006.201.18:01:46.09#ibcon#enter sib2, iclass 38, count 2 2006.201.18:01:46.09#ibcon#flushed, iclass 38, count 2 2006.201.18:01:46.09#ibcon#about to write, iclass 38, count 2 2006.201.18:01:46.09#ibcon#wrote, iclass 38, count 2 2006.201.18:01:46.09#ibcon#about to read 3, iclass 38, count 2 2006.201.18:01:46.12#ibcon#read 3, iclass 38, count 2 2006.201.18:01:46.12#ibcon#about to read 4, iclass 38, count 2 2006.201.18:01:46.12#ibcon#read 4, iclass 38, count 2 2006.201.18:01:46.12#ibcon#about to read 5, iclass 38, count 2 2006.201.18:01:46.12#ibcon#read 5, iclass 38, count 2 2006.201.18:01:46.12#ibcon#about to read 6, iclass 38, count 2 2006.201.18:01:46.12#ibcon#read 6, iclass 38, count 2 2006.201.18:01:46.12#ibcon#end of sib2, iclass 38, count 2 2006.201.18:01:46.12#ibcon#*after write, iclass 38, count 2 2006.201.18:01:46.12#ibcon#*before return 0, iclass 38, count 2 2006.201.18:01:46.12#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:46.12#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:01:46.12#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.18:01:46.12#ibcon#ireg 7 cls_cnt 0 2006.201.18:01:46.12#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:46.24#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:46.24#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:46.24#ibcon#enter wrdev, iclass 38, count 0 2006.201.18:01:46.24#ibcon#first serial, iclass 38, count 0 2006.201.18:01:46.24#ibcon#enter sib2, iclass 38, count 0 2006.201.18:01:46.24#ibcon#flushed, iclass 38, count 0 2006.201.18:01:46.24#ibcon#about to write, iclass 38, count 0 2006.201.18:01:46.24#ibcon#wrote, iclass 38, count 0 2006.201.18:01:46.24#ibcon#about to read 3, iclass 38, count 0 2006.201.18:01:46.26#ibcon#read 3, iclass 38, count 0 2006.201.18:01:46.26#ibcon#about to read 4, iclass 38, count 0 2006.201.18:01:46.26#ibcon#read 4, iclass 38, count 0 2006.201.18:01:46.26#ibcon#about to read 5, iclass 38, count 0 2006.201.18:01:46.26#ibcon#read 5, iclass 38, count 0 2006.201.18:01:46.26#ibcon#about to read 6, iclass 38, count 0 2006.201.18:01:46.26#ibcon#read 6, iclass 38, count 0 2006.201.18:01:46.26#ibcon#end of sib2, iclass 38, count 0 2006.201.18:01:46.26#ibcon#*mode == 0, iclass 38, count 0 2006.201.18:01:46.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.18:01:46.26#ibcon#[27=USB\r\n] 2006.201.18:01:46.26#ibcon#*before write, iclass 38, count 0 2006.201.18:01:46.26#ibcon#enter sib2, iclass 38, count 0 2006.201.18:01:46.26#ibcon#flushed, iclass 38, count 0 2006.201.18:01:46.26#ibcon#about to write, iclass 38, count 0 2006.201.18:01:46.26#ibcon#wrote, iclass 38, count 0 2006.201.18:01:46.26#ibcon#about to read 3, iclass 38, count 0 2006.201.18:01:46.29#ibcon#read 3, iclass 38, count 0 2006.201.18:01:46.29#ibcon#about to read 4, iclass 38, count 0 2006.201.18:01:46.29#ibcon#read 4, iclass 38, count 0 2006.201.18:01:46.29#ibcon#about to read 5, iclass 38, count 0 2006.201.18:01:46.29#ibcon#read 5, iclass 38, count 0 2006.201.18:01:46.29#ibcon#about to read 6, iclass 38, count 0 2006.201.18:01:46.29#ibcon#read 6, iclass 38, count 0 2006.201.18:01:46.29#ibcon#end of sib2, iclass 38, count 0 2006.201.18:01:46.29#ibcon#*after write, iclass 38, count 0 2006.201.18:01:46.29#ibcon#*before return 0, iclass 38, count 0 2006.201.18:01:46.29#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:46.29#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:01:46.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.18:01:46.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.18:01:46.29$vck44/vabw=wide 2006.201.18:01:46.29#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.18:01:46.29#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.18:01:46.29#ibcon#ireg 8 cls_cnt 0 2006.201.18:01:46.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:46.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:46.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:46.29#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:01:46.29#ibcon#first serial, iclass 40, count 0 2006.201.18:01:46.29#ibcon#enter sib2, iclass 40, count 0 2006.201.18:01:46.29#ibcon#flushed, iclass 40, count 0 2006.201.18:01:46.29#ibcon#about to write, iclass 40, count 0 2006.201.18:01:46.29#ibcon#wrote, iclass 40, count 0 2006.201.18:01:46.29#ibcon#about to read 3, iclass 40, count 0 2006.201.18:01:46.31#ibcon#read 3, iclass 40, count 0 2006.201.18:01:46.31#ibcon#about to read 4, iclass 40, count 0 2006.201.18:01:46.31#ibcon#read 4, iclass 40, count 0 2006.201.18:01:46.31#ibcon#about to read 5, iclass 40, count 0 2006.201.18:01:46.31#ibcon#read 5, iclass 40, count 0 2006.201.18:01:46.31#ibcon#about to read 6, iclass 40, count 0 2006.201.18:01:46.31#ibcon#read 6, iclass 40, count 0 2006.201.18:01:46.31#ibcon#end of sib2, iclass 40, count 0 2006.201.18:01:46.31#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:01:46.31#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:01:46.31#ibcon#[25=BW32\r\n] 2006.201.18:01:46.31#ibcon#*before write, iclass 40, count 0 2006.201.18:01:46.31#ibcon#enter sib2, iclass 40, count 0 2006.201.18:01:46.31#ibcon#flushed, iclass 40, count 0 2006.201.18:01:46.31#ibcon#about to write, iclass 40, count 0 2006.201.18:01:46.31#ibcon#wrote, iclass 40, count 0 2006.201.18:01:46.31#ibcon#about to read 3, iclass 40, count 0 2006.201.18:01:46.35#ibcon#read 3, iclass 40, count 0 2006.201.18:01:46.35#ibcon#about to read 4, iclass 40, count 0 2006.201.18:01:46.35#ibcon#read 4, iclass 40, count 0 2006.201.18:01:46.35#ibcon#about to read 5, iclass 40, count 0 2006.201.18:01:46.35#ibcon#read 5, iclass 40, count 0 2006.201.18:01:46.35#ibcon#about to read 6, iclass 40, count 0 2006.201.18:01:46.35#ibcon#read 6, iclass 40, count 0 2006.201.18:01:46.35#ibcon#end of sib2, iclass 40, count 0 2006.201.18:01:46.35#ibcon#*after write, iclass 40, count 0 2006.201.18:01:46.35#ibcon#*before return 0, iclass 40, count 0 2006.201.18:01:46.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:46.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:01:46.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:01:46.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:01:46.35$vck44/vbbw=wide 2006.201.18:01:46.35#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.18:01:46.35#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.18:01:46.35#ibcon#ireg 8 cls_cnt 0 2006.201.18:01:46.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:01:46.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:01:46.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:01:46.41#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:01:46.41#ibcon#first serial, iclass 4, count 0 2006.201.18:01:46.41#ibcon#enter sib2, iclass 4, count 0 2006.201.18:01:46.41#ibcon#flushed, iclass 4, count 0 2006.201.18:01:46.41#ibcon#about to write, iclass 4, count 0 2006.201.18:01:46.41#ibcon#wrote, iclass 4, count 0 2006.201.18:01:46.41#ibcon#about to read 3, iclass 4, count 0 2006.201.18:01:46.43#ibcon#read 3, iclass 4, count 0 2006.201.18:01:46.43#ibcon#about to read 4, iclass 4, count 0 2006.201.18:01:46.43#ibcon#read 4, iclass 4, count 0 2006.201.18:01:46.43#ibcon#about to read 5, iclass 4, count 0 2006.201.18:01:46.43#ibcon#read 5, iclass 4, count 0 2006.201.18:01:46.43#ibcon#about to read 6, iclass 4, count 0 2006.201.18:01:46.43#ibcon#read 6, iclass 4, count 0 2006.201.18:01:46.43#ibcon#end of sib2, iclass 4, count 0 2006.201.18:01:46.43#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:01:46.43#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:01:46.43#ibcon#[27=BW32\r\n] 2006.201.18:01:46.43#ibcon#*before write, iclass 4, count 0 2006.201.18:01:46.43#ibcon#enter sib2, iclass 4, count 0 2006.201.18:01:46.43#ibcon#flushed, iclass 4, count 0 2006.201.18:01:46.43#ibcon#about to write, iclass 4, count 0 2006.201.18:01:46.43#ibcon#wrote, iclass 4, count 0 2006.201.18:01:46.43#ibcon#about to read 3, iclass 4, count 0 2006.201.18:01:46.46#ibcon#read 3, iclass 4, count 0 2006.201.18:01:46.46#ibcon#about to read 4, iclass 4, count 0 2006.201.18:01:46.46#ibcon#read 4, iclass 4, count 0 2006.201.18:01:46.46#ibcon#about to read 5, iclass 4, count 0 2006.201.18:01:46.46#ibcon#read 5, iclass 4, count 0 2006.201.18:01:46.46#ibcon#about to read 6, iclass 4, count 0 2006.201.18:01:46.46#ibcon#read 6, iclass 4, count 0 2006.201.18:01:46.46#ibcon#end of sib2, iclass 4, count 0 2006.201.18:01:46.46#ibcon#*after write, iclass 4, count 0 2006.201.18:01:46.46#ibcon#*before return 0, iclass 4, count 0 2006.201.18:01:46.46#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:01:46.46#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:01:46.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:01:46.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:01:46.46$setupk4/ifdk4 2006.201.18:01:46.46$ifdk4/lo= 2006.201.18:01:46.46$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:01:46.46$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:01:46.46$ifdk4/patch= 2006.201.18:01:46.46$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:01:46.46$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:01:46.46$setupk4/!*+20s 2006.201.18:01:52.42#abcon#<5=/16 0.6 1.1 20.541001002.3\r\n> 2006.201.18:01:52.44#abcon#{5=INTERFACE CLEAR} 2006.201.18:01:52.50#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:02:00.90$setupk4/"tpicd 2006.201.18:02:00.90$setupk4/echo=off 2006.201.18:02:00.90$setupk4/xlog=off 2006.201.18:02:00.90:!2006.201.18:07:13 2006.201.18:02:33.13#trakl#Source acquired 2006.201.18:02:34.13#flagr#flagr/antenna,acquired 2006.201.18:07:13.00:preob 2006.201.18:07:14.14/onsource/TRACKING 2006.201.18:07:14.14:!2006.201.18:07:23 2006.201.18:07:23.00:"tape 2006.201.18:07:23.00:"st=record 2006.201.18:07:23.00:data_valid=on 2006.201.18:07:23.00:midob 2006.201.18:07:23.14/onsource/TRACKING 2006.201.18:07:23.14/wx/20.51,1002.2,100 2006.201.18:07:23.28/cable/+6.4782E-03 2006.201.18:07:24.37/va/01,08,usb,yes,40,43 2006.201.18:07:24.37/va/02,07,usb,yes,43,44 2006.201.18:07:24.37/va/03,08,usb,yes,39,41 2006.201.18:07:24.37/va/04,07,usb,yes,44,47 2006.201.18:07:24.37/va/05,04,usb,yes,39,40 2006.201.18:07:24.37/va/06,05,usb,yes,40,40 2006.201.18:07:24.37/va/07,05,usb,yes,39,40 2006.201.18:07:24.37/va/08,04,usb,yes,38,46 2006.201.18:07:24.60/valo/01,524.99,yes,locked 2006.201.18:07:24.60/valo/02,534.99,yes,locked 2006.201.18:07:24.60/valo/03,564.99,yes,locked 2006.201.18:07:24.60/valo/04,624.99,yes,locked 2006.201.18:07:24.60/valo/05,734.99,yes,locked 2006.201.18:07:24.60/valo/06,814.99,yes,locked 2006.201.18:07:24.60/valo/07,864.99,yes,locked 2006.201.18:07:24.60/valo/08,884.99,yes,locked 2006.201.18:07:25.69/vb/01,04,usb,yes,31,28 2006.201.18:07:25.69/vb/02,05,usb,yes,29,29 2006.201.18:07:25.69/vb/03,04,usb,yes,30,33 2006.201.18:07:25.69/vb/04,05,usb,yes,30,29 2006.201.18:07:25.69/vb/05,04,usb,yes,27,29 2006.201.18:07:25.69/vb/06,04,usb,yes,31,28 2006.201.18:07:25.69/vb/07,04,usb,yes,31,31 2006.201.18:07:25.69/vb/08,04,usb,yes,29,32 2006.201.18:07:25.93/vblo/01,629.99,yes,locked 2006.201.18:07:25.93/vblo/02,634.99,yes,locked 2006.201.18:07:25.93/vblo/03,649.99,yes,locked 2006.201.18:07:25.93/vblo/04,679.99,yes,locked 2006.201.18:07:25.93/vblo/05,709.99,yes,locked 2006.201.18:07:25.93/vblo/06,719.99,yes,locked 2006.201.18:07:25.93/vblo/07,734.99,yes,locked 2006.201.18:07:25.93/vblo/08,744.99,yes,locked 2006.201.18:07:26.08/vabw/8 2006.201.18:07:26.23/vbbw/8 2006.201.18:07:26.32/xfe/off,on,16.0 2006.201.18:07:26.71/ifatt/23,28,28,28 2006.201.18:07:27.07/fmout-gps/S +4.57E-07 2006.201.18:07:27.11:!2006.201.18:08:23 2006.201.18:08:23.00:data_valid=off 2006.201.18:08:23.00:"et 2006.201.18:08:23.00:!+3s 2006.201.18:08:26.02:"tape 2006.201.18:08:26.02:postob 2006.201.18:08:26.21/cable/+6.4771E-03 2006.201.18:08:26.21/wx/20.51,1002.2,100 2006.201.18:08:26.28/fmout-gps/S +4.57E-07 2006.201.18:08:26.28:scan_name=201-1814,jd0607,210 2006.201.18:08:26.28:source=0059+581,010245.76,582411.1,2000.0,cw 2006.201.18:08:27.14#flagr#flagr/antenna,new-source 2006.201.18:08:27.14:checkk5 2006.201.18:08:27.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:08:27.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:08:28.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:08:28.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:08:29.01/chk_obsdata//k5ts1/T2011807??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.18:08:29.37/chk_obsdata//k5ts2/T2011807??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.18:08:29.73/chk_obsdata//k5ts3/T2011807??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.18:08:30.09/chk_obsdata//k5ts4/T2011807??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.18:08:30.78/k5log//k5ts1_log_newline 2006.201.18:08:31.47/k5log//k5ts2_log_newline 2006.201.18:08:32.15/k5log//k5ts3_log_newline 2006.201.18:08:32.84/k5log//k5ts4_log_newline 2006.201.18:08:32.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:08:32.87:setupk4=1 2006.201.18:08:32.87$setupk4/echo=on 2006.201.18:08:32.87$setupk4/pcalon 2006.201.18:08:32.87$pcalon/"no phase cal control is implemented here 2006.201.18:08:32.87$setupk4/"tpicd=stop 2006.201.18:08:32.87$setupk4/"rec=synch_on 2006.201.18:08:32.87$setupk4/"rec_mode=128 2006.201.18:08:32.87$setupk4/!* 2006.201.18:08:32.87$setupk4/recpk4 2006.201.18:08:32.87$recpk4/recpatch= 2006.201.18:08:32.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:08:32.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:08:32.87$setupk4/vck44 2006.201.18:08:32.87$vck44/valo=1,524.99 2006.201.18:08:32.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.18:08:32.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.18:08:32.87#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:32.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:32.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:32.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:32.87#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:08:32.87#ibcon#first serial, iclass 22, count 0 2006.201.18:08:32.87#ibcon#enter sib2, iclass 22, count 0 2006.201.18:08:32.87#ibcon#flushed, iclass 22, count 0 2006.201.18:08:32.87#ibcon#about to write, iclass 22, count 0 2006.201.18:08:32.87#ibcon#wrote, iclass 22, count 0 2006.201.18:08:32.87#ibcon#about to read 3, iclass 22, count 0 2006.201.18:08:32.91#ibcon#read 3, iclass 22, count 0 2006.201.18:08:32.91#ibcon#about to read 4, iclass 22, count 0 2006.201.18:08:32.91#ibcon#read 4, iclass 22, count 0 2006.201.18:08:32.91#ibcon#about to read 5, iclass 22, count 0 2006.201.18:08:32.91#ibcon#read 5, iclass 22, count 0 2006.201.18:08:32.91#ibcon#about to read 6, iclass 22, count 0 2006.201.18:08:32.91#ibcon#read 6, iclass 22, count 0 2006.201.18:08:32.91#ibcon#end of sib2, iclass 22, count 0 2006.201.18:08:32.91#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:08:32.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:08:32.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:08:32.91#ibcon#*before write, iclass 22, count 0 2006.201.18:08:32.91#ibcon#enter sib2, iclass 22, count 0 2006.201.18:08:32.91#ibcon#flushed, iclass 22, count 0 2006.201.18:08:32.91#ibcon#about to write, iclass 22, count 0 2006.201.18:08:32.91#ibcon#wrote, iclass 22, count 0 2006.201.18:08:32.91#ibcon#about to read 3, iclass 22, count 0 2006.201.18:08:32.96#ibcon#read 3, iclass 22, count 0 2006.201.18:08:32.96#ibcon#about to read 4, iclass 22, count 0 2006.201.18:08:32.96#ibcon#read 4, iclass 22, count 0 2006.201.18:08:32.96#ibcon#about to read 5, iclass 22, count 0 2006.201.18:08:32.96#ibcon#read 5, iclass 22, count 0 2006.201.18:08:32.96#ibcon#about to read 6, iclass 22, count 0 2006.201.18:08:32.96#ibcon#read 6, iclass 22, count 0 2006.201.18:08:32.96#ibcon#end of sib2, iclass 22, count 0 2006.201.18:08:32.96#ibcon#*after write, iclass 22, count 0 2006.201.18:08:32.96#ibcon#*before return 0, iclass 22, count 0 2006.201.18:08:32.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:32.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:32.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:08:32.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:08:32.96$vck44/va=1,8 2006.201.18:08:32.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.18:08:32.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.18:08:32.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:32.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:32.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:32.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:32.96#ibcon#enter wrdev, iclass 24, count 2 2006.201.18:08:32.96#ibcon#first serial, iclass 24, count 2 2006.201.18:08:32.96#ibcon#enter sib2, iclass 24, count 2 2006.201.18:08:32.96#ibcon#flushed, iclass 24, count 2 2006.201.18:08:32.96#ibcon#about to write, iclass 24, count 2 2006.201.18:08:32.96#ibcon#wrote, iclass 24, count 2 2006.201.18:08:32.96#ibcon#about to read 3, iclass 24, count 2 2006.201.18:08:32.98#ibcon#read 3, iclass 24, count 2 2006.201.18:08:32.98#ibcon#about to read 4, iclass 24, count 2 2006.201.18:08:32.98#ibcon#read 4, iclass 24, count 2 2006.201.18:08:32.98#ibcon#about to read 5, iclass 24, count 2 2006.201.18:08:32.98#ibcon#read 5, iclass 24, count 2 2006.201.18:08:32.98#ibcon#about to read 6, iclass 24, count 2 2006.201.18:08:32.98#ibcon#read 6, iclass 24, count 2 2006.201.18:08:32.98#ibcon#end of sib2, iclass 24, count 2 2006.201.18:08:32.98#ibcon#*mode == 0, iclass 24, count 2 2006.201.18:08:32.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.18:08:32.98#ibcon#[25=AT01-08\r\n] 2006.201.18:08:32.98#ibcon#*before write, iclass 24, count 2 2006.201.18:08:32.98#ibcon#enter sib2, iclass 24, count 2 2006.201.18:08:32.98#ibcon#flushed, iclass 24, count 2 2006.201.18:08:32.98#ibcon#about to write, iclass 24, count 2 2006.201.18:08:32.98#ibcon#wrote, iclass 24, count 2 2006.201.18:08:32.98#ibcon#about to read 3, iclass 24, count 2 2006.201.18:08:33.01#ibcon#read 3, iclass 24, count 2 2006.201.18:08:33.01#ibcon#about to read 4, iclass 24, count 2 2006.201.18:08:33.01#ibcon#read 4, iclass 24, count 2 2006.201.18:08:33.01#ibcon#about to read 5, iclass 24, count 2 2006.201.18:08:33.01#ibcon#read 5, iclass 24, count 2 2006.201.18:08:33.01#ibcon#about to read 6, iclass 24, count 2 2006.201.18:08:33.01#ibcon#read 6, iclass 24, count 2 2006.201.18:08:33.01#ibcon#end of sib2, iclass 24, count 2 2006.201.18:08:33.01#ibcon#*after write, iclass 24, count 2 2006.201.18:08:33.01#ibcon#*before return 0, iclass 24, count 2 2006.201.18:08:33.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:33.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:33.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.18:08:33.01#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:33.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:33.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:33.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:33.13#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:08:33.13#ibcon#first serial, iclass 24, count 0 2006.201.18:08:33.13#ibcon#enter sib2, iclass 24, count 0 2006.201.18:08:33.13#ibcon#flushed, iclass 24, count 0 2006.201.18:08:33.13#ibcon#about to write, iclass 24, count 0 2006.201.18:08:33.13#ibcon#wrote, iclass 24, count 0 2006.201.18:08:33.13#ibcon#about to read 3, iclass 24, count 0 2006.201.18:08:33.15#ibcon#read 3, iclass 24, count 0 2006.201.18:08:33.15#ibcon#about to read 4, iclass 24, count 0 2006.201.18:08:33.15#ibcon#read 4, iclass 24, count 0 2006.201.18:08:33.15#ibcon#about to read 5, iclass 24, count 0 2006.201.18:08:33.15#ibcon#read 5, iclass 24, count 0 2006.201.18:08:33.15#ibcon#about to read 6, iclass 24, count 0 2006.201.18:08:33.15#ibcon#read 6, iclass 24, count 0 2006.201.18:08:33.15#ibcon#end of sib2, iclass 24, count 0 2006.201.18:08:33.15#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:08:33.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:08:33.15#ibcon#[25=USB\r\n] 2006.201.18:08:33.15#ibcon#*before write, iclass 24, count 0 2006.201.18:08:33.15#ibcon#enter sib2, iclass 24, count 0 2006.201.18:08:33.15#ibcon#flushed, iclass 24, count 0 2006.201.18:08:33.15#ibcon#about to write, iclass 24, count 0 2006.201.18:08:33.15#ibcon#wrote, iclass 24, count 0 2006.201.18:08:33.15#ibcon#about to read 3, iclass 24, count 0 2006.201.18:08:33.18#ibcon#read 3, iclass 24, count 0 2006.201.18:08:33.18#ibcon#about to read 4, iclass 24, count 0 2006.201.18:08:33.18#ibcon#read 4, iclass 24, count 0 2006.201.18:08:33.18#ibcon#about to read 5, iclass 24, count 0 2006.201.18:08:33.18#ibcon#read 5, iclass 24, count 0 2006.201.18:08:33.18#ibcon#about to read 6, iclass 24, count 0 2006.201.18:08:33.18#ibcon#read 6, iclass 24, count 0 2006.201.18:08:33.18#ibcon#end of sib2, iclass 24, count 0 2006.201.18:08:33.18#ibcon#*after write, iclass 24, count 0 2006.201.18:08:33.18#ibcon#*before return 0, iclass 24, count 0 2006.201.18:08:33.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:33.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:33.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:08:33.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:08:33.18$vck44/valo=2,534.99 2006.201.18:08:33.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.18:08:33.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.18:08:33.18#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:33.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:33.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:33.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:33.18#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:08:33.18#ibcon#first serial, iclass 26, count 0 2006.201.18:08:33.18#ibcon#enter sib2, iclass 26, count 0 2006.201.18:08:33.18#ibcon#flushed, iclass 26, count 0 2006.201.18:08:33.18#ibcon#about to write, iclass 26, count 0 2006.201.18:08:33.18#ibcon#wrote, iclass 26, count 0 2006.201.18:08:33.18#ibcon#about to read 3, iclass 26, count 0 2006.201.18:08:33.20#ibcon#read 3, iclass 26, count 0 2006.201.18:08:33.20#ibcon#about to read 4, iclass 26, count 0 2006.201.18:08:33.20#ibcon#read 4, iclass 26, count 0 2006.201.18:08:33.20#ibcon#about to read 5, iclass 26, count 0 2006.201.18:08:33.20#ibcon#read 5, iclass 26, count 0 2006.201.18:08:33.20#ibcon#about to read 6, iclass 26, count 0 2006.201.18:08:33.20#ibcon#read 6, iclass 26, count 0 2006.201.18:08:33.20#ibcon#end of sib2, iclass 26, count 0 2006.201.18:08:33.20#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:08:33.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:08:33.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:08:33.20#ibcon#*before write, iclass 26, count 0 2006.201.18:08:33.20#ibcon#enter sib2, iclass 26, count 0 2006.201.18:08:33.20#ibcon#flushed, iclass 26, count 0 2006.201.18:08:33.20#ibcon#about to write, iclass 26, count 0 2006.201.18:08:33.20#ibcon#wrote, iclass 26, count 0 2006.201.18:08:33.20#ibcon#about to read 3, iclass 26, count 0 2006.201.18:08:33.24#ibcon#read 3, iclass 26, count 0 2006.201.18:08:33.24#ibcon#about to read 4, iclass 26, count 0 2006.201.18:08:33.24#ibcon#read 4, iclass 26, count 0 2006.201.18:08:33.24#ibcon#about to read 5, iclass 26, count 0 2006.201.18:08:33.24#ibcon#read 5, iclass 26, count 0 2006.201.18:08:33.24#ibcon#about to read 6, iclass 26, count 0 2006.201.18:08:33.24#ibcon#read 6, iclass 26, count 0 2006.201.18:08:33.24#ibcon#end of sib2, iclass 26, count 0 2006.201.18:08:33.24#ibcon#*after write, iclass 26, count 0 2006.201.18:08:33.24#ibcon#*before return 0, iclass 26, count 0 2006.201.18:08:33.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:33.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:33.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:08:33.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:08:33.24$vck44/va=2,7 2006.201.18:08:33.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.18:08:33.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.18:08:33.24#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:33.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:33.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:33.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:33.30#ibcon#enter wrdev, iclass 28, count 2 2006.201.18:08:33.30#ibcon#first serial, iclass 28, count 2 2006.201.18:08:33.30#ibcon#enter sib2, iclass 28, count 2 2006.201.18:08:33.30#ibcon#flushed, iclass 28, count 2 2006.201.18:08:33.30#ibcon#about to write, iclass 28, count 2 2006.201.18:08:33.30#ibcon#wrote, iclass 28, count 2 2006.201.18:08:33.30#ibcon#about to read 3, iclass 28, count 2 2006.201.18:08:33.32#ibcon#read 3, iclass 28, count 2 2006.201.18:08:33.32#ibcon#about to read 4, iclass 28, count 2 2006.201.18:08:33.32#ibcon#read 4, iclass 28, count 2 2006.201.18:08:33.32#ibcon#about to read 5, iclass 28, count 2 2006.201.18:08:33.32#ibcon#read 5, iclass 28, count 2 2006.201.18:08:33.32#ibcon#about to read 6, iclass 28, count 2 2006.201.18:08:33.32#ibcon#read 6, iclass 28, count 2 2006.201.18:08:33.32#ibcon#end of sib2, iclass 28, count 2 2006.201.18:08:33.32#ibcon#*mode == 0, iclass 28, count 2 2006.201.18:08:33.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.18:08:33.32#ibcon#[25=AT02-07\r\n] 2006.201.18:08:33.32#ibcon#*before write, iclass 28, count 2 2006.201.18:08:33.32#ibcon#enter sib2, iclass 28, count 2 2006.201.18:08:33.32#ibcon#flushed, iclass 28, count 2 2006.201.18:08:33.32#ibcon#about to write, iclass 28, count 2 2006.201.18:08:33.32#ibcon#wrote, iclass 28, count 2 2006.201.18:08:33.32#ibcon#about to read 3, iclass 28, count 2 2006.201.18:08:33.35#ibcon#read 3, iclass 28, count 2 2006.201.18:08:33.35#ibcon#about to read 4, iclass 28, count 2 2006.201.18:08:33.35#ibcon#read 4, iclass 28, count 2 2006.201.18:08:33.35#ibcon#about to read 5, iclass 28, count 2 2006.201.18:08:33.35#ibcon#read 5, iclass 28, count 2 2006.201.18:08:33.35#ibcon#about to read 6, iclass 28, count 2 2006.201.18:08:33.35#ibcon#read 6, iclass 28, count 2 2006.201.18:08:33.35#ibcon#end of sib2, iclass 28, count 2 2006.201.18:08:33.35#ibcon#*after write, iclass 28, count 2 2006.201.18:08:33.35#ibcon#*before return 0, iclass 28, count 2 2006.201.18:08:33.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:33.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:33.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.18:08:33.35#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:33.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:33.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:33.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:33.47#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:08:33.47#ibcon#first serial, iclass 28, count 0 2006.201.18:08:33.47#ibcon#enter sib2, iclass 28, count 0 2006.201.18:08:33.47#ibcon#flushed, iclass 28, count 0 2006.201.18:08:33.47#ibcon#about to write, iclass 28, count 0 2006.201.18:08:33.47#ibcon#wrote, iclass 28, count 0 2006.201.18:08:33.47#ibcon#about to read 3, iclass 28, count 0 2006.201.18:08:33.49#ibcon#read 3, iclass 28, count 0 2006.201.18:08:33.49#ibcon#about to read 4, iclass 28, count 0 2006.201.18:08:33.49#ibcon#read 4, iclass 28, count 0 2006.201.18:08:33.49#ibcon#about to read 5, iclass 28, count 0 2006.201.18:08:33.49#ibcon#read 5, iclass 28, count 0 2006.201.18:08:33.49#ibcon#about to read 6, iclass 28, count 0 2006.201.18:08:33.49#ibcon#read 6, iclass 28, count 0 2006.201.18:08:33.49#ibcon#end of sib2, iclass 28, count 0 2006.201.18:08:33.49#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:08:33.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:08:33.49#ibcon#[25=USB\r\n] 2006.201.18:08:33.49#ibcon#*before write, iclass 28, count 0 2006.201.18:08:33.49#ibcon#enter sib2, iclass 28, count 0 2006.201.18:08:33.49#ibcon#flushed, iclass 28, count 0 2006.201.18:08:33.49#ibcon#about to write, iclass 28, count 0 2006.201.18:08:33.49#ibcon#wrote, iclass 28, count 0 2006.201.18:08:33.49#ibcon#about to read 3, iclass 28, count 0 2006.201.18:08:33.52#ibcon#read 3, iclass 28, count 0 2006.201.18:08:33.52#ibcon#about to read 4, iclass 28, count 0 2006.201.18:08:33.52#ibcon#read 4, iclass 28, count 0 2006.201.18:08:33.52#ibcon#about to read 5, iclass 28, count 0 2006.201.18:08:33.52#ibcon#read 5, iclass 28, count 0 2006.201.18:08:33.52#ibcon#about to read 6, iclass 28, count 0 2006.201.18:08:33.52#ibcon#read 6, iclass 28, count 0 2006.201.18:08:33.52#ibcon#end of sib2, iclass 28, count 0 2006.201.18:08:33.52#ibcon#*after write, iclass 28, count 0 2006.201.18:08:33.52#ibcon#*before return 0, iclass 28, count 0 2006.201.18:08:33.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:33.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:33.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:08:33.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:08:33.52$vck44/valo=3,564.99 2006.201.18:08:33.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.18:08:33.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.18:08:33.52#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:33.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:33.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:33.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:33.52#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:08:33.52#ibcon#first serial, iclass 30, count 0 2006.201.18:08:33.52#ibcon#enter sib2, iclass 30, count 0 2006.201.18:08:33.52#ibcon#flushed, iclass 30, count 0 2006.201.18:08:33.52#ibcon#about to write, iclass 30, count 0 2006.201.18:08:33.52#ibcon#wrote, iclass 30, count 0 2006.201.18:08:33.52#ibcon#about to read 3, iclass 30, count 0 2006.201.18:08:33.54#ibcon#read 3, iclass 30, count 0 2006.201.18:08:33.54#ibcon#about to read 4, iclass 30, count 0 2006.201.18:08:33.54#ibcon#read 4, iclass 30, count 0 2006.201.18:08:33.54#ibcon#about to read 5, iclass 30, count 0 2006.201.18:08:33.54#ibcon#read 5, iclass 30, count 0 2006.201.18:08:33.54#ibcon#about to read 6, iclass 30, count 0 2006.201.18:08:33.54#ibcon#read 6, iclass 30, count 0 2006.201.18:08:33.54#ibcon#end of sib2, iclass 30, count 0 2006.201.18:08:33.54#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:08:33.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:08:33.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:08:33.54#ibcon#*before write, iclass 30, count 0 2006.201.18:08:33.54#ibcon#enter sib2, iclass 30, count 0 2006.201.18:08:33.54#ibcon#flushed, iclass 30, count 0 2006.201.18:08:33.54#ibcon#about to write, iclass 30, count 0 2006.201.18:08:33.54#ibcon#wrote, iclass 30, count 0 2006.201.18:08:33.54#ibcon#about to read 3, iclass 30, count 0 2006.201.18:08:33.58#ibcon#read 3, iclass 30, count 0 2006.201.18:08:33.58#ibcon#about to read 4, iclass 30, count 0 2006.201.18:08:33.58#ibcon#read 4, iclass 30, count 0 2006.201.18:08:33.58#ibcon#about to read 5, iclass 30, count 0 2006.201.18:08:33.58#ibcon#read 5, iclass 30, count 0 2006.201.18:08:33.58#ibcon#about to read 6, iclass 30, count 0 2006.201.18:08:33.58#ibcon#read 6, iclass 30, count 0 2006.201.18:08:33.58#ibcon#end of sib2, iclass 30, count 0 2006.201.18:08:33.58#ibcon#*after write, iclass 30, count 0 2006.201.18:08:33.58#ibcon#*before return 0, iclass 30, count 0 2006.201.18:08:33.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:33.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:33.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:08:33.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:08:33.58$vck44/va=3,8 2006.201.18:08:33.58#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.18:08:33.58#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.18:08:33.58#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:33.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:33.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:33.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:33.64#ibcon#enter wrdev, iclass 32, count 2 2006.201.18:08:33.64#ibcon#first serial, iclass 32, count 2 2006.201.18:08:33.64#ibcon#enter sib2, iclass 32, count 2 2006.201.18:08:33.64#ibcon#flushed, iclass 32, count 2 2006.201.18:08:33.64#ibcon#about to write, iclass 32, count 2 2006.201.18:08:33.64#ibcon#wrote, iclass 32, count 2 2006.201.18:08:33.64#ibcon#about to read 3, iclass 32, count 2 2006.201.18:08:33.66#ibcon#read 3, iclass 32, count 2 2006.201.18:08:33.66#ibcon#about to read 4, iclass 32, count 2 2006.201.18:08:33.66#ibcon#read 4, iclass 32, count 2 2006.201.18:08:33.66#ibcon#about to read 5, iclass 32, count 2 2006.201.18:08:33.66#ibcon#read 5, iclass 32, count 2 2006.201.18:08:33.66#ibcon#about to read 6, iclass 32, count 2 2006.201.18:08:33.66#ibcon#read 6, iclass 32, count 2 2006.201.18:08:33.66#ibcon#end of sib2, iclass 32, count 2 2006.201.18:08:33.66#ibcon#*mode == 0, iclass 32, count 2 2006.201.18:08:33.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.18:08:33.66#ibcon#[25=AT03-08\r\n] 2006.201.18:08:33.66#ibcon#*before write, iclass 32, count 2 2006.201.18:08:33.66#ibcon#enter sib2, iclass 32, count 2 2006.201.18:08:33.66#ibcon#flushed, iclass 32, count 2 2006.201.18:08:33.66#ibcon#about to write, iclass 32, count 2 2006.201.18:08:33.66#ibcon#wrote, iclass 32, count 2 2006.201.18:08:33.66#ibcon#about to read 3, iclass 32, count 2 2006.201.18:08:33.69#ibcon#read 3, iclass 32, count 2 2006.201.18:08:33.69#ibcon#about to read 4, iclass 32, count 2 2006.201.18:08:33.69#ibcon#read 4, iclass 32, count 2 2006.201.18:08:33.69#ibcon#about to read 5, iclass 32, count 2 2006.201.18:08:33.69#ibcon#read 5, iclass 32, count 2 2006.201.18:08:33.69#ibcon#about to read 6, iclass 32, count 2 2006.201.18:08:33.69#ibcon#read 6, iclass 32, count 2 2006.201.18:08:33.69#ibcon#end of sib2, iclass 32, count 2 2006.201.18:08:33.69#ibcon#*after write, iclass 32, count 2 2006.201.18:08:33.69#ibcon#*before return 0, iclass 32, count 2 2006.201.18:08:33.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:33.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:33.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.18:08:33.69#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:33.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:33.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:33.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:33.81#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:08:33.81#ibcon#first serial, iclass 32, count 0 2006.201.18:08:33.81#ibcon#enter sib2, iclass 32, count 0 2006.201.18:08:33.81#ibcon#flushed, iclass 32, count 0 2006.201.18:08:33.81#ibcon#about to write, iclass 32, count 0 2006.201.18:08:33.81#ibcon#wrote, iclass 32, count 0 2006.201.18:08:33.81#ibcon#about to read 3, iclass 32, count 0 2006.201.18:08:33.83#ibcon#read 3, iclass 32, count 0 2006.201.18:08:33.83#ibcon#about to read 4, iclass 32, count 0 2006.201.18:08:33.83#ibcon#read 4, iclass 32, count 0 2006.201.18:08:33.83#ibcon#about to read 5, iclass 32, count 0 2006.201.18:08:33.83#ibcon#read 5, iclass 32, count 0 2006.201.18:08:33.83#ibcon#about to read 6, iclass 32, count 0 2006.201.18:08:33.83#ibcon#read 6, iclass 32, count 0 2006.201.18:08:33.83#ibcon#end of sib2, iclass 32, count 0 2006.201.18:08:33.83#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:08:33.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:08:33.83#ibcon#[25=USB\r\n] 2006.201.18:08:33.83#ibcon#*before write, iclass 32, count 0 2006.201.18:08:33.83#ibcon#enter sib2, iclass 32, count 0 2006.201.18:08:33.83#ibcon#flushed, iclass 32, count 0 2006.201.18:08:33.83#ibcon#about to write, iclass 32, count 0 2006.201.18:08:33.83#ibcon#wrote, iclass 32, count 0 2006.201.18:08:33.83#ibcon#about to read 3, iclass 32, count 0 2006.201.18:08:33.86#ibcon#read 3, iclass 32, count 0 2006.201.18:08:33.86#ibcon#about to read 4, iclass 32, count 0 2006.201.18:08:33.86#ibcon#read 4, iclass 32, count 0 2006.201.18:08:33.86#ibcon#about to read 5, iclass 32, count 0 2006.201.18:08:33.86#ibcon#read 5, iclass 32, count 0 2006.201.18:08:33.86#ibcon#about to read 6, iclass 32, count 0 2006.201.18:08:33.86#ibcon#read 6, iclass 32, count 0 2006.201.18:08:33.86#ibcon#end of sib2, iclass 32, count 0 2006.201.18:08:33.86#ibcon#*after write, iclass 32, count 0 2006.201.18:08:33.86#ibcon#*before return 0, iclass 32, count 0 2006.201.18:08:33.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:33.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:33.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:08:33.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:08:33.86$vck44/valo=4,624.99 2006.201.18:08:33.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.18:08:33.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.18:08:33.86#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:33.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:33.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:33.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:33.86#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:08:33.86#ibcon#first serial, iclass 34, count 0 2006.201.18:08:33.86#ibcon#enter sib2, iclass 34, count 0 2006.201.18:08:33.86#ibcon#flushed, iclass 34, count 0 2006.201.18:08:33.86#ibcon#about to write, iclass 34, count 0 2006.201.18:08:33.86#ibcon#wrote, iclass 34, count 0 2006.201.18:08:33.86#ibcon#about to read 3, iclass 34, count 0 2006.201.18:08:33.88#ibcon#read 3, iclass 34, count 0 2006.201.18:08:33.88#ibcon#about to read 4, iclass 34, count 0 2006.201.18:08:33.88#ibcon#read 4, iclass 34, count 0 2006.201.18:08:33.88#ibcon#about to read 5, iclass 34, count 0 2006.201.18:08:33.88#ibcon#read 5, iclass 34, count 0 2006.201.18:08:33.88#ibcon#about to read 6, iclass 34, count 0 2006.201.18:08:33.88#ibcon#read 6, iclass 34, count 0 2006.201.18:08:33.88#ibcon#end of sib2, iclass 34, count 0 2006.201.18:08:33.88#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:08:33.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:08:33.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:08:33.88#ibcon#*before write, iclass 34, count 0 2006.201.18:08:33.88#ibcon#enter sib2, iclass 34, count 0 2006.201.18:08:33.88#ibcon#flushed, iclass 34, count 0 2006.201.18:08:33.88#ibcon#about to write, iclass 34, count 0 2006.201.18:08:33.88#ibcon#wrote, iclass 34, count 0 2006.201.18:08:33.88#ibcon#about to read 3, iclass 34, count 0 2006.201.18:08:33.93#ibcon#read 3, iclass 34, count 0 2006.201.18:08:33.93#ibcon#about to read 4, iclass 34, count 0 2006.201.18:08:33.93#ibcon#read 4, iclass 34, count 0 2006.201.18:08:33.93#ibcon#about to read 5, iclass 34, count 0 2006.201.18:08:33.93#ibcon#read 5, iclass 34, count 0 2006.201.18:08:33.93#ibcon#about to read 6, iclass 34, count 0 2006.201.18:08:33.93#ibcon#read 6, iclass 34, count 0 2006.201.18:08:33.93#ibcon#end of sib2, iclass 34, count 0 2006.201.18:08:33.93#ibcon#*after write, iclass 34, count 0 2006.201.18:08:33.93#ibcon#*before return 0, iclass 34, count 0 2006.201.18:08:33.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:33.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:33.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:08:33.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:08:33.93$vck44/va=4,7 2006.201.18:08:33.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.18:08:33.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.18:08:33.93#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:33.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:33.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:33.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:33.98#ibcon#enter wrdev, iclass 36, count 2 2006.201.18:08:33.98#ibcon#first serial, iclass 36, count 2 2006.201.18:08:33.98#ibcon#enter sib2, iclass 36, count 2 2006.201.18:08:33.98#ibcon#flushed, iclass 36, count 2 2006.201.18:08:33.98#ibcon#about to write, iclass 36, count 2 2006.201.18:08:33.98#ibcon#wrote, iclass 36, count 2 2006.201.18:08:33.98#ibcon#about to read 3, iclass 36, count 2 2006.201.18:08:34.00#ibcon#read 3, iclass 36, count 2 2006.201.18:08:34.00#ibcon#about to read 4, iclass 36, count 2 2006.201.18:08:34.00#ibcon#read 4, iclass 36, count 2 2006.201.18:08:34.00#ibcon#about to read 5, iclass 36, count 2 2006.201.18:08:34.00#ibcon#read 5, iclass 36, count 2 2006.201.18:08:34.00#ibcon#about to read 6, iclass 36, count 2 2006.201.18:08:34.00#ibcon#read 6, iclass 36, count 2 2006.201.18:08:34.00#ibcon#end of sib2, iclass 36, count 2 2006.201.18:08:34.00#ibcon#*mode == 0, iclass 36, count 2 2006.201.18:08:34.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.18:08:34.00#ibcon#[25=AT04-07\r\n] 2006.201.18:08:34.00#ibcon#*before write, iclass 36, count 2 2006.201.18:08:34.00#ibcon#enter sib2, iclass 36, count 2 2006.201.18:08:34.00#ibcon#flushed, iclass 36, count 2 2006.201.18:08:34.00#ibcon#about to write, iclass 36, count 2 2006.201.18:08:34.00#ibcon#wrote, iclass 36, count 2 2006.201.18:08:34.00#ibcon#about to read 3, iclass 36, count 2 2006.201.18:08:34.03#ibcon#read 3, iclass 36, count 2 2006.201.18:08:34.03#ibcon#about to read 4, iclass 36, count 2 2006.201.18:08:34.03#ibcon#read 4, iclass 36, count 2 2006.201.18:08:34.03#ibcon#about to read 5, iclass 36, count 2 2006.201.18:08:34.03#ibcon#read 5, iclass 36, count 2 2006.201.18:08:34.03#ibcon#about to read 6, iclass 36, count 2 2006.201.18:08:34.03#ibcon#read 6, iclass 36, count 2 2006.201.18:08:34.03#ibcon#end of sib2, iclass 36, count 2 2006.201.18:08:34.03#ibcon#*after write, iclass 36, count 2 2006.201.18:08:34.03#ibcon#*before return 0, iclass 36, count 2 2006.201.18:08:34.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:34.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:34.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.18:08:34.03#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:34.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:34.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:34.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:34.15#ibcon#enter wrdev, iclass 36, count 0 2006.201.18:08:34.15#ibcon#first serial, iclass 36, count 0 2006.201.18:08:34.15#ibcon#enter sib2, iclass 36, count 0 2006.201.18:08:34.15#ibcon#flushed, iclass 36, count 0 2006.201.18:08:34.15#ibcon#about to write, iclass 36, count 0 2006.201.18:08:34.15#ibcon#wrote, iclass 36, count 0 2006.201.18:08:34.15#ibcon#about to read 3, iclass 36, count 0 2006.201.18:08:34.17#ibcon#read 3, iclass 36, count 0 2006.201.18:08:34.17#ibcon#about to read 4, iclass 36, count 0 2006.201.18:08:34.17#ibcon#read 4, iclass 36, count 0 2006.201.18:08:34.17#ibcon#about to read 5, iclass 36, count 0 2006.201.18:08:34.17#ibcon#read 5, iclass 36, count 0 2006.201.18:08:34.17#ibcon#about to read 6, iclass 36, count 0 2006.201.18:08:34.17#ibcon#read 6, iclass 36, count 0 2006.201.18:08:34.17#ibcon#end of sib2, iclass 36, count 0 2006.201.18:08:34.17#ibcon#*mode == 0, iclass 36, count 0 2006.201.18:08:34.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.18:08:34.17#ibcon#[25=USB\r\n] 2006.201.18:08:34.17#ibcon#*before write, iclass 36, count 0 2006.201.18:08:34.17#ibcon#enter sib2, iclass 36, count 0 2006.201.18:08:34.17#ibcon#flushed, iclass 36, count 0 2006.201.18:08:34.17#ibcon#about to write, iclass 36, count 0 2006.201.18:08:34.17#ibcon#wrote, iclass 36, count 0 2006.201.18:08:34.17#ibcon#about to read 3, iclass 36, count 0 2006.201.18:08:34.20#ibcon#read 3, iclass 36, count 0 2006.201.18:08:34.20#ibcon#about to read 4, iclass 36, count 0 2006.201.18:08:34.20#ibcon#read 4, iclass 36, count 0 2006.201.18:08:34.20#ibcon#about to read 5, iclass 36, count 0 2006.201.18:08:34.20#ibcon#read 5, iclass 36, count 0 2006.201.18:08:34.20#ibcon#about to read 6, iclass 36, count 0 2006.201.18:08:34.20#ibcon#read 6, iclass 36, count 0 2006.201.18:08:34.20#ibcon#end of sib2, iclass 36, count 0 2006.201.18:08:34.20#ibcon#*after write, iclass 36, count 0 2006.201.18:08:34.20#ibcon#*before return 0, iclass 36, count 0 2006.201.18:08:34.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:34.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:34.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.18:08:34.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.18:08:34.20$vck44/valo=5,734.99 2006.201.18:08:34.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.18:08:34.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.18:08:34.20#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:34.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:34.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:34.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:34.20#ibcon#enter wrdev, iclass 38, count 0 2006.201.18:08:34.20#ibcon#first serial, iclass 38, count 0 2006.201.18:08:34.20#ibcon#enter sib2, iclass 38, count 0 2006.201.18:08:34.20#ibcon#flushed, iclass 38, count 0 2006.201.18:08:34.20#ibcon#about to write, iclass 38, count 0 2006.201.18:08:34.20#ibcon#wrote, iclass 38, count 0 2006.201.18:08:34.20#ibcon#about to read 3, iclass 38, count 0 2006.201.18:08:34.22#ibcon#read 3, iclass 38, count 0 2006.201.18:08:34.22#ibcon#about to read 4, iclass 38, count 0 2006.201.18:08:34.22#ibcon#read 4, iclass 38, count 0 2006.201.18:08:34.22#ibcon#about to read 5, iclass 38, count 0 2006.201.18:08:34.22#ibcon#read 5, iclass 38, count 0 2006.201.18:08:34.22#ibcon#about to read 6, iclass 38, count 0 2006.201.18:08:34.22#ibcon#read 6, iclass 38, count 0 2006.201.18:08:34.22#ibcon#end of sib2, iclass 38, count 0 2006.201.18:08:34.22#ibcon#*mode == 0, iclass 38, count 0 2006.201.18:08:34.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.18:08:34.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:08:34.22#ibcon#*before write, iclass 38, count 0 2006.201.18:08:34.22#ibcon#enter sib2, iclass 38, count 0 2006.201.18:08:34.22#ibcon#flushed, iclass 38, count 0 2006.201.18:08:34.22#ibcon#about to write, iclass 38, count 0 2006.201.18:08:34.22#ibcon#wrote, iclass 38, count 0 2006.201.18:08:34.22#ibcon#about to read 3, iclass 38, count 0 2006.201.18:08:34.26#ibcon#read 3, iclass 38, count 0 2006.201.18:08:34.26#ibcon#about to read 4, iclass 38, count 0 2006.201.18:08:34.26#ibcon#read 4, iclass 38, count 0 2006.201.18:08:34.26#ibcon#about to read 5, iclass 38, count 0 2006.201.18:08:34.26#ibcon#read 5, iclass 38, count 0 2006.201.18:08:34.26#ibcon#about to read 6, iclass 38, count 0 2006.201.18:08:34.26#ibcon#read 6, iclass 38, count 0 2006.201.18:08:34.26#ibcon#end of sib2, iclass 38, count 0 2006.201.18:08:34.26#ibcon#*after write, iclass 38, count 0 2006.201.18:08:34.26#ibcon#*before return 0, iclass 38, count 0 2006.201.18:08:34.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:34.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:34.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.18:08:34.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.18:08:34.26$vck44/va=5,4 2006.201.18:08:34.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.18:08:34.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.18:08:34.26#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:34.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:34.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:34.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:34.32#ibcon#enter wrdev, iclass 40, count 2 2006.201.18:08:34.32#ibcon#first serial, iclass 40, count 2 2006.201.18:08:34.32#ibcon#enter sib2, iclass 40, count 2 2006.201.18:08:34.32#ibcon#flushed, iclass 40, count 2 2006.201.18:08:34.32#ibcon#about to write, iclass 40, count 2 2006.201.18:08:34.32#ibcon#wrote, iclass 40, count 2 2006.201.18:08:34.32#ibcon#about to read 3, iclass 40, count 2 2006.201.18:08:34.34#ibcon#read 3, iclass 40, count 2 2006.201.18:08:34.34#ibcon#about to read 4, iclass 40, count 2 2006.201.18:08:34.34#ibcon#read 4, iclass 40, count 2 2006.201.18:08:34.34#ibcon#about to read 5, iclass 40, count 2 2006.201.18:08:34.34#ibcon#read 5, iclass 40, count 2 2006.201.18:08:34.34#ibcon#about to read 6, iclass 40, count 2 2006.201.18:08:34.34#ibcon#read 6, iclass 40, count 2 2006.201.18:08:34.34#ibcon#end of sib2, iclass 40, count 2 2006.201.18:08:34.34#ibcon#*mode == 0, iclass 40, count 2 2006.201.18:08:34.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.18:08:34.34#ibcon#[25=AT05-04\r\n] 2006.201.18:08:34.34#ibcon#*before write, iclass 40, count 2 2006.201.18:08:34.34#ibcon#enter sib2, iclass 40, count 2 2006.201.18:08:34.34#ibcon#flushed, iclass 40, count 2 2006.201.18:08:34.34#ibcon#about to write, iclass 40, count 2 2006.201.18:08:34.34#ibcon#wrote, iclass 40, count 2 2006.201.18:08:34.34#ibcon#about to read 3, iclass 40, count 2 2006.201.18:08:34.37#ibcon#read 3, iclass 40, count 2 2006.201.18:08:34.37#ibcon#about to read 4, iclass 40, count 2 2006.201.18:08:34.37#ibcon#read 4, iclass 40, count 2 2006.201.18:08:34.37#ibcon#about to read 5, iclass 40, count 2 2006.201.18:08:34.37#ibcon#read 5, iclass 40, count 2 2006.201.18:08:34.37#ibcon#about to read 6, iclass 40, count 2 2006.201.18:08:34.37#ibcon#read 6, iclass 40, count 2 2006.201.18:08:34.37#ibcon#end of sib2, iclass 40, count 2 2006.201.18:08:34.37#ibcon#*after write, iclass 40, count 2 2006.201.18:08:34.37#ibcon#*before return 0, iclass 40, count 2 2006.201.18:08:34.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:34.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:34.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.18:08:34.37#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:34.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:34.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:34.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:34.49#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:08:34.49#ibcon#first serial, iclass 40, count 0 2006.201.18:08:34.49#ibcon#enter sib2, iclass 40, count 0 2006.201.18:08:34.49#ibcon#flushed, iclass 40, count 0 2006.201.18:08:34.49#ibcon#about to write, iclass 40, count 0 2006.201.18:08:34.49#ibcon#wrote, iclass 40, count 0 2006.201.18:08:34.49#ibcon#about to read 3, iclass 40, count 0 2006.201.18:08:34.51#ibcon#read 3, iclass 40, count 0 2006.201.18:08:34.51#ibcon#about to read 4, iclass 40, count 0 2006.201.18:08:34.51#ibcon#read 4, iclass 40, count 0 2006.201.18:08:34.51#ibcon#about to read 5, iclass 40, count 0 2006.201.18:08:34.51#ibcon#read 5, iclass 40, count 0 2006.201.18:08:34.51#ibcon#about to read 6, iclass 40, count 0 2006.201.18:08:34.51#ibcon#read 6, iclass 40, count 0 2006.201.18:08:34.51#ibcon#end of sib2, iclass 40, count 0 2006.201.18:08:34.51#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:08:34.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:08:34.51#ibcon#[25=USB\r\n] 2006.201.18:08:34.51#ibcon#*before write, iclass 40, count 0 2006.201.18:08:34.51#ibcon#enter sib2, iclass 40, count 0 2006.201.18:08:34.51#ibcon#flushed, iclass 40, count 0 2006.201.18:08:34.51#ibcon#about to write, iclass 40, count 0 2006.201.18:08:34.51#ibcon#wrote, iclass 40, count 0 2006.201.18:08:34.51#ibcon#about to read 3, iclass 40, count 0 2006.201.18:08:34.54#ibcon#read 3, iclass 40, count 0 2006.201.18:08:34.54#ibcon#about to read 4, iclass 40, count 0 2006.201.18:08:34.54#ibcon#read 4, iclass 40, count 0 2006.201.18:08:34.54#ibcon#about to read 5, iclass 40, count 0 2006.201.18:08:34.54#ibcon#read 5, iclass 40, count 0 2006.201.18:08:34.54#ibcon#about to read 6, iclass 40, count 0 2006.201.18:08:34.54#ibcon#read 6, iclass 40, count 0 2006.201.18:08:34.54#ibcon#end of sib2, iclass 40, count 0 2006.201.18:08:34.54#ibcon#*after write, iclass 40, count 0 2006.201.18:08:34.54#ibcon#*before return 0, iclass 40, count 0 2006.201.18:08:34.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:34.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:34.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:08:34.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:08:34.54$vck44/valo=6,814.99 2006.201.18:08:34.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.18:08:34.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.18:08:34.54#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:34.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:34.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:34.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:34.54#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:08:34.54#ibcon#first serial, iclass 4, count 0 2006.201.18:08:34.54#ibcon#enter sib2, iclass 4, count 0 2006.201.18:08:34.54#ibcon#flushed, iclass 4, count 0 2006.201.18:08:34.54#ibcon#about to write, iclass 4, count 0 2006.201.18:08:34.54#ibcon#wrote, iclass 4, count 0 2006.201.18:08:34.54#ibcon#about to read 3, iclass 4, count 0 2006.201.18:08:34.56#ibcon#read 3, iclass 4, count 0 2006.201.18:08:34.56#ibcon#about to read 4, iclass 4, count 0 2006.201.18:08:34.56#ibcon#read 4, iclass 4, count 0 2006.201.18:08:34.56#ibcon#about to read 5, iclass 4, count 0 2006.201.18:08:34.56#ibcon#read 5, iclass 4, count 0 2006.201.18:08:34.56#ibcon#about to read 6, iclass 4, count 0 2006.201.18:08:34.56#ibcon#read 6, iclass 4, count 0 2006.201.18:08:34.56#ibcon#end of sib2, iclass 4, count 0 2006.201.18:08:34.56#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:08:34.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:08:34.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:08:34.56#ibcon#*before write, iclass 4, count 0 2006.201.18:08:34.56#ibcon#enter sib2, iclass 4, count 0 2006.201.18:08:34.56#ibcon#flushed, iclass 4, count 0 2006.201.18:08:34.56#ibcon#about to write, iclass 4, count 0 2006.201.18:08:34.56#ibcon#wrote, iclass 4, count 0 2006.201.18:08:34.56#ibcon#about to read 3, iclass 4, count 0 2006.201.18:08:34.60#ibcon#read 3, iclass 4, count 0 2006.201.18:08:34.60#ibcon#about to read 4, iclass 4, count 0 2006.201.18:08:34.60#ibcon#read 4, iclass 4, count 0 2006.201.18:08:34.60#ibcon#about to read 5, iclass 4, count 0 2006.201.18:08:34.60#ibcon#read 5, iclass 4, count 0 2006.201.18:08:34.60#ibcon#about to read 6, iclass 4, count 0 2006.201.18:08:34.60#ibcon#read 6, iclass 4, count 0 2006.201.18:08:34.60#ibcon#end of sib2, iclass 4, count 0 2006.201.18:08:34.60#ibcon#*after write, iclass 4, count 0 2006.201.18:08:34.60#ibcon#*before return 0, iclass 4, count 0 2006.201.18:08:34.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:34.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:34.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:08:34.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:08:34.60$vck44/va=6,5 2006.201.18:08:34.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.18:08:34.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.18:08:34.60#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:34.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:34.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:34.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:34.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.18:08:34.66#ibcon#first serial, iclass 6, count 2 2006.201.18:08:34.66#ibcon#enter sib2, iclass 6, count 2 2006.201.18:08:34.66#ibcon#flushed, iclass 6, count 2 2006.201.18:08:34.66#ibcon#about to write, iclass 6, count 2 2006.201.18:08:34.66#ibcon#wrote, iclass 6, count 2 2006.201.18:08:34.66#ibcon#about to read 3, iclass 6, count 2 2006.201.18:08:34.68#ibcon#read 3, iclass 6, count 2 2006.201.18:08:34.68#ibcon#about to read 4, iclass 6, count 2 2006.201.18:08:34.68#ibcon#read 4, iclass 6, count 2 2006.201.18:08:34.68#ibcon#about to read 5, iclass 6, count 2 2006.201.18:08:34.68#ibcon#read 5, iclass 6, count 2 2006.201.18:08:34.68#ibcon#about to read 6, iclass 6, count 2 2006.201.18:08:34.68#ibcon#read 6, iclass 6, count 2 2006.201.18:08:34.68#ibcon#end of sib2, iclass 6, count 2 2006.201.18:08:34.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.18:08:34.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.18:08:34.68#ibcon#[25=AT06-05\r\n] 2006.201.18:08:34.68#ibcon#*before write, iclass 6, count 2 2006.201.18:08:34.68#ibcon#enter sib2, iclass 6, count 2 2006.201.18:08:34.68#ibcon#flushed, iclass 6, count 2 2006.201.18:08:34.68#ibcon#about to write, iclass 6, count 2 2006.201.18:08:34.68#ibcon#wrote, iclass 6, count 2 2006.201.18:08:34.68#ibcon#about to read 3, iclass 6, count 2 2006.201.18:08:34.71#ibcon#read 3, iclass 6, count 2 2006.201.18:08:34.71#ibcon#about to read 4, iclass 6, count 2 2006.201.18:08:34.71#ibcon#read 4, iclass 6, count 2 2006.201.18:08:34.71#ibcon#about to read 5, iclass 6, count 2 2006.201.18:08:34.71#ibcon#read 5, iclass 6, count 2 2006.201.18:08:34.71#ibcon#about to read 6, iclass 6, count 2 2006.201.18:08:34.71#ibcon#read 6, iclass 6, count 2 2006.201.18:08:34.71#ibcon#end of sib2, iclass 6, count 2 2006.201.18:08:34.71#ibcon#*after write, iclass 6, count 2 2006.201.18:08:34.71#ibcon#*before return 0, iclass 6, count 2 2006.201.18:08:34.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:34.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:34.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.18:08:34.71#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:34.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:34.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:34.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:34.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:08:34.83#ibcon#first serial, iclass 6, count 0 2006.201.18:08:34.83#ibcon#enter sib2, iclass 6, count 0 2006.201.18:08:34.83#ibcon#flushed, iclass 6, count 0 2006.201.18:08:34.83#ibcon#about to write, iclass 6, count 0 2006.201.18:08:34.83#ibcon#wrote, iclass 6, count 0 2006.201.18:08:34.83#ibcon#about to read 3, iclass 6, count 0 2006.201.18:08:34.85#ibcon#read 3, iclass 6, count 0 2006.201.18:08:34.85#ibcon#about to read 4, iclass 6, count 0 2006.201.18:08:34.85#ibcon#read 4, iclass 6, count 0 2006.201.18:08:34.85#ibcon#about to read 5, iclass 6, count 0 2006.201.18:08:34.85#ibcon#read 5, iclass 6, count 0 2006.201.18:08:34.85#ibcon#about to read 6, iclass 6, count 0 2006.201.18:08:34.85#ibcon#read 6, iclass 6, count 0 2006.201.18:08:34.85#ibcon#end of sib2, iclass 6, count 0 2006.201.18:08:34.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:08:34.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:08:34.85#ibcon#[25=USB\r\n] 2006.201.18:08:34.85#ibcon#*before write, iclass 6, count 0 2006.201.18:08:34.85#ibcon#enter sib2, iclass 6, count 0 2006.201.18:08:34.85#ibcon#flushed, iclass 6, count 0 2006.201.18:08:34.85#ibcon#about to write, iclass 6, count 0 2006.201.18:08:34.85#ibcon#wrote, iclass 6, count 0 2006.201.18:08:34.85#ibcon#about to read 3, iclass 6, count 0 2006.201.18:08:34.88#ibcon#read 3, iclass 6, count 0 2006.201.18:08:34.88#ibcon#about to read 4, iclass 6, count 0 2006.201.18:08:34.88#ibcon#read 4, iclass 6, count 0 2006.201.18:08:34.88#ibcon#about to read 5, iclass 6, count 0 2006.201.18:08:34.88#ibcon#read 5, iclass 6, count 0 2006.201.18:08:34.88#ibcon#about to read 6, iclass 6, count 0 2006.201.18:08:34.88#ibcon#read 6, iclass 6, count 0 2006.201.18:08:34.88#ibcon#end of sib2, iclass 6, count 0 2006.201.18:08:34.88#ibcon#*after write, iclass 6, count 0 2006.201.18:08:34.88#ibcon#*before return 0, iclass 6, count 0 2006.201.18:08:34.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:34.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:34.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:08:34.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:08:34.88$vck44/valo=7,864.99 2006.201.18:08:34.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.18:08:34.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.18:08:34.88#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:34.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:34.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:34.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:34.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:08:34.88#ibcon#first serial, iclass 10, count 0 2006.201.18:08:34.88#ibcon#enter sib2, iclass 10, count 0 2006.201.18:08:34.88#ibcon#flushed, iclass 10, count 0 2006.201.18:08:34.88#ibcon#about to write, iclass 10, count 0 2006.201.18:08:34.88#ibcon#wrote, iclass 10, count 0 2006.201.18:08:34.88#ibcon#about to read 3, iclass 10, count 0 2006.201.18:08:34.90#ibcon#read 3, iclass 10, count 0 2006.201.18:08:34.90#ibcon#about to read 4, iclass 10, count 0 2006.201.18:08:34.90#ibcon#read 4, iclass 10, count 0 2006.201.18:08:34.90#ibcon#about to read 5, iclass 10, count 0 2006.201.18:08:34.90#ibcon#read 5, iclass 10, count 0 2006.201.18:08:34.90#ibcon#about to read 6, iclass 10, count 0 2006.201.18:08:34.90#ibcon#read 6, iclass 10, count 0 2006.201.18:08:34.90#ibcon#end of sib2, iclass 10, count 0 2006.201.18:08:34.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:08:34.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:08:34.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:08:34.90#ibcon#*before write, iclass 10, count 0 2006.201.18:08:34.90#ibcon#enter sib2, iclass 10, count 0 2006.201.18:08:34.90#ibcon#flushed, iclass 10, count 0 2006.201.18:08:34.90#ibcon#about to write, iclass 10, count 0 2006.201.18:08:34.90#ibcon#wrote, iclass 10, count 0 2006.201.18:08:34.90#ibcon#about to read 3, iclass 10, count 0 2006.201.18:08:34.94#ibcon#read 3, iclass 10, count 0 2006.201.18:08:34.94#ibcon#about to read 4, iclass 10, count 0 2006.201.18:08:34.94#ibcon#read 4, iclass 10, count 0 2006.201.18:08:34.94#ibcon#about to read 5, iclass 10, count 0 2006.201.18:08:34.94#ibcon#read 5, iclass 10, count 0 2006.201.18:08:34.94#ibcon#about to read 6, iclass 10, count 0 2006.201.18:08:34.94#ibcon#read 6, iclass 10, count 0 2006.201.18:08:34.94#ibcon#end of sib2, iclass 10, count 0 2006.201.18:08:34.94#ibcon#*after write, iclass 10, count 0 2006.201.18:08:34.94#ibcon#*before return 0, iclass 10, count 0 2006.201.18:08:34.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:34.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:34.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:08:34.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:08:34.94$vck44/va=7,5 2006.201.18:08:34.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.18:08:34.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.18:08:34.94#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:34.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:35.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:35.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:35.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.18:08:35.00#ibcon#first serial, iclass 12, count 2 2006.201.18:08:35.00#ibcon#enter sib2, iclass 12, count 2 2006.201.18:08:35.00#ibcon#flushed, iclass 12, count 2 2006.201.18:08:35.00#ibcon#about to write, iclass 12, count 2 2006.201.18:08:35.00#ibcon#wrote, iclass 12, count 2 2006.201.18:08:35.00#ibcon#about to read 3, iclass 12, count 2 2006.201.18:08:35.02#ibcon#read 3, iclass 12, count 2 2006.201.18:08:35.02#ibcon#about to read 4, iclass 12, count 2 2006.201.18:08:35.02#ibcon#read 4, iclass 12, count 2 2006.201.18:08:35.02#ibcon#about to read 5, iclass 12, count 2 2006.201.18:08:35.02#ibcon#read 5, iclass 12, count 2 2006.201.18:08:35.02#ibcon#about to read 6, iclass 12, count 2 2006.201.18:08:35.02#ibcon#read 6, iclass 12, count 2 2006.201.18:08:35.02#ibcon#end of sib2, iclass 12, count 2 2006.201.18:08:35.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.18:08:35.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.18:08:35.02#ibcon#[25=AT07-05\r\n] 2006.201.18:08:35.02#ibcon#*before write, iclass 12, count 2 2006.201.18:08:35.02#ibcon#enter sib2, iclass 12, count 2 2006.201.18:08:35.02#ibcon#flushed, iclass 12, count 2 2006.201.18:08:35.02#ibcon#about to write, iclass 12, count 2 2006.201.18:08:35.02#ibcon#wrote, iclass 12, count 2 2006.201.18:08:35.02#ibcon#about to read 3, iclass 12, count 2 2006.201.18:08:35.05#ibcon#read 3, iclass 12, count 2 2006.201.18:08:35.05#ibcon#about to read 4, iclass 12, count 2 2006.201.18:08:35.05#ibcon#read 4, iclass 12, count 2 2006.201.18:08:35.05#ibcon#about to read 5, iclass 12, count 2 2006.201.18:08:35.05#ibcon#read 5, iclass 12, count 2 2006.201.18:08:35.05#ibcon#about to read 6, iclass 12, count 2 2006.201.18:08:35.05#ibcon#read 6, iclass 12, count 2 2006.201.18:08:35.05#ibcon#end of sib2, iclass 12, count 2 2006.201.18:08:35.05#ibcon#*after write, iclass 12, count 2 2006.201.18:08:35.05#ibcon#*before return 0, iclass 12, count 2 2006.201.18:08:35.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:35.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:35.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.18:08:35.05#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:35.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:35.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:35.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:35.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:08:35.17#ibcon#first serial, iclass 12, count 0 2006.201.18:08:35.17#ibcon#enter sib2, iclass 12, count 0 2006.201.18:08:35.17#ibcon#flushed, iclass 12, count 0 2006.201.18:08:35.17#ibcon#about to write, iclass 12, count 0 2006.201.18:08:35.17#ibcon#wrote, iclass 12, count 0 2006.201.18:08:35.17#ibcon#about to read 3, iclass 12, count 0 2006.201.18:08:35.20#ibcon#read 3, iclass 12, count 0 2006.201.18:08:35.20#ibcon#about to read 4, iclass 12, count 0 2006.201.18:08:35.20#ibcon#read 4, iclass 12, count 0 2006.201.18:08:35.20#ibcon#about to read 5, iclass 12, count 0 2006.201.18:08:35.20#ibcon#read 5, iclass 12, count 0 2006.201.18:08:35.20#ibcon#about to read 6, iclass 12, count 0 2006.201.18:08:35.20#ibcon#read 6, iclass 12, count 0 2006.201.18:08:35.20#ibcon#end of sib2, iclass 12, count 0 2006.201.18:08:35.20#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:08:35.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:08:35.20#ibcon#[25=USB\r\n] 2006.201.18:08:35.20#ibcon#*before write, iclass 12, count 0 2006.201.18:08:35.20#ibcon#enter sib2, iclass 12, count 0 2006.201.18:08:35.20#ibcon#flushed, iclass 12, count 0 2006.201.18:08:35.20#ibcon#about to write, iclass 12, count 0 2006.201.18:08:35.20#ibcon#wrote, iclass 12, count 0 2006.201.18:08:35.20#ibcon#about to read 3, iclass 12, count 0 2006.201.18:08:35.23#ibcon#read 3, iclass 12, count 0 2006.201.18:08:35.23#ibcon#about to read 4, iclass 12, count 0 2006.201.18:08:35.23#ibcon#read 4, iclass 12, count 0 2006.201.18:08:35.23#ibcon#about to read 5, iclass 12, count 0 2006.201.18:08:35.23#ibcon#read 5, iclass 12, count 0 2006.201.18:08:35.23#ibcon#about to read 6, iclass 12, count 0 2006.201.18:08:35.23#ibcon#read 6, iclass 12, count 0 2006.201.18:08:35.23#ibcon#end of sib2, iclass 12, count 0 2006.201.18:08:35.23#ibcon#*after write, iclass 12, count 0 2006.201.18:08:35.23#ibcon#*before return 0, iclass 12, count 0 2006.201.18:08:35.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:35.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:35.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:08:35.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:08:35.23$vck44/valo=8,884.99 2006.201.18:08:35.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.18:08:35.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.18:08:35.23#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:35.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:35.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:35.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:35.23#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:08:35.23#ibcon#first serial, iclass 14, count 0 2006.201.18:08:35.23#ibcon#enter sib2, iclass 14, count 0 2006.201.18:08:35.23#ibcon#flushed, iclass 14, count 0 2006.201.18:08:35.23#ibcon#about to write, iclass 14, count 0 2006.201.18:08:35.23#ibcon#wrote, iclass 14, count 0 2006.201.18:08:35.23#ibcon#about to read 3, iclass 14, count 0 2006.201.18:08:35.25#ibcon#read 3, iclass 14, count 0 2006.201.18:08:35.25#ibcon#about to read 4, iclass 14, count 0 2006.201.18:08:35.25#ibcon#read 4, iclass 14, count 0 2006.201.18:08:35.25#ibcon#about to read 5, iclass 14, count 0 2006.201.18:08:35.25#ibcon#read 5, iclass 14, count 0 2006.201.18:08:35.25#ibcon#about to read 6, iclass 14, count 0 2006.201.18:08:35.25#ibcon#read 6, iclass 14, count 0 2006.201.18:08:35.25#ibcon#end of sib2, iclass 14, count 0 2006.201.18:08:35.25#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:08:35.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:08:35.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:08:35.25#ibcon#*before write, iclass 14, count 0 2006.201.18:08:35.25#ibcon#enter sib2, iclass 14, count 0 2006.201.18:08:35.25#ibcon#flushed, iclass 14, count 0 2006.201.18:08:35.25#ibcon#about to write, iclass 14, count 0 2006.201.18:08:35.25#ibcon#wrote, iclass 14, count 0 2006.201.18:08:35.25#ibcon#about to read 3, iclass 14, count 0 2006.201.18:08:35.29#ibcon#read 3, iclass 14, count 0 2006.201.18:08:35.29#ibcon#about to read 4, iclass 14, count 0 2006.201.18:08:35.29#ibcon#read 4, iclass 14, count 0 2006.201.18:08:35.29#ibcon#about to read 5, iclass 14, count 0 2006.201.18:08:35.29#ibcon#read 5, iclass 14, count 0 2006.201.18:08:35.29#ibcon#about to read 6, iclass 14, count 0 2006.201.18:08:35.29#ibcon#read 6, iclass 14, count 0 2006.201.18:08:35.29#ibcon#end of sib2, iclass 14, count 0 2006.201.18:08:35.29#ibcon#*after write, iclass 14, count 0 2006.201.18:08:35.29#ibcon#*before return 0, iclass 14, count 0 2006.201.18:08:35.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:35.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:35.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:08:35.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:08:35.29$vck44/va=8,4 2006.201.18:08:35.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.18:08:35.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.18:08:35.29#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:35.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:08:35.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:08:35.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:08:35.35#ibcon#enter wrdev, iclass 16, count 2 2006.201.18:08:35.35#ibcon#first serial, iclass 16, count 2 2006.201.18:08:35.35#ibcon#enter sib2, iclass 16, count 2 2006.201.18:08:35.35#ibcon#flushed, iclass 16, count 2 2006.201.18:08:35.35#ibcon#about to write, iclass 16, count 2 2006.201.18:08:35.35#ibcon#wrote, iclass 16, count 2 2006.201.18:08:35.35#ibcon#about to read 3, iclass 16, count 2 2006.201.18:08:35.37#ibcon#read 3, iclass 16, count 2 2006.201.18:08:35.37#ibcon#about to read 4, iclass 16, count 2 2006.201.18:08:35.37#ibcon#read 4, iclass 16, count 2 2006.201.18:08:35.37#ibcon#about to read 5, iclass 16, count 2 2006.201.18:08:35.37#ibcon#read 5, iclass 16, count 2 2006.201.18:08:35.37#ibcon#about to read 6, iclass 16, count 2 2006.201.18:08:35.37#ibcon#read 6, iclass 16, count 2 2006.201.18:08:35.37#ibcon#end of sib2, iclass 16, count 2 2006.201.18:08:35.37#ibcon#*mode == 0, iclass 16, count 2 2006.201.18:08:35.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.18:08:35.37#ibcon#[25=AT08-04\r\n] 2006.201.18:08:35.37#ibcon#*before write, iclass 16, count 2 2006.201.18:08:35.37#ibcon#enter sib2, iclass 16, count 2 2006.201.18:08:35.37#ibcon#flushed, iclass 16, count 2 2006.201.18:08:35.37#ibcon#about to write, iclass 16, count 2 2006.201.18:08:35.37#ibcon#wrote, iclass 16, count 2 2006.201.18:08:35.37#ibcon#about to read 3, iclass 16, count 2 2006.201.18:08:35.40#ibcon#read 3, iclass 16, count 2 2006.201.18:08:35.40#ibcon#about to read 4, iclass 16, count 2 2006.201.18:08:35.40#ibcon#read 4, iclass 16, count 2 2006.201.18:08:35.40#ibcon#about to read 5, iclass 16, count 2 2006.201.18:08:35.40#ibcon#read 5, iclass 16, count 2 2006.201.18:08:35.40#ibcon#about to read 6, iclass 16, count 2 2006.201.18:08:35.40#ibcon#read 6, iclass 16, count 2 2006.201.18:08:35.40#ibcon#end of sib2, iclass 16, count 2 2006.201.18:08:35.40#ibcon#*after write, iclass 16, count 2 2006.201.18:08:35.40#ibcon#*before return 0, iclass 16, count 2 2006.201.18:08:35.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:08:35.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:08:35.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.18:08:35.40#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:35.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:08:35.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:08:35.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:08:35.52#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:08:35.52#ibcon#first serial, iclass 16, count 0 2006.201.18:08:35.52#ibcon#enter sib2, iclass 16, count 0 2006.201.18:08:35.52#ibcon#flushed, iclass 16, count 0 2006.201.18:08:35.52#ibcon#about to write, iclass 16, count 0 2006.201.18:08:35.52#ibcon#wrote, iclass 16, count 0 2006.201.18:08:35.52#ibcon#about to read 3, iclass 16, count 0 2006.201.18:08:35.54#ibcon#read 3, iclass 16, count 0 2006.201.18:08:35.54#ibcon#about to read 4, iclass 16, count 0 2006.201.18:08:35.54#ibcon#read 4, iclass 16, count 0 2006.201.18:08:35.54#ibcon#about to read 5, iclass 16, count 0 2006.201.18:08:35.54#ibcon#read 5, iclass 16, count 0 2006.201.18:08:35.54#ibcon#about to read 6, iclass 16, count 0 2006.201.18:08:35.54#ibcon#read 6, iclass 16, count 0 2006.201.18:08:35.54#ibcon#end of sib2, iclass 16, count 0 2006.201.18:08:35.54#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:08:35.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:08:35.54#ibcon#[25=USB\r\n] 2006.201.18:08:35.54#ibcon#*before write, iclass 16, count 0 2006.201.18:08:35.54#ibcon#enter sib2, iclass 16, count 0 2006.201.18:08:35.54#ibcon#flushed, iclass 16, count 0 2006.201.18:08:35.54#ibcon#about to write, iclass 16, count 0 2006.201.18:08:35.54#ibcon#wrote, iclass 16, count 0 2006.201.18:08:35.54#ibcon#about to read 3, iclass 16, count 0 2006.201.18:08:35.57#ibcon#read 3, iclass 16, count 0 2006.201.18:08:35.57#ibcon#about to read 4, iclass 16, count 0 2006.201.18:08:35.57#ibcon#read 4, iclass 16, count 0 2006.201.18:08:35.57#ibcon#about to read 5, iclass 16, count 0 2006.201.18:08:35.57#ibcon#read 5, iclass 16, count 0 2006.201.18:08:35.57#ibcon#about to read 6, iclass 16, count 0 2006.201.18:08:35.57#ibcon#read 6, iclass 16, count 0 2006.201.18:08:35.57#ibcon#end of sib2, iclass 16, count 0 2006.201.18:08:35.57#ibcon#*after write, iclass 16, count 0 2006.201.18:08:35.57#ibcon#*before return 0, iclass 16, count 0 2006.201.18:08:35.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:08:35.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:08:35.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:08:35.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:08:35.57$vck44/vblo=1,629.99 2006.201.18:08:35.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.18:08:35.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.18:08:35.57#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:35.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:08:35.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:08:35.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:08:35.57#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:08:35.57#ibcon#first serial, iclass 18, count 0 2006.201.18:08:35.57#ibcon#enter sib2, iclass 18, count 0 2006.201.18:08:35.57#ibcon#flushed, iclass 18, count 0 2006.201.18:08:35.57#ibcon#about to write, iclass 18, count 0 2006.201.18:08:35.57#ibcon#wrote, iclass 18, count 0 2006.201.18:08:35.57#ibcon#about to read 3, iclass 18, count 0 2006.201.18:08:35.59#ibcon#read 3, iclass 18, count 0 2006.201.18:08:35.59#ibcon#about to read 4, iclass 18, count 0 2006.201.18:08:35.59#ibcon#read 4, iclass 18, count 0 2006.201.18:08:35.59#ibcon#about to read 5, iclass 18, count 0 2006.201.18:08:35.59#ibcon#read 5, iclass 18, count 0 2006.201.18:08:35.59#ibcon#about to read 6, iclass 18, count 0 2006.201.18:08:35.59#ibcon#read 6, iclass 18, count 0 2006.201.18:08:35.59#ibcon#end of sib2, iclass 18, count 0 2006.201.18:08:35.59#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:08:35.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:08:35.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:08:35.59#ibcon#*before write, iclass 18, count 0 2006.201.18:08:35.59#ibcon#enter sib2, iclass 18, count 0 2006.201.18:08:35.59#ibcon#flushed, iclass 18, count 0 2006.201.18:08:35.59#ibcon#about to write, iclass 18, count 0 2006.201.18:08:35.59#ibcon#wrote, iclass 18, count 0 2006.201.18:08:35.59#ibcon#about to read 3, iclass 18, count 0 2006.201.18:08:35.63#ibcon#read 3, iclass 18, count 0 2006.201.18:08:35.63#ibcon#about to read 4, iclass 18, count 0 2006.201.18:08:35.63#ibcon#read 4, iclass 18, count 0 2006.201.18:08:35.63#ibcon#about to read 5, iclass 18, count 0 2006.201.18:08:35.63#ibcon#read 5, iclass 18, count 0 2006.201.18:08:35.63#ibcon#about to read 6, iclass 18, count 0 2006.201.18:08:35.63#ibcon#read 6, iclass 18, count 0 2006.201.18:08:35.63#ibcon#end of sib2, iclass 18, count 0 2006.201.18:08:35.63#ibcon#*after write, iclass 18, count 0 2006.201.18:08:35.63#ibcon#*before return 0, iclass 18, count 0 2006.201.18:08:35.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:08:35.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:08:35.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:08:35.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:08:35.63$vck44/vb=1,4 2006.201.18:08:35.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.18:08:35.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.18:08:35.63#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:35.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:08:35.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:08:35.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:08:35.63#ibcon#enter wrdev, iclass 20, count 2 2006.201.18:08:35.63#ibcon#first serial, iclass 20, count 2 2006.201.18:08:35.63#ibcon#enter sib2, iclass 20, count 2 2006.201.18:08:35.63#ibcon#flushed, iclass 20, count 2 2006.201.18:08:35.63#ibcon#about to write, iclass 20, count 2 2006.201.18:08:35.63#ibcon#wrote, iclass 20, count 2 2006.201.18:08:35.63#ibcon#about to read 3, iclass 20, count 2 2006.201.18:08:35.65#ibcon#read 3, iclass 20, count 2 2006.201.18:08:35.65#ibcon#about to read 4, iclass 20, count 2 2006.201.18:08:35.65#ibcon#read 4, iclass 20, count 2 2006.201.18:08:35.65#ibcon#about to read 5, iclass 20, count 2 2006.201.18:08:35.65#ibcon#read 5, iclass 20, count 2 2006.201.18:08:35.65#ibcon#about to read 6, iclass 20, count 2 2006.201.18:08:35.65#ibcon#read 6, iclass 20, count 2 2006.201.18:08:35.65#ibcon#end of sib2, iclass 20, count 2 2006.201.18:08:35.65#ibcon#*mode == 0, iclass 20, count 2 2006.201.18:08:35.65#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.18:08:35.65#ibcon#[27=AT01-04\r\n] 2006.201.18:08:35.65#ibcon#*before write, iclass 20, count 2 2006.201.18:08:35.65#ibcon#enter sib2, iclass 20, count 2 2006.201.18:08:35.65#ibcon#flushed, iclass 20, count 2 2006.201.18:08:35.65#ibcon#about to write, iclass 20, count 2 2006.201.18:08:35.65#ibcon#wrote, iclass 20, count 2 2006.201.18:08:35.65#ibcon#about to read 3, iclass 20, count 2 2006.201.18:08:35.68#ibcon#read 3, iclass 20, count 2 2006.201.18:08:35.68#ibcon#about to read 4, iclass 20, count 2 2006.201.18:08:35.68#ibcon#read 4, iclass 20, count 2 2006.201.18:08:35.68#ibcon#about to read 5, iclass 20, count 2 2006.201.18:08:35.68#ibcon#read 5, iclass 20, count 2 2006.201.18:08:35.68#ibcon#about to read 6, iclass 20, count 2 2006.201.18:08:35.68#ibcon#read 6, iclass 20, count 2 2006.201.18:08:35.68#ibcon#end of sib2, iclass 20, count 2 2006.201.18:08:35.68#ibcon#*after write, iclass 20, count 2 2006.201.18:08:35.68#ibcon#*before return 0, iclass 20, count 2 2006.201.18:08:35.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:08:35.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:08:35.68#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.18:08:35.68#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:35.68#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:08:35.80#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:08:35.80#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:08:35.80#ibcon#enter wrdev, iclass 20, count 0 2006.201.18:08:35.80#ibcon#first serial, iclass 20, count 0 2006.201.18:08:35.80#ibcon#enter sib2, iclass 20, count 0 2006.201.18:08:35.80#ibcon#flushed, iclass 20, count 0 2006.201.18:08:35.80#ibcon#about to write, iclass 20, count 0 2006.201.18:08:35.80#ibcon#wrote, iclass 20, count 0 2006.201.18:08:35.80#ibcon#about to read 3, iclass 20, count 0 2006.201.18:08:35.82#ibcon#read 3, iclass 20, count 0 2006.201.18:08:35.82#ibcon#about to read 4, iclass 20, count 0 2006.201.18:08:35.82#ibcon#read 4, iclass 20, count 0 2006.201.18:08:35.82#ibcon#about to read 5, iclass 20, count 0 2006.201.18:08:35.82#ibcon#read 5, iclass 20, count 0 2006.201.18:08:35.82#ibcon#about to read 6, iclass 20, count 0 2006.201.18:08:35.82#ibcon#read 6, iclass 20, count 0 2006.201.18:08:35.82#ibcon#end of sib2, iclass 20, count 0 2006.201.18:08:35.82#ibcon#*mode == 0, iclass 20, count 0 2006.201.18:08:35.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.18:08:35.82#ibcon#[27=USB\r\n] 2006.201.18:08:35.82#ibcon#*before write, iclass 20, count 0 2006.201.18:08:35.82#ibcon#enter sib2, iclass 20, count 0 2006.201.18:08:35.82#ibcon#flushed, iclass 20, count 0 2006.201.18:08:35.82#ibcon#about to write, iclass 20, count 0 2006.201.18:08:35.82#ibcon#wrote, iclass 20, count 0 2006.201.18:08:35.82#ibcon#about to read 3, iclass 20, count 0 2006.201.18:08:35.85#ibcon#read 3, iclass 20, count 0 2006.201.18:08:35.85#ibcon#about to read 4, iclass 20, count 0 2006.201.18:08:35.85#ibcon#read 4, iclass 20, count 0 2006.201.18:08:35.85#ibcon#about to read 5, iclass 20, count 0 2006.201.18:08:35.85#ibcon#read 5, iclass 20, count 0 2006.201.18:08:35.85#ibcon#about to read 6, iclass 20, count 0 2006.201.18:08:35.85#ibcon#read 6, iclass 20, count 0 2006.201.18:08:35.85#ibcon#end of sib2, iclass 20, count 0 2006.201.18:08:35.85#ibcon#*after write, iclass 20, count 0 2006.201.18:08:35.85#ibcon#*before return 0, iclass 20, count 0 2006.201.18:08:35.85#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:08:35.85#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:08:35.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.18:08:35.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.18:08:35.85$vck44/vblo=2,634.99 2006.201.18:08:35.85#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.18:08:35.85#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.18:08:35.85#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:35.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:35.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:35.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:35.85#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:08:35.85#ibcon#first serial, iclass 22, count 0 2006.201.18:08:35.85#ibcon#enter sib2, iclass 22, count 0 2006.201.18:08:35.85#ibcon#flushed, iclass 22, count 0 2006.201.18:08:35.85#ibcon#about to write, iclass 22, count 0 2006.201.18:08:35.85#ibcon#wrote, iclass 22, count 0 2006.201.18:08:35.85#ibcon#about to read 3, iclass 22, count 0 2006.201.18:08:35.87#ibcon#read 3, iclass 22, count 0 2006.201.18:08:35.87#ibcon#about to read 4, iclass 22, count 0 2006.201.18:08:35.87#ibcon#read 4, iclass 22, count 0 2006.201.18:08:35.87#ibcon#about to read 5, iclass 22, count 0 2006.201.18:08:35.87#ibcon#read 5, iclass 22, count 0 2006.201.18:08:35.87#ibcon#about to read 6, iclass 22, count 0 2006.201.18:08:35.87#ibcon#read 6, iclass 22, count 0 2006.201.18:08:35.87#ibcon#end of sib2, iclass 22, count 0 2006.201.18:08:35.87#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:08:35.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:08:35.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:08:35.87#ibcon#*before write, iclass 22, count 0 2006.201.18:08:35.87#ibcon#enter sib2, iclass 22, count 0 2006.201.18:08:35.87#ibcon#flushed, iclass 22, count 0 2006.201.18:08:35.87#ibcon#about to write, iclass 22, count 0 2006.201.18:08:35.87#ibcon#wrote, iclass 22, count 0 2006.201.18:08:35.87#ibcon#about to read 3, iclass 22, count 0 2006.201.18:08:35.91#ibcon#read 3, iclass 22, count 0 2006.201.18:08:35.91#ibcon#about to read 4, iclass 22, count 0 2006.201.18:08:35.91#ibcon#read 4, iclass 22, count 0 2006.201.18:08:35.91#ibcon#about to read 5, iclass 22, count 0 2006.201.18:08:35.91#ibcon#read 5, iclass 22, count 0 2006.201.18:08:35.91#ibcon#about to read 6, iclass 22, count 0 2006.201.18:08:35.91#ibcon#read 6, iclass 22, count 0 2006.201.18:08:35.91#ibcon#end of sib2, iclass 22, count 0 2006.201.18:08:35.91#ibcon#*after write, iclass 22, count 0 2006.201.18:08:35.91#ibcon#*before return 0, iclass 22, count 0 2006.201.18:08:35.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:35.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:08:35.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:08:35.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:08:35.91$vck44/vb=2,5 2006.201.18:08:35.91#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.18:08:35.91#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.18:08:35.91#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:35.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:35.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:35.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:35.97#ibcon#enter wrdev, iclass 24, count 2 2006.201.18:08:35.97#ibcon#first serial, iclass 24, count 2 2006.201.18:08:35.97#ibcon#enter sib2, iclass 24, count 2 2006.201.18:08:35.97#ibcon#flushed, iclass 24, count 2 2006.201.18:08:35.97#ibcon#about to write, iclass 24, count 2 2006.201.18:08:35.97#ibcon#wrote, iclass 24, count 2 2006.201.18:08:35.97#ibcon#about to read 3, iclass 24, count 2 2006.201.18:08:35.99#ibcon#read 3, iclass 24, count 2 2006.201.18:08:35.99#ibcon#about to read 4, iclass 24, count 2 2006.201.18:08:35.99#ibcon#read 4, iclass 24, count 2 2006.201.18:08:35.99#ibcon#about to read 5, iclass 24, count 2 2006.201.18:08:35.99#ibcon#read 5, iclass 24, count 2 2006.201.18:08:35.99#ibcon#about to read 6, iclass 24, count 2 2006.201.18:08:35.99#ibcon#read 6, iclass 24, count 2 2006.201.18:08:35.99#ibcon#end of sib2, iclass 24, count 2 2006.201.18:08:35.99#ibcon#*mode == 0, iclass 24, count 2 2006.201.18:08:35.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.18:08:35.99#ibcon#[27=AT02-05\r\n] 2006.201.18:08:35.99#ibcon#*before write, iclass 24, count 2 2006.201.18:08:35.99#ibcon#enter sib2, iclass 24, count 2 2006.201.18:08:35.99#ibcon#flushed, iclass 24, count 2 2006.201.18:08:35.99#ibcon#about to write, iclass 24, count 2 2006.201.18:08:35.99#ibcon#wrote, iclass 24, count 2 2006.201.18:08:35.99#ibcon#about to read 3, iclass 24, count 2 2006.201.18:08:36.02#ibcon#read 3, iclass 24, count 2 2006.201.18:08:36.02#ibcon#about to read 4, iclass 24, count 2 2006.201.18:08:36.02#ibcon#read 4, iclass 24, count 2 2006.201.18:08:36.02#ibcon#about to read 5, iclass 24, count 2 2006.201.18:08:36.02#ibcon#read 5, iclass 24, count 2 2006.201.18:08:36.02#ibcon#about to read 6, iclass 24, count 2 2006.201.18:08:36.02#ibcon#read 6, iclass 24, count 2 2006.201.18:08:36.02#ibcon#end of sib2, iclass 24, count 2 2006.201.18:08:36.02#ibcon#*after write, iclass 24, count 2 2006.201.18:08:36.02#ibcon#*before return 0, iclass 24, count 2 2006.201.18:08:36.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:36.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:08:36.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.18:08:36.02#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:36.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:36.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:36.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:36.14#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:08:36.14#ibcon#first serial, iclass 24, count 0 2006.201.18:08:36.14#ibcon#enter sib2, iclass 24, count 0 2006.201.18:08:36.14#ibcon#flushed, iclass 24, count 0 2006.201.18:08:36.14#ibcon#about to write, iclass 24, count 0 2006.201.18:08:36.14#ibcon#wrote, iclass 24, count 0 2006.201.18:08:36.14#ibcon#about to read 3, iclass 24, count 0 2006.201.18:08:36.16#ibcon#read 3, iclass 24, count 0 2006.201.18:08:36.16#ibcon#about to read 4, iclass 24, count 0 2006.201.18:08:36.16#ibcon#read 4, iclass 24, count 0 2006.201.18:08:36.16#ibcon#about to read 5, iclass 24, count 0 2006.201.18:08:36.16#ibcon#read 5, iclass 24, count 0 2006.201.18:08:36.16#ibcon#about to read 6, iclass 24, count 0 2006.201.18:08:36.16#ibcon#read 6, iclass 24, count 0 2006.201.18:08:36.16#ibcon#end of sib2, iclass 24, count 0 2006.201.18:08:36.16#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:08:36.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:08:36.16#ibcon#[27=USB\r\n] 2006.201.18:08:36.16#ibcon#*before write, iclass 24, count 0 2006.201.18:08:36.16#ibcon#enter sib2, iclass 24, count 0 2006.201.18:08:36.16#ibcon#flushed, iclass 24, count 0 2006.201.18:08:36.16#ibcon#about to write, iclass 24, count 0 2006.201.18:08:36.16#ibcon#wrote, iclass 24, count 0 2006.201.18:08:36.16#ibcon#about to read 3, iclass 24, count 0 2006.201.18:08:36.19#ibcon#read 3, iclass 24, count 0 2006.201.18:08:36.19#ibcon#about to read 4, iclass 24, count 0 2006.201.18:08:36.19#ibcon#read 4, iclass 24, count 0 2006.201.18:08:36.19#ibcon#about to read 5, iclass 24, count 0 2006.201.18:08:36.19#ibcon#read 5, iclass 24, count 0 2006.201.18:08:36.19#ibcon#about to read 6, iclass 24, count 0 2006.201.18:08:36.19#ibcon#read 6, iclass 24, count 0 2006.201.18:08:36.19#ibcon#end of sib2, iclass 24, count 0 2006.201.18:08:36.19#ibcon#*after write, iclass 24, count 0 2006.201.18:08:36.19#ibcon#*before return 0, iclass 24, count 0 2006.201.18:08:36.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:36.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:08:36.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:08:36.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:08:36.19$vck44/vblo=3,649.99 2006.201.18:08:36.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.18:08:36.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.18:08:36.19#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:36.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:36.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:36.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:36.19#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:08:36.19#ibcon#first serial, iclass 26, count 0 2006.201.18:08:36.19#ibcon#enter sib2, iclass 26, count 0 2006.201.18:08:36.19#ibcon#flushed, iclass 26, count 0 2006.201.18:08:36.19#ibcon#about to write, iclass 26, count 0 2006.201.18:08:36.19#ibcon#wrote, iclass 26, count 0 2006.201.18:08:36.19#ibcon#about to read 3, iclass 26, count 0 2006.201.18:08:36.21#ibcon#read 3, iclass 26, count 0 2006.201.18:08:36.21#ibcon#about to read 4, iclass 26, count 0 2006.201.18:08:36.21#ibcon#read 4, iclass 26, count 0 2006.201.18:08:36.21#ibcon#about to read 5, iclass 26, count 0 2006.201.18:08:36.21#ibcon#read 5, iclass 26, count 0 2006.201.18:08:36.21#ibcon#about to read 6, iclass 26, count 0 2006.201.18:08:36.21#ibcon#read 6, iclass 26, count 0 2006.201.18:08:36.21#ibcon#end of sib2, iclass 26, count 0 2006.201.18:08:36.21#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:08:36.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:08:36.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:08:36.21#ibcon#*before write, iclass 26, count 0 2006.201.18:08:36.21#ibcon#enter sib2, iclass 26, count 0 2006.201.18:08:36.21#ibcon#flushed, iclass 26, count 0 2006.201.18:08:36.21#ibcon#about to write, iclass 26, count 0 2006.201.18:08:36.21#ibcon#wrote, iclass 26, count 0 2006.201.18:08:36.21#ibcon#about to read 3, iclass 26, count 0 2006.201.18:08:36.25#ibcon#read 3, iclass 26, count 0 2006.201.18:08:36.25#ibcon#about to read 4, iclass 26, count 0 2006.201.18:08:36.25#ibcon#read 4, iclass 26, count 0 2006.201.18:08:36.25#ibcon#about to read 5, iclass 26, count 0 2006.201.18:08:36.25#ibcon#read 5, iclass 26, count 0 2006.201.18:08:36.25#ibcon#about to read 6, iclass 26, count 0 2006.201.18:08:36.25#ibcon#read 6, iclass 26, count 0 2006.201.18:08:36.25#ibcon#end of sib2, iclass 26, count 0 2006.201.18:08:36.25#ibcon#*after write, iclass 26, count 0 2006.201.18:08:36.25#ibcon#*before return 0, iclass 26, count 0 2006.201.18:08:36.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:36.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:08:36.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:08:36.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:08:36.25$vck44/vb=3,4 2006.201.18:08:36.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.18:08:36.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.18:08:36.25#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:36.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:36.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:36.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:36.31#ibcon#enter wrdev, iclass 28, count 2 2006.201.18:08:36.31#ibcon#first serial, iclass 28, count 2 2006.201.18:08:36.31#ibcon#enter sib2, iclass 28, count 2 2006.201.18:08:36.31#ibcon#flushed, iclass 28, count 2 2006.201.18:08:36.31#ibcon#about to write, iclass 28, count 2 2006.201.18:08:36.31#ibcon#wrote, iclass 28, count 2 2006.201.18:08:36.31#ibcon#about to read 3, iclass 28, count 2 2006.201.18:08:36.33#ibcon#read 3, iclass 28, count 2 2006.201.18:08:36.33#ibcon#about to read 4, iclass 28, count 2 2006.201.18:08:36.33#ibcon#read 4, iclass 28, count 2 2006.201.18:08:36.33#ibcon#about to read 5, iclass 28, count 2 2006.201.18:08:36.33#ibcon#read 5, iclass 28, count 2 2006.201.18:08:36.33#ibcon#about to read 6, iclass 28, count 2 2006.201.18:08:36.33#ibcon#read 6, iclass 28, count 2 2006.201.18:08:36.33#ibcon#end of sib2, iclass 28, count 2 2006.201.18:08:36.33#ibcon#*mode == 0, iclass 28, count 2 2006.201.18:08:36.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.18:08:36.33#ibcon#[27=AT03-04\r\n] 2006.201.18:08:36.33#ibcon#*before write, iclass 28, count 2 2006.201.18:08:36.33#ibcon#enter sib2, iclass 28, count 2 2006.201.18:08:36.33#ibcon#flushed, iclass 28, count 2 2006.201.18:08:36.33#ibcon#about to write, iclass 28, count 2 2006.201.18:08:36.33#ibcon#wrote, iclass 28, count 2 2006.201.18:08:36.33#ibcon#about to read 3, iclass 28, count 2 2006.201.18:08:36.36#ibcon#read 3, iclass 28, count 2 2006.201.18:08:36.36#ibcon#about to read 4, iclass 28, count 2 2006.201.18:08:36.36#ibcon#read 4, iclass 28, count 2 2006.201.18:08:36.36#ibcon#about to read 5, iclass 28, count 2 2006.201.18:08:36.36#ibcon#read 5, iclass 28, count 2 2006.201.18:08:36.36#ibcon#about to read 6, iclass 28, count 2 2006.201.18:08:36.36#ibcon#read 6, iclass 28, count 2 2006.201.18:08:36.36#ibcon#end of sib2, iclass 28, count 2 2006.201.18:08:36.36#ibcon#*after write, iclass 28, count 2 2006.201.18:08:36.36#ibcon#*before return 0, iclass 28, count 2 2006.201.18:08:36.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:36.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:08:36.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.18:08:36.36#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:36.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:36.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:36.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:36.48#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:08:36.48#ibcon#first serial, iclass 28, count 0 2006.201.18:08:36.48#ibcon#enter sib2, iclass 28, count 0 2006.201.18:08:36.48#ibcon#flushed, iclass 28, count 0 2006.201.18:08:36.48#ibcon#about to write, iclass 28, count 0 2006.201.18:08:36.48#ibcon#wrote, iclass 28, count 0 2006.201.18:08:36.48#ibcon#about to read 3, iclass 28, count 0 2006.201.18:08:36.50#ibcon#read 3, iclass 28, count 0 2006.201.18:08:36.50#ibcon#about to read 4, iclass 28, count 0 2006.201.18:08:36.50#ibcon#read 4, iclass 28, count 0 2006.201.18:08:36.50#ibcon#about to read 5, iclass 28, count 0 2006.201.18:08:36.50#ibcon#read 5, iclass 28, count 0 2006.201.18:08:36.50#ibcon#about to read 6, iclass 28, count 0 2006.201.18:08:36.50#ibcon#read 6, iclass 28, count 0 2006.201.18:08:36.50#ibcon#end of sib2, iclass 28, count 0 2006.201.18:08:36.50#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:08:36.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:08:36.50#ibcon#[27=USB\r\n] 2006.201.18:08:36.50#ibcon#*before write, iclass 28, count 0 2006.201.18:08:36.50#ibcon#enter sib2, iclass 28, count 0 2006.201.18:08:36.50#ibcon#flushed, iclass 28, count 0 2006.201.18:08:36.50#ibcon#about to write, iclass 28, count 0 2006.201.18:08:36.50#ibcon#wrote, iclass 28, count 0 2006.201.18:08:36.50#ibcon#about to read 3, iclass 28, count 0 2006.201.18:08:36.53#ibcon#read 3, iclass 28, count 0 2006.201.18:08:36.53#ibcon#about to read 4, iclass 28, count 0 2006.201.18:08:36.53#ibcon#read 4, iclass 28, count 0 2006.201.18:08:36.53#ibcon#about to read 5, iclass 28, count 0 2006.201.18:08:36.53#ibcon#read 5, iclass 28, count 0 2006.201.18:08:36.53#ibcon#about to read 6, iclass 28, count 0 2006.201.18:08:36.53#ibcon#read 6, iclass 28, count 0 2006.201.18:08:36.53#ibcon#end of sib2, iclass 28, count 0 2006.201.18:08:36.53#ibcon#*after write, iclass 28, count 0 2006.201.18:08:36.53#ibcon#*before return 0, iclass 28, count 0 2006.201.18:08:36.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:36.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:08:36.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:08:36.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:08:36.53$vck44/vblo=4,679.99 2006.201.18:08:36.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.18:08:36.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.18:08:36.53#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:36.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:36.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:36.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:36.53#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:08:36.53#ibcon#first serial, iclass 30, count 0 2006.201.18:08:36.53#ibcon#enter sib2, iclass 30, count 0 2006.201.18:08:36.53#ibcon#flushed, iclass 30, count 0 2006.201.18:08:36.53#ibcon#about to write, iclass 30, count 0 2006.201.18:08:36.53#ibcon#wrote, iclass 30, count 0 2006.201.18:08:36.53#ibcon#about to read 3, iclass 30, count 0 2006.201.18:08:36.55#ibcon#read 3, iclass 30, count 0 2006.201.18:08:36.55#ibcon#about to read 4, iclass 30, count 0 2006.201.18:08:36.55#ibcon#read 4, iclass 30, count 0 2006.201.18:08:36.55#ibcon#about to read 5, iclass 30, count 0 2006.201.18:08:36.55#ibcon#read 5, iclass 30, count 0 2006.201.18:08:36.55#ibcon#about to read 6, iclass 30, count 0 2006.201.18:08:36.55#ibcon#read 6, iclass 30, count 0 2006.201.18:08:36.55#ibcon#end of sib2, iclass 30, count 0 2006.201.18:08:36.55#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:08:36.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:08:36.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:08:36.55#ibcon#*before write, iclass 30, count 0 2006.201.18:08:36.55#ibcon#enter sib2, iclass 30, count 0 2006.201.18:08:36.55#ibcon#flushed, iclass 30, count 0 2006.201.18:08:36.55#ibcon#about to write, iclass 30, count 0 2006.201.18:08:36.55#ibcon#wrote, iclass 30, count 0 2006.201.18:08:36.55#ibcon#about to read 3, iclass 30, count 0 2006.201.18:08:36.59#ibcon#read 3, iclass 30, count 0 2006.201.18:08:36.59#ibcon#about to read 4, iclass 30, count 0 2006.201.18:08:36.59#ibcon#read 4, iclass 30, count 0 2006.201.18:08:36.59#ibcon#about to read 5, iclass 30, count 0 2006.201.18:08:36.59#ibcon#read 5, iclass 30, count 0 2006.201.18:08:36.59#ibcon#about to read 6, iclass 30, count 0 2006.201.18:08:36.59#ibcon#read 6, iclass 30, count 0 2006.201.18:08:36.59#ibcon#end of sib2, iclass 30, count 0 2006.201.18:08:36.59#ibcon#*after write, iclass 30, count 0 2006.201.18:08:36.59#ibcon#*before return 0, iclass 30, count 0 2006.201.18:08:36.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:36.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:08:36.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:08:36.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:08:36.59$vck44/vb=4,5 2006.201.18:08:36.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.18:08:36.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.18:08:36.59#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:36.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:36.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:36.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:36.65#ibcon#enter wrdev, iclass 32, count 2 2006.201.18:08:36.65#ibcon#first serial, iclass 32, count 2 2006.201.18:08:36.65#ibcon#enter sib2, iclass 32, count 2 2006.201.18:08:36.65#ibcon#flushed, iclass 32, count 2 2006.201.18:08:36.65#ibcon#about to write, iclass 32, count 2 2006.201.18:08:36.65#ibcon#wrote, iclass 32, count 2 2006.201.18:08:36.65#ibcon#about to read 3, iclass 32, count 2 2006.201.18:08:36.67#ibcon#read 3, iclass 32, count 2 2006.201.18:08:36.67#ibcon#about to read 4, iclass 32, count 2 2006.201.18:08:36.67#ibcon#read 4, iclass 32, count 2 2006.201.18:08:36.67#ibcon#about to read 5, iclass 32, count 2 2006.201.18:08:36.67#ibcon#read 5, iclass 32, count 2 2006.201.18:08:36.67#ibcon#about to read 6, iclass 32, count 2 2006.201.18:08:36.67#ibcon#read 6, iclass 32, count 2 2006.201.18:08:36.67#ibcon#end of sib2, iclass 32, count 2 2006.201.18:08:36.67#ibcon#*mode == 0, iclass 32, count 2 2006.201.18:08:36.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.18:08:36.67#ibcon#[27=AT04-05\r\n] 2006.201.18:08:36.67#ibcon#*before write, iclass 32, count 2 2006.201.18:08:36.67#ibcon#enter sib2, iclass 32, count 2 2006.201.18:08:36.67#ibcon#flushed, iclass 32, count 2 2006.201.18:08:36.67#ibcon#about to write, iclass 32, count 2 2006.201.18:08:36.67#ibcon#wrote, iclass 32, count 2 2006.201.18:08:36.67#ibcon#about to read 3, iclass 32, count 2 2006.201.18:08:36.70#ibcon#read 3, iclass 32, count 2 2006.201.18:08:36.70#ibcon#about to read 4, iclass 32, count 2 2006.201.18:08:36.70#ibcon#read 4, iclass 32, count 2 2006.201.18:08:36.70#ibcon#about to read 5, iclass 32, count 2 2006.201.18:08:36.70#ibcon#read 5, iclass 32, count 2 2006.201.18:08:36.70#ibcon#about to read 6, iclass 32, count 2 2006.201.18:08:36.70#ibcon#read 6, iclass 32, count 2 2006.201.18:08:36.70#ibcon#end of sib2, iclass 32, count 2 2006.201.18:08:36.70#ibcon#*after write, iclass 32, count 2 2006.201.18:08:36.70#ibcon#*before return 0, iclass 32, count 2 2006.201.18:08:36.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:36.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:08:36.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.18:08:36.70#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:36.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:36.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:36.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:36.82#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:08:36.82#ibcon#first serial, iclass 32, count 0 2006.201.18:08:36.82#ibcon#enter sib2, iclass 32, count 0 2006.201.18:08:36.82#ibcon#flushed, iclass 32, count 0 2006.201.18:08:36.82#ibcon#about to write, iclass 32, count 0 2006.201.18:08:36.82#ibcon#wrote, iclass 32, count 0 2006.201.18:08:36.82#ibcon#about to read 3, iclass 32, count 0 2006.201.18:08:36.84#ibcon#read 3, iclass 32, count 0 2006.201.18:08:36.84#ibcon#about to read 4, iclass 32, count 0 2006.201.18:08:36.84#ibcon#read 4, iclass 32, count 0 2006.201.18:08:36.84#ibcon#about to read 5, iclass 32, count 0 2006.201.18:08:36.84#ibcon#read 5, iclass 32, count 0 2006.201.18:08:36.84#ibcon#about to read 6, iclass 32, count 0 2006.201.18:08:36.84#ibcon#read 6, iclass 32, count 0 2006.201.18:08:36.84#ibcon#end of sib2, iclass 32, count 0 2006.201.18:08:36.84#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:08:36.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:08:36.84#ibcon#[27=USB\r\n] 2006.201.18:08:36.84#ibcon#*before write, iclass 32, count 0 2006.201.18:08:36.84#ibcon#enter sib2, iclass 32, count 0 2006.201.18:08:36.84#ibcon#flushed, iclass 32, count 0 2006.201.18:08:36.84#ibcon#about to write, iclass 32, count 0 2006.201.18:08:36.84#ibcon#wrote, iclass 32, count 0 2006.201.18:08:36.84#ibcon#about to read 3, iclass 32, count 0 2006.201.18:08:36.87#ibcon#read 3, iclass 32, count 0 2006.201.18:08:36.87#ibcon#about to read 4, iclass 32, count 0 2006.201.18:08:36.87#ibcon#read 4, iclass 32, count 0 2006.201.18:08:36.87#ibcon#about to read 5, iclass 32, count 0 2006.201.18:08:36.87#ibcon#read 5, iclass 32, count 0 2006.201.18:08:36.87#ibcon#about to read 6, iclass 32, count 0 2006.201.18:08:36.87#ibcon#read 6, iclass 32, count 0 2006.201.18:08:36.87#ibcon#end of sib2, iclass 32, count 0 2006.201.18:08:36.87#ibcon#*after write, iclass 32, count 0 2006.201.18:08:36.87#ibcon#*before return 0, iclass 32, count 0 2006.201.18:08:36.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:36.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:08:36.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:08:36.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:08:36.87$vck44/vblo=5,709.99 2006.201.18:08:36.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.18:08:36.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.18:08:36.87#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:36.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:36.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:36.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:36.87#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:08:36.87#ibcon#first serial, iclass 34, count 0 2006.201.18:08:36.87#ibcon#enter sib2, iclass 34, count 0 2006.201.18:08:36.87#ibcon#flushed, iclass 34, count 0 2006.201.18:08:36.87#ibcon#about to write, iclass 34, count 0 2006.201.18:08:36.87#ibcon#wrote, iclass 34, count 0 2006.201.18:08:36.87#ibcon#about to read 3, iclass 34, count 0 2006.201.18:08:36.89#ibcon#read 3, iclass 34, count 0 2006.201.18:08:36.89#ibcon#about to read 4, iclass 34, count 0 2006.201.18:08:36.89#ibcon#read 4, iclass 34, count 0 2006.201.18:08:36.89#ibcon#about to read 5, iclass 34, count 0 2006.201.18:08:36.89#ibcon#read 5, iclass 34, count 0 2006.201.18:08:36.89#ibcon#about to read 6, iclass 34, count 0 2006.201.18:08:36.89#ibcon#read 6, iclass 34, count 0 2006.201.18:08:36.89#ibcon#end of sib2, iclass 34, count 0 2006.201.18:08:36.89#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:08:36.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:08:36.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:08:36.89#ibcon#*before write, iclass 34, count 0 2006.201.18:08:36.89#ibcon#enter sib2, iclass 34, count 0 2006.201.18:08:36.89#ibcon#flushed, iclass 34, count 0 2006.201.18:08:36.89#ibcon#about to write, iclass 34, count 0 2006.201.18:08:36.89#ibcon#wrote, iclass 34, count 0 2006.201.18:08:36.89#ibcon#about to read 3, iclass 34, count 0 2006.201.18:08:36.94#ibcon#read 3, iclass 34, count 0 2006.201.18:08:36.94#ibcon#about to read 4, iclass 34, count 0 2006.201.18:08:36.94#ibcon#read 4, iclass 34, count 0 2006.201.18:08:36.94#ibcon#about to read 5, iclass 34, count 0 2006.201.18:08:36.94#ibcon#read 5, iclass 34, count 0 2006.201.18:08:36.94#ibcon#about to read 6, iclass 34, count 0 2006.201.18:08:36.94#ibcon#read 6, iclass 34, count 0 2006.201.18:08:36.94#ibcon#end of sib2, iclass 34, count 0 2006.201.18:08:36.94#ibcon#*after write, iclass 34, count 0 2006.201.18:08:36.94#ibcon#*before return 0, iclass 34, count 0 2006.201.18:08:36.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:36.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:08:36.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:08:36.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:08:36.94$vck44/vb=5,4 2006.201.18:08:36.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.18:08:36.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.18:08:36.94#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:36.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:36.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:36.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:36.99#ibcon#enter wrdev, iclass 36, count 2 2006.201.18:08:36.99#ibcon#first serial, iclass 36, count 2 2006.201.18:08:36.99#ibcon#enter sib2, iclass 36, count 2 2006.201.18:08:36.99#ibcon#flushed, iclass 36, count 2 2006.201.18:08:36.99#ibcon#about to write, iclass 36, count 2 2006.201.18:08:36.99#ibcon#wrote, iclass 36, count 2 2006.201.18:08:36.99#ibcon#about to read 3, iclass 36, count 2 2006.201.18:08:37.01#ibcon#read 3, iclass 36, count 2 2006.201.18:08:37.01#ibcon#about to read 4, iclass 36, count 2 2006.201.18:08:37.01#ibcon#read 4, iclass 36, count 2 2006.201.18:08:37.01#ibcon#about to read 5, iclass 36, count 2 2006.201.18:08:37.01#ibcon#read 5, iclass 36, count 2 2006.201.18:08:37.01#ibcon#about to read 6, iclass 36, count 2 2006.201.18:08:37.01#ibcon#read 6, iclass 36, count 2 2006.201.18:08:37.01#ibcon#end of sib2, iclass 36, count 2 2006.201.18:08:37.01#ibcon#*mode == 0, iclass 36, count 2 2006.201.18:08:37.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.18:08:37.01#ibcon#[27=AT05-04\r\n] 2006.201.18:08:37.01#ibcon#*before write, iclass 36, count 2 2006.201.18:08:37.01#ibcon#enter sib2, iclass 36, count 2 2006.201.18:08:37.01#ibcon#flushed, iclass 36, count 2 2006.201.18:08:37.01#ibcon#about to write, iclass 36, count 2 2006.201.18:08:37.01#ibcon#wrote, iclass 36, count 2 2006.201.18:08:37.01#ibcon#about to read 3, iclass 36, count 2 2006.201.18:08:37.04#ibcon#read 3, iclass 36, count 2 2006.201.18:08:37.04#ibcon#about to read 4, iclass 36, count 2 2006.201.18:08:37.04#ibcon#read 4, iclass 36, count 2 2006.201.18:08:37.04#ibcon#about to read 5, iclass 36, count 2 2006.201.18:08:37.04#ibcon#read 5, iclass 36, count 2 2006.201.18:08:37.04#ibcon#about to read 6, iclass 36, count 2 2006.201.18:08:37.04#ibcon#read 6, iclass 36, count 2 2006.201.18:08:37.04#ibcon#end of sib2, iclass 36, count 2 2006.201.18:08:37.04#ibcon#*after write, iclass 36, count 2 2006.201.18:08:37.04#ibcon#*before return 0, iclass 36, count 2 2006.201.18:08:37.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:37.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:08:37.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.18:08:37.04#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:37.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:37.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:37.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:37.16#ibcon#enter wrdev, iclass 36, count 0 2006.201.18:08:37.16#ibcon#first serial, iclass 36, count 0 2006.201.18:08:37.16#ibcon#enter sib2, iclass 36, count 0 2006.201.18:08:37.16#ibcon#flushed, iclass 36, count 0 2006.201.18:08:37.16#ibcon#about to write, iclass 36, count 0 2006.201.18:08:37.16#ibcon#wrote, iclass 36, count 0 2006.201.18:08:37.16#ibcon#about to read 3, iclass 36, count 0 2006.201.18:08:37.18#ibcon#read 3, iclass 36, count 0 2006.201.18:08:37.18#ibcon#about to read 4, iclass 36, count 0 2006.201.18:08:37.18#ibcon#read 4, iclass 36, count 0 2006.201.18:08:37.18#ibcon#about to read 5, iclass 36, count 0 2006.201.18:08:37.18#ibcon#read 5, iclass 36, count 0 2006.201.18:08:37.18#ibcon#about to read 6, iclass 36, count 0 2006.201.18:08:37.18#ibcon#read 6, iclass 36, count 0 2006.201.18:08:37.18#ibcon#end of sib2, iclass 36, count 0 2006.201.18:08:37.18#ibcon#*mode == 0, iclass 36, count 0 2006.201.18:08:37.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.18:08:37.18#ibcon#[27=USB\r\n] 2006.201.18:08:37.18#ibcon#*before write, iclass 36, count 0 2006.201.18:08:37.18#ibcon#enter sib2, iclass 36, count 0 2006.201.18:08:37.18#ibcon#flushed, iclass 36, count 0 2006.201.18:08:37.18#ibcon#about to write, iclass 36, count 0 2006.201.18:08:37.18#ibcon#wrote, iclass 36, count 0 2006.201.18:08:37.18#ibcon#about to read 3, iclass 36, count 0 2006.201.18:08:37.21#ibcon#read 3, iclass 36, count 0 2006.201.18:08:37.21#ibcon#about to read 4, iclass 36, count 0 2006.201.18:08:37.21#ibcon#read 4, iclass 36, count 0 2006.201.18:08:37.21#ibcon#about to read 5, iclass 36, count 0 2006.201.18:08:37.21#ibcon#read 5, iclass 36, count 0 2006.201.18:08:37.21#ibcon#about to read 6, iclass 36, count 0 2006.201.18:08:37.21#ibcon#read 6, iclass 36, count 0 2006.201.18:08:37.21#ibcon#end of sib2, iclass 36, count 0 2006.201.18:08:37.21#ibcon#*after write, iclass 36, count 0 2006.201.18:08:37.21#ibcon#*before return 0, iclass 36, count 0 2006.201.18:08:37.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:37.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:08:37.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.18:08:37.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.18:08:37.21$vck44/vblo=6,719.99 2006.201.18:08:37.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.18:08:37.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.18:08:37.21#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:37.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:37.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:37.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:37.21#ibcon#enter wrdev, iclass 38, count 0 2006.201.18:08:37.21#ibcon#first serial, iclass 38, count 0 2006.201.18:08:37.21#ibcon#enter sib2, iclass 38, count 0 2006.201.18:08:37.21#ibcon#flushed, iclass 38, count 0 2006.201.18:08:37.21#ibcon#about to write, iclass 38, count 0 2006.201.18:08:37.21#ibcon#wrote, iclass 38, count 0 2006.201.18:08:37.21#ibcon#about to read 3, iclass 38, count 0 2006.201.18:08:37.23#ibcon#read 3, iclass 38, count 0 2006.201.18:08:37.23#ibcon#about to read 4, iclass 38, count 0 2006.201.18:08:37.23#ibcon#read 4, iclass 38, count 0 2006.201.18:08:37.23#ibcon#about to read 5, iclass 38, count 0 2006.201.18:08:37.23#ibcon#read 5, iclass 38, count 0 2006.201.18:08:37.23#ibcon#about to read 6, iclass 38, count 0 2006.201.18:08:37.23#ibcon#read 6, iclass 38, count 0 2006.201.18:08:37.23#ibcon#end of sib2, iclass 38, count 0 2006.201.18:08:37.23#ibcon#*mode == 0, iclass 38, count 0 2006.201.18:08:37.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.18:08:37.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:08:37.23#ibcon#*before write, iclass 38, count 0 2006.201.18:08:37.23#ibcon#enter sib2, iclass 38, count 0 2006.201.18:08:37.23#ibcon#flushed, iclass 38, count 0 2006.201.18:08:37.23#ibcon#about to write, iclass 38, count 0 2006.201.18:08:37.23#ibcon#wrote, iclass 38, count 0 2006.201.18:08:37.23#ibcon#about to read 3, iclass 38, count 0 2006.201.18:08:37.27#ibcon#read 3, iclass 38, count 0 2006.201.18:08:37.27#ibcon#about to read 4, iclass 38, count 0 2006.201.18:08:37.27#ibcon#read 4, iclass 38, count 0 2006.201.18:08:37.27#ibcon#about to read 5, iclass 38, count 0 2006.201.18:08:37.27#ibcon#read 5, iclass 38, count 0 2006.201.18:08:37.27#ibcon#about to read 6, iclass 38, count 0 2006.201.18:08:37.27#ibcon#read 6, iclass 38, count 0 2006.201.18:08:37.27#ibcon#end of sib2, iclass 38, count 0 2006.201.18:08:37.27#ibcon#*after write, iclass 38, count 0 2006.201.18:08:37.27#ibcon#*before return 0, iclass 38, count 0 2006.201.18:08:37.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:37.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:08:37.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.18:08:37.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.18:08:37.27$vck44/vb=6,4 2006.201.18:08:37.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.18:08:37.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.18:08:37.27#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:37.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:37.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:37.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:37.33#ibcon#enter wrdev, iclass 40, count 2 2006.201.18:08:37.33#ibcon#first serial, iclass 40, count 2 2006.201.18:08:37.33#ibcon#enter sib2, iclass 40, count 2 2006.201.18:08:37.33#ibcon#flushed, iclass 40, count 2 2006.201.18:08:37.33#ibcon#about to write, iclass 40, count 2 2006.201.18:08:37.33#ibcon#wrote, iclass 40, count 2 2006.201.18:08:37.33#ibcon#about to read 3, iclass 40, count 2 2006.201.18:08:37.35#ibcon#read 3, iclass 40, count 2 2006.201.18:08:37.35#ibcon#about to read 4, iclass 40, count 2 2006.201.18:08:37.35#ibcon#read 4, iclass 40, count 2 2006.201.18:08:37.35#ibcon#about to read 5, iclass 40, count 2 2006.201.18:08:37.35#ibcon#read 5, iclass 40, count 2 2006.201.18:08:37.35#ibcon#about to read 6, iclass 40, count 2 2006.201.18:08:37.35#ibcon#read 6, iclass 40, count 2 2006.201.18:08:37.35#ibcon#end of sib2, iclass 40, count 2 2006.201.18:08:37.35#ibcon#*mode == 0, iclass 40, count 2 2006.201.18:08:37.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.18:08:37.35#ibcon#[27=AT06-04\r\n] 2006.201.18:08:37.35#ibcon#*before write, iclass 40, count 2 2006.201.18:08:37.35#ibcon#enter sib2, iclass 40, count 2 2006.201.18:08:37.35#ibcon#flushed, iclass 40, count 2 2006.201.18:08:37.35#ibcon#about to write, iclass 40, count 2 2006.201.18:08:37.35#ibcon#wrote, iclass 40, count 2 2006.201.18:08:37.35#ibcon#about to read 3, iclass 40, count 2 2006.201.18:08:37.38#ibcon#read 3, iclass 40, count 2 2006.201.18:08:37.38#ibcon#about to read 4, iclass 40, count 2 2006.201.18:08:37.38#ibcon#read 4, iclass 40, count 2 2006.201.18:08:37.38#ibcon#about to read 5, iclass 40, count 2 2006.201.18:08:37.38#ibcon#read 5, iclass 40, count 2 2006.201.18:08:37.38#ibcon#about to read 6, iclass 40, count 2 2006.201.18:08:37.38#ibcon#read 6, iclass 40, count 2 2006.201.18:08:37.38#ibcon#end of sib2, iclass 40, count 2 2006.201.18:08:37.38#ibcon#*after write, iclass 40, count 2 2006.201.18:08:37.38#ibcon#*before return 0, iclass 40, count 2 2006.201.18:08:37.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:37.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:08:37.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.18:08:37.38#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:37.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:37.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:37.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:37.50#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:08:37.50#ibcon#first serial, iclass 40, count 0 2006.201.18:08:37.50#ibcon#enter sib2, iclass 40, count 0 2006.201.18:08:37.50#ibcon#flushed, iclass 40, count 0 2006.201.18:08:37.50#ibcon#about to write, iclass 40, count 0 2006.201.18:08:37.50#ibcon#wrote, iclass 40, count 0 2006.201.18:08:37.50#ibcon#about to read 3, iclass 40, count 0 2006.201.18:08:37.52#ibcon#read 3, iclass 40, count 0 2006.201.18:08:37.52#ibcon#about to read 4, iclass 40, count 0 2006.201.18:08:37.52#ibcon#read 4, iclass 40, count 0 2006.201.18:08:37.52#ibcon#about to read 5, iclass 40, count 0 2006.201.18:08:37.52#ibcon#read 5, iclass 40, count 0 2006.201.18:08:37.52#ibcon#about to read 6, iclass 40, count 0 2006.201.18:08:37.52#ibcon#read 6, iclass 40, count 0 2006.201.18:08:37.52#ibcon#end of sib2, iclass 40, count 0 2006.201.18:08:37.52#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:08:37.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:08:37.52#ibcon#[27=USB\r\n] 2006.201.18:08:37.52#ibcon#*before write, iclass 40, count 0 2006.201.18:08:37.52#ibcon#enter sib2, iclass 40, count 0 2006.201.18:08:37.52#ibcon#flushed, iclass 40, count 0 2006.201.18:08:37.52#ibcon#about to write, iclass 40, count 0 2006.201.18:08:37.52#ibcon#wrote, iclass 40, count 0 2006.201.18:08:37.52#ibcon#about to read 3, iclass 40, count 0 2006.201.18:08:37.55#ibcon#read 3, iclass 40, count 0 2006.201.18:08:37.55#ibcon#about to read 4, iclass 40, count 0 2006.201.18:08:37.55#ibcon#read 4, iclass 40, count 0 2006.201.18:08:37.55#ibcon#about to read 5, iclass 40, count 0 2006.201.18:08:37.55#ibcon#read 5, iclass 40, count 0 2006.201.18:08:37.55#ibcon#about to read 6, iclass 40, count 0 2006.201.18:08:37.55#ibcon#read 6, iclass 40, count 0 2006.201.18:08:37.55#ibcon#end of sib2, iclass 40, count 0 2006.201.18:08:37.55#ibcon#*after write, iclass 40, count 0 2006.201.18:08:37.55#ibcon#*before return 0, iclass 40, count 0 2006.201.18:08:37.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:37.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:08:37.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:08:37.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:08:37.55$vck44/vblo=7,734.99 2006.201.18:08:37.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.18:08:37.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.18:08:37.55#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:37.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:37.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:37.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:37.55#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:08:37.55#ibcon#first serial, iclass 4, count 0 2006.201.18:08:37.55#ibcon#enter sib2, iclass 4, count 0 2006.201.18:08:37.55#ibcon#flushed, iclass 4, count 0 2006.201.18:08:37.55#ibcon#about to write, iclass 4, count 0 2006.201.18:08:37.55#ibcon#wrote, iclass 4, count 0 2006.201.18:08:37.55#ibcon#about to read 3, iclass 4, count 0 2006.201.18:08:37.57#ibcon#read 3, iclass 4, count 0 2006.201.18:08:37.57#ibcon#about to read 4, iclass 4, count 0 2006.201.18:08:37.57#ibcon#read 4, iclass 4, count 0 2006.201.18:08:37.57#ibcon#about to read 5, iclass 4, count 0 2006.201.18:08:37.57#ibcon#read 5, iclass 4, count 0 2006.201.18:08:37.57#ibcon#about to read 6, iclass 4, count 0 2006.201.18:08:37.57#ibcon#read 6, iclass 4, count 0 2006.201.18:08:37.57#ibcon#end of sib2, iclass 4, count 0 2006.201.18:08:37.57#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:08:37.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:08:37.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:08:37.57#ibcon#*before write, iclass 4, count 0 2006.201.18:08:37.57#ibcon#enter sib2, iclass 4, count 0 2006.201.18:08:37.57#ibcon#flushed, iclass 4, count 0 2006.201.18:08:37.57#ibcon#about to write, iclass 4, count 0 2006.201.18:08:37.57#ibcon#wrote, iclass 4, count 0 2006.201.18:08:37.57#ibcon#about to read 3, iclass 4, count 0 2006.201.18:08:37.62#ibcon#read 3, iclass 4, count 0 2006.201.18:08:37.62#ibcon#about to read 4, iclass 4, count 0 2006.201.18:08:37.62#ibcon#read 4, iclass 4, count 0 2006.201.18:08:37.62#ibcon#about to read 5, iclass 4, count 0 2006.201.18:08:37.62#ibcon#read 5, iclass 4, count 0 2006.201.18:08:37.62#ibcon#about to read 6, iclass 4, count 0 2006.201.18:08:37.62#ibcon#read 6, iclass 4, count 0 2006.201.18:08:37.62#ibcon#end of sib2, iclass 4, count 0 2006.201.18:08:37.62#ibcon#*after write, iclass 4, count 0 2006.201.18:08:37.62#ibcon#*before return 0, iclass 4, count 0 2006.201.18:08:37.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:37.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:08:37.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:08:37.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:08:37.62$vck44/vb=7,4 2006.201.18:08:37.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.18:08:37.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.18:08:37.62#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:37.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:37.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:37.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:37.67#ibcon#enter wrdev, iclass 6, count 2 2006.201.18:08:37.67#ibcon#first serial, iclass 6, count 2 2006.201.18:08:37.67#ibcon#enter sib2, iclass 6, count 2 2006.201.18:08:37.67#ibcon#flushed, iclass 6, count 2 2006.201.18:08:37.67#ibcon#about to write, iclass 6, count 2 2006.201.18:08:37.67#ibcon#wrote, iclass 6, count 2 2006.201.18:08:37.67#ibcon#about to read 3, iclass 6, count 2 2006.201.18:08:37.69#ibcon#read 3, iclass 6, count 2 2006.201.18:08:37.69#ibcon#about to read 4, iclass 6, count 2 2006.201.18:08:37.69#ibcon#read 4, iclass 6, count 2 2006.201.18:08:37.69#ibcon#about to read 5, iclass 6, count 2 2006.201.18:08:37.69#ibcon#read 5, iclass 6, count 2 2006.201.18:08:37.69#ibcon#about to read 6, iclass 6, count 2 2006.201.18:08:37.69#ibcon#read 6, iclass 6, count 2 2006.201.18:08:37.69#ibcon#end of sib2, iclass 6, count 2 2006.201.18:08:37.69#ibcon#*mode == 0, iclass 6, count 2 2006.201.18:08:37.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.18:08:37.69#ibcon#[27=AT07-04\r\n] 2006.201.18:08:37.69#ibcon#*before write, iclass 6, count 2 2006.201.18:08:37.69#ibcon#enter sib2, iclass 6, count 2 2006.201.18:08:37.69#ibcon#flushed, iclass 6, count 2 2006.201.18:08:37.69#ibcon#about to write, iclass 6, count 2 2006.201.18:08:37.69#ibcon#wrote, iclass 6, count 2 2006.201.18:08:37.69#ibcon#about to read 3, iclass 6, count 2 2006.201.18:08:37.72#ibcon#read 3, iclass 6, count 2 2006.201.18:08:37.72#ibcon#about to read 4, iclass 6, count 2 2006.201.18:08:37.72#ibcon#read 4, iclass 6, count 2 2006.201.18:08:37.72#ibcon#about to read 5, iclass 6, count 2 2006.201.18:08:37.72#ibcon#read 5, iclass 6, count 2 2006.201.18:08:37.72#ibcon#about to read 6, iclass 6, count 2 2006.201.18:08:37.72#ibcon#read 6, iclass 6, count 2 2006.201.18:08:37.72#ibcon#end of sib2, iclass 6, count 2 2006.201.18:08:37.72#ibcon#*after write, iclass 6, count 2 2006.201.18:08:37.72#ibcon#*before return 0, iclass 6, count 2 2006.201.18:08:37.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:37.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:08:37.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.18:08:37.72#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:37.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:37.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:37.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:37.84#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:08:37.84#ibcon#first serial, iclass 6, count 0 2006.201.18:08:37.84#ibcon#enter sib2, iclass 6, count 0 2006.201.18:08:37.84#ibcon#flushed, iclass 6, count 0 2006.201.18:08:37.84#ibcon#about to write, iclass 6, count 0 2006.201.18:08:37.84#ibcon#wrote, iclass 6, count 0 2006.201.18:08:37.84#ibcon#about to read 3, iclass 6, count 0 2006.201.18:08:37.86#ibcon#read 3, iclass 6, count 0 2006.201.18:08:37.86#ibcon#about to read 4, iclass 6, count 0 2006.201.18:08:37.86#ibcon#read 4, iclass 6, count 0 2006.201.18:08:37.86#ibcon#about to read 5, iclass 6, count 0 2006.201.18:08:37.86#ibcon#read 5, iclass 6, count 0 2006.201.18:08:37.86#ibcon#about to read 6, iclass 6, count 0 2006.201.18:08:37.86#ibcon#read 6, iclass 6, count 0 2006.201.18:08:37.86#ibcon#end of sib2, iclass 6, count 0 2006.201.18:08:37.86#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:08:37.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:08:37.86#ibcon#[27=USB\r\n] 2006.201.18:08:37.86#ibcon#*before write, iclass 6, count 0 2006.201.18:08:37.86#ibcon#enter sib2, iclass 6, count 0 2006.201.18:08:37.86#ibcon#flushed, iclass 6, count 0 2006.201.18:08:37.86#ibcon#about to write, iclass 6, count 0 2006.201.18:08:37.86#ibcon#wrote, iclass 6, count 0 2006.201.18:08:37.86#ibcon#about to read 3, iclass 6, count 0 2006.201.18:08:37.89#ibcon#read 3, iclass 6, count 0 2006.201.18:08:37.89#ibcon#about to read 4, iclass 6, count 0 2006.201.18:08:37.89#ibcon#read 4, iclass 6, count 0 2006.201.18:08:37.89#ibcon#about to read 5, iclass 6, count 0 2006.201.18:08:37.89#ibcon#read 5, iclass 6, count 0 2006.201.18:08:37.89#ibcon#about to read 6, iclass 6, count 0 2006.201.18:08:37.89#ibcon#read 6, iclass 6, count 0 2006.201.18:08:37.89#ibcon#end of sib2, iclass 6, count 0 2006.201.18:08:37.89#ibcon#*after write, iclass 6, count 0 2006.201.18:08:37.89#ibcon#*before return 0, iclass 6, count 0 2006.201.18:08:37.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:37.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:08:37.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:08:37.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:08:37.89$vck44/vblo=8,744.99 2006.201.18:08:37.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.18:08:37.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.18:08:37.89#ibcon#ireg 17 cls_cnt 0 2006.201.18:08:37.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:37.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:37.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:37.89#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:08:37.89#ibcon#first serial, iclass 10, count 0 2006.201.18:08:37.89#ibcon#enter sib2, iclass 10, count 0 2006.201.18:08:37.89#ibcon#flushed, iclass 10, count 0 2006.201.18:08:37.89#ibcon#about to write, iclass 10, count 0 2006.201.18:08:37.89#ibcon#wrote, iclass 10, count 0 2006.201.18:08:37.89#ibcon#about to read 3, iclass 10, count 0 2006.201.18:08:37.91#ibcon#read 3, iclass 10, count 0 2006.201.18:08:37.91#ibcon#about to read 4, iclass 10, count 0 2006.201.18:08:37.91#ibcon#read 4, iclass 10, count 0 2006.201.18:08:37.91#ibcon#about to read 5, iclass 10, count 0 2006.201.18:08:37.91#ibcon#read 5, iclass 10, count 0 2006.201.18:08:37.91#ibcon#about to read 6, iclass 10, count 0 2006.201.18:08:37.91#ibcon#read 6, iclass 10, count 0 2006.201.18:08:37.91#ibcon#end of sib2, iclass 10, count 0 2006.201.18:08:37.91#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:08:37.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:08:37.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:08:37.91#ibcon#*before write, iclass 10, count 0 2006.201.18:08:37.91#ibcon#enter sib2, iclass 10, count 0 2006.201.18:08:37.91#ibcon#flushed, iclass 10, count 0 2006.201.18:08:37.91#ibcon#about to write, iclass 10, count 0 2006.201.18:08:37.91#ibcon#wrote, iclass 10, count 0 2006.201.18:08:37.91#ibcon#about to read 3, iclass 10, count 0 2006.201.18:08:37.95#ibcon#read 3, iclass 10, count 0 2006.201.18:08:37.95#ibcon#about to read 4, iclass 10, count 0 2006.201.18:08:37.95#ibcon#read 4, iclass 10, count 0 2006.201.18:08:37.95#ibcon#about to read 5, iclass 10, count 0 2006.201.18:08:37.95#ibcon#read 5, iclass 10, count 0 2006.201.18:08:37.95#ibcon#about to read 6, iclass 10, count 0 2006.201.18:08:37.95#ibcon#read 6, iclass 10, count 0 2006.201.18:08:37.95#ibcon#end of sib2, iclass 10, count 0 2006.201.18:08:37.95#ibcon#*after write, iclass 10, count 0 2006.201.18:08:37.95#ibcon#*before return 0, iclass 10, count 0 2006.201.18:08:37.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:37.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:08:37.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:08:37.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:08:37.95$vck44/vb=8,4 2006.201.18:08:37.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.18:08:37.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.18:08:37.95#ibcon#ireg 11 cls_cnt 2 2006.201.18:08:37.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:38.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:38.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:38.01#ibcon#enter wrdev, iclass 12, count 2 2006.201.18:08:38.01#ibcon#first serial, iclass 12, count 2 2006.201.18:08:38.01#ibcon#enter sib2, iclass 12, count 2 2006.201.18:08:38.01#ibcon#flushed, iclass 12, count 2 2006.201.18:08:38.01#ibcon#about to write, iclass 12, count 2 2006.201.18:08:38.01#ibcon#wrote, iclass 12, count 2 2006.201.18:08:38.01#ibcon#about to read 3, iclass 12, count 2 2006.201.18:08:38.03#ibcon#read 3, iclass 12, count 2 2006.201.18:08:38.03#ibcon#about to read 4, iclass 12, count 2 2006.201.18:08:38.03#ibcon#read 4, iclass 12, count 2 2006.201.18:08:38.03#ibcon#about to read 5, iclass 12, count 2 2006.201.18:08:38.03#ibcon#read 5, iclass 12, count 2 2006.201.18:08:38.03#ibcon#about to read 6, iclass 12, count 2 2006.201.18:08:38.03#ibcon#read 6, iclass 12, count 2 2006.201.18:08:38.03#ibcon#end of sib2, iclass 12, count 2 2006.201.18:08:38.03#ibcon#*mode == 0, iclass 12, count 2 2006.201.18:08:38.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.18:08:38.03#ibcon#[27=AT08-04\r\n] 2006.201.18:08:38.03#ibcon#*before write, iclass 12, count 2 2006.201.18:08:38.03#ibcon#enter sib2, iclass 12, count 2 2006.201.18:08:38.03#ibcon#flushed, iclass 12, count 2 2006.201.18:08:38.03#ibcon#about to write, iclass 12, count 2 2006.201.18:08:38.03#ibcon#wrote, iclass 12, count 2 2006.201.18:08:38.03#ibcon#about to read 3, iclass 12, count 2 2006.201.18:08:38.06#ibcon#read 3, iclass 12, count 2 2006.201.18:08:38.06#ibcon#about to read 4, iclass 12, count 2 2006.201.18:08:38.06#ibcon#read 4, iclass 12, count 2 2006.201.18:08:38.06#ibcon#about to read 5, iclass 12, count 2 2006.201.18:08:38.06#ibcon#read 5, iclass 12, count 2 2006.201.18:08:38.06#ibcon#about to read 6, iclass 12, count 2 2006.201.18:08:38.06#ibcon#read 6, iclass 12, count 2 2006.201.18:08:38.06#ibcon#end of sib2, iclass 12, count 2 2006.201.18:08:38.06#ibcon#*after write, iclass 12, count 2 2006.201.18:08:38.06#ibcon#*before return 0, iclass 12, count 2 2006.201.18:08:38.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:38.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:08:38.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.18:08:38.06#ibcon#ireg 7 cls_cnt 0 2006.201.18:08:38.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:38.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:38.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:38.18#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:08:38.18#ibcon#first serial, iclass 12, count 0 2006.201.18:08:38.18#ibcon#enter sib2, iclass 12, count 0 2006.201.18:08:38.18#ibcon#flushed, iclass 12, count 0 2006.201.18:08:38.18#ibcon#about to write, iclass 12, count 0 2006.201.18:08:38.18#ibcon#wrote, iclass 12, count 0 2006.201.18:08:38.18#ibcon#about to read 3, iclass 12, count 0 2006.201.18:08:38.20#ibcon#read 3, iclass 12, count 0 2006.201.18:08:38.20#ibcon#about to read 4, iclass 12, count 0 2006.201.18:08:38.20#ibcon#read 4, iclass 12, count 0 2006.201.18:08:38.20#ibcon#about to read 5, iclass 12, count 0 2006.201.18:08:38.20#ibcon#read 5, iclass 12, count 0 2006.201.18:08:38.20#ibcon#about to read 6, iclass 12, count 0 2006.201.18:08:38.20#ibcon#read 6, iclass 12, count 0 2006.201.18:08:38.20#ibcon#end of sib2, iclass 12, count 0 2006.201.18:08:38.20#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:08:38.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:08:38.20#ibcon#[27=USB\r\n] 2006.201.18:08:38.20#ibcon#*before write, iclass 12, count 0 2006.201.18:08:38.20#ibcon#enter sib2, iclass 12, count 0 2006.201.18:08:38.20#ibcon#flushed, iclass 12, count 0 2006.201.18:08:38.20#ibcon#about to write, iclass 12, count 0 2006.201.18:08:38.20#ibcon#wrote, iclass 12, count 0 2006.201.18:08:38.20#ibcon#about to read 3, iclass 12, count 0 2006.201.18:08:38.23#ibcon#read 3, iclass 12, count 0 2006.201.18:08:38.23#ibcon#about to read 4, iclass 12, count 0 2006.201.18:08:38.23#ibcon#read 4, iclass 12, count 0 2006.201.18:08:38.23#ibcon#about to read 5, iclass 12, count 0 2006.201.18:08:38.23#ibcon#read 5, iclass 12, count 0 2006.201.18:08:38.23#ibcon#about to read 6, iclass 12, count 0 2006.201.18:08:38.23#ibcon#read 6, iclass 12, count 0 2006.201.18:08:38.23#ibcon#end of sib2, iclass 12, count 0 2006.201.18:08:38.23#ibcon#*after write, iclass 12, count 0 2006.201.18:08:38.23#ibcon#*before return 0, iclass 12, count 0 2006.201.18:08:38.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:38.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:08:38.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:08:38.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:08:38.23$vck44/vabw=wide 2006.201.18:08:38.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.18:08:38.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.18:08:38.23#ibcon#ireg 8 cls_cnt 0 2006.201.18:08:38.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:38.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:38.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:38.23#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:08:38.23#ibcon#first serial, iclass 14, count 0 2006.201.18:08:38.23#ibcon#enter sib2, iclass 14, count 0 2006.201.18:08:38.23#ibcon#flushed, iclass 14, count 0 2006.201.18:08:38.23#ibcon#about to write, iclass 14, count 0 2006.201.18:08:38.23#ibcon#wrote, iclass 14, count 0 2006.201.18:08:38.23#ibcon#about to read 3, iclass 14, count 0 2006.201.18:08:38.25#ibcon#read 3, iclass 14, count 0 2006.201.18:08:38.25#ibcon#about to read 4, iclass 14, count 0 2006.201.18:08:38.25#ibcon#read 4, iclass 14, count 0 2006.201.18:08:38.25#ibcon#about to read 5, iclass 14, count 0 2006.201.18:08:38.25#ibcon#read 5, iclass 14, count 0 2006.201.18:08:38.25#ibcon#about to read 6, iclass 14, count 0 2006.201.18:08:38.25#ibcon#read 6, iclass 14, count 0 2006.201.18:08:38.25#ibcon#end of sib2, iclass 14, count 0 2006.201.18:08:38.25#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:08:38.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:08:38.25#ibcon#[25=BW32\r\n] 2006.201.18:08:38.25#ibcon#*before write, iclass 14, count 0 2006.201.18:08:38.25#ibcon#enter sib2, iclass 14, count 0 2006.201.18:08:38.25#ibcon#flushed, iclass 14, count 0 2006.201.18:08:38.25#ibcon#about to write, iclass 14, count 0 2006.201.18:08:38.25#ibcon#wrote, iclass 14, count 0 2006.201.18:08:38.25#ibcon#about to read 3, iclass 14, count 0 2006.201.18:08:38.28#ibcon#read 3, iclass 14, count 0 2006.201.18:08:38.28#ibcon#about to read 4, iclass 14, count 0 2006.201.18:08:38.28#ibcon#read 4, iclass 14, count 0 2006.201.18:08:38.28#ibcon#about to read 5, iclass 14, count 0 2006.201.18:08:38.28#ibcon#read 5, iclass 14, count 0 2006.201.18:08:38.28#ibcon#about to read 6, iclass 14, count 0 2006.201.18:08:38.28#ibcon#read 6, iclass 14, count 0 2006.201.18:08:38.28#ibcon#end of sib2, iclass 14, count 0 2006.201.18:08:38.28#ibcon#*after write, iclass 14, count 0 2006.201.18:08:38.28#ibcon#*before return 0, iclass 14, count 0 2006.201.18:08:38.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:38.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:08:38.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:08:38.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:08:38.28$vck44/vbbw=wide 2006.201.18:08:38.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.18:08:38.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.18:08:38.28#ibcon#ireg 8 cls_cnt 0 2006.201.18:08:38.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:08:38.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:08:38.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:08:38.35#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:08:38.35#ibcon#first serial, iclass 16, count 0 2006.201.18:08:38.35#ibcon#enter sib2, iclass 16, count 0 2006.201.18:08:38.35#ibcon#flushed, iclass 16, count 0 2006.201.18:08:38.35#ibcon#about to write, iclass 16, count 0 2006.201.18:08:38.35#ibcon#wrote, iclass 16, count 0 2006.201.18:08:38.35#ibcon#about to read 3, iclass 16, count 0 2006.201.18:08:38.37#ibcon#read 3, iclass 16, count 0 2006.201.18:08:38.37#ibcon#about to read 4, iclass 16, count 0 2006.201.18:08:38.37#ibcon#read 4, iclass 16, count 0 2006.201.18:08:38.37#ibcon#about to read 5, iclass 16, count 0 2006.201.18:08:38.37#ibcon#read 5, iclass 16, count 0 2006.201.18:08:38.37#ibcon#about to read 6, iclass 16, count 0 2006.201.18:08:38.37#ibcon#read 6, iclass 16, count 0 2006.201.18:08:38.37#ibcon#end of sib2, iclass 16, count 0 2006.201.18:08:38.37#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:08:38.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:08:38.37#ibcon#[27=BW32\r\n] 2006.201.18:08:38.37#ibcon#*before write, iclass 16, count 0 2006.201.18:08:38.37#ibcon#enter sib2, iclass 16, count 0 2006.201.18:08:38.37#ibcon#flushed, iclass 16, count 0 2006.201.18:08:38.37#ibcon#about to write, iclass 16, count 0 2006.201.18:08:38.37#ibcon#wrote, iclass 16, count 0 2006.201.18:08:38.37#ibcon#about to read 3, iclass 16, count 0 2006.201.18:08:38.40#ibcon#read 3, iclass 16, count 0 2006.201.18:08:38.40#ibcon#about to read 4, iclass 16, count 0 2006.201.18:08:38.40#ibcon#read 4, iclass 16, count 0 2006.201.18:08:38.40#ibcon#about to read 5, iclass 16, count 0 2006.201.18:08:38.40#ibcon#read 5, iclass 16, count 0 2006.201.18:08:38.40#ibcon#about to read 6, iclass 16, count 0 2006.201.18:08:38.40#ibcon#read 6, iclass 16, count 0 2006.201.18:08:38.40#ibcon#end of sib2, iclass 16, count 0 2006.201.18:08:38.40#ibcon#*after write, iclass 16, count 0 2006.201.18:08:38.40#ibcon#*before return 0, iclass 16, count 0 2006.201.18:08:38.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:08:38.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:08:38.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:08:38.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:08:38.40$setupk4/ifdk4 2006.201.18:08:38.40$ifdk4/lo= 2006.201.18:08:38.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:08:38.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:08:38.40$ifdk4/patch= 2006.201.18:08:38.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:08:38.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:08:38.40$setupk4/!*+20s 2006.201.18:08:42.15#abcon#<5=/16 0.8 1.5 20.511001002.2\r\n> 2006.201.18:08:42.17#abcon#{5=INTERFACE CLEAR} 2006.201.18:08:42.23#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:08:52.14#trakl#Source acquired 2006.201.18:08:52.32#abcon#<5=/16 0.7 1.4 20.511001002.2\r\n> 2006.201.18:08:52.34#abcon#{5=INTERFACE CLEAR} 2006.201.18:08:52.40#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:08:52.88$setupk4/"tpicd 2006.201.18:08:52.88$setupk4/echo=off 2006.201.18:08:52.88$setupk4/xlog=off 2006.201.18:08:52.88:!2006.201.18:14:00 2006.201.18:08:53.14#flagr#flagr/antenna,acquired 2006.201.18:14:00.00:preob 2006.201.18:14:00.14/onsource/TRACKING 2006.201.18:14:00.14:!2006.201.18:14:10 2006.201.18:14:10.00:"tape 2006.201.18:14:10.00:"st=record 2006.201.18:14:10.00:data_valid=on 2006.201.18:14:10.00:midob 2006.201.18:14:11.14/onsource/TRACKING 2006.201.18:14:11.14/wx/20.50,1002.2,100 2006.201.18:14:11.29/cable/+6.4773E-03 2006.201.18:14:12.38/va/01,08,usb,yes,36,39 2006.201.18:14:12.38/va/02,07,usb,yes,39,40 2006.201.18:14:12.38/va/03,08,usb,yes,35,37 2006.201.18:14:12.38/va/04,07,usb,yes,40,42 2006.201.18:14:12.38/va/05,04,usb,yes,36,36 2006.201.18:14:12.38/va/06,05,usb,yes,36,36 2006.201.18:14:12.38/va/07,05,usb,yes,35,36 2006.201.18:14:12.38/va/08,04,usb,yes,35,41 2006.201.18:14:12.61/valo/01,524.99,yes,locked 2006.201.18:14:12.61/valo/02,534.99,yes,locked 2006.201.18:14:12.61/valo/03,564.99,yes,locked 2006.201.18:14:12.61/valo/04,624.99,yes,locked 2006.201.18:14:12.61/valo/05,734.99,yes,locked 2006.201.18:14:12.61/valo/06,814.99,yes,locked 2006.201.18:14:12.61/valo/07,864.99,yes,locked 2006.201.18:14:12.61/valo/08,884.99,yes,locked 2006.201.18:14:13.70/vb/01,04,usb,yes,28,26 2006.201.18:14:13.70/vb/02,05,usb,yes,27,27 2006.201.18:14:13.70/vb/03,04,usb,yes,28,31 2006.201.18:14:13.70/vb/04,05,usb,yes,28,27 2006.201.18:14:13.70/vb/05,04,usb,yes,25,27 2006.201.18:14:13.70/vb/06,04,usb,yes,29,25 2006.201.18:14:13.70/vb/07,04,usb,yes,29,29 2006.201.18:14:13.70/vb/08,04,usb,yes,27,30 2006.201.18:14:13.94/vblo/01,629.99,yes,locked 2006.201.18:14:13.94/vblo/02,634.99,yes,locked 2006.201.18:14:13.94/vblo/03,649.99,yes,locked 2006.201.18:14:13.94/vblo/04,679.99,yes,locked 2006.201.18:14:13.94/vblo/05,709.99,yes,locked 2006.201.18:14:13.94/vblo/06,719.99,yes,locked 2006.201.18:14:13.94/vblo/07,734.99,yes,locked 2006.201.18:14:13.94/vblo/08,744.99,yes,locked 2006.201.18:14:14.09/vabw/8 2006.201.18:14:14.24/vbbw/8 2006.201.18:14:14.33/xfe/off,on,15.5 2006.201.18:14:14.72/ifatt/23,28,28,28 2006.201.18:14:15.07/fmout-gps/S +4.59E-07 2006.201.18:14:15.11:!2006.201.18:17:40 2006.201.18:17:40.00:data_valid=off 2006.201.18:17:40.00:"et 2006.201.18:17:40.00:!+3s 2006.201.18:17:43.02:"tape 2006.201.18:17:43.02:postob 2006.201.18:17:43.22/cable/+6.4775E-03 2006.201.18:17:43.22/wx/20.49,1002.2,100 2006.201.18:17:43.30/fmout-gps/S +4.59E-07 2006.201.18:17:43.30:scan_name=201-1821,jd0607,140 2006.201.18:17:43.30:source=0528+134,053056.42,133155.1,2000.0,cw 2006.201.18:17:44.14#flagr#flagr/antenna,new-source 2006.201.18:17:44.14:checkk5 2006.201.18:17:44.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:17:44.92/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:17:45.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:17:45.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:17:46.04/chk_obsdata//k5ts1/T2011814??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.18:17:46.41/chk_obsdata//k5ts2/T2011814??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.18:17:46.77/chk_obsdata//k5ts3/T2011814??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.18:17:47.14/chk_obsdata//k5ts4/T2011814??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.18:17:47.83/k5log//k5ts1_log_newline 2006.201.18:17:48.52/k5log//k5ts2_log_newline 2006.201.18:17:49.21/k5log//k5ts3_log_newline 2006.201.18:17:49.90/k5log//k5ts4_log_newline 2006.201.18:17:49.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:17:49.92:setupk4=1 2006.201.18:17:49.92$setupk4/echo=on 2006.201.18:17:49.92$setupk4/pcalon 2006.201.18:17:49.92$pcalon/"no phase cal control is implemented here 2006.201.18:17:49.92$setupk4/"tpicd=stop 2006.201.18:17:49.92$setupk4/"rec=synch_on 2006.201.18:17:49.92$setupk4/"rec_mode=128 2006.201.18:17:49.92$setupk4/!* 2006.201.18:17:49.92$setupk4/recpk4 2006.201.18:17:49.92$recpk4/recpatch= 2006.201.18:17:49.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:17:49.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:17:49.93$setupk4/vck44 2006.201.18:17:49.93$vck44/valo=1,524.99 2006.201.18:17:49.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.18:17:49.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.18:17:49.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:49.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:49.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:49.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:49.93#ibcon#enter wrdev, iclass 21, count 0 2006.201.18:17:49.93#ibcon#first serial, iclass 21, count 0 2006.201.18:17:49.93#ibcon#enter sib2, iclass 21, count 0 2006.201.18:17:49.93#ibcon#flushed, iclass 21, count 0 2006.201.18:17:49.93#ibcon#about to write, iclass 21, count 0 2006.201.18:17:49.93#ibcon#wrote, iclass 21, count 0 2006.201.18:17:49.93#ibcon#about to read 3, iclass 21, count 0 2006.201.18:17:49.96#ibcon#read 3, iclass 21, count 0 2006.201.18:17:49.96#ibcon#about to read 4, iclass 21, count 0 2006.201.18:17:49.96#ibcon#read 4, iclass 21, count 0 2006.201.18:17:49.96#ibcon#about to read 5, iclass 21, count 0 2006.201.18:17:49.96#ibcon#read 5, iclass 21, count 0 2006.201.18:17:49.96#ibcon#about to read 6, iclass 21, count 0 2006.201.18:17:49.96#ibcon#read 6, iclass 21, count 0 2006.201.18:17:49.96#ibcon#end of sib2, iclass 21, count 0 2006.201.18:17:49.96#ibcon#*mode == 0, iclass 21, count 0 2006.201.18:17:49.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.18:17:49.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:17:49.96#ibcon#*before write, iclass 21, count 0 2006.201.18:17:49.96#ibcon#enter sib2, iclass 21, count 0 2006.201.18:17:49.96#ibcon#flushed, iclass 21, count 0 2006.201.18:17:49.96#ibcon#about to write, iclass 21, count 0 2006.201.18:17:49.96#ibcon#wrote, iclass 21, count 0 2006.201.18:17:49.96#ibcon#about to read 3, iclass 21, count 0 2006.201.18:17:50.01#ibcon#read 3, iclass 21, count 0 2006.201.18:17:50.01#ibcon#about to read 4, iclass 21, count 0 2006.201.18:17:50.01#ibcon#read 4, iclass 21, count 0 2006.201.18:17:50.01#ibcon#about to read 5, iclass 21, count 0 2006.201.18:17:50.01#ibcon#read 5, iclass 21, count 0 2006.201.18:17:50.01#ibcon#about to read 6, iclass 21, count 0 2006.201.18:17:50.01#ibcon#read 6, iclass 21, count 0 2006.201.18:17:50.01#ibcon#end of sib2, iclass 21, count 0 2006.201.18:17:50.01#ibcon#*after write, iclass 21, count 0 2006.201.18:17:50.01#ibcon#*before return 0, iclass 21, count 0 2006.201.18:17:50.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:50.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:50.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.18:17:50.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.18:17:50.01$vck44/va=1,8 2006.201.18:17:50.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.18:17:50.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.18:17:50.01#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:50.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:50.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:50.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:50.01#ibcon#enter wrdev, iclass 23, count 2 2006.201.18:17:50.01#ibcon#first serial, iclass 23, count 2 2006.201.18:17:50.01#ibcon#enter sib2, iclass 23, count 2 2006.201.18:17:50.01#ibcon#flushed, iclass 23, count 2 2006.201.18:17:50.01#ibcon#about to write, iclass 23, count 2 2006.201.18:17:50.01#ibcon#wrote, iclass 23, count 2 2006.201.18:17:50.01#ibcon#about to read 3, iclass 23, count 2 2006.201.18:17:50.03#ibcon#read 3, iclass 23, count 2 2006.201.18:17:50.03#ibcon#about to read 4, iclass 23, count 2 2006.201.18:17:50.03#ibcon#read 4, iclass 23, count 2 2006.201.18:17:50.03#ibcon#about to read 5, iclass 23, count 2 2006.201.18:17:50.03#ibcon#read 5, iclass 23, count 2 2006.201.18:17:50.03#ibcon#about to read 6, iclass 23, count 2 2006.201.18:17:50.03#ibcon#read 6, iclass 23, count 2 2006.201.18:17:50.03#ibcon#end of sib2, iclass 23, count 2 2006.201.18:17:50.03#ibcon#*mode == 0, iclass 23, count 2 2006.201.18:17:50.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.18:17:50.03#ibcon#[25=AT01-08\r\n] 2006.201.18:17:50.03#ibcon#*before write, iclass 23, count 2 2006.201.18:17:50.03#ibcon#enter sib2, iclass 23, count 2 2006.201.18:17:50.03#ibcon#flushed, iclass 23, count 2 2006.201.18:17:50.03#ibcon#about to write, iclass 23, count 2 2006.201.18:17:50.03#ibcon#wrote, iclass 23, count 2 2006.201.18:17:50.03#ibcon#about to read 3, iclass 23, count 2 2006.201.18:17:50.06#ibcon#read 3, iclass 23, count 2 2006.201.18:17:50.06#ibcon#about to read 4, iclass 23, count 2 2006.201.18:17:50.06#ibcon#read 4, iclass 23, count 2 2006.201.18:17:50.06#ibcon#about to read 5, iclass 23, count 2 2006.201.18:17:50.06#ibcon#read 5, iclass 23, count 2 2006.201.18:17:50.06#ibcon#about to read 6, iclass 23, count 2 2006.201.18:17:50.06#ibcon#read 6, iclass 23, count 2 2006.201.18:17:50.06#ibcon#end of sib2, iclass 23, count 2 2006.201.18:17:50.06#ibcon#*after write, iclass 23, count 2 2006.201.18:17:50.06#ibcon#*before return 0, iclass 23, count 2 2006.201.18:17:50.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:50.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:50.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.18:17:50.06#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:50.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:50.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:50.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:50.18#ibcon#enter wrdev, iclass 23, count 0 2006.201.18:17:50.18#ibcon#first serial, iclass 23, count 0 2006.201.18:17:50.18#ibcon#enter sib2, iclass 23, count 0 2006.201.18:17:50.18#ibcon#flushed, iclass 23, count 0 2006.201.18:17:50.18#ibcon#about to write, iclass 23, count 0 2006.201.18:17:50.18#ibcon#wrote, iclass 23, count 0 2006.201.18:17:50.18#ibcon#about to read 3, iclass 23, count 0 2006.201.18:17:50.20#ibcon#read 3, iclass 23, count 0 2006.201.18:17:50.20#ibcon#about to read 4, iclass 23, count 0 2006.201.18:17:50.20#ibcon#read 4, iclass 23, count 0 2006.201.18:17:50.20#ibcon#about to read 5, iclass 23, count 0 2006.201.18:17:50.20#ibcon#read 5, iclass 23, count 0 2006.201.18:17:50.20#ibcon#about to read 6, iclass 23, count 0 2006.201.18:17:50.20#ibcon#read 6, iclass 23, count 0 2006.201.18:17:50.20#ibcon#end of sib2, iclass 23, count 0 2006.201.18:17:50.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.18:17:50.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.18:17:50.20#ibcon#[25=USB\r\n] 2006.201.18:17:50.20#ibcon#*before write, iclass 23, count 0 2006.201.18:17:50.20#ibcon#enter sib2, iclass 23, count 0 2006.201.18:17:50.20#ibcon#flushed, iclass 23, count 0 2006.201.18:17:50.20#ibcon#about to write, iclass 23, count 0 2006.201.18:17:50.20#ibcon#wrote, iclass 23, count 0 2006.201.18:17:50.20#ibcon#about to read 3, iclass 23, count 0 2006.201.18:17:50.23#ibcon#read 3, iclass 23, count 0 2006.201.18:17:50.23#ibcon#about to read 4, iclass 23, count 0 2006.201.18:17:50.23#ibcon#read 4, iclass 23, count 0 2006.201.18:17:50.23#ibcon#about to read 5, iclass 23, count 0 2006.201.18:17:50.23#ibcon#read 5, iclass 23, count 0 2006.201.18:17:50.23#ibcon#about to read 6, iclass 23, count 0 2006.201.18:17:50.23#ibcon#read 6, iclass 23, count 0 2006.201.18:17:50.23#ibcon#end of sib2, iclass 23, count 0 2006.201.18:17:50.23#ibcon#*after write, iclass 23, count 0 2006.201.18:17:50.23#ibcon#*before return 0, iclass 23, count 0 2006.201.18:17:50.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:50.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:50.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.18:17:50.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.18:17:50.23$vck44/valo=2,534.99 2006.201.18:17:50.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.18:17:50.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.18:17:50.23#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:50.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:50.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:50.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:50.23#ibcon#enter wrdev, iclass 25, count 0 2006.201.18:17:50.23#ibcon#first serial, iclass 25, count 0 2006.201.18:17:50.23#ibcon#enter sib2, iclass 25, count 0 2006.201.18:17:50.23#ibcon#flushed, iclass 25, count 0 2006.201.18:17:50.23#ibcon#about to write, iclass 25, count 0 2006.201.18:17:50.23#ibcon#wrote, iclass 25, count 0 2006.201.18:17:50.23#ibcon#about to read 3, iclass 25, count 0 2006.201.18:17:50.25#ibcon#read 3, iclass 25, count 0 2006.201.18:17:50.25#ibcon#about to read 4, iclass 25, count 0 2006.201.18:17:50.25#ibcon#read 4, iclass 25, count 0 2006.201.18:17:50.25#ibcon#about to read 5, iclass 25, count 0 2006.201.18:17:50.25#ibcon#read 5, iclass 25, count 0 2006.201.18:17:50.25#ibcon#about to read 6, iclass 25, count 0 2006.201.18:17:50.25#ibcon#read 6, iclass 25, count 0 2006.201.18:17:50.25#ibcon#end of sib2, iclass 25, count 0 2006.201.18:17:50.25#ibcon#*mode == 0, iclass 25, count 0 2006.201.18:17:50.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.18:17:50.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:17:50.25#ibcon#*before write, iclass 25, count 0 2006.201.18:17:50.25#ibcon#enter sib2, iclass 25, count 0 2006.201.18:17:50.25#ibcon#flushed, iclass 25, count 0 2006.201.18:17:50.25#ibcon#about to write, iclass 25, count 0 2006.201.18:17:50.25#ibcon#wrote, iclass 25, count 0 2006.201.18:17:50.25#ibcon#about to read 3, iclass 25, count 0 2006.201.18:17:50.29#ibcon#read 3, iclass 25, count 0 2006.201.18:17:50.29#ibcon#about to read 4, iclass 25, count 0 2006.201.18:17:50.29#ibcon#read 4, iclass 25, count 0 2006.201.18:17:50.29#ibcon#about to read 5, iclass 25, count 0 2006.201.18:17:50.29#ibcon#read 5, iclass 25, count 0 2006.201.18:17:50.29#ibcon#about to read 6, iclass 25, count 0 2006.201.18:17:50.29#ibcon#read 6, iclass 25, count 0 2006.201.18:17:50.29#ibcon#end of sib2, iclass 25, count 0 2006.201.18:17:50.29#ibcon#*after write, iclass 25, count 0 2006.201.18:17:50.29#ibcon#*before return 0, iclass 25, count 0 2006.201.18:17:50.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:50.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:50.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.18:17:50.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.18:17:50.29$vck44/va=2,7 2006.201.18:17:50.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.18:17:50.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.18:17:50.29#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:50.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:50.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:50.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:50.35#ibcon#enter wrdev, iclass 27, count 2 2006.201.18:17:50.35#ibcon#first serial, iclass 27, count 2 2006.201.18:17:50.35#ibcon#enter sib2, iclass 27, count 2 2006.201.18:17:50.35#ibcon#flushed, iclass 27, count 2 2006.201.18:17:50.35#ibcon#about to write, iclass 27, count 2 2006.201.18:17:50.35#ibcon#wrote, iclass 27, count 2 2006.201.18:17:50.35#ibcon#about to read 3, iclass 27, count 2 2006.201.18:17:50.37#ibcon#read 3, iclass 27, count 2 2006.201.18:17:50.37#ibcon#about to read 4, iclass 27, count 2 2006.201.18:17:50.37#ibcon#read 4, iclass 27, count 2 2006.201.18:17:50.37#ibcon#about to read 5, iclass 27, count 2 2006.201.18:17:50.37#ibcon#read 5, iclass 27, count 2 2006.201.18:17:50.37#ibcon#about to read 6, iclass 27, count 2 2006.201.18:17:50.37#ibcon#read 6, iclass 27, count 2 2006.201.18:17:50.37#ibcon#end of sib2, iclass 27, count 2 2006.201.18:17:50.37#ibcon#*mode == 0, iclass 27, count 2 2006.201.18:17:50.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.18:17:50.37#ibcon#[25=AT02-07\r\n] 2006.201.18:17:50.37#ibcon#*before write, iclass 27, count 2 2006.201.18:17:50.37#ibcon#enter sib2, iclass 27, count 2 2006.201.18:17:50.37#ibcon#flushed, iclass 27, count 2 2006.201.18:17:50.37#ibcon#about to write, iclass 27, count 2 2006.201.18:17:50.37#ibcon#wrote, iclass 27, count 2 2006.201.18:17:50.37#ibcon#about to read 3, iclass 27, count 2 2006.201.18:17:50.40#ibcon#read 3, iclass 27, count 2 2006.201.18:17:50.40#ibcon#about to read 4, iclass 27, count 2 2006.201.18:17:50.40#ibcon#read 4, iclass 27, count 2 2006.201.18:17:50.40#ibcon#about to read 5, iclass 27, count 2 2006.201.18:17:50.40#ibcon#read 5, iclass 27, count 2 2006.201.18:17:50.40#ibcon#about to read 6, iclass 27, count 2 2006.201.18:17:50.40#ibcon#read 6, iclass 27, count 2 2006.201.18:17:50.40#ibcon#end of sib2, iclass 27, count 2 2006.201.18:17:50.40#ibcon#*after write, iclass 27, count 2 2006.201.18:17:50.40#ibcon#*before return 0, iclass 27, count 2 2006.201.18:17:50.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:50.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:50.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.18:17:50.40#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:50.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:50.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:50.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:50.52#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:17:50.52#ibcon#first serial, iclass 27, count 0 2006.201.18:17:50.52#ibcon#enter sib2, iclass 27, count 0 2006.201.18:17:50.52#ibcon#flushed, iclass 27, count 0 2006.201.18:17:50.52#ibcon#about to write, iclass 27, count 0 2006.201.18:17:50.52#ibcon#wrote, iclass 27, count 0 2006.201.18:17:50.52#ibcon#about to read 3, iclass 27, count 0 2006.201.18:17:50.54#ibcon#read 3, iclass 27, count 0 2006.201.18:17:50.54#ibcon#about to read 4, iclass 27, count 0 2006.201.18:17:50.54#ibcon#read 4, iclass 27, count 0 2006.201.18:17:50.54#ibcon#about to read 5, iclass 27, count 0 2006.201.18:17:50.54#ibcon#read 5, iclass 27, count 0 2006.201.18:17:50.54#ibcon#about to read 6, iclass 27, count 0 2006.201.18:17:50.54#ibcon#read 6, iclass 27, count 0 2006.201.18:17:50.54#ibcon#end of sib2, iclass 27, count 0 2006.201.18:17:50.54#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:17:50.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:17:50.54#ibcon#[25=USB\r\n] 2006.201.18:17:50.54#ibcon#*before write, iclass 27, count 0 2006.201.18:17:50.54#ibcon#enter sib2, iclass 27, count 0 2006.201.18:17:50.54#ibcon#flushed, iclass 27, count 0 2006.201.18:17:50.54#ibcon#about to write, iclass 27, count 0 2006.201.18:17:50.54#ibcon#wrote, iclass 27, count 0 2006.201.18:17:50.54#ibcon#about to read 3, iclass 27, count 0 2006.201.18:17:50.57#ibcon#read 3, iclass 27, count 0 2006.201.18:17:50.57#ibcon#about to read 4, iclass 27, count 0 2006.201.18:17:50.57#ibcon#read 4, iclass 27, count 0 2006.201.18:17:50.57#ibcon#about to read 5, iclass 27, count 0 2006.201.18:17:50.57#ibcon#read 5, iclass 27, count 0 2006.201.18:17:50.57#ibcon#about to read 6, iclass 27, count 0 2006.201.18:17:50.57#ibcon#read 6, iclass 27, count 0 2006.201.18:17:50.57#ibcon#end of sib2, iclass 27, count 0 2006.201.18:17:50.57#ibcon#*after write, iclass 27, count 0 2006.201.18:17:50.57#ibcon#*before return 0, iclass 27, count 0 2006.201.18:17:50.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:50.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:50.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:17:50.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:17:50.57$vck44/valo=3,564.99 2006.201.18:17:50.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.18:17:50.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.18:17:50.57#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:50.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:50.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:50.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:50.57#ibcon#enter wrdev, iclass 29, count 0 2006.201.18:17:50.57#ibcon#first serial, iclass 29, count 0 2006.201.18:17:50.57#ibcon#enter sib2, iclass 29, count 0 2006.201.18:17:50.57#ibcon#flushed, iclass 29, count 0 2006.201.18:17:50.57#ibcon#about to write, iclass 29, count 0 2006.201.18:17:50.57#ibcon#wrote, iclass 29, count 0 2006.201.18:17:50.57#ibcon#about to read 3, iclass 29, count 0 2006.201.18:17:50.59#ibcon#read 3, iclass 29, count 0 2006.201.18:17:50.59#ibcon#about to read 4, iclass 29, count 0 2006.201.18:17:50.59#ibcon#read 4, iclass 29, count 0 2006.201.18:17:50.59#ibcon#about to read 5, iclass 29, count 0 2006.201.18:17:50.59#ibcon#read 5, iclass 29, count 0 2006.201.18:17:50.59#ibcon#about to read 6, iclass 29, count 0 2006.201.18:17:50.59#ibcon#read 6, iclass 29, count 0 2006.201.18:17:50.59#ibcon#end of sib2, iclass 29, count 0 2006.201.18:17:50.59#ibcon#*mode == 0, iclass 29, count 0 2006.201.18:17:50.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.18:17:50.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:17:50.59#ibcon#*before write, iclass 29, count 0 2006.201.18:17:50.59#ibcon#enter sib2, iclass 29, count 0 2006.201.18:17:50.59#ibcon#flushed, iclass 29, count 0 2006.201.18:17:50.59#ibcon#about to write, iclass 29, count 0 2006.201.18:17:50.59#ibcon#wrote, iclass 29, count 0 2006.201.18:17:50.59#ibcon#about to read 3, iclass 29, count 0 2006.201.18:17:50.64#ibcon#read 3, iclass 29, count 0 2006.201.18:17:50.64#ibcon#about to read 4, iclass 29, count 0 2006.201.18:17:50.64#ibcon#read 4, iclass 29, count 0 2006.201.18:17:50.64#ibcon#about to read 5, iclass 29, count 0 2006.201.18:17:50.64#ibcon#read 5, iclass 29, count 0 2006.201.18:17:50.64#ibcon#about to read 6, iclass 29, count 0 2006.201.18:17:50.64#ibcon#read 6, iclass 29, count 0 2006.201.18:17:50.64#ibcon#end of sib2, iclass 29, count 0 2006.201.18:17:50.64#ibcon#*after write, iclass 29, count 0 2006.201.18:17:50.64#ibcon#*before return 0, iclass 29, count 0 2006.201.18:17:50.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:50.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:50.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.18:17:50.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.18:17:50.64$vck44/va=3,8 2006.201.18:17:50.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.18:17:50.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.18:17:50.64#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:50.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:50.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:50.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:50.69#ibcon#enter wrdev, iclass 31, count 2 2006.201.18:17:50.69#ibcon#first serial, iclass 31, count 2 2006.201.18:17:50.69#ibcon#enter sib2, iclass 31, count 2 2006.201.18:17:50.69#ibcon#flushed, iclass 31, count 2 2006.201.18:17:50.69#ibcon#about to write, iclass 31, count 2 2006.201.18:17:50.69#ibcon#wrote, iclass 31, count 2 2006.201.18:17:50.69#ibcon#about to read 3, iclass 31, count 2 2006.201.18:17:50.71#ibcon#read 3, iclass 31, count 2 2006.201.18:17:50.71#ibcon#about to read 4, iclass 31, count 2 2006.201.18:17:50.71#ibcon#read 4, iclass 31, count 2 2006.201.18:17:50.71#ibcon#about to read 5, iclass 31, count 2 2006.201.18:17:50.71#ibcon#read 5, iclass 31, count 2 2006.201.18:17:50.71#ibcon#about to read 6, iclass 31, count 2 2006.201.18:17:50.71#ibcon#read 6, iclass 31, count 2 2006.201.18:17:50.71#ibcon#end of sib2, iclass 31, count 2 2006.201.18:17:50.71#ibcon#*mode == 0, iclass 31, count 2 2006.201.18:17:50.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.18:17:50.71#ibcon#[25=AT03-08\r\n] 2006.201.18:17:50.71#ibcon#*before write, iclass 31, count 2 2006.201.18:17:50.71#ibcon#enter sib2, iclass 31, count 2 2006.201.18:17:50.71#ibcon#flushed, iclass 31, count 2 2006.201.18:17:50.71#ibcon#about to write, iclass 31, count 2 2006.201.18:17:50.71#ibcon#wrote, iclass 31, count 2 2006.201.18:17:50.71#ibcon#about to read 3, iclass 31, count 2 2006.201.18:17:50.74#ibcon#read 3, iclass 31, count 2 2006.201.18:17:50.74#ibcon#about to read 4, iclass 31, count 2 2006.201.18:17:50.74#ibcon#read 4, iclass 31, count 2 2006.201.18:17:50.74#ibcon#about to read 5, iclass 31, count 2 2006.201.18:17:50.74#ibcon#read 5, iclass 31, count 2 2006.201.18:17:50.74#ibcon#about to read 6, iclass 31, count 2 2006.201.18:17:50.74#ibcon#read 6, iclass 31, count 2 2006.201.18:17:50.74#ibcon#end of sib2, iclass 31, count 2 2006.201.18:17:50.74#ibcon#*after write, iclass 31, count 2 2006.201.18:17:50.74#ibcon#*before return 0, iclass 31, count 2 2006.201.18:17:50.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:50.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:50.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.18:17:50.74#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:50.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:50.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:50.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:50.86#ibcon#enter wrdev, iclass 31, count 0 2006.201.18:17:50.86#ibcon#first serial, iclass 31, count 0 2006.201.18:17:50.86#ibcon#enter sib2, iclass 31, count 0 2006.201.18:17:50.86#ibcon#flushed, iclass 31, count 0 2006.201.18:17:50.86#ibcon#about to write, iclass 31, count 0 2006.201.18:17:50.86#ibcon#wrote, iclass 31, count 0 2006.201.18:17:50.86#ibcon#about to read 3, iclass 31, count 0 2006.201.18:17:50.88#ibcon#read 3, iclass 31, count 0 2006.201.18:17:50.88#ibcon#about to read 4, iclass 31, count 0 2006.201.18:17:50.88#ibcon#read 4, iclass 31, count 0 2006.201.18:17:50.88#ibcon#about to read 5, iclass 31, count 0 2006.201.18:17:50.88#ibcon#read 5, iclass 31, count 0 2006.201.18:17:50.88#ibcon#about to read 6, iclass 31, count 0 2006.201.18:17:50.88#ibcon#read 6, iclass 31, count 0 2006.201.18:17:50.88#ibcon#end of sib2, iclass 31, count 0 2006.201.18:17:50.88#ibcon#*mode == 0, iclass 31, count 0 2006.201.18:17:50.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.18:17:50.88#ibcon#[25=USB\r\n] 2006.201.18:17:50.88#ibcon#*before write, iclass 31, count 0 2006.201.18:17:50.88#ibcon#enter sib2, iclass 31, count 0 2006.201.18:17:50.88#ibcon#flushed, iclass 31, count 0 2006.201.18:17:50.88#ibcon#about to write, iclass 31, count 0 2006.201.18:17:50.88#ibcon#wrote, iclass 31, count 0 2006.201.18:17:50.88#ibcon#about to read 3, iclass 31, count 0 2006.201.18:17:50.91#ibcon#read 3, iclass 31, count 0 2006.201.18:17:50.91#ibcon#about to read 4, iclass 31, count 0 2006.201.18:17:50.91#ibcon#read 4, iclass 31, count 0 2006.201.18:17:50.91#ibcon#about to read 5, iclass 31, count 0 2006.201.18:17:50.91#ibcon#read 5, iclass 31, count 0 2006.201.18:17:50.91#ibcon#about to read 6, iclass 31, count 0 2006.201.18:17:50.91#ibcon#read 6, iclass 31, count 0 2006.201.18:17:50.91#ibcon#end of sib2, iclass 31, count 0 2006.201.18:17:50.91#ibcon#*after write, iclass 31, count 0 2006.201.18:17:50.91#ibcon#*before return 0, iclass 31, count 0 2006.201.18:17:50.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:50.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:50.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.18:17:50.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.18:17:50.91$vck44/valo=4,624.99 2006.201.18:17:50.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.18:17:50.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.18:17:50.91#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:50.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:50.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:50.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:50.91#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:17:50.91#ibcon#first serial, iclass 33, count 0 2006.201.18:17:50.91#ibcon#enter sib2, iclass 33, count 0 2006.201.18:17:50.91#ibcon#flushed, iclass 33, count 0 2006.201.18:17:50.91#ibcon#about to write, iclass 33, count 0 2006.201.18:17:50.91#ibcon#wrote, iclass 33, count 0 2006.201.18:17:50.91#ibcon#about to read 3, iclass 33, count 0 2006.201.18:17:50.93#ibcon#read 3, iclass 33, count 0 2006.201.18:17:50.93#ibcon#about to read 4, iclass 33, count 0 2006.201.18:17:50.93#ibcon#read 4, iclass 33, count 0 2006.201.18:17:50.93#ibcon#about to read 5, iclass 33, count 0 2006.201.18:17:50.93#ibcon#read 5, iclass 33, count 0 2006.201.18:17:50.93#ibcon#about to read 6, iclass 33, count 0 2006.201.18:17:50.93#ibcon#read 6, iclass 33, count 0 2006.201.18:17:50.93#ibcon#end of sib2, iclass 33, count 0 2006.201.18:17:50.93#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:17:50.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:17:50.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:17:50.93#ibcon#*before write, iclass 33, count 0 2006.201.18:17:50.93#ibcon#enter sib2, iclass 33, count 0 2006.201.18:17:50.93#ibcon#flushed, iclass 33, count 0 2006.201.18:17:50.93#ibcon#about to write, iclass 33, count 0 2006.201.18:17:50.93#ibcon#wrote, iclass 33, count 0 2006.201.18:17:50.93#ibcon#about to read 3, iclass 33, count 0 2006.201.18:17:50.98#ibcon#read 3, iclass 33, count 0 2006.201.18:17:50.98#ibcon#about to read 4, iclass 33, count 0 2006.201.18:17:50.98#ibcon#read 4, iclass 33, count 0 2006.201.18:17:50.98#ibcon#about to read 5, iclass 33, count 0 2006.201.18:17:50.98#ibcon#read 5, iclass 33, count 0 2006.201.18:17:50.98#ibcon#about to read 6, iclass 33, count 0 2006.201.18:17:50.98#ibcon#read 6, iclass 33, count 0 2006.201.18:17:50.98#ibcon#end of sib2, iclass 33, count 0 2006.201.18:17:50.98#ibcon#*after write, iclass 33, count 0 2006.201.18:17:50.98#ibcon#*before return 0, iclass 33, count 0 2006.201.18:17:50.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:50.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:50.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:17:50.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:17:50.98$vck44/va=4,7 2006.201.18:17:50.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.18:17:50.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.18:17:50.98#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:50.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:51.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:51.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:51.03#ibcon#enter wrdev, iclass 35, count 2 2006.201.18:17:51.03#ibcon#first serial, iclass 35, count 2 2006.201.18:17:51.03#ibcon#enter sib2, iclass 35, count 2 2006.201.18:17:51.03#ibcon#flushed, iclass 35, count 2 2006.201.18:17:51.03#ibcon#about to write, iclass 35, count 2 2006.201.18:17:51.03#ibcon#wrote, iclass 35, count 2 2006.201.18:17:51.03#ibcon#about to read 3, iclass 35, count 2 2006.201.18:17:51.05#ibcon#read 3, iclass 35, count 2 2006.201.18:17:51.05#ibcon#about to read 4, iclass 35, count 2 2006.201.18:17:51.05#ibcon#read 4, iclass 35, count 2 2006.201.18:17:51.05#ibcon#about to read 5, iclass 35, count 2 2006.201.18:17:51.05#ibcon#read 5, iclass 35, count 2 2006.201.18:17:51.05#ibcon#about to read 6, iclass 35, count 2 2006.201.18:17:51.05#ibcon#read 6, iclass 35, count 2 2006.201.18:17:51.05#ibcon#end of sib2, iclass 35, count 2 2006.201.18:17:51.05#ibcon#*mode == 0, iclass 35, count 2 2006.201.18:17:51.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.18:17:51.05#ibcon#[25=AT04-07\r\n] 2006.201.18:17:51.05#ibcon#*before write, iclass 35, count 2 2006.201.18:17:51.05#ibcon#enter sib2, iclass 35, count 2 2006.201.18:17:51.05#ibcon#flushed, iclass 35, count 2 2006.201.18:17:51.05#ibcon#about to write, iclass 35, count 2 2006.201.18:17:51.05#ibcon#wrote, iclass 35, count 2 2006.201.18:17:51.05#ibcon#about to read 3, iclass 35, count 2 2006.201.18:17:51.08#ibcon#read 3, iclass 35, count 2 2006.201.18:17:51.08#ibcon#about to read 4, iclass 35, count 2 2006.201.18:17:51.08#ibcon#read 4, iclass 35, count 2 2006.201.18:17:51.08#ibcon#about to read 5, iclass 35, count 2 2006.201.18:17:51.08#ibcon#read 5, iclass 35, count 2 2006.201.18:17:51.08#ibcon#about to read 6, iclass 35, count 2 2006.201.18:17:51.08#ibcon#read 6, iclass 35, count 2 2006.201.18:17:51.08#ibcon#end of sib2, iclass 35, count 2 2006.201.18:17:51.08#ibcon#*after write, iclass 35, count 2 2006.201.18:17:51.08#ibcon#*before return 0, iclass 35, count 2 2006.201.18:17:51.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:51.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:51.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.18:17:51.08#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:51.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:51.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:51.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:51.20#ibcon#enter wrdev, iclass 35, count 0 2006.201.18:17:51.20#ibcon#first serial, iclass 35, count 0 2006.201.18:17:51.20#ibcon#enter sib2, iclass 35, count 0 2006.201.18:17:51.20#ibcon#flushed, iclass 35, count 0 2006.201.18:17:51.20#ibcon#about to write, iclass 35, count 0 2006.201.18:17:51.20#ibcon#wrote, iclass 35, count 0 2006.201.18:17:51.20#ibcon#about to read 3, iclass 35, count 0 2006.201.18:17:51.22#ibcon#read 3, iclass 35, count 0 2006.201.18:17:51.22#ibcon#about to read 4, iclass 35, count 0 2006.201.18:17:51.22#ibcon#read 4, iclass 35, count 0 2006.201.18:17:51.22#ibcon#about to read 5, iclass 35, count 0 2006.201.18:17:51.22#ibcon#read 5, iclass 35, count 0 2006.201.18:17:51.22#ibcon#about to read 6, iclass 35, count 0 2006.201.18:17:51.22#ibcon#read 6, iclass 35, count 0 2006.201.18:17:51.22#ibcon#end of sib2, iclass 35, count 0 2006.201.18:17:51.22#ibcon#*mode == 0, iclass 35, count 0 2006.201.18:17:51.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.18:17:51.22#ibcon#[25=USB\r\n] 2006.201.18:17:51.22#ibcon#*before write, iclass 35, count 0 2006.201.18:17:51.22#ibcon#enter sib2, iclass 35, count 0 2006.201.18:17:51.22#ibcon#flushed, iclass 35, count 0 2006.201.18:17:51.22#ibcon#about to write, iclass 35, count 0 2006.201.18:17:51.22#ibcon#wrote, iclass 35, count 0 2006.201.18:17:51.22#ibcon#about to read 3, iclass 35, count 0 2006.201.18:17:51.25#ibcon#read 3, iclass 35, count 0 2006.201.18:17:51.25#ibcon#about to read 4, iclass 35, count 0 2006.201.18:17:51.25#ibcon#read 4, iclass 35, count 0 2006.201.18:17:51.25#ibcon#about to read 5, iclass 35, count 0 2006.201.18:17:51.25#ibcon#read 5, iclass 35, count 0 2006.201.18:17:51.25#ibcon#about to read 6, iclass 35, count 0 2006.201.18:17:51.25#ibcon#read 6, iclass 35, count 0 2006.201.18:17:51.25#ibcon#end of sib2, iclass 35, count 0 2006.201.18:17:51.25#ibcon#*after write, iclass 35, count 0 2006.201.18:17:51.25#ibcon#*before return 0, iclass 35, count 0 2006.201.18:17:51.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:51.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:51.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.18:17:51.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.18:17:51.25$vck44/valo=5,734.99 2006.201.18:17:51.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.18:17:51.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.18:17:51.25#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:51.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:51.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:51.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:51.25#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:17:51.25#ibcon#first serial, iclass 37, count 0 2006.201.18:17:51.25#ibcon#enter sib2, iclass 37, count 0 2006.201.18:17:51.25#ibcon#flushed, iclass 37, count 0 2006.201.18:17:51.25#ibcon#about to write, iclass 37, count 0 2006.201.18:17:51.25#ibcon#wrote, iclass 37, count 0 2006.201.18:17:51.25#ibcon#about to read 3, iclass 37, count 0 2006.201.18:17:51.27#ibcon#read 3, iclass 37, count 0 2006.201.18:17:51.27#ibcon#about to read 4, iclass 37, count 0 2006.201.18:17:51.27#ibcon#read 4, iclass 37, count 0 2006.201.18:17:51.27#ibcon#about to read 5, iclass 37, count 0 2006.201.18:17:51.27#ibcon#read 5, iclass 37, count 0 2006.201.18:17:51.27#ibcon#about to read 6, iclass 37, count 0 2006.201.18:17:51.27#ibcon#read 6, iclass 37, count 0 2006.201.18:17:51.27#ibcon#end of sib2, iclass 37, count 0 2006.201.18:17:51.27#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:17:51.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:17:51.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:17:51.27#ibcon#*before write, iclass 37, count 0 2006.201.18:17:51.27#ibcon#enter sib2, iclass 37, count 0 2006.201.18:17:51.27#ibcon#flushed, iclass 37, count 0 2006.201.18:17:51.27#ibcon#about to write, iclass 37, count 0 2006.201.18:17:51.27#ibcon#wrote, iclass 37, count 0 2006.201.18:17:51.27#ibcon#about to read 3, iclass 37, count 0 2006.201.18:17:51.31#ibcon#read 3, iclass 37, count 0 2006.201.18:17:51.31#ibcon#about to read 4, iclass 37, count 0 2006.201.18:17:51.31#ibcon#read 4, iclass 37, count 0 2006.201.18:17:51.31#ibcon#about to read 5, iclass 37, count 0 2006.201.18:17:51.31#ibcon#read 5, iclass 37, count 0 2006.201.18:17:51.31#ibcon#about to read 6, iclass 37, count 0 2006.201.18:17:51.31#ibcon#read 6, iclass 37, count 0 2006.201.18:17:51.31#ibcon#end of sib2, iclass 37, count 0 2006.201.18:17:51.31#ibcon#*after write, iclass 37, count 0 2006.201.18:17:51.31#ibcon#*before return 0, iclass 37, count 0 2006.201.18:17:51.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:51.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:51.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:17:51.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:17:51.31$vck44/va=5,4 2006.201.18:17:51.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.18:17:51.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.18:17:51.31#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:51.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:51.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:51.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:51.37#ibcon#enter wrdev, iclass 39, count 2 2006.201.18:17:51.37#ibcon#first serial, iclass 39, count 2 2006.201.18:17:51.37#ibcon#enter sib2, iclass 39, count 2 2006.201.18:17:51.37#ibcon#flushed, iclass 39, count 2 2006.201.18:17:51.37#ibcon#about to write, iclass 39, count 2 2006.201.18:17:51.37#ibcon#wrote, iclass 39, count 2 2006.201.18:17:51.37#ibcon#about to read 3, iclass 39, count 2 2006.201.18:17:51.39#ibcon#read 3, iclass 39, count 2 2006.201.18:17:51.39#ibcon#about to read 4, iclass 39, count 2 2006.201.18:17:51.39#ibcon#read 4, iclass 39, count 2 2006.201.18:17:51.39#ibcon#about to read 5, iclass 39, count 2 2006.201.18:17:51.39#ibcon#read 5, iclass 39, count 2 2006.201.18:17:51.39#ibcon#about to read 6, iclass 39, count 2 2006.201.18:17:51.39#ibcon#read 6, iclass 39, count 2 2006.201.18:17:51.39#ibcon#end of sib2, iclass 39, count 2 2006.201.18:17:51.39#ibcon#*mode == 0, iclass 39, count 2 2006.201.18:17:51.39#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.18:17:51.39#ibcon#[25=AT05-04\r\n] 2006.201.18:17:51.39#ibcon#*before write, iclass 39, count 2 2006.201.18:17:51.39#ibcon#enter sib2, iclass 39, count 2 2006.201.18:17:51.39#ibcon#flushed, iclass 39, count 2 2006.201.18:17:51.39#ibcon#about to write, iclass 39, count 2 2006.201.18:17:51.39#ibcon#wrote, iclass 39, count 2 2006.201.18:17:51.39#ibcon#about to read 3, iclass 39, count 2 2006.201.18:17:51.42#ibcon#read 3, iclass 39, count 2 2006.201.18:17:51.42#ibcon#about to read 4, iclass 39, count 2 2006.201.18:17:51.42#ibcon#read 4, iclass 39, count 2 2006.201.18:17:51.42#ibcon#about to read 5, iclass 39, count 2 2006.201.18:17:51.42#ibcon#read 5, iclass 39, count 2 2006.201.18:17:51.42#ibcon#about to read 6, iclass 39, count 2 2006.201.18:17:51.42#ibcon#read 6, iclass 39, count 2 2006.201.18:17:51.42#ibcon#end of sib2, iclass 39, count 2 2006.201.18:17:51.42#ibcon#*after write, iclass 39, count 2 2006.201.18:17:51.42#ibcon#*before return 0, iclass 39, count 2 2006.201.18:17:51.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:51.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:51.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.18:17:51.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:51.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:51.45#abcon#<5=/16 0.5 1.4 20.491001002.1\r\n> 2006.201.18:17:51.47#abcon#{5=INTERFACE CLEAR} 2006.201.18:17:51.53#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:17:51.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:51.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:51.54#ibcon#enter wrdev, iclass 39, count 0 2006.201.18:17:51.54#ibcon#first serial, iclass 39, count 0 2006.201.18:17:51.54#ibcon#enter sib2, iclass 39, count 0 2006.201.18:17:51.54#ibcon#flushed, iclass 39, count 0 2006.201.18:17:51.54#ibcon#about to write, iclass 39, count 0 2006.201.18:17:51.54#ibcon#wrote, iclass 39, count 0 2006.201.18:17:51.54#ibcon#about to read 3, iclass 39, count 0 2006.201.18:17:51.56#ibcon#read 3, iclass 39, count 0 2006.201.18:17:51.56#ibcon#about to read 4, iclass 39, count 0 2006.201.18:17:51.56#ibcon#read 4, iclass 39, count 0 2006.201.18:17:51.56#ibcon#about to read 5, iclass 39, count 0 2006.201.18:17:51.56#ibcon#read 5, iclass 39, count 0 2006.201.18:17:51.56#ibcon#about to read 6, iclass 39, count 0 2006.201.18:17:51.56#ibcon#read 6, iclass 39, count 0 2006.201.18:17:51.56#ibcon#end of sib2, iclass 39, count 0 2006.201.18:17:51.56#ibcon#*mode == 0, iclass 39, count 0 2006.201.18:17:51.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.18:17:51.56#ibcon#[25=USB\r\n] 2006.201.18:17:51.56#ibcon#*before write, iclass 39, count 0 2006.201.18:17:51.56#ibcon#enter sib2, iclass 39, count 0 2006.201.18:17:51.56#ibcon#flushed, iclass 39, count 0 2006.201.18:17:51.56#ibcon#about to write, iclass 39, count 0 2006.201.18:17:51.56#ibcon#wrote, iclass 39, count 0 2006.201.18:17:51.56#ibcon#about to read 3, iclass 39, count 0 2006.201.18:17:51.59#ibcon#read 3, iclass 39, count 0 2006.201.18:17:51.59#ibcon#about to read 4, iclass 39, count 0 2006.201.18:17:51.59#ibcon#read 4, iclass 39, count 0 2006.201.18:17:51.59#ibcon#about to read 5, iclass 39, count 0 2006.201.18:17:51.59#ibcon#read 5, iclass 39, count 0 2006.201.18:17:51.59#ibcon#about to read 6, iclass 39, count 0 2006.201.18:17:51.59#ibcon#read 6, iclass 39, count 0 2006.201.18:17:51.59#ibcon#end of sib2, iclass 39, count 0 2006.201.18:17:51.59#ibcon#*after write, iclass 39, count 0 2006.201.18:17:51.59#ibcon#*before return 0, iclass 39, count 0 2006.201.18:17:51.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:51.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:51.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.18:17:51.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.18:17:51.59$vck44/valo=6,814.99 2006.201.18:17:51.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.18:17:51.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.18:17:51.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:51.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:51.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:51.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:51.59#ibcon#enter wrdev, iclass 7, count 0 2006.201.18:17:51.59#ibcon#first serial, iclass 7, count 0 2006.201.18:17:51.59#ibcon#enter sib2, iclass 7, count 0 2006.201.18:17:51.59#ibcon#flushed, iclass 7, count 0 2006.201.18:17:51.59#ibcon#about to write, iclass 7, count 0 2006.201.18:17:51.59#ibcon#wrote, iclass 7, count 0 2006.201.18:17:51.59#ibcon#about to read 3, iclass 7, count 0 2006.201.18:17:51.61#ibcon#read 3, iclass 7, count 0 2006.201.18:17:51.61#ibcon#about to read 4, iclass 7, count 0 2006.201.18:17:51.61#ibcon#read 4, iclass 7, count 0 2006.201.18:17:51.61#ibcon#about to read 5, iclass 7, count 0 2006.201.18:17:51.61#ibcon#read 5, iclass 7, count 0 2006.201.18:17:51.61#ibcon#about to read 6, iclass 7, count 0 2006.201.18:17:51.61#ibcon#read 6, iclass 7, count 0 2006.201.18:17:51.61#ibcon#end of sib2, iclass 7, count 0 2006.201.18:17:51.61#ibcon#*mode == 0, iclass 7, count 0 2006.201.18:17:51.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.18:17:51.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:17:51.61#ibcon#*before write, iclass 7, count 0 2006.201.18:17:51.61#ibcon#enter sib2, iclass 7, count 0 2006.201.18:17:51.61#ibcon#flushed, iclass 7, count 0 2006.201.18:17:51.61#ibcon#about to write, iclass 7, count 0 2006.201.18:17:51.61#ibcon#wrote, iclass 7, count 0 2006.201.18:17:51.61#ibcon#about to read 3, iclass 7, count 0 2006.201.18:17:51.65#ibcon#read 3, iclass 7, count 0 2006.201.18:17:51.65#ibcon#about to read 4, iclass 7, count 0 2006.201.18:17:51.65#ibcon#read 4, iclass 7, count 0 2006.201.18:17:51.65#ibcon#about to read 5, iclass 7, count 0 2006.201.18:17:51.65#ibcon#read 5, iclass 7, count 0 2006.201.18:17:51.65#ibcon#about to read 6, iclass 7, count 0 2006.201.18:17:51.65#ibcon#read 6, iclass 7, count 0 2006.201.18:17:51.65#ibcon#end of sib2, iclass 7, count 0 2006.201.18:17:51.65#ibcon#*after write, iclass 7, count 0 2006.201.18:17:51.65#ibcon#*before return 0, iclass 7, count 0 2006.201.18:17:51.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:51.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:51.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.18:17:51.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.18:17:51.65$vck44/va=6,5 2006.201.18:17:51.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.18:17:51.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.18:17:51.65#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:51.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:51.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:51.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:51.71#ibcon#enter wrdev, iclass 11, count 2 2006.201.18:17:51.71#ibcon#first serial, iclass 11, count 2 2006.201.18:17:51.71#ibcon#enter sib2, iclass 11, count 2 2006.201.18:17:51.71#ibcon#flushed, iclass 11, count 2 2006.201.18:17:51.71#ibcon#about to write, iclass 11, count 2 2006.201.18:17:51.71#ibcon#wrote, iclass 11, count 2 2006.201.18:17:51.71#ibcon#about to read 3, iclass 11, count 2 2006.201.18:17:51.73#ibcon#read 3, iclass 11, count 2 2006.201.18:17:51.73#ibcon#about to read 4, iclass 11, count 2 2006.201.18:17:51.73#ibcon#read 4, iclass 11, count 2 2006.201.18:17:51.73#ibcon#about to read 5, iclass 11, count 2 2006.201.18:17:51.73#ibcon#read 5, iclass 11, count 2 2006.201.18:17:51.73#ibcon#about to read 6, iclass 11, count 2 2006.201.18:17:51.73#ibcon#read 6, iclass 11, count 2 2006.201.18:17:51.73#ibcon#end of sib2, iclass 11, count 2 2006.201.18:17:51.73#ibcon#*mode == 0, iclass 11, count 2 2006.201.18:17:51.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.18:17:51.73#ibcon#[25=AT06-05\r\n] 2006.201.18:17:51.73#ibcon#*before write, iclass 11, count 2 2006.201.18:17:51.73#ibcon#enter sib2, iclass 11, count 2 2006.201.18:17:51.73#ibcon#flushed, iclass 11, count 2 2006.201.18:17:51.73#ibcon#about to write, iclass 11, count 2 2006.201.18:17:51.73#ibcon#wrote, iclass 11, count 2 2006.201.18:17:51.73#ibcon#about to read 3, iclass 11, count 2 2006.201.18:17:51.76#ibcon#read 3, iclass 11, count 2 2006.201.18:17:51.76#ibcon#about to read 4, iclass 11, count 2 2006.201.18:17:51.76#ibcon#read 4, iclass 11, count 2 2006.201.18:17:51.76#ibcon#about to read 5, iclass 11, count 2 2006.201.18:17:51.76#ibcon#read 5, iclass 11, count 2 2006.201.18:17:51.76#ibcon#about to read 6, iclass 11, count 2 2006.201.18:17:51.76#ibcon#read 6, iclass 11, count 2 2006.201.18:17:51.76#ibcon#end of sib2, iclass 11, count 2 2006.201.18:17:51.76#ibcon#*after write, iclass 11, count 2 2006.201.18:17:51.76#ibcon#*before return 0, iclass 11, count 2 2006.201.18:17:51.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:51.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:51.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.18:17:51.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:51.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:51.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:51.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:51.88#ibcon#enter wrdev, iclass 11, count 0 2006.201.18:17:51.88#ibcon#first serial, iclass 11, count 0 2006.201.18:17:51.88#ibcon#enter sib2, iclass 11, count 0 2006.201.18:17:51.88#ibcon#flushed, iclass 11, count 0 2006.201.18:17:51.88#ibcon#about to write, iclass 11, count 0 2006.201.18:17:51.88#ibcon#wrote, iclass 11, count 0 2006.201.18:17:51.88#ibcon#about to read 3, iclass 11, count 0 2006.201.18:17:51.90#ibcon#read 3, iclass 11, count 0 2006.201.18:17:51.90#ibcon#about to read 4, iclass 11, count 0 2006.201.18:17:51.90#ibcon#read 4, iclass 11, count 0 2006.201.18:17:51.90#ibcon#about to read 5, iclass 11, count 0 2006.201.18:17:51.90#ibcon#read 5, iclass 11, count 0 2006.201.18:17:51.90#ibcon#about to read 6, iclass 11, count 0 2006.201.18:17:51.90#ibcon#read 6, iclass 11, count 0 2006.201.18:17:51.90#ibcon#end of sib2, iclass 11, count 0 2006.201.18:17:51.90#ibcon#*mode == 0, iclass 11, count 0 2006.201.18:17:51.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.18:17:51.90#ibcon#[25=USB\r\n] 2006.201.18:17:51.90#ibcon#*before write, iclass 11, count 0 2006.201.18:17:51.90#ibcon#enter sib2, iclass 11, count 0 2006.201.18:17:51.90#ibcon#flushed, iclass 11, count 0 2006.201.18:17:51.90#ibcon#about to write, iclass 11, count 0 2006.201.18:17:51.90#ibcon#wrote, iclass 11, count 0 2006.201.18:17:51.90#ibcon#about to read 3, iclass 11, count 0 2006.201.18:17:51.93#ibcon#read 3, iclass 11, count 0 2006.201.18:17:51.93#ibcon#about to read 4, iclass 11, count 0 2006.201.18:17:51.93#ibcon#read 4, iclass 11, count 0 2006.201.18:17:51.93#ibcon#about to read 5, iclass 11, count 0 2006.201.18:17:51.93#ibcon#read 5, iclass 11, count 0 2006.201.18:17:51.93#ibcon#about to read 6, iclass 11, count 0 2006.201.18:17:51.93#ibcon#read 6, iclass 11, count 0 2006.201.18:17:51.93#ibcon#end of sib2, iclass 11, count 0 2006.201.18:17:51.93#ibcon#*after write, iclass 11, count 0 2006.201.18:17:51.93#ibcon#*before return 0, iclass 11, count 0 2006.201.18:17:51.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:51.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:51.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.18:17:51.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.18:17:51.93$vck44/valo=7,864.99 2006.201.18:17:51.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.18:17:51.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.18:17:51.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:51.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:51.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:51.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:51.93#ibcon#enter wrdev, iclass 13, count 0 2006.201.18:17:51.93#ibcon#first serial, iclass 13, count 0 2006.201.18:17:51.93#ibcon#enter sib2, iclass 13, count 0 2006.201.18:17:51.93#ibcon#flushed, iclass 13, count 0 2006.201.18:17:51.93#ibcon#about to write, iclass 13, count 0 2006.201.18:17:51.93#ibcon#wrote, iclass 13, count 0 2006.201.18:17:51.93#ibcon#about to read 3, iclass 13, count 0 2006.201.18:17:51.95#ibcon#read 3, iclass 13, count 0 2006.201.18:17:51.95#ibcon#about to read 4, iclass 13, count 0 2006.201.18:17:51.95#ibcon#read 4, iclass 13, count 0 2006.201.18:17:51.95#ibcon#about to read 5, iclass 13, count 0 2006.201.18:17:51.95#ibcon#read 5, iclass 13, count 0 2006.201.18:17:51.95#ibcon#about to read 6, iclass 13, count 0 2006.201.18:17:51.95#ibcon#read 6, iclass 13, count 0 2006.201.18:17:51.95#ibcon#end of sib2, iclass 13, count 0 2006.201.18:17:51.95#ibcon#*mode == 0, iclass 13, count 0 2006.201.18:17:51.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.18:17:51.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:17:51.95#ibcon#*before write, iclass 13, count 0 2006.201.18:17:51.95#ibcon#enter sib2, iclass 13, count 0 2006.201.18:17:51.95#ibcon#flushed, iclass 13, count 0 2006.201.18:17:51.95#ibcon#about to write, iclass 13, count 0 2006.201.18:17:51.95#ibcon#wrote, iclass 13, count 0 2006.201.18:17:51.95#ibcon#about to read 3, iclass 13, count 0 2006.201.18:17:51.99#ibcon#read 3, iclass 13, count 0 2006.201.18:17:51.99#ibcon#about to read 4, iclass 13, count 0 2006.201.18:17:51.99#ibcon#read 4, iclass 13, count 0 2006.201.18:17:51.99#ibcon#about to read 5, iclass 13, count 0 2006.201.18:17:51.99#ibcon#read 5, iclass 13, count 0 2006.201.18:17:51.99#ibcon#about to read 6, iclass 13, count 0 2006.201.18:17:51.99#ibcon#read 6, iclass 13, count 0 2006.201.18:17:51.99#ibcon#end of sib2, iclass 13, count 0 2006.201.18:17:51.99#ibcon#*after write, iclass 13, count 0 2006.201.18:17:51.99#ibcon#*before return 0, iclass 13, count 0 2006.201.18:17:51.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:51.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:51.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.18:17:51.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.18:17:51.99$vck44/va=7,5 2006.201.18:17:51.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.18:17:51.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.18:17:51.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:51.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:52.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:52.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:52.05#ibcon#enter wrdev, iclass 15, count 2 2006.201.18:17:52.05#ibcon#first serial, iclass 15, count 2 2006.201.18:17:52.05#ibcon#enter sib2, iclass 15, count 2 2006.201.18:17:52.05#ibcon#flushed, iclass 15, count 2 2006.201.18:17:52.05#ibcon#about to write, iclass 15, count 2 2006.201.18:17:52.05#ibcon#wrote, iclass 15, count 2 2006.201.18:17:52.05#ibcon#about to read 3, iclass 15, count 2 2006.201.18:17:52.07#ibcon#read 3, iclass 15, count 2 2006.201.18:17:52.07#ibcon#about to read 4, iclass 15, count 2 2006.201.18:17:52.07#ibcon#read 4, iclass 15, count 2 2006.201.18:17:52.07#ibcon#about to read 5, iclass 15, count 2 2006.201.18:17:52.07#ibcon#read 5, iclass 15, count 2 2006.201.18:17:52.07#ibcon#about to read 6, iclass 15, count 2 2006.201.18:17:52.07#ibcon#read 6, iclass 15, count 2 2006.201.18:17:52.07#ibcon#end of sib2, iclass 15, count 2 2006.201.18:17:52.07#ibcon#*mode == 0, iclass 15, count 2 2006.201.18:17:52.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.18:17:52.07#ibcon#[25=AT07-05\r\n] 2006.201.18:17:52.07#ibcon#*before write, iclass 15, count 2 2006.201.18:17:52.07#ibcon#enter sib2, iclass 15, count 2 2006.201.18:17:52.07#ibcon#flushed, iclass 15, count 2 2006.201.18:17:52.07#ibcon#about to write, iclass 15, count 2 2006.201.18:17:52.07#ibcon#wrote, iclass 15, count 2 2006.201.18:17:52.07#ibcon#about to read 3, iclass 15, count 2 2006.201.18:17:52.10#ibcon#read 3, iclass 15, count 2 2006.201.18:17:52.10#ibcon#about to read 4, iclass 15, count 2 2006.201.18:17:52.10#ibcon#read 4, iclass 15, count 2 2006.201.18:17:52.10#ibcon#about to read 5, iclass 15, count 2 2006.201.18:17:52.10#ibcon#read 5, iclass 15, count 2 2006.201.18:17:52.10#ibcon#about to read 6, iclass 15, count 2 2006.201.18:17:52.10#ibcon#read 6, iclass 15, count 2 2006.201.18:17:52.10#ibcon#end of sib2, iclass 15, count 2 2006.201.18:17:52.10#ibcon#*after write, iclass 15, count 2 2006.201.18:17:52.10#ibcon#*before return 0, iclass 15, count 2 2006.201.18:17:52.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:52.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:52.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.18:17:52.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:52.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:52.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:52.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:52.22#ibcon#enter wrdev, iclass 15, count 0 2006.201.18:17:52.22#ibcon#first serial, iclass 15, count 0 2006.201.18:17:52.22#ibcon#enter sib2, iclass 15, count 0 2006.201.18:17:52.22#ibcon#flushed, iclass 15, count 0 2006.201.18:17:52.22#ibcon#about to write, iclass 15, count 0 2006.201.18:17:52.22#ibcon#wrote, iclass 15, count 0 2006.201.18:17:52.22#ibcon#about to read 3, iclass 15, count 0 2006.201.18:17:52.24#ibcon#read 3, iclass 15, count 0 2006.201.18:17:52.24#ibcon#about to read 4, iclass 15, count 0 2006.201.18:17:52.24#ibcon#read 4, iclass 15, count 0 2006.201.18:17:52.24#ibcon#about to read 5, iclass 15, count 0 2006.201.18:17:52.24#ibcon#read 5, iclass 15, count 0 2006.201.18:17:52.24#ibcon#about to read 6, iclass 15, count 0 2006.201.18:17:52.24#ibcon#read 6, iclass 15, count 0 2006.201.18:17:52.24#ibcon#end of sib2, iclass 15, count 0 2006.201.18:17:52.24#ibcon#*mode == 0, iclass 15, count 0 2006.201.18:17:52.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.18:17:52.24#ibcon#[25=USB\r\n] 2006.201.18:17:52.24#ibcon#*before write, iclass 15, count 0 2006.201.18:17:52.24#ibcon#enter sib2, iclass 15, count 0 2006.201.18:17:52.24#ibcon#flushed, iclass 15, count 0 2006.201.18:17:52.24#ibcon#about to write, iclass 15, count 0 2006.201.18:17:52.24#ibcon#wrote, iclass 15, count 0 2006.201.18:17:52.24#ibcon#about to read 3, iclass 15, count 0 2006.201.18:17:52.27#ibcon#read 3, iclass 15, count 0 2006.201.18:17:52.27#ibcon#about to read 4, iclass 15, count 0 2006.201.18:17:52.27#ibcon#read 4, iclass 15, count 0 2006.201.18:17:52.27#ibcon#about to read 5, iclass 15, count 0 2006.201.18:17:52.27#ibcon#read 5, iclass 15, count 0 2006.201.18:17:52.27#ibcon#about to read 6, iclass 15, count 0 2006.201.18:17:52.27#ibcon#read 6, iclass 15, count 0 2006.201.18:17:52.27#ibcon#end of sib2, iclass 15, count 0 2006.201.18:17:52.27#ibcon#*after write, iclass 15, count 0 2006.201.18:17:52.27#ibcon#*before return 0, iclass 15, count 0 2006.201.18:17:52.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:52.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:52.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.18:17:52.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.18:17:52.27$vck44/valo=8,884.99 2006.201.18:17:52.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.18:17:52.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.18:17:52.27#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:52.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:52.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:52.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:52.27#ibcon#enter wrdev, iclass 17, count 0 2006.201.18:17:52.27#ibcon#first serial, iclass 17, count 0 2006.201.18:17:52.27#ibcon#enter sib2, iclass 17, count 0 2006.201.18:17:52.27#ibcon#flushed, iclass 17, count 0 2006.201.18:17:52.27#ibcon#about to write, iclass 17, count 0 2006.201.18:17:52.27#ibcon#wrote, iclass 17, count 0 2006.201.18:17:52.27#ibcon#about to read 3, iclass 17, count 0 2006.201.18:17:52.29#ibcon#read 3, iclass 17, count 0 2006.201.18:17:52.29#ibcon#about to read 4, iclass 17, count 0 2006.201.18:17:52.29#ibcon#read 4, iclass 17, count 0 2006.201.18:17:52.29#ibcon#about to read 5, iclass 17, count 0 2006.201.18:17:52.29#ibcon#read 5, iclass 17, count 0 2006.201.18:17:52.29#ibcon#about to read 6, iclass 17, count 0 2006.201.18:17:52.29#ibcon#read 6, iclass 17, count 0 2006.201.18:17:52.29#ibcon#end of sib2, iclass 17, count 0 2006.201.18:17:52.29#ibcon#*mode == 0, iclass 17, count 0 2006.201.18:17:52.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.18:17:52.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:17:52.29#ibcon#*before write, iclass 17, count 0 2006.201.18:17:52.29#ibcon#enter sib2, iclass 17, count 0 2006.201.18:17:52.29#ibcon#flushed, iclass 17, count 0 2006.201.18:17:52.29#ibcon#about to write, iclass 17, count 0 2006.201.18:17:52.29#ibcon#wrote, iclass 17, count 0 2006.201.18:17:52.29#ibcon#about to read 3, iclass 17, count 0 2006.201.18:17:52.33#ibcon#read 3, iclass 17, count 0 2006.201.18:17:52.33#ibcon#about to read 4, iclass 17, count 0 2006.201.18:17:52.33#ibcon#read 4, iclass 17, count 0 2006.201.18:17:52.33#ibcon#about to read 5, iclass 17, count 0 2006.201.18:17:52.33#ibcon#read 5, iclass 17, count 0 2006.201.18:17:52.33#ibcon#about to read 6, iclass 17, count 0 2006.201.18:17:52.33#ibcon#read 6, iclass 17, count 0 2006.201.18:17:52.33#ibcon#end of sib2, iclass 17, count 0 2006.201.18:17:52.33#ibcon#*after write, iclass 17, count 0 2006.201.18:17:52.33#ibcon#*before return 0, iclass 17, count 0 2006.201.18:17:52.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:52.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:52.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.18:17:52.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.18:17:52.33$vck44/va=8,4 2006.201.18:17:52.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.18:17:52.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.18:17:52.33#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:52.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:17:52.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:17:52.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:17:52.39#ibcon#enter wrdev, iclass 19, count 2 2006.201.18:17:52.39#ibcon#first serial, iclass 19, count 2 2006.201.18:17:52.39#ibcon#enter sib2, iclass 19, count 2 2006.201.18:17:52.39#ibcon#flushed, iclass 19, count 2 2006.201.18:17:52.39#ibcon#about to write, iclass 19, count 2 2006.201.18:17:52.39#ibcon#wrote, iclass 19, count 2 2006.201.18:17:52.39#ibcon#about to read 3, iclass 19, count 2 2006.201.18:17:52.41#ibcon#read 3, iclass 19, count 2 2006.201.18:17:52.41#ibcon#about to read 4, iclass 19, count 2 2006.201.18:17:52.41#ibcon#read 4, iclass 19, count 2 2006.201.18:17:52.41#ibcon#about to read 5, iclass 19, count 2 2006.201.18:17:52.41#ibcon#read 5, iclass 19, count 2 2006.201.18:17:52.41#ibcon#about to read 6, iclass 19, count 2 2006.201.18:17:52.41#ibcon#read 6, iclass 19, count 2 2006.201.18:17:52.41#ibcon#end of sib2, iclass 19, count 2 2006.201.18:17:52.41#ibcon#*mode == 0, iclass 19, count 2 2006.201.18:17:52.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.18:17:52.41#ibcon#[25=AT08-04\r\n] 2006.201.18:17:52.41#ibcon#*before write, iclass 19, count 2 2006.201.18:17:52.41#ibcon#enter sib2, iclass 19, count 2 2006.201.18:17:52.41#ibcon#flushed, iclass 19, count 2 2006.201.18:17:52.41#ibcon#about to write, iclass 19, count 2 2006.201.18:17:52.41#ibcon#wrote, iclass 19, count 2 2006.201.18:17:52.41#ibcon#about to read 3, iclass 19, count 2 2006.201.18:17:52.44#ibcon#read 3, iclass 19, count 2 2006.201.18:17:52.44#ibcon#about to read 4, iclass 19, count 2 2006.201.18:17:52.44#ibcon#read 4, iclass 19, count 2 2006.201.18:17:52.44#ibcon#about to read 5, iclass 19, count 2 2006.201.18:17:52.44#ibcon#read 5, iclass 19, count 2 2006.201.18:17:52.44#ibcon#about to read 6, iclass 19, count 2 2006.201.18:17:52.44#ibcon#read 6, iclass 19, count 2 2006.201.18:17:52.44#ibcon#end of sib2, iclass 19, count 2 2006.201.18:17:52.44#ibcon#*after write, iclass 19, count 2 2006.201.18:17:52.44#ibcon#*before return 0, iclass 19, count 2 2006.201.18:17:52.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:17:52.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:17:52.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.18:17:52.44#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:52.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:17:52.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:17:52.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:17:52.56#ibcon#enter wrdev, iclass 19, count 0 2006.201.18:17:52.56#ibcon#first serial, iclass 19, count 0 2006.201.18:17:52.56#ibcon#enter sib2, iclass 19, count 0 2006.201.18:17:52.56#ibcon#flushed, iclass 19, count 0 2006.201.18:17:52.56#ibcon#about to write, iclass 19, count 0 2006.201.18:17:52.56#ibcon#wrote, iclass 19, count 0 2006.201.18:17:52.56#ibcon#about to read 3, iclass 19, count 0 2006.201.18:17:52.58#ibcon#read 3, iclass 19, count 0 2006.201.18:17:52.58#ibcon#about to read 4, iclass 19, count 0 2006.201.18:17:52.58#ibcon#read 4, iclass 19, count 0 2006.201.18:17:52.58#ibcon#about to read 5, iclass 19, count 0 2006.201.18:17:52.58#ibcon#read 5, iclass 19, count 0 2006.201.18:17:52.58#ibcon#about to read 6, iclass 19, count 0 2006.201.18:17:52.58#ibcon#read 6, iclass 19, count 0 2006.201.18:17:52.58#ibcon#end of sib2, iclass 19, count 0 2006.201.18:17:52.58#ibcon#*mode == 0, iclass 19, count 0 2006.201.18:17:52.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.18:17:52.58#ibcon#[25=USB\r\n] 2006.201.18:17:52.58#ibcon#*before write, iclass 19, count 0 2006.201.18:17:52.58#ibcon#enter sib2, iclass 19, count 0 2006.201.18:17:52.58#ibcon#flushed, iclass 19, count 0 2006.201.18:17:52.58#ibcon#about to write, iclass 19, count 0 2006.201.18:17:52.58#ibcon#wrote, iclass 19, count 0 2006.201.18:17:52.58#ibcon#about to read 3, iclass 19, count 0 2006.201.18:17:52.61#ibcon#read 3, iclass 19, count 0 2006.201.18:17:52.61#ibcon#about to read 4, iclass 19, count 0 2006.201.18:17:52.61#ibcon#read 4, iclass 19, count 0 2006.201.18:17:52.61#ibcon#about to read 5, iclass 19, count 0 2006.201.18:17:52.61#ibcon#read 5, iclass 19, count 0 2006.201.18:17:52.61#ibcon#about to read 6, iclass 19, count 0 2006.201.18:17:52.61#ibcon#read 6, iclass 19, count 0 2006.201.18:17:52.61#ibcon#end of sib2, iclass 19, count 0 2006.201.18:17:52.61#ibcon#*after write, iclass 19, count 0 2006.201.18:17:52.61#ibcon#*before return 0, iclass 19, count 0 2006.201.18:17:52.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:17:52.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:17:52.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.18:17:52.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.18:17:52.61$vck44/vblo=1,629.99 2006.201.18:17:52.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.18:17:52.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.18:17:52.61#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:52.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:52.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:52.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:52.61#ibcon#enter wrdev, iclass 21, count 0 2006.201.18:17:52.61#ibcon#first serial, iclass 21, count 0 2006.201.18:17:52.61#ibcon#enter sib2, iclass 21, count 0 2006.201.18:17:52.61#ibcon#flushed, iclass 21, count 0 2006.201.18:17:52.61#ibcon#about to write, iclass 21, count 0 2006.201.18:17:52.61#ibcon#wrote, iclass 21, count 0 2006.201.18:17:52.61#ibcon#about to read 3, iclass 21, count 0 2006.201.18:17:52.63#ibcon#read 3, iclass 21, count 0 2006.201.18:17:52.63#ibcon#about to read 4, iclass 21, count 0 2006.201.18:17:52.63#ibcon#read 4, iclass 21, count 0 2006.201.18:17:52.63#ibcon#about to read 5, iclass 21, count 0 2006.201.18:17:52.63#ibcon#read 5, iclass 21, count 0 2006.201.18:17:52.63#ibcon#about to read 6, iclass 21, count 0 2006.201.18:17:52.63#ibcon#read 6, iclass 21, count 0 2006.201.18:17:52.63#ibcon#end of sib2, iclass 21, count 0 2006.201.18:17:52.63#ibcon#*mode == 0, iclass 21, count 0 2006.201.18:17:52.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.18:17:52.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:17:52.63#ibcon#*before write, iclass 21, count 0 2006.201.18:17:52.63#ibcon#enter sib2, iclass 21, count 0 2006.201.18:17:52.63#ibcon#flushed, iclass 21, count 0 2006.201.18:17:52.63#ibcon#about to write, iclass 21, count 0 2006.201.18:17:52.63#ibcon#wrote, iclass 21, count 0 2006.201.18:17:52.63#ibcon#about to read 3, iclass 21, count 0 2006.201.18:17:52.67#ibcon#read 3, iclass 21, count 0 2006.201.18:17:52.67#ibcon#about to read 4, iclass 21, count 0 2006.201.18:17:52.67#ibcon#read 4, iclass 21, count 0 2006.201.18:17:52.67#ibcon#about to read 5, iclass 21, count 0 2006.201.18:17:52.67#ibcon#read 5, iclass 21, count 0 2006.201.18:17:52.67#ibcon#about to read 6, iclass 21, count 0 2006.201.18:17:52.67#ibcon#read 6, iclass 21, count 0 2006.201.18:17:52.67#ibcon#end of sib2, iclass 21, count 0 2006.201.18:17:52.67#ibcon#*after write, iclass 21, count 0 2006.201.18:17:52.67#ibcon#*before return 0, iclass 21, count 0 2006.201.18:17:52.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:52.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:17:52.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.18:17:52.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.18:17:52.67$vck44/vb=1,4 2006.201.18:17:52.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.18:17:52.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.18:17:52.67#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:52.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:52.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:52.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:52.67#ibcon#enter wrdev, iclass 23, count 2 2006.201.18:17:52.67#ibcon#first serial, iclass 23, count 2 2006.201.18:17:52.67#ibcon#enter sib2, iclass 23, count 2 2006.201.18:17:52.67#ibcon#flushed, iclass 23, count 2 2006.201.18:17:52.67#ibcon#about to write, iclass 23, count 2 2006.201.18:17:52.67#ibcon#wrote, iclass 23, count 2 2006.201.18:17:52.67#ibcon#about to read 3, iclass 23, count 2 2006.201.18:17:52.69#ibcon#read 3, iclass 23, count 2 2006.201.18:17:52.69#ibcon#about to read 4, iclass 23, count 2 2006.201.18:17:52.69#ibcon#read 4, iclass 23, count 2 2006.201.18:17:52.69#ibcon#about to read 5, iclass 23, count 2 2006.201.18:17:52.69#ibcon#read 5, iclass 23, count 2 2006.201.18:17:52.69#ibcon#about to read 6, iclass 23, count 2 2006.201.18:17:52.69#ibcon#read 6, iclass 23, count 2 2006.201.18:17:52.69#ibcon#end of sib2, iclass 23, count 2 2006.201.18:17:52.69#ibcon#*mode == 0, iclass 23, count 2 2006.201.18:17:52.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.18:17:52.69#ibcon#[27=AT01-04\r\n] 2006.201.18:17:52.69#ibcon#*before write, iclass 23, count 2 2006.201.18:17:52.69#ibcon#enter sib2, iclass 23, count 2 2006.201.18:17:52.69#ibcon#flushed, iclass 23, count 2 2006.201.18:17:52.69#ibcon#about to write, iclass 23, count 2 2006.201.18:17:52.69#ibcon#wrote, iclass 23, count 2 2006.201.18:17:52.69#ibcon#about to read 3, iclass 23, count 2 2006.201.18:17:52.72#ibcon#read 3, iclass 23, count 2 2006.201.18:17:52.72#ibcon#about to read 4, iclass 23, count 2 2006.201.18:17:52.72#ibcon#read 4, iclass 23, count 2 2006.201.18:17:52.72#ibcon#about to read 5, iclass 23, count 2 2006.201.18:17:52.72#ibcon#read 5, iclass 23, count 2 2006.201.18:17:52.72#ibcon#about to read 6, iclass 23, count 2 2006.201.18:17:52.72#ibcon#read 6, iclass 23, count 2 2006.201.18:17:52.72#ibcon#end of sib2, iclass 23, count 2 2006.201.18:17:52.72#ibcon#*after write, iclass 23, count 2 2006.201.18:17:52.72#ibcon#*before return 0, iclass 23, count 2 2006.201.18:17:52.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:52.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:17:52.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.18:17:52.72#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:52.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:52.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:52.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:52.84#ibcon#enter wrdev, iclass 23, count 0 2006.201.18:17:52.84#ibcon#first serial, iclass 23, count 0 2006.201.18:17:52.84#ibcon#enter sib2, iclass 23, count 0 2006.201.18:17:52.84#ibcon#flushed, iclass 23, count 0 2006.201.18:17:52.84#ibcon#about to write, iclass 23, count 0 2006.201.18:17:52.84#ibcon#wrote, iclass 23, count 0 2006.201.18:17:52.84#ibcon#about to read 3, iclass 23, count 0 2006.201.18:17:52.86#ibcon#read 3, iclass 23, count 0 2006.201.18:17:52.86#ibcon#about to read 4, iclass 23, count 0 2006.201.18:17:52.86#ibcon#read 4, iclass 23, count 0 2006.201.18:17:52.86#ibcon#about to read 5, iclass 23, count 0 2006.201.18:17:52.86#ibcon#read 5, iclass 23, count 0 2006.201.18:17:52.86#ibcon#about to read 6, iclass 23, count 0 2006.201.18:17:52.86#ibcon#read 6, iclass 23, count 0 2006.201.18:17:52.86#ibcon#end of sib2, iclass 23, count 0 2006.201.18:17:52.86#ibcon#*mode == 0, iclass 23, count 0 2006.201.18:17:52.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.18:17:52.86#ibcon#[27=USB\r\n] 2006.201.18:17:52.86#ibcon#*before write, iclass 23, count 0 2006.201.18:17:52.86#ibcon#enter sib2, iclass 23, count 0 2006.201.18:17:52.86#ibcon#flushed, iclass 23, count 0 2006.201.18:17:52.86#ibcon#about to write, iclass 23, count 0 2006.201.18:17:52.86#ibcon#wrote, iclass 23, count 0 2006.201.18:17:52.86#ibcon#about to read 3, iclass 23, count 0 2006.201.18:17:52.89#ibcon#read 3, iclass 23, count 0 2006.201.18:17:52.89#ibcon#about to read 4, iclass 23, count 0 2006.201.18:17:52.89#ibcon#read 4, iclass 23, count 0 2006.201.18:17:52.89#ibcon#about to read 5, iclass 23, count 0 2006.201.18:17:52.89#ibcon#read 5, iclass 23, count 0 2006.201.18:17:52.89#ibcon#about to read 6, iclass 23, count 0 2006.201.18:17:52.89#ibcon#read 6, iclass 23, count 0 2006.201.18:17:52.89#ibcon#end of sib2, iclass 23, count 0 2006.201.18:17:52.89#ibcon#*after write, iclass 23, count 0 2006.201.18:17:52.89#ibcon#*before return 0, iclass 23, count 0 2006.201.18:17:52.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:52.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:17:52.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.18:17:52.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.18:17:52.89$vck44/vblo=2,634.99 2006.201.18:17:52.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.18:17:52.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.18:17:52.89#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:52.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:52.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:52.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:52.89#ibcon#enter wrdev, iclass 25, count 0 2006.201.18:17:52.89#ibcon#first serial, iclass 25, count 0 2006.201.18:17:52.89#ibcon#enter sib2, iclass 25, count 0 2006.201.18:17:52.89#ibcon#flushed, iclass 25, count 0 2006.201.18:17:52.89#ibcon#about to write, iclass 25, count 0 2006.201.18:17:52.89#ibcon#wrote, iclass 25, count 0 2006.201.18:17:52.89#ibcon#about to read 3, iclass 25, count 0 2006.201.18:17:52.91#ibcon#read 3, iclass 25, count 0 2006.201.18:17:52.91#ibcon#about to read 4, iclass 25, count 0 2006.201.18:17:52.91#ibcon#read 4, iclass 25, count 0 2006.201.18:17:52.91#ibcon#about to read 5, iclass 25, count 0 2006.201.18:17:52.91#ibcon#read 5, iclass 25, count 0 2006.201.18:17:52.91#ibcon#about to read 6, iclass 25, count 0 2006.201.18:17:52.91#ibcon#read 6, iclass 25, count 0 2006.201.18:17:52.91#ibcon#end of sib2, iclass 25, count 0 2006.201.18:17:52.91#ibcon#*mode == 0, iclass 25, count 0 2006.201.18:17:52.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.18:17:52.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:17:52.91#ibcon#*before write, iclass 25, count 0 2006.201.18:17:52.91#ibcon#enter sib2, iclass 25, count 0 2006.201.18:17:52.91#ibcon#flushed, iclass 25, count 0 2006.201.18:17:52.91#ibcon#about to write, iclass 25, count 0 2006.201.18:17:52.91#ibcon#wrote, iclass 25, count 0 2006.201.18:17:52.91#ibcon#about to read 3, iclass 25, count 0 2006.201.18:17:52.95#ibcon#read 3, iclass 25, count 0 2006.201.18:17:52.95#ibcon#about to read 4, iclass 25, count 0 2006.201.18:17:52.95#ibcon#read 4, iclass 25, count 0 2006.201.18:17:52.95#ibcon#about to read 5, iclass 25, count 0 2006.201.18:17:52.95#ibcon#read 5, iclass 25, count 0 2006.201.18:17:52.95#ibcon#about to read 6, iclass 25, count 0 2006.201.18:17:52.95#ibcon#read 6, iclass 25, count 0 2006.201.18:17:52.95#ibcon#end of sib2, iclass 25, count 0 2006.201.18:17:52.95#ibcon#*after write, iclass 25, count 0 2006.201.18:17:52.95#ibcon#*before return 0, iclass 25, count 0 2006.201.18:17:52.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:52.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:17:52.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.18:17:52.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.18:17:52.95$vck44/vb=2,5 2006.201.18:17:52.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.18:17:52.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.18:17:52.95#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:52.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:53.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:53.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:53.01#ibcon#enter wrdev, iclass 27, count 2 2006.201.18:17:53.01#ibcon#first serial, iclass 27, count 2 2006.201.18:17:53.01#ibcon#enter sib2, iclass 27, count 2 2006.201.18:17:53.01#ibcon#flushed, iclass 27, count 2 2006.201.18:17:53.01#ibcon#about to write, iclass 27, count 2 2006.201.18:17:53.01#ibcon#wrote, iclass 27, count 2 2006.201.18:17:53.01#ibcon#about to read 3, iclass 27, count 2 2006.201.18:17:53.03#ibcon#read 3, iclass 27, count 2 2006.201.18:17:53.03#ibcon#about to read 4, iclass 27, count 2 2006.201.18:17:53.03#ibcon#read 4, iclass 27, count 2 2006.201.18:17:53.03#ibcon#about to read 5, iclass 27, count 2 2006.201.18:17:53.03#ibcon#read 5, iclass 27, count 2 2006.201.18:17:53.03#ibcon#about to read 6, iclass 27, count 2 2006.201.18:17:53.03#ibcon#read 6, iclass 27, count 2 2006.201.18:17:53.03#ibcon#end of sib2, iclass 27, count 2 2006.201.18:17:53.03#ibcon#*mode == 0, iclass 27, count 2 2006.201.18:17:53.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.18:17:53.03#ibcon#[27=AT02-05\r\n] 2006.201.18:17:53.03#ibcon#*before write, iclass 27, count 2 2006.201.18:17:53.03#ibcon#enter sib2, iclass 27, count 2 2006.201.18:17:53.03#ibcon#flushed, iclass 27, count 2 2006.201.18:17:53.03#ibcon#about to write, iclass 27, count 2 2006.201.18:17:53.03#ibcon#wrote, iclass 27, count 2 2006.201.18:17:53.03#ibcon#about to read 3, iclass 27, count 2 2006.201.18:17:53.06#ibcon#read 3, iclass 27, count 2 2006.201.18:17:53.06#ibcon#about to read 4, iclass 27, count 2 2006.201.18:17:53.06#ibcon#read 4, iclass 27, count 2 2006.201.18:17:53.06#ibcon#about to read 5, iclass 27, count 2 2006.201.18:17:53.06#ibcon#read 5, iclass 27, count 2 2006.201.18:17:53.06#ibcon#about to read 6, iclass 27, count 2 2006.201.18:17:53.06#ibcon#read 6, iclass 27, count 2 2006.201.18:17:53.06#ibcon#end of sib2, iclass 27, count 2 2006.201.18:17:53.06#ibcon#*after write, iclass 27, count 2 2006.201.18:17:53.06#ibcon#*before return 0, iclass 27, count 2 2006.201.18:17:53.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:53.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:17:53.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.18:17:53.06#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:53.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:53.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:53.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:53.18#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:17:53.18#ibcon#first serial, iclass 27, count 0 2006.201.18:17:53.18#ibcon#enter sib2, iclass 27, count 0 2006.201.18:17:53.18#ibcon#flushed, iclass 27, count 0 2006.201.18:17:53.18#ibcon#about to write, iclass 27, count 0 2006.201.18:17:53.18#ibcon#wrote, iclass 27, count 0 2006.201.18:17:53.18#ibcon#about to read 3, iclass 27, count 0 2006.201.18:17:53.20#ibcon#read 3, iclass 27, count 0 2006.201.18:17:53.20#ibcon#about to read 4, iclass 27, count 0 2006.201.18:17:53.20#ibcon#read 4, iclass 27, count 0 2006.201.18:17:53.20#ibcon#about to read 5, iclass 27, count 0 2006.201.18:17:53.20#ibcon#read 5, iclass 27, count 0 2006.201.18:17:53.20#ibcon#about to read 6, iclass 27, count 0 2006.201.18:17:53.20#ibcon#read 6, iclass 27, count 0 2006.201.18:17:53.20#ibcon#end of sib2, iclass 27, count 0 2006.201.18:17:53.20#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:17:53.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:17:53.20#ibcon#[27=USB\r\n] 2006.201.18:17:53.20#ibcon#*before write, iclass 27, count 0 2006.201.18:17:53.20#ibcon#enter sib2, iclass 27, count 0 2006.201.18:17:53.20#ibcon#flushed, iclass 27, count 0 2006.201.18:17:53.20#ibcon#about to write, iclass 27, count 0 2006.201.18:17:53.20#ibcon#wrote, iclass 27, count 0 2006.201.18:17:53.20#ibcon#about to read 3, iclass 27, count 0 2006.201.18:17:53.23#ibcon#read 3, iclass 27, count 0 2006.201.18:17:53.23#ibcon#about to read 4, iclass 27, count 0 2006.201.18:17:53.23#ibcon#read 4, iclass 27, count 0 2006.201.18:17:53.23#ibcon#about to read 5, iclass 27, count 0 2006.201.18:17:53.23#ibcon#read 5, iclass 27, count 0 2006.201.18:17:53.23#ibcon#about to read 6, iclass 27, count 0 2006.201.18:17:53.23#ibcon#read 6, iclass 27, count 0 2006.201.18:17:53.23#ibcon#end of sib2, iclass 27, count 0 2006.201.18:17:53.23#ibcon#*after write, iclass 27, count 0 2006.201.18:17:53.23#ibcon#*before return 0, iclass 27, count 0 2006.201.18:17:53.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:53.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:17:53.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:17:53.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:17:53.23$vck44/vblo=3,649.99 2006.201.18:17:53.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.18:17:53.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.18:17:53.23#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:53.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:53.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:53.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:53.23#ibcon#enter wrdev, iclass 29, count 0 2006.201.18:17:53.23#ibcon#first serial, iclass 29, count 0 2006.201.18:17:53.23#ibcon#enter sib2, iclass 29, count 0 2006.201.18:17:53.23#ibcon#flushed, iclass 29, count 0 2006.201.18:17:53.23#ibcon#about to write, iclass 29, count 0 2006.201.18:17:53.23#ibcon#wrote, iclass 29, count 0 2006.201.18:17:53.23#ibcon#about to read 3, iclass 29, count 0 2006.201.18:17:53.25#ibcon#read 3, iclass 29, count 0 2006.201.18:17:53.25#ibcon#about to read 4, iclass 29, count 0 2006.201.18:17:53.25#ibcon#read 4, iclass 29, count 0 2006.201.18:17:53.25#ibcon#about to read 5, iclass 29, count 0 2006.201.18:17:53.25#ibcon#read 5, iclass 29, count 0 2006.201.18:17:53.25#ibcon#about to read 6, iclass 29, count 0 2006.201.18:17:53.25#ibcon#read 6, iclass 29, count 0 2006.201.18:17:53.25#ibcon#end of sib2, iclass 29, count 0 2006.201.18:17:53.25#ibcon#*mode == 0, iclass 29, count 0 2006.201.18:17:53.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.18:17:53.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:17:53.25#ibcon#*before write, iclass 29, count 0 2006.201.18:17:53.25#ibcon#enter sib2, iclass 29, count 0 2006.201.18:17:53.25#ibcon#flushed, iclass 29, count 0 2006.201.18:17:53.25#ibcon#about to write, iclass 29, count 0 2006.201.18:17:53.25#ibcon#wrote, iclass 29, count 0 2006.201.18:17:53.25#ibcon#about to read 3, iclass 29, count 0 2006.201.18:17:53.29#ibcon#read 3, iclass 29, count 0 2006.201.18:17:53.29#ibcon#about to read 4, iclass 29, count 0 2006.201.18:17:53.29#ibcon#read 4, iclass 29, count 0 2006.201.18:17:53.29#ibcon#about to read 5, iclass 29, count 0 2006.201.18:17:53.29#ibcon#read 5, iclass 29, count 0 2006.201.18:17:53.29#ibcon#about to read 6, iclass 29, count 0 2006.201.18:17:53.29#ibcon#read 6, iclass 29, count 0 2006.201.18:17:53.29#ibcon#end of sib2, iclass 29, count 0 2006.201.18:17:53.29#ibcon#*after write, iclass 29, count 0 2006.201.18:17:53.29#ibcon#*before return 0, iclass 29, count 0 2006.201.18:17:53.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:53.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:17:53.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.18:17:53.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.18:17:53.29$vck44/vb=3,4 2006.201.18:17:53.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.18:17:53.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.18:17:53.29#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:53.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:53.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:53.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:53.35#ibcon#enter wrdev, iclass 31, count 2 2006.201.18:17:53.35#ibcon#first serial, iclass 31, count 2 2006.201.18:17:53.35#ibcon#enter sib2, iclass 31, count 2 2006.201.18:17:53.35#ibcon#flushed, iclass 31, count 2 2006.201.18:17:53.35#ibcon#about to write, iclass 31, count 2 2006.201.18:17:53.35#ibcon#wrote, iclass 31, count 2 2006.201.18:17:53.35#ibcon#about to read 3, iclass 31, count 2 2006.201.18:17:53.37#ibcon#read 3, iclass 31, count 2 2006.201.18:17:53.37#ibcon#about to read 4, iclass 31, count 2 2006.201.18:17:53.37#ibcon#read 4, iclass 31, count 2 2006.201.18:17:53.37#ibcon#about to read 5, iclass 31, count 2 2006.201.18:17:53.37#ibcon#read 5, iclass 31, count 2 2006.201.18:17:53.37#ibcon#about to read 6, iclass 31, count 2 2006.201.18:17:53.37#ibcon#read 6, iclass 31, count 2 2006.201.18:17:53.37#ibcon#end of sib2, iclass 31, count 2 2006.201.18:17:53.37#ibcon#*mode == 0, iclass 31, count 2 2006.201.18:17:53.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.18:17:53.37#ibcon#[27=AT03-04\r\n] 2006.201.18:17:53.37#ibcon#*before write, iclass 31, count 2 2006.201.18:17:53.37#ibcon#enter sib2, iclass 31, count 2 2006.201.18:17:53.37#ibcon#flushed, iclass 31, count 2 2006.201.18:17:53.37#ibcon#about to write, iclass 31, count 2 2006.201.18:17:53.37#ibcon#wrote, iclass 31, count 2 2006.201.18:17:53.37#ibcon#about to read 3, iclass 31, count 2 2006.201.18:17:53.40#ibcon#read 3, iclass 31, count 2 2006.201.18:17:53.40#ibcon#about to read 4, iclass 31, count 2 2006.201.18:17:53.40#ibcon#read 4, iclass 31, count 2 2006.201.18:17:53.40#ibcon#about to read 5, iclass 31, count 2 2006.201.18:17:53.40#ibcon#read 5, iclass 31, count 2 2006.201.18:17:53.40#ibcon#about to read 6, iclass 31, count 2 2006.201.18:17:53.40#ibcon#read 6, iclass 31, count 2 2006.201.18:17:53.40#ibcon#end of sib2, iclass 31, count 2 2006.201.18:17:53.40#ibcon#*after write, iclass 31, count 2 2006.201.18:17:53.40#ibcon#*before return 0, iclass 31, count 2 2006.201.18:17:53.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:53.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:17:53.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.18:17:53.40#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:53.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:53.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:53.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:53.52#ibcon#enter wrdev, iclass 31, count 0 2006.201.18:17:53.52#ibcon#first serial, iclass 31, count 0 2006.201.18:17:53.52#ibcon#enter sib2, iclass 31, count 0 2006.201.18:17:53.52#ibcon#flushed, iclass 31, count 0 2006.201.18:17:53.52#ibcon#about to write, iclass 31, count 0 2006.201.18:17:53.52#ibcon#wrote, iclass 31, count 0 2006.201.18:17:53.52#ibcon#about to read 3, iclass 31, count 0 2006.201.18:17:53.54#ibcon#read 3, iclass 31, count 0 2006.201.18:17:53.54#ibcon#about to read 4, iclass 31, count 0 2006.201.18:17:53.54#ibcon#read 4, iclass 31, count 0 2006.201.18:17:53.54#ibcon#about to read 5, iclass 31, count 0 2006.201.18:17:53.54#ibcon#read 5, iclass 31, count 0 2006.201.18:17:53.54#ibcon#about to read 6, iclass 31, count 0 2006.201.18:17:53.54#ibcon#read 6, iclass 31, count 0 2006.201.18:17:53.54#ibcon#end of sib2, iclass 31, count 0 2006.201.18:17:53.54#ibcon#*mode == 0, iclass 31, count 0 2006.201.18:17:53.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.18:17:53.54#ibcon#[27=USB\r\n] 2006.201.18:17:53.54#ibcon#*before write, iclass 31, count 0 2006.201.18:17:53.54#ibcon#enter sib2, iclass 31, count 0 2006.201.18:17:53.54#ibcon#flushed, iclass 31, count 0 2006.201.18:17:53.54#ibcon#about to write, iclass 31, count 0 2006.201.18:17:53.54#ibcon#wrote, iclass 31, count 0 2006.201.18:17:53.54#ibcon#about to read 3, iclass 31, count 0 2006.201.18:17:53.57#ibcon#read 3, iclass 31, count 0 2006.201.18:17:53.57#ibcon#about to read 4, iclass 31, count 0 2006.201.18:17:53.57#ibcon#read 4, iclass 31, count 0 2006.201.18:17:53.57#ibcon#about to read 5, iclass 31, count 0 2006.201.18:17:53.57#ibcon#read 5, iclass 31, count 0 2006.201.18:17:53.57#ibcon#about to read 6, iclass 31, count 0 2006.201.18:17:53.57#ibcon#read 6, iclass 31, count 0 2006.201.18:17:53.57#ibcon#end of sib2, iclass 31, count 0 2006.201.18:17:53.57#ibcon#*after write, iclass 31, count 0 2006.201.18:17:53.57#ibcon#*before return 0, iclass 31, count 0 2006.201.18:17:53.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:53.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:17:53.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.18:17:53.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.18:17:53.57$vck44/vblo=4,679.99 2006.201.18:17:53.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.18:17:53.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.18:17:53.57#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:53.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:53.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:53.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:53.57#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:17:53.57#ibcon#first serial, iclass 33, count 0 2006.201.18:17:53.57#ibcon#enter sib2, iclass 33, count 0 2006.201.18:17:53.57#ibcon#flushed, iclass 33, count 0 2006.201.18:17:53.57#ibcon#about to write, iclass 33, count 0 2006.201.18:17:53.57#ibcon#wrote, iclass 33, count 0 2006.201.18:17:53.57#ibcon#about to read 3, iclass 33, count 0 2006.201.18:17:53.59#ibcon#read 3, iclass 33, count 0 2006.201.18:17:53.59#ibcon#about to read 4, iclass 33, count 0 2006.201.18:17:53.59#ibcon#read 4, iclass 33, count 0 2006.201.18:17:53.59#ibcon#about to read 5, iclass 33, count 0 2006.201.18:17:53.59#ibcon#read 5, iclass 33, count 0 2006.201.18:17:53.59#ibcon#about to read 6, iclass 33, count 0 2006.201.18:17:53.59#ibcon#read 6, iclass 33, count 0 2006.201.18:17:53.59#ibcon#end of sib2, iclass 33, count 0 2006.201.18:17:53.59#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:17:53.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:17:53.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:17:53.59#ibcon#*before write, iclass 33, count 0 2006.201.18:17:53.59#ibcon#enter sib2, iclass 33, count 0 2006.201.18:17:53.59#ibcon#flushed, iclass 33, count 0 2006.201.18:17:53.59#ibcon#about to write, iclass 33, count 0 2006.201.18:17:53.59#ibcon#wrote, iclass 33, count 0 2006.201.18:17:53.59#ibcon#about to read 3, iclass 33, count 0 2006.201.18:17:53.64#ibcon#read 3, iclass 33, count 0 2006.201.18:17:53.64#ibcon#about to read 4, iclass 33, count 0 2006.201.18:17:53.64#ibcon#read 4, iclass 33, count 0 2006.201.18:17:53.64#ibcon#about to read 5, iclass 33, count 0 2006.201.18:17:53.64#ibcon#read 5, iclass 33, count 0 2006.201.18:17:53.64#ibcon#about to read 6, iclass 33, count 0 2006.201.18:17:53.64#ibcon#read 6, iclass 33, count 0 2006.201.18:17:53.64#ibcon#end of sib2, iclass 33, count 0 2006.201.18:17:53.64#ibcon#*after write, iclass 33, count 0 2006.201.18:17:53.64#ibcon#*before return 0, iclass 33, count 0 2006.201.18:17:53.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:53.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:17:53.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:17:53.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:17:53.64$vck44/vb=4,5 2006.201.18:17:53.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.18:17:53.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.18:17:53.64#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:53.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:53.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:53.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:53.69#ibcon#enter wrdev, iclass 35, count 2 2006.201.18:17:53.69#ibcon#first serial, iclass 35, count 2 2006.201.18:17:53.69#ibcon#enter sib2, iclass 35, count 2 2006.201.18:17:53.69#ibcon#flushed, iclass 35, count 2 2006.201.18:17:53.69#ibcon#about to write, iclass 35, count 2 2006.201.18:17:53.69#ibcon#wrote, iclass 35, count 2 2006.201.18:17:53.69#ibcon#about to read 3, iclass 35, count 2 2006.201.18:17:53.71#ibcon#read 3, iclass 35, count 2 2006.201.18:17:53.71#ibcon#about to read 4, iclass 35, count 2 2006.201.18:17:53.71#ibcon#read 4, iclass 35, count 2 2006.201.18:17:53.71#ibcon#about to read 5, iclass 35, count 2 2006.201.18:17:53.71#ibcon#read 5, iclass 35, count 2 2006.201.18:17:53.71#ibcon#about to read 6, iclass 35, count 2 2006.201.18:17:53.71#ibcon#read 6, iclass 35, count 2 2006.201.18:17:53.71#ibcon#end of sib2, iclass 35, count 2 2006.201.18:17:53.71#ibcon#*mode == 0, iclass 35, count 2 2006.201.18:17:53.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.18:17:53.71#ibcon#[27=AT04-05\r\n] 2006.201.18:17:53.71#ibcon#*before write, iclass 35, count 2 2006.201.18:17:53.71#ibcon#enter sib2, iclass 35, count 2 2006.201.18:17:53.71#ibcon#flushed, iclass 35, count 2 2006.201.18:17:53.71#ibcon#about to write, iclass 35, count 2 2006.201.18:17:53.71#ibcon#wrote, iclass 35, count 2 2006.201.18:17:53.71#ibcon#about to read 3, iclass 35, count 2 2006.201.18:17:53.74#ibcon#read 3, iclass 35, count 2 2006.201.18:17:53.74#ibcon#about to read 4, iclass 35, count 2 2006.201.18:17:53.74#ibcon#read 4, iclass 35, count 2 2006.201.18:17:53.74#ibcon#about to read 5, iclass 35, count 2 2006.201.18:17:53.74#ibcon#read 5, iclass 35, count 2 2006.201.18:17:53.74#ibcon#about to read 6, iclass 35, count 2 2006.201.18:17:53.74#ibcon#read 6, iclass 35, count 2 2006.201.18:17:53.74#ibcon#end of sib2, iclass 35, count 2 2006.201.18:17:53.74#ibcon#*after write, iclass 35, count 2 2006.201.18:17:53.74#ibcon#*before return 0, iclass 35, count 2 2006.201.18:17:53.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:53.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:17:53.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.18:17:53.74#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:53.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:53.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:53.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:53.86#ibcon#enter wrdev, iclass 35, count 0 2006.201.18:17:53.86#ibcon#first serial, iclass 35, count 0 2006.201.18:17:53.86#ibcon#enter sib2, iclass 35, count 0 2006.201.18:17:53.86#ibcon#flushed, iclass 35, count 0 2006.201.18:17:53.86#ibcon#about to write, iclass 35, count 0 2006.201.18:17:53.86#ibcon#wrote, iclass 35, count 0 2006.201.18:17:53.86#ibcon#about to read 3, iclass 35, count 0 2006.201.18:17:53.88#ibcon#read 3, iclass 35, count 0 2006.201.18:17:53.88#ibcon#about to read 4, iclass 35, count 0 2006.201.18:17:53.88#ibcon#read 4, iclass 35, count 0 2006.201.18:17:53.88#ibcon#about to read 5, iclass 35, count 0 2006.201.18:17:53.88#ibcon#read 5, iclass 35, count 0 2006.201.18:17:53.88#ibcon#about to read 6, iclass 35, count 0 2006.201.18:17:53.88#ibcon#read 6, iclass 35, count 0 2006.201.18:17:53.88#ibcon#end of sib2, iclass 35, count 0 2006.201.18:17:53.88#ibcon#*mode == 0, iclass 35, count 0 2006.201.18:17:53.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.18:17:53.88#ibcon#[27=USB\r\n] 2006.201.18:17:53.88#ibcon#*before write, iclass 35, count 0 2006.201.18:17:53.88#ibcon#enter sib2, iclass 35, count 0 2006.201.18:17:53.88#ibcon#flushed, iclass 35, count 0 2006.201.18:17:53.88#ibcon#about to write, iclass 35, count 0 2006.201.18:17:53.88#ibcon#wrote, iclass 35, count 0 2006.201.18:17:53.88#ibcon#about to read 3, iclass 35, count 0 2006.201.18:17:53.91#ibcon#read 3, iclass 35, count 0 2006.201.18:17:53.91#ibcon#about to read 4, iclass 35, count 0 2006.201.18:17:53.91#ibcon#read 4, iclass 35, count 0 2006.201.18:17:53.91#ibcon#about to read 5, iclass 35, count 0 2006.201.18:17:53.91#ibcon#read 5, iclass 35, count 0 2006.201.18:17:53.91#ibcon#about to read 6, iclass 35, count 0 2006.201.18:17:53.91#ibcon#read 6, iclass 35, count 0 2006.201.18:17:53.91#ibcon#end of sib2, iclass 35, count 0 2006.201.18:17:53.91#ibcon#*after write, iclass 35, count 0 2006.201.18:17:53.91#ibcon#*before return 0, iclass 35, count 0 2006.201.18:17:53.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:53.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:17:53.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.18:17:53.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.18:17:53.91$vck44/vblo=5,709.99 2006.201.18:17:53.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.18:17:53.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.18:17:53.91#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:53.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:53.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:53.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:53.91#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:17:53.91#ibcon#first serial, iclass 37, count 0 2006.201.18:17:53.91#ibcon#enter sib2, iclass 37, count 0 2006.201.18:17:53.91#ibcon#flushed, iclass 37, count 0 2006.201.18:17:53.91#ibcon#about to write, iclass 37, count 0 2006.201.18:17:53.91#ibcon#wrote, iclass 37, count 0 2006.201.18:17:53.91#ibcon#about to read 3, iclass 37, count 0 2006.201.18:17:53.93#ibcon#read 3, iclass 37, count 0 2006.201.18:17:53.93#ibcon#about to read 4, iclass 37, count 0 2006.201.18:17:53.93#ibcon#read 4, iclass 37, count 0 2006.201.18:17:53.93#ibcon#about to read 5, iclass 37, count 0 2006.201.18:17:53.93#ibcon#read 5, iclass 37, count 0 2006.201.18:17:53.93#ibcon#about to read 6, iclass 37, count 0 2006.201.18:17:53.93#ibcon#read 6, iclass 37, count 0 2006.201.18:17:53.93#ibcon#end of sib2, iclass 37, count 0 2006.201.18:17:53.93#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:17:53.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:17:53.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:17:53.93#ibcon#*before write, iclass 37, count 0 2006.201.18:17:53.93#ibcon#enter sib2, iclass 37, count 0 2006.201.18:17:53.93#ibcon#flushed, iclass 37, count 0 2006.201.18:17:53.93#ibcon#about to write, iclass 37, count 0 2006.201.18:17:53.93#ibcon#wrote, iclass 37, count 0 2006.201.18:17:53.93#ibcon#about to read 3, iclass 37, count 0 2006.201.18:17:53.97#ibcon#read 3, iclass 37, count 0 2006.201.18:17:53.97#ibcon#about to read 4, iclass 37, count 0 2006.201.18:17:53.97#ibcon#read 4, iclass 37, count 0 2006.201.18:17:53.97#ibcon#about to read 5, iclass 37, count 0 2006.201.18:17:53.97#ibcon#read 5, iclass 37, count 0 2006.201.18:17:53.97#ibcon#about to read 6, iclass 37, count 0 2006.201.18:17:53.97#ibcon#read 6, iclass 37, count 0 2006.201.18:17:53.97#ibcon#end of sib2, iclass 37, count 0 2006.201.18:17:53.97#ibcon#*after write, iclass 37, count 0 2006.201.18:17:53.97#ibcon#*before return 0, iclass 37, count 0 2006.201.18:17:53.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:53.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:17:53.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:17:53.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:17:53.97$vck44/vb=5,4 2006.201.18:17:53.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.18:17:53.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.18:17:53.97#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:53.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:54.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:54.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:54.03#ibcon#enter wrdev, iclass 39, count 2 2006.201.18:17:54.03#ibcon#first serial, iclass 39, count 2 2006.201.18:17:54.03#ibcon#enter sib2, iclass 39, count 2 2006.201.18:17:54.03#ibcon#flushed, iclass 39, count 2 2006.201.18:17:54.03#ibcon#about to write, iclass 39, count 2 2006.201.18:17:54.03#ibcon#wrote, iclass 39, count 2 2006.201.18:17:54.03#ibcon#about to read 3, iclass 39, count 2 2006.201.18:17:54.05#ibcon#read 3, iclass 39, count 2 2006.201.18:17:54.05#ibcon#about to read 4, iclass 39, count 2 2006.201.18:17:54.05#ibcon#read 4, iclass 39, count 2 2006.201.18:17:54.05#ibcon#about to read 5, iclass 39, count 2 2006.201.18:17:54.05#ibcon#read 5, iclass 39, count 2 2006.201.18:17:54.05#ibcon#about to read 6, iclass 39, count 2 2006.201.18:17:54.05#ibcon#read 6, iclass 39, count 2 2006.201.18:17:54.05#ibcon#end of sib2, iclass 39, count 2 2006.201.18:17:54.05#ibcon#*mode == 0, iclass 39, count 2 2006.201.18:17:54.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.18:17:54.05#ibcon#[27=AT05-04\r\n] 2006.201.18:17:54.05#ibcon#*before write, iclass 39, count 2 2006.201.18:17:54.05#ibcon#enter sib2, iclass 39, count 2 2006.201.18:17:54.05#ibcon#flushed, iclass 39, count 2 2006.201.18:17:54.05#ibcon#about to write, iclass 39, count 2 2006.201.18:17:54.05#ibcon#wrote, iclass 39, count 2 2006.201.18:17:54.05#ibcon#about to read 3, iclass 39, count 2 2006.201.18:17:54.08#ibcon#read 3, iclass 39, count 2 2006.201.18:17:54.08#ibcon#about to read 4, iclass 39, count 2 2006.201.18:17:54.08#ibcon#read 4, iclass 39, count 2 2006.201.18:17:54.08#ibcon#about to read 5, iclass 39, count 2 2006.201.18:17:54.08#ibcon#read 5, iclass 39, count 2 2006.201.18:17:54.08#ibcon#about to read 6, iclass 39, count 2 2006.201.18:17:54.08#ibcon#read 6, iclass 39, count 2 2006.201.18:17:54.08#ibcon#end of sib2, iclass 39, count 2 2006.201.18:17:54.08#ibcon#*after write, iclass 39, count 2 2006.201.18:17:54.08#ibcon#*before return 0, iclass 39, count 2 2006.201.18:17:54.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:54.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:17:54.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.18:17:54.08#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:54.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:54.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:54.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:54.20#ibcon#enter wrdev, iclass 39, count 0 2006.201.18:17:54.20#ibcon#first serial, iclass 39, count 0 2006.201.18:17:54.20#ibcon#enter sib2, iclass 39, count 0 2006.201.18:17:54.20#ibcon#flushed, iclass 39, count 0 2006.201.18:17:54.20#ibcon#about to write, iclass 39, count 0 2006.201.18:17:54.20#ibcon#wrote, iclass 39, count 0 2006.201.18:17:54.20#ibcon#about to read 3, iclass 39, count 0 2006.201.18:17:54.22#ibcon#read 3, iclass 39, count 0 2006.201.18:17:54.22#ibcon#about to read 4, iclass 39, count 0 2006.201.18:17:54.22#ibcon#read 4, iclass 39, count 0 2006.201.18:17:54.22#ibcon#about to read 5, iclass 39, count 0 2006.201.18:17:54.22#ibcon#read 5, iclass 39, count 0 2006.201.18:17:54.22#ibcon#about to read 6, iclass 39, count 0 2006.201.18:17:54.22#ibcon#read 6, iclass 39, count 0 2006.201.18:17:54.22#ibcon#end of sib2, iclass 39, count 0 2006.201.18:17:54.22#ibcon#*mode == 0, iclass 39, count 0 2006.201.18:17:54.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.18:17:54.22#ibcon#[27=USB\r\n] 2006.201.18:17:54.22#ibcon#*before write, iclass 39, count 0 2006.201.18:17:54.22#ibcon#enter sib2, iclass 39, count 0 2006.201.18:17:54.22#ibcon#flushed, iclass 39, count 0 2006.201.18:17:54.22#ibcon#about to write, iclass 39, count 0 2006.201.18:17:54.22#ibcon#wrote, iclass 39, count 0 2006.201.18:17:54.22#ibcon#about to read 3, iclass 39, count 0 2006.201.18:17:54.25#ibcon#read 3, iclass 39, count 0 2006.201.18:17:54.25#ibcon#about to read 4, iclass 39, count 0 2006.201.18:17:54.25#ibcon#read 4, iclass 39, count 0 2006.201.18:17:54.25#ibcon#about to read 5, iclass 39, count 0 2006.201.18:17:54.25#ibcon#read 5, iclass 39, count 0 2006.201.18:17:54.25#ibcon#about to read 6, iclass 39, count 0 2006.201.18:17:54.25#ibcon#read 6, iclass 39, count 0 2006.201.18:17:54.25#ibcon#end of sib2, iclass 39, count 0 2006.201.18:17:54.25#ibcon#*after write, iclass 39, count 0 2006.201.18:17:54.25#ibcon#*before return 0, iclass 39, count 0 2006.201.18:17:54.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:54.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:17:54.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.18:17:54.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.18:17:54.25$vck44/vblo=6,719.99 2006.201.18:17:54.25#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.18:17:54.25#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.18:17:54.25#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:54.25#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:17:54.25#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:17:54.25#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:17:54.25#ibcon#enter wrdev, iclass 2, count 0 2006.201.18:17:54.25#ibcon#first serial, iclass 2, count 0 2006.201.18:17:54.25#ibcon#enter sib2, iclass 2, count 0 2006.201.18:17:54.25#ibcon#flushed, iclass 2, count 0 2006.201.18:17:54.25#ibcon#about to write, iclass 2, count 0 2006.201.18:17:54.25#ibcon#wrote, iclass 2, count 0 2006.201.18:17:54.25#ibcon#about to read 3, iclass 2, count 0 2006.201.18:17:54.27#ibcon#read 3, iclass 2, count 0 2006.201.18:17:54.27#ibcon#about to read 4, iclass 2, count 0 2006.201.18:17:54.27#ibcon#read 4, iclass 2, count 0 2006.201.18:17:54.27#ibcon#about to read 5, iclass 2, count 0 2006.201.18:17:54.27#ibcon#read 5, iclass 2, count 0 2006.201.18:17:54.27#ibcon#about to read 6, iclass 2, count 0 2006.201.18:17:54.27#ibcon#read 6, iclass 2, count 0 2006.201.18:17:54.27#ibcon#end of sib2, iclass 2, count 0 2006.201.18:17:54.27#ibcon#*mode == 0, iclass 2, count 0 2006.201.18:17:54.27#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.18:17:54.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:17:54.27#ibcon#*before write, iclass 2, count 0 2006.201.18:17:54.27#ibcon#enter sib2, iclass 2, count 0 2006.201.18:17:54.27#ibcon#flushed, iclass 2, count 0 2006.201.18:17:54.27#ibcon#about to write, iclass 2, count 0 2006.201.18:17:54.27#ibcon#wrote, iclass 2, count 0 2006.201.18:17:54.27#ibcon#about to read 3, iclass 2, count 0 2006.201.18:17:54.31#ibcon#read 3, iclass 2, count 0 2006.201.18:17:54.31#ibcon#about to read 4, iclass 2, count 0 2006.201.18:17:54.31#ibcon#read 4, iclass 2, count 0 2006.201.18:17:54.31#ibcon#about to read 5, iclass 2, count 0 2006.201.18:17:54.31#ibcon#read 5, iclass 2, count 0 2006.201.18:17:54.31#ibcon#about to read 6, iclass 2, count 0 2006.201.18:17:54.31#ibcon#read 6, iclass 2, count 0 2006.201.18:17:54.31#ibcon#end of sib2, iclass 2, count 0 2006.201.18:17:54.31#ibcon#*after write, iclass 2, count 0 2006.201.18:17:54.31#ibcon#*before return 0, iclass 2, count 0 2006.201.18:17:54.31#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:17:54.31#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:17:54.31#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.18:17:54.31#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.18:17:54.31$vck44/vb=6,4 2006.201.18:17:54.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.18:17:54.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.18:17:54.31#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:54.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:17:54.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:17:54.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:17:54.37#ibcon#enter wrdev, iclass 5, count 2 2006.201.18:17:54.37#ibcon#first serial, iclass 5, count 2 2006.201.18:17:54.37#ibcon#enter sib2, iclass 5, count 2 2006.201.18:17:54.37#ibcon#flushed, iclass 5, count 2 2006.201.18:17:54.37#ibcon#about to write, iclass 5, count 2 2006.201.18:17:54.37#ibcon#wrote, iclass 5, count 2 2006.201.18:17:54.37#ibcon#about to read 3, iclass 5, count 2 2006.201.18:17:54.39#ibcon#read 3, iclass 5, count 2 2006.201.18:17:54.39#ibcon#about to read 4, iclass 5, count 2 2006.201.18:17:54.39#ibcon#read 4, iclass 5, count 2 2006.201.18:17:54.39#ibcon#about to read 5, iclass 5, count 2 2006.201.18:17:54.39#ibcon#read 5, iclass 5, count 2 2006.201.18:17:54.39#ibcon#about to read 6, iclass 5, count 2 2006.201.18:17:54.39#ibcon#read 6, iclass 5, count 2 2006.201.18:17:54.39#ibcon#end of sib2, iclass 5, count 2 2006.201.18:17:54.39#ibcon#*mode == 0, iclass 5, count 2 2006.201.18:17:54.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.18:17:54.39#ibcon#[27=AT06-04\r\n] 2006.201.18:17:54.39#ibcon#*before write, iclass 5, count 2 2006.201.18:17:54.39#ibcon#enter sib2, iclass 5, count 2 2006.201.18:17:54.39#ibcon#flushed, iclass 5, count 2 2006.201.18:17:54.39#ibcon#about to write, iclass 5, count 2 2006.201.18:17:54.39#ibcon#wrote, iclass 5, count 2 2006.201.18:17:54.39#ibcon#about to read 3, iclass 5, count 2 2006.201.18:17:54.42#ibcon#read 3, iclass 5, count 2 2006.201.18:17:54.42#ibcon#about to read 4, iclass 5, count 2 2006.201.18:17:54.42#ibcon#read 4, iclass 5, count 2 2006.201.18:17:54.42#ibcon#about to read 5, iclass 5, count 2 2006.201.18:17:54.42#ibcon#read 5, iclass 5, count 2 2006.201.18:17:54.42#ibcon#about to read 6, iclass 5, count 2 2006.201.18:17:54.42#ibcon#read 6, iclass 5, count 2 2006.201.18:17:54.42#ibcon#end of sib2, iclass 5, count 2 2006.201.18:17:54.42#ibcon#*after write, iclass 5, count 2 2006.201.18:17:54.42#ibcon#*before return 0, iclass 5, count 2 2006.201.18:17:54.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:17:54.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:17:54.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.18:17:54.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:54.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:17:54.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:17:54.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:17:54.54#ibcon#enter wrdev, iclass 5, count 0 2006.201.18:17:54.54#ibcon#first serial, iclass 5, count 0 2006.201.18:17:54.54#ibcon#enter sib2, iclass 5, count 0 2006.201.18:17:54.54#ibcon#flushed, iclass 5, count 0 2006.201.18:17:54.54#ibcon#about to write, iclass 5, count 0 2006.201.18:17:54.54#ibcon#wrote, iclass 5, count 0 2006.201.18:17:54.54#ibcon#about to read 3, iclass 5, count 0 2006.201.18:17:54.56#ibcon#read 3, iclass 5, count 0 2006.201.18:17:54.56#ibcon#about to read 4, iclass 5, count 0 2006.201.18:17:54.56#ibcon#read 4, iclass 5, count 0 2006.201.18:17:54.56#ibcon#about to read 5, iclass 5, count 0 2006.201.18:17:54.56#ibcon#read 5, iclass 5, count 0 2006.201.18:17:54.56#ibcon#about to read 6, iclass 5, count 0 2006.201.18:17:54.56#ibcon#read 6, iclass 5, count 0 2006.201.18:17:54.56#ibcon#end of sib2, iclass 5, count 0 2006.201.18:17:54.56#ibcon#*mode == 0, iclass 5, count 0 2006.201.18:17:54.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.18:17:54.56#ibcon#[27=USB\r\n] 2006.201.18:17:54.56#ibcon#*before write, iclass 5, count 0 2006.201.18:17:54.56#ibcon#enter sib2, iclass 5, count 0 2006.201.18:17:54.56#ibcon#flushed, iclass 5, count 0 2006.201.18:17:54.56#ibcon#about to write, iclass 5, count 0 2006.201.18:17:54.56#ibcon#wrote, iclass 5, count 0 2006.201.18:17:54.56#ibcon#about to read 3, iclass 5, count 0 2006.201.18:17:54.59#ibcon#read 3, iclass 5, count 0 2006.201.18:17:54.59#ibcon#about to read 4, iclass 5, count 0 2006.201.18:17:54.59#ibcon#read 4, iclass 5, count 0 2006.201.18:17:54.59#ibcon#about to read 5, iclass 5, count 0 2006.201.18:17:54.59#ibcon#read 5, iclass 5, count 0 2006.201.18:17:54.59#ibcon#about to read 6, iclass 5, count 0 2006.201.18:17:54.59#ibcon#read 6, iclass 5, count 0 2006.201.18:17:54.59#ibcon#end of sib2, iclass 5, count 0 2006.201.18:17:54.59#ibcon#*after write, iclass 5, count 0 2006.201.18:17:54.59#ibcon#*before return 0, iclass 5, count 0 2006.201.18:17:54.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:17:54.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:17:54.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.18:17:54.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.18:17:54.59$vck44/vblo=7,734.99 2006.201.18:17:54.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.18:17:54.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.18:17:54.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:54.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:54.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:54.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:54.59#ibcon#enter wrdev, iclass 7, count 0 2006.201.18:17:54.59#ibcon#first serial, iclass 7, count 0 2006.201.18:17:54.59#ibcon#enter sib2, iclass 7, count 0 2006.201.18:17:54.59#ibcon#flushed, iclass 7, count 0 2006.201.18:17:54.59#ibcon#about to write, iclass 7, count 0 2006.201.18:17:54.59#ibcon#wrote, iclass 7, count 0 2006.201.18:17:54.59#ibcon#about to read 3, iclass 7, count 0 2006.201.18:17:54.61#ibcon#read 3, iclass 7, count 0 2006.201.18:17:54.61#ibcon#about to read 4, iclass 7, count 0 2006.201.18:17:54.61#ibcon#read 4, iclass 7, count 0 2006.201.18:17:54.61#ibcon#about to read 5, iclass 7, count 0 2006.201.18:17:54.61#ibcon#read 5, iclass 7, count 0 2006.201.18:17:54.61#ibcon#about to read 6, iclass 7, count 0 2006.201.18:17:54.61#ibcon#read 6, iclass 7, count 0 2006.201.18:17:54.61#ibcon#end of sib2, iclass 7, count 0 2006.201.18:17:54.61#ibcon#*mode == 0, iclass 7, count 0 2006.201.18:17:54.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.18:17:54.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:17:54.61#ibcon#*before write, iclass 7, count 0 2006.201.18:17:54.61#ibcon#enter sib2, iclass 7, count 0 2006.201.18:17:54.61#ibcon#flushed, iclass 7, count 0 2006.201.18:17:54.61#ibcon#about to write, iclass 7, count 0 2006.201.18:17:54.61#ibcon#wrote, iclass 7, count 0 2006.201.18:17:54.61#ibcon#about to read 3, iclass 7, count 0 2006.201.18:17:54.65#ibcon#read 3, iclass 7, count 0 2006.201.18:17:54.65#ibcon#about to read 4, iclass 7, count 0 2006.201.18:17:54.65#ibcon#read 4, iclass 7, count 0 2006.201.18:17:54.65#ibcon#about to read 5, iclass 7, count 0 2006.201.18:17:54.65#ibcon#read 5, iclass 7, count 0 2006.201.18:17:54.65#ibcon#about to read 6, iclass 7, count 0 2006.201.18:17:54.65#ibcon#read 6, iclass 7, count 0 2006.201.18:17:54.65#ibcon#end of sib2, iclass 7, count 0 2006.201.18:17:54.65#ibcon#*after write, iclass 7, count 0 2006.201.18:17:54.65#ibcon#*before return 0, iclass 7, count 0 2006.201.18:17:54.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:54.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:17:54.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.18:17:54.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.18:17:54.65$vck44/vb=7,4 2006.201.18:17:54.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.18:17:54.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.18:17:54.65#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:54.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:54.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:54.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:54.71#ibcon#enter wrdev, iclass 11, count 2 2006.201.18:17:54.71#ibcon#first serial, iclass 11, count 2 2006.201.18:17:54.71#ibcon#enter sib2, iclass 11, count 2 2006.201.18:17:54.71#ibcon#flushed, iclass 11, count 2 2006.201.18:17:54.71#ibcon#about to write, iclass 11, count 2 2006.201.18:17:54.71#ibcon#wrote, iclass 11, count 2 2006.201.18:17:54.71#ibcon#about to read 3, iclass 11, count 2 2006.201.18:17:54.73#ibcon#read 3, iclass 11, count 2 2006.201.18:17:54.73#ibcon#about to read 4, iclass 11, count 2 2006.201.18:17:54.73#ibcon#read 4, iclass 11, count 2 2006.201.18:17:54.73#ibcon#about to read 5, iclass 11, count 2 2006.201.18:17:54.73#ibcon#read 5, iclass 11, count 2 2006.201.18:17:54.73#ibcon#about to read 6, iclass 11, count 2 2006.201.18:17:54.73#ibcon#read 6, iclass 11, count 2 2006.201.18:17:54.73#ibcon#end of sib2, iclass 11, count 2 2006.201.18:17:54.73#ibcon#*mode == 0, iclass 11, count 2 2006.201.18:17:54.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.18:17:54.73#ibcon#[27=AT07-04\r\n] 2006.201.18:17:54.73#ibcon#*before write, iclass 11, count 2 2006.201.18:17:54.73#ibcon#enter sib2, iclass 11, count 2 2006.201.18:17:54.73#ibcon#flushed, iclass 11, count 2 2006.201.18:17:54.73#ibcon#about to write, iclass 11, count 2 2006.201.18:17:54.73#ibcon#wrote, iclass 11, count 2 2006.201.18:17:54.73#ibcon#about to read 3, iclass 11, count 2 2006.201.18:17:54.76#ibcon#read 3, iclass 11, count 2 2006.201.18:17:54.76#ibcon#about to read 4, iclass 11, count 2 2006.201.18:17:54.76#ibcon#read 4, iclass 11, count 2 2006.201.18:17:54.76#ibcon#about to read 5, iclass 11, count 2 2006.201.18:17:54.76#ibcon#read 5, iclass 11, count 2 2006.201.18:17:54.76#ibcon#about to read 6, iclass 11, count 2 2006.201.18:17:54.76#ibcon#read 6, iclass 11, count 2 2006.201.18:17:54.76#ibcon#end of sib2, iclass 11, count 2 2006.201.18:17:54.76#ibcon#*after write, iclass 11, count 2 2006.201.18:17:54.76#ibcon#*before return 0, iclass 11, count 2 2006.201.18:17:54.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:54.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:17:54.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.18:17:54.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:54.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:54.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:54.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:54.88#ibcon#enter wrdev, iclass 11, count 0 2006.201.18:17:54.88#ibcon#first serial, iclass 11, count 0 2006.201.18:17:54.88#ibcon#enter sib2, iclass 11, count 0 2006.201.18:17:54.88#ibcon#flushed, iclass 11, count 0 2006.201.18:17:54.88#ibcon#about to write, iclass 11, count 0 2006.201.18:17:54.88#ibcon#wrote, iclass 11, count 0 2006.201.18:17:54.88#ibcon#about to read 3, iclass 11, count 0 2006.201.18:17:54.90#ibcon#read 3, iclass 11, count 0 2006.201.18:17:54.90#ibcon#about to read 4, iclass 11, count 0 2006.201.18:17:54.90#ibcon#read 4, iclass 11, count 0 2006.201.18:17:54.90#ibcon#about to read 5, iclass 11, count 0 2006.201.18:17:54.90#ibcon#read 5, iclass 11, count 0 2006.201.18:17:54.90#ibcon#about to read 6, iclass 11, count 0 2006.201.18:17:54.90#ibcon#read 6, iclass 11, count 0 2006.201.18:17:54.90#ibcon#end of sib2, iclass 11, count 0 2006.201.18:17:54.90#ibcon#*mode == 0, iclass 11, count 0 2006.201.18:17:54.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.18:17:54.90#ibcon#[27=USB\r\n] 2006.201.18:17:54.90#ibcon#*before write, iclass 11, count 0 2006.201.18:17:54.90#ibcon#enter sib2, iclass 11, count 0 2006.201.18:17:54.90#ibcon#flushed, iclass 11, count 0 2006.201.18:17:54.90#ibcon#about to write, iclass 11, count 0 2006.201.18:17:54.90#ibcon#wrote, iclass 11, count 0 2006.201.18:17:54.90#ibcon#about to read 3, iclass 11, count 0 2006.201.18:17:54.93#ibcon#read 3, iclass 11, count 0 2006.201.18:17:54.93#ibcon#about to read 4, iclass 11, count 0 2006.201.18:17:54.93#ibcon#read 4, iclass 11, count 0 2006.201.18:17:54.93#ibcon#about to read 5, iclass 11, count 0 2006.201.18:17:54.93#ibcon#read 5, iclass 11, count 0 2006.201.18:17:54.93#ibcon#about to read 6, iclass 11, count 0 2006.201.18:17:54.93#ibcon#read 6, iclass 11, count 0 2006.201.18:17:54.93#ibcon#end of sib2, iclass 11, count 0 2006.201.18:17:54.93#ibcon#*after write, iclass 11, count 0 2006.201.18:17:54.93#ibcon#*before return 0, iclass 11, count 0 2006.201.18:17:54.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:54.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:17:54.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.18:17:54.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.18:17:54.93$vck44/vblo=8,744.99 2006.201.18:17:54.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.18:17:54.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.18:17:54.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:17:54.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:54.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:54.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:54.93#ibcon#enter wrdev, iclass 13, count 0 2006.201.18:17:54.93#ibcon#first serial, iclass 13, count 0 2006.201.18:17:54.93#ibcon#enter sib2, iclass 13, count 0 2006.201.18:17:54.93#ibcon#flushed, iclass 13, count 0 2006.201.18:17:54.93#ibcon#about to write, iclass 13, count 0 2006.201.18:17:54.93#ibcon#wrote, iclass 13, count 0 2006.201.18:17:54.93#ibcon#about to read 3, iclass 13, count 0 2006.201.18:17:54.95#ibcon#read 3, iclass 13, count 0 2006.201.18:17:54.95#ibcon#about to read 4, iclass 13, count 0 2006.201.18:17:54.95#ibcon#read 4, iclass 13, count 0 2006.201.18:17:54.95#ibcon#about to read 5, iclass 13, count 0 2006.201.18:17:54.95#ibcon#read 5, iclass 13, count 0 2006.201.18:17:54.95#ibcon#about to read 6, iclass 13, count 0 2006.201.18:17:54.95#ibcon#read 6, iclass 13, count 0 2006.201.18:17:54.95#ibcon#end of sib2, iclass 13, count 0 2006.201.18:17:54.95#ibcon#*mode == 0, iclass 13, count 0 2006.201.18:17:54.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.18:17:54.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:17:54.95#ibcon#*before write, iclass 13, count 0 2006.201.18:17:54.95#ibcon#enter sib2, iclass 13, count 0 2006.201.18:17:54.95#ibcon#flushed, iclass 13, count 0 2006.201.18:17:54.95#ibcon#about to write, iclass 13, count 0 2006.201.18:17:54.95#ibcon#wrote, iclass 13, count 0 2006.201.18:17:54.95#ibcon#about to read 3, iclass 13, count 0 2006.201.18:17:54.99#ibcon#read 3, iclass 13, count 0 2006.201.18:17:54.99#ibcon#about to read 4, iclass 13, count 0 2006.201.18:17:54.99#ibcon#read 4, iclass 13, count 0 2006.201.18:17:54.99#ibcon#about to read 5, iclass 13, count 0 2006.201.18:17:54.99#ibcon#read 5, iclass 13, count 0 2006.201.18:17:54.99#ibcon#about to read 6, iclass 13, count 0 2006.201.18:17:54.99#ibcon#read 6, iclass 13, count 0 2006.201.18:17:54.99#ibcon#end of sib2, iclass 13, count 0 2006.201.18:17:54.99#ibcon#*after write, iclass 13, count 0 2006.201.18:17:54.99#ibcon#*before return 0, iclass 13, count 0 2006.201.18:17:54.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:54.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:17:54.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.18:17:54.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.18:17:54.99$vck44/vb=8,4 2006.201.18:17:54.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.18:17:54.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.18:17:54.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:17:54.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:55.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:55.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:55.05#ibcon#enter wrdev, iclass 15, count 2 2006.201.18:17:55.05#ibcon#first serial, iclass 15, count 2 2006.201.18:17:55.05#ibcon#enter sib2, iclass 15, count 2 2006.201.18:17:55.05#ibcon#flushed, iclass 15, count 2 2006.201.18:17:55.05#ibcon#about to write, iclass 15, count 2 2006.201.18:17:55.05#ibcon#wrote, iclass 15, count 2 2006.201.18:17:55.05#ibcon#about to read 3, iclass 15, count 2 2006.201.18:17:55.07#ibcon#read 3, iclass 15, count 2 2006.201.18:17:55.07#ibcon#about to read 4, iclass 15, count 2 2006.201.18:17:55.07#ibcon#read 4, iclass 15, count 2 2006.201.18:17:55.07#ibcon#about to read 5, iclass 15, count 2 2006.201.18:17:55.07#ibcon#read 5, iclass 15, count 2 2006.201.18:17:55.07#ibcon#about to read 6, iclass 15, count 2 2006.201.18:17:55.07#ibcon#read 6, iclass 15, count 2 2006.201.18:17:55.07#ibcon#end of sib2, iclass 15, count 2 2006.201.18:17:55.07#ibcon#*mode == 0, iclass 15, count 2 2006.201.18:17:55.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.18:17:55.07#ibcon#[27=AT08-04\r\n] 2006.201.18:17:55.07#ibcon#*before write, iclass 15, count 2 2006.201.18:17:55.07#ibcon#enter sib2, iclass 15, count 2 2006.201.18:17:55.07#ibcon#flushed, iclass 15, count 2 2006.201.18:17:55.07#ibcon#about to write, iclass 15, count 2 2006.201.18:17:55.07#ibcon#wrote, iclass 15, count 2 2006.201.18:17:55.07#ibcon#about to read 3, iclass 15, count 2 2006.201.18:17:55.10#ibcon#read 3, iclass 15, count 2 2006.201.18:17:55.10#ibcon#about to read 4, iclass 15, count 2 2006.201.18:17:55.10#ibcon#read 4, iclass 15, count 2 2006.201.18:17:55.10#ibcon#about to read 5, iclass 15, count 2 2006.201.18:17:55.10#ibcon#read 5, iclass 15, count 2 2006.201.18:17:55.10#ibcon#about to read 6, iclass 15, count 2 2006.201.18:17:55.10#ibcon#read 6, iclass 15, count 2 2006.201.18:17:55.10#ibcon#end of sib2, iclass 15, count 2 2006.201.18:17:55.10#ibcon#*after write, iclass 15, count 2 2006.201.18:17:55.10#ibcon#*before return 0, iclass 15, count 2 2006.201.18:17:55.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:55.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:17:55.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.18:17:55.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:17:55.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:55.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:55.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:55.22#ibcon#enter wrdev, iclass 15, count 0 2006.201.18:17:55.22#ibcon#first serial, iclass 15, count 0 2006.201.18:17:55.22#ibcon#enter sib2, iclass 15, count 0 2006.201.18:17:55.22#ibcon#flushed, iclass 15, count 0 2006.201.18:17:55.22#ibcon#about to write, iclass 15, count 0 2006.201.18:17:55.22#ibcon#wrote, iclass 15, count 0 2006.201.18:17:55.22#ibcon#about to read 3, iclass 15, count 0 2006.201.18:17:55.24#ibcon#read 3, iclass 15, count 0 2006.201.18:17:55.24#ibcon#about to read 4, iclass 15, count 0 2006.201.18:17:55.24#ibcon#read 4, iclass 15, count 0 2006.201.18:17:55.24#ibcon#about to read 5, iclass 15, count 0 2006.201.18:17:55.24#ibcon#read 5, iclass 15, count 0 2006.201.18:17:55.24#ibcon#about to read 6, iclass 15, count 0 2006.201.18:17:55.24#ibcon#read 6, iclass 15, count 0 2006.201.18:17:55.24#ibcon#end of sib2, iclass 15, count 0 2006.201.18:17:55.24#ibcon#*mode == 0, iclass 15, count 0 2006.201.18:17:55.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.18:17:55.24#ibcon#[27=USB\r\n] 2006.201.18:17:55.24#ibcon#*before write, iclass 15, count 0 2006.201.18:17:55.24#ibcon#enter sib2, iclass 15, count 0 2006.201.18:17:55.24#ibcon#flushed, iclass 15, count 0 2006.201.18:17:55.24#ibcon#about to write, iclass 15, count 0 2006.201.18:17:55.24#ibcon#wrote, iclass 15, count 0 2006.201.18:17:55.24#ibcon#about to read 3, iclass 15, count 0 2006.201.18:17:55.27#ibcon#read 3, iclass 15, count 0 2006.201.18:17:55.27#ibcon#about to read 4, iclass 15, count 0 2006.201.18:17:55.27#ibcon#read 4, iclass 15, count 0 2006.201.18:17:55.27#ibcon#about to read 5, iclass 15, count 0 2006.201.18:17:55.27#ibcon#read 5, iclass 15, count 0 2006.201.18:17:55.27#ibcon#about to read 6, iclass 15, count 0 2006.201.18:17:55.27#ibcon#read 6, iclass 15, count 0 2006.201.18:17:55.27#ibcon#end of sib2, iclass 15, count 0 2006.201.18:17:55.27#ibcon#*after write, iclass 15, count 0 2006.201.18:17:55.27#ibcon#*before return 0, iclass 15, count 0 2006.201.18:17:55.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:55.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:17:55.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.18:17:55.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.18:17:55.27$vck44/vabw=wide 2006.201.18:17:55.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.18:17:55.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.18:17:55.27#ibcon#ireg 8 cls_cnt 0 2006.201.18:17:55.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:55.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:55.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:55.27#ibcon#enter wrdev, iclass 17, count 0 2006.201.18:17:55.27#ibcon#first serial, iclass 17, count 0 2006.201.18:17:55.27#ibcon#enter sib2, iclass 17, count 0 2006.201.18:17:55.27#ibcon#flushed, iclass 17, count 0 2006.201.18:17:55.27#ibcon#about to write, iclass 17, count 0 2006.201.18:17:55.27#ibcon#wrote, iclass 17, count 0 2006.201.18:17:55.27#ibcon#about to read 3, iclass 17, count 0 2006.201.18:17:55.29#ibcon#read 3, iclass 17, count 0 2006.201.18:17:55.29#ibcon#about to read 4, iclass 17, count 0 2006.201.18:17:55.29#ibcon#read 4, iclass 17, count 0 2006.201.18:17:55.29#ibcon#about to read 5, iclass 17, count 0 2006.201.18:17:55.29#ibcon#read 5, iclass 17, count 0 2006.201.18:17:55.29#ibcon#about to read 6, iclass 17, count 0 2006.201.18:17:55.29#ibcon#read 6, iclass 17, count 0 2006.201.18:17:55.29#ibcon#end of sib2, iclass 17, count 0 2006.201.18:17:55.29#ibcon#*mode == 0, iclass 17, count 0 2006.201.18:17:55.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.18:17:55.29#ibcon#[25=BW32\r\n] 2006.201.18:17:55.29#ibcon#*before write, iclass 17, count 0 2006.201.18:17:55.29#ibcon#enter sib2, iclass 17, count 0 2006.201.18:17:55.29#ibcon#flushed, iclass 17, count 0 2006.201.18:17:55.29#ibcon#about to write, iclass 17, count 0 2006.201.18:17:55.29#ibcon#wrote, iclass 17, count 0 2006.201.18:17:55.29#ibcon#about to read 3, iclass 17, count 0 2006.201.18:17:55.32#ibcon#read 3, iclass 17, count 0 2006.201.18:17:55.32#ibcon#about to read 4, iclass 17, count 0 2006.201.18:17:55.32#ibcon#read 4, iclass 17, count 0 2006.201.18:17:55.32#ibcon#about to read 5, iclass 17, count 0 2006.201.18:17:55.32#ibcon#read 5, iclass 17, count 0 2006.201.18:17:55.32#ibcon#about to read 6, iclass 17, count 0 2006.201.18:17:55.32#ibcon#read 6, iclass 17, count 0 2006.201.18:17:55.32#ibcon#end of sib2, iclass 17, count 0 2006.201.18:17:55.32#ibcon#*after write, iclass 17, count 0 2006.201.18:17:55.32#ibcon#*before return 0, iclass 17, count 0 2006.201.18:17:55.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:55.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:17:55.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.18:17:55.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.18:17:55.32$vck44/vbbw=wide 2006.201.18:17:55.32#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.18:17:55.32#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.18:17:55.32#ibcon#ireg 8 cls_cnt 0 2006.201.18:17:55.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:17:55.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:17:55.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:17:55.39#ibcon#enter wrdev, iclass 19, count 0 2006.201.18:17:55.39#ibcon#first serial, iclass 19, count 0 2006.201.18:17:55.39#ibcon#enter sib2, iclass 19, count 0 2006.201.18:17:55.39#ibcon#flushed, iclass 19, count 0 2006.201.18:17:55.39#ibcon#about to write, iclass 19, count 0 2006.201.18:17:55.39#ibcon#wrote, iclass 19, count 0 2006.201.18:17:55.39#ibcon#about to read 3, iclass 19, count 0 2006.201.18:17:55.41#ibcon#read 3, iclass 19, count 0 2006.201.18:17:55.41#ibcon#about to read 4, iclass 19, count 0 2006.201.18:17:55.41#ibcon#read 4, iclass 19, count 0 2006.201.18:17:55.41#ibcon#about to read 5, iclass 19, count 0 2006.201.18:17:55.41#ibcon#read 5, iclass 19, count 0 2006.201.18:17:55.41#ibcon#about to read 6, iclass 19, count 0 2006.201.18:17:55.41#ibcon#read 6, iclass 19, count 0 2006.201.18:17:55.41#ibcon#end of sib2, iclass 19, count 0 2006.201.18:17:55.41#ibcon#*mode == 0, iclass 19, count 0 2006.201.18:17:55.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.18:17:55.41#ibcon#[27=BW32\r\n] 2006.201.18:17:55.41#ibcon#*before write, iclass 19, count 0 2006.201.18:17:55.41#ibcon#enter sib2, iclass 19, count 0 2006.201.18:17:55.41#ibcon#flushed, iclass 19, count 0 2006.201.18:17:55.41#ibcon#about to write, iclass 19, count 0 2006.201.18:17:55.41#ibcon#wrote, iclass 19, count 0 2006.201.18:17:55.41#ibcon#about to read 3, iclass 19, count 0 2006.201.18:17:55.44#ibcon#read 3, iclass 19, count 0 2006.201.18:17:55.44#ibcon#about to read 4, iclass 19, count 0 2006.201.18:17:55.44#ibcon#read 4, iclass 19, count 0 2006.201.18:17:55.44#ibcon#about to read 5, iclass 19, count 0 2006.201.18:17:55.44#ibcon#read 5, iclass 19, count 0 2006.201.18:17:55.44#ibcon#about to read 6, iclass 19, count 0 2006.201.18:17:55.44#ibcon#read 6, iclass 19, count 0 2006.201.18:17:55.44#ibcon#end of sib2, iclass 19, count 0 2006.201.18:17:55.44#ibcon#*after write, iclass 19, count 0 2006.201.18:17:55.44#ibcon#*before return 0, iclass 19, count 0 2006.201.18:17:55.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:17:55.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:17:55.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.18:17:55.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.18:17:55.44$setupk4/ifdk4 2006.201.18:17:55.44$ifdk4/lo= 2006.201.18:17:55.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:17:55.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:17:55.44$ifdk4/patch= 2006.201.18:17:55.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:17:55.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:17:55.44$setupk4/!*+20s 2006.201.18:18:01.62#abcon#<5=/16 0.6 1.4 20.491001002.1\r\n> 2006.201.18:18:01.64#abcon#{5=INTERFACE CLEAR} 2006.201.18:18:01.70#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:18:09.93$setupk4/"tpicd 2006.201.18:18:09.93$setupk4/echo=off 2006.201.18:18:09.93$setupk4/xlog=off 2006.201.18:18:09.93:!2006.201.18:20:57 2006.201.18:18:14.14#trakl#Source acquired 2006.201.18:18:16.14#flagr#flagr/antenna,acquired 2006.201.18:20:57.00:preob 2006.201.18:20:57.14/onsource/TRACKING 2006.201.18:20:57.14:!2006.201.18:21:07 2006.201.18:21:07.00:"tape 2006.201.18:21:07.00:"st=record 2006.201.18:21:07.00:data_valid=on 2006.201.18:21:07.00:midob 2006.201.18:21:07.14/onsource/TRACKING 2006.201.18:21:07.14/wx/20.48,1002.0,100 2006.201.18:21:07.21/cable/+6.4779E-03 2006.201.18:21:08.30/va/01,08,usb,yes,44,47 2006.201.18:21:08.30/va/02,07,usb,yes,48,49 2006.201.18:21:08.30/va/03,08,usb,yes,43,45 2006.201.18:21:08.30/va/04,07,usb,yes,49,52 2006.201.18:21:08.30/va/05,04,usb,yes,44,45 2006.201.18:21:08.30/va/06,05,usb,yes,44,44 2006.201.18:21:08.30/va/07,05,usb,yes,43,45 2006.201.18:21:08.30/va/08,04,usb,yes,43,50 2006.201.18:21:08.53/valo/01,524.99,yes,locked 2006.201.18:21:08.53/valo/02,534.99,yes,locked 2006.201.18:21:08.53/valo/03,564.99,yes,locked 2006.201.18:21:08.53/valo/04,624.99,yes,locked 2006.201.18:21:08.53/valo/05,734.99,yes,locked 2006.201.18:21:08.53/valo/06,814.99,yes,locked 2006.201.18:21:08.53/valo/07,864.99,yes,locked 2006.201.18:21:08.53/valo/08,884.99,yes,locked 2006.201.18:21:09.62/vb/01,04,usb,yes,33,30 2006.201.18:21:09.62/vb/02,05,usb,yes,31,31 2006.201.18:21:09.62/vb/03,04,usb,yes,33,35 2006.201.18:21:09.62/vb/04,05,usb,yes,32,31 2006.201.18:21:09.62/vb/05,04,usb,yes,29,31 2006.201.18:21:09.62/vb/06,04,usb,yes,33,29 2006.201.18:21:09.62/vb/07,04,usb,yes,33,33 2006.201.18:21:09.62/vb/08,04,usb,yes,31,34 2006.201.18:21:09.86/vblo/01,629.99,yes,locked 2006.201.18:21:09.86/vblo/02,634.99,yes,locked 2006.201.18:21:09.86/vblo/03,649.99,yes,locked 2006.201.18:21:09.86/vblo/04,679.99,yes,locked 2006.201.18:21:09.86/vblo/05,709.99,yes,locked 2006.201.18:21:09.86/vblo/06,719.99,yes,locked 2006.201.18:21:09.86/vblo/07,734.99,yes,locked 2006.201.18:21:09.86/vblo/08,744.99,yes,locked 2006.201.18:21:10.01/vabw/8 2006.201.18:21:10.16/vbbw/8 2006.201.18:21:10.25/xfe/off,on,15.5 2006.201.18:21:10.65/ifatt/23,28,28,28 2006.201.18:21:11.07/fmout-gps/S +4.58E-07 2006.201.18:21:11.11:!2006.201.18:23:27 2006.201.18:23:27.00:data_valid=off 2006.201.18:23:27.00:"et 2006.201.18:23:27.00:!+3s 2006.201.18:23:30.02:"tape 2006.201.18:23:30.02:postob 2006.201.18:23:30.21/cable/+6.4768E-03 2006.201.18:23:30.21/wx/20.48,1002.0,100 2006.201.18:23:30.29/fmout-gps/S +4.58E-07 2006.201.18:23:30.29:scan_name=201-1824,jd0607,300 2006.201.18:23:30.29:source=cta26,033930.94,-014635.8,2000.0,cw 2006.201.18:23:31.14#flagr#flagr/antenna,new-source 2006.201.18:23:31.14:checkk5 2006.201.18:23:31.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:23:31.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:23:32.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:23:32.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:23:33.01/chk_obsdata//k5ts1/T2011821??a.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.18:23:33.38/chk_obsdata//k5ts2/T2011821??b.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.18:23:33.74/chk_obsdata//k5ts3/T2011821??c.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.18:23:34.11/chk_obsdata//k5ts4/T2011821??d.dat file size is correct (nominal:560MB, actual:556MB). 2006.201.18:23:34.80/k5log//k5ts1_log_newline 2006.201.18:23:35.48/k5log//k5ts2_log_newline 2006.201.18:23:36.17/k5log//k5ts3_log_newline 2006.201.18:23:36.85/k5log//k5ts4_log_newline 2006.201.18:23:36.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:23:36.87:setupk4=1 2006.201.18:23:36.87$setupk4/echo=on 2006.201.18:23:36.87$setupk4/pcalon 2006.201.18:23:36.87$pcalon/"no phase cal control is implemented here 2006.201.18:23:36.87$setupk4/"tpicd=stop 2006.201.18:23:36.87$setupk4/"rec=synch_on 2006.201.18:23:36.87$setupk4/"rec_mode=128 2006.201.18:23:36.87$setupk4/!* 2006.201.18:23:36.87$setupk4/recpk4 2006.201.18:23:36.87$recpk4/recpatch= 2006.201.18:23:36.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:23:36.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:23:36.88$setupk4/vck44 2006.201.18:23:36.88$vck44/valo=1,524.99 2006.201.18:23:36.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.18:23:36.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.18:23:36.88#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:36.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:36.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:36.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:36.88#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:23:36.88#ibcon#first serial, iclass 12, count 0 2006.201.18:23:36.88#ibcon#enter sib2, iclass 12, count 0 2006.201.18:23:36.88#ibcon#flushed, iclass 12, count 0 2006.201.18:23:36.88#ibcon#about to write, iclass 12, count 0 2006.201.18:23:36.88#ibcon#wrote, iclass 12, count 0 2006.201.18:23:36.88#ibcon#about to read 3, iclass 12, count 0 2006.201.18:23:36.91#ibcon#read 3, iclass 12, count 0 2006.201.18:23:36.91#ibcon#about to read 4, iclass 12, count 0 2006.201.18:23:36.91#ibcon#read 4, iclass 12, count 0 2006.201.18:23:36.91#ibcon#about to read 5, iclass 12, count 0 2006.201.18:23:36.91#ibcon#read 5, iclass 12, count 0 2006.201.18:23:36.91#ibcon#about to read 6, iclass 12, count 0 2006.201.18:23:36.91#ibcon#read 6, iclass 12, count 0 2006.201.18:23:36.91#ibcon#end of sib2, iclass 12, count 0 2006.201.18:23:36.91#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:23:36.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:23:36.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:23:36.91#ibcon#*before write, iclass 12, count 0 2006.201.18:23:36.91#ibcon#enter sib2, iclass 12, count 0 2006.201.18:23:36.91#ibcon#flushed, iclass 12, count 0 2006.201.18:23:36.91#ibcon#about to write, iclass 12, count 0 2006.201.18:23:36.91#ibcon#wrote, iclass 12, count 0 2006.201.18:23:36.91#ibcon#about to read 3, iclass 12, count 0 2006.201.18:23:36.96#ibcon#read 3, iclass 12, count 0 2006.201.18:23:36.96#ibcon#about to read 4, iclass 12, count 0 2006.201.18:23:36.96#ibcon#read 4, iclass 12, count 0 2006.201.18:23:36.96#ibcon#about to read 5, iclass 12, count 0 2006.201.18:23:36.96#ibcon#read 5, iclass 12, count 0 2006.201.18:23:36.96#ibcon#about to read 6, iclass 12, count 0 2006.201.18:23:36.96#ibcon#read 6, iclass 12, count 0 2006.201.18:23:36.96#ibcon#end of sib2, iclass 12, count 0 2006.201.18:23:36.96#ibcon#*after write, iclass 12, count 0 2006.201.18:23:36.96#ibcon#*before return 0, iclass 12, count 0 2006.201.18:23:36.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:36.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:36.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:23:36.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:23:36.96$vck44/va=1,8 2006.201.18:23:36.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.18:23:36.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.18:23:36.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:36.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:36.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:36.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:36.96#ibcon#enter wrdev, iclass 14, count 2 2006.201.18:23:36.96#ibcon#first serial, iclass 14, count 2 2006.201.18:23:36.96#ibcon#enter sib2, iclass 14, count 2 2006.201.18:23:36.96#ibcon#flushed, iclass 14, count 2 2006.201.18:23:36.96#ibcon#about to write, iclass 14, count 2 2006.201.18:23:36.96#ibcon#wrote, iclass 14, count 2 2006.201.18:23:36.96#ibcon#about to read 3, iclass 14, count 2 2006.201.18:23:36.98#ibcon#read 3, iclass 14, count 2 2006.201.18:23:36.98#ibcon#about to read 4, iclass 14, count 2 2006.201.18:23:36.98#ibcon#read 4, iclass 14, count 2 2006.201.18:23:36.98#ibcon#about to read 5, iclass 14, count 2 2006.201.18:23:36.98#ibcon#read 5, iclass 14, count 2 2006.201.18:23:36.98#ibcon#about to read 6, iclass 14, count 2 2006.201.18:23:36.98#ibcon#read 6, iclass 14, count 2 2006.201.18:23:36.98#ibcon#end of sib2, iclass 14, count 2 2006.201.18:23:36.98#ibcon#*mode == 0, iclass 14, count 2 2006.201.18:23:36.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.18:23:36.98#ibcon#[25=AT01-08\r\n] 2006.201.18:23:36.98#ibcon#*before write, iclass 14, count 2 2006.201.18:23:36.98#ibcon#enter sib2, iclass 14, count 2 2006.201.18:23:36.98#ibcon#flushed, iclass 14, count 2 2006.201.18:23:36.98#ibcon#about to write, iclass 14, count 2 2006.201.18:23:36.98#ibcon#wrote, iclass 14, count 2 2006.201.18:23:36.98#ibcon#about to read 3, iclass 14, count 2 2006.201.18:23:37.01#ibcon#read 3, iclass 14, count 2 2006.201.18:23:37.01#ibcon#about to read 4, iclass 14, count 2 2006.201.18:23:37.01#ibcon#read 4, iclass 14, count 2 2006.201.18:23:37.01#ibcon#about to read 5, iclass 14, count 2 2006.201.18:23:37.01#ibcon#read 5, iclass 14, count 2 2006.201.18:23:37.01#ibcon#about to read 6, iclass 14, count 2 2006.201.18:23:37.01#ibcon#read 6, iclass 14, count 2 2006.201.18:23:37.01#ibcon#end of sib2, iclass 14, count 2 2006.201.18:23:37.01#ibcon#*after write, iclass 14, count 2 2006.201.18:23:37.01#ibcon#*before return 0, iclass 14, count 2 2006.201.18:23:37.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:37.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:37.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.18:23:37.01#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:37.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:37.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:37.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:37.13#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:23:37.13#ibcon#first serial, iclass 14, count 0 2006.201.18:23:37.13#ibcon#enter sib2, iclass 14, count 0 2006.201.18:23:37.13#ibcon#flushed, iclass 14, count 0 2006.201.18:23:37.13#ibcon#about to write, iclass 14, count 0 2006.201.18:23:37.13#ibcon#wrote, iclass 14, count 0 2006.201.18:23:37.13#ibcon#about to read 3, iclass 14, count 0 2006.201.18:23:37.15#ibcon#read 3, iclass 14, count 0 2006.201.18:23:37.15#ibcon#about to read 4, iclass 14, count 0 2006.201.18:23:37.15#ibcon#read 4, iclass 14, count 0 2006.201.18:23:37.15#ibcon#about to read 5, iclass 14, count 0 2006.201.18:23:37.15#ibcon#read 5, iclass 14, count 0 2006.201.18:23:37.15#ibcon#about to read 6, iclass 14, count 0 2006.201.18:23:37.15#ibcon#read 6, iclass 14, count 0 2006.201.18:23:37.15#ibcon#end of sib2, iclass 14, count 0 2006.201.18:23:37.15#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:23:37.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:23:37.15#ibcon#[25=USB\r\n] 2006.201.18:23:37.15#ibcon#*before write, iclass 14, count 0 2006.201.18:23:37.15#ibcon#enter sib2, iclass 14, count 0 2006.201.18:23:37.15#ibcon#flushed, iclass 14, count 0 2006.201.18:23:37.15#ibcon#about to write, iclass 14, count 0 2006.201.18:23:37.15#ibcon#wrote, iclass 14, count 0 2006.201.18:23:37.15#ibcon#about to read 3, iclass 14, count 0 2006.201.18:23:37.18#ibcon#read 3, iclass 14, count 0 2006.201.18:23:37.18#ibcon#about to read 4, iclass 14, count 0 2006.201.18:23:37.18#ibcon#read 4, iclass 14, count 0 2006.201.18:23:37.18#ibcon#about to read 5, iclass 14, count 0 2006.201.18:23:37.18#ibcon#read 5, iclass 14, count 0 2006.201.18:23:37.18#ibcon#about to read 6, iclass 14, count 0 2006.201.18:23:37.18#ibcon#read 6, iclass 14, count 0 2006.201.18:23:37.18#ibcon#end of sib2, iclass 14, count 0 2006.201.18:23:37.18#ibcon#*after write, iclass 14, count 0 2006.201.18:23:37.18#ibcon#*before return 0, iclass 14, count 0 2006.201.18:23:37.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:37.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:37.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:23:37.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:23:37.18$vck44/valo=2,534.99 2006.201.18:23:37.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.18:23:37.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.18:23:37.18#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:37.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:37.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:37.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:37.18#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:23:37.18#ibcon#first serial, iclass 16, count 0 2006.201.18:23:37.18#ibcon#enter sib2, iclass 16, count 0 2006.201.18:23:37.18#ibcon#flushed, iclass 16, count 0 2006.201.18:23:37.18#ibcon#about to write, iclass 16, count 0 2006.201.18:23:37.18#ibcon#wrote, iclass 16, count 0 2006.201.18:23:37.18#ibcon#about to read 3, iclass 16, count 0 2006.201.18:23:37.20#ibcon#read 3, iclass 16, count 0 2006.201.18:23:37.20#ibcon#about to read 4, iclass 16, count 0 2006.201.18:23:37.20#ibcon#read 4, iclass 16, count 0 2006.201.18:23:37.20#ibcon#about to read 5, iclass 16, count 0 2006.201.18:23:37.20#ibcon#read 5, iclass 16, count 0 2006.201.18:23:37.20#ibcon#about to read 6, iclass 16, count 0 2006.201.18:23:37.20#ibcon#read 6, iclass 16, count 0 2006.201.18:23:37.20#ibcon#end of sib2, iclass 16, count 0 2006.201.18:23:37.20#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:23:37.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:23:37.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:23:37.20#ibcon#*before write, iclass 16, count 0 2006.201.18:23:37.20#ibcon#enter sib2, iclass 16, count 0 2006.201.18:23:37.20#ibcon#flushed, iclass 16, count 0 2006.201.18:23:37.20#ibcon#about to write, iclass 16, count 0 2006.201.18:23:37.20#ibcon#wrote, iclass 16, count 0 2006.201.18:23:37.20#ibcon#about to read 3, iclass 16, count 0 2006.201.18:23:37.25#ibcon#read 3, iclass 16, count 0 2006.201.18:23:37.25#ibcon#about to read 4, iclass 16, count 0 2006.201.18:23:37.25#ibcon#read 4, iclass 16, count 0 2006.201.18:23:37.25#ibcon#about to read 5, iclass 16, count 0 2006.201.18:23:37.25#ibcon#read 5, iclass 16, count 0 2006.201.18:23:37.25#ibcon#about to read 6, iclass 16, count 0 2006.201.18:23:37.25#ibcon#read 6, iclass 16, count 0 2006.201.18:23:37.25#ibcon#end of sib2, iclass 16, count 0 2006.201.18:23:37.25#ibcon#*after write, iclass 16, count 0 2006.201.18:23:37.25#ibcon#*before return 0, iclass 16, count 0 2006.201.18:23:37.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:37.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:37.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:23:37.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:23:37.25$vck44/va=2,7 2006.201.18:23:37.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.18:23:37.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.18:23:37.25#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:37.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:37.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:37.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:37.30#ibcon#enter wrdev, iclass 18, count 2 2006.201.18:23:37.30#ibcon#first serial, iclass 18, count 2 2006.201.18:23:37.30#ibcon#enter sib2, iclass 18, count 2 2006.201.18:23:37.30#ibcon#flushed, iclass 18, count 2 2006.201.18:23:37.30#ibcon#about to write, iclass 18, count 2 2006.201.18:23:37.30#ibcon#wrote, iclass 18, count 2 2006.201.18:23:37.30#ibcon#about to read 3, iclass 18, count 2 2006.201.18:23:37.32#ibcon#read 3, iclass 18, count 2 2006.201.18:23:37.32#ibcon#about to read 4, iclass 18, count 2 2006.201.18:23:37.32#ibcon#read 4, iclass 18, count 2 2006.201.18:23:37.32#ibcon#about to read 5, iclass 18, count 2 2006.201.18:23:37.32#ibcon#read 5, iclass 18, count 2 2006.201.18:23:37.32#ibcon#about to read 6, iclass 18, count 2 2006.201.18:23:37.32#ibcon#read 6, iclass 18, count 2 2006.201.18:23:37.32#ibcon#end of sib2, iclass 18, count 2 2006.201.18:23:37.32#ibcon#*mode == 0, iclass 18, count 2 2006.201.18:23:37.32#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.18:23:37.32#ibcon#[25=AT02-07\r\n] 2006.201.18:23:37.32#ibcon#*before write, iclass 18, count 2 2006.201.18:23:37.32#ibcon#enter sib2, iclass 18, count 2 2006.201.18:23:37.32#ibcon#flushed, iclass 18, count 2 2006.201.18:23:37.32#ibcon#about to write, iclass 18, count 2 2006.201.18:23:37.32#ibcon#wrote, iclass 18, count 2 2006.201.18:23:37.32#ibcon#about to read 3, iclass 18, count 2 2006.201.18:23:37.35#ibcon#read 3, iclass 18, count 2 2006.201.18:23:37.35#ibcon#about to read 4, iclass 18, count 2 2006.201.18:23:37.35#ibcon#read 4, iclass 18, count 2 2006.201.18:23:37.35#ibcon#about to read 5, iclass 18, count 2 2006.201.18:23:37.35#ibcon#read 5, iclass 18, count 2 2006.201.18:23:37.35#ibcon#about to read 6, iclass 18, count 2 2006.201.18:23:37.35#ibcon#read 6, iclass 18, count 2 2006.201.18:23:37.35#ibcon#end of sib2, iclass 18, count 2 2006.201.18:23:37.35#ibcon#*after write, iclass 18, count 2 2006.201.18:23:37.35#ibcon#*before return 0, iclass 18, count 2 2006.201.18:23:37.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:37.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:37.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.18:23:37.35#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:37.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:37.37#abcon#<5=/02 0.6 1.4 20.481001002.0\r\n> 2006.201.18:23:37.39#abcon#{5=INTERFACE CLEAR} 2006.201.18:23:37.45#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:23:37.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:37.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:37.47#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:23:37.47#ibcon#first serial, iclass 18, count 0 2006.201.18:23:37.47#ibcon#enter sib2, iclass 18, count 0 2006.201.18:23:37.47#ibcon#flushed, iclass 18, count 0 2006.201.18:23:37.47#ibcon#about to write, iclass 18, count 0 2006.201.18:23:37.47#ibcon#wrote, iclass 18, count 0 2006.201.18:23:37.47#ibcon#about to read 3, iclass 18, count 0 2006.201.18:23:37.49#ibcon#read 3, iclass 18, count 0 2006.201.18:23:37.49#ibcon#about to read 4, iclass 18, count 0 2006.201.18:23:37.49#ibcon#read 4, iclass 18, count 0 2006.201.18:23:37.49#ibcon#about to read 5, iclass 18, count 0 2006.201.18:23:37.49#ibcon#read 5, iclass 18, count 0 2006.201.18:23:37.50#ibcon#about to read 6, iclass 18, count 0 2006.201.18:23:37.50#ibcon#read 6, iclass 18, count 0 2006.201.18:23:37.50#ibcon#end of sib2, iclass 18, count 0 2006.201.18:23:37.50#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:23:37.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:23:37.50#ibcon#[25=USB\r\n] 2006.201.18:23:37.50#ibcon#*before write, iclass 18, count 0 2006.201.18:23:37.50#ibcon#enter sib2, iclass 18, count 0 2006.201.18:23:37.50#ibcon#flushed, iclass 18, count 0 2006.201.18:23:37.50#ibcon#about to write, iclass 18, count 0 2006.201.18:23:37.50#ibcon#wrote, iclass 18, count 0 2006.201.18:23:37.50#ibcon#about to read 3, iclass 18, count 0 2006.201.18:23:37.53#ibcon#read 3, iclass 18, count 0 2006.201.18:23:37.53#ibcon#about to read 4, iclass 18, count 0 2006.201.18:23:37.53#ibcon#read 4, iclass 18, count 0 2006.201.18:23:37.53#ibcon#about to read 5, iclass 18, count 0 2006.201.18:23:37.53#ibcon#read 5, iclass 18, count 0 2006.201.18:23:37.53#ibcon#about to read 6, iclass 18, count 0 2006.201.18:23:37.53#ibcon#read 6, iclass 18, count 0 2006.201.18:23:37.53#ibcon#end of sib2, iclass 18, count 0 2006.201.18:23:37.53#ibcon#*after write, iclass 18, count 0 2006.201.18:23:37.53#ibcon#*before return 0, iclass 18, count 0 2006.201.18:23:37.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:37.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:37.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:23:37.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:23:37.53$vck44/valo=3,564.99 2006.201.18:23:37.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.18:23:37.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.18:23:37.53#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:37.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:37.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:37.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:37.53#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:23:37.53#ibcon#first serial, iclass 24, count 0 2006.201.18:23:37.53#ibcon#enter sib2, iclass 24, count 0 2006.201.18:23:37.53#ibcon#flushed, iclass 24, count 0 2006.201.18:23:37.53#ibcon#about to write, iclass 24, count 0 2006.201.18:23:37.53#ibcon#wrote, iclass 24, count 0 2006.201.18:23:37.53#ibcon#about to read 3, iclass 24, count 0 2006.201.18:23:37.55#ibcon#read 3, iclass 24, count 0 2006.201.18:23:37.55#ibcon#about to read 4, iclass 24, count 0 2006.201.18:23:37.55#ibcon#read 4, iclass 24, count 0 2006.201.18:23:37.55#ibcon#about to read 5, iclass 24, count 0 2006.201.18:23:37.55#ibcon#read 5, iclass 24, count 0 2006.201.18:23:37.55#ibcon#about to read 6, iclass 24, count 0 2006.201.18:23:37.55#ibcon#read 6, iclass 24, count 0 2006.201.18:23:37.55#ibcon#end of sib2, iclass 24, count 0 2006.201.18:23:37.55#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:23:37.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:23:37.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:23:37.55#ibcon#*before write, iclass 24, count 0 2006.201.18:23:37.55#ibcon#enter sib2, iclass 24, count 0 2006.201.18:23:37.55#ibcon#flushed, iclass 24, count 0 2006.201.18:23:37.55#ibcon#about to write, iclass 24, count 0 2006.201.18:23:37.55#ibcon#wrote, iclass 24, count 0 2006.201.18:23:37.55#ibcon#about to read 3, iclass 24, count 0 2006.201.18:23:37.59#ibcon#read 3, iclass 24, count 0 2006.201.18:23:37.59#ibcon#about to read 4, iclass 24, count 0 2006.201.18:23:37.59#ibcon#read 4, iclass 24, count 0 2006.201.18:23:37.59#ibcon#about to read 5, iclass 24, count 0 2006.201.18:23:37.59#ibcon#read 5, iclass 24, count 0 2006.201.18:23:37.59#ibcon#about to read 6, iclass 24, count 0 2006.201.18:23:37.59#ibcon#read 6, iclass 24, count 0 2006.201.18:23:37.59#ibcon#end of sib2, iclass 24, count 0 2006.201.18:23:37.59#ibcon#*after write, iclass 24, count 0 2006.201.18:23:37.59#ibcon#*before return 0, iclass 24, count 0 2006.201.18:23:37.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:37.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:37.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:23:37.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:23:37.59$vck44/va=3,8 2006.201.18:23:37.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.18:23:37.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.18:23:37.59#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:37.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:37.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:37.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:37.65#ibcon#enter wrdev, iclass 26, count 2 2006.201.18:23:37.65#ibcon#first serial, iclass 26, count 2 2006.201.18:23:37.65#ibcon#enter sib2, iclass 26, count 2 2006.201.18:23:37.65#ibcon#flushed, iclass 26, count 2 2006.201.18:23:37.65#ibcon#about to write, iclass 26, count 2 2006.201.18:23:37.65#ibcon#wrote, iclass 26, count 2 2006.201.18:23:37.65#ibcon#about to read 3, iclass 26, count 2 2006.201.18:23:37.67#ibcon#read 3, iclass 26, count 2 2006.201.18:23:37.67#ibcon#about to read 4, iclass 26, count 2 2006.201.18:23:37.67#ibcon#read 4, iclass 26, count 2 2006.201.18:23:37.67#ibcon#about to read 5, iclass 26, count 2 2006.201.18:23:37.67#ibcon#read 5, iclass 26, count 2 2006.201.18:23:37.67#ibcon#about to read 6, iclass 26, count 2 2006.201.18:23:37.67#ibcon#read 6, iclass 26, count 2 2006.201.18:23:37.67#ibcon#end of sib2, iclass 26, count 2 2006.201.18:23:37.67#ibcon#*mode == 0, iclass 26, count 2 2006.201.18:23:37.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.18:23:37.67#ibcon#[25=AT03-08\r\n] 2006.201.18:23:37.67#ibcon#*before write, iclass 26, count 2 2006.201.18:23:37.67#ibcon#enter sib2, iclass 26, count 2 2006.201.18:23:37.67#ibcon#flushed, iclass 26, count 2 2006.201.18:23:37.67#ibcon#about to write, iclass 26, count 2 2006.201.18:23:37.67#ibcon#wrote, iclass 26, count 2 2006.201.18:23:37.67#ibcon#about to read 3, iclass 26, count 2 2006.201.18:23:37.71#ibcon#read 3, iclass 26, count 2 2006.201.18:23:37.71#ibcon#about to read 4, iclass 26, count 2 2006.201.18:23:37.71#ibcon#read 4, iclass 26, count 2 2006.201.18:23:37.71#ibcon#about to read 5, iclass 26, count 2 2006.201.18:23:37.71#ibcon#read 5, iclass 26, count 2 2006.201.18:23:37.71#ibcon#about to read 6, iclass 26, count 2 2006.201.18:23:37.71#ibcon#read 6, iclass 26, count 2 2006.201.18:23:37.71#ibcon#end of sib2, iclass 26, count 2 2006.201.18:23:37.71#ibcon#*after write, iclass 26, count 2 2006.201.18:23:37.71#ibcon#*before return 0, iclass 26, count 2 2006.201.18:23:37.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:37.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:37.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.18:23:37.71#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:37.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:37.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:37.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:37.83#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:23:37.83#ibcon#first serial, iclass 26, count 0 2006.201.18:23:37.83#ibcon#enter sib2, iclass 26, count 0 2006.201.18:23:37.83#ibcon#flushed, iclass 26, count 0 2006.201.18:23:37.83#ibcon#about to write, iclass 26, count 0 2006.201.18:23:37.83#ibcon#wrote, iclass 26, count 0 2006.201.18:23:37.83#ibcon#about to read 3, iclass 26, count 0 2006.201.18:23:37.85#ibcon#read 3, iclass 26, count 0 2006.201.18:23:37.85#ibcon#about to read 4, iclass 26, count 0 2006.201.18:23:37.85#ibcon#read 4, iclass 26, count 0 2006.201.18:23:37.85#ibcon#about to read 5, iclass 26, count 0 2006.201.18:23:37.85#ibcon#read 5, iclass 26, count 0 2006.201.18:23:37.85#ibcon#about to read 6, iclass 26, count 0 2006.201.18:23:37.85#ibcon#read 6, iclass 26, count 0 2006.201.18:23:37.85#ibcon#end of sib2, iclass 26, count 0 2006.201.18:23:37.85#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:23:37.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:23:37.85#ibcon#[25=USB\r\n] 2006.201.18:23:37.85#ibcon#*before write, iclass 26, count 0 2006.201.18:23:37.85#ibcon#enter sib2, iclass 26, count 0 2006.201.18:23:37.85#ibcon#flushed, iclass 26, count 0 2006.201.18:23:37.85#ibcon#about to write, iclass 26, count 0 2006.201.18:23:37.85#ibcon#wrote, iclass 26, count 0 2006.201.18:23:37.85#ibcon#about to read 3, iclass 26, count 0 2006.201.18:23:37.88#ibcon#read 3, iclass 26, count 0 2006.201.18:23:37.88#ibcon#about to read 4, iclass 26, count 0 2006.201.18:23:37.88#ibcon#read 4, iclass 26, count 0 2006.201.18:23:37.88#ibcon#about to read 5, iclass 26, count 0 2006.201.18:23:37.88#ibcon#read 5, iclass 26, count 0 2006.201.18:23:37.88#ibcon#about to read 6, iclass 26, count 0 2006.201.18:23:37.88#ibcon#read 6, iclass 26, count 0 2006.201.18:23:37.88#ibcon#end of sib2, iclass 26, count 0 2006.201.18:23:37.88#ibcon#*after write, iclass 26, count 0 2006.201.18:23:37.88#ibcon#*before return 0, iclass 26, count 0 2006.201.18:23:37.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:37.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:37.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:23:37.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:23:37.88$vck44/valo=4,624.99 2006.201.18:23:37.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.18:23:37.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.18:23:37.88#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:37.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:37.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:37.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:37.88#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:23:37.88#ibcon#first serial, iclass 28, count 0 2006.201.18:23:37.88#ibcon#enter sib2, iclass 28, count 0 2006.201.18:23:37.88#ibcon#flushed, iclass 28, count 0 2006.201.18:23:37.88#ibcon#about to write, iclass 28, count 0 2006.201.18:23:37.88#ibcon#wrote, iclass 28, count 0 2006.201.18:23:37.88#ibcon#about to read 3, iclass 28, count 0 2006.201.18:23:37.90#ibcon#read 3, iclass 28, count 0 2006.201.18:23:37.90#ibcon#about to read 4, iclass 28, count 0 2006.201.18:23:37.90#ibcon#read 4, iclass 28, count 0 2006.201.18:23:37.90#ibcon#about to read 5, iclass 28, count 0 2006.201.18:23:37.90#ibcon#read 5, iclass 28, count 0 2006.201.18:23:37.90#ibcon#about to read 6, iclass 28, count 0 2006.201.18:23:37.90#ibcon#read 6, iclass 28, count 0 2006.201.18:23:37.90#ibcon#end of sib2, iclass 28, count 0 2006.201.18:23:37.90#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:23:37.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:23:37.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:23:37.90#ibcon#*before write, iclass 28, count 0 2006.201.18:23:37.90#ibcon#enter sib2, iclass 28, count 0 2006.201.18:23:37.90#ibcon#flushed, iclass 28, count 0 2006.201.18:23:37.90#ibcon#about to write, iclass 28, count 0 2006.201.18:23:37.90#ibcon#wrote, iclass 28, count 0 2006.201.18:23:37.90#ibcon#about to read 3, iclass 28, count 0 2006.201.18:23:37.95#ibcon#read 3, iclass 28, count 0 2006.201.18:23:37.95#ibcon#about to read 4, iclass 28, count 0 2006.201.18:23:37.95#ibcon#read 4, iclass 28, count 0 2006.201.18:23:37.95#ibcon#about to read 5, iclass 28, count 0 2006.201.18:23:37.95#ibcon#read 5, iclass 28, count 0 2006.201.18:23:37.95#ibcon#about to read 6, iclass 28, count 0 2006.201.18:23:37.95#ibcon#read 6, iclass 28, count 0 2006.201.18:23:37.95#ibcon#end of sib2, iclass 28, count 0 2006.201.18:23:37.95#ibcon#*after write, iclass 28, count 0 2006.201.18:23:37.95#ibcon#*before return 0, iclass 28, count 0 2006.201.18:23:37.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:37.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:37.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:23:37.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:23:37.95$vck44/va=4,7 2006.201.18:23:37.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.18:23:37.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.18:23:37.95#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:37.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:38.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:38.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:38.00#ibcon#enter wrdev, iclass 30, count 2 2006.201.18:23:38.00#ibcon#first serial, iclass 30, count 2 2006.201.18:23:38.00#ibcon#enter sib2, iclass 30, count 2 2006.201.18:23:38.00#ibcon#flushed, iclass 30, count 2 2006.201.18:23:38.00#ibcon#about to write, iclass 30, count 2 2006.201.18:23:38.00#ibcon#wrote, iclass 30, count 2 2006.201.18:23:38.00#ibcon#about to read 3, iclass 30, count 2 2006.201.18:23:38.02#ibcon#read 3, iclass 30, count 2 2006.201.18:23:38.02#ibcon#about to read 4, iclass 30, count 2 2006.201.18:23:38.02#ibcon#read 4, iclass 30, count 2 2006.201.18:23:38.02#ibcon#about to read 5, iclass 30, count 2 2006.201.18:23:38.02#ibcon#read 5, iclass 30, count 2 2006.201.18:23:38.02#ibcon#about to read 6, iclass 30, count 2 2006.201.18:23:38.02#ibcon#read 6, iclass 30, count 2 2006.201.18:23:38.02#ibcon#end of sib2, iclass 30, count 2 2006.201.18:23:38.02#ibcon#*mode == 0, iclass 30, count 2 2006.201.18:23:38.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.18:23:38.02#ibcon#[25=AT04-07\r\n] 2006.201.18:23:38.02#ibcon#*before write, iclass 30, count 2 2006.201.18:23:38.02#ibcon#enter sib2, iclass 30, count 2 2006.201.18:23:38.02#ibcon#flushed, iclass 30, count 2 2006.201.18:23:38.02#ibcon#about to write, iclass 30, count 2 2006.201.18:23:38.02#ibcon#wrote, iclass 30, count 2 2006.201.18:23:38.02#ibcon#about to read 3, iclass 30, count 2 2006.201.18:23:38.05#ibcon#read 3, iclass 30, count 2 2006.201.18:23:38.05#ibcon#about to read 4, iclass 30, count 2 2006.201.18:23:38.05#ibcon#read 4, iclass 30, count 2 2006.201.18:23:38.05#ibcon#about to read 5, iclass 30, count 2 2006.201.18:23:38.05#ibcon#read 5, iclass 30, count 2 2006.201.18:23:38.05#ibcon#about to read 6, iclass 30, count 2 2006.201.18:23:38.05#ibcon#read 6, iclass 30, count 2 2006.201.18:23:38.05#ibcon#end of sib2, iclass 30, count 2 2006.201.18:23:38.05#ibcon#*after write, iclass 30, count 2 2006.201.18:23:38.05#ibcon#*before return 0, iclass 30, count 2 2006.201.18:23:38.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:38.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:38.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.18:23:38.05#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:38.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:38.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:38.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:38.17#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:23:38.17#ibcon#first serial, iclass 30, count 0 2006.201.18:23:38.17#ibcon#enter sib2, iclass 30, count 0 2006.201.18:23:38.17#ibcon#flushed, iclass 30, count 0 2006.201.18:23:38.17#ibcon#about to write, iclass 30, count 0 2006.201.18:23:38.17#ibcon#wrote, iclass 30, count 0 2006.201.18:23:38.17#ibcon#about to read 3, iclass 30, count 0 2006.201.18:23:38.19#ibcon#read 3, iclass 30, count 0 2006.201.18:23:38.19#ibcon#about to read 4, iclass 30, count 0 2006.201.18:23:38.19#ibcon#read 4, iclass 30, count 0 2006.201.18:23:38.19#ibcon#about to read 5, iclass 30, count 0 2006.201.18:23:38.19#ibcon#read 5, iclass 30, count 0 2006.201.18:23:38.19#ibcon#about to read 6, iclass 30, count 0 2006.201.18:23:38.19#ibcon#read 6, iclass 30, count 0 2006.201.18:23:38.19#ibcon#end of sib2, iclass 30, count 0 2006.201.18:23:38.19#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:23:38.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:23:38.19#ibcon#[25=USB\r\n] 2006.201.18:23:38.19#ibcon#*before write, iclass 30, count 0 2006.201.18:23:38.19#ibcon#enter sib2, iclass 30, count 0 2006.201.18:23:38.19#ibcon#flushed, iclass 30, count 0 2006.201.18:23:38.19#ibcon#about to write, iclass 30, count 0 2006.201.18:23:38.19#ibcon#wrote, iclass 30, count 0 2006.201.18:23:38.19#ibcon#about to read 3, iclass 30, count 0 2006.201.18:23:38.22#ibcon#read 3, iclass 30, count 0 2006.201.18:23:38.22#ibcon#about to read 4, iclass 30, count 0 2006.201.18:23:38.22#ibcon#read 4, iclass 30, count 0 2006.201.18:23:38.22#ibcon#about to read 5, iclass 30, count 0 2006.201.18:23:38.22#ibcon#read 5, iclass 30, count 0 2006.201.18:23:38.22#ibcon#about to read 6, iclass 30, count 0 2006.201.18:23:38.22#ibcon#read 6, iclass 30, count 0 2006.201.18:23:38.22#ibcon#end of sib2, iclass 30, count 0 2006.201.18:23:38.22#ibcon#*after write, iclass 30, count 0 2006.201.18:23:38.22#ibcon#*before return 0, iclass 30, count 0 2006.201.18:23:38.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:38.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:38.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:23:38.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:23:38.22$vck44/valo=5,734.99 2006.201.18:23:38.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.18:23:38.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.18:23:38.22#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:38.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:38.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:38.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:38.22#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:23:38.22#ibcon#first serial, iclass 32, count 0 2006.201.18:23:38.22#ibcon#enter sib2, iclass 32, count 0 2006.201.18:23:38.22#ibcon#flushed, iclass 32, count 0 2006.201.18:23:38.22#ibcon#about to write, iclass 32, count 0 2006.201.18:23:38.22#ibcon#wrote, iclass 32, count 0 2006.201.18:23:38.22#ibcon#about to read 3, iclass 32, count 0 2006.201.18:23:38.24#ibcon#read 3, iclass 32, count 0 2006.201.18:23:38.24#ibcon#about to read 4, iclass 32, count 0 2006.201.18:23:38.24#ibcon#read 4, iclass 32, count 0 2006.201.18:23:38.24#ibcon#about to read 5, iclass 32, count 0 2006.201.18:23:38.24#ibcon#read 5, iclass 32, count 0 2006.201.18:23:38.24#ibcon#about to read 6, iclass 32, count 0 2006.201.18:23:38.24#ibcon#read 6, iclass 32, count 0 2006.201.18:23:38.24#ibcon#end of sib2, iclass 32, count 0 2006.201.18:23:38.24#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:23:38.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:23:38.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:23:38.24#ibcon#*before write, iclass 32, count 0 2006.201.18:23:38.24#ibcon#enter sib2, iclass 32, count 0 2006.201.18:23:38.24#ibcon#flushed, iclass 32, count 0 2006.201.18:23:38.24#ibcon#about to write, iclass 32, count 0 2006.201.18:23:38.24#ibcon#wrote, iclass 32, count 0 2006.201.18:23:38.24#ibcon#about to read 3, iclass 32, count 0 2006.201.18:23:38.28#ibcon#read 3, iclass 32, count 0 2006.201.18:23:38.28#ibcon#about to read 4, iclass 32, count 0 2006.201.18:23:38.28#ibcon#read 4, iclass 32, count 0 2006.201.18:23:38.28#ibcon#about to read 5, iclass 32, count 0 2006.201.18:23:38.28#ibcon#read 5, iclass 32, count 0 2006.201.18:23:38.28#ibcon#about to read 6, iclass 32, count 0 2006.201.18:23:38.28#ibcon#read 6, iclass 32, count 0 2006.201.18:23:38.28#ibcon#end of sib2, iclass 32, count 0 2006.201.18:23:38.28#ibcon#*after write, iclass 32, count 0 2006.201.18:23:38.28#ibcon#*before return 0, iclass 32, count 0 2006.201.18:23:38.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:38.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:38.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:23:38.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:23:38.28$vck44/va=5,4 2006.201.18:23:38.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.18:23:38.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.18:23:38.28#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:38.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:38.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:38.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:38.34#ibcon#enter wrdev, iclass 34, count 2 2006.201.18:23:38.34#ibcon#first serial, iclass 34, count 2 2006.201.18:23:38.34#ibcon#enter sib2, iclass 34, count 2 2006.201.18:23:38.34#ibcon#flushed, iclass 34, count 2 2006.201.18:23:38.34#ibcon#about to write, iclass 34, count 2 2006.201.18:23:38.34#ibcon#wrote, iclass 34, count 2 2006.201.18:23:38.34#ibcon#about to read 3, iclass 34, count 2 2006.201.18:23:38.36#ibcon#read 3, iclass 34, count 2 2006.201.18:23:38.36#ibcon#about to read 4, iclass 34, count 2 2006.201.18:23:38.36#ibcon#read 4, iclass 34, count 2 2006.201.18:23:38.36#ibcon#about to read 5, iclass 34, count 2 2006.201.18:23:38.36#ibcon#read 5, iclass 34, count 2 2006.201.18:23:38.36#ibcon#about to read 6, iclass 34, count 2 2006.201.18:23:38.36#ibcon#read 6, iclass 34, count 2 2006.201.18:23:38.36#ibcon#end of sib2, iclass 34, count 2 2006.201.18:23:38.36#ibcon#*mode == 0, iclass 34, count 2 2006.201.18:23:38.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.18:23:38.36#ibcon#[25=AT05-04\r\n] 2006.201.18:23:38.36#ibcon#*before write, iclass 34, count 2 2006.201.18:23:38.36#ibcon#enter sib2, iclass 34, count 2 2006.201.18:23:38.36#ibcon#flushed, iclass 34, count 2 2006.201.18:23:38.36#ibcon#about to write, iclass 34, count 2 2006.201.18:23:38.36#ibcon#wrote, iclass 34, count 2 2006.201.18:23:38.36#ibcon#about to read 3, iclass 34, count 2 2006.201.18:23:38.39#ibcon#read 3, iclass 34, count 2 2006.201.18:23:38.39#ibcon#about to read 4, iclass 34, count 2 2006.201.18:23:38.39#ibcon#read 4, iclass 34, count 2 2006.201.18:23:38.39#ibcon#about to read 5, iclass 34, count 2 2006.201.18:23:38.39#ibcon#read 5, iclass 34, count 2 2006.201.18:23:38.39#ibcon#about to read 6, iclass 34, count 2 2006.201.18:23:38.39#ibcon#read 6, iclass 34, count 2 2006.201.18:23:38.39#ibcon#end of sib2, iclass 34, count 2 2006.201.18:23:38.39#ibcon#*after write, iclass 34, count 2 2006.201.18:23:38.39#ibcon#*before return 0, iclass 34, count 2 2006.201.18:23:38.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:38.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:38.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.18:23:38.39#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:38.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:38.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:38.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:38.51#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:23:38.51#ibcon#first serial, iclass 34, count 0 2006.201.18:23:38.51#ibcon#enter sib2, iclass 34, count 0 2006.201.18:23:38.51#ibcon#flushed, iclass 34, count 0 2006.201.18:23:38.51#ibcon#about to write, iclass 34, count 0 2006.201.18:23:38.51#ibcon#wrote, iclass 34, count 0 2006.201.18:23:38.51#ibcon#about to read 3, iclass 34, count 0 2006.201.18:23:38.53#ibcon#read 3, iclass 34, count 0 2006.201.18:23:38.53#ibcon#about to read 4, iclass 34, count 0 2006.201.18:23:38.53#ibcon#read 4, iclass 34, count 0 2006.201.18:23:38.53#ibcon#about to read 5, iclass 34, count 0 2006.201.18:23:38.53#ibcon#read 5, iclass 34, count 0 2006.201.18:23:38.53#ibcon#about to read 6, iclass 34, count 0 2006.201.18:23:38.53#ibcon#read 6, iclass 34, count 0 2006.201.18:23:38.53#ibcon#end of sib2, iclass 34, count 0 2006.201.18:23:38.53#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:23:38.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:23:38.53#ibcon#[25=USB\r\n] 2006.201.18:23:38.53#ibcon#*before write, iclass 34, count 0 2006.201.18:23:38.53#ibcon#enter sib2, iclass 34, count 0 2006.201.18:23:38.53#ibcon#flushed, iclass 34, count 0 2006.201.18:23:38.53#ibcon#about to write, iclass 34, count 0 2006.201.18:23:38.53#ibcon#wrote, iclass 34, count 0 2006.201.18:23:38.53#ibcon#about to read 3, iclass 34, count 0 2006.201.18:23:38.56#ibcon#read 3, iclass 34, count 0 2006.201.18:23:38.56#ibcon#about to read 4, iclass 34, count 0 2006.201.18:23:38.56#ibcon#read 4, iclass 34, count 0 2006.201.18:23:38.56#ibcon#about to read 5, iclass 34, count 0 2006.201.18:23:38.56#ibcon#read 5, iclass 34, count 0 2006.201.18:23:38.56#ibcon#about to read 6, iclass 34, count 0 2006.201.18:23:38.56#ibcon#read 6, iclass 34, count 0 2006.201.18:23:38.56#ibcon#end of sib2, iclass 34, count 0 2006.201.18:23:38.56#ibcon#*after write, iclass 34, count 0 2006.201.18:23:38.56#ibcon#*before return 0, iclass 34, count 0 2006.201.18:23:38.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:38.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:38.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:23:38.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:23:38.56$vck44/valo=6,814.99 2006.201.18:23:38.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.18:23:38.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.18:23:38.56#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:38.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:38.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:38.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:38.56#ibcon#enter wrdev, iclass 36, count 0 2006.201.18:23:38.56#ibcon#first serial, iclass 36, count 0 2006.201.18:23:38.56#ibcon#enter sib2, iclass 36, count 0 2006.201.18:23:38.56#ibcon#flushed, iclass 36, count 0 2006.201.18:23:38.56#ibcon#about to write, iclass 36, count 0 2006.201.18:23:38.56#ibcon#wrote, iclass 36, count 0 2006.201.18:23:38.56#ibcon#about to read 3, iclass 36, count 0 2006.201.18:23:38.58#ibcon#read 3, iclass 36, count 0 2006.201.18:23:38.58#ibcon#about to read 4, iclass 36, count 0 2006.201.18:23:38.58#ibcon#read 4, iclass 36, count 0 2006.201.18:23:38.58#ibcon#about to read 5, iclass 36, count 0 2006.201.18:23:38.58#ibcon#read 5, iclass 36, count 0 2006.201.18:23:38.58#ibcon#about to read 6, iclass 36, count 0 2006.201.18:23:38.58#ibcon#read 6, iclass 36, count 0 2006.201.18:23:38.58#ibcon#end of sib2, iclass 36, count 0 2006.201.18:23:38.58#ibcon#*mode == 0, iclass 36, count 0 2006.201.18:23:38.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.18:23:38.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:23:38.58#ibcon#*before write, iclass 36, count 0 2006.201.18:23:38.58#ibcon#enter sib2, iclass 36, count 0 2006.201.18:23:38.58#ibcon#flushed, iclass 36, count 0 2006.201.18:23:38.58#ibcon#about to write, iclass 36, count 0 2006.201.18:23:38.58#ibcon#wrote, iclass 36, count 0 2006.201.18:23:38.58#ibcon#about to read 3, iclass 36, count 0 2006.201.18:23:38.63#ibcon#read 3, iclass 36, count 0 2006.201.18:23:38.63#ibcon#about to read 4, iclass 36, count 0 2006.201.18:23:38.63#ibcon#read 4, iclass 36, count 0 2006.201.18:23:38.63#ibcon#about to read 5, iclass 36, count 0 2006.201.18:23:38.63#ibcon#read 5, iclass 36, count 0 2006.201.18:23:38.63#ibcon#about to read 6, iclass 36, count 0 2006.201.18:23:38.63#ibcon#read 6, iclass 36, count 0 2006.201.18:23:38.63#ibcon#end of sib2, iclass 36, count 0 2006.201.18:23:38.63#ibcon#*after write, iclass 36, count 0 2006.201.18:23:38.63#ibcon#*before return 0, iclass 36, count 0 2006.201.18:23:38.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:38.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:38.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.18:23:38.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.18:23:38.63$vck44/va=6,5 2006.201.18:23:38.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.18:23:38.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.18:23:38.63#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:38.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:38.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:38.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:38.68#ibcon#enter wrdev, iclass 38, count 2 2006.201.18:23:38.68#ibcon#first serial, iclass 38, count 2 2006.201.18:23:38.68#ibcon#enter sib2, iclass 38, count 2 2006.201.18:23:38.68#ibcon#flushed, iclass 38, count 2 2006.201.18:23:38.68#ibcon#about to write, iclass 38, count 2 2006.201.18:23:38.68#ibcon#wrote, iclass 38, count 2 2006.201.18:23:38.68#ibcon#about to read 3, iclass 38, count 2 2006.201.18:23:38.70#ibcon#read 3, iclass 38, count 2 2006.201.18:23:38.70#ibcon#about to read 4, iclass 38, count 2 2006.201.18:23:38.70#ibcon#read 4, iclass 38, count 2 2006.201.18:23:38.70#ibcon#about to read 5, iclass 38, count 2 2006.201.18:23:38.70#ibcon#read 5, iclass 38, count 2 2006.201.18:23:38.70#ibcon#about to read 6, iclass 38, count 2 2006.201.18:23:38.70#ibcon#read 6, iclass 38, count 2 2006.201.18:23:38.70#ibcon#end of sib2, iclass 38, count 2 2006.201.18:23:38.70#ibcon#*mode == 0, iclass 38, count 2 2006.201.18:23:38.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.18:23:38.70#ibcon#[25=AT06-05\r\n] 2006.201.18:23:38.70#ibcon#*before write, iclass 38, count 2 2006.201.18:23:38.70#ibcon#enter sib2, iclass 38, count 2 2006.201.18:23:38.70#ibcon#flushed, iclass 38, count 2 2006.201.18:23:38.70#ibcon#about to write, iclass 38, count 2 2006.201.18:23:38.70#ibcon#wrote, iclass 38, count 2 2006.201.18:23:38.70#ibcon#about to read 3, iclass 38, count 2 2006.201.18:23:38.73#ibcon#read 3, iclass 38, count 2 2006.201.18:23:38.73#ibcon#about to read 4, iclass 38, count 2 2006.201.18:23:38.73#ibcon#read 4, iclass 38, count 2 2006.201.18:23:38.73#ibcon#about to read 5, iclass 38, count 2 2006.201.18:23:38.73#ibcon#read 5, iclass 38, count 2 2006.201.18:23:38.73#ibcon#about to read 6, iclass 38, count 2 2006.201.18:23:38.73#ibcon#read 6, iclass 38, count 2 2006.201.18:23:38.73#ibcon#end of sib2, iclass 38, count 2 2006.201.18:23:38.73#ibcon#*after write, iclass 38, count 2 2006.201.18:23:38.73#ibcon#*before return 0, iclass 38, count 2 2006.201.18:23:38.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:38.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:38.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.18:23:38.73#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:38.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:38.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:38.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:38.85#ibcon#enter wrdev, iclass 38, count 0 2006.201.18:23:38.85#ibcon#first serial, iclass 38, count 0 2006.201.18:23:38.85#ibcon#enter sib2, iclass 38, count 0 2006.201.18:23:38.85#ibcon#flushed, iclass 38, count 0 2006.201.18:23:38.85#ibcon#about to write, iclass 38, count 0 2006.201.18:23:38.85#ibcon#wrote, iclass 38, count 0 2006.201.18:23:38.85#ibcon#about to read 3, iclass 38, count 0 2006.201.18:23:38.87#ibcon#read 3, iclass 38, count 0 2006.201.18:23:38.87#ibcon#about to read 4, iclass 38, count 0 2006.201.18:23:38.87#ibcon#read 4, iclass 38, count 0 2006.201.18:23:38.87#ibcon#about to read 5, iclass 38, count 0 2006.201.18:23:38.87#ibcon#read 5, iclass 38, count 0 2006.201.18:23:38.87#ibcon#about to read 6, iclass 38, count 0 2006.201.18:23:38.87#ibcon#read 6, iclass 38, count 0 2006.201.18:23:38.87#ibcon#end of sib2, iclass 38, count 0 2006.201.18:23:38.87#ibcon#*mode == 0, iclass 38, count 0 2006.201.18:23:38.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.18:23:38.87#ibcon#[25=USB\r\n] 2006.201.18:23:38.87#ibcon#*before write, iclass 38, count 0 2006.201.18:23:38.87#ibcon#enter sib2, iclass 38, count 0 2006.201.18:23:38.87#ibcon#flushed, iclass 38, count 0 2006.201.18:23:38.87#ibcon#about to write, iclass 38, count 0 2006.201.18:23:38.87#ibcon#wrote, iclass 38, count 0 2006.201.18:23:38.87#ibcon#about to read 3, iclass 38, count 0 2006.201.18:23:38.90#ibcon#read 3, iclass 38, count 0 2006.201.18:23:38.90#ibcon#about to read 4, iclass 38, count 0 2006.201.18:23:38.90#ibcon#read 4, iclass 38, count 0 2006.201.18:23:38.90#ibcon#about to read 5, iclass 38, count 0 2006.201.18:23:38.90#ibcon#read 5, iclass 38, count 0 2006.201.18:23:38.90#ibcon#about to read 6, iclass 38, count 0 2006.201.18:23:38.90#ibcon#read 6, iclass 38, count 0 2006.201.18:23:38.90#ibcon#end of sib2, iclass 38, count 0 2006.201.18:23:38.90#ibcon#*after write, iclass 38, count 0 2006.201.18:23:38.90#ibcon#*before return 0, iclass 38, count 0 2006.201.18:23:38.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:38.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:38.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.18:23:38.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.18:23:38.90$vck44/valo=7,864.99 2006.201.18:23:38.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.18:23:38.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.18:23:38.90#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:38.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:38.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:38.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:38.90#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:23:38.90#ibcon#first serial, iclass 40, count 0 2006.201.18:23:38.90#ibcon#enter sib2, iclass 40, count 0 2006.201.18:23:38.90#ibcon#flushed, iclass 40, count 0 2006.201.18:23:38.90#ibcon#about to write, iclass 40, count 0 2006.201.18:23:38.90#ibcon#wrote, iclass 40, count 0 2006.201.18:23:38.90#ibcon#about to read 3, iclass 40, count 0 2006.201.18:23:38.92#ibcon#read 3, iclass 40, count 0 2006.201.18:23:38.92#ibcon#about to read 4, iclass 40, count 0 2006.201.18:23:38.92#ibcon#read 4, iclass 40, count 0 2006.201.18:23:38.92#ibcon#about to read 5, iclass 40, count 0 2006.201.18:23:38.92#ibcon#read 5, iclass 40, count 0 2006.201.18:23:38.92#ibcon#about to read 6, iclass 40, count 0 2006.201.18:23:38.92#ibcon#read 6, iclass 40, count 0 2006.201.18:23:38.92#ibcon#end of sib2, iclass 40, count 0 2006.201.18:23:38.92#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:23:38.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:23:38.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:23:38.92#ibcon#*before write, iclass 40, count 0 2006.201.18:23:38.92#ibcon#enter sib2, iclass 40, count 0 2006.201.18:23:38.92#ibcon#flushed, iclass 40, count 0 2006.201.18:23:38.92#ibcon#about to write, iclass 40, count 0 2006.201.18:23:38.92#ibcon#wrote, iclass 40, count 0 2006.201.18:23:38.92#ibcon#about to read 3, iclass 40, count 0 2006.201.18:23:38.96#ibcon#read 3, iclass 40, count 0 2006.201.18:23:38.96#ibcon#about to read 4, iclass 40, count 0 2006.201.18:23:38.96#ibcon#read 4, iclass 40, count 0 2006.201.18:23:38.96#ibcon#about to read 5, iclass 40, count 0 2006.201.18:23:38.96#ibcon#read 5, iclass 40, count 0 2006.201.18:23:38.96#ibcon#about to read 6, iclass 40, count 0 2006.201.18:23:38.96#ibcon#read 6, iclass 40, count 0 2006.201.18:23:38.96#ibcon#end of sib2, iclass 40, count 0 2006.201.18:23:38.96#ibcon#*after write, iclass 40, count 0 2006.201.18:23:38.96#ibcon#*before return 0, iclass 40, count 0 2006.201.18:23:38.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:38.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:38.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:23:38.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:23:38.96$vck44/va=7,5 2006.201.18:23:38.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.18:23:38.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.18:23:38.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:38.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:39.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:39.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:39.02#ibcon#enter wrdev, iclass 4, count 2 2006.201.18:23:39.02#ibcon#first serial, iclass 4, count 2 2006.201.18:23:39.02#ibcon#enter sib2, iclass 4, count 2 2006.201.18:23:39.02#ibcon#flushed, iclass 4, count 2 2006.201.18:23:39.02#ibcon#about to write, iclass 4, count 2 2006.201.18:23:39.02#ibcon#wrote, iclass 4, count 2 2006.201.18:23:39.02#ibcon#about to read 3, iclass 4, count 2 2006.201.18:23:39.04#ibcon#read 3, iclass 4, count 2 2006.201.18:23:39.04#ibcon#about to read 4, iclass 4, count 2 2006.201.18:23:39.04#ibcon#read 4, iclass 4, count 2 2006.201.18:23:39.04#ibcon#about to read 5, iclass 4, count 2 2006.201.18:23:39.04#ibcon#read 5, iclass 4, count 2 2006.201.18:23:39.04#ibcon#about to read 6, iclass 4, count 2 2006.201.18:23:39.04#ibcon#read 6, iclass 4, count 2 2006.201.18:23:39.04#ibcon#end of sib2, iclass 4, count 2 2006.201.18:23:39.04#ibcon#*mode == 0, iclass 4, count 2 2006.201.18:23:39.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.18:23:39.04#ibcon#[25=AT07-05\r\n] 2006.201.18:23:39.04#ibcon#*before write, iclass 4, count 2 2006.201.18:23:39.04#ibcon#enter sib2, iclass 4, count 2 2006.201.18:23:39.04#ibcon#flushed, iclass 4, count 2 2006.201.18:23:39.04#ibcon#about to write, iclass 4, count 2 2006.201.18:23:39.04#ibcon#wrote, iclass 4, count 2 2006.201.18:23:39.04#ibcon#about to read 3, iclass 4, count 2 2006.201.18:23:39.07#ibcon#read 3, iclass 4, count 2 2006.201.18:23:39.07#ibcon#about to read 4, iclass 4, count 2 2006.201.18:23:39.07#ibcon#read 4, iclass 4, count 2 2006.201.18:23:39.07#ibcon#about to read 5, iclass 4, count 2 2006.201.18:23:39.07#ibcon#read 5, iclass 4, count 2 2006.201.18:23:39.07#ibcon#about to read 6, iclass 4, count 2 2006.201.18:23:39.07#ibcon#read 6, iclass 4, count 2 2006.201.18:23:39.07#ibcon#end of sib2, iclass 4, count 2 2006.201.18:23:39.07#ibcon#*after write, iclass 4, count 2 2006.201.18:23:39.07#ibcon#*before return 0, iclass 4, count 2 2006.201.18:23:39.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:39.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:39.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.18:23:39.07#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:39.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:39.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:39.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:39.19#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:23:39.19#ibcon#first serial, iclass 4, count 0 2006.201.18:23:39.19#ibcon#enter sib2, iclass 4, count 0 2006.201.18:23:39.19#ibcon#flushed, iclass 4, count 0 2006.201.18:23:39.19#ibcon#about to write, iclass 4, count 0 2006.201.18:23:39.19#ibcon#wrote, iclass 4, count 0 2006.201.18:23:39.19#ibcon#about to read 3, iclass 4, count 0 2006.201.18:23:39.21#ibcon#read 3, iclass 4, count 0 2006.201.18:23:39.21#ibcon#about to read 4, iclass 4, count 0 2006.201.18:23:39.21#ibcon#read 4, iclass 4, count 0 2006.201.18:23:39.21#ibcon#about to read 5, iclass 4, count 0 2006.201.18:23:39.21#ibcon#read 5, iclass 4, count 0 2006.201.18:23:39.21#ibcon#about to read 6, iclass 4, count 0 2006.201.18:23:39.21#ibcon#read 6, iclass 4, count 0 2006.201.18:23:39.21#ibcon#end of sib2, iclass 4, count 0 2006.201.18:23:39.21#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:23:39.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:23:39.21#ibcon#[25=USB\r\n] 2006.201.18:23:39.21#ibcon#*before write, iclass 4, count 0 2006.201.18:23:39.21#ibcon#enter sib2, iclass 4, count 0 2006.201.18:23:39.21#ibcon#flushed, iclass 4, count 0 2006.201.18:23:39.21#ibcon#about to write, iclass 4, count 0 2006.201.18:23:39.21#ibcon#wrote, iclass 4, count 0 2006.201.18:23:39.21#ibcon#about to read 3, iclass 4, count 0 2006.201.18:23:39.24#ibcon#read 3, iclass 4, count 0 2006.201.18:23:39.24#ibcon#about to read 4, iclass 4, count 0 2006.201.18:23:39.24#ibcon#read 4, iclass 4, count 0 2006.201.18:23:39.24#ibcon#about to read 5, iclass 4, count 0 2006.201.18:23:39.24#ibcon#read 5, iclass 4, count 0 2006.201.18:23:39.24#ibcon#about to read 6, iclass 4, count 0 2006.201.18:23:39.24#ibcon#read 6, iclass 4, count 0 2006.201.18:23:39.24#ibcon#end of sib2, iclass 4, count 0 2006.201.18:23:39.24#ibcon#*after write, iclass 4, count 0 2006.201.18:23:39.24#ibcon#*before return 0, iclass 4, count 0 2006.201.18:23:39.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:39.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:39.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:23:39.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:23:39.24$vck44/valo=8,884.99 2006.201.18:23:39.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.18:23:39.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.18:23:39.24#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:39.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:39.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:39.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:39.24#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:23:39.24#ibcon#first serial, iclass 6, count 0 2006.201.18:23:39.24#ibcon#enter sib2, iclass 6, count 0 2006.201.18:23:39.24#ibcon#flushed, iclass 6, count 0 2006.201.18:23:39.24#ibcon#about to write, iclass 6, count 0 2006.201.18:23:39.24#ibcon#wrote, iclass 6, count 0 2006.201.18:23:39.24#ibcon#about to read 3, iclass 6, count 0 2006.201.18:23:39.26#ibcon#read 3, iclass 6, count 0 2006.201.18:23:39.26#ibcon#about to read 4, iclass 6, count 0 2006.201.18:23:39.26#ibcon#read 4, iclass 6, count 0 2006.201.18:23:39.26#ibcon#about to read 5, iclass 6, count 0 2006.201.18:23:39.26#ibcon#read 5, iclass 6, count 0 2006.201.18:23:39.26#ibcon#about to read 6, iclass 6, count 0 2006.201.18:23:39.26#ibcon#read 6, iclass 6, count 0 2006.201.18:23:39.26#ibcon#end of sib2, iclass 6, count 0 2006.201.18:23:39.26#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:23:39.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:23:39.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:23:39.26#ibcon#*before write, iclass 6, count 0 2006.201.18:23:39.26#ibcon#enter sib2, iclass 6, count 0 2006.201.18:23:39.26#ibcon#flushed, iclass 6, count 0 2006.201.18:23:39.26#ibcon#about to write, iclass 6, count 0 2006.201.18:23:39.26#ibcon#wrote, iclass 6, count 0 2006.201.18:23:39.26#ibcon#about to read 3, iclass 6, count 0 2006.201.18:23:39.30#ibcon#read 3, iclass 6, count 0 2006.201.18:23:39.30#ibcon#about to read 4, iclass 6, count 0 2006.201.18:23:39.30#ibcon#read 4, iclass 6, count 0 2006.201.18:23:39.30#ibcon#about to read 5, iclass 6, count 0 2006.201.18:23:39.30#ibcon#read 5, iclass 6, count 0 2006.201.18:23:39.30#ibcon#about to read 6, iclass 6, count 0 2006.201.18:23:39.30#ibcon#read 6, iclass 6, count 0 2006.201.18:23:39.30#ibcon#end of sib2, iclass 6, count 0 2006.201.18:23:39.30#ibcon#*after write, iclass 6, count 0 2006.201.18:23:39.30#ibcon#*before return 0, iclass 6, count 0 2006.201.18:23:39.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:39.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:39.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:23:39.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:23:39.30$vck44/va=8,4 2006.201.18:23:39.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.18:23:39.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.18:23:39.30#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:39.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:23:39.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:23:39.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:23:39.36#ibcon#enter wrdev, iclass 10, count 2 2006.201.18:23:39.36#ibcon#first serial, iclass 10, count 2 2006.201.18:23:39.36#ibcon#enter sib2, iclass 10, count 2 2006.201.18:23:39.36#ibcon#flushed, iclass 10, count 2 2006.201.18:23:39.36#ibcon#about to write, iclass 10, count 2 2006.201.18:23:39.36#ibcon#wrote, iclass 10, count 2 2006.201.18:23:39.36#ibcon#about to read 3, iclass 10, count 2 2006.201.18:23:39.38#ibcon#read 3, iclass 10, count 2 2006.201.18:23:39.38#ibcon#about to read 4, iclass 10, count 2 2006.201.18:23:39.38#ibcon#read 4, iclass 10, count 2 2006.201.18:23:39.38#ibcon#about to read 5, iclass 10, count 2 2006.201.18:23:39.38#ibcon#read 5, iclass 10, count 2 2006.201.18:23:39.38#ibcon#about to read 6, iclass 10, count 2 2006.201.18:23:39.38#ibcon#read 6, iclass 10, count 2 2006.201.18:23:39.38#ibcon#end of sib2, iclass 10, count 2 2006.201.18:23:39.38#ibcon#*mode == 0, iclass 10, count 2 2006.201.18:23:39.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.18:23:39.38#ibcon#[25=AT08-04\r\n] 2006.201.18:23:39.38#ibcon#*before write, iclass 10, count 2 2006.201.18:23:39.38#ibcon#enter sib2, iclass 10, count 2 2006.201.18:23:39.38#ibcon#flushed, iclass 10, count 2 2006.201.18:23:39.38#ibcon#about to write, iclass 10, count 2 2006.201.18:23:39.38#ibcon#wrote, iclass 10, count 2 2006.201.18:23:39.38#ibcon#about to read 3, iclass 10, count 2 2006.201.18:23:39.42#ibcon#read 3, iclass 10, count 2 2006.201.18:23:39.42#ibcon#about to read 4, iclass 10, count 2 2006.201.18:23:39.42#ibcon#read 4, iclass 10, count 2 2006.201.18:23:39.42#ibcon#about to read 5, iclass 10, count 2 2006.201.18:23:39.42#ibcon#read 5, iclass 10, count 2 2006.201.18:23:39.42#ibcon#about to read 6, iclass 10, count 2 2006.201.18:23:39.42#ibcon#read 6, iclass 10, count 2 2006.201.18:23:39.42#ibcon#end of sib2, iclass 10, count 2 2006.201.18:23:39.42#ibcon#*after write, iclass 10, count 2 2006.201.18:23:39.42#ibcon#*before return 0, iclass 10, count 2 2006.201.18:23:39.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:23:39.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:23:39.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.18:23:39.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:39.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:23:39.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:23:39.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:23:39.54#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:23:39.54#ibcon#first serial, iclass 10, count 0 2006.201.18:23:39.54#ibcon#enter sib2, iclass 10, count 0 2006.201.18:23:39.54#ibcon#flushed, iclass 10, count 0 2006.201.18:23:39.54#ibcon#about to write, iclass 10, count 0 2006.201.18:23:39.54#ibcon#wrote, iclass 10, count 0 2006.201.18:23:39.54#ibcon#about to read 3, iclass 10, count 0 2006.201.18:23:39.56#ibcon#read 3, iclass 10, count 0 2006.201.18:23:39.56#ibcon#about to read 4, iclass 10, count 0 2006.201.18:23:39.56#ibcon#read 4, iclass 10, count 0 2006.201.18:23:39.56#ibcon#about to read 5, iclass 10, count 0 2006.201.18:23:39.56#ibcon#read 5, iclass 10, count 0 2006.201.18:23:39.56#ibcon#about to read 6, iclass 10, count 0 2006.201.18:23:39.56#ibcon#read 6, iclass 10, count 0 2006.201.18:23:39.56#ibcon#end of sib2, iclass 10, count 0 2006.201.18:23:39.56#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:23:39.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:23:39.56#ibcon#[25=USB\r\n] 2006.201.18:23:39.56#ibcon#*before write, iclass 10, count 0 2006.201.18:23:39.56#ibcon#enter sib2, iclass 10, count 0 2006.201.18:23:39.56#ibcon#flushed, iclass 10, count 0 2006.201.18:23:39.56#ibcon#about to write, iclass 10, count 0 2006.201.18:23:39.56#ibcon#wrote, iclass 10, count 0 2006.201.18:23:39.56#ibcon#about to read 3, iclass 10, count 0 2006.201.18:23:39.59#ibcon#read 3, iclass 10, count 0 2006.201.18:23:39.59#ibcon#about to read 4, iclass 10, count 0 2006.201.18:23:39.59#ibcon#read 4, iclass 10, count 0 2006.201.18:23:39.59#ibcon#about to read 5, iclass 10, count 0 2006.201.18:23:39.59#ibcon#read 5, iclass 10, count 0 2006.201.18:23:39.59#ibcon#about to read 6, iclass 10, count 0 2006.201.18:23:39.59#ibcon#read 6, iclass 10, count 0 2006.201.18:23:39.59#ibcon#end of sib2, iclass 10, count 0 2006.201.18:23:39.59#ibcon#*after write, iclass 10, count 0 2006.201.18:23:39.59#ibcon#*before return 0, iclass 10, count 0 2006.201.18:23:39.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:23:39.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:23:39.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:23:39.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:23:39.59$vck44/vblo=1,629.99 2006.201.18:23:39.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.18:23:39.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.18:23:39.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:39.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:39.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:39.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:39.59#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:23:39.59#ibcon#first serial, iclass 12, count 0 2006.201.18:23:39.59#ibcon#enter sib2, iclass 12, count 0 2006.201.18:23:39.59#ibcon#flushed, iclass 12, count 0 2006.201.18:23:39.59#ibcon#about to write, iclass 12, count 0 2006.201.18:23:39.59#ibcon#wrote, iclass 12, count 0 2006.201.18:23:39.59#ibcon#about to read 3, iclass 12, count 0 2006.201.18:23:39.61#ibcon#read 3, iclass 12, count 0 2006.201.18:23:39.61#ibcon#about to read 4, iclass 12, count 0 2006.201.18:23:39.61#ibcon#read 4, iclass 12, count 0 2006.201.18:23:39.61#ibcon#about to read 5, iclass 12, count 0 2006.201.18:23:39.61#ibcon#read 5, iclass 12, count 0 2006.201.18:23:39.61#ibcon#about to read 6, iclass 12, count 0 2006.201.18:23:39.61#ibcon#read 6, iclass 12, count 0 2006.201.18:23:39.61#ibcon#end of sib2, iclass 12, count 0 2006.201.18:23:39.61#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:23:39.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:23:39.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:23:39.61#ibcon#*before write, iclass 12, count 0 2006.201.18:23:39.61#ibcon#enter sib2, iclass 12, count 0 2006.201.18:23:39.61#ibcon#flushed, iclass 12, count 0 2006.201.18:23:39.61#ibcon#about to write, iclass 12, count 0 2006.201.18:23:39.61#ibcon#wrote, iclass 12, count 0 2006.201.18:23:39.61#ibcon#about to read 3, iclass 12, count 0 2006.201.18:23:39.66#ibcon#read 3, iclass 12, count 0 2006.201.18:23:39.66#ibcon#about to read 4, iclass 12, count 0 2006.201.18:23:39.66#ibcon#read 4, iclass 12, count 0 2006.201.18:23:39.66#ibcon#about to read 5, iclass 12, count 0 2006.201.18:23:39.66#ibcon#read 5, iclass 12, count 0 2006.201.18:23:39.66#ibcon#about to read 6, iclass 12, count 0 2006.201.18:23:39.66#ibcon#read 6, iclass 12, count 0 2006.201.18:23:39.66#ibcon#end of sib2, iclass 12, count 0 2006.201.18:23:39.66#ibcon#*after write, iclass 12, count 0 2006.201.18:23:39.66#ibcon#*before return 0, iclass 12, count 0 2006.201.18:23:39.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:39.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:23:39.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:23:39.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:23:39.66$vck44/vb=1,4 2006.201.18:23:39.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.18:23:39.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.18:23:39.66#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:39.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:39.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:39.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:39.66#ibcon#enter wrdev, iclass 14, count 2 2006.201.18:23:39.66#ibcon#first serial, iclass 14, count 2 2006.201.18:23:39.66#ibcon#enter sib2, iclass 14, count 2 2006.201.18:23:39.66#ibcon#flushed, iclass 14, count 2 2006.201.18:23:39.66#ibcon#about to write, iclass 14, count 2 2006.201.18:23:39.66#ibcon#wrote, iclass 14, count 2 2006.201.18:23:39.66#ibcon#about to read 3, iclass 14, count 2 2006.201.18:23:39.68#ibcon#read 3, iclass 14, count 2 2006.201.18:23:39.68#ibcon#about to read 4, iclass 14, count 2 2006.201.18:23:39.68#ibcon#read 4, iclass 14, count 2 2006.201.18:23:39.68#ibcon#about to read 5, iclass 14, count 2 2006.201.18:23:39.68#ibcon#read 5, iclass 14, count 2 2006.201.18:23:39.68#ibcon#about to read 6, iclass 14, count 2 2006.201.18:23:39.68#ibcon#read 6, iclass 14, count 2 2006.201.18:23:39.68#ibcon#end of sib2, iclass 14, count 2 2006.201.18:23:39.68#ibcon#*mode == 0, iclass 14, count 2 2006.201.18:23:39.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.18:23:39.68#ibcon#[27=AT01-04\r\n] 2006.201.18:23:39.68#ibcon#*before write, iclass 14, count 2 2006.201.18:23:39.68#ibcon#enter sib2, iclass 14, count 2 2006.201.18:23:39.68#ibcon#flushed, iclass 14, count 2 2006.201.18:23:39.68#ibcon#about to write, iclass 14, count 2 2006.201.18:23:39.68#ibcon#wrote, iclass 14, count 2 2006.201.18:23:39.68#ibcon#about to read 3, iclass 14, count 2 2006.201.18:23:39.71#ibcon#read 3, iclass 14, count 2 2006.201.18:23:39.71#ibcon#about to read 4, iclass 14, count 2 2006.201.18:23:39.71#ibcon#read 4, iclass 14, count 2 2006.201.18:23:39.71#ibcon#about to read 5, iclass 14, count 2 2006.201.18:23:39.71#ibcon#read 5, iclass 14, count 2 2006.201.18:23:39.71#ibcon#about to read 6, iclass 14, count 2 2006.201.18:23:39.71#ibcon#read 6, iclass 14, count 2 2006.201.18:23:39.71#ibcon#end of sib2, iclass 14, count 2 2006.201.18:23:39.71#ibcon#*after write, iclass 14, count 2 2006.201.18:23:39.71#ibcon#*before return 0, iclass 14, count 2 2006.201.18:23:39.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:39.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:23:39.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.18:23:39.71#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:39.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:39.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:39.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:39.83#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:23:39.83#ibcon#first serial, iclass 14, count 0 2006.201.18:23:39.83#ibcon#enter sib2, iclass 14, count 0 2006.201.18:23:39.83#ibcon#flushed, iclass 14, count 0 2006.201.18:23:39.83#ibcon#about to write, iclass 14, count 0 2006.201.18:23:39.83#ibcon#wrote, iclass 14, count 0 2006.201.18:23:39.83#ibcon#about to read 3, iclass 14, count 0 2006.201.18:23:39.85#ibcon#read 3, iclass 14, count 0 2006.201.18:23:39.85#ibcon#about to read 4, iclass 14, count 0 2006.201.18:23:39.85#ibcon#read 4, iclass 14, count 0 2006.201.18:23:39.85#ibcon#about to read 5, iclass 14, count 0 2006.201.18:23:39.85#ibcon#read 5, iclass 14, count 0 2006.201.18:23:39.85#ibcon#about to read 6, iclass 14, count 0 2006.201.18:23:39.85#ibcon#read 6, iclass 14, count 0 2006.201.18:23:39.85#ibcon#end of sib2, iclass 14, count 0 2006.201.18:23:39.85#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:23:39.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:23:39.85#ibcon#[27=USB\r\n] 2006.201.18:23:39.85#ibcon#*before write, iclass 14, count 0 2006.201.18:23:39.85#ibcon#enter sib2, iclass 14, count 0 2006.201.18:23:39.85#ibcon#flushed, iclass 14, count 0 2006.201.18:23:39.85#ibcon#about to write, iclass 14, count 0 2006.201.18:23:39.85#ibcon#wrote, iclass 14, count 0 2006.201.18:23:39.85#ibcon#about to read 3, iclass 14, count 0 2006.201.18:23:39.88#ibcon#read 3, iclass 14, count 0 2006.201.18:23:39.88#ibcon#about to read 4, iclass 14, count 0 2006.201.18:23:39.88#ibcon#read 4, iclass 14, count 0 2006.201.18:23:39.88#ibcon#about to read 5, iclass 14, count 0 2006.201.18:23:39.88#ibcon#read 5, iclass 14, count 0 2006.201.18:23:39.88#ibcon#about to read 6, iclass 14, count 0 2006.201.18:23:39.88#ibcon#read 6, iclass 14, count 0 2006.201.18:23:39.88#ibcon#end of sib2, iclass 14, count 0 2006.201.18:23:39.88#ibcon#*after write, iclass 14, count 0 2006.201.18:23:39.88#ibcon#*before return 0, iclass 14, count 0 2006.201.18:23:39.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:39.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:23:39.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:23:39.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:23:39.88$vck44/vblo=2,634.99 2006.201.18:23:39.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.18:23:39.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.18:23:39.88#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:39.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:39.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:39.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:39.88#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:23:39.88#ibcon#first serial, iclass 16, count 0 2006.201.18:23:39.88#ibcon#enter sib2, iclass 16, count 0 2006.201.18:23:39.88#ibcon#flushed, iclass 16, count 0 2006.201.18:23:39.88#ibcon#about to write, iclass 16, count 0 2006.201.18:23:39.88#ibcon#wrote, iclass 16, count 0 2006.201.18:23:39.88#ibcon#about to read 3, iclass 16, count 0 2006.201.18:23:39.90#ibcon#read 3, iclass 16, count 0 2006.201.18:23:39.90#ibcon#about to read 4, iclass 16, count 0 2006.201.18:23:39.90#ibcon#read 4, iclass 16, count 0 2006.201.18:23:39.90#ibcon#about to read 5, iclass 16, count 0 2006.201.18:23:39.90#ibcon#read 5, iclass 16, count 0 2006.201.18:23:39.90#ibcon#about to read 6, iclass 16, count 0 2006.201.18:23:39.90#ibcon#read 6, iclass 16, count 0 2006.201.18:23:39.90#ibcon#end of sib2, iclass 16, count 0 2006.201.18:23:39.90#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:23:39.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:23:39.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:23:39.90#ibcon#*before write, iclass 16, count 0 2006.201.18:23:39.90#ibcon#enter sib2, iclass 16, count 0 2006.201.18:23:39.90#ibcon#flushed, iclass 16, count 0 2006.201.18:23:39.90#ibcon#about to write, iclass 16, count 0 2006.201.18:23:39.90#ibcon#wrote, iclass 16, count 0 2006.201.18:23:39.90#ibcon#about to read 3, iclass 16, count 0 2006.201.18:23:39.94#ibcon#read 3, iclass 16, count 0 2006.201.18:23:39.94#ibcon#about to read 4, iclass 16, count 0 2006.201.18:23:39.94#ibcon#read 4, iclass 16, count 0 2006.201.18:23:39.94#ibcon#about to read 5, iclass 16, count 0 2006.201.18:23:39.94#ibcon#read 5, iclass 16, count 0 2006.201.18:23:39.94#ibcon#about to read 6, iclass 16, count 0 2006.201.18:23:39.94#ibcon#read 6, iclass 16, count 0 2006.201.18:23:39.94#ibcon#end of sib2, iclass 16, count 0 2006.201.18:23:39.94#ibcon#*after write, iclass 16, count 0 2006.201.18:23:39.94#ibcon#*before return 0, iclass 16, count 0 2006.201.18:23:39.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:39.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:23:39.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:23:39.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:23:39.94$vck44/vb=2,5 2006.201.18:23:39.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.18:23:39.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.18:23:39.94#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:39.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:40.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:40.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:40.00#ibcon#enter wrdev, iclass 18, count 2 2006.201.18:23:40.00#ibcon#first serial, iclass 18, count 2 2006.201.18:23:40.00#ibcon#enter sib2, iclass 18, count 2 2006.201.18:23:40.00#ibcon#flushed, iclass 18, count 2 2006.201.18:23:40.00#ibcon#about to write, iclass 18, count 2 2006.201.18:23:40.00#ibcon#wrote, iclass 18, count 2 2006.201.18:23:40.00#ibcon#about to read 3, iclass 18, count 2 2006.201.18:23:40.02#ibcon#read 3, iclass 18, count 2 2006.201.18:23:40.02#ibcon#about to read 4, iclass 18, count 2 2006.201.18:23:40.02#ibcon#read 4, iclass 18, count 2 2006.201.18:23:40.02#ibcon#about to read 5, iclass 18, count 2 2006.201.18:23:40.02#ibcon#read 5, iclass 18, count 2 2006.201.18:23:40.02#ibcon#about to read 6, iclass 18, count 2 2006.201.18:23:40.02#ibcon#read 6, iclass 18, count 2 2006.201.18:23:40.02#ibcon#end of sib2, iclass 18, count 2 2006.201.18:23:40.02#ibcon#*mode == 0, iclass 18, count 2 2006.201.18:23:40.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.18:23:40.02#ibcon#[27=AT02-05\r\n] 2006.201.18:23:40.02#ibcon#*before write, iclass 18, count 2 2006.201.18:23:40.02#ibcon#enter sib2, iclass 18, count 2 2006.201.18:23:40.02#ibcon#flushed, iclass 18, count 2 2006.201.18:23:40.02#ibcon#about to write, iclass 18, count 2 2006.201.18:23:40.02#ibcon#wrote, iclass 18, count 2 2006.201.18:23:40.02#ibcon#about to read 3, iclass 18, count 2 2006.201.18:23:40.05#ibcon#read 3, iclass 18, count 2 2006.201.18:23:40.05#ibcon#about to read 4, iclass 18, count 2 2006.201.18:23:40.05#ibcon#read 4, iclass 18, count 2 2006.201.18:23:40.05#ibcon#about to read 5, iclass 18, count 2 2006.201.18:23:40.05#ibcon#read 5, iclass 18, count 2 2006.201.18:23:40.05#ibcon#about to read 6, iclass 18, count 2 2006.201.18:23:40.05#ibcon#read 6, iclass 18, count 2 2006.201.18:23:40.05#ibcon#end of sib2, iclass 18, count 2 2006.201.18:23:40.05#ibcon#*after write, iclass 18, count 2 2006.201.18:23:40.05#ibcon#*before return 0, iclass 18, count 2 2006.201.18:23:40.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:40.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:23:40.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.18:23:40.05#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:40.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:40.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:40.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:40.17#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:23:40.17#ibcon#first serial, iclass 18, count 0 2006.201.18:23:40.17#ibcon#enter sib2, iclass 18, count 0 2006.201.18:23:40.17#ibcon#flushed, iclass 18, count 0 2006.201.18:23:40.17#ibcon#about to write, iclass 18, count 0 2006.201.18:23:40.17#ibcon#wrote, iclass 18, count 0 2006.201.18:23:40.17#ibcon#about to read 3, iclass 18, count 0 2006.201.18:23:40.19#ibcon#read 3, iclass 18, count 0 2006.201.18:23:40.19#ibcon#about to read 4, iclass 18, count 0 2006.201.18:23:40.19#ibcon#read 4, iclass 18, count 0 2006.201.18:23:40.19#ibcon#about to read 5, iclass 18, count 0 2006.201.18:23:40.19#ibcon#read 5, iclass 18, count 0 2006.201.18:23:40.19#ibcon#about to read 6, iclass 18, count 0 2006.201.18:23:40.19#ibcon#read 6, iclass 18, count 0 2006.201.18:23:40.19#ibcon#end of sib2, iclass 18, count 0 2006.201.18:23:40.19#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:23:40.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:23:40.19#ibcon#[27=USB\r\n] 2006.201.18:23:40.19#ibcon#*before write, iclass 18, count 0 2006.201.18:23:40.19#ibcon#enter sib2, iclass 18, count 0 2006.201.18:23:40.19#ibcon#flushed, iclass 18, count 0 2006.201.18:23:40.19#ibcon#about to write, iclass 18, count 0 2006.201.18:23:40.19#ibcon#wrote, iclass 18, count 0 2006.201.18:23:40.19#ibcon#about to read 3, iclass 18, count 0 2006.201.18:23:40.22#ibcon#read 3, iclass 18, count 0 2006.201.18:23:40.22#ibcon#about to read 4, iclass 18, count 0 2006.201.18:23:40.22#ibcon#read 4, iclass 18, count 0 2006.201.18:23:40.22#ibcon#about to read 5, iclass 18, count 0 2006.201.18:23:40.22#ibcon#read 5, iclass 18, count 0 2006.201.18:23:40.22#ibcon#about to read 6, iclass 18, count 0 2006.201.18:23:40.22#ibcon#read 6, iclass 18, count 0 2006.201.18:23:40.22#ibcon#end of sib2, iclass 18, count 0 2006.201.18:23:40.22#ibcon#*after write, iclass 18, count 0 2006.201.18:23:40.22#ibcon#*before return 0, iclass 18, count 0 2006.201.18:23:40.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:40.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:23:40.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:23:40.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:23:40.22$vck44/vblo=3,649.99 2006.201.18:23:40.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.18:23:40.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.18:23:40.22#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:40.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:23:40.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:23:40.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:23:40.22#ibcon#enter wrdev, iclass 20, count 0 2006.201.18:23:40.22#ibcon#first serial, iclass 20, count 0 2006.201.18:23:40.22#ibcon#enter sib2, iclass 20, count 0 2006.201.18:23:40.22#ibcon#flushed, iclass 20, count 0 2006.201.18:23:40.22#ibcon#about to write, iclass 20, count 0 2006.201.18:23:40.22#ibcon#wrote, iclass 20, count 0 2006.201.18:23:40.22#ibcon#about to read 3, iclass 20, count 0 2006.201.18:23:40.24#ibcon#read 3, iclass 20, count 0 2006.201.18:23:40.24#ibcon#about to read 4, iclass 20, count 0 2006.201.18:23:40.24#ibcon#read 4, iclass 20, count 0 2006.201.18:23:40.24#ibcon#about to read 5, iclass 20, count 0 2006.201.18:23:40.24#ibcon#read 5, iclass 20, count 0 2006.201.18:23:40.24#ibcon#about to read 6, iclass 20, count 0 2006.201.18:23:40.24#ibcon#read 6, iclass 20, count 0 2006.201.18:23:40.24#ibcon#end of sib2, iclass 20, count 0 2006.201.18:23:40.24#ibcon#*mode == 0, iclass 20, count 0 2006.201.18:23:40.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.18:23:40.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:23:40.24#ibcon#*before write, iclass 20, count 0 2006.201.18:23:40.24#ibcon#enter sib2, iclass 20, count 0 2006.201.18:23:40.24#ibcon#flushed, iclass 20, count 0 2006.201.18:23:40.24#ibcon#about to write, iclass 20, count 0 2006.201.18:23:40.24#ibcon#wrote, iclass 20, count 0 2006.201.18:23:40.24#ibcon#about to read 3, iclass 20, count 0 2006.201.18:23:40.28#ibcon#read 3, iclass 20, count 0 2006.201.18:23:40.28#ibcon#about to read 4, iclass 20, count 0 2006.201.18:23:40.28#ibcon#read 4, iclass 20, count 0 2006.201.18:23:40.28#ibcon#about to read 5, iclass 20, count 0 2006.201.18:23:40.28#ibcon#read 5, iclass 20, count 0 2006.201.18:23:40.28#ibcon#about to read 6, iclass 20, count 0 2006.201.18:23:40.28#ibcon#read 6, iclass 20, count 0 2006.201.18:23:40.28#ibcon#end of sib2, iclass 20, count 0 2006.201.18:23:40.28#ibcon#*after write, iclass 20, count 0 2006.201.18:23:40.28#ibcon#*before return 0, iclass 20, count 0 2006.201.18:23:40.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:23:40.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:23:40.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.18:23:40.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.18:23:40.28$vck44/vb=3,4 2006.201.18:23:40.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.18:23:40.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.18:23:40.28#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:40.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:23:40.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:23:40.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:23:40.34#ibcon#enter wrdev, iclass 22, count 2 2006.201.18:23:40.34#ibcon#first serial, iclass 22, count 2 2006.201.18:23:40.34#ibcon#enter sib2, iclass 22, count 2 2006.201.18:23:40.34#ibcon#flushed, iclass 22, count 2 2006.201.18:23:40.34#ibcon#about to write, iclass 22, count 2 2006.201.18:23:40.34#ibcon#wrote, iclass 22, count 2 2006.201.18:23:40.34#ibcon#about to read 3, iclass 22, count 2 2006.201.18:23:40.36#ibcon#read 3, iclass 22, count 2 2006.201.18:23:40.36#ibcon#about to read 4, iclass 22, count 2 2006.201.18:23:40.36#ibcon#read 4, iclass 22, count 2 2006.201.18:23:40.36#ibcon#about to read 5, iclass 22, count 2 2006.201.18:23:40.36#ibcon#read 5, iclass 22, count 2 2006.201.18:23:40.36#ibcon#about to read 6, iclass 22, count 2 2006.201.18:23:40.36#ibcon#read 6, iclass 22, count 2 2006.201.18:23:40.36#ibcon#end of sib2, iclass 22, count 2 2006.201.18:23:40.36#ibcon#*mode == 0, iclass 22, count 2 2006.201.18:23:40.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.18:23:40.36#ibcon#[27=AT03-04\r\n] 2006.201.18:23:40.36#ibcon#*before write, iclass 22, count 2 2006.201.18:23:40.36#ibcon#enter sib2, iclass 22, count 2 2006.201.18:23:40.36#ibcon#flushed, iclass 22, count 2 2006.201.18:23:40.36#ibcon#about to write, iclass 22, count 2 2006.201.18:23:40.36#ibcon#wrote, iclass 22, count 2 2006.201.18:23:40.36#ibcon#about to read 3, iclass 22, count 2 2006.201.18:23:40.39#ibcon#read 3, iclass 22, count 2 2006.201.18:23:40.39#ibcon#about to read 4, iclass 22, count 2 2006.201.18:23:40.39#ibcon#read 4, iclass 22, count 2 2006.201.18:23:40.39#ibcon#about to read 5, iclass 22, count 2 2006.201.18:23:40.39#ibcon#read 5, iclass 22, count 2 2006.201.18:23:40.39#ibcon#about to read 6, iclass 22, count 2 2006.201.18:23:40.39#ibcon#read 6, iclass 22, count 2 2006.201.18:23:40.39#ibcon#end of sib2, iclass 22, count 2 2006.201.18:23:40.39#ibcon#*after write, iclass 22, count 2 2006.201.18:23:40.39#ibcon#*before return 0, iclass 22, count 2 2006.201.18:23:40.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:23:40.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:23:40.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.18:23:40.39#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:40.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:23:40.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:23:40.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:23:40.51#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:23:40.51#ibcon#first serial, iclass 22, count 0 2006.201.18:23:40.51#ibcon#enter sib2, iclass 22, count 0 2006.201.18:23:40.51#ibcon#flushed, iclass 22, count 0 2006.201.18:23:40.51#ibcon#about to write, iclass 22, count 0 2006.201.18:23:40.51#ibcon#wrote, iclass 22, count 0 2006.201.18:23:40.51#ibcon#about to read 3, iclass 22, count 0 2006.201.18:23:40.53#ibcon#read 3, iclass 22, count 0 2006.201.18:23:40.53#ibcon#about to read 4, iclass 22, count 0 2006.201.18:23:40.53#ibcon#read 4, iclass 22, count 0 2006.201.18:23:40.53#ibcon#about to read 5, iclass 22, count 0 2006.201.18:23:40.53#ibcon#read 5, iclass 22, count 0 2006.201.18:23:40.53#ibcon#about to read 6, iclass 22, count 0 2006.201.18:23:40.53#ibcon#read 6, iclass 22, count 0 2006.201.18:23:40.53#ibcon#end of sib2, iclass 22, count 0 2006.201.18:23:40.53#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:23:40.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:23:40.53#ibcon#[27=USB\r\n] 2006.201.18:23:40.53#ibcon#*before write, iclass 22, count 0 2006.201.18:23:40.53#ibcon#enter sib2, iclass 22, count 0 2006.201.18:23:40.53#ibcon#flushed, iclass 22, count 0 2006.201.18:23:40.53#ibcon#about to write, iclass 22, count 0 2006.201.18:23:40.53#ibcon#wrote, iclass 22, count 0 2006.201.18:23:40.53#ibcon#about to read 3, iclass 22, count 0 2006.201.18:23:40.56#ibcon#read 3, iclass 22, count 0 2006.201.18:23:40.56#ibcon#about to read 4, iclass 22, count 0 2006.201.18:23:40.56#ibcon#read 4, iclass 22, count 0 2006.201.18:23:40.56#ibcon#about to read 5, iclass 22, count 0 2006.201.18:23:40.56#ibcon#read 5, iclass 22, count 0 2006.201.18:23:40.56#ibcon#about to read 6, iclass 22, count 0 2006.201.18:23:40.56#ibcon#read 6, iclass 22, count 0 2006.201.18:23:40.56#ibcon#end of sib2, iclass 22, count 0 2006.201.18:23:40.56#ibcon#*after write, iclass 22, count 0 2006.201.18:23:40.56#ibcon#*before return 0, iclass 22, count 0 2006.201.18:23:40.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:23:40.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:23:40.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:23:40.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:23:40.56$vck44/vblo=4,679.99 2006.201.18:23:40.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.18:23:40.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.18:23:40.56#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:40.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:40.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:40.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:40.56#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:23:40.56#ibcon#first serial, iclass 24, count 0 2006.201.18:23:40.56#ibcon#enter sib2, iclass 24, count 0 2006.201.18:23:40.56#ibcon#flushed, iclass 24, count 0 2006.201.18:23:40.56#ibcon#about to write, iclass 24, count 0 2006.201.18:23:40.56#ibcon#wrote, iclass 24, count 0 2006.201.18:23:40.56#ibcon#about to read 3, iclass 24, count 0 2006.201.18:23:40.58#ibcon#read 3, iclass 24, count 0 2006.201.18:23:40.58#ibcon#about to read 4, iclass 24, count 0 2006.201.18:23:40.58#ibcon#read 4, iclass 24, count 0 2006.201.18:23:40.58#ibcon#about to read 5, iclass 24, count 0 2006.201.18:23:40.58#ibcon#read 5, iclass 24, count 0 2006.201.18:23:40.58#ibcon#about to read 6, iclass 24, count 0 2006.201.18:23:40.58#ibcon#read 6, iclass 24, count 0 2006.201.18:23:40.58#ibcon#end of sib2, iclass 24, count 0 2006.201.18:23:40.58#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:23:40.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:23:40.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:23:40.58#ibcon#*before write, iclass 24, count 0 2006.201.18:23:40.58#ibcon#enter sib2, iclass 24, count 0 2006.201.18:23:40.58#ibcon#flushed, iclass 24, count 0 2006.201.18:23:40.58#ibcon#about to write, iclass 24, count 0 2006.201.18:23:40.58#ibcon#wrote, iclass 24, count 0 2006.201.18:23:40.58#ibcon#about to read 3, iclass 24, count 0 2006.201.18:23:40.62#ibcon#read 3, iclass 24, count 0 2006.201.18:23:40.62#ibcon#about to read 4, iclass 24, count 0 2006.201.18:23:40.62#ibcon#read 4, iclass 24, count 0 2006.201.18:23:40.62#ibcon#about to read 5, iclass 24, count 0 2006.201.18:23:40.62#ibcon#read 5, iclass 24, count 0 2006.201.18:23:40.62#ibcon#about to read 6, iclass 24, count 0 2006.201.18:23:40.62#ibcon#read 6, iclass 24, count 0 2006.201.18:23:40.62#ibcon#end of sib2, iclass 24, count 0 2006.201.18:23:40.62#ibcon#*after write, iclass 24, count 0 2006.201.18:23:40.62#ibcon#*before return 0, iclass 24, count 0 2006.201.18:23:40.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:40.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:23:40.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:23:40.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:23:40.62$vck44/vb=4,5 2006.201.18:23:40.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.18:23:40.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.18:23:40.62#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:40.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:40.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:40.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:40.68#ibcon#enter wrdev, iclass 26, count 2 2006.201.18:23:40.68#ibcon#first serial, iclass 26, count 2 2006.201.18:23:40.68#ibcon#enter sib2, iclass 26, count 2 2006.201.18:23:40.68#ibcon#flushed, iclass 26, count 2 2006.201.18:23:40.68#ibcon#about to write, iclass 26, count 2 2006.201.18:23:40.68#ibcon#wrote, iclass 26, count 2 2006.201.18:23:40.68#ibcon#about to read 3, iclass 26, count 2 2006.201.18:23:40.70#ibcon#read 3, iclass 26, count 2 2006.201.18:23:40.70#ibcon#about to read 4, iclass 26, count 2 2006.201.18:23:40.70#ibcon#read 4, iclass 26, count 2 2006.201.18:23:40.70#ibcon#about to read 5, iclass 26, count 2 2006.201.18:23:40.70#ibcon#read 5, iclass 26, count 2 2006.201.18:23:40.70#ibcon#about to read 6, iclass 26, count 2 2006.201.18:23:40.70#ibcon#read 6, iclass 26, count 2 2006.201.18:23:40.70#ibcon#end of sib2, iclass 26, count 2 2006.201.18:23:40.70#ibcon#*mode == 0, iclass 26, count 2 2006.201.18:23:40.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.18:23:40.70#ibcon#[27=AT04-05\r\n] 2006.201.18:23:40.70#ibcon#*before write, iclass 26, count 2 2006.201.18:23:40.70#ibcon#enter sib2, iclass 26, count 2 2006.201.18:23:40.70#ibcon#flushed, iclass 26, count 2 2006.201.18:23:40.70#ibcon#about to write, iclass 26, count 2 2006.201.18:23:40.70#ibcon#wrote, iclass 26, count 2 2006.201.18:23:40.70#ibcon#about to read 3, iclass 26, count 2 2006.201.18:23:40.73#ibcon#read 3, iclass 26, count 2 2006.201.18:23:40.73#ibcon#about to read 4, iclass 26, count 2 2006.201.18:23:40.73#ibcon#read 4, iclass 26, count 2 2006.201.18:23:40.73#ibcon#about to read 5, iclass 26, count 2 2006.201.18:23:40.73#ibcon#read 5, iclass 26, count 2 2006.201.18:23:40.73#ibcon#about to read 6, iclass 26, count 2 2006.201.18:23:40.73#ibcon#read 6, iclass 26, count 2 2006.201.18:23:40.73#ibcon#end of sib2, iclass 26, count 2 2006.201.18:23:40.73#ibcon#*after write, iclass 26, count 2 2006.201.18:23:40.73#ibcon#*before return 0, iclass 26, count 2 2006.201.18:23:40.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:40.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:23:40.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.18:23:40.73#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:40.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:40.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:40.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:40.85#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:23:40.85#ibcon#first serial, iclass 26, count 0 2006.201.18:23:40.85#ibcon#enter sib2, iclass 26, count 0 2006.201.18:23:40.85#ibcon#flushed, iclass 26, count 0 2006.201.18:23:40.85#ibcon#about to write, iclass 26, count 0 2006.201.18:23:40.85#ibcon#wrote, iclass 26, count 0 2006.201.18:23:40.85#ibcon#about to read 3, iclass 26, count 0 2006.201.18:23:40.87#ibcon#read 3, iclass 26, count 0 2006.201.18:23:40.87#ibcon#about to read 4, iclass 26, count 0 2006.201.18:23:40.87#ibcon#read 4, iclass 26, count 0 2006.201.18:23:40.87#ibcon#about to read 5, iclass 26, count 0 2006.201.18:23:40.87#ibcon#read 5, iclass 26, count 0 2006.201.18:23:40.87#ibcon#about to read 6, iclass 26, count 0 2006.201.18:23:40.87#ibcon#read 6, iclass 26, count 0 2006.201.18:23:40.87#ibcon#end of sib2, iclass 26, count 0 2006.201.18:23:40.87#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:23:40.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:23:40.87#ibcon#[27=USB\r\n] 2006.201.18:23:40.87#ibcon#*before write, iclass 26, count 0 2006.201.18:23:40.87#ibcon#enter sib2, iclass 26, count 0 2006.201.18:23:40.87#ibcon#flushed, iclass 26, count 0 2006.201.18:23:40.87#ibcon#about to write, iclass 26, count 0 2006.201.18:23:40.87#ibcon#wrote, iclass 26, count 0 2006.201.18:23:40.87#ibcon#about to read 3, iclass 26, count 0 2006.201.18:23:40.90#ibcon#read 3, iclass 26, count 0 2006.201.18:23:40.90#ibcon#about to read 4, iclass 26, count 0 2006.201.18:23:40.90#ibcon#read 4, iclass 26, count 0 2006.201.18:23:40.90#ibcon#about to read 5, iclass 26, count 0 2006.201.18:23:40.90#ibcon#read 5, iclass 26, count 0 2006.201.18:23:40.90#ibcon#about to read 6, iclass 26, count 0 2006.201.18:23:40.90#ibcon#read 6, iclass 26, count 0 2006.201.18:23:40.90#ibcon#end of sib2, iclass 26, count 0 2006.201.18:23:40.90#ibcon#*after write, iclass 26, count 0 2006.201.18:23:40.90#ibcon#*before return 0, iclass 26, count 0 2006.201.18:23:40.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:40.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:23:40.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:23:40.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:23:40.90$vck44/vblo=5,709.99 2006.201.18:23:40.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.18:23:40.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.18:23:40.90#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:40.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:40.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:40.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:40.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:23:40.90#ibcon#first serial, iclass 28, count 0 2006.201.18:23:40.90#ibcon#enter sib2, iclass 28, count 0 2006.201.18:23:40.90#ibcon#flushed, iclass 28, count 0 2006.201.18:23:40.90#ibcon#about to write, iclass 28, count 0 2006.201.18:23:40.90#ibcon#wrote, iclass 28, count 0 2006.201.18:23:40.90#ibcon#about to read 3, iclass 28, count 0 2006.201.18:23:40.92#ibcon#read 3, iclass 28, count 0 2006.201.18:23:40.92#ibcon#about to read 4, iclass 28, count 0 2006.201.18:23:40.92#ibcon#read 4, iclass 28, count 0 2006.201.18:23:40.92#ibcon#about to read 5, iclass 28, count 0 2006.201.18:23:40.92#ibcon#read 5, iclass 28, count 0 2006.201.18:23:40.92#ibcon#about to read 6, iclass 28, count 0 2006.201.18:23:40.92#ibcon#read 6, iclass 28, count 0 2006.201.18:23:40.92#ibcon#end of sib2, iclass 28, count 0 2006.201.18:23:40.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:23:40.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:23:40.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:23:40.92#ibcon#*before write, iclass 28, count 0 2006.201.18:23:40.92#ibcon#enter sib2, iclass 28, count 0 2006.201.18:23:40.92#ibcon#flushed, iclass 28, count 0 2006.201.18:23:40.92#ibcon#about to write, iclass 28, count 0 2006.201.18:23:40.92#ibcon#wrote, iclass 28, count 0 2006.201.18:23:40.92#ibcon#about to read 3, iclass 28, count 0 2006.201.18:23:40.96#ibcon#read 3, iclass 28, count 0 2006.201.18:23:40.96#ibcon#about to read 4, iclass 28, count 0 2006.201.18:23:40.96#ibcon#read 4, iclass 28, count 0 2006.201.18:23:40.96#ibcon#about to read 5, iclass 28, count 0 2006.201.18:23:40.96#ibcon#read 5, iclass 28, count 0 2006.201.18:23:40.96#ibcon#about to read 6, iclass 28, count 0 2006.201.18:23:40.96#ibcon#read 6, iclass 28, count 0 2006.201.18:23:40.96#ibcon#end of sib2, iclass 28, count 0 2006.201.18:23:40.96#ibcon#*after write, iclass 28, count 0 2006.201.18:23:40.96#ibcon#*before return 0, iclass 28, count 0 2006.201.18:23:40.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:40.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:23:40.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:23:40.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:23:40.96$vck44/vb=5,4 2006.201.18:23:40.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.18:23:40.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.18:23:40.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:40.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:41.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:41.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:41.02#ibcon#enter wrdev, iclass 30, count 2 2006.201.18:23:41.02#ibcon#first serial, iclass 30, count 2 2006.201.18:23:41.02#ibcon#enter sib2, iclass 30, count 2 2006.201.18:23:41.02#ibcon#flushed, iclass 30, count 2 2006.201.18:23:41.02#ibcon#about to write, iclass 30, count 2 2006.201.18:23:41.02#ibcon#wrote, iclass 30, count 2 2006.201.18:23:41.02#ibcon#about to read 3, iclass 30, count 2 2006.201.18:23:41.04#ibcon#read 3, iclass 30, count 2 2006.201.18:23:41.04#ibcon#about to read 4, iclass 30, count 2 2006.201.18:23:41.04#ibcon#read 4, iclass 30, count 2 2006.201.18:23:41.04#ibcon#about to read 5, iclass 30, count 2 2006.201.18:23:41.04#ibcon#read 5, iclass 30, count 2 2006.201.18:23:41.04#ibcon#about to read 6, iclass 30, count 2 2006.201.18:23:41.04#ibcon#read 6, iclass 30, count 2 2006.201.18:23:41.04#ibcon#end of sib2, iclass 30, count 2 2006.201.18:23:41.04#ibcon#*mode == 0, iclass 30, count 2 2006.201.18:23:41.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.18:23:41.04#ibcon#[27=AT05-04\r\n] 2006.201.18:23:41.04#ibcon#*before write, iclass 30, count 2 2006.201.18:23:41.04#ibcon#enter sib2, iclass 30, count 2 2006.201.18:23:41.04#ibcon#flushed, iclass 30, count 2 2006.201.18:23:41.04#ibcon#about to write, iclass 30, count 2 2006.201.18:23:41.04#ibcon#wrote, iclass 30, count 2 2006.201.18:23:41.04#ibcon#about to read 3, iclass 30, count 2 2006.201.18:23:41.07#ibcon#read 3, iclass 30, count 2 2006.201.18:23:41.07#ibcon#about to read 4, iclass 30, count 2 2006.201.18:23:41.07#ibcon#read 4, iclass 30, count 2 2006.201.18:23:41.07#ibcon#about to read 5, iclass 30, count 2 2006.201.18:23:41.07#ibcon#read 5, iclass 30, count 2 2006.201.18:23:41.07#ibcon#about to read 6, iclass 30, count 2 2006.201.18:23:41.07#ibcon#read 6, iclass 30, count 2 2006.201.18:23:41.07#ibcon#end of sib2, iclass 30, count 2 2006.201.18:23:41.07#ibcon#*after write, iclass 30, count 2 2006.201.18:23:41.07#ibcon#*before return 0, iclass 30, count 2 2006.201.18:23:41.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:41.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:23:41.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.18:23:41.07#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:41.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:41.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:41.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:41.19#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:23:41.19#ibcon#first serial, iclass 30, count 0 2006.201.18:23:41.19#ibcon#enter sib2, iclass 30, count 0 2006.201.18:23:41.19#ibcon#flushed, iclass 30, count 0 2006.201.18:23:41.19#ibcon#about to write, iclass 30, count 0 2006.201.18:23:41.19#ibcon#wrote, iclass 30, count 0 2006.201.18:23:41.19#ibcon#about to read 3, iclass 30, count 0 2006.201.18:23:41.22#ibcon#read 3, iclass 30, count 0 2006.201.18:23:41.22#ibcon#about to read 4, iclass 30, count 0 2006.201.18:23:41.22#ibcon#read 4, iclass 30, count 0 2006.201.18:23:41.22#ibcon#about to read 5, iclass 30, count 0 2006.201.18:23:41.22#ibcon#read 5, iclass 30, count 0 2006.201.18:23:41.22#ibcon#about to read 6, iclass 30, count 0 2006.201.18:23:41.22#ibcon#read 6, iclass 30, count 0 2006.201.18:23:41.22#ibcon#end of sib2, iclass 30, count 0 2006.201.18:23:41.22#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:23:41.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:23:41.22#ibcon#[27=USB\r\n] 2006.201.18:23:41.22#ibcon#*before write, iclass 30, count 0 2006.201.18:23:41.22#ibcon#enter sib2, iclass 30, count 0 2006.201.18:23:41.22#ibcon#flushed, iclass 30, count 0 2006.201.18:23:41.22#ibcon#about to write, iclass 30, count 0 2006.201.18:23:41.22#ibcon#wrote, iclass 30, count 0 2006.201.18:23:41.22#ibcon#about to read 3, iclass 30, count 0 2006.201.18:23:41.25#ibcon#read 3, iclass 30, count 0 2006.201.18:23:41.25#ibcon#about to read 4, iclass 30, count 0 2006.201.18:23:41.25#ibcon#read 4, iclass 30, count 0 2006.201.18:23:41.25#ibcon#about to read 5, iclass 30, count 0 2006.201.18:23:41.25#ibcon#read 5, iclass 30, count 0 2006.201.18:23:41.25#ibcon#about to read 6, iclass 30, count 0 2006.201.18:23:41.25#ibcon#read 6, iclass 30, count 0 2006.201.18:23:41.25#ibcon#end of sib2, iclass 30, count 0 2006.201.18:23:41.25#ibcon#*after write, iclass 30, count 0 2006.201.18:23:41.25#ibcon#*before return 0, iclass 30, count 0 2006.201.18:23:41.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:41.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:23:41.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:23:41.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:23:41.25$vck44/vblo=6,719.99 2006.201.18:23:41.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.18:23:41.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.18:23:41.25#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:41.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:41.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:41.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:41.25#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:23:41.25#ibcon#first serial, iclass 32, count 0 2006.201.18:23:41.25#ibcon#enter sib2, iclass 32, count 0 2006.201.18:23:41.25#ibcon#flushed, iclass 32, count 0 2006.201.18:23:41.25#ibcon#about to write, iclass 32, count 0 2006.201.18:23:41.25#ibcon#wrote, iclass 32, count 0 2006.201.18:23:41.25#ibcon#about to read 3, iclass 32, count 0 2006.201.18:23:41.27#ibcon#read 3, iclass 32, count 0 2006.201.18:23:41.27#ibcon#about to read 4, iclass 32, count 0 2006.201.18:23:41.27#ibcon#read 4, iclass 32, count 0 2006.201.18:23:41.27#ibcon#about to read 5, iclass 32, count 0 2006.201.18:23:41.27#ibcon#read 5, iclass 32, count 0 2006.201.18:23:41.27#ibcon#about to read 6, iclass 32, count 0 2006.201.18:23:41.27#ibcon#read 6, iclass 32, count 0 2006.201.18:23:41.27#ibcon#end of sib2, iclass 32, count 0 2006.201.18:23:41.27#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:23:41.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:23:41.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:23:41.27#ibcon#*before write, iclass 32, count 0 2006.201.18:23:41.27#ibcon#enter sib2, iclass 32, count 0 2006.201.18:23:41.27#ibcon#flushed, iclass 32, count 0 2006.201.18:23:41.27#ibcon#about to write, iclass 32, count 0 2006.201.18:23:41.27#ibcon#wrote, iclass 32, count 0 2006.201.18:23:41.27#ibcon#about to read 3, iclass 32, count 0 2006.201.18:23:41.31#ibcon#read 3, iclass 32, count 0 2006.201.18:23:41.31#ibcon#about to read 4, iclass 32, count 0 2006.201.18:23:41.31#ibcon#read 4, iclass 32, count 0 2006.201.18:23:41.31#ibcon#about to read 5, iclass 32, count 0 2006.201.18:23:41.31#ibcon#read 5, iclass 32, count 0 2006.201.18:23:41.31#ibcon#about to read 6, iclass 32, count 0 2006.201.18:23:41.31#ibcon#read 6, iclass 32, count 0 2006.201.18:23:41.31#ibcon#end of sib2, iclass 32, count 0 2006.201.18:23:41.31#ibcon#*after write, iclass 32, count 0 2006.201.18:23:41.31#ibcon#*before return 0, iclass 32, count 0 2006.201.18:23:41.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:41.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:23:41.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:23:41.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:23:41.31$vck44/vb=6,4 2006.201.18:23:41.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.18:23:41.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.18:23:41.31#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:41.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:41.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:41.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:41.37#ibcon#enter wrdev, iclass 34, count 2 2006.201.18:23:41.37#ibcon#first serial, iclass 34, count 2 2006.201.18:23:41.37#ibcon#enter sib2, iclass 34, count 2 2006.201.18:23:41.37#ibcon#flushed, iclass 34, count 2 2006.201.18:23:41.37#ibcon#about to write, iclass 34, count 2 2006.201.18:23:41.37#ibcon#wrote, iclass 34, count 2 2006.201.18:23:41.37#ibcon#about to read 3, iclass 34, count 2 2006.201.18:23:41.39#ibcon#read 3, iclass 34, count 2 2006.201.18:23:41.39#ibcon#about to read 4, iclass 34, count 2 2006.201.18:23:41.39#ibcon#read 4, iclass 34, count 2 2006.201.18:23:41.39#ibcon#about to read 5, iclass 34, count 2 2006.201.18:23:41.39#ibcon#read 5, iclass 34, count 2 2006.201.18:23:41.39#ibcon#about to read 6, iclass 34, count 2 2006.201.18:23:41.39#ibcon#read 6, iclass 34, count 2 2006.201.18:23:41.39#ibcon#end of sib2, iclass 34, count 2 2006.201.18:23:41.39#ibcon#*mode == 0, iclass 34, count 2 2006.201.18:23:41.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.18:23:41.39#ibcon#[27=AT06-04\r\n] 2006.201.18:23:41.39#ibcon#*before write, iclass 34, count 2 2006.201.18:23:41.39#ibcon#enter sib2, iclass 34, count 2 2006.201.18:23:41.39#ibcon#flushed, iclass 34, count 2 2006.201.18:23:41.39#ibcon#about to write, iclass 34, count 2 2006.201.18:23:41.39#ibcon#wrote, iclass 34, count 2 2006.201.18:23:41.39#ibcon#about to read 3, iclass 34, count 2 2006.201.18:23:41.42#ibcon#read 3, iclass 34, count 2 2006.201.18:23:41.42#ibcon#about to read 4, iclass 34, count 2 2006.201.18:23:41.42#ibcon#read 4, iclass 34, count 2 2006.201.18:23:41.42#ibcon#about to read 5, iclass 34, count 2 2006.201.18:23:41.42#ibcon#read 5, iclass 34, count 2 2006.201.18:23:41.42#ibcon#about to read 6, iclass 34, count 2 2006.201.18:23:41.42#ibcon#read 6, iclass 34, count 2 2006.201.18:23:41.42#ibcon#end of sib2, iclass 34, count 2 2006.201.18:23:41.42#ibcon#*after write, iclass 34, count 2 2006.201.18:23:41.42#ibcon#*before return 0, iclass 34, count 2 2006.201.18:23:41.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:41.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:23:41.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.18:23:41.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:41.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:41.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:41.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:41.54#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:23:41.54#ibcon#first serial, iclass 34, count 0 2006.201.18:23:41.54#ibcon#enter sib2, iclass 34, count 0 2006.201.18:23:41.54#ibcon#flushed, iclass 34, count 0 2006.201.18:23:41.54#ibcon#about to write, iclass 34, count 0 2006.201.18:23:41.54#ibcon#wrote, iclass 34, count 0 2006.201.18:23:41.54#ibcon#about to read 3, iclass 34, count 0 2006.201.18:23:41.56#ibcon#read 3, iclass 34, count 0 2006.201.18:23:41.56#ibcon#about to read 4, iclass 34, count 0 2006.201.18:23:41.56#ibcon#read 4, iclass 34, count 0 2006.201.18:23:41.56#ibcon#about to read 5, iclass 34, count 0 2006.201.18:23:41.56#ibcon#read 5, iclass 34, count 0 2006.201.18:23:41.56#ibcon#about to read 6, iclass 34, count 0 2006.201.18:23:41.56#ibcon#read 6, iclass 34, count 0 2006.201.18:23:41.56#ibcon#end of sib2, iclass 34, count 0 2006.201.18:23:41.56#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:23:41.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:23:41.56#ibcon#[27=USB\r\n] 2006.201.18:23:41.56#ibcon#*before write, iclass 34, count 0 2006.201.18:23:41.56#ibcon#enter sib2, iclass 34, count 0 2006.201.18:23:41.56#ibcon#flushed, iclass 34, count 0 2006.201.18:23:41.56#ibcon#about to write, iclass 34, count 0 2006.201.18:23:41.56#ibcon#wrote, iclass 34, count 0 2006.201.18:23:41.56#ibcon#about to read 3, iclass 34, count 0 2006.201.18:23:41.59#ibcon#read 3, iclass 34, count 0 2006.201.18:23:41.59#ibcon#about to read 4, iclass 34, count 0 2006.201.18:23:41.59#ibcon#read 4, iclass 34, count 0 2006.201.18:23:41.59#ibcon#about to read 5, iclass 34, count 0 2006.201.18:23:41.59#ibcon#read 5, iclass 34, count 0 2006.201.18:23:41.59#ibcon#about to read 6, iclass 34, count 0 2006.201.18:23:41.59#ibcon#read 6, iclass 34, count 0 2006.201.18:23:41.59#ibcon#end of sib2, iclass 34, count 0 2006.201.18:23:41.59#ibcon#*after write, iclass 34, count 0 2006.201.18:23:41.59#ibcon#*before return 0, iclass 34, count 0 2006.201.18:23:41.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:41.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:23:41.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:23:41.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:23:41.59$vck44/vblo=7,734.99 2006.201.18:23:41.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.18:23:41.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.18:23:41.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:41.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:41.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:41.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:41.59#ibcon#enter wrdev, iclass 36, count 0 2006.201.18:23:41.59#ibcon#first serial, iclass 36, count 0 2006.201.18:23:41.59#ibcon#enter sib2, iclass 36, count 0 2006.201.18:23:41.59#ibcon#flushed, iclass 36, count 0 2006.201.18:23:41.59#ibcon#about to write, iclass 36, count 0 2006.201.18:23:41.59#ibcon#wrote, iclass 36, count 0 2006.201.18:23:41.59#ibcon#about to read 3, iclass 36, count 0 2006.201.18:23:41.61#ibcon#read 3, iclass 36, count 0 2006.201.18:23:41.61#ibcon#about to read 4, iclass 36, count 0 2006.201.18:23:41.61#ibcon#read 4, iclass 36, count 0 2006.201.18:23:41.61#ibcon#about to read 5, iclass 36, count 0 2006.201.18:23:41.61#ibcon#read 5, iclass 36, count 0 2006.201.18:23:41.61#ibcon#about to read 6, iclass 36, count 0 2006.201.18:23:41.61#ibcon#read 6, iclass 36, count 0 2006.201.18:23:41.61#ibcon#end of sib2, iclass 36, count 0 2006.201.18:23:41.61#ibcon#*mode == 0, iclass 36, count 0 2006.201.18:23:41.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.18:23:41.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:23:41.61#ibcon#*before write, iclass 36, count 0 2006.201.18:23:41.61#ibcon#enter sib2, iclass 36, count 0 2006.201.18:23:41.61#ibcon#flushed, iclass 36, count 0 2006.201.18:23:41.61#ibcon#about to write, iclass 36, count 0 2006.201.18:23:41.61#ibcon#wrote, iclass 36, count 0 2006.201.18:23:41.61#ibcon#about to read 3, iclass 36, count 0 2006.201.18:23:41.65#ibcon#read 3, iclass 36, count 0 2006.201.18:23:41.65#ibcon#about to read 4, iclass 36, count 0 2006.201.18:23:41.65#ibcon#read 4, iclass 36, count 0 2006.201.18:23:41.65#ibcon#about to read 5, iclass 36, count 0 2006.201.18:23:41.65#ibcon#read 5, iclass 36, count 0 2006.201.18:23:41.65#ibcon#about to read 6, iclass 36, count 0 2006.201.18:23:41.65#ibcon#read 6, iclass 36, count 0 2006.201.18:23:41.65#ibcon#end of sib2, iclass 36, count 0 2006.201.18:23:41.65#ibcon#*after write, iclass 36, count 0 2006.201.18:23:41.65#ibcon#*before return 0, iclass 36, count 0 2006.201.18:23:41.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:41.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:23:41.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.18:23:41.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.18:23:41.65$vck44/vb=7,4 2006.201.18:23:41.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.18:23:41.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.18:23:41.65#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:41.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:41.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:41.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:41.71#ibcon#enter wrdev, iclass 38, count 2 2006.201.18:23:41.71#ibcon#first serial, iclass 38, count 2 2006.201.18:23:41.71#ibcon#enter sib2, iclass 38, count 2 2006.201.18:23:41.71#ibcon#flushed, iclass 38, count 2 2006.201.18:23:41.71#ibcon#about to write, iclass 38, count 2 2006.201.18:23:41.71#ibcon#wrote, iclass 38, count 2 2006.201.18:23:41.71#ibcon#about to read 3, iclass 38, count 2 2006.201.18:23:41.73#ibcon#read 3, iclass 38, count 2 2006.201.18:23:41.73#ibcon#about to read 4, iclass 38, count 2 2006.201.18:23:41.73#ibcon#read 4, iclass 38, count 2 2006.201.18:23:41.73#ibcon#about to read 5, iclass 38, count 2 2006.201.18:23:41.73#ibcon#read 5, iclass 38, count 2 2006.201.18:23:41.73#ibcon#about to read 6, iclass 38, count 2 2006.201.18:23:41.73#ibcon#read 6, iclass 38, count 2 2006.201.18:23:41.73#ibcon#end of sib2, iclass 38, count 2 2006.201.18:23:41.73#ibcon#*mode == 0, iclass 38, count 2 2006.201.18:23:41.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.18:23:41.73#ibcon#[27=AT07-04\r\n] 2006.201.18:23:41.73#ibcon#*before write, iclass 38, count 2 2006.201.18:23:41.73#ibcon#enter sib2, iclass 38, count 2 2006.201.18:23:41.73#ibcon#flushed, iclass 38, count 2 2006.201.18:23:41.73#ibcon#about to write, iclass 38, count 2 2006.201.18:23:41.73#ibcon#wrote, iclass 38, count 2 2006.201.18:23:41.73#ibcon#about to read 3, iclass 38, count 2 2006.201.18:23:41.76#ibcon#read 3, iclass 38, count 2 2006.201.18:23:41.76#ibcon#about to read 4, iclass 38, count 2 2006.201.18:23:41.76#ibcon#read 4, iclass 38, count 2 2006.201.18:23:41.76#ibcon#about to read 5, iclass 38, count 2 2006.201.18:23:41.76#ibcon#read 5, iclass 38, count 2 2006.201.18:23:41.76#ibcon#about to read 6, iclass 38, count 2 2006.201.18:23:41.76#ibcon#read 6, iclass 38, count 2 2006.201.18:23:41.76#ibcon#end of sib2, iclass 38, count 2 2006.201.18:23:41.76#ibcon#*after write, iclass 38, count 2 2006.201.18:23:41.76#ibcon#*before return 0, iclass 38, count 2 2006.201.18:23:41.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:41.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:23:41.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.18:23:41.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:41.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:41.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:41.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:41.88#ibcon#enter wrdev, iclass 38, count 0 2006.201.18:23:41.88#ibcon#first serial, iclass 38, count 0 2006.201.18:23:41.88#ibcon#enter sib2, iclass 38, count 0 2006.201.18:23:41.88#ibcon#flushed, iclass 38, count 0 2006.201.18:23:41.88#ibcon#about to write, iclass 38, count 0 2006.201.18:23:41.88#ibcon#wrote, iclass 38, count 0 2006.201.18:23:41.88#ibcon#about to read 3, iclass 38, count 0 2006.201.18:23:41.90#ibcon#read 3, iclass 38, count 0 2006.201.18:23:41.90#ibcon#about to read 4, iclass 38, count 0 2006.201.18:23:41.90#ibcon#read 4, iclass 38, count 0 2006.201.18:23:41.90#ibcon#about to read 5, iclass 38, count 0 2006.201.18:23:41.90#ibcon#read 5, iclass 38, count 0 2006.201.18:23:41.90#ibcon#about to read 6, iclass 38, count 0 2006.201.18:23:41.90#ibcon#read 6, iclass 38, count 0 2006.201.18:23:41.90#ibcon#end of sib2, iclass 38, count 0 2006.201.18:23:41.90#ibcon#*mode == 0, iclass 38, count 0 2006.201.18:23:41.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.18:23:41.90#ibcon#[27=USB\r\n] 2006.201.18:23:41.90#ibcon#*before write, iclass 38, count 0 2006.201.18:23:41.90#ibcon#enter sib2, iclass 38, count 0 2006.201.18:23:41.90#ibcon#flushed, iclass 38, count 0 2006.201.18:23:41.90#ibcon#about to write, iclass 38, count 0 2006.201.18:23:41.90#ibcon#wrote, iclass 38, count 0 2006.201.18:23:41.90#ibcon#about to read 3, iclass 38, count 0 2006.201.18:23:41.93#ibcon#read 3, iclass 38, count 0 2006.201.18:23:41.93#ibcon#about to read 4, iclass 38, count 0 2006.201.18:23:41.93#ibcon#read 4, iclass 38, count 0 2006.201.18:23:41.93#ibcon#about to read 5, iclass 38, count 0 2006.201.18:23:41.93#ibcon#read 5, iclass 38, count 0 2006.201.18:23:41.93#ibcon#about to read 6, iclass 38, count 0 2006.201.18:23:41.93#ibcon#read 6, iclass 38, count 0 2006.201.18:23:41.93#ibcon#end of sib2, iclass 38, count 0 2006.201.18:23:41.93#ibcon#*after write, iclass 38, count 0 2006.201.18:23:41.93#ibcon#*before return 0, iclass 38, count 0 2006.201.18:23:41.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:41.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:23:41.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.18:23:41.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.18:23:41.93$vck44/vblo=8,744.99 2006.201.18:23:41.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.18:23:41.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.18:23:41.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:23:41.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:41.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:41.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:41.93#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:23:41.93#ibcon#first serial, iclass 40, count 0 2006.201.18:23:41.93#ibcon#enter sib2, iclass 40, count 0 2006.201.18:23:41.93#ibcon#flushed, iclass 40, count 0 2006.201.18:23:41.93#ibcon#about to write, iclass 40, count 0 2006.201.18:23:41.93#ibcon#wrote, iclass 40, count 0 2006.201.18:23:41.93#ibcon#about to read 3, iclass 40, count 0 2006.201.18:23:41.95#ibcon#read 3, iclass 40, count 0 2006.201.18:23:41.95#ibcon#about to read 4, iclass 40, count 0 2006.201.18:23:41.95#ibcon#read 4, iclass 40, count 0 2006.201.18:23:41.95#ibcon#about to read 5, iclass 40, count 0 2006.201.18:23:41.95#ibcon#read 5, iclass 40, count 0 2006.201.18:23:41.95#ibcon#about to read 6, iclass 40, count 0 2006.201.18:23:41.95#ibcon#read 6, iclass 40, count 0 2006.201.18:23:41.95#ibcon#end of sib2, iclass 40, count 0 2006.201.18:23:41.95#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:23:41.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:23:41.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:23:41.95#ibcon#*before write, iclass 40, count 0 2006.201.18:23:41.95#ibcon#enter sib2, iclass 40, count 0 2006.201.18:23:41.95#ibcon#flushed, iclass 40, count 0 2006.201.18:23:41.95#ibcon#about to write, iclass 40, count 0 2006.201.18:23:41.95#ibcon#wrote, iclass 40, count 0 2006.201.18:23:41.95#ibcon#about to read 3, iclass 40, count 0 2006.201.18:23:41.99#ibcon#read 3, iclass 40, count 0 2006.201.18:23:41.99#ibcon#about to read 4, iclass 40, count 0 2006.201.18:23:41.99#ibcon#read 4, iclass 40, count 0 2006.201.18:23:41.99#ibcon#about to read 5, iclass 40, count 0 2006.201.18:23:41.99#ibcon#read 5, iclass 40, count 0 2006.201.18:23:41.99#ibcon#about to read 6, iclass 40, count 0 2006.201.18:23:41.99#ibcon#read 6, iclass 40, count 0 2006.201.18:23:41.99#ibcon#end of sib2, iclass 40, count 0 2006.201.18:23:41.99#ibcon#*after write, iclass 40, count 0 2006.201.18:23:41.99#ibcon#*before return 0, iclass 40, count 0 2006.201.18:23:41.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:41.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:23:41.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:23:41.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:23:41.99$vck44/vb=8,4 2006.201.18:23:41.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.18:23:41.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.18:23:41.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:23:41.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:42.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:42.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:42.05#ibcon#enter wrdev, iclass 4, count 2 2006.201.18:23:42.05#ibcon#first serial, iclass 4, count 2 2006.201.18:23:42.05#ibcon#enter sib2, iclass 4, count 2 2006.201.18:23:42.05#ibcon#flushed, iclass 4, count 2 2006.201.18:23:42.05#ibcon#about to write, iclass 4, count 2 2006.201.18:23:42.05#ibcon#wrote, iclass 4, count 2 2006.201.18:23:42.05#ibcon#about to read 3, iclass 4, count 2 2006.201.18:23:42.07#ibcon#read 3, iclass 4, count 2 2006.201.18:23:42.07#ibcon#about to read 4, iclass 4, count 2 2006.201.18:23:42.07#ibcon#read 4, iclass 4, count 2 2006.201.18:23:42.07#ibcon#about to read 5, iclass 4, count 2 2006.201.18:23:42.07#ibcon#read 5, iclass 4, count 2 2006.201.18:23:42.07#ibcon#about to read 6, iclass 4, count 2 2006.201.18:23:42.07#ibcon#read 6, iclass 4, count 2 2006.201.18:23:42.07#ibcon#end of sib2, iclass 4, count 2 2006.201.18:23:42.07#ibcon#*mode == 0, iclass 4, count 2 2006.201.18:23:42.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.18:23:42.07#ibcon#[27=AT08-04\r\n] 2006.201.18:23:42.07#ibcon#*before write, iclass 4, count 2 2006.201.18:23:42.07#ibcon#enter sib2, iclass 4, count 2 2006.201.18:23:42.07#ibcon#flushed, iclass 4, count 2 2006.201.18:23:42.07#ibcon#about to write, iclass 4, count 2 2006.201.18:23:42.07#ibcon#wrote, iclass 4, count 2 2006.201.18:23:42.07#ibcon#about to read 3, iclass 4, count 2 2006.201.18:23:42.10#ibcon#read 3, iclass 4, count 2 2006.201.18:23:42.10#ibcon#about to read 4, iclass 4, count 2 2006.201.18:23:42.10#ibcon#read 4, iclass 4, count 2 2006.201.18:23:42.10#ibcon#about to read 5, iclass 4, count 2 2006.201.18:23:42.10#ibcon#read 5, iclass 4, count 2 2006.201.18:23:42.10#ibcon#about to read 6, iclass 4, count 2 2006.201.18:23:42.10#ibcon#read 6, iclass 4, count 2 2006.201.18:23:42.10#ibcon#end of sib2, iclass 4, count 2 2006.201.18:23:42.10#ibcon#*after write, iclass 4, count 2 2006.201.18:23:42.10#ibcon#*before return 0, iclass 4, count 2 2006.201.18:23:42.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:42.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:23:42.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.18:23:42.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:23:42.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:42.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:42.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:42.22#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:23:42.22#ibcon#first serial, iclass 4, count 0 2006.201.18:23:42.22#ibcon#enter sib2, iclass 4, count 0 2006.201.18:23:42.22#ibcon#flushed, iclass 4, count 0 2006.201.18:23:42.22#ibcon#about to write, iclass 4, count 0 2006.201.18:23:42.22#ibcon#wrote, iclass 4, count 0 2006.201.18:23:42.22#ibcon#about to read 3, iclass 4, count 0 2006.201.18:23:42.24#ibcon#read 3, iclass 4, count 0 2006.201.18:23:42.24#ibcon#about to read 4, iclass 4, count 0 2006.201.18:23:42.24#ibcon#read 4, iclass 4, count 0 2006.201.18:23:42.24#ibcon#about to read 5, iclass 4, count 0 2006.201.18:23:42.24#ibcon#read 5, iclass 4, count 0 2006.201.18:23:42.24#ibcon#about to read 6, iclass 4, count 0 2006.201.18:23:42.24#ibcon#read 6, iclass 4, count 0 2006.201.18:23:42.24#ibcon#end of sib2, iclass 4, count 0 2006.201.18:23:42.24#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:23:42.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:23:42.24#ibcon#[27=USB\r\n] 2006.201.18:23:42.24#ibcon#*before write, iclass 4, count 0 2006.201.18:23:42.24#ibcon#enter sib2, iclass 4, count 0 2006.201.18:23:42.24#ibcon#flushed, iclass 4, count 0 2006.201.18:23:42.24#ibcon#about to write, iclass 4, count 0 2006.201.18:23:42.24#ibcon#wrote, iclass 4, count 0 2006.201.18:23:42.24#ibcon#about to read 3, iclass 4, count 0 2006.201.18:23:42.27#ibcon#read 3, iclass 4, count 0 2006.201.18:23:42.27#ibcon#about to read 4, iclass 4, count 0 2006.201.18:23:42.27#ibcon#read 4, iclass 4, count 0 2006.201.18:23:42.27#ibcon#about to read 5, iclass 4, count 0 2006.201.18:23:42.27#ibcon#read 5, iclass 4, count 0 2006.201.18:23:42.27#ibcon#about to read 6, iclass 4, count 0 2006.201.18:23:42.27#ibcon#read 6, iclass 4, count 0 2006.201.18:23:42.27#ibcon#end of sib2, iclass 4, count 0 2006.201.18:23:42.27#ibcon#*after write, iclass 4, count 0 2006.201.18:23:42.27#ibcon#*before return 0, iclass 4, count 0 2006.201.18:23:42.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:42.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:23:42.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:23:42.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:23:42.27$vck44/vabw=wide 2006.201.18:23:42.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.18:23:42.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.18:23:42.27#ibcon#ireg 8 cls_cnt 0 2006.201.18:23:42.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:42.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:42.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:42.27#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:23:42.27#ibcon#first serial, iclass 6, count 0 2006.201.18:23:42.27#ibcon#enter sib2, iclass 6, count 0 2006.201.18:23:42.27#ibcon#flushed, iclass 6, count 0 2006.201.18:23:42.27#ibcon#about to write, iclass 6, count 0 2006.201.18:23:42.27#ibcon#wrote, iclass 6, count 0 2006.201.18:23:42.27#ibcon#about to read 3, iclass 6, count 0 2006.201.18:23:42.29#ibcon#read 3, iclass 6, count 0 2006.201.18:23:42.29#ibcon#about to read 4, iclass 6, count 0 2006.201.18:23:42.29#ibcon#read 4, iclass 6, count 0 2006.201.18:23:42.29#ibcon#about to read 5, iclass 6, count 0 2006.201.18:23:42.29#ibcon#read 5, iclass 6, count 0 2006.201.18:23:42.29#ibcon#about to read 6, iclass 6, count 0 2006.201.18:23:42.29#ibcon#read 6, iclass 6, count 0 2006.201.18:23:42.29#ibcon#end of sib2, iclass 6, count 0 2006.201.18:23:42.29#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:23:42.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:23:42.29#ibcon#[25=BW32\r\n] 2006.201.18:23:42.29#ibcon#*before write, iclass 6, count 0 2006.201.18:23:42.29#ibcon#enter sib2, iclass 6, count 0 2006.201.18:23:42.29#ibcon#flushed, iclass 6, count 0 2006.201.18:23:42.29#ibcon#about to write, iclass 6, count 0 2006.201.18:23:42.29#ibcon#wrote, iclass 6, count 0 2006.201.18:23:42.29#ibcon#about to read 3, iclass 6, count 0 2006.201.18:23:42.33#ibcon#read 3, iclass 6, count 0 2006.201.18:23:42.33#ibcon#about to read 4, iclass 6, count 0 2006.201.18:23:42.33#ibcon#read 4, iclass 6, count 0 2006.201.18:23:42.33#ibcon#about to read 5, iclass 6, count 0 2006.201.18:23:42.33#ibcon#read 5, iclass 6, count 0 2006.201.18:23:42.33#ibcon#about to read 6, iclass 6, count 0 2006.201.18:23:42.33#ibcon#read 6, iclass 6, count 0 2006.201.18:23:42.33#ibcon#end of sib2, iclass 6, count 0 2006.201.18:23:42.33#ibcon#*after write, iclass 6, count 0 2006.201.18:23:42.33#ibcon#*before return 0, iclass 6, count 0 2006.201.18:23:42.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:42.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:23:42.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:23:42.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:23:42.33$vck44/vbbw=wide 2006.201.18:23:42.33#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.18:23:42.33#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.18:23:42.33#ibcon#ireg 8 cls_cnt 0 2006.201.18:23:42.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:23:42.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:23:42.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:23:42.39#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:23:42.39#ibcon#first serial, iclass 10, count 0 2006.201.18:23:42.39#ibcon#enter sib2, iclass 10, count 0 2006.201.18:23:42.39#ibcon#flushed, iclass 10, count 0 2006.201.18:23:42.39#ibcon#about to write, iclass 10, count 0 2006.201.18:23:42.39#ibcon#wrote, iclass 10, count 0 2006.201.18:23:42.39#ibcon#about to read 3, iclass 10, count 0 2006.201.18:23:42.41#ibcon#read 3, iclass 10, count 0 2006.201.18:23:42.41#ibcon#about to read 4, iclass 10, count 0 2006.201.18:23:42.41#ibcon#read 4, iclass 10, count 0 2006.201.18:23:42.41#ibcon#about to read 5, iclass 10, count 0 2006.201.18:23:42.41#ibcon#read 5, iclass 10, count 0 2006.201.18:23:42.41#ibcon#about to read 6, iclass 10, count 0 2006.201.18:23:42.41#ibcon#read 6, iclass 10, count 0 2006.201.18:23:42.41#ibcon#end of sib2, iclass 10, count 0 2006.201.18:23:42.41#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:23:42.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:23:42.41#ibcon#[27=BW32\r\n] 2006.201.18:23:42.41#ibcon#*before write, iclass 10, count 0 2006.201.18:23:42.41#ibcon#enter sib2, iclass 10, count 0 2006.201.18:23:42.41#ibcon#flushed, iclass 10, count 0 2006.201.18:23:42.41#ibcon#about to write, iclass 10, count 0 2006.201.18:23:42.41#ibcon#wrote, iclass 10, count 0 2006.201.18:23:42.41#ibcon#about to read 3, iclass 10, count 0 2006.201.18:23:42.44#ibcon#read 3, iclass 10, count 0 2006.201.18:23:42.44#ibcon#about to read 4, iclass 10, count 0 2006.201.18:23:42.44#ibcon#read 4, iclass 10, count 0 2006.201.18:23:42.44#ibcon#about to read 5, iclass 10, count 0 2006.201.18:23:42.44#ibcon#read 5, iclass 10, count 0 2006.201.18:23:42.44#ibcon#about to read 6, iclass 10, count 0 2006.201.18:23:42.44#ibcon#read 6, iclass 10, count 0 2006.201.18:23:42.44#ibcon#end of sib2, iclass 10, count 0 2006.201.18:23:42.44#ibcon#*after write, iclass 10, count 0 2006.201.18:23:42.44#ibcon#*before return 0, iclass 10, count 0 2006.201.18:23:42.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:23:42.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:23:42.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:23:42.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:23:42.44$setupk4/ifdk4 2006.201.18:23:42.44$ifdk4/lo= 2006.201.18:23:42.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:23:42.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:23:42.44$ifdk4/patch= 2006.201.18:23:42.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:23:42.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:23:42.44$setupk4/!*+20s 2006.201.18:23:47.54#abcon#<5=/02 0.7 1.4 20.481001002.0\r\n> 2006.201.18:23:47.56#abcon#{5=INTERFACE CLEAR} 2006.201.18:23:47.62#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:23:50.14#trakl#Source acquired 2006.201.18:23:50.14#flagr#flagr/antenna,acquired 2006.201.18:23:56.88$setupk4/"tpicd 2006.201.18:23:56.88$setupk4/echo=off 2006.201.18:23:56.88$setupk4/xlog=off 2006.201.18:23:56.88:!2006.201.18:24:15 2006.201.18:24:15.00:preob 2006.201.18:24:15.14/onsource/TRACKING 2006.201.18:24:15.14:!2006.201.18:24:25 2006.201.18:24:25.00:"tape 2006.201.18:24:25.00:"st=record 2006.201.18:24:25.00:data_valid=on 2006.201.18:24:25.00:midob 2006.201.18:24:26.14/onsource/TRACKING 2006.201.18:24:26.14/wx/20.48,1002.0,100 2006.201.18:24:26.28/cable/+6.4780E-03 2006.201.18:24:27.37/va/01,08,usb,yes,37,39 2006.201.18:24:27.37/va/02,07,usb,yes,39,40 2006.201.18:24:27.37/va/03,08,usb,yes,36,37 2006.201.18:24:27.37/va/04,07,usb,yes,41,43 2006.201.18:24:27.37/va/05,04,usb,yes,36,37 2006.201.18:24:27.37/va/06,05,usb,yes,36,36 2006.201.18:24:27.37/va/07,05,usb,yes,36,37 2006.201.18:24:27.37/va/08,04,usb,yes,35,42 2006.201.18:24:27.60/valo/01,524.99,yes,locked 2006.201.18:24:27.60/valo/02,534.99,yes,locked 2006.201.18:24:27.60/valo/03,564.99,yes,locked 2006.201.18:24:27.60/valo/04,624.99,yes,locked 2006.201.18:24:27.60/valo/05,734.99,yes,locked 2006.201.18:24:27.60/valo/06,814.99,yes,locked 2006.201.18:24:27.60/valo/07,864.99,yes,locked 2006.201.18:24:27.60/valo/08,884.99,yes,locked 2006.201.18:24:28.69/vb/01,04,usb,yes,30,27 2006.201.18:24:28.69/vb/02,05,usb,yes,28,28 2006.201.18:24:28.69/vb/03,04,usb,yes,29,32 2006.201.18:24:28.69/vb/04,05,usb,yes,29,28 2006.201.18:24:28.69/vb/05,04,usb,yes,26,28 2006.201.18:24:28.69/vb/06,04,usb,yes,30,27 2006.201.18:24:28.69/vb/07,04,usb,yes,30,30 2006.201.18:24:28.69/vb/08,04,usb,yes,28,31 2006.201.18:24:28.93/vblo/01,629.99,yes,locked 2006.201.18:24:28.93/vblo/02,634.99,yes,locked 2006.201.18:24:28.93/vblo/03,649.99,yes,locked 2006.201.18:24:28.93/vblo/04,679.99,yes,locked 2006.201.18:24:28.93/vblo/05,709.99,yes,locked 2006.201.18:24:28.93/vblo/06,719.99,yes,locked 2006.201.18:24:28.93/vblo/07,734.99,yes,locked 2006.201.18:24:28.93/vblo/08,744.99,yes,locked 2006.201.18:24:29.08/vabw/8 2006.201.18:24:29.23/vbbw/8 2006.201.18:24:29.32/xfe/off,on,15.5 2006.201.18:24:29.71/ifatt/23,28,28,28 2006.201.18:24:30.06/fmout-gps/S +4.56E-07 2006.201.18:24:30.13:!2006.201.18:29:25 2006.201.18:29:25.00:data_valid=off 2006.201.18:29:25.00:"et 2006.201.18:29:25.00:!+3s 2006.201.18:29:28.01:"tape 2006.201.18:29:28.01:postob 2006.201.18:29:28.20/cable/+6.4768E-03 2006.201.18:29:28.20/wx/20.50,1002.0,100 2006.201.18:29:28.26/fmout-gps/S +4.55E-07 2006.201.18:29:28.26:scan_name=201-1838,jd0607,40 2006.201.18:29:28.26:source=3c454.3,225357.75,160853.6,2000.0,cw 2006.201.18:29:29.14#flagr#flagr/antenna,new-source 2006.201.18:29:29.14:checkk5 2006.201.18:29:29.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:29:29.93/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:29:30.31/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:29:30.69/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:29:31.05/chk_obsdata//k5ts1/T2011824??a.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.201.18:29:31.42/chk_obsdata//k5ts2/T2011824??b.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.201.18:29:31.79/chk_obsdata//k5ts3/T2011824??c.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.201.18:29:32.15/chk_obsdata//k5ts4/T2011824??d.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.201.18:29:32.84/k5log//k5ts1_log_newline 2006.201.18:29:33.54/k5log//k5ts2_log_newline 2006.201.18:29:34.23/k5log//k5ts3_log_newline 2006.201.18:29:34.91/k5log//k5ts4_log_newline 2006.201.18:29:34.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:29:34.94:setupk4=1 2006.201.18:29:34.94$setupk4/echo=on 2006.201.18:29:34.94$setupk4/pcalon 2006.201.18:29:34.94$pcalon/"no phase cal control is implemented here 2006.201.18:29:34.94$setupk4/"tpicd=stop 2006.201.18:29:34.94$setupk4/"rec=synch_on 2006.201.18:29:34.94$setupk4/"rec_mode=128 2006.201.18:29:34.94$setupk4/!* 2006.201.18:29:34.94$setupk4/recpk4 2006.201.18:29:34.94$recpk4/recpatch= 2006.201.18:29:34.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:29:34.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:29:34.94$setupk4/vck44 2006.201.18:29:34.94$vck44/valo=1,524.99 2006.201.18:29:34.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.18:29:34.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.18:29:34.94#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:34.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:34.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:34.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:34.94#ibcon#enter wrdev, iclass 11, count 0 2006.201.18:29:34.94#ibcon#first serial, iclass 11, count 0 2006.201.18:29:34.94#ibcon#enter sib2, iclass 11, count 0 2006.201.18:29:34.94#ibcon#flushed, iclass 11, count 0 2006.201.18:29:34.94#ibcon#about to write, iclass 11, count 0 2006.201.18:29:34.94#ibcon#wrote, iclass 11, count 0 2006.201.18:29:34.94#ibcon#about to read 3, iclass 11, count 0 2006.201.18:29:34.98#ibcon#read 3, iclass 11, count 0 2006.201.18:29:34.98#ibcon#about to read 4, iclass 11, count 0 2006.201.18:29:34.98#ibcon#read 4, iclass 11, count 0 2006.201.18:29:34.98#ibcon#about to read 5, iclass 11, count 0 2006.201.18:29:34.98#ibcon#read 5, iclass 11, count 0 2006.201.18:29:34.98#ibcon#about to read 6, iclass 11, count 0 2006.201.18:29:34.98#ibcon#read 6, iclass 11, count 0 2006.201.18:29:34.98#ibcon#end of sib2, iclass 11, count 0 2006.201.18:29:34.98#ibcon#*mode == 0, iclass 11, count 0 2006.201.18:29:34.98#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.18:29:34.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:29:34.98#ibcon#*before write, iclass 11, count 0 2006.201.18:29:34.98#ibcon#enter sib2, iclass 11, count 0 2006.201.18:29:34.98#ibcon#flushed, iclass 11, count 0 2006.201.18:29:34.98#ibcon#about to write, iclass 11, count 0 2006.201.18:29:34.98#ibcon#wrote, iclass 11, count 0 2006.201.18:29:34.98#ibcon#about to read 3, iclass 11, count 0 2006.201.18:29:35.03#ibcon#read 3, iclass 11, count 0 2006.201.18:29:35.03#ibcon#about to read 4, iclass 11, count 0 2006.201.18:29:35.03#ibcon#read 4, iclass 11, count 0 2006.201.18:29:35.03#ibcon#about to read 5, iclass 11, count 0 2006.201.18:29:35.03#ibcon#read 5, iclass 11, count 0 2006.201.18:29:35.03#ibcon#about to read 6, iclass 11, count 0 2006.201.18:29:35.03#ibcon#read 6, iclass 11, count 0 2006.201.18:29:35.03#ibcon#end of sib2, iclass 11, count 0 2006.201.18:29:35.03#ibcon#*after write, iclass 11, count 0 2006.201.18:29:35.03#ibcon#*before return 0, iclass 11, count 0 2006.201.18:29:35.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:35.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:35.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.18:29:35.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.18:29:35.03$vck44/va=1,8 2006.201.18:29:35.03#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.18:29:35.03#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.18:29:35.03#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:35.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:35.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:35.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:35.03#ibcon#enter wrdev, iclass 13, count 2 2006.201.18:29:35.03#ibcon#first serial, iclass 13, count 2 2006.201.18:29:35.03#ibcon#enter sib2, iclass 13, count 2 2006.201.18:29:35.03#ibcon#flushed, iclass 13, count 2 2006.201.18:29:35.03#ibcon#about to write, iclass 13, count 2 2006.201.18:29:35.03#ibcon#wrote, iclass 13, count 2 2006.201.18:29:35.03#ibcon#about to read 3, iclass 13, count 2 2006.201.18:29:35.05#ibcon#read 3, iclass 13, count 2 2006.201.18:29:35.05#ibcon#about to read 4, iclass 13, count 2 2006.201.18:29:35.05#ibcon#read 4, iclass 13, count 2 2006.201.18:29:35.05#ibcon#about to read 5, iclass 13, count 2 2006.201.18:29:35.05#ibcon#read 5, iclass 13, count 2 2006.201.18:29:35.05#ibcon#about to read 6, iclass 13, count 2 2006.201.18:29:35.05#ibcon#read 6, iclass 13, count 2 2006.201.18:29:35.05#ibcon#end of sib2, iclass 13, count 2 2006.201.18:29:35.05#ibcon#*mode == 0, iclass 13, count 2 2006.201.18:29:35.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.18:29:35.05#ibcon#[25=AT01-08\r\n] 2006.201.18:29:35.05#ibcon#*before write, iclass 13, count 2 2006.201.18:29:35.05#ibcon#enter sib2, iclass 13, count 2 2006.201.18:29:35.05#ibcon#flushed, iclass 13, count 2 2006.201.18:29:35.05#ibcon#about to write, iclass 13, count 2 2006.201.18:29:35.05#ibcon#wrote, iclass 13, count 2 2006.201.18:29:35.05#ibcon#about to read 3, iclass 13, count 2 2006.201.18:29:35.09#ibcon#read 3, iclass 13, count 2 2006.201.18:29:35.09#ibcon#about to read 4, iclass 13, count 2 2006.201.18:29:35.09#ibcon#read 4, iclass 13, count 2 2006.201.18:29:35.09#ibcon#about to read 5, iclass 13, count 2 2006.201.18:29:35.09#ibcon#read 5, iclass 13, count 2 2006.201.18:29:35.09#ibcon#about to read 6, iclass 13, count 2 2006.201.18:29:35.09#ibcon#read 6, iclass 13, count 2 2006.201.18:29:35.09#ibcon#end of sib2, iclass 13, count 2 2006.201.18:29:35.09#ibcon#*after write, iclass 13, count 2 2006.201.18:29:35.09#ibcon#*before return 0, iclass 13, count 2 2006.201.18:29:35.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:35.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:35.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.18:29:35.09#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:35.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:35.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:35.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:35.21#ibcon#enter wrdev, iclass 13, count 0 2006.201.18:29:35.21#ibcon#first serial, iclass 13, count 0 2006.201.18:29:35.21#ibcon#enter sib2, iclass 13, count 0 2006.201.18:29:35.21#ibcon#flushed, iclass 13, count 0 2006.201.18:29:35.21#ibcon#about to write, iclass 13, count 0 2006.201.18:29:35.21#ibcon#wrote, iclass 13, count 0 2006.201.18:29:35.21#ibcon#about to read 3, iclass 13, count 0 2006.201.18:29:35.24#ibcon#read 3, iclass 13, count 0 2006.201.18:29:35.24#ibcon#about to read 4, iclass 13, count 0 2006.201.18:29:35.24#ibcon#read 4, iclass 13, count 0 2006.201.18:29:35.24#ibcon#about to read 5, iclass 13, count 0 2006.201.18:29:35.24#ibcon#read 5, iclass 13, count 0 2006.201.18:29:35.24#ibcon#about to read 6, iclass 13, count 0 2006.201.18:29:35.24#ibcon#read 6, iclass 13, count 0 2006.201.18:29:35.24#ibcon#end of sib2, iclass 13, count 0 2006.201.18:29:35.24#ibcon#*mode == 0, iclass 13, count 0 2006.201.18:29:35.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.18:29:35.24#ibcon#[25=USB\r\n] 2006.201.18:29:35.24#ibcon#*before write, iclass 13, count 0 2006.201.18:29:35.24#ibcon#enter sib2, iclass 13, count 0 2006.201.18:29:35.24#ibcon#flushed, iclass 13, count 0 2006.201.18:29:35.24#ibcon#about to write, iclass 13, count 0 2006.201.18:29:35.24#ibcon#wrote, iclass 13, count 0 2006.201.18:29:35.24#ibcon#about to read 3, iclass 13, count 0 2006.201.18:29:35.27#ibcon#read 3, iclass 13, count 0 2006.201.18:29:35.27#ibcon#about to read 4, iclass 13, count 0 2006.201.18:29:35.27#ibcon#read 4, iclass 13, count 0 2006.201.18:29:35.27#ibcon#about to read 5, iclass 13, count 0 2006.201.18:29:35.27#ibcon#read 5, iclass 13, count 0 2006.201.18:29:35.27#ibcon#about to read 6, iclass 13, count 0 2006.201.18:29:35.27#ibcon#read 6, iclass 13, count 0 2006.201.18:29:35.27#ibcon#end of sib2, iclass 13, count 0 2006.201.18:29:35.27#ibcon#*after write, iclass 13, count 0 2006.201.18:29:35.27#ibcon#*before return 0, iclass 13, count 0 2006.201.18:29:35.27#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:35.27#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:35.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.18:29:35.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.18:29:35.27$vck44/valo=2,534.99 2006.201.18:29:35.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.18:29:35.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.18:29:35.27#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:35.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:35.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:35.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:35.27#ibcon#enter wrdev, iclass 15, count 0 2006.201.18:29:35.27#ibcon#first serial, iclass 15, count 0 2006.201.18:29:35.27#ibcon#enter sib2, iclass 15, count 0 2006.201.18:29:35.27#ibcon#flushed, iclass 15, count 0 2006.201.18:29:35.27#ibcon#about to write, iclass 15, count 0 2006.201.18:29:35.27#ibcon#wrote, iclass 15, count 0 2006.201.18:29:35.27#ibcon#about to read 3, iclass 15, count 0 2006.201.18:29:35.29#ibcon#read 3, iclass 15, count 0 2006.201.18:29:35.29#ibcon#about to read 4, iclass 15, count 0 2006.201.18:29:35.29#ibcon#read 4, iclass 15, count 0 2006.201.18:29:35.29#ibcon#about to read 5, iclass 15, count 0 2006.201.18:29:35.29#ibcon#read 5, iclass 15, count 0 2006.201.18:29:35.29#ibcon#about to read 6, iclass 15, count 0 2006.201.18:29:35.29#ibcon#read 6, iclass 15, count 0 2006.201.18:29:35.29#ibcon#end of sib2, iclass 15, count 0 2006.201.18:29:35.29#ibcon#*mode == 0, iclass 15, count 0 2006.201.18:29:35.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.18:29:35.29#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:29:35.29#ibcon#*before write, iclass 15, count 0 2006.201.18:29:35.29#ibcon#enter sib2, iclass 15, count 0 2006.201.18:29:35.29#ibcon#flushed, iclass 15, count 0 2006.201.18:29:35.29#ibcon#about to write, iclass 15, count 0 2006.201.18:29:35.29#ibcon#wrote, iclass 15, count 0 2006.201.18:29:35.29#ibcon#about to read 3, iclass 15, count 0 2006.201.18:29:35.33#ibcon#read 3, iclass 15, count 0 2006.201.18:29:35.33#ibcon#about to read 4, iclass 15, count 0 2006.201.18:29:35.33#ibcon#read 4, iclass 15, count 0 2006.201.18:29:35.33#ibcon#about to read 5, iclass 15, count 0 2006.201.18:29:35.33#ibcon#read 5, iclass 15, count 0 2006.201.18:29:35.33#ibcon#about to read 6, iclass 15, count 0 2006.201.18:29:35.33#ibcon#read 6, iclass 15, count 0 2006.201.18:29:35.33#ibcon#end of sib2, iclass 15, count 0 2006.201.18:29:35.33#ibcon#*after write, iclass 15, count 0 2006.201.18:29:35.33#ibcon#*before return 0, iclass 15, count 0 2006.201.18:29:35.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:35.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:35.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.18:29:35.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.18:29:35.33$vck44/va=2,7 2006.201.18:29:35.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.18:29:35.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.18:29:35.33#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:35.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:35.39#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:35.39#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:35.39#ibcon#enter wrdev, iclass 17, count 2 2006.201.18:29:35.39#ibcon#first serial, iclass 17, count 2 2006.201.18:29:35.39#ibcon#enter sib2, iclass 17, count 2 2006.201.18:29:35.39#ibcon#flushed, iclass 17, count 2 2006.201.18:29:35.39#ibcon#about to write, iclass 17, count 2 2006.201.18:29:35.39#ibcon#wrote, iclass 17, count 2 2006.201.18:29:35.39#ibcon#about to read 3, iclass 17, count 2 2006.201.18:29:35.41#ibcon#read 3, iclass 17, count 2 2006.201.18:29:35.41#ibcon#about to read 4, iclass 17, count 2 2006.201.18:29:35.41#ibcon#read 4, iclass 17, count 2 2006.201.18:29:35.41#ibcon#about to read 5, iclass 17, count 2 2006.201.18:29:35.41#ibcon#read 5, iclass 17, count 2 2006.201.18:29:35.41#ibcon#about to read 6, iclass 17, count 2 2006.201.18:29:35.41#ibcon#read 6, iclass 17, count 2 2006.201.18:29:35.41#ibcon#end of sib2, iclass 17, count 2 2006.201.18:29:35.41#ibcon#*mode == 0, iclass 17, count 2 2006.201.18:29:35.41#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.18:29:35.41#ibcon#[25=AT02-07\r\n] 2006.201.18:29:35.41#ibcon#*before write, iclass 17, count 2 2006.201.18:29:35.41#ibcon#enter sib2, iclass 17, count 2 2006.201.18:29:35.41#ibcon#flushed, iclass 17, count 2 2006.201.18:29:35.41#ibcon#about to write, iclass 17, count 2 2006.201.18:29:35.41#ibcon#wrote, iclass 17, count 2 2006.201.18:29:35.41#ibcon#about to read 3, iclass 17, count 2 2006.201.18:29:35.44#ibcon#read 3, iclass 17, count 2 2006.201.18:29:35.44#ibcon#about to read 4, iclass 17, count 2 2006.201.18:29:35.44#ibcon#read 4, iclass 17, count 2 2006.201.18:29:35.44#ibcon#about to read 5, iclass 17, count 2 2006.201.18:29:35.44#ibcon#read 5, iclass 17, count 2 2006.201.18:29:35.44#ibcon#about to read 6, iclass 17, count 2 2006.201.18:29:35.44#ibcon#read 6, iclass 17, count 2 2006.201.18:29:35.44#ibcon#end of sib2, iclass 17, count 2 2006.201.18:29:35.44#ibcon#*after write, iclass 17, count 2 2006.201.18:29:35.44#ibcon#*before return 0, iclass 17, count 2 2006.201.18:29:35.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:35.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:35.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.18:29:35.44#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:35.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:35.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:35.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:35.56#ibcon#enter wrdev, iclass 17, count 0 2006.201.18:29:35.56#ibcon#first serial, iclass 17, count 0 2006.201.18:29:35.56#ibcon#enter sib2, iclass 17, count 0 2006.201.18:29:35.56#ibcon#flushed, iclass 17, count 0 2006.201.18:29:35.56#ibcon#about to write, iclass 17, count 0 2006.201.18:29:35.56#ibcon#wrote, iclass 17, count 0 2006.201.18:29:35.56#ibcon#about to read 3, iclass 17, count 0 2006.201.18:29:35.58#ibcon#read 3, iclass 17, count 0 2006.201.18:29:35.58#ibcon#about to read 4, iclass 17, count 0 2006.201.18:29:35.58#ibcon#read 4, iclass 17, count 0 2006.201.18:29:35.58#ibcon#about to read 5, iclass 17, count 0 2006.201.18:29:35.58#ibcon#read 5, iclass 17, count 0 2006.201.18:29:35.58#ibcon#about to read 6, iclass 17, count 0 2006.201.18:29:35.58#ibcon#read 6, iclass 17, count 0 2006.201.18:29:35.58#ibcon#end of sib2, iclass 17, count 0 2006.201.18:29:35.58#ibcon#*mode == 0, iclass 17, count 0 2006.201.18:29:35.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.18:29:35.58#ibcon#[25=USB\r\n] 2006.201.18:29:35.58#ibcon#*before write, iclass 17, count 0 2006.201.18:29:35.58#ibcon#enter sib2, iclass 17, count 0 2006.201.18:29:35.58#ibcon#flushed, iclass 17, count 0 2006.201.18:29:35.58#ibcon#about to write, iclass 17, count 0 2006.201.18:29:35.58#ibcon#wrote, iclass 17, count 0 2006.201.18:29:35.58#ibcon#about to read 3, iclass 17, count 0 2006.201.18:29:35.61#ibcon#read 3, iclass 17, count 0 2006.201.18:29:35.61#ibcon#about to read 4, iclass 17, count 0 2006.201.18:29:35.61#ibcon#read 4, iclass 17, count 0 2006.201.18:29:35.61#ibcon#about to read 5, iclass 17, count 0 2006.201.18:29:35.61#ibcon#read 5, iclass 17, count 0 2006.201.18:29:35.61#ibcon#about to read 6, iclass 17, count 0 2006.201.18:29:35.61#ibcon#read 6, iclass 17, count 0 2006.201.18:29:35.61#ibcon#end of sib2, iclass 17, count 0 2006.201.18:29:35.61#ibcon#*after write, iclass 17, count 0 2006.201.18:29:35.61#ibcon#*before return 0, iclass 17, count 0 2006.201.18:29:35.61#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:35.61#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:35.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.18:29:35.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.18:29:35.61$vck44/valo=3,564.99 2006.201.18:29:35.61#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.18:29:35.61#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.18:29:35.61#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:35.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:35.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:35.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:35.61#ibcon#enter wrdev, iclass 19, count 0 2006.201.18:29:35.61#ibcon#first serial, iclass 19, count 0 2006.201.18:29:35.61#ibcon#enter sib2, iclass 19, count 0 2006.201.18:29:35.61#ibcon#flushed, iclass 19, count 0 2006.201.18:29:35.61#ibcon#about to write, iclass 19, count 0 2006.201.18:29:35.61#ibcon#wrote, iclass 19, count 0 2006.201.18:29:35.61#ibcon#about to read 3, iclass 19, count 0 2006.201.18:29:35.63#ibcon#read 3, iclass 19, count 0 2006.201.18:29:35.63#ibcon#about to read 4, iclass 19, count 0 2006.201.18:29:35.63#ibcon#read 4, iclass 19, count 0 2006.201.18:29:35.63#ibcon#about to read 5, iclass 19, count 0 2006.201.18:29:35.63#ibcon#read 5, iclass 19, count 0 2006.201.18:29:35.63#ibcon#about to read 6, iclass 19, count 0 2006.201.18:29:35.63#ibcon#read 6, iclass 19, count 0 2006.201.18:29:35.63#ibcon#end of sib2, iclass 19, count 0 2006.201.18:29:35.63#ibcon#*mode == 0, iclass 19, count 0 2006.201.18:29:35.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.18:29:35.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:29:35.63#ibcon#*before write, iclass 19, count 0 2006.201.18:29:35.63#ibcon#enter sib2, iclass 19, count 0 2006.201.18:29:35.63#ibcon#flushed, iclass 19, count 0 2006.201.18:29:35.63#ibcon#about to write, iclass 19, count 0 2006.201.18:29:35.63#ibcon#wrote, iclass 19, count 0 2006.201.18:29:35.63#ibcon#about to read 3, iclass 19, count 0 2006.201.18:29:35.67#ibcon#read 3, iclass 19, count 0 2006.201.18:29:35.67#ibcon#about to read 4, iclass 19, count 0 2006.201.18:29:35.67#ibcon#read 4, iclass 19, count 0 2006.201.18:29:35.67#ibcon#about to read 5, iclass 19, count 0 2006.201.18:29:35.67#ibcon#read 5, iclass 19, count 0 2006.201.18:29:35.67#ibcon#about to read 6, iclass 19, count 0 2006.201.18:29:35.67#ibcon#read 6, iclass 19, count 0 2006.201.18:29:35.67#ibcon#end of sib2, iclass 19, count 0 2006.201.18:29:35.67#ibcon#*after write, iclass 19, count 0 2006.201.18:29:35.67#ibcon#*before return 0, iclass 19, count 0 2006.201.18:29:35.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:35.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:35.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.18:29:35.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.18:29:35.67$vck44/va=3,8 2006.201.18:29:35.67#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.18:29:35.67#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.18:29:35.67#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:35.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:35.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:35.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:35.73#ibcon#enter wrdev, iclass 21, count 2 2006.201.18:29:35.73#ibcon#first serial, iclass 21, count 2 2006.201.18:29:35.73#ibcon#enter sib2, iclass 21, count 2 2006.201.18:29:35.73#ibcon#flushed, iclass 21, count 2 2006.201.18:29:35.73#ibcon#about to write, iclass 21, count 2 2006.201.18:29:35.73#ibcon#wrote, iclass 21, count 2 2006.201.18:29:35.73#ibcon#about to read 3, iclass 21, count 2 2006.201.18:29:35.75#ibcon#read 3, iclass 21, count 2 2006.201.18:29:35.75#ibcon#about to read 4, iclass 21, count 2 2006.201.18:29:35.75#ibcon#read 4, iclass 21, count 2 2006.201.18:29:35.75#ibcon#about to read 5, iclass 21, count 2 2006.201.18:29:35.75#ibcon#read 5, iclass 21, count 2 2006.201.18:29:35.75#ibcon#about to read 6, iclass 21, count 2 2006.201.18:29:35.75#ibcon#read 6, iclass 21, count 2 2006.201.18:29:35.75#ibcon#end of sib2, iclass 21, count 2 2006.201.18:29:35.75#ibcon#*mode == 0, iclass 21, count 2 2006.201.18:29:35.75#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.18:29:35.75#ibcon#[25=AT03-08\r\n] 2006.201.18:29:35.75#ibcon#*before write, iclass 21, count 2 2006.201.18:29:35.75#ibcon#enter sib2, iclass 21, count 2 2006.201.18:29:35.75#ibcon#flushed, iclass 21, count 2 2006.201.18:29:35.75#ibcon#about to write, iclass 21, count 2 2006.201.18:29:35.75#ibcon#wrote, iclass 21, count 2 2006.201.18:29:35.75#ibcon#about to read 3, iclass 21, count 2 2006.201.18:29:35.78#ibcon#read 3, iclass 21, count 2 2006.201.18:29:35.78#ibcon#about to read 4, iclass 21, count 2 2006.201.18:29:35.78#ibcon#read 4, iclass 21, count 2 2006.201.18:29:35.78#ibcon#about to read 5, iclass 21, count 2 2006.201.18:29:35.78#ibcon#read 5, iclass 21, count 2 2006.201.18:29:35.78#ibcon#about to read 6, iclass 21, count 2 2006.201.18:29:35.78#ibcon#read 6, iclass 21, count 2 2006.201.18:29:35.78#ibcon#end of sib2, iclass 21, count 2 2006.201.18:29:35.78#ibcon#*after write, iclass 21, count 2 2006.201.18:29:35.78#ibcon#*before return 0, iclass 21, count 2 2006.201.18:29:35.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:35.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:35.78#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.18:29:35.78#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:35.78#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:35.90#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:35.90#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:35.90#ibcon#enter wrdev, iclass 21, count 0 2006.201.18:29:35.90#ibcon#first serial, iclass 21, count 0 2006.201.18:29:35.90#ibcon#enter sib2, iclass 21, count 0 2006.201.18:29:35.90#ibcon#flushed, iclass 21, count 0 2006.201.18:29:35.90#ibcon#about to write, iclass 21, count 0 2006.201.18:29:35.90#ibcon#wrote, iclass 21, count 0 2006.201.18:29:35.90#ibcon#about to read 3, iclass 21, count 0 2006.201.18:29:35.92#ibcon#read 3, iclass 21, count 0 2006.201.18:29:35.92#ibcon#about to read 4, iclass 21, count 0 2006.201.18:29:35.92#ibcon#read 4, iclass 21, count 0 2006.201.18:29:35.92#ibcon#about to read 5, iclass 21, count 0 2006.201.18:29:35.92#ibcon#read 5, iclass 21, count 0 2006.201.18:29:35.92#ibcon#about to read 6, iclass 21, count 0 2006.201.18:29:35.92#ibcon#read 6, iclass 21, count 0 2006.201.18:29:35.92#ibcon#end of sib2, iclass 21, count 0 2006.201.18:29:35.92#ibcon#*mode == 0, iclass 21, count 0 2006.201.18:29:35.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.18:29:35.92#ibcon#[25=USB\r\n] 2006.201.18:29:35.92#ibcon#*before write, iclass 21, count 0 2006.201.18:29:35.92#ibcon#enter sib2, iclass 21, count 0 2006.201.18:29:35.92#ibcon#flushed, iclass 21, count 0 2006.201.18:29:35.92#ibcon#about to write, iclass 21, count 0 2006.201.18:29:35.92#ibcon#wrote, iclass 21, count 0 2006.201.18:29:35.92#ibcon#about to read 3, iclass 21, count 0 2006.201.18:29:35.95#ibcon#read 3, iclass 21, count 0 2006.201.18:29:35.95#ibcon#about to read 4, iclass 21, count 0 2006.201.18:29:35.95#ibcon#read 4, iclass 21, count 0 2006.201.18:29:35.95#ibcon#about to read 5, iclass 21, count 0 2006.201.18:29:35.95#ibcon#read 5, iclass 21, count 0 2006.201.18:29:35.95#ibcon#about to read 6, iclass 21, count 0 2006.201.18:29:35.95#ibcon#read 6, iclass 21, count 0 2006.201.18:29:35.95#ibcon#end of sib2, iclass 21, count 0 2006.201.18:29:35.95#ibcon#*after write, iclass 21, count 0 2006.201.18:29:35.95#ibcon#*before return 0, iclass 21, count 0 2006.201.18:29:35.95#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:35.95#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:35.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.18:29:35.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.18:29:35.95$vck44/valo=4,624.99 2006.201.18:29:35.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.18:29:35.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.18:29:35.95#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:35.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:35.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:35.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:35.95#ibcon#enter wrdev, iclass 23, count 0 2006.201.18:29:35.95#ibcon#first serial, iclass 23, count 0 2006.201.18:29:35.95#ibcon#enter sib2, iclass 23, count 0 2006.201.18:29:35.95#ibcon#flushed, iclass 23, count 0 2006.201.18:29:35.95#ibcon#about to write, iclass 23, count 0 2006.201.18:29:35.95#ibcon#wrote, iclass 23, count 0 2006.201.18:29:35.95#ibcon#about to read 3, iclass 23, count 0 2006.201.18:29:35.97#ibcon#read 3, iclass 23, count 0 2006.201.18:29:35.97#ibcon#about to read 4, iclass 23, count 0 2006.201.18:29:35.97#ibcon#read 4, iclass 23, count 0 2006.201.18:29:35.97#ibcon#about to read 5, iclass 23, count 0 2006.201.18:29:35.97#ibcon#read 5, iclass 23, count 0 2006.201.18:29:35.97#ibcon#about to read 6, iclass 23, count 0 2006.201.18:29:35.97#ibcon#read 6, iclass 23, count 0 2006.201.18:29:35.97#ibcon#end of sib2, iclass 23, count 0 2006.201.18:29:35.97#ibcon#*mode == 0, iclass 23, count 0 2006.201.18:29:35.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.18:29:35.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:29:35.97#ibcon#*before write, iclass 23, count 0 2006.201.18:29:35.97#ibcon#enter sib2, iclass 23, count 0 2006.201.18:29:35.97#ibcon#flushed, iclass 23, count 0 2006.201.18:29:35.97#ibcon#about to write, iclass 23, count 0 2006.201.18:29:35.97#ibcon#wrote, iclass 23, count 0 2006.201.18:29:35.97#ibcon#about to read 3, iclass 23, count 0 2006.201.18:29:36.02#ibcon#read 3, iclass 23, count 0 2006.201.18:29:36.02#ibcon#about to read 4, iclass 23, count 0 2006.201.18:29:36.02#ibcon#read 4, iclass 23, count 0 2006.201.18:29:36.02#ibcon#about to read 5, iclass 23, count 0 2006.201.18:29:36.02#ibcon#read 5, iclass 23, count 0 2006.201.18:29:36.02#ibcon#about to read 6, iclass 23, count 0 2006.201.18:29:36.02#ibcon#read 6, iclass 23, count 0 2006.201.18:29:36.02#ibcon#end of sib2, iclass 23, count 0 2006.201.18:29:36.02#ibcon#*after write, iclass 23, count 0 2006.201.18:29:36.02#ibcon#*before return 0, iclass 23, count 0 2006.201.18:29:36.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:36.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:36.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.18:29:36.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.18:29:36.02$vck44/va=4,7 2006.201.18:29:36.02#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.18:29:36.02#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.18:29:36.02#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:36.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:36.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:36.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:36.07#ibcon#enter wrdev, iclass 25, count 2 2006.201.18:29:36.07#ibcon#first serial, iclass 25, count 2 2006.201.18:29:36.07#ibcon#enter sib2, iclass 25, count 2 2006.201.18:29:36.07#ibcon#flushed, iclass 25, count 2 2006.201.18:29:36.07#ibcon#about to write, iclass 25, count 2 2006.201.18:29:36.07#ibcon#wrote, iclass 25, count 2 2006.201.18:29:36.07#ibcon#about to read 3, iclass 25, count 2 2006.201.18:29:36.09#ibcon#read 3, iclass 25, count 2 2006.201.18:29:36.09#ibcon#about to read 4, iclass 25, count 2 2006.201.18:29:36.09#ibcon#read 4, iclass 25, count 2 2006.201.18:29:36.09#ibcon#about to read 5, iclass 25, count 2 2006.201.18:29:36.09#ibcon#read 5, iclass 25, count 2 2006.201.18:29:36.09#ibcon#about to read 6, iclass 25, count 2 2006.201.18:29:36.09#ibcon#read 6, iclass 25, count 2 2006.201.18:29:36.09#ibcon#end of sib2, iclass 25, count 2 2006.201.18:29:36.09#ibcon#*mode == 0, iclass 25, count 2 2006.201.18:29:36.09#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.18:29:36.09#ibcon#[25=AT04-07\r\n] 2006.201.18:29:36.09#ibcon#*before write, iclass 25, count 2 2006.201.18:29:36.09#ibcon#enter sib2, iclass 25, count 2 2006.201.18:29:36.09#ibcon#flushed, iclass 25, count 2 2006.201.18:29:36.09#ibcon#about to write, iclass 25, count 2 2006.201.18:29:36.09#ibcon#wrote, iclass 25, count 2 2006.201.18:29:36.09#ibcon#about to read 3, iclass 25, count 2 2006.201.18:29:36.12#ibcon#read 3, iclass 25, count 2 2006.201.18:29:36.12#ibcon#about to read 4, iclass 25, count 2 2006.201.18:29:36.12#ibcon#read 4, iclass 25, count 2 2006.201.18:29:36.12#ibcon#about to read 5, iclass 25, count 2 2006.201.18:29:36.12#ibcon#read 5, iclass 25, count 2 2006.201.18:29:36.12#ibcon#about to read 6, iclass 25, count 2 2006.201.18:29:36.12#ibcon#read 6, iclass 25, count 2 2006.201.18:29:36.12#ibcon#end of sib2, iclass 25, count 2 2006.201.18:29:36.12#ibcon#*after write, iclass 25, count 2 2006.201.18:29:36.12#ibcon#*before return 0, iclass 25, count 2 2006.201.18:29:36.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:36.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:36.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.18:29:36.12#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:36.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:36.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:36.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:36.24#ibcon#enter wrdev, iclass 25, count 0 2006.201.18:29:36.24#ibcon#first serial, iclass 25, count 0 2006.201.18:29:36.24#ibcon#enter sib2, iclass 25, count 0 2006.201.18:29:36.24#ibcon#flushed, iclass 25, count 0 2006.201.18:29:36.24#ibcon#about to write, iclass 25, count 0 2006.201.18:29:36.24#ibcon#wrote, iclass 25, count 0 2006.201.18:29:36.24#ibcon#about to read 3, iclass 25, count 0 2006.201.18:29:36.26#ibcon#read 3, iclass 25, count 0 2006.201.18:29:36.26#ibcon#about to read 4, iclass 25, count 0 2006.201.18:29:36.26#ibcon#read 4, iclass 25, count 0 2006.201.18:29:36.26#ibcon#about to read 5, iclass 25, count 0 2006.201.18:29:36.26#ibcon#read 5, iclass 25, count 0 2006.201.18:29:36.26#ibcon#about to read 6, iclass 25, count 0 2006.201.18:29:36.26#ibcon#read 6, iclass 25, count 0 2006.201.18:29:36.26#ibcon#end of sib2, iclass 25, count 0 2006.201.18:29:36.26#ibcon#*mode == 0, iclass 25, count 0 2006.201.18:29:36.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.18:29:36.26#ibcon#[25=USB\r\n] 2006.201.18:29:36.26#ibcon#*before write, iclass 25, count 0 2006.201.18:29:36.26#ibcon#enter sib2, iclass 25, count 0 2006.201.18:29:36.26#ibcon#flushed, iclass 25, count 0 2006.201.18:29:36.26#ibcon#about to write, iclass 25, count 0 2006.201.18:29:36.26#ibcon#wrote, iclass 25, count 0 2006.201.18:29:36.26#ibcon#about to read 3, iclass 25, count 0 2006.201.18:29:36.29#ibcon#read 3, iclass 25, count 0 2006.201.18:29:36.29#ibcon#about to read 4, iclass 25, count 0 2006.201.18:29:36.29#ibcon#read 4, iclass 25, count 0 2006.201.18:29:36.29#ibcon#about to read 5, iclass 25, count 0 2006.201.18:29:36.29#ibcon#read 5, iclass 25, count 0 2006.201.18:29:36.29#ibcon#about to read 6, iclass 25, count 0 2006.201.18:29:36.29#ibcon#read 6, iclass 25, count 0 2006.201.18:29:36.29#ibcon#end of sib2, iclass 25, count 0 2006.201.18:29:36.29#ibcon#*after write, iclass 25, count 0 2006.201.18:29:36.29#ibcon#*before return 0, iclass 25, count 0 2006.201.18:29:36.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:36.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:36.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.18:29:36.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.18:29:36.29$vck44/valo=5,734.99 2006.201.18:29:36.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.18:29:36.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.18:29:36.29#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:36.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:36.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:36.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:36.29#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:29:36.29#ibcon#first serial, iclass 27, count 0 2006.201.18:29:36.29#ibcon#enter sib2, iclass 27, count 0 2006.201.18:29:36.29#ibcon#flushed, iclass 27, count 0 2006.201.18:29:36.29#ibcon#about to write, iclass 27, count 0 2006.201.18:29:36.29#ibcon#wrote, iclass 27, count 0 2006.201.18:29:36.29#ibcon#about to read 3, iclass 27, count 0 2006.201.18:29:36.31#ibcon#read 3, iclass 27, count 0 2006.201.18:29:36.31#ibcon#about to read 4, iclass 27, count 0 2006.201.18:29:36.31#ibcon#read 4, iclass 27, count 0 2006.201.18:29:36.31#ibcon#about to read 5, iclass 27, count 0 2006.201.18:29:36.31#ibcon#read 5, iclass 27, count 0 2006.201.18:29:36.31#ibcon#about to read 6, iclass 27, count 0 2006.201.18:29:36.31#ibcon#read 6, iclass 27, count 0 2006.201.18:29:36.31#ibcon#end of sib2, iclass 27, count 0 2006.201.18:29:36.31#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:29:36.31#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:29:36.31#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:29:36.31#ibcon#*before write, iclass 27, count 0 2006.201.18:29:36.31#ibcon#enter sib2, iclass 27, count 0 2006.201.18:29:36.31#ibcon#flushed, iclass 27, count 0 2006.201.18:29:36.31#ibcon#about to write, iclass 27, count 0 2006.201.18:29:36.31#ibcon#wrote, iclass 27, count 0 2006.201.18:29:36.31#ibcon#about to read 3, iclass 27, count 0 2006.201.18:29:36.35#ibcon#read 3, iclass 27, count 0 2006.201.18:29:36.35#ibcon#about to read 4, iclass 27, count 0 2006.201.18:29:36.35#ibcon#read 4, iclass 27, count 0 2006.201.18:29:36.35#ibcon#about to read 5, iclass 27, count 0 2006.201.18:29:36.35#ibcon#read 5, iclass 27, count 0 2006.201.18:29:36.35#ibcon#about to read 6, iclass 27, count 0 2006.201.18:29:36.35#ibcon#read 6, iclass 27, count 0 2006.201.18:29:36.35#ibcon#end of sib2, iclass 27, count 0 2006.201.18:29:36.35#ibcon#*after write, iclass 27, count 0 2006.201.18:29:36.35#ibcon#*before return 0, iclass 27, count 0 2006.201.18:29:36.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:36.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:36.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:29:36.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:29:36.35$vck44/va=5,4 2006.201.18:29:36.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.18:29:36.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.18:29:36.35#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:36.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:36.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:36.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:36.41#ibcon#enter wrdev, iclass 29, count 2 2006.201.18:29:36.41#ibcon#first serial, iclass 29, count 2 2006.201.18:29:36.41#ibcon#enter sib2, iclass 29, count 2 2006.201.18:29:36.41#ibcon#flushed, iclass 29, count 2 2006.201.18:29:36.41#ibcon#about to write, iclass 29, count 2 2006.201.18:29:36.41#ibcon#wrote, iclass 29, count 2 2006.201.18:29:36.41#ibcon#about to read 3, iclass 29, count 2 2006.201.18:29:36.43#ibcon#read 3, iclass 29, count 2 2006.201.18:29:36.43#ibcon#about to read 4, iclass 29, count 2 2006.201.18:29:36.43#ibcon#read 4, iclass 29, count 2 2006.201.18:29:36.43#ibcon#about to read 5, iclass 29, count 2 2006.201.18:29:36.43#ibcon#read 5, iclass 29, count 2 2006.201.18:29:36.43#ibcon#about to read 6, iclass 29, count 2 2006.201.18:29:36.43#ibcon#read 6, iclass 29, count 2 2006.201.18:29:36.43#ibcon#end of sib2, iclass 29, count 2 2006.201.18:29:36.43#ibcon#*mode == 0, iclass 29, count 2 2006.201.18:29:36.43#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.18:29:36.43#ibcon#[25=AT05-04\r\n] 2006.201.18:29:36.43#ibcon#*before write, iclass 29, count 2 2006.201.18:29:36.43#ibcon#enter sib2, iclass 29, count 2 2006.201.18:29:36.43#ibcon#flushed, iclass 29, count 2 2006.201.18:29:36.43#ibcon#about to write, iclass 29, count 2 2006.201.18:29:36.43#ibcon#wrote, iclass 29, count 2 2006.201.18:29:36.43#ibcon#about to read 3, iclass 29, count 2 2006.201.18:29:36.46#ibcon#read 3, iclass 29, count 2 2006.201.18:29:36.46#ibcon#about to read 4, iclass 29, count 2 2006.201.18:29:36.46#ibcon#read 4, iclass 29, count 2 2006.201.18:29:36.46#ibcon#about to read 5, iclass 29, count 2 2006.201.18:29:36.46#ibcon#read 5, iclass 29, count 2 2006.201.18:29:36.46#ibcon#about to read 6, iclass 29, count 2 2006.201.18:29:36.46#ibcon#read 6, iclass 29, count 2 2006.201.18:29:36.46#ibcon#end of sib2, iclass 29, count 2 2006.201.18:29:36.46#ibcon#*after write, iclass 29, count 2 2006.201.18:29:36.46#ibcon#*before return 0, iclass 29, count 2 2006.201.18:29:36.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:36.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:36.46#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.18:29:36.46#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:36.46#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:36.58#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:36.58#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:36.58#ibcon#enter wrdev, iclass 29, count 0 2006.201.18:29:36.58#ibcon#first serial, iclass 29, count 0 2006.201.18:29:36.58#ibcon#enter sib2, iclass 29, count 0 2006.201.18:29:36.58#ibcon#flushed, iclass 29, count 0 2006.201.18:29:36.58#ibcon#about to write, iclass 29, count 0 2006.201.18:29:36.58#ibcon#wrote, iclass 29, count 0 2006.201.18:29:36.58#ibcon#about to read 3, iclass 29, count 0 2006.201.18:29:36.60#ibcon#read 3, iclass 29, count 0 2006.201.18:29:36.60#ibcon#about to read 4, iclass 29, count 0 2006.201.18:29:36.60#ibcon#read 4, iclass 29, count 0 2006.201.18:29:36.60#ibcon#about to read 5, iclass 29, count 0 2006.201.18:29:36.60#ibcon#read 5, iclass 29, count 0 2006.201.18:29:36.60#ibcon#about to read 6, iclass 29, count 0 2006.201.18:29:36.60#ibcon#read 6, iclass 29, count 0 2006.201.18:29:36.60#ibcon#end of sib2, iclass 29, count 0 2006.201.18:29:36.60#ibcon#*mode == 0, iclass 29, count 0 2006.201.18:29:36.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.18:29:36.60#ibcon#[25=USB\r\n] 2006.201.18:29:36.60#ibcon#*before write, iclass 29, count 0 2006.201.18:29:36.60#ibcon#enter sib2, iclass 29, count 0 2006.201.18:29:36.60#ibcon#flushed, iclass 29, count 0 2006.201.18:29:36.60#ibcon#about to write, iclass 29, count 0 2006.201.18:29:36.60#ibcon#wrote, iclass 29, count 0 2006.201.18:29:36.60#ibcon#about to read 3, iclass 29, count 0 2006.201.18:29:36.63#ibcon#read 3, iclass 29, count 0 2006.201.18:29:36.63#ibcon#about to read 4, iclass 29, count 0 2006.201.18:29:36.63#ibcon#read 4, iclass 29, count 0 2006.201.18:29:36.63#ibcon#about to read 5, iclass 29, count 0 2006.201.18:29:36.63#ibcon#read 5, iclass 29, count 0 2006.201.18:29:36.63#ibcon#about to read 6, iclass 29, count 0 2006.201.18:29:36.63#ibcon#read 6, iclass 29, count 0 2006.201.18:29:36.63#ibcon#end of sib2, iclass 29, count 0 2006.201.18:29:36.63#ibcon#*after write, iclass 29, count 0 2006.201.18:29:36.63#ibcon#*before return 0, iclass 29, count 0 2006.201.18:29:36.63#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:36.63#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:36.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.18:29:36.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.18:29:36.63$vck44/valo=6,814.99 2006.201.18:29:36.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.18:29:36.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.18:29:36.63#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:36.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:36.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:36.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:36.63#ibcon#enter wrdev, iclass 31, count 0 2006.201.18:29:36.63#ibcon#first serial, iclass 31, count 0 2006.201.18:29:36.63#ibcon#enter sib2, iclass 31, count 0 2006.201.18:29:36.63#ibcon#flushed, iclass 31, count 0 2006.201.18:29:36.63#ibcon#about to write, iclass 31, count 0 2006.201.18:29:36.63#ibcon#wrote, iclass 31, count 0 2006.201.18:29:36.63#ibcon#about to read 3, iclass 31, count 0 2006.201.18:29:36.65#ibcon#read 3, iclass 31, count 0 2006.201.18:29:36.65#ibcon#about to read 4, iclass 31, count 0 2006.201.18:29:36.65#ibcon#read 4, iclass 31, count 0 2006.201.18:29:36.65#ibcon#about to read 5, iclass 31, count 0 2006.201.18:29:36.65#ibcon#read 5, iclass 31, count 0 2006.201.18:29:36.65#ibcon#about to read 6, iclass 31, count 0 2006.201.18:29:36.65#ibcon#read 6, iclass 31, count 0 2006.201.18:29:36.65#ibcon#end of sib2, iclass 31, count 0 2006.201.18:29:36.65#ibcon#*mode == 0, iclass 31, count 0 2006.201.18:29:36.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.18:29:36.65#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:29:36.65#ibcon#*before write, iclass 31, count 0 2006.201.18:29:36.65#ibcon#enter sib2, iclass 31, count 0 2006.201.18:29:36.65#ibcon#flushed, iclass 31, count 0 2006.201.18:29:36.65#ibcon#about to write, iclass 31, count 0 2006.201.18:29:36.65#ibcon#wrote, iclass 31, count 0 2006.201.18:29:36.65#ibcon#about to read 3, iclass 31, count 0 2006.201.18:29:36.69#ibcon#read 3, iclass 31, count 0 2006.201.18:29:36.69#ibcon#about to read 4, iclass 31, count 0 2006.201.18:29:36.69#ibcon#read 4, iclass 31, count 0 2006.201.18:29:36.69#ibcon#about to read 5, iclass 31, count 0 2006.201.18:29:36.69#ibcon#read 5, iclass 31, count 0 2006.201.18:29:36.69#ibcon#about to read 6, iclass 31, count 0 2006.201.18:29:36.69#ibcon#read 6, iclass 31, count 0 2006.201.18:29:36.69#ibcon#end of sib2, iclass 31, count 0 2006.201.18:29:36.69#ibcon#*after write, iclass 31, count 0 2006.201.18:29:36.69#ibcon#*before return 0, iclass 31, count 0 2006.201.18:29:36.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:36.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:36.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.18:29:36.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.18:29:36.69$vck44/va=6,5 2006.201.18:29:36.69#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.18:29:36.69#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.18:29:36.69#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:36.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:36.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:36.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:36.75#ibcon#enter wrdev, iclass 33, count 2 2006.201.18:29:36.75#ibcon#first serial, iclass 33, count 2 2006.201.18:29:36.75#ibcon#enter sib2, iclass 33, count 2 2006.201.18:29:36.75#ibcon#flushed, iclass 33, count 2 2006.201.18:29:36.75#ibcon#about to write, iclass 33, count 2 2006.201.18:29:36.75#ibcon#wrote, iclass 33, count 2 2006.201.18:29:36.75#ibcon#about to read 3, iclass 33, count 2 2006.201.18:29:36.77#ibcon#read 3, iclass 33, count 2 2006.201.18:29:36.77#ibcon#about to read 4, iclass 33, count 2 2006.201.18:29:36.77#ibcon#read 4, iclass 33, count 2 2006.201.18:29:36.77#ibcon#about to read 5, iclass 33, count 2 2006.201.18:29:36.77#ibcon#read 5, iclass 33, count 2 2006.201.18:29:36.77#ibcon#about to read 6, iclass 33, count 2 2006.201.18:29:36.77#ibcon#read 6, iclass 33, count 2 2006.201.18:29:36.77#ibcon#end of sib2, iclass 33, count 2 2006.201.18:29:36.77#ibcon#*mode == 0, iclass 33, count 2 2006.201.18:29:36.77#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.18:29:36.77#ibcon#[25=AT06-05\r\n] 2006.201.18:29:36.77#ibcon#*before write, iclass 33, count 2 2006.201.18:29:36.77#ibcon#enter sib2, iclass 33, count 2 2006.201.18:29:36.77#ibcon#flushed, iclass 33, count 2 2006.201.18:29:36.77#ibcon#about to write, iclass 33, count 2 2006.201.18:29:36.77#ibcon#wrote, iclass 33, count 2 2006.201.18:29:36.77#ibcon#about to read 3, iclass 33, count 2 2006.201.18:29:36.80#ibcon#read 3, iclass 33, count 2 2006.201.18:29:36.80#ibcon#about to read 4, iclass 33, count 2 2006.201.18:29:36.80#ibcon#read 4, iclass 33, count 2 2006.201.18:29:36.80#ibcon#about to read 5, iclass 33, count 2 2006.201.18:29:36.80#ibcon#read 5, iclass 33, count 2 2006.201.18:29:36.80#ibcon#about to read 6, iclass 33, count 2 2006.201.18:29:36.80#ibcon#read 6, iclass 33, count 2 2006.201.18:29:36.80#ibcon#end of sib2, iclass 33, count 2 2006.201.18:29:36.80#ibcon#*after write, iclass 33, count 2 2006.201.18:29:36.80#ibcon#*before return 0, iclass 33, count 2 2006.201.18:29:36.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:36.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:36.80#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.18:29:36.80#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:36.80#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:36.92#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:36.92#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:36.92#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:29:36.92#ibcon#first serial, iclass 33, count 0 2006.201.18:29:36.92#ibcon#enter sib2, iclass 33, count 0 2006.201.18:29:36.92#ibcon#flushed, iclass 33, count 0 2006.201.18:29:36.92#ibcon#about to write, iclass 33, count 0 2006.201.18:29:36.92#ibcon#wrote, iclass 33, count 0 2006.201.18:29:36.92#ibcon#about to read 3, iclass 33, count 0 2006.201.18:29:36.94#ibcon#read 3, iclass 33, count 0 2006.201.18:29:36.94#ibcon#about to read 4, iclass 33, count 0 2006.201.18:29:36.94#ibcon#read 4, iclass 33, count 0 2006.201.18:29:36.94#ibcon#about to read 5, iclass 33, count 0 2006.201.18:29:36.94#ibcon#read 5, iclass 33, count 0 2006.201.18:29:36.94#ibcon#about to read 6, iclass 33, count 0 2006.201.18:29:36.94#ibcon#read 6, iclass 33, count 0 2006.201.18:29:36.94#ibcon#end of sib2, iclass 33, count 0 2006.201.18:29:36.94#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:29:36.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:29:36.94#ibcon#[25=USB\r\n] 2006.201.18:29:36.94#ibcon#*before write, iclass 33, count 0 2006.201.18:29:36.94#ibcon#enter sib2, iclass 33, count 0 2006.201.18:29:36.94#ibcon#flushed, iclass 33, count 0 2006.201.18:29:36.94#ibcon#about to write, iclass 33, count 0 2006.201.18:29:36.94#ibcon#wrote, iclass 33, count 0 2006.201.18:29:36.94#ibcon#about to read 3, iclass 33, count 0 2006.201.18:29:36.97#ibcon#read 3, iclass 33, count 0 2006.201.18:29:36.97#ibcon#about to read 4, iclass 33, count 0 2006.201.18:29:36.97#ibcon#read 4, iclass 33, count 0 2006.201.18:29:36.97#ibcon#about to read 5, iclass 33, count 0 2006.201.18:29:36.97#ibcon#read 5, iclass 33, count 0 2006.201.18:29:36.97#ibcon#about to read 6, iclass 33, count 0 2006.201.18:29:36.97#ibcon#read 6, iclass 33, count 0 2006.201.18:29:36.97#ibcon#end of sib2, iclass 33, count 0 2006.201.18:29:36.97#ibcon#*after write, iclass 33, count 0 2006.201.18:29:36.97#ibcon#*before return 0, iclass 33, count 0 2006.201.18:29:36.97#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:36.97#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:36.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:29:36.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:29:36.97$vck44/valo=7,864.99 2006.201.18:29:36.97#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.18:29:36.97#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.18:29:36.97#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:36.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:36.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:36.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:36.97#ibcon#enter wrdev, iclass 35, count 0 2006.201.18:29:36.97#ibcon#first serial, iclass 35, count 0 2006.201.18:29:36.97#ibcon#enter sib2, iclass 35, count 0 2006.201.18:29:36.97#ibcon#flushed, iclass 35, count 0 2006.201.18:29:36.97#ibcon#about to write, iclass 35, count 0 2006.201.18:29:36.97#ibcon#wrote, iclass 35, count 0 2006.201.18:29:36.97#ibcon#about to read 3, iclass 35, count 0 2006.201.18:29:36.99#ibcon#read 3, iclass 35, count 0 2006.201.18:29:36.99#ibcon#about to read 4, iclass 35, count 0 2006.201.18:29:36.99#ibcon#read 4, iclass 35, count 0 2006.201.18:29:36.99#ibcon#about to read 5, iclass 35, count 0 2006.201.18:29:36.99#ibcon#read 5, iclass 35, count 0 2006.201.18:29:36.99#ibcon#about to read 6, iclass 35, count 0 2006.201.18:29:36.99#ibcon#read 6, iclass 35, count 0 2006.201.18:29:36.99#ibcon#end of sib2, iclass 35, count 0 2006.201.18:29:36.99#ibcon#*mode == 0, iclass 35, count 0 2006.201.18:29:36.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.18:29:36.99#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:29:36.99#ibcon#*before write, iclass 35, count 0 2006.201.18:29:36.99#ibcon#enter sib2, iclass 35, count 0 2006.201.18:29:36.99#ibcon#flushed, iclass 35, count 0 2006.201.18:29:36.99#ibcon#about to write, iclass 35, count 0 2006.201.18:29:36.99#ibcon#wrote, iclass 35, count 0 2006.201.18:29:36.99#ibcon#about to read 3, iclass 35, count 0 2006.201.18:29:37.03#ibcon#read 3, iclass 35, count 0 2006.201.18:29:37.03#ibcon#about to read 4, iclass 35, count 0 2006.201.18:29:37.03#ibcon#read 4, iclass 35, count 0 2006.201.18:29:37.03#ibcon#about to read 5, iclass 35, count 0 2006.201.18:29:37.03#ibcon#read 5, iclass 35, count 0 2006.201.18:29:37.03#ibcon#about to read 6, iclass 35, count 0 2006.201.18:29:37.03#ibcon#read 6, iclass 35, count 0 2006.201.18:29:37.03#ibcon#end of sib2, iclass 35, count 0 2006.201.18:29:37.03#ibcon#*after write, iclass 35, count 0 2006.201.18:29:37.03#ibcon#*before return 0, iclass 35, count 0 2006.201.18:29:37.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:37.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:37.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.18:29:37.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.18:29:37.03$vck44/va=7,5 2006.201.18:29:37.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.18:29:37.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.18:29:37.03#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:37.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:37.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:37.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:37.09#ibcon#enter wrdev, iclass 37, count 2 2006.201.18:29:37.09#ibcon#first serial, iclass 37, count 2 2006.201.18:29:37.09#ibcon#enter sib2, iclass 37, count 2 2006.201.18:29:37.09#ibcon#flushed, iclass 37, count 2 2006.201.18:29:37.09#ibcon#about to write, iclass 37, count 2 2006.201.18:29:37.09#ibcon#wrote, iclass 37, count 2 2006.201.18:29:37.09#ibcon#about to read 3, iclass 37, count 2 2006.201.18:29:37.11#ibcon#read 3, iclass 37, count 2 2006.201.18:29:37.11#ibcon#about to read 4, iclass 37, count 2 2006.201.18:29:37.11#ibcon#read 4, iclass 37, count 2 2006.201.18:29:37.11#ibcon#about to read 5, iclass 37, count 2 2006.201.18:29:37.11#ibcon#read 5, iclass 37, count 2 2006.201.18:29:37.11#ibcon#about to read 6, iclass 37, count 2 2006.201.18:29:37.11#ibcon#read 6, iclass 37, count 2 2006.201.18:29:37.11#ibcon#end of sib2, iclass 37, count 2 2006.201.18:29:37.11#ibcon#*mode == 0, iclass 37, count 2 2006.201.18:29:37.11#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.18:29:37.11#ibcon#[25=AT07-05\r\n] 2006.201.18:29:37.11#ibcon#*before write, iclass 37, count 2 2006.201.18:29:37.11#ibcon#enter sib2, iclass 37, count 2 2006.201.18:29:37.11#ibcon#flushed, iclass 37, count 2 2006.201.18:29:37.11#ibcon#about to write, iclass 37, count 2 2006.201.18:29:37.11#ibcon#wrote, iclass 37, count 2 2006.201.18:29:37.11#ibcon#about to read 3, iclass 37, count 2 2006.201.18:29:37.14#ibcon#read 3, iclass 37, count 2 2006.201.18:29:37.14#ibcon#about to read 4, iclass 37, count 2 2006.201.18:29:37.14#ibcon#read 4, iclass 37, count 2 2006.201.18:29:37.14#ibcon#about to read 5, iclass 37, count 2 2006.201.18:29:37.14#ibcon#read 5, iclass 37, count 2 2006.201.18:29:37.14#ibcon#about to read 6, iclass 37, count 2 2006.201.18:29:37.14#ibcon#read 6, iclass 37, count 2 2006.201.18:29:37.14#ibcon#end of sib2, iclass 37, count 2 2006.201.18:29:37.14#ibcon#*after write, iclass 37, count 2 2006.201.18:29:37.14#ibcon#*before return 0, iclass 37, count 2 2006.201.18:29:37.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:37.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:37.14#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.18:29:37.14#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:37.14#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:37.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:37.26#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:37.26#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:29:37.26#ibcon#first serial, iclass 37, count 0 2006.201.18:29:37.26#ibcon#enter sib2, iclass 37, count 0 2006.201.18:29:37.26#ibcon#flushed, iclass 37, count 0 2006.201.18:29:37.26#ibcon#about to write, iclass 37, count 0 2006.201.18:29:37.26#ibcon#wrote, iclass 37, count 0 2006.201.18:29:37.26#ibcon#about to read 3, iclass 37, count 0 2006.201.18:29:37.28#ibcon#read 3, iclass 37, count 0 2006.201.18:29:37.28#ibcon#about to read 4, iclass 37, count 0 2006.201.18:29:37.28#ibcon#read 4, iclass 37, count 0 2006.201.18:29:37.28#ibcon#about to read 5, iclass 37, count 0 2006.201.18:29:37.28#ibcon#read 5, iclass 37, count 0 2006.201.18:29:37.28#ibcon#about to read 6, iclass 37, count 0 2006.201.18:29:37.28#ibcon#read 6, iclass 37, count 0 2006.201.18:29:37.28#ibcon#end of sib2, iclass 37, count 0 2006.201.18:29:37.28#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:29:37.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:29:37.28#ibcon#[25=USB\r\n] 2006.201.18:29:37.28#ibcon#*before write, iclass 37, count 0 2006.201.18:29:37.28#ibcon#enter sib2, iclass 37, count 0 2006.201.18:29:37.28#ibcon#flushed, iclass 37, count 0 2006.201.18:29:37.28#ibcon#about to write, iclass 37, count 0 2006.201.18:29:37.28#ibcon#wrote, iclass 37, count 0 2006.201.18:29:37.28#ibcon#about to read 3, iclass 37, count 0 2006.201.18:29:37.31#ibcon#read 3, iclass 37, count 0 2006.201.18:29:37.31#ibcon#about to read 4, iclass 37, count 0 2006.201.18:29:37.31#ibcon#read 4, iclass 37, count 0 2006.201.18:29:37.31#ibcon#about to read 5, iclass 37, count 0 2006.201.18:29:37.31#ibcon#read 5, iclass 37, count 0 2006.201.18:29:37.31#ibcon#about to read 6, iclass 37, count 0 2006.201.18:29:37.31#ibcon#read 6, iclass 37, count 0 2006.201.18:29:37.31#ibcon#end of sib2, iclass 37, count 0 2006.201.18:29:37.31#ibcon#*after write, iclass 37, count 0 2006.201.18:29:37.31#ibcon#*before return 0, iclass 37, count 0 2006.201.18:29:37.31#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:37.31#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:37.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:29:37.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:29:37.31$vck44/valo=8,884.99 2006.201.18:29:37.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.18:29:37.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.18:29:37.31#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:37.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:37.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:37.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:37.31#ibcon#enter wrdev, iclass 39, count 0 2006.201.18:29:37.31#ibcon#first serial, iclass 39, count 0 2006.201.18:29:37.31#ibcon#enter sib2, iclass 39, count 0 2006.201.18:29:37.31#ibcon#flushed, iclass 39, count 0 2006.201.18:29:37.31#ibcon#about to write, iclass 39, count 0 2006.201.18:29:37.31#ibcon#wrote, iclass 39, count 0 2006.201.18:29:37.31#ibcon#about to read 3, iclass 39, count 0 2006.201.18:29:37.33#ibcon#read 3, iclass 39, count 0 2006.201.18:29:37.33#ibcon#about to read 4, iclass 39, count 0 2006.201.18:29:37.33#ibcon#read 4, iclass 39, count 0 2006.201.18:29:37.33#ibcon#about to read 5, iclass 39, count 0 2006.201.18:29:37.33#ibcon#read 5, iclass 39, count 0 2006.201.18:29:37.33#ibcon#about to read 6, iclass 39, count 0 2006.201.18:29:37.33#ibcon#read 6, iclass 39, count 0 2006.201.18:29:37.33#ibcon#end of sib2, iclass 39, count 0 2006.201.18:29:37.33#ibcon#*mode == 0, iclass 39, count 0 2006.201.18:29:37.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.18:29:37.33#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:29:37.33#ibcon#*before write, iclass 39, count 0 2006.201.18:29:37.33#ibcon#enter sib2, iclass 39, count 0 2006.201.18:29:37.33#ibcon#flushed, iclass 39, count 0 2006.201.18:29:37.33#ibcon#about to write, iclass 39, count 0 2006.201.18:29:37.33#ibcon#wrote, iclass 39, count 0 2006.201.18:29:37.33#ibcon#about to read 3, iclass 39, count 0 2006.201.18:29:37.37#ibcon#read 3, iclass 39, count 0 2006.201.18:29:37.37#ibcon#about to read 4, iclass 39, count 0 2006.201.18:29:37.37#ibcon#read 4, iclass 39, count 0 2006.201.18:29:37.37#ibcon#about to read 5, iclass 39, count 0 2006.201.18:29:37.37#ibcon#read 5, iclass 39, count 0 2006.201.18:29:37.37#ibcon#about to read 6, iclass 39, count 0 2006.201.18:29:37.37#ibcon#read 6, iclass 39, count 0 2006.201.18:29:37.37#ibcon#end of sib2, iclass 39, count 0 2006.201.18:29:37.37#ibcon#*after write, iclass 39, count 0 2006.201.18:29:37.37#ibcon#*before return 0, iclass 39, count 0 2006.201.18:29:37.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:37.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:37.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.18:29:37.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.18:29:37.37$vck44/va=8,4 2006.201.18:29:37.37#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.18:29:37.37#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.18:29:37.37#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:37.37#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:29:37.43#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:29:37.43#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:29:37.43#ibcon#enter wrdev, iclass 2, count 2 2006.201.18:29:37.43#ibcon#first serial, iclass 2, count 2 2006.201.18:29:37.43#ibcon#enter sib2, iclass 2, count 2 2006.201.18:29:37.43#ibcon#flushed, iclass 2, count 2 2006.201.18:29:37.43#ibcon#about to write, iclass 2, count 2 2006.201.18:29:37.43#ibcon#wrote, iclass 2, count 2 2006.201.18:29:37.43#ibcon#about to read 3, iclass 2, count 2 2006.201.18:29:37.45#ibcon#read 3, iclass 2, count 2 2006.201.18:29:37.45#ibcon#about to read 4, iclass 2, count 2 2006.201.18:29:37.45#ibcon#read 4, iclass 2, count 2 2006.201.18:29:37.45#ibcon#about to read 5, iclass 2, count 2 2006.201.18:29:37.45#ibcon#read 5, iclass 2, count 2 2006.201.18:29:37.45#ibcon#about to read 6, iclass 2, count 2 2006.201.18:29:37.45#ibcon#read 6, iclass 2, count 2 2006.201.18:29:37.45#ibcon#end of sib2, iclass 2, count 2 2006.201.18:29:37.45#ibcon#*mode == 0, iclass 2, count 2 2006.201.18:29:37.45#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.18:29:37.45#ibcon#[25=AT08-04\r\n] 2006.201.18:29:37.45#ibcon#*before write, iclass 2, count 2 2006.201.18:29:37.45#ibcon#enter sib2, iclass 2, count 2 2006.201.18:29:37.45#ibcon#flushed, iclass 2, count 2 2006.201.18:29:37.45#ibcon#about to write, iclass 2, count 2 2006.201.18:29:37.45#ibcon#wrote, iclass 2, count 2 2006.201.18:29:37.45#ibcon#about to read 3, iclass 2, count 2 2006.201.18:29:37.48#ibcon#read 3, iclass 2, count 2 2006.201.18:29:37.48#ibcon#about to read 4, iclass 2, count 2 2006.201.18:29:37.48#ibcon#read 4, iclass 2, count 2 2006.201.18:29:37.48#ibcon#about to read 5, iclass 2, count 2 2006.201.18:29:37.48#ibcon#read 5, iclass 2, count 2 2006.201.18:29:37.48#ibcon#about to read 6, iclass 2, count 2 2006.201.18:29:37.48#ibcon#read 6, iclass 2, count 2 2006.201.18:29:37.48#ibcon#end of sib2, iclass 2, count 2 2006.201.18:29:37.48#ibcon#*after write, iclass 2, count 2 2006.201.18:29:37.48#ibcon#*before return 0, iclass 2, count 2 2006.201.18:29:37.48#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:29:37.48#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:29:37.48#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.18:29:37.48#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:37.48#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:29:37.60#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:29:37.60#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:29:37.60#ibcon#enter wrdev, iclass 2, count 0 2006.201.18:29:37.60#ibcon#first serial, iclass 2, count 0 2006.201.18:29:37.60#ibcon#enter sib2, iclass 2, count 0 2006.201.18:29:37.60#ibcon#flushed, iclass 2, count 0 2006.201.18:29:37.60#ibcon#about to write, iclass 2, count 0 2006.201.18:29:37.60#ibcon#wrote, iclass 2, count 0 2006.201.18:29:37.60#ibcon#about to read 3, iclass 2, count 0 2006.201.18:29:37.62#ibcon#read 3, iclass 2, count 0 2006.201.18:29:37.62#ibcon#about to read 4, iclass 2, count 0 2006.201.18:29:37.62#ibcon#read 4, iclass 2, count 0 2006.201.18:29:37.62#ibcon#about to read 5, iclass 2, count 0 2006.201.18:29:37.62#ibcon#read 5, iclass 2, count 0 2006.201.18:29:37.62#ibcon#about to read 6, iclass 2, count 0 2006.201.18:29:37.62#ibcon#read 6, iclass 2, count 0 2006.201.18:29:37.62#ibcon#end of sib2, iclass 2, count 0 2006.201.18:29:37.62#ibcon#*mode == 0, iclass 2, count 0 2006.201.18:29:37.62#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.18:29:37.62#ibcon#[25=USB\r\n] 2006.201.18:29:37.62#ibcon#*before write, iclass 2, count 0 2006.201.18:29:37.62#ibcon#enter sib2, iclass 2, count 0 2006.201.18:29:37.62#ibcon#flushed, iclass 2, count 0 2006.201.18:29:37.62#ibcon#about to write, iclass 2, count 0 2006.201.18:29:37.62#ibcon#wrote, iclass 2, count 0 2006.201.18:29:37.62#ibcon#about to read 3, iclass 2, count 0 2006.201.18:29:37.65#ibcon#read 3, iclass 2, count 0 2006.201.18:29:37.65#ibcon#about to read 4, iclass 2, count 0 2006.201.18:29:37.65#ibcon#read 4, iclass 2, count 0 2006.201.18:29:37.65#ibcon#about to read 5, iclass 2, count 0 2006.201.18:29:37.65#ibcon#read 5, iclass 2, count 0 2006.201.18:29:37.65#ibcon#about to read 6, iclass 2, count 0 2006.201.18:29:37.65#ibcon#read 6, iclass 2, count 0 2006.201.18:29:37.65#ibcon#end of sib2, iclass 2, count 0 2006.201.18:29:37.65#ibcon#*after write, iclass 2, count 0 2006.201.18:29:37.65#ibcon#*before return 0, iclass 2, count 0 2006.201.18:29:37.65#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:29:37.65#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:29:37.65#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.18:29:37.65#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.18:29:37.65$vck44/vblo=1,629.99 2006.201.18:29:37.65#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.18:29:37.65#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.18:29:37.65#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:37.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:29:37.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:29:37.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:29:37.65#ibcon#enter wrdev, iclass 5, count 0 2006.201.18:29:37.65#ibcon#first serial, iclass 5, count 0 2006.201.18:29:37.65#ibcon#enter sib2, iclass 5, count 0 2006.201.18:29:37.65#ibcon#flushed, iclass 5, count 0 2006.201.18:29:37.65#ibcon#about to write, iclass 5, count 0 2006.201.18:29:37.65#ibcon#wrote, iclass 5, count 0 2006.201.18:29:37.65#ibcon#about to read 3, iclass 5, count 0 2006.201.18:29:37.67#ibcon#read 3, iclass 5, count 0 2006.201.18:29:37.67#ibcon#about to read 4, iclass 5, count 0 2006.201.18:29:37.67#ibcon#read 4, iclass 5, count 0 2006.201.18:29:37.67#ibcon#about to read 5, iclass 5, count 0 2006.201.18:29:37.67#ibcon#read 5, iclass 5, count 0 2006.201.18:29:37.67#ibcon#about to read 6, iclass 5, count 0 2006.201.18:29:37.67#ibcon#read 6, iclass 5, count 0 2006.201.18:29:37.67#ibcon#end of sib2, iclass 5, count 0 2006.201.18:29:37.67#ibcon#*mode == 0, iclass 5, count 0 2006.201.18:29:37.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.18:29:37.67#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:29:37.67#ibcon#*before write, iclass 5, count 0 2006.201.18:29:37.67#ibcon#enter sib2, iclass 5, count 0 2006.201.18:29:37.67#ibcon#flushed, iclass 5, count 0 2006.201.18:29:37.67#ibcon#about to write, iclass 5, count 0 2006.201.18:29:37.67#ibcon#wrote, iclass 5, count 0 2006.201.18:29:37.67#ibcon#about to read 3, iclass 5, count 0 2006.201.18:29:37.72#ibcon#read 3, iclass 5, count 0 2006.201.18:29:37.72#ibcon#about to read 4, iclass 5, count 0 2006.201.18:29:37.72#ibcon#read 4, iclass 5, count 0 2006.201.18:29:37.72#ibcon#about to read 5, iclass 5, count 0 2006.201.18:29:37.72#ibcon#read 5, iclass 5, count 0 2006.201.18:29:37.72#ibcon#about to read 6, iclass 5, count 0 2006.201.18:29:37.72#ibcon#read 6, iclass 5, count 0 2006.201.18:29:37.72#ibcon#end of sib2, iclass 5, count 0 2006.201.18:29:37.72#ibcon#*after write, iclass 5, count 0 2006.201.18:29:37.72#ibcon#*before return 0, iclass 5, count 0 2006.201.18:29:37.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:29:37.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:29:37.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.18:29:37.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.18:29:37.72$vck44/vb=1,4 2006.201.18:29:37.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.18:29:37.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.18:29:37.72#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:37.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:29:37.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:29:37.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:29:37.72#ibcon#enter wrdev, iclass 7, count 2 2006.201.18:29:37.72#ibcon#first serial, iclass 7, count 2 2006.201.18:29:37.72#ibcon#enter sib2, iclass 7, count 2 2006.201.18:29:37.72#ibcon#flushed, iclass 7, count 2 2006.201.18:29:37.72#ibcon#about to write, iclass 7, count 2 2006.201.18:29:37.72#ibcon#wrote, iclass 7, count 2 2006.201.18:29:37.72#ibcon#about to read 3, iclass 7, count 2 2006.201.18:29:37.74#ibcon#read 3, iclass 7, count 2 2006.201.18:29:37.74#ibcon#about to read 4, iclass 7, count 2 2006.201.18:29:37.74#ibcon#read 4, iclass 7, count 2 2006.201.18:29:37.74#ibcon#about to read 5, iclass 7, count 2 2006.201.18:29:37.74#ibcon#read 5, iclass 7, count 2 2006.201.18:29:37.74#ibcon#about to read 6, iclass 7, count 2 2006.201.18:29:37.74#ibcon#read 6, iclass 7, count 2 2006.201.18:29:37.74#ibcon#end of sib2, iclass 7, count 2 2006.201.18:29:37.74#ibcon#*mode == 0, iclass 7, count 2 2006.201.18:29:37.74#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.18:29:37.74#ibcon#[27=AT01-04\r\n] 2006.201.18:29:37.74#ibcon#*before write, iclass 7, count 2 2006.201.18:29:37.74#ibcon#enter sib2, iclass 7, count 2 2006.201.18:29:37.74#ibcon#flushed, iclass 7, count 2 2006.201.18:29:37.74#ibcon#about to write, iclass 7, count 2 2006.201.18:29:37.74#ibcon#wrote, iclass 7, count 2 2006.201.18:29:37.74#ibcon#about to read 3, iclass 7, count 2 2006.201.18:29:37.77#ibcon#read 3, iclass 7, count 2 2006.201.18:29:37.77#ibcon#about to read 4, iclass 7, count 2 2006.201.18:29:37.77#ibcon#read 4, iclass 7, count 2 2006.201.18:29:37.77#ibcon#about to read 5, iclass 7, count 2 2006.201.18:29:37.77#ibcon#read 5, iclass 7, count 2 2006.201.18:29:37.77#ibcon#about to read 6, iclass 7, count 2 2006.201.18:29:37.77#ibcon#read 6, iclass 7, count 2 2006.201.18:29:37.77#ibcon#end of sib2, iclass 7, count 2 2006.201.18:29:37.77#ibcon#*after write, iclass 7, count 2 2006.201.18:29:37.77#ibcon#*before return 0, iclass 7, count 2 2006.201.18:29:37.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:29:37.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:29:37.77#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.18:29:37.77#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:37.77#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:29:37.89#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:29:37.89#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:29:37.89#ibcon#enter wrdev, iclass 7, count 0 2006.201.18:29:37.89#ibcon#first serial, iclass 7, count 0 2006.201.18:29:37.89#ibcon#enter sib2, iclass 7, count 0 2006.201.18:29:37.89#ibcon#flushed, iclass 7, count 0 2006.201.18:29:37.89#ibcon#about to write, iclass 7, count 0 2006.201.18:29:37.89#ibcon#wrote, iclass 7, count 0 2006.201.18:29:37.89#ibcon#about to read 3, iclass 7, count 0 2006.201.18:29:37.91#ibcon#read 3, iclass 7, count 0 2006.201.18:29:37.91#ibcon#about to read 4, iclass 7, count 0 2006.201.18:29:37.91#ibcon#read 4, iclass 7, count 0 2006.201.18:29:37.91#ibcon#about to read 5, iclass 7, count 0 2006.201.18:29:37.91#ibcon#read 5, iclass 7, count 0 2006.201.18:29:37.91#ibcon#about to read 6, iclass 7, count 0 2006.201.18:29:37.91#ibcon#read 6, iclass 7, count 0 2006.201.18:29:37.91#ibcon#end of sib2, iclass 7, count 0 2006.201.18:29:37.91#ibcon#*mode == 0, iclass 7, count 0 2006.201.18:29:37.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.18:29:37.91#ibcon#[27=USB\r\n] 2006.201.18:29:37.91#ibcon#*before write, iclass 7, count 0 2006.201.18:29:37.91#ibcon#enter sib2, iclass 7, count 0 2006.201.18:29:37.91#ibcon#flushed, iclass 7, count 0 2006.201.18:29:37.91#ibcon#about to write, iclass 7, count 0 2006.201.18:29:37.91#ibcon#wrote, iclass 7, count 0 2006.201.18:29:37.91#ibcon#about to read 3, iclass 7, count 0 2006.201.18:29:37.94#ibcon#read 3, iclass 7, count 0 2006.201.18:29:37.94#ibcon#about to read 4, iclass 7, count 0 2006.201.18:29:37.94#ibcon#read 4, iclass 7, count 0 2006.201.18:29:37.94#ibcon#about to read 5, iclass 7, count 0 2006.201.18:29:37.94#ibcon#read 5, iclass 7, count 0 2006.201.18:29:37.94#ibcon#about to read 6, iclass 7, count 0 2006.201.18:29:37.94#ibcon#read 6, iclass 7, count 0 2006.201.18:29:37.94#ibcon#end of sib2, iclass 7, count 0 2006.201.18:29:37.94#ibcon#*after write, iclass 7, count 0 2006.201.18:29:37.94#ibcon#*before return 0, iclass 7, count 0 2006.201.18:29:37.94#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:29:37.94#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:29:37.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.18:29:37.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.18:29:37.94$vck44/vblo=2,634.99 2006.201.18:29:37.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.18:29:37.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.18:29:37.94#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:37.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:37.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:37.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:37.94#ibcon#enter wrdev, iclass 11, count 0 2006.201.18:29:37.94#ibcon#first serial, iclass 11, count 0 2006.201.18:29:37.94#ibcon#enter sib2, iclass 11, count 0 2006.201.18:29:37.94#ibcon#flushed, iclass 11, count 0 2006.201.18:29:37.94#ibcon#about to write, iclass 11, count 0 2006.201.18:29:37.94#ibcon#wrote, iclass 11, count 0 2006.201.18:29:37.94#ibcon#about to read 3, iclass 11, count 0 2006.201.18:29:37.96#ibcon#read 3, iclass 11, count 0 2006.201.18:29:37.96#ibcon#about to read 4, iclass 11, count 0 2006.201.18:29:37.96#ibcon#read 4, iclass 11, count 0 2006.201.18:29:37.96#ibcon#about to read 5, iclass 11, count 0 2006.201.18:29:37.96#ibcon#read 5, iclass 11, count 0 2006.201.18:29:37.96#ibcon#about to read 6, iclass 11, count 0 2006.201.18:29:37.96#ibcon#read 6, iclass 11, count 0 2006.201.18:29:37.96#ibcon#end of sib2, iclass 11, count 0 2006.201.18:29:37.96#ibcon#*mode == 0, iclass 11, count 0 2006.201.18:29:37.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.18:29:37.96#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:29:37.96#ibcon#*before write, iclass 11, count 0 2006.201.18:29:37.96#ibcon#enter sib2, iclass 11, count 0 2006.201.18:29:37.96#ibcon#flushed, iclass 11, count 0 2006.201.18:29:37.96#ibcon#about to write, iclass 11, count 0 2006.201.18:29:37.96#ibcon#wrote, iclass 11, count 0 2006.201.18:29:37.96#ibcon#about to read 3, iclass 11, count 0 2006.201.18:29:38.00#ibcon#read 3, iclass 11, count 0 2006.201.18:29:38.00#ibcon#about to read 4, iclass 11, count 0 2006.201.18:29:38.00#ibcon#read 4, iclass 11, count 0 2006.201.18:29:38.00#ibcon#about to read 5, iclass 11, count 0 2006.201.18:29:38.00#ibcon#read 5, iclass 11, count 0 2006.201.18:29:38.00#ibcon#about to read 6, iclass 11, count 0 2006.201.18:29:38.00#ibcon#read 6, iclass 11, count 0 2006.201.18:29:38.00#ibcon#end of sib2, iclass 11, count 0 2006.201.18:29:38.00#ibcon#*after write, iclass 11, count 0 2006.201.18:29:38.00#ibcon#*before return 0, iclass 11, count 0 2006.201.18:29:38.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:38.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:29:38.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.18:29:38.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.18:29:38.00$vck44/vb=2,5 2006.201.18:29:38.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.18:29:38.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.18:29:38.00#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:38.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:38.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:38.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:38.06#ibcon#enter wrdev, iclass 13, count 2 2006.201.18:29:38.06#ibcon#first serial, iclass 13, count 2 2006.201.18:29:38.06#ibcon#enter sib2, iclass 13, count 2 2006.201.18:29:38.06#ibcon#flushed, iclass 13, count 2 2006.201.18:29:38.06#ibcon#about to write, iclass 13, count 2 2006.201.18:29:38.06#ibcon#wrote, iclass 13, count 2 2006.201.18:29:38.06#ibcon#about to read 3, iclass 13, count 2 2006.201.18:29:38.08#ibcon#read 3, iclass 13, count 2 2006.201.18:29:38.08#ibcon#about to read 4, iclass 13, count 2 2006.201.18:29:38.08#ibcon#read 4, iclass 13, count 2 2006.201.18:29:38.08#ibcon#about to read 5, iclass 13, count 2 2006.201.18:29:38.08#ibcon#read 5, iclass 13, count 2 2006.201.18:29:38.08#ibcon#about to read 6, iclass 13, count 2 2006.201.18:29:38.08#ibcon#read 6, iclass 13, count 2 2006.201.18:29:38.08#ibcon#end of sib2, iclass 13, count 2 2006.201.18:29:38.08#ibcon#*mode == 0, iclass 13, count 2 2006.201.18:29:38.08#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.18:29:38.08#ibcon#[27=AT02-05\r\n] 2006.201.18:29:38.08#ibcon#*before write, iclass 13, count 2 2006.201.18:29:38.08#ibcon#enter sib2, iclass 13, count 2 2006.201.18:29:38.08#ibcon#flushed, iclass 13, count 2 2006.201.18:29:38.08#ibcon#about to write, iclass 13, count 2 2006.201.18:29:38.08#ibcon#wrote, iclass 13, count 2 2006.201.18:29:38.08#ibcon#about to read 3, iclass 13, count 2 2006.201.18:29:38.11#ibcon#read 3, iclass 13, count 2 2006.201.18:29:38.11#ibcon#about to read 4, iclass 13, count 2 2006.201.18:29:38.11#ibcon#read 4, iclass 13, count 2 2006.201.18:29:38.11#ibcon#about to read 5, iclass 13, count 2 2006.201.18:29:38.11#ibcon#read 5, iclass 13, count 2 2006.201.18:29:38.11#ibcon#about to read 6, iclass 13, count 2 2006.201.18:29:38.11#ibcon#read 6, iclass 13, count 2 2006.201.18:29:38.11#ibcon#end of sib2, iclass 13, count 2 2006.201.18:29:38.11#ibcon#*after write, iclass 13, count 2 2006.201.18:29:38.11#ibcon#*before return 0, iclass 13, count 2 2006.201.18:29:38.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:38.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:29:38.11#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.18:29:38.11#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:38.11#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:38.23#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:38.23#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:38.23#ibcon#enter wrdev, iclass 13, count 0 2006.201.18:29:38.23#ibcon#first serial, iclass 13, count 0 2006.201.18:29:38.23#ibcon#enter sib2, iclass 13, count 0 2006.201.18:29:38.23#ibcon#flushed, iclass 13, count 0 2006.201.18:29:38.23#ibcon#about to write, iclass 13, count 0 2006.201.18:29:38.23#ibcon#wrote, iclass 13, count 0 2006.201.18:29:38.23#ibcon#about to read 3, iclass 13, count 0 2006.201.18:29:38.25#ibcon#read 3, iclass 13, count 0 2006.201.18:29:38.25#ibcon#about to read 4, iclass 13, count 0 2006.201.18:29:38.25#ibcon#read 4, iclass 13, count 0 2006.201.18:29:38.25#ibcon#about to read 5, iclass 13, count 0 2006.201.18:29:38.25#ibcon#read 5, iclass 13, count 0 2006.201.18:29:38.25#ibcon#about to read 6, iclass 13, count 0 2006.201.18:29:38.25#ibcon#read 6, iclass 13, count 0 2006.201.18:29:38.25#ibcon#end of sib2, iclass 13, count 0 2006.201.18:29:38.25#ibcon#*mode == 0, iclass 13, count 0 2006.201.18:29:38.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.18:29:38.25#ibcon#[27=USB\r\n] 2006.201.18:29:38.25#ibcon#*before write, iclass 13, count 0 2006.201.18:29:38.25#ibcon#enter sib2, iclass 13, count 0 2006.201.18:29:38.25#ibcon#flushed, iclass 13, count 0 2006.201.18:29:38.25#ibcon#about to write, iclass 13, count 0 2006.201.18:29:38.25#ibcon#wrote, iclass 13, count 0 2006.201.18:29:38.25#ibcon#about to read 3, iclass 13, count 0 2006.201.18:29:38.28#ibcon#read 3, iclass 13, count 0 2006.201.18:29:38.28#ibcon#about to read 4, iclass 13, count 0 2006.201.18:29:38.28#ibcon#read 4, iclass 13, count 0 2006.201.18:29:38.28#ibcon#about to read 5, iclass 13, count 0 2006.201.18:29:38.28#ibcon#read 5, iclass 13, count 0 2006.201.18:29:38.28#ibcon#about to read 6, iclass 13, count 0 2006.201.18:29:38.28#ibcon#read 6, iclass 13, count 0 2006.201.18:29:38.28#ibcon#end of sib2, iclass 13, count 0 2006.201.18:29:38.28#ibcon#*after write, iclass 13, count 0 2006.201.18:29:38.28#ibcon#*before return 0, iclass 13, count 0 2006.201.18:29:38.28#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:38.28#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:29:38.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.18:29:38.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.18:29:38.28$vck44/vblo=3,649.99 2006.201.18:29:38.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.18:29:38.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.18:29:38.28#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:38.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:38.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:38.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:38.28#ibcon#enter wrdev, iclass 15, count 0 2006.201.18:29:38.28#ibcon#first serial, iclass 15, count 0 2006.201.18:29:38.28#ibcon#enter sib2, iclass 15, count 0 2006.201.18:29:38.28#ibcon#flushed, iclass 15, count 0 2006.201.18:29:38.28#ibcon#about to write, iclass 15, count 0 2006.201.18:29:38.28#ibcon#wrote, iclass 15, count 0 2006.201.18:29:38.28#ibcon#about to read 3, iclass 15, count 0 2006.201.18:29:38.30#ibcon#read 3, iclass 15, count 0 2006.201.18:29:38.30#ibcon#about to read 4, iclass 15, count 0 2006.201.18:29:38.30#ibcon#read 4, iclass 15, count 0 2006.201.18:29:38.30#ibcon#about to read 5, iclass 15, count 0 2006.201.18:29:38.30#ibcon#read 5, iclass 15, count 0 2006.201.18:29:38.30#ibcon#about to read 6, iclass 15, count 0 2006.201.18:29:38.30#ibcon#read 6, iclass 15, count 0 2006.201.18:29:38.30#ibcon#end of sib2, iclass 15, count 0 2006.201.18:29:38.30#ibcon#*mode == 0, iclass 15, count 0 2006.201.18:29:38.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.18:29:38.30#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:29:38.30#ibcon#*before write, iclass 15, count 0 2006.201.18:29:38.30#ibcon#enter sib2, iclass 15, count 0 2006.201.18:29:38.30#ibcon#flushed, iclass 15, count 0 2006.201.18:29:38.30#ibcon#about to write, iclass 15, count 0 2006.201.18:29:38.30#ibcon#wrote, iclass 15, count 0 2006.201.18:29:38.30#ibcon#about to read 3, iclass 15, count 0 2006.201.18:29:38.35#ibcon#read 3, iclass 15, count 0 2006.201.18:29:38.35#ibcon#about to read 4, iclass 15, count 0 2006.201.18:29:38.35#ibcon#read 4, iclass 15, count 0 2006.201.18:29:38.35#ibcon#about to read 5, iclass 15, count 0 2006.201.18:29:38.35#ibcon#read 5, iclass 15, count 0 2006.201.18:29:38.35#ibcon#about to read 6, iclass 15, count 0 2006.201.18:29:38.35#ibcon#read 6, iclass 15, count 0 2006.201.18:29:38.35#ibcon#end of sib2, iclass 15, count 0 2006.201.18:29:38.35#ibcon#*after write, iclass 15, count 0 2006.201.18:29:38.35#ibcon#*before return 0, iclass 15, count 0 2006.201.18:29:38.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:38.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:29:38.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.18:29:38.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.18:29:38.35$vck44/vb=3,4 2006.201.18:29:38.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.18:29:38.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.18:29:38.35#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:38.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:38.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:38.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:38.40#ibcon#enter wrdev, iclass 17, count 2 2006.201.18:29:38.40#ibcon#first serial, iclass 17, count 2 2006.201.18:29:38.40#ibcon#enter sib2, iclass 17, count 2 2006.201.18:29:38.40#ibcon#flushed, iclass 17, count 2 2006.201.18:29:38.40#ibcon#about to write, iclass 17, count 2 2006.201.18:29:38.40#ibcon#wrote, iclass 17, count 2 2006.201.18:29:38.40#ibcon#about to read 3, iclass 17, count 2 2006.201.18:29:38.42#ibcon#read 3, iclass 17, count 2 2006.201.18:29:38.42#ibcon#about to read 4, iclass 17, count 2 2006.201.18:29:38.42#ibcon#read 4, iclass 17, count 2 2006.201.18:29:38.42#ibcon#about to read 5, iclass 17, count 2 2006.201.18:29:38.42#ibcon#read 5, iclass 17, count 2 2006.201.18:29:38.42#ibcon#about to read 6, iclass 17, count 2 2006.201.18:29:38.42#ibcon#read 6, iclass 17, count 2 2006.201.18:29:38.42#ibcon#end of sib2, iclass 17, count 2 2006.201.18:29:38.42#ibcon#*mode == 0, iclass 17, count 2 2006.201.18:29:38.42#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.18:29:38.42#ibcon#[27=AT03-04\r\n] 2006.201.18:29:38.42#ibcon#*before write, iclass 17, count 2 2006.201.18:29:38.42#ibcon#enter sib2, iclass 17, count 2 2006.201.18:29:38.42#ibcon#flushed, iclass 17, count 2 2006.201.18:29:38.42#ibcon#about to write, iclass 17, count 2 2006.201.18:29:38.42#ibcon#wrote, iclass 17, count 2 2006.201.18:29:38.42#ibcon#about to read 3, iclass 17, count 2 2006.201.18:29:38.45#ibcon#read 3, iclass 17, count 2 2006.201.18:29:38.45#ibcon#about to read 4, iclass 17, count 2 2006.201.18:29:38.45#ibcon#read 4, iclass 17, count 2 2006.201.18:29:38.45#ibcon#about to read 5, iclass 17, count 2 2006.201.18:29:38.45#ibcon#read 5, iclass 17, count 2 2006.201.18:29:38.45#ibcon#about to read 6, iclass 17, count 2 2006.201.18:29:38.45#ibcon#read 6, iclass 17, count 2 2006.201.18:29:38.45#ibcon#end of sib2, iclass 17, count 2 2006.201.18:29:38.45#ibcon#*after write, iclass 17, count 2 2006.201.18:29:38.45#ibcon#*before return 0, iclass 17, count 2 2006.201.18:29:38.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:38.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:29:38.45#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.18:29:38.45#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:38.45#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:38.57#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:38.57#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:38.57#ibcon#enter wrdev, iclass 17, count 0 2006.201.18:29:38.57#ibcon#first serial, iclass 17, count 0 2006.201.18:29:38.57#ibcon#enter sib2, iclass 17, count 0 2006.201.18:29:38.57#ibcon#flushed, iclass 17, count 0 2006.201.18:29:38.57#ibcon#about to write, iclass 17, count 0 2006.201.18:29:38.57#ibcon#wrote, iclass 17, count 0 2006.201.18:29:38.57#ibcon#about to read 3, iclass 17, count 0 2006.201.18:29:38.59#ibcon#read 3, iclass 17, count 0 2006.201.18:29:38.59#ibcon#about to read 4, iclass 17, count 0 2006.201.18:29:38.59#ibcon#read 4, iclass 17, count 0 2006.201.18:29:38.59#ibcon#about to read 5, iclass 17, count 0 2006.201.18:29:38.59#ibcon#read 5, iclass 17, count 0 2006.201.18:29:38.59#ibcon#about to read 6, iclass 17, count 0 2006.201.18:29:38.59#ibcon#read 6, iclass 17, count 0 2006.201.18:29:38.59#ibcon#end of sib2, iclass 17, count 0 2006.201.18:29:38.59#ibcon#*mode == 0, iclass 17, count 0 2006.201.18:29:38.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.18:29:38.59#ibcon#[27=USB\r\n] 2006.201.18:29:38.59#ibcon#*before write, iclass 17, count 0 2006.201.18:29:38.59#ibcon#enter sib2, iclass 17, count 0 2006.201.18:29:38.59#ibcon#flushed, iclass 17, count 0 2006.201.18:29:38.59#ibcon#about to write, iclass 17, count 0 2006.201.18:29:38.59#ibcon#wrote, iclass 17, count 0 2006.201.18:29:38.59#ibcon#about to read 3, iclass 17, count 0 2006.201.18:29:38.62#ibcon#read 3, iclass 17, count 0 2006.201.18:29:38.62#ibcon#about to read 4, iclass 17, count 0 2006.201.18:29:38.62#ibcon#read 4, iclass 17, count 0 2006.201.18:29:38.62#ibcon#about to read 5, iclass 17, count 0 2006.201.18:29:38.62#ibcon#read 5, iclass 17, count 0 2006.201.18:29:38.62#ibcon#about to read 6, iclass 17, count 0 2006.201.18:29:38.62#ibcon#read 6, iclass 17, count 0 2006.201.18:29:38.62#ibcon#end of sib2, iclass 17, count 0 2006.201.18:29:38.62#ibcon#*after write, iclass 17, count 0 2006.201.18:29:38.62#ibcon#*before return 0, iclass 17, count 0 2006.201.18:29:38.62#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:38.62#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:29:38.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.18:29:38.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.18:29:38.62$vck44/vblo=4,679.99 2006.201.18:29:38.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.18:29:38.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.18:29:38.62#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:38.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:38.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:38.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:38.62#ibcon#enter wrdev, iclass 19, count 0 2006.201.18:29:38.62#ibcon#first serial, iclass 19, count 0 2006.201.18:29:38.62#ibcon#enter sib2, iclass 19, count 0 2006.201.18:29:38.62#ibcon#flushed, iclass 19, count 0 2006.201.18:29:38.62#ibcon#about to write, iclass 19, count 0 2006.201.18:29:38.62#ibcon#wrote, iclass 19, count 0 2006.201.18:29:38.62#ibcon#about to read 3, iclass 19, count 0 2006.201.18:29:38.64#ibcon#read 3, iclass 19, count 0 2006.201.18:29:38.64#ibcon#about to read 4, iclass 19, count 0 2006.201.18:29:38.64#ibcon#read 4, iclass 19, count 0 2006.201.18:29:38.64#ibcon#about to read 5, iclass 19, count 0 2006.201.18:29:38.64#ibcon#read 5, iclass 19, count 0 2006.201.18:29:38.64#ibcon#about to read 6, iclass 19, count 0 2006.201.18:29:38.64#ibcon#read 6, iclass 19, count 0 2006.201.18:29:38.64#ibcon#end of sib2, iclass 19, count 0 2006.201.18:29:38.64#ibcon#*mode == 0, iclass 19, count 0 2006.201.18:29:38.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.18:29:38.64#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:29:38.64#ibcon#*before write, iclass 19, count 0 2006.201.18:29:38.64#ibcon#enter sib2, iclass 19, count 0 2006.201.18:29:38.64#ibcon#flushed, iclass 19, count 0 2006.201.18:29:38.64#ibcon#about to write, iclass 19, count 0 2006.201.18:29:38.64#ibcon#wrote, iclass 19, count 0 2006.201.18:29:38.64#ibcon#about to read 3, iclass 19, count 0 2006.201.18:29:38.68#ibcon#read 3, iclass 19, count 0 2006.201.18:29:38.68#ibcon#about to read 4, iclass 19, count 0 2006.201.18:29:38.68#ibcon#read 4, iclass 19, count 0 2006.201.18:29:38.68#ibcon#about to read 5, iclass 19, count 0 2006.201.18:29:38.68#ibcon#read 5, iclass 19, count 0 2006.201.18:29:38.68#ibcon#about to read 6, iclass 19, count 0 2006.201.18:29:38.68#ibcon#read 6, iclass 19, count 0 2006.201.18:29:38.68#ibcon#end of sib2, iclass 19, count 0 2006.201.18:29:38.68#ibcon#*after write, iclass 19, count 0 2006.201.18:29:38.68#ibcon#*before return 0, iclass 19, count 0 2006.201.18:29:38.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:38.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:29:38.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.18:29:38.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.18:29:38.68$vck44/vb=4,5 2006.201.18:29:38.68#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.18:29:38.68#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.18:29:38.68#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:38.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:38.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:38.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:38.74#ibcon#enter wrdev, iclass 21, count 2 2006.201.18:29:38.74#ibcon#first serial, iclass 21, count 2 2006.201.18:29:38.74#ibcon#enter sib2, iclass 21, count 2 2006.201.18:29:38.74#ibcon#flushed, iclass 21, count 2 2006.201.18:29:38.74#ibcon#about to write, iclass 21, count 2 2006.201.18:29:38.74#ibcon#wrote, iclass 21, count 2 2006.201.18:29:38.74#ibcon#about to read 3, iclass 21, count 2 2006.201.18:29:38.76#ibcon#read 3, iclass 21, count 2 2006.201.18:29:38.76#ibcon#about to read 4, iclass 21, count 2 2006.201.18:29:38.76#ibcon#read 4, iclass 21, count 2 2006.201.18:29:38.76#ibcon#about to read 5, iclass 21, count 2 2006.201.18:29:38.76#ibcon#read 5, iclass 21, count 2 2006.201.18:29:38.76#ibcon#about to read 6, iclass 21, count 2 2006.201.18:29:38.76#ibcon#read 6, iclass 21, count 2 2006.201.18:29:38.76#ibcon#end of sib2, iclass 21, count 2 2006.201.18:29:38.76#ibcon#*mode == 0, iclass 21, count 2 2006.201.18:29:38.76#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.18:29:38.76#ibcon#[27=AT04-05\r\n] 2006.201.18:29:38.76#ibcon#*before write, iclass 21, count 2 2006.201.18:29:38.76#ibcon#enter sib2, iclass 21, count 2 2006.201.18:29:38.76#ibcon#flushed, iclass 21, count 2 2006.201.18:29:38.76#ibcon#about to write, iclass 21, count 2 2006.201.18:29:38.76#ibcon#wrote, iclass 21, count 2 2006.201.18:29:38.76#ibcon#about to read 3, iclass 21, count 2 2006.201.18:29:38.79#ibcon#read 3, iclass 21, count 2 2006.201.18:29:38.79#ibcon#about to read 4, iclass 21, count 2 2006.201.18:29:38.79#ibcon#read 4, iclass 21, count 2 2006.201.18:29:38.79#ibcon#about to read 5, iclass 21, count 2 2006.201.18:29:38.79#ibcon#read 5, iclass 21, count 2 2006.201.18:29:38.79#ibcon#about to read 6, iclass 21, count 2 2006.201.18:29:38.79#ibcon#read 6, iclass 21, count 2 2006.201.18:29:38.79#ibcon#end of sib2, iclass 21, count 2 2006.201.18:29:38.79#ibcon#*after write, iclass 21, count 2 2006.201.18:29:38.79#ibcon#*before return 0, iclass 21, count 2 2006.201.18:29:38.79#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:38.79#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:29:38.79#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.18:29:38.79#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:38.79#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:38.91#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:38.91#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:38.91#ibcon#enter wrdev, iclass 21, count 0 2006.201.18:29:38.91#ibcon#first serial, iclass 21, count 0 2006.201.18:29:38.91#ibcon#enter sib2, iclass 21, count 0 2006.201.18:29:38.91#ibcon#flushed, iclass 21, count 0 2006.201.18:29:38.91#ibcon#about to write, iclass 21, count 0 2006.201.18:29:38.91#ibcon#wrote, iclass 21, count 0 2006.201.18:29:38.91#ibcon#about to read 3, iclass 21, count 0 2006.201.18:29:38.93#ibcon#read 3, iclass 21, count 0 2006.201.18:29:38.93#ibcon#about to read 4, iclass 21, count 0 2006.201.18:29:38.93#ibcon#read 4, iclass 21, count 0 2006.201.18:29:38.93#ibcon#about to read 5, iclass 21, count 0 2006.201.18:29:38.93#ibcon#read 5, iclass 21, count 0 2006.201.18:29:38.93#ibcon#about to read 6, iclass 21, count 0 2006.201.18:29:38.93#ibcon#read 6, iclass 21, count 0 2006.201.18:29:38.93#ibcon#end of sib2, iclass 21, count 0 2006.201.18:29:38.93#ibcon#*mode == 0, iclass 21, count 0 2006.201.18:29:38.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.18:29:38.93#ibcon#[27=USB\r\n] 2006.201.18:29:38.93#ibcon#*before write, iclass 21, count 0 2006.201.18:29:38.93#ibcon#enter sib2, iclass 21, count 0 2006.201.18:29:38.93#ibcon#flushed, iclass 21, count 0 2006.201.18:29:38.93#ibcon#about to write, iclass 21, count 0 2006.201.18:29:38.93#ibcon#wrote, iclass 21, count 0 2006.201.18:29:38.93#ibcon#about to read 3, iclass 21, count 0 2006.201.18:29:38.96#ibcon#read 3, iclass 21, count 0 2006.201.18:29:38.96#ibcon#about to read 4, iclass 21, count 0 2006.201.18:29:38.96#ibcon#read 4, iclass 21, count 0 2006.201.18:29:38.96#ibcon#about to read 5, iclass 21, count 0 2006.201.18:29:38.96#ibcon#read 5, iclass 21, count 0 2006.201.18:29:38.96#ibcon#about to read 6, iclass 21, count 0 2006.201.18:29:38.96#ibcon#read 6, iclass 21, count 0 2006.201.18:29:38.96#ibcon#end of sib2, iclass 21, count 0 2006.201.18:29:38.96#ibcon#*after write, iclass 21, count 0 2006.201.18:29:38.96#ibcon#*before return 0, iclass 21, count 0 2006.201.18:29:38.96#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:38.96#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:29:38.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.18:29:38.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.18:29:38.96$vck44/vblo=5,709.99 2006.201.18:29:38.96#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.18:29:38.96#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.18:29:38.96#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:38.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:38.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:38.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:38.96#ibcon#enter wrdev, iclass 23, count 0 2006.201.18:29:38.96#ibcon#first serial, iclass 23, count 0 2006.201.18:29:38.96#ibcon#enter sib2, iclass 23, count 0 2006.201.18:29:38.96#ibcon#flushed, iclass 23, count 0 2006.201.18:29:38.96#ibcon#about to write, iclass 23, count 0 2006.201.18:29:38.96#ibcon#wrote, iclass 23, count 0 2006.201.18:29:38.96#ibcon#about to read 3, iclass 23, count 0 2006.201.18:29:38.98#ibcon#read 3, iclass 23, count 0 2006.201.18:29:38.98#ibcon#about to read 4, iclass 23, count 0 2006.201.18:29:38.98#ibcon#read 4, iclass 23, count 0 2006.201.18:29:38.98#ibcon#about to read 5, iclass 23, count 0 2006.201.18:29:38.98#ibcon#read 5, iclass 23, count 0 2006.201.18:29:38.98#ibcon#about to read 6, iclass 23, count 0 2006.201.18:29:38.98#ibcon#read 6, iclass 23, count 0 2006.201.18:29:38.98#ibcon#end of sib2, iclass 23, count 0 2006.201.18:29:38.98#ibcon#*mode == 0, iclass 23, count 0 2006.201.18:29:38.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.18:29:38.98#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:29:38.98#ibcon#*before write, iclass 23, count 0 2006.201.18:29:38.98#ibcon#enter sib2, iclass 23, count 0 2006.201.18:29:38.98#ibcon#flushed, iclass 23, count 0 2006.201.18:29:38.98#ibcon#about to write, iclass 23, count 0 2006.201.18:29:38.98#ibcon#wrote, iclass 23, count 0 2006.201.18:29:38.98#ibcon#about to read 3, iclass 23, count 0 2006.201.18:29:39.03#ibcon#read 3, iclass 23, count 0 2006.201.18:29:39.03#ibcon#about to read 4, iclass 23, count 0 2006.201.18:29:39.03#ibcon#read 4, iclass 23, count 0 2006.201.18:29:39.03#ibcon#about to read 5, iclass 23, count 0 2006.201.18:29:39.03#ibcon#read 5, iclass 23, count 0 2006.201.18:29:39.03#ibcon#about to read 6, iclass 23, count 0 2006.201.18:29:39.03#ibcon#read 6, iclass 23, count 0 2006.201.18:29:39.03#ibcon#end of sib2, iclass 23, count 0 2006.201.18:29:39.03#ibcon#*after write, iclass 23, count 0 2006.201.18:29:39.03#ibcon#*before return 0, iclass 23, count 0 2006.201.18:29:39.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:39.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:29:39.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.18:29:39.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.18:29:39.03$vck44/vb=5,4 2006.201.18:29:39.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.18:29:39.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.18:29:39.03#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:39.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:39.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:39.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:39.08#ibcon#enter wrdev, iclass 25, count 2 2006.201.18:29:39.08#ibcon#first serial, iclass 25, count 2 2006.201.18:29:39.08#ibcon#enter sib2, iclass 25, count 2 2006.201.18:29:39.08#ibcon#flushed, iclass 25, count 2 2006.201.18:29:39.08#ibcon#about to write, iclass 25, count 2 2006.201.18:29:39.08#ibcon#wrote, iclass 25, count 2 2006.201.18:29:39.08#ibcon#about to read 3, iclass 25, count 2 2006.201.18:29:39.10#ibcon#read 3, iclass 25, count 2 2006.201.18:29:39.10#ibcon#about to read 4, iclass 25, count 2 2006.201.18:29:39.10#ibcon#read 4, iclass 25, count 2 2006.201.18:29:39.10#ibcon#about to read 5, iclass 25, count 2 2006.201.18:29:39.10#ibcon#read 5, iclass 25, count 2 2006.201.18:29:39.10#ibcon#about to read 6, iclass 25, count 2 2006.201.18:29:39.10#ibcon#read 6, iclass 25, count 2 2006.201.18:29:39.10#ibcon#end of sib2, iclass 25, count 2 2006.201.18:29:39.10#ibcon#*mode == 0, iclass 25, count 2 2006.201.18:29:39.10#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.18:29:39.10#ibcon#[27=AT05-04\r\n] 2006.201.18:29:39.10#ibcon#*before write, iclass 25, count 2 2006.201.18:29:39.10#ibcon#enter sib2, iclass 25, count 2 2006.201.18:29:39.10#ibcon#flushed, iclass 25, count 2 2006.201.18:29:39.10#ibcon#about to write, iclass 25, count 2 2006.201.18:29:39.10#ibcon#wrote, iclass 25, count 2 2006.201.18:29:39.10#ibcon#about to read 3, iclass 25, count 2 2006.201.18:29:39.13#ibcon#read 3, iclass 25, count 2 2006.201.18:29:39.13#ibcon#about to read 4, iclass 25, count 2 2006.201.18:29:39.13#ibcon#read 4, iclass 25, count 2 2006.201.18:29:39.13#ibcon#about to read 5, iclass 25, count 2 2006.201.18:29:39.13#ibcon#read 5, iclass 25, count 2 2006.201.18:29:39.13#ibcon#about to read 6, iclass 25, count 2 2006.201.18:29:39.13#ibcon#read 6, iclass 25, count 2 2006.201.18:29:39.13#ibcon#end of sib2, iclass 25, count 2 2006.201.18:29:39.13#ibcon#*after write, iclass 25, count 2 2006.201.18:29:39.13#ibcon#*before return 0, iclass 25, count 2 2006.201.18:29:39.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:39.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:29:39.13#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.18:29:39.13#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:39.13#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:39.25#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:39.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:39.25#ibcon#enter wrdev, iclass 25, count 0 2006.201.18:29:39.25#ibcon#first serial, iclass 25, count 0 2006.201.18:29:39.25#ibcon#enter sib2, iclass 25, count 0 2006.201.18:29:39.25#ibcon#flushed, iclass 25, count 0 2006.201.18:29:39.25#ibcon#about to write, iclass 25, count 0 2006.201.18:29:39.25#ibcon#wrote, iclass 25, count 0 2006.201.18:29:39.25#ibcon#about to read 3, iclass 25, count 0 2006.201.18:29:39.27#ibcon#read 3, iclass 25, count 0 2006.201.18:29:39.27#ibcon#about to read 4, iclass 25, count 0 2006.201.18:29:39.27#ibcon#read 4, iclass 25, count 0 2006.201.18:29:39.27#ibcon#about to read 5, iclass 25, count 0 2006.201.18:29:39.27#ibcon#read 5, iclass 25, count 0 2006.201.18:29:39.27#ibcon#about to read 6, iclass 25, count 0 2006.201.18:29:39.27#ibcon#read 6, iclass 25, count 0 2006.201.18:29:39.27#ibcon#end of sib2, iclass 25, count 0 2006.201.18:29:39.27#ibcon#*mode == 0, iclass 25, count 0 2006.201.18:29:39.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.18:29:39.27#ibcon#[27=USB\r\n] 2006.201.18:29:39.27#ibcon#*before write, iclass 25, count 0 2006.201.18:29:39.27#ibcon#enter sib2, iclass 25, count 0 2006.201.18:29:39.27#ibcon#flushed, iclass 25, count 0 2006.201.18:29:39.27#ibcon#about to write, iclass 25, count 0 2006.201.18:29:39.27#ibcon#wrote, iclass 25, count 0 2006.201.18:29:39.27#ibcon#about to read 3, iclass 25, count 0 2006.201.18:29:39.30#ibcon#read 3, iclass 25, count 0 2006.201.18:29:39.30#ibcon#about to read 4, iclass 25, count 0 2006.201.18:29:39.30#ibcon#read 4, iclass 25, count 0 2006.201.18:29:39.30#ibcon#about to read 5, iclass 25, count 0 2006.201.18:29:39.30#ibcon#read 5, iclass 25, count 0 2006.201.18:29:39.30#ibcon#about to read 6, iclass 25, count 0 2006.201.18:29:39.30#ibcon#read 6, iclass 25, count 0 2006.201.18:29:39.30#ibcon#end of sib2, iclass 25, count 0 2006.201.18:29:39.30#ibcon#*after write, iclass 25, count 0 2006.201.18:29:39.30#ibcon#*before return 0, iclass 25, count 0 2006.201.18:29:39.30#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:39.30#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:29:39.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.18:29:39.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.18:29:39.30$vck44/vblo=6,719.99 2006.201.18:29:39.30#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.18:29:39.30#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.18:29:39.30#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:39.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:39.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:39.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:39.30#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:29:39.30#ibcon#first serial, iclass 27, count 0 2006.201.18:29:39.30#ibcon#enter sib2, iclass 27, count 0 2006.201.18:29:39.30#ibcon#flushed, iclass 27, count 0 2006.201.18:29:39.30#ibcon#about to write, iclass 27, count 0 2006.201.18:29:39.30#ibcon#wrote, iclass 27, count 0 2006.201.18:29:39.30#ibcon#about to read 3, iclass 27, count 0 2006.201.18:29:39.32#ibcon#read 3, iclass 27, count 0 2006.201.18:29:39.32#ibcon#about to read 4, iclass 27, count 0 2006.201.18:29:39.32#ibcon#read 4, iclass 27, count 0 2006.201.18:29:39.32#ibcon#about to read 5, iclass 27, count 0 2006.201.18:29:39.32#ibcon#read 5, iclass 27, count 0 2006.201.18:29:39.32#ibcon#about to read 6, iclass 27, count 0 2006.201.18:29:39.32#ibcon#read 6, iclass 27, count 0 2006.201.18:29:39.32#ibcon#end of sib2, iclass 27, count 0 2006.201.18:29:39.32#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:29:39.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:29:39.32#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:29:39.32#ibcon#*before write, iclass 27, count 0 2006.201.18:29:39.32#ibcon#enter sib2, iclass 27, count 0 2006.201.18:29:39.32#ibcon#flushed, iclass 27, count 0 2006.201.18:29:39.32#ibcon#about to write, iclass 27, count 0 2006.201.18:29:39.32#ibcon#wrote, iclass 27, count 0 2006.201.18:29:39.32#ibcon#about to read 3, iclass 27, count 0 2006.201.18:29:39.36#ibcon#read 3, iclass 27, count 0 2006.201.18:29:39.36#ibcon#about to read 4, iclass 27, count 0 2006.201.18:29:39.36#ibcon#read 4, iclass 27, count 0 2006.201.18:29:39.36#ibcon#about to read 5, iclass 27, count 0 2006.201.18:29:39.36#ibcon#read 5, iclass 27, count 0 2006.201.18:29:39.36#ibcon#about to read 6, iclass 27, count 0 2006.201.18:29:39.36#ibcon#read 6, iclass 27, count 0 2006.201.18:29:39.36#ibcon#end of sib2, iclass 27, count 0 2006.201.18:29:39.36#ibcon#*after write, iclass 27, count 0 2006.201.18:29:39.36#ibcon#*before return 0, iclass 27, count 0 2006.201.18:29:39.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:39.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:29:39.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:29:39.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:29:39.36$vck44/vb=6,4 2006.201.18:29:39.36#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.18:29:39.36#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.18:29:39.36#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:39.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:39.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:39.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:39.42#ibcon#enter wrdev, iclass 29, count 2 2006.201.18:29:39.42#ibcon#first serial, iclass 29, count 2 2006.201.18:29:39.42#ibcon#enter sib2, iclass 29, count 2 2006.201.18:29:39.42#ibcon#flushed, iclass 29, count 2 2006.201.18:29:39.42#ibcon#about to write, iclass 29, count 2 2006.201.18:29:39.42#ibcon#wrote, iclass 29, count 2 2006.201.18:29:39.42#ibcon#about to read 3, iclass 29, count 2 2006.201.18:29:39.44#ibcon#read 3, iclass 29, count 2 2006.201.18:29:39.44#ibcon#about to read 4, iclass 29, count 2 2006.201.18:29:39.44#ibcon#read 4, iclass 29, count 2 2006.201.18:29:39.44#ibcon#about to read 5, iclass 29, count 2 2006.201.18:29:39.44#ibcon#read 5, iclass 29, count 2 2006.201.18:29:39.44#ibcon#about to read 6, iclass 29, count 2 2006.201.18:29:39.44#ibcon#read 6, iclass 29, count 2 2006.201.18:29:39.44#ibcon#end of sib2, iclass 29, count 2 2006.201.18:29:39.44#ibcon#*mode == 0, iclass 29, count 2 2006.201.18:29:39.44#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.18:29:39.44#ibcon#[27=AT06-04\r\n] 2006.201.18:29:39.44#ibcon#*before write, iclass 29, count 2 2006.201.18:29:39.44#ibcon#enter sib2, iclass 29, count 2 2006.201.18:29:39.44#ibcon#flushed, iclass 29, count 2 2006.201.18:29:39.44#ibcon#about to write, iclass 29, count 2 2006.201.18:29:39.44#ibcon#wrote, iclass 29, count 2 2006.201.18:29:39.44#ibcon#about to read 3, iclass 29, count 2 2006.201.18:29:39.47#ibcon#read 3, iclass 29, count 2 2006.201.18:29:39.47#ibcon#about to read 4, iclass 29, count 2 2006.201.18:29:39.47#ibcon#read 4, iclass 29, count 2 2006.201.18:29:39.47#ibcon#about to read 5, iclass 29, count 2 2006.201.18:29:39.47#ibcon#read 5, iclass 29, count 2 2006.201.18:29:39.47#ibcon#about to read 6, iclass 29, count 2 2006.201.18:29:39.47#ibcon#read 6, iclass 29, count 2 2006.201.18:29:39.47#ibcon#end of sib2, iclass 29, count 2 2006.201.18:29:39.47#ibcon#*after write, iclass 29, count 2 2006.201.18:29:39.47#ibcon#*before return 0, iclass 29, count 2 2006.201.18:29:39.47#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:39.47#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:29:39.47#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.18:29:39.47#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:39.47#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:39.59#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:39.59#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:39.59#ibcon#enter wrdev, iclass 29, count 0 2006.201.18:29:39.59#ibcon#first serial, iclass 29, count 0 2006.201.18:29:39.59#ibcon#enter sib2, iclass 29, count 0 2006.201.18:29:39.59#ibcon#flushed, iclass 29, count 0 2006.201.18:29:39.59#ibcon#about to write, iclass 29, count 0 2006.201.18:29:39.59#ibcon#wrote, iclass 29, count 0 2006.201.18:29:39.59#ibcon#about to read 3, iclass 29, count 0 2006.201.18:29:39.61#ibcon#read 3, iclass 29, count 0 2006.201.18:29:39.61#ibcon#about to read 4, iclass 29, count 0 2006.201.18:29:39.61#ibcon#read 4, iclass 29, count 0 2006.201.18:29:39.61#ibcon#about to read 5, iclass 29, count 0 2006.201.18:29:39.61#ibcon#read 5, iclass 29, count 0 2006.201.18:29:39.61#ibcon#about to read 6, iclass 29, count 0 2006.201.18:29:39.61#ibcon#read 6, iclass 29, count 0 2006.201.18:29:39.61#ibcon#end of sib2, iclass 29, count 0 2006.201.18:29:39.61#ibcon#*mode == 0, iclass 29, count 0 2006.201.18:29:39.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.18:29:39.61#ibcon#[27=USB\r\n] 2006.201.18:29:39.61#ibcon#*before write, iclass 29, count 0 2006.201.18:29:39.61#ibcon#enter sib2, iclass 29, count 0 2006.201.18:29:39.61#ibcon#flushed, iclass 29, count 0 2006.201.18:29:39.61#ibcon#about to write, iclass 29, count 0 2006.201.18:29:39.61#ibcon#wrote, iclass 29, count 0 2006.201.18:29:39.61#ibcon#about to read 3, iclass 29, count 0 2006.201.18:29:39.64#ibcon#read 3, iclass 29, count 0 2006.201.18:29:39.64#ibcon#about to read 4, iclass 29, count 0 2006.201.18:29:39.64#ibcon#read 4, iclass 29, count 0 2006.201.18:29:39.64#ibcon#about to read 5, iclass 29, count 0 2006.201.18:29:39.64#ibcon#read 5, iclass 29, count 0 2006.201.18:29:39.64#ibcon#about to read 6, iclass 29, count 0 2006.201.18:29:39.64#ibcon#read 6, iclass 29, count 0 2006.201.18:29:39.64#ibcon#end of sib2, iclass 29, count 0 2006.201.18:29:39.64#ibcon#*after write, iclass 29, count 0 2006.201.18:29:39.64#ibcon#*before return 0, iclass 29, count 0 2006.201.18:29:39.64#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:39.64#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:29:39.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.18:29:39.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.18:29:39.64$vck44/vblo=7,734.99 2006.201.18:29:39.64#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.18:29:39.64#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.18:29:39.64#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:39.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:39.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:39.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:39.64#ibcon#enter wrdev, iclass 31, count 0 2006.201.18:29:39.64#ibcon#first serial, iclass 31, count 0 2006.201.18:29:39.64#ibcon#enter sib2, iclass 31, count 0 2006.201.18:29:39.64#ibcon#flushed, iclass 31, count 0 2006.201.18:29:39.64#ibcon#about to write, iclass 31, count 0 2006.201.18:29:39.64#ibcon#wrote, iclass 31, count 0 2006.201.18:29:39.64#ibcon#about to read 3, iclass 31, count 0 2006.201.18:29:39.66#ibcon#read 3, iclass 31, count 0 2006.201.18:29:39.66#ibcon#about to read 4, iclass 31, count 0 2006.201.18:29:39.66#ibcon#read 4, iclass 31, count 0 2006.201.18:29:39.66#ibcon#about to read 5, iclass 31, count 0 2006.201.18:29:39.66#ibcon#read 5, iclass 31, count 0 2006.201.18:29:39.66#ibcon#about to read 6, iclass 31, count 0 2006.201.18:29:39.66#ibcon#read 6, iclass 31, count 0 2006.201.18:29:39.66#ibcon#end of sib2, iclass 31, count 0 2006.201.18:29:39.66#ibcon#*mode == 0, iclass 31, count 0 2006.201.18:29:39.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.18:29:39.66#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:29:39.66#ibcon#*before write, iclass 31, count 0 2006.201.18:29:39.66#ibcon#enter sib2, iclass 31, count 0 2006.201.18:29:39.66#ibcon#flushed, iclass 31, count 0 2006.201.18:29:39.66#ibcon#about to write, iclass 31, count 0 2006.201.18:29:39.66#ibcon#wrote, iclass 31, count 0 2006.201.18:29:39.66#ibcon#about to read 3, iclass 31, count 0 2006.201.18:29:39.70#ibcon#read 3, iclass 31, count 0 2006.201.18:29:39.70#ibcon#about to read 4, iclass 31, count 0 2006.201.18:29:39.70#ibcon#read 4, iclass 31, count 0 2006.201.18:29:39.70#ibcon#about to read 5, iclass 31, count 0 2006.201.18:29:39.70#ibcon#read 5, iclass 31, count 0 2006.201.18:29:39.70#ibcon#about to read 6, iclass 31, count 0 2006.201.18:29:39.70#ibcon#read 6, iclass 31, count 0 2006.201.18:29:39.70#ibcon#end of sib2, iclass 31, count 0 2006.201.18:29:39.70#ibcon#*after write, iclass 31, count 0 2006.201.18:29:39.70#ibcon#*before return 0, iclass 31, count 0 2006.201.18:29:39.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:39.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:29:39.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.18:29:39.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.18:29:39.70$vck44/vb=7,4 2006.201.18:29:39.70#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.18:29:39.70#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.18:29:39.70#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:39.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:39.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:39.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:39.76#ibcon#enter wrdev, iclass 33, count 2 2006.201.18:29:39.76#ibcon#first serial, iclass 33, count 2 2006.201.18:29:39.76#ibcon#enter sib2, iclass 33, count 2 2006.201.18:29:39.76#ibcon#flushed, iclass 33, count 2 2006.201.18:29:39.76#ibcon#about to write, iclass 33, count 2 2006.201.18:29:39.76#ibcon#wrote, iclass 33, count 2 2006.201.18:29:39.76#ibcon#about to read 3, iclass 33, count 2 2006.201.18:29:39.78#ibcon#read 3, iclass 33, count 2 2006.201.18:29:39.78#ibcon#about to read 4, iclass 33, count 2 2006.201.18:29:39.78#ibcon#read 4, iclass 33, count 2 2006.201.18:29:39.78#ibcon#about to read 5, iclass 33, count 2 2006.201.18:29:39.78#ibcon#read 5, iclass 33, count 2 2006.201.18:29:39.78#ibcon#about to read 6, iclass 33, count 2 2006.201.18:29:39.78#ibcon#read 6, iclass 33, count 2 2006.201.18:29:39.78#ibcon#end of sib2, iclass 33, count 2 2006.201.18:29:39.78#ibcon#*mode == 0, iclass 33, count 2 2006.201.18:29:39.78#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.18:29:39.78#ibcon#[27=AT07-04\r\n] 2006.201.18:29:39.78#ibcon#*before write, iclass 33, count 2 2006.201.18:29:39.78#ibcon#enter sib2, iclass 33, count 2 2006.201.18:29:39.78#ibcon#flushed, iclass 33, count 2 2006.201.18:29:39.78#ibcon#about to write, iclass 33, count 2 2006.201.18:29:39.78#ibcon#wrote, iclass 33, count 2 2006.201.18:29:39.78#ibcon#about to read 3, iclass 33, count 2 2006.201.18:29:39.81#ibcon#read 3, iclass 33, count 2 2006.201.18:29:39.81#ibcon#about to read 4, iclass 33, count 2 2006.201.18:29:39.81#ibcon#read 4, iclass 33, count 2 2006.201.18:29:39.81#ibcon#about to read 5, iclass 33, count 2 2006.201.18:29:39.81#ibcon#read 5, iclass 33, count 2 2006.201.18:29:39.81#ibcon#about to read 6, iclass 33, count 2 2006.201.18:29:39.81#ibcon#read 6, iclass 33, count 2 2006.201.18:29:39.81#ibcon#end of sib2, iclass 33, count 2 2006.201.18:29:39.81#ibcon#*after write, iclass 33, count 2 2006.201.18:29:39.81#ibcon#*before return 0, iclass 33, count 2 2006.201.18:29:39.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:39.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:29:39.81#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.18:29:39.81#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:39.81#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:39.93#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:39.93#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:39.93#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:29:39.93#ibcon#first serial, iclass 33, count 0 2006.201.18:29:39.93#ibcon#enter sib2, iclass 33, count 0 2006.201.18:29:39.93#ibcon#flushed, iclass 33, count 0 2006.201.18:29:39.93#ibcon#about to write, iclass 33, count 0 2006.201.18:29:39.93#ibcon#wrote, iclass 33, count 0 2006.201.18:29:39.93#ibcon#about to read 3, iclass 33, count 0 2006.201.18:29:39.95#ibcon#read 3, iclass 33, count 0 2006.201.18:29:39.95#ibcon#about to read 4, iclass 33, count 0 2006.201.18:29:39.95#ibcon#read 4, iclass 33, count 0 2006.201.18:29:39.95#ibcon#about to read 5, iclass 33, count 0 2006.201.18:29:39.95#ibcon#read 5, iclass 33, count 0 2006.201.18:29:39.95#ibcon#about to read 6, iclass 33, count 0 2006.201.18:29:39.95#ibcon#read 6, iclass 33, count 0 2006.201.18:29:39.95#ibcon#end of sib2, iclass 33, count 0 2006.201.18:29:39.95#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:29:39.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:29:39.95#ibcon#[27=USB\r\n] 2006.201.18:29:39.95#ibcon#*before write, iclass 33, count 0 2006.201.18:29:39.95#ibcon#enter sib2, iclass 33, count 0 2006.201.18:29:39.95#ibcon#flushed, iclass 33, count 0 2006.201.18:29:39.95#ibcon#about to write, iclass 33, count 0 2006.201.18:29:39.95#ibcon#wrote, iclass 33, count 0 2006.201.18:29:39.95#ibcon#about to read 3, iclass 33, count 0 2006.201.18:29:39.98#ibcon#read 3, iclass 33, count 0 2006.201.18:29:39.98#ibcon#about to read 4, iclass 33, count 0 2006.201.18:29:39.98#ibcon#read 4, iclass 33, count 0 2006.201.18:29:39.98#ibcon#about to read 5, iclass 33, count 0 2006.201.18:29:39.98#ibcon#read 5, iclass 33, count 0 2006.201.18:29:39.98#ibcon#about to read 6, iclass 33, count 0 2006.201.18:29:39.98#ibcon#read 6, iclass 33, count 0 2006.201.18:29:39.98#ibcon#end of sib2, iclass 33, count 0 2006.201.18:29:39.98#ibcon#*after write, iclass 33, count 0 2006.201.18:29:39.98#ibcon#*before return 0, iclass 33, count 0 2006.201.18:29:39.98#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:39.98#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:29:39.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:29:39.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:29:39.98$vck44/vblo=8,744.99 2006.201.18:29:39.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.18:29:39.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.18:29:39.98#ibcon#ireg 17 cls_cnt 0 2006.201.18:29:39.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:39.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:39.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:39.98#ibcon#enter wrdev, iclass 35, count 0 2006.201.18:29:39.98#ibcon#first serial, iclass 35, count 0 2006.201.18:29:39.98#ibcon#enter sib2, iclass 35, count 0 2006.201.18:29:39.98#ibcon#flushed, iclass 35, count 0 2006.201.18:29:39.98#ibcon#about to write, iclass 35, count 0 2006.201.18:29:39.98#ibcon#wrote, iclass 35, count 0 2006.201.18:29:39.98#ibcon#about to read 3, iclass 35, count 0 2006.201.18:29:40.00#ibcon#read 3, iclass 35, count 0 2006.201.18:29:40.00#ibcon#about to read 4, iclass 35, count 0 2006.201.18:29:40.00#ibcon#read 4, iclass 35, count 0 2006.201.18:29:40.00#ibcon#about to read 5, iclass 35, count 0 2006.201.18:29:40.00#ibcon#read 5, iclass 35, count 0 2006.201.18:29:40.00#ibcon#about to read 6, iclass 35, count 0 2006.201.18:29:40.00#ibcon#read 6, iclass 35, count 0 2006.201.18:29:40.00#ibcon#end of sib2, iclass 35, count 0 2006.201.18:29:40.00#ibcon#*mode == 0, iclass 35, count 0 2006.201.18:29:40.00#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.18:29:40.00#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:29:40.00#ibcon#*before write, iclass 35, count 0 2006.201.18:29:40.00#ibcon#enter sib2, iclass 35, count 0 2006.201.18:29:40.00#ibcon#flushed, iclass 35, count 0 2006.201.18:29:40.00#ibcon#about to write, iclass 35, count 0 2006.201.18:29:40.00#ibcon#wrote, iclass 35, count 0 2006.201.18:29:40.00#ibcon#about to read 3, iclass 35, count 0 2006.201.18:29:40.04#ibcon#read 3, iclass 35, count 0 2006.201.18:29:40.04#ibcon#about to read 4, iclass 35, count 0 2006.201.18:29:40.04#ibcon#read 4, iclass 35, count 0 2006.201.18:29:40.04#ibcon#about to read 5, iclass 35, count 0 2006.201.18:29:40.04#ibcon#read 5, iclass 35, count 0 2006.201.18:29:40.04#ibcon#about to read 6, iclass 35, count 0 2006.201.18:29:40.04#ibcon#read 6, iclass 35, count 0 2006.201.18:29:40.04#ibcon#end of sib2, iclass 35, count 0 2006.201.18:29:40.04#ibcon#*after write, iclass 35, count 0 2006.201.18:29:40.04#ibcon#*before return 0, iclass 35, count 0 2006.201.18:29:40.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:40.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:29:40.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.18:29:40.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.18:29:40.04$vck44/vb=8,4 2006.201.18:29:40.04#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.18:29:40.04#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.18:29:40.04#ibcon#ireg 11 cls_cnt 2 2006.201.18:29:40.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:40.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:40.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:40.10#ibcon#enter wrdev, iclass 37, count 2 2006.201.18:29:40.10#ibcon#first serial, iclass 37, count 2 2006.201.18:29:40.10#ibcon#enter sib2, iclass 37, count 2 2006.201.18:29:40.10#ibcon#flushed, iclass 37, count 2 2006.201.18:29:40.10#ibcon#about to write, iclass 37, count 2 2006.201.18:29:40.10#ibcon#wrote, iclass 37, count 2 2006.201.18:29:40.10#ibcon#about to read 3, iclass 37, count 2 2006.201.18:29:40.12#ibcon#read 3, iclass 37, count 2 2006.201.18:29:40.12#ibcon#about to read 4, iclass 37, count 2 2006.201.18:29:40.12#ibcon#read 4, iclass 37, count 2 2006.201.18:29:40.12#ibcon#about to read 5, iclass 37, count 2 2006.201.18:29:40.12#ibcon#read 5, iclass 37, count 2 2006.201.18:29:40.12#ibcon#about to read 6, iclass 37, count 2 2006.201.18:29:40.12#ibcon#read 6, iclass 37, count 2 2006.201.18:29:40.12#ibcon#end of sib2, iclass 37, count 2 2006.201.18:29:40.12#ibcon#*mode == 0, iclass 37, count 2 2006.201.18:29:40.12#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.18:29:40.12#ibcon#[27=AT08-04\r\n] 2006.201.18:29:40.12#ibcon#*before write, iclass 37, count 2 2006.201.18:29:40.12#ibcon#enter sib2, iclass 37, count 2 2006.201.18:29:40.12#ibcon#flushed, iclass 37, count 2 2006.201.18:29:40.12#ibcon#about to write, iclass 37, count 2 2006.201.18:29:40.12#ibcon#wrote, iclass 37, count 2 2006.201.18:29:40.12#ibcon#about to read 3, iclass 37, count 2 2006.201.18:29:40.15#ibcon#read 3, iclass 37, count 2 2006.201.18:29:40.15#ibcon#about to read 4, iclass 37, count 2 2006.201.18:29:40.15#ibcon#read 4, iclass 37, count 2 2006.201.18:29:40.15#ibcon#about to read 5, iclass 37, count 2 2006.201.18:29:40.15#ibcon#read 5, iclass 37, count 2 2006.201.18:29:40.15#ibcon#about to read 6, iclass 37, count 2 2006.201.18:29:40.15#ibcon#read 6, iclass 37, count 2 2006.201.18:29:40.15#ibcon#end of sib2, iclass 37, count 2 2006.201.18:29:40.15#ibcon#*after write, iclass 37, count 2 2006.201.18:29:40.15#ibcon#*before return 0, iclass 37, count 2 2006.201.18:29:40.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:40.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:29:40.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.18:29:40.15#ibcon#ireg 7 cls_cnt 0 2006.201.18:29:40.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:40.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:40.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:40.27#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:29:40.27#ibcon#first serial, iclass 37, count 0 2006.201.18:29:40.27#ibcon#enter sib2, iclass 37, count 0 2006.201.18:29:40.27#ibcon#flushed, iclass 37, count 0 2006.201.18:29:40.27#ibcon#about to write, iclass 37, count 0 2006.201.18:29:40.27#ibcon#wrote, iclass 37, count 0 2006.201.18:29:40.27#ibcon#about to read 3, iclass 37, count 0 2006.201.18:29:40.29#ibcon#read 3, iclass 37, count 0 2006.201.18:29:40.29#ibcon#about to read 4, iclass 37, count 0 2006.201.18:29:40.29#ibcon#read 4, iclass 37, count 0 2006.201.18:29:40.29#ibcon#about to read 5, iclass 37, count 0 2006.201.18:29:40.29#ibcon#read 5, iclass 37, count 0 2006.201.18:29:40.29#ibcon#about to read 6, iclass 37, count 0 2006.201.18:29:40.29#ibcon#read 6, iclass 37, count 0 2006.201.18:29:40.29#ibcon#end of sib2, iclass 37, count 0 2006.201.18:29:40.29#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:29:40.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:29:40.29#ibcon#[27=USB\r\n] 2006.201.18:29:40.29#ibcon#*before write, iclass 37, count 0 2006.201.18:29:40.29#ibcon#enter sib2, iclass 37, count 0 2006.201.18:29:40.29#ibcon#flushed, iclass 37, count 0 2006.201.18:29:40.29#ibcon#about to write, iclass 37, count 0 2006.201.18:29:40.29#ibcon#wrote, iclass 37, count 0 2006.201.18:29:40.29#ibcon#about to read 3, iclass 37, count 0 2006.201.18:29:40.32#ibcon#read 3, iclass 37, count 0 2006.201.18:29:40.32#ibcon#about to read 4, iclass 37, count 0 2006.201.18:29:40.32#ibcon#read 4, iclass 37, count 0 2006.201.18:29:40.32#ibcon#about to read 5, iclass 37, count 0 2006.201.18:29:40.32#ibcon#read 5, iclass 37, count 0 2006.201.18:29:40.32#ibcon#about to read 6, iclass 37, count 0 2006.201.18:29:40.32#ibcon#read 6, iclass 37, count 0 2006.201.18:29:40.32#ibcon#end of sib2, iclass 37, count 0 2006.201.18:29:40.32#ibcon#*after write, iclass 37, count 0 2006.201.18:29:40.32#ibcon#*before return 0, iclass 37, count 0 2006.201.18:29:40.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:40.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:29:40.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:29:40.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:29:40.32$vck44/vabw=wide 2006.201.18:29:40.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.18:29:40.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.18:29:40.32#ibcon#ireg 8 cls_cnt 0 2006.201.18:29:40.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:40.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:40.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:40.32#ibcon#enter wrdev, iclass 39, count 0 2006.201.18:29:40.32#ibcon#first serial, iclass 39, count 0 2006.201.18:29:40.32#ibcon#enter sib2, iclass 39, count 0 2006.201.18:29:40.32#ibcon#flushed, iclass 39, count 0 2006.201.18:29:40.32#ibcon#about to write, iclass 39, count 0 2006.201.18:29:40.32#ibcon#wrote, iclass 39, count 0 2006.201.18:29:40.32#ibcon#about to read 3, iclass 39, count 0 2006.201.18:29:40.34#ibcon#read 3, iclass 39, count 0 2006.201.18:29:40.34#ibcon#about to read 4, iclass 39, count 0 2006.201.18:29:40.34#ibcon#read 4, iclass 39, count 0 2006.201.18:29:40.34#ibcon#about to read 5, iclass 39, count 0 2006.201.18:29:40.34#ibcon#read 5, iclass 39, count 0 2006.201.18:29:40.34#ibcon#about to read 6, iclass 39, count 0 2006.201.18:29:40.34#ibcon#read 6, iclass 39, count 0 2006.201.18:29:40.34#ibcon#end of sib2, iclass 39, count 0 2006.201.18:29:40.34#ibcon#*mode == 0, iclass 39, count 0 2006.201.18:29:40.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.18:29:40.34#ibcon#[25=BW32\r\n] 2006.201.18:29:40.34#ibcon#*before write, iclass 39, count 0 2006.201.18:29:40.34#ibcon#enter sib2, iclass 39, count 0 2006.201.18:29:40.34#ibcon#flushed, iclass 39, count 0 2006.201.18:29:40.34#ibcon#about to write, iclass 39, count 0 2006.201.18:29:40.34#ibcon#wrote, iclass 39, count 0 2006.201.18:29:40.34#ibcon#about to read 3, iclass 39, count 0 2006.201.18:29:40.37#ibcon#read 3, iclass 39, count 0 2006.201.18:29:40.37#ibcon#about to read 4, iclass 39, count 0 2006.201.18:29:40.37#ibcon#read 4, iclass 39, count 0 2006.201.18:29:40.37#ibcon#about to read 5, iclass 39, count 0 2006.201.18:29:40.37#ibcon#read 5, iclass 39, count 0 2006.201.18:29:40.37#ibcon#about to read 6, iclass 39, count 0 2006.201.18:29:40.37#ibcon#read 6, iclass 39, count 0 2006.201.18:29:40.37#ibcon#end of sib2, iclass 39, count 0 2006.201.18:29:40.37#ibcon#*after write, iclass 39, count 0 2006.201.18:29:40.37#ibcon#*before return 0, iclass 39, count 0 2006.201.18:29:40.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:40.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:29:40.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.18:29:40.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.18:29:40.37$vck44/vbbw=wide 2006.201.18:29:40.37#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.18:29:40.37#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.18:29:40.37#ibcon#ireg 8 cls_cnt 0 2006.201.18:29:40.37#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:29:40.44#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:29:40.44#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:29:40.44#ibcon#enter wrdev, iclass 2, count 0 2006.201.18:29:40.44#ibcon#first serial, iclass 2, count 0 2006.201.18:29:40.44#ibcon#enter sib2, iclass 2, count 0 2006.201.18:29:40.44#ibcon#flushed, iclass 2, count 0 2006.201.18:29:40.44#ibcon#about to write, iclass 2, count 0 2006.201.18:29:40.44#ibcon#wrote, iclass 2, count 0 2006.201.18:29:40.44#ibcon#about to read 3, iclass 2, count 0 2006.201.18:29:40.46#ibcon#read 3, iclass 2, count 0 2006.201.18:29:40.46#ibcon#about to read 4, iclass 2, count 0 2006.201.18:29:40.46#ibcon#read 4, iclass 2, count 0 2006.201.18:29:40.46#ibcon#about to read 5, iclass 2, count 0 2006.201.18:29:40.46#ibcon#read 5, iclass 2, count 0 2006.201.18:29:40.46#ibcon#about to read 6, iclass 2, count 0 2006.201.18:29:40.46#ibcon#read 6, iclass 2, count 0 2006.201.18:29:40.46#ibcon#end of sib2, iclass 2, count 0 2006.201.18:29:40.46#ibcon#*mode == 0, iclass 2, count 0 2006.201.18:29:40.46#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.18:29:40.46#ibcon#[27=BW32\r\n] 2006.201.18:29:40.46#ibcon#*before write, iclass 2, count 0 2006.201.18:29:40.46#ibcon#enter sib2, iclass 2, count 0 2006.201.18:29:40.46#ibcon#flushed, iclass 2, count 0 2006.201.18:29:40.46#ibcon#about to write, iclass 2, count 0 2006.201.18:29:40.46#ibcon#wrote, iclass 2, count 0 2006.201.18:29:40.46#ibcon#about to read 3, iclass 2, count 0 2006.201.18:29:40.49#ibcon#read 3, iclass 2, count 0 2006.201.18:29:40.49#ibcon#about to read 4, iclass 2, count 0 2006.201.18:29:40.49#ibcon#read 4, iclass 2, count 0 2006.201.18:29:40.49#ibcon#about to read 5, iclass 2, count 0 2006.201.18:29:40.49#ibcon#read 5, iclass 2, count 0 2006.201.18:29:40.49#ibcon#about to read 6, iclass 2, count 0 2006.201.18:29:40.49#ibcon#read 6, iclass 2, count 0 2006.201.18:29:40.49#ibcon#end of sib2, iclass 2, count 0 2006.201.18:29:40.49#ibcon#*after write, iclass 2, count 0 2006.201.18:29:40.49#ibcon#*before return 0, iclass 2, count 0 2006.201.18:29:40.49#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:29:40.49#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:29:40.49#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.18:29:40.49#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.18:29:40.49$setupk4/ifdk4 2006.201.18:29:40.49$ifdk4/lo= 2006.201.18:29:40.49$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:29:40.49$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:29:40.49$ifdk4/patch= 2006.201.18:29:40.49$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:29:40.49$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:29:40.49$setupk4/!*+20s 2006.201.18:29:43.49#abcon#<5=/04 0.7 1.4 20.501001002.0\r\n> 2006.201.18:29:43.51#abcon#{5=INTERFACE CLEAR} 2006.201.18:29:43.57#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:29:53.66#abcon#<5=/04 0.7 1.3 20.501001002.0\r\n> 2006.201.18:29:53.68#abcon#{5=INTERFACE CLEAR} 2006.201.18:29:53.74#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:29:54.95$setupk4/"tpicd 2006.201.18:29:54.95$setupk4/echo=off 2006.201.18:29:54.95$setupk4/xlog=off 2006.201.18:29:54.95:!2006.201.18:38:28 2006.201.18:30:11.14#trakl#Source acquired 2006.201.18:30:13.14#flagr#flagr/antenna,acquired 2006.201.18:38:28.00:preob 2006.201.18:38:29.14/onsource/TRACKING 2006.201.18:38:29.14:!2006.201.18:38:38 2006.201.18:38:38.00:"tape 2006.201.18:38:38.00:"st=record 2006.201.18:38:38.00:data_valid=on 2006.201.18:38:38.00:midob 2006.201.18:38:38.14/onsource/TRACKING 2006.201.18:38:38.14/wx/20.50,1002.1,100 2006.201.18:38:38.29/cable/+6.4778E-03 2006.201.18:38:39.38/va/01,08,usb,yes,42,44 2006.201.18:38:39.38/va/02,07,usb,yes,45,46 2006.201.18:38:39.38/va/03,08,usb,yes,41,42 2006.201.18:38:39.38/va/04,07,usb,yes,46,49 2006.201.18:38:39.38/va/05,04,usb,yes,41,42 2006.201.18:38:39.38/va/06,05,usb,yes,41,41 2006.201.18:38:39.38/va/07,05,usb,yes,40,42 2006.201.18:38:39.38/va/08,04,usb,yes,40,48 2006.201.18:38:39.61/valo/01,524.99,yes,locked 2006.201.18:38:39.61/valo/02,534.99,yes,locked 2006.201.18:38:39.61/valo/03,564.99,yes,locked 2006.201.18:38:39.61/valo/04,624.99,yes,locked 2006.201.18:38:39.61/valo/05,734.99,yes,locked 2006.201.18:38:39.61/valo/06,814.99,yes,locked 2006.201.18:38:39.61/valo/07,864.99,yes,locked 2006.201.18:38:39.61/valo/08,884.99,yes,locked 2006.201.18:38:40.70/vb/01,04,usb,yes,30,28 2006.201.18:38:40.70/vb/02,05,usb,yes,28,28 2006.201.18:38:40.70/vb/03,04,usb,yes,29,32 2006.201.18:38:40.70/vb/04,05,usb,yes,29,28 2006.201.18:38:40.70/vb/05,04,usb,yes,26,28 2006.201.18:38:40.70/vb/06,04,usb,yes,30,27 2006.201.18:38:40.70/vb/07,04,usb,yes,30,30 2006.201.18:38:40.70/vb/08,04,usb,yes,28,31 2006.201.18:38:40.94/vblo/01,629.99,yes,locked 2006.201.18:38:40.94/vblo/02,634.99,yes,locked 2006.201.18:38:40.94/vblo/03,649.99,yes,locked 2006.201.18:38:40.94/vblo/04,679.99,yes,locked 2006.201.18:38:40.94/vblo/05,709.99,yes,locked 2006.201.18:38:40.94/vblo/06,719.99,yes,locked 2006.201.18:38:40.94/vblo/07,734.99,yes,locked 2006.201.18:38:40.94/vblo/08,744.99,yes,locked 2006.201.18:38:41.09/vabw/8 2006.201.18:38:41.24/vbbw/8 2006.201.18:38:41.33/xfe/off,on,15.2 2006.201.18:38:41.72/ifatt/23,28,28,28 2006.201.18:38:42.06/fmout-gps/S +4.53E-07 2006.201.18:38:42.10:!2006.201.18:39:18 2006.201.18:39:18.00:data_valid=off 2006.201.18:39:18.00:"et 2006.201.18:39:18.00:!+3s 2006.201.18:39:21.02:"tape 2006.201.18:39:21.02:postob 2006.201.18:39:21.12/cable/+6.4794E-03 2006.201.18:39:21.12/wx/20.50,1002.1,100 2006.201.18:39:21.18/fmout-gps/S +4.53E-07 2006.201.18:39:21.18:scan_name=201-1840,jd0607,170 2006.201.18:39:21.18:source=3c446,222547.26,-045701.4,2000.0,cw 2006.201.18:39:23.14#flagr#flagr/antenna,new-source 2006.201.18:39:23.14:checkk5 2006.201.18:39:23.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:39:23.92/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:39:24.32/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:39:24.69/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:39:25.06/chk_obsdata//k5ts1/T2011838??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.18:39:25.42/chk_obsdata//k5ts2/T2011838??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.18:39:25.79/chk_obsdata//k5ts3/T2011838??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.18:39:26.15/chk_obsdata//k5ts4/T2011838??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.18:39:26.85/k5log//k5ts1_log_newline 2006.201.18:39:27.53/k5log//k5ts2_log_newline 2006.201.18:39:28.22/k5log//k5ts3_log_newline 2006.201.18:39:28.90/k5log//k5ts4_log_newline 2006.201.18:39:28.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:39:28.93:setupk4=1 2006.201.18:39:28.93$setupk4/echo=on 2006.201.18:39:28.93$setupk4/pcalon 2006.201.18:39:28.93$pcalon/"no phase cal control is implemented here 2006.201.18:39:28.93$setupk4/"tpicd=stop 2006.201.18:39:28.93$setupk4/"rec=synch_on 2006.201.18:39:28.93$setupk4/"rec_mode=128 2006.201.18:39:28.93$setupk4/!* 2006.201.18:39:28.93$setupk4/recpk4 2006.201.18:39:28.93$recpk4/recpatch= 2006.201.18:39:28.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:39:28.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:39:28.93$setupk4/vck44 2006.201.18:39:28.93$vck44/valo=1,524.99 2006.201.18:39:28.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.18:39:28.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.18:39:28.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:28.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:28.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:28.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:28.93#ibcon#enter wrdev, iclass 21, count 0 2006.201.18:39:28.93#ibcon#first serial, iclass 21, count 0 2006.201.18:39:28.93#ibcon#enter sib2, iclass 21, count 0 2006.201.18:39:28.93#ibcon#flushed, iclass 21, count 0 2006.201.18:39:28.93#ibcon#about to write, iclass 21, count 0 2006.201.18:39:28.93#ibcon#wrote, iclass 21, count 0 2006.201.18:39:28.93#ibcon#about to read 3, iclass 21, count 0 2006.201.18:39:28.95#ibcon#read 3, iclass 21, count 0 2006.201.18:39:28.95#ibcon#about to read 4, iclass 21, count 0 2006.201.18:39:28.95#ibcon#read 4, iclass 21, count 0 2006.201.18:39:28.95#ibcon#about to read 5, iclass 21, count 0 2006.201.18:39:28.95#ibcon#read 5, iclass 21, count 0 2006.201.18:39:28.95#ibcon#about to read 6, iclass 21, count 0 2006.201.18:39:28.95#ibcon#read 6, iclass 21, count 0 2006.201.18:39:28.95#ibcon#end of sib2, iclass 21, count 0 2006.201.18:39:28.95#ibcon#*mode == 0, iclass 21, count 0 2006.201.18:39:28.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.18:39:28.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:39:28.95#ibcon#*before write, iclass 21, count 0 2006.201.18:39:28.95#ibcon#enter sib2, iclass 21, count 0 2006.201.18:39:28.95#ibcon#flushed, iclass 21, count 0 2006.201.18:39:28.95#ibcon#about to write, iclass 21, count 0 2006.201.18:39:28.95#ibcon#wrote, iclass 21, count 0 2006.201.18:39:28.95#ibcon#about to read 3, iclass 21, count 0 2006.201.18:39:29.00#ibcon#read 3, iclass 21, count 0 2006.201.18:39:29.00#ibcon#about to read 4, iclass 21, count 0 2006.201.18:39:29.00#ibcon#read 4, iclass 21, count 0 2006.201.18:39:29.00#ibcon#about to read 5, iclass 21, count 0 2006.201.18:39:29.00#ibcon#read 5, iclass 21, count 0 2006.201.18:39:29.00#ibcon#about to read 6, iclass 21, count 0 2006.201.18:39:29.00#ibcon#read 6, iclass 21, count 0 2006.201.18:39:29.00#ibcon#end of sib2, iclass 21, count 0 2006.201.18:39:29.00#ibcon#*after write, iclass 21, count 0 2006.201.18:39:29.00#ibcon#*before return 0, iclass 21, count 0 2006.201.18:39:29.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:29.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:29.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.18:39:29.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.18:39:29.00$vck44/va=1,8 2006.201.18:39:29.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.18:39:29.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.18:39:29.00#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:29.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:29.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:29.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:29.00#ibcon#enter wrdev, iclass 23, count 2 2006.201.18:39:29.00#ibcon#first serial, iclass 23, count 2 2006.201.18:39:29.00#ibcon#enter sib2, iclass 23, count 2 2006.201.18:39:29.00#ibcon#flushed, iclass 23, count 2 2006.201.18:39:29.00#ibcon#about to write, iclass 23, count 2 2006.201.18:39:29.00#ibcon#wrote, iclass 23, count 2 2006.201.18:39:29.00#ibcon#about to read 3, iclass 23, count 2 2006.201.18:39:29.02#ibcon#read 3, iclass 23, count 2 2006.201.18:39:29.02#ibcon#about to read 4, iclass 23, count 2 2006.201.18:39:29.02#ibcon#read 4, iclass 23, count 2 2006.201.18:39:29.02#ibcon#about to read 5, iclass 23, count 2 2006.201.18:39:29.02#ibcon#read 5, iclass 23, count 2 2006.201.18:39:29.02#ibcon#about to read 6, iclass 23, count 2 2006.201.18:39:29.02#ibcon#read 6, iclass 23, count 2 2006.201.18:39:29.02#ibcon#end of sib2, iclass 23, count 2 2006.201.18:39:29.02#ibcon#*mode == 0, iclass 23, count 2 2006.201.18:39:29.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.18:39:29.02#ibcon#[25=AT01-08\r\n] 2006.201.18:39:29.02#ibcon#*before write, iclass 23, count 2 2006.201.18:39:29.02#ibcon#enter sib2, iclass 23, count 2 2006.201.18:39:29.02#ibcon#flushed, iclass 23, count 2 2006.201.18:39:29.02#ibcon#about to write, iclass 23, count 2 2006.201.18:39:29.02#ibcon#wrote, iclass 23, count 2 2006.201.18:39:29.02#ibcon#about to read 3, iclass 23, count 2 2006.201.18:39:29.05#ibcon#read 3, iclass 23, count 2 2006.201.18:39:29.05#ibcon#about to read 4, iclass 23, count 2 2006.201.18:39:29.05#ibcon#read 4, iclass 23, count 2 2006.201.18:39:29.05#ibcon#about to read 5, iclass 23, count 2 2006.201.18:39:29.05#ibcon#read 5, iclass 23, count 2 2006.201.18:39:29.05#ibcon#about to read 6, iclass 23, count 2 2006.201.18:39:29.05#ibcon#read 6, iclass 23, count 2 2006.201.18:39:29.05#ibcon#end of sib2, iclass 23, count 2 2006.201.18:39:29.05#ibcon#*after write, iclass 23, count 2 2006.201.18:39:29.05#ibcon#*before return 0, iclass 23, count 2 2006.201.18:39:29.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:29.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:29.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.18:39:29.05#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:29.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:29.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:29.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:29.17#ibcon#enter wrdev, iclass 23, count 0 2006.201.18:39:29.17#ibcon#first serial, iclass 23, count 0 2006.201.18:39:29.17#ibcon#enter sib2, iclass 23, count 0 2006.201.18:39:29.17#ibcon#flushed, iclass 23, count 0 2006.201.18:39:29.17#ibcon#about to write, iclass 23, count 0 2006.201.18:39:29.17#ibcon#wrote, iclass 23, count 0 2006.201.18:39:29.17#ibcon#about to read 3, iclass 23, count 0 2006.201.18:39:29.19#ibcon#read 3, iclass 23, count 0 2006.201.18:39:29.19#ibcon#about to read 4, iclass 23, count 0 2006.201.18:39:29.19#ibcon#read 4, iclass 23, count 0 2006.201.18:39:29.19#ibcon#about to read 5, iclass 23, count 0 2006.201.18:39:29.19#ibcon#read 5, iclass 23, count 0 2006.201.18:39:29.19#ibcon#about to read 6, iclass 23, count 0 2006.201.18:39:29.19#ibcon#read 6, iclass 23, count 0 2006.201.18:39:29.19#ibcon#end of sib2, iclass 23, count 0 2006.201.18:39:29.19#ibcon#*mode == 0, iclass 23, count 0 2006.201.18:39:29.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.18:39:29.19#ibcon#[25=USB\r\n] 2006.201.18:39:29.19#ibcon#*before write, iclass 23, count 0 2006.201.18:39:29.19#ibcon#enter sib2, iclass 23, count 0 2006.201.18:39:29.19#ibcon#flushed, iclass 23, count 0 2006.201.18:39:29.19#ibcon#about to write, iclass 23, count 0 2006.201.18:39:29.19#ibcon#wrote, iclass 23, count 0 2006.201.18:39:29.19#ibcon#about to read 3, iclass 23, count 0 2006.201.18:39:29.22#ibcon#read 3, iclass 23, count 0 2006.201.18:39:29.22#ibcon#about to read 4, iclass 23, count 0 2006.201.18:39:29.22#ibcon#read 4, iclass 23, count 0 2006.201.18:39:29.22#ibcon#about to read 5, iclass 23, count 0 2006.201.18:39:29.22#ibcon#read 5, iclass 23, count 0 2006.201.18:39:29.22#ibcon#about to read 6, iclass 23, count 0 2006.201.18:39:29.22#ibcon#read 6, iclass 23, count 0 2006.201.18:39:29.22#ibcon#end of sib2, iclass 23, count 0 2006.201.18:39:29.22#ibcon#*after write, iclass 23, count 0 2006.201.18:39:29.22#ibcon#*before return 0, iclass 23, count 0 2006.201.18:39:29.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:29.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:29.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.18:39:29.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.18:39:29.22$vck44/valo=2,534.99 2006.201.18:39:29.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.18:39:29.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.18:39:29.22#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:29.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:29.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:29.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:29.22#ibcon#enter wrdev, iclass 25, count 0 2006.201.18:39:29.22#ibcon#first serial, iclass 25, count 0 2006.201.18:39:29.22#ibcon#enter sib2, iclass 25, count 0 2006.201.18:39:29.22#ibcon#flushed, iclass 25, count 0 2006.201.18:39:29.22#ibcon#about to write, iclass 25, count 0 2006.201.18:39:29.22#ibcon#wrote, iclass 25, count 0 2006.201.18:39:29.22#ibcon#about to read 3, iclass 25, count 0 2006.201.18:39:29.24#ibcon#read 3, iclass 25, count 0 2006.201.18:39:29.24#ibcon#about to read 4, iclass 25, count 0 2006.201.18:39:29.24#ibcon#read 4, iclass 25, count 0 2006.201.18:39:29.24#ibcon#about to read 5, iclass 25, count 0 2006.201.18:39:29.24#ibcon#read 5, iclass 25, count 0 2006.201.18:39:29.24#ibcon#about to read 6, iclass 25, count 0 2006.201.18:39:29.24#ibcon#read 6, iclass 25, count 0 2006.201.18:39:29.24#ibcon#end of sib2, iclass 25, count 0 2006.201.18:39:29.24#ibcon#*mode == 0, iclass 25, count 0 2006.201.18:39:29.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.18:39:29.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:39:29.24#ibcon#*before write, iclass 25, count 0 2006.201.18:39:29.24#ibcon#enter sib2, iclass 25, count 0 2006.201.18:39:29.24#ibcon#flushed, iclass 25, count 0 2006.201.18:39:29.24#ibcon#about to write, iclass 25, count 0 2006.201.18:39:29.24#ibcon#wrote, iclass 25, count 0 2006.201.18:39:29.24#ibcon#about to read 3, iclass 25, count 0 2006.201.18:39:29.28#ibcon#read 3, iclass 25, count 0 2006.201.18:39:29.28#ibcon#about to read 4, iclass 25, count 0 2006.201.18:39:29.28#ibcon#read 4, iclass 25, count 0 2006.201.18:39:29.28#ibcon#about to read 5, iclass 25, count 0 2006.201.18:39:29.28#ibcon#read 5, iclass 25, count 0 2006.201.18:39:29.28#ibcon#about to read 6, iclass 25, count 0 2006.201.18:39:29.28#ibcon#read 6, iclass 25, count 0 2006.201.18:39:29.28#ibcon#end of sib2, iclass 25, count 0 2006.201.18:39:29.28#ibcon#*after write, iclass 25, count 0 2006.201.18:39:29.28#ibcon#*before return 0, iclass 25, count 0 2006.201.18:39:29.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:29.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:29.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.18:39:29.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.18:39:29.28$vck44/va=2,7 2006.201.18:39:29.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.18:39:29.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.18:39:29.28#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:29.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:29.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:29.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:29.34#ibcon#enter wrdev, iclass 27, count 2 2006.201.18:39:29.34#ibcon#first serial, iclass 27, count 2 2006.201.18:39:29.34#ibcon#enter sib2, iclass 27, count 2 2006.201.18:39:29.34#ibcon#flushed, iclass 27, count 2 2006.201.18:39:29.34#ibcon#about to write, iclass 27, count 2 2006.201.18:39:29.34#ibcon#wrote, iclass 27, count 2 2006.201.18:39:29.34#ibcon#about to read 3, iclass 27, count 2 2006.201.18:39:29.36#ibcon#read 3, iclass 27, count 2 2006.201.18:39:29.36#ibcon#about to read 4, iclass 27, count 2 2006.201.18:39:29.36#ibcon#read 4, iclass 27, count 2 2006.201.18:39:29.36#ibcon#about to read 5, iclass 27, count 2 2006.201.18:39:29.36#ibcon#read 5, iclass 27, count 2 2006.201.18:39:29.36#ibcon#about to read 6, iclass 27, count 2 2006.201.18:39:29.36#ibcon#read 6, iclass 27, count 2 2006.201.18:39:29.36#ibcon#end of sib2, iclass 27, count 2 2006.201.18:39:29.36#ibcon#*mode == 0, iclass 27, count 2 2006.201.18:39:29.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.18:39:29.36#ibcon#[25=AT02-07\r\n] 2006.201.18:39:29.36#ibcon#*before write, iclass 27, count 2 2006.201.18:39:29.36#ibcon#enter sib2, iclass 27, count 2 2006.201.18:39:29.36#ibcon#flushed, iclass 27, count 2 2006.201.18:39:29.36#ibcon#about to write, iclass 27, count 2 2006.201.18:39:29.36#ibcon#wrote, iclass 27, count 2 2006.201.18:39:29.36#ibcon#about to read 3, iclass 27, count 2 2006.201.18:39:29.39#ibcon#read 3, iclass 27, count 2 2006.201.18:39:29.39#ibcon#about to read 4, iclass 27, count 2 2006.201.18:39:29.39#ibcon#read 4, iclass 27, count 2 2006.201.18:39:29.39#ibcon#about to read 5, iclass 27, count 2 2006.201.18:39:29.39#ibcon#read 5, iclass 27, count 2 2006.201.18:39:29.39#ibcon#about to read 6, iclass 27, count 2 2006.201.18:39:29.39#ibcon#read 6, iclass 27, count 2 2006.201.18:39:29.39#ibcon#end of sib2, iclass 27, count 2 2006.201.18:39:29.39#ibcon#*after write, iclass 27, count 2 2006.201.18:39:29.39#ibcon#*before return 0, iclass 27, count 2 2006.201.18:39:29.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:29.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:29.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.18:39:29.39#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:29.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:29.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:29.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:29.51#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:39:29.51#ibcon#first serial, iclass 27, count 0 2006.201.18:39:29.51#ibcon#enter sib2, iclass 27, count 0 2006.201.18:39:29.51#ibcon#flushed, iclass 27, count 0 2006.201.18:39:29.51#ibcon#about to write, iclass 27, count 0 2006.201.18:39:29.51#ibcon#wrote, iclass 27, count 0 2006.201.18:39:29.51#ibcon#about to read 3, iclass 27, count 0 2006.201.18:39:29.53#ibcon#read 3, iclass 27, count 0 2006.201.18:39:29.53#ibcon#about to read 4, iclass 27, count 0 2006.201.18:39:29.53#ibcon#read 4, iclass 27, count 0 2006.201.18:39:29.53#ibcon#about to read 5, iclass 27, count 0 2006.201.18:39:29.53#ibcon#read 5, iclass 27, count 0 2006.201.18:39:29.53#ibcon#about to read 6, iclass 27, count 0 2006.201.18:39:29.53#ibcon#read 6, iclass 27, count 0 2006.201.18:39:29.53#ibcon#end of sib2, iclass 27, count 0 2006.201.18:39:29.53#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:39:29.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:39:29.53#ibcon#[25=USB\r\n] 2006.201.18:39:29.53#ibcon#*before write, iclass 27, count 0 2006.201.18:39:29.53#ibcon#enter sib2, iclass 27, count 0 2006.201.18:39:29.53#ibcon#flushed, iclass 27, count 0 2006.201.18:39:29.53#ibcon#about to write, iclass 27, count 0 2006.201.18:39:29.53#ibcon#wrote, iclass 27, count 0 2006.201.18:39:29.53#ibcon#about to read 3, iclass 27, count 0 2006.201.18:39:29.56#ibcon#read 3, iclass 27, count 0 2006.201.18:39:29.56#ibcon#about to read 4, iclass 27, count 0 2006.201.18:39:29.56#ibcon#read 4, iclass 27, count 0 2006.201.18:39:29.56#ibcon#about to read 5, iclass 27, count 0 2006.201.18:39:29.56#ibcon#read 5, iclass 27, count 0 2006.201.18:39:29.56#ibcon#about to read 6, iclass 27, count 0 2006.201.18:39:29.56#ibcon#read 6, iclass 27, count 0 2006.201.18:39:29.56#ibcon#end of sib2, iclass 27, count 0 2006.201.18:39:29.56#ibcon#*after write, iclass 27, count 0 2006.201.18:39:29.56#ibcon#*before return 0, iclass 27, count 0 2006.201.18:39:29.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:29.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:29.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:39:29.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:39:29.56$vck44/valo=3,564.99 2006.201.18:39:29.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.18:39:29.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.18:39:29.56#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:29.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:29.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:29.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:29.56#ibcon#enter wrdev, iclass 29, count 0 2006.201.18:39:29.56#ibcon#first serial, iclass 29, count 0 2006.201.18:39:29.56#ibcon#enter sib2, iclass 29, count 0 2006.201.18:39:29.56#ibcon#flushed, iclass 29, count 0 2006.201.18:39:29.56#ibcon#about to write, iclass 29, count 0 2006.201.18:39:29.56#ibcon#wrote, iclass 29, count 0 2006.201.18:39:29.56#ibcon#about to read 3, iclass 29, count 0 2006.201.18:39:29.58#ibcon#read 3, iclass 29, count 0 2006.201.18:39:29.58#ibcon#about to read 4, iclass 29, count 0 2006.201.18:39:29.58#ibcon#read 4, iclass 29, count 0 2006.201.18:39:29.58#ibcon#about to read 5, iclass 29, count 0 2006.201.18:39:29.58#ibcon#read 5, iclass 29, count 0 2006.201.18:39:29.58#ibcon#about to read 6, iclass 29, count 0 2006.201.18:39:29.58#ibcon#read 6, iclass 29, count 0 2006.201.18:39:29.58#ibcon#end of sib2, iclass 29, count 0 2006.201.18:39:29.58#ibcon#*mode == 0, iclass 29, count 0 2006.201.18:39:29.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.18:39:29.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:39:29.58#ibcon#*before write, iclass 29, count 0 2006.201.18:39:29.58#ibcon#enter sib2, iclass 29, count 0 2006.201.18:39:29.58#ibcon#flushed, iclass 29, count 0 2006.201.18:39:29.58#ibcon#about to write, iclass 29, count 0 2006.201.18:39:29.58#ibcon#wrote, iclass 29, count 0 2006.201.18:39:29.58#ibcon#about to read 3, iclass 29, count 0 2006.201.18:39:29.63#ibcon#read 3, iclass 29, count 0 2006.201.18:39:29.63#ibcon#about to read 4, iclass 29, count 0 2006.201.18:39:29.63#ibcon#read 4, iclass 29, count 0 2006.201.18:39:29.63#ibcon#about to read 5, iclass 29, count 0 2006.201.18:39:29.63#ibcon#read 5, iclass 29, count 0 2006.201.18:39:29.63#ibcon#about to read 6, iclass 29, count 0 2006.201.18:39:29.63#ibcon#read 6, iclass 29, count 0 2006.201.18:39:29.63#ibcon#end of sib2, iclass 29, count 0 2006.201.18:39:29.63#ibcon#*after write, iclass 29, count 0 2006.201.18:39:29.63#ibcon#*before return 0, iclass 29, count 0 2006.201.18:39:29.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:29.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:29.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.18:39:29.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.18:39:29.63$vck44/va=3,8 2006.201.18:39:29.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.18:39:29.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.18:39:29.63#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:29.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:29.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:29.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:29.68#ibcon#enter wrdev, iclass 31, count 2 2006.201.18:39:29.68#ibcon#first serial, iclass 31, count 2 2006.201.18:39:29.68#ibcon#enter sib2, iclass 31, count 2 2006.201.18:39:29.68#ibcon#flushed, iclass 31, count 2 2006.201.18:39:29.68#ibcon#about to write, iclass 31, count 2 2006.201.18:39:29.68#ibcon#wrote, iclass 31, count 2 2006.201.18:39:29.68#ibcon#about to read 3, iclass 31, count 2 2006.201.18:39:29.70#ibcon#read 3, iclass 31, count 2 2006.201.18:39:29.70#ibcon#about to read 4, iclass 31, count 2 2006.201.18:39:29.70#ibcon#read 4, iclass 31, count 2 2006.201.18:39:29.70#ibcon#about to read 5, iclass 31, count 2 2006.201.18:39:29.70#ibcon#read 5, iclass 31, count 2 2006.201.18:39:29.70#ibcon#about to read 6, iclass 31, count 2 2006.201.18:39:29.70#ibcon#read 6, iclass 31, count 2 2006.201.18:39:29.70#ibcon#end of sib2, iclass 31, count 2 2006.201.18:39:29.70#ibcon#*mode == 0, iclass 31, count 2 2006.201.18:39:29.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.18:39:29.70#ibcon#[25=AT03-08\r\n] 2006.201.18:39:29.70#ibcon#*before write, iclass 31, count 2 2006.201.18:39:29.70#ibcon#enter sib2, iclass 31, count 2 2006.201.18:39:29.70#ibcon#flushed, iclass 31, count 2 2006.201.18:39:29.70#ibcon#about to write, iclass 31, count 2 2006.201.18:39:29.70#ibcon#wrote, iclass 31, count 2 2006.201.18:39:29.70#ibcon#about to read 3, iclass 31, count 2 2006.201.18:39:29.73#ibcon#read 3, iclass 31, count 2 2006.201.18:39:29.73#ibcon#about to read 4, iclass 31, count 2 2006.201.18:39:29.73#ibcon#read 4, iclass 31, count 2 2006.201.18:39:29.73#ibcon#about to read 5, iclass 31, count 2 2006.201.18:39:29.73#ibcon#read 5, iclass 31, count 2 2006.201.18:39:29.73#ibcon#about to read 6, iclass 31, count 2 2006.201.18:39:29.73#ibcon#read 6, iclass 31, count 2 2006.201.18:39:29.73#ibcon#end of sib2, iclass 31, count 2 2006.201.18:39:29.73#ibcon#*after write, iclass 31, count 2 2006.201.18:39:29.73#ibcon#*before return 0, iclass 31, count 2 2006.201.18:39:29.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:29.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:29.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.18:39:29.73#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:29.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:29.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:29.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:29.85#ibcon#enter wrdev, iclass 31, count 0 2006.201.18:39:29.85#ibcon#first serial, iclass 31, count 0 2006.201.18:39:29.85#ibcon#enter sib2, iclass 31, count 0 2006.201.18:39:29.85#ibcon#flushed, iclass 31, count 0 2006.201.18:39:29.85#ibcon#about to write, iclass 31, count 0 2006.201.18:39:29.85#ibcon#wrote, iclass 31, count 0 2006.201.18:39:29.85#ibcon#about to read 3, iclass 31, count 0 2006.201.18:39:29.87#ibcon#read 3, iclass 31, count 0 2006.201.18:39:29.87#ibcon#about to read 4, iclass 31, count 0 2006.201.18:39:29.87#ibcon#read 4, iclass 31, count 0 2006.201.18:39:29.87#ibcon#about to read 5, iclass 31, count 0 2006.201.18:39:29.87#ibcon#read 5, iclass 31, count 0 2006.201.18:39:29.87#ibcon#about to read 6, iclass 31, count 0 2006.201.18:39:29.87#ibcon#read 6, iclass 31, count 0 2006.201.18:39:29.87#ibcon#end of sib2, iclass 31, count 0 2006.201.18:39:29.87#ibcon#*mode == 0, iclass 31, count 0 2006.201.18:39:29.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.18:39:29.87#ibcon#[25=USB\r\n] 2006.201.18:39:29.87#ibcon#*before write, iclass 31, count 0 2006.201.18:39:29.87#ibcon#enter sib2, iclass 31, count 0 2006.201.18:39:29.87#ibcon#flushed, iclass 31, count 0 2006.201.18:39:29.87#ibcon#about to write, iclass 31, count 0 2006.201.18:39:29.87#ibcon#wrote, iclass 31, count 0 2006.201.18:39:29.87#ibcon#about to read 3, iclass 31, count 0 2006.201.18:39:29.90#ibcon#read 3, iclass 31, count 0 2006.201.18:39:29.90#ibcon#about to read 4, iclass 31, count 0 2006.201.18:39:29.90#ibcon#read 4, iclass 31, count 0 2006.201.18:39:29.90#ibcon#about to read 5, iclass 31, count 0 2006.201.18:39:29.90#ibcon#read 5, iclass 31, count 0 2006.201.18:39:29.90#ibcon#about to read 6, iclass 31, count 0 2006.201.18:39:29.90#ibcon#read 6, iclass 31, count 0 2006.201.18:39:29.90#ibcon#end of sib2, iclass 31, count 0 2006.201.18:39:29.90#ibcon#*after write, iclass 31, count 0 2006.201.18:39:29.90#ibcon#*before return 0, iclass 31, count 0 2006.201.18:39:29.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:29.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:29.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.18:39:29.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.18:39:29.90$vck44/valo=4,624.99 2006.201.18:39:29.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.18:39:29.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.18:39:29.90#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:29.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:29.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:29.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:29.90#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:39:29.90#ibcon#first serial, iclass 33, count 0 2006.201.18:39:29.90#ibcon#enter sib2, iclass 33, count 0 2006.201.18:39:29.90#ibcon#flushed, iclass 33, count 0 2006.201.18:39:29.90#ibcon#about to write, iclass 33, count 0 2006.201.18:39:29.90#ibcon#wrote, iclass 33, count 0 2006.201.18:39:29.90#ibcon#about to read 3, iclass 33, count 0 2006.201.18:39:29.92#ibcon#read 3, iclass 33, count 0 2006.201.18:39:29.92#ibcon#about to read 4, iclass 33, count 0 2006.201.18:39:29.92#ibcon#read 4, iclass 33, count 0 2006.201.18:39:29.92#ibcon#about to read 5, iclass 33, count 0 2006.201.18:39:29.92#ibcon#read 5, iclass 33, count 0 2006.201.18:39:29.92#ibcon#about to read 6, iclass 33, count 0 2006.201.18:39:29.92#ibcon#read 6, iclass 33, count 0 2006.201.18:39:29.92#ibcon#end of sib2, iclass 33, count 0 2006.201.18:39:29.92#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:39:29.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:39:29.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:39:29.92#ibcon#*before write, iclass 33, count 0 2006.201.18:39:29.92#ibcon#enter sib2, iclass 33, count 0 2006.201.18:39:29.92#ibcon#flushed, iclass 33, count 0 2006.201.18:39:29.92#ibcon#about to write, iclass 33, count 0 2006.201.18:39:29.92#ibcon#wrote, iclass 33, count 0 2006.201.18:39:29.92#ibcon#about to read 3, iclass 33, count 0 2006.201.18:39:29.97#ibcon#read 3, iclass 33, count 0 2006.201.18:39:29.97#ibcon#about to read 4, iclass 33, count 0 2006.201.18:39:29.97#ibcon#read 4, iclass 33, count 0 2006.201.18:39:29.97#ibcon#about to read 5, iclass 33, count 0 2006.201.18:39:29.97#ibcon#read 5, iclass 33, count 0 2006.201.18:39:29.97#ibcon#about to read 6, iclass 33, count 0 2006.201.18:39:29.97#ibcon#read 6, iclass 33, count 0 2006.201.18:39:29.97#ibcon#end of sib2, iclass 33, count 0 2006.201.18:39:29.97#ibcon#*after write, iclass 33, count 0 2006.201.18:39:29.97#ibcon#*before return 0, iclass 33, count 0 2006.201.18:39:29.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:29.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:29.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:39:29.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:39:29.97$vck44/va=4,7 2006.201.18:39:29.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.18:39:29.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.18:39:29.97#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:29.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:30.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:30.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:30.02#ibcon#enter wrdev, iclass 35, count 2 2006.201.18:39:30.02#ibcon#first serial, iclass 35, count 2 2006.201.18:39:30.02#ibcon#enter sib2, iclass 35, count 2 2006.201.18:39:30.02#ibcon#flushed, iclass 35, count 2 2006.201.18:39:30.02#ibcon#about to write, iclass 35, count 2 2006.201.18:39:30.02#ibcon#wrote, iclass 35, count 2 2006.201.18:39:30.02#ibcon#about to read 3, iclass 35, count 2 2006.201.18:39:30.04#ibcon#read 3, iclass 35, count 2 2006.201.18:39:30.04#ibcon#about to read 4, iclass 35, count 2 2006.201.18:39:30.04#ibcon#read 4, iclass 35, count 2 2006.201.18:39:30.04#ibcon#about to read 5, iclass 35, count 2 2006.201.18:39:30.04#ibcon#read 5, iclass 35, count 2 2006.201.18:39:30.04#ibcon#about to read 6, iclass 35, count 2 2006.201.18:39:30.04#ibcon#read 6, iclass 35, count 2 2006.201.18:39:30.04#ibcon#end of sib2, iclass 35, count 2 2006.201.18:39:30.04#ibcon#*mode == 0, iclass 35, count 2 2006.201.18:39:30.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.18:39:30.04#ibcon#[25=AT04-07\r\n] 2006.201.18:39:30.04#ibcon#*before write, iclass 35, count 2 2006.201.18:39:30.04#ibcon#enter sib2, iclass 35, count 2 2006.201.18:39:30.04#ibcon#flushed, iclass 35, count 2 2006.201.18:39:30.04#ibcon#about to write, iclass 35, count 2 2006.201.18:39:30.04#ibcon#wrote, iclass 35, count 2 2006.201.18:39:30.04#ibcon#about to read 3, iclass 35, count 2 2006.201.18:39:30.07#ibcon#read 3, iclass 35, count 2 2006.201.18:39:30.07#ibcon#about to read 4, iclass 35, count 2 2006.201.18:39:30.07#ibcon#read 4, iclass 35, count 2 2006.201.18:39:30.07#ibcon#about to read 5, iclass 35, count 2 2006.201.18:39:30.07#ibcon#read 5, iclass 35, count 2 2006.201.18:39:30.07#ibcon#about to read 6, iclass 35, count 2 2006.201.18:39:30.07#ibcon#read 6, iclass 35, count 2 2006.201.18:39:30.07#ibcon#end of sib2, iclass 35, count 2 2006.201.18:39:30.07#ibcon#*after write, iclass 35, count 2 2006.201.18:39:30.07#ibcon#*before return 0, iclass 35, count 2 2006.201.18:39:30.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:30.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:30.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.18:39:30.07#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:30.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:30.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:30.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:30.19#ibcon#enter wrdev, iclass 35, count 0 2006.201.18:39:30.19#ibcon#first serial, iclass 35, count 0 2006.201.18:39:30.19#ibcon#enter sib2, iclass 35, count 0 2006.201.18:39:30.19#ibcon#flushed, iclass 35, count 0 2006.201.18:39:30.19#ibcon#about to write, iclass 35, count 0 2006.201.18:39:30.19#ibcon#wrote, iclass 35, count 0 2006.201.18:39:30.19#ibcon#about to read 3, iclass 35, count 0 2006.201.18:39:30.22#ibcon#read 3, iclass 35, count 0 2006.201.18:39:30.22#ibcon#about to read 4, iclass 35, count 0 2006.201.18:39:30.22#ibcon#read 4, iclass 35, count 0 2006.201.18:39:30.22#ibcon#about to read 5, iclass 35, count 0 2006.201.18:39:30.22#ibcon#read 5, iclass 35, count 0 2006.201.18:39:30.22#ibcon#about to read 6, iclass 35, count 0 2006.201.18:39:30.22#ibcon#read 6, iclass 35, count 0 2006.201.18:39:30.22#ibcon#end of sib2, iclass 35, count 0 2006.201.18:39:30.22#ibcon#*mode == 0, iclass 35, count 0 2006.201.18:39:30.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.18:39:30.22#ibcon#[25=USB\r\n] 2006.201.18:39:30.22#ibcon#*before write, iclass 35, count 0 2006.201.18:39:30.22#ibcon#enter sib2, iclass 35, count 0 2006.201.18:39:30.22#ibcon#flushed, iclass 35, count 0 2006.201.18:39:30.22#ibcon#about to write, iclass 35, count 0 2006.201.18:39:30.22#ibcon#wrote, iclass 35, count 0 2006.201.18:39:30.22#ibcon#about to read 3, iclass 35, count 0 2006.201.18:39:30.25#ibcon#read 3, iclass 35, count 0 2006.201.18:39:30.25#ibcon#about to read 4, iclass 35, count 0 2006.201.18:39:30.25#ibcon#read 4, iclass 35, count 0 2006.201.18:39:30.25#ibcon#about to read 5, iclass 35, count 0 2006.201.18:39:30.25#ibcon#read 5, iclass 35, count 0 2006.201.18:39:30.25#ibcon#about to read 6, iclass 35, count 0 2006.201.18:39:30.25#ibcon#read 6, iclass 35, count 0 2006.201.18:39:30.25#ibcon#end of sib2, iclass 35, count 0 2006.201.18:39:30.25#ibcon#*after write, iclass 35, count 0 2006.201.18:39:30.25#ibcon#*before return 0, iclass 35, count 0 2006.201.18:39:30.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:30.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:30.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.18:39:30.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.18:39:30.25$vck44/valo=5,734.99 2006.201.18:39:30.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.18:39:30.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.18:39:30.25#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:30.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:30.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:30.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:30.25#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:39:30.25#ibcon#first serial, iclass 37, count 0 2006.201.18:39:30.25#ibcon#enter sib2, iclass 37, count 0 2006.201.18:39:30.25#ibcon#flushed, iclass 37, count 0 2006.201.18:39:30.25#ibcon#about to write, iclass 37, count 0 2006.201.18:39:30.25#ibcon#wrote, iclass 37, count 0 2006.201.18:39:30.25#ibcon#about to read 3, iclass 37, count 0 2006.201.18:39:30.27#ibcon#read 3, iclass 37, count 0 2006.201.18:39:30.27#ibcon#about to read 4, iclass 37, count 0 2006.201.18:39:30.27#ibcon#read 4, iclass 37, count 0 2006.201.18:39:30.27#ibcon#about to read 5, iclass 37, count 0 2006.201.18:39:30.27#ibcon#read 5, iclass 37, count 0 2006.201.18:39:30.27#ibcon#about to read 6, iclass 37, count 0 2006.201.18:39:30.27#ibcon#read 6, iclass 37, count 0 2006.201.18:39:30.27#ibcon#end of sib2, iclass 37, count 0 2006.201.18:39:30.27#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:39:30.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:39:30.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:39:30.27#ibcon#*before write, iclass 37, count 0 2006.201.18:39:30.27#ibcon#enter sib2, iclass 37, count 0 2006.201.18:39:30.27#ibcon#flushed, iclass 37, count 0 2006.201.18:39:30.27#ibcon#about to write, iclass 37, count 0 2006.201.18:39:30.27#ibcon#wrote, iclass 37, count 0 2006.201.18:39:30.27#ibcon#about to read 3, iclass 37, count 0 2006.201.18:39:30.31#ibcon#read 3, iclass 37, count 0 2006.201.18:39:30.31#ibcon#about to read 4, iclass 37, count 0 2006.201.18:39:30.31#ibcon#read 4, iclass 37, count 0 2006.201.18:39:30.31#ibcon#about to read 5, iclass 37, count 0 2006.201.18:39:30.31#ibcon#read 5, iclass 37, count 0 2006.201.18:39:30.31#ibcon#about to read 6, iclass 37, count 0 2006.201.18:39:30.31#ibcon#read 6, iclass 37, count 0 2006.201.18:39:30.31#ibcon#end of sib2, iclass 37, count 0 2006.201.18:39:30.31#ibcon#*after write, iclass 37, count 0 2006.201.18:39:30.31#ibcon#*before return 0, iclass 37, count 0 2006.201.18:39:30.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:30.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:30.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:39:30.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:39:30.31$vck44/va=5,4 2006.201.18:39:30.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.18:39:30.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.18:39:30.31#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:30.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:30.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:30.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:30.37#ibcon#enter wrdev, iclass 39, count 2 2006.201.18:39:30.37#ibcon#first serial, iclass 39, count 2 2006.201.18:39:30.37#ibcon#enter sib2, iclass 39, count 2 2006.201.18:39:30.37#ibcon#flushed, iclass 39, count 2 2006.201.18:39:30.37#ibcon#about to write, iclass 39, count 2 2006.201.18:39:30.37#ibcon#wrote, iclass 39, count 2 2006.201.18:39:30.37#ibcon#about to read 3, iclass 39, count 2 2006.201.18:39:30.39#ibcon#read 3, iclass 39, count 2 2006.201.18:39:30.39#ibcon#about to read 4, iclass 39, count 2 2006.201.18:39:30.39#ibcon#read 4, iclass 39, count 2 2006.201.18:39:30.39#ibcon#about to read 5, iclass 39, count 2 2006.201.18:39:30.39#ibcon#read 5, iclass 39, count 2 2006.201.18:39:30.39#ibcon#about to read 6, iclass 39, count 2 2006.201.18:39:30.39#ibcon#read 6, iclass 39, count 2 2006.201.18:39:30.39#ibcon#end of sib2, iclass 39, count 2 2006.201.18:39:30.39#ibcon#*mode == 0, iclass 39, count 2 2006.201.18:39:30.39#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.18:39:30.39#ibcon#[25=AT05-04\r\n] 2006.201.18:39:30.39#ibcon#*before write, iclass 39, count 2 2006.201.18:39:30.39#ibcon#enter sib2, iclass 39, count 2 2006.201.18:39:30.39#ibcon#flushed, iclass 39, count 2 2006.201.18:39:30.39#ibcon#about to write, iclass 39, count 2 2006.201.18:39:30.39#ibcon#wrote, iclass 39, count 2 2006.201.18:39:30.39#ibcon#about to read 3, iclass 39, count 2 2006.201.18:39:30.42#ibcon#read 3, iclass 39, count 2 2006.201.18:39:30.42#ibcon#about to read 4, iclass 39, count 2 2006.201.18:39:30.42#ibcon#read 4, iclass 39, count 2 2006.201.18:39:30.42#ibcon#about to read 5, iclass 39, count 2 2006.201.18:39:30.42#ibcon#read 5, iclass 39, count 2 2006.201.18:39:30.42#ibcon#about to read 6, iclass 39, count 2 2006.201.18:39:30.42#ibcon#read 6, iclass 39, count 2 2006.201.18:39:30.42#ibcon#end of sib2, iclass 39, count 2 2006.201.18:39:30.42#ibcon#*after write, iclass 39, count 2 2006.201.18:39:30.42#ibcon#*before return 0, iclass 39, count 2 2006.201.18:39:30.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:30.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:30.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.18:39:30.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:30.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:30.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:30.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:30.54#ibcon#enter wrdev, iclass 39, count 0 2006.201.18:39:30.54#ibcon#first serial, iclass 39, count 0 2006.201.18:39:30.54#ibcon#enter sib2, iclass 39, count 0 2006.201.18:39:30.54#ibcon#flushed, iclass 39, count 0 2006.201.18:39:30.54#ibcon#about to write, iclass 39, count 0 2006.201.18:39:30.54#ibcon#wrote, iclass 39, count 0 2006.201.18:39:30.54#ibcon#about to read 3, iclass 39, count 0 2006.201.18:39:30.56#ibcon#read 3, iclass 39, count 0 2006.201.18:39:30.56#ibcon#about to read 4, iclass 39, count 0 2006.201.18:39:30.56#ibcon#read 4, iclass 39, count 0 2006.201.18:39:30.56#ibcon#about to read 5, iclass 39, count 0 2006.201.18:39:30.56#ibcon#read 5, iclass 39, count 0 2006.201.18:39:30.56#ibcon#about to read 6, iclass 39, count 0 2006.201.18:39:30.56#ibcon#read 6, iclass 39, count 0 2006.201.18:39:30.56#ibcon#end of sib2, iclass 39, count 0 2006.201.18:39:30.56#ibcon#*mode == 0, iclass 39, count 0 2006.201.18:39:30.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.18:39:30.56#ibcon#[25=USB\r\n] 2006.201.18:39:30.56#ibcon#*before write, iclass 39, count 0 2006.201.18:39:30.56#ibcon#enter sib2, iclass 39, count 0 2006.201.18:39:30.56#ibcon#flushed, iclass 39, count 0 2006.201.18:39:30.56#ibcon#about to write, iclass 39, count 0 2006.201.18:39:30.56#ibcon#wrote, iclass 39, count 0 2006.201.18:39:30.56#ibcon#about to read 3, iclass 39, count 0 2006.201.18:39:30.59#ibcon#read 3, iclass 39, count 0 2006.201.18:39:30.59#ibcon#about to read 4, iclass 39, count 0 2006.201.18:39:30.59#ibcon#read 4, iclass 39, count 0 2006.201.18:39:30.59#ibcon#about to read 5, iclass 39, count 0 2006.201.18:39:30.59#ibcon#read 5, iclass 39, count 0 2006.201.18:39:30.59#ibcon#about to read 6, iclass 39, count 0 2006.201.18:39:30.59#ibcon#read 6, iclass 39, count 0 2006.201.18:39:30.59#ibcon#end of sib2, iclass 39, count 0 2006.201.18:39:30.59#ibcon#*after write, iclass 39, count 0 2006.201.18:39:30.59#ibcon#*before return 0, iclass 39, count 0 2006.201.18:39:30.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:30.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:30.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.18:39:30.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.18:39:30.59$vck44/valo=6,814.99 2006.201.18:39:30.59#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.18:39:30.59#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.18:39:30.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:30.59#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:30.59#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:30.59#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:30.59#ibcon#enter wrdev, iclass 2, count 0 2006.201.18:39:30.59#ibcon#first serial, iclass 2, count 0 2006.201.18:39:30.59#ibcon#enter sib2, iclass 2, count 0 2006.201.18:39:30.59#ibcon#flushed, iclass 2, count 0 2006.201.18:39:30.59#ibcon#about to write, iclass 2, count 0 2006.201.18:39:30.59#ibcon#wrote, iclass 2, count 0 2006.201.18:39:30.59#ibcon#about to read 3, iclass 2, count 0 2006.201.18:39:30.61#ibcon#read 3, iclass 2, count 0 2006.201.18:39:30.61#ibcon#about to read 4, iclass 2, count 0 2006.201.18:39:30.61#ibcon#read 4, iclass 2, count 0 2006.201.18:39:30.61#ibcon#about to read 5, iclass 2, count 0 2006.201.18:39:30.61#ibcon#read 5, iclass 2, count 0 2006.201.18:39:30.61#ibcon#about to read 6, iclass 2, count 0 2006.201.18:39:30.61#ibcon#read 6, iclass 2, count 0 2006.201.18:39:30.61#ibcon#end of sib2, iclass 2, count 0 2006.201.18:39:30.61#ibcon#*mode == 0, iclass 2, count 0 2006.201.18:39:30.61#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.18:39:30.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:39:30.61#ibcon#*before write, iclass 2, count 0 2006.201.18:39:30.61#ibcon#enter sib2, iclass 2, count 0 2006.201.18:39:30.61#ibcon#flushed, iclass 2, count 0 2006.201.18:39:30.61#ibcon#about to write, iclass 2, count 0 2006.201.18:39:30.61#ibcon#wrote, iclass 2, count 0 2006.201.18:39:30.61#ibcon#about to read 3, iclass 2, count 0 2006.201.18:39:30.65#ibcon#read 3, iclass 2, count 0 2006.201.18:39:30.65#ibcon#about to read 4, iclass 2, count 0 2006.201.18:39:30.65#ibcon#read 4, iclass 2, count 0 2006.201.18:39:30.65#ibcon#about to read 5, iclass 2, count 0 2006.201.18:39:30.65#ibcon#read 5, iclass 2, count 0 2006.201.18:39:30.65#ibcon#about to read 6, iclass 2, count 0 2006.201.18:39:30.65#ibcon#read 6, iclass 2, count 0 2006.201.18:39:30.65#ibcon#end of sib2, iclass 2, count 0 2006.201.18:39:30.65#ibcon#*after write, iclass 2, count 0 2006.201.18:39:30.65#ibcon#*before return 0, iclass 2, count 0 2006.201.18:39:30.65#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:30.65#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:30.65#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.18:39:30.65#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.18:39:30.65$vck44/va=6,5 2006.201.18:39:30.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.18:39:30.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.18:39:30.65#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:30.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:30.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:30.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:30.71#ibcon#enter wrdev, iclass 5, count 2 2006.201.18:39:30.71#ibcon#first serial, iclass 5, count 2 2006.201.18:39:30.71#ibcon#enter sib2, iclass 5, count 2 2006.201.18:39:30.71#ibcon#flushed, iclass 5, count 2 2006.201.18:39:30.71#ibcon#about to write, iclass 5, count 2 2006.201.18:39:30.71#ibcon#wrote, iclass 5, count 2 2006.201.18:39:30.71#ibcon#about to read 3, iclass 5, count 2 2006.201.18:39:30.73#ibcon#read 3, iclass 5, count 2 2006.201.18:39:30.73#ibcon#about to read 4, iclass 5, count 2 2006.201.18:39:30.73#ibcon#read 4, iclass 5, count 2 2006.201.18:39:30.73#ibcon#about to read 5, iclass 5, count 2 2006.201.18:39:30.73#ibcon#read 5, iclass 5, count 2 2006.201.18:39:30.73#ibcon#about to read 6, iclass 5, count 2 2006.201.18:39:30.73#ibcon#read 6, iclass 5, count 2 2006.201.18:39:30.73#ibcon#end of sib2, iclass 5, count 2 2006.201.18:39:30.73#ibcon#*mode == 0, iclass 5, count 2 2006.201.18:39:30.73#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.18:39:30.73#ibcon#[25=AT06-05\r\n] 2006.201.18:39:30.73#ibcon#*before write, iclass 5, count 2 2006.201.18:39:30.73#ibcon#enter sib2, iclass 5, count 2 2006.201.18:39:30.73#ibcon#flushed, iclass 5, count 2 2006.201.18:39:30.73#ibcon#about to write, iclass 5, count 2 2006.201.18:39:30.73#ibcon#wrote, iclass 5, count 2 2006.201.18:39:30.73#ibcon#about to read 3, iclass 5, count 2 2006.201.18:39:30.76#ibcon#read 3, iclass 5, count 2 2006.201.18:39:30.76#ibcon#about to read 4, iclass 5, count 2 2006.201.18:39:30.76#ibcon#read 4, iclass 5, count 2 2006.201.18:39:30.76#ibcon#about to read 5, iclass 5, count 2 2006.201.18:39:30.76#ibcon#read 5, iclass 5, count 2 2006.201.18:39:30.76#ibcon#about to read 6, iclass 5, count 2 2006.201.18:39:30.76#ibcon#read 6, iclass 5, count 2 2006.201.18:39:30.76#ibcon#end of sib2, iclass 5, count 2 2006.201.18:39:30.76#ibcon#*after write, iclass 5, count 2 2006.201.18:39:30.76#ibcon#*before return 0, iclass 5, count 2 2006.201.18:39:30.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:30.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:30.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.18:39:30.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:30.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:30.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:30.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:30.88#ibcon#enter wrdev, iclass 5, count 0 2006.201.18:39:30.88#ibcon#first serial, iclass 5, count 0 2006.201.18:39:30.88#ibcon#enter sib2, iclass 5, count 0 2006.201.18:39:30.88#ibcon#flushed, iclass 5, count 0 2006.201.18:39:30.88#ibcon#about to write, iclass 5, count 0 2006.201.18:39:30.88#ibcon#wrote, iclass 5, count 0 2006.201.18:39:30.88#ibcon#about to read 3, iclass 5, count 0 2006.201.18:39:30.90#ibcon#read 3, iclass 5, count 0 2006.201.18:39:30.90#ibcon#about to read 4, iclass 5, count 0 2006.201.18:39:30.90#ibcon#read 4, iclass 5, count 0 2006.201.18:39:30.90#ibcon#about to read 5, iclass 5, count 0 2006.201.18:39:30.90#ibcon#read 5, iclass 5, count 0 2006.201.18:39:30.90#ibcon#about to read 6, iclass 5, count 0 2006.201.18:39:30.90#ibcon#read 6, iclass 5, count 0 2006.201.18:39:30.90#ibcon#end of sib2, iclass 5, count 0 2006.201.18:39:30.90#ibcon#*mode == 0, iclass 5, count 0 2006.201.18:39:30.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.18:39:30.90#ibcon#[25=USB\r\n] 2006.201.18:39:30.90#ibcon#*before write, iclass 5, count 0 2006.201.18:39:30.90#ibcon#enter sib2, iclass 5, count 0 2006.201.18:39:30.90#ibcon#flushed, iclass 5, count 0 2006.201.18:39:30.90#ibcon#about to write, iclass 5, count 0 2006.201.18:39:30.90#ibcon#wrote, iclass 5, count 0 2006.201.18:39:30.90#ibcon#about to read 3, iclass 5, count 0 2006.201.18:39:30.93#ibcon#read 3, iclass 5, count 0 2006.201.18:39:30.93#ibcon#about to read 4, iclass 5, count 0 2006.201.18:39:30.93#ibcon#read 4, iclass 5, count 0 2006.201.18:39:30.93#ibcon#about to read 5, iclass 5, count 0 2006.201.18:39:30.93#ibcon#read 5, iclass 5, count 0 2006.201.18:39:30.93#ibcon#about to read 6, iclass 5, count 0 2006.201.18:39:30.93#ibcon#read 6, iclass 5, count 0 2006.201.18:39:30.93#ibcon#end of sib2, iclass 5, count 0 2006.201.18:39:30.93#ibcon#*after write, iclass 5, count 0 2006.201.18:39:30.93#ibcon#*before return 0, iclass 5, count 0 2006.201.18:39:30.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:30.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:30.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.18:39:30.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.18:39:30.93$vck44/valo=7,864.99 2006.201.18:39:30.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.18:39:30.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.18:39:30.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:30.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:30.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:30.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:30.93#ibcon#enter wrdev, iclass 7, count 0 2006.201.18:39:30.93#ibcon#first serial, iclass 7, count 0 2006.201.18:39:30.93#ibcon#enter sib2, iclass 7, count 0 2006.201.18:39:30.93#ibcon#flushed, iclass 7, count 0 2006.201.18:39:30.93#ibcon#about to write, iclass 7, count 0 2006.201.18:39:30.93#ibcon#wrote, iclass 7, count 0 2006.201.18:39:30.93#ibcon#about to read 3, iclass 7, count 0 2006.201.18:39:30.95#ibcon#read 3, iclass 7, count 0 2006.201.18:39:30.95#ibcon#about to read 4, iclass 7, count 0 2006.201.18:39:30.95#ibcon#read 4, iclass 7, count 0 2006.201.18:39:30.95#ibcon#about to read 5, iclass 7, count 0 2006.201.18:39:30.95#ibcon#read 5, iclass 7, count 0 2006.201.18:39:30.95#ibcon#about to read 6, iclass 7, count 0 2006.201.18:39:30.95#ibcon#read 6, iclass 7, count 0 2006.201.18:39:30.95#ibcon#end of sib2, iclass 7, count 0 2006.201.18:39:30.95#ibcon#*mode == 0, iclass 7, count 0 2006.201.18:39:30.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.18:39:30.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:39:30.95#ibcon#*before write, iclass 7, count 0 2006.201.18:39:30.95#ibcon#enter sib2, iclass 7, count 0 2006.201.18:39:30.95#ibcon#flushed, iclass 7, count 0 2006.201.18:39:30.95#ibcon#about to write, iclass 7, count 0 2006.201.18:39:30.95#ibcon#wrote, iclass 7, count 0 2006.201.18:39:30.95#ibcon#about to read 3, iclass 7, count 0 2006.201.18:39:31.00#ibcon#read 3, iclass 7, count 0 2006.201.18:39:31.00#ibcon#about to read 4, iclass 7, count 0 2006.201.18:39:31.00#ibcon#read 4, iclass 7, count 0 2006.201.18:39:31.00#ibcon#about to read 5, iclass 7, count 0 2006.201.18:39:31.00#ibcon#read 5, iclass 7, count 0 2006.201.18:39:31.00#ibcon#about to read 6, iclass 7, count 0 2006.201.18:39:31.00#ibcon#read 6, iclass 7, count 0 2006.201.18:39:31.00#ibcon#end of sib2, iclass 7, count 0 2006.201.18:39:31.00#ibcon#*after write, iclass 7, count 0 2006.201.18:39:31.00#ibcon#*before return 0, iclass 7, count 0 2006.201.18:39:31.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:31.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:31.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.18:39:31.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.18:39:31.00$vck44/va=7,5 2006.201.18:39:31.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.18:39:31.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.18:39:31.00#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:31.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:31.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:31.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:31.05#ibcon#enter wrdev, iclass 11, count 2 2006.201.18:39:31.05#ibcon#first serial, iclass 11, count 2 2006.201.18:39:31.05#ibcon#enter sib2, iclass 11, count 2 2006.201.18:39:31.05#ibcon#flushed, iclass 11, count 2 2006.201.18:39:31.05#ibcon#about to write, iclass 11, count 2 2006.201.18:39:31.05#ibcon#wrote, iclass 11, count 2 2006.201.18:39:31.05#ibcon#about to read 3, iclass 11, count 2 2006.201.18:39:31.07#ibcon#read 3, iclass 11, count 2 2006.201.18:39:31.07#ibcon#about to read 4, iclass 11, count 2 2006.201.18:39:31.07#ibcon#read 4, iclass 11, count 2 2006.201.18:39:31.07#ibcon#about to read 5, iclass 11, count 2 2006.201.18:39:31.07#ibcon#read 5, iclass 11, count 2 2006.201.18:39:31.07#ibcon#about to read 6, iclass 11, count 2 2006.201.18:39:31.07#ibcon#read 6, iclass 11, count 2 2006.201.18:39:31.07#ibcon#end of sib2, iclass 11, count 2 2006.201.18:39:31.07#ibcon#*mode == 0, iclass 11, count 2 2006.201.18:39:31.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.18:39:31.07#ibcon#[25=AT07-05\r\n] 2006.201.18:39:31.07#ibcon#*before write, iclass 11, count 2 2006.201.18:39:31.07#ibcon#enter sib2, iclass 11, count 2 2006.201.18:39:31.07#ibcon#flushed, iclass 11, count 2 2006.201.18:39:31.07#ibcon#about to write, iclass 11, count 2 2006.201.18:39:31.07#ibcon#wrote, iclass 11, count 2 2006.201.18:39:31.07#ibcon#about to read 3, iclass 11, count 2 2006.201.18:39:31.10#ibcon#read 3, iclass 11, count 2 2006.201.18:39:31.10#ibcon#about to read 4, iclass 11, count 2 2006.201.18:39:31.10#ibcon#read 4, iclass 11, count 2 2006.201.18:39:31.10#ibcon#about to read 5, iclass 11, count 2 2006.201.18:39:31.10#ibcon#read 5, iclass 11, count 2 2006.201.18:39:31.10#ibcon#about to read 6, iclass 11, count 2 2006.201.18:39:31.10#ibcon#read 6, iclass 11, count 2 2006.201.18:39:31.10#ibcon#end of sib2, iclass 11, count 2 2006.201.18:39:31.10#ibcon#*after write, iclass 11, count 2 2006.201.18:39:31.10#ibcon#*before return 0, iclass 11, count 2 2006.201.18:39:31.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:31.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:31.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.18:39:31.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:31.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:31.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:31.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:31.22#ibcon#enter wrdev, iclass 11, count 0 2006.201.18:39:31.22#ibcon#first serial, iclass 11, count 0 2006.201.18:39:31.22#ibcon#enter sib2, iclass 11, count 0 2006.201.18:39:31.22#ibcon#flushed, iclass 11, count 0 2006.201.18:39:31.22#ibcon#about to write, iclass 11, count 0 2006.201.18:39:31.22#ibcon#wrote, iclass 11, count 0 2006.201.18:39:31.22#ibcon#about to read 3, iclass 11, count 0 2006.201.18:39:31.24#ibcon#read 3, iclass 11, count 0 2006.201.18:39:31.24#ibcon#about to read 4, iclass 11, count 0 2006.201.18:39:31.24#ibcon#read 4, iclass 11, count 0 2006.201.18:39:31.24#ibcon#about to read 5, iclass 11, count 0 2006.201.18:39:31.24#ibcon#read 5, iclass 11, count 0 2006.201.18:39:31.24#ibcon#about to read 6, iclass 11, count 0 2006.201.18:39:31.24#ibcon#read 6, iclass 11, count 0 2006.201.18:39:31.24#ibcon#end of sib2, iclass 11, count 0 2006.201.18:39:31.24#ibcon#*mode == 0, iclass 11, count 0 2006.201.18:39:31.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.18:39:31.24#ibcon#[25=USB\r\n] 2006.201.18:39:31.24#ibcon#*before write, iclass 11, count 0 2006.201.18:39:31.24#ibcon#enter sib2, iclass 11, count 0 2006.201.18:39:31.24#ibcon#flushed, iclass 11, count 0 2006.201.18:39:31.24#ibcon#about to write, iclass 11, count 0 2006.201.18:39:31.24#ibcon#wrote, iclass 11, count 0 2006.201.18:39:31.24#ibcon#about to read 3, iclass 11, count 0 2006.201.18:39:31.27#ibcon#read 3, iclass 11, count 0 2006.201.18:39:31.27#ibcon#about to read 4, iclass 11, count 0 2006.201.18:39:31.27#ibcon#read 4, iclass 11, count 0 2006.201.18:39:31.27#ibcon#about to read 5, iclass 11, count 0 2006.201.18:39:31.27#ibcon#read 5, iclass 11, count 0 2006.201.18:39:31.27#ibcon#about to read 6, iclass 11, count 0 2006.201.18:39:31.27#ibcon#read 6, iclass 11, count 0 2006.201.18:39:31.27#ibcon#end of sib2, iclass 11, count 0 2006.201.18:39:31.27#ibcon#*after write, iclass 11, count 0 2006.201.18:39:31.27#ibcon#*before return 0, iclass 11, count 0 2006.201.18:39:31.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:31.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:31.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.18:39:31.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.18:39:31.27$vck44/valo=8,884.99 2006.201.18:39:31.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.18:39:31.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.18:39:31.27#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:31.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:31.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:31.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:31.27#ibcon#enter wrdev, iclass 13, count 0 2006.201.18:39:31.27#ibcon#first serial, iclass 13, count 0 2006.201.18:39:31.27#ibcon#enter sib2, iclass 13, count 0 2006.201.18:39:31.27#ibcon#flushed, iclass 13, count 0 2006.201.18:39:31.27#ibcon#about to write, iclass 13, count 0 2006.201.18:39:31.27#ibcon#wrote, iclass 13, count 0 2006.201.18:39:31.27#ibcon#about to read 3, iclass 13, count 0 2006.201.18:39:31.29#ibcon#read 3, iclass 13, count 0 2006.201.18:39:31.29#ibcon#about to read 4, iclass 13, count 0 2006.201.18:39:31.29#ibcon#read 4, iclass 13, count 0 2006.201.18:39:31.29#ibcon#about to read 5, iclass 13, count 0 2006.201.18:39:31.29#ibcon#read 5, iclass 13, count 0 2006.201.18:39:31.29#ibcon#about to read 6, iclass 13, count 0 2006.201.18:39:31.29#ibcon#read 6, iclass 13, count 0 2006.201.18:39:31.29#ibcon#end of sib2, iclass 13, count 0 2006.201.18:39:31.29#ibcon#*mode == 0, iclass 13, count 0 2006.201.18:39:31.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.18:39:31.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:39:31.29#ibcon#*before write, iclass 13, count 0 2006.201.18:39:31.29#ibcon#enter sib2, iclass 13, count 0 2006.201.18:39:31.29#ibcon#flushed, iclass 13, count 0 2006.201.18:39:31.29#ibcon#about to write, iclass 13, count 0 2006.201.18:39:31.29#ibcon#wrote, iclass 13, count 0 2006.201.18:39:31.29#ibcon#about to read 3, iclass 13, count 0 2006.201.18:39:31.33#ibcon#read 3, iclass 13, count 0 2006.201.18:39:31.33#ibcon#about to read 4, iclass 13, count 0 2006.201.18:39:31.33#ibcon#read 4, iclass 13, count 0 2006.201.18:39:31.33#ibcon#about to read 5, iclass 13, count 0 2006.201.18:39:31.33#ibcon#read 5, iclass 13, count 0 2006.201.18:39:31.33#ibcon#about to read 6, iclass 13, count 0 2006.201.18:39:31.33#ibcon#read 6, iclass 13, count 0 2006.201.18:39:31.33#ibcon#end of sib2, iclass 13, count 0 2006.201.18:39:31.33#ibcon#*after write, iclass 13, count 0 2006.201.18:39:31.33#ibcon#*before return 0, iclass 13, count 0 2006.201.18:39:31.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:31.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:31.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.18:39:31.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.18:39:31.33$vck44/va=8,4 2006.201.18:39:31.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.18:39:31.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.18:39:31.33#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:31.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:39:31.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:39:31.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:39:31.39#ibcon#enter wrdev, iclass 15, count 2 2006.201.18:39:31.39#ibcon#first serial, iclass 15, count 2 2006.201.18:39:31.39#ibcon#enter sib2, iclass 15, count 2 2006.201.18:39:31.39#ibcon#flushed, iclass 15, count 2 2006.201.18:39:31.39#ibcon#about to write, iclass 15, count 2 2006.201.18:39:31.39#ibcon#wrote, iclass 15, count 2 2006.201.18:39:31.39#ibcon#about to read 3, iclass 15, count 2 2006.201.18:39:31.41#ibcon#read 3, iclass 15, count 2 2006.201.18:39:31.41#ibcon#about to read 4, iclass 15, count 2 2006.201.18:39:31.41#ibcon#read 4, iclass 15, count 2 2006.201.18:39:31.41#ibcon#about to read 5, iclass 15, count 2 2006.201.18:39:31.41#ibcon#read 5, iclass 15, count 2 2006.201.18:39:31.41#ibcon#about to read 6, iclass 15, count 2 2006.201.18:39:31.41#ibcon#read 6, iclass 15, count 2 2006.201.18:39:31.41#ibcon#end of sib2, iclass 15, count 2 2006.201.18:39:31.41#ibcon#*mode == 0, iclass 15, count 2 2006.201.18:39:31.41#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.18:39:31.41#ibcon#[25=AT08-04\r\n] 2006.201.18:39:31.41#ibcon#*before write, iclass 15, count 2 2006.201.18:39:31.41#ibcon#enter sib2, iclass 15, count 2 2006.201.18:39:31.41#ibcon#flushed, iclass 15, count 2 2006.201.18:39:31.41#ibcon#about to write, iclass 15, count 2 2006.201.18:39:31.41#ibcon#wrote, iclass 15, count 2 2006.201.18:39:31.41#ibcon#about to read 3, iclass 15, count 2 2006.201.18:39:31.44#ibcon#read 3, iclass 15, count 2 2006.201.18:39:31.44#ibcon#about to read 4, iclass 15, count 2 2006.201.18:39:31.44#ibcon#read 4, iclass 15, count 2 2006.201.18:39:31.44#ibcon#about to read 5, iclass 15, count 2 2006.201.18:39:31.44#ibcon#read 5, iclass 15, count 2 2006.201.18:39:31.44#ibcon#about to read 6, iclass 15, count 2 2006.201.18:39:31.44#ibcon#read 6, iclass 15, count 2 2006.201.18:39:31.44#ibcon#end of sib2, iclass 15, count 2 2006.201.18:39:31.44#ibcon#*after write, iclass 15, count 2 2006.201.18:39:31.44#ibcon#*before return 0, iclass 15, count 2 2006.201.18:39:31.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:39:31.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.18:39:31.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.18:39:31.44#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:31.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:39:31.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:39:31.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:39:31.56#ibcon#enter wrdev, iclass 15, count 0 2006.201.18:39:31.56#ibcon#first serial, iclass 15, count 0 2006.201.18:39:31.56#ibcon#enter sib2, iclass 15, count 0 2006.201.18:39:31.56#ibcon#flushed, iclass 15, count 0 2006.201.18:39:31.56#ibcon#about to write, iclass 15, count 0 2006.201.18:39:31.56#ibcon#wrote, iclass 15, count 0 2006.201.18:39:31.56#ibcon#about to read 3, iclass 15, count 0 2006.201.18:39:31.58#ibcon#read 3, iclass 15, count 0 2006.201.18:39:31.58#ibcon#about to read 4, iclass 15, count 0 2006.201.18:39:31.58#ibcon#read 4, iclass 15, count 0 2006.201.18:39:31.58#ibcon#about to read 5, iclass 15, count 0 2006.201.18:39:31.58#ibcon#read 5, iclass 15, count 0 2006.201.18:39:31.58#ibcon#about to read 6, iclass 15, count 0 2006.201.18:39:31.58#ibcon#read 6, iclass 15, count 0 2006.201.18:39:31.58#ibcon#end of sib2, iclass 15, count 0 2006.201.18:39:31.58#ibcon#*mode == 0, iclass 15, count 0 2006.201.18:39:31.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.18:39:31.58#ibcon#[25=USB\r\n] 2006.201.18:39:31.58#ibcon#*before write, iclass 15, count 0 2006.201.18:39:31.58#ibcon#enter sib2, iclass 15, count 0 2006.201.18:39:31.58#ibcon#flushed, iclass 15, count 0 2006.201.18:39:31.58#ibcon#about to write, iclass 15, count 0 2006.201.18:39:31.58#ibcon#wrote, iclass 15, count 0 2006.201.18:39:31.58#ibcon#about to read 3, iclass 15, count 0 2006.201.18:39:31.61#ibcon#read 3, iclass 15, count 0 2006.201.18:39:31.61#ibcon#about to read 4, iclass 15, count 0 2006.201.18:39:31.61#ibcon#read 4, iclass 15, count 0 2006.201.18:39:31.61#ibcon#about to read 5, iclass 15, count 0 2006.201.18:39:31.61#ibcon#read 5, iclass 15, count 0 2006.201.18:39:31.61#ibcon#about to read 6, iclass 15, count 0 2006.201.18:39:31.61#ibcon#read 6, iclass 15, count 0 2006.201.18:39:31.61#ibcon#end of sib2, iclass 15, count 0 2006.201.18:39:31.61#ibcon#*after write, iclass 15, count 0 2006.201.18:39:31.61#ibcon#*before return 0, iclass 15, count 0 2006.201.18:39:31.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:39:31.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.18:39:31.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.18:39:31.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.18:39:31.61$vck44/vblo=1,629.99 2006.201.18:39:31.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.18:39:31.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.18:39:31.61#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:31.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:39:31.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:39:31.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:39:31.61#ibcon#enter wrdev, iclass 17, count 0 2006.201.18:39:31.61#ibcon#first serial, iclass 17, count 0 2006.201.18:39:31.61#ibcon#enter sib2, iclass 17, count 0 2006.201.18:39:31.61#ibcon#flushed, iclass 17, count 0 2006.201.18:39:31.61#ibcon#about to write, iclass 17, count 0 2006.201.18:39:31.61#ibcon#wrote, iclass 17, count 0 2006.201.18:39:31.61#ibcon#about to read 3, iclass 17, count 0 2006.201.18:39:31.63#ibcon#read 3, iclass 17, count 0 2006.201.18:39:31.63#ibcon#about to read 4, iclass 17, count 0 2006.201.18:39:31.63#ibcon#read 4, iclass 17, count 0 2006.201.18:39:31.63#ibcon#about to read 5, iclass 17, count 0 2006.201.18:39:31.63#ibcon#read 5, iclass 17, count 0 2006.201.18:39:31.63#ibcon#about to read 6, iclass 17, count 0 2006.201.18:39:31.63#ibcon#read 6, iclass 17, count 0 2006.201.18:39:31.63#ibcon#end of sib2, iclass 17, count 0 2006.201.18:39:31.63#ibcon#*mode == 0, iclass 17, count 0 2006.201.18:39:31.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.18:39:31.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:39:31.63#ibcon#*before write, iclass 17, count 0 2006.201.18:39:31.63#ibcon#enter sib2, iclass 17, count 0 2006.201.18:39:31.63#ibcon#flushed, iclass 17, count 0 2006.201.18:39:31.63#ibcon#about to write, iclass 17, count 0 2006.201.18:39:31.63#ibcon#wrote, iclass 17, count 0 2006.201.18:39:31.63#ibcon#about to read 3, iclass 17, count 0 2006.201.18:39:31.67#ibcon#read 3, iclass 17, count 0 2006.201.18:39:31.67#ibcon#about to read 4, iclass 17, count 0 2006.201.18:39:31.67#ibcon#read 4, iclass 17, count 0 2006.201.18:39:31.67#ibcon#about to read 5, iclass 17, count 0 2006.201.18:39:31.67#ibcon#read 5, iclass 17, count 0 2006.201.18:39:31.67#ibcon#about to read 6, iclass 17, count 0 2006.201.18:39:31.67#ibcon#read 6, iclass 17, count 0 2006.201.18:39:31.67#ibcon#end of sib2, iclass 17, count 0 2006.201.18:39:31.67#ibcon#*after write, iclass 17, count 0 2006.201.18:39:31.67#ibcon#*before return 0, iclass 17, count 0 2006.201.18:39:31.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:39:31.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.18:39:31.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.18:39:31.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.18:39:31.67$vck44/vb=1,4 2006.201.18:39:31.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.18:39:31.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.18:39:31.67#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:31.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:39:31.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:39:31.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:39:31.67#ibcon#enter wrdev, iclass 19, count 2 2006.201.18:39:31.67#ibcon#first serial, iclass 19, count 2 2006.201.18:39:31.67#ibcon#enter sib2, iclass 19, count 2 2006.201.18:39:31.67#ibcon#flushed, iclass 19, count 2 2006.201.18:39:31.67#ibcon#about to write, iclass 19, count 2 2006.201.18:39:31.67#ibcon#wrote, iclass 19, count 2 2006.201.18:39:31.67#ibcon#about to read 3, iclass 19, count 2 2006.201.18:39:31.69#ibcon#read 3, iclass 19, count 2 2006.201.18:39:31.69#ibcon#about to read 4, iclass 19, count 2 2006.201.18:39:31.69#ibcon#read 4, iclass 19, count 2 2006.201.18:39:31.69#ibcon#about to read 5, iclass 19, count 2 2006.201.18:39:31.69#ibcon#read 5, iclass 19, count 2 2006.201.18:39:31.69#ibcon#about to read 6, iclass 19, count 2 2006.201.18:39:31.69#ibcon#read 6, iclass 19, count 2 2006.201.18:39:31.69#ibcon#end of sib2, iclass 19, count 2 2006.201.18:39:31.69#ibcon#*mode == 0, iclass 19, count 2 2006.201.18:39:31.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.18:39:31.69#ibcon#[27=AT01-04\r\n] 2006.201.18:39:31.69#ibcon#*before write, iclass 19, count 2 2006.201.18:39:31.69#ibcon#enter sib2, iclass 19, count 2 2006.201.18:39:31.69#ibcon#flushed, iclass 19, count 2 2006.201.18:39:31.69#ibcon#about to write, iclass 19, count 2 2006.201.18:39:31.69#ibcon#wrote, iclass 19, count 2 2006.201.18:39:31.69#ibcon#about to read 3, iclass 19, count 2 2006.201.18:39:31.72#ibcon#read 3, iclass 19, count 2 2006.201.18:39:31.72#ibcon#about to read 4, iclass 19, count 2 2006.201.18:39:31.72#ibcon#read 4, iclass 19, count 2 2006.201.18:39:31.72#ibcon#about to read 5, iclass 19, count 2 2006.201.18:39:31.72#ibcon#read 5, iclass 19, count 2 2006.201.18:39:31.72#ibcon#about to read 6, iclass 19, count 2 2006.201.18:39:31.72#ibcon#read 6, iclass 19, count 2 2006.201.18:39:31.72#ibcon#end of sib2, iclass 19, count 2 2006.201.18:39:31.72#ibcon#*after write, iclass 19, count 2 2006.201.18:39:31.72#ibcon#*before return 0, iclass 19, count 2 2006.201.18:39:31.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:39:31.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.18:39:31.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.18:39:31.72#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:31.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:39:31.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:39:31.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:39:31.84#ibcon#enter wrdev, iclass 19, count 0 2006.201.18:39:31.84#ibcon#first serial, iclass 19, count 0 2006.201.18:39:31.84#ibcon#enter sib2, iclass 19, count 0 2006.201.18:39:31.84#ibcon#flushed, iclass 19, count 0 2006.201.18:39:31.84#ibcon#about to write, iclass 19, count 0 2006.201.18:39:31.84#ibcon#wrote, iclass 19, count 0 2006.201.18:39:31.84#ibcon#about to read 3, iclass 19, count 0 2006.201.18:39:31.86#ibcon#read 3, iclass 19, count 0 2006.201.18:39:31.86#ibcon#about to read 4, iclass 19, count 0 2006.201.18:39:31.86#ibcon#read 4, iclass 19, count 0 2006.201.18:39:31.86#ibcon#about to read 5, iclass 19, count 0 2006.201.18:39:31.86#ibcon#read 5, iclass 19, count 0 2006.201.18:39:31.86#ibcon#about to read 6, iclass 19, count 0 2006.201.18:39:31.86#ibcon#read 6, iclass 19, count 0 2006.201.18:39:31.86#ibcon#end of sib2, iclass 19, count 0 2006.201.18:39:31.86#ibcon#*mode == 0, iclass 19, count 0 2006.201.18:39:31.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.18:39:31.86#ibcon#[27=USB\r\n] 2006.201.18:39:31.86#ibcon#*before write, iclass 19, count 0 2006.201.18:39:31.86#ibcon#enter sib2, iclass 19, count 0 2006.201.18:39:31.86#ibcon#flushed, iclass 19, count 0 2006.201.18:39:31.86#ibcon#about to write, iclass 19, count 0 2006.201.18:39:31.86#ibcon#wrote, iclass 19, count 0 2006.201.18:39:31.86#ibcon#about to read 3, iclass 19, count 0 2006.201.18:39:31.89#ibcon#read 3, iclass 19, count 0 2006.201.18:39:31.89#ibcon#about to read 4, iclass 19, count 0 2006.201.18:39:31.89#ibcon#read 4, iclass 19, count 0 2006.201.18:39:31.89#ibcon#about to read 5, iclass 19, count 0 2006.201.18:39:31.89#ibcon#read 5, iclass 19, count 0 2006.201.18:39:31.89#ibcon#about to read 6, iclass 19, count 0 2006.201.18:39:31.89#ibcon#read 6, iclass 19, count 0 2006.201.18:39:31.89#ibcon#end of sib2, iclass 19, count 0 2006.201.18:39:31.89#ibcon#*after write, iclass 19, count 0 2006.201.18:39:31.89#ibcon#*before return 0, iclass 19, count 0 2006.201.18:39:31.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:39:31.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.18:39:31.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.18:39:31.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.18:39:31.89$vck44/vblo=2,634.99 2006.201.18:39:31.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.18:39:31.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.18:39:31.89#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:31.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:31.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:31.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:31.89#ibcon#enter wrdev, iclass 21, count 0 2006.201.18:39:31.89#ibcon#first serial, iclass 21, count 0 2006.201.18:39:31.89#ibcon#enter sib2, iclass 21, count 0 2006.201.18:39:31.89#ibcon#flushed, iclass 21, count 0 2006.201.18:39:31.89#ibcon#about to write, iclass 21, count 0 2006.201.18:39:31.89#ibcon#wrote, iclass 21, count 0 2006.201.18:39:31.89#ibcon#about to read 3, iclass 21, count 0 2006.201.18:39:31.91#ibcon#read 3, iclass 21, count 0 2006.201.18:39:31.91#ibcon#about to read 4, iclass 21, count 0 2006.201.18:39:31.91#ibcon#read 4, iclass 21, count 0 2006.201.18:39:31.91#ibcon#about to read 5, iclass 21, count 0 2006.201.18:39:31.91#ibcon#read 5, iclass 21, count 0 2006.201.18:39:31.91#ibcon#about to read 6, iclass 21, count 0 2006.201.18:39:31.91#ibcon#read 6, iclass 21, count 0 2006.201.18:39:31.91#ibcon#end of sib2, iclass 21, count 0 2006.201.18:39:31.91#ibcon#*mode == 0, iclass 21, count 0 2006.201.18:39:31.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.18:39:31.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:39:31.91#ibcon#*before write, iclass 21, count 0 2006.201.18:39:31.91#ibcon#enter sib2, iclass 21, count 0 2006.201.18:39:31.91#ibcon#flushed, iclass 21, count 0 2006.201.18:39:31.91#ibcon#about to write, iclass 21, count 0 2006.201.18:39:31.91#ibcon#wrote, iclass 21, count 0 2006.201.18:39:31.91#ibcon#about to read 3, iclass 21, count 0 2006.201.18:39:31.96#ibcon#read 3, iclass 21, count 0 2006.201.18:39:31.96#ibcon#about to read 4, iclass 21, count 0 2006.201.18:39:31.96#ibcon#read 4, iclass 21, count 0 2006.201.18:39:31.96#ibcon#about to read 5, iclass 21, count 0 2006.201.18:39:31.96#ibcon#read 5, iclass 21, count 0 2006.201.18:39:31.96#ibcon#about to read 6, iclass 21, count 0 2006.201.18:39:31.96#ibcon#read 6, iclass 21, count 0 2006.201.18:39:31.96#ibcon#end of sib2, iclass 21, count 0 2006.201.18:39:31.96#ibcon#*after write, iclass 21, count 0 2006.201.18:39:31.96#ibcon#*before return 0, iclass 21, count 0 2006.201.18:39:31.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:31.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.18:39:31.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.18:39:31.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.18:39:31.96$vck44/vb=2,5 2006.201.18:39:31.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.18:39:31.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.18:39:31.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:31.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:32.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:32.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:32.01#ibcon#enter wrdev, iclass 23, count 2 2006.201.18:39:32.01#ibcon#first serial, iclass 23, count 2 2006.201.18:39:32.01#ibcon#enter sib2, iclass 23, count 2 2006.201.18:39:32.01#ibcon#flushed, iclass 23, count 2 2006.201.18:39:32.01#ibcon#about to write, iclass 23, count 2 2006.201.18:39:32.01#ibcon#wrote, iclass 23, count 2 2006.201.18:39:32.01#ibcon#about to read 3, iclass 23, count 2 2006.201.18:39:32.03#ibcon#read 3, iclass 23, count 2 2006.201.18:39:32.03#ibcon#about to read 4, iclass 23, count 2 2006.201.18:39:32.03#ibcon#read 4, iclass 23, count 2 2006.201.18:39:32.03#ibcon#about to read 5, iclass 23, count 2 2006.201.18:39:32.03#ibcon#read 5, iclass 23, count 2 2006.201.18:39:32.03#ibcon#about to read 6, iclass 23, count 2 2006.201.18:39:32.03#ibcon#read 6, iclass 23, count 2 2006.201.18:39:32.03#ibcon#end of sib2, iclass 23, count 2 2006.201.18:39:32.03#ibcon#*mode == 0, iclass 23, count 2 2006.201.18:39:32.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.18:39:32.03#ibcon#[27=AT02-05\r\n] 2006.201.18:39:32.03#ibcon#*before write, iclass 23, count 2 2006.201.18:39:32.03#ibcon#enter sib2, iclass 23, count 2 2006.201.18:39:32.03#ibcon#flushed, iclass 23, count 2 2006.201.18:39:32.03#ibcon#about to write, iclass 23, count 2 2006.201.18:39:32.03#ibcon#wrote, iclass 23, count 2 2006.201.18:39:32.03#ibcon#about to read 3, iclass 23, count 2 2006.201.18:39:32.06#ibcon#read 3, iclass 23, count 2 2006.201.18:39:32.06#ibcon#about to read 4, iclass 23, count 2 2006.201.18:39:32.06#ibcon#read 4, iclass 23, count 2 2006.201.18:39:32.06#ibcon#about to read 5, iclass 23, count 2 2006.201.18:39:32.06#ibcon#read 5, iclass 23, count 2 2006.201.18:39:32.06#ibcon#about to read 6, iclass 23, count 2 2006.201.18:39:32.06#ibcon#read 6, iclass 23, count 2 2006.201.18:39:32.06#ibcon#end of sib2, iclass 23, count 2 2006.201.18:39:32.06#ibcon#*after write, iclass 23, count 2 2006.201.18:39:32.06#ibcon#*before return 0, iclass 23, count 2 2006.201.18:39:32.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:32.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.18:39:32.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.18:39:32.06#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:32.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:32.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:32.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:32.18#ibcon#enter wrdev, iclass 23, count 0 2006.201.18:39:32.18#ibcon#first serial, iclass 23, count 0 2006.201.18:39:32.18#ibcon#enter sib2, iclass 23, count 0 2006.201.18:39:32.18#ibcon#flushed, iclass 23, count 0 2006.201.18:39:32.18#ibcon#about to write, iclass 23, count 0 2006.201.18:39:32.18#ibcon#wrote, iclass 23, count 0 2006.201.18:39:32.18#ibcon#about to read 3, iclass 23, count 0 2006.201.18:39:32.20#ibcon#read 3, iclass 23, count 0 2006.201.18:39:32.20#ibcon#about to read 4, iclass 23, count 0 2006.201.18:39:32.20#ibcon#read 4, iclass 23, count 0 2006.201.18:39:32.20#ibcon#about to read 5, iclass 23, count 0 2006.201.18:39:32.20#ibcon#read 5, iclass 23, count 0 2006.201.18:39:32.20#ibcon#about to read 6, iclass 23, count 0 2006.201.18:39:32.20#ibcon#read 6, iclass 23, count 0 2006.201.18:39:32.20#ibcon#end of sib2, iclass 23, count 0 2006.201.18:39:32.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.18:39:32.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.18:39:32.20#ibcon#[27=USB\r\n] 2006.201.18:39:32.20#ibcon#*before write, iclass 23, count 0 2006.201.18:39:32.20#ibcon#enter sib2, iclass 23, count 0 2006.201.18:39:32.20#ibcon#flushed, iclass 23, count 0 2006.201.18:39:32.20#ibcon#about to write, iclass 23, count 0 2006.201.18:39:32.20#ibcon#wrote, iclass 23, count 0 2006.201.18:39:32.20#ibcon#about to read 3, iclass 23, count 0 2006.201.18:39:32.23#ibcon#read 3, iclass 23, count 0 2006.201.18:39:32.23#ibcon#about to read 4, iclass 23, count 0 2006.201.18:39:32.23#ibcon#read 4, iclass 23, count 0 2006.201.18:39:32.23#ibcon#about to read 5, iclass 23, count 0 2006.201.18:39:32.23#ibcon#read 5, iclass 23, count 0 2006.201.18:39:32.23#ibcon#about to read 6, iclass 23, count 0 2006.201.18:39:32.23#ibcon#read 6, iclass 23, count 0 2006.201.18:39:32.23#ibcon#end of sib2, iclass 23, count 0 2006.201.18:39:32.23#ibcon#*after write, iclass 23, count 0 2006.201.18:39:32.23#ibcon#*before return 0, iclass 23, count 0 2006.201.18:39:32.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:32.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.18:39:32.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.18:39:32.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.18:39:32.23$vck44/vblo=3,649.99 2006.201.18:39:32.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.18:39:32.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.18:39:32.23#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:32.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:32.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:32.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:32.23#ibcon#enter wrdev, iclass 25, count 0 2006.201.18:39:32.23#ibcon#first serial, iclass 25, count 0 2006.201.18:39:32.23#ibcon#enter sib2, iclass 25, count 0 2006.201.18:39:32.23#ibcon#flushed, iclass 25, count 0 2006.201.18:39:32.23#ibcon#about to write, iclass 25, count 0 2006.201.18:39:32.23#ibcon#wrote, iclass 25, count 0 2006.201.18:39:32.23#ibcon#about to read 3, iclass 25, count 0 2006.201.18:39:32.25#ibcon#read 3, iclass 25, count 0 2006.201.18:39:32.25#ibcon#about to read 4, iclass 25, count 0 2006.201.18:39:32.25#ibcon#read 4, iclass 25, count 0 2006.201.18:39:32.25#ibcon#about to read 5, iclass 25, count 0 2006.201.18:39:32.25#ibcon#read 5, iclass 25, count 0 2006.201.18:39:32.25#ibcon#about to read 6, iclass 25, count 0 2006.201.18:39:32.25#ibcon#read 6, iclass 25, count 0 2006.201.18:39:32.25#ibcon#end of sib2, iclass 25, count 0 2006.201.18:39:32.25#ibcon#*mode == 0, iclass 25, count 0 2006.201.18:39:32.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.18:39:32.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:39:32.25#ibcon#*before write, iclass 25, count 0 2006.201.18:39:32.25#ibcon#enter sib2, iclass 25, count 0 2006.201.18:39:32.25#ibcon#flushed, iclass 25, count 0 2006.201.18:39:32.25#ibcon#about to write, iclass 25, count 0 2006.201.18:39:32.25#ibcon#wrote, iclass 25, count 0 2006.201.18:39:32.25#ibcon#about to read 3, iclass 25, count 0 2006.201.18:39:32.29#ibcon#read 3, iclass 25, count 0 2006.201.18:39:32.29#ibcon#about to read 4, iclass 25, count 0 2006.201.18:39:32.29#ibcon#read 4, iclass 25, count 0 2006.201.18:39:32.29#ibcon#about to read 5, iclass 25, count 0 2006.201.18:39:32.29#ibcon#read 5, iclass 25, count 0 2006.201.18:39:32.29#ibcon#about to read 6, iclass 25, count 0 2006.201.18:39:32.29#ibcon#read 6, iclass 25, count 0 2006.201.18:39:32.29#ibcon#end of sib2, iclass 25, count 0 2006.201.18:39:32.29#ibcon#*after write, iclass 25, count 0 2006.201.18:39:32.29#ibcon#*before return 0, iclass 25, count 0 2006.201.18:39:32.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:32.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.18:39:32.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.18:39:32.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.18:39:32.29$vck44/vb=3,4 2006.201.18:39:32.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.18:39:32.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.18:39:32.29#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:32.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:32.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:32.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:32.35#ibcon#enter wrdev, iclass 27, count 2 2006.201.18:39:32.35#ibcon#first serial, iclass 27, count 2 2006.201.18:39:32.35#ibcon#enter sib2, iclass 27, count 2 2006.201.18:39:32.35#ibcon#flushed, iclass 27, count 2 2006.201.18:39:32.35#ibcon#about to write, iclass 27, count 2 2006.201.18:39:32.35#ibcon#wrote, iclass 27, count 2 2006.201.18:39:32.35#ibcon#about to read 3, iclass 27, count 2 2006.201.18:39:32.37#ibcon#read 3, iclass 27, count 2 2006.201.18:39:32.37#ibcon#about to read 4, iclass 27, count 2 2006.201.18:39:32.37#ibcon#read 4, iclass 27, count 2 2006.201.18:39:32.37#ibcon#about to read 5, iclass 27, count 2 2006.201.18:39:32.37#ibcon#read 5, iclass 27, count 2 2006.201.18:39:32.37#ibcon#about to read 6, iclass 27, count 2 2006.201.18:39:32.37#ibcon#read 6, iclass 27, count 2 2006.201.18:39:32.37#ibcon#end of sib2, iclass 27, count 2 2006.201.18:39:32.37#ibcon#*mode == 0, iclass 27, count 2 2006.201.18:39:32.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.18:39:32.37#ibcon#[27=AT03-04\r\n] 2006.201.18:39:32.37#ibcon#*before write, iclass 27, count 2 2006.201.18:39:32.37#ibcon#enter sib2, iclass 27, count 2 2006.201.18:39:32.37#ibcon#flushed, iclass 27, count 2 2006.201.18:39:32.37#ibcon#about to write, iclass 27, count 2 2006.201.18:39:32.37#ibcon#wrote, iclass 27, count 2 2006.201.18:39:32.37#ibcon#about to read 3, iclass 27, count 2 2006.201.18:39:32.40#ibcon#read 3, iclass 27, count 2 2006.201.18:39:32.40#ibcon#about to read 4, iclass 27, count 2 2006.201.18:39:32.40#ibcon#read 4, iclass 27, count 2 2006.201.18:39:32.40#ibcon#about to read 5, iclass 27, count 2 2006.201.18:39:32.40#ibcon#read 5, iclass 27, count 2 2006.201.18:39:32.40#ibcon#about to read 6, iclass 27, count 2 2006.201.18:39:32.40#ibcon#read 6, iclass 27, count 2 2006.201.18:39:32.40#ibcon#end of sib2, iclass 27, count 2 2006.201.18:39:32.40#ibcon#*after write, iclass 27, count 2 2006.201.18:39:32.40#ibcon#*before return 0, iclass 27, count 2 2006.201.18:39:32.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:32.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.18:39:32.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.18:39:32.40#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:32.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:32.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:32.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:32.52#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:39:32.52#ibcon#first serial, iclass 27, count 0 2006.201.18:39:32.52#ibcon#enter sib2, iclass 27, count 0 2006.201.18:39:32.52#ibcon#flushed, iclass 27, count 0 2006.201.18:39:32.52#ibcon#about to write, iclass 27, count 0 2006.201.18:39:32.52#ibcon#wrote, iclass 27, count 0 2006.201.18:39:32.52#ibcon#about to read 3, iclass 27, count 0 2006.201.18:39:32.54#ibcon#read 3, iclass 27, count 0 2006.201.18:39:32.54#ibcon#about to read 4, iclass 27, count 0 2006.201.18:39:32.54#ibcon#read 4, iclass 27, count 0 2006.201.18:39:32.54#ibcon#about to read 5, iclass 27, count 0 2006.201.18:39:32.54#ibcon#read 5, iclass 27, count 0 2006.201.18:39:32.54#ibcon#about to read 6, iclass 27, count 0 2006.201.18:39:32.54#ibcon#read 6, iclass 27, count 0 2006.201.18:39:32.54#ibcon#end of sib2, iclass 27, count 0 2006.201.18:39:32.54#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:39:32.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:39:32.54#ibcon#[27=USB\r\n] 2006.201.18:39:32.54#ibcon#*before write, iclass 27, count 0 2006.201.18:39:32.54#ibcon#enter sib2, iclass 27, count 0 2006.201.18:39:32.54#ibcon#flushed, iclass 27, count 0 2006.201.18:39:32.54#ibcon#about to write, iclass 27, count 0 2006.201.18:39:32.54#ibcon#wrote, iclass 27, count 0 2006.201.18:39:32.54#ibcon#about to read 3, iclass 27, count 0 2006.201.18:39:32.57#ibcon#read 3, iclass 27, count 0 2006.201.18:39:32.57#ibcon#about to read 4, iclass 27, count 0 2006.201.18:39:32.57#ibcon#read 4, iclass 27, count 0 2006.201.18:39:32.57#ibcon#about to read 5, iclass 27, count 0 2006.201.18:39:32.57#ibcon#read 5, iclass 27, count 0 2006.201.18:39:32.57#ibcon#about to read 6, iclass 27, count 0 2006.201.18:39:32.57#ibcon#read 6, iclass 27, count 0 2006.201.18:39:32.57#ibcon#end of sib2, iclass 27, count 0 2006.201.18:39:32.57#ibcon#*after write, iclass 27, count 0 2006.201.18:39:32.57#ibcon#*before return 0, iclass 27, count 0 2006.201.18:39:32.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:32.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.18:39:32.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:39:32.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:39:32.57$vck44/vblo=4,679.99 2006.201.18:39:32.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.18:39:32.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.18:39:32.57#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:32.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:32.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:32.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:32.57#ibcon#enter wrdev, iclass 29, count 0 2006.201.18:39:32.57#ibcon#first serial, iclass 29, count 0 2006.201.18:39:32.57#ibcon#enter sib2, iclass 29, count 0 2006.201.18:39:32.57#ibcon#flushed, iclass 29, count 0 2006.201.18:39:32.57#ibcon#about to write, iclass 29, count 0 2006.201.18:39:32.57#ibcon#wrote, iclass 29, count 0 2006.201.18:39:32.57#ibcon#about to read 3, iclass 29, count 0 2006.201.18:39:32.59#ibcon#read 3, iclass 29, count 0 2006.201.18:39:32.59#ibcon#about to read 4, iclass 29, count 0 2006.201.18:39:32.59#ibcon#read 4, iclass 29, count 0 2006.201.18:39:32.59#ibcon#about to read 5, iclass 29, count 0 2006.201.18:39:32.59#ibcon#read 5, iclass 29, count 0 2006.201.18:39:32.59#ibcon#about to read 6, iclass 29, count 0 2006.201.18:39:32.59#ibcon#read 6, iclass 29, count 0 2006.201.18:39:32.59#ibcon#end of sib2, iclass 29, count 0 2006.201.18:39:32.59#ibcon#*mode == 0, iclass 29, count 0 2006.201.18:39:32.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.18:39:32.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:39:32.59#ibcon#*before write, iclass 29, count 0 2006.201.18:39:32.59#ibcon#enter sib2, iclass 29, count 0 2006.201.18:39:32.59#ibcon#flushed, iclass 29, count 0 2006.201.18:39:32.59#ibcon#about to write, iclass 29, count 0 2006.201.18:39:32.59#ibcon#wrote, iclass 29, count 0 2006.201.18:39:32.59#ibcon#about to read 3, iclass 29, count 0 2006.201.18:39:32.63#ibcon#read 3, iclass 29, count 0 2006.201.18:39:32.63#ibcon#about to read 4, iclass 29, count 0 2006.201.18:39:32.63#ibcon#read 4, iclass 29, count 0 2006.201.18:39:32.63#ibcon#about to read 5, iclass 29, count 0 2006.201.18:39:32.63#ibcon#read 5, iclass 29, count 0 2006.201.18:39:32.63#ibcon#about to read 6, iclass 29, count 0 2006.201.18:39:32.63#ibcon#read 6, iclass 29, count 0 2006.201.18:39:32.63#ibcon#end of sib2, iclass 29, count 0 2006.201.18:39:32.63#ibcon#*after write, iclass 29, count 0 2006.201.18:39:32.63#ibcon#*before return 0, iclass 29, count 0 2006.201.18:39:32.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:32.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.18:39:32.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.18:39:32.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.18:39:32.63$vck44/vb=4,5 2006.201.18:39:32.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.18:39:32.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.18:39:32.63#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:32.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:32.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:32.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:32.69#ibcon#enter wrdev, iclass 31, count 2 2006.201.18:39:32.69#ibcon#first serial, iclass 31, count 2 2006.201.18:39:32.69#ibcon#enter sib2, iclass 31, count 2 2006.201.18:39:32.69#ibcon#flushed, iclass 31, count 2 2006.201.18:39:32.69#ibcon#about to write, iclass 31, count 2 2006.201.18:39:32.69#ibcon#wrote, iclass 31, count 2 2006.201.18:39:32.69#ibcon#about to read 3, iclass 31, count 2 2006.201.18:39:32.71#ibcon#read 3, iclass 31, count 2 2006.201.18:39:32.71#ibcon#about to read 4, iclass 31, count 2 2006.201.18:39:32.71#ibcon#read 4, iclass 31, count 2 2006.201.18:39:32.71#ibcon#about to read 5, iclass 31, count 2 2006.201.18:39:32.71#ibcon#read 5, iclass 31, count 2 2006.201.18:39:32.71#ibcon#about to read 6, iclass 31, count 2 2006.201.18:39:32.71#ibcon#read 6, iclass 31, count 2 2006.201.18:39:32.71#ibcon#end of sib2, iclass 31, count 2 2006.201.18:39:32.71#ibcon#*mode == 0, iclass 31, count 2 2006.201.18:39:32.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.18:39:32.71#ibcon#[27=AT04-05\r\n] 2006.201.18:39:32.71#ibcon#*before write, iclass 31, count 2 2006.201.18:39:32.71#ibcon#enter sib2, iclass 31, count 2 2006.201.18:39:32.71#ibcon#flushed, iclass 31, count 2 2006.201.18:39:32.71#ibcon#about to write, iclass 31, count 2 2006.201.18:39:32.71#ibcon#wrote, iclass 31, count 2 2006.201.18:39:32.71#ibcon#about to read 3, iclass 31, count 2 2006.201.18:39:32.74#ibcon#read 3, iclass 31, count 2 2006.201.18:39:32.74#ibcon#about to read 4, iclass 31, count 2 2006.201.18:39:32.74#ibcon#read 4, iclass 31, count 2 2006.201.18:39:32.74#ibcon#about to read 5, iclass 31, count 2 2006.201.18:39:32.74#ibcon#read 5, iclass 31, count 2 2006.201.18:39:32.74#ibcon#about to read 6, iclass 31, count 2 2006.201.18:39:32.74#ibcon#read 6, iclass 31, count 2 2006.201.18:39:32.74#ibcon#end of sib2, iclass 31, count 2 2006.201.18:39:32.74#ibcon#*after write, iclass 31, count 2 2006.201.18:39:32.74#ibcon#*before return 0, iclass 31, count 2 2006.201.18:39:32.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:32.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.18:39:32.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.18:39:32.74#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:32.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:32.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:32.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:32.86#ibcon#enter wrdev, iclass 31, count 0 2006.201.18:39:32.86#ibcon#first serial, iclass 31, count 0 2006.201.18:39:32.86#ibcon#enter sib2, iclass 31, count 0 2006.201.18:39:32.86#ibcon#flushed, iclass 31, count 0 2006.201.18:39:32.86#ibcon#about to write, iclass 31, count 0 2006.201.18:39:32.86#ibcon#wrote, iclass 31, count 0 2006.201.18:39:32.86#ibcon#about to read 3, iclass 31, count 0 2006.201.18:39:32.88#ibcon#read 3, iclass 31, count 0 2006.201.18:39:32.88#ibcon#about to read 4, iclass 31, count 0 2006.201.18:39:32.88#ibcon#read 4, iclass 31, count 0 2006.201.18:39:32.88#ibcon#about to read 5, iclass 31, count 0 2006.201.18:39:32.88#ibcon#read 5, iclass 31, count 0 2006.201.18:39:32.88#ibcon#about to read 6, iclass 31, count 0 2006.201.18:39:32.88#ibcon#read 6, iclass 31, count 0 2006.201.18:39:32.88#ibcon#end of sib2, iclass 31, count 0 2006.201.18:39:32.88#ibcon#*mode == 0, iclass 31, count 0 2006.201.18:39:32.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.18:39:32.88#ibcon#[27=USB\r\n] 2006.201.18:39:32.88#ibcon#*before write, iclass 31, count 0 2006.201.18:39:32.88#ibcon#enter sib2, iclass 31, count 0 2006.201.18:39:32.88#ibcon#flushed, iclass 31, count 0 2006.201.18:39:32.88#ibcon#about to write, iclass 31, count 0 2006.201.18:39:32.88#ibcon#wrote, iclass 31, count 0 2006.201.18:39:32.88#ibcon#about to read 3, iclass 31, count 0 2006.201.18:39:32.91#ibcon#read 3, iclass 31, count 0 2006.201.18:39:32.91#ibcon#about to read 4, iclass 31, count 0 2006.201.18:39:32.91#ibcon#read 4, iclass 31, count 0 2006.201.18:39:32.91#ibcon#about to read 5, iclass 31, count 0 2006.201.18:39:32.91#ibcon#read 5, iclass 31, count 0 2006.201.18:39:32.91#ibcon#about to read 6, iclass 31, count 0 2006.201.18:39:32.91#ibcon#read 6, iclass 31, count 0 2006.201.18:39:32.91#ibcon#end of sib2, iclass 31, count 0 2006.201.18:39:32.91#ibcon#*after write, iclass 31, count 0 2006.201.18:39:32.91#ibcon#*before return 0, iclass 31, count 0 2006.201.18:39:32.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:32.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.18:39:32.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.18:39:32.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.18:39:32.91$vck44/vblo=5,709.99 2006.201.18:39:32.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.18:39:32.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.18:39:32.91#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:32.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:32.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:32.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:32.91#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:39:32.91#ibcon#first serial, iclass 33, count 0 2006.201.18:39:32.91#ibcon#enter sib2, iclass 33, count 0 2006.201.18:39:32.91#ibcon#flushed, iclass 33, count 0 2006.201.18:39:32.91#ibcon#about to write, iclass 33, count 0 2006.201.18:39:32.91#ibcon#wrote, iclass 33, count 0 2006.201.18:39:32.91#ibcon#about to read 3, iclass 33, count 0 2006.201.18:39:32.93#ibcon#read 3, iclass 33, count 0 2006.201.18:39:32.93#ibcon#about to read 4, iclass 33, count 0 2006.201.18:39:32.93#ibcon#read 4, iclass 33, count 0 2006.201.18:39:32.93#ibcon#about to read 5, iclass 33, count 0 2006.201.18:39:32.93#ibcon#read 5, iclass 33, count 0 2006.201.18:39:32.93#ibcon#about to read 6, iclass 33, count 0 2006.201.18:39:32.93#ibcon#read 6, iclass 33, count 0 2006.201.18:39:32.93#ibcon#end of sib2, iclass 33, count 0 2006.201.18:39:32.93#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:39:32.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:39:32.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:39:32.93#ibcon#*before write, iclass 33, count 0 2006.201.18:39:32.93#ibcon#enter sib2, iclass 33, count 0 2006.201.18:39:32.93#ibcon#flushed, iclass 33, count 0 2006.201.18:39:32.93#ibcon#about to write, iclass 33, count 0 2006.201.18:39:32.93#ibcon#wrote, iclass 33, count 0 2006.201.18:39:32.93#ibcon#about to read 3, iclass 33, count 0 2006.201.18:39:32.98#ibcon#read 3, iclass 33, count 0 2006.201.18:39:32.98#ibcon#about to read 4, iclass 33, count 0 2006.201.18:39:32.98#ibcon#read 4, iclass 33, count 0 2006.201.18:39:32.98#ibcon#about to read 5, iclass 33, count 0 2006.201.18:39:32.98#ibcon#read 5, iclass 33, count 0 2006.201.18:39:32.98#ibcon#about to read 6, iclass 33, count 0 2006.201.18:39:32.98#ibcon#read 6, iclass 33, count 0 2006.201.18:39:32.98#ibcon#end of sib2, iclass 33, count 0 2006.201.18:39:32.98#ibcon#*after write, iclass 33, count 0 2006.201.18:39:32.98#ibcon#*before return 0, iclass 33, count 0 2006.201.18:39:32.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:32.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:39:32.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:39:32.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:39:32.98$vck44/vb=5,4 2006.201.18:39:32.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.18:39:32.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.18:39:32.98#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:32.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:33.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:33.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:33.03#ibcon#enter wrdev, iclass 35, count 2 2006.201.18:39:33.03#ibcon#first serial, iclass 35, count 2 2006.201.18:39:33.03#ibcon#enter sib2, iclass 35, count 2 2006.201.18:39:33.03#ibcon#flushed, iclass 35, count 2 2006.201.18:39:33.03#ibcon#about to write, iclass 35, count 2 2006.201.18:39:33.03#ibcon#wrote, iclass 35, count 2 2006.201.18:39:33.03#ibcon#about to read 3, iclass 35, count 2 2006.201.18:39:33.05#ibcon#read 3, iclass 35, count 2 2006.201.18:39:33.05#ibcon#about to read 4, iclass 35, count 2 2006.201.18:39:33.05#ibcon#read 4, iclass 35, count 2 2006.201.18:39:33.05#ibcon#about to read 5, iclass 35, count 2 2006.201.18:39:33.05#ibcon#read 5, iclass 35, count 2 2006.201.18:39:33.05#ibcon#about to read 6, iclass 35, count 2 2006.201.18:39:33.05#ibcon#read 6, iclass 35, count 2 2006.201.18:39:33.05#ibcon#end of sib2, iclass 35, count 2 2006.201.18:39:33.05#ibcon#*mode == 0, iclass 35, count 2 2006.201.18:39:33.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.18:39:33.05#ibcon#[27=AT05-04\r\n] 2006.201.18:39:33.05#ibcon#*before write, iclass 35, count 2 2006.201.18:39:33.05#ibcon#enter sib2, iclass 35, count 2 2006.201.18:39:33.05#ibcon#flushed, iclass 35, count 2 2006.201.18:39:33.05#ibcon#about to write, iclass 35, count 2 2006.201.18:39:33.05#ibcon#wrote, iclass 35, count 2 2006.201.18:39:33.05#ibcon#about to read 3, iclass 35, count 2 2006.201.18:39:33.08#ibcon#read 3, iclass 35, count 2 2006.201.18:39:33.08#ibcon#about to read 4, iclass 35, count 2 2006.201.18:39:33.08#ibcon#read 4, iclass 35, count 2 2006.201.18:39:33.08#ibcon#about to read 5, iclass 35, count 2 2006.201.18:39:33.08#ibcon#read 5, iclass 35, count 2 2006.201.18:39:33.08#ibcon#about to read 6, iclass 35, count 2 2006.201.18:39:33.08#ibcon#read 6, iclass 35, count 2 2006.201.18:39:33.08#ibcon#end of sib2, iclass 35, count 2 2006.201.18:39:33.08#ibcon#*after write, iclass 35, count 2 2006.201.18:39:33.08#ibcon#*before return 0, iclass 35, count 2 2006.201.18:39:33.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:33.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.18:39:33.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.18:39:33.08#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:33.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:33.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:33.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:33.20#ibcon#enter wrdev, iclass 35, count 0 2006.201.18:39:33.20#ibcon#first serial, iclass 35, count 0 2006.201.18:39:33.20#ibcon#enter sib2, iclass 35, count 0 2006.201.18:39:33.20#ibcon#flushed, iclass 35, count 0 2006.201.18:39:33.20#ibcon#about to write, iclass 35, count 0 2006.201.18:39:33.20#ibcon#wrote, iclass 35, count 0 2006.201.18:39:33.20#ibcon#about to read 3, iclass 35, count 0 2006.201.18:39:33.22#ibcon#read 3, iclass 35, count 0 2006.201.18:39:33.22#ibcon#about to read 4, iclass 35, count 0 2006.201.18:39:33.22#ibcon#read 4, iclass 35, count 0 2006.201.18:39:33.22#ibcon#about to read 5, iclass 35, count 0 2006.201.18:39:33.22#ibcon#read 5, iclass 35, count 0 2006.201.18:39:33.22#ibcon#about to read 6, iclass 35, count 0 2006.201.18:39:33.22#ibcon#read 6, iclass 35, count 0 2006.201.18:39:33.22#ibcon#end of sib2, iclass 35, count 0 2006.201.18:39:33.22#ibcon#*mode == 0, iclass 35, count 0 2006.201.18:39:33.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.18:39:33.22#ibcon#[27=USB\r\n] 2006.201.18:39:33.22#ibcon#*before write, iclass 35, count 0 2006.201.18:39:33.22#ibcon#enter sib2, iclass 35, count 0 2006.201.18:39:33.22#ibcon#flushed, iclass 35, count 0 2006.201.18:39:33.22#ibcon#about to write, iclass 35, count 0 2006.201.18:39:33.22#ibcon#wrote, iclass 35, count 0 2006.201.18:39:33.22#ibcon#about to read 3, iclass 35, count 0 2006.201.18:39:33.25#ibcon#read 3, iclass 35, count 0 2006.201.18:39:33.25#ibcon#about to read 4, iclass 35, count 0 2006.201.18:39:33.25#ibcon#read 4, iclass 35, count 0 2006.201.18:39:33.25#ibcon#about to read 5, iclass 35, count 0 2006.201.18:39:33.25#ibcon#read 5, iclass 35, count 0 2006.201.18:39:33.25#ibcon#about to read 6, iclass 35, count 0 2006.201.18:39:33.25#ibcon#read 6, iclass 35, count 0 2006.201.18:39:33.25#ibcon#end of sib2, iclass 35, count 0 2006.201.18:39:33.25#ibcon#*after write, iclass 35, count 0 2006.201.18:39:33.25#ibcon#*before return 0, iclass 35, count 0 2006.201.18:39:33.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:33.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.18:39:33.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.18:39:33.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.18:39:33.25$vck44/vblo=6,719.99 2006.201.18:39:33.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.18:39:33.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.18:39:33.25#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:33.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:33.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:33.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:33.25#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:39:33.25#ibcon#first serial, iclass 37, count 0 2006.201.18:39:33.25#ibcon#enter sib2, iclass 37, count 0 2006.201.18:39:33.25#ibcon#flushed, iclass 37, count 0 2006.201.18:39:33.25#ibcon#about to write, iclass 37, count 0 2006.201.18:39:33.25#ibcon#wrote, iclass 37, count 0 2006.201.18:39:33.25#ibcon#about to read 3, iclass 37, count 0 2006.201.18:39:33.27#ibcon#read 3, iclass 37, count 0 2006.201.18:39:33.27#ibcon#about to read 4, iclass 37, count 0 2006.201.18:39:33.27#ibcon#read 4, iclass 37, count 0 2006.201.18:39:33.27#ibcon#about to read 5, iclass 37, count 0 2006.201.18:39:33.27#ibcon#read 5, iclass 37, count 0 2006.201.18:39:33.27#ibcon#about to read 6, iclass 37, count 0 2006.201.18:39:33.27#ibcon#read 6, iclass 37, count 0 2006.201.18:39:33.27#ibcon#end of sib2, iclass 37, count 0 2006.201.18:39:33.27#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:39:33.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:39:33.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:39:33.27#ibcon#*before write, iclass 37, count 0 2006.201.18:39:33.27#ibcon#enter sib2, iclass 37, count 0 2006.201.18:39:33.27#ibcon#flushed, iclass 37, count 0 2006.201.18:39:33.27#ibcon#about to write, iclass 37, count 0 2006.201.18:39:33.27#ibcon#wrote, iclass 37, count 0 2006.201.18:39:33.27#ibcon#about to read 3, iclass 37, count 0 2006.201.18:39:33.31#ibcon#read 3, iclass 37, count 0 2006.201.18:39:33.31#ibcon#about to read 4, iclass 37, count 0 2006.201.18:39:33.31#ibcon#read 4, iclass 37, count 0 2006.201.18:39:33.31#ibcon#about to read 5, iclass 37, count 0 2006.201.18:39:33.31#ibcon#read 5, iclass 37, count 0 2006.201.18:39:33.31#ibcon#about to read 6, iclass 37, count 0 2006.201.18:39:33.31#ibcon#read 6, iclass 37, count 0 2006.201.18:39:33.31#ibcon#end of sib2, iclass 37, count 0 2006.201.18:39:33.31#ibcon#*after write, iclass 37, count 0 2006.201.18:39:33.31#ibcon#*before return 0, iclass 37, count 0 2006.201.18:39:33.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:33.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.18:39:33.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:39:33.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:39:33.31$vck44/vb=6,4 2006.201.18:39:33.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.18:39:33.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.18:39:33.31#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:33.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:33.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:33.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:33.37#ibcon#enter wrdev, iclass 39, count 2 2006.201.18:39:33.37#ibcon#first serial, iclass 39, count 2 2006.201.18:39:33.37#ibcon#enter sib2, iclass 39, count 2 2006.201.18:39:33.37#ibcon#flushed, iclass 39, count 2 2006.201.18:39:33.37#ibcon#about to write, iclass 39, count 2 2006.201.18:39:33.37#ibcon#wrote, iclass 39, count 2 2006.201.18:39:33.37#ibcon#about to read 3, iclass 39, count 2 2006.201.18:39:33.39#ibcon#read 3, iclass 39, count 2 2006.201.18:39:33.39#ibcon#about to read 4, iclass 39, count 2 2006.201.18:39:33.39#ibcon#read 4, iclass 39, count 2 2006.201.18:39:33.39#ibcon#about to read 5, iclass 39, count 2 2006.201.18:39:33.39#ibcon#read 5, iclass 39, count 2 2006.201.18:39:33.39#ibcon#about to read 6, iclass 39, count 2 2006.201.18:39:33.39#ibcon#read 6, iclass 39, count 2 2006.201.18:39:33.39#ibcon#end of sib2, iclass 39, count 2 2006.201.18:39:33.39#ibcon#*mode == 0, iclass 39, count 2 2006.201.18:39:33.39#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.18:39:33.39#ibcon#[27=AT06-04\r\n] 2006.201.18:39:33.39#ibcon#*before write, iclass 39, count 2 2006.201.18:39:33.39#ibcon#enter sib2, iclass 39, count 2 2006.201.18:39:33.39#ibcon#flushed, iclass 39, count 2 2006.201.18:39:33.39#ibcon#about to write, iclass 39, count 2 2006.201.18:39:33.39#ibcon#wrote, iclass 39, count 2 2006.201.18:39:33.39#ibcon#about to read 3, iclass 39, count 2 2006.201.18:39:33.42#ibcon#read 3, iclass 39, count 2 2006.201.18:39:33.42#ibcon#about to read 4, iclass 39, count 2 2006.201.18:39:33.42#ibcon#read 4, iclass 39, count 2 2006.201.18:39:33.42#ibcon#about to read 5, iclass 39, count 2 2006.201.18:39:33.42#ibcon#read 5, iclass 39, count 2 2006.201.18:39:33.42#ibcon#about to read 6, iclass 39, count 2 2006.201.18:39:33.42#ibcon#read 6, iclass 39, count 2 2006.201.18:39:33.42#ibcon#end of sib2, iclass 39, count 2 2006.201.18:39:33.42#ibcon#*after write, iclass 39, count 2 2006.201.18:39:33.42#ibcon#*before return 0, iclass 39, count 2 2006.201.18:39:33.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:33.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.18:39:33.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.18:39:33.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:33.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:33.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:33.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:33.54#ibcon#enter wrdev, iclass 39, count 0 2006.201.18:39:33.54#ibcon#first serial, iclass 39, count 0 2006.201.18:39:33.54#ibcon#enter sib2, iclass 39, count 0 2006.201.18:39:33.54#ibcon#flushed, iclass 39, count 0 2006.201.18:39:33.54#ibcon#about to write, iclass 39, count 0 2006.201.18:39:33.54#ibcon#wrote, iclass 39, count 0 2006.201.18:39:33.54#ibcon#about to read 3, iclass 39, count 0 2006.201.18:39:33.56#ibcon#read 3, iclass 39, count 0 2006.201.18:39:33.56#ibcon#about to read 4, iclass 39, count 0 2006.201.18:39:33.56#ibcon#read 4, iclass 39, count 0 2006.201.18:39:33.56#ibcon#about to read 5, iclass 39, count 0 2006.201.18:39:33.56#ibcon#read 5, iclass 39, count 0 2006.201.18:39:33.56#ibcon#about to read 6, iclass 39, count 0 2006.201.18:39:33.56#ibcon#read 6, iclass 39, count 0 2006.201.18:39:33.56#ibcon#end of sib2, iclass 39, count 0 2006.201.18:39:33.56#ibcon#*mode == 0, iclass 39, count 0 2006.201.18:39:33.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.18:39:33.56#ibcon#[27=USB\r\n] 2006.201.18:39:33.56#ibcon#*before write, iclass 39, count 0 2006.201.18:39:33.56#ibcon#enter sib2, iclass 39, count 0 2006.201.18:39:33.56#ibcon#flushed, iclass 39, count 0 2006.201.18:39:33.56#ibcon#about to write, iclass 39, count 0 2006.201.18:39:33.56#ibcon#wrote, iclass 39, count 0 2006.201.18:39:33.56#ibcon#about to read 3, iclass 39, count 0 2006.201.18:39:33.59#ibcon#read 3, iclass 39, count 0 2006.201.18:39:33.59#ibcon#about to read 4, iclass 39, count 0 2006.201.18:39:33.59#ibcon#read 4, iclass 39, count 0 2006.201.18:39:33.59#ibcon#about to read 5, iclass 39, count 0 2006.201.18:39:33.59#ibcon#read 5, iclass 39, count 0 2006.201.18:39:33.59#ibcon#about to read 6, iclass 39, count 0 2006.201.18:39:33.59#ibcon#read 6, iclass 39, count 0 2006.201.18:39:33.59#ibcon#end of sib2, iclass 39, count 0 2006.201.18:39:33.59#ibcon#*after write, iclass 39, count 0 2006.201.18:39:33.59#ibcon#*before return 0, iclass 39, count 0 2006.201.18:39:33.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:33.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.18:39:33.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.18:39:33.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.18:39:33.59$vck44/vblo=7,734.99 2006.201.18:39:33.59#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.18:39:33.59#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.18:39:33.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:33.59#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:33.59#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:33.59#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:33.59#ibcon#enter wrdev, iclass 2, count 0 2006.201.18:39:33.59#ibcon#first serial, iclass 2, count 0 2006.201.18:39:33.59#ibcon#enter sib2, iclass 2, count 0 2006.201.18:39:33.59#ibcon#flushed, iclass 2, count 0 2006.201.18:39:33.59#ibcon#about to write, iclass 2, count 0 2006.201.18:39:33.59#ibcon#wrote, iclass 2, count 0 2006.201.18:39:33.59#ibcon#about to read 3, iclass 2, count 0 2006.201.18:39:33.61#ibcon#read 3, iclass 2, count 0 2006.201.18:39:33.61#ibcon#about to read 4, iclass 2, count 0 2006.201.18:39:33.61#ibcon#read 4, iclass 2, count 0 2006.201.18:39:33.61#ibcon#about to read 5, iclass 2, count 0 2006.201.18:39:33.61#ibcon#read 5, iclass 2, count 0 2006.201.18:39:33.61#ibcon#about to read 6, iclass 2, count 0 2006.201.18:39:33.61#ibcon#read 6, iclass 2, count 0 2006.201.18:39:33.61#ibcon#end of sib2, iclass 2, count 0 2006.201.18:39:33.61#ibcon#*mode == 0, iclass 2, count 0 2006.201.18:39:33.61#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.18:39:33.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:39:33.61#ibcon#*before write, iclass 2, count 0 2006.201.18:39:33.61#ibcon#enter sib2, iclass 2, count 0 2006.201.18:39:33.61#ibcon#flushed, iclass 2, count 0 2006.201.18:39:33.61#ibcon#about to write, iclass 2, count 0 2006.201.18:39:33.61#ibcon#wrote, iclass 2, count 0 2006.201.18:39:33.61#ibcon#about to read 3, iclass 2, count 0 2006.201.18:39:33.66#ibcon#read 3, iclass 2, count 0 2006.201.18:39:33.66#ibcon#about to read 4, iclass 2, count 0 2006.201.18:39:33.66#ibcon#read 4, iclass 2, count 0 2006.201.18:39:33.66#ibcon#about to read 5, iclass 2, count 0 2006.201.18:39:33.66#ibcon#read 5, iclass 2, count 0 2006.201.18:39:33.66#ibcon#about to read 6, iclass 2, count 0 2006.201.18:39:33.66#ibcon#read 6, iclass 2, count 0 2006.201.18:39:33.66#ibcon#end of sib2, iclass 2, count 0 2006.201.18:39:33.66#ibcon#*after write, iclass 2, count 0 2006.201.18:39:33.66#ibcon#*before return 0, iclass 2, count 0 2006.201.18:39:33.66#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:33.66#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.18:39:33.66#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.18:39:33.66#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.18:39:33.66$vck44/vb=7,4 2006.201.18:39:33.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.18:39:33.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.18:39:33.66#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:33.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:33.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:33.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:33.71#ibcon#enter wrdev, iclass 5, count 2 2006.201.18:39:33.71#ibcon#first serial, iclass 5, count 2 2006.201.18:39:33.71#ibcon#enter sib2, iclass 5, count 2 2006.201.18:39:33.71#ibcon#flushed, iclass 5, count 2 2006.201.18:39:33.71#ibcon#about to write, iclass 5, count 2 2006.201.18:39:33.71#ibcon#wrote, iclass 5, count 2 2006.201.18:39:33.71#ibcon#about to read 3, iclass 5, count 2 2006.201.18:39:33.73#ibcon#read 3, iclass 5, count 2 2006.201.18:39:33.73#ibcon#about to read 4, iclass 5, count 2 2006.201.18:39:33.73#ibcon#read 4, iclass 5, count 2 2006.201.18:39:33.73#ibcon#about to read 5, iclass 5, count 2 2006.201.18:39:33.73#ibcon#read 5, iclass 5, count 2 2006.201.18:39:33.73#ibcon#about to read 6, iclass 5, count 2 2006.201.18:39:33.73#ibcon#read 6, iclass 5, count 2 2006.201.18:39:33.73#ibcon#end of sib2, iclass 5, count 2 2006.201.18:39:33.73#ibcon#*mode == 0, iclass 5, count 2 2006.201.18:39:33.73#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.18:39:33.73#ibcon#[27=AT07-04\r\n] 2006.201.18:39:33.73#ibcon#*before write, iclass 5, count 2 2006.201.18:39:33.73#ibcon#enter sib2, iclass 5, count 2 2006.201.18:39:33.73#ibcon#flushed, iclass 5, count 2 2006.201.18:39:33.73#ibcon#about to write, iclass 5, count 2 2006.201.18:39:33.73#ibcon#wrote, iclass 5, count 2 2006.201.18:39:33.73#ibcon#about to read 3, iclass 5, count 2 2006.201.18:39:33.76#ibcon#read 3, iclass 5, count 2 2006.201.18:39:33.76#ibcon#about to read 4, iclass 5, count 2 2006.201.18:39:33.76#ibcon#read 4, iclass 5, count 2 2006.201.18:39:33.76#ibcon#about to read 5, iclass 5, count 2 2006.201.18:39:33.76#ibcon#read 5, iclass 5, count 2 2006.201.18:39:33.76#ibcon#about to read 6, iclass 5, count 2 2006.201.18:39:33.76#ibcon#read 6, iclass 5, count 2 2006.201.18:39:33.76#ibcon#end of sib2, iclass 5, count 2 2006.201.18:39:33.76#ibcon#*after write, iclass 5, count 2 2006.201.18:39:33.76#ibcon#*before return 0, iclass 5, count 2 2006.201.18:39:33.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:33.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.18:39:33.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.18:39:33.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:33.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:33.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:33.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:33.88#ibcon#enter wrdev, iclass 5, count 0 2006.201.18:39:33.88#ibcon#first serial, iclass 5, count 0 2006.201.18:39:33.88#ibcon#enter sib2, iclass 5, count 0 2006.201.18:39:33.88#ibcon#flushed, iclass 5, count 0 2006.201.18:39:33.88#ibcon#about to write, iclass 5, count 0 2006.201.18:39:33.88#ibcon#wrote, iclass 5, count 0 2006.201.18:39:33.88#ibcon#about to read 3, iclass 5, count 0 2006.201.18:39:33.90#ibcon#read 3, iclass 5, count 0 2006.201.18:39:33.90#ibcon#about to read 4, iclass 5, count 0 2006.201.18:39:33.90#ibcon#read 4, iclass 5, count 0 2006.201.18:39:33.90#ibcon#about to read 5, iclass 5, count 0 2006.201.18:39:33.90#ibcon#read 5, iclass 5, count 0 2006.201.18:39:33.90#ibcon#about to read 6, iclass 5, count 0 2006.201.18:39:33.90#ibcon#read 6, iclass 5, count 0 2006.201.18:39:33.90#ibcon#end of sib2, iclass 5, count 0 2006.201.18:39:33.90#ibcon#*mode == 0, iclass 5, count 0 2006.201.18:39:33.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.18:39:33.90#ibcon#[27=USB\r\n] 2006.201.18:39:33.90#ibcon#*before write, iclass 5, count 0 2006.201.18:39:33.90#ibcon#enter sib2, iclass 5, count 0 2006.201.18:39:33.90#ibcon#flushed, iclass 5, count 0 2006.201.18:39:33.90#ibcon#about to write, iclass 5, count 0 2006.201.18:39:33.90#ibcon#wrote, iclass 5, count 0 2006.201.18:39:33.90#ibcon#about to read 3, iclass 5, count 0 2006.201.18:39:33.93#ibcon#read 3, iclass 5, count 0 2006.201.18:39:33.93#ibcon#about to read 4, iclass 5, count 0 2006.201.18:39:33.93#ibcon#read 4, iclass 5, count 0 2006.201.18:39:33.93#ibcon#about to read 5, iclass 5, count 0 2006.201.18:39:33.93#ibcon#read 5, iclass 5, count 0 2006.201.18:39:33.93#ibcon#about to read 6, iclass 5, count 0 2006.201.18:39:33.93#ibcon#read 6, iclass 5, count 0 2006.201.18:39:33.93#ibcon#end of sib2, iclass 5, count 0 2006.201.18:39:33.93#ibcon#*after write, iclass 5, count 0 2006.201.18:39:33.93#ibcon#*before return 0, iclass 5, count 0 2006.201.18:39:33.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:33.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.18:39:33.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.18:39:33.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.18:39:33.93$vck44/vblo=8,744.99 2006.201.18:39:33.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.18:39:33.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.18:39:33.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:39:33.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:33.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:33.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:33.93#ibcon#enter wrdev, iclass 7, count 0 2006.201.18:39:33.93#ibcon#first serial, iclass 7, count 0 2006.201.18:39:33.93#ibcon#enter sib2, iclass 7, count 0 2006.201.18:39:33.93#ibcon#flushed, iclass 7, count 0 2006.201.18:39:33.93#ibcon#about to write, iclass 7, count 0 2006.201.18:39:33.93#ibcon#wrote, iclass 7, count 0 2006.201.18:39:33.93#ibcon#about to read 3, iclass 7, count 0 2006.201.18:39:33.95#ibcon#read 3, iclass 7, count 0 2006.201.18:39:33.95#ibcon#about to read 4, iclass 7, count 0 2006.201.18:39:33.95#ibcon#read 4, iclass 7, count 0 2006.201.18:39:33.95#ibcon#about to read 5, iclass 7, count 0 2006.201.18:39:33.95#ibcon#read 5, iclass 7, count 0 2006.201.18:39:33.95#ibcon#about to read 6, iclass 7, count 0 2006.201.18:39:33.95#ibcon#read 6, iclass 7, count 0 2006.201.18:39:33.95#ibcon#end of sib2, iclass 7, count 0 2006.201.18:39:33.95#ibcon#*mode == 0, iclass 7, count 0 2006.201.18:39:33.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.18:39:33.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:39:33.95#ibcon#*before write, iclass 7, count 0 2006.201.18:39:33.95#ibcon#enter sib2, iclass 7, count 0 2006.201.18:39:33.95#ibcon#flushed, iclass 7, count 0 2006.201.18:39:33.95#ibcon#about to write, iclass 7, count 0 2006.201.18:39:33.95#ibcon#wrote, iclass 7, count 0 2006.201.18:39:33.95#ibcon#about to read 3, iclass 7, count 0 2006.201.18:39:33.99#ibcon#read 3, iclass 7, count 0 2006.201.18:39:33.99#ibcon#about to read 4, iclass 7, count 0 2006.201.18:39:33.99#ibcon#read 4, iclass 7, count 0 2006.201.18:39:33.99#ibcon#about to read 5, iclass 7, count 0 2006.201.18:39:33.99#ibcon#read 5, iclass 7, count 0 2006.201.18:39:33.99#ibcon#about to read 6, iclass 7, count 0 2006.201.18:39:33.99#ibcon#read 6, iclass 7, count 0 2006.201.18:39:33.99#ibcon#end of sib2, iclass 7, count 0 2006.201.18:39:33.99#ibcon#*after write, iclass 7, count 0 2006.201.18:39:33.99#ibcon#*before return 0, iclass 7, count 0 2006.201.18:39:33.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:33.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.18:39:33.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.18:39:33.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.18:39:33.99$vck44/vb=8,4 2006.201.18:39:33.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.18:39:33.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.18:39:33.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:39:33.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:34.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:34.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:34.05#ibcon#enter wrdev, iclass 11, count 2 2006.201.18:39:34.05#ibcon#first serial, iclass 11, count 2 2006.201.18:39:34.05#ibcon#enter sib2, iclass 11, count 2 2006.201.18:39:34.05#ibcon#flushed, iclass 11, count 2 2006.201.18:39:34.05#ibcon#about to write, iclass 11, count 2 2006.201.18:39:34.05#ibcon#wrote, iclass 11, count 2 2006.201.18:39:34.05#ibcon#about to read 3, iclass 11, count 2 2006.201.18:39:34.07#ibcon#read 3, iclass 11, count 2 2006.201.18:39:34.07#ibcon#about to read 4, iclass 11, count 2 2006.201.18:39:34.07#ibcon#read 4, iclass 11, count 2 2006.201.18:39:34.07#ibcon#about to read 5, iclass 11, count 2 2006.201.18:39:34.07#ibcon#read 5, iclass 11, count 2 2006.201.18:39:34.07#ibcon#about to read 6, iclass 11, count 2 2006.201.18:39:34.07#ibcon#read 6, iclass 11, count 2 2006.201.18:39:34.07#ibcon#end of sib2, iclass 11, count 2 2006.201.18:39:34.07#ibcon#*mode == 0, iclass 11, count 2 2006.201.18:39:34.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.18:39:34.07#ibcon#[27=AT08-04\r\n] 2006.201.18:39:34.07#ibcon#*before write, iclass 11, count 2 2006.201.18:39:34.07#ibcon#enter sib2, iclass 11, count 2 2006.201.18:39:34.07#ibcon#flushed, iclass 11, count 2 2006.201.18:39:34.07#ibcon#about to write, iclass 11, count 2 2006.201.18:39:34.07#ibcon#wrote, iclass 11, count 2 2006.201.18:39:34.07#ibcon#about to read 3, iclass 11, count 2 2006.201.18:39:34.10#ibcon#read 3, iclass 11, count 2 2006.201.18:39:34.10#ibcon#about to read 4, iclass 11, count 2 2006.201.18:39:34.10#ibcon#read 4, iclass 11, count 2 2006.201.18:39:34.10#ibcon#about to read 5, iclass 11, count 2 2006.201.18:39:34.10#ibcon#read 5, iclass 11, count 2 2006.201.18:39:34.10#ibcon#about to read 6, iclass 11, count 2 2006.201.18:39:34.10#ibcon#read 6, iclass 11, count 2 2006.201.18:39:34.10#ibcon#end of sib2, iclass 11, count 2 2006.201.18:39:34.10#ibcon#*after write, iclass 11, count 2 2006.201.18:39:34.10#ibcon#*before return 0, iclass 11, count 2 2006.201.18:39:34.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:34.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.18:39:34.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.18:39:34.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:39:34.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:34.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:34.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:34.22#ibcon#enter wrdev, iclass 11, count 0 2006.201.18:39:34.22#ibcon#first serial, iclass 11, count 0 2006.201.18:39:34.22#ibcon#enter sib2, iclass 11, count 0 2006.201.18:39:34.22#ibcon#flushed, iclass 11, count 0 2006.201.18:39:34.22#ibcon#about to write, iclass 11, count 0 2006.201.18:39:34.22#ibcon#wrote, iclass 11, count 0 2006.201.18:39:34.22#ibcon#about to read 3, iclass 11, count 0 2006.201.18:39:34.24#ibcon#read 3, iclass 11, count 0 2006.201.18:39:34.24#ibcon#about to read 4, iclass 11, count 0 2006.201.18:39:34.24#ibcon#read 4, iclass 11, count 0 2006.201.18:39:34.24#ibcon#about to read 5, iclass 11, count 0 2006.201.18:39:34.24#ibcon#read 5, iclass 11, count 0 2006.201.18:39:34.24#ibcon#about to read 6, iclass 11, count 0 2006.201.18:39:34.24#ibcon#read 6, iclass 11, count 0 2006.201.18:39:34.24#ibcon#end of sib2, iclass 11, count 0 2006.201.18:39:34.24#ibcon#*mode == 0, iclass 11, count 0 2006.201.18:39:34.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.18:39:34.24#ibcon#[27=USB\r\n] 2006.201.18:39:34.24#ibcon#*before write, iclass 11, count 0 2006.201.18:39:34.24#ibcon#enter sib2, iclass 11, count 0 2006.201.18:39:34.24#ibcon#flushed, iclass 11, count 0 2006.201.18:39:34.24#ibcon#about to write, iclass 11, count 0 2006.201.18:39:34.24#ibcon#wrote, iclass 11, count 0 2006.201.18:39:34.24#ibcon#about to read 3, iclass 11, count 0 2006.201.18:39:34.27#ibcon#read 3, iclass 11, count 0 2006.201.18:39:34.27#ibcon#about to read 4, iclass 11, count 0 2006.201.18:39:34.27#ibcon#read 4, iclass 11, count 0 2006.201.18:39:34.27#ibcon#about to read 5, iclass 11, count 0 2006.201.18:39:34.27#ibcon#read 5, iclass 11, count 0 2006.201.18:39:34.27#ibcon#about to read 6, iclass 11, count 0 2006.201.18:39:34.27#ibcon#read 6, iclass 11, count 0 2006.201.18:39:34.27#ibcon#end of sib2, iclass 11, count 0 2006.201.18:39:34.27#ibcon#*after write, iclass 11, count 0 2006.201.18:39:34.27#ibcon#*before return 0, iclass 11, count 0 2006.201.18:39:34.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:34.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.18:39:34.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.18:39:34.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.18:39:34.27$vck44/vabw=wide 2006.201.18:39:34.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.18:39:34.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.18:39:34.27#ibcon#ireg 8 cls_cnt 0 2006.201.18:39:34.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:34.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:34.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:34.27#ibcon#enter wrdev, iclass 13, count 0 2006.201.18:39:34.27#ibcon#first serial, iclass 13, count 0 2006.201.18:39:34.27#ibcon#enter sib2, iclass 13, count 0 2006.201.18:39:34.27#ibcon#flushed, iclass 13, count 0 2006.201.18:39:34.27#ibcon#about to write, iclass 13, count 0 2006.201.18:39:34.27#ibcon#wrote, iclass 13, count 0 2006.201.18:39:34.27#ibcon#about to read 3, iclass 13, count 0 2006.201.18:39:34.29#ibcon#read 3, iclass 13, count 0 2006.201.18:39:34.29#ibcon#about to read 4, iclass 13, count 0 2006.201.18:39:34.29#ibcon#read 4, iclass 13, count 0 2006.201.18:39:34.29#ibcon#about to read 5, iclass 13, count 0 2006.201.18:39:34.29#ibcon#read 5, iclass 13, count 0 2006.201.18:39:34.29#ibcon#about to read 6, iclass 13, count 0 2006.201.18:39:34.29#ibcon#read 6, iclass 13, count 0 2006.201.18:39:34.29#ibcon#end of sib2, iclass 13, count 0 2006.201.18:39:34.29#ibcon#*mode == 0, iclass 13, count 0 2006.201.18:39:34.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.18:39:34.29#ibcon#[25=BW32\r\n] 2006.201.18:39:34.29#ibcon#*before write, iclass 13, count 0 2006.201.18:39:34.29#ibcon#enter sib2, iclass 13, count 0 2006.201.18:39:34.29#ibcon#flushed, iclass 13, count 0 2006.201.18:39:34.29#ibcon#about to write, iclass 13, count 0 2006.201.18:39:34.29#ibcon#wrote, iclass 13, count 0 2006.201.18:39:34.29#ibcon#about to read 3, iclass 13, count 0 2006.201.18:39:34.32#ibcon#read 3, iclass 13, count 0 2006.201.18:39:34.32#ibcon#about to read 4, iclass 13, count 0 2006.201.18:39:34.32#ibcon#read 4, iclass 13, count 0 2006.201.18:39:34.32#ibcon#about to read 5, iclass 13, count 0 2006.201.18:39:34.32#ibcon#read 5, iclass 13, count 0 2006.201.18:39:34.32#ibcon#about to read 6, iclass 13, count 0 2006.201.18:39:34.32#ibcon#read 6, iclass 13, count 0 2006.201.18:39:34.32#ibcon#end of sib2, iclass 13, count 0 2006.201.18:39:34.32#ibcon#*after write, iclass 13, count 0 2006.201.18:39:34.32#ibcon#*before return 0, iclass 13, count 0 2006.201.18:39:34.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:34.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.18:39:34.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.18:39:34.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.18:39:34.32$vck44/vbbw=wide 2006.201.18:39:34.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.18:39:34.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.18:39:34.32#ibcon#ireg 8 cls_cnt 0 2006.201.18:39:34.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:39:34.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:39:34.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:39:34.39#ibcon#enter wrdev, iclass 15, count 0 2006.201.18:39:34.39#ibcon#first serial, iclass 15, count 0 2006.201.18:39:34.39#ibcon#enter sib2, iclass 15, count 0 2006.201.18:39:34.39#ibcon#flushed, iclass 15, count 0 2006.201.18:39:34.39#ibcon#about to write, iclass 15, count 0 2006.201.18:39:34.39#ibcon#wrote, iclass 15, count 0 2006.201.18:39:34.39#ibcon#about to read 3, iclass 15, count 0 2006.201.18:39:34.41#ibcon#read 3, iclass 15, count 0 2006.201.18:39:34.41#ibcon#about to read 4, iclass 15, count 0 2006.201.18:39:34.41#ibcon#read 4, iclass 15, count 0 2006.201.18:39:34.41#ibcon#about to read 5, iclass 15, count 0 2006.201.18:39:34.41#ibcon#read 5, iclass 15, count 0 2006.201.18:39:34.41#ibcon#about to read 6, iclass 15, count 0 2006.201.18:39:34.41#ibcon#read 6, iclass 15, count 0 2006.201.18:39:34.41#ibcon#end of sib2, iclass 15, count 0 2006.201.18:39:34.41#ibcon#*mode == 0, iclass 15, count 0 2006.201.18:39:34.41#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.18:39:34.41#ibcon#[27=BW32\r\n] 2006.201.18:39:34.41#ibcon#*before write, iclass 15, count 0 2006.201.18:39:34.41#ibcon#enter sib2, iclass 15, count 0 2006.201.18:39:34.41#ibcon#flushed, iclass 15, count 0 2006.201.18:39:34.41#ibcon#about to write, iclass 15, count 0 2006.201.18:39:34.41#ibcon#wrote, iclass 15, count 0 2006.201.18:39:34.41#ibcon#about to read 3, iclass 15, count 0 2006.201.18:39:34.44#ibcon#read 3, iclass 15, count 0 2006.201.18:39:34.44#ibcon#about to read 4, iclass 15, count 0 2006.201.18:39:34.44#ibcon#read 4, iclass 15, count 0 2006.201.18:39:34.44#ibcon#about to read 5, iclass 15, count 0 2006.201.18:39:34.44#ibcon#read 5, iclass 15, count 0 2006.201.18:39:34.44#ibcon#about to read 6, iclass 15, count 0 2006.201.18:39:34.44#ibcon#read 6, iclass 15, count 0 2006.201.18:39:34.44#ibcon#end of sib2, iclass 15, count 0 2006.201.18:39:34.44#ibcon#*after write, iclass 15, count 0 2006.201.18:39:34.44#ibcon#*before return 0, iclass 15, count 0 2006.201.18:39:34.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:39:34.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:39:34.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.18:39:34.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.18:39:34.44$setupk4/ifdk4 2006.201.18:39:34.44$ifdk4/lo= 2006.201.18:39:34.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:39:34.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:39:34.44$ifdk4/patch= 2006.201.18:39:34.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:39:34.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:39:34.44$setupk4/!*+20s 2006.201.18:39:36.38#abcon#<5=/02 0.6 1.9 20.501001002.1\r\n> 2006.201.18:39:36.40#abcon#{5=INTERFACE CLEAR} 2006.201.18:39:36.46#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:39:44.14#trakl#Source acquired 2006.201.18:39:45.14#flagr#flagr/antenna,acquired 2006.201.18:39:46.55#abcon#<5=/02 0.6 1.9 20.501001002.1\r\n> 2006.201.18:39:46.57#abcon#{5=INTERFACE CLEAR} 2006.201.18:39:46.63#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:39:48.94$setupk4/"tpicd 2006.201.18:39:48.94$setupk4/echo=off 2006.201.18:39:48.94$setupk4/xlog=off 2006.201.18:39:48.94:!2006.201.18:39:57 2006.201.18:39:57.00:preob 2006.201.18:39:58.14/onsource/TRACKING 2006.201.18:39:58.14:!2006.201.18:40:07 2006.201.18:40:07.00:"tape 2006.201.18:40:07.00:"st=record 2006.201.18:40:07.00:data_valid=on 2006.201.18:40:07.00:midob 2006.201.18:40:07.14/onsource/TRACKING 2006.201.18:40:07.14/wx/20.50,1002.1,100 2006.201.18:40:07.25/cable/+6.4788E-03 2006.201.18:40:08.34/va/01,08,usb,yes,41,43 2006.201.18:40:08.34/va/02,07,usb,yes,44,45 2006.201.18:40:08.34/va/03,08,usb,yes,40,41 2006.201.18:40:08.34/va/04,07,usb,yes,45,48 2006.201.18:40:08.34/va/05,04,usb,yes,40,41 2006.201.18:40:08.34/va/06,05,usb,yes,40,40 2006.201.18:40:08.34/va/07,05,usb,yes,39,41 2006.201.18:40:08.34/va/08,04,usb,yes,39,46 2006.201.18:40:08.57/valo/01,524.99,yes,locked 2006.201.18:40:08.57/valo/02,534.99,yes,locked 2006.201.18:40:08.57/valo/03,564.99,yes,locked 2006.201.18:40:08.57/valo/04,624.99,yes,locked 2006.201.18:40:08.57/valo/05,734.99,yes,locked 2006.201.18:40:08.57/valo/06,814.99,yes,locked 2006.201.18:40:08.57/valo/07,864.99,yes,locked 2006.201.18:40:08.57/valo/08,884.99,yes,locked 2006.201.18:40:09.66/vb/01,04,usb,yes,29,27 2006.201.18:40:09.66/vb/02,05,usb,yes,28,28 2006.201.18:40:09.66/vb/03,04,usb,yes,29,32 2006.201.18:40:09.66/vb/04,05,usb,yes,29,28 2006.201.18:40:09.66/vb/05,04,usb,yes,26,28 2006.201.18:40:09.66/vb/06,04,usb,yes,30,26 2006.201.18:40:09.66/vb/07,04,usb,yes,30,30 2006.201.18:40:09.66/vb/08,04,usb,yes,27,31 2006.201.18:40:09.90/vblo/01,629.99,yes,locked 2006.201.18:40:09.90/vblo/02,634.99,yes,locked 2006.201.18:40:09.90/vblo/03,649.99,yes,locked 2006.201.18:40:09.90/vblo/04,679.99,yes,locked 2006.201.18:40:09.90/vblo/05,709.99,yes,locked 2006.201.18:40:09.90/vblo/06,719.99,yes,locked 2006.201.18:40:09.90/vblo/07,734.99,yes,locked 2006.201.18:40:09.90/vblo/08,744.99,yes,locked 2006.201.18:40:10.05/vabw/8 2006.201.18:40:10.20/vbbw/8 2006.201.18:40:10.29/xfe/off,on,15.2 2006.201.18:40:10.66/ifatt/23,28,28,28 2006.201.18:40:11.06/fmout-gps/S +4.52E-07 2006.201.18:40:11.10:!2006.201.18:42:57 2006.201.18:42:57.00:data_valid=off 2006.201.18:42:57.00:"et 2006.201.18:42:57.00:!+3s 2006.201.18:43:00.02:"tape 2006.201.18:43:00.02:postob 2006.201.18:43:00.13/cable/+6.4782E-03 2006.201.18:43:00.13/wx/20.49,1002.1,100 2006.201.18:43:00.21/fmout-gps/S +4.50E-07 2006.201.18:43:00.21:scan_name=201-1845,jd0607,120 2006.201.18:43:00.21:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.18:43:01.14#flagr#flagr/antenna,new-source 2006.201.18:43:01.14:checkk5 2006.201.18:43:01.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:43:01.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:43:02.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:43:02.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:43:03.04/chk_obsdata//k5ts1/T2011840??a.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.18:43:03.40/chk_obsdata//k5ts2/T2011840??b.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.18:43:03.77/chk_obsdata//k5ts3/T2011840??c.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.18:43:04.14/chk_obsdata//k5ts4/T2011840??d.dat file size is correct (nominal:680MB, actual:676MB). 2006.201.18:43:04.83/k5log//k5ts1_log_newline 2006.201.18:43:05.52/k5log//k5ts2_log_newline 2006.201.18:43:06.20/k5log//k5ts3_log_newline 2006.201.18:43:06.89/k5log//k5ts4_log_newline 2006.201.18:43:06.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:43:06.91:setupk4=1 2006.201.18:43:06.91$setupk4/echo=on 2006.201.18:43:06.91$setupk4/pcalon 2006.201.18:43:06.91$pcalon/"no phase cal control is implemented here 2006.201.18:43:06.91$setupk4/"tpicd=stop 2006.201.18:43:06.91$setupk4/"rec=synch_on 2006.201.18:43:06.91$setupk4/"rec_mode=128 2006.201.18:43:06.91$setupk4/!* 2006.201.18:43:06.91$setupk4/recpk4 2006.201.18:43:06.91$recpk4/recpatch= 2006.201.18:43:06.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:43:06.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:43:06.92$setupk4/vck44 2006.201.18:43:06.92$vck44/valo=1,524.99 2006.201.18:43:06.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.18:43:06.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.18:43:06.92#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:06.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:43:06.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:43:06.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:43:06.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:43:06.92#ibcon#first serial, iclass 32, count 0 2006.201.18:43:06.92#ibcon#enter sib2, iclass 32, count 0 2006.201.18:43:06.92#ibcon#flushed, iclass 32, count 0 2006.201.18:43:06.92#ibcon#about to write, iclass 32, count 0 2006.201.18:43:06.92#ibcon#wrote, iclass 32, count 0 2006.201.18:43:06.92#ibcon#about to read 3, iclass 32, count 0 2006.201.18:43:06.95#ibcon#read 3, iclass 32, count 0 2006.201.18:43:06.95#ibcon#about to read 4, iclass 32, count 0 2006.201.18:43:06.95#ibcon#read 4, iclass 32, count 0 2006.201.18:43:06.95#ibcon#about to read 5, iclass 32, count 0 2006.201.18:43:06.95#ibcon#read 5, iclass 32, count 0 2006.201.18:43:06.95#ibcon#about to read 6, iclass 32, count 0 2006.201.18:43:06.95#ibcon#read 6, iclass 32, count 0 2006.201.18:43:06.95#ibcon#end of sib2, iclass 32, count 0 2006.201.18:43:06.95#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:43:06.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:43:06.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:43:06.95#ibcon#*before write, iclass 32, count 0 2006.201.18:43:06.95#ibcon#enter sib2, iclass 32, count 0 2006.201.18:43:06.95#ibcon#flushed, iclass 32, count 0 2006.201.18:43:06.95#ibcon#about to write, iclass 32, count 0 2006.201.18:43:06.95#ibcon#wrote, iclass 32, count 0 2006.201.18:43:06.95#ibcon#about to read 3, iclass 32, count 0 2006.201.18:43:07.01#ibcon#read 3, iclass 32, count 0 2006.201.18:43:07.01#ibcon#about to read 4, iclass 32, count 0 2006.201.18:43:07.01#ibcon#read 4, iclass 32, count 0 2006.201.18:43:07.01#ibcon#about to read 5, iclass 32, count 0 2006.201.18:43:07.01#ibcon#read 5, iclass 32, count 0 2006.201.18:43:07.01#ibcon#about to read 6, iclass 32, count 0 2006.201.18:43:07.01#ibcon#read 6, iclass 32, count 0 2006.201.18:43:07.01#ibcon#end of sib2, iclass 32, count 0 2006.201.18:43:07.01#ibcon#*after write, iclass 32, count 0 2006.201.18:43:07.01#ibcon#*before return 0, iclass 32, count 0 2006.201.18:43:07.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:43:07.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.18:43:07.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:43:07.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:43:07.01$vck44/va=1,8 2006.201.18:43:07.01#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.18:43:07.01#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.18:43:07.01#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:07.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:43:07.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:43:07.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:43:07.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.18:43:07.01#ibcon#first serial, iclass 34, count 2 2006.201.18:43:07.01#ibcon#enter sib2, iclass 34, count 2 2006.201.18:43:07.01#ibcon#flushed, iclass 34, count 2 2006.201.18:43:07.01#ibcon#about to write, iclass 34, count 2 2006.201.18:43:07.01#ibcon#wrote, iclass 34, count 2 2006.201.18:43:07.01#ibcon#about to read 3, iclass 34, count 2 2006.201.18:43:07.03#ibcon#read 3, iclass 34, count 2 2006.201.18:43:07.03#ibcon#about to read 4, iclass 34, count 2 2006.201.18:43:07.03#ibcon#read 4, iclass 34, count 2 2006.201.18:43:07.03#ibcon#about to read 5, iclass 34, count 2 2006.201.18:43:07.03#ibcon#read 5, iclass 34, count 2 2006.201.18:43:07.03#ibcon#about to read 6, iclass 34, count 2 2006.201.18:43:07.03#ibcon#read 6, iclass 34, count 2 2006.201.18:43:07.03#ibcon#end of sib2, iclass 34, count 2 2006.201.18:43:07.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.18:43:07.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.18:43:07.03#ibcon#[25=AT01-08\r\n] 2006.201.18:43:07.03#ibcon#*before write, iclass 34, count 2 2006.201.18:43:07.03#ibcon#enter sib2, iclass 34, count 2 2006.201.18:43:07.03#ibcon#flushed, iclass 34, count 2 2006.201.18:43:07.03#ibcon#about to write, iclass 34, count 2 2006.201.18:43:07.03#ibcon#wrote, iclass 34, count 2 2006.201.18:43:07.03#ibcon#about to read 3, iclass 34, count 2 2006.201.18:43:07.07#ibcon#read 3, iclass 34, count 2 2006.201.18:43:07.07#ibcon#about to read 4, iclass 34, count 2 2006.201.18:43:07.07#ibcon#read 4, iclass 34, count 2 2006.201.18:43:07.07#ibcon#about to read 5, iclass 34, count 2 2006.201.18:43:07.07#ibcon#read 5, iclass 34, count 2 2006.201.18:43:07.07#ibcon#about to read 6, iclass 34, count 2 2006.201.18:43:07.07#ibcon#read 6, iclass 34, count 2 2006.201.18:43:07.07#ibcon#end of sib2, iclass 34, count 2 2006.201.18:43:07.07#ibcon#*after write, iclass 34, count 2 2006.201.18:43:07.07#ibcon#*before return 0, iclass 34, count 2 2006.201.18:43:07.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:43:07.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.18:43:07.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.18:43:07.07#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:07.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:43:07.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:43:07.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:43:07.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:43:07.19#ibcon#first serial, iclass 34, count 0 2006.201.18:43:07.19#ibcon#enter sib2, iclass 34, count 0 2006.201.18:43:07.19#ibcon#flushed, iclass 34, count 0 2006.201.18:43:07.19#ibcon#about to write, iclass 34, count 0 2006.201.18:43:07.19#ibcon#wrote, iclass 34, count 0 2006.201.18:43:07.19#ibcon#about to read 3, iclass 34, count 0 2006.201.18:43:07.22#ibcon#read 3, iclass 34, count 0 2006.201.18:43:07.22#ibcon#about to read 4, iclass 34, count 0 2006.201.18:43:07.22#ibcon#read 4, iclass 34, count 0 2006.201.18:43:07.22#ibcon#about to read 5, iclass 34, count 0 2006.201.18:43:07.22#ibcon#read 5, iclass 34, count 0 2006.201.18:43:07.22#ibcon#about to read 6, iclass 34, count 0 2006.201.18:43:07.22#ibcon#read 6, iclass 34, count 0 2006.201.18:43:07.22#ibcon#end of sib2, iclass 34, count 0 2006.201.18:43:07.22#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:43:07.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:43:07.22#ibcon#[25=USB\r\n] 2006.201.18:43:07.22#ibcon#*before write, iclass 34, count 0 2006.201.18:43:07.22#ibcon#enter sib2, iclass 34, count 0 2006.201.18:43:07.22#ibcon#flushed, iclass 34, count 0 2006.201.18:43:07.22#ibcon#about to write, iclass 34, count 0 2006.201.18:43:07.22#ibcon#wrote, iclass 34, count 0 2006.201.18:43:07.22#ibcon#about to read 3, iclass 34, count 0 2006.201.18:43:07.25#ibcon#read 3, iclass 34, count 0 2006.201.18:43:07.25#ibcon#about to read 4, iclass 34, count 0 2006.201.18:43:07.25#ibcon#read 4, iclass 34, count 0 2006.201.18:43:07.25#ibcon#about to read 5, iclass 34, count 0 2006.201.18:43:07.25#ibcon#read 5, iclass 34, count 0 2006.201.18:43:07.25#ibcon#about to read 6, iclass 34, count 0 2006.201.18:43:07.25#ibcon#read 6, iclass 34, count 0 2006.201.18:43:07.25#ibcon#end of sib2, iclass 34, count 0 2006.201.18:43:07.25#ibcon#*after write, iclass 34, count 0 2006.201.18:43:07.25#ibcon#*before return 0, iclass 34, count 0 2006.201.18:43:07.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:43:07.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.18:43:07.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:43:07.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:43:07.25$vck44/valo=2,534.99 2006.201.18:43:07.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.18:43:07.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.18:43:07.25#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:07.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:43:07.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:43:07.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:43:07.25#ibcon#enter wrdev, iclass 36, count 0 2006.201.18:43:07.25#ibcon#first serial, iclass 36, count 0 2006.201.18:43:07.25#ibcon#enter sib2, iclass 36, count 0 2006.201.18:43:07.25#ibcon#flushed, iclass 36, count 0 2006.201.18:43:07.25#ibcon#about to write, iclass 36, count 0 2006.201.18:43:07.25#ibcon#wrote, iclass 36, count 0 2006.201.18:43:07.25#ibcon#about to read 3, iclass 36, count 0 2006.201.18:43:07.27#ibcon#read 3, iclass 36, count 0 2006.201.18:43:07.27#ibcon#about to read 4, iclass 36, count 0 2006.201.18:43:07.27#ibcon#read 4, iclass 36, count 0 2006.201.18:43:07.27#ibcon#about to read 5, iclass 36, count 0 2006.201.18:43:07.27#ibcon#read 5, iclass 36, count 0 2006.201.18:43:07.27#ibcon#about to read 6, iclass 36, count 0 2006.201.18:43:07.27#ibcon#read 6, iclass 36, count 0 2006.201.18:43:07.27#ibcon#end of sib2, iclass 36, count 0 2006.201.18:43:07.27#ibcon#*mode == 0, iclass 36, count 0 2006.201.18:43:07.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.18:43:07.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:43:07.27#ibcon#*before write, iclass 36, count 0 2006.201.18:43:07.27#ibcon#enter sib2, iclass 36, count 0 2006.201.18:43:07.27#ibcon#flushed, iclass 36, count 0 2006.201.18:43:07.27#ibcon#about to write, iclass 36, count 0 2006.201.18:43:07.27#ibcon#wrote, iclass 36, count 0 2006.201.18:43:07.27#ibcon#about to read 3, iclass 36, count 0 2006.201.18:43:07.31#ibcon#read 3, iclass 36, count 0 2006.201.18:43:07.31#ibcon#about to read 4, iclass 36, count 0 2006.201.18:43:07.31#ibcon#read 4, iclass 36, count 0 2006.201.18:43:07.31#ibcon#about to read 5, iclass 36, count 0 2006.201.18:43:07.31#ibcon#read 5, iclass 36, count 0 2006.201.18:43:07.31#ibcon#about to read 6, iclass 36, count 0 2006.201.18:43:07.31#ibcon#read 6, iclass 36, count 0 2006.201.18:43:07.31#ibcon#end of sib2, iclass 36, count 0 2006.201.18:43:07.31#ibcon#*after write, iclass 36, count 0 2006.201.18:43:07.31#ibcon#*before return 0, iclass 36, count 0 2006.201.18:43:07.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:43:07.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.18:43:07.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.18:43:07.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.18:43:07.31$vck44/va=2,7 2006.201.18:43:07.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.18:43:07.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.18:43:07.31#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:07.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:43:07.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:43:07.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:43:07.37#ibcon#enter wrdev, iclass 38, count 2 2006.201.18:43:07.37#ibcon#first serial, iclass 38, count 2 2006.201.18:43:07.37#ibcon#enter sib2, iclass 38, count 2 2006.201.18:43:07.37#ibcon#flushed, iclass 38, count 2 2006.201.18:43:07.37#ibcon#about to write, iclass 38, count 2 2006.201.18:43:07.37#ibcon#wrote, iclass 38, count 2 2006.201.18:43:07.37#ibcon#about to read 3, iclass 38, count 2 2006.201.18:43:07.39#ibcon#read 3, iclass 38, count 2 2006.201.18:43:07.39#ibcon#about to read 4, iclass 38, count 2 2006.201.18:43:07.39#ibcon#read 4, iclass 38, count 2 2006.201.18:43:07.39#ibcon#about to read 5, iclass 38, count 2 2006.201.18:43:07.39#ibcon#read 5, iclass 38, count 2 2006.201.18:43:07.39#ibcon#about to read 6, iclass 38, count 2 2006.201.18:43:07.39#ibcon#read 6, iclass 38, count 2 2006.201.18:43:07.39#ibcon#end of sib2, iclass 38, count 2 2006.201.18:43:07.39#ibcon#*mode == 0, iclass 38, count 2 2006.201.18:43:07.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.18:43:07.39#ibcon#[25=AT02-07\r\n] 2006.201.18:43:07.39#ibcon#*before write, iclass 38, count 2 2006.201.18:43:07.39#ibcon#enter sib2, iclass 38, count 2 2006.201.18:43:07.39#ibcon#flushed, iclass 38, count 2 2006.201.18:43:07.39#ibcon#about to write, iclass 38, count 2 2006.201.18:43:07.39#ibcon#wrote, iclass 38, count 2 2006.201.18:43:07.39#ibcon#about to read 3, iclass 38, count 2 2006.201.18:43:07.42#ibcon#read 3, iclass 38, count 2 2006.201.18:43:07.42#ibcon#about to read 4, iclass 38, count 2 2006.201.18:43:07.42#ibcon#read 4, iclass 38, count 2 2006.201.18:43:07.42#ibcon#about to read 5, iclass 38, count 2 2006.201.18:43:07.42#ibcon#read 5, iclass 38, count 2 2006.201.18:43:07.42#ibcon#about to read 6, iclass 38, count 2 2006.201.18:43:07.42#ibcon#read 6, iclass 38, count 2 2006.201.18:43:07.42#ibcon#end of sib2, iclass 38, count 2 2006.201.18:43:07.42#ibcon#*after write, iclass 38, count 2 2006.201.18:43:07.42#ibcon#*before return 0, iclass 38, count 2 2006.201.18:43:07.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:43:07.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.18:43:07.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.18:43:07.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:07.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:43:07.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:43:07.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:43:07.54#ibcon#enter wrdev, iclass 38, count 0 2006.201.18:43:07.54#ibcon#first serial, iclass 38, count 0 2006.201.18:43:07.54#ibcon#enter sib2, iclass 38, count 0 2006.201.18:43:07.54#ibcon#flushed, iclass 38, count 0 2006.201.18:43:07.54#ibcon#about to write, iclass 38, count 0 2006.201.18:43:07.54#ibcon#wrote, iclass 38, count 0 2006.201.18:43:07.54#ibcon#about to read 3, iclass 38, count 0 2006.201.18:43:07.56#ibcon#read 3, iclass 38, count 0 2006.201.18:43:07.56#ibcon#about to read 4, iclass 38, count 0 2006.201.18:43:07.56#ibcon#read 4, iclass 38, count 0 2006.201.18:43:07.56#ibcon#about to read 5, iclass 38, count 0 2006.201.18:43:07.56#ibcon#read 5, iclass 38, count 0 2006.201.18:43:07.56#ibcon#about to read 6, iclass 38, count 0 2006.201.18:43:07.56#ibcon#read 6, iclass 38, count 0 2006.201.18:43:07.56#ibcon#end of sib2, iclass 38, count 0 2006.201.18:43:07.56#ibcon#*mode == 0, iclass 38, count 0 2006.201.18:43:07.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.18:43:07.56#ibcon#[25=USB\r\n] 2006.201.18:43:07.56#ibcon#*before write, iclass 38, count 0 2006.201.18:43:07.56#ibcon#enter sib2, iclass 38, count 0 2006.201.18:43:07.56#ibcon#flushed, iclass 38, count 0 2006.201.18:43:07.56#ibcon#about to write, iclass 38, count 0 2006.201.18:43:07.56#ibcon#wrote, iclass 38, count 0 2006.201.18:43:07.56#ibcon#about to read 3, iclass 38, count 0 2006.201.18:43:07.59#ibcon#read 3, iclass 38, count 0 2006.201.18:43:07.59#ibcon#about to read 4, iclass 38, count 0 2006.201.18:43:07.59#ibcon#read 4, iclass 38, count 0 2006.201.18:43:07.59#ibcon#about to read 5, iclass 38, count 0 2006.201.18:43:07.59#ibcon#read 5, iclass 38, count 0 2006.201.18:43:07.59#ibcon#about to read 6, iclass 38, count 0 2006.201.18:43:07.59#ibcon#read 6, iclass 38, count 0 2006.201.18:43:07.59#ibcon#end of sib2, iclass 38, count 0 2006.201.18:43:07.59#ibcon#*after write, iclass 38, count 0 2006.201.18:43:07.59#ibcon#*before return 0, iclass 38, count 0 2006.201.18:43:07.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:43:07.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.18:43:07.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.18:43:07.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.18:43:07.59$vck44/valo=3,564.99 2006.201.18:43:07.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.18:43:07.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.18:43:07.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:07.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:07.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:07.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:07.59#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:43:07.59#ibcon#first serial, iclass 40, count 0 2006.201.18:43:07.59#ibcon#enter sib2, iclass 40, count 0 2006.201.18:43:07.59#ibcon#flushed, iclass 40, count 0 2006.201.18:43:07.59#ibcon#about to write, iclass 40, count 0 2006.201.18:43:07.59#ibcon#wrote, iclass 40, count 0 2006.201.18:43:07.59#ibcon#about to read 3, iclass 40, count 0 2006.201.18:43:07.61#ibcon#read 3, iclass 40, count 0 2006.201.18:43:07.61#ibcon#about to read 4, iclass 40, count 0 2006.201.18:43:07.61#ibcon#read 4, iclass 40, count 0 2006.201.18:43:07.61#ibcon#about to read 5, iclass 40, count 0 2006.201.18:43:07.61#ibcon#read 5, iclass 40, count 0 2006.201.18:43:07.61#ibcon#about to read 6, iclass 40, count 0 2006.201.18:43:07.61#ibcon#read 6, iclass 40, count 0 2006.201.18:43:07.61#ibcon#end of sib2, iclass 40, count 0 2006.201.18:43:07.61#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:43:07.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:43:07.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:43:07.61#ibcon#*before write, iclass 40, count 0 2006.201.18:43:07.61#ibcon#enter sib2, iclass 40, count 0 2006.201.18:43:07.61#ibcon#flushed, iclass 40, count 0 2006.201.18:43:07.61#ibcon#about to write, iclass 40, count 0 2006.201.18:43:07.61#ibcon#wrote, iclass 40, count 0 2006.201.18:43:07.61#ibcon#about to read 3, iclass 40, count 0 2006.201.18:43:07.66#ibcon#read 3, iclass 40, count 0 2006.201.18:43:07.66#ibcon#about to read 4, iclass 40, count 0 2006.201.18:43:07.66#ibcon#read 4, iclass 40, count 0 2006.201.18:43:07.66#ibcon#about to read 5, iclass 40, count 0 2006.201.18:43:07.66#ibcon#read 5, iclass 40, count 0 2006.201.18:43:07.66#ibcon#about to read 6, iclass 40, count 0 2006.201.18:43:07.66#ibcon#read 6, iclass 40, count 0 2006.201.18:43:07.66#ibcon#end of sib2, iclass 40, count 0 2006.201.18:43:07.66#ibcon#*after write, iclass 40, count 0 2006.201.18:43:07.66#ibcon#*before return 0, iclass 40, count 0 2006.201.18:43:07.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:07.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:07.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:43:07.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:43:07.66$vck44/va=3,8 2006.201.18:43:07.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.18:43:07.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.18:43:07.66#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:07.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:07.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:07.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:07.71#ibcon#enter wrdev, iclass 4, count 2 2006.201.18:43:07.71#ibcon#first serial, iclass 4, count 2 2006.201.18:43:07.71#ibcon#enter sib2, iclass 4, count 2 2006.201.18:43:07.71#ibcon#flushed, iclass 4, count 2 2006.201.18:43:07.71#ibcon#about to write, iclass 4, count 2 2006.201.18:43:07.71#ibcon#wrote, iclass 4, count 2 2006.201.18:43:07.71#ibcon#about to read 3, iclass 4, count 2 2006.201.18:43:07.73#ibcon#read 3, iclass 4, count 2 2006.201.18:43:07.73#ibcon#about to read 4, iclass 4, count 2 2006.201.18:43:07.73#ibcon#read 4, iclass 4, count 2 2006.201.18:43:07.73#ibcon#about to read 5, iclass 4, count 2 2006.201.18:43:07.73#ibcon#read 5, iclass 4, count 2 2006.201.18:43:07.73#ibcon#about to read 6, iclass 4, count 2 2006.201.18:43:07.73#ibcon#read 6, iclass 4, count 2 2006.201.18:43:07.73#ibcon#end of sib2, iclass 4, count 2 2006.201.18:43:07.73#ibcon#*mode == 0, iclass 4, count 2 2006.201.18:43:07.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.18:43:07.73#ibcon#[25=AT03-08\r\n] 2006.201.18:43:07.73#ibcon#*before write, iclass 4, count 2 2006.201.18:43:07.73#ibcon#enter sib2, iclass 4, count 2 2006.201.18:43:07.73#ibcon#flushed, iclass 4, count 2 2006.201.18:43:07.73#ibcon#about to write, iclass 4, count 2 2006.201.18:43:07.73#ibcon#wrote, iclass 4, count 2 2006.201.18:43:07.73#ibcon#about to read 3, iclass 4, count 2 2006.201.18:43:07.76#ibcon#read 3, iclass 4, count 2 2006.201.18:43:07.76#ibcon#about to read 4, iclass 4, count 2 2006.201.18:43:07.76#ibcon#read 4, iclass 4, count 2 2006.201.18:43:07.76#ibcon#about to read 5, iclass 4, count 2 2006.201.18:43:07.76#ibcon#read 5, iclass 4, count 2 2006.201.18:43:07.76#ibcon#about to read 6, iclass 4, count 2 2006.201.18:43:07.76#ibcon#read 6, iclass 4, count 2 2006.201.18:43:07.76#ibcon#end of sib2, iclass 4, count 2 2006.201.18:43:07.76#ibcon#*after write, iclass 4, count 2 2006.201.18:43:07.76#ibcon#*before return 0, iclass 4, count 2 2006.201.18:43:07.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:07.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:07.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.18:43:07.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:07.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:07.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:07.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:07.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:43:07.88#ibcon#first serial, iclass 4, count 0 2006.201.18:43:07.88#ibcon#enter sib2, iclass 4, count 0 2006.201.18:43:07.88#ibcon#flushed, iclass 4, count 0 2006.201.18:43:07.88#ibcon#about to write, iclass 4, count 0 2006.201.18:43:07.88#ibcon#wrote, iclass 4, count 0 2006.201.18:43:07.88#ibcon#about to read 3, iclass 4, count 0 2006.201.18:43:07.90#ibcon#read 3, iclass 4, count 0 2006.201.18:43:07.90#ibcon#about to read 4, iclass 4, count 0 2006.201.18:43:07.90#ibcon#read 4, iclass 4, count 0 2006.201.18:43:07.90#ibcon#about to read 5, iclass 4, count 0 2006.201.18:43:07.90#ibcon#read 5, iclass 4, count 0 2006.201.18:43:07.90#ibcon#about to read 6, iclass 4, count 0 2006.201.18:43:07.90#ibcon#read 6, iclass 4, count 0 2006.201.18:43:07.90#ibcon#end of sib2, iclass 4, count 0 2006.201.18:43:07.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:43:07.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:43:07.90#ibcon#[25=USB\r\n] 2006.201.18:43:07.90#ibcon#*before write, iclass 4, count 0 2006.201.18:43:07.90#ibcon#enter sib2, iclass 4, count 0 2006.201.18:43:07.90#ibcon#flushed, iclass 4, count 0 2006.201.18:43:07.90#ibcon#about to write, iclass 4, count 0 2006.201.18:43:07.90#ibcon#wrote, iclass 4, count 0 2006.201.18:43:07.90#ibcon#about to read 3, iclass 4, count 0 2006.201.18:43:07.93#ibcon#read 3, iclass 4, count 0 2006.201.18:43:07.93#ibcon#about to read 4, iclass 4, count 0 2006.201.18:43:07.93#ibcon#read 4, iclass 4, count 0 2006.201.18:43:07.93#ibcon#about to read 5, iclass 4, count 0 2006.201.18:43:07.93#ibcon#read 5, iclass 4, count 0 2006.201.18:43:07.93#ibcon#about to read 6, iclass 4, count 0 2006.201.18:43:07.93#ibcon#read 6, iclass 4, count 0 2006.201.18:43:07.93#ibcon#end of sib2, iclass 4, count 0 2006.201.18:43:07.93#ibcon#*after write, iclass 4, count 0 2006.201.18:43:07.93#ibcon#*before return 0, iclass 4, count 0 2006.201.18:43:07.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:07.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:07.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:43:07.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:43:07.93$vck44/valo=4,624.99 2006.201.18:43:07.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.18:43:07.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.18:43:07.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:07.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:07.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:07.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:07.93#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:43:07.93#ibcon#first serial, iclass 6, count 0 2006.201.18:43:07.93#ibcon#enter sib2, iclass 6, count 0 2006.201.18:43:07.93#ibcon#flushed, iclass 6, count 0 2006.201.18:43:07.93#ibcon#about to write, iclass 6, count 0 2006.201.18:43:07.93#ibcon#wrote, iclass 6, count 0 2006.201.18:43:07.93#ibcon#about to read 3, iclass 6, count 0 2006.201.18:43:07.95#ibcon#read 3, iclass 6, count 0 2006.201.18:43:07.95#ibcon#about to read 4, iclass 6, count 0 2006.201.18:43:07.95#ibcon#read 4, iclass 6, count 0 2006.201.18:43:07.95#ibcon#about to read 5, iclass 6, count 0 2006.201.18:43:07.95#ibcon#read 5, iclass 6, count 0 2006.201.18:43:07.95#ibcon#about to read 6, iclass 6, count 0 2006.201.18:43:07.95#ibcon#read 6, iclass 6, count 0 2006.201.18:43:07.95#ibcon#end of sib2, iclass 6, count 0 2006.201.18:43:07.95#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:43:07.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:43:07.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:43:07.95#ibcon#*before write, iclass 6, count 0 2006.201.18:43:07.95#ibcon#enter sib2, iclass 6, count 0 2006.201.18:43:07.95#ibcon#flushed, iclass 6, count 0 2006.201.18:43:07.95#ibcon#about to write, iclass 6, count 0 2006.201.18:43:07.95#ibcon#wrote, iclass 6, count 0 2006.201.18:43:07.95#ibcon#about to read 3, iclass 6, count 0 2006.201.18:43:08.00#ibcon#read 3, iclass 6, count 0 2006.201.18:43:08.00#ibcon#about to read 4, iclass 6, count 0 2006.201.18:43:08.00#ibcon#read 4, iclass 6, count 0 2006.201.18:43:08.00#ibcon#about to read 5, iclass 6, count 0 2006.201.18:43:08.00#ibcon#read 5, iclass 6, count 0 2006.201.18:43:08.00#ibcon#about to read 6, iclass 6, count 0 2006.201.18:43:08.00#ibcon#read 6, iclass 6, count 0 2006.201.18:43:08.00#ibcon#end of sib2, iclass 6, count 0 2006.201.18:43:08.00#ibcon#*after write, iclass 6, count 0 2006.201.18:43:08.00#ibcon#*before return 0, iclass 6, count 0 2006.201.18:43:08.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:08.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:08.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:43:08.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:43:08.00$vck44/va=4,7 2006.201.18:43:08.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.18:43:08.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.18:43:08.00#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:08.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:08.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:08.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:08.05#ibcon#enter wrdev, iclass 10, count 2 2006.201.18:43:08.05#ibcon#first serial, iclass 10, count 2 2006.201.18:43:08.05#ibcon#enter sib2, iclass 10, count 2 2006.201.18:43:08.05#ibcon#flushed, iclass 10, count 2 2006.201.18:43:08.05#ibcon#about to write, iclass 10, count 2 2006.201.18:43:08.05#ibcon#wrote, iclass 10, count 2 2006.201.18:43:08.05#ibcon#about to read 3, iclass 10, count 2 2006.201.18:43:08.07#ibcon#read 3, iclass 10, count 2 2006.201.18:43:08.07#ibcon#about to read 4, iclass 10, count 2 2006.201.18:43:08.07#ibcon#read 4, iclass 10, count 2 2006.201.18:43:08.07#ibcon#about to read 5, iclass 10, count 2 2006.201.18:43:08.07#ibcon#read 5, iclass 10, count 2 2006.201.18:43:08.07#ibcon#about to read 6, iclass 10, count 2 2006.201.18:43:08.07#ibcon#read 6, iclass 10, count 2 2006.201.18:43:08.07#ibcon#end of sib2, iclass 10, count 2 2006.201.18:43:08.07#ibcon#*mode == 0, iclass 10, count 2 2006.201.18:43:08.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.18:43:08.07#ibcon#[25=AT04-07\r\n] 2006.201.18:43:08.07#ibcon#*before write, iclass 10, count 2 2006.201.18:43:08.07#ibcon#enter sib2, iclass 10, count 2 2006.201.18:43:08.07#ibcon#flushed, iclass 10, count 2 2006.201.18:43:08.07#ibcon#about to write, iclass 10, count 2 2006.201.18:43:08.07#ibcon#wrote, iclass 10, count 2 2006.201.18:43:08.07#ibcon#about to read 3, iclass 10, count 2 2006.201.18:43:08.10#ibcon#read 3, iclass 10, count 2 2006.201.18:43:08.10#ibcon#about to read 4, iclass 10, count 2 2006.201.18:43:08.10#ibcon#read 4, iclass 10, count 2 2006.201.18:43:08.10#ibcon#about to read 5, iclass 10, count 2 2006.201.18:43:08.10#ibcon#read 5, iclass 10, count 2 2006.201.18:43:08.10#ibcon#about to read 6, iclass 10, count 2 2006.201.18:43:08.10#ibcon#read 6, iclass 10, count 2 2006.201.18:43:08.10#ibcon#end of sib2, iclass 10, count 2 2006.201.18:43:08.10#ibcon#*after write, iclass 10, count 2 2006.201.18:43:08.10#ibcon#*before return 0, iclass 10, count 2 2006.201.18:43:08.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:08.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:08.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.18:43:08.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:08.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:08.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:08.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:08.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:43:08.22#ibcon#first serial, iclass 10, count 0 2006.201.18:43:08.22#ibcon#enter sib2, iclass 10, count 0 2006.201.18:43:08.22#ibcon#flushed, iclass 10, count 0 2006.201.18:43:08.22#ibcon#about to write, iclass 10, count 0 2006.201.18:43:08.22#ibcon#wrote, iclass 10, count 0 2006.201.18:43:08.22#ibcon#about to read 3, iclass 10, count 0 2006.201.18:43:08.24#ibcon#read 3, iclass 10, count 0 2006.201.18:43:08.24#ibcon#about to read 4, iclass 10, count 0 2006.201.18:43:08.24#ibcon#read 4, iclass 10, count 0 2006.201.18:43:08.24#ibcon#about to read 5, iclass 10, count 0 2006.201.18:43:08.24#ibcon#read 5, iclass 10, count 0 2006.201.18:43:08.24#ibcon#about to read 6, iclass 10, count 0 2006.201.18:43:08.24#ibcon#read 6, iclass 10, count 0 2006.201.18:43:08.24#ibcon#end of sib2, iclass 10, count 0 2006.201.18:43:08.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:43:08.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:43:08.24#ibcon#[25=USB\r\n] 2006.201.18:43:08.24#ibcon#*before write, iclass 10, count 0 2006.201.18:43:08.24#ibcon#enter sib2, iclass 10, count 0 2006.201.18:43:08.24#ibcon#flushed, iclass 10, count 0 2006.201.18:43:08.24#ibcon#about to write, iclass 10, count 0 2006.201.18:43:08.24#ibcon#wrote, iclass 10, count 0 2006.201.18:43:08.24#ibcon#about to read 3, iclass 10, count 0 2006.201.18:43:08.27#ibcon#read 3, iclass 10, count 0 2006.201.18:43:08.27#ibcon#about to read 4, iclass 10, count 0 2006.201.18:43:08.27#ibcon#read 4, iclass 10, count 0 2006.201.18:43:08.27#ibcon#about to read 5, iclass 10, count 0 2006.201.18:43:08.27#ibcon#read 5, iclass 10, count 0 2006.201.18:43:08.27#ibcon#about to read 6, iclass 10, count 0 2006.201.18:43:08.27#ibcon#read 6, iclass 10, count 0 2006.201.18:43:08.27#ibcon#end of sib2, iclass 10, count 0 2006.201.18:43:08.27#ibcon#*after write, iclass 10, count 0 2006.201.18:43:08.27#ibcon#*before return 0, iclass 10, count 0 2006.201.18:43:08.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:08.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:08.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:43:08.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:43:08.27$vck44/valo=5,734.99 2006.201.18:43:08.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.18:43:08.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.18:43:08.27#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:08.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:08.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:08.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:08.27#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:43:08.27#ibcon#first serial, iclass 12, count 0 2006.201.18:43:08.27#ibcon#enter sib2, iclass 12, count 0 2006.201.18:43:08.27#ibcon#flushed, iclass 12, count 0 2006.201.18:43:08.27#ibcon#about to write, iclass 12, count 0 2006.201.18:43:08.27#ibcon#wrote, iclass 12, count 0 2006.201.18:43:08.27#ibcon#about to read 3, iclass 12, count 0 2006.201.18:43:08.29#ibcon#read 3, iclass 12, count 0 2006.201.18:43:08.29#ibcon#about to read 4, iclass 12, count 0 2006.201.18:43:08.29#ibcon#read 4, iclass 12, count 0 2006.201.18:43:08.29#ibcon#about to read 5, iclass 12, count 0 2006.201.18:43:08.29#ibcon#read 5, iclass 12, count 0 2006.201.18:43:08.29#ibcon#about to read 6, iclass 12, count 0 2006.201.18:43:08.29#ibcon#read 6, iclass 12, count 0 2006.201.18:43:08.29#ibcon#end of sib2, iclass 12, count 0 2006.201.18:43:08.29#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:43:08.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:43:08.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:43:08.29#ibcon#*before write, iclass 12, count 0 2006.201.18:43:08.29#ibcon#enter sib2, iclass 12, count 0 2006.201.18:43:08.29#ibcon#flushed, iclass 12, count 0 2006.201.18:43:08.29#ibcon#about to write, iclass 12, count 0 2006.201.18:43:08.29#ibcon#wrote, iclass 12, count 0 2006.201.18:43:08.29#ibcon#about to read 3, iclass 12, count 0 2006.201.18:43:08.33#ibcon#read 3, iclass 12, count 0 2006.201.18:43:08.33#ibcon#about to read 4, iclass 12, count 0 2006.201.18:43:08.33#ibcon#read 4, iclass 12, count 0 2006.201.18:43:08.33#ibcon#about to read 5, iclass 12, count 0 2006.201.18:43:08.33#ibcon#read 5, iclass 12, count 0 2006.201.18:43:08.33#ibcon#about to read 6, iclass 12, count 0 2006.201.18:43:08.33#ibcon#read 6, iclass 12, count 0 2006.201.18:43:08.33#ibcon#end of sib2, iclass 12, count 0 2006.201.18:43:08.33#ibcon#*after write, iclass 12, count 0 2006.201.18:43:08.33#ibcon#*before return 0, iclass 12, count 0 2006.201.18:43:08.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:08.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:08.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:43:08.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:43:08.33$vck44/va=5,4 2006.201.18:43:08.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.18:43:08.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.18:43:08.33#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:08.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:08.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:08.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:08.39#ibcon#enter wrdev, iclass 14, count 2 2006.201.18:43:08.39#ibcon#first serial, iclass 14, count 2 2006.201.18:43:08.39#ibcon#enter sib2, iclass 14, count 2 2006.201.18:43:08.39#ibcon#flushed, iclass 14, count 2 2006.201.18:43:08.39#ibcon#about to write, iclass 14, count 2 2006.201.18:43:08.39#ibcon#wrote, iclass 14, count 2 2006.201.18:43:08.39#ibcon#about to read 3, iclass 14, count 2 2006.201.18:43:08.41#ibcon#read 3, iclass 14, count 2 2006.201.18:43:08.41#ibcon#about to read 4, iclass 14, count 2 2006.201.18:43:08.41#ibcon#read 4, iclass 14, count 2 2006.201.18:43:08.41#ibcon#about to read 5, iclass 14, count 2 2006.201.18:43:08.41#ibcon#read 5, iclass 14, count 2 2006.201.18:43:08.41#ibcon#about to read 6, iclass 14, count 2 2006.201.18:43:08.41#ibcon#read 6, iclass 14, count 2 2006.201.18:43:08.41#ibcon#end of sib2, iclass 14, count 2 2006.201.18:43:08.41#ibcon#*mode == 0, iclass 14, count 2 2006.201.18:43:08.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.18:43:08.41#ibcon#[25=AT05-04\r\n] 2006.201.18:43:08.41#ibcon#*before write, iclass 14, count 2 2006.201.18:43:08.41#ibcon#enter sib2, iclass 14, count 2 2006.201.18:43:08.41#ibcon#flushed, iclass 14, count 2 2006.201.18:43:08.41#ibcon#about to write, iclass 14, count 2 2006.201.18:43:08.41#ibcon#wrote, iclass 14, count 2 2006.201.18:43:08.41#ibcon#about to read 3, iclass 14, count 2 2006.201.18:43:08.44#ibcon#read 3, iclass 14, count 2 2006.201.18:43:08.44#ibcon#about to read 4, iclass 14, count 2 2006.201.18:43:08.44#ibcon#read 4, iclass 14, count 2 2006.201.18:43:08.44#ibcon#about to read 5, iclass 14, count 2 2006.201.18:43:08.44#ibcon#read 5, iclass 14, count 2 2006.201.18:43:08.44#ibcon#about to read 6, iclass 14, count 2 2006.201.18:43:08.44#ibcon#read 6, iclass 14, count 2 2006.201.18:43:08.44#ibcon#end of sib2, iclass 14, count 2 2006.201.18:43:08.44#ibcon#*after write, iclass 14, count 2 2006.201.18:43:08.44#ibcon#*before return 0, iclass 14, count 2 2006.201.18:43:08.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:08.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:08.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.18:43:08.44#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:08.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:08.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:08.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:08.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:43:08.56#ibcon#first serial, iclass 14, count 0 2006.201.18:43:08.56#ibcon#enter sib2, iclass 14, count 0 2006.201.18:43:08.56#ibcon#flushed, iclass 14, count 0 2006.201.18:43:08.56#ibcon#about to write, iclass 14, count 0 2006.201.18:43:08.56#ibcon#wrote, iclass 14, count 0 2006.201.18:43:08.56#ibcon#about to read 3, iclass 14, count 0 2006.201.18:43:08.58#ibcon#read 3, iclass 14, count 0 2006.201.18:43:08.58#ibcon#about to read 4, iclass 14, count 0 2006.201.18:43:08.58#ibcon#read 4, iclass 14, count 0 2006.201.18:43:08.58#ibcon#about to read 5, iclass 14, count 0 2006.201.18:43:08.58#ibcon#read 5, iclass 14, count 0 2006.201.18:43:08.58#ibcon#about to read 6, iclass 14, count 0 2006.201.18:43:08.58#ibcon#read 6, iclass 14, count 0 2006.201.18:43:08.58#ibcon#end of sib2, iclass 14, count 0 2006.201.18:43:08.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:43:08.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:43:08.58#ibcon#[25=USB\r\n] 2006.201.18:43:08.58#ibcon#*before write, iclass 14, count 0 2006.201.18:43:08.58#ibcon#enter sib2, iclass 14, count 0 2006.201.18:43:08.58#ibcon#flushed, iclass 14, count 0 2006.201.18:43:08.58#ibcon#about to write, iclass 14, count 0 2006.201.18:43:08.58#ibcon#wrote, iclass 14, count 0 2006.201.18:43:08.58#ibcon#about to read 3, iclass 14, count 0 2006.201.18:43:08.61#ibcon#read 3, iclass 14, count 0 2006.201.18:43:08.61#ibcon#about to read 4, iclass 14, count 0 2006.201.18:43:08.61#ibcon#read 4, iclass 14, count 0 2006.201.18:43:08.61#ibcon#about to read 5, iclass 14, count 0 2006.201.18:43:08.61#ibcon#read 5, iclass 14, count 0 2006.201.18:43:08.61#ibcon#about to read 6, iclass 14, count 0 2006.201.18:43:08.61#ibcon#read 6, iclass 14, count 0 2006.201.18:43:08.61#ibcon#end of sib2, iclass 14, count 0 2006.201.18:43:08.61#ibcon#*after write, iclass 14, count 0 2006.201.18:43:08.61#ibcon#*before return 0, iclass 14, count 0 2006.201.18:43:08.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:08.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:08.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:43:08.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:43:08.61$vck44/valo=6,814.99 2006.201.18:43:08.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.18:43:08.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.18:43:08.61#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:08.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:08.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:08.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:08.61#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:43:08.61#ibcon#first serial, iclass 16, count 0 2006.201.18:43:08.61#ibcon#enter sib2, iclass 16, count 0 2006.201.18:43:08.61#ibcon#flushed, iclass 16, count 0 2006.201.18:43:08.61#ibcon#about to write, iclass 16, count 0 2006.201.18:43:08.61#ibcon#wrote, iclass 16, count 0 2006.201.18:43:08.61#ibcon#about to read 3, iclass 16, count 0 2006.201.18:43:08.63#ibcon#read 3, iclass 16, count 0 2006.201.18:43:08.63#ibcon#about to read 4, iclass 16, count 0 2006.201.18:43:08.63#ibcon#read 4, iclass 16, count 0 2006.201.18:43:08.63#ibcon#about to read 5, iclass 16, count 0 2006.201.18:43:08.63#ibcon#read 5, iclass 16, count 0 2006.201.18:43:08.63#ibcon#about to read 6, iclass 16, count 0 2006.201.18:43:08.63#ibcon#read 6, iclass 16, count 0 2006.201.18:43:08.63#ibcon#end of sib2, iclass 16, count 0 2006.201.18:43:08.63#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:43:08.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:43:08.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:43:08.63#ibcon#*before write, iclass 16, count 0 2006.201.18:43:08.63#ibcon#enter sib2, iclass 16, count 0 2006.201.18:43:08.63#ibcon#flushed, iclass 16, count 0 2006.201.18:43:08.63#ibcon#about to write, iclass 16, count 0 2006.201.18:43:08.63#ibcon#wrote, iclass 16, count 0 2006.201.18:43:08.63#ibcon#about to read 3, iclass 16, count 0 2006.201.18:43:08.68#ibcon#read 3, iclass 16, count 0 2006.201.18:43:08.68#ibcon#about to read 4, iclass 16, count 0 2006.201.18:43:08.68#ibcon#read 4, iclass 16, count 0 2006.201.18:43:08.68#ibcon#about to read 5, iclass 16, count 0 2006.201.18:43:08.68#ibcon#read 5, iclass 16, count 0 2006.201.18:43:08.68#ibcon#about to read 6, iclass 16, count 0 2006.201.18:43:08.68#ibcon#read 6, iclass 16, count 0 2006.201.18:43:08.68#ibcon#end of sib2, iclass 16, count 0 2006.201.18:43:08.68#ibcon#*after write, iclass 16, count 0 2006.201.18:43:08.68#ibcon#*before return 0, iclass 16, count 0 2006.201.18:43:08.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:08.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:08.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:43:08.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:43:08.68$vck44/va=6,5 2006.201.18:43:08.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.18:43:08.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.18:43:08.68#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:08.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:08.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:08.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:08.73#ibcon#enter wrdev, iclass 18, count 2 2006.201.18:43:08.73#ibcon#first serial, iclass 18, count 2 2006.201.18:43:08.73#ibcon#enter sib2, iclass 18, count 2 2006.201.18:43:08.73#ibcon#flushed, iclass 18, count 2 2006.201.18:43:08.73#ibcon#about to write, iclass 18, count 2 2006.201.18:43:08.73#ibcon#wrote, iclass 18, count 2 2006.201.18:43:08.73#ibcon#about to read 3, iclass 18, count 2 2006.201.18:43:08.75#ibcon#read 3, iclass 18, count 2 2006.201.18:43:08.75#ibcon#about to read 4, iclass 18, count 2 2006.201.18:43:08.75#ibcon#read 4, iclass 18, count 2 2006.201.18:43:08.75#ibcon#about to read 5, iclass 18, count 2 2006.201.18:43:08.75#ibcon#read 5, iclass 18, count 2 2006.201.18:43:08.75#ibcon#about to read 6, iclass 18, count 2 2006.201.18:43:08.75#ibcon#read 6, iclass 18, count 2 2006.201.18:43:08.75#ibcon#end of sib2, iclass 18, count 2 2006.201.18:43:08.75#ibcon#*mode == 0, iclass 18, count 2 2006.201.18:43:08.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.18:43:08.75#ibcon#[25=AT06-05\r\n] 2006.201.18:43:08.75#ibcon#*before write, iclass 18, count 2 2006.201.18:43:08.75#ibcon#enter sib2, iclass 18, count 2 2006.201.18:43:08.75#ibcon#flushed, iclass 18, count 2 2006.201.18:43:08.75#ibcon#about to write, iclass 18, count 2 2006.201.18:43:08.75#ibcon#wrote, iclass 18, count 2 2006.201.18:43:08.75#ibcon#about to read 3, iclass 18, count 2 2006.201.18:43:08.78#ibcon#read 3, iclass 18, count 2 2006.201.18:43:08.78#ibcon#about to read 4, iclass 18, count 2 2006.201.18:43:08.78#ibcon#read 4, iclass 18, count 2 2006.201.18:43:08.78#ibcon#about to read 5, iclass 18, count 2 2006.201.18:43:08.78#ibcon#read 5, iclass 18, count 2 2006.201.18:43:08.78#ibcon#about to read 6, iclass 18, count 2 2006.201.18:43:08.78#ibcon#read 6, iclass 18, count 2 2006.201.18:43:08.78#ibcon#end of sib2, iclass 18, count 2 2006.201.18:43:08.78#ibcon#*after write, iclass 18, count 2 2006.201.18:43:08.78#ibcon#*before return 0, iclass 18, count 2 2006.201.18:43:08.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:08.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:08.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.18:43:08.78#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:08.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:08.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:08.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:08.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:43:08.90#ibcon#first serial, iclass 18, count 0 2006.201.18:43:08.90#ibcon#enter sib2, iclass 18, count 0 2006.201.18:43:08.90#ibcon#flushed, iclass 18, count 0 2006.201.18:43:08.90#ibcon#about to write, iclass 18, count 0 2006.201.18:43:08.90#ibcon#wrote, iclass 18, count 0 2006.201.18:43:08.90#ibcon#about to read 3, iclass 18, count 0 2006.201.18:43:08.92#ibcon#read 3, iclass 18, count 0 2006.201.18:43:08.92#ibcon#about to read 4, iclass 18, count 0 2006.201.18:43:08.92#ibcon#read 4, iclass 18, count 0 2006.201.18:43:08.92#ibcon#about to read 5, iclass 18, count 0 2006.201.18:43:08.92#ibcon#read 5, iclass 18, count 0 2006.201.18:43:08.92#ibcon#about to read 6, iclass 18, count 0 2006.201.18:43:08.92#ibcon#read 6, iclass 18, count 0 2006.201.18:43:08.92#ibcon#end of sib2, iclass 18, count 0 2006.201.18:43:08.92#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:43:08.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:43:08.92#ibcon#[25=USB\r\n] 2006.201.18:43:08.92#ibcon#*before write, iclass 18, count 0 2006.201.18:43:08.92#ibcon#enter sib2, iclass 18, count 0 2006.201.18:43:08.92#ibcon#flushed, iclass 18, count 0 2006.201.18:43:08.92#ibcon#about to write, iclass 18, count 0 2006.201.18:43:08.92#ibcon#wrote, iclass 18, count 0 2006.201.18:43:08.92#ibcon#about to read 3, iclass 18, count 0 2006.201.18:43:08.95#ibcon#read 3, iclass 18, count 0 2006.201.18:43:08.95#ibcon#about to read 4, iclass 18, count 0 2006.201.18:43:08.95#ibcon#read 4, iclass 18, count 0 2006.201.18:43:08.95#ibcon#about to read 5, iclass 18, count 0 2006.201.18:43:08.95#ibcon#read 5, iclass 18, count 0 2006.201.18:43:08.95#ibcon#about to read 6, iclass 18, count 0 2006.201.18:43:08.95#ibcon#read 6, iclass 18, count 0 2006.201.18:43:08.95#ibcon#end of sib2, iclass 18, count 0 2006.201.18:43:08.95#ibcon#*after write, iclass 18, count 0 2006.201.18:43:08.95#ibcon#*before return 0, iclass 18, count 0 2006.201.18:43:08.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:08.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:08.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:43:08.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:43:08.95$vck44/valo=7,864.99 2006.201.18:43:08.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.18:43:08.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.18:43:08.95#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:08.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:08.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:08.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:08.95#ibcon#enter wrdev, iclass 20, count 0 2006.201.18:43:08.95#ibcon#first serial, iclass 20, count 0 2006.201.18:43:08.95#ibcon#enter sib2, iclass 20, count 0 2006.201.18:43:08.95#ibcon#flushed, iclass 20, count 0 2006.201.18:43:08.95#ibcon#about to write, iclass 20, count 0 2006.201.18:43:08.95#ibcon#wrote, iclass 20, count 0 2006.201.18:43:08.95#ibcon#about to read 3, iclass 20, count 0 2006.201.18:43:08.97#ibcon#read 3, iclass 20, count 0 2006.201.18:43:08.97#ibcon#about to read 4, iclass 20, count 0 2006.201.18:43:08.97#ibcon#read 4, iclass 20, count 0 2006.201.18:43:08.97#ibcon#about to read 5, iclass 20, count 0 2006.201.18:43:08.97#ibcon#read 5, iclass 20, count 0 2006.201.18:43:08.97#ibcon#about to read 6, iclass 20, count 0 2006.201.18:43:08.97#ibcon#read 6, iclass 20, count 0 2006.201.18:43:08.97#ibcon#end of sib2, iclass 20, count 0 2006.201.18:43:08.97#ibcon#*mode == 0, iclass 20, count 0 2006.201.18:43:08.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.18:43:08.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:43:08.97#ibcon#*before write, iclass 20, count 0 2006.201.18:43:08.97#ibcon#enter sib2, iclass 20, count 0 2006.201.18:43:08.97#ibcon#flushed, iclass 20, count 0 2006.201.18:43:08.97#ibcon#about to write, iclass 20, count 0 2006.201.18:43:08.97#ibcon#wrote, iclass 20, count 0 2006.201.18:43:08.97#ibcon#about to read 3, iclass 20, count 0 2006.201.18:43:09.01#ibcon#read 3, iclass 20, count 0 2006.201.18:43:09.01#ibcon#about to read 4, iclass 20, count 0 2006.201.18:43:09.01#ibcon#read 4, iclass 20, count 0 2006.201.18:43:09.01#ibcon#about to read 5, iclass 20, count 0 2006.201.18:43:09.01#ibcon#read 5, iclass 20, count 0 2006.201.18:43:09.01#ibcon#about to read 6, iclass 20, count 0 2006.201.18:43:09.01#ibcon#read 6, iclass 20, count 0 2006.201.18:43:09.01#ibcon#end of sib2, iclass 20, count 0 2006.201.18:43:09.01#ibcon#*after write, iclass 20, count 0 2006.201.18:43:09.01#ibcon#*before return 0, iclass 20, count 0 2006.201.18:43:09.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:09.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:09.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.18:43:09.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.18:43:09.01$vck44/va=7,5 2006.201.18:43:09.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.18:43:09.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.18:43:09.01#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:09.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:09.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:09.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:09.07#ibcon#enter wrdev, iclass 22, count 2 2006.201.18:43:09.07#ibcon#first serial, iclass 22, count 2 2006.201.18:43:09.07#ibcon#enter sib2, iclass 22, count 2 2006.201.18:43:09.07#ibcon#flushed, iclass 22, count 2 2006.201.18:43:09.07#ibcon#about to write, iclass 22, count 2 2006.201.18:43:09.07#ibcon#wrote, iclass 22, count 2 2006.201.18:43:09.07#ibcon#about to read 3, iclass 22, count 2 2006.201.18:43:09.09#ibcon#read 3, iclass 22, count 2 2006.201.18:43:09.09#ibcon#about to read 4, iclass 22, count 2 2006.201.18:43:09.09#ibcon#read 4, iclass 22, count 2 2006.201.18:43:09.09#ibcon#about to read 5, iclass 22, count 2 2006.201.18:43:09.09#ibcon#read 5, iclass 22, count 2 2006.201.18:43:09.09#ibcon#about to read 6, iclass 22, count 2 2006.201.18:43:09.09#ibcon#read 6, iclass 22, count 2 2006.201.18:43:09.09#ibcon#end of sib2, iclass 22, count 2 2006.201.18:43:09.09#ibcon#*mode == 0, iclass 22, count 2 2006.201.18:43:09.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.18:43:09.09#ibcon#[25=AT07-05\r\n] 2006.201.18:43:09.09#ibcon#*before write, iclass 22, count 2 2006.201.18:43:09.09#ibcon#enter sib2, iclass 22, count 2 2006.201.18:43:09.09#ibcon#flushed, iclass 22, count 2 2006.201.18:43:09.09#ibcon#about to write, iclass 22, count 2 2006.201.18:43:09.09#ibcon#wrote, iclass 22, count 2 2006.201.18:43:09.09#ibcon#about to read 3, iclass 22, count 2 2006.201.18:43:09.12#ibcon#read 3, iclass 22, count 2 2006.201.18:43:09.12#ibcon#about to read 4, iclass 22, count 2 2006.201.18:43:09.12#ibcon#read 4, iclass 22, count 2 2006.201.18:43:09.12#ibcon#about to read 5, iclass 22, count 2 2006.201.18:43:09.12#ibcon#read 5, iclass 22, count 2 2006.201.18:43:09.12#ibcon#about to read 6, iclass 22, count 2 2006.201.18:43:09.12#ibcon#read 6, iclass 22, count 2 2006.201.18:43:09.12#ibcon#end of sib2, iclass 22, count 2 2006.201.18:43:09.12#ibcon#*after write, iclass 22, count 2 2006.201.18:43:09.12#ibcon#*before return 0, iclass 22, count 2 2006.201.18:43:09.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:09.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:09.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.18:43:09.12#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:09.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:09.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:09.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:09.24#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:43:09.24#ibcon#first serial, iclass 22, count 0 2006.201.18:43:09.24#ibcon#enter sib2, iclass 22, count 0 2006.201.18:43:09.24#ibcon#flushed, iclass 22, count 0 2006.201.18:43:09.24#ibcon#about to write, iclass 22, count 0 2006.201.18:43:09.24#ibcon#wrote, iclass 22, count 0 2006.201.18:43:09.24#ibcon#about to read 3, iclass 22, count 0 2006.201.18:43:09.26#ibcon#read 3, iclass 22, count 0 2006.201.18:43:09.26#ibcon#about to read 4, iclass 22, count 0 2006.201.18:43:09.26#ibcon#read 4, iclass 22, count 0 2006.201.18:43:09.26#ibcon#about to read 5, iclass 22, count 0 2006.201.18:43:09.26#ibcon#read 5, iclass 22, count 0 2006.201.18:43:09.26#ibcon#about to read 6, iclass 22, count 0 2006.201.18:43:09.26#ibcon#read 6, iclass 22, count 0 2006.201.18:43:09.26#ibcon#end of sib2, iclass 22, count 0 2006.201.18:43:09.26#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:43:09.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:43:09.26#ibcon#[25=USB\r\n] 2006.201.18:43:09.26#ibcon#*before write, iclass 22, count 0 2006.201.18:43:09.26#ibcon#enter sib2, iclass 22, count 0 2006.201.18:43:09.26#ibcon#flushed, iclass 22, count 0 2006.201.18:43:09.26#ibcon#about to write, iclass 22, count 0 2006.201.18:43:09.26#ibcon#wrote, iclass 22, count 0 2006.201.18:43:09.26#ibcon#about to read 3, iclass 22, count 0 2006.201.18:43:09.29#ibcon#read 3, iclass 22, count 0 2006.201.18:43:09.29#ibcon#about to read 4, iclass 22, count 0 2006.201.18:43:09.29#ibcon#read 4, iclass 22, count 0 2006.201.18:43:09.29#ibcon#about to read 5, iclass 22, count 0 2006.201.18:43:09.29#ibcon#read 5, iclass 22, count 0 2006.201.18:43:09.29#ibcon#about to read 6, iclass 22, count 0 2006.201.18:43:09.29#ibcon#read 6, iclass 22, count 0 2006.201.18:43:09.29#ibcon#end of sib2, iclass 22, count 0 2006.201.18:43:09.29#ibcon#*after write, iclass 22, count 0 2006.201.18:43:09.29#ibcon#*before return 0, iclass 22, count 0 2006.201.18:43:09.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:09.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:09.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:43:09.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:43:09.29$vck44/valo=8,884.99 2006.201.18:43:09.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.18:43:09.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.18:43:09.29#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:09.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:09.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:09.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:09.29#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:43:09.29#ibcon#first serial, iclass 24, count 0 2006.201.18:43:09.29#ibcon#enter sib2, iclass 24, count 0 2006.201.18:43:09.29#ibcon#flushed, iclass 24, count 0 2006.201.18:43:09.29#ibcon#about to write, iclass 24, count 0 2006.201.18:43:09.29#ibcon#wrote, iclass 24, count 0 2006.201.18:43:09.29#ibcon#about to read 3, iclass 24, count 0 2006.201.18:43:09.31#ibcon#read 3, iclass 24, count 0 2006.201.18:43:09.31#ibcon#about to read 4, iclass 24, count 0 2006.201.18:43:09.31#ibcon#read 4, iclass 24, count 0 2006.201.18:43:09.31#ibcon#about to read 5, iclass 24, count 0 2006.201.18:43:09.31#ibcon#read 5, iclass 24, count 0 2006.201.18:43:09.31#ibcon#about to read 6, iclass 24, count 0 2006.201.18:43:09.31#ibcon#read 6, iclass 24, count 0 2006.201.18:43:09.31#ibcon#end of sib2, iclass 24, count 0 2006.201.18:43:09.31#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:43:09.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:43:09.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:43:09.31#ibcon#*before write, iclass 24, count 0 2006.201.18:43:09.31#ibcon#enter sib2, iclass 24, count 0 2006.201.18:43:09.31#ibcon#flushed, iclass 24, count 0 2006.201.18:43:09.31#ibcon#about to write, iclass 24, count 0 2006.201.18:43:09.31#ibcon#wrote, iclass 24, count 0 2006.201.18:43:09.31#ibcon#about to read 3, iclass 24, count 0 2006.201.18:43:09.35#ibcon#read 3, iclass 24, count 0 2006.201.18:43:09.35#ibcon#about to read 4, iclass 24, count 0 2006.201.18:43:09.35#ibcon#read 4, iclass 24, count 0 2006.201.18:43:09.35#ibcon#about to read 5, iclass 24, count 0 2006.201.18:43:09.35#ibcon#read 5, iclass 24, count 0 2006.201.18:43:09.35#ibcon#about to read 6, iclass 24, count 0 2006.201.18:43:09.35#ibcon#read 6, iclass 24, count 0 2006.201.18:43:09.35#ibcon#end of sib2, iclass 24, count 0 2006.201.18:43:09.35#ibcon#*after write, iclass 24, count 0 2006.201.18:43:09.35#ibcon#*before return 0, iclass 24, count 0 2006.201.18:43:09.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:09.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:09.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:43:09.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:43:09.35$vck44/va=8,4 2006.201.18:43:09.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.18:43:09.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.18:43:09.35#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:09.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:09.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:09.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:09.41#ibcon#enter wrdev, iclass 26, count 2 2006.201.18:43:09.41#ibcon#first serial, iclass 26, count 2 2006.201.18:43:09.41#ibcon#enter sib2, iclass 26, count 2 2006.201.18:43:09.41#ibcon#flushed, iclass 26, count 2 2006.201.18:43:09.41#ibcon#about to write, iclass 26, count 2 2006.201.18:43:09.41#ibcon#wrote, iclass 26, count 2 2006.201.18:43:09.41#ibcon#about to read 3, iclass 26, count 2 2006.201.18:43:09.43#ibcon#read 3, iclass 26, count 2 2006.201.18:43:09.43#ibcon#about to read 4, iclass 26, count 2 2006.201.18:43:09.43#ibcon#read 4, iclass 26, count 2 2006.201.18:43:09.43#ibcon#about to read 5, iclass 26, count 2 2006.201.18:43:09.43#ibcon#read 5, iclass 26, count 2 2006.201.18:43:09.43#ibcon#about to read 6, iclass 26, count 2 2006.201.18:43:09.43#ibcon#read 6, iclass 26, count 2 2006.201.18:43:09.43#ibcon#end of sib2, iclass 26, count 2 2006.201.18:43:09.43#ibcon#*mode == 0, iclass 26, count 2 2006.201.18:43:09.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.18:43:09.43#ibcon#[25=AT08-04\r\n] 2006.201.18:43:09.43#ibcon#*before write, iclass 26, count 2 2006.201.18:43:09.43#ibcon#enter sib2, iclass 26, count 2 2006.201.18:43:09.43#ibcon#flushed, iclass 26, count 2 2006.201.18:43:09.43#ibcon#about to write, iclass 26, count 2 2006.201.18:43:09.43#ibcon#wrote, iclass 26, count 2 2006.201.18:43:09.43#ibcon#about to read 3, iclass 26, count 2 2006.201.18:43:09.46#ibcon#read 3, iclass 26, count 2 2006.201.18:43:09.46#ibcon#about to read 4, iclass 26, count 2 2006.201.18:43:09.46#ibcon#read 4, iclass 26, count 2 2006.201.18:43:09.46#ibcon#about to read 5, iclass 26, count 2 2006.201.18:43:09.46#ibcon#read 5, iclass 26, count 2 2006.201.18:43:09.46#ibcon#about to read 6, iclass 26, count 2 2006.201.18:43:09.46#ibcon#read 6, iclass 26, count 2 2006.201.18:43:09.46#ibcon#end of sib2, iclass 26, count 2 2006.201.18:43:09.46#ibcon#*after write, iclass 26, count 2 2006.201.18:43:09.46#ibcon#*before return 0, iclass 26, count 2 2006.201.18:43:09.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:09.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:09.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.18:43:09.46#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:09.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:09.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:09.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:09.58#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:43:09.58#ibcon#first serial, iclass 26, count 0 2006.201.18:43:09.58#ibcon#enter sib2, iclass 26, count 0 2006.201.18:43:09.58#ibcon#flushed, iclass 26, count 0 2006.201.18:43:09.58#ibcon#about to write, iclass 26, count 0 2006.201.18:43:09.58#ibcon#wrote, iclass 26, count 0 2006.201.18:43:09.58#ibcon#about to read 3, iclass 26, count 0 2006.201.18:43:09.60#ibcon#read 3, iclass 26, count 0 2006.201.18:43:09.60#ibcon#about to read 4, iclass 26, count 0 2006.201.18:43:09.60#ibcon#read 4, iclass 26, count 0 2006.201.18:43:09.60#ibcon#about to read 5, iclass 26, count 0 2006.201.18:43:09.60#ibcon#read 5, iclass 26, count 0 2006.201.18:43:09.60#ibcon#about to read 6, iclass 26, count 0 2006.201.18:43:09.60#ibcon#read 6, iclass 26, count 0 2006.201.18:43:09.60#ibcon#end of sib2, iclass 26, count 0 2006.201.18:43:09.60#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:43:09.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:43:09.60#ibcon#[25=USB\r\n] 2006.201.18:43:09.60#ibcon#*before write, iclass 26, count 0 2006.201.18:43:09.60#ibcon#enter sib2, iclass 26, count 0 2006.201.18:43:09.60#ibcon#flushed, iclass 26, count 0 2006.201.18:43:09.60#ibcon#about to write, iclass 26, count 0 2006.201.18:43:09.60#ibcon#wrote, iclass 26, count 0 2006.201.18:43:09.60#ibcon#about to read 3, iclass 26, count 0 2006.201.18:43:09.63#ibcon#read 3, iclass 26, count 0 2006.201.18:43:09.63#ibcon#about to read 4, iclass 26, count 0 2006.201.18:43:09.63#ibcon#read 4, iclass 26, count 0 2006.201.18:43:09.63#ibcon#about to read 5, iclass 26, count 0 2006.201.18:43:09.63#ibcon#read 5, iclass 26, count 0 2006.201.18:43:09.63#ibcon#about to read 6, iclass 26, count 0 2006.201.18:43:09.63#ibcon#read 6, iclass 26, count 0 2006.201.18:43:09.63#ibcon#end of sib2, iclass 26, count 0 2006.201.18:43:09.63#ibcon#*after write, iclass 26, count 0 2006.201.18:43:09.63#ibcon#*before return 0, iclass 26, count 0 2006.201.18:43:09.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:09.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:09.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:43:09.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:43:09.63$vck44/vblo=1,629.99 2006.201.18:43:09.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.18:43:09.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.18:43:09.63#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:09.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:09.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:09.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:09.63#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:43:09.63#ibcon#first serial, iclass 28, count 0 2006.201.18:43:09.63#ibcon#enter sib2, iclass 28, count 0 2006.201.18:43:09.63#ibcon#flushed, iclass 28, count 0 2006.201.18:43:09.63#ibcon#about to write, iclass 28, count 0 2006.201.18:43:09.63#ibcon#wrote, iclass 28, count 0 2006.201.18:43:09.63#ibcon#about to read 3, iclass 28, count 0 2006.201.18:43:09.65#ibcon#read 3, iclass 28, count 0 2006.201.18:43:09.65#ibcon#about to read 4, iclass 28, count 0 2006.201.18:43:09.65#ibcon#read 4, iclass 28, count 0 2006.201.18:43:09.65#ibcon#about to read 5, iclass 28, count 0 2006.201.18:43:09.65#ibcon#read 5, iclass 28, count 0 2006.201.18:43:09.65#ibcon#about to read 6, iclass 28, count 0 2006.201.18:43:09.65#ibcon#read 6, iclass 28, count 0 2006.201.18:43:09.65#ibcon#end of sib2, iclass 28, count 0 2006.201.18:43:09.65#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:43:09.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:43:09.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:43:09.65#ibcon#*before write, iclass 28, count 0 2006.201.18:43:09.65#ibcon#enter sib2, iclass 28, count 0 2006.201.18:43:09.65#ibcon#flushed, iclass 28, count 0 2006.201.18:43:09.65#ibcon#about to write, iclass 28, count 0 2006.201.18:43:09.65#ibcon#wrote, iclass 28, count 0 2006.201.18:43:09.65#ibcon#about to read 3, iclass 28, count 0 2006.201.18:43:09.70#ibcon#read 3, iclass 28, count 0 2006.201.18:43:09.70#ibcon#about to read 4, iclass 28, count 0 2006.201.18:43:09.70#ibcon#read 4, iclass 28, count 0 2006.201.18:43:09.70#ibcon#about to read 5, iclass 28, count 0 2006.201.18:43:09.70#ibcon#read 5, iclass 28, count 0 2006.201.18:43:09.70#ibcon#about to read 6, iclass 28, count 0 2006.201.18:43:09.70#ibcon#read 6, iclass 28, count 0 2006.201.18:43:09.70#ibcon#end of sib2, iclass 28, count 0 2006.201.18:43:09.70#ibcon#*after write, iclass 28, count 0 2006.201.18:43:09.70#ibcon#*before return 0, iclass 28, count 0 2006.201.18:43:09.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:09.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:09.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:43:09.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:43:09.70$vck44/vb=1,4 2006.201.18:43:09.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.18:43:09.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.18:43:09.70#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:09.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:43:09.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:43:09.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:43:09.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.18:43:09.70#ibcon#first serial, iclass 30, count 2 2006.201.18:43:09.70#ibcon#enter sib2, iclass 30, count 2 2006.201.18:43:09.70#ibcon#flushed, iclass 30, count 2 2006.201.18:43:09.70#ibcon#about to write, iclass 30, count 2 2006.201.18:43:09.70#ibcon#wrote, iclass 30, count 2 2006.201.18:43:09.70#ibcon#about to read 3, iclass 30, count 2 2006.201.18:43:09.72#ibcon#read 3, iclass 30, count 2 2006.201.18:43:09.72#ibcon#about to read 4, iclass 30, count 2 2006.201.18:43:09.72#ibcon#read 4, iclass 30, count 2 2006.201.18:43:09.72#ibcon#about to read 5, iclass 30, count 2 2006.201.18:43:09.72#ibcon#read 5, iclass 30, count 2 2006.201.18:43:09.72#ibcon#about to read 6, iclass 30, count 2 2006.201.18:43:09.72#ibcon#read 6, iclass 30, count 2 2006.201.18:43:09.72#ibcon#end of sib2, iclass 30, count 2 2006.201.18:43:09.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.18:43:09.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.18:43:09.72#ibcon#[27=AT01-04\r\n] 2006.201.18:43:09.72#ibcon#*before write, iclass 30, count 2 2006.201.18:43:09.72#ibcon#enter sib2, iclass 30, count 2 2006.201.18:43:09.72#ibcon#flushed, iclass 30, count 2 2006.201.18:43:09.72#ibcon#about to write, iclass 30, count 2 2006.201.18:43:09.72#ibcon#wrote, iclass 30, count 2 2006.201.18:43:09.72#ibcon#about to read 3, iclass 30, count 2 2006.201.18:43:09.75#ibcon#read 3, iclass 30, count 2 2006.201.18:43:09.75#ibcon#about to read 4, iclass 30, count 2 2006.201.18:43:09.75#ibcon#read 4, iclass 30, count 2 2006.201.18:43:09.75#ibcon#about to read 5, iclass 30, count 2 2006.201.18:43:09.75#ibcon#read 5, iclass 30, count 2 2006.201.18:43:09.75#ibcon#about to read 6, iclass 30, count 2 2006.201.18:43:09.75#ibcon#read 6, iclass 30, count 2 2006.201.18:43:09.75#ibcon#end of sib2, iclass 30, count 2 2006.201.18:43:09.75#ibcon#*after write, iclass 30, count 2 2006.201.18:43:09.75#ibcon#*before return 0, iclass 30, count 2 2006.201.18:43:09.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:43:09.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.18:43:09.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.18:43:09.75#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:09.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:43:09.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:43:09.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:43:09.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:43:09.87#ibcon#first serial, iclass 30, count 0 2006.201.18:43:09.87#ibcon#enter sib2, iclass 30, count 0 2006.201.18:43:09.87#ibcon#flushed, iclass 30, count 0 2006.201.18:43:09.87#ibcon#about to write, iclass 30, count 0 2006.201.18:43:09.87#ibcon#wrote, iclass 30, count 0 2006.201.18:43:09.87#ibcon#about to read 3, iclass 30, count 0 2006.201.18:43:09.89#ibcon#read 3, iclass 30, count 0 2006.201.18:43:09.89#ibcon#about to read 4, iclass 30, count 0 2006.201.18:43:09.89#ibcon#read 4, iclass 30, count 0 2006.201.18:43:09.89#ibcon#about to read 5, iclass 30, count 0 2006.201.18:43:09.89#ibcon#read 5, iclass 30, count 0 2006.201.18:43:09.89#ibcon#about to read 6, iclass 30, count 0 2006.201.18:43:09.89#ibcon#read 6, iclass 30, count 0 2006.201.18:43:09.89#ibcon#end of sib2, iclass 30, count 0 2006.201.18:43:09.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:43:09.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:43:09.89#ibcon#[27=USB\r\n] 2006.201.18:43:09.89#ibcon#*before write, iclass 30, count 0 2006.201.18:43:09.89#ibcon#enter sib2, iclass 30, count 0 2006.201.18:43:09.89#ibcon#flushed, iclass 30, count 0 2006.201.18:43:09.89#ibcon#about to write, iclass 30, count 0 2006.201.18:43:09.89#ibcon#wrote, iclass 30, count 0 2006.201.18:43:09.89#ibcon#about to read 3, iclass 30, count 0 2006.201.18:43:09.92#ibcon#read 3, iclass 30, count 0 2006.201.18:43:09.92#ibcon#about to read 4, iclass 30, count 0 2006.201.18:43:09.92#ibcon#read 4, iclass 30, count 0 2006.201.18:43:09.92#ibcon#about to read 5, iclass 30, count 0 2006.201.18:43:09.92#ibcon#read 5, iclass 30, count 0 2006.201.18:43:09.92#ibcon#about to read 6, iclass 30, count 0 2006.201.18:43:09.92#ibcon#read 6, iclass 30, count 0 2006.201.18:43:09.92#ibcon#end of sib2, iclass 30, count 0 2006.201.18:43:09.92#ibcon#*after write, iclass 30, count 0 2006.201.18:43:09.92#ibcon#*before return 0, iclass 30, count 0 2006.201.18:43:09.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:43:09.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.18:43:09.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:43:09.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:43:09.92$vck44/vblo=2,634.99 2006.201.18:43:09.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.18:43:09.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.18:43:09.92#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:09.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:43:09.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:43:09.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:43:09.92#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:43:09.92#ibcon#first serial, iclass 33, count 0 2006.201.18:43:09.92#ibcon#enter sib2, iclass 33, count 0 2006.201.18:43:09.92#ibcon#flushed, iclass 33, count 0 2006.201.18:43:09.92#ibcon#about to write, iclass 33, count 0 2006.201.18:43:09.92#ibcon#wrote, iclass 33, count 0 2006.201.18:43:09.92#ibcon#about to read 3, iclass 33, count 0 2006.201.18:43:09.94#ibcon#read 3, iclass 33, count 0 2006.201.18:43:09.94#ibcon#about to read 4, iclass 33, count 0 2006.201.18:43:09.94#ibcon#read 4, iclass 33, count 0 2006.201.18:43:09.94#ibcon#about to read 5, iclass 33, count 0 2006.201.18:43:09.94#ibcon#read 5, iclass 33, count 0 2006.201.18:43:09.94#ibcon#about to read 6, iclass 33, count 0 2006.201.18:43:09.94#ibcon#read 6, iclass 33, count 0 2006.201.18:43:09.94#ibcon#end of sib2, iclass 33, count 0 2006.201.18:43:09.94#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:43:09.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:43:09.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:43:09.94#ibcon#*before write, iclass 33, count 0 2006.201.18:43:09.94#ibcon#enter sib2, iclass 33, count 0 2006.201.18:43:09.94#ibcon#flushed, iclass 33, count 0 2006.201.18:43:09.94#ibcon#about to write, iclass 33, count 0 2006.201.18:43:09.94#ibcon#wrote, iclass 33, count 0 2006.201.18:43:09.94#ibcon#about to read 3, iclass 33, count 0 2006.201.18:43:09.95#abcon#<5=/02 0.7 2.4 20.491001002.1\r\n> 2006.201.18:43:09.97#abcon#{5=INTERFACE CLEAR} 2006.201.18:43:09.98#ibcon#read 3, iclass 33, count 0 2006.201.18:43:09.98#ibcon#about to read 4, iclass 33, count 0 2006.201.18:43:09.98#ibcon#read 4, iclass 33, count 0 2006.201.18:43:09.98#ibcon#about to read 5, iclass 33, count 0 2006.201.18:43:09.98#ibcon#read 5, iclass 33, count 0 2006.201.18:43:09.98#ibcon#about to read 6, iclass 33, count 0 2006.201.18:43:09.98#ibcon#read 6, iclass 33, count 0 2006.201.18:43:09.98#ibcon#end of sib2, iclass 33, count 0 2006.201.18:43:09.98#ibcon#*after write, iclass 33, count 0 2006.201.18:43:09.98#ibcon#*before return 0, iclass 33, count 0 2006.201.18:43:09.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:43:09.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:43:09.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:43:09.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:43:09.98$vck44/vb=2,5 2006.201.18:43:09.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.18:43:09.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.18:43:09.98#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:09.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:43:10.03#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:43:10.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:43:10.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:43:10.04#ibcon#enter wrdev, iclass 37, count 2 2006.201.18:43:10.04#ibcon#first serial, iclass 37, count 2 2006.201.18:43:10.04#ibcon#enter sib2, iclass 37, count 2 2006.201.18:43:10.04#ibcon#flushed, iclass 37, count 2 2006.201.18:43:10.04#ibcon#about to write, iclass 37, count 2 2006.201.18:43:10.04#ibcon#wrote, iclass 37, count 2 2006.201.18:43:10.04#ibcon#about to read 3, iclass 37, count 2 2006.201.18:43:10.06#ibcon#read 3, iclass 37, count 2 2006.201.18:43:10.06#ibcon#about to read 4, iclass 37, count 2 2006.201.18:43:10.06#ibcon#read 4, iclass 37, count 2 2006.201.18:43:10.06#ibcon#about to read 5, iclass 37, count 2 2006.201.18:43:10.06#ibcon#read 5, iclass 37, count 2 2006.201.18:43:10.06#ibcon#about to read 6, iclass 37, count 2 2006.201.18:43:10.06#ibcon#read 6, iclass 37, count 2 2006.201.18:43:10.06#ibcon#end of sib2, iclass 37, count 2 2006.201.18:43:10.06#ibcon#*mode == 0, iclass 37, count 2 2006.201.18:43:10.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.18:43:10.06#ibcon#[27=AT02-05\r\n] 2006.201.18:43:10.06#ibcon#*before write, iclass 37, count 2 2006.201.18:43:10.06#ibcon#enter sib2, iclass 37, count 2 2006.201.18:43:10.06#ibcon#flushed, iclass 37, count 2 2006.201.18:43:10.06#ibcon#about to write, iclass 37, count 2 2006.201.18:43:10.06#ibcon#wrote, iclass 37, count 2 2006.201.18:43:10.06#ibcon#about to read 3, iclass 37, count 2 2006.201.18:43:10.09#ibcon#read 3, iclass 37, count 2 2006.201.18:43:10.09#ibcon#about to read 4, iclass 37, count 2 2006.201.18:43:10.09#ibcon#read 4, iclass 37, count 2 2006.201.18:43:10.09#ibcon#about to read 5, iclass 37, count 2 2006.201.18:43:10.09#ibcon#read 5, iclass 37, count 2 2006.201.18:43:10.09#ibcon#about to read 6, iclass 37, count 2 2006.201.18:43:10.09#ibcon#read 6, iclass 37, count 2 2006.201.18:43:10.09#ibcon#end of sib2, iclass 37, count 2 2006.201.18:43:10.09#ibcon#*after write, iclass 37, count 2 2006.201.18:43:10.09#ibcon#*before return 0, iclass 37, count 2 2006.201.18:43:10.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:43:10.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:43:10.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.18:43:10.09#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:10.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:43:10.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:43:10.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:43:10.21#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:43:10.21#ibcon#first serial, iclass 37, count 0 2006.201.18:43:10.21#ibcon#enter sib2, iclass 37, count 0 2006.201.18:43:10.21#ibcon#flushed, iclass 37, count 0 2006.201.18:43:10.21#ibcon#about to write, iclass 37, count 0 2006.201.18:43:10.21#ibcon#wrote, iclass 37, count 0 2006.201.18:43:10.21#ibcon#about to read 3, iclass 37, count 0 2006.201.18:43:10.23#ibcon#read 3, iclass 37, count 0 2006.201.18:43:10.23#ibcon#about to read 4, iclass 37, count 0 2006.201.18:43:10.23#ibcon#read 4, iclass 37, count 0 2006.201.18:43:10.23#ibcon#about to read 5, iclass 37, count 0 2006.201.18:43:10.23#ibcon#read 5, iclass 37, count 0 2006.201.18:43:10.23#ibcon#about to read 6, iclass 37, count 0 2006.201.18:43:10.23#ibcon#read 6, iclass 37, count 0 2006.201.18:43:10.23#ibcon#end of sib2, iclass 37, count 0 2006.201.18:43:10.23#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:43:10.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:43:10.23#ibcon#[27=USB\r\n] 2006.201.18:43:10.23#ibcon#*before write, iclass 37, count 0 2006.201.18:43:10.23#ibcon#enter sib2, iclass 37, count 0 2006.201.18:43:10.23#ibcon#flushed, iclass 37, count 0 2006.201.18:43:10.23#ibcon#about to write, iclass 37, count 0 2006.201.18:43:10.23#ibcon#wrote, iclass 37, count 0 2006.201.18:43:10.23#ibcon#about to read 3, iclass 37, count 0 2006.201.18:43:10.26#ibcon#read 3, iclass 37, count 0 2006.201.18:43:10.26#ibcon#about to read 4, iclass 37, count 0 2006.201.18:43:10.26#ibcon#read 4, iclass 37, count 0 2006.201.18:43:10.26#ibcon#about to read 5, iclass 37, count 0 2006.201.18:43:10.26#ibcon#read 5, iclass 37, count 0 2006.201.18:43:10.26#ibcon#about to read 6, iclass 37, count 0 2006.201.18:43:10.26#ibcon#read 6, iclass 37, count 0 2006.201.18:43:10.26#ibcon#end of sib2, iclass 37, count 0 2006.201.18:43:10.26#ibcon#*after write, iclass 37, count 0 2006.201.18:43:10.26#ibcon#*before return 0, iclass 37, count 0 2006.201.18:43:10.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:43:10.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:43:10.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:43:10.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:43:10.26$vck44/vblo=3,649.99 2006.201.18:43:10.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.18:43:10.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.18:43:10.26#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:10.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:10.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:10.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:10.26#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:43:10.26#ibcon#first serial, iclass 40, count 0 2006.201.18:43:10.26#ibcon#enter sib2, iclass 40, count 0 2006.201.18:43:10.26#ibcon#flushed, iclass 40, count 0 2006.201.18:43:10.26#ibcon#about to write, iclass 40, count 0 2006.201.18:43:10.26#ibcon#wrote, iclass 40, count 0 2006.201.18:43:10.26#ibcon#about to read 3, iclass 40, count 0 2006.201.18:43:10.28#ibcon#read 3, iclass 40, count 0 2006.201.18:43:10.28#ibcon#about to read 4, iclass 40, count 0 2006.201.18:43:10.28#ibcon#read 4, iclass 40, count 0 2006.201.18:43:10.28#ibcon#about to read 5, iclass 40, count 0 2006.201.18:43:10.28#ibcon#read 5, iclass 40, count 0 2006.201.18:43:10.28#ibcon#about to read 6, iclass 40, count 0 2006.201.18:43:10.28#ibcon#read 6, iclass 40, count 0 2006.201.18:43:10.28#ibcon#end of sib2, iclass 40, count 0 2006.201.18:43:10.28#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:43:10.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:43:10.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:43:10.28#ibcon#*before write, iclass 40, count 0 2006.201.18:43:10.28#ibcon#enter sib2, iclass 40, count 0 2006.201.18:43:10.28#ibcon#flushed, iclass 40, count 0 2006.201.18:43:10.28#ibcon#about to write, iclass 40, count 0 2006.201.18:43:10.28#ibcon#wrote, iclass 40, count 0 2006.201.18:43:10.28#ibcon#about to read 3, iclass 40, count 0 2006.201.18:43:10.32#ibcon#read 3, iclass 40, count 0 2006.201.18:43:10.32#ibcon#about to read 4, iclass 40, count 0 2006.201.18:43:10.32#ibcon#read 4, iclass 40, count 0 2006.201.18:43:10.32#ibcon#about to read 5, iclass 40, count 0 2006.201.18:43:10.32#ibcon#read 5, iclass 40, count 0 2006.201.18:43:10.32#ibcon#about to read 6, iclass 40, count 0 2006.201.18:43:10.32#ibcon#read 6, iclass 40, count 0 2006.201.18:43:10.32#ibcon#end of sib2, iclass 40, count 0 2006.201.18:43:10.32#ibcon#*after write, iclass 40, count 0 2006.201.18:43:10.32#ibcon#*before return 0, iclass 40, count 0 2006.201.18:43:10.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:10.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.18:43:10.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:43:10.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:43:10.32$vck44/vb=3,4 2006.201.18:43:10.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.18:43:10.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.18:43:10.32#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:10.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:10.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:10.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:10.38#ibcon#enter wrdev, iclass 4, count 2 2006.201.18:43:10.38#ibcon#first serial, iclass 4, count 2 2006.201.18:43:10.38#ibcon#enter sib2, iclass 4, count 2 2006.201.18:43:10.38#ibcon#flushed, iclass 4, count 2 2006.201.18:43:10.38#ibcon#about to write, iclass 4, count 2 2006.201.18:43:10.38#ibcon#wrote, iclass 4, count 2 2006.201.18:43:10.38#ibcon#about to read 3, iclass 4, count 2 2006.201.18:43:10.40#ibcon#read 3, iclass 4, count 2 2006.201.18:43:10.40#ibcon#about to read 4, iclass 4, count 2 2006.201.18:43:10.40#ibcon#read 4, iclass 4, count 2 2006.201.18:43:10.40#ibcon#about to read 5, iclass 4, count 2 2006.201.18:43:10.40#ibcon#read 5, iclass 4, count 2 2006.201.18:43:10.40#ibcon#about to read 6, iclass 4, count 2 2006.201.18:43:10.40#ibcon#read 6, iclass 4, count 2 2006.201.18:43:10.40#ibcon#end of sib2, iclass 4, count 2 2006.201.18:43:10.40#ibcon#*mode == 0, iclass 4, count 2 2006.201.18:43:10.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.18:43:10.40#ibcon#[27=AT03-04\r\n] 2006.201.18:43:10.40#ibcon#*before write, iclass 4, count 2 2006.201.18:43:10.40#ibcon#enter sib2, iclass 4, count 2 2006.201.18:43:10.40#ibcon#flushed, iclass 4, count 2 2006.201.18:43:10.40#ibcon#about to write, iclass 4, count 2 2006.201.18:43:10.40#ibcon#wrote, iclass 4, count 2 2006.201.18:43:10.40#ibcon#about to read 3, iclass 4, count 2 2006.201.18:43:10.43#ibcon#read 3, iclass 4, count 2 2006.201.18:43:10.43#ibcon#about to read 4, iclass 4, count 2 2006.201.18:43:10.43#ibcon#read 4, iclass 4, count 2 2006.201.18:43:10.43#ibcon#about to read 5, iclass 4, count 2 2006.201.18:43:10.43#ibcon#read 5, iclass 4, count 2 2006.201.18:43:10.43#ibcon#about to read 6, iclass 4, count 2 2006.201.18:43:10.43#ibcon#read 6, iclass 4, count 2 2006.201.18:43:10.43#ibcon#end of sib2, iclass 4, count 2 2006.201.18:43:10.43#ibcon#*after write, iclass 4, count 2 2006.201.18:43:10.43#ibcon#*before return 0, iclass 4, count 2 2006.201.18:43:10.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:10.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.18:43:10.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.18:43:10.43#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:10.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:10.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:10.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:10.55#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:43:10.55#ibcon#first serial, iclass 4, count 0 2006.201.18:43:10.55#ibcon#enter sib2, iclass 4, count 0 2006.201.18:43:10.55#ibcon#flushed, iclass 4, count 0 2006.201.18:43:10.55#ibcon#about to write, iclass 4, count 0 2006.201.18:43:10.55#ibcon#wrote, iclass 4, count 0 2006.201.18:43:10.55#ibcon#about to read 3, iclass 4, count 0 2006.201.18:43:10.57#ibcon#read 3, iclass 4, count 0 2006.201.18:43:10.57#ibcon#about to read 4, iclass 4, count 0 2006.201.18:43:10.57#ibcon#read 4, iclass 4, count 0 2006.201.18:43:10.57#ibcon#about to read 5, iclass 4, count 0 2006.201.18:43:10.57#ibcon#read 5, iclass 4, count 0 2006.201.18:43:10.57#ibcon#about to read 6, iclass 4, count 0 2006.201.18:43:10.57#ibcon#read 6, iclass 4, count 0 2006.201.18:43:10.57#ibcon#end of sib2, iclass 4, count 0 2006.201.18:43:10.57#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:43:10.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:43:10.57#ibcon#[27=USB\r\n] 2006.201.18:43:10.57#ibcon#*before write, iclass 4, count 0 2006.201.18:43:10.57#ibcon#enter sib2, iclass 4, count 0 2006.201.18:43:10.57#ibcon#flushed, iclass 4, count 0 2006.201.18:43:10.57#ibcon#about to write, iclass 4, count 0 2006.201.18:43:10.57#ibcon#wrote, iclass 4, count 0 2006.201.18:43:10.57#ibcon#about to read 3, iclass 4, count 0 2006.201.18:43:10.60#ibcon#read 3, iclass 4, count 0 2006.201.18:43:10.60#ibcon#about to read 4, iclass 4, count 0 2006.201.18:43:10.60#ibcon#read 4, iclass 4, count 0 2006.201.18:43:10.60#ibcon#about to read 5, iclass 4, count 0 2006.201.18:43:10.60#ibcon#read 5, iclass 4, count 0 2006.201.18:43:10.60#ibcon#about to read 6, iclass 4, count 0 2006.201.18:43:10.60#ibcon#read 6, iclass 4, count 0 2006.201.18:43:10.60#ibcon#end of sib2, iclass 4, count 0 2006.201.18:43:10.60#ibcon#*after write, iclass 4, count 0 2006.201.18:43:10.60#ibcon#*before return 0, iclass 4, count 0 2006.201.18:43:10.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:10.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.18:43:10.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:43:10.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:43:10.60$vck44/vblo=4,679.99 2006.201.18:43:10.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.18:43:10.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.18:43:10.60#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:10.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:10.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:10.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:10.60#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:43:10.60#ibcon#first serial, iclass 6, count 0 2006.201.18:43:10.60#ibcon#enter sib2, iclass 6, count 0 2006.201.18:43:10.60#ibcon#flushed, iclass 6, count 0 2006.201.18:43:10.60#ibcon#about to write, iclass 6, count 0 2006.201.18:43:10.60#ibcon#wrote, iclass 6, count 0 2006.201.18:43:10.60#ibcon#about to read 3, iclass 6, count 0 2006.201.18:43:10.62#ibcon#read 3, iclass 6, count 0 2006.201.18:43:10.62#ibcon#about to read 4, iclass 6, count 0 2006.201.18:43:10.62#ibcon#read 4, iclass 6, count 0 2006.201.18:43:10.62#ibcon#about to read 5, iclass 6, count 0 2006.201.18:43:10.62#ibcon#read 5, iclass 6, count 0 2006.201.18:43:10.62#ibcon#about to read 6, iclass 6, count 0 2006.201.18:43:10.62#ibcon#read 6, iclass 6, count 0 2006.201.18:43:10.62#ibcon#end of sib2, iclass 6, count 0 2006.201.18:43:10.62#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:43:10.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:43:10.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:43:10.62#ibcon#*before write, iclass 6, count 0 2006.201.18:43:10.62#ibcon#enter sib2, iclass 6, count 0 2006.201.18:43:10.62#ibcon#flushed, iclass 6, count 0 2006.201.18:43:10.62#ibcon#about to write, iclass 6, count 0 2006.201.18:43:10.62#ibcon#wrote, iclass 6, count 0 2006.201.18:43:10.62#ibcon#about to read 3, iclass 6, count 0 2006.201.18:43:10.67#ibcon#read 3, iclass 6, count 0 2006.201.18:43:10.67#ibcon#about to read 4, iclass 6, count 0 2006.201.18:43:10.67#ibcon#read 4, iclass 6, count 0 2006.201.18:43:10.67#ibcon#about to read 5, iclass 6, count 0 2006.201.18:43:10.67#ibcon#read 5, iclass 6, count 0 2006.201.18:43:10.67#ibcon#about to read 6, iclass 6, count 0 2006.201.18:43:10.67#ibcon#read 6, iclass 6, count 0 2006.201.18:43:10.67#ibcon#end of sib2, iclass 6, count 0 2006.201.18:43:10.67#ibcon#*after write, iclass 6, count 0 2006.201.18:43:10.67#ibcon#*before return 0, iclass 6, count 0 2006.201.18:43:10.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:10.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.18:43:10.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:43:10.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:43:10.67$vck44/vb=4,5 2006.201.18:43:10.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.18:43:10.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.18:43:10.67#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:10.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:10.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:10.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:10.72#ibcon#enter wrdev, iclass 10, count 2 2006.201.18:43:10.72#ibcon#first serial, iclass 10, count 2 2006.201.18:43:10.72#ibcon#enter sib2, iclass 10, count 2 2006.201.18:43:10.72#ibcon#flushed, iclass 10, count 2 2006.201.18:43:10.72#ibcon#about to write, iclass 10, count 2 2006.201.18:43:10.72#ibcon#wrote, iclass 10, count 2 2006.201.18:43:10.72#ibcon#about to read 3, iclass 10, count 2 2006.201.18:43:10.74#ibcon#read 3, iclass 10, count 2 2006.201.18:43:10.74#ibcon#about to read 4, iclass 10, count 2 2006.201.18:43:10.74#ibcon#read 4, iclass 10, count 2 2006.201.18:43:10.74#ibcon#about to read 5, iclass 10, count 2 2006.201.18:43:10.74#ibcon#read 5, iclass 10, count 2 2006.201.18:43:10.74#ibcon#about to read 6, iclass 10, count 2 2006.201.18:43:10.74#ibcon#read 6, iclass 10, count 2 2006.201.18:43:10.74#ibcon#end of sib2, iclass 10, count 2 2006.201.18:43:10.74#ibcon#*mode == 0, iclass 10, count 2 2006.201.18:43:10.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.18:43:10.74#ibcon#[27=AT04-05\r\n] 2006.201.18:43:10.74#ibcon#*before write, iclass 10, count 2 2006.201.18:43:10.74#ibcon#enter sib2, iclass 10, count 2 2006.201.18:43:10.74#ibcon#flushed, iclass 10, count 2 2006.201.18:43:10.74#ibcon#about to write, iclass 10, count 2 2006.201.18:43:10.74#ibcon#wrote, iclass 10, count 2 2006.201.18:43:10.74#ibcon#about to read 3, iclass 10, count 2 2006.201.18:43:10.77#ibcon#read 3, iclass 10, count 2 2006.201.18:43:10.77#ibcon#about to read 4, iclass 10, count 2 2006.201.18:43:10.77#ibcon#read 4, iclass 10, count 2 2006.201.18:43:10.77#ibcon#about to read 5, iclass 10, count 2 2006.201.18:43:10.77#ibcon#read 5, iclass 10, count 2 2006.201.18:43:10.77#ibcon#about to read 6, iclass 10, count 2 2006.201.18:43:10.77#ibcon#read 6, iclass 10, count 2 2006.201.18:43:10.77#ibcon#end of sib2, iclass 10, count 2 2006.201.18:43:10.77#ibcon#*after write, iclass 10, count 2 2006.201.18:43:10.77#ibcon#*before return 0, iclass 10, count 2 2006.201.18:43:10.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:10.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.18:43:10.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.18:43:10.77#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:10.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:10.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:10.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:10.89#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:43:10.89#ibcon#first serial, iclass 10, count 0 2006.201.18:43:10.89#ibcon#enter sib2, iclass 10, count 0 2006.201.18:43:10.89#ibcon#flushed, iclass 10, count 0 2006.201.18:43:10.89#ibcon#about to write, iclass 10, count 0 2006.201.18:43:10.89#ibcon#wrote, iclass 10, count 0 2006.201.18:43:10.89#ibcon#about to read 3, iclass 10, count 0 2006.201.18:43:10.91#ibcon#read 3, iclass 10, count 0 2006.201.18:43:10.91#ibcon#about to read 4, iclass 10, count 0 2006.201.18:43:10.91#ibcon#read 4, iclass 10, count 0 2006.201.18:43:10.91#ibcon#about to read 5, iclass 10, count 0 2006.201.18:43:10.91#ibcon#read 5, iclass 10, count 0 2006.201.18:43:10.91#ibcon#about to read 6, iclass 10, count 0 2006.201.18:43:10.91#ibcon#read 6, iclass 10, count 0 2006.201.18:43:10.91#ibcon#end of sib2, iclass 10, count 0 2006.201.18:43:10.91#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:43:10.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:43:10.91#ibcon#[27=USB\r\n] 2006.201.18:43:10.91#ibcon#*before write, iclass 10, count 0 2006.201.18:43:10.91#ibcon#enter sib2, iclass 10, count 0 2006.201.18:43:10.91#ibcon#flushed, iclass 10, count 0 2006.201.18:43:10.91#ibcon#about to write, iclass 10, count 0 2006.201.18:43:10.91#ibcon#wrote, iclass 10, count 0 2006.201.18:43:10.91#ibcon#about to read 3, iclass 10, count 0 2006.201.18:43:10.94#ibcon#read 3, iclass 10, count 0 2006.201.18:43:10.94#ibcon#about to read 4, iclass 10, count 0 2006.201.18:43:10.94#ibcon#read 4, iclass 10, count 0 2006.201.18:43:10.94#ibcon#about to read 5, iclass 10, count 0 2006.201.18:43:10.94#ibcon#read 5, iclass 10, count 0 2006.201.18:43:10.94#ibcon#about to read 6, iclass 10, count 0 2006.201.18:43:10.94#ibcon#read 6, iclass 10, count 0 2006.201.18:43:10.94#ibcon#end of sib2, iclass 10, count 0 2006.201.18:43:10.94#ibcon#*after write, iclass 10, count 0 2006.201.18:43:10.94#ibcon#*before return 0, iclass 10, count 0 2006.201.18:43:10.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:10.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.18:43:10.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:43:10.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:43:10.94$vck44/vblo=5,709.99 2006.201.18:43:10.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.18:43:10.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.18:43:10.94#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:10.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:10.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:10.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:10.94#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:43:10.94#ibcon#first serial, iclass 12, count 0 2006.201.18:43:10.94#ibcon#enter sib2, iclass 12, count 0 2006.201.18:43:10.94#ibcon#flushed, iclass 12, count 0 2006.201.18:43:10.94#ibcon#about to write, iclass 12, count 0 2006.201.18:43:10.94#ibcon#wrote, iclass 12, count 0 2006.201.18:43:10.94#ibcon#about to read 3, iclass 12, count 0 2006.201.18:43:10.96#ibcon#read 3, iclass 12, count 0 2006.201.18:43:10.96#ibcon#about to read 4, iclass 12, count 0 2006.201.18:43:10.96#ibcon#read 4, iclass 12, count 0 2006.201.18:43:10.96#ibcon#about to read 5, iclass 12, count 0 2006.201.18:43:10.96#ibcon#read 5, iclass 12, count 0 2006.201.18:43:10.96#ibcon#about to read 6, iclass 12, count 0 2006.201.18:43:10.96#ibcon#read 6, iclass 12, count 0 2006.201.18:43:10.96#ibcon#end of sib2, iclass 12, count 0 2006.201.18:43:10.96#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:43:10.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:43:10.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:43:10.96#ibcon#*before write, iclass 12, count 0 2006.201.18:43:10.96#ibcon#enter sib2, iclass 12, count 0 2006.201.18:43:10.96#ibcon#flushed, iclass 12, count 0 2006.201.18:43:10.96#ibcon#about to write, iclass 12, count 0 2006.201.18:43:10.96#ibcon#wrote, iclass 12, count 0 2006.201.18:43:10.96#ibcon#about to read 3, iclass 12, count 0 2006.201.18:43:11.00#ibcon#read 3, iclass 12, count 0 2006.201.18:43:11.00#ibcon#about to read 4, iclass 12, count 0 2006.201.18:43:11.00#ibcon#read 4, iclass 12, count 0 2006.201.18:43:11.00#ibcon#about to read 5, iclass 12, count 0 2006.201.18:43:11.00#ibcon#read 5, iclass 12, count 0 2006.201.18:43:11.00#ibcon#about to read 6, iclass 12, count 0 2006.201.18:43:11.00#ibcon#read 6, iclass 12, count 0 2006.201.18:43:11.00#ibcon#end of sib2, iclass 12, count 0 2006.201.18:43:11.00#ibcon#*after write, iclass 12, count 0 2006.201.18:43:11.00#ibcon#*before return 0, iclass 12, count 0 2006.201.18:43:11.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:11.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.18:43:11.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:43:11.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:43:11.00$vck44/vb=5,4 2006.201.18:43:11.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.18:43:11.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.18:43:11.00#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:11.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:11.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:11.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:11.06#ibcon#enter wrdev, iclass 14, count 2 2006.201.18:43:11.06#ibcon#first serial, iclass 14, count 2 2006.201.18:43:11.06#ibcon#enter sib2, iclass 14, count 2 2006.201.18:43:11.06#ibcon#flushed, iclass 14, count 2 2006.201.18:43:11.06#ibcon#about to write, iclass 14, count 2 2006.201.18:43:11.06#ibcon#wrote, iclass 14, count 2 2006.201.18:43:11.06#ibcon#about to read 3, iclass 14, count 2 2006.201.18:43:11.08#ibcon#read 3, iclass 14, count 2 2006.201.18:43:11.08#ibcon#about to read 4, iclass 14, count 2 2006.201.18:43:11.08#ibcon#read 4, iclass 14, count 2 2006.201.18:43:11.08#ibcon#about to read 5, iclass 14, count 2 2006.201.18:43:11.08#ibcon#read 5, iclass 14, count 2 2006.201.18:43:11.08#ibcon#about to read 6, iclass 14, count 2 2006.201.18:43:11.08#ibcon#read 6, iclass 14, count 2 2006.201.18:43:11.08#ibcon#end of sib2, iclass 14, count 2 2006.201.18:43:11.08#ibcon#*mode == 0, iclass 14, count 2 2006.201.18:43:11.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.18:43:11.08#ibcon#[27=AT05-04\r\n] 2006.201.18:43:11.08#ibcon#*before write, iclass 14, count 2 2006.201.18:43:11.08#ibcon#enter sib2, iclass 14, count 2 2006.201.18:43:11.08#ibcon#flushed, iclass 14, count 2 2006.201.18:43:11.08#ibcon#about to write, iclass 14, count 2 2006.201.18:43:11.08#ibcon#wrote, iclass 14, count 2 2006.201.18:43:11.08#ibcon#about to read 3, iclass 14, count 2 2006.201.18:43:11.11#ibcon#read 3, iclass 14, count 2 2006.201.18:43:11.11#ibcon#about to read 4, iclass 14, count 2 2006.201.18:43:11.11#ibcon#read 4, iclass 14, count 2 2006.201.18:43:11.11#ibcon#about to read 5, iclass 14, count 2 2006.201.18:43:11.11#ibcon#read 5, iclass 14, count 2 2006.201.18:43:11.11#ibcon#about to read 6, iclass 14, count 2 2006.201.18:43:11.11#ibcon#read 6, iclass 14, count 2 2006.201.18:43:11.11#ibcon#end of sib2, iclass 14, count 2 2006.201.18:43:11.11#ibcon#*after write, iclass 14, count 2 2006.201.18:43:11.11#ibcon#*before return 0, iclass 14, count 2 2006.201.18:43:11.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:11.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.18:43:11.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.18:43:11.11#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:11.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:11.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:11.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:11.23#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:43:11.23#ibcon#first serial, iclass 14, count 0 2006.201.18:43:11.23#ibcon#enter sib2, iclass 14, count 0 2006.201.18:43:11.23#ibcon#flushed, iclass 14, count 0 2006.201.18:43:11.23#ibcon#about to write, iclass 14, count 0 2006.201.18:43:11.23#ibcon#wrote, iclass 14, count 0 2006.201.18:43:11.23#ibcon#about to read 3, iclass 14, count 0 2006.201.18:43:11.25#ibcon#read 3, iclass 14, count 0 2006.201.18:43:11.25#ibcon#about to read 4, iclass 14, count 0 2006.201.18:43:11.25#ibcon#read 4, iclass 14, count 0 2006.201.18:43:11.25#ibcon#about to read 5, iclass 14, count 0 2006.201.18:43:11.25#ibcon#read 5, iclass 14, count 0 2006.201.18:43:11.25#ibcon#about to read 6, iclass 14, count 0 2006.201.18:43:11.25#ibcon#read 6, iclass 14, count 0 2006.201.18:43:11.25#ibcon#end of sib2, iclass 14, count 0 2006.201.18:43:11.25#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:43:11.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:43:11.25#ibcon#[27=USB\r\n] 2006.201.18:43:11.25#ibcon#*before write, iclass 14, count 0 2006.201.18:43:11.25#ibcon#enter sib2, iclass 14, count 0 2006.201.18:43:11.25#ibcon#flushed, iclass 14, count 0 2006.201.18:43:11.25#ibcon#about to write, iclass 14, count 0 2006.201.18:43:11.25#ibcon#wrote, iclass 14, count 0 2006.201.18:43:11.25#ibcon#about to read 3, iclass 14, count 0 2006.201.18:43:11.28#ibcon#read 3, iclass 14, count 0 2006.201.18:43:11.28#ibcon#about to read 4, iclass 14, count 0 2006.201.18:43:11.28#ibcon#read 4, iclass 14, count 0 2006.201.18:43:11.28#ibcon#about to read 5, iclass 14, count 0 2006.201.18:43:11.28#ibcon#read 5, iclass 14, count 0 2006.201.18:43:11.28#ibcon#about to read 6, iclass 14, count 0 2006.201.18:43:11.28#ibcon#read 6, iclass 14, count 0 2006.201.18:43:11.28#ibcon#end of sib2, iclass 14, count 0 2006.201.18:43:11.28#ibcon#*after write, iclass 14, count 0 2006.201.18:43:11.28#ibcon#*before return 0, iclass 14, count 0 2006.201.18:43:11.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:11.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.18:43:11.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:43:11.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:43:11.28$vck44/vblo=6,719.99 2006.201.18:43:11.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.18:43:11.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.18:43:11.28#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:11.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:11.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:11.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:11.28#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:43:11.28#ibcon#first serial, iclass 16, count 0 2006.201.18:43:11.28#ibcon#enter sib2, iclass 16, count 0 2006.201.18:43:11.28#ibcon#flushed, iclass 16, count 0 2006.201.18:43:11.28#ibcon#about to write, iclass 16, count 0 2006.201.18:43:11.28#ibcon#wrote, iclass 16, count 0 2006.201.18:43:11.28#ibcon#about to read 3, iclass 16, count 0 2006.201.18:43:11.30#ibcon#read 3, iclass 16, count 0 2006.201.18:43:11.30#ibcon#about to read 4, iclass 16, count 0 2006.201.18:43:11.30#ibcon#read 4, iclass 16, count 0 2006.201.18:43:11.30#ibcon#about to read 5, iclass 16, count 0 2006.201.18:43:11.30#ibcon#read 5, iclass 16, count 0 2006.201.18:43:11.30#ibcon#about to read 6, iclass 16, count 0 2006.201.18:43:11.30#ibcon#read 6, iclass 16, count 0 2006.201.18:43:11.30#ibcon#end of sib2, iclass 16, count 0 2006.201.18:43:11.30#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:43:11.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:43:11.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:43:11.30#ibcon#*before write, iclass 16, count 0 2006.201.18:43:11.30#ibcon#enter sib2, iclass 16, count 0 2006.201.18:43:11.30#ibcon#flushed, iclass 16, count 0 2006.201.18:43:11.30#ibcon#about to write, iclass 16, count 0 2006.201.18:43:11.30#ibcon#wrote, iclass 16, count 0 2006.201.18:43:11.30#ibcon#about to read 3, iclass 16, count 0 2006.201.18:43:11.34#ibcon#read 3, iclass 16, count 0 2006.201.18:43:11.34#ibcon#about to read 4, iclass 16, count 0 2006.201.18:43:11.34#ibcon#read 4, iclass 16, count 0 2006.201.18:43:11.34#ibcon#about to read 5, iclass 16, count 0 2006.201.18:43:11.34#ibcon#read 5, iclass 16, count 0 2006.201.18:43:11.34#ibcon#about to read 6, iclass 16, count 0 2006.201.18:43:11.34#ibcon#read 6, iclass 16, count 0 2006.201.18:43:11.34#ibcon#end of sib2, iclass 16, count 0 2006.201.18:43:11.34#ibcon#*after write, iclass 16, count 0 2006.201.18:43:11.34#ibcon#*before return 0, iclass 16, count 0 2006.201.18:43:11.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:11.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.18:43:11.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:43:11.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:43:11.34$vck44/vb=6,4 2006.201.18:43:11.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.18:43:11.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.18:43:11.34#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:11.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:11.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:11.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:11.40#ibcon#enter wrdev, iclass 18, count 2 2006.201.18:43:11.40#ibcon#first serial, iclass 18, count 2 2006.201.18:43:11.40#ibcon#enter sib2, iclass 18, count 2 2006.201.18:43:11.40#ibcon#flushed, iclass 18, count 2 2006.201.18:43:11.40#ibcon#about to write, iclass 18, count 2 2006.201.18:43:11.40#ibcon#wrote, iclass 18, count 2 2006.201.18:43:11.40#ibcon#about to read 3, iclass 18, count 2 2006.201.18:43:11.42#ibcon#read 3, iclass 18, count 2 2006.201.18:43:11.42#ibcon#about to read 4, iclass 18, count 2 2006.201.18:43:11.42#ibcon#read 4, iclass 18, count 2 2006.201.18:43:11.42#ibcon#about to read 5, iclass 18, count 2 2006.201.18:43:11.42#ibcon#read 5, iclass 18, count 2 2006.201.18:43:11.42#ibcon#about to read 6, iclass 18, count 2 2006.201.18:43:11.42#ibcon#read 6, iclass 18, count 2 2006.201.18:43:11.42#ibcon#end of sib2, iclass 18, count 2 2006.201.18:43:11.42#ibcon#*mode == 0, iclass 18, count 2 2006.201.18:43:11.42#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.18:43:11.42#ibcon#[27=AT06-04\r\n] 2006.201.18:43:11.42#ibcon#*before write, iclass 18, count 2 2006.201.18:43:11.42#ibcon#enter sib2, iclass 18, count 2 2006.201.18:43:11.42#ibcon#flushed, iclass 18, count 2 2006.201.18:43:11.42#ibcon#about to write, iclass 18, count 2 2006.201.18:43:11.42#ibcon#wrote, iclass 18, count 2 2006.201.18:43:11.42#ibcon#about to read 3, iclass 18, count 2 2006.201.18:43:11.45#ibcon#read 3, iclass 18, count 2 2006.201.18:43:11.45#ibcon#about to read 4, iclass 18, count 2 2006.201.18:43:11.45#ibcon#read 4, iclass 18, count 2 2006.201.18:43:11.45#ibcon#about to read 5, iclass 18, count 2 2006.201.18:43:11.45#ibcon#read 5, iclass 18, count 2 2006.201.18:43:11.45#ibcon#about to read 6, iclass 18, count 2 2006.201.18:43:11.45#ibcon#read 6, iclass 18, count 2 2006.201.18:43:11.45#ibcon#end of sib2, iclass 18, count 2 2006.201.18:43:11.45#ibcon#*after write, iclass 18, count 2 2006.201.18:43:11.45#ibcon#*before return 0, iclass 18, count 2 2006.201.18:43:11.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:11.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.18:43:11.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.18:43:11.45#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:11.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:11.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:11.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:11.57#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:43:11.57#ibcon#first serial, iclass 18, count 0 2006.201.18:43:11.57#ibcon#enter sib2, iclass 18, count 0 2006.201.18:43:11.57#ibcon#flushed, iclass 18, count 0 2006.201.18:43:11.57#ibcon#about to write, iclass 18, count 0 2006.201.18:43:11.57#ibcon#wrote, iclass 18, count 0 2006.201.18:43:11.57#ibcon#about to read 3, iclass 18, count 0 2006.201.18:43:11.59#ibcon#read 3, iclass 18, count 0 2006.201.18:43:11.59#ibcon#about to read 4, iclass 18, count 0 2006.201.18:43:11.59#ibcon#read 4, iclass 18, count 0 2006.201.18:43:11.59#ibcon#about to read 5, iclass 18, count 0 2006.201.18:43:11.59#ibcon#read 5, iclass 18, count 0 2006.201.18:43:11.59#ibcon#about to read 6, iclass 18, count 0 2006.201.18:43:11.59#ibcon#read 6, iclass 18, count 0 2006.201.18:43:11.59#ibcon#end of sib2, iclass 18, count 0 2006.201.18:43:11.59#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:43:11.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:43:11.59#ibcon#[27=USB\r\n] 2006.201.18:43:11.59#ibcon#*before write, iclass 18, count 0 2006.201.18:43:11.59#ibcon#enter sib2, iclass 18, count 0 2006.201.18:43:11.59#ibcon#flushed, iclass 18, count 0 2006.201.18:43:11.59#ibcon#about to write, iclass 18, count 0 2006.201.18:43:11.59#ibcon#wrote, iclass 18, count 0 2006.201.18:43:11.59#ibcon#about to read 3, iclass 18, count 0 2006.201.18:43:11.62#ibcon#read 3, iclass 18, count 0 2006.201.18:43:11.62#ibcon#about to read 4, iclass 18, count 0 2006.201.18:43:11.62#ibcon#read 4, iclass 18, count 0 2006.201.18:43:11.62#ibcon#about to read 5, iclass 18, count 0 2006.201.18:43:11.62#ibcon#read 5, iclass 18, count 0 2006.201.18:43:11.62#ibcon#about to read 6, iclass 18, count 0 2006.201.18:43:11.62#ibcon#read 6, iclass 18, count 0 2006.201.18:43:11.62#ibcon#end of sib2, iclass 18, count 0 2006.201.18:43:11.62#ibcon#*after write, iclass 18, count 0 2006.201.18:43:11.62#ibcon#*before return 0, iclass 18, count 0 2006.201.18:43:11.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:11.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.18:43:11.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:43:11.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:43:11.62$vck44/vblo=7,734.99 2006.201.18:43:11.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.18:43:11.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.18:43:11.62#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:11.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:11.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:11.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:11.62#ibcon#enter wrdev, iclass 20, count 0 2006.201.18:43:11.62#ibcon#first serial, iclass 20, count 0 2006.201.18:43:11.62#ibcon#enter sib2, iclass 20, count 0 2006.201.18:43:11.62#ibcon#flushed, iclass 20, count 0 2006.201.18:43:11.62#ibcon#about to write, iclass 20, count 0 2006.201.18:43:11.62#ibcon#wrote, iclass 20, count 0 2006.201.18:43:11.62#ibcon#about to read 3, iclass 20, count 0 2006.201.18:43:11.64#ibcon#read 3, iclass 20, count 0 2006.201.18:43:11.64#ibcon#about to read 4, iclass 20, count 0 2006.201.18:43:11.64#ibcon#read 4, iclass 20, count 0 2006.201.18:43:11.64#ibcon#about to read 5, iclass 20, count 0 2006.201.18:43:11.64#ibcon#read 5, iclass 20, count 0 2006.201.18:43:11.64#ibcon#about to read 6, iclass 20, count 0 2006.201.18:43:11.64#ibcon#read 6, iclass 20, count 0 2006.201.18:43:11.64#ibcon#end of sib2, iclass 20, count 0 2006.201.18:43:11.64#ibcon#*mode == 0, iclass 20, count 0 2006.201.18:43:11.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.18:43:11.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:43:11.64#ibcon#*before write, iclass 20, count 0 2006.201.18:43:11.64#ibcon#enter sib2, iclass 20, count 0 2006.201.18:43:11.64#ibcon#flushed, iclass 20, count 0 2006.201.18:43:11.64#ibcon#about to write, iclass 20, count 0 2006.201.18:43:11.64#ibcon#wrote, iclass 20, count 0 2006.201.18:43:11.64#ibcon#about to read 3, iclass 20, count 0 2006.201.18:43:11.69#ibcon#read 3, iclass 20, count 0 2006.201.18:43:11.69#ibcon#about to read 4, iclass 20, count 0 2006.201.18:43:11.69#ibcon#read 4, iclass 20, count 0 2006.201.18:43:11.69#ibcon#about to read 5, iclass 20, count 0 2006.201.18:43:11.69#ibcon#read 5, iclass 20, count 0 2006.201.18:43:11.69#ibcon#about to read 6, iclass 20, count 0 2006.201.18:43:11.69#ibcon#read 6, iclass 20, count 0 2006.201.18:43:11.69#ibcon#end of sib2, iclass 20, count 0 2006.201.18:43:11.69#ibcon#*after write, iclass 20, count 0 2006.201.18:43:11.69#ibcon#*before return 0, iclass 20, count 0 2006.201.18:43:11.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:11.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.18:43:11.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.18:43:11.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.18:43:11.69$vck44/vb=7,4 2006.201.18:43:11.69#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.18:43:11.69#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.18:43:11.69#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:11.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:11.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:11.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:11.74#ibcon#enter wrdev, iclass 22, count 2 2006.201.18:43:11.74#ibcon#first serial, iclass 22, count 2 2006.201.18:43:11.74#ibcon#enter sib2, iclass 22, count 2 2006.201.18:43:11.74#ibcon#flushed, iclass 22, count 2 2006.201.18:43:11.74#ibcon#about to write, iclass 22, count 2 2006.201.18:43:11.74#ibcon#wrote, iclass 22, count 2 2006.201.18:43:11.74#ibcon#about to read 3, iclass 22, count 2 2006.201.18:43:11.76#ibcon#read 3, iclass 22, count 2 2006.201.18:43:11.76#ibcon#about to read 4, iclass 22, count 2 2006.201.18:43:11.76#ibcon#read 4, iclass 22, count 2 2006.201.18:43:11.76#ibcon#about to read 5, iclass 22, count 2 2006.201.18:43:11.76#ibcon#read 5, iclass 22, count 2 2006.201.18:43:11.76#ibcon#about to read 6, iclass 22, count 2 2006.201.18:43:11.76#ibcon#read 6, iclass 22, count 2 2006.201.18:43:11.76#ibcon#end of sib2, iclass 22, count 2 2006.201.18:43:11.76#ibcon#*mode == 0, iclass 22, count 2 2006.201.18:43:11.76#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.18:43:11.76#ibcon#[27=AT07-04\r\n] 2006.201.18:43:11.76#ibcon#*before write, iclass 22, count 2 2006.201.18:43:11.76#ibcon#enter sib2, iclass 22, count 2 2006.201.18:43:11.76#ibcon#flushed, iclass 22, count 2 2006.201.18:43:11.76#ibcon#about to write, iclass 22, count 2 2006.201.18:43:11.76#ibcon#wrote, iclass 22, count 2 2006.201.18:43:11.76#ibcon#about to read 3, iclass 22, count 2 2006.201.18:43:11.79#ibcon#read 3, iclass 22, count 2 2006.201.18:43:11.79#ibcon#about to read 4, iclass 22, count 2 2006.201.18:43:11.79#ibcon#read 4, iclass 22, count 2 2006.201.18:43:11.79#ibcon#about to read 5, iclass 22, count 2 2006.201.18:43:11.79#ibcon#read 5, iclass 22, count 2 2006.201.18:43:11.79#ibcon#about to read 6, iclass 22, count 2 2006.201.18:43:11.79#ibcon#read 6, iclass 22, count 2 2006.201.18:43:11.79#ibcon#end of sib2, iclass 22, count 2 2006.201.18:43:11.79#ibcon#*after write, iclass 22, count 2 2006.201.18:43:11.79#ibcon#*before return 0, iclass 22, count 2 2006.201.18:43:11.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:11.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.18:43:11.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.18:43:11.79#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:11.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:11.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:11.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:11.91#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:43:11.91#ibcon#first serial, iclass 22, count 0 2006.201.18:43:11.91#ibcon#enter sib2, iclass 22, count 0 2006.201.18:43:11.91#ibcon#flushed, iclass 22, count 0 2006.201.18:43:11.91#ibcon#about to write, iclass 22, count 0 2006.201.18:43:11.91#ibcon#wrote, iclass 22, count 0 2006.201.18:43:11.91#ibcon#about to read 3, iclass 22, count 0 2006.201.18:43:11.93#ibcon#read 3, iclass 22, count 0 2006.201.18:43:11.93#ibcon#about to read 4, iclass 22, count 0 2006.201.18:43:11.93#ibcon#read 4, iclass 22, count 0 2006.201.18:43:11.93#ibcon#about to read 5, iclass 22, count 0 2006.201.18:43:11.93#ibcon#read 5, iclass 22, count 0 2006.201.18:43:11.93#ibcon#about to read 6, iclass 22, count 0 2006.201.18:43:11.93#ibcon#read 6, iclass 22, count 0 2006.201.18:43:11.93#ibcon#end of sib2, iclass 22, count 0 2006.201.18:43:11.93#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:43:11.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:43:11.93#ibcon#[27=USB\r\n] 2006.201.18:43:11.93#ibcon#*before write, iclass 22, count 0 2006.201.18:43:11.93#ibcon#enter sib2, iclass 22, count 0 2006.201.18:43:11.93#ibcon#flushed, iclass 22, count 0 2006.201.18:43:11.93#ibcon#about to write, iclass 22, count 0 2006.201.18:43:11.93#ibcon#wrote, iclass 22, count 0 2006.201.18:43:11.93#ibcon#about to read 3, iclass 22, count 0 2006.201.18:43:11.96#ibcon#read 3, iclass 22, count 0 2006.201.18:43:11.96#ibcon#about to read 4, iclass 22, count 0 2006.201.18:43:11.96#ibcon#read 4, iclass 22, count 0 2006.201.18:43:11.96#ibcon#about to read 5, iclass 22, count 0 2006.201.18:43:11.96#ibcon#read 5, iclass 22, count 0 2006.201.18:43:11.96#ibcon#about to read 6, iclass 22, count 0 2006.201.18:43:11.96#ibcon#read 6, iclass 22, count 0 2006.201.18:43:11.96#ibcon#end of sib2, iclass 22, count 0 2006.201.18:43:11.96#ibcon#*after write, iclass 22, count 0 2006.201.18:43:11.96#ibcon#*before return 0, iclass 22, count 0 2006.201.18:43:11.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:11.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.18:43:11.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:43:11.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:43:11.96$vck44/vblo=8,744.99 2006.201.18:43:11.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.18:43:11.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.18:43:11.96#ibcon#ireg 17 cls_cnt 0 2006.201.18:43:11.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:11.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:11.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:11.96#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:43:11.96#ibcon#first serial, iclass 24, count 0 2006.201.18:43:11.96#ibcon#enter sib2, iclass 24, count 0 2006.201.18:43:11.96#ibcon#flushed, iclass 24, count 0 2006.201.18:43:11.96#ibcon#about to write, iclass 24, count 0 2006.201.18:43:11.96#ibcon#wrote, iclass 24, count 0 2006.201.18:43:11.96#ibcon#about to read 3, iclass 24, count 0 2006.201.18:43:11.98#ibcon#read 3, iclass 24, count 0 2006.201.18:43:11.98#ibcon#about to read 4, iclass 24, count 0 2006.201.18:43:11.98#ibcon#read 4, iclass 24, count 0 2006.201.18:43:11.98#ibcon#about to read 5, iclass 24, count 0 2006.201.18:43:11.98#ibcon#read 5, iclass 24, count 0 2006.201.18:43:11.98#ibcon#about to read 6, iclass 24, count 0 2006.201.18:43:11.98#ibcon#read 6, iclass 24, count 0 2006.201.18:43:11.98#ibcon#end of sib2, iclass 24, count 0 2006.201.18:43:11.98#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:43:11.98#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:43:11.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:43:11.98#ibcon#*before write, iclass 24, count 0 2006.201.18:43:11.98#ibcon#enter sib2, iclass 24, count 0 2006.201.18:43:11.98#ibcon#flushed, iclass 24, count 0 2006.201.18:43:11.98#ibcon#about to write, iclass 24, count 0 2006.201.18:43:11.98#ibcon#wrote, iclass 24, count 0 2006.201.18:43:11.98#ibcon#about to read 3, iclass 24, count 0 2006.201.18:43:12.02#ibcon#read 3, iclass 24, count 0 2006.201.18:43:12.02#ibcon#about to read 4, iclass 24, count 0 2006.201.18:43:12.02#ibcon#read 4, iclass 24, count 0 2006.201.18:43:12.02#ibcon#about to read 5, iclass 24, count 0 2006.201.18:43:12.02#ibcon#read 5, iclass 24, count 0 2006.201.18:43:12.02#ibcon#about to read 6, iclass 24, count 0 2006.201.18:43:12.02#ibcon#read 6, iclass 24, count 0 2006.201.18:43:12.02#ibcon#end of sib2, iclass 24, count 0 2006.201.18:43:12.02#ibcon#*after write, iclass 24, count 0 2006.201.18:43:12.02#ibcon#*before return 0, iclass 24, count 0 2006.201.18:43:12.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:12.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.18:43:12.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:43:12.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:43:12.02$vck44/vb=8,4 2006.201.18:43:12.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.18:43:12.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.18:43:12.02#ibcon#ireg 11 cls_cnt 2 2006.201.18:43:12.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:12.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:12.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:12.08#ibcon#enter wrdev, iclass 26, count 2 2006.201.18:43:12.08#ibcon#first serial, iclass 26, count 2 2006.201.18:43:12.08#ibcon#enter sib2, iclass 26, count 2 2006.201.18:43:12.08#ibcon#flushed, iclass 26, count 2 2006.201.18:43:12.08#ibcon#about to write, iclass 26, count 2 2006.201.18:43:12.08#ibcon#wrote, iclass 26, count 2 2006.201.18:43:12.08#ibcon#about to read 3, iclass 26, count 2 2006.201.18:43:12.10#ibcon#read 3, iclass 26, count 2 2006.201.18:43:12.10#ibcon#about to read 4, iclass 26, count 2 2006.201.18:43:12.10#ibcon#read 4, iclass 26, count 2 2006.201.18:43:12.10#ibcon#about to read 5, iclass 26, count 2 2006.201.18:43:12.10#ibcon#read 5, iclass 26, count 2 2006.201.18:43:12.10#ibcon#about to read 6, iclass 26, count 2 2006.201.18:43:12.10#ibcon#read 6, iclass 26, count 2 2006.201.18:43:12.10#ibcon#end of sib2, iclass 26, count 2 2006.201.18:43:12.10#ibcon#*mode == 0, iclass 26, count 2 2006.201.18:43:12.10#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.18:43:12.10#ibcon#[27=AT08-04\r\n] 2006.201.18:43:12.10#ibcon#*before write, iclass 26, count 2 2006.201.18:43:12.10#ibcon#enter sib2, iclass 26, count 2 2006.201.18:43:12.10#ibcon#flushed, iclass 26, count 2 2006.201.18:43:12.10#ibcon#about to write, iclass 26, count 2 2006.201.18:43:12.10#ibcon#wrote, iclass 26, count 2 2006.201.18:43:12.10#ibcon#about to read 3, iclass 26, count 2 2006.201.18:43:12.13#ibcon#read 3, iclass 26, count 2 2006.201.18:43:12.13#ibcon#about to read 4, iclass 26, count 2 2006.201.18:43:12.13#ibcon#read 4, iclass 26, count 2 2006.201.18:43:12.13#ibcon#about to read 5, iclass 26, count 2 2006.201.18:43:12.13#ibcon#read 5, iclass 26, count 2 2006.201.18:43:12.13#ibcon#about to read 6, iclass 26, count 2 2006.201.18:43:12.13#ibcon#read 6, iclass 26, count 2 2006.201.18:43:12.13#ibcon#end of sib2, iclass 26, count 2 2006.201.18:43:12.13#ibcon#*after write, iclass 26, count 2 2006.201.18:43:12.13#ibcon#*before return 0, iclass 26, count 2 2006.201.18:43:12.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:12.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.18:43:12.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.18:43:12.13#ibcon#ireg 7 cls_cnt 0 2006.201.18:43:12.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:12.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:12.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:12.25#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:43:12.25#ibcon#first serial, iclass 26, count 0 2006.201.18:43:12.25#ibcon#enter sib2, iclass 26, count 0 2006.201.18:43:12.25#ibcon#flushed, iclass 26, count 0 2006.201.18:43:12.25#ibcon#about to write, iclass 26, count 0 2006.201.18:43:12.25#ibcon#wrote, iclass 26, count 0 2006.201.18:43:12.25#ibcon#about to read 3, iclass 26, count 0 2006.201.18:43:12.27#ibcon#read 3, iclass 26, count 0 2006.201.18:43:12.27#ibcon#about to read 4, iclass 26, count 0 2006.201.18:43:12.27#ibcon#read 4, iclass 26, count 0 2006.201.18:43:12.27#ibcon#about to read 5, iclass 26, count 0 2006.201.18:43:12.27#ibcon#read 5, iclass 26, count 0 2006.201.18:43:12.27#ibcon#about to read 6, iclass 26, count 0 2006.201.18:43:12.27#ibcon#read 6, iclass 26, count 0 2006.201.18:43:12.27#ibcon#end of sib2, iclass 26, count 0 2006.201.18:43:12.27#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:43:12.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:43:12.27#ibcon#[27=USB\r\n] 2006.201.18:43:12.27#ibcon#*before write, iclass 26, count 0 2006.201.18:43:12.27#ibcon#enter sib2, iclass 26, count 0 2006.201.18:43:12.27#ibcon#flushed, iclass 26, count 0 2006.201.18:43:12.27#ibcon#about to write, iclass 26, count 0 2006.201.18:43:12.27#ibcon#wrote, iclass 26, count 0 2006.201.18:43:12.27#ibcon#about to read 3, iclass 26, count 0 2006.201.18:43:12.30#ibcon#read 3, iclass 26, count 0 2006.201.18:43:12.30#ibcon#about to read 4, iclass 26, count 0 2006.201.18:43:12.30#ibcon#read 4, iclass 26, count 0 2006.201.18:43:12.30#ibcon#about to read 5, iclass 26, count 0 2006.201.18:43:12.30#ibcon#read 5, iclass 26, count 0 2006.201.18:43:12.30#ibcon#about to read 6, iclass 26, count 0 2006.201.18:43:12.30#ibcon#read 6, iclass 26, count 0 2006.201.18:43:12.30#ibcon#end of sib2, iclass 26, count 0 2006.201.18:43:12.30#ibcon#*after write, iclass 26, count 0 2006.201.18:43:12.30#ibcon#*before return 0, iclass 26, count 0 2006.201.18:43:12.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:12.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.18:43:12.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:43:12.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:43:12.30$vck44/vabw=wide 2006.201.18:43:12.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.18:43:12.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.18:43:12.30#ibcon#ireg 8 cls_cnt 0 2006.201.18:43:12.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:12.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:12.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:12.30#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:43:12.30#ibcon#first serial, iclass 28, count 0 2006.201.18:43:12.30#ibcon#enter sib2, iclass 28, count 0 2006.201.18:43:12.30#ibcon#flushed, iclass 28, count 0 2006.201.18:43:12.30#ibcon#about to write, iclass 28, count 0 2006.201.18:43:12.30#ibcon#wrote, iclass 28, count 0 2006.201.18:43:12.30#ibcon#about to read 3, iclass 28, count 0 2006.201.18:43:12.32#ibcon#read 3, iclass 28, count 0 2006.201.18:43:12.32#ibcon#about to read 4, iclass 28, count 0 2006.201.18:43:12.32#ibcon#read 4, iclass 28, count 0 2006.201.18:43:12.32#ibcon#about to read 5, iclass 28, count 0 2006.201.18:43:12.32#ibcon#read 5, iclass 28, count 0 2006.201.18:43:12.32#ibcon#about to read 6, iclass 28, count 0 2006.201.18:43:12.32#ibcon#read 6, iclass 28, count 0 2006.201.18:43:12.32#ibcon#end of sib2, iclass 28, count 0 2006.201.18:43:12.32#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:43:12.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:43:12.32#ibcon#[25=BW32\r\n] 2006.201.18:43:12.32#ibcon#*before write, iclass 28, count 0 2006.201.18:43:12.32#ibcon#enter sib2, iclass 28, count 0 2006.201.18:43:12.32#ibcon#flushed, iclass 28, count 0 2006.201.18:43:12.32#ibcon#about to write, iclass 28, count 0 2006.201.18:43:12.32#ibcon#wrote, iclass 28, count 0 2006.201.18:43:12.32#ibcon#about to read 3, iclass 28, count 0 2006.201.18:43:12.35#ibcon#read 3, iclass 28, count 0 2006.201.18:43:12.35#ibcon#about to read 4, iclass 28, count 0 2006.201.18:43:12.35#ibcon#read 4, iclass 28, count 0 2006.201.18:43:12.35#ibcon#about to read 5, iclass 28, count 0 2006.201.18:43:12.35#ibcon#read 5, iclass 28, count 0 2006.201.18:43:12.35#ibcon#about to read 6, iclass 28, count 0 2006.201.18:43:12.35#ibcon#read 6, iclass 28, count 0 2006.201.18:43:12.35#ibcon#end of sib2, iclass 28, count 0 2006.201.18:43:12.35#ibcon#*after write, iclass 28, count 0 2006.201.18:43:12.35#ibcon#*before return 0, iclass 28, count 0 2006.201.18:43:12.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:12.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:43:12.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:43:12.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:43:12.35$vck44/vbbw=wide 2006.201.18:43:12.35#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.18:43:12.35#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.18:43:12.35#ibcon#ireg 8 cls_cnt 0 2006.201.18:43:12.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:43:12.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:43:12.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:43:12.42#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:43:12.42#ibcon#first serial, iclass 30, count 0 2006.201.18:43:12.42#ibcon#enter sib2, iclass 30, count 0 2006.201.18:43:12.42#ibcon#flushed, iclass 30, count 0 2006.201.18:43:12.42#ibcon#about to write, iclass 30, count 0 2006.201.18:43:12.42#ibcon#wrote, iclass 30, count 0 2006.201.18:43:12.42#ibcon#about to read 3, iclass 30, count 0 2006.201.18:43:12.44#ibcon#read 3, iclass 30, count 0 2006.201.18:43:12.44#ibcon#about to read 4, iclass 30, count 0 2006.201.18:43:12.44#ibcon#read 4, iclass 30, count 0 2006.201.18:43:12.44#ibcon#about to read 5, iclass 30, count 0 2006.201.18:43:12.44#ibcon#read 5, iclass 30, count 0 2006.201.18:43:12.44#ibcon#about to read 6, iclass 30, count 0 2006.201.18:43:12.44#ibcon#read 6, iclass 30, count 0 2006.201.18:43:12.44#ibcon#end of sib2, iclass 30, count 0 2006.201.18:43:12.44#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:43:12.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:43:12.44#ibcon#[27=BW32\r\n] 2006.201.18:43:12.44#ibcon#*before write, iclass 30, count 0 2006.201.18:43:12.44#ibcon#enter sib2, iclass 30, count 0 2006.201.18:43:12.44#ibcon#flushed, iclass 30, count 0 2006.201.18:43:12.44#ibcon#about to write, iclass 30, count 0 2006.201.18:43:12.44#ibcon#wrote, iclass 30, count 0 2006.201.18:43:12.44#ibcon#about to read 3, iclass 30, count 0 2006.201.18:43:12.47#ibcon#read 3, iclass 30, count 0 2006.201.18:43:12.47#ibcon#about to read 4, iclass 30, count 0 2006.201.18:43:12.47#ibcon#read 4, iclass 30, count 0 2006.201.18:43:12.47#ibcon#about to read 5, iclass 30, count 0 2006.201.18:43:12.47#ibcon#read 5, iclass 30, count 0 2006.201.18:43:12.47#ibcon#about to read 6, iclass 30, count 0 2006.201.18:43:12.47#ibcon#read 6, iclass 30, count 0 2006.201.18:43:12.47#ibcon#end of sib2, iclass 30, count 0 2006.201.18:43:12.47#ibcon#*after write, iclass 30, count 0 2006.201.18:43:12.47#ibcon#*before return 0, iclass 30, count 0 2006.201.18:43:12.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:43:12.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:43:12.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:43:12.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:43:12.47$setupk4/ifdk4 2006.201.18:43:12.47$ifdk4/lo= 2006.201.18:43:12.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:43:12.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:43:12.47$ifdk4/patch= 2006.201.18:43:12.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:43:12.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:43:12.47$setupk4/!*+20s 2006.201.18:43:20.12#abcon#<5=/02 0.6 2.4 20.491001002.1\r\n> 2006.201.18:43:20.14#abcon#{5=INTERFACE CLEAR} 2006.201.18:43:20.20#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:43:26.92$setupk4/"tpicd 2006.201.18:43:26.92$setupk4/echo=off 2006.201.18:43:26.92$setupk4/xlog=off 2006.201.18:43:26.92:!2006.201.18:45:38 2006.201.18:43:29.14#trakl#Source acquired 2006.201.18:43:29.14#flagr#flagr/antenna,acquired 2006.201.18:45:38.00:preob 2006.201.18:45:39.13/onsource/TRACKING 2006.201.18:45:39.13:!2006.201.18:45:48 2006.201.18:45:48.00:"tape 2006.201.18:45:48.00:"st=record 2006.201.18:45:48.00:data_valid=on 2006.201.18:45:48.00:midob 2006.201.18:45:48.13/onsource/TRACKING 2006.201.18:45:48.13/wx/20.48,1002.1,100 2006.201.18:45:48.28/cable/+6.4802E-03 2006.201.18:45:49.37/va/01,08,usb,yes,37,40 2006.201.18:45:49.37/va/02,07,usb,yes,40,41 2006.201.18:45:49.37/va/03,08,usb,yes,36,38 2006.201.18:45:49.37/va/04,07,usb,yes,41,43 2006.201.18:45:49.37/va/05,04,usb,yes,37,37 2006.201.18:45:49.37/va/06,05,usb,yes,37,37 2006.201.18:45:49.37/va/07,05,usb,yes,36,37 2006.201.18:45:49.37/va/08,04,usb,yes,36,42 2006.201.18:45:49.60/valo/01,524.99,yes,locked 2006.201.18:45:49.60/valo/02,534.99,yes,locked 2006.201.18:45:49.60/valo/03,564.99,yes,locked 2006.201.18:45:49.60/valo/04,624.99,yes,locked 2006.201.18:45:49.60/valo/05,734.99,yes,locked 2006.201.18:45:49.60/valo/06,814.99,yes,locked 2006.201.18:45:49.60/valo/07,864.99,yes,locked 2006.201.18:45:49.60/valo/08,884.99,yes,locked 2006.201.18:45:50.69/vb/01,04,usb,yes,29,27 2006.201.18:45:50.69/vb/02,05,usb,yes,27,27 2006.201.18:45:50.69/vb/03,04,usb,yes,28,31 2006.201.18:45:50.69/vb/04,05,usb,yes,29,28 2006.201.18:45:50.69/vb/05,04,usb,yes,25,28 2006.201.18:45:50.69/vb/06,04,usb,yes,30,26 2006.201.18:45:50.69/vb/07,04,usb,yes,29,29 2006.201.18:45:50.69/vb/08,04,usb,yes,27,30 2006.201.18:45:50.92/vblo/01,629.99,yes,locked 2006.201.18:45:50.92/vblo/02,634.99,yes,locked 2006.201.18:45:50.92/vblo/03,649.99,yes,locked 2006.201.18:45:50.92/vblo/04,679.99,yes,locked 2006.201.18:45:50.92/vblo/05,709.99,yes,locked 2006.201.18:45:50.92/vblo/06,719.99,yes,locked 2006.201.18:45:50.92/vblo/07,734.99,yes,locked 2006.201.18:45:50.92/vblo/08,744.99,yes,locked 2006.201.18:45:51.07/vabw/8 2006.201.18:45:51.22/vbbw/8 2006.201.18:45:51.31/xfe/off,on,15.5 2006.201.18:45:51.68/ifatt/23,28,28,28 2006.201.18:45:52.06/fmout-gps/S +4.49E-07 2006.201.18:45:52.13:!2006.201.18:47:48 2006.201.18:47:48.00:data_valid=off 2006.201.18:47:48.00:"et 2006.201.18:47:48.00:!+3s 2006.201.18:47:51.02:"tape 2006.201.18:47:51.02:postob 2006.201.18:47:51.13/cable/+6.4792E-03 2006.201.18:47:51.13/wx/20.48,1002.1,100 2006.201.18:47:51.20/fmout-gps/S +4.49E-07 2006.201.18:47:51.20:scan_name=201-1854,jd0607,50 2006.201.18:47:51.21:source=0552+398,055530.81,394849.2,2000.0,cw 2006.201.18:47:52.14#flagr#flagr/antenna,new-source 2006.201.18:47:52.14:checkk5 2006.201.18:47:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:47:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:47:53.31/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:47:53.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:47:54.04/chk_obsdata//k5ts1/T2011845??a.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.18:47:54.42/chk_obsdata//k5ts2/T2011845??b.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.18:47:54.79/chk_obsdata//k5ts3/T2011845??c.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.18:47:55.15/chk_obsdata//k5ts4/T2011845??d.dat file size is correct (nominal:480MB, actual:476MB). 2006.201.18:47:55.84/k5log//k5ts1_log_newline 2006.201.18:47:56.52/k5log//k5ts2_log_newline 2006.201.18:47:57.21/k5log//k5ts3_log_newline 2006.201.18:47:57.89/k5log//k5ts4_log_newline 2006.201.18:47:57.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:47:57.91:setupk4=1 2006.201.18:47:57.91$setupk4/echo=on 2006.201.18:47:57.91$setupk4/pcalon 2006.201.18:47:57.91$pcalon/"no phase cal control is implemented here 2006.201.18:47:57.91$setupk4/"tpicd=stop 2006.201.18:47:57.91$setupk4/"rec=synch_on 2006.201.18:47:57.91$setupk4/"rec_mode=128 2006.201.18:47:57.91$setupk4/!* 2006.201.18:47:57.91$setupk4/recpk4 2006.201.18:47:57.91$recpk4/recpatch= 2006.201.18:47:57.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:47:57.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:47:57.92$setupk4/vck44 2006.201.18:47:57.92$vck44/valo=1,524.99 2006.201.18:47:57.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.18:47:57.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.18:47:57.92#ibcon#ireg 17 cls_cnt 0 2006.201.18:47:57.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:47:57.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:47:57.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:47:57.92#ibcon#enter wrdev, iclass 39, count 0 2006.201.18:47:57.92#ibcon#first serial, iclass 39, count 0 2006.201.18:47:57.92#ibcon#enter sib2, iclass 39, count 0 2006.201.18:47:57.92#ibcon#flushed, iclass 39, count 0 2006.201.18:47:57.92#ibcon#about to write, iclass 39, count 0 2006.201.18:47:57.92#ibcon#wrote, iclass 39, count 0 2006.201.18:47:57.92#ibcon#about to read 3, iclass 39, count 0 2006.201.18:47:57.96#ibcon#read 3, iclass 39, count 0 2006.201.18:47:57.96#ibcon#about to read 4, iclass 39, count 0 2006.201.18:47:57.96#ibcon#read 4, iclass 39, count 0 2006.201.18:47:57.96#ibcon#about to read 5, iclass 39, count 0 2006.201.18:47:57.96#ibcon#read 5, iclass 39, count 0 2006.201.18:47:57.96#ibcon#about to read 6, iclass 39, count 0 2006.201.18:47:57.96#ibcon#read 6, iclass 39, count 0 2006.201.18:47:57.96#ibcon#end of sib2, iclass 39, count 0 2006.201.18:47:57.96#ibcon#*mode == 0, iclass 39, count 0 2006.201.18:47:57.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.18:47:57.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:47:57.96#ibcon#*before write, iclass 39, count 0 2006.201.18:47:57.96#ibcon#enter sib2, iclass 39, count 0 2006.201.18:47:57.96#ibcon#flushed, iclass 39, count 0 2006.201.18:47:57.96#ibcon#about to write, iclass 39, count 0 2006.201.18:47:57.96#ibcon#wrote, iclass 39, count 0 2006.201.18:47:57.96#ibcon#about to read 3, iclass 39, count 0 2006.201.18:47:58.01#ibcon#read 3, iclass 39, count 0 2006.201.18:47:58.01#ibcon#about to read 4, iclass 39, count 0 2006.201.18:47:58.01#ibcon#read 4, iclass 39, count 0 2006.201.18:47:58.01#ibcon#about to read 5, iclass 39, count 0 2006.201.18:47:58.01#ibcon#read 5, iclass 39, count 0 2006.201.18:47:58.01#ibcon#about to read 6, iclass 39, count 0 2006.201.18:47:58.01#ibcon#read 6, iclass 39, count 0 2006.201.18:47:58.01#ibcon#end of sib2, iclass 39, count 0 2006.201.18:47:58.01#ibcon#*after write, iclass 39, count 0 2006.201.18:47:58.01#ibcon#*before return 0, iclass 39, count 0 2006.201.18:47:58.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:47:58.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:47:58.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.18:47:58.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.18:47:58.01$vck44/va=1,8 2006.201.18:47:58.01#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.18:47:58.01#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.18:47:58.01#ibcon#ireg 11 cls_cnt 2 2006.201.18:47:58.01#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:47:58.01#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:47:58.01#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:47:58.01#ibcon#enter wrdev, iclass 2, count 2 2006.201.18:47:58.01#ibcon#first serial, iclass 2, count 2 2006.201.18:47:58.01#ibcon#enter sib2, iclass 2, count 2 2006.201.18:47:58.01#ibcon#flushed, iclass 2, count 2 2006.201.18:47:58.01#ibcon#about to write, iclass 2, count 2 2006.201.18:47:58.01#ibcon#wrote, iclass 2, count 2 2006.201.18:47:58.01#ibcon#about to read 3, iclass 2, count 2 2006.201.18:47:58.03#ibcon#read 3, iclass 2, count 2 2006.201.18:47:58.03#ibcon#about to read 4, iclass 2, count 2 2006.201.18:47:58.03#ibcon#read 4, iclass 2, count 2 2006.201.18:47:58.03#ibcon#about to read 5, iclass 2, count 2 2006.201.18:47:58.03#ibcon#read 5, iclass 2, count 2 2006.201.18:47:58.03#ibcon#about to read 6, iclass 2, count 2 2006.201.18:47:58.03#ibcon#read 6, iclass 2, count 2 2006.201.18:47:58.03#ibcon#end of sib2, iclass 2, count 2 2006.201.18:47:58.03#ibcon#*mode == 0, iclass 2, count 2 2006.201.18:47:58.03#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.18:47:58.03#ibcon#[25=AT01-08\r\n] 2006.201.18:47:58.03#ibcon#*before write, iclass 2, count 2 2006.201.18:47:58.03#ibcon#enter sib2, iclass 2, count 2 2006.201.18:47:58.03#ibcon#flushed, iclass 2, count 2 2006.201.18:47:58.03#ibcon#about to write, iclass 2, count 2 2006.201.18:47:58.03#ibcon#wrote, iclass 2, count 2 2006.201.18:47:58.03#ibcon#about to read 3, iclass 2, count 2 2006.201.18:47:58.06#ibcon#read 3, iclass 2, count 2 2006.201.18:47:58.06#ibcon#about to read 4, iclass 2, count 2 2006.201.18:47:58.06#ibcon#read 4, iclass 2, count 2 2006.201.18:47:58.06#ibcon#about to read 5, iclass 2, count 2 2006.201.18:47:58.06#ibcon#read 5, iclass 2, count 2 2006.201.18:47:58.06#ibcon#about to read 6, iclass 2, count 2 2006.201.18:47:58.06#ibcon#read 6, iclass 2, count 2 2006.201.18:47:58.06#ibcon#end of sib2, iclass 2, count 2 2006.201.18:47:58.06#ibcon#*after write, iclass 2, count 2 2006.201.18:47:58.06#ibcon#*before return 0, iclass 2, count 2 2006.201.18:47:58.06#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:47:58.06#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:47:58.06#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.18:47:58.06#ibcon#ireg 7 cls_cnt 0 2006.201.18:47:58.06#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:47:58.18#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:47:58.18#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:47:58.18#ibcon#enter wrdev, iclass 2, count 0 2006.201.18:47:58.18#ibcon#first serial, iclass 2, count 0 2006.201.18:47:58.18#ibcon#enter sib2, iclass 2, count 0 2006.201.18:47:58.18#ibcon#flushed, iclass 2, count 0 2006.201.18:47:58.18#ibcon#about to write, iclass 2, count 0 2006.201.18:47:58.18#ibcon#wrote, iclass 2, count 0 2006.201.18:47:58.18#ibcon#about to read 3, iclass 2, count 0 2006.201.18:47:58.20#ibcon#read 3, iclass 2, count 0 2006.201.18:47:58.20#ibcon#about to read 4, iclass 2, count 0 2006.201.18:47:58.20#ibcon#read 4, iclass 2, count 0 2006.201.18:47:58.20#ibcon#about to read 5, iclass 2, count 0 2006.201.18:47:58.20#ibcon#read 5, iclass 2, count 0 2006.201.18:47:58.20#ibcon#about to read 6, iclass 2, count 0 2006.201.18:47:58.20#ibcon#read 6, iclass 2, count 0 2006.201.18:47:58.20#ibcon#end of sib2, iclass 2, count 0 2006.201.18:47:58.20#ibcon#*mode == 0, iclass 2, count 0 2006.201.18:47:58.20#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.18:47:58.20#ibcon#[25=USB\r\n] 2006.201.18:47:58.20#ibcon#*before write, iclass 2, count 0 2006.201.18:47:58.20#ibcon#enter sib2, iclass 2, count 0 2006.201.18:47:58.20#ibcon#flushed, iclass 2, count 0 2006.201.18:47:58.20#ibcon#about to write, iclass 2, count 0 2006.201.18:47:58.20#ibcon#wrote, iclass 2, count 0 2006.201.18:47:58.20#ibcon#about to read 3, iclass 2, count 0 2006.201.18:47:58.23#ibcon#read 3, iclass 2, count 0 2006.201.18:47:58.23#ibcon#about to read 4, iclass 2, count 0 2006.201.18:47:58.23#ibcon#read 4, iclass 2, count 0 2006.201.18:47:58.23#ibcon#about to read 5, iclass 2, count 0 2006.201.18:47:58.23#ibcon#read 5, iclass 2, count 0 2006.201.18:47:58.23#ibcon#about to read 6, iclass 2, count 0 2006.201.18:47:58.23#ibcon#read 6, iclass 2, count 0 2006.201.18:47:58.23#ibcon#end of sib2, iclass 2, count 0 2006.201.18:47:58.23#ibcon#*after write, iclass 2, count 0 2006.201.18:47:58.23#ibcon#*before return 0, iclass 2, count 0 2006.201.18:47:58.23#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:47:58.23#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:47:58.23#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.18:47:58.23#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.18:47:58.23$vck44/valo=2,534.99 2006.201.18:47:58.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.18:47:58.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.18:47:58.23#ibcon#ireg 17 cls_cnt 0 2006.201.18:47:58.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:47:58.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:47:58.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:47:58.23#ibcon#enter wrdev, iclass 5, count 0 2006.201.18:47:58.23#ibcon#first serial, iclass 5, count 0 2006.201.18:47:58.23#ibcon#enter sib2, iclass 5, count 0 2006.201.18:47:58.23#ibcon#flushed, iclass 5, count 0 2006.201.18:47:58.23#ibcon#about to write, iclass 5, count 0 2006.201.18:47:58.23#ibcon#wrote, iclass 5, count 0 2006.201.18:47:58.23#ibcon#about to read 3, iclass 5, count 0 2006.201.18:47:58.25#ibcon#read 3, iclass 5, count 0 2006.201.18:47:58.25#ibcon#about to read 4, iclass 5, count 0 2006.201.18:47:58.25#ibcon#read 4, iclass 5, count 0 2006.201.18:47:58.25#ibcon#about to read 5, iclass 5, count 0 2006.201.18:47:58.25#ibcon#read 5, iclass 5, count 0 2006.201.18:47:58.25#ibcon#about to read 6, iclass 5, count 0 2006.201.18:47:58.25#ibcon#read 6, iclass 5, count 0 2006.201.18:47:58.25#ibcon#end of sib2, iclass 5, count 0 2006.201.18:47:58.25#ibcon#*mode == 0, iclass 5, count 0 2006.201.18:47:58.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.18:47:58.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:47:58.25#ibcon#*before write, iclass 5, count 0 2006.201.18:47:58.25#ibcon#enter sib2, iclass 5, count 0 2006.201.18:47:58.25#ibcon#flushed, iclass 5, count 0 2006.201.18:47:58.25#ibcon#about to write, iclass 5, count 0 2006.201.18:47:58.25#ibcon#wrote, iclass 5, count 0 2006.201.18:47:58.25#ibcon#about to read 3, iclass 5, count 0 2006.201.18:47:58.29#ibcon#read 3, iclass 5, count 0 2006.201.18:47:58.29#ibcon#about to read 4, iclass 5, count 0 2006.201.18:47:58.29#ibcon#read 4, iclass 5, count 0 2006.201.18:47:58.29#ibcon#about to read 5, iclass 5, count 0 2006.201.18:47:58.29#ibcon#read 5, iclass 5, count 0 2006.201.18:47:58.29#ibcon#about to read 6, iclass 5, count 0 2006.201.18:47:58.29#ibcon#read 6, iclass 5, count 0 2006.201.18:47:58.29#ibcon#end of sib2, iclass 5, count 0 2006.201.18:47:58.29#ibcon#*after write, iclass 5, count 0 2006.201.18:47:58.29#ibcon#*before return 0, iclass 5, count 0 2006.201.18:47:58.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:47:58.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:47:58.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.18:47:58.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.18:47:58.29$vck44/va=2,7 2006.201.18:47:58.29#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.18:47:58.29#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.18:47:58.29#ibcon#ireg 11 cls_cnt 2 2006.201.18:47:58.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:47:58.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:47:58.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:47:58.35#ibcon#enter wrdev, iclass 7, count 2 2006.201.18:47:58.35#ibcon#first serial, iclass 7, count 2 2006.201.18:47:58.35#ibcon#enter sib2, iclass 7, count 2 2006.201.18:47:58.35#ibcon#flushed, iclass 7, count 2 2006.201.18:47:58.35#ibcon#about to write, iclass 7, count 2 2006.201.18:47:58.35#ibcon#wrote, iclass 7, count 2 2006.201.18:47:58.35#ibcon#about to read 3, iclass 7, count 2 2006.201.18:47:58.37#ibcon#read 3, iclass 7, count 2 2006.201.18:47:58.37#ibcon#about to read 4, iclass 7, count 2 2006.201.18:47:58.37#ibcon#read 4, iclass 7, count 2 2006.201.18:47:58.37#ibcon#about to read 5, iclass 7, count 2 2006.201.18:47:58.37#ibcon#read 5, iclass 7, count 2 2006.201.18:47:58.37#ibcon#about to read 6, iclass 7, count 2 2006.201.18:47:58.37#ibcon#read 6, iclass 7, count 2 2006.201.18:47:58.37#ibcon#end of sib2, iclass 7, count 2 2006.201.18:47:58.37#ibcon#*mode == 0, iclass 7, count 2 2006.201.18:47:58.37#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.18:47:58.37#ibcon#[25=AT02-07\r\n] 2006.201.18:47:58.37#ibcon#*before write, iclass 7, count 2 2006.201.18:47:58.37#ibcon#enter sib2, iclass 7, count 2 2006.201.18:47:58.37#ibcon#flushed, iclass 7, count 2 2006.201.18:47:58.37#ibcon#about to write, iclass 7, count 2 2006.201.18:47:58.37#ibcon#wrote, iclass 7, count 2 2006.201.18:47:58.37#ibcon#about to read 3, iclass 7, count 2 2006.201.18:47:58.40#ibcon#read 3, iclass 7, count 2 2006.201.18:47:58.40#ibcon#about to read 4, iclass 7, count 2 2006.201.18:47:58.40#ibcon#read 4, iclass 7, count 2 2006.201.18:47:58.40#ibcon#about to read 5, iclass 7, count 2 2006.201.18:47:58.40#ibcon#read 5, iclass 7, count 2 2006.201.18:47:58.40#ibcon#about to read 6, iclass 7, count 2 2006.201.18:47:58.40#ibcon#read 6, iclass 7, count 2 2006.201.18:47:58.40#ibcon#end of sib2, iclass 7, count 2 2006.201.18:47:58.40#ibcon#*after write, iclass 7, count 2 2006.201.18:47:58.40#ibcon#*before return 0, iclass 7, count 2 2006.201.18:47:58.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:47:58.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:47:58.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.18:47:58.40#ibcon#ireg 7 cls_cnt 0 2006.201.18:47:58.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:47:58.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:47:58.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:47:58.52#ibcon#enter wrdev, iclass 7, count 0 2006.201.18:47:58.52#ibcon#first serial, iclass 7, count 0 2006.201.18:47:58.52#ibcon#enter sib2, iclass 7, count 0 2006.201.18:47:58.52#ibcon#flushed, iclass 7, count 0 2006.201.18:47:58.52#ibcon#about to write, iclass 7, count 0 2006.201.18:47:58.52#ibcon#wrote, iclass 7, count 0 2006.201.18:47:58.52#ibcon#about to read 3, iclass 7, count 0 2006.201.18:47:58.54#ibcon#read 3, iclass 7, count 0 2006.201.18:47:58.54#ibcon#about to read 4, iclass 7, count 0 2006.201.18:47:58.54#ibcon#read 4, iclass 7, count 0 2006.201.18:47:58.54#ibcon#about to read 5, iclass 7, count 0 2006.201.18:47:58.54#ibcon#read 5, iclass 7, count 0 2006.201.18:47:58.54#ibcon#about to read 6, iclass 7, count 0 2006.201.18:47:58.54#ibcon#read 6, iclass 7, count 0 2006.201.18:47:58.54#ibcon#end of sib2, iclass 7, count 0 2006.201.18:47:58.54#ibcon#*mode == 0, iclass 7, count 0 2006.201.18:47:58.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.18:47:58.54#ibcon#[25=USB\r\n] 2006.201.18:47:58.54#ibcon#*before write, iclass 7, count 0 2006.201.18:47:58.54#ibcon#enter sib2, iclass 7, count 0 2006.201.18:47:58.54#ibcon#flushed, iclass 7, count 0 2006.201.18:47:58.54#ibcon#about to write, iclass 7, count 0 2006.201.18:47:58.54#ibcon#wrote, iclass 7, count 0 2006.201.18:47:58.54#ibcon#about to read 3, iclass 7, count 0 2006.201.18:47:58.57#ibcon#read 3, iclass 7, count 0 2006.201.18:47:58.57#ibcon#about to read 4, iclass 7, count 0 2006.201.18:47:58.57#ibcon#read 4, iclass 7, count 0 2006.201.18:47:58.57#ibcon#about to read 5, iclass 7, count 0 2006.201.18:47:58.57#ibcon#read 5, iclass 7, count 0 2006.201.18:47:58.57#ibcon#about to read 6, iclass 7, count 0 2006.201.18:47:58.57#ibcon#read 6, iclass 7, count 0 2006.201.18:47:58.57#ibcon#end of sib2, iclass 7, count 0 2006.201.18:47:58.57#ibcon#*after write, iclass 7, count 0 2006.201.18:47:58.57#ibcon#*before return 0, iclass 7, count 0 2006.201.18:47:58.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:47:58.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:47:58.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.18:47:58.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.18:47:58.57$vck44/valo=3,564.99 2006.201.18:47:58.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.18:47:58.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.18:47:58.57#ibcon#ireg 17 cls_cnt 0 2006.201.18:47:58.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:47:58.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:47:58.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:47:58.57#ibcon#enter wrdev, iclass 11, count 0 2006.201.18:47:58.57#ibcon#first serial, iclass 11, count 0 2006.201.18:47:58.57#ibcon#enter sib2, iclass 11, count 0 2006.201.18:47:58.57#ibcon#flushed, iclass 11, count 0 2006.201.18:47:58.57#ibcon#about to write, iclass 11, count 0 2006.201.18:47:58.57#ibcon#wrote, iclass 11, count 0 2006.201.18:47:58.57#ibcon#about to read 3, iclass 11, count 0 2006.201.18:47:58.59#ibcon#read 3, iclass 11, count 0 2006.201.18:47:58.59#ibcon#about to read 4, iclass 11, count 0 2006.201.18:47:58.59#ibcon#read 4, iclass 11, count 0 2006.201.18:47:58.59#ibcon#about to read 5, iclass 11, count 0 2006.201.18:47:58.59#ibcon#read 5, iclass 11, count 0 2006.201.18:47:58.59#ibcon#about to read 6, iclass 11, count 0 2006.201.18:47:58.59#ibcon#read 6, iclass 11, count 0 2006.201.18:47:58.59#ibcon#end of sib2, iclass 11, count 0 2006.201.18:47:58.59#ibcon#*mode == 0, iclass 11, count 0 2006.201.18:47:58.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.18:47:58.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:47:58.59#ibcon#*before write, iclass 11, count 0 2006.201.18:47:58.59#ibcon#enter sib2, iclass 11, count 0 2006.201.18:47:58.59#ibcon#flushed, iclass 11, count 0 2006.201.18:47:58.59#ibcon#about to write, iclass 11, count 0 2006.201.18:47:58.59#ibcon#wrote, iclass 11, count 0 2006.201.18:47:58.59#ibcon#about to read 3, iclass 11, count 0 2006.201.18:47:58.64#ibcon#read 3, iclass 11, count 0 2006.201.18:47:58.64#ibcon#about to read 4, iclass 11, count 0 2006.201.18:47:58.64#ibcon#read 4, iclass 11, count 0 2006.201.18:47:58.64#ibcon#about to read 5, iclass 11, count 0 2006.201.18:47:58.64#ibcon#read 5, iclass 11, count 0 2006.201.18:47:58.64#ibcon#about to read 6, iclass 11, count 0 2006.201.18:47:58.64#ibcon#read 6, iclass 11, count 0 2006.201.18:47:58.64#ibcon#end of sib2, iclass 11, count 0 2006.201.18:47:58.64#ibcon#*after write, iclass 11, count 0 2006.201.18:47:58.64#ibcon#*before return 0, iclass 11, count 0 2006.201.18:47:58.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:47:58.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:47:58.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.18:47:58.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.18:47:58.64$vck44/va=3,8 2006.201.18:47:58.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.18:47:58.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.18:47:58.64#ibcon#ireg 11 cls_cnt 2 2006.201.18:47:58.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:47:58.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:47:58.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:47:58.69#ibcon#enter wrdev, iclass 13, count 2 2006.201.18:47:58.69#ibcon#first serial, iclass 13, count 2 2006.201.18:47:58.69#ibcon#enter sib2, iclass 13, count 2 2006.201.18:47:58.69#ibcon#flushed, iclass 13, count 2 2006.201.18:47:58.69#ibcon#about to write, iclass 13, count 2 2006.201.18:47:58.69#ibcon#wrote, iclass 13, count 2 2006.201.18:47:58.69#ibcon#about to read 3, iclass 13, count 2 2006.201.18:47:58.71#ibcon#read 3, iclass 13, count 2 2006.201.18:47:58.71#ibcon#about to read 4, iclass 13, count 2 2006.201.18:47:58.71#ibcon#read 4, iclass 13, count 2 2006.201.18:47:58.71#ibcon#about to read 5, iclass 13, count 2 2006.201.18:47:58.71#ibcon#read 5, iclass 13, count 2 2006.201.18:47:58.71#ibcon#about to read 6, iclass 13, count 2 2006.201.18:47:58.71#ibcon#read 6, iclass 13, count 2 2006.201.18:47:58.71#ibcon#end of sib2, iclass 13, count 2 2006.201.18:47:58.71#ibcon#*mode == 0, iclass 13, count 2 2006.201.18:47:58.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.18:47:58.71#ibcon#[25=AT03-08\r\n] 2006.201.18:47:58.71#ibcon#*before write, iclass 13, count 2 2006.201.18:47:58.71#ibcon#enter sib2, iclass 13, count 2 2006.201.18:47:58.71#ibcon#flushed, iclass 13, count 2 2006.201.18:47:58.71#ibcon#about to write, iclass 13, count 2 2006.201.18:47:58.71#ibcon#wrote, iclass 13, count 2 2006.201.18:47:58.71#ibcon#about to read 3, iclass 13, count 2 2006.201.18:47:58.74#ibcon#read 3, iclass 13, count 2 2006.201.18:47:58.74#ibcon#about to read 4, iclass 13, count 2 2006.201.18:47:58.74#ibcon#read 4, iclass 13, count 2 2006.201.18:47:58.74#ibcon#about to read 5, iclass 13, count 2 2006.201.18:47:58.74#ibcon#read 5, iclass 13, count 2 2006.201.18:47:58.74#ibcon#about to read 6, iclass 13, count 2 2006.201.18:47:58.74#ibcon#read 6, iclass 13, count 2 2006.201.18:47:58.74#ibcon#end of sib2, iclass 13, count 2 2006.201.18:47:58.74#ibcon#*after write, iclass 13, count 2 2006.201.18:47:58.74#ibcon#*before return 0, iclass 13, count 2 2006.201.18:47:58.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:47:58.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:47:58.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.18:47:58.74#ibcon#ireg 7 cls_cnt 0 2006.201.18:47:58.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:47:58.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:47:58.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:47:58.86#ibcon#enter wrdev, iclass 13, count 0 2006.201.18:47:58.86#ibcon#first serial, iclass 13, count 0 2006.201.18:47:58.86#ibcon#enter sib2, iclass 13, count 0 2006.201.18:47:58.86#ibcon#flushed, iclass 13, count 0 2006.201.18:47:58.86#ibcon#about to write, iclass 13, count 0 2006.201.18:47:58.86#ibcon#wrote, iclass 13, count 0 2006.201.18:47:58.86#ibcon#about to read 3, iclass 13, count 0 2006.201.18:47:58.88#ibcon#read 3, iclass 13, count 0 2006.201.18:47:58.88#ibcon#about to read 4, iclass 13, count 0 2006.201.18:47:58.88#ibcon#read 4, iclass 13, count 0 2006.201.18:47:58.88#ibcon#about to read 5, iclass 13, count 0 2006.201.18:47:58.88#ibcon#read 5, iclass 13, count 0 2006.201.18:47:58.88#ibcon#about to read 6, iclass 13, count 0 2006.201.18:47:58.88#ibcon#read 6, iclass 13, count 0 2006.201.18:47:58.88#ibcon#end of sib2, iclass 13, count 0 2006.201.18:47:58.88#ibcon#*mode == 0, iclass 13, count 0 2006.201.18:47:58.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.18:47:58.88#ibcon#[25=USB\r\n] 2006.201.18:47:58.88#ibcon#*before write, iclass 13, count 0 2006.201.18:47:58.88#ibcon#enter sib2, iclass 13, count 0 2006.201.18:47:58.88#ibcon#flushed, iclass 13, count 0 2006.201.18:47:58.88#ibcon#about to write, iclass 13, count 0 2006.201.18:47:58.88#ibcon#wrote, iclass 13, count 0 2006.201.18:47:58.88#ibcon#about to read 3, iclass 13, count 0 2006.201.18:47:58.91#ibcon#read 3, iclass 13, count 0 2006.201.18:47:58.91#ibcon#about to read 4, iclass 13, count 0 2006.201.18:47:58.91#ibcon#read 4, iclass 13, count 0 2006.201.18:47:58.91#ibcon#about to read 5, iclass 13, count 0 2006.201.18:47:58.91#ibcon#read 5, iclass 13, count 0 2006.201.18:47:58.91#ibcon#about to read 6, iclass 13, count 0 2006.201.18:47:58.91#ibcon#read 6, iclass 13, count 0 2006.201.18:47:58.91#ibcon#end of sib2, iclass 13, count 0 2006.201.18:47:58.91#ibcon#*after write, iclass 13, count 0 2006.201.18:47:58.91#ibcon#*before return 0, iclass 13, count 0 2006.201.18:47:58.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:47:58.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:47:58.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.18:47:58.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.18:47:58.91$vck44/valo=4,624.99 2006.201.18:47:58.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.18:47:58.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.18:47:58.91#ibcon#ireg 17 cls_cnt 0 2006.201.18:47:58.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:47:58.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:47:58.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:47:58.91#ibcon#enter wrdev, iclass 15, count 0 2006.201.18:47:58.91#ibcon#first serial, iclass 15, count 0 2006.201.18:47:58.91#ibcon#enter sib2, iclass 15, count 0 2006.201.18:47:58.91#ibcon#flushed, iclass 15, count 0 2006.201.18:47:58.91#ibcon#about to write, iclass 15, count 0 2006.201.18:47:58.91#ibcon#wrote, iclass 15, count 0 2006.201.18:47:58.91#ibcon#about to read 3, iclass 15, count 0 2006.201.18:47:58.93#ibcon#read 3, iclass 15, count 0 2006.201.18:47:58.93#ibcon#about to read 4, iclass 15, count 0 2006.201.18:47:58.93#ibcon#read 4, iclass 15, count 0 2006.201.18:47:58.93#ibcon#about to read 5, iclass 15, count 0 2006.201.18:47:58.93#ibcon#read 5, iclass 15, count 0 2006.201.18:47:58.93#ibcon#about to read 6, iclass 15, count 0 2006.201.18:47:58.93#ibcon#read 6, iclass 15, count 0 2006.201.18:47:58.93#ibcon#end of sib2, iclass 15, count 0 2006.201.18:47:58.93#ibcon#*mode == 0, iclass 15, count 0 2006.201.18:47:58.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.18:47:58.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:47:58.93#ibcon#*before write, iclass 15, count 0 2006.201.18:47:58.93#ibcon#enter sib2, iclass 15, count 0 2006.201.18:47:58.93#ibcon#flushed, iclass 15, count 0 2006.201.18:47:58.93#ibcon#about to write, iclass 15, count 0 2006.201.18:47:58.93#ibcon#wrote, iclass 15, count 0 2006.201.18:47:58.93#ibcon#about to read 3, iclass 15, count 0 2006.201.18:47:58.97#ibcon#read 3, iclass 15, count 0 2006.201.18:47:58.97#ibcon#about to read 4, iclass 15, count 0 2006.201.18:47:58.97#ibcon#read 4, iclass 15, count 0 2006.201.18:47:58.97#ibcon#about to read 5, iclass 15, count 0 2006.201.18:47:58.97#ibcon#read 5, iclass 15, count 0 2006.201.18:47:58.97#ibcon#about to read 6, iclass 15, count 0 2006.201.18:47:58.97#ibcon#read 6, iclass 15, count 0 2006.201.18:47:58.97#ibcon#end of sib2, iclass 15, count 0 2006.201.18:47:58.97#ibcon#*after write, iclass 15, count 0 2006.201.18:47:58.97#ibcon#*before return 0, iclass 15, count 0 2006.201.18:47:58.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:47:58.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:47:58.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.18:47:58.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.18:47:58.97$vck44/va=4,7 2006.201.18:47:58.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.18:47:58.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.18:47:58.97#ibcon#ireg 11 cls_cnt 2 2006.201.18:47:58.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:47:59.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:47:59.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:47:59.03#ibcon#enter wrdev, iclass 17, count 2 2006.201.18:47:59.03#ibcon#first serial, iclass 17, count 2 2006.201.18:47:59.03#ibcon#enter sib2, iclass 17, count 2 2006.201.18:47:59.03#ibcon#flushed, iclass 17, count 2 2006.201.18:47:59.03#ibcon#about to write, iclass 17, count 2 2006.201.18:47:59.03#ibcon#wrote, iclass 17, count 2 2006.201.18:47:59.03#ibcon#about to read 3, iclass 17, count 2 2006.201.18:47:59.05#ibcon#read 3, iclass 17, count 2 2006.201.18:47:59.05#ibcon#about to read 4, iclass 17, count 2 2006.201.18:47:59.05#ibcon#read 4, iclass 17, count 2 2006.201.18:47:59.05#ibcon#about to read 5, iclass 17, count 2 2006.201.18:47:59.05#ibcon#read 5, iclass 17, count 2 2006.201.18:47:59.05#ibcon#about to read 6, iclass 17, count 2 2006.201.18:47:59.05#ibcon#read 6, iclass 17, count 2 2006.201.18:47:59.05#ibcon#end of sib2, iclass 17, count 2 2006.201.18:47:59.05#ibcon#*mode == 0, iclass 17, count 2 2006.201.18:47:59.05#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.18:47:59.05#ibcon#[25=AT04-07\r\n] 2006.201.18:47:59.05#ibcon#*before write, iclass 17, count 2 2006.201.18:47:59.05#ibcon#enter sib2, iclass 17, count 2 2006.201.18:47:59.05#ibcon#flushed, iclass 17, count 2 2006.201.18:47:59.05#ibcon#about to write, iclass 17, count 2 2006.201.18:47:59.05#ibcon#wrote, iclass 17, count 2 2006.201.18:47:59.05#ibcon#about to read 3, iclass 17, count 2 2006.201.18:47:59.08#ibcon#read 3, iclass 17, count 2 2006.201.18:47:59.08#ibcon#about to read 4, iclass 17, count 2 2006.201.18:47:59.08#ibcon#read 4, iclass 17, count 2 2006.201.18:47:59.08#ibcon#about to read 5, iclass 17, count 2 2006.201.18:47:59.08#ibcon#read 5, iclass 17, count 2 2006.201.18:47:59.08#ibcon#about to read 6, iclass 17, count 2 2006.201.18:47:59.08#ibcon#read 6, iclass 17, count 2 2006.201.18:47:59.08#ibcon#end of sib2, iclass 17, count 2 2006.201.18:47:59.08#ibcon#*after write, iclass 17, count 2 2006.201.18:47:59.08#ibcon#*before return 0, iclass 17, count 2 2006.201.18:47:59.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:47:59.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:47:59.08#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.18:47:59.08#ibcon#ireg 7 cls_cnt 0 2006.201.18:47:59.08#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:47:59.20#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:47:59.20#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:47:59.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.18:47:59.20#ibcon#first serial, iclass 17, count 0 2006.201.18:47:59.20#ibcon#enter sib2, iclass 17, count 0 2006.201.18:47:59.20#ibcon#flushed, iclass 17, count 0 2006.201.18:47:59.20#ibcon#about to write, iclass 17, count 0 2006.201.18:47:59.20#ibcon#wrote, iclass 17, count 0 2006.201.18:47:59.20#ibcon#about to read 3, iclass 17, count 0 2006.201.18:47:59.22#ibcon#read 3, iclass 17, count 0 2006.201.18:47:59.22#ibcon#about to read 4, iclass 17, count 0 2006.201.18:47:59.22#ibcon#read 4, iclass 17, count 0 2006.201.18:47:59.22#ibcon#about to read 5, iclass 17, count 0 2006.201.18:47:59.22#ibcon#read 5, iclass 17, count 0 2006.201.18:47:59.22#ibcon#about to read 6, iclass 17, count 0 2006.201.18:47:59.22#ibcon#read 6, iclass 17, count 0 2006.201.18:47:59.22#ibcon#end of sib2, iclass 17, count 0 2006.201.18:47:59.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.18:47:59.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.18:47:59.22#ibcon#[25=USB\r\n] 2006.201.18:47:59.22#ibcon#*before write, iclass 17, count 0 2006.201.18:47:59.22#ibcon#enter sib2, iclass 17, count 0 2006.201.18:47:59.22#ibcon#flushed, iclass 17, count 0 2006.201.18:47:59.22#ibcon#about to write, iclass 17, count 0 2006.201.18:47:59.22#ibcon#wrote, iclass 17, count 0 2006.201.18:47:59.22#ibcon#about to read 3, iclass 17, count 0 2006.201.18:47:59.25#ibcon#read 3, iclass 17, count 0 2006.201.18:47:59.25#ibcon#about to read 4, iclass 17, count 0 2006.201.18:47:59.25#ibcon#read 4, iclass 17, count 0 2006.201.18:47:59.25#ibcon#about to read 5, iclass 17, count 0 2006.201.18:47:59.25#ibcon#read 5, iclass 17, count 0 2006.201.18:47:59.25#ibcon#about to read 6, iclass 17, count 0 2006.201.18:47:59.25#ibcon#read 6, iclass 17, count 0 2006.201.18:47:59.25#ibcon#end of sib2, iclass 17, count 0 2006.201.18:47:59.25#ibcon#*after write, iclass 17, count 0 2006.201.18:47:59.25#ibcon#*before return 0, iclass 17, count 0 2006.201.18:47:59.25#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:47:59.25#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:47:59.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.18:47:59.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.18:47:59.25$vck44/valo=5,734.99 2006.201.18:47:59.25#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.18:47:59.25#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.18:47:59.25#ibcon#ireg 17 cls_cnt 0 2006.201.18:47:59.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:47:59.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:47:59.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:47:59.25#ibcon#enter wrdev, iclass 19, count 0 2006.201.18:47:59.25#ibcon#first serial, iclass 19, count 0 2006.201.18:47:59.25#ibcon#enter sib2, iclass 19, count 0 2006.201.18:47:59.25#ibcon#flushed, iclass 19, count 0 2006.201.18:47:59.25#ibcon#about to write, iclass 19, count 0 2006.201.18:47:59.25#ibcon#wrote, iclass 19, count 0 2006.201.18:47:59.25#ibcon#about to read 3, iclass 19, count 0 2006.201.18:47:59.27#ibcon#read 3, iclass 19, count 0 2006.201.18:47:59.27#ibcon#about to read 4, iclass 19, count 0 2006.201.18:47:59.27#ibcon#read 4, iclass 19, count 0 2006.201.18:47:59.27#ibcon#about to read 5, iclass 19, count 0 2006.201.18:47:59.27#ibcon#read 5, iclass 19, count 0 2006.201.18:47:59.27#ibcon#about to read 6, iclass 19, count 0 2006.201.18:47:59.27#ibcon#read 6, iclass 19, count 0 2006.201.18:47:59.27#ibcon#end of sib2, iclass 19, count 0 2006.201.18:47:59.27#ibcon#*mode == 0, iclass 19, count 0 2006.201.18:47:59.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.18:47:59.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:47:59.27#ibcon#*before write, iclass 19, count 0 2006.201.18:47:59.27#ibcon#enter sib2, iclass 19, count 0 2006.201.18:47:59.27#ibcon#flushed, iclass 19, count 0 2006.201.18:47:59.27#ibcon#about to write, iclass 19, count 0 2006.201.18:47:59.27#ibcon#wrote, iclass 19, count 0 2006.201.18:47:59.27#ibcon#about to read 3, iclass 19, count 0 2006.201.18:47:59.31#ibcon#read 3, iclass 19, count 0 2006.201.18:47:59.31#ibcon#about to read 4, iclass 19, count 0 2006.201.18:47:59.31#ibcon#read 4, iclass 19, count 0 2006.201.18:47:59.31#ibcon#about to read 5, iclass 19, count 0 2006.201.18:47:59.31#ibcon#read 5, iclass 19, count 0 2006.201.18:47:59.31#ibcon#about to read 6, iclass 19, count 0 2006.201.18:47:59.31#ibcon#read 6, iclass 19, count 0 2006.201.18:47:59.31#ibcon#end of sib2, iclass 19, count 0 2006.201.18:47:59.31#ibcon#*after write, iclass 19, count 0 2006.201.18:47:59.31#ibcon#*before return 0, iclass 19, count 0 2006.201.18:47:59.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:47:59.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:47:59.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.18:47:59.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.18:47:59.31$vck44/va=5,4 2006.201.18:47:59.31#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.18:47:59.31#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.18:47:59.31#ibcon#ireg 11 cls_cnt 2 2006.201.18:47:59.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:47:59.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:47:59.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:47:59.37#ibcon#enter wrdev, iclass 21, count 2 2006.201.18:47:59.37#ibcon#first serial, iclass 21, count 2 2006.201.18:47:59.37#ibcon#enter sib2, iclass 21, count 2 2006.201.18:47:59.37#ibcon#flushed, iclass 21, count 2 2006.201.18:47:59.37#ibcon#about to write, iclass 21, count 2 2006.201.18:47:59.37#ibcon#wrote, iclass 21, count 2 2006.201.18:47:59.37#ibcon#about to read 3, iclass 21, count 2 2006.201.18:47:59.39#ibcon#read 3, iclass 21, count 2 2006.201.18:47:59.39#ibcon#about to read 4, iclass 21, count 2 2006.201.18:47:59.39#ibcon#read 4, iclass 21, count 2 2006.201.18:47:59.39#ibcon#about to read 5, iclass 21, count 2 2006.201.18:47:59.39#ibcon#read 5, iclass 21, count 2 2006.201.18:47:59.39#ibcon#about to read 6, iclass 21, count 2 2006.201.18:47:59.39#ibcon#read 6, iclass 21, count 2 2006.201.18:47:59.39#ibcon#end of sib2, iclass 21, count 2 2006.201.18:47:59.39#ibcon#*mode == 0, iclass 21, count 2 2006.201.18:47:59.39#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.18:47:59.39#ibcon#[25=AT05-04\r\n] 2006.201.18:47:59.39#ibcon#*before write, iclass 21, count 2 2006.201.18:47:59.39#ibcon#enter sib2, iclass 21, count 2 2006.201.18:47:59.39#ibcon#flushed, iclass 21, count 2 2006.201.18:47:59.39#ibcon#about to write, iclass 21, count 2 2006.201.18:47:59.39#ibcon#wrote, iclass 21, count 2 2006.201.18:47:59.39#ibcon#about to read 3, iclass 21, count 2 2006.201.18:47:59.42#ibcon#read 3, iclass 21, count 2 2006.201.18:47:59.42#ibcon#about to read 4, iclass 21, count 2 2006.201.18:47:59.42#ibcon#read 4, iclass 21, count 2 2006.201.18:47:59.42#ibcon#about to read 5, iclass 21, count 2 2006.201.18:47:59.42#ibcon#read 5, iclass 21, count 2 2006.201.18:47:59.42#ibcon#about to read 6, iclass 21, count 2 2006.201.18:47:59.42#ibcon#read 6, iclass 21, count 2 2006.201.18:47:59.42#ibcon#end of sib2, iclass 21, count 2 2006.201.18:47:59.42#ibcon#*after write, iclass 21, count 2 2006.201.18:47:59.42#ibcon#*before return 0, iclass 21, count 2 2006.201.18:47:59.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:47:59.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:47:59.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.18:47:59.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:47:59.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:47:59.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:47:59.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:47:59.54#ibcon#enter wrdev, iclass 21, count 0 2006.201.18:47:59.54#ibcon#first serial, iclass 21, count 0 2006.201.18:47:59.54#ibcon#enter sib2, iclass 21, count 0 2006.201.18:47:59.54#ibcon#flushed, iclass 21, count 0 2006.201.18:47:59.54#ibcon#about to write, iclass 21, count 0 2006.201.18:47:59.54#ibcon#wrote, iclass 21, count 0 2006.201.18:47:59.54#ibcon#about to read 3, iclass 21, count 0 2006.201.18:47:59.56#ibcon#read 3, iclass 21, count 0 2006.201.18:47:59.56#ibcon#about to read 4, iclass 21, count 0 2006.201.18:47:59.56#ibcon#read 4, iclass 21, count 0 2006.201.18:47:59.56#ibcon#about to read 5, iclass 21, count 0 2006.201.18:47:59.56#ibcon#read 5, iclass 21, count 0 2006.201.18:47:59.56#ibcon#about to read 6, iclass 21, count 0 2006.201.18:47:59.56#ibcon#read 6, iclass 21, count 0 2006.201.18:47:59.56#ibcon#end of sib2, iclass 21, count 0 2006.201.18:47:59.56#ibcon#*mode == 0, iclass 21, count 0 2006.201.18:47:59.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.18:47:59.56#ibcon#[25=USB\r\n] 2006.201.18:47:59.56#ibcon#*before write, iclass 21, count 0 2006.201.18:47:59.56#ibcon#enter sib2, iclass 21, count 0 2006.201.18:47:59.56#ibcon#flushed, iclass 21, count 0 2006.201.18:47:59.56#ibcon#about to write, iclass 21, count 0 2006.201.18:47:59.56#ibcon#wrote, iclass 21, count 0 2006.201.18:47:59.56#ibcon#about to read 3, iclass 21, count 0 2006.201.18:47:59.59#ibcon#read 3, iclass 21, count 0 2006.201.18:47:59.59#ibcon#about to read 4, iclass 21, count 0 2006.201.18:47:59.59#ibcon#read 4, iclass 21, count 0 2006.201.18:47:59.59#ibcon#about to read 5, iclass 21, count 0 2006.201.18:47:59.59#ibcon#read 5, iclass 21, count 0 2006.201.18:47:59.59#ibcon#about to read 6, iclass 21, count 0 2006.201.18:47:59.59#ibcon#read 6, iclass 21, count 0 2006.201.18:47:59.59#ibcon#end of sib2, iclass 21, count 0 2006.201.18:47:59.59#ibcon#*after write, iclass 21, count 0 2006.201.18:47:59.59#ibcon#*before return 0, iclass 21, count 0 2006.201.18:47:59.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:47:59.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:47:59.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.18:47:59.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.18:47:59.59$vck44/valo=6,814.99 2006.201.18:47:59.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.18:47:59.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.18:47:59.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:47:59.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:47:59.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:47:59.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:47:59.59#ibcon#enter wrdev, iclass 23, count 0 2006.201.18:47:59.59#ibcon#first serial, iclass 23, count 0 2006.201.18:47:59.59#ibcon#enter sib2, iclass 23, count 0 2006.201.18:47:59.59#ibcon#flushed, iclass 23, count 0 2006.201.18:47:59.59#ibcon#about to write, iclass 23, count 0 2006.201.18:47:59.59#ibcon#wrote, iclass 23, count 0 2006.201.18:47:59.59#ibcon#about to read 3, iclass 23, count 0 2006.201.18:47:59.61#ibcon#read 3, iclass 23, count 0 2006.201.18:47:59.61#ibcon#about to read 4, iclass 23, count 0 2006.201.18:47:59.61#ibcon#read 4, iclass 23, count 0 2006.201.18:47:59.61#ibcon#about to read 5, iclass 23, count 0 2006.201.18:47:59.61#ibcon#read 5, iclass 23, count 0 2006.201.18:47:59.61#ibcon#about to read 6, iclass 23, count 0 2006.201.18:47:59.61#ibcon#read 6, iclass 23, count 0 2006.201.18:47:59.61#ibcon#end of sib2, iclass 23, count 0 2006.201.18:47:59.61#ibcon#*mode == 0, iclass 23, count 0 2006.201.18:47:59.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.18:47:59.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:47:59.61#ibcon#*before write, iclass 23, count 0 2006.201.18:47:59.61#ibcon#enter sib2, iclass 23, count 0 2006.201.18:47:59.61#ibcon#flushed, iclass 23, count 0 2006.201.18:47:59.61#ibcon#about to write, iclass 23, count 0 2006.201.18:47:59.61#ibcon#wrote, iclass 23, count 0 2006.201.18:47:59.61#ibcon#about to read 3, iclass 23, count 0 2006.201.18:47:59.65#ibcon#read 3, iclass 23, count 0 2006.201.18:47:59.65#ibcon#about to read 4, iclass 23, count 0 2006.201.18:47:59.65#ibcon#read 4, iclass 23, count 0 2006.201.18:47:59.65#ibcon#about to read 5, iclass 23, count 0 2006.201.18:47:59.65#ibcon#read 5, iclass 23, count 0 2006.201.18:47:59.65#ibcon#about to read 6, iclass 23, count 0 2006.201.18:47:59.65#ibcon#read 6, iclass 23, count 0 2006.201.18:47:59.65#ibcon#end of sib2, iclass 23, count 0 2006.201.18:47:59.65#ibcon#*after write, iclass 23, count 0 2006.201.18:47:59.65#ibcon#*before return 0, iclass 23, count 0 2006.201.18:47:59.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:47:59.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:47:59.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.18:47:59.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.18:47:59.65$vck44/va=6,5 2006.201.18:47:59.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.18:47:59.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.18:47:59.65#ibcon#ireg 11 cls_cnt 2 2006.201.18:47:59.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:47:59.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:47:59.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:47:59.71#ibcon#enter wrdev, iclass 25, count 2 2006.201.18:47:59.71#ibcon#first serial, iclass 25, count 2 2006.201.18:47:59.71#ibcon#enter sib2, iclass 25, count 2 2006.201.18:47:59.71#ibcon#flushed, iclass 25, count 2 2006.201.18:47:59.71#ibcon#about to write, iclass 25, count 2 2006.201.18:47:59.71#ibcon#wrote, iclass 25, count 2 2006.201.18:47:59.71#ibcon#about to read 3, iclass 25, count 2 2006.201.18:47:59.73#ibcon#read 3, iclass 25, count 2 2006.201.18:47:59.73#ibcon#about to read 4, iclass 25, count 2 2006.201.18:47:59.73#ibcon#read 4, iclass 25, count 2 2006.201.18:47:59.73#ibcon#about to read 5, iclass 25, count 2 2006.201.18:47:59.73#ibcon#read 5, iclass 25, count 2 2006.201.18:47:59.73#ibcon#about to read 6, iclass 25, count 2 2006.201.18:47:59.73#ibcon#read 6, iclass 25, count 2 2006.201.18:47:59.73#ibcon#end of sib2, iclass 25, count 2 2006.201.18:47:59.73#ibcon#*mode == 0, iclass 25, count 2 2006.201.18:47:59.73#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.18:47:59.73#ibcon#[25=AT06-05\r\n] 2006.201.18:47:59.73#ibcon#*before write, iclass 25, count 2 2006.201.18:47:59.73#ibcon#enter sib2, iclass 25, count 2 2006.201.18:47:59.73#ibcon#flushed, iclass 25, count 2 2006.201.18:47:59.73#ibcon#about to write, iclass 25, count 2 2006.201.18:47:59.73#ibcon#wrote, iclass 25, count 2 2006.201.18:47:59.73#ibcon#about to read 3, iclass 25, count 2 2006.201.18:47:59.76#ibcon#read 3, iclass 25, count 2 2006.201.18:47:59.76#ibcon#about to read 4, iclass 25, count 2 2006.201.18:47:59.76#ibcon#read 4, iclass 25, count 2 2006.201.18:47:59.76#ibcon#about to read 5, iclass 25, count 2 2006.201.18:47:59.76#ibcon#read 5, iclass 25, count 2 2006.201.18:47:59.76#ibcon#about to read 6, iclass 25, count 2 2006.201.18:47:59.76#ibcon#read 6, iclass 25, count 2 2006.201.18:47:59.76#ibcon#end of sib2, iclass 25, count 2 2006.201.18:47:59.76#ibcon#*after write, iclass 25, count 2 2006.201.18:47:59.76#ibcon#*before return 0, iclass 25, count 2 2006.201.18:47:59.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:47:59.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:47:59.76#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.18:47:59.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:47:59.76#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:47:59.88#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:47:59.88#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:47:59.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.18:47:59.88#ibcon#first serial, iclass 25, count 0 2006.201.18:47:59.88#ibcon#enter sib2, iclass 25, count 0 2006.201.18:47:59.88#ibcon#flushed, iclass 25, count 0 2006.201.18:47:59.88#ibcon#about to write, iclass 25, count 0 2006.201.18:47:59.88#ibcon#wrote, iclass 25, count 0 2006.201.18:47:59.88#ibcon#about to read 3, iclass 25, count 0 2006.201.18:47:59.90#ibcon#read 3, iclass 25, count 0 2006.201.18:47:59.90#ibcon#about to read 4, iclass 25, count 0 2006.201.18:47:59.90#ibcon#read 4, iclass 25, count 0 2006.201.18:47:59.90#ibcon#about to read 5, iclass 25, count 0 2006.201.18:47:59.90#ibcon#read 5, iclass 25, count 0 2006.201.18:47:59.90#ibcon#about to read 6, iclass 25, count 0 2006.201.18:47:59.90#ibcon#read 6, iclass 25, count 0 2006.201.18:47:59.90#ibcon#end of sib2, iclass 25, count 0 2006.201.18:47:59.90#ibcon#*mode == 0, iclass 25, count 0 2006.201.18:47:59.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.18:47:59.90#ibcon#[25=USB\r\n] 2006.201.18:47:59.90#ibcon#*before write, iclass 25, count 0 2006.201.18:47:59.90#ibcon#enter sib2, iclass 25, count 0 2006.201.18:47:59.90#ibcon#flushed, iclass 25, count 0 2006.201.18:47:59.90#ibcon#about to write, iclass 25, count 0 2006.201.18:47:59.90#ibcon#wrote, iclass 25, count 0 2006.201.18:47:59.90#ibcon#about to read 3, iclass 25, count 0 2006.201.18:47:59.93#ibcon#read 3, iclass 25, count 0 2006.201.18:47:59.93#ibcon#about to read 4, iclass 25, count 0 2006.201.18:47:59.93#ibcon#read 4, iclass 25, count 0 2006.201.18:47:59.93#ibcon#about to read 5, iclass 25, count 0 2006.201.18:47:59.93#ibcon#read 5, iclass 25, count 0 2006.201.18:47:59.93#ibcon#about to read 6, iclass 25, count 0 2006.201.18:47:59.93#ibcon#read 6, iclass 25, count 0 2006.201.18:47:59.93#ibcon#end of sib2, iclass 25, count 0 2006.201.18:47:59.93#ibcon#*after write, iclass 25, count 0 2006.201.18:47:59.93#ibcon#*before return 0, iclass 25, count 0 2006.201.18:47:59.93#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:47:59.93#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:47:59.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.18:47:59.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.18:47:59.93$vck44/valo=7,864.99 2006.201.18:47:59.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.18:47:59.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.18:47:59.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:47:59.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:47:59.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:47:59.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:47:59.93#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:47:59.93#ibcon#first serial, iclass 27, count 0 2006.201.18:47:59.93#ibcon#enter sib2, iclass 27, count 0 2006.201.18:47:59.93#ibcon#flushed, iclass 27, count 0 2006.201.18:47:59.93#ibcon#about to write, iclass 27, count 0 2006.201.18:47:59.93#ibcon#wrote, iclass 27, count 0 2006.201.18:47:59.93#ibcon#about to read 3, iclass 27, count 0 2006.201.18:47:59.95#ibcon#read 3, iclass 27, count 0 2006.201.18:47:59.95#ibcon#about to read 4, iclass 27, count 0 2006.201.18:47:59.95#ibcon#read 4, iclass 27, count 0 2006.201.18:47:59.95#ibcon#about to read 5, iclass 27, count 0 2006.201.18:47:59.95#ibcon#read 5, iclass 27, count 0 2006.201.18:47:59.95#ibcon#about to read 6, iclass 27, count 0 2006.201.18:47:59.95#ibcon#read 6, iclass 27, count 0 2006.201.18:47:59.95#ibcon#end of sib2, iclass 27, count 0 2006.201.18:47:59.95#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:47:59.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:47:59.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:47:59.95#ibcon#*before write, iclass 27, count 0 2006.201.18:47:59.95#ibcon#enter sib2, iclass 27, count 0 2006.201.18:47:59.95#ibcon#flushed, iclass 27, count 0 2006.201.18:47:59.95#ibcon#about to write, iclass 27, count 0 2006.201.18:47:59.95#ibcon#wrote, iclass 27, count 0 2006.201.18:47:59.95#ibcon#about to read 3, iclass 27, count 0 2006.201.18:47:59.99#ibcon#read 3, iclass 27, count 0 2006.201.18:47:59.99#ibcon#about to read 4, iclass 27, count 0 2006.201.18:47:59.99#ibcon#read 4, iclass 27, count 0 2006.201.18:47:59.99#ibcon#about to read 5, iclass 27, count 0 2006.201.18:47:59.99#ibcon#read 5, iclass 27, count 0 2006.201.18:47:59.99#ibcon#about to read 6, iclass 27, count 0 2006.201.18:47:59.99#ibcon#read 6, iclass 27, count 0 2006.201.18:47:59.99#ibcon#end of sib2, iclass 27, count 0 2006.201.18:47:59.99#ibcon#*after write, iclass 27, count 0 2006.201.18:47:59.99#ibcon#*before return 0, iclass 27, count 0 2006.201.18:47:59.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:47:59.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:47:59.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:47:59.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:47:59.99$vck44/va=7,5 2006.201.18:47:59.99#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.18:47:59.99#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.18:47:59.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:47:59.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:00.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:00.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:00.05#ibcon#enter wrdev, iclass 29, count 2 2006.201.18:48:00.05#ibcon#first serial, iclass 29, count 2 2006.201.18:48:00.05#ibcon#enter sib2, iclass 29, count 2 2006.201.18:48:00.05#ibcon#flushed, iclass 29, count 2 2006.201.18:48:00.05#ibcon#about to write, iclass 29, count 2 2006.201.18:48:00.05#ibcon#wrote, iclass 29, count 2 2006.201.18:48:00.05#ibcon#about to read 3, iclass 29, count 2 2006.201.18:48:00.07#ibcon#read 3, iclass 29, count 2 2006.201.18:48:00.07#ibcon#about to read 4, iclass 29, count 2 2006.201.18:48:00.07#ibcon#read 4, iclass 29, count 2 2006.201.18:48:00.07#ibcon#about to read 5, iclass 29, count 2 2006.201.18:48:00.07#ibcon#read 5, iclass 29, count 2 2006.201.18:48:00.07#ibcon#about to read 6, iclass 29, count 2 2006.201.18:48:00.07#ibcon#read 6, iclass 29, count 2 2006.201.18:48:00.07#ibcon#end of sib2, iclass 29, count 2 2006.201.18:48:00.07#ibcon#*mode == 0, iclass 29, count 2 2006.201.18:48:00.07#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.18:48:00.07#ibcon#[25=AT07-05\r\n] 2006.201.18:48:00.07#ibcon#*before write, iclass 29, count 2 2006.201.18:48:00.07#ibcon#enter sib2, iclass 29, count 2 2006.201.18:48:00.07#ibcon#flushed, iclass 29, count 2 2006.201.18:48:00.07#ibcon#about to write, iclass 29, count 2 2006.201.18:48:00.07#ibcon#wrote, iclass 29, count 2 2006.201.18:48:00.07#ibcon#about to read 3, iclass 29, count 2 2006.201.18:48:00.10#ibcon#read 3, iclass 29, count 2 2006.201.18:48:00.10#ibcon#about to read 4, iclass 29, count 2 2006.201.18:48:00.10#ibcon#read 4, iclass 29, count 2 2006.201.18:48:00.10#ibcon#about to read 5, iclass 29, count 2 2006.201.18:48:00.10#ibcon#read 5, iclass 29, count 2 2006.201.18:48:00.10#ibcon#about to read 6, iclass 29, count 2 2006.201.18:48:00.10#ibcon#read 6, iclass 29, count 2 2006.201.18:48:00.10#ibcon#end of sib2, iclass 29, count 2 2006.201.18:48:00.10#ibcon#*after write, iclass 29, count 2 2006.201.18:48:00.10#ibcon#*before return 0, iclass 29, count 2 2006.201.18:48:00.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:00.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:00.10#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.18:48:00.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:00.10#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:00.22#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:00.22#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:00.22#ibcon#enter wrdev, iclass 29, count 0 2006.201.18:48:00.22#ibcon#first serial, iclass 29, count 0 2006.201.18:48:00.22#ibcon#enter sib2, iclass 29, count 0 2006.201.18:48:00.22#ibcon#flushed, iclass 29, count 0 2006.201.18:48:00.22#ibcon#about to write, iclass 29, count 0 2006.201.18:48:00.22#ibcon#wrote, iclass 29, count 0 2006.201.18:48:00.22#ibcon#about to read 3, iclass 29, count 0 2006.201.18:48:00.24#ibcon#read 3, iclass 29, count 0 2006.201.18:48:00.24#ibcon#about to read 4, iclass 29, count 0 2006.201.18:48:00.24#ibcon#read 4, iclass 29, count 0 2006.201.18:48:00.24#ibcon#about to read 5, iclass 29, count 0 2006.201.18:48:00.24#ibcon#read 5, iclass 29, count 0 2006.201.18:48:00.24#ibcon#about to read 6, iclass 29, count 0 2006.201.18:48:00.24#ibcon#read 6, iclass 29, count 0 2006.201.18:48:00.24#ibcon#end of sib2, iclass 29, count 0 2006.201.18:48:00.24#ibcon#*mode == 0, iclass 29, count 0 2006.201.18:48:00.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.18:48:00.24#ibcon#[25=USB\r\n] 2006.201.18:48:00.24#ibcon#*before write, iclass 29, count 0 2006.201.18:48:00.24#ibcon#enter sib2, iclass 29, count 0 2006.201.18:48:00.24#ibcon#flushed, iclass 29, count 0 2006.201.18:48:00.24#ibcon#about to write, iclass 29, count 0 2006.201.18:48:00.24#ibcon#wrote, iclass 29, count 0 2006.201.18:48:00.24#ibcon#about to read 3, iclass 29, count 0 2006.201.18:48:00.27#ibcon#read 3, iclass 29, count 0 2006.201.18:48:00.27#ibcon#about to read 4, iclass 29, count 0 2006.201.18:48:00.27#ibcon#read 4, iclass 29, count 0 2006.201.18:48:00.27#ibcon#about to read 5, iclass 29, count 0 2006.201.18:48:00.27#ibcon#read 5, iclass 29, count 0 2006.201.18:48:00.27#ibcon#about to read 6, iclass 29, count 0 2006.201.18:48:00.27#ibcon#read 6, iclass 29, count 0 2006.201.18:48:00.27#ibcon#end of sib2, iclass 29, count 0 2006.201.18:48:00.27#ibcon#*after write, iclass 29, count 0 2006.201.18:48:00.27#ibcon#*before return 0, iclass 29, count 0 2006.201.18:48:00.27#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:00.27#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:00.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.18:48:00.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.18:48:00.27$vck44/valo=8,884.99 2006.201.18:48:00.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.18:48:00.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.18:48:00.27#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:00.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:00.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:00.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:00.27#ibcon#enter wrdev, iclass 31, count 0 2006.201.18:48:00.27#ibcon#first serial, iclass 31, count 0 2006.201.18:48:00.27#ibcon#enter sib2, iclass 31, count 0 2006.201.18:48:00.27#ibcon#flushed, iclass 31, count 0 2006.201.18:48:00.27#ibcon#about to write, iclass 31, count 0 2006.201.18:48:00.27#ibcon#wrote, iclass 31, count 0 2006.201.18:48:00.27#ibcon#about to read 3, iclass 31, count 0 2006.201.18:48:00.29#ibcon#read 3, iclass 31, count 0 2006.201.18:48:00.29#ibcon#about to read 4, iclass 31, count 0 2006.201.18:48:00.29#ibcon#read 4, iclass 31, count 0 2006.201.18:48:00.29#ibcon#about to read 5, iclass 31, count 0 2006.201.18:48:00.29#ibcon#read 5, iclass 31, count 0 2006.201.18:48:00.29#ibcon#about to read 6, iclass 31, count 0 2006.201.18:48:00.29#ibcon#read 6, iclass 31, count 0 2006.201.18:48:00.29#ibcon#end of sib2, iclass 31, count 0 2006.201.18:48:00.29#ibcon#*mode == 0, iclass 31, count 0 2006.201.18:48:00.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.18:48:00.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:48:00.29#ibcon#*before write, iclass 31, count 0 2006.201.18:48:00.29#ibcon#enter sib2, iclass 31, count 0 2006.201.18:48:00.29#ibcon#flushed, iclass 31, count 0 2006.201.18:48:00.29#ibcon#about to write, iclass 31, count 0 2006.201.18:48:00.29#ibcon#wrote, iclass 31, count 0 2006.201.18:48:00.29#ibcon#about to read 3, iclass 31, count 0 2006.201.18:48:00.33#ibcon#read 3, iclass 31, count 0 2006.201.18:48:00.33#ibcon#about to read 4, iclass 31, count 0 2006.201.18:48:00.33#ibcon#read 4, iclass 31, count 0 2006.201.18:48:00.33#ibcon#about to read 5, iclass 31, count 0 2006.201.18:48:00.33#ibcon#read 5, iclass 31, count 0 2006.201.18:48:00.33#ibcon#about to read 6, iclass 31, count 0 2006.201.18:48:00.33#ibcon#read 6, iclass 31, count 0 2006.201.18:48:00.33#ibcon#end of sib2, iclass 31, count 0 2006.201.18:48:00.33#ibcon#*after write, iclass 31, count 0 2006.201.18:48:00.33#ibcon#*before return 0, iclass 31, count 0 2006.201.18:48:00.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:00.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:00.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.18:48:00.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.18:48:00.33$vck44/va=8,4 2006.201.18:48:00.33#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.18:48:00.33#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.18:48:00.33#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:00.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:48:00.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:48:00.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:48:00.39#ibcon#enter wrdev, iclass 33, count 2 2006.201.18:48:00.39#ibcon#first serial, iclass 33, count 2 2006.201.18:48:00.39#ibcon#enter sib2, iclass 33, count 2 2006.201.18:48:00.39#ibcon#flushed, iclass 33, count 2 2006.201.18:48:00.39#ibcon#about to write, iclass 33, count 2 2006.201.18:48:00.39#ibcon#wrote, iclass 33, count 2 2006.201.18:48:00.39#ibcon#about to read 3, iclass 33, count 2 2006.201.18:48:00.41#ibcon#read 3, iclass 33, count 2 2006.201.18:48:00.41#ibcon#about to read 4, iclass 33, count 2 2006.201.18:48:00.41#ibcon#read 4, iclass 33, count 2 2006.201.18:48:00.41#ibcon#about to read 5, iclass 33, count 2 2006.201.18:48:00.41#ibcon#read 5, iclass 33, count 2 2006.201.18:48:00.41#ibcon#about to read 6, iclass 33, count 2 2006.201.18:48:00.41#ibcon#read 6, iclass 33, count 2 2006.201.18:48:00.41#ibcon#end of sib2, iclass 33, count 2 2006.201.18:48:00.41#ibcon#*mode == 0, iclass 33, count 2 2006.201.18:48:00.41#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.18:48:00.41#ibcon#[25=AT08-04\r\n] 2006.201.18:48:00.41#ibcon#*before write, iclass 33, count 2 2006.201.18:48:00.41#ibcon#enter sib2, iclass 33, count 2 2006.201.18:48:00.41#ibcon#flushed, iclass 33, count 2 2006.201.18:48:00.41#ibcon#about to write, iclass 33, count 2 2006.201.18:48:00.41#ibcon#wrote, iclass 33, count 2 2006.201.18:48:00.41#ibcon#about to read 3, iclass 33, count 2 2006.201.18:48:00.44#ibcon#read 3, iclass 33, count 2 2006.201.18:48:00.44#ibcon#about to read 4, iclass 33, count 2 2006.201.18:48:00.44#ibcon#read 4, iclass 33, count 2 2006.201.18:48:00.44#ibcon#about to read 5, iclass 33, count 2 2006.201.18:48:00.44#ibcon#read 5, iclass 33, count 2 2006.201.18:48:00.44#ibcon#about to read 6, iclass 33, count 2 2006.201.18:48:00.44#ibcon#read 6, iclass 33, count 2 2006.201.18:48:00.44#ibcon#end of sib2, iclass 33, count 2 2006.201.18:48:00.44#ibcon#*after write, iclass 33, count 2 2006.201.18:48:00.44#ibcon#*before return 0, iclass 33, count 2 2006.201.18:48:00.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:48:00.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.18:48:00.44#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.18:48:00.44#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:00.44#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:48:00.56#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:48:00.56#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:48:00.56#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:48:00.56#ibcon#first serial, iclass 33, count 0 2006.201.18:48:00.56#ibcon#enter sib2, iclass 33, count 0 2006.201.18:48:00.56#ibcon#flushed, iclass 33, count 0 2006.201.18:48:00.56#ibcon#about to write, iclass 33, count 0 2006.201.18:48:00.56#ibcon#wrote, iclass 33, count 0 2006.201.18:48:00.56#ibcon#about to read 3, iclass 33, count 0 2006.201.18:48:00.58#ibcon#read 3, iclass 33, count 0 2006.201.18:48:00.58#ibcon#about to read 4, iclass 33, count 0 2006.201.18:48:00.58#ibcon#read 4, iclass 33, count 0 2006.201.18:48:00.58#ibcon#about to read 5, iclass 33, count 0 2006.201.18:48:00.58#ibcon#read 5, iclass 33, count 0 2006.201.18:48:00.58#ibcon#about to read 6, iclass 33, count 0 2006.201.18:48:00.58#ibcon#read 6, iclass 33, count 0 2006.201.18:48:00.58#ibcon#end of sib2, iclass 33, count 0 2006.201.18:48:00.58#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:48:00.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:48:00.58#ibcon#[25=USB\r\n] 2006.201.18:48:00.58#ibcon#*before write, iclass 33, count 0 2006.201.18:48:00.58#ibcon#enter sib2, iclass 33, count 0 2006.201.18:48:00.58#ibcon#flushed, iclass 33, count 0 2006.201.18:48:00.58#ibcon#about to write, iclass 33, count 0 2006.201.18:48:00.58#ibcon#wrote, iclass 33, count 0 2006.201.18:48:00.58#ibcon#about to read 3, iclass 33, count 0 2006.201.18:48:00.61#ibcon#read 3, iclass 33, count 0 2006.201.18:48:00.61#ibcon#about to read 4, iclass 33, count 0 2006.201.18:48:00.61#ibcon#read 4, iclass 33, count 0 2006.201.18:48:00.61#ibcon#about to read 5, iclass 33, count 0 2006.201.18:48:00.61#ibcon#read 5, iclass 33, count 0 2006.201.18:48:00.61#ibcon#about to read 6, iclass 33, count 0 2006.201.18:48:00.61#ibcon#read 6, iclass 33, count 0 2006.201.18:48:00.61#ibcon#end of sib2, iclass 33, count 0 2006.201.18:48:00.61#ibcon#*after write, iclass 33, count 0 2006.201.18:48:00.61#ibcon#*before return 0, iclass 33, count 0 2006.201.18:48:00.61#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:48:00.61#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.18:48:00.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:48:00.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:48:00.61$vck44/vblo=1,629.99 2006.201.18:48:00.61#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.18:48:00.61#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.18:48:00.61#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:00.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:48:00.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:48:00.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:48:00.61#ibcon#enter wrdev, iclass 35, count 0 2006.201.18:48:00.61#ibcon#first serial, iclass 35, count 0 2006.201.18:48:00.61#ibcon#enter sib2, iclass 35, count 0 2006.201.18:48:00.61#ibcon#flushed, iclass 35, count 0 2006.201.18:48:00.61#ibcon#about to write, iclass 35, count 0 2006.201.18:48:00.61#ibcon#wrote, iclass 35, count 0 2006.201.18:48:00.61#ibcon#about to read 3, iclass 35, count 0 2006.201.18:48:00.63#ibcon#read 3, iclass 35, count 0 2006.201.18:48:00.63#ibcon#about to read 4, iclass 35, count 0 2006.201.18:48:00.63#ibcon#read 4, iclass 35, count 0 2006.201.18:48:00.63#ibcon#about to read 5, iclass 35, count 0 2006.201.18:48:00.63#ibcon#read 5, iclass 35, count 0 2006.201.18:48:00.63#ibcon#about to read 6, iclass 35, count 0 2006.201.18:48:00.63#ibcon#read 6, iclass 35, count 0 2006.201.18:48:00.63#ibcon#end of sib2, iclass 35, count 0 2006.201.18:48:00.63#ibcon#*mode == 0, iclass 35, count 0 2006.201.18:48:00.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.18:48:00.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:48:00.63#ibcon#*before write, iclass 35, count 0 2006.201.18:48:00.63#ibcon#enter sib2, iclass 35, count 0 2006.201.18:48:00.63#ibcon#flushed, iclass 35, count 0 2006.201.18:48:00.63#ibcon#about to write, iclass 35, count 0 2006.201.18:48:00.63#ibcon#wrote, iclass 35, count 0 2006.201.18:48:00.63#ibcon#about to read 3, iclass 35, count 0 2006.201.18:48:00.67#ibcon#read 3, iclass 35, count 0 2006.201.18:48:00.67#ibcon#about to read 4, iclass 35, count 0 2006.201.18:48:00.67#ibcon#read 4, iclass 35, count 0 2006.201.18:48:00.67#ibcon#about to read 5, iclass 35, count 0 2006.201.18:48:00.67#ibcon#read 5, iclass 35, count 0 2006.201.18:48:00.67#ibcon#about to read 6, iclass 35, count 0 2006.201.18:48:00.67#ibcon#read 6, iclass 35, count 0 2006.201.18:48:00.67#ibcon#end of sib2, iclass 35, count 0 2006.201.18:48:00.67#ibcon#*after write, iclass 35, count 0 2006.201.18:48:00.67#ibcon#*before return 0, iclass 35, count 0 2006.201.18:48:00.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:48:00.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.18:48:00.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.18:48:00.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.18:48:00.67$vck44/vb=1,4 2006.201.18:48:00.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.18:48:00.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.18:48:00.67#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:00.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:48:00.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:48:00.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:48:00.67#ibcon#enter wrdev, iclass 37, count 2 2006.201.18:48:00.67#ibcon#first serial, iclass 37, count 2 2006.201.18:48:00.67#ibcon#enter sib2, iclass 37, count 2 2006.201.18:48:00.67#ibcon#flushed, iclass 37, count 2 2006.201.18:48:00.67#ibcon#about to write, iclass 37, count 2 2006.201.18:48:00.67#ibcon#wrote, iclass 37, count 2 2006.201.18:48:00.67#ibcon#about to read 3, iclass 37, count 2 2006.201.18:48:00.69#ibcon#read 3, iclass 37, count 2 2006.201.18:48:00.69#ibcon#about to read 4, iclass 37, count 2 2006.201.18:48:00.69#ibcon#read 4, iclass 37, count 2 2006.201.18:48:00.69#ibcon#about to read 5, iclass 37, count 2 2006.201.18:48:00.69#ibcon#read 5, iclass 37, count 2 2006.201.18:48:00.69#ibcon#about to read 6, iclass 37, count 2 2006.201.18:48:00.69#ibcon#read 6, iclass 37, count 2 2006.201.18:48:00.69#ibcon#end of sib2, iclass 37, count 2 2006.201.18:48:00.69#ibcon#*mode == 0, iclass 37, count 2 2006.201.18:48:00.69#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.18:48:00.69#ibcon#[27=AT01-04\r\n] 2006.201.18:48:00.69#ibcon#*before write, iclass 37, count 2 2006.201.18:48:00.69#ibcon#enter sib2, iclass 37, count 2 2006.201.18:48:00.69#ibcon#flushed, iclass 37, count 2 2006.201.18:48:00.69#ibcon#about to write, iclass 37, count 2 2006.201.18:48:00.69#ibcon#wrote, iclass 37, count 2 2006.201.18:48:00.69#ibcon#about to read 3, iclass 37, count 2 2006.201.18:48:00.72#ibcon#read 3, iclass 37, count 2 2006.201.18:48:00.72#ibcon#about to read 4, iclass 37, count 2 2006.201.18:48:00.72#ibcon#read 4, iclass 37, count 2 2006.201.18:48:00.72#ibcon#about to read 5, iclass 37, count 2 2006.201.18:48:00.72#ibcon#read 5, iclass 37, count 2 2006.201.18:48:00.72#ibcon#about to read 6, iclass 37, count 2 2006.201.18:48:00.72#ibcon#read 6, iclass 37, count 2 2006.201.18:48:00.72#ibcon#end of sib2, iclass 37, count 2 2006.201.18:48:00.72#ibcon#*after write, iclass 37, count 2 2006.201.18:48:00.72#ibcon#*before return 0, iclass 37, count 2 2006.201.18:48:00.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:48:00.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:48:00.72#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.18:48:00.72#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:00.72#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:48:00.84#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:48:00.84#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:48:00.84#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:48:00.84#ibcon#first serial, iclass 37, count 0 2006.201.18:48:00.84#ibcon#enter sib2, iclass 37, count 0 2006.201.18:48:00.84#ibcon#flushed, iclass 37, count 0 2006.201.18:48:00.84#ibcon#about to write, iclass 37, count 0 2006.201.18:48:00.84#ibcon#wrote, iclass 37, count 0 2006.201.18:48:00.84#ibcon#about to read 3, iclass 37, count 0 2006.201.18:48:00.86#ibcon#read 3, iclass 37, count 0 2006.201.18:48:00.86#ibcon#about to read 4, iclass 37, count 0 2006.201.18:48:00.86#ibcon#read 4, iclass 37, count 0 2006.201.18:48:00.86#ibcon#about to read 5, iclass 37, count 0 2006.201.18:48:00.86#ibcon#read 5, iclass 37, count 0 2006.201.18:48:00.86#ibcon#about to read 6, iclass 37, count 0 2006.201.18:48:00.86#ibcon#read 6, iclass 37, count 0 2006.201.18:48:00.86#ibcon#end of sib2, iclass 37, count 0 2006.201.18:48:00.86#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:48:00.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:48:00.86#ibcon#[27=USB\r\n] 2006.201.18:48:00.86#ibcon#*before write, iclass 37, count 0 2006.201.18:48:00.86#ibcon#enter sib2, iclass 37, count 0 2006.201.18:48:00.86#ibcon#flushed, iclass 37, count 0 2006.201.18:48:00.86#ibcon#about to write, iclass 37, count 0 2006.201.18:48:00.86#ibcon#wrote, iclass 37, count 0 2006.201.18:48:00.86#ibcon#about to read 3, iclass 37, count 0 2006.201.18:48:00.89#ibcon#read 3, iclass 37, count 0 2006.201.18:48:00.89#ibcon#about to read 4, iclass 37, count 0 2006.201.18:48:00.89#ibcon#read 4, iclass 37, count 0 2006.201.18:48:00.89#ibcon#about to read 5, iclass 37, count 0 2006.201.18:48:00.89#ibcon#read 5, iclass 37, count 0 2006.201.18:48:00.89#ibcon#about to read 6, iclass 37, count 0 2006.201.18:48:00.89#ibcon#read 6, iclass 37, count 0 2006.201.18:48:00.89#ibcon#end of sib2, iclass 37, count 0 2006.201.18:48:00.89#ibcon#*after write, iclass 37, count 0 2006.201.18:48:00.89#ibcon#*before return 0, iclass 37, count 0 2006.201.18:48:00.89#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:48:00.89#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:48:00.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:48:00.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:48:00.89$vck44/vblo=2,634.99 2006.201.18:48:00.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.18:48:00.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.18:48:00.89#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:00.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:48:00.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:48:00.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:48:00.89#ibcon#enter wrdev, iclass 39, count 0 2006.201.18:48:00.89#ibcon#first serial, iclass 39, count 0 2006.201.18:48:00.89#ibcon#enter sib2, iclass 39, count 0 2006.201.18:48:00.89#ibcon#flushed, iclass 39, count 0 2006.201.18:48:00.89#ibcon#about to write, iclass 39, count 0 2006.201.18:48:00.89#ibcon#wrote, iclass 39, count 0 2006.201.18:48:00.89#ibcon#about to read 3, iclass 39, count 0 2006.201.18:48:00.91#ibcon#read 3, iclass 39, count 0 2006.201.18:48:00.91#ibcon#about to read 4, iclass 39, count 0 2006.201.18:48:00.91#ibcon#read 4, iclass 39, count 0 2006.201.18:48:00.91#ibcon#about to read 5, iclass 39, count 0 2006.201.18:48:00.91#ibcon#read 5, iclass 39, count 0 2006.201.18:48:00.91#ibcon#about to read 6, iclass 39, count 0 2006.201.18:48:00.91#ibcon#read 6, iclass 39, count 0 2006.201.18:48:00.91#ibcon#end of sib2, iclass 39, count 0 2006.201.18:48:00.91#ibcon#*mode == 0, iclass 39, count 0 2006.201.18:48:00.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.18:48:00.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:48:00.91#ibcon#*before write, iclass 39, count 0 2006.201.18:48:00.91#ibcon#enter sib2, iclass 39, count 0 2006.201.18:48:00.91#ibcon#flushed, iclass 39, count 0 2006.201.18:48:00.91#ibcon#about to write, iclass 39, count 0 2006.201.18:48:00.91#ibcon#wrote, iclass 39, count 0 2006.201.18:48:00.91#ibcon#about to read 3, iclass 39, count 0 2006.201.18:48:00.96#ibcon#read 3, iclass 39, count 0 2006.201.18:48:00.96#ibcon#about to read 4, iclass 39, count 0 2006.201.18:48:00.96#ibcon#read 4, iclass 39, count 0 2006.201.18:48:00.96#ibcon#about to read 5, iclass 39, count 0 2006.201.18:48:00.96#ibcon#read 5, iclass 39, count 0 2006.201.18:48:00.96#ibcon#about to read 6, iclass 39, count 0 2006.201.18:48:00.96#ibcon#read 6, iclass 39, count 0 2006.201.18:48:00.96#ibcon#end of sib2, iclass 39, count 0 2006.201.18:48:00.96#ibcon#*after write, iclass 39, count 0 2006.201.18:48:00.96#ibcon#*before return 0, iclass 39, count 0 2006.201.18:48:00.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:48:00.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.18:48:00.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.18:48:00.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.18:48:00.96$vck44/vb=2,5 2006.201.18:48:00.96#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.18:48:00.96#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.18:48:00.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:00.96#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:48:01.01#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:48:01.01#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:48:01.01#ibcon#enter wrdev, iclass 2, count 2 2006.201.18:48:01.01#ibcon#first serial, iclass 2, count 2 2006.201.18:48:01.01#ibcon#enter sib2, iclass 2, count 2 2006.201.18:48:01.01#ibcon#flushed, iclass 2, count 2 2006.201.18:48:01.01#ibcon#about to write, iclass 2, count 2 2006.201.18:48:01.01#ibcon#wrote, iclass 2, count 2 2006.201.18:48:01.01#ibcon#about to read 3, iclass 2, count 2 2006.201.18:48:01.03#ibcon#read 3, iclass 2, count 2 2006.201.18:48:01.03#ibcon#about to read 4, iclass 2, count 2 2006.201.18:48:01.03#ibcon#read 4, iclass 2, count 2 2006.201.18:48:01.03#ibcon#about to read 5, iclass 2, count 2 2006.201.18:48:01.03#ibcon#read 5, iclass 2, count 2 2006.201.18:48:01.03#ibcon#about to read 6, iclass 2, count 2 2006.201.18:48:01.03#ibcon#read 6, iclass 2, count 2 2006.201.18:48:01.03#ibcon#end of sib2, iclass 2, count 2 2006.201.18:48:01.03#ibcon#*mode == 0, iclass 2, count 2 2006.201.18:48:01.03#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.18:48:01.03#ibcon#[27=AT02-05\r\n] 2006.201.18:48:01.03#ibcon#*before write, iclass 2, count 2 2006.201.18:48:01.03#ibcon#enter sib2, iclass 2, count 2 2006.201.18:48:01.03#ibcon#flushed, iclass 2, count 2 2006.201.18:48:01.03#ibcon#about to write, iclass 2, count 2 2006.201.18:48:01.03#ibcon#wrote, iclass 2, count 2 2006.201.18:48:01.03#ibcon#about to read 3, iclass 2, count 2 2006.201.18:48:01.06#ibcon#read 3, iclass 2, count 2 2006.201.18:48:01.06#ibcon#about to read 4, iclass 2, count 2 2006.201.18:48:01.06#ibcon#read 4, iclass 2, count 2 2006.201.18:48:01.06#ibcon#about to read 5, iclass 2, count 2 2006.201.18:48:01.06#ibcon#read 5, iclass 2, count 2 2006.201.18:48:01.06#ibcon#about to read 6, iclass 2, count 2 2006.201.18:48:01.06#ibcon#read 6, iclass 2, count 2 2006.201.18:48:01.06#ibcon#end of sib2, iclass 2, count 2 2006.201.18:48:01.06#ibcon#*after write, iclass 2, count 2 2006.201.18:48:01.06#ibcon#*before return 0, iclass 2, count 2 2006.201.18:48:01.06#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:48:01.06#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.18:48:01.06#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.18:48:01.06#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:01.06#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:48:01.18#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:48:01.18#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:48:01.18#ibcon#enter wrdev, iclass 2, count 0 2006.201.18:48:01.18#ibcon#first serial, iclass 2, count 0 2006.201.18:48:01.18#ibcon#enter sib2, iclass 2, count 0 2006.201.18:48:01.18#ibcon#flushed, iclass 2, count 0 2006.201.18:48:01.18#ibcon#about to write, iclass 2, count 0 2006.201.18:48:01.18#ibcon#wrote, iclass 2, count 0 2006.201.18:48:01.18#ibcon#about to read 3, iclass 2, count 0 2006.201.18:48:01.20#ibcon#read 3, iclass 2, count 0 2006.201.18:48:01.20#ibcon#about to read 4, iclass 2, count 0 2006.201.18:48:01.20#ibcon#read 4, iclass 2, count 0 2006.201.18:48:01.20#ibcon#about to read 5, iclass 2, count 0 2006.201.18:48:01.20#ibcon#read 5, iclass 2, count 0 2006.201.18:48:01.20#ibcon#about to read 6, iclass 2, count 0 2006.201.18:48:01.20#ibcon#read 6, iclass 2, count 0 2006.201.18:48:01.20#ibcon#end of sib2, iclass 2, count 0 2006.201.18:48:01.20#ibcon#*mode == 0, iclass 2, count 0 2006.201.18:48:01.20#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.18:48:01.20#ibcon#[27=USB\r\n] 2006.201.18:48:01.20#ibcon#*before write, iclass 2, count 0 2006.201.18:48:01.20#ibcon#enter sib2, iclass 2, count 0 2006.201.18:48:01.20#ibcon#flushed, iclass 2, count 0 2006.201.18:48:01.20#ibcon#about to write, iclass 2, count 0 2006.201.18:48:01.20#ibcon#wrote, iclass 2, count 0 2006.201.18:48:01.20#ibcon#about to read 3, iclass 2, count 0 2006.201.18:48:01.23#ibcon#read 3, iclass 2, count 0 2006.201.18:48:01.23#ibcon#about to read 4, iclass 2, count 0 2006.201.18:48:01.23#ibcon#read 4, iclass 2, count 0 2006.201.18:48:01.23#ibcon#about to read 5, iclass 2, count 0 2006.201.18:48:01.23#ibcon#read 5, iclass 2, count 0 2006.201.18:48:01.23#ibcon#about to read 6, iclass 2, count 0 2006.201.18:48:01.23#ibcon#read 6, iclass 2, count 0 2006.201.18:48:01.23#ibcon#end of sib2, iclass 2, count 0 2006.201.18:48:01.23#ibcon#*after write, iclass 2, count 0 2006.201.18:48:01.23#ibcon#*before return 0, iclass 2, count 0 2006.201.18:48:01.23#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:48:01.23#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.18:48:01.23#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.18:48:01.23#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.18:48:01.23$vck44/vblo=3,649.99 2006.201.18:48:01.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.18:48:01.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.18:48:01.23#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:01.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:48:01.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:48:01.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:48:01.23#ibcon#enter wrdev, iclass 5, count 0 2006.201.18:48:01.23#ibcon#first serial, iclass 5, count 0 2006.201.18:48:01.23#ibcon#enter sib2, iclass 5, count 0 2006.201.18:48:01.23#ibcon#flushed, iclass 5, count 0 2006.201.18:48:01.23#ibcon#about to write, iclass 5, count 0 2006.201.18:48:01.23#ibcon#wrote, iclass 5, count 0 2006.201.18:48:01.23#ibcon#about to read 3, iclass 5, count 0 2006.201.18:48:01.25#ibcon#read 3, iclass 5, count 0 2006.201.18:48:01.25#ibcon#about to read 4, iclass 5, count 0 2006.201.18:48:01.25#ibcon#read 4, iclass 5, count 0 2006.201.18:48:01.25#ibcon#about to read 5, iclass 5, count 0 2006.201.18:48:01.25#ibcon#read 5, iclass 5, count 0 2006.201.18:48:01.25#ibcon#about to read 6, iclass 5, count 0 2006.201.18:48:01.25#ibcon#read 6, iclass 5, count 0 2006.201.18:48:01.25#ibcon#end of sib2, iclass 5, count 0 2006.201.18:48:01.25#ibcon#*mode == 0, iclass 5, count 0 2006.201.18:48:01.25#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.18:48:01.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:48:01.25#ibcon#*before write, iclass 5, count 0 2006.201.18:48:01.25#ibcon#enter sib2, iclass 5, count 0 2006.201.18:48:01.25#ibcon#flushed, iclass 5, count 0 2006.201.18:48:01.25#ibcon#about to write, iclass 5, count 0 2006.201.18:48:01.25#ibcon#wrote, iclass 5, count 0 2006.201.18:48:01.25#ibcon#about to read 3, iclass 5, count 0 2006.201.18:48:01.29#ibcon#read 3, iclass 5, count 0 2006.201.18:48:01.29#ibcon#about to read 4, iclass 5, count 0 2006.201.18:48:01.29#ibcon#read 4, iclass 5, count 0 2006.201.18:48:01.29#ibcon#about to read 5, iclass 5, count 0 2006.201.18:48:01.29#ibcon#read 5, iclass 5, count 0 2006.201.18:48:01.29#ibcon#about to read 6, iclass 5, count 0 2006.201.18:48:01.29#ibcon#read 6, iclass 5, count 0 2006.201.18:48:01.29#ibcon#end of sib2, iclass 5, count 0 2006.201.18:48:01.29#ibcon#*after write, iclass 5, count 0 2006.201.18:48:01.29#ibcon#*before return 0, iclass 5, count 0 2006.201.18:48:01.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:48:01.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.18:48:01.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.18:48:01.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.18:48:01.29$vck44/vb=3,4 2006.201.18:48:01.29#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.18:48:01.29#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.18:48:01.29#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:01.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:48:01.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:48:01.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:48:01.35#ibcon#enter wrdev, iclass 7, count 2 2006.201.18:48:01.35#ibcon#first serial, iclass 7, count 2 2006.201.18:48:01.35#ibcon#enter sib2, iclass 7, count 2 2006.201.18:48:01.35#ibcon#flushed, iclass 7, count 2 2006.201.18:48:01.35#ibcon#about to write, iclass 7, count 2 2006.201.18:48:01.35#ibcon#wrote, iclass 7, count 2 2006.201.18:48:01.35#ibcon#about to read 3, iclass 7, count 2 2006.201.18:48:01.37#ibcon#read 3, iclass 7, count 2 2006.201.18:48:01.37#ibcon#about to read 4, iclass 7, count 2 2006.201.18:48:01.37#ibcon#read 4, iclass 7, count 2 2006.201.18:48:01.37#ibcon#about to read 5, iclass 7, count 2 2006.201.18:48:01.37#ibcon#read 5, iclass 7, count 2 2006.201.18:48:01.37#ibcon#about to read 6, iclass 7, count 2 2006.201.18:48:01.37#ibcon#read 6, iclass 7, count 2 2006.201.18:48:01.37#ibcon#end of sib2, iclass 7, count 2 2006.201.18:48:01.37#ibcon#*mode == 0, iclass 7, count 2 2006.201.18:48:01.37#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.18:48:01.37#ibcon#[27=AT03-04\r\n] 2006.201.18:48:01.37#ibcon#*before write, iclass 7, count 2 2006.201.18:48:01.37#ibcon#enter sib2, iclass 7, count 2 2006.201.18:48:01.37#ibcon#flushed, iclass 7, count 2 2006.201.18:48:01.37#ibcon#about to write, iclass 7, count 2 2006.201.18:48:01.37#ibcon#wrote, iclass 7, count 2 2006.201.18:48:01.37#ibcon#about to read 3, iclass 7, count 2 2006.201.18:48:01.40#ibcon#read 3, iclass 7, count 2 2006.201.18:48:01.40#ibcon#about to read 4, iclass 7, count 2 2006.201.18:48:01.40#ibcon#read 4, iclass 7, count 2 2006.201.18:48:01.40#ibcon#about to read 5, iclass 7, count 2 2006.201.18:48:01.40#ibcon#read 5, iclass 7, count 2 2006.201.18:48:01.40#ibcon#about to read 6, iclass 7, count 2 2006.201.18:48:01.40#ibcon#read 6, iclass 7, count 2 2006.201.18:48:01.40#ibcon#end of sib2, iclass 7, count 2 2006.201.18:48:01.40#ibcon#*after write, iclass 7, count 2 2006.201.18:48:01.40#ibcon#*before return 0, iclass 7, count 2 2006.201.18:48:01.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:48:01.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.18:48:01.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.18:48:01.40#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:01.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:48:01.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:48:01.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:48:01.52#ibcon#enter wrdev, iclass 7, count 0 2006.201.18:48:01.52#ibcon#first serial, iclass 7, count 0 2006.201.18:48:01.52#ibcon#enter sib2, iclass 7, count 0 2006.201.18:48:01.52#ibcon#flushed, iclass 7, count 0 2006.201.18:48:01.52#ibcon#about to write, iclass 7, count 0 2006.201.18:48:01.52#ibcon#wrote, iclass 7, count 0 2006.201.18:48:01.52#ibcon#about to read 3, iclass 7, count 0 2006.201.18:48:01.54#ibcon#read 3, iclass 7, count 0 2006.201.18:48:01.54#ibcon#about to read 4, iclass 7, count 0 2006.201.18:48:01.54#ibcon#read 4, iclass 7, count 0 2006.201.18:48:01.54#ibcon#about to read 5, iclass 7, count 0 2006.201.18:48:01.54#ibcon#read 5, iclass 7, count 0 2006.201.18:48:01.54#ibcon#about to read 6, iclass 7, count 0 2006.201.18:48:01.54#ibcon#read 6, iclass 7, count 0 2006.201.18:48:01.54#ibcon#end of sib2, iclass 7, count 0 2006.201.18:48:01.54#ibcon#*mode == 0, iclass 7, count 0 2006.201.18:48:01.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.18:48:01.54#ibcon#[27=USB\r\n] 2006.201.18:48:01.54#ibcon#*before write, iclass 7, count 0 2006.201.18:48:01.54#ibcon#enter sib2, iclass 7, count 0 2006.201.18:48:01.54#ibcon#flushed, iclass 7, count 0 2006.201.18:48:01.54#ibcon#about to write, iclass 7, count 0 2006.201.18:48:01.54#ibcon#wrote, iclass 7, count 0 2006.201.18:48:01.54#ibcon#about to read 3, iclass 7, count 0 2006.201.18:48:01.57#ibcon#read 3, iclass 7, count 0 2006.201.18:48:01.57#ibcon#about to read 4, iclass 7, count 0 2006.201.18:48:01.57#ibcon#read 4, iclass 7, count 0 2006.201.18:48:01.57#ibcon#about to read 5, iclass 7, count 0 2006.201.18:48:01.57#ibcon#read 5, iclass 7, count 0 2006.201.18:48:01.57#ibcon#about to read 6, iclass 7, count 0 2006.201.18:48:01.57#ibcon#read 6, iclass 7, count 0 2006.201.18:48:01.57#ibcon#end of sib2, iclass 7, count 0 2006.201.18:48:01.57#ibcon#*after write, iclass 7, count 0 2006.201.18:48:01.57#ibcon#*before return 0, iclass 7, count 0 2006.201.18:48:01.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:48:01.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.18:48:01.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.18:48:01.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.18:48:01.57$vck44/vblo=4,679.99 2006.201.18:48:01.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.18:48:01.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.18:48:01.57#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:01.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:48:01.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:48:01.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:48:01.57#ibcon#enter wrdev, iclass 11, count 0 2006.201.18:48:01.57#ibcon#first serial, iclass 11, count 0 2006.201.18:48:01.57#ibcon#enter sib2, iclass 11, count 0 2006.201.18:48:01.57#ibcon#flushed, iclass 11, count 0 2006.201.18:48:01.57#ibcon#about to write, iclass 11, count 0 2006.201.18:48:01.57#ibcon#wrote, iclass 11, count 0 2006.201.18:48:01.57#ibcon#about to read 3, iclass 11, count 0 2006.201.18:48:01.59#ibcon#read 3, iclass 11, count 0 2006.201.18:48:01.59#ibcon#about to read 4, iclass 11, count 0 2006.201.18:48:01.59#ibcon#read 4, iclass 11, count 0 2006.201.18:48:01.59#ibcon#about to read 5, iclass 11, count 0 2006.201.18:48:01.59#ibcon#read 5, iclass 11, count 0 2006.201.18:48:01.59#ibcon#about to read 6, iclass 11, count 0 2006.201.18:48:01.59#ibcon#read 6, iclass 11, count 0 2006.201.18:48:01.59#ibcon#end of sib2, iclass 11, count 0 2006.201.18:48:01.59#ibcon#*mode == 0, iclass 11, count 0 2006.201.18:48:01.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.18:48:01.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:48:01.59#ibcon#*before write, iclass 11, count 0 2006.201.18:48:01.59#ibcon#enter sib2, iclass 11, count 0 2006.201.18:48:01.59#ibcon#flushed, iclass 11, count 0 2006.201.18:48:01.59#ibcon#about to write, iclass 11, count 0 2006.201.18:48:01.59#ibcon#wrote, iclass 11, count 0 2006.201.18:48:01.59#ibcon#about to read 3, iclass 11, count 0 2006.201.18:48:01.63#ibcon#read 3, iclass 11, count 0 2006.201.18:48:01.63#ibcon#about to read 4, iclass 11, count 0 2006.201.18:48:01.63#ibcon#read 4, iclass 11, count 0 2006.201.18:48:01.63#ibcon#about to read 5, iclass 11, count 0 2006.201.18:48:01.63#ibcon#read 5, iclass 11, count 0 2006.201.18:48:01.63#ibcon#about to read 6, iclass 11, count 0 2006.201.18:48:01.63#ibcon#read 6, iclass 11, count 0 2006.201.18:48:01.63#ibcon#end of sib2, iclass 11, count 0 2006.201.18:48:01.63#ibcon#*after write, iclass 11, count 0 2006.201.18:48:01.63#ibcon#*before return 0, iclass 11, count 0 2006.201.18:48:01.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:48:01.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.18:48:01.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.18:48:01.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.18:48:01.63$vck44/vb=4,5 2006.201.18:48:01.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.18:48:01.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.18:48:01.63#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:01.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:48:01.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:48:01.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:48:01.69#ibcon#enter wrdev, iclass 13, count 2 2006.201.18:48:01.69#ibcon#first serial, iclass 13, count 2 2006.201.18:48:01.69#ibcon#enter sib2, iclass 13, count 2 2006.201.18:48:01.69#ibcon#flushed, iclass 13, count 2 2006.201.18:48:01.69#ibcon#about to write, iclass 13, count 2 2006.201.18:48:01.69#ibcon#wrote, iclass 13, count 2 2006.201.18:48:01.69#ibcon#about to read 3, iclass 13, count 2 2006.201.18:48:01.71#ibcon#read 3, iclass 13, count 2 2006.201.18:48:01.71#ibcon#about to read 4, iclass 13, count 2 2006.201.18:48:01.71#ibcon#read 4, iclass 13, count 2 2006.201.18:48:01.71#ibcon#about to read 5, iclass 13, count 2 2006.201.18:48:01.71#ibcon#read 5, iclass 13, count 2 2006.201.18:48:01.71#ibcon#about to read 6, iclass 13, count 2 2006.201.18:48:01.71#ibcon#read 6, iclass 13, count 2 2006.201.18:48:01.71#ibcon#end of sib2, iclass 13, count 2 2006.201.18:48:01.71#ibcon#*mode == 0, iclass 13, count 2 2006.201.18:48:01.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.18:48:01.71#ibcon#[27=AT04-05\r\n] 2006.201.18:48:01.71#ibcon#*before write, iclass 13, count 2 2006.201.18:48:01.71#ibcon#enter sib2, iclass 13, count 2 2006.201.18:48:01.71#ibcon#flushed, iclass 13, count 2 2006.201.18:48:01.71#ibcon#about to write, iclass 13, count 2 2006.201.18:48:01.71#ibcon#wrote, iclass 13, count 2 2006.201.18:48:01.71#ibcon#about to read 3, iclass 13, count 2 2006.201.18:48:01.74#ibcon#read 3, iclass 13, count 2 2006.201.18:48:01.74#ibcon#about to read 4, iclass 13, count 2 2006.201.18:48:01.74#ibcon#read 4, iclass 13, count 2 2006.201.18:48:01.74#ibcon#about to read 5, iclass 13, count 2 2006.201.18:48:01.74#ibcon#read 5, iclass 13, count 2 2006.201.18:48:01.74#ibcon#about to read 6, iclass 13, count 2 2006.201.18:48:01.74#ibcon#read 6, iclass 13, count 2 2006.201.18:48:01.74#ibcon#end of sib2, iclass 13, count 2 2006.201.18:48:01.74#ibcon#*after write, iclass 13, count 2 2006.201.18:48:01.74#ibcon#*before return 0, iclass 13, count 2 2006.201.18:48:01.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:48:01.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.18:48:01.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.18:48:01.74#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:01.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:48:01.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:48:01.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:48:01.86#ibcon#enter wrdev, iclass 13, count 0 2006.201.18:48:01.86#ibcon#first serial, iclass 13, count 0 2006.201.18:48:01.86#ibcon#enter sib2, iclass 13, count 0 2006.201.18:48:01.86#ibcon#flushed, iclass 13, count 0 2006.201.18:48:01.86#ibcon#about to write, iclass 13, count 0 2006.201.18:48:01.86#ibcon#wrote, iclass 13, count 0 2006.201.18:48:01.86#ibcon#about to read 3, iclass 13, count 0 2006.201.18:48:01.88#ibcon#read 3, iclass 13, count 0 2006.201.18:48:01.88#ibcon#about to read 4, iclass 13, count 0 2006.201.18:48:01.88#ibcon#read 4, iclass 13, count 0 2006.201.18:48:01.88#ibcon#about to read 5, iclass 13, count 0 2006.201.18:48:01.88#ibcon#read 5, iclass 13, count 0 2006.201.18:48:01.88#ibcon#about to read 6, iclass 13, count 0 2006.201.18:48:01.88#ibcon#read 6, iclass 13, count 0 2006.201.18:48:01.88#ibcon#end of sib2, iclass 13, count 0 2006.201.18:48:01.88#ibcon#*mode == 0, iclass 13, count 0 2006.201.18:48:01.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.18:48:01.88#ibcon#[27=USB\r\n] 2006.201.18:48:01.88#ibcon#*before write, iclass 13, count 0 2006.201.18:48:01.88#ibcon#enter sib2, iclass 13, count 0 2006.201.18:48:01.88#ibcon#flushed, iclass 13, count 0 2006.201.18:48:01.88#ibcon#about to write, iclass 13, count 0 2006.201.18:48:01.88#ibcon#wrote, iclass 13, count 0 2006.201.18:48:01.88#ibcon#about to read 3, iclass 13, count 0 2006.201.18:48:01.91#ibcon#read 3, iclass 13, count 0 2006.201.18:48:01.91#ibcon#about to read 4, iclass 13, count 0 2006.201.18:48:01.91#ibcon#read 4, iclass 13, count 0 2006.201.18:48:01.91#ibcon#about to read 5, iclass 13, count 0 2006.201.18:48:01.91#ibcon#read 5, iclass 13, count 0 2006.201.18:48:01.91#ibcon#about to read 6, iclass 13, count 0 2006.201.18:48:01.91#ibcon#read 6, iclass 13, count 0 2006.201.18:48:01.91#ibcon#end of sib2, iclass 13, count 0 2006.201.18:48:01.91#ibcon#*after write, iclass 13, count 0 2006.201.18:48:01.91#ibcon#*before return 0, iclass 13, count 0 2006.201.18:48:01.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:48:01.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.18:48:01.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.18:48:01.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.18:48:01.91$vck44/vblo=5,709.99 2006.201.18:48:01.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.18:48:01.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.18:48:01.91#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:01.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:48:01.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:48:01.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:48:01.91#ibcon#enter wrdev, iclass 15, count 0 2006.201.18:48:01.91#ibcon#first serial, iclass 15, count 0 2006.201.18:48:01.91#ibcon#enter sib2, iclass 15, count 0 2006.201.18:48:01.91#ibcon#flushed, iclass 15, count 0 2006.201.18:48:01.91#ibcon#about to write, iclass 15, count 0 2006.201.18:48:01.91#ibcon#wrote, iclass 15, count 0 2006.201.18:48:01.91#ibcon#about to read 3, iclass 15, count 0 2006.201.18:48:01.93#ibcon#read 3, iclass 15, count 0 2006.201.18:48:01.93#ibcon#about to read 4, iclass 15, count 0 2006.201.18:48:01.93#ibcon#read 4, iclass 15, count 0 2006.201.18:48:01.93#ibcon#about to read 5, iclass 15, count 0 2006.201.18:48:01.93#ibcon#read 5, iclass 15, count 0 2006.201.18:48:01.93#ibcon#about to read 6, iclass 15, count 0 2006.201.18:48:01.93#ibcon#read 6, iclass 15, count 0 2006.201.18:48:01.93#ibcon#end of sib2, iclass 15, count 0 2006.201.18:48:01.93#ibcon#*mode == 0, iclass 15, count 0 2006.201.18:48:01.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.18:48:01.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:48:01.93#ibcon#*before write, iclass 15, count 0 2006.201.18:48:01.93#ibcon#enter sib2, iclass 15, count 0 2006.201.18:48:01.93#ibcon#flushed, iclass 15, count 0 2006.201.18:48:01.93#ibcon#about to write, iclass 15, count 0 2006.201.18:48:01.93#ibcon#wrote, iclass 15, count 0 2006.201.18:48:01.93#ibcon#about to read 3, iclass 15, count 0 2006.201.18:48:01.97#ibcon#read 3, iclass 15, count 0 2006.201.18:48:01.97#ibcon#about to read 4, iclass 15, count 0 2006.201.18:48:01.97#ibcon#read 4, iclass 15, count 0 2006.201.18:48:01.97#ibcon#about to read 5, iclass 15, count 0 2006.201.18:48:01.97#ibcon#read 5, iclass 15, count 0 2006.201.18:48:01.97#ibcon#about to read 6, iclass 15, count 0 2006.201.18:48:01.97#ibcon#read 6, iclass 15, count 0 2006.201.18:48:01.97#ibcon#end of sib2, iclass 15, count 0 2006.201.18:48:01.97#ibcon#*after write, iclass 15, count 0 2006.201.18:48:01.97#ibcon#*before return 0, iclass 15, count 0 2006.201.18:48:01.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:48:01.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.18:48:01.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.18:48:01.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.18:48:01.97$vck44/vb=5,4 2006.201.18:48:01.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.18:48:01.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.18:48:01.97#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:01.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:48:02.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:48:02.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:48:02.03#ibcon#enter wrdev, iclass 17, count 2 2006.201.18:48:02.03#ibcon#first serial, iclass 17, count 2 2006.201.18:48:02.03#ibcon#enter sib2, iclass 17, count 2 2006.201.18:48:02.03#ibcon#flushed, iclass 17, count 2 2006.201.18:48:02.03#ibcon#about to write, iclass 17, count 2 2006.201.18:48:02.03#ibcon#wrote, iclass 17, count 2 2006.201.18:48:02.03#ibcon#about to read 3, iclass 17, count 2 2006.201.18:48:02.05#ibcon#read 3, iclass 17, count 2 2006.201.18:48:02.05#ibcon#about to read 4, iclass 17, count 2 2006.201.18:48:02.05#ibcon#read 4, iclass 17, count 2 2006.201.18:48:02.05#ibcon#about to read 5, iclass 17, count 2 2006.201.18:48:02.05#ibcon#read 5, iclass 17, count 2 2006.201.18:48:02.05#ibcon#about to read 6, iclass 17, count 2 2006.201.18:48:02.05#ibcon#read 6, iclass 17, count 2 2006.201.18:48:02.05#ibcon#end of sib2, iclass 17, count 2 2006.201.18:48:02.05#ibcon#*mode == 0, iclass 17, count 2 2006.201.18:48:02.05#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.18:48:02.05#ibcon#[27=AT05-04\r\n] 2006.201.18:48:02.05#ibcon#*before write, iclass 17, count 2 2006.201.18:48:02.05#ibcon#enter sib2, iclass 17, count 2 2006.201.18:48:02.05#ibcon#flushed, iclass 17, count 2 2006.201.18:48:02.05#ibcon#about to write, iclass 17, count 2 2006.201.18:48:02.05#ibcon#wrote, iclass 17, count 2 2006.201.18:48:02.05#ibcon#about to read 3, iclass 17, count 2 2006.201.18:48:02.08#ibcon#read 3, iclass 17, count 2 2006.201.18:48:02.08#ibcon#about to read 4, iclass 17, count 2 2006.201.18:48:02.08#ibcon#read 4, iclass 17, count 2 2006.201.18:48:02.08#ibcon#about to read 5, iclass 17, count 2 2006.201.18:48:02.08#ibcon#read 5, iclass 17, count 2 2006.201.18:48:02.08#ibcon#about to read 6, iclass 17, count 2 2006.201.18:48:02.08#ibcon#read 6, iclass 17, count 2 2006.201.18:48:02.08#ibcon#end of sib2, iclass 17, count 2 2006.201.18:48:02.08#ibcon#*after write, iclass 17, count 2 2006.201.18:48:02.08#ibcon#*before return 0, iclass 17, count 2 2006.201.18:48:02.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:48:02.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.18:48:02.08#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.18:48:02.08#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:02.08#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:48:02.20#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:48:02.20#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:48:02.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.18:48:02.20#ibcon#first serial, iclass 17, count 0 2006.201.18:48:02.20#ibcon#enter sib2, iclass 17, count 0 2006.201.18:48:02.20#ibcon#flushed, iclass 17, count 0 2006.201.18:48:02.20#ibcon#about to write, iclass 17, count 0 2006.201.18:48:02.20#ibcon#wrote, iclass 17, count 0 2006.201.18:48:02.20#ibcon#about to read 3, iclass 17, count 0 2006.201.18:48:02.22#ibcon#read 3, iclass 17, count 0 2006.201.18:48:02.22#ibcon#about to read 4, iclass 17, count 0 2006.201.18:48:02.22#ibcon#read 4, iclass 17, count 0 2006.201.18:48:02.22#ibcon#about to read 5, iclass 17, count 0 2006.201.18:48:02.22#ibcon#read 5, iclass 17, count 0 2006.201.18:48:02.22#ibcon#about to read 6, iclass 17, count 0 2006.201.18:48:02.22#ibcon#read 6, iclass 17, count 0 2006.201.18:48:02.22#ibcon#end of sib2, iclass 17, count 0 2006.201.18:48:02.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.18:48:02.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.18:48:02.22#ibcon#[27=USB\r\n] 2006.201.18:48:02.22#ibcon#*before write, iclass 17, count 0 2006.201.18:48:02.22#ibcon#enter sib2, iclass 17, count 0 2006.201.18:48:02.22#ibcon#flushed, iclass 17, count 0 2006.201.18:48:02.22#ibcon#about to write, iclass 17, count 0 2006.201.18:48:02.22#ibcon#wrote, iclass 17, count 0 2006.201.18:48:02.22#ibcon#about to read 3, iclass 17, count 0 2006.201.18:48:02.25#ibcon#read 3, iclass 17, count 0 2006.201.18:48:02.25#ibcon#about to read 4, iclass 17, count 0 2006.201.18:48:02.25#ibcon#read 4, iclass 17, count 0 2006.201.18:48:02.25#ibcon#about to read 5, iclass 17, count 0 2006.201.18:48:02.25#ibcon#read 5, iclass 17, count 0 2006.201.18:48:02.25#ibcon#about to read 6, iclass 17, count 0 2006.201.18:48:02.25#ibcon#read 6, iclass 17, count 0 2006.201.18:48:02.25#ibcon#end of sib2, iclass 17, count 0 2006.201.18:48:02.25#ibcon#*after write, iclass 17, count 0 2006.201.18:48:02.25#ibcon#*before return 0, iclass 17, count 0 2006.201.18:48:02.25#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:48:02.25#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.18:48:02.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.18:48:02.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.18:48:02.25$vck44/vblo=6,719.99 2006.201.18:48:02.25#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.18:48:02.25#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.18:48:02.25#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:02.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:48:02.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:48:02.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:48:02.25#ibcon#enter wrdev, iclass 19, count 0 2006.201.18:48:02.25#ibcon#first serial, iclass 19, count 0 2006.201.18:48:02.25#ibcon#enter sib2, iclass 19, count 0 2006.201.18:48:02.25#ibcon#flushed, iclass 19, count 0 2006.201.18:48:02.25#ibcon#about to write, iclass 19, count 0 2006.201.18:48:02.25#ibcon#wrote, iclass 19, count 0 2006.201.18:48:02.25#ibcon#about to read 3, iclass 19, count 0 2006.201.18:48:02.27#ibcon#read 3, iclass 19, count 0 2006.201.18:48:02.27#ibcon#about to read 4, iclass 19, count 0 2006.201.18:48:02.27#ibcon#read 4, iclass 19, count 0 2006.201.18:48:02.27#ibcon#about to read 5, iclass 19, count 0 2006.201.18:48:02.27#ibcon#read 5, iclass 19, count 0 2006.201.18:48:02.27#ibcon#about to read 6, iclass 19, count 0 2006.201.18:48:02.27#ibcon#read 6, iclass 19, count 0 2006.201.18:48:02.27#ibcon#end of sib2, iclass 19, count 0 2006.201.18:48:02.27#ibcon#*mode == 0, iclass 19, count 0 2006.201.18:48:02.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.18:48:02.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:48:02.27#ibcon#*before write, iclass 19, count 0 2006.201.18:48:02.27#ibcon#enter sib2, iclass 19, count 0 2006.201.18:48:02.27#ibcon#flushed, iclass 19, count 0 2006.201.18:48:02.27#ibcon#about to write, iclass 19, count 0 2006.201.18:48:02.27#ibcon#wrote, iclass 19, count 0 2006.201.18:48:02.27#ibcon#about to read 3, iclass 19, count 0 2006.201.18:48:02.31#ibcon#read 3, iclass 19, count 0 2006.201.18:48:02.31#ibcon#about to read 4, iclass 19, count 0 2006.201.18:48:02.31#ibcon#read 4, iclass 19, count 0 2006.201.18:48:02.31#ibcon#about to read 5, iclass 19, count 0 2006.201.18:48:02.31#ibcon#read 5, iclass 19, count 0 2006.201.18:48:02.31#ibcon#about to read 6, iclass 19, count 0 2006.201.18:48:02.31#ibcon#read 6, iclass 19, count 0 2006.201.18:48:02.31#ibcon#end of sib2, iclass 19, count 0 2006.201.18:48:02.31#ibcon#*after write, iclass 19, count 0 2006.201.18:48:02.31#ibcon#*before return 0, iclass 19, count 0 2006.201.18:48:02.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:48:02.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.18:48:02.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.18:48:02.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.18:48:02.31$vck44/vb=6,4 2006.201.18:48:02.31#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.18:48:02.31#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.18:48:02.31#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:02.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:48:02.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:48:02.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:48:02.37#ibcon#enter wrdev, iclass 21, count 2 2006.201.18:48:02.37#ibcon#first serial, iclass 21, count 2 2006.201.18:48:02.37#ibcon#enter sib2, iclass 21, count 2 2006.201.18:48:02.37#ibcon#flushed, iclass 21, count 2 2006.201.18:48:02.37#ibcon#about to write, iclass 21, count 2 2006.201.18:48:02.37#ibcon#wrote, iclass 21, count 2 2006.201.18:48:02.37#ibcon#about to read 3, iclass 21, count 2 2006.201.18:48:02.39#ibcon#read 3, iclass 21, count 2 2006.201.18:48:02.39#ibcon#about to read 4, iclass 21, count 2 2006.201.18:48:02.39#ibcon#read 4, iclass 21, count 2 2006.201.18:48:02.39#ibcon#about to read 5, iclass 21, count 2 2006.201.18:48:02.39#ibcon#read 5, iclass 21, count 2 2006.201.18:48:02.39#ibcon#about to read 6, iclass 21, count 2 2006.201.18:48:02.39#ibcon#read 6, iclass 21, count 2 2006.201.18:48:02.39#ibcon#end of sib2, iclass 21, count 2 2006.201.18:48:02.39#ibcon#*mode == 0, iclass 21, count 2 2006.201.18:48:02.39#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.18:48:02.39#ibcon#[27=AT06-04\r\n] 2006.201.18:48:02.39#ibcon#*before write, iclass 21, count 2 2006.201.18:48:02.39#ibcon#enter sib2, iclass 21, count 2 2006.201.18:48:02.39#ibcon#flushed, iclass 21, count 2 2006.201.18:48:02.39#ibcon#about to write, iclass 21, count 2 2006.201.18:48:02.39#ibcon#wrote, iclass 21, count 2 2006.201.18:48:02.39#ibcon#about to read 3, iclass 21, count 2 2006.201.18:48:02.42#ibcon#read 3, iclass 21, count 2 2006.201.18:48:02.42#ibcon#about to read 4, iclass 21, count 2 2006.201.18:48:02.42#ibcon#read 4, iclass 21, count 2 2006.201.18:48:02.42#ibcon#about to read 5, iclass 21, count 2 2006.201.18:48:02.42#ibcon#read 5, iclass 21, count 2 2006.201.18:48:02.42#ibcon#about to read 6, iclass 21, count 2 2006.201.18:48:02.42#ibcon#read 6, iclass 21, count 2 2006.201.18:48:02.42#ibcon#end of sib2, iclass 21, count 2 2006.201.18:48:02.42#ibcon#*after write, iclass 21, count 2 2006.201.18:48:02.42#ibcon#*before return 0, iclass 21, count 2 2006.201.18:48:02.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:48:02.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.18:48:02.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.18:48:02.42#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:02.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:48:02.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:48:02.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:48:02.54#ibcon#enter wrdev, iclass 21, count 0 2006.201.18:48:02.54#ibcon#first serial, iclass 21, count 0 2006.201.18:48:02.54#ibcon#enter sib2, iclass 21, count 0 2006.201.18:48:02.54#ibcon#flushed, iclass 21, count 0 2006.201.18:48:02.54#ibcon#about to write, iclass 21, count 0 2006.201.18:48:02.54#ibcon#wrote, iclass 21, count 0 2006.201.18:48:02.54#ibcon#about to read 3, iclass 21, count 0 2006.201.18:48:02.56#ibcon#read 3, iclass 21, count 0 2006.201.18:48:02.56#ibcon#about to read 4, iclass 21, count 0 2006.201.18:48:02.56#ibcon#read 4, iclass 21, count 0 2006.201.18:48:02.56#ibcon#about to read 5, iclass 21, count 0 2006.201.18:48:02.56#ibcon#read 5, iclass 21, count 0 2006.201.18:48:02.56#ibcon#about to read 6, iclass 21, count 0 2006.201.18:48:02.56#ibcon#read 6, iclass 21, count 0 2006.201.18:48:02.56#ibcon#end of sib2, iclass 21, count 0 2006.201.18:48:02.56#ibcon#*mode == 0, iclass 21, count 0 2006.201.18:48:02.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.18:48:02.56#ibcon#[27=USB\r\n] 2006.201.18:48:02.56#ibcon#*before write, iclass 21, count 0 2006.201.18:48:02.56#ibcon#enter sib2, iclass 21, count 0 2006.201.18:48:02.56#ibcon#flushed, iclass 21, count 0 2006.201.18:48:02.56#ibcon#about to write, iclass 21, count 0 2006.201.18:48:02.56#ibcon#wrote, iclass 21, count 0 2006.201.18:48:02.56#ibcon#about to read 3, iclass 21, count 0 2006.201.18:48:02.59#ibcon#read 3, iclass 21, count 0 2006.201.18:48:02.59#ibcon#about to read 4, iclass 21, count 0 2006.201.18:48:02.59#ibcon#read 4, iclass 21, count 0 2006.201.18:48:02.59#ibcon#about to read 5, iclass 21, count 0 2006.201.18:48:02.59#ibcon#read 5, iclass 21, count 0 2006.201.18:48:02.59#ibcon#about to read 6, iclass 21, count 0 2006.201.18:48:02.59#ibcon#read 6, iclass 21, count 0 2006.201.18:48:02.59#ibcon#end of sib2, iclass 21, count 0 2006.201.18:48:02.59#ibcon#*after write, iclass 21, count 0 2006.201.18:48:02.59#ibcon#*before return 0, iclass 21, count 0 2006.201.18:48:02.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:48:02.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.18:48:02.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.18:48:02.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.18:48:02.59$vck44/vblo=7,734.99 2006.201.18:48:02.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.18:48:02.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.18:48:02.59#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:02.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:48:02.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:48:02.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:48:02.59#ibcon#enter wrdev, iclass 23, count 0 2006.201.18:48:02.59#ibcon#first serial, iclass 23, count 0 2006.201.18:48:02.59#ibcon#enter sib2, iclass 23, count 0 2006.201.18:48:02.59#ibcon#flushed, iclass 23, count 0 2006.201.18:48:02.59#ibcon#about to write, iclass 23, count 0 2006.201.18:48:02.59#ibcon#wrote, iclass 23, count 0 2006.201.18:48:02.59#ibcon#about to read 3, iclass 23, count 0 2006.201.18:48:02.61#ibcon#read 3, iclass 23, count 0 2006.201.18:48:02.61#ibcon#about to read 4, iclass 23, count 0 2006.201.18:48:02.61#ibcon#read 4, iclass 23, count 0 2006.201.18:48:02.61#ibcon#about to read 5, iclass 23, count 0 2006.201.18:48:02.61#ibcon#read 5, iclass 23, count 0 2006.201.18:48:02.61#ibcon#about to read 6, iclass 23, count 0 2006.201.18:48:02.61#ibcon#read 6, iclass 23, count 0 2006.201.18:48:02.61#ibcon#end of sib2, iclass 23, count 0 2006.201.18:48:02.61#ibcon#*mode == 0, iclass 23, count 0 2006.201.18:48:02.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.18:48:02.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:48:02.61#ibcon#*before write, iclass 23, count 0 2006.201.18:48:02.61#ibcon#enter sib2, iclass 23, count 0 2006.201.18:48:02.61#ibcon#flushed, iclass 23, count 0 2006.201.18:48:02.61#ibcon#about to write, iclass 23, count 0 2006.201.18:48:02.61#ibcon#wrote, iclass 23, count 0 2006.201.18:48:02.61#ibcon#about to read 3, iclass 23, count 0 2006.201.18:48:02.65#ibcon#read 3, iclass 23, count 0 2006.201.18:48:02.65#ibcon#about to read 4, iclass 23, count 0 2006.201.18:48:02.65#ibcon#read 4, iclass 23, count 0 2006.201.18:48:02.65#ibcon#about to read 5, iclass 23, count 0 2006.201.18:48:02.65#ibcon#read 5, iclass 23, count 0 2006.201.18:48:02.65#ibcon#about to read 6, iclass 23, count 0 2006.201.18:48:02.65#ibcon#read 6, iclass 23, count 0 2006.201.18:48:02.65#ibcon#end of sib2, iclass 23, count 0 2006.201.18:48:02.65#ibcon#*after write, iclass 23, count 0 2006.201.18:48:02.65#ibcon#*before return 0, iclass 23, count 0 2006.201.18:48:02.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:48:02.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.18:48:02.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.18:48:02.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.18:48:02.65$vck44/vb=7,4 2006.201.18:48:02.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.18:48:02.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.18:48:02.65#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:02.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:48:02.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:48:02.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:48:02.71#ibcon#enter wrdev, iclass 25, count 2 2006.201.18:48:02.71#ibcon#first serial, iclass 25, count 2 2006.201.18:48:02.71#ibcon#enter sib2, iclass 25, count 2 2006.201.18:48:02.71#ibcon#flushed, iclass 25, count 2 2006.201.18:48:02.71#ibcon#about to write, iclass 25, count 2 2006.201.18:48:02.71#ibcon#wrote, iclass 25, count 2 2006.201.18:48:02.71#ibcon#about to read 3, iclass 25, count 2 2006.201.18:48:02.73#ibcon#read 3, iclass 25, count 2 2006.201.18:48:02.73#ibcon#about to read 4, iclass 25, count 2 2006.201.18:48:02.73#ibcon#read 4, iclass 25, count 2 2006.201.18:48:02.73#ibcon#about to read 5, iclass 25, count 2 2006.201.18:48:02.73#ibcon#read 5, iclass 25, count 2 2006.201.18:48:02.73#ibcon#about to read 6, iclass 25, count 2 2006.201.18:48:02.73#ibcon#read 6, iclass 25, count 2 2006.201.18:48:02.73#ibcon#end of sib2, iclass 25, count 2 2006.201.18:48:02.73#ibcon#*mode == 0, iclass 25, count 2 2006.201.18:48:02.73#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.18:48:02.73#ibcon#[27=AT07-04\r\n] 2006.201.18:48:02.73#ibcon#*before write, iclass 25, count 2 2006.201.18:48:02.73#ibcon#enter sib2, iclass 25, count 2 2006.201.18:48:02.73#ibcon#flushed, iclass 25, count 2 2006.201.18:48:02.73#ibcon#about to write, iclass 25, count 2 2006.201.18:48:02.73#ibcon#wrote, iclass 25, count 2 2006.201.18:48:02.73#ibcon#about to read 3, iclass 25, count 2 2006.201.18:48:02.76#ibcon#read 3, iclass 25, count 2 2006.201.18:48:02.76#ibcon#about to read 4, iclass 25, count 2 2006.201.18:48:02.76#ibcon#read 4, iclass 25, count 2 2006.201.18:48:02.76#ibcon#about to read 5, iclass 25, count 2 2006.201.18:48:02.76#ibcon#read 5, iclass 25, count 2 2006.201.18:48:02.76#ibcon#about to read 6, iclass 25, count 2 2006.201.18:48:02.76#ibcon#read 6, iclass 25, count 2 2006.201.18:48:02.76#ibcon#end of sib2, iclass 25, count 2 2006.201.18:48:02.76#ibcon#*after write, iclass 25, count 2 2006.201.18:48:02.76#ibcon#*before return 0, iclass 25, count 2 2006.201.18:48:02.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:48:02.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.18:48:02.76#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.18:48:02.76#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:02.76#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:48:02.88#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:48:02.88#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:48:02.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.18:48:02.88#ibcon#first serial, iclass 25, count 0 2006.201.18:48:02.88#ibcon#enter sib2, iclass 25, count 0 2006.201.18:48:02.88#ibcon#flushed, iclass 25, count 0 2006.201.18:48:02.88#ibcon#about to write, iclass 25, count 0 2006.201.18:48:02.88#ibcon#wrote, iclass 25, count 0 2006.201.18:48:02.88#ibcon#about to read 3, iclass 25, count 0 2006.201.18:48:02.90#ibcon#read 3, iclass 25, count 0 2006.201.18:48:02.90#ibcon#about to read 4, iclass 25, count 0 2006.201.18:48:02.90#ibcon#read 4, iclass 25, count 0 2006.201.18:48:02.90#ibcon#about to read 5, iclass 25, count 0 2006.201.18:48:02.90#ibcon#read 5, iclass 25, count 0 2006.201.18:48:02.90#ibcon#about to read 6, iclass 25, count 0 2006.201.18:48:02.90#ibcon#read 6, iclass 25, count 0 2006.201.18:48:02.90#ibcon#end of sib2, iclass 25, count 0 2006.201.18:48:02.90#ibcon#*mode == 0, iclass 25, count 0 2006.201.18:48:02.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.18:48:02.90#ibcon#[27=USB\r\n] 2006.201.18:48:02.90#ibcon#*before write, iclass 25, count 0 2006.201.18:48:02.90#ibcon#enter sib2, iclass 25, count 0 2006.201.18:48:02.90#ibcon#flushed, iclass 25, count 0 2006.201.18:48:02.90#ibcon#about to write, iclass 25, count 0 2006.201.18:48:02.90#ibcon#wrote, iclass 25, count 0 2006.201.18:48:02.90#ibcon#about to read 3, iclass 25, count 0 2006.201.18:48:02.93#ibcon#read 3, iclass 25, count 0 2006.201.18:48:02.93#ibcon#about to read 4, iclass 25, count 0 2006.201.18:48:02.93#ibcon#read 4, iclass 25, count 0 2006.201.18:48:02.93#ibcon#about to read 5, iclass 25, count 0 2006.201.18:48:02.93#ibcon#read 5, iclass 25, count 0 2006.201.18:48:02.93#ibcon#about to read 6, iclass 25, count 0 2006.201.18:48:02.93#ibcon#read 6, iclass 25, count 0 2006.201.18:48:02.93#ibcon#end of sib2, iclass 25, count 0 2006.201.18:48:02.93#ibcon#*after write, iclass 25, count 0 2006.201.18:48:02.93#ibcon#*before return 0, iclass 25, count 0 2006.201.18:48:02.93#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:48:02.93#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.18:48:02.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.18:48:02.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.18:48:02.93$vck44/vblo=8,744.99 2006.201.18:48:02.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.18:48:02.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.18:48:02.93#ibcon#ireg 17 cls_cnt 0 2006.201.18:48:02.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:48:02.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:48:02.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:48:02.93#ibcon#enter wrdev, iclass 27, count 0 2006.201.18:48:02.93#ibcon#first serial, iclass 27, count 0 2006.201.18:48:02.93#ibcon#enter sib2, iclass 27, count 0 2006.201.18:48:02.93#ibcon#flushed, iclass 27, count 0 2006.201.18:48:02.93#ibcon#about to write, iclass 27, count 0 2006.201.18:48:02.93#ibcon#wrote, iclass 27, count 0 2006.201.18:48:02.93#ibcon#about to read 3, iclass 27, count 0 2006.201.18:48:02.95#ibcon#read 3, iclass 27, count 0 2006.201.18:48:02.95#ibcon#about to read 4, iclass 27, count 0 2006.201.18:48:02.95#ibcon#read 4, iclass 27, count 0 2006.201.18:48:02.95#ibcon#about to read 5, iclass 27, count 0 2006.201.18:48:02.95#ibcon#read 5, iclass 27, count 0 2006.201.18:48:02.95#ibcon#about to read 6, iclass 27, count 0 2006.201.18:48:02.95#ibcon#read 6, iclass 27, count 0 2006.201.18:48:02.95#ibcon#end of sib2, iclass 27, count 0 2006.201.18:48:02.95#ibcon#*mode == 0, iclass 27, count 0 2006.201.18:48:02.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.18:48:02.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:48:02.95#ibcon#*before write, iclass 27, count 0 2006.201.18:48:02.95#ibcon#enter sib2, iclass 27, count 0 2006.201.18:48:02.95#ibcon#flushed, iclass 27, count 0 2006.201.18:48:02.95#ibcon#about to write, iclass 27, count 0 2006.201.18:48:02.95#ibcon#wrote, iclass 27, count 0 2006.201.18:48:02.95#ibcon#about to read 3, iclass 27, count 0 2006.201.18:48:02.99#ibcon#read 3, iclass 27, count 0 2006.201.18:48:02.99#ibcon#about to read 4, iclass 27, count 0 2006.201.18:48:02.99#ibcon#read 4, iclass 27, count 0 2006.201.18:48:02.99#ibcon#about to read 5, iclass 27, count 0 2006.201.18:48:02.99#ibcon#read 5, iclass 27, count 0 2006.201.18:48:02.99#ibcon#about to read 6, iclass 27, count 0 2006.201.18:48:02.99#ibcon#read 6, iclass 27, count 0 2006.201.18:48:02.99#ibcon#end of sib2, iclass 27, count 0 2006.201.18:48:02.99#ibcon#*after write, iclass 27, count 0 2006.201.18:48:02.99#ibcon#*before return 0, iclass 27, count 0 2006.201.18:48:02.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:48:02.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.18:48:02.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.18:48:02.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.18:48:02.99$vck44/vb=8,4 2006.201.18:48:02.99#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.18:48:02.99#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.18:48:02.99#ibcon#ireg 11 cls_cnt 2 2006.201.18:48:02.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:03.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:03.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:03.05#ibcon#enter wrdev, iclass 29, count 2 2006.201.18:48:03.05#ibcon#first serial, iclass 29, count 2 2006.201.18:48:03.05#ibcon#enter sib2, iclass 29, count 2 2006.201.18:48:03.05#ibcon#flushed, iclass 29, count 2 2006.201.18:48:03.05#ibcon#about to write, iclass 29, count 2 2006.201.18:48:03.05#ibcon#wrote, iclass 29, count 2 2006.201.18:48:03.05#ibcon#about to read 3, iclass 29, count 2 2006.201.18:48:03.07#ibcon#read 3, iclass 29, count 2 2006.201.18:48:03.07#ibcon#about to read 4, iclass 29, count 2 2006.201.18:48:03.07#ibcon#read 4, iclass 29, count 2 2006.201.18:48:03.07#ibcon#about to read 5, iclass 29, count 2 2006.201.18:48:03.07#ibcon#read 5, iclass 29, count 2 2006.201.18:48:03.07#ibcon#about to read 6, iclass 29, count 2 2006.201.18:48:03.07#ibcon#read 6, iclass 29, count 2 2006.201.18:48:03.07#ibcon#end of sib2, iclass 29, count 2 2006.201.18:48:03.07#ibcon#*mode == 0, iclass 29, count 2 2006.201.18:48:03.07#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.18:48:03.07#ibcon#[27=AT08-04\r\n] 2006.201.18:48:03.07#ibcon#*before write, iclass 29, count 2 2006.201.18:48:03.07#ibcon#enter sib2, iclass 29, count 2 2006.201.18:48:03.07#ibcon#flushed, iclass 29, count 2 2006.201.18:48:03.07#ibcon#about to write, iclass 29, count 2 2006.201.18:48:03.07#ibcon#wrote, iclass 29, count 2 2006.201.18:48:03.07#ibcon#about to read 3, iclass 29, count 2 2006.201.18:48:03.10#ibcon#read 3, iclass 29, count 2 2006.201.18:48:03.10#ibcon#about to read 4, iclass 29, count 2 2006.201.18:48:03.10#ibcon#read 4, iclass 29, count 2 2006.201.18:48:03.10#ibcon#about to read 5, iclass 29, count 2 2006.201.18:48:03.10#ibcon#read 5, iclass 29, count 2 2006.201.18:48:03.10#ibcon#about to read 6, iclass 29, count 2 2006.201.18:48:03.10#ibcon#read 6, iclass 29, count 2 2006.201.18:48:03.10#ibcon#end of sib2, iclass 29, count 2 2006.201.18:48:03.10#ibcon#*after write, iclass 29, count 2 2006.201.18:48:03.10#ibcon#*before return 0, iclass 29, count 2 2006.201.18:48:03.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:03.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.18:48:03.10#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.18:48:03.10#ibcon#ireg 7 cls_cnt 0 2006.201.18:48:03.10#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:03.22#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:03.22#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:03.22#ibcon#enter wrdev, iclass 29, count 0 2006.201.18:48:03.22#ibcon#first serial, iclass 29, count 0 2006.201.18:48:03.22#ibcon#enter sib2, iclass 29, count 0 2006.201.18:48:03.22#ibcon#flushed, iclass 29, count 0 2006.201.18:48:03.22#ibcon#about to write, iclass 29, count 0 2006.201.18:48:03.22#ibcon#wrote, iclass 29, count 0 2006.201.18:48:03.22#ibcon#about to read 3, iclass 29, count 0 2006.201.18:48:03.24#ibcon#read 3, iclass 29, count 0 2006.201.18:48:03.24#ibcon#about to read 4, iclass 29, count 0 2006.201.18:48:03.24#ibcon#read 4, iclass 29, count 0 2006.201.18:48:03.24#ibcon#about to read 5, iclass 29, count 0 2006.201.18:48:03.24#ibcon#read 5, iclass 29, count 0 2006.201.18:48:03.24#ibcon#about to read 6, iclass 29, count 0 2006.201.18:48:03.24#ibcon#read 6, iclass 29, count 0 2006.201.18:48:03.24#ibcon#end of sib2, iclass 29, count 0 2006.201.18:48:03.24#ibcon#*mode == 0, iclass 29, count 0 2006.201.18:48:03.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.18:48:03.24#ibcon#[27=USB\r\n] 2006.201.18:48:03.24#ibcon#*before write, iclass 29, count 0 2006.201.18:48:03.24#ibcon#enter sib2, iclass 29, count 0 2006.201.18:48:03.24#ibcon#flushed, iclass 29, count 0 2006.201.18:48:03.24#ibcon#about to write, iclass 29, count 0 2006.201.18:48:03.24#ibcon#wrote, iclass 29, count 0 2006.201.18:48:03.24#ibcon#about to read 3, iclass 29, count 0 2006.201.18:48:03.27#ibcon#read 3, iclass 29, count 0 2006.201.18:48:03.27#ibcon#about to read 4, iclass 29, count 0 2006.201.18:48:03.27#ibcon#read 4, iclass 29, count 0 2006.201.18:48:03.27#ibcon#about to read 5, iclass 29, count 0 2006.201.18:48:03.27#ibcon#read 5, iclass 29, count 0 2006.201.18:48:03.27#ibcon#about to read 6, iclass 29, count 0 2006.201.18:48:03.27#ibcon#read 6, iclass 29, count 0 2006.201.18:48:03.27#ibcon#end of sib2, iclass 29, count 0 2006.201.18:48:03.27#ibcon#*after write, iclass 29, count 0 2006.201.18:48:03.27#ibcon#*before return 0, iclass 29, count 0 2006.201.18:48:03.27#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:03.27#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.18:48:03.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.18:48:03.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.18:48:03.27$vck44/vabw=wide 2006.201.18:48:03.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.18:48:03.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.18:48:03.27#ibcon#ireg 8 cls_cnt 0 2006.201.18:48:03.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:03.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:03.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:03.27#ibcon#enter wrdev, iclass 31, count 0 2006.201.18:48:03.27#ibcon#first serial, iclass 31, count 0 2006.201.18:48:03.27#ibcon#enter sib2, iclass 31, count 0 2006.201.18:48:03.27#ibcon#flushed, iclass 31, count 0 2006.201.18:48:03.27#ibcon#about to write, iclass 31, count 0 2006.201.18:48:03.27#ibcon#wrote, iclass 31, count 0 2006.201.18:48:03.27#ibcon#about to read 3, iclass 31, count 0 2006.201.18:48:03.29#ibcon#read 3, iclass 31, count 0 2006.201.18:48:03.29#ibcon#about to read 4, iclass 31, count 0 2006.201.18:48:03.29#ibcon#read 4, iclass 31, count 0 2006.201.18:48:03.29#ibcon#about to read 5, iclass 31, count 0 2006.201.18:48:03.29#ibcon#read 5, iclass 31, count 0 2006.201.18:48:03.29#ibcon#about to read 6, iclass 31, count 0 2006.201.18:48:03.29#ibcon#read 6, iclass 31, count 0 2006.201.18:48:03.29#ibcon#end of sib2, iclass 31, count 0 2006.201.18:48:03.29#ibcon#*mode == 0, iclass 31, count 0 2006.201.18:48:03.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.18:48:03.29#ibcon#[25=BW32\r\n] 2006.201.18:48:03.29#ibcon#*before write, iclass 31, count 0 2006.201.18:48:03.29#ibcon#enter sib2, iclass 31, count 0 2006.201.18:48:03.29#ibcon#flushed, iclass 31, count 0 2006.201.18:48:03.29#ibcon#about to write, iclass 31, count 0 2006.201.18:48:03.29#ibcon#wrote, iclass 31, count 0 2006.201.18:48:03.29#ibcon#about to read 3, iclass 31, count 0 2006.201.18:48:03.32#ibcon#read 3, iclass 31, count 0 2006.201.18:48:03.32#ibcon#about to read 4, iclass 31, count 0 2006.201.18:48:03.32#ibcon#read 4, iclass 31, count 0 2006.201.18:48:03.32#ibcon#about to read 5, iclass 31, count 0 2006.201.18:48:03.32#ibcon#read 5, iclass 31, count 0 2006.201.18:48:03.32#ibcon#about to read 6, iclass 31, count 0 2006.201.18:48:03.32#ibcon#read 6, iclass 31, count 0 2006.201.18:48:03.32#ibcon#end of sib2, iclass 31, count 0 2006.201.18:48:03.32#ibcon#*after write, iclass 31, count 0 2006.201.18:48:03.32#ibcon#*before return 0, iclass 31, count 0 2006.201.18:48:03.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:03.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.18:48:03.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.18:48:03.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.18:48:03.32$vck44/vbbw=wide 2006.201.18:48:03.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.18:48:03.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.18:48:03.32#ibcon#ireg 8 cls_cnt 0 2006.201.18:48:03.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:48:03.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:48:03.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:48:03.39#ibcon#enter wrdev, iclass 33, count 0 2006.201.18:48:03.39#ibcon#first serial, iclass 33, count 0 2006.201.18:48:03.39#ibcon#enter sib2, iclass 33, count 0 2006.201.18:48:03.39#ibcon#flushed, iclass 33, count 0 2006.201.18:48:03.39#ibcon#about to write, iclass 33, count 0 2006.201.18:48:03.39#ibcon#wrote, iclass 33, count 0 2006.201.18:48:03.39#ibcon#about to read 3, iclass 33, count 0 2006.201.18:48:03.41#ibcon#read 3, iclass 33, count 0 2006.201.18:48:03.41#ibcon#about to read 4, iclass 33, count 0 2006.201.18:48:03.41#ibcon#read 4, iclass 33, count 0 2006.201.18:48:03.41#ibcon#about to read 5, iclass 33, count 0 2006.201.18:48:03.41#ibcon#read 5, iclass 33, count 0 2006.201.18:48:03.41#ibcon#about to read 6, iclass 33, count 0 2006.201.18:48:03.41#ibcon#read 6, iclass 33, count 0 2006.201.18:48:03.41#ibcon#end of sib2, iclass 33, count 0 2006.201.18:48:03.41#ibcon#*mode == 0, iclass 33, count 0 2006.201.18:48:03.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.18:48:03.41#ibcon#[27=BW32\r\n] 2006.201.18:48:03.41#ibcon#*before write, iclass 33, count 0 2006.201.18:48:03.41#ibcon#enter sib2, iclass 33, count 0 2006.201.18:48:03.41#ibcon#flushed, iclass 33, count 0 2006.201.18:48:03.41#ibcon#about to write, iclass 33, count 0 2006.201.18:48:03.41#ibcon#wrote, iclass 33, count 0 2006.201.18:48:03.41#ibcon#about to read 3, iclass 33, count 0 2006.201.18:48:03.44#ibcon#read 3, iclass 33, count 0 2006.201.18:48:03.44#ibcon#about to read 4, iclass 33, count 0 2006.201.18:48:03.44#ibcon#read 4, iclass 33, count 0 2006.201.18:48:03.44#ibcon#about to read 5, iclass 33, count 0 2006.201.18:48:03.44#ibcon#read 5, iclass 33, count 0 2006.201.18:48:03.44#ibcon#about to read 6, iclass 33, count 0 2006.201.18:48:03.44#ibcon#read 6, iclass 33, count 0 2006.201.18:48:03.44#ibcon#end of sib2, iclass 33, count 0 2006.201.18:48:03.44#ibcon#*after write, iclass 33, count 0 2006.201.18:48:03.44#ibcon#*before return 0, iclass 33, count 0 2006.201.18:48:03.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:48:03.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.18:48:03.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.18:48:03.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.18:48:03.44$setupk4/ifdk4 2006.201.18:48:03.44$ifdk4/lo= 2006.201.18:48:03.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:48:03.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:48:03.44$ifdk4/patch= 2006.201.18:48:03.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:48:03.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:48:03.44$setupk4/!*+20s 2006.201.18:48:04.99#abcon#<5=/03 0.8 2.4 20.491001002.0\r\n> 2006.201.18:48:05.01#abcon#{5=INTERFACE CLEAR} 2006.201.18:48:05.07#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:48:15.16#abcon#<5=/03 0.8 2.4 20.491001002.0\r\n> 2006.201.18:48:15.18#abcon#{5=INTERFACE CLEAR} 2006.201.18:48:15.24#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:48:17.92$setupk4/"tpicd 2006.201.18:48:17.92$setupk4/echo=off 2006.201.18:48:17.92$setupk4/xlog=off 2006.201.18:48:17.92:!2006.201.18:54:12 2006.201.18:49:08.14#trakl#Source acquired 2006.201.18:49:09.14#flagr#flagr/antenna,acquired 2006.201.18:54:12.00:preob 2006.201.18:54:13.13/onsource/TRACKING 2006.201.18:54:13.13:!2006.201.18:54:22 2006.201.18:54:22.00:"tape 2006.201.18:54:22.00:"st=record 2006.201.18:54:22.00:data_valid=on 2006.201.18:54:22.00:midob 2006.201.18:54:22.14/onsource/TRACKING 2006.201.18:54:22.14/wx/20.50,1002.1,100 2006.201.18:54:22.28/cable/+6.4773E-03 2006.201.18:54:23.37/va/01,08,usb,yes,39,42 2006.201.18:54:23.37/va/02,07,usb,yes,42,43 2006.201.18:54:23.37/va/03,08,usb,yes,38,40 2006.201.18:54:23.37/va/04,07,usb,yes,43,46 2006.201.18:54:23.37/va/05,04,usb,yes,39,39 2006.201.18:54:23.37/va/06,05,usb,yes,39,39 2006.201.18:54:23.37/va/07,05,usb,yes,38,39 2006.201.18:54:23.37/va/08,04,usb,yes,38,45 2006.201.18:54:23.60/valo/01,524.99,yes,locked 2006.201.18:54:23.60/valo/02,534.99,yes,locked 2006.201.18:54:23.60/valo/03,564.99,yes,locked 2006.201.18:54:23.60/valo/04,624.99,yes,locked 2006.201.18:54:23.60/valo/05,734.99,yes,locked 2006.201.18:54:23.60/valo/06,814.99,yes,locked 2006.201.18:54:23.60/valo/07,864.99,yes,locked 2006.201.18:54:23.60/valo/08,884.99,yes,locked 2006.201.18:54:24.69/vb/01,04,usb,yes,30,28 2006.201.18:54:24.69/vb/02,05,usb,yes,28,28 2006.201.18:54:24.69/vb/03,04,usb,yes,29,32 2006.201.18:54:24.69/vb/04,05,usb,yes,29,28 2006.201.18:54:24.69/vb/05,04,usb,yes,26,28 2006.201.18:54:24.69/vb/06,04,usb,yes,30,27 2006.201.18:54:24.69/vb/07,04,usb,yes,30,30 2006.201.18:54:24.69/vb/08,04,usb,yes,28,31 2006.201.18:54:24.93/vblo/01,629.99,yes,locked 2006.201.18:54:24.93/vblo/02,634.99,yes,locked 2006.201.18:54:24.93/vblo/03,649.99,yes,locked 2006.201.18:54:24.93/vblo/04,679.99,yes,locked 2006.201.18:54:24.93/vblo/05,709.99,yes,locked 2006.201.18:54:24.93/vblo/06,719.99,yes,locked 2006.201.18:54:24.93/vblo/07,734.99,yes,locked 2006.201.18:54:24.93/vblo/08,744.99,yes,locked 2006.201.18:54:25.08/vabw/8 2006.201.18:54:25.23/vbbw/8 2006.201.18:54:25.32/xfe/off,on,15.2 2006.201.18:54:25.69/ifatt/23,28,28,28 2006.201.18:54:26.07/fmout-gps/S +4.47E-07 2006.201.18:54:26.11:!2006.201.18:55:12 2006.201.18:55:12.00:data_valid=off 2006.201.18:55:12.00:"et 2006.201.18:55:12.00:!+3s 2006.201.18:55:15.02:"tape 2006.201.18:55:15.02:postob 2006.201.18:55:15.21/cable/+6.4789E-03 2006.201.18:55:15.21/wx/20.50,1002.1,100 2006.201.18:55:15.28/fmout-gps/S +4.47E-07 2006.201.18:55:15.28:scan_name=201-1858,jd0607,110 2006.201.18:55:15.28:source=0528+134,053056.42,133155.1,2000.0,cw 2006.201.18:55:16.14#flagr#flagr/antenna,new-source 2006.201.18:55:16.14:checkk5 2006.201.18:55:16.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.18:55:16.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.18:55:17.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.18:55:17.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.18:55:18.01/chk_obsdata//k5ts1/T2011854??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.18:55:18.37/chk_obsdata//k5ts2/T2011854??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.18:55:18.73/chk_obsdata//k5ts3/T2011854??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.18:55:19.10/chk_obsdata//k5ts4/T2011854??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.18:55:19.79/k5log//k5ts1_log_newline 2006.201.18:55:20.47/k5log//k5ts2_log_newline 2006.201.18:55:21.15/k5log//k5ts3_log_newline 2006.201.18:55:21.84/k5log//k5ts4_log_newline 2006.201.18:55:21.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.18:55:21.87:setupk4=1 2006.201.18:55:21.87$setupk4/echo=on 2006.201.18:55:21.87$setupk4/pcalon 2006.201.18:55:21.87$pcalon/"no phase cal control is implemented here 2006.201.18:55:21.87$setupk4/"tpicd=stop 2006.201.18:55:21.87$setupk4/"rec=synch_on 2006.201.18:55:21.87$setupk4/"rec_mode=128 2006.201.18:55:21.87$setupk4/!* 2006.201.18:55:21.87$setupk4/recpk4 2006.201.18:55:21.87$recpk4/recpatch= 2006.201.18:55:21.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.18:55:21.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.18:55:21.87$setupk4/vck44 2006.201.18:55:21.87$vck44/valo=1,524.99 2006.201.18:55:21.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.18:55:21.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.18:55:21.87#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:21.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:21.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:21.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:21.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:55:21.87#ibcon#first serial, iclass 30, count 0 2006.201.18:55:21.87#ibcon#enter sib2, iclass 30, count 0 2006.201.18:55:21.87#ibcon#flushed, iclass 30, count 0 2006.201.18:55:21.87#ibcon#about to write, iclass 30, count 0 2006.201.18:55:21.87#ibcon#wrote, iclass 30, count 0 2006.201.18:55:21.87#ibcon#about to read 3, iclass 30, count 0 2006.201.18:55:21.91#ibcon#read 3, iclass 30, count 0 2006.201.18:55:21.91#ibcon#about to read 4, iclass 30, count 0 2006.201.18:55:21.91#ibcon#read 4, iclass 30, count 0 2006.201.18:55:21.91#ibcon#about to read 5, iclass 30, count 0 2006.201.18:55:21.91#ibcon#read 5, iclass 30, count 0 2006.201.18:55:21.91#ibcon#about to read 6, iclass 30, count 0 2006.201.18:55:21.91#ibcon#read 6, iclass 30, count 0 2006.201.18:55:21.91#ibcon#end of sib2, iclass 30, count 0 2006.201.18:55:21.91#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:55:21.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:55:21.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.18:55:21.91#ibcon#*before write, iclass 30, count 0 2006.201.18:55:21.91#ibcon#enter sib2, iclass 30, count 0 2006.201.18:55:21.91#ibcon#flushed, iclass 30, count 0 2006.201.18:55:21.91#ibcon#about to write, iclass 30, count 0 2006.201.18:55:21.91#ibcon#wrote, iclass 30, count 0 2006.201.18:55:21.91#ibcon#about to read 3, iclass 30, count 0 2006.201.18:55:21.96#ibcon#read 3, iclass 30, count 0 2006.201.18:55:21.96#ibcon#about to read 4, iclass 30, count 0 2006.201.18:55:21.96#ibcon#read 4, iclass 30, count 0 2006.201.18:55:21.96#ibcon#about to read 5, iclass 30, count 0 2006.201.18:55:21.96#ibcon#read 5, iclass 30, count 0 2006.201.18:55:21.96#ibcon#about to read 6, iclass 30, count 0 2006.201.18:55:21.96#ibcon#read 6, iclass 30, count 0 2006.201.18:55:21.96#ibcon#end of sib2, iclass 30, count 0 2006.201.18:55:21.96#ibcon#*after write, iclass 30, count 0 2006.201.18:55:21.96#ibcon#*before return 0, iclass 30, count 0 2006.201.18:55:21.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:21.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:21.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:55:21.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:55:21.96$vck44/va=1,8 2006.201.18:55:21.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.18:55:21.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.18:55:21.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:21.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:21.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:21.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:21.96#ibcon#enter wrdev, iclass 32, count 2 2006.201.18:55:21.96#ibcon#first serial, iclass 32, count 2 2006.201.18:55:21.96#ibcon#enter sib2, iclass 32, count 2 2006.201.18:55:21.96#ibcon#flushed, iclass 32, count 2 2006.201.18:55:21.96#ibcon#about to write, iclass 32, count 2 2006.201.18:55:21.96#ibcon#wrote, iclass 32, count 2 2006.201.18:55:21.96#ibcon#about to read 3, iclass 32, count 2 2006.201.18:55:21.98#ibcon#read 3, iclass 32, count 2 2006.201.18:55:21.98#ibcon#about to read 4, iclass 32, count 2 2006.201.18:55:21.98#ibcon#read 4, iclass 32, count 2 2006.201.18:55:21.98#ibcon#about to read 5, iclass 32, count 2 2006.201.18:55:21.98#ibcon#read 5, iclass 32, count 2 2006.201.18:55:21.98#ibcon#about to read 6, iclass 32, count 2 2006.201.18:55:21.98#ibcon#read 6, iclass 32, count 2 2006.201.18:55:21.98#ibcon#end of sib2, iclass 32, count 2 2006.201.18:55:21.98#ibcon#*mode == 0, iclass 32, count 2 2006.201.18:55:21.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.18:55:21.98#ibcon#[25=AT01-08\r\n] 2006.201.18:55:21.98#ibcon#*before write, iclass 32, count 2 2006.201.18:55:21.98#ibcon#enter sib2, iclass 32, count 2 2006.201.18:55:21.98#ibcon#flushed, iclass 32, count 2 2006.201.18:55:21.98#ibcon#about to write, iclass 32, count 2 2006.201.18:55:21.98#ibcon#wrote, iclass 32, count 2 2006.201.18:55:21.98#ibcon#about to read 3, iclass 32, count 2 2006.201.18:55:22.02#ibcon#read 3, iclass 32, count 2 2006.201.18:55:22.02#ibcon#about to read 4, iclass 32, count 2 2006.201.18:55:22.02#ibcon#read 4, iclass 32, count 2 2006.201.18:55:22.02#ibcon#about to read 5, iclass 32, count 2 2006.201.18:55:22.02#ibcon#read 5, iclass 32, count 2 2006.201.18:55:22.02#ibcon#about to read 6, iclass 32, count 2 2006.201.18:55:22.02#ibcon#read 6, iclass 32, count 2 2006.201.18:55:22.02#ibcon#end of sib2, iclass 32, count 2 2006.201.18:55:22.02#ibcon#*after write, iclass 32, count 2 2006.201.18:55:22.02#ibcon#*before return 0, iclass 32, count 2 2006.201.18:55:22.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:22.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:22.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.18:55:22.02#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:22.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:22.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:22.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:22.14#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:55:22.14#ibcon#first serial, iclass 32, count 0 2006.201.18:55:22.14#ibcon#enter sib2, iclass 32, count 0 2006.201.18:55:22.14#ibcon#flushed, iclass 32, count 0 2006.201.18:55:22.14#ibcon#about to write, iclass 32, count 0 2006.201.18:55:22.14#ibcon#wrote, iclass 32, count 0 2006.201.18:55:22.14#ibcon#about to read 3, iclass 32, count 0 2006.201.18:55:22.16#ibcon#read 3, iclass 32, count 0 2006.201.18:55:22.16#ibcon#about to read 4, iclass 32, count 0 2006.201.18:55:22.16#ibcon#read 4, iclass 32, count 0 2006.201.18:55:22.16#ibcon#about to read 5, iclass 32, count 0 2006.201.18:55:22.16#ibcon#read 5, iclass 32, count 0 2006.201.18:55:22.16#ibcon#about to read 6, iclass 32, count 0 2006.201.18:55:22.16#ibcon#read 6, iclass 32, count 0 2006.201.18:55:22.16#ibcon#end of sib2, iclass 32, count 0 2006.201.18:55:22.16#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:55:22.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:55:22.16#ibcon#[25=USB\r\n] 2006.201.18:55:22.16#ibcon#*before write, iclass 32, count 0 2006.201.18:55:22.16#ibcon#enter sib2, iclass 32, count 0 2006.201.18:55:22.16#ibcon#flushed, iclass 32, count 0 2006.201.18:55:22.16#ibcon#about to write, iclass 32, count 0 2006.201.18:55:22.16#ibcon#wrote, iclass 32, count 0 2006.201.18:55:22.16#ibcon#about to read 3, iclass 32, count 0 2006.201.18:55:22.19#ibcon#read 3, iclass 32, count 0 2006.201.18:55:22.19#ibcon#about to read 4, iclass 32, count 0 2006.201.18:55:22.19#ibcon#read 4, iclass 32, count 0 2006.201.18:55:22.19#ibcon#about to read 5, iclass 32, count 0 2006.201.18:55:22.19#ibcon#read 5, iclass 32, count 0 2006.201.18:55:22.19#ibcon#about to read 6, iclass 32, count 0 2006.201.18:55:22.19#ibcon#read 6, iclass 32, count 0 2006.201.18:55:22.19#ibcon#end of sib2, iclass 32, count 0 2006.201.18:55:22.19#ibcon#*after write, iclass 32, count 0 2006.201.18:55:22.19#ibcon#*before return 0, iclass 32, count 0 2006.201.18:55:22.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:22.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:22.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:55:22.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:55:22.19$vck44/valo=2,534.99 2006.201.18:55:22.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.18:55:22.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.18:55:22.19#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:22.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:22.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:22.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:22.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:55:22.19#ibcon#first serial, iclass 34, count 0 2006.201.18:55:22.19#ibcon#enter sib2, iclass 34, count 0 2006.201.18:55:22.19#ibcon#flushed, iclass 34, count 0 2006.201.18:55:22.19#ibcon#about to write, iclass 34, count 0 2006.201.18:55:22.19#ibcon#wrote, iclass 34, count 0 2006.201.18:55:22.19#ibcon#about to read 3, iclass 34, count 0 2006.201.18:55:22.21#ibcon#read 3, iclass 34, count 0 2006.201.18:55:22.21#ibcon#about to read 4, iclass 34, count 0 2006.201.18:55:22.21#ibcon#read 4, iclass 34, count 0 2006.201.18:55:22.21#ibcon#about to read 5, iclass 34, count 0 2006.201.18:55:22.21#ibcon#read 5, iclass 34, count 0 2006.201.18:55:22.21#ibcon#about to read 6, iclass 34, count 0 2006.201.18:55:22.21#ibcon#read 6, iclass 34, count 0 2006.201.18:55:22.21#ibcon#end of sib2, iclass 34, count 0 2006.201.18:55:22.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:55:22.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:55:22.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.18:55:22.21#ibcon#*before write, iclass 34, count 0 2006.201.18:55:22.21#ibcon#enter sib2, iclass 34, count 0 2006.201.18:55:22.21#ibcon#flushed, iclass 34, count 0 2006.201.18:55:22.21#ibcon#about to write, iclass 34, count 0 2006.201.18:55:22.21#ibcon#wrote, iclass 34, count 0 2006.201.18:55:22.21#ibcon#about to read 3, iclass 34, count 0 2006.201.18:55:22.26#ibcon#read 3, iclass 34, count 0 2006.201.18:55:22.26#ibcon#about to read 4, iclass 34, count 0 2006.201.18:55:22.26#ibcon#read 4, iclass 34, count 0 2006.201.18:55:22.26#ibcon#about to read 5, iclass 34, count 0 2006.201.18:55:22.26#ibcon#read 5, iclass 34, count 0 2006.201.18:55:22.26#ibcon#about to read 6, iclass 34, count 0 2006.201.18:55:22.26#ibcon#read 6, iclass 34, count 0 2006.201.18:55:22.26#ibcon#end of sib2, iclass 34, count 0 2006.201.18:55:22.26#ibcon#*after write, iclass 34, count 0 2006.201.18:55:22.26#ibcon#*before return 0, iclass 34, count 0 2006.201.18:55:22.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:22.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:22.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:55:22.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:55:22.26$vck44/va=2,7 2006.201.18:55:22.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.18:55:22.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.18:55:22.26#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:22.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:55:22.30#abcon#<5=/04 1.1 2.0 20.501001002.1\r\n> 2006.201.18:55:22.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:55:22.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:55:22.31#ibcon#enter wrdev, iclass 37, count 2 2006.201.18:55:22.31#ibcon#first serial, iclass 37, count 2 2006.201.18:55:22.31#ibcon#enter sib2, iclass 37, count 2 2006.201.18:55:22.31#ibcon#flushed, iclass 37, count 2 2006.201.18:55:22.31#ibcon#about to write, iclass 37, count 2 2006.201.18:55:22.31#ibcon#wrote, iclass 37, count 2 2006.201.18:55:22.31#ibcon#about to read 3, iclass 37, count 2 2006.201.18:55:22.32#abcon#{5=INTERFACE CLEAR} 2006.201.18:55:22.33#ibcon#read 3, iclass 37, count 2 2006.201.18:55:22.33#ibcon#about to read 4, iclass 37, count 2 2006.201.18:55:22.33#ibcon#read 4, iclass 37, count 2 2006.201.18:55:22.33#ibcon#about to read 5, iclass 37, count 2 2006.201.18:55:22.33#ibcon#read 5, iclass 37, count 2 2006.201.18:55:22.33#ibcon#about to read 6, iclass 37, count 2 2006.201.18:55:22.33#ibcon#read 6, iclass 37, count 2 2006.201.18:55:22.33#ibcon#end of sib2, iclass 37, count 2 2006.201.18:55:22.33#ibcon#*mode == 0, iclass 37, count 2 2006.201.18:55:22.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.18:55:22.33#ibcon#[25=AT02-07\r\n] 2006.201.18:55:22.33#ibcon#*before write, iclass 37, count 2 2006.201.18:55:22.33#ibcon#enter sib2, iclass 37, count 2 2006.201.18:55:22.33#ibcon#flushed, iclass 37, count 2 2006.201.18:55:22.33#ibcon#about to write, iclass 37, count 2 2006.201.18:55:22.33#ibcon#wrote, iclass 37, count 2 2006.201.18:55:22.33#ibcon#about to read 3, iclass 37, count 2 2006.201.18:55:22.36#ibcon#read 3, iclass 37, count 2 2006.201.18:55:22.36#ibcon#about to read 4, iclass 37, count 2 2006.201.18:55:22.36#ibcon#read 4, iclass 37, count 2 2006.201.18:55:22.36#ibcon#about to read 5, iclass 37, count 2 2006.201.18:55:22.36#ibcon#read 5, iclass 37, count 2 2006.201.18:55:22.36#ibcon#about to read 6, iclass 37, count 2 2006.201.18:55:22.36#ibcon#read 6, iclass 37, count 2 2006.201.18:55:22.36#ibcon#end of sib2, iclass 37, count 2 2006.201.18:55:22.36#ibcon#*after write, iclass 37, count 2 2006.201.18:55:22.36#ibcon#*before return 0, iclass 37, count 2 2006.201.18:55:22.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:55:22.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.18:55:22.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.18:55:22.36#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:22.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:55:22.38#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:55:22.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:55:22.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:55:22.48#ibcon#enter wrdev, iclass 37, count 0 2006.201.18:55:22.48#ibcon#first serial, iclass 37, count 0 2006.201.18:55:22.48#ibcon#enter sib2, iclass 37, count 0 2006.201.18:55:22.48#ibcon#flushed, iclass 37, count 0 2006.201.18:55:22.48#ibcon#about to write, iclass 37, count 0 2006.201.18:55:22.48#ibcon#wrote, iclass 37, count 0 2006.201.18:55:22.48#ibcon#about to read 3, iclass 37, count 0 2006.201.18:55:22.51#ibcon#read 3, iclass 37, count 0 2006.201.18:55:22.51#ibcon#about to read 4, iclass 37, count 0 2006.201.18:55:22.51#ibcon#read 4, iclass 37, count 0 2006.201.18:55:22.51#ibcon#about to read 5, iclass 37, count 0 2006.201.18:55:22.51#ibcon#read 5, iclass 37, count 0 2006.201.18:55:22.51#ibcon#about to read 6, iclass 37, count 0 2006.201.18:55:22.51#ibcon#read 6, iclass 37, count 0 2006.201.18:55:22.51#ibcon#end of sib2, iclass 37, count 0 2006.201.18:55:22.51#ibcon#*mode == 0, iclass 37, count 0 2006.201.18:55:22.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.18:55:22.51#ibcon#[25=USB\r\n] 2006.201.18:55:22.51#ibcon#*before write, iclass 37, count 0 2006.201.18:55:22.51#ibcon#enter sib2, iclass 37, count 0 2006.201.18:55:22.51#ibcon#flushed, iclass 37, count 0 2006.201.18:55:22.51#ibcon#about to write, iclass 37, count 0 2006.201.18:55:22.51#ibcon#wrote, iclass 37, count 0 2006.201.18:55:22.51#ibcon#about to read 3, iclass 37, count 0 2006.201.18:55:22.54#ibcon#read 3, iclass 37, count 0 2006.201.18:55:22.54#ibcon#about to read 4, iclass 37, count 0 2006.201.18:55:22.54#ibcon#read 4, iclass 37, count 0 2006.201.18:55:22.54#ibcon#about to read 5, iclass 37, count 0 2006.201.18:55:22.54#ibcon#read 5, iclass 37, count 0 2006.201.18:55:22.54#ibcon#about to read 6, iclass 37, count 0 2006.201.18:55:22.54#ibcon#read 6, iclass 37, count 0 2006.201.18:55:22.54#ibcon#end of sib2, iclass 37, count 0 2006.201.18:55:22.54#ibcon#*after write, iclass 37, count 0 2006.201.18:55:22.54#ibcon#*before return 0, iclass 37, count 0 2006.201.18:55:22.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:55:22.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.18:55:22.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.18:55:22.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.18:55:22.54$vck44/valo=3,564.99 2006.201.18:55:22.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.18:55:22.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.18:55:22.54#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:22.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:22.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:22.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:22.54#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:55:22.54#ibcon#first serial, iclass 4, count 0 2006.201.18:55:22.54#ibcon#enter sib2, iclass 4, count 0 2006.201.18:55:22.54#ibcon#flushed, iclass 4, count 0 2006.201.18:55:22.54#ibcon#about to write, iclass 4, count 0 2006.201.18:55:22.54#ibcon#wrote, iclass 4, count 0 2006.201.18:55:22.54#ibcon#about to read 3, iclass 4, count 0 2006.201.18:55:22.56#ibcon#read 3, iclass 4, count 0 2006.201.18:55:22.56#ibcon#about to read 4, iclass 4, count 0 2006.201.18:55:22.56#ibcon#read 4, iclass 4, count 0 2006.201.18:55:22.56#ibcon#about to read 5, iclass 4, count 0 2006.201.18:55:22.56#ibcon#read 5, iclass 4, count 0 2006.201.18:55:22.56#ibcon#about to read 6, iclass 4, count 0 2006.201.18:55:22.56#ibcon#read 6, iclass 4, count 0 2006.201.18:55:22.56#ibcon#end of sib2, iclass 4, count 0 2006.201.18:55:22.56#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:55:22.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:55:22.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.18:55:22.56#ibcon#*before write, iclass 4, count 0 2006.201.18:55:22.56#ibcon#enter sib2, iclass 4, count 0 2006.201.18:55:22.56#ibcon#flushed, iclass 4, count 0 2006.201.18:55:22.56#ibcon#about to write, iclass 4, count 0 2006.201.18:55:22.56#ibcon#wrote, iclass 4, count 0 2006.201.18:55:22.56#ibcon#about to read 3, iclass 4, count 0 2006.201.18:55:22.60#ibcon#read 3, iclass 4, count 0 2006.201.18:55:22.60#ibcon#about to read 4, iclass 4, count 0 2006.201.18:55:22.60#ibcon#read 4, iclass 4, count 0 2006.201.18:55:22.60#ibcon#about to read 5, iclass 4, count 0 2006.201.18:55:22.60#ibcon#read 5, iclass 4, count 0 2006.201.18:55:22.60#ibcon#about to read 6, iclass 4, count 0 2006.201.18:55:22.60#ibcon#read 6, iclass 4, count 0 2006.201.18:55:22.60#ibcon#end of sib2, iclass 4, count 0 2006.201.18:55:22.60#ibcon#*after write, iclass 4, count 0 2006.201.18:55:22.60#ibcon#*before return 0, iclass 4, count 0 2006.201.18:55:22.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:22.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:22.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:55:22.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:55:22.60$vck44/va=3,8 2006.201.18:55:22.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.18:55:22.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.18:55:22.60#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:22.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:22.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:22.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:22.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.18:55:22.66#ibcon#first serial, iclass 6, count 2 2006.201.18:55:22.66#ibcon#enter sib2, iclass 6, count 2 2006.201.18:55:22.66#ibcon#flushed, iclass 6, count 2 2006.201.18:55:22.66#ibcon#about to write, iclass 6, count 2 2006.201.18:55:22.66#ibcon#wrote, iclass 6, count 2 2006.201.18:55:22.66#ibcon#about to read 3, iclass 6, count 2 2006.201.18:55:22.68#ibcon#read 3, iclass 6, count 2 2006.201.18:55:22.68#ibcon#about to read 4, iclass 6, count 2 2006.201.18:55:22.68#ibcon#read 4, iclass 6, count 2 2006.201.18:55:22.68#ibcon#about to read 5, iclass 6, count 2 2006.201.18:55:22.68#ibcon#read 5, iclass 6, count 2 2006.201.18:55:22.68#ibcon#about to read 6, iclass 6, count 2 2006.201.18:55:22.68#ibcon#read 6, iclass 6, count 2 2006.201.18:55:22.68#ibcon#end of sib2, iclass 6, count 2 2006.201.18:55:22.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.18:55:22.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.18:55:22.68#ibcon#[25=AT03-08\r\n] 2006.201.18:55:22.68#ibcon#*before write, iclass 6, count 2 2006.201.18:55:22.68#ibcon#enter sib2, iclass 6, count 2 2006.201.18:55:22.68#ibcon#flushed, iclass 6, count 2 2006.201.18:55:22.68#ibcon#about to write, iclass 6, count 2 2006.201.18:55:22.68#ibcon#wrote, iclass 6, count 2 2006.201.18:55:22.68#ibcon#about to read 3, iclass 6, count 2 2006.201.18:55:22.71#ibcon#read 3, iclass 6, count 2 2006.201.18:55:22.71#ibcon#about to read 4, iclass 6, count 2 2006.201.18:55:22.71#ibcon#read 4, iclass 6, count 2 2006.201.18:55:22.71#ibcon#about to read 5, iclass 6, count 2 2006.201.18:55:22.71#ibcon#read 5, iclass 6, count 2 2006.201.18:55:22.71#ibcon#about to read 6, iclass 6, count 2 2006.201.18:55:22.71#ibcon#read 6, iclass 6, count 2 2006.201.18:55:22.71#ibcon#end of sib2, iclass 6, count 2 2006.201.18:55:22.71#ibcon#*after write, iclass 6, count 2 2006.201.18:55:22.71#ibcon#*before return 0, iclass 6, count 2 2006.201.18:55:22.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:22.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:22.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.18:55:22.71#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:22.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:22.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:22.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:22.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:55:22.83#ibcon#first serial, iclass 6, count 0 2006.201.18:55:22.83#ibcon#enter sib2, iclass 6, count 0 2006.201.18:55:22.83#ibcon#flushed, iclass 6, count 0 2006.201.18:55:22.83#ibcon#about to write, iclass 6, count 0 2006.201.18:55:22.83#ibcon#wrote, iclass 6, count 0 2006.201.18:55:22.83#ibcon#about to read 3, iclass 6, count 0 2006.201.18:55:22.85#ibcon#read 3, iclass 6, count 0 2006.201.18:55:22.85#ibcon#about to read 4, iclass 6, count 0 2006.201.18:55:22.85#ibcon#read 4, iclass 6, count 0 2006.201.18:55:22.85#ibcon#about to read 5, iclass 6, count 0 2006.201.18:55:22.85#ibcon#read 5, iclass 6, count 0 2006.201.18:55:22.85#ibcon#about to read 6, iclass 6, count 0 2006.201.18:55:22.85#ibcon#read 6, iclass 6, count 0 2006.201.18:55:22.85#ibcon#end of sib2, iclass 6, count 0 2006.201.18:55:22.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:55:22.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:55:22.85#ibcon#[25=USB\r\n] 2006.201.18:55:22.85#ibcon#*before write, iclass 6, count 0 2006.201.18:55:22.85#ibcon#enter sib2, iclass 6, count 0 2006.201.18:55:22.85#ibcon#flushed, iclass 6, count 0 2006.201.18:55:22.85#ibcon#about to write, iclass 6, count 0 2006.201.18:55:22.85#ibcon#wrote, iclass 6, count 0 2006.201.18:55:22.85#ibcon#about to read 3, iclass 6, count 0 2006.201.18:55:22.88#ibcon#read 3, iclass 6, count 0 2006.201.18:55:22.88#ibcon#about to read 4, iclass 6, count 0 2006.201.18:55:22.88#ibcon#read 4, iclass 6, count 0 2006.201.18:55:22.88#ibcon#about to read 5, iclass 6, count 0 2006.201.18:55:22.88#ibcon#read 5, iclass 6, count 0 2006.201.18:55:22.88#ibcon#about to read 6, iclass 6, count 0 2006.201.18:55:22.88#ibcon#read 6, iclass 6, count 0 2006.201.18:55:22.88#ibcon#end of sib2, iclass 6, count 0 2006.201.18:55:22.88#ibcon#*after write, iclass 6, count 0 2006.201.18:55:22.88#ibcon#*before return 0, iclass 6, count 0 2006.201.18:55:22.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:22.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:22.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:55:22.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:55:22.88$vck44/valo=4,624.99 2006.201.18:55:22.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.18:55:22.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.18:55:22.88#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:22.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:22.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:22.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:22.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:55:22.88#ibcon#first serial, iclass 10, count 0 2006.201.18:55:22.88#ibcon#enter sib2, iclass 10, count 0 2006.201.18:55:22.88#ibcon#flushed, iclass 10, count 0 2006.201.18:55:22.88#ibcon#about to write, iclass 10, count 0 2006.201.18:55:22.88#ibcon#wrote, iclass 10, count 0 2006.201.18:55:22.88#ibcon#about to read 3, iclass 10, count 0 2006.201.18:55:22.90#ibcon#read 3, iclass 10, count 0 2006.201.18:55:22.90#ibcon#about to read 4, iclass 10, count 0 2006.201.18:55:22.90#ibcon#read 4, iclass 10, count 0 2006.201.18:55:22.90#ibcon#about to read 5, iclass 10, count 0 2006.201.18:55:22.90#ibcon#read 5, iclass 10, count 0 2006.201.18:55:22.90#ibcon#about to read 6, iclass 10, count 0 2006.201.18:55:22.90#ibcon#read 6, iclass 10, count 0 2006.201.18:55:22.90#ibcon#end of sib2, iclass 10, count 0 2006.201.18:55:22.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:55:22.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:55:22.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.18:55:22.90#ibcon#*before write, iclass 10, count 0 2006.201.18:55:22.90#ibcon#enter sib2, iclass 10, count 0 2006.201.18:55:22.90#ibcon#flushed, iclass 10, count 0 2006.201.18:55:22.90#ibcon#about to write, iclass 10, count 0 2006.201.18:55:22.90#ibcon#wrote, iclass 10, count 0 2006.201.18:55:22.90#ibcon#about to read 3, iclass 10, count 0 2006.201.18:55:22.94#ibcon#read 3, iclass 10, count 0 2006.201.18:55:22.94#ibcon#about to read 4, iclass 10, count 0 2006.201.18:55:22.94#ibcon#read 4, iclass 10, count 0 2006.201.18:55:22.94#ibcon#about to read 5, iclass 10, count 0 2006.201.18:55:22.94#ibcon#read 5, iclass 10, count 0 2006.201.18:55:22.94#ibcon#about to read 6, iclass 10, count 0 2006.201.18:55:22.94#ibcon#read 6, iclass 10, count 0 2006.201.18:55:22.94#ibcon#end of sib2, iclass 10, count 0 2006.201.18:55:22.94#ibcon#*after write, iclass 10, count 0 2006.201.18:55:22.94#ibcon#*before return 0, iclass 10, count 0 2006.201.18:55:22.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:22.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:22.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:55:22.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:55:22.94$vck44/va=4,7 2006.201.18:55:22.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.18:55:22.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.18:55:22.94#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:22.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:23.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:23.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:23.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.18:55:23.00#ibcon#first serial, iclass 12, count 2 2006.201.18:55:23.00#ibcon#enter sib2, iclass 12, count 2 2006.201.18:55:23.00#ibcon#flushed, iclass 12, count 2 2006.201.18:55:23.00#ibcon#about to write, iclass 12, count 2 2006.201.18:55:23.00#ibcon#wrote, iclass 12, count 2 2006.201.18:55:23.00#ibcon#about to read 3, iclass 12, count 2 2006.201.18:55:23.02#ibcon#read 3, iclass 12, count 2 2006.201.18:55:23.02#ibcon#about to read 4, iclass 12, count 2 2006.201.18:55:23.02#ibcon#read 4, iclass 12, count 2 2006.201.18:55:23.02#ibcon#about to read 5, iclass 12, count 2 2006.201.18:55:23.02#ibcon#read 5, iclass 12, count 2 2006.201.18:55:23.02#ibcon#about to read 6, iclass 12, count 2 2006.201.18:55:23.02#ibcon#read 6, iclass 12, count 2 2006.201.18:55:23.02#ibcon#end of sib2, iclass 12, count 2 2006.201.18:55:23.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.18:55:23.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.18:55:23.02#ibcon#[25=AT04-07\r\n] 2006.201.18:55:23.02#ibcon#*before write, iclass 12, count 2 2006.201.18:55:23.02#ibcon#enter sib2, iclass 12, count 2 2006.201.18:55:23.02#ibcon#flushed, iclass 12, count 2 2006.201.18:55:23.02#ibcon#about to write, iclass 12, count 2 2006.201.18:55:23.02#ibcon#wrote, iclass 12, count 2 2006.201.18:55:23.02#ibcon#about to read 3, iclass 12, count 2 2006.201.18:55:23.05#ibcon#read 3, iclass 12, count 2 2006.201.18:55:23.05#ibcon#about to read 4, iclass 12, count 2 2006.201.18:55:23.05#ibcon#read 4, iclass 12, count 2 2006.201.18:55:23.05#ibcon#about to read 5, iclass 12, count 2 2006.201.18:55:23.05#ibcon#read 5, iclass 12, count 2 2006.201.18:55:23.05#ibcon#about to read 6, iclass 12, count 2 2006.201.18:55:23.05#ibcon#read 6, iclass 12, count 2 2006.201.18:55:23.05#ibcon#end of sib2, iclass 12, count 2 2006.201.18:55:23.05#ibcon#*after write, iclass 12, count 2 2006.201.18:55:23.05#ibcon#*before return 0, iclass 12, count 2 2006.201.18:55:23.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:23.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:23.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.18:55:23.05#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:23.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:23.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:23.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:23.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:55:23.17#ibcon#first serial, iclass 12, count 0 2006.201.18:55:23.17#ibcon#enter sib2, iclass 12, count 0 2006.201.18:55:23.17#ibcon#flushed, iclass 12, count 0 2006.201.18:55:23.17#ibcon#about to write, iclass 12, count 0 2006.201.18:55:23.17#ibcon#wrote, iclass 12, count 0 2006.201.18:55:23.17#ibcon#about to read 3, iclass 12, count 0 2006.201.18:55:23.19#ibcon#read 3, iclass 12, count 0 2006.201.18:55:23.19#ibcon#about to read 4, iclass 12, count 0 2006.201.18:55:23.19#ibcon#read 4, iclass 12, count 0 2006.201.18:55:23.19#ibcon#about to read 5, iclass 12, count 0 2006.201.18:55:23.19#ibcon#read 5, iclass 12, count 0 2006.201.18:55:23.19#ibcon#about to read 6, iclass 12, count 0 2006.201.18:55:23.19#ibcon#read 6, iclass 12, count 0 2006.201.18:55:23.19#ibcon#end of sib2, iclass 12, count 0 2006.201.18:55:23.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:55:23.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:55:23.19#ibcon#[25=USB\r\n] 2006.201.18:55:23.19#ibcon#*before write, iclass 12, count 0 2006.201.18:55:23.19#ibcon#enter sib2, iclass 12, count 0 2006.201.18:55:23.19#ibcon#flushed, iclass 12, count 0 2006.201.18:55:23.19#ibcon#about to write, iclass 12, count 0 2006.201.18:55:23.19#ibcon#wrote, iclass 12, count 0 2006.201.18:55:23.19#ibcon#about to read 3, iclass 12, count 0 2006.201.18:55:23.22#ibcon#read 3, iclass 12, count 0 2006.201.18:55:23.22#ibcon#about to read 4, iclass 12, count 0 2006.201.18:55:23.22#ibcon#read 4, iclass 12, count 0 2006.201.18:55:23.22#ibcon#about to read 5, iclass 12, count 0 2006.201.18:55:23.22#ibcon#read 5, iclass 12, count 0 2006.201.18:55:23.22#ibcon#about to read 6, iclass 12, count 0 2006.201.18:55:23.22#ibcon#read 6, iclass 12, count 0 2006.201.18:55:23.22#ibcon#end of sib2, iclass 12, count 0 2006.201.18:55:23.22#ibcon#*after write, iclass 12, count 0 2006.201.18:55:23.22#ibcon#*before return 0, iclass 12, count 0 2006.201.18:55:23.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:23.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:23.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:55:23.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:55:23.22$vck44/valo=5,734.99 2006.201.18:55:23.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.18:55:23.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.18:55:23.22#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:23.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:23.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:23.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:23.22#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:55:23.22#ibcon#first serial, iclass 14, count 0 2006.201.18:55:23.22#ibcon#enter sib2, iclass 14, count 0 2006.201.18:55:23.22#ibcon#flushed, iclass 14, count 0 2006.201.18:55:23.22#ibcon#about to write, iclass 14, count 0 2006.201.18:55:23.22#ibcon#wrote, iclass 14, count 0 2006.201.18:55:23.22#ibcon#about to read 3, iclass 14, count 0 2006.201.18:55:23.24#ibcon#read 3, iclass 14, count 0 2006.201.18:55:23.24#ibcon#about to read 4, iclass 14, count 0 2006.201.18:55:23.24#ibcon#read 4, iclass 14, count 0 2006.201.18:55:23.24#ibcon#about to read 5, iclass 14, count 0 2006.201.18:55:23.24#ibcon#read 5, iclass 14, count 0 2006.201.18:55:23.24#ibcon#about to read 6, iclass 14, count 0 2006.201.18:55:23.24#ibcon#read 6, iclass 14, count 0 2006.201.18:55:23.24#ibcon#end of sib2, iclass 14, count 0 2006.201.18:55:23.24#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:55:23.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:55:23.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.18:55:23.24#ibcon#*before write, iclass 14, count 0 2006.201.18:55:23.24#ibcon#enter sib2, iclass 14, count 0 2006.201.18:55:23.24#ibcon#flushed, iclass 14, count 0 2006.201.18:55:23.24#ibcon#about to write, iclass 14, count 0 2006.201.18:55:23.24#ibcon#wrote, iclass 14, count 0 2006.201.18:55:23.24#ibcon#about to read 3, iclass 14, count 0 2006.201.18:55:23.28#ibcon#read 3, iclass 14, count 0 2006.201.18:55:23.28#ibcon#about to read 4, iclass 14, count 0 2006.201.18:55:23.28#ibcon#read 4, iclass 14, count 0 2006.201.18:55:23.28#ibcon#about to read 5, iclass 14, count 0 2006.201.18:55:23.28#ibcon#read 5, iclass 14, count 0 2006.201.18:55:23.28#ibcon#about to read 6, iclass 14, count 0 2006.201.18:55:23.28#ibcon#read 6, iclass 14, count 0 2006.201.18:55:23.28#ibcon#end of sib2, iclass 14, count 0 2006.201.18:55:23.28#ibcon#*after write, iclass 14, count 0 2006.201.18:55:23.28#ibcon#*before return 0, iclass 14, count 0 2006.201.18:55:23.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:23.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:23.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:55:23.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:55:23.28$vck44/va=5,4 2006.201.18:55:23.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.18:55:23.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.18:55:23.28#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:23.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:23.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:23.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:23.34#ibcon#enter wrdev, iclass 16, count 2 2006.201.18:55:23.34#ibcon#first serial, iclass 16, count 2 2006.201.18:55:23.34#ibcon#enter sib2, iclass 16, count 2 2006.201.18:55:23.34#ibcon#flushed, iclass 16, count 2 2006.201.18:55:23.34#ibcon#about to write, iclass 16, count 2 2006.201.18:55:23.34#ibcon#wrote, iclass 16, count 2 2006.201.18:55:23.34#ibcon#about to read 3, iclass 16, count 2 2006.201.18:55:23.36#ibcon#read 3, iclass 16, count 2 2006.201.18:55:23.36#ibcon#about to read 4, iclass 16, count 2 2006.201.18:55:23.36#ibcon#read 4, iclass 16, count 2 2006.201.18:55:23.36#ibcon#about to read 5, iclass 16, count 2 2006.201.18:55:23.36#ibcon#read 5, iclass 16, count 2 2006.201.18:55:23.36#ibcon#about to read 6, iclass 16, count 2 2006.201.18:55:23.36#ibcon#read 6, iclass 16, count 2 2006.201.18:55:23.36#ibcon#end of sib2, iclass 16, count 2 2006.201.18:55:23.36#ibcon#*mode == 0, iclass 16, count 2 2006.201.18:55:23.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.18:55:23.36#ibcon#[25=AT05-04\r\n] 2006.201.18:55:23.36#ibcon#*before write, iclass 16, count 2 2006.201.18:55:23.36#ibcon#enter sib2, iclass 16, count 2 2006.201.18:55:23.36#ibcon#flushed, iclass 16, count 2 2006.201.18:55:23.36#ibcon#about to write, iclass 16, count 2 2006.201.18:55:23.36#ibcon#wrote, iclass 16, count 2 2006.201.18:55:23.36#ibcon#about to read 3, iclass 16, count 2 2006.201.18:55:23.39#ibcon#read 3, iclass 16, count 2 2006.201.18:55:23.39#ibcon#about to read 4, iclass 16, count 2 2006.201.18:55:23.39#ibcon#read 4, iclass 16, count 2 2006.201.18:55:23.39#ibcon#about to read 5, iclass 16, count 2 2006.201.18:55:23.39#ibcon#read 5, iclass 16, count 2 2006.201.18:55:23.39#ibcon#about to read 6, iclass 16, count 2 2006.201.18:55:23.39#ibcon#read 6, iclass 16, count 2 2006.201.18:55:23.39#ibcon#end of sib2, iclass 16, count 2 2006.201.18:55:23.39#ibcon#*after write, iclass 16, count 2 2006.201.18:55:23.39#ibcon#*before return 0, iclass 16, count 2 2006.201.18:55:23.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:23.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:23.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.18:55:23.39#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:23.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:23.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:23.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:23.51#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:55:23.51#ibcon#first serial, iclass 16, count 0 2006.201.18:55:23.51#ibcon#enter sib2, iclass 16, count 0 2006.201.18:55:23.51#ibcon#flushed, iclass 16, count 0 2006.201.18:55:23.51#ibcon#about to write, iclass 16, count 0 2006.201.18:55:23.51#ibcon#wrote, iclass 16, count 0 2006.201.18:55:23.51#ibcon#about to read 3, iclass 16, count 0 2006.201.18:55:23.53#ibcon#read 3, iclass 16, count 0 2006.201.18:55:23.53#ibcon#about to read 4, iclass 16, count 0 2006.201.18:55:23.53#ibcon#read 4, iclass 16, count 0 2006.201.18:55:23.53#ibcon#about to read 5, iclass 16, count 0 2006.201.18:55:23.53#ibcon#read 5, iclass 16, count 0 2006.201.18:55:23.53#ibcon#about to read 6, iclass 16, count 0 2006.201.18:55:23.53#ibcon#read 6, iclass 16, count 0 2006.201.18:55:23.53#ibcon#end of sib2, iclass 16, count 0 2006.201.18:55:23.53#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:55:23.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:55:23.53#ibcon#[25=USB\r\n] 2006.201.18:55:23.53#ibcon#*before write, iclass 16, count 0 2006.201.18:55:23.53#ibcon#enter sib2, iclass 16, count 0 2006.201.18:55:23.53#ibcon#flushed, iclass 16, count 0 2006.201.18:55:23.53#ibcon#about to write, iclass 16, count 0 2006.201.18:55:23.53#ibcon#wrote, iclass 16, count 0 2006.201.18:55:23.53#ibcon#about to read 3, iclass 16, count 0 2006.201.18:55:23.56#ibcon#read 3, iclass 16, count 0 2006.201.18:55:23.56#ibcon#about to read 4, iclass 16, count 0 2006.201.18:55:23.56#ibcon#read 4, iclass 16, count 0 2006.201.18:55:23.56#ibcon#about to read 5, iclass 16, count 0 2006.201.18:55:23.56#ibcon#read 5, iclass 16, count 0 2006.201.18:55:23.56#ibcon#about to read 6, iclass 16, count 0 2006.201.18:55:23.56#ibcon#read 6, iclass 16, count 0 2006.201.18:55:23.56#ibcon#end of sib2, iclass 16, count 0 2006.201.18:55:23.56#ibcon#*after write, iclass 16, count 0 2006.201.18:55:23.56#ibcon#*before return 0, iclass 16, count 0 2006.201.18:55:23.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:23.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:23.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:55:23.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:55:23.56$vck44/valo=6,814.99 2006.201.18:55:23.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.18:55:23.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.18:55:23.56#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:23.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:23.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:23.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:23.56#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:55:23.56#ibcon#first serial, iclass 18, count 0 2006.201.18:55:23.56#ibcon#enter sib2, iclass 18, count 0 2006.201.18:55:23.56#ibcon#flushed, iclass 18, count 0 2006.201.18:55:23.56#ibcon#about to write, iclass 18, count 0 2006.201.18:55:23.56#ibcon#wrote, iclass 18, count 0 2006.201.18:55:23.56#ibcon#about to read 3, iclass 18, count 0 2006.201.18:55:23.58#ibcon#read 3, iclass 18, count 0 2006.201.18:55:23.58#ibcon#about to read 4, iclass 18, count 0 2006.201.18:55:23.58#ibcon#read 4, iclass 18, count 0 2006.201.18:55:23.58#ibcon#about to read 5, iclass 18, count 0 2006.201.18:55:23.58#ibcon#read 5, iclass 18, count 0 2006.201.18:55:23.58#ibcon#about to read 6, iclass 18, count 0 2006.201.18:55:23.58#ibcon#read 6, iclass 18, count 0 2006.201.18:55:23.58#ibcon#end of sib2, iclass 18, count 0 2006.201.18:55:23.58#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:55:23.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:55:23.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.18:55:23.58#ibcon#*before write, iclass 18, count 0 2006.201.18:55:23.58#ibcon#enter sib2, iclass 18, count 0 2006.201.18:55:23.58#ibcon#flushed, iclass 18, count 0 2006.201.18:55:23.58#ibcon#about to write, iclass 18, count 0 2006.201.18:55:23.58#ibcon#wrote, iclass 18, count 0 2006.201.18:55:23.58#ibcon#about to read 3, iclass 18, count 0 2006.201.18:55:23.62#ibcon#read 3, iclass 18, count 0 2006.201.18:55:23.62#ibcon#about to read 4, iclass 18, count 0 2006.201.18:55:23.62#ibcon#read 4, iclass 18, count 0 2006.201.18:55:23.62#ibcon#about to read 5, iclass 18, count 0 2006.201.18:55:23.62#ibcon#read 5, iclass 18, count 0 2006.201.18:55:23.62#ibcon#about to read 6, iclass 18, count 0 2006.201.18:55:23.62#ibcon#read 6, iclass 18, count 0 2006.201.18:55:23.62#ibcon#end of sib2, iclass 18, count 0 2006.201.18:55:23.62#ibcon#*after write, iclass 18, count 0 2006.201.18:55:23.62#ibcon#*before return 0, iclass 18, count 0 2006.201.18:55:23.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:23.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:23.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:55:23.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:55:23.62$vck44/va=6,5 2006.201.18:55:23.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.18:55:23.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.18:55:23.62#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:23.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:23.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:23.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:23.68#ibcon#enter wrdev, iclass 20, count 2 2006.201.18:55:23.68#ibcon#first serial, iclass 20, count 2 2006.201.18:55:23.68#ibcon#enter sib2, iclass 20, count 2 2006.201.18:55:23.68#ibcon#flushed, iclass 20, count 2 2006.201.18:55:23.68#ibcon#about to write, iclass 20, count 2 2006.201.18:55:23.68#ibcon#wrote, iclass 20, count 2 2006.201.18:55:23.68#ibcon#about to read 3, iclass 20, count 2 2006.201.18:55:23.70#ibcon#read 3, iclass 20, count 2 2006.201.18:55:23.70#ibcon#about to read 4, iclass 20, count 2 2006.201.18:55:23.70#ibcon#read 4, iclass 20, count 2 2006.201.18:55:23.70#ibcon#about to read 5, iclass 20, count 2 2006.201.18:55:23.70#ibcon#read 5, iclass 20, count 2 2006.201.18:55:23.70#ibcon#about to read 6, iclass 20, count 2 2006.201.18:55:23.70#ibcon#read 6, iclass 20, count 2 2006.201.18:55:23.70#ibcon#end of sib2, iclass 20, count 2 2006.201.18:55:23.70#ibcon#*mode == 0, iclass 20, count 2 2006.201.18:55:23.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.18:55:23.70#ibcon#[25=AT06-05\r\n] 2006.201.18:55:23.70#ibcon#*before write, iclass 20, count 2 2006.201.18:55:23.70#ibcon#enter sib2, iclass 20, count 2 2006.201.18:55:23.70#ibcon#flushed, iclass 20, count 2 2006.201.18:55:23.70#ibcon#about to write, iclass 20, count 2 2006.201.18:55:23.70#ibcon#wrote, iclass 20, count 2 2006.201.18:55:23.70#ibcon#about to read 3, iclass 20, count 2 2006.201.18:55:23.73#ibcon#read 3, iclass 20, count 2 2006.201.18:55:23.73#ibcon#about to read 4, iclass 20, count 2 2006.201.18:55:23.73#ibcon#read 4, iclass 20, count 2 2006.201.18:55:23.73#ibcon#about to read 5, iclass 20, count 2 2006.201.18:55:23.73#ibcon#read 5, iclass 20, count 2 2006.201.18:55:23.73#ibcon#about to read 6, iclass 20, count 2 2006.201.18:55:23.73#ibcon#read 6, iclass 20, count 2 2006.201.18:55:23.73#ibcon#end of sib2, iclass 20, count 2 2006.201.18:55:23.73#ibcon#*after write, iclass 20, count 2 2006.201.18:55:23.73#ibcon#*before return 0, iclass 20, count 2 2006.201.18:55:23.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:23.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:23.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.18:55:23.73#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:23.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:23.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:23.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:23.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.18:55:23.85#ibcon#first serial, iclass 20, count 0 2006.201.18:55:23.85#ibcon#enter sib2, iclass 20, count 0 2006.201.18:55:23.85#ibcon#flushed, iclass 20, count 0 2006.201.18:55:23.85#ibcon#about to write, iclass 20, count 0 2006.201.18:55:23.85#ibcon#wrote, iclass 20, count 0 2006.201.18:55:23.85#ibcon#about to read 3, iclass 20, count 0 2006.201.18:55:23.87#ibcon#read 3, iclass 20, count 0 2006.201.18:55:23.87#ibcon#about to read 4, iclass 20, count 0 2006.201.18:55:23.87#ibcon#read 4, iclass 20, count 0 2006.201.18:55:23.87#ibcon#about to read 5, iclass 20, count 0 2006.201.18:55:23.87#ibcon#read 5, iclass 20, count 0 2006.201.18:55:23.87#ibcon#about to read 6, iclass 20, count 0 2006.201.18:55:23.87#ibcon#read 6, iclass 20, count 0 2006.201.18:55:23.87#ibcon#end of sib2, iclass 20, count 0 2006.201.18:55:23.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.18:55:23.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.18:55:23.87#ibcon#[25=USB\r\n] 2006.201.18:55:23.87#ibcon#*before write, iclass 20, count 0 2006.201.18:55:23.87#ibcon#enter sib2, iclass 20, count 0 2006.201.18:55:23.87#ibcon#flushed, iclass 20, count 0 2006.201.18:55:23.87#ibcon#about to write, iclass 20, count 0 2006.201.18:55:23.87#ibcon#wrote, iclass 20, count 0 2006.201.18:55:23.87#ibcon#about to read 3, iclass 20, count 0 2006.201.18:55:23.90#ibcon#read 3, iclass 20, count 0 2006.201.18:55:23.90#ibcon#about to read 4, iclass 20, count 0 2006.201.18:55:23.90#ibcon#read 4, iclass 20, count 0 2006.201.18:55:23.90#ibcon#about to read 5, iclass 20, count 0 2006.201.18:55:23.90#ibcon#read 5, iclass 20, count 0 2006.201.18:55:23.90#ibcon#about to read 6, iclass 20, count 0 2006.201.18:55:23.90#ibcon#read 6, iclass 20, count 0 2006.201.18:55:23.90#ibcon#end of sib2, iclass 20, count 0 2006.201.18:55:23.90#ibcon#*after write, iclass 20, count 0 2006.201.18:55:23.90#ibcon#*before return 0, iclass 20, count 0 2006.201.18:55:23.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:23.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:23.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.18:55:23.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.18:55:23.90$vck44/valo=7,864.99 2006.201.18:55:23.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.18:55:23.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.18:55:23.90#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:23.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:23.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:23.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:23.90#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:55:23.90#ibcon#first serial, iclass 22, count 0 2006.201.18:55:23.90#ibcon#enter sib2, iclass 22, count 0 2006.201.18:55:23.90#ibcon#flushed, iclass 22, count 0 2006.201.18:55:23.90#ibcon#about to write, iclass 22, count 0 2006.201.18:55:23.90#ibcon#wrote, iclass 22, count 0 2006.201.18:55:23.90#ibcon#about to read 3, iclass 22, count 0 2006.201.18:55:23.92#ibcon#read 3, iclass 22, count 0 2006.201.18:55:23.92#ibcon#about to read 4, iclass 22, count 0 2006.201.18:55:23.92#ibcon#read 4, iclass 22, count 0 2006.201.18:55:23.92#ibcon#about to read 5, iclass 22, count 0 2006.201.18:55:23.92#ibcon#read 5, iclass 22, count 0 2006.201.18:55:23.92#ibcon#about to read 6, iclass 22, count 0 2006.201.18:55:23.92#ibcon#read 6, iclass 22, count 0 2006.201.18:55:23.92#ibcon#end of sib2, iclass 22, count 0 2006.201.18:55:23.92#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:55:23.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:55:23.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.18:55:23.92#ibcon#*before write, iclass 22, count 0 2006.201.18:55:23.92#ibcon#enter sib2, iclass 22, count 0 2006.201.18:55:23.92#ibcon#flushed, iclass 22, count 0 2006.201.18:55:23.92#ibcon#about to write, iclass 22, count 0 2006.201.18:55:23.92#ibcon#wrote, iclass 22, count 0 2006.201.18:55:23.92#ibcon#about to read 3, iclass 22, count 0 2006.201.18:55:23.96#ibcon#read 3, iclass 22, count 0 2006.201.18:55:23.96#ibcon#about to read 4, iclass 22, count 0 2006.201.18:55:23.96#ibcon#read 4, iclass 22, count 0 2006.201.18:55:23.96#ibcon#about to read 5, iclass 22, count 0 2006.201.18:55:23.96#ibcon#read 5, iclass 22, count 0 2006.201.18:55:23.96#ibcon#about to read 6, iclass 22, count 0 2006.201.18:55:23.96#ibcon#read 6, iclass 22, count 0 2006.201.18:55:23.96#ibcon#end of sib2, iclass 22, count 0 2006.201.18:55:23.96#ibcon#*after write, iclass 22, count 0 2006.201.18:55:23.96#ibcon#*before return 0, iclass 22, count 0 2006.201.18:55:23.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:23.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:23.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:55:23.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:55:23.96$vck44/va=7,5 2006.201.18:55:23.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.18:55:23.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.18:55:23.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:23.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:24.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:24.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:24.02#ibcon#enter wrdev, iclass 24, count 2 2006.201.18:55:24.02#ibcon#first serial, iclass 24, count 2 2006.201.18:55:24.02#ibcon#enter sib2, iclass 24, count 2 2006.201.18:55:24.02#ibcon#flushed, iclass 24, count 2 2006.201.18:55:24.02#ibcon#about to write, iclass 24, count 2 2006.201.18:55:24.02#ibcon#wrote, iclass 24, count 2 2006.201.18:55:24.02#ibcon#about to read 3, iclass 24, count 2 2006.201.18:55:24.04#ibcon#read 3, iclass 24, count 2 2006.201.18:55:24.04#ibcon#about to read 4, iclass 24, count 2 2006.201.18:55:24.04#ibcon#read 4, iclass 24, count 2 2006.201.18:55:24.04#ibcon#about to read 5, iclass 24, count 2 2006.201.18:55:24.04#ibcon#read 5, iclass 24, count 2 2006.201.18:55:24.04#ibcon#about to read 6, iclass 24, count 2 2006.201.18:55:24.04#ibcon#read 6, iclass 24, count 2 2006.201.18:55:24.04#ibcon#end of sib2, iclass 24, count 2 2006.201.18:55:24.04#ibcon#*mode == 0, iclass 24, count 2 2006.201.18:55:24.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.18:55:24.04#ibcon#[25=AT07-05\r\n] 2006.201.18:55:24.04#ibcon#*before write, iclass 24, count 2 2006.201.18:55:24.04#ibcon#enter sib2, iclass 24, count 2 2006.201.18:55:24.04#ibcon#flushed, iclass 24, count 2 2006.201.18:55:24.04#ibcon#about to write, iclass 24, count 2 2006.201.18:55:24.04#ibcon#wrote, iclass 24, count 2 2006.201.18:55:24.04#ibcon#about to read 3, iclass 24, count 2 2006.201.18:55:24.07#ibcon#read 3, iclass 24, count 2 2006.201.18:55:24.07#ibcon#about to read 4, iclass 24, count 2 2006.201.18:55:24.07#ibcon#read 4, iclass 24, count 2 2006.201.18:55:24.07#ibcon#about to read 5, iclass 24, count 2 2006.201.18:55:24.07#ibcon#read 5, iclass 24, count 2 2006.201.18:55:24.07#ibcon#about to read 6, iclass 24, count 2 2006.201.18:55:24.07#ibcon#read 6, iclass 24, count 2 2006.201.18:55:24.07#ibcon#end of sib2, iclass 24, count 2 2006.201.18:55:24.07#ibcon#*after write, iclass 24, count 2 2006.201.18:55:24.07#ibcon#*before return 0, iclass 24, count 2 2006.201.18:55:24.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:24.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:24.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.18:55:24.07#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:24.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:24.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:24.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:24.19#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:55:24.19#ibcon#first serial, iclass 24, count 0 2006.201.18:55:24.19#ibcon#enter sib2, iclass 24, count 0 2006.201.18:55:24.19#ibcon#flushed, iclass 24, count 0 2006.201.18:55:24.19#ibcon#about to write, iclass 24, count 0 2006.201.18:55:24.19#ibcon#wrote, iclass 24, count 0 2006.201.18:55:24.19#ibcon#about to read 3, iclass 24, count 0 2006.201.18:55:24.21#ibcon#read 3, iclass 24, count 0 2006.201.18:55:24.21#ibcon#about to read 4, iclass 24, count 0 2006.201.18:55:24.21#ibcon#read 4, iclass 24, count 0 2006.201.18:55:24.21#ibcon#about to read 5, iclass 24, count 0 2006.201.18:55:24.21#ibcon#read 5, iclass 24, count 0 2006.201.18:55:24.21#ibcon#about to read 6, iclass 24, count 0 2006.201.18:55:24.21#ibcon#read 6, iclass 24, count 0 2006.201.18:55:24.21#ibcon#end of sib2, iclass 24, count 0 2006.201.18:55:24.21#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:55:24.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:55:24.21#ibcon#[25=USB\r\n] 2006.201.18:55:24.21#ibcon#*before write, iclass 24, count 0 2006.201.18:55:24.21#ibcon#enter sib2, iclass 24, count 0 2006.201.18:55:24.21#ibcon#flushed, iclass 24, count 0 2006.201.18:55:24.21#ibcon#about to write, iclass 24, count 0 2006.201.18:55:24.21#ibcon#wrote, iclass 24, count 0 2006.201.18:55:24.21#ibcon#about to read 3, iclass 24, count 0 2006.201.18:55:24.24#ibcon#read 3, iclass 24, count 0 2006.201.18:55:24.24#ibcon#about to read 4, iclass 24, count 0 2006.201.18:55:24.24#ibcon#read 4, iclass 24, count 0 2006.201.18:55:24.24#ibcon#about to read 5, iclass 24, count 0 2006.201.18:55:24.24#ibcon#read 5, iclass 24, count 0 2006.201.18:55:24.24#ibcon#about to read 6, iclass 24, count 0 2006.201.18:55:24.24#ibcon#read 6, iclass 24, count 0 2006.201.18:55:24.24#ibcon#end of sib2, iclass 24, count 0 2006.201.18:55:24.24#ibcon#*after write, iclass 24, count 0 2006.201.18:55:24.24#ibcon#*before return 0, iclass 24, count 0 2006.201.18:55:24.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:24.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:24.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:55:24.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:55:24.24$vck44/valo=8,884.99 2006.201.18:55:24.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.18:55:24.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.18:55:24.24#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:24.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:24.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:24.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:24.24#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:55:24.24#ibcon#first serial, iclass 26, count 0 2006.201.18:55:24.24#ibcon#enter sib2, iclass 26, count 0 2006.201.18:55:24.24#ibcon#flushed, iclass 26, count 0 2006.201.18:55:24.24#ibcon#about to write, iclass 26, count 0 2006.201.18:55:24.24#ibcon#wrote, iclass 26, count 0 2006.201.18:55:24.24#ibcon#about to read 3, iclass 26, count 0 2006.201.18:55:24.26#ibcon#read 3, iclass 26, count 0 2006.201.18:55:24.26#ibcon#about to read 4, iclass 26, count 0 2006.201.18:55:24.26#ibcon#read 4, iclass 26, count 0 2006.201.18:55:24.26#ibcon#about to read 5, iclass 26, count 0 2006.201.18:55:24.26#ibcon#read 5, iclass 26, count 0 2006.201.18:55:24.26#ibcon#about to read 6, iclass 26, count 0 2006.201.18:55:24.26#ibcon#read 6, iclass 26, count 0 2006.201.18:55:24.26#ibcon#end of sib2, iclass 26, count 0 2006.201.18:55:24.26#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:55:24.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:55:24.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.18:55:24.26#ibcon#*before write, iclass 26, count 0 2006.201.18:55:24.26#ibcon#enter sib2, iclass 26, count 0 2006.201.18:55:24.26#ibcon#flushed, iclass 26, count 0 2006.201.18:55:24.26#ibcon#about to write, iclass 26, count 0 2006.201.18:55:24.26#ibcon#wrote, iclass 26, count 0 2006.201.18:55:24.26#ibcon#about to read 3, iclass 26, count 0 2006.201.18:55:24.30#ibcon#read 3, iclass 26, count 0 2006.201.18:55:24.30#ibcon#about to read 4, iclass 26, count 0 2006.201.18:55:24.30#ibcon#read 4, iclass 26, count 0 2006.201.18:55:24.30#ibcon#about to read 5, iclass 26, count 0 2006.201.18:55:24.30#ibcon#read 5, iclass 26, count 0 2006.201.18:55:24.30#ibcon#about to read 6, iclass 26, count 0 2006.201.18:55:24.30#ibcon#read 6, iclass 26, count 0 2006.201.18:55:24.30#ibcon#end of sib2, iclass 26, count 0 2006.201.18:55:24.30#ibcon#*after write, iclass 26, count 0 2006.201.18:55:24.30#ibcon#*before return 0, iclass 26, count 0 2006.201.18:55:24.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:24.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:24.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:55:24.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:55:24.30$vck44/va=8,4 2006.201.18:55:24.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.18:55:24.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.18:55:24.30#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:24.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:55:24.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:55:24.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:55:24.36#ibcon#enter wrdev, iclass 28, count 2 2006.201.18:55:24.36#ibcon#first serial, iclass 28, count 2 2006.201.18:55:24.36#ibcon#enter sib2, iclass 28, count 2 2006.201.18:55:24.36#ibcon#flushed, iclass 28, count 2 2006.201.18:55:24.36#ibcon#about to write, iclass 28, count 2 2006.201.18:55:24.36#ibcon#wrote, iclass 28, count 2 2006.201.18:55:24.36#ibcon#about to read 3, iclass 28, count 2 2006.201.18:55:24.38#ibcon#read 3, iclass 28, count 2 2006.201.18:55:24.38#ibcon#about to read 4, iclass 28, count 2 2006.201.18:55:24.38#ibcon#read 4, iclass 28, count 2 2006.201.18:55:24.38#ibcon#about to read 5, iclass 28, count 2 2006.201.18:55:24.38#ibcon#read 5, iclass 28, count 2 2006.201.18:55:24.38#ibcon#about to read 6, iclass 28, count 2 2006.201.18:55:24.38#ibcon#read 6, iclass 28, count 2 2006.201.18:55:24.38#ibcon#end of sib2, iclass 28, count 2 2006.201.18:55:24.38#ibcon#*mode == 0, iclass 28, count 2 2006.201.18:55:24.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.18:55:24.38#ibcon#[25=AT08-04\r\n] 2006.201.18:55:24.38#ibcon#*before write, iclass 28, count 2 2006.201.18:55:24.38#ibcon#enter sib2, iclass 28, count 2 2006.201.18:55:24.38#ibcon#flushed, iclass 28, count 2 2006.201.18:55:24.38#ibcon#about to write, iclass 28, count 2 2006.201.18:55:24.38#ibcon#wrote, iclass 28, count 2 2006.201.18:55:24.38#ibcon#about to read 3, iclass 28, count 2 2006.201.18:55:24.41#ibcon#read 3, iclass 28, count 2 2006.201.18:55:24.41#ibcon#about to read 4, iclass 28, count 2 2006.201.18:55:24.41#ibcon#read 4, iclass 28, count 2 2006.201.18:55:24.41#ibcon#about to read 5, iclass 28, count 2 2006.201.18:55:24.41#ibcon#read 5, iclass 28, count 2 2006.201.18:55:24.41#ibcon#about to read 6, iclass 28, count 2 2006.201.18:55:24.41#ibcon#read 6, iclass 28, count 2 2006.201.18:55:24.41#ibcon#end of sib2, iclass 28, count 2 2006.201.18:55:24.41#ibcon#*after write, iclass 28, count 2 2006.201.18:55:24.41#ibcon#*before return 0, iclass 28, count 2 2006.201.18:55:24.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:55:24.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.18:55:24.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.18:55:24.41#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:24.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:55:24.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:55:24.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:55:24.53#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:55:24.53#ibcon#first serial, iclass 28, count 0 2006.201.18:55:24.53#ibcon#enter sib2, iclass 28, count 0 2006.201.18:55:24.53#ibcon#flushed, iclass 28, count 0 2006.201.18:55:24.53#ibcon#about to write, iclass 28, count 0 2006.201.18:55:24.53#ibcon#wrote, iclass 28, count 0 2006.201.18:55:24.53#ibcon#about to read 3, iclass 28, count 0 2006.201.18:55:24.55#ibcon#read 3, iclass 28, count 0 2006.201.18:55:24.55#ibcon#about to read 4, iclass 28, count 0 2006.201.18:55:24.55#ibcon#read 4, iclass 28, count 0 2006.201.18:55:24.55#ibcon#about to read 5, iclass 28, count 0 2006.201.18:55:24.55#ibcon#read 5, iclass 28, count 0 2006.201.18:55:24.55#ibcon#about to read 6, iclass 28, count 0 2006.201.18:55:24.55#ibcon#read 6, iclass 28, count 0 2006.201.18:55:24.55#ibcon#end of sib2, iclass 28, count 0 2006.201.18:55:24.55#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:55:24.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:55:24.55#ibcon#[25=USB\r\n] 2006.201.18:55:24.55#ibcon#*before write, iclass 28, count 0 2006.201.18:55:24.55#ibcon#enter sib2, iclass 28, count 0 2006.201.18:55:24.55#ibcon#flushed, iclass 28, count 0 2006.201.18:55:24.55#ibcon#about to write, iclass 28, count 0 2006.201.18:55:24.55#ibcon#wrote, iclass 28, count 0 2006.201.18:55:24.55#ibcon#about to read 3, iclass 28, count 0 2006.201.18:55:24.58#ibcon#read 3, iclass 28, count 0 2006.201.18:55:24.58#ibcon#about to read 4, iclass 28, count 0 2006.201.18:55:24.58#ibcon#read 4, iclass 28, count 0 2006.201.18:55:24.58#ibcon#about to read 5, iclass 28, count 0 2006.201.18:55:24.58#ibcon#read 5, iclass 28, count 0 2006.201.18:55:24.58#ibcon#about to read 6, iclass 28, count 0 2006.201.18:55:24.58#ibcon#read 6, iclass 28, count 0 2006.201.18:55:24.58#ibcon#end of sib2, iclass 28, count 0 2006.201.18:55:24.58#ibcon#*after write, iclass 28, count 0 2006.201.18:55:24.58#ibcon#*before return 0, iclass 28, count 0 2006.201.18:55:24.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:55:24.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.18:55:24.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:55:24.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:55:24.58$vck44/vblo=1,629.99 2006.201.18:55:24.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.18:55:24.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.18:55:24.58#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:24.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:24.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:24.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:24.58#ibcon#enter wrdev, iclass 30, count 0 2006.201.18:55:24.58#ibcon#first serial, iclass 30, count 0 2006.201.18:55:24.58#ibcon#enter sib2, iclass 30, count 0 2006.201.18:55:24.58#ibcon#flushed, iclass 30, count 0 2006.201.18:55:24.58#ibcon#about to write, iclass 30, count 0 2006.201.18:55:24.58#ibcon#wrote, iclass 30, count 0 2006.201.18:55:24.58#ibcon#about to read 3, iclass 30, count 0 2006.201.18:55:24.60#ibcon#read 3, iclass 30, count 0 2006.201.18:55:24.60#ibcon#about to read 4, iclass 30, count 0 2006.201.18:55:24.60#ibcon#read 4, iclass 30, count 0 2006.201.18:55:24.60#ibcon#about to read 5, iclass 30, count 0 2006.201.18:55:24.60#ibcon#read 5, iclass 30, count 0 2006.201.18:55:24.60#ibcon#about to read 6, iclass 30, count 0 2006.201.18:55:24.60#ibcon#read 6, iclass 30, count 0 2006.201.18:55:24.60#ibcon#end of sib2, iclass 30, count 0 2006.201.18:55:24.60#ibcon#*mode == 0, iclass 30, count 0 2006.201.18:55:24.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.18:55:24.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.18:55:24.60#ibcon#*before write, iclass 30, count 0 2006.201.18:55:24.60#ibcon#enter sib2, iclass 30, count 0 2006.201.18:55:24.60#ibcon#flushed, iclass 30, count 0 2006.201.18:55:24.60#ibcon#about to write, iclass 30, count 0 2006.201.18:55:24.60#ibcon#wrote, iclass 30, count 0 2006.201.18:55:24.60#ibcon#about to read 3, iclass 30, count 0 2006.201.18:55:24.64#ibcon#read 3, iclass 30, count 0 2006.201.18:55:24.64#ibcon#about to read 4, iclass 30, count 0 2006.201.18:55:24.64#ibcon#read 4, iclass 30, count 0 2006.201.18:55:24.64#ibcon#about to read 5, iclass 30, count 0 2006.201.18:55:24.64#ibcon#read 5, iclass 30, count 0 2006.201.18:55:24.64#ibcon#about to read 6, iclass 30, count 0 2006.201.18:55:24.64#ibcon#read 6, iclass 30, count 0 2006.201.18:55:24.64#ibcon#end of sib2, iclass 30, count 0 2006.201.18:55:24.64#ibcon#*after write, iclass 30, count 0 2006.201.18:55:24.64#ibcon#*before return 0, iclass 30, count 0 2006.201.18:55:24.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:24.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.18:55:24.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.18:55:24.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.18:55:24.64$vck44/vb=1,4 2006.201.18:55:24.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.18:55:24.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.18:55:24.64#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:24.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:24.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:24.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:24.64#ibcon#enter wrdev, iclass 32, count 2 2006.201.18:55:24.64#ibcon#first serial, iclass 32, count 2 2006.201.18:55:24.64#ibcon#enter sib2, iclass 32, count 2 2006.201.18:55:24.64#ibcon#flushed, iclass 32, count 2 2006.201.18:55:24.64#ibcon#about to write, iclass 32, count 2 2006.201.18:55:24.64#ibcon#wrote, iclass 32, count 2 2006.201.18:55:24.64#ibcon#about to read 3, iclass 32, count 2 2006.201.18:55:24.66#ibcon#read 3, iclass 32, count 2 2006.201.18:55:24.66#ibcon#about to read 4, iclass 32, count 2 2006.201.18:55:24.66#ibcon#read 4, iclass 32, count 2 2006.201.18:55:24.66#ibcon#about to read 5, iclass 32, count 2 2006.201.18:55:24.66#ibcon#read 5, iclass 32, count 2 2006.201.18:55:24.66#ibcon#about to read 6, iclass 32, count 2 2006.201.18:55:24.66#ibcon#read 6, iclass 32, count 2 2006.201.18:55:24.66#ibcon#end of sib2, iclass 32, count 2 2006.201.18:55:24.66#ibcon#*mode == 0, iclass 32, count 2 2006.201.18:55:24.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.18:55:24.66#ibcon#[27=AT01-04\r\n] 2006.201.18:55:24.66#ibcon#*before write, iclass 32, count 2 2006.201.18:55:24.66#ibcon#enter sib2, iclass 32, count 2 2006.201.18:55:24.66#ibcon#flushed, iclass 32, count 2 2006.201.18:55:24.66#ibcon#about to write, iclass 32, count 2 2006.201.18:55:24.66#ibcon#wrote, iclass 32, count 2 2006.201.18:55:24.66#ibcon#about to read 3, iclass 32, count 2 2006.201.18:55:24.69#ibcon#read 3, iclass 32, count 2 2006.201.18:55:24.69#ibcon#about to read 4, iclass 32, count 2 2006.201.18:55:24.69#ibcon#read 4, iclass 32, count 2 2006.201.18:55:24.69#ibcon#about to read 5, iclass 32, count 2 2006.201.18:55:24.69#ibcon#read 5, iclass 32, count 2 2006.201.18:55:24.69#ibcon#about to read 6, iclass 32, count 2 2006.201.18:55:24.69#ibcon#read 6, iclass 32, count 2 2006.201.18:55:24.69#ibcon#end of sib2, iclass 32, count 2 2006.201.18:55:24.69#ibcon#*after write, iclass 32, count 2 2006.201.18:55:24.69#ibcon#*before return 0, iclass 32, count 2 2006.201.18:55:24.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:24.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.18:55:24.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.18:55:24.69#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:24.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:24.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:24.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:24.81#ibcon#enter wrdev, iclass 32, count 0 2006.201.18:55:24.81#ibcon#first serial, iclass 32, count 0 2006.201.18:55:24.81#ibcon#enter sib2, iclass 32, count 0 2006.201.18:55:24.81#ibcon#flushed, iclass 32, count 0 2006.201.18:55:24.81#ibcon#about to write, iclass 32, count 0 2006.201.18:55:24.81#ibcon#wrote, iclass 32, count 0 2006.201.18:55:24.81#ibcon#about to read 3, iclass 32, count 0 2006.201.18:55:24.83#ibcon#read 3, iclass 32, count 0 2006.201.18:55:24.83#ibcon#about to read 4, iclass 32, count 0 2006.201.18:55:24.83#ibcon#read 4, iclass 32, count 0 2006.201.18:55:24.83#ibcon#about to read 5, iclass 32, count 0 2006.201.18:55:24.83#ibcon#read 5, iclass 32, count 0 2006.201.18:55:24.83#ibcon#about to read 6, iclass 32, count 0 2006.201.18:55:24.83#ibcon#read 6, iclass 32, count 0 2006.201.18:55:24.83#ibcon#end of sib2, iclass 32, count 0 2006.201.18:55:24.83#ibcon#*mode == 0, iclass 32, count 0 2006.201.18:55:24.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.18:55:24.83#ibcon#[27=USB\r\n] 2006.201.18:55:24.83#ibcon#*before write, iclass 32, count 0 2006.201.18:55:24.83#ibcon#enter sib2, iclass 32, count 0 2006.201.18:55:24.83#ibcon#flushed, iclass 32, count 0 2006.201.18:55:24.83#ibcon#about to write, iclass 32, count 0 2006.201.18:55:24.83#ibcon#wrote, iclass 32, count 0 2006.201.18:55:24.83#ibcon#about to read 3, iclass 32, count 0 2006.201.18:55:24.86#ibcon#read 3, iclass 32, count 0 2006.201.18:55:24.86#ibcon#about to read 4, iclass 32, count 0 2006.201.18:55:24.86#ibcon#read 4, iclass 32, count 0 2006.201.18:55:24.86#ibcon#about to read 5, iclass 32, count 0 2006.201.18:55:24.86#ibcon#read 5, iclass 32, count 0 2006.201.18:55:24.86#ibcon#about to read 6, iclass 32, count 0 2006.201.18:55:24.86#ibcon#read 6, iclass 32, count 0 2006.201.18:55:24.86#ibcon#end of sib2, iclass 32, count 0 2006.201.18:55:24.86#ibcon#*after write, iclass 32, count 0 2006.201.18:55:24.86#ibcon#*before return 0, iclass 32, count 0 2006.201.18:55:24.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:24.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.18:55:24.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.18:55:24.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.18:55:24.86$vck44/vblo=2,634.99 2006.201.18:55:24.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.18:55:24.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.18:55:24.86#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:24.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:24.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:24.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:24.86#ibcon#enter wrdev, iclass 34, count 0 2006.201.18:55:24.86#ibcon#first serial, iclass 34, count 0 2006.201.18:55:24.86#ibcon#enter sib2, iclass 34, count 0 2006.201.18:55:24.86#ibcon#flushed, iclass 34, count 0 2006.201.18:55:24.86#ibcon#about to write, iclass 34, count 0 2006.201.18:55:24.86#ibcon#wrote, iclass 34, count 0 2006.201.18:55:24.86#ibcon#about to read 3, iclass 34, count 0 2006.201.18:55:24.88#ibcon#read 3, iclass 34, count 0 2006.201.18:55:24.88#ibcon#about to read 4, iclass 34, count 0 2006.201.18:55:24.88#ibcon#read 4, iclass 34, count 0 2006.201.18:55:24.88#ibcon#about to read 5, iclass 34, count 0 2006.201.18:55:24.88#ibcon#read 5, iclass 34, count 0 2006.201.18:55:24.88#ibcon#about to read 6, iclass 34, count 0 2006.201.18:55:24.88#ibcon#read 6, iclass 34, count 0 2006.201.18:55:24.88#ibcon#end of sib2, iclass 34, count 0 2006.201.18:55:24.88#ibcon#*mode == 0, iclass 34, count 0 2006.201.18:55:24.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.18:55:24.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.18:55:24.88#ibcon#*before write, iclass 34, count 0 2006.201.18:55:24.88#ibcon#enter sib2, iclass 34, count 0 2006.201.18:55:24.88#ibcon#flushed, iclass 34, count 0 2006.201.18:55:24.88#ibcon#about to write, iclass 34, count 0 2006.201.18:55:24.88#ibcon#wrote, iclass 34, count 0 2006.201.18:55:24.88#ibcon#about to read 3, iclass 34, count 0 2006.201.18:55:24.92#ibcon#read 3, iclass 34, count 0 2006.201.18:55:24.92#ibcon#about to read 4, iclass 34, count 0 2006.201.18:55:24.92#ibcon#read 4, iclass 34, count 0 2006.201.18:55:24.92#ibcon#about to read 5, iclass 34, count 0 2006.201.18:55:24.92#ibcon#read 5, iclass 34, count 0 2006.201.18:55:24.92#ibcon#about to read 6, iclass 34, count 0 2006.201.18:55:24.92#ibcon#read 6, iclass 34, count 0 2006.201.18:55:24.92#ibcon#end of sib2, iclass 34, count 0 2006.201.18:55:24.92#ibcon#*after write, iclass 34, count 0 2006.201.18:55:24.92#ibcon#*before return 0, iclass 34, count 0 2006.201.18:55:24.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:24.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.18:55:24.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.18:55:24.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.18:55:24.92$vck44/vb=2,5 2006.201.18:55:24.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.18:55:24.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.18:55:24.92#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:24.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:55:24.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:55:24.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:55:24.98#ibcon#enter wrdev, iclass 36, count 2 2006.201.18:55:24.98#ibcon#first serial, iclass 36, count 2 2006.201.18:55:24.98#ibcon#enter sib2, iclass 36, count 2 2006.201.18:55:24.98#ibcon#flushed, iclass 36, count 2 2006.201.18:55:24.98#ibcon#about to write, iclass 36, count 2 2006.201.18:55:24.98#ibcon#wrote, iclass 36, count 2 2006.201.18:55:24.98#ibcon#about to read 3, iclass 36, count 2 2006.201.18:55:25.00#ibcon#read 3, iclass 36, count 2 2006.201.18:55:25.00#ibcon#about to read 4, iclass 36, count 2 2006.201.18:55:25.00#ibcon#read 4, iclass 36, count 2 2006.201.18:55:25.00#ibcon#about to read 5, iclass 36, count 2 2006.201.18:55:25.00#ibcon#read 5, iclass 36, count 2 2006.201.18:55:25.00#ibcon#about to read 6, iclass 36, count 2 2006.201.18:55:25.00#ibcon#read 6, iclass 36, count 2 2006.201.18:55:25.00#ibcon#end of sib2, iclass 36, count 2 2006.201.18:55:25.00#ibcon#*mode == 0, iclass 36, count 2 2006.201.18:55:25.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.18:55:25.00#ibcon#[27=AT02-05\r\n] 2006.201.18:55:25.00#ibcon#*before write, iclass 36, count 2 2006.201.18:55:25.00#ibcon#enter sib2, iclass 36, count 2 2006.201.18:55:25.00#ibcon#flushed, iclass 36, count 2 2006.201.18:55:25.00#ibcon#about to write, iclass 36, count 2 2006.201.18:55:25.00#ibcon#wrote, iclass 36, count 2 2006.201.18:55:25.00#ibcon#about to read 3, iclass 36, count 2 2006.201.18:55:25.03#ibcon#read 3, iclass 36, count 2 2006.201.18:55:25.03#ibcon#about to read 4, iclass 36, count 2 2006.201.18:55:25.03#ibcon#read 4, iclass 36, count 2 2006.201.18:55:25.03#ibcon#about to read 5, iclass 36, count 2 2006.201.18:55:25.03#ibcon#read 5, iclass 36, count 2 2006.201.18:55:25.03#ibcon#about to read 6, iclass 36, count 2 2006.201.18:55:25.03#ibcon#read 6, iclass 36, count 2 2006.201.18:55:25.03#ibcon#end of sib2, iclass 36, count 2 2006.201.18:55:25.03#ibcon#*after write, iclass 36, count 2 2006.201.18:55:25.03#ibcon#*before return 0, iclass 36, count 2 2006.201.18:55:25.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:55:25.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.18:55:25.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.18:55:25.03#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:25.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:55:25.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:55:25.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:55:25.15#ibcon#enter wrdev, iclass 36, count 0 2006.201.18:55:25.15#ibcon#first serial, iclass 36, count 0 2006.201.18:55:25.15#ibcon#enter sib2, iclass 36, count 0 2006.201.18:55:25.15#ibcon#flushed, iclass 36, count 0 2006.201.18:55:25.15#ibcon#about to write, iclass 36, count 0 2006.201.18:55:25.15#ibcon#wrote, iclass 36, count 0 2006.201.18:55:25.15#ibcon#about to read 3, iclass 36, count 0 2006.201.18:55:25.17#ibcon#read 3, iclass 36, count 0 2006.201.18:55:25.17#ibcon#about to read 4, iclass 36, count 0 2006.201.18:55:25.17#ibcon#read 4, iclass 36, count 0 2006.201.18:55:25.17#ibcon#about to read 5, iclass 36, count 0 2006.201.18:55:25.17#ibcon#read 5, iclass 36, count 0 2006.201.18:55:25.17#ibcon#about to read 6, iclass 36, count 0 2006.201.18:55:25.17#ibcon#read 6, iclass 36, count 0 2006.201.18:55:25.17#ibcon#end of sib2, iclass 36, count 0 2006.201.18:55:25.17#ibcon#*mode == 0, iclass 36, count 0 2006.201.18:55:25.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.18:55:25.17#ibcon#[27=USB\r\n] 2006.201.18:55:25.17#ibcon#*before write, iclass 36, count 0 2006.201.18:55:25.17#ibcon#enter sib2, iclass 36, count 0 2006.201.18:55:25.17#ibcon#flushed, iclass 36, count 0 2006.201.18:55:25.17#ibcon#about to write, iclass 36, count 0 2006.201.18:55:25.17#ibcon#wrote, iclass 36, count 0 2006.201.18:55:25.17#ibcon#about to read 3, iclass 36, count 0 2006.201.18:55:25.20#ibcon#read 3, iclass 36, count 0 2006.201.18:55:25.20#ibcon#about to read 4, iclass 36, count 0 2006.201.18:55:25.20#ibcon#read 4, iclass 36, count 0 2006.201.18:55:25.20#ibcon#about to read 5, iclass 36, count 0 2006.201.18:55:25.20#ibcon#read 5, iclass 36, count 0 2006.201.18:55:25.20#ibcon#about to read 6, iclass 36, count 0 2006.201.18:55:25.20#ibcon#read 6, iclass 36, count 0 2006.201.18:55:25.20#ibcon#end of sib2, iclass 36, count 0 2006.201.18:55:25.20#ibcon#*after write, iclass 36, count 0 2006.201.18:55:25.20#ibcon#*before return 0, iclass 36, count 0 2006.201.18:55:25.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:55:25.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.18:55:25.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.18:55:25.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.18:55:25.20$vck44/vblo=3,649.99 2006.201.18:55:25.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.18:55:25.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.18:55:25.20#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:25.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:55:25.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:55:25.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:55:25.20#ibcon#enter wrdev, iclass 38, count 0 2006.201.18:55:25.20#ibcon#first serial, iclass 38, count 0 2006.201.18:55:25.20#ibcon#enter sib2, iclass 38, count 0 2006.201.18:55:25.20#ibcon#flushed, iclass 38, count 0 2006.201.18:55:25.20#ibcon#about to write, iclass 38, count 0 2006.201.18:55:25.20#ibcon#wrote, iclass 38, count 0 2006.201.18:55:25.20#ibcon#about to read 3, iclass 38, count 0 2006.201.18:55:25.22#ibcon#read 3, iclass 38, count 0 2006.201.18:55:25.22#ibcon#about to read 4, iclass 38, count 0 2006.201.18:55:25.22#ibcon#read 4, iclass 38, count 0 2006.201.18:55:25.22#ibcon#about to read 5, iclass 38, count 0 2006.201.18:55:25.22#ibcon#read 5, iclass 38, count 0 2006.201.18:55:25.22#ibcon#about to read 6, iclass 38, count 0 2006.201.18:55:25.22#ibcon#read 6, iclass 38, count 0 2006.201.18:55:25.22#ibcon#end of sib2, iclass 38, count 0 2006.201.18:55:25.22#ibcon#*mode == 0, iclass 38, count 0 2006.201.18:55:25.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.18:55:25.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.18:55:25.22#ibcon#*before write, iclass 38, count 0 2006.201.18:55:25.22#ibcon#enter sib2, iclass 38, count 0 2006.201.18:55:25.22#ibcon#flushed, iclass 38, count 0 2006.201.18:55:25.22#ibcon#about to write, iclass 38, count 0 2006.201.18:55:25.22#ibcon#wrote, iclass 38, count 0 2006.201.18:55:25.22#ibcon#about to read 3, iclass 38, count 0 2006.201.18:55:25.26#ibcon#read 3, iclass 38, count 0 2006.201.18:55:25.26#ibcon#about to read 4, iclass 38, count 0 2006.201.18:55:25.26#ibcon#read 4, iclass 38, count 0 2006.201.18:55:25.26#ibcon#about to read 5, iclass 38, count 0 2006.201.18:55:25.26#ibcon#read 5, iclass 38, count 0 2006.201.18:55:25.26#ibcon#about to read 6, iclass 38, count 0 2006.201.18:55:25.26#ibcon#read 6, iclass 38, count 0 2006.201.18:55:25.26#ibcon#end of sib2, iclass 38, count 0 2006.201.18:55:25.26#ibcon#*after write, iclass 38, count 0 2006.201.18:55:25.26#ibcon#*before return 0, iclass 38, count 0 2006.201.18:55:25.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:55:25.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.18:55:25.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.18:55:25.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.18:55:25.26$vck44/vb=3,4 2006.201.18:55:25.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.18:55:25.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.18:55:25.26#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:25.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:55:25.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:55:25.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:55:25.32#ibcon#enter wrdev, iclass 40, count 2 2006.201.18:55:25.32#ibcon#first serial, iclass 40, count 2 2006.201.18:55:25.32#ibcon#enter sib2, iclass 40, count 2 2006.201.18:55:25.32#ibcon#flushed, iclass 40, count 2 2006.201.18:55:25.32#ibcon#about to write, iclass 40, count 2 2006.201.18:55:25.32#ibcon#wrote, iclass 40, count 2 2006.201.18:55:25.32#ibcon#about to read 3, iclass 40, count 2 2006.201.18:55:25.34#ibcon#read 3, iclass 40, count 2 2006.201.18:55:25.34#ibcon#about to read 4, iclass 40, count 2 2006.201.18:55:25.34#ibcon#read 4, iclass 40, count 2 2006.201.18:55:25.34#ibcon#about to read 5, iclass 40, count 2 2006.201.18:55:25.34#ibcon#read 5, iclass 40, count 2 2006.201.18:55:25.34#ibcon#about to read 6, iclass 40, count 2 2006.201.18:55:25.34#ibcon#read 6, iclass 40, count 2 2006.201.18:55:25.34#ibcon#end of sib2, iclass 40, count 2 2006.201.18:55:25.34#ibcon#*mode == 0, iclass 40, count 2 2006.201.18:55:25.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.18:55:25.34#ibcon#[27=AT03-04\r\n] 2006.201.18:55:25.34#ibcon#*before write, iclass 40, count 2 2006.201.18:55:25.34#ibcon#enter sib2, iclass 40, count 2 2006.201.18:55:25.34#ibcon#flushed, iclass 40, count 2 2006.201.18:55:25.34#ibcon#about to write, iclass 40, count 2 2006.201.18:55:25.34#ibcon#wrote, iclass 40, count 2 2006.201.18:55:25.34#ibcon#about to read 3, iclass 40, count 2 2006.201.18:55:25.37#ibcon#read 3, iclass 40, count 2 2006.201.18:55:25.37#ibcon#about to read 4, iclass 40, count 2 2006.201.18:55:25.37#ibcon#read 4, iclass 40, count 2 2006.201.18:55:25.37#ibcon#about to read 5, iclass 40, count 2 2006.201.18:55:25.37#ibcon#read 5, iclass 40, count 2 2006.201.18:55:25.37#ibcon#about to read 6, iclass 40, count 2 2006.201.18:55:25.37#ibcon#read 6, iclass 40, count 2 2006.201.18:55:25.37#ibcon#end of sib2, iclass 40, count 2 2006.201.18:55:25.37#ibcon#*after write, iclass 40, count 2 2006.201.18:55:25.37#ibcon#*before return 0, iclass 40, count 2 2006.201.18:55:25.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:55:25.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.18:55:25.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.18:55:25.37#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:25.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:55:25.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:55:25.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:55:25.49#ibcon#enter wrdev, iclass 40, count 0 2006.201.18:55:25.49#ibcon#first serial, iclass 40, count 0 2006.201.18:55:25.49#ibcon#enter sib2, iclass 40, count 0 2006.201.18:55:25.49#ibcon#flushed, iclass 40, count 0 2006.201.18:55:25.49#ibcon#about to write, iclass 40, count 0 2006.201.18:55:25.49#ibcon#wrote, iclass 40, count 0 2006.201.18:55:25.49#ibcon#about to read 3, iclass 40, count 0 2006.201.18:55:25.51#ibcon#read 3, iclass 40, count 0 2006.201.18:55:25.51#ibcon#about to read 4, iclass 40, count 0 2006.201.18:55:25.51#ibcon#read 4, iclass 40, count 0 2006.201.18:55:25.51#ibcon#about to read 5, iclass 40, count 0 2006.201.18:55:25.51#ibcon#read 5, iclass 40, count 0 2006.201.18:55:25.51#ibcon#about to read 6, iclass 40, count 0 2006.201.18:55:25.51#ibcon#read 6, iclass 40, count 0 2006.201.18:55:25.51#ibcon#end of sib2, iclass 40, count 0 2006.201.18:55:25.51#ibcon#*mode == 0, iclass 40, count 0 2006.201.18:55:25.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.18:55:25.51#ibcon#[27=USB\r\n] 2006.201.18:55:25.51#ibcon#*before write, iclass 40, count 0 2006.201.18:55:25.51#ibcon#enter sib2, iclass 40, count 0 2006.201.18:55:25.51#ibcon#flushed, iclass 40, count 0 2006.201.18:55:25.51#ibcon#about to write, iclass 40, count 0 2006.201.18:55:25.51#ibcon#wrote, iclass 40, count 0 2006.201.18:55:25.51#ibcon#about to read 3, iclass 40, count 0 2006.201.18:55:25.54#ibcon#read 3, iclass 40, count 0 2006.201.18:55:25.54#ibcon#about to read 4, iclass 40, count 0 2006.201.18:55:25.54#ibcon#read 4, iclass 40, count 0 2006.201.18:55:25.54#ibcon#about to read 5, iclass 40, count 0 2006.201.18:55:25.54#ibcon#read 5, iclass 40, count 0 2006.201.18:55:25.54#ibcon#about to read 6, iclass 40, count 0 2006.201.18:55:25.54#ibcon#read 6, iclass 40, count 0 2006.201.18:55:25.54#ibcon#end of sib2, iclass 40, count 0 2006.201.18:55:25.54#ibcon#*after write, iclass 40, count 0 2006.201.18:55:25.54#ibcon#*before return 0, iclass 40, count 0 2006.201.18:55:25.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:55:25.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.18:55:25.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.18:55:25.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.18:55:25.54$vck44/vblo=4,679.99 2006.201.18:55:25.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.18:55:25.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.18:55:25.54#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:25.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:25.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:25.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:25.54#ibcon#enter wrdev, iclass 4, count 0 2006.201.18:55:25.54#ibcon#first serial, iclass 4, count 0 2006.201.18:55:25.54#ibcon#enter sib2, iclass 4, count 0 2006.201.18:55:25.54#ibcon#flushed, iclass 4, count 0 2006.201.18:55:25.54#ibcon#about to write, iclass 4, count 0 2006.201.18:55:25.54#ibcon#wrote, iclass 4, count 0 2006.201.18:55:25.54#ibcon#about to read 3, iclass 4, count 0 2006.201.18:55:25.56#ibcon#read 3, iclass 4, count 0 2006.201.18:55:25.56#ibcon#about to read 4, iclass 4, count 0 2006.201.18:55:25.56#ibcon#read 4, iclass 4, count 0 2006.201.18:55:25.56#ibcon#about to read 5, iclass 4, count 0 2006.201.18:55:25.56#ibcon#read 5, iclass 4, count 0 2006.201.18:55:25.56#ibcon#about to read 6, iclass 4, count 0 2006.201.18:55:25.56#ibcon#read 6, iclass 4, count 0 2006.201.18:55:25.56#ibcon#end of sib2, iclass 4, count 0 2006.201.18:55:25.56#ibcon#*mode == 0, iclass 4, count 0 2006.201.18:55:25.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.18:55:25.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.18:55:25.56#ibcon#*before write, iclass 4, count 0 2006.201.18:55:25.56#ibcon#enter sib2, iclass 4, count 0 2006.201.18:55:25.56#ibcon#flushed, iclass 4, count 0 2006.201.18:55:25.56#ibcon#about to write, iclass 4, count 0 2006.201.18:55:25.56#ibcon#wrote, iclass 4, count 0 2006.201.18:55:25.56#ibcon#about to read 3, iclass 4, count 0 2006.201.18:55:25.60#ibcon#read 3, iclass 4, count 0 2006.201.18:55:25.60#ibcon#about to read 4, iclass 4, count 0 2006.201.18:55:25.60#ibcon#read 4, iclass 4, count 0 2006.201.18:55:25.60#ibcon#about to read 5, iclass 4, count 0 2006.201.18:55:25.60#ibcon#read 5, iclass 4, count 0 2006.201.18:55:25.60#ibcon#about to read 6, iclass 4, count 0 2006.201.18:55:25.60#ibcon#read 6, iclass 4, count 0 2006.201.18:55:25.60#ibcon#end of sib2, iclass 4, count 0 2006.201.18:55:25.60#ibcon#*after write, iclass 4, count 0 2006.201.18:55:25.60#ibcon#*before return 0, iclass 4, count 0 2006.201.18:55:25.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:25.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.18:55:25.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.18:55:25.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.18:55:25.60$vck44/vb=4,5 2006.201.18:55:25.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.18:55:25.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.18:55:25.60#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:25.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:25.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:25.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:25.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.18:55:25.66#ibcon#first serial, iclass 6, count 2 2006.201.18:55:25.66#ibcon#enter sib2, iclass 6, count 2 2006.201.18:55:25.66#ibcon#flushed, iclass 6, count 2 2006.201.18:55:25.66#ibcon#about to write, iclass 6, count 2 2006.201.18:55:25.66#ibcon#wrote, iclass 6, count 2 2006.201.18:55:25.66#ibcon#about to read 3, iclass 6, count 2 2006.201.18:55:25.68#ibcon#read 3, iclass 6, count 2 2006.201.18:55:25.68#ibcon#about to read 4, iclass 6, count 2 2006.201.18:55:25.68#ibcon#read 4, iclass 6, count 2 2006.201.18:55:25.68#ibcon#about to read 5, iclass 6, count 2 2006.201.18:55:25.68#ibcon#read 5, iclass 6, count 2 2006.201.18:55:25.68#ibcon#about to read 6, iclass 6, count 2 2006.201.18:55:25.68#ibcon#read 6, iclass 6, count 2 2006.201.18:55:25.68#ibcon#end of sib2, iclass 6, count 2 2006.201.18:55:25.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.18:55:25.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.18:55:25.68#ibcon#[27=AT04-05\r\n] 2006.201.18:55:25.68#ibcon#*before write, iclass 6, count 2 2006.201.18:55:25.68#ibcon#enter sib2, iclass 6, count 2 2006.201.18:55:25.68#ibcon#flushed, iclass 6, count 2 2006.201.18:55:25.68#ibcon#about to write, iclass 6, count 2 2006.201.18:55:25.68#ibcon#wrote, iclass 6, count 2 2006.201.18:55:25.68#ibcon#about to read 3, iclass 6, count 2 2006.201.18:55:25.71#ibcon#read 3, iclass 6, count 2 2006.201.18:55:25.71#ibcon#about to read 4, iclass 6, count 2 2006.201.18:55:25.71#ibcon#read 4, iclass 6, count 2 2006.201.18:55:25.71#ibcon#about to read 5, iclass 6, count 2 2006.201.18:55:25.71#ibcon#read 5, iclass 6, count 2 2006.201.18:55:25.71#ibcon#about to read 6, iclass 6, count 2 2006.201.18:55:25.71#ibcon#read 6, iclass 6, count 2 2006.201.18:55:25.71#ibcon#end of sib2, iclass 6, count 2 2006.201.18:55:25.71#ibcon#*after write, iclass 6, count 2 2006.201.18:55:25.71#ibcon#*before return 0, iclass 6, count 2 2006.201.18:55:25.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:25.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.18:55:25.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.18:55:25.71#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:25.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:25.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:25.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:25.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.18:55:25.83#ibcon#first serial, iclass 6, count 0 2006.201.18:55:25.83#ibcon#enter sib2, iclass 6, count 0 2006.201.18:55:25.83#ibcon#flushed, iclass 6, count 0 2006.201.18:55:25.83#ibcon#about to write, iclass 6, count 0 2006.201.18:55:25.83#ibcon#wrote, iclass 6, count 0 2006.201.18:55:25.83#ibcon#about to read 3, iclass 6, count 0 2006.201.18:55:25.85#ibcon#read 3, iclass 6, count 0 2006.201.18:55:25.85#ibcon#about to read 4, iclass 6, count 0 2006.201.18:55:25.85#ibcon#read 4, iclass 6, count 0 2006.201.18:55:25.85#ibcon#about to read 5, iclass 6, count 0 2006.201.18:55:25.85#ibcon#read 5, iclass 6, count 0 2006.201.18:55:25.85#ibcon#about to read 6, iclass 6, count 0 2006.201.18:55:25.85#ibcon#read 6, iclass 6, count 0 2006.201.18:55:25.85#ibcon#end of sib2, iclass 6, count 0 2006.201.18:55:25.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.18:55:25.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.18:55:25.85#ibcon#[27=USB\r\n] 2006.201.18:55:25.85#ibcon#*before write, iclass 6, count 0 2006.201.18:55:25.85#ibcon#enter sib2, iclass 6, count 0 2006.201.18:55:25.85#ibcon#flushed, iclass 6, count 0 2006.201.18:55:25.85#ibcon#about to write, iclass 6, count 0 2006.201.18:55:25.85#ibcon#wrote, iclass 6, count 0 2006.201.18:55:25.85#ibcon#about to read 3, iclass 6, count 0 2006.201.18:55:25.88#ibcon#read 3, iclass 6, count 0 2006.201.18:55:25.88#ibcon#about to read 4, iclass 6, count 0 2006.201.18:55:25.88#ibcon#read 4, iclass 6, count 0 2006.201.18:55:25.88#ibcon#about to read 5, iclass 6, count 0 2006.201.18:55:25.88#ibcon#read 5, iclass 6, count 0 2006.201.18:55:25.88#ibcon#about to read 6, iclass 6, count 0 2006.201.18:55:25.88#ibcon#read 6, iclass 6, count 0 2006.201.18:55:25.88#ibcon#end of sib2, iclass 6, count 0 2006.201.18:55:25.88#ibcon#*after write, iclass 6, count 0 2006.201.18:55:25.88#ibcon#*before return 0, iclass 6, count 0 2006.201.18:55:25.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:25.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.18:55:25.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.18:55:25.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.18:55:25.88$vck44/vblo=5,709.99 2006.201.18:55:25.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.18:55:25.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.18:55:25.88#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:25.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:25.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:25.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:25.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.18:55:25.88#ibcon#first serial, iclass 10, count 0 2006.201.18:55:25.88#ibcon#enter sib2, iclass 10, count 0 2006.201.18:55:25.88#ibcon#flushed, iclass 10, count 0 2006.201.18:55:25.88#ibcon#about to write, iclass 10, count 0 2006.201.18:55:25.88#ibcon#wrote, iclass 10, count 0 2006.201.18:55:25.88#ibcon#about to read 3, iclass 10, count 0 2006.201.18:55:25.90#ibcon#read 3, iclass 10, count 0 2006.201.18:55:25.90#ibcon#about to read 4, iclass 10, count 0 2006.201.18:55:25.90#ibcon#read 4, iclass 10, count 0 2006.201.18:55:25.90#ibcon#about to read 5, iclass 10, count 0 2006.201.18:55:25.90#ibcon#read 5, iclass 10, count 0 2006.201.18:55:25.90#ibcon#about to read 6, iclass 10, count 0 2006.201.18:55:25.90#ibcon#read 6, iclass 10, count 0 2006.201.18:55:25.90#ibcon#end of sib2, iclass 10, count 0 2006.201.18:55:25.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.18:55:25.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.18:55:25.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.18:55:25.90#ibcon#*before write, iclass 10, count 0 2006.201.18:55:25.90#ibcon#enter sib2, iclass 10, count 0 2006.201.18:55:25.90#ibcon#flushed, iclass 10, count 0 2006.201.18:55:25.90#ibcon#about to write, iclass 10, count 0 2006.201.18:55:25.90#ibcon#wrote, iclass 10, count 0 2006.201.18:55:25.90#ibcon#about to read 3, iclass 10, count 0 2006.201.18:55:25.95#ibcon#read 3, iclass 10, count 0 2006.201.18:55:25.95#ibcon#about to read 4, iclass 10, count 0 2006.201.18:55:25.95#ibcon#read 4, iclass 10, count 0 2006.201.18:55:25.95#ibcon#about to read 5, iclass 10, count 0 2006.201.18:55:25.95#ibcon#read 5, iclass 10, count 0 2006.201.18:55:25.95#ibcon#about to read 6, iclass 10, count 0 2006.201.18:55:25.95#ibcon#read 6, iclass 10, count 0 2006.201.18:55:25.95#ibcon#end of sib2, iclass 10, count 0 2006.201.18:55:25.95#ibcon#*after write, iclass 10, count 0 2006.201.18:55:25.95#ibcon#*before return 0, iclass 10, count 0 2006.201.18:55:25.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:25.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.18:55:25.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.18:55:25.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.18:55:25.95$vck44/vb=5,4 2006.201.18:55:25.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.18:55:25.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.18:55:25.95#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:25.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:26.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:26.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:26.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.18:55:26.00#ibcon#first serial, iclass 12, count 2 2006.201.18:55:26.00#ibcon#enter sib2, iclass 12, count 2 2006.201.18:55:26.00#ibcon#flushed, iclass 12, count 2 2006.201.18:55:26.00#ibcon#about to write, iclass 12, count 2 2006.201.18:55:26.00#ibcon#wrote, iclass 12, count 2 2006.201.18:55:26.00#ibcon#about to read 3, iclass 12, count 2 2006.201.18:55:26.02#ibcon#read 3, iclass 12, count 2 2006.201.18:55:26.02#ibcon#about to read 4, iclass 12, count 2 2006.201.18:55:26.02#ibcon#read 4, iclass 12, count 2 2006.201.18:55:26.02#ibcon#about to read 5, iclass 12, count 2 2006.201.18:55:26.02#ibcon#read 5, iclass 12, count 2 2006.201.18:55:26.02#ibcon#about to read 6, iclass 12, count 2 2006.201.18:55:26.02#ibcon#read 6, iclass 12, count 2 2006.201.18:55:26.02#ibcon#end of sib2, iclass 12, count 2 2006.201.18:55:26.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.18:55:26.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.18:55:26.02#ibcon#[27=AT05-04\r\n] 2006.201.18:55:26.02#ibcon#*before write, iclass 12, count 2 2006.201.18:55:26.02#ibcon#enter sib2, iclass 12, count 2 2006.201.18:55:26.02#ibcon#flushed, iclass 12, count 2 2006.201.18:55:26.02#ibcon#about to write, iclass 12, count 2 2006.201.18:55:26.02#ibcon#wrote, iclass 12, count 2 2006.201.18:55:26.02#ibcon#about to read 3, iclass 12, count 2 2006.201.18:55:26.05#ibcon#read 3, iclass 12, count 2 2006.201.18:55:26.05#ibcon#about to read 4, iclass 12, count 2 2006.201.18:55:26.05#ibcon#read 4, iclass 12, count 2 2006.201.18:55:26.05#ibcon#about to read 5, iclass 12, count 2 2006.201.18:55:26.05#ibcon#read 5, iclass 12, count 2 2006.201.18:55:26.05#ibcon#about to read 6, iclass 12, count 2 2006.201.18:55:26.05#ibcon#read 6, iclass 12, count 2 2006.201.18:55:26.05#ibcon#end of sib2, iclass 12, count 2 2006.201.18:55:26.05#ibcon#*after write, iclass 12, count 2 2006.201.18:55:26.05#ibcon#*before return 0, iclass 12, count 2 2006.201.18:55:26.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:26.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.18:55:26.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.18:55:26.05#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:26.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:26.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:26.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:26.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.18:55:26.17#ibcon#first serial, iclass 12, count 0 2006.201.18:55:26.17#ibcon#enter sib2, iclass 12, count 0 2006.201.18:55:26.17#ibcon#flushed, iclass 12, count 0 2006.201.18:55:26.17#ibcon#about to write, iclass 12, count 0 2006.201.18:55:26.17#ibcon#wrote, iclass 12, count 0 2006.201.18:55:26.17#ibcon#about to read 3, iclass 12, count 0 2006.201.18:55:26.19#ibcon#read 3, iclass 12, count 0 2006.201.18:55:26.19#ibcon#about to read 4, iclass 12, count 0 2006.201.18:55:26.19#ibcon#read 4, iclass 12, count 0 2006.201.18:55:26.19#ibcon#about to read 5, iclass 12, count 0 2006.201.18:55:26.19#ibcon#read 5, iclass 12, count 0 2006.201.18:55:26.19#ibcon#about to read 6, iclass 12, count 0 2006.201.18:55:26.19#ibcon#read 6, iclass 12, count 0 2006.201.18:55:26.19#ibcon#end of sib2, iclass 12, count 0 2006.201.18:55:26.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.18:55:26.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.18:55:26.19#ibcon#[27=USB\r\n] 2006.201.18:55:26.19#ibcon#*before write, iclass 12, count 0 2006.201.18:55:26.19#ibcon#enter sib2, iclass 12, count 0 2006.201.18:55:26.19#ibcon#flushed, iclass 12, count 0 2006.201.18:55:26.19#ibcon#about to write, iclass 12, count 0 2006.201.18:55:26.19#ibcon#wrote, iclass 12, count 0 2006.201.18:55:26.19#ibcon#about to read 3, iclass 12, count 0 2006.201.18:55:26.22#ibcon#read 3, iclass 12, count 0 2006.201.18:55:26.22#ibcon#about to read 4, iclass 12, count 0 2006.201.18:55:26.22#ibcon#read 4, iclass 12, count 0 2006.201.18:55:26.22#ibcon#about to read 5, iclass 12, count 0 2006.201.18:55:26.22#ibcon#read 5, iclass 12, count 0 2006.201.18:55:26.22#ibcon#about to read 6, iclass 12, count 0 2006.201.18:55:26.22#ibcon#read 6, iclass 12, count 0 2006.201.18:55:26.22#ibcon#end of sib2, iclass 12, count 0 2006.201.18:55:26.22#ibcon#*after write, iclass 12, count 0 2006.201.18:55:26.22#ibcon#*before return 0, iclass 12, count 0 2006.201.18:55:26.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:26.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.18:55:26.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.18:55:26.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.18:55:26.22$vck44/vblo=6,719.99 2006.201.18:55:26.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.18:55:26.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.18:55:26.22#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:26.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:26.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:26.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:26.22#ibcon#enter wrdev, iclass 14, count 0 2006.201.18:55:26.22#ibcon#first serial, iclass 14, count 0 2006.201.18:55:26.22#ibcon#enter sib2, iclass 14, count 0 2006.201.18:55:26.22#ibcon#flushed, iclass 14, count 0 2006.201.18:55:26.22#ibcon#about to write, iclass 14, count 0 2006.201.18:55:26.22#ibcon#wrote, iclass 14, count 0 2006.201.18:55:26.22#ibcon#about to read 3, iclass 14, count 0 2006.201.18:55:26.24#ibcon#read 3, iclass 14, count 0 2006.201.18:55:26.24#ibcon#about to read 4, iclass 14, count 0 2006.201.18:55:26.24#ibcon#read 4, iclass 14, count 0 2006.201.18:55:26.24#ibcon#about to read 5, iclass 14, count 0 2006.201.18:55:26.24#ibcon#read 5, iclass 14, count 0 2006.201.18:55:26.24#ibcon#about to read 6, iclass 14, count 0 2006.201.18:55:26.24#ibcon#read 6, iclass 14, count 0 2006.201.18:55:26.24#ibcon#end of sib2, iclass 14, count 0 2006.201.18:55:26.24#ibcon#*mode == 0, iclass 14, count 0 2006.201.18:55:26.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.18:55:26.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.18:55:26.24#ibcon#*before write, iclass 14, count 0 2006.201.18:55:26.24#ibcon#enter sib2, iclass 14, count 0 2006.201.18:55:26.24#ibcon#flushed, iclass 14, count 0 2006.201.18:55:26.24#ibcon#about to write, iclass 14, count 0 2006.201.18:55:26.24#ibcon#wrote, iclass 14, count 0 2006.201.18:55:26.24#ibcon#about to read 3, iclass 14, count 0 2006.201.18:55:26.28#ibcon#read 3, iclass 14, count 0 2006.201.18:55:26.28#ibcon#about to read 4, iclass 14, count 0 2006.201.18:55:26.28#ibcon#read 4, iclass 14, count 0 2006.201.18:55:26.28#ibcon#about to read 5, iclass 14, count 0 2006.201.18:55:26.28#ibcon#read 5, iclass 14, count 0 2006.201.18:55:26.28#ibcon#about to read 6, iclass 14, count 0 2006.201.18:55:26.28#ibcon#read 6, iclass 14, count 0 2006.201.18:55:26.28#ibcon#end of sib2, iclass 14, count 0 2006.201.18:55:26.28#ibcon#*after write, iclass 14, count 0 2006.201.18:55:26.28#ibcon#*before return 0, iclass 14, count 0 2006.201.18:55:26.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:26.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.18:55:26.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.18:55:26.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.18:55:26.28$vck44/vb=6,4 2006.201.18:55:26.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.18:55:26.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.18:55:26.28#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:26.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:26.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:26.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:26.34#ibcon#enter wrdev, iclass 16, count 2 2006.201.18:55:26.34#ibcon#first serial, iclass 16, count 2 2006.201.18:55:26.34#ibcon#enter sib2, iclass 16, count 2 2006.201.18:55:26.34#ibcon#flushed, iclass 16, count 2 2006.201.18:55:26.34#ibcon#about to write, iclass 16, count 2 2006.201.18:55:26.34#ibcon#wrote, iclass 16, count 2 2006.201.18:55:26.34#ibcon#about to read 3, iclass 16, count 2 2006.201.18:55:26.36#ibcon#read 3, iclass 16, count 2 2006.201.18:55:26.36#ibcon#about to read 4, iclass 16, count 2 2006.201.18:55:26.36#ibcon#read 4, iclass 16, count 2 2006.201.18:55:26.36#ibcon#about to read 5, iclass 16, count 2 2006.201.18:55:26.36#ibcon#read 5, iclass 16, count 2 2006.201.18:55:26.36#ibcon#about to read 6, iclass 16, count 2 2006.201.18:55:26.36#ibcon#read 6, iclass 16, count 2 2006.201.18:55:26.36#ibcon#end of sib2, iclass 16, count 2 2006.201.18:55:26.36#ibcon#*mode == 0, iclass 16, count 2 2006.201.18:55:26.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.18:55:26.36#ibcon#[27=AT06-04\r\n] 2006.201.18:55:26.36#ibcon#*before write, iclass 16, count 2 2006.201.18:55:26.36#ibcon#enter sib2, iclass 16, count 2 2006.201.18:55:26.36#ibcon#flushed, iclass 16, count 2 2006.201.18:55:26.36#ibcon#about to write, iclass 16, count 2 2006.201.18:55:26.36#ibcon#wrote, iclass 16, count 2 2006.201.18:55:26.36#ibcon#about to read 3, iclass 16, count 2 2006.201.18:55:26.39#ibcon#read 3, iclass 16, count 2 2006.201.18:55:26.39#ibcon#about to read 4, iclass 16, count 2 2006.201.18:55:26.39#ibcon#read 4, iclass 16, count 2 2006.201.18:55:26.39#ibcon#about to read 5, iclass 16, count 2 2006.201.18:55:26.39#ibcon#read 5, iclass 16, count 2 2006.201.18:55:26.39#ibcon#about to read 6, iclass 16, count 2 2006.201.18:55:26.39#ibcon#read 6, iclass 16, count 2 2006.201.18:55:26.39#ibcon#end of sib2, iclass 16, count 2 2006.201.18:55:26.39#ibcon#*after write, iclass 16, count 2 2006.201.18:55:26.39#ibcon#*before return 0, iclass 16, count 2 2006.201.18:55:26.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:26.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.18:55:26.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.18:55:26.39#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:26.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:26.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:26.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:26.51#ibcon#enter wrdev, iclass 16, count 0 2006.201.18:55:26.51#ibcon#first serial, iclass 16, count 0 2006.201.18:55:26.51#ibcon#enter sib2, iclass 16, count 0 2006.201.18:55:26.51#ibcon#flushed, iclass 16, count 0 2006.201.18:55:26.51#ibcon#about to write, iclass 16, count 0 2006.201.18:55:26.51#ibcon#wrote, iclass 16, count 0 2006.201.18:55:26.51#ibcon#about to read 3, iclass 16, count 0 2006.201.18:55:26.53#ibcon#read 3, iclass 16, count 0 2006.201.18:55:26.53#ibcon#about to read 4, iclass 16, count 0 2006.201.18:55:26.53#ibcon#read 4, iclass 16, count 0 2006.201.18:55:26.53#ibcon#about to read 5, iclass 16, count 0 2006.201.18:55:26.53#ibcon#read 5, iclass 16, count 0 2006.201.18:55:26.53#ibcon#about to read 6, iclass 16, count 0 2006.201.18:55:26.53#ibcon#read 6, iclass 16, count 0 2006.201.18:55:26.53#ibcon#end of sib2, iclass 16, count 0 2006.201.18:55:26.53#ibcon#*mode == 0, iclass 16, count 0 2006.201.18:55:26.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.18:55:26.53#ibcon#[27=USB\r\n] 2006.201.18:55:26.53#ibcon#*before write, iclass 16, count 0 2006.201.18:55:26.53#ibcon#enter sib2, iclass 16, count 0 2006.201.18:55:26.53#ibcon#flushed, iclass 16, count 0 2006.201.18:55:26.53#ibcon#about to write, iclass 16, count 0 2006.201.18:55:26.53#ibcon#wrote, iclass 16, count 0 2006.201.18:55:26.53#ibcon#about to read 3, iclass 16, count 0 2006.201.18:55:26.56#ibcon#read 3, iclass 16, count 0 2006.201.18:55:26.56#ibcon#about to read 4, iclass 16, count 0 2006.201.18:55:26.56#ibcon#read 4, iclass 16, count 0 2006.201.18:55:26.56#ibcon#about to read 5, iclass 16, count 0 2006.201.18:55:26.56#ibcon#read 5, iclass 16, count 0 2006.201.18:55:26.56#ibcon#about to read 6, iclass 16, count 0 2006.201.18:55:26.56#ibcon#read 6, iclass 16, count 0 2006.201.18:55:26.56#ibcon#end of sib2, iclass 16, count 0 2006.201.18:55:26.56#ibcon#*after write, iclass 16, count 0 2006.201.18:55:26.56#ibcon#*before return 0, iclass 16, count 0 2006.201.18:55:26.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:26.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.18:55:26.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.18:55:26.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.18:55:26.56$vck44/vblo=7,734.99 2006.201.18:55:26.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.18:55:26.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.18:55:26.56#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:26.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:26.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:26.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:26.56#ibcon#enter wrdev, iclass 18, count 0 2006.201.18:55:26.56#ibcon#first serial, iclass 18, count 0 2006.201.18:55:26.56#ibcon#enter sib2, iclass 18, count 0 2006.201.18:55:26.56#ibcon#flushed, iclass 18, count 0 2006.201.18:55:26.56#ibcon#about to write, iclass 18, count 0 2006.201.18:55:26.56#ibcon#wrote, iclass 18, count 0 2006.201.18:55:26.56#ibcon#about to read 3, iclass 18, count 0 2006.201.18:55:26.58#ibcon#read 3, iclass 18, count 0 2006.201.18:55:26.58#ibcon#about to read 4, iclass 18, count 0 2006.201.18:55:26.58#ibcon#read 4, iclass 18, count 0 2006.201.18:55:26.58#ibcon#about to read 5, iclass 18, count 0 2006.201.18:55:26.58#ibcon#read 5, iclass 18, count 0 2006.201.18:55:26.58#ibcon#about to read 6, iclass 18, count 0 2006.201.18:55:26.58#ibcon#read 6, iclass 18, count 0 2006.201.18:55:26.58#ibcon#end of sib2, iclass 18, count 0 2006.201.18:55:26.58#ibcon#*mode == 0, iclass 18, count 0 2006.201.18:55:26.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.18:55:26.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.18:55:26.58#ibcon#*before write, iclass 18, count 0 2006.201.18:55:26.58#ibcon#enter sib2, iclass 18, count 0 2006.201.18:55:26.58#ibcon#flushed, iclass 18, count 0 2006.201.18:55:26.58#ibcon#about to write, iclass 18, count 0 2006.201.18:55:26.58#ibcon#wrote, iclass 18, count 0 2006.201.18:55:26.58#ibcon#about to read 3, iclass 18, count 0 2006.201.18:55:26.63#ibcon#read 3, iclass 18, count 0 2006.201.18:55:26.63#ibcon#about to read 4, iclass 18, count 0 2006.201.18:55:26.63#ibcon#read 4, iclass 18, count 0 2006.201.18:55:26.63#ibcon#about to read 5, iclass 18, count 0 2006.201.18:55:26.63#ibcon#read 5, iclass 18, count 0 2006.201.18:55:26.63#ibcon#about to read 6, iclass 18, count 0 2006.201.18:55:26.63#ibcon#read 6, iclass 18, count 0 2006.201.18:55:26.63#ibcon#end of sib2, iclass 18, count 0 2006.201.18:55:26.63#ibcon#*after write, iclass 18, count 0 2006.201.18:55:26.63#ibcon#*before return 0, iclass 18, count 0 2006.201.18:55:26.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:26.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.18:55:26.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.18:55:26.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.18:55:26.63$vck44/vb=7,4 2006.201.18:55:26.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.18:55:26.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.18:55:26.63#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:26.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:26.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:26.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:26.68#ibcon#enter wrdev, iclass 20, count 2 2006.201.18:55:26.68#ibcon#first serial, iclass 20, count 2 2006.201.18:55:26.68#ibcon#enter sib2, iclass 20, count 2 2006.201.18:55:26.68#ibcon#flushed, iclass 20, count 2 2006.201.18:55:26.68#ibcon#about to write, iclass 20, count 2 2006.201.18:55:26.68#ibcon#wrote, iclass 20, count 2 2006.201.18:55:26.68#ibcon#about to read 3, iclass 20, count 2 2006.201.18:55:26.70#ibcon#read 3, iclass 20, count 2 2006.201.18:55:26.70#ibcon#about to read 4, iclass 20, count 2 2006.201.18:55:26.70#ibcon#read 4, iclass 20, count 2 2006.201.18:55:26.70#ibcon#about to read 5, iclass 20, count 2 2006.201.18:55:26.70#ibcon#read 5, iclass 20, count 2 2006.201.18:55:26.70#ibcon#about to read 6, iclass 20, count 2 2006.201.18:55:26.70#ibcon#read 6, iclass 20, count 2 2006.201.18:55:26.70#ibcon#end of sib2, iclass 20, count 2 2006.201.18:55:26.70#ibcon#*mode == 0, iclass 20, count 2 2006.201.18:55:26.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.18:55:26.70#ibcon#[27=AT07-04\r\n] 2006.201.18:55:26.70#ibcon#*before write, iclass 20, count 2 2006.201.18:55:26.70#ibcon#enter sib2, iclass 20, count 2 2006.201.18:55:26.70#ibcon#flushed, iclass 20, count 2 2006.201.18:55:26.70#ibcon#about to write, iclass 20, count 2 2006.201.18:55:26.70#ibcon#wrote, iclass 20, count 2 2006.201.18:55:26.70#ibcon#about to read 3, iclass 20, count 2 2006.201.18:55:26.73#ibcon#read 3, iclass 20, count 2 2006.201.18:55:26.73#ibcon#about to read 4, iclass 20, count 2 2006.201.18:55:26.73#ibcon#read 4, iclass 20, count 2 2006.201.18:55:26.73#ibcon#about to read 5, iclass 20, count 2 2006.201.18:55:26.73#ibcon#read 5, iclass 20, count 2 2006.201.18:55:26.73#ibcon#about to read 6, iclass 20, count 2 2006.201.18:55:26.73#ibcon#read 6, iclass 20, count 2 2006.201.18:55:26.73#ibcon#end of sib2, iclass 20, count 2 2006.201.18:55:26.73#ibcon#*after write, iclass 20, count 2 2006.201.18:55:26.73#ibcon#*before return 0, iclass 20, count 2 2006.201.18:55:26.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:26.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.18:55:26.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.18:55:26.73#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:26.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:26.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:26.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:26.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.18:55:26.85#ibcon#first serial, iclass 20, count 0 2006.201.18:55:26.85#ibcon#enter sib2, iclass 20, count 0 2006.201.18:55:26.85#ibcon#flushed, iclass 20, count 0 2006.201.18:55:26.85#ibcon#about to write, iclass 20, count 0 2006.201.18:55:26.85#ibcon#wrote, iclass 20, count 0 2006.201.18:55:26.85#ibcon#about to read 3, iclass 20, count 0 2006.201.18:55:26.87#ibcon#read 3, iclass 20, count 0 2006.201.18:55:26.87#ibcon#about to read 4, iclass 20, count 0 2006.201.18:55:26.87#ibcon#read 4, iclass 20, count 0 2006.201.18:55:26.87#ibcon#about to read 5, iclass 20, count 0 2006.201.18:55:26.87#ibcon#read 5, iclass 20, count 0 2006.201.18:55:26.87#ibcon#about to read 6, iclass 20, count 0 2006.201.18:55:26.87#ibcon#read 6, iclass 20, count 0 2006.201.18:55:26.87#ibcon#end of sib2, iclass 20, count 0 2006.201.18:55:26.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.18:55:26.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.18:55:26.87#ibcon#[27=USB\r\n] 2006.201.18:55:26.87#ibcon#*before write, iclass 20, count 0 2006.201.18:55:26.87#ibcon#enter sib2, iclass 20, count 0 2006.201.18:55:26.87#ibcon#flushed, iclass 20, count 0 2006.201.18:55:26.87#ibcon#about to write, iclass 20, count 0 2006.201.18:55:26.87#ibcon#wrote, iclass 20, count 0 2006.201.18:55:26.87#ibcon#about to read 3, iclass 20, count 0 2006.201.18:55:26.90#ibcon#read 3, iclass 20, count 0 2006.201.18:55:26.90#ibcon#about to read 4, iclass 20, count 0 2006.201.18:55:26.90#ibcon#read 4, iclass 20, count 0 2006.201.18:55:26.90#ibcon#about to read 5, iclass 20, count 0 2006.201.18:55:26.90#ibcon#read 5, iclass 20, count 0 2006.201.18:55:26.90#ibcon#about to read 6, iclass 20, count 0 2006.201.18:55:26.90#ibcon#read 6, iclass 20, count 0 2006.201.18:55:26.90#ibcon#end of sib2, iclass 20, count 0 2006.201.18:55:26.90#ibcon#*after write, iclass 20, count 0 2006.201.18:55:26.90#ibcon#*before return 0, iclass 20, count 0 2006.201.18:55:26.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:26.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.18:55:26.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.18:55:26.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.18:55:26.90$vck44/vblo=8,744.99 2006.201.18:55:26.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.18:55:26.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.18:55:26.90#ibcon#ireg 17 cls_cnt 0 2006.201.18:55:26.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:26.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:26.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:26.90#ibcon#enter wrdev, iclass 22, count 0 2006.201.18:55:26.90#ibcon#first serial, iclass 22, count 0 2006.201.18:55:26.90#ibcon#enter sib2, iclass 22, count 0 2006.201.18:55:26.90#ibcon#flushed, iclass 22, count 0 2006.201.18:55:26.90#ibcon#about to write, iclass 22, count 0 2006.201.18:55:26.90#ibcon#wrote, iclass 22, count 0 2006.201.18:55:26.90#ibcon#about to read 3, iclass 22, count 0 2006.201.18:55:26.92#ibcon#read 3, iclass 22, count 0 2006.201.18:55:26.92#ibcon#about to read 4, iclass 22, count 0 2006.201.18:55:26.92#ibcon#read 4, iclass 22, count 0 2006.201.18:55:26.92#ibcon#about to read 5, iclass 22, count 0 2006.201.18:55:26.92#ibcon#read 5, iclass 22, count 0 2006.201.18:55:26.92#ibcon#about to read 6, iclass 22, count 0 2006.201.18:55:26.92#ibcon#read 6, iclass 22, count 0 2006.201.18:55:26.92#ibcon#end of sib2, iclass 22, count 0 2006.201.18:55:26.92#ibcon#*mode == 0, iclass 22, count 0 2006.201.18:55:26.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.18:55:26.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.18:55:26.92#ibcon#*before write, iclass 22, count 0 2006.201.18:55:26.92#ibcon#enter sib2, iclass 22, count 0 2006.201.18:55:26.92#ibcon#flushed, iclass 22, count 0 2006.201.18:55:26.92#ibcon#about to write, iclass 22, count 0 2006.201.18:55:26.92#ibcon#wrote, iclass 22, count 0 2006.201.18:55:26.92#ibcon#about to read 3, iclass 22, count 0 2006.201.18:55:26.96#ibcon#read 3, iclass 22, count 0 2006.201.18:55:26.96#ibcon#about to read 4, iclass 22, count 0 2006.201.18:55:26.96#ibcon#read 4, iclass 22, count 0 2006.201.18:55:26.96#ibcon#about to read 5, iclass 22, count 0 2006.201.18:55:26.96#ibcon#read 5, iclass 22, count 0 2006.201.18:55:26.96#ibcon#about to read 6, iclass 22, count 0 2006.201.18:55:26.96#ibcon#read 6, iclass 22, count 0 2006.201.18:55:26.96#ibcon#end of sib2, iclass 22, count 0 2006.201.18:55:26.96#ibcon#*after write, iclass 22, count 0 2006.201.18:55:26.96#ibcon#*before return 0, iclass 22, count 0 2006.201.18:55:26.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:26.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.18:55:26.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.18:55:26.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.18:55:26.96$vck44/vb=8,4 2006.201.18:55:26.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.18:55:26.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.18:55:26.96#ibcon#ireg 11 cls_cnt 2 2006.201.18:55:26.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:27.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:27.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:27.02#ibcon#enter wrdev, iclass 24, count 2 2006.201.18:55:27.02#ibcon#first serial, iclass 24, count 2 2006.201.18:55:27.02#ibcon#enter sib2, iclass 24, count 2 2006.201.18:55:27.02#ibcon#flushed, iclass 24, count 2 2006.201.18:55:27.02#ibcon#about to write, iclass 24, count 2 2006.201.18:55:27.02#ibcon#wrote, iclass 24, count 2 2006.201.18:55:27.02#ibcon#about to read 3, iclass 24, count 2 2006.201.18:55:27.04#ibcon#read 3, iclass 24, count 2 2006.201.18:55:27.04#ibcon#about to read 4, iclass 24, count 2 2006.201.18:55:27.04#ibcon#read 4, iclass 24, count 2 2006.201.18:55:27.04#ibcon#about to read 5, iclass 24, count 2 2006.201.18:55:27.04#ibcon#read 5, iclass 24, count 2 2006.201.18:55:27.04#ibcon#about to read 6, iclass 24, count 2 2006.201.18:55:27.04#ibcon#read 6, iclass 24, count 2 2006.201.18:55:27.04#ibcon#end of sib2, iclass 24, count 2 2006.201.18:55:27.04#ibcon#*mode == 0, iclass 24, count 2 2006.201.18:55:27.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.18:55:27.04#ibcon#[27=AT08-04\r\n] 2006.201.18:55:27.04#ibcon#*before write, iclass 24, count 2 2006.201.18:55:27.04#ibcon#enter sib2, iclass 24, count 2 2006.201.18:55:27.04#ibcon#flushed, iclass 24, count 2 2006.201.18:55:27.04#ibcon#about to write, iclass 24, count 2 2006.201.18:55:27.04#ibcon#wrote, iclass 24, count 2 2006.201.18:55:27.04#ibcon#about to read 3, iclass 24, count 2 2006.201.18:55:27.07#ibcon#read 3, iclass 24, count 2 2006.201.18:55:27.07#ibcon#about to read 4, iclass 24, count 2 2006.201.18:55:27.07#ibcon#read 4, iclass 24, count 2 2006.201.18:55:27.07#ibcon#about to read 5, iclass 24, count 2 2006.201.18:55:27.07#ibcon#read 5, iclass 24, count 2 2006.201.18:55:27.07#ibcon#about to read 6, iclass 24, count 2 2006.201.18:55:27.07#ibcon#read 6, iclass 24, count 2 2006.201.18:55:27.07#ibcon#end of sib2, iclass 24, count 2 2006.201.18:55:27.07#ibcon#*after write, iclass 24, count 2 2006.201.18:55:27.07#ibcon#*before return 0, iclass 24, count 2 2006.201.18:55:27.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:27.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.18:55:27.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.18:55:27.07#ibcon#ireg 7 cls_cnt 0 2006.201.18:55:27.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:27.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:27.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:27.19#ibcon#enter wrdev, iclass 24, count 0 2006.201.18:55:27.19#ibcon#first serial, iclass 24, count 0 2006.201.18:55:27.19#ibcon#enter sib2, iclass 24, count 0 2006.201.18:55:27.19#ibcon#flushed, iclass 24, count 0 2006.201.18:55:27.19#ibcon#about to write, iclass 24, count 0 2006.201.18:55:27.19#ibcon#wrote, iclass 24, count 0 2006.201.18:55:27.19#ibcon#about to read 3, iclass 24, count 0 2006.201.18:55:27.21#ibcon#read 3, iclass 24, count 0 2006.201.18:55:27.21#ibcon#about to read 4, iclass 24, count 0 2006.201.18:55:27.21#ibcon#read 4, iclass 24, count 0 2006.201.18:55:27.21#ibcon#about to read 5, iclass 24, count 0 2006.201.18:55:27.21#ibcon#read 5, iclass 24, count 0 2006.201.18:55:27.21#ibcon#about to read 6, iclass 24, count 0 2006.201.18:55:27.21#ibcon#read 6, iclass 24, count 0 2006.201.18:55:27.21#ibcon#end of sib2, iclass 24, count 0 2006.201.18:55:27.21#ibcon#*mode == 0, iclass 24, count 0 2006.201.18:55:27.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.18:55:27.21#ibcon#[27=USB\r\n] 2006.201.18:55:27.21#ibcon#*before write, iclass 24, count 0 2006.201.18:55:27.21#ibcon#enter sib2, iclass 24, count 0 2006.201.18:55:27.21#ibcon#flushed, iclass 24, count 0 2006.201.18:55:27.21#ibcon#about to write, iclass 24, count 0 2006.201.18:55:27.21#ibcon#wrote, iclass 24, count 0 2006.201.18:55:27.21#ibcon#about to read 3, iclass 24, count 0 2006.201.18:55:27.24#ibcon#read 3, iclass 24, count 0 2006.201.18:55:27.24#ibcon#about to read 4, iclass 24, count 0 2006.201.18:55:27.24#ibcon#read 4, iclass 24, count 0 2006.201.18:55:27.24#ibcon#about to read 5, iclass 24, count 0 2006.201.18:55:27.24#ibcon#read 5, iclass 24, count 0 2006.201.18:55:27.24#ibcon#about to read 6, iclass 24, count 0 2006.201.18:55:27.24#ibcon#read 6, iclass 24, count 0 2006.201.18:55:27.24#ibcon#end of sib2, iclass 24, count 0 2006.201.18:55:27.24#ibcon#*after write, iclass 24, count 0 2006.201.18:55:27.24#ibcon#*before return 0, iclass 24, count 0 2006.201.18:55:27.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:27.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.18:55:27.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.18:55:27.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.18:55:27.24$vck44/vabw=wide 2006.201.18:55:27.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.18:55:27.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.18:55:27.24#ibcon#ireg 8 cls_cnt 0 2006.201.18:55:27.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:27.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:27.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:27.24#ibcon#enter wrdev, iclass 26, count 0 2006.201.18:55:27.24#ibcon#first serial, iclass 26, count 0 2006.201.18:55:27.24#ibcon#enter sib2, iclass 26, count 0 2006.201.18:55:27.24#ibcon#flushed, iclass 26, count 0 2006.201.18:55:27.24#ibcon#about to write, iclass 26, count 0 2006.201.18:55:27.24#ibcon#wrote, iclass 26, count 0 2006.201.18:55:27.24#ibcon#about to read 3, iclass 26, count 0 2006.201.18:55:27.26#ibcon#read 3, iclass 26, count 0 2006.201.18:55:27.26#ibcon#about to read 4, iclass 26, count 0 2006.201.18:55:27.26#ibcon#read 4, iclass 26, count 0 2006.201.18:55:27.26#ibcon#about to read 5, iclass 26, count 0 2006.201.18:55:27.26#ibcon#read 5, iclass 26, count 0 2006.201.18:55:27.26#ibcon#about to read 6, iclass 26, count 0 2006.201.18:55:27.26#ibcon#read 6, iclass 26, count 0 2006.201.18:55:27.26#ibcon#end of sib2, iclass 26, count 0 2006.201.18:55:27.26#ibcon#*mode == 0, iclass 26, count 0 2006.201.18:55:27.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.18:55:27.26#ibcon#[25=BW32\r\n] 2006.201.18:55:27.26#ibcon#*before write, iclass 26, count 0 2006.201.18:55:27.26#ibcon#enter sib2, iclass 26, count 0 2006.201.18:55:27.26#ibcon#flushed, iclass 26, count 0 2006.201.18:55:27.26#ibcon#about to write, iclass 26, count 0 2006.201.18:55:27.26#ibcon#wrote, iclass 26, count 0 2006.201.18:55:27.26#ibcon#about to read 3, iclass 26, count 0 2006.201.18:55:27.29#ibcon#read 3, iclass 26, count 0 2006.201.18:55:27.29#ibcon#about to read 4, iclass 26, count 0 2006.201.18:55:27.29#ibcon#read 4, iclass 26, count 0 2006.201.18:55:27.29#ibcon#about to read 5, iclass 26, count 0 2006.201.18:55:27.29#ibcon#read 5, iclass 26, count 0 2006.201.18:55:27.29#ibcon#about to read 6, iclass 26, count 0 2006.201.18:55:27.29#ibcon#read 6, iclass 26, count 0 2006.201.18:55:27.29#ibcon#end of sib2, iclass 26, count 0 2006.201.18:55:27.29#ibcon#*after write, iclass 26, count 0 2006.201.18:55:27.29#ibcon#*before return 0, iclass 26, count 0 2006.201.18:55:27.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:27.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.18:55:27.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.18:55:27.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.18:55:27.29$vck44/vbbw=wide 2006.201.18:55:27.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.18:55:27.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.18:55:27.29#ibcon#ireg 8 cls_cnt 0 2006.201.18:55:27.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:55:27.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:55:27.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:55:27.36#ibcon#enter wrdev, iclass 28, count 0 2006.201.18:55:27.36#ibcon#first serial, iclass 28, count 0 2006.201.18:55:27.36#ibcon#enter sib2, iclass 28, count 0 2006.201.18:55:27.36#ibcon#flushed, iclass 28, count 0 2006.201.18:55:27.36#ibcon#about to write, iclass 28, count 0 2006.201.18:55:27.36#ibcon#wrote, iclass 28, count 0 2006.201.18:55:27.36#ibcon#about to read 3, iclass 28, count 0 2006.201.18:55:27.38#ibcon#read 3, iclass 28, count 0 2006.201.18:55:27.38#ibcon#about to read 4, iclass 28, count 0 2006.201.18:55:27.38#ibcon#read 4, iclass 28, count 0 2006.201.18:55:27.38#ibcon#about to read 5, iclass 28, count 0 2006.201.18:55:27.38#ibcon#read 5, iclass 28, count 0 2006.201.18:55:27.38#ibcon#about to read 6, iclass 28, count 0 2006.201.18:55:27.38#ibcon#read 6, iclass 28, count 0 2006.201.18:55:27.38#ibcon#end of sib2, iclass 28, count 0 2006.201.18:55:27.38#ibcon#*mode == 0, iclass 28, count 0 2006.201.18:55:27.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.18:55:27.38#ibcon#[27=BW32\r\n] 2006.201.18:55:27.38#ibcon#*before write, iclass 28, count 0 2006.201.18:55:27.38#ibcon#enter sib2, iclass 28, count 0 2006.201.18:55:27.38#ibcon#flushed, iclass 28, count 0 2006.201.18:55:27.38#ibcon#about to write, iclass 28, count 0 2006.201.18:55:27.38#ibcon#wrote, iclass 28, count 0 2006.201.18:55:27.38#ibcon#about to read 3, iclass 28, count 0 2006.201.18:55:27.41#ibcon#read 3, iclass 28, count 0 2006.201.18:55:27.41#ibcon#about to read 4, iclass 28, count 0 2006.201.18:55:27.41#ibcon#read 4, iclass 28, count 0 2006.201.18:55:27.41#ibcon#about to read 5, iclass 28, count 0 2006.201.18:55:27.41#ibcon#read 5, iclass 28, count 0 2006.201.18:55:27.41#ibcon#about to read 6, iclass 28, count 0 2006.201.18:55:27.41#ibcon#read 6, iclass 28, count 0 2006.201.18:55:27.41#ibcon#end of sib2, iclass 28, count 0 2006.201.18:55:27.41#ibcon#*after write, iclass 28, count 0 2006.201.18:55:27.41#ibcon#*before return 0, iclass 28, count 0 2006.201.18:55:27.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:55:27.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.18:55:27.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.18:55:27.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.18:55:27.41$setupk4/ifdk4 2006.201.18:55:27.41$ifdk4/lo= 2006.201.18:55:27.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.18:55:27.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.18:55:27.41$ifdk4/patch= 2006.201.18:55:27.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.18:55:27.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.18:55:27.41$setupk4/!*+20s 2006.201.18:55:32.47#abcon#<5=/04 1.1 2.0 20.501001002.1\r\n> 2006.201.18:55:32.49#abcon#{5=INTERFACE CLEAR} 2006.201.18:55:32.56#abcon#[5=S1D000X0/0*\r\n] 2006.201.18:55:36.14#trakl#Source acquired 2006.201.18:55:38.14#flagr#flagr/antenna,acquired 2006.201.18:55:41.88$setupk4/"tpicd 2006.201.18:55:41.88$setupk4/echo=off 2006.201.18:55:41.88$setupk4/xlog=off 2006.201.18:55:41.88:!2006.201.18:58:49 2006.201.18:58:49.00:preob 2006.201.18:58:49.14/onsource/TRACKING 2006.201.18:58:49.14:!2006.201.18:58:59 2006.201.18:58:59.00:"tape 2006.201.18:58:59.00:"st=record 2006.201.18:58:59.00:data_valid=on 2006.201.18:58:59.00:midob 2006.201.18:58:59.14/onsource/TRACKING 2006.201.18:58:59.14/wx/20.51,1002.1,100 2006.201.18:58:59.21/cable/+6.4790E-03 2006.201.18:59:00.30/va/01,08,usb,yes,44,47 2006.201.18:59:00.30/va/02,07,usb,yes,47,48 2006.201.18:59:00.30/va/03,08,usb,yes,43,45 2006.201.18:59:00.30/va/04,07,usb,yes,49,51 2006.201.18:59:00.30/va/05,04,usb,yes,43,44 2006.201.18:59:00.30/va/06,05,usb,yes,44,44 2006.201.18:59:00.30/va/07,05,usb,yes,43,44 2006.201.18:59:00.30/va/08,04,usb,yes,42,50 2006.201.18:59:00.53/valo/01,524.99,yes,locked 2006.201.18:59:00.53/valo/02,534.99,yes,locked 2006.201.18:59:00.53/valo/03,564.99,yes,locked 2006.201.18:59:00.53/valo/04,624.99,yes,locked 2006.201.18:59:00.53/valo/05,734.99,yes,locked 2006.201.18:59:00.53/valo/06,814.99,yes,locked 2006.201.18:59:00.53/valo/07,864.99,yes,locked 2006.201.18:59:00.53/valo/08,884.99,yes,locked 2006.201.18:59:01.62/vb/01,04,usb,yes,31,29 2006.201.18:59:01.62/vb/02,05,usb,yes,29,29 2006.201.18:59:01.62/vb/03,04,usb,yes,30,33 2006.201.18:59:01.62/vb/04,05,usb,yes,31,30 2006.201.18:59:01.62/vb/05,04,usb,yes,27,30 2006.201.18:59:01.62/vb/06,04,usb,yes,32,28 2006.201.18:59:01.62/vb/07,04,usb,yes,32,31 2006.201.18:59:01.62/vb/08,04,usb,yes,29,32 2006.201.18:59:01.85/vblo/01,629.99,yes,locked 2006.201.18:59:01.85/vblo/02,634.99,yes,locked 2006.201.18:59:01.85/vblo/03,649.99,yes,locked 2006.201.18:59:01.85/vblo/04,679.99,yes,locked 2006.201.18:59:01.85/vblo/05,709.99,yes,locked 2006.201.18:59:01.85/vblo/06,719.99,yes,locked 2006.201.18:59:01.85/vblo/07,734.99,yes,locked 2006.201.18:59:01.85/vblo/08,744.99,yes,locked 2006.201.18:59:02.00/vabw/8 2006.201.18:59:02.15/vbbw/8 2006.201.18:59:02.24/xfe/off,on,15.5 2006.201.18:59:02.61/ifatt/23,28,28,28 2006.201.18:59:03.07/fmout-gps/S +4.48E-07 2006.201.18:59:03.11:!2006.201.19:00:49 2006.201.19:00:49.00:data_valid=off 2006.201.19:00:49.00:"et 2006.201.19:00:49.00:!+3s 2006.201.19:00:52.02:"tape 2006.201.19:00:52.02:postob 2006.201.19:00:52.21/cable/+6.4763E-03 2006.201.19:00:52.21/wx/20.51,1002.1,100 2006.201.19:00:52.27/fmout-gps/S +4.48E-07 2006.201.19:00:52.27:scan_name=201-1907,jd0607,260 2006.201.19:00:52.27:source=1044+719,104827.62,714335.9,2000.0,neutral 2006.201.19:00:53.13#flagr#flagr/antenna,new-source 2006.201.19:00:53.13:checkk5 2006.201.19:00:53.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:00:53.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:00:54.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:00:54.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:00:55.01/chk_obsdata//k5ts1/T2011858??a.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.19:00:55.37/chk_obsdata//k5ts2/T2011858??b.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.19:00:55.74/chk_obsdata//k5ts3/T2011858??c.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.19:00:56.11/chk_obsdata//k5ts4/T2011858??d.dat file size is correct (nominal:440MB, actual:436MB). 2006.201.19:00:56.79/k5log//k5ts1_log_newline 2006.201.19:00:57.48/k5log//k5ts2_log_newline 2006.201.19:00:58.17/k5log//k5ts3_log_newline 2006.201.19:00:58.85/k5log//k5ts4_log_newline 2006.201.19:00:58.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:00:58.88:setupk4=1 2006.201.19:00:58.88$setupk4/echo=on 2006.201.19:00:58.88$setupk4/pcalon 2006.201.19:00:58.88$pcalon/"no phase cal control is implemented here 2006.201.19:00:58.88$setupk4/"tpicd=stop 2006.201.19:00:58.88$setupk4/"rec=synch_on 2006.201.19:00:58.88$setupk4/"rec_mode=128 2006.201.19:00:58.88$setupk4/!* 2006.201.19:00:58.88$setupk4/recpk4 2006.201.19:00:58.88$recpk4/recpatch= 2006.201.19:00:58.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:00:58.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:00:58.88$setupk4/vck44 2006.201.19:00:58.88$vck44/valo=1,524.99 2006.201.19:00:58.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.19:00:58.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.19:00:58.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:00:58.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:00:58.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:00:58.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:00:58.88#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:00:58.88#ibcon#first serial, iclass 21, count 0 2006.201.19:00:58.88#ibcon#enter sib2, iclass 21, count 0 2006.201.19:00:58.88#ibcon#flushed, iclass 21, count 0 2006.201.19:00:58.88#ibcon#about to write, iclass 21, count 0 2006.201.19:00:58.88#ibcon#wrote, iclass 21, count 0 2006.201.19:00:58.88#ibcon#about to read 3, iclass 21, count 0 2006.201.19:00:58.90#ibcon#read 3, iclass 21, count 0 2006.201.19:00:58.90#ibcon#about to read 4, iclass 21, count 0 2006.201.19:00:58.90#ibcon#read 4, iclass 21, count 0 2006.201.19:00:58.90#ibcon#about to read 5, iclass 21, count 0 2006.201.19:00:58.90#ibcon#read 5, iclass 21, count 0 2006.201.19:00:58.90#ibcon#about to read 6, iclass 21, count 0 2006.201.19:00:58.90#ibcon#read 6, iclass 21, count 0 2006.201.19:00:58.90#ibcon#end of sib2, iclass 21, count 0 2006.201.19:00:58.90#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:00:58.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:00:58.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:00:58.90#ibcon#*before write, iclass 21, count 0 2006.201.19:00:58.90#ibcon#enter sib2, iclass 21, count 0 2006.201.19:00:58.90#ibcon#flushed, iclass 21, count 0 2006.201.19:00:58.90#ibcon#about to write, iclass 21, count 0 2006.201.19:00:58.90#ibcon#wrote, iclass 21, count 0 2006.201.19:00:58.90#ibcon#about to read 3, iclass 21, count 0 2006.201.19:00:58.95#ibcon#read 3, iclass 21, count 0 2006.201.19:00:58.95#ibcon#about to read 4, iclass 21, count 0 2006.201.19:00:58.95#ibcon#read 4, iclass 21, count 0 2006.201.19:00:58.95#ibcon#about to read 5, iclass 21, count 0 2006.201.19:00:58.95#ibcon#read 5, iclass 21, count 0 2006.201.19:00:58.95#ibcon#about to read 6, iclass 21, count 0 2006.201.19:00:58.95#ibcon#read 6, iclass 21, count 0 2006.201.19:00:58.95#ibcon#end of sib2, iclass 21, count 0 2006.201.19:00:58.95#ibcon#*after write, iclass 21, count 0 2006.201.19:00:58.95#ibcon#*before return 0, iclass 21, count 0 2006.201.19:00:58.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:00:58.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:00:58.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:00:58.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:00:58.95$vck44/va=1,8 2006.201.19:00:58.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.19:00:58.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.19:00:58.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:00:58.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:00:58.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:00:58.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:00:58.95#ibcon#enter wrdev, iclass 23, count 2 2006.201.19:00:58.95#ibcon#first serial, iclass 23, count 2 2006.201.19:00:58.95#ibcon#enter sib2, iclass 23, count 2 2006.201.19:00:58.95#ibcon#flushed, iclass 23, count 2 2006.201.19:00:58.95#ibcon#about to write, iclass 23, count 2 2006.201.19:00:58.95#ibcon#wrote, iclass 23, count 2 2006.201.19:00:58.95#ibcon#about to read 3, iclass 23, count 2 2006.201.19:00:58.97#ibcon#read 3, iclass 23, count 2 2006.201.19:00:58.97#ibcon#about to read 4, iclass 23, count 2 2006.201.19:00:58.97#ibcon#read 4, iclass 23, count 2 2006.201.19:00:58.97#ibcon#about to read 5, iclass 23, count 2 2006.201.19:00:58.97#ibcon#read 5, iclass 23, count 2 2006.201.19:00:58.97#ibcon#about to read 6, iclass 23, count 2 2006.201.19:00:58.97#ibcon#read 6, iclass 23, count 2 2006.201.19:00:58.97#ibcon#end of sib2, iclass 23, count 2 2006.201.19:00:58.97#ibcon#*mode == 0, iclass 23, count 2 2006.201.19:00:58.97#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.19:00:58.97#ibcon#[25=AT01-08\r\n] 2006.201.19:00:58.97#ibcon#*before write, iclass 23, count 2 2006.201.19:00:58.97#ibcon#enter sib2, iclass 23, count 2 2006.201.19:00:58.97#ibcon#flushed, iclass 23, count 2 2006.201.19:00:58.97#ibcon#about to write, iclass 23, count 2 2006.201.19:00:58.97#ibcon#wrote, iclass 23, count 2 2006.201.19:00:58.97#ibcon#about to read 3, iclass 23, count 2 2006.201.19:00:59.00#ibcon#read 3, iclass 23, count 2 2006.201.19:00:59.00#ibcon#about to read 4, iclass 23, count 2 2006.201.19:00:59.00#ibcon#read 4, iclass 23, count 2 2006.201.19:00:59.00#ibcon#about to read 5, iclass 23, count 2 2006.201.19:00:59.00#ibcon#read 5, iclass 23, count 2 2006.201.19:00:59.00#ibcon#about to read 6, iclass 23, count 2 2006.201.19:00:59.00#ibcon#read 6, iclass 23, count 2 2006.201.19:00:59.00#ibcon#end of sib2, iclass 23, count 2 2006.201.19:00:59.00#ibcon#*after write, iclass 23, count 2 2006.201.19:00:59.00#ibcon#*before return 0, iclass 23, count 2 2006.201.19:00:59.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:00:59.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:00:59.00#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.19:00:59.00#ibcon#ireg 7 cls_cnt 0 2006.201.19:00:59.00#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:00:59.12#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:00:59.12#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:00:59.12#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:00:59.12#ibcon#first serial, iclass 23, count 0 2006.201.19:00:59.12#ibcon#enter sib2, iclass 23, count 0 2006.201.19:00:59.12#ibcon#flushed, iclass 23, count 0 2006.201.19:00:59.12#ibcon#about to write, iclass 23, count 0 2006.201.19:00:59.12#ibcon#wrote, iclass 23, count 0 2006.201.19:00:59.12#ibcon#about to read 3, iclass 23, count 0 2006.201.19:00:59.14#ibcon#read 3, iclass 23, count 0 2006.201.19:00:59.14#ibcon#about to read 4, iclass 23, count 0 2006.201.19:00:59.14#ibcon#read 4, iclass 23, count 0 2006.201.19:00:59.14#ibcon#about to read 5, iclass 23, count 0 2006.201.19:00:59.14#ibcon#read 5, iclass 23, count 0 2006.201.19:00:59.14#ibcon#about to read 6, iclass 23, count 0 2006.201.19:00:59.14#ibcon#read 6, iclass 23, count 0 2006.201.19:00:59.14#ibcon#end of sib2, iclass 23, count 0 2006.201.19:00:59.14#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:00:59.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:00:59.14#ibcon#[25=USB\r\n] 2006.201.19:00:59.14#ibcon#*before write, iclass 23, count 0 2006.201.19:00:59.14#ibcon#enter sib2, iclass 23, count 0 2006.201.19:00:59.14#ibcon#flushed, iclass 23, count 0 2006.201.19:00:59.14#ibcon#about to write, iclass 23, count 0 2006.201.19:00:59.14#ibcon#wrote, iclass 23, count 0 2006.201.19:00:59.14#ibcon#about to read 3, iclass 23, count 0 2006.201.19:00:59.17#ibcon#read 3, iclass 23, count 0 2006.201.19:00:59.17#ibcon#about to read 4, iclass 23, count 0 2006.201.19:00:59.17#ibcon#read 4, iclass 23, count 0 2006.201.19:00:59.17#ibcon#about to read 5, iclass 23, count 0 2006.201.19:00:59.17#ibcon#read 5, iclass 23, count 0 2006.201.19:00:59.17#ibcon#about to read 6, iclass 23, count 0 2006.201.19:00:59.17#ibcon#read 6, iclass 23, count 0 2006.201.19:00:59.17#ibcon#end of sib2, iclass 23, count 0 2006.201.19:00:59.17#ibcon#*after write, iclass 23, count 0 2006.201.19:00:59.17#ibcon#*before return 0, iclass 23, count 0 2006.201.19:00:59.17#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:00:59.17#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:00:59.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:00:59.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:00:59.17$vck44/valo=2,534.99 2006.201.19:00:59.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.19:00:59.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.19:00:59.17#ibcon#ireg 17 cls_cnt 0 2006.201.19:00:59.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:00:59.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:00:59.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:00:59.17#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:00:59.17#ibcon#first serial, iclass 25, count 0 2006.201.19:00:59.17#ibcon#enter sib2, iclass 25, count 0 2006.201.19:00:59.17#ibcon#flushed, iclass 25, count 0 2006.201.19:00:59.17#ibcon#about to write, iclass 25, count 0 2006.201.19:00:59.17#ibcon#wrote, iclass 25, count 0 2006.201.19:00:59.17#ibcon#about to read 3, iclass 25, count 0 2006.201.19:00:59.19#ibcon#read 3, iclass 25, count 0 2006.201.19:00:59.19#ibcon#about to read 4, iclass 25, count 0 2006.201.19:00:59.19#ibcon#read 4, iclass 25, count 0 2006.201.19:00:59.19#ibcon#about to read 5, iclass 25, count 0 2006.201.19:00:59.19#ibcon#read 5, iclass 25, count 0 2006.201.19:00:59.19#ibcon#about to read 6, iclass 25, count 0 2006.201.19:00:59.19#ibcon#read 6, iclass 25, count 0 2006.201.19:00:59.19#ibcon#end of sib2, iclass 25, count 0 2006.201.19:00:59.19#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:00:59.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:00:59.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:00:59.19#ibcon#*before write, iclass 25, count 0 2006.201.19:00:59.19#ibcon#enter sib2, iclass 25, count 0 2006.201.19:00:59.19#ibcon#flushed, iclass 25, count 0 2006.201.19:00:59.19#ibcon#about to write, iclass 25, count 0 2006.201.19:00:59.19#ibcon#wrote, iclass 25, count 0 2006.201.19:00:59.19#ibcon#about to read 3, iclass 25, count 0 2006.201.19:00:59.24#ibcon#read 3, iclass 25, count 0 2006.201.19:00:59.24#ibcon#about to read 4, iclass 25, count 0 2006.201.19:00:59.24#ibcon#read 4, iclass 25, count 0 2006.201.19:00:59.24#ibcon#about to read 5, iclass 25, count 0 2006.201.19:00:59.24#ibcon#read 5, iclass 25, count 0 2006.201.19:00:59.24#ibcon#about to read 6, iclass 25, count 0 2006.201.19:00:59.24#ibcon#read 6, iclass 25, count 0 2006.201.19:00:59.24#ibcon#end of sib2, iclass 25, count 0 2006.201.19:00:59.24#ibcon#*after write, iclass 25, count 0 2006.201.19:00:59.24#ibcon#*before return 0, iclass 25, count 0 2006.201.19:00:59.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:00:59.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:00:59.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:00:59.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:00:59.24$vck44/va=2,7 2006.201.19:00:59.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.19:00:59.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.19:00:59.24#ibcon#ireg 11 cls_cnt 2 2006.201.19:00:59.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:00:59.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:00:59.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:00:59.29#ibcon#enter wrdev, iclass 27, count 2 2006.201.19:00:59.29#ibcon#first serial, iclass 27, count 2 2006.201.19:00:59.29#ibcon#enter sib2, iclass 27, count 2 2006.201.19:00:59.29#ibcon#flushed, iclass 27, count 2 2006.201.19:00:59.29#ibcon#about to write, iclass 27, count 2 2006.201.19:00:59.29#ibcon#wrote, iclass 27, count 2 2006.201.19:00:59.29#ibcon#about to read 3, iclass 27, count 2 2006.201.19:00:59.31#ibcon#read 3, iclass 27, count 2 2006.201.19:00:59.31#ibcon#about to read 4, iclass 27, count 2 2006.201.19:00:59.31#ibcon#read 4, iclass 27, count 2 2006.201.19:00:59.31#ibcon#about to read 5, iclass 27, count 2 2006.201.19:00:59.31#ibcon#read 5, iclass 27, count 2 2006.201.19:00:59.31#ibcon#about to read 6, iclass 27, count 2 2006.201.19:00:59.31#ibcon#read 6, iclass 27, count 2 2006.201.19:00:59.31#ibcon#end of sib2, iclass 27, count 2 2006.201.19:00:59.31#ibcon#*mode == 0, iclass 27, count 2 2006.201.19:00:59.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.19:00:59.31#ibcon#[25=AT02-07\r\n] 2006.201.19:00:59.31#ibcon#*before write, iclass 27, count 2 2006.201.19:00:59.31#ibcon#enter sib2, iclass 27, count 2 2006.201.19:00:59.31#ibcon#flushed, iclass 27, count 2 2006.201.19:00:59.31#ibcon#about to write, iclass 27, count 2 2006.201.19:00:59.31#ibcon#wrote, iclass 27, count 2 2006.201.19:00:59.31#ibcon#about to read 3, iclass 27, count 2 2006.201.19:00:59.34#ibcon#read 3, iclass 27, count 2 2006.201.19:00:59.34#ibcon#about to read 4, iclass 27, count 2 2006.201.19:00:59.34#ibcon#read 4, iclass 27, count 2 2006.201.19:00:59.34#ibcon#about to read 5, iclass 27, count 2 2006.201.19:00:59.34#ibcon#read 5, iclass 27, count 2 2006.201.19:00:59.34#ibcon#about to read 6, iclass 27, count 2 2006.201.19:00:59.34#ibcon#read 6, iclass 27, count 2 2006.201.19:00:59.34#ibcon#end of sib2, iclass 27, count 2 2006.201.19:00:59.34#ibcon#*after write, iclass 27, count 2 2006.201.19:00:59.34#ibcon#*before return 0, iclass 27, count 2 2006.201.19:00:59.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:00:59.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:00:59.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.19:00:59.34#ibcon#ireg 7 cls_cnt 0 2006.201.19:00:59.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:00:59.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:00:59.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:00:59.46#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:00:59.46#ibcon#first serial, iclass 27, count 0 2006.201.19:00:59.46#ibcon#enter sib2, iclass 27, count 0 2006.201.19:00:59.46#ibcon#flushed, iclass 27, count 0 2006.201.19:00:59.46#ibcon#about to write, iclass 27, count 0 2006.201.19:00:59.46#ibcon#wrote, iclass 27, count 0 2006.201.19:00:59.46#ibcon#about to read 3, iclass 27, count 0 2006.201.19:00:59.48#ibcon#read 3, iclass 27, count 0 2006.201.19:00:59.48#ibcon#about to read 4, iclass 27, count 0 2006.201.19:00:59.48#ibcon#read 4, iclass 27, count 0 2006.201.19:00:59.48#ibcon#about to read 5, iclass 27, count 0 2006.201.19:00:59.48#ibcon#read 5, iclass 27, count 0 2006.201.19:00:59.48#ibcon#about to read 6, iclass 27, count 0 2006.201.19:00:59.48#ibcon#read 6, iclass 27, count 0 2006.201.19:00:59.48#ibcon#end of sib2, iclass 27, count 0 2006.201.19:00:59.48#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:00:59.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:00:59.48#ibcon#[25=USB\r\n] 2006.201.19:00:59.48#ibcon#*before write, iclass 27, count 0 2006.201.19:00:59.48#ibcon#enter sib2, iclass 27, count 0 2006.201.19:00:59.48#ibcon#flushed, iclass 27, count 0 2006.201.19:00:59.48#ibcon#about to write, iclass 27, count 0 2006.201.19:00:59.48#ibcon#wrote, iclass 27, count 0 2006.201.19:00:59.48#ibcon#about to read 3, iclass 27, count 0 2006.201.19:00:59.51#ibcon#read 3, iclass 27, count 0 2006.201.19:00:59.51#ibcon#about to read 4, iclass 27, count 0 2006.201.19:00:59.51#ibcon#read 4, iclass 27, count 0 2006.201.19:00:59.51#ibcon#about to read 5, iclass 27, count 0 2006.201.19:00:59.51#ibcon#read 5, iclass 27, count 0 2006.201.19:00:59.51#ibcon#about to read 6, iclass 27, count 0 2006.201.19:00:59.51#ibcon#read 6, iclass 27, count 0 2006.201.19:00:59.51#ibcon#end of sib2, iclass 27, count 0 2006.201.19:00:59.51#ibcon#*after write, iclass 27, count 0 2006.201.19:00:59.51#ibcon#*before return 0, iclass 27, count 0 2006.201.19:00:59.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:00:59.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:00:59.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:00:59.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:00:59.51$vck44/valo=3,564.99 2006.201.19:00:59.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.19:00:59.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.19:00:59.51#ibcon#ireg 17 cls_cnt 0 2006.201.19:00:59.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:00:59.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:00:59.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:00:59.51#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:00:59.51#ibcon#first serial, iclass 29, count 0 2006.201.19:00:59.51#ibcon#enter sib2, iclass 29, count 0 2006.201.19:00:59.51#ibcon#flushed, iclass 29, count 0 2006.201.19:00:59.51#ibcon#about to write, iclass 29, count 0 2006.201.19:00:59.51#ibcon#wrote, iclass 29, count 0 2006.201.19:00:59.51#ibcon#about to read 3, iclass 29, count 0 2006.201.19:00:59.53#ibcon#read 3, iclass 29, count 0 2006.201.19:00:59.53#ibcon#about to read 4, iclass 29, count 0 2006.201.19:00:59.53#ibcon#read 4, iclass 29, count 0 2006.201.19:00:59.53#ibcon#about to read 5, iclass 29, count 0 2006.201.19:00:59.53#ibcon#read 5, iclass 29, count 0 2006.201.19:00:59.53#ibcon#about to read 6, iclass 29, count 0 2006.201.19:00:59.53#ibcon#read 6, iclass 29, count 0 2006.201.19:00:59.53#ibcon#end of sib2, iclass 29, count 0 2006.201.19:00:59.53#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:00:59.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:00:59.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:00:59.53#ibcon#*before write, iclass 29, count 0 2006.201.19:00:59.53#ibcon#enter sib2, iclass 29, count 0 2006.201.19:00:59.53#ibcon#flushed, iclass 29, count 0 2006.201.19:00:59.53#ibcon#about to write, iclass 29, count 0 2006.201.19:00:59.53#ibcon#wrote, iclass 29, count 0 2006.201.19:00:59.53#ibcon#about to read 3, iclass 29, count 0 2006.201.19:00:59.58#ibcon#read 3, iclass 29, count 0 2006.201.19:00:59.58#ibcon#about to read 4, iclass 29, count 0 2006.201.19:00:59.58#ibcon#read 4, iclass 29, count 0 2006.201.19:00:59.58#ibcon#about to read 5, iclass 29, count 0 2006.201.19:00:59.58#ibcon#read 5, iclass 29, count 0 2006.201.19:00:59.58#ibcon#about to read 6, iclass 29, count 0 2006.201.19:00:59.58#ibcon#read 6, iclass 29, count 0 2006.201.19:00:59.58#ibcon#end of sib2, iclass 29, count 0 2006.201.19:00:59.58#ibcon#*after write, iclass 29, count 0 2006.201.19:00:59.58#ibcon#*before return 0, iclass 29, count 0 2006.201.19:00:59.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:00:59.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:00:59.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:00:59.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:00:59.58$vck44/va=3,8 2006.201.19:00:59.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.19:00:59.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.19:00:59.58#ibcon#ireg 11 cls_cnt 2 2006.201.19:00:59.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:00:59.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:00:59.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:00:59.63#ibcon#enter wrdev, iclass 31, count 2 2006.201.19:00:59.63#ibcon#first serial, iclass 31, count 2 2006.201.19:00:59.63#ibcon#enter sib2, iclass 31, count 2 2006.201.19:00:59.63#ibcon#flushed, iclass 31, count 2 2006.201.19:00:59.63#ibcon#about to write, iclass 31, count 2 2006.201.19:00:59.63#ibcon#wrote, iclass 31, count 2 2006.201.19:00:59.63#ibcon#about to read 3, iclass 31, count 2 2006.201.19:00:59.65#ibcon#read 3, iclass 31, count 2 2006.201.19:00:59.65#ibcon#about to read 4, iclass 31, count 2 2006.201.19:00:59.65#ibcon#read 4, iclass 31, count 2 2006.201.19:00:59.65#ibcon#about to read 5, iclass 31, count 2 2006.201.19:00:59.65#ibcon#read 5, iclass 31, count 2 2006.201.19:00:59.65#ibcon#about to read 6, iclass 31, count 2 2006.201.19:00:59.65#ibcon#read 6, iclass 31, count 2 2006.201.19:00:59.65#ibcon#end of sib2, iclass 31, count 2 2006.201.19:00:59.65#ibcon#*mode == 0, iclass 31, count 2 2006.201.19:00:59.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.19:00:59.65#ibcon#[25=AT03-08\r\n] 2006.201.19:00:59.65#ibcon#*before write, iclass 31, count 2 2006.201.19:00:59.65#ibcon#enter sib2, iclass 31, count 2 2006.201.19:00:59.65#ibcon#flushed, iclass 31, count 2 2006.201.19:00:59.65#ibcon#about to write, iclass 31, count 2 2006.201.19:00:59.65#ibcon#wrote, iclass 31, count 2 2006.201.19:00:59.65#ibcon#about to read 3, iclass 31, count 2 2006.201.19:00:59.68#ibcon#read 3, iclass 31, count 2 2006.201.19:00:59.68#ibcon#about to read 4, iclass 31, count 2 2006.201.19:00:59.68#ibcon#read 4, iclass 31, count 2 2006.201.19:00:59.68#ibcon#about to read 5, iclass 31, count 2 2006.201.19:00:59.68#ibcon#read 5, iclass 31, count 2 2006.201.19:00:59.68#ibcon#about to read 6, iclass 31, count 2 2006.201.19:00:59.68#ibcon#read 6, iclass 31, count 2 2006.201.19:00:59.68#ibcon#end of sib2, iclass 31, count 2 2006.201.19:00:59.68#ibcon#*after write, iclass 31, count 2 2006.201.19:00:59.68#ibcon#*before return 0, iclass 31, count 2 2006.201.19:00:59.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:00:59.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:00:59.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.19:00:59.68#ibcon#ireg 7 cls_cnt 0 2006.201.19:00:59.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:00:59.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:00:59.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:00:59.80#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:00:59.80#ibcon#first serial, iclass 31, count 0 2006.201.19:00:59.80#ibcon#enter sib2, iclass 31, count 0 2006.201.19:00:59.80#ibcon#flushed, iclass 31, count 0 2006.201.19:00:59.80#ibcon#about to write, iclass 31, count 0 2006.201.19:00:59.80#ibcon#wrote, iclass 31, count 0 2006.201.19:00:59.80#ibcon#about to read 3, iclass 31, count 0 2006.201.19:00:59.82#ibcon#read 3, iclass 31, count 0 2006.201.19:00:59.82#ibcon#about to read 4, iclass 31, count 0 2006.201.19:00:59.82#ibcon#read 4, iclass 31, count 0 2006.201.19:00:59.82#ibcon#about to read 5, iclass 31, count 0 2006.201.19:00:59.82#ibcon#read 5, iclass 31, count 0 2006.201.19:00:59.82#ibcon#about to read 6, iclass 31, count 0 2006.201.19:00:59.82#ibcon#read 6, iclass 31, count 0 2006.201.19:00:59.82#ibcon#end of sib2, iclass 31, count 0 2006.201.19:00:59.82#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:00:59.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:00:59.82#ibcon#[25=USB\r\n] 2006.201.19:00:59.82#ibcon#*before write, iclass 31, count 0 2006.201.19:00:59.82#ibcon#enter sib2, iclass 31, count 0 2006.201.19:00:59.82#ibcon#flushed, iclass 31, count 0 2006.201.19:00:59.82#ibcon#about to write, iclass 31, count 0 2006.201.19:00:59.82#ibcon#wrote, iclass 31, count 0 2006.201.19:00:59.82#ibcon#about to read 3, iclass 31, count 0 2006.201.19:00:59.85#ibcon#read 3, iclass 31, count 0 2006.201.19:00:59.85#ibcon#about to read 4, iclass 31, count 0 2006.201.19:00:59.85#ibcon#read 4, iclass 31, count 0 2006.201.19:00:59.85#ibcon#about to read 5, iclass 31, count 0 2006.201.19:00:59.85#ibcon#read 5, iclass 31, count 0 2006.201.19:00:59.85#ibcon#about to read 6, iclass 31, count 0 2006.201.19:00:59.85#ibcon#read 6, iclass 31, count 0 2006.201.19:00:59.85#ibcon#end of sib2, iclass 31, count 0 2006.201.19:00:59.85#ibcon#*after write, iclass 31, count 0 2006.201.19:00:59.85#ibcon#*before return 0, iclass 31, count 0 2006.201.19:00:59.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:00:59.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:00:59.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:00:59.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:00:59.85$vck44/valo=4,624.99 2006.201.19:00:59.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.19:00:59.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.19:00:59.85#ibcon#ireg 17 cls_cnt 0 2006.201.19:00:59.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:00:59.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:00:59.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:00:59.85#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:00:59.85#ibcon#first serial, iclass 33, count 0 2006.201.19:00:59.85#ibcon#enter sib2, iclass 33, count 0 2006.201.19:00:59.85#ibcon#flushed, iclass 33, count 0 2006.201.19:00:59.85#ibcon#about to write, iclass 33, count 0 2006.201.19:00:59.85#ibcon#wrote, iclass 33, count 0 2006.201.19:00:59.85#ibcon#about to read 3, iclass 33, count 0 2006.201.19:00:59.87#ibcon#read 3, iclass 33, count 0 2006.201.19:00:59.87#ibcon#about to read 4, iclass 33, count 0 2006.201.19:00:59.87#ibcon#read 4, iclass 33, count 0 2006.201.19:00:59.87#ibcon#about to read 5, iclass 33, count 0 2006.201.19:00:59.87#ibcon#read 5, iclass 33, count 0 2006.201.19:00:59.87#ibcon#about to read 6, iclass 33, count 0 2006.201.19:00:59.87#ibcon#read 6, iclass 33, count 0 2006.201.19:00:59.87#ibcon#end of sib2, iclass 33, count 0 2006.201.19:00:59.87#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:00:59.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:00:59.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:00:59.87#ibcon#*before write, iclass 33, count 0 2006.201.19:00:59.87#ibcon#enter sib2, iclass 33, count 0 2006.201.19:00:59.87#ibcon#flushed, iclass 33, count 0 2006.201.19:00:59.87#ibcon#about to write, iclass 33, count 0 2006.201.19:00:59.87#ibcon#wrote, iclass 33, count 0 2006.201.19:00:59.87#ibcon#about to read 3, iclass 33, count 0 2006.201.19:00:59.92#ibcon#read 3, iclass 33, count 0 2006.201.19:00:59.92#ibcon#about to read 4, iclass 33, count 0 2006.201.19:00:59.92#ibcon#read 4, iclass 33, count 0 2006.201.19:00:59.92#ibcon#about to read 5, iclass 33, count 0 2006.201.19:00:59.92#ibcon#read 5, iclass 33, count 0 2006.201.19:00:59.92#ibcon#about to read 6, iclass 33, count 0 2006.201.19:00:59.92#ibcon#read 6, iclass 33, count 0 2006.201.19:00:59.92#ibcon#end of sib2, iclass 33, count 0 2006.201.19:00:59.92#ibcon#*after write, iclass 33, count 0 2006.201.19:00:59.92#ibcon#*before return 0, iclass 33, count 0 2006.201.19:00:59.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:00:59.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:00:59.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:00:59.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:00:59.92$vck44/va=4,7 2006.201.19:00:59.92#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.19:00:59.92#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.19:00:59.92#ibcon#ireg 11 cls_cnt 2 2006.201.19:00:59.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:00:59.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:00:59.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:00:59.97#ibcon#enter wrdev, iclass 35, count 2 2006.201.19:00:59.97#ibcon#first serial, iclass 35, count 2 2006.201.19:00:59.97#ibcon#enter sib2, iclass 35, count 2 2006.201.19:00:59.97#ibcon#flushed, iclass 35, count 2 2006.201.19:00:59.97#ibcon#about to write, iclass 35, count 2 2006.201.19:00:59.97#ibcon#wrote, iclass 35, count 2 2006.201.19:00:59.97#ibcon#about to read 3, iclass 35, count 2 2006.201.19:00:59.99#ibcon#read 3, iclass 35, count 2 2006.201.19:00:59.99#ibcon#about to read 4, iclass 35, count 2 2006.201.19:00:59.99#ibcon#read 4, iclass 35, count 2 2006.201.19:00:59.99#ibcon#about to read 5, iclass 35, count 2 2006.201.19:00:59.99#ibcon#read 5, iclass 35, count 2 2006.201.19:00:59.99#ibcon#about to read 6, iclass 35, count 2 2006.201.19:00:59.99#ibcon#read 6, iclass 35, count 2 2006.201.19:00:59.99#ibcon#end of sib2, iclass 35, count 2 2006.201.19:00:59.99#ibcon#*mode == 0, iclass 35, count 2 2006.201.19:00:59.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.19:00:59.99#ibcon#[25=AT04-07\r\n] 2006.201.19:00:59.99#ibcon#*before write, iclass 35, count 2 2006.201.19:00:59.99#ibcon#enter sib2, iclass 35, count 2 2006.201.19:00:59.99#ibcon#flushed, iclass 35, count 2 2006.201.19:00:59.99#ibcon#about to write, iclass 35, count 2 2006.201.19:00:59.99#ibcon#wrote, iclass 35, count 2 2006.201.19:00:59.99#ibcon#about to read 3, iclass 35, count 2 2006.201.19:01:00.02#ibcon#read 3, iclass 35, count 2 2006.201.19:01:00.02#ibcon#about to read 4, iclass 35, count 2 2006.201.19:01:00.02#ibcon#read 4, iclass 35, count 2 2006.201.19:01:00.02#ibcon#about to read 5, iclass 35, count 2 2006.201.19:01:00.02#ibcon#read 5, iclass 35, count 2 2006.201.19:01:00.02#ibcon#about to read 6, iclass 35, count 2 2006.201.19:01:00.02#ibcon#read 6, iclass 35, count 2 2006.201.19:01:00.02#ibcon#end of sib2, iclass 35, count 2 2006.201.19:01:00.02#ibcon#*after write, iclass 35, count 2 2006.201.19:01:00.02#ibcon#*before return 0, iclass 35, count 2 2006.201.19:01:00.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:01:00.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:01:00.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.19:01:00.02#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:00.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:00.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:00.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:00.14#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:01:00.14#ibcon#first serial, iclass 35, count 0 2006.201.19:01:00.14#ibcon#enter sib2, iclass 35, count 0 2006.201.19:01:00.14#ibcon#flushed, iclass 35, count 0 2006.201.19:01:00.14#ibcon#about to write, iclass 35, count 0 2006.201.19:01:00.14#ibcon#wrote, iclass 35, count 0 2006.201.19:01:00.14#ibcon#about to read 3, iclass 35, count 0 2006.201.19:01:00.16#ibcon#read 3, iclass 35, count 0 2006.201.19:01:00.16#ibcon#about to read 4, iclass 35, count 0 2006.201.19:01:00.16#ibcon#read 4, iclass 35, count 0 2006.201.19:01:00.16#ibcon#about to read 5, iclass 35, count 0 2006.201.19:01:00.16#ibcon#read 5, iclass 35, count 0 2006.201.19:01:00.16#ibcon#about to read 6, iclass 35, count 0 2006.201.19:01:00.16#ibcon#read 6, iclass 35, count 0 2006.201.19:01:00.16#ibcon#end of sib2, iclass 35, count 0 2006.201.19:01:00.16#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:01:00.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:01:00.16#ibcon#[25=USB\r\n] 2006.201.19:01:00.16#ibcon#*before write, iclass 35, count 0 2006.201.19:01:00.16#ibcon#enter sib2, iclass 35, count 0 2006.201.19:01:00.16#ibcon#flushed, iclass 35, count 0 2006.201.19:01:00.16#ibcon#about to write, iclass 35, count 0 2006.201.19:01:00.16#ibcon#wrote, iclass 35, count 0 2006.201.19:01:00.16#ibcon#about to read 3, iclass 35, count 0 2006.201.19:01:00.19#ibcon#read 3, iclass 35, count 0 2006.201.19:01:00.19#ibcon#about to read 4, iclass 35, count 0 2006.201.19:01:00.19#ibcon#read 4, iclass 35, count 0 2006.201.19:01:00.19#ibcon#about to read 5, iclass 35, count 0 2006.201.19:01:00.19#ibcon#read 5, iclass 35, count 0 2006.201.19:01:00.19#ibcon#about to read 6, iclass 35, count 0 2006.201.19:01:00.19#ibcon#read 6, iclass 35, count 0 2006.201.19:01:00.19#ibcon#end of sib2, iclass 35, count 0 2006.201.19:01:00.19#ibcon#*after write, iclass 35, count 0 2006.201.19:01:00.19#ibcon#*before return 0, iclass 35, count 0 2006.201.19:01:00.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:00.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:00.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:01:00.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:01:00.19$vck44/valo=5,734.99 2006.201.19:01:00.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.19:01:00.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.19:01:00.19#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:00.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:00.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:00.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:00.19#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:01:00.19#ibcon#first serial, iclass 37, count 0 2006.201.19:01:00.19#ibcon#enter sib2, iclass 37, count 0 2006.201.19:01:00.19#ibcon#flushed, iclass 37, count 0 2006.201.19:01:00.19#ibcon#about to write, iclass 37, count 0 2006.201.19:01:00.19#ibcon#wrote, iclass 37, count 0 2006.201.19:01:00.19#ibcon#about to read 3, iclass 37, count 0 2006.201.19:01:00.21#ibcon#read 3, iclass 37, count 0 2006.201.19:01:00.21#ibcon#about to read 4, iclass 37, count 0 2006.201.19:01:00.21#ibcon#read 4, iclass 37, count 0 2006.201.19:01:00.21#ibcon#about to read 5, iclass 37, count 0 2006.201.19:01:00.21#ibcon#read 5, iclass 37, count 0 2006.201.19:01:00.21#ibcon#about to read 6, iclass 37, count 0 2006.201.19:01:00.21#ibcon#read 6, iclass 37, count 0 2006.201.19:01:00.21#ibcon#end of sib2, iclass 37, count 0 2006.201.19:01:00.21#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:01:00.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:01:00.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:01:00.21#ibcon#*before write, iclass 37, count 0 2006.201.19:01:00.21#ibcon#enter sib2, iclass 37, count 0 2006.201.19:01:00.21#ibcon#flushed, iclass 37, count 0 2006.201.19:01:00.21#ibcon#about to write, iclass 37, count 0 2006.201.19:01:00.21#ibcon#wrote, iclass 37, count 0 2006.201.19:01:00.21#ibcon#about to read 3, iclass 37, count 0 2006.201.19:01:00.25#ibcon#read 3, iclass 37, count 0 2006.201.19:01:00.25#ibcon#about to read 4, iclass 37, count 0 2006.201.19:01:00.25#ibcon#read 4, iclass 37, count 0 2006.201.19:01:00.25#ibcon#about to read 5, iclass 37, count 0 2006.201.19:01:00.25#ibcon#read 5, iclass 37, count 0 2006.201.19:01:00.25#ibcon#about to read 6, iclass 37, count 0 2006.201.19:01:00.25#ibcon#read 6, iclass 37, count 0 2006.201.19:01:00.25#ibcon#end of sib2, iclass 37, count 0 2006.201.19:01:00.25#ibcon#*after write, iclass 37, count 0 2006.201.19:01:00.25#ibcon#*before return 0, iclass 37, count 0 2006.201.19:01:00.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:00.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:00.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:01:00.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:01:00.25$vck44/va=5,4 2006.201.19:01:00.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.19:01:00.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.19:01:00.25#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:00.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:00.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:00.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:00.31#ibcon#enter wrdev, iclass 39, count 2 2006.201.19:01:00.31#ibcon#first serial, iclass 39, count 2 2006.201.19:01:00.31#ibcon#enter sib2, iclass 39, count 2 2006.201.19:01:00.31#ibcon#flushed, iclass 39, count 2 2006.201.19:01:00.31#ibcon#about to write, iclass 39, count 2 2006.201.19:01:00.31#ibcon#wrote, iclass 39, count 2 2006.201.19:01:00.31#ibcon#about to read 3, iclass 39, count 2 2006.201.19:01:00.33#ibcon#read 3, iclass 39, count 2 2006.201.19:01:00.33#ibcon#about to read 4, iclass 39, count 2 2006.201.19:01:00.33#ibcon#read 4, iclass 39, count 2 2006.201.19:01:00.33#ibcon#about to read 5, iclass 39, count 2 2006.201.19:01:00.33#ibcon#read 5, iclass 39, count 2 2006.201.19:01:00.33#ibcon#about to read 6, iclass 39, count 2 2006.201.19:01:00.33#ibcon#read 6, iclass 39, count 2 2006.201.19:01:00.33#ibcon#end of sib2, iclass 39, count 2 2006.201.19:01:00.33#ibcon#*mode == 0, iclass 39, count 2 2006.201.19:01:00.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.19:01:00.33#ibcon#[25=AT05-04\r\n] 2006.201.19:01:00.33#ibcon#*before write, iclass 39, count 2 2006.201.19:01:00.33#ibcon#enter sib2, iclass 39, count 2 2006.201.19:01:00.33#ibcon#flushed, iclass 39, count 2 2006.201.19:01:00.33#ibcon#about to write, iclass 39, count 2 2006.201.19:01:00.33#ibcon#wrote, iclass 39, count 2 2006.201.19:01:00.33#ibcon#about to read 3, iclass 39, count 2 2006.201.19:01:00.36#ibcon#read 3, iclass 39, count 2 2006.201.19:01:00.36#ibcon#about to read 4, iclass 39, count 2 2006.201.19:01:00.36#ibcon#read 4, iclass 39, count 2 2006.201.19:01:00.36#ibcon#about to read 5, iclass 39, count 2 2006.201.19:01:00.36#ibcon#read 5, iclass 39, count 2 2006.201.19:01:00.36#ibcon#about to read 6, iclass 39, count 2 2006.201.19:01:00.36#ibcon#read 6, iclass 39, count 2 2006.201.19:01:00.36#ibcon#end of sib2, iclass 39, count 2 2006.201.19:01:00.36#ibcon#*after write, iclass 39, count 2 2006.201.19:01:00.36#ibcon#*before return 0, iclass 39, count 2 2006.201.19:01:00.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:00.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:00.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.19:01:00.36#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:00.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:00.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:00.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:00.48#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:01:00.48#ibcon#first serial, iclass 39, count 0 2006.201.19:01:00.48#ibcon#enter sib2, iclass 39, count 0 2006.201.19:01:00.48#ibcon#flushed, iclass 39, count 0 2006.201.19:01:00.48#ibcon#about to write, iclass 39, count 0 2006.201.19:01:00.48#ibcon#wrote, iclass 39, count 0 2006.201.19:01:00.48#ibcon#about to read 3, iclass 39, count 0 2006.201.19:01:00.50#ibcon#read 3, iclass 39, count 0 2006.201.19:01:00.50#ibcon#about to read 4, iclass 39, count 0 2006.201.19:01:00.50#ibcon#read 4, iclass 39, count 0 2006.201.19:01:00.50#ibcon#about to read 5, iclass 39, count 0 2006.201.19:01:00.50#ibcon#read 5, iclass 39, count 0 2006.201.19:01:00.50#ibcon#about to read 6, iclass 39, count 0 2006.201.19:01:00.50#ibcon#read 6, iclass 39, count 0 2006.201.19:01:00.50#ibcon#end of sib2, iclass 39, count 0 2006.201.19:01:00.50#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:01:00.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:01:00.50#ibcon#[25=USB\r\n] 2006.201.19:01:00.50#ibcon#*before write, iclass 39, count 0 2006.201.19:01:00.50#ibcon#enter sib2, iclass 39, count 0 2006.201.19:01:00.50#ibcon#flushed, iclass 39, count 0 2006.201.19:01:00.50#ibcon#about to write, iclass 39, count 0 2006.201.19:01:00.50#ibcon#wrote, iclass 39, count 0 2006.201.19:01:00.50#ibcon#about to read 3, iclass 39, count 0 2006.201.19:01:00.53#ibcon#read 3, iclass 39, count 0 2006.201.19:01:00.53#ibcon#about to read 4, iclass 39, count 0 2006.201.19:01:00.53#ibcon#read 4, iclass 39, count 0 2006.201.19:01:00.53#ibcon#about to read 5, iclass 39, count 0 2006.201.19:01:00.53#ibcon#read 5, iclass 39, count 0 2006.201.19:01:00.53#ibcon#about to read 6, iclass 39, count 0 2006.201.19:01:00.53#ibcon#read 6, iclass 39, count 0 2006.201.19:01:00.53#ibcon#end of sib2, iclass 39, count 0 2006.201.19:01:00.53#ibcon#*after write, iclass 39, count 0 2006.201.19:01:00.53#ibcon#*before return 0, iclass 39, count 0 2006.201.19:01:00.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:00.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:00.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:01:00.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:01:00.53$vck44/valo=6,814.99 2006.201.19:01:00.53#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.19:01:00.53#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.19:01:00.53#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:00.53#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:00.53#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:00.53#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:00.53#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:01:00.53#ibcon#first serial, iclass 2, count 0 2006.201.19:01:00.53#ibcon#enter sib2, iclass 2, count 0 2006.201.19:01:00.53#ibcon#flushed, iclass 2, count 0 2006.201.19:01:00.53#ibcon#about to write, iclass 2, count 0 2006.201.19:01:00.53#ibcon#wrote, iclass 2, count 0 2006.201.19:01:00.53#ibcon#about to read 3, iclass 2, count 0 2006.201.19:01:00.55#ibcon#read 3, iclass 2, count 0 2006.201.19:01:00.55#ibcon#about to read 4, iclass 2, count 0 2006.201.19:01:00.55#ibcon#read 4, iclass 2, count 0 2006.201.19:01:00.55#ibcon#about to read 5, iclass 2, count 0 2006.201.19:01:00.55#ibcon#read 5, iclass 2, count 0 2006.201.19:01:00.55#ibcon#about to read 6, iclass 2, count 0 2006.201.19:01:00.55#ibcon#read 6, iclass 2, count 0 2006.201.19:01:00.55#ibcon#end of sib2, iclass 2, count 0 2006.201.19:01:00.55#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:01:00.55#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:01:00.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:01:00.55#ibcon#*before write, iclass 2, count 0 2006.201.19:01:00.55#ibcon#enter sib2, iclass 2, count 0 2006.201.19:01:00.55#ibcon#flushed, iclass 2, count 0 2006.201.19:01:00.55#ibcon#about to write, iclass 2, count 0 2006.201.19:01:00.55#ibcon#wrote, iclass 2, count 0 2006.201.19:01:00.55#ibcon#about to read 3, iclass 2, count 0 2006.201.19:01:00.59#ibcon#read 3, iclass 2, count 0 2006.201.19:01:00.59#ibcon#about to read 4, iclass 2, count 0 2006.201.19:01:00.59#ibcon#read 4, iclass 2, count 0 2006.201.19:01:00.59#ibcon#about to read 5, iclass 2, count 0 2006.201.19:01:00.59#ibcon#read 5, iclass 2, count 0 2006.201.19:01:00.59#ibcon#about to read 6, iclass 2, count 0 2006.201.19:01:00.59#ibcon#read 6, iclass 2, count 0 2006.201.19:01:00.59#ibcon#end of sib2, iclass 2, count 0 2006.201.19:01:00.59#ibcon#*after write, iclass 2, count 0 2006.201.19:01:00.59#ibcon#*before return 0, iclass 2, count 0 2006.201.19:01:00.59#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:00.59#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:00.59#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:01:00.59#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:01:00.59$vck44/va=6,5 2006.201.19:01:00.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.19:01:00.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.19:01:00.59#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:00.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:00.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:00.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:00.65#ibcon#enter wrdev, iclass 5, count 2 2006.201.19:01:00.65#ibcon#first serial, iclass 5, count 2 2006.201.19:01:00.65#ibcon#enter sib2, iclass 5, count 2 2006.201.19:01:00.65#ibcon#flushed, iclass 5, count 2 2006.201.19:01:00.65#ibcon#about to write, iclass 5, count 2 2006.201.19:01:00.65#ibcon#wrote, iclass 5, count 2 2006.201.19:01:00.65#ibcon#about to read 3, iclass 5, count 2 2006.201.19:01:00.67#ibcon#read 3, iclass 5, count 2 2006.201.19:01:00.67#ibcon#about to read 4, iclass 5, count 2 2006.201.19:01:00.67#ibcon#read 4, iclass 5, count 2 2006.201.19:01:00.67#ibcon#about to read 5, iclass 5, count 2 2006.201.19:01:00.67#ibcon#read 5, iclass 5, count 2 2006.201.19:01:00.67#ibcon#about to read 6, iclass 5, count 2 2006.201.19:01:00.67#ibcon#read 6, iclass 5, count 2 2006.201.19:01:00.67#ibcon#end of sib2, iclass 5, count 2 2006.201.19:01:00.67#ibcon#*mode == 0, iclass 5, count 2 2006.201.19:01:00.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.19:01:00.67#ibcon#[25=AT06-05\r\n] 2006.201.19:01:00.67#ibcon#*before write, iclass 5, count 2 2006.201.19:01:00.67#ibcon#enter sib2, iclass 5, count 2 2006.201.19:01:00.67#ibcon#flushed, iclass 5, count 2 2006.201.19:01:00.67#ibcon#about to write, iclass 5, count 2 2006.201.19:01:00.67#ibcon#wrote, iclass 5, count 2 2006.201.19:01:00.67#ibcon#about to read 3, iclass 5, count 2 2006.201.19:01:00.70#ibcon#read 3, iclass 5, count 2 2006.201.19:01:00.70#ibcon#about to read 4, iclass 5, count 2 2006.201.19:01:00.70#ibcon#read 4, iclass 5, count 2 2006.201.19:01:00.70#ibcon#about to read 5, iclass 5, count 2 2006.201.19:01:00.70#ibcon#read 5, iclass 5, count 2 2006.201.19:01:00.70#ibcon#about to read 6, iclass 5, count 2 2006.201.19:01:00.70#ibcon#read 6, iclass 5, count 2 2006.201.19:01:00.70#ibcon#end of sib2, iclass 5, count 2 2006.201.19:01:00.70#ibcon#*after write, iclass 5, count 2 2006.201.19:01:00.70#ibcon#*before return 0, iclass 5, count 2 2006.201.19:01:00.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:00.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:00.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.19:01:00.70#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:00.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:00.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:00.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:00.82#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:01:00.82#ibcon#first serial, iclass 5, count 0 2006.201.19:01:00.82#ibcon#enter sib2, iclass 5, count 0 2006.201.19:01:00.82#ibcon#flushed, iclass 5, count 0 2006.201.19:01:00.82#ibcon#about to write, iclass 5, count 0 2006.201.19:01:00.82#ibcon#wrote, iclass 5, count 0 2006.201.19:01:00.82#ibcon#about to read 3, iclass 5, count 0 2006.201.19:01:00.84#ibcon#read 3, iclass 5, count 0 2006.201.19:01:00.84#ibcon#about to read 4, iclass 5, count 0 2006.201.19:01:00.84#ibcon#read 4, iclass 5, count 0 2006.201.19:01:00.84#ibcon#about to read 5, iclass 5, count 0 2006.201.19:01:00.84#ibcon#read 5, iclass 5, count 0 2006.201.19:01:00.84#ibcon#about to read 6, iclass 5, count 0 2006.201.19:01:00.84#ibcon#read 6, iclass 5, count 0 2006.201.19:01:00.84#ibcon#end of sib2, iclass 5, count 0 2006.201.19:01:00.84#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:01:00.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:01:00.84#ibcon#[25=USB\r\n] 2006.201.19:01:00.84#ibcon#*before write, iclass 5, count 0 2006.201.19:01:00.84#ibcon#enter sib2, iclass 5, count 0 2006.201.19:01:00.84#ibcon#flushed, iclass 5, count 0 2006.201.19:01:00.84#ibcon#about to write, iclass 5, count 0 2006.201.19:01:00.84#ibcon#wrote, iclass 5, count 0 2006.201.19:01:00.84#ibcon#about to read 3, iclass 5, count 0 2006.201.19:01:00.87#ibcon#read 3, iclass 5, count 0 2006.201.19:01:00.87#ibcon#about to read 4, iclass 5, count 0 2006.201.19:01:00.87#ibcon#read 4, iclass 5, count 0 2006.201.19:01:00.87#ibcon#about to read 5, iclass 5, count 0 2006.201.19:01:00.87#ibcon#read 5, iclass 5, count 0 2006.201.19:01:00.87#ibcon#about to read 6, iclass 5, count 0 2006.201.19:01:00.87#ibcon#read 6, iclass 5, count 0 2006.201.19:01:00.87#ibcon#end of sib2, iclass 5, count 0 2006.201.19:01:00.87#ibcon#*after write, iclass 5, count 0 2006.201.19:01:00.87#ibcon#*before return 0, iclass 5, count 0 2006.201.19:01:00.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:00.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:00.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:01:00.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:01:00.87$vck44/valo=7,864.99 2006.201.19:01:00.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.19:01:00.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.19:01:00.87#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:00.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:00.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:00.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:00.87#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:01:00.87#ibcon#first serial, iclass 7, count 0 2006.201.19:01:00.87#ibcon#enter sib2, iclass 7, count 0 2006.201.19:01:00.87#ibcon#flushed, iclass 7, count 0 2006.201.19:01:00.87#ibcon#about to write, iclass 7, count 0 2006.201.19:01:00.87#ibcon#wrote, iclass 7, count 0 2006.201.19:01:00.87#ibcon#about to read 3, iclass 7, count 0 2006.201.19:01:00.89#ibcon#read 3, iclass 7, count 0 2006.201.19:01:00.89#ibcon#about to read 4, iclass 7, count 0 2006.201.19:01:00.89#ibcon#read 4, iclass 7, count 0 2006.201.19:01:00.89#ibcon#about to read 5, iclass 7, count 0 2006.201.19:01:00.89#ibcon#read 5, iclass 7, count 0 2006.201.19:01:00.89#ibcon#about to read 6, iclass 7, count 0 2006.201.19:01:00.89#ibcon#read 6, iclass 7, count 0 2006.201.19:01:00.89#ibcon#end of sib2, iclass 7, count 0 2006.201.19:01:00.89#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:01:00.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:01:00.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:01:00.89#ibcon#*before write, iclass 7, count 0 2006.201.19:01:00.89#ibcon#enter sib2, iclass 7, count 0 2006.201.19:01:00.89#ibcon#flushed, iclass 7, count 0 2006.201.19:01:00.89#ibcon#about to write, iclass 7, count 0 2006.201.19:01:00.89#ibcon#wrote, iclass 7, count 0 2006.201.19:01:00.89#ibcon#about to read 3, iclass 7, count 0 2006.201.19:01:00.94#ibcon#read 3, iclass 7, count 0 2006.201.19:01:00.94#ibcon#about to read 4, iclass 7, count 0 2006.201.19:01:00.94#ibcon#read 4, iclass 7, count 0 2006.201.19:01:00.94#ibcon#about to read 5, iclass 7, count 0 2006.201.19:01:00.94#ibcon#read 5, iclass 7, count 0 2006.201.19:01:00.94#ibcon#about to read 6, iclass 7, count 0 2006.201.19:01:00.94#ibcon#read 6, iclass 7, count 0 2006.201.19:01:00.94#ibcon#end of sib2, iclass 7, count 0 2006.201.19:01:00.94#ibcon#*after write, iclass 7, count 0 2006.201.19:01:00.94#ibcon#*before return 0, iclass 7, count 0 2006.201.19:01:00.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:00.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:00.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:01:00.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:01:00.94$vck44/va=7,5 2006.201.19:01:00.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.19:01:00.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.19:01:00.94#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:00.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:00.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:00.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:00.99#ibcon#enter wrdev, iclass 11, count 2 2006.201.19:01:00.99#ibcon#first serial, iclass 11, count 2 2006.201.19:01:00.99#ibcon#enter sib2, iclass 11, count 2 2006.201.19:01:00.99#ibcon#flushed, iclass 11, count 2 2006.201.19:01:00.99#ibcon#about to write, iclass 11, count 2 2006.201.19:01:00.99#ibcon#wrote, iclass 11, count 2 2006.201.19:01:00.99#ibcon#about to read 3, iclass 11, count 2 2006.201.19:01:01.01#ibcon#read 3, iclass 11, count 2 2006.201.19:01:01.01#ibcon#about to read 4, iclass 11, count 2 2006.201.19:01:01.01#ibcon#read 4, iclass 11, count 2 2006.201.19:01:01.01#ibcon#about to read 5, iclass 11, count 2 2006.201.19:01:01.01#ibcon#read 5, iclass 11, count 2 2006.201.19:01:01.01#ibcon#about to read 6, iclass 11, count 2 2006.201.19:01:01.01#ibcon#read 6, iclass 11, count 2 2006.201.19:01:01.01#ibcon#end of sib2, iclass 11, count 2 2006.201.19:01:01.01#ibcon#*mode == 0, iclass 11, count 2 2006.201.19:01:01.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.19:01:01.01#ibcon#[25=AT07-05\r\n] 2006.201.19:01:01.01#ibcon#*before write, iclass 11, count 2 2006.201.19:01:01.01#ibcon#enter sib2, iclass 11, count 2 2006.201.19:01:01.01#ibcon#flushed, iclass 11, count 2 2006.201.19:01:01.01#ibcon#about to write, iclass 11, count 2 2006.201.19:01:01.01#ibcon#wrote, iclass 11, count 2 2006.201.19:01:01.01#ibcon#about to read 3, iclass 11, count 2 2006.201.19:01:01.04#ibcon#read 3, iclass 11, count 2 2006.201.19:01:01.04#ibcon#about to read 4, iclass 11, count 2 2006.201.19:01:01.04#ibcon#read 4, iclass 11, count 2 2006.201.19:01:01.04#ibcon#about to read 5, iclass 11, count 2 2006.201.19:01:01.04#ibcon#read 5, iclass 11, count 2 2006.201.19:01:01.04#ibcon#about to read 6, iclass 11, count 2 2006.201.19:01:01.04#ibcon#read 6, iclass 11, count 2 2006.201.19:01:01.04#ibcon#end of sib2, iclass 11, count 2 2006.201.19:01:01.04#ibcon#*after write, iclass 11, count 2 2006.201.19:01:01.04#ibcon#*before return 0, iclass 11, count 2 2006.201.19:01:01.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:01.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:01.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.19:01:01.04#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:01.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:01.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:01.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:01.16#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:01:01.16#ibcon#first serial, iclass 11, count 0 2006.201.19:01:01.16#ibcon#enter sib2, iclass 11, count 0 2006.201.19:01:01.16#ibcon#flushed, iclass 11, count 0 2006.201.19:01:01.16#ibcon#about to write, iclass 11, count 0 2006.201.19:01:01.16#ibcon#wrote, iclass 11, count 0 2006.201.19:01:01.16#ibcon#about to read 3, iclass 11, count 0 2006.201.19:01:01.18#ibcon#read 3, iclass 11, count 0 2006.201.19:01:01.18#ibcon#about to read 4, iclass 11, count 0 2006.201.19:01:01.18#ibcon#read 4, iclass 11, count 0 2006.201.19:01:01.18#ibcon#about to read 5, iclass 11, count 0 2006.201.19:01:01.18#ibcon#read 5, iclass 11, count 0 2006.201.19:01:01.18#ibcon#about to read 6, iclass 11, count 0 2006.201.19:01:01.18#ibcon#read 6, iclass 11, count 0 2006.201.19:01:01.18#ibcon#end of sib2, iclass 11, count 0 2006.201.19:01:01.18#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:01:01.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:01:01.18#ibcon#[25=USB\r\n] 2006.201.19:01:01.18#ibcon#*before write, iclass 11, count 0 2006.201.19:01:01.18#ibcon#enter sib2, iclass 11, count 0 2006.201.19:01:01.18#ibcon#flushed, iclass 11, count 0 2006.201.19:01:01.18#ibcon#about to write, iclass 11, count 0 2006.201.19:01:01.18#ibcon#wrote, iclass 11, count 0 2006.201.19:01:01.18#ibcon#about to read 3, iclass 11, count 0 2006.201.19:01:01.21#ibcon#read 3, iclass 11, count 0 2006.201.19:01:01.21#ibcon#about to read 4, iclass 11, count 0 2006.201.19:01:01.21#ibcon#read 4, iclass 11, count 0 2006.201.19:01:01.21#ibcon#about to read 5, iclass 11, count 0 2006.201.19:01:01.21#ibcon#read 5, iclass 11, count 0 2006.201.19:01:01.21#ibcon#about to read 6, iclass 11, count 0 2006.201.19:01:01.21#ibcon#read 6, iclass 11, count 0 2006.201.19:01:01.21#ibcon#end of sib2, iclass 11, count 0 2006.201.19:01:01.21#ibcon#*after write, iclass 11, count 0 2006.201.19:01:01.21#ibcon#*before return 0, iclass 11, count 0 2006.201.19:01:01.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:01.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:01.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:01:01.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:01:01.21$vck44/valo=8,884.99 2006.201.19:01:01.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.19:01:01.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.19:01:01.21#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:01.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:01.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:01.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:01.21#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:01:01.21#ibcon#first serial, iclass 13, count 0 2006.201.19:01:01.21#ibcon#enter sib2, iclass 13, count 0 2006.201.19:01:01.21#ibcon#flushed, iclass 13, count 0 2006.201.19:01:01.21#ibcon#about to write, iclass 13, count 0 2006.201.19:01:01.21#ibcon#wrote, iclass 13, count 0 2006.201.19:01:01.21#ibcon#about to read 3, iclass 13, count 0 2006.201.19:01:01.23#ibcon#read 3, iclass 13, count 0 2006.201.19:01:01.23#ibcon#about to read 4, iclass 13, count 0 2006.201.19:01:01.23#ibcon#read 4, iclass 13, count 0 2006.201.19:01:01.23#ibcon#about to read 5, iclass 13, count 0 2006.201.19:01:01.23#ibcon#read 5, iclass 13, count 0 2006.201.19:01:01.23#ibcon#about to read 6, iclass 13, count 0 2006.201.19:01:01.23#ibcon#read 6, iclass 13, count 0 2006.201.19:01:01.23#ibcon#end of sib2, iclass 13, count 0 2006.201.19:01:01.23#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:01:01.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:01:01.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:01:01.23#ibcon#*before write, iclass 13, count 0 2006.201.19:01:01.23#ibcon#enter sib2, iclass 13, count 0 2006.201.19:01:01.23#ibcon#flushed, iclass 13, count 0 2006.201.19:01:01.23#ibcon#about to write, iclass 13, count 0 2006.201.19:01:01.23#ibcon#wrote, iclass 13, count 0 2006.201.19:01:01.23#ibcon#about to read 3, iclass 13, count 0 2006.201.19:01:01.27#ibcon#read 3, iclass 13, count 0 2006.201.19:01:01.27#ibcon#about to read 4, iclass 13, count 0 2006.201.19:01:01.27#ibcon#read 4, iclass 13, count 0 2006.201.19:01:01.27#ibcon#about to read 5, iclass 13, count 0 2006.201.19:01:01.27#ibcon#read 5, iclass 13, count 0 2006.201.19:01:01.27#ibcon#about to read 6, iclass 13, count 0 2006.201.19:01:01.27#ibcon#read 6, iclass 13, count 0 2006.201.19:01:01.27#ibcon#end of sib2, iclass 13, count 0 2006.201.19:01:01.27#ibcon#*after write, iclass 13, count 0 2006.201.19:01:01.27#ibcon#*before return 0, iclass 13, count 0 2006.201.19:01:01.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:01.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:01.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:01:01.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:01:01.27$vck44/va=8,4 2006.201.19:01:01.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.19:01:01.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.19:01:01.27#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:01.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:01:01.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:01:01.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:01:01.33#ibcon#enter wrdev, iclass 15, count 2 2006.201.19:01:01.33#ibcon#first serial, iclass 15, count 2 2006.201.19:01:01.33#ibcon#enter sib2, iclass 15, count 2 2006.201.19:01:01.33#ibcon#flushed, iclass 15, count 2 2006.201.19:01:01.33#ibcon#about to write, iclass 15, count 2 2006.201.19:01:01.33#ibcon#wrote, iclass 15, count 2 2006.201.19:01:01.33#ibcon#about to read 3, iclass 15, count 2 2006.201.19:01:01.35#ibcon#read 3, iclass 15, count 2 2006.201.19:01:01.35#ibcon#about to read 4, iclass 15, count 2 2006.201.19:01:01.35#ibcon#read 4, iclass 15, count 2 2006.201.19:01:01.35#ibcon#about to read 5, iclass 15, count 2 2006.201.19:01:01.35#ibcon#read 5, iclass 15, count 2 2006.201.19:01:01.35#ibcon#about to read 6, iclass 15, count 2 2006.201.19:01:01.35#ibcon#read 6, iclass 15, count 2 2006.201.19:01:01.35#ibcon#end of sib2, iclass 15, count 2 2006.201.19:01:01.35#ibcon#*mode == 0, iclass 15, count 2 2006.201.19:01:01.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.19:01:01.35#ibcon#[25=AT08-04\r\n] 2006.201.19:01:01.35#ibcon#*before write, iclass 15, count 2 2006.201.19:01:01.35#ibcon#enter sib2, iclass 15, count 2 2006.201.19:01:01.35#ibcon#flushed, iclass 15, count 2 2006.201.19:01:01.35#ibcon#about to write, iclass 15, count 2 2006.201.19:01:01.35#ibcon#wrote, iclass 15, count 2 2006.201.19:01:01.35#ibcon#about to read 3, iclass 15, count 2 2006.201.19:01:01.38#ibcon#read 3, iclass 15, count 2 2006.201.19:01:01.38#ibcon#about to read 4, iclass 15, count 2 2006.201.19:01:01.38#ibcon#read 4, iclass 15, count 2 2006.201.19:01:01.38#ibcon#about to read 5, iclass 15, count 2 2006.201.19:01:01.38#ibcon#read 5, iclass 15, count 2 2006.201.19:01:01.38#ibcon#about to read 6, iclass 15, count 2 2006.201.19:01:01.38#ibcon#read 6, iclass 15, count 2 2006.201.19:01:01.38#ibcon#end of sib2, iclass 15, count 2 2006.201.19:01:01.38#ibcon#*after write, iclass 15, count 2 2006.201.19:01:01.38#ibcon#*before return 0, iclass 15, count 2 2006.201.19:01:01.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:01:01.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:01:01.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.19:01:01.38#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:01.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:01:01.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:01:01.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:01:01.50#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:01:01.50#ibcon#first serial, iclass 15, count 0 2006.201.19:01:01.50#ibcon#enter sib2, iclass 15, count 0 2006.201.19:01:01.50#ibcon#flushed, iclass 15, count 0 2006.201.19:01:01.50#ibcon#about to write, iclass 15, count 0 2006.201.19:01:01.50#ibcon#wrote, iclass 15, count 0 2006.201.19:01:01.50#ibcon#about to read 3, iclass 15, count 0 2006.201.19:01:01.52#ibcon#read 3, iclass 15, count 0 2006.201.19:01:01.52#ibcon#about to read 4, iclass 15, count 0 2006.201.19:01:01.52#ibcon#read 4, iclass 15, count 0 2006.201.19:01:01.52#ibcon#about to read 5, iclass 15, count 0 2006.201.19:01:01.52#ibcon#read 5, iclass 15, count 0 2006.201.19:01:01.52#ibcon#about to read 6, iclass 15, count 0 2006.201.19:01:01.52#ibcon#read 6, iclass 15, count 0 2006.201.19:01:01.52#ibcon#end of sib2, iclass 15, count 0 2006.201.19:01:01.52#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:01:01.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:01:01.52#ibcon#[25=USB\r\n] 2006.201.19:01:01.52#ibcon#*before write, iclass 15, count 0 2006.201.19:01:01.52#ibcon#enter sib2, iclass 15, count 0 2006.201.19:01:01.52#ibcon#flushed, iclass 15, count 0 2006.201.19:01:01.52#ibcon#about to write, iclass 15, count 0 2006.201.19:01:01.52#ibcon#wrote, iclass 15, count 0 2006.201.19:01:01.52#ibcon#about to read 3, iclass 15, count 0 2006.201.19:01:01.55#ibcon#read 3, iclass 15, count 0 2006.201.19:01:01.55#ibcon#about to read 4, iclass 15, count 0 2006.201.19:01:01.55#ibcon#read 4, iclass 15, count 0 2006.201.19:01:01.55#ibcon#about to read 5, iclass 15, count 0 2006.201.19:01:01.55#ibcon#read 5, iclass 15, count 0 2006.201.19:01:01.55#ibcon#about to read 6, iclass 15, count 0 2006.201.19:01:01.55#ibcon#read 6, iclass 15, count 0 2006.201.19:01:01.55#ibcon#end of sib2, iclass 15, count 0 2006.201.19:01:01.55#ibcon#*after write, iclass 15, count 0 2006.201.19:01:01.55#ibcon#*before return 0, iclass 15, count 0 2006.201.19:01:01.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:01:01.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:01:01.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:01:01.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:01:01.55$vck44/vblo=1,629.99 2006.201.19:01:01.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.19:01:01.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.19:01:01.55#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:01.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:01:01.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:01:01.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:01:01.55#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:01:01.55#ibcon#first serial, iclass 17, count 0 2006.201.19:01:01.55#ibcon#enter sib2, iclass 17, count 0 2006.201.19:01:01.55#ibcon#flushed, iclass 17, count 0 2006.201.19:01:01.55#ibcon#about to write, iclass 17, count 0 2006.201.19:01:01.55#ibcon#wrote, iclass 17, count 0 2006.201.19:01:01.55#ibcon#about to read 3, iclass 17, count 0 2006.201.19:01:01.57#ibcon#read 3, iclass 17, count 0 2006.201.19:01:01.57#ibcon#about to read 4, iclass 17, count 0 2006.201.19:01:01.57#ibcon#read 4, iclass 17, count 0 2006.201.19:01:01.57#ibcon#about to read 5, iclass 17, count 0 2006.201.19:01:01.57#ibcon#read 5, iclass 17, count 0 2006.201.19:01:01.57#ibcon#about to read 6, iclass 17, count 0 2006.201.19:01:01.57#ibcon#read 6, iclass 17, count 0 2006.201.19:01:01.57#ibcon#end of sib2, iclass 17, count 0 2006.201.19:01:01.57#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:01:01.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:01:01.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:01:01.57#ibcon#*before write, iclass 17, count 0 2006.201.19:01:01.57#ibcon#enter sib2, iclass 17, count 0 2006.201.19:01:01.57#ibcon#flushed, iclass 17, count 0 2006.201.19:01:01.57#ibcon#about to write, iclass 17, count 0 2006.201.19:01:01.57#ibcon#wrote, iclass 17, count 0 2006.201.19:01:01.57#ibcon#about to read 3, iclass 17, count 0 2006.201.19:01:01.62#ibcon#read 3, iclass 17, count 0 2006.201.19:01:01.62#ibcon#about to read 4, iclass 17, count 0 2006.201.19:01:01.62#ibcon#read 4, iclass 17, count 0 2006.201.19:01:01.62#ibcon#about to read 5, iclass 17, count 0 2006.201.19:01:01.62#ibcon#read 5, iclass 17, count 0 2006.201.19:01:01.62#ibcon#about to read 6, iclass 17, count 0 2006.201.19:01:01.62#ibcon#read 6, iclass 17, count 0 2006.201.19:01:01.62#ibcon#end of sib2, iclass 17, count 0 2006.201.19:01:01.62#ibcon#*after write, iclass 17, count 0 2006.201.19:01:01.62#ibcon#*before return 0, iclass 17, count 0 2006.201.19:01:01.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:01:01.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:01:01.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:01:01.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:01:01.62$vck44/vb=1,4 2006.201.19:01:01.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.19:01:01.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.19:01:01.62#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:01.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:01:01.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:01:01.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:01:01.62#ibcon#enter wrdev, iclass 19, count 2 2006.201.19:01:01.62#ibcon#first serial, iclass 19, count 2 2006.201.19:01:01.62#ibcon#enter sib2, iclass 19, count 2 2006.201.19:01:01.62#ibcon#flushed, iclass 19, count 2 2006.201.19:01:01.62#ibcon#about to write, iclass 19, count 2 2006.201.19:01:01.62#ibcon#wrote, iclass 19, count 2 2006.201.19:01:01.62#ibcon#about to read 3, iclass 19, count 2 2006.201.19:01:01.64#ibcon#read 3, iclass 19, count 2 2006.201.19:01:01.64#ibcon#about to read 4, iclass 19, count 2 2006.201.19:01:01.64#ibcon#read 4, iclass 19, count 2 2006.201.19:01:01.64#ibcon#about to read 5, iclass 19, count 2 2006.201.19:01:01.64#ibcon#read 5, iclass 19, count 2 2006.201.19:01:01.64#ibcon#about to read 6, iclass 19, count 2 2006.201.19:01:01.64#ibcon#read 6, iclass 19, count 2 2006.201.19:01:01.64#ibcon#end of sib2, iclass 19, count 2 2006.201.19:01:01.64#ibcon#*mode == 0, iclass 19, count 2 2006.201.19:01:01.64#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.19:01:01.64#ibcon#[27=AT01-04\r\n] 2006.201.19:01:01.64#ibcon#*before write, iclass 19, count 2 2006.201.19:01:01.64#ibcon#enter sib2, iclass 19, count 2 2006.201.19:01:01.64#ibcon#flushed, iclass 19, count 2 2006.201.19:01:01.64#ibcon#about to write, iclass 19, count 2 2006.201.19:01:01.64#ibcon#wrote, iclass 19, count 2 2006.201.19:01:01.64#ibcon#about to read 3, iclass 19, count 2 2006.201.19:01:01.67#ibcon#read 3, iclass 19, count 2 2006.201.19:01:01.67#ibcon#about to read 4, iclass 19, count 2 2006.201.19:01:01.67#ibcon#read 4, iclass 19, count 2 2006.201.19:01:01.67#ibcon#about to read 5, iclass 19, count 2 2006.201.19:01:01.67#ibcon#read 5, iclass 19, count 2 2006.201.19:01:01.67#ibcon#about to read 6, iclass 19, count 2 2006.201.19:01:01.67#ibcon#read 6, iclass 19, count 2 2006.201.19:01:01.67#ibcon#end of sib2, iclass 19, count 2 2006.201.19:01:01.67#ibcon#*after write, iclass 19, count 2 2006.201.19:01:01.67#ibcon#*before return 0, iclass 19, count 2 2006.201.19:01:01.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:01:01.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:01:01.67#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.19:01:01.67#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:01.67#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:01:01.79#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:01:01.79#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:01:01.79#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:01:01.79#ibcon#first serial, iclass 19, count 0 2006.201.19:01:01.79#ibcon#enter sib2, iclass 19, count 0 2006.201.19:01:01.79#ibcon#flushed, iclass 19, count 0 2006.201.19:01:01.79#ibcon#about to write, iclass 19, count 0 2006.201.19:01:01.79#ibcon#wrote, iclass 19, count 0 2006.201.19:01:01.79#ibcon#about to read 3, iclass 19, count 0 2006.201.19:01:01.81#ibcon#read 3, iclass 19, count 0 2006.201.19:01:01.81#ibcon#about to read 4, iclass 19, count 0 2006.201.19:01:01.81#ibcon#read 4, iclass 19, count 0 2006.201.19:01:01.81#ibcon#about to read 5, iclass 19, count 0 2006.201.19:01:01.81#ibcon#read 5, iclass 19, count 0 2006.201.19:01:01.81#ibcon#about to read 6, iclass 19, count 0 2006.201.19:01:01.81#ibcon#read 6, iclass 19, count 0 2006.201.19:01:01.81#ibcon#end of sib2, iclass 19, count 0 2006.201.19:01:01.81#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:01:01.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:01:01.81#ibcon#[27=USB\r\n] 2006.201.19:01:01.81#ibcon#*before write, iclass 19, count 0 2006.201.19:01:01.81#ibcon#enter sib2, iclass 19, count 0 2006.201.19:01:01.81#ibcon#flushed, iclass 19, count 0 2006.201.19:01:01.81#ibcon#about to write, iclass 19, count 0 2006.201.19:01:01.81#ibcon#wrote, iclass 19, count 0 2006.201.19:01:01.81#ibcon#about to read 3, iclass 19, count 0 2006.201.19:01:01.84#ibcon#read 3, iclass 19, count 0 2006.201.19:01:01.84#ibcon#about to read 4, iclass 19, count 0 2006.201.19:01:01.84#ibcon#read 4, iclass 19, count 0 2006.201.19:01:01.84#ibcon#about to read 5, iclass 19, count 0 2006.201.19:01:01.84#ibcon#read 5, iclass 19, count 0 2006.201.19:01:01.84#ibcon#about to read 6, iclass 19, count 0 2006.201.19:01:01.84#ibcon#read 6, iclass 19, count 0 2006.201.19:01:01.84#ibcon#end of sib2, iclass 19, count 0 2006.201.19:01:01.84#ibcon#*after write, iclass 19, count 0 2006.201.19:01:01.84#ibcon#*before return 0, iclass 19, count 0 2006.201.19:01:01.84#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:01:01.84#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:01:01.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:01:01.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:01:01.84$vck44/vblo=2,634.99 2006.201.19:01:01.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.19:01:01.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.19:01:01.84#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:01.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:01:01.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:01:01.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:01:01.84#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:01:01.84#ibcon#first serial, iclass 21, count 0 2006.201.19:01:01.84#ibcon#enter sib2, iclass 21, count 0 2006.201.19:01:01.84#ibcon#flushed, iclass 21, count 0 2006.201.19:01:01.84#ibcon#about to write, iclass 21, count 0 2006.201.19:01:01.84#ibcon#wrote, iclass 21, count 0 2006.201.19:01:01.84#ibcon#about to read 3, iclass 21, count 0 2006.201.19:01:01.86#ibcon#read 3, iclass 21, count 0 2006.201.19:01:01.86#ibcon#about to read 4, iclass 21, count 0 2006.201.19:01:01.86#ibcon#read 4, iclass 21, count 0 2006.201.19:01:01.86#ibcon#about to read 5, iclass 21, count 0 2006.201.19:01:01.86#ibcon#read 5, iclass 21, count 0 2006.201.19:01:01.86#ibcon#about to read 6, iclass 21, count 0 2006.201.19:01:01.86#ibcon#read 6, iclass 21, count 0 2006.201.19:01:01.86#ibcon#end of sib2, iclass 21, count 0 2006.201.19:01:01.86#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:01:01.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:01:01.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:01:01.86#ibcon#*before write, iclass 21, count 0 2006.201.19:01:01.86#ibcon#enter sib2, iclass 21, count 0 2006.201.19:01:01.86#ibcon#flushed, iclass 21, count 0 2006.201.19:01:01.86#ibcon#about to write, iclass 21, count 0 2006.201.19:01:01.86#ibcon#wrote, iclass 21, count 0 2006.201.19:01:01.86#ibcon#about to read 3, iclass 21, count 0 2006.201.19:01:01.90#ibcon#read 3, iclass 21, count 0 2006.201.19:01:01.90#ibcon#about to read 4, iclass 21, count 0 2006.201.19:01:01.90#ibcon#read 4, iclass 21, count 0 2006.201.19:01:01.90#ibcon#about to read 5, iclass 21, count 0 2006.201.19:01:01.90#ibcon#read 5, iclass 21, count 0 2006.201.19:01:01.90#ibcon#about to read 6, iclass 21, count 0 2006.201.19:01:01.90#ibcon#read 6, iclass 21, count 0 2006.201.19:01:01.90#ibcon#end of sib2, iclass 21, count 0 2006.201.19:01:01.90#ibcon#*after write, iclass 21, count 0 2006.201.19:01:01.90#ibcon#*before return 0, iclass 21, count 0 2006.201.19:01:01.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:01:01.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:01:01.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:01:01.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:01:01.90$vck44/vb=2,5 2006.201.19:01:01.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.19:01:01.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.19:01:01.90#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:01.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:01:01.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:01:01.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:01:01.96#ibcon#enter wrdev, iclass 23, count 2 2006.201.19:01:01.96#ibcon#first serial, iclass 23, count 2 2006.201.19:01:01.96#ibcon#enter sib2, iclass 23, count 2 2006.201.19:01:01.96#ibcon#flushed, iclass 23, count 2 2006.201.19:01:01.96#ibcon#about to write, iclass 23, count 2 2006.201.19:01:01.96#ibcon#wrote, iclass 23, count 2 2006.201.19:01:01.96#ibcon#about to read 3, iclass 23, count 2 2006.201.19:01:01.98#ibcon#read 3, iclass 23, count 2 2006.201.19:01:01.98#ibcon#about to read 4, iclass 23, count 2 2006.201.19:01:01.98#ibcon#read 4, iclass 23, count 2 2006.201.19:01:01.98#ibcon#about to read 5, iclass 23, count 2 2006.201.19:01:01.98#ibcon#read 5, iclass 23, count 2 2006.201.19:01:01.98#ibcon#about to read 6, iclass 23, count 2 2006.201.19:01:01.98#ibcon#read 6, iclass 23, count 2 2006.201.19:01:01.98#ibcon#end of sib2, iclass 23, count 2 2006.201.19:01:01.98#ibcon#*mode == 0, iclass 23, count 2 2006.201.19:01:01.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.19:01:01.98#ibcon#[27=AT02-05\r\n] 2006.201.19:01:01.98#ibcon#*before write, iclass 23, count 2 2006.201.19:01:01.98#ibcon#enter sib2, iclass 23, count 2 2006.201.19:01:01.98#ibcon#flushed, iclass 23, count 2 2006.201.19:01:01.98#ibcon#about to write, iclass 23, count 2 2006.201.19:01:01.98#ibcon#wrote, iclass 23, count 2 2006.201.19:01:01.98#ibcon#about to read 3, iclass 23, count 2 2006.201.19:01:02.01#ibcon#read 3, iclass 23, count 2 2006.201.19:01:02.01#ibcon#about to read 4, iclass 23, count 2 2006.201.19:01:02.01#ibcon#read 4, iclass 23, count 2 2006.201.19:01:02.01#ibcon#about to read 5, iclass 23, count 2 2006.201.19:01:02.01#ibcon#read 5, iclass 23, count 2 2006.201.19:01:02.01#ibcon#about to read 6, iclass 23, count 2 2006.201.19:01:02.01#ibcon#read 6, iclass 23, count 2 2006.201.19:01:02.01#ibcon#end of sib2, iclass 23, count 2 2006.201.19:01:02.01#ibcon#*after write, iclass 23, count 2 2006.201.19:01:02.01#ibcon#*before return 0, iclass 23, count 2 2006.201.19:01:02.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:01:02.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:01:02.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.19:01:02.01#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:02.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:01:02.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:01:02.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:01:02.13#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:01:02.13#ibcon#first serial, iclass 23, count 0 2006.201.19:01:02.13#ibcon#enter sib2, iclass 23, count 0 2006.201.19:01:02.13#ibcon#flushed, iclass 23, count 0 2006.201.19:01:02.13#ibcon#about to write, iclass 23, count 0 2006.201.19:01:02.13#ibcon#wrote, iclass 23, count 0 2006.201.19:01:02.13#ibcon#about to read 3, iclass 23, count 0 2006.201.19:01:02.15#ibcon#read 3, iclass 23, count 0 2006.201.19:01:02.15#ibcon#about to read 4, iclass 23, count 0 2006.201.19:01:02.15#ibcon#read 4, iclass 23, count 0 2006.201.19:01:02.15#ibcon#about to read 5, iclass 23, count 0 2006.201.19:01:02.15#ibcon#read 5, iclass 23, count 0 2006.201.19:01:02.15#ibcon#about to read 6, iclass 23, count 0 2006.201.19:01:02.15#ibcon#read 6, iclass 23, count 0 2006.201.19:01:02.15#ibcon#end of sib2, iclass 23, count 0 2006.201.19:01:02.15#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:01:02.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:01:02.15#ibcon#[27=USB\r\n] 2006.201.19:01:02.15#ibcon#*before write, iclass 23, count 0 2006.201.19:01:02.15#ibcon#enter sib2, iclass 23, count 0 2006.201.19:01:02.15#ibcon#flushed, iclass 23, count 0 2006.201.19:01:02.15#ibcon#about to write, iclass 23, count 0 2006.201.19:01:02.15#ibcon#wrote, iclass 23, count 0 2006.201.19:01:02.15#ibcon#about to read 3, iclass 23, count 0 2006.201.19:01:02.18#ibcon#read 3, iclass 23, count 0 2006.201.19:01:02.18#ibcon#about to read 4, iclass 23, count 0 2006.201.19:01:02.18#ibcon#read 4, iclass 23, count 0 2006.201.19:01:02.18#ibcon#about to read 5, iclass 23, count 0 2006.201.19:01:02.18#ibcon#read 5, iclass 23, count 0 2006.201.19:01:02.18#ibcon#about to read 6, iclass 23, count 0 2006.201.19:01:02.18#ibcon#read 6, iclass 23, count 0 2006.201.19:01:02.18#ibcon#end of sib2, iclass 23, count 0 2006.201.19:01:02.18#ibcon#*after write, iclass 23, count 0 2006.201.19:01:02.18#ibcon#*before return 0, iclass 23, count 0 2006.201.19:01:02.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:01:02.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:01:02.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:01:02.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:01:02.18$vck44/vblo=3,649.99 2006.201.19:01:02.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.19:01:02.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.19:01:02.18#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:02.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:01:02.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:01:02.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:01:02.18#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:01:02.18#ibcon#first serial, iclass 25, count 0 2006.201.19:01:02.18#ibcon#enter sib2, iclass 25, count 0 2006.201.19:01:02.18#ibcon#flushed, iclass 25, count 0 2006.201.19:01:02.18#ibcon#about to write, iclass 25, count 0 2006.201.19:01:02.18#ibcon#wrote, iclass 25, count 0 2006.201.19:01:02.18#ibcon#about to read 3, iclass 25, count 0 2006.201.19:01:02.20#ibcon#read 3, iclass 25, count 0 2006.201.19:01:02.20#ibcon#about to read 4, iclass 25, count 0 2006.201.19:01:02.20#ibcon#read 4, iclass 25, count 0 2006.201.19:01:02.20#ibcon#about to read 5, iclass 25, count 0 2006.201.19:01:02.20#ibcon#read 5, iclass 25, count 0 2006.201.19:01:02.20#ibcon#about to read 6, iclass 25, count 0 2006.201.19:01:02.20#ibcon#read 6, iclass 25, count 0 2006.201.19:01:02.20#ibcon#end of sib2, iclass 25, count 0 2006.201.19:01:02.20#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:01:02.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:01:02.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:01:02.20#ibcon#*before write, iclass 25, count 0 2006.201.19:01:02.20#ibcon#enter sib2, iclass 25, count 0 2006.201.19:01:02.20#ibcon#flushed, iclass 25, count 0 2006.201.19:01:02.20#ibcon#about to write, iclass 25, count 0 2006.201.19:01:02.20#ibcon#wrote, iclass 25, count 0 2006.201.19:01:02.20#ibcon#about to read 3, iclass 25, count 0 2006.201.19:01:02.24#ibcon#read 3, iclass 25, count 0 2006.201.19:01:02.24#ibcon#about to read 4, iclass 25, count 0 2006.201.19:01:02.24#ibcon#read 4, iclass 25, count 0 2006.201.19:01:02.24#ibcon#about to read 5, iclass 25, count 0 2006.201.19:01:02.24#ibcon#read 5, iclass 25, count 0 2006.201.19:01:02.24#ibcon#about to read 6, iclass 25, count 0 2006.201.19:01:02.24#ibcon#read 6, iclass 25, count 0 2006.201.19:01:02.24#ibcon#end of sib2, iclass 25, count 0 2006.201.19:01:02.24#ibcon#*after write, iclass 25, count 0 2006.201.19:01:02.24#ibcon#*before return 0, iclass 25, count 0 2006.201.19:01:02.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:01:02.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:01:02.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:01:02.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:01:02.24$vck44/vb=3,4 2006.201.19:01:02.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.19:01:02.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.19:01:02.24#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:02.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:01:02.30#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:01:02.30#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:01:02.30#ibcon#enter wrdev, iclass 27, count 2 2006.201.19:01:02.30#ibcon#first serial, iclass 27, count 2 2006.201.19:01:02.30#ibcon#enter sib2, iclass 27, count 2 2006.201.19:01:02.30#ibcon#flushed, iclass 27, count 2 2006.201.19:01:02.30#ibcon#about to write, iclass 27, count 2 2006.201.19:01:02.30#ibcon#wrote, iclass 27, count 2 2006.201.19:01:02.30#ibcon#about to read 3, iclass 27, count 2 2006.201.19:01:02.32#ibcon#read 3, iclass 27, count 2 2006.201.19:01:02.32#ibcon#about to read 4, iclass 27, count 2 2006.201.19:01:02.32#ibcon#read 4, iclass 27, count 2 2006.201.19:01:02.32#ibcon#about to read 5, iclass 27, count 2 2006.201.19:01:02.32#ibcon#read 5, iclass 27, count 2 2006.201.19:01:02.32#ibcon#about to read 6, iclass 27, count 2 2006.201.19:01:02.32#ibcon#read 6, iclass 27, count 2 2006.201.19:01:02.32#ibcon#end of sib2, iclass 27, count 2 2006.201.19:01:02.32#ibcon#*mode == 0, iclass 27, count 2 2006.201.19:01:02.32#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.19:01:02.32#ibcon#[27=AT03-04\r\n] 2006.201.19:01:02.32#ibcon#*before write, iclass 27, count 2 2006.201.19:01:02.32#ibcon#enter sib2, iclass 27, count 2 2006.201.19:01:02.32#ibcon#flushed, iclass 27, count 2 2006.201.19:01:02.32#ibcon#about to write, iclass 27, count 2 2006.201.19:01:02.32#ibcon#wrote, iclass 27, count 2 2006.201.19:01:02.32#ibcon#about to read 3, iclass 27, count 2 2006.201.19:01:02.35#ibcon#read 3, iclass 27, count 2 2006.201.19:01:02.35#ibcon#about to read 4, iclass 27, count 2 2006.201.19:01:02.35#ibcon#read 4, iclass 27, count 2 2006.201.19:01:02.35#ibcon#about to read 5, iclass 27, count 2 2006.201.19:01:02.35#ibcon#read 5, iclass 27, count 2 2006.201.19:01:02.35#ibcon#about to read 6, iclass 27, count 2 2006.201.19:01:02.35#ibcon#read 6, iclass 27, count 2 2006.201.19:01:02.35#ibcon#end of sib2, iclass 27, count 2 2006.201.19:01:02.35#ibcon#*after write, iclass 27, count 2 2006.201.19:01:02.35#ibcon#*before return 0, iclass 27, count 2 2006.201.19:01:02.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:01:02.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:01:02.35#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.19:01:02.35#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:02.35#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:01:02.47#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:01:02.47#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:01:02.47#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:01:02.47#ibcon#first serial, iclass 27, count 0 2006.201.19:01:02.47#ibcon#enter sib2, iclass 27, count 0 2006.201.19:01:02.47#ibcon#flushed, iclass 27, count 0 2006.201.19:01:02.47#ibcon#about to write, iclass 27, count 0 2006.201.19:01:02.47#ibcon#wrote, iclass 27, count 0 2006.201.19:01:02.47#ibcon#about to read 3, iclass 27, count 0 2006.201.19:01:02.49#ibcon#read 3, iclass 27, count 0 2006.201.19:01:02.49#ibcon#about to read 4, iclass 27, count 0 2006.201.19:01:02.49#ibcon#read 4, iclass 27, count 0 2006.201.19:01:02.49#ibcon#about to read 5, iclass 27, count 0 2006.201.19:01:02.49#ibcon#read 5, iclass 27, count 0 2006.201.19:01:02.49#ibcon#about to read 6, iclass 27, count 0 2006.201.19:01:02.49#ibcon#read 6, iclass 27, count 0 2006.201.19:01:02.49#ibcon#end of sib2, iclass 27, count 0 2006.201.19:01:02.49#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:01:02.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:01:02.49#ibcon#[27=USB\r\n] 2006.201.19:01:02.49#ibcon#*before write, iclass 27, count 0 2006.201.19:01:02.49#ibcon#enter sib2, iclass 27, count 0 2006.201.19:01:02.49#ibcon#flushed, iclass 27, count 0 2006.201.19:01:02.49#ibcon#about to write, iclass 27, count 0 2006.201.19:01:02.49#ibcon#wrote, iclass 27, count 0 2006.201.19:01:02.49#ibcon#about to read 3, iclass 27, count 0 2006.201.19:01:02.52#ibcon#read 3, iclass 27, count 0 2006.201.19:01:02.52#ibcon#about to read 4, iclass 27, count 0 2006.201.19:01:02.52#ibcon#read 4, iclass 27, count 0 2006.201.19:01:02.52#ibcon#about to read 5, iclass 27, count 0 2006.201.19:01:02.52#ibcon#read 5, iclass 27, count 0 2006.201.19:01:02.52#ibcon#about to read 6, iclass 27, count 0 2006.201.19:01:02.52#ibcon#read 6, iclass 27, count 0 2006.201.19:01:02.52#ibcon#end of sib2, iclass 27, count 0 2006.201.19:01:02.52#ibcon#*after write, iclass 27, count 0 2006.201.19:01:02.52#ibcon#*before return 0, iclass 27, count 0 2006.201.19:01:02.52#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:01:02.52#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:01:02.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:01:02.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:01:02.52$vck44/vblo=4,679.99 2006.201.19:01:02.52#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.19:01:02.52#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.19:01:02.52#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:02.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:01:02.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:01:02.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:01:02.52#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:01:02.52#ibcon#first serial, iclass 29, count 0 2006.201.19:01:02.52#ibcon#enter sib2, iclass 29, count 0 2006.201.19:01:02.52#ibcon#flushed, iclass 29, count 0 2006.201.19:01:02.52#ibcon#about to write, iclass 29, count 0 2006.201.19:01:02.52#ibcon#wrote, iclass 29, count 0 2006.201.19:01:02.52#ibcon#about to read 3, iclass 29, count 0 2006.201.19:01:02.54#ibcon#read 3, iclass 29, count 0 2006.201.19:01:02.54#ibcon#about to read 4, iclass 29, count 0 2006.201.19:01:02.54#ibcon#read 4, iclass 29, count 0 2006.201.19:01:02.54#ibcon#about to read 5, iclass 29, count 0 2006.201.19:01:02.54#ibcon#read 5, iclass 29, count 0 2006.201.19:01:02.54#ibcon#about to read 6, iclass 29, count 0 2006.201.19:01:02.54#ibcon#read 6, iclass 29, count 0 2006.201.19:01:02.54#ibcon#end of sib2, iclass 29, count 0 2006.201.19:01:02.54#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:01:02.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:01:02.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:01:02.54#ibcon#*before write, iclass 29, count 0 2006.201.19:01:02.54#ibcon#enter sib2, iclass 29, count 0 2006.201.19:01:02.54#ibcon#flushed, iclass 29, count 0 2006.201.19:01:02.54#ibcon#about to write, iclass 29, count 0 2006.201.19:01:02.54#ibcon#wrote, iclass 29, count 0 2006.201.19:01:02.54#ibcon#about to read 3, iclass 29, count 0 2006.201.19:01:02.59#ibcon#read 3, iclass 29, count 0 2006.201.19:01:02.59#ibcon#about to read 4, iclass 29, count 0 2006.201.19:01:02.59#ibcon#read 4, iclass 29, count 0 2006.201.19:01:02.59#ibcon#about to read 5, iclass 29, count 0 2006.201.19:01:02.59#ibcon#read 5, iclass 29, count 0 2006.201.19:01:02.59#ibcon#about to read 6, iclass 29, count 0 2006.201.19:01:02.59#ibcon#read 6, iclass 29, count 0 2006.201.19:01:02.59#ibcon#end of sib2, iclass 29, count 0 2006.201.19:01:02.59#ibcon#*after write, iclass 29, count 0 2006.201.19:01:02.59#ibcon#*before return 0, iclass 29, count 0 2006.201.19:01:02.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:01:02.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:01:02.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:01:02.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:01:02.59$vck44/vb=4,5 2006.201.19:01:02.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.19:01:02.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.19:01:02.59#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:02.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:01:02.64#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:01:02.64#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:01:02.64#ibcon#enter wrdev, iclass 31, count 2 2006.201.19:01:02.64#ibcon#first serial, iclass 31, count 2 2006.201.19:01:02.64#ibcon#enter sib2, iclass 31, count 2 2006.201.19:01:02.64#ibcon#flushed, iclass 31, count 2 2006.201.19:01:02.64#ibcon#about to write, iclass 31, count 2 2006.201.19:01:02.64#ibcon#wrote, iclass 31, count 2 2006.201.19:01:02.64#ibcon#about to read 3, iclass 31, count 2 2006.201.19:01:02.66#ibcon#read 3, iclass 31, count 2 2006.201.19:01:02.66#ibcon#about to read 4, iclass 31, count 2 2006.201.19:01:02.66#ibcon#read 4, iclass 31, count 2 2006.201.19:01:02.66#ibcon#about to read 5, iclass 31, count 2 2006.201.19:01:02.66#ibcon#read 5, iclass 31, count 2 2006.201.19:01:02.66#ibcon#about to read 6, iclass 31, count 2 2006.201.19:01:02.66#ibcon#read 6, iclass 31, count 2 2006.201.19:01:02.66#ibcon#end of sib2, iclass 31, count 2 2006.201.19:01:02.66#ibcon#*mode == 0, iclass 31, count 2 2006.201.19:01:02.66#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.19:01:02.66#ibcon#[27=AT04-05\r\n] 2006.201.19:01:02.66#ibcon#*before write, iclass 31, count 2 2006.201.19:01:02.66#ibcon#enter sib2, iclass 31, count 2 2006.201.19:01:02.66#ibcon#flushed, iclass 31, count 2 2006.201.19:01:02.66#ibcon#about to write, iclass 31, count 2 2006.201.19:01:02.66#ibcon#wrote, iclass 31, count 2 2006.201.19:01:02.66#ibcon#about to read 3, iclass 31, count 2 2006.201.19:01:02.69#ibcon#read 3, iclass 31, count 2 2006.201.19:01:02.69#ibcon#about to read 4, iclass 31, count 2 2006.201.19:01:02.69#ibcon#read 4, iclass 31, count 2 2006.201.19:01:02.69#ibcon#about to read 5, iclass 31, count 2 2006.201.19:01:02.69#ibcon#read 5, iclass 31, count 2 2006.201.19:01:02.69#ibcon#about to read 6, iclass 31, count 2 2006.201.19:01:02.69#ibcon#read 6, iclass 31, count 2 2006.201.19:01:02.69#ibcon#end of sib2, iclass 31, count 2 2006.201.19:01:02.69#ibcon#*after write, iclass 31, count 2 2006.201.19:01:02.69#ibcon#*before return 0, iclass 31, count 2 2006.201.19:01:02.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:01:02.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:01:02.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.19:01:02.69#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:02.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:01:02.81#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:01:02.81#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:01:02.81#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:01:02.81#ibcon#first serial, iclass 31, count 0 2006.201.19:01:02.81#ibcon#enter sib2, iclass 31, count 0 2006.201.19:01:02.81#ibcon#flushed, iclass 31, count 0 2006.201.19:01:02.81#ibcon#about to write, iclass 31, count 0 2006.201.19:01:02.81#ibcon#wrote, iclass 31, count 0 2006.201.19:01:02.81#ibcon#about to read 3, iclass 31, count 0 2006.201.19:01:02.83#ibcon#read 3, iclass 31, count 0 2006.201.19:01:02.83#ibcon#about to read 4, iclass 31, count 0 2006.201.19:01:02.83#ibcon#read 4, iclass 31, count 0 2006.201.19:01:02.83#ibcon#about to read 5, iclass 31, count 0 2006.201.19:01:02.83#ibcon#read 5, iclass 31, count 0 2006.201.19:01:02.83#ibcon#about to read 6, iclass 31, count 0 2006.201.19:01:02.83#ibcon#read 6, iclass 31, count 0 2006.201.19:01:02.83#ibcon#end of sib2, iclass 31, count 0 2006.201.19:01:02.83#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:01:02.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:01:02.83#ibcon#[27=USB\r\n] 2006.201.19:01:02.83#ibcon#*before write, iclass 31, count 0 2006.201.19:01:02.83#ibcon#enter sib2, iclass 31, count 0 2006.201.19:01:02.83#ibcon#flushed, iclass 31, count 0 2006.201.19:01:02.83#ibcon#about to write, iclass 31, count 0 2006.201.19:01:02.83#ibcon#wrote, iclass 31, count 0 2006.201.19:01:02.83#ibcon#about to read 3, iclass 31, count 0 2006.201.19:01:02.86#ibcon#read 3, iclass 31, count 0 2006.201.19:01:02.86#ibcon#about to read 4, iclass 31, count 0 2006.201.19:01:02.86#ibcon#read 4, iclass 31, count 0 2006.201.19:01:02.86#ibcon#about to read 5, iclass 31, count 0 2006.201.19:01:02.86#ibcon#read 5, iclass 31, count 0 2006.201.19:01:02.86#ibcon#about to read 6, iclass 31, count 0 2006.201.19:01:02.86#ibcon#read 6, iclass 31, count 0 2006.201.19:01:02.86#ibcon#end of sib2, iclass 31, count 0 2006.201.19:01:02.86#ibcon#*after write, iclass 31, count 0 2006.201.19:01:02.86#ibcon#*before return 0, iclass 31, count 0 2006.201.19:01:02.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:01:02.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:01:02.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:01:02.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:01:02.86$vck44/vblo=5,709.99 2006.201.19:01:02.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.19:01:02.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.19:01:02.86#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:02.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:01:02.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:01:02.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:01:02.86#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:01:02.86#ibcon#first serial, iclass 33, count 0 2006.201.19:01:02.86#ibcon#enter sib2, iclass 33, count 0 2006.201.19:01:02.86#ibcon#flushed, iclass 33, count 0 2006.201.19:01:02.86#ibcon#about to write, iclass 33, count 0 2006.201.19:01:02.86#ibcon#wrote, iclass 33, count 0 2006.201.19:01:02.86#ibcon#about to read 3, iclass 33, count 0 2006.201.19:01:02.88#ibcon#read 3, iclass 33, count 0 2006.201.19:01:02.88#ibcon#about to read 4, iclass 33, count 0 2006.201.19:01:02.88#ibcon#read 4, iclass 33, count 0 2006.201.19:01:02.88#ibcon#about to read 5, iclass 33, count 0 2006.201.19:01:02.88#ibcon#read 5, iclass 33, count 0 2006.201.19:01:02.88#ibcon#about to read 6, iclass 33, count 0 2006.201.19:01:02.88#ibcon#read 6, iclass 33, count 0 2006.201.19:01:02.88#ibcon#end of sib2, iclass 33, count 0 2006.201.19:01:02.88#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:01:02.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:01:02.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:01:02.88#ibcon#*before write, iclass 33, count 0 2006.201.19:01:02.88#ibcon#enter sib2, iclass 33, count 0 2006.201.19:01:02.88#ibcon#flushed, iclass 33, count 0 2006.201.19:01:02.88#ibcon#about to write, iclass 33, count 0 2006.201.19:01:02.88#ibcon#wrote, iclass 33, count 0 2006.201.19:01:02.88#ibcon#about to read 3, iclass 33, count 0 2006.201.19:01:02.92#ibcon#read 3, iclass 33, count 0 2006.201.19:01:02.92#ibcon#about to read 4, iclass 33, count 0 2006.201.19:01:02.92#ibcon#read 4, iclass 33, count 0 2006.201.19:01:02.92#ibcon#about to read 5, iclass 33, count 0 2006.201.19:01:02.92#ibcon#read 5, iclass 33, count 0 2006.201.19:01:02.92#ibcon#about to read 6, iclass 33, count 0 2006.201.19:01:02.92#ibcon#read 6, iclass 33, count 0 2006.201.19:01:02.92#ibcon#end of sib2, iclass 33, count 0 2006.201.19:01:02.92#ibcon#*after write, iclass 33, count 0 2006.201.19:01:02.92#ibcon#*before return 0, iclass 33, count 0 2006.201.19:01:02.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:01:02.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:01:02.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:01:02.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:01:02.92$vck44/vb=5,4 2006.201.19:01:02.92#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.19:01:02.92#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.19:01:02.92#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:02.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:01:02.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:01:02.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:01:02.98#ibcon#enter wrdev, iclass 35, count 2 2006.201.19:01:02.98#ibcon#first serial, iclass 35, count 2 2006.201.19:01:02.98#ibcon#enter sib2, iclass 35, count 2 2006.201.19:01:02.98#ibcon#flushed, iclass 35, count 2 2006.201.19:01:02.98#ibcon#about to write, iclass 35, count 2 2006.201.19:01:02.98#ibcon#wrote, iclass 35, count 2 2006.201.19:01:02.98#ibcon#about to read 3, iclass 35, count 2 2006.201.19:01:03.00#ibcon#read 3, iclass 35, count 2 2006.201.19:01:03.00#ibcon#about to read 4, iclass 35, count 2 2006.201.19:01:03.00#ibcon#read 4, iclass 35, count 2 2006.201.19:01:03.00#ibcon#about to read 5, iclass 35, count 2 2006.201.19:01:03.00#ibcon#read 5, iclass 35, count 2 2006.201.19:01:03.00#ibcon#about to read 6, iclass 35, count 2 2006.201.19:01:03.00#ibcon#read 6, iclass 35, count 2 2006.201.19:01:03.00#ibcon#end of sib2, iclass 35, count 2 2006.201.19:01:03.00#ibcon#*mode == 0, iclass 35, count 2 2006.201.19:01:03.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.19:01:03.00#ibcon#[27=AT05-04\r\n] 2006.201.19:01:03.00#ibcon#*before write, iclass 35, count 2 2006.201.19:01:03.00#ibcon#enter sib2, iclass 35, count 2 2006.201.19:01:03.00#ibcon#flushed, iclass 35, count 2 2006.201.19:01:03.00#ibcon#about to write, iclass 35, count 2 2006.201.19:01:03.00#ibcon#wrote, iclass 35, count 2 2006.201.19:01:03.00#ibcon#about to read 3, iclass 35, count 2 2006.201.19:01:03.03#ibcon#read 3, iclass 35, count 2 2006.201.19:01:03.03#ibcon#about to read 4, iclass 35, count 2 2006.201.19:01:03.03#ibcon#read 4, iclass 35, count 2 2006.201.19:01:03.03#ibcon#about to read 5, iclass 35, count 2 2006.201.19:01:03.03#ibcon#read 5, iclass 35, count 2 2006.201.19:01:03.03#ibcon#about to read 6, iclass 35, count 2 2006.201.19:01:03.03#ibcon#read 6, iclass 35, count 2 2006.201.19:01:03.03#ibcon#end of sib2, iclass 35, count 2 2006.201.19:01:03.03#ibcon#*after write, iclass 35, count 2 2006.201.19:01:03.03#ibcon#*before return 0, iclass 35, count 2 2006.201.19:01:03.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:01:03.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:01:03.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.19:01:03.03#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:03.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:03.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:03.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:03.15#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:01:03.15#ibcon#first serial, iclass 35, count 0 2006.201.19:01:03.15#ibcon#enter sib2, iclass 35, count 0 2006.201.19:01:03.15#ibcon#flushed, iclass 35, count 0 2006.201.19:01:03.15#ibcon#about to write, iclass 35, count 0 2006.201.19:01:03.15#ibcon#wrote, iclass 35, count 0 2006.201.19:01:03.15#ibcon#about to read 3, iclass 35, count 0 2006.201.19:01:03.17#ibcon#read 3, iclass 35, count 0 2006.201.19:01:03.17#ibcon#about to read 4, iclass 35, count 0 2006.201.19:01:03.17#ibcon#read 4, iclass 35, count 0 2006.201.19:01:03.17#ibcon#about to read 5, iclass 35, count 0 2006.201.19:01:03.17#ibcon#read 5, iclass 35, count 0 2006.201.19:01:03.17#ibcon#about to read 6, iclass 35, count 0 2006.201.19:01:03.17#ibcon#read 6, iclass 35, count 0 2006.201.19:01:03.17#ibcon#end of sib2, iclass 35, count 0 2006.201.19:01:03.17#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:01:03.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:01:03.17#ibcon#[27=USB\r\n] 2006.201.19:01:03.17#ibcon#*before write, iclass 35, count 0 2006.201.19:01:03.17#ibcon#enter sib2, iclass 35, count 0 2006.201.19:01:03.17#ibcon#flushed, iclass 35, count 0 2006.201.19:01:03.17#ibcon#about to write, iclass 35, count 0 2006.201.19:01:03.17#ibcon#wrote, iclass 35, count 0 2006.201.19:01:03.17#ibcon#about to read 3, iclass 35, count 0 2006.201.19:01:03.20#ibcon#read 3, iclass 35, count 0 2006.201.19:01:03.20#ibcon#about to read 4, iclass 35, count 0 2006.201.19:01:03.20#ibcon#read 4, iclass 35, count 0 2006.201.19:01:03.20#ibcon#about to read 5, iclass 35, count 0 2006.201.19:01:03.20#ibcon#read 5, iclass 35, count 0 2006.201.19:01:03.20#ibcon#about to read 6, iclass 35, count 0 2006.201.19:01:03.20#ibcon#read 6, iclass 35, count 0 2006.201.19:01:03.20#ibcon#end of sib2, iclass 35, count 0 2006.201.19:01:03.20#ibcon#*after write, iclass 35, count 0 2006.201.19:01:03.20#ibcon#*before return 0, iclass 35, count 0 2006.201.19:01:03.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:03.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:01:03.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:01:03.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:01:03.20$vck44/vblo=6,719.99 2006.201.19:01:03.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.19:01:03.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.19:01:03.20#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:03.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:03.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:03.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:03.20#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:01:03.20#ibcon#first serial, iclass 37, count 0 2006.201.19:01:03.20#ibcon#enter sib2, iclass 37, count 0 2006.201.19:01:03.20#ibcon#flushed, iclass 37, count 0 2006.201.19:01:03.20#ibcon#about to write, iclass 37, count 0 2006.201.19:01:03.20#ibcon#wrote, iclass 37, count 0 2006.201.19:01:03.20#ibcon#about to read 3, iclass 37, count 0 2006.201.19:01:03.22#ibcon#read 3, iclass 37, count 0 2006.201.19:01:03.22#ibcon#about to read 4, iclass 37, count 0 2006.201.19:01:03.22#ibcon#read 4, iclass 37, count 0 2006.201.19:01:03.22#ibcon#about to read 5, iclass 37, count 0 2006.201.19:01:03.22#ibcon#read 5, iclass 37, count 0 2006.201.19:01:03.22#ibcon#about to read 6, iclass 37, count 0 2006.201.19:01:03.22#ibcon#read 6, iclass 37, count 0 2006.201.19:01:03.22#ibcon#end of sib2, iclass 37, count 0 2006.201.19:01:03.22#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:01:03.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:01:03.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:01:03.22#ibcon#*before write, iclass 37, count 0 2006.201.19:01:03.22#ibcon#enter sib2, iclass 37, count 0 2006.201.19:01:03.22#ibcon#flushed, iclass 37, count 0 2006.201.19:01:03.22#ibcon#about to write, iclass 37, count 0 2006.201.19:01:03.22#ibcon#wrote, iclass 37, count 0 2006.201.19:01:03.22#ibcon#about to read 3, iclass 37, count 0 2006.201.19:01:03.26#ibcon#read 3, iclass 37, count 0 2006.201.19:01:03.26#ibcon#about to read 4, iclass 37, count 0 2006.201.19:01:03.26#ibcon#read 4, iclass 37, count 0 2006.201.19:01:03.26#ibcon#about to read 5, iclass 37, count 0 2006.201.19:01:03.26#ibcon#read 5, iclass 37, count 0 2006.201.19:01:03.26#ibcon#about to read 6, iclass 37, count 0 2006.201.19:01:03.26#ibcon#read 6, iclass 37, count 0 2006.201.19:01:03.26#ibcon#end of sib2, iclass 37, count 0 2006.201.19:01:03.26#ibcon#*after write, iclass 37, count 0 2006.201.19:01:03.26#ibcon#*before return 0, iclass 37, count 0 2006.201.19:01:03.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:03.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:01:03.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:01:03.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:01:03.26$vck44/vb=6,4 2006.201.19:01:03.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.19:01:03.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.19:01:03.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:03.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:03.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:03.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:03.32#ibcon#enter wrdev, iclass 39, count 2 2006.201.19:01:03.32#ibcon#first serial, iclass 39, count 2 2006.201.19:01:03.32#ibcon#enter sib2, iclass 39, count 2 2006.201.19:01:03.32#ibcon#flushed, iclass 39, count 2 2006.201.19:01:03.32#ibcon#about to write, iclass 39, count 2 2006.201.19:01:03.32#ibcon#wrote, iclass 39, count 2 2006.201.19:01:03.32#ibcon#about to read 3, iclass 39, count 2 2006.201.19:01:03.34#ibcon#read 3, iclass 39, count 2 2006.201.19:01:03.34#ibcon#about to read 4, iclass 39, count 2 2006.201.19:01:03.34#ibcon#read 4, iclass 39, count 2 2006.201.19:01:03.34#ibcon#about to read 5, iclass 39, count 2 2006.201.19:01:03.34#ibcon#read 5, iclass 39, count 2 2006.201.19:01:03.34#ibcon#about to read 6, iclass 39, count 2 2006.201.19:01:03.34#ibcon#read 6, iclass 39, count 2 2006.201.19:01:03.34#ibcon#end of sib2, iclass 39, count 2 2006.201.19:01:03.34#ibcon#*mode == 0, iclass 39, count 2 2006.201.19:01:03.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.19:01:03.34#ibcon#[27=AT06-04\r\n] 2006.201.19:01:03.34#ibcon#*before write, iclass 39, count 2 2006.201.19:01:03.34#ibcon#enter sib2, iclass 39, count 2 2006.201.19:01:03.34#ibcon#flushed, iclass 39, count 2 2006.201.19:01:03.34#ibcon#about to write, iclass 39, count 2 2006.201.19:01:03.34#ibcon#wrote, iclass 39, count 2 2006.201.19:01:03.34#ibcon#about to read 3, iclass 39, count 2 2006.201.19:01:03.37#ibcon#read 3, iclass 39, count 2 2006.201.19:01:03.37#ibcon#about to read 4, iclass 39, count 2 2006.201.19:01:03.37#ibcon#read 4, iclass 39, count 2 2006.201.19:01:03.37#ibcon#about to read 5, iclass 39, count 2 2006.201.19:01:03.37#ibcon#read 5, iclass 39, count 2 2006.201.19:01:03.37#ibcon#about to read 6, iclass 39, count 2 2006.201.19:01:03.37#ibcon#read 6, iclass 39, count 2 2006.201.19:01:03.37#ibcon#end of sib2, iclass 39, count 2 2006.201.19:01:03.37#ibcon#*after write, iclass 39, count 2 2006.201.19:01:03.37#ibcon#*before return 0, iclass 39, count 2 2006.201.19:01:03.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:03.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:01:03.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.19:01:03.37#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:03.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:03.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:03.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:03.49#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:01:03.49#ibcon#first serial, iclass 39, count 0 2006.201.19:01:03.49#ibcon#enter sib2, iclass 39, count 0 2006.201.19:01:03.49#ibcon#flushed, iclass 39, count 0 2006.201.19:01:03.49#ibcon#about to write, iclass 39, count 0 2006.201.19:01:03.49#ibcon#wrote, iclass 39, count 0 2006.201.19:01:03.49#ibcon#about to read 3, iclass 39, count 0 2006.201.19:01:03.51#ibcon#read 3, iclass 39, count 0 2006.201.19:01:03.51#ibcon#about to read 4, iclass 39, count 0 2006.201.19:01:03.51#ibcon#read 4, iclass 39, count 0 2006.201.19:01:03.51#ibcon#about to read 5, iclass 39, count 0 2006.201.19:01:03.51#ibcon#read 5, iclass 39, count 0 2006.201.19:01:03.51#ibcon#about to read 6, iclass 39, count 0 2006.201.19:01:03.51#ibcon#read 6, iclass 39, count 0 2006.201.19:01:03.51#ibcon#end of sib2, iclass 39, count 0 2006.201.19:01:03.51#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:01:03.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:01:03.51#ibcon#[27=USB\r\n] 2006.201.19:01:03.51#ibcon#*before write, iclass 39, count 0 2006.201.19:01:03.51#ibcon#enter sib2, iclass 39, count 0 2006.201.19:01:03.51#ibcon#flushed, iclass 39, count 0 2006.201.19:01:03.51#ibcon#about to write, iclass 39, count 0 2006.201.19:01:03.51#ibcon#wrote, iclass 39, count 0 2006.201.19:01:03.51#ibcon#about to read 3, iclass 39, count 0 2006.201.19:01:03.54#ibcon#read 3, iclass 39, count 0 2006.201.19:01:03.54#ibcon#about to read 4, iclass 39, count 0 2006.201.19:01:03.54#ibcon#read 4, iclass 39, count 0 2006.201.19:01:03.54#ibcon#about to read 5, iclass 39, count 0 2006.201.19:01:03.54#ibcon#read 5, iclass 39, count 0 2006.201.19:01:03.54#ibcon#about to read 6, iclass 39, count 0 2006.201.19:01:03.54#ibcon#read 6, iclass 39, count 0 2006.201.19:01:03.54#ibcon#end of sib2, iclass 39, count 0 2006.201.19:01:03.54#ibcon#*after write, iclass 39, count 0 2006.201.19:01:03.54#ibcon#*before return 0, iclass 39, count 0 2006.201.19:01:03.54#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:03.54#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:01:03.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:01:03.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:01:03.54$vck44/vblo=7,734.99 2006.201.19:01:03.54#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.19:01:03.54#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.19:01:03.54#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:03.54#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:03.54#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:03.54#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:03.54#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:01:03.54#ibcon#first serial, iclass 2, count 0 2006.201.19:01:03.54#ibcon#enter sib2, iclass 2, count 0 2006.201.19:01:03.54#ibcon#flushed, iclass 2, count 0 2006.201.19:01:03.54#ibcon#about to write, iclass 2, count 0 2006.201.19:01:03.54#ibcon#wrote, iclass 2, count 0 2006.201.19:01:03.54#ibcon#about to read 3, iclass 2, count 0 2006.201.19:01:03.56#ibcon#read 3, iclass 2, count 0 2006.201.19:01:03.56#ibcon#about to read 4, iclass 2, count 0 2006.201.19:01:03.56#ibcon#read 4, iclass 2, count 0 2006.201.19:01:03.56#ibcon#about to read 5, iclass 2, count 0 2006.201.19:01:03.56#ibcon#read 5, iclass 2, count 0 2006.201.19:01:03.56#ibcon#about to read 6, iclass 2, count 0 2006.201.19:01:03.56#ibcon#read 6, iclass 2, count 0 2006.201.19:01:03.56#ibcon#end of sib2, iclass 2, count 0 2006.201.19:01:03.56#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:01:03.56#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:01:03.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:01:03.56#ibcon#*before write, iclass 2, count 0 2006.201.19:01:03.56#ibcon#enter sib2, iclass 2, count 0 2006.201.19:01:03.56#ibcon#flushed, iclass 2, count 0 2006.201.19:01:03.56#ibcon#about to write, iclass 2, count 0 2006.201.19:01:03.56#ibcon#wrote, iclass 2, count 0 2006.201.19:01:03.56#ibcon#about to read 3, iclass 2, count 0 2006.201.19:01:03.60#ibcon#read 3, iclass 2, count 0 2006.201.19:01:03.60#ibcon#about to read 4, iclass 2, count 0 2006.201.19:01:03.60#ibcon#read 4, iclass 2, count 0 2006.201.19:01:03.60#ibcon#about to read 5, iclass 2, count 0 2006.201.19:01:03.60#ibcon#read 5, iclass 2, count 0 2006.201.19:01:03.60#ibcon#about to read 6, iclass 2, count 0 2006.201.19:01:03.60#ibcon#read 6, iclass 2, count 0 2006.201.19:01:03.60#ibcon#end of sib2, iclass 2, count 0 2006.201.19:01:03.60#ibcon#*after write, iclass 2, count 0 2006.201.19:01:03.60#ibcon#*before return 0, iclass 2, count 0 2006.201.19:01:03.60#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:03.60#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:01:03.60#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:01:03.60#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:01:03.60$vck44/vb=7,4 2006.201.19:01:03.60#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.19:01:03.60#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.19:01:03.60#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:03.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:03.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:03.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:03.66#ibcon#enter wrdev, iclass 5, count 2 2006.201.19:01:03.66#ibcon#first serial, iclass 5, count 2 2006.201.19:01:03.66#ibcon#enter sib2, iclass 5, count 2 2006.201.19:01:03.66#ibcon#flushed, iclass 5, count 2 2006.201.19:01:03.66#ibcon#about to write, iclass 5, count 2 2006.201.19:01:03.66#ibcon#wrote, iclass 5, count 2 2006.201.19:01:03.66#ibcon#about to read 3, iclass 5, count 2 2006.201.19:01:03.68#ibcon#read 3, iclass 5, count 2 2006.201.19:01:03.68#ibcon#about to read 4, iclass 5, count 2 2006.201.19:01:03.68#ibcon#read 4, iclass 5, count 2 2006.201.19:01:03.68#ibcon#about to read 5, iclass 5, count 2 2006.201.19:01:03.68#ibcon#read 5, iclass 5, count 2 2006.201.19:01:03.68#ibcon#about to read 6, iclass 5, count 2 2006.201.19:01:03.68#ibcon#read 6, iclass 5, count 2 2006.201.19:01:03.68#ibcon#end of sib2, iclass 5, count 2 2006.201.19:01:03.68#ibcon#*mode == 0, iclass 5, count 2 2006.201.19:01:03.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.19:01:03.68#ibcon#[27=AT07-04\r\n] 2006.201.19:01:03.68#ibcon#*before write, iclass 5, count 2 2006.201.19:01:03.68#ibcon#enter sib2, iclass 5, count 2 2006.201.19:01:03.68#ibcon#flushed, iclass 5, count 2 2006.201.19:01:03.68#ibcon#about to write, iclass 5, count 2 2006.201.19:01:03.68#ibcon#wrote, iclass 5, count 2 2006.201.19:01:03.68#ibcon#about to read 3, iclass 5, count 2 2006.201.19:01:03.71#ibcon#read 3, iclass 5, count 2 2006.201.19:01:03.71#ibcon#about to read 4, iclass 5, count 2 2006.201.19:01:03.71#ibcon#read 4, iclass 5, count 2 2006.201.19:01:03.71#ibcon#about to read 5, iclass 5, count 2 2006.201.19:01:03.71#ibcon#read 5, iclass 5, count 2 2006.201.19:01:03.71#ibcon#about to read 6, iclass 5, count 2 2006.201.19:01:03.71#ibcon#read 6, iclass 5, count 2 2006.201.19:01:03.71#ibcon#end of sib2, iclass 5, count 2 2006.201.19:01:03.71#ibcon#*after write, iclass 5, count 2 2006.201.19:01:03.71#ibcon#*before return 0, iclass 5, count 2 2006.201.19:01:03.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:03.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:01:03.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.19:01:03.71#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:03.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:03.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:03.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:03.83#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:01:03.83#ibcon#first serial, iclass 5, count 0 2006.201.19:01:03.83#ibcon#enter sib2, iclass 5, count 0 2006.201.19:01:03.83#ibcon#flushed, iclass 5, count 0 2006.201.19:01:03.83#ibcon#about to write, iclass 5, count 0 2006.201.19:01:03.83#ibcon#wrote, iclass 5, count 0 2006.201.19:01:03.83#ibcon#about to read 3, iclass 5, count 0 2006.201.19:01:03.85#ibcon#read 3, iclass 5, count 0 2006.201.19:01:03.85#ibcon#about to read 4, iclass 5, count 0 2006.201.19:01:03.85#ibcon#read 4, iclass 5, count 0 2006.201.19:01:03.85#ibcon#about to read 5, iclass 5, count 0 2006.201.19:01:03.85#ibcon#read 5, iclass 5, count 0 2006.201.19:01:03.85#ibcon#about to read 6, iclass 5, count 0 2006.201.19:01:03.85#ibcon#read 6, iclass 5, count 0 2006.201.19:01:03.85#ibcon#end of sib2, iclass 5, count 0 2006.201.19:01:03.85#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:01:03.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:01:03.85#ibcon#[27=USB\r\n] 2006.201.19:01:03.85#ibcon#*before write, iclass 5, count 0 2006.201.19:01:03.85#ibcon#enter sib2, iclass 5, count 0 2006.201.19:01:03.85#ibcon#flushed, iclass 5, count 0 2006.201.19:01:03.85#ibcon#about to write, iclass 5, count 0 2006.201.19:01:03.85#ibcon#wrote, iclass 5, count 0 2006.201.19:01:03.85#ibcon#about to read 3, iclass 5, count 0 2006.201.19:01:03.88#ibcon#read 3, iclass 5, count 0 2006.201.19:01:03.88#ibcon#about to read 4, iclass 5, count 0 2006.201.19:01:03.88#ibcon#read 4, iclass 5, count 0 2006.201.19:01:03.88#ibcon#about to read 5, iclass 5, count 0 2006.201.19:01:03.88#ibcon#read 5, iclass 5, count 0 2006.201.19:01:03.88#ibcon#about to read 6, iclass 5, count 0 2006.201.19:01:03.88#ibcon#read 6, iclass 5, count 0 2006.201.19:01:03.88#ibcon#end of sib2, iclass 5, count 0 2006.201.19:01:03.88#ibcon#*after write, iclass 5, count 0 2006.201.19:01:03.88#ibcon#*before return 0, iclass 5, count 0 2006.201.19:01:03.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:03.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:01:03.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:01:03.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:01:03.88$vck44/vblo=8,744.99 2006.201.19:01:03.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.19:01:03.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.19:01:03.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:01:03.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:03.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:03.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:03.88#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:01:03.88#ibcon#first serial, iclass 7, count 0 2006.201.19:01:03.88#ibcon#enter sib2, iclass 7, count 0 2006.201.19:01:03.88#ibcon#flushed, iclass 7, count 0 2006.201.19:01:03.88#ibcon#about to write, iclass 7, count 0 2006.201.19:01:03.88#ibcon#wrote, iclass 7, count 0 2006.201.19:01:03.88#ibcon#about to read 3, iclass 7, count 0 2006.201.19:01:03.90#ibcon#read 3, iclass 7, count 0 2006.201.19:01:03.90#ibcon#about to read 4, iclass 7, count 0 2006.201.19:01:03.90#ibcon#read 4, iclass 7, count 0 2006.201.19:01:03.90#ibcon#about to read 5, iclass 7, count 0 2006.201.19:01:03.90#ibcon#read 5, iclass 7, count 0 2006.201.19:01:03.90#ibcon#about to read 6, iclass 7, count 0 2006.201.19:01:03.90#ibcon#read 6, iclass 7, count 0 2006.201.19:01:03.90#ibcon#end of sib2, iclass 7, count 0 2006.201.19:01:03.90#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:01:03.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:01:03.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:01:03.90#ibcon#*before write, iclass 7, count 0 2006.201.19:01:03.90#ibcon#enter sib2, iclass 7, count 0 2006.201.19:01:03.90#ibcon#flushed, iclass 7, count 0 2006.201.19:01:03.90#ibcon#about to write, iclass 7, count 0 2006.201.19:01:03.90#ibcon#wrote, iclass 7, count 0 2006.201.19:01:03.90#ibcon#about to read 3, iclass 7, count 0 2006.201.19:01:03.95#ibcon#read 3, iclass 7, count 0 2006.201.19:01:03.95#ibcon#about to read 4, iclass 7, count 0 2006.201.19:01:03.95#ibcon#read 4, iclass 7, count 0 2006.201.19:01:03.95#ibcon#about to read 5, iclass 7, count 0 2006.201.19:01:03.95#ibcon#read 5, iclass 7, count 0 2006.201.19:01:03.95#ibcon#about to read 6, iclass 7, count 0 2006.201.19:01:03.95#ibcon#read 6, iclass 7, count 0 2006.201.19:01:03.95#ibcon#end of sib2, iclass 7, count 0 2006.201.19:01:03.95#ibcon#*after write, iclass 7, count 0 2006.201.19:01:03.95#ibcon#*before return 0, iclass 7, count 0 2006.201.19:01:03.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:03.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:01:03.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:01:03.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:01:03.95$vck44/vb=8,4 2006.201.19:01:03.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.19:01:03.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.19:01:03.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:01:03.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:04.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:04.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:04.00#ibcon#enter wrdev, iclass 11, count 2 2006.201.19:01:04.00#ibcon#first serial, iclass 11, count 2 2006.201.19:01:04.00#ibcon#enter sib2, iclass 11, count 2 2006.201.19:01:04.00#ibcon#flushed, iclass 11, count 2 2006.201.19:01:04.00#ibcon#about to write, iclass 11, count 2 2006.201.19:01:04.00#ibcon#wrote, iclass 11, count 2 2006.201.19:01:04.00#ibcon#about to read 3, iclass 11, count 2 2006.201.19:01:04.02#ibcon#read 3, iclass 11, count 2 2006.201.19:01:04.02#ibcon#about to read 4, iclass 11, count 2 2006.201.19:01:04.02#ibcon#read 4, iclass 11, count 2 2006.201.19:01:04.02#ibcon#about to read 5, iclass 11, count 2 2006.201.19:01:04.02#ibcon#read 5, iclass 11, count 2 2006.201.19:01:04.02#ibcon#about to read 6, iclass 11, count 2 2006.201.19:01:04.02#ibcon#read 6, iclass 11, count 2 2006.201.19:01:04.02#ibcon#end of sib2, iclass 11, count 2 2006.201.19:01:04.02#ibcon#*mode == 0, iclass 11, count 2 2006.201.19:01:04.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.19:01:04.02#ibcon#[27=AT08-04\r\n] 2006.201.19:01:04.02#ibcon#*before write, iclass 11, count 2 2006.201.19:01:04.02#ibcon#enter sib2, iclass 11, count 2 2006.201.19:01:04.02#ibcon#flushed, iclass 11, count 2 2006.201.19:01:04.02#ibcon#about to write, iclass 11, count 2 2006.201.19:01:04.02#ibcon#wrote, iclass 11, count 2 2006.201.19:01:04.02#ibcon#about to read 3, iclass 11, count 2 2006.201.19:01:04.05#ibcon#read 3, iclass 11, count 2 2006.201.19:01:04.05#ibcon#about to read 4, iclass 11, count 2 2006.201.19:01:04.05#ibcon#read 4, iclass 11, count 2 2006.201.19:01:04.05#ibcon#about to read 5, iclass 11, count 2 2006.201.19:01:04.05#ibcon#read 5, iclass 11, count 2 2006.201.19:01:04.05#ibcon#about to read 6, iclass 11, count 2 2006.201.19:01:04.05#ibcon#read 6, iclass 11, count 2 2006.201.19:01:04.05#ibcon#end of sib2, iclass 11, count 2 2006.201.19:01:04.05#ibcon#*after write, iclass 11, count 2 2006.201.19:01:04.05#ibcon#*before return 0, iclass 11, count 2 2006.201.19:01:04.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:04.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:01:04.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.19:01:04.05#ibcon#ireg 7 cls_cnt 0 2006.201.19:01:04.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:04.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:04.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:04.17#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:01:04.17#ibcon#first serial, iclass 11, count 0 2006.201.19:01:04.17#ibcon#enter sib2, iclass 11, count 0 2006.201.19:01:04.17#ibcon#flushed, iclass 11, count 0 2006.201.19:01:04.17#ibcon#about to write, iclass 11, count 0 2006.201.19:01:04.17#ibcon#wrote, iclass 11, count 0 2006.201.19:01:04.17#ibcon#about to read 3, iclass 11, count 0 2006.201.19:01:04.20#ibcon#read 3, iclass 11, count 0 2006.201.19:01:04.20#ibcon#about to read 4, iclass 11, count 0 2006.201.19:01:04.20#ibcon#read 4, iclass 11, count 0 2006.201.19:01:04.20#ibcon#about to read 5, iclass 11, count 0 2006.201.19:01:04.20#ibcon#read 5, iclass 11, count 0 2006.201.19:01:04.20#ibcon#about to read 6, iclass 11, count 0 2006.201.19:01:04.20#ibcon#read 6, iclass 11, count 0 2006.201.19:01:04.20#ibcon#end of sib2, iclass 11, count 0 2006.201.19:01:04.20#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:01:04.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:01:04.20#ibcon#[27=USB\r\n] 2006.201.19:01:04.20#ibcon#*before write, iclass 11, count 0 2006.201.19:01:04.20#ibcon#enter sib2, iclass 11, count 0 2006.201.19:01:04.20#ibcon#flushed, iclass 11, count 0 2006.201.19:01:04.20#ibcon#about to write, iclass 11, count 0 2006.201.19:01:04.20#ibcon#wrote, iclass 11, count 0 2006.201.19:01:04.20#ibcon#about to read 3, iclass 11, count 0 2006.201.19:01:04.23#ibcon#read 3, iclass 11, count 0 2006.201.19:01:04.23#ibcon#about to read 4, iclass 11, count 0 2006.201.19:01:04.23#ibcon#read 4, iclass 11, count 0 2006.201.19:01:04.23#ibcon#about to read 5, iclass 11, count 0 2006.201.19:01:04.23#ibcon#read 5, iclass 11, count 0 2006.201.19:01:04.23#ibcon#about to read 6, iclass 11, count 0 2006.201.19:01:04.23#ibcon#read 6, iclass 11, count 0 2006.201.19:01:04.23#ibcon#end of sib2, iclass 11, count 0 2006.201.19:01:04.23#ibcon#*after write, iclass 11, count 0 2006.201.19:01:04.23#ibcon#*before return 0, iclass 11, count 0 2006.201.19:01:04.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:04.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:01:04.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:01:04.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:01:04.23$vck44/vabw=wide 2006.201.19:01:04.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.19:01:04.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.19:01:04.23#ibcon#ireg 8 cls_cnt 0 2006.201.19:01:04.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:04.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:04.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:04.23#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:01:04.23#ibcon#first serial, iclass 13, count 0 2006.201.19:01:04.23#ibcon#enter sib2, iclass 13, count 0 2006.201.19:01:04.23#ibcon#flushed, iclass 13, count 0 2006.201.19:01:04.23#ibcon#about to write, iclass 13, count 0 2006.201.19:01:04.23#ibcon#wrote, iclass 13, count 0 2006.201.19:01:04.23#ibcon#about to read 3, iclass 13, count 0 2006.201.19:01:04.25#ibcon#read 3, iclass 13, count 0 2006.201.19:01:04.25#ibcon#about to read 4, iclass 13, count 0 2006.201.19:01:04.25#ibcon#read 4, iclass 13, count 0 2006.201.19:01:04.25#ibcon#about to read 5, iclass 13, count 0 2006.201.19:01:04.25#ibcon#read 5, iclass 13, count 0 2006.201.19:01:04.25#ibcon#about to read 6, iclass 13, count 0 2006.201.19:01:04.25#ibcon#read 6, iclass 13, count 0 2006.201.19:01:04.25#ibcon#end of sib2, iclass 13, count 0 2006.201.19:01:04.25#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:01:04.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:01:04.25#ibcon#[25=BW32\r\n] 2006.201.19:01:04.25#ibcon#*before write, iclass 13, count 0 2006.201.19:01:04.25#ibcon#enter sib2, iclass 13, count 0 2006.201.19:01:04.25#ibcon#flushed, iclass 13, count 0 2006.201.19:01:04.25#ibcon#about to write, iclass 13, count 0 2006.201.19:01:04.25#ibcon#wrote, iclass 13, count 0 2006.201.19:01:04.25#ibcon#about to read 3, iclass 13, count 0 2006.201.19:01:04.28#ibcon#read 3, iclass 13, count 0 2006.201.19:01:04.28#ibcon#about to read 4, iclass 13, count 0 2006.201.19:01:04.28#ibcon#read 4, iclass 13, count 0 2006.201.19:01:04.28#ibcon#about to read 5, iclass 13, count 0 2006.201.19:01:04.28#ibcon#read 5, iclass 13, count 0 2006.201.19:01:04.28#ibcon#about to read 6, iclass 13, count 0 2006.201.19:01:04.28#ibcon#read 6, iclass 13, count 0 2006.201.19:01:04.28#ibcon#end of sib2, iclass 13, count 0 2006.201.19:01:04.28#ibcon#*after write, iclass 13, count 0 2006.201.19:01:04.28#ibcon#*before return 0, iclass 13, count 0 2006.201.19:01:04.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:04.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:01:04.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:01:04.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:01:04.28$vck44/vbbw=wide 2006.201.19:01:04.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.19:01:04.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.19:01:04.28#ibcon#ireg 8 cls_cnt 0 2006.201.19:01:04.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:01:04.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:01:04.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:01:04.35#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:01:04.35#ibcon#first serial, iclass 15, count 0 2006.201.19:01:04.35#ibcon#enter sib2, iclass 15, count 0 2006.201.19:01:04.35#ibcon#flushed, iclass 15, count 0 2006.201.19:01:04.35#ibcon#about to write, iclass 15, count 0 2006.201.19:01:04.35#ibcon#wrote, iclass 15, count 0 2006.201.19:01:04.35#ibcon#about to read 3, iclass 15, count 0 2006.201.19:01:04.37#ibcon#read 3, iclass 15, count 0 2006.201.19:01:04.37#ibcon#about to read 4, iclass 15, count 0 2006.201.19:01:04.37#ibcon#read 4, iclass 15, count 0 2006.201.19:01:04.37#ibcon#about to read 5, iclass 15, count 0 2006.201.19:01:04.37#ibcon#read 5, iclass 15, count 0 2006.201.19:01:04.37#ibcon#about to read 6, iclass 15, count 0 2006.201.19:01:04.37#ibcon#read 6, iclass 15, count 0 2006.201.19:01:04.37#ibcon#end of sib2, iclass 15, count 0 2006.201.19:01:04.37#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:01:04.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:01:04.37#ibcon#[27=BW32\r\n] 2006.201.19:01:04.37#ibcon#*before write, iclass 15, count 0 2006.201.19:01:04.37#ibcon#enter sib2, iclass 15, count 0 2006.201.19:01:04.37#ibcon#flushed, iclass 15, count 0 2006.201.19:01:04.37#ibcon#about to write, iclass 15, count 0 2006.201.19:01:04.37#ibcon#wrote, iclass 15, count 0 2006.201.19:01:04.37#ibcon#about to read 3, iclass 15, count 0 2006.201.19:01:04.40#ibcon#read 3, iclass 15, count 0 2006.201.19:01:04.40#ibcon#about to read 4, iclass 15, count 0 2006.201.19:01:04.40#ibcon#read 4, iclass 15, count 0 2006.201.19:01:04.40#ibcon#about to read 5, iclass 15, count 0 2006.201.19:01:04.40#ibcon#read 5, iclass 15, count 0 2006.201.19:01:04.40#ibcon#about to read 6, iclass 15, count 0 2006.201.19:01:04.40#ibcon#read 6, iclass 15, count 0 2006.201.19:01:04.40#ibcon#end of sib2, iclass 15, count 0 2006.201.19:01:04.40#ibcon#*after write, iclass 15, count 0 2006.201.19:01:04.40#ibcon#*before return 0, iclass 15, count 0 2006.201.19:01:04.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:01:04.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:01:04.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:01:04.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:01:04.40$setupk4/ifdk4 2006.201.19:01:04.40$ifdk4/lo= 2006.201.19:01:04.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:01:04.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:01:04.40$ifdk4/patch= 2006.201.19:01:04.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:01:04.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:01:04.40$setupk4/!*+20s 2006.201.19:01:08.22#abcon#<5=/04 1.0 2.0 20.511001002.1\r\n> 2006.201.19:01:08.24#abcon#{5=INTERFACE CLEAR} 2006.201.19:01:08.30#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:01:18.39#abcon#<5=/04 1.0 2.0 20.511001002.1\r\n> 2006.201.19:01:18.41#abcon#{5=INTERFACE CLEAR} 2006.201.19:01:18.47#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:01:18.89$setupk4/"tpicd 2006.201.19:01:18.89$setupk4/echo=off 2006.201.19:01:18.89$setupk4/xlog=off 2006.201.19:01:18.89:!2006.201.19:07:31 2006.201.19:01:28.13#trakl#Source acquired 2006.201.19:01:30.13#flagr#flagr/antenna,acquired 2006.201.19:07:31.00:preob 2006.201.19:07:31.14/onsource/TRACKING 2006.201.19:07:31.14:!2006.201.19:07:41 2006.201.19:07:41.00:"tape 2006.201.19:07:41.00:"st=record 2006.201.19:07:41.00:data_valid=on 2006.201.19:07:41.00:midob 2006.201.19:07:42.14/onsource/TRACKING 2006.201.19:07:42.14/wx/20.51,1002.2,100 2006.201.19:07:42.22/cable/+6.4788E-03 2006.201.19:07:43.31/va/01,08,usb,yes,45,48 2006.201.19:07:43.31/va/02,07,usb,yes,49,50 2006.201.19:07:43.31/va/03,08,usb,yes,44,46 2006.201.19:07:43.31/va/04,07,usb,yes,50,53 2006.201.19:07:43.31/va/05,04,usb,yes,45,46 2006.201.19:07:43.31/va/06,05,usb,yes,45,45 2006.201.19:07:43.31/va/07,05,usb,yes,44,46 2006.201.19:07:43.31/va/08,04,usb,yes,44,52 2006.201.19:07:43.54/valo/01,524.99,yes,locked 2006.201.19:07:43.54/valo/02,534.99,yes,locked 2006.201.19:07:43.54/valo/03,564.99,yes,locked 2006.201.19:07:43.54/valo/04,624.99,yes,locked 2006.201.19:07:43.54/valo/05,734.99,yes,locked 2006.201.19:07:43.54/valo/06,814.99,yes,locked 2006.201.19:07:43.54/valo/07,864.99,yes,locked 2006.201.19:07:43.54/valo/08,884.99,yes,locked 2006.201.19:07:44.63/vb/01,04,usb,yes,30,30 2006.201.19:07:44.63/vb/02,05,usb,yes,28,30 2006.201.19:07:44.63/vb/03,04,usb,yes,30,33 2006.201.19:07:44.63/vb/04,05,usb,yes,30,29 2006.201.19:07:44.63/vb/05,04,usb,yes,26,29 2006.201.19:07:44.63/vb/06,04,usb,yes,31,27 2006.201.19:07:44.63/vb/07,04,usb,yes,31,31 2006.201.19:07:44.63/vb/08,04,usb,yes,28,32 2006.201.19:07:44.86/vblo/01,629.99,yes,locked 2006.201.19:07:44.86/vblo/02,634.99,yes,locked 2006.201.19:07:44.86/vblo/03,649.99,yes,locked 2006.201.19:07:44.86/vblo/04,679.99,yes,locked 2006.201.19:07:44.86/vblo/05,709.99,yes,locked 2006.201.19:07:44.86/vblo/06,719.99,yes,locked 2006.201.19:07:44.86/vblo/07,734.99,yes,locked 2006.201.19:07:44.86/vblo/08,744.99,yes,locked 2006.201.19:07:45.01/vabw/8 2006.201.19:07:45.16/vbbw/8 2006.201.19:07:45.25/xfe/off,on,15.5 2006.201.19:07:45.62/ifatt/23,28,28,28 2006.201.19:07:46.06/fmout-gps/S +4.49E-07 2006.201.19:07:46.13:!2006.201.19:12:01 2006.201.19:12:01.00:data_valid=off 2006.201.19:12:01.00:"et 2006.201.19:12:01.00:!+3s 2006.201.19:12:04.02:"tape 2006.201.19:12:04.02:postob 2006.201.19:12:04.21/cable/+6.4786E-03 2006.201.19:12:04.21/wx/20.52,1002.2,100 2006.201.19:12:04.29/fmout-gps/S +4.50E-07 2006.201.19:12:04.29:scan_name=201-1913,jd0607,60 2006.201.19:12:04.29:source=3c345,164258.81,394837.0,2000.0,ccw 2006.201.19:12:05.14#flagr#flagr/antenna,new-source 2006.201.19:12:05.14:checkk5 2006.201.19:12:05.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:12:05.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:12:06.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:12:06.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:12:07.02/chk_obsdata//k5ts1/T2011907??a.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.201.19:12:07.39/chk_obsdata//k5ts2/T2011907??b.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.201.19:12:07.76/chk_obsdata//k5ts3/T2011907??c.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.201.19:12:08.12/chk_obsdata//k5ts4/T2011907??d.dat file size is correct (nominal:1040MB, actual:1036MB). 2006.201.19:12:08.82/k5log//k5ts1_log_newline 2006.201.19:12:09.54/k5log//k5ts2_log_newline 2006.201.19:12:10.24/k5log//k5ts3_log_newline 2006.201.19:12:10.94/k5log//k5ts4_log_newline 2006.201.19:12:10.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:12:10.97:setupk4=1 2006.201.19:12:10.97$setupk4/echo=on 2006.201.19:12:10.97$setupk4/pcalon 2006.201.19:12:10.97$pcalon/"no phase cal control is implemented here 2006.201.19:12:10.97$setupk4/"tpicd=stop 2006.201.19:12:10.97$setupk4/"rec=synch_on 2006.201.19:12:10.97$setupk4/"rec_mode=128 2006.201.19:12:10.97$setupk4/!* 2006.201.19:12:10.97$setupk4/recpk4 2006.201.19:12:10.97$recpk4/recpatch= 2006.201.19:12:10.97$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:12:10.97$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:12:10.97$setupk4/vck44 2006.201.19:12:10.97$vck44/valo=1,524.99 2006.201.19:12:10.97#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.19:12:10.97#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.19:12:10.97#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:10.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:10.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:10.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:10.97#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:12:10.97#ibcon#first serial, iclass 32, count 0 2006.201.19:12:10.97#ibcon#enter sib2, iclass 32, count 0 2006.201.19:12:10.97#ibcon#flushed, iclass 32, count 0 2006.201.19:12:10.97#ibcon#about to write, iclass 32, count 0 2006.201.19:12:10.97#ibcon#wrote, iclass 32, count 0 2006.201.19:12:10.97#ibcon#about to read 3, iclass 32, count 0 2006.201.19:12:11.01#ibcon#read 3, iclass 32, count 0 2006.201.19:12:11.01#ibcon#about to read 4, iclass 32, count 0 2006.201.19:12:11.01#ibcon#read 4, iclass 32, count 0 2006.201.19:12:11.01#ibcon#about to read 5, iclass 32, count 0 2006.201.19:12:11.01#ibcon#read 5, iclass 32, count 0 2006.201.19:12:11.01#ibcon#about to read 6, iclass 32, count 0 2006.201.19:12:11.01#ibcon#read 6, iclass 32, count 0 2006.201.19:12:11.01#ibcon#end of sib2, iclass 32, count 0 2006.201.19:12:11.01#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:12:11.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:12:11.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:12:11.01#ibcon#*before write, iclass 32, count 0 2006.201.19:12:11.01#ibcon#enter sib2, iclass 32, count 0 2006.201.19:12:11.01#ibcon#flushed, iclass 32, count 0 2006.201.19:12:11.01#ibcon#about to write, iclass 32, count 0 2006.201.19:12:11.01#ibcon#wrote, iclass 32, count 0 2006.201.19:12:11.01#ibcon#about to read 3, iclass 32, count 0 2006.201.19:12:11.06#ibcon#read 3, iclass 32, count 0 2006.201.19:12:11.06#ibcon#about to read 4, iclass 32, count 0 2006.201.19:12:11.06#ibcon#read 4, iclass 32, count 0 2006.201.19:12:11.06#ibcon#about to read 5, iclass 32, count 0 2006.201.19:12:11.06#ibcon#read 5, iclass 32, count 0 2006.201.19:12:11.06#ibcon#about to read 6, iclass 32, count 0 2006.201.19:12:11.06#ibcon#read 6, iclass 32, count 0 2006.201.19:12:11.06#ibcon#end of sib2, iclass 32, count 0 2006.201.19:12:11.06#ibcon#*after write, iclass 32, count 0 2006.201.19:12:11.06#ibcon#*before return 0, iclass 32, count 0 2006.201.19:12:11.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:11.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:11.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:12:11.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:12:11.06$vck44/va=1,8 2006.201.19:12:11.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.19:12:11.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.19:12:11.06#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:11.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:11.06#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:11.06#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:11.06#ibcon#enter wrdev, iclass 34, count 2 2006.201.19:12:11.06#ibcon#first serial, iclass 34, count 2 2006.201.19:12:11.06#ibcon#enter sib2, iclass 34, count 2 2006.201.19:12:11.06#ibcon#flushed, iclass 34, count 2 2006.201.19:12:11.06#ibcon#about to write, iclass 34, count 2 2006.201.19:12:11.06#ibcon#wrote, iclass 34, count 2 2006.201.19:12:11.06#ibcon#about to read 3, iclass 34, count 2 2006.201.19:12:11.08#ibcon#read 3, iclass 34, count 2 2006.201.19:12:11.08#ibcon#about to read 4, iclass 34, count 2 2006.201.19:12:11.08#ibcon#read 4, iclass 34, count 2 2006.201.19:12:11.08#ibcon#about to read 5, iclass 34, count 2 2006.201.19:12:11.08#ibcon#read 5, iclass 34, count 2 2006.201.19:12:11.08#ibcon#about to read 6, iclass 34, count 2 2006.201.19:12:11.08#ibcon#read 6, iclass 34, count 2 2006.201.19:12:11.08#ibcon#end of sib2, iclass 34, count 2 2006.201.19:12:11.08#ibcon#*mode == 0, iclass 34, count 2 2006.201.19:12:11.08#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.19:12:11.08#ibcon#[25=AT01-08\r\n] 2006.201.19:12:11.08#ibcon#*before write, iclass 34, count 2 2006.201.19:12:11.08#ibcon#enter sib2, iclass 34, count 2 2006.201.19:12:11.08#ibcon#flushed, iclass 34, count 2 2006.201.19:12:11.08#ibcon#about to write, iclass 34, count 2 2006.201.19:12:11.08#ibcon#wrote, iclass 34, count 2 2006.201.19:12:11.08#ibcon#about to read 3, iclass 34, count 2 2006.201.19:12:11.11#ibcon#read 3, iclass 34, count 2 2006.201.19:12:11.11#ibcon#about to read 4, iclass 34, count 2 2006.201.19:12:11.11#ibcon#read 4, iclass 34, count 2 2006.201.19:12:11.11#ibcon#about to read 5, iclass 34, count 2 2006.201.19:12:11.11#ibcon#read 5, iclass 34, count 2 2006.201.19:12:11.11#ibcon#about to read 6, iclass 34, count 2 2006.201.19:12:11.11#ibcon#read 6, iclass 34, count 2 2006.201.19:12:11.11#ibcon#end of sib2, iclass 34, count 2 2006.201.19:12:11.11#ibcon#*after write, iclass 34, count 2 2006.201.19:12:11.11#ibcon#*before return 0, iclass 34, count 2 2006.201.19:12:11.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:11.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:11.11#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.19:12:11.11#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:11.11#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:11.23#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:11.23#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:11.23#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:12:11.23#ibcon#first serial, iclass 34, count 0 2006.201.19:12:11.23#ibcon#enter sib2, iclass 34, count 0 2006.201.19:12:11.23#ibcon#flushed, iclass 34, count 0 2006.201.19:12:11.23#ibcon#about to write, iclass 34, count 0 2006.201.19:12:11.23#ibcon#wrote, iclass 34, count 0 2006.201.19:12:11.23#ibcon#about to read 3, iclass 34, count 0 2006.201.19:12:11.25#ibcon#read 3, iclass 34, count 0 2006.201.19:12:11.25#ibcon#about to read 4, iclass 34, count 0 2006.201.19:12:11.25#ibcon#read 4, iclass 34, count 0 2006.201.19:12:11.25#ibcon#about to read 5, iclass 34, count 0 2006.201.19:12:11.25#ibcon#read 5, iclass 34, count 0 2006.201.19:12:11.25#ibcon#about to read 6, iclass 34, count 0 2006.201.19:12:11.25#ibcon#read 6, iclass 34, count 0 2006.201.19:12:11.25#ibcon#end of sib2, iclass 34, count 0 2006.201.19:12:11.25#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:12:11.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:12:11.25#ibcon#[25=USB\r\n] 2006.201.19:12:11.25#ibcon#*before write, iclass 34, count 0 2006.201.19:12:11.25#ibcon#enter sib2, iclass 34, count 0 2006.201.19:12:11.25#ibcon#flushed, iclass 34, count 0 2006.201.19:12:11.25#ibcon#about to write, iclass 34, count 0 2006.201.19:12:11.25#ibcon#wrote, iclass 34, count 0 2006.201.19:12:11.25#ibcon#about to read 3, iclass 34, count 0 2006.201.19:12:11.28#ibcon#read 3, iclass 34, count 0 2006.201.19:12:11.28#ibcon#about to read 4, iclass 34, count 0 2006.201.19:12:11.28#ibcon#read 4, iclass 34, count 0 2006.201.19:12:11.28#ibcon#about to read 5, iclass 34, count 0 2006.201.19:12:11.28#ibcon#read 5, iclass 34, count 0 2006.201.19:12:11.28#ibcon#about to read 6, iclass 34, count 0 2006.201.19:12:11.28#ibcon#read 6, iclass 34, count 0 2006.201.19:12:11.28#ibcon#end of sib2, iclass 34, count 0 2006.201.19:12:11.28#ibcon#*after write, iclass 34, count 0 2006.201.19:12:11.28#ibcon#*before return 0, iclass 34, count 0 2006.201.19:12:11.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:11.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:11.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:12:11.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:12:11.28$vck44/valo=2,534.99 2006.201.19:12:11.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.19:12:11.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.19:12:11.28#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:11.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:11.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:11.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:11.28#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:12:11.28#ibcon#first serial, iclass 36, count 0 2006.201.19:12:11.28#ibcon#enter sib2, iclass 36, count 0 2006.201.19:12:11.28#ibcon#flushed, iclass 36, count 0 2006.201.19:12:11.28#ibcon#about to write, iclass 36, count 0 2006.201.19:12:11.28#ibcon#wrote, iclass 36, count 0 2006.201.19:12:11.28#ibcon#about to read 3, iclass 36, count 0 2006.201.19:12:11.30#ibcon#read 3, iclass 36, count 0 2006.201.19:12:11.30#ibcon#about to read 4, iclass 36, count 0 2006.201.19:12:11.30#ibcon#read 4, iclass 36, count 0 2006.201.19:12:11.30#ibcon#about to read 5, iclass 36, count 0 2006.201.19:12:11.30#ibcon#read 5, iclass 36, count 0 2006.201.19:12:11.30#ibcon#about to read 6, iclass 36, count 0 2006.201.19:12:11.30#ibcon#read 6, iclass 36, count 0 2006.201.19:12:11.30#ibcon#end of sib2, iclass 36, count 0 2006.201.19:12:11.30#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:12:11.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:12:11.30#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:12:11.30#ibcon#*before write, iclass 36, count 0 2006.201.19:12:11.30#ibcon#enter sib2, iclass 36, count 0 2006.201.19:12:11.30#ibcon#flushed, iclass 36, count 0 2006.201.19:12:11.30#ibcon#about to write, iclass 36, count 0 2006.201.19:12:11.30#ibcon#wrote, iclass 36, count 0 2006.201.19:12:11.30#ibcon#about to read 3, iclass 36, count 0 2006.201.19:12:11.35#ibcon#read 3, iclass 36, count 0 2006.201.19:12:11.35#ibcon#about to read 4, iclass 36, count 0 2006.201.19:12:11.35#ibcon#read 4, iclass 36, count 0 2006.201.19:12:11.35#ibcon#about to read 5, iclass 36, count 0 2006.201.19:12:11.35#ibcon#read 5, iclass 36, count 0 2006.201.19:12:11.35#ibcon#about to read 6, iclass 36, count 0 2006.201.19:12:11.35#ibcon#read 6, iclass 36, count 0 2006.201.19:12:11.35#ibcon#end of sib2, iclass 36, count 0 2006.201.19:12:11.35#ibcon#*after write, iclass 36, count 0 2006.201.19:12:11.35#ibcon#*before return 0, iclass 36, count 0 2006.201.19:12:11.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:11.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:11.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:12:11.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:12:11.35$vck44/va=2,7 2006.201.19:12:11.35#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.19:12:11.35#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.19:12:11.35#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:11.35#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:11.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:11.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:11.40#ibcon#enter wrdev, iclass 38, count 2 2006.201.19:12:11.40#ibcon#first serial, iclass 38, count 2 2006.201.19:12:11.40#ibcon#enter sib2, iclass 38, count 2 2006.201.19:12:11.40#ibcon#flushed, iclass 38, count 2 2006.201.19:12:11.40#ibcon#about to write, iclass 38, count 2 2006.201.19:12:11.40#ibcon#wrote, iclass 38, count 2 2006.201.19:12:11.40#ibcon#about to read 3, iclass 38, count 2 2006.201.19:12:11.42#ibcon#read 3, iclass 38, count 2 2006.201.19:12:11.42#ibcon#about to read 4, iclass 38, count 2 2006.201.19:12:11.42#ibcon#read 4, iclass 38, count 2 2006.201.19:12:11.42#ibcon#about to read 5, iclass 38, count 2 2006.201.19:12:11.42#ibcon#read 5, iclass 38, count 2 2006.201.19:12:11.42#ibcon#about to read 6, iclass 38, count 2 2006.201.19:12:11.42#ibcon#read 6, iclass 38, count 2 2006.201.19:12:11.42#ibcon#end of sib2, iclass 38, count 2 2006.201.19:12:11.42#ibcon#*mode == 0, iclass 38, count 2 2006.201.19:12:11.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.19:12:11.42#ibcon#[25=AT02-07\r\n] 2006.201.19:12:11.42#ibcon#*before write, iclass 38, count 2 2006.201.19:12:11.42#ibcon#enter sib2, iclass 38, count 2 2006.201.19:12:11.42#ibcon#flushed, iclass 38, count 2 2006.201.19:12:11.42#ibcon#about to write, iclass 38, count 2 2006.201.19:12:11.42#ibcon#wrote, iclass 38, count 2 2006.201.19:12:11.42#ibcon#about to read 3, iclass 38, count 2 2006.201.19:12:11.45#ibcon#read 3, iclass 38, count 2 2006.201.19:12:11.45#ibcon#about to read 4, iclass 38, count 2 2006.201.19:12:11.45#ibcon#read 4, iclass 38, count 2 2006.201.19:12:11.45#ibcon#about to read 5, iclass 38, count 2 2006.201.19:12:11.45#ibcon#read 5, iclass 38, count 2 2006.201.19:12:11.45#ibcon#about to read 6, iclass 38, count 2 2006.201.19:12:11.45#ibcon#read 6, iclass 38, count 2 2006.201.19:12:11.45#ibcon#end of sib2, iclass 38, count 2 2006.201.19:12:11.45#ibcon#*after write, iclass 38, count 2 2006.201.19:12:11.45#ibcon#*before return 0, iclass 38, count 2 2006.201.19:12:11.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:11.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:11.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.19:12:11.45#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:11.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:11.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:11.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:11.57#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:12:11.57#ibcon#first serial, iclass 38, count 0 2006.201.19:12:11.57#ibcon#enter sib2, iclass 38, count 0 2006.201.19:12:11.57#ibcon#flushed, iclass 38, count 0 2006.201.19:12:11.57#ibcon#about to write, iclass 38, count 0 2006.201.19:12:11.57#ibcon#wrote, iclass 38, count 0 2006.201.19:12:11.57#ibcon#about to read 3, iclass 38, count 0 2006.201.19:12:11.59#ibcon#read 3, iclass 38, count 0 2006.201.19:12:11.59#ibcon#about to read 4, iclass 38, count 0 2006.201.19:12:11.59#ibcon#read 4, iclass 38, count 0 2006.201.19:12:11.59#ibcon#about to read 5, iclass 38, count 0 2006.201.19:12:11.59#ibcon#read 5, iclass 38, count 0 2006.201.19:12:11.59#ibcon#about to read 6, iclass 38, count 0 2006.201.19:12:11.59#ibcon#read 6, iclass 38, count 0 2006.201.19:12:11.59#ibcon#end of sib2, iclass 38, count 0 2006.201.19:12:11.59#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:12:11.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:12:11.59#ibcon#[25=USB\r\n] 2006.201.19:12:11.59#ibcon#*before write, iclass 38, count 0 2006.201.19:12:11.59#ibcon#enter sib2, iclass 38, count 0 2006.201.19:12:11.59#ibcon#flushed, iclass 38, count 0 2006.201.19:12:11.59#ibcon#about to write, iclass 38, count 0 2006.201.19:12:11.59#ibcon#wrote, iclass 38, count 0 2006.201.19:12:11.59#ibcon#about to read 3, iclass 38, count 0 2006.201.19:12:11.62#ibcon#read 3, iclass 38, count 0 2006.201.19:12:11.62#ibcon#about to read 4, iclass 38, count 0 2006.201.19:12:11.62#ibcon#read 4, iclass 38, count 0 2006.201.19:12:11.62#ibcon#about to read 5, iclass 38, count 0 2006.201.19:12:11.62#ibcon#read 5, iclass 38, count 0 2006.201.19:12:11.62#ibcon#about to read 6, iclass 38, count 0 2006.201.19:12:11.62#ibcon#read 6, iclass 38, count 0 2006.201.19:12:11.62#ibcon#end of sib2, iclass 38, count 0 2006.201.19:12:11.62#ibcon#*after write, iclass 38, count 0 2006.201.19:12:11.62#ibcon#*before return 0, iclass 38, count 0 2006.201.19:12:11.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:11.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:11.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:12:11.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:12:11.62$vck44/valo=3,564.99 2006.201.19:12:11.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.19:12:11.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.19:12:11.62#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:11.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:11.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:11.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:11.62#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:12:11.62#ibcon#first serial, iclass 40, count 0 2006.201.19:12:11.62#ibcon#enter sib2, iclass 40, count 0 2006.201.19:12:11.62#ibcon#flushed, iclass 40, count 0 2006.201.19:12:11.62#ibcon#about to write, iclass 40, count 0 2006.201.19:12:11.62#ibcon#wrote, iclass 40, count 0 2006.201.19:12:11.62#ibcon#about to read 3, iclass 40, count 0 2006.201.19:12:11.64#ibcon#read 3, iclass 40, count 0 2006.201.19:12:11.64#ibcon#about to read 4, iclass 40, count 0 2006.201.19:12:11.64#ibcon#read 4, iclass 40, count 0 2006.201.19:12:11.64#ibcon#about to read 5, iclass 40, count 0 2006.201.19:12:11.64#ibcon#read 5, iclass 40, count 0 2006.201.19:12:11.64#ibcon#about to read 6, iclass 40, count 0 2006.201.19:12:11.64#ibcon#read 6, iclass 40, count 0 2006.201.19:12:11.64#ibcon#end of sib2, iclass 40, count 0 2006.201.19:12:11.64#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:12:11.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:12:11.64#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:12:11.64#ibcon#*before write, iclass 40, count 0 2006.201.19:12:11.64#ibcon#enter sib2, iclass 40, count 0 2006.201.19:12:11.64#ibcon#flushed, iclass 40, count 0 2006.201.19:12:11.64#ibcon#about to write, iclass 40, count 0 2006.201.19:12:11.64#ibcon#wrote, iclass 40, count 0 2006.201.19:12:11.64#ibcon#about to read 3, iclass 40, count 0 2006.201.19:12:11.69#ibcon#read 3, iclass 40, count 0 2006.201.19:12:11.69#ibcon#about to read 4, iclass 40, count 0 2006.201.19:12:11.69#ibcon#read 4, iclass 40, count 0 2006.201.19:12:11.69#ibcon#about to read 5, iclass 40, count 0 2006.201.19:12:11.69#ibcon#read 5, iclass 40, count 0 2006.201.19:12:11.69#ibcon#about to read 6, iclass 40, count 0 2006.201.19:12:11.69#ibcon#read 6, iclass 40, count 0 2006.201.19:12:11.69#ibcon#end of sib2, iclass 40, count 0 2006.201.19:12:11.69#ibcon#*after write, iclass 40, count 0 2006.201.19:12:11.69#ibcon#*before return 0, iclass 40, count 0 2006.201.19:12:11.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:11.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:11.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:12:11.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:12:11.69$vck44/va=3,8 2006.201.19:12:11.69#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.19:12:11.69#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.19:12:11.69#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:11.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:11.74#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:11.74#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:11.74#ibcon#enter wrdev, iclass 4, count 2 2006.201.19:12:11.74#ibcon#first serial, iclass 4, count 2 2006.201.19:12:11.74#ibcon#enter sib2, iclass 4, count 2 2006.201.19:12:11.74#ibcon#flushed, iclass 4, count 2 2006.201.19:12:11.74#ibcon#about to write, iclass 4, count 2 2006.201.19:12:11.74#ibcon#wrote, iclass 4, count 2 2006.201.19:12:11.74#ibcon#about to read 3, iclass 4, count 2 2006.201.19:12:11.76#ibcon#read 3, iclass 4, count 2 2006.201.19:12:11.76#ibcon#about to read 4, iclass 4, count 2 2006.201.19:12:11.76#ibcon#read 4, iclass 4, count 2 2006.201.19:12:11.76#ibcon#about to read 5, iclass 4, count 2 2006.201.19:12:11.76#ibcon#read 5, iclass 4, count 2 2006.201.19:12:11.76#ibcon#about to read 6, iclass 4, count 2 2006.201.19:12:11.76#ibcon#read 6, iclass 4, count 2 2006.201.19:12:11.76#ibcon#end of sib2, iclass 4, count 2 2006.201.19:12:11.76#ibcon#*mode == 0, iclass 4, count 2 2006.201.19:12:11.76#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.19:12:11.76#ibcon#[25=AT03-08\r\n] 2006.201.19:12:11.76#ibcon#*before write, iclass 4, count 2 2006.201.19:12:11.76#ibcon#enter sib2, iclass 4, count 2 2006.201.19:12:11.76#ibcon#flushed, iclass 4, count 2 2006.201.19:12:11.76#ibcon#about to write, iclass 4, count 2 2006.201.19:12:11.76#ibcon#wrote, iclass 4, count 2 2006.201.19:12:11.76#ibcon#about to read 3, iclass 4, count 2 2006.201.19:12:11.79#ibcon#read 3, iclass 4, count 2 2006.201.19:12:11.79#ibcon#about to read 4, iclass 4, count 2 2006.201.19:12:11.79#ibcon#read 4, iclass 4, count 2 2006.201.19:12:11.79#ibcon#about to read 5, iclass 4, count 2 2006.201.19:12:11.79#ibcon#read 5, iclass 4, count 2 2006.201.19:12:11.79#ibcon#about to read 6, iclass 4, count 2 2006.201.19:12:11.79#ibcon#read 6, iclass 4, count 2 2006.201.19:12:11.79#ibcon#end of sib2, iclass 4, count 2 2006.201.19:12:11.79#ibcon#*after write, iclass 4, count 2 2006.201.19:12:11.79#ibcon#*before return 0, iclass 4, count 2 2006.201.19:12:11.79#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:11.79#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:11.79#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.19:12:11.79#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:11.79#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:11.91#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:11.91#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:11.91#ibcon#enter wrdev, iclass 4, count 0 2006.201.19:12:11.91#ibcon#first serial, iclass 4, count 0 2006.201.19:12:11.91#ibcon#enter sib2, iclass 4, count 0 2006.201.19:12:11.91#ibcon#flushed, iclass 4, count 0 2006.201.19:12:11.91#ibcon#about to write, iclass 4, count 0 2006.201.19:12:11.91#ibcon#wrote, iclass 4, count 0 2006.201.19:12:11.91#ibcon#about to read 3, iclass 4, count 0 2006.201.19:12:11.93#ibcon#read 3, iclass 4, count 0 2006.201.19:12:11.93#ibcon#about to read 4, iclass 4, count 0 2006.201.19:12:11.93#ibcon#read 4, iclass 4, count 0 2006.201.19:12:11.93#ibcon#about to read 5, iclass 4, count 0 2006.201.19:12:11.93#ibcon#read 5, iclass 4, count 0 2006.201.19:12:11.93#ibcon#about to read 6, iclass 4, count 0 2006.201.19:12:11.93#ibcon#read 6, iclass 4, count 0 2006.201.19:12:11.93#ibcon#end of sib2, iclass 4, count 0 2006.201.19:12:11.93#ibcon#*mode == 0, iclass 4, count 0 2006.201.19:12:11.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.19:12:11.93#ibcon#[25=USB\r\n] 2006.201.19:12:11.93#ibcon#*before write, iclass 4, count 0 2006.201.19:12:11.93#ibcon#enter sib2, iclass 4, count 0 2006.201.19:12:11.93#ibcon#flushed, iclass 4, count 0 2006.201.19:12:11.93#ibcon#about to write, iclass 4, count 0 2006.201.19:12:11.93#ibcon#wrote, iclass 4, count 0 2006.201.19:12:11.93#ibcon#about to read 3, iclass 4, count 0 2006.201.19:12:11.96#ibcon#read 3, iclass 4, count 0 2006.201.19:12:11.96#ibcon#about to read 4, iclass 4, count 0 2006.201.19:12:11.96#ibcon#read 4, iclass 4, count 0 2006.201.19:12:11.96#ibcon#about to read 5, iclass 4, count 0 2006.201.19:12:11.96#ibcon#read 5, iclass 4, count 0 2006.201.19:12:11.96#ibcon#about to read 6, iclass 4, count 0 2006.201.19:12:11.96#ibcon#read 6, iclass 4, count 0 2006.201.19:12:11.96#ibcon#end of sib2, iclass 4, count 0 2006.201.19:12:11.96#ibcon#*after write, iclass 4, count 0 2006.201.19:12:11.96#ibcon#*before return 0, iclass 4, count 0 2006.201.19:12:11.96#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:11.96#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:11.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.19:12:11.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.19:12:11.96$vck44/valo=4,624.99 2006.201.19:12:11.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.19:12:11.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.19:12:11.96#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:11.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:11.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:11.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:11.96#ibcon#enter wrdev, iclass 6, count 0 2006.201.19:12:11.96#ibcon#first serial, iclass 6, count 0 2006.201.19:12:11.96#ibcon#enter sib2, iclass 6, count 0 2006.201.19:12:11.96#ibcon#flushed, iclass 6, count 0 2006.201.19:12:11.96#ibcon#about to write, iclass 6, count 0 2006.201.19:12:11.96#ibcon#wrote, iclass 6, count 0 2006.201.19:12:11.96#ibcon#about to read 3, iclass 6, count 0 2006.201.19:12:11.98#ibcon#read 3, iclass 6, count 0 2006.201.19:12:11.98#ibcon#about to read 4, iclass 6, count 0 2006.201.19:12:11.98#ibcon#read 4, iclass 6, count 0 2006.201.19:12:11.98#ibcon#about to read 5, iclass 6, count 0 2006.201.19:12:11.98#ibcon#read 5, iclass 6, count 0 2006.201.19:12:11.98#ibcon#about to read 6, iclass 6, count 0 2006.201.19:12:11.98#ibcon#read 6, iclass 6, count 0 2006.201.19:12:11.98#ibcon#end of sib2, iclass 6, count 0 2006.201.19:12:11.98#ibcon#*mode == 0, iclass 6, count 0 2006.201.19:12:11.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.19:12:11.98#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:12:11.98#ibcon#*before write, iclass 6, count 0 2006.201.19:12:11.98#ibcon#enter sib2, iclass 6, count 0 2006.201.19:12:11.98#ibcon#flushed, iclass 6, count 0 2006.201.19:12:11.98#ibcon#about to write, iclass 6, count 0 2006.201.19:12:11.98#ibcon#wrote, iclass 6, count 0 2006.201.19:12:11.98#ibcon#about to read 3, iclass 6, count 0 2006.201.19:12:12.03#ibcon#read 3, iclass 6, count 0 2006.201.19:12:12.03#ibcon#about to read 4, iclass 6, count 0 2006.201.19:12:12.03#ibcon#read 4, iclass 6, count 0 2006.201.19:12:12.03#ibcon#about to read 5, iclass 6, count 0 2006.201.19:12:12.03#ibcon#read 5, iclass 6, count 0 2006.201.19:12:12.03#ibcon#about to read 6, iclass 6, count 0 2006.201.19:12:12.03#ibcon#read 6, iclass 6, count 0 2006.201.19:12:12.03#ibcon#end of sib2, iclass 6, count 0 2006.201.19:12:12.03#ibcon#*after write, iclass 6, count 0 2006.201.19:12:12.03#ibcon#*before return 0, iclass 6, count 0 2006.201.19:12:12.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:12.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:12.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.19:12:12.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.19:12:12.03$vck44/va=4,7 2006.201.19:12:12.03#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.19:12:12.03#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.19:12:12.03#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:12.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:12.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:12.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:12.08#ibcon#enter wrdev, iclass 10, count 2 2006.201.19:12:12.08#ibcon#first serial, iclass 10, count 2 2006.201.19:12:12.08#ibcon#enter sib2, iclass 10, count 2 2006.201.19:12:12.08#ibcon#flushed, iclass 10, count 2 2006.201.19:12:12.08#ibcon#about to write, iclass 10, count 2 2006.201.19:12:12.08#ibcon#wrote, iclass 10, count 2 2006.201.19:12:12.08#ibcon#about to read 3, iclass 10, count 2 2006.201.19:12:12.10#ibcon#read 3, iclass 10, count 2 2006.201.19:12:12.10#ibcon#about to read 4, iclass 10, count 2 2006.201.19:12:12.10#ibcon#read 4, iclass 10, count 2 2006.201.19:12:12.10#ibcon#about to read 5, iclass 10, count 2 2006.201.19:12:12.10#ibcon#read 5, iclass 10, count 2 2006.201.19:12:12.10#ibcon#about to read 6, iclass 10, count 2 2006.201.19:12:12.10#ibcon#read 6, iclass 10, count 2 2006.201.19:12:12.10#ibcon#end of sib2, iclass 10, count 2 2006.201.19:12:12.10#ibcon#*mode == 0, iclass 10, count 2 2006.201.19:12:12.10#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.19:12:12.10#ibcon#[25=AT04-07\r\n] 2006.201.19:12:12.10#ibcon#*before write, iclass 10, count 2 2006.201.19:12:12.10#ibcon#enter sib2, iclass 10, count 2 2006.201.19:12:12.10#ibcon#flushed, iclass 10, count 2 2006.201.19:12:12.10#ibcon#about to write, iclass 10, count 2 2006.201.19:12:12.10#ibcon#wrote, iclass 10, count 2 2006.201.19:12:12.10#ibcon#about to read 3, iclass 10, count 2 2006.201.19:12:12.13#ibcon#read 3, iclass 10, count 2 2006.201.19:12:12.13#ibcon#about to read 4, iclass 10, count 2 2006.201.19:12:12.13#ibcon#read 4, iclass 10, count 2 2006.201.19:12:12.13#ibcon#about to read 5, iclass 10, count 2 2006.201.19:12:12.13#ibcon#read 5, iclass 10, count 2 2006.201.19:12:12.13#ibcon#about to read 6, iclass 10, count 2 2006.201.19:12:12.13#ibcon#read 6, iclass 10, count 2 2006.201.19:12:12.13#ibcon#end of sib2, iclass 10, count 2 2006.201.19:12:12.13#ibcon#*after write, iclass 10, count 2 2006.201.19:12:12.13#ibcon#*before return 0, iclass 10, count 2 2006.201.19:12:12.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:12.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:12.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.19:12:12.13#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:12.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:12.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:12.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:12.25#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:12:12.25#ibcon#first serial, iclass 10, count 0 2006.201.19:12:12.25#ibcon#enter sib2, iclass 10, count 0 2006.201.19:12:12.25#ibcon#flushed, iclass 10, count 0 2006.201.19:12:12.25#ibcon#about to write, iclass 10, count 0 2006.201.19:12:12.25#ibcon#wrote, iclass 10, count 0 2006.201.19:12:12.25#ibcon#about to read 3, iclass 10, count 0 2006.201.19:12:12.27#ibcon#read 3, iclass 10, count 0 2006.201.19:12:12.27#ibcon#about to read 4, iclass 10, count 0 2006.201.19:12:12.27#ibcon#read 4, iclass 10, count 0 2006.201.19:12:12.27#ibcon#about to read 5, iclass 10, count 0 2006.201.19:12:12.27#ibcon#read 5, iclass 10, count 0 2006.201.19:12:12.27#ibcon#about to read 6, iclass 10, count 0 2006.201.19:12:12.27#ibcon#read 6, iclass 10, count 0 2006.201.19:12:12.27#ibcon#end of sib2, iclass 10, count 0 2006.201.19:12:12.27#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:12:12.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:12:12.27#ibcon#[25=USB\r\n] 2006.201.19:12:12.27#ibcon#*before write, iclass 10, count 0 2006.201.19:12:12.27#ibcon#enter sib2, iclass 10, count 0 2006.201.19:12:12.27#ibcon#flushed, iclass 10, count 0 2006.201.19:12:12.27#ibcon#about to write, iclass 10, count 0 2006.201.19:12:12.27#ibcon#wrote, iclass 10, count 0 2006.201.19:12:12.27#ibcon#about to read 3, iclass 10, count 0 2006.201.19:12:12.30#ibcon#read 3, iclass 10, count 0 2006.201.19:12:12.30#ibcon#about to read 4, iclass 10, count 0 2006.201.19:12:12.30#ibcon#read 4, iclass 10, count 0 2006.201.19:12:12.30#ibcon#about to read 5, iclass 10, count 0 2006.201.19:12:12.30#ibcon#read 5, iclass 10, count 0 2006.201.19:12:12.30#ibcon#about to read 6, iclass 10, count 0 2006.201.19:12:12.30#ibcon#read 6, iclass 10, count 0 2006.201.19:12:12.30#ibcon#end of sib2, iclass 10, count 0 2006.201.19:12:12.30#ibcon#*after write, iclass 10, count 0 2006.201.19:12:12.30#ibcon#*before return 0, iclass 10, count 0 2006.201.19:12:12.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:12.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:12.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:12:12.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:12:12.30$vck44/valo=5,734.99 2006.201.19:12:12.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.19:12:12.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.19:12:12.30#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:12.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:12.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:12.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:12.30#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:12:12.30#ibcon#first serial, iclass 12, count 0 2006.201.19:12:12.30#ibcon#enter sib2, iclass 12, count 0 2006.201.19:12:12.30#ibcon#flushed, iclass 12, count 0 2006.201.19:12:12.30#ibcon#about to write, iclass 12, count 0 2006.201.19:12:12.30#ibcon#wrote, iclass 12, count 0 2006.201.19:12:12.30#ibcon#about to read 3, iclass 12, count 0 2006.201.19:12:12.32#ibcon#read 3, iclass 12, count 0 2006.201.19:12:12.32#ibcon#about to read 4, iclass 12, count 0 2006.201.19:12:12.32#ibcon#read 4, iclass 12, count 0 2006.201.19:12:12.32#ibcon#about to read 5, iclass 12, count 0 2006.201.19:12:12.32#ibcon#read 5, iclass 12, count 0 2006.201.19:12:12.32#ibcon#about to read 6, iclass 12, count 0 2006.201.19:12:12.32#ibcon#read 6, iclass 12, count 0 2006.201.19:12:12.32#ibcon#end of sib2, iclass 12, count 0 2006.201.19:12:12.32#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:12:12.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:12:12.32#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:12:12.32#ibcon#*before write, iclass 12, count 0 2006.201.19:12:12.32#ibcon#enter sib2, iclass 12, count 0 2006.201.19:12:12.32#ibcon#flushed, iclass 12, count 0 2006.201.19:12:12.32#ibcon#about to write, iclass 12, count 0 2006.201.19:12:12.32#ibcon#wrote, iclass 12, count 0 2006.201.19:12:12.32#ibcon#about to read 3, iclass 12, count 0 2006.201.19:12:12.36#ibcon#read 3, iclass 12, count 0 2006.201.19:12:12.36#ibcon#about to read 4, iclass 12, count 0 2006.201.19:12:12.36#ibcon#read 4, iclass 12, count 0 2006.201.19:12:12.36#ibcon#about to read 5, iclass 12, count 0 2006.201.19:12:12.36#ibcon#read 5, iclass 12, count 0 2006.201.19:12:12.36#ibcon#about to read 6, iclass 12, count 0 2006.201.19:12:12.36#ibcon#read 6, iclass 12, count 0 2006.201.19:12:12.36#ibcon#end of sib2, iclass 12, count 0 2006.201.19:12:12.36#ibcon#*after write, iclass 12, count 0 2006.201.19:12:12.36#ibcon#*before return 0, iclass 12, count 0 2006.201.19:12:12.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:12.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:12.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:12:12.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:12:12.36$vck44/va=5,4 2006.201.19:12:12.36#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.19:12:12.36#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.19:12:12.36#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:12.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:12.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:12.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:12.42#ibcon#enter wrdev, iclass 14, count 2 2006.201.19:12:12.42#ibcon#first serial, iclass 14, count 2 2006.201.19:12:12.42#ibcon#enter sib2, iclass 14, count 2 2006.201.19:12:12.42#ibcon#flushed, iclass 14, count 2 2006.201.19:12:12.42#ibcon#about to write, iclass 14, count 2 2006.201.19:12:12.42#ibcon#wrote, iclass 14, count 2 2006.201.19:12:12.42#ibcon#about to read 3, iclass 14, count 2 2006.201.19:12:12.44#ibcon#read 3, iclass 14, count 2 2006.201.19:12:12.44#ibcon#about to read 4, iclass 14, count 2 2006.201.19:12:12.44#ibcon#read 4, iclass 14, count 2 2006.201.19:12:12.44#ibcon#about to read 5, iclass 14, count 2 2006.201.19:12:12.44#ibcon#read 5, iclass 14, count 2 2006.201.19:12:12.44#ibcon#about to read 6, iclass 14, count 2 2006.201.19:12:12.44#ibcon#read 6, iclass 14, count 2 2006.201.19:12:12.44#ibcon#end of sib2, iclass 14, count 2 2006.201.19:12:12.44#ibcon#*mode == 0, iclass 14, count 2 2006.201.19:12:12.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.19:12:12.44#ibcon#[25=AT05-04\r\n] 2006.201.19:12:12.44#ibcon#*before write, iclass 14, count 2 2006.201.19:12:12.44#ibcon#enter sib2, iclass 14, count 2 2006.201.19:12:12.44#ibcon#flushed, iclass 14, count 2 2006.201.19:12:12.44#ibcon#about to write, iclass 14, count 2 2006.201.19:12:12.44#ibcon#wrote, iclass 14, count 2 2006.201.19:12:12.44#ibcon#about to read 3, iclass 14, count 2 2006.201.19:12:12.47#ibcon#read 3, iclass 14, count 2 2006.201.19:12:12.47#ibcon#about to read 4, iclass 14, count 2 2006.201.19:12:12.47#ibcon#read 4, iclass 14, count 2 2006.201.19:12:12.47#ibcon#about to read 5, iclass 14, count 2 2006.201.19:12:12.47#ibcon#read 5, iclass 14, count 2 2006.201.19:12:12.47#ibcon#about to read 6, iclass 14, count 2 2006.201.19:12:12.47#ibcon#read 6, iclass 14, count 2 2006.201.19:12:12.47#ibcon#end of sib2, iclass 14, count 2 2006.201.19:12:12.47#ibcon#*after write, iclass 14, count 2 2006.201.19:12:12.47#ibcon#*before return 0, iclass 14, count 2 2006.201.19:12:12.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:12.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:12.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.19:12:12.47#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:12.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:12.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:12.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:12.59#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:12:12.59#ibcon#first serial, iclass 14, count 0 2006.201.19:12:12.59#ibcon#enter sib2, iclass 14, count 0 2006.201.19:12:12.59#ibcon#flushed, iclass 14, count 0 2006.201.19:12:12.59#ibcon#about to write, iclass 14, count 0 2006.201.19:12:12.59#ibcon#wrote, iclass 14, count 0 2006.201.19:12:12.59#ibcon#about to read 3, iclass 14, count 0 2006.201.19:12:12.61#ibcon#read 3, iclass 14, count 0 2006.201.19:12:12.61#ibcon#about to read 4, iclass 14, count 0 2006.201.19:12:12.61#ibcon#read 4, iclass 14, count 0 2006.201.19:12:12.61#ibcon#about to read 5, iclass 14, count 0 2006.201.19:12:12.61#ibcon#read 5, iclass 14, count 0 2006.201.19:12:12.61#ibcon#about to read 6, iclass 14, count 0 2006.201.19:12:12.61#ibcon#read 6, iclass 14, count 0 2006.201.19:12:12.61#ibcon#end of sib2, iclass 14, count 0 2006.201.19:12:12.61#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:12:12.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:12:12.61#ibcon#[25=USB\r\n] 2006.201.19:12:12.61#ibcon#*before write, iclass 14, count 0 2006.201.19:12:12.61#ibcon#enter sib2, iclass 14, count 0 2006.201.19:12:12.61#ibcon#flushed, iclass 14, count 0 2006.201.19:12:12.61#ibcon#about to write, iclass 14, count 0 2006.201.19:12:12.61#ibcon#wrote, iclass 14, count 0 2006.201.19:12:12.61#ibcon#about to read 3, iclass 14, count 0 2006.201.19:12:12.64#ibcon#read 3, iclass 14, count 0 2006.201.19:12:12.64#ibcon#about to read 4, iclass 14, count 0 2006.201.19:12:12.64#ibcon#read 4, iclass 14, count 0 2006.201.19:12:12.64#ibcon#about to read 5, iclass 14, count 0 2006.201.19:12:12.64#ibcon#read 5, iclass 14, count 0 2006.201.19:12:12.64#ibcon#about to read 6, iclass 14, count 0 2006.201.19:12:12.64#ibcon#read 6, iclass 14, count 0 2006.201.19:12:12.64#ibcon#end of sib2, iclass 14, count 0 2006.201.19:12:12.64#ibcon#*after write, iclass 14, count 0 2006.201.19:12:12.64#ibcon#*before return 0, iclass 14, count 0 2006.201.19:12:12.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:12.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:12.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:12:12.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:12:12.64$vck44/valo=6,814.99 2006.201.19:12:12.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.19:12:12.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.19:12:12.64#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:12.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:12.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:12.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:12.64#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:12:12.64#ibcon#first serial, iclass 16, count 0 2006.201.19:12:12.64#ibcon#enter sib2, iclass 16, count 0 2006.201.19:12:12.64#ibcon#flushed, iclass 16, count 0 2006.201.19:12:12.64#ibcon#about to write, iclass 16, count 0 2006.201.19:12:12.64#ibcon#wrote, iclass 16, count 0 2006.201.19:12:12.64#ibcon#about to read 3, iclass 16, count 0 2006.201.19:12:12.66#ibcon#read 3, iclass 16, count 0 2006.201.19:12:12.66#ibcon#about to read 4, iclass 16, count 0 2006.201.19:12:12.66#ibcon#read 4, iclass 16, count 0 2006.201.19:12:12.66#ibcon#about to read 5, iclass 16, count 0 2006.201.19:12:12.66#ibcon#read 5, iclass 16, count 0 2006.201.19:12:12.66#ibcon#about to read 6, iclass 16, count 0 2006.201.19:12:12.66#ibcon#read 6, iclass 16, count 0 2006.201.19:12:12.66#ibcon#end of sib2, iclass 16, count 0 2006.201.19:12:12.66#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:12:12.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:12:12.66#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:12:12.66#ibcon#*before write, iclass 16, count 0 2006.201.19:12:12.66#ibcon#enter sib2, iclass 16, count 0 2006.201.19:12:12.66#ibcon#flushed, iclass 16, count 0 2006.201.19:12:12.66#ibcon#about to write, iclass 16, count 0 2006.201.19:12:12.66#ibcon#wrote, iclass 16, count 0 2006.201.19:12:12.66#ibcon#about to read 3, iclass 16, count 0 2006.201.19:12:12.70#ibcon#read 3, iclass 16, count 0 2006.201.19:12:12.70#ibcon#about to read 4, iclass 16, count 0 2006.201.19:12:12.70#ibcon#read 4, iclass 16, count 0 2006.201.19:12:12.70#ibcon#about to read 5, iclass 16, count 0 2006.201.19:12:12.70#ibcon#read 5, iclass 16, count 0 2006.201.19:12:12.70#ibcon#about to read 6, iclass 16, count 0 2006.201.19:12:12.70#ibcon#read 6, iclass 16, count 0 2006.201.19:12:12.70#ibcon#end of sib2, iclass 16, count 0 2006.201.19:12:12.70#ibcon#*after write, iclass 16, count 0 2006.201.19:12:12.70#ibcon#*before return 0, iclass 16, count 0 2006.201.19:12:12.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:12.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:12.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:12:12.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:12:12.70$vck44/va=6,5 2006.201.19:12:12.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.19:12:12.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.19:12:12.70#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:12.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:12.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:12.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:12.76#ibcon#enter wrdev, iclass 18, count 2 2006.201.19:12:12.76#ibcon#first serial, iclass 18, count 2 2006.201.19:12:12.76#ibcon#enter sib2, iclass 18, count 2 2006.201.19:12:12.76#ibcon#flushed, iclass 18, count 2 2006.201.19:12:12.76#ibcon#about to write, iclass 18, count 2 2006.201.19:12:12.76#ibcon#wrote, iclass 18, count 2 2006.201.19:12:12.76#ibcon#about to read 3, iclass 18, count 2 2006.201.19:12:12.78#ibcon#read 3, iclass 18, count 2 2006.201.19:12:12.78#ibcon#about to read 4, iclass 18, count 2 2006.201.19:12:12.78#ibcon#read 4, iclass 18, count 2 2006.201.19:12:12.78#ibcon#about to read 5, iclass 18, count 2 2006.201.19:12:12.78#ibcon#read 5, iclass 18, count 2 2006.201.19:12:12.78#ibcon#about to read 6, iclass 18, count 2 2006.201.19:12:12.78#ibcon#read 6, iclass 18, count 2 2006.201.19:12:12.78#ibcon#end of sib2, iclass 18, count 2 2006.201.19:12:12.78#ibcon#*mode == 0, iclass 18, count 2 2006.201.19:12:12.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.19:12:12.78#ibcon#[25=AT06-05\r\n] 2006.201.19:12:12.78#ibcon#*before write, iclass 18, count 2 2006.201.19:12:12.78#ibcon#enter sib2, iclass 18, count 2 2006.201.19:12:12.78#ibcon#flushed, iclass 18, count 2 2006.201.19:12:12.78#ibcon#about to write, iclass 18, count 2 2006.201.19:12:12.78#ibcon#wrote, iclass 18, count 2 2006.201.19:12:12.78#ibcon#about to read 3, iclass 18, count 2 2006.201.19:12:12.81#ibcon#read 3, iclass 18, count 2 2006.201.19:12:12.81#ibcon#about to read 4, iclass 18, count 2 2006.201.19:12:12.81#ibcon#read 4, iclass 18, count 2 2006.201.19:12:12.81#ibcon#about to read 5, iclass 18, count 2 2006.201.19:12:12.81#ibcon#read 5, iclass 18, count 2 2006.201.19:12:12.81#ibcon#about to read 6, iclass 18, count 2 2006.201.19:12:12.81#ibcon#read 6, iclass 18, count 2 2006.201.19:12:12.81#ibcon#end of sib2, iclass 18, count 2 2006.201.19:12:12.81#ibcon#*after write, iclass 18, count 2 2006.201.19:12:12.81#ibcon#*before return 0, iclass 18, count 2 2006.201.19:12:12.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:12.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:12.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.19:12:12.81#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:12.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:12.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:12.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:12.93#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:12:12.93#ibcon#first serial, iclass 18, count 0 2006.201.19:12:12.93#ibcon#enter sib2, iclass 18, count 0 2006.201.19:12:12.93#ibcon#flushed, iclass 18, count 0 2006.201.19:12:12.93#ibcon#about to write, iclass 18, count 0 2006.201.19:12:12.93#ibcon#wrote, iclass 18, count 0 2006.201.19:12:12.93#ibcon#about to read 3, iclass 18, count 0 2006.201.19:12:12.95#ibcon#read 3, iclass 18, count 0 2006.201.19:12:12.95#ibcon#about to read 4, iclass 18, count 0 2006.201.19:12:12.95#ibcon#read 4, iclass 18, count 0 2006.201.19:12:12.95#ibcon#about to read 5, iclass 18, count 0 2006.201.19:12:12.95#ibcon#read 5, iclass 18, count 0 2006.201.19:12:12.95#ibcon#about to read 6, iclass 18, count 0 2006.201.19:12:12.95#ibcon#read 6, iclass 18, count 0 2006.201.19:12:12.95#ibcon#end of sib2, iclass 18, count 0 2006.201.19:12:12.95#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:12:12.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:12:12.95#ibcon#[25=USB\r\n] 2006.201.19:12:12.95#ibcon#*before write, iclass 18, count 0 2006.201.19:12:12.95#ibcon#enter sib2, iclass 18, count 0 2006.201.19:12:12.95#ibcon#flushed, iclass 18, count 0 2006.201.19:12:12.95#ibcon#about to write, iclass 18, count 0 2006.201.19:12:12.95#ibcon#wrote, iclass 18, count 0 2006.201.19:12:12.95#ibcon#about to read 3, iclass 18, count 0 2006.201.19:12:12.98#ibcon#read 3, iclass 18, count 0 2006.201.19:12:12.98#ibcon#about to read 4, iclass 18, count 0 2006.201.19:12:12.98#ibcon#read 4, iclass 18, count 0 2006.201.19:12:12.98#ibcon#about to read 5, iclass 18, count 0 2006.201.19:12:12.98#ibcon#read 5, iclass 18, count 0 2006.201.19:12:12.98#ibcon#about to read 6, iclass 18, count 0 2006.201.19:12:12.98#ibcon#read 6, iclass 18, count 0 2006.201.19:12:12.98#ibcon#end of sib2, iclass 18, count 0 2006.201.19:12:12.98#ibcon#*after write, iclass 18, count 0 2006.201.19:12:12.98#ibcon#*before return 0, iclass 18, count 0 2006.201.19:12:12.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:12.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:12.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:12:12.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:12:12.98$vck44/valo=7,864.99 2006.201.19:12:12.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.19:12:12.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.19:12:12.98#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:12.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:12.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:12.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:12.98#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:12:12.98#ibcon#first serial, iclass 20, count 0 2006.201.19:12:12.98#ibcon#enter sib2, iclass 20, count 0 2006.201.19:12:12.98#ibcon#flushed, iclass 20, count 0 2006.201.19:12:12.98#ibcon#about to write, iclass 20, count 0 2006.201.19:12:12.98#ibcon#wrote, iclass 20, count 0 2006.201.19:12:12.98#ibcon#about to read 3, iclass 20, count 0 2006.201.19:12:13.00#ibcon#read 3, iclass 20, count 0 2006.201.19:12:13.00#ibcon#about to read 4, iclass 20, count 0 2006.201.19:12:13.00#ibcon#read 4, iclass 20, count 0 2006.201.19:12:13.00#ibcon#about to read 5, iclass 20, count 0 2006.201.19:12:13.00#ibcon#read 5, iclass 20, count 0 2006.201.19:12:13.00#ibcon#about to read 6, iclass 20, count 0 2006.201.19:12:13.00#ibcon#read 6, iclass 20, count 0 2006.201.19:12:13.00#ibcon#end of sib2, iclass 20, count 0 2006.201.19:12:13.00#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:12:13.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:12:13.00#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:12:13.00#ibcon#*before write, iclass 20, count 0 2006.201.19:12:13.00#ibcon#enter sib2, iclass 20, count 0 2006.201.19:12:13.00#ibcon#flushed, iclass 20, count 0 2006.201.19:12:13.00#ibcon#about to write, iclass 20, count 0 2006.201.19:12:13.00#ibcon#wrote, iclass 20, count 0 2006.201.19:12:13.00#ibcon#about to read 3, iclass 20, count 0 2006.201.19:12:13.05#ibcon#read 3, iclass 20, count 0 2006.201.19:12:13.05#ibcon#about to read 4, iclass 20, count 0 2006.201.19:12:13.05#ibcon#read 4, iclass 20, count 0 2006.201.19:12:13.05#ibcon#about to read 5, iclass 20, count 0 2006.201.19:12:13.05#ibcon#read 5, iclass 20, count 0 2006.201.19:12:13.05#ibcon#about to read 6, iclass 20, count 0 2006.201.19:12:13.05#ibcon#read 6, iclass 20, count 0 2006.201.19:12:13.05#ibcon#end of sib2, iclass 20, count 0 2006.201.19:12:13.05#ibcon#*after write, iclass 20, count 0 2006.201.19:12:13.05#ibcon#*before return 0, iclass 20, count 0 2006.201.19:12:13.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:13.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:13.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:12:13.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:12:13.05$vck44/va=7,5 2006.201.19:12:13.05#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.19:12:13.05#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.19:12:13.05#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:13.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:13.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:13.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:13.10#ibcon#enter wrdev, iclass 22, count 2 2006.201.19:12:13.10#ibcon#first serial, iclass 22, count 2 2006.201.19:12:13.10#ibcon#enter sib2, iclass 22, count 2 2006.201.19:12:13.10#ibcon#flushed, iclass 22, count 2 2006.201.19:12:13.10#ibcon#about to write, iclass 22, count 2 2006.201.19:12:13.10#ibcon#wrote, iclass 22, count 2 2006.201.19:12:13.10#ibcon#about to read 3, iclass 22, count 2 2006.201.19:12:13.12#ibcon#read 3, iclass 22, count 2 2006.201.19:12:13.12#ibcon#about to read 4, iclass 22, count 2 2006.201.19:12:13.12#ibcon#read 4, iclass 22, count 2 2006.201.19:12:13.12#ibcon#about to read 5, iclass 22, count 2 2006.201.19:12:13.12#ibcon#read 5, iclass 22, count 2 2006.201.19:12:13.12#ibcon#about to read 6, iclass 22, count 2 2006.201.19:12:13.12#ibcon#read 6, iclass 22, count 2 2006.201.19:12:13.12#ibcon#end of sib2, iclass 22, count 2 2006.201.19:12:13.12#ibcon#*mode == 0, iclass 22, count 2 2006.201.19:12:13.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.19:12:13.12#ibcon#[25=AT07-05\r\n] 2006.201.19:12:13.12#ibcon#*before write, iclass 22, count 2 2006.201.19:12:13.12#ibcon#enter sib2, iclass 22, count 2 2006.201.19:12:13.12#ibcon#flushed, iclass 22, count 2 2006.201.19:12:13.12#ibcon#about to write, iclass 22, count 2 2006.201.19:12:13.12#ibcon#wrote, iclass 22, count 2 2006.201.19:12:13.12#ibcon#about to read 3, iclass 22, count 2 2006.201.19:12:13.15#ibcon#read 3, iclass 22, count 2 2006.201.19:12:13.15#ibcon#about to read 4, iclass 22, count 2 2006.201.19:12:13.15#ibcon#read 4, iclass 22, count 2 2006.201.19:12:13.15#ibcon#about to read 5, iclass 22, count 2 2006.201.19:12:13.15#ibcon#read 5, iclass 22, count 2 2006.201.19:12:13.15#ibcon#about to read 6, iclass 22, count 2 2006.201.19:12:13.15#ibcon#read 6, iclass 22, count 2 2006.201.19:12:13.15#ibcon#end of sib2, iclass 22, count 2 2006.201.19:12:13.15#ibcon#*after write, iclass 22, count 2 2006.201.19:12:13.15#ibcon#*before return 0, iclass 22, count 2 2006.201.19:12:13.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:13.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:13.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.19:12:13.15#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:13.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:13.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:13.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:13.27#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:12:13.27#ibcon#first serial, iclass 22, count 0 2006.201.19:12:13.27#ibcon#enter sib2, iclass 22, count 0 2006.201.19:12:13.27#ibcon#flushed, iclass 22, count 0 2006.201.19:12:13.27#ibcon#about to write, iclass 22, count 0 2006.201.19:12:13.27#ibcon#wrote, iclass 22, count 0 2006.201.19:12:13.27#ibcon#about to read 3, iclass 22, count 0 2006.201.19:12:13.29#ibcon#read 3, iclass 22, count 0 2006.201.19:12:13.29#ibcon#about to read 4, iclass 22, count 0 2006.201.19:12:13.29#ibcon#read 4, iclass 22, count 0 2006.201.19:12:13.29#ibcon#about to read 5, iclass 22, count 0 2006.201.19:12:13.29#ibcon#read 5, iclass 22, count 0 2006.201.19:12:13.29#ibcon#about to read 6, iclass 22, count 0 2006.201.19:12:13.29#ibcon#read 6, iclass 22, count 0 2006.201.19:12:13.29#ibcon#end of sib2, iclass 22, count 0 2006.201.19:12:13.29#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:12:13.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:12:13.29#ibcon#[25=USB\r\n] 2006.201.19:12:13.29#ibcon#*before write, iclass 22, count 0 2006.201.19:12:13.29#ibcon#enter sib2, iclass 22, count 0 2006.201.19:12:13.29#ibcon#flushed, iclass 22, count 0 2006.201.19:12:13.29#ibcon#about to write, iclass 22, count 0 2006.201.19:12:13.29#ibcon#wrote, iclass 22, count 0 2006.201.19:12:13.29#ibcon#about to read 3, iclass 22, count 0 2006.201.19:12:13.32#ibcon#read 3, iclass 22, count 0 2006.201.19:12:13.32#ibcon#about to read 4, iclass 22, count 0 2006.201.19:12:13.32#ibcon#read 4, iclass 22, count 0 2006.201.19:12:13.32#ibcon#about to read 5, iclass 22, count 0 2006.201.19:12:13.32#ibcon#read 5, iclass 22, count 0 2006.201.19:12:13.32#ibcon#about to read 6, iclass 22, count 0 2006.201.19:12:13.32#ibcon#read 6, iclass 22, count 0 2006.201.19:12:13.32#ibcon#end of sib2, iclass 22, count 0 2006.201.19:12:13.32#ibcon#*after write, iclass 22, count 0 2006.201.19:12:13.32#ibcon#*before return 0, iclass 22, count 0 2006.201.19:12:13.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:13.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:13.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:12:13.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:12:13.32$vck44/valo=8,884.99 2006.201.19:12:13.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.19:12:13.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.19:12:13.32#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:13.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:13.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:13.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:13.32#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:12:13.32#ibcon#first serial, iclass 24, count 0 2006.201.19:12:13.32#ibcon#enter sib2, iclass 24, count 0 2006.201.19:12:13.32#ibcon#flushed, iclass 24, count 0 2006.201.19:12:13.32#ibcon#about to write, iclass 24, count 0 2006.201.19:12:13.32#ibcon#wrote, iclass 24, count 0 2006.201.19:12:13.32#ibcon#about to read 3, iclass 24, count 0 2006.201.19:12:13.34#ibcon#read 3, iclass 24, count 0 2006.201.19:12:13.34#ibcon#about to read 4, iclass 24, count 0 2006.201.19:12:13.34#ibcon#read 4, iclass 24, count 0 2006.201.19:12:13.34#ibcon#about to read 5, iclass 24, count 0 2006.201.19:12:13.34#ibcon#read 5, iclass 24, count 0 2006.201.19:12:13.34#ibcon#about to read 6, iclass 24, count 0 2006.201.19:12:13.34#ibcon#read 6, iclass 24, count 0 2006.201.19:12:13.34#ibcon#end of sib2, iclass 24, count 0 2006.201.19:12:13.34#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:12:13.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:12:13.34#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:12:13.34#ibcon#*before write, iclass 24, count 0 2006.201.19:12:13.34#ibcon#enter sib2, iclass 24, count 0 2006.201.19:12:13.34#ibcon#flushed, iclass 24, count 0 2006.201.19:12:13.34#ibcon#about to write, iclass 24, count 0 2006.201.19:12:13.34#ibcon#wrote, iclass 24, count 0 2006.201.19:12:13.34#ibcon#about to read 3, iclass 24, count 0 2006.201.19:12:13.38#ibcon#read 3, iclass 24, count 0 2006.201.19:12:13.38#ibcon#about to read 4, iclass 24, count 0 2006.201.19:12:13.38#ibcon#read 4, iclass 24, count 0 2006.201.19:12:13.38#ibcon#about to read 5, iclass 24, count 0 2006.201.19:12:13.38#ibcon#read 5, iclass 24, count 0 2006.201.19:12:13.38#ibcon#about to read 6, iclass 24, count 0 2006.201.19:12:13.38#ibcon#read 6, iclass 24, count 0 2006.201.19:12:13.38#ibcon#end of sib2, iclass 24, count 0 2006.201.19:12:13.38#ibcon#*after write, iclass 24, count 0 2006.201.19:12:13.38#ibcon#*before return 0, iclass 24, count 0 2006.201.19:12:13.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:13.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:13.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:12:13.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:12:13.38$vck44/va=8,4 2006.201.19:12:13.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.19:12:13.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.19:12:13.38#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:13.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:12:13.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:12:13.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:12:13.44#ibcon#enter wrdev, iclass 26, count 2 2006.201.19:12:13.44#ibcon#first serial, iclass 26, count 2 2006.201.19:12:13.44#ibcon#enter sib2, iclass 26, count 2 2006.201.19:12:13.44#ibcon#flushed, iclass 26, count 2 2006.201.19:12:13.44#ibcon#about to write, iclass 26, count 2 2006.201.19:12:13.44#ibcon#wrote, iclass 26, count 2 2006.201.19:12:13.44#ibcon#about to read 3, iclass 26, count 2 2006.201.19:12:13.46#ibcon#read 3, iclass 26, count 2 2006.201.19:12:13.46#ibcon#about to read 4, iclass 26, count 2 2006.201.19:12:13.46#ibcon#read 4, iclass 26, count 2 2006.201.19:12:13.46#ibcon#about to read 5, iclass 26, count 2 2006.201.19:12:13.46#ibcon#read 5, iclass 26, count 2 2006.201.19:12:13.46#ibcon#about to read 6, iclass 26, count 2 2006.201.19:12:13.46#ibcon#read 6, iclass 26, count 2 2006.201.19:12:13.46#ibcon#end of sib2, iclass 26, count 2 2006.201.19:12:13.46#ibcon#*mode == 0, iclass 26, count 2 2006.201.19:12:13.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.19:12:13.46#ibcon#[25=AT08-04\r\n] 2006.201.19:12:13.46#ibcon#*before write, iclass 26, count 2 2006.201.19:12:13.46#ibcon#enter sib2, iclass 26, count 2 2006.201.19:12:13.46#ibcon#flushed, iclass 26, count 2 2006.201.19:12:13.46#ibcon#about to write, iclass 26, count 2 2006.201.19:12:13.46#ibcon#wrote, iclass 26, count 2 2006.201.19:12:13.46#ibcon#about to read 3, iclass 26, count 2 2006.201.19:12:13.49#ibcon#read 3, iclass 26, count 2 2006.201.19:12:13.49#ibcon#about to read 4, iclass 26, count 2 2006.201.19:12:13.49#ibcon#read 4, iclass 26, count 2 2006.201.19:12:13.49#ibcon#about to read 5, iclass 26, count 2 2006.201.19:12:13.49#ibcon#read 5, iclass 26, count 2 2006.201.19:12:13.49#ibcon#about to read 6, iclass 26, count 2 2006.201.19:12:13.49#ibcon#read 6, iclass 26, count 2 2006.201.19:12:13.49#ibcon#end of sib2, iclass 26, count 2 2006.201.19:12:13.49#ibcon#*after write, iclass 26, count 2 2006.201.19:12:13.49#ibcon#*before return 0, iclass 26, count 2 2006.201.19:12:13.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:12:13.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:12:13.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.19:12:13.49#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:13.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:12:13.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:12:13.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:12:13.61#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:12:13.61#ibcon#first serial, iclass 26, count 0 2006.201.19:12:13.61#ibcon#enter sib2, iclass 26, count 0 2006.201.19:12:13.61#ibcon#flushed, iclass 26, count 0 2006.201.19:12:13.61#ibcon#about to write, iclass 26, count 0 2006.201.19:12:13.61#ibcon#wrote, iclass 26, count 0 2006.201.19:12:13.61#ibcon#about to read 3, iclass 26, count 0 2006.201.19:12:13.63#ibcon#read 3, iclass 26, count 0 2006.201.19:12:13.63#ibcon#about to read 4, iclass 26, count 0 2006.201.19:12:13.63#ibcon#read 4, iclass 26, count 0 2006.201.19:12:13.63#ibcon#about to read 5, iclass 26, count 0 2006.201.19:12:13.63#ibcon#read 5, iclass 26, count 0 2006.201.19:12:13.63#ibcon#about to read 6, iclass 26, count 0 2006.201.19:12:13.63#ibcon#read 6, iclass 26, count 0 2006.201.19:12:13.63#ibcon#end of sib2, iclass 26, count 0 2006.201.19:12:13.63#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:12:13.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:12:13.63#ibcon#[25=USB\r\n] 2006.201.19:12:13.63#ibcon#*before write, iclass 26, count 0 2006.201.19:12:13.63#ibcon#enter sib2, iclass 26, count 0 2006.201.19:12:13.63#ibcon#flushed, iclass 26, count 0 2006.201.19:12:13.63#ibcon#about to write, iclass 26, count 0 2006.201.19:12:13.63#ibcon#wrote, iclass 26, count 0 2006.201.19:12:13.63#ibcon#about to read 3, iclass 26, count 0 2006.201.19:12:13.66#ibcon#read 3, iclass 26, count 0 2006.201.19:12:13.66#ibcon#about to read 4, iclass 26, count 0 2006.201.19:12:13.66#ibcon#read 4, iclass 26, count 0 2006.201.19:12:13.66#ibcon#about to read 5, iclass 26, count 0 2006.201.19:12:13.66#ibcon#read 5, iclass 26, count 0 2006.201.19:12:13.66#ibcon#about to read 6, iclass 26, count 0 2006.201.19:12:13.66#ibcon#read 6, iclass 26, count 0 2006.201.19:12:13.66#ibcon#end of sib2, iclass 26, count 0 2006.201.19:12:13.66#ibcon#*after write, iclass 26, count 0 2006.201.19:12:13.66#ibcon#*before return 0, iclass 26, count 0 2006.201.19:12:13.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:12:13.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:12:13.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:12:13.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:12:13.66$vck44/vblo=1,629.99 2006.201.19:12:13.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.19:12:13.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.19:12:13.66#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:13.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:12:13.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:12:13.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:12:13.66#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:12:13.66#ibcon#first serial, iclass 28, count 0 2006.201.19:12:13.66#ibcon#enter sib2, iclass 28, count 0 2006.201.19:12:13.66#ibcon#flushed, iclass 28, count 0 2006.201.19:12:13.66#ibcon#about to write, iclass 28, count 0 2006.201.19:12:13.66#ibcon#wrote, iclass 28, count 0 2006.201.19:12:13.66#ibcon#about to read 3, iclass 28, count 0 2006.201.19:12:13.68#ibcon#read 3, iclass 28, count 0 2006.201.19:12:13.68#ibcon#about to read 4, iclass 28, count 0 2006.201.19:12:13.68#ibcon#read 4, iclass 28, count 0 2006.201.19:12:13.68#ibcon#about to read 5, iclass 28, count 0 2006.201.19:12:13.68#ibcon#read 5, iclass 28, count 0 2006.201.19:12:13.68#ibcon#about to read 6, iclass 28, count 0 2006.201.19:12:13.68#ibcon#read 6, iclass 28, count 0 2006.201.19:12:13.68#ibcon#end of sib2, iclass 28, count 0 2006.201.19:12:13.68#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:12:13.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:12:13.68#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:12:13.68#ibcon#*before write, iclass 28, count 0 2006.201.19:12:13.68#ibcon#enter sib2, iclass 28, count 0 2006.201.19:12:13.68#ibcon#flushed, iclass 28, count 0 2006.201.19:12:13.68#ibcon#about to write, iclass 28, count 0 2006.201.19:12:13.68#ibcon#wrote, iclass 28, count 0 2006.201.19:12:13.68#ibcon#about to read 3, iclass 28, count 0 2006.201.19:12:13.73#ibcon#read 3, iclass 28, count 0 2006.201.19:12:13.73#ibcon#about to read 4, iclass 28, count 0 2006.201.19:12:13.73#ibcon#read 4, iclass 28, count 0 2006.201.19:12:13.73#ibcon#about to read 5, iclass 28, count 0 2006.201.19:12:13.73#ibcon#read 5, iclass 28, count 0 2006.201.19:12:13.73#ibcon#about to read 6, iclass 28, count 0 2006.201.19:12:13.73#ibcon#read 6, iclass 28, count 0 2006.201.19:12:13.73#ibcon#end of sib2, iclass 28, count 0 2006.201.19:12:13.73#ibcon#*after write, iclass 28, count 0 2006.201.19:12:13.73#ibcon#*before return 0, iclass 28, count 0 2006.201.19:12:13.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:12:13.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:12:13.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:12:13.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:12:13.73$vck44/vb=1,4 2006.201.19:12:13.73#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.19:12:13.73#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.19:12:13.73#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:13.73#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:12:13.73#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:12:13.73#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:12:13.73#ibcon#enter wrdev, iclass 30, count 2 2006.201.19:12:13.73#ibcon#first serial, iclass 30, count 2 2006.201.19:12:13.73#ibcon#enter sib2, iclass 30, count 2 2006.201.19:12:13.73#ibcon#flushed, iclass 30, count 2 2006.201.19:12:13.73#ibcon#about to write, iclass 30, count 2 2006.201.19:12:13.73#ibcon#wrote, iclass 30, count 2 2006.201.19:12:13.73#ibcon#about to read 3, iclass 30, count 2 2006.201.19:12:13.75#ibcon#read 3, iclass 30, count 2 2006.201.19:12:13.75#ibcon#about to read 4, iclass 30, count 2 2006.201.19:12:13.75#ibcon#read 4, iclass 30, count 2 2006.201.19:12:13.75#ibcon#about to read 5, iclass 30, count 2 2006.201.19:12:13.75#ibcon#read 5, iclass 30, count 2 2006.201.19:12:13.75#ibcon#about to read 6, iclass 30, count 2 2006.201.19:12:13.75#ibcon#read 6, iclass 30, count 2 2006.201.19:12:13.75#ibcon#end of sib2, iclass 30, count 2 2006.201.19:12:13.75#ibcon#*mode == 0, iclass 30, count 2 2006.201.19:12:13.75#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.19:12:13.75#ibcon#[27=AT01-04\r\n] 2006.201.19:12:13.75#ibcon#*before write, iclass 30, count 2 2006.201.19:12:13.75#ibcon#enter sib2, iclass 30, count 2 2006.201.19:12:13.75#ibcon#flushed, iclass 30, count 2 2006.201.19:12:13.75#ibcon#about to write, iclass 30, count 2 2006.201.19:12:13.75#ibcon#wrote, iclass 30, count 2 2006.201.19:12:13.75#ibcon#about to read 3, iclass 30, count 2 2006.201.19:12:13.78#ibcon#read 3, iclass 30, count 2 2006.201.19:12:13.78#ibcon#about to read 4, iclass 30, count 2 2006.201.19:12:13.78#ibcon#read 4, iclass 30, count 2 2006.201.19:12:13.78#ibcon#about to read 5, iclass 30, count 2 2006.201.19:12:13.78#ibcon#read 5, iclass 30, count 2 2006.201.19:12:13.78#ibcon#about to read 6, iclass 30, count 2 2006.201.19:12:13.78#ibcon#read 6, iclass 30, count 2 2006.201.19:12:13.78#ibcon#end of sib2, iclass 30, count 2 2006.201.19:12:13.78#ibcon#*after write, iclass 30, count 2 2006.201.19:12:13.78#ibcon#*before return 0, iclass 30, count 2 2006.201.19:12:13.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:12:13.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:12:13.78#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.19:12:13.78#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:13.78#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:12:13.90#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:12:13.90#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:12:13.90#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:12:13.90#ibcon#first serial, iclass 30, count 0 2006.201.19:12:13.90#ibcon#enter sib2, iclass 30, count 0 2006.201.19:12:13.90#ibcon#flushed, iclass 30, count 0 2006.201.19:12:13.90#ibcon#about to write, iclass 30, count 0 2006.201.19:12:13.90#ibcon#wrote, iclass 30, count 0 2006.201.19:12:13.90#ibcon#about to read 3, iclass 30, count 0 2006.201.19:12:13.92#ibcon#read 3, iclass 30, count 0 2006.201.19:12:13.92#ibcon#about to read 4, iclass 30, count 0 2006.201.19:12:13.92#ibcon#read 4, iclass 30, count 0 2006.201.19:12:13.92#ibcon#about to read 5, iclass 30, count 0 2006.201.19:12:13.92#ibcon#read 5, iclass 30, count 0 2006.201.19:12:13.92#ibcon#about to read 6, iclass 30, count 0 2006.201.19:12:13.92#ibcon#read 6, iclass 30, count 0 2006.201.19:12:13.92#ibcon#end of sib2, iclass 30, count 0 2006.201.19:12:13.92#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:12:13.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:12:13.92#ibcon#[27=USB\r\n] 2006.201.19:12:13.92#ibcon#*before write, iclass 30, count 0 2006.201.19:12:13.92#ibcon#enter sib2, iclass 30, count 0 2006.201.19:12:13.92#ibcon#flushed, iclass 30, count 0 2006.201.19:12:13.92#ibcon#about to write, iclass 30, count 0 2006.201.19:12:13.92#ibcon#wrote, iclass 30, count 0 2006.201.19:12:13.92#ibcon#about to read 3, iclass 30, count 0 2006.201.19:12:13.95#ibcon#read 3, iclass 30, count 0 2006.201.19:12:13.95#ibcon#about to read 4, iclass 30, count 0 2006.201.19:12:13.95#ibcon#read 4, iclass 30, count 0 2006.201.19:12:13.95#ibcon#about to read 5, iclass 30, count 0 2006.201.19:12:13.95#ibcon#read 5, iclass 30, count 0 2006.201.19:12:13.95#ibcon#about to read 6, iclass 30, count 0 2006.201.19:12:13.95#ibcon#read 6, iclass 30, count 0 2006.201.19:12:13.95#ibcon#end of sib2, iclass 30, count 0 2006.201.19:12:13.95#ibcon#*after write, iclass 30, count 0 2006.201.19:12:13.95#ibcon#*before return 0, iclass 30, count 0 2006.201.19:12:13.95#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:12:13.95#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:12:13.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:12:13.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:12:13.95$vck44/vblo=2,634.99 2006.201.19:12:13.95#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.19:12:13.95#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.19:12:13.95#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:13.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:13.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:13.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:13.95#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:12:13.95#ibcon#first serial, iclass 32, count 0 2006.201.19:12:13.95#ibcon#enter sib2, iclass 32, count 0 2006.201.19:12:13.95#ibcon#flushed, iclass 32, count 0 2006.201.19:12:13.95#ibcon#about to write, iclass 32, count 0 2006.201.19:12:13.95#ibcon#wrote, iclass 32, count 0 2006.201.19:12:13.95#ibcon#about to read 3, iclass 32, count 0 2006.201.19:12:13.97#ibcon#read 3, iclass 32, count 0 2006.201.19:12:13.97#ibcon#about to read 4, iclass 32, count 0 2006.201.19:12:13.97#ibcon#read 4, iclass 32, count 0 2006.201.19:12:13.97#ibcon#about to read 5, iclass 32, count 0 2006.201.19:12:13.97#ibcon#read 5, iclass 32, count 0 2006.201.19:12:13.97#ibcon#about to read 6, iclass 32, count 0 2006.201.19:12:13.97#ibcon#read 6, iclass 32, count 0 2006.201.19:12:13.97#ibcon#end of sib2, iclass 32, count 0 2006.201.19:12:13.97#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:12:13.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:12:13.97#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:12:13.97#ibcon#*before write, iclass 32, count 0 2006.201.19:12:13.97#ibcon#enter sib2, iclass 32, count 0 2006.201.19:12:13.97#ibcon#flushed, iclass 32, count 0 2006.201.19:12:13.97#ibcon#about to write, iclass 32, count 0 2006.201.19:12:13.97#ibcon#wrote, iclass 32, count 0 2006.201.19:12:13.97#ibcon#about to read 3, iclass 32, count 0 2006.201.19:12:14.01#ibcon#read 3, iclass 32, count 0 2006.201.19:12:14.01#ibcon#about to read 4, iclass 32, count 0 2006.201.19:12:14.01#ibcon#read 4, iclass 32, count 0 2006.201.19:12:14.01#ibcon#about to read 5, iclass 32, count 0 2006.201.19:12:14.01#ibcon#read 5, iclass 32, count 0 2006.201.19:12:14.01#ibcon#about to read 6, iclass 32, count 0 2006.201.19:12:14.01#ibcon#read 6, iclass 32, count 0 2006.201.19:12:14.01#ibcon#end of sib2, iclass 32, count 0 2006.201.19:12:14.01#ibcon#*after write, iclass 32, count 0 2006.201.19:12:14.01#ibcon#*before return 0, iclass 32, count 0 2006.201.19:12:14.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:14.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:12:14.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:12:14.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:12:14.01$vck44/vb=2,5 2006.201.19:12:14.01#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.19:12:14.01#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.19:12:14.01#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:14.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:14.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:14.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:14.07#ibcon#enter wrdev, iclass 34, count 2 2006.201.19:12:14.07#ibcon#first serial, iclass 34, count 2 2006.201.19:12:14.07#ibcon#enter sib2, iclass 34, count 2 2006.201.19:12:14.07#ibcon#flushed, iclass 34, count 2 2006.201.19:12:14.07#ibcon#about to write, iclass 34, count 2 2006.201.19:12:14.07#ibcon#wrote, iclass 34, count 2 2006.201.19:12:14.07#ibcon#about to read 3, iclass 34, count 2 2006.201.19:12:14.09#ibcon#read 3, iclass 34, count 2 2006.201.19:12:14.09#ibcon#about to read 4, iclass 34, count 2 2006.201.19:12:14.09#ibcon#read 4, iclass 34, count 2 2006.201.19:12:14.09#ibcon#about to read 5, iclass 34, count 2 2006.201.19:12:14.09#ibcon#read 5, iclass 34, count 2 2006.201.19:12:14.09#ibcon#about to read 6, iclass 34, count 2 2006.201.19:12:14.09#ibcon#read 6, iclass 34, count 2 2006.201.19:12:14.09#ibcon#end of sib2, iclass 34, count 2 2006.201.19:12:14.09#ibcon#*mode == 0, iclass 34, count 2 2006.201.19:12:14.09#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.19:12:14.09#ibcon#[27=AT02-05\r\n] 2006.201.19:12:14.09#ibcon#*before write, iclass 34, count 2 2006.201.19:12:14.09#ibcon#enter sib2, iclass 34, count 2 2006.201.19:12:14.09#ibcon#flushed, iclass 34, count 2 2006.201.19:12:14.09#ibcon#about to write, iclass 34, count 2 2006.201.19:12:14.09#ibcon#wrote, iclass 34, count 2 2006.201.19:12:14.09#ibcon#about to read 3, iclass 34, count 2 2006.201.19:12:14.12#ibcon#read 3, iclass 34, count 2 2006.201.19:12:14.12#ibcon#about to read 4, iclass 34, count 2 2006.201.19:12:14.12#ibcon#read 4, iclass 34, count 2 2006.201.19:12:14.12#ibcon#about to read 5, iclass 34, count 2 2006.201.19:12:14.12#ibcon#read 5, iclass 34, count 2 2006.201.19:12:14.12#ibcon#about to read 6, iclass 34, count 2 2006.201.19:12:14.12#ibcon#read 6, iclass 34, count 2 2006.201.19:12:14.12#ibcon#end of sib2, iclass 34, count 2 2006.201.19:12:14.12#ibcon#*after write, iclass 34, count 2 2006.201.19:12:14.12#ibcon#*before return 0, iclass 34, count 2 2006.201.19:12:14.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:14.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:12:14.12#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.19:12:14.12#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:14.12#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:14.24#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:14.24#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:14.24#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:12:14.24#ibcon#first serial, iclass 34, count 0 2006.201.19:12:14.24#ibcon#enter sib2, iclass 34, count 0 2006.201.19:12:14.24#ibcon#flushed, iclass 34, count 0 2006.201.19:12:14.24#ibcon#about to write, iclass 34, count 0 2006.201.19:12:14.24#ibcon#wrote, iclass 34, count 0 2006.201.19:12:14.24#ibcon#about to read 3, iclass 34, count 0 2006.201.19:12:14.26#ibcon#read 3, iclass 34, count 0 2006.201.19:12:14.26#ibcon#about to read 4, iclass 34, count 0 2006.201.19:12:14.26#ibcon#read 4, iclass 34, count 0 2006.201.19:12:14.26#ibcon#about to read 5, iclass 34, count 0 2006.201.19:12:14.26#ibcon#read 5, iclass 34, count 0 2006.201.19:12:14.26#ibcon#about to read 6, iclass 34, count 0 2006.201.19:12:14.26#ibcon#read 6, iclass 34, count 0 2006.201.19:12:14.26#ibcon#end of sib2, iclass 34, count 0 2006.201.19:12:14.26#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:12:14.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:12:14.26#ibcon#[27=USB\r\n] 2006.201.19:12:14.26#ibcon#*before write, iclass 34, count 0 2006.201.19:12:14.26#ibcon#enter sib2, iclass 34, count 0 2006.201.19:12:14.26#ibcon#flushed, iclass 34, count 0 2006.201.19:12:14.26#ibcon#about to write, iclass 34, count 0 2006.201.19:12:14.26#ibcon#wrote, iclass 34, count 0 2006.201.19:12:14.26#ibcon#about to read 3, iclass 34, count 0 2006.201.19:12:14.29#ibcon#read 3, iclass 34, count 0 2006.201.19:12:14.29#ibcon#about to read 4, iclass 34, count 0 2006.201.19:12:14.29#ibcon#read 4, iclass 34, count 0 2006.201.19:12:14.29#ibcon#about to read 5, iclass 34, count 0 2006.201.19:12:14.29#ibcon#read 5, iclass 34, count 0 2006.201.19:12:14.29#ibcon#about to read 6, iclass 34, count 0 2006.201.19:12:14.29#ibcon#read 6, iclass 34, count 0 2006.201.19:12:14.29#ibcon#end of sib2, iclass 34, count 0 2006.201.19:12:14.29#ibcon#*after write, iclass 34, count 0 2006.201.19:12:14.29#ibcon#*before return 0, iclass 34, count 0 2006.201.19:12:14.29#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:14.29#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:12:14.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:12:14.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:12:14.29$vck44/vblo=3,649.99 2006.201.19:12:14.29#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.19:12:14.29#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.19:12:14.29#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:14.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:14.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:14.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:14.29#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:12:14.29#ibcon#first serial, iclass 36, count 0 2006.201.19:12:14.29#ibcon#enter sib2, iclass 36, count 0 2006.201.19:12:14.29#ibcon#flushed, iclass 36, count 0 2006.201.19:12:14.29#ibcon#about to write, iclass 36, count 0 2006.201.19:12:14.29#ibcon#wrote, iclass 36, count 0 2006.201.19:12:14.29#ibcon#about to read 3, iclass 36, count 0 2006.201.19:12:14.31#ibcon#read 3, iclass 36, count 0 2006.201.19:12:14.31#ibcon#about to read 4, iclass 36, count 0 2006.201.19:12:14.31#ibcon#read 4, iclass 36, count 0 2006.201.19:12:14.31#ibcon#about to read 5, iclass 36, count 0 2006.201.19:12:14.31#ibcon#read 5, iclass 36, count 0 2006.201.19:12:14.31#ibcon#about to read 6, iclass 36, count 0 2006.201.19:12:14.31#ibcon#read 6, iclass 36, count 0 2006.201.19:12:14.31#ibcon#end of sib2, iclass 36, count 0 2006.201.19:12:14.31#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:12:14.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:12:14.31#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:12:14.31#ibcon#*before write, iclass 36, count 0 2006.201.19:12:14.31#ibcon#enter sib2, iclass 36, count 0 2006.201.19:12:14.31#ibcon#flushed, iclass 36, count 0 2006.201.19:12:14.31#ibcon#about to write, iclass 36, count 0 2006.201.19:12:14.31#ibcon#wrote, iclass 36, count 0 2006.201.19:12:14.31#ibcon#about to read 3, iclass 36, count 0 2006.201.19:12:14.36#ibcon#read 3, iclass 36, count 0 2006.201.19:12:14.36#ibcon#about to read 4, iclass 36, count 0 2006.201.19:12:14.36#ibcon#read 4, iclass 36, count 0 2006.201.19:12:14.36#ibcon#about to read 5, iclass 36, count 0 2006.201.19:12:14.36#ibcon#read 5, iclass 36, count 0 2006.201.19:12:14.36#ibcon#about to read 6, iclass 36, count 0 2006.201.19:12:14.36#ibcon#read 6, iclass 36, count 0 2006.201.19:12:14.36#ibcon#end of sib2, iclass 36, count 0 2006.201.19:12:14.36#ibcon#*after write, iclass 36, count 0 2006.201.19:12:14.36#ibcon#*before return 0, iclass 36, count 0 2006.201.19:12:14.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:14.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:12:14.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:12:14.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:12:14.36$vck44/vb=3,4 2006.201.19:12:14.36#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.19:12:14.36#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.19:12:14.36#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:14.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:14.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:14.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:14.41#ibcon#enter wrdev, iclass 38, count 2 2006.201.19:12:14.41#ibcon#first serial, iclass 38, count 2 2006.201.19:12:14.41#ibcon#enter sib2, iclass 38, count 2 2006.201.19:12:14.41#ibcon#flushed, iclass 38, count 2 2006.201.19:12:14.41#ibcon#about to write, iclass 38, count 2 2006.201.19:12:14.41#ibcon#wrote, iclass 38, count 2 2006.201.19:12:14.41#ibcon#about to read 3, iclass 38, count 2 2006.201.19:12:14.43#ibcon#read 3, iclass 38, count 2 2006.201.19:12:14.43#ibcon#about to read 4, iclass 38, count 2 2006.201.19:12:14.43#ibcon#read 4, iclass 38, count 2 2006.201.19:12:14.43#ibcon#about to read 5, iclass 38, count 2 2006.201.19:12:14.43#ibcon#read 5, iclass 38, count 2 2006.201.19:12:14.43#ibcon#about to read 6, iclass 38, count 2 2006.201.19:12:14.43#ibcon#read 6, iclass 38, count 2 2006.201.19:12:14.43#ibcon#end of sib2, iclass 38, count 2 2006.201.19:12:14.43#ibcon#*mode == 0, iclass 38, count 2 2006.201.19:12:14.43#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.19:12:14.43#ibcon#[27=AT03-04\r\n] 2006.201.19:12:14.43#ibcon#*before write, iclass 38, count 2 2006.201.19:12:14.43#ibcon#enter sib2, iclass 38, count 2 2006.201.19:12:14.43#ibcon#flushed, iclass 38, count 2 2006.201.19:12:14.43#ibcon#about to write, iclass 38, count 2 2006.201.19:12:14.43#ibcon#wrote, iclass 38, count 2 2006.201.19:12:14.43#ibcon#about to read 3, iclass 38, count 2 2006.201.19:12:14.46#ibcon#read 3, iclass 38, count 2 2006.201.19:12:14.46#ibcon#about to read 4, iclass 38, count 2 2006.201.19:12:14.46#ibcon#read 4, iclass 38, count 2 2006.201.19:12:14.46#ibcon#about to read 5, iclass 38, count 2 2006.201.19:12:14.46#ibcon#read 5, iclass 38, count 2 2006.201.19:12:14.46#ibcon#about to read 6, iclass 38, count 2 2006.201.19:12:14.46#ibcon#read 6, iclass 38, count 2 2006.201.19:12:14.46#ibcon#end of sib2, iclass 38, count 2 2006.201.19:12:14.46#ibcon#*after write, iclass 38, count 2 2006.201.19:12:14.46#ibcon#*before return 0, iclass 38, count 2 2006.201.19:12:14.46#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:14.46#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:12:14.46#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.19:12:14.46#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:14.46#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:14.58#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:14.58#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:14.58#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:12:14.58#ibcon#first serial, iclass 38, count 0 2006.201.19:12:14.58#ibcon#enter sib2, iclass 38, count 0 2006.201.19:12:14.58#ibcon#flushed, iclass 38, count 0 2006.201.19:12:14.58#ibcon#about to write, iclass 38, count 0 2006.201.19:12:14.58#ibcon#wrote, iclass 38, count 0 2006.201.19:12:14.58#ibcon#about to read 3, iclass 38, count 0 2006.201.19:12:14.60#ibcon#read 3, iclass 38, count 0 2006.201.19:12:14.60#ibcon#about to read 4, iclass 38, count 0 2006.201.19:12:14.60#ibcon#read 4, iclass 38, count 0 2006.201.19:12:14.60#ibcon#about to read 5, iclass 38, count 0 2006.201.19:12:14.60#ibcon#read 5, iclass 38, count 0 2006.201.19:12:14.60#ibcon#about to read 6, iclass 38, count 0 2006.201.19:12:14.60#ibcon#read 6, iclass 38, count 0 2006.201.19:12:14.60#ibcon#end of sib2, iclass 38, count 0 2006.201.19:12:14.60#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:12:14.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:12:14.60#ibcon#[27=USB\r\n] 2006.201.19:12:14.60#ibcon#*before write, iclass 38, count 0 2006.201.19:12:14.60#ibcon#enter sib2, iclass 38, count 0 2006.201.19:12:14.60#ibcon#flushed, iclass 38, count 0 2006.201.19:12:14.60#ibcon#about to write, iclass 38, count 0 2006.201.19:12:14.60#ibcon#wrote, iclass 38, count 0 2006.201.19:12:14.60#ibcon#about to read 3, iclass 38, count 0 2006.201.19:12:14.63#ibcon#read 3, iclass 38, count 0 2006.201.19:12:14.63#ibcon#about to read 4, iclass 38, count 0 2006.201.19:12:14.63#ibcon#read 4, iclass 38, count 0 2006.201.19:12:14.63#ibcon#about to read 5, iclass 38, count 0 2006.201.19:12:14.63#ibcon#read 5, iclass 38, count 0 2006.201.19:12:14.63#ibcon#about to read 6, iclass 38, count 0 2006.201.19:12:14.63#ibcon#read 6, iclass 38, count 0 2006.201.19:12:14.63#ibcon#end of sib2, iclass 38, count 0 2006.201.19:12:14.63#ibcon#*after write, iclass 38, count 0 2006.201.19:12:14.63#ibcon#*before return 0, iclass 38, count 0 2006.201.19:12:14.63#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:14.63#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:12:14.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:12:14.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:12:14.63$vck44/vblo=4,679.99 2006.201.19:12:14.63#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.19:12:14.63#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.19:12:14.63#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:14.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:14.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:14.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:14.63#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:12:14.63#ibcon#first serial, iclass 40, count 0 2006.201.19:12:14.63#ibcon#enter sib2, iclass 40, count 0 2006.201.19:12:14.63#ibcon#flushed, iclass 40, count 0 2006.201.19:12:14.63#ibcon#about to write, iclass 40, count 0 2006.201.19:12:14.63#ibcon#wrote, iclass 40, count 0 2006.201.19:12:14.63#ibcon#about to read 3, iclass 40, count 0 2006.201.19:12:14.65#ibcon#read 3, iclass 40, count 0 2006.201.19:12:14.65#ibcon#about to read 4, iclass 40, count 0 2006.201.19:12:14.65#ibcon#read 4, iclass 40, count 0 2006.201.19:12:14.65#ibcon#about to read 5, iclass 40, count 0 2006.201.19:12:14.65#ibcon#read 5, iclass 40, count 0 2006.201.19:12:14.65#ibcon#about to read 6, iclass 40, count 0 2006.201.19:12:14.65#ibcon#read 6, iclass 40, count 0 2006.201.19:12:14.65#ibcon#end of sib2, iclass 40, count 0 2006.201.19:12:14.65#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:12:14.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:12:14.65#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:12:14.65#ibcon#*before write, iclass 40, count 0 2006.201.19:12:14.65#ibcon#enter sib2, iclass 40, count 0 2006.201.19:12:14.65#ibcon#flushed, iclass 40, count 0 2006.201.19:12:14.65#ibcon#about to write, iclass 40, count 0 2006.201.19:12:14.65#ibcon#wrote, iclass 40, count 0 2006.201.19:12:14.65#ibcon#about to read 3, iclass 40, count 0 2006.201.19:12:14.70#ibcon#read 3, iclass 40, count 0 2006.201.19:12:14.70#ibcon#about to read 4, iclass 40, count 0 2006.201.19:12:14.70#ibcon#read 4, iclass 40, count 0 2006.201.19:12:14.70#ibcon#about to read 5, iclass 40, count 0 2006.201.19:12:14.70#ibcon#read 5, iclass 40, count 0 2006.201.19:12:14.70#ibcon#about to read 6, iclass 40, count 0 2006.201.19:12:14.70#ibcon#read 6, iclass 40, count 0 2006.201.19:12:14.70#ibcon#end of sib2, iclass 40, count 0 2006.201.19:12:14.70#ibcon#*after write, iclass 40, count 0 2006.201.19:12:14.70#ibcon#*before return 0, iclass 40, count 0 2006.201.19:12:14.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:14.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:12:14.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:12:14.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:12:14.70$vck44/vb=4,5 2006.201.19:12:14.70#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.19:12:14.70#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.19:12:14.70#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:14.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:14.75#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:14.75#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:14.75#ibcon#enter wrdev, iclass 4, count 2 2006.201.19:12:14.75#ibcon#first serial, iclass 4, count 2 2006.201.19:12:14.75#ibcon#enter sib2, iclass 4, count 2 2006.201.19:12:14.75#ibcon#flushed, iclass 4, count 2 2006.201.19:12:14.75#ibcon#about to write, iclass 4, count 2 2006.201.19:12:14.75#ibcon#wrote, iclass 4, count 2 2006.201.19:12:14.75#ibcon#about to read 3, iclass 4, count 2 2006.201.19:12:14.77#ibcon#read 3, iclass 4, count 2 2006.201.19:12:14.77#ibcon#about to read 4, iclass 4, count 2 2006.201.19:12:14.77#ibcon#read 4, iclass 4, count 2 2006.201.19:12:14.77#ibcon#about to read 5, iclass 4, count 2 2006.201.19:12:14.77#ibcon#read 5, iclass 4, count 2 2006.201.19:12:14.77#ibcon#about to read 6, iclass 4, count 2 2006.201.19:12:14.77#ibcon#read 6, iclass 4, count 2 2006.201.19:12:14.77#ibcon#end of sib2, iclass 4, count 2 2006.201.19:12:14.77#ibcon#*mode == 0, iclass 4, count 2 2006.201.19:12:14.77#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.19:12:14.77#ibcon#[27=AT04-05\r\n] 2006.201.19:12:14.77#ibcon#*before write, iclass 4, count 2 2006.201.19:12:14.77#ibcon#enter sib2, iclass 4, count 2 2006.201.19:12:14.77#ibcon#flushed, iclass 4, count 2 2006.201.19:12:14.77#ibcon#about to write, iclass 4, count 2 2006.201.19:12:14.77#ibcon#wrote, iclass 4, count 2 2006.201.19:12:14.77#ibcon#about to read 3, iclass 4, count 2 2006.201.19:12:14.80#ibcon#read 3, iclass 4, count 2 2006.201.19:12:14.80#ibcon#about to read 4, iclass 4, count 2 2006.201.19:12:14.80#ibcon#read 4, iclass 4, count 2 2006.201.19:12:14.80#ibcon#about to read 5, iclass 4, count 2 2006.201.19:12:14.80#ibcon#read 5, iclass 4, count 2 2006.201.19:12:14.80#ibcon#about to read 6, iclass 4, count 2 2006.201.19:12:14.80#ibcon#read 6, iclass 4, count 2 2006.201.19:12:14.80#ibcon#end of sib2, iclass 4, count 2 2006.201.19:12:14.80#ibcon#*after write, iclass 4, count 2 2006.201.19:12:14.80#ibcon#*before return 0, iclass 4, count 2 2006.201.19:12:14.80#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:14.80#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:12:14.80#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.19:12:14.80#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:14.80#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:14.92#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:14.92#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:14.92#ibcon#enter wrdev, iclass 4, count 0 2006.201.19:12:14.92#ibcon#first serial, iclass 4, count 0 2006.201.19:12:14.92#ibcon#enter sib2, iclass 4, count 0 2006.201.19:12:14.92#ibcon#flushed, iclass 4, count 0 2006.201.19:12:14.92#ibcon#about to write, iclass 4, count 0 2006.201.19:12:14.92#ibcon#wrote, iclass 4, count 0 2006.201.19:12:14.92#ibcon#about to read 3, iclass 4, count 0 2006.201.19:12:14.94#ibcon#read 3, iclass 4, count 0 2006.201.19:12:14.94#ibcon#about to read 4, iclass 4, count 0 2006.201.19:12:14.94#ibcon#read 4, iclass 4, count 0 2006.201.19:12:14.94#ibcon#about to read 5, iclass 4, count 0 2006.201.19:12:14.94#ibcon#read 5, iclass 4, count 0 2006.201.19:12:14.94#ibcon#about to read 6, iclass 4, count 0 2006.201.19:12:14.94#ibcon#read 6, iclass 4, count 0 2006.201.19:12:14.94#ibcon#end of sib2, iclass 4, count 0 2006.201.19:12:14.94#ibcon#*mode == 0, iclass 4, count 0 2006.201.19:12:14.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.19:12:14.94#ibcon#[27=USB\r\n] 2006.201.19:12:14.94#ibcon#*before write, iclass 4, count 0 2006.201.19:12:14.94#ibcon#enter sib2, iclass 4, count 0 2006.201.19:12:14.94#ibcon#flushed, iclass 4, count 0 2006.201.19:12:14.94#ibcon#about to write, iclass 4, count 0 2006.201.19:12:14.94#ibcon#wrote, iclass 4, count 0 2006.201.19:12:14.94#ibcon#about to read 3, iclass 4, count 0 2006.201.19:12:14.97#ibcon#read 3, iclass 4, count 0 2006.201.19:12:14.97#ibcon#about to read 4, iclass 4, count 0 2006.201.19:12:14.97#ibcon#read 4, iclass 4, count 0 2006.201.19:12:14.97#ibcon#about to read 5, iclass 4, count 0 2006.201.19:12:14.97#ibcon#read 5, iclass 4, count 0 2006.201.19:12:14.97#ibcon#about to read 6, iclass 4, count 0 2006.201.19:12:14.97#ibcon#read 6, iclass 4, count 0 2006.201.19:12:14.97#ibcon#end of sib2, iclass 4, count 0 2006.201.19:12:14.97#ibcon#*after write, iclass 4, count 0 2006.201.19:12:14.97#ibcon#*before return 0, iclass 4, count 0 2006.201.19:12:14.97#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:14.97#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:12:14.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.19:12:14.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.19:12:14.97$vck44/vblo=5,709.99 2006.201.19:12:14.97#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.19:12:14.97#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.19:12:14.97#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:14.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:14.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:14.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:14.97#ibcon#enter wrdev, iclass 6, count 0 2006.201.19:12:14.97#ibcon#first serial, iclass 6, count 0 2006.201.19:12:14.97#ibcon#enter sib2, iclass 6, count 0 2006.201.19:12:14.97#ibcon#flushed, iclass 6, count 0 2006.201.19:12:14.97#ibcon#about to write, iclass 6, count 0 2006.201.19:12:14.97#ibcon#wrote, iclass 6, count 0 2006.201.19:12:14.97#ibcon#about to read 3, iclass 6, count 0 2006.201.19:12:14.99#ibcon#read 3, iclass 6, count 0 2006.201.19:12:14.99#ibcon#about to read 4, iclass 6, count 0 2006.201.19:12:14.99#ibcon#read 4, iclass 6, count 0 2006.201.19:12:14.99#ibcon#about to read 5, iclass 6, count 0 2006.201.19:12:14.99#ibcon#read 5, iclass 6, count 0 2006.201.19:12:14.99#ibcon#about to read 6, iclass 6, count 0 2006.201.19:12:14.99#ibcon#read 6, iclass 6, count 0 2006.201.19:12:14.99#ibcon#end of sib2, iclass 6, count 0 2006.201.19:12:14.99#ibcon#*mode == 0, iclass 6, count 0 2006.201.19:12:14.99#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.19:12:14.99#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:12:14.99#ibcon#*before write, iclass 6, count 0 2006.201.19:12:14.99#ibcon#enter sib2, iclass 6, count 0 2006.201.19:12:14.99#ibcon#flushed, iclass 6, count 0 2006.201.19:12:14.99#ibcon#about to write, iclass 6, count 0 2006.201.19:12:14.99#ibcon#wrote, iclass 6, count 0 2006.201.19:12:14.99#ibcon#about to read 3, iclass 6, count 0 2006.201.19:12:15.03#ibcon#read 3, iclass 6, count 0 2006.201.19:12:15.03#ibcon#about to read 4, iclass 6, count 0 2006.201.19:12:15.03#ibcon#read 4, iclass 6, count 0 2006.201.19:12:15.03#ibcon#about to read 5, iclass 6, count 0 2006.201.19:12:15.03#ibcon#read 5, iclass 6, count 0 2006.201.19:12:15.03#ibcon#about to read 6, iclass 6, count 0 2006.201.19:12:15.03#ibcon#read 6, iclass 6, count 0 2006.201.19:12:15.03#ibcon#end of sib2, iclass 6, count 0 2006.201.19:12:15.03#ibcon#*after write, iclass 6, count 0 2006.201.19:12:15.03#ibcon#*before return 0, iclass 6, count 0 2006.201.19:12:15.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:15.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:12:15.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.19:12:15.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.19:12:15.03$vck44/vb=5,4 2006.201.19:12:15.03#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.19:12:15.03#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.19:12:15.03#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:15.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:15.09#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:15.09#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:15.09#ibcon#enter wrdev, iclass 10, count 2 2006.201.19:12:15.09#ibcon#first serial, iclass 10, count 2 2006.201.19:12:15.09#ibcon#enter sib2, iclass 10, count 2 2006.201.19:12:15.09#ibcon#flushed, iclass 10, count 2 2006.201.19:12:15.09#ibcon#about to write, iclass 10, count 2 2006.201.19:12:15.09#ibcon#wrote, iclass 10, count 2 2006.201.19:12:15.09#ibcon#about to read 3, iclass 10, count 2 2006.201.19:12:15.11#ibcon#read 3, iclass 10, count 2 2006.201.19:12:15.11#ibcon#about to read 4, iclass 10, count 2 2006.201.19:12:15.11#ibcon#read 4, iclass 10, count 2 2006.201.19:12:15.11#ibcon#about to read 5, iclass 10, count 2 2006.201.19:12:15.11#ibcon#read 5, iclass 10, count 2 2006.201.19:12:15.11#ibcon#about to read 6, iclass 10, count 2 2006.201.19:12:15.11#ibcon#read 6, iclass 10, count 2 2006.201.19:12:15.11#ibcon#end of sib2, iclass 10, count 2 2006.201.19:12:15.11#ibcon#*mode == 0, iclass 10, count 2 2006.201.19:12:15.11#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.19:12:15.11#ibcon#[27=AT05-04\r\n] 2006.201.19:12:15.11#ibcon#*before write, iclass 10, count 2 2006.201.19:12:15.11#ibcon#enter sib2, iclass 10, count 2 2006.201.19:12:15.11#ibcon#flushed, iclass 10, count 2 2006.201.19:12:15.11#ibcon#about to write, iclass 10, count 2 2006.201.19:12:15.11#ibcon#wrote, iclass 10, count 2 2006.201.19:12:15.11#ibcon#about to read 3, iclass 10, count 2 2006.201.19:12:15.14#ibcon#read 3, iclass 10, count 2 2006.201.19:12:15.14#ibcon#about to read 4, iclass 10, count 2 2006.201.19:12:15.14#ibcon#read 4, iclass 10, count 2 2006.201.19:12:15.14#ibcon#about to read 5, iclass 10, count 2 2006.201.19:12:15.14#ibcon#read 5, iclass 10, count 2 2006.201.19:12:15.14#ibcon#about to read 6, iclass 10, count 2 2006.201.19:12:15.14#ibcon#read 6, iclass 10, count 2 2006.201.19:12:15.14#ibcon#end of sib2, iclass 10, count 2 2006.201.19:12:15.14#ibcon#*after write, iclass 10, count 2 2006.201.19:12:15.14#ibcon#*before return 0, iclass 10, count 2 2006.201.19:12:15.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:15.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:12:15.14#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.19:12:15.14#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:15.14#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:15.26#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:15.26#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:15.26#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:12:15.26#ibcon#first serial, iclass 10, count 0 2006.201.19:12:15.26#ibcon#enter sib2, iclass 10, count 0 2006.201.19:12:15.26#ibcon#flushed, iclass 10, count 0 2006.201.19:12:15.26#ibcon#about to write, iclass 10, count 0 2006.201.19:12:15.26#ibcon#wrote, iclass 10, count 0 2006.201.19:12:15.26#ibcon#about to read 3, iclass 10, count 0 2006.201.19:12:15.28#ibcon#read 3, iclass 10, count 0 2006.201.19:12:15.28#ibcon#about to read 4, iclass 10, count 0 2006.201.19:12:15.28#ibcon#read 4, iclass 10, count 0 2006.201.19:12:15.28#ibcon#about to read 5, iclass 10, count 0 2006.201.19:12:15.28#ibcon#read 5, iclass 10, count 0 2006.201.19:12:15.28#ibcon#about to read 6, iclass 10, count 0 2006.201.19:12:15.28#ibcon#read 6, iclass 10, count 0 2006.201.19:12:15.28#ibcon#end of sib2, iclass 10, count 0 2006.201.19:12:15.28#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:12:15.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:12:15.28#ibcon#[27=USB\r\n] 2006.201.19:12:15.28#ibcon#*before write, iclass 10, count 0 2006.201.19:12:15.28#ibcon#enter sib2, iclass 10, count 0 2006.201.19:12:15.28#ibcon#flushed, iclass 10, count 0 2006.201.19:12:15.28#ibcon#about to write, iclass 10, count 0 2006.201.19:12:15.28#ibcon#wrote, iclass 10, count 0 2006.201.19:12:15.28#ibcon#about to read 3, iclass 10, count 0 2006.201.19:12:15.31#ibcon#read 3, iclass 10, count 0 2006.201.19:12:15.31#ibcon#about to read 4, iclass 10, count 0 2006.201.19:12:15.31#ibcon#read 4, iclass 10, count 0 2006.201.19:12:15.31#ibcon#about to read 5, iclass 10, count 0 2006.201.19:12:15.31#ibcon#read 5, iclass 10, count 0 2006.201.19:12:15.31#ibcon#about to read 6, iclass 10, count 0 2006.201.19:12:15.31#ibcon#read 6, iclass 10, count 0 2006.201.19:12:15.31#ibcon#end of sib2, iclass 10, count 0 2006.201.19:12:15.31#ibcon#*after write, iclass 10, count 0 2006.201.19:12:15.31#ibcon#*before return 0, iclass 10, count 0 2006.201.19:12:15.31#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:15.31#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:12:15.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:12:15.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:12:15.31$vck44/vblo=6,719.99 2006.201.19:12:15.31#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.19:12:15.31#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.19:12:15.31#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:15.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:15.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:15.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:15.31#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:12:15.31#ibcon#first serial, iclass 12, count 0 2006.201.19:12:15.31#ibcon#enter sib2, iclass 12, count 0 2006.201.19:12:15.31#ibcon#flushed, iclass 12, count 0 2006.201.19:12:15.31#ibcon#about to write, iclass 12, count 0 2006.201.19:12:15.31#ibcon#wrote, iclass 12, count 0 2006.201.19:12:15.31#ibcon#about to read 3, iclass 12, count 0 2006.201.19:12:15.33#ibcon#read 3, iclass 12, count 0 2006.201.19:12:15.33#ibcon#about to read 4, iclass 12, count 0 2006.201.19:12:15.33#ibcon#read 4, iclass 12, count 0 2006.201.19:12:15.33#ibcon#about to read 5, iclass 12, count 0 2006.201.19:12:15.33#ibcon#read 5, iclass 12, count 0 2006.201.19:12:15.33#ibcon#about to read 6, iclass 12, count 0 2006.201.19:12:15.33#ibcon#read 6, iclass 12, count 0 2006.201.19:12:15.33#ibcon#end of sib2, iclass 12, count 0 2006.201.19:12:15.33#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:12:15.33#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:12:15.33#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:12:15.33#ibcon#*before write, iclass 12, count 0 2006.201.19:12:15.33#ibcon#enter sib2, iclass 12, count 0 2006.201.19:12:15.33#ibcon#flushed, iclass 12, count 0 2006.201.19:12:15.33#ibcon#about to write, iclass 12, count 0 2006.201.19:12:15.33#ibcon#wrote, iclass 12, count 0 2006.201.19:12:15.33#ibcon#about to read 3, iclass 12, count 0 2006.201.19:12:15.38#ibcon#read 3, iclass 12, count 0 2006.201.19:12:15.38#ibcon#about to read 4, iclass 12, count 0 2006.201.19:12:15.38#ibcon#read 4, iclass 12, count 0 2006.201.19:12:15.38#ibcon#about to read 5, iclass 12, count 0 2006.201.19:12:15.38#ibcon#read 5, iclass 12, count 0 2006.201.19:12:15.38#ibcon#about to read 6, iclass 12, count 0 2006.201.19:12:15.38#ibcon#read 6, iclass 12, count 0 2006.201.19:12:15.38#ibcon#end of sib2, iclass 12, count 0 2006.201.19:12:15.38#ibcon#*after write, iclass 12, count 0 2006.201.19:12:15.38#ibcon#*before return 0, iclass 12, count 0 2006.201.19:12:15.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:15.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:12:15.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:12:15.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:12:15.38$vck44/vb=6,4 2006.201.19:12:15.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.19:12:15.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.19:12:15.38#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:15.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:15.43#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:15.43#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:15.43#ibcon#enter wrdev, iclass 14, count 2 2006.201.19:12:15.43#ibcon#first serial, iclass 14, count 2 2006.201.19:12:15.43#ibcon#enter sib2, iclass 14, count 2 2006.201.19:12:15.43#ibcon#flushed, iclass 14, count 2 2006.201.19:12:15.43#ibcon#about to write, iclass 14, count 2 2006.201.19:12:15.43#ibcon#wrote, iclass 14, count 2 2006.201.19:12:15.43#ibcon#about to read 3, iclass 14, count 2 2006.201.19:12:15.45#ibcon#read 3, iclass 14, count 2 2006.201.19:12:15.45#ibcon#about to read 4, iclass 14, count 2 2006.201.19:12:15.45#ibcon#read 4, iclass 14, count 2 2006.201.19:12:15.45#ibcon#about to read 5, iclass 14, count 2 2006.201.19:12:15.45#ibcon#read 5, iclass 14, count 2 2006.201.19:12:15.45#ibcon#about to read 6, iclass 14, count 2 2006.201.19:12:15.45#ibcon#read 6, iclass 14, count 2 2006.201.19:12:15.45#ibcon#end of sib2, iclass 14, count 2 2006.201.19:12:15.45#ibcon#*mode == 0, iclass 14, count 2 2006.201.19:12:15.45#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.19:12:15.45#ibcon#[27=AT06-04\r\n] 2006.201.19:12:15.45#ibcon#*before write, iclass 14, count 2 2006.201.19:12:15.45#ibcon#enter sib2, iclass 14, count 2 2006.201.19:12:15.45#ibcon#flushed, iclass 14, count 2 2006.201.19:12:15.45#ibcon#about to write, iclass 14, count 2 2006.201.19:12:15.45#ibcon#wrote, iclass 14, count 2 2006.201.19:12:15.45#ibcon#about to read 3, iclass 14, count 2 2006.201.19:12:15.48#ibcon#read 3, iclass 14, count 2 2006.201.19:12:15.48#ibcon#about to read 4, iclass 14, count 2 2006.201.19:12:15.48#ibcon#read 4, iclass 14, count 2 2006.201.19:12:15.48#ibcon#about to read 5, iclass 14, count 2 2006.201.19:12:15.48#ibcon#read 5, iclass 14, count 2 2006.201.19:12:15.48#ibcon#about to read 6, iclass 14, count 2 2006.201.19:12:15.48#ibcon#read 6, iclass 14, count 2 2006.201.19:12:15.48#ibcon#end of sib2, iclass 14, count 2 2006.201.19:12:15.48#ibcon#*after write, iclass 14, count 2 2006.201.19:12:15.48#ibcon#*before return 0, iclass 14, count 2 2006.201.19:12:15.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:15.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:12:15.48#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.19:12:15.48#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:15.48#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:15.60#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:15.60#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:15.60#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:12:15.60#ibcon#first serial, iclass 14, count 0 2006.201.19:12:15.60#ibcon#enter sib2, iclass 14, count 0 2006.201.19:12:15.60#ibcon#flushed, iclass 14, count 0 2006.201.19:12:15.60#ibcon#about to write, iclass 14, count 0 2006.201.19:12:15.60#ibcon#wrote, iclass 14, count 0 2006.201.19:12:15.60#ibcon#about to read 3, iclass 14, count 0 2006.201.19:12:15.62#ibcon#read 3, iclass 14, count 0 2006.201.19:12:15.62#ibcon#about to read 4, iclass 14, count 0 2006.201.19:12:15.62#ibcon#read 4, iclass 14, count 0 2006.201.19:12:15.62#ibcon#about to read 5, iclass 14, count 0 2006.201.19:12:15.62#ibcon#read 5, iclass 14, count 0 2006.201.19:12:15.62#ibcon#about to read 6, iclass 14, count 0 2006.201.19:12:15.62#ibcon#read 6, iclass 14, count 0 2006.201.19:12:15.62#ibcon#end of sib2, iclass 14, count 0 2006.201.19:12:15.62#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:12:15.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:12:15.62#ibcon#[27=USB\r\n] 2006.201.19:12:15.62#ibcon#*before write, iclass 14, count 0 2006.201.19:12:15.62#ibcon#enter sib2, iclass 14, count 0 2006.201.19:12:15.62#ibcon#flushed, iclass 14, count 0 2006.201.19:12:15.62#ibcon#about to write, iclass 14, count 0 2006.201.19:12:15.62#ibcon#wrote, iclass 14, count 0 2006.201.19:12:15.62#ibcon#about to read 3, iclass 14, count 0 2006.201.19:12:15.65#ibcon#read 3, iclass 14, count 0 2006.201.19:12:15.65#ibcon#about to read 4, iclass 14, count 0 2006.201.19:12:15.65#ibcon#read 4, iclass 14, count 0 2006.201.19:12:15.65#ibcon#about to read 5, iclass 14, count 0 2006.201.19:12:15.65#ibcon#read 5, iclass 14, count 0 2006.201.19:12:15.65#ibcon#about to read 6, iclass 14, count 0 2006.201.19:12:15.65#ibcon#read 6, iclass 14, count 0 2006.201.19:12:15.65#ibcon#end of sib2, iclass 14, count 0 2006.201.19:12:15.65#ibcon#*after write, iclass 14, count 0 2006.201.19:12:15.65#ibcon#*before return 0, iclass 14, count 0 2006.201.19:12:15.65#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:15.65#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:12:15.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:12:15.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:12:15.65$vck44/vblo=7,734.99 2006.201.19:12:15.65#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.19:12:15.65#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.19:12:15.65#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:15.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:15.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:15.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:15.65#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:12:15.65#ibcon#first serial, iclass 16, count 0 2006.201.19:12:15.65#ibcon#enter sib2, iclass 16, count 0 2006.201.19:12:15.65#ibcon#flushed, iclass 16, count 0 2006.201.19:12:15.65#ibcon#about to write, iclass 16, count 0 2006.201.19:12:15.65#ibcon#wrote, iclass 16, count 0 2006.201.19:12:15.65#ibcon#about to read 3, iclass 16, count 0 2006.201.19:12:15.67#ibcon#read 3, iclass 16, count 0 2006.201.19:12:15.67#ibcon#about to read 4, iclass 16, count 0 2006.201.19:12:15.67#ibcon#read 4, iclass 16, count 0 2006.201.19:12:15.67#ibcon#about to read 5, iclass 16, count 0 2006.201.19:12:15.67#ibcon#read 5, iclass 16, count 0 2006.201.19:12:15.67#ibcon#about to read 6, iclass 16, count 0 2006.201.19:12:15.67#ibcon#read 6, iclass 16, count 0 2006.201.19:12:15.67#ibcon#end of sib2, iclass 16, count 0 2006.201.19:12:15.67#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:12:15.67#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:12:15.67#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:12:15.67#ibcon#*before write, iclass 16, count 0 2006.201.19:12:15.67#ibcon#enter sib2, iclass 16, count 0 2006.201.19:12:15.67#ibcon#flushed, iclass 16, count 0 2006.201.19:12:15.67#ibcon#about to write, iclass 16, count 0 2006.201.19:12:15.67#ibcon#wrote, iclass 16, count 0 2006.201.19:12:15.67#ibcon#about to read 3, iclass 16, count 0 2006.201.19:12:15.71#ibcon#read 3, iclass 16, count 0 2006.201.19:12:15.71#ibcon#about to read 4, iclass 16, count 0 2006.201.19:12:15.71#ibcon#read 4, iclass 16, count 0 2006.201.19:12:15.71#ibcon#about to read 5, iclass 16, count 0 2006.201.19:12:15.71#ibcon#read 5, iclass 16, count 0 2006.201.19:12:15.71#ibcon#about to read 6, iclass 16, count 0 2006.201.19:12:15.71#ibcon#read 6, iclass 16, count 0 2006.201.19:12:15.71#ibcon#end of sib2, iclass 16, count 0 2006.201.19:12:15.71#ibcon#*after write, iclass 16, count 0 2006.201.19:12:15.71#ibcon#*before return 0, iclass 16, count 0 2006.201.19:12:15.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:15.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:12:15.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:12:15.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:12:15.71$vck44/vb=7,4 2006.201.19:12:15.71#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.19:12:15.71#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.19:12:15.71#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:15.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:15.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:15.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:15.77#ibcon#enter wrdev, iclass 18, count 2 2006.201.19:12:15.77#ibcon#first serial, iclass 18, count 2 2006.201.19:12:15.77#ibcon#enter sib2, iclass 18, count 2 2006.201.19:12:15.77#ibcon#flushed, iclass 18, count 2 2006.201.19:12:15.77#ibcon#about to write, iclass 18, count 2 2006.201.19:12:15.77#ibcon#wrote, iclass 18, count 2 2006.201.19:12:15.77#ibcon#about to read 3, iclass 18, count 2 2006.201.19:12:15.79#ibcon#read 3, iclass 18, count 2 2006.201.19:12:15.79#ibcon#about to read 4, iclass 18, count 2 2006.201.19:12:15.79#ibcon#read 4, iclass 18, count 2 2006.201.19:12:15.79#ibcon#about to read 5, iclass 18, count 2 2006.201.19:12:15.79#ibcon#read 5, iclass 18, count 2 2006.201.19:12:15.79#ibcon#about to read 6, iclass 18, count 2 2006.201.19:12:15.79#ibcon#read 6, iclass 18, count 2 2006.201.19:12:15.79#ibcon#end of sib2, iclass 18, count 2 2006.201.19:12:15.79#ibcon#*mode == 0, iclass 18, count 2 2006.201.19:12:15.79#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.19:12:15.79#ibcon#[27=AT07-04\r\n] 2006.201.19:12:15.79#ibcon#*before write, iclass 18, count 2 2006.201.19:12:15.79#ibcon#enter sib2, iclass 18, count 2 2006.201.19:12:15.79#ibcon#flushed, iclass 18, count 2 2006.201.19:12:15.79#ibcon#about to write, iclass 18, count 2 2006.201.19:12:15.79#ibcon#wrote, iclass 18, count 2 2006.201.19:12:15.79#ibcon#about to read 3, iclass 18, count 2 2006.201.19:12:15.82#ibcon#read 3, iclass 18, count 2 2006.201.19:12:15.82#ibcon#about to read 4, iclass 18, count 2 2006.201.19:12:15.82#ibcon#read 4, iclass 18, count 2 2006.201.19:12:15.82#ibcon#about to read 5, iclass 18, count 2 2006.201.19:12:15.82#ibcon#read 5, iclass 18, count 2 2006.201.19:12:15.82#ibcon#about to read 6, iclass 18, count 2 2006.201.19:12:15.82#ibcon#read 6, iclass 18, count 2 2006.201.19:12:15.82#ibcon#end of sib2, iclass 18, count 2 2006.201.19:12:15.82#ibcon#*after write, iclass 18, count 2 2006.201.19:12:15.82#ibcon#*before return 0, iclass 18, count 2 2006.201.19:12:15.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:15.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:12:15.82#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.19:12:15.82#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:15.82#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:15.94#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:15.94#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:15.94#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:12:15.94#ibcon#first serial, iclass 18, count 0 2006.201.19:12:15.94#ibcon#enter sib2, iclass 18, count 0 2006.201.19:12:15.94#ibcon#flushed, iclass 18, count 0 2006.201.19:12:15.94#ibcon#about to write, iclass 18, count 0 2006.201.19:12:15.94#ibcon#wrote, iclass 18, count 0 2006.201.19:12:15.94#ibcon#about to read 3, iclass 18, count 0 2006.201.19:12:15.96#ibcon#read 3, iclass 18, count 0 2006.201.19:12:15.96#ibcon#about to read 4, iclass 18, count 0 2006.201.19:12:15.96#ibcon#read 4, iclass 18, count 0 2006.201.19:12:15.96#ibcon#about to read 5, iclass 18, count 0 2006.201.19:12:15.96#ibcon#read 5, iclass 18, count 0 2006.201.19:12:15.96#ibcon#about to read 6, iclass 18, count 0 2006.201.19:12:15.96#ibcon#read 6, iclass 18, count 0 2006.201.19:12:15.96#ibcon#end of sib2, iclass 18, count 0 2006.201.19:12:15.96#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:12:15.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:12:15.96#ibcon#[27=USB\r\n] 2006.201.19:12:15.96#ibcon#*before write, iclass 18, count 0 2006.201.19:12:15.96#ibcon#enter sib2, iclass 18, count 0 2006.201.19:12:15.96#ibcon#flushed, iclass 18, count 0 2006.201.19:12:15.96#ibcon#about to write, iclass 18, count 0 2006.201.19:12:15.96#ibcon#wrote, iclass 18, count 0 2006.201.19:12:15.96#ibcon#about to read 3, iclass 18, count 0 2006.201.19:12:15.99#ibcon#read 3, iclass 18, count 0 2006.201.19:12:15.99#ibcon#about to read 4, iclass 18, count 0 2006.201.19:12:15.99#ibcon#read 4, iclass 18, count 0 2006.201.19:12:15.99#ibcon#about to read 5, iclass 18, count 0 2006.201.19:12:15.99#ibcon#read 5, iclass 18, count 0 2006.201.19:12:15.99#ibcon#about to read 6, iclass 18, count 0 2006.201.19:12:15.99#ibcon#read 6, iclass 18, count 0 2006.201.19:12:15.99#ibcon#end of sib2, iclass 18, count 0 2006.201.19:12:15.99#ibcon#*after write, iclass 18, count 0 2006.201.19:12:15.99#ibcon#*before return 0, iclass 18, count 0 2006.201.19:12:15.99#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:15.99#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:12:15.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:12:15.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:12:15.99$vck44/vblo=8,744.99 2006.201.19:12:15.99#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.19:12:15.99#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.19:12:15.99#ibcon#ireg 17 cls_cnt 0 2006.201.19:12:15.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:15.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:15.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:15.99#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:12:15.99#ibcon#first serial, iclass 20, count 0 2006.201.19:12:15.99#ibcon#enter sib2, iclass 20, count 0 2006.201.19:12:15.99#ibcon#flushed, iclass 20, count 0 2006.201.19:12:15.99#ibcon#about to write, iclass 20, count 0 2006.201.19:12:15.99#ibcon#wrote, iclass 20, count 0 2006.201.19:12:15.99#ibcon#about to read 3, iclass 20, count 0 2006.201.19:12:16.01#ibcon#read 3, iclass 20, count 0 2006.201.19:12:16.01#ibcon#about to read 4, iclass 20, count 0 2006.201.19:12:16.01#ibcon#read 4, iclass 20, count 0 2006.201.19:12:16.01#ibcon#about to read 5, iclass 20, count 0 2006.201.19:12:16.01#ibcon#read 5, iclass 20, count 0 2006.201.19:12:16.01#ibcon#about to read 6, iclass 20, count 0 2006.201.19:12:16.01#ibcon#read 6, iclass 20, count 0 2006.201.19:12:16.01#ibcon#end of sib2, iclass 20, count 0 2006.201.19:12:16.01#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:12:16.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:12:16.01#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:12:16.01#ibcon#*before write, iclass 20, count 0 2006.201.19:12:16.01#ibcon#enter sib2, iclass 20, count 0 2006.201.19:12:16.01#ibcon#flushed, iclass 20, count 0 2006.201.19:12:16.01#ibcon#about to write, iclass 20, count 0 2006.201.19:12:16.01#ibcon#wrote, iclass 20, count 0 2006.201.19:12:16.01#ibcon#about to read 3, iclass 20, count 0 2006.201.19:12:16.06#ibcon#read 3, iclass 20, count 0 2006.201.19:12:16.06#ibcon#about to read 4, iclass 20, count 0 2006.201.19:12:16.06#ibcon#read 4, iclass 20, count 0 2006.201.19:12:16.06#ibcon#about to read 5, iclass 20, count 0 2006.201.19:12:16.06#ibcon#read 5, iclass 20, count 0 2006.201.19:12:16.06#ibcon#about to read 6, iclass 20, count 0 2006.201.19:12:16.06#ibcon#read 6, iclass 20, count 0 2006.201.19:12:16.06#ibcon#end of sib2, iclass 20, count 0 2006.201.19:12:16.06#ibcon#*after write, iclass 20, count 0 2006.201.19:12:16.06#ibcon#*before return 0, iclass 20, count 0 2006.201.19:12:16.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:16.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:12:16.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:12:16.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:12:16.06$vck44/vb=8,4 2006.201.19:12:16.06#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.19:12:16.06#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.19:12:16.06#ibcon#ireg 11 cls_cnt 2 2006.201.19:12:16.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:16.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:16.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:16.11#ibcon#enter wrdev, iclass 22, count 2 2006.201.19:12:16.11#ibcon#first serial, iclass 22, count 2 2006.201.19:12:16.11#ibcon#enter sib2, iclass 22, count 2 2006.201.19:12:16.11#ibcon#flushed, iclass 22, count 2 2006.201.19:12:16.11#ibcon#about to write, iclass 22, count 2 2006.201.19:12:16.11#ibcon#wrote, iclass 22, count 2 2006.201.19:12:16.11#ibcon#about to read 3, iclass 22, count 2 2006.201.19:12:16.13#ibcon#read 3, iclass 22, count 2 2006.201.19:12:16.13#ibcon#about to read 4, iclass 22, count 2 2006.201.19:12:16.13#ibcon#read 4, iclass 22, count 2 2006.201.19:12:16.13#ibcon#about to read 5, iclass 22, count 2 2006.201.19:12:16.13#ibcon#read 5, iclass 22, count 2 2006.201.19:12:16.13#ibcon#about to read 6, iclass 22, count 2 2006.201.19:12:16.13#ibcon#read 6, iclass 22, count 2 2006.201.19:12:16.13#ibcon#end of sib2, iclass 22, count 2 2006.201.19:12:16.13#ibcon#*mode == 0, iclass 22, count 2 2006.201.19:12:16.13#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.19:12:16.13#ibcon#[27=AT08-04\r\n] 2006.201.19:12:16.13#ibcon#*before write, iclass 22, count 2 2006.201.19:12:16.13#ibcon#enter sib2, iclass 22, count 2 2006.201.19:12:16.13#ibcon#flushed, iclass 22, count 2 2006.201.19:12:16.13#ibcon#about to write, iclass 22, count 2 2006.201.19:12:16.13#ibcon#wrote, iclass 22, count 2 2006.201.19:12:16.13#ibcon#about to read 3, iclass 22, count 2 2006.201.19:12:16.16#ibcon#read 3, iclass 22, count 2 2006.201.19:12:16.16#ibcon#about to read 4, iclass 22, count 2 2006.201.19:12:16.16#ibcon#read 4, iclass 22, count 2 2006.201.19:12:16.16#ibcon#about to read 5, iclass 22, count 2 2006.201.19:12:16.16#ibcon#read 5, iclass 22, count 2 2006.201.19:12:16.16#ibcon#about to read 6, iclass 22, count 2 2006.201.19:12:16.16#ibcon#read 6, iclass 22, count 2 2006.201.19:12:16.16#ibcon#end of sib2, iclass 22, count 2 2006.201.19:12:16.16#ibcon#*after write, iclass 22, count 2 2006.201.19:12:16.16#ibcon#*before return 0, iclass 22, count 2 2006.201.19:12:16.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:16.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:12:16.16#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.19:12:16.16#ibcon#ireg 7 cls_cnt 0 2006.201.19:12:16.16#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:16.28#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:16.28#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:16.28#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:12:16.28#ibcon#first serial, iclass 22, count 0 2006.201.19:12:16.28#ibcon#enter sib2, iclass 22, count 0 2006.201.19:12:16.28#ibcon#flushed, iclass 22, count 0 2006.201.19:12:16.28#ibcon#about to write, iclass 22, count 0 2006.201.19:12:16.28#ibcon#wrote, iclass 22, count 0 2006.201.19:12:16.28#ibcon#about to read 3, iclass 22, count 0 2006.201.19:12:16.30#ibcon#read 3, iclass 22, count 0 2006.201.19:12:16.30#ibcon#about to read 4, iclass 22, count 0 2006.201.19:12:16.30#ibcon#read 4, iclass 22, count 0 2006.201.19:12:16.30#ibcon#about to read 5, iclass 22, count 0 2006.201.19:12:16.30#ibcon#read 5, iclass 22, count 0 2006.201.19:12:16.30#ibcon#about to read 6, iclass 22, count 0 2006.201.19:12:16.30#ibcon#read 6, iclass 22, count 0 2006.201.19:12:16.30#ibcon#end of sib2, iclass 22, count 0 2006.201.19:12:16.30#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:12:16.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:12:16.30#ibcon#[27=USB\r\n] 2006.201.19:12:16.30#ibcon#*before write, iclass 22, count 0 2006.201.19:12:16.30#ibcon#enter sib2, iclass 22, count 0 2006.201.19:12:16.30#ibcon#flushed, iclass 22, count 0 2006.201.19:12:16.30#ibcon#about to write, iclass 22, count 0 2006.201.19:12:16.30#ibcon#wrote, iclass 22, count 0 2006.201.19:12:16.30#ibcon#about to read 3, iclass 22, count 0 2006.201.19:12:16.33#ibcon#read 3, iclass 22, count 0 2006.201.19:12:16.33#ibcon#about to read 4, iclass 22, count 0 2006.201.19:12:16.33#ibcon#read 4, iclass 22, count 0 2006.201.19:12:16.33#ibcon#about to read 5, iclass 22, count 0 2006.201.19:12:16.33#ibcon#read 5, iclass 22, count 0 2006.201.19:12:16.33#ibcon#about to read 6, iclass 22, count 0 2006.201.19:12:16.33#ibcon#read 6, iclass 22, count 0 2006.201.19:12:16.33#ibcon#end of sib2, iclass 22, count 0 2006.201.19:12:16.33#ibcon#*after write, iclass 22, count 0 2006.201.19:12:16.33#ibcon#*before return 0, iclass 22, count 0 2006.201.19:12:16.33#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:16.33#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:12:16.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:12:16.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:12:16.33$vck44/vabw=wide 2006.201.19:12:16.33#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.19:12:16.33#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.19:12:16.33#ibcon#ireg 8 cls_cnt 0 2006.201.19:12:16.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:16.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:16.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:16.33#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:12:16.33#ibcon#first serial, iclass 24, count 0 2006.201.19:12:16.33#ibcon#enter sib2, iclass 24, count 0 2006.201.19:12:16.33#ibcon#flushed, iclass 24, count 0 2006.201.19:12:16.33#ibcon#about to write, iclass 24, count 0 2006.201.19:12:16.33#ibcon#wrote, iclass 24, count 0 2006.201.19:12:16.33#ibcon#about to read 3, iclass 24, count 0 2006.201.19:12:16.35#ibcon#read 3, iclass 24, count 0 2006.201.19:12:16.35#ibcon#about to read 4, iclass 24, count 0 2006.201.19:12:16.35#ibcon#read 4, iclass 24, count 0 2006.201.19:12:16.35#ibcon#about to read 5, iclass 24, count 0 2006.201.19:12:16.35#ibcon#read 5, iclass 24, count 0 2006.201.19:12:16.35#ibcon#about to read 6, iclass 24, count 0 2006.201.19:12:16.35#ibcon#read 6, iclass 24, count 0 2006.201.19:12:16.35#ibcon#end of sib2, iclass 24, count 0 2006.201.19:12:16.35#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:12:16.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:12:16.35#ibcon#[25=BW32\r\n] 2006.201.19:12:16.35#ibcon#*before write, iclass 24, count 0 2006.201.19:12:16.35#ibcon#enter sib2, iclass 24, count 0 2006.201.19:12:16.35#ibcon#flushed, iclass 24, count 0 2006.201.19:12:16.35#ibcon#about to write, iclass 24, count 0 2006.201.19:12:16.35#ibcon#wrote, iclass 24, count 0 2006.201.19:12:16.35#ibcon#about to read 3, iclass 24, count 0 2006.201.19:12:16.39#ibcon#read 3, iclass 24, count 0 2006.201.19:12:16.39#ibcon#about to read 4, iclass 24, count 0 2006.201.19:12:16.39#ibcon#read 4, iclass 24, count 0 2006.201.19:12:16.39#ibcon#about to read 5, iclass 24, count 0 2006.201.19:12:16.39#ibcon#read 5, iclass 24, count 0 2006.201.19:12:16.39#ibcon#about to read 6, iclass 24, count 0 2006.201.19:12:16.39#ibcon#read 6, iclass 24, count 0 2006.201.19:12:16.39#ibcon#end of sib2, iclass 24, count 0 2006.201.19:12:16.39#ibcon#*after write, iclass 24, count 0 2006.201.19:12:16.39#ibcon#*before return 0, iclass 24, count 0 2006.201.19:12:16.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:16.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:12:16.39#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:12:16.39#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:12:16.39$vck44/vbbw=wide 2006.201.19:12:16.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.19:12:16.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.19:12:16.39#ibcon#ireg 8 cls_cnt 0 2006.201.19:12:16.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:12:16.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:12:16.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:12:16.45#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:12:16.45#ibcon#first serial, iclass 26, count 0 2006.201.19:12:16.45#ibcon#enter sib2, iclass 26, count 0 2006.201.19:12:16.45#ibcon#flushed, iclass 26, count 0 2006.201.19:12:16.45#ibcon#about to write, iclass 26, count 0 2006.201.19:12:16.45#ibcon#wrote, iclass 26, count 0 2006.201.19:12:16.45#ibcon#about to read 3, iclass 26, count 0 2006.201.19:12:16.47#ibcon#read 3, iclass 26, count 0 2006.201.19:12:16.47#ibcon#about to read 4, iclass 26, count 0 2006.201.19:12:16.47#ibcon#read 4, iclass 26, count 0 2006.201.19:12:16.47#ibcon#about to read 5, iclass 26, count 0 2006.201.19:12:16.47#ibcon#read 5, iclass 26, count 0 2006.201.19:12:16.47#ibcon#about to read 6, iclass 26, count 0 2006.201.19:12:16.47#ibcon#read 6, iclass 26, count 0 2006.201.19:12:16.47#ibcon#end of sib2, iclass 26, count 0 2006.201.19:12:16.47#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:12:16.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:12:16.47#ibcon#[27=BW32\r\n] 2006.201.19:12:16.47#ibcon#*before write, iclass 26, count 0 2006.201.19:12:16.47#ibcon#enter sib2, iclass 26, count 0 2006.201.19:12:16.47#ibcon#flushed, iclass 26, count 0 2006.201.19:12:16.47#ibcon#about to write, iclass 26, count 0 2006.201.19:12:16.47#ibcon#wrote, iclass 26, count 0 2006.201.19:12:16.47#ibcon#about to read 3, iclass 26, count 0 2006.201.19:12:16.50#ibcon#read 3, iclass 26, count 0 2006.201.19:12:16.50#ibcon#about to read 4, iclass 26, count 0 2006.201.19:12:16.50#ibcon#read 4, iclass 26, count 0 2006.201.19:12:16.50#ibcon#about to read 5, iclass 26, count 0 2006.201.19:12:16.50#ibcon#read 5, iclass 26, count 0 2006.201.19:12:16.50#ibcon#about to read 6, iclass 26, count 0 2006.201.19:12:16.50#ibcon#read 6, iclass 26, count 0 2006.201.19:12:16.50#ibcon#end of sib2, iclass 26, count 0 2006.201.19:12:16.50#ibcon#*after write, iclass 26, count 0 2006.201.19:12:16.50#ibcon#*before return 0, iclass 26, count 0 2006.201.19:12:16.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:12:16.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:12:16.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:12:16.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:12:16.50$setupk4/ifdk4 2006.201.19:12:16.50$ifdk4/lo= 2006.201.19:12:16.50$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:12:16.50$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:12:16.50$ifdk4/patch= 2006.201.19:12:16.50$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:12:16.50$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:12:16.50$setupk4/!*+20s 2006.201.19:12:19.57#abcon#<5=/04 0.9 2.5 20.521001002.2\r\n> 2006.201.19:12:19.59#abcon#{5=INTERFACE CLEAR} 2006.201.19:12:19.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:12:29.74#abcon#<5=/04 0.9 2.4 20.521001002.2\r\n> 2006.201.19:12:29.76#abcon#{5=INTERFACE CLEAR} 2006.201.19:12:29.82#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:12:30.98$setupk4/"tpicd 2006.201.19:12:30.98$setupk4/echo=off 2006.201.19:12:30.98$setupk4/xlog=off 2006.201.19:12:30.98:!2006.201.19:13:10 2006.201.19:12:33.14#trakl#Source acquired 2006.201.19:12:33.14#flagr#flagr/antenna,acquired 2006.201.19:13:10.00:preob 2006.201.19:13:10.14/onsource/TRACKING 2006.201.19:13:10.14:!2006.201.19:13:20 2006.201.19:13:20.00:"tape 2006.201.19:13:20.00:"st=record 2006.201.19:13:20.00:data_valid=on 2006.201.19:13:20.00:midob 2006.201.19:13:21.14/onsource/TRACKING 2006.201.19:13:21.14/wx/20.51,1002.3,100 2006.201.19:13:21.26/cable/+6.4800E-03 2006.201.19:13:22.35/va/01,08,usb,yes,58,62 2006.201.19:13:22.35/va/02,07,usb,yes,62,64 2006.201.19:13:22.35/va/03,08,usb,yes,57,59 2006.201.19:13:22.35/va/04,07,usb,yes,64,68 2006.201.19:13:22.35/va/05,04,usb,yes,57,59 2006.201.19:13:22.35/va/06,05,usb,yes,57,58 2006.201.19:13:22.35/va/07,05,usb,yes,56,58 2006.201.19:13:22.35/va/08,04,usb,yes,56,65 2006.201.19:13:22.58/valo/01,524.99,yes,locked 2006.201.19:13:22.58/valo/02,534.99,yes,locked 2006.201.19:13:22.58/valo/03,564.99,yes,locked 2006.201.19:13:22.58/valo/04,624.99,yes,locked 2006.201.19:13:22.58/valo/05,734.99,yes,locked 2006.201.19:13:22.58/valo/06,814.99,yes,locked 2006.201.19:13:22.58/valo/07,864.99,yes,locked 2006.201.19:13:22.58/valo/08,884.99,yes,locked 2006.201.19:13:23.67/vb/01,04,usb,yes,43,41 2006.201.19:13:23.67/vb/02,05,usb,yes,40,41 2006.201.19:13:23.67/vb/03,04,usb,yes,42,46 2006.201.19:13:23.67/vb/04,05,usb,yes,42,41 2006.201.19:13:23.67/vb/05,04,usb,yes,38,41 2006.201.19:13:23.67/vb/06,04,usb,yes,44,39 2006.201.19:13:23.67/vb/07,04,usb,yes,43,44 2006.201.19:13:23.67/vb/08,04,usb,yes,40,44 2006.201.19:13:23.91/vblo/01,629.99,yes,locked 2006.201.19:13:23.91/vblo/02,634.99,yes,locked 2006.201.19:13:23.91/vblo/03,649.99,yes,locked 2006.201.19:13:23.91/vblo/04,679.99,yes,locked 2006.201.19:13:23.91/vblo/05,709.99,yes,locked 2006.201.19:13:23.91/vblo/06,719.99,yes,locked 2006.201.19:13:23.91/vblo/07,734.99,yes,locked 2006.201.19:13:23.91/vblo/08,744.99,yes,locked 2006.201.19:13:24.06/vabw/8 2006.201.19:13:24.21/vbbw/8 2006.201.19:13:24.30/xfe/off,on,16.7 2006.201.19:13:24.69/ifatt/23,28,28,28 2006.201.19:13:25.06/fmout-gps/S +4.51E-07 2006.201.19:13:25.10:!2006.201.19:14:20 2006.201.19:14:20.00:data_valid=off 2006.201.19:14:20.00:"et 2006.201.19:14:20.00:!+3s 2006.201.19:14:23.02:"tape 2006.201.19:14:23.02:postob 2006.201.19:14:23.09/cable/+6.4784E-03 2006.201.19:14:23.09/wx/20.50,1002.3,100 2006.201.19:14:23.17/fmout-gps/S +4.51E-07 2006.201.19:14:23.17:scan_name=201-1916,jd0607,40 2006.201.19:14:23.18:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.201.19:14:24.14#flagr#flagr/antenna,new-source 2006.201.19:14:24.14:checkk5 2006.201.19:14:24.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:14:24.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:14:25.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:14:25.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:14:26.01/chk_obsdata//k5ts1/T2011913??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.19:14:26.37/chk_obsdata//k5ts2/T2011913??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.19:14:26.74/chk_obsdata//k5ts3/T2011913??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.19:14:27.11/chk_obsdata//k5ts4/T2011913??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.19:14:27.81/k5log//k5ts1_log_newline 2006.201.19:14:28.52/k5log//k5ts2_log_newline 2006.201.19:14:29.21/k5log//k5ts3_log_newline 2006.201.19:14:29.90/k5log//k5ts4_log_newline 2006.201.19:14:29.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:14:29.93:setupk4=1 2006.201.19:14:29.93$setupk4/echo=on 2006.201.19:14:29.93$setupk4/pcalon 2006.201.19:14:29.93$pcalon/"no phase cal control is implemented here 2006.201.19:14:29.93$setupk4/"tpicd=stop 2006.201.19:14:29.93$setupk4/"rec=synch_on 2006.201.19:14:29.93$setupk4/"rec_mode=128 2006.201.19:14:29.93$setupk4/!* 2006.201.19:14:29.93$setupk4/recpk4 2006.201.19:14:29.93$recpk4/recpatch= 2006.201.19:14:29.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:14:29.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:14:29.93$setupk4/vck44 2006.201.19:14:29.93$vck44/valo=1,524.99 2006.201.19:14:29.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.19:14:29.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.19:14:29.93#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:29.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:29.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:29.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:29.93#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:14:29.93#ibcon#first serial, iclass 11, count 0 2006.201.19:14:29.93#ibcon#enter sib2, iclass 11, count 0 2006.201.19:14:29.93#ibcon#flushed, iclass 11, count 0 2006.201.19:14:29.93#ibcon#about to write, iclass 11, count 0 2006.201.19:14:29.93#ibcon#wrote, iclass 11, count 0 2006.201.19:14:29.93#ibcon#about to read 3, iclass 11, count 0 2006.201.19:14:29.97#ibcon#read 3, iclass 11, count 0 2006.201.19:14:29.97#ibcon#about to read 4, iclass 11, count 0 2006.201.19:14:29.97#ibcon#read 4, iclass 11, count 0 2006.201.19:14:29.97#ibcon#about to read 5, iclass 11, count 0 2006.201.19:14:29.97#ibcon#read 5, iclass 11, count 0 2006.201.19:14:29.97#ibcon#about to read 6, iclass 11, count 0 2006.201.19:14:29.97#ibcon#read 6, iclass 11, count 0 2006.201.19:14:29.97#ibcon#end of sib2, iclass 11, count 0 2006.201.19:14:29.97#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:14:29.97#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:14:29.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:14:29.97#ibcon#*before write, iclass 11, count 0 2006.201.19:14:29.97#ibcon#enter sib2, iclass 11, count 0 2006.201.19:14:29.97#ibcon#flushed, iclass 11, count 0 2006.201.19:14:29.97#ibcon#about to write, iclass 11, count 0 2006.201.19:14:29.97#ibcon#wrote, iclass 11, count 0 2006.201.19:14:29.97#ibcon#about to read 3, iclass 11, count 0 2006.201.19:14:30.02#ibcon#read 3, iclass 11, count 0 2006.201.19:14:30.02#ibcon#about to read 4, iclass 11, count 0 2006.201.19:14:30.02#ibcon#read 4, iclass 11, count 0 2006.201.19:14:30.02#ibcon#about to read 5, iclass 11, count 0 2006.201.19:14:30.02#ibcon#read 5, iclass 11, count 0 2006.201.19:14:30.02#ibcon#about to read 6, iclass 11, count 0 2006.201.19:14:30.02#ibcon#read 6, iclass 11, count 0 2006.201.19:14:30.02#ibcon#end of sib2, iclass 11, count 0 2006.201.19:14:30.02#ibcon#*after write, iclass 11, count 0 2006.201.19:14:30.02#ibcon#*before return 0, iclass 11, count 0 2006.201.19:14:30.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:30.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:30.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:14:30.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:14:30.02$vck44/va=1,8 2006.201.19:14:30.02#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.19:14:30.02#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.19:14:30.02#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:30.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:30.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:30.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:30.02#ibcon#enter wrdev, iclass 13, count 2 2006.201.19:14:30.02#ibcon#first serial, iclass 13, count 2 2006.201.19:14:30.02#ibcon#enter sib2, iclass 13, count 2 2006.201.19:14:30.02#ibcon#flushed, iclass 13, count 2 2006.201.19:14:30.02#ibcon#about to write, iclass 13, count 2 2006.201.19:14:30.02#ibcon#wrote, iclass 13, count 2 2006.201.19:14:30.02#ibcon#about to read 3, iclass 13, count 2 2006.201.19:14:30.04#ibcon#read 3, iclass 13, count 2 2006.201.19:14:30.04#ibcon#about to read 4, iclass 13, count 2 2006.201.19:14:30.04#ibcon#read 4, iclass 13, count 2 2006.201.19:14:30.04#ibcon#about to read 5, iclass 13, count 2 2006.201.19:14:30.04#ibcon#read 5, iclass 13, count 2 2006.201.19:14:30.04#ibcon#about to read 6, iclass 13, count 2 2006.201.19:14:30.04#ibcon#read 6, iclass 13, count 2 2006.201.19:14:30.04#ibcon#end of sib2, iclass 13, count 2 2006.201.19:14:30.04#ibcon#*mode == 0, iclass 13, count 2 2006.201.19:14:30.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.19:14:30.04#ibcon#[25=AT01-08\r\n] 2006.201.19:14:30.04#ibcon#*before write, iclass 13, count 2 2006.201.19:14:30.04#ibcon#enter sib2, iclass 13, count 2 2006.201.19:14:30.04#ibcon#flushed, iclass 13, count 2 2006.201.19:14:30.04#ibcon#about to write, iclass 13, count 2 2006.201.19:14:30.04#ibcon#wrote, iclass 13, count 2 2006.201.19:14:30.04#ibcon#about to read 3, iclass 13, count 2 2006.201.19:14:30.07#ibcon#read 3, iclass 13, count 2 2006.201.19:14:30.07#ibcon#about to read 4, iclass 13, count 2 2006.201.19:14:30.07#ibcon#read 4, iclass 13, count 2 2006.201.19:14:30.07#ibcon#about to read 5, iclass 13, count 2 2006.201.19:14:30.07#ibcon#read 5, iclass 13, count 2 2006.201.19:14:30.07#ibcon#about to read 6, iclass 13, count 2 2006.201.19:14:30.07#ibcon#read 6, iclass 13, count 2 2006.201.19:14:30.07#ibcon#end of sib2, iclass 13, count 2 2006.201.19:14:30.07#ibcon#*after write, iclass 13, count 2 2006.201.19:14:30.07#ibcon#*before return 0, iclass 13, count 2 2006.201.19:14:30.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:30.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:30.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.19:14:30.07#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:30.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:30.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:30.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:30.19#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:14:30.19#ibcon#first serial, iclass 13, count 0 2006.201.19:14:30.19#ibcon#enter sib2, iclass 13, count 0 2006.201.19:14:30.19#ibcon#flushed, iclass 13, count 0 2006.201.19:14:30.19#ibcon#about to write, iclass 13, count 0 2006.201.19:14:30.19#ibcon#wrote, iclass 13, count 0 2006.201.19:14:30.19#ibcon#about to read 3, iclass 13, count 0 2006.201.19:14:30.21#ibcon#read 3, iclass 13, count 0 2006.201.19:14:30.21#ibcon#about to read 4, iclass 13, count 0 2006.201.19:14:30.21#ibcon#read 4, iclass 13, count 0 2006.201.19:14:30.21#ibcon#about to read 5, iclass 13, count 0 2006.201.19:14:30.21#ibcon#read 5, iclass 13, count 0 2006.201.19:14:30.21#ibcon#about to read 6, iclass 13, count 0 2006.201.19:14:30.21#ibcon#read 6, iclass 13, count 0 2006.201.19:14:30.21#ibcon#end of sib2, iclass 13, count 0 2006.201.19:14:30.21#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:14:30.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:14:30.21#ibcon#[25=USB\r\n] 2006.201.19:14:30.21#ibcon#*before write, iclass 13, count 0 2006.201.19:14:30.21#ibcon#enter sib2, iclass 13, count 0 2006.201.19:14:30.21#ibcon#flushed, iclass 13, count 0 2006.201.19:14:30.21#ibcon#about to write, iclass 13, count 0 2006.201.19:14:30.21#ibcon#wrote, iclass 13, count 0 2006.201.19:14:30.21#ibcon#about to read 3, iclass 13, count 0 2006.201.19:14:30.24#ibcon#read 3, iclass 13, count 0 2006.201.19:14:30.24#ibcon#about to read 4, iclass 13, count 0 2006.201.19:14:30.24#ibcon#read 4, iclass 13, count 0 2006.201.19:14:30.24#ibcon#about to read 5, iclass 13, count 0 2006.201.19:14:30.24#ibcon#read 5, iclass 13, count 0 2006.201.19:14:30.24#ibcon#about to read 6, iclass 13, count 0 2006.201.19:14:30.24#ibcon#read 6, iclass 13, count 0 2006.201.19:14:30.24#ibcon#end of sib2, iclass 13, count 0 2006.201.19:14:30.24#ibcon#*after write, iclass 13, count 0 2006.201.19:14:30.24#ibcon#*before return 0, iclass 13, count 0 2006.201.19:14:30.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:30.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:30.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:14:30.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:14:30.24$vck44/valo=2,534.99 2006.201.19:14:30.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.19:14:30.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.19:14:30.24#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:30.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:30.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:30.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:30.24#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:14:30.24#ibcon#first serial, iclass 15, count 0 2006.201.19:14:30.24#ibcon#enter sib2, iclass 15, count 0 2006.201.19:14:30.24#ibcon#flushed, iclass 15, count 0 2006.201.19:14:30.24#ibcon#about to write, iclass 15, count 0 2006.201.19:14:30.24#ibcon#wrote, iclass 15, count 0 2006.201.19:14:30.24#ibcon#about to read 3, iclass 15, count 0 2006.201.19:14:30.26#ibcon#read 3, iclass 15, count 0 2006.201.19:14:30.26#ibcon#about to read 4, iclass 15, count 0 2006.201.19:14:30.26#ibcon#read 4, iclass 15, count 0 2006.201.19:14:30.26#ibcon#about to read 5, iclass 15, count 0 2006.201.19:14:30.26#ibcon#read 5, iclass 15, count 0 2006.201.19:14:30.26#ibcon#about to read 6, iclass 15, count 0 2006.201.19:14:30.26#ibcon#read 6, iclass 15, count 0 2006.201.19:14:30.26#ibcon#end of sib2, iclass 15, count 0 2006.201.19:14:30.26#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:14:30.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:14:30.26#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:14:30.26#ibcon#*before write, iclass 15, count 0 2006.201.19:14:30.26#ibcon#enter sib2, iclass 15, count 0 2006.201.19:14:30.26#ibcon#flushed, iclass 15, count 0 2006.201.19:14:30.26#ibcon#about to write, iclass 15, count 0 2006.201.19:14:30.26#ibcon#wrote, iclass 15, count 0 2006.201.19:14:30.26#ibcon#about to read 3, iclass 15, count 0 2006.201.19:14:30.30#ibcon#read 3, iclass 15, count 0 2006.201.19:14:30.30#ibcon#about to read 4, iclass 15, count 0 2006.201.19:14:30.30#ibcon#read 4, iclass 15, count 0 2006.201.19:14:30.30#ibcon#about to read 5, iclass 15, count 0 2006.201.19:14:30.30#ibcon#read 5, iclass 15, count 0 2006.201.19:14:30.30#ibcon#about to read 6, iclass 15, count 0 2006.201.19:14:30.30#ibcon#read 6, iclass 15, count 0 2006.201.19:14:30.30#ibcon#end of sib2, iclass 15, count 0 2006.201.19:14:30.30#ibcon#*after write, iclass 15, count 0 2006.201.19:14:30.30#ibcon#*before return 0, iclass 15, count 0 2006.201.19:14:30.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:30.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:30.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:14:30.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:14:30.30$vck44/va=2,7 2006.201.19:14:30.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.19:14:30.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.19:14:30.30#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:30.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:30.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:30.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:30.36#ibcon#enter wrdev, iclass 17, count 2 2006.201.19:14:30.36#ibcon#first serial, iclass 17, count 2 2006.201.19:14:30.36#ibcon#enter sib2, iclass 17, count 2 2006.201.19:14:30.36#ibcon#flushed, iclass 17, count 2 2006.201.19:14:30.36#ibcon#about to write, iclass 17, count 2 2006.201.19:14:30.36#ibcon#wrote, iclass 17, count 2 2006.201.19:14:30.36#ibcon#about to read 3, iclass 17, count 2 2006.201.19:14:30.38#ibcon#read 3, iclass 17, count 2 2006.201.19:14:30.38#ibcon#about to read 4, iclass 17, count 2 2006.201.19:14:30.38#ibcon#read 4, iclass 17, count 2 2006.201.19:14:30.38#ibcon#about to read 5, iclass 17, count 2 2006.201.19:14:30.38#ibcon#read 5, iclass 17, count 2 2006.201.19:14:30.38#ibcon#about to read 6, iclass 17, count 2 2006.201.19:14:30.38#ibcon#read 6, iclass 17, count 2 2006.201.19:14:30.38#ibcon#end of sib2, iclass 17, count 2 2006.201.19:14:30.38#ibcon#*mode == 0, iclass 17, count 2 2006.201.19:14:30.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.19:14:30.38#ibcon#[25=AT02-07\r\n] 2006.201.19:14:30.38#ibcon#*before write, iclass 17, count 2 2006.201.19:14:30.38#ibcon#enter sib2, iclass 17, count 2 2006.201.19:14:30.38#ibcon#flushed, iclass 17, count 2 2006.201.19:14:30.38#ibcon#about to write, iclass 17, count 2 2006.201.19:14:30.38#ibcon#wrote, iclass 17, count 2 2006.201.19:14:30.38#ibcon#about to read 3, iclass 17, count 2 2006.201.19:14:30.41#ibcon#read 3, iclass 17, count 2 2006.201.19:14:30.41#ibcon#about to read 4, iclass 17, count 2 2006.201.19:14:30.41#ibcon#read 4, iclass 17, count 2 2006.201.19:14:30.41#ibcon#about to read 5, iclass 17, count 2 2006.201.19:14:30.41#ibcon#read 5, iclass 17, count 2 2006.201.19:14:30.41#ibcon#about to read 6, iclass 17, count 2 2006.201.19:14:30.41#ibcon#read 6, iclass 17, count 2 2006.201.19:14:30.41#ibcon#end of sib2, iclass 17, count 2 2006.201.19:14:30.41#ibcon#*after write, iclass 17, count 2 2006.201.19:14:30.41#ibcon#*before return 0, iclass 17, count 2 2006.201.19:14:30.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:30.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:30.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.19:14:30.41#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:30.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:30.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:30.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:30.53#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:14:30.53#ibcon#first serial, iclass 17, count 0 2006.201.19:14:30.53#ibcon#enter sib2, iclass 17, count 0 2006.201.19:14:30.53#ibcon#flushed, iclass 17, count 0 2006.201.19:14:30.53#ibcon#about to write, iclass 17, count 0 2006.201.19:14:30.53#ibcon#wrote, iclass 17, count 0 2006.201.19:14:30.53#ibcon#about to read 3, iclass 17, count 0 2006.201.19:14:30.55#ibcon#read 3, iclass 17, count 0 2006.201.19:14:30.55#ibcon#about to read 4, iclass 17, count 0 2006.201.19:14:30.55#ibcon#read 4, iclass 17, count 0 2006.201.19:14:30.55#ibcon#about to read 5, iclass 17, count 0 2006.201.19:14:30.55#ibcon#read 5, iclass 17, count 0 2006.201.19:14:30.55#ibcon#about to read 6, iclass 17, count 0 2006.201.19:14:30.55#ibcon#read 6, iclass 17, count 0 2006.201.19:14:30.55#ibcon#end of sib2, iclass 17, count 0 2006.201.19:14:30.55#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:14:30.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:14:30.55#ibcon#[25=USB\r\n] 2006.201.19:14:30.55#ibcon#*before write, iclass 17, count 0 2006.201.19:14:30.55#ibcon#enter sib2, iclass 17, count 0 2006.201.19:14:30.55#ibcon#flushed, iclass 17, count 0 2006.201.19:14:30.55#ibcon#about to write, iclass 17, count 0 2006.201.19:14:30.55#ibcon#wrote, iclass 17, count 0 2006.201.19:14:30.55#ibcon#about to read 3, iclass 17, count 0 2006.201.19:14:30.58#ibcon#read 3, iclass 17, count 0 2006.201.19:14:30.58#ibcon#about to read 4, iclass 17, count 0 2006.201.19:14:30.58#ibcon#read 4, iclass 17, count 0 2006.201.19:14:30.58#ibcon#about to read 5, iclass 17, count 0 2006.201.19:14:30.58#ibcon#read 5, iclass 17, count 0 2006.201.19:14:30.58#ibcon#about to read 6, iclass 17, count 0 2006.201.19:14:30.58#ibcon#read 6, iclass 17, count 0 2006.201.19:14:30.58#ibcon#end of sib2, iclass 17, count 0 2006.201.19:14:30.58#ibcon#*after write, iclass 17, count 0 2006.201.19:14:30.58#ibcon#*before return 0, iclass 17, count 0 2006.201.19:14:30.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:30.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:30.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:14:30.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:14:30.58$vck44/valo=3,564.99 2006.201.19:14:30.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.19:14:30.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.19:14:30.58#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:30.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:30.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:30.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:30.58#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:14:30.58#ibcon#first serial, iclass 19, count 0 2006.201.19:14:30.58#ibcon#enter sib2, iclass 19, count 0 2006.201.19:14:30.58#ibcon#flushed, iclass 19, count 0 2006.201.19:14:30.58#ibcon#about to write, iclass 19, count 0 2006.201.19:14:30.58#ibcon#wrote, iclass 19, count 0 2006.201.19:14:30.58#ibcon#about to read 3, iclass 19, count 0 2006.201.19:14:30.60#ibcon#read 3, iclass 19, count 0 2006.201.19:14:30.60#ibcon#about to read 4, iclass 19, count 0 2006.201.19:14:30.60#ibcon#read 4, iclass 19, count 0 2006.201.19:14:30.60#ibcon#about to read 5, iclass 19, count 0 2006.201.19:14:30.60#ibcon#read 5, iclass 19, count 0 2006.201.19:14:30.60#ibcon#about to read 6, iclass 19, count 0 2006.201.19:14:30.60#ibcon#read 6, iclass 19, count 0 2006.201.19:14:30.60#ibcon#end of sib2, iclass 19, count 0 2006.201.19:14:30.60#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:14:30.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:14:30.60#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:14:30.60#ibcon#*before write, iclass 19, count 0 2006.201.19:14:30.60#ibcon#enter sib2, iclass 19, count 0 2006.201.19:14:30.60#ibcon#flushed, iclass 19, count 0 2006.201.19:14:30.60#ibcon#about to write, iclass 19, count 0 2006.201.19:14:30.60#ibcon#wrote, iclass 19, count 0 2006.201.19:14:30.60#ibcon#about to read 3, iclass 19, count 0 2006.201.19:14:30.65#ibcon#read 3, iclass 19, count 0 2006.201.19:14:30.65#ibcon#about to read 4, iclass 19, count 0 2006.201.19:14:30.65#ibcon#read 4, iclass 19, count 0 2006.201.19:14:30.65#ibcon#about to read 5, iclass 19, count 0 2006.201.19:14:30.65#ibcon#read 5, iclass 19, count 0 2006.201.19:14:30.65#ibcon#about to read 6, iclass 19, count 0 2006.201.19:14:30.65#ibcon#read 6, iclass 19, count 0 2006.201.19:14:30.65#ibcon#end of sib2, iclass 19, count 0 2006.201.19:14:30.65#ibcon#*after write, iclass 19, count 0 2006.201.19:14:30.65#ibcon#*before return 0, iclass 19, count 0 2006.201.19:14:30.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:30.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:30.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:14:30.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:14:30.65$vck44/va=3,8 2006.201.19:14:30.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.19:14:30.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.19:14:30.65#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:30.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:30.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:30.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:30.70#ibcon#enter wrdev, iclass 21, count 2 2006.201.19:14:30.70#ibcon#first serial, iclass 21, count 2 2006.201.19:14:30.70#ibcon#enter sib2, iclass 21, count 2 2006.201.19:14:30.70#ibcon#flushed, iclass 21, count 2 2006.201.19:14:30.70#ibcon#about to write, iclass 21, count 2 2006.201.19:14:30.70#ibcon#wrote, iclass 21, count 2 2006.201.19:14:30.70#ibcon#about to read 3, iclass 21, count 2 2006.201.19:14:30.72#ibcon#read 3, iclass 21, count 2 2006.201.19:14:30.72#ibcon#about to read 4, iclass 21, count 2 2006.201.19:14:30.72#ibcon#read 4, iclass 21, count 2 2006.201.19:14:30.72#ibcon#about to read 5, iclass 21, count 2 2006.201.19:14:30.72#ibcon#read 5, iclass 21, count 2 2006.201.19:14:30.72#ibcon#about to read 6, iclass 21, count 2 2006.201.19:14:30.72#ibcon#read 6, iclass 21, count 2 2006.201.19:14:30.72#ibcon#end of sib2, iclass 21, count 2 2006.201.19:14:30.72#ibcon#*mode == 0, iclass 21, count 2 2006.201.19:14:30.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.19:14:30.72#ibcon#[25=AT03-08\r\n] 2006.201.19:14:30.72#ibcon#*before write, iclass 21, count 2 2006.201.19:14:30.72#ibcon#enter sib2, iclass 21, count 2 2006.201.19:14:30.72#ibcon#flushed, iclass 21, count 2 2006.201.19:14:30.72#ibcon#about to write, iclass 21, count 2 2006.201.19:14:30.72#ibcon#wrote, iclass 21, count 2 2006.201.19:14:30.72#ibcon#about to read 3, iclass 21, count 2 2006.201.19:14:30.75#ibcon#read 3, iclass 21, count 2 2006.201.19:14:30.75#ibcon#about to read 4, iclass 21, count 2 2006.201.19:14:30.75#ibcon#read 4, iclass 21, count 2 2006.201.19:14:30.75#ibcon#about to read 5, iclass 21, count 2 2006.201.19:14:30.75#ibcon#read 5, iclass 21, count 2 2006.201.19:14:30.75#ibcon#about to read 6, iclass 21, count 2 2006.201.19:14:30.75#ibcon#read 6, iclass 21, count 2 2006.201.19:14:30.75#ibcon#end of sib2, iclass 21, count 2 2006.201.19:14:30.75#ibcon#*after write, iclass 21, count 2 2006.201.19:14:30.75#ibcon#*before return 0, iclass 21, count 2 2006.201.19:14:30.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:30.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:30.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.19:14:30.75#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:30.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:30.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:30.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:30.87#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:14:30.87#ibcon#first serial, iclass 21, count 0 2006.201.19:14:30.87#ibcon#enter sib2, iclass 21, count 0 2006.201.19:14:30.87#ibcon#flushed, iclass 21, count 0 2006.201.19:14:30.87#ibcon#about to write, iclass 21, count 0 2006.201.19:14:30.87#ibcon#wrote, iclass 21, count 0 2006.201.19:14:30.87#ibcon#about to read 3, iclass 21, count 0 2006.201.19:14:30.89#ibcon#read 3, iclass 21, count 0 2006.201.19:14:30.89#ibcon#about to read 4, iclass 21, count 0 2006.201.19:14:30.89#ibcon#read 4, iclass 21, count 0 2006.201.19:14:30.89#ibcon#about to read 5, iclass 21, count 0 2006.201.19:14:30.89#ibcon#read 5, iclass 21, count 0 2006.201.19:14:30.89#ibcon#about to read 6, iclass 21, count 0 2006.201.19:14:30.89#ibcon#read 6, iclass 21, count 0 2006.201.19:14:30.89#ibcon#end of sib2, iclass 21, count 0 2006.201.19:14:30.89#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:14:30.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:14:30.89#ibcon#[25=USB\r\n] 2006.201.19:14:30.89#ibcon#*before write, iclass 21, count 0 2006.201.19:14:30.89#ibcon#enter sib2, iclass 21, count 0 2006.201.19:14:30.89#ibcon#flushed, iclass 21, count 0 2006.201.19:14:30.89#ibcon#about to write, iclass 21, count 0 2006.201.19:14:30.89#ibcon#wrote, iclass 21, count 0 2006.201.19:14:30.89#ibcon#about to read 3, iclass 21, count 0 2006.201.19:14:30.92#ibcon#read 3, iclass 21, count 0 2006.201.19:14:30.92#ibcon#about to read 4, iclass 21, count 0 2006.201.19:14:30.92#ibcon#read 4, iclass 21, count 0 2006.201.19:14:30.92#ibcon#about to read 5, iclass 21, count 0 2006.201.19:14:30.92#ibcon#read 5, iclass 21, count 0 2006.201.19:14:30.92#ibcon#about to read 6, iclass 21, count 0 2006.201.19:14:30.92#ibcon#read 6, iclass 21, count 0 2006.201.19:14:30.92#ibcon#end of sib2, iclass 21, count 0 2006.201.19:14:30.92#ibcon#*after write, iclass 21, count 0 2006.201.19:14:30.92#ibcon#*before return 0, iclass 21, count 0 2006.201.19:14:30.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:30.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:30.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:14:30.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:14:30.92$vck44/valo=4,624.99 2006.201.19:14:30.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.19:14:30.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.19:14:30.92#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:30.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:30.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:30.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:30.92#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:14:30.92#ibcon#first serial, iclass 23, count 0 2006.201.19:14:30.92#ibcon#enter sib2, iclass 23, count 0 2006.201.19:14:30.92#ibcon#flushed, iclass 23, count 0 2006.201.19:14:30.92#ibcon#about to write, iclass 23, count 0 2006.201.19:14:30.92#ibcon#wrote, iclass 23, count 0 2006.201.19:14:30.92#ibcon#about to read 3, iclass 23, count 0 2006.201.19:14:30.94#ibcon#read 3, iclass 23, count 0 2006.201.19:14:30.94#ibcon#about to read 4, iclass 23, count 0 2006.201.19:14:30.94#ibcon#read 4, iclass 23, count 0 2006.201.19:14:30.94#ibcon#about to read 5, iclass 23, count 0 2006.201.19:14:30.94#ibcon#read 5, iclass 23, count 0 2006.201.19:14:30.94#ibcon#about to read 6, iclass 23, count 0 2006.201.19:14:30.94#ibcon#read 6, iclass 23, count 0 2006.201.19:14:30.94#ibcon#end of sib2, iclass 23, count 0 2006.201.19:14:30.94#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:14:30.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:14:30.94#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:14:30.94#ibcon#*before write, iclass 23, count 0 2006.201.19:14:30.94#ibcon#enter sib2, iclass 23, count 0 2006.201.19:14:30.94#ibcon#flushed, iclass 23, count 0 2006.201.19:14:30.94#ibcon#about to write, iclass 23, count 0 2006.201.19:14:30.94#ibcon#wrote, iclass 23, count 0 2006.201.19:14:30.94#ibcon#about to read 3, iclass 23, count 0 2006.201.19:14:30.98#ibcon#read 3, iclass 23, count 0 2006.201.19:14:30.98#ibcon#about to read 4, iclass 23, count 0 2006.201.19:14:30.98#ibcon#read 4, iclass 23, count 0 2006.201.19:14:30.98#ibcon#about to read 5, iclass 23, count 0 2006.201.19:14:30.98#ibcon#read 5, iclass 23, count 0 2006.201.19:14:30.98#ibcon#about to read 6, iclass 23, count 0 2006.201.19:14:30.98#ibcon#read 6, iclass 23, count 0 2006.201.19:14:30.98#ibcon#end of sib2, iclass 23, count 0 2006.201.19:14:30.98#ibcon#*after write, iclass 23, count 0 2006.201.19:14:30.98#ibcon#*before return 0, iclass 23, count 0 2006.201.19:14:30.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:30.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:30.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:14:30.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:14:30.98$vck44/va=4,7 2006.201.19:14:30.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.19:14:30.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.19:14:30.98#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:30.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:31.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:31.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:31.04#ibcon#enter wrdev, iclass 25, count 2 2006.201.19:14:31.04#ibcon#first serial, iclass 25, count 2 2006.201.19:14:31.04#ibcon#enter sib2, iclass 25, count 2 2006.201.19:14:31.04#ibcon#flushed, iclass 25, count 2 2006.201.19:14:31.04#ibcon#about to write, iclass 25, count 2 2006.201.19:14:31.04#ibcon#wrote, iclass 25, count 2 2006.201.19:14:31.04#ibcon#about to read 3, iclass 25, count 2 2006.201.19:14:31.06#ibcon#read 3, iclass 25, count 2 2006.201.19:14:31.06#ibcon#about to read 4, iclass 25, count 2 2006.201.19:14:31.06#ibcon#read 4, iclass 25, count 2 2006.201.19:14:31.06#ibcon#about to read 5, iclass 25, count 2 2006.201.19:14:31.06#ibcon#read 5, iclass 25, count 2 2006.201.19:14:31.06#ibcon#about to read 6, iclass 25, count 2 2006.201.19:14:31.06#ibcon#read 6, iclass 25, count 2 2006.201.19:14:31.06#ibcon#end of sib2, iclass 25, count 2 2006.201.19:14:31.06#ibcon#*mode == 0, iclass 25, count 2 2006.201.19:14:31.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.19:14:31.06#ibcon#[25=AT04-07\r\n] 2006.201.19:14:31.06#ibcon#*before write, iclass 25, count 2 2006.201.19:14:31.06#ibcon#enter sib2, iclass 25, count 2 2006.201.19:14:31.06#ibcon#flushed, iclass 25, count 2 2006.201.19:14:31.06#ibcon#about to write, iclass 25, count 2 2006.201.19:14:31.06#ibcon#wrote, iclass 25, count 2 2006.201.19:14:31.06#ibcon#about to read 3, iclass 25, count 2 2006.201.19:14:31.09#ibcon#read 3, iclass 25, count 2 2006.201.19:14:31.09#ibcon#about to read 4, iclass 25, count 2 2006.201.19:14:31.09#ibcon#read 4, iclass 25, count 2 2006.201.19:14:31.09#ibcon#about to read 5, iclass 25, count 2 2006.201.19:14:31.09#ibcon#read 5, iclass 25, count 2 2006.201.19:14:31.09#ibcon#about to read 6, iclass 25, count 2 2006.201.19:14:31.09#ibcon#read 6, iclass 25, count 2 2006.201.19:14:31.09#ibcon#end of sib2, iclass 25, count 2 2006.201.19:14:31.09#ibcon#*after write, iclass 25, count 2 2006.201.19:14:31.09#ibcon#*before return 0, iclass 25, count 2 2006.201.19:14:31.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:31.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:31.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.19:14:31.09#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:31.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:31.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:31.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:31.21#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:14:31.21#ibcon#first serial, iclass 25, count 0 2006.201.19:14:31.21#ibcon#enter sib2, iclass 25, count 0 2006.201.19:14:31.21#ibcon#flushed, iclass 25, count 0 2006.201.19:14:31.21#ibcon#about to write, iclass 25, count 0 2006.201.19:14:31.21#ibcon#wrote, iclass 25, count 0 2006.201.19:14:31.21#ibcon#about to read 3, iclass 25, count 0 2006.201.19:14:31.23#ibcon#read 3, iclass 25, count 0 2006.201.19:14:31.23#ibcon#about to read 4, iclass 25, count 0 2006.201.19:14:31.23#ibcon#read 4, iclass 25, count 0 2006.201.19:14:31.23#ibcon#about to read 5, iclass 25, count 0 2006.201.19:14:31.23#ibcon#read 5, iclass 25, count 0 2006.201.19:14:31.23#ibcon#about to read 6, iclass 25, count 0 2006.201.19:14:31.23#ibcon#read 6, iclass 25, count 0 2006.201.19:14:31.23#ibcon#end of sib2, iclass 25, count 0 2006.201.19:14:31.23#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:14:31.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:14:31.23#ibcon#[25=USB\r\n] 2006.201.19:14:31.23#ibcon#*before write, iclass 25, count 0 2006.201.19:14:31.23#ibcon#enter sib2, iclass 25, count 0 2006.201.19:14:31.23#ibcon#flushed, iclass 25, count 0 2006.201.19:14:31.23#ibcon#about to write, iclass 25, count 0 2006.201.19:14:31.23#ibcon#wrote, iclass 25, count 0 2006.201.19:14:31.23#ibcon#about to read 3, iclass 25, count 0 2006.201.19:14:31.26#ibcon#read 3, iclass 25, count 0 2006.201.19:14:31.26#ibcon#about to read 4, iclass 25, count 0 2006.201.19:14:31.26#ibcon#read 4, iclass 25, count 0 2006.201.19:14:31.26#ibcon#about to read 5, iclass 25, count 0 2006.201.19:14:31.26#ibcon#read 5, iclass 25, count 0 2006.201.19:14:31.26#ibcon#about to read 6, iclass 25, count 0 2006.201.19:14:31.26#ibcon#read 6, iclass 25, count 0 2006.201.19:14:31.26#ibcon#end of sib2, iclass 25, count 0 2006.201.19:14:31.26#ibcon#*after write, iclass 25, count 0 2006.201.19:14:31.26#ibcon#*before return 0, iclass 25, count 0 2006.201.19:14:31.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:31.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:31.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:14:31.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:14:31.26$vck44/valo=5,734.99 2006.201.19:14:31.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.19:14:31.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.19:14:31.26#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:31.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:31.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:31.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:31.26#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:14:31.26#ibcon#first serial, iclass 27, count 0 2006.201.19:14:31.26#ibcon#enter sib2, iclass 27, count 0 2006.201.19:14:31.26#ibcon#flushed, iclass 27, count 0 2006.201.19:14:31.26#ibcon#about to write, iclass 27, count 0 2006.201.19:14:31.26#ibcon#wrote, iclass 27, count 0 2006.201.19:14:31.26#ibcon#about to read 3, iclass 27, count 0 2006.201.19:14:31.28#ibcon#read 3, iclass 27, count 0 2006.201.19:14:31.28#ibcon#about to read 4, iclass 27, count 0 2006.201.19:14:31.28#ibcon#read 4, iclass 27, count 0 2006.201.19:14:31.28#ibcon#about to read 5, iclass 27, count 0 2006.201.19:14:31.28#ibcon#read 5, iclass 27, count 0 2006.201.19:14:31.28#ibcon#about to read 6, iclass 27, count 0 2006.201.19:14:31.28#ibcon#read 6, iclass 27, count 0 2006.201.19:14:31.28#ibcon#end of sib2, iclass 27, count 0 2006.201.19:14:31.28#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:14:31.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:14:31.28#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:14:31.28#ibcon#*before write, iclass 27, count 0 2006.201.19:14:31.28#ibcon#enter sib2, iclass 27, count 0 2006.201.19:14:31.28#ibcon#flushed, iclass 27, count 0 2006.201.19:14:31.28#ibcon#about to write, iclass 27, count 0 2006.201.19:14:31.28#ibcon#wrote, iclass 27, count 0 2006.201.19:14:31.28#ibcon#about to read 3, iclass 27, count 0 2006.201.19:14:31.32#ibcon#read 3, iclass 27, count 0 2006.201.19:14:31.32#ibcon#about to read 4, iclass 27, count 0 2006.201.19:14:31.32#ibcon#read 4, iclass 27, count 0 2006.201.19:14:31.32#ibcon#about to read 5, iclass 27, count 0 2006.201.19:14:31.32#ibcon#read 5, iclass 27, count 0 2006.201.19:14:31.32#ibcon#about to read 6, iclass 27, count 0 2006.201.19:14:31.32#ibcon#read 6, iclass 27, count 0 2006.201.19:14:31.32#ibcon#end of sib2, iclass 27, count 0 2006.201.19:14:31.32#ibcon#*after write, iclass 27, count 0 2006.201.19:14:31.32#ibcon#*before return 0, iclass 27, count 0 2006.201.19:14:31.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:31.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:31.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:14:31.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:14:31.32$vck44/va=5,4 2006.201.19:14:31.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.19:14:31.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.19:14:31.32#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:31.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:31.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:31.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:31.38#ibcon#enter wrdev, iclass 29, count 2 2006.201.19:14:31.38#ibcon#first serial, iclass 29, count 2 2006.201.19:14:31.38#ibcon#enter sib2, iclass 29, count 2 2006.201.19:14:31.38#ibcon#flushed, iclass 29, count 2 2006.201.19:14:31.38#ibcon#about to write, iclass 29, count 2 2006.201.19:14:31.38#ibcon#wrote, iclass 29, count 2 2006.201.19:14:31.38#ibcon#about to read 3, iclass 29, count 2 2006.201.19:14:31.40#ibcon#read 3, iclass 29, count 2 2006.201.19:14:31.40#ibcon#about to read 4, iclass 29, count 2 2006.201.19:14:31.40#ibcon#read 4, iclass 29, count 2 2006.201.19:14:31.40#ibcon#about to read 5, iclass 29, count 2 2006.201.19:14:31.40#ibcon#read 5, iclass 29, count 2 2006.201.19:14:31.40#ibcon#about to read 6, iclass 29, count 2 2006.201.19:14:31.40#ibcon#read 6, iclass 29, count 2 2006.201.19:14:31.40#ibcon#end of sib2, iclass 29, count 2 2006.201.19:14:31.40#ibcon#*mode == 0, iclass 29, count 2 2006.201.19:14:31.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.19:14:31.40#ibcon#[25=AT05-04\r\n] 2006.201.19:14:31.40#ibcon#*before write, iclass 29, count 2 2006.201.19:14:31.40#ibcon#enter sib2, iclass 29, count 2 2006.201.19:14:31.40#ibcon#flushed, iclass 29, count 2 2006.201.19:14:31.40#ibcon#about to write, iclass 29, count 2 2006.201.19:14:31.40#ibcon#wrote, iclass 29, count 2 2006.201.19:14:31.40#ibcon#about to read 3, iclass 29, count 2 2006.201.19:14:31.43#ibcon#read 3, iclass 29, count 2 2006.201.19:14:31.43#ibcon#about to read 4, iclass 29, count 2 2006.201.19:14:31.43#ibcon#read 4, iclass 29, count 2 2006.201.19:14:31.43#ibcon#about to read 5, iclass 29, count 2 2006.201.19:14:31.43#ibcon#read 5, iclass 29, count 2 2006.201.19:14:31.43#ibcon#about to read 6, iclass 29, count 2 2006.201.19:14:31.43#ibcon#read 6, iclass 29, count 2 2006.201.19:14:31.43#ibcon#end of sib2, iclass 29, count 2 2006.201.19:14:31.43#ibcon#*after write, iclass 29, count 2 2006.201.19:14:31.43#ibcon#*before return 0, iclass 29, count 2 2006.201.19:14:31.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:31.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:31.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.19:14:31.43#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:31.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:31.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:31.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:31.55#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:14:31.55#ibcon#first serial, iclass 29, count 0 2006.201.19:14:31.55#ibcon#enter sib2, iclass 29, count 0 2006.201.19:14:31.55#ibcon#flushed, iclass 29, count 0 2006.201.19:14:31.55#ibcon#about to write, iclass 29, count 0 2006.201.19:14:31.55#ibcon#wrote, iclass 29, count 0 2006.201.19:14:31.55#ibcon#about to read 3, iclass 29, count 0 2006.201.19:14:31.57#ibcon#read 3, iclass 29, count 0 2006.201.19:14:31.57#ibcon#about to read 4, iclass 29, count 0 2006.201.19:14:31.57#ibcon#read 4, iclass 29, count 0 2006.201.19:14:31.57#ibcon#about to read 5, iclass 29, count 0 2006.201.19:14:31.57#ibcon#read 5, iclass 29, count 0 2006.201.19:14:31.57#ibcon#about to read 6, iclass 29, count 0 2006.201.19:14:31.57#ibcon#read 6, iclass 29, count 0 2006.201.19:14:31.57#ibcon#end of sib2, iclass 29, count 0 2006.201.19:14:31.57#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:14:31.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:14:31.57#ibcon#[25=USB\r\n] 2006.201.19:14:31.57#ibcon#*before write, iclass 29, count 0 2006.201.19:14:31.57#ibcon#enter sib2, iclass 29, count 0 2006.201.19:14:31.57#ibcon#flushed, iclass 29, count 0 2006.201.19:14:31.57#ibcon#about to write, iclass 29, count 0 2006.201.19:14:31.57#ibcon#wrote, iclass 29, count 0 2006.201.19:14:31.57#ibcon#about to read 3, iclass 29, count 0 2006.201.19:14:31.60#ibcon#read 3, iclass 29, count 0 2006.201.19:14:31.60#ibcon#about to read 4, iclass 29, count 0 2006.201.19:14:31.60#ibcon#read 4, iclass 29, count 0 2006.201.19:14:31.60#ibcon#about to read 5, iclass 29, count 0 2006.201.19:14:31.60#ibcon#read 5, iclass 29, count 0 2006.201.19:14:31.60#ibcon#about to read 6, iclass 29, count 0 2006.201.19:14:31.60#ibcon#read 6, iclass 29, count 0 2006.201.19:14:31.60#ibcon#end of sib2, iclass 29, count 0 2006.201.19:14:31.60#ibcon#*after write, iclass 29, count 0 2006.201.19:14:31.60#ibcon#*before return 0, iclass 29, count 0 2006.201.19:14:31.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:31.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:31.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:14:31.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:14:31.60$vck44/valo=6,814.99 2006.201.19:14:31.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.19:14:31.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.19:14:31.60#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:31.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:31.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:31.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:31.60#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:14:31.60#ibcon#first serial, iclass 31, count 0 2006.201.19:14:31.60#ibcon#enter sib2, iclass 31, count 0 2006.201.19:14:31.60#ibcon#flushed, iclass 31, count 0 2006.201.19:14:31.60#ibcon#about to write, iclass 31, count 0 2006.201.19:14:31.60#ibcon#wrote, iclass 31, count 0 2006.201.19:14:31.60#ibcon#about to read 3, iclass 31, count 0 2006.201.19:14:31.62#ibcon#read 3, iclass 31, count 0 2006.201.19:14:31.62#ibcon#about to read 4, iclass 31, count 0 2006.201.19:14:31.62#ibcon#read 4, iclass 31, count 0 2006.201.19:14:31.62#ibcon#about to read 5, iclass 31, count 0 2006.201.19:14:31.62#ibcon#read 5, iclass 31, count 0 2006.201.19:14:31.62#ibcon#about to read 6, iclass 31, count 0 2006.201.19:14:31.62#ibcon#read 6, iclass 31, count 0 2006.201.19:14:31.62#ibcon#end of sib2, iclass 31, count 0 2006.201.19:14:31.62#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:14:31.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:14:31.62#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:14:31.62#ibcon#*before write, iclass 31, count 0 2006.201.19:14:31.62#ibcon#enter sib2, iclass 31, count 0 2006.201.19:14:31.62#ibcon#flushed, iclass 31, count 0 2006.201.19:14:31.62#ibcon#about to write, iclass 31, count 0 2006.201.19:14:31.62#ibcon#wrote, iclass 31, count 0 2006.201.19:14:31.62#ibcon#about to read 3, iclass 31, count 0 2006.201.19:14:31.67#ibcon#read 3, iclass 31, count 0 2006.201.19:14:31.67#ibcon#about to read 4, iclass 31, count 0 2006.201.19:14:31.67#ibcon#read 4, iclass 31, count 0 2006.201.19:14:31.67#ibcon#about to read 5, iclass 31, count 0 2006.201.19:14:31.67#ibcon#read 5, iclass 31, count 0 2006.201.19:14:31.67#ibcon#about to read 6, iclass 31, count 0 2006.201.19:14:31.67#ibcon#read 6, iclass 31, count 0 2006.201.19:14:31.67#ibcon#end of sib2, iclass 31, count 0 2006.201.19:14:31.67#ibcon#*after write, iclass 31, count 0 2006.201.19:14:31.67#ibcon#*before return 0, iclass 31, count 0 2006.201.19:14:31.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:31.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:31.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:14:31.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:14:31.67$vck44/va=6,5 2006.201.19:14:31.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.19:14:31.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.19:14:31.67#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:31.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:31.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:31.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:31.72#ibcon#enter wrdev, iclass 33, count 2 2006.201.19:14:31.72#ibcon#first serial, iclass 33, count 2 2006.201.19:14:31.72#ibcon#enter sib2, iclass 33, count 2 2006.201.19:14:31.72#ibcon#flushed, iclass 33, count 2 2006.201.19:14:31.72#ibcon#about to write, iclass 33, count 2 2006.201.19:14:31.72#ibcon#wrote, iclass 33, count 2 2006.201.19:14:31.72#ibcon#about to read 3, iclass 33, count 2 2006.201.19:14:31.74#ibcon#read 3, iclass 33, count 2 2006.201.19:14:31.74#ibcon#about to read 4, iclass 33, count 2 2006.201.19:14:31.74#ibcon#read 4, iclass 33, count 2 2006.201.19:14:31.74#ibcon#about to read 5, iclass 33, count 2 2006.201.19:14:31.74#ibcon#read 5, iclass 33, count 2 2006.201.19:14:31.74#ibcon#about to read 6, iclass 33, count 2 2006.201.19:14:31.74#ibcon#read 6, iclass 33, count 2 2006.201.19:14:31.74#ibcon#end of sib2, iclass 33, count 2 2006.201.19:14:31.74#ibcon#*mode == 0, iclass 33, count 2 2006.201.19:14:31.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.19:14:31.74#ibcon#[25=AT06-05\r\n] 2006.201.19:14:31.74#ibcon#*before write, iclass 33, count 2 2006.201.19:14:31.74#ibcon#enter sib2, iclass 33, count 2 2006.201.19:14:31.74#ibcon#flushed, iclass 33, count 2 2006.201.19:14:31.74#ibcon#about to write, iclass 33, count 2 2006.201.19:14:31.74#ibcon#wrote, iclass 33, count 2 2006.201.19:14:31.74#ibcon#about to read 3, iclass 33, count 2 2006.201.19:14:31.77#ibcon#read 3, iclass 33, count 2 2006.201.19:14:31.77#ibcon#about to read 4, iclass 33, count 2 2006.201.19:14:31.77#ibcon#read 4, iclass 33, count 2 2006.201.19:14:31.77#ibcon#about to read 5, iclass 33, count 2 2006.201.19:14:31.77#ibcon#read 5, iclass 33, count 2 2006.201.19:14:31.77#ibcon#about to read 6, iclass 33, count 2 2006.201.19:14:31.77#ibcon#read 6, iclass 33, count 2 2006.201.19:14:31.77#ibcon#end of sib2, iclass 33, count 2 2006.201.19:14:31.77#ibcon#*after write, iclass 33, count 2 2006.201.19:14:31.77#ibcon#*before return 0, iclass 33, count 2 2006.201.19:14:31.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:31.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:31.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.19:14:31.77#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:31.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:31.78#abcon#<5=/04 0.9 2.4 20.501001002.3\r\n> 2006.201.19:14:31.80#abcon#{5=INTERFACE CLEAR} 2006.201.19:14:31.86#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:14:31.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:31.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:31.89#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:14:31.89#ibcon#first serial, iclass 33, count 0 2006.201.19:14:31.89#ibcon#enter sib2, iclass 33, count 0 2006.201.19:14:31.89#ibcon#flushed, iclass 33, count 0 2006.201.19:14:31.89#ibcon#about to write, iclass 33, count 0 2006.201.19:14:31.89#ibcon#wrote, iclass 33, count 0 2006.201.19:14:31.89#ibcon#about to read 3, iclass 33, count 0 2006.201.19:14:31.91#ibcon#read 3, iclass 33, count 0 2006.201.19:14:31.91#ibcon#about to read 4, iclass 33, count 0 2006.201.19:14:31.91#ibcon#read 4, iclass 33, count 0 2006.201.19:14:31.91#ibcon#about to read 5, iclass 33, count 0 2006.201.19:14:31.91#ibcon#read 5, iclass 33, count 0 2006.201.19:14:31.91#ibcon#about to read 6, iclass 33, count 0 2006.201.19:14:31.91#ibcon#read 6, iclass 33, count 0 2006.201.19:14:31.91#ibcon#end of sib2, iclass 33, count 0 2006.201.19:14:31.91#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:14:31.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:14:31.91#ibcon#[25=USB\r\n] 2006.201.19:14:31.91#ibcon#*before write, iclass 33, count 0 2006.201.19:14:31.91#ibcon#enter sib2, iclass 33, count 0 2006.201.19:14:31.91#ibcon#flushed, iclass 33, count 0 2006.201.19:14:31.91#ibcon#about to write, iclass 33, count 0 2006.201.19:14:31.91#ibcon#wrote, iclass 33, count 0 2006.201.19:14:31.91#ibcon#about to read 3, iclass 33, count 0 2006.201.19:14:31.94#ibcon#read 3, iclass 33, count 0 2006.201.19:14:31.94#ibcon#about to read 4, iclass 33, count 0 2006.201.19:14:31.94#ibcon#read 4, iclass 33, count 0 2006.201.19:14:31.94#ibcon#about to read 5, iclass 33, count 0 2006.201.19:14:31.94#ibcon#read 5, iclass 33, count 0 2006.201.19:14:31.94#ibcon#about to read 6, iclass 33, count 0 2006.201.19:14:31.94#ibcon#read 6, iclass 33, count 0 2006.201.19:14:31.94#ibcon#end of sib2, iclass 33, count 0 2006.201.19:14:31.94#ibcon#*after write, iclass 33, count 0 2006.201.19:14:31.94#ibcon#*before return 0, iclass 33, count 0 2006.201.19:14:31.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:31.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:31.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:14:31.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:14:31.94$vck44/valo=7,864.99 2006.201.19:14:31.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.19:14:31.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.19:14:31.94#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:31.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:31.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:31.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:31.94#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:14:31.94#ibcon#first serial, iclass 39, count 0 2006.201.19:14:31.94#ibcon#enter sib2, iclass 39, count 0 2006.201.19:14:31.94#ibcon#flushed, iclass 39, count 0 2006.201.19:14:31.94#ibcon#about to write, iclass 39, count 0 2006.201.19:14:31.94#ibcon#wrote, iclass 39, count 0 2006.201.19:14:31.94#ibcon#about to read 3, iclass 39, count 0 2006.201.19:14:31.96#ibcon#read 3, iclass 39, count 0 2006.201.19:14:31.96#ibcon#about to read 4, iclass 39, count 0 2006.201.19:14:31.96#ibcon#read 4, iclass 39, count 0 2006.201.19:14:31.96#ibcon#about to read 5, iclass 39, count 0 2006.201.19:14:31.96#ibcon#read 5, iclass 39, count 0 2006.201.19:14:31.96#ibcon#about to read 6, iclass 39, count 0 2006.201.19:14:31.96#ibcon#read 6, iclass 39, count 0 2006.201.19:14:31.96#ibcon#end of sib2, iclass 39, count 0 2006.201.19:14:31.96#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:14:31.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:14:31.96#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:14:31.96#ibcon#*before write, iclass 39, count 0 2006.201.19:14:31.96#ibcon#enter sib2, iclass 39, count 0 2006.201.19:14:31.96#ibcon#flushed, iclass 39, count 0 2006.201.19:14:31.96#ibcon#about to write, iclass 39, count 0 2006.201.19:14:31.96#ibcon#wrote, iclass 39, count 0 2006.201.19:14:31.96#ibcon#about to read 3, iclass 39, count 0 2006.201.19:14:32.00#ibcon#read 3, iclass 39, count 0 2006.201.19:14:32.00#ibcon#about to read 4, iclass 39, count 0 2006.201.19:14:32.00#ibcon#read 4, iclass 39, count 0 2006.201.19:14:32.00#ibcon#about to read 5, iclass 39, count 0 2006.201.19:14:32.00#ibcon#read 5, iclass 39, count 0 2006.201.19:14:32.00#ibcon#about to read 6, iclass 39, count 0 2006.201.19:14:32.00#ibcon#read 6, iclass 39, count 0 2006.201.19:14:32.00#ibcon#end of sib2, iclass 39, count 0 2006.201.19:14:32.00#ibcon#*after write, iclass 39, count 0 2006.201.19:14:32.00#ibcon#*before return 0, iclass 39, count 0 2006.201.19:14:32.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:32.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:32.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:14:32.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:14:32.00$vck44/va=7,5 2006.201.19:14:32.00#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.19:14:32.00#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.19:14:32.00#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:32.00#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:32.06#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:32.06#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:32.06#ibcon#enter wrdev, iclass 2, count 2 2006.201.19:14:32.06#ibcon#first serial, iclass 2, count 2 2006.201.19:14:32.06#ibcon#enter sib2, iclass 2, count 2 2006.201.19:14:32.06#ibcon#flushed, iclass 2, count 2 2006.201.19:14:32.06#ibcon#about to write, iclass 2, count 2 2006.201.19:14:32.06#ibcon#wrote, iclass 2, count 2 2006.201.19:14:32.06#ibcon#about to read 3, iclass 2, count 2 2006.201.19:14:32.08#ibcon#read 3, iclass 2, count 2 2006.201.19:14:32.08#ibcon#about to read 4, iclass 2, count 2 2006.201.19:14:32.08#ibcon#read 4, iclass 2, count 2 2006.201.19:14:32.08#ibcon#about to read 5, iclass 2, count 2 2006.201.19:14:32.08#ibcon#read 5, iclass 2, count 2 2006.201.19:14:32.08#ibcon#about to read 6, iclass 2, count 2 2006.201.19:14:32.08#ibcon#read 6, iclass 2, count 2 2006.201.19:14:32.08#ibcon#end of sib2, iclass 2, count 2 2006.201.19:14:32.08#ibcon#*mode == 0, iclass 2, count 2 2006.201.19:14:32.08#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.19:14:32.08#ibcon#[25=AT07-05\r\n] 2006.201.19:14:32.08#ibcon#*before write, iclass 2, count 2 2006.201.19:14:32.08#ibcon#enter sib2, iclass 2, count 2 2006.201.19:14:32.08#ibcon#flushed, iclass 2, count 2 2006.201.19:14:32.08#ibcon#about to write, iclass 2, count 2 2006.201.19:14:32.08#ibcon#wrote, iclass 2, count 2 2006.201.19:14:32.08#ibcon#about to read 3, iclass 2, count 2 2006.201.19:14:32.11#ibcon#read 3, iclass 2, count 2 2006.201.19:14:32.11#ibcon#about to read 4, iclass 2, count 2 2006.201.19:14:32.11#ibcon#read 4, iclass 2, count 2 2006.201.19:14:32.11#ibcon#about to read 5, iclass 2, count 2 2006.201.19:14:32.11#ibcon#read 5, iclass 2, count 2 2006.201.19:14:32.11#ibcon#about to read 6, iclass 2, count 2 2006.201.19:14:32.11#ibcon#read 6, iclass 2, count 2 2006.201.19:14:32.11#ibcon#end of sib2, iclass 2, count 2 2006.201.19:14:32.11#ibcon#*after write, iclass 2, count 2 2006.201.19:14:32.11#ibcon#*before return 0, iclass 2, count 2 2006.201.19:14:32.11#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:32.11#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:32.11#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.19:14:32.11#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:32.11#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:32.23#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:32.23#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:32.23#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:14:32.23#ibcon#first serial, iclass 2, count 0 2006.201.19:14:32.23#ibcon#enter sib2, iclass 2, count 0 2006.201.19:14:32.23#ibcon#flushed, iclass 2, count 0 2006.201.19:14:32.23#ibcon#about to write, iclass 2, count 0 2006.201.19:14:32.23#ibcon#wrote, iclass 2, count 0 2006.201.19:14:32.23#ibcon#about to read 3, iclass 2, count 0 2006.201.19:14:32.25#ibcon#read 3, iclass 2, count 0 2006.201.19:14:32.25#ibcon#about to read 4, iclass 2, count 0 2006.201.19:14:32.25#ibcon#read 4, iclass 2, count 0 2006.201.19:14:32.25#ibcon#about to read 5, iclass 2, count 0 2006.201.19:14:32.25#ibcon#read 5, iclass 2, count 0 2006.201.19:14:32.25#ibcon#about to read 6, iclass 2, count 0 2006.201.19:14:32.25#ibcon#read 6, iclass 2, count 0 2006.201.19:14:32.25#ibcon#end of sib2, iclass 2, count 0 2006.201.19:14:32.25#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:14:32.25#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:14:32.25#ibcon#[25=USB\r\n] 2006.201.19:14:32.25#ibcon#*before write, iclass 2, count 0 2006.201.19:14:32.25#ibcon#enter sib2, iclass 2, count 0 2006.201.19:14:32.25#ibcon#flushed, iclass 2, count 0 2006.201.19:14:32.25#ibcon#about to write, iclass 2, count 0 2006.201.19:14:32.25#ibcon#wrote, iclass 2, count 0 2006.201.19:14:32.25#ibcon#about to read 3, iclass 2, count 0 2006.201.19:14:32.28#ibcon#read 3, iclass 2, count 0 2006.201.19:14:32.28#ibcon#about to read 4, iclass 2, count 0 2006.201.19:14:32.28#ibcon#read 4, iclass 2, count 0 2006.201.19:14:32.28#ibcon#about to read 5, iclass 2, count 0 2006.201.19:14:32.28#ibcon#read 5, iclass 2, count 0 2006.201.19:14:32.28#ibcon#about to read 6, iclass 2, count 0 2006.201.19:14:32.28#ibcon#read 6, iclass 2, count 0 2006.201.19:14:32.28#ibcon#end of sib2, iclass 2, count 0 2006.201.19:14:32.28#ibcon#*after write, iclass 2, count 0 2006.201.19:14:32.28#ibcon#*before return 0, iclass 2, count 0 2006.201.19:14:32.28#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:32.28#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:32.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:14:32.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:14:32.28$vck44/valo=8,884.99 2006.201.19:14:32.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.19:14:32.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.19:14:32.28#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:32.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:32.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:32.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:32.28#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:14:32.28#ibcon#first serial, iclass 5, count 0 2006.201.19:14:32.28#ibcon#enter sib2, iclass 5, count 0 2006.201.19:14:32.28#ibcon#flushed, iclass 5, count 0 2006.201.19:14:32.28#ibcon#about to write, iclass 5, count 0 2006.201.19:14:32.28#ibcon#wrote, iclass 5, count 0 2006.201.19:14:32.28#ibcon#about to read 3, iclass 5, count 0 2006.201.19:14:32.30#ibcon#read 3, iclass 5, count 0 2006.201.19:14:32.30#ibcon#about to read 4, iclass 5, count 0 2006.201.19:14:32.30#ibcon#read 4, iclass 5, count 0 2006.201.19:14:32.30#ibcon#about to read 5, iclass 5, count 0 2006.201.19:14:32.30#ibcon#read 5, iclass 5, count 0 2006.201.19:14:32.30#ibcon#about to read 6, iclass 5, count 0 2006.201.19:14:32.30#ibcon#read 6, iclass 5, count 0 2006.201.19:14:32.30#ibcon#end of sib2, iclass 5, count 0 2006.201.19:14:32.30#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:14:32.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:14:32.30#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:14:32.30#ibcon#*before write, iclass 5, count 0 2006.201.19:14:32.30#ibcon#enter sib2, iclass 5, count 0 2006.201.19:14:32.30#ibcon#flushed, iclass 5, count 0 2006.201.19:14:32.30#ibcon#about to write, iclass 5, count 0 2006.201.19:14:32.30#ibcon#wrote, iclass 5, count 0 2006.201.19:14:32.30#ibcon#about to read 3, iclass 5, count 0 2006.201.19:14:32.34#ibcon#read 3, iclass 5, count 0 2006.201.19:14:32.34#ibcon#about to read 4, iclass 5, count 0 2006.201.19:14:32.34#ibcon#read 4, iclass 5, count 0 2006.201.19:14:32.34#ibcon#about to read 5, iclass 5, count 0 2006.201.19:14:32.34#ibcon#read 5, iclass 5, count 0 2006.201.19:14:32.34#ibcon#about to read 6, iclass 5, count 0 2006.201.19:14:32.34#ibcon#read 6, iclass 5, count 0 2006.201.19:14:32.34#ibcon#end of sib2, iclass 5, count 0 2006.201.19:14:32.34#ibcon#*after write, iclass 5, count 0 2006.201.19:14:32.34#ibcon#*before return 0, iclass 5, count 0 2006.201.19:14:32.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:32.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:32.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:14:32.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:14:32.34$vck44/va=8,4 2006.201.19:14:32.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.19:14:32.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.19:14:32.34#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:32.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:14:32.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:14:32.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:14:32.40#ibcon#enter wrdev, iclass 7, count 2 2006.201.19:14:32.40#ibcon#first serial, iclass 7, count 2 2006.201.19:14:32.40#ibcon#enter sib2, iclass 7, count 2 2006.201.19:14:32.40#ibcon#flushed, iclass 7, count 2 2006.201.19:14:32.40#ibcon#about to write, iclass 7, count 2 2006.201.19:14:32.40#ibcon#wrote, iclass 7, count 2 2006.201.19:14:32.40#ibcon#about to read 3, iclass 7, count 2 2006.201.19:14:32.42#ibcon#read 3, iclass 7, count 2 2006.201.19:14:32.42#ibcon#about to read 4, iclass 7, count 2 2006.201.19:14:32.42#ibcon#read 4, iclass 7, count 2 2006.201.19:14:32.42#ibcon#about to read 5, iclass 7, count 2 2006.201.19:14:32.42#ibcon#read 5, iclass 7, count 2 2006.201.19:14:32.42#ibcon#about to read 6, iclass 7, count 2 2006.201.19:14:32.42#ibcon#read 6, iclass 7, count 2 2006.201.19:14:32.42#ibcon#end of sib2, iclass 7, count 2 2006.201.19:14:32.42#ibcon#*mode == 0, iclass 7, count 2 2006.201.19:14:32.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.19:14:32.42#ibcon#[25=AT08-04\r\n] 2006.201.19:14:32.42#ibcon#*before write, iclass 7, count 2 2006.201.19:14:32.42#ibcon#enter sib2, iclass 7, count 2 2006.201.19:14:32.42#ibcon#flushed, iclass 7, count 2 2006.201.19:14:32.42#ibcon#about to write, iclass 7, count 2 2006.201.19:14:32.42#ibcon#wrote, iclass 7, count 2 2006.201.19:14:32.42#ibcon#about to read 3, iclass 7, count 2 2006.201.19:14:32.45#ibcon#read 3, iclass 7, count 2 2006.201.19:14:32.45#ibcon#about to read 4, iclass 7, count 2 2006.201.19:14:32.45#ibcon#read 4, iclass 7, count 2 2006.201.19:14:32.45#ibcon#about to read 5, iclass 7, count 2 2006.201.19:14:32.45#ibcon#read 5, iclass 7, count 2 2006.201.19:14:32.45#ibcon#about to read 6, iclass 7, count 2 2006.201.19:14:32.45#ibcon#read 6, iclass 7, count 2 2006.201.19:14:32.45#ibcon#end of sib2, iclass 7, count 2 2006.201.19:14:32.45#ibcon#*after write, iclass 7, count 2 2006.201.19:14:32.45#ibcon#*before return 0, iclass 7, count 2 2006.201.19:14:32.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:14:32.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:14:32.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.19:14:32.45#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:32.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:14:32.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:14:32.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:14:32.57#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:14:32.57#ibcon#first serial, iclass 7, count 0 2006.201.19:14:32.57#ibcon#enter sib2, iclass 7, count 0 2006.201.19:14:32.57#ibcon#flushed, iclass 7, count 0 2006.201.19:14:32.57#ibcon#about to write, iclass 7, count 0 2006.201.19:14:32.57#ibcon#wrote, iclass 7, count 0 2006.201.19:14:32.57#ibcon#about to read 3, iclass 7, count 0 2006.201.19:14:32.59#ibcon#read 3, iclass 7, count 0 2006.201.19:14:32.59#ibcon#about to read 4, iclass 7, count 0 2006.201.19:14:32.59#ibcon#read 4, iclass 7, count 0 2006.201.19:14:32.59#ibcon#about to read 5, iclass 7, count 0 2006.201.19:14:32.59#ibcon#read 5, iclass 7, count 0 2006.201.19:14:32.59#ibcon#about to read 6, iclass 7, count 0 2006.201.19:14:32.59#ibcon#read 6, iclass 7, count 0 2006.201.19:14:32.59#ibcon#end of sib2, iclass 7, count 0 2006.201.19:14:32.59#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:14:32.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:14:32.59#ibcon#[25=USB\r\n] 2006.201.19:14:32.59#ibcon#*before write, iclass 7, count 0 2006.201.19:14:32.59#ibcon#enter sib2, iclass 7, count 0 2006.201.19:14:32.59#ibcon#flushed, iclass 7, count 0 2006.201.19:14:32.59#ibcon#about to write, iclass 7, count 0 2006.201.19:14:32.59#ibcon#wrote, iclass 7, count 0 2006.201.19:14:32.59#ibcon#about to read 3, iclass 7, count 0 2006.201.19:14:32.62#ibcon#read 3, iclass 7, count 0 2006.201.19:14:32.62#ibcon#about to read 4, iclass 7, count 0 2006.201.19:14:32.62#ibcon#read 4, iclass 7, count 0 2006.201.19:14:32.62#ibcon#about to read 5, iclass 7, count 0 2006.201.19:14:32.62#ibcon#read 5, iclass 7, count 0 2006.201.19:14:32.62#ibcon#about to read 6, iclass 7, count 0 2006.201.19:14:32.62#ibcon#read 6, iclass 7, count 0 2006.201.19:14:32.62#ibcon#end of sib2, iclass 7, count 0 2006.201.19:14:32.62#ibcon#*after write, iclass 7, count 0 2006.201.19:14:32.62#ibcon#*before return 0, iclass 7, count 0 2006.201.19:14:32.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:14:32.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:14:32.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:14:32.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:14:32.62$vck44/vblo=1,629.99 2006.201.19:14:32.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.19:14:32.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.19:14:32.62#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:32.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:32.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:32.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:32.62#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:14:32.62#ibcon#first serial, iclass 11, count 0 2006.201.19:14:32.62#ibcon#enter sib2, iclass 11, count 0 2006.201.19:14:32.62#ibcon#flushed, iclass 11, count 0 2006.201.19:14:32.62#ibcon#about to write, iclass 11, count 0 2006.201.19:14:32.62#ibcon#wrote, iclass 11, count 0 2006.201.19:14:32.62#ibcon#about to read 3, iclass 11, count 0 2006.201.19:14:32.64#ibcon#read 3, iclass 11, count 0 2006.201.19:14:32.64#ibcon#about to read 4, iclass 11, count 0 2006.201.19:14:32.64#ibcon#read 4, iclass 11, count 0 2006.201.19:14:32.64#ibcon#about to read 5, iclass 11, count 0 2006.201.19:14:32.64#ibcon#read 5, iclass 11, count 0 2006.201.19:14:32.64#ibcon#about to read 6, iclass 11, count 0 2006.201.19:14:32.64#ibcon#read 6, iclass 11, count 0 2006.201.19:14:32.64#ibcon#end of sib2, iclass 11, count 0 2006.201.19:14:32.64#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:14:32.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:14:32.64#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:14:32.64#ibcon#*before write, iclass 11, count 0 2006.201.19:14:32.64#ibcon#enter sib2, iclass 11, count 0 2006.201.19:14:32.64#ibcon#flushed, iclass 11, count 0 2006.201.19:14:32.64#ibcon#about to write, iclass 11, count 0 2006.201.19:14:32.64#ibcon#wrote, iclass 11, count 0 2006.201.19:14:32.64#ibcon#about to read 3, iclass 11, count 0 2006.201.19:14:32.69#ibcon#read 3, iclass 11, count 0 2006.201.19:14:32.69#ibcon#about to read 4, iclass 11, count 0 2006.201.19:14:32.69#ibcon#read 4, iclass 11, count 0 2006.201.19:14:32.69#ibcon#about to read 5, iclass 11, count 0 2006.201.19:14:32.69#ibcon#read 5, iclass 11, count 0 2006.201.19:14:32.69#ibcon#about to read 6, iclass 11, count 0 2006.201.19:14:32.69#ibcon#read 6, iclass 11, count 0 2006.201.19:14:32.69#ibcon#end of sib2, iclass 11, count 0 2006.201.19:14:32.69#ibcon#*after write, iclass 11, count 0 2006.201.19:14:32.69#ibcon#*before return 0, iclass 11, count 0 2006.201.19:14:32.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:32.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:14:32.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:14:32.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:14:32.69$vck44/vb=1,4 2006.201.19:14:32.69#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.19:14:32.69#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.19:14:32.69#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:32.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:32.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:32.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:32.69#ibcon#enter wrdev, iclass 13, count 2 2006.201.19:14:32.69#ibcon#first serial, iclass 13, count 2 2006.201.19:14:32.69#ibcon#enter sib2, iclass 13, count 2 2006.201.19:14:32.69#ibcon#flushed, iclass 13, count 2 2006.201.19:14:32.69#ibcon#about to write, iclass 13, count 2 2006.201.19:14:32.69#ibcon#wrote, iclass 13, count 2 2006.201.19:14:32.69#ibcon#about to read 3, iclass 13, count 2 2006.201.19:14:32.71#ibcon#read 3, iclass 13, count 2 2006.201.19:14:32.71#ibcon#about to read 4, iclass 13, count 2 2006.201.19:14:32.71#ibcon#read 4, iclass 13, count 2 2006.201.19:14:32.71#ibcon#about to read 5, iclass 13, count 2 2006.201.19:14:32.71#ibcon#read 5, iclass 13, count 2 2006.201.19:14:32.71#ibcon#about to read 6, iclass 13, count 2 2006.201.19:14:32.71#ibcon#read 6, iclass 13, count 2 2006.201.19:14:32.71#ibcon#end of sib2, iclass 13, count 2 2006.201.19:14:32.71#ibcon#*mode == 0, iclass 13, count 2 2006.201.19:14:32.71#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.19:14:32.71#ibcon#[27=AT01-04\r\n] 2006.201.19:14:32.71#ibcon#*before write, iclass 13, count 2 2006.201.19:14:32.71#ibcon#enter sib2, iclass 13, count 2 2006.201.19:14:32.71#ibcon#flushed, iclass 13, count 2 2006.201.19:14:32.71#ibcon#about to write, iclass 13, count 2 2006.201.19:14:32.71#ibcon#wrote, iclass 13, count 2 2006.201.19:14:32.71#ibcon#about to read 3, iclass 13, count 2 2006.201.19:14:32.74#ibcon#read 3, iclass 13, count 2 2006.201.19:14:32.74#ibcon#about to read 4, iclass 13, count 2 2006.201.19:14:32.74#ibcon#read 4, iclass 13, count 2 2006.201.19:14:32.74#ibcon#about to read 5, iclass 13, count 2 2006.201.19:14:32.74#ibcon#read 5, iclass 13, count 2 2006.201.19:14:32.74#ibcon#about to read 6, iclass 13, count 2 2006.201.19:14:32.74#ibcon#read 6, iclass 13, count 2 2006.201.19:14:32.74#ibcon#end of sib2, iclass 13, count 2 2006.201.19:14:32.74#ibcon#*after write, iclass 13, count 2 2006.201.19:14:32.74#ibcon#*before return 0, iclass 13, count 2 2006.201.19:14:32.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:32.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:14:32.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.19:14:32.74#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:32.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:32.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:32.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:32.86#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:14:32.86#ibcon#first serial, iclass 13, count 0 2006.201.19:14:32.86#ibcon#enter sib2, iclass 13, count 0 2006.201.19:14:32.86#ibcon#flushed, iclass 13, count 0 2006.201.19:14:32.86#ibcon#about to write, iclass 13, count 0 2006.201.19:14:32.86#ibcon#wrote, iclass 13, count 0 2006.201.19:14:32.86#ibcon#about to read 3, iclass 13, count 0 2006.201.19:14:32.88#ibcon#read 3, iclass 13, count 0 2006.201.19:14:32.88#ibcon#about to read 4, iclass 13, count 0 2006.201.19:14:32.88#ibcon#read 4, iclass 13, count 0 2006.201.19:14:32.88#ibcon#about to read 5, iclass 13, count 0 2006.201.19:14:32.88#ibcon#read 5, iclass 13, count 0 2006.201.19:14:32.88#ibcon#about to read 6, iclass 13, count 0 2006.201.19:14:32.88#ibcon#read 6, iclass 13, count 0 2006.201.19:14:32.88#ibcon#end of sib2, iclass 13, count 0 2006.201.19:14:32.88#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:14:32.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:14:32.88#ibcon#[27=USB\r\n] 2006.201.19:14:32.88#ibcon#*before write, iclass 13, count 0 2006.201.19:14:32.88#ibcon#enter sib2, iclass 13, count 0 2006.201.19:14:32.88#ibcon#flushed, iclass 13, count 0 2006.201.19:14:32.88#ibcon#about to write, iclass 13, count 0 2006.201.19:14:32.88#ibcon#wrote, iclass 13, count 0 2006.201.19:14:32.88#ibcon#about to read 3, iclass 13, count 0 2006.201.19:14:32.91#ibcon#read 3, iclass 13, count 0 2006.201.19:14:32.91#ibcon#about to read 4, iclass 13, count 0 2006.201.19:14:32.91#ibcon#read 4, iclass 13, count 0 2006.201.19:14:32.91#ibcon#about to read 5, iclass 13, count 0 2006.201.19:14:32.91#ibcon#read 5, iclass 13, count 0 2006.201.19:14:32.91#ibcon#about to read 6, iclass 13, count 0 2006.201.19:14:32.91#ibcon#read 6, iclass 13, count 0 2006.201.19:14:32.91#ibcon#end of sib2, iclass 13, count 0 2006.201.19:14:32.91#ibcon#*after write, iclass 13, count 0 2006.201.19:14:32.91#ibcon#*before return 0, iclass 13, count 0 2006.201.19:14:32.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:32.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:14:32.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:14:32.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:14:32.91$vck44/vblo=2,634.99 2006.201.19:14:32.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.19:14:32.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.19:14:32.91#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:32.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:32.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:32.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:32.91#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:14:32.91#ibcon#first serial, iclass 15, count 0 2006.201.19:14:32.91#ibcon#enter sib2, iclass 15, count 0 2006.201.19:14:32.91#ibcon#flushed, iclass 15, count 0 2006.201.19:14:32.91#ibcon#about to write, iclass 15, count 0 2006.201.19:14:32.91#ibcon#wrote, iclass 15, count 0 2006.201.19:14:32.91#ibcon#about to read 3, iclass 15, count 0 2006.201.19:14:32.93#ibcon#read 3, iclass 15, count 0 2006.201.19:14:32.93#ibcon#about to read 4, iclass 15, count 0 2006.201.19:14:32.93#ibcon#read 4, iclass 15, count 0 2006.201.19:14:32.93#ibcon#about to read 5, iclass 15, count 0 2006.201.19:14:32.93#ibcon#read 5, iclass 15, count 0 2006.201.19:14:32.93#ibcon#about to read 6, iclass 15, count 0 2006.201.19:14:32.93#ibcon#read 6, iclass 15, count 0 2006.201.19:14:32.93#ibcon#end of sib2, iclass 15, count 0 2006.201.19:14:32.93#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:14:32.93#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:14:32.93#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:14:32.93#ibcon#*before write, iclass 15, count 0 2006.201.19:14:32.93#ibcon#enter sib2, iclass 15, count 0 2006.201.19:14:32.93#ibcon#flushed, iclass 15, count 0 2006.201.19:14:32.93#ibcon#about to write, iclass 15, count 0 2006.201.19:14:32.93#ibcon#wrote, iclass 15, count 0 2006.201.19:14:32.93#ibcon#about to read 3, iclass 15, count 0 2006.201.19:14:32.97#ibcon#read 3, iclass 15, count 0 2006.201.19:14:32.97#ibcon#about to read 4, iclass 15, count 0 2006.201.19:14:32.97#ibcon#read 4, iclass 15, count 0 2006.201.19:14:32.97#ibcon#about to read 5, iclass 15, count 0 2006.201.19:14:32.97#ibcon#read 5, iclass 15, count 0 2006.201.19:14:32.97#ibcon#about to read 6, iclass 15, count 0 2006.201.19:14:32.97#ibcon#read 6, iclass 15, count 0 2006.201.19:14:32.97#ibcon#end of sib2, iclass 15, count 0 2006.201.19:14:32.97#ibcon#*after write, iclass 15, count 0 2006.201.19:14:32.97#ibcon#*before return 0, iclass 15, count 0 2006.201.19:14:32.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:32.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:14:32.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:14:32.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:14:32.97$vck44/vb=2,5 2006.201.19:14:32.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.19:14:32.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.19:14:32.97#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:32.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:33.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:33.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:33.03#ibcon#enter wrdev, iclass 17, count 2 2006.201.19:14:33.03#ibcon#first serial, iclass 17, count 2 2006.201.19:14:33.03#ibcon#enter sib2, iclass 17, count 2 2006.201.19:14:33.03#ibcon#flushed, iclass 17, count 2 2006.201.19:14:33.03#ibcon#about to write, iclass 17, count 2 2006.201.19:14:33.03#ibcon#wrote, iclass 17, count 2 2006.201.19:14:33.03#ibcon#about to read 3, iclass 17, count 2 2006.201.19:14:33.05#ibcon#read 3, iclass 17, count 2 2006.201.19:14:33.05#ibcon#about to read 4, iclass 17, count 2 2006.201.19:14:33.05#ibcon#read 4, iclass 17, count 2 2006.201.19:14:33.05#ibcon#about to read 5, iclass 17, count 2 2006.201.19:14:33.05#ibcon#read 5, iclass 17, count 2 2006.201.19:14:33.05#ibcon#about to read 6, iclass 17, count 2 2006.201.19:14:33.05#ibcon#read 6, iclass 17, count 2 2006.201.19:14:33.05#ibcon#end of sib2, iclass 17, count 2 2006.201.19:14:33.05#ibcon#*mode == 0, iclass 17, count 2 2006.201.19:14:33.05#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.19:14:33.05#ibcon#[27=AT02-05\r\n] 2006.201.19:14:33.05#ibcon#*before write, iclass 17, count 2 2006.201.19:14:33.05#ibcon#enter sib2, iclass 17, count 2 2006.201.19:14:33.05#ibcon#flushed, iclass 17, count 2 2006.201.19:14:33.05#ibcon#about to write, iclass 17, count 2 2006.201.19:14:33.05#ibcon#wrote, iclass 17, count 2 2006.201.19:14:33.05#ibcon#about to read 3, iclass 17, count 2 2006.201.19:14:33.08#ibcon#read 3, iclass 17, count 2 2006.201.19:14:33.08#ibcon#about to read 4, iclass 17, count 2 2006.201.19:14:33.08#ibcon#read 4, iclass 17, count 2 2006.201.19:14:33.08#ibcon#about to read 5, iclass 17, count 2 2006.201.19:14:33.08#ibcon#read 5, iclass 17, count 2 2006.201.19:14:33.08#ibcon#about to read 6, iclass 17, count 2 2006.201.19:14:33.08#ibcon#read 6, iclass 17, count 2 2006.201.19:14:33.08#ibcon#end of sib2, iclass 17, count 2 2006.201.19:14:33.08#ibcon#*after write, iclass 17, count 2 2006.201.19:14:33.08#ibcon#*before return 0, iclass 17, count 2 2006.201.19:14:33.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:33.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:14:33.08#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.19:14:33.08#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:33.08#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:33.20#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:33.20#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:33.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:14:33.20#ibcon#first serial, iclass 17, count 0 2006.201.19:14:33.20#ibcon#enter sib2, iclass 17, count 0 2006.201.19:14:33.20#ibcon#flushed, iclass 17, count 0 2006.201.19:14:33.20#ibcon#about to write, iclass 17, count 0 2006.201.19:14:33.20#ibcon#wrote, iclass 17, count 0 2006.201.19:14:33.20#ibcon#about to read 3, iclass 17, count 0 2006.201.19:14:33.22#ibcon#read 3, iclass 17, count 0 2006.201.19:14:33.22#ibcon#about to read 4, iclass 17, count 0 2006.201.19:14:33.22#ibcon#read 4, iclass 17, count 0 2006.201.19:14:33.22#ibcon#about to read 5, iclass 17, count 0 2006.201.19:14:33.22#ibcon#read 5, iclass 17, count 0 2006.201.19:14:33.22#ibcon#about to read 6, iclass 17, count 0 2006.201.19:14:33.22#ibcon#read 6, iclass 17, count 0 2006.201.19:14:33.22#ibcon#end of sib2, iclass 17, count 0 2006.201.19:14:33.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:14:33.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:14:33.22#ibcon#[27=USB\r\n] 2006.201.19:14:33.22#ibcon#*before write, iclass 17, count 0 2006.201.19:14:33.22#ibcon#enter sib2, iclass 17, count 0 2006.201.19:14:33.22#ibcon#flushed, iclass 17, count 0 2006.201.19:14:33.22#ibcon#about to write, iclass 17, count 0 2006.201.19:14:33.22#ibcon#wrote, iclass 17, count 0 2006.201.19:14:33.22#ibcon#about to read 3, iclass 17, count 0 2006.201.19:14:33.25#ibcon#read 3, iclass 17, count 0 2006.201.19:14:33.25#ibcon#about to read 4, iclass 17, count 0 2006.201.19:14:33.25#ibcon#read 4, iclass 17, count 0 2006.201.19:14:33.25#ibcon#about to read 5, iclass 17, count 0 2006.201.19:14:33.25#ibcon#read 5, iclass 17, count 0 2006.201.19:14:33.25#ibcon#about to read 6, iclass 17, count 0 2006.201.19:14:33.25#ibcon#read 6, iclass 17, count 0 2006.201.19:14:33.25#ibcon#end of sib2, iclass 17, count 0 2006.201.19:14:33.25#ibcon#*after write, iclass 17, count 0 2006.201.19:14:33.25#ibcon#*before return 0, iclass 17, count 0 2006.201.19:14:33.25#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:33.25#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:14:33.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:14:33.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:14:33.25$vck44/vblo=3,649.99 2006.201.19:14:33.25#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.19:14:33.25#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.19:14:33.25#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:33.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:33.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:33.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:33.25#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:14:33.25#ibcon#first serial, iclass 19, count 0 2006.201.19:14:33.25#ibcon#enter sib2, iclass 19, count 0 2006.201.19:14:33.25#ibcon#flushed, iclass 19, count 0 2006.201.19:14:33.25#ibcon#about to write, iclass 19, count 0 2006.201.19:14:33.25#ibcon#wrote, iclass 19, count 0 2006.201.19:14:33.25#ibcon#about to read 3, iclass 19, count 0 2006.201.19:14:33.27#ibcon#read 3, iclass 19, count 0 2006.201.19:14:33.27#ibcon#about to read 4, iclass 19, count 0 2006.201.19:14:33.27#ibcon#read 4, iclass 19, count 0 2006.201.19:14:33.27#ibcon#about to read 5, iclass 19, count 0 2006.201.19:14:33.27#ibcon#read 5, iclass 19, count 0 2006.201.19:14:33.27#ibcon#about to read 6, iclass 19, count 0 2006.201.19:14:33.27#ibcon#read 6, iclass 19, count 0 2006.201.19:14:33.27#ibcon#end of sib2, iclass 19, count 0 2006.201.19:14:33.27#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:14:33.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:14:33.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:14:33.27#ibcon#*before write, iclass 19, count 0 2006.201.19:14:33.27#ibcon#enter sib2, iclass 19, count 0 2006.201.19:14:33.27#ibcon#flushed, iclass 19, count 0 2006.201.19:14:33.27#ibcon#about to write, iclass 19, count 0 2006.201.19:14:33.27#ibcon#wrote, iclass 19, count 0 2006.201.19:14:33.27#ibcon#about to read 3, iclass 19, count 0 2006.201.19:14:33.31#ibcon#read 3, iclass 19, count 0 2006.201.19:14:33.31#ibcon#about to read 4, iclass 19, count 0 2006.201.19:14:33.31#ibcon#read 4, iclass 19, count 0 2006.201.19:14:33.31#ibcon#about to read 5, iclass 19, count 0 2006.201.19:14:33.31#ibcon#read 5, iclass 19, count 0 2006.201.19:14:33.31#ibcon#about to read 6, iclass 19, count 0 2006.201.19:14:33.31#ibcon#read 6, iclass 19, count 0 2006.201.19:14:33.31#ibcon#end of sib2, iclass 19, count 0 2006.201.19:14:33.31#ibcon#*after write, iclass 19, count 0 2006.201.19:14:33.31#ibcon#*before return 0, iclass 19, count 0 2006.201.19:14:33.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:33.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:14:33.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:14:33.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:14:33.31$vck44/vb=3,4 2006.201.19:14:33.31#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.19:14:33.31#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.19:14:33.31#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:33.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:33.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:33.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:33.37#ibcon#enter wrdev, iclass 21, count 2 2006.201.19:14:33.37#ibcon#first serial, iclass 21, count 2 2006.201.19:14:33.37#ibcon#enter sib2, iclass 21, count 2 2006.201.19:14:33.37#ibcon#flushed, iclass 21, count 2 2006.201.19:14:33.37#ibcon#about to write, iclass 21, count 2 2006.201.19:14:33.37#ibcon#wrote, iclass 21, count 2 2006.201.19:14:33.37#ibcon#about to read 3, iclass 21, count 2 2006.201.19:14:33.39#ibcon#read 3, iclass 21, count 2 2006.201.19:14:33.39#ibcon#about to read 4, iclass 21, count 2 2006.201.19:14:33.39#ibcon#read 4, iclass 21, count 2 2006.201.19:14:33.39#ibcon#about to read 5, iclass 21, count 2 2006.201.19:14:33.39#ibcon#read 5, iclass 21, count 2 2006.201.19:14:33.39#ibcon#about to read 6, iclass 21, count 2 2006.201.19:14:33.39#ibcon#read 6, iclass 21, count 2 2006.201.19:14:33.39#ibcon#end of sib2, iclass 21, count 2 2006.201.19:14:33.39#ibcon#*mode == 0, iclass 21, count 2 2006.201.19:14:33.39#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.19:14:33.39#ibcon#[27=AT03-04\r\n] 2006.201.19:14:33.39#ibcon#*before write, iclass 21, count 2 2006.201.19:14:33.39#ibcon#enter sib2, iclass 21, count 2 2006.201.19:14:33.39#ibcon#flushed, iclass 21, count 2 2006.201.19:14:33.39#ibcon#about to write, iclass 21, count 2 2006.201.19:14:33.39#ibcon#wrote, iclass 21, count 2 2006.201.19:14:33.39#ibcon#about to read 3, iclass 21, count 2 2006.201.19:14:33.43#ibcon#read 3, iclass 21, count 2 2006.201.19:14:33.43#ibcon#about to read 4, iclass 21, count 2 2006.201.19:14:33.43#ibcon#read 4, iclass 21, count 2 2006.201.19:14:33.43#ibcon#about to read 5, iclass 21, count 2 2006.201.19:14:33.43#ibcon#read 5, iclass 21, count 2 2006.201.19:14:33.43#ibcon#about to read 6, iclass 21, count 2 2006.201.19:14:33.43#ibcon#read 6, iclass 21, count 2 2006.201.19:14:33.43#ibcon#end of sib2, iclass 21, count 2 2006.201.19:14:33.43#ibcon#*after write, iclass 21, count 2 2006.201.19:14:33.43#ibcon#*before return 0, iclass 21, count 2 2006.201.19:14:33.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:33.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:14:33.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.19:14:33.43#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:33.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:33.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:33.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:33.55#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:14:33.55#ibcon#first serial, iclass 21, count 0 2006.201.19:14:33.55#ibcon#enter sib2, iclass 21, count 0 2006.201.19:14:33.55#ibcon#flushed, iclass 21, count 0 2006.201.19:14:33.55#ibcon#about to write, iclass 21, count 0 2006.201.19:14:33.55#ibcon#wrote, iclass 21, count 0 2006.201.19:14:33.55#ibcon#about to read 3, iclass 21, count 0 2006.201.19:14:33.57#ibcon#read 3, iclass 21, count 0 2006.201.19:14:33.57#ibcon#about to read 4, iclass 21, count 0 2006.201.19:14:33.57#ibcon#read 4, iclass 21, count 0 2006.201.19:14:33.57#ibcon#about to read 5, iclass 21, count 0 2006.201.19:14:33.57#ibcon#read 5, iclass 21, count 0 2006.201.19:14:33.57#ibcon#about to read 6, iclass 21, count 0 2006.201.19:14:33.57#ibcon#read 6, iclass 21, count 0 2006.201.19:14:33.57#ibcon#end of sib2, iclass 21, count 0 2006.201.19:14:33.57#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:14:33.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:14:33.57#ibcon#[27=USB\r\n] 2006.201.19:14:33.57#ibcon#*before write, iclass 21, count 0 2006.201.19:14:33.57#ibcon#enter sib2, iclass 21, count 0 2006.201.19:14:33.57#ibcon#flushed, iclass 21, count 0 2006.201.19:14:33.57#ibcon#about to write, iclass 21, count 0 2006.201.19:14:33.57#ibcon#wrote, iclass 21, count 0 2006.201.19:14:33.57#ibcon#about to read 3, iclass 21, count 0 2006.201.19:14:33.60#ibcon#read 3, iclass 21, count 0 2006.201.19:14:33.60#ibcon#about to read 4, iclass 21, count 0 2006.201.19:14:33.60#ibcon#read 4, iclass 21, count 0 2006.201.19:14:33.60#ibcon#about to read 5, iclass 21, count 0 2006.201.19:14:33.60#ibcon#read 5, iclass 21, count 0 2006.201.19:14:33.60#ibcon#about to read 6, iclass 21, count 0 2006.201.19:14:33.60#ibcon#read 6, iclass 21, count 0 2006.201.19:14:33.60#ibcon#end of sib2, iclass 21, count 0 2006.201.19:14:33.60#ibcon#*after write, iclass 21, count 0 2006.201.19:14:33.60#ibcon#*before return 0, iclass 21, count 0 2006.201.19:14:33.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:33.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:14:33.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:14:33.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:14:33.60$vck44/vblo=4,679.99 2006.201.19:14:33.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.19:14:33.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.19:14:33.60#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:33.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:33.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:33.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:33.60#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:14:33.60#ibcon#first serial, iclass 23, count 0 2006.201.19:14:33.60#ibcon#enter sib2, iclass 23, count 0 2006.201.19:14:33.60#ibcon#flushed, iclass 23, count 0 2006.201.19:14:33.60#ibcon#about to write, iclass 23, count 0 2006.201.19:14:33.60#ibcon#wrote, iclass 23, count 0 2006.201.19:14:33.60#ibcon#about to read 3, iclass 23, count 0 2006.201.19:14:33.62#ibcon#read 3, iclass 23, count 0 2006.201.19:14:33.62#ibcon#about to read 4, iclass 23, count 0 2006.201.19:14:33.62#ibcon#read 4, iclass 23, count 0 2006.201.19:14:33.62#ibcon#about to read 5, iclass 23, count 0 2006.201.19:14:33.62#ibcon#read 5, iclass 23, count 0 2006.201.19:14:33.62#ibcon#about to read 6, iclass 23, count 0 2006.201.19:14:33.62#ibcon#read 6, iclass 23, count 0 2006.201.19:14:33.62#ibcon#end of sib2, iclass 23, count 0 2006.201.19:14:33.62#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:14:33.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:14:33.62#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:14:33.62#ibcon#*before write, iclass 23, count 0 2006.201.19:14:33.62#ibcon#enter sib2, iclass 23, count 0 2006.201.19:14:33.62#ibcon#flushed, iclass 23, count 0 2006.201.19:14:33.62#ibcon#about to write, iclass 23, count 0 2006.201.19:14:33.62#ibcon#wrote, iclass 23, count 0 2006.201.19:14:33.62#ibcon#about to read 3, iclass 23, count 0 2006.201.19:14:33.66#ibcon#read 3, iclass 23, count 0 2006.201.19:14:33.66#ibcon#about to read 4, iclass 23, count 0 2006.201.19:14:33.66#ibcon#read 4, iclass 23, count 0 2006.201.19:14:33.66#ibcon#about to read 5, iclass 23, count 0 2006.201.19:14:33.66#ibcon#read 5, iclass 23, count 0 2006.201.19:14:33.66#ibcon#about to read 6, iclass 23, count 0 2006.201.19:14:33.66#ibcon#read 6, iclass 23, count 0 2006.201.19:14:33.66#ibcon#end of sib2, iclass 23, count 0 2006.201.19:14:33.66#ibcon#*after write, iclass 23, count 0 2006.201.19:14:33.66#ibcon#*before return 0, iclass 23, count 0 2006.201.19:14:33.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:33.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:14:33.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:14:33.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:14:33.66$vck44/vb=4,5 2006.201.19:14:33.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.19:14:33.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.19:14:33.66#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:33.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:33.72#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:33.72#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:33.72#ibcon#enter wrdev, iclass 25, count 2 2006.201.19:14:33.72#ibcon#first serial, iclass 25, count 2 2006.201.19:14:33.72#ibcon#enter sib2, iclass 25, count 2 2006.201.19:14:33.72#ibcon#flushed, iclass 25, count 2 2006.201.19:14:33.72#ibcon#about to write, iclass 25, count 2 2006.201.19:14:33.72#ibcon#wrote, iclass 25, count 2 2006.201.19:14:33.72#ibcon#about to read 3, iclass 25, count 2 2006.201.19:14:33.74#ibcon#read 3, iclass 25, count 2 2006.201.19:14:33.74#ibcon#about to read 4, iclass 25, count 2 2006.201.19:14:33.74#ibcon#read 4, iclass 25, count 2 2006.201.19:14:33.74#ibcon#about to read 5, iclass 25, count 2 2006.201.19:14:33.74#ibcon#read 5, iclass 25, count 2 2006.201.19:14:33.74#ibcon#about to read 6, iclass 25, count 2 2006.201.19:14:33.74#ibcon#read 6, iclass 25, count 2 2006.201.19:14:33.74#ibcon#end of sib2, iclass 25, count 2 2006.201.19:14:33.74#ibcon#*mode == 0, iclass 25, count 2 2006.201.19:14:33.74#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.19:14:33.74#ibcon#[27=AT04-05\r\n] 2006.201.19:14:33.74#ibcon#*before write, iclass 25, count 2 2006.201.19:14:33.74#ibcon#enter sib2, iclass 25, count 2 2006.201.19:14:33.74#ibcon#flushed, iclass 25, count 2 2006.201.19:14:33.74#ibcon#about to write, iclass 25, count 2 2006.201.19:14:33.74#ibcon#wrote, iclass 25, count 2 2006.201.19:14:33.74#ibcon#about to read 3, iclass 25, count 2 2006.201.19:14:33.77#ibcon#read 3, iclass 25, count 2 2006.201.19:14:33.77#ibcon#about to read 4, iclass 25, count 2 2006.201.19:14:33.77#ibcon#read 4, iclass 25, count 2 2006.201.19:14:33.77#ibcon#about to read 5, iclass 25, count 2 2006.201.19:14:33.77#ibcon#read 5, iclass 25, count 2 2006.201.19:14:33.77#ibcon#about to read 6, iclass 25, count 2 2006.201.19:14:33.77#ibcon#read 6, iclass 25, count 2 2006.201.19:14:33.77#ibcon#end of sib2, iclass 25, count 2 2006.201.19:14:33.77#ibcon#*after write, iclass 25, count 2 2006.201.19:14:33.77#ibcon#*before return 0, iclass 25, count 2 2006.201.19:14:33.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:33.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:14:33.77#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.19:14:33.77#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:33.77#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:33.89#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:33.89#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:33.89#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:14:33.89#ibcon#first serial, iclass 25, count 0 2006.201.19:14:33.89#ibcon#enter sib2, iclass 25, count 0 2006.201.19:14:33.89#ibcon#flushed, iclass 25, count 0 2006.201.19:14:33.89#ibcon#about to write, iclass 25, count 0 2006.201.19:14:33.89#ibcon#wrote, iclass 25, count 0 2006.201.19:14:33.89#ibcon#about to read 3, iclass 25, count 0 2006.201.19:14:33.91#ibcon#read 3, iclass 25, count 0 2006.201.19:14:33.91#ibcon#about to read 4, iclass 25, count 0 2006.201.19:14:33.91#ibcon#read 4, iclass 25, count 0 2006.201.19:14:33.91#ibcon#about to read 5, iclass 25, count 0 2006.201.19:14:33.91#ibcon#read 5, iclass 25, count 0 2006.201.19:14:33.91#ibcon#about to read 6, iclass 25, count 0 2006.201.19:14:33.91#ibcon#read 6, iclass 25, count 0 2006.201.19:14:33.91#ibcon#end of sib2, iclass 25, count 0 2006.201.19:14:33.91#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:14:33.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:14:33.91#ibcon#[27=USB\r\n] 2006.201.19:14:33.91#ibcon#*before write, iclass 25, count 0 2006.201.19:14:33.91#ibcon#enter sib2, iclass 25, count 0 2006.201.19:14:33.91#ibcon#flushed, iclass 25, count 0 2006.201.19:14:33.91#ibcon#about to write, iclass 25, count 0 2006.201.19:14:33.91#ibcon#wrote, iclass 25, count 0 2006.201.19:14:33.91#ibcon#about to read 3, iclass 25, count 0 2006.201.19:14:33.94#ibcon#read 3, iclass 25, count 0 2006.201.19:14:33.94#ibcon#about to read 4, iclass 25, count 0 2006.201.19:14:33.94#ibcon#read 4, iclass 25, count 0 2006.201.19:14:33.94#ibcon#about to read 5, iclass 25, count 0 2006.201.19:14:33.94#ibcon#read 5, iclass 25, count 0 2006.201.19:14:33.94#ibcon#about to read 6, iclass 25, count 0 2006.201.19:14:33.94#ibcon#read 6, iclass 25, count 0 2006.201.19:14:33.94#ibcon#end of sib2, iclass 25, count 0 2006.201.19:14:33.94#ibcon#*after write, iclass 25, count 0 2006.201.19:14:33.94#ibcon#*before return 0, iclass 25, count 0 2006.201.19:14:33.94#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:33.94#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:14:33.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:14:33.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:14:33.94$vck44/vblo=5,709.99 2006.201.19:14:33.94#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.19:14:33.94#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.19:14:33.94#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:33.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:33.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:33.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:33.94#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:14:33.94#ibcon#first serial, iclass 27, count 0 2006.201.19:14:33.94#ibcon#enter sib2, iclass 27, count 0 2006.201.19:14:33.94#ibcon#flushed, iclass 27, count 0 2006.201.19:14:33.94#ibcon#about to write, iclass 27, count 0 2006.201.19:14:33.94#ibcon#wrote, iclass 27, count 0 2006.201.19:14:33.94#ibcon#about to read 3, iclass 27, count 0 2006.201.19:14:33.96#ibcon#read 3, iclass 27, count 0 2006.201.19:14:33.96#ibcon#about to read 4, iclass 27, count 0 2006.201.19:14:33.96#ibcon#read 4, iclass 27, count 0 2006.201.19:14:33.96#ibcon#about to read 5, iclass 27, count 0 2006.201.19:14:33.96#ibcon#read 5, iclass 27, count 0 2006.201.19:14:33.96#ibcon#about to read 6, iclass 27, count 0 2006.201.19:14:33.96#ibcon#read 6, iclass 27, count 0 2006.201.19:14:33.96#ibcon#end of sib2, iclass 27, count 0 2006.201.19:14:33.96#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:14:33.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:14:33.96#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:14:33.96#ibcon#*before write, iclass 27, count 0 2006.201.19:14:33.96#ibcon#enter sib2, iclass 27, count 0 2006.201.19:14:33.96#ibcon#flushed, iclass 27, count 0 2006.201.19:14:33.96#ibcon#about to write, iclass 27, count 0 2006.201.19:14:33.96#ibcon#wrote, iclass 27, count 0 2006.201.19:14:33.96#ibcon#about to read 3, iclass 27, count 0 2006.201.19:14:34.00#ibcon#read 3, iclass 27, count 0 2006.201.19:14:34.00#ibcon#about to read 4, iclass 27, count 0 2006.201.19:14:34.00#ibcon#read 4, iclass 27, count 0 2006.201.19:14:34.00#ibcon#about to read 5, iclass 27, count 0 2006.201.19:14:34.00#ibcon#read 5, iclass 27, count 0 2006.201.19:14:34.00#ibcon#about to read 6, iclass 27, count 0 2006.201.19:14:34.00#ibcon#read 6, iclass 27, count 0 2006.201.19:14:34.00#ibcon#end of sib2, iclass 27, count 0 2006.201.19:14:34.00#ibcon#*after write, iclass 27, count 0 2006.201.19:14:34.00#ibcon#*before return 0, iclass 27, count 0 2006.201.19:14:34.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:34.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:14:34.00#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:14:34.00#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:14:34.00$vck44/vb=5,4 2006.201.19:14:34.00#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.19:14:34.00#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.19:14:34.00#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:34.00#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:34.06#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:34.06#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:34.06#ibcon#enter wrdev, iclass 29, count 2 2006.201.19:14:34.06#ibcon#first serial, iclass 29, count 2 2006.201.19:14:34.06#ibcon#enter sib2, iclass 29, count 2 2006.201.19:14:34.06#ibcon#flushed, iclass 29, count 2 2006.201.19:14:34.06#ibcon#about to write, iclass 29, count 2 2006.201.19:14:34.06#ibcon#wrote, iclass 29, count 2 2006.201.19:14:34.06#ibcon#about to read 3, iclass 29, count 2 2006.201.19:14:34.08#ibcon#read 3, iclass 29, count 2 2006.201.19:14:34.08#ibcon#about to read 4, iclass 29, count 2 2006.201.19:14:34.08#ibcon#read 4, iclass 29, count 2 2006.201.19:14:34.08#ibcon#about to read 5, iclass 29, count 2 2006.201.19:14:34.08#ibcon#read 5, iclass 29, count 2 2006.201.19:14:34.08#ibcon#about to read 6, iclass 29, count 2 2006.201.19:14:34.08#ibcon#read 6, iclass 29, count 2 2006.201.19:14:34.08#ibcon#end of sib2, iclass 29, count 2 2006.201.19:14:34.08#ibcon#*mode == 0, iclass 29, count 2 2006.201.19:14:34.08#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.19:14:34.08#ibcon#[27=AT05-04\r\n] 2006.201.19:14:34.08#ibcon#*before write, iclass 29, count 2 2006.201.19:14:34.08#ibcon#enter sib2, iclass 29, count 2 2006.201.19:14:34.08#ibcon#flushed, iclass 29, count 2 2006.201.19:14:34.08#ibcon#about to write, iclass 29, count 2 2006.201.19:14:34.08#ibcon#wrote, iclass 29, count 2 2006.201.19:14:34.08#ibcon#about to read 3, iclass 29, count 2 2006.201.19:14:34.11#ibcon#read 3, iclass 29, count 2 2006.201.19:14:34.11#ibcon#about to read 4, iclass 29, count 2 2006.201.19:14:34.11#ibcon#read 4, iclass 29, count 2 2006.201.19:14:34.11#ibcon#about to read 5, iclass 29, count 2 2006.201.19:14:34.11#ibcon#read 5, iclass 29, count 2 2006.201.19:14:34.11#ibcon#about to read 6, iclass 29, count 2 2006.201.19:14:34.11#ibcon#read 6, iclass 29, count 2 2006.201.19:14:34.11#ibcon#end of sib2, iclass 29, count 2 2006.201.19:14:34.11#ibcon#*after write, iclass 29, count 2 2006.201.19:14:34.11#ibcon#*before return 0, iclass 29, count 2 2006.201.19:14:34.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:34.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:14:34.11#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.19:14:34.11#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:34.11#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:34.23#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:34.23#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:34.23#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:14:34.23#ibcon#first serial, iclass 29, count 0 2006.201.19:14:34.23#ibcon#enter sib2, iclass 29, count 0 2006.201.19:14:34.23#ibcon#flushed, iclass 29, count 0 2006.201.19:14:34.23#ibcon#about to write, iclass 29, count 0 2006.201.19:14:34.23#ibcon#wrote, iclass 29, count 0 2006.201.19:14:34.23#ibcon#about to read 3, iclass 29, count 0 2006.201.19:14:34.25#ibcon#read 3, iclass 29, count 0 2006.201.19:14:34.25#ibcon#about to read 4, iclass 29, count 0 2006.201.19:14:34.25#ibcon#read 4, iclass 29, count 0 2006.201.19:14:34.25#ibcon#about to read 5, iclass 29, count 0 2006.201.19:14:34.25#ibcon#read 5, iclass 29, count 0 2006.201.19:14:34.25#ibcon#about to read 6, iclass 29, count 0 2006.201.19:14:34.25#ibcon#read 6, iclass 29, count 0 2006.201.19:14:34.25#ibcon#end of sib2, iclass 29, count 0 2006.201.19:14:34.25#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:14:34.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:14:34.25#ibcon#[27=USB\r\n] 2006.201.19:14:34.25#ibcon#*before write, iclass 29, count 0 2006.201.19:14:34.25#ibcon#enter sib2, iclass 29, count 0 2006.201.19:14:34.25#ibcon#flushed, iclass 29, count 0 2006.201.19:14:34.25#ibcon#about to write, iclass 29, count 0 2006.201.19:14:34.25#ibcon#wrote, iclass 29, count 0 2006.201.19:14:34.25#ibcon#about to read 3, iclass 29, count 0 2006.201.19:14:34.28#ibcon#read 3, iclass 29, count 0 2006.201.19:14:34.28#ibcon#about to read 4, iclass 29, count 0 2006.201.19:14:34.28#ibcon#read 4, iclass 29, count 0 2006.201.19:14:34.28#ibcon#about to read 5, iclass 29, count 0 2006.201.19:14:34.28#ibcon#read 5, iclass 29, count 0 2006.201.19:14:34.28#ibcon#about to read 6, iclass 29, count 0 2006.201.19:14:34.28#ibcon#read 6, iclass 29, count 0 2006.201.19:14:34.28#ibcon#end of sib2, iclass 29, count 0 2006.201.19:14:34.28#ibcon#*after write, iclass 29, count 0 2006.201.19:14:34.28#ibcon#*before return 0, iclass 29, count 0 2006.201.19:14:34.28#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:34.28#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:14:34.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:14:34.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:14:34.28$vck44/vblo=6,719.99 2006.201.19:14:34.28#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.19:14:34.28#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.19:14:34.28#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:34.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:34.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:34.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:34.28#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:14:34.28#ibcon#first serial, iclass 31, count 0 2006.201.19:14:34.28#ibcon#enter sib2, iclass 31, count 0 2006.201.19:14:34.28#ibcon#flushed, iclass 31, count 0 2006.201.19:14:34.28#ibcon#about to write, iclass 31, count 0 2006.201.19:14:34.28#ibcon#wrote, iclass 31, count 0 2006.201.19:14:34.28#ibcon#about to read 3, iclass 31, count 0 2006.201.19:14:34.30#ibcon#read 3, iclass 31, count 0 2006.201.19:14:34.30#ibcon#about to read 4, iclass 31, count 0 2006.201.19:14:34.30#ibcon#read 4, iclass 31, count 0 2006.201.19:14:34.30#ibcon#about to read 5, iclass 31, count 0 2006.201.19:14:34.30#ibcon#read 5, iclass 31, count 0 2006.201.19:14:34.30#ibcon#about to read 6, iclass 31, count 0 2006.201.19:14:34.30#ibcon#read 6, iclass 31, count 0 2006.201.19:14:34.30#ibcon#end of sib2, iclass 31, count 0 2006.201.19:14:34.30#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:14:34.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:14:34.30#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:14:34.30#ibcon#*before write, iclass 31, count 0 2006.201.19:14:34.30#ibcon#enter sib2, iclass 31, count 0 2006.201.19:14:34.30#ibcon#flushed, iclass 31, count 0 2006.201.19:14:34.30#ibcon#about to write, iclass 31, count 0 2006.201.19:14:34.30#ibcon#wrote, iclass 31, count 0 2006.201.19:14:34.30#ibcon#about to read 3, iclass 31, count 0 2006.201.19:14:34.35#ibcon#read 3, iclass 31, count 0 2006.201.19:14:34.35#ibcon#about to read 4, iclass 31, count 0 2006.201.19:14:34.35#ibcon#read 4, iclass 31, count 0 2006.201.19:14:34.35#ibcon#about to read 5, iclass 31, count 0 2006.201.19:14:34.35#ibcon#read 5, iclass 31, count 0 2006.201.19:14:34.35#ibcon#about to read 6, iclass 31, count 0 2006.201.19:14:34.35#ibcon#read 6, iclass 31, count 0 2006.201.19:14:34.35#ibcon#end of sib2, iclass 31, count 0 2006.201.19:14:34.35#ibcon#*after write, iclass 31, count 0 2006.201.19:14:34.35#ibcon#*before return 0, iclass 31, count 0 2006.201.19:14:34.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:34.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:14:34.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:14:34.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:14:34.35$vck44/vb=6,4 2006.201.19:14:34.35#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.19:14:34.35#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.19:14:34.35#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:34.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:34.40#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:34.40#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:34.40#ibcon#enter wrdev, iclass 33, count 2 2006.201.19:14:34.40#ibcon#first serial, iclass 33, count 2 2006.201.19:14:34.40#ibcon#enter sib2, iclass 33, count 2 2006.201.19:14:34.40#ibcon#flushed, iclass 33, count 2 2006.201.19:14:34.40#ibcon#about to write, iclass 33, count 2 2006.201.19:14:34.40#ibcon#wrote, iclass 33, count 2 2006.201.19:14:34.40#ibcon#about to read 3, iclass 33, count 2 2006.201.19:14:34.42#ibcon#read 3, iclass 33, count 2 2006.201.19:14:34.42#ibcon#about to read 4, iclass 33, count 2 2006.201.19:14:34.42#ibcon#read 4, iclass 33, count 2 2006.201.19:14:34.42#ibcon#about to read 5, iclass 33, count 2 2006.201.19:14:34.42#ibcon#read 5, iclass 33, count 2 2006.201.19:14:34.42#ibcon#about to read 6, iclass 33, count 2 2006.201.19:14:34.42#ibcon#read 6, iclass 33, count 2 2006.201.19:14:34.42#ibcon#end of sib2, iclass 33, count 2 2006.201.19:14:34.42#ibcon#*mode == 0, iclass 33, count 2 2006.201.19:14:34.42#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.19:14:34.42#ibcon#[27=AT06-04\r\n] 2006.201.19:14:34.42#ibcon#*before write, iclass 33, count 2 2006.201.19:14:34.42#ibcon#enter sib2, iclass 33, count 2 2006.201.19:14:34.42#ibcon#flushed, iclass 33, count 2 2006.201.19:14:34.42#ibcon#about to write, iclass 33, count 2 2006.201.19:14:34.42#ibcon#wrote, iclass 33, count 2 2006.201.19:14:34.42#ibcon#about to read 3, iclass 33, count 2 2006.201.19:14:34.45#ibcon#read 3, iclass 33, count 2 2006.201.19:14:34.45#ibcon#about to read 4, iclass 33, count 2 2006.201.19:14:34.45#ibcon#read 4, iclass 33, count 2 2006.201.19:14:34.45#ibcon#about to read 5, iclass 33, count 2 2006.201.19:14:34.45#ibcon#read 5, iclass 33, count 2 2006.201.19:14:34.45#ibcon#about to read 6, iclass 33, count 2 2006.201.19:14:34.45#ibcon#read 6, iclass 33, count 2 2006.201.19:14:34.45#ibcon#end of sib2, iclass 33, count 2 2006.201.19:14:34.45#ibcon#*after write, iclass 33, count 2 2006.201.19:14:34.45#ibcon#*before return 0, iclass 33, count 2 2006.201.19:14:34.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:34.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:14:34.45#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.19:14:34.45#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:34.45#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:34.57#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:34.57#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:34.57#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:14:34.57#ibcon#first serial, iclass 33, count 0 2006.201.19:14:34.57#ibcon#enter sib2, iclass 33, count 0 2006.201.19:14:34.57#ibcon#flushed, iclass 33, count 0 2006.201.19:14:34.57#ibcon#about to write, iclass 33, count 0 2006.201.19:14:34.57#ibcon#wrote, iclass 33, count 0 2006.201.19:14:34.57#ibcon#about to read 3, iclass 33, count 0 2006.201.19:14:34.59#ibcon#read 3, iclass 33, count 0 2006.201.19:14:34.59#ibcon#about to read 4, iclass 33, count 0 2006.201.19:14:34.59#ibcon#read 4, iclass 33, count 0 2006.201.19:14:34.59#ibcon#about to read 5, iclass 33, count 0 2006.201.19:14:34.59#ibcon#read 5, iclass 33, count 0 2006.201.19:14:34.59#ibcon#about to read 6, iclass 33, count 0 2006.201.19:14:34.59#ibcon#read 6, iclass 33, count 0 2006.201.19:14:34.59#ibcon#end of sib2, iclass 33, count 0 2006.201.19:14:34.59#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:14:34.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:14:34.59#ibcon#[27=USB\r\n] 2006.201.19:14:34.59#ibcon#*before write, iclass 33, count 0 2006.201.19:14:34.59#ibcon#enter sib2, iclass 33, count 0 2006.201.19:14:34.59#ibcon#flushed, iclass 33, count 0 2006.201.19:14:34.59#ibcon#about to write, iclass 33, count 0 2006.201.19:14:34.59#ibcon#wrote, iclass 33, count 0 2006.201.19:14:34.59#ibcon#about to read 3, iclass 33, count 0 2006.201.19:14:34.62#ibcon#read 3, iclass 33, count 0 2006.201.19:14:34.62#ibcon#about to read 4, iclass 33, count 0 2006.201.19:14:34.62#ibcon#read 4, iclass 33, count 0 2006.201.19:14:34.62#ibcon#about to read 5, iclass 33, count 0 2006.201.19:14:34.62#ibcon#read 5, iclass 33, count 0 2006.201.19:14:34.62#ibcon#about to read 6, iclass 33, count 0 2006.201.19:14:34.62#ibcon#read 6, iclass 33, count 0 2006.201.19:14:34.62#ibcon#end of sib2, iclass 33, count 0 2006.201.19:14:34.62#ibcon#*after write, iclass 33, count 0 2006.201.19:14:34.62#ibcon#*before return 0, iclass 33, count 0 2006.201.19:14:34.62#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:34.62#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:14:34.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:14:34.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:14:34.62$vck44/vblo=7,734.99 2006.201.19:14:34.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.19:14:34.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.19:14:34.62#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:34.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:14:34.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:14:34.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:14:34.62#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:14:34.62#ibcon#first serial, iclass 35, count 0 2006.201.19:14:34.62#ibcon#enter sib2, iclass 35, count 0 2006.201.19:14:34.62#ibcon#flushed, iclass 35, count 0 2006.201.19:14:34.62#ibcon#about to write, iclass 35, count 0 2006.201.19:14:34.62#ibcon#wrote, iclass 35, count 0 2006.201.19:14:34.62#ibcon#about to read 3, iclass 35, count 0 2006.201.19:14:34.64#ibcon#read 3, iclass 35, count 0 2006.201.19:14:34.64#ibcon#about to read 4, iclass 35, count 0 2006.201.19:14:34.64#ibcon#read 4, iclass 35, count 0 2006.201.19:14:34.64#ibcon#about to read 5, iclass 35, count 0 2006.201.19:14:34.64#ibcon#read 5, iclass 35, count 0 2006.201.19:14:34.64#ibcon#about to read 6, iclass 35, count 0 2006.201.19:14:34.64#ibcon#read 6, iclass 35, count 0 2006.201.19:14:34.64#ibcon#end of sib2, iclass 35, count 0 2006.201.19:14:34.64#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:14:34.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:14:34.64#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:14:34.64#ibcon#*before write, iclass 35, count 0 2006.201.19:14:34.64#ibcon#enter sib2, iclass 35, count 0 2006.201.19:14:34.64#ibcon#flushed, iclass 35, count 0 2006.201.19:14:34.64#ibcon#about to write, iclass 35, count 0 2006.201.19:14:34.64#ibcon#wrote, iclass 35, count 0 2006.201.19:14:34.64#ibcon#about to read 3, iclass 35, count 0 2006.201.19:14:34.68#ibcon#read 3, iclass 35, count 0 2006.201.19:14:34.68#ibcon#about to read 4, iclass 35, count 0 2006.201.19:14:34.68#ibcon#read 4, iclass 35, count 0 2006.201.19:14:34.68#ibcon#about to read 5, iclass 35, count 0 2006.201.19:14:34.68#ibcon#read 5, iclass 35, count 0 2006.201.19:14:34.68#ibcon#about to read 6, iclass 35, count 0 2006.201.19:14:34.68#ibcon#read 6, iclass 35, count 0 2006.201.19:14:34.68#ibcon#end of sib2, iclass 35, count 0 2006.201.19:14:34.68#ibcon#*after write, iclass 35, count 0 2006.201.19:14:34.68#ibcon#*before return 0, iclass 35, count 0 2006.201.19:14:34.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:14:34.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:14:34.68#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:14:34.68#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:14:34.68$vck44/vb=7,4 2006.201.19:14:34.68#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.19:14:34.68#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.19:14:34.68#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:34.68#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:14:34.74#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:14:34.74#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:14:34.74#ibcon#enter wrdev, iclass 37, count 2 2006.201.19:14:34.74#ibcon#first serial, iclass 37, count 2 2006.201.19:14:34.74#ibcon#enter sib2, iclass 37, count 2 2006.201.19:14:34.74#ibcon#flushed, iclass 37, count 2 2006.201.19:14:34.74#ibcon#about to write, iclass 37, count 2 2006.201.19:14:34.74#ibcon#wrote, iclass 37, count 2 2006.201.19:14:34.74#ibcon#about to read 3, iclass 37, count 2 2006.201.19:14:34.76#ibcon#read 3, iclass 37, count 2 2006.201.19:14:34.76#ibcon#about to read 4, iclass 37, count 2 2006.201.19:14:34.76#ibcon#read 4, iclass 37, count 2 2006.201.19:14:34.76#ibcon#about to read 5, iclass 37, count 2 2006.201.19:14:34.76#ibcon#read 5, iclass 37, count 2 2006.201.19:14:34.76#ibcon#about to read 6, iclass 37, count 2 2006.201.19:14:34.76#ibcon#read 6, iclass 37, count 2 2006.201.19:14:34.76#ibcon#end of sib2, iclass 37, count 2 2006.201.19:14:34.76#ibcon#*mode == 0, iclass 37, count 2 2006.201.19:14:34.76#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.19:14:34.76#ibcon#[27=AT07-04\r\n] 2006.201.19:14:34.76#ibcon#*before write, iclass 37, count 2 2006.201.19:14:34.76#ibcon#enter sib2, iclass 37, count 2 2006.201.19:14:34.76#ibcon#flushed, iclass 37, count 2 2006.201.19:14:34.76#ibcon#about to write, iclass 37, count 2 2006.201.19:14:34.76#ibcon#wrote, iclass 37, count 2 2006.201.19:14:34.76#ibcon#about to read 3, iclass 37, count 2 2006.201.19:14:34.79#ibcon#read 3, iclass 37, count 2 2006.201.19:14:34.79#ibcon#about to read 4, iclass 37, count 2 2006.201.19:14:34.79#ibcon#read 4, iclass 37, count 2 2006.201.19:14:34.79#ibcon#about to read 5, iclass 37, count 2 2006.201.19:14:34.79#ibcon#read 5, iclass 37, count 2 2006.201.19:14:34.79#ibcon#about to read 6, iclass 37, count 2 2006.201.19:14:34.79#ibcon#read 6, iclass 37, count 2 2006.201.19:14:34.79#ibcon#end of sib2, iclass 37, count 2 2006.201.19:14:34.79#ibcon#*after write, iclass 37, count 2 2006.201.19:14:34.79#ibcon#*before return 0, iclass 37, count 2 2006.201.19:14:34.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:14:34.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:14:34.79#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.19:14:34.79#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:34.79#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:14:34.91#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:14:34.91#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:14:34.91#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:14:34.91#ibcon#first serial, iclass 37, count 0 2006.201.19:14:34.91#ibcon#enter sib2, iclass 37, count 0 2006.201.19:14:34.91#ibcon#flushed, iclass 37, count 0 2006.201.19:14:34.91#ibcon#about to write, iclass 37, count 0 2006.201.19:14:34.91#ibcon#wrote, iclass 37, count 0 2006.201.19:14:34.91#ibcon#about to read 3, iclass 37, count 0 2006.201.19:14:34.93#ibcon#read 3, iclass 37, count 0 2006.201.19:14:34.93#ibcon#about to read 4, iclass 37, count 0 2006.201.19:14:34.93#ibcon#read 4, iclass 37, count 0 2006.201.19:14:34.93#ibcon#about to read 5, iclass 37, count 0 2006.201.19:14:34.93#ibcon#read 5, iclass 37, count 0 2006.201.19:14:34.93#ibcon#about to read 6, iclass 37, count 0 2006.201.19:14:34.93#ibcon#read 6, iclass 37, count 0 2006.201.19:14:34.93#ibcon#end of sib2, iclass 37, count 0 2006.201.19:14:34.93#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:14:34.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:14:34.93#ibcon#[27=USB\r\n] 2006.201.19:14:34.93#ibcon#*before write, iclass 37, count 0 2006.201.19:14:34.93#ibcon#enter sib2, iclass 37, count 0 2006.201.19:14:34.93#ibcon#flushed, iclass 37, count 0 2006.201.19:14:34.93#ibcon#about to write, iclass 37, count 0 2006.201.19:14:34.93#ibcon#wrote, iclass 37, count 0 2006.201.19:14:34.93#ibcon#about to read 3, iclass 37, count 0 2006.201.19:14:34.96#ibcon#read 3, iclass 37, count 0 2006.201.19:14:34.96#ibcon#about to read 4, iclass 37, count 0 2006.201.19:14:34.96#ibcon#read 4, iclass 37, count 0 2006.201.19:14:34.96#ibcon#about to read 5, iclass 37, count 0 2006.201.19:14:34.96#ibcon#read 5, iclass 37, count 0 2006.201.19:14:34.96#ibcon#about to read 6, iclass 37, count 0 2006.201.19:14:34.96#ibcon#read 6, iclass 37, count 0 2006.201.19:14:34.96#ibcon#end of sib2, iclass 37, count 0 2006.201.19:14:34.96#ibcon#*after write, iclass 37, count 0 2006.201.19:14:34.96#ibcon#*before return 0, iclass 37, count 0 2006.201.19:14:34.96#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:14:34.96#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:14:34.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:14:34.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:14:34.96$vck44/vblo=8,744.99 2006.201.19:14:34.96#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.19:14:34.96#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.19:14:34.96#ibcon#ireg 17 cls_cnt 0 2006.201.19:14:34.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:34.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:34.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:34.96#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:14:34.96#ibcon#first serial, iclass 39, count 0 2006.201.19:14:34.96#ibcon#enter sib2, iclass 39, count 0 2006.201.19:14:34.96#ibcon#flushed, iclass 39, count 0 2006.201.19:14:34.96#ibcon#about to write, iclass 39, count 0 2006.201.19:14:34.96#ibcon#wrote, iclass 39, count 0 2006.201.19:14:34.96#ibcon#about to read 3, iclass 39, count 0 2006.201.19:14:34.98#ibcon#read 3, iclass 39, count 0 2006.201.19:14:34.98#ibcon#about to read 4, iclass 39, count 0 2006.201.19:14:34.98#ibcon#read 4, iclass 39, count 0 2006.201.19:14:34.98#ibcon#about to read 5, iclass 39, count 0 2006.201.19:14:34.98#ibcon#read 5, iclass 39, count 0 2006.201.19:14:34.98#ibcon#about to read 6, iclass 39, count 0 2006.201.19:14:34.98#ibcon#read 6, iclass 39, count 0 2006.201.19:14:34.98#ibcon#end of sib2, iclass 39, count 0 2006.201.19:14:34.98#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:14:34.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:14:34.98#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:14:34.98#ibcon#*before write, iclass 39, count 0 2006.201.19:14:34.98#ibcon#enter sib2, iclass 39, count 0 2006.201.19:14:34.98#ibcon#flushed, iclass 39, count 0 2006.201.19:14:34.98#ibcon#about to write, iclass 39, count 0 2006.201.19:14:34.98#ibcon#wrote, iclass 39, count 0 2006.201.19:14:34.98#ibcon#about to read 3, iclass 39, count 0 2006.201.19:14:35.02#ibcon#read 3, iclass 39, count 0 2006.201.19:14:35.02#ibcon#about to read 4, iclass 39, count 0 2006.201.19:14:35.02#ibcon#read 4, iclass 39, count 0 2006.201.19:14:35.02#ibcon#about to read 5, iclass 39, count 0 2006.201.19:14:35.02#ibcon#read 5, iclass 39, count 0 2006.201.19:14:35.02#ibcon#about to read 6, iclass 39, count 0 2006.201.19:14:35.02#ibcon#read 6, iclass 39, count 0 2006.201.19:14:35.02#ibcon#end of sib2, iclass 39, count 0 2006.201.19:14:35.02#ibcon#*after write, iclass 39, count 0 2006.201.19:14:35.02#ibcon#*before return 0, iclass 39, count 0 2006.201.19:14:35.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:35.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:14:35.02#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:14:35.02#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:14:35.02$vck44/vb=8,4 2006.201.19:14:35.02#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.19:14:35.02#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.19:14:35.02#ibcon#ireg 11 cls_cnt 2 2006.201.19:14:35.02#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:35.08#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:35.08#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:35.08#ibcon#enter wrdev, iclass 2, count 2 2006.201.19:14:35.08#ibcon#first serial, iclass 2, count 2 2006.201.19:14:35.08#ibcon#enter sib2, iclass 2, count 2 2006.201.19:14:35.08#ibcon#flushed, iclass 2, count 2 2006.201.19:14:35.08#ibcon#about to write, iclass 2, count 2 2006.201.19:14:35.08#ibcon#wrote, iclass 2, count 2 2006.201.19:14:35.08#ibcon#about to read 3, iclass 2, count 2 2006.201.19:14:35.10#ibcon#read 3, iclass 2, count 2 2006.201.19:14:35.10#ibcon#about to read 4, iclass 2, count 2 2006.201.19:14:35.10#ibcon#read 4, iclass 2, count 2 2006.201.19:14:35.10#ibcon#about to read 5, iclass 2, count 2 2006.201.19:14:35.10#ibcon#read 5, iclass 2, count 2 2006.201.19:14:35.10#ibcon#about to read 6, iclass 2, count 2 2006.201.19:14:35.10#ibcon#read 6, iclass 2, count 2 2006.201.19:14:35.10#ibcon#end of sib2, iclass 2, count 2 2006.201.19:14:35.10#ibcon#*mode == 0, iclass 2, count 2 2006.201.19:14:35.10#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.19:14:35.10#ibcon#[27=AT08-04\r\n] 2006.201.19:14:35.10#ibcon#*before write, iclass 2, count 2 2006.201.19:14:35.10#ibcon#enter sib2, iclass 2, count 2 2006.201.19:14:35.10#ibcon#flushed, iclass 2, count 2 2006.201.19:14:35.10#ibcon#about to write, iclass 2, count 2 2006.201.19:14:35.10#ibcon#wrote, iclass 2, count 2 2006.201.19:14:35.10#ibcon#about to read 3, iclass 2, count 2 2006.201.19:14:35.13#ibcon#read 3, iclass 2, count 2 2006.201.19:14:35.13#ibcon#about to read 4, iclass 2, count 2 2006.201.19:14:35.13#ibcon#read 4, iclass 2, count 2 2006.201.19:14:35.13#ibcon#about to read 5, iclass 2, count 2 2006.201.19:14:35.13#ibcon#read 5, iclass 2, count 2 2006.201.19:14:35.13#ibcon#about to read 6, iclass 2, count 2 2006.201.19:14:35.13#ibcon#read 6, iclass 2, count 2 2006.201.19:14:35.13#ibcon#end of sib2, iclass 2, count 2 2006.201.19:14:35.13#ibcon#*after write, iclass 2, count 2 2006.201.19:14:35.13#ibcon#*before return 0, iclass 2, count 2 2006.201.19:14:35.13#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:35.13#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:14:35.13#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.19:14:35.13#ibcon#ireg 7 cls_cnt 0 2006.201.19:14:35.13#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:35.25#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:35.25#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:35.25#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:14:35.25#ibcon#first serial, iclass 2, count 0 2006.201.19:14:35.25#ibcon#enter sib2, iclass 2, count 0 2006.201.19:14:35.25#ibcon#flushed, iclass 2, count 0 2006.201.19:14:35.25#ibcon#about to write, iclass 2, count 0 2006.201.19:14:35.25#ibcon#wrote, iclass 2, count 0 2006.201.19:14:35.25#ibcon#about to read 3, iclass 2, count 0 2006.201.19:14:35.27#ibcon#read 3, iclass 2, count 0 2006.201.19:14:35.27#ibcon#about to read 4, iclass 2, count 0 2006.201.19:14:35.27#ibcon#read 4, iclass 2, count 0 2006.201.19:14:35.27#ibcon#about to read 5, iclass 2, count 0 2006.201.19:14:35.27#ibcon#read 5, iclass 2, count 0 2006.201.19:14:35.27#ibcon#about to read 6, iclass 2, count 0 2006.201.19:14:35.27#ibcon#read 6, iclass 2, count 0 2006.201.19:14:35.27#ibcon#end of sib2, iclass 2, count 0 2006.201.19:14:35.27#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:14:35.27#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:14:35.27#ibcon#[27=USB\r\n] 2006.201.19:14:35.27#ibcon#*before write, iclass 2, count 0 2006.201.19:14:35.27#ibcon#enter sib2, iclass 2, count 0 2006.201.19:14:35.27#ibcon#flushed, iclass 2, count 0 2006.201.19:14:35.27#ibcon#about to write, iclass 2, count 0 2006.201.19:14:35.27#ibcon#wrote, iclass 2, count 0 2006.201.19:14:35.27#ibcon#about to read 3, iclass 2, count 0 2006.201.19:14:35.30#ibcon#read 3, iclass 2, count 0 2006.201.19:14:35.30#ibcon#about to read 4, iclass 2, count 0 2006.201.19:14:35.30#ibcon#read 4, iclass 2, count 0 2006.201.19:14:35.30#ibcon#about to read 5, iclass 2, count 0 2006.201.19:14:35.30#ibcon#read 5, iclass 2, count 0 2006.201.19:14:35.30#ibcon#about to read 6, iclass 2, count 0 2006.201.19:14:35.30#ibcon#read 6, iclass 2, count 0 2006.201.19:14:35.30#ibcon#end of sib2, iclass 2, count 0 2006.201.19:14:35.30#ibcon#*after write, iclass 2, count 0 2006.201.19:14:35.30#ibcon#*before return 0, iclass 2, count 0 2006.201.19:14:35.30#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:35.30#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:14:35.30#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:14:35.30#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:14:35.30$vck44/vabw=wide 2006.201.19:14:35.30#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.19:14:35.30#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.19:14:35.30#ibcon#ireg 8 cls_cnt 0 2006.201.19:14:35.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:35.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:35.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:35.30#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:14:35.30#ibcon#first serial, iclass 5, count 0 2006.201.19:14:35.30#ibcon#enter sib2, iclass 5, count 0 2006.201.19:14:35.30#ibcon#flushed, iclass 5, count 0 2006.201.19:14:35.30#ibcon#about to write, iclass 5, count 0 2006.201.19:14:35.30#ibcon#wrote, iclass 5, count 0 2006.201.19:14:35.30#ibcon#about to read 3, iclass 5, count 0 2006.201.19:14:35.32#ibcon#read 3, iclass 5, count 0 2006.201.19:14:35.32#ibcon#about to read 4, iclass 5, count 0 2006.201.19:14:35.32#ibcon#read 4, iclass 5, count 0 2006.201.19:14:35.32#ibcon#about to read 5, iclass 5, count 0 2006.201.19:14:35.32#ibcon#read 5, iclass 5, count 0 2006.201.19:14:35.32#ibcon#about to read 6, iclass 5, count 0 2006.201.19:14:35.32#ibcon#read 6, iclass 5, count 0 2006.201.19:14:35.32#ibcon#end of sib2, iclass 5, count 0 2006.201.19:14:35.32#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:14:35.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:14:35.32#ibcon#[25=BW32\r\n] 2006.201.19:14:35.32#ibcon#*before write, iclass 5, count 0 2006.201.19:14:35.32#ibcon#enter sib2, iclass 5, count 0 2006.201.19:14:35.32#ibcon#flushed, iclass 5, count 0 2006.201.19:14:35.32#ibcon#about to write, iclass 5, count 0 2006.201.19:14:35.32#ibcon#wrote, iclass 5, count 0 2006.201.19:14:35.32#ibcon#about to read 3, iclass 5, count 0 2006.201.19:14:35.36#ibcon#read 3, iclass 5, count 0 2006.201.19:14:35.36#ibcon#about to read 4, iclass 5, count 0 2006.201.19:14:35.36#ibcon#read 4, iclass 5, count 0 2006.201.19:14:35.36#ibcon#about to read 5, iclass 5, count 0 2006.201.19:14:35.36#ibcon#read 5, iclass 5, count 0 2006.201.19:14:35.36#ibcon#about to read 6, iclass 5, count 0 2006.201.19:14:35.36#ibcon#read 6, iclass 5, count 0 2006.201.19:14:35.36#ibcon#end of sib2, iclass 5, count 0 2006.201.19:14:35.36#ibcon#*after write, iclass 5, count 0 2006.201.19:14:35.36#ibcon#*before return 0, iclass 5, count 0 2006.201.19:14:35.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:35.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:14:35.36#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:14:35.36#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:14:35.36$vck44/vbbw=wide 2006.201.19:14:35.36#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.19:14:35.36#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.19:14:35.36#ibcon#ireg 8 cls_cnt 0 2006.201.19:14:35.36#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:14:35.42#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:14:35.42#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:14:35.42#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:14:35.42#ibcon#first serial, iclass 7, count 0 2006.201.19:14:35.42#ibcon#enter sib2, iclass 7, count 0 2006.201.19:14:35.42#ibcon#flushed, iclass 7, count 0 2006.201.19:14:35.42#ibcon#about to write, iclass 7, count 0 2006.201.19:14:35.42#ibcon#wrote, iclass 7, count 0 2006.201.19:14:35.42#ibcon#about to read 3, iclass 7, count 0 2006.201.19:14:35.44#ibcon#read 3, iclass 7, count 0 2006.201.19:14:35.44#ibcon#about to read 4, iclass 7, count 0 2006.201.19:14:35.44#ibcon#read 4, iclass 7, count 0 2006.201.19:14:35.44#ibcon#about to read 5, iclass 7, count 0 2006.201.19:14:35.44#ibcon#read 5, iclass 7, count 0 2006.201.19:14:35.44#ibcon#about to read 6, iclass 7, count 0 2006.201.19:14:35.44#ibcon#read 6, iclass 7, count 0 2006.201.19:14:35.44#ibcon#end of sib2, iclass 7, count 0 2006.201.19:14:35.44#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:14:35.44#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:14:35.44#ibcon#[27=BW32\r\n] 2006.201.19:14:35.44#ibcon#*before write, iclass 7, count 0 2006.201.19:14:35.44#ibcon#enter sib2, iclass 7, count 0 2006.201.19:14:35.44#ibcon#flushed, iclass 7, count 0 2006.201.19:14:35.44#ibcon#about to write, iclass 7, count 0 2006.201.19:14:35.44#ibcon#wrote, iclass 7, count 0 2006.201.19:14:35.44#ibcon#about to read 3, iclass 7, count 0 2006.201.19:14:35.47#ibcon#read 3, iclass 7, count 0 2006.201.19:14:35.47#ibcon#about to read 4, iclass 7, count 0 2006.201.19:14:35.47#ibcon#read 4, iclass 7, count 0 2006.201.19:14:35.47#ibcon#about to read 5, iclass 7, count 0 2006.201.19:14:35.47#ibcon#read 5, iclass 7, count 0 2006.201.19:14:35.47#ibcon#about to read 6, iclass 7, count 0 2006.201.19:14:35.47#ibcon#read 6, iclass 7, count 0 2006.201.19:14:35.47#ibcon#end of sib2, iclass 7, count 0 2006.201.19:14:35.47#ibcon#*after write, iclass 7, count 0 2006.201.19:14:35.47#ibcon#*before return 0, iclass 7, count 0 2006.201.19:14:35.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:14:35.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:14:35.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:14:35.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:14:35.47$setupk4/ifdk4 2006.201.19:14:35.47$ifdk4/lo= 2006.201.19:14:35.47$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:14:35.47$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:14:35.47$ifdk4/patch= 2006.201.19:14:35.47$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:14:35.47$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:14:35.47$setupk4/!*+20s 2006.201.19:14:41.95#abcon#<5=/04 0.9 2.4 20.501001002.3\r\n> 2006.201.19:14:41.97#abcon#{5=INTERFACE CLEAR} 2006.201.19:14:42.03#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:14:49.94$setupk4/"tpicd 2006.201.19:14:49.94$setupk4/echo=off 2006.201.19:14:49.94$setupk4/xlog=off 2006.201.19:14:49.94:!2006.201.19:16:06 2006.201.19:14:59.14#trakl#Source acquired 2006.201.19:14:59.14#flagr#flagr/antenna,acquired 2006.201.19:16:06.00:preob 2006.201.19:16:06.14/onsource/TRACKING 2006.201.19:16:06.14:!2006.201.19:16:16 2006.201.19:16:16.00:"tape 2006.201.19:16:16.00:"st=record 2006.201.19:16:16.00:data_valid=on 2006.201.19:16:16.00:midob 2006.201.19:16:17.14/onsource/TRACKING 2006.201.19:16:17.14/wx/20.49,1002.4,100 2006.201.19:16:17.28/cable/+6.4793E-03 2006.201.19:16:18.37/va/01,08,usb,yes,58,62 2006.201.19:16:18.37/va/02,07,usb,yes,63,64 2006.201.19:16:18.37/va/03,08,usb,yes,57,59 2006.201.19:16:18.37/va/04,07,usb,yes,64,68 2006.201.19:16:18.37/va/05,04,usb,yes,58,59 2006.201.19:16:18.37/va/06,05,usb,yes,58,58 2006.201.19:16:18.37/va/07,05,usb,yes,57,58 2006.201.19:16:18.37/va/08,04,usb,yes,56,66 2006.201.19:16:18.60/valo/01,524.99,yes,locked 2006.201.19:16:18.60/valo/02,534.99,yes,locked 2006.201.19:16:18.60/valo/03,564.99,yes,locked 2006.201.19:16:18.60/valo/04,624.99,yes,locked 2006.201.19:16:18.60/valo/05,734.99,yes,locked 2006.201.19:16:18.60/valo/06,814.99,yes,locked 2006.201.19:16:18.60/valo/07,864.99,yes,locked 2006.201.19:16:18.60/valo/08,884.99,yes,locked 2006.201.19:16:19.69/vb/01,04,usb,yes,33,31 2006.201.19:16:19.69/vb/02,05,usb,yes,31,31 2006.201.19:16:19.69/vb/03,04,usb,yes,33,36 2006.201.19:16:19.69/vb/04,05,usb,yes,33,32 2006.201.19:16:19.69/vb/05,04,usb,yes,29,32 2006.201.19:16:19.69/vb/06,04,usb,yes,34,30 2006.201.19:16:19.69/vb/07,04,usb,yes,34,34 2006.201.19:16:19.69/vb/08,04,usb,yes,31,35 2006.201.19:16:19.92/vblo/01,629.99,yes,locked 2006.201.19:16:19.92/vblo/02,634.99,yes,locked 2006.201.19:16:19.92/vblo/03,649.99,yes,locked 2006.201.19:16:19.92/vblo/04,679.99,yes,locked 2006.201.19:16:19.92/vblo/05,709.99,yes,locked 2006.201.19:16:19.92/vblo/06,719.99,yes,locked 2006.201.19:16:19.92/vblo/07,734.99,yes,locked 2006.201.19:16:19.92/vblo/08,744.99,yes,locked 2006.201.19:16:20.07/vabw/8 2006.201.19:16:20.22/vbbw/8 2006.201.19:16:20.31/xfe/off,on,16.5 2006.201.19:16:20.70/ifatt/23,28,28,28 2006.201.19:16:21.06/fmout-gps/S +4.50E-07 2006.201.19:16:21.10:!2006.201.19:16:56 2006.201.19:16:56.00:data_valid=off 2006.201.19:16:56.00:"et 2006.201.19:16:56.00:!+3s 2006.201.19:16:59.01:"tape 2006.201.19:16:59.01:postob 2006.201.19:16:59.17/cable/+6.4795E-03 2006.201.19:16:59.17/wx/20.49,1002.4,100 2006.201.19:16:59.23/fmout-gps/S +4.51E-07 2006.201.19:16:59.23:scan_name=201-1917,jd0607,180 2006.201.19:16:59.23:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.201.19:17:01.14#flagr#flagr/antenna,new-source 2006.201.19:17:01.14:checkk5 2006.201.19:17:01.49/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:17:01.86/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:17:02.23/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:17:02.60/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:17:02.97/chk_obsdata//k5ts1/T2011916??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:17:03.34/chk_obsdata//k5ts2/T2011916??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:17:03.70/chk_obsdata//k5ts3/T2011916??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:17:04.06/chk_obsdata//k5ts4/T2011916??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:17:04.75/k5log//k5ts1_log_newline 2006.201.19:17:05.43/k5log//k5ts2_log_newline 2006.201.19:17:06.12/k5log//k5ts3_log_newline 2006.201.19:17:06.81/k5log//k5ts4_log_newline 2006.201.19:17:06.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:17:06.83:setupk4=1 2006.201.19:17:06.83$setupk4/echo=on 2006.201.19:17:06.83$setupk4/pcalon 2006.201.19:17:06.84$pcalon/"no phase cal control is implemented here 2006.201.19:17:06.84$setupk4/"tpicd=stop 2006.201.19:17:06.84$setupk4/"rec=synch_on 2006.201.19:17:06.84$setupk4/"rec_mode=128 2006.201.19:17:06.84$setupk4/!* 2006.201.19:17:06.84$setupk4/recpk4 2006.201.19:17:06.84$recpk4/recpatch= 2006.201.19:17:06.84$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:17:06.84$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:17:06.84$setupk4/vck44 2006.201.19:17:06.84$vck44/valo=1,524.99 2006.201.19:17:06.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.19:17:06.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.19:17:06.84#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:06.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:06.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:06.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:06.84#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:17:06.84#ibcon#first serial, iclass 38, count 0 2006.201.19:17:06.84#ibcon#enter sib2, iclass 38, count 0 2006.201.19:17:06.84#ibcon#flushed, iclass 38, count 0 2006.201.19:17:06.84#ibcon#about to write, iclass 38, count 0 2006.201.19:17:06.84#ibcon#wrote, iclass 38, count 0 2006.201.19:17:06.84#ibcon#about to read 3, iclass 38, count 0 2006.201.19:17:06.88#ibcon#read 3, iclass 38, count 0 2006.201.19:17:06.88#ibcon#about to read 4, iclass 38, count 0 2006.201.19:17:06.88#ibcon#read 4, iclass 38, count 0 2006.201.19:17:06.88#ibcon#about to read 5, iclass 38, count 0 2006.201.19:17:06.88#ibcon#read 5, iclass 38, count 0 2006.201.19:17:06.88#ibcon#about to read 6, iclass 38, count 0 2006.201.19:17:06.88#ibcon#read 6, iclass 38, count 0 2006.201.19:17:06.88#ibcon#end of sib2, iclass 38, count 0 2006.201.19:17:06.88#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:17:06.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:17:06.88#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:17:06.88#ibcon#*before write, iclass 38, count 0 2006.201.19:17:06.88#ibcon#enter sib2, iclass 38, count 0 2006.201.19:17:06.88#ibcon#flushed, iclass 38, count 0 2006.201.19:17:06.88#ibcon#about to write, iclass 38, count 0 2006.201.19:17:06.88#ibcon#wrote, iclass 38, count 0 2006.201.19:17:06.88#ibcon#about to read 3, iclass 38, count 0 2006.201.19:17:06.93#ibcon#read 3, iclass 38, count 0 2006.201.19:17:06.93#ibcon#about to read 4, iclass 38, count 0 2006.201.19:17:06.93#ibcon#read 4, iclass 38, count 0 2006.201.19:17:06.93#ibcon#about to read 5, iclass 38, count 0 2006.201.19:17:06.93#ibcon#read 5, iclass 38, count 0 2006.201.19:17:06.93#ibcon#about to read 6, iclass 38, count 0 2006.201.19:17:06.93#ibcon#read 6, iclass 38, count 0 2006.201.19:17:06.93#ibcon#end of sib2, iclass 38, count 0 2006.201.19:17:06.93#ibcon#*after write, iclass 38, count 0 2006.201.19:17:06.93#ibcon#*before return 0, iclass 38, count 0 2006.201.19:17:06.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:06.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:06.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:17:06.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:17:06.93$vck44/va=1,8 2006.201.19:17:06.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.19:17:06.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.19:17:06.93#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:06.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:06.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:06.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:06.93#ibcon#enter wrdev, iclass 40, count 2 2006.201.19:17:06.93#ibcon#first serial, iclass 40, count 2 2006.201.19:17:06.93#ibcon#enter sib2, iclass 40, count 2 2006.201.19:17:06.93#ibcon#flushed, iclass 40, count 2 2006.201.19:17:06.93#ibcon#about to write, iclass 40, count 2 2006.201.19:17:06.93#ibcon#wrote, iclass 40, count 2 2006.201.19:17:06.93#ibcon#about to read 3, iclass 40, count 2 2006.201.19:17:06.95#ibcon#read 3, iclass 40, count 2 2006.201.19:17:06.95#ibcon#about to read 4, iclass 40, count 2 2006.201.19:17:06.95#ibcon#read 4, iclass 40, count 2 2006.201.19:17:06.95#ibcon#about to read 5, iclass 40, count 2 2006.201.19:17:06.95#ibcon#read 5, iclass 40, count 2 2006.201.19:17:06.95#ibcon#about to read 6, iclass 40, count 2 2006.201.19:17:06.95#ibcon#read 6, iclass 40, count 2 2006.201.19:17:06.95#ibcon#end of sib2, iclass 40, count 2 2006.201.19:17:06.95#ibcon#*mode == 0, iclass 40, count 2 2006.201.19:17:06.95#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.19:17:06.95#ibcon#[25=AT01-08\r\n] 2006.201.19:17:06.95#ibcon#*before write, iclass 40, count 2 2006.201.19:17:06.95#ibcon#enter sib2, iclass 40, count 2 2006.201.19:17:06.95#ibcon#flushed, iclass 40, count 2 2006.201.19:17:06.95#ibcon#about to write, iclass 40, count 2 2006.201.19:17:06.95#ibcon#wrote, iclass 40, count 2 2006.201.19:17:06.95#ibcon#about to read 3, iclass 40, count 2 2006.201.19:17:06.99#ibcon#read 3, iclass 40, count 2 2006.201.19:17:06.99#ibcon#about to read 4, iclass 40, count 2 2006.201.19:17:06.99#ibcon#read 4, iclass 40, count 2 2006.201.19:17:06.99#ibcon#about to read 5, iclass 40, count 2 2006.201.19:17:06.99#ibcon#read 5, iclass 40, count 2 2006.201.19:17:06.99#ibcon#about to read 6, iclass 40, count 2 2006.201.19:17:06.99#ibcon#read 6, iclass 40, count 2 2006.201.19:17:06.99#ibcon#end of sib2, iclass 40, count 2 2006.201.19:17:06.99#ibcon#*after write, iclass 40, count 2 2006.201.19:17:06.99#ibcon#*before return 0, iclass 40, count 2 2006.201.19:17:06.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:06.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:06.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.19:17:06.99#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:06.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:07.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:07.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:07.11#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:17:07.11#ibcon#first serial, iclass 40, count 0 2006.201.19:17:07.11#ibcon#enter sib2, iclass 40, count 0 2006.201.19:17:07.11#ibcon#flushed, iclass 40, count 0 2006.201.19:17:07.11#ibcon#about to write, iclass 40, count 0 2006.201.19:17:07.11#ibcon#wrote, iclass 40, count 0 2006.201.19:17:07.11#ibcon#about to read 3, iclass 40, count 0 2006.201.19:17:07.13#ibcon#read 3, iclass 40, count 0 2006.201.19:17:07.13#ibcon#about to read 4, iclass 40, count 0 2006.201.19:17:07.13#ibcon#read 4, iclass 40, count 0 2006.201.19:17:07.13#ibcon#about to read 5, iclass 40, count 0 2006.201.19:17:07.13#ibcon#read 5, iclass 40, count 0 2006.201.19:17:07.13#ibcon#about to read 6, iclass 40, count 0 2006.201.19:17:07.13#ibcon#read 6, iclass 40, count 0 2006.201.19:17:07.13#ibcon#end of sib2, iclass 40, count 0 2006.201.19:17:07.13#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:17:07.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:17:07.13#ibcon#[25=USB\r\n] 2006.201.19:17:07.13#ibcon#*before write, iclass 40, count 0 2006.201.19:17:07.13#ibcon#enter sib2, iclass 40, count 0 2006.201.19:17:07.13#ibcon#flushed, iclass 40, count 0 2006.201.19:17:07.13#ibcon#about to write, iclass 40, count 0 2006.201.19:17:07.13#ibcon#wrote, iclass 40, count 0 2006.201.19:17:07.13#ibcon#about to read 3, iclass 40, count 0 2006.201.19:17:07.16#ibcon#read 3, iclass 40, count 0 2006.201.19:17:07.16#ibcon#about to read 4, iclass 40, count 0 2006.201.19:17:07.16#ibcon#read 4, iclass 40, count 0 2006.201.19:17:07.16#ibcon#about to read 5, iclass 40, count 0 2006.201.19:17:07.16#ibcon#read 5, iclass 40, count 0 2006.201.19:17:07.16#ibcon#about to read 6, iclass 40, count 0 2006.201.19:17:07.16#ibcon#read 6, iclass 40, count 0 2006.201.19:17:07.16#ibcon#end of sib2, iclass 40, count 0 2006.201.19:17:07.16#ibcon#*after write, iclass 40, count 0 2006.201.19:17:07.16#ibcon#*before return 0, iclass 40, count 0 2006.201.19:17:07.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:07.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:07.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:17:07.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:17:07.16$vck44/valo=2,534.99 2006.201.19:17:07.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.19:17:07.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.19:17:07.16#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:07.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:07.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:07.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:07.16#ibcon#enter wrdev, iclass 4, count 0 2006.201.19:17:07.16#ibcon#first serial, iclass 4, count 0 2006.201.19:17:07.16#ibcon#enter sib2, iclass 4, count 0 2006.201.19:17:07.16#ibcon#flushed, iclass 4, count 0 2006.201.19:17:07.16#ibcon#about to write, iclass 4, count 0 2006.201.19:17:07.16#ibcon#wrote, iclass 4, count 0 2006.201.19:17:07.16#ibcon#about to read 3, iclass 4, count 0 2006.201.19:17:07.18#ibcon#read 3, iclass 4, count 0 2006.201.19:17:07.18#ibcon#about to read 4, iclass 4, count 0 2006.201.19:17:07.18#ibcon#read 4, iclass 4, count 0 2006.201.19:17:07.18#ibcon#about to read 5, iclass 4, count 0 2006.201.19:17:07.18#ibcon#read 5, iclass 4, count 0 2006.201.19:17:07.18#ibcon#about to read 6, iclass 4, count 0 2006.201.19:17:07.18#ibcon#read 6, iclass 4, count 0 2006.201.19:17:07.18#ibcon#end of sib2, iclass 4, count 0 2006.201.19:17:07.18#ibcon#*mode == 0, iclass 4, count 0 2006.201.19:17:07.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.19:17:07.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:17:07.18#ibcon#*before write, iclass 4, count 0 2006.201.19:17:07.18#ibcon#enter sib2, iclass 4, count 0 2006.201.19:17:07.18#ibcon#flushed, iclass 4, count 0 2006.201.19:17:07.18#ibcon#about to write, iclass 4, count 0 2006.201.19:17:07.18#ibcon#wrote, iclass 4, count 0 2006.201.19:17:07.18#ibcon#about to read 3, iclass 4, count 0 2006.201.19:17:07.22#ibcon#read 3, iclass 4, count 0 2006.201.19:17:07.22#ibcon#about to read 4, iclass 4, count 0 2006.201.19:17:07.22#ibcon#read 4, iclass 4, count 0 2006.201.19:17:07.22#ibcon#about to read 5, iclass 4, count 0 2006.201.19:17:07.22#ibcon#read 5, iclass 4, count 0 2006.201.19:17:07.22#ibcon#about to read 6, iclass 4, count 0 2006.201.19:17:07.22#ibcon#read 6, iclass 4, count 0 2006.201.19:17:07.22#ibcon#end of sib2, iclass 4, count 0 2006.201.19:17:07.22#ibcon#*after write, iclass 4, count 0 2006.201.19:17:07.22#ibcon#*before return 0, iclass 4, count 0 2006.201.19:17:07.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:07.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:07.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.19:17:07.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.19:17:07.22$vck44/va=2,7 2006.201.19:17:07.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.19:17:07.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.19:17:07.22#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:07.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:07.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:07.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:07.28#ibcon#enter wrdev, iclass 6, count 2 2006.201.19:17:07.28#ibcon#first serial, iclass 6, count 2 2006.201.19:17:07.28#ibcon#enter sib2, iclass 6, count 2 2006.201.19:17:07.28#ibcon#flushed, iclass 6, count 2 2006.201.19:17:07.28#ibcon#about to write, iclass 6, count 2 2006.201.19:17:07.28#ibcon#wrote, iclass 6, count 2 2006.201.19:17:07.28#ibcon#about to read 3, iclass 6, count 2 2006.201.19:17:07.30#ibcon#read 3, iclass 6, count 2 2006.201.19:17:07.30#ibcon#about to read 4, iclass 6, count 2 2006.201.19:17:07.30#ibcon#read 4, iclass 6, count 2 2006.201.19:17:07.30#ibcon#about to read 5, iclass 6, count 2 2006.201.19:17:07.30#ibcon#read 5, iclass 6, count 2 2006.201.19:17:07.30#ibcon#about to read 6, iclass 6, count 2 2006.201.19:17:07.30#ibcon#read 6, iclass 6, count 2 2006.201.19:17:07.30#ibcon#end of sib2, iclass 6, count 2 2006.201.19:17:07.30#ibcon#*mode == 0, iclass 6, count 2 2006.201.19:17:07.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.19:17:07.30#ibcon#[25=AT02-07\r\n] 2006.201.19:17:07.30#ibcon#*before write, iclass 6, count 2 2006.201.19:17:07.30#ibcon#enter sib2, iclass 6, count 2 2006.201.19:17:07.30#ibcon#flushed, iclass 6, count 2 2006.201.19:17:07.30#ibcon#about to write, iclass 6, count 2 2006.201.19:17:07.30#ibcon#wrote, iclass 6, count 2 2006.201.19:17:07.30#ibcon#about to read 3, iclass 6, count 2 2006.201.19:17:07.33#ibcon#read 3, iclass 6, count 2 2006.201.19:17:07.33#ibcon#about to read 4, iclass 6, count 2 2006.201.19:17:07.33#ibcon#read 4, iclass 6, count 2 2006.201.19:17:07.33#ibcon#about to read 5, iclass 6, count 2 2006.201.19:17:07.33#ibcon#read 5, iclass 6, count 2 2006.201.19:17:07.33#ibcon#about to read 6, iclass 6, count 2 2006.201.19:17:07.33#ibcon#read 6, iclass 6, count 2 2006.201.19:17:07.33#ibcon#end of sib2, iclass 6, count 2 2006.201.19:17:07.33#ibcon#*after write, iclass 6, count 2 2006.201.19:17:07.33#ibcon#*before return 0, iclass 6, count 2 2006.201.19:17:07.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:07.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:07.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.19:17:07.33#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:07.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:07.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:07.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:07.45#ibcon#enter wrdev, iclass 6, count 0 2006.201.19:17:07.45#ibcon#first serial, iclass 6, count 0 2006.201.19:17:07.45#ibcon#enter sib2, iclass 6, count 0 2006.201.19:17:07.45#ibcon#flushed, iclass 6, count 0 2006.201.19:17:07.45#ibcon#about to write, iclass 6, count 0 2006.201.19:17:07.45#ibcon#wrote, iclass 6, count 0 2006.201.19:17:07.45#ibcon#about to read 3, iclass 6, count 0 2006.201.19:17:07.47#ibcon#read 3, iclass 6, count 0 2006.201.19:17:07.47#ibcon#about to read 4, iclass 6, count 0 2006.201.19:17:07.47#ibcon#read 4, iclass 6, count 0 2006.201.19:17:07.47#ibcon#about to read 5, iclass 6, count 0 2006.201.19:17:07.47#ibcon#read 5, iclass 6, count 0 2006.201.19:17:07.47#ibcon#about to read 6, iclass 6, count 0 2006.201.19:17:07.47#ibcon#read 6, iclass 6, count 0 2006.201.19:17:07.47#ibcon#end of sib2, iclass 6, count 0 2006.201.19:17:07.47#ibcon#*mode == 0, iclass 6, count 0 2006.201.19:17:07.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.19:17:07.47#ibcon#[25=USB\r\n] 2006.201.19:17:07.47#ibcon#*before write, iclass 6, count 0 2006.201.19:17:07.47#ibcon#enter sib2, iclass 6, count 0 2006.201.19:17:07.47#ibcon#flushed, iclass 6, count 0 2006.201.19:17:07.47#ibcon#about to write, iclass 6, count 0 2006.201.19:17:07.47#ibcon#wrote, iclass 6, count 0 2006.201.19:17:07.47#ibcon#about to read 3, iclass 6, count 0 2006.201.19:17:07.50#ibcon#read 3, iclass 6, count 0 2006.201.19:17:07.50#ibcon#about to read 4, iclass 6, count 0 2006.201.19:17:07.50#ibcon#read 4, iclass 6, count 0 2006.201.19:17:07.50#ibcon#about to read 5, iclass 6, count 0 2006.201.19:17:07.50#ibcon#read 5, iclass 6, count 0 2006.201.19:17:07.50#ibcon#about to read 6, iclass 6, count 0 2006.201.19:17:07.50#ibcon#read 6, iclass 6, count 0 2006.201.19:17:07.50#ibcon#end of sib2, iclass 6, count 0 2006.201.19:17:07.50#ibcon#*after write, iclass 6, count 0 2006.201.19:17:07.50#ibcon#*before return 0, iclass 6, count 0 2006.201.19:17:07.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:07.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:07.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.19:17:07.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.19:17:07.50$vck44/valo=3,564.99 2006.201.19:17:07.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.19:17:07.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.19:17:07.50#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:07.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:07.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:07.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:07.50#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:17:07.50#ibcon#first serial, iclass 10, count 0 2006.201.19:17:07.50#ibcon#enter sib2, iclass 10, count 0 2006.201.19:17:07.50#ibcon#flushed, iclass 10, count 0 2006.201.19:17:07.50#ibcon#about to write, iclass 10, count 0 2006.201.19:17:07.50#ibcon#wrote, iclass 10, count 0 2006.201.19:17:07.50#ibcon#about to read 3, iclass 10, count 0 2006.201.19:17:07.52#ibcon#read 3, iclass 10, count 0 2006.201.19:17:07.52#ibcon#about to read 4, iclass 10, count 0 2006.201.19:17:07.52#ibcon#read 4, iclass 10, count 0 2006.201.19:17:07.52#ibcon#about to read 5, iclass 10, count 0 2006.201.19:17:07.52#ibcon#read 5, iclass 10, count 0 2006.201.19:17:07.52#ibcon#about to read 6, iclass 10, count 0 2006.201.19:17:07.52#ibcon#read 6, iclass 10, count 0 2006.201.19:17:07.52#ibcon#end of sib2, iclass 10, count 0 2006.201.19:17:07.52#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:17:07.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:17:07.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:17:07.52#ibcon#*before write, iclass 10, count 0 2006.201.19:17:07.52#ibcon#enter sib2, iclass 10, count 0 2006.201.19:17:07.52#ibcon#flushed, iclass 10, count 0 2006.201.19:17:07.52#ibcon#about to write, iclass 10, count 0 2006.201.19:17:07.52#ibcon#wrote, iclass 10, count 0 2006.201.19:17:07.52#ibcon#about to read 3, iclass 10, count 0 2006.201.19:17:07.56#ibcon#read 3, iclass 10, count 0 2006.201.19:17:07.56#ibcon#about to read 4, iclass 10, count 0 2006.201.19:17:07.56#ibcon#read 4, iclass 10, count 0 2006.201.19:17:07.56#ibcon#about to read 5, iclass 10, count 0 2006.201.19:17:07.56#ibcon#read 5, iclass 10, count 0 2006.201.19:17:07.56#ibcon#about to read 6, iclass 10, count 0 2006.201.19:17:07.56#ibcon#read 6, iclass 10, count 0 2006.201.19:17:07.56#ibcon#end of sib2, iclass 10, count 0 2006.201.19:17:07.56#ibcon#*after write, iclass 10, count 0 2006.201.19:17:07.56#ibcon#*before return 0, iclass 10, count 0 2006.201.19:17:07.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:07.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:07.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:17:07.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:17:07.56$vck44/va=3,8 2006.201.19:17:07.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.19:17:07.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.19:17:07.56#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:07.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:07.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:07.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:07.62#ibcon#enter wrdev, iclass 12, count 2 2006.201.19:17:07.62#ibcon#first serial, iclass 12, count 2 2006.201.19:17:07.62#ibcon#enter sib2, iclass 12, count 2 2006.201.19:17:07.62#ibcon#flushed, iclass 12, count 2 2006.201.19:17:07.62#ibcon#about to write, iclass 12, count 2 2006.201.19:17:07.62#ibcon#wrote, iclass 12, count 2 2006.201.19:17:07.62#ibcon#about to read 3, iclass 12, count 2 2006.201.19:17:07.64#ibcon#read 3, iclass 12, count 2 2006.201.19:17:07.64#ibcon#about to read 4, iclass 12, count 2 2006.201.19:17:07.64#ibcon#read 4, iclass 12, count 2 2006.201.19:17:07.64#ibcon#about to read 5, iclass 12, count 2 2006.201.19:17:07.64#ibcon#read 5, iclass 12, count 2 2006.201.19:17:07.64#ibcon#about to read 6, iclass 12, count 2 2006.201.19:17:07.64#ibcon#read 6, iclass 12, count 2 2006.201.19:17:07.64#ibcon#end of sib2, iclass 12, count 2 2006.201.19:17:07.64#ibcon#*mode == 0, iclass 12, count 2 2006.201.19:17:07.64#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.19:17:07.64#ibcon#[25=AT03-08\r\n] 2006.201.19:17:07.64#ibcon#*before write, iclass 12, count 2 2006.201.19:17:07.64#ibcon#enter sib2, iclass 12, count 2 2006.201.19:17:07.64#ibcon#flushed, iclass 12, count 2 2006.201.19:17:07.64#ibcon#about to write, iclass 12, count 2 2006.201.19:17:07.64#ibcon#wrote, iclass 12, count 2 2006.201.19:17:07.64#ibcon#about to read 3, iclass 12, count 2 2006.201.19:17:07.67#ibcon#read 3, iclass 12, count 2 2006.201.19:17:07.67#ibcon#about to read 4, iclass 12, count 2 2006.201.19:17:07.67#ibcon#read 4, iclass 12, count 2 2006.201.19:17:07.67#ibcon#about to read 5, iclass 12, count 2 2006.201.19:17:07.67#ibcon#read 5, iclass 12, count 2 2006.201.19:17:07.67#ibcon#about to read 6, iclass 12, count 2 2006.201.19:17:07.67#ibcon#read 6, iclass 12, count 2 2006.201.19:17:07.67#ibcon#end of sib2, iclass 12, count 2 2006.201.19:17:07.67#ibcon#*after write, iclass 12, count 2 2006.201.19:17:07.67#ibcon#*before return 0, iclass 12, count 2 2006.201.19:17:07.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:07.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:07.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.19:17:07.67#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:07.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:07.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:07.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:07.79#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:17:07.79#ibcon#first serial, iclass 12, count 0 2006.201.19:17:07.79#ibcon#enter sib2, iclass 12, count 0 2006.201.19:17:07.79#ibcon#flushed, iclass 12, count 0 2006.201.19:17:07.79#ibcon#about to write, iclass 12, count 0 2006.201.19:17:07.79#ibcon#wrote, iclass 12, count 0 2006.201.19:17:07.79#ibcon#about to read 3, iclass 12, count 0 2006.201.19:17:07.81#ibcon#read 3, iclass 12, count 0 2006.201.19:17:07.81#ibcon#about to read 4, iclass 12, count 0 2006.201.19:17:07.81#ibcon#read 4, iclass 12, count 0 2006.201.19:17:07.81#ibcon#about to read 5, iclass 12, count 0 2006.201.19:17:07.81#ibcon#read 5, iclass 12, count 0 2006.201.19:17:07.81#ibcon#about to read 6, iclass 12, count 0 2006.201.19:17:07.81#ibcon#read 6, iclass 12, count 0 2006.201.19:17:07.81#ibcon#end of sib2, iclass 12, count 0 2006.201.19:17:07.81#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:17:07.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:17:07.81#ibcon#[25=USB\r\n] 2006.201.19:17:07.81#ibcon#*before write, iclass 12, count 0 2006.201.19:17:07.81#ibcon#enter sib2, iclass 12, count 0 2006.201.19:17:07.81#ibcon#flushed, iclass 12, count 0 2006.201.19:17:07.81#ibcon#about to write, iclass 12, count 0 2006.201.19:17:07.81#ibcon#wrote, iclass 12, count 0 2006.201.19:17:07.81#ibcon#about to read 3, iclass 12, count 0 2006.201.19:17:07.84#ibcon#read 3, iclass 12, count 0 2006.201.19:17:07.84#ibcon#about to read 4, iclass 12, count 0 2006.201.19:17:07.84#ibcon#read 4, iclass 12, count 0 2006.201.19:17:07.84#ibcon#about to read 5, iclass 12, count 0 2006.201.19:17:07.84#ibcon#read 5, iclass 12, count 0 2006.201.19:17:07.84#ibcon#about to read 6, iclass 12, count 0 2006.201.19:17:07.84#ibcon#read 6, iclass 12, count 0 2006.201.19:17:07.84#ibcon#end of sib2, iclass 12, count 0 2006.201.19:17:07.84#ibcon#*after write, iclass 12, count 0 2006.201.19:17:07.84#ibcon#*before return 0, iclass 12, count 0 2006.201.19:17:07.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:07.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:07.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:17:07.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:17:07.84$vck44/valo=4,624.99 2006.201.19:17:07.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.19:17:07.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.19:17:07.84#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:07.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:07.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:07.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:07.84#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:17:07.84#ibcon#first serial, iclass 14, count 0 2006.201.19:17:07.84#ibcon#enter sib2, iclass 14, count 0 2006.201.19:17:07.84#ibcon#flushed, iclass 14, count 0 2006.201.19:17:07.84#ibcon#about to write, iclass 14, count 0 2006.201.19:17:07.84#ibcon#wrote, iclass 14, count 0 2006.201.19:17:07.84#ibcon#about to read 3, iclass 14, count 0 2006.201.19:17:07.86#ibcon#read 3, iclass 14, count 0 2006.201.19:17:07.86#ibcon#about to read 4, iclass 14, count 0 2006.201.19:17:07.86#ibcon#read 4, iclass 14, count 0 2006.201.19:17:07.86#ibcon#about to read 5, iclass 14, count 0 2006.201.19:17:07.86#ibcon#read 5, iclass 14, count 0 2006.201.19:17:07.86#ibcon#about to read 6, iclass 14, count 0 2006.201.19:17:07.86#ibcon#read 6, iclass 14, count 0 2006.201.19:17:07.86#ibcon#end of sib2, iclass 14, count 0 2006.201.19:17:07.86#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:17:07.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:17:07.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:17:07.86#ibcon#*before write, iclass 14, count 0 2006.201.19:17:07.86#ibcon#enter sib2, iclass 14, count 0 2006.201.19:17:07.86#ibcon#flushed, iclass 14, count 0 2006.201.19:17:07.86#ibcon#about to write, iclass 14, count 0 2006.201.19:17:07.86#ibcon#wrote, iclass 14, count 0 2006.201.19:17:07.86#ibcon#about to read 3, iclass 14, count 0 2006.201.19:17:07.91#ibcon#read 3, iclass 14, count 0 2006.201.19:17:07.91#ibcon#about to read 4, iclass 14, count 0 2006.201.19:17:07.91#ibcon#read 4, iclass 14, count 0 2006.201.19:17:07.91#ibcon#about to read 5, iclass 14, count 0 2006.201.19:17:07.91#ibcon#read 5, iclass 14, count 0 2006.201.19:17:07.91#ibcon#about to read 6, iclass 14, count 0 2006.201.19:17:07.91#ibcon#read 6, iclass 14, count 0 2006.201.19:17:07.91#ibcon#end of sib2, iclass 14, count 0 2006.201.19:17:07.91#ibcon#*after write, iclass 14, count 0 2006.201.19:17:07.91#ibcon#*before return 0, iclass 14, count 0 2006.201.19:17:07.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:07.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:07.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:17:07.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:17:07.91$vck44/va=4,7 2006.201.19:17:07.91#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.19:17:07.91#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.19:17:07.91#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:07.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:07.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:07.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:07.96#ibcon#enter wrdev, iclass 16, count 2 2006.201.19:17:07.96#ibcon#first serial, iclass 16, count 2 2006.201.19:17:07.96#ibcon#enter sib2, iclass 16, count 2 2006.201.19:17:07.96#ibcon#flushed, iclass 16, count 2 2006.201.19:17:07.96#ibcon#about to write, iclass 16, count 2 2006.201.19:17:07.96#ibcon#wrote, iclass 16, count 2 2006.201.19:17:07.96#ibcon#about to read 3, iclass 16, count 2 2006.201.19:17:07.98#ibcon#read 3, iclass 16, count 2 2006.201.19:17:07.98#ibcon#about to read 4, iclass 16, count 2 2006.201.19:17:07.98#ibcon#read 4, iclass 16, count 2 2006.201.19:17:07.98#ibcon#about to read 5, iclass 16, count 2 2006.201.19:17:07.98#ibcon#read 5, iclass 16, count 2 2006.201.19:17:07.98#ibcon#about to read 6, iclass 16, count 2 2006.201.19:17:07.98#ibcon#read 6, iclass 16, count 2 2006.201.19:17:07.98#ibcon#end of sib2, iclass 16, count 2 2006.201.19:17:07.98#ibcon#*mode == 0, iclass 16, count 2 2006.201.19:17:07.98#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.19:17:07.98#ibcon#[25=AT04-07\r\n] 2006.201.19:17:07.98#ibcon#*before write, iclass 16, count 2 2006.201.19:17:07.98#ibcon#enter sib2, iclass 16, count 2 2006.201.19:17:07.98#ibcon#flushed, iclass 16, count 2 2006.201.19:17:07.98#ibcon#about to write, iclass 16, count 2 2006.201.19:17:07.98#ibcon#wrote, iclass 16, count 2 2006.201.19:17:07.98#ibcon#about to read 3, iclass 16, count 2 2006.201.19:17:08.01#ibcon#read 3, iclass 16, count 2 2006.201.19:17:08.01#ibcon#about to read 4, iclass 16, count 2 2006.201.19:17:08.01#ibcon#read 4, iclass 16, count 2 2006.201.19:17:08.01#ibcon#about to read 5, iclass 16, count 2 2006.201.19:17:08.01#ibcon#read 5, iclass 16, count 2 2006.201.19:17:08.01#ibcon#about to read 6, iclass 16, count 2 2006.201.19:17:08.01#ibcon#read 6, iclass 16, count 2 2006.201.19:17:08.01#ibcon#end of sib2, iclass 16, count 2 2006.201.19:17:08.01#ibcon#*after write, iclass 16, count 2 2006.201.19:17:08.01#ibcon#*before return 0, iclass 16, count 2 2006.201.19:17:08.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:08.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:08.01#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.19:17:08.01#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:08.01#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:08.13#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:08.13#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:08.13#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:17:08.13#ibcon#first serial, iclass 16, count 0 2006.201.19:17:08.13#ibcon#enter sib2, iclass 16, count 0 2006.201.19:17:08.13#ibcon#flushed, iclass 16, count 0 2006.201.19:17:08.13#ibcon#about to write, iclass 16, count 0 2006.201.19:17:08.13#ibcon#wrote, iclass 16, count 0 2006.201.19:17:08.13#ibcon#about to read 3, iclass 16, count 0 2006.201.19:17:08.15#ibcon#read 3, iclass 16, count 0 2006.201.19:17:08.15#ibcon#about to read 4, iclass 16, count 0 2006.201.19:17:08.15#ibcon#read 4, iclass 16, count 0 2006.201.19:17:08.15#ibcon#about to read 5, iclass 16, count 0 2006.201.19:17:08.15#ibcon#read 5, iclass 16, count 0 2006.201.19:17:08.15#ibcon#about to read 6, iclass 16, count 0 2006.201.19:17:08.15#ibcon#read 6, iclass 16, count 0 2006.201.19:17:08.15#ibcon#end of sib2, iclass 16, count 0 2006.201.19:17:08.15#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:17:08.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:17:08.15#ibcon#[25=USB\r\n] 2006.201.19:17:08.15#ibcon#*before write, iclass 16, count 0 2006.201.19:17:08.15#ibcon#enter sib2, iclass 16, count 0 2006.201.19:17:08.15#ibcon#flushed, iclass 16, count 0 2006.201.19:17:08.15#ibcon#about to write, iclass 16, count 0 2006.201.19:17:08.15#ibcon#wrote, iclass 16, count 0 2006.201.19:17:08.15#ibcon#about to read 3, iclass 16, count 0 2006.201.19:17:08.18#ibcon#read 3, iclass 16, count 0 2006.201.19:17:08.18#ibcon#about to read 4, iclass 16, count 0 2006.201.19:17:08.18#ibcon#read 4, iclass 16, count 0 2006.201.19:17:08.18#ibcon#about to read 5, iclass 16, count 0 2006.201.19:17:08.18#ibcon#read 5, iclass 16, count 0 2006.201.19:17:08.18#ibcon#about to read 6, iclass 16, count 0 2006.201.19:17:08.18#ibcon#read 6, iclass 16, count 0 2006.201.19:17:08.18#ibcon#end of sib2, iclass 16, count 0 2006.201.19:17:08.18#ibcon#*after write, iclass 16, count 0 2006.201.19:17:08.18#ibcon#*before return 0, iclass 16, count 0 2006.201.19:17:08.18#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:08.18#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:08.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:17:08.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:17:08.18$vck44/valo=5,734.99 2006.201.19:17:08.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.19:17:08.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.19:17:08.18#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:08.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:08.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:08.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:08.18#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:17:08.18#ibcon#first serial, iclass 18, count 0 2006.201.19:17:08.18#ibcon#enter sib2, iclass 18, count 0 2006.201.19:17:08.18#ibcon#flushed, iclass 18, count 0 2006.201.19:17:08.18#ibcon#about to write, iclass 18, count 0 2006.201.19:17:08.18#ibcon#wrote, iclass 18, count 0 2006.201.19:17:08.18#ibcon#about to read 3, iclass 18, count 0 2006.201.19:17:08.20#ibcon#read 3, iclass 18, count 0 2006.201.19:17:08.20#ibcon#about to read 4, iclass 18, count 0 2006.201.19:17:08.20#ibcon#read 4, iclass 18, count 0 2006.201.19:17:08.20#ibcon#about to read 5, iclass 18, count 0 2006.201.19:17:08.20#ibcon#read 5, iclass 18, count 0 2006.201.19:17:08.20#ibcon#about to read 6, iclass 18, count 0 2006.201.19:17:08.20#ibcon#read 6, iclass 18, count 0 2006.201.19:17:08.20#ibcon#end of sib2, iclass 18, count 0 2006.201.19:17:08.20#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:17:08.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:17:08.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:17:08.20#ibcon#*before write, iclass 18, count 0 2006.201.19:17:08.20#ibcon#enter sib2, iclass 18, count 0 2006.201.19:17:08.20#ibcon#flushed, iclass 18, count 0 2006.201.19:17:08.20#ibcon#about to write, iclass 18, count 0 2006.201.19:17:08.20#ibcon#wrote, iclass 18, count 0 2006.201.19:17:08.20#ibcon#about to read 3, iclass 18, count 0 2006.201.19:17:08.24#ibcon#read 3, iclass 18, count 0 2006.201.19:17:08.24#ibcon#about to read 4, iclass 18, count 0 2006.201.19:17:08.24#ibcon#read 4, iclass 18, count 0 2006.201.19:17:08.24#ibcon#about to read 5, iclass 18, count 0 2006.201.19:17:08.24#ibcon#read 5, iclass 18, count 0 2006.201.19:17:08.24#ibcon#about to read 6, iclass 18, count 0 2006.201.19:17:08.24#ibcon#read 6, iclass 18, count 0 2006.201.19:17:08.24#ibcon#end of sib2, iclass 18, count 0 2006.201.19:17:08.24#ibcon#*after write, iclass 18, count 0 2006.201.19:17:08.24#ibcon#*before return 0, iclass 18, count 0 2006.201.19:17:08.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:08.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:08.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:17:08.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:17:08.24$vck44/va=5,4 2006.201.19:17:08.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.19:17:08.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.19:17:08.24#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:08.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:08.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:08.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:08.30#ibcon#enter wrdev, iclass 20, count 2 2006.201.19:17:08.30#ibcon#first serial, iclass 20, count 2 2006.201.19:17:08.30#ibcon#enter sib2, iclass 20, count 2 2006.201.19:17:08.30#ibcon#flushed, iclass 20, count 2 2006.201.19:17:08.30#ibcon#about to write, iclass 20, count 2 2006.201.19:17:08.30#ibcon#wrote, iclass 20, count 2 2006.201.19:17:08.30#ibcon#about to read 3, iclass 20, count 2 2006.201.19:17:08.32#ibcon#read 3, iclass 20, count 2 2006.201.19:17:08.32#ibcon#about to read 4, iclass 20, count 2 2006.201.19:17:08.32#ibcon#read 4, iclass 20, count 2 2006.201.19:17:08.32#ibcon#about to read 5, iclass 20, count 2 2006.201.19:17:08.32#ibcon#read 5, iclass 20, count 2 2006.201.19:17:08.32#ibcon#about to read 6, iclass 20, count 2 2006.201.19:17:08.32#ibcon#read 6, iclass 20, count 2 2006.201.19:17:08.32#ibcon#end of sib2, iclass 20, count 2 2006.201.19:17:08.32#ibcon#*mode == 0, iclass 20, count 2 2006.201.19:17:08.32#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.19:17:08.32#ibcon#[25=AT05-04\r\n] 2006.201.19:17:08.32#ibcon#*before write, iclass 20, count 2 2006.201.19:17:08.32#ibcon#enter sib2, iclass 20, count 2 2006.201.19:17:08.32#ibcon#flushed, iclass 20, count 2 2006.201.19:17:08.32#ibcon#about to write, iclass 20, count 2 2006.201.19:17:08.32#ibcon#wrote, iclass 20, count 2 2006.201.19:17:08.32#ibcon#about to read 3, iclass 20, count 2 2006.201.19:17:08.35#ibcon#read 3, iclass 20, count 2 2006.201.19:17:08.35#ibcon#about to read 4, iclass 20, count 2 2006.201.19:17:08.35#ibcon#read 4, iclass 20, count 2 2006.201.19:17:08.35#ibcon#about to read 5, iclass 20, count 2 2006.201.19:17:08.35#ibcon#read 5, iclass 20, count 2 2006.201.19:17:08.35#ibcon#about to read 6, iclass 20, count 2 2006.201.19:17:08.35#ibcon#read 6, iclass 20, count 2 2006.201.19:17:08.35#ibcon#end of sib2, iclass 20, count 2 2006.201.19:17:08.35#ibcon#*after write, iclass 20, count 2 2006.201.19:17:08.35#ibcon#*before return 0, iclass 20, count 2 2006.201.19:17:08.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:08.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:08.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.19:17:08.35#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:08.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:08.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:08.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:08.47#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:17:08.47#ibcon#first serial, iclass 20, count 0 2006.201.19:17:08.47#ibcon#enter sib2, iclass 20, count 0 2006.201.19:17:08.47#ibcon#flushed, iclass 20, count 0 2006.201.19:17:08.47#ibcon#about to write, iclass 20, count 0 2006.201.19:17:08.47#ibcon#wrote, iclass 20, count 0 2006.201.19:17:08.47#ibcon#about to read 3, iclass 20, count 0 2006.201.19:17:08.49#ibcon#read 3, iclass 20, count 0 2006.201.19:17:08.49#ibcon#about to read 4, iclass 20, count 0 2006.201.19:17:08.49#ibcon#read 4, iclass 20, count 0 2006.201.19:17:08.49#ibcon#about to read 5, iclass 20, count 0 2006.201.19:17:08.49#ibcon#read 5, iclass 20, count 0 2006.201.19:17:08.49#ibcon#about to read 6, iclass 20, count 0 2006.201.19:17:08.49#ibcon#read 6, iclass 20, count 0 2006.201.19:17:08.49#ibcon#end of sib2, iclass 20, count 0 2006.201.19:17:08.49#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:17:08.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:17:08.49#ibcon#[25=USB\r\n] 2006.201.19:17:08.49#ibcon#*before write, iclass 20, count 0 2006.201.19:17:08.49#ibcon#enter sib2, iclass 20, count 0 2006.201.19:17:08.49#ibcon#flushed, iclass 20, count 0 2006.201.19:17:08.49#ibcon#about to write, iclass 20, count 0 2006.201.19:17:08.49#ibcon#wrote, iclass 20, count 0 2006.201.19:17:08.49#ibcon#about to read 3, iclass 20, count 0 2006.201.19:17:08.52#ibcon#read 3, iclass 20, count 0 2006.201.19:17:08.52#ibcon#about to read 4, iclass 20, count 0 2006.201.19:17:08.52#ibcon#read 4, iclass 20, count 0 2006.201.19:17:08.52#ibcon#about to read 5, iclass 20, count 0 2006.201.19:17:08.52#ibcon#read 5, iclass 20, count 0 2006.201.19:17:08.52#ibcon#about to read 6, iclass 20, count 0 2006.201.19:17:08.52#ibcon#read 6, iclass 20, count 0 2006.201.19:17:08.52#ibcon#end of sib2, iclass 20, count 0 2006.201.19:17:08.52#ibcon#*after write, iclass 20, count 0 2006.201.19:17:08.52#ibcon#*before return 0, iclass 20, count 0 2006.201.19:17:08.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:08.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:08.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:17:08.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:17:08.52$vck44/valo=6,814.99 2006.201.19:17:08.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.19:17:08.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.19:17:08.52#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:08.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:08.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:08.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:08.52#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:17:08.52#ibcon#first serial, iclass 22, count 0 2006.201.19:17:08.52#ibcon#enter sib2, iclass 22, count 0 2006.201.19:17:08.52#ibcon#flushed, iclass 22, count 0 2006.201.19:17:08.52#ibcon#about to write, iclass 22, count 0 2006.201.19:17:08.52#ibcon#wrote, iclass 22, count 0 2006.201.19:17:08.52#ibcon#about to read 3, iclass 22, count 0 2006.201.19:17:08.54#ibcon#read 3, iclass 22, count 0 2006.201.19:17:08.54#ibcon#about to read 4, iclass 22, count 0 2006.201.19:17:08.54#ibcon#read 4, iclass 22, count 0 2006.201.19:17:08.54#ibcon#about to read 5, iclass 22, count 0 2006.201.19:17:08.54#ibcon#read 5, iclass 22, count 0 2006.201.19:17:08.54#ibcon#about to read 6, iclass 22, count 0 2006.201.19:17:08.54#ibcon#read 6, iclass 22, count 0 2006.201.19:17:08.54#ibcon#end of sib2, iclass 22, count 0 2006.201.19:17:08.54#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:17:08.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:17:08.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:17:08.54#ibcon#*before write, iclass 22, count 0 2006.201.19:17:08.54#ibcon#enter sib2, iclass 22, count 0 2006.201.19:17:08.54#ibcon#flushed, iclass 22, count 0 2006.201.19:17:08.54#ibcon#about to write, iclass 22, count 0 2006.201.19:17:08.54#ibcon#wrote, iclass 22, count 0 2006.201.19:17:08.54#ibcon#about to read 3, iclass 22, count 0 2006.201.19:17:08.59#ibcon#read 3, iclass 22, count 0 2006.201.19:17:08.59#ibcon#about to read 4, iclass 22, count 0 2006.201.19:17:08.59#ibcon#read 4, iclass 22, count 0 2006.201.19:17:08.59#ibcon#about to read 5, iclass 22, count 0 2006.201.19:17:08.59#ibcon#read 5, iclass 22, count 0 2006.201.19:17:08.59#ibcon#about to read 6, iclass 22, count 0 2006.201.19:17:08.59#ibcon#read 6, iclass 22, count 0 2006.201.19:17:08.59#ibcon#end of sib2, iclass 22, count 0 2006.201.19:17:08.59#ibcon#*after write, iclass 22, count 0 2006.201.19:17:08.59#ibcon#*before return 0, iclass 22, count 0 2006.201.19:17:08.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:08.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:08.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:17:08.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:17:08.59$vck44/va=6,5 2006.201.19:17:08.59#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.19:17:08.59#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.19:17:08.59#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:08.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:08.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:08.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:08.64#ibcon#enter wrdev, iclass 24, count 2 2006.201.19:17:08.64#ibcon#first serial, iclass 24, count 2 2006.201.19:17:08.64#ibcon#enter sib2, iclass 24, count 2 2006.201.19:17:08.64#ibcon#flushed, iclass 24, count 2 2006.201.19:17:08.64#ibcon#about to write, iclass 24, count 2 2006.201.19:17:08.64#ibcon#wrote, iclass 24, count 2 2006.201.19:17:08.64#ibcon#about to read 3, iclass 24, count 2 2006.201.19:17:08.66#ibcon#read 3, iclass 24, count 2 2006.201.19:17:08.66#ibcon#about to read 4, iclass 24, count 2 2006.201.19:17:08.66#ibcon#read 4, iclass 24, count 2 2006.201.19:17:08.66#ibcon#about to read 5, iclass 24, count 2 2006.201.19:17:08.66#ibcon#read 5, iclass 24, count 2 2006.201.19:17:08.66#ibcon#about to read 6, iclass 24, count 2 2006.201.19:17:08.66#ibcon#read 6, iclass 24, count 2 2006.201.19:17:08.66#ibcon#end of sib2, iclass 24, count 2 2006.201.19:17:08.66#ibcon#*mode == 0, iclass 24, count 2 2006.201.19:17:08.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.19:17:08.66#ibcon#[25=AT06-05\r\n] 2006.201.19:17:08.66#ibcon#*before write, iclass 24, count 2 2006.201.19:17:08.66#ibcon#enter sib2, iclass 24, count 2 2006.201.19:17:08.66#ibcon#flushed, iclass 24, count 2 2006.201.19:17:08.66#ibcon#about to write, iclass 24, count 2 2006.201.19:17:08.66#ibcon#wrote, iclass 24, count 2 2006.201.19:17:08.66#ibcon#about to read 3, iclass 24, count 2 2006.201.19:17:08.69#ibcon#read 3, iclass 24, count 2 2006.201.19:17:08.69#ibcon#about to read 4, iclass 24, count 2 2006.201.19:17:08.69#ibcon#read 4, iclass 24, count 2 2006.201.19:17:08.69#ibcon#about to read 5, iclass 24, count 2 2006.201.19:17:08.69#ibcon#read 5, iclass 24, count 2 2006.201.19:17:08.69#ibcon#about to read 6, iclass 24, count 2 2006.201.19:17:08.69#ibcon#read 6, iclass 24, count 2 2006.201.19:17:08.69#ibcon#end of sib2, iclass 24, count 2 2006.201.19:17:08.69#ibcon#*after write, iclass 24, count 2 2006.201.19:17:08.69#ibcon#*before return 0, iclass 24, count 2 2006.201.19:17:08.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:08.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:08.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.19:17:08.69#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:08.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:08.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:08.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:08.81#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:17:08.81#ibcon#first serial, iclass 24, count 0 2006.201.19:17:08.81#ibcon#enter sib2, iclass 24, count 0 2006.201.19:17:08.81#ibcon#flushed, iclass 24, count 0 2006.201.19:17:08.81#ibcon#about to write, iclass 24, count 0 2006.201.19:17:08.81#ibcon#wrote, iclass 24, count 0 2006.201.19:17:08.81#ibcon#about to read 3, iclass 24, count 0 2006.201.19:17:08.83#ibcon#read 3, iclass 24, count 0 2006.201.19:17:08.83#ibcon#about to read 4, iclass 24, count 0 2006.201.19:17:08.83#ibcon#read 4, iclass 24, count 0 2006.201.19:17:08.83#ibcon#about to read 5, iclass 24, count 0 2006.201.19:17:08.83#ibcon#read 5, iclass 24, count 0 2006.201.19:17:08.83#ibcon#about to read 6, iclass 24, count 0 2006.201.19:17:08.83#ibcon#read 6, iclass 24, count 0 2006.201.19:17:08.83#ibcon#end of sib2, iclass 24, count 0 2006.201.19:17:08.83#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:17:08.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:17:08.83#ibcon#[25=USB\r\n] 2006.201.19:17:08.83#ibcon#*before write, iclass 24, count 0 2006.201.19:17:08.83#ibcon#enter sib2, iclass 24, count 0 2006.201.19:17:08.83#ibcon#flushed, iclass 24, count 0 2006.201.19:17:08.83#ibcon#about to write, iclass 24, count 0 2006.201.19:17:08.83#ibcon#wrote, iclass 24, count 0 2006.201.19:17:08.83#ibcon#about to read 3, iclass 24, count 0 2006.201.19:17:08.86#ibcon#read 3, iclass 24, count 0 2006.201.19:17:08.86#ibcon#about to read 4, iclass 24, count 0 2006.201.19:17:08.86#ibcon#read 4, iclass 24, count 0 2006.201.19:17:08.86#ibcon#about to read 5, iclass 24, count 0 2006.201.19:17:08.86#ibcon#read 5, iclass 24, count 0 2006.201.19:17:08.86#ibcon#about to read 6, iclass 24, count 0 2006.201.19:17:08.86#ibcon#read 6, iclass 24, count 0 2006.201.19:17:08.86#ibcon#end of sib2, iclass 24, count 0 2006.201.19:17:08.86#ibcon#*after write, iclass 24, count 0 2006.201.19:17:08.86#ibcon#*before return 0, iclass 24, count 0 2006.201.19:17:08.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:08.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:08.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:17:08.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:17:08.86$vck44/valo=7,864.99 2006.201.19:17:08.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.19:17:08.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.19:17:08.86#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:08.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:08.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:08.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:08.86#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:17:08.86#ibcon#first serial, iclass 26, count 0 2006.201.19:17:08.86#ibcon#enter sib2, iclass 26, count 0 2006.201.19:17:08.86#ibcon#flushed, iclass 26, count 0 2006.201.19:17:08.86#ibcon#about to write, iclass 26, count 0 2006.201.19:17:08.86#ibcon#wrote, iclass 26, count 0 2006.201.19:17:08.86#ibcon#about to read 3, iclass 26, count 0 2006.201.19:17:08.88#ibcon#read 3, iclass 26, count 0 2006.201.19:17:08.88#ibcon#about to read 4, iclass 26, count 0 2006.201.19:17:08.88#ibcon#read 4, iclass 26, count 0 2006.201.19:17:08.88#ibcon#about to read 5, iclass 26, count 0 2006.201.19:17:08.88#ibcon#read 5, iclass 26, count 0 2006.201.19:17:08.88#ibcon#about to read 6, iclass 26, count 0 2006.201.19:17:08.88#ibcon#read 6, iclass 26, count 0 2006.201.19:17:08.88#ibcon#end of sib2, iclass 26, count 0 2006.201.19:17:08.88#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:17:08.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:17:08.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:17:08.88#ibcon#*before write, iclass 26, count 0 2006.201.19:17:08.88#ibcon#enter sib2, iclass 26, count 0 2006.201.19:17:08.88#ibcon#flushed, iclass 26, count 0 2006.201.19:17:08.88#ibcon#about to write, iclass 26, count 0 2006.201.19:17:08.88#ibcon#wrote, iclass 26, count 0 2006.201.19:17:08.88#ibcon#about to read 3, iclass 26, count 0 2006.201.19:17:08.92#ibcon#read 3, iclass 26, count 0 2006.201.19:17:08.92#ibcon#about to read 4, iclass 26, count 0 2006.201.19:17:08.92#ibcon#read 4, iclass 26, count 0 2006.201.19:17:08.92#ibcon#about to read 5, iclass 26, count 0 2006.201.19:17:08.92#ibcon#read 5, iclass 26, count 0 2006.201.19:17:08.92#ibcon#about to read 6, iclass 26, count 0 2006.201.19:17:08.92#ibcon#read 6, iclass 26, count 0 2006.201.19:17:08.92#ibcon#end of sib2, iclass 26, count 0 2006.201.19:17:08.92#ibcon#*after write, iclass 26, count 0 2006.201.19:17:08.92#ibcon#*before return 0, iclass 26, count 0 2006.201.19:17:08.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:08.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:08.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:17:08.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:17:08.92$vck44/va=7,5 2006.201.19:17:08.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.19:17:08.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.19:17:08.92#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:08.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:08.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:08.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:08.98#ibcon#enter wrdev, iclass 28, count 2 2006.201.19:17:08.98#ibcon#first serial, iclass 28, count 2 2006.201.19:17:08.98#ibcon#enter sib2, iclass 28, count 2 2006.201.19:17:08.98#ibcon#flushed, iclass 28, count 2 2006.201.19:17:08.98#ibcon#about to write, iclass 28, count 2 2006.201.19:17:08.98#ibcon#wrote, iclass 28, count 2 2006.201.19:17:08.98#ibcon#about to read 3, iclass 28, count 2 2006.201.19:17:09.00#ibcon#read 3, iclass 28, count 2 2006.201.19:17:09.00#ibcon#about to read 4, iclass 28, count 2 2006.201.19:17:09.00#ibcon#read 4, iclass 28, count 2 2006.201.19:17:09.00#ibcon#about to read 5, iclass 28, count 2 2006.201.19:17:09.00#ibcon#read 5, iclass 28, count 2 2006.201.19:17:09.00#ibcon#about to read 6, iclass 28, count 2 2006.201.19:17:09.00#ibcon#read 6, iclass 28, count 2 2006.201.19:17:09.00#ibcon#end of sib2, iclass 28, count 2 2006.201.19:17:09.00#ibcon#*mode == 0, iclass 28, count 2 2006.201.19:17:09.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.19:17:09.00#ibcon#[25=AT07-05\r\n] 2006.201.19:17:09.00#ibcon#*before write, iclass 28, count 2 2006.201.19:17:09.00#ibcon#enter sib2, iclass 28, count 2 2006.201.19:17:09.00#ibcon#flushed, iclass 28, count 2 2006.201.19:17:09.00#ibcon#about to write, iclass 28, count 2 2006.201.19:17:09.00#ibcon#wrote, iclass 28, count 2 2006.201.19:17:09.00#ibcon#about to read 3, iclass 28, count 2 2006.201.19:17:09.03#ibcon#read 3, iclass 28, count 2 2006.201.19:17:09.03#ibcon#about to read 4, iclass 28, count 2 2006.201.19:17:09.03#ibcon#read 4, iclass 28, count 2 2006.201.19:17:09.03#ibcon#about to read 5, iclass 28, count 2 2006.201.19:17:09.03#ibcon#read 5, iclass 28, count 2 2006.201.19:17:09.03#ibcon#about to read 6, iclass 28, count 2 2006.201.19:17:09.03#ibcon#read 6, iclass 28, count 2 2006.201.19:17:09.03#ibcon#end of sib2, iclass 28, count 2 2006.201.19:17:09.03#ibcon#*after write, iclass 28, count 2 2006.201.19:17:09.03#ibcon#*before return 0, iclass 28, count 2 2006.201.19:17:09.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:09.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:09.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.19:17:09.03#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:09.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:09.15#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:09.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:09.15#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:17:09.15#ibcon#first serial, iclass 28, count 0 2006.201.19:17:09.15#ibcon#enter sib2, iclass 28, count 0 2006.201.19:17:09.15#ibcon#flushed, iclass 28, count 0 2006.201.19:17:09.15#ibcon#about to write, iclass 28, count 0 2006.201.19:17:09.15#ibcon#wrote, iclass 28, count 0 2006.201.19:17:09.15#ibcon#about to read 3, iclass 28, count 0 2006.201.19:17:09.17#ibcon#read 3, iclass 28, count 0 2006.201.19:17:09.17#ibcon#about to read 4, iclass 28, count 0 2006.201.19:17:09.17#ibcon#read 4, iclass 28, count 0 2006.201.19:17:09.17#ibcon#about to read 5, iclass 28, count 0 2006.201.19:17:09.17#ibcon#read 5, iclass 28, count 0 2006.201.19:17:09.17#ibcon#about to read 6, iclass 28, count 0 2006.201.19:17:09.17#ibcon#read 6, iclass 28, count 0 2006.201.19:17:09.17#ibcon#end of sib2, iclass 28, count 0 2006.201.19:17:09.17#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:17:09.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:17:09.17#ibcon#[25=USB\r\n] 2006.201.19:17:09.17#ibcon#*before write, iclass 28, count 0 2006.201.19:17:09.17#ibcon#enter sib2, iclass 28, count 0 2006.201.19:17:09.17#ibcon#flushed, iclass 28, count 0 2006.201.19:17:09.17#ibcon#about to write, iclass 28, count 0 2006.201.19:17:09.17#ibcon#wrote, iclass 28, count 0 2006.201.19:17:09.17#ibcon#about to read 3, iclass 28, count 0 2006.201.19:17:09.20#ibcon#read 3, iclass 28, count 0 2006.201.19:17:09.20#ibcon#about to read 4, iclass 28, count 0 2006.201.19:17:09.20#ibcon#read 4, iclass 28, count 0 2006.201.19:17:09.20#ibcon#about to read 5, iclass 28, count 0 2006.201.19:17:09.20#ibcon#read 5, iclass 28, count 0 2006.201.19:17:09.20#ibcon#about to read 6, iclass 28, count 0 2006.201.19:17:09.20#ibcon#read 6, iclass 28, count 0 2006.201.19:17:09.20#ibcon#end of sib2, iclass 28, count 0 2006.201.19:17:09.20#ibcon#*after write, iclass 28, count 0 2006.201.19:17:09.20#ibcon#*before return 0, iclass 28, count 0 2006.201.19:17:09.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:09.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:09.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:17:09.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:17:09.20$vck44/valo=8,884.99 2006.201.19:17:09.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.19:17:09.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.19:17:09.20#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:09.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:09.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:09.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:09.20#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:17:09.20#ibcon#first serial, iclass 30, count 0 2006.201.19:17:09.20#ibcon#enter sib2, iclass 30, count 0 2006.201.19:17:09.20#ibcon#flushed, iclass 30, count 0 2006.201.19:17:09.20#ibcon#about to write, iclass 30, count 0 2006.201.19:17:09.20#ibcon#wrote, iclass 30, count 0 2006.201.19:17:09.20#ibcon#about to read 3, iclass 30, count 0 2006.201.19:17:09.22#ibcon#read 3, iclass 30, count 0 2006.201.19:17:09.22#ibcon#about to read 4, iclass 30, count 0 2006.201.19:17:09.22#ibcon#read 4, iclass 30, count 0 2006.201.19:17:09.22#ibcon#about to read 5, iclass 30, count 0 2006.201.19:17:09.22#ibcon#read 5, iclass 30, count 0 2006.201.19:17:09.22#ibcon#about to read 6, iclass 30, count 0 2006.201.19:17:09.22#ibcon#read 6, iclass 30, count 0 2006.201.19:17:09.22#ibcon#end of sib2, iclass 30, count 0 2006.201.19:17:09.22#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:17:09.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:17:09.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:17:09.22#ibcon#*before write, iclass 30, count 0 2006.201.19:17:09.22#ibcon#enter sib2, iclass 30, count 0 2006.201.19:17:09.22#ibcon#flushed, iclass 30, count 0 2006.201.19:17:09.22#ibcon#about to write, iclass 30, count 0 2006.201.19:17:09.22#ibcon#wrote, iclass 30, count 0 2006.201.19:17:09.22#ibcon#about to read 3, iclass 30, count 0 2006.201.19:17:09.26#ibcon#read 3, iclass 30, count 0 2006.201.19:17:09.26#ibcon#about to read 4, iclass 30, count 0 2006.201.19:17:09.26#ibcon#read 4, iclass 30, count 0 2006.201.19:17:09.26#ibcon#about to read 5, iclass 30, count 0 2006.201.19:17:09.26#ibcon#read 5, iclass 30, count 0 2006.201.19:17:09.26#ibcon#about to read 6, iclass 30, count 0 2006.201.19:17:09.26#ibcon#read 6, iclass 30, count 0 2006.201.19:17:09.26#ibcon#end of sib2, iclass 30, count 0 2006.201.19:17:09.26#ibcon#*after write, iclass 30, count 0 2006.201.19:17:09.26#ibcon#*before return 0, iclass 30, count 0 2006.201.19:17:09.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:09.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:09.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:17:09.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:17:09.26$vck44/va=8,4 2006.201.19:17:09.26#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.19:17:09.26#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.19:17:09.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:09.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:17:09.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:17:09.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:17:09.32#ibcon#enter wrdev, iclass 32, count 2 2006.201.19:17:09.32#ibcon#first serial, iclass 32, count 2 2006.201.19:17:09.32#ibcon#enter sib2, iclass 32, count 2 2006.201.19:17:09.32#ibcon#flushed, iclass 32, count 2 2006.201.19:17:09.32#ibcon#about to write, iclass 32, count 2 2006.201.19:17:09.32#ibcon#wrote, iclass 32, count 2 2006.201.19:17:09.32#ibcon#about to read 3, iclass 32, count 2 2006.201.19:17:09.34#ibcon#read 3, iclass 32, count 2 2006.201.19:17:09.34#ibcon#about to read 4, iclass 32, count 2 2006.201.19:17:09.34#ibcon#read 4, iclass 32, count 2 2006.201.19:17:09.34#ibcon#about to read 5, iclass 32, count 2 2006.201.19:17:09.34#ibcon#read 5, iclass 32, count 2 2006.201.19:17:09.34#ibcon#about to read 6, iclass 32, count 2 2006.201.19:17:09.34#ibcon#read 6, iclass 32, count 2 2006.201.19:17:09.34#ibcon#end of sib2, iclass 32, count 2 2006.201.19:17:09.34#ibcon#*mode == 0, iclass 32, count 2 2006.201.19:17:09.34#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.19:17:09.34#ibcon#[25=AT08-04\r\n] 2006.201.19:17:09.34#ibcon#*before write, iclass 32, count 2 2006.201.19:17:09.34#ibcon#enter sib2, iclass 32, count 2 2006.201.19:17:09.34#ibcon#flushed, iclass 32, count 2 2006.201.19:17:09.34#ibcon#about to write, iclass 32, count 2 2006.201.19:17:09.34#ibcon#wrote, iclass 32, count 2 2006.201.19:17:09.34#ibcon#about to read 3, iclass 32, count 2 2006.201.19:17:09.37#ibcon#read 3, iclass 32, count 2 2006.201.19:17:09.37#ibcon#about to read 4, iclass 32, count 2 2006.201.19:17:09.37#ibcon#read 4, iclass 32, count 2 2006.201.19:17:09.37#ibcon#about to read 5, iclass 32, count 2 2006.201.19:17:09.37#ibcon#read 5, iclass 32, count 2 2006.201.19:17:09.37#ibcon#about to read 6, iclass 32, count 2 2006.201.19:17:09.37#ibcon#read 6, iclass 32, count 2 2006.201.19:17:09.37#ibcon#end of sib2, iclass 32, count 2 2006.201.19:17:09.37#ibcon#*after write, iclass 32, count 2 2006.201.19:17:09.37#ibcon#*before return 0, iclass 32, count 2 2006.201.19:17:09.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:17:09.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:17:09.37#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.19:17:09.37#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:09.37#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:17:09.49#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:17:09.49#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:17:09.49#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:17:09.49#ibcon#first serial, iclass 32, count 0 2006.201.19:17:09.49#ibcon#enter sib2, iclass 32, count 0 2006.201.19:17:09.49#ibcon#flushed, iclass 32, count 0 2006.201.19:17:09.49#ibcon#about to write, iclass 32, count 0 2006.201.19:17:09.49#ibcon#wrote, iclass 32, count 0 2006.201.19:17:09.49#ibcon#about to read 3, iclass 32, count 0 2006.201.19:17:09.51#ibcon#read 3, iclass 32, count 0 2006.201.19:17:09.51#ibcon#about to read 4, iclass 32, count 0 2006.201.19:17:09.51#ibcon#read 4, iclass 32, count 0 2006.201.19:17:09.51#ibcon#about to read 5, iclass 32, count 0 2006.201.19:17:09.51#ibcon#read 5, iclass 32, count 0 2006.201.19:17:09.51#ibcon#about to read 6, iclass 32, count 0 2006.201.19:17:09.51#ibcon#read 6, iclass 32, count 0 2006.201.19:17:09.51#ibcon#end of sib2, iclass 32, count 0 2006.201.19:17:09.51#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:17:09.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:17:09.51#ibcon#[25=USB\r\n] 2006.201.19:17:09.51#ibcon#*before write, iclass 32, count 0 2006.201.19:17:09.51#ibcon#enter sib2, iclass 32, count 0 2006.201.19:17:09.51#ibcon#flushed, iclass 32, count 0 2006.201.19:17:09.51#ibcon#about to write, iclass 32, count 0 2006.201.19:17:09.51#ibcon#wrote, iclass 32, count 0 2006.201.19:17:09.51#ibcon#about to read 3, iclass 32, count 0 2006.201.19:17:09.54#ibcon#read 3, iclass 32, count 0 2006.201.19:17:09.54#ibcon#about to read 4, iclass 32, count 0 2006.201.19:17:09.54#ibcon#read 4, iclass 32, count 0 2006.201.19:17:09.54#ibcon#about to read 5, iclass 32, count 0 2006.201.19:17:09.54#ibcon#read 5, iclass 32, count 0 2006.201.19:17:09.54#ibcon#about to read 6, iclass 32, count 0 2006.201.19:17:09.54#ibcon#read 6, iclass 32, count 0 2006.201.19:17:09.54#ibcon#end of sib2, iclass 32, count 0 2006.201.19:17:09.54#ibcon#*after write, iclass 32, count 0 2006.201.19:17:09.54#ibcon#*before return 0, iclass 32, count 0 2006.201.19:17:09.54#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:17:09.54#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:17:09.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:17:09.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:17:09.54$vck44/vblo=1,629.99 2006.201.19:17:09.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.19:17:09.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.19:17:09.54#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:09.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:17:09.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:17:09.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:17:09.54#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:17:09.54#ibcon#first serial, iclass 34, count 0 2006.201.19:17:09.54#ibcon#enter sib2, iclass 34, count 0 2006.201.19:17:09.54#ibcon#flushed, iclass 34, count 0 2006.201.19:17:09.54#ibcon#about to write, iclass 34, count 0 2006.201.19:17:09.54#ibcon#wrote, iclass 34, count 0 2006.201.19:17:09.54#ibcon#about to read 3, iclass 34, count 0 2006.201.19:17:09.56#ibcon#read 3, iclass 34, count 0 2006.201.19:17:09.56#ibcon#about to read 4, iclass 34, count 0 2006.201.19:17:09.56#ibcon#read 4, iclass 34, count 0 2006.201.19:17:09.56#ibcon#about to read 5, iclass 34, count 0 2006.201.19:17:09.56#ibcon#read 5, iclass 34, count 0 2006.201.19:17:09.56#ibcon#about to read 6, iclass 34, count 0 2006.201.19:17:09.56#ibcon#read 6, iclass 34, count 0 2006.201.19:17:09.56#ibcon#end of sib2, iclass 34, count 0 2006.201.19:17:09.56#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:17:09.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:17:09.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:17:09.56#ibcon#*before write, iclass 34, count 0 2006.201.19:17:09.56#ibcon#enter sib2, iclass 34, count 0 2006.201.19:17:09.56#ibcon#flushed, iclass 34, count 0 2006.201.19:17:09.56#ibcon#about to write, iclass 34, count 0 2006.201.19:17:09.56#ibcon#wrote, iclass 34, count 0 2006.201.19:17:09.56#ibcon#about to read 3, iclass 34, count 0 2006.201.19:17:09.60#ibcon#read 3, iclass 34, count 0 2006.201.19:17:09.60#ibcon#about to read 4, iclass 34, count 0 2006.201.19:17:09.60#ibcon#read 4, iclass 34, count 0 2006.201.19:17:09.60#ibcon#about to read 5, iclass 34, count 0 2006.201.19:17:09.60#ibcon#read 5, iclass 34, count 0 2006.201.19:17:09.60#ibcon#about to read 6, iclass 34, count 0 2006.201.19:17:09.60#ibcon#read 6, iclass 34, count 0 2006.201.19:17:09.60#ibcon#end of sib2, iclass 34, count 0 2006.201.19:17:09.60#ibcon#*after write, iclass 34, count 0 2006.201.19:17:09.60#ibcon#*before return 0, iclass 34, count 0 2006.201.19:17:09.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:17:09.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:17:09.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:17:09.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:17:09.60$vck44/vb=1,4 2006.201.19:17:09.60#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.19:17:09.60#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.19:17:09.60#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:09.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:17:09.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:17:09.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:17:09.60#ibcon#enter wrdev, iclass 36, count 2 2006.201.19:17:09.60#ibcon#first serial, iclass 36, count 2 2006.201.19:17:09.60#ibcon#enter sib2, iclass 36, count 2 2006.201.19:17:09.60#ibcon#flushed, iclass 36, count 2 2006.201.19:17:09.60#ibcon#about to write, iclass 36, count 2 2006.201.19:17:09.60#ibcon#wrote, iclass 36, count 2 2006.201.19:17:09.60#ibcon#about to read 3, iclass 36, count 2 2006.201.19:17:09.62#ibcon#read 3, iclass 36, count 2 2006.201.19:17:09.62#ibcon#about to read 4, iclass 36, count 2 2006.201.19:17:09.62#ibcon#read 4, iclass 36, count 2 2006.201.19:17:09.62#ibcon#about to read 5, iclass 36, count 2 2006.201.19:17:09.62#ibcon#read 5, iclass 36, count 2 2006.201.19:17:09.62#ibcon#about to read 6, iclass 36, count 2 2006.201.19:17:09.62#ibcon#read 6, iclass 36, count 2 2006.201.19:17:09.62#ibcon#end of sib2, iclass 36, count 2 2006.201.19:17:09.62#ibcon#*mode == 0, iclass 36, count 2 2006.201.19:17:09.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.19:17:09.62#ibcon#[27=AT01-04\r\n] 2006.201.19:17:09.62#ibcon#*before write, iclass 36, count 2 2006.201.19:17:09.62#ibcon#enter sib2, iclass 36, count 2 2006.201.19:17:09.62#ibcon#flushed, iclass 36, count 2 2006.201.19:17:09.62#ibcon#about to write, iclass 36, count 2 2006.201.19:17:09.62#ibcon#wrote, iclass 36, count 2 2006.201.19:17:09.62#ibcon#about to read 3, iclass 36, count 2 2006.201.19:17:09.65#ibcon#read 3, iclass 36, count 2 2006.201.19:17:09.65#ibcon#about to read 4, iclass 36, count 2 2006.201.19:17:09.65#ibcon#read 4, iclass 36, count 2 2006.201.19:17:09.65#ibcon#about to read 5, iclass 36, count 2 2006.201.19:17:09.65#ibcon#read 5, iclass 36, count 2 2006.201.19:17:09.65#ibcon#about to read 6, iclass 36, count 2 2006.201.19:17:09.65#ibcon#read 6, iclass 36, count 2 2006.201.19:17:09.65#ibcon#end of sib2, iclass 36, count 2 2006.201.19:17:09.65#ibcon#*after write, iclass 36, count 2 2006.201.19:17:09.65#ibcon#*before return 0, iclass 36, count 2 2006.201.19:17:09.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:17:09.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:17:09.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.19:17:09.65#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:09.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:17:09.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:17:09.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:17:09.77#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:17:09.77#ibcon#first serial, iclass 36, count 0 2006.201.19:17:09.77#ibcon#enter sib2, iclass 36, count 0 2006.201.19:17:09.77#ibcon#flushed, iclass 36, count 0 2006.201.19:17:09.77#ibcon#about to write, iclass 36, count 0 2006.201.19:17:09.77#ibcon#wrote, iclass 36, count 0 2006.201.19:17:09.77#ibcon#about to read 3, iclass 36, count 0 2006.201.19:17:09.79#ibcon#read 3, iclass 36, count 0 2006.201.19:17:09.79#ibcon#about to read 4, iclass 36, count 0 2006.201.19:17:09.79#ibcon#read 4, iclass 36, count 0 2006.201.19:17:09.79#ibcon#about to read 5, iclass 36, count 0 2006.201.19:17:09.79#ibcon#read 5, iclass 36, count 0 2006.201.19:17:09.79#ibcon#about to read 6, iclass 36, count 0 2006.201.19:17:09.79#ibcon#read 6, iclass 36, count 0 2006.201.19:17:09.79#ibcon#end of sib2, iclass 36, count 0 2006.201.19:17:09.79#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:17:09.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:17:09.79#ibcon#[27=USB\r\n] 2006.201.19:17:09.79#ibcon#*before write, iclass 36, count 0 2006.201.19:17:09.79#ibcon#enter sib2, iclass 36, count 0 2006.201.19:17:09.79#ibcon#flushed, iclass 36, count 0 2006.201.19:17:09.79#ibcon#about to write, iclass 36, count 0 2006.201.19:17:09.79#ibcon#wrote, iclass 36, count 0 2006.201.19:17:09.79#ibcon#about to read 3, iclass 36, count 0 2006.201.19:17:09.82#ibcon#read 3, iclass 36, count 0 2006.201.19:17:09.82#ibcon#about to read 4, iclass 36, count 0 2006.201.19:17:09.82#ibcon#read 4, iclass 36, count 0 2006.201.19:17:09.82#ibcon#about to read 5, iclass 36, count 0 2006.201.19:17:09.82#ibcon#read 5, iclass 36, count 0 2006.201.19:17:09.82#ibcon#about to read 6, iclass 36, count 0 2006.201.19:17:09.82#ibcon#read 6, iclass 36, count 0 2006.201.19:17:09.82#ibcon#end of sib2, iclass 36, count 0 2006.201.19:17:09.82#ibcon#*after write, iclass 36, count 0 2006.201.19:17:09.82#ibcon#*before return 0, iclass 36, count 0 2006.201.19:17:09.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:17:09.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:17:09.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:17:09.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:17:09.82$vck44/vblo=2,634.99 2006.201.19:17:09.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.19:17:09.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.19:17:09.82#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:09.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:09.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:09.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:09.82#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:17:09.82#ibcon#first serial, iclass 38, count 0 2006.201.19:17:09.82#ibcon#enter sib2, iclass 38, count 0 2006.201.19:17:09.82#ibcon#flushed, iclass 38, count 0 2006.201.19:17:09.82#ibcon#about to write, iclass 38, count 0 2006.201.19:17:09.82#ibcon#wrote, iclass 38, count 0 2006.201.19:17:09.82#ibcon#about to read 3, iclass 38, count 0 2006.201.19:17:09.84#ibcon#read 3, iclass 38, count 0 2006.201.19:17:09.84#ibcon#about to read 4, iclass 38, count 0 2006.201.19:17:09.84#ibcon#read 4, iclass 38, count 0 2006.201.19:17:09.84#ibcon#about to read 5, iclass 38, count 0 2006.201.19:17:09.84#ibcon#read 5, iclass 38, count 0 2006.201.19:17:09.84#ibcon#about to read 6, iclass 38, count 0 2006.201.19:17:09.84#ibcon#read 6, iclass 38, count 0 2006.201.19:17:09.84#ibcon#end of sib2, iclass 38, count 0 2006.201.19:17:09.84#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:17:09.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:17:09.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:17:09.84#ibcon#*before write, iclass 38, count 0 2006.201.19:17:09.84#ibcon#enter sib2, iclass 38, count 0 2006.201.19:17:09.84#ibcon#flushed, iclass 38, count 0 2006.201.19:17:09.84#ibcon#about to write, iclass 38, count 0 2006.201.19:17:09.84#ibcon#wrote, iclass 38, count 0 2006.201.19:17:09.84#ibcon#about to read 3, iclass 38, count 0 2006.201.19:17:09.88#ibcon#read 3, iclass 38, count 0 2006.201.19:17:09.88#ibcon#about to read 4, iclass 38, count 0 2006.201.19:17:09.88#ibcon#read 4, iclass 38, count 0 2006.201.19:17:09.88#ibcon#about to read 5, iclass 38, count 0 2006.201.19:17:09.88#ibcon#read 5, iclass 38, count 0 2006.201.19:17:09.88#ibcon#about to read 6, iclass 38, count 0 2006.201.19:17:09.88#ibcon#read 6, iclass 38, count 0 2006.201.19:17:09.88#ibcon#end of sib2, iclass 38, count 0 2006.201.19:17:09.88#ibcon#*after write, iclass 38, count 0 2006.201.19:17:09.88#ibcon#*before return 0, iclass 38, count 0 2006.201.19:17:09.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:09.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:17:09.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:17:09.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:17:09.88$vck44/vb=2,5 2006.201.19:17:09.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.19:17:09.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.19:17:09.88#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:09.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:09.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:09.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:09.94#ibcon#enter wrdev, iclass 40, count 2 2006.201.19:17:09.94#ibcon#first serial, iclass 40, count 2 2006.201.19:17:09.94#ibcon#enter sib2, iclass 40, count 2 2006.201.19:17:09.94#ibcon#flushed, iclass 40, count 2 2006.201.19:17:09.94#ibcon#about to write, iclass 40, count 2 2006.201.19:17:09.94#ibcon#wrote, iclass 40, count 2 2006.201.19:17:09.94#ibcon#about to read 3, iclass 40, count 2 2006.201.19:17:09.96#ibcon#read 3, iclass 40, count 2 2006.201.19:17:09.96#ibcon#about to read 4, iclass 40, count 2 2006.201.19:17:09.96#ibcon#read 4, iclass 40, count 2 2006.201.19:17:09.96#ibcon#about to read 5, iclass 40, count 2 2006.201.19:17:09.96#ibcon#read 5, iclass 40, count 2 2006.201.19:17:09.96#ibcon#about to read 6, iclass 40, count 2 2006.201.19:17:09.96#ibcon#read 6, iclass 40, count 2 2006.201.19:17:09.96#ibcon#end of sib2, iclass 40, count 2 2006.201.19:17:09.96#ibcon#*mode == 0, iclass 40, count 2 2006.201.19:17:09.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.19:17:09.96#ibcon#[27=AT02-05\r\n] 2006.201.19:17:09.96#ibcon#*before write, iclass 40, count 2 2006.201.19:17:09.96#ibcon#enter sib2, iclass 40, count 2 2006.201.19:17:09.96#ibcon#flushed, iclass 40, count 2 2006.201.19:17:09.96#ibcon#about to write, iclass 40, count 2 2006.201.19:17:09.96#ibcon#wrote, iclass 40, count 2 2006.201.19:17:09.96#ibcon#about to read 3, iclass 40, count 2 2006.201.19:17:09.99#ibcon#read 3, iclass 40, count 2 2006.201.19:17:09.99#ibcon#about to read 4, iclass 40, count 2 2006.201.19:17:09.99#ibcon#read 4, iclass 40, count 2 2006.201.19:17:09.99#ibcon#about to read 5, iclass 40, count 2 2006.201.19:17:09.99#ibcon#read 5, iclass 40, count 2 2006.201.19:17:09.99#ibcon#about to read 6, iclass 40, count 2 2006.201.19:17:09.99#ibcon#read 6, iclass 40, count 2 2006.201.19:17:09.99#ibcon#end of sib2, iclass 40, count 2 2006.201.19:17:09.99#ibcon#*after write, iclass 40, count 2 2006.201.19:17:09.99#ibcon#*before return 0, iclass 40, count 2 2006.201.19:17:09.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:09.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:17:09.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.19:17:09.99#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:09.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:10.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:10.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:10.11#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:17:10.11#ibcon#first serial, iclass 40, count 0 2006.201.19:17:10.11#ibcon#enter sib2, iclass 40, count 0 2006.201.19:17:10.11#ibcon#flushed, iclass 40, count 0 2006.201.19:17:10.11#ibcon#about to write, iclass 40, count 0 2006.201.19:17:10.11#ibcon#wrote, iclass 40, count 0 2006.201.19:17:10.11#ibcon#about to read 3, iclass 40, count 0 2006.201.19:17:10.13#ibcon#read 3, iclass 40, count 0 2006.201.19:17:10.13#ibcon#about to read 4, iclass 40, count 0 2006.201.19:17:10.13#ibcon#read 4, iclass 40, count 0 2006.201.19:17:10.13#ibcon#about to read 5, iclass 40, count 0 2006.201.19:17:10.13#ibcon#read 5, iclass 40, count 0 2006.201.19:17:10.13#ibcon#about to read 6, iclass 40, count 0 2006.201.19:17:10.13#ibcon#read 6, iclass 40, count 0 2006.201.19:17:10.13#ibcon#end of sib2, iclass 40, count 0 2006.201.19:17:10.13#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:17:10.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:17:10.13#ibcon#[27=USB\r\n] 2006.201.19:17:10.13#ibcon#*before write, iclass 40, count 0 2006.201.19:17:10.13#ibcon#enter sib2, iclass 40, count 0 2006.201.19:17:10.13#ibcon#flushed, iclass 40, count 0 2006.201.19:17:10.13#ibcon#about to write, iclass 40, count 0 2006.201.19:17:10.13#ibcon#wrote, iclass 40, count 0 2006.201.19:17:10.13#ibcon#about to read 3, iclass 40, count 0 2006.201.19:17:10.16#ibcon#read 3, iclass 40, count 0 2006.201.19:17:10.16#ibcon#about to read 4, iclass 40, count 0 2006.201.19:17:10.16#ibcon#read 4, iclass 40, count 0 2006.201.19:17:10.16#ibcon#about to read 5, iclass 40, count 0 2006.201.19:17:10.16#ibcon#read 5, iclass 40, count 0 2006.201.19:17:10.16#ibcon#about to read 6, iclass 40, count 0 2006.201.19:17:10.16#ibcon#read 6, iclass 40, count 0 2006.201.19:17:10.16#ibcon#end of sib2, iclass 40, count 0 2006.201.19:17:10.16#ibcon#*after write, iclass 40, count 0 2006.201.19:17:10.16#ibcon#*before return 0, iclass 40, count 0 2006.201.19:17:10.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:10.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:17:10.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:17:10.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:17:10.16$vck44/vblo=3,649.99 2006.201.19:17:10.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.19:17:10.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.19:17:10.16#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:10.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:10.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:10.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:10.16#ibcon#enter wrdev, iclass 4, count 0 2006.201.19:17:10.16#ibcon#first serial, iclass 4, count 0 2006.201.19:17:10.16#ibcon#enter sib2, iclass 4, count 0 2006.201.19:17:10.16#ibcon#flushed, iclass 4, count 0 2006.201.19:17:10.16#ibcon#about to write, iclass 4, count 0 2006.201.19:17:10.16#ibcon#wrote, iclass 4, count 0 2006.201.19:17:10.16#ibcon#about to read 3, iclass 4, count 0 2006.201.19:17:10.18#ibcon#read 3, iclass 4, count 0 2006.201.19:17:10.18#ibcon#about to read 4, iclass 4, count 0 2006.201.19:17:10.18#ibcon#read 4, iclass 4, count 0 2006.201.19:17:10.18#ibcon#about to read 5, iclass 4, count 0 2006.201.19:17:10.18#ibcon#read 5, iclass 4, count 0 2006.201.19:17:10.18#ibcon#about to read 6, iclass 4, count 0 2006.201.19:17:10.18#ibcon#read 6, iclass 4, count 0 2006.201.19:17:10.18#ibcon#end of sib2, iclass 4, count 0 2006.201.19:17:10.18#ibcon#*mode == 0, iclass 4, count 0 2006.201.19:17:10.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.19:17:10.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:17:10.18#ibcon#*before write, iclass 4, count 0 2006.201.19:17:10.18#ibcon#enter sib2, iclass 4, count 0 2006.201.19:17:10.18#ibcon#flushed, iclass 4, count 0 2006.201.19:17:10.18#ibcon#about to write, iclass 4, count 0 2006.201.19:17:10.18#ibcon#wrote, iclass 4, count 0 2006.201.19:17:10.18#ibcon#about to read 3, iclass 4, count 0 2006.201.19:17:10.22#ibcon#read 3, iclass 4, count 0 2006.201.19:17:10.22#ibcon#about to read 4, iclass 4, count 0 2006.201.19:17:10.22#ibcon#read 4, iclass 4, count 0 2006.201.19:17:10.22#ibcon#about to read 5, iclass 4, count 0 2006.201.19:17:10.22#ibcon#read 5, iclass 4, count 0 2006.201.19:17:10.22#ibcon#about to read 6, iclass 4, count 0 2006.201.19:17:10.22#ibcon#read 6, iclass 4, count 0 2006.201.19:17:10.22#ibcon#end of sib2, iclass 4, count 0 2006.201.19:17:10.22#ibcon#*after write, iclass 4, count 0 2006.201.19:17:10.22#ibcon#*before return 0, iclass 4, count 0 2006.201.19:17:10.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:10.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:17:10.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.19:17:10.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.19:17:10.22$vck44/vb=3,4 2006.201.19:17:10.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.19:17:10.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.19:17:10.22#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:10.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:10.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:10.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:10.28#ibcon#enter wrdev, iclass 6, count 2 2006.201.19:17:10.28#ibcon#first serial, iclass 6, count 2 2006.201.19:17:10.28#ibcon#enter sib2, iclass 6, count 2 2006.201.19:17:10.28#ibcon#flushed, iclass 6, count 2 2006.201.19:17:10.28#ibcon#about to write, iclass 6, count 2 2006.201.19:17:10.28#ibcon#wrote, iclass 6, count 2 2006.201.19:17:10.28#ibcon#about to read 3, iclass 6, count 2 2006.201.19:17:10.30#ibcon#read 3, iclass 6, count 2 2006.201.19:17:10.30#ibcon#about to read 4, iclass 6, count 2 2006.201.19:17:10.30#ibcon#read 4, iclass 6, count 2 2006.201.19:17:10.30#ibcon#about to read 5, iclass 6, count 2 2006.201.19:17:10.30#ibcon#read 5, iclass 6, count 2 2006.201.19:17:10.30#ibcon#about to read 6, iclass 6, count 2 2006.201.19:17:10.30#ibcon#read 6, iclass 6, count 2 2006.201.19:17:10.30#ibcon#end of sib2, iclass 6, count 2 2006.201.19:17:10.30#ibcon#*mode == 0, iclass 6, count 2 2006.201.19:17:10.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.19:17:10.30#ibcon#[27=AT03-04\r\n] 2006.201.19:17:10.30#ibcon#*before write, iclass 6, count 2 2006.201.19:17:10.30#ibcon#enter sib2, iclass 6, count 2 2006.201.19:17:10.30#ibcon#flushed, iclass 6, count 2 2006.201.19:17:10.30#ibcon#about to write, iclass 6, count 2 2006.201.19:17:10.30#ibcon#wrote, iclass 6, count 2 2006.201.19:17:10.30#ibcon#about to read 3, iclass 6, count 2 2006.201.19:17:10.33#ibcon#read 3, iclass 6, count 2 2006.201.19:17:10.33#ibcon#about to read 4, iclass 6, count 2 2006.201.19:17:10.33#ibcon#read 4, iclass 6, count 2 2006.201.19:17:10.33#ibcon#about to read 5, iclass 6, count 2 2006.201.19:17:10.33#ibcon#read 5, iclass 6, count 2 2006.201.19:17:10.33#ibcon#about to read 6, iclass 6, count 2 2006.201.19:17:10.33#ibcon#read 6, iclass 6, count 2 2006.201.19:17:10.33#ibcon#end of sib2, iclass 6, count 2 2006.201.19:17:10.33#ibcon#*after write, iclass 6, count 2 2006.201.19:17:10.33#ibcon#*before return 0, iclass 6, count 2 2006.201.19:17:10.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:10.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:17:10.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.19:17:10.33#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:10.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:10.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:10.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:10.45#ibcon#enter wrdev, iclass 6, count 0 2006.201.19:17:10.45#ibcon#first serial, iclass 6, count 0 2006.201.19:17:10.45#ibcon#enter sib2, iclass 6, count 0 2006.201.19:17:10.45#ibcon#flushed, iclass 6, count 0 2006.201.19:17:10.45#ibcon#about to write, iclass 6, count 0 2006.201.19:17:10.45#ibcon#wrote, iclass 6, count 0 2006.201.19:17:10.45#ibcon#about to read 3, iclass 6, count 0 2006.201.19:17:10.47#ibcon#read 3, iclass 6, count 0 2006.201.19:17:10.47#ibcon#about to read 4, iclass 6, count 0 2006.201.19:17:10.47#ibcon#read 4, iclass 6, count 0 2006.201.19:17:10.47#ibcon#about to read 5, iclass 6, count 0 2006.201.19:17:10.47#ibcon#read 5, iclass 6, count 0 2006.201.19:17:10.47#ibcon#about to read 6, iclass 6, count 0 2006.201.19:17:10.47#ibcon#read 6, iclass 6, count 0 2006.201.19:17:10.47#ibcon#end of sib2, iclass 6, count 0 2006.201.19:17:10.47#ibcon#*mode == 0, iclass 6, count 0 2006.201.19:17:10.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.19:17:10.47#ibcon#[27=USB\r\n] 2006.201.19:17:10.47#ibcon#*before write, iclass 6, count 0 2006.201.19:17:10.47#ibcon#enter sib2, iclass 6, count 0 2006.201.19:17:10.47#ibcon#flushed, iclass 6, count 0 2006.201.19:17:10.47#ibcon#about to write, iclass 6, count 0 2006.201.19:17:10.47#ibcon#wrote, iclass 6, count 0 2006.201.19:17:10.47#ibcon#about to read 3, iclass 6, count 0 2006.201.19:17:10.50#ibcon#read 3, iclass 6, count 0 2006.201.19:17:10.50#ibcon#about to read 4, iclass 6, count 0 2006.201.19:17:10.50#ibcon#read 4, iclass 6, count 0 2006.201.19:17:10.50#ibcon#about to read 5, iclass 6, count 0 2006.201.19:17:10.50#ibcon#read 5, iclass 6, count 0 2006.201.19:17:10.50#ibcon#about to read 6, iclass 6, count 0 2006.201.19:17:10.50#ibcon#read 6, iclass 6, count 0 2006.201.19:17:10.50#ibcon#end of sib2, iclass 6, count 0 2006.201.19:17:10.50#ibcon#*after write, iclass 6, count 0 2006.201.19:17:10.50#ibcon#*before return 0, iclass 6, count 0 2006.201.19:17:10.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:10.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:17:10.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.19:17:10.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.19:17:10.50$vck44/vblo=4,679.99 2006.201.19:17:10.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.19:17:10.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.19:17:10.50#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:10.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:10.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:10.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:10.50#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:17:10.50#ibcon#first serial, iclass 10, count 0 2006.201.19:17:10.50#ibcon#enter sib2, iclass 10, count 0 2006.201.19:17:10.50#ibcon#flushed, iclass 10, count 0 2006.201.19:17:10.50#ibcon#about to write, iclass 10, count 0 2006.201.19:17:10.50#ibcon#wrote, iclass 10, count 0 2006.201.19:17:10.50#ibcon#about to read 3, iclass 10, count 0 2006.201.19:17:10.52#ibcon#read 3, iclass 10, count 0 2006.201.19:17:10.52#ibcon#about to read 4, iclass 10, count 0 2006.201.19:17:10.52#ibcon#read 4, iclass 10, count 0 2006.201.19:17:10.52#ibcon#about to read 5, iclass 10, count 0 2006.201.19:17:10.52#ibcon#read 5, iclass 10, count 0 2006.201.19:17:10.52#ibcon#about to read 6, iclass 10, count 0 2006.201.19:17:10.52#ibcon#read 6, iclass 10, count 0 2006.201.19:17:10.52#ibcon#end of sib2, iclass 10, count 0 2006.201.19:17:10.52#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:17:10.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:17:10.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:17:10.52#ibcon#*before write, iclass 10, count 0 2006.201.19:17:10.52#ibcon#enter sib2, iclass 10, count 0 2006.201.19:17:10.52#ibcon#flushed, iclass 10, count 0 2006.201.19:17:10.52#ibcon#about to write, iclass 10, count 0 2006.201.19:17:10.52#ibcon#wrote, iclass 10, count 0 2006.201.19:17:10.52#ibcon#about to read 3, iclass 10, count 0 2006.201.19:17:10.56#ibcon#read 3, iclass 10, count 0 2006.201.19:17:10.56#ibcon#about to read 4, iclass 10, count 0 2006.201.19:17:10.56#ibcon#read 4, iclass 10, count 0 2006.201.19:17:10.56#ibcon#about to read 5, iclass 10, count 0 2006.201.19:17:10.56#ibcon#read 5, iclass 10, count 0 2006.201.19:17:10.56#ibcon#about to read 6, iclass 10, count 0 2006.201.19:17:10.56#ibcon#read 6, iclass 10, count 0 2006.201.19:17:10.56#ibcon#end of sib2, iclass 10, count 0 2006.201.19:17:10.56#ibcon#*after write, iclass 10, count 0 2006.201.19:17:10.56#ibcon#*before return 0, iclass 10, count 0 2006.201.19:17:10.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:10.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:17:10.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:17:10.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:17:10.56$vck44/vb=4,5 2006.201.19:17:10.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.19:17:10.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.19:17:10.56#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:10.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:10.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:10.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:10.62#ibcon#enter wrdev, iclass 12, count 2 2006.201.19:17:10.62#ibcon#first serial, iclass 12, count 2 2006.201.19:17:10.62#ibcon#enter sib2, iclass 12, count 2 2006.201.19:17:10.62#ibcon#flushed, iclass 12, count 2 2006.201.19:17:10.62#ibcon#about to write, iclass 12, count 2 2006.201.19:17:10.62#ibcon#wrote, iclass 12, count 2 2006.201.19:17:10.62#ibcon#about to read 3, iclass 12, count 2 2006.201.19:17:10.64#ibcon#read 3, iclass 12, count 2 2006.201.19:17:10.64#ibcon#about to read 4, iclass 12, count 2 2006.201.19:17:10.64#ibcon#read 4, iclass 12, count 2 2006.201.19:17:10.64#ibcon#about to read 5, iclass 12, count 2 2006.201.19:17:10.64#ibcon#read 5, iclass 12, count 2 2006.201.19:17:10.64#ibcon#about to read 6, iclass 12, count 2 2006.201.19:17:10.64#ibcon#read 6, iclass 12, count 2 2006.201.19:17:10.64#ibcon#end of sib2, iclass 12, count 2 2006.201.19:17:10.64#ibcon#*mode == 0, iclass 12, count 2 2006.201.19:17:10.64#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.19:17:10.64#ibcon#[27=AT04-05\r\n] 2006.201.19:17:10.64#ibcon#*before write, iclass 12, count 2 2006.201.19:17:10.64#ibcon#enter sib2, iclass 12, count 2 2006.201.19:17:10.64#ibcon#flushed, iclass 12, count 2 2006.201.19:17:10.64#ibcon#about to write, iclass 12, count 2 2006.201.19:17:10.64#ibcon#wrote, iclass 12, count 2 2006.201.19:17:10.64#ibcon#about to read 3, iclass 12, count 2 2006.201.19:17:10.67#ibcon#read 3, iclass 12, count 2 2006.201.19:17:10.67#ibcon#about to read 4, iclass 12, count 2 2006.201.19:17:10.67#ibcon#read 4, iclass 12, count 2 2006.201.19:17:10.67#ibcon#about to read 5, iclass 12, count 2 2006.201.19:17:10.67#ibcon#read 5, iclass 12, count 2 2006.201.19:17:10.67#ibcon#about to read 6, iclass 12, count 2 2006.201.19:17:10.67#ibcon#read 6, iclass 12, count 2 2006.201.19:17:10.67#ibcon#end of sib2, iclass 12, count 2 2006.201.19:17:10.67#ibcon#*after write, iclass 12, count 2 2006.201.19:17:10.67#ibcon#*before return 0, iclass 12, count 2 2006.201.19:17:10.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:10.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:17:10.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.19:17:10.67#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:10.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:10.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:10.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:10.79#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:17:10.79#ibcon#first serial, iclass 12, count 0 2006.201.19:17:10.79#ibcon#enter sib2, iclass 12, count 0 2006.201.19:17:10.79#ibcon#flushed, iclass 12, count 0 2006.201.19:17:10.79#ibcon#about to write, iclass 12, count 0 2006.201.19:17:10.79#ibcon#wrote, iclass 12, count 0 2006.201.19:17:10.79#ibcon#about to read 3, iclass 12, count 0 2006.201.19:17:10.81#ibcon#read 3, iclass 12, count 0 2006.201.19:17:10.81#ibcon#about to read 4, iclass 12, count 0 2006.201.19:17:10.81#ibcon#read 4, iclass 12, count 0 2006.201.19:17:10.81#ibcon#about to read 5, iclass 12, count 0 2006.201.19:17:10.81#ibcon#read 5, iclass 12, count 0 2006.201.19:17:10.81#ibcon#about to read 6, iclass 12, count 0 2006.201.19:17:10.81#ibcon#read 6, iclass 12, count 0 2006.201.19:17:10.81#ibcon#end of sib2, iclass 12, count 0 2006.201.19:17:10.81#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:17:10.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:17:10.81#ibcon#[27=USB\r\n] 2006.201.19:17:10.81#ibcon#*before write, iclass 12, count 0 2006.201.19:17:10.81#ibcon#enter sib2, iclass 12, count 0 2006.201.19:17:10.81#ibcon#flushed, iclass 12, count 0 2006.201.19:17:10.81#ibcon#about to write, iclass 12, count 0 2006.201.19:17:10.81#ibcon#wrote, iclass 12, count 0 2006.201.19:17:10.81#ibcon#about to read 3, iclass 12, count 0 2006.201.19:17:10.84#ibcon#read 3, iclass 12, count 0 2006.201.19:17:10.84#ibcon#about to read 4, iclass 12, count 0 2006.201.19:17:10.84#ibcon#read 4, iclass 12, count 0 2006.201.19:17:10.84#ibcon#about to read 5, iclass 12, count 0 2006.201.19:17:10.84#ibcon#read 5, iclass 12, count 0 2006.201.19:17:10.84#ibcon#about to read 6, iclass 12, count 0 2006.201.19:17:10.84#ibcon#read 6, iclass 12, count 0 2006.201.19:17:10.84#ibcon#end of sib2, iclass 12, count 0 2006.201.19:17:10.84#ibcon#*after write, iclass 12, count 0 2006.201.19:17:10.84#ibcon#*before return 0, iclass 12, count 0 2006.201.19:17:10.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:10.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:17:10.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:17:10.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:17:10.84$vck44/vblo=5,709.99 2006.201.19:17:10.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.19:17:10.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.19:17:10.84#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:10.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:10.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:10.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:10.84#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:17:10.84#ibcon#first serial, iclass 14, count 0 2006.201.19:17:10.84#ibcon#enter sib2, iclass 14, count 0 2006.201.19:17:10.84#ibcon#flushed, iclass 14, count 0 2006.201.19:17:10.84#ibcon#about to write, iclass 14, count 0 2006.201.19:17:10.84#ibcon#wrote, iclass 14, count 0 2006.201.19:17:10.84#ibcon#about to read 3, iclass 14, count 0 2006.201.19:17:10.86#ibcon#read 3, iclass 14, count 0 2006.201.19:17:10.86#ibcon#about to read 4, iclass 14, count 0 2006.201.19:17:10.86#ibcon#read 4, iclass 14, count 0 2006.201.19:17:10.86#ibcon#about to read 5, iclass 14, count 0 2006.201.19:17:10.86#ibcon#read 5, iclass 14, count 0 2006.201.19:17:10.86#ibcon#about to read 6, iclass 14, count 0 2006.201.19:17:10.86#ibcon#read 6, iclass 14, count 0 2006.201.19:17:10.86#ibcon#end of sib2, iclass 14, count 0 2006.201.19:17:10.86#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:17:10.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:17:10.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:17:10.86#ibcon#*before write, iclass 14, count 0 2006.201.19:17:10.86#ibcon#enter sib2, iclass 14, count 0 2006.201.19:17:10.86#ibcon#flushed, iclass 14, count 0 2006.201.19:17:10.86#ibcon#about to write, iclass 14, count 0 2006.201.19:17:10.86#ibcon#wrote, iclass 14, count 0 2006.201.19:17:10.86#ibcon#about to read 3, iclass 14, count 0 2006.201.19:17:10.90#ibcon#read 3, iclass 14, count 0 2006.201.19:17:10.90#ibcon#about to read 4, iclass 14, count 0 2006.201.19:17:10.90#ibcon#read 4, iclass 14, count 0 2006.201.19:17:10.90#ibcon#about to read 5, iclass 14, count 0 2006.201.19:17:10.90#ibcon#read 5, iclass 14, count 0 2006.201.19:17:10.90#ibcon#about to read 6, iclass 14, count 0 2006.201.19:17:10.90#ibcon#read 6, iclass 14, count 0 2006.201.19:17:10.90#ibcon#end of sib2, iclass 14, count 0 2006.201.19:17:10.90#ibcon#*after write, iclass 14, count 0 2006.201.19:17:10.90#ibcon#*before return 0, iclass 14, count 0 2006.201.19:17:10.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:10.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:17:10.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:17:10.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:17:10.90$vck44/vb=5,4 2006.201.19:17:10.90#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.19:17:10.90#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.19:17:10.90#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:10.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:10.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:10.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:10.96#ibcon#enter wrdev, iclass 16, count 2 2006.201.19:17:10.96#ibcon#first serial, iclass 16, count 2 2006.201.19:17:10.96#ibcon#enter sib2, iclass 16, count 2 2006.201.19:17:10.96#ibcon#flushed, iclass 16, count 2 2006.201.19:17:10.96#ibcon#about to write, iclass 16, count 2 2006.201.19:17:10.96#ibcon#wrote, iclass 16, count 2 2006.201.19:17:10.96#ibcon#about to read 3, iclass 16, count 2 2006.201.19:17:10.98#ibcon#read 3, iclass 16, count 2 2006.201.19:17:10.98#ibcon#about to read 4, iclass 16, count 2 2006.201.19:17:10.98#ibcon#read 4, iclass 16, count 2 2006.201.19:17:10.98#ibcon#about to read 5, iclass 16, count 2 2006.201.19:17:10.98#ibcon#read 5, iclass 16, count 2 2006.201.19:17:10.98#ibcon#about to read 6, iclass 16, count 2 2006.201.19:17:10.98#ibcon#read 6, iclass 16, count 2 2006.201.19:17:10.98#ibcon#end of sib2, iclass 16, count 2 2006.201.19:17:10.98#ibcon#*mode == 0, iclass 16, count 2 2006.201.19:17:10.98#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.19:17:10.98#ibcon#[27=AT05-04\r\n] 2006.201.19:17:10.98#ibcon#*before write, iclass 16, count 2 2006.201.19:17:10.98#ibcon#enter sib2, iclass 16, count 2 2006.201.19:17:10.98#ibcon#flushed, iclass 16, count 2 2006.201.19:17:10.98#ibcon#about to write, iclass 16, count 2 2006.201.19:17:10.98#ibcon#wrote, iclass 16, count 2 2006.201.19:17:10.98#ibcon#about to read 3, iclass 16, count 2 2006.201.19:17:11.01#ibcon#read 3, iclass 16, count 2 2006.201.19:17:11.01#ibcon#about to read 4, iclass 16, count 2 2006.201.19:17:11.01#ibcon#read 4, iclass 16, count 2 2006.201.19:17:11.01#ibcon#about to read 5, iclass 16, count 2 2006.201.19:17:11.01#ibcon#read 5, iclass 16, count 2 2006.201.19:17:11.01#ibcon#about to read 6, iclass 16, count 2 2006.201.19:17:11.01#ibcon#read 6, iclass 16, count 2 2006.201.19:17:11.01#ibcon#end of sib2, iclass 16, count 2 2006.201.19:17:11.01#ibcon#*after write, iclass 16, count 2 2006.201.19:17:11.01#ibcon#*before return 0, iclass 16, count 2 2006.201.19:17:11.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:11.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:17:11.01#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.19:17:11.01#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:11.01#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:11.13#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:11.13#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:11.13#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:17:11.13#ibcon#first serial, iclass 16, count 0 2006.201.19:17:11.13#ibcon#enter sib2, iclass 16, count 0 2006.201.19:17:11.13#ibcon#flushed, iclass 16, count 0 2006.201.19:17:11.13#ibcon#about to write, iclass 16, count 0 2006.201.19:17:11.13#ibcon#wrote, iclass 16, count 0 2006.201.19:17:11.13#ibcon#about to read 3, iclass 16, count 0 2006.201.19:17:11.15#ibcon#read 3, iclass 16, count 0 2006.201.19:17:11.15#ibcon#about to read 4, iclass 16, count 0 2006.201.19:17:11.15#ibcon#read 4, iclass 16, count 0 2006.201.19:17:11.15#ibcon#about to read 5, iclass 16, count 0 2006.201.19:17:11.15#ibcon#read 5, iclass 16, count 0 2006.201.19:17:11.15#ibcon#about to read 6, iclass 16, count 0 2006.201.19:17:11.15#ibcon#read 6, iclass 16, count 0 2006.201.19:17:11.15#ibcon#end of sib2, iclass 16, count 0 2006.201.19:17:11.15#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:17:11.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:17:11.15#ibcon#[27=USB\r\n] 2006.201.19:17:11.15#ibcon#*before write, iclass 16, count 0 2006.201.19:17:11.15#ibcon#enter sib2, iclass 16, count 0 2006.201.19:17:11.15#ibcon#flushed, iclass 16, count 0 2006.201.19:17:11.15#ibcon#about to write, iclass 16, count 0 2006.201.19:17:11.15#ibcon#wrote, iclass 16, count 0 2006.201.19:17:11.15#ibcon#about to read 3, iclass 16, count 0 2006.201.19:17:11.18#ibcon#read 3, iclass 16, count 0 2006.201.19:17:11.18#ibcon#about to read 4, iclass 16, count 0 2006.201.19:17:11.18#ibcon#read 4, iclass 16, count 0 2006.201.19:17:11.18#ibcon#about to read 5, iclass 16, count 0 2006.201.19:17:11.18#ibcon#read 5, iclass 16, count 0 2006.201.19:17:11.18#ibcon#about to read 6, iclass 16, count 0 2006.201.19:17:11.18#ibcon#read 6, iclass 16, count 0 2006.201.19:17:11.18#ibcon#end of sib2, iclass 16, count 0 2006.201.19:17:11.18#ibcon#*after write, iclass 16, count 0 2006.201.19:17:11.18#ibcon#*before return 0, iclass 16, count 0 2006.201.19:17:11.18#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:11.18#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:17:11.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:17:11.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:17:11.18$vck44/vblo=6,719.99 2006.201.19:17:11.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.19:17:11.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.19:17:11.18#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:11.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:11.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:11.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:11.18#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:17:11.18#ibcon#first serial, iclass 18, count 0 2006.201.19:17:11.18#ibcon#enter sib2, iclass 18, count 0 2006.201.19:17:11.18#ibcon#flushed, iclass 18, count 0 2006.201.19:17:11.18#ibcon#about to write, iclass 18, count 0 2006.201.19:17:11.18#ibcon#wrote, iclass 18, count 0 2006.201.19:17:11.18#ibcon#about to read 3, iclass 18, count 0 2006.201.19:17:11.20#ibcon#read 3, iclass 18, count 0 2006.201.19:17:11.20#ibcon#about to read 4, iclass 18, count 0 2006.201.19:17:11.20#ibcon#read 4, iclass 18, count 0 2006.201.19:17:11.20#ibcon#about to read 5, iclass 18, count 0 2006.201.19:17:11.20#ibcon#read 5, iclass 18, count 0 2006.201.19:17:11.20#ibcon#about to read 6, iclass 18, count 0 2006.201.19:17:11.20#ibcon#read 6, iclass 18, count 0 2006.201.19:17:11.20#ibcon#end of sib2, iclass 18, count 0 2006.201.19:17:11.20#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:17:11.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:17:11.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:17:11.20#ibcon#*before write, iclass 18, count 0 2006.201.19:17:11.20#ibcon#enter sib2, iclass 18, count 0 2006.201.19:17:11.20#ibcon#flushed, iclass 18, count 0 2006.201.19:17:11.20#ibcon#about to write, iclass 18, count 0 2006.201.19:17:11.20#ibcon#wrote, iclass 18, count 0 2006.201.19:17:11.20#ibcon#about to read 3, iclass 18, count 0 2006.201.19:17:11.24#ibcon#read 3, iclass 18, count 0 2006.201.19:17:11.24#ibcon#about to read 4, iclass 18, count 0 2006.201.19:17:11.24#ibcon#read 4, iclass 18, count 0 2006.201.19:17:11.24#ibcon#about to read 5, iclass 18, count 0 2006.201.19:17:11.24#ibcon#read 5, iclass 18, count 0 2006.201.19:17:11.24#ibcon#about to read 6, iclass 18, count 0 2006.201.19:17:11.24#ibcon#read 6, iclass 18, count 0 2006.201.19:17:11.24#ibcon#end of sib2, iclass 18, count 0 2006.201.19:17:11.24#ibcon#*after write, iclass 18, count 0 2006.201.19:17:11.24#ibcon#*before return 0, iclass 18, count 0 2006.201.19:17:11.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:11.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:17:11.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:17:11.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:17:11.24$vck44/vb=6,4 2006.201.19:17:11.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.19:17:11.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.19:17:11.24#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:11.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:11.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:11.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:11.30#ibcon#enter wrdev, iclass 20, count 2 2006.201.19:17:11.30#ibcon#first serial, iclass 20, count 2 2006.201.19:17:11.30#ibcon#enter sib2, iclass 20, count 2 2006.201.19:17:11.30#ibcon#flushed, iclass 20, count 2 2006.201.19:17:11.30#ibcon#about to write, iclass 20, count 2 2006.201.19:17:11.30#ibcon#wrote, iclass 20, count 2 2006.201.19:17:11.30#ibcon#about to read 3, iclass 20, count 2 2006.201.19:17:11.32#ibcon#read 3, iclass 20, count 2 2006.201.19:17:11.32#ibcon#about to read 4, iclass 20, count 2 2006.201.19:17:11.32#ibcon#read 4, iclass 20, count 2 2006.201.19:17:11.32#ibcon#about to read 5, iclass 20, count 2 2006.201.19:17:11.32#ibcon#read 5, iclass 20, count 2 2006.201.19:17:11.32#ibcon#about to read 6, iclass 20, count 2 2006.201.19:17:11.32#ibcon#read 6, iclass 20, count 2 2006.201.19:17:11.32#ibcon#end of sib2, iclass 20, count 2 2006.201.19:17:11.32#ibcon#*mode == 0, iclass 20, count 2 2006.201.19:17:11.32#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.19:17:11.32#ibcon#[27=AT06-04\r\n] 2006.201.19:17:11.32#ibcon#*before write, iclass 20, count 2 2006.201.19:17:11.32#ibcon#enter sib2, iclass 20, count 2 2006.201.19:17:11.32#ibcon#flushed, iclass 20, count 2 2006.201.19:17:11.32#ibcon#about to write, iclass 20, count 2 2006.201.19:17:11.32#ibcon#wrote, iclass 20, count 2 2006.201.19:17:11.32#ibcon#about to read 3, iclass 20, count 2 2006.201.19:17:11.35#ibcon#read 3, iclass 20, count 2 2006.201.19:17:11.35#ibcon#about to read 4, iclass 20, count 2 2006.201.19:17:11.35#ibcon#read 4, iclass 20, count 2 2006.201.19:17:11.35#ibcon#about to read 5, iclass 20, count 2 2006.201.19:17:11.35#ibcon#read 5, iclass 20, count 2 2006.201.19:17:11.35#ibcon#about to read 6, iclass 20, count 2 2006.201.19:17:11.35#ibcon#read 6, iclass 20, count 2 2006.201.19:17:11.35#ibcon#end of sib2, iclass 20, count 2 2006.201.19:17:11.35#ibcon#*after write, iclass 20, count 2 2006.201.19:17:11.35#ibcon#*before return 0, iclass 20, count 2 2006.201.19:17:11.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:11.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:17:11.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.19:17:11.35#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:11.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:11.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:11.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:11.47#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:17:11.47#ibcon#first serial, iclass 20, count 0 2006.201.19:17:11.47#ibcon#enter sib2, iclass 20, count 0 2006.201.19:17:11.47#ibcon#flushed, iclass 20, count 0 2006.201.19:17:11.47#ibcon#about to write, iclass 20, count 0 2006.201.19:17:11.47#ibcon#wrote, iclass 20, count 0 2006.201.19:17:11.47#ibcon#about to read 3, iclass 20, count 0 2006.201.19:17:11.49#ibcon#read 3, iclass 20, count 0 2006.201.19:17:11.49#ibcon#about to read 4, iclass 20, count 0 2006.201.19:17:11.49#ibcon#read 4, iclass 20, count 0 2006.201.19:17:11.49#ibcon#about to read 5, iclass 20, count 0 2006.201.19:17:11.49#ibcon#read 5, iclass 20, count 0 2006.201.19:17:11.49#ibcon#about to read 6, iclass 20, count 0 2006.201.19:17:11.49#ibcon#read 6, iclass 20, count 0 2006.201.19:17:11.49#ibcon#end of sib2, iclass 20, count 0 2006.201.19:17:11.49#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:17:11.49#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:17:11.49#ibcon#[27=USB\r\n] 2006.201.19:17:11.49#ibcon#*before write, iclass 20, count 0 2006.201.19:17:11.49#ibcon#enter sib2, iclass 20, count 0 2006.201.19:17:11.49#ibcon#flushed, iclass 20, count 0 2006.201.19:17:11.49#ibcon#about to write, iclass 20, count 0 2006.201.19:17:11.49#ibcon#wrote, iclass 20, count 0 2006.201.19:17:11.49#ibcon#about to read 3, iclass 20, count 0 2006.201.19:17:11.52#ibcon#read 3, iclass 20, count 0 2006.201.19:17:11.52#ibcon#about to read 4, iclass 20, count 0 2006.201.19:17:11.52#ibcon#read 4, iclass 20, count 0 2006.201.19:17:11.52#ibcon#about to read 5, iclass 20, count 0 2006.201.19:17:11.52#ibcon#read 5, iclass 20, count 0 2006.201.19:17:11.52#ibcon#about to read 6, iclass 20, count 0 2006.201.19:17:11.52#ibcon#read 6, iclass 20, count 0 2006.201.19:17:11.52#ibcon#end of sib2, iclass 20, count 0 2006.201.19:17:11.52#ibcon#*after write, iclass 20, count 0 2006.201.19:17:11.52#ibcon#*before return 0, iclass 20, count 0 2006.201.19:17:11.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:11.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:17:11.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:17:11.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:17:11.52$vck44/vblo=7,734.99 2006.201.19:17:11.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.19:17:11.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.19:17:11.52#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:11.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:11.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:11.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:11.52#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:17:11.52#ibcon#first serial, iclass 22, count 0 2006.201.19:17:11.52#ibcon#enter sib2, iclass 22, count 0 2006.201.19:17:11.52#ibcon#flushed, iclass 22, count 0 2006.201.19:17:11.52#ibcon#about to write, iclass 22, count 0 2006.201.19:17:11.52#ibcon#wrote, iclass 22, count 0 2006.201.19:17:11.52#ibcon#about to read 3, iclass 22, count 0 2006.201.19:17:11.54#ibcon#read 3, iclass 22, count 0 2006.201.19:17:11.54#ibcon#about to read 4, iclass 22, count 0 2006.201.19:17:11.54#ibcon#read 4, iclass 22, count 0 2006.201.19:17:11.54#ibcon#about to read 5, iclass 22, count 0 2006.201.19:17:11.54#ibcon#read 5, iclass 22, count 0 2006.201.19:17:11.54#ibcon#about to read 6, iclass 22, count 0 2006.201.19:17:11.54#ibcon#read 6, iclass 22, count 0 2006.201.19:17:11.54#ibcon#end of sib2, iclass 22, count 0 2006.201.19:17:11.54#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:17:11.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:17:11.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:17:11.54#ibcon#*before write, iclass 22, count 0 2006.201.19:17:11.54#ibcon#enter sib2, iclass 22, count 0 2006.201.19:17:11.54#ibcon#flushed, iclass 22, count 0 2006.201.19:17:11.54#ibcon#about to write, iclass 22, count 0 2006.201.19:17:11.54#ibcon#wrote, iclass 22, count 0 2006.201.19:17:11.54#ibcon#about to read 3, iclass 22, count 0 2006.201.19:17:11.58#ibcon#read 3, iclass 22, count 0 2006.201.19:17:11.58#ibcon#about to read 4, iclass 22, count 0 2006.201.19:17:11.58#ibcon#read 4, iclass 22, count 0 2006.201.19:17:11.58#ibcon#about to read 5, iclass 22, count 0 2006.201.19:17:11.58#ibcon#read 5, iclass 22, count 0 2006.201.19:17:11.58#ibcon#about to read 6, iclass 22, count 0 2006.201.19:17:11.58#ibcon#read 6, iclass 22, count 0 2006.201.19:17:11.58#ibcon#end of sib2, iclass 22, count 0 2006.201.19:17:11.58#ibcon#*after write, iclass 22, count 0 2006.201.19:17:11.58#ibcon#*before return 0, iclass 22, count 0 2006.201.19:17:11.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:11.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:17:11.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:17:11.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:17:11.58$vck44/vb=7,4 2006.201.19:17:11.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.19:17:11.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.19:17:11.58#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:11.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:11.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:11.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:11.64#ibcon#enter wrdev, iclass 24, count 2 2006.201.19:17:11.64#ibcon#first serial, iclass 24, count 2 2006.201.19:17:11.64#ibcon#enter sib2, iclass 24, count 2 2006.201.19:17:11.64#ibcon#flushed, iclass 24, count 2 2006.201.19:17:11.64#ibcon#about to write, iclass 24, count 2 2006.201.19:17:11.64#ibcon#wrote, iclass 24, count 2 2006.201.19:17:11.64#ibcon#about to read 3, iclass 24, count 2 2006.201.19:17:11.66#ibcon#read 3, iclass 24, count 2 2006.201.19:17:11.66#ibcon#about to read 4, iclass 24, count 2 2006.201.19:17:11.66#ibcon#read 4, iclass 24, count 2 2006.201.19:17:11.66#ibcon#about to read 5, iclass 24, count 2 2006.201.19:17:11.66#ibcon#read 5, iclass 24, count 2 2006.201.19:17:11.66#ibcon#about to read 6, iclass 24, count 2 2006.201.19:17:11.66#ibcon#read 6, iclass 24, count 2 2006.201.19:17:11.66#ibcon#end of sib2, iclass 24, count 2 2006.201.19:17:11.66#ibcon#*mode == 0, iclass 24, count 2 2006.201.19:17:11.66#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.19:17:11.66#ibcon#[27=AT07-04\r\n] 2006.201.19:17:11.66#ibcon#*before write, iclass 24, count 2 2006.201.19:17:11.66#ibcon#enter sib2, iclass 24, count 2 2006.201.19:17:11.66#ibcon#flushed, iclass 24, count 2 2006.201.19:17:11.66#ibcon#about to write, iclass 24, count 2 2006.201.19:17:11.66#ibcon#wrote, iclass 24, count 2 2006.201.19:17:11.66#ibcon#about to read 3, iclass 24, count 2 2006.201.19:17:11.69#ibcon#read 3, iclass 24, count 2 2006.201.19:17:11.69#ibcon#about to read 4, iclass 24, count 2 2006.201.19:17:11.69#ibcon#read 4, iclass 24, count 2 2006.201.19:17:11.69#ibcon#about to read 5, iclass 24, count 2 2006.201.19:17:11.69#ibcon#read 5, iclass 24, count 2 2006.201.19:17:11.69#ibcon#about to read 6, iclass 24, count 2 2006.201.19:17:11.69#ibcon#read 6, iclass 24, count 2 2006.201.19:17:11.69#ibcon#end of sib2, iclass 24, count 2 2006.201.19:17:11.69#ibcon#*after write, iclass 24, count 2 2006.201.19:17:11.69#ibcon#*before return 0, iclass 24, count 2 2006.201.19:17:11.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:11.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:17:11.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.19:17:11.69#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:11.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:11.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:11.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:11.81#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:17:11.81#ibcon#first serial, iclass 24, count 0 2006.201.19:17:11.81#ibcon#enter sib2, iclass 24, count 0 2006.201.19:17:11.81#ibcon#flushed, iclass 24, count 0 2006.201.19:17:11.81#ibcon#about to write, iclass 24, count 0 2006.201.19:17:11.81#ibcon#wrote, iclass 24, count 0 2006.201.19:17:11.81#ibcon#about to read 3, iclass 24, count 0 2006.201.19:17:11.83#ibcon#read 3, iclass 24, count 0 2006.201.19:17:11.83#ibcon#about to read 4, iclass 24, count 0 2006.201.19:17:11.83#ibcon#read 4, iclass 24, count 0 2006.201.19:17:11.83#ibcon#about to read 5, iclass 24, count 0 2006.201.19:17:11.83#ibcon#read 5, iclass 24, count 0 2006.201.19:17:11.83#ibcon#about to read 6, iclass 24, count 0 2006.201.19:17:11.83#ibcon#read 6, iclass 24, count 0 2006.201.19:17:11.83#ibcon#end of sib2, iclass 24, count 0 2006.201.19:17:11.83#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:17:11.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:17:11.83#ibcon#[27=USB\r\n] 2006.201.19:17:11.83#ibcon#*before write, iclass 24, count 0 2006.201.19:17:11.83#ibcon#enter sib2, iclass 24, count 0 2006.201.19:17:11.83#ibcon#flushed, iclass 24, count 0 2006.201.19:17:11.83#ibcon#about to write, iclass 24, count 0 2006.201.19:17:11.83#ibcon#wrote, iclass 24, count 0 2006.201.19:17:11.83#ibcon#about to read 3, iclass 24, count 0 2006.201.19:17:11.86#ibcon#read 3, iclass 24, count 0 2006.201.19:17:11.86#ibcon#about to read 4, iclass 24, count 0 2006.201.19:17:11.86#ibcon#read 4, iclass 24, count 0 2006.201.19:17:11.86#ibcon#about to read 5, iclass 24, count 0 2006.201.19:17:11.86#ibcon#read 5, iclass 24, count 0 2006.201.19:17:11.86#ibcon#about to read 6, iclass 24, count 0 2006.201.19:17:11.86#ibcon#read 6, iclass 24, count 0 2006.201.19:17:11.86#ibcon#end of sib2, iclass 24, count 0 2006.201.19:17:11.86#ibcon#*after write, iclass 24, count 0 2006.201.19:17:11.86#ibcon#*before return 0, iclass 24, count 0 2006.201.19:17:11.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:11.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:17:11.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:17:11.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:17:11.86$vck44/vblo=8,744.99 2006.201.19:17:11.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.19:17:11.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.19:17:11.86#ibcon#ireg 17 cls_cnt 0 2006.201.19:17:11.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:11.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:11.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:11.86#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:17:11.86#ibcon#first serial, iclass 26, count 0 2006.201.19:17:11.86#ibcon#enter sib2, iclass 26, count 0 2006.201.19:17:11.86#ibcon#flushed, iclass 26, count 0 2006.201.19:17:11.86#ibcon#about to write, iclass 26, count 0 2006.201.19:17:11.86#ibcon#wrote, iclass 26, count 0 2006.201.19:17:11.86#ibcon#about to read 3, iclass 26, count 0 2006.201.19:17:11.88#ibcon#read 3, iclass 26, count 0 2006.201.19:17:11.88#ibcon#about to read 4, iclass 26, count 0 2006.201.19:17:11.88#ibcon#read 4, iclass 26, count 0 2006.201.19:17:11.88#ibcon#about to read 5, iclass 26, count 0 2006.201.19:17:11.88#ibcon#read 5, iclass 26, count 0 2006.201.19:17:11.88#ibcon#about to read 6, iclass 26, count 0 2006.201.19:17:11.88#ibcon#read 6, iclass 26, count 0 2006.201.19:17:11.88#ibcon#end of sib2, iclass 26, count 0 2006.201.19:17:11.88#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:17:11.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:17:11.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:17:11.88#ibcon#*before write, iclass 26, count 0 2006.201.19:17:11.88#ibcon#enter sib2, iclass 26, count 0 2006.201.19:17:11.88#ibcon#flushed, iclass 26, count 0 2006.201.19:17:11.88#ibcon#about to write, iclass 26, count 0 2006.201.19:17:11.88#ibcon#wrote, iclass 26, count 0 2006.201.19:17:11.88#ibcon#about to read 3, iclass 26, count 0 2006.201.19:17:11.92#ibcon#read 3, iclass 26, count 0 2006.201.19:17:11.92#ibcon#about to read 4, iclass 26, count 0 2006.201.19:17:11.92#ibcon#read 4, iclass 26, count 0 2006.201.19:17:11.92#ibcon#about to read 5, iclass 26, count 0 2006.201.19:17:11.92#ibcon#read 5, iclass 26, count 0 2006.201.19:17:11.92#ibcon#about to read 6, iclass 26, count 0 2006.201.19:17:11.92#ibcon#read 6, iclass 26, count 0 2006.201.19:17:11.92#ibcon#end of sib2, iclass 26, count 0 2006.201.19:17:11.92#ibcon#*after write, iclass 26, count 0 2006.201.19:17:11.92#ibcon#*before return 0, iclass 26, count 0 2006.201.19:17:11.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:11.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:17:11.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:17:11.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:17:11.92$vck44/vb=8,4 2006.201.19:17:11.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.19:17:11.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.19:17:11.92#ibcon#ireg 11 cls_cnt 2 2006.201.19:17:11.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:11.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:11.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:11.98#ibcon#enter wrdev, iclass 28, count 2 2006.201.19:17:11.98#ibcon#first serial, iclass 28, count 2 2006.201.19:17:11.98#ibcon#enter sib2, iclass 28, count 2 2006.201.19:17:11.98#ibcon#flushed, iclass 28, count 2 2006.201.19:17:11.98#ibcon#about to write, iclass 28, count 2 2006.201.19:17:11.98#ibcon#wrote, iclass 28, count 2 2006.201.19:17:11.98#ibcon#about to read 3, iclass 28, count 2 2006.201.19:17:12.00#ibcon#read 3, iclass 28, count 2 2006.201.19:17:12.00#ibcon#about to read 4, iclass 28, count 2 2006.201.19:17:12.00#ibcon#read 4, iclass 28, count 2 2006.201.19:17:12.00#ibcon#about to read 5, iclass 28, count 2 2006.201.19:17:12.00#ibcon#read 5, iclass 28, count 2 2006.201.19:17:12.00#ibcon#about to read 6, iclass 28, count 2 2006.201.19:17:12.00#ibcon#read 6, iclass 28, count 2 2006.201.19:17:12.00#ibcon#end of sib2, iclass 28, count 2 2006.201.19:17:12.00#ibcon#*mode == 0, iclass 28, count 2 2006.201.19:17:12.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.19:17:12.00#ibcon#[27=AT08-04\r\n] 2006.201.19:17:12.00#ibcon#*before write, iclass 28, count 2 2006.201.19:17:12.00#ibcon#enter sib2, iclass 28, count 2 2006.201.19:17:12.00#ibcon#flushed, iclass 28, count 2 2006.201.19:17:12.00#ibcon#about to write, iclass 28, count 2 2006.201.19:17:12.00#ibcon#wrote, iclass 28, count 2 2006.201.19:17:12.00#ibcon#about to read 3, iclass 28, count 2 2006.201.19:17:12.03#ibcon#read 3, iclass 28, count 2 2006.201.19:17:12.03#ibcon#about to read 4, iclass 28, count 2 2006.201.19:17:12.03#ibcon#read 4, iclass 28, count 2 2006.201.19:17:12.03#ibcon#about to read 5, iclass 28, count 2 2006.201.19:17:12.03#ibcon#read 5, iclass 28, count 2 2006.201.19:17:12.03#ibcon#about to read 6, iclass 28, count 2 2006.201.19:17:12.03#ibcon#read 6, iclass 28, count 2 2006.201.19:17:12.03#ibcon#end of sib2, iclass 28, count 2 2006.201.19:17:12.03#ibcon#*after write, iclass 28, count 2 2006.201.19:17:12.03#ibcon#*before return 0, iclass 28, count 2 2006.201.19:17:12.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:12.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:17:12.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.19:17:12.03#ibcon#ireg 7 cls_cnt 0 2006.201.19:17:12.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:12.15#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:12.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:12.15#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:17:12.15#ibcon#first serial, iclass 28, count 0 2006.201.19:17:12.15#ibcon#enter sib2, iclass 28, count 0 2006.201.19:17:12.15#ibcon#flushed, iclass 28, count 0 2006.201.19:17:12.15#ibcon#about to write, iclass 28, count 0 2006.201.19:17:12.15#ibcon#wrote, iclass 28, count 0 2006.201.19:17:12.15#ibcon#about to read 3, iclass 28, count 0 2006.201.19:17:12.17#ibcon#read 3, iclass 28, count 0 2006.201.19:17:12.17#ibcon#about to read 4, iclass 28, count 0 2006.201.19:17:12.17#ibcon#read 4, iclass 28, count 0 2006.201.19:17:12.17#ibcon#about to read 5, iclass 28, count 0 2006.201.19:17:12.17#ibcon#read 5, iclass 28, count 0 2006.201.19:17:12.17#ibcon#about to read 6, iclass 28, count 0 2006.201.19:17:12.17#ibcon#read 6, iclass 28, count 0 2006.201.19:17:12.17#ibcon#end of sib2, iclass 28, count 0 2006.201.19:17:12.17#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:17:12.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:17:12.17#ibcon#[27=USB\r\n] 2006.201.19:17:12.17#ibcon#*before write, iclass 28, count 0 2006.201.19:17:12.17#ibcon#enter sib2, iclass 28, count 0 2006.201.19:17:12.17#ibcon#flushed, iclass 28, count 0 2006.201.19:17:12.17#ibcon#about to write, iclass 28, count 0 2006.201.19:17:12.17#ibcon#wrote, iclass 28, count 0 2006.201.19:17:12.17#ibcon#about to read 3, iclass 28, count 0 2006.201.19:17:12.20#ibcon#read 3, iclass 28, count 0 2006.201.19:17:12.20#ibcon#about to read 4, iclass 28, count 0 2006.201.19:17:12.20#ibcon#read 4, iclass 28, count 0 2006.201.19:17:12.20#ibcon#about to read 5, iclass 28, count 0 2006.201.19:17:12.20#ibcon#read 5, iclass 28, count 0 2006.201.19:17:12.20#ibcon#about to read 6, iclass 28, count 0 2006.201.19:17:12.20#ibcon#read 6, iclass 28, count 0 2006.201.19:17:12.20#ibcon#end of sib2, iclass 28, count 0 2006.201.19:17:12.20#ibcon#*after write, iclass 28, count 0 2006.201.19:17:12.20#ibcon#*before return 0, iclass 28, count 0 2006.201.19:17:12.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:12.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:17:12.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:17:12.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:17:12.20$vck44/vabw=wide 2006.201.19:17:12.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.19:17:12.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.19:17:12.20#ibcon#ireg 8 cls_cnt 0 2006.201.19:17:12.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:12.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:12.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:12.20#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:17:12.20#ibcon#first serial, iclass 30, count 0 2006.201.19:17:12.20#ibcon#enter sib2, iclass 30, count 0 2006.201.19:17:12.20#ibcon#flushed, iclass 30, count 0 2006.201.19:17:12.20#ibcon#about to write, iclass 30, count 0 2006.201.19:17:12.20#ibcon#wrote, iclass 30, count 0 2006.201.19:17:12.20#ibcon#about to read 3, iclass 30, count 0 2006.201.19:17:12.22#ibcon#read 3, iclass 30, count 0 2006.201.19:17:12.22#ibcon#about to read 4, iclass 30, count 0 2006.201.19:17:12.22#ibcon#read 4, iclass 30, count 0 2006.201.19:17:12.22#ibcon#about to read 5, iclass 30, count 0 2006.201.19:17:12.22#ibcon#read 5, iclass 30, count 0 2006.201.19:17:12.22#ibcon#about to read 6, iclass 30, count 0 2006.201.19:17:12.22#ibcon#read 6, iclass 30, count 0 2006.201.19:17:12.22#ibcon#end of sib2, iclass 30, count 0 2006.201.19:17:12.22#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:17:12.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:17:12.22#ibcon#[25=BW32\r\n] 2006.201.19:17:12.22#ibcon#*before write, iclass 30, count 0 2006.201.19:17:12.22#ibcon#enter sib2, iclass 30, count 0 2006.201.19:17:12.22#ibcon#flushed, iclass 30, count 0 2006.201.19:17:12.22#ibcon#about to write, iclass 30, count 0 2006.201.19:17:12.22#ibcon#wrote, iclass 30, count 0 2006.201.19:17:12.22#ibcon#about to read 3, iclass 30, count 0 2006.201.19:17:12.25#ibcon#read 3, iclass 30, count 0 2006.201.19:17:12.25#ibcon#about to read 4, iclass 30, count 0 2006.201.19:17:12.25#ibcon#read 4, iclass 30, count 0 2006.201.19:17:12.25#ibcon#about to read 5, iclass 30, count 0 2006.201.19:17:12.25#ibcon#read 5, iclass 30, count 0 2006.201.19:17:12.25#ibcon#about to read 6, iclass 30, count 0 2006.201.19:17:12.25#ibcon#read 6, iclass 30, count 0 2006.201.19:17:12.25#ibcon#end of sib2, iclass 30, count 0 2006.201.19:17:12.25#ibcon#*after write, iclass 30, count 0 2006.201.19:17:12.25#ibcon#*before return 0, iclass 30, count 0 2006.201.19:17:12.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:12.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:17:12.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:17:12.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:17:12.25$vck44/vbbw=wide 2006.201.19:17:12.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.19:17:12.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.19:17:12.25#ibcon#ireg 8 cls_cnt 0 2006.201.19:17:12.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:17:12.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:17:12.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:17:12.32#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:17:12.32#ibcon#first serial, iclass 32, count 0 2006.201.19:17:12.32#ibcon#enter sib2, iclass 32, count 0 2006.201.19:17:12.32#ibcon#flushed, iclass 32, count 0 2006.201.19:17:12.32#ibcon#about to write, iclass 32, count 0 2006.201.19:17:12.32#ibcon#wrote, iclass 32, count 0 2006.201.19:17:12.32#ibcon#about to read 3, iclass 32, count 0 2006.201.19:17:12.34#ibcon#read 3, iclass 32, count 0 2006.201.19:17:12.34#ibcon#about to read 4, iclass 32, count 0 2006.201.19:17:12.34#ibcon#read 4, iclass 32, count 0 2006.201.19:17:12.34#ibcon#about to read 5, iclass 32, count 0 2006.201.19:17:12.34#ibcon#read 5, iclass 32, count 0 2006.201.19:17:12.34#ibcon#about to read 6, iclass 32, count 0 2006.201.19:17:12.34#ibcon#read 6, iclass 32, count 0 2006.201.19:17:12.34#ibcon#end of sib2, iclass 32, count 0 2006.201.19:17:12.34#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:17:12.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:17:12.34#ibcon#[27=BW32\r\n] 2006.201.19:17:12.34#ibcon#*before write, iclass 32, count 0 2006.201.19:17:12.34#ibcon#enter sib2, iclass 32, count 0 2006.201.19:17:12.34#ibcon#flushed, iclass 32, count 0 2006.201.19:17:12.34#ibcon#about to write, iclass 32, count 0 2006.201.19:17:12.34#ibcon#wrote, iclass 32, count 0 2006.201.19:17:12.34#ibcon#about to read 3, iclass 32, count 0 2006.201.19:17:12.37#ibcon#read 3, iclass 32, count 0 2006.201.19:17:12.37#ibcon#about to read 4, iclass 32, count 0 2006.201.19:17:12.37#ibcon#read 4, iclass 32, count 0 2006.201.19:17:12.37#ibcon#about to read 5, iclass 32, count 0 2006.201.19:17:12.37#ibcon#read 5, iclass 32, count 0 2006.201.19:17:12.37#ibcon#about to read 6, iclass 32, count 0 2006.201.19:17:12.37#ibcon#read 6, iclass 32, count 0 2006.201.19:17:12.37#ibcon#end of sib2, iclass 32, count 0 2006.201.19:17:12.37#ibcon#*after write, iclass 32, count 0 2006.201.19:17:12.37#ibcon#*before return 0, iclass 32, count 0 2006.201.19:17:12.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:17:12.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:17:12.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:17:12.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:17:12.37$setupk4/ifdk4 2006.201.19:17:12.37$ifdk4/lo= 2006.201.19:17:12.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:17:12.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:17:12.37$ifdk4/patch= 2006.201.19:17:12.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:17:12.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:17:12.37$setupk4/!*+20s 2006.201.19:17:14.50#abcon#<5=/03 0.9 2.4 20.491001002.4\r\n> 2006.201.19:17:14.52#abcon#{5=INTERFACE CLEAR} 2006.201.19:17:14.58#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:17:21.14#trakl#Source acquired 2006.201.19:17:23.14#flagr#flagr/antenna,acquired 2006.201.19:17:24.67#abcon#<5=/03 0.9 2.5 20.491001002.4\r\n> 2006.201.19:17:24.69#abcon#{5=INTERFACE CLEAR} 2006.201.19:17:24.75#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:17:26.85$setupk4/"tpicd 2006.201.19:17:26.85$setupk4/echo=off 2006.201.19:17:26.85$setupk4/xlog=off 2006.201.19:17:26.85:!2006.201.19:17:34 2006.201.19:17:34.00:preob 2006.201.19:17:34.13/onsource/TRACKING 2006.201.19:17:34.13:!2006.201.19:17:44 2006.201.19:17:44.00:"tape 2006.201.19:17:44.00:"st=record 2006.201.19:17:44.00:data_valid=on 2006.201.19:17:44.00:midob 2006.201.19:17:45.13/onsource/TRACKING 2006.201.19:17:45.13/wx/20.49,1002.4,100 2006.201.19:17:45.20/cable/+6.4796E-03 2006.201.19:17:46.29/va/01,08,usb,yes,54,57 2006.201.19:17:46.29/va/02,07,usb,yes,58,59 2006.201.19:17:46.29/va/03,08,usb,yes,53,55 2006.201.19:17:46.29/va/04,07,usb,yes,60,63 2006.201.19:17:46.29/va/05,04,usb,yes,53,55 2006.201.19:17:46.29/va/06,05,usb,yes,54,54 2006.201.19:17:46.29/va/07,05,usb,yes,53,54 2006.201.19:17:46.29/va/08,04,usb,yes,52,61 2006.201.19:17:46.52/valo/01,524.99,yes,locked 2006.201.19:17:46.52/valo/02,534.99,yes,locked 2006.201.19:17:46.52/valo/03,564.99,yes,locked 2006.201.19:17:46.52/valo/04,624.99,yes,locked 2006.201.19:17:46.52/valo/05,734.99,yes,locked 2006.201.19:17:46.52/valo/06,814.99,yes,locked 2006.201.19:17:46.52/valo/07,864.99,yes,locked 2006.201.19:17:46.52/valo/08,884.99,yes,locked 2006.201.19:17:47.61/vb/01,04,usb,yes,32,29 2006.201.19:17:47.61/vb/02,05,usb,yes,30,30 2006.201.19:17:47.61/vb/03,04,usb,yes,31,34 2006.201.19:17:47.61/vb/04,05,usb,yes,32,30 2006.201.19:17:47.61/vb/05,04,usb,yes,28,31 2006.201.19:17:47.61/vb/06,04,usb,yes,33,29 2006.201.19:17:47.61/vb/07,04,usb,yes,32,32 2006.201.19:17:47.61/vb/08,04,usb,yes,30,33 2006.201.19:17:47.84/vblo/01,629.99,yes,locked 2006.201.19:17:47.84/vblo/02,634.99,yes,locked 2006.201.19:17:47.84/vblo/03,649.99,yes,locked 2006.201.19:17:47.84/vblo/04,679.99,yes,locked 2006.201.19:17:47.84/vblo/05,709.99,yes,locked 2006.201.19:17:47.84/vblo/06,719.99,yes,locked 2006.201.19:17:47.84/vblo/07,734.99,yes,locked 2006.201.19:17:47.84/vblo/08,744.99,yes,locked 2006.201.19:17:47.99/vabw/8 2006.201.19:17:48.14/vbbw/8 2006.201.19:17:48.23/xfe/off,on,16.5 2006.201.19:17:48.61/ifatt/23,28,28,28 2006.201.19:17:49.06/fmout-gps/S +4.50E-07 2006.201.19:17:49.13:!2006.201.19:20:44 2006.201.19:20:44.00:data_valid=off 2006.201.19:20:44.00:"et 2006.201.19:20:44.00:!+3s 2006.201.19:20:47.02:"tape 2006.201.19:20:47.02:postob 2006.201.19:20:47.14/cable/+6.4778E-03 2006.201.19:20:47.14/wx/20.49,1002.5,100 2006.201.19:20:47.21/fmout-gps/S +4.50E-07 2006.201.19:20:47.21:scan_name=201-1923,jd0607,120 2006.201.19:20:47.21:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.201.19:20:48.14#flagr#flagr/antenna,new-source 2006.201.19:20:48.14:checkk5 2006.201.19:20:48.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:20:48.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:20:49.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:20:49.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:20:50.03/chk_obsdata//k5ts1/T2011917??a.dat file size is correct (nominal:720MB, actual:716MB). 2006.201.19:20:50.40/chk_obsdata//k5ts2/T2011917??b.dat file size is correct (nominal:720MB, actual:716MB). 2006.201.19:20:50.77/chk_obsdata//k5ts3/T2011917??c.dat file size is correct (nominal:720MB, actual:716MB). 2006.201.19:20:51.14/chk_obsdata//k5ts4/T2011917??d.dat file size is correct (nominal:720MB, actual:716MB). 2006.201.19:20:51.82/k5log//k5ts1_log_newline 2006.201.19:20:52.51/k5log//k5ts2_log_newline 2006.201.19:20:53.21/k5log//k5ts3_log_newline 2006.201.19:20:53.89/k5log//k5ts4_log_newline 2006.201.19:20:53.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:20:53.92:setupk4=1 2006.201.19:20:53.92$setupk4/echo=on 2006.201.19:20:53.92$setupk4/pcalon 2006.201.19:20:53.92$pcalon/"no phase cal control is implemented here 2006.201.19:20:53.92$setupk4/"tpicd=stop 2006.201.19:20:53.92$setupk4/"rec=synch_on 2006.201.19:20:53.92$setupk4/"rec_mode=128 2006.201.19:20:53.92$setupk4/!* 2006.201.19:20:53.92$setupk4/recpk4 2006.201.19:20:53.92$recpk4/recpatch= 2006.201.19:20:53.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:20:53.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:20:53.92$setupk4/vck44 2006.201.19:20:53.92$vck44/valo=1,524.99 2006.201.19:20:53.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.19:20:53.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.19:20:53.92#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:53.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:53.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:53.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:53.92#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:20:53.92#ibcon#first serial, iclass 17, count 0 2006.201.19:20:53.92#ibcon#enter sib2, iclass 17, count 0 2006.201.19:20:53.92#ibcon#flushed, iclass 17, count 0 2006.201.19:20:53.92#ibcon#about to write, iclass 17, count 0 2006.201.19:20:53.92#ibcon#wrote, iclass 17, count 0 2006.201.19:20:53.92#ibcon#about to read 3, iclass 17, count 0 2006.201.19:20:53.94#ibcon#read 3, iclass 17, count 0 2006.201.19:20:53.94#ibcon#about to read 4, iclass 17, count 0 2006.201.19:20:53.94#ibcon#read 4, iclass 17, count 0 2006.201.19:20:53.94#ibcon#about to read 5, iclass 17, count 0 2006.201.19:20:53.94#ibcon#read 5, iclass 17, count 0 2006.201.19:20:53.94#ibcon#about to read 6, iclass 17, count 0 2006.201.19:20:53.94#ibcon#read 6, iclass 17, count 0 2006.201.19:20:53.94#ibcon#end of sib2, iclass 17, count 0 2006.201.19:20:53.94#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:20:53.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:20:53.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:20:53.94#ibcon#*before write, iclass 17, count 0 2006.201.19:20:53.94#ibcon#enter sib2, iclass 17, count 0 2006.201.19:20:53.94#ibcon#flushed, iclass 17, count 0 2006.201.19:20:53.94#ibcon#about to write, iclass 17, count 0 2006.201.19:20:53.94#ibcon#wrote, iclass 17, count 0 2006.201.19:20:53.94#ibcon#about to read 3, iclass 17, count 0 2006.201.19:20:53.99#ibcon#read 3, iclass 17, count 0 2006.201.19:20:53.99#ibcon#about to read 4, iclass 17, count 0 2006.201.19:20:53.99#ibcon#read 4, iclass 17, count 0 2006.201.19:20:53.99#ibcon#about to read 5, iclass 17, count 0 2006.201.19:20:53.99#ibcon#read 5, iclass 17, count 0 2006.201.19:20:53.99#ibcon#about to read 6, iclass 17, count 0 2006.201.19:20:53.99#ibcon#read 6, iclass 17, count 0 2006.201.19:20:53.99#ibcon#end of sib2, iclass 17, count 0 2006.201.19:20:53.99#ibcon#*after write, iclass 17, count 0 2006.201.19:20:53.99#ibcon#*before return 0, iclass 17, count 0 2006.201.19:20:53.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:53.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:53.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:20:53.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:20:53.99$vck44/va=1,8 2006.201.19:20:53.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.19:20:53.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.19:20:53.99#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:53.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:53.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:53.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:53.99#ibcon#enter wrdev, iclass 19, count 2 2006.201.19:20:53.99#ibcon#first serial, iclass 19, count 2 2006.201.19:20:53.99#ibcon#enter sib2, iclass 19, count 2 2006.201.19:20:53.99#ibcon#flushed, iclass 19, count 2 2006.201.19:20:53.99#ibcon#about to write, iclass 19, count 2 2006.201.19:20:53.99#ibcon#wrote, iclass 19, count 2 2006.201.19:20:53.99#ibcon#about to read 3, iclass 19, count 2 2006.201.19:20:54.01#ibcon#read 3, iclass 19, count 2 2006.201.19:20:54.01#ibcon#about to read 4, iclass 19, count 2 2006.201.19:20:54.01#ibcon#read 4, iclass 19, count 2 2006.201.19:20:54.01#ibcon#about to read 5, iclass 19, count 2 2006.201.19:20:54.01#ibcon#read 5, iclass 19, count 2 2006.201.19:20:54.01#ibcon#about to read 6, iclass 19, count 2 2006.201.19:20:54.01#ibcon#read 6, iclass 19, count 2 2006.201.19:20:54.01#ibcon#end of sib2, iclass 19, count 2 2006.201.19:20:54.01#ibcon#*mode == 0, iclass 19, count 2 2006.201.19:20:54.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.19:20:54.01#ibcon#[25=AT01-08\r\n] 2006.201.19:20:54.01#ibcon#*before write, iclass 19, count 2 2006.201.19:20:54.01#ibcon#enter sib2, iclass 19, count 2 2006.201.19:20:54.01#ibcon#flushed, iclass 19, count 2 2006.201.19:20:54.01#ibcon#about to write, iclass 19, count 2 2006.201.19:20:54.01#ibcon#wrote, iclass 19, count 2 2006.201.19:20:54.01#ibcon#about to read 3, iclass 19, count 2 2006.201.19:20:54.04#ibcon#read 3, iclass 19, count 2 2006.201.19:20:54.04#ibcon#about to read 4, iclass 19, count 2 2006.201.19:20:54.04#ibcon#read 4, iclass 19, count 2 2006.201.19:20:54.04#ibcon#about to read 5, iclass 19, count 2 2006.201.19:20:54.04#ibcon#read 5, iclass 19, count 2 2006.201.19:20:54.04#ibcon#about to read 6, iclass 19, count 2 2006.201.19:20:54.04#ibcon#read 6, iclass 19, count 2 2006.201.19:20:54.04#ibcon#end of sib2, iclass 19, count 2 2006.201.19:20:54.04#ibcon#*after write, iclass 19, count 2 2006.201.19:20:54.04#ibcon#*before return 0, iclass 19, count 2 2006.201.19:20:54.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:54.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:54.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.19:20:54.04#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:54.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:54.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:54.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:54.16#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:20:54.16#ibcon#first serial, iclass 19, count 0 2006.201.19:20:54.16#ibcon#enter sib2, iclass 19, count 0 2006.201.19:20:54.16#ibcon#flushed, iclass 19, count 0 2006.201.19:20:54.16#ibcon#about to write, iclass 19, count 0 2006.201.19:20:54.16#ibcon#wrote, iclass 19, count 0 2006.201.19:20:54.16#ibcon#about to read 3, iclass 19, count 0 2006.201.19:20:54.18#ibcon#read 3, iclass 19, count 0 2006.201.19:20:54.18#ibcon#about to read 4, iclass 19, count 0 2006.201.19:20:54.18#ibcon#read 4, iclass 19, count 0 2006.201.19:20:54.18#ibcon#about to read 5, iclass 19, count 0 2006.201.19:20:54.18#ibcon#read 5, iclass 19, count 0 2006.201.19:20:54.18#ibcon#about to read 6, iclass 19, count 0 2006.201.19:20:54.18#ibcon#read 6, iclass 19, count 0 2006.201.19:20:54.18#ibcon#end of sib2, iclass 19, count 0 2006.201.19:20:54.18#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:20:54.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:20:54.18#ibcon#[25=USB\r\n] 2006.201.19:20:54.18#ibcon#*before write, iclass 19, count 0 2006.201.19:20:54.18#ibcon#enter sib2, iclass 19, count 0 2006.201.19:20:54.18#ibcon#flushed, iclass 19, count 0 2006.201.19:20:54.18#ibcon#about to write, iclass 19, count 0 2006.201.19:20:54.18#ibcon#wrote, iclass 19, count 0 2006.201.19:20:54.18#ibcon#about to read 3, iclass 19, count 0 2006.201.19:20:54.21#ibcon#read 3, iclass 19, count 0 2006.201.19:20:54.21#ibcon#about to read 4, iclass 19, count 0 2006.201.19:20:54.21#ibcon#read 4, iclass 19, count 0 2006.201.19:20:54.21#ibcon#about to read 5, iclass 19, count 0 2006.201.19:20:54.21#ibcon#read 5, iclass 19, count 0 2006.201.19:20:54.21#ibcon#about to read 6, iclass 19, count 0 2006.201.19:20:54.21#ibcon#read 6, iclass 19, count 0 2006.201.19:20:54.21#ibcon#end of sib2, iclass 19, count 0 2006.201.19:20:54.21#ibcon#*after write, iclass 19, count 0 2006.201.19:20:54.21#ibcon#*before return 0, iclass 19, count 0 2006.201.19:20:54.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:54.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:54.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:20:54.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:20:54.21$vck44/valo=2,534.99 2006.201.19:20:54.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.19:20:54.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.19:20:54.21#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:54.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:54.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:54.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:54.21#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:20:54.21#ibcon#first serial, iclass 21, count 0 2006.201.19:20:54.21#ibcon#enter sib2, iclass 21, count 0 2006.201.19:20:54.21#ibcon#flushed, iclass 21, count 0 2006.201.19:20:54.21#ibcon#about to write, iclass 21, count 0 2006.201.19:20:54.21#ibcon#wrote, iclass 21, count 0 2006.201.19:20:54.21#ibcon#about to read 3, iclass 21, count 0 2006.201.19:20:54.23#ibcon#read 3, iclass 21, count 0 2006.201.19:20:54.23#ibcon#about to read 4, iclass 21, count 0 2006.201.19:20:54.23#ibcon#read 4, iclass 21, count 0 2006.201.19:20:54.23#ibcon#about to read 5, iclass 21, count 0 2006.201.19:20:54.23#ibcon#read 5, iclass 21, count 0 2006.201.19:20:54.23#ibcon#about to read 6, iclass 21, count 0 2006.201.19:20:54.23#ibcon#read 6, iclass 21, count 0 2006.201.19:20:54.23#ibcon#end of sib2, iclass 21, count 0 2006.201.19:20:54.23#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:20:54.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:20:54.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:20:54.23#ibcon#*before write, iclass 21, count 0 2006.201.19:20:54.23#ibcon#enter sib2, iclass 21, count 0 2006.201.19:20:54.23#ibcon#flushed, iclass 21, count 0 2006.201.19:20:54.23#ibcon#about to write, iclass 21, count 0 2006.201.19:20:54.23#ibcon#wrote, iclass 21, count 0 2006.201.19:20:54.23#ibcon#about to read 3, iclass 21, count 0 2006.201.19:20:54.27#ibcon#read 3, iclass 21, count 0 2006.201.19:20:54.27#ibcon#about to read 4, iclass 21, count 0 2006.201.19:20:54.27#ibcon#read 4, iclass 21, count 0 2006.201.19:20:54.27#ibcon#about to read 5, iclass 21, count 0 2006.201.19:20:54.27#ibcon#read 5, iclass 21, count 0 2006.201.19:20:54.27#ibcon#about to read 6, iclass 21, count 0 2006.201.19:20:54.27#ibcon#read 6, iclass 21, count 0 2006.201.19:20:54.27#ibcon#end of sib2, iclass 21, count 0 2006.201.19:20:54.27#ibcon#*after write, iclass 21, count 0 2006.201.19:20:54.27#ibcon#*before return 0, iclass 21, count 0 2006.201.19:20:54.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:54.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:54.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:20:54.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:20:54.27$vck44/va=2,7 2006.201.19:20:54.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.19:20:54.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.19:20:54.27#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:54.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:54.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:54.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:54.33#ibcon#enter wrdev, iclass 23, count 2 2006.201.19:20:54.33#ibcon#first serial, iclass 23, count 2 2006.201.19:20:54.33#ibcon#enter sib2, iclass 23, count 2 2006.201.19:20:54.33#ibcon#flushed, iclass 23, count 2 2006.201.19:20:54.33#ibcon#about to write, iclass 23, count 2 2006.201.19:20:54.33#ibcon#wrote, iclass 23, count 2 2006.201.19:20:54.33#ibcon#about to read 3, iclass 23, count 2 2006.201.19:20:54.35#ibcon#read 3, iclass 23, count 2 2006.201.19:20:54.35#ibcon#about to read 4, iclass 23, count 2 2006.201.19:20:54.35#ibcon#read 4, iclass 23, count 2 2006.201.19:20:54.35#ibcon#about to read 5, iclass 23, count 2 2006.201.19:20:54.35#ibcon#read 5, iclass 23, count 2 2006.201.19:20:54.35#ibcon#about to read 6, iclass 23, count 2 2006.201.19:20:54.35#ibcon#read 6, iclass 23, count 2 2006.201.19:20:54.35#ibcon#end of sib2, iclass 23, count 2 2006.201.19:20:54.35#ibcon#*mode == 0, iclass 23, count 2 2006.201.19:20:54.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.19:20:54.35#ibcon#[25=AT02-07\r\n] 2006.201.19:20:54.35#ibcon#*before write, iclass 23, count 2 2006.201.19:20:54.35#ibcon#enter sib2, iclass 23, count 2 2006.201.19:20:54.35#ibcon#flushed, iclass 23, count 2 2006.201.19:20:54.35#ibcon#about to write, iclass 23, count 2 2006.201.19:20:54.35#ibcon#wrote, iclass 23, count 2 2006.201.19:20:54.35#ibcon#about to read 3, iclass 23, count 2 2006.201.19:20:54.38#ibcon#read 3, iclass 23, count 2 2006.201.19:20:54.38#ibcon#about to read 4, iclass 23, count 2 2006.201.19:20:54.38#ibcon#read 4, iclass 23, count 2 2006.201.19:20:54.38#ibcon#about to read 5, iclass 23, count 2 2006.201.19:20:54.38#ibcon#read 5, iclass 23, count 2 2006.201.19:20:54.38#ibcon#about to read 6, iclass 23, count 2 2006.201.19:20:54.38#ibcon#read 6, iclass 23, count 2 2006.201.19:20:54.38#ibcon#end of sib2, iclass 23, count 2 2006.201.19:20:54.38#ibcon#*after write, iclass 23, count 2 2006.201.19:20:54.38#ibcon#*before return 0, iclass 23, count 2 2006.201.19:20:54.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:54.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:54.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.19:20:54.38#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:54.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:54.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:54.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:54.50#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:20:54.50#ibcon#first serial, iclass 23, count 0 2006.201.19:20:54.50#ibcon#enter sib2, iclass 23, count 0 2006.201.19:20:54.50#ibcon#flushed, iclass 23, count 0 2006.201.19:20:54.50#ibcon#about to write, iclass 23, count 0 2006.201.19:20:54.50#ibcon#wrote, iclass 23, count 0 2006.201.19:20:54.50#ibcon#about to read 3, iclass 23, count 0 2006.201.19:20:54.52#ibcon#read 3, iclass 23, count 0 2006.201.19:20:54.52#ibcon#about to read 4, iclass 23, count 0 2006.201.19:20:54.52#ibcon#read 4, iclass 23, count 0 2006.201.19:20:54.52#ibcon#about to read 5, iclass 23, count 0 2006.201.19:20:54.52#ibcon#read 5, iclass 23, count 0 2006.201.19:20:54.52#ibcon#about to read 6, iclass 23, count 0 2006.201.19:20:54.52#ibcon#read 6, iclass 23, count 0 2006.201.19:20:54.52#ibcon#end of sib2, iclass 23, count 0 2006.201.19:20:54.52#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:20:54.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:20:54.52#ibcon#[25=USB\r\n] 2006.201.19:20:54.52#ibcon#*before write, iclass 23, count 0 2006.201.19:20:54.52#ibcon#enter sib2, iclass 23, count 0 2006.201.19:20:54.52#ibcon#flushed, iclass 23, count 0 2006.201.19:20:54.52#ibcon#about to write, iclass 23, count 0 2006.201.19:20:54.52#ibcon#wrote, iclass 23, count 0 2006.201.19:20:54.52#ibcon#about to read 3, iclass 23, count 0 2006.201.19:20:54.55#ibcon#read 3, iclass 23, count 0 2006.201.19:20:54.55#ibcon#about to read 4, iclass 23, count 0 2006.201.19:20:54.55#ibcon#read 4, iclass 23, count 0 2006.201.19:20:54.55#ibcon#about to read 5, iclass 23, count 0 2006.201.19:20:54.55#ibcon#read 5, iclass 23, count 0 2006.201.19:20:54.55#ibcon#about to read 6, iclass 23, count 0 2006.201.19:20:54.55#ibcon#read 6, iclass 23, count 0 2006.201.19:20:54.55#ibcon#end of sib2, iclass 23, count 0 2006.201.19:20:54.55#ibcon#*after write, iclass 23, count 0 2006.201.19:20:54.55#ibcon#*before return 0, iclass 23, count 0 2006.201.19:20:54.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:54.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:54.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:20:54.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:20:54.55$vck44/valo=3,564.99 2006.201.19:20:54.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.19:20:54.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.19:20:54.55#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:54.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:54.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:54.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:54.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:20:54.55#ibcon#first serial, iclass 25, count 0 2006.201.19:20:54.55#ibcon#enter sib2, iclass 25, count 0 2006.201.19:20:54.55#ibcon#flushed, iclass 25, count 0 2006.201.19:20:54.55#ibcon#about to write, iclass 25, count 0 2006.201.19:20:54.55#ibcon#wrote, iclass 25, count 0 2006.201.19:20:54.55#ibcon#about to read 3, iclass 25, count 0 2006.201.19:20:54.57#ibcon#read 3, iclass 25, count 0 2006.201.19:20:54.57#ibcon#about to read 4, iclass 25, count 0 2006.201.19:20:54.57#ibcon#read 4, iclass 25, count 0 2006.201.19:20:54.57#ibcon#about to read 5, iclass 25, count 0 2006.201.19:20:54.57#ibcon#read 5, iclass 25, count 0 2006.201.19:20:54.57#ibcon#about to read 6, iclass 25, count 0 2006.201.19:20:54.57#ibcon#read 6, iclass 25, count 0 2006.201.19:20:54.57#ibcon#end of sib2, iclass 25, count 0 2006.201.19:20:54.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:20:54.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:20:54.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:20:54.57#ibcon#*before write, iclass 25, count 0 2006.201.19:20:54.57#ibcon#enter sib2, iclass 25, count 0 2006.201.19:20:54.57#ibcon#flushed, iclass 25, count 0 2006.201.19:20:54.57#ibcon#about to write, iclass 25, count 0 2006.201.19:20:54.57#ibcon#wrote, iclass 25, count 0 2006.201.19:20:54.57#ibcon#about to read 3, iclass 25, count 0 2006.201.19:20:54.62#ibcon#read 3, iclass 25, count 0 2006.201.19:20:54.62#ibcon#about to read 4, iclass 25, count 0 2006.201.19:20:54.62#ibcon#read 4, iclass 25, count 0 2006.201.19:20:54.62#ibcon#about to read 5, iclass 25, count 0 2006.201.19:20:54.62#ibcon#read 5, iclass 25, count 0 2006.201.19:20:54.62#ibcon#about to read 6, iclass 25, count 0 2006.201.19:20:54.62#ibcon#read 6, iclass 25, count 0 2006.201.19:20:54.62#ibcon#end of sib2, iclass 25, count 0 2006.201.19:20:54.62#ibcon#*after write, iclass 25, count 0 2006.201.19:20:54.62#ibcon#*before return 0, iclass 25, count 0 2006.201.19:20:54.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:54.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:54.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:20:54.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:20:54.62$vck44/va=3,8 2006.201.19:20:54.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.19:20:54.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.19:20:54.62#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:54.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:54.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:54.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:54.67#ibcon#enter wrdev, iclass 27, count 2 2006.201.19:20:54.67#ibcon#first serial, iclass 27, count 2 2006.201.19:20:54.67#ibcon#enter sib2, iclass 27, count 2 2006.201.19:20:54.67#ibcon#flushed, iclass 27, count 2 2006.201.19:20:54.67#ibcon#about to write, iclass 27, count 2 2006.201.19:20:54.67#ibcon#wrote, iclass 27, count 2 2006.201.19:20:54.67#ibcon#about to read 3, iclass 27, count 2 2006.201.19:20:54.69#ibcon#read 3, iclass 27, count 2 2006.201.19:20:54.69#ibcon#about to read 4, iclass 27, count 2 2006.201.19:20:54.69#ibcon#read 4, iclass 27, count 2 2006.201.19:20:54.69#ibcon#about to read 5, iclass 27, count 2 2006.201.19:20:54.69#ibcon#read 5, iclass 27, count 2 2006.201.19:20:54.69#ibcon#about to read 6, iclass 27, count 2 2006.201.19:20:54.69#ibcon#read 6, iclass 27, count 2 2006.201.19:20:54.69#ibcon#end of sib2, iclass 27, count 2 2006.201.19:20:54.69#ibcon#*mode == 0, iclass 27, count 2 2006.201.19:20:54.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.19:20:54.69#ibcon#[25=AT03-08\r\n] 2006.201.19:20:54.69#ibcon#*before write, iclass 27, count 2 2006.201.19:20:54.69#ibcon#enter sib2, iclass 27, count 2 2006.201.19:20:54.69#ibcon#flushed, iclass 27, count 2 2006.201.19:20:54.69#ibcon#about to write, iclass 27, count 2 2006.201.19:20:54.69#ibcon#wrote, iclass 27, count 2 2006.201.19:20:54.69#ibcon#about to read 3, iclass 27, count 2 2006.201.19:20:54.72#ibcon#read 3, iclass 27, count 2 2006.201.19:20:54.72#ibcon#about to read 4, iclass 27, count 2 2006.201.19:20:54.72#ibcon#read 4, iclass 27, count 2 2006.201.19:20:54.72#ibcon#about to read 5, iclass 27, count 2 2006.201.19:20:54.72#ibcon#read 5, iclass 27, count 2 2006.201.19:20:54.72#ibcon#about to read 6, iclass 27, count 2 2006.201.19:20:54.72#ibcon#read 6, iclass 27, count 2 2006.201.19:20:54.72#ibcon#end of sib2, iclass 27, count 2 2006.201.19:20:54.72#ibcon#*after write, iclass 27, count 2 2006.201.19:20:54.72#ibcon#*before return 0, iclass 27, count 2 2006.201.19:20:54.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:54.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:54.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.19:20:54.72#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:54.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:54.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:54.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:54.84#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:20:54.84#ibcon#first serial, iclass 27, count 0 2006.201.19:20:54.84#ibcon#enter sib2, iclass 27, count 0 2006.201.19:20:54.84#ibcon#flushed, iclass 27, count 0 2006.201.19:20:54.84#ibcon#about to write, iclass 27, count 0 2006.201.19:20:54.84#ibcon#wrote, iclass 27, count 0 2006.201.19:20:54.84#ibcon#about to read 3, iclass 27, count 0 2006.201.19:20:54.86#ibcon#read 3, iclass 27, count 0 2006.201.19:20:54.86#ibcon#about to read 4, iclass 27, count 0 2006.201.19:20:54.86#ibcon#read 4, iclass 27, count 0 2006.201.19:20:54.86#ibcon#about to read 5, iclass 27, count 0 2006.201.19:20:54.86#ibcon#read 5, iclass 27, count 0 2006.201.19:20:54.86#ibcon#about to read 6, iclass 27, count 0 2006.201.19:20:54.86#ibcon#read 6, iclass 27, count 0 2006.201.19:20:54.86#ibcon#end of sib2, iclass 27, count 0 2006.201.19:20:54.86#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:20:54.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:20:54.86#ibcon#[25=USB\r\n] 2006.201.19:20:54.86#ibcon#*before write, iclass 27, count 0 2006.201.19:20:54.86#ibcon#enter sib2, iclass 27, count 0 2006.201.19:20:54.86#ibcon#flushed, iclass 27, count 0 2006.201.19:20:54.86#ibcon#about to write, iclass 27, count 0 2006.201.19:20:54.86#ibcon#wrote, iclass 27, count 0 2006.201.19:20:54.86#ibcon#about to read 3, iclass 27, count 0 2006.201.19:20:54.89#ibcon#read 3, iclass 27, count 0 2006.201.19:20:54.89#ibcon#about to read 4, iclass 27, count 0 2006.201.19:20:54.89#ibcon#read 4, iclass 27, count 0 2006.201.19:20:54.89#ibcon#about to read 5, iclass 27, count 0 2006.201.19:20:54.89#ibcon#read 5, iclass 27, count 0 2006.201.19:20:54.89#ibcon#about to read 6, iclass 27, count 0 2006.201.19:20:54.89#ibcon#read 6, iclass 27, count 0 2006.201.19:20:54.89#ibcon#end of sib2, iclass 27, count 0 2006.201.19:20:54.89#ibcon#*after write, iclass 27, count 0 2006.201.19:20:54.89#ibcon#*before return 0, iclass 27, count 0 2006.201.19:20:54.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:54.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:54.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:20:54.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:20:54.89$vck44/valo=4,624.99 2006.201.19:20:54.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.19:20:54.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.19:20:54.89#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:54.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:54.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:54.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:54.89#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:20:54.89#ibcon#first serial, iclass 29, count 0 2006.201.19:20:54.89#ibcon#enter sib2, iclass 29, count 0 2006.201.19:20:54.89#ibcon#flushed, iclass 29, count 0 2006.201.19:20:54.89#ibcon#about to write, iclass 29, count 0 2006.201.19:20:54.89#ibcon#wrote, iclass 29, count 0 2006.201.19:20:54.89#ibcon#about to read 3, iclass 29, count 0 2006.201.19:20:54.91#ibcon#read 3, iclass 29, count 0 2006.201.19:20:54.91#ibcon#about to read 4, iclass 29, count 0 2006.201.19:20:54.91#ibcon#read 4, iclass 29, count 0 2006.201.19:20:54.91#ibcon#about to read 5, iclass 29, count 0 2006.201.19:20:54.91#ibcon#read 5, iclass 29, count 0 2006.201.19:20:54.91#ibcon#about to read 6, iclass 29, count 0 2006.201.19:20:54.91#ibcon#read 6, iclass 29, count 0 2006.201.19:20:54.91#ibcon#end of sib2, iclass 29, count 0 2006.201.19:20:54.91#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:20:54.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:20:54.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:20:54.91#ibcon#*before write, iclass 29, count 0 2006.201.19:20:54.91#ibcon#enter sib2, iclass 29, count 0 2006.201.19:20:54.91#ibcon#flushed, iclass 29, count 0 2006.201.19:20:54.91#ibcon#about to write, iclass 29, count 0 2006.201.19:20:54.91#ibcon#wrote, iclass 29, count 0 2006.201.19:20:54.91#ibcon#about to read 3, iclass 29, count 0 2006.201.19:20:54.96#ibcon#read 3, iclass 29, count 0 2006.201.19:20:54.96#ibcon#about to read 4, iclass 29, count 0 2006.201.19:20:54.96#ibcon#read 4, iclass 29, count 0 2006.201.19:20:54.96#ibcon#about to read 5, iclass 29, count 0 2006.201.19:20:54.96#ibcon#read 5, iclass 29, count 0 2006.201.19:20:54.96#ibcon#about to read 6, iclass 29, count 0 2006.201.19:20:54.96#ibcon#read 6, iclass 29, count 0 2006.201.19:20:54.96#ibcon#end of sib2, iclass 29, count 0 2006.201.19:20:54.96#ibcon#*after write, iclass 29, count 0 2006.201.19:20:54.96#ibcon#*before return 0, iclass 29, count 0 2006.201.19:20:54.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:54.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:54.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:20:54.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:20:54.96$vck44/va=4,7 2006.201.19:20:54.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.19:20:54.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.19:20:54.96#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:54.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:55.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:55.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:55.01#ibcon#enter wrdev, iclass 31, count 2 2006.201.19:20:55.01#ibcon#first serial, iclass 31, count 2 2006.201.19:20:55.01#ibcon#enter sib2, iclass 31, count 2 2006.201.19:20:55.01#ibcon#flushed, iclass 31, count 2 2006.201.19:20:55.01#ibcon#about to write, iclass 31, count 2 2006.201.19:20:55.01#ibcon#wrote, iclass 31, count 2 2006.201.19:20:55.01#ibcon#about to read 3, iclass 31, count 2 2006.201.19:20:55.03#ibcon#read 3, iclass 31, count 2 2006.201.19:20:55.03#ibcon#about to read 4, iclass 31, count 2 2006.201.19:20:55.03#ibcon#read 4, iclass 31, count 2 2006.201.19:20:55.03#ibcon#about to read 5, iclass 31, count 2 2006.201.19:20:55.03#ibcon#read 5, iclass 31, count 2 2006.201.19:20:55.03#ibcon#about to read 6, iclass 31, count 2 2006.201.19:20:55.03#ibcon#read 6, iclass 31, count 2 2006.201.19:20:55.03#ibcon#end of sib2, iclass 31, count 2 2006.201.19:20:55.03#ibcon#*mode == 0, iclass 31, count 2 2006.201.19:20:55.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.19:20:55.03#ibcon#[25=AT04-07\r\n] 2006.201.19:20:55.03#ibcon#*before write, iclass 31, count 2 2006.201.19:20:55.03#ibcon#enter sib2, iclass 31, count 2 2006.201.19:20:55.03#ibcon#flushed, iclass 31, count 2 2006.201.19:20:55.03#ibcon#about to write, iclass 31, count 2 2006.201.19:20:55.03#ibcon#wrote, iclass 31, count 2 2006.201.19:20:55.03#ibcon#about to read 3, iclass 31, count 2 2006.201.19:20:55.06#ibcon#read 3, iclass 31, count 2 2006.201.19:20:55.06#ibcon#about to read 4, iclass 31, count 2 2006.201.19:20:55.06#ibcon#read 4, iclass 31, count 2 2006.201.19:20:55.06#ibcon#about to read 5, iclass 31, count 2 2006.201.19:20:55.06#ibcon#read 5, iclass 31, count 2 2006.201.19:20:55.06#ibcon#about to read 6, iclass 31, count 2 2006.201.19:20:55.06#ibcon#read 6, iclass 31, count 2 2006.201.19:20:55.06#ibcon#end of sib2, iclass 31, count 2 2006.201.19:20:55.06#ibcon#*after write, iclass 31, count 2 2006.201.19:20:55.06#ibcon#*before return 0, iclass 31, count 2 2006.201.19:20:55.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:55.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:55.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.19:20:55.06#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:55.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:55.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:55.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:55.18#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:20:55.18#ibcon#first serial, iclass 31, count 0 2006.201.19:20:55.18#ibcon#enter sib2, iclass 31, count 0 2006.201.19:20:55.18#ibcon#flushed, iclass 31, count 0 2006.201.19:20:55.18#ibcon#about to write, iclass 31, count 0 2006.201.19:20:55.18#ibcon#wrote, iclass 31, count 0 2006.201.19:20:55.18#ibcon#about to read 3, iclass 31, count 0 2006.201.19:20:55.20#ibcon#read 3, iclass 31, count 0 2006.201.19:20:55.20#ibcon#about to read 4, iclass 31, count 0 2006.201.19:20:55.20#ibcon#read 4, iclass 31, count 0 2006.201.19:20:55.20#ibcon#about to read 5, iclass 31, count 0 2006.201.19:20:55.20#ibcon#read 5, iclass 31, count 0 2006.201.19:20:55.20#ibcon#about to read 6, iclass 31, count 0 2006.201.19:20:55.20#ibcon#read 6, iclass 31, count 0 2006.201.19:20:55.20#ibcon#end of sib2, iclass 31, count 0 2006.201.19:20:55.20#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:20:55.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:20:55.20#ibcon#[25=USB\r\n] 2006.201.19:20:55.20#ibcon#*before write, iclass 31, count 0 2006.201.19:20:55.20#ibcon#enter sib2, iclass 31, count 0 2006.201.19:20:55.20#ibcon#flushed, iclass 31, count 0 2006.201.19:20:55.20#ibcon#about to write, iclass 31, count 0 2006.201.19:20:55.20#ibcon#wrote, iclass 31, count 0 2006.201.19:20:55.20#ibcon#about to read 3, iclass 31, count 0 2006.201.19:20:55.23#ibcon#read 3, iclass 31, count 0 2006.201.19:20:55.23#ibcon#about to read 4, iclass 31, count 0 2006.201.19:20:55.23#ibcon#read 4, iclass 31, count 0 2006.201.19:20:55.23#ibcon#about to read 5, iclass 31, count 0 2006.201.19:20:55.23#ibcon#read 5, iclass 31, count 0 2006.201.19:20:55.23#ibcon#about to read 6, iclass 31, count 0 2006.201.19:20:55.23#ibcon#read 6, iclass 31, count 0 2006.201.19:20:55.23#ibcon#end of sib2, iclass 31, count 0 2006.201.19:20:55.23#ibcon#*after write, iclass 31, count 0 2006.201.19:20:55.23#ibcon#*before return 0, iclass 31, count 0 2006.201.19:20:55.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:55.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:55.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:20:55.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:20:55.23$vck44/valo=5,734.99 2006.201.19:20:55.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.19:20:55.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.19:20:55.23#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:55.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:55.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:55.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:55.23#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:20:55.23#ibcon#first serial, iclass 33, count 0 2006.201.19:20:55.23#ibcon#enter sib2, iclass 33, count 0 2006.201.19:20:55.23#ibcon#flushed, iclass 33, count 0 2006.201.19:20:55.23#ibcon#about to write, iclass 33, count 0 2006.201.19:20:55.23#ibcon#wrote, iclass 33, count 0 2006.201.19:20:55.23#ibcon#about to read 3, iclass 33, count 0 2006.201.19:20:55.25#ibcon#read 3, iclass 33, count 0 2006.201.19:20:55.25#ibcon#about to read 4, iclass 33, count 0 2006.201.19:20:55.25#ibcon#read 4, iclass 33, count 0 2006.201.19:20:55.25#ibcon#about to read 5, iclass 33, count 0 2006.201.19:20:55.25#ibcon#read 5, iclass 33, count 0 2006.201.19:20:55.25#ibcon#about to read 6, iclass 33, count 0 2006.201.19:20:55.25#ibcon#read 6, iclass 33, count 0 2006.201.19:20:55.25#ibcon#end of sib2, iclass 33, count 0 2006.201.19:20:55.25#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:20:55.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:20:55.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:20:55.25#ibcon#*before write, iclass 33, count 0 2006.201.19:20:55.25#ibcon#enter sib2, iclass 33, count 0 2006.201.19:20:55.25#ibcon#flushed, iclass 33, count 0 2006.201.19:20:55.25#ibcon#about to write, iclass 33, count 0 2006.201.19:20:55.25#ibcon#wrote, iclass 33, count 0 2006.201.19:20:55.25#ibcon#about to read 3, iclass 33, count 0 2006.201.19:20:55.29#ibcon#read 3, iclass 33, count 0 2006.201.19:20:55.29#ibcon#about to read 4, iclass 33, count 0 2006.201.19:20:55.29#ibcon#read 4, iclass 33, count 0 2006.201.19:20:55.29#ibcon#about to read 5, iclass 33, count 0 2006.201.19:20:55.29#ibcon#read 5, iclass 33, count 0 2006.201.19:20:55.29#ibcon#about to read 6, iclass 33, count 0 2006.201.19:20:55.29#ibcon#read 6, iclass 33, count 0 2006.201.19:20:55.29#ibcon#end of sib2, iclass 33, count 0 2006.201.19:20:55.29#ibcon#*after write, iclass 33, count 0 2006.201.19:20:55.29#ibcon#*before return 0, iclass 33, count 0 2006.201.19:20:55.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:55.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:55.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:20:55.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:20:55.29$vck44/va=5,4 2006.201.19:20:55.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.19:20:55.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.19:20:55.29#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:55.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:55.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:55.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:55.35#ibcon#enter wrdev, iclass 35, count 2 2006.201.19:20:55.35#ibcon#first serial, iclass 35, count 2 2006.201.19:20:55.35#ibcon#enter sib2, iclass 35, count 2 2006.201.19:20:55.35#ibcon#flushed, iclass 35, count 2 2006.201.19:20:55.35#ibcon#about to write, iclass 35, count 2 2006.201.19:20:55.35#ibcon#wrote, iclass 35, count 2 2006.201.19:20:55.35#ibcon#about to read 3, iclass 35, count 2 2006.201.19:20:55.37#ibcon#read 3, iclass 35, count 2 2006.201.19:20:55.37#ibcon#about to read 4, iclass 35, count 2 2006.201.19:20:55.37#ibcon#read 4, iclass 35, count 2 2006.201.19:20:55.37#ibcon#about to read 5, iclass 35, count 2 2006.201.19:20:55.37#ibcon#read 5, iclass 35, count 2 2006.201.19:20:55.37#ibcon#about to read 6, iclass 35, count 2 2006.201.19:20:55.37#ibcon#read 6, iclass 35, count 2 2006.201.19:20:55.37#ibcon#end of sib2, iclass 35, count 2 2006.201.19:20:55.37#ibcon#*mode == 0, iclass 35, count 2 2006.201.19:20:55.37#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.19:20:55.37#ibcon#[25=AT05-04\r\n] 2006.201.19:20:55.37#ibcon#*before write, iclass 35, count 2 2006.201.19:20:55.37#ibcon#enter sib2, iclass 35, count 2 2006.201.19:20:55.37#ibcon#flushed, iclass 35, count 2 2006.201.19:20:55.37#ibcon#about to write, iclass 35, count 2 2006.201.19:20:55.37#ibcon#wrote, iclass 35, count 2 2006.201.19:20:55.37#ibcon#about to read 3, iclass 35, count 2 2006.201.19:20:55.40#ibcon#read 3, iclass 35, count 2 2006.201.19:20:55.40#ibcon#about to read 4, iclass 35, count 2 2006.201.19:20:55.40#ibcon#read 4, iclass 35, count 2 2006.201.19:20:55.40#ibcon#about to read 5, iclass 35, count 2 2006.201.19:20:55.40#ibcon#read 5, iclass 35, count 2 2006.201.19:20:55.40#ibcon#about to read 6, iclass 35, count 2 2006.201.19:20:55.40#ibcon#read 6, iclass 35, count 2 2006.201.19:20:55.40#ibcon#end of sib2, iclass 35, count 2 2006.201.19:20:55.40#ibcon#*after write, iclass 35, count 2 2006.201.19:20:55.40#ibcon#*before return 0, iclass 35, count 2 2006.201.19:20:55.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:55.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:55.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.19:20:55.40#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:55.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:55.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:55.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:55.52#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:20:55.52#ibcon#first serial, iclass 35, count 0 2006.201.19:20:55.52#ibcon#enter sib2, iclass 35, count 0 2006.201.19:20:55.52#ibcon#flushed, iclass 35, count 0 2006.201.19:20:55.52#ibcon#about to write, iclass 35, count 0 2006.201.19:20:55.52#ibcon#wrote, iclass 35, count 0 2006.201.19:20:55.52#ibcon#about to read 3, iclass 35, count 0 2006.201.19:20:55.54#ibcon#read 3, iclass 35, count 0 2006.201.19:20:55.54#ibcon#about to read 4, iclass 35, count 0 2006.201.19:20:55.54#ibcon#read 4, iclass 35, count 0 2006.201.19:20:55.54#ibcon#about to read 5, iclass 35, count 0 2006.201.19:20:55.54#ibcon#read 5, iclass 35, count 0 2006.201.19:20:55.54#ibcon#about to read 6, iclass 35, count 0 2006.201.19:20:55.54#ibcon#read 6, iclass 35, count 0 2006.201.19:20:55.54#ibcon#end of sib2, iclass 35, count 0 2006.201.19:20:55.54#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:20:55.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:20:55.54#ibcon#[25=USB\r\n] 2006.201.19:20:55.54#ibcon#*before write, iclass 35, count 0 2006.201.19:20:55.54#ibcon#enter sib2, iclass 35, count 0 2006.201.19:20:55.54#ibcon#flushed, iclass 35, count 0 2006.201.19:20:55.54#ibcon#about to write, iclass 35, count 0 2006.201.19:20:55.54#ibcon#wrote, iclass 35, count 0 2006.201.19:20:55.54#ibcon#about to read 3, iclass 35, count 0 2006.201.19:20:55.57#ibcon#read 3, iclass 35, count 0 2006.201.19:20:55.57#ibcon#about to read 4, iclass 35, count 0 2006.201.19:20:55.57#ibcon#read 4, iclass 35, count 0 2006.201.19:20:55.57#ibcon#about to read 5, iclass 35, count 0 2006.201.19:20:55.57#ibcon#read 5, iclass 35, count 0 2006.201.19:20:55.57#ibcon#about to read 6, iclass 35, count 0 2006.201.19:20:55.57#ibcon#read 6, iclass 35, count 0 2006.201.19:20:55.57#ibcon#end of sib2, iclass 35, count 0 2006.201.19:20:55.57#ibcon#*after write, iclass 35, count 0 2006.201.19:20:55.57#ibcon#*before return 0, iclass 35, count 0 2006.201.19:20:55.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:55.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:55.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:20:55.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:20:55.57$vck44/valo=6,814.99 2006.201.19:20:55.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.19:20:55.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.19:20:55.57#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:55.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:20:55.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:20:55.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:20:55.57#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:20:55.57#ibcon#first serial, iclass 37, count 0 2006.201.19:20:55.57#ibcon#enter sib2, iclass 37, count 0 2006.201.19:20:55.57#ibcon#flushed, iclass 37, count 0 2006.201.19:20:55.57#ibcon#about to write, iclass 37, count 0 2006.201.19:20:55.57#ibcon#wrote, iclass 37, count 0 2006.201.19:20:55.57#ibcon#about to read 3, iclass 37, count 0 2006.201.19:20:55.59#ibcon#read 3, iclass 37, count 0 2006.201.19:20:55.59#ibcon#about to read 4, iclass 37, count 0 2006.201.19:20:55.59#ibcon#read 4, iclass 37, count 0 2006.201.19:20:55.59#ibcon#about to read 5, iclass 37, count 0 2006.201.19:20:55.59#ibcon#read 5, iclass 37, count 0 2006.201.19:20:55.59#ibcon#about to read 6, iclass 37, count 0 2006.201.19:20:55.59#ibcon#read 6, iclass 37, count 0 2006.201.19:20:55.59#ibcon#end of sib2, iclass 37, count 0 2006.201.19:20:55.59#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:20:55.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:20:55.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:20:55.59#ibcon#*before write, iclass 37, count 0 2006.201.19:20:55.59#ibcon#enter sib2, iclass 37, count 0 2006.201.19:20:55.59#ibcon#flushed, iclass 37, count 0 2006.201.19:20:55.59#ibcon#about to write, iclass 37, count 0 2006.201.19:20:55.59#ibcon#wrote, iclass 37, count 0 2006.201.19:20:55.59#ibcon#about to read 3, iclass 37, count 0 2006.201.19:20:55.63#ibcon#read 3, iclass 37, count 0 2006.201.19:20:55.63#ibcon#about to read 4, iclass 37, count 0 2006.201.19:20:55.63#ibcon#read 4, iclass 37, count 0 2006.201.19:20:55.63#ibcon#about to read 5, iclass 37, count 0 2006.201.19:20:55.63#ibcon#read 5, iclass 37, count 0 2006.201.19:20:55.63#ibcon#about to read 6, iclass 37, count 0 2006.201.19:20:55.63#ibcon#read 6, iclass 37, count 0 2006.201.19:20:55.63#ibcon#end of sib2, iclass 37, count 0 2006.201.19:20:55.63#ibcon#*after write, iclass 37, count 0 2006.201.19:20:55.63#ibcon#*before return 0, iclass 37, count 0 2006.201.19:20:55.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:20:55.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:20:55.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:20:55.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:20:55.63$vck44/va=6,5 2006.201.19:20:55.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.19:20:55.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.19:20:55.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:55.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:20:55.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:20:55.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:20:55.69#ibcon#enter wrdev, iclass 39, count 2 2006.201.19:20:55.69#ibcon#first serial, iclass 39, count 2 2006.201.19:20:55.69#ibcon#enter sib2, iclass 39, count 2 2006.201.19:20:55.69#ibcon#flushed, iclass 39, count 2 2006.201.19:20:55.69#ibcon#about to write, iclass 39, count 2 2006.201.19:20:55.69#ibcon#wrote, iclass 39, count 2 2006.201.19:20:55.69#ibcon#about to read 3, iclass 39, count 2 2006.201.19:20:55.71#ibcon#read 3, iclass 39, count 2 2006.201.19:20:55.71#ibcon#about to read 4, iclass 39, count 2 2006.201.19:20:55.71#ibcon#read 4, iclass 39, count 2 2006.201.19:20:55.71#ibcon#about to read 5, iclass 39, count 2 2006.201.19:20:55.71#ibcon#read 5, iclass 39, count 2 2006.201.19:20:55.71#ibcon#about to read 6, iclass 39, count 2 2006.201.19:20:55.71#ibcon#read 6, iclass 39, count 2 2006.201.19:20:55.71#ibcon#end of sib2, iclass 39, count 2 2006.201.19:20:55.71#ibcon#*mode == 0, iclass 39, count 2 2006.201.19:20:55.71#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.19:20:55.71#ibcon#[25=AT06-05\r\n] 2006.201.19:20:55.71#ibcon#*before write, iclass 39, count 2 2006.201.19:20:55.71#ibcon#enter sib2, iclass 39, count 2 2006.201.19:20:55.71#ibcon#flushed, iclass 39, count 2 2006.201.19:20:55.71#ibcon#about to write, iclass 39, count 2 2006.201.19:20:55.71#ibcon#wrote, iclass 39, count 2 2006.201.19:20:55.71#ibcon#about to read 3, iclass 39, count 2 2006.201.19:20:55.74#ibcon#read 3, iclass 39, count 2 2006.201.19:20:55.74#ibcon#about to read 4, iclass 39, count 2 2006.201.19:20:55.74#ibcon#read 4, iclass 39, count 2 2006.201.19:20:55.74#ibcon#about to read 5, iclass 39, count 2 2006.201.19:20:55.74#ibcon#read 5, iclass 39, count 2 2006.201.19:20:55.74#ibcon#about to read 6, iclass 39, count 2 2006.201.19:20:55.74#ibcon#read 6, iclass 39, count 2 2006.201.19:20:55.74#ibcon#end of sib2, iclass 39, count 2 2006.201.19:20:55.74#ibcon#*after write, iclass 39, count 2 2006.201.19:20:55.74#ibcon#*before return 0, iclass 39, count 2 2006.201.19:20:55.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:20:55.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:20:55.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.19:20:55.74#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:55.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:20:55.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:20:55.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:20:55.86#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:20:55.86#ibcon#first serial, iclass 39, count 0 2006.201.19:20:55.86#ibcon#enter sib2, iclass 39, count 0 2006.201.19:20:55.86#ibcon#flushed, iclass 39, count 0 2006.201.19:20:55.86#ibcon#about to write, iclass 39, count 0 2006.201.19:20:55.86#ibcon#wrote, iclass 39, count 0 2006.201.19:20:55.86#ibcon#about to read 3, iclass 39, count 0 2006.201.19:20:55.88#ibcon#read 3, iclass 39, count 0 2006.201.19:20:55.88#ibcon#about to read 4, iclass 39, count 0 2006.201.19:20:55.88#ibcon#read 4, iclass 39, count 0 2006.201.19:20:55.88#ibcon#about to read 5, iclass 39, count 0 2006.201.19:20:55.88#ibcon#read 5, iclass 39, count 0 2006.201.19:20:55.88#ibcon#about to read 6, iclass 39, count 0 2006.201.19:20:55.88#ibcon#read 6, iclass 39, count 0 2006.201.19:20:55.88#ibcon#end of sib2, iclass 39, count 0 2006.201.19:20:55.88#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:20:55.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:20:55.88#ibcon#[25=USB\r\n] 2006.201.19:20:55.88#ibcon#*before write, iclass 39, count 0 2006.201.19:20:55.88#ibcon#enter sib2, iclass 39, count 0 2006.201.19:20:55.88#ibcon#flushed, iclass 39, count 0 2006.201.19:20:55.88#ibcon#about to write, iclass 39, count 0 2006.201.19:20:55.88#ibcon#wrote, iclass 39, count 0 2006.201.19:20:55.88#ibcon#about to read 3, iclass 39, count 0 2006.201.19:20:55.91#ibcon#read 3, iclass 39, count 0 2006.201.19:20:55.91#ibcon#about to read 4, iclass 39, count 0 2006.201.19:20:55.91#ibcon#read 4, iclass 39, count 0 2006.201.19:20:55.91#ibcon#about to read 5, iclass 39, count 0 2006.201.19:20:55.91#ibcon#read 5, iclass 39, count 0 2006.201.19:20:55.91#ibcon#about to read 6, iclass 39, count 0 2006.201.19:20:55.91#ibcon#read 6, iclass 39, count 0 2006.201.19:20:55.91#ibcon#end of sib2, iclass 39, count 0 2006.201.19:20:55.91#ibcon#*after write, iclass 39, count 0 2006.201.19:20:55.91#ibcon#*before return 0, iclass 39, count 0 2006.201.19:20:55.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:20:55.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:20:55.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:20:55.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:20:55.91$vck44/valo=7,864.99 2006.201.19:20:55.91#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.19:20:55.91#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.19:20:55.91#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:55.91#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:55.91#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:55.91#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:55.91#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:20:55.91#ibcon#first serial, iclass 2, count 0 2006.201.19:20:55.91#ibcon#enter sib2, iclass 2, count 0 2006.201.19:20:55.91#ibcon#flushed, iclass 2, count 0 2006.201.19:20:55.91#ibcon#about to write, iclass 2, count 0 2006.201.19:20:55.91#ibcon#wrote, iclass 2, count 0 2006.201.19:20:55.91#ibcon#about to read 3, iclass 2, count 0 2006.201.19:20:55.93#ibcon#read 3, iclass 2, count 0 2006.201.19:20:55.93#ibcon#about to read 4, iclass 2, count 0 2006.201.19:20:55.93#ibcon#read 4, iclass 2, count 0 2006.201.19:20:55.93#ibcon#about to read 5, iclass 2, count 0 2006.201.19:20:55.93#ibcon#read 5, iclass 2, count 0 2006.201.19:20:55.93#ibcon#about to read 6, iclass 2, count 0 2006.201.19:20:55.93#ibcon#read 6, iclass 2, count 0 2006.201.19:20:55.93#ibcon#end of sib2, iclass 2, count 0 2006.201.19:20:55.93#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:20:55.93#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:20:55.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:20:55.93#ibcon#*before write, iclass 2, count 0 2006.201.19:20:55.93#ibcon#enter sib2, iclass 2, count 0 2006.201.19:20:55.93#ibcon#flushed, iclass 2, count 0 2006.201.19:20:55.93#ibcon#about to write, iclass 2, count 0 2006.201.19:20:55.93#ibcon#wrote, iclass 2, count 0 2006.201.19:20:55.93#ibcon#about to read 3, iclass 2, count 0 2006.201.19:20:55.97#ibcon#read 3, iclass 2, count 0 2006.201.19:20:55.97#ibcon#about to read 4, iclass 2, count 0 2006.201.19:20:55.97#ibcon#read 4, iclass 2, count 0 2006.201.19:20:55.97#ibcon#about to read 5, iclass 2, count 0 2006.201.19:20:55.97#ibcon#read 5, iclass 2, count 0 2006.201.19:20:55.97#ibcon#about to read 6, iclass 2, count 0 2006.201.19:20:55.97#ibcon#read 6, iclass 2, count 0 2006.201.19:20:55.97#ibcon#end of sib2, iclass 2, count 0 2006.201.19:20:55.97#ibcon#*after write, iclass 2, count 0 2006.201.19:20:55.97#ibcon#*before return 0, iclass 2, count 0 2006.201.19:20:55.97#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:55.97#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:55.97#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:20:55.97#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:20:55.97$vck44/va=7,5 2006.201.19:20:55.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.19:20:55.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.19:20:55.97#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:55.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:56.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:56.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:56.03#ibcon#enter wrdev, iclass 5, count 2 2006.201.19:20:56.03#ibcon#first serial, iclass 5, count 2 2006.201.19:20:56.03#ibcon#enter sib2, iclass 5, count 2 2006.201.19:20:56.03#ibcon#flushed, iclass 5, count 2 2006.201.19:20:56.03#ibcon#about to write, iclass 5, count 2 2006.201.19:20:56.03#ibcon#wrote, iclass 5, count 2 2006.201.19:20:56.03#ibcon#about to read 3, iclass 5, count 2 2006.201.19:20:56.05#ibcon#read 3, iclass 5, count 2 2006.201.19:20:56.05#ibcon#about to read 4, iclass 5, count 2 2006.201.19:20:56.05#ibcon#read 4, iclass 5, count 2 2006.201.19:20:56.05#ibcon#about to read 5, iclass 5, count 2 2006.201.19:20:56.05#ibcon#read 5, iclass 5, count 2 2006.201.19:20:56.05#ibcon#about to read 6, iclass 5, count 2 2006.201.19:20:56.05#ibcon#read 6, iclass 5, count 2 2006.201.19:20:56.05#ibcon#end of sib2, iclass 5, count 2 2006.201.19:20:56.05#ibcon#*mode == 0, iclass 5, count 2 2006.201.19:20:56.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.19:20:56.05#ibcon#[25=AT07-05\r\n] 2006.201.19:20:56.05#ibcon#*before write, iclass 5, count 2 2006.201.19:20:56.05#ibcon#enter sib2, iclass 5, count 2 2006.201.19:20:56.05#ibcon#flushed, iclass 5, count 2 2006.201.19:20:56.05#ibcon#about to write, iclass 5, count 2 2006.201.19:20:56.05#ibcon#wrote, iclass 5, count 2 2006.201.19:20:56.05#ibcon#about to read 3, iclass 5, count 2 2006.201.19:20:56.08#ibcon#read 3, iclass 5, count 2 2006.201.19:20:56.08#ibcon#about to read 4, iclass 5, count 2 2006.201.19:20:56.08#ibcon#read 4, iclass 5, count 2 2006.201.19:20:56.08#ibcon#about to read 5, iclass 5, count 2 2006.201.19:20:56.08#ibcon#read 5, iclass 5, count 2 2006.201.19:20:56.08#ibcon#about to read 6, iclass 5, count 2 2006.201.19:20:56.08#ibcon#read 6, iclass 5, count 2 2006.201.19:20:56.08#ibcon#end of sib2, iclass 5, count 2 2006.201.19:20:56.08#ibcon#*after write, iclass 5, count 2 2006.201.19:20:56.08#ibcon#*before return 0, iclass 5, count 2 2006.201.19:20:56.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:56.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:56.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.19:20:56.08#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:56.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:56.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:56.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:56.20#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:20:56.20#ibcon#first serial, iclass 5, count 0 2006.201.19:20:56.20#ibcon#enter sib2, iclass 5, count 0 2006.201.19:20:56.20#ibcon#flushed, iclass 5, count 0 2006.201.19:20:56.20#ibcon#about to write, iclass 5, count 0 2006.201.19:20:56.20#ibcon#wrote, iclass 5, count 0 2006.201.19:20:56.20#ibcon#about to read 3, iclass 5, count 0 2006.201.19:20:56.22#ibcon#read 3, iclass 5, count 0 2006.201.19:20:56.22#ibcon#about to read 4, iclass 5, count 0 2006.201.19:20:56.22#ibcon#read 4, iclass 5, count 0 2006.201.19:20:56.22#ibcon#about to read 5, iclass 5, count 0 2006.201.19:20:56.22#ibcon#read 5, iclass 5, count 0 2006.201.19:20:56.22#ibcon#about to read 6, iclass 5, count 0 2006.201.19:20:56.22#ibcon#read 6, iclass 5, count 0 2006.201.19:20:56.22#ibcon#end of sib2, iclass 5, count 0 2006.201.19:20:56.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:20:56.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:20:56.22#ibcon#[25=USB\r\n] 2006.201.19:20:56.22#ibcon#*before write, iclass 5, count 0 2006.201.19:20:56.22#ibcon#enter sib2, iclass 5, count 0 2006.201.19:20:56.22#ibcon#flushed, iclass 5, count 0 2006.201.19:20:56.22#ibcon#about to write, iclass 5, count 0 2006.201.19:20:56.22#ibcon#wrote, iclass 5, count 0 2006.201.19:20:56.22#ibcon#about to read 3, iclass 5, count 0 2006.201.19:20:56.25#ibcon#read 3, iclass 5, count 0 2006.201.19:20:56.25#ibcon#about to read 4, iclass 5, count 0 2006.201.19:20:56.25#ibcon#read 4, iclass 5, count 0 2006.201.19:20:56.25#ibcon#about to read 5, iclass 5, count 0 2006.201.19:20:56.25#ibcon#read 5, iclass 5, count 0 2006.201.19:20:56.25#ibcon#about to read 6, iclass 5, count 0 2006.201.19:20:56.25#ibcon#read 6, iclass 5, count 0 2006.201.19:20:56.25#ibcon#end of sib2, iclass 5, count 0 2006.201.19:20:56.25#ibcon#*after write, iclass 5, count 0 2006.201.19:20:56.25#ibcon#*before return 0, iclass 5, count 0 2006.201.19:20:56.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:56.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:56.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:20:56.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:20:56.25$vck44/valo=8,884.99 2006.201.19:20:56.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.19:20:56.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.19:20:56.25#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:56.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:56.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:56.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:56.25#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:20:56.25#ibcon#first serial, iclass 7, count 0 2006.201.19:20:56.25#ibcon#enter sib2, iclass 7, count 0 2006.201.19:20:56.25#ibcon#flushed, iclass 7, count 0 2006.201.19:20:56.25#ibcon#about to write, iclass 7, count 0 2006.201.19:20:56.25#ibcon#wrote, iclass 7, count 0 2006.201.19:20:56.25#ibcon#about to read 3, iclass 7, count 0 2006.201.19:20:56.27#ibcon#read 3, iclass 7, count 0 2006.201.19:20:56.27#ibcon#about to read 4, iclass 7, count 0 2006.201.19:20:56.27#ibcon#read 4, iclass 7, count 0 2006.201.19:20:56.27#ibcon#about to read 5, iclass 7, count 0 2006.201.19:20:56.27#ibcon#read 5, iclass 7, count 0 2006.201.19:20:56.27#ibcon#about to read 6, iclass 7, count 0 2006.201.19:20:56.27#ibcon#read 6, iclass 7, count 0 2006.201.19:20:56.27#ibcon#end of sib2, iclass 7, count 0 2006.201.19:20:56.27#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:20:56.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:20:56.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:20:56.27#ibcon#*before write, iclass 7, count 0 2006.201.19:20:56.27#ibcon#enter sib2, iclass 7, count 0 2006.201.19:20:56.27#ibcon#flushed, iclass 7, count 0 2006.201.19:20:56.27#ibcon#about to write, iclass 7, count 0 2006.201.19:20:56.27#ibcon#wrote, iclass 7, count 0 2006.201.19:20:56.27#ibcon#about to read 3, iclass 7, count 0 2006.201.19:20:56.31#ibcon#read 3, iclass 7, count 0 2006.201.19:20:56.31#ibcon#about to read 4, iclass 7, count 0 2006.201.19:20:56.31#ibcon#read 4, iclass 7, count 0 2006.201.19:20:56.31#ibcon#about to read 5, iclass 7, count 0 2006.201.19:20:56.31#ibcon#read 5, iclass 7, count 0 2006.201.19:20:56.31#ibcon#about to read 6, iclass 7, count 0 2006.201.19:20:56.31#ibcon#read 6, iclass 7, count 0 2006.201.19:20:56.31#ibcon#end of sib2, iclass 7, count 0 2006.201.19:20:56.31#ibcon#*after write, iclass 7, count 0 2006.201.19:20:56.31#ibcon#*before return 0, iclass 7, count 0 2006.201.19:20:56.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:56.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:56.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:20:56.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:20:56.31$vck44/va=8,4 2006.201.19:20:56.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.19:20:56.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.19:20:56.31#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:56.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:56.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:56.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:56.37#ibcon#enter wrdev, iclass 11, count 2 2006.201.19:20:56.37#ibcon#first serial, iclass 11, count 2 2006.201.19:20:56.37#ibcon#enter sib2, iclass 11, count 2 2006.201.19:20:56.37#ibcon#flushed, iclass 11, count 2 2006.201.19:20:56.37#ibcon#about to write, iclass 11, count 2 2006.201.19:20:56.37#ibcon#wrote, iclass 11, count 2 2006.201.19:20:56.37#ibcon#about to read 3, iclass 11, count 2 2006.201.19:20:56.39#ibcon#read 3, iclass 11, count 2 2006.201.19:20:56.39#ibcon#about to read 4, iclass 11, count 2 2006.201.19:20:56.39#ibcon#read 4, iclass 11, count 2 2006.201.19:20:56.39#ibcon#about to read 5, iclass 11, count 2 2006.201.19:20:56.39#ibcon#read 5, iclass 11, count 2 2006.201.19:20:56.39#ibcon#about to read 6, iclass 11, count 2 2006.201.19:20:56.39#ibcon#read 6, iclass 11, count 2 2006.201.19:20:56.39#ibcon#end of sib2, iclass 11, count 2 2006.201.19:20:56.39#ibcon#*mode == 0, iclass 11, count 2 2006.201.19:20:56.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.19:20:56.39#ibcon#[25=AT08-04\r\n] 2006.201.19:20:56.39#ibcon#*before write, iclass 11, count 2 2006.201.19:20:56.39#ibcon#enter sib2, iclass 11, count 2 2006.201.19:20:56.39#ibcon#flushed, iclass 11, count 2 2006.201.19:20:56.39#ibcon#about to write, iclass 11, count 2 2006.201.19:20:56.39#ibcon#wrote, iclass 11, count 2 2006.201.19:20:56.39#ibcon#about to read 3, iclass 11, count 2 2006.201.19:20:56.42#ibcon#read 3, iclass 11, count 2 2006.201.19:20:56.42#ibcon#about to read 4, iclass 11, count 2 2006.201.19:20:56.42#ibcon#read 4, iclass 11, count 2 2006.201.19:20:56.42#ibcon#about to read 5, iclass 11, count 2 2006.201.19:20:56.42#ibcon#read 5, iclass 11, count 2 2006.201.19:20:56.42#ibcon#about to read 6, iclass 11, count 2 2006.201.19:20:56.42#ibcon#read 6, iclass 11, count 2 2006.201.19:20:56.42#ibcon#end of sib2, iclass 11, count 2 2006.201.19:20:56.42#ibcon#*after write, iclass 11, count 2 2006.201.19:20:56.42#ibcon#*before return 0, iclass 11, count 2 2006.201.19:20:56.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:56.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:56.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.19:20:56.42#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:56.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:56.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:56.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:56.54#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:20:56.54#ibcon#first serial, iclass 11, count 0 2006.201.19:20:56.54#ibcon#enter sib2, iclass 11, count 0 2006.201.19:20:56.54#ibcon#flushed, iclass 11, count 0 2006.201.19:20:56.54#ibcon#about to write, iclass 11, count 0 2006.201.19:20:56.54#ibcon#wrote, iclass 11, count 0 2006.201.19:20:56.54#ibcon#about to read 3, iclass 11, count 0 2006.201.19:20:56.56#ibcon#read 3, iclass 11, count 0 2006.201.19:20:56.56#ibcon#about to read 4, iclass 11, count 0 2006.201.19:20:56.56#ibcon#read 4, iclass 11, count 0 2006.201.19:20:56.56#ibcon#about to read 5, iclass 11, count 0 2006.201.19:20:56.56#ibcon#read 5, iclass 11, count 0 2006.201.19:20:56.56#ibcon#about to read 6, iclass 11, count 0 2006.201.19:20:56.56#ibcon#read 6, iclass 11, count 0 2006.201.19:20:56.56#ibcon#end of sib2, iclass 11, count 0 2006.201.19:20:56.56#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:20:56.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:20:56.56#ibcon#[25=USB\r\n] 2006.201.19:20:56.56#ibcon#*before write, iclass 11, count 0 2006.201.19:20:56.56#ibcon#enter sib2, iclass 11, count 0 2006.201.19:20:56.56#ibcon#flushed, iclass 11, count 0 2006.201.19:20:56.56#ibcon#about to write, iclass 11, count 0 2006.201.19:20:56.56#ibcon#wrote, iclass 11, count 0 2006.201.19:20:56.56#ibcon#about to read 3, iclass 11, count 0 2006.201.19:20:56.59#ibcon#read 3, iclass 11, count 0 2006.201.19:20:56.59#ibcon#about to read 4, iclass 11, count 0 2006.201.19:20:56.59#ibcon#read 4, iclass 11, count 0 2006.201.19:20:56.59#ibcon#about to read 5, iclass 11, count 0 2006.201.19:20:56.59#ibcon#read 5, iclass 11, count 0 2006.201.19:20:56.59#ibcon#about to read 6, iclass 11, count 0 2006.201.19:20:56.59#ibcon#read 6, iclass 11, count 0 2006.201.19:20:56.59#ibcon#end of sib2, iclass 11, count 0 2006.201.19:20:56.59#ibcon#*after write, iclass 11, count 0 2006.201.19:20:56.59#ibcon#*before return 0, iclass 11, count 0 2006.201.19:20:56.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:56.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:56.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:20:56.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:20:56.59$vck44/vblo=1,629.99 2006.201.19:20:56.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.19:20:56.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.19:20:56.59#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:56.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:56.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:56.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:56.59#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:20:56.59#ibcon#first serial, iclass 13, count 0 2006.201.19:20:56.59#ibcon#enter sib2, iclass 13, count 0 2006.201.19:20:56.59#ibcon#flushed, iclass 13, count 0 2006.201.19:20:56.59#ibcon#about to write, iclass 13, count 0 2006.201.19:20:56.59#ibcon#wrote, iclass 13, count 0 2006.201.19:20:56.59#ibcon#about to read 3, iclass 13, count 0 2006.201.19:20:56.61#ibcon#read 3, iclass 13, count 0 2006.201.19:20:56.61#ibcon#about to read 4, iclass 13, count 0 2006.201.19:20:56.61#ibcon#read 4, iclass 13, count 0 2006.201.19:20:56.61#ibcon#about to read 5, iclass 13, count 0 2006.201.19:20:56.61#ibcon#read 5, iclass 13, count 0 2006.201.19:20:56.61#ibcon#about to read 6, iclass 13, count 0 2006.201.19:20:56.61#ibcon#read 6, iclass 13, count 0 2006.201.19:20:56.61#ibcon#end of sib2, iclass 13, count 0 2006.201.19:20:56.61#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:20:56.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:20:56.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:20:56.61#ibcon#*before write, iclass 13, count 0 2006.201.19:20:56.61#ibcon#enter sib2, iclass 13, count 0 2006.201.19:20:56.61#ibcon#flushed, iclass 13, count 0 2006.201.19:20:56.61#ibcon#about to write, iclass 13, count 0 2006.201.19:20:56.61#ibcon#wrote, iclass 13, count 0 2006.201.19:20:56.61#ibcon#about to read 3, iclass 13, count 0 2006.201.19:20:56.65#ibcon#read 3, iclass 13, count 0 2006.201.19:20:56.65#ibcon#about to read 4, iclass 13, count 0 2006.201.19:20:56.65#ibcon#read 4, iclass 13, count 0 2006.201.19:20:56.65#ibcon#about to read 5, iclass 13, count 0 2006.201.19:20:56.65#ibcon#read 5, iclass 13, count 0 2006.201.19:20:56.65#ibcon#about to read 6, iclass 13, count 0 2006.201.19:20:56.65#ibcon#read 6, iclass 13, count 0 2006.201.19:20:56.65#ibcon#end of sib2, iclass 13, count 0 2006.201.19:20:56.65#ibcon#*after write, iclass 13, count 0 2006.201.19:20:56.65#ibcon#*before return 0, iclass 13, count 0 2006.201.19:20:56.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:56.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:56.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:20:56.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:20:56.65$vck44/vb=1,4 2006.201.19:20:56.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.19:20:56.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.19:20:56.65#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:56.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:20:56.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:20:56.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:20:56.65#ibcon#enter wrdev, iclass 15, count 2 2006.201.19:20:56.65#ibcon#first serial, iclass 15, count 2 2006.201.19:20:56.65#ibcon#enter sib2, iclass 15, count 2 2006.201.19:20:56.65#ibcon#flushed, iclass 15, count 2 2006.201.19:20:56.65#ibcon#about to write, iclass 15, count 2 2006.201.19:20:56.65#ibcon#wrote, iclass 15, count 2 2006.201.19:20:56.65#ibcon#about to read 3, iclass 15, count 2 2006.201.19:20:56.67#ibcon#read 3, iclass 15, count 2 2006.201.19:20:56.67#ibcon#about to read 4, iclass 15, count 2 2006.201.19:20:56.67#ibcon#read 4, iclass 15, count 2 2006.201.19:20:56.67#ibcon#about to read 5, iclass 15, count 2 2006.201.19:20:56.67#ibcon#read 5, iclass 15, count 2 2006.201.19:20:56.67#ibcon#about to read 6, iclass 15, count 2 2006.201.19:20:56.67#ibcon#read 6, iclass 15, count 2 2006.201.19:20:56.67#ibcon#end of sib2, iclass 15, count 2 2006.201.19:20:56.67#ibcon#*mode == 0, iclass 15, count 2 2006.201.19:20:56.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.19:20:56.67#ibcon#[27=AT01-04\r\n] 2006.201.19:20:56.67#ibcon#*before write, iclass 15, count 2 2006.201.19:20:56.67#ibcon#enter sib2, iclass 15, count 2 2006.201.19:20:56.67#ibcon#flushed, iclass 15, count 2 2006.201.19:20:56.67#ibcon#about to write, iclass 15, count 2 2006.201.19:20:56.67#ibcon#wrote, iclass 15, count 2 2006.201.19:20:56.67#ibcon#about to read 3, iclass 15, count 2 2006.201.19:20:56.70#ibcon#read 3, iclass 15, count 2 2006.201.19:20:56.70#ibcon#about to read 4, iclass 15, count 2 2006.201.19:20:56.70#ibcon#read 4, iclass 15, count 2 2006.201.19:20:56.70#ibcon#about to read 5, iclass 15, count 2 2006.201.19:20:56.70#ibcon#read 5, iclass 15, count 2 2006.201.19:20:56.70#ibcon#about to read 6, iclass 15, count 2 2006.201.19:20:56.70#ibcon#read 6, iclass 15, count 2 2006.201.19:20:56.70#ibcon#end of sib2, iclass 15, count 2 2006.201.19:20:56.70#ibcon#*after write, iclass 15, count 2 2006.201.19:20:56.70#ibcon#*before return 0, iclass 15, count 2 2006.201.19:20:56.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:20:56.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:20:56.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.19:20:56.70#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:56.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:20:56.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:20:56.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:20:56.82#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:20:56.82#ibcon#first serial, iclass 15, count 0 2006.201.19:20:56.82#ibcon#enter sib2, iclass 15, count 0 2006.201.19:20:56.82#ibcon#flushed, iclass 15, count 0 2006.201.19:20:56.82#ibcon#about to write, iclass 15, count 0 2006.201.19:20:56.82#ibcon#wrote, iclass 15, count 0 2006.201.19:20:56.82#ibcon#about to read 3, iclass 15, count 0 2006.201.19:20:56.84#ibcon#read 3, iclass 15, count 0 2006.201.19:20:56.84#ibcon#about to read 4, iclass 15, count 0 2006.201.19:20:56.84#ibcon#read 4, iclass 15, count 0 2006.201.19:20:56.84#ibcon#about to read 5, iclass 15, count 0 2006.201.19:20:56.84#ibcon#read 5, iclass 15, count 0 2006.201.19:20:56.84#ibcon#about to read 6, iclass 15, count 0 2006.201.19:20:56.84#ibcon#read 6, iclass 15, count 0 2006.201.19:20:56.84#ibcon#end of sib2, iclass 15, count 0 2006.201.19:20:56.84#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:20:56.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:20:56.84#ibcon#[27=USB\r\n] 2006.201.19:20:56.84#ibcon#*before write, iclass 15, count 0 2006.201.19:20:56.84#ibcon#enter sib2, iclass 15, count 0 2006.201.19:20:56.84#ibcon#flushed, iclass 15, count 0 2006.201.19:20:56.84#ibcon#about to write, iclass 15, count 0 2006.201.19:20:56.84#ibcon#wrote, iclass 15, count 0 2006.201.19:20:56.84#ibcon#about to read 3, iclass 15, count 0 2006.201.19:20:56.87#ibcon#read 3, iclass 15, count 0 2006.201.19:20:56.87#ibcon#about to read 4, iclass 15, count 0 2006.201.19:20:56.87#ibcon#read 4, iclass 15, count 0 2006.201.19:20:56.87#ibcon#about to read 5, iclass 15, count 0 2006.201.19:20:56.87#ibcon#read 5, iclass 15, count 0 2006.201.19:20:56.87#ibcon#about to read 6, iclass 15, count 0 2006.201.19:20:56.87#ibcon#read 6, iclass 15, count 0 2006.201.19:20:56.87#ibcon#end of sib2, iclass 15, count 0 2006.201.19:20:56.87#ibcon#*after write, iclass 15, count 0 2006.201.19:20:56.87#ibcon#*before return 0, iclass 15, count 0 2006.201.19:20:56.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:20:56.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:20:56.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:20:56.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:20:56.87$vck44/vblo=2,634.99 2006.201.19:20:56.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.19:20:56.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.19:20:56.87#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:56.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:56.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:56.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:56.87#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:20:56.87#ibcon#first serial, iclass 17, count 0 2006.201.19:20:56.87#ibcon#enter sib2, iclass 17, count 0 2006.201.19:20:56.87#ibcon#flushed, iclass 17, count 0 2006.201.19:20:56.87#ibcon#about to write, iclass 17, count 0 2006.201.19:20:56.87#ibcon#wrote, iclass 17, count 0 2006.201.19:20:56.87#ibcon#about to read 3, iclass 17, count 0 2006.201.19:20:56.89#ibcon#read 3, iclass 17, count 0 2006.201.19:20:56.89#ibcon#about to read 4, iclass 17, count 0 2006.201.19:20:56.89#ibcon#read 4, iclass 17, count 0 2006.201.19:20:56.89#ibcon#about to read 5, iclass 17, count 0 2006.201.19:20:56.89#ibcon#read 5, iclass 17, count 0 2006.201.19:20:56.89#ibcon#about to read 6, iclass 17, count 0 2006.201.19:20:56.89#ibcon#read 6, iclass 17, count 0 2006.201.19:20:56.89#ibcon#end of sib2, iclass 17, count 0 2006.201.19:20:56.89#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:20:56.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:20:56.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:20:56.89#ibcon#*before write, iclass 17, count 0 2006.201.19:20:56.89#ibcon#enter sib2, iclass 17, count 0 2006.201.19:20:56.89#ibcon#flushed, iclass 17, count 0 2006.201.19:20:56.89#ibcon#about to write, iclass 17, count 0 2006.201.19:20:56.89#ibcon#wrote, iclass 17, count 0 2006.201.19:20:56.89#ibcon#about to read 3, iclass 17, count 0 2006.201.19:20:56.93#ibcon#read 3, iclass 17, count 0 2006.201.19:20:56.93#ibcon#about to read 4, iclass 17, count 0 2006.201.19:20:56.93#ibcon#read 4, iclass 17, count 0 2006.201.19:20:56.93#ibcon#about to read 5, iclass 17, count 0 2006.201.19:20:56.93#ibcon#read 5, iclass 17, count 0 2006.201.19:20:56.93#ibcon#about to read 6, iclass 17, count 0 2006.201.19:20:56.93#ibcon#read 6, iclass 17, count 0 2006.201.19:20:56.93#ibcon#end of sib2, iclass 17, count 0 2006.201.19:20:56.93#ibcon#*after write, iclass 17, count 0 2006.201.19:20:56.93#ibcon#*before return 0, iclass 17, count 0 2006.201.19:20:56.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:56.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:20:56.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:20:56.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:20:56.93$vck44/vb=2,5 2006.201.19:20:56.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.19:20:56.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.19:20:56.93#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:56.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:56.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:56.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:56.99#ibcon#enter wrdev, iclass 19, count 2 2006.201.19:20:56.99#ibcon#first serial, iclass 19, count 2 2006.201.19:20:56.99#ibcon#enter sib2, iclass 19, count 2 2006.201.19:20:56.99#ibcon#flushed, iclass 19, count 2 2006.201.19:20:56.99#ibcon#about to write, iclass 19, count 2 2006.201.19:20:56.99#ibcon#wrote, iclass 19, count 2 2006.201.19:20:56.99#ibcon#about to read 3, iclass 19, count 2 2006.201.19:20:57.01#ibcon#read 3, iclass 19, count 2 2006.201.19:20:57.01#ibcon#about to read 4, iclass 19, count 2 2006.201.19:20:57.01#ibcon#read 4, iclass 19, count 2 2006.201.19:20:57.01#ibcon#about to read 5, iclass 19, count 2 2006.201.19:20:57.01#ibcon#read 5, iclass 19, count 2 2006.201.19:20:57.01#ibcon#about to read 6, iclass 19, count 2 2006.201.19:20:57.01#ibcon#read 6, iclass 19, count 2 2006.201.19:20:57.01#ibcon#end of sib2, iclass 19, count 2 2006.201.19:20:57.01#ibcon#*mode == 0, iclass 19, count 2 2006.201.19:20:57.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.19:20:57.01#ibcon#[27=AT02-05\r\n] 2006.201.19:20:57.01#ibcon#*before write, iclass 19, count 2 2006.201.19:20:57.01#ibcon#enter sib2, iclass 19, count 2 2006.201.19:20:57.01#ibcon#flushed, iclass 19, count 2 2006.201.19:20:57.01#ibcon#about to write, iclass 19, count 2 2006.201.19:20:57.01#ibcon#wrote, iclass 19, count 2 2006.201.19:20:57.01#ibcon#about to read 3, iclass 19, count 2 2006.201.19:20:57.04#ibcon#read 3, iclass 19, count 2 2006.201.19:20:57.04#ibcon#about to read 4, iclass 19, count 2 2006.201.19:20:57.04#ibcon#read 4, iclass 19, count 2 2006.201.19:20:57.04#ibcon#about to read 5, iclass 19, count 2 2006.201.19:20:57.04#ibcon#read 5, iclass 19, count 2 2006.201.19:20:57.04#ibcon#about to read 6, iclass 19, count 2 2006.201.19:20:57.04#ibcon#read 6, iclass 19, count 2 2006.201.19:20:57.04#ibcon#end of sib2, iclass 19, count 2 2006.201.19:20:57.04#ibcon#*after write, iclass 19, count 2 2006.201.19:20:57.04#ibcon#*before return 0, iclass 19, count 2 2006.201.19:20:57.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:57.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:20:57.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.19:20:57.04#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:57.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:57.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:57.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:57.16#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:20:57.16#ibcon#first serial, iclass 19, count 0 2006.201.19:20:57.16#ibcon#enter sib2, iclass 19, count 0 2006.201.19:20:57.16#ibcon#flushed, iclass 19, count 0 2006.201.19:20:57.16#ibcon#about to write, iclass 19, count 0 2006.201.19:20:57.16#ibcon#wrote, iclass 19, count 0 2006.201.19:20:57.16#ibcon#about to read 3, iclass 19, count 0 2006.201.19:20:57.18#ibcon#read 3, iclass 19, count 0 2006.201.19:20:57.18#ibcon#about to read 4, iclass 19, count 0 2006.201.19:20:57.18#ibcon#read 4, iclass 19, count 0 2006.201.19:20:57.18#ibcon#about to read 5, iclass 19, count 0 2006.201.19:20:57.18#ibcon#read 5, iclass 19, count 0 2006.201.19:20:57.18#ibcon#about to read 6, iclass 19, count 0 2006.201.19:20:57.18#ibcon#read 6, iclass 19, count 0 2006.201.19:20:57.18#ibcon#end of sib2, iclass 19, count 0 2006.201.19:20:57.18#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:20:57.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:20:57.18#ibcon#[27=USB\r\n] 2006.201.19:20:57.18#ibcon#*before write, iclass 19, count 0 2006.201.19:20:57.18#ibcon#enter sib2, iclass 19, count 0 2006.201.19:20:57.18#ibcon#flushed, iclass 19, count 0 2006.201.19:20:57.18#ibcon#about to write, iclass 19, count 0 2006.201.19:20:57.18#ibcon#wrote, iclass 19, count 0 2006.201.19:20:57.18#ibcon#about to read 3, iclass 19, count 0 2006.201.19:20:57.21#ibcon#read 3, iclass 19, count 0 2006.201.19:20:57.21#ibcon#about to read 4, iclass 19, count 0 2006.201.19:20:57.21#ibcon#read 4, iclass 19, count 0 2006.201.19:20:57.21#ibcon#about to read 5, iclass 19, count 0 2006.201.19:20:57.21#ibcon#read 5, iclass 19, count 0 2006.201.19:20:57.21#ibcon#about to read 6, iclass 19, count 0 2006.201.19:20:57.21#ibcon#read 6, iclass 19, count 0 2006.201.19:20:57.21#ibcon#end of sib2, iclass 19, count 0 2006.201.19:20:57.21#ibcon#*after write, iclass 19, count 0 2006.201.19:20:57.21#ibcon#*before return 0, iclass 19, count 0 2006.201.19:20:57.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:57.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:20:57.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:20:57.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:20:57.21$vck44/vblo=3,649.99 2006.201.19:20:57.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.19:20:57.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.19:20:57.21#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:57.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:57.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:57.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:57.21#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:20:57.21#ibcon#first serial, iclass 21, count 0 2006.201.19:20:57.21#ibcon#enter sib2, iclass 21, count 0 2006.201.19:20:57.21#ibcon#flushed, iclass 21, count 0 2006.201.19:20:57.21#ibcon#about to write, iclass 21, count 0 2006.201.19:20:57.21#ibcon#wrote, iclass 21, count 0 2006.201.19:20:57.21#ibcon#about to read 3, iclass 21, count 0 2006.201.19:20:57.23#ibcon#read 3, iclass 21, count 0 2006.201.19:20:57.23#ibcon#about to read 4, iclass 21, count 0 2006.201.19:20:57.23#ibcon#read 4, iclass 21, count 0 2006.201.19:20:57.23#ibcon#about to read 5, iclass 21, count 0 2006.201.19:20:57.23#ibcon#read 5, iclass 21, count 0 2006.201.19:20:57.23#ibcon#about to read 6, iclass 21, count 0 2006.201.19:20:57.23#ibcon#read 6, iclass 21, count 0 2006.201.19:20:57.23#ibcon#end of sib2, iclass 21, count 0 2006.201.19:20:57.23#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:20:57.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:20:57.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:20:57.23#ibcon#*before write, iclass 21, count 0 2006.201.19:20:57.23#ibcon#enter sib2, iclass 21, count 0 2006.201.19:20:57.23#ibcon#flushed, iclass 21, count 0 2006.201.19:20:57.23#ibcon#about to write, iclass 21, count 0 2006.201.19:20:57.23#ibcon#wrote, iclass 21, count 0 2006.201.19:20:57.23#ibcon#about to read 3, iclass 21, count 0 2006.201.19:20:57.27#ibcon#read 3, iclass 21, count 0 2006.201.19:20:57.27#ibcon#about to read 4, iclass 21, count 0 2006.201.19:20:57.27#ibcon#read 4, iclass 21, count 0 2006.201.19:20:57.27#ibcon#about to read 5, iclass 21, count 0 2006.201.19:20:57.27#ibcon#read 5, iclass 21, count 0 2006.201.19:20:57.27#ibcon#about to read 6, iclass 21, count 0 2006.201.19:20:57.27#ibcon#read 6, iclass 21, count 0 2006.201.19:20:57.27#ibcon#end of sib2, iclass 21, count 0 2006.201.19:20:57.27#ibcon#*after write, iclass 21, count 0 2006.201.19:20:57.27#ibcon#*before return 0, iclass 21, count 0 2006.201.19:20:57.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:57.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:20:57.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:20:57.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:20:57.27$vck44/vb=3,4 2006.201.19:20:57.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.19:20:57.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.19:20:57.27#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:57.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:57.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:57.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:57.33#ibcon#enter wrdev, iclass 23, count 2 2006.201.19:20:57.33#ibcon#first serial, iclass 23, count 2 2006.201.19:20:57.33#ibcon#enter sib2, iclass 23, count 2 2006.201.19:20:57.33#ibcon#flushed, iclass 23, count 2 2006.201.19:20:57.33#ibcon#about to write, iclass 23, count 2 2006.201.19:20:57.33#ibcon#wrote, iclass 23, count 2 2006.201.19:20:57.33#ibcon#about to read 3, iclass 23, count 2 2006.201.19:20:57.35#ibcon#read 3, iclass 23, count 2 2006.201.19:20:57.35#ibcon#about to read 4, iclass 23, count 2 2006.201.19:20:57.35#ibcon#read 4, iclass 23, count 2 2006.201.19:20:57.35#ibcon#about to read 5, iclass 23, count 2 2006.201.19:20:57.35#ibcon#read 5, iclass 23, count 2 2006.201.19:20:57.35#ibcon#about to read 6, iclass 23, count 2 2006.201.19:20:57.35#ibcon#read 6, iclass 23, count 2 2006.201.19:20:57.35#ibcon#end of sib2, iclass 23, count 2 2006.201.19:20:57.35#ibcon#*mode == 0, iclass 23, count 2 2006.201.19:20:57.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.19:20:57.35#ibcon#[27=AT03-04\r\n] 2006.201.19:20:57.35#ibcon#*before write, iclass 23, count 2 2006.201.19:20:57.35#ibcon#enter sib2, iclass 23, count 2 2006.201.19:20:57.35#ibcon#flushed, iclass 23, count 2 2006.201.19:20:57.35#ibcon#about to write, iclass 23, count 2 2006.201.19:20:57.35#ibcon#wrote, iclass 23, count 2 2006.201.19:20:57.35#ibcon#about to read 3, iclass 23, count 2 2006.201.19:20:57.38#ibcon#read 3, iclass 23, count 2 2006.201.19:20:57.38#ibcon#about to read 4, iclass 23, count 2 2006.201.19:20:57.38#ibcon#read 4, iclass 23, count 2 2006.201.19:20:57.38#ibcon#about to read 5, iclass 23, count 2 2006.201.19:20:57.38#ibcon#read 5, iclass 23, count 2 2006.201.19:20:57.38#ibcon#about to read 6, iclass 23, count 2 2006.201.19:20:57.38#ibcon#read 6, iclass 23, count 2 2006.201.19:20:57.38#ibcon#end of sib2, iclass 23, count 2 2006.201.19:20:57.38#ibcon#*after write, iclass 23, count 2 2006.201.19:20:57.38#ibcon#*before return 0, iclass 23, count 2 2006.201.19:20:57.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:57.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:20:57.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.19:20:57.38#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:57.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:57.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:57.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:57.50#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:20:57.50#ibcon#first serial, iclass 23, count 0 2006.201.19:20:57.50#ibcon#enter sib2, iclass 23, count 0 2006.201.19:20:57.50#ibcon#flushed, iclass 23, count 0 2006.201.19:20:57.50#ibcon#about to write, iclass 23, count 0 2006.201.19:20:57.50#ibcon#wrote, iclass 23, count 0 2006.201.19:20:57.50#ibcon#about to read 3, iclass 23, count 0 2006.201.19:20:57.52#ibcon#read 3, iclass 23, count 0 2006.201.19:20:57.52#ibcon#about to read 4, iclass 23, count 0 2006.201.19:20:57.52#ibcon#read 4, iclass 23, count 0 2006.201.19:20:57.52#ibcon#about to read 5, iclass 23, count 0 2006.201.19:20:57.52#ibcon#read 5, iclass 23, count 0 2006.201.19:20:57.52#ibcon#about to read 6, iclass 23, count 0 2006.201.19:20:57.52#ibcon#read 6, iclass 23, count 0 2006.201.19:20:57.52#ibcon#end of sib2, iclass 23, count 0 2006.201.19:20:57.52#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:20:57.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:20:57.52#ibcon#[27=USB\r\n] 2006.201.19:20:57.52#ibcon#*before write, iclass 23, count 0 2006.201.19:20:57.52#ibcon#enter sib2, iclass 23, count 0 2006.201.19:20:57.52#ibcon#flushed, iclass 23, count 0 2006.201.19:20:57.52#ibcon#about to write, iclass 23, count 0 2006.201.19:20:57.52#ibcon#wrote, iclass 23, count 0 2006.201.19:20:57.52#ibcon#about to read 3, iclass 23, count 0 2006.201.19:20:57.55#ibcon#read 3, iclass 23, count 0 2006.201.19:20:57.55#ibcon#about to read 4, iclass 23, count 0 2006.201.19:20:57.55#ibcon#read 4, iclass 23, count 0 2006.201.19:20:57.55#ibcon#about to read 5, iclass 23, count 0 2006.201.19:20:57.55#ibcon#read 5, iclass 23, count 0 2006.201.19:20:57.55#ibcon#about to read 6, iclass 23, count 0 2006.201.19:20:57.55#ibcon#read 6, iclass 23, count 0 2006.201.19:20:57.55#ibcon#end of sib2, iclass 23, count 0 2006.201.19:20:57.55#ibcon#*after write, iclass 23, count 0 2006.201.19:20:57.55#ibcon#*before return 0, iclass 23, count 0 2006.201.19:20:57.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:57.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:20:57.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:20:57.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:20:57.55$vck44/vblo=4,679.99 2006.201.19:20:57.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.19:20:57.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.19:20:57.55#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:57.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:57.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:57.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:57.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:20:57.55#ibcon#first serial, iclass 25, count 0 2006.201.19:20:57.55#ibcon#enter sib2, iclass 25, count 0 2006.201.19:20:57.55#ibcon#flushed, iclass 25, count 0 2006.201.19:20:57.55#ibcon#about to write, iclass 25, count 0 2006.201.19:20:57.55#ibcon#wrote, iclass 25, count 0 2006.201.19:20:57.55#ibcon#about to read 3, iclass 25, count 0 2006.201.19:20:57.57#ibcon#read 3, iclass 25, count 0 2006.201.19:20:57.57#ibcon#about to read 4, iclass 25, count 0 2006.201.19:20:57.57#ibcon#read 4, iclass 25, count 0 2006.201.19:20:57.57#ibcon#about to read 5, iclass 25, count 0 2006.201.19:20:57.57#ibcon#read 5, iclass 25, count 0 2006.201.19:20:57.57#ibcon#about to read 6, iclass 25, count 0 2006.201.19:20:57.57#ibcon#read 6, iclass 25, count 0 2006.201.19:20:57.57#ibcon#end of sib2, iclass 25, count 0 2006.201.19:20:57.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:20:57.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:20:57.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:20:57.57#ibcon#*before write, iclass 25, count 0 2006.201.19:20:57.57#ibcon#enter sib2, iclass 25, count 0 2006.201.19:20:57.57#ibcon#flushed, iclass 25, count 0 2006.201.19:20:57.57#ibcon#about to write, iclass 25, count 0 2006.201.19:20:57.57#ibcon#wrote, iclass 25, count 0 2006.201.19:20:57.57#ibcon#about to read 3, iclass 25, count 0 2006.201.19:20:57.61#ibcon#read 3, iclass 25, count 0 2006.201.19:20:57.61#ibcon#about to read 4, iclass 25, count 0 2006.201.19:20:57.61#ibcon#read 4, iclass 25, count 0 2006.201.19:20:57.61#ibcon#about to read 5, iclass 25, count 0 2006.201.19:20:57.61#ibcon#read 5, iclass 25, count 0 2006.201.19:20:57.61#ibcon#about to read 6, iclass 25, count 0 2006.201.19:20:57.61#ibcon#read 6, iclass 25, count 0 2006.201.19:20:57.61#ibcon#end of sib2, iclass 25, count 0 2006.201.19:20:57.61#ibcon#*after write, iclass 25, count 0 2006.201.19:20:57.61#ibcon#*before return 0, iclass 25, count 0 2006.201.19:20:57.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:57.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:20:57.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:20:57.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:20:57.61$vck44/vb=4,5 2006.201.19:20:57.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.19:20:57.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.19:20:57.61#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:57.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:57.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:57.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:57.67#ibcon#enter wrdev, iclass 27, count 2 2006.201.19:20:57.67#ibcon#first serial, iclass 27, count 2 2006.201.19:20:57.67#ibcon#enter sib2, iclass 27, count 2 2006.201.19:20:57.67#ibcon#flushed, iclass 27, count 2 2006.201.19:20:57.67#ibcon#about to write, iclass 27, count 2 2006.201.19:20:57.67#ibcon#wrote, iclass 27, count 2 2006.201.19:20:57.67#ibcon#about to read 3, iclass 27, count 2 2006.201.19:20:57.69#ibcon#read 3, iclass 27, count 2 2006.201.19:20:57.69#ibcon#about to read 4, iclass 27, count 2 2006.201.19:20:57.69#ibcon#read 4, iclass 27, count 2 2006.201.19:20:57.69#ibcon#about to read 5, iclass 27, count 2 2006.201.19:20:57.69#ibcon#read 5, iclass 27, count 2 2006.201.19:20:57.69#ibcon#about to read 6, iclass 27, count 2 2006.201.19:20:57.69#ibcon#read 6, iclass 27, count 2 2006.201.19:20:57.69#ibcon#end of sib2, iclass 27, count 2 2006.201.19:20:57.69#ibcon#*mode == 0, iclass 27, count 2 2006.201.19:20:57.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.19:20:57.69#ibcon#[27=AT04-05\r\n] 2006.201.19:20:57.69#ibcon#*before write, iclass 27, count 2 2006.201.19:20:57.69#ibcon#enter sib2, iclass 27, count 2 2006.201.19:20:57.69#ibcon#flushed, iclass 27, count 2 2006.201.19:20:57.69#ibcon#about to write, iclass 27, count 2 2006.201.19:20:57.69#ibcon#wrote, iclass 27, count 2 2006.201.19:20:57.69#ibcon#about to read 3, iclass 27, count 2 2006.201.19:20:57.72#ibcon#read 3, iclass 27, count 2 2006.201.19:20:57.72#ibcon#about to read 4, iclass 27, count 2 2006.201.19:20:57.72#ibcon#read 4, iclass 27, count 2 2006.201.19:20:57.72#ibcon#about to read 5, iclass 27, count 2 2006.201.19:20:57.72#ibcon#read 5, iclass 27, count 2 2006.201.19:20:57.72#ibcon#about to read 6, iclass 27, count 2 2006.201.19:20:57.72#ibcon#read 6, iclass 27, count 2 2006.201.19:20:57.72#ibcon#end of sib2, iclass 27, count 2 2006.201.19:20:57.72#ibcon#*after write, iclass 27, count 2 2006.201.19:20:57.72#ibcon#*before return 0, iclass 27, count 2 2006.201.19:20:57.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:57.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:20:57.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.19:20:57.72#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:57.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:57.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:57.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:57.84#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:20:57.84#ibcon#first serial, iclass 27, count 0 2006.201.19:20:57.84#ibcon#enter sib2, iclass 27, count 0 2006.201.19:20:57.84#ibcon#flushed, iclass 27, count 0 2006.201.19:20:57.84#ibcon#about to write, iclass 27, count 0 2006.201.19:20:57.84#ibcon#wrote, iclass 27, count 0 2006.201.19:20:57.84#ibcon#about to read 3, iclass 27, count 0 2006.201.19:20:57.86#ibcon#read 3, iclass 27, count 0 2006.201.19:20:57.86#ibcon#about to read 4, iclass 27, count 0 2006.201.19:20:57.86#ibcon#read 4, iclass 27, count 0 2006.201.19:20:57.86#ibcon#about to read 5, iclass 27, count 0 2006.201.19:20:57.86#ibcon#read 5, iclass 27, count 0 2006.201.19:20:57.86#ibcon#about to read 6, iclass 27, count 0 2006.201.19:20:57.86#ibcon#read 6, iclass 27, count 0 2006.201.19:20:57.86#ibcon#end of sib2, iclass 27, count 0 2006.201.19:20:57.86#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:20:57.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:20:57.86#ibcon#[27=USB\r\n] 2006.201.19:20:57.86#ibcon#*before write, iclass 27, count 0 2006.201.19:20:57.86#ibcon#enter sib2, iclass 27, count 0 2006.201.19:20:57.86#ibcon#flushed, iclass 27, count 0 2006.201.19:20:57.86#ibcon#about to write, iclass 27, count 0 2006.201.19:20:57.86#ibcon#wrote, iclass 27, count 0 2006.201.19:20:57.86#ibcon#about to read 3, iclass 27, count 0 2006.201.19:20:57.89#ibcon#read 3, iclass 27, count 0 2006.201.19:20:57.89#ibcon#about to read 4, iclass 27, count 0 2006.201.19:20:57.89#ibcon#read 4, iclass 27, count 0 2006.201.19:20:57.89#ibcon#about to read 5, iclass 27, count 0 2006.201.19:20:57.89#ibcon#read 5, iclass 27, count 0 2006.201.19:20:57.89#ibcon#about to read 6, iclass 27, count 0 2006.201.19:20:57.89#ibcon#read 6, iclass 27, count 0 2006.201.19:20:57.89#ibcon#end of sib2, iclass 27, count 0 2006.201.19:20:57.89#ibcon#*after write, iclass 27, count 0 2006.201.19:20:57.89#ibcon#*before return 0, iclass 27, count 0 2006.201.19:20:57.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:57.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:20:57.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:20:57.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:20:57.89$vck44/vblo=5,709.99 2006.201.19:20:57.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.19:20:57.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.19:20:57.89#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:57.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:57.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:57.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:57.89#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:20:57.89#ibcon#first serial, iclass 29, count 0 2006.201.19:20:57.89#ibcon#enter sib2, iclass 29, count 0 2006.201.19:20:57.89#ibcon#flushed, iclass 29, count 0 2006.201.19:20:57.89#ibcon#about to write, iclass 29, count 0 2006.201.19:20:57.89#ibcon#wrote, iclass 29, count 0 2006.201.19:20:57.89#ibcon#about to read 3, iclass 29, count 0 2006.201.19:20:57.91#ibcon#read 3, iclass 29, count 0 2006.201.19:20:57.91#ibcon#about to read 4, iclass 29, count 0 2006.201.19:20:57.91#ibcon#read 4, iclass 29, count 0 2006.201.19:20:57.91#ibcon#about to read 5, iclass 29, count 0 2006.201.19:20:57.91#ibcon#read 5, iclass 29, count 0 2006.201.19:20:57.91#ibcon#about to read 6, iclass 29, count 0 2006.201.19:20:57.91#ibcon#read 6, iclass 29, count 0 2006.201.19:20:57.91#ibcon#end of sib2, iclass 29, count 0 2006.201.19:20:57.91#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:20:57.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:20:57.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:20:57.91#ibcon#*before write, iclass 29, count 0 2006.201.19:20:57.91#ibcon#enter sib2, iclass 29, count 0 2006.201.19:20:57.91#ibcon#flushed, iclass 29, count 0 2006.201.19:20:57.91#ibcon#about to write, iclass 29, count 0 2006.201.19:20:57.91#ibcon#wrote, iclass 29, count 0 2006.201.19:20:57.91#ibcon#about to read 3, iclass 29, count 0 2006.201.19:20:57.96#ibcon#read 3, iclass 29, count 0 2006.201.19:20:57.96#ibcon#about to read 4, iclass 29, count 0 2006.201.19:20:57.96#ibcon#read 4, iclass 29, count 0 2006.201.19:20:57.96#ibcon#about to read 5, iclass 29, count 0 2006.201.19:20:57.96#ibcon#read 5, iclass 29, count 0 2006.201.19:20:57.96#ibcon#about to read 6, iclass 29, count 0 2006.201.19:20:57.96#ibcon#read 6, iclass 29, count 0 2006.201.19:20:57.96#ibcon#end of sib2, iclass 29, count 0 2006.201.19:20:57.96#ibcon#*after write, iclass 29, count 0 2006.201.19:20:57.96#ibcon#*before return 0, iclass 29, count 0 2006.201.19:20:57.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:57.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:20:57.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:20:57.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:20:57.96$vck44/vb=5,4 2006.201.19:20:57.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.19:20:57.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.19:20:57.96#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:57.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:58.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:58.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:58.01#ibcon#enter wrdev, iclass 31, count 2 2006.201.19:20:58.01#ibcon#first serial, iclass 31, count 2 2006.201.19:20:58.01#ibcon#enter sib2, iclass 31, count 2 2006.201.19:20:58.01#ibcon#flushed, iclass 31, count 2 2006.201.19:20:58.01#ibcon#about to write, iclass 31, count 2 2006.201.19:20:58.01#ibcon#wrote, iclass 31, count 2 2006.201.19:20:58.01#ibcon#about to read 3, iclass 31, count 2 2006.201.19:20:58.03#ibcon#read 3, iclass 31, count 2 2006.201.19:20:58.03#ibcon#about to read 4, iclass 31, count 2 2006.201.19:20:58.03#ibcon#read 4, iclass 31, count 2 2006.201.19:20:58.03#ibcon#about to read 5, iclass 31, count 2 2006.201.19:20:58.03#ibcon#read 5, iclass 31, count 2 2006.201.19:20:58.03#ibcon#about to read 6, iclass 31, count 2 2006.201.19:20:58.03#ibcon#read 6, iclass 31, count 2 2006.201.19:20:58.03#ibcon#end of sib2, iclass 31, count 2 2006.201.19:20:58.03#ibcon#*mode == 0, iclass 31, count 2 2006.201.19:20:58.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.19:20:58.03#ibcon#[27=AT05-04\r\n] 2006.201.19:20:58.03#ibcon#*before write, iclass 31, count 2 2006.201.19:20:58.03#ibcon#enter sib2, iclass 31, count 2 2006.201.19:20:58.03#ibcon#flushed, iclass 31, count 2 2006.201.19:20:58.03#ibcon#about to write, iclass 31, count 2 2006.201.19:20:58.03#ibcon#wrote, iclass 31, count 2 2006.201.19:20:58.03#ibcon#about to read 3, iclass 31, count 2 2006.201.19:20:58.06#ibcon#read 3, iclass 31, count 2 2006.201.19:20:58.06#ibcon#about to read 4, iclass 31, count 2 2006.201.19:20:58.06#ibcon#read 4, iclass 31, count 2 2006.201.19:20:58.06#ibcon#about to read 5, iclass 31, count 2 2006.201.19:20:58.06#ibcon#read 5, iclass 31, count 2 2006.201.19:20:58.06#ibcon#about to read 6, iclass 31, count 2 2006.201.19:20:58.06#ibcon#read 6, iclass 31, count 2 2006.201.19:20:58.06#ibcon#end of sib2, iclass 31, count 2 2006.201.19:20:58.06#ibcon#*after write, iclass 31, count 2 2006.201.19:20:58.06#ibcon#*before return 0, iclass 31, count 2 2006.201.19:20:58.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:58.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:20:58.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.19:20:58.06#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:58.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:58.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:58.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:58.18#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:20:58.18#ibcon#first serial, iclass 31, count 0 2006.201.19:20:58.18#ibcon#enter sib2, iclass 31, count 0 2006.201.19:20:58.18#ibcon#flushed, iclass 31, count 0 2006.201.19:20:58.18#ibcon#about to write, iclass 31, count 0 2006.201.19:20:58.18#ibcon#wrote, iclass 31, count 0 2006.201.19:20:58.18#ibcon#about to read 3, iclass 31, count 0 2006.201.19:20:58.20#ibcon#read 3, iclass 31, count 0 2006.201.19:20:58.20#ibcon#about to read 4, iclass 31, count 0 2006.201.19:20:58.20#ibcon#read 4, iclass 31, count 0 2006.201.19:20:58.20#ibcon#about to read 5, iclass 31, count 0 2006.201.19:20:58.20#ibcon#read 5, iclass 31, count 0 2006.201.19:20:58.20#ibcon#about to read 6, iclass 31, count 0 2006.201.19:20:58.20#ibcon#read 6, iclass 31, count 0 2006.201.19:20:58.20#ibcon#end of sib2, iclass 31, count 0 2006.201.19:20:58.20#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:20:58.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:20:58.20#ibcon#[27=USB\r\n] 2006.201.19:20:58.20#ibcon#*before write, iclass 31, count 0 2006.201.19:20:58.20#ibcon#enter sib2, iclass 31, count 0 2006.201.19:20:58.20#ibcon#flushed, iclass 31, count 0 2006.201.19:20:58.20#ibcon#about to write, iclass 31, count 0 2006.201.19:20:58.20#ibcon#wrote, iclass 31, count 0 2006.201.19:20:58.20#ibcon#about to read 3, iclass 31, count 0 2006.201.19:20:58.23#ibcon#read 3, iclass 31, count 0 2006.201.19:20:58.23#ibcon#about to read 4, iclass 31, count 0 2006.201.19:20:58.23#ibcon#read 4, iclass 31, count 0 2006.201.19:20:58.23#ibcon#about to read 5, iclass 31, count 0 2006.201.19:20:58.23#ibcon#read 5, iclass 31, count 0 2006.201.19:20:58.23#ibcon#about to read 6, iclass 31, count 0 2006.201.19:20:58.23#ibcon#read 6, iclass 31, count 0 2006.201.19:20:58.23#ibcon#end of sib2, iclass 31, count 0 2006.201.19:20:58.23#ibcon#*after write, iclass 31, count 0 2006.201.19:20:58.23#ibcon#*before return 0, iclass 31, count 0 2006.201.19:20:58.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:58.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:20:58.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:20:58.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:20:58.23$vck44/vblo=6,719.99 2006.201.19:20:58.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.19:20:58.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.19:20:58.23#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:58.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:58.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:58.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:58.23#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:20:58.23#ibcon#first serial, iclass 33, count 0 2006.201.19:20:58.23#ibcon#enter sib2, iclass 33, count 0 2006.201.19:20:58.23#ibcon#flushed, iclass 33, count 0 2006.201.19:20:58.23#ibcon#about to write, iclass 33, count 0 2006.201.19:20:58.23#ibcon#wrote, iclass 33, count 0 2006.201.19:20:58.23#ibcon#about to read 3, iclass 33, count 0 2006.201.19:20:58.25#ibcon#read 3, iclass 33, count 0 2006.201.19:20:58.25#ibcon#about to read 4, iclass 33, count 0 2006.201.19:20:58.25#ibcon#read 4, iclass 33, count 0 2006.201.19:20:58.25#ibcon#about to read 5, iclass 33, count 0 2006.201.19:20:58.25#ibcon#read 5, iclass 33, count 0 2006.201.19:20:58.25#ibcon#about to read 6, iclass 33, count 0 2006.201.19:20:58.25#ibcon#read 6, iclass 33, count 0 2006.201.19:20:58.25#ibcon#end of sib2, iclass 33, count 0 2006.201.19:20:58.25#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:20:58.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:20:58.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:20:58.25#ibcon#*before write, iclass 33, count 0 2006.201.19:20:58.25#ibcon#enter sib2, iclass 33, count 0 2006.201.19:20:58.25#ibcon#flushed, iclass 33, count 0 2006.201.19:20:58.25#ibcon#about to write, iclass 33, count 0 2006.201.19:20:58.25#ibcon#wrote, iclass 33, count 0 2006.201.19:20:58.25#ibcon#about to read 3, iclass 33, count 0 2006.201.19:20:58.29#ibcon#read 3, iclass 33, count 0 2006.201.19:20:58.29#ibcon#about to read 4, iclass 33, count 0 2006.201.19:20:58.29#ibcon#read 4, iclass 33, count 0 2006.201.19:20:58.29#ibcon#about to read 5, iclass 33, count 0 2006.201.19:20:58.29#ibcon#read 5, iclass 33, count 0 2006.201.19:20:58.29#ibcon#about to read 6, iclass 33, count 0 2006.201.19:20:58.29#ibcon#read 6, iclass 33, count 0 2006.201.19:20:58.29#ibcon#end of sib2, iclass 33, count 0 2006.201.19:20:58.29#ibcon#*after write, iclass 33, count 0 2006.201.19:20:58.29#ibcon#*before return 0, iclass 33, count 0 2006.201.19:20:58.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:58.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:20:58.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:20:58.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:20:58.29$vck44/vb=6,4 2006.201.19:20:58.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.19:20:58.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.19:20:58.29#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:58.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:58.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:58.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:58.35#ibcon#enter wrdev, iclass 35, count 2 2006.201.19:20:58.35#ibcon#first serial, iclass 35, count 2 2006.201.19:20:58.35#ibcon#enter sib2, iclass 35, count 2 2006.201.19:20:58.35#ibcon#flushed, iclass 35, count 2 2006.201.19:20:58.35#ibcon#about to write, iclass 35, count 2 2006.201.19:20:58.35#ibcon#wrote, iclass 35, count 2 2006.201.19:20:58.35#ibcon#about to read 3, iclass 35, count 2 2006.201.19:20:58.37#ibcon#read 3, iclass 35, count 2 2006.201.19:20:58.37#ibcon#about to read 4, iclass 35, count 2 2006.201.19:20:58.37#ibcon#read 4, iclass 35, count 2 2006.201.19:20:58.37#ibcon#about to read 5, iclass 35, count 2 2006.201.19:20:58.37#ibcon#read 5, iclass 35, count 2 2006.201.19:20:58.37#ibcon#about to read 6, iclass 35, count 2 2006.201.19:20:58.37#ibcon#read 6, iclass 35, count 2 2006.201.19:20:58.37#ibcon#end of sib2, iclass 35, count 2 2006.201.19:20:58.37#ibcon#*mode == 0, iclass 35, count 2 2006.201.19:20:58.37#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.19:20:58.37#ibcon#[27=AT06-04\r\n] 2006.201.19:20:58.37#ibcon#*before write, iclass 35, count 2 2006.201.19:20:58.37#ibcon#enter sib2, iclass 35, count 2 2006.201.19:20:58.37#ibcon#flushed, iclass 35, count 2 2006.201.19:20:58.37#ibcon#about to write, iclass 35, count 2 2006.201.19:20:58.37#ibcon#wrote, iclass 35, count 2 2006.201.19:20:58.37#ibcon#about to read 3, iclass 35, count 2 2006.201.19:20:58.39#abcon#<5=/03 1.0 2.5 20.491001002.5\r\n> 2006.201.19:20:58.40#ibcon#read 3, iclass 35, count 2 2006.201.19:20:58.40#ibcon#about to read 4, iclass 35, count 2 2006.201.19:20:58.40#ibcon#read 4, iclass 35, count 2 2006.201.19:20:58.40#ibcon#about to read 5, iclass 35, count 2 2006.201.19:20:58.40#ibcon#read 5, iclass 35, count 2 2006.201.19:20:58.40#ibcon#about to read 6, iclass 35, count 2 2006.201.19:20:58.40#ibcon#read 6, iclass 35, count 2 2006.201.19:20:58.40#ibcon#end of sib2, iclass 35, count 2 2006.201.19:20:58.40#ibcon#*after write, iclass 35, count 2 2006.201.19:20:58.40#ibcon#*before return 0, iclass 35, count 2 2006.201.19:20:58.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:58.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:20:58.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.19:20:58.40#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:58.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:58.41#abcon#{5=INTERFACE CLEAR} 2006.201.19:20:58.47#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:20:58.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:58.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:58.52#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:20:58.52#ibcon#first serial, iclass 35, count 0 2006.201.19:20:58.52#ibcon#enter sib2, iclass 35, count 0 2006.201.19:20:58.52#ibcon#flushed, iclass 35, count 0 2006.201.19:20:58.52#ibcon#about to write, iclass 35, count 0 2006.201.19:20:58.52#ibcon#wrote, iclass 35, count 0 2006.201.19:20:58.52#ibcon#about to read 3, iclass 35, count 0 2006.201.19:20:58.54#ibcon#read 3, iclass 35, count 0 2006.201.19:20:58.54#ibcon#about to read 4, iclass 35, count 0 2006.201.19:20:58.54#ibcon#read 4, iclass 35, count 0 2006.201.19:20:58.54#ibcon#about to read 5, iclass 35, count 0 2006.201.19:20:58.54#ibcon#read 5, iclass 35, count 0 2006.201.19:20:58.54#ibcon#about to read 6, iclass 35, count 0 2006.201.19:20:58.54#ibcon#read 6, iclass 35, count 0 2006.201.19:20:58.54#ibcon#end of sib2, iclass 35, count 0 2006.201.19:20:58.54#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:20:58.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:20:58.54#ibcon#[27=USB\r\n] 2006.201.19:20:58.54#ibcon#*before write, iclass 35, count 0 2006.201.19:20:58.54#ibcon#enter sib2, iclass 35, count 0 2006.201.19:20:58.54#ibcon#flushed, iclass 35, count 0 2006.201.19:20:58.54#ibcon#about to write, iclass 35, count 0 2006.201.19:20:58.54#ibcon#wrote, iclass 35, count 0 2006.201.19:20:58.54#ibcon#about to read 3, iclass 35, count 0 2006.201.19:20:58.57#ibcon#read 3, iclass 35, count 0 2006.201.19:20:58.57#ibcon#about to read 4, iclass 35, count 0 2006.201.19:20:58.57#ibcon#read 4, iclass 35, count 0 2006.201.19:20:58.57#ibcon#about to read 5, iclass 35, count 0 2006.201.19:20:58.57#ibcon#read 5, iclass 35, count 0 2006.201.19:20:58.57#ibcon#about to read 6, iclass 35, count 0 2006.201.19:20:58.57#ibcon#read 6, iclass 35, count 0 2006.201.19:20:58.57#ibcon#end of sib2, iclass 35, count 0 2006.201.19:20:58.57#ibcon#*after write, iclass 35, count 0 2006.201.19:20:58.57#ibcon#*before return 0, iclass 35, count 0 2006.201.19:20:58.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:58.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:20:58.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:20:58.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:20:58.57$vck44/vblo=7,734.99 2006.201.19:20:58.57#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.19:20:58.57#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.19:20:58.57#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:58.57#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:58.57#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:58.57#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:58.57#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:20:58.57#ibcon#first serial, iclass 2, count 0 2006.201.19:20:58.57#ibcon#enter sib2, iclass 2, count 0 2006.201.19:20:58.57#ibcon#flushed, iclass 2, count 0 2006.201.19:20:58.57#ibcon#about to write, iclass 2, count 0 2006.201.19:20:58.57#ibcon#wrote, iclass 2, count 0 2006.201.19:20:58.57#ibcon#about to read 3, iclass 2, count 0 2006.201.19:20:58.59#ibcon#read 3, iclass 2, count 0 2006.201.19:20:58.59#ibcon#about to read 4, iclass 2, count 0 2006.201.19:20:58.59#ibcon#read 4, iclass 2, count 0 2006.201.19:20:58.59#ibcon#about to read 5, iclass 2, count 0 2006.201.19:20:58.59#ibcon#read 5, iclass 2, count 0 2006.201.19:20:58.59#ibcon#about to read 6, iclass 2, count 0 2006.201.19:20:58.59#ibcon#read 6, iclass 2, count 0 2006.201.19:20:58.59#ibcon#end of sib2, iclass 2, count 0 2006.201.19:20:58.59#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:20:58.59#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:20:58.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:20:58.59#ibcon#*before write, iclass 2, count 0 2006.201.19:20:58.59#ibcon#enter sib2, iclass 2, count 0 2006.201.19:20:58.59#ibcon#flushed, iclass 2, count 0 2006.201.19:20:58.59#ibcon#about to write, iclass 2, count 0 2006.201.19:20:58.59#ibcon#wrote, iclass 2, count 0 2006.201.19:20:58.59#ibcon#about to read 3, iclass 2, count 0 2006.201.19:20:58.63#ibcon#read 3, iclass 2, count 0 2006.201.19:20:58.63#ibcon#about to read 4, iclass 2, count 0 2006.201.19:20:58.63#ibcon#read 4, iclass 2, count 0 2006.201.19:20:58.63#ibcon#about to read 5, iclass 2, count 0 2006.201.19:20:58.63#ibcon#read 5, iclass 2, count 0 2006.201.19:20:58.63#ibcon#about to read 6, iclass 2, count 0 2006.201.19:20:58.63#ibcon#read 6, iclass 2, count 0 2006.201.19:20:58.63#ibcon#end of sib2, iclass 2, count 0 2006.201.19:20:58.63#ibcon#*after write, iclass 2, count 0 2006.201.19:20:58.63#ibcon#*before return 0, iclass 2, count 0 2006.201.19:20:58.63#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:58.63#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:20:58.63#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:20:58.63#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:20:58.63$vck44/vb=7,4 2006.201.19:20:58.63#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.19:20:58.63#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.19:20:58.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:58.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:58.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:58.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:58.69#ibcon#enter wrdev, iclass 5, count 2 2006.201.19:20:58.69#ibcon#first serial, iclass 5, count 2 2006.201.19:20:58.69#ibcon#enter sib2, iclass 5, count 2 2006.201.19:20:58.69#ibcon#flushed, iclass 5, count 2 2006.201.19:20:58.69#ibcon#about to write, iclass 5, count 2 2006.201.19:20:58.69#ibcon#wrote, iclass 5, count 2 2006.201.19:20:58.69#ibcon#about to read 3, iclass 5, count 2 2006.201.19:20:58.71#ibcon#read 3, iclass 5, count 2 2006.201.19:20:58.71#ibcon#about to read 4, iclass 5, count 2 2006.201.19:20:58.71#ibcon#read 4, iclass 5, count 2 2006.201.19:20:58.71#ibcon#about to read 5, iclass 5, count 2 2006.201.19:20:58.71#ibcon#read 5, iclass 5, count 2 2006.201.19:20:58.71#ibcon#about to read 6, iclass 5, count 2 2006.201.19:20:58.71#ibcon#read 6, iclass 5, count 2 2006.201.19:20:58.71#ibcon#end of sib2, iclass 5, count 2 2006.201.19:20:58.71#ibcon#*mode == 0, iclass 5, count 2 2006.201.19:20:58.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.19:20:58.71#ibcon#[27=AT07-04\r\n] 2006.201.19:20:58.71#ibcon#*before write, iclass 5, count 2 2006.201.19:20:58.71#ibcon#enter sib2, iclass 5, count 2 2006.201.19:20:58.71#ibcon#flushed, iclass 5, count 2 2006.201.19:20:58.71#ibcon#about to write, iclass 5, count 2 2006.201.19:20:58.71#ibcon#wrote, iclass 5, count 2 2006.201.19:20:58.71#ibcon#about to read 3, iclass 5, count 2 2006.201.19:20:58.74#ibcon#read 3, iclass 5, count 2 2006.201.19:20:58.74#ibcon#about to read 4, iclass 5, count 2 2006.201.19:20:58.74#ibcon#read 4, iclass 5, count 2 2006.201.19:20:58.74#ibcon#about to read 5, iclass 5, count 2 2006.201.19:20:58.74#ibcon#read 5, iclass 5, count 2 2006.201.19:20:58.74#ibcon#about to read 6, iclass 5, count 2 2006.201.19:20:58.74#ibcon#read 6, iclass 5, count 2 2006.201.19:20:58.74#ibcon#end of sib2, iclass 5, count 2 2006.201.19:20:58.74#ibcon#*after write, iclass 5, count 2 2006.201.19:20:58.74#ibcon#*before return 0, iclass 5, count 2 2006.201.19:20:58.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:58.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:20:58.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.19:20:58.74#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:58.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:58.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:58.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:58.86#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:20:58.86#ibcon#first serial, iclass 5, count 0 2006.201.19:20:58.86#ibcon#enter sib2, iclass 5, count 0 2006.201.19:20:58.86#ibcon#flushed, iclass 5, count 0 2006.201.19:20:58.86#ibcon#about to write, iclass 5, count 0 2006.201.19:20:58.86#ibcon#wrote, iclass 5, count 0 2006.201.19:20:58.86#ibcon#about to read 3, iclass 5, count 0 2006.201.19:20:58.88#ibcon#read 3, iclass 5, count 0 2006.201.19:20:58.88#ibcon#about to read 4, iclass 5, count 0 2006.201.19:20:58.88#ibcon#read 4, iclass 5, count 0 2006.201.19:20:58.88#ibcon#about to read 5, iclass 5, count 0 2006.201.19:20:58.88#ibcon#read 5, iclass 5, count 0 2006.201.19:20:58.88#ibcon#about to read 6, iclass 5, count 0 2006.201.19:20:58.88#ibcon#read 6, iclass 5, count 0 2006.201.19:20:58.88#ibcon#end of sib2, iclass 5, count 0 2006.201.19:20:58.88#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:20:58.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:20:58.88#ibcon#[27=USB\r\n] 2006.201.19:20:58.88#ibcon#*before write, iclass 5, count 0 2006.201.19:20:58.88#ibcon#enter sib2, iclass 5, count 0 2006.201.19:20:58.88#ibcon#flushed, iclass 5, count 0 2006.201.19:20:58.88#ibcon#about to write, iclass 5, count 0 2006.201.19:20:58.88#ibcon#wrote, iclass 5, count 0 2006.201.19:20:58.88#ibcon#about to read 3, iclass 5, count 0 2006.201.19:20:58.91#ibcon#read 3, iclass 5, count 0 2006.201.19:20:58.91#ibcon#about to read 4, iclass 5, count 0 2006.201.19:20:58.91#ibcon#read 4, iclass 5, count 0 2006.201.19:20:58.91#ibcon#about to read 5, iclass 5, count 0 2006.201.19:20:58.91#ibcon#read 5, iclass 5, count 0 2006.201.19:20:58.91#ibcon#about to read 6, iclass 5, count 0 2006.201.19:20:58.91#ibcon#read 6, iclass 5, count 0 2006.201.19:20:58.91#ibcon#end of sib2, iclass 5, count 0 2006.201.19:20:58.91#ibcon#*after write, iclass 5, count 0 2006.201.19:20:58.91#ibcon#*before return 0, iclass 5, count 0 2006.201.19:20:58.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:58.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:20:58.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:20:58.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:20:58.91$vck44/vblo=8,744.99 2006.201.19:20:58.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.19:20:58.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.19:20:58.91#ibcon#ireg 17 cls_cnt 0 2006.201.19:20:58.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:58.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:58.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:58.91#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:20:58.91#ibcon#first serial, iclass 7, count 0 2006.201.19:20:58.91#ibcon#enter sib2, iclass 7, count 0 2006.201.19:20:58.91#ibcon#flushed, iclass 7, count 0 2006.201.19:20:58.91#ibcon#about to write, iclass 7, count 0 2006.201.19:20:58.91#ibcon#wrote, iclass 7, count 0 2006.201.19:20:58.91#ibcon#about to read 3, iclass 7, count 0 2006.201.19:20:58.93#ibcon#read 3, iclass 7, count 0 2006.201.19:20:58.93#ibcon#about to read 4, iclass 7, count 0 2006.201.19:20:58.93#ibcon#read 4, iclass 7, count 0 2006.201.19:20:58.93#ibcon#about to read 5, iclass 7, count 0 2006.201.19:20:58.93#ibcon#read 5, iclass 7, count 0 2006.201.19:20:58.93#ibcon#about to read 6, iclass 7, count 0 2006.201.19:20:58.93#ibcon#read 6, iclass 7, count 0 2006.201.19:20:58.93#ibcon#end of sib2, iclass 7, count 0 2006.201.19:20:58.93#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:20:58.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:20:58.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:20:58.93#ibcon#*before write, iclass 7, count 0 2006.201.19:20:58.93#ibcon#enter sib2, iclass 7, count 0 2006.201.19:20:58.93#ibcon#flushed, iclass 7, count 0 2006.201.19:20:58.93#ibcon#about to write, iclass 7, count 0 2006.201.19:20:58.93#ibcon#wrote, iclass 7, count 0 2006.201.19:20:58.93#ibcon#about to read 3, iclass 7, count 0 2006.201.19:20:58.98#ibcon#read 3, iclass 7, count 0 2006.201.19:20:58.98#ibcon#about to read 4, iclass 7, count 0 2006.201.19:20:58.98#ibcon#read 4, iclass 7, count 0 2006.201.19:20:58.98#ibcon#about to read 5, iclass 7, count 0 2006.201.19:20:58.98#ibcon#read 5, iclass 7, count 0 2006.201.19:20:58.98#ibcon#about to read 6, iclass 7, count 0 2006.201.19:20:58.98#ibcon#read 6, iclass 7, count 0 2006.201.19:20:58.98#ibcon#end of sib2, iclass 7, count 0 2006.201.19:20:58.98#ibcon#*after write, iclass 7, count 0 2006.201.19:20:58.98#ibcon#*before return 0, iclass 7, count 0 2006.201.19:20:58.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:58.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:20:58.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:20:58.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:20:58.98$vck44/vb=8,4 2006.201.19:20:58.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.19:20:58.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.19:20:58.98#ibcon#ireg 11 cls_cnt 2 2006.201.19:20:58.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:59.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:59.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:59.03#ibcon#enter wrdev, iclass 11, count 2 2006.201.19:20:59.03#ibcon#first serial, iclass 11, count 2 2006.201.19:20:59.03#ibcon#enter sib2, iclass 11, count 2 2006.201.19:20:59.03#ibcon#flushed, iclass 11, count 2 2006.201.19:20:59.03#ibcon#about to write, iclass 11, count 2 2006.201.19:20:59.03#ibcon#wrote, iclass 11, count 2 2006.201.19:20:59.03#ibcon#about to read 3, iclass 11, count 2 2006.201.19:20:59.05#ibcon#read 3, iclass 11, count 2 2006.201.19:20:59.05#ibcon#about to read 4, iclass 11, count 2 2006.201.19:20:59.05#ibcon#read 4, iclass 11, count 2 2006.201.19:20:59.05#ibcon#about to read 5, iclass 11, count 2 2006.201.19:20:59.05#ibcon#read 5, iclass 11, count 2 2006.201.19:20:59.05#ibcon#about to read 6, iclass 11, count 2 2006.201.19:20:59.05#ibcon#read 6, iclass 11, count 2 2006.201.19:20:59.05#ibcon#end of sib2, iclass 11, count 2 2006.201.19:20:59.05#ibcon#*mode == 0, iclass 11, count 2 2006.201.19:20:59.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.19:20:59.05#ibcon#[27=AT08-04\r\n] 2006.201.19:20:59.05#ibcon#*before write, iclass 11, count 2 2006.201.19:20:59.05#ibcon#enter sib2, iclass 11, count 2 2006.201.19:20:59.05#ibcon#flushed, iclass 11, count 2 2006.201.19:20:59.05#ibcon#about to write, iclass 11, count 2 2006.201.19:20:59.05#ibcon#wrote, iclass 11, count 2 2006.201.19:20:59.05#ibcon#about to read 3, iclass 11, count 2 2006.201.19:20:59.08#ibcon#read 3, iclass 11, count 2 2006.201.19:20:59.08#ibcon#about to read 4, iclass 11, count 2 2006.201.19:20:59.08#ibcon#read 4, iclass 11, count 2 2006.201.19:20:59.08#ibcon#about to read 5, iclass 11, count 2 2006.201.19:20:59.08#ibcon#read 5, iclass 11, count 2 2006.201.19:20:59.08#ibcon#about to read 6, iclass 11, count 2 2006.201.19:20:59.08#ibcon#read 6, iclass 11, count 2 2006.201.19:20:59.08#ibcon#end of sib2, iclass 11, count 2 2006.201.19:20:59.08#ibcon#*after write, iclass 11, count 2 2006.201.19:20:59.08#ibcon#*before return 0, iclass 11, count 2 2006.201.19:20:59.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:59.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:20:59.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.19:20:59.08#ibcon#ireg 7 cls_cnt 0 2006.201.19:20:59.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:59.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:59.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:59.20#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:20:59.20#ibcon#first serial, iclass 11, count 0 2006.201.19:20:59.20#ibcon#enter sib2, iclass 11, count 0 2006.201.19:20:59.20#ibcon#flushed, iclass 11, count 0 2006.201.19:20:59.20#ibcon#about to write, iclass 11, count 0 2006.201.19:20:59.20#ibcon#wrote, iclass 11, count 0 2006.201.19:20:59.20#ibcon#about to read 3, iclass 11, count 0 2006.201.19:20:59.22#ibcon#read 3, iclass 11, count 0 2006.201.19:20:59.22#ibcon#about to read 4, iclass 11, count 0 2006.201.19:20:59.22#ibcon#read 4, iclass 11, count 0 2006.201.19:20:59.22#ibcon#about to read 5, iclass 11, count 0 2006.201.19:20:59.22#ibcon#read 5, iclass 11, count 0 2006.201.19:20:59.22#ibcon#about to read 6, iclass 11, count 0 2006.201.19:20:59.22#ibcon#read 6, iclass 11, count 0 2006.201.19:20:59.22#ibcon#end of sib2, iclass 11, count 0 2006.201.19:20:59.22#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:20:59.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:20:59.22#ibcon#[27=USB\r\n] 2006.201.19:20:59.22#ibcon#*before write, iclass 11, count 0 2006.201.19:20:59.22#ibcon#enter sib2, iclass 11, count 0 2006.201.19:20:59.22#ibcon#flushed, iclass 11, count 0 2006.201.19:20:59.22#ibcon#about to write, iclass 11, count 0 2006.201.19:20:59.22#ibcon#wrote, iclass 11, count 0 2006.201.19:20:59.22#ibcon#about to read 3, iclass 11, count 0 2006.201.19:20:59.25#ibcon#read 3, iclass 11, count 0 2006.201.19:20:59.25#ibcon#about to read 4, iclass 11, count 0 2006.201.19:20:59.25#ibcon#read 4, iclass 11, count 0 2006.201.19:20:59.25#ibcon#about to read 5, iclass 11, count 0 2006.201.19:20:59.25#ibcon#read 5, iclass 11, count 0 2006.201.19:20:59.25#ibcon#about to read 6, iclass 11, count 0 2006.201.19:20:59.25#ibcon#read 6, iclass 11, count 0 2006.201.19:20:59.25#ibcon#end of sib2, iclass 11, count 0 2006.201.19:20:59.25#ibcon#*after write, iclass 11, count 0 2006.201.19:20:59.25#ibcon#*before return 0, iclass 11, count 0 2006.201.19:20:59.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:59.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:20:59.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:20:59.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:20:59.25$vck44/vabw=wide 2006.201.19:20:59.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.19:20:59.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.19:20:59.25#ibcon#ireg 8 cls_cnt 0 2006.201.19:20:59.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:59.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:59.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:59.25#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:20:59.25#ibcon#first serial, iclass 13, count 0 2006.201.19:20:59.25#ibcon#enter sib2, iclass 13, count 0 2006.201.19:20:59.25#ibcon#flushed, iclass 13, count 0 2006.201.19:20:59.25#ibcon#about to write, iclass 13, count 0 2006.201.19:20:59.25#ibcon#wrote, iclass 13, count 0 2006.201.19:20:59.25#ibcon#about to read 3, iclass 13, count 0 2006.201.19:20:59.27#ibcon#read 3, iclass 13, count 0 2006.201.19:20:59.27#ibcon#about to read 4, iclass 13, count 0 2006.201.19:20:59.27#ibcon#read 4, iclass 13, count 0 2006.201.19:20:59.27#ibcon#about to read 5, iclass 13, count 0 2006.201.19:20:59.27#ibcon#read 5, iclass 13, count 0 2006.201.19:20:59.27#ibcon#about to read 6, iclass 13, count 0 2006.201.19:20:59.27#ibcon#read 6, iclass 13, count 0 2006.201.19:20:59.27#ibcon#end of sib2, iclass 13, count 0 2006.201.19:20:59.27#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:20:59.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:20:59.27#ibcon#[25=BW32\r\n] 2006.201.19:20:59.27#ibcon#*before write, iclass 13, count 0 2006.201.19:20:59.27#ibcon#enter sib2, iclass 13, count 0 2006.201.19:20:59.27#ibcon#flushed, iclass 13, count 0 2006.201.19:20:59.27#ibcon#about to write, iclass 13, count 0 2006.201.19:20:59.27#ibcon#wrote, iclass 13, count 0 2006.201.19:20:59.27#ibcon#about to read 3, iclass 13, count 0 2006.201.19:20:59.30#ibcon#read 3, iclass 13, count 0 2006.201.19:20:59.30#ibcon#about to read 4, iclass 13, count 0 2006.201.19:20:59.30#ibcon#read 4, iclass 13, count 0 2006.201.19:20:59.30#ibcon#about to read 5, iclass 13, count 0 2006.201.19:20:59.30#ibcon#read 5, iclass 13, count 0 2006.201.19:20:59.30#ibcon#about to read 6, iclass 13, count 0 2006.201.19:20:59.30#ibcon#read 6, iclass 13, count 0 2006.201.19:20:59.30#ibcon#end of sib2, iclass 13, count 0 2006.201.19:20:59.30#ibcon#*after write, iclass 13, count 0 2006.201.19:20:59.30#ibcon#*before return 0, iclass 13, count 0 2006.201.19:20:59.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:59.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:20:59.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:20:59.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:20:59.30$vck44/vbbw=wide 2006.201.19:20:59.30#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.19:20:59.30#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.19:20:59.30#ibcon#ireg 8 cls_cnt 0 2006.201.19:20:59.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:20:59.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:20:59.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:20:59.37#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:20:59.37#ibcon#first serial, iclass 15, count 0 2006.201.19:20:59.37#ibcon#enter sib2, iclass 15, count 0 2006.201.19:20:59.37#ibcon#flushed, iclass 15, count 0 2006.201.19:20:59.37#ibcon#about to write, iclass 15, count 0 2006.201.19:20:59.37#ibcon#wrote, iclass 15, count 0 2006.201.19:20:59.37#ibcon#about to read 3, iclass 15, count 0 2006.201.19:20:59.39#ibcon#read 3, iclass 15, count 0 2006.201.19:20:59.39#ibcon#about to read 4, iclass 15, count 0 2006.201.19:20:59.39#ibcon#read 4, iclass 15, count 0 2006.201.19:20:59.39#ibcon#about to read 5, iclass 15, count 0 2006.201.19:20:59.39#ibcon#read 5, iclass 15, count 0 2006.201.19:20:59.39#ibcon#about to read 6, iclass 15, count 0 2006.201.19:20:59.39#ibcon#read 6, iclass 15, count 0 2006.201.19:20:59.39#ibcon#end of sib2, iclass 15, count 0 2006.201.19:20:59.39#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:20:59.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:20:59.39#ibcon#[27=BW32\r\n] 2006.201.19:20:59.39#ibcon#*before write, iclass 15, count 0 2006.201.19:20:59.39#ibcon#enter sib2, iclass 15, count 0 2006.201.19:20:59.39#ibcon#flushed, iclass 15, count 0 2006.201.19:20:59.39#ibcon#about to write, iclass 15, count 0 2006.201.19:20:59.39#ibcon#wrote, iclass 15, count 0 2006.201.19:20:59.39#ibcon#about to read 3, iclass 15, count 0 2006.201.19:20:59.42#ibcon#read 3, iclass 15, count 0 2006.201.19:20:59.42#ibcon#about to read 4, iclass 15, count 0 2006.201.19:20:59.42#ibcon#read 4, iclass 15, count 0 2006.201.19:20:59.42#ibcon#about to read 5, iclass 15, count 0 2006.201.19:20:59.42#ibcon#read 5, iclass 15, count 0 2006.201.19:20:59.42#ibcon#about to read 6, iclass 15, count 0 2006.201.19:20:59.42#ibcon#read 6, iclass 15, count 0 2006.201.19:20:59.42#ibcon#end of sib2, iclass 15, count 0 2006.201.19:20:59.42#ibcon#*after write, iclass 15, count 0 2006.201.19:20:59.42#ibcon#*before return 0, iclass 15, count 0 2006.201.19:20:59.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:20:59.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:20:59.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:20:59.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:20:59.42$setupk4/ifdk4 2006.201.19:20:59.42$ifdk4/lo= 2006.201.19:20:59.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:20:59.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:20:59.42$ifdk4/patch= 2006.201.19:20:59.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:20:59.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:20:59.42$setupk4/!*+20s 2006.201.19:21:08.56#abcon#<5=/03 0.9 2.4 20.491001002.5\r\n> 2006.201.19:21:08.58#abcon#{5=INTERFACE CLEAR} 2006.201.19:21:08.64#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:21:13.93$setupk4/"tpicd 2006.201.19:21:13.93$setupk4/echo=off 2006.201.19:21:13.93$setupk4/xlog=off 2006.201.19:21:13.93:!2006.201.19:23:11 2006.201.19:21:15.14#trakl#Source acquired 2006.201.19:21:17.14#flagr#flagr/antenna,acquired 2006.201.19:23:11.00:preob 2006.201.19:23:12.14/onsource/TRACKING 2006.201.19:23:12.14:!2006.201.19:23:21 2006.201.19:23:21.00:"tape 2006.201.19:23:21.00:"st=record 2006.201.19:23:21.00:data_valid=on 2006.201.19:23:21.00:midob 2006.201.19:23:21.14/onsource/TRACKING 2006.201.19:23:21.14/wx/20.49,1002.5,100 2006.201.19:23:21.21/cable/+6.4807E-03 2006.201.19:23:22.30/va/01,08,usb,yes,54,57 2006.201.19:23:22.30/va/02,07,usb,yes,58,59 2006.201.19:23:22.30/va/03,08,usb,yes,53,55 2006.201.19:23:22.30/va/04,07,usb,yes,60,63 2006.201.19:23:22.30/va/05,04,usb,yes,53,55 2006.201.19:23:22.30/va/06,05,usb,yes,54,54 2006.201.19:23:22.30/va/07,05,usb,yes,53,54 2006.201.19:23:22.30/va/08,04,usb,yes,52,61 2006.201.19:23:22.53/valo/01,524.99,yes,locked 2006.201.19:23:22.53/valo/02,534.99,yes,locked 2006.201.19:23:22.53/valo/03,564.99,yes,locked 2006.201.19:23:22.53/valo/04,624.99,yes,locked 2006.201.19:23:22.53/valo/05,734.99,yes,locked 2006.201.19:23:22.53/valo/06,814.99,yes,locked 2006.201.19:23:22.53/valo/07,864.99,yes,locked 2006.201.19:23:22.53/valo/08,884.99,yes,locked 2006.201.19:23:23.62/vb/01,04,usb,yes,31,29 2006.201.19:23:23.62/vb/02,05,usb,yes,30,30 2006.201.19:23:23.62/vb/03,04,usb,yes,31,34 2006.201.19:23:23.62/vb/04,05,usb,yes,31,30 2006.201.19:23:23.62/vb/05,04,usb,yes,28,30 2006.201.19:23:23.62/vb/06,04,usb,yes,32,28 2006.201.19:23:23.62/vb/07,04,usb,yes,32,32 2006.201.19:23:23.62/vb/08,04,usb,yes,29,33 2006.201.19:23:23.86/vblo/01,629.99,yes,locked 2006.201.19:23:23.86/vblo/02,634.99,yes,locked 2006.201.19:23:23.86/vblo/03,649.99,yes,locked 2006.201.19:23:23.86/vblo/04,679.99,yes,locked 2006.201.19:23:23.86/vblo/05,709.99,yes,locked 2006.201.19:23:23.86/vblo/06,719.99,yes,locked 2006.201.19:23:23.86/vblo/07,734.99,yes,locked 2006.201.19:23:23.86/vblo/08,744.99,yes,locked 2006.201.19:23:24.01/vabw/8 2006.201.19:23:24.16/vbbw/8 2006.201.19:23:24.25/xfe/off,on,15.2 2006.201.19:23:24.63/ifatt/23,28,28,28 2006.201.19:23:25.07/fmout-gps/S +4.50E-07 2006.201.19:23:25.11:!2006.201.19:25:21 2006.201.19:25:21.00:data_valid=off 2006.201.19:25:21.00:"et 2006.201.19:25:21.00:!+3s 2006.201.19:25:24.02:"tape 2006.201.19:25:24.02:postob 2006.201.19:25:24.20/cable/+6.4801E-03 2006.201.19:25:24.20/wx/20.49,1002.4,100 2006.201.19:25:24.28/fmout-gps/S +4.47E-07 2006.201.19:25:24.28:scan_name=201-1931,jd0607,250 2006.201.19:25:24.28:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.201.19:25:25.14#flagr#flagr/antenna,new-source 2006.201.19:25:25.14:checkk5 2006.201.19:25:25.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:25:25.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:25:26.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:25:26.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:25:27.02/chk_obsdata//k5ts1/T2011923??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.201.19:25:27.39/chk_obsdata//k5ts2/T2011923??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.201.19:25:27.76/chk_obsdata//k5ts3/T2011923??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.201.19:25:28.13/chk_obsdata//k5ts4/T2011923??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.201.19:25:28.82/k5log//k5ts1_log_newline 2006.201.19:25:29.54/k5log//k5ts2_log_newline 2006.201.19:25:30.22/k5log//k5ts3_log_newline 2006.201.19:25:30.90/k5log//k5ts4_log_newline 2006.201.19:25:30.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:25:30.93:setupk4=1 2006.201.19:25:30.93$setupk4/echo=on 2006.201.19:25:30.93$setupk4/pcalon 2006.201.19:25:30.93$pcalon/"no phase cal control is implemented here 2006.201.19:25:30.93$setupk4/"tpicd=stop 2006.201.19:25:30.93$setupk4/"rec=synch_on 2006.201.19:25:30.93$setupk4/"rec_mode=128 2006.201.19:25:30.93$setupk4/!* 2006.201.19:25:30.93$setupk4/recpk4 2006.201.19:25:30.93$recpk4/recpatch= 2006.201.19:25:30.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:25:30.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:25:30.93$setupk4/vck44 2006.201.19:25:30.93$vck44/valo=1,524.99 2006.201.19:25:30.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.19:25:30.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.19:25:30.93#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:30.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:30.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:30.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:30.93#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:25:30.93#ibcon#first serial, iclass 16, count 0 2006.201.19:25:30.93#ibcon#enter sib2, iclass 16, count 0 2006.201.19:25:30.93#ibcon#flushed, iclass 16, count 0 2006.201.19:25:30.93#ibcon#about to write, iclass 16, count 0 2006.201.19:25:30.93#ibcon#wrote, iclass 16, count 0 2006.201.19:25:30.93#ibcon#about to read 3, iclass 16, count 0 2006.201.19:25:30.95#ibcon#read 3, iclass 16, count 0 2006.201.19:25:30.95#ibcon#about to read 4, iclass 16, count 0 2006.201.19:25:30.95#ibcon#read 4, iclass 16, count 0 2006.201.19:25:30.95#ibcon#about to read 5, iclass 16, count 0 2006.201.19:25:30.95#ibcon#read 5, iclass 16, count 0 2006.201.19:25:30.95#ibcon#about to read 6, iclass 16, count 0 2006.201.19:25:30.95#ibcon#read 6, iclass 16, count 0 2006.201.19:25:30.95#ibcon#end of sib2, iclass 16, count 0 2006.201.19:25:30.95#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:25:30.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:25:30.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:25:30.95#ibcon#*before write, iclass 16, count 0 2006.201.19:25:30.95#ibcon#enter sib2, iclass 16, count 0 2006.201.19:25:30.95#ibcon#flushed, iclass 16, count 0 2006.201.19:25:30.95#ibcon#about to write, iclass 16, count 0 2006.201.19:25:30.95#ibcon#wrote, iclass 16, count 0 2006.201.19:25:30.95#ibcon#about to read 3, iclass 16, count 0 2006.201.19:25:31.00#ibcon#read 3, iclass 16, count 0 2006.201.19:25:31.00#ibcon#about to read 4, iclass 16, count 0 2006.201.19:25:31.00#ibcon#read 4, iclass 16, count 0 2006.201.19:25:31.00#ibcon#about to read 5, iclass 16, count 0 2006.201.19:25:31.00#ibcon#read 5, iclass 16, count 0 2006.201.19:25:31.00#ibcon#about to read 6, iclass 16, count 0 2006.201.19:25:31.00#ibcon#read 6, iclass 16, count 0 2006.201.19:25:31.00#ibcon#end of sib2, iclass 16, count 0 2006.201.19:25:31.00#ibcon#*after write, iclass 16, count 0 2006.201.19:25:31.00#ibcon#*before return 0, iclass 16, count 0 2006.201.19:25:31.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:31.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:31.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:25:31.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:25:31.00$vck44/va=1,8 2006.201.19:25:31.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.19:25:31.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.19:25:31.00#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:31.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:31.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:31.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:31.00#ibcon#enter wrdev, iclass 18, count 2 2006.201.19:25:31.00#ibcon#first serial, iclass 18, count 2 2006.201.19:25:31.00#ibcon#enter sib2, iclass 18, count 2 2006.201.19:25:31.00#ibcon#flushed, iclass 18, count 2 2006.201.19:25:31.00#ibcon#about to write, iclass 18, count 2 2006.201.19:25:31.00#ibcon#wrote, iclass 18, count 2 2006.201.19:25:31.00#ibcon#about to read 3, iclass 18, count 2 2006.201.19:25:31.02#ibcon#read 3, iclass 18, count 2 2006.201.19:25:31.02#ibcon#about to read 4, iclass 18, count 2 2006.201.19:25:31.02#ibcon#read 4, iclass 18, count 2 2006.201.19:25:31.02#ibcon#about to read 5, iclass 18, count 2 2006.201.19:25:31.02#ibcon#read 5, iclass 18, count 2 2006.201.19:25:31.02#ibcon#about to read 6, iclass 18, count 2 2006.201.19:25:31.02#ibcon#read 6, iclass 18, count 2 2006.201.19:25:31.02#ibcon#end of sib2, iclass 18, count 2 2006.201.19:25:31.02#ibcon#*mode == 0, iclass 18, count 2 2006.201.19:25:31.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.19:25:31.02#ibcon#[25=AT01-08\r\n] 2006.201.19:25:31.02#ibcon#*before write, iclass 18, count 2 2006.201.19:25:31.02#ibcon#enter sib2, iclass 18, count 2 2006.201.19:25:31.02#ibcon#flushed, iclass 18, count 2 2006.201.19:25:31.02#ibcon#about to write, iclass 18, count 2 2006.201.19:25:31.02#ibcon#wrote, iclass 18, count 2 2006.201.19:25:31.02#ibcon#about to read 3, iclass 18, count 2 2006.201.19:25:31.05#ibcon#read 3, iclass 18, count 2 2006.201.19:25:31.05#ibcon#about to read 4, iclass 18, count 2 2006.201.19:25:31.05#ibcon#read 4, iclass 18, count 2 2006.201.19:25:31.05#ibcon#about to read 5, iclass 18, count 2 2006.201.19:25:31.05#ibcon#read 5, iclass 18, count 2 2006.201.19:25:31.05#ibcon#about to read 6, iclass 18, count 2 2006.201.19:25:31.05#ibcon#read 6, iclass 18, count 2 2006.201.19:25:31.05#ibcon#end of sib2, iclass 18, count 2 2006.201.19:25:31.05#ibcon#*after write, iclass 18, count 2 2006.201.19:25:31.05#ibcon#*before return 0, iclass 18, count 2 2006.201.19:25:31.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:31.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:31.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.19:25:31.05#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:31.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:31.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:31.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:31.17#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:25:31.17#ibcon#first serial, iclass 18, count 0 2006.201.19:25:31.17#ibcon#enter sib2, iclass 18, count 0 2006.201.19:25:31.17#ibcon#flushed, iclass 18, count 0 2006.201.19:25:31.17#ibcon#about to write, iclass 18, count 0 2006.201.19:25:31.17#ibcon#wrote, iclass 18, count 0 2006.201.19:25:31.17#ibcon#about to read 3, iclass 18, count 0 2006.201.19:25:31.19#ibcon#read 3, iclass 18, count 0 2006.201.19:25:31.19#ibcon#about to read 4, iclass 18, count 0 2006.201.19:25:31.19#ibcon#read 4, iclass 18, count 0 2006.201.19:25:31.19#ibcon#about to read 5, iclass 18, count 0 2006.201.19:25:31.19#ibcon#read 5, iclass 18, count 0 2006.201.19:25:31.19#ibcon#about to read 6, iclass 18, count 0 2006.201.19:25:31.19#ibcon#read 6, iclass 18, count 0 2006.201.19:25:31.19#ibcon#end of sib2, iclass 18, count 0 2006.201.19:25:31.19#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:25:31.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:25:31.19#ibcon#[25=USB\r\n] 2006.201.19:25:31.19#ibcon#*before write, iclass 18, count 0 2006.201.19:25:31.19#ibcon#enter sib2, iclass 18, count 0 2006.201.19:25:31.19#ibcon#flushed, iclass 18, count 0 2006.201.19:25:31.19#ibcon#about to write, iclass 18, count 0 2006.201.19:25:31.19#ibcon#wrote, iclass 18, count 0 2006.201.19:25:31.19#ibcon#about to read 3, iclass 18, count 0 2006.201.19:25:31.22#ibcon#read 3, iclass 18, count 0 2006.201.19:25:31.22#ibcon#about to read 4, iclass 18, count 0 2006.201.19:25:31.22#ibcon#read 4, iclass 18, count 0 2006.201.19:25:31.22#ibcon#about to read 5, iclass 18, count 0 2006.201.19:25:31.22#ibcon#read 5, iclass 18, count 0 2006.201.19:25:31.22#ibcon#about to read 6, iclass 18, count 0 2006.201.19:25:31.22#ibcon#read 6, iclass 18, count 0 2006.201.19:25:31.22#ibcon#end of sib2, iclass 18, count 0 2006.201.19:25:31.22#ibcon#*after write, iclass 18, count 0 2006.201.19:25:31.22#ibcon#*before return 0, iclass 18, count 0 2006.201.19:25:31.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:31.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:31.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:25:31.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:25:31.22$vck44/valo=2,534.99 2006.201.19:25:31.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.19:25:31.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.19:25:31.22#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:31.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:31.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:31.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:31.22#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:25:31.22#ibcon#first serial, iclass 20, count 0 2006.201.19:25:31.22#ibcon#enter sib2, iclass 20, count 0 2006.201.19:25:31.22#ibcon#flushed, iclass 20, count 0 2006.201.19:25:31.22#ibcon#about to write, iclass 20, count 0 2006.201.19:25:31.22#ibcon#wrote, iclass 20, count 0 2006.201.19:25:31.22#ibcon#about to read 3, iclass 20, count 0 2006.201.19:25:31.24#ibcon#read 3, iclass 20, count 0 2006.201.19:25:31.24#ibcon#about to read 4, iclass 20, count 0 2006.201.19:25:31.24#ibcon#read 4, iclass 20, count 0 2006.201.19:25:31.24#ibcon#about to read 5, iclass 20, count 0 2006.201.19:25:31.24#ibcon#read 5, iclass 20, count 0 2006.201.19:25:31.24#ibcon#about to read 6, iclass 20, count 0 2006.201.19:25:31.24#ibcon#read 6, iclass 20, count 0 2006.201.19:25:31.24#ibcon#end of sib2, iclass 20, count 0 2006.201.19:25:31.24#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:25:31.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:25:31.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:25:31.24#ibcon#*before write, iclass 20, count 0 2006.201.19:25:31.24#ibcon#enter sib2, iclass 20, count 0 2006.201.19:25:31.24#ibcon#flushed, iclass 20, count 0 2006.201.19:25:31.24#ibcon#about to write, iclass 20, count 0 2006.201.19:25:31.24#ibcon#wrote, iclass 20, count 0 2006.201.19:25:31.24#ibcon#about to read 3, iclass 20, count 0 2006.201.19:25:31.28#ibcon#read 3, iclass 20, count 0 2006.201.19:25:31.28#ibcon#about to read 4, iclass 20, count 0 2006.201.19:25:31.28#ibcon#read 4, iclass 20, count 0 2006.201.19:25:31.28#ibcon#about to read 5, iclass 20, count 0 2006.201.19:25:31.28#ibcon#read 5, iclass 20, count 0 2006.201.19:25:31.28#ibcon#about to read 6, iclass 20, count 0 2006.201.19:25:31.28#ibcon#read 6, iclass 20, count 0 2006.201.19:25:31.28#ibcon#end of sib2, iclass 20, count 0 2006.201.19:25:31.28#ibcon#*after write, iclass 20, count 0 2006.201.19:25:31.28#ibcon#*before return 0, iclass 20, count 0 2006.201.19:25:31.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:31.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:31.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:25:31.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:25:31.28$vck44/va=2,7 2006.201.19:25:31.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.19:25:31.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.19:25:31.28#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:31.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:31.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:31.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:31.34#ibcon#enter wrdev, iclass 22, count 2 2006.201.19:25:31.34#ibcon#first serial, iclass 22, count 2 2006.201.19:25:31.34#ibcon#enter sib2, iclass 22, count 2 2006.201.19:25:31.34#ibcon#flushed, iclass 22, count 2 2006.201.19:25:31.34#ibcon#about to write, iclass 22, count 2 2006.201.19:25:31.34#ibcon#wrote, iclass 22, count 2 2006.201.19:25:31.34#ibcon#about to read 3, iclass 22, count 2 2006.201.19:25:31.36#ibcon#read 3, iclass 22, count 2 2006.201.19:25:31.36#ibcon#about to read 4, iclass 22, count 2 2006.201.19:25:31.36#ibcon#read 4, iclass 22, count 2 2006.201.19:25:31.36#ibcon#about to read 5, iclass 22, count 2 2006.201.19:25:31.36#ibcon#read 5, iclass 22, count 2 2006.201.19:25:31.36#ibcon#about to read 6, iclass 22, count 2 2006.201.19:25:31.36#ibcon#read 6, iclass 22, count 2 2006.201.19:25:31.36#ibcon#end of sib2, iclass 22, count 2 2006.201.19:25:31.36#ibcon#*mode == 0, iclass 22, count 2 2006.201.19:25:31.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.19:25:31.36#ibcon#[25=AT02-07\r\n] 2006.201.19:25:31.36#ibcon#*before write, iclass 22, count 2 2006.201.19:25:31.36#ibcon#enter sib2, iclass 22, count 2 2006.201.19:25:31.36#ibcon#flushed, iclass 22, count 2 2006.201.19:25:31.36#ibcon#about to write, iclass 22, count 2 2006.201.19:25:31.36#ibcon#wrote, iclass 22, count 2 2006.201.19:25:31.36#ibcon#about to read 3, iclass 22, count 2 2006.201.19:25:31.39#ibcon#read 3, iclass 22, count 2 2006.201.19:25:31.39#ibcon#about to read 4, iclass 22, count 2 2006.201.19:25:31.39#ibcon#read 4, iclass 22, count 2 2006.201.19:25:31.39#ibcon#about to read 5, iclass 22, count 2 2006.201.19:25:31.39#ibcon#read 5, iclass 22, count 2 2006.201.19:25:31.39#ibcon#about to read 6, iclass 22, count 2 2006.201.19:25:31.39#ibcon#read 6, iclass 22, count 2 2006.201.19:25:31.39#ibcon#end of sib2, iclass 22, count 2 2006.201.19:25:31.39#ibcon#*after write, iclass 22, count 2 2006.201.19:25:31.39#ibcon#*before return 0, iclass 22, count 2 2006.201.19:25:31.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:31.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:31.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.19:25:31.39#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:31.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:31.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:31.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:31.51#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:25:31.51#ibcon#first serial, iclass 22, count 0 2006.201.19:25:31.51#ibcon#enter sib2, iclass 22, count 0 2006.201.19:25:31.51#ibcon#flushed, iclass 22, count 0 2006.201.19:25:31.51#ibcon#about to write, iclass 22, count 0 2006.201.19:25:31.51#ibcon#wrote, iclass 22, count 0 2006.201.19:25:31.51#ibcon#about to read 3, iclass 22, count 0 2006.201.19:25:31.53#ibcon#read 3, iclass 22, count 0 2006.201.19:25:31.53#ibcon#about to read 4, iclass 22, count 0 2006.201.19:25:31.53#ibcon#read 4, iclass 22, count 0 2006.201.19:25:31.53#ibcon#about to read 5, iclass 22, count 0 2006.201.19:25:31.53#ibcon#read 5, iclass 22, count 0 2006.201.19:25:31.53#ibcon#about to read 6, iclass 22, count 0 2006.201.19:25:31.53#ibcon#read 6, iclass 22, count 0 2006.201.19:25:31.53#ibcon#end of sib2, iclass 22, count 0 2006.201.19:25:31.53#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:25:31.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:25:31.53#ibcon#[25=USB\r\n] 2006.201.19:25:31.53#ibcon#*before write, iclass 22, count 0 2006.201.19:25:31.53#ibcon#enter sib2, iclass 22, count 0 2006.201.19:25:31.53#ibcon#flushed, iclass 22, count 0 2006.201.19:25:31.53#ibcon#about to write, iclass 22, count 0 2006.201.19:25:31.53#ibcon#wrote, iclass 22, count 0 2006.201.19:25:31.53#ibcon#about to read 3, iclass 22, count 0 2006.201.19:25:31.56#ibcon#read 3, iclass 22, count 0 2006.201.19:25:31.56#ibcon#about to read 4, iclass 22, count 0 2006.201.19:25:31.56#ibcon#read 4, iclass 22, count 0 2006.201.19:25:31.56#ibcon#about to read 5, iclass 22, count 0 2006.201.19:25:31.56#ibcon#read 5, iclass 22, count 0 2006.201.19:25:31.56#ibcon#about to read 6, iclass 22, count 0 2006.201.19:25:31.56#ibcon#read 6, iclass 22, count 0 2006.201.19:25:31.56#ibcon#end of sib2, iclass 22, count 0 2006.201.19:25:31.56#ibcon#*after write, iclass 22, count 0 2006.201.19:25:31.56#ibcon#*before return 0, iclass 22, count 0 2006.201.19:25:31.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:31.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:31.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:25:31.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:25:31.56$vck44/valo=3,564.99 2006.201.19:25:31.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.19:25:31.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.19:25:31.56#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:31.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:31.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:31.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:31.56#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:25:31.56#ibcon#first serial, iclass 24, count 0 2006.201.19:25:31.56#ibcon#enter sib2, iclass 24, count 0 2006.201.19:25:31.56#ibcon#flushed, iclass 24, count 0 2006.201.19:25:31.56#ibcon#about to write, iclass 24, count 0 2006.201.19:25:31.56#ibcon#wrote, iclass 24, count 0 2006.201.19:25:31.56#ibcon#about to read 3, iclass 24, count 0 2006.201.19:25:31.58#ibcon#read 3, iclass 24, count 0 2006.201.19:25:31.58#ibcon#about to read 4, iclass 24, count 0 2006.201.19:25:31.58#ibcon#read 4, iclass 24, count 0 2006.201.19:25:31.58#ibcon#about to read 5, iclass 24, count 0 2006.201.19:25:31.58#ibcon#read 5, iclass 24, count 0 2006.201.19:25:31.58#ibcon#about to read 6, iclass 24, count 0 2006.201.19:25:31.58#ibcon#read 6, iclass 24, count 0 2006.201.19:25:31.58#ibcon#end of sib2, iclass 24, count 0 2006.201.19:25:31.58#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:25:31.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:25:31.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:25:31.58#ibcon#*before write, iclass 24, count 0 2006.201.19:25:31.58#ibcon#enter sib2, iclass 24, count 0 2006.201.19:25:31.58#ibcon#flushed, iclass 24, count 0 2006.201.19:25:31.58#ibcon#about to write, iclass 24, count 0 2006.201.19:25:31.58#ibcon#wrote, iclass 24, count 0 2006.201.19:25:31.58#ibcon#about to read 3, iclass 24, count 0 2006.201.19:25:31.63#ibcon#read 3, iclass 24, count 0 2006.201.19:25:31.63#ibcon#about to read 4, iclass 24, count 0 2006.201.19:25:31.63#ibcon#read 4, iclass 24, count 0 2006.201.19:25:31.63#ibcon#about to read 5, iclass 24, count 0 2006.201.19:25:31.63#ibcon#read 5, iclass 24, count 0 2006.201.19:25:31.63#ibcon#about to read 6, iclass 24, count 0 2006.201.19:25:31.63#ibcon#read 6, iclass 24, count 0 2006.201.19:25:31.63#ibcon#end of sib2, iclass 24, count 0 2006.201.19:25:31.63#ibcon#*after write, iclass 24, count 0 2006.201.19:25:31.63#ibcon#*before return 0, iclass 24, count 0 2006.201.19:25:31.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:31.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:31.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:25:31.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:25:31.63$vck44/va=3,8 2006.201.19:25:31.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.19:25:31.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.19:25:31.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:31.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:31.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:31.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:31.68#ibcon#enter wrdev, iclass 26, count 2 2006.201.19:25:31.68#ibcon#first serial, iclass 26, count 2 2006.201.19:25:31.68#ibcon#enter sib2, iclass 26, count 2 2006.201.19:25:31.68#ibcon#flushed, iclass 26, count 2 2006.201.19:25:31.68#ibcon#about to write, iclass 26, count 2 2006.201.19:25:31.68#ibcon#wrote, iclass 26, count 2 2006.201.19:25:31.68#ibcon#about to read 3, iclass 26, count 2 2006.201.19:25:31.70#ibcon#read 3, iclass 26, count 2 2006.201.19:25:31.70#ibcon#about to read 4, iclass 26, count 2 2006.201.19:25:31.70#ibcon#read 4, iclass 26, count 2 2006.201.19:25:31.70#ibcon#about to read 5, iclass 26, count 2 2006.201.19:25:31.70#ibcon#read 5, iclass 26, count 2 2006.201.19:25:31.70#ibcon#about to read 6, iclass 26, count 2 2006.201.19:25:31.70#ibcon#read 6, iclass 26, count 2 2006.201.19:25:31.70#ibcon#end of sib2, iclass 26, count 2 2006.201.19:25:31.70#ibcon#*mode == 0, iclass 26, count 2 2006.201.19:25:31.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.19:25:31.70#ibcon#[25=AT03-08\r\n] 2006.201.19:25:31.70#ibcon#*before write, iclass 26, count 2 2006.201.19:25:31.70#ibcon#enter sib2, iclass 26, count 2 2006.201.19:25:31.70#ibcon#flushed, iclass 26, count 2 2006.201.19:25:31.70#ibcon#about to write, iclass 26, count 2 2006.201.19:25:31.70#ibcon#wrote, iclass 26, count 2 2006.201.19:25:31.70#ibcon#about to read 3, iclass 26, count 2 2006.201.19:25:31.73#ibcon#read 3, iclass 26, count 2 2006.201.19:25:31.73#ibcon#about to read 4, iclass 26, count 2 2006.201.19:25:31.73#ibcon#read 4, iclass 26, count 2 2006.201.19:25:31.73#ibcon#about to read 5, iclass 26, count 2 2006.201.19:25:31.73#ibcon#read 5, iclass 26, count 2 2006.201.19:25:31.73#ibcon#about to read 6, iclass 26, count 2 2006.201.19:25:31.73#ibcon#read 6, iclass 26, count 2 2006.201.19:25:31.73#ibcon#end of sib2, iclass 26, count 2 2006.201.19:25:31.73#ibcon#*after write, iclass 26, count 2 2006.201.19:25:31.73#ibcon#*before return 0, iclass 26, count 2 2006.201.19:25:31.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:31.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:31.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.19:25:31.73#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:31.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:31.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:31.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:31.85#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:25:31.85#ibcon#first serial, iclass 26, count 0 2006.201.19:25:31.85#ibcon#enter sib2, iclass 26, count 0 2006.201.19:25:31.85#ibcon#flushed, iclass 26, count 0 2006.201.19:25:31.85#ibcon#about to write, iclass 26, count 0 2006.201.19:25:31.85#ibcon#wrote, iclass 26, count 0 2006.201.19:25:31.85#ibcon#about to read 3, iclass 26, count 0 2006.201.19:25:31.87#ibcon#read 3, iclass 26, count 0 2006.201.19:25:31.87#ibcon#about to read 4, iclass 26, count 0 2006.201.19:25:31.87#ibcon#read 4, iclass 26, count 0 2006.201.19:25:31.87#ibcon#about to read 5, iclass 26, count 0 2006.201.19:25:31.87#ibcon#read 5, iclass 26, count 0 2006.201.19:25:31.87#ibcon#about to read 6, iclass 26, count 0 2006.201.19:25:31.87#ibcon#read 6, iclass 26, count 0 2006.201.19:25:31.87#ibcon#end of sib2, iclass 26, count 0 2006.201.19:25:31.87#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:25:31.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:25:31.87#ibcon#[25=USB\r\n] 2006.201.19:25:31.87#ibcon#*before write, iclass 26, count 0 2006.201.19:25:31.87#ibcon#enter sib2, iclass 26, count 0 2006.201.19:25:31.87#ibcon#flushed, iclass 26, count 0 2006.201.19:25:31.87#ibcon#about to write, iclass 26, count 0 2006.201.19:25:31.87#ibcon#wrote, iclass 26, count 0 2006.201.19:25:31.87#ibcon#about to read 3, iclass 26, count 0 2006.201.19:25:31.90#ibcon#read 3, iclass 26, count 0 2006.201.19:25:31.90#ibcon#about to read 4, iclass 26, count 0 2006.201.19:25:31.90#ibcon#read 4, iclass 26, count 0 2006.201.19:25:31.90#ibcon#about to read 5, iclass 26, count 0 2006.201.19:25:31.90#ibcon#read 5, iclass 26, count 0 2006.201.19:25:31.90#ibcon#about to read 6, iclass 26, count 0 2006.201.19:25:31.90#ibcon#read 6, iclass 26, count 0 2006.201.19:25:31.90#ibcon#end of sib2, iclass 26, count 0 2006.201.19:25:31.90#ibcon#*after write, iclass 26, count 0 2006.201.19:25:31.90#ibcon#*before return 0, iclass 26, count 0 2006.201.19:25:31.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:31.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:31.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:25:31.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:25:31.90$vck44/valo=4,624.99 2006.201.19:25:31.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.19:25:31.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.19:25:31.90#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:31.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:31.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:31.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:31.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:25:31.90#ibcon#first serial, iclass 28, count 0 2006.201.19:25:31.90#ibcon#enter sib2, iclass 28, count 0 2006.201.19:25:31.90#ibcon#flushed, iclass 28, count 0 2006.201.19:25:31.90#ibcon#about to write, iclass 28, count 0 2006.201.19:25:31.90#ibcon#wrote, iclass 28, count 0 2006.201.19:25:31.90#ibcon#about to read 3, iclass 28, count 0 2006.201.19:25:31.92#ibcon#read 3, iclass 28, count 0 2006.201.19:25:31.92#ibcon#about to read 4, iclass 28, count 0 2006.201.19:25:31.92#ibcon#read 4, iclass 28, count 0 2006.201.19:25:31.92#ibcon#about to read 5, iclass 28, count 0 2006.201.19:25:31.92#ibcon#read 5, iclass 28, count 0 2006.201.19:25:31.92#ibcon#about to read 6, iclass 28, count 0 2006.201.19:25:31.92#ibcon#read 6, iclass 28, count 0 2006.201.19:25:31.92#ibcon#end of sib2, iclass 28, count 0 2006.201.19:25:31.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:25:31.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:25:31.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:25:31.92#ibcon#*before write, iclass 28, count 0 2006.201.19:25:31.92#ibcon#enter sib2, iclass 28, count 0 2006.201.19:25:31.92#ibcon#flushed, iclass 28, count 0 2006.201.19:25:31.92#ibcon#about to write, iclass 28, count 0 2006.201.19:25:31.92#ibcon#wrote, iclass 28, count 0 2006.201.19:25:31.92#ibcon#about to read 3, iclass 28, count 0 2006.201.19:25:31.96#ibcon#read 3, iclass 28, count 0 2006.201.19:25:31.96#ibcon#about to read 4, iclass 28, count 0 2006.201.19:25:31.96#ibcon#read 4, iclass 28, count 0 2006.201.19:25:31.96#ibcon#about to read 5, iclass 28, count 0 2006.201.19:25:31.96#ibcon#read 5, iclass 28, count 0 2006.201.19:25:31.96#ibcon#about to read 6, iclass 28, count 0 2006.201.19:25:31.96#ibcon#read 6, iclass 28, count 0 2006.201.19:25:31.96#ibcon#end of sib2, iclass 28, count 0 2006.201.19:25:31.96#ibcon#*after write, iclass 28, count 0 2006.201.19:25:31.96#ibcon#*before return 0, iclass 28, count 0 2006.201.19:25:31.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:31.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:31.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:25:31.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:25:31.96$vck44/va=4,7 2006.201.19:25:31.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.19:25:31.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.19:25:31.96#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:31.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:32.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:32.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:32.02#ibcon#enter wrdev, iclass 30, count 2 2006.201.19:25:32.02#ibcon#first serial, iclass 30, count 2 2006.201.19:25:32.02#ibcon#enter sib2, iclass 30, count 2 2006.201.19:25:32.02#ibcon#flushed, iclass 30, count 2 2006.201.19:25:32.02#ibcon#about to write, iclass 30, count 2 2006.201.19:25:32.02#ibcon#wrote, iclass 30, count 2 2006.201.19:25:32.02#ibcon#about to read 3, iclass 30, count 2 2006.201.19:25:32.04#ibcon#read 3, iclass 30, count 2 2006.201.19:25:32.04#ibcon#about to read 4, iclass 30, count 2 2006.201.19:25:32.04#ibcon#read 4, iclass 30, count 2 2006.201.19:25:32.04#ibcon#about to read 5, iclass 30, count 2 2006.201.19:25:32.04#ibcon#read 5, iclass 30, count 2 2006.201.19:25:32.04#ibcon#about to read 6, iclass 30, count 2 2006.201.19:25:32.04#ibcon#read 6, iclass 30, count 2 2006.201.19:25:32.04#ibcon#end of sib2, iclass 30, count 2 2006.201.19:25:32.04#ibcon#*mode == 0, iclass 30, count 2 2006.201.19:25:32.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.19:25:32.04#ibcon#[25=AT04-07\r\n] 2006.201.19:25:32.04#ibcon#*before write, iclass 30, count 2 2006.201.19:25:32.04#ibcon#enter sib2, iclass 30, count 2 2006.201.19:25:32.04#ibcon#flushed, iclass 30, count 2 2006.201.19:25:32.04#ibcon#about to write, iclass 30, count 2 2006.201.19:25:32.04#ibcon#wrote, iclass 30, count 2 2006.201.19:25:32.04#ibcon#about to read 3, iclass 30, count 2 2006.201.19:25:32.07#ibcon#read 3, iclass 30, count 2 2006.201.19:25:32.07#ibcon#about to read 4, iclass 30, count 2 2006.201.19:25:32.07#ibcon#read 4, iclass 30, count 2 2006.201.19:25:32.07#ibcon#about to read 5, iclass 30, count 2 2006.201.19:25:32.07#ibcon#read 5, iclass 30, count 2 2006.201.19:25:32.07#ibcon#about to read 6, iclass 30, count 2 2006.201.19:25:32.07#ibcon#read 6, iclass 30, count 2 2006.201.19:25:32.07#ibcon#end of sib2, iclass 30, count 2 2006.201.19:25:32.07#ibcon#*after write, iclass 30, count 2 2006.201.19:25:32.07#ibcon#*before return 0, iclass 30, count 2 2006.201.19:25:32.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:32.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:32.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.19:25:32.07#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:32.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:32.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:32.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:32.19#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:25:32.19#ibcon#first serial, iclass 30, count 0 2006.201.19:25:32.19#ibcon#enter sib2, iclass 30, count 0 2006.201.19:25:32.19#ibcon#flushed, iclass 30, count 0 2006.201.19:25:32.19#ibcon#about to write, iclass 30, count 0 2006.201.19:25:32.19#ibcon#wrote, iclass 30, count 0 2006.201.19:25:32.19#ibcon#about to read 3, iclass 30, count 0 2006.201.19:25:32.21#ibcon#read 3, iclass 30, count 0 2006.201.19:25:32.21#ibcon#about to read 4, iclass 30, count 0 2006.201.19:25:32.21#ibcon#read 4, iclass 30, count 0 2006.201.19:25:32.21#ibcon#about to read 5, iclass 30, count 0 2006.201.19:25:32.21#ibcon#read 5, iclass 30, count 0 2006.201.19:25:32.21#ibcon#about to read 6, iclass 30, count 0 2006.201.19:25:32.21#ibcon#read 6, iclass 30, count 0 2006.201.19:25:32.21#ibcon#end of sib2, iclass 30, count 0 2006.201.19:25:32.21#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:25:32.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:25:32.21#ibcon#[25=USB\r\n] 2006.201.19:25:32.21#ibcon#*before write, iclass 30, count 0 2006.201.19:25:32.21#ibcon#enter sib2, iclass 30, count 0 2006.201.19:25:32.21#ibcon#flushed, iclass 30, count 0 2006.201.19:25:32.21#ibcon#about to write, iclass 30, count 0 2006.201.19:25:32.21#ibcon#wrote, iclass 30, count 0 2006.201.19:25:32.21#ibcon#about to read 3, iclass 30, count 0 2006.201.19:25:32.24#ibcon#read 3, iclass 30, count 0 2006.201.19:25:32.24#ibcon#about to read 4, iclass 30, count 0 2006.201.19:25:32.24#ibcon#read 4, iclass 30, count 0 2006.201.19:25:32.24#ibcon#about to read 5, iclass 30, count 0 2006.201.19:25:32.24#ibcon#read 5, iclass 30, count 0 2006.201.19:25:32.24#ibcon#about to read 6, iclass 30, count 0 2006.201.19:25:32.24#ibcon#read 6, iclass 30, count 0 2006.201.19:25:32.24#ibcon#end of sib2, iclass 30, count 0 2006.201.19:25:32.24#ibcon#*after write, iclass 30, count 0 2006.201.19:25:32.24#ibcon#*before return 0, iclass 30, count 0 2006.201.19:25:32.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:32.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:32.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:25:32.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:25:32.24$vck44/valo=5,734.99 2006.201.19:25:32.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.19:25:32.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.19:25:32.24#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:32.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:32.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:32.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:32.24#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:25:32.24#ibcon#first serial, iclass 32, count 0 2006.201.19:25:32.24#ibcon#enter sib2, iclass 32, count 0 2006.201.19:25:32.24#ibcon#flushed, iclass 32, count 0 2006.201.19:25:32.24#ibcon#about to write, iclass 32, count 0 2006.201.19:25:32.24#ibcon#wrote, iclass 32, count 0 2006.201.19:25:32.24#ibcon#about to read 3, iclass 32, count 0 2006.201.19:25:32.26#ibcon#read 3, iclass 32, count 0 2006.201.19:25:32.26#ibcon#about to read 4, iclass 32, count 0 2006.201.19:25:32.26#ibcon#read 4, iclass 32, count 0 2006.201.19:25:32.26#ibcon#about to read 5, iclass 32, count 0 2006.201.19:25:32.26#ibcon#read 5, iclass 32, count 0 2006.201.19:25:32.26#ibcon#about to read 6, iclass 32, count 0 2006.201.19:25:32.26#ibcon#read 6, iclass 32, count 0 2006.201.19:25:32.26#ibcon#end of sib2, iclass 32, count 0 2006.201.19:25:32.26#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:25:32.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:25:32.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:25:32.26#ibcon#*before write, iclass 32, count 0 2006.201.19:25:32.26#ibcon#enter sib2, iclass 32, count 0 2006.201.19:25:32.26#ibcon#flushed, iclass 32, count 0 2006.201.19:25:32.26#ibcon#about to write, iclass 32, count 0 2006.201.19:25:32.26#ibcon#wrote, iclass 32, count 0 2006.201.19:25:32.26#ibcon#about to read 3, iclass 32, count 0 2006.201.19:25:32.30#ibcon#read 3, iclass 32, count 0 2006.201.19:25:32.30#ibcon#about to read 4, iclass 32, count 0 2006.201.19:25:32.30#ibcon#read 4, iclass 32, count 0 2006.201.19:25:32.30#ibcon#about to read 5, iclass 32, count 0 2006.201.19:25:32.30#ibcon#read 5, iclass 32, count 0 2006.201.19:25:32.30#ibcon#about to read 6, iclass 32, count 0 2006.201.19:25:32.30#ibcon#read 6, iclass 32, count 0 2006.201.19:25:32.30#ibcon#end of sib2, iclass 32, count 0 2006.201.19:25:32.30#ibcon#*after write, iclass 32, count 0 2006.201.19:25:32.30#ibcon#*before return 0, iclass 32, count 0 2006.201.19:25:32.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:32.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:32.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:25:32.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:25:32.30$vck44/va=5,4 2006.201.19:25:32.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.19:25:32.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.19:25:32.30#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:32.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:32.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:32.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:32.36#ibcon#enter wrdev, iclass 34, count 2 2006.201.19:25:32.36#ibcon#first serial, iclass 34, count 2 2006.201.19:25:32.36#ibcon#enter sib2, iclass 34, count 2 2006.201.19:25:32.36#ibcon#flushed, iclass 34, count 2 2006.201.19:25:32.36#ibcon#about to write, iclass 34, count 2 2006.201.19:25:32.36#ibcon#wrote, iclass 34, count 2 2006.201.19:25:32.36#ibcon#about to read 3, iclass 34, count 2 2006.201.19:25:32.38#ibcon#read 3, iclass 34, count 2 2006.201.19:25:32.38#ibcon#about to read 4, iclass 34, count 2 2006.201.19:25:32.38#ibcon#read 4, iclass 34, count 2 2006.201.19:25:32.38#ibcon#about to read 5, iclass 34, count 2 2006.201.19:25:32.38#ibcon#read 5, iclass 34, count 2 2006.201.19:25:32.38#ibcon#about to read 6, iclass 34, count 2 2006.201.19:25:32.38#ibcon#read 6, iclass 34, count 2 2006.201.19:25:32.38#ibcon#end of sib2, iclass 34, count 2 2006.201.19:25:32.38#ibcon#*mode == 0, iclass 34, count 2 2006.201.19:25:32.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.19:25:32.38#ibcon#[25=AT05-04\r\n] 2006.201.19:25:32.38#ibcon#*before write, iclass 34, count 2 2006.201.19:25:32.38#ibcon#enter sib2, iclass 34, count 2 2006.201.19:25:32.38#ibcon#flushed, iclass 34, count 2 2006.201.19:25:32.38#ibcon#about to write, iclass 34, count 2 2006.201.19:25:32.38#ibcon#wrote, iclass 34, count 2 2006.201.19:25:32.38#ibcon#about to read 3, iclass 34, count 2 2006.201.19:25:32.41#ibcon#read 3, iclass 34, count 2 2006.201.19:25:32.41#ibcon#about to read 4, iclass 34, count 2 2006.201.19:25:32.41#ibcon#read 4, iclass 34, count 2 2006.201.19:25:32.41#ibcon#about to read 5, iclass 34, count 2 2006.201.19:25:32.41#ibcon#read 5, iclass 34, count 2 2006.201.19:25:32.41#ibcon#about to read 6, iclass 34, count 2 2006.201.19:25:32.41#ibcon#read 6, iclass 34, count 2 2006.201.19:25:32.41#ibcon#end of sib2, iclass 34, count 2 2006.201.19:25:32.41#ibcon#*after write, iclass 34, count 2 2006.201.19:25:32.41#ibcon#*before return 0, iclass 34, count 2 2006.201.19:25:32.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:32.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:32.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.19:25:32.41#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:32.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:32.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:32.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:32.53#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:25:32.53#ibcon#first serial, iclass 34, count 0 2006.201.19:25:32.53#ibcon#enter sib2, iclass 34, count 0 2006.201.19:25:32.53#ibcon#flushed, iclass 34, count 0 2006.201.19:25:32.53#ibcon#about to write, iclass 34, count 0 2006.201.19:25:32.53#ibcon#wrote, iclass 34, count 0 2006.201.19:25:32.53#ibcon#about to read 3, iclass 34, count 0 2006.201.19:25:32.55#ibcon#read 3, iclass 34, count 0 2006.201.19:25:32.55#ibcon#about to read 4, iclass 34, count 0 2006.201.19:25:32.55#ibcon#read 4, iclass 34, count 0 2006.201.19:25:32.55#ibcon#about to read 5, iclass 34, count 0 2006.201.19:25:32.55#ibcon#read 5, iclass 34, count 0 2006.201.19:25:32.55#ibcon#about to read 6, iclass 34, count 0 2006.201.19:25:32.55#ibcon#read 6, iclass 34, count 0 2006.201.19:25:32.55#ibcon#end of sib2, iclass 34, count 0 2006.201.19:25:32.55#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:25:32.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:25:32.55#ibcon#[25=USB\r\n] 2006.201.19:25:32.55#ibcon#*before write, iclass 34, count 0 2006.201.19:25:32.55#ibcon#enter sib2, iclass 34, count 0 2006.201.19:25:32.55#ibcon#flushed, iclass 34, count 0 2006.201.19:25:32.55#ibcon#about to write, iclass 34, count 0 2006.201.19:25:32.55#ibcon#wrote, iclass 34, count 0 2006.201.19:25:32.55#ibcon#about to read 3, iclass 34, count 0 2006.201.19:25:32.58#ibcon#read 3, iclass 34, count 0 2006.201.19:25:32.58#ibcon#about to read 4, iclass 34, count 0 2006.201.19:25:32.58#ibcon#read 4, iclass 34, count 0 2006.201.19:25:32.58#ibcon#about to read 5, iclass 34, count 0 2006.201.19:25:32.58#ibcon#read 5, iclass 34, count 0 2006.201.19:25:32.58#ibcon#about to read 6, iclass 34, count 0 2006.201.19:25:32.58#ibcon#read 6, iclass 34, count 0 2006.201.19:25:32.58#ibcon#end of sib2, iclass 34, count 0 2006.201.19:25:32.58#ibcon#*after write, iclass 34, count 0 2006.201.19:25:32.58#ibcon#*before return 0, iclass 34, count 0 2006.201.19:25:32.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:32.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:32.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:25:32.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:25:32.58$vck44/valo=6,814.99 2006.201.19:25:32.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.19:25:32.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.19:25:32.58#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:32.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:32.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:32.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:32.58#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:25:32.58#ibcon#first serial, iclass 36, count 0 2006.201.19:25:32.58#ibcon#enter sib2, iclass 36, count 0 2006.201.19:25:32.58#ibcon#flushed, iclass 36, count 0 2006.201.19:25:32.58#ibcon#about to write, iclass 36, count 0 2006.201.19:25:32.58#ibcon#wrote, iclass 36, count 0 2006.201.19:25:32.58#ibcon#about to read 3, iclass 36, count 0 2006.201.19:25:32.60#ibcon#read 3, iclass 36, count 0 2006.201.19:25:32.60#ibcon#about to read 4, iclass 36, count 0 2006.201.19:25:32.60#ibcon#read 4, iclass 36, count 0 2006.201.19:25:32.60#ibcon#about to read 5, iclass 36, count 0 2006.201.19:25:32.60#ibcon#read 5, iclass 36, count 0 2006.201.19:25:32.60#ibcon#about to read 6, iclass 36, count 0 2006.201.19:25:32.60#ibcon#read 6, iclass 36, count 0 2006.201.19:25:32.60#ibcon#end of sib2, iclass 36, count 0 2006.201.19:25:32.60#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:25:32.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:25:32.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:25:32.60#ibcon#*before write, iclass 36, count 0 2006.201.19:25:32.60#ibcon#enter sib2, iclass 36, count 0 2006.201.19:25:32.60#ibcon#flushed, iclass 36, count 0 2006.201.19:25:32.60#ibcon#about to write, iclass 36, count 0 2006.201.19:25:32.60#ibcon#wrote, iclass 36, count 0 2006.201.19:25:32.60#ibcon#about to read 3, iclass 36, count 0 2006.201.19:25:32.64#ibcon#read 3, iclass 36, count 0 2006.201.19:25:32.64#ibcon#about to read 4, iclass 36, count 0 2006.201.19:25:32.64#ibcon#read 4, iclass 36, count 0 2006.201.19:25:32.64#ibcon#about to read 5, iclass 36, count 0 2006.201.19:25:32.64#ibcon#read 5, iclass 36, count 0 2006.201.19:25:32.64#ibcon#about to read 6, iclass 36, count 0 2006.201.19:25:32.64#ibcon#read 6, iclass 36, count 0 2006.201.19:25:32.64#ibcon#end of sib2, iclass 36, count 0 2006.201.19:25:32.64#ibcon#*after write, iclass 36, count 0 2006.201.19:25:32.64#ibcon#*before return 0, iclass 36, count 0 2006.201.19:25:32.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:32.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:32.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:25:32.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:25:32.64$vck44/va=6,5 2006.201.19:25:32.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.19:25:32.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.19:25:32.64#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:32.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:32.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:32.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:32.70#ibcon#enter wrdev, iclass 38, count 2 2006.201.19:25:32.70#ibcon#first serial, iclass 38, count 2 2006.201.19:25:32.70#ibcon#enter sib2, iclass 38, count 2 2006.201.19:25:32.70#ibcon#flushed, iclass 38, count 2 2006.201.19:25:32.70#ibcon#about to write, iclass 38, count 2 2006.201.19:25:32.70#ibcon#wrote, iclass 38, count 2 2006.201.19:25:32.70#ibcon#about to read 3, iclass 38, count 2 2006.201.19:25:32.72#ibcon#read 3, iclass 38, count 2 2006.201.19:25:32.72#ibcon#about to read 4, iclass 38, count 2 2006.201.19:25:32.72#ibcon#read 4, iclass 38, count 2 2006.201.19:25:32.72#ibcon#about to read 5, iclass 38, count 2 2006.201.19:25:32.72#ibcon#read 5, iclass 38, count 2 2006.201.19:25:32.72#ibcon#about to read 6, iclass 38, count 2 2006.201.19:25:32.72#ibcon#read 6, iclass 38, count 2 2006.201.19:25:32.72#ibcon#end of sib2, iclass 38, count 2 2006.201.19:25:32.72#ibcon#*mode == 0, iclass 38, count 2 2006.201.19:25:32.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.19:25:32.72#ibcon#[25=AT06-05\r\n] 2006.201.19:25:32.72#ibcon#*before write, iclass 38, count 2 2006.201.19:25:32.72#ibcon#enter sib2, iclass 38, count 2 2006.201.19:25:32.72#ibcon#flushed, iclass 38, count 2 2006.201.19:25:32.72#ibcon#about to write, iclass 38, count 2 2006.201.19:25:32.72#ibcon#wrote, iclass 38, count 2 2006.201.19:25:32.72#ibcon#about to read 3, iclass 38, count 2 2006.201.19:25:32.75#ibcon#read 3, iclass 38, count 2 2006.201.19:25:32.75#ibcon#about to read 4, iclass 38, count 2 2006.201.19:25:32.75#ibcon#read 4, iclass 38, count 2 2006.201.19:25:32.75#ibcon#about to read 5, iclass 38, count 2 2006.201.19:25:32.75#ibcon#read 5, iclass 38, count 2 2006.201.19:25:32.75#ibcon#about to read 6, iclass 38, count 2 2006.201.19:25:32.75#ibcon#read 6, iclass 38, count 2 2006.201.19:25:32.75#ibcon#end of sib2, iclass 38, count 2 2006.201.19:25:32.75#ibcon#*after write, iclass 38, count 2 2006.201.19:25:32.75#ibcon#*before return 0, iclass 38, count 2 2006.201.19:25:32.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:32.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:32.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.19:25:32.75#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:32.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:32.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:32.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:32.87#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:25:32.87#ibcon#first serial, iclass 38, count 0 2006.201.19:25:32.87#ibcon#enter sib2, iclass 38, count 0 2006.201.19:25:32.87#ibcon#flushed, iclass 38, count 0 2006.201.19:25:32.87#ibcon#about to write, iclass 38, count 0 2006.201.19:25:32.87#ibcon#wrote, iclass 38, count 0 2006.201.19:25:32.87#ibcon#about to read 3, iclass 38, count 0 2006.201.19:25:32.89#ibcon#read 3, iclass 38, count 0 2006.201.19:25:32.89#ibcon#about to read 4, iclass 38, count 0 2006.201.19:25:32.89#ibcon#read 4, iclass 38, count 0 2006.201.19:25:32.89#ibcon#about to read 5, iclass 38, count 0 2006.201.19:25:32.89#ibcon#read 5, iclass 38, count 0 2006.201.19:25:32.89#ibcon#about to read 6, iclass 38, count 0 2006.201.19:25:32.89#ibcon#read 6, iclass 38, count 0 2006.201.19:25:32.89#ibcon#end of sib2, iclass 38, count 0 2006.201.19:25:32.89#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:25:32.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:25:32.89#ibcon#[25=USB\r\n] 2006.201.19:25:32.89#ibcon#*before write, iclass 38, count 0 2006.201.19:25:32.89#ibcon#enter sib2, iclass 38, count 0 2006.201.19:25:32.89#ibcon#flushed, iclass 38, count 0 2006.201.19:25:32.89#ibcon#about to write, iclass 38, count 0 2006.201.19:25:32.89#ibcon#wrote, iclass 38, count 0 2006.201.19:25:32.89#ibcon#about to read 3, iclass 38, count 0 2006.201.19:25:32.92#ibcon#read 3, iclass 38, count 0 2006.201.19:25:32.92#ibcon#about to read 4, iclass 38, count 0 2006.201.19:25:32.92#ibcon#read 4, iclass 38, count 0 2006.201.19:25:32.92#ibcon#about to read 5, iclass 38, count 0 2006.201.19:25:32.92#ibcon#read 5, iclass 38, count 0 2006.201.19:25:32.92#ibcon#about to read 6, iclass 38, count 0 2006.201.19:25:32.92#ibcon#read 6, iclass 38, count 0 2006.201.19:25:32.92#ibcon#end of sib2, iclass 38, count 0 2006.201.19:25:32.92#ibcon#*after write, iclass 38, count 0 2006.201.19:25:32.92#ibcon#*before return 0, iclass 38, count 0 2006.201.19:25:32.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:32.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:32.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:25:32.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:25:32.92$vck44/valo=7,864.99 2006.201.19:25:32.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.19:25:32.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.19:25:32.92#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:32.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:32.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:32.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:32.92#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:25:32.92#ibcon#first serial, iclass 40, count 0 2006.201.19:25:32.92#ibcon#enter sib2, iclass 40, count 0 2006.201.19:25:32.92#ibcon#flushed, iclass 40, count 0 2006.201.19:25:32.92#ibcon#about to write, iclass 40, count 0 2006.201.19:25:32.92#ibcon#wrote, iclass 40, count 0 2006.201.19:25:32.92#ibcon#about to read 3, iclass 40, count 0 2006.201.19:25:32.94#ibcon#read 3, iclass 40, count 0 2006.201.19:25:32.94#ibcon#about to read 4, iclass 40, count 0 2006.201.19:25:32.94#ibcon#read 4, iclass 40, count 0 2006.201.19:25:32.94#ibcon#about to read 5, iclass 40, count 0 2006.201.19:25:32.94#ibcon#read 5, iclass 40, count 0 2006.201.19:25:32.94#ibcon#about to read 6, iclass 40, count 0 2006.201.19:25:32.94#ibcon#read 6, iclass 40, count 0 2006.201.19:25:32.94#ibcon#end of sib2, iclass 40, count 0 2006.201.19:25:32.94#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:25:32.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:25:32.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:25:32.94#ibcon#*before write, iclass 40, count 0 2006.201.19:25:32.94#ibcon#enter sib2, iclass 40, count 0 2006.201.19:25:32.94#ibcon#flushed, iclass 40, count 0 2006.201.19:25:32.94#ibcon#about to write, iclass 40, count 0 2006.201.19:25:32.94#ibcon#wrote, iclass 40, count 0 2006.201.19:25:32.94#ibcon#about to read 3, iclass 40, count 0 2006.201.19:25:32.98#abcon#<5=/03 0.8 2.2 20.491001002.4\r\n> 2006.201.19:25:32.98#ibcon#read 3, iclass 40, count 0 2006.201.19:25:32.98#ibcon#about to read 4, iclass 40, count 0 2006.201.19:25:32.98#ibcon#read 4, iclass 40, count 0 2006.201.19:25:32.98#ibcon#about to read 5, iclass 40, count 0 2006.201.19:25:32.98#ibcon#read 5, iclass 40, count 0 2006.201.19:25:32.98#ibcon#about to read 6, iclass 40, count 0 2006.201.19:25:32.98#ibcon#read 6, iclass 40, count 0 2006.201.19:25:32.98#ibcon#end of sib2, iclass 40, count 0 2006.201.19:25:32.98#ibcon#*after write, iclass 40, count 0 2006.201.19:25:32.98#ibcon#*before return 0, iclass 40, count 0 2006.201.19:25:32.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:32.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:32.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:25:32.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:25:32.98$vck44/va=7,5 2006.201.19:25:32.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.19:25:32.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.19:25:32.98#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:32.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:25:33.00#abcon#{5=INTERFACE CLEAR} 2006.201.19:25:33.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:25:33.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:25:33.04#ibcon#enter wrdev, iclass 7, count 2 2006.201.19:25:33.04#ibcon#first serial, iclass 7, count 2 2006.201.19:25:33.04#ibcon#enter sib2, iclass 7, count 2 2006.201.19:25:33.04#ibcon#flushed, iclass 7, count 2 2006.201.19:25:33.04#ibcon#about to write, iclass 7, count 2 2006.201.19:25:33.04#ibcon#wrote, iclass 7, count 2 2006.201.19:25:33.04#ibcon#about to read 3, iclass 7, count 2 2006.201.19:25:33.06#ibcon#read 3, iclass 7, count 2 2006.201.19:25:33.06#ibcon#about to read 4, iclass 7, count 2 2006.201.19:25:33.06#ibcon#read 4, iclass 7, count 2 2006.201.19:25:33.06#ibcon#about to read 5, iclass 7, count 2 2006.201.19:25:33.06#ibcon#read 5, iclass 7, count 2 2006.201.19:25:33.06#ibcon#about to read 6, iclass 7, count 2 2006.201.19:25:33.06#ibcon#read 6, iclass 7, count 2 2006.201.19:25:33.06#ibcon#end of sib2, iclass 7, count 2 2006.201.19:25:33.06#ibcon#*mode == 0, iclass 7, count 2 2006.201.19:25:33.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.19:25:33.06#ibcon#[25=AT07-05\r\n] 2006.201.19:25:33.06#ibcon#*before write, iclass 7, count 2 2006.201.19:25:33.06#ibcon#enter sib2, iclass 7, count 2 2006.201.19:25:33.06#ibcon#flushed, iclass 7, count 2 2006.201.19:25:33.06#ibcon#about to write, iclass 7, count 2 2006.201.19:25:33.06#ibcon#wrote, iclass 7, count 2 2006.201.19:25:33.06#ibcon#about to read 3, iclass 7, count 2 2006.201.19:25:33.06#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:25:33.09#ibcon#read 3, iclass 7, count 2 2006.201.19:25:33.09#ibcon#about to read 4, iclass 7, count 2 2006.201.19:25:33.09#ibcon#read 4, iclass 7, count 2 2006.201.19:25:33.09#ibcon#about to read 5, iclass 7, count 2 2006.201.19:25:33.09#ibcon#read 5, iclass 7, count 2 2006.201.19:25:33.09#ibcon#about to read 6, iclass 7, count 2 2006.201.19:25:33.09#ibcon#read 6, iclass 7, count 2 2006.201.19:25:33.09#ibcon#end of sib2, iclass 7, count 2 2006.201.19:25:33.09#ibcon#*after write, iclass 7, count 2 2006.201.19:25:33.09#ibcon#*before return 0, iclass 7, count 2 2006.201.19:25:33.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:25:33.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:25:33.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.19:25:33.09#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:33.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:25:33.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:25:33.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:25:33.21#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:25:33.21#ibcon#first serial, iclass 7, count 0 2006.201.19:25:33.21#ibcon#enter sib2, iclass 7, count 0 2006.201.19:25:33.21#ibcon#flushed, iclass 7, count 0 2006.201.19:25:33.21#ibcon#about to write, iclass 7, count 0 2006.201.19:25:33.21#ibcon#wrote, iclass 7, count 0 2006.201.19:25:33.21#ibcon#about to read 3, iclass 7, count 0 2006.201.19:25:33.23#ibcon#read 3, iclass 7, count 0 2006.201.19:25:33.23#ibcon#about to read 4, iclass 7, count 0 2006.201.19:25:33.23#ibcon#read 4, iclass 7, count 0 2006.201.19:25:33.23#ibcon#about to read 5, iclass 7, count 0 2006.201.19:25:33.23#ibcon#read 5, iclass 7, count 0 2006.201.19:25:33.23#ibcon#about to read 6, iclass 7, count 0 2006.201.19:25:33.23#ibcon#read 6, iclass 7, count 0 2006.201.19:25:33.23#ibcon#end of sib2, iclass 7, count 0 2006.201.19:25:33.23#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:25:33.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:25:33.23#ibcon#[25=USB\r\n] 2006.201.19:25:33.23#ibcon#*before write, iclass 7, count 0 2006.201.19:25:33.23#ibcon#enter sib2, iclass 7, count 0 2006.201.19:25:33.23#ibcon#flushed, iclass 7, count 0 2006.201.19:25:33.23#ibcon#about to write, iclass 7, count 0 2006.201.19:25:33.23#ibcon#wrote, iclass 7, count 0 2006.201.19:25:33.23#ibcon#about to read 3, iclass 7, count 0 2006.201.19:25:33.26#ibcon#read 3, iclass 7, count 0 2006.201.19:25:33.26#ibcon#about to read 4, iclass 7, count 0 2006.201.19:25:33.26#ibcon#read 4, iclass 7, count 0 2006.201.19:25:33.26#ibcon#about to read 5, iclass 7, count 0 2006.201.19:25:33.26#ibcon#read 5, iclass 7, count 0 2006.201.19:25:33.26#ibcon#about to read 6, iclass 7, count 0 2006.201.19:25:33.26#ibcon#read 6, iclass 7, count 0 2006.201.19:25:33.26#ibcon#end of sib2, iclass 7, count 0 2006.201.19:25:33.26#ibcon#*after write, iclass 7, count 0 2006.201.19:25:33.26#ibcon#*before return 0, iclass 7, count 0 2006.201.19:25:33.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:25:33.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:25:33.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:25:33.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:25:33.26$vck44/valo=8,884.99 2006.201.19:25:33.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.19:25:33.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.19:25:33.26#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:33.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:33.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:33.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:33.26#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:25:33.26#ibcon#first serial, iclass 12, count 0 2006.201.19:25:33.26#ibcon#enter sib2, iclass 12, count 0 2006.201.19:25:33.26#ibcon#flushed, iclass 12, count 0 2006.201.19:25:33.26#ibcon#about to write, iclass 12, count 0 2006.201.19:25:33.26#ibcon#wrote, iclass 12, count 0 2006.201.19:25:33.26#ibcon#about to read 3, iclass 12, count 0 2006.201.19:25:33.28#ibcon#read 3, iclass 12, count 0 2006.201.19:25:33.28#ibcon#about to read 4, iclass 12, count 0 2006.201.19:25:33.28#ibcon#read 4, iclass 12, count 0 2006.201.19:25:33.28#ibcon#about to read 5, iclass 12, count 0 2006.201.19:25:33.28#ibcon#read 5, iclass 12, count 0 2006.201.19:25:33.28#ibcon#about to read 6, iclass 12, count 0 2006.201.19:25:33.28#ibcon#read 6, iclass 12, count 0 2006.201.19:25:33.28#ibcon#end of sib2, iclass 12, count 0 2006.201.19:25:33.28#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:25:33.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:25:33.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:25:33.28#ibcon#*before write, iclass 12, count 0 2006.201.19:25:33.28#ibcon#enter sib2, iclass 12, count 0 2006.201.19:25:33.28#ibcon#flushed, iclass 12, count 0 2006.201.19:25:33.28#ibcon#about to write, iclass 12, count 0 2006.201.19:25:33.28#ibcon#wrote, iclass 12, count 0 2006.201.19:25:33.28#ibcon#about to read 3, iclass 12, count 0 2006.201.19:25:33.32#ibcon#read 3, iclass 12, count 0 2006.201.19:25:33.32#ibcon#about to read 4, iclass 12, count 0 2006.201.19:25:33.32#ibcon#read 4, iclass 12, count 0 2006.201.19:25:33.32#ibcon#about to read 5, iclass 12, count 0 2006.201.19:25:33.32#ibcon#read 5, iclass 12, count 0 2006.201.19:25:33.32#ibcon#about to read 6, iclass 12, count 0 2006.201.19:25:33.32#ibcon#read 6, iclass 12, count 0 2006.201.19:25:33.32#ibcon#end of sib2, iclass 12, count 0 2006.201.19:25:33.32#ibcon#*after write, iclass 12, count 0 2006.201.19:25:33.32#ibcon#*before return 0, iclass 12, count 0 2006.201.19:25:33.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:33.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:33.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:25:33.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:25:33.32$vck44/va=8,4 2006.201.19:25:33.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.19:25:33.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.19:25:33.32#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:33.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:25:33.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:25:33.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:25:33.38#ibcon#enter wrdev, iclass 14, count 2 2006.201.19:25:33.38#ibcon#first serial, iclass 14, count 2 2006.201.19:25:33.38#ibcon#enter sib2, iclass 14, count 2 2006.201.19:25:33.38#ibcon#flushed, iclass 14, count 2 2006.201.19:25:33.38#ibcon#about to write, iclass 14, count 2 2006.201.19:25:33.38#ibcon#wrote, iclass 14, count 2 2006.201.19:25:33.38#ibcon#about to read 3, iclass 14, count 2 2006.201.19:25:33.40#ibcon#read 3, iclass 14, count 2 2006.201.19:25:33.40#ibcon#about to read 4, iclass 14, count 2 2006.201.19:25:33.40#ibcon#read 4, iclass 14, count 2 2006.201.19:25:33.40#ibcon#about to read 5, iclass 14, count 2 2006.201.19:25:33.40#ibcon#read 5, iclass 14, count 2 2006.201.19:25:33.40#ibcon#about to read 6, iclass 14, count 2 2006.201.19:25:33.40#ibcon#read 6, iclass 14, count 2 2006.201.19:25:33.40#ibcon#end of sib2, iclass 14, count 2 2006.201.19:25:33.40#ibcon#*mode == 0, iclass 14, count 2 2006.201.19:25:33.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.19:25:33.40#ibcon#[25=AT08-04\r\n] 2006.201.19:25:33.40#ibcon#*before write, iclass 14, count 2 2006.201.19:25:33.40#ibcon#enter sib2, iclass 14, count 2 2006.201.19:25:33.40#ibcon#flushed, iclass 14, count 2 2006.201.19:25:33.40#ibcon#about to write, iclass 14, count 2 2006.201.19:25:33.40#ibcon#wrote, iclass 14, count 2 2006.201.19:25:33.40#ibcon#about to read 3, iclass 14, count 2 2006.201.19:25:33.43#ibcon#read 3, iclass 14, count 2 2006.201.19:25:33.43#ibcon#about to read 4, iclass 14, count 2 2006.201.19:25:33.43#ibcon#read 4, iclass 14, count 2 2006.201.19:25:33.43#ibcon#about to read 5, iclass 14, count 2 2006.201.19:25:33.43#ibcon#read 5, iclass 14, count 2 2006.201.19:25:33.43#ibcon#about to read 6, iclass 14, count 2 2006.201.19:25:33.43#ibcon#read 6, iclass 14, count 2 2006.201.19:25:33.43#ibcon#end of sib2, iclass 14, count 2 2006.201.19:25:33.43#ibcon#*after write, iclass 14, count 2 2006.201.19:25:33.43#ibcon#*before return 0, iclass 14, count 2 2006.201.19:25:33.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:25:33.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:25:33.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.19:25:33.43#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:33.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:25:33.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:25:33.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:25:33.55#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:25:33.55#ibcon#first serial, iclass 14, count 0 2006.201.19:25:33.55#ibcon#enter sib2, iclass 14, count 0 2006.201.19:25:33.55#ibcon#flushed, iclass 14, count 0 2006.201.19:25:33.55#ibcon#about to write, iclass 14, count 0 2006.201.19:25:33.55#ibcon#wrote, iclass 14, count 0 2006.201.19:25:33.55#ibcon#about to read 3, iclass 14, count 0 2006.201.19:25:33.57#ibcon#read 3, iclass 14, count 0 2006.201.19:25:33.57#ibcon#about to read 4, iclass 14, count 0 2006.201.19:25:33.57#ibcon#read 4, iclass 14, count 0 2006.201.19:25:33.57#ibcon#about to read 5, iclass 14, count 0 2006.201.19:25:33.57#ibcon#read 5, iclass 14, count 0 2006.201.19:25:33.57#ibcon#about to read 6, iclass 14, count 0 2006.201.19:25:33.57#ibcon#read 6, iclass 14, count 0 2006.201.19:25:33.57#ibcon#end of sib2, iclass 14, count 0 2006.201.19:25:33.57#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:25:33.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:25:33.57#ibcon#[25=USB\r\n] 2006.201.19:25:33.57#ibcon#*before write, iclass 14, count 0 2006.201.19:25:33.57#ibcon#enter sib2, iclass 14, count 0 2006.201.19:25:33.57#ibcon#flushed, iclass 14, count 0 2006.201.19:25:33.57#ibcon#about to write, iclass 14, count 0 2006.201.19:25:33.57#ibcon#wrote, iclass 14, count 0 2006.201.19:25:33.57#ibcon#about to read 3, iclass 14, count 0 2006.201.19:25:33.60#ibcon#read 3, iclass 14, count 0 2006.201.19:25:33.60#ibcon#about to read 4, iclass 14, count 0 2006.201.19:25:33.60#ibcon#read 4, iclass 14, count 0 2006.201.19:25:33.60#ibcon#about to read 5, iclass 14, count 0 2006.201.19:25:33.60#ibcon#read 5, iclass 14, count 0 2006.201.19:25:33.60#ibcon#about to read 6, iclass 14, count 0 2006.201.19:25:33.60#ibcon#read 6, iclass 14, count 0 2006.201.19:25:33.60#ibcon#end of sib2, iclass 14, count 0 2006.201.19:25:33.60#ibcon#*after write, iclass 14, count 0 2006.201.19:25:33.60#ibcon#*before return 0, iclass 14, count 0 2006.201.19:25:33.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:25:33.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:25:33.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:25:33.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:25:33.60$vck44/vblo=1,629.99 2006.201.19:25:33.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.19:25:33.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.19:25:33.60#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:33.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:33.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:33.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:33.60#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:25:33.60#ibcon#first serial, iclass 16, count 0 2006.201.19:25:33.60#ibcon#enter sib2, iclass 16, count 0 2006.201.19:25:33.60#ibcon#flushed, iclass 16, count 0 2006.201.19:25:33.60#ibcon#about to write, iclass 16, count 0 2006.201.19:25:33.60#ibcon#wrote, iclass 16, count 0 2006.201.19:25:33.60#ibcon#about to read 3, iclass 16, count 0 2006.201.19:25:33.62#ibcon#read 3, iclass 16, count 0 2006.201.19:25:33.62#ibcon#about to read 4, iclass 16, count 0 2006.201.19:25:33.62#ibcon#read 4, iclass 16, count 0 2006.201.19:25:33.62#ibcon#about to read 5, iclass 16, count 0 2006.201.19:25:33.62#ibcon#read 5, iclass 16, count 0 2006.201.19:25:33.62#ibcon#about to read 6, iclass 16, count 0 2006.201.19:25:33.62#ibcon#read 6, iclass 16, count 0 2006.201.19:25:33.62#ibcon#end of sib2, iclass 16, count 0 2006.201.19:25:33.62#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:25:33.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:25:33.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:25:33.62#ibcon#*before write, iclass 16, count 0 2006.201.19:25:33.62#ibcon#enter sib2, iclass 16, count 0 2006.201.19:25:33.62#ibcon#flushed, iclass 16, count 0 2006.201.19:25:33.62#ibcon#about to write, iclass 16, count 0 2006.201.19:25:33.62#ibcon#wrote, iclass 16, count 0 2006.201.19:25:33.62#ibcon#about to read 3, iclass 16, count 0 2006.201.19:25:33.66#ibcon#read 3, iclass 16, count 0 2006.201.19:25:33.66#ibcon#about to read 4, iclass 16, count 0 2006.201.19:25:33.66#ibcon#read 4, iclass 16, count 0 2006.201.19:25:33.66#ibcon#about to read 5, iclass 16, count 0 2006.201.19:25:33.66#ibcon#read 5, iclass 16, count 0 2006.201.19:25:33.66#ibcon#about to read 6, iclass 16, count 0 2006.201.19:25:33.66#ibcon#read 6, iclass 16, count 0 2006.201.19:25:33.66#ibcon#end of sib2, iclass 16, count 0 2006.201.19:25:33.66#ibcon#*after write, iclass 16, count 0 2006.201.19:25:33.66#ibcon#*before return 0, iclass 16, count 0 2006.201.19:25:33.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:33.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:25:33.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:25:33.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:25:33.66$vck44/vb=1,4 2006.201.19:25:33.66#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.19:25:33.66#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.19:25:33.66#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:33.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:33.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:33.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:33.66#ibcon#enter wrdev, iclass 18, count 2 2006.201.19:25:33.66#ibcon#first serial, iclass 18, count 2 2006.201.19:25:33.66#ibcon#enter sib2, iclass 18, count 2 2006.201.19:25:33.66#ibcon#flushed, iclass 18, count 2 2006.201.19:25:33.66#ibcon#about to write, iclass 18, count 2 2006.201.19:25:33.66#ibcon#wrote, iclass 18, count 2 2006.201.19:25:33.66#ibcon#about to read 3, iclass 18, count 2 2006.201.19:25:33.68#ibcon#read 3, iclass 18, count 2 2006.201.19:25:33.68#ibcon#about to read 4, iclass 18, count 2 2006.201.19:25:33.68#ibcon#read 4, iclass 18, count 2 2006.201.19:25:33.68#ibcon#about to read 5, iclass 18, count 2 2006.201.19:25:33.68#ibcon#read 5, iclass 18, count 2 2006.201.19:25:33.68#ibcon#about to read 6, iclass 18, count 2 2006.201.19:25:33.68#ibcon#read 6, iclass 18, count 2 2006.201.19:25:33.68#ibcon#end of sib2, iclass 18, count 2 2006.201.19:25:33.68#ibcon#*mode == 0, iclass 18, count 2 2006.201.19:25:33.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.19:25:33.68#ibcon#[27=AT01-04\r\n] 2006.201.19:25:33.68#ibcon#*before write, iclass 18, count 2 2006.201.19:25:33.68#ibcon#enter sib2, iclass 18, count 2 2006.201.19:25:33.68#ibcon#flushed, iclass 18, count 2 2006.201.19:25:33.68#ibcon#about to write, iclass 18, count 2 2006.201.19:25:33.68#ibcon#wrote, iclass 18, count 2 2006.201.19:25:33.68#ibcon#about to read 3, iclass 18, count 2 2006.201.19:25:33.71#ibcon#read 3, iclass 18, count 2 2006.201.19:25:33.71#ibcon#about to read 4, iclass 18, count 2 2006.201.19:25:33.71#ibcon#read 4, iclass 18, count 2 2006.201.19:25:33.71#ibcon#about to read 5, iclass 18, count 2 2006.201.19:25:33.71#ibcon#read 5, iclass 18, count 2 2006.201.19:25:33.71#ibcon#about to read 6, iclass 18, count 2 2006.201.19:25:33.71#ibcon#read 6, iclass 18, count 2 2006.201.19:25:33.71#ibcon#end of sib2, iclass 18, count 2 2006.201.19:25:33.71#ibcon#*after write, iclass 18, count 2 2006.201.19:25:33.71#ibcon#*before return 0, iclass 18, count 2 2006.201.19:25:33.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:33.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:25:33.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.19:25:33.71#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:33.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:33.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:33.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:33.83#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:25:33.83#ibcon#first serial, iclass 18, count 0 2006.201.19:25:33.83#ibcon#enter sib2, iclass 18, count 0 2006.201.19:25:33.83#ibcon#flushed, iclass 18, count 0 2006.201.19:25:33.83#ibcon#about to write, iclass 18, count 0 2006.201.19:25:33.83#ibcon#wrote, iclass 18, count 0 2006.201.19:25:33.83#ibcon#about to read 3, iclass 18, count 0 2006.201.19:25:33.85#ibcon#read 3, iclass 18, count 0 2006.201.19:25:33.85#ibcon#about to read 4, iclass 18, count 0 2006.201.19:25:33.85#ibcon#read 4, iclass 18, count 0 2006.201.19:25:33.85#ibcon#about to read 5, iclass 18, count 0 2006.201.19:25:33.85#ibcon#read 5, iclass 18, count 0 2006.201.19:25:33.85#ibcon#about to read 6, iclass 18, count 0 2006.201.19:25:33.85#ibcon#read 6, iclass 18, count 0 2006.201.19:25:33.85#ibcon#end of sib2, iclass 18, count 0 2006.201.19:25:33.85#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:25:33.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:25:33.85#ibcon#[27=USB\r\n] 2006.201.19:25:33.85#ibcon#*before write, iclass 18, count 0 2006.201.19:25:33.85#ibcon#enter sib2, iclass 18, count 0 2006.201.19:25:33.85#ibcon#flushed, iclass 18, count 0 2006.201.19:25:33.85#ibcon#about to write, iclass 18, count 0 2006.201.19:25:33.85#ibcon#wrote, iclass 18, count 0 2006.201.19:25:33.85#ibcon#about to read 3, iclass 18, count 0 2006.201.19:25:33.88#ibcon#read 3, iclass 18, count 0 2006.201.19:25:33.88#ibcon#about to read 4, iclass 18, count 0 2006.201.19:25:33.88#ibcon#read 4, iclass 18, count 0 2006.201.19:25:33.88#ibcon#about to read 5, iclass 18, count 0 2006.201.19:25:33.88#ibcon#read 5, iclass 18, count 0 2006.201.19:25:33.88#ibcon#about to read 6, iclass 18, count 0 2006.201.19:25:33.88#ibcon#read 6, iclass 18, count 0 2006.201.19:25:33.88#ibcon#end of sib2, iclass 18, count 0 2006.201.19:25:33.88#ibcon#*after write, iclass 18, count 0 2006.201.19:25:33.88#ibcon#*before return 0, iclass 18, count 0 2006.201.19:25:33.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:33.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:25:33.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:25:33.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:25:33.88$vck44/vblo=2,634.99 2006.201.19:25:33.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.19:25:33.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.19:25:33.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:33.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:33.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:33.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:33.88#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:25:33.88#ibcon#first serial, iclass 20, count 0 2006.201.19:25:33.88#ibcon#enter sib2, iclass 20, count 0 2006.201.19:25:33.88#ibcon#flushed, iclass 20, count 0 2006.201.19:25:33.88#ibcon#about to write, iclass 20, count 0 2006.201.19:25:33.88#ibcon#wrote, iclass 20, count 0 2006.201.19:25:33.88#ibcon#about to read 3, iclass 20, count 0 2006.201.19:25:33.90#ibcon#read 3, iclass 20, count 0 2006.201.19:25:33.90#ibcon#about to read 4, iclass 20, count 0 2006.201.19:25:33.90#ibcon#read 4, iclass 20, count 0 2006.201.19:25:33.90#ibcon#about to read 5, iclass 20, count 0 2006.201.19:25:33.90#ibcon#read 5, iclass 20, count 0 2006.201.19:25:33.90#ibcon#about to read 6, iclass 20, count 0 2006.201.19:25:33.90#ibcon#read 6, iclass 20, count 0 2006.201.19:25:33.90#ibcon#end of sib2, iclass 20, count 0 2006.201.19:25:33.90#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:25:33.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:25:33.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:25:33.90#ibcon#*before write, iclass 20, count 0 2006.201.19:25:33.90#ibcon#enter sib2, iclass 20, count 0 2006.201.19:25:33.90#ibcon#flushed, iclass 20, count 0 2006.201.19:25:33.90#ibcon#about to write, iclass 20, count 0 2006.201.19:25:33.90#ibcon#wrote, iclass 20, count 0 2006.201.19:25:33.90#ibcon#about to read 3, iclass 20, count 0 2006.201.19:25:33.94#ibcon#read 3, iclass 20, count 0 2006.201.19:25:33.94#ibcon#about to read 4, iclass 20, count 0 2006.201.19:25:33.94#ibcon#read 4, iclass 20, count 0 2006.201.19:25:33.94#ibcon#about to read 5, iclass 20, count 0 2006.201.19:25:33.94#ibcon#read 5, iclass 20, count 0 2006.201.19:25:33.94#ibcon#about to read 6, iclass 20, count 0 2006.201.19:25:33.94#ibcon#read 6, iclass 20, count 0 2006.201.19:25:33.94#ibcon#end of sib2, iclass 20, count 0 2006.201.19:25:33.94#ibcon#*after write, iclass 20, count 0 2006.201.19:25:33.94#ibcon#*before return 0, iclass 20, count 0 2006.201.19:25:33.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:33.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:25:33.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:25:33.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:25:33.94$vck44/vb=2,5 2006.201.19:25:33.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.19:25:33.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.19:25:33.94#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:33.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:34.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:34.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:34.00#ibcon#enter wrdev, iclass 22, count 2 2006.201.19:25:34.00#ibcon#first serial, iclass 22, count 2 2006.201.19:25:34.00#ibcon#enter sib2, iclass 22, count 2 2006.201.19:25:34.00#ibcon#flushed, iclass 22, count 2 2006.201.19:25:34.00#ibcon#about to write, iclass 22, count 2 2006.201.19:25:34.00#ibcon#wrote, iclass 22, count 2 2006.201.19:25:34.00#ibcon#about to read 3, iclass 22, count 2 2006.201.19:25:34.02#ibcon#read 3, iclass 22, count 2 2006.201.19:25:34.02#ibcon#about to read 4, iclass 22, count 2 2006.201.19:25:34.02#ibcon#read 4, iclass 22, count 2 2006.201.19:25:34.02#ibcon#about to read 5, iclass 22, count 2 2006.201.19:25:34.02#ibcon#read 5, iclass 22, count 2 2006.201.19:25:34.02#ibcon#about to read 6, iclass 22, count 2 2006.201.19:25:34.02#ibcon#read 6, iclass 22, count 2 2006.201.19:25:34.02#ibcon#end of sib2, iclass 22, count 2 2006.201.19:25:34.02#ibcon#*mode == 0, iclass 22, count 2 2006.201.19:25:34.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.19:25:34.02#ibcon#[27=AT02-05\r\n] 2006.201.19:25:34.02#ibcon#*before write, iclass 22, count 2 2006.201.19:25:34.02#ibcon#enter sib2, iclass 22, count 2 2006.201.19:25:34.02#ibcon#flushed, iclass 22, count 2 2006.201.19:25:34.02#ibcon#about to write, iclass 22, count 2 2006.201.19:25:34.02#ibcon#wrote, iclass 22, count 2 2006.201.19:25:34.02#ibcon#about to read 3, iclass 22, count 2 2006.201.19:25:34.05#ibcon#read 3, iclass 22, count 2 2006.201.19:25:34.05#ibcon#about to read 4, iclass 22, count 2 2006.201.19:25:34.05#ibcon#read 4, iclass 22, count 2 2006.201.19:25:34.05#ibcon#about to read 5, iclass 22, count 2 2006.201.19:25:34.05#ibcon#read 5, iclass 22, count 2 2006.201.19:25:34.05#ibcon#about to read 6, iclass 22, count 2 2006.201.19:25:34.05#ibcon#read 6, iclass 22, count 2 2006.201.19:25:34.05#ibcon#end of sib2, iclass 22, count 2 2006.201.19:25:34.05#ibcon#*after write, iclass 22, count 2 2006.201.19:25:34.05#ibcon#*before return 0, iclass 22, count 2 2006.201.19:25:34.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:34.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:25:34.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.19:25:34.05#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:34.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:34.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:34.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:34.17#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:25:34.17#ibcon#first serial, iclass 22, count 0 2006.201.19:25:34.17#ibcon#enter sib2, iclass 22, count 0 2006.201.19:25:34.17#ibcon#flushed, iclass 22, count 0 2006.201.19:25:34.17#ibcon#about to write, iclass 22, count 0 2006.201.19:25:34.17#ibcon#wrote, iclass 22, count 0 2006.201.19:25:34.17#ibcon#about to read 3, iclass 22, count 0 2006.201.19:25:34.19#ibcon#read 3, iclass 22, count 0 2006.201.19:25:34.19#ibcon#about to read 4, iclass 22, count 0 2006.201.19:25:34.19#ibcon#read 4, iclass 22, count 0 2006.201.19:25:34.19#ibcon#about to read 5, iclass 22, count 0 2006.201.19:25:34.19#ibcon#read 5, iclass 22, count 0 2006.201.19:25:34.19#ibcon#about to read 6, iclass 22, count 0 2006.201.19:25:34.19#ibcon#read 6, iclass 22, count 0 2006.201.19:25:34.19#ibcon#end of sib2, iclass 22, count 0 2006.201.19:25:34.19#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:25:34.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:25:34.19#ibcon#[27=USB\r\n] 2006.201.19:25:34.19#ibcon#*before write, iclass 22, count 0 2006.201.19:25:34.19#ibcon#enter sib2, iclass 22, count 0 2006.201.19:25:34.19#ibcon#flushed, iclass 22, count 0 2006.201.19:25:34.19#ibcon#about to write, iclass 22, count 0 2006.201.19:25:34.19#ibcon#wrote, iclass 22, count 0 2006.201.19:25:34.19#ibcon#about to read 3, iclass 22, count 0 2006.201.19:25:34.22#ibcon#read 3, iclass 22, count 0 2006.201.19:25:34.22#ibcon#about to read 4, iclass 22, count 0 2006.201.19:25:34.22#ibcon#read 4, iclass 22, count 0 2006.201.19:25:34.22#ibcon#about to read 5, iclass 22, count 0 2006.201.19:25:34.22#ibcon#read 5, iclass 22, count 0 2006.201.19:25:34.22#ibcon#about to read 6, iclass 22, count 0 2006.201.19:25:34.22#ibcon#read 6, iclass 22, count 0 2006.201.19:25:34.22#ibcon#end of sib2, iclass 22, count 0 2006.201.19:25:34.22#ibcon#*after write, iclass 22, count 0 2006.201.19:25:34.22#ibcon#*before return 0, iclass 22, count 0 2006.201.19:25:34.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:34.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:25:34.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:25:34.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:25:34.22$vck44/vblo=3,649.99 2006.201.19:25:34.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.19:25:34.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.19:25:34.22#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:34.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:34.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:34.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:34.22#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:25:34.22#ibcon#first serial, iclass 24, count 0 2006.201.19:25:34.22#ibcon#enter sib2, iclass 24, count 0 2006.201.19:25:34.22#ibcon#flushed, iclass 24, count 0 2006.201.19:25:34.22#ibcon#about to write, iclass 24, count 0 2006.201.19:25:34.22#ibcon#wrote, iclass 24, count 0 2006.201.19:25:34.22#ibcon#about to read 3, iclass 24, count 0 2006.201.19:25:34.24#ibcon#read 3, iclass 24, count 0 2006.201.19:25:34.24#ibcon#about to read 4, iclass 24, count 0 2006.201.19:25:34.24#ibcon#read 4, iclass 24, count 0 2006.201.19:25:34.24#ibcon#about to read 5, iclass 24, count 0 2006.201.19:25:34.24#ibcon#read 5, iclass 24, count 0 2006.201.19:25:34.24#ibcon#about to read 6, iclass 24, count 0 2006.201.19:25:34.24#ibcon#read 6, iclass 24, count 0 2006.201.19:25:34.24#ibcon#end of sib2, iclass 24, count 0 2006.201.19:25:34.24#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:25:34.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:25:34.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:25:34.24#ibcon#*before write, iclass 24, count 0 2006.201.19:25:34.24#ibcon#enter sib2, iclass 24, count 0 2006.201.19:25:34.24#ibcon#flushed, iclass 24, count 0 2006.201.19:25:34.24#ibcon#about to write, iclass 24, count 0 2006.201.19:25:34.24#ibcon#wrote, iclass 24, count 0 2006.201.19:25:34.24#ibcon#about to read 3, iclass 24, count 0 2006.201.19:25:34.28#ibcon#read 3, iclass 24, count 0 2006.201.19:25:34.28#ibcon#about to read 4, iclass 24, count 0 2006.201.19:25:34.28#ibcon#read 4, iclass 24, count 0 2006.201.19:25:34.28#ibcon#about to read 5, iclass 24, count 0 2006.201.19:25:34.28#ibcon#read 5, iclass 24, count 0 2006.201.19:25:34.28#ibcon#about to read 6, iclass 24, count 0 2006.201.19:25:34.28#ibcon#read 6, iclass 24, count 0 2006.201.19:25:34.28#ibcon#end of sib2, iclass 24, count 0 2006.201.19:25:34.28#ibcon#*after write, iclass 24, count 0 2006.201.19:25:34.28#ibcon#*before return 0, iclass 24, count 0 2006.201.19:25:34.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:34.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:25:34.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:25:34.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:25:34.28$vck44/vb=3,4 2006.201.19:25:34.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.19:25:34.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.19:25:34.28#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:34.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:34.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:34.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:34.34#ibcon#enter wrdev, iclass 26, count 2 2006.201.19:25:34.34#ibcon#first serial, iclass 26, count 2 2006.201.19:25:34.34#ibcon#enter sib2, iclass 26, count 2 2006.201.19:25:34.34#ibcon#flushed, iclass 26, count 2 2006.201.19:25:34.34#ibcon#about to write, iclass 26, count 2 2006.201.19:25:34.34#ibcon#wrote, iclass 26, count 2 2006.201.19:25:34.34#ibcon#about to read 3, iclass 26, count 2 2006.201.19:25:34.36#ibcon#read 3, iclass 26, count 2 2006.201.19:25:34.36#ibcon#about to read 4, iclass 26, count 2 2006.201.19:25:34.36#ibcon#read 4, iclass 26, count 2 2006.201.19:25:34.36#ibcon#about to read 5, iclass 26, count 2 2006.201.19:25:34.36#ibcon#read 5, iclass 26, count 2 2006.201.19:25:34.36#ibcon#about to read 6, iclass 26, count 2 2006.201.19:25:34.36#ibcon#read 6, iclass 26, count 2 2006.201.19:25:34.36#ibcon#end of sib2, iclass 26, count 2 2006.201.19:25:34.36#ibcon#*mode == 0, iclass 26, count 2 2006.201.19:25:34.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.19:25:34.36#ibcon#[27=AT03-04\r\n] 2006.201.19:25:34.36#ibcon#*before write, iclass 26, count 2 2006.201.19:25:34.36#ibcon#enter sib2, iclass 26, count 2 2006.201.19:25:34.36#ibcon#flushed, iclass 26, count 2 2006.201.19:25:34.36#ibcon#about to write, iclass 26, count 2 2006.201.19:25:34.36#ibcon#wrote, iclass 26, count 2 2006.201.19:25:34.36#ibcon#about to read 3, iclass 26, count 2 2006.201.19:25:34.39#ibcon#read 3, iclass 26, count 2 2006.201.19:25:34.39#ibcon#about to read 4, iclass 26, count 2 2006.201.19:25:34.39#ibcon#read 4, iclass 26, count 2 2006.201.19:25:34.39#ibcon#about to read 5, iclass 26, count 2 2006.201.19:25:34.39#ibcon#read 5, iclass 26, count 2 2006.201.19:25:34.39#ibcon#about to read 6, iclass 26, count 2 2006.201.19:25:34.39#ibcon#read 6, iclass 26, count 2 2006.201.19:25:34.39#ibcon#end of sib2, iclass 26, count 2 2006.201.19:25:34.39#ibcon#*after write, iclass 26, count 2 2006.201.19:25:34.39#ibcon#*before return 0, iclass 26, count 2 2006.201.19:25:34.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:34.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:25:34.39#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.19:25:34.39#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:34.39#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:34.51#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:34.51#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:34.51#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:25:34.51#ibcon#first serial, iclass 26, count 0 2006.201.19:25:34.51#ibcon#enter sib2, iclass 26, count 0 2006.201.19:25:34.51#ibcon#flushed, iclass 26, count 0 2006.201.19:25:34.51#ibcon#about to write, iclass 26, count 0 2006.201.19:25:34.51#ibcon#wrote, iclass 26, count 0 2006.201.19:25:34.51#ibcon#about to read 3, iclass 26, count 0 2006.201.19:25:34.53#ibcon#read 3, iclass 26, count 0 2006.201.19:25:34.53#ibcon#about to read 4, iclass 26, count 0 2006.201.19:25:34.53#ibcon#read 4, iclass 26, count 0 2006.201.19:25:34.53#ibcon#about to read 5, iclass 26, count 0 2006.201.19:25:34.53#ibcon#read 5, iclass 26, count 0 2006.201.19:25:34.53#ibcon#about to read 6, iclass 26, count 0 2006.201.19:25:34.53#ibcon#read 6, iclass 26, count 0 2006.201.19:25:34.53#ibcon#end of sib2, iclass 26, count 0 2006.201.19:25:34.53#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:25:34.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:25:34.53#ibcon#[27=USB\r\n] 2006.201.19:25:34.53#ibcon#*before write, iclass 26, count 0 2006.201.19:25:34.53#ibcon#enter sib2, iclass 26, count 0 2006.201.19:25:34.53#ibcon#flushed, iclass 26, count 0 2006.201.19:25:34.53#ibcon#about to write, iclass 26, count 0 2006.201.19:25:34.53#ibcon#wrote, iclass 26, count 0 2006.201.19:25:34.53#ibcon#about to read 3, iclass 26, count 0 2006.201.19:25:34.56#ibcon#read 3, iclass 26, count 0 2006.201.19:25:34.56#ibcon#about to read 4, iclass 26, count 0 2006.201.19:25:34.56#ibcon#read 4, iclass 26, count 0 2006.201.19:25:34.56#ibcon#about to read 5, iclass 26, count 0 2006.201.19:25:34.56#ibcon#read 5, iclass 26, count 0 2006.201.19:25:34.56#ibcon#about to read 6, iclass 26, count 0 2006.201.19:25:34.56#ibcon#read 6, iclass 26, count 0 2006.201.19:25:34.56#ibcon#end of sib2, iclass 26, count 0 2006.201.19:25:34.56#ibcon#*after write, iclass 26, count 0 2006.201.19:25:34.56#ibcon#*before return 0, iclass 26, count 0 2006.201.19:25:34.56#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:34.56#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:25:34.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:25:34.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:25:34.56$vck44/vblo=4,679.99 2006.201.19:25:34.56#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.19:25:34.56#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.19:25:34.56#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:34.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:34.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:34.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:34.56#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:25:34.56#ibcon#first serial, iclass 28, count 0 2006.201.19:25:34.56#ibcon#enter sib2, iclass 28, count 0 2006.201.19:25:34.56#ibcon#flushed, iclass 28, count 0 2006.201.19:25:34.56#ibcon#about to write, iclass 28, count 0 2006.201.19:25:34.56#ibcon#wrote, iclass 28, count 0 2006.201.19:25:34.56#ibcon#about to read 3, iclass 28, count 0 2006.201.19:25:34.58#ibcon#read 3, iclass 28, count 0 2006.201.19:25:34.58#ibcon#about to read 4, iclass 28, count 0 2006.201.19:25:34.58#ibcon#read 4, iclass 28, count 0 2006.201.19:25:34.58#ibcon#about to read 5, iclass 28, count 0 2006.201.19:25:34.58#ibcon#read 5, iclass 28, count 0 2006.201.19:25:34.58#ibcon#about to read 6, iclass 28, count 0 2006.201.19:25:34.58#ibcon#read 6, iclass 28, count 0 2006.201.19:25:34.58#ibcon#end of sib2, iclass 28, count 0 2006.201.19:25:34.58#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:25:34.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:25:34.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:25:34.58#ibcon#*before write, iclass 28, count 0 2006.201.19:25:34.58#ibcon#enter sib2, iclass 28, count 0 2006.201.19:25:34.58#ibcon#flushed, iclass 28, count 0 2006.201.19:25:34.58#ibcon#about to write, iclass 28, count 0 2006.201.19:25:34.58#ibcon#wrote, iclass 28, count 0 2006.201.19:25:34.58#ibcon#about to read 3, iclass 28, count 0 2006.201.19:25:34.62#ibcon#read 3, iclass 28, count 0 2006.201.19:25:34.62#ibcon#about to read 4, iclass 28, count 0 2006.201.19:25:34.62#ibcon#read 4, iclass 28, count 0 2006.201.19:25:34.62#ibcon#about to read 5, iclass 28, count 0 2006.201.19:25:34.62#ibcon#read 5, iclass 28, count 0 2006.201.19:25:34.62#ibcon#about to read 6, iclass 28, count 0 2006.201.19:25:34.62#ibcon#read 6, iclass 28, count 0 2006.201.19:25:34.62#ibcon#end of sib2, iclass 28, count 0 2006.201.19:25:34.62#ibcon#*after write, iclass 28, count 0 2006.201.19:25:34.62#ibcon#*before return 0, iclass 28, count 0 2006.201.19:25:34.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:34.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:25:34.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:25:34.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:25:34.62$vck44/vb=4,5 2006.201.19:25:34.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.19:25:34.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.19:25:34.62#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:34.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:34.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:34.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:34.68#ibcon#enter wrdev, iclass 30, count 2 2006.201.19:25:34.68#ibcon#first serial, iclass 30, count 2 2006.201.19:25:34.68#ibcon#enter sib2, iclass 30, count 2 2006.201.19:25:34.68#ibcon#flushed, iclass 30, count 2 2006.201.19:25:34.68#ibcon#about to write, iclass 30, count 2 2006.201.19:25:34.68#ibcon#wrote, iclass 30, count 2 2006.201.19:25:34.68#ibcon#about to read 3, iclass 30, count 2 2006.201.19:25:34.70#ibcon#read 3, iclass 30, count 2 2006.201.19:25:34.70#ibcon#about to read 4, iclass 30, count 2 2006.201.19:25:34.70#ibcon#read 4, iclass 30, count 2 2006.201.19:25:34.70#ibcon#about to read 5, iclass 30, count 2 2006.201.19:25:34.70#ibcon#read 5, iclass 30, count 2 2006.201.19:25:34.70#ibcon#about to read 6, iclass 30, count 2 2006.201.19:25:34.70#ibcon#read 6, iclass 30, count 2 2006.201.19:25:34.70#ibcon#end of sib2, iclass 30, count 2 2006.201.19:25:34.70#ibcon#*mode == 0, iclass 30, count 2 2006.201.19:25:34.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.19:25:34.70#ibcon#[27=AT04-05\r\n] 2006.201.19:25:34.70#ibcon#*before write, iclass 30, count 2 2006.201.19:25:34.70#ibcon#enter sib2, iclass 30, count 2 2006.201.19:25:34.70#ibcon#flushed, iclass 30, count 2 2006.201.19:25:34.70#ibcon#about to write, iclass 30, count 2 2006.201.19:25:34.70#ibcon#wrote, iclass 30, count 2 2006.201.19:25:34.70#ibcon#about to read 3, iclass 30, count 2 2006.201.19:25:34.73#ibcon#read 3, iclass 30, count 2 2006.201.19:25:34.73#ibcon#about to read 4, iclass 30, count 2 2006.201.19:25:34.73#ibcon#read 4, iclass 30, count 2 2006.201.19:25:34.73#ibcon#about to read 5, iclass 30, count 2 2006.201.19:25:34.73#ibcon#read 5, iclass 30, count 2 2006.201.19:25:34.73#ibcon#about to read 6, iclass 30, count 2 2006.201.19:25:34.73#ibcon#read 6, iclass 30, count 2 2006.201.19:25:34.73#ibcon#end of sib2, iclass 30, count 2 2006.201.19:25:34.73#ibcon#*after write, iclass 30, count 2 2006.201.19:25:34.73#ibcon#*before return 0, iclass 30, count 2 2006.201.19:25:34.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:34.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:25:34.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.19:25:34.73#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:34.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:34.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:34.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:34.85#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:25:34.85#ibcon#first serial, iclass 30, count 0 2006.201.19:25:34.85#ibcon#enter sib2, iclass 30, count 0 2006.201.19:25:34.85#ibcon#flushed, iclass 30, count 0 2006.201.19:25:34.85#ibcon#about to write, iclass 30, count 0 2006.201.19:25:34.85#ibcon#wrote, iclass 30, count 0 2006.201.19:25:34.85#ibcon#about to read 3, iclass 30, count 0 2006.201.19:25:34.87#ibcon#read 3, iclass 30, count 0 2006.201.19:25:34.87#ibcon#about to read 4, iclass 30, count 0 2006.201.19:25:34.87#ibcon#read 4, iclass 30, count 0 2006.201.19:25:34.87#ibcon#about to read 5, iclass 30, count 0 2006.201.19:25:34.87#ibcon#read 5, iclass 30, count 0 2006.201.19:25:34.87#ibcon#about to read 6, iclass 30, count 0 2006.201.19:25:34.87#ibcon#read 6, iclass 30, count 0 2006.201.19:25:34.87#ibcon#end of sib2, iclass 30, count 0 2006.201.19:25:34.87#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:25:34.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:25:34.87#ibcon#[27=USB\r\n] 2006.201.19:25:34.87#ibcon#*before write, iclass 30, count 0 2006.201.19:25:34.87#ibcon#enter sib2, iclass 30, count 0 2006.201.19:25:34.87#ibcon#flushed, iclass 30, count 0 2006.201.19:25:34.87#ibcon#about to write, iclass 30, count 0 2006.201.19:25:34.87#ibcon#wrote, iclass 30, count 0 2006.201.19:25:34.87#ibcon#about to read 3, iclass 30, count 0 2006.201.19:25:34.90#ibcon#read 3, iclass 30, count 0 2006.201.19:25:34.90#ibcon#about to read 4, iclass 30, count 0 2006.201.19:25:34.90#ibcon#read 4, iclass 30, count 0 2006.201.19:25:34.90#ibcon#about to read 5, iclass 30, count 0 2006.201.19:25:34.90#ibcon#read 5, iclass 30, count 0 2006.201.19:25:34.90#ibcon#about to read 6, iclass 30, count 0 2006.201.19:25:34.90#ibcon#read 6, iclass 30, count 0 2006.201.19:25:34.90#ibcon#end of sib2, iclass 30, count 0 2006.201.19:25:34.90#ibcon#*after write, iclass 30, count 0 2006.201.19:25:34.90#ibcon#*before return 0, iclass 30, count 0 2006.201.19:25:34.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:34.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:25:34.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:25:34.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:25:34.90$vck44/vblo=5,709.99 2006.201.19:25:34.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.19:25:34.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.19:25:34.90#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:34.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:34.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:34.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:34.90#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:25:34.90#ibcon#first serial, iclass 32, count 0 2006.201.19:25:34.90#ibcon#enter sib2, iclass 32, count 0 2006.201.19:25:34.90#ibcon#flushed, iclass 32, count 0 2006.201.19:25:34.90#ibcon#about to write, iclass 32, count 0 2006.201.19:25:34.90#ibcon#wrote, iclass 32, count 0 2006.201.19:25:34.90#ibcon#about to read 3, iclass 32, count 0 2006.201.19:25:34.92#ibcon#read 3, iclass 32, count 0 2006.201.19:25:34.92#ibcon#about to read 4, iclass 32, count 0 2006.201.19:25:34.92#ibcon#read 4, iclass 32, count 0 2006.201.19:25:34.92#ibcon#about to read 5, iclass 32, count 0 2006.201.19:25:34.92#ibcon#read 5, iclass 32, count 0 2006.201.19:25:34.92#ibcon#about to read 6, iclass 32, count 0 2006.201.19:25:34.92#ibcon#read 6, iclass 32, count 0 2006.201.19:25:34.92#ibcon#end of sib2, iclass 32, count 0 2006.201.19:25:34.92#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:25:34.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:25:34.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:25:34.92#ibcon#*before write, iclass 32, count 0 2006.201.19:25:34.92#ibcon#enter sib2, iclass 32, count 0 2006.201.19:25:34.92#ibcon#flushed, iclass 32, count 0 2006.201.19:25:34.92#ibcon#about to write, iclass 32, count 0 2006.201.19:25:34.92#ibcon#wrote, iclass 32, count 0 2006.201.19:25:34.92#ibcon#about to read 3, iclass 32, count 0 2006.201.19:25:34.96#ibcon#read 3, iclass 32, count 0 2006.201.19:25:34.96#ibcon#about to read 4, iclass 32, count 0 2006.201.19:25:34.96#ibcon#read 4, iclass 32, count 0 2006.201.19:25:34.96#ibcon#about to read 5, iclass 32, count 0 2006.201.19:25:34.96#ibcon#read 5, iclass 32, count 0 2006.201.19:25:34.96#ibcon#about to read 6, iclass 32, count 0 2006.201.19:25:34.96#ibcon#read 6, iclass 32, count 0 2006.201.19:25:34.96#ibcon#end of sib2, iclass 32, count 0 2006.201.19:25:34.96#ibcon#*after write, iclass 32, count 0 2006.201.19:25:34.96#ibcon#*before return 0, iclass 32, count 0 2006.201.19:25:34.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:34.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:25:34.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:25:34.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:25:34.96$vck44/vb=5,4 2006.201.19:25:34.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.19:25:34.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.19:25:34.96#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:34.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:35.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:35.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:35.02#ibcon#enter wrdev, iclass 34, count 2 2006.201.19:25:35.02#ibcon#first serial, iclass 34, count 2 2006.201.19:25:35.02#ibcon#enter sib2, iclass 34, count 2 2006.201.19:25:35.02#ibcon#flushed, iclass 34, count 2 2006.201.19:25:35.02#ibcon#about to write, iclass 34, count 2 2006.201.19:25:35.02#ibcon#wrote, iclass 34, count 2 2006.201.19:25:35.02#ibcon#about to read 3, iclass 34, count 2 2006.201.19:25:35.04#ibcon#read 3, iclass 34, count 2 2006.201.19:25:35.04#ibcon#about to read 4, iclass 34, count 2 2006.201.19:25:35.04#ibcon#read 4, iclass 34, count 2 2006.201.19:25:35.04#ibcon#about to read 5, iclass 34, count 2 2006.201.19:25:35.04#ibcon#read 5, iclass 34, count 2 2006.201.19:25:35.04#ibcon#about to read 6, iclass 34, count 2 2006.201.19:25:35.04#ibcon#read 6, iclass 34, count 2 2006.201.19:25:35.04#ibcon#end of sib2, iclass 34, count 2 2006.201.19:25:35.04#ibcon#*mode == 0, iclass 34, count 2 2006.201.19:25:35.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.19:25:35.04#ibcon#[27=AT05-04\r\n] 2006.201.19:25:35.04#ibcon#*before write, iclass 34, count 2 2006.201.19:25:35.04#ibcon#enter sib2, iclass 34, count 2 2006.201.19:25:35.04#ibcon#flushed, iclass 34, count 2 2006.201.19:25:35.04#ibcon#about to write, iclass 34, count 2 2006.201.19:25:35.04#ibcon#wrote, iclass 34, count 2 2006.201.19:25:35.04#ibcon#about to read 3, iclass 34, count 2 2006.201.19:25:35.07#ibcon#read 3, iclass 34, count 2 2006.201.19:25:35.07#ibcon#about to read 4, iclass 34, count 2 2006.201.19:25:35.07#ibcon#read 4, iclass 34, count 2 2006.201.19:25:35.07#ibcon#about to read 5, iclass 34, count 2 2006.201.19:25:35.07#ibcon#read 5, iclass 34, count 2 2006.201.19:25:35.07#ibcon#about to read 6, iclass 34, count 2 2006.201.19:25:35.07#ibcon#read 6, iclass 34, count 2 2006.201.19:25:35.07#ibcon#end of sib2, iclass 34, count 2 2006.201.19:25:35.07#ibcon#*after write, iclass 34, count 2 2006.201.19:25:35.07#ibcon#*before return 0, iclass 34, count 2 2006.201.19:25:35.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:35.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:25:35.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.19:25:35.07#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:35.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:35.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:35.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:35.19#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:25:35.19#ibcon#first serial, iclass 34, count 0 2006.201.19:25:35.19#ibcon#enter sib2, iclass 34, count 0 2006.201.19:25:35.19#ibcon#flushed, iclass 34, count 0 2006.201.19:25:35.19#ibcon#about to write, iclass 34, count 0 2006.201.19:25:35.19#ibcon#wrote, iclass 34, count 0 2006.201.19:25:35.19#ibcon#about to read 3, iclass 34, count 0 2006.201.19:25:35.21#ibcon#read 3, iclass 34, count 0 2006.201.19:25:35.21#ibcon#about to read 4, iclass 34, count 0 2006.201.19:25:35.21#ibcon#read 4, iclass 34, count 0 2006.201.19:25:35.21#ibcon#about to read 5, iclass 34, count 0 2006.201.19:25:35.21#ibcon#read 5, iclass 34, count 0 2006.201.19:25:35.21#ibcon#about to read 6, iclass 34, count 0 2006.201.19:25:35.21#ibcon#read 6, iclass 34, count 0 2006.201.19:25:35.21#ibcon#end of sib2, iclass 34, count 0 2006.201.19:25:35.21#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:25:35.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:25:35.21#ibcon#[27=USB\r\n] 2006.201.19:25:35.21#ibcon#*before write, iclass 34, count 0 2006.201.19:25:35.21#ibcon#enter sib2, iclass 34, count 0 2006.201.19:25:35.21#ibcon#flushed, iclass 34, count 0 2006.201.19:25:35.21#ibcon#about to write, iclass 34, count 0 2006.201.19:25:35.21#ibcon#wrote, iclass 34, count 0 2006.201.19:25:35.21#ibcon#about to read 3, iclass 34, count 0 2006.201.19:25:35.24#ibcon#read 3, iclass 34, count 0 2006.201.19:25:35.24#ibcon#about to read 4, iclass 34, count 0 2006.201.19:25:35.24#ibcon#read 4, iclass 34, count 0 2006.201.19:25:35.24#ibcon#about to read 5, iclass 34, count 0 2006.201.19:25:35.24#ibcon#read 5, iclass 34, count 0 2006.201.19:25:35.24#ibcon#about to read 6, iclass 34, count 0 2006.201.19:25:35.24#ibcon#read 6, iclass 34, count 0 2006.201.19:25:35.24#ibcon#end of sib2, iclass 34, count 0 2006.201.19:25:35.24#ibcon#*after write, iclass 34, count 0 2006.201.19:25:35.24#ibcon#*before return 0, iclass 34, count 0 2006.201.19:25:35.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:35.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:25:35.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:25:35.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:25:35.24$vck44/vblo=6,719.99 2006.201.19:25:35.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.19:25:35.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.19:25:35.24#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:35.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:35.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:35.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:35.24#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:25:35.24#ibcon#first serial, iclass 36, count 0 2006.201.19:25:35.24#ibcon#enter sib2, iclass 36, count 0 2006.201.19:25:35.24#ibcon#flushed, iclass 36, count 0 2006.201.19:25:35.24#ibcon#about to write, iclass 36, count 0 2006.201.19:25:35.24#ibcon#wrote, iclass 36, count 0 2006.201.19:25:35.24#ibcon#about to read 3, iclass 36, count 0 2006.201.19:25:35.26#ibcon#read 3, iclass 36, count 0 2006.201.19:25:35.26#ibcon#about to read 4, iclass 36, count 0 2006.201.19:25:35.26#ibcon#read 4, iclass 36, count 0 2006.201.19:25:35.26#ibcon#about to read 5, iclass 36, count 0 2006.201.19:25:35.26#ibcon#read 5, iclass 36, count 0 2006.201.19:25:35.26#ibcon#about to read 6, iclass 36, count 0 2006.201.19:25:35.26#ibcon#read 6, iclass 36, count 0 2006.201.19:25:35.26#ibcon#end of sib2, iclass 36, count 0 2006.201.19:25:35.26#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:25:35.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:25:35.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:25:35.26#ibcon#*before write, iclass 36, count 0 2006.201.19:25:35.26#ibcon#enter sib2, iclass 36, count 0 2006.201.19:25:35.26#ibcon#flushed, iclass 36, count 0 2006.201.19:25:35.26#ibcon#about to write, iclass 36, count 0 2006.201.19:25:35.26#ibcon#wrote, iclass 36, count 0 2006.201.19:25:35.26#ibcon#about to read 3, iclass 36, count 0 2006.201.19:25:35.30#ibcon#read 3, iclass 36, count 0 2006.201.19:25:35.30#ibcon#about to read 4, iclass 36, count 0 2006.201.19:25:35.30#ibcon#read 4, iclass 36, count 0 2006.201.19:25:35.30#ibcon#about to read 5, iclass 36, count 0 2006.201.19:25:35.30#ibcon#read 5, iclass 36, count 0 2006.201.19:25:35.30#ibcon#about to read 6, iclass 36, count 0 2006.201.19:25:35.30#ibcon#read 6, iclass 36, count 0 2006.201.19:25:35.30#ibcon#end of sib2, iclass 36, count 0 2006.201.19:25:35.30#ibcon#*after write, iclass 36, count 0 2006.201.19:25:35.30#ibcon#*before return 0, iclass 36, count 0 2006.201.19:25:35.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:35.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:25:35.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:25:35.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:25:35.30$vck44/vb=6,4 2006.201.19:25:35.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.19:25:35.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.19:25:35.30#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:35.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:35.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:35.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:35.36#ibcon#enter wrdev, iclass 38, count 2 2006.201.19:25:35.36#ibcon#first serial, iclass 38, count 2 2006.201.19:25:35.36#ibcon#enter sib2, iclass 38, count 2 2006.201.19:25:35.36#ibcon#flushed, iclass 38, count 2 2006.201.19:25:35.36#ibcon#about to write, iclass 38, count 2 2006.201.19:25:35.36#ibcon#wrote, iclass 38, count 2 2006.201.19:25:35.36#ibcon#about to read 3, iclass 38, count 2 2006.201.19:25:35.38#ibcon#read 3, iclass 38, count 2 2006.201.19:25:35.38#ibcon#about to read 4, iclass 38, count 2 2006.201.19:25:35.38#ibcon#read 4, iclass 38, count 2 2006.201.19:25:35.38#ibcon#about to read 5, iclass 38, count 2 2006.201.19:25:35.38#ibcon#read 5, iclass 38, count 2 2006.201.19:25:35.38#ibcon#about to read 6, iclass 38, count 2 2006.201.19:25:35.38#ibcon#read 6, iclass 38, count 2 2006.201.19:25:35.38#ibcon#end of sib2, iclass 38, count 2 2006.201.19:25:35.38#ibcon#*mode == 0, iclass 38, count 2 2006.201.19:25:35.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.19:25:35.38#ibcon#[27=AT06-04\r\n] 2006.201.19:25:35.38#ibcon#*before write, iclass 38, count 2 2006.201.19:25:35.38#ibcon#enter sib2, iclass 38, count 2 2006.201.19:25:35.38#ibcon#flushed, iclass 38, count 2 2006.201.19:25:35.38#ibcon#about to write, iclass 38, count 2 2006.201.19:25:35.38#ibcon#wrote, iclass 38, count 2 2006.201.19:25:35.38#ibcon#about to read 3, iclass 38, count 2 2006.201.19:25:35.41#ibcon#read 3, iclass 38, count 2 2006.201.19:25:35.41#ibcon#about to read 4, iclass 38, count 2 2006.201.19:25:35.41#ibcon#read 4, iclass 38, count 2 2006.201.19:25:35.41#ibcon#about to read 5, iclass 38, count 2 2006.201.19:25:35.41#ibcon#read 5, iclass 38, count 2 2006.201.19:25:35.41#ibcon#about to read 6, iclass 38, count 2 2006.201.19:25:35.41#ibcon#read 6, iclass 38, count 2 2006.201.19:25:35.41#ibcon#end of sib2, iclass 38, count 2 2006.201.19:25:35.41#ibcon#*after write, iclass 38, count 2 2006.201.19:25:35.41#ibcon#*before return 0, iclass 38, count 2 2006.201.19:25:35.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:35.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:25:35.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.19:25:35.41#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:35.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:35.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:35.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:35.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:25:35.53#ibcon#first serial, iclass 38, count 0 2006.201.19:25:35.53#ibcon#enter sib2, iclass 38, count 0 2006.201.19:25:35.53#ibcon#flushed, iclass 38, count 0 2006.201.19:25:35.53#ibcon#about to write, iclass 38, count 0 2006.201.19:25:35.53#ibcon#wrote, iclass 38, count 0 2006.201.19:25:35.53#ibcon#about to read 3, iclass 38, count 0 2006.201.19:25:35.55#ibcon#read 3, iclass 38, count 0 2006.201.19:25:35.55#ibcon#about to read 4, iclass 38, count 0 2006.201.19:25:35.55#ibcon#read 4, iclass 38, count 0 2006.201.19:25:35.55#ibcon#about to read 5, iclass 38, count 0 2006.201.19:25:35.55#ibcon#read 5, iclass 38, count 0 2006.201.19:25:35.55#ibcon#about to read 6, iclass 38, count 0 2006.201.19:25:35.55#ibcon#read 6, iclass 38, count 0 2006.201.19:25:35.55#ibcon#end of sib2, iclass 38, count 0 2006.201.19:25:35.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:25:35.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:25:35.55#ibcon#[27=USB\r\n] 2006.201.19:25:35.55#ibcon#*before write, iclass 38, count 0 2006.201.19:25:35.55#ibcon#enter sib2, iclass 38, count 0 2006.201.19:25:35.55#ibcon#flushed, iclass 38, count 0 2006.201.19:25:35.55#ibcon#about to write, iclass 38, count 0 2006.201.19:25:35.55#ibcon#wrote, iclass 38, count 0 2006.201.19:25:35.55#ibcon#about to read 3, iclass 38, count 0 2006.201.19:25:35.58#ibcon#read 3, iclass 38, count 0 2006.201.19:25:35.58#ibcon#about to read 4, iclass 38, count 0 2006.201.19:25:35.58#ibcon#read 4, iclass 38, count 0 2006.201.19:25:35.58#ibcon#about to read 5, iclass 38, count 0 2006.201.19:25:35.58#ibcon#read 5, iclass 38, count 0 2006.201.19:25:35.58#ibcon#about to read 6, iclass 38, count 0 2006.201.19:25:35.58#ibcon#read 6, iclass 38, count 0 2006.201.19:25:35.58#ibcon#end of sib2, iclass 38, count 0 2006.201.19:25:35.58#ibcon#*after write, iclass 38, count 0 2006.201.19:25:35.58#ibcon#*before return 0, iclass 38, count 0 2006.201.19:25:35.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:35.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:25:35.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:25:35.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:25:35.58$vck44/vblo=7,734.99 2006.201.19:25:35.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.19:25:35.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.19:25:35.58#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:35.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:35.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:35.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:35.58#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:25:35.58#ibcon#first serial, iclass 40, count 0 2006.201.19:25:35.58#ibcon#enter sib2, iclass 40, count 0 2006.201.19:25:35.58#ibcon#flushed, iclass 40, count 0 2006.201.19:25:35.58#ibcon#about to write, iclass 40, count 0 2006.201.19:25:35.58#ibcon#wrote, iclass 40, count 0 2006.201.19:25:35.58#ibcon#about to read 3, iclass 40, count 0 2006.201.19:25:35.60#ibcon#read 3, iclass 40, count 0 2006.201.19:25:35.60#ibcon#about to read 4, iclass 40, count 0 2006.201.19:25:35.60#ibcon#read 4, iclass 40, count 0 2006.201.19:25:35.60#ibcon#about to read 5, iclass 40, count 0 2006.201.19:25:35.60#ibcon#read 5, iclass 40, count 0 2006.201.19:25:35.60#ibcon#about to read 6, iclass 40, count 0 2006.201.19:25:35.60#ibcon#read 6, iclass 40, count 0 2006.201.19:25:35.60#ibcon#end of sib2, iclass 40, count 0 2006.201.19:25:35.60#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:25:35.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:25:35.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:25:35.60#ibcon#*before write, iclass 40, count 0 2006.201.19:25:35.60#ibcon#enter sib2, iclass 40, count 0 2006.201.19:25:35.60#ibcon#flushed, iclass 40, count 0 2006.201.19:25:35.60#ibcon#about to write, iclass 40, count 0 2006.201.19:25:35.60#ibcon#wrote, iclass 40, count 0 2006.201.19:25:35.60#ibcon#about to read 3, iclass 40, count 0 2006.201.19:25:35.65#ibcon#read 3, iclass 40, count 0 2006.201.19:25:35.65#ibcon#about to read 4, iclass 40, count 0 2006.201.19:25:35.65#ibcon#read 4, iclass 40, count 0 2006.201.19:25:35.65#ibcon#about to read 5, iclass 40, count 0 2006.201.19:25:35.65#ibcon#read 5, iclass 40, count 0 2006.201.19:25:35.65#ibcon#about to read 6, iclass 40, count 0 2006.201.19:25:35.65#ibcon#read 6, iclass 40, count 0 2006.201.19:25:35.65#ibcon#end of sib2, iclass 40, count 0 2006.201.19:25:35.65#ibcon#*after write, iclass 40, count 0 2006.201.19:25:35.65#ibcon#*before return 0, iclass 40, count 0 2006.201.19:25:35.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:35.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:25:35.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:25:35.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:25:35.65$vck44/vb=7,4 2006.201.19:25:35.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.19:25:35.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.19:25:35.65#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:35.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:25:35.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:25:35.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:25:35.70#ibcon#enter wrdev, iclass 4, count 2 2006.201.19:25:35.70#ibcon#first serial, iclass 4, count 2 2006.201.19:25:35.70#ibcon#enter sib2, iclass 4, count 2 2006.201.19:25:35.70#ibcon#flushed, iclass 4, count 2 2006.201.19:25:35.70#ibcon#about to write, iclass 4, count 2 2006.201.19:25:35.70#ibcon#wrote, iclass 4, count 2 2006.201.19:25:35.70#ibcon#about to read 3, iclass 4, count 2 2006.201.19:25:35.72#ibcon#read 3, iclass 4, count 2 2006.201.19:25:35.72#ibcon#about to read 4, iclass 4, count 2 2006.201.19:25:35.72#ibcon#read 4, iclass 4, count 2 2006.201.19:25:35.72#ibcon#about to read 5, iclass 4, count 2 2006.201.19:25:35.72#ibcon#read 5, iclass 4, count 2 2006.201.19:25:35.72#ibcon#about to read 6, iclass 4, count 2 2006.201.19:25:35.72#ibcon#read 6, iclass 4, count 2 2006.201.19:25:35.72#ibcon#end of sib2, iclass 4, count 2 2006.201.19:25:35.72#ibcon#*mode == 0, iclass 4, count 2 2006.201.19:25:35.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.19:25:35.72#ibcon#[27=AT07-04\r\n] 2006.201.19:25:35.72#ibcon#*before write, iclass 4, count 2 2006.201.19:25:35.72#ibcon#enter sib2, iclass 4, count 2 2006.201.19:25:35.72#ibcon#flushed, iclass 4, count 2 2006.201.19:25:35.72#ibcon#about to write, iclass 4, count 2 2006.201.19:25:35.72#ibcon#wrote, iclass 4, count 2 2006.201.19:25:35.72#ibcon#about to read 3, iclass 4, count 2 2006.201.19:25:35.75#ibcon#read 3, iclass 4, count 2 2006.201.19:25:35.75#ibcon#about to read 4, iclass 4, count 2 2006.201.19:25:35.75#ibcon#read 4, iclass 4, count 2 2006.201.19:25:35.75#ibcon#about to read 5, iclass 4, count 2 2006.201.19:25:35.75#ibcon#read 5, iclass 4, count 2 2006.201.19:25:35.75#ibcon#about to read 6, iclass 4, count 2 2006.201.19:25:35.75#ibcon#read 6, iclass 4, count 2 2006.201.19:25:35.75#ibcon#end of sib2, iclass 4, count 2 2006.201.19:25:35.75#ibcon#*after write, iclass 4, count 2 2006.201.19:25:35.75#ibcon#*before return 0, iclass 4, count 2 2006.201.19:25:35.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:25:35.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:25:35.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.19:25:35.75#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:35.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:25:35.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:25:35.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:25:35.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.19:25:35.87#ibcon#first serial, iclass 4, count 0 2006.201.19:25:35.87#ibcon#enter sib2, iclass 4, count 0 2006.201.19:25:35.87#ibcon#flushed, iclass 4, count 0 2006.201.19:25:35.87#ibcon#about to write, iclass 4, count 0 2006.201.19:25:35.87#ibcon#wrote, iclass 4, count 0 2006.201.19:25:35.87#ibcon#about to read 3, iclass 4, count 0 2006.201.19:25:35.89#ibcon#read 3, iclass 4, count 0 2006.201.19:25:35.89#ibcon#about to read 4, iclass 4, count 0 2006.201.19:25:35.89#ibcon#read 4, iclass 4, count 0 2006.201.19:25:35.89#ibcon#about to read 5, iclass 4, count 0 2006.201.19:25:35.89#ibcon#read 5, iclass 4, count 0 2006.201.19:25:35.89#ibcon#about to read 6, iclass 4, count 0 2006.201.19:25:35.89#ibcon#read 6, iclass 4, count 0 2006.201.19:25:35.89#ibcon#end of sib2, iclass 4, count 0 2006.201.19:25:35.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.19:25:35.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.19:25:35.89#ibcon#[27=USB\r\n] 2006.201.19:25:35.89#ibcon#*before write, iclass 4, count 0 2006.201.19:25:35.89#ibcon#enter sib2, iclass 4, count 0 2006.201.19:25:35.89#ibcon#flushed, iclass 4, count 0 2006.201.19:25:35.89#ibcon#about to write, iclass 4, count 0 2006.201.19:25:35.89#ibcon#wrote, iclass 4, count 0 2006.201.19:25:35.89#ibcon#about to read 3, iclass 4, count 0 2006.201.19:25:35.92#ibcon#read 3, iclass 4, count 0 2006.201.19:25:35.92#ibcon#about to read 4, iclass 4, count 0 2006.201.19:25:35.92#ibcon#read 4, iclass 4, count 0 2006.201.19:25:35.92#ibcon#about to read 5, iclass 4, count 0 2006.201.19:25:35.92#ibcon#read 5, iclass 4, count 0 2006.201.19:25:35.92#ibcon#about to read 6, iclass 4, count 0 2006.201.19:25:35.92#ibcon#read 6, iclass 4, count 0 2006.201.19:25:35.92#ibcon#end of sib2, iclass 4, count 0 2006.201.19:25:35.92#ibcon#*after write, iclass 4, count 0 2006.201.19:25:35.92#ibcon#*before return 0, iclass 4, count 0 2006.201.19:25:35.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:25:35.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:25:35.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.19:25:35.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.19:25:35.92$vck44/vblo=8,744.99 2006.201.19:25:35.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.19:25:35.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.19:25:35.92#ibcon#ireg 17 cls_cnt 0 2006.201.19:25:35.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:25:35.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:25:35.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:25:35.92#ibcon#enter wrdev, iclass 6, count 0 2006.201.19:25:35.92#ibcon#first serial, iclass 6, count 0 2006.201.19:25:35.92#ibcon#enter sib2, iclass 6, count 0 2006.201.19:25:35.92#ibcon#flushed, iclass 6, count 0 2006.201.19:25:35.92#ibcon#about to write, iclass 6, count 0 2006.201.19:25:35.92#ibcon#wrote, iclass 6, count 0 2006.201.19:25:35.92#ibcon#about to read 3, iclass 6, count 0 2006.201.19:25:35.94#ibcon#read 3, iclass 6, count 0 2006.201.19:25:35.94#ibcon#about to read 4, iclass 6, count 0 2006.201.19:25:35.94#ibcon#read 4, iclass 6, count 0 2006.201.19:25:35.94#ibcon#about to read 5, iclass 6, count 0 2006.201.19:25:35.94#ibcon#read 5, iclass 6, count 0 2006.201.19:25:35.94#ibcon#about to read 6, iclass 6, count 0 2006.201.19:25:35.94#ibcon#read 6, iclass 6, count 0 2006.201.19:25:35.94#ibcon#end of sib2, iclass 6, count 0 2006.201.19:25:35.94#ibcon#*mode == 0, iclass 6, count 0 2006.201.19:25:35.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.19:25:35.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:25:35.94#ibcon#*before write, iclass 6, count 0 2006.201.19:25:35.94#ibcon#enter sib2, iclass 6, count 0 2006.201.19:25:35.94#ibcon#flushed, iclass 6, count 0 2006.201.19:25:35.94#ibcon#about to write, iclass 6, count 0 2006.201.19:25:35.94#ibcon#wrote, iclass 6, count 0 2006.201.19:25:35.94#ibcon#about to read 3, iclass 6, count 0 2006.201.19:25:35.98#ibcon#read 3, iclass 6, count 0 2006.201.19:25:35.98#ibcon#about to read 4, iclass 6, count 0 2006.201.19:25:35.98#ibcon#read 4, iclass 6, count 0 2006.201.19:25:35.98#ibcon#about to read 5, iclass 6, count 0 2006.201.19:25:35.98#ibcon#read 5, iclass 6, count 0 2006.201.19:25:35.98#ibcon#about to read 6, iclass 6, count 0 2006.201.19:25:35.98#ibcon#read 6, iclass 6, count 0 2006.201.19:25:35.98#ibcon#end of sib2, iclass 6, count 0 2006.201.19:25:35.98#ibcon#*after write, iclass 6, count 0 2006.201.19:25:35.98#ibcon#*before return 0, iclass 6, count 0 2006.201.19:25:35.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:25:35.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:25:35.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.19:25:35.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.19:25:35.98$vck44/vb=8,4 2006.201.19:25:35.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.19:25:35.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.19:25:35.98#ibcon#ireg 11 cls_cnt 2 2006.201.19:25:35.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:25:36.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:25:36.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:25:36.04#ibcon#enter wrdev, iclass 10, count 2 2006.201.19:25:36.04#ibcon#first serial, iclass 10, count 2 2006.201.19:25:36.04#ibcon#enter sib2, iclass 10, count 2 2006.201.19:25:36.04#ibcon#flushed, iclass 10, count 2 2006.201.19:25:36.04#ibcon#about to write, iclass 10, count 2 2006.201.19:25:36.04#ibcon#wrote, iclass 10, count 2 2006.201.19:25:36.04#ibcon#about to read 3, iclass 10, count 2 2006.201.19:25:36.06#ibcon#read 3, iclass 10, count 2 2006.201.19:25:36.06#ibcon#about to read 4, iclass 10, count 2 2006.201.19:25:36.06#ibcon#read 4, iclass 10, count 2 2006.201.19:25:36.06#ibcon#about to read 5, iclass 10, count 2 2006.201.19:25:36.06#ibcon#read 5, iclass 10, count 2 2006.201.19:25:36.06#ibcon#about to read 6, iclass 10, count 2 2006.201.19:25:36.06#ibcon#read 6, iclass 10, count 2 2006.201.19:25:36.06#ibcon#end of sib2, iclass 10, count 2 2006.201.19:25:36.06#ibcon#*mode == 0, iclass 10, count 2 2006.201.19:25:36.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.19:25:36.06#ibcon#[27=AT08-04\r\n] 2006.201.19:25:36.06#ibcon#*before write, iclass 10, count 2 2006.201.19:25:36.06#ibcon#enter sib2, iclass 10, count 2 2006.201.19:25:36.06#ibcon#flushed, iclass 10, count 2 2006.201.19:25:36.06#ibcon#about to write, iclass 10, count 2 2006.201.19:25:36.06#ibcon#wrote, iclass 10, count 2 2006.201.19:25:36.06#ibcon#about to read 3, iclass 10, count 2 2006.201.19:25:36.09#ibcon#read 3, iclass 10, count 2 2006.201.19:25:36.09#ibcon#about to read 4, iclass 10, count 2 2006.201.19:25:36.09#ibcon#read 4, iclass 10, count 2 2006.201.19:25:36.09#ibcon#about to read 5, iclass 10, count 2 2006.201.19:25:36.09#ibcon#read 5, iclass 10, count 2 2006.201.19:25:36.09#ibcon#about to read 6, iclass 10, count 2 2006.201.19:25:36.09#ibcon#read 6, iclass 10, count 2 2006.201.19:25:36.09#ibcon#end of sib2, iclass 10, count 2 2006.201.19:25:36.09#ibcon#*after write, iclass 10, count 2 2006.201.19:25:36.09#ibcon#*before return 0, iclass 10, count 2 2006.201.19:25:36.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:25:36.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:25:36.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.19:25:36.09#ibcon#ireg 7 cls_cnt 0 2006.201.19:25:36.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:25:36.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:25:36.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:25:36.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:25:36.21#ibcon#first serial, iclass 10, count 0 2006.201.19:25:36.21#ibcon#enter sib2, iclass 10, count 0 2006.201.19:25:36.21#ibcon#flushed, iclass 10, count 0 2006.201.19:25:36.21#ibcon#about to write, iclass 10, count 0 2006.201.19:25:36.21#ibcon#wrote, iclass 10, count 0 2006.201.19:25:36.21#ibcon#about to read 3, iclass 10, count 0 2006.201.19:25:36.23#ibcon#read 3, iclass 10, count 0 2006.201.19:25:36.23#ibcon#about to read 4, iclass 10, count 0 2006.201.19:25:36.23#ibcon#read 4, iclass 10, count 0 2006.201.19:25:36.23#ibcon#about to read 5, iclass 10, count 0 2006.201.19:25:36.23#ibcon#read 5, iclass 10, count 0 2006.201.19:25:36.23#ibcon#about to read 6, iclass 10, count 0 2006.201.19:25:36.23#ibcon#read 6, iclass 10, count 0 2006.201.19:25:36.23#ibcon#end of sib2, iclass 10, count 0 2006.201.19:25:36.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:25:36.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:25:36.23#ibcon#[27=USB\r\n] 2006.201.19:25:36.23#ibcon#*before write, iclass 10, count 0 2006.201.19:25:36.23#ibcon#enter sib2, iclass 10, count 0 2006.201.19:25:36.23#ibcon#flushed, iclass 10, count 0 2006.201.19:25:36.23#ibcon#about to write, iclass 10, count 0 2006.201.19:25:36.23#ibcon#wrote, iclass 10, count 0 2006.201.19:25:36.23#ibcon#about to read 3, iclass 10, count 0 2006.201.19:25:36.26#ibcon#read 3, iclass 10, count 0 2006.201.19:25:36.26#ibcon#about to read 4, iclass 10, count 0 2006.201.19:25:36.26#ibcon#read 4, iclass 10, count 0 2006.201.19:25:36.26#ibcon#about to read 5, iclass 10, count 0 2006.201.19:25:36.26#ibcon#read 5, iclass 10, count 0 2006.201.19:25:36.26#ibcon#about to read 6, iclass 10, count 0 2006.201.19:25:36.26#ibcon#read 6, iclass 10, count 0 2006.201.19:25:36.26#ibcon#end of sib2, iclass 10, count 0 2006.201.19:25:36.26#ibcon#*after write, iclass 10, count 0 2006.201.19:25:36.26#ibcon#*before return 0, iclass 10, count 0 2006.201.19:25:36.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:25:36.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:25:36.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:25:36.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:25:36.26$vck44/vabw=wide 2006.201.19:25:36.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.19:25:36.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.19:25:36.26#ibcon#ireg 8 cls_cnt 0 2006.201.19:25:36.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:36.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:36.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:36.26#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:25:36.26#ibcon#first serial, iclass 12, count 0 2006.201.19:25:36.26#ibcon#enter sib2, iclass 12, count 0 2006.201.19:25:36.26#ibcon#flushed, iclass 12, count 0 2006.201.19:25:36.26#ibcon#about to write, iclass 12, count 0 2006.201.19:25:36.26#ibcon#wrote, iclass 12, count 0 2006.201.19:25:36.26#ibcon#about to read 3, iclass 12, count 0 2006.201.19:25:36.28#ibcon#read 3, iclass 12, count 0 2006.201.19:25:36.28#ibcon#about to read 4, iclass 12, count 0 2006.201.19:25:36.28#ibcon#read 4, iclass 12, count 0 2006.201.19:25:36.28#ibcon#about to read 5, iclass 12, count 0 2006.201.19:25:36.28#ibcon#read 5, iclass 12, count 0 2006.201.19:25:36.28#ibcon#about to read 6, iclass 12, count 0 2006.201.19:25:36.28#ibcon#read 6, iclass 12, count 0 2006.201.19:25:36.28#ibcon#end of sib2, iclass 12, count 0 2006.201.19:25:36.28#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:25:36.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:25:36.28#ibcon#[25=BW32\r\n] 2006.201.19:25:36.28#ibcon#*before write, iclass 12, count 0 2006.201.19:25:36.28#ibcon#enter sib2, iclass 12, count 0 2006.201.19:25:36.28#ibcon#flushed, iclass 12, count 0 2006.201.19:25:36.28#ibcon#about to write, iclass 12, count 0 2006.201.19:25:36.28#ibcon#wrote, iclass 12, count 0 2006.201.19:25:36.28#ibcon#about to read 3, iclass 12, count 0 2006.201.19:25:36.31#ibcon#read 3, iclass 12, count 0 2006.201.19:25:36.31#ibcon#about to read 4, iclass 12, count 0 2006.201.19:25:36.31#ibcon#read 4, iclass 12, count 0 2006.201.19:25:36.31#ibcon#about to read 5, iclass 12, count 0 2006.201.19:25:36.31#ibcon#read 5, iclass 12, count 0 2006.201.19:25:36.31#ibcon#about to read 6, iclass 12, count 0 2006.201.19:25:36.31#ibcon#read 6, iclass 12, count 0 2006.201.19:25:36.31#ibcon#end of sib2, iclass 12, count 0 2006.201.19:25:36.31#ibcon#*after write, iclass 12, count 0 2006.201.19:25:36.31#ibcon#*before return 0, iclass 12, count 0 2006.201.19:25:36.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:36.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:25:36.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:25:36.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:25:36.31$vck44/vbbw=wide 2006.201.19:25:36.31#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.19:25:36.31#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.19:25:36.31#ibcon#ireg 8 cls_cnt 0 2006.201.19:25:36.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:25:36.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:25:36.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:25:36.38#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:25:36.38#ibcon#first serial, iclass 14, count 0 2006.201.19:25:36.38#ibcon#enter sib2, iclass 14, count 0 2006.201.19:25:36.38#ibcon#flushed, iclass 14, count 0 2006.201.19:25:36.38#ibcon#about to write, iclass 14, count 0 2006.201.19:25:36.38#ibcon#wrote, iclass 14, count 0 2006.201.19:25:36.38#ibcon#about to read 3, iclass 14, count 0 2006.201.19:25:36.40#ibcon#read 3, iclass 14, count 0 2006.201.19:25:36.40#ibcon#about to read 4, iclass 14, count 0 2006.201.19:25:36.40#ibcon#read 4, iclass 14, count 0 2006.201.19:25:36.40#ibcon#about to read 5, iclass 14, count 0 2006.201.19:25:36.40#ibcon#read 5, iclass 14, count 0 2006.201.19:25:36.40#ibcon#about to read 6, iclass 14, count 0 2006.201.19:25:36.40#ibcon#read 6, iclass 14, count 0 2006.201.19:25:36.40#ibcon#end of sib2, iclass 14, count 0 2006.201.19:25:36.40#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:25:36.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:25:36.40#ibcon#[27=BW32\r\n] 2006.201.19:25:36.40#ibcon#*before write, iclass 14, count 0 2006.201.19:25:36.40#ibcon#enter sib2, iclass 14, count 0 2006.201.19:25:36.40#ibcon#flushed, iclass 14, count 0 2006.201.19:25:36.40#ibcon#about to write, iclass 14, count 0 2006.201.19:25:36.40#ibcon#wrote, iclass 14, count 0 2006.201.19:25:36.40#ibcon#about to read 3, iclass 14, count 0 2006.201.19:25:36.43#ibcon#read 3, iclass 14, count 0 2006.201.19:25:36.43#ibcon#about to read 4, iclass 14, count 0 2006.201.19:25:36.43#ibcon#read 4, iclass 14, count 0 2006.201.19:25:36.43#ibcon#about to read 5, iclass 14, count 0 2006.201.19:25:36.43#ibcon#read 5, iclass 14, count 0 2006.201.19:25:36.43#ibcon#about to read 6, iclass 14, count 0 2006.201.19:25:36.43#ibcon#read 6, iclass 14, count 0 2006.201.19:25:36.43#ibcon#end of sib2, iclass 14, count 0 2006.201.19:25:36.43#ibcon#*after write, iclass 14, count 0 2006.201.19:25:36.43#ibcon#*before return 0, iclass 14, count 0 2006.201.19:25:36.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:25:36.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:25:36.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:25:36.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:25:36.43$setupk4/ifdk4 2006.201.19:25:36.43$ifdk4/lo= 2006.201.19:25:36.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:25:36.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:25:36.43$ifdk4/patch= 2006.201.19:25:36.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:25:36.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:25:36.43$setupk4/!*+20s 2006.201.19:25:43.15#abcon#<5=/03 0.9 2.2 20.491001002.4\r\n> 2006.201.19:25:43.17#abcon#{5=INTERFACE CLEAR} 2006.201.19:25:43.23#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:25:50.94$setupk4/"tpicd 2006.201.19:25:50.94$setupk4/echo=off 2006.201.19:25:50.94$setupk4/xlog=off 2006.201.19:25:50.94:!2006.201.19:31:34 2006.201.19:26:23.13#trakl#Source acquired 2006.201.19:26:24.13#flagr#flagr/antenna,acquired 2006.201.19:31:34.00:preob 2006.201.19:31:34.14/onsource/TRACKING 2006.201.19:31:34.14:!2006.201.19:31:44 2006.201.19:31:44.00:"tape 2006.201.19:31:44.00:"st=record 2006.201.19:31:44.00:data_valid=on 2006.201.19:31:44.00:midob 2006.201.19:31:45.14/onsource/TRACKING 2006.201.19:31:45.14/wx/20.45,1002.4,100 2006.201.19:31:45.26/cable/+6.4787E-03 2006.201.19:31:46.35/va/01,08,usb,yes,57,61 2006.201.19:31:46.35/va/02,07,usb,yes,61,62 2006.201.19:31:46.35/va/03,08,usb,yes,56,58 2006.201.19:31:46.35/va/04,07,usb,yes,63,66 2006.201.19:31:46.35/va/05,04,usb,yes,56,58 2006.201.19:31:46.35/va/06,05,usb,yes,57,57 2006.201.19:31:46.35/va/07,05,usb,yes,56,57 2006.201.19:31:46.35/va/08,04,usb,yes,55,65 2006.201.19:31:46.58/valo/01,524.99,yes,locked 2006.201.19:31:46.58/valo/02,534.99,yes,locked 2006.201.19:31:46.58/valo/03,564.99,yes,locked 2006.201.19:31:46.58/valo/04,624.99,yes,locked 2006.201.19:31:46.58/valo/05,734.99,yes,locked 2006.201.19:31:46.58/valo/06,814.99,yes,locked 2006.201.19:31:46.58/valo/07,864.99,yes,locked 2006.201.19:31:46.58/valo/08,884.99,yes,locked 2006.201.19:31:47.67/vb/01,04,usb,yes,33,30 2006.201.19:31:47.67/vb/02,05,usb,yes,31,31 2006.201.19:31:47.67/vb/03,04,usb,yes,32,35 2006.201.19:31:47.67/vb/04,05,usb,yes,32,31 2006.201.19:31:47.67/vb/05,04,usb,yes,29,31 2006.201.19:31:47.67/vb/06,04,usb,yes,33,29 2006.201.19:31:47.67/vb/07,04,usb,yes,33,33 2006.201.19:31:47.67/vb/08,04,usb,yes,30,34 2006.201.19:31:47.91/vblo/01,629.99,yes,locked 2006.201.19:31:47.91/vblo/02,634.99,yes,locked 2006.201.19:31:47.91/vblo/03,649.99,yes,locked 2006.201.19:31:47.91/vblo/04,679.99,yes,locked 2006.201.19:31:47.91/vblo/05,709.99,yes,locked 2006.201.19:31:47.91/vblo/06,719.99,yes,locked 2006.201.19:31:47.91/vblo/07,734.99,yes,locked 2006.201.19:31:47.91/vblo/08,744.99,yes,locked 2006.201.19:31:48.06/vabw/8 2006.201.19:31:48.21/vbbw/8 2006.201.19:31:48.36/xfe/off,on,15.2 2006.201.19:31:48.74/ifatt/23,28,28,28 2006.201.19:31:49.06/fmout-gps/S +4.48E-07 2006.201.19:31:49.13:!2006.201.19:35:54 2006.201.19:35:54.00:data_valid=off 2006.201.19:35:54.00:"et 2006.201.19:35:54.00:!+3s 2006.201.19:35:57.02:"tape 2006.201.19:35:57.02:postob 2006.201.19:35:57.18/cable/+6.4784E-03 2006.201.19:35:57.18/wx/20.44,1002.3,100 2006.201.19:35:57.26/fmout-gps/S +4.48E-07 2006.201.19:35:57.26:scan_name=201-1945,jd0607,50 2006.201.19:35:57.26:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.201.19:35:59.13#flagr#flagr/antenna,new-source 2006.201.19:35:59.13:checkk5 2006.201.19:35:59.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:35:59.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:36:00.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:36:00.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:36:01.02/chk_obsdata//k5ts1/T2011931??a.dat file size is correct (nominal:1000MB, actual:996MB). 2006.201.19:36:01.39/chk_obsdata//k5ts2/T2011931??b.dat file size is correct (nominal:1000MB, actual:996MB). 2006.201.19:36:01.75/chk_obsdata//k5ts3/T2011931??c.dat file size is correct (nominal:1000MB, actual:996MB). 2006.201.19:36:02.12/chk_obsdata//k5ts4/T2011931??d.dat file size is correct (nominal:1000MB, actual:996MB). 2006.201.19:36:02.81/k5log//k5ts1_log_newline 2006.201.19:36:03.49/k5log//k5ts2_log_newline 2006.201.19:36:04.18/k5log//k5ts3_log_newline 2006.201.19:36:04.86/k5log//k5ts4_log_newline 2006.201.19:36:04.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:36:04.88:setupk4=1 2006.201.19:36:04.88$setupk4/echo=on 2006.201.19:36:04.88$setupk4/pcalon 2006.201.19:36:04.88$pcalon/"no phase cal control is implemented here 2006.201.19:36:04.88$setupk4/"tpicd=stop 2006.201.19:36:04.88$setupk4/"rec=synch_on 2006.201.19:36:04.88$setupk4/"rec_mode=128 2006.201.19:36:04.88$setupk4/!* 2006.201.19:36:04.88$setupk4/recpk4 2006.201.19:36:04.88$recpk4/recpatch= 2006.201.19:36:04.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:36:04.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:36:04.89$setupk4/vck44 2006.201.19:36:04.89$vck44/valo=1,524.99 2006.201.19:36:04.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.19:36:04.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.19:36:04.89#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:04.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:04.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:04.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:04.89#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:36:04.89#ibcon#first serial, iclass 15, count 0 2006.201.19:36:04.89#ibcon#enter sib2, iclass 15, count 0 2006.201.19:36:04.89#ibcon#flushed, iclass 15, count 0 2006.201.19:36:04.89#ibcon#about to write, iclass 15, count 0 2006.201.19:36:04.89#ibcon#wrote, iclass 15, count 0 2006.201.19:36:04.89#ibcon#about to read 3, iclass 15, count 0 2006.201.19:36:04.92#ibcon#read 3, iclass 15, count 0 2006.201.19:36:04.92#ibcon#about to read 4, iclass 15, count 0 2006.201.19:36:04.92#ibcon#read 4, iclass 15, count 0 2006.201.19:36:04.92#ibcon#about to read 5, iclass 15, count 0 2006.201.19:36:04.92#ibcon#read 5, iclass 15, count 0 2006.201.19:36:04.92#ibcon#about to read 6, iclass 15, count 0 2006.201.19:36:04.92#ibcon#read 6, iclass 15, count 0 2006.201.19:36:04.92#ibcon#end of sib2, iclass 15, count 0 2006.201.19:36:04.92#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:36:04.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:36:04.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:36:04.92#ibcon#*before write, iclass 15, count 0 2006.201.19:36:04.92#ibcon#enter sib2, iclass 15, count 0 2006.201.19:36:04.92#ibcon#flushed, iclass 15, count 0 2006.201.19:36:04.92#ibcon#about to write, iclass 15, count 0 2006.201.19:36:04.92#ibcon#wrote, iclass 15, count 0 2006.201.19:36:04.92#ibcon#about to read 3, iclass 15, count 0 2006.201.19:36:04.98#ibcon#read 3, iclass 15, count 0 2006.201.19:36:04.98#ibcon#about to read 4, iclass 15, count 0 2006.201.19:36:04.98#ibcon#read 4, iclass 15, count 0 2006.201.19:36:04.98#ibcon#about to read 5, iclass 15, count 0 2006.201.19:36:04.98#ibcon#read 5, iclass 15, count 0 2006.201.19:36:04.98#ibcon#about to read 6, iclass 15, count 0 2006.201.19:36:04.98#ibcon#read 6, iclass 15, count 0 2006.201.19:36:04.98#ibcon#end of sib2, iclass 15, count 0 2006.201.19:36:04.98#ibcon#*after write, iclass 15, count 0 2006.201.19:36:04.98#ibcon#*before return 0, iclass 15, count 0 2006.201.19:36:04.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:04.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:04.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:36:04.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:36:04.98$vck44/va=1,8 2006.201.19:36:04.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.19:36:04.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.19:36:04.98#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:04.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:04.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:04.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:04.98#ibcon#enter wrdev, iclass 17, count 2 2006.201.19:36:04.98#ibcon#first serial, iclass 17, count 2 2006.201.19:36:04.98#ibcon#enter sib2, iclass 17, count 2 2006.201.19:36:04.98#ibcon#flushed, iclass 17, count 2 2006.201.19:36:04.98#ibcon#about to write, iclass 17, count 2 2006.201.19:36:04.98#ibcon#wrote, iclass 17, count 2 2006.201.19:36:04.98#ibcon#about to read 3, iclass 17, count 2 2006.201.19:36:05.00#ibcon#read 3, iclass 17, count 2 2006.201.19:36:05.00#ibcon#about to read 4, iclass 17, count 2 2006.201.19:36:05.00#ibcon#read 4, iclass 17, count 2 2006.201.19:36:05.00#ibcon#about to read 5, iclass 17, count 2 2006.201.19:36:05.00#ibcon#read 5, iclass 17, count 2 2006.201.19:36:05.00#ibcon#about to read 6, iclass 17, count 2 2006.201.19:36:05.00#ibcon#read 6, iclass 17, count 2 2006.201.19:36:05.00#ibcon#end of sib2, iclass 17, count 2 2006.201.19:36:05.00#ibcon#*mode == 0, iclass 17, count 2 2006.201.19:36:05.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.19:36:05.00#ibcon#[25=AT01-08\r\n] 2006.201.19:36:05.00#ibcon#*before write, iclass 17, count 2 2006.201.19:36:05.00#ibcon#enter sib2, iclass 17, count 2 2006.201.19:36:05.00#ibcon#flushed, iclass 17, count 2 2006.201.19:36:05.00#ibcon#about to write, iclass 17, count 2 2006.201.19:36:05.00#ibcon#wrote, iclass 17, count 2 2006.201.19:36:05.00#ibcon#about to read 3, iclass 17, count 2 2006.201.19:36:05.04#ibcon#read 3, iclass 17, count 2 2006.201.19:36:05.04#ibcon#about to read 4, iclass 17, count 2 2006.201.19:36:05.04#ibcon#read 4, iclass 17, count 2 2006.201.19:36:05.04#ibcon#about to read 5, iclass 17, count 2 2006.201.19:36:05.04#ibcon#read 5, iclass 17, count 2 2006.201.19:36:05.04#ibcon#about to read 6, iclass 17, count 2 2006.201.19:36:05.04#ibcon#read 6, iclass 17, count 2 2006.201.19:36:05.04#ibcon#end of sib2, iclass 17, count 2 2006.201.19:36:05.04#ibcon#*after write, iclass 17, count 2 2006.201.19:36:05.04#ibcon#*before return 0, iclass 17, count 2 2006.201.19:36:05.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:05.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:05.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.19:36:05.04#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:05.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:05.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:05.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:05.16#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:36:05.16#ibcon#first serial, iclass 17, count 0 2006.201.19:36:05.16#ibcon#enter sib2, iclass 17, count 0 2006.201.19:36:05.16#ibcon#flushed, iclass 17, count 0 2006.201.19:36:05.16#ibcon#about to write, iclass 17, count 0 2006.201.19:36:05.16#ibcon#wrote, iclass 17, count 0 2006.201.19:36:05.16#ibcon#about to read 3, iclass 17, count 0 2006.201.19:36:05.19#ibcon#read 3, iclass 17, count 0 2006.201.19:36:05.19#ibcon#about to read 4, iclass 17, count 0 2006.201.19:36:05.19#ibcon#read 4, iclass 17, count 0 2006.201.19:36:05.19#ibcon#about to read 5, iclass 17, count 0 2006.201.19:36:05.19#ibcon#read 5, iclass 17, count 0 2006.201.19:36:05.19#ibcon#about to read 6, iclass 17, count 0 2006.201.19:36:05.19#ibcon#read 6, iclass 17, count 0 2006.201.19:36:05.19#ibcon#end of sib2, iclass 17, count 0 2006.201.19:36:05.19#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:36:05.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:36:05.19#ibcon#[25=USB\r\n] 2006.201.19:36:05.19#ibcon#*before write, iclass 17, count 0 2006.201.19:36:05.19#ibcon#enter sib2, iclass 17, count 0 2006.201.19:36:05.19#ibcon#flushed, iclass 17, count 0 2006.201.19:36:05.19#ibcon#about to write, iclass 17, count 0 2006.201.19:36:05.19#ibcon#wrote, iclass 17, count 0 2006.201.19:36:05.19#ibcon#about to read 3, iclass 17, count 0 2006.201.19:36:05.22#ibcon#read 3, iclass 17, count 0 2006.201.19:36:05.22#ibcon#about to read 4, iclass 17, count 0 2006.201.19:36:05.22#ibcon#read 4, iclass 17, count 0 2006.201.19:36:05.22#ibcon#about to read 5, iclass 17, count 0 2006.201.19:36:05.22#ibcon#read 5, iclass 17, count 0 2006.201.19:36:05.22#ibcon#about to read 6, iclass 17, count 0 2006.201.19:36:05.22#ibcon#read 6, iclass 17, count 0 2006.201.19:36:05.22#ibcon#end of sib2, iclass 17, count 0 2006.201.19:36:05.22#ibcon#*after write, iclass 17, count 0 2006.201.19:36:05.22#ibcon#*before return 0, iclass 17, count 0 2006.201.19:36:05.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:05.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:05.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:36:05.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:36:05.22$vck44/valo=2,534.99 2006.201.19:36:05.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.19:36:05.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.19:36:05.22#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:05.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:05.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:05.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:05.22#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:36:05.22#ibcon#first serial, iclass 19, count 0 2006.201.19:36:05.22#ibcon#enter sib2, iclass 19, count 0 2006.201.19:36:05.22#ibcon#flushed, iclass 19, count 0 2006.201.19:36:05.22#ibcon#about to write, iclass 19, count 0 2006.201.19:36:05.22#ibcon#wrote, iclass 19, count 0 2006.201.19:36:05.22#ibcon#about to read 3, iclass 19, count 0 2006.201.19:36:05.24#ibcon#read 3, iclass 19, count 0 2006.201.19:36:05.24#ibcon#about to read 4, iclass 19, count 0 2006.201.19:36:05.24#ibcon#read 4, iclass 19, count 0 2006.201.19:36:05.24#ibcon#about to read 5, iclass 19, count 0 2006.201.19:36:05.24#ibcon#read 5, iclass 19, count 0 2006.201.19:36:05.24#ibcon#about to read 6, iclass 19, count 0 2006.201.19:36:05.24#ibcon#read 6, iclass 19, count 0 2006.201.19:36:05.24#ibcon#end of sib2, iclass 19, count 0 2006.201.19:36:05.24#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:36:05.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:36:05.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:36:05.24#ibcon#*before write, iclass 19, count 0 2006.201.19:36:05.24#ibcon#enter sib2, iclass 19, count 0 2006.201.19:36:05.24#ibcon#flushed, iclass 19, count 0 2006.201.19:36:05.24#ibcon#about to write, iclass 19, count 0 2006.201.19:36:05.24#ibcon#wrote, iclass 19, count 0 2006.201.19:36:05.24#ibcon#about to read 3, iclass 19, count 0 2006.201.19:36:05.28#ibcon#read 3, iclass 19, count 0 2006.201.19:36:05.28#ibcon#about to read 4, iclass 19, count 0 2006.201.19:36:05.28#ibcon#read 4, iclass 19, count 0 2006.201.19:36:05.28#ibcon#about to read 5, iclass 19, count 0 2006.201.19:36:05.28#ibcon#read 5, iclass 19, count 0 2006.201.19:36:05.28#ibcon#about to read 6, iclass 19, count 0 2006.201.19:36:05.28#ibcon#read 6, iclass 19, count 0 2006.201.19:36:05.28#ibcon#end of sib2, iclass 19, count 0 2006.201.19:36:05.28#ibcon#*after write, iclass 19, count 0 2006.201.19:36:05.28#ibcon#*before return 0, iclass 19, count 0 2006.201.19:36:05.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:05.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:05.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:36:05.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:36:05.28$vck44/va=2,7 2006.201.19:36:05.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.19:36:05.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.19:36:05.28#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:05.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:05.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:05.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:05.34#ibcon#enter wrdev, iclass 21, count 2 2006.201.19:36:05.34#ibcon#first serial, iclass 21, count 2 2006.201.19:36:05.34#ibcon#enter sib2, iclass 21, count 2 2006.201.19:36:05.34#ibcon#flushed, iclass 21, count 2 2006.201.19:36:05.34#ibcon#about to write, iclass 21, count 2 2006.201.19:36:05.34#ibcon#wrote, iclass 21, count 2 2006.201.19:36:05.34#ibcon#about to read 3, iclass 21, count 2 2006.201.19:36:05.36#ibcon#read 3, iclass 21, count 2 2006.201.19:36:05.36#ibcon#about to read 4, iclass 21, count 2 2006.201.19:36:05.36#ibcon#read 4, iclass 21, count 2 2006.201.19:36:05.36#ibcon#about to read 5, iclass 21, count 2 2006.201.19:36:05.36#ibcon#read 5, iclass 21, count 2 2006.201.19:36:05.36#ibcon#about to read 6, iclass 21, count 2 2006.201.19:36:05.36#ibcon#read 6, iclass 21, count 2 2006.201.19:36:05.36#ibcon#end of sib2, iclass 21, count 2 2006.201.19:36:05.36#ibcon#*mode == 0, iclass 21, count 2 2006.201.19:36:05.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.19:36:05.36#ibcon#[25=AT02-07\r\n] 2006.201.19:36:05.36#ibcon#*before write, iclass 21, count 2 2006.201.19:36:05.36#ibcon#enter sib2, iclass 21, count 2 2006.201.19:36:05.36#ibcon#flushed, iclass 21, count 2 2006.201.19:36:05.36#ibcon#about to write, iclass 21, count 2 2006.201.19:36:05.36#ibcon#wrote, iclass 21, count 2 2006.201.19:36:05.36#ibcon#about to read 3, iclass 21, count 2 2006.201.19:36:05.39#ibcon#read 3, iclass 21, count 2 2006.201.19:36:05.39#ibcon#about to read 4, iclass 21, count 2 2006.201.19:36:05.39#ibcon#read 4, iclass 21, count 2 2006.201.19:36:05.39#ibcon#about to read 5, iclass 21, count 2 2006.201.19:36:05.39#ibcon#read 5, iclass 21, count 2 2006.201.19:36:05.39#ibcon#about to read 6, iclass 21, count 2 2006.201.19:36:05.39#ibcon#read 6, iclass 21, count 2 2006.201.19:36:05.39#ibcon#end of sib2, iclass 21, count 2 2006.201.19:36:05.39#ibcon#*after write, iclass 21, count 2 2006.201.19:36:05.39#ibcon#*before return 0, iclass 21, count 2 2006.201.19:36:05.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:05.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:05.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.19:36:05.39#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:05.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:05.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:05.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:05.51#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:36:05.51#ibcon#first serial, iclass 21, count 0 2006.201.19:36:05.51#ibcon#enter sib2, iclass 21, count 0 2006.201.19:36:05.51#ibcon#flushed, iclass 21, count 0 2006.201.19:36:05.51#ibcon#about to write, iclass 21, count 0 2006.201.19:36:05.51#ibcon#wrote, iclass 21, count 0 2006.201.19:36:05.51#ibcon#about to read 3, iclass 21, count 0 2006.201.19:36:05.53#ibcon#read 3, iclass 21, count 0 2006.201.19:36:05.53#ibcon#about to read 4, iclass 21, count 0 2006.201.19:36:05.53#ibcon#read 4, iclass 21, count 0 2006.201.19:36:05.53#ibcon#about to read 5, iclass 21, count 0 2006.201.19:36:05.53#ibcon#read 5, iclass 21, count 0 2006.201.19:36:05.53#ibcon#about to read 6, iclass 21, count 0 2006.201.19:36:05.53#ibcon#read 6, iclass 21, count 0 2006.201.19:36:05.53#ibcon#end of sib2, iclass 21, count 0 2006.201.19:36:05.53#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:36:05.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:36:05.53#ibcon#[25=USB\r\n] 2006.201.19:36:05.53#ibcon#*before write, iclass 21, count 0 2006.201.19:36:05.53#ibcon#enter sib2, iclass 21, count 0 2006.201.19:36:05.53#ibcon#flushed, iclass 21, count 0 2006.201.19:36:05.53#ibcon#about to write, iclass 21, count 0 2006.201.19:36:05.53#ibcon#wrote, iclass 21, count 0 2006.201.19:36:05.53#ibcon#about to read 3, iclass 21, count 0 2006.201.19:36:05.56#ibcon#read 3, iclass 21, count 0 2006.201.19:36:05.56#ibcon#about to read 4, iclass 21, count 0 2006.201.19:36:05.56#ibcon#read 4, iclass 21, count 0 2006.201.19:36:05.56#ibcon#about to read 5, iclass 21, count 0 2006.201.19:36:05.56#ibcon#read 5, iclass 21, count 0 2006.201.19:36:05.56#ibcon#about to read 6, iclass 21, count 0 2006.201.19:36:05.56#ibcon#read 6, iclass 21, count 0 2006.201.19:36:05.56#ibcon#end of sib2, iclass 21, count 0 2006.201.19:36:05.56#ibcon#*after write, iclass 21, count 0 2006.201.19:36:05.56#ibcon#*before return 0, iclass 21, count 0 2006.201.19:36:05.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:05.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:05.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:36:05.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:36:05.56$vck44/valo=3,564.99 2006.201.19:36:05.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.19:36:05.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.19:36:05.56#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:05.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:05.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:05.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:05.56#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:36:05.56#ibcon#first serial, iclass 23, count 0 2006.201.19:36:05.56#ibcon#enter sib2, iclass 23, count 0 2006.201.19:36:05.56#ibcon#flushed, iclass 23, count 0 2006.201.19:36:05.56#ibcon#about to write, iclass 23, count 0 2006.201.19:36:05.56#ibcon#wrote, iclass 23, count 0 2006.201.19:36:05.56#ibcon#about to read 3, iclass 23, count 0 2006.201.19:36:05.58#ibcon#read 3, iclass 23, count 0 2006.201.19:36:05.58#ibcon#about to read 4, iclass 23, count 0 2006.201.19:36:05.58#ibcon#read 4, iclass 23, count 0 2006.201.19:36:05.58#ibcon#about to read 5, iclass 23, count 0 2006.201.19:36:05.58#ibcon#read 5, iclass 23, count 0 2006.201.19:36:05.58#ibcon#about to read 6, iclass 23, count 0 2006.201.19:36:05.58#ibcon#read 6, iclass 23, count 0 2006.201.19:36:05.58#ibcon#end of sib2, iclass 23, count 0 2006.201.19:36:05.58#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:36:05.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:36:05.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:36:05.58#ibcon#*before write, iclass 23, count 0 2006.201.19:36:05.58#ibcon#enter sib2, iclass 23, count 0 2006.201.19:36:05.58#ibcon#flushed, iclass 23, count 0 2006.201.19:36:05.58#ibcon#about to write, iclass 23, count 0 2006.201.19:36:05.58#ibcon#wrote, iclass 23, count 0 2006.201.19:36:05.58#ibcon#about to read 3, iclass 23, count 0 2006.201.19:36:05.63#ibcon#read 3, iclass 23, count 0 2006.201.19:36:05.63#ibcon#about to read 4, iclass 23, count 0 2006.201.19:36:05.63#ibcon#read 4, iclass 23, count 0 2006.201.19:36:05.63#ibcon#about to read 5, iclass 23, count 0 2006.201.19:36:05.63#ibcon#read 5, iclass 23, count 0 2006.201.19:36:05.63#ibcon#about to read 6, iclass 23, count 0 2006.201.19:36:05.63#ibcon#read 6, iclass 23, count 0 2006.201.19:36:05.63#ibcon#end of sib2, iclass 23, count 0 2006.201.19:36:05.63#ibcon#*after write, iclass 23, count 0 2006.201.19:36:05.63#ibcon#*before return 0, iclass 23, count 0 2006.201.19:36:05.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:05.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:05.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:36:05.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:36:05.63$vck44/va=3,8 2006.201.19:36:05.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.19:36:05.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.19:36:05.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:05.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:05.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:05.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:05.68#ibcon#enter wrdev, iclass 25, count 2 2006.201.19:36:05.68#ibcon#first serial, iclass 25, count 2 2006.201.19:36:05.68#ibcon#enter sib2, iclass 25, count 2 2006.201.19:36:05.68#ibcon#flushed, iclass 25, count 2 2006.201.19:36:05.68#ibcon#about to write, iclass 25, count 2 2006.201.19:36:05.68#ibcon#wrote, iclass 25, count 2 2006.201.19:36:05.68#ibcon#about to read 3, iclass 25, count 2 2006.201.19:36:05.70#ibcon#read 3, iclass 25, count 2 2006.201.19:36:05.70#ibcon#about to read 4, iclass 25, count 2 2006.201.19:36:05.70#ibcon#read 4, iclass 25, count 2 2006.201.19:36:05.70#ibcon#about to read 5, iclass 25, count 2 2006.201.19:36:05.70#ibcon#read 5, iclass 25, count 2 2006.201.19:36:05.70#ibcon#about to read 6, iclass 25, count 2 2006.201.19:36:05.70#ibcon#read 6, iclass 25, count 2 2006.201.19:36:05.70#ibcon#end of sib2, iclass 25, count 2 2006.201.19:36:05.70#ibcon#*mode == 0, iclass 25, count 2 2006.201.19:36:05.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.19:36:05.70#ibcon#[25=AT03-08\r\n] 2006.201.19:36:05.70#ibcon#*before write, iclass 25, count 2 2006.201.19:36:05.70#ibcon#enter sib2, iclass 25, count 2 2006.201.19:36:05.70#ibcon#flushed, iclass 25, count 2 2006.201.19:36:05.70#ibcon#about to write, iclass 25, count 2 2006.201.19:36:05.70#ibcon#wrote, iclass 25, count 2 2006.201.19:36:05.70#ibcon#about to read 3, iclass 25, count 2 2006.201.19:36:05.73#ibcon#read 3, iclass 25, count 2 2006.201.19:36:05.73#ibcon#about to read 4, iclass 25, count 2 2006.201.19:36:05.73#ibcon#read 4, iclass 25, count 2 2006.201.19:36:05.73#ibcon#about to read 5, iclass 25, count 2 2006.201.19:36:05.73#ibcon#read 5, iclass 25, count 2 2006.201.19:36:05.73#ibcon#about to read 6, iclass 25, count 2 2006.201.19:36:05.73#ibcon#read 6, iclass 25, count 2 2006.201.19:36:05.73#ibcon#end of sib2, iclass 25, count 2 2006.201.19:36:05.73#ibcon#*after write, iclass 25, count 2 2006.201.19:36:05.73#ibcon#*before return 0, iclass 25, count 2 2006.201.19:36:05.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:05.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:05.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.19:36:05.73#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:05.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:05.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:05.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:05.85#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:36:05.85#ibcon#first serial, iclass 25, count 0 2006.201.19:36:05.85#ibcon#enter sib2, iclass 25, count 0 2006.201.19:36:05.85#ibcon#flushed, iclass 25, count 0 2006.201.19:36:05.85#ibcon#about to write, iclass 25, count 0 2006.201.19:36:05.85#ibcon#wrote, iclass 25, count 0 2006.201.19:36:05.85#ibcon#about to read 3, iclass 25, count 0 2006.201.19:36:05.87#ibcon#read 3, iclass 25, count 0 2006.201.19:36:05.87#ibcon#about to read 4, iclass 25, count 0 2006.201.19:36:05.87#ibcon#read 4, iclass 25, count 0 2006.201.19:36:05.87#ibcon#about to read 5, iclass 25, count 0 2006.201.19:36:05.87#ibcon#read 5, iclass 25, count 0 2006.201.19:36:05.87#ibcon#about to read 6, iclass 25, count 0 2006.201.19:36:05.87#ibcon#read 6, iclass 25, count 0 2006.201.19:36:05.87#ibcon#end of sib2, iclass 25, count 0 2006.201.19:36:05.87#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:36:05.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:36:05.87#ibcon#[25=USB\r\n] 2006.201.19:36:05.87#ibcon#*before write, iclass 25, count 0 2006.201.19:36:05.87#ibcon#enter sib2, iclass 25, count 0 2006.201.19:36:05.87#ibcon#flushed, iclass 25, count 0 2006.201.19:36:05.87#ibcon#about to write, iclass 25, count 0 2006.201.19:36:05.87#ibcon#wrote, iclass 25, count 0 2006.201.19:36:05.87#ibcon#about to read 3, iclass 25, count 0 2006.201.19:36:05.90#ibcon#read 3, iclass 25, count 0 2006.201.19:36:05.90#ibcon#about to read 4, iclass 25, count 0 2006.201.19:36:05.90#ibcon#read 4, iclass 25, count 0 2006.201.19:36:05.90#ibcon#about to read 5, iclass 25, count 0 2006.201.19:36:05.90#ibcon#read 5, iclass 25, count 0 2006.201.19:36:05.90#ibcon#about to read 6, iclass 25, count 0 2006.201.19:36:05.90#ibcon#read 6, iclass 25, count 0 2006.201.19:36:05.90#ibcon#end of sib2, iclass 25, count 0 2006.201.19:36:05.90#ibcon#*after write, iclass 25, count 0 2006.201.19:36:05.90#ibcon#*before return 0, iclass 25, count 0 2006.201.19:36:05.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:05.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:05.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:36:05.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:36:05.90$vck44/valo=4,624.99 2006.201.19:36:05.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.19:36:05.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.19:36:05.90#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:05.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:05.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:05.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:05.90#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:36:05.90#ibcon#first serial, iclass 27, count 0 2006.201.19:36:05.90#ibcon#enter sib2, iclass 27, count 0 2006.201.19:36:05.90#ibcon#flushed, iclass 27, count 0 2006.201.19:36:05.90#ibcon#about to write, iclass 27, count 0 2006.201.19:36:05.90#ibcon#wrote, iclass 27, count 0 2006.201.19:36:05.90#ibcon#about to read 3, iclass 27, count 0 2006.201.19:36:05.92#ibcon#read 3, iclass 27, count 0 2006.201.19:36:05.92#ibcon#about to read 4, iclass 27, count 0 2006.201.19:36:05.92#ibcon#read 4, iclass 27, count 0 2006.201.19:36:05.92#ibcon#about to read 5, iclass 27, count 0 2006.201.19:36:05.92#ibcon#read 5, iclass 27, count 0 2006.201.19:36:05.92#ibcon#about to read 6, iclass 27, count 0 2006.201.19:36:05.92#ibcon#read 6, iclass 27, count 0 2006.201.19:36:05.92#ibcon#end of sib2, iclass 27, count 0 2006.201.19:36:05.92#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:36:05.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:36:05.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:36:05.92#ibcon#*before write, iclass 27, count 0 2006.201.19:36:05.92#ibcon#enter sib2, iclass 27, count 0 2006.201.19:36:05.92#ibcon#flushed, iclass 27, count 0 2006.201.19:36:05.92#ibcon#about to write, iclass 27, count 0 2006.201.19:36:05.92#ibcon#wrote, iclass 27, count 0 2006.201.19:36:05.92#ibcon#about to read 3, iclass 27, count 0 2006.201.19:36:05.97#ibcon#read 3, iclass 27, count 0 2006.201.19:36:05.97#ibcon#about to read 4, iclass 27, count 0 2006.201.19:36:05.97#ibcon#read 4, iclass 27, count 0 2006.201.19:36:05.97#ibcon#about to read 5, iclass 27, count 0 2006.201.19:36:05.97#ibcon#read 5, iclass 27, count 0 2006.201.19:36:05.97#ibcon#about to read 6, iclass 27, count 0 2006.201.19:36:05.97#ibcon#read 6, iclass 27, count 0 2006.201.19:36:05.97#ibcon#end of sib2, iclass 27, count 0 2006.201.19:36:05.97#ibcon#*after write, iclass 27, count 0 2006.201.19:36:05.97#ibcon#*before return 0, iclass 27, count 0 2006.201.19:36:05.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:05.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:05.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:36:05.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:36:05.97$vck44/va=4,7 2006.201.19:36:05.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.19:36:05.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.19:36:05.97#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:05.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:06.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:06.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:06.02#ibcon#enter wrdev, iclass 29, count 2 2006.201.19:36:06.02#ibcon#first serial, iclass 29, count 2 2006.201.19:36:06.02#ibcon#enter sib2, iclass 29, count 2 2006.201.19:36:06.02#ibcon#flushed, iclass 29, count 2 2006.201.19:36:06.02#ibcon#about to write, iclass 29, count 2 2006.201.19:36:06.02#ibcon#wrote, iclass 29, count 2 2006.201.19:36:06.02#ibcon#about to read 3, iclass 29, count 2 2006.201.19:36:06.04#ibcon#read 3, iclass 29, count 2 2006.201.19:36:06.04#ibcon#about to read 4, iclass 29, count 2 2006.201.19:36:06.04#ibcon#read 4, iclass 29, count 2 2006.201.19:36:06.04#ibcon#about to read 5, iclass 29, count 2 2006.201.19:36:06.04#ibcon#read 5, iclass 29, count 2 2006.201.19:36:06.04#ibcon#about to read 6, iclass 29, count 2 2006.201.19:36:06.04#ibcon#read 6, iclass 29, count 2 2006.201.19:36:06.04#ibcon#end of sib2, iclass 29, count 2 2006.201.19:36:06.04#ibcon#*mode == 0, iclass 29, count 2 2006.201.19:36:06.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.19:36:06.04#ibcon#[25=AT04-07\r\n] 2006.201.19:36:06.04#ibcon#*before write, iclass 29, count 2 2006.201.19:36:06.04#ibcon#enter sib2, iclass 29, count 2 2006.201.19:36:06.04#ibcon#flushed, iclass 29, count 2 2006.201.19:36:06.04#ibcon#about to write, iclass 29, count 2 2006.201.19:36:06.04#ibcon#wrote, iclass 29, count 2 2006.201.19:36:06.04#ibcon#about to read 3, iclass 29, count 2 2006.201.19:36:06.07#ibcon#read 3, iclass 29, count 2 2006.201.19:36:06.07#ibcon#about to read 4, iclass 29, count 2 2006.201.19:36:06.07#ibcon#read 4, iclass 29, count 2 2006.201.19:36:06.07#ibcon#about to read 5, iclass 29, count 2 2006.201.19:36:06.07#ibcon#read 5, iclass 29, count 2 2006.201.19:36:06.07#ibcon#about to read 6, iclass 29, count 2 2006.201.19:36:06.07#ibcon#read 6, iclass 29, count 2 2006.201.19:36:06.07#ibcon#end of sib2, iclass 29, count 2 2006.201.19:36:06.07#ibcon#*after write, iclass 29, count 2 2006.201.19:36:06.07#ibcon#*before return 0, iclass 29, count 2 2006.201.19:36:06.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:06.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:06.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.19:36:06.07#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:06.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:06.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:06.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:06.19#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:36:06.19#ibcon#first serial, iclass 29, count 0 2006.201.19:36:06.19#ibcon#enter sib2, iclass 29, count 0 2006.201.19:36:06.19#ibcon#flushed, iclass 29, count 0 2006.201.19:36:06.19#ibcon#about to write, iclass 29, count 0 2006.201.19:36:06.19#ibcon#wrote, iclass 29, count 0 2006.201.19:36:06.19#ibcon#about to read 3, iclass 29, count 0 2006.201.19:36:06.21#ibcon#read 3, iclass 29, count 0 2006.201.19:36:06.21#ibcon#about to read 4, iclass 29, count 0 2006.201.19:36:06.21#ibcon#read 4, iclass 29, count 0 2006.201.19:36:06.21#ibcon#about to read 5, iclass 29, count 0 2006.201.19:36:06.21#ibcon#read 5, iclass 29, count 0 2006.201.19:36:06.21#ibcon#about to read 6, iclass 29, count 0 2006.201.19:36:06.21#ibcon#read 6, iclass 29, count 0 2006.201.19:36:06.21#ibcon#end of sib2, iclass 29, count 0 2006.201.19:36:06.21#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:36:06.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:36:06.21#ibcon#[25=USB\r\n] 2006.201.19:36:06.21#ibcon#*before write, iclass 29, count 0 2006.201.19:36:06.21#ibcon#enter sib2, iclass 29, count 0 2006.201.19:36:06.21#ibcon#flushed, iclass 29, count 0 2006.201.19:36:06.21#ibcon#about to write, iclass 29, count 0 2006.201.19:36:06.21#ibcon#wrote, iclass 29, count 0 2006.201.19:36:06.21#ibcon#about to read 3, iclass 29, count 0 2006.201.19:36:06.24#ibcon#read 3, iclass 29, count 0 2006.201.19:36:06.24#ibcon#about to read 4, iclass 29, count 0 2006.201.19:36:06.24#ibcon#read 4, iclass 29, count 0 2006.201.19:36:06.24#ibcon#about to read 5, iclass 29, count 0 2006.201.19:36:06.24#ibcon#read 5, iclass 29, count 0 2006.201.19:36:06.24#ibcon#about to read 6, iclass 29, count 0 2006.201.19:36:06.24#ibcon#read 6, iclass 29, count 0 2006.201.19:36:06.24#ibcon#end of sib2, iclass 29, count 0 2006.201.19:36:06.24#ibcon#*after write, iclass 29, count 0 2006.201.19:36:06.24#ibcon#*before return 0, iclass 29, count 0 2006.201.19:36:06.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:06.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:06.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:36:06.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:36:06.24$vck44/valo=5,734.99 2006.201.19:36:06.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.19:36:06.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.19:36:06.24#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:06.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:06.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:06.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:06.24#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:36:06.24#ibcon#first serial, iclass 31, count 0 2006.201.19:36:06.24#ibcon#enter sib2, iclass 31, count 0 2006.201.19:36:06.24#ibcon#flushed, iclass 31, count 0 2006.201.19:36:06.24#ibcon#about to write, iclass 31, count 0 2006.201.19:36:06.24#ibcon#wrote, iclass 31, count 0 2006.201.19:36:06.24#ibcon#about to read 3, iclass 31, count 0 2006.201.19:36:06.26#ibcon#read 3, iclass 31, count 0 2006.201.19:36:06.26#ibcon#about to read 4, iclass 31, count 0 2006.201.19:36:06.26#ibcon#read 4, iclass 31, count 0 2006.201.19:36:06.26#ibcon#about to read 5, iclass 31, count 0 2006.201.19:36:06.26#ibcon#read 5, iclass 31, count 0 2006.201.19:36:06.26#ibcon#about to read 6, iclass 31, count 0 2006.201.19:36:06.26#ibcon#read 6, iclass 31, count 0 2006.201.19:36:06.26#ibcon#end of sib2, iclass 31, count 0 2006.201.19:36:06.26#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:36:06.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:36:06.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:36:06.26#ibcon#*before write, iclass 31, count 0 2006.201.19:36:06.26#ibcon#enter sib2, iclass 31, count 0 2006.201.19:36:06.26#ibcon#flushed, iclass 31, count 0 2006.201.19:36:06.26#ibcon#about to write, iclass 31, count 0 2006.201.19:36:06.26#ibcon#wrote, iclass 31, count 0 2006.201.19:36:06.26#ibcon#about to read 3, iclass 31, count 0 2006.201.19:36:06.30#ibcon#read 3, iclass 31, count 0 2006.201.19:36:06.30#ibcon#about to read 4, iclass 31, count 0 2006.201.19:36:06.30#ibcon#read 4, iclass 31, count 0 2006.201.19:36:06.30#ibcon#about to read 5, iclass 31, count 0 2006.201.19:36:06.30#ibcon#read 5, iclass 31, count 0 2006.201.19:36:06.30#ibcon#about to read 6, iclass 31, count 0 2006.201.19:36:06.30#ibcon#read 6, iclass 31, count 0 2006.201.19:36:06.30#ibcon#end of sib2, iclass 31, count 0 2006.201.19:36:06.30#ibcon#*after write, iclass 31, count 0 2006.201.19:36:06.30#ibcon#*before return 0, iclass 31, count 0 2006.201.19:36:06.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:06.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:06.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:36:06.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:36:06.30$vck44/va=5,4 2006.201.19:36:06.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.19:36:06.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.19:36:06.30#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:06.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:06.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:06.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:06.36#ibcon#enter wrdev, iclass 33, count 2 2006.201.19:36:06.36#ibcon#first serial, iclass 33, count 2 2006.201.19:36:06.36#ibcon#enter sib2, iclass 33, count 2 2006.201.19:36:06.36#ibcon#flushed, iclass 33, count 2 2006.201.19:36:06.36#ibcon#about to write, iclass 33, count 2 2006.201.19:36:06.36#ibcon#wrote, iclass 33, count 2 2006.201.19:36:06.36#ibcon#about to read 3, iclass 33, count 2 2006.201.19:36:06.38#ibcon#read 3, iclass 33, count 2 2006.201.19:36:06.38#ibcon#about to read 4, iclass 33, count 2 2006.201.19:36:06.38#ibcon#read 4, iclass 33, count 2 2006.201.19:36:06.38#ibcon#about to read 5, iclass 33, count 2 2006.201.19:36:06.38#ibcon#read 5, iclass 33, count 2 2006.201.19:36:06.38#ibcon#about to read 6, iclass 33, count 2 2006.201.19:36:06.38#ibcon#read 6, iclass 33, count 2 2006.201.19:36:06.38#ibcon#end of sib2, iclass 33, count 2 2006.201.19:36:06.38#ibcon#*mode == 0, iclass 33, count 2 2006.201.19:36:06.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.19:36:06.38#ibcon#[25=AT05-04\r\n] 2006.201.19:36:06.38#ibcon#*before write, iclass 33, count 2 2006.201.19:36:06.38#ibcon#enter sib2, iclass 33, count 2 2006.201.19:36:06.38#ibcon#flushed, iclass 33, count 2 2006.201.19:36:06.38#ibcon#about to write, iclass 33, count 2 2006.201.19:36:06.38#ibcon#wrote, iclass 33, count 2 2006.201.19:36:06.38#ibcon#about to read 3, iclass 33, count 2 2006.201.19:36:06.41#ibcon#read 3, iclass 33, count 2 2006.201.19:36:06.41#ibcon#about to read 4, iclass 33, count 2 2006.201.19:36:06.41#ibcon#read 4, iclass 33, count 2 2006.201.19:36:06.41#ibcon#about to read 5, iclass 33, count 2 2006.201.19:36:06.41#ibcon#read 5, iclass 33, count 2 2006.201.19:36:06.41#ibcon#about to read 6, iclass 33, count 2 2006.201.19:36:06.41#ibcon#read 6, iclass 33, count 2 2006.201.19:36:06.41#ibcon#end of sib2, iclass 33, count 2 2006.201.19:36:06.41#ibcon#*after write, iclass 33, count 2 2006.201.19:36:06.41#ibcon#*before return 0, iclass 33, count 2 2006.201.19:36:06.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:06.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:06.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.19:36:06.41#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:06.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:06.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:06.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:06.53#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:36:06.53#ibcon#first serial, iclass 33, count 0 2006.201.19:36:06.53#ibcon#enter sib2, iclass 33, count 0 2006.201.19:36:06.53#ibcon#flushed, iclass 33, count 0 2006.201.19:36:06.53#ibcon#about to write, iclass 33, count 0 2006.201.19:36:06.53#ibcon#wrote, iclass 33, count 0 2006.201.19:36:06.53#ibcon#about to read 3, iclass 33, count 0 2006.201.19:36:06.55#ibcon#read 3, iclass 33, count 0 2006.201.19:36:06.55#ibcon#about to read 4, iclass 33, count 0 2006.201.19:36:06.55#ibcon#read 4, iclass 33, count 0 2006.201.19:36:06.55#ibcon#about to read 5, iclass 33, count 0 2006.201.19:36:06.55#ibcon#read 5, iclass 33, count 0 2006.201.19:36:06.55#ibcon#about to read 6, iclass 33, count 0 2006.201.19:36:06.55#ibcon#read 6, iclass 33, count 0 2006.201.19:36:06.55#ibcon#end of sib2, iclass 33, count 0 2006.201.19:36:06.55#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:36:06.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:36:06.55#ibcon#[25=USB\r\n] 2006.201.19:36:06.55#ibcon#*before write, iclass 33, count 0 2006.201.19:36:06.55#ibcon#enter sib2, iclass 33, count 0 2006.201.19:36:06.55#ibcon#flushed, iclass 33, count 0 2006.201.19:36:06.55#ibcon#about to write, iclass 33, count 0 2006.201.19:36:06.55#ibcon#wrote, iclass 33, count 0 2006.201.19:36:06.55#ibcon#about to read 3, iclass 33, count 0 2006.201.19:36:06.58#ibcon#read 3, iclass 33, count 0 2006.201.19:36:06.58#ibcon#about to read 4, iclass 33, count 0 2006.201.19:36:06.58#ibcon#read 4, iclass 33, count 0 2006.201.19:36:06.58#ibcon#about to read 5, iclass 33, count 0 2006.201.19:36:06.58#ibcon#read 5, iclass 33, count 0 2006.201.19:36:06.58#ibcon#about to read 6, iclass 33, count 0 2006.201.19:36:06.58#ibcon#read 6, iclass 33, count 0 2006.201.19:36:06.58#ibcon#end of sib2, iclass 33, count 0 2006.201.19:36:06.58#ibcon#*after write, iclass 33, count 0 2006.201.19:36:06.58#ibcon#*before return 0, iclass 33, count 0 2006.201.19:36:06.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:06.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:06.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:36:06.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:36:06.58$vck44/valo=6,814.99 2006.201.19:36:06.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.19:36:06.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.19:36:06.58#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:06.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:06.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:06.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:06.58#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:36:06.58#ibcon#first serial, iclass 35, count 0 2006.201.19:36:06.58#ibcon#enter sib2, iclass 35, count 0 2006.201.19:36:06.58#ibcon#flushed, iclass 35, count 0 2006.201.19:36:06.58#ibcon#about to write, iclass 35, count 0 2006.201.19:36:06.58#ibcon#wrote, iclass 35, count 0 2006.201.19:36:06.58#ibcon#about to read 3, iclass 35, count 0 2006.201.19:36:06.60#ibcon#read 3, iclass 35, count 0 2006.201.19:36:06.60#ibcon#about to read 4, iclass 35, count 0 2006.201.19:36:06.60#ibcon#read 4, iclass 35, count 0 2006.201.19:36:06.60#ibcon#about to read 5, iclass 35, count 0 2006.201.19:36:06.60#ibcon#read 5, iclass 35, count 0 2006.201.19:36:06.60#ibcon#about to read 6, iclass 35, count 0 2006.201.19:36:06.60#ibcon#read 6, iclass 35, count 0 2006.201.19:36:06.60#ibcon#end of sib2, iclass 35, count 0 2006.201.19:36:06.60#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:36:06.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:36:06.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:36:06.60#ibcon#*before write, iclass 35, count 0 2006.201.19:36:06.60#ibcon#enter sib2, iclass 35, count 0 2006.201.19:36:06.60#ibcon#flushed, iclass 35, count 0 2006.201.19:36:06.60#ibcon#about to write, iclass 35, count 0 2006.201.19:36:06.60#ibcon#wrote, iclass 35, count 0 2006.201.19:36:06.60#ibcon#about to read 3, iclass 35, count 0 2006.201.19:36:06.64#ibcon#read 3, iclass 35, count 0 2006.201.19:36:06.64#ibcon#about to read 4, iclass 35, count 0 2006.201.19:36:06.64#ibcon#read 4, iclass 35, count 0 2006.201.19:36:06.64#ibcon#about to read 5, iclass 35, count 0 2006.201.19:36:06.64#ibcon#read 5, iclass 35, count 0 2006.201.19:36:06.64#ibcon#about to read 6, iclass 35, count 0 2006.201.19:36:06.64#ibcon#read 6, iclass 35, count 0 2006.201.19:36:06.64#ibcon#end of sib2, iclass 35, count 0 2006.201.19:36:06.64#ibcon#*after write, iclass 35, count 0 2006.201.19:36:06.64#ibcon#*before return 0, iclass 35, count 0 2006.201.19:36:06.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:06.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:06.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:36:06.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:36:06.64$vck44/va=6,5 2006.201.19:36:06.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.19:36:06.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.19:36:06.64#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:06.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:06.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:06.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:06.70#ibcon#enter wrdev, iclass 37, count 2 2006.201.19:36:06.70#ibcon#first serial, iclass 37, count 2 2006.201.19:36:06.70#ibcon#enter sib2, iclass 37, count 2 2006.201.19:36:06.70#ibcon#flushed, iclass 37, count 2 2006.201.19:36:06.70#ibcon#about to write, iclass 37, count 2 2006.201.19:36:06.70#ibcon#wrote, iclass 37, count 2 2006.201.19:36:06.70#ibcon#about to read 3, iclass 37, count 2 2006.201.19:36:06.72#ibcon#read 3, iclass 37, count 2 2006.201.19:36:06.72#ibcon#about to read 4, iclass 37, count 2 2006.201.19:36:06.72#ibcon#read 4, iclass 37, count 2 2006.201.19:36:06.72#ibcon#about to read 5, iclass 37, count 2 2006.201.19:36:06.72#ibcon#read 5, iclass 37, count 2 2006.201.19:36:06.72#ibcon#about to read 6, iclass 37, count 2 2006.201.19:36:06.72#ibcon#read 6, iclass 37, count 2 2006.201.19:36:06.72#ibcon#end of sib2, iclass 37, count 2 2006.201.19:36:06.72#ibcon#*mode == 0, iclass 37, count 2 2006.201.19:36:06.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.19:36:06.72#ibcon#[25=AT06-05\r\n] 2006.201.19:36:06.72#ibcon#*before write, iclass 37, count 2 2006.201.19:36:06.72#ibcon#enter sib2, iclass 37, count 2 2006.201.19:36:06.72#ibcon#flushed, iclass 37, count 2 2006.201.19:36:06.72#ibcon#about to write, iclass 37, count 2 2006.201.19:36:06.72#ibcon#wrote, iclass 37, count 2 2006.201.19:36:06.72#ibcon#about to read 3, iclass 37, count 2 2006.201.19:36:06.75#ibcon#read 3, iclass 37, count 2 2006.201.19:36:06.75#ibcon#about to read 4, iclass 37, count 2 2006.201.19:36:06.75#ibcon#read 4, iclass 37, count 2 2006.201.19:36:06.75#ibcon#about to read 5, iclass 37, count 2 2006.201.19:36:06.75#ibcon#read 5, iclass 37, count 2 2006.201.19:36:06.75#ibcon#about to read 6, iclass 37, count 2 2006.201.19:36:06.75#ibcon#read 6, iclass 37, count 2 2006.201.19:36:06.75#ibcon#end of sib2, iclass 37, count 2 2006.201.19:36:06.75#ibcon#*after write, iclass 37, count 2 2006.201.19:36:06.75#ibcon#*before return 0, iclass 37, count 2 2006.201.19:36:06.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:06.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:06.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.19:36:06.75#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:06.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:06.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:06.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:06.87#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:36:06.87#ibcon#first serial, iclass 37, count 0 2006.201.19:36:06.87#ibcon#enter sib2, iclass 37, count 0 2006.201.19:36:06.87#ibcon#flushed, iclass 37, count 0 2006.201.19:36:06.87#ibcon#about to write, iclass 37, count 0 2006.201.19:36:06.87#ibcon#wrote, iclass 37, count 0 2006.201.19:36:06.87#ibcon#about to read 3, iclass 37, count 0 2006.201.19:36:06.89#ibcon#read 3, iclass 37, count 0 2006.201.19:36:06.89#ibcon#about to read 4, iclass 37, count 0 2006.201.19:36:06.89#ibcon#read 4, iclass 37, count 0 2006.201.19:36:06.89#ibcon#about to read 5, iclass 37, count 0 2006.201.19:36:06.89#ibcon#read 5, iclass 37, count 0 2006.201.19:36:06.89#ibcon#about to read 6, iclass 37, count 0 2006.201.19:36:06.89#ibcon#read 6, iclass 37, count 0 2006.201.19:36:06.89#ibcon#end of sib2, iclass 37, count 0 2006.201.19:36:06.89#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:36:06.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:36:06.89#ibcon#[25=USB\r\n] 2006.201.19:36:06.89#ibcon#*before write, iclass 37, count 0 2006.201.19:36:06.89#ibcon#enter sib2, iclass 37, count 0 2006.201.19:36:06.89#ibcon#flushed, iclass 37, count 0 2006.201.19:36:06.89#ibcon#about to write, iclass 37, count 0 2006.201.19:36:06.89#ibcon#wrote, iclass 37, count 0 2006.201.19:36:06.89#ibcon#about to read 3, iclass 37, count 0 2006.201.19:36:06.92#ibcon#read 3, iclass 37, count 0 2006.201.19:36:06.92#ibcon#about to read 4, iclass 37, count 0 2006.201.19:36:06.92#ibcon#read 4, iclass 37, count 0 2006.201.19:36:06.92#ibcon#about to read 5, iclass 37, count 0 2006.201.19:36:06.92#ibcon#read 5, iclass 37, count 0 2006.201.19:36:06.92#ibcon#about to read 6, iclass 37, count 0 2006.201.19:36:06.92#ibcon#read 6, iclass 37, count 0 2006.201.19:36:06.92#ibcon#end of sib2, iclass 37, count 0 2006.201.19:36:06.92#ibcon#*after write, iclass 37, count 0 2006.201.19:36:06.92#ibcon#*before return 0, iclass 37, count 0 2006.201.19:36:06.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:06.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:06.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:36:06.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:36:06.92$vck44/valo=7,864.99 2006.201.19:36:06.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.19:36:06.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.19:36:06.92#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:06.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:06.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:06.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:06.92#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:36:06.92#ibcon#first serial, iclass 39, count 0 2006.201.19:36:06.92#ibcon#enter sib2, iclass 39, count 0 2006.201.19:36:06.92#ibcon#flushed, iclass 39, count 0 2006.201.19:36:06.92#ibcon#about to write, iclass 39, count 0 2006.201.19:36:06.92#ibcon#wrote, iclass 39, count 0 2006.201.19:36:06.92#ibcon#about to read 3, iclass 39, count 0 2006.201.19:36:06.94#ibcon#read 3, iclass 39, count 0 2006.201.19:36:06.94#ibcon#about to read 4, iclass 39, count 0 2006.201.19:36:06.94#ibcon#read 4, iclass 39, count 0 2006.201.19:36:06.94#ibcon#about to read 5, iclass 39, count 0 2006.201.19:36:06.94#ibcon#read 5, iclass 39, count 0 2006.201.19:36:06.94#ibcon#about to read 6, iclass 39, count 0 2006.201.19:36:06.94#ibcon#read 6, iclass 39, count 0 2006.201.19:36:06.94#ibcon#end of sib2, iclass 39, count 0 2006.201.19:36:06.94#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:36:06.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:36:06.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:36:06.94#ibcon#*before write, iclass 39, count 0 2006.201.19:36:06.94#ibcon#enter sib2, iclass 39, count 0 2006.201.19:36:06.94#ibcon#flushed, iclass 39, count 0 2006.201.19:36:06.94#ibcon#about to write, iclass 39, count 0 2006.201.19:36:06.94#ibcon#wrote, iclass 39, count 0 2006.201.19:36:06.94#ibcon#about to read 3, iclass 39, count 0 2006.201.19:36:06.99#ibcon#read 3, iclass 39, count 0 2006.201.19:36:06.99#ibcon#about to read 4, iclass 39, count 0 2006.201.19:36:06.99#ibcon#read 4, iclass 39, count 0 2006.201.19:36:06.99#ibcon#about to read 5, iclass 39, count 0 2006.201.19:36:06.99#ibcon#read 5, iclass 39, count 0 2006.201.19:36:06.99#ibcon#about to read 6, iclass 39, count 0 2006.201.19:36:06.99#ibcon#read 6, iclass 39, count 0 2006.201.19:36:06.99#ibcon#end of sib2, iclass 39, count 0 2006.201.19:36:06.99#ibcon#*after write, iclass 39, count 0 2006.201.19:36:06.99#ibcon#*before return 0, iclass 39, count 0 2006.201.19:36:06.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:06.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:06.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:36:06.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:36:06.99$vck44/va=7,5 2006.201.19:36:06.99#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.19:36:06.99#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.19:36:06.99#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:06.99#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:07.04#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:07.04#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:07.04#ibcon#enter wrdev, iclass 2, count 2 2006.201.19:36:07.04#ibcon#first serial, iclass 2, count 2 2006.201.19:36:07.04#ibcon#enter sib2, iclass 2, count 2 2006.201.19:36:07.04#ibcon#flushed, iclass 2, count 2 2006.201.19:36:07.04#ibcon#about to write, iclass 2, count 2 2006.201.19:36:07.04#ibcon#wrote, iclass 2, count 2 2006.201.19:36:07.04#ibcon#about to read 3, iclass 2, count 2 2006.201.19:36:07.06#ibcon#read 3, iclass 2, count 2 2006.201.19:36:07.06#ibcon#about to read 4, iclass 2, count 2 2006.201.19:36:07.06#ibcon#read 4, iclass 2, count 2 2006.201.19:36:07.06#ibcon#about to read 5, iclass 2, count 2 2006.201.19:36:07.06#ibcon#read 5, iclass 2, count 2 2006.201.19:36:07.06#ibcon#about to read 6, iclass 2, count 2 2006.201.19:36:07.06#ibcon#read 6, iclass 2, count 2 2006.201.19:36:07.06#ibcon#end of sib2, iclass 2, count 2 2006.201.19:36:07.06#ibcon#*mode == 0, iclass 2, count 2 2006.201.19:36:07.06#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.19:36:07.06#ibcon#[25=AT07-05\r\n] 2006.201.19:36:07.06#ibcon#*before write, iclass 2, count 2 2006.201.19:36:07.06#ibcon#enter sib2, iclass 2, count 2 2006.201.19:36:07.06#ibcon#flushed, iclass 2, count 2 2006.201.19:36:07.06#ibcon#about to write, iclass 2, count 2 2006.201.19:36:07.06#ibcon#wrote, iclass 2, count 2 2006.201.19:36:07.06#ibcon#about to read 3, iclass 2, count 2 2006.201.19:36:07.09#ibcon#read 3, iclass 2, count 2 2006.201.19:36:07.09#ibcon#about to read 4, iclass 2, count 2 2006.201.19:36:07.09#ibcon#read 4, iclass 2, count 2 2006.201.19:36:07.09#ibcon#about to read 5, iclass 2, count 2 2006.201.19:36:07.09#ibcon#read 5, iclass 2, count 2 2006.201.19:36:07.09#ibcon#about to read 6, iclass 2, count 2 2006.201.19:36:07.09#ibcon#read 6, iclass 2, count 2 2006.201.19:36:07.09#ibcon#end of sib2, iclass 2, count 2 2006.201.19:36:07.09#ibcon#*after write, iclass 2, count 2 2006.201.19:36:07.09#ibcon#*before return 0, iclass 2, count 2 2006.201.19:36:07.09#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:07.09#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:07.09#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.19:36:07.09#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:07.09#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:07.21#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:07.21#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:07.21#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:36:07.21#ibcon#first serial, iclass 2, count 0 2006.201.19:36:07.21#ibcon#enter sib2, iclass 2, count 0 2006.201.19:36:07.21#ibcon#flushed, iclass 2, count 0 2006.201.19:36:07.21#ibcon#about to write, iclass 2, count 0 2006.201.19:36:07.21#ibcon#wrote, iclass 2, count 0 2006.201.19:36:07.21#ibcon#about to read 3, iclass 2, count 0 2006.201.19:36:07.23#ibcon#read 3, iclass 2, count 0 2006.201.19:36:07.23#ibcon#about to read 4, iclass 2, count 0 2006.201.19:36:07.23#ibcon#read 4, iclass 2, count 0 2006.201.19:36:07.23#ibcon#about to read 5, iclass 2, count 0 2006.201.19:36:07.23#ibcon#read 5, iclass 2, count 0 2006.201.19:36:07.23#ibcon#about to read 6, iclass 2, count 0 2006.201.19:36:07.23#ibcon#read 6, iclass 2, count 0 2006.201.19:36:07.23#ibcon#end of sib2, iclass 2, count 0 2006.201.19:36:07.23#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:36:07.23#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:36:07.23#ibcon#[25=USB\r\n] 2006.201.19:36:07.23#ibcon#*before write, iclass 2, count 0 2006.201.19:36:07.23#ibcon#enter sib2, iclass 2, count 0 2006.201.19:36:07.23#ibcon#flushed, iclass 2, count 0 2006.201.19:36:07.23#ibcon#about to write, iclass 2, count 0 2006.201.19:36:07.23#ibcon#wrote, iclass 2, count 0 2006.201.19:36:07.23#ibcon#about to read 3, iclass 2, count 0 2006.201.19:36:07.26#ibcon#read 3, iclass 2, count 0 2006.201.19:36:07.26#ibcon#about to read 4, iclass 2, count 0 2006.201.19:36:07.26#ibcon#read 4, iclass 2, count 0 2006.201.19:36:07.26#ibcon#about to read 5, iclass 2, count 0 2006.201.19:36:07.26#ibcon#read 5, iclass 2, count 0 2006.201.19:36:07.26#ibcon#about to read 6, iclass 2, count 0 2006.201.19:36:07.26#ibcon#read 6, iclass 2, count 0 2006.201.19:36:07.26#ibcon#end of sib2, iclass 2, count 0 2006.201.19:36:07.26#ibcon#*after write, iclass 2, count 0 2006.201.19:36:07.26#ibcon#*before return 0, iclass 2, count 0 2006.201.19:36:07.26#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:07.26#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:07.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:36:07.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:36:07.26$vck44/valo=8,884.99 2006.201.19:36:07.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.19:36:07.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.19:36:07.26#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:07.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:07.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:07.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:07.26#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:36:07.26#ibcon#first serial, iclass 5, count 0 2006.201.19:36:07.26#ibcon#enter sib2, iclass 5, count 0 2006.201.19:36:07.26#ibcon#flushed, iclass 5, count 0 2006.201.19:36:07.26#ibcon#about to write, iclass 5, count 0 2006.201.19:36:07.26#ibcon#wrote, iclass 5, count 0 2006.201.19:36:07.26#ibcon#about to read 3, iclass 5, count 0 2006.201.19:36:07.28#ibcon#read 3, iclass 5, count 0 2006.201.19:36:07.28#ibcon#about to read 4, iclass 5, count 0 2006.201.19:36:07.28#ibcon#read 4, iclass 5, count 0 2006.201.19:36:07.28#ibcon#about to read 5, iclass 5, count 0 2006.201.19:36:07.28#ibcon#read 5, iclass 5, count 0 2006.201.19:36:07.28#ibcon#about to read 6, iclass 5, count 0 2006.201.19:36:07.28#ibcon#read 6, iclass 5, count 0 2006.201.19:36:07.28#ibcon#end of sib2, iclass 5, count 0 2006.201.19:36:07.28#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:36:07.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:36:07.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:36:07.28#ibcon#*before write, iclass 5, count 0 2006.201.19:36:07.28#ibcon#enter sib2, iclass 5, count 0 2006.201.19:36:07.28#ibcon#flushed, iclass 5, count 0 2006.201.19:36:07.28#ibcon#about to write, iclass 5, count 0 2006.201.19:36:07.28#ibcon#wrote, iclass 5, count 0 2006.201.19:36:07.28#ibcon#about to read 3, iclass 5, count 0 2006.201.19:36:07.32#ibcon#read 3, iclass 5, count 0 2006.201.19:36:07.32#ibcon#about to read 4, iclass 5, count 0 2006.201.19:36:07.32#ibcon#read 4, iclass 5, count 0 2006.201.19:36:07.32#ibcon#about to read 5, iclass 5, count 0 2006.201.19:36:07.32#ibcon#read 5, iclass 5, count 0 2006.201.19:36:07.32#ibcon#about to read 6, iclass 5, count 0 2006.201.19:36:07.32#ibcon#read 6, iclass 5, count 0 2006.201.19:36:07.32#ibcon#end of sib2, iclass 5, count 0 2006.201.19:36:07.32#ibcon#*after write, iclass 5, count 0 2006.201.19:36:07.32#ibcon#*before return 0, iclass 5, count 0 2006.201.19:36:07.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:07.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:07.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:36:07.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:36:07.32$vck44/va=8,4 2006.201.19:36:07.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.19:36:07.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.19:36:07.32#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:07.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:36:07.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:36:07.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:36:07.38#ibcon#enter wrdev, iclass 7, count 2 2006.201.19:36:07.38#ibcon#first serial, iclass 7, count 2 2006.201.19:36:07.38#ibcon#enter sib2, iclass 7, count 2 2006.201.19:36:07.38#ibcon#flushed, iclass 7, count 2 2006.201.19:36:07.38#ibcon#about to write, iclass 7, count 2 2006.201.19:36:07.38#ibcon#wrote, iclass 7, count 2 2006.201.19:36:07.38#ibcon#about to read 3, iclass 7, count 2 2006.201.19:36:07.40#ibcon#read 3, iclass 7, count 2 2006.201.19:36:07.40#ibcon#about to read 4, iclass 7, count 2 2006.201.19:36:07.40#ibcon#read 4, iclass 7, count 2 2006.201.19:36:07.40#ibcon#about to read 5, iclass 7, count 2 2006.201.19:36:07.40#ibcon#read 5, iclass 7, count 2 2006.201.19:36:07.40#ibcon#about to read 6, iclass 7, count 2 2006.201.19:36:07.40#ibcon#read 6, iclass 7, count 2 2006.201.19:36:07.40#ibcon#end of sib2, iclass 7, count 2 2006.201.19:36:07.40#ibcon#*mode == 0, iclass 7, count 2 2006.201.19:36:07.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.19:36:07.40#ibcon#[25=AT08-04\r\n] 2006.201.19:36:07.40#ibcon#*before write, iclass 7, count 2 2006.201.19:36:07.40#ibcon#enter sib2, iclass 7, count 2 2006.201.19:36:07.40#ibcon#flushed, iclass 7, count 2 2006.201.19:36:07.40#ibcon#about to write, iclass 7, count 2 2006.201.19:36:07.40#ibcon#wrote, iclass 7, count 2 2006.201.19:36:07.40#ibcon#about to read 3, iclass 7, count 2 2006.201.19:36:07.43#ibcon#read 3, iclass 7, count 2 2006.201.19:36:07.43#ibcon#about to read 4, iclass 7, count 2 2006.201.19:36:07.43#ibcon#read 4, iclass 7, count 2 2006.201.19:36:07.43#ibcon#about to read 5, iclass 7, count 2 2006.201.19:36:07.43#ibcon#read 5, iclass 7, count 2 2006.201.19:36:07.43#ibcon#about to read 6, iclass 7, count 2 2006.201.19:36:07.43#ibcon#read 6, iclass 7, count 2 2006.201.19:36:07.43#ibcon#end of sib2, iclass 7, count 2 2006.201.19:36:07.43#ibcon#*after write, iclass 7, count 2 2006.201.19:36:07.43#ibcon#*before return 0, iclass 7, count 2 2006.201.19:36:07.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:36:07.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:36:07.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.19:36:07.43#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:07.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:36:07.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:36:07.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:36:07.55#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:36:07.55#ibcon#first serial, iclass 7, count 0 2006.201.19:36:07.55#ibcon#enter sib2, iclass 7, count 0 2006.201.19:36:07.55#ibcon#flushed, iclass 7, count 0 2006.201.19:36:07.55#ibcon#about to write, iclass 7, count 0 2006.201.19:36:07.55#ibcon#wrote, iclass 7, count 0 2006.201.19:36:07.55#ibcon#about to read 3, iclass 7, count 0 2006.201.19:36:07.57#ibcon#read 3, iclass 7, count 0 2006.201.19:36:07.57#ibcon#about to read 4, iclass 7, count 0 2006.201.19:36:07.57#ibcon#read 4, iclass 7, count 0 2006.201.19:36:07.57#ibcon#about to read 5, iclass 7, count 0 2006.201.19:36:07.57#ibcon#read 5, iclass 7, count 0 2006.201.19:36:07.57#ibcon#about to read 6, iclass 7, count 0 2006.201.19:36:07.57#ibcon#read 6, iclass 7, count 0 2006.201.19:36:07.57#ibcon#end of sib2, iclass 7, count 0 2006.201.19:36:07.57#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:36:07.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:36:07.57#ibcon#[25=USB\r\n] 2006.201.19:36:07.57#ibcon#*before write, iclass 7, count 0 2006.201.19:36:07.57#ibcon#enter sib2, iclass 7, count 0 2006.201.19:36:07.57#ibcon#flushed, iclass 7, count 0 2006.201.19:36:07.57#ibcon#about to write, iclass 7, count 0 2006.201.19:36:07.57#ibcon#wrote, iclass 7, count 0 2006.201.19:36:07.57#ibcon#about to read 3, iclass 7, count 0 2006.201.19:36:07.60#ibcon#read 3, iclass 7, count 0 2006.201.19:36:07.60#ibcon#about to read 4, iclass 7, count 0 2006.201.19:36:07.60#ibcon#read 4, iclass 7, count 0 2006.201.19:36:07.60#ibcon#about to read 5, iclass 7, count 0 2006.201.19:36:07.60#ibcon#read 5, iclass 7, count 0 2006.201.19:36:07.60#ibcon#about to read 6, iclass 7, count 0 2006.201.19:36:07.60#ibcon#read 6, iclass 7, count 0 2006.201.19:36:07.60#ibcon#end of sib2, iclass 7, count 0 2006.201.19:36:07.60#ibcon#*after write, iclass 7, count 0 2006.201.19:36:07.60#ibcon#*before return 0, iclass 7, count 0 2006.201.19:36:07.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:36:07.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:36:07.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:36:07.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:36:07.60$vck44/vblo=1,629.99 2006.201.19:36:07.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.19:36:07.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.19:36:07.60#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:07.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:36:07.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:36:07.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:36:07.60#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:36:07.60#ibcon#first serial, iclass 11, count 0 2006.201.19:36:07.60#ibcon#enter sib2, iclass 11, count 0 2006.201.19:36:07.60#ibcon#flushed, iclass 11, count 0 2006.201.19:36:07.60#ibcon#about to write, iclass 11, count 0 2006.201.19:36:07.60#ibcon#wrote, iclass 11, count 0 2006.201.19:36:07.60#ibcon#about to read 3, iclass 11, count 0 2006.201.19:36:07.62#ibcon#read 3, iclass 11, count 0 2006.201.19:36:07.62#ibcon#about to read 4, iclass 11, count 0 2006.201.19:36:07.62#ibcon#read 4, iclass 11, count 0 2006.201.19:36:07.62#ibcon#about to read 5, iclass 11, count 0 2006.201.19:36:07.62#ibcon#read 5, iclass 11, count 0 2006.201.19:36:07.62#ibcon#about to read 6, iclass 11, count 0 2006.201.19:36:07.62#ibcon#read 6, iclass 11, count 0 2006.201.19:36:07.62#ibcon#end of sib2, iclass 11, count 0 2006.201.19:36:07.62#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:36:07.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:36:07.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:36:07.62#ibcon#*before write, iclass 11, count 0 2006.201.19:36:07.62#ibcon#enter sib2, iclass 11, count 0 2006.201.19:36:07.62#ibcon#flushed, iclass 11, count 0 2006.201.19:36:07.62#ibcon#about to write, iclass 11, count 0 2006.201.19:36:07.62#ibcon#wrote, iclass 11, count 0 2006.201.19:36:07.62#ibcon#about to read 3, iclass 11, count 0 2006.201.19:36:07.66#ibcon#read 3, iclass 11, count 0 2006.201.19:36:07.66#ibcon#about to read 4, iclass 11, count 0 2006.201.19:36:07.66#ibcon#read 4, iclass 11, count 0 2006.201.19:36:07.66#ibcon#about to read 5, iclass 11, count 0 2006.201.19:36:07.66#ibcon#read 5, iclass 11, count 0 2006.201.19:36:07.66#ibcon#about to read 6, iclass 11, count 0 2006.201.19:36:07.66#ibcon#read 6, iclass 11, count 0 2006.201.19:36:07.66#ibcon#end of sib2, iclass 11, count 0 2006.201.19:36:07.66#ibcon#*after write, iclass 11, count 0 2006.201.19:36:07.66#ibcon#*before return 0, iclass 11, count 0 2006.201.19:36:07.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:36:07.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:36:07.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:36:07.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:36:07.66$vck44/vb=1,4 2006.201.19:36:07.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.19:36:07.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.19:36:07.66#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:07.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:36:07.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:36:07.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:36:07.66#ibcon#enter wrdev, iclass 13, count 2 2006.201.19:36:07.66#ibcon#first serial, iclass 13, count 2 2006.201.19:36:07.66#ibcon#enter sib2, iclass 13, count 2 2006.201.19:36:07.66#ibcon#flushed, iclass 13, count 2 2006.201.19:36:07.66#ibcon#about to write, iclass 13, count 2 2006.201.19:36:07.66#ibcon#wrote, iclass 13, count 2 2006.201.19:36:07.66#ibcon#about to read 3, iclass 13, count 2 2006.201.19:36:07.68#ibcon#read 3, iclass 13, count 2 2006.201.19:36:07.68#ibcon#about to read 4, iclass 13, count 2 2006.201.19:36:07.68#ibcon#read 4, iclass 13, count 2 2006.201.19:36:07.68#ibcon#about to read 5, iclass 13, count 2 2006.201.19:36:07.68#ibcon#read 5, iclass 13, count 2 2006.201.19:36:07.68#ibcon#about to read 6, iclass 13, count 2 2006.201.19:36:07.68#ibcon#read 6, iclass 13, count 2 2006.201.19:36:07.68#ibcon#end of sib2, iclass 13, count 2 2006.201.19:36:07.68#ibcon#*mode == 0, iclass 13, count 2 2006.201.19:36:07.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.19:36:07.68#ibcon#[27=AT01-04\r\n] 2006.201.19:36:07.68#ibcon#*before write, iclass 13, count 2 2006.201.19:36:07.68#ibcon#enter sib2, iclass 13, count 2 2006.201.19:36:07.68#ibcon#flushed, iclass 13, count 2 2006.201.19:36:07.68#ibcon#about to write, iclass 13, count 2 2006.201.19:36:07.68#ibcon#wrote, iclass 13, count 2 2006.201.19:36:07.68#ibcon#about to read 3, iclass 13, count 2 2006.201.19:36:07.71#ibcon#read 3, iclass 13, count 2 2006.201.19:36:07.71#ibcon#about to read 4, iclass 13, count 2 2006.201.19:36:07.71#ibcon#read 4, iclass 13, count 2 2006.201.19:36:07.71#ibcon#about to read 5, iclass 13, count 2 2006.201.19:36:07.71#ibcon#read 5, iclass 13, count 2 2006.201.19:36:07.71#ibcon#about to read 6, iclass 13, count 2 2006.201.19:36:07.71#ibcon#read 6, iclass 13, count 2 2006.201.19:36:07.71#ibcon#end of sib2, iclass 13, count 2 2006.201.19:36:07.71#ibcon#*after write, iclass 13, count 2 2006.201.19:36:07.71#ibcon#*before return 0, iclass 13, count 2 2006.201.19:36:07.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:36:07.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:36:07.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.19:36:07.71#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:07.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:36:07.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:36:07.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:36:07.83#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:36:07.83#ibcon#first serial, iclass 13, count 0 2006.201.19:36:07.83#ibcon#enter sib2, iclass 13, count 0 2006.201.19:36:07.83#ibcon#flushed, iclass 13, count 0 2006.201.19:36:07.83#ibcon#about to write, iclass 13, count 0 2006.201.19:36:07.83#ibcon#wrote, iclass 13, count 0 2006.201.19:36:07.83#ibcon#about to read 3, iclass 13, count 0 2006.201.19:36:07.85#ibcon#read 3, iclass 13, count 0 2006.201.19:36:07.85#ibcon#about to read 4, iclass 13, count 0 2006.201.19:36:07.85#ibcon#read 4, iclass 13, count 0 2006.201.19:36:07.85#ibcon#about to read 5, iclass 13, count 0 2006.201.19:36:07.85#ibcon#read 5, iclass 13, count 0 2006.201.19:36:07.85#ibcon#about to read 6, iclass 13, count 0 2006.201.19:36:07.85#ibcon#read 6, iclass 13, count 0 2006.201.19:36:07.85#ibcon#end of sib2, iclass 13, count 0 2006.201.19:36:07.85#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:36:07.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:36:07.85#ibcon#[27=USB\r\n] 2006.201.19:36:07.85#ibcon#*before write, iclass 13, count 0 2006.201.19:36:07.85#ibcon#enter sib2, iclass 13, count 0 2006.201.19:36:07.85#ibcon#flushed, iclass 13, count 0 2006.201.19:36:07.85#ibcon#about to write, iclass 13, count 0 2006.201.19:36:07.85#ibcon#wrote, iclass 13, count 0 2006.201.19:36:07.85#ibcon#about to read 3, iclass 13, count 0 2006.201.19:36:07.88#ibcon#read 3, iclass 13, count 0 2006.201.19:36:07.88#ibcon#about to read 4, iclass 13, count 0 2006.201.19:36:07.88#ibcon#read 4, iclass 13, count 0 2006.201.19:36:07.88#ibcon#about to read 5, iclass 13, count 0 2006.201.19:36:07.88#ibcon#read 5, iclass 13, count 0 2006.201.19:36:07.88#ibcon#about to read 6, iclass 13, count 0 2006.201.19:36:07.88#ibcon#read 6, iclass 13, count 0 2006.201.19:36:07.88#ibcon#end of sib2, iclass 13, count 0 2006.201.19:36:07.88#ibcon#*after write, iclass 13, count 0 2006.201.19:36:07.88#ibcon#*before return 0, iclass 13, count 0 2006.201.19:36:07.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:36:07.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:36:07.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:36:07.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:36:07.88$vck44/vblo=2,634.99 2006.201.19:36:07.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.19:36:07.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.19:36:07.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:07.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:07.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:07.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:07.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:36:07.88#ibcon#first serial, iclass 15, count 0 2006.201.19:36:07.88#ibcon#enter sib2, iclass 15, count 0 2006.201.19:36:07.88#ibcon#flushed, iclass 15, count 0 2006.201.19:36:07.88#ibcon#about to write, iclass 15, count 0 2006.201.19:36:07.88#ibcon#wrote, iclass 15, count 0 2006.201.19:36:07.88#ibcon#about to read 3, iclass 15, count 0 2006.201.19:36:07.90#ibcon#read 3, iclass 15, count 0 2006.201.19:36:07.90#ibcon#about to read 4, iclass 15, count 0 2006.201.19:36:07.90#ibcon#read 4, iclass 15, count 0 2006.201.19:36:07.90#ibcon#about to read 5, iclass 15, count 0 2006.201.19:36:07.90#ibcon#read 5, iclass 15, count 0 2006.201.19:36:07.90#ibcon#about to read 6, iclass 15, count 0 2006.201.19:36:07.90#ibcon#read 6, iclass 15, count 0 2006.201.19:36:07.90#ibcon#end of sib2, iclass 15, count 0 2006.201.19:36:07.90#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:36:07.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:36:07.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:36:07.90#ibcon#*before write, iclass 15, count 0 2006.201.19:36:07.90#ibcon#enter sib2, iclass 15, count 0 2006.201.19:36:07.90#ibcon#flushed, iclass 15, count 0 2006.201.19:36:07.90#ibcon#about to write, iclass 15, count 0 2006.201.19:36:07.90#ibcon#wrote, iclass 15, count 0 2006.201.19:36:07.90#ibcon#about to read 3, iclass 15, count 0 2006.201.19:36:07.95#ibcon#read 3, iclass 15, count 0 2006.201.19:36:07.95#ibcon#about to read 4, iclass 15, count 0 2006.201.19:36:07.95#ibcon#read 4, iclass 15, count 0 2006.201.19:36:07.95#ibcon#about to read 5, iclass 15, count 0 2006.201.19:36:07.95#ibcon#read 5, iclass 15, count 0 2006.201.19:36:07.95#ibcon#about to read 6, iclass 15, count 0 2006.201.19:36:07.95#ibcon#read 6, iclass 15, count 0 2006.201.19:36:07.95#ibcon#end of sib2, iclass 15, count 0 2006.201.19:36:07.95#ibcon#*after write, iclass 15, count 0 2006.201.19:36:07.95#ibcon#*before return 0, iclass 15, count 0 2006.201.19:36:07.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:07.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:36:07.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:36:07.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:36:07.95$vck44/vb=2,5 2006.201.19:36:07.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.19:36:07.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.19:36:07.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:07.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:08.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:08.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:08.00#ibcon#enter wrdev, iclass 17, count 2 2006.201.19:36:08.00#ibcon#first serial, iclass 17, count 2 2006.201.19:36:08.00#ibcon#enter sib2, iclass 17, count 2 2006.201.19:36:08.00#ibcon#flushed, iclass 17, count 2 2006.201.19:36:08.00#ibcon#about to write, iclass 17, count 2 2006.201.19:36:08.00#ibcon#wrote, iclass 17, count 2 2006.201.19:36:08.00#ibcon#about to read 3, iclass 17, count 2 2006.201.19:36:08.02#ibcon#read 3, iclass 17, count 2 2006.201.19:36:08.02#ibcon#about to read 4, iclass 17, count 2 2006.201.19:36:08.02#ibcon#read 4, iclass 17, count 2 2006.201.19:36:08.02#ibcon#about to read 5, iclass 17, count 2 2006.201.19:36:08.02#ibcon#read 5, iclass 17, count 2 2006.201.19:36:08.02#ibcon#about to read 6, iclass 17, count 2 2006.201.19:36:08.02#ibcon#read 6, iclass 17, count 2 2006.201.19:36:08.02#ibcon#end of sib2, iclass 17, count 2 2006.201.19:36:08.02#ibcon#*mode == 0, iclass 17, count 2 2006.201.19:36:08.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.19:36:08.02#ibcon#[27=AT02-05\r\n] 2006.201.19:36:08.02#ibcon#*before write, iclass 17, count 2 2006.201.19:36:08.02#ibcon#enter sib2, iclass 17, count 2 2006.201.19:36:08.02#ibcon#flushed, iclass 17, count 2 2006.201.19:36:08.02#ibcon#about to write, iclass 17, count 2 2006.201.19:36:08.02#ibcon#wrote, iclass 17, count 2 2006.201.19:36:08.02#ibcon#about to read 3, iclass 17, count 2 2006.201.19:36:08.05#ibcon#read 3, iclass 17, count 2 2006.201.19:36:08.05#ibcon#about to read 4, iclass 17, count 2 2006.201.19:36:08.05#ibcon#read 4, iclass 17, count 2 2006.201.19:36:08.05#ibcon#about to read 5, iclass 17, count 2 2006.201.19:36:08.05#ibcon#read 5, iclass 17, count 2 2006.201.19:36:08.05#ibcon#about to read 6, iclass 17, count 2 2006.201.19:36:08.05#ibcon#read 6, iclass 17, count 2 2006.201.19:36:08.05#ibcon#end of sib2, iclass 17, count 2 2006.201.19:36:08.05#ibcon#*after write, iclass 17, count 2 2006.201.19:36:08.05#ibcon#*before return 0, iclass 17, count 2 2006.201.19:36:08.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:08.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:36:08.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.19:36:08.05#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:08.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:08.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:08.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:08.17#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:36:08.17#ibcon#first serial, iclass 17, count 0 2006.201.19:36:08.17#ibcon#enter sib2, iclass 17, count 0 2006.201.19:36:08.17#ibcon#flushed, iclass 17, count 0 2006.201.19:36:08.17#ibcon#about to write, iclass 17, count 0 2006.201.19:36:08.17#ibcon#wrote, iclass 17, count 0 2006.201.19:36:08.17#ibcon#about to read 3, iclass 17, count 0 2006.201.19:36:08.19#ibcon#read 3, iclass 17, count 0 2006.201.19:36:08.19#ibcon#about to read 4, iclass 17, count 0 2006.201.19:36:08.19#ibcon#read 4, iclass 17, count 0 2006.201.19:36:08.19#ibcon#about to read 5, iclass 17, count 0 2006.201.19:36:08.19#ibcon#read 5, iclass 17, count 0 2006.201.19:36:08.19#ibcon#about to read 6, iclass 17, count 0 2006.201.19:36:08.19#ibcon#read 6, iclass 17, count 0 2006.201.19:36:08.19#ibcon#end of sib2, iclass 17, count 0 2006.201.19:36:08.19#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:36:08.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:36:08.19#ibcon#[27=USB\r\n] 2006.201.19:36:08.19#ibcon#*before write, iclass 17, count 0 2006.201.19:36:08.19#ibcon#enter sib2, iclass 17, count 0 2006.201.19:36:08.19#ibcon#flushed, iclass 17, count 0 2006.201.19:36:08.19#ibcon#about to write, iclass 17, count 0 2006.201.19:36:08.19#ibcon#wrote, iclass 17, count 0 2006.201.19:36:08.19#ibcon#about to read 3, iclass 17, count 0 2006.201.19:36:08.22#ibcon#read 3, iclass 17, count 0 2006.201.19:36:08.22#ibcon#about to read 4, iclass 17, count 0 2006.201.19:36:08.22#ibcon#read 4, iclass 17, count 0 2006.201.19:36:08.22#ibcon#about to read 5, iclass 17, count 0 2006.201.19:36:08.22#ibcon#read 5, iclass 17, count 0 2006.201.19:36:08.22#ibcon#about to read 6, iclass 17, count 0 2006.201.19:36:08.22#ibcon#read 6, iclass 17, count 0 2006.201.19:36:08.22#ibcon#end of sib2, iclass 17, count 0 2006.201.19:36:08.22#ibcon#*after write, iclass 17, count 0 2006.201.19:36:08.22#ibcon#*before return 0, iclass 17, count 0 2006.201.19:36:08.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:08.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:36:08.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:36:08.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:36:08.22$vck44/vblo=3,649.99 2006.201.19:36:08.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.19:36:08.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.19:36:08.22#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:08.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:08.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:08.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:08.22#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:36:08.22#ibcon#first serial, iclass 19, count 0 2006.201.19:36:08.22#ibcon#enter sib2, iclass 19, count 0 2006.201.19:36:08.22#ibcon#flushed, iclass 19, count 0 2006.201.19:36:08.22#ibcon#about to write, iclass 19, count 0 2006.201.19:36:08.22#ibcon#wrote, iclass 19, count 0 2006.201.19:36:08.22#ibcon#about to read 3, iclass 19, count 0 2006.201.19:36:08.24#ibcon#read 3, iclass 19, count 0 2006.201.19:36:08.24#ibcon#about to read 4, iclass 19, count 0 2006.201.19:36:08.24#ibcon#read 4, iclass 19, count 0 2006.201.19:36:08.24#ibcon#about to read 5, iclass 19, count 0 2006.201.19:36:08.24#ibcon#read 5, iclass 19, count 0 2006.201.19:36:08.24#ibcon#about to read 6, iclass 19, count 0 2006.201.19:36:08.24#ibcon#read 6, iclass 19, count 0 2006.201.19:36:08.24#ibcon#end of sib2, iclass 19, count 0 2006.201.19:36:08.24#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:36:08.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:36:08.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:36:08.24#ibcon#*before write, iclass 19, count 0 2006.201.19:36:08.24#ibcon#enter sib2, iclass 19, count 0 2006.201.19:36:08.24#ibcon#flushed, iclass 19, count 0 2006.201.19:36:08.24#ibcon#about to write, iclass 19, count 0 2006.201.19:36:08.24#ibcon#wrote, iclass 19, count 0 2006.201.19:36:08.24#ibcon#about to read 3, iclass 19, count 0 2006.201.19:36:08.28#ibcon#read 3, iclass 19, count 0 2006.201.19:36:08.28#ibcon#about to read 4, iclass 19, count 0 2006.201.19:36:08.28#ibcon#read 4, iclass 19, count 0 2006.201.19:36:08.28#ibcon#about to read 5, iclass 19, count 0 2006.201.19:36:08.28#ibcon#read 5, iclass 19, count 0 2006.201.19:36:08.28#ibcon#about to read 6, iclass 19, count 0 2006.201.19:36:08.28#ibcon#read 6, iclass 19, count 0 2006.201.19:36:08.28#ibcon#end of sib2, iclass 19, count 0 2006.201.19:36:08.28#ibcon#*after write, iclass 19, count 0 2006.201.19:36:08.28#ibcon#*before return 0, iclass 19, count 0 2006.201.19:36:08.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:08.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:36:08.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:36:08.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:36:08.28$vck44/vb=3,4 2006.201.19:36:08.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.19:36:08.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.19:36:08.28#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:08.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:08.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:08.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:08.34#ibcon#enter wrdev, iclass 21, count 2 2006.201.19:36:08.34#ibcon#first serial, iclass 21, count 2 2006.201.19:36:08.34#ibcon#enter sib2, iclass 21, count 2 2006.201.19:36:08.34#ibcon#flushed, iclass 21, count 2 2006.201.19:36:08.34#ibcon#about to write, iclass 21, count 2 2006.201.19:36:08.34#ibcon#wrote, iclass 21, count 2 2006.201.19:36:08.34#ibcon#about to read 3, iclass 21, count 2 2006.201.19:36:08.36#ibcon#read 3, iclass 21, count 2 2006.201.19:36:08.36#ibcon#about to read 4, iclass 21, count 2 2006.201.19:36:08.36#ibcon#read 4, iclass 21, count 2 2006.201.19:36:08.36#ibcon#about to read 5, iclass 21, count 2 2006.201.19:36:08.36#ibcon#read 5, iclass 21, count 2 2006.201.19:36:08.36#ibcon#about to read 6, iclass 21, count 2 2006.201.19:36:08.36#ibcon#read 6, iclass 21, count 2 2006.201.19:36:08.36#ibcon#end of sib2, iclass 21, count 2 2006.201.19:36:08.36#ibcon#*mode == 0, iclass 21, count 2 2006.201.19:36:08.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.19:36:08.36#ibcon#[27=AT03-04\r\n] 2006.201.19:36:08.36#ibcon#*before write, iclass 21, count 2 2006.201.19:36:08.36#ibcon#enter sib2, iclass 21, count 2 2006.201.19:36:08.36#ibcon#flushed, iclass 21, count 2 2006.201.19:36:08.36#ibcon#about to write, iclass 21, count 2 2006.201.19:36:08.36#ibcon#wrote, iclass 21, count 2 2006.201.19:36:08.36#ibcon#about to read 3, iclass 21, count 2 2006.201.19:36:08.39#ibcon#read 3, iclass 21, count 2 2006.201.19:36:08.39#ibcon#about to read 4, iclass 21, count 2 2006.201.19:36:08.39#ibcon#read 4, iclass 21, count 2 2006.201.19:36:08.39#ibcon#about to read 5, iclass 21, count 2 2006.201.19:36:08.39#ibcon#read 5, iclass 21, count 2 2006.201.19:36:08.39#ibcon#about to read 6, iclass 21, count 2 2006.201.19:36:08.39#ibcon#read 6, iclass 21, count 2 2006.201.19:36:08.39#ibcon#end of sib2, iclass 21, count 2 2006.201.19:36:08.39#ibcon#*after write, iclass 21, count 2 2006.201.19:36:08.39#ibcon#*before return 0, iclass 21, count 2 2006.201.19:36:08.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:08.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:36:08.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.19:36:08.39#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:08.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:08.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:08.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:08.51#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:36:08.51#ibcon#first serial, iclass 21, count 0 2006.201.19:36:08.51#ibcon#enter sib2, iclass 21, count 0 2006.201.19:36:08.51#ibcon#flushed, iclass 21, count 0 2006.201.19:36:08.51#ibcon#about to write, iclass 21, count 0 2006.201.19:36:08.51#ibcon#wrote, iclass 21, count 0 2006.201.19:36:08.51#ibcon#about to read 3, iclass 21, count 0 2006.201.19:36:08.53#ibcon#read 3, iclass 21, count 0 2006.201.19:36:08.53#ibcon#about to read 4, iclass 21, count 0 2006.201.19:36:08.53#ibcon#read 4, iclass 21, count 0 2006.201.19:36:08.53#ibcon#about to read 5, iclass 21, count 0 2006.201.19:36:08.53#ibcon#read 5, iclass 21, count 0 2006.201.19:36:08.53#ibcon#about to read 6, iclass 21, count 0 2006.201.19:36:08.53#ibcon#read 6, iclass 21, count 0 2006.201.19:36:08.53#ibcon#end of sib2, iclass 21, count 0 2006.201.19:36:08.53#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:36:08.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:36:08.53#ibcon#[27=USB\r\n] 2006.201.19:36:08.53#ibcon#*before write, iclass 21, count 0 2006.201.19:36:08.53#ibcon#enter sib2, iclass 21, count 0 2006.201.19:36:08.53#ibcon#flushed, iclass 21, count 0 2006.201.19:36:08.53#ibcon#about to write, iclass 21, count 0 2006.201.19:36:08.53#ibcon#wrote, iclass 21, count 0 2006.201.19:36:08.53#ibcon#about to read 3, iclass 21, count 0 2006.201.19:36:08.56#ibcon#read 3, iclass 21, count 0 2006.201.19:36:08.56#ibcon#about to read 4, iclass 21, count 0 2006.201.19:36:08.56#ibcon#read 4, iclass 21, count 0 2006.201.19:36:08.56#ibcon#about to read 5, iclass 21, count 0 2006.201.19:36:08.56#ibcon#read 5, iclass 21, count 0 2006.201.19:36:08.56#ibcon#about to read 6, iclass 21, count 0 2006.201.19:36:08.56#ibcon#read 6, iclass 21, count 0 2006.201.19:36:08.56#ibcon#end of sib2, iclass 21, count 0 2006.201.19:36:08.56#ibcon#*after write, iclass 21, count 0 2006.201.19:36:08.56#ibcon#*before return 0, iclass 21, count 0 2006.201.19:36:08.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:08.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:36:08.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:36:08.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:36:08.56$vck44/vblo=4,679.99 2006.201.19:36:08.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.19:36:08.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.19:36:08.56#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:08.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:08.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:08.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:08.56#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:36:08.56#ibcon#first serial, iclass 23, count 0 2006.201.19:36:08.56#ibcon#enter sib2, iclass 23, count 0 2006.201.19:36:08.56#ibcon#flushed, iclass 23, count 0 2006.201.19:36:08.56#ibcon#about to write, iclass 23, count 0 2006.201.19:36:08.56#ibcon#wrote, iclass 23, count 0 2006.201.19:36:08.56#ibcon#about to read 3, iclass 23, count 0 2006.201.19:36:08.58#ibcon#read 3, iclass 23, count 0 2006.201.19:36:08.58#ibcon#about to read 4, iclass 23, count 0 2006.201.19:36:08.58#ibcon#read 4, iclass 23, count 0 2006.201.19:36:08.58#ibcon#about to read 5, iclass 23, count 0 2006.201.19:36:08.58#ibcon#read 5, iclass 23, count 0 2006.201.19:36:08.58#ibcon#about to read 6, iclass 23, count 0 2006.201.19:36:08.58#ibcon#read 6, iclass 23, count 0 2006.201.19:36:08.58#ibcon#end of sib2, iclass 23, count 0 2006.201.19:36:08.58#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:36:08.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:36:08.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:36:08.58#ibcon#*before write, iclass 23, count 0 2006.201.19:36:08.58#ibcon#enter sib2, iclass 23, count 0 2006.201.19:36:08.58#ibcon#flushed, iclass 23, count 0 2006.201.19:36:08.58#ibcon#about to write, iclass 23, count 0 2006.201.19:36:08.58#ibcon#wrote, iclass 23, count 0 2006.201.19:36:08.58#ibcon#about to read 3, iclass 23, count 0 2006.201.19:36:08.62#ibcon#read 3, iclass 23, count 0 2006.201.19:36:08.62#ibcon#about to read 4, iclass 23, count 0 2006.201.19:36:08.62#ibcon#read 4, iclass 23, count 0 2006.201.19:36:08.62#ibcon#about to read 5, iclass 23, count 0 2006.201.19:36:08.62#ibcon#read 5, iclass 23, count 0 2006.201.19:36:08.62#ibcon#about to read 6, iclass 23, count 0 2006.201.19:36:08.62#ibcon#read 6, iclass 23, count 0 2006.201.19:36:08.62#ibcon#end of sib2, iclass 23, count 0 2006.201.19:36:08.62#ibcon#*after write, iclass 23, count 0 2006.201.19:36:08.62#ibcon#*before return 0, iclass 23, count 0 2006.201.19:36:08.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:08.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:36:08.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:36:08.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:36:08.62$vck44/vb=4,5 2006.201.19:36:08.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.19:36:08.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.19:36:08.62#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:08.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:08.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:08.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:08.68#ibcon#enter wrdev, iclass 25, count 2 2006.201.19:36:08.68#ibcon#first serial, iclass 25, count 2 2006.201.19:36:08.68#ibcon#enter sib2, iclass 25, count 2 2006.201.19:36:08.68#ibcon#flushed, iclass 25, count 2 2006.201.19:36:08.68#ibcon#about to write, iclass 25, count 2 2006.201.19:36:08.68#ibcon#wrote, iclass 25, count 2 2006.201.19:36:08.68#ibcon#about to read 3, iclass 25, count 2 2006.201.19:36:08.70#ibcon#read 3, iclass 25, count 2 2006.201.19:36:08.70#ibcon#about to read 4, iclass 25, count 2 2006.201.19:36:08.70#ibcon#read 4, iclass 25, count 2 2006.201.19:36:08.70#ibcon#about to read 5, iclass 25, count 2 2006.201.19:36:08.70#ibcon#read 5, iclass 25, count 2 2006.201.19:36:08.70#ibcon#about to read 6, iclass 25, count 2 2006.201.19:36:08.70#ibcon#read 6, iclass 25, count 2 2006.201.19:36:08.70#ibcon#end of sib2, iclass 25, count 2 2006.201.19:36:08.70#ibcon#*mode == 0, iclass 25, count 2 2006.201.19:36:08.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.19:36:08.70#ibcon#[27=AT04-05\r\n] 2006.201.19:36:08.70#ibcon#*before write, iclass 25, count 2 2006.201.19:36:08.70#ibcon#enter sib2, iclass 25, count 2 2006.201.19:36:08.70#ibcon#flushed, iclass 25, count 2 2006.201.19:36:08.70#ibcon#about to write, iclass 25, count 2 2006.201.19:36:08.70#ibcon#wrote, iclass 25, count 2 2006.201.19:36:08.70#ibcon#about to read 3, iclass 25, count 2 2006.201.19:36:08.73#ibcon#read 3, iclass 25, count 2 2006.201.19:36:08.73#ibcon#about to read 4, iclass 25, count 2 2006.201.19:36:08.73#ibcon#read 4, iclass 25, count 2 2006.201.19:36:08.73#ibcon#about to read 5, iclass 25, count 2 2006.201.19:36:08.73#ibcon#read 5, iclass 25, count 2 2006.201.19:36:08.73#ibcon#about to read 6, iclass 25, count 2 2006.201.19:36:08.73#ibcon#read 6, iclass 25, count 2 2006.201.19:36:08.73#ibcon#end of sib2, iclass 25, count 2 2006.201.19:36:08.73#ibcon#*after write, iclass 25, count 2 2006.201.19:36:08.73#ibcon#*before return 0, iclass 25, count 2 2006.201.19:36:08.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:08.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:36:08.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.19:36:08.73#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:08.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:08.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:08.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:08.85#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:36:08.85#ibcon#first serial, iclass 25, count 0 2006.201.19:36:08.85#ibcon#enter sib2, iclass 25, count 0 2006.201.19:36:08.85#ibcon#flushed, iclass 25, count 0 2006.201.19:36:08.85#ibcon#about to write, iclass 25, count 0 2006.201.19:36:08.85#ibcon#wrote, iclass 25, count 0 2006.201.19:36:08.85#ibcon#about to read 3, iclass 25, count 0 2006.201.19:36:08.87#ibcon#read 3, iclass 25, count 0 2006.201.19:36:08.87#ibcon#about to read 4, iclass 25, count 0 2006.201.19:36:08.87#ibcon#read 4, iclass 25, count 0 2006.201.19:36:08.87#ibcon#about to read 5, iclass 25, count 0 2006.201.19:36:08.87#ibcon#read 5, iclass 25, count 0 2006.201.19:36:08.87#ibcon#about to read 6, iclass 25, count 0 2006.201.19:36:08.87#ibcon#read 6, iclass 25, count 0 2006.201.19:36:08.87#ibcon#end of sib2, iclass 25, count 0 2006.201.19:36:08.87#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:36:08.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:36:08.87#ibcon#[27=USB\r\n] 2006.201.19:36:08.87#ibcon#*before write, iclass 25, count 0 2006.201.19:36:08.87#ibcon#enter sib2, iclass 25, count 0 2006.201.19:36:08.87#ibcon#flushed, iclass 25, count 0 2006.201.19:36:08.87#ibcon#about to write, iclass 25, count 0 2006.201.19:36:08.87#ibcon#wrote, iclass 25, count 0 2006.201.19:36:08.87#ibcon#about to read 3, iclass 25, count 0 2006.201.19:36:08.90#ibcon#read 3, iclass 25, count 0 2006.201.19:36:08.90#ibcon#about to read 4, iclass 25, count 0 2006.201.19:36:08.90#ibcon#read 4, iclass 25, count 0 2006.201.19:36:08.90#ibcon#about to read 5, iclass 25, count 0 2006.201.19:36:08.90#ibcon#read 5, iclass 25, count 0 2006.201.19:36:08.90#ibcon#about to read 6, iclass 25, count 0 2006.201.19:36:08.90#ibcon#read 6, iclass 25, count 0 2006.201.19:36:08.90#ibcon#end of sib2, iclass 25, count 0 2006.201.19:36:08.90#ibcon#*after write, iclass 25, count 0 2006.201.19:36:08.90#ibcon#*before return 0, iclass 25, count 0 2006.201.19:36:08.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:08.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:36:08.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:36:08.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:36:08.90$vck44/vblo=5,709.99 2006.201.19:36:08.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.19:36:08.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.19:36:08.90#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:08.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:08.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:08.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:08.90#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:36:08.90#ibcon#first serial, iclass 27, count 0 2006.201.19:36:08.90#ibcon#enter sib2, iclass 27, count 0 2006.201.19:36:08.90#ibcon#flushed, iclass 27, count 0 2006.201.19:36:08.90#ibcon#about to write, iclass 27, count 0 2006.201.19:36:08.90#ibcon#wrote, iclass 27, count 0 2006.201.19:36:08.90#ibcon#about to read 3, iclass 27, count 0 2006.201.19:36:08.92#ibcon#read 3, iclass 27, count 0 2006.201.19:36:08.92#ibcon#about to read 4, iclass 27, count 0 2006.201.19:36:08.92#ibcon#read 4, iclass 27, count 0 2006.201.19:36:08.92#ibcon#about to read 5, iclass 27, count 0 2006.201.19:36:08.92#ibcon#read 5, iclass 27, count 0 2006.201.19:36:08.92#ibcon#about to read 6, iclass 27, count 0 2006.201.19:36:08.92#ibcon#read 6, iclass 27, count 0 2006.201.19:36:08.92#ibcon#end of sib2, iclass 27, count 0 2006.201.19:36:08.92#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:36:08.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:36:08.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:36:08.92#ibcon#*before write, iclass 27, count 0 2006.201.19:36:08.92#ibcon#enter sib2, iclass 27, count 0 2006.201.19:36:08.92#ibcon#flushed, iclass 27, count 0 2006.201.19:36:08.92#ibcon#about to write, iclass 27, count 0 2006.201.19:36:08.92#ibcon#wrote, iclass 27, count 0 2006.201.19:36:08.92#ibcon#about to read 3, iclass 27, count 0 2006.201.19:36:08.97#ibcon#read 3, iclass 27, count 0 2006.201.19:36:08.97#ibcon#about to read 4, iclass 27, count 0 2006.201.19:36:08.97#ibcon#read 4, iclass 27, count 0 2006.201.19:36:08.97#ibcon#about to read 5, iclass 27, count 0 2006.201.19:36:08.97#ibcon#read 5, iclass 27, count 0 2006.201.19:36:08.97#ibcon#about to read 6, iclass 27, count 0 2006.201.19:36:08.97#ibcon#read 6, iclass 27, count 0 2006.201.19:36:08.97#ibcon#end of sib2, iclass 27, count 0 2006.201.19:36:08.97#ibcon#*after write, iclass 27, count 0 2006.201.19:36:08.97#ibcon#*before return 0, iclass 27, count 0 2006.201.19:36:08.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:08.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:36:08.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:36:08.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:36:08.97$vck44/vb=5,4 2006.201.19:36:08.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.19:36:08.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.19:36:08.97#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:08.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:09.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:09.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:09.02#ibcon#enter wrdev, iclass 29, count 2 2006.201.19:36:09.02#ibcon#first serial, iclass 29, count 2 2006.201.19:36:09.02#ibcon#enter sib2, iclass 29, count 2 2006.201.19:36:09.02#ibcon#flushed, iclass 29, count 2 2006.201.19:36:09.02#ibcon#about to write, iclass 29, count 2 2006.201.19:36:09.02#ibcon#wrote, iclass 29, count 2 2006.201.19:36:09.02#ibcon#about to read 3, iclass 29, count 2 2006.201.19:36:09.04#ibcon#read 3, iclass 29, count 2 2006.201.19:36:09.04#ibcon#about to read 4, iclass 29, count 2 2006.201.19:36:09.04#ibcon#read 4, iclass 29, count 2 2006.201.19:36:09.04#ibcon#about to read 5, iclass 29, count 2 2006.201.19:36:09.04#ibcon#read 5, iclass 29, count 2 2006.201.19:36:09.04#ibcon#about to read 6, iclass 29, count 2 2006.201.19:36:09.04#ibcon#read 6, iclass 29, count 2 2006.201.19:36:09.04#ibcon#end of sib2, iclass 29, count 2 2006.201.19:36:09.04#ibcon#*mode == 0, iclass 29, count 2 2006.201.19:36:09.04#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.19:36:09.04#ibcon#[27=AT05-04\r\n] 2006.201.19:36:09.04#ibcon#*before write, iclass 29, count 2 2006.201.19:36:09.04#ibcon#enter sib2, iclass 29, count 2 2006.201.19:36:09.04#ibcon#flushed, iclass 29, count 2 2006.201.19:36:09.04#ibcon#about to write, iclass 29, count 2 2006.201.19:36:09.04#ibcon#wrote, iclass 29, count 2 2006.201.19:36:09.04#ibcon#about to read 3, iclass 29, count 2 2006.201.19:36:09.07#ibcon#read 3, iclass 29, count 2 2006.201.19:36:09.07#ibcon#about to read 4, iclass 29, count 2 2006.201.19:36:09.07#ibcon#read 4, iclass 29, count 2 2006.201.19:36:09.07#ibcon#about to read 5, iclass 29, count 2 2006.201.19:36:09.07#ibcon#read 5, iclass 29, count 2 2006.201.19:36:09.07#ibcon#about to read 6, iclass 29, count 2 2006.201.19:36:09.07#ibcon#read 6, iclass 29, count 2 2006.201.19:36:09.07#ibcon#end of sib2, iclass 29, count 2 2006.201.19:36:09.07#ibcon#*after write, iclass 29, count 2 2006.201.19:36:09.07#ibcon#*before return 0, iclass 29, count 2 2006.201.19:36:09.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:09.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:36:09.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.19:36:09.07#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:09.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:09.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:09.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:09.19#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:36:09.19#ibcon#first serial, iclass 29, count 0 2006.201.19:36:09.19#ibcon#enter sib2, iclass 29, count 0 2006.201.19:36:09.19#ibcon#flushed, iclass 29, count 0 2006.201.19:36:09.19#ibcon#about to write, iclass 29, count 0 2006.201.19:36:09.19#ibcon#wrote, iclass 29, count 0 2006.201.19:36:09.19#ibcon#about to read 3, iclass 29, count 0 2006.201.19:36:09.21#ibcon#read 3, iclass 29, count 0 2006.201.19:36:09.21#ibcon#about to read 4, iclass 29, count 0 2006.201.19:36:09.21#ibcon#read 4, iclass 29, count 0 2006.201.19:36:09.21#ibcon#about to read 5, iclass 29, count 0 2006.201.19:36:09.21#ibcon#read 5, iclass 29, count 0 2006.201.19:36:09.21#ibcon#about to read 6, iclass 29, count 0 2006.201.19:36:09.21#ibcon#read 6, iclass 29, count 0 2006.201.19:36:09.21#ibcon#end of sib2, iclass 29, count 0 2006.201.19:36:09.21#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:36:09.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:36:09.21#ibcon#[27=USB\r\n] 2006.201.19:36:09.21#ibcon#*before write, iclass 29, count 0 2006.201.19:36:09.21#ibcon#enter sib2, iclass 29, count 0 2006.201.19:36:09.21#ibcon#flushed, iclass 29, count 0 2006.201.19:36:09.21#ibcon#about to write, iclass 29, count 0 2006.201.19:36:09.21#ibcon#wrote, iclass 29, count 0 2006.201.19:36:09.21#ibcon#about to read 3, iclass 29, count 0 2006.201.19:36:09.24#ibcon#read 3, iclass 29, count 0 2006.201.19:36:09.24#ibcon#about to read 4, iclass 29, count 0 2006.201.19:36:09.24#ibcon#read 4, iclass 29, count 0 2006.201.19:36:09.24#ibcon#about to read 5, iclass 29, count 0 2006.201.19:36:09.24#ibcon#read 5, iclass 29, count 0 2006.201.19:36:09.24#ibcon#about to read 6, iclass 29, count 0 2006.201.19:36:09.24#ibcon#read 6, iclass 29, count 0 2006.201.19:36:09.24#ibcon#end of sib2, iclass 29, count 0 2006.201.19:36:09.24#ibcon#*after write, iclass 29, count 0 2006.201.19:36:09.24#ibcon#*before return 0, iclass 29, count 0 2006.201.19:36:09.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:09.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:36:09.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:36:09.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:36:09.24$vck44/vblo=6,719.99 2006.201.19:36:09.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.19:36:09.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.19:36:09.24#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:09.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:09.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:09.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:09.24#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:36:09.24#ibcon#first serial, iclass 31, count 0 2006.201.19:36:09.24#ibcon#enter sib2, iclass 31, count 0 2006.201.19:36:09.24#ibcon#flushed, iclass 31, count 0 2006.201.19:36:09.24#ibcon#about to write, iclass 31, count 0 2006.201.19:36:09.24#ibcon#wrote, iclass 31, count 0 2006.201.19:36:09.24#ibcon#about to read 3, iclass 31, count 0 2006.201.19:36:09.26#ibcon#read 3, iclass 31, count 0 2006.201.19:36:09.26#ibcon#about to read 4, iclass 31, count 0 2006.201.19:36:09.26#ibcon#read 4, iclass 31, count 0 2006.201.19:36:09.26#ibcon#about to read 5, iclass 31, count 0 2006.201.19:36:09.26#ibcon#read 5, iclass 31, count 0 2006.201.19:36:09.26#ibcon#about to read 6, iclass 31, count 0 2006.201.19:36:09.26#ibcon#read 6, iclass 31, count 0 2006.201.19:36:09.26#ibcon#end of sib2, iclass 31, count 0 2006.201.19:36:09.26#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:36:09.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:36:09.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:36:09.26#ibcon#*before write, iclass 31, count 0 2006.201.19:36:09.26#ibcon#enter sib2, iclass 31, count 0 2006.201.19:36:09.26#ibcon#flushed, iclass 31, count 0 2006.201.19:36:09.26#ibcon#about to write, iclass 31, count 0 2006.201.19:36:09.26#ibcon#wrote, iclass 31, count 0 2006.201.19:36:09.26#ibcon#about to read 3, iclass 31, count 0 2006.201.19:36:09.30#ibcon#read 3, iclass 31, count 0 2006.201.19:36:09.30#ibcon#about to read 4, iclass 31, count 0 2006.201.19:36:09.30#ibcon#read 4, iclass 31, count 0 2006.201.19:36:09.30#ibcon#about to read 5, iclass 31, count 0 2006.201.19:36:09.30#ibcon#read 5, iclass 31, count 0 2006.201.19:36:09.30#ibcon#about to read 6, iclass 31, count 0 2006.201.19:36:09.30#ibcon#read 6, iclass 31, count 0 2006.201.19:36:09.30#ibcon#end of sib2, iclass 31, count 0 2006.201.19:36:09.30#ibcon#*after write, iclass 31, count 0 2006.201.19:36:09.30#ibcon#*before return 0, iclass 31, count 0 2006.201.19:36:09.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:09.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:36:09.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:36:09.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:36:09.30$vck44/vb=6,4 2006.201.19:36:09.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.19:36:09.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.19:36:09.30#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:09.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:09.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:09.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:09.36#ibcon#enter wrdev, iclass 33, count 2 2006.201.19:36:09.36#ibcon#first serial, iclass 33, count 2 2006.201.19:36:09.36#ibcon#enter sib2, iclass 33, count 2 2006.201.19:36:09.36#ibcon#flushed, iclass 33, count 2 2006.201.19:36:09.36#ibcon#about to write, iclass 33, count 2 2006.201.19:36:09.36#ibcon#wrote, iclass 33, count 2 2006.201.19:36:09.36#ibcon#about to read 3, iclass 33, count 2 2006.201.19:36:09.38#ibcon#read 3, iclass 33, count 2 2006.201.19:36:09.38#ibcon#about to read 4, iclass 33, count 2 2006.201.19:36:09.38#ibcon#read 4, iclass 33, count 2 2006.201.19:36:09.38#ibcon#about to read 5, iclass 33, count 2 2006.201.19:36:09.38#ibcon#read 5, iclass 33, count 2 2006.201.19:36:09.38#ibcon#about to read 6, iclass 33, count 2 2006.201.19:36:09.38#ibcon#read 6, iclass 33, count 2 2006.201.19:36:09.38#ibcon#end of sib2, iclass 33, count 2 2006.201.19:36:09.38#ibcon#*mode == 0, iclass 33, count 2 2006.201.19:36:09.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.19:36:09.38#ibcon#[27=AT06-04\r\n] 2006.201.19:36:09.38#ibcon#*before write, iclass 33, count 2 2006.201.19:36:09.38#ibcon#enter sib2, iclass 33, count 2 2006.201.19:36:09.38#ibcon#flushed, iclass 33, count 2 2006.201.19:36:09.38#ibcon#about to write, iclass 33, count 2 2006.201.19:36:09.38#ibcon#wrote, iclass 33, count 2 2006.201.19:36:09.38#ibcon#about to read 3, iclass 33, count 2 2006.201.19:36:09.41#ibcon#read 3, iclass 33, count 2 2006.201.19:36:09.41#ibcon#about to read 4, iclass 33, count 2 2006.201.19:36:09.41#ibcon#read 4, iclass 33, count 2 2006.201.19:36:09.41#ibcon#about to read 5, iclass 33, count 2 2006.201.19:36:09.41#ibcon#read 5, iclass 33, count 2 2006.201.19:36:09.41#ibcon#about to read 6, iclass 33, count 2 2006.201.19:36:09.41#ibcon#read 6, iclass 33, count 2 2006.201.19:36:09.41#ibcon#end of sib2, iclass 33, count 2 2006.201.19:36:09.41#ibcon#*after write, iclass 33, count 2 2006.201.19:36:09.41#ibcon#*before return 0, iclass 33, count 2 2006.201.19:36:09.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:09.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:36:09.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.19:36:09.41#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:09.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:09.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:09.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:09.53#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:36:09.53#ibcon#first serial, iclass 33, count 0 2006.201.19:36:09.53#ibcon#enter sib2, iclass 33, count 0 2006.201.19:36:09.53#ibcon#flushed, iclass 33, count 0 2006.201.19:36:09.53#ibcon#about to write, iclass 33, count 0 2006.201.19:36:09.53#ibcon#wrote, iclass 33, count 0 2006.201.19:36:09.53#ibcon#about to read 3, iclass 33, count 0 2006.201.19:36:09.55#ibcon#read 3, iclass 33, count 0 2006.201.19:36:09.55#ibcon#about to read 4, iclass 33, count 0 2006.201.19:36:09.55#ibcon#read 4, iclass 33, count 0 2006.201.19:36:09.55#ibcon#about to read 5, iclass 33, count 0 2006.201.19:36:09.55#ibcon#read 5, iclass 33, count 0 2006.201.19:36:09.55#ibcon#about to read 6, iclass 33, count 0 2006.201.19:36:09.55#ibcon#read 6, iclass 33, count 0 2006.201.19:36:09.55#ibcon#end of sib2, iclass 33, count 0 2006.201.19:36:09.55#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:36:09.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:36:09.55#ibcon#[27=USB\r\n] 2006.201.19:36:09.55#ibcon#*before write, iclass 33, count 0 2006.201.19:36:09.55#ibcon#enter sib2, iclass 33, count 0 2006.201.19:36:09.55#ibcon#flushed, iclass 33, count 0 2006.201.19:36:09.55#ibcon#about to write, iclass 33, count 0 2006.201.19:36:09.55#ibcon#wrote, iclass 33, count 0 2006.201.19:36:09.55#ibcon#about to read 3, iclass 33, count 0 2006.201.19:36:09.58#ibcon#read 3, iclass 33, count 0 2006.201.19:36:09.58#ibcon#about to read 4, iclass 33, count 0 2006.201.19:36:09.58#ibcon#read 4, iclass 33, count 0 2006.201.19:36:09.58#ibcon#about to read 5, iclass 33, count 0 2006.201.19:36:09.58#ibcon#read 5, iclass 33, count 0 2006.201.19:36:09.58#ibcon#about to read 6, iclass 33, count 0 2006.201.19:36:09.58#ibcon#read 6, iclass 33, count 0 2006.201.19:36:09.58#ibcon#end of sib2, iclass 33, count 0 2006.201.19:36:09.58#ibcon#*after write, iclass 33, count 0 2006.201.19:36:09.58#ibcon#*before return 0, iclass 33, count 0 2006.201.19:36:09.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:09.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:36:09.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:36:09.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:36:09.58$vck44/vblo=7,734.99 2006.201.19:36:09.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.19:36:09.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.19:36:09.58#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:09.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:09.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:09.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:09.58#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:36:09.58#ibcon#first serial, iclass 35, count 0 2006.201.19:36:09.58#ibcon#enter sib2, iclass 35, count 0 2006.201.19:36:09.58#ibcon#flushed, iclass 35, count 0 2006.201.19:36:09.58#ibcon#about to write, iclass 35, count 0 2006.201.19:36:09.58#ibcon#wrote, iclass 35, count 0 2006.201.19:36:09.58#ibcon#about to read 3, iclass 35, count 0 2006.201.19:36:09.60#ibcon#read 3, iclass 35, count 0 2006.201.19:36:09.60#ibcon#about to read 4, iclass 35, count 0 2006.201.19:36:09.60#ibcon#read 4, iclass 35, count 0 2006.201.19:36:09.60#ibcon#about to read 5, iclass 35, count 0 2006.201.19:36:09.60#ibcon#read 5, iclass 35, count 0 2006.201.19:36:09.60#ibcon#about to read 6, iclass 35, count 0 2006.201.19:36:09.60#ibcon#read 6, iclass 35, count 0 2006.201.19:36:09.60#ibcon#end of sib2, iclass 35, count 0 2006.201.19:36:09.60#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:36:09.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:36:09.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:36:09.60#ibcon#*before write, iclass 35, count 0 2006.201.19:36:09.60#ibcon#enter sib2, iclass 35, count 0 2006.201.19:36:09.60#ibcon#flushed, iclass 35, count 0 2006.201.19:36:09.60#ibcon#about to write, iclass 35, count 0 2006.201.19:36:09.60#ibcon#wrote, iclass 35, count 0 2006.201.19:36:09.60#ibcon#about to read 3, iclass 35, count 0 2006.201.19:36:09.65#ibcon#read 3, iclass 35, count 0 2006.201.19:36:09.65#ibcon#about to read 4, iclass 35, count 0 2006.201.19:36:09.65#ibcon#read 4, iclass 35, count 0 2006.201.19:36:09.65#ibcon#about to read 5, iclass 35, count 0 2006.201.19:36:09.65#ibcon#read 5, iclass 35, count 0 2006.201.19:36:09.65#ibcon#about to read 6, iclass 35, count 0 2006.201.19:36:09.65#ibcon#read 6, iclass 35, count 0 2006.201.19:36:09.65#ibcon#end of sib2, iclass 35, count 0 2006.201.19:36:09.65#ibcon#*after write, iclass 35, count 0 2006.201.19:36:09.65#ibcon#*before return 0, iclass 35, count 0 2006.201.19:36:09.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:09.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:36:09.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:36:09.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:36:09.65$vck44/vb=7,4 2006.201.19:36:09.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.19:36:09.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.19:36:09.65#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:09.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:09.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:09.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:09.70#ibcon#enter wrdev, iclass 37, count 2 2006.201.19:36:09.70#ibcon#first serial, iclass 37, count 2 2006.201.19:36:09.70#ibcon#enter sib2, iclass 37, count 2 2006.201.19:36:09.70#ibcon#flushed, iclass 37, count 2 2006.201.19:36:09.70#ibcon#about to write, iclass 37, count 2 2006.201.19:36:09.70#ibcon#wrote, iclass 37, count 2 2006.201.19:36:09.70#ibcon#about to read 3, iclass 37, count 2 2006.201.19:36:09.72#ibcon#read 3, iclass 37, count 2 2006.201.19:36:09.72#ibcon#about to read 4, iclass 37, count 2 2006.201.19:36:09.72#ibcon#read 4, iclass 37, count 2 2006.201.19:36:09.72#ibcon#about to read 5, iclass 37, count 2 2006.201.19:36:09.72#ibcon#read 5, iclass 37, count 2 2006.201.19:36:09.72#ibcon#about to read 6, iclass 37, count 2 2006.201.19:36:09.72#ibcon#read 6, iclass 37, count 2 2006.201.19:36:09.72#ibcon#end of sib2, iclass 37, count 2 2006.201.19:36:09.72#ibcon#*mode == 0, iclass 37, count 2 2006.201.19:36:09.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.19:36:09.72#ibcon#[27=AT07-04\r\n] 2006.201.19:36:09.72#ibcon#*before write, iclass 37, count 2 2006.201.19:36:09.72#ibcon#enter sib2, iclass 37, count 2 2006.201.19:36:09.72#ibcon#flushed, iclass 37, count 2 2006.201.19:36:09.72#ibcon#about to write, iclass 37, count 2 2006.201.19:36:09.72#ibcon#wrote, iclass 37, count 2 2006.201.19:36:09.72#ibcon#about to read 3, iclass 37, count 2 2006.201.19:36:09.75#ibcon#read 3, iclass 37, count 2 2006.201.19:36:09.75#ibcon#about to read 4, iclass 37, count 2 2006.201.19:36:09.75#ibcon#read 4, iclass 37, count 2 2006.201.19:36:09.75#ibcon#about to read 5, iclass 37, count 2 2006.201.19:36:09.75#ibcon#read 5, iclass 37, count 2 2006.201.19:36:09.75#ibcon#about to read 6, iclass 37, count 2 2006.201.19:36:09.75#ibcon#read 6, iclass 37, count 2 2006.201.19:36:09.75#ibcon#end of sib2, iclass 37, count 2 2006.201.19:36:09.75#ibcon#*after write, iclass 37, count 2 2006.201.19:36:09.75#ibcon#*before return 0, iclass 37, count 2 2006.201.19:36:09.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:09.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:36:09.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.19:36:09.75#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:09.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:09.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:09.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:09.87#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:36:09.87#ibcon#first serial, iclass 37, count 0 2006.201.19:36:09.87#ibcon#enter sib2, iclass 37, count 0 2006.201.19:36:09.87#ibcon#flushed, iclass 37, count 0 2006.201.19:36:09.87#ibcon#about to write, iclass 37, count 0 2006.201.19:36:09.87#ibcon#wrote, iclass 37, count 0 2006.201.19:36:09.87#ibcon#about to read 3, iclass 37, count 0 2006.201.19:36:09.89#ibcon#read 3, iclass 37, count 0 2006.201.19:36:09.89#ibcon#about to read 4, iclass 37, count 0 2006.201.19:36:09.89#ibcon#read 4, iclass 37, count 0 2006.201.19:36:09.89#ibcon#about to read 5, iclass 37, count 0 2006.201.19:36:09.89#ibcon#read 5, iclass 37, count 0 2006.201.19:36:09.89#ibcon#about to read 6, iclass 37, count 0 2006.201.19:36:09.89#ibcon#read 6, iclass 37, count 0 2006.201.19:36:09.89#ibcon#end of sib2, iclass 37, count 0 2006.201.19:36:09.89#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:36:09.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:36:09.89#ibcon#[27=USB\r\n] 2006.201.19:36:09.89#ibcon#*before write, iclass 37, count 0 2006.201.19:36:09.89#ibcon#enter sib2, iclass 37, count 0 2006.201.19:36:09.89#ibcon#flushed, iclass 37, count 0 2006.201.19:36:09.89#ibcon#about to write, iclass 37, count 0 2006.201.19:36:09.89#ibcon#wrote, iclass 37, count 0 2006.201.19:36:09.89#ibcon#about to read 3, iclass 37, count 0 2006.201.19:36:09.92#ibcon#read 3, iclass 37, count 0 2006.201.19:36:09.92#ibcon#about to read 4, iclass 37, count 0 2006.201.19:36:09.92#ibcon#read 4, iclass 37, count 0 2006.201.19:36:09.92#ibcon#about to read 5, iclass 37, count 0 2006.201.19:36:09.92#ibcon#read 5, iclass 37, count 0 2006.201.19:36:09.92#ibcon#about to read 6, iclass 37, count 0 2006.201.19:36:09.92#ibcon#read 6, iclass 37, count 0 2006.201.19:36:09.92#ibcon#end of sib2, iclass 37, count 0 2006.201.19:36:09.92#ibcon#*after write, iclass 37, count 0 2006.201.19:36:09.92#ibcon#*before return 0, iclass 37, count 0 2006.201.19:36:09.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:09.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:36:09.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:36:09.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:36:09.92$vck44/vblo=8,744.99 2006.201.19:36:09.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.19:36:09.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.19:36:09.92#ibcon#ireg 17 cls_cnt 0 2006.201.19:36:09.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:09.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:09.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:09.92#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:36:09.92#ibcon#first serial, iclass 39, count 0 2006.201.19:36:09.92#ibcon#enter sib2, iclass 39, count 0 2006.201.19:36:09.92#ibcon#flushed, iclass 39, count 0 2006.201.19:36:09.92#ibcon#about to write, iclass 39, count 0 2006.201.19:36:09.92#ibcon#wrote, iclass 39, count 0 2006.201.19:36:09.92#ibcon#about to read 3, iclass 39, count 0 2006.201.19:36:09.94#ibcon#read 3, iclass 39, count 0 2006.201.19:36:09.94#ibcon#about to read 4, iclass 39, count 0 2006.201.19:36:09.94#ibcon#read 4, iclass 39, count 0 2006.201.19:36:09.94#ibcon#about to read 5, iclass 39, count 0 2006.201.19:36:09.94#ibcon#read 5, iclass 39, count 0 2006.201.19:36:09.94#ibcon#about to read 6, iclass 39, count 0 2006.201.19:36:09.94#ibcon#read 6, iclass 39, count 0 2006.201.19:36:09.94#ibcon#end of sib2, iclass 39, count 0 2006.201.19:36:09.94#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:36:09.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:36:09.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:36:09.94#ibcon#*before write, iclass 39, count 0 2006.201.19:36:09.94#ibcon#enter sib2, iclass 39, count 0 2006.201.19:36:09.94#ibcon#flushed, iclass 39, count 0 2006.201.19:36:09.94#ibcon#about to write, iclass 39, count 0 2006.201.19:36:09.94#ibcon#wrote, iclass 39, count 0 2006.201.19:36:09.94#ibcon#about to read 3, iclass 39, count 0 2006.201.19:36:09.99#ibcon#read 3, iclass 39, count 0 2006.201.19:36:09.99#ibcon#about to read 4, iclass 39, count 0 2006.201.19:36:09.99#ibcon#read 4, iclass 39, count 0 2006.201.19:36:09.99#ibcon#about to read 5, iclass 39, count 0 2006.201.19:36:09.99#ibcon#read 5, iclass 39, count 0 2006.201.19:36:09.99#ibcon#about to read 6, iclass 39, count 0 2006.201.19:36:09.99#ibcon#read 6, iclass 39, count 0 2006.201.19:36:09.99#ibcon#end of sib2, iclass 39, count 0 2006.201.19:36:09.99#ibcon#*after write, iclass 39, count 0 2006.201.19:36:09.99#ibcon#*before return 0, iclass 39, count 0 2006.201.19:36:09.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:09.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:36:09.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:36:09.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:36:09.99$vck44/vb=8,4 2006.201.19:36:09.99#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.19:36:09.99#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.19:36:09.99#ibcon#ireg 11 cls_cnt 2 2006.201.19:36:09.99#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:10.04#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:10.04#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:10.04#ibcon#enter wrdev, iclass 2, count 2 2006.201.19:36:10.04#ibcon#first serial, iclass 2, count 2 2006.201.19:36:10.04#ibcon#enter sib2, iclass 2, count 2 2006.201.19:36:10.04#ibcon#flushed, iclass 2, count 2 2006.201.19:36:10.04#ibcon#about to write, iclass 2, count 2 2006.201.19:36:10.04#ibcon#wrote, iclass 2, count 2 2006.201.19:36:10.04#ibcon#about to read 3, iclass 2, count 2 2006.201.19:36:10.06#ibcon#read 3, iclass 2, count 2 2006.201.19:36:10.06#ibcon#about to read 4, iclass 2, count 2 2006.201.19:36:10.06#ibcon#read 4, iclass 2, count 2 2006.201.19:36:10.06#ibcon#about to read 5, iclass 2, count 2 2006.201.19:36:10.06#ibcon#read 5, iclass 2, count 2 2006.201.19:36:10.06#ibcon#about to read 6, iclass 2, count 2 2006.201.19:36:10.06#ibcon#read 6, iclass 2, count 2 2006.201.19:36:10.06#ibcon#end of sib2, iclass 2, count 2 2006.201.19:36:10.06#ibcon#*mode == 0, iclass 2, count 2 2006.201.19:36:10.06#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.19:36:10.06#ibcon#[27=AT08-04\r\n] 2006.201.19:36:10.06#ibcon#*before write, iclass 2, count 2 2006.201.19:36:10.06#ibcon#enter sib2, iclass 2, count 2 2006.201.19:36:10.06#ibcon#flushed, iclass 2, count 2 2006.201.19:36:10.06#ibcon#about to write, iclass 2, count 2 2006.201.19:36:10.06#ibcon#wrote, iclass 2, count 2 2006.201.19:36:10.06#ibcon#about to read 3, iclass 2, count 2 2006.201.19:36:10.09#ibcon#read 3, iclass 2, count 2 2006.201.19:36:10.09#ibcon#about to read 4, iclass 2, count 2 2006.201.19:36:10.09#ibcon#read 4, iclass 2, count 2 2006.201.19:36:10.09#ibcon#about to read 5, iclass 2, count 2 2006.201.19:36:10.09#ibcon#read 5, iclass 2, count 2 2006.201.19:36:10.09#ibcon#about to read 6, iclass 2, count 2 2006.201.19:36:10.09#ibcon#read 6, iclass 2, count 2 2006.201.19:36:10.09#ibcon#end of sib2, iclass 2, count 2 2006.201.19:36:10.09#ibcon#*after write, iclass 2, count 2 2006.201.19:36:10.09#ibcon#*before return 0, iclass 2, count 2 2006.201.19:36:10.09#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:10.09#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:36:10.09#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.19:36:10.09#ibcon#ireg 7 cls_cnt 0 2006.201.19:36:10.09#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:10.21#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:10.21#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:10.21#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:36:10.21#ibcon#first serial, iclass 2, count 0 2006.201.19:36:10.21#ibcon#enter sib2, iclass 2, count 0 2006.201.19:36:10.21#ibcon#flushed, iclass 2, count 0 2006.201.19:36:10.21#ibcon#about to write, iclass 2, count 0 2006.201.19:36:10.21#ibcon#wrote, iclass 2, count 0 2006.201.19:36:10.21#ibcon#about to read 3, iclass 2, count 0 2006.201.19:36:10.23#ibcon#read 3, iclass 2, count 0 2006.201.19:36:10.23#ibcon#about to read 4, iclass 2, count 0 2006.201.19:36:10.23#ibcon#read 4, iclass 2, count 0 2006.201.19:36:10.23#ibcon#about to read 5, iclass 2, count 0 2006.201.19:36:10.23#ibcon#read 5, iclass 2, count 0 2006.201.19:36:10.23#ibcon#about to read 6, iclass 2, count 0 2006.201.19:36:10.23#ibcon#read 6, iclass 2, count 0 2006.201.19:36:10.23#ibcon#end of sib2, iclass 2, count 0 2006.201.19:36:10.23#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:36:10.23#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:36:10.23#ibcon#[27=USB\r\n] 2006.201.19:36:10.23#ibcon#*before write, iclass 2, count 0 2006.201.19:36:10.23#ibcon#enter sib2, iclass 2, count 0 2006.201.19:36:10.23#ibcon#flushed, iclass 2, count 0 2006.201.19:36:10.23#ibcon#about to write, iclass 2, count 0 2006.201.19:36:10.23#ibcon#wrote, iclass 2, count 0 2006.201.19:36:10.23#ibcon#about to read 3, iclass 2, count 0 2006.201.19:36:10.26#ibcon#read 3, iclass 2, count 0 2006.201.19:36:10.26#ibcon#about to read 4, iclass 2, count 0 2006.201.19:36:10.26#ibcon#read 4, iclass 2, count 0 2006.201.19:36:10.26#ibcon#about to read 5, iclass 2, count 0 2006.201.19:36:10.26#ibcon#read 5, iclass 2, count 0 2006.201.19:36:10.26#ibcon#about to read 6, iclass 2, count 0 2006.201.19:36:10.26#ibcon#read 6, iclass 2, count 0 2006.201.19:36:10.26#ibcon#end of sib2, iclass 2, count 0 2006.201.19:36:10.26#ibcon#*after write, iclass 2, count 0 2006.201.19:36:10.26#ibcon#*before return 0, iclass 2, count 0 2006.201.19:36:10.26#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:10.26#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:36:10.26#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:36:10.26#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:36:10.26$vck44/vabw=wide 2006.201.19:36:10.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.19:36:10.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.19:36:10.26#ibcon#ireg 8 cls_cnt 0 2006.201.19:36:10.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:10.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:10.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:10.26#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:36:10.26#ibcon#first serial, iclass 5, count 0 2006.201.19:36:10.26#ibcon#enter sib2, iclass 5, count 0 2006.201.19:36:10.26#ibcon#flushed, iclass 5, count 0 2006.201.19:36:10.26#ibcon#about to write, iclass 5, count 0 2006.201.19:36:10.26#ibcon#wrote, iclass 5, count 0 2006.201.19:36:10.26#ibcon#about to read 3, iclass 5, count 0 2006.201.19:36:10.28#ibcon#read 3, iclass 5, count 0 2006.201.19:36:10.28#ibcon#about to read 4, iclass 5, count 0 2006.201.19:36:10.28#ibcon#read 4, iclass 5, count 0 2006.201.19:36:10.28#ibcon#about to read 5, iclass 5, count 0 2006.201.19:36:10.28#ibcon#read 5, iclass 5, count 0 2006.201.19:36:10.28#ibcon#about to read 6, iclass 5, count 0 2006.201.19:36:10.28#ibcon#read 6, iclass 5, count 0 2006.201.19:36:10.28#ibcon#end of sib2, iclass 5, count 0 2006.201.19:36:10.28#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:36:10.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:36:10.28#ibcon#[25=BW32\r\n] 2006.201.19:36:10.28#ibcon#*before write, iclass 5, count 0 2006.201.19:36:10.28#ibcon#enter sib2, iclass 5, count 0 2006.201.19:36:10.28#ibcon#flushed, iclass 5, count 0 2006.201.19:36:10.28#ibcon#about to write, iclass 5, count 0 2006.201.19:36:10.28#ibcon#wrote, iclass 5, count 0 2006.201.19:36:10.28#ibcon#about to read 3, iclass 5, count 0 2006.201.19:36:10.31#ibcon#read 3, iclass 5, count 0 2006.201.19:36:10.31#ibcon#about to read 4, iclass 5, count 0 2006.201.19:36:10.31#ibcon#read 4, iclass 5, count 0 2006.201.19:36:10.31#ibcon#about to read 5, iclass 5, count 0 2006.201.19:36:10.31#ibcon#read 5, iclass 5, count 0 2006.201.19:36:10.31#ibcon#about to read 6, iclass 5, count 0 2006.201.19:36:10.31#ibcon#read 6, iclass 5, count 0 2006.201.19:36:10.31#ibcon#end of sib2, iclass 5, count 0 2006.201.19:36:10.31#ibcon#*after write, iclass 5, count 0 2006.201.19:36:10.31#ibcon#*before return 0, iclass 5, count 0 2006.201.19:36:10.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:10.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:36:10.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:36:10.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:36:10.31$vck44/vbbw=wide 2006.201.19:36:10.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.19:36:10.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.19:36:10.31#ibcon#ireg 8 cls_cnt 0 2006.201.19:36:10.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:36:10.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:36:10.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:36:10.38#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:36:10.38#ibcon#first serial, iclass 7, count 0 2006.201.19:36:10.38#ibcon#enter sib2, iclass 7, count 0 2006.201.19:36:10.38#ibcon#flushed, iclass 7, count 0 2006.201.19:36:10.38#ibcon#about to write, iclass 7, count 0 2006.201.19:36:10.38#ibcon#wrote, iclass 7, count 0 2006.201.19:36:10.38#ibcon#about to read 3, iclass 7, count 0 2006.201.19:36:10.40#ibcon#read 3, iclass 7, count 0 2006.201.19:36:10.40#ibcon#about to read 4, iclass 7, count 0 2006.201.19:36:10.40#ibcon#read 4, iclass 7, count 0 2006.201.19:36:10.40#ibcon#about to read 5, iclass 7, count 0 2006.201.19:36:10.40#ibcon#read 5, iclass 7, count 0 2006.201.19:36:10.40#ibcon#about to read 6, iclass 7, count 0 2006.201.19:36:10.40#ibcon#read 6, iclass 7, count 0 2006.201.19:36:10.40#ibcon#end of sib2, iclass 7, count 0 2006.201.19:36:10.40#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:36:10.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:36:10.40#ibcon#[27=BW32\r\n] 2006.201.19:36:10.40#ibcon#*before write, iclass 7, count 0 2006.201.19:36:10.40#ibcon#enter sib2, iclass 7, count 0 2006.201.19:36:10.40#ibcon#flushed, iclass 7, count 0 2006.201.19:36:10.40#ibcon#about to write, iclass 7, count 0 2006.201.19:36:10.40#ibcon#wrote, iclass 7, count 0 2006.201.19:36:10.40#ibcon#about to read 3, iclass 7, count 0 2006.201.19:36:10.43#ibcon#read 3, iclass 7, count 0 2006.201.19:36:10.43#ibcon#about to read 4, iclass 7, count 0 2006.201.19:36:10.43#ibcon#read 4, iclass 7, count 0 2006.201.19:36:10.43#ibcon#about to read 5, iclass 7, count 0 2006.201.19:36:10.43#ibcon#read 5, iclass 7, count 0 2006.201.19:36:10.43#ibcon#about to read 6, iclass 7, count 0 2006.201.19:36:10.43#ibcon#read 6, iclass 7, count 0 2006.201.19:36:10.43#ibcon#end of sib2, iclass 7, count 0 2006.201.19:36:10.43#ibcon#*after write, iclass 7, count 0 2006.201.19:36:10.43#ibcon#*before return 0, iclass 7, count 0 2006.201.19:36:10.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:36:10.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:36:10.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:36:10.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:36:10.43$setupk4/ifdk4 2006.201.19:36:10.43$ifdk4/lo= 2006.201.19:36:10.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:36:10.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:36:10.43$ifdk4/patch= 2006.201.19:36:10.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:36:10.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:36:10.43$setupk4/!*+20s 2006.201.19:36:13.92#abcon#<5=/03 1.8 3.4 20.441001002.3\r\n> 2006.201.19:36:13.94#abcon#{5=INTERFACE CLEAR} 2006.201.19:36:14.00#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:36:24.09#abcon#<5=/03 1.8 3.4 20.441001002.3\r\n> 2006.201.19:36:24.11#abcon#{5=INTERFACE CLEAR} 2006.201.19:36:24.17#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:36:24.89$setupk4/"tpicd 2006.201.19:36:24.89$setupk4/echo=off 2006.201.19:36:24.89$setupk4/xlog=off 2006.201.19:36:24.89:!2006.201.19:45:26 2006.201.19:36:32.13#trakl#Source acquired 2006.201.19:36:33.13#flagr#flagr/antenna,acquired 2006.201.19:45:26.00:preob 2006.201.19:45:26.14/onsource/TRACKING 2006.201.19:45:26.14:!2006.201.19:45:36 2006.201.19:45:36.00:"tape 2006.201.19:45:36.00:"st=record 2006.201.19:45:36.00:data_valid=on 2006.201.19:45:36.00:midob 2006.201.19:45:36.14/onsource/TRACKING 2006.201.19:45:36.14/wx/20.40,1002.2,100 2006.201.19:45:36.21/cable/+6.4772E-03 2006.201.19:45:37.30/va/01,08,usb,yes,42,45 2006.201.19:45:37.30/va/02,07,usb,yes,46,47 2006.201.19:45:37.30/va/03,08,usb,yes,41,43 2006.201.19:45:37.30/va/04,07,usb,yes,47,50 2006.201.19:45:37.30/va/05,04,usb,yes,42,43 2006.201.19:45:37.30/va/06,05,usb,yes,42,42 2006.201.19:45:37.30/va/07,05,usb,yes,41,43 2006.201.19:45:37.30/va/08,04,usb,yes,41,49 2006.201.19:45:37.53/valo/01,524.99,yes,locked 2006.201.19:45:37.53/valo/02,534.99,yes,locked 2006.201.19:45:37.53/valo/03,564.99,yes,locked 2006.201.19:45:37.53/valo/04,624.99,yes,locked 2006.201.19:45:37.53/valo/05,734.99,yes,locked 2006.201.19:45:37.53/valo/06,814.99,yes,locked 2006.201.19:45:37.53/valo/07,864.99,yes,locked 2006.201.19:45:37.53/valo/08,884.99,yes,locked 2006.201.19:45:38.62/vb/01,04,usb,yes,30,28 2006.201.19:45:38.62/vb/02,05,usb,yes,29,28 2006.201.19:45:38.62/vb/03,04,usb,yes,30,33 2006.201.19:45:38.62/vb/04,05,usb,yes,30,29 2006.201.19:45:38.62/vb/05,04,usb,yes,26,29 2006.201.19:45:38.62/vb/06,04,usb,yes,31,27 2006.201.19:45:38.62/vb/07,04,usb,yes,31,31 2006.201.19:45:38.62/vb/08,04,usb,yes,28,32 2006.201.19:45:38.85/vblo/01,629.99,yes,locked 2006.201.19:45:38.85/vblo/02,634.99,yes,locked 2006.201.19:45:38.85/vblo/03,649.99,yes,locked 2006.201.19:45:38.85/vblo/04,679.99,yes,locked 2006.201.19:45:38.85/vblo/05,709.99,yes,locked 2006.201.19:45:38.85/vblo/06,719.99,yes,locked 2006.201.19:45:38.85/vblo/07,734.99,yes,locked 2006.201.19:45:38.85/vblo/08,744.99,yes,locked 2006.201.19:45:39.00/vabw/8 2006.201.19:45:39.15/vbbw/8 2006.201.19:45:39.24/xfe/off,on,15.0 2006.201.19:45:39.62/ifatt/23,28,28,28 2006.201.19:45:40.05/fmout-gps/S +4.52E-07 2006.201.19:45:40.10:!2006.201.19:46:26 2006.201.19:46:26.00:data_valid=off 2006.201.19:46:26.00:"et 2006.201.19:46:26.00:!+3s 2006.201.19:46:29.02:"tape 2006.201.19:46:29.02:postob 2006.201.19:46:29.24/cable/+6.4771E-03 2006.201.19:46:29.24/wx/20.39,1002.2,100 2006.201.19:46:29.32/fmout-gps/S +4.52E-07 2006.201.19:46:29.32:scan_name=201-1949,jd0607,100 2006.201.19:46:29.32:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.201.19:46:30.14#flagr#flagr/antenna,new-source 2006.201.19:46:30.14:checkk5 2006.201.19:46:30.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:46:30.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:46:31.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:46:31.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:46:32.01/chk_obsdata//k5ts1/T2011945??a.dat file size is correct (nominal:200MB, actual:200MB). 2006.201.19:46:32.37/chk_obsdata//k5ts2/T2011945??b.dat file size is correct (nominal:200MB, actual:200MB). 2006.201.19:46:32.74/chk_obsdata//k5ts3/T2011945??c.dat file size is correct (nominal:200MB, actual:200MB). 2006.201.19:46:33.11/chk_obsdata//k5ts4/T2011945??d.dat file size is correct (nominal:200MB, actual:200MB). 2006.201.19:46:33.80/k5log//k5ts1_log_newline 2006.201.19:46:34.48/k5log//k5ts2_log_newline 2006.201.19:46:35.17/k5log//k5ts3_log_newline 2006.201.19:46:35.85/k5log//k5ts4_log_newline 2006.201.19:46:35.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:46:35.88:setupk4=1 2006.201.19:46:35.88$setupk4/echo=on 2006.201.19:46:35.88$setupk4/pcalon 2006.201.19:46:35.88$pcalon/"no phase cal control is implemented here 2006.201.19:46:35.88$setupk4/"tpicd=stop 2006.201.19:46:35.88$setupk4/"rec=synch_on 2006.201.19:46:35.88$setupk4/"rec_mode=128 2006.201.19:46:35.88$setupk4/!* 2006.201.19:46:35.88$setupk4/recpk4 2006.201.19:46:35.88$recpk4/recpatch= 2006.201.19:46:35.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:46:35.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:46:35.88$setupk4/vck44 2006.201.19:46:35.88$vck44/valo=1,524.99 2006.201.19:46:35.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.19:46:35.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.19:46:35.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:35.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:35.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:35.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:35.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:46:35.88#ibcon#first serial, iclass 10, count 0 2006.201.19:46:35.88#ibcon#enter sib2, iclass 10, count 0 2006.201.19:46:35.88#ibcon#flushed, iclass 10, count 0 2006.201.19:46:35.88#ibcon#about to write, iclass 10, count 0 2006.201.19:46:35.88#ibcon#wrote, iclass 10, count 0 2006.201.19:46:35.88#ibcon#about to read 3, iclass 10, count 0 2006.201.19:46:35.92#ibcon#read 3, iclass 10, count 0 2006.201.19:46:35.92#ibcon#about to read 4, iclass 10, count 0 2006.201.19:46:35.92#ibcon#read 4, iclass 10, count 0 2006.201.19:46:35.92#ibcon#about to read 5, iclass 10, count 0 2006.201.19:46:35.92#ibcon#read 5, iclass 10, count 0 2006.201.19:46:35.92#ibcon#about to read 6, iclass 10, count 0 2006.201.19:46:35.92#ibcon#read 6, iclass 10, count 0 2006.201.19:46:35.92#ibcon#end of sib2, iclass 10, count 0 2006.201.19:46:35.92#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:46:35.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:46:35.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:46:35.92#ibcon#*before write, iclass 10, count 0 2006.201.19:46:35.92#ibcon#enter sib2, iclass 10, count 0 2006.201.19:46:35.92#ibcon#flushed, iclass 10, count 0 2006.201.19:46:35.92#ibcon#about to write, iclass 10, count 0 2006.201.19:46:35.92#ibcon#wrote, iclass 10, count 0 2006.201.19:46:35.92#ibcon#about to read 3, iclass 10, count 0 2006.201.19:46:35.97#ibcon#read 3, iclass 10, count 0 2006.201.19:46:35.97#ibcon#about to read 4, iclass 10, count 0 2006.201.19:46:35.97#ibcon#read 4, iclass 10, count 0 2006.201.19:46:35.97#ibcon#about to read 5, iclass 10, count 0 2006.201.19:46:35.97#ibcon#read 5, iclass 10, count 0 2006.201.19:46:35.97#ibcon#about to read 6, iclass 10, count 0 2006.201.19:46:35.97#ibcon#read 6, iclass 10, count 0 2006.201.19:46:35.97#ibcon#end of sib2, iclass 10, count 0 2006.201.19:46:35.97#ibcon#*after write, iclass 10, count 0 2006.201.19:46:35.97#ibcon#*before return 0, iclass 10, count 0 2006.201.19:46:35.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:35.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:35.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:46:35.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:46:35.97$vck44/va=1,8 2006.201.19:46:35.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.19:46:35.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.19:46:35.97#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:35.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:35.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:35.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:35.97#ibcon#enter wrdev, iclass 12, count 2 2006.201.19:46:35.97#ibcon#first serial, iclass 12, count 2 2006.201.19:46:35.97#ibcon#enter sib2, iclass 12, count 2 2006.201.19:46:35.97#ibcon#flushed, iclass 12, count 2 2006.201.19:46:35.97#ibcon#about to write, iclass 12, count 2 2006.201.19:46:35.97#ibcon#wrote, iclass 12, count 2 2006.201.19:46:35.97#ibcon#about to read 3, iclass 12, count 2 2006.201.19:46:35.99#ibcon#read 3, iclass 12, count 2 2006.201.19:46:35.99#ibcon#about to read 4, iclass 12, count 2 2006.201.19:46:35.99#ibcon#read 4, iclass 12, count 2 2006.201.19:46:35.99#ibcon#about to read 5, iclass 12, count 2 2006.201.19:46:35.99#ibcon#read 5, iclass 12, count 2 2006.201.19:46:35.99#ibcon#about to read 6, iclass 12, count 2 2006.201.19:46:35.99#ibcon#read 6, iclass 12, count 2 2006.201.19:46:35.99#ibcon#end of sib2, iclass 12, count 2 2006.201.19:46:35.99#ibcon#*mode == 0, iclass 12, count 2 2006.201.19:46:35.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.19:46:35.99#ibcon#[25=AT01-08\r\n] 2006.201.19:46:35.99#ibcon#*before write, iclass 12, count 2 2006.201.19:46:35.99#ibcon#enter sib2, iclass 12, count 2 2006.201.19:46:35.99#ibcon#flushed, iclass 12, count 2 2006.201.19:46:35.99#ibcon#about to write, iclass 12, count 2 2006.201.19:46:35.99#ibcon#wrote, iclass 12, count 2 2006.201.19:46:35.99#ibcon#about to read 3, iclass 12, count 2 2006.201.19:46:36.02#ibcon#read 3, iclass 12, count 2 2006.201.19:46:36.02#ibcon#about to read 4, iclass 12, count 2 2006.201.19:46:36.02#ibcon#read 4, iclass 12, count 2 2006.201.19:46:36.02#ibcon#about to read 5, iclass 12, count 2 2006.201.19:46:36.02#ibcon#read 5, iclass 12, count 2 2006.201.19:46:36.02#ibcon#about to read 6, iclass 12, count 2 2006.201.19:46:36.02#ibcon#read 6, iclass 12, count 2 2006.201.19:46:36.02#ibcon#end of sib2, iclass 12, count 2 2006.201.19:46:36.02#ibcon#*after write, iclass 12, count 2 2006.201.19:46:36.02#ibcon#*before return 0, iclass 12, count 2 2006.201.19:46:36.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:36.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:36.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.19:46:36.02#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:36.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:36.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:36.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:36.14#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:46:36.14#ibcon#first serial, iclass 12, count 0 2006.201.19:46:36.14#ibcon#enter sib2, iclass 12, count 0 2006.201.19:46:36.14#ibcon#flushed, iclass 12, count 0 2006.201.19:46:36.14#ibcon#about to write, iclass 12, count 0 2006.201.19:46:36.14#ibcon#wrote, iclass 12, count 0 2006.201.19:46:36.14#ibcon#about to read 3, iclass 12, count 0 2006.201.19:46:36.16#ibcon#read 3, iclass 12, count 0 2006.201.19:46:36.16#ibcon#about to read 4, iclass 12, count 0 2006.201.19:46:36.16#ibcon#read 4, iclass 12, count 0 2006.201.19:46:36.16#ibcon#about to read 5, iclass 12, count 0 2006.201.19:46:36.16#ibcon#read 5, iclass 12, count 0 2006.201.19:46:36.16#ibcon#about to read 6, iclass 12, count 0 2006.201.19:46:36.16#ibcon#read 6, iclass 12, count 0 2006.201.19:46:36.16#ibcon#end of sib2, iclass 12, count 0 2006.201.19:46:36.16#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:46:36.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:46:36.16#ibcon#[25=USB\r\n] 2006.201.19:46:36.16#ibcon#*before write, iclass 12, count 0 2006.201.19:46:36.16#ibcon#enter sib2, iclass 12, count 0 2006.201.19:46:36.16#ibcon#flushed, iclass 12, count 0 2006.201.19:46:36.16#ibcon#about to write, iclass 12, count 0 2006.201.19:46:36.16#ibcon#wrote, iclass 12, count 0 2006.201.19:46:36.16#ibcon#about to read 3, iclass 12, count 0 2006.201.19:46:36.19#ibcon#read 3, iclass 12, count 0 2006.201.19:46:36.19#ibcon#about to read 4, iclass 12, count 0 2006.201.19:46:36.19#ibcon#read 4, iclass 12, count 0 2006.201.19:46:36.19#ibcon#about to read 5, iclass 12, count 0 2006.201.19:46:36.19#ibcon#read 5, iclass 12, count 0 2006.201.19:46:36.19#ibcon#about to read 6, iclass 12, count 0 2006.201.19:46:36.19#ibcon#read 6, iclass 12, count 0 2006.201.19:46:36.19#ibcon#end of sib2, iclass 12, count 0 2006.201.19:46:36.19#ibcon#*after write, iclass 12, count 0 2006.201.19:46:36.19#ibcon#*before return 0, iclass 12, count 0 2006.201.19:46:36.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:36.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:36.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:46:36.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:46:36.19$vck44/valo=2,534.99 2006.201.19:46:36.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.19:46:36.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.19:46:36.19#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:36.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:36.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:36.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:36.19#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:46:36.19#ibcon#first serial, iclass 14, count 0 2006.201.19:46:36.19#ibcon#enter sib2, iclass 14, count 0 2006.201.19:46:36.19#ibcon#flushed, iclass 14, count 0 2006.201.19:46:36.19#ibcon#about to write, iclass 14, count 0 2006.201.19:46:36.19#ibcon#wrote, iclass 14, count 0 2006.201.19:46:36.19#ibcon#about to read 3, iclass 14, count 0 2006.201.19:46:36.21#ibcon#read 3, iclass 14, count 0 2006.201.19:46:36.21#ibcon#about to read 4, iclass 14, count 0 2006.201.19:46:36.21#ibcon#read 4, iclass 14, count 0 2006.201.19:46:36.21#ibcon#about to read 5, iclass 14, count 0 2006.201.19:46:36.21#ibcon#read 5, iclass 14, count 0 2006.201.19:46:36.21#ibcon#about to read 6, iclass 14, count 0 2006.201.19:46:36.21#ibcon#read 6, iclass 14, count 0 2006.201.19:46:36.21#ibcon#end of sib2, iclass 14, count 0 2006.201.19:46:36.21#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:46:36.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:46:36.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:46:36.21#ibcon#*before write, iclass 14, count 0 2006.201.19:46:36.21#ibcon#enter sib2, iclass 14, count 0 2006.201.19:46:36.21#ibcon#flushed, iclass 14, count 0 2006.201.19:46:36.21#ibcon#about to write, iclass 14, count 0 2006.201.19:46:36.21#ibcon#wrote, iclass 14, count 0 2006.201.19:46:36.21#ibcon#about to read 3, iclass 14, count 0 2006.201.19:46:36.26#ibcon#read 3, iclass 14, count 0 2006.201.19:46:36.26#ibcon#about to read 4, iclass 14, count 0 2006.201.19:46:36.26#ibcon#read 4, iclass 14, count 0 2006.201.19:46:36.26#ibcon#about to read 5, iclass 14, count 0 2006.201.19:46:36.26#ibcon#read 5, iclass 14, count 0 2006.201.19:46:36.26#ibcon#about to read 6, iclass 14, count 0 2006.201.19:46:36.26#ibcon#read 6, iclass 14, count 0 2006.201.19:46:36.26#ibcon#end of sib2, iclass 14, count 0 2006.201.19:46:36.26#ibcon#*after write, iclass 14, count 0 2006.201.19:46:36.26#ibcon#*before return 0, iclass 14, count 0 2006.201.19:46:36.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:36.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:36.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:46:36.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:46:36.26$vck44/va=2,7 2006.201.19:46:36.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.19:46:36.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.19:46:36.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:36.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:36.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:36.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:36.31#ibcon#enter wrdev, iclass 16, count 2 2006.201.19:46:36.31#ibcon#first serial, iclass 16, count 2 2006.201.19:46:36.31#ibcon#enter sib2, iclass 16, count 2 2006.201.19:46:36.31#ibcon#flushed, iclass 16, count 2 2006.201.19:46:36.31#ibcon#about to write, iclass 16, count 2 2006.201.19:46:36.31#ibcon#wrote, iclass 16, count 2 2006.201.19:46:36.31#ibcon#about to read 3, iclass 16, count 2 2006.201.19:46:36.33#ibcon#read 3, iclass 16, count 2 2006.201.19:46:36.33#ibcon#about to read 4, iclass 16, count 2 2006.201.19:46:36.33#ibcon#read 4, iclass 16, count 2 2006.201.19:46:36.33#ibcon#about to read 5, iclass 16, count 2 2006.201.19:46:36.33#ibcon#read 5, iclass 16, count 2 2006.201.19:46:36.33#ibcon#about to read 6, iclass 16, count 2 2006.201.19:46:36.33#ibcon#read 6, iclass 16, count 2 2006.201.19:46:36.33#ibcon#end of sib2, iclass 16, count 2 2006.201.19:46:36.33#ibcon#*mode == 0, iclass 16, count 2 2006.201.19:46:36.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.19:46:36.33#ibcon#[25=AT02-07\r\n] 2006.201.19:46:36.33#ibcon#*before write, iclass 16, count 2 2006.201.19:46:36.33#ibcon#enter sib2, iclass 16, count 2 2006.201.19:46:36.33#ibcon#flushed, iclass 16, count 2 2006.201.19:46:36.33#ibcon#about to write, iclass 16, count 2 2006.201.19:46:36.33#ibcon#wrote, iclass 16, count 2 2006.201.19:46:36.33#ibcon#about to read 3, iclass 16, count 2 2006.201.19:46:36.36#ibcon#read 3, iclass 16, count 2 2006.201.19:46:36.36#ibcon#about to read 4, iclass 16, count 2 2006.201.19:46:36.36#ibcon#read 4, iclass 16, count 2 2006.201.19:46:36.36#ibcon#about to read 5, iclass 16, count 2 2006.201.19:46:36.36#ibcon#read 5, iclass 16, count 2 2006.201.19:46:36.36#ibcon#about to read 6, iclass 16, count 2 2006.201.19:46:36.36#ibcon#read 6, iclass 16, count 2 2006.201.19:46:36.36#ibcon#end of sib2, iclass 16, count 2 2006.201.19:46:36.36#ibcon#*after write, iclass 16, count 2 2006.201.19:46:36.36#ibcon#*before return 0, iclass 16, count 2 2006.201.19:46:36.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:36.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:36.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.19:46:36.36#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:36.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:36.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:36.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:36.48#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:46:36.48#ibcon#first serial, iclass 16, count 0 2006.201.19:46:36.48#ibcon#enter sib2, iclass 16, count 0 2006.201.19:46:36.48#ibcon#flushed, iclass 16, count 0 2006.201.19:46:36.48#ibcon#about to write, iclass 16, count 0 2006.201.19:46:36.48#ibcon#wrote, iclass 16, count 0 2006.201.19:46:36.48#ibcon#about to read 3, iclass 16, count 0 2006.201.19:46:36.50#ibcon#read 3, iclass 16, count 0 2006.201.19:46:36.50#ibcon#about to read 4, iclass 16, count 0 2006.201.19:46:36.50#ibcon#read 4, iclass 16, count 0 2006.201.19:46:36.50#ibcon#about to read 5, iclass 16, count 0 2006.201.19:46:36.50#ibcon#read 5, iclass 16, count 0 2006.201.19:46:36.50#ibcon#about to read 6, iclass 16, count 0 2006.201.19:46:36.50#ibcon#read 6, iclass 16, count 0 2006.201.19:46:36.50#ibcon#end of sib2, iclass 16, count 0 2006.201.19:46:36.50#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:46:36.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:46:36.50#ibcon#[25=USB\r\n] 2006.201.19:46:36.50#ibcon#*before write, iclass 16, count 0 2006.201.19:46:36.50#ibcon#enter sib2, iclass 16, count 0 2006.201.19:46:36.50#ibcon#flushed, iclass 16, count 0 2006.201.19:46:36.50#ibcon#about to write, iclass 16, count 0 2006.201.19:46:36.50#ibcon#wrote, iclass 16, count 0 2006.201.19:46:36.50#ibcon#about to read 3, iclass 16, count 0 2006.201.19:46:36.53#ibcon#read 3, iclass 16, count 0 2006.201.19:46:36.53#ibcon#about to read 4, iclass 16, count 0 2006.201.19:46:36.53#ibcon#read 4, iclass 16, count 0 2006.201.19:46:36.53#ibcon#about to read 5, iclass 16, count 0 2006.201.19:46:36.53#ibcon#read 5, iclass 16, count 0 2006.201.19:46:36.53#ibcon#about to read 6, iclass 16, count 0 2006.201.19:46:36.53#ibcon#read 6, iclass 16, count 0 2006.201.19:46:36.53#ibcon#end of sib2, iclass 16, count 0 2006.201.19:46:36.53#ibcon#*after write, iclass 16, count 0 2006.201.19:46:36.53#ibcon#*before return 0, iclass 16, count 0 2006.201.19:46:36.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:36.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:36.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:46:36.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:46:36.53$vck44/valo=3,564.99 2006.201.19:46:36.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.19:46:36.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.19:46:36.53#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:36.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:36.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:36.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:36.53#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:46:36.53#ibcon#first serial, iclass 18, count 0 2006.201.19:46:36.53#ibcon#enter sib2, iclass 18, count 0 2006.201.19:46:36.53#ibcon#flushed, iclass 18, count 0 2006.201.19:46:36.53#ibcon#about to write, iclass 18, count 0 2006.201.19:46:36.53#ibcon#wrote, iclass 18, count 0 2006.201.19:46:36.53#ibcon#about to read 3, iclass 18, count 0 2006.201.19:46:36.55#ibcon#read 3, iclass 18, count 0 2006.201.19:46:36.55#ibcon#about to read 4, iclass 18, count 0 2006.201.19:46:36.55#ibcon#read 4, iclass 18, count 0 2006.201.19:46:36.55#ibcon#about to read 5, iclass 18, count 0 2006.201.19:46:36.55#ibcon#read 5, iclass 18, count 0 2006.201.19:46:36.55#ibcon#about to read 6, iclass 18, count 0 2006.201.19:46:36.55#ibcon#read 6, iclass 18, count 0 2006.201.19:46:36.55#ibcon#end of sib2, iclass 18, count 0 2006.201.19:46:36.55#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:46:36.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:46:36.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:46:36.55#ibcon#*before write, iclass 18, count 0 2006.201.19:46:36.55#ibcon#enter sib2, iclass 18, count 0 2006.201.19:46:36.55#ibcon#flushed, iclass 18, count 0 2006.201.19:46:36.55#ibcon#about to write, iclass 18, count 0 2006.201.19:46:36.55#ibcon#wrote, iclass 18, count 0 2006.201.19:46:36.55#ibcon#about to read 3, iclass 18, count 0 2006.201.19:46:36.60#ibcon#read 3, iclass 18, count 0 2006.201.19:46:36.60#ibcon#about to read 4, iclass 18, count 0 2006.201.19:46:36.60#ibcon#read 4, iclass 18, count 0 2006.201.19:46:36.60#ibcon#about to read 5, iclass 18, count 0 2006.201.19:46:36.60#ibcon#read 5, iclass 18, count 0 2006.201.19:46:36.60#ibcon#about to read 6, iclass 18, count 0 2006.201.19:46:36.60#ibcon#read 6, iclass 18, count 0 2006.201.19:46:36.60#ibcon#end of sib2, iclass 18, count 0 2006.201.19:46:36.60#ibcon#*after write, iclass 18, count 0 2006.201.19:46:36.60#ibcon#*before return 0, iclass 18, count 0 2006.201.19:46:36.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:36.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:36.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:46:36.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:46:36.60$vck44/va=3,8 2006.201.19:46:36.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.19:46:36.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.19:46:36.60#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:36.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:36.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:36.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:36.65#ibcon#enter wrdev, iclass 20, count 2 2006.201.19:46:36.65#ibcon#first serial, iclass 20, count 2 2006.201.19:46:36.65#ibcon#enter sib2, iclass 20, count 2 2006.201.19:46:36.65#ibcon#flushed, iclass 20, count 2 2006.201.19:46:36.65#ibcon#about to write, iclass 20, count 2 2006.201.19:46:36.65#ibcon#wrote, iclass 20, count 2 2006.201.19:46:36.65#ibcon#about to read 3, iclass 20, count 2 2006.201.19:46:36.67#ibcon#read 3, iclass 20, count 2 2006.201.19:46:36.67#ibcon#about to read 4, iclass 20, count 2 2006.201.19:46:36.67#ibcon#read 4, iclass 20, count 2 2006.201.19:46:36.67#ibcon#about to read 5, iclass 20, count 2 2006.201.19:46:36.67#ibcon#read 5, iclass 20, count 2 2006.201.19:46:36.67#ibcon#about to read 6, iclass 20, count 2 2006.201.19:46:36.67#ibcon#read 6, iclass 20, count 2 2006.201.19:46:36.67#ibcon#end of sib2, iclass 20, count 2 2006.201.19:46:36.67#ibcon#*mode == 0, iclass 20, count 2 2006.201.19:46:36.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.19:46:36.67#ibcon#[25=AT03-08\r\n] 2006.201.19:46:36.67#ibcon#*before write, iclass 20, count 2 2006.201.19:46:36.67#ibcon#enter sib2, iclass 20, count 2 2006.201.19:46:36.67#ibcon#flushed, iclass 20, count 2 2006.201.19:46:36.67#ibcon#about to write, iclass 20, count 2 2006.201.19:46:36.67#ibcon#wrote, iclass 20, count 2 2006.201.19:46:36.67#ibcon#about to read 3, iclass 20, count 2 2006.201.19:46:36.70#ibcon#read 3, iclass 20, count 2 2006.201.19:46:36.70#ibcon#about to read 4, iclass 20, count 2 2006.201.19:46:36.70#ibcon#read 4, iclass 20, count 2 2006.201.19:46:36.70#ibcon#about to read 5, iclass 20, count 2 2006.201.19:46:36.70#ibcon#read 5, iclass 20, count 2 2006.201.19:46:36.70#ibcon#about to read 6, iclass 20, count 2 2006.201.19:46:36.70#ibcon#read 6, iclass 20, count 2 2006.201.19:46:36.70#ibcon#end of sib2, iclass 20, count 2 2006.201.19:46:36.70#ibcon#*after write, iclass 20, count 2 2006.201.19:46:36.70#ibcon#*before return 0, iclass 20, count 2 2006.201.19:46:36.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:36.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:36.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.19:46:36.70#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:36.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:36.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:36.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:36.82#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:46:36.82#ibcon#first serial, iclass 20, count 0 2006.201.19:46:36.82#ibcon#enter sib2, iclass 20, count 0 2006.201.19:46:36.82#ibcon#flushed, iclass 20, count 0 2006.201.19:46:36.82#ibcon#about to write, iclass 20, count 0 2006.201.19:46:36.82#ibcon#wrote, iclass 20, count 0 2006.201.19:46:36.82#ibcon#about to read 3, iclass 20, count 0 2006.201.19:46:36.84#ibcon#read 3, iclass 20, count 0 2006.201.19:46:36.84#ibcon#about to read 4, iclass 20, count 0 2006.201.19:46:36.84#ibcon#read 4, iclass 20, count 0 2006.201.19:46:36.84#ibcon#about to read 5, iclass 20, count 0 2006.201.19:46:36.84#ibcon#read 5, iclass 20, count 0 2006.201.19:46:36.84#ibcon#about to read 6, iclass 20, count 0 2006.201.19:46:36.84#ibcon#read 6, iclass 20, count 0 2006.201.19:46:36.84#ibcon#end of sib2, iclass 20, count 0 2006.201.19:46:36.84#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:46:36.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:46:36.84#ibcon#[25=USB\r\n] 2006.201.19:46:36.84#ibcon#*before write, iclass 20, count 0 2006.201.19:46:36.84#ibcon#enter sib2, iclass 20, count 0 2006.201.19:46:36.84#ibcon#flushed, iclass 20, count 0 2006.201.19:46:36.84#ibcon#about to write, iclass 20, count 0 2006.201.19:46:36.84#ibcon#wrote, iclass 20, count 0 2006.201.19:46:36.84#ibcon#about to read 3, iclass 20, count 0 2006.201.19:46:36.87#ibcon#read 3, iclass 20, count 0 2006.201.19:46:36.87#ibcon#about to read 4, iclass 20, count 0 2006.201.19:46:36.87#ibcon#read 4, iclass 20, count 0 2006.201.19:46:36.87#ibcon#about to read 5, iclass 20, count 0 2006.201.19:46:36.87#ibcon#read 5, iclass 20, count 0 2006.201.19:46:36.87#ibcon#about to read 6, iclass 20, count 0 2006.201.19:46:36.87#ibcon#read 6, iclass 20, count 0 2006.201.19:46:36.87#ibcon#end of sib2, iclass 20, count 0 2006.201.19:46:36.87#ibcon#*after write, iclass 20, count 0 2006.201.19:46:36.87#ibcon#*before return 0, iclass 20, count 0 2006.201.19:46:36.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:36.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:36.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:46:36.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:46:36.87$vck44/valo=4,624.99 2006.201.19:46:36.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.19:46:36.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.19:46:36.87#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:36.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:36.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:36.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:36.87#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:46:36.87#ibcon#first serial, iclass 22, count 0 2006.201.19:46:36.87#ibcon#enter sib2, iclass 22, count 0 2006.201.19:46:36.87#ibcon#flushed, iclass 22, count 0 2006.201.19:46:36.87#ibcon#about to write, iclass 22, count 0 2006.201.19:46:36.87#ibcon#wrote, iclass 22, count 0 2006.201.19:46:36.87#ibcon#about to read 3, iclass 22, count 0 2006.201.19:46:36.89#ibcon#read 3, iclass 22, count 0 2006.201.19:46:36.89#ibcon#about to read 4, iclass 22, count 0 2006.201.19:46:36.89#ibcon#read 4, iclass 22, count 0 2006.201.19:46:36.89#ibcon#about to read 5, iclass 22, count 0 2006.201.19:46:36.89#ibcon#read 5, iclass 22, count 0 2006.201.19:46:36.89#ibcon#about to read 6, iclass 22, count 0 2006.201.19:46:36.89#ibcon#read 6, iclass 22, count 0 2006.201.19:46:36.89#ibcon#end of sib2, iclass 22, count 0 2006.201.19:46:36.89#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:46:36.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:46:36.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:46:36.89#ibcon#*before write, iclass 22, count 0 2006.201.19:46:36.89#ibcon#enter sib2, iclass 22, count 0 2006.201.19:46:36.89#ibcon#flushed, iclass 22, count 0 2006.201.19:46:36.89#ibcon#about to write, iclass 22, count 0 2006.201.19:46:36.89#ibcon#wrote, iclass 22, count 0 2006.201.19:46:36.89#ibcon#about to read 3, iclass 22, count 0 2006.201.19:46:36.94#ibcon#read 3, iclass 22, count 0 2006.201.19:46:36.94#ibcon#about to read 4, iclass 22, count 0 2006.201.19:46:36.94#ibcon#read 4, iclass 22, count 0 2006.201.19:46:36.94#ibcon#about to read 5, iclass 22, count 0 2006.201.19:46:36.94#ibcon#read 5, iclass 22, count 0 2006.201.19:46:36.94#ibcon#about to read 6, iclass 22, count 0 2006.201.19:46:36.94#ibcon#read 6, iclass 22, count 0 2006.201.19:46:36.94#ibcon#end of sib2, iclass 22, count 0 2006.201.19:46:36.94#ibcon#*after write, iclass 22, count 0 2006.201.19:46:36.94#ibcon#*before return 0, iclass 22, count 0 2006.201.19:46:36.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:36.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:36.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:46:36.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:46:36.94$vck44/va=4,7 2006.201.19:46:36.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.19:46:36.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.19:46:36.94#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:36.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:36.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:36.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:36.99#ibcon#enter wrdev, iclass 24, count 2 2006.201.19:46:36.99#ibcon#first serial, iclass 24, count 2 2006.201.19:46:36.99#ibcon#enter sib2, iclass 24, count 2 2006.201.19:46:36.99#ibcon#flushed, iclass 24, count 2 2006.201.19:46:36.99#ibcon#about to write, iclass 24, count 2 2006.201.19:46:36.99#ibcon#wrote, iclass 24, count 2 2006.201.19:46:36.99#ibcon#about to read 3, iclass 24, count 2 2006.201.19:46:37.01#ibcon#read 3, iclass 24, count 2 2006.201.19:46:37.01#ibcon#about to read 4, iclass 24, count 2 2006.201.19:46:37.01#ibcon#read 4, iclass 24, count 2 2006.201.19:46:37.01#ibcon#about to read 5, iclass 24, count 2 2006.201.19:46:37.01#ibcon#read 5, iclass 24, count 2 2006.201.19:46:37.01#ibcon#about to read 6, iclass 24, count 2 2006.201.19:46:37.01#ibcon#read 6, iclass 24, count 2 2006.201.19:46:37.01#ibcon#end of sib2, iclass 24, count 2 2006.201.19:46:37.01#ibcon#*mode == 0, iclass 24, count 2 2006.201.19:46:37.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.19:46:37.01#ibcon#[25=AT04-07\r\n] 2006.201.19:46:37.01#ibcon#*before write, iclass 24, count 2 2006.201.19:46:37.01#ibcon#enter sib2, iclass 24, count 2 2006.201.19:46:37.01#ibcon#flushed, iclass 24, count 2 2006.201.19:46:37.01#ibcon#about to write, iclass 24, count 2 2006.201.19:46:37.01#ibcon#wrote, iclass 24, count 2 2006.201.19:46:37.01#ibcon#about to read 3, iclass 24, count 2 2006.201.19:46:37.04#ibcon#read 3, iclass 24, count 2 2006.201.19:46:37.04#ibcon#about to read 4, iclass 24, count 2 2006.201.19:46:37.04#ibcon#read 4, iclass 24, count 2 2006.201.19:46:37.04#ibcon#about to read 5, iclass 24, count 2 2006.201.19:46:37.04#ibcon#read 5, iclass 24, count 2 2006.201.19:46:37.04#ibcon#about to read 6, iclass 24, count 2 2006.201.19:46:37.04#ibcon#read 6, iclass 24, count 2 2006.201.19:46:37.04#ibcon#end of sib2, iclass 24, count 2 2006.201.19:46:37.04#ibcon#*after write, iclass 24, count 2 2006.201.19:46:37.04#ibcon#*before return 0, iclass 24, count 2 2006.201.19:46:37.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:37.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:37.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.19:46:37.04#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:37.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:37.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:37.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:37.16#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:46:37.16#ibcon#first serial, iclass 24, count 0 2006.201.19:46:37.16#ibcon#enter sib2, iclass 24, count 0 2006.201.19:46:37.16#ibcon#flushed, iclass 24, count 0 2006.201.19:46:37.16#ibcon#about to write, iclass 24, count 0 2006.201.19:46:37.16#ibcon#wrote, iclass 24, count 0 2006.201.19:46:37.16#ibcon#about to read 3, iclass 24, count 0 2006.201.19:46:37.18#ibcon#read 3, iclass 24, count 0 2006.201.19:46:37.18#ibcon#about to read 4, iclass 24, count 0 2006.201.19:46:37.18#ibcon#read 4, iclass 24, count 0 2006.201.19:46:37.18#ibcon#about to read 5, iclass 24, count 0 2006.201.19:46:37.18#ibcon#read 5, iclass 24, count 0 2006.201.19:46:37.18#ibcon#about to read 6, iclass 24, count 0 2006.201.19:46:37.18#ibcon#read 6, iclass 24, count 0 2006.201.19:46:37.18#ibcon#end of sib2, iclass 24, count 0 2006.201.19:46:37.18#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:46:37.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:46:37.18#ibcon#[25=USB\r\n] 2006.201.19:46:37.18#ibcon#*before write, iclass 24, count 0 2006.201.19:46:37.18#ibcon#enter sib2, iclass 24, count 0 2006.201.19:46:37.18#ibcon#flushed, iclass 24, count 0 2006.201.19:46:37.18#ibcon#about to write, iclass 24, count 0 2006.201.19:46:37.18#ibcon#wrote, iclass 24, count 0 2006.201.19:46:37.18#ibcon#about to read 3, iclass 24, count 0 2006.201.19:46:37.21#ibcon#read 3, iclass 24, count 0 2006.201.19:46:37.21#ibcon#about to read 4, iclass 24, count 0 2006.201.19:46:37.21#ibcon#read 4, iclass 24, count 0 2006.201.19:46:37.21#ibcon#about to read 5, iclass 24, count 0 2006.201.19:46:37.21#ibcon#read 5, iclass 24, count 0 2006.201.19:46:37.21#ibcon#about to read 6, iclass 24, count 0 2006.201.19:46:37.21#ibcon#read 6, iclass 24, count 0 2006.201.19:46:37.21#ibcon#end of sib2, iclass 24, count 0 2006.201.19:46:37.21#ibcon#*after write, iclass 24, count 0 2006.201.19:46:37.21#ibcon#*before return 0, iclass 24, count 0 2006.201.19:46:37.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:37.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:37.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:46:37.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:46:37.21$vck44/valo=5,734.99 2006.201.19:46:37.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.19:46:37.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.19:46:37.21#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:37.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:37.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:37.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:37.21#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:46:37.21#ibcon#first serial, iclass 26, count 0 2006.201.19:46:37.21#ibcon#enter sib2, iclass 26, count 0 2006.201.19:46:37.21#ibcon#flushed, iclass 26, count 0 2006.201.19:46:37.21#ibcon#about to write, iclass 26, count 0 2006.201.19:46:37.21#ibcon#wrote, iclass 26, count 0 2006.201.19:46:37.21#ibcon#about to read 3, iclass 26, count 0 2006.201.19:46:37.23#ibcon#read 3, iclass 26, count 0 2006.201.19:46:37.23#ibcon#about to read 4, iclass 26, count 0 2006.201.19:46:37.23#ibcon#read 4, iclass 26, count 0 2006.201.19:46:37.23#ibcon#about to read 5, iclass 26, count 0 2006.201.19:46:37.23#ibcon#read 5, iclass 26, count 0 2006.201.19:46:37.23#ibcon#about to read 6, iclass 26, count 0 2006.201.19:46:37.23#ibcon#read 6, iclass 26, count 0 2006.201.19:46:37.23#ibcon#end of sib2, iclass 26, count 0 2006.201.19:46:37.23#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:46:37.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:46:37.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:46:37.23#ibcon#*before write, iclass 26, count 0 2006.201.19:46:37.23#ibcon#enter sib2, iclass 26, count 0 2006.201.19:46:37.23#ibcon#flushed, iclass 26, count 0 2006.201.19:46:37.23#ibcon#about to write, iclass 26, count 0 2006.201.19:46:37.23#ibcon#wrote, iclass 26, count 0 2006.201.19:46:37.23#ibcon#about to read 3, iclass 26, count 0 2006.201.19:46:37.27#ibcon#read 3, iclass 26, count 0 2006.201.19:46:37.27#ibcon#about to read 4, iclass 26, count 0 2006.201.19:46:37.27#ibcon#read 4, iclass 26, count 0 2006.201.19:46:37.27#ibcon#about to read 5, iclass 26, count 0 2006.201.19:46:37.27#ibcon#read 5, iclass 26, count 0 2006.201.19:46:37.27#ibcon#about to read 6, iclass 26, count 0 2006.201.19:46:37.27#ibcon#read 6, iclass 26, count 0 2006.201.19:46:37.27#ibcon#end of sib2, iclass 26, count 0 2006.201.19:46:37.27#ibcon#*after write, iclass 26, count 0 2006.201.19:46:37.27#ibcon#*before return 0, iclass 26, count 0 2006.201.19:46:37.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:37.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:37.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:46:37.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:46:37.27$vck44/va=5,4 2006.201.19:46:37.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.19:46:37.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.19:46:37.27#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:37.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:37.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:37.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:37.33#ibcon#enter wrdev, iclass 28, count 2 2006.201.19:46:37.33#ibcon#first serial, iclass 28, count 2 2006.201.19:46:37.33#ibcon#enter sib2, iclass 28, count 2 2006.201.19:46:37.33#ibcon#flushed, iclass 28, count 2 2006.201.19:46:37.33#ibcon#about to write, iclass 28, count 2 2006.201.19:46:37.33#ibcon#wrote, iclass 28, count 2 2006.201.19:46:37.33#ibcon#about to read 3, iclass 28, count 2 2006.201.19:46:37.35#ibcon#read 3, iclass 28, count 2 2006.201.19:46:37.35#ibcon#about to read 4, iclass 28, count 2 2006.201.19:46:37.35#ibcon#read 4, iclass 28, count 2 2006.201.19:46:37.35#ibcon#about to read 5, iclass 28, count 2 2006.201.19:46:37.35#ibcon#read 5, iclass 28, count 2 2006.201.19:46:37.35#ibcon#about to read 6, iclass 28, count 2 2006.201.19:46:37.35#ibcon#read 6, iclass 28, count 2 2006.201.19:46:37.35#ibcon#end of sib2, iclass 28, count 2 2006.201.19:46:37.35#ibcon#*mode == 0, iclass 28, count 2 2006.201.19:46:37.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.19:46:37.35#ibcon#[25=AT05-04\r\n] 2006.201.19:46:37.35#ibcon#*before write, iclass 28, count 2 2006.201.19:46:37.35#ibcon#enter sib2, iclass 28, count 2 2006.201.19:46:37.35#ibcon#flushed, iclass 28, count 2 2006.201.19:46:37.35#ibcon#about to write, iclass 28, count 2 2006.201.19:46:37.35#ibcon#wrote, iclass 28, count 2 2006.201.19:46:37.35#ibcon#about to read 3, iclass 28, count 2 2006.201.19:46:37.38#ibcon#read 3, iclass 28, count 2 2006.201.19:46:37.38#ibcon#about to read 4, iclass 28, count 2 2006.201.19:46:37.38#ibcon#read 4, iclass 28, count 2 2006.201.19:46:37.38#ibcon#about to read 5, iclass 28, count 2 2006.201.19:46:37.38#ibcon#read 5, iclass 28, count 2 2006.201.19:46:37.38#ibcon#about to read 6, iclass 28, count 2 2006.201.19:46:37.38#ibcon#read 6, iclass 28, count 2 2006.201.19:46:37.38#ibcon#end of sib2, iclass 28, count 2 2006.201.19:46:37.38#ibcon#*after write, iclass 28, count 2 2006.201.19:46:37.38#ibcon#*before return 0, iclass 28, count 2 2006.201.19:46:37.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:37.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:37.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.19:46:37.38#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:37.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:37.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:37.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:37.50#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:46:37.50#ibcon#first serial, iclass 28, count 0 2006.201.19:46:37.50#ibcon#enter sib2, iclass 28, count 0 2006.201.19:46:37.50#ibcon#flushed, iclass 28, count 0 2006.201.19:46:37.50#ibcon#about to write, iclass 28, count 0 2006.201.19:46:37.50#ibcon#wrote, iclass 28, count 0 2006.201.19:46:37.50#ibcon#about to read 3, iclass 28, count 0 2006.201.19:46:37.52#ibcon#read 3, iclass 28, count 0 2006.201.19:46:37.52#ibcon#about to read 4, iclass 28, count 0 2006.201.19:46:37.52#ibcon#read 4, iclass 28, count 0 2006.201.19:46:37.52#ibcon#about to read 5, iclass 28, count 0 2006.201.19:46:37.52#ibcon#read 5, iclass 28, count 0 2006.201.19:46:37.52#ibcon#about to read 6, iclass 28, count 0 2006.201.19:46:37.52#ibcon#read 6, iclass 28, count 0 2006.201.19:46:37.52#ibcon#end of sib2, iclass 28, count 0 2006.201.19:46:37.52#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:46:37.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:46:37.52#ibcon#[25=USB\r\n] 2006.201.19:46:37.52#ibcon#*before write, iclass 28, count 0 2006.201.19:46:37.52#ibcon#enter sib2, iclass 28, count 0 2006.201.19:46:37.52#ibcon#flushed, iclass 28, count 0 2006.201.19:46:37.52#ibcon#about to write, iclass 28, count 0 2006.201.19:46:37.52#ibcon#wrote, iclass 28, count 0 2006.201.19:46:37.52#ibcon#about to read 3, iclass 28, count 0 2006.201.19:46:37.55#ibcon#read 3, iclass 28, count 0 2006.201.19:46:37.55#ibcon#about to read 4, iclass 28, count 0 2006.201.19:46:37.55#ibcon#read 4, iclass 28, count 0 2006.201.19:46:37.55#ibcon#about to read 5, iclass 28, count 0 2006.201.19:46:37.55#ibcon#read 5, iclass 28, count 0 2006.201.19:46:37.55#ibcon#about to read 6, iclass 28, count 0 2006.201.19:46:37.55#ibcon#read 6, iclass 28, count 0 2006.201.19:46:37.55#ibcon#end of sib2, iclass 28, count 0 2006.201.19:46:37.55#ibcon#*after write, iclass 28, count 0 2006.201.19:46:37.55#ibcon#*before return 0, iclass 28, count 0 2006.201.19:46:37.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:37.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:37.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:46:37.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:46:37.55$vck44/valo=6,814.99 2006.201.19:46:37.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.19:46:37.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.19:46:37.55#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:37.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:37.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:37.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:37.55#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:46:37.55#ibcon#first serial, iclass 30, count 0 2006.201.19:46:37.55#ibcon#enter sib2, iclass 30, count 0 2006.201.19:46:37.55#ibcon#flushed, iclass 30, count 0 2006.201.19:46:37.55#ibcon#about to write, iclass 30, count 0 2006.201.19:46:37.55#ibcon#wrote, iclass 30, count 0 2006.201.19:46:37.55#ibcon#about to read 3, iclass 30, count 0 2006.201.19:46:37.57#ibcon#read 3, iclass 30, count 0 2006.201.19:46:37.57#ibcon#about to read 4, iclass 30, count 0 2006.201.19:46:37.57#ibcon#read 4, iclass 30, count 0 2006.201.19:46:37.57#ibcon#about to read 5, iclass 30, count 0 2006.201.19:46:37.57#ibcon#read 5, iclass 30, count 0 2006.201.19:46:37.57#ibcon#about to read 6, iclass 30, count 0 2006.201.19:46:37.57#ibcon#read 6, iclass 30, count 0 2006.201.19:46:37.57#ibcon#end of sib2, iclass 30, count 0 2006.201.19:46:37.57#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:46:37.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:46:37.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:46:37.57#ibcon#*before write, iclass 30, count 0 2006.201.19:46:37.57#ibcon#enter sib2, iclass 30, count 0 2006.201.19:46:37.57#ibcon#flushed, iclass 30, count 0 2006.201.19:46:37.57#ibcon#about to write, iclass 30, count 0 2006.201.19:46:37.57#ibcon#wrote, iclass 30, count 0 2006.201.19:46:37.57#ibcon#about to read 3, iclass 30, count 0 2006.201.19:46:37.62#ibcon#read 3, iclass 30, count 0 2006.201.19:46:37.62#ibcon#about to read 4, iclass 30, count 0 2006.201.19:46:37.62#ibcon#read 4, iclass 30, count 0 2006.201.19:46:37.62#ibcon#about to read 5, iclass 30, count 0 2006.201.19:46:37.62#ibcon#read 5, iclass 30, count 0 2006.201.19:46:37.62#ibcon#about to read 6, iclass 30, count 0 2006.201.19:46:37.62#ibcon#read 6, iclass 30, count 0 2006.201.19:46:37.62#ibcon#end of sib2, iclass 30, count 0 2006.201.19:46:37.62#ibcon#*after write, iclass 30, count 0 2006.201.19:46:37.62#ibcon#*before return 0, iclass 30, count 0 2006.201.19:46:37.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:37.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:37.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:46:37.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:46:37.62$vck44/va=6,5 2006.201.19:46:37.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.19:46:37.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.19:46:37.62#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:37.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:37.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:37.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:37.67#ibcon#enter wrdev, iclass 32, count 2 2006.201.19:46:37.67#ibcon#first serial, iclass 32, count 2 2006.201.19:46:37.67#ibcon#enter sib2, iclass 32, count 2 2006.201.19:46:37.67#ibcon#flushed, iclass 32, count 2 2006.201.19:46:37.67#ibcon#about to write, iclass 32, count 2 2006.201.19:46:37.67#ibcon#wrote, iclass 32, count 2 2006.201.19:46:37.67#ibcon#about to read 3, iclass 32, count 2 2006.201.19:46:37.69#ibcon#read 3, iclass 32, count 2 2006.201.19:46:37.69#ibcon#about to read 4, iclass 32, count 2 2006.201.19:46:37.69#ibcon#read 4, iclass 32, count 2 2006.201.19:46:37.69#ibcon#about to read 5, iclass 32, count 2 2006.201.19:46:37.69#ibcon#read 5, iclass 32, count 2 2006.201.19:46:37.69#ibcon#about to read 6, iclass 32, count 2 2006.201.19:46:37.69#ibcon#read 6, iclass 32, count 2 2006.201.19:46:37.69#ibcon#end of sib2, iclass 32, count 2 2006.201.19:46:37.69#ibcon#*mode == 0, iclass 32, count 2 2006.201.19:46:37.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.19:46:37.69#ibcon#[25=AT06-05\r\n] 2006.201.19:46:37.69#ibcon#*before write, iclass 32, count 2 2006.201.19:46:37.69#ibcon#enter sib2, iclass 32, count 2 2006.201.19:46:37.69#ibcon#flushed, iclass 32, count 2 2006.201.19:46:37.69#ibcon#about to write, iclass 32, count 2 2006.201.19:46:37.69#ibcon#wrote, iclass 32, count 2 2006.201.19:46:37.69#ibcon#about to read 3, iclass 32, count 2 2006.201.19:46:37.72#ibcon#read 3, iclass 32, count 2 2006.201.19:46:37.72#ibcon#about to read 4, iclass 32, count 2 2006.201.19:46:37.72#ibcon#read 4, iclass 32, count 2 2006.201.19:46:37.72#ibcon#about to read 5, iclass 32, count 2 2006.201.19:46:37.72#ibcon#read 5, iclass 32, count 2 2006.201.19:46:37.72#ibcon#about to read 6, iclass 32, count 2 2006.201.19:46:37.72#ibcon#read 6, iclass 32, count 2 2006.201.19:46:37.72#ibcon#end of sib2, iclass 32, count 2 2006.201.19:46:37.72#ibcon#*after write, iclass 32, count 2 2006.201.19:46:37.72#ibcon#*before return 0, iclass 32, count 2 2006.201.19:46:37.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:37.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:37.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.19:46:37.72#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:37.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:37.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:37.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:37.84#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:46:37.84#ibcon#first serial, iclass 32, count 0 2006.201.19:46:37.84#ibcon#enter sib2, iclass 32, count 0 2006.201.19:46:37.84#ibcon#flushed, iclass 32, count 0 2006.201.19:46:37.84#ibcon#about to write, iclass 32, count 0 2006.201.19:46:37.84#ibcon#wrote, iclass 32, count 0 2006.201.19:46:37.84#ibcon#about to read 3, iclass 32, count 0 2006.201.19:46:37.86#ibcon#read 3, iclass 32, count 0 2006.201.19:46:37.86#ibcon#about to read 4, iclass 32, count 0 2006.201.19:46:37.86#ibcon#read 4, iclass 32, count 0 2006.201.19:46:37.86#ibcon#about to read 5, iclass 32, count 0 2006.201.19:46:37.86#ibcon#read 5, iclass 32, count 0 2006.201.19:46:37.86#ibcon#about to read 6, iclass 32, count 0 2006.201.19:46:37.86#ibcon#read 6, iclass 32, count 0 2006.201.19:46:37.86#ibcon#end of sib2, iclass 32, count 0 2006.201.19:46:37.86#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:46:37.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:46:37.86#ibcon#[25=USB\r\n] 2006.201.19:46:37.86#ibcon#*before write, iclass 32, count 0 2006.201.19:46:37.86#ibcon#enter sib2, iclass 32, count 0 2006.201.19:46:37.86#ibcon#flushed, iclass 32, count 0 2006.201.19:46:37.86#ibcon#about to write, iclass 32, count 0 2006.201.19:46:37.86#ibcon#wrote, iclass 32, count 0 2006.201.19:46:37.86#ibcon#about to read 3, iclass 32, count 0 2006.201.19:46:37.89#ibcon#read 3, iclass 32, count 0 2006.201.19:46:37.89#ibcon#about to read 4, iclass 32, count 0 2006.201.19:46:37.89#ibcon#read 4, iclass 32, count 0 2006.201.19:46:37.89#ibcon#about to read 5, iclass 32, count 0 2006.201.19:46:37.89#ibcon#read 5, iclass 32, count 0 2006.201.19:46:37.89#ibcon#about to read 6, iclass 32, count 0 2006.201.19:46:37.89#ibcon#read 6, iclass 32, count 0 2006.201.19:46:37.89#ibcon#end of sib2, iclass 32, count 0 2006.201.19:46:37.89#ibcon#*after write, iclass 32, count 0 2006.201.19:46:37.89#ibcon#*before return 0, iclass 32, count 0 2006.201.19:46:37.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:37.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:37.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:46:37.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:46:37.89$vck44/valo=7,864.99 2006.201.19:46:37.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.19:46:37.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.19:46:37.89#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:37.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:37.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:37.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:37.89#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:46:37.89#ibcon#first serial, iclass 34, count 0 2006.201.19:46:37.89#ibcon#enter sib2, iclass 34, count 0 2006.201.19:46:37.89#ibcon#flushed, iclass 34, count 0 2006.201.19:46:37.89#ibcon#about to write, iclass 34, count 0 2006.201.19:46:37.89#ibcon#wrote, iclass 34, count 0 2006.201.19:46:37.89#ibcon#about to read 3, iclass 34, count 0 2006.201.19:46:37.91#ibcon#read 3, iclass 34, count 0 2006.201.19:46:37.91#ibcon#about to read 4, iclass 34, count 0 2006.201.19:46:37.91#ibcon#read 4, iclass 34, count 0 2006.201.19:46:37.91#ibcon#about to read 5, iclass 34, count 0 2006.201.19:46:37.91#ibcon#read 5, iclass 34, count 0 2006.201.19:46:37.91#ibcon#about to read 6, iclass 34, count 0 2006.201.19:46:37.91#ibcon#read 6, iclass 34, count 0 2006.201.19:46:37.91#ibcon#end of sib2, iclass 34, count 0 2006.201.19:46:37.91#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:46:37.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:46:37.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:46:37.91#ibcon#*before write, iclass 34, count 0 2006.201.19:46:37.91#ibcon#enter sib2, iclass 34, count 0 2006.201.19:46:37.91#ibcon#flushed, iclass 34, count 0 2006.201.19:46:37.91#ibcon#about to write, iclass 34, count 0 2006.201.19:46:37.91#ibcon#wrote, iclass 34, count 0 2006.201.19:46:37.91#ibcon#about to read 3, iclass 34, count 0 2006.201.19:46:37.95#ibcon#read 3, iclass 34, count 0 2006.201.19:46:37.95#ibcon#about to read 4, iclass 34, count 0 2006.201.19:46:37.95#ibcon#read 4, iclass 34, count 0 2006.201.19:46:37.95#ibcon#about to read 5, iclass 34, count 0 2006.201.19:46:37.95#ibcon#read 5, iclass 34, count 0 2006.201.19:46:37.95#ibcon#about to read 6, iclass 34, count 0 2006.201.19:46:37.95#ibcon#read 6, iclass 34, count 0 2006.201.19:46:37.95#ibcon#end of sib2, iclass 34, count 0 2006.201.19:46:37.95#ibcon#*after write, iclass 34, count 0 2006.201.19:46:37.95#ibcon#*before return 0, iclass 34, count 0 2006.201.19:46:37.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:37.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:37.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:46:37.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:46:37.95$vck44/va=7,5 2006.201.19:46:37.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.19:46:37.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.19:46:37.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:37.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:38.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:38.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:38.01#ibcon#enter wrdev, iclass 36, count 2 2006.201.19:46:38.01#ibcon#first serial, iclass 36, count 2 2006.201.19:46:38.01#ibcon#enter sib2, iclass 36, count 2 2006.201.19:46:38.01#ibcon#flushed, iclass 36, count 2 2006.201.19:46:38.01#ibcon#about to write, iclass 36, count 2 2006.201.19:46:38.01#ibcon#wrote, iclass 36, count 2 2006.201.19:46:38.01#ibcon#about to read 3, iclass 36, count 2 2006.201.19:46:38.03#ibcon#read 3, iclass 36, count 2 2006.201.19:46:38.03#ibcon#about to read 4, iclass 36, count 2 2006.201.19:46:38.03#ibcon#read 4, iclass 36, count 2 2006.201.19:46:38.03#ibcon#about to read 5, iclass 36, count 2 2006.201.19:46:38.03#ibcon#read 5, iclass 36, count 2 2006.201.19:46:38.03#ibcon#about to read 6, iclass 36, count 2 2006.201.19:46:38.03#ibcon#read 6, iclass 36, count 2 2006.201.19:46:38.03#ibcon#end of sib2, iclass 36, count 2 2006.201.19:46:38.03#ibcon#*mode == 0, iclass 36, count 2 2006.201.19:46:38.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.19:46:38.03#ibcon#[25=AT07-05\r\n] 2006.201.19:46:38.03#ibcon#*before write, iclass 36, count 2 2006.201.19:46:38.03#ibcon#enter sib2, iclass 36, count 2 2006.201.19:46:38.03#ibcon#flushed, iclass 36, count 2 2006.201.19:46:38.03#ibcon#about to write, iclass 36, count 2 2006.201.19:46:38.03#ibcon#wrote, iclass 36, count 2 2006.201.19:46:38.03#ibcon#about to read 3, iclass 36, count 2 2006.201.19:46:38.06#ibcon#read 3, iclass 36, count 2 2006.201.19:46:38.06#ibcon#about to read 4, iclass 36, count 2 2006.201.19:46:38.06#ibcon#read 4, iclass 36, count 2 2006.201.19:46:38.06#ibcon#about to read 5, iclass 36, count 2 2006.201.19:46:38.06#ibcon#read 5, iclass 36, count 2 2006.201.19:46:38.06#ibcon#about to read 6, iclass 36, count 2 2006.201.19:46:38.06#ibcon#read 6, iclass 36, count 2 2006.201.19:46:38.06#ibcon#end of sib2, iclass 36, count 2 2006.201.19:46:38.06#ibcon#*after write, iclass 36, count 2 2006.201.19:46:38.06#ibcon#*before return 0, iclass 36, count 2 2006.201.19:46:38.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:38.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:38.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.19:46:38.06#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:38.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:38.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:38.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:38.18#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:46:38.18#ibcon#first serial, iclass 36, count 0 2006.201.19:46:38.18#ibcon#enter sib2, iclass 36, count 0 2006.201.19:46:38.18#ibcon#flushed, iclass 36, count 0 2006.201.19:46:38.18#ibcon#about to write, iclass 36, count 0 2006.201.19:46:38.18#ibcon#wrote, iclass 36, count 0 2006.201.19:46:38.18#ibcon#about to read 3, iclass 36, count 0 2006.201.19:46:38.20#ibcon#read 3, iclass 36, count 0 2006.201.19:46:38.20#ibcon#about to read 4, iclass 36, count 0 2006.201.19:46:38.20#ibcon#read 4, iclass 36, count 0 2006.201.19:46:38.20#ibcon#about to read 5, iclass 36, count 0 2006.201.19:46:38.20#ibcon#read 5, iclass 36, count 0 2006.201.19:46:38.20#ibcon#about to read 6, iclass 36, count 0 2006.201.19:46:38.20#ibcon#read 6, iclass 36, count 0 2006.201.19:46:38.20#ibcon#end of sib2, iclass 36, count 0 2006.201.19:46:38.20#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:46:38.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:46:38.20#ibcon#[25=USB\r\n] 2006.201.19:46:38.20#ibcon#*before write, iclass 36, count 0 2006.201.19:46:38.20#ibcon#enter sib2, iclass 36, count 0 2006.201.19:46:38.20#ibcon#flushed, iclass 36, count 0 2006.201.19:46:38.20#ibcon#about to write, iclass 36, count 0 2006.201.19:46:38.20#ibcon#wrote, iclass 36, count 0 2006.201.19:46:38.20#ibcon#about to read 3, iclass 36, count 0 2006.201.19:46:38.23#ibcon#read 3, iclass 36, count 0 2006.201.19:46:38.23#ibcon#about to read 4, iclass 36, count 0 2006.201.19:46:38.23#ibcon#read 4, iclass 36, count 0 2006.201.19:46:38.23#ibcon#about to read 5, iclass 36, count 0 2006.201.19:46:38.23#ibcon#read 5, iclass 36, count 0 2006.201.19:46:38.23#ibcon#about to read 6, iclass 36, count 0 2006.201.19:46:38.23#ibcon#read 6, iclass 36, count 0 2006.201.19:46:38.23#ibcon#end of sib2, iclass 36, count 0 2006.201.19:46:38.23#ibcon#*after write, iclass 36, count 0 2006.201.19:46:38.23#ibcon#*before return 0, iclass 36, count 0 2006.201.19:46:38.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:38.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:38.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:46:38.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:46:38.23$vck44/valo=8,884.99 2006.201.19:46:38.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.19:46:38.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.19:46:38.23#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:38.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:38.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:38.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:38.23#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:46:38.23#ibcon#first serial, iclass 38, count 0 2006.201.19:46:38.23#ibcon#enter sib2, iclass 38, count 0 2006.201.19:46:38.23#ibcon#flushed, iclass 38, count 0 2006.201.19:46:38.23#ibcon#about to write, iclass 38, count 0 2006.201.19:46:38.23#ibcon#wrote, iclass 38, count 0 2006.201.19:46:38.23#ibcon#about to read 3, iclass 38, count 0 2006.201.19:46:38.25#ibcon#read 3, iclass 38, count 0 2006.201.19:46:38.25#ibcon#about to read 4, iclass 38, count 0 2006.201.19:46:38.25#ibcon#read 4, iclass 38, count 0 2006.201.19:46:38.25#ibcon#about to read 5, iclass 38, count 0 2006.201.19:46:38.25#ibcon#read 5, iclass 38, count 0 2006.201.19:46:38.25#ibcon#about to read 6, iclass 38, count 0 2006.201.19:46:38.25#ibcon#read 6, iclass 38, count 0 2006.201.19:46:38.25#ibcon#end of sib2, iclass 38, count 0 2006.201.19:46:38.25#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:46:38.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:46:38.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:46:38.25#ibcon#*before write, iclass 38, count 0 2006.201.19:46:38.25#ibcon#enter sib2, iclass 38, count 0 2006.201.19:46:38.25#ibcon#flushed, iclass 38, count 0 2006.201.19:46:38.25#ibcon#about to write, iclass 38, count 0 2006.201.19:46:38.25#ibcon#wrote, iclass 38, count 0 2006.201.19:46:38.25#ibcon#about to read 3, iclass 38, count 0 2006.201.19:46:38.29#ibcon#read 3, iclass 38, count 0 2006.201.19:46:38.29#ibcon#about to read 4, iclass 38, count 0 2006.201.19:46:38.29#ibcon#read 4, iclass 38, count 0 2006.201.19:46:38.29#ibcon#about to read 5, iclass 38, count 0 2006.201.19:46:38.29#ibcon#read 5, iclass 38, count 0 2006.201.19:46:38.29#ibcon#about to read 6, iclass 38, count 0 2006.201.19:46:38.29#ibcon#read 6, iclass 38, count 0 2006.201.19:46:38.29#ibcon#end of sib2, iclass 38, count 0 2006.201.19:46:38.29#ibcon#*after write, iclass 38, count 0 2006.201.19:46:38.29#ibcon#*before return 0, iclass 38, count 0 2006.201.19:46:38.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:38.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:38.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:46:38.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:46:38.29$vck44/va=8,4 2006.201.19:46:38.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.19:46:38.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.19:46:38.29#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:38.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:46:38.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:46:38.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:46:38.35#ibcon#enter wrdev, iclass 40, count 2 2006.201.19:46:38.35#ibcon#first serial, iclass 40, count 2 2006.201.19:46:38.35#ibcon#enter sib2, iclass 40, count 2 2006.201.19:46:38.35#ibcon#flushed, iclass 40, count 2 2006.201.19:46:38.35#ibcon#about to write, iclass 40, count 2 2006.201.19:46:38.35#ibcon#wrote, iclass 40, count 2 2006.201.19:46:38.35#ibcon#about to read 3, iclass 40, count 2 2006.201.19:46:38.37#ibcon#read 3, iclass 40, count 2 2006.201.19:46:38.37#ibcon#about to read 4, iclass 40, count 2 2006.201.19:46:38.37#ibcon#read 4, iclass 40, count 2 2006.201.19:46:38.37#ibcon#about to read 5, iclass 40, count 2 2006.201.19:46:38.37#ibcon#read 5, iclass 40, count 2 2006.201.19:46:38.37#ibcon#about to read 6, iclass 40, count 2 2006.201.19:46:38.37#ibcon#read 6, iclass 40, count 2 2006.201.19:46:38.37#ibcon#end of sib2, iclass 40, count 2 2006.201.19:46:38.37#ibcon#*mode == 0, iclass 40, count 2 2006.201.19:46:38.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.19:46:38.37#ibcon#[25=AT08-04\r\n] 2006.201.19:46:38.37#ibcon#*before write, iclass 40, count 2 2006.201.19:46:38.37#ibcon#enter sib2, iclass 40, count 2 2006.201.19:46:38.37#ibcon#flushed, iclass 40, count 2 2006.201.19:46:38.37#ibcon#about to write, iclass 40, count 2 2006.201.19:46:38.37#ibcon#wrote, iclass 40, count 2 2006.201.19:46:38.37#ibcon#about to read 3, iclass 40, count 2 2006.201.19:46:38.40#ibcon#read 3, iclass 40, count 2 2006.201.19:46:38.40#ibcon#about to read 4, iclass 40, count 2 2006.201.19:46:38.40#ibcon#read 4, iclass 40, count 2 2006.201.19:46:38.40#ibcon#about to read 5, iclass 40, count 2 2006.201.19:46:38.40#ibcon#read 5, iclass 40, count 2 2006.201.19:46:38.40#ibcon#about to read 6, iclass 40, count 2 2006.201.19:46:38.40#ibcon#read 6, iclass 40, count 2 2006.201.19:46:38.40#ibcon#end of sib2, iclass 40, count 2 2006.201.19:46:38.40#ibcon#*after write, iclass 40, count 2 2006.201.19:46:38.40#ibcon#*before return 0, iclass 40, count 2 2006.201.19:46:38.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:46:38.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.19:46:38.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.19:46:38.40#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:38.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:46:38.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:46:38.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:46:38.52#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:46:38.52#ibcon#first serial, iclass 40, count 0 2006.201.19:46:38.52#ibcon#enter sib2, iclass 40, count 0 2006.201.19:46:38.52#ibcon#flushed, iclass 40, count 0 2006.201.19:46:38.52#ibcon#about to write, iclass 40, count 0 2006.201.19:46:38.52#ibcon#wrote, iclass 40, count 0 2006.201.19:46:38.52#ibcon#about to read 3, iclass 40, count 0 2006.201.19:46:38.54#ibcon#read 3, iclass 40, count 0 2006.201.19:46:38.54#ibcon#about to read 4, iclass 40, count 0 2006.201.19:46:38.54#ibcon#read 4, iclass 40, count 0 2006.201.19:46:38.54#ibcon#about to read 5, iclass 40, count 0 2006.201.19:46:38.54#ibcon#read 5, iclass 40, count 0 2006.201.19:46:38.54#ibcon#about to read 6, iclass 40, count 0 2006.201.19:46:38.54#ibcon#read 6, iclass 40, count 0 2006.201.19:46:38.54#ibcon#end of sib2, iclass 40, count 0 2006.201.19:46:38.54#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:46:38.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:46:38.54#ibcon#[25=USB\r\n] 2006.201.19:46:38.54#ibcon#*before write, iclass 40, count 0 2006.201.19:46:38.54#ibcon#enter sib2, iclass 40, count 0 2006.201.19:46:38.54#ibcon#flushed, iclass 40, count 0 2006.201.19:46:38.54#ibcon#about to write, iclass 40, count 0 2006.201.19:46:38.54#ibcon#wrote, iclass 40, count 0 2006.201.19:46:38.54#ibcon#about to read 3, iclass 40, count 0 2006.201.19:46:38.57#ibcon#read 3, iclass 40, count 0 2006.201.19:46:38.57#ibcon#about to read 4, iclass 40, count 0 2006.201.19:46:38.57#ibcon#read 4, iclass 40, count 0 2006.201.19:46:38.57#ibcon#about to read 5, iclass 40, count 0 2006.201.19:46:38.57#ibcon#read 5, iclass 40, count 0 2006.201.19:46:38.57#ibcon#about to read 6, iclass 40, count 0 2006.201.19:46:38.57#ibcon#read 6, iclass 40, count 0 2006.201.19:46:38.57#ibcon#end of sib2, iclass 40, count 0 2006.201.19:46:38.57#ibcon#*after write, iclass 40, count 0 2006.201.19:46:38.57#ibcon#*before return 0, iclass 40, count 0 2006.201.19:46:38.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:46:38.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.19:46:38.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:46:38.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:46:38.57$vck44/vblo=1,629.99 2006.201.19:46:38.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.19:46:38.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.19:46:38.57#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:38.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:46:38.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:46:38.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:46:38.57#ibcon#enter wrdev, iclass 4, count 0 2006.201.19:46:38.57#ibcon#first serial, iclass 4, count 0 2006.201.19:46:38.57#ibcon#enter sib2, iclass 4, count 0 2006.201.19:46:38.57#ibcon#flushed, iclass 4, count 0 2006.201.19:46:38.57#ibcon#about to write, iclass 4, count 0 2006.201.19:46:38.57#ibcon#wrote, iclass 4, count 0 2006.201.19:46:38.57#ibcon#about to read 3, iclass 4, count 0 2006.201.19:46:38.59#ibcon#read 3, iclass 4, count 0 2006.201.19:46:38.59#ibcon#about to read 4, iclass 4, count 0 2006.201.19:46:38.59#ibcon#read 4, iclass 4, count 0 2006.201.19:46:38.59#ibcon#about to read 5, iclass 4, count 0 2006.201.19:46:38.59#ibcon#read 5, iclass 4, count 0 2006.201.19:46:38.59#ibcon#about to read 6, iclass 4, count 0 2006.201.19:46:38.59#ibcon#read 6, iclass 4, count 0 2006.201.19:46:38.59#ibcon#end of sib2, iclass 4, count 0 2006.201.19:46:38.59#ibcon#*mode == 0, iclass 4, count 0 2006.201.19:46:38.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.19:46:38.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:46:38.59#ibcon#*before write, iclass 4, count 0 2006.201.19:46:38.59#ibcon#enter sib2, iclass 4, count 0 2006.201.19:46:38.59#ibcon#flushed, iclass 4, count 0 2006.201.19:46:38.59#ibcon#about to write, iclass 4, count 0 2006.201.19:46:38.59#ibcon#wrote, iclass 4, count 0 2006.201.19:46:38.59#ibcon#about to read 3, iclass 4, count 0 2006.201.19:46:38.63#ibcon#read 3, iclass 4, count 0 2006.201.19:46:38.63#ibcon#about to read 4, iclass 4, count 0 2006.201.19:46:38.63#ibcon#read 4, iclass 4, count 0 2006.201.19:46:38.63#ibcon#about to read 5, iclass 4, count 0 2006.201.19:46:38.63#ibcon#read 5, iclass 4, count 0 2006.201.19:46:38.63#ibcon#about to read 6, iclass 4, count 0 2006.201.19:46:38.63#ibcon#read 6, iclass 4, count 0 2006.201.19:46:38.63#ibcon#end of sib2, iclass 4, count 0 2006.201.19:46:38.63#ibcon#*after write, iclass 4, count 0 2006.201.19:46:38.63#ibcon#*before return 0, iclass 4, count 0 2006.201.19:46:38.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:46:38.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.19:46:38.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.19:46:38.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.19:46:38.63$vck44/vb=1,4 2006.201.19:46:38.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.19:46:38.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.19:46:38.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:38.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:46:38.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:46:38.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:46:38.63#ibcon#enter wrdev, iclass 6, count 2 2006.201.19:46:38.63#ibcon#first serial, iclass 6, count 2 2006.201.19:46:38.63#ibcon#enter sib2, iclass 6, count 2 2006.201.19:46:38.63#ibcon#flushed, iclass 6, count 2 2006.201.19:46:38.63#ibcon#about to write, iclass 6, count 2 2006.201.19:46:38.63#ibcon#wrote, iclass 6, count 2 2006.201.19:46:38.63#ibcon#about to read 3, iclass 6, count 2 2006.201.19:46:38.65#ibcon#read 3, iclass 6, count 2 2006.201.19:46:38.65#ibcon#about to read 4, iclass 6, count 2 2006.201.19:46:38.65#ibcon#read 4, iclass 6, count 2 2006.201.19:46:38.65#ibcon#about to read 5, iclass 6, count 2 2006.201.19:46:38.65#ibcon#read 5, iclass 6, count 2 2006.201.19:46:38.65#ibcon#about to read 6, iclass 6, count 2 2006.201.19:46:38.65#ibcon#read 6, iclass 6, count 2 2006.201.19:46:38.65#ibcon#end of sib2, iclass 6, count 2 2006.201.19:46:38.65#ibcon#*mode == 0, iclass 6, count 2 2006.201.19:46:38.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.19:46:38.65#ibcon#[27=AT01-04\r\n] 2006.201.19:46:38.65#ibcon#*before write, iclass 6, count 2 2006.201.19:46:38.65#ibcon#enter sib2, iclass 6, count 2 2006.201.19:46:38.65#ibcon#flushed, iclass 6, count 2 2006.201.19:46:38.65#ibcon#about to write, iclass 6, count 2 2006.201.19:46:38.65#ibcon#wrote, iclass 6, count 2 2006.201.19:46:38.65#ibcon#about to read 3, iclass 6, count 2 2006.201.19:46:38.68#ibcon#read 3, iclass 6, count 2 2006.201.19:46:38.68#ibcon#about to read 4, iclass 6, count 2 2006.201.19:46:38.68#ibcon#read 4, iclass 6, count 2 2006.201.19:46:38.68#ibcon#about to read 5, iclass 6, count 2 2006.201.19:46:38.68#ibcon#read 5, iclass 6, count 2 2006.201.19:46:38.68#ibcon#about to read 6, iclass 6, count 2 2006.201.19:46:38.68#ibcon#read 6, iclass 6, count 2 2006.201.19:46:38.68#ibcon#end of sib2, iclass 6, count 2 2006.201.19:46:38.68#ibcon#*after write, iclass 6, count 2 2006.201.19:46:38.68#ibcon#*before return 0, iclass 6, count 2 2006.201.19:46:38.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:46:38.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.19:46:38.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.19:46:38.68#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:38.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:46:38.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:46:38.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:46:38.80#ibcon#enter wrdev, iclass 6, count 0 2006.201.19:46:38.80#ibcon#first serial, iclass 6, count 0 2006.201.19:46:38.80#ibcon#enter sib2, iclass 6, count 0 2006.201.19:46:38.80#ibcon#flushed, iclass 6, count 0 2006.201.19:46:38.80#ibcon#about to write, iclass 6, count 0 2006.201.19:46:38.80#ibcon#wrote, iclass 6, count 0 2006.201.19:46:38.80#ibcon#about to read 3, iclass 6, count 0 2006.201.19:46:38.82#ibcon#read 3, iclass 6, count 0 2006.201.19:46:38.82#ibcon#about to read 4, iclass 6, count 0 2006.201.19:46:38.82#ibcon#read 4, iclass 6, count 0 2006.201.19:46:38.82#ibcon#about to read 5, iclass 6, count 0 2006.201.19:46:38.82#ibcon#read 5, iclass 6, count 0 2006.201.19:46:38.82#ibcon#about to read 6, iclass 6, count 0 2006.201.19:46:38.82#ibcon#read 6, iclass 6, count 0 2006.201.19:46:38.82#ibcon#end of sib2, iclass 6, count 0 2006.201.19:46:38.82#ibcon#*mode == 0, iclass 6, count 0 2006.201.19:46:38.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.19:46:38.82#ibcon#[27=USB\r\n] 2006.201.19:46:38.82#ibcon#*before write, iclass 6, count 0 2006.201.19:46:38.82#ibcon#enter sib2, iclass 6, count 0 2006.201.19:46:38.82#ibcon#flushed, iclass 6, count 0 2006.201.19:46:38.82#ibcon#about to write, iclass 6, count 0 2006.201.19:46:38.82#ibcon#wrote, iclass 6, count 0 2006.201.19:46:38.82#ibcon#about to read 3, iclass 6, count 0 2006.201.19:46:38.85#ibcon#read 3, iclass 6, count 0 2006.201.19:46:38.85#ibcon#about to read 4, iclass 6, count 0 2006.201.19:46:38.85#ibcon#read 4, iclass 6, count 0 2006.201.19:46:38.85#ibcon#about to read 5, iclass 6, count 0 2006.201.19:46:38.85#ibcon#read 5, iclass 6, count 0 2006.201.19:46:38.85#ibcon#about to read 6, iclass 6, count 0 2006.201.19:46:38.85#ibcon#read 6, iclass 6, count 0 2006.201.19:46:38.85#ibcon#end of sib2, iclass 6, count 0 2006.201.19:46:38.85#ibcon#*after write, iclass 6, count 0 2006.201.19:46:38.85#ibcon#*before return 0, iclass 6, count 0 2006.201.19:46:38.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:46:38.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.19:46:38.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.19:46:38.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.19:46:38.85$vck44/vblo=2,634.99 2006.201.19:46:38.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.19:46:38.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.19:46:38.85#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:38.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:38.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:38.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:38.85#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:46:38.85#ibcon#first serial, iclass 10, count 0 2006.201.19:46:38.85#ibcon#enter sib2, iclass 10, count 0 2006.201.19:46:38.85#ibcon#flushed, iclass 10, count 0 2006.201.19:46:38.85#ibcon#about to write, iclass 10, count 0 2006.201.19:46:38.85#ibcon#wrote, iclass 10, count 0 2006.201.19:46:38.85#ibcon#about to read 3, iclass 10, count 0 2006.201.19:46:38.87#ibcon#read 3, iclass 10, count 0 2006.201.19:46:38.87#ibcon#about to read 4, iclass 10, count 0 2006.201.19:46:38.87#ibcon#read 4, iclass 10, count 0 2006.201.19:46:38.87#ibcon#about to read 5, iclass 10, count 0 2006.201.19:46:38.87#ibcon#read 5, iclass 10, count 0 2006.201.19:46:38.87#ibcon#about to read 6, iclass 10, count 0 2006.201.19:46:38.87#ibcon#read 6, iclass 10, count 0 2006.201.19:46:38.87#ibcon#end of sib2, iclass 10, count 0 2006.201.19:46:38.87#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:46:38.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:46:38.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:46:38.87#ibcon#*before write, iclass 10, count 0 2006.201.19:46:38.87#ibcon#enter sib2, iclass 10, count 0 2006.201.19:46:38.87#ibcon#flushed, iclass 10, count 0 2006.201.19:46:38.87#ibcon#about to write, iclass 10, count 0 2006.201.19:46:38.87#ibcon#wrote, iclass 10, count 0 2006.201.19:46:38.87#ibcon#about to read 3, iclass 10, count 0 2006.201.19:46:38.91#ibcon#read 3, iclass 10, count 0 2006.201.19:46:38.91#ibcon#about to read 4, iclass 10, count 0 2006.201.19:46:38.91#ibcon#read 4, iclass 10, count 0 2006.201.19:46:38.91#ibcon#about to read 5, iclass 10, count 0 2006.201.19:46:38.91#ibcon#read 5, iclass 10, count 0 2006.201.19:46:38.91#ibcon#about to read 6, iclass 10, count 0 2006.201.19:46:38.91#ibcon#read 6, iclass 10, count 0 2006.201.19:46:38.91#ibcon#end of sib2, iclass 10, count 0 2006.201.19:46:38.91#ibcon#*after write, iclass 10, count 0 2006.201.19:46:38.91#ibcon#*before return 0, iclass 10, count 0 2006.201.19:46:38.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:38.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.19:46:38.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:46:38.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:46:38.91$vck44/vb=2,5 2006.201.19:46:38.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.19:46:38.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.19:46:38.91#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:38.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:38.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:38.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:38.97#ibcon#enter wrdev, iclass 12, count 2 2006.201.19:46:38.97#ibcon#first serial, iclass 12, count 2 2006.201.19:46:38.97#ibcon#enter sib2, iclass 12, count 2 2006.201.19:46:38.97#ibcon#flushed, iclass 12, count 2 2006.201.19:46:38.97#ibcon#about to write, iclass 12, count 2 2006.201.19:46:38.97#ibcon#wrote, iclass 12, count 2 2006.201.19:46:38.97#ibcon#about to read 3, iclass 12, count 2 2006.201.19:46:38.99#ibcon#read 3, iclass 12, count 2 2006.201.19:46:38.99#ibcon#about to read 4, iclass 12, count 2 2006.201.19:46:38.99#ibcon#read 4, iclass 12, count 2 2006.201.19:46:38.99#ibcon#about to read 5, iclass 12, count 2 2006.201.19:46:38.99#ibcon#read 5, iclass 12, count 2 2006.201.19:46:38.99#ibcon#about to read 6, iclass 12, count 2 2006.201.19:46:38.99#ibcon#read 6, iclass 12, count 2 2006.201.19:46:38.99#ibcon#end of sib2, iclass 12, count 2 2006.201.19:46:38.99#ibcon#*mode == 0, iclass 12, count 2 2006.201.19:46:38.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.19:46:38.99#ibcon#[27=AT02-05\r\n] 2006.201.19:46:38.99#ibcon#*before write, iclass 12, count 2 2006.201.19:46:38.99#ibcon#enter sib2, iclass 12, count 2 2006.201.19:46:38.99#ibcon#flushed, iclass 12, count 2 2006.201.19:46:38.99#ibcon#about to write, iclass 12, count 2 2006.201.19:46:38.99#ibcon#wrote, iclass 12, count 2 2006.201.19:46:38.99#ibcon#about to read 3, iclass 12, count 2 2006.201.19:46:39.02#ibcon#read 3, iclass 12, count 2 2006.201.19:46:39.02#ibcon#about to read 4, iclass 12, count 2 2006.201.19:46:39.02#ibcon#read 4, iclass 12, count 2 2006.201.19:46:39.02#ibcon#about to read 5, iclass 12, count 2 2006.201.19:46:39.02#ibcon#read 5, iclass 12, count 2 2006.201.19:46:39.02#ibcon#about to read 6, iclass 12, count 2 2006.201.19:46:39.02#ibcon#read 6, iclass 12, count 2 2006.201.19:46:39.02#ibcon#end of sib2, iclass 12, count 2 2006.201.19:46:39.02#ibcon#*after write, iclass 12, count 2 2006.201.19:46:39.02#ibcon#*before return 0, iclass 12, count 2 2006.201.19:46:39.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:39.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.19:46:39.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.19:46:39.02#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:39.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:39.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:39.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:39.14#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:46:39.14#ibcon#first serial, iclass 12, count 0 2006.201.19:46:39.14#ibcon#enter sib2, iclass 12, count 0 2006.201.19:46:39.14#ibcon#flushed, iclass 12, count 0 2006.201.19:46:39.14#ibcon#about to write, iclass 12, count 0 2006.201.19:46:39.14#ibcon#wrote, iclass 12, count 0 2006.201.19:46:39.14#ibcon#about to read 3, iclass 12, count 0 2006.201.19:46:39.16#ibcon#read 3, iclass 12, count 0 2006.201.19:46:39.16#ibcon#about to read 4, iclass 12, count 0 2006.201.19:46:39.16#ibcon#read 4, iclass 12, count 0 2006.201.19:46:39.16#ibcon#about to read 5, iclass 12, count 0 2006.201.19:46:39.16#ibcon#read 5, iclass 12, count 0 2006.201.19:46:39.16#ibcon#about to read 6, iclass 12, count 0 2006.201.19:46:39.16#ibcon#read 6, iclass 12, count 0 2006.201.19:46:39.16#ibcon#end of sib2, iclass 12, count 0 2006.201.19:46:39.16#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:46:39.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:46:39.16#ibcon#[27=USB\r\n] 2006.201.19:46:39.16#ibcon#*before write, iclass 12, count 0 2006.201.19:46:39.16#ibcon#enter sib2, iclass 12, count 0 2006.201.19:46:39.16#ibcon#flushed, iclass 12, count 0 2006.201.19:46:39.16#ibcon#about to write, iclass 12, count 0 2006.201.19:46:39.16#ibcon#wrote, iclass 12, count 0 2006.201.19:46:39.16#ibcon#about to read 3, iclass 12, count 0 2006.201.19:46:39.19#ibcon#read 3, iclass 12, count 0 2006.201.19:46:39.19#ibcon#about to read 4, iclass 12, count 0 2006.201.19:46:39.19#ibcon#read 4, iclass 12, count 0 2006.201.19:46:39.19#ibcon#about to read 5, iclass 12, count 0 2006.201.19:46:39.19#ibcon#read 5, iclass 12, count 0 2006.201.19:46:39.19#ibcon#about to read 6, iclass 12, count 0 2006.201.19:46:39.19#ibcon#read 6, iclass 12, count 0 2006.201.19:46:39.19#ibcon#end of sib2, iclass 12, count 0 2006.201.19:46:39.19#ibcon#*after write, iclass 12, count 0 2006.201.19:46:39.19#ibcon#*before return 0, iclass 12, count 0 2006.201.19:46:39.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:39.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.19:46:39.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:46:39.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:46:39.19$vck44/vblo=3,649.99 2006.201.19:46:39.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.19:46:39.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.19:46:39.19#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:39.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:39.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:39.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:39.19#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:46:39.19#ibcon#first serial, iclass 14, count 0 2006.201.19:46:39.19#ibcon#enter sib2, iclass 14, count 0 2006.201.19:46:39.19#ibcon#flushed, iclass 14, count 0 2006.201.19:46:39.19#ibcon#about to write, iclass 14, count 0 2006.201.19:46:39.19#ibcon#wrote, iclass 14, count 0 2006.201.19:46:39.19#ibcon#about to read 3, iclass 14, count 0 2006.201.19:46:39.21#ibcon#read 3, iclass 14, count 0 2006.201.19:46:39.21#ibcon#about to read 4, iclass 14, count 0 2006.201.19:46:39.21#ibcon#read 4, iclass 14, count 0 2006.201.19:46:39.21#ibcon#about to read 5, iclass 14, count 0 2006.201.19:46:39.21#ibcon#read 5, iclass 14, count 0 2006.201.19:46:39.21#ibcon#about to read 6, iclass 14, count 0 2006.201.19:46:39.21#ibcon#read 6, iclass 14, count 0 2006.201.19:46:39.21#ibcon#end of sib2, iclass 14, count 0 2006.201.19:46:39.21#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:46:39.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:46:39.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:46:39.21#ibcon#*before write, iclass 14, count 0 2006.201.19:46:39.21#ibcon#enter sib2, iclass 14, count 0 2006.201.19:46:39.21#ibcon#flushed, iclass 14, count 0 2006.201.19:46:39.21#ibcon#about to write, iclass 14, count 0 2006.201.19:46:39.21#ibcon#wrote, iclass 14, count 0 2006.201.19:46:39.21#ibcon#about to read 3, iclass 14, count 0 2006.201.19:46:39.25#ibcon#read 3, iclass 14, count 0 2006.201.19:46:39.25#ibcon#about to read 4, iclass 14, count 0 2006.201.19:46:39.25#ibcon#read 4, iclass 14, count 0 2006.201.19:46:39.25#ibcon#about to read 5, iclass 14, count 0 2006.201.19:46:39.25#ibcon#read 5, iclass 14, count 0 2006.201.19:46:39.25#ibcon#about to read 6, iclass 14, count 0 2006.201.19:46:39.25#ibcon#read 6, iclass 14, count 0 2006.201.19:46:39.25#ibcon#end of sib2, iclass 14, count 0 2006.201.19:46:39.25#ibcon#*after write, iclass 14, count 0 2006.201.19:46:39.25#ibcon#*before return 0, iclass 14, count 0 2006.201.19:46:39.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:39.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:46:39.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:46:39.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:46:39.25$vck44/vb=3,4 2006.201.19:46:39.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.19:46:39.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.19:46:39.25#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:39.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:39.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:39.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:39.31#ibcon#enter wrdev, iclass 16, count 2 2006.201.19:46:39.31#ibcon#first serial, iclass 16, count 2 2006.201.19:46:39.31#ibcon#enter sib2, iclass 16, count 2 2006.201.19:46:39.31#ibcon#flushed, iclass 16, count 2 2006.201.19:46:39.31#ibcon#about to write, iclass 16, count 2 2006.201.19:46:39.31#ibcon#wrote, iclass 16, count 2 2006.201.19:46:39.31#ibcon#about to read 3, iclass 16, count 2 2006.201.19:46:39.33#ibcon#read 3, iclass 16, count 2 2006.201.19:46:39.33#ibcon#about to read 4, iclass 16, count 2 2006.201.19:46:39.33#ibcon#read 4, iclass 16, count 2 2006.201.19:46:39.33#ibcon#about to read 5, iclass 16, count 2 2006.201.19:46:39.33#ibcon#read 5, iclass 16, count 2 2006.201.19:46:39.33#ibcon#about to read 6, iclass 16, count 2 2006.201.19:46:39.33#ibcon#read 6, iclass 16, count 2 2006.201.19:46:39.33#ibcon#end of sib2, iclass 16, count 2 2006.201.19:46:39.33#ibcon#*mode == 0, iclass 16, count 2 2006.201.19:46:39.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.19:46:39.33#ibcon#[27=AT03-04\r\n] 2006.201.19:46:39.33#ibcon#*before write, iclass 16, count 2 2006.201.19:46:39.33#ibcon#enter sib2, iclass 16, count 2 2006.201.19:46:39.33#ibcon#flushed, iclass 16, count 2 2006.201.19:46:39.33#ibcon#about to write, iclass 16, count 2 2006.201.19:46:39.33#ibcon#wrote, iclass 16, count 2 2006.201.19:46:39.33#ibcon#about to read 3, iclass 16, count 2 2006.201.19:46:39.36#ibcon#read 3, iclass 16, count 2 2006.201.19:46:39.36#ibcon#about to read 4, iclass 16, count 2 2006.201.19:46:39.36#ibcon#read 4, iclass 16, count 2 2006.201.19:46:39.36#ibcon#about to read 5, iclass 16, count 2 2006.201.19:46:39.36#ibcon#read 5, iclass 16, count 2 2006.201.19:46:39.36#ibcon#about to read 6, iclass 16, count 2 2006.201.19:46:39.36#ibcon#read 6, iclass 16, count 2 2006.201.19:46:39.36#ibcon#end of sib2, iclass 16, count 2 2006.201.19:46:39.36#ibcon#*after write, iclass 16, count 2 2006.201.19:46:39.36#ibcon#*before return 0, iclass 16, count 2 2006.201.19:46:39.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:39.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.19:46:39.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.19:46:39.36#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:39.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:39.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:39.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:39.48#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:46:39.48#ibcon#first serial, iclass 16, count 0 2006.201.19:46:39.48#ibcon#enter sib2, iclass 16, count 0 2006.201.19:46:39.48#ibcon#flushed, iclass 16, count 0 2006.201.19:46:39.48#ibcon#about to write, iclass 16, count 0 2006.201.19:46:39.48#ibcon#wrote, iclass 16, count 0 2006.201.19:46:39.48#ibcon#about to read 3, iclass 16, count 0 2006.201.19:46:39.50#ibcon#read 3, iclass 16, count 0 2006.201.19:46:39.50#ibcon#about to read 4, iclass 16, count 0 2006.201.19:46:39.50#ibcon#read 4, iclass 16, count 0 2006.201.19:46:39.50#ibcon#about to read 5, iclass 16, count 0 2006.201.19:46:39.50#ibcon#read 5, iclass 16, count 0 2006.201.19:46:39.50#ibcon#about to read 6, iclass 16, count 0 2006.201.19:46:39.50#ibcon#read 6, iclass 16, count 0 2006.201.19:46:39.50#ibcon#end of sib2, iclass 16, count 0 2006.201.19:46:39.50#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:46:39.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:46:39.50#ibcon#[27=USB\r\n] 2006.201.19:46:39.50#ibcon#*before write, iclass 16, count 0 2006.201.19:46:39.50#ibcon#enter sib2, iclass 16, count 0 2006.201.19:46:39.50#ibcon#flushed, iclass 16, count 0 2006.201.19:46:39.50#ibcon#about to write, iclass 16, count 0 2006.201.19:46:39.50#ibcon#wrote, iclass 16, count 0 2006.201.19:46:39.50#ibcon#about to read 3, iclass 16, count 0 2006.201.19:46:39.53#ibcon#read 3, iclass 16, count 0 2006.201.19:46:39.53#ibcon#about to read 4, iclass 16, count 0 2006.201.19:46:39.53#ibcon#read 4, iclass 16, count 0 2006.201.19:46:39.53#ibcon#about to read 5, iclass 16, count 0 2006.201.19:46:39.53#ibcon#read 5, iclass 16, count 0 2006.201.19:46:39.53#ibcon#about to read 6, iclass 16, count 0 2006.201.19:46:39.53#ibcon#read 6, iclass 16, count 0 2006.201.19:46:39.53#ibcon#end of sib2, iclass 16, count 0 2006.201.19:46:39.53#ibcon#*after write, iclass 16, count 0 2006.201.19:46:39.53#ibcon#*before return 0, iclass 16, count 0 2006.201.19:46:39.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:39.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.19:46:39.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:46:39.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:46:39.53$vck44/vblo=4,679.99 2006.201.19:46:39.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.19:46:39.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.19:46:39.53#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:39.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:39.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:39.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:39.53#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:46:39.53#ibcon#first serial, iclass 18, count 0 2006.201.19:46:39.53#ibcon#enter sib2, iclass 18, count 0 2006.201.19:46:39.53#ibcon#flushed, iclass 18, count 0 2006.201.19:46:39.53#ibcon#about to write, iclass 18, count 0 2006.201.19:46:39.53#ibcon#wrote, iclass 18, count 0 2006.201.19:46:39.53#ibcon#about to read 3, iclass 18, count 0 2006.201.19:46:39.55#ibcon#read 3, iclass 18, count 0 2006.201.19:46:39.55#ibcon#about to read 4, iclass 18, count 0 2006.201.19:46:39.55#ibcon#read 4, iclass 18, count 0 2006.201.19:46:39.55#ibcon#about to read 5, iclass 18, count 0 2006.201.19:46:39.55#ibcon#read 5, iclass 18, count 0 2006.201.19:46:39.55#ibcon#about to read 6, iclass 18, count 0 2006.201.19:46:39.55#ibcon#read 6, iclass 18, count 0 2006.201.19:46:39.55#ibcon#end of sib2, iclass 18, count 0 2006.201.19:46:39.55#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:46:39.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:46:39.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:46:39.55#ibcon#*before write, iclass 18, count 0 2006.201.19:46:39.55#ibcon#enter sib2, iclass 18, count 0 2006.201.19:46:39.55#ibcon#flushed, iclass 18, count 0 2006.201.19:46:39.55#ibcon#about to write, iclass 18, count 0 2006.201.19:46:39.55#ibcon#wrote, iclass 18, count 0 2006.201.19:46:39.55#ibcon#about to read 3, iclass 18, count 0 2006.201.19:46:39.60#ibcon#read 3, iclass 18, count 0 2006.201.19:46:39.60#ibcon#about to read 4, iclass 18, count 0 2006.201.19:46:39.60#ibcon#read 4, iclass 18, count 0 2006.201.19:46:39.60#ibcon#about to read 5, iclass 18, count 0 2006.201.19:46:39.60#ibcon#read 5, iclass 18, count 0 2006.201.19:46:39.60#ibcon#about to read 6, iclass 18, count 0 2006.201.19:46:39.60#ibcon#read 6, iclass 18, count 0 2006.201.19:46:39.60#ibcon#end of sib2, iclass 18, count 0 2006.201.19:46:39.60#ibcon#*after write, iclass 18, count 0 2006.201.19:46:39.60#ibcon#*before return 0, iclass 18, count 0 2006.201.19:46:39.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:39.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.19:46:39.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:46:39.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:46:39.60$vck44/vb=4,5 2006.201.19:46:39.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.19:46:39.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.19:46:39.60#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:39.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:39.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:39.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:39.65#ibcon#enter wrdev, iclass 20, count 2 2006.201.19:46:39.65#ibcon#first serial, iclass 20, count 2 2006.201.19:46:39.65#ibcon#enter sib2, iclass 20, count 2 2006.201.19:46:39.65#ibcon#flushed, iclass 20, count 2 2006.201.19:46:39.65#ibcon#about to write, iclass 20, count 2 2006.201.19:46:39.65#ibcon#wrote, iclass 20, count 2 2006.201.19:46:39.65#ibcon#about to read 3, iclass 20, count 2 2006.201.19:46:39.67#ibcon#read 3, iclass 20, count 2 2006.201.19:46:39.67#ibcon#about to read 4, iclass 20, count 2 2006.201.19:46:39.67#ibcon#read 4, iclass 20, count 2 2006.201.19:46:39.67#ibcon#about to read 5, iclass 20, count 2 2006.201.19:46:39.67#ibcon#read 5, iclass 20, count 2 2006.201.19:46:39.67#ibcon#about to read 6, iclass 20, count 2 2006.201.19:46:39.67#ibcon#read 6, iclass 20, count 2 2006.201.19:46:39.67#ibcon#end of sib2, iclass 20, count 2 2006.201.19:46:39.67#ibcon#*mode == 0, iclass 20, count 2 2006.201.19:46:39.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.19:46:39.67#ibcon#[27=AT04-05\r\n] 2006.201.19:46:39.67#ibcon#*before write, iclass 20, count 2 2006.201.19:46:39.67#ibcon#enter sib2, iclass 20, count 2 2006.201.19:46:39.67#ibcon#flushed, iclass 20, count 2 2006.201.19:46:39.67#ibcon#about to write, iclass 20, count 2 2006.201.19:46:39.67#ibcon#wrote, iclass 20, count 2 2006.201.19:46:39.67#ibcon#about to read 3, iclass 20, count 2 2006.201.19:46:39.70#ibcon#read 3, iclass 20, count 2 2006.201.19:46:39.70#ibcon#about to read 4, iclass 20, count 2 2006.201.19:46:39.70#ibcon#read 4, iclass 20, count 2 2006.201.19:46:39.70#ibcon#about to read 5, iclass 20, count 2 2006.201.19:46:39.70#ibcon#read 5, iclass 20, count 2 2006.201.19:46:39.70#ibcon#about to read 6, iclass 20, count 2 2006.201.19:46:39.70#ibcon#read 6, iclass 20, count 2 2006.201.19:46:39.70#ibcon#end of sib2, iclass 20, count 2 2006.201.19:46:39.70#ibcon#*after write, iclass 20, count 2 2006.201.19:46:39.70#ibcon#*before return 0, iclass 20, count 2 2006.201.19:46:39.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:39.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.19:46:39.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.19:46:39.70#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:39.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:39.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:39.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:39.82#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:46:39.82#ibcon#first serial, iclass 20, count 0 2006.201.19:46:39.82#ibcon#enter sib2, iclass 20, count 0 2006.201.19:46:39.82#ibcon#flushed, iclass 20, count 0 2006.201.19:46:39.82#ibcon#about to write, iclass 20, count 0 2006.201.19:46:39.82#ibcon#wrote, iclass 20, count 0 2006.201.19:46:39.82#ibcon#about to read 3, iclass 20, count 0 2006.201.19:46:39.84#ibcon#read 3, iclass 20, count 0 2006.201.19:46:39.84#ibcon#about to read 4, iclass 20, count 0 2006.201.19:46:39.84#ibcon#read 4, iclass 20, count 0 2006.201.19:46:39.84#ibcon#about to read 5, iclass 20, count 0 2006.201.19:46:39.84#ibcon#read 5, iclass 20, count 0 2006.201.19:46:39.84#ibcon#about to read 6, iclass 20, count 0 2006.201.19:46:39.84#ibcon#read 6, iclass 20, count 0 2006.201.19:46:39.84#ibcon#end of sib2, iclass 20, count 0 2006.201.19:46:39.84#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:46:39.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:46:39.84#ibcon#[27=USB\r\n] 2006.201.19:46:39.84#ibcon#*before write, iclass 20, count 0 2006.201.19:46:39.84#ibcon#enter sib2, iclass 20, count 0 2006.201.19:46:39.84#ibcon#flushed, iclass 20, count 0 2006.201.19:46:39.84#ibcon#about to write, iclass 20, count 0 2006.201.19:46:39.84#ibcon#wrote, iclass 20, count 0 2006.201.19:46:39.84#ibcon#about to read 3, iclass 20, count 0 2006.201.19:46:39.87#ibcon#read 3, iclass 20, count 0 2006.201.19:46:39.87#ibcon#about to read 4, iclass 20, count 0 2006.201.19:46:39.87#ibcon#read 4, iclass 20, count 0 2006.201.19:46:39.87#ibcon#about to read 5, iclass 20, count 0 2006.201.19:46:39.87#ibcon#read 5, iclass 20, count 0 2006.201.19:46:39.87#ibcon#about to read 6, iclass 20, count 0 2006.201.19:46:39.87#ibcon#read 6, iclass 20, count 0 2006.201.19:46:39.87#ibcon#end of sib2, iclass 20, count 0 2006.201.19:46:39.87#ibcon#*after write, iclass 20, count 0 2006.201.19:46:39.87#ibcon#*before return 0, iclass 20, count 0 2006.201.19:46:39.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:39.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.19:46:39.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:46:39.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:46:39.87$vck44/vblo=5,709.99 2006.201.19:46:39.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.19:46:39.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.19:46:39.87#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:39.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:39.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:39.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:39.87#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:46:39.87#ibcon#first serial, iclass 22, count 0 2006.201.19:46:39.87#ibcon#enter sib2, iclass 22, count 0 2006.201.19:46:39.87#ibcon#flushed, iclass 22, count 0 2006.201.19:46:39.87#ibcon#about to write, iclass 22, count 0 2006.201.19:46:39.87#ibcon#wrote, iclass 22, count 0 2006.201.19:46:39.87#ibcon#about to read 3, iclass 22, count 0 2006.201.19:46:39.89#ibcon#read 3, iclass 22, count 0 2006.201.19:46:39.89#ibcon#about to read 4, iclass 22, count 0 2006.201.19:46:39.89#ibcon#read 4, iclass 22, count 0 2006.201.19:46:39.89#ibcon#about to read 5, iclass 22, count 0 2006.201.19:46:39.89#ibcon#read 5, iclass 22, count 0 2006.201.19:46:39.89#ibcon#about to read 6, iclass 22, count 0 2006.201.19:46:39.89#ibcon#read 6, iclass 22, count 0 2006.201.19:46:39.89#ibcon#end of sib2, iclass 22, count 0 2006.201.19:46:39.89#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:46:39.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:46:39.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:46:39.89#ibcon#*before write, iclass 22, count 0 2006.201.19:46:39.89#ibcon#enter sib2, iclass 22, count 0 2006.201.19:46:39.89#ibcon#flushed, iclass 22, count 0 2006.201.19:46:39.89#ibcon#about to write, iclass 22, count 0 2006.201.19:46:39.89#ibcon#wrote, iclass 22, count 0 2006.201.19:46:39.89#ibcon#about to read 3, iclass 22, count 0 2006.201.19:46:39.93#ibcon#read 3, iclass 22, count 0 2006.201.19:46:39.93#ibcon#about to read 4, iclass 22, count 0 2006.201.19:46:39.93#ibcon#read 4, iclass 22, count 0 2006.201.19:46:39.93#ibcon#about to read 5, iclass 22, count 0 2006.201.19:46:39.93#ibcon#read 5, iclass 22, count 0 2006.201.19:46:39.93#ibcon#about to read 6, iclass 22, count 0 2006.201.19:46:39.93#ibcon#read 6, iclass 22, count 0 2006.201.19:46:39.93#ibcon#end of sib2, iclass 22, count 0 2006.201.19:46:39.93#ibcon#*after write, iclass 22, count 0 2006.201.19:46:39.93#ibcon#*before return 0, iclass 22, count 0 2006.201.19:46:39.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:39.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.19:46:39.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:46:39.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:46:39.93$vck44/vb=5,4 2006.201.19:46:39.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.19:46:39.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.19:46:39.93#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:39.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:39.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:39.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:39.99#ibcon#enter wrdev, iclass 24, count 2 2006.201.19:46:39.99#ibcon#first serial, iclass 24, count 2 2006.201.19:46:39.99#ibcon#enter sib2, iclass 24, count 2 2006.201.19:46:39.99#ibcon#flushed, iclass 24, count 2 2006.201.19:46:39.99#ibcon#about to write, iclass 24, count 2 2006.201.19:46:39.99#ibcon#wrote, iclass 24, count 2 2006.201.19:46:39.99#ibcon#about to read 3, iclass 24, count 2 2006.201.19:46:40.01#ibcon#read 3, iclass 24, count 2 2006.201.19:46:40.01#ibcon#about to read 4, iclass 24, count 2 2006.201.19:46:40.01#ibcon#read 4, iclass 24, count 2 2006.201.19:46:40.01#ibcon#about to read 5, iclass 24, count 2 2006.201.19:46:40.01#ibcon#read 5, iclass 24, count 2 2006.201.19:46:40.01#ibcon#about to read 6, iclass 24, count 2 2006.201.19:46:40.01#ibcon#read 6, iclass 24, count 2 2006.201.19:46:40.01#ibcon#end of sib2, iclass 24, count 2 2006.201.19:46:40.01#ibcon#*mode == 0, iclass 24, count 2 2006.201.19:46:40.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.19:46:40.01#ibcon#[27=AT05-04\r\n] 2006.201.19:46:40.01#ibcon#*before write, iclass 24, count 2 2006.201.19:46:40.01#ibcon#enter sib2, iclass 24, count 2 2006.201.19:46:40.01#ibcon#flushed, iclass 24, count 2 2006.201.19:46:40.01#ibcon#about to write, iclass 24, count 2 2006.201.19:46:40.01#ibcon#wrote, iclass 24, count 2 2006.201.19:46:40.01#ibcon#about to read 3, iclass 24, count 2 2006.201.19:46:40.04#ibcon#read 3, iclass 24, count 2 2006.201.19:46:40.04#ibcon#about to read 4, iclass 24, count 2 2006.201.19:46:40.04#ibcon#read 4, iclass 24, count 2 2006.201.19:46:40.04#ibcon#about to read 5, iclass 24, count 2 2006.201.19:46:40.04#ibcon#read 5, iclass 24, count 2 2006.201.19:46:40.04#ibcon#about to read 6, iclass 24, count 2 2006.201.19:46:40.04#ibcon#read 6, iclass 24, count 2 2006.201.19:46:40.04#ibcon#end of sib2, iclass 24, count 2 2006.201.19:46:40.04#ibcon#*after write, iclass 24, count 2 2006.201.19:46:40.04#ibcon#*before return 0, iclass 24, count 2 2006.201.19:46:40.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:40.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.19:46:40.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.19:46:40.04#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:40.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:40.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:40.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:40.16#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:46:40.16#ibcon#first serial, iclass 24, count 0 2006.201.19:46:40.16#ibcon#enter sib2, iclass 24, count 0 2006.201.19:46:40.16#ibcon#flushed, iclass 24, count 0 2006.201.19:46:40.16#ibcon#about to write, iclass 24, count 0 2006.201.19:46:40.16#ibcon#wrote, iclass 24, count 0 2006.201.19:46:40.16#ibcon#about to read 3, iclass 24, count 0 2006.201.19:46:40.18#ibcon#read 3, iclass 24, count 0 2006.201.19:46:40.18#ibcon#about to read 4, iclass 24, count 0 2006.201.19:46:40.18#ibcon#read 4, iclass 24, count 0 2006.201.19:46:40.18#ibcon#about to read 5, iclass 24, count 0 2006.201.19:46:40.18#ibcon#read 5, iclass 24, count 0 2006.201.19:46:40.18#ibcon#about to read 6, iclass 24, count 0 2006.201.19:46:40.18#ibcon#read 6, iclass 24, count 0 2006.201.19:46:40.18#ibcon#end of sib2, iclass 24, count 0 2006.201.19:46:40.18#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:46:40.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:46:40.18#ibcon#[27=USB\r\n] 2006.201.19:46:40.18#ibcon#*before write, iclass 24, count 0 2006.201.19:46:40.18#ibcon#enter sib2, iclass 24, count 0 2006.201.19:46:40.18#ibcon#flushed, iclass 24, count 0 2006.201.19:46:40.18#ibcon#about to write, iclass 24, count 0 2006.201.19:46:40.18#ibcon#wrote, iclass 24, count 0 2006.201.19:46:40.18#ibcon#about to read 3, iclass 24, count 0 2006.201.19:46:40.21#ibcon#read 3, iclass 24, count 0 2006.201.19:46:40.21#ibcon#about to read 4, iclass 24, count 0 2006.201.19:46:40.21#ibcon#read 4, iclass 24, count 0 2006.201.19:46:40.21#ibcon#about to read 5, iclass 24, count 0 2006.201.19:46:40.21#ibcon#read 5, iclass 24, count 0 2006.201.19:46:40.21#ibcon#about to read 6, iclass 24, count 0 2006.201.19:46:40.21#ibcon#read 6, iclass 24, count 0 2006.201.19:46:40.21#ibcon#end of sib2, iclass 24, count 0 2006.201.19:46:40.21#ibcon#*after write, iclass 24, count 0 2006.201.19:46:40.21#ibcon#*before return 0, iclass 24, count 0 2006.201.19:46:40.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:40.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.19:46:40.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:46:40.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:46:40.21$vck44/vblo=6,719.99 2006.201.19:46:40.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.19:46:40.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.19:46:40.21#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:40.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:40.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:40.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:40.21#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:46:40.21#ibcon#first serial, iclass 26, count 0 2006.201.19:46:40.21#ibcon#enter sib2, iclass 26, count 0 2006.201.19:46:40.21#ibcon#flushed, iclass 26, count 0 2006.201.19:46:40.21#ibcon#about to write, iclass 26, count 0 2006.201.19:46:40.21#ibcon#wrote, iclass 26, count 0 2006.201.19:46:40.21#ibcon#about to read 3, iclass 26, count 0 2006.201.19:46:40.23#ibcon#read 3, iclass 26, count 0 2006.201.19:46:40.23#ibcon#about to read 4, iclass 26, count 0 2006.201.19:46:40.23#ibcon#read 4, iclass 26, count 0 2006.201.19:46:40.23#ibcon#about to read 5, iclass 26, count 0 2006.201.19:46:40.23#ibcon#read 5, iclass 26, count 0 2006.201.19:46:40.23#ibcon#about to read 6, iclass 26, count 0 2006.201.19:46:40.23#ibcon#read 6, iclass 26, count 0 2006.201.19:46:40.23#ibcon#end of sib2, iclass 26, count 0 2006.201.19:46:40.23#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:46:40.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:46:40.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:46:40.23#ibcon#*before write, iclass 26, count 0 2006.201.19:46:40.23#ibcon#enter sib2, iclass 26, count 0 2006.201.19:46:40.23#ibcon#flushed, iclass 26, count 0 2006.201.19:46:40.23#ibcon#about to write, iclass 26, count 0 2006.201.19:46:40.23#ibcon#wrote, iclass 26, count 0 2006.201.19:46:40.23#ibcon#about to read 3, iclass 26, count 0 2006.201.19:46:40.27#ibcon#read 3, iclass 26, count 0 2006.201.19:46:40.27#ibcon#about to read 4, iclass 26, count 0 2006.201.19:46:40.27#ibcon#read 4, iclass 26, count 0 2006.201.19:46:40.27#ibcon#about to read 5, iclass 26, count 0 2006.201.19:46:40.27#ibcon#read 5, iclass 26, count 0 2006.201.19:46:40.27#ibcon#about to read 6, iclass 26, count 0 2006.201.19:46:40.27#ibcon#read 6, iclass 26, count 0 2006.201.19:46:40.27#ibcon#end of sib2, iclass 26, count 0 2006.201.19:46:40.27#ibcon#*after write, iclass 26, count 0 2006.201.19:46:40.27#ibcon#*before return 0, iclass 26, count 0 2006.201.19:46:40.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:40.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.19:46:40.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:46:40.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:46:40.27$vck44/vb=6,4 2006.201.19:46:40.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.19:46:40.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.19:46:40.27#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:40.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:40.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:40.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:40.33#ibcon#enter wrdev, iclass 28, count 2 2006.201.19:46:40.33#ibcon#first serial, iclass 28, count 2 2006.201.19:46:40.33#ibcon#enter sib2, iclass 28, count 2 2006.201.19:46:40.33#ibcon#flushed, iclass 28, count 2 2006.201.19:46:40.33#ibcon#about to write, iclass 28, count 2 2006.201.19:46:40.33#ibcon#wrote, iclass 28, count 2 2006.201.19:46:40.33#ibcon#about to read 3, iclass 28, count 2 2006.201.19:46:40.35#ibcon#read 3, iclass 28, count 2 2006.201.19:46:40.35#ibcon#about to read 4, iclass 28, count 2 2006.201.19:46:40.35#ibcon#read 4, iclass 28, count 2 2006.201.19:46:40.35#ibcon#about to read 5, iclass 28, count 2 2006.201.19:46:40.35#ibcon#read 5, iclass 28, count 2 2006.201.19:46:40.35#ibcon#about to read 6, iclass 28, count 2 2006.201.19:46:40.35#ibcon#read 6, iclass 28, count 2 2006.201.19:46:40.35#ibcon#end of sib2, iclass 28, count 2 2006.201.19:46:40.35#ibcon#*mode == 0, iclass 28, count 2 2006.201.19:46:40.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.19:46:40.35#ibcon#[27=AT06-04\r\n] 2006.201.19:46:40.35#ibcon#*before write, iclass 28, count 2 2006.201.19:46:40.35#ibcon#enter sib2, iclass 28, count 2 2006.201.19:46:40.35#ibcon#flushed, iclass 28, count 2 2006.201.19:46:40.35#ibcon#about to write, iclass 28, count 2 2006.201.19:46:40.35#ibcon#wrote, iclass 28, count 2 2006.201.19:46:40.35#ibcon#about to read 3, iclass 28, count 2 2006.201.19:46:40.38#ibcon#read 3, iclass 28, count 2 2006.201.19:46:40.38#ibcon#about to read 4, iclass 28, count 2 2006.201.19:46:40.38#ibcon#read 4, iclass 28, count 2 2006.201.19:46:40.38#ibcon#about to read 5, iclass 28, count 2 2006.201.19:46:40.38#ibcon#read 5, iclass 28, count 2 2006.201.19:46:40.38#ibcon#about to read 6, iclass 28, count 2 2006.201.19:46:40.38#ibcon#read 6, iclass 28, count 2 2006.201.19:46:40.38#ibcon#end of sib2, iclass 28, count 2 2006.201.19:46:40.38#ibcon#*after write, iclass 28, count 2 2006.201.19:46:40.38#ibcon#*before return 0, iclass 28, count 2 2006.201.19:46:40.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:40.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.19:46:40.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.19:46:40.38#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:40.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:40.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:40.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:40.50#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:46:40.50#ibcon#first serial, iclass 28, count 0 2006.201.19:46:40.50#ibcon#enter sib2, iclass 28, count 0 2006.201.19:46:40.50#ibcon#flushed, iclass 28, count 0 2006.201.19:46:40.50#ibcon#about to write, iclass 28, count 0 2006.201.19:46:40.50#ibcon#wrote, iclass 28, count 0 2006.201.19:46:40.50#ibcon#about to read 3, iclass 28, count 0 2006.201.19:46:40.52#ibcon#read 3, iclass 28, count 0 2006.201.19:46:40.52#ibcon#about to read 4, iclass 28, count 0 2006.201.19:46:40.52#ibcon#read 4, iclass 28, count 0 2006.201.19:46:40.52#ibcon#about to read 5, iclass 28, count 0 2006.201.19:46:40.52#ibcon#read 5, iclass 28, count 0 2006.201.19:46:40.52#ibcon#about to read 6, iclass 28, count 0 2006.201.19:46:40.52#ibcon#read 6, iclass 28, count 0 2006.201.19:46:40.52#ibcon#end of sib2, iclass 28, count 0 2006.201.19:46:40.52#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:46:40.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:46:40.52#ibcon#[27=USB\r\n] 2006.201.19:46:40.52#ibcon#*before write, iclass 28, count 0 2006.201.19:46:40.52#ibcon#enter sib2, iclass 28, count 0 2006.201.19:46:40.52#ibcon#flushed, iclass 28, count 0 2006.201.19:46:40.52#ibcon#about to write, iclass 28, count 0 2006.201.19:46:40.52#ibcon#wrote, iclass 28, count 0 2006.201.19:46:40.52#ibcon#about to read 3, iclass 28, count 0 2006.201.19:46:40.55#ibcon#read 3, iclass 28, count 0 2006.201.19:46:40.55#ibcon#about to read 4, iclass 28, count 0 2006.201.19:46:40.55#ibcon#read 4, iclass 28, count 0 2006.201.19:46:40.55#ibcon#about to read 5, iclass 28, count 0 2006.201.19:46:40.55#ibcon#read 5, iclass 28, count 0 2006.201.19:46:40.55#ibcon#about to read 6, iclass 28, count 0 2006.201.19:46:40.55#ibcon#read 6, iclass 28, count 0 2006.201.19:46:40.55#ibcon#end of sib2, iclass 28, count 0 2006.201.19:46:40.55#ibcon#*after write, iclass 28, count 0 2006.201.19:46:40.55#ibcon#*before return 0, iclass 28, count 0 2006.201.19:46:40.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:40.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.19:46:40.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:46:40.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:46:40.55$vck44/vblo=7,734.99 2006.201.19:46:40.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.19:46:40.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.19:46:40.55#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:40.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:40.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:40.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:40.55#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:46:40.55#ibcon#first serial, iclass 30, count 0 2006.201.19:46:40.55#ibcon#enter sib2, iclass 30, count 0 2006.201.19:46:40.55#ibcon#flushed, iclass 30, count 0 2006.201.19:46:40.55#ibcon#about to write, iclass 30, count 0 2006.201.19:46:40.55#ibcon#wrote, iclass 30, count 0 2006.201.19:46:40.55#ibcon#about to read 3, iclass 30, count 0 2006.201.19:46:40.57#ibcon#read 3, iclass 30, count 0 2006.201.19:46:40.57#ibcon#about to read 4, iclass 30, count 0 2006.201.19:46:40.57#ibcon#read 4, iclass 30, count 0 2006.201.19:46:40.57#ibcon#about to read 5, iclass 30, count 0 2006.201.19:46:40.57#ibcon#read 5, iclass 30, count 0 2006.201.19:46:40.57#ibcon#about to read 6, iclass 30, count 0 2006.201.19:46:40.57#ibcon#read 6, iclass 30, count 0 2006.201.19:46:40.57#ibcon#end of sib2, iclass 30, count 0 2006.201.19:46:40.57#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:46:40.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:46:40.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:46:40.57#ibcon#*before write, iclass 30, count 0 2006.201.19:46:40.57#ibcon#enter sib2, iclass 30, count 0 2006.201.19:46:40.57#ibcon#flushed, iclass 30, count 0 2006.201.19:46:40.57#ibcon#about to write, iclass 30, count 0 2006.201.19:46:40.57#ibcon#wrote, iclass 30, count 0 2006.201.19:46:40.57#ibcon#about to read 3, iclass 30, count 0 2006.201.19:46:40.61#ibcon#read 3, iclass 30, count 0 2006.201.19:46:40.61#ibcon#about to read 4, iclass 30, count 0 2006.201.19:46:40.61#ibcon#read 4, iclass 30, count 0 2006.201.19:46:40.61#ibcon#about to read 5, iclass 30, count 0 2006.201.19:46:40.61#ibcon#read 5, iclass 30, count 0 2006.201.19:46:40.61#ibcon#about to read 6, iclass 30, count 0 2006.201.19:46:40.61#ibcon#read 6, iclass 30, count 0 2006.201.19:46:40.61#ibcon#end of sib2, iclass 30, count 0 2006.201.19:46:40.61#ibcon#*after write, iclass 30, count 0 2006.201.19:46:40.61#ibcon#*before return 0, iclass 30, count 0 2006.201.19:46:40.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:40.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.19:46:40.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:46:40.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:46:40.61$vck44/vb=7,4 2006.201.19:46:40.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.19:46:40.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.19:46:40.61#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:40.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:40.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:40.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:40.67#ibcon#enter wrdev, iclass 32, count 2 2006.201.19:46:40.67#ibcon#first serial, iclass 32, count 2 2006.201.19:46:40.67#ibcon#enter sib2, iclass 32, count 2 2006.201.19:46:40.67#ibcon#flushed, iclass 32, count 2 2006.201.19:46:40.67#ibcon#about to write, iclass 32, count 2 2006.201.19:46:40.67#ibcon#wrote, iclass 32, count 2 2006.201.19:46:40.67#ibcon#about to read 3, iclass 32, count 2 2006.201.19:46:40.69#ibcon#read 3, iclass 32, count 2 2006.201.19:46:40.69#ibcon#about to read 4, iclass 32, count 2 2006.201.19:46:40.69#ibcon#read 4, iclass 32, count 2 2006.201.19:46:40.69#ibcon#about to read 5, iclass 32, count 2 2006.201.19:46:40.69#ibcon#read 5, iclass 32, count 2 2006.201.19:46:40.69#ibcon#about to read 6, iclass 32, count 2 2006.201.19:46:40.69#ibcon#read 6, iclass 32, count 2 2006.201.19:46:40.69#ibcon#end of sib2, iclass 32, count 2 2006.201.19:46:40.69#ibcon#*mode == 0, iclass 32, count 2 2006.201.19:46:40.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.19:46:40.69#ibcon#[27=AT07-04\r\n] 2006.201.19:46:40.69#ibcon#*before write, iclass 32, count 2 2006.201.19:46:40.69#ibcon#enter sib2, iclass 32, count 2 2006.201.19:46:40.69#ibcon#flushed, iclass 32, count 2 2006.201.19:46:40.69#ibcon#about to write, iclass 32, count 2 2006.201.19:46:40.69#ibcon#wrote, iclass 32, count 2 2006.201.19:46:40.69#ibcon#about to read 3, iclass 32, count 2 2006.201.19:46:40.72#ibcon#read 3, iclass 32, count 2 2006.201.19:46:40.72#ibcon#about to read 4, iclass 32, count 2 2006.201.19:46:40.72#ibcon#read 4, iclass 32, count 2 2006.201.19:46:40.72#ibcon#about to read 5, iclass 32, count 2 2006.201.19:46:40.72#ibcon#read 5, iclass 32, count 2 2006.201.19:46:40.72#ibcon#about to read 6, iclass 32, count 2 2006.201.19:46:40.72#ibcon#read 6, iclass 32, count 2 2006.201.19:46:40.72#ibcon#end of sib2, iclass 32, count 2 2006.201.19:46:40.72#ibcon#*after write, iclass 32, count 2 2006.201.19:46:40.72#ibcon#*before return 0, iclass 32, count 2 2006.201.19:46:40.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:40.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.19:46:40.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.19:46:40.72#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:40.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:40.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:40.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:40.84#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:46:40.84#ibcon#first serial, iclass 32, count 0 2006.201.19:46:40.84#ibcon#enter sib2, iclass 32, count 0 2006.201.19:46:40.84#ibcon#flushed, iclass 32, count 0 2006.201.19:46:40.84#ibcon#about to write, iclass 32, count 0 2006.201.19:46:40.84#ibcon#wrote, iclass 32, count 0 2006.201.19:46:40.84#ibcon#about to read 3, iclass 32, count 0 2006.201.19:46:40.86#ibcon#read 3, iclass 32, count 0 2006.201.19:46:40.86#ibcon#about to read 4, iclass 32, count 0 2006.201.19:46:40.86#ibcon#read 4, iclass 32, count 0 2006.201.19:46:40.86#ibcon#about to read 5, iclass 32, count 0 2006.201.19:46:40.86#ibcon#read 5, iclass 32, count 0 2006.201.19:46:40.86#ibcon#about to read 6, iclass 32, count 0 2006.201.19:46:40.86#ibcon#read 6, iclass 32, count 0 2006.201.19:46:40.86#ibcon#end of sib2, iclass 32, count 0 2006.201.19:46:40.86#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:46:40.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:46:40.86#ibcon#[27=USB\r\n] 2006.201.19:46:40.86#ibcon#*before write, iclass 32, count 0 2006.201.19:46:40.86#ibcon#enter sib2, iclass 32, count 0 2006.201.19:46:40.86#ibcon#flushed, iclass 32, count 0 2006.201.19:46:40.86#ibcon#about to write, iclass 32, count 0 2006.201.19:46:40.86#ibcon#wrote, iclass 32, count 0 2006.201.19:46:40.86#ibcon#about to read 3, iclass 32, count 0 2006.201.19:46:40.89#ibcon#read 3, iclass 32, count 0 2006.201.19:46:40.89#ibcon#about to read 4, iclass 32, count 0 2006.201.19:46:40.89#ibcon#read 4, iclass 32, count 0 2006.201.19:46:40.89#ibcon#about to read 5, iclass 32, count 0 2006.201.19:46:40.89#ibcon#read 5, iclass 32, count 0 2006.201.19:46:40.89#ibcon#about to read 6, iclass 32, count 0 2006.201.19:46:40.89#ibcon#read 6, iclass 32, count 0 2006.201.19:46:40.89#ibcon#end of sib2, iclass 32, count 0 2006.201.19:46:40.89#ibcon#*after write, iclass 32, count 0 2006.201.19:46:40.89#ibcon#*before return 0, iclass 32, count 0 2006.201.19:46:40.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:40.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.19:46:40.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:46:40.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:46:40.89$vck44/vblo=8,744.99 2006.201.19:46:40.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.19:46:40.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.19:46:40.89#ibcon#ireg 17 cls_cnt 0 2006.201.19:46:40.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:40.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:40.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:40.89#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:46:40.89#ibcon#first serial, iclass 34, count 0 2006.201.19:46:40.89#ibcon#enter sib2, iclass 34, count 0 2006.201.19:46:40.89#ibcon#flushed, iclass 34, count 0 2006.201.19:46:40.89#ibcon#about to write, iclass 34, count 0 2006.201.19:46:40.89#ibcon#wrote, iclass 34, count 0 2006.201.19:46:40.89#ibcon#about to read 3, iclass 34, count 0 2006.201.19:46:40.91#ibcon#read 3, iclass 34, count 0 2006.201.19:46:40.91#ibcon#about to read 4, iclass 34, count 0 2006.201.19:46:40.91#ibcon#read 4, iclass 34, count 0 2006.201.19:46:40.91#ibcon#about to read 5, iclass 34, count 0 2006.201.19:46:40.91#ibcon#read 5, iclass 34, count 0 2006.201.19:46:40.91#ibcon#about to read 6, iclass 34, count 0 2006.201.19:46:40.91#ibcon#read 6, iclass 34, count 0 2006.201.19:46:40.91#ibcon#end of sib2, iclass 34, count 0 2006.201.19:46:40.91#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:46:40.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:46:40.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:46:40.91#ibcon#*before write, iclass 34, count 0 2006.201.19:46:40.91#ibcon#enter sib2, iclass 34, count 0 2006.201.19:46:40.91#ibcon#flushed, iclass 34, count 0 2006.201.19:46:40.91#ibcon#about to write, iclass 34, count 0 2006.201.19:46:40.91#ibcon#wrote, iclass 34, count 0 2006.201.19:46:40.91#ibcon#about to read 3, iclass 34, count 0 2006.201.19:46:40.95#ibcon#read 3, iclass 34, count 0 2006.201.19:46:40.95#ibcon#about to read 4, iclass 34, count 0 2006.201.19:46:40.95#ibcon#read 4, iclass 34, count 0 2006.201.19:46:40.95#ibcon#about to read 5, iclass 34, count 0 2006.201.19:46:40.95#ibcon#read 5, iclass 34, count 0 2006.201.19:46:40.95#ibcon#about to read 6, iclass 34, count 0 2006.201.19:46:40.95#ibcon#read 6, iclass 34, count 0 2006.201.19:46:40.95#ibcon#end of sib2, iclass 34, count 0 2006.201.19:46:40.95#ibcon#*after write, iclass 34, count 0 2006.201.19:46:40.95#ibcon#*before return 0, iclass 34, count 0 2006.201.19:46:40.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:40.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.19:46:40.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:46:40.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:46:40.95$vck44/vb=8,4 2006.201.19:46:40.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.19:46:40.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.19:46:40.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:46:40.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:41.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:41.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:41.01#ibcon#enter wrdev, iclass 36, count 2 2006.201.19:46:41.01#ibcon#first serial, iclass 36, count 2 2006.201.19:46:41.01#ibcon#enter sib2, iclass 36, count 2 2006.201.19:46:41.01#ibcon#flushed, iclass 36, count 2 2006.201.19:46:41.01#ibcon#about to write, iclass 36, count 2 2006.201.19:46:41.01#ibcon#wrote, iclass 36, count 2 2006.201.19:46:41.01#ibcon#about to read 3, iclass 36, count 2 2006.201.19:46:41.03#ibcon#read 3, iclass 36, count 2 2006.201.19:46:41.03#ibcon#about to read 4, iclass 36, count 2 2006.201.19:46:41.03#ibcon#read 4, iclass 36, count 2 2006.201.19:46:41.03#ibcon#about to read 5, iclass 36, count 2 2006.201.19:46:41.03#ibcon#read 5, iclass 36, count 2 2006.201.19:46:41.03#ibcon#about to read 6, iclass 36, count 2 2006.201.19:46:41.03#ibcon#read 6, iclass 36, count 2 2006.201.19:46:41.03#ibcon#end of sib2, iclass 36, count 2 2006.201.19:46:41.03#ibcon#*mode == 0, iclass 36, count 2 2006.201.19:46:41.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.19:46:41.03#ibcon#[27=AT08-04\r\n] 2006.201.19:46:41.03#ibcon#*before write, iclass 36, count 2 2006.201.19:46:41.03#ibcon#enter sib2, iclass 36, count 2 2006.201.19:46:41.03#ibcon#flushed, iclass 36, count 2 2006.201.19:46:41.03#ibcon#about to write, iclass 36, count 2 2006.201.19:46:41.03#ibcon#wrote, iclass 36, count 2 2006.201.19:46:41.03#ibcon#about to read 3, iclass 36, count 2 2006.201.19:46:41.06#ibcon#read 3, iclass 36, count 2 2006.201.19:46:41.06#ibcon#about to read 4, iclass 36, count 2 2006.201.19:46:41.06#ibcon#read 4, iclass 36, count 2 2006.201.19:46:41.06#ibcon#about to read 5, iclass 36, count 2 2006.201.19:46:41.06#ibcon#read 5, iclass 36, count 2 2006.201.19:46:41.06#ibcon#about to read 6, iclass 36, count 2 2006.201.19:46:41.06#ibcon#read 6, iclass 36, count 2 2006.201.19:46:41.06#ibcon#end of sib2, iclass 36, count 2 2006.201.19:46:41.06#ibcon#*after write, iclass 36, count 2 2006.201.19:46:41.06#ibcon#*before return 0, iclass 36, count 2 2006.201.19:46:41.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:41.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.19:46:41.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.19:46:41.06#ibcon#ireg 7 cls_cnt 0 2006.201.19:46:41.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:41.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:41.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:41.18#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:46:41.18#ibcon#first serial, iclass 36, count 0 2006.201.19:46:41.18#ibcon#enter sib2, iclass 36, count 0 2006.201.19:46:41.18#ibcon#flushed, iclass 36, count 0 2006.201.19:46:41.18#ibcon#about to write, iclass 36, count 0 2006.201.19:46:41.18#ibcon#wrote, iclass 36, count 0 2006.201.19:46:41.18#ibcon#about to read 3, iclass 36, count 0 2006.201.19:46:41.21#ibcon#read 3, iclass 36, count 0 2006.201.19:46:41.21#ibcon#about to read 4, iclass 36, count 0 2006.201.19:46:41.21#ibcon#read 4, iclass 36, count 0 2006.201.19:46:41.21#ibcon#about to read 5, iclass 36, count 0 2006.201.19:46:41.21#ibcon#read 5, iclass 36, count 0 2006.201.19:46:41.21#ibcon#about to read 6, iclass 36, count 0 2006.201.19:46:41.21#ibcon#read 6, iclass 36, count 0 2006.201.19:46:41.21#ibcon#end of sib2, iclass 36, count 0 2006.201.19:46:41.21#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:46:41.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:46:41.21#ibcon#[27=USB\r\n] 2006.201.19:46:41.21#ibcon#*before write, iclass 36, count 0 2006.201.19:46:41.21#ibcon#enter sib2, iclass 36, count 0 2006.201.19:46:41.21#ibcon#flushed, iclass 36, count 0 2006.201.19:46:41.21#ibcon#about to write, iclass 36, count 0 2006.201.19:46:41.21#ibcon#wrote, iclass 36, count 0 2006.201.19:46:41.21#ibcon#about to read 3, iclass 36, count 0 2006.201.19:46:41.24#ibcon#read 3, iclass 36, count 0 2006.201.19:46:41.24#ibcon#about to read 4, iclass 36, count 0 2006.201.19:46:41.24#ibcon#read 4, iclass 36, count 0 2006.201.19:46:41.24#ibcon#about to read 5, iclass 36, count 0 2006.201.19:46:41.24#ibcon#read 5, iclass 36, count 0 2006.201.19:46:41.24#ibcon#about to read 6, iclass 36, count 0 2006.201.19:46:41.24#ibcon#read 6, iclass 36, count 0 2006.201.19:46:41.24#ibcon#end of sib2, iclass 36, count 0 2006.201.19:46:41.24#ibcon#*after write, iclass 36, count 0 2006.201.19:46:41.24#ibcon#*before return 0, iclass 36, count 0 2006.201.19:46:41.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:41.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.19:46:41.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:46:41.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:46:41.24$vck44/vabw=wide 2006.201.19:46:41.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.19:46:41.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.19:46:41.24#ibcon#ireg 8 cls_cnt 0 2006.201.19:46:41.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:41.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:41.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:41.24#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:46:41.24#ibcon#first serial, iclass 38, count 0 2006.201.19:46:41.24#ibcon#enter sib2, iclass 38, count 0 2006.201.19:46:41.24#ibcon#flushed, iclass 38, count 0 2006.201.19:46:41.24#ibcon#about to write, iclass 38, count 0 2006.201.19:46:41.24#ibcon#wrote, iclass 38, count 0 2006.201.19:46:41.24#ibcon#about to read 3, iclass 38, count 0 2006.201.19:46:41.26#ibcon#read 3, iclass 38, count 0 2006.201.19:46:41.26#ibcon#about to read 4, iclass 38, count 0 2006.201.19:46:41.26#ibcon#read 4, iclass 38, count 0 2006.201.19:46:41.26#ibcon#about to read 5, iclass 38, count 0 2006.201.19:46:41.26#ibcon#read 5, iclass 38, count 0 2006.201.19:46:41.26#ibcon#about to read 6, iclass 38, count 0 2006.201.19:46:41.26#ibcon#read 6, iclass 38, count 0 2006.201.19:46:41.26#ibcon#end of sib2, iclass 38, count 0 2006.201.19:46:41.26#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:46:41.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:46:41.26#ibcon#[25=BW32\r\n] 2006.201.19:46:41.26#ibcon#*before write, iclass 38, count 0 2006.201.19:46:41.26#ibcon#enter sib2, iclass 38, count 0 2006.201.19:46:41.26#ibcon#flushed, iclass 38, count 0 2006.201.19:46:41.26#ibcon#about to write, iclass 38, count 0 2006.201.19:46:41.26#ibcon#wrote, iclass 38, count 0 2006.201.19:46:41.26#ibcon#about to read 3, iclass 38, count 0 2006.201.19:46:41.29#ibcon#read 3, iclass 38, count 0 2006.201.19:46:41.29#ibcon#about to read 4, iclass 38, count 0 2006.201.19:46:41.29#ibcon#read 4, iclass 38, count 0 2006.201.19:46:41.29#ibcon#about to read 5, iclass 38, count 0 2006.201.19:46:41.29#ibcon#read 5, iclass 38, count 0 2006.201.19:46:41.29#ibcon#about to read 6, iclass 38, count 0 2006.201.19:46:41.29#ibcon#read 6, iclass 38, count 0 2006.201.19:46:41.29#ibcon#end of sib2, iclass 38, count 0 2006.201.19:46:41.29#ibcon#*after write, iclass 38, count 0 2006.201.19:46:41.29#ibcon#*before return 0, iclass 38, count 0 2006.201.19:46:41.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:41.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.19:46:41.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:46:41.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:46:41.29$vck44/vbbw=wide 2006.201.19:46:41.29#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.19:46:41.29#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.19:46:41.29#ibcon#ireg 8 cls_cnt 0 2006.201.19:46:41.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:46:41.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:46:41.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:46:41.36#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:46:41.36#ibcon#first serial, iclass 40, count 0 2006.201.19:46:41.36#ibcon#enter sib2, iclass 40, count 0 2006.201.19:46:41.36#ibcon#flushed, iclass 40, count 0 2006.201.19:46:41.36#ibcon#about to write, iclass 40, count 0 2006.201.19:46:41.36#ibcon#wrote, iclass 40, count 0 2006.201.19:46:41.36#ibcon#about to read 3, iclass 40, count 0 2006.201.19:46:41.38#ibcon#read 3, iclass 40, count 0 2006.201.19:46:41.38#ibcon#about to read 4, iclass 40, count 0 2006.201.19:46:41.38#ibcon#read 4, iclass 40, count 0 2006.201.19:46:41.38#ibcon#about to read 5, iclass 40, count 0 2006.201.19:46:41.38#ibcon#read 5, iclass 40, count 0 2006.201.19:46:41.38#ibcon#about to read 6, iclass 40, count 0 2006.201.19:46:41.38#ibcon#read 6, iclass 40, count 0 2006.201.19:46:41.38#ibcon#end of sib2, iclass 40, count 0 2006.201.19:46:41.38#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:46:41.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:46:41.38#ibcon#[27=BW32\r\n] 2006.201.19:46:41.38#ibcon#*before write, iclass 40, count 0 2006.201.19:46:41.38#ibcon#enter sib2, iclass 40, count 0 2006.201.19:46:41.38#ibcon#flushed, iclass 40, count 0 2006.201.19:46:41.38#ibcon#about to write, iclass 40, count 0 2006.201.19:46:41.38#ibcon#wrote, iclass 40, count 0 2006.201.19:46:41.38#ibcon#about to read 3, iclass 40, count 0 2006.201.19:46:41.41#ibcon#read 3, iclass 40, count 0 2006.201.19:46:41.41#ibcon#about to read 4, iclass 40, count 0 2006.201.19:46:41.41#ibcon#read 4, iclass 40, count 0 2006.201.19:46:41.41#ibcon#about to read 5, iclass 40, count 0 2006.201.19:46:41.41#ibcon#read 5, iclass 40, count 0 2006.201.19:46:41.41#ibcon#about to read 6, iclass 40, count 0 2006.201.19:46:41.41#ibcon#read 6, iclass 40, count 0 2006.201.19:46:41.41#ibcon#end of sib2, iclass 40, count 0 2006.201.19:46:41.41#ibcon#*after write, iclass 40, count 0 2006.201.19:46:41.41#ibcon#*before return 0, iclass 40, count 0 2006.201.19:46:41.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:46:41.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:46:41.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:46:41.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:46:41.41$setupk4/ifdk4 2006.201.19:46:41.41$ifdk4/lo= 2006.201.19:46:41.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:46:41.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:46:41.41$ifdk4/patch= 2006.201.19:46:41.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:46:41.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:46:41.41$setupk4/!*+20s 2006.201.19:46:44.69#abcon#<5=/03 2.0 4.2 20.391001002.2\r\n> 2006.201.19:46:44.71#abcon#{5=INTERFACE CLEAR} 2006.201.19:46:44.77#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:46:53.14#trakl#Source acquired 2006.201.19:46:54.98#abcon#<5=/03 2.0 4.2 20.381001002.2\r\n> 2006.201.19:46:55.00#abcon#{5=INTERFACE CLEAR} 2006.201.19:46:55.06#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:46:55.14#flagr#flagr/antenna,acquired 2006.201.19:46:55.89$setupk4/"tpicd 2006.201.19:46:55.89$setupk4/echo=off 2006.201.19:46:55.89$setupk4/xlog=off 2006.201.19:46:55.89:!2006.201.19:49:13 2006.201.19:49:13.00:preob 2006.201.19:49:14.14/onsource/TRACKING 2006.201.19:49:14.14:!2006.201.19:49:23 2006.201.19:49:23.00:"tape 2006.201.19:49:23.00:"st=record 2006.201.19:49:23.00:data_valid=on 2006.201.19:49:23.00:midob 2006.201.19:49:23.14/onsource/TRACKING 2006.201.19:49:23.14/wx/20.37,1002.2,100 2006.201.19:49:23.21/cable/+6.4794E-03 2006.201.19:49:24.30/va/01,08,usb,yes,41,44 2006.201.19:49:24.30/va/02,07,usb,yes,44,45 2006.201.19:49:24.30/va/03,08,usb,yes,40,42 2006.201.19:49:24.30/va/04,07,usb,yes,46,48 2006.201.19:49:24.30/va/05,04,usb,yes,41,42 2006.201.19:49:24.30/va/06,05,usb,yes,41,41 2006.201.19:49:24.30/va/07,05,usb,yes,40,42 2006.201.19:49:24.30/va/08,04,usb,yes,40,47 2006.201.19:49:24.53/valo/01,524.99,yes,locked 2006.201.19:49:24.53/valo/02,534.99,yes,locked 2006.201.19:49:24.53/valo/03,564.99,yes,locked 2006.201.19:49:24.53/valo/04,624.99,yes,locked 2006.201.19:49:24.53/valo/05,734.99,yes,locked 2006.201.19:49:24.53/valo/06,814.99,yes,locked 2006.201.19:49:24.53/valo/07,864.99,yes,locked 2006.201.19:49:24.53/valo/08,884.99,yes,locked 2006.201.19:49:25.62/vb/01,04,usb,yes,30,28 2006.201.19:49:25.62/vb/02,05,usb,yes,28,28 2006.201.19:49:25.62/vb/03,04,usb,yes,29,32 2006.201.19:49:25.62/vb/04,05,usb,yes,30,29 2006.201.19:49:25.62/vb/05,04,usb,yes,26,29 2006.201.19:49:25.62/vb/06,04,usb,yes,31,27 2006.201.19:49:25.62/vb/07,04,usb,yes,30,30 2006.201.19:49:25.62/vb/08,04,usb,yes,28,31 2006.201.19:49:25.86/vblo/01,629.99,yes,locked 2006.201.19:49:25.86/vblo/02,634.99,yes,locked 2006.201.19:49:25.86/vblo/03,649.99,yes,locked 2006.201.19:49:25.86/vblo/04,679.99,yes,locked 2006.201.19:49:25.86/vblo/05,709.99,yes,locked 2006.201.19:49:25.86/vblo/06,719.99,yes,locked 2006.201.19:49:25.86/vblo/07,734.99,yes,locked 2006.201.19:49:25.86/vblo/08,744.99,yes,locked 2006.201.19:49:26.01/vabw/8 2006.201.19:49:26.16/vbbw/8 2006.201.19:49:26.25/xfe/off,on,14.0 2006.201.19:49:26.63/ifatt/23,28,28,28 2006.201.19:49:27.06/fmout-gps/S +4.53E-07 2006.201.19:49:27.10:!2006.201.19:51:03 2006.201.19:51:03.00:data_valid=off 2006.201.19:51:03.00:"et 2006.201.19:51:03.00:!+3s 2006.201.19:51:06.02:"tape 2006.201.19:51:06.02:postob 2006.201.19:51:06.18/cable/+6.4788E-03 2006.201.19:51:06.21/wx/20.35,1002.2,100 2006.201.19:51:06.29/fmout-gps/S +4.54E-07 2006.201.19:51:06.29:scan_name=201-1955,jd0607,40 2006.201.19:51:06.29:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.201.19:51:08.14#flagr#flagr/antenna,new-source 2006.201.19:51:08.14:checkk5 2006.201.19:51:08.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:51:08.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:51:09.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:51:09.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:51:10.01/chk_obsdata//k5ts1/T2011949??a.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.19:51:10.38/chk_obsdata//k5ts2/T2011949??b.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.19:51:10.74/chk_obsdata//k5ts3/T2011949??c.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.19:51:11.11/chk_obsdata//k5ts4/T2011949??d.dat file size is correct (nominal:400MB, actual:396MB). 2006.201.19:51:11.80/k5log//k5ts1_log_newline 2006.201.19:51:12.48/k5log//k5ts2_log_newline 2006.201.19:51:13.17/k5log//k5ts3_log_newline 2006.201.19:51:13.86/k5log//k5ts4_log_newline 2006.201.19:51:13.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:51:13.88:setupk4=1 2006.201.19:51:13.88$setupk4/echo=on 2006.201.19:51:13.88$setupk4/pcalon 2006.201.19:51:13.88$pcalon/"no phase cal control is implemented here 2006.201.19:51:13.88$setupk4/"tpicd=stop 2006.201.19:51:13.88$setupk4/"rec=synch_on 2006.201.19:51:13.88$setupk4/"rec_mode=128 2006.201.19:51:13.88$setupk4/!* 2006.201.19:51:13.88$setupk4/recpk4 2006.201.19:51:13.88$recpk4/recpatch= 2006.201.19:51:13.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:51:13.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:51:13.89$setupk4/vck44 2006.201.19:51:13.89$vck44/valo=1,524.99 2006.201.19:51:13.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.19:51:13.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.19:51:13.89#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:13.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:13.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:13.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:13.89#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:51:13.89#ibcon#first serial, iclass 7, count 0 2006.201.19:51:13.89#ibcon#enter sib2, iclass 7, count 0 2006.201.19:51:13.89#ibcon#flushed, iclass 7, count 0 2006.201.19:51:13.89#ibcon#about to write, iclass 7, count 0 2006.201.19:51:13.89#ibcon#wrote, iclass 7, count 0 2006.201.19:51:13.89#ibcon#about to read 3, iclass 7, count 0 2006.201.19:51:13.92#ibcon#read 3, iclass 7, count 0 2006.201.19:51:13.92#ibcon#about to read 4, iclass 7, count 0 2006.201.19:51:13.92#ibcon#read 4, iclass 7, count 0 2006.201.19:51:13.92#ibcon#about to read 5, iclass 7, count 0 2006.201.19:51:13.92#ibcon#read 5, iclass 7, count 0 2006.201.19:51:13.92#ibcon#about to read 6, iclass 7, count 0 2006.201.19:51:13.92#ibcon#read 6, iclass 7, count 0 2006.201.19:51:13.92#ibcon#end of sib2, iclass 7, count 0 2006.201.19:51:13.92#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:51:13.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:51:13.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:51:13.92#ibcon#*before write, iclass 7, count 0 2006.201.19:51:13.92#ibcon#enter sib2, iclass 7, count 0 2006.201.19:51:13.92#ibcon#flushed, iclass 7, count 0 2006.201.19:51:13.92#ibcon#about to write, iclass 7, count 0 2006.201.19:51:13.92#ibcon#wrote, iclass 7, count 0 2006.201.19:51:13.92#ibcon#about to read 3, iclass 7, count 0 2006.201.19:51:13.97#ibcon#read 3, iclass 7, count 0 2006.201.19:51:13.97#ibcon#about to read 4, iclass 7, count 0 2006.201.19:51:13.97#ibcon#read 4, iclass 7, count 0 2006.201.19:51:13.97#ibcon#about to read 5, iclass 7, count 0 2006.201.19:51:13.97#ibcon#read 5, iclass 7, count 0 2006.201.19:51:13.97#ibcon#about to read 6, iclass 7, count 0 2006.201.19:51:13.97#ibcon#read 6, iclass 7, count 0 2006.201.19:51:13.97#ibcon#end of sib2, iclass 7, count 0 2006.201.19:51:13.97#ibcon#*after write, iclass 7, count 0 2006.201.19:51:13.97#ibcon#*before return 0, iclass 7, count 0 2006.201.19:51:13.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:13.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:13.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:51:13.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:51:13.97$vck44/va=1,8 2006.201.19:51:13.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.19:51:13.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.19:51:13.97#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:13.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:13.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:13.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:13.97#ibcon#enter wrdev, iclass 11, count 2 2006.201.19:51:13.97#ibcon#first serial, iclass 11, count 2 2006.201.19:51:13.97#ibcon#enter sib2, iclass 11, count 2 2006.201.19:51:13.97#ibcon#flushed, iclass 11, count 2 2006.201.19:51:13.97#ibcon#about to write, iclass 11, count 2 2006.201.19:51:13.97#ibcon#wrote, iclass 11, count 2 2006.201.19:51:13.97#ibcon#about to read 3, iclass 11, count 2 2006.201.19:51:13.99#ibcon#read 3, iclass 11, count 2 2006.201.19:51:13.99#ibcon#about to read 4, iclass 11, count 2 2006.201.19:51:13.99#ibcon#read 4, iclass 11, count 2 2006.201.19:51:13.99#ibcon#about to read 5, iclass 11, count 2 2006.201.19:51:13.99#ibcon#read 5, iclass 11, count 2 2006.201.19:51:13.99#ibcon#about to read 6, iclass 11, count 2 2006.201.19:51:13.99#ibcon#read 6, iclass 11, count 2 2006.201.19:51:13.99#ibcon#end of sib2, iclass 11, count 2 2006.201.19:51:13.99#ibcon#*mode == 0, iclass 11, count 2 2006.201.19:51:13.99#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.19:51:13.99#ibcon#[25=AT01-08\r\n] 2006.201.19:51:13.99#ibcon#*before write, iclass 11, count 2 2006.201.19:51:13.99#ibcon#enter sib2, iclass 11, count 2 2006.201.19:51:13.99#ibcon#flushed, iclass 11, count 2 2006.201.19:51:13.99#ibcon#about to write, iclass 11, count 2 2006.201.19:51:13.99#ibcon#wrote, iclass 11, count 2 2006.201.19:51:13.99#ibcon#about to read 3, iclass 11, count 2 2006.201.19:51:14.02#ibcon#read 3, iclass 11, count 2 2006.201.19:51:14.02#ibcon#about to read 4, iclass 11, count 2 2006.201.19:51:14.02#ibcon#read 4, iclass 11, count 2 2006.201.19:51:14.02#ibcon#about to read 5, iclass 11, count 2 2006.201.19:51:14.02#ibcon#read 5, iclass 11, count 2 2006.201.19:51:14.02#ibcon#about to read 6, iclass 11, count 2 2006.201.19:51:14.02#ibcon#read 6, iclass 11, count 2 2006.201.19:51:14.02#ibcon#end of sib2, iclass 11, count 2 2006.201.19:51:14.02#ibcon#*after write, iclass 11, count 2 2006.201.19:51:14.02#ibcon#*before return 0, iclass 11, count 2 2006.201.19:51:14.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:14.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:14.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.19:51:14.02#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:14.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:14.14#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:14.14#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:14.14#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:51:14.14#ibcon#first serial, iclass 11, count 0 2006.201.19:51:14.14#ibcon#enter sib2, iclass 11, count 0 2006.201.19:51:14.14#ibcon#flushed, iclass 11, count 0 2006.201.19:51:14.14#ibcon#about to write, iclass 11, count 0 2006.201.19:51:14.14#ibcon#wrote, iclass 11, count 0 2006.201.19:51:14.14#ibcon#about to read 3, iclass 11, count 0 2006.201.19:51:14.16#ibcon#read 3, iclass 11, count 0 2006.201.19:51:14.16#ibcon#about to read 4, iclass 11, count 0 2006.201.19:51:14.16#ibcon#read 4, iclass 11, count 0 2006.201.19:51:14.16#ibcon#about to read 5, iclass 11, count 0 2006.201.19:51:14.16#ibcon#read 5, iclass 11, count 0 2006.201.19:51:14.16#ibcon#about to read 6, iclass 11, count 0 2006.201.19:51:14.16#ibcon#read 6, iclass 11, count 0 2006.201.19:51:14.16#ibcon#end of sib2, iclass 11, count 0 2006.201.19:51:14.16#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:51:14.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:51:14.16#ibcon#[25=USB\r\n] 2006.201.19:51:14.16#ibcon#*before write, iclass 11, count 0 2006.201.19:51:14.16#ibcon#enter sib2, iclass 11, count 0 2006.201.19:51:14.16#ibcon#flushed, iclass 11, count 0 2006.201.19:51:14.16#ibcon#about to write, iclass 11, count 0 2006.201.19:51:14.16#ibcon#wrote, iclass 11, count 0 2006.201.19:51:14.16#ibcon#about to read 3, iclass 11, count 0 2006.201.19:51:14.19#ibcon#read 3, iclass 11, count 0 2006.201.19:51:14.19#ibcon#about to read 4, iclass 11, count 0 2006.201.19:51:14.19#ibcon#read 4, iclass 11, count 0 2006.201.19:51:14.19#ibcon#about to read 5, iclass 11, count 0 2006.201.19:51:14.19#ibcon#read 5, iclass 11, count 0 2006.201.19:51:14.19#ibcon#about to read 6, iclass 11, count 0 2006.201.19:51:14.19#ibcon#read 6, iclass 11, count 0 2006.201.19:51:14.19#ibcon#end of sib2, iclass 11, count 0 2006.201.19:51:14.19#ibcon#*after write, iclass 11, count 0 2006.201.19:51:14.19#ibcon#*before return 0, iclass 11, count 0 2006.201.19:51:14.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:14.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:14.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:51:14.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:51:14.19$vck44/valo=2,534.99 2006.201.19:51:14.19#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.19:51:14.19#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.19:51:14.19#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:14.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:14.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:14.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:14.19#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:51:14.19#ibcon#first serial, iclass 13, count 0 2006.201.19:51:14.19#ibcon#enter sib2, iclass 13, count 0 2006.201.19:51:14.19#ibcon#flushed, iclass 13, count 0 2006.201.19:51:14.19#ibcon#about to write, iclass 13, count 0 2006.201.19:51:14.19#ibcon#wrote, iclass 13, count 0 2006.201.19:51:14.19#ibcon#about to read 3, iclass 13, count 0 2006.201.19:51:14.21#ibcon#read 3, iclass 13, count 0 2006.201.19:51:14.21#ibcon#about to read 4, iclass 13, count 0 2006.201.19:51:14.21#ibcon#read 4, iclass 13, count 0 2006.201.19:51:14.21#ibcon#about to read 5, iclass 13, count 0 2006.201.19:51:14.21#ibcon#read 5, iclass 13, count 0 2006.201.19:51:14.21#ibcon#about to read 6, iclass 13, count 0 2006.201.19:51:14.21#ibcon#read 6, iclass 13, count 0 2006.201.19:51:14.21#ibcon#end of sib2, iclass 13, count 0 2006.201.19:51:14.21#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:51:14.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:51:14.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:51:14.21#ibcon#*before write, iclass 13, count 0 2006.201.19:51:14.21#ibcon#enter sib2, iclass 13, count 0 2006.201.19:51:14.21#ibcon#flushed, iclass 13, count 0 2006.201.19:51:14.21#ibcon#about to write, iclass 13, count 0 2006.201.19:51:14.21#ibcon#wrote, iclass 13, count 0 2006.201.19:51:14.21#ibcon#about to read 3, iclass 13, count 0 2006.201.19:51:14.26#ibcon#read 3, iclass 13, count 0 2006.201.19:51:14.26#ibcon#about to read 4, iclass 13, count 0 2006.201.19:51:14.26#ibcon#read 4, iclass 13, count 0 2006.201.19:51:14.26#ibcon#about to read 5, iclass 13, count 0 2006.201.19:51:14.26#ibcon#read 5, iclass 13, count 0 2006.201.19:51:14.26#ibcon#about to read 6, iclass 13, count 0 2006.201.19:51:14.26#ibcon#read 6, iclass 13, count 0 2006.201.19:51:14.26#ibcon#end of sib2, iclass 13, count 0 2006.201.19:51:14.26#ibcon#*after write, iclass 13, count 0 2006.201.19:51:14.26#ibcon#*before return 0, iclass 13, count 0 2006.201.19:51:14.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:14.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:14.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:51:14.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:51:14.26$vck44/va=2,7 2006.201.19:51:14.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.19:51:14.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.19:51:14.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:14.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:14.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:14.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:14.31#ibcon#enter wrdev, iclass 15, count 2 2006.201.19:51:14.31#ibcon#first serial, iclass 15, count 2 2006.201.19:51:14.31#ibcon#enter sib2, iclass 15, count 2 2006.201.19:51:14.31#ibcon#flushed, iclass 15, count 2 2006.201.19:51:14.31#ibcon#about to write, iclass 15, count 2 2006.201.19:51:14.31#ibcon#wrote, iclass 15, count 2 2006.201.19:51:14.31#ibcon#about to read 3, iclass 15, count 2 2006.201.19:51:14.33#ibcon#read 3, iclass 15, count 2 2006.201.19:51:14.33#ibcon#about to read 4, iclass 15, count 2 2006.201.19:51:14.33#ibcon#read 4, iclass 15, count 2 2006.201.19:51:14.33#ibcon#about to read 5, iclass 15, count 2 2006.201.19:51:14.33#ibcon#read 5, iclass 15, count 2 2006.201.19:51:14.33#ibcon#about to read 6, iclass 15, count 2 2006.201.19:51:14.33#ibcon#read 6, iclass 15, count 2 2006.201.19:51:14.33#ibcon#end of sib2, iclass 15, count 2 2006.201.19:51:14.33#ibcon#*mode == 0, iclass 15, count 2 2006.201.19:51:14.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.19:51:14.33#ibcon#[25=AT02-07\r\n] 2006.201.19:51:14.33#ibcon#*before write, iclass 15, count 2 2006.201.19:51:14.33#ibcon#enter sib2, iclass 15, count 2 2006.201.19:51:14.33#ibcon#flushed, iclass 15, count 2 2006.201.19:51:14.33#ibcon#about to write, iclass 15, count 2 2006.201.19:51:14.33#ibcon#wrote, iclass 15, count 2 2006.201.19:51:14.33#ibcon#about to read 3, iclass 15, count 2 2006.201.19:51:14.36#ibcon#read 3, iclass 15, count 2 2006.201.19:51:14.36#ibcon#about to read 4, iclass 15, count 2 2006.201.19:51:14.36#ibcon#read 4, iclass 15, count 2 2006.201.19:51:14.36#ibcon#about to read 5, iclass 15, count 2 2006.201.19:51:14.36#ibcon#read 5, iclass 15, count 2 2006.201.19:51:14.36#ibcon#about to read 6, iclass 15, count 2 2006.201.19:51:14.36#ibcon#read 6, iclass 15, count 2 2006.201.19:51:14.36#ibcon#end of sib2, iclass 15, count 2 2006.201.19:51:14.36#ibcon#*after write, iclass 15, count 2 2006.201.19:51:14.36#ibcon#*before return 0, iclass 15, count 2 2006.201.19:51:14.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:14.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:14.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.19:51:14.36#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:14.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:14.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:14.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:14.48#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:51:14.48#ibcon#first serial, iclass 15, count 0 2006.201.19:51:14.48#ibcon#enter sib2, iclass 15, count 0 2006.201.19:51:14.48#ibcon#flushed, iclass 15, count 0 2006.201.19:51:14.48#ibcon#about to write, iclass 15, count 0 2006.201.19:51:14.48#ibcon#wrote, iclass 15, count 0 2006.201.19:51:14.48#ibcon#about to read 3, iclass 15, count 0 2006.201.19:51:14.50#ibcon#read 3, iclass 15, count 0 2006.201.19:51:14.50#ibcon#about to read 4, iclass 15, count 0 2006.201.19:51:14.50#ibcon#read 4, iclass 15, count 0 2006.201.19:51:14.50#ibcon#about to read 5, iclass 15, count 0 2006.201.19:51:14.50#ibcon#read 5, iclass 15, count 0 2006.201.19:51:14.50#ibcon#about to read 6, iclass 15, count 0 2006.201.19:51:14.50#ibcon#read 6, iclass 15, count 0 2006.201.19:51:14.50#ibcon#end of sib2, iclass 15, count 0 2006.201.19:51:14.50#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:51:14.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:51:14.50#ibcon#[25=USB\r\n] 2006.201.19:51:14.50#ibcon#*before write, iclass 15, count 0 2006.201.19:51:14.50#ibcon#enter sib2, iclass 15, count 0 2006.201.19:51:14.50#ibcon#flushed, iclass 15, count 0 2006.201.19:51:14.50#ibcon#about to write, iclass 15, count 0 2006.201.19:51:14.50#ibcon#wrote, iclass 15, count 0 2006.201.19:51:14.50#ibcon#about to read 3, iclass 15, count 0 2006.201.19:51:14.53#ibcon#read 3, iclass 15, count 0 2006.201.19:51:14.53#ibcon#about to read 4, iclass 15, count 0 2006.201.19:51:14.53#ibcon#read 4, iclass 15, count 0 2006.201.19:51:14.53#ibcon#about to read 5, iclass 15, count 0 2006.201.19:51:14.53#ibcon#read 5, iclass 15, count 0 2006.201.19:51:14.53#ibcon#about to read 6, iclass 15, count 0 2006.201.19:51:14.53#ibcon#read 6, iclass 15, count 0 2006.201.19:51:14.53#ibcon#end of sib2, iclass 15, count 0 2006.201.19:51:14.53#ibcon#*after write, iclass 15, count 0 2006.201.19:51:14.53#ibcon#*before return 0, iclass 15, count 0 2006.201.19:51:14.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:14.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:14.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:51:14.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:51:14.53$vck44/valo=3,564.99 2006.201.19:51:14.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.19:51:14.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.19:51:14.53#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:14.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:14.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:14.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:14.53#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:51:14.53#ibcon#first serial, iclass 17, count 0 2006.201.19:51:14.53#ibcon#enter sib2, iclass 17, count 0 2006.201.19:51:14.53#ibcon#flushed, iclass 17, count 0 2006.201.19:51:14.53#ibcon#about to write, iclass 17, count 0 2006.201.19:51:14.53#ibcon#wrote, iclass 17, count 0 2006.201.19:51:14.53#ibcon#about to read 3, iclass 17, count 0 2006.201.19:51:14.55#ibcon#read 3, iclass 17, count 0 2006.201.19:51:14.55#ibcon#about to read 4, iclass 17, count 0 2006.201.19:51:14.55#ibcon#read 4, iclass 17, count 0 2006.201.19:51:14.55#ibcon#about to read 5, iclass 17, count 0 2006.201.19:51:14.55#ibcon#read 5, iclass 17, count 0 2006.201.19:51:14.55#ibcon#about to read 6, iclass 17, count 0 2006.201.19:51:14.55#ibcon#read 6, iclass 17, count 0 2006.201.19:51:14.55#ibcon#end of sib2, iclass 17, count 0 2006.201.19:51:14.55#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:51:14.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:51:14.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:51:14.55#ibcon#*before write, iclass 17, count 0 2006.201.19:51:14.55#ibcon#enter sib2, iclass 17, count 0 2006.201.19:51:14.55#ibcon#flushed, iclass 17, count 0 2006.201.19:51:14.55#ibcon#about to write, iclass 17, count 0 2006.201.19:51:14.55#ibcon#wrote, iclass 17, count 0 2006.201.19:51:14.55#ibcon#about to read 3, iclass 17, count 0 2006.201.19:51:14.60#ibcon#read 3, iclass 17, count 0 2006.201.19:51:14.60#ibcon#about to read 4, iclass 17, count 0 2006.201.19:51:14.60#ibcon#read 4, iclass 17, count 0 2006.201.19:51:14.60#ibcon#about to read 5, iclass 17, count 0 2006.201.19:51:14.60#ibcon#read 5, iclass 17, count 0 2006.201.19:51:14.60#ibcon#about to read 6, iclass 17, count 0 2006.201.19:51:14.60#ibcon#read 6, iclass 17, count 0 2006.201.19:51:14.60#ibcon#end of sib2, iclass 17, count 0 2006.201.19:51:14.60#ibcon#*after write, iclass 17, count 0 2006.201.19:51:14.60#ibcon#*before return 0, iclass 17, count 0 2006.201.19:51:14.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:14.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:14.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:51:14.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:51:14.60$vck44/va=3,8 2006.201.19:51:14.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.19:51:14.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.19:51:14.60#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:14.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:14.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:14.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:14.65#ibcon#enter wrdev, iclass 19, count 2 2006.201.19:51:14.65#ibcon#first serial, iclass 19, count 2 2006.201.19:51:14.65#ibcon#enter sib2, iclass 19, count 2 2006.201.19:51:14.65#ibcon#flushed, iclass 19, count 2 2006.201.19:51:14.65#ibcon#about to write, iclass 19, count 2 2006.201.19:51:14.65#ibcon#wrote, iclass 19, count 2 2006.201.19:51:14.65#ibcon#about to read 3, iclass 19, count 2 2006.201.19:51:14.67#ibcon#read 3, iclass 19, count 2 2006.201.19:51:14.67#ibcon#about to read 4, iclass 19, count 2 2006.201.19:51:14.67#ibcon#read 4, iclass 19, count 2 2006.201.19:51:14.67#ibcon#about to read 5, iclass 19, count 2 2006.201.19:51:14.67#ibcon#read 5, iclass 19, count 2 2006.201.19:51:14.67#ibcon#about to read 6, iclass 19, count 2 2006.201.19:51:14.67#ibcon#read 6, iclass 19, count 2 2006.201.19:51:14.67#ibcon#end of sib2, iclass 19, count 2 2006.201.19:51:14.67#ibcon#*mode == 0, iclass 19, count 2 2006.201.19:51:14.67#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.19:51:14.67#ibcon#[25=AT03-08\r\n] 2006.201.19:51:14.67#ibcon#*before write, iclass 19, count 2 2006.201.19:51:14.67#ibcon#enter sib2, iclass 19, count 2 2006.201.19:51:14.67#ibcon#flushed, iclass 19, count 2 2006.201.19:51:14.67#ibcon#about to write, iclass 19, count 2 2006.201.19:51:14.67#ibcon#wrote, iclass 19, count 2 2006.201.19:51:14.67#ibcon#about to read 3, iclass 19, count 2 2006.201.19:51:14.70#ibcon#read 3, iclass 19, count 2 2006.201.19:51:14.70#ibcon#about to read 4, iclass 19, count 2 2006.201.19:51:14.70#ibcon#read 4, iclass 19, count 2 2006.201.19:51:14.70#ibcon#about to read 5, iclass 19, count 2 2006.201.19:51:14.70#ibcon#read 5, iclass 19, count 2 2006.201.19:51:14.70#ibcon#about to read 6, iclass 19, count 2 2006.201.19:51:14.70#ibcon#read 6, iclass 19, count 2 2006.201.19:51:14.70#ibcon#end of sib2, iclass 19, count 2 2006.201.19:51:14.70#ibcon#*after write, iclass 19, count 2 2006.201.19:51:14.70#ibcon#*before return 0, iclass 19, count 2 2006.201.19:51:14.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:14.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:14.70#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.19:51:14.70#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:14.70#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:14.82#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:14.82#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:14.82#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:51:14.82#ibcon#first serial, iclass 19, count 0 2006.201.19:51:14.82#ibcon#enter sib2, iclass 19, count 0 2006.201.19:51:14.82#ibcon#flushed, iclass 19, count 0 2006.201.19:51:14.82#ibcon#about to write, iclass 19, count 0 2006.201.19:51:14.82#ibcon#wrote, iclass 19, count 0 2006.201.19:51:14.82#ibcon#about to read 3, iclass 19, count 0 2006.201.19:51:14.84#ibcon#read 3, iclass 19, count 0 2006.201.19:51:14.84#ibcon#about to read 4, iclass 19, count 0 2006.201.19:51:14.84#ibcon#read 4, iclass 19, count 0 2006.201.19:51:14.84#ibcon#about to read 5, iclass 19, count 0 2006.201.19:51:14.84#ibcon#read 5, iclass 19, count 0 2006.201.19:51:14.84#ibcon#about to read 6, iclass 19, count 0 2006.201.19:51:14.84#ibcon#read 6, iclass 19, count 0 2006.201.19:51:14.84#ibcon#end of sib2, iclass 19, count 0 2006.201.19:51:14.84#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:51:14.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:51:14.84#ibcon#[25=USB\r\n] 2006.201.19:51:14.84#ibcon#*before write, iclass 19, count 0 2006.201.19:51:14.84#ibcon#enter sib2, iclass 19, count 0 2006.201.19:51:14.84#ibcon#flushed, iclass 19, count 0 2006.201.19:51:14.84#ibcon#about to write, iclass 19, count 0 2006.201.19:51:14.84#ibcon#wrote, iclass 19, count 0 2006.201.19:51:14.84#ibcon#about to read 3, iclass 19, count 0 2006.201.19:51:14.87#ibcon#read 3, iclass 19, count 0 2006.201.19:51:14.87#ibcon#about to read 4, iclass 19, count 0 2006.201.19:51:14.87#ibcon#read 4, iclass 19, count 0 2006.201.19:51:14.87#ibcon#about to read 5, iclass 19, count 0 2006.201.19:51:14.87#ibcon#read 5, iclass 19, count 0 2006.201.19:51:14.87#ibcon#about to read 6, iclass 19, count 0 2006.201.19:51:14.87#ibcon#read 6, iclass 19, count 0 2006.201.19:51:14.87#ibcon#end of sib2, iclass 19, count 0 2006.201.19:51:14.87#ibcon#*after write, iclass 19, count 0 2006.201.19:51:14.87#ibcon#*before return 0, iclass 19, count 0 2006.201.19:51:14.87#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:14.87#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:14.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:51:14.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:51:14.87$vck44/valo=4,624.99 2006.201.19:51:14.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.19:51:14.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.19:51:14.87#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:14.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:14.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:14.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:14.87#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:51:14.87#ibcon#first serial, iclass 21, count 0 2006.201.19:51:14.87#ibcon#enter sib2, iclass 21, count 0 2006.201.19:51:14.87#ibcon#flushed, iclass 21, count 0 2006.201.19:51:14.87#ibcon#about to write, iclass 21, count 0 2006.201.19:51:14.87#ibcon#wrote, iclass 21, count 0 2006.201.19:51:14.87#ibcon#about to read 3, iclass 21, count 0 2006.201.19:51:14.89#ibcon#read 3, iclass 21, count 0 2006.201.19:51:14.89#ibcon#about to read 4, iclass 21, count 0 2006.201.19:51:14.89#ibcon#read 4, iclass 21, count 0 2006.201.19:51:14.89#ibcon#about to read 5, iclass 21, count 0 2006.201.19:51:14.89#ibcon#read 5, iclass 21, count 0 2006.201.19:51:14.89#ibcon#about to read 6, iclass 21, count 0 2006.201.19:51:14.89#ibcon#read 6, iclass 21, count 0 2006.201.19:51:14.89#ibcon#end of sib2, iclass 21, count 0 2006.201.19:51:14.89#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:51:14.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:51:14.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:51:14.89#ibcon#*before write, iclass 21, count 0 2006.201.19:51:14.89#ibcon#enter sib2, iclass 21, count 0 2006.201.19:51:14.89#ibcon#flushed, iclass 21, count 0 2006.201.19:51:14.89#ibcon#about to write, iclass 21, count 0 2006.201.19:51:14.89#ibcon#wrote, iclass 21, count 0 2006.201.19:51:14.89#ibcon#about to read 3, iclass 21, count 0 2006.201.19:51:14.94#ibcon#read 3, iclass 21, count 0 2006.201.19:51:14.94#ibcon#about to read 4, iclass 21, count 0 2006.201.19:51:14.94#ibcon#read 4, iclass 21, count 0 2006.201.19:51:14.94#ibcon#about to read 5, iclass 21, count 0 2006.201.19:51:14.94#ibcon#read 5, iclass 21, count 0 2006.201.19:51:14.94#ibcon#about to read 6, iclass 21, count 0 2006.201.19:51:14.94#ibcon#read 6, iclass 21, count 0 2006.201.19:51:14.94#ibcon#end of sib2, iclass 21, count 0 2006.201.19:51:14.94#ibcon#*after write, iclass 21, count 0 2006.201.19:51:14.94#ibcon#*before return 0, iclass 21, count 0 2006.201.19:51:14.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:14.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:14.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:51:14.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:51:14.94$vck44/va=4,7 2006.201.19:51:14.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.19:51:14.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.19:51:14.94#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:14.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:14.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:14.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:14.99#ibcon#enter wrdev, iclass 23, count 2 2006.201.19:51:14.99#ibcon#first serial, iclass 23, count 2 2006.201.19:51:14.99#ibcon#enter sib2, iclass 23, count 2 2006.201.19:51:14.99#ibcon#flushed, iclass 23, count 2 2006.201.19:51:14.99#ibcon#about to write, iclass 23, count 2 2006.201.19:51:14.99#ibcon#wrote, iclass 23, count 2 2006.201.19:51:14.99#ibcon#about to read 3, iclass 23, count 2 2006.201.19:51:15.01#ibcon#read 3, iclass 23, count 2 2006.201.19:51:15.01#ibcon#about to read 4, iclass 23, count 2 2006.201.19:51:15.01#ibcon#read 4, iclass 23, count 2 2006.201.19:51:15.01#ibcon#about to read 5, iclass 23, count 2 2006.201.19:51:15.01#ibcon#read 5, iclass 23, count 2 2006.201.19:51:15.01#ibcon#about to read 6, iclass 23, count 2 2006.201.19:51:15.01#ibcon#read 6, iclass 23, count 2 2006.201.19:51:15.01#ibcon#end of sib2, iclass 23, count 2 2006.201.19:51:15.01#ibcon#*mode == 0, iclass 23, count 2 2006.201.19:51:15.01#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.19:51:15.01#ibcon#[25=AT04-07\r\n] 2006.201.19:51:15.01#ibcon#*before write, iclass 23, count 2 2006.201.19:51:15.01#ibcon#enter sib2, iclass 23, count 2 2006.201.19:51:15.01#ibcon#flushed, iclass 23, count 2 2006.201.19:51:15.01#ibcon#about to write, iclass 23, count 2 2006.201.19:51:15.01#ibcon#wrote, iclass 23, count 2 2006.201.19:51:15.01#ibcon#about to read 3, iclass 23, count 2 2006.201.19:51:15.04#ibcon#read 3, iclass 23, count 2 2006.201.19:51:15.04#ibcon#about to read 4, iclass 23, count 2 2006.201.19:51:15.04#ibcon#read 4, iclass 23, count 2 2006.201.19:51:15.04#ibcon#about to read 5, iclass 23, count 2 2006.201.19:51:15.04#ibcon#read 5, iclass 23, count 2 2006.201.19:51:15.04#ibcon#about to read 6, iclass 23, count 2 2006.201.19:51:15.04#ibcon#read 6, iclass 23, count 2 2006.201.19:51:15.04#ibcon#end of sib2, iclass 23, count 2 2006.201.19:51:15.04#ibcon#*after write, iclass 23, count 2 2006.201.19:51:15.04#ibcon#*before return 0, iclass 23, count 2 2006.201.19:51:15.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:15.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:15.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.19:51:15.04#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:15.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:15.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:15.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:15.16#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:51:15.16#ibcon#first serial, iclass 23, count 0 2006.201.19:51:15.16#ibcon#enter sib2, iclass 23, count 0 2006.201.19:51:15.16#ibcon#flushed, iclass 23, count 0 2006.201.19:51:15.16#ibcon#about to write, iclass 23, count 0 2006.201.19:51:15.16#ibcon#wrote, iclass 23, count 0 2006.201.19:51:15.16#ibcon#about to read 3, iclass 23, count 0 2006.201.19:51:15.18#ibcon#read 3, iclass 23, count 0 2006.201.19:51:15.18#ibcon#about to read 4, iclass 23, count 0 2006.201.19:51:15.18#ibcon#read 4, iclass 23, count 0 2006.201.19:51:15.18#ibcon#about to read 5, iclass 23, count 0 2006.201.19:51:15.18#ibcon#read 5, iclass 23, count 0 2006.201.19:51:15.18#ibcon#about to read 6, iclass 23, count 0 2006.201.19:51:15.18#ibcon#read 6, iclass 23, count 0 2006.201.19:51:15.18#ibcon#end of sib2, iclass 23, count 0 2006.201.19:51:15.18#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:51:15.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:51:15.18#ibcon#[25=USB\r\n] 2006.201.19:51:15.18#ibcon#*before write, iclass 23, count 0 2006.201.19:51:15.18#ibcon#enter sib2, iclass 23, count 0 2006.201.19:51:15.18#ibcon#flushed, iclass 23, count 0 2006.201.19:51:15.18#ibcon#about to write, iclass 23, count 0 2006.201.19:51:15.18#ibcon#wrote, iclass 23, count 0 2006.201.19:51:15.18#ibcon#about to read 3, iclass 23, count 0 2006.201.19:51:15.21#ibcon#read 3, iclass 23, count 0 2006.201.19:51:15.21#ibcon#about to read 4, iclass 23, count 0 2006.201.19:51:15.21#ibcon#read 4, iclass 23, count 0 2006.201.19:51:15.21#ibcon#about to read 5, iclass 23, count 0 2006.201.19:51:15.21#ibcon#read 5, iclass 23, count 0 2006.201.19:51:15.21#ibcon#about to read 6, iclass 23, count 0 2006.201.19:51:15.21#ibcon#read 6, iclass 23, count 0 2006.201.19:51:15.21#ibcon#end of sib2, iclass 23, count 0 2006.201.19:51:15.21#ibcon#*after write, iclass 23, count 0 2006.201.19:51:15.21#ibcon#*before return 0, iclass 23, count 0 2006.201.19:51:15.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:15.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:15.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:51:15.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:51:15.21$vck44/valo=5,734.99 2006.201.19:51:15.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.19:51:15.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.19:51:15.21#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:15.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:15.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:15.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:15.21#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:51:15.21#ibcon#first serial, iclass 25, count 0 2006.201.19:51:15.21#ibcon#enter sib2, iclass 25, count 0 2006.201.19:51:15.21#ibcon#flushed, iclass 25, count 0 2006.201.19:51:15.21#ibcon#about to write, iclass 25, count 0 2006.201.19:51:15.21#ibcon#wrote, iclass 25, count 0 2006.201.19:51:15.21#ibcon#about to read 3, iclass 25, count 0 2006.201.19:51:15.23#ibcon#read 3, iclass 25, count 0 2006.201.19:51:15.23#ibcon#about to read 4, iclass 25, count 0 2006.201.19:51:15.23#ibcon#read 4, iclass 25, count 0 2006.201.19:51:15.23#ibcon#about to read 5, iclass 25, count 0 2006.201.19:51:15.23#ibcon#read 5, iclass 25, count 0 2006.201.19:51:15.23#ibcon#about to read 6, iclass 25, count 0 2006.201.19:51:15.23#ibcon#read 6, iclass 25, count 0 2006.201.19:51:15.23#ibcon#end of sib2, iclass 25, count 0 2006.201.19:51:15.23#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:51:15.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:51:15.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:51:15.23#ibcon#*before write, iclass 25, count 0 2006.201.19:51:15.23#ibcon#enter sib2, iclass 25, count 0 2006.201.19:51:15.23#ibcon#flushed, iclass 25, count 0 2006.201.19:51:15.23#ibcon#about to write, iclass 25, count 0 2006.201.19:51:15.23#ibcon#wrote, iclass 25, count 0 2006.201.19:51:15.23#ibcon#about to read 3, iclass 25, count 0 2006.201.19:51:15.27#ibcon#read 3, iclass 25, count 0 2006.201.19:51:15.27#ibcon#about to read 4, iclass 25, count 0 2006.201.19:51:15.27#ibcon#read 4, iclass 25, count 0 2006.201.19:51:15.27#ibcon#about to read 5, iclass 25, count 0 2006.201.19:51:15.27#ibcon#read 5, iclass 25, count 0 2006.201.19:51:15.27#ibcon#about to read 6, iclass 25, count 0 2006.201.19:51:15.27#ibcon#read 6, iclass 25, count 0 2006.201.19:51:15.27#ibcon#end of sib2, iclass 25, count 0 2006.201.19:51:15.27#ibcon#*after write, iclass 25, count 0 2006.201.19:51:15.27#ibcon#*before return 0, iclass 25, count 0 2006.201.19:51:15.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:15.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:15.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:51:15.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:51:15.27$vck44/va=5,4 2006.201.19:51:15.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.19:51:15.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.19:51:15.27#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:15.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:15.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:15.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:15.33#ibcon#enter wrdev, iclass 27, count 2 2006.201.19:51:15.33#ibcon#first serial, iclass 27, count 2 2006.201.19:51:15.33#ibcon#enter sib2, iclass 27, count 2 2006.201.19:51:15.33#ibcon#flushed, iclass 27, count 2 2006.201.19:51:15.33#ibcon#about to write, iclass 27, count 2 2006.201.19:51:15.33#ibcon#wrote, iclass 27, count 2 2006.201.19:51:15.33#ibcon#about to read 3, iclass 27, count 2 2006.201.19:51:15.35#ibcon#read 3, iclass 27, count 2 2006.201.19:51:15.35#ibcon#about to read 4, iclass 27, count 2 2006.201.19:51:15.35#ibcon#read 4, iclass 27, count 2 2006.201.19:51:15.35#ibcon#about to read 5, iclass 27, count 2 2006.201.19:51:15.35#ibcon#read 5, iclass 27, count 2 2006.201.19:51:15.35#ibcon#about to read 6, iclass 27, count 2 2006.201.19:51:15.35#ibcon#read 6, iclass 27, count 2 2006.201.19:51:15.35#ibcon#end of sib2, iclass 27, count 2 2006.201.19:51:15.35#ibcon#*mode == 0, iclass 27, count 2 2006.201.19:51:15.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.19:51:15.35#ibcon#[25=AT05-04\r\n] 2006.201.19:51:15.35#ibcon#*before write, iclass 27, count 2 2006.201.19:51:15.35#ibcon#enter sib2, iclass 27, count 2 2006.201.19:51:15.35#ibcon#flushed, iclass 27, count 2 2006.201.19:51:15.35#ibcon#about to write, iclass 27, count 2 2006.201.19:51:15.35#ibcon#wrote, iclass 27, count 2 2006.201.19:51:15.35#ibcon#about to read 3, iclass 27, count 2 2006.201.19:51:15.38#ibcon#read 3, iclass 27, count 2 2006.201.19:51:15.38#ibcon#about to read 4, iclass 27, count 2 2006.201.19:51:15.38#ibcon#read 4, iclass 27, count 2 2006.201.19:51:15.38#ibcon#about to read 5, iclass 27, count 2 2006.201.19:51:15.38#ibcon#read 5, iclass 27, count 2 2006.201.19:51:15.38#ibcon#about to read 6, iclass 27, count 2 2006.201.19:51:15.38#ibcon#read 6, iclass 27, count 2 2006.201.19:51:15.38#ibcon#end of sib2, iclass 27, count 2 2006.201.19:51:15.38#ibcon#*after write, iclass 27, count 2 2006.201.19:51:15.38#ibcon#*before return 0, iclass 27, count 2 2006.201.19:51:15.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:15.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:15.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.19:51:15.38#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:15.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:15.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:15.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:15.50#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:51:15.50#ibcon#first serial, iclass 27, count 0 2006.201.19:51:15.50#ibcon#enter sib2, iclass 27, count 0 2006.201.19:51:15.50#ibcon#flushed, iclass 27, count 0 2006.201.19:51:15.50#ibcon#about to write, iclass 27, count 0 2006.201.19:51:15.50#ibcon#wrote, iclass 27, count 0 2006.201.19:51:15.50#ibcon#about to read 3, iclass 27, count 0 2006.201.19:51:15.52#ibcon#read 3, iclass 27, count 0 2006.201.19:51:15.52#ibcon#about to read 4, iclass 27, count 0 2006.201.19:51:15.52#ibcon#read 4, iclass 27, count 0 2006.201.19:51:15.52#ibcon#about to read 5, iclass 27, count 0 2006.201.19:51:15.52#ibcon#read 5, iclass 27, count 0 2006.201.19:51:15.52#ibcon#about to read 6, iclass 27, count 0 2006.201.19:51:15.52#ibcon#read 6, iclass 27, count 0 2006.201.19:51:15.52#ibcon#end of sib2, iclass 27, count 0 2006.201.19:51:15.52#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:51:15.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:51:15.52#ibcon#[25=USB\r\n] 2006.201.19:51:15.52#ibcon#*before write, iclass 27, count 0 2006.201.19:51:15.52#ibcon#enter sib2, iclass 27, count 0 2006.201.19:51:15.52#ibcon#flushed, iclass 27, count 0 2006.201.19:51:15.52#ibcon#about to write, iclass 27, count 0 2006.201.19:51:15.52#ibcon#wrote, iclass 27, count 0 2006.201.19:51:15.52#ibcon#about to read 3, iclass 27, count 0 2006.201.19:51:15.55#ibcon#read 3, iclass 27, count 0 2006.201.19:51:15.55#ibcon#about to read 4, iclass 27, count 0 2006.201.19:51:15.55#ibcon#read 4, iclass 27, count 0 2006.201.19:51:15.55#ibcon#about to read 5, iclass 27, count 0 2006.201.19:51:15.55#ibcon#read 5, iclass 27, count 0 2006.201.19:51:15.55#ibcon#about to read 6, iclass 27, count 0 2006.201.19:51:15.55#ibcon#read 6, iclass 27, count 0 2006.201.19:51:15.55#ibcon#end of sib2, iclass 27, count 0 2006.201.19:51:15.55#ibcon#*after write, iclass 27, count 0 2006.201.19:51:15.55#ibcon#*before return 0, iclass 27, count 0 2006.201.19:51:15.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:15.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:15.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:51:15.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:51:15.55$vck44/valo=6,814.99 2006.201.19:51:15.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.19:51:15.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.19:51:15.55#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:15.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:15.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:15.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:15.55#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:51:15.55#ibcon#first serial, iclass 29, count 0 2006.201.19:51:15.55#ibcon#enter sib2, iclass 29, count 0 2006.201.19:51:15.55#ibcon#flushed, iclass 29, count 0 2006.201.19:51:15.55#ibcon#about to write, iclass 29, count 0 2006.201.19:51:15.55#ibcon#wrote, iclass 29, count 0 2006.201.19:51:15.55#ibcon#about to read 3, iclass 29, count 0 2006.201.19:51:15.57#ibcon#read 3, iclass 29, count 0 2006.201.19:51:15.57#ibcon#about to read 4, iclass 29, count 0 2006.201.19:51:15.57#ibcon#read 4, iclass 29, count 0 2006.201.19:51:15.57#ibcon#about to read 5, iclass 29, count 0 2006.201.19:51:15.57#ibcon#read 5, iclass 29, count 0 2006.201.19:51:15.57#ibcon#about to read 6, iclass 29, count 0 2006.201.19:51:15.57#ibcon#read 6, iclass 29, count 0 2006.201.19:51:15.57#ibcon#end of sib2, iclass 29, count 0 2006.201.19:51:15.57#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:51:15.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:51:15.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:51:15.57#ibcon#*before write, iclass 29, count 0 2006.201.19:51:15.57#ibcon#enter sib2, iclass 29, count 0 2006.201.19:51:15.57#ibcon#flushed, iclass 29, count 0 2006.201.19:51:15.57#ibcon#about to write, iclass 29, count 0 2006.201.19:51:15.57#ibcon#wrote, iclass 29, count 0 2006.201.19:51:15.57#ibcon#about to read 3, iclass 29, count 0 2006.201.19:51:15.62#ibcon#read 3, iclass 29, count 0 2006.201.19:51:15.62#ibcon#about to read 4, iclass 29, count 0 2006.201.19:51:15.62#ibcon#read 4, iclass 29, count 0 2006.201.19:51:15.62#ibcon#about to read 5, iclass 29, count 0 2006.201.19:51:15.62#ibcon#read 5, iclass 29, count 0 2006.201.19:51:15.62#ibcon#about to read 6, iclass 29, count 0 2006.201.19:51:15.62#ibcon#read 6, iclass 29, count 0 2006.201.19:51:15.62#ibcon#end of sib2, iclass 29, count 0 2006.201.19:51:15.62#ibcon#*after write, iclass 29, count 0 2006.201.19:51:15.62#ibcon#*before return 0, iclass 29, count 0 2006.201.19:51:15.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:15.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:15.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:51:15.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:51:15.62$vck44/va=6,5 2006.201.19:51:15.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.19:51:15.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.19:51:15.62#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:15.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:15.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:15.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:15.67#ibcon#enter wrdev, iclass 31, count 2 2006.201.19:51:15.67#ibcon#first serial, iclass 31, count 2 2006.201.19:51:15.67#ibcon#enter sib2, iclass 31, count 2 2006.201.19:51:15.67#ibcon#flushed, iclass 31, count 2 2006.201.19:51:15.67#ibcon#about to write, iclass 31, count 2 2006.201.19:51:15.67#ibcon#wrote, iclass 31, count 2 2006.201.19:51:15.67#ibcon#about to read 3, iclass 31, count 2 2006.201.19:51:15.69#ibcon#read 3, iclass 31, count 2 2006.201.19:51:15.69#ibcon#about to read 4, iclass 31, count 2 2006.201.19:51:15.69#ibcon#read 4, iclass 31, count 2 2006.201.19:51:15.69#ibcon#about to read 5, iclass 31, count 2 2006.201.19:51:15.69#ibcon#read 5, iclass 31, count 2 2006.201.19:51:15.69#ibcon#about to read 6, iclass 31, count 2 2006.201.19:51:15.69#ibcon#read 6, iclass 31, count 2 2006.201.19:51:15.69#ibcon#end of sib2, iclass 31, count 2 2006.201.19:51:15.69#ibcon#*mode == 0, iclass 31, count 2 2006.201.19:51:15.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.19:51:15.69#ibcon#[25=AT06-05\r\n] 2006.201.19:51:15.69#ibcon#*before write, iclass 31, count 2 2006.201.19:51:15.69#ibcon#enter sib2, iclass 31, count 2 2006.201.19:51:15.69#ibcon#flushed, iclass 31, count 2 2006.201.19:51:15.69#ibcon#about to write, iclass 31, count 2 2006.201.19:51:15.69#ibcon#wrote, iclass 31, count 2 2006.201.19:51:15.69#ibcon#about to read 3, iclass 31, count 2 2006.201.19:51:15.72#ibcon#read 3, iclass 31, count 2 2006.201.19:51:15.72#ibcon#about to read 4, iclass 31, count 2 2006.201.19:51:15.72#ibcon#read 4, iclass 31, count 2 2006.201.19:51:15.72#ibcon#about to read 5, iclass 31, count 2 2006.201.19:51:15.72#ibcon#read 5, iclass 31, count 2 2006.201.19:51:15.72#ibcon#about to read 6, iclass 31, count 2 2006.201.19:51:15.72#ibcon#read 6, iclass 31, count 2 2006.201.19:51:15.72#ibcon#end of sib2, iclass 31, count 2 2006.201.19:51:15.72#ibcon#*after write, iclass 31, count 2 2006.201.19:51:15.72#ibcon#*before return 0, iclass 31, count 2 2006.201.19:51:15.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:15.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:15.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.19:51:15.72#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:15.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:15.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:15.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:15.84#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:51:15.84#ibcon#first serial, iclass 31, count 0 2006.201.19:51:15.84#ibcon#enter sib2, iclass 31, count 0 2006.201.19:51:15.84#ibcon#flushed, iclass 31, count 0 2006.201.19:51:15.84#ibcon#about to write, iclass 31, count 0 2006.201.19:51:15.84#ibcon#wrote, iclass 31, count 0 2006.201.19:51:15.84#ibcon#about to read 3, iclass 31, count 0 2006.201.19:51:15.86#ibcon#read 3, iclass 31, count 0 2006.201.19:51:15.86#ibcon#about to read 4, iclass 31, count 0 2006.201.19:51:15.86#ibcon#read 4, iclass 31, count 0 2006.201.19:51:15.86#ibcon#about to read 5, iclass 31, count 0 2006.201.19:51:15.86#ibcon#read 5, iclass 31, count 0 2006.201.19:51:15.86#ibcon#about to read 6, iclass 31, count 0 2006.201.19:51:15.86#ibcon#read 6, iclass 31, count 0 2006.201.19:51:15.86#ibcon#end of sib2, iclass 31, count 0 2006.201.19:51:15.86#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:51:15.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:51:15.86#ibcon#[25=USB\r\n] 2006.201.19:51:15.86#ibcon#*before write, iclass 31, count 0 2006.201.19:51:15.86#ibcon#enter sib2, iclass 31, count 0 2006.201.19:51:15.86#ibcon#flushed, iclass 31, count 0 2006.201.19:51:15.86#ibcon#about to write, iclass 31, count 0 2006.201.19:51:15.86#ibcon#wrote, iclass 31, count 0 2006.201.19:51:15.86#ibcon#about to read 3, iclass 31, count 0 2006.201.19:51:15.89#ibcon#read 3, iclass 31, count 0 2006.201.19:51:15.89#ibcon#about to read 4, iclass 31, count 0 2006.201.19:51:15.89#ibcon#read 4, iclass 31, count 0 2006.201.19:51:15.89#ibcon#about to read 5, iclass 31, count 0 2006.201.19:51:15.89#ibcon#read 5, iclass 31, count 0 2006.201.19:51:15.89#ibcon#about to read 6, iclass 31, count 0 2006.201.19:51:15.89#ibcon#read 6, iclass 31, count 0 2006.201.19:51:15.89#ibcon#end of sib2, iclass 31, count 0 2006.201.19:51:15.89#ibcon#*after write, iclass 31, count 0 2006.201.19:51:15.89#ibcon#*before return 0, iclass 31, count 0 2006.201.19:51:15.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:15.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:15.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:51:15.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:51:15.89$vck44/valo=7,864.99 2006.201.19:51:15.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.19:51:15.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.19:51:15.89#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:15.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:15.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:15.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:15.89#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:51:15.89#ibcon#first serial, iclass 33, count 0 2006.201.19:51:15.89#ibcon#enter sib2, iclass 33, count 0 2006.201.19:51:15.89#ibcon#flushed, iclass 33, count 0 2006.201.19:51:15.89#ibcon#about to write, iclass 33, count 0 2006.201.19:51:15.89#ibcon#wrote, iclass 33, count 0 2006.201.19:51:15.89#ibcon#about to read 3, iclass 33, count 0 2006.201.19:51:15.91#ibcon#read 3, iclass 33, count 0 2006.201.19:51:15.91#ibcon#about to read 4, iclass 33, count 0 2006.201.19:51:15.91#ibcon#read 4, iclass 33, count 0 2006.201.19:51:15.91#ibcon#about to read 5, iclass 33, count 0 2006.201.19:51:15.91#ibcon#read 5, iclass 33, count 0 2006.201.19:51:15.91#ibcon#about to read 6, iclass 33, count 0 2006.201.19:51:15.91#ibcon#read 6, iclass 33, count 0 2006.201.19:51:15.91#ibcon#end of sib2, iclass 33, count 0 2006.201.19:51:15.91#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:51:15.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:51:15.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:51:15.91#ibcon#*before write, iclass 33, count 0 2006.201.19:51:15.91#ibcon#enter sib2, iclass 33, count 0 2006.201.19:51:15.91#ibcon#flushed, iclass 33, count 0 2006.201.19:51:15.91#ibcon#about to write, iclass 33, count 0 2006.201.19:51:15.91#ibcon#wrote, iclass 33, count 0 2006.201.19:51:15.91#ibcon#about to read 3, iclass 33, count 0 2006.201.19:51:15.95#ibcon#read 3, iclass 33, count 0 2006.201.19:51:15.95#ibcon#about to read 4, iclass 33, count 0 2006.201.19:51:15.95#ibcon#read 4, iclass 33, count 0 2006.201.19:51:15.95#ibcon#about to read 5, iclass 33, count 0 2006.201.19:51:15.95#ibcon#read 5, iclass 33, count 0 2006.201.19:51:15.95#ibcon#about to read 6, iclass 33, count 0 2006.201.19:51:15.95#ibcon#read 6, iclass 33, count 0 2006.201.19:51:15.95#ibcon#end of sib2, iclass 33, count 0 2006.201.19:51:15.95#ibcon#*after write, iclass 33, count 0 2006.201.19:51:15.95#ibcon#*before return 0, iclass 33, count 0 2006.201.19:51:15.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:15.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:15.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:51:15.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:51:15.95$vck44/va=7,5 2006.201.19:51:15.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.19:51:15.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.19:51:15.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:15.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:16.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:16.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:16.01#ibcon#enter wrdev, iclass 35, count 2 2006.201.19:51:16.01#ibcon#first serial, iclass 35, count 2 2006.201.19:51:16.01#ibcon#enter sib2, iclass 35, count 2 2006.201.19:51:16.01#ibcon#flushed, iclass 35, count 2 2006.201.19:51:16.01#ibcon#about to write, iclass 35, count 2 2006.201.19:51:16.01#ibcon#wrote, iclass 35, count 2 2006.201.19:51:16.01#ibcon#about to read 3, iclass 35, count 2 2006.201.19:51:16.03#ibcon#read 3, iclass 35, count 2 2006.201.19:51:16.03#ibcon#about to read 4, iclass 35, count 2 2006.201.19:51:16.03#ibcon#read 4, iclass 35, count 2 2006.201.19:51:16.03#ibcon#about to read 5, iclass 35, count 2 2006.201.19:51:16.03#ibcon#read 5, iclass 35, count 2 2006.201.19:51:16.03#ibcon#about to read 6, iclass 35, count 2 2006.201.19:51:16.03#ibcon#read 6, iclass 35, count 2 2006.201.19:51:16.03#ibcon#end of sib2, iclass 35, count 2 2006.201.19:51:16.03#ibcon#*mode == 0, iclass 35, count 2 2006.201.19:51:16.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.19:51:16.03#ibcon#[25=AT07-05\r\n] 2006.201.19:51:16.03#ibcon#*before write, iclass 35, count 2 2006.201.19:51:16.03#ibcon#enter sib2, iclass 35, count 2 2006.201.19:51:16.03#ibcon#flushed, iclass 35, count 2 2006.201.19:51:16.03#ibcon#about to write, iclass 35, count 2 2006.201.19:51:16.03#ibcon#wrote, iclass 35, count 2 2006.201.19:51:16.03#ibcon#about to read 3, iclass 35, count 2 2006.201.19:51:16.06#ibcon#read 3, iclass 35, count 2 2006.201.19:51:16.06#ibcon#about to read 4, iclass 35, count 2 2006.201.19:51:16.06#ibcon#read 4, iclass 35, count 2 2006.201.19:51:16.06#ibcon#about to read 5, iclass 35, count 2 2006.201.19:51:16.06#ibcon#read 5, iclass 35, count 2 2006.201.19:51:16.06#ibcon#about to read 6, iclass 35, count 2 2006.201.19:51:16.06#ibcon#read 6, iclass 35, count 2 2006.201.19:51:16.06#ibcon#end of sib2, iclass 35, count 2 2006.201.19:51:16.06#ibcon#*after write, iclass 35, count 2 2006.201.19:51:16.06#ibcon#*before return 0, iclass 35, count 2 2006.201.19:51:16.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:16.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:16.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.19:51:16.06#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:16.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:16.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:16.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:16.18#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:51:16.18#ibcon#first serial, iclass 35, count 0 2006.201.19:51:16.18#ibcon#enter sib2, iclass 35, count 0 2006.201.19:51:16.18#ibcon#flushed, iclass 35, count 0 2006.201.19:51:16.18#ibcon#about to write, iclass 35, count 0 2006.201.19:51:16.18#ibcon#wrote, iclass 35, count 0 2006.201.19:51:16.18#ibcon#about to read 3, iclass 35, count 0 2006.201.19:51:16.20#ibcon#read 3, iclass 35, count 0 2006.201.19:51:16.20#ibcon#about to read 4, iclass 35, count 0 2006.201.19:51:16.20#ibcon#read 4, iclass 35, count 0 2006.201.19:51:16.20#ibcon#about to read 5, iclass 35, count 0 2006.201.19:51:16.20#ibcon#read 5, iclass 35, count 0 2006.201.19:51:16.20#ibcon#about to read 6, iclass 35, count 0 2006.201.19:51:16.20#ibcon#read 6, iclass 35, count 0 2006.201.19:51:16.20#ibcon#end of sib2, iclass 35, count 0 2006.201.19:51:16.20#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:51:16.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:51:16.20#ibcon#[25=USB\r\n] 2006.201.19:51:16.20#ibcon#*before write, iclass 35, count 0 2006.201.19:51:16.20#ibcon#enter sib2, iclass 35, count 0 2006.201.19:51:16.20#ibcon#flushed, iclass 35, count 0 2006.201.19:51:16.20#ibcon#about to write, iclass 35, count 0 2006.201.19:51:16.20#ibcon#wrote, iclass 35, count 0 2006.201.19:51:16.20#ibcon#about to read 3, iclass 35, count 0 2006.201.19:51:16.23#ibcon#read 3, iclass 35, count 0 2006.201.19:51:16.23#ibcon#about to read 4, iclass 35, count 0 2006.201.19:51:16.23#ibcon#read 4, iclass 35, count 0 2006.201.19:51:16.23#ibcon#about to read 5, iclass 35, count 0 2006.201.19:51:16.23#ibcon#read 5, iclass 35, count 0 2006.201.19:51:16.23#ibcon#about to read 6, iclass 35, count 0 2006.201.19:51:16.23#ibcon#read 6, iclass 35, count 0 2006.201.19:51:16.23#ibcon#end of sib2, iclass 35, count 0 2006.201.19:51:16.23#ibcon#*after write, iclass 35, count 0 2006.201.19:51:16.23#ibcon#*before return 0, iclass 35, count 0 2006.201.19:51:16.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:16.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:16.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:51:16.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:51:16.23$vck44/valo=8,884.99 2006.201.19:51:16.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.19:51:16.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.19:51:16.23#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:16.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:16.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:16.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:16.23#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:51:16.23#ibcon#first serial, iclass 37, count 0 2006.201.19:51:16.23#ibcon#enter sib2, iclass 37, count 0 2006.201.19:51:16.23#ibcon#flushed, iclass 37, count 0 2006.201.19:51:16.23#ibcon#about to write, iclass 37, count 0 2006.201.19:51:16.23#ibcon#wrote, iclass 37, count 0 2006.201.19:51:16.23#ibcon#about to read 3, iclass 37, count 0 2006.201.19:51:16.25#ibcon#read 3, iclass 37, count 0 2006.201.19:51:16.25#ibcon#about to read 4, iclass 37, count 0 2006.201.19:51:16.25#ibcon#read 4, iclass 37, count 0 2006.201.19:51:16.25#ibcon#about to read 5, iclass 37, count 0 2006.201.19:51:16.25#ibcon#read 5, iclass 37, count 0 2006.201.19:51:16.25#ibcon#about to read 6, iclass 37, count 0 2006.201.19:51:16.25#ibcon#read 6, iclass 37, count 0 2006.201.19:51:16.25#ibcon#end of sib2, iclass 37, count 0 2006.201.19:51:16.25#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:51:16.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:51:16.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:51:16.25#ibcon#*before write, iclass 37, count 0 2006.201.19:51:16.25#ibcon#enter sib2, iclass 37, count 0 2006.201.19:51:16.25#ibcon#flushed, iclass 37, count 0 2006.201.19:51:16.25#ibcon#about to write, iclass 37, count 0 2006.201.19:51:16.25#ibcon#wrote, iclass 37, count 0 2006.201.19:51:16.25#ibcon#about to read 3, iclass 37, count 0 2006.201.19:51:16.29#ibcon#read 3, iclass 37, count 0 2006.201.19:51:16.29#ibcon#about to read 4, iclass 37, count 0 2006.201.19:51:16.29#ibcon#read 4, iclass 37, count 0 2006.201.19:51:16.29#ibcon#about to read 5, iclass 37, count 0 2006.201.19:51:16.29#ibcon#read 5, iclass 37, count 0 2006.201.19:51:16.29#ibcon#about to read 6, iclass 37, count 0 2006.201.19:51:16.29#ibcon#read 6, iclass 37, count 0 2006.201.19:51:16.29#ibcon#end of sib2, iclass 37, count 0 2006.201.19:51:16.29#ibcon#*after write, iclass 37, count 0 2006.201.19:51:16.29#ibcon#*before return 0, iclass 37, count 0 2006.201.19:51:16.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:16.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:16.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:51:16.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:51:16.29$vck44/va=8,4 2006.201.19:51:16.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.19:51:16.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.19:51:16.29#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:16.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:51:16.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:51:16.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:51:16.35#ibcon#enter wrdev, iclass 39, count 2 2006.201.19:51:16.35#ibcon#first serial, iclass 39, count 2 2006.201.19:51:16.35#ibcon#enter sib2, iclass 39, count 2 2006.201.19:51:16.35#ibcon#flushed, iclass 39, count 2 2006.201.19:51:16.35#ibcon#about to write, iclass 39, count 2 2006.201.19:51:16.35#ibcon#wrote, iclass 39, count 2 2006.201.19:51:16.35#ibcon#about to read 3, iclass 39, count 2 2006.201.19:51:16.37#ibcon#read 3, iclass 39, count 2 2006.201.19:51:16.37#ibcon#about to read 4, iclass 39, count 2 2006.201.19:51:16.37#ibcon#read 4, iclass 39, count 2 2006.201.19:51:16.37#ibcon#about to read 5, iclass 39, count 2 2006.201.19:51:16.37#ibcon#read 5, iclass 39, count 2 2006.201.19:51:16.37#ibcon#about to read 6, iclass 39, count 2 2006.201.19:51:16.37#ibcon#read 6, iclass 39, count 2 2006.201.19:51:16.37#ibcon#end of sib2, iclass 39, count 2 2006.201.19:51:16.37#ibcon#*mode == 0, iclass 39, count 2 2006.201.19:51:16.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.19:51:16.37#ibcon#[25=AT08-04\r\n] 2006.201.19:51:16.37#ibcon#*before write, iclass 39, count 2 2006.201.19:51:16.37#ibcon#enter sib2, iclass 39, count 2 2006.201.19:51:16.37#ibcon#flushed, iclass 39, count 2 2006.201.19:51:16.37#ibcon#about to write, iclass 39, count 2 2006.201.19:51:16.37#ibcon#wrote, iclass 39, count 2 2006.201.19:51:16.37#ibcon#about to read 3, iclass 39, count 2 2006.201.19:51:16.40#ibcon#read 3, iclass 39, count 2 2006.201.19:51:16.40#ibcon#about to read 4, iclass 39, count 2 2006.201.19:51:16.40#ibcon#read 4, iclass 39, count 2 2006.201.19:51:16.40#ibcon#about to read 5, iclass 39, count 2 2006.201.19:51:16.40#ibcon#read 5, iclass 39, count 2 2006.201.19:51:16.40#ibcon#about to read 6, iclass 39, count 2 2006.201.19:51:16.40#ibcon#read 6, iclass 39, count 2 2006.201.19:51:16.40#ibcon#end of sib2, iclass 39, count 2 2006.201.19:51:16.40#ibcon#*after write, iclass 39, count 2 2006.201.19:51:16.40#ibcon#*before return 0, iclass 39, count 2 2006.201.19:51:16.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:51:16.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.19:51:16.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.19:51:16.40#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:16.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:51:16.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:51:16.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:51:16.52#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:51:16.52#ibcon#first serial, iclass 39, count 0 2006.201.19:51:16.52#ibcon#enter sib2, iclass 39, count 0 2006.201.19:51:16.52#ibcon#flushed, iclass 39, count 0 2006.201.19:51:16.52#ibcon#about to write, iclass 39, count 0 2006.201.19:51:16.52#ibcon#wrote, iclass 39, count 0 2006.201.19:51:16.52#ibcon#about to read 3, iclass 39, count 0 2006.201.19:51:16.54#ibcon#read 3, iclass 39, count 0 2006.201.19:51:16.54#ibcon#about to read 4, iclass 39, count 0 2006.201.19:51:16.54#ibcon#read 4, iclass 39, count 0 2006.201.19:51:16.54#ibcon#about to read 5, iclass 39, count 0 2006.201.19:51:16.54#ibcon#read 5, iclass 39, count 0 2006.201.19:51:16.54#ibcon#about to read 6, iclass 39, count 0 2006.201.19:51:16.54#ibcon#read 6, iclass 39, count 0 2006.201.19:51:16.54#ibcon#end of sib2, iclass 39, count 0 2006.201.19:51:16.54#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:51:16.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:51:16.54#ibcon#[25=USB\r\n] 2006.201.19:51:16.54#ibcon#*before write, iclass 39, count 0 2006.201.19:51:16.54#ibcon#enter sib2, iclass 39, count 0 2006.201.19:51:16.54#ibcon#flushed, iclass 39, count 0 2006.201.19:51:16.54#ibcon#about to write, iclass 39, count 0 2006.201.19:51:16.54#ibcon#wrote, iclass 39, count 0 2006.201.19:51:16.54#ibcon#about to read 3, iclass 39, count 0 2006.201.19:51:16.57#ibcon#read 3, iclass 39, count 0 2006.201.19:51:16.57#ibcon#about to read 4, iclass 39, count 0 2006.201.19:51:16.57#ibcon#read 4, iclass 39, count 0 2006.201.19:51:16.57#ibcon#about to read 5, iclass 39, count 0 2006.201.19:51:16.57#ibcon#read 5, iclass 39, count 0 2006.201.19:51:16.57#ibcon#about to read 6, iclass 39, count 0 2006.201.19:51:16.57#ibcon#read 6, iclass 39, count 0 2006.201.19:51:16.57#ibcon#end of sib2, iclass 39, count 0 2006.201.19:51:16.57#ibcon#*after write, iclass 39, count 0 2006.201.19:51:16.57#ibcon#*before return 0, iclass 39, count 0 2006.201.19:51:16.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:51:16.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.19:51:16.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:51:16.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:51:16.57$vck44/vblo=1,629.99 2006.201.19:51:16.57#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.19:51:16.57#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.19:51:16.57#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:16.57#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:51:16.57#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:51:16.57#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:51:16.57#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:51:16.57#ibcon#first serial, iclass 2, count 0 2006.201.19:51:16.57#ibcon#enter sib2, iclass 2, count 0 2006.201.19:51:16.57#ibcon#flushed, iclass 2, count 0 2006.201.19:51:16.57#ibcon#about to write, iclass 2, count 0 2006.201.19:51:16.57#ibcon#wrote, iclass 2, count 0 2006.201.19:51:16.57#ibcon#about to read 3, iclass 2, count 0 2006.201.19:51:16.59#ibcon#read 3, iclass 2, count 0 2006.201.19:51:16.59#ibcon#about to read 4, iclass 2, count 0 2006.201.19:51:16.59#ibcon#read 4, iclass 2, count 0 2006.201.19:51:16.59#ibcon#about to read 5, iclass 2, count 0 2006.201.19:51:16.59#ibcon#read 5, iclass 2, count 0 2006.201.19:51:16.59#ibcon#about to read 6, iclass 2, count 0 2006.201.19:51:16.59#ibcon#read 6, iclass 2, count 0 2006.201.19:51:16.59#ibcon#end of sib2, iclass 2, count 0 2006.201.19:51:16.59#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:51:16.59#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:51:16.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:51:16.59#ibcon#*before write, iclass 2, count 0 2006.201.19:51:16.59#ibcon#enter sib2, iclass 2, count 0 2006.201.19:51:16.59#ibcon#flushed, iclass 2, count 0 2006.201.19:51:16.59#ibcon#about to write, iclass 2, count 0 2006.201.19:51:16.59#ibcon#wrote, iclass 2, count 0 2006.201.19:51:16.59#ibcon#about to read 3, iclass 2, count 0 2006.201.19:51:16.64#ibcon#read 3, iclass 2, count 0 2006.201.19:51:16.64#ibcon#about to read 4, iclass 2, count 0 2006.201.19:51:16.64#ibcon#read 4, iclass 2, count 0 2006.201.19:51:16.64#ibcon#about to read 5, iclass 2, count 0 2006.201.19:51:16.64#ibcon#read 5, iclass 2, count 0 2006.201.19:51:16.64#ibcon#about to read 6, iclass 2, count 0 2006.201.19:51:16.64#ibcon#read 6, iclass 2, count 0 2006.201.19:51:16.64#ibcon#end of sib2, iclass 2, count 0 2006.201.19:51:16.64#ibcon#*after write, iclass 2, count 0 2006.201.19:51:16.64#ibcon#*before return 0, iclass 2, count 0 2006.201.19:51:16.64#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:51:16.64#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.19:51:16.64#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:51:16.64#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:51:16.64$vck44/vb=1,4 2006.201.19:51:16.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.19:51:16.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.19:51:16.64#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:16.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:51:16.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:51:16.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:51:16.64#ibcon#enter wrdev, iclass 5, count 2 2006.201.19:51:16.64#ibcon#first serial, iclass 5, count 2 2006.201.19:51:16.64#ibcon#enter sib2, iclass 5, count 2 2006.201.19:51:16.64#ibcon#flushed, iclass 5, count 2 2006.201.19:51:16.64#ibcon#about to write, iclass 5, count 2 2006.201.19:51:16.64#ibcon#wrote, iclass 5, count 2 2006.201.19:51:16.64#ibcon#about to read 3, iclass 5, count 2 2006.201.19:51:16.66#ibcon#read 3, iclass 5, count 2 2006.201.19:51:16.66#ibcon#about to read 4, iclass 5, count 2 2006.201.19:51:16.66#ibcon#read 4, iclass 5, count 2 2006.201.19:51:16.66#ibcon#about to read 5, iclass 5, count 2 2006.201.19:51:16.66#ibcon#read 5, iclass 5, count 2 2006.201.19:51:16.66#ibcon#about to read 6, iclass 5, count 2 2006.201.19:51:16.66#ibcon#read 6, iclass 5, count 2 2006.201.19:51:16.66#ibcon#end of sib2, iclass 5, count 2 2006.201.19:51:16.66#ibcon#*mode == 0, iclass 5, count 2 2006.201.19:51:16.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.19:51:16.66#ibcon#[27=AT01-04\r\n] 2006.201.19:51:16.66#ibcon#*before write, iclass 5, count 2 2006.201.19:51:16.66#ibcon#enter sib2, iclass 5, count 2 2006.201.19:51:16.66#ibcon#flushed, iclass 5, count 2 2006.201.19:51:16.66#ibcon#about to write, iclass 5, count 2 2006.201.19:51:16.66#ibcon#wrote, iclass 5, count 2 2006.201.19:51:16.66#ibcon#about to read 3, iclass 5, count 2 2006.201.19:51:16.69#ibcon#read 3, iclass 5, count 2 2006.201.19:51:16.69#ibcon#about to read 4, iclass 5, count 2 2006.201.19:51:16.69#ibcon#read 4, iclass 5, count 2 2006.201.19:51:16.69#ibcon#about to read 5, iclass 5, count 2 2006.201.19:51:16.69#ibcon#read 5, iclass 5, count 2 2006.201.19:51:16.69#ibcon#about to read 6, iclass 5, count 2 2006.201.19:51:16.69#ibcon#read 6, iclass 5, count 2 2006.201.19:51:16.69#ibcon#end of sib2, iclass 5, count 2 2006.201.19:51:16.69#ibcon#*after write, iclass 5, count 2 2006.201.19:51:16.69#ibcon#*before return 0, iclass 5, count 2 2006.201.19:51:16.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:51:16.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.19:51:16.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.19:51:16.69#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:16.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:51:16.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:51:16.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:51:16.81#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:51:16.81#ibcon#first serial, iclass 5, count 0 2006.201.19:51:16.81#ibcon#enter sib2, iclass 5, count 0 2006.201.19:51:16.81#ibcon#flushed, iclass 5, count 0 2006.201.19:51:16.81#ibcon#about to write, iclass 5, count 0 2006.201.19:51:16.81#ibcon#wrote, iclass 5, count 0 2006.201.19:51:16.81#ibcon#about to read 3, iclass 5, count 0 2006.201.19:51:16.83#ibcon#read 3, iclass 5, count 0 2006.201.19:51:16.83#ibcon#about to read 4, iclass 5, count 0 2006.201.19:51:16.83#ibcon#read 4, iclass 5, count 0 2006.201.19:51:16.83#ibcon#about to read 5, iclass 5, count 0 2006.201.19:51:16.83#ibcon#read 5, iclass 5, count 0 2006.201.19:51:16.83#ibcon#about to read 6, iclass 5, count 0 2006.201.19:51:16.83#ibcon#read 6, iclass 5, count 0 2006.201.19:51:16.83#ibcon#end of sib2, iclass 5, count 0 2006.201.19:51:16.83#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:51:16.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:51:16.83#ibcon#[27=USB\r\n] 2006.201.19:51:16.83#ibcon#*before write, iclass 5, count 0 2006.201.19:51:16.83#ibcon#enter sib2, iclass 5, count 0 2006.201.19:51:16.83#ibcon#flushed, iclass 5, count 0 2006.201.19:51:16.83#ibcon#about to write, iclass 5, count 0 2006.201.19:51:16.83#ibcon#wrote, iclass 5, count 0 2006.201.19:51:16.83#ibcon#about to read 3, iclass 5, count 0 2006.201.19:51:16.86#ibcon#read 3, iclass 5, count 0 2006.201.19:51:16.86#ibcon#about to read 4, iclass 5, count 0 2006.201.19:51:16.86#ibcon#read 4, iclass 5, count 0 2006.201.19:51:16.86#ibcon#about to read 5, iclass 5, count 0 2006.201.19:51:16.86#ibcon#read 5, iclass 5, count 0 2006.201.19:51:16.86#ibcon#about to read 6, iclass 5, count 0 2006.201.19:51:16.86#ibcon#read 6, iclass 5, count 0 2006.201.19:51:16.86#ibcon#end of sib2, iclass 5, count 0 2006.201.19:51:16.86#ibcon#*after write, iclass 5, count 0 2006.201.19:51:16.86#ibcon#*before return 0, iclass 5, count 0 2006.201.19:51:16.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:51:16.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.19:51:16.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:51:16.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:51:16.86$vck44/vblo=2,634.99 2006.201.19:51:16.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.19:51:16.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.19:51:16.86#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:16.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:16.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:16.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:16.86#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:51:16.86#ibcon#first serial, iclass 7, count 0 2006.201.19:51:16.86#ibcon#enter sib2, iclass 7, count 0 2006.201.19:51:16.86#ibcon#flushed, iclass 7, count 0 2006.201.19:51:16.86#ibcon#about to write, iclass 7, count 0 2006.201.19:51:16.86#ibcon#wrote, iclass 7, count 0 2006.201.19:51:16.86#ibcon#about to read 3, iclass 7, count 0 2006.201.19:51:16.88#ibcon#read 3, iclass 7, count 0 2006.201.19:51:16.88#ibcon#about to read 4, iclass 7, count 0 2006.201.19:51:16.88#ibcon#read 4, iclass 7, count 0 2006.201.19:51:16.88#ibcon#about to read 5, iclass 7, count 0 2006.201.19:51:16.88#ibcon#read 5, iclass 7, count 0 2006.201.19:51:16.88#ibcon#about to read 6, iclass 7, count 0 2006.201.19:51:16.88#ibcon#read 6, iclass 7, count 0 2006.201.19:51:16.88#ibcon#end of sib2, iclass 7, count 0 2006.201.19:51:16.88#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:51:16.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:51:16.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:51:16.88#ibcon#*before write, iclass 7, count 0 2006.201.19:51:16.88#ibcon#enter sib2, iclass 7, count 0 2006.201.19:51:16.88#ibcon#flushed, iclass 7, count 0 2006.201.19:51:16.88#ibcon#about to write, iclass 7, count 0 2006.201.19:51:16.88#ibcon#wrote, iclass 7, count 0 2006.201.19:51:16.88#ibcon#about to read 3, iclass 7, count 0 2006.201.19:51:16.92#ibcon#read 3, iclass 7, count 0 2006.201.19:51:16.92#ibcon#about to read 4, iclass 7, count 0 2006.201.19:51:16.92#ibcon#read 4, iclass 7, count 0 2006.201.19:51:16.92#ibcon#about to read 5, iclass 7, count 0 2006.201.19:51:16.92#ibcon#read 5, iclass 7, count 0 2006.201.19:51:16.92#ibcon#about to read 6, iclass 7, count 0 2006.201.19:51:16.92#ibcon#read 6, iclass 7, count 0 2006.201.19:51:16.92#ibcon#end of sib2, iclass 7, count 0 2006.201.19:51:16.92#ibcon#*after write, iclass 7, count 0 2006.201.19:51:16.92#ibcon#*before return 0, iclass 7, count 0 2006.201.19:51:16.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:16.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.19:51:16.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:51:16.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:51:16.92$vck44/vb=2,5 2006.201.19:51:16.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.19:51:16.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.19:51:16.92#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:16.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:16.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:16.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:16.98#ibcon#enter wrdev, iclass 11, count 2 2006.201.19:51:16.98#ibcon#first serial, iclass 11, count 2 2006.201.19:51:16.98#ibcon#enter sib2, iclass 11, count 2 2006.201.19:51:16.98#ibcon#flushed, iclass 11, count 2 2006.201.19:51:16.98#ibcon#about to write, iclass 11, count 2 2006.201.19:51:16.98#ibcon#wrote, iclass 11, count 2 2006.201.19:51:16.98#ibcon#about to read 3, iclass 11, count 2 2006.201.19:51:17.00#ibcon#read 3, iclass 11, count 2 2006.201.19:51:17.00#ibcon#about to read 4, iclass 11, count 2 2006.201.19:51:17.00#ibcon#read 4, iclass 11, count 2 2006.201.19:51:17.00#ibcon#about to read 5, iclass 11, count 2 2006.201.19:51:17.00#ibcon#read 5, iclass 11, count 2 2006.201.19:51:17.00#ibcon#about to read 6, iclass 11, count 2 2006.201.19:51:17.00#ibcon#read 6, iclass 11, count 2 2006.201.19:51:17.00#ibcon#end of sib2, iclass 11, count 2 2006.201.19:51:17.00#ibcon#*mode == 0, iclass 11, count 2 2006.201.19:51:17.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.19:51:17.00#ibcon#[27=AT02-05\r\n] 2006.201.19:51:17.00#ibcon#*before write, iclass 11, count 2 2006.201.19:51:17.00#ibcon#enter sib2, iclass 11, count 2 2006.201.19:51:17.00#ibcon#flushed, iclass 11, count 2 2006.201.19:51:17.00#ibcon#about to write, iclass 11, count 2 2006.201.19:51:17.00#ibcon#wrote, iclass 11, count 2 2006.201.19:51:17.00#ibcon#about to read 3, iclass 11, count 2 2006.201.19:51:17.03#ibcon#read 3, iclass 11, count 2 2006.201.19:51:17.03#ibcon#about to read 4, iclass 11, count 2 2006.201.19:51:17.03#ibcon#read 4, iclass 11, count 2 2006.201.19:51:17.03#ibcon#about to read 5, iclass 11, count 2 2006.201.19:51:17.03#ibcon#read 5, iclass 11, count 2 2006.201.19:51:17.03#ibcon#about to read 6, iclass 11, count 2 2006.201.19:51:17.03#ibcon#read 6, iclass 11, count 2 2006.201.19:51:17.03#ibcon#end of sib2, iclass 11, count 2 2006.201.19:51:17.03#ibcon#*after write, iclass 11, count 2 2006.201.19:51:17.03#ibcon#*before return 0, iclass 11, count 2 2006.201.19:51:17.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:17.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.19:51:17.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.19:51:17.03#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:17.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:17.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:17.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:17.15#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:51:17.15#ibcon#first serial, iclass 11, count 0 2006.201.19:51:17.15#ibcon#enter sib2, iclass 11, count 0 2006.201.19:51:17.15#ibcon#flushed, iclass 11, count 0 2006.201.19:51:17.15#ibcon#about to write, iclass 11, count 0 2006.201.19:51:17.15#ibcon#wrote, iclass 11, count 0 2006.201.19:51:17.15#ibcon#about to read 3, iclass 11, count 0 2006.201.19:51:17.17#ibcon#read 3, iclass 11, count 0 2006.201.19:51:17.17#ibcon#about to read 4, iclass 11, count 0 2006.201.19:51:17.17#ibcon#read 4, iclass 11, count 0 2006.201.19:51:17.17#ibcon#about to read 5, iclass 11, count 0 2006.201.19:51:17.17#ibcon#read 5, iclass 11, count 0 2006.201.19:51:17.17#ibcon#about to read 6, iclass 11, count 0 2006.201.19:51:17.17#ibcon#read 6, iclass 11, count 0 2006.201.19:51:17.17#ibcon#end of sib2, iclass 11, count 0 2006.201.19:51:17.17#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:51:17.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:51:17.17#ibcon#[27=USB\r\n] 2006.201.19:51:17.17#ibcon#*before write, iclass 11, count 0 2006.201.19:51:17.17#ibcon#enter sib2, iclass 11, count 0 2006.201.19:51:17.17#ibcon#flushed, iclass 11, count 0 2006.201.19:51:17.17#ibcon#about to write, iclass 11, count 0 2006.201.19:51:17.17#ibcon#wrote, iclass 11, count 0 2006.201.19:51:17.17#ibcon#about to read 3, iclass 11, count 0 2006.201.19:51:17.20#ibcon#read 3, iclass 11, count 0 2006.201.19:51:17.20#ibcon#about to read 4, iclass 11, count 0 2006.201.19:51:17.20#ibcon#read 4, iclass 11, count 0 2006.201.19:51:17.20#ibcon#about to read 5, iclass 11, count 0 2006.201.19:51:17.20#ibcon#read 5, iclass 11, count 0 2006.201.19:51:17.20#ibcon#about to read 6, iclass 11, count 0 2006.201.19:51:17.20#ibcon#read 6, iclass 11, count 0 2006.201.19:51:17.20#ibcon#end of sib2, iclass 11, count 0 2006.201.19:51:17.20#ibcon#*after write, iclass 11, count 0 2006.201.19:51:17.20#ibcon#*before return 0, iclass 11, count 0 2006.201.19:51:17.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:17.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.19:51:17.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:51:17.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:51:17.20$vck44/vblo=3,649.99 2006.201.19:51:17.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.19:51:17.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.19:51:17.20#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:17.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:17.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:17.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:17.20#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:51:17.20#ibcon#first serial, iclass 13, count 0 2006.201.19:51:17.20#ibcon#enter sib2, iclass 13, count 0 2006.201.19:51:17.20#ibcon#flushed, iclass 13, count 0 2006.201.19:51:17.20#ibcon#about to write, iclass 13, count 0 2006.201.19:51:17.20#ibcon#wrote, iclass 13, count 0 2006.201.19:51:17.20#ibcon#about to read 3, iclass 13, count 0 2006.201.19:51:17.22#ibcon#read 3, iclass 13, count 0 2006.201.19:51:17.22#ibcon#about to read 4, iclass 13, count 0 2006.201.19:51:17.22#ibcon#read 4, iclass 13, count 0 2006.201.19:51:17.22#ibcon#about to read 5, iclass 13, count 0 2006.201.19:51:17.22#ibcon#read 5, iclass 13, count 0 2006.201.19:51:17.22#ibcon#about to read 6, iclass 13, count 0 2006.201.19:51:17.22#ibcon#read 6, iclass 13, count 0 2006.201.19:51:17.22#ibcon#end of sib2, iclass 13, count 0 2006.201.19:51:17.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:51:17.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:51:17.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:51:17.22#ibcon#*before write, iclass 13, count 0 2006.201.19:51:17.22#ibcon#enter sib2, iclass 13, count 0 2006.201.19:51:17.22#ibcon#flushed, iclass 13, count 0 2006.201.19:51:17.22#ibcon#about to write, iclass 13, count 0 2006.201.19:51:17.22#ibcon#wrote, iclass 13, count 0 2006.201.19:51:17.22#ibcon#about to read 3, iclass 13, count 0 2006.201.19:51:17.26#ibcon#read 3, iclass 13, count 0 2006.201.19:51:17.26#ibcon#about to read 4, iclass 13, count 0 2006.201.19:51:17.26#ibcon#read 4, iclass 13, count 0 2006.201.19:51:17.26#ibcon#about to read 5, iclass 13, count 0 2006.201.19:51:17.26#ibcon#read 5, iclass 13, count 0 2006.201.19:51:17.26#ibcon#about to read 6, iclass 13, count 0 2006.201.19:51:17.26#ibcon#read 6, iclass 13, count 0 2006.201.19:51:17.26#ibcon#end of sib2, iclass 13, count 0 2006.201.19:51:17.26#ibcon#*after write, iclass 13, count 0 2006.201.19:51:17.26#ibcon#*before return 0, iclass 13, count 0 2006.201.19:51:17.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:17.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:51:17.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:51:17.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:51:17.26$vck44/vb=3,4 2006.201.19:51:17.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.19:51:17.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.19:51:17.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:17.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:17.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:17.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:17.32#ibcon#enter wrdev, iclass 15, count 2 2006.201.19:51:17.32#ibcon#first serial, iclass 15, count 2 2006.201.19:51:17.32#ibcon#enter sib2, iclass 15, count 2 2006.201.19:51:17.32#ibcon#flushed, iclass 15, count 2 2006.201.19:51:17.32#ibcon#about to write, iclass 15, count 2 2006.201.19:51:17.32#ibcon#wrote, iclass 15, count 2 2006.201.19:51:17.32#ibcon#about to read 3, iclass 15, count 2 2006.201.19:51:17.34#ibcon#read 3, iclass 15, count 2 2006.201.19:51:17.34#ibcon#about to read 4, iclass 15, count 2 2006.201.19:51:17.34#ibcon#read 4, iclass 15, count 2 2006.201.19:51:17.34#ibcon#about to read 5, iclass 15, count 2 2006.201.19:51:17.34#ibcon#read 5, iclass 15, count 2 2006.201.19:51:17.34#ibcon#about to read 6, iclass 15, count 2 2006.201.19:51:17.34#ibcon#read 6, iclass 15, count 2 2006.201.19:51:17.34#ibcon#end of sib2, iclass 15, count 2 2006.201.19:51:17.34#ibcon#*mode == 0, iclass 15, count 2 2006.201.19:51:17.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.19:51:17.34#ibcon#[27=AT03-04\r\n] 2006.201.19:51:17.34#ibcon#*before write, iclass 15, count 2 2006.201.19:51:17.34#ibcon#enter sib2, iclass 15, count 2 2006.201.19:51:17.34#ibcon#flushed, iclass 15, count 2 2006.201.19:51:17.34#ibcon#about to write, iclass 15, count 2 2006.201.19:51:17.34#ibcon#wrote, iclass 15, count 2 2006.201.19:51:17.34#ibcon#about to read 3, iclass 15, count 2 2006.201.19:51:17.37#ibcon#read 3, iclass 15, count 2 2006.201.19:51:17.37#ibcon#about to read 4, iclass 15, count 2 2006.201.19:51:17.37#ibcon#read 4, iclass 15, count 2 2006.201.19:51:17.37#ibcon#about to read 5, iclass 15, count 2 2006.201.19:51:17.37#ibcon#read 5, iclass 15, count 2 2006.201.19:51:17.37#ibcon#about to read 6, iclass 15, count 2 2006.201.19:51:17.37#ibcon#read 6, iclass 15, count 2 2006.201.19:51:17.37#ibcon#end of sib2, iclass 15, count 2 2006.201.19:51:17.37#ibcon#*after write, iclass 15, count 2 2006.201.19:51:17.37#ibcon#*before return 0, iclass 15, count 2 2006.201.19:51:17.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:17.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.19:51:17.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.19:51:17.37#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:17.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:17.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:17.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:17.49#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:51:17.49#ibcon#first serial, iclass 15, count 0 2006.201.19:51:17.49#ibcon#enter sib2, iclass 15, count 0 2006.201.19:51:17.49#ibcon#flushed, iclass 15, count 0 2006.201.19:51:17.49#ibcon#about to write, iclass 15, count 0 2006.201.19:51:17.49#ibcon#wrote, iclass 15, count 0 2006.201.19:51:17.49#ibcon#about to read 3, iclass 15, count 0 2006.201.19:51:17.51#ibcon#read 3, iclass 15, count 0 2006.201.19:51:17.51#ibcon#about to read 4, iclass 15, count 0 2006.201.19:51:17.51#ibcon#read 4, iclass 15, count 0 2006.201.19:51:17.51#ibcon#about to read 5, iclass 15, count 0 2006.201.19:51:17.51#ibcon#read 5, iclass 15, count 0 2006.201.19:51:17.51#ibcon#about to read 6, iclass 15, count 0 2006.201.19:51:17.51#ibcon#read 6, iclass 15, count 0 2006.201.19:51:17.51#ibcon#end of sib2, iclass 15, count 0 2006.201.19:51:17.51#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:51:17.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:51:17.51#ibcon#[27=USB\r\n] 2006.201.19:51:17.51#ibcon#*before write, iclass 15, count 0 2006.201.19:51:17.51#ibcon#enter sib2, iclass 15, count 0 2006.201.19:51:17.51#ibcon#flushed, iclass 15, count 0 2006.201.19:51:17.51#ibcon#about to write, iclass 15, count 0 2006.201.19:51:17.51#ibcon#wrote, iclass 15, count 0 2006.201.19:51:17.51#ibcon#about to read 3, iclass 15, count 0 2006.201.19:51:17.54#ibcon#read 3, iclass 15, count 0 2006.201.19:51:17.54#ibcon#about to read 4, iclass 15, count 0 2006.201.19:51:17.54#ibcon#read 4, iclass 15, count 0 2006.201.19:51:17.54#ibcon#about to read 5, iclass 15, count 0 2006.201.19:51:17.54#ibcon#read 5, iclass 15, count 0 2006.201.19:51:17.54#ibcon#about to read 6, iclass 15, count 0 2006.201.19:51:17.54#ibcon#read 6, iclass 15, count 0 2006.201.19:51:17.54#ibcon#end of sib2, iclass 15, count 0 2006.201.19:51:17.54#ibcon#*after write, iclass 15, count 0 2006.201.19:51:17.54#ibcon#*before return 0, iclass 15, count 0 2006.201.19:51:17.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:17.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.19:51:17.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:51:17.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:51:17.54$vck44/vblo=4,679.99 2006.201.19:51:17.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.19:51:17.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.19:51:17.54#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:17.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:17.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:17.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:17.54#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:51:17.54#ibcon#first serial, iclass 17, count 0 2006.201.19:51:17.54#ibcon#enter sib2, iclass 17, count 0 2006.201.19:51:17.54#ibcon#flushed, iclass 17, count 0 2006.201.19:51:17.54#ibcon#about to write, iclass 17, count 0 2006.201.19:51:17.54#ibcon#wrote, iclass 17, count 0 2006.201.19:51:17.54#ibcon#about to read 3, iclass 17, count 0 2006.201.19:51:17.56#ibcon#read 3, iclass 17, count 0 2006.201.19:51:17.56#ibcon#about to read 4, iclass 17, count 0 2006.201.19:51:17.56#ibcon#read 4, iclass 17, count 0 2006.201.19:51:17.56#ibcon#about to read 5, iclass 17, count 0 2006.201.19:51:17.56#ibcon#read 5, iclass 17, count 0 2006.201.19:51:17.56#ibcon#about to read 6, iclass 17, count 0 2006.201.19:51:17.56#ibcon#read 6, iclass 17, count 0 2006.201.19:51:17.56#ibcon#end of sib2, iclass 17, count 0 2006.201.19:51:17.56#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:51:17.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:51:17.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:51:17.56#ibcon#*before write, iclass 17, count 0 2006.201.19:51:17.56#ibcon#enter sib2, iclass 17, count 0 2006.201.19:51:17.56#ibcon#flushed, iclass 17, count 0 2006.201.19:51:17.56#ibcon#about to write, iclass 17, count 0 2006.201.19:51:17.56#ibcon#wrote, iclass 17, count 0 2006.201.19:51:17.56#ibcon#about to read 3, iclass 17, count 0 2006.201.19:51:17.61#ibcon#read 3, iclass 17, count 0 2006.201.19:51:17.61#ibcon#about to read 4, iclass 17, count 0 2006.201.19:51:17.61#ibcon#read 4, iclass 17, count 0 2006.201.19:51:17.61#ibcon#about to read 5, iclass 17, count 0 2006.201.19:51:17.61#ibcon#read 5, iclass 17, count 0 2006.201.19:51:17.61#ibcon#about to read 6, iclass 17, count 0 2006.201.19:51:17.61#ibcon#read 6, iclass 17, count 0 2006.201.19:51:17.61#ibcon#end of sib2, iclass 17, count 0 2006.201.19:51:17.61#ibcon#*after write, iclass 17, count 0 2006.201.19:51:17.61#ibcon#*before return 0, iclass 17, count 0 2006.201.19:51:17.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:17.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.19:51:17.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:51:17.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:51:17.61$vck44/vb=4,5 2006.201.19:51:17.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.19:51:17.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.19:51:17.61#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:17.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:17.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:17.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:17.66#ibcon#enter wrdev, iclass 19, count 2 2006.201.19:51:17.66#ibcon#first serial, iclass 19, count 2 2006.201.19:51:17.66#ibcon#enter sib2, iclass 19, count 2 2006.201.19:51:17.66#ibcon#flushed, iclass 19, count 2 2006.201.19:51:17.66#ibcon#about to write, iclass 19, count 2 2006.201.19:51:17.66#ibcon#wrote, iclass 19, count 2 2006.201.19:51:17.66#ibcon#about to read 3, iclass 19, count 2 2006.201.19:51:17.68#ibcon#read 3, iclass 19, count 2 2006.201.19:51:17.68#ibcon#about to read 4, iclass 19, count 2 2006.201.19:51:17.68#ibcon#read 4, iclass 19, count 2 2006.201.19:51:17.68#ibcon#about to read 5, iclass 19, count 2 2006.201.19:51:17.68#ibcon#read 5, iclass 19, count 2 2006.201.19:51:17.68#ibcon#about to read 6, iclass 19, count 2 2006.201.19:51:17.68#ibcon#read 6, iclass 19, count 2 2006.201.19:51:17.68#ibcon#end of sib2, iclass 19, count 2 2006.201.19:51:17.68#ibcon#*mode == 0, iclass 19, count 2 2006.201.19:51:17.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.19:51:17.68#ibcon#[27=AT04-05\r\n] 2006.201.19:51:17.68#ibcon#*before write, iclass 19, count 2 2006.201.19:51:17.68#ibcon#enter sib2, iclass 19, count 2 2006.201.19:51:17.68#ibcon#flushed, iclass 19, count 2 2006.201.19:51:17.68#ibcon#about to write, iclass 19, count 2 2006.201.19:51:17.68#ibcon#wrote, iclass 19, count 2 2006.201.19:51:17.68#ibcon#about to read 3, iclass 19, count 2 2006.201.19:51:17.71#ibcon#read 3, iclass 19, count 2 2006.201.19:51:17.71#ibcon#about to read 4, iclass 19, count 2 2006.201.19:51:17.71#ibcon#read 4, iclass 19, count 2 2006.201.19:51:17.71#ibcon#about to read 5, iclass 19, count 2 2006.201.19:51:17.71#ibcon#read 5, iclass 19, count 2 2006.201.19:51:17.71#ibcon#about to read 6, iclass 19, count 2 2006.201.19:51:17.71#ibcon#read 6, iclass 19, count 2 2006.201.19:51:17.71#ibcon#end of sib2, iclass 19, count 2 2006.201.19:51:17.71#ibcon#*after write, iclass 19, count 2 2006.201.19:51:17.71#ibcon#*before return 0, iclass 19, count 2 2006.201.19:51:17.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:17.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.19:51:17.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.19:51:17.71#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:17.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:17.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:17.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:17.83#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:51:17.83#ibcon#first serial, iclass 19, count 0 2006.201.19:51:17.83#ibcon#enter sib2, iclass 19, count 0 2006.201.19:51:17.83#ibcon#flushed, iclass 19, count 0 2006.201.19:51:17.83#ibcon#about to write, iclass 19, count 0 2006.201.19:51:17.83#ibcon#wrote, iclass 19, count 0 2006.201.19:51:17.83#ibcon#about to read 3, iclass 19, count 0 2006.201.19:51:17.85#ibcon#read 3, iclass 19, count 0 2006.201.19:51:17.85#ibcon#about to read 4, iclass 19, count 0 2006.201.19:51:17.85#ibcon#read 4, iclass 19, count 0 2006.201.19:51:17.85#ibcon#about to read 5, iclass 19, count 0 2006.201.19:51:17.85#ibcon#read 5, iclass 19, count 0 2006.201.19:51:17.85#ibcon#about to read 6, iclass 19, count 0 2006.201.19:51:17.85#ibcon#read 6, iclass 19, count 0 2006.201.19:51:17.85#ibcon#end of sib2, iclass 19, count 0 2006.201.19:51:17.85#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:51:17.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:51:17.85#ibcon#[27=USB\r\n] 2006.201.19:51:17.85#ibcon#*before write, iclass 19, count 0 2006.201.19:51:17.85#ibcon#enter sib2, iclass 19, count 0 2006.201.19:51:17.85#ibcon#flushed, iclass 19, count 0 2006.201.19:51:17.85#ibcon#about to write, iclass 19, count 0 2006.201.19:51:17.85#ibcon#wrote, iclass 19, count 0 2006.201.19:51:17.85#ibcon#about to read 3, iclass 19, count 0 2006.201.19:51:17.88#ibcon#read 3, iclass 19, count 0 2006.201.19:51:17.88#ibcon#about to read 4, iclass 19, count 0 2006.201.19:51:17.88#ibcon#read 4, iclass 19, count 0 2006.201.19:51:17.88#ibcon#about to read 5, iclass 19, count 0 2006.201.19:51:17.88#ibcon#read 5, iclass 19, count 0 2006.201.19:51:17.88#ibcon#about to read 6, iclass 19, count 0 2006.201.19:51:17.88#ibcon#read 6, iclass 19, count 0 2006.201.19:51:17.88#ibcon#end of sib2, iclass 19, count 0 2006.201.19:51:17.88#ibcon#*after write, iclass 19, count 0 2006.201.19:51:17.88#ibcon#*before return 0, iclass 19, count 0 2006.201.19:51:17.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:17.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.19:51:17.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:51:17.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:51:17.88$vck44/vblo=5,709.99 2006.201.19:51:17.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.19:51:17.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.19:51:17.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:17.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:17.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:17.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:17.88#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:51:17.88#ibcon#first serial, iclass 21, count 0 2006.201.19:51:17.88#ibcon#enter sib2, iclass 21, count 0 2006.201.19:51:17.88#ibcon#flushed, iclass 21, count 0 2006.201.19:51:17.88#ibcon#about to write, iclass 21, count 0 2006.201.19:51:17.88#ibcon#wrote, iclass 21, count 0 2006.201.19:51:17.88#ibcon#about to read 3, iclass 21, count 0 2006.201.19:51:17.90#ibcon#read 3, iclass 21, count 0 2006.201.19:51:17.90#ibcon#about to read 4, iclass 21, count 0 2006.201.19:51:17.90#ibcon#read 4, iclass 21, count 0 2006.201.19:51:17.90#ibcon#about to read 5, iclass 21, count 0 2006.201.19:51:17.90#ibcon#read 5, iclass 21, count 0 2006.201.19:51:17.90#ibcon#about to read 6, iclass 21, count 0 2006.201.19:51:17.90#ibcon#read 6, iclass 21, count 0 2006.201.19:51:17.90#ibcon#end of sib2, iclass 21, count 0 2006.201.19:51:17.90#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:51:17.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:51:17.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:51:17.90#ibcon#*before write, iclass 21, count 0 2006.201.19:51:17.90#ibcon#enter sib2, iclass 21, count 0 2006.201.19:51:17.90#ibcon#flushed, iclass 21, count 0 2006.201.19:51:17.90#ibcon#about to write, iclass 21, count 0 2006.201.19:51:17.90#ibcon#wrote, iclass 21, count 0 2006.201.19:51:17.90#ibcon#about to read 3, iclass 21, count 0 2006.201.19:51:17.94#ibcon#read 3, iclass 21, count 0 2006.201.19:51:17.94#ibcon#about to read 4, iclass 21, count 0 2006.201.19:51:17.94#ibcon#read 4, iclass 21, count 0 2006.201.19:51:17.94#ibcon#about to read 5, iclass 21, count 0 2006.201.19:51:17.94#ibcon#read 5, iclass 21, count 0 2006.201.19:51:17.94#ibcon#about to read 6, iclass 21, count 0 2006.201.19:51:17.94#ibcon#read 6, iclass 21, count 0 2006.201.19:51:17.94#ibcon#end of sib2, iclass 21, count 0 2006.201.19:51:17.94#ibcon#*after write, iclass 21, count 0 2006.201.19:51:17.94#ibcon#*before return 0, iclass 21, count 0 2006.201.19:51:17.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:17.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.19:51:17.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:51:17.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:51:17.94$vck44/vb=5,4 2006.201.19:51:17.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.19:51:17.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.19:51:17.94#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:17.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:18.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:18.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:18.00#ibcon#enter wrdev, iclass 23, count 2 2006.201.19:51:18.00#ibcon#first serial, iclass 23, count 2 2006.201.19:51:18.00#ibcon#enter sib2, iclass 23, count 2 2006.201.19:51:18.00#ibcon#flushed, iclass 23, count 2 2006.201.19:51:18.00#ibcon#about to write, iclass 23, count 2 2006.201.19:51:18.00#ibcon#wrote, iclass 23, count 2 2006.201.19:51:18.00#ibcon#about to read 3, iclass 23, count 2 2006.201.19:51:18.02#ibcon#read 3, iclass 23, count 2 2006.201.19:51:18.02#ibcon#about to read 4, iclass 23, count 2 2006.201.19:51:18.02#ibcon#read 4, iclass 23, count 2 2006.201.19:51:18.02#ibcon#about to read 5, iclass 23, count 2 2006.201.19:51:18.02#ibcon#read 5, iclass 23, count 2 2006.201.19:51:18.02#ibcon#about to read 6, iclass 23, count 2 2006.201.19:51:18.02#ibcon#read 6, iclass 23, count 2 2006.201.19:51:18.02#ibcon#end of sib2, iclass 23, count 2 2006.201.19:51:18.02#ibcon#*mode == 0, iclass 23, count 2 2006.201.19:51:18.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.19:51:18.02#ibcon#[27=AT05-04\r\n] 2006.201.19:51:18.02#ibcon#*before write, iclass 23, count 2 2006.201.19:51:18.02#ibcon#enter sib2, iclass 23, count 2 2006.201.19:51:18.02#ibcon#flushed, iclass 23, count 2 2006.201.19:51:18.02#ibcon#about to write, iclass 23, count 2 2006.201.19:51:18.02#ibcon#wrote, iclass 23, count 2 2006.201.19:51:18.02#ibcon#about to read 3, iclass 23, count 2 2006.201.19:51:18.05#ibcon#read 3, iclass 23, count 2 2006.201.19:51:18.05#ibcon#about to read 4, iclass 23, count 2 2006.201.19:51:18.05#ibcon#read 4, iclass 23, count 2 2006.201.19:51:18.05#ibcon#about to read 5, iclass 23, count 2 2006.201.19:51:18.05#ibcon#read 5, iclass 23, count 2 2006.201.19:51:18.05#ibcon#about to read 6, iclass 23, count 2 2006.201.19:51:18.05#ibcon#read 6, iclass 23, count 2 2006.201.19:51:18.05#ibcon#end of sib2, iclass 23, count 2 2006.201.19:51:18.05#ibcon#*after write, iclass 23, count 2 2006.201.19:51:18.05#ibcon#*before return 0, iclass 23, count 2 2006.201.19:51:18.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:18.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.19:51:18.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.19:51:18.05#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:18.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:18.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:18.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:18.17#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:51:18.17#ibcon#first serial, iclass 23, count 0 2006.201.19:51:18.17#ibcon#enter sib2, iclass 23, count 0 2006.201.19:51:18.17#ibcon#flushed, iclass 23, count 0 2006.201.19:51:18.17#ibcon#about to write, iclass 23, count 0 2006.201.19:51:18.17#ibcon#wrote, iclass 23, count 0 2006.201.19:51:18.17#ibcon#about to read 3, iclass 23, count 0 2006.201.19:51:18.20#ibcon#read 3, iclass 23, count 0 2006.201.19:51:18.20#ibcon#about to read 4, iclass 23, count 0 2006.201.19:51:18.20#ibcon#read 4, iclass 23, count 0 2006.201.19:51:18.20#ibcon#about to read 5, iclass 23, count 0 2006.201.19:51:18.20#ibcon#read 5, iclass 23, count 0 2006.201.19:51:18.20#ibcon#about to read 6, iclass 23, count 0 2006.201.19:51:18.20#ibcon#read 6, iclass 23, count 0 2006.201.19:51:18.20#ibcon#end of sib2, iclass 23, count 0 2006.201.19:51:18.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:51:18.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:51:18.20#ibcon#[27=USB\r\n] 2006.201.19:51:18.20#ibcon#*before write, iclass 23, count 0 2006.201.19:51:18.20#ibcon#enter sib2, iclass 23, count 0 2006.201.19:51:18.20#ibcon#flushed, iclass 23, count 0 2006.201.19:51:18.20#ibcon#about to write, iclass 23, count 0 2006.201.19:51:18.20#ibcon#wrote, iclass 23, count 0 2006.201.19:51:18.20#ibcon#about to read 3, iclass 23, count 0 2006.201.19:51:18.23#ibcon#read 3, iclass 23, count 0 2006.201.19:51:18.23#ibcon#about to read 4, iclass 23, count 0 2006.201.19:51:18.23#ibcon#read 4, iclass 23, count 0 2006.201.19:51:18.23#ibcon#about to read 5, iclass 23, count 0 2006.201.19:51:18.23#ibcon#read 5, iclass 23, count 0 2006.201.19:51:18.23#ibcon#about to read 6, iclass 23, count 0 2006.201.19:51:18.23#ibcon#read 6, iclass 23, count 0 2006.201.19:51:18.23#ibcon#end of sib2, iclass 23, count 0 2006.201.19:51:18.23#ibcon#*after write, iclass 23, count 0 2006.201.19:51:18.23#ibcon#*before return 0, iclass 23, count 0 2006.201.19:51:18.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:18.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.19:51:18.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:51:18.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:51:18.23$vck44/vblo=6,719.99 2006.201.19:51:18.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.19:51:18.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.19:51:18.23#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:18.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:18.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:18.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:18.23#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:51:18.23#ibcon#first serial, iclass 25, count 0 2006.201.19:51:18.23#ibcon#enter sib2, iclass 25, count 0 2006.201.19:51:18.23#ibcon#flushed, iclass 25, count 0 2006.201.19:51:18.23#ibcon#about to write, iclass 25, count 0 2006.201.19:51:18.23#ibcon#wrote, iclass 25, count 0 2006.201.19:51:18.23#ibcon#about to read 3, iclass 25, count 0 2006.201.19:51:18.25#ibcon#read 3, iclass 25, count 0 2006.201.19:51:18.25#ibcon#about to read 4, iclass 25, count 0 2006.201.19:51:18.25#ibcon#read 4, iclass 25, count 0 2006.201.19:51:18.25#ibcon#about to read 5, iclass 25, count 0 2006.201.19:51:18.25#ibcon#read 5, iclass 25, count 0 2006.201.19:51:18.25#ibcon#about to read 6, iclass 25, count 0 2006.201.19:51:18.25#ibcon#read 6, iclass 25, count 0 2006.201.19:51:18.25#ibcon#end of sib2, iclass 25, count 0 2006.201.19:51:18.25#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:51:18.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:51:18.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:51:18.25#ibcon#*before write, iclass 25, count 0 2006.201.19:51:18.25#ibcon#enter sib2, iclass 25, count 0 2006.201.19:51:18.25#ibcon#flushed, iclass 25, count 0 2006.201.19:51:18.25#ibcon#about to write, iclass 25, count 0 2006.201.19:51:18.25#ibcon#wrote, iclass 25, count 0 2006.201.19:51:18.25#ibcon#about to read 3, iclass 25, count 0 2006.201.19:51:18.29#ibcon#read 3, iclass 25, count 0 2006.201.19:51:18.29#ibcon#about to read 4, iclass 25, count 0 2006.201.19:51:18.29#ibcon#read 4, iclass 25, count 0 2006.201.19:51:18.29#ibcon#about to read 5, iclass 25, count 0 2006.201.19:51:18.29#ibcon#read 5, iclass 25, count 0 2006.201.19:51:18.29#ibcon#about to read 6, iclass 25, count 0 2006.201.19:51:18.29#ibcon#read 6, iclass 25, count 0 2006.201.19:51:18.29#ibcon#end of sib2, iclass 25, count 0 2006.201.19:51:18.29#ibcon#*after write, iclass 25, count 0 2006.201.19:51:18.29#ibcon#*before return 0, iclass 25, count 0 2006.201.19:51:18.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:18.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.19:51:18.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:51:18.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:51:18.29$vck44/vb=6,4 2006.201.19:51:18.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.19:51:18.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.19:51:18.29#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:18.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:18.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:18.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:18.35#ibcon#enter wrdev, iclass 27, count 2 2006.201.19:51:18.35#ibcon#first serial, iclass 27, count 2 2006.201.19:51:18.35#ibcon#enter sib2, iclass 27, count 2 2006.201.19:51:18.35#ibcon#flushed, iclass 27, count 2 2006.201.19:51:18.35#ibcon#about to write, iclass 27, count 2 2006.201.19:51:18.35#ibcon#wrote, iclass 27, count 2 2006.201.19:51:18.35#ibcon#about to read 3, iclass 27, count 2 2006.201.19:51:18.37#ibcon#read 3, iclass 27, count 2 2006.201.19:51:18.37#ibcon#about to read 4, iclass 27, count 2 2006.201.19:51:18.37#ibcon#read 4, iclass 27, count 2 2006.201.19:51:18.37#ibcon#about to read 5, iclass 27, count 2 2006.201.19:51:18.37#ibcon#read 5, iclass 27, count 2 2006.201.19:51:18.37#ibcon#about to read 6, iclass 27, count 2 2006.201.19:51:18.37#ibcon#read 6, iclass 27, count 2 2006.201.19:51:18.37#ibcon#end of sib2, iclass 27, count 2 2006.201.19:51:18.37#ibcon#*mode == 0, iclass 27, count 2 2006.201.19:51:18.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.19:51:18.37#ibcon#[27=AT06-04\r\n] 2006.201.19:51:18.37#ibcon#*before write, iclass 27, count 2 2006.201.19:51:18.37#ibcon#enter sib2, iclass 27, count 2 2006.201.19:51:18.37#ibcon#flushed, iclass 27, count 2 2006.201.19:51:18.37#ibcon#about to write, iclass 27, count 2 2006.201.19:51:18.37#ibcon#wrote, iclass 27, count 2 2006.201.19:51:18.37#ibcon#about to read 3, iclass 27, count 2 2006.201.19:51:18.40#ibcon#read 3, iclass 27, count 2 2006.201.19:51:18.40#ibcon#about to read 4, iclass 27, count 2 2006.201.19:51:18.40#ibcon#read 4, iclass 27, count 2 2006.201.19:51:18.40#ibcon#about to read 5, iclass 27, count 2 2006.201.19:51:18.40#ibcon#read 5, iclass 27, count 2 2006.201.19:51:18.40#ibcon#about to read 6, iclass 27, count 2 2006.201.19:51:18.40#ibcon#read 6, iclass 27, count 2 2006.201.19:51:18.40#ibcon#end of sib2, iclass 27, count 2 2006.201.19:51:18.40#ibcon#*after write, iclass 27, count 2 2006.201.19:51:18.40#ibcon#*before return 0, iclass 27, count 2 2006.201.19:51:18.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:18.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.19:51:18.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.19:51:18.40#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:18.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:18.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:18.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:18.52#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:51:18.52#ibcon#first serial, iclass 27, count 0 2006.201.19:51:18.52#ibcon#enter sib2, iclass 27, count 0 2006.201.19:51:18.52#ibcon#flushed, iclass 27, count 0 2006.201.19:51:18.52#ibcon#about to write, iclass 27, count 0 2006.201.19:51:18.52#ibcon#wrote, iclass 27, count 0 2006.201.19:51:18.52#ibcon#about to read 3, iclass 27, count 0 2006.201.19:51:18.54#ibcon#read 3, iclass 27, count 0 2006.201.19:51:18.54#ibcon#about to read 4, iclass 27, count 0 2006.201.19:51:18.54#ibcon#read 4, iclass 27, count 0 2006.201.19:51:18.54#ibcon#about to read 5, iclass 27, count 0 2006.201.19:51:18.54#ibcon#read 5, iclass 27, count 0 2006.201.19:51:18.54#ibcon#about to read 6, iclass 27, count 0 2006.201.19:51:18.54#ibcon#read 6, iclass 27, count 0 2006.201.19:51:18.54#ibcon#end of sib2, iclass 27, count 0 2006.201.19:51:18.54#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:51:18.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:51:18.54#ibcon#[27=USB\r\n] 2006.201.19:51:18.54#ibcon#*before write, iclass 27, count 0 2006.201.19:51:18.54#ibcon#enter sib2, iclass 27, count 0 2006.201.19:51:18.54#ibcon#flushed, iclass 27, count 0 2006.201.19:51:18.54#ibcon#about to write, iclass 27, count 0 2006.201.19:51:18.54#ibcon#wrote, iclass 27, count 0 2006.201.19:51:18.54#ibcon#about to read 3, iclass 27, count 0 2006.201.19:51:18.57#ibcon#read 3, iclass 27, count 0 2006.201.19:51:18.57#ibcon#about to read 4, iclass 27, count 0 2006.201.19:51:18.57#ibcon#read 4, iclass 27, count 0 2006.201.19:51:18.57#ibcon#about to read 5, iclass 27, count 0 2006.201.19:51:18.57#ibcon#read 5, iclass 27, count 0 2006.201.19:51:18.57#ibcon#about to read 6, iclass 27, count 0 2006.201.19:51:18.57#ibcon#read 6, iclass 27, count 0 2006.201.19:51:18.57#ibcon#end of sib2, iclass 27, count 0 2006.201.19:51:18.57#ibcon#*after write, iclass 27, count 0 2006.201.19:51:18.57#ibcon#*before return 0, iclass 27, count 0 2006.201.19:51:18.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:18.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.19:51:18.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:51:18.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:51:18.57$vck44/vblo=7,734.99 2006.201.19:51:18.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.19:51:18.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.19:51:18.57#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:18.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:18.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:18.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:18.57#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:51:18.57#ibcon#first serial, iclass 29, count 0 2006.201.19:51:18.57#ibcon#enter sib2, iclass 29, count 0 2006.201.19:51:18.57#ibcon#flushed, iclass 29, count 0 2006.201.19:51:18.57#ibcon#about to write, iclass 29, count 0 2006.201.19:51:18.57#ibcon#wrote, iclass 29, count 0 2006.201.19:51:18.57#ibcon#about to read 3, iclass 29, count 0 2006.201.19:51:18.59#ibcon#read 3, iclass 29, count 0 2006.201.19:51:18.59#ibcon#about to read 4, iclass 29, count 0 2006.201.19:51:18.59#ibcon#read 4, iclass 29, count 0 2006.201.19:51:18.59#ibcon#about to read 5, iclass 29, count 0 2006.201.19:51:18.59#ibcon#read 5, iclass 29, count 0 2006.201.19:51:18.59#ibcon#about to read 6, iclass 29, count 0 2006.201.19:51:18.59#ibcon#read 6, iclass 29, count 0 2006.201.19:51:18.59#ibcon#end of sib2, iclass 29, count 0 2006.201.19:51:18.59#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:51:18.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:51:18.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:51:18.59#ibcon#*before write, iclass 29, count 0 2006.201.19:51:18.59#ibcon#enter sib2, iclass 29, count 0 2006.201.19:51:18.59#ibcon#flushed, iclass 29, count 0 2006.201.19:51:18.59#ibcon#about to write, iclass 29, count 0 2006.201.19:51:18.59#ibcon#wrote, iclass 29, count 0 2006.201.19:51:18.59#ibcon#about to read 3, iclass 29, count 0 2006.201.19:51:18.63#ibcon#read 3, iclass 29, count 0 2006.201.19:51:18.63#ibcon#about to read 4, iclass 29, count 0 2006.201.19:51:18.63#ibcon#read 4, iclass 29, count 0 2006.201.19:51:18.63#ibcon#about to read 5, iclass 29, count 0 2006.201.19:51:18.63#ibcon#read 5, iclass 29, count 0 2006.201.19:51:18.63#ibcon#about to read 6, iclass 29, count 0 2006.201.19:51:18.63#ibcon#read 6, iclass 29, count 0 2006.201.19:51:18.63#ibcon#end of sib2, iclass 29, count 0 2006.201.19:51:18.63#ibcon#*after write, iclass 29, count 0 2006.201.19:51:18.63#ibcon#*before return 0, iclass 29, count 0 2006.201.19:51:18.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:18.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.19:51:18.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:51:18.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:51:18.63$vck44/vb=7,4 2006.201.19:51:18.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.19:51:18.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.19:51:18.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:18.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:18.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:18.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:18.69#ibcon#enter wrdev, iclass 31, count 2 2006.201.19:51:18.69#ibcon#first serial, iclass 31, count 2 2006.201.19:51:18.69#ibcon#enter sib2, iclass 31, count 2 2006.201.19:51:18.69#ibcon#flushed, iclass 31, count 2 2006.201.19:51:18.69#ibcon#about to write, iclass 31, count 2 2006.201.19:51:18.69#ibcon#wrote, iclass 31, count 2 2006.201.19:51:18.69#ibcon#about to read 3, iclass 31, count 2 2006.201.19:51:18.71#ibcon#read 3, iclass 31, count 2 2006.201.19:51:18.71#ibcon#about to read 4, iclass 31, count 2 2006.201.19:51:18.71#ibcon#read 4, iclass 31, count 2 2006.201.19:51:18.71#ibcon#about to read 5, iclass 31, count 2 2006.201.19:51:18.71#ibcon#read 5, iclass 31, count 2 2006.201.19:51:18.71#ibcon#about to read 6, iclass 31, count 2 2006.201.19:51:18.71#ibcon#read 6, iclass 31, count 2 2006.201.19:51:18.71#ibcon#end of sib2, iclass 31, count 2 2006.201.19:51:18.71#ibcon#*mode == 0, iclass 31, count 2 2006.201.19:51:18.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.19:51:18.71#ibcon#[27=AT07-04\r\n] 2006.201.19:51:18.71#ibcon#*before write, iclass 31, count 2 2006.201.19:51:18.71#ibcon#enter sib2, iclass 31, count 2 2006.201.19:51:18.71#ibcon#flushed, iclass 31, count 2 2006.201.19:51:18.71#ibcon#about to write, iclass 31, count 2 2006.201.19:51:18.71#ibcon#wrote, iclass 31, count 2 2006.201.19:51:18.71#ibcon#about to read 3, iclass 31, count 2 2006.201.19:51:18.74#ibcon#read 3, iclass 31, count 2 2006.201.19:51:18.74#ibcon#about to read 4, iclass 31, count 2 2006.201.19:51:18.74#ibcon#read 4, iclass 31, count 2 2006.201.19:51:18.74#ibcon#about to read 5, iclass 31, count 2 2006.201.19:51:18.74#ibcon#read 5, iclass 31, count 2 2006.201.19:51:18.74#ibcon#about to read 6, iclass 31, count 2 2006.201.19:51:18.74#ibcon#read 6, iclass 31, count 2 2006.201.19:51:18.74#ibcon#end of sib2, iclass 31, count 2 2006.201.19:51:18.74#ibcon#*after write, iclass 31, count 2 2006.201.19:51:18.74#ibcon#*before return 0, iclass 31, count 2 2006.201.19:51:18.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:18.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.19:51:18.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.19:51:18.74#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:18.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:18.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:18.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:18.86#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:51:18.86#ibcon#first serial, iclass 31, count 0 2006.201.19:51:18.86#ibcon#enter sib2, iclass 31, count 0 2006.201.19:51:18.86#ibcon#flushed, iclass 31, count 0 2006.201.19:51:18.86#ibcon#about to write, iclass 31, count 0 2006.201.19:51:18.86#ibcon#wrote, iclass 31, count 0 2006.201.19:51:18.86#ibcon#about to read 3, iclass 31, count 0 2006.201.19:51:18.88#ibcon#read 3, iclass 31, count 0 2006.201.19:51:18.88#ibcon#about to read 4, iclass 31, count 0 2006.201.19:51:18.88#ibcon#read 4, iclass 31, count 0 2006.201.19:51:18.88#ibcon#about to read 5, iclass 31, count 0 2006.201.19:51:18.88#ibcon#read 5, iclass 31, count 0 2006.201.19:51:18.88#ibcon#about to read 6, iclass 31, count 0 2006.201.19:51:18.88#ibcon#read 6, iclass 31, count 0 2006.201.19:51:18.88#ibcon#end of sib2, iclass 31, count 0 2006.201.19:51:18.88#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:51:18.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:51:18.88#ibcon#[27=USB\r\n] 2006.201.19:51:18.88#ibcon#*before write, iclass 31, count 0 2006.201.19:51:18.88#ibcon#enter sib2, iclass 31, count 0 2006.201.19:51:18.88#ibcon#flushed, iclass 31, count 0 2006.201.19:51:18.88#ibcon#about to write, iclass 31, count 0 2006.201.19:51:18.88#ibcon#wrote, iclass 31, count 0 2006.201.19:51:18.88#ibcon#about to read 3, iclass 31, count 0 2006.201.19:51:18.91#ibcon#read 3, iclass 31, count 0 2006.201.19:51:18.91#ibcon#about to read 4, iclass 31, count 0 2006.201.19:51:18.91#ibcon#read 4, iclass 31, count 0 2006.201.19:51:18.91#ibcon#about to read 5, iclass 31, count 0 2006.201.19:51:18.91#ibcon#read 5, iclass 31, count 0 2006.201.19:51:18.91#ibcon#about to read 6, iclass 31, count 0 2006.201.19:51:18.91#ibcon#read 6, iclass 31, count 0 2006.201.19:51:18.91#ibcon#end of sib2, iclass 31, count 0 2006.201.19:51:18.91#ibcon#*after write, iclass 31, count 0 2006.201.19:51:18.91#ibcon#*before return 0, iclass 31, count 0 2006.201.19:51:18.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:18.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.19:51:18.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:51:18.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:51:18.91$vck44/vblo=8,744.99 2006.201.19:51:18.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.19:51:18.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.19:51:18.91#ibcon#ireg 17 cls_cnt 0 2006.201.19:51:18.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:18.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:18.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:18.91#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:51:18.91#ibcon#first serial, iclass 33, count 0 2006.201.19:51:18.91#ibcon#enter sib2, iclass 33, count 0 2006.201.19:51:18.91#ibcon#flushed, iclass 33, count 0 2006.201.19:51:18.91#ibcon#about to write, iclass 33, count 0 2006.201.19:51:18.91#ibcon#wrote, iclass 33, count 0 2006.201.19:51:18.91#ibcon#about to read 3, iclass 33, count 0 2006.201.19:51:18.93#ibcon#read 3, iclass 33, count 0 2006.201.19:51:18.93#ibcon#about to read 4, iclass 33, count 0 2006.201.19:51:18.93#ibcon#read 4, iclass 33, count 0 2006.201.19:51:18.93#ibcon#about to read 5, iclass 33, count 0 2006.201.19:51:18.93#ibcon#read 5, iclass 33, count 0 2006.201.19:51:18.93#ibcon#about to read 6, iclass 33, count 0 2006.201.19:51:18.93#ibcon#read 6, iclass 33, count 0 2006.201.19:51:18.93#ibcon#end of sib2, iclass 33, count 0 2006.201.19:51:18.93#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:51:18.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:51:18.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:51:18.93#ibcon#*before write, iclass 33, count 0 2006.201.19:51:18.93#ibcon#enter sib2, iclass 33, count 0 2006.201.19:51:18.93#ibcon#flushed, iclass 33, count 0 2006.201.19:51:18.93#ibcon#about to write, iclass 33, count 0 2006.201.19:51:18.93#ibcon#wrote, iclass 33, count 0 2006.201.19:51:18.93#ibcon#about to read 3, iclass 33, count 0 2006.201.19:51:18.98#ibcon#read 3, iclass 33, count 0 2006.201.19:51:18.98#ibcon#about to read 4, iclass 33, count 0 2006.201.19:51:18.98#ibcon#read 4, iclass 33, count 0 2006.201.19:51:18.98#ibcon#about to read 5, iclass 33, count 0 2006.201.19:51:18.98#ibcon#read 5, iclass 33, count 0 2006.201.19:51:18.98#ibcon#about to read 6, iclass 33, count 0 2006.201.19:51:18.98#ibcon#read 6, iclass 33, count 0 2006.201.19:51:18.98#ibcon#end of sib2, iclass 33, count 0 2006.201.19:51:18.98#ibcon#*after write, iclass 33, count 0 2006.201.19:51:18.98#ibcon#*before return 0, iclass 33, count 0 2006.201.19:51:18.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:18.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.19:51:18.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:51:18.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:51:18.98$vck44/vb=8,4 2006.201.19:51:18.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.19:51:18.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.19:51:18.98#ibcon#ireg 11 cls_cnt 2 2006.201.19:51:18.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:19.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:19.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:19.03#ibcon#enter wrdev, iclass 35, count 2 2006.201.19:51:19.03#ibcon#first serial, iclass 35, count 2 2006.201.19:51:19.03#ibcon#enter sib2, iclass 35, count 2 2006.201.19:51:19.03#ibcon#flushed, iclass 35, count 2 2006.201.19:51:19.03#ibcon#about to write, iclass 35, count 2 2006.201.19:51:19.03#ibcon#wrote, iclass 35, count 2 2006.201.19:51:19.03#ibcon#about to read 3, iclass 35, count 2 2006.201.19:51:19.05#ibcon#read 3, iclass 35, count 2 2006.201.19:51:19.05#ibcon#about to read 4, iclass 35, count 2 2006.201.19:51:19.05#ibcon#read 4, iclass 35, count 2 2006.201.19:51:19.05#ibcon#about to read 5, iclass 35, count 2 2006.201.19:51:19.05#ibcon#read 5, iclass 35, count 2 2006.201.19:51:19.05#ibcon#about to read 6, iclass 35, count 2 2006.201.19:51:19.05#ibcon#read 6, iclass 35, count 2 2006.201.19:51:19.05#ibcon#end of sib2, iclass 35, count 2 2006.201.19:51:19.05#ibcon#*mode == 0, iclass 35, count 2 2006.201.19:51:19.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.19:51:19.05#ibcon#[27=AT08-04\r\n] 2006.201.19:51:19.05#ibcon#*before write, iclass 35, count 2 2006.201.19:51:19.05#ibcon#enter sib2, iclass 35, count 2 2006.201.19:51:19.05#ibcon#flushed, iclass 35, count 2 2006.201.19:51:19.05#ibcon#about to write, iclass 35, count 2 2006.201.19:51:19.05#ibcon#wrote, iclass 35, count 2 2006.201.19:51:19.05#ibcon#about to read 3, iclass 35, count 2 2006.201.19:51:19.08#ibcon#read 3, iclass 35, count 2 2006.201.19:51:19.08#ibcon#about to read 4, iclass 35, count 2 2006.201.19:51:19.08#ibcon#read 4, iclass 35, count 2 2006.201.19:51:19.08#ibcon#about to read 5, iclass 35, count 2 2006.201.19:51:19.08#ibcon#read 5, iclass 35, count 2 2006.201.19:51:19.08#ibcon#about to read 6, iclass 35, count 2 2006.201.19:51:19.08#ibcon#read 6, iclass 35, count 2 2006.201.19:51:19.08#ibcon#end of sib2, iclass 35, count 2 2006.201.19:51:19.08#ibcon#*after write, iclass 35, count 2 2006.201.19:51:19.08#ibcon#*before return 0, iclass 35, count 2 2006.201.19:51:19.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:19.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.19:51:19.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.19:51:19.08#ibcon#ireg 7 cls_cnt 0 2006.201.19:51:19.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:19.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:19.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:19.20#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:51:19.20#ibcon#first serial, iclass 35, count 0 2006.201.19:51:19.20#ibcon#enter sib2, iclass 35, count 0 2006.201.19:51:19.20#ibcon#flushed, iclass 35, count 0 2006.201.19:51:19.20#ibcon#about to write, iclass 35, count 0 2006.201.19:51:19.20#ibcon#wrote, iclass 35, count 0 2006.201.19:51:19.20#ibcon#about to read 3, iclass 35, count 0 2006.201.19:51:19.23#ibcon#read 3, iclass 35, count 0 2006.201.19:51:19.23#ibcon#about to read 4, iclass 35, count 0 2006.201.19:51:19.23#ibcon#read 4, iclass 35, count 0 2006.201.19:51:19.23#ibcon#about to read 5, iclass 35, count 0 2006.201.19:51:19.23#ibcon#read 5, iclass 35, count 0 2006.201.19:51:19.23#ibcon#about to read 6, iclass 35, count 0 2006.201.19:51:19.23#ibcon#read 6, iclass 35, count 0 2006.201.19:51:19.23#ibcon#end of sib2, iclass 35, count 0 2006.201.19:51:19.23#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:51:19.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:51:19.23#ibcon#[27=USB\r\n] 2006.201.19:51:19.23#ibcon#*before write, iclass 35, count 0 2006.201.19:51:19.23#ibcon#enter sib2, iclass 35, count 0 2006.201.19:51:19.23#ibcon#flushed, iclass 35, count 0 2006.201.19:51:19.23#ibcon#about to write, iclass 35, count 0 2006.201.19:51:19.23#ibcon#wrote, iclass 35, count 0 2006.201.19:51:19.23#ibcon#about to read 3, iclass 35, count 0 2006.201.19:51:19.26#ibcon#read 3, iclass 35, count 0 2006.201.19:51:19.26#ibcon#about to read 4, iclass 35, count 0 2006.201.19:51:19.26#ibcon#read 4, iclass 35, count 0 2006.201.19:51:19.26#ibcon#about to read 5, iclass 35, count 0 2006.201.19:51:19.26#ibcon#read 5, iclass 35, count 0 2006.201.19:51:19.26#ibcon#about to read 6, iclass 35, count 0 2006.201.19:51:19.26#ibcon#read 6, iclass 35, count 0 2006.201.19:51:19.26#ibcon#end of sib2, iclass 35, count 0 2006.201.19:51:19.26#ibcon#*after write, iclass 35, count 0 2006.201.19:51:19.26#ibcon#*before return 0, iclass 35, count 0 2006.201.19:51:19.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:19.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.19:51:19.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:51:19.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:51:19.26$vck44/vabw=wide 2006.201.19:51:19.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.19:51:19.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.19:51:19.26#ibcon#ireg 8 cls_cnt 0 2006.201.19:51:19.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:19.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:19.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:19.26#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:51:19.26#ibcon#first serial, iclass 37, count 0 2006.201.19:51:19.26#ibcon#enter sib2, iclass 37, count 0 2006.201.19:51:19.26#ibcon#flushed, iclass 37, count 0 2006.201.19:51:19.26#ibcon#about to write, iclass 37, count 0 2006.201.19:51:19.26#ibcon#wrote, iclass 37, count 0 2006.201.19:51:19.26#ibcon#about to read 3, iclass 37, count 0 2006.201.19:51:19.28#ibcon#read 3, iclass 37, count 0 2006.201.19:51:19.28#ibcon#about to read 4, iclass 37, count 0 2006.201.19:51:19.28#ibcon#read 4, iclass 37, count 0 2006.201.19:51:19.28#ibcon#about to read 5, iclass 37, count 0 2006.201.19:51:19.28#ibcon#read 5, iclass 37, count 0 2006.201.19:51:19.28#ibcon#about to read 6, iclass 37, count 0 2006.201.19:51:19.28#ibcon#read 6, iclass 37, count 0 2006.201.19:51:19.28#ibcon#end of sib2, iclass 37, count 0 2006.201.19:51:19.28#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:51:19.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:51:19.28#ibcon#[25=BW32\r\n] 2006.201.19:51:19.28#ibcon#*before write, iclass 37, count 0 2006.201.19:51:19.28#ibcon#enter sib2, iclass 37, count 0 2006.201.19:51:19.28#ibcon#flushed, iclass 37, count 0 2006.201.19:51:19.28#ibcon#about to write, iclass 37, count 0 2006.201.19:51:19.28#ibcon#wrote, iclass 37, count 0 2006.201.19:51:19.28#ibcon#about to read 3, iclass 37, count 0 2006.201.19:51:19.31#ibcon#read 3, iclass 37, count 0 2006.201.19:51:19.31#ibcon#about to read 4, iclass 37, count 0 2006.201.19:51:19.31#ibcon#read 4, iclass 37, count 0 2006.201.19:51:19.31#ibcon#about to read 5, iclass 37, count 0 2006.201.19:51:19.31#ibcon#read 5, iclass 37, count 0 2006.201.19:51:19.31#ibcon#about to read 6, iclass 37, count 0 2006.201.19:51:19.31#ibcon#read 6, iclass 37, count 0 2006.201.19:51:19.31#ibcon#end of sib2, iclass 37, count 0 2006.201.19:51:19.31#ibcon#*after write, iclass 37, count 0 2006.201.19:51:19.31#ibcon#*before return 0, iclass 37, count 0 2006.201.19:51:19.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:19.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.19:51:19.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:51:19.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:51:19.31$vck44/vbbw=wide 2006.201.19:51:19.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.19:51:19.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.19:51:19.31#ibcon#ireg 8 cls_cnt 0 2006.201.19:51:19.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:51:19.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:51:19.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:51:19.38#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:51:19.38#ibcon#first serial, iclass 39, count 0 2006.201.19:51:19.38#ibcon#enter sib2, iclass 39, count 0 2006.201.19:51:19.38#ibcon#flushed, iclass 39, count 0 2006.201.19:51:19.38#ibcon#about to write, iclass 39, count 0 2006.201.19:51:19.38#ibcon#wrote, iclass 39, count 0 2006.201.19:51:19.38#ibcon#about to read 3, iclass 39, count 0 2006.201.19:51:19.40#ibcon#read 3, iclass 39, count 0 2006.201.19:51:19.40#ibcon#about to read 4, iclass 39, count 0 2006.201.19:51:19.40#ibcon#read 4, iclass 39, count 0 2006.201.19:51:19.40#ibcon#about to read 5, iclass 39, count 0 2006.201.19:51:19.40#ibcon#read 5, iclass 39, count 0 2006.201.19:51:19.40#ibcon#about to read 6, iclass 39, count 0 2006.201.19:51:19.40#ibcon#read 6, iclass 39, count 0 2006.201.19:51:19.40#ibcon#end of sib2, iclass 39, count 0 2006.201.19:51:19.40#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:51:19.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:51:19.40#ibcon#[27=BW32\r\n] 2006.201.19:51:19.40#ibcon#*before write, iclass 39, count 0 2006.201.19:51:19.40#ibcon#enter sib2, iclass 39, count 0 2006.201.19:51:19.40#ibcon#flushed, iclass 39, count 0 2006.201.19:51:19.40#ibcon#about to write, iclass 39, count 0 2006.201.19:51:19.40#ibcon#wrote, iclass 39, count 0 2006.201.19:51:19.40#ibcon#about to read 3, iclass 39, count 0 2006.201.19:51:19.40#abcon#<5=/04 2.0 4.2 20.351001002.2\r\n> 2006.201.19:51:19.42#abcon#{5=INTERFACE CLEAR} 2006.201.19:51:19.43#ibcon#read 3, iclass 39, count 0 2006.201.19:51:19.43#ibcon#about to read 4, iclass 39, count 0 2006.201.19:51:19.43#ibcon#read 4, iclass 39, count 0 2006.201.19:51:19.43#ibcon#about to read 5, iclass 39, count 0 2006.201.19:51:19.43#ibcon#read 5, iclass 39, count 0 2006.201.19:51:19.43#ibcon#about to read 6, iclass 39, count 0 2006.201.19:51:19.43#ibcon#read 6, iclass 39, count 0 2006.201.19:51:19.43#ibcon#end of sib2, iclass 39, count 0 2006.201.19:51:19.43#ibcon#*after write, iclass 39, count 0 2006.201.19:51:19.43#ibcon#*before return 0, iclass 39, count 0 2006.201.19:51:19.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:51:19.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:51:19.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:51:19.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:51:19.43$setupk4/ifdk4 2006.201.19:51:19.43$ifdk4/lo= 2006.201.19:51:19.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:51:19.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:51:19.43$ifdk4/patch= 2006.201.19:51:19.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:51:19.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:51:19.43$setupk4/!*+20s 2006.201.19:51:19.48#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:51:29.57#abcon#<5=/04 2.0 4.2 20.351001002.2\r\n> 2006.201.19:51:29.59#abcon#{5=INTERFACE CLEAR} 2006.201.19:51:29.65#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:51:33.89$setupk4/"tpicd 2006.201.19:51:33.89$setupk4/echo=off 2006.201.19:51:33.89$setupk4/xlog=off 2006.201.19:51:33.89:!2006.201.19:55:16 2006.201.19:52:06.13#trakl#Source acquired 2006.201.19:52:06.13#flagr#flagr/antenna,acquired 2006.201.19:55:16.00:preob 2006.201.19:55:16.14/onsource/TRACKING 2006.201.19:55:16.14:!2006.201.19:55:26 2006.201.19:55:26.00:"tape 2006.201.19:55:26.00:"st=record 2006.201.19:55:26.00:data_valid=on 2006.201.19:55:26.00:midob 2006.201.19:55:27.14/onsource/TRACKING 2006.201.19:55:27.14/wx/20.33,1002.1,100 2006.201.19:55:27.33/cable/+6.4809E-03 2006.201.19:55:28.42/va/01,08,usb,yes,43,46 2006.201.19:55:28.42/va/02,07,usb,yes,46,47 2006.201.19:55:28.42/va/03,08,usb,yes,42,44 2006.201.19:55:28.42/va/04,07,usb,yes,48,50 2006.201.19:55:28.42/va/05,04,usb,yes,43,44 2006.201.19:55:28.42/va/06,05,usb,yes,43,43 2006.201.19:55:28.42/va/07,05,usb,yes,42,43 2006.201.19:55:28.42/va/08,04,usb,yes,41,49 2006.201.19:55:28.65/valo/01,524.99,yes,locked 2006.201.19:55:28.65/valo/02,534.99,yes,locked 2006.201.19:55:28.65/valo/03,564.99,yes,locked 2006.201.19:55:28.65/valo/04,624.99,yes,locked 2006.201.19:55:28.65/valo/05,734.99,yes,locked 2006.201.19:55:28.65/valo/06,814.99,yes,locked 2006.201.19:55:28.65/valo/07,864.99,yes,locked 2006.201.19:55:28.65/valo/08,884.99,yes,locked 2006.201.19:55:29.74/vb/01,04,usb,yes,30,28 2006.201.19:55:29.74/vb/02,05,usb,yes,29,29 2006.201.19:55:29.74/vb/03,04,usb,yes,30,33 2006.201.19:55:29.74/vb/04,05,usb,yes,30,29 2006.201.19:55:29.74/vb/05,04,usb,yes,26,29 2006.201.19:55:29.74/vb/06,04,usb,yes,31,27 2006.201.19:55:29.74/vb/07,04,usb,yes,31,31 2006.201.19:55:29.74/vb/08,04,usb,yes,28,32 2006.201.19:55:29.97/vblo/01,629.99,yes,locked 2006.201.19:55:29.97/vblo/02,634.99,yes,locked 2006.201.19:55:29.97/vblo/03,649.99,yes,locked 2006.201.19:55:29.97/vblo/04,679.99,yes,locked 2006.201.19:55:29.97/vblo/05,709.99,yes,locked 2006.201.19:55:29.97/vblo/06,719.99,yes,locked 2006.201.19:55:29.97/vblo/07,734.99,yes,locked 2006.201.19:55:29.97/vblo/08,744.99,yes,locked 2006.201.19:55:30.12/vabw/8 2006.201.19:55:30.27/vbbw/8 2006.201.19:55:30.43/xfe/off,on,14.2 2006.201.19:55:30.81/ifatt/23,28,28,28 2006.201.19:55:31.07/fmout-gps/S +4.56E-07 2006.201.19:55:31.11:!2006.201.19:56:06 2006.201.19:56:06.00:data_valid=off 2006.201.19:56:06.00:"et 2006.201.19:56:06.00:!+3s 2006.201.19:56:09.02:"tape 2006.201.19:56:09.02:postob 2006.201.19:56:09.13/cable/+6.4814E-03 2006.201.19:56:09.13/wx/20.33,1002.1,100 2006.201.19:56:09.20/fmout-gps/S +4.57E-07 2006.201.19:56:09.20:scan_name=201-1956,jd0607,40 2006.201.19:56:09.20:source=2134+00,213638.59,004154.2,2000.0,ccw 2006.201.19:56:11.14#flagr#flagr/antenna,new-source 2006.201.19:56:11.14:checkk5 2006.201.19:56:11.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:56:11.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:56:12.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:56:12.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:56:13.01/chk_obsdata//k5ts1/T2011955??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:56:13.37/chk_obsdata//k5ts2/T2011955??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:56:13.74/chk_obsdata//k5ts3/T2011955??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:56:14.11/chk_obsdata//k5ts4/T2011955??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:56:14.79/k5log//k5ts1_log_newline 2006.201.19:56:15.48/k5log//k5ts2_log_newline 2006.201.19:56:16.17/k5log//k5ts3_log_newline 2006.201.19:56:16.87/k5log//k5ts4_log_newline 2006.201.19:56:16.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:56:16.89:setupk4=1 2006.201.19:56:16.89$setupk4/echo=on 2006.201.19:56:16.89$setupk4/pcalon 2006.201.19:56:16.89$pcalon/"no phase cal control is implemented here 2006.201.19:56:16.89$setupk4/"tpicd=stop 2006.201.19:56:16.89$setupk4/"rec=synch_on 2006.201.19:56:16.89$setupk4/"rec_mode=128 2006.201.19:56:16.89$setupk4/!* 2006.201.19:56:16.89$setupk4/recpk4 2006.201.19:56:16.89$recpk4/recpatch= 2006.201.19:56:16.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:56:16.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:56:16.90$setupk4/vck44 2006.201.19:56:16.90$vck44/valo=1,524.99 2006.201.19:56:16.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.19:56:16.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.19:56:16.90#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:16.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:16.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:16.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:16.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:56:16.90#ibcon#first serial, iclass 20, count 0 2006.201.19:56:16.90#ibcon#enter sib2, iclass 20, count 0 2006.201.19:56:16.90#ibcon#flushed, iclass 20, count 0 2006.201.19:56:16.90#ibcon#about to write, iclass 20, count 0 2006.201.19:56:16.90#ibcon#wrote, iclass 20, count 0 2006.201.19:56:16.90#ibcon#about to read 3, iclass 20, count 0 2006.201.19:56:16.93#ibcon#read 3, iclass 20, count 0 2006.201.19:56:16.93#ibcon#about to read 4, iclass 20, count 0 2006.201.19:56:16.93#ibcon#read 4, iclass 20, count 0 2006.201.19:56:16.93#ibcon#about to read 5, iclass 20, count 0 2006.201.19:56:16.93#ibcon#read 5, iclass 20, count 0 2006.201.19:56:16.93#ibcon#about to read 6, iclass 20, count 0 2006.201.19:56:16.93#ibcon#read 6, iclass 20, count 0 2006.201.19:56:16.93#ibcon#end of sib2, iclass 20, count 0 2006.201.19:56:16.93#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:56:16.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:56:16.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:56:16.93#ibcon#*before write, iclass 20, count 0 2006.201.19:56:16.93#ibcon#enter sib2, iclass 20, count 0 2006.201.19:56:16.93#ibcon#flushed, iclass 20, count 0 2006.201.19:56:16.93#ibcon#about to write, iclass 20, count 0 2006.201.19:56:16.93#ibcon#wrote, iclass 20, count 0 2006.201.19:56:16.93#ibcon#about to read 3, iclass 20, count 0 2006.201.19:56:16.98#ibcon#read 3, iclass 20, count 0 2006.201.19:56:16.98#ibcon#about to read 4, iclass 20, count 0 2006.201.19:56:16.98#ibcon#read 4, iclass 20, count 0 2006.201.19:56:16.98#ibcon#about to read 5, iclass 20, count 0 2006.201.19:56:16.98#ibcon#read 5, iclass 20, count 0 2006.201.19:56:16.98#ibcon#about to read 6, iclass 20, count 0 2006.201.19:56:16.98#ibcon#read 6, iclass 20, count 0 2006.201.19:56:16.98#ibcon#end of sib2, iclass 20, count 0 2006.201.19:56:16.98#ibcon#*after write, iclass 20, count 0 2006.201.19:56:16.98#ibcon#*before return 0, iclass 20, count 0 2006.201.19:56:16.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:16.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:16.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:56:16.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:56:16.98$vck44/va=1,8 2006.201.19:56:16.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.19:56:16.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.19:56:16.98#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:16.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:16.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:16.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:16.98#ibcon#enter wrdev, iclass 22, count 2 2006.201.19:56:16.98#ibcon#first serial, iclass 22, count 2 2006.201.19:56:16.98#ibcon#enter sib2, iclass 22, count 2 2006.201.19:56:16.98#ibcon#flushed, iclass 22, count 2 2006.201.19:56:16.98#ibcon#about to write, iclass 22, count 2 2006.201.19:56:16.98#ibcon#wrote, iclass 22, count 2 2006.201.19:56:16.98#ibcon#about to read 3, iclass 22, count 2 2006.201.19:56:17.00#ibcon#read 3, iclass 22, count 2 2006.201.19:56:17.00#ibcon#about to read 4, iclass 22, count 2 2006.201.19:56:17.00#ibcon#read 4, iclass 22, count 2 2006.201.19:56:17.00#ibcon#about to read 5, iclass 22, count 2 2006.201.19:56:17.00#ibcon#read 5, iclass 22, count 2 2006.201.19:56:17.00#ibcon#about to read 6, iclass 22, count 2 2006.201.19:56:17.00#ibcon#read 6, iclass 22, count 2 2006.201.19:56:17.00#ibcon#end of sib2, iclass 22, count 2 2006.201.19:56:17.00#ibcon#*mode == 0, iclass 22, count 2 2006.201.19:56:17.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.19:56:17.00#ibcon#[25=AT01-08\r\n] 2006.201.19:56:17.00#ibcon#*before write, iclass 22, count 2 2006.201.19:56:17.00#ibcon#enter sib2, iclass 22, count 2 2006.201.19:56:17.00#ibcon#flushed, iclass 22, count 2 2006.201.19:56:17.00#ibcon#about to write, iclass 22, count 2 2006.201.19:56:17.00#ibcon#wrote, iclass 22, count 2 2006.201.19:56:17.00#ibcon#about to read 3, iclass 22, count 2 2006.201.19:56:17.03#ibcon#read 3, iclass 22, count 2 2006.201.19:56:17.03#ibcon#about to read 4, iclass 22, count 2 2006.201.19:56:17.03#ibcon#read 4, iclass 22, count 2 2006.201.19:56:17.03#ibcon#about to read 5, iclass 22, count 2 2006.201.19:56:17.03#ibcon#read 5, iclass 22, count 2 2006.201.19:56:17.03#ibcon#about to read 6, iclass 22, count 2 2006.201.19:56:17.03#ibcon#read 6, iclass 22, count 2 2006.201.19:56:17.03#ibcon#end of sib2, iclass 22, count 2 2006.201.19:56:17.03#ibcon#*after write, iclass 22, count 2 2006.201.19:56:17.03#ibcon#*before return 0, iclass 22, count 2 2006.201.19:56:17.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:17.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:17.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.19:56:17.03#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:17.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:17.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:17.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:17.15#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:56:17.15#ibcon#first serial, iclass 22, count 0 2006.201.19:56:17.15#ibcon#enter sib2, iclass 22, count 0 2006.201.19:56:17.15#ibcon#flushed, iclass 22, count 0 2006.201.19:56:17.15#ibcon#about to write, iclass 22, count 0 2006.201.19:56:17.15#ibcon#wrote, iclass 22, count 0 2006.201.19:56:17.15#ibcon#about to read 3, iclass 22, count 0 2006.201.19:56:17.17#ibcon#read 3, iclass 22, count 0 2006.201.19:56:17.17#ibcon#about to read 4, iclass 22, count 0 2006.201.19:56:17.17#ibcon#read 4, iclass 22, count 0 2006.201.19:56:17.17#ibcon#about to read 5, iclass 22, count 0 2006.201.19:56:17.17#ibcon#read 5, iclass 22, count 0 2006.201.19:56:17.17#ibcon#about to read 6, iclass 22, count 0 2006.201.19:56:17.17#ibcon#read 6, iclass 22, count 0 2006.201.19:56:17.17#ibcon#end of sib2, iclass 22, count 0 2006.201.19:56:17.17#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:56:17.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:56:17.17#ibcon#[25=USB\r\n] 2006.201.19:56:17.17#ibcon#*before write, iclass 22, count 0 2006.201.19:56:17.17#ibcon#enter sib2, iclass 22, count 0 2006.201.19:56:17.17#ibcon#flushed, iclass 22, count 0 2006.201.19:56:17.17#ibcon#about to write, iclass 22, count 0 2006.201.19:56:17.17#ibcon#wrote, iclass 22, count 0 2006.201.19:56:17.17#ibcon#about to read 3, iclass 22, count 0 2006.201.19:56:17.20#ibcon#read 3, iclass 22, count 0 2006.201.19:56:17.20#ibcon#about to read 4, iclass 22, count 0 2006.201.19:56:17.20#ibcon#read 4, iclass 22, count 0 2006.201.19:56:17.20#ibcon#about to read 5, iclass 22, count 0 2006.201.19:56:17.20#ibcon#read 5, iclass 22, count 0 2006.201.19:56:17.20#ibcon#about to read 6, iclass 22, count 0 2006.201.19:56:17.20#ibcon#read 6, iclass 22, count 0 2006.201.19:56:17.20#ibcon#end of sib2, iclass 22, count 0 2006.201.19:56:17.20#ibcon#*after write, iclass 22, count 0 2006.201.19:56:17.20#ibcon#*before return 0, iclass 22, count 0 2006.201.19:56:17.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:17.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:17.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:56:17.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:56:17.20$vck44/valo=2,534.99 2006.201.19:56:17.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.19:56:17.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.19:56:17.20#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:17.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:17.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:17.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:17.20#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:56:17.20#ibcon#first serial, iclass 24, count 0 2006.201.19:56:17.20#ibcon#enter sib2, iclass 24, count 0 2006.201.19:56:17.20#ibcon#flushed, iclass 24, count 0 2006.201.19:56:17.20#ibcon#about to write, iclass 24, count 0 2006.201.19:56:17.20#ibcon#wrote, iclass 24, count 0 2006.201.19:56:17.20#ibcon#about to read 3, iclass 24, count 0 2006.201.19:56:17.22#ibcon#read 3, iclass 24, count 0 2006.201.19:56:17.22#ibcon#about to read 4, iclass 24, count 0 2006.201.19:56:17.22#ibcon#read 4, iclass 24, count 0 2006.201.19:56:17.22#ibcon#about to read 5, iclass 24, count 0 2006.201.19:56:17.22#ibcon#read 5, iclass 24, count 0 2006.201.19:56:17.22#ibcon#about to read 6, iclass 24, count 0 2006.201.19:56:17.22#ibcon#read 6, iclass 24, count 0 2006.201.19:56:17.22#ibcon#end of sib2, iclass 24, count 0 2006.201.19:56:17.22#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:56:17.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:56:17.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:56:17.22#ibcon#*before write, iclass 24, count 0 2006.201.19:56:17.22#ibcon#enter sib2, iclass 24, count 0 2006.201.19:56:17.22#ibcon#flushed, iclass 24, count 0 2006.201.19:56:17.22#ibcon#about to write, iclass 24, count 0 2006.201.19:56:17.22#ibcon#wrote, iclass 24, count 0 2006.201.19:56:17.22#ibcon#about to read 3, iclass 24, count 0 2006.201.19:56:17.26#ibcon#read 3, iclass 24, count 0 2006.201.19:56:17.26#ibcon#about to read 4, iclass 24, count 0 2006.201.19:56:17.26#ibcon#read 4, iclass 24, count 0 2006.201.19:56:17.26#ibcon#about to read 5, iclass 24, count 0 2006.201.19:56:17.26#ibcon#read 5, iclass 24, count 0 2006.201.19:56:17.26#ibcon#about to read 6, iclass 24, count 0 2006.201.19:56:17.26#ibcon#read 6, iclass 24, count 0 2006.201.19:56:17.26#ibcon#end of sib2, iclass 24, count 0 2006.201.19:56:17.26#ibcon#*after write, iclass 24, count 0 2006.201.19:56:17.26#ibcon#*before return 0, iclass 24, count 0 2006.201.19:56:17.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:17.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:17.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:56:17.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:56:17.26$vck44/va=2,7 2006.201.19:56:17.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.19:56:17.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.19:56:17.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:17.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:17.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:17.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:17.32#ibcon#enter wrdev, iclass 26, count 2 2006.201.19:56:17.32#ibcon#first serial, iclass 26, count 2 2006.201.19:56:17.32#ibcon#enter sib2, iclass 26, count 2 2006.201.19:56:17.32#ibcon#flushed, iclass 26, count 2 2006.201.19:56:17.32#ibcon#about to write, iclass 26, count 2 2006.201.19:56:17.32#ibcon#wrote, iclass 26, count 2 2006.201.19:56:17.32#ibcon#about to read 3, iclass 26, count 2 2006.201.19:56:17.34#ibcon#read 3, iclass 26, count 2 2006.201.19:56:17.34#ibcon#about to read 4, iclass 26, count 2 2006.201.19:56:17.34#ibcon#read 4, iclass 26, count 2 2006.201.19:56:17.34#ibcon#about to read 5, iclass 26, count 2 2006.201.19:56:17.34#ibcon#read 5, iclass 26, count 2 2006.201.19:56:17.34#ibcon#about to read 6, iclass 26, count 2 2006.201.19:56:17.34#ibcon#read 6, iclass 26, count 2 2006.201.19:56:17.34#ibcon#end of sib2, iclass 26, count 2 2006.201.19:56:17.34#ibcon#*mode == 0, iclass 26, count 2 2006.201.19:56:17.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.19:56:17.34#ibcon#[25=AT02-07\r\n] 2006.201.19:56:17.34#ibcon#*before write, iclass 26, count 2 2006.201.19:56:17.34#ibcon#enter sib2, iclass 26, count 2 2006.201.19:56:17.34#ibcon#flushed, iclass 26, count 2 2006.201.19:56:17.34#ibcon#about to write, iclass 26, count 2 2006.201.19:56:17.34#ibcon#wrote, iclass 26, count 2 2006.201.19:56:17.34#ibcon#about to read 3, iclass 26, count 2 2006.201.19:56:17.37#ibcon#read 3, iclass 26, count 2 2006.201.19:56:17.37#ibcon#about to read 4, iclass 26, count 2 2006.201.19:56:17.37#ibcon#read 4, iclass 26, count 2 2006.201.19:56:17.37#ibcon#about to read 5, iclass 26, count 2 2006.201.19:56:17.37#ibcon#read 5, iclass 26, count 2 2006.201.19:56:17.37#ibcon#about to read 6, iclass 26, count 2 2006.201.19:56:17.37#ibcon#read 6, iclass 26, count 2 2006.201.19:56:17.37#ibcon#end of sib2, iclass 26, count 2 2006.201.19:56:17.37#ibcon#*after write, iclass 26, count 2 2006.201.19:56:17.37#ibcon#*before return 0, iclass 26, count 2 2006.201.19:56:17.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:17.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:17.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.19:56:17.37#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:17.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:17.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:17.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:17.49#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:56:17.49#ibcon#first serial, iclass 26, count 0 2006.201.19:56:17.49#ibcon#enter sib2, iclass 26, count 0 2006.201.19:56:17.49#ibcon#flushed, iclass 26, count 0 2006.201.19:56:17.49#ibcon#about to write, iclass 26, count 0 2006.201.19:56:17.49#ibcon#wrote, iclass 26, count 0 2006.201.19:56:17.49#ibcon#about to read 3, iclass 26, count 0 2006.201.19:56:17.51#ibcon#read 3, iclass 26, count 0 2006.201.19:56:17.51#ibcon#about to read 4, iclass 26, count 0 2006.201.19:56:17.51#ibcon#read 4, iclass 26, count 0 2006.201.19:56:17.51#ibcon#about to read 5, iclass 26, count 0 2006.201.19:56:17.51#ibcon#read 5, iclass 26, count 0 2006.201.19:56:17.51#ibcon#about to read 6, iclass 26, count 0 2006.201.19:56:17.51#ibcon#read 6, iclass 26, count 0 2006.201.19:56:17.51#ibcon#end of sib2, iclass 26, count 0 2006.201.19:56:17.51#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:56:17.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:56:17.51#ibcon#[25=USB\r\n] 2006.201.19:56:17.51#ibcon#*before write, iclass 26, count 0 2006.201.19:56:17.51#ibcon#enter sib2, iclass 26, count 0 2006.201.19:56:17.51#ibcon#flushed, iclass 26, count 0 2006.201.19:56:17.51#ibcon#about to write, iclass 26, count 0 2006.201.19:56:17.51#ibcon#wrote, iclass 26, count 0 2006.201.19:56:17.51#ibcon#about to read 3, iclass 26, count 0 2006.201.19:56:17.54#ibcon#read 3, iclass 26, count 0 2006.201.19:56:17.54#ibcon#about to read 4, iclass 26, count 0 2006.201.19:56:17.54#ibcon#read 4, iclass 26, count 0 2006.201.19:56:17.54#ibcon#about to read 5, iclass 26, count 0 2006.201.19:56:17.54#ibcon#read 5, iclass 26, count 0 2006.201.19:56:17.54#ibcon#about to read 6, iclass 26, count 0 2006.201.19:56:17.54#ibcon#read 6, iclass 26, count 0 2006.201.19:56:17.54#ibcon#end of sib2, iclass 26, count 0 2006.201.19:56:17.54#ibcon#*after write, iclass 26, count 0 2006.201.19:56:17.54#ibcon#*before return 0, iclass 26, count 0 2006.201.19:56:17.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:17.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:17.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:56:17.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:56:17.54$vck44/valo=3,564.99 2006.201.19:56:17.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.19:56:17.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.19:56:17.54#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:17.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:17.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:17.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:17.54#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:56:17.54#ibcon#first serial, iclass 28, count 0 2006.201.19:56:17.54#ibcon#enter sib2, iclass 28, count 0 2006.201.19:56:17.54#ibcon#flushed, iclass 28, count 0 2006.201.19:56:17.54#ibcon#about to write, iclass 28, count 0 2006.201.19:56:17.54#ibcon#wrote, iclass 28, count 0 2006.201.19:56:17.54#ibcon#about to read 3, iclass 28, count 0 2006.201.19:56:17.56#ibcon#read 3, iclass 28, count 0 2006.201.19:56:17.56#ibcon#about to read 4, iclass 28, count 0 2006.201.19:56:17.56#ibcon#read 4, iclass 28, count 0 2006.201.19:56:17.56#ibcon#about to read 5, iclass 28, count 0 2006.201.19:56:17.56#ibcon#read 5, iclass 28, count 0 2006.201.19:56:17.56#ibcon#about to read 6, iclass 28, count 0 2006.201.19:56:17.56#ibcon#read 6, iclass 28, count 0 2006.201.19:56:17.56#ibcon#end of sib2, iclass 28, count 0 2006.201.19:56:17.56#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:56:17.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:56:17.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:56:17.56#ibcon#*before write, iclass 28, count 0 2006.201.19:56:17.56#ibcon#enter sib2, iclass 28, count 0 2006.201.19:56:17.56#ibcon#flushed, iclass 28, count 0 2006.201.19:56:17.56#ibcon#about to write, iclass 28, count 0 2006.201.19:56:17.56#ibcon#wrote, iclass 28, count 0 2006.201.19:56:17.56#ibcon#about to read 3, iclass 28, count 0 2006.201.19:56:17.60#ibcon#read 3, iclass 28, count 0 2006.201.19:56:17.60#ibcon#about to read 4, iclass 28, count 0 2006.201.19:56:17.60#ibcon#read 4, iclass 28, count 0 2006.201.19:56:17.60#ibcon#about to read 5, iclass 28, count 0 2006.201.19:56:17.60#ibcon#read 5, iclass 28, count 0 2006.201.19:56:17.60#ibcon#about to read 6, iclass 28, count 0 2006.201.19:56:17.60#ibcon#read 6, iclass 28, count 0 2006.201.19:56:17.60#ibcon#end of sib2, iclass 28, count 0 2006.201.19:56:17.60#ibcon#*after write, iclass 28, count 0 2006.201.19:56:17.60#ibcon#*before return 0, iclass 28, count 0 2006.201.19:56:17.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:17.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:17.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:56:17.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:56:17.60$vck44/va=3,8 2006.201.19:56:17.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.19:56:17.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.19:56:17.60#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:17.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:17.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:17.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:17.66#ibcon#enter wrdev, iclass 30, count 2 2006.201.19:56:17.66#ibcon#first serial, iclass 30, count 2 2006.201.19:56:17.66#ibcon#enter sib2, iclass 30, count 2 2006.201.19:56:17.66#ibcon#flushed, iclass 30, count 2 2006.201.19:56:17.66#ibcon#about to write, iclass 30, count 2 2006.201.19:56:17.66#ibcon#wrote, iclass 30, count 2 2006.201.19:56:17.66#ibcon#about to read 3, iclass 30, count 2 2006.201.19:56:17.68#ibcon#read 3, iclass 30, count 2 2006.201.19:56:17.68#ibcon#about to read 4, iclass 30, count 2 2006.201.19:56:17.68#ibcon#read 4, iclass 30, count 2 2006.201.19:56:17.68#ibcon#about to read 5, iclass 30, count 2 2006.201.19:56:17.68#ibcon#read 5, iclass 30, count 2 2006.201.19:56:17.68#ibcon#about to read 6, iclass 30, count 2 2006.201.19:56:17.68#ibcon#read 6, iclass 30, count 2 2006.201.19:56:17.68#ibcon#end of sib2, iclass 30, count 2 2006.201.19:56:17.68#ibcon#*mode == 0, iclass 30, count 2 2006.201.19:56:17.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.19:56:17.68#ibcon#[25=AT03-08\r\n] 2006.201.19:56:17.68#ibcon#*before write, iclass 30, count 2 2006.201.19:56:17.68#ibcon#enter sib2, iclass 30, count 2 2006.201.19:56:17.68#ibcon#flushed, iclass 30, count 2 2006.201.19:56:17.68#ibcon#about to write, iclass 30, count 2 2006.201.19:56:17.68#ibcon#wrote, iclass 30, count 2 2006.201.19:56:17.68#ibcon#about to read 3, iclass 30, count 2 2006.201.19:56:17.71#ibcon#read 3, iclass 30, count 2 2006.201.19:56:17.71#ibcon#about to read 4, iclass 30, count 2 2006.201.19:56:17.71#ibcon#read 4, iclass 30, count 2 2006.201.19:56:17.71#ibcon#about to read 5, iclass 30, count 2 2006.201.19:56:17.71#ibcon#read 5, iclass 30, count 2 2006.201.19:56:17.71#ibcon#about to read 6, iclass 30, count 2 2006.201.19:56:17.71#ibcon#read 6, iclass 30, count 2 2006.201.19:56:17.71#ibcon#end of sib2, iclass 30, count 2 2006.201.19:56:17.71#ibcon#*after write, iclass 30, count 2 2006.201.19:56:17.71#ibcon#*before return 0, iclass 30, count 2 2006.201.19:56:17.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:17.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:17.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.19:56:17.71#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:17.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:17.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:17.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:17.83#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:56:17.83#ibcon#first serial, iclass 30, count 0 2006.201.19:56:17.83#ibcon#enter sib2, iclass 30, count 0 2006.201.19:56:17.83#ibcon#flushed, iclass 30, count 0 2006.201.19:56:17.83#ibcon#about to write, iclass 30, count 0 2006.201.19:56:17.83#ibcon#wrote, iclass 30, count 0 2006.201.19:56:17.83#ibcon#about to read 3, iclass 30, count 0 2006.201.19:56:17.85#ibcon#read 3, iclass 30, count 0 2006.201.19:56:17.85#ibcon#about to read 4, iclass 30, count 0 2006.201.19:56:17.85#ibcon#read 4, iclass 30, count 0 2006.201.19:56:17.85#ibcon#about to read 5, iclass 30, count 0 2006.201.19:56:17.85#ibcon#read 5, iclass 30, count 0 2006.201.19:56:17.85#ibcon#about to read 6, iclass 30, count 0 2006.201.19:56:17.85#ibcon#read 6, iclass 30, count 0 2006.201.19:56:17.85#ibcon#end of sib2, iclass 30, count 0 2006.201.19:56:17.85#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:56:17.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:56:17.85#ibcon#[25=USB\r\n] 2006.201.19:56:17.85#ibcon#*before write, iclass 30, count 0 2006.201.19:56:17.85#ibcon#enter sib2, iclass 30, count 0 2006.201.19:56:17.85#ibcon#flushed, iclass 30, count 0 2006.201.19:56:17.85#ibcon#about to write, iclass 30, count 0 2006.201.19:56:17.85#ibcon#wrote, iclass 30, count 0 2006.201.19:56:17.85#ibcon#about to read 3, iclass 30, count 0 2006.201.19:56:17.88#ibcon#read 3, iclass 30, count 0 2006.201.19:56:17.88#ibcon#about to read 4, iclass 30, count 0 2006.201.19:56:17.88#ibcon#read 4, iclass 30, count 0 2006.201.19:56:17.88#ibcon#about to read 5, iclass 30, count 0 2006.201.19:56:17.88#ibcon#read 5, iclass 30, count 0 2006.201.19:56:17.88#ibcon#about to read 6, iclass 30, count 0 2006.201.19:56:17.88#ibcon#read 6, iclass 30, count 0 2006.201.19:56:17.88#ibcon#end of sib2, iclass 30, count 0 2006.201.19:56:17.88#ibcon#*after write, iclass 30, count 0 2006.201.19:56:17.88#ibcon#*before return 0, iclass 30, count 0 2006.201.19:56:17.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:17.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:17.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:56:17.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:56:17.88$vck44/valo=4,624.99 2006.201.19:56:17.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.19:56:17.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.19:56:17.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:17.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:17.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:17.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:17.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:56:17.88#ibcon#first serial, iclass 32, count 0 2006.201.19:56:17.88#ibcon#enter sib2, iclass 32, count 0 2006.201.19:56:17.88#ibcon#flushed, iclass 32, count 0 2006.201.19:56:17.88#ibcon#about to write, iclass 32, count 0 2006.201.19:56:17.88#ibcon#wrote, iclass 32, count 0 2006.201.19:56:17.88#ibcon#about to read 3, iclass 32, count 0 2006.201.19:56:17.90#ibcon#read 3, iclass 32, count 0 2006.201.19:56:17.90#ibcon#about to read 4, iclass 32, count 0 2006.201.19:56:17.90#ibcon#read 4, iclass 32, count 0 2006.201.19:56:17.90#ibcon#about to read 5, iclass 32, count 0 2006.201.19:56:17.90#ibcon#read 5, iclass 32, count 0 2006.201.19:56:17.90#ibcon#about to read 6, iclass 32, count 0 2006.201.19:56:17.90#ibcon#read 6, iclass 32, count 0 2006.201.19:56:17.90#ibcon#end of sib2, iclass 32, count 0 2006.201.19:56:17.90#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:56:17.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:56:17.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:56:17.90#ibcon#*before write, iclass 32, count 0 2006.201.19:56:17.90#ibcon#enter sib2, iclass 32, count 0 2006.201.19:56:17.90#ibcon#flushed, iclass 32, count 0 2006.201.19:56:17.90#ibcon#about to write, iclass 32, count 0 2006.201.19:56:17.90#ibcon#wrote, iclass 32, count 0 2006.201.19:56:17.90#ibcon#about to read 3, iclass 32, count 0 2006.201.19:56:17.95#ibcon#read 3, iclass 32, count 0 2006.201.19:56:17.95#ibcon#about to read 4, iclass 32, count 0 2006.201.19:56:17.95#ibcon#read 4, iclass 32, count 0 2006.201.19:56:17.95#ibcon#about to read 5, iclass 32, count 0 2006.201.19:56:17.95#ibcon#read 5, iclass 32, count 0 2006.201.19:56:17.95#ibcon#about to read 6, iclass 32, count 0 2006.201.19:56:17.95#ibcon#read 6, iclass 32, count 0 2006.201.19:56:17.95#ibcon#end of sib2, iclass 32, count 0 2006.201.19:56:17.95#ibcon#*after write, iclass 32, count 0 2006.201.19:56:17.95#ibcon#*before return 0, iclass 32, count 0 2006.201.19:56:17.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:17.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:17.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:56:17.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:56:17.95$vck44/va=4,7 2006.201.19:56:17.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.19:56:17.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.19:56:17.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:17.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:18.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:18.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:18.00#ibcon#enter wrdev, iclass 34, count 2 2006.201.19:56:18.00#ibcon#first serial, iclass 34, count 2 2006.201.19:56:18.00#ibcon#enter sib2, iclass 34, count 2 2006.201.19:56:18.00#ibcon#flushed, iclass 34, count 2 2006.201.19:56:18.00#ibcon#about to write, iclass 34, count 2 2006.201.19:56:18.00#ibcon#wrote, iclass 34, count 2 2006.201.19:56:18.00#ibcon#about to read 3, iclass 34, count 2 2006.201.19:56:18.02#ibcon#read 3, iclass 34, count 2 2006.201.19:56:18.02#ibcon#about to read 4, iclass 34, count 2 2006.201.19:56:18.02#ibcon#read 4, iclass 34, count 2 2006.201.19:56:18.02#ibcon#about to read 5, iclass 34, count 2 2006.201.19:56:18.02#ibcon#read 5, iclass 34, count 2 2006.201.19:56:18.02#ibcon#about to read 6, iclass 34, count 2 2006.201.19:56:18.02#ibcon#read 6, iclass 34, count 2 2006.201.19:56:18.02#ibcon#end of sib2, iclass 34, count 2 2006.201.19:56:18.02#ibcon#*mode == 0, iclass 34, count 2 2006.201.19:56:18.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.19:56:18.02#ibcon#[25=AT04-07\r\n] 2006.201.19:56:18.02#ibcon#*before write, iclass 34, count 2 2006.201.19:56:18.02#ibcon#enter sib2, iclass 34, count 2 2006.201.19:56:18.02#ibcon#flushed, iclass 34, count 2 2006.201.19:56:18.02#ibcon#about to write, iclass 34, count 2 2006.201.19:56:18.02#ibcon#wrote, iclass 34, count 2 2006.201.19:56:18.02#ibcon#about to read 3, iclass 34, count 2 2006.201.19:56:18.05#ibcon#read 3, iclass 34, count 2 2006.201.19:56:18.05#ibcon#about to read 4, iclass 34, count 2 2006.201.19:56:18.05#ibcon#read 4, iclass 34, count 2 2006.201.19:56:18.05#ibcon#about to read 5, iclass 34, count 2 2006.201.19:56:18.05#ibcon#read 5, iclass 34, count 2 2006.201.19:56:18.05#ibcon#about to read 6, iclass 34, count 2 2006.201.19:56:18.05#ibcon#read 6, iclass 34, count 2 2006.201.19:56:18.05#ibcon#end of sib2, iclass 34, count 2 2006.201.19:56:18.05#ibcon#*after write, iclass 34, count 2 2006.201.19:56:18.05#ibcon#*before return 0, iclass 34, count 2 2006.201.19:56:18.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:18.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:18.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.19:56:18.05#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:18.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:18.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:18.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:18.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:56:18.17#ibcon#first serial, iclass 34, count 0 2006.201.19:56:18.17#ibcon#enter sib2, iclass 34, count 0 2006.201.19:56:18.17#ibcon#flushed, iclass 34, count 0 2006.201.19:56:18.17#ibcon#about to write, iclass 34, count 0 2006.201.19:56:18.17#ibcon#wrote, iclass 34, count 0 2006.201.19:56:18.17#ibcon#about to read 3, iclass 34, count 0 2006.201.19:56:18.19#ibcon#read 3, iclass 34, count 0 2006.201.19:56:18.19#ibcon#about to read 4, iclass 34, count 0 2006.201.19:56:18.19#ibcon#read 4, iclass 34, count 0 2006.201.19:56:18.19#ibcon#about to read 5, iclass 34, count 0 2006.201.19:56:18.19#ibcon#read 5, iclass 34, count 0 2006.201.19:56:18.19#ibcon#about to read 6, iclass 34, count 0 2006.201.19:56:18.19#ibcon#read 6, iclass 34, count 0 2006.201.19:56:18.19#ibcon#end of sib2, iclass 34, count 0 2006.201.19:56:18.19#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:56:18.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:56:18.19#ibcon#[25=USB\r\n] 2006.201.19:56:18.19#ibcon#*before write, iclass 34, count 0 2006.201.19:56:18.19#ibcon#enter sib2, iclass 34, count 0 2006.201.19:56:18.19#ibcon#flushed, iclass 34, count 0 2006.201.19:56:18.19#ibcon#about to write, iclass 34, count 0 2006.201.19:56:18.19#ibcon#wrote, iclass 34, count 0 2006.201.19:56:18.19#ibcon#about to read 3, iclass 34, count 0 2006.201.19:56:18.22#ibcon#read 3, iclass 34, count 0 2006.201.19:56:18.22#ibcon#about to read 4, iclass 34, count 0 2006.201.19:56:18.22#ibcon#read 4, iclass 34, count 0 2006.201.19:56:18.22#ibcon#about to read 5, iclass 34, count 0 2006.201.19:56:18.22#ibcon#read 5, iclass 34, count 0 2006.201.19:56:18.22#ibcon#about to read 6, iclass 34, count 0 2006.201.19:56:18.22#ibcon#read 6, iclass 34, count 0 2006.201.19:56:18.22#ibcon#end of sib2, iclass 34, count 0 2006.201.19:56:18.22#ibcon#*after write, iclass 34, count 0 2006.201.19:56:18.22#ibcon#*before return 0, iclass 34, count 0 2006.201.19:56:18.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:18.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:18.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:56:18.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:56:18.22$vck44/valo=5,734.99 2006.201.19:56:18.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.19:56:18.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.19:56:18.22#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:18.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:18.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:18.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:18.22#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:56:18.22#ibcon#first serial, iclass 36, count 0 2006.201.19:56:18.22#ibcon#enter sib2, iclass 36, count 0 2006.201.19:56:18.22#ibcon#flushed, iclass 36, count 0 2006.201.19:56:18.22#ibcon#about to write, iclass 36, count 0 2006.201.19:56:18.22#ibcon#wrote, iclass 36, count 0 2006.201.19:56:18.22#ibcon#about to read 3, iclass 36, count 0 2006.201.19:56:18.24#ibcon#read 3, iclass 36, count 0 2006.201.19:56:18.24#ibcon#about to read 4, iclass 36, count 0 2006.201.19:56:18.24#ibcon#read 4, iclass 36, count 0 2006.201.19:56:18.24#ibcon#about to read 5, iclass 36, count 0 2006.201.19:56:18.24#ibcon#read 5, iclass 36, count 0 2006.201.19:56:18.24#ibcon#about to read 6, iclass 36, count 0 2006.201.19:56:18.24#ibcon#read 6, iclass 36, count 0 2006.201.19:56:18.24#ibcon#end of sib2, iclass 36, count 0 2006.201.19:56:18.24#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:56:18.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:56:18.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:56:18.24#ibcon#*before write, iclass 36, count 0 2006.201.19:56:18.24#ibcon#enter sib2, iclass 36, count 0 2006.201.19:56:18.24#ibcon#flushed, iclass 36, count 0 2006.201.19:56:18.24#ibcon#about to write, iclass 36, count 0 2006.201.19:56:18.24#ibcon#wrote, iclass 36, count 0 2006.201.19:56:18.24#ibcon#about to read 3, iclass 36, count 0 2006.201.19:56:18.28#ibcon#read 3, iclass 36, count 0 2006.201.19:56:18.28#ibcon#about to read 4, iclass 36, count 0 2006.201.19:56:18.28#ibcon#read 4, iclass 36, count 0 2006.201.19:56:18.28#ibcon#about to read 5, iclass 36, count 0 2006.201.19:56:18.28#ibcon#read 5, iclass 36, count 0 2006.201.19:56:18.28#ibcon#about to read 6, iclass 36, count 0 2006.201.19:56:18.28#ibcon#read 6, iclass 36, count 0 2006.201.19:56:18.28#ibcon#end of sib2, iclass 36, count 0 2006.201.19:56:18.28#ibcon#*after write, iclass 36, count 0 2006.201.19:56:18.28#ibcon#*before return 0, iclass 36, count 0 2006.201.19:56:18.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:18.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:18.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:56:18.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:56:18.28$vck44/va=5,4 2006.201.19:56:18.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.19:56:18.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.19:56:18.28#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:18.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:18.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:18.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:18.34#ibcon#enter wrdev, iclass 38, count 2 2006.201.19:56:18.34#ibcon#first serial, iclass 38, count 2 2006.201.19:56:18.34#ibcon#enter sib2, iclass 38, count 2 2006.201.19:56:18.34#ibcon#flushed, iclass 38, count 2 2006.201.19:56:18.34#ibcon#about to write, iclass 38, count 2 2006.201.19:56:18.34#ibcon#wrote, iclass 38, count 2 2006.201.19:56:18.34#ibcon#about to read 3, iclass 38, count 2 2006.201.19:56:18.36#ibcon#read 3, iclass 38, count 2 2006.201.19:56:18.36#ibcon#about to read 4, iclass 38, count 2 2006.201.19:56:18.36#ibcon#read 4, iclass 38, count 2 2006.201.19:56:18.36#ibcon#about to read 5, iclass 38, count 2 2006.201.19:56:18.36#ibcon#read 5, iclass 38, count 2 2006.201.19:56:18.36#ibcon#about to read 6, iclass 38, count 2 2006.201.19:56:18.36#ibcon#read 6, iclass 38, count 2 2006.201.19:56:18.36#ibcon#end of sib2, iclass 38, count 2 2006.201.19:56:18.36#ibcon#*mode == 0, iclass 38, count 2 2006.201.19:56:18.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.19:56:18.36#ibcon#[25=AT05-04\r\n] 2006.201.19:56:18.36#ibcon#*before write, iclass 38, count 2 2006.201.19:56:18.36#ibcon#enter sib2, iclass 38, count 2 2006.201.19:56:18.36#ibcon#flushed, iclass 38, count 2 2006.201.19:56:18.36#ibcon#about to write, iclass 38, count 2 2006.201.19:56:18.36#ibcon#wrote, iclass 38, count 2 2006.201.19:56:18.36#ibcon#about to read 3, iclass 38, count 2 2006.201.19:56:18.39#ibcon#read 3, iclass 38, count 2 2006.201.19:56:18.39#ibcon#about to read 4, iclass 38, count 2 2006.201.19:56:18.39#ibcon#read 4, iclass 38, count 2 2006.201.19:56:18.39#ibcon#about to read 5, iclass 38, count 2 2006.201.19:56:18.39#ibcon#read 5, iclass 38, count 2 2006.201.19:56:18.39#ibcon#about to read 6, iclass 38, count 2 2006.201.19:56:18.39#ibcon#read 6, iclass 38, count 2 2006.201.19:56:18.39#ibcon#end of sib2, iclass 38, count 2 2006.201.19:56:18.39#ibcon#*after write, iclass 38, count 2 2006.201.19:56:18.39#ibcon#*before return 0, iclass 38, count 2 2006.201.19:56:18.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:18.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:18.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.19:56:18.39#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:18.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:18.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:18.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:18.51#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:56:18.51#ibcon#first serial, iclass 38, count 0 2006.201.19:56:18.51#ibcon#enter sib2, iclass 38, count 0 2006.201.19:56:18.51#ibcon#flushed, iclass 38, count 0 2006.201.19:56:18.51#ibcon#about to write, iclass 38, count 0 2006.201.19:56:18.51#ibcon#wrote, iclass 38, count 0 2006.201.19:56:18.51#ibcon#about to read 3, iclass 38, count 0 2006.201.19:56:18.53#ibcon#read 3, iclass 38, count 0 2006.201.19:56:18.53#ibcon#about to read 4, iclass 38, count 0 2006.201.19:56:18.53#ibcon#read 4, iclass 38, count 0 2006.201.19:56:18.53#ibcon#about to read 5, iclass 38, count 0 2006.201.19:56:18.53#ibcon#read 5, iclass 38, count 0 2006.201.19:56:18.53#ibcon#about to read 6, iclass 38, count 0 2006.201.19:56:18.53#ibcon#read 6, iclass 38, count 0 2006.201.19:56:18.53#ibcon#end of sib2, iclass 38, count 0 2006.201.19:56:18.53#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:56:18.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:56:18.53#ibcon#[25=USB\r\n] 2006.201.19:56:18.53#ibcon#*before write, iclass 38, count 0 2006.201.19:56:18.53#ibcon#enter sib2, iclass 38, count 0 2006.201.19:56:18.53#ibcon#flushed, iclass 38, count 0 2006.201.19:56:18.53#ibcon#about to write, iclass 38, count 0 2006.201.19:56:18.53#ibcon#wrote, iclass 38, count 0 2006.201.19:56:18.53#ibcon#about to read 3, iclass 38, count 0 2006.201.19:56:18.56#ibcon#read 3, iclass 38, count 0 2006.201.19:56:18.56#ibcon#about to read 4, iclass 38, count 0 2006.201.19:56:18.56#ibcon#read 4, iclass 38, count 0 2006.201.19:56:18.56#ibcon#about to read 5, iclass 38, count 0 2006.201.19:56:18.56#ibcon#read 5, iclass 38, count 0 2006.201.19:56:18.56#ibcon#about to read 6, iclass 38, count 0 2006.201.19:56:18.56#ibcon#read 6, iclass 38, count 0 2006.201.19:56:18.56#ibcon#end of sib2, iclass 38, count 0 2006.201.19:56:18.56#ibcon#*after write, iclass 38, count 0 2006.201.19:56:18.56#ibcon#*before return 0, iclass 38, count 0 2006.201.19:56:18.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:18.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:18.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:56:18.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:56:18.56$vck44/valo=6,814.99 2006.201.19:56:18.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.19:56:18.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.19:56:18.56#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:18.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:18.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:18.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:18.56#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:56:18.56#ibcon#first serial, iclass 40, count 0 2006.201.19:56:18.56#ibcon#enter sib2, iclass 40, count 0 2006.201.19:56:18.56#ibcon#flushed, iclass 40, count 0 2006.201.19:56:18.56#ibcon#about to write, iclass 40, count 0 2006.201.19:56:18.56#ibcon#wrote, iclass 40, count 0 2006.201.19:56:18.56#ibcon#about to read 3, iclass 40, count 0 2006.201.19:56:18.58#ibcon#read 3, iclass 40, count 0 2006.201.19:56:18.58#ibcon#about to read 4, iclass 40, count 0 2006.201.19:56:18.58#ibcon#read 4, iclass 40, count 0 2006.201.19:56:18.58#ibcon#about to read 5, iclass 40, count 0 2006.201.19:56:18.58#ibcon#read 5, iclass 40, count 0 2006.201.19:56:18.58#ibcon#about to read 6, iclass 40, count 0 2006.201.19:56:18.58#ibcon#read 6, iclass 40, count 0 2006.201.19:56:18.58#ibcon#end of sib2, iclass 40, count 0 2006.201.19:56:18.58#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:56:18.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:56:18.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:56:18.58#ibcon#*before write, iclass 40, count 0 2006.201.19:56:18.58#ibcon#enter sib2, iclass 40, count 0 2006.201.19:56:18.58#ibcon#flushed, iclass 40, count 0 2006.201.19:56:18.58#ibcon#about to write, iclass 40, count 0 2006.201.19:56:18.58#ibcon#wrote, iclass 40, count 0 2006.201.19:56:18.58#ibcon#about to read 3, iclass 40, count 0 2006.201.19:56:18.63#ibcon#read 3, iclass 40, count 0 2006.201.19:56:18.63#ibcon#about to read 4, iclass 40, count 0 2006.201.19:56:18.63#ibcon#read 4, iclass 40, count 0 2006.201.19:56:18.63#ibcon#about to read 5, iclass 40, count 0 2006.201.19:56:18.63#ibcon#read 5, iclass 40, count 0 2006.201.19:56:18.63#ibcon#about to read 6, iclass 40, count 0 2006.201.19:56:18.63#ibcon#read 6, iclass 40, count 0 2006.201.19:56:18.63#ibcon#end of sib2, iclass 40, count 0 2006.201.19:56:18.63#ibcon#*after write, iclass 40, count 0 2006.201.19:56:18.63#ibcon#*before return 0, iclass 40, count 0 2006.201.19:56:18.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:18.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:18.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:56:18.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:56:18.63$vck44/va=6,5 2006.201.19:56:18.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.19:56:18.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.19:56:18.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:18.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:18.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:18.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:18.68#ibcon#enter wrdev, iclass 4, count 2 2006.201.19:56:18.68#ibcon#first serial, iclass 4, count 2 2006.201.19:56:18.68#ibcon#enter sib2, iclass 4, count 2 2006.201.19:56:18.68#ibcon#flushed, iclass 4, count 2 2006.201.19:56:18.68#ibcon#about to write, iclass 4, count 2 2006.201.19:56:18.68#ibcon#wrote, iclass 4, count 2 2006.201.19:56:18.68#ibcon#about to read 3, iclass 4, count 2 2006.201.19:56:18.70#ibcon#read 3, iclass 4, count 2 2006.201.19:56:18.70#ibcon#about to read 4, iclass 4, count 2 2006.201.19:56:18.70#ibcon#read 4, iclass 4, count 2 2006.201.19:56:18.70#ibcon#about to read 5, iclass 4, count 2 2006.201.19:56:18.70#ibcon#read 5, iclass 4, count 2 2006.201.19:56:18.70#ibcon#about to read 6, iclass 4, count 2 2006.201.19:56:18.70#ibcon#read 6, iclass 4, count 2 2006.201.19:56:18.70#ibcon#end of sib2, iclass 4, count 2 2006.201.19:56:18.70#ibcon#*mode == 0, iclass 4, count 2 2006.201.19:56:18.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.19:56:18.70#ibcon#[25=AT06-05\r\n] 2006.201.19:56:18.70#ibcon#*before write, iclass 4, count 2 2006.201.19:56:18.70#ibcon#enter sib2, iclass 4, count 2 2006.201.19:56:18.70#ibcon#flushed, iclass 4, count 2 2006.201.19:56:18.70#ibcon#about to write, iclass 4, count 2 2006.201.19:56:18.70#ibcon#wrote, iclass 4, count 2 2006.201.19:56:18.70#ibcon#about to read 3, iclass 4, count 2 2006.201.19:56:18.73#ibcon#read 3, iclass 4, count 2 2006.201.19:56:18.73#ibcon#about to read 4, iclass 4, count 2 2006.201.19:56:18.73#ibcon#read 4, iclass 4, count 2 2006.201.19:56:18.73#ibcon#about to read 5, iclass 4, count 2 2006.201.19:56:18.73#ibcon#read 5, iclass 4, count 2 2006.201.19:56:18.73#ibcon#about to read 6, iclass 4, count 2 2006.201.19:56:18.73#ibcon#read 6, iclass 4, count 2 2006.201.19:56:18.73#ibcon#end of sib2, iclass 4, count 2 2006.201.19:56:18.73#ibcon#*after write, iclass 4, count 2 2006.201.19:56:18.73#ibcon#*before return 0, iclass 4, count 2 2006.201.19:56:18.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:18.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:18.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.19:56:18.73#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:18.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:18.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:18.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:18.85#ibcon#enter wrdev, iclass 4, count 0 2006.201.19:56:18.85#ibcon#first serial, iclass 4, count 0 2006.201.19:56:18.85#ibcon#enter sib2, iclass 4, count 0 2006.201.19:56:18.85#ibcon#flushed, iclass 4, count 0 2006.201.19:56:18.85#ibcon#about to write, iclass 4, count 0 2006.201.19:56:18.85#ibcon#wrote, iclass 4, count 0 2006.201.19:56:18.85#ibcon#about to read 3, iclass 4, count 0 2006.201.19:56:18.87#ibcon#read 3, iclass 4, count 0 2006.201.19:56:18.87#ibcon#about to read 4, iclass 4, count 0 2006.201.19:56:18.87#ibcon#read 4, iclass 4, count 0 2006.201.19:56:18.87#ibcon#about to read 5, iclass 4, count 0 2006.201.19:56:18.87#ibcon#read 5, iclass 4, count 0 2006.201.19:56:18.87#ibcon#about to read 6, iclass 4, count 0 2006.201.19:56:18.87#ibcon#read 6, iclass 4, count 0 2006.201.19:56:18.87#ibcon#end of sib2, iclass 4, count 0 2006.201.19:56:18.87#ibcon#*mode == 0, iclass 4, count 0 2006.201.19:56:18.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.19:56:18.87#ibcon#[25=USB\r\n] 2006.201.19:56:18.87#ibcon#*before write, iclass 4, count 0 2006.201.19:56:18.87#ibcon#enter sib2, iclass 4, count 0 2006.201.19:56:18.87#ibcon#flushed, iclass 4, count 0 2006.201.19:56:18.87#ibcon#about to write, iclass 4, count 0 2006.201.19:56:18.87#ibcon#wrote, iclass 4, count 0 2006.201.19:56:18.87#ibcon#about to read 3, iclass 4, count 0 2006.201.19:56:18.90#ibcon#read 3, iclass 4, count 0 2006.201.19:56:18.90#ibcon#about to read 4, iclass 4, count 0 2006.201.19:56:18.90#ibcon#read 4, iclass 4, count 0 2006.201.19:56:18.90#ibcon#about to read 5, iclass 4, count 0 2006.201.19:56:18.90#ibcon#read 5, iclass 4, count 0 2006.201.19:56:18.90#ibcon#about to read 6, iclass 4, count 0 2006.201.19:56:18.90#ibcon#read 6, iclass 4, count 0 2006.201.19:56:18.90#ibcon#end of sib2, iclass 4, count 0 2006.201.19:56:18.90#ibcon#*after write, iclass 4, count 0 2006.201.19:56:18.90#ibcon#*before return 0, iclass 4, count 0 2006.201.19:56:18.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:18.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:18.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.19:56:18.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.19:56:18.90$vck44/valo=7,864.99 2006.201.19:56:18.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.19:56:18.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.19:56:18.90#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:18.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:18.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:18.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:18.90#ibcon#enter wrdev, iclass 6, count 0 2006.201.19:56:18.90#ibcon#first serial, iclass 6, count 0 2006.201.19:56:18.90#ibcon#enter sib2, iclass 6, count 0 2006.201.19:56:18.90#ibcon#flushed, iclass 6, count 0 2006.201.19:56:18.90#ibcon#about to write, iclass 6, count 0 2006.201.19:56:18.90#ibcon#wrote, iclass 6, count 0 2006.201.19:56:18.90#ibcon#about to read 3, iclass 6, count 0 2006.201.19:56:18.92#ibcon#read 3, iclass 6, count 0 2006.201.19:56:18.92#ibcon#about to read 4, iclass 6, count 0 2006.201.19:56:18.92#ibcon#read 4, iclass 6, count 0 2006.201.19:56:18.92#ibcon#about to read 5, iclass 6, count 0 2006.201.19:56:18.92#ibcon#read 5, iclass 6, count 0 2006.201.19:56:18.92#ibcon#about to read 6, iclass 6, count 0 2006.201.19:56:18.92#ibcon#read 6, iclass 6, count 0 2006.201.19:56:18.92#ibcon#end of sib2, iclass 6, count 0 2006.201.19:56:18.92#ibcon#*mode == 0, iclass 6, count 0 2006.201.19:56:18.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.19:56:18.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:56:18.92#ibcon#*before write, iclass 6, count 0 2006.201.19:56:18.92#ibcon#enter sib2, iclass 6, count 0 2006.201.19:56:18.92#ibcon#flushed, iclass 6, count 0 2006.201.19:56:18.92#ibcon#about to write, iclass 6, count 0 2006.201.19:56:18.92#ibcon#wrote, iclass 6, count 0 2006.201.19:56:18.92#ibcon#about to read 3, iclass 6, count 0 2006.201.19:56:18.96#ibcon#read 3, iclass 6, count 0 2006.201.19:56:18.96#ibcon#about to read 4, iclass 6, count 0 2006.201.19:56:18.96#ibcon#read 4, iclass 6, count 0 2006.201.19:56:18.96#ibcon#about to read 5, iclass 6, count 0 2006.201.19:56:18.96#ibcon#read 5, iclass 6, count 0 2006.201.19:56:18.96#ibcon#about to read 6, iclass 6, count 0 2006.201.19:56:18.96#ibcon#read 6, iclass 6, count 0 2006.201.19:56:18.96#ibcon#end of sib2, iclass 6, count 0 2006.201.19:56:18.96#ibcon#*after write, iclass 6, count 0 2006.201.19:56:18.96#ibcon#*before return 0, iclass 6, count 0 2006.201.19:56:18.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:18.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:18.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.19:56:18.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.19:56:18.96$vck44/va=7,5 2006.201.19:56:18.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.19:56:18.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.19:56:18.96#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:18.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:19.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:19.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:19.02#ibcon#enter wrdev, iclass 10, count 2 2006.201.19:56:19.02#ibcon#first serial, iclass 10, count 2 2006.201.19:56:19.02#ibcon#enter sib2, iclass 10, count 2 2006.201.19:56:19.02#ibcon#flushed, iclass 10, count 2 2006.201.19:56:19.02#ibcon#about to write, iclass 10, count 2 2006.201.19:56:19.02#ibcon#wrote, iclass 10, count 2 2006.201.19:56:19.02#ibcon#about to read 3, iclass 10, count 2 2006.201.19:56:19.04#ibcon#read 3, iclass 10, count 2 2006.201.19:56:19.04#ibcon#about to read 4, iclass 10, count 2 2006.201.19:56:19.04#ibcon#read 4, iclass 10, count 2 2006.201.19:56:19.04#ibcon#about to read 5, iclass 10, count 2 2006.201.19:56:19.04#ibcon#read 5, iclass 10, count 2 2006.201.19:56:19.04#ibcon#about to read 6, iclass 10, count 2 2006.201.19:56:19.04#ibcon#read 6, iclass 10, count 2 2006.201.19:56:19.04#ibcon#end of sib2, iclass 10, count 2 2006.201.19:56:19.04#ibcon#*mode == 0, iclass 10, count 2 2006.201.19:56:19.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.19:56:19.04#ibcon#[25=AT07-05\r\n] 2006.201.19:56:19.04#ibcon#*before write, iclass 10, count 2 2006.201.19:56:19.04#ibcon#enter sib2, iclass 10, count 2 2006.201.19:56:19.04#ibcon#flushed, iclass 10, count 2 2006.201.19:56:19.04#ibcon#about to write, iclass 10, count 2 2006.201.19:56:19.04#ibcon#wrote, iclass 10, count 2 2006.201.19:56:19.04#ibcon#about to read 3, iclass 10, count 2 2006.201.19:56:19.07#ibcon#read 3, iclass 10, count 2 2006.201.19:56:19.07#ibcon#about to read 4, iclass 10, count 2 2006.201.19:56:19.07#ibcon#read 4, iclass 10, count 2 2006.201.19:56:19.07#ibcon#about to read 5, iclass 10, count 2 2006.201.19:56:19.07#ibcon#read 5, iclass 10, count 2 2006.201.19:56:19.07#ibcon#about to read 6, iclass 10, count 2 2006.201.19:56:19.07#ibcon#read 6, iclass 10, count 2 2006.201.19:56:19.07#ibcon#end of sib2, iclass 10, count 2 2006.201.19:56:19.07#ibcon#*after write, iclass 10, count 2 2006.201.19:56:19.07#ibcon#*before return 0, iclass 10, count 2 2006.201.19:56:19.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:19.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:19.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.19:56:19.07#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:19.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:19.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:19.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:19.19#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:56:19.19#ibcon#first serial, iclass 10, count 0 2006.201.19:56:19.19#ibcon#enter sib2, iclass 10, count 0 2006.201.19:56:19.19#ibcon#flushed, iclass 10, count 0 2006.201.19:56:19.19#ibcon#about to write, iclass 10, count 0 2006.201.19:56:19.19#ibcon#wrote, iclass 10, count 0 2006.201.19:56:19.19#ibcon#about to read 3, iclass 10, count 0 2006.201.19:56:19.21#ibcon#read 3, iclass 10, count 0 2006.201.19:56:19.21#ibcon#about to read 4, iclass 10, count 0 2006.201.19:56:19.21#ibcon#read 4, iclass 10, count 0 2006.201.19:56:19.21#ibcon#about to read 5, iclass 10, count 0 2006.201.19:56:19.21#ibcon#read 5, iclass 10, count 0 2006.201.19:56:19.21#ibcon#about to read 6, iclass 10, count 0 2006.201.19:56:19.21#ibcon#read 6, iclass 10, count 0 2006.201.19:56:19.21#ibcon#end of sib2, iclass 10, count 0 2006.201.19:56:19.21#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:56:19.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:56:19.21#ibcon#[25=USB\r\n] 2006.201.19:56:19.21#ibcon#*before write, iclass 10, count 0 2006.201.19:56:19.21#ibcon#enter sib2, iclass 10, count 0 2006.201.19:56:19.21#ibcon#flushed, iclass 10, count 0 2006.201.19:56:19.21#ibcon#about to write, iclass 10, count 0 2006.201.19:56:19.21#ibcon#wrote, iclass 10, count 0 2006.201.19:56:19.21#ibcon#about to read 3, iclass 10, count 0 2006.201.19:56:19.24#ibcon#read 3, iclass 10, count 0 2006.201.19:56:19.24#ibcon#about to read 4, iclass 10, count 0 2006.201.19:56:19.24#ibcon#read 4, iclass 10, count 0 2006.201.19:56:19.24#ibcon#about to read 5, iclass 10, count 0 2006.201.19:56:19.24#ibcon#read 5, iclass 10, count 0 2006.201.19:56:19.24#ibcon#about to read 6, iclass 10, count 0 2006.201.19:56:19.24#ibcon#read 6, iclass 10, count 0 2006.201.19:56:19.24#ibcon#end of sib2, iclass 10, count 0 2006.201.19:56:19.24#ibcon#*after write, iclass 10, count 0 2006.201.19:56:19.24#ibcon#*before return 0, iclass 10, count 0 2006.201.19:56:19.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:19.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:19.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:56:19.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:56:19.24$vck44/valo=8,884.99 2006.201.19:56:19.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.19:56:19.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.19:56:19.24#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:19.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:19.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:19.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:19.24#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:56:19.24#ibcon#first serial, iclass 12, count 0 2006.201.19:56:19.24#ibcon#enter sib2, iclass 12, count 0 2006.201.19:56:19.24#ibcon#flushed, iclass 12, count 0 2006.201.19:56:19.24#ibcon#about to write, iclass 12, count 0 2006.201.19:56:19.24#ibcon#wrote, iclass 12, count 0 2006.201.19:56:19.24#ibcon#about to read 3, iclass 12, count 0 2006.201.19:56:19.26#ibcon#read 3, iclass 12, count 0 2006.201.19:56:19.26#ibcon#about to read 4, iclass 12, count 0 2006.201.19:56:19.26#ibcon#read 4, iclass 12, count 0 2006.201.19:56:19.26#ibcon#about to read 5, iclass 12, count 0 2006.201.19:56:19.26#ibcon#read 5, iclass 12, count 0 2006.201.19:56:19.26#ibcon#about to read 6, iclass 12, count 0 2006.201.19:56:19.26#ibcon#read 6, iclass 12, count 0 2006.201.19:56:19.26#ibcon#end of sib2, iclass 12, count 0 2006.201.19:56:19.26#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:56:19.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:56:19.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:56:19.26#ibcon#*before write, iclass 12, count 0 2006.201.19:56:19.26#ibcon#enter sib2, iclass 12, count 0 2006.201.19:56:19.26#ibcon#flushed, iclass 12, count 0 2006.201.19:56:19.26#ibcon#about to write, iclass 12, count 0 2006.201.19:56:19.26#ibcon#wrote, iclass 12, count 0 2006.201.19:56:19.26#ibcon#about to read 3, iclass 12, count 0 2006.201.19:56:19.31#ibcon#read 3, iclass 12, count 0 2006.201.19:56:19.31#ibcon#about to read 4, iclass 12, count 0 2006.201.19:56:19.31#ibcon#read 4, iclass 12, count 0 2006.201.19:56:19.31#ibcon#about to read 5, iclass 12, count 0 2006.201.19:56:19.31#ibcon#read 5, iclass 12, count 0 2006.201.19:56:19.31#ibcon#about to read 6, iclass 12, count 0 2006.201.19:56:19.31#ibcon#read 6, iclass 12, count 0 2006.201.19:56:19.31#ibcon#end of sib2, iclass 12, count 0 2006.201.19:56:19.31#ibcon#*after write, iclass 12, count 0 2006.201.19:56:19.31#ibcon#*before return 0, iclass 12, count 0 2006.201.19:56:19.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:19.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:19.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:56:19.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:56:19.31$vck44/va=8,4 2006.201.19:56:19.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.19:56:19.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.19:56:19.31#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:19.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:56:19.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:56:19.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:56:19.36#ibcon#enter wrdev, iclass 14, count 2 2006.201.19:56:19.36#ibcon#first serial, iclass 14, count 2 2006.201.19:56:19.36#ibcon#enter sib2, iclass 14, count 2 2006.201.19:56:19.36#ibcon#flushed, iclass 14, count 2 2006.201.19:56:19.36#ibcon#about to write, iclass 14, count 2 2006.201.19:56:19.36#ibcon#wrote, iclass 14, count 2 2006.201.19:56:19.36#ibcon#about to read 3, iclass 14, count 2 2006.201.19:56:19.38#ibcon#read 3, iclass 14, count 2 2006.201.19:56:19.38#ibcon#about to read 4, iclass 14, count 2 2006.201.19:56:19.38#ibcon#read 4, iclass 14, count 2 2006.201.19:56:19.38#ibcon#about to read 5, iclass 14, count 2 2006.201.19:56:19.38#ibcon#read 5, iclass 14, count 2 2006.201.19:56:19.38#ibcon#about to read 6, iclass 14, count 2 2006.201.19:56:19.38#ibcon#read 6, iclass 14, count 2 2006.201.19:56:19.38#ibcon#end of sib2, iclass 14, count 2 2006.201.19:56:19.38#ibcon#*mode == 0, iclass 14, count 2 2006.201.19:56:19.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.19:56:19.38#ibcon#[25=AT08-04\r\n] 2006.201.19:56:19.38#ibcon#*before write, iclass 14, count 2 2006.201.19:56:19.38#ibcon#enter sib2, iclass 14, count 2 2006.201.19:56:19.38#ibcon#flushed, iclass 14, count 2 2006.201.19:56:19.38#ibcon#about to write, iclass 14, count 2 2006.201.19:56:19.38#ibcon#wrote, iclass 14, count 2 2006.201.19:56:19.38#ibcon#about to read 3, iclass 14, count 2 2006.201.19:56:19.41#ibcon#read 3, iclass 14, count 2 2006.201.19:56:19.41#ibcon#about to read 4, iclass 14, count 2 2006.201.19:56:19.41#ibcon#read 4, iclass 14, count 2 2006.201.19:56:19.41#ibcon#about to read 5, iclass 14, count 2 2006.201.19:56:19.41#ibcon#read 5, iclass 14, count 2 2006.201.19:56:19.41#ibcon#about to read 6, iclass 14, count 2 2006.201.19:56:19.41#ibcon#read 6, iclass 14, count 2 2006.201.19:56:19.41#ibcon#end of sib2, iclass 14, count 2 2006.201.19:56:19.41#ibcon#*after write, iclass 14, count 2 2006.201.19:56:19.41#ibcon#*before return 0, iclass 14, count 2 2006.201.19:56:19.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:56:19.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.19:56:19.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.19:56:19.41#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:19.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:56:19.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:56:19.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:56:19.53#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:56:19.53#ibcon#first serial, iclass 14, count 0 2006.201.19:56:19.53#ibcon#enter sib2, iclass 14, count 0 2006.201.19:56:19.53#ibcon#flushed, iclass 14, count 0 2006.201.19:56:19.53#ibcon#about to write, iclass 14, count 0 2006.201.19:56:19.53#ibcon#wrote, iclass 14, count 0 2006.201.19:56:19.53#ibcon#about to read 3, iclass 14, count 0 2006.201.19:56:19.55#ibcon#read 3, iclass 14, count 0 2006.201.19:56:19.55#ibcon#about to read 4, iclass 14, count 0 2006.201.19:56:19.55#ibcon#read 4, iclass 14, count 0 2006.201.19:56:19.55#ibcon#about to read 5, iclass 14, count 0 2006.201.19:56:19.55#ibcon#read 5, iclass 14, count 0 2006.201.19:56:19.55#ibcon#about to read 6, iclass 14, count 0 2006.201.19:56:19.55#ibcon#read 6, iclass 14, count 0 2006.201.19:56:19.55#ibcon#end of sib2, iclass 14, count 0 2006.201.19:56:19.55#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:56:19.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:56:19.55#ibcon#[25=USB\r\n] 2006.201.19:56:19.55#ibcon#*before write, iclass 14, count 0 2006.201.19:56:19.55#ibcon#enter sib2, iclass 14, count 0 2006.201.19:56:19.55#ibcon#flushed, iclass 14, count 0 2006.201.19:56:19.55#ibcon#about to write, iclass 14, count 0 2006.201.19:56:19.55#ibcon#wrote, iclass 14, count 0 2006.201.19:56:19.55#ibcon#about to read 3, iclass 14, count 0 2006.201.19:56:19.58#ibcon#read 3, iclass 14, count 0 2006.201.19:56:19.58#ibcon#about to read 4, iclass 14, count 0 2006.201.19:56:19.58#ibcon#read 4, iclass 14, count 0 2006.201.19:56:19.58#ibcon#about to read 5, iclass 14, count 0 2006.201.19:56:19.58#ibcon#read 5, iclass 14, count 0 2006.201.19:56:19.58#ibcon#about to read 6, iclass 14, count 0 2006.201.19:56:19.58#ibcon#read 6, iclass 14, count 0 2006.201.19:56:19.58#ibcon#end of sib2, iclass 14, count 0 2006.201.19:56:19.58#ibcon#*after write, iclass 14, count 0 2006.201.19:56:19.58#ibcon#*before return 0, iclass 14, count 0 2006.201.19:56:19.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:56:19.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.19:56:19.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:56:19.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:56:19.58$vck44/vblo=1,629.99 2006.201.19:56:19.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.19:56:19.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.19:56:19.58#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:19.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:56:19.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:56:19.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:56:19.58#ibcon#enter wrdev, iclass 16, count 0 2006.201.19:56:19.58#ibcon#first serial, iclass 16, count 0 2006.201.19:56:19.58#ibcon#enter sib2, iclass 16, count 0 2006.201.19:56:19.58#ibcon#flushed, iclass 16, count 0 2006.201.19:56:19.58#ibcon#about to write, iclass 16, count 0 2006.201.19:56:19.58#ibcon#wrote, iclass 16, count 0 2006.201.19:56:19.58#ibcon#about to read 3, iclass 16, count 0 2006.201.19:56:19.60#ibcon#read 3, iclass 16, count 0 2006.201.19:56:19.60#ibcon#about to read 4, iclass 16, count 0 2006.201.19:56:19.60#ibcon#read 4, iclass 16, count 0 2006.201.19:56:19.60#ibcon#about to read 5, iclass 16, count 0 2006.201.19:56:19.60#ibcon#read 5, iclass 16, count 0 2006.201.19:56:19.60#ibcon#about to read 6, iclass 16, count 0 2006.201.19:56:19.60#ibcon#read 6, iclass 16, count 0 2006.201.19:56:19.60#ibcon#end of sib2, iclass 16, count 0 2006.201.19:56:19.60#ibcon#*mode == 0, iclass 16, count 0 2006.201.19:56:19.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.19:56:19.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:56:19.60#ibcon#*before write, iclass 16, count 0 2006.201.19:56:19.60#ibcon#enter sib2, iclass 16, count 0 2006.201.19:56:19.60#ibcon#flushed, iclass 16, count 0 2006.201.19:56:19.60#ibcon#about to write, iclass 16, count 0 2006.201.19:56:19.60#ibcon#wrote, iclass 16, count 0 2006.201.19:56:19.60#ibcon#about to read 3, iclass 16, count 0 2006.201.19:56:19.64#ibcon#read 3, iclass 16, count 0 2006.201.19:56:19.64#ibcon#about to read 4, iclass 16, count 0 2006.201.19:56:19.64#ibcon#read 4, iclass 16, count 0 2006.201.19:56:19.64#ibcon#about to read 5, iclass 16, count 0 2006.201.19:56:19.64#ibcon#read 5, iclass 16, count 0 2006.201.19:56:19.64#ibcon#about to read 6, iclass 16, count 0 2006.201.19:56:19.64#ibcon#read 6, iclass 16, count 0 2006.201.19:56:19.64#ibcon#end of sib2, iclass 16, count 0 2006.201.19:56:19.64#ibcon#*after write, iclass 16, count 0 2006.201.19:56:19.64#ibcon#*before return 0, iclass 16, count 0 2006.201.19:56:19.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:56:19.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.19:56:19.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.19:56:19.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.19:56:19.64$vck44/vb=1,4 2006.201.19:56:19.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.19:56:19.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.19:56:19.64#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:19.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:56:19.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:56:19.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:56:19.64#ibcon#enter wrdev, iclass 18, count 2 2006.201.19:56:19.64#ibcon#first serial, iclass 18, count 2 2006.201.19:56:19.64#ibcon#enter sib2, iclass 18, count 2 2006.201.19:56:19.64#ibcon#flushed, iclass 18, count 2 2006.201.19:56:19.64#ibcon#about to write, iclass 18, count 2 2006.201.19:56:19.64#ibcon#wrote, iclass 18, count 2 2006.201.19:56:19.64#ibcon#about to read 3, iclass 18, count 2 2006.201.19:56:19.66#ibcon#read 3, iclass 18, count 2 2006.201.19:56:19.66#ibcon#about to read 4, iclass 18, count 2 2006.201.19:56:19.66#ibcon#read 4, iclass 18, count 2 2006.201.19:56:19.66#ibcon#about to read 5, iclass 18, count 2 2006.201.19:56:19.66#ibcon#read 5, iclass 18, count 2 2006.201.19:56:19.66#ibcon#about to read 6, iclass 18, count 2 2006.201.19:56:19.66#ibcon#read 6, iclass 18, count 2 2006.201.19:56:19.66#ibcon#end of sib2, iclass 18, count 2 2006.201.19:56:19.66#ibcon#*mode == 0, iclass 18, count 2 2006.201.19:56:19.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.19:56:19.66#ibcon#[27=AT01-04\r\n] 2006.201.19:56:19.66#ibcon#*before write, iclass 18, count 2 2006.201.19:56:19.66#ibcon#enter sib2, iclass 18, count 2 2006.201.19:56:19.66#ibcon#flushed, iclass 18, count 2 2006.201.19:56:19.66#ibcon#about to write, iclass 18, count 2 2006.201.19:56:19.66#ibcon#wrote, iclass 18, count 2 2006.201.19:56:19.66#ibcon#about to read 3, iclass 18, count 2 2006.201.19:56:19.69#ibcon#read 3, iclass 18, count 2 2006.201.19:56:19.69#ibcon#about to read 4, iclass 18, count 2 2006.201.19:56:19.69#ibcon#read 4, iclass 18, count 2 2006.201.19:56:19.69#ibcon#about to read 5, iclass 18, count 2 2006.201.19:56:19.69#ibcon#read 5, iclass 18, count 2 2006.201.19:56:19.69#ibcon#about to read 6, iclass 18, count 2 2006.201.19:56:19.69#ibcon#read 6, iclass 18, count 2 2006.201.19:56:19.69#ibcon#end of sib2, iclass 18, count 2 2006.201.19:56:19.69#ibcon#*after write, iclass 18, count 2 2006.201.19:56:19.69#ibcon#*before return 0, iclass 18, count 2 2006.201.19:56:19.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:56:19.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.19:56:19.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.19:56:19.69#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:19.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:56:19.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:56:19.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:56:19.81#ibcon#enter wrdev, iclass 18, count 0 2006.201.19:56:19.81#ibcon#first serial, iclass 18, count 0 2006.201.19:56:19.81#ibcon#enter sib2, iclass 18, count 0 2006.201.19:56:19.81#ibcon#flushed, iclass 18, count 0 2006.201.19:56:19.81#ibcon#about to write, iclass 18, count 0 2006.201.19:56:19.81#ibcon#wrote, iclass 18, count 0 2006.201.19:56:19.81#ibcon#about to read 3, iclass 18, count 0 2006.201.19:56:19.83#ibcon#read 3, iclass 18, count 0 2006.201.19:56:19.83#ibcon#about to read 4, iclass 18, count 0 2006.201.19:56:19.83#ibcon#read 4, iclass 18, count 0 2006.201.19:56:19.83#ibcon#about to read 5, iclass 18, count 0 2006.201.19:56:19.83#ibcon#read 5, iclass 18, count 0 2006.201.19:56:19.83#ibcon#about to read 6, iclass 18, count 0 2006.201.19:56:19.83#ibcon#read 6, iclass 18, count 0 2006.201.19:56:19.83#ibcon#end of sib2, iclass 18, count 0 2006.201.19:56:19.83#ibcon#*mode == 0, iclass 18, count 0 2006.201.19:56:19.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.19:56:19.83#ibcon#[27=USB\r\n] 2006.201.19:56:19.83#ibcon#*before write, iclass 18, count 0 2006.201.19:56:19.83#ibcon#enter sib2, iclass 18, count 0 2006.201.19:56:19.83#ibcon#flushed, iclass 18, count 0 2006.201.19:56:19.83#ibcon#about to write, iclass 18, count 0 2006.201.19:56:19.83#ibcon#wrote, iclass 18, count 0 2006.201.19:56:19.83#ibcon#about to read 3, iclass 18, count 0 2006.201.19:56:19.86#ibcon#read 3, iclass 18, count 0 2006.201.19:56:19.86#ibcon#about to read 4, iclass 18, count 0 2006.201.19:56:19.86#ibcon#read 4, iclass 18, count 0 2006.201.19:56:19.86#ibcon#about to read 5, iclass 18, count 0 2006.201.19:56:19.86#ibcon#read 5, iclass 18, count 0 2006.201.19:56:19.86#ibcon#about to read 6, iclass 18, count 0 2006.201.19:56:19.86#ibcon#read 6, iclass 18, count 0 2006.201.19:56:19.86#ibcon#end of sib2, iclass 18, count 0 2006.201.19:56:19.86#ibcon#*after write, iclass 18, count 0 2006.201.19:56:19.86#ibcon#*before return 0, iclass 18, count 0 2006.201.19:56:19.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:56:19.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.19:56:19.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.19:56:19.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.19:56:19.86$vck44/vblo=2,634.99 2006.201.19:56:19.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.19:56:19.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.19:56:19.86#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:19.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:19.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:19.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:19.86#ibcon#enter wrdev, iclass 20, count 0 2006.201.19:56:19.86#ibcon#first serial, iclass 20, count 0 2006.201.19:56:19.86#ibcon#enter sib2, iclass 20, count 0 2006.201.19:56:19.86#ibcon#flushed, iclass 20, count 0 2006.201.19:56:19.86#ibcon#about to write, iclass 20, count 0 2006.201.19:56:19.86#ibcon#wrote, iclass 20, count 0 2006.201.19:56:19.86#ibcon#about to read 3, iclass 20, count 0 2006.201.19:56:19.88#ibcon#read 3, iclass 20, count 0 2006.201.19:56:19.88#ibcon#about to read 4, iclass 20, count 0 2006.201.19:56:19.88#ibcon#read 4, iclass 20, count 0 2006.201.19:56:19.88#ibcon#about to read 5, iclass 20, count 0 2006.201.19:56:19.88#ibcon#read 5, iclass 20, count 0 2006.201.19:56:19.88#ibcon#about to read 6, iclass 20, count 0 2006.201.19:56:19.88#ibcon#read 6, iclass 20, count 0 2006.201.19:56:19.88#ibcon#end of sib2, iclass 20, count 0 2006.201.19:56:19.88#ibcon#*mode == 0, iclass 20, count 0 2006.201.19:56:19.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.19:56:19.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:56:19.88#ibcon#*before write, iclass 20, count 0 2006.201.19:56:19.88#ibcon#enter sib2, iclass 20, count 0 2006.201.19:56:19.88#ibcon#flushed, iclass 20, count 0 2006.201.19:56:19.88#ibcon#about to write, iclass 20, count 0 2006.201.19:56:19.88#ibcon#wrote, iclass 20, count 0 2006.201.19:56:19.88#ibcon#about to read 3, iclass 20, count 0 2006.201.19:56:19.92#ibcon#read 3, iclass 20, count 0 2006.201.19:56:19.92#ibcon#about to read 4, iclass 20, count 0 2006.201.19:56:19.92#ibcon#read 4, iclass 20, count 0 2006.201.19:56:19.92#ibcon#about to read 5, iclass 20, count 0 2006.201.19:56:19.92#ibcon#read 5, iclass 20, count 0 2006.201.19:56:19.92#ibcon#about to read 6, iclass 20, count 0 2006.201.19:56:19.92#ibcon#read 6, iclass 20, count 0 2006.201.19:56:19.92#ibcon#end of sib2, iclass 20, count 0 2006.201.19:56:19.92#ibcon#*after write, iclass 20, count 0 2006.201.19:56:19.92#ibcon#*before return 0, iclass 20, count 0 2006.201.19:56:19.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:19.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.19:56:19.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.19:56:19.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.19:56:19.92$vck44/vb=2,5 2006.201.19:56:19.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.19:56:19.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.19:56:19.92#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:19.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:19.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:19.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:19.98#ibcon#enter wrdev, iclass 22, count 2 2006.201.19:56:19.98#ibcon#first serial, iclass 22, count 2 2006.201.19:56:19.98#ibcon#enter sib2, iclass 22, count 2 2006.201.19:56:19.98#ibcon#flushed, iclass 22, count 2 2006.201.19:56:19.98#ibcon#about to write, iclass 22, count 2 2006.201.19:56:19.98#ibcon#wrote, iclass 22, count 2 2006.201.19:56:19.98#ibcon#about to read 3, iclass 22, count 2 2006.201.19:56:20.00#ibcon#read 3, iclass 22, count 2 2006.201.19:56:20.00#ibcon#about to read 4, iclass 22, count 2 2006.201.19:56:20.00#ibcon#read 4, iclass 22, count 2 2006.201.19:56:20.00#ibcon#about to read 5, iclass 22, count 2 2006.201.19:56:20.00#ibcon#read 5, iclass 22, count 2 2006.201.19:56:20.00#ibcon#about to read 6, iclass 22, count 2 2006.201.19:56:20.00#ibcon#read 6, iclass 22, count 2 2006.201.19:56:20.00#ibcon#end of sib2, iclass 22, count 2 2006.201.19:56:20.00#ibcon#*mode == 0, iclass 22, count 2 2006.201.19:56:20.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.19:56:20.00#ibcon#[27=AT02-05\r\n] 2006.201.19:56:20.00#ibcon#*before write, iclass 22, count 2 2006.201.19:56:20.00#ibcon#enter sib2, iclass 22, count 2 2006.201.19:56:20.00#ibcon#flushed, iclass 22, count 2 2006.201.19:56:20.00#ibcon#about to write, iclass 22, count 2 2006.201.19:56:20.00#ibcon#wrote, iclass 22, count 2 2006.201.19:56:20.00#ibcon#about to read 3, iclass 22, count 2 2006.201.19:56:20.03#ibcon#read 3, iclass 22, count 2 2006.201.19:56:20.03#ibcon#about to read 4, iclass 22, count 2 2006.201.19:56:20.03#ibcon#read 4, iclass 22, count 2 2006.201.19:56:20.03#ibcon#about to read 5, iclass 22, count 2 2006.201.19:56:20.03#ibcon#read 5, iclass 22, count 2 2006.201.19:56:20.03#ibcon#about to read 6, iclass 22, count 2 2006.201.19:56:20.03#ibcon#read 6, iclass 22, count 2 2006.201.19:56:20.03#ibcon#end of sib2, iclass 22, count 2 2006.201.19:56:20.03#ibcon#*after write, iclass 22, count 2 2006.201.19:56:20.03#ibcon#*before return 0, iclass 22, count 2 2006.201.19:56:20.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:20.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.19:56:20.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.19:56:20.03#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:20.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:20.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:20.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:20.15#ibcon#enter wrdev, iclass 22, count 0 2006.201.19:56:20.15#ibcon#first serial, iclass 22, count 0 2006.201.19:56:20.15#ibcon#enter sib2, iclass 22, count 0 2006.201.19:56:20.15#ibcon#flushed, iclass 22, count 0 2006.201.19:56:20.15#ibcon#about to write, iclass 22, count 0 2006.201.19:56:20.15#ibcon#wrote, iclass 22, count 0 2006.201.19:56:20.15#ibcon#about to read 3, iclass 22, count 0 2006.201.19:56:20.17#ibcon#read 3, iclass 22, count 0 2006.201.19:56:20.17#ibcon#about to read 4, iclass 22, count 0 2006.201.19:56:20.17#ibcon#read 4, iclass 22, count 0 2006.201.19:56:20.17#ibcon#about to read 5, iclass 22, count 0 2006.201.19:56:20.17#ibcon#read 5, iclass 22, count 0 2006.201.19:56:20.17#ibcon#about to read 6, iclass 22, count 0 2006.201.19:56:20.17#ibcon#read 6, iclass 22, count 0 2006.201.19:56:20.17#ibcon#end of sib2, iclass 22, count 0 2006.201.19:56:20.17#ibcon#*mode == 0, iclass 22, count 0 2006.201.19:56:20.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.19:56:20.17#ibcon#[27=USB\r\n] 2006.201.19:56:20.17#ibcon#*before write, iclass 22, count 0 2006.201.19:56:20.17#ibcon#enter sib2, iclass 22, count 0 2006.201.19:56:20.17#ibcon#flushed, iclass 22, count 0 2006.201.19:56:20.17#ibcon#about to write, iclass 22, count 0 2006.201.19:56:20.17#ibcon#wrote, iclass 22, count 0 2006.201.19:56:20.17#ibcon#about to read 3, iclass 22, count 0 2006.201.19:56:20.20#ibcon#read 3, iclass 22, count 0 2006.201.19:56:20.20#ibcon#about to read 4, iclass 22, count 0 2006.201.19:56:20.20#ibcon#read 4, iclass 22, count 0 2006.201.19:56:20.20#ibcon#about to read 5, iclass 22, count 0 2006.201.19:56:20.20#ibcon#read 5, iclass 22, count 0 2006.201.19:56:20.20#ibcon#about to read 6, iclass 22, count 0 2006.201.19:56:20.20#ibcon#read 6, iclass 22, count 0 2006.201.19:56:20.20#ibcon#end of sib2, iclass 22, count 0 2006.201.19:56:20.20#ibcon#*after write, iclass 22, count 0 2006.201.19:56:20.20#ibcon#*before return 0, iclass 22, count 0 2006.201.19:56:20.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:20.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.19:56:20.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.19:56:20.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.19:56:20.20$vck44/vblo=3,649.99 2006.201.19:56:20.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.19:56:20.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.19:56:20.20#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:20.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:20.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:20.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:20.20#ibcon#enter wrdev, iclass 24, count 0 2006.201.19:56:20.20#ibcon#first serial, iclass 24, count 0 2006.201.19:56:20.20#ibcon#enter sib2, iclass 24, count 0 2006.201.19:56:20.20#ibcon#flushed, iclass 24, count 0 2006.201.19:56:20.20#ibcon#about to write, iclass 24, count 0 2006.201.19:56:20.20#ibcon#wrote, iclass 24, count 0 2006.201.19:56:20.20#ibcon#about to read 3, iclass 24, count 0 2006.201.19:56:20.22#ibcon#read 3, iclass 24, count 0 2006.201.19:56:20.22#ibcon#about to read 4, iclass 24, count 0 2006.201.19:56:20.22#ibcon#read 4, iclass 24, count 0 2006.201.19:56:20.22#ibcon#about to read 5, iclass 24, count 0 2006.201.19:56:20.22#ibcon#read 5, iclass 24, count 0 2006.201.19:56:20.22#ibcon#about to read 6, iclass 24, count 0 2006.201.19:56:20.22#ibcon#read 6, iclass 24, count 0 2006.201.19:56:20.22#ibcon#end of sib2, iclass 24, count 0 2006.201.19:56:20.22#ibcon#*mode == 0, iclass 24, count 0 2006.201.19:56:20.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.19:56:20.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:56:20.22#ibcon#*before write, iclass 24, count 0 2006.201.19:56:20.22#ibcon#enter sib2, iclass 24, count 0 2006.201.19:56:20.22#ibcon#flushed, iclass 24, count 0 2006.201.19:56:20.22#ibcon#about to write, iclass 24, count 0 2006.201.19:56:20.22#ibcon#wrote, iclass 24, count 0 2006.201.19:56:20.22#ibcon#about to read 3, iclass 24, count 0 2006.201.19:56:20.26#ibcon#read 3, iclass 24, count 0 2006.201.19:56:20.26#ibcon#about to read 4, iclass 24, count 0 2006.201.19:56:20.26#ibcon#read 4, iclass 24, count 0 2006.201.19:56:20.26#ibcon#about to read 5, iclass 24, count 0 2006.201.19:56:20.26#ibcon#read 5, iclass 24, count 0 2006.201.19:56:20.26#ibcon#about to read 6, iclass 24, count 0 2006.201.19:56:20.26#ibcon#read 6, iclass 24, count 0 2006.201.19:56:20.26#ibcon#end of sib2, iclass 24, count 0 2006.201.19:56:20.26#ibcon#*after write, iclass 24, count 0 2006.201.19:56:20.26#ibcon#*before return 0, iclass 24, count 0 2006.201.19:56:20.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:20.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.19:56:20.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.19:56:20.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.19:56:20.26$vck44/vb=3,4 2006.201.19:56:20.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.19:56:20.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.19:56:20.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:20.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:20.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:20.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:20.32#ibcon#enter wrdev, iclass 26, count 2 2006.201.19:56:20.32#ibcon#first serial, iclass 26, count 2 2006.201.19:56:20.32#ibcon#enter sib2, iclass 26, count 2 2006.201.19:56:20.32#ibcon#flushed, iclass 26, count 2 2006.201.19:56:20.32#ibcon#about to write, iclass 26, count 2 2006.201.19:56:20.32#ibcon#wrote, iclass 26, count 2 2006.201.19:56:20.32#ibcon#about to read 3, iclass 26, count 2 2006.201.19:56:20.34#ibcon#read 3, iclass 26, count 2 2006.201.19:56:20.34#ibcon#about to read 4, iclass 26, count 2 2006.201.19:56:20.34#ibcon#read 4, iclass 26, count 2 2006.201.19:56:20.34#ibcon#about to read 5, iclass 26, count 2 2006.201.19:56:20.34#ibcon#read 5, iclass 26, count 2 2006.201.19:56:20.34#ibcon#about to read 6, iclass 26, count 2 2006.201.19:56:20.34#ibcon#read 6, iclass 26, count 2 2006.201.19:56:20.34#ibcon#end of sib2, iclass 26, count 2 2006.201.19:56:20.34#ibcon#*mode == 0, iclass 26, count 2 2006.201.19:56:20.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.19:56:20.34#ibcon#[27=AT03-04\r\n] 2006.201.19:56:20.34#ibcon#*before write, iclass 26, count 2 2006.201.19:56:20.34#ibcon#enter sib2, iclass 26, count 2 2006.201.19:56:20.34#ibcon#flushed, iclass 26, count 2 2006.201.19:56:20.34#ibcon#about to write, iclass 26, count 2 2006.201.19:56:20.34#ibcon#wrote, iclass 26, count 2 2006.201.19:56:20.34#ibcon#about to read 3, iclass 26, count 2 2006.201.19:56:20.37#ibcon#read 3, iclass 26, count 2 2006.201.19:56:20.37#ibcon#about to read 4, iclass 26, count 2 2006.201.19:56:20.37#ibcon#read 4, iclass 26, count 2 2006.201.19:56:20.37#ibcon#about to read 5, iclass 26, count 2 2006.201.19:56:20.37#ibcon#read 5, iclass 26, count 2 2006.201.19:56:20.37#ibcon#about to read 6, iclass 26, count 2 2006.201.19:56:20.37#ibcon#read 6, iclass 26, count 2 2006.201.19:56:20.37#ibcon#end of sib2, iclass 26, count 2 2006.201.19:56:20.37#ibcon#*after write, iclass 26, count 2 2006.201.19:56:20.37#ibcon#*before return 0, iclass 26, count 2 2006.201.19:56:20.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:20.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.19:56:20.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.19:56:20.37#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:20.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:20.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:20.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:20.49#ibcon#enter wrdev, iclass 26, count 0 2006.201.19:56:20.49#ibcon#first serial, iclass 26, count 0 2006.201.19:56:20.49#ibcon#enter sib2, iclass 26, count 0 2006.201.19:56:20.49#ibcon#flushed, iclass 26, count 0 2006.201.19:56:20.49#ibcon#about to write, iclass 26, count 0 2006.201.19:56:20.49#ibcon#wrote, iclass 26, count 0 2006.201.19:56:20.49#ibcon#about to read 3, iclass 26, count 0 2006.201.19:56:20.51#ibcon#read 3, iclass 26, count 0 2006.201.19:56:20.51#ibcon#about to read 4, iclass 26, count 0 2006.201.19:56:20.51#ibcon#read 4, iclass 26, count 0 2006.201.19:56:20.51#ibcon#about to read 5, iclass 26, count 0 2006.201.19:56:20.51#ibcon#read 5, iclass 26, count 0 2006.201.19:56:20.51#ibcon#about to read 6, iclass 26, count 0 2006.201.19:56:20.51#ibcon#read 6, iclass 26, count 0 2006.201.19:56:20.51#ibcon#end of sib2, iclass 26, count 0 2006.201.19:56:20.51#ibcon#*mode == 0, iclass 26, count 0 2006.201.19:56:20.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.19:56:20.51#ibcon#[27=USB\r\n] 2006.201.19:56:20.51#ibcon#*before write, iclass 26, count 0 2006.201.19:56:20.51#ibcon#enter sib2, iclass 26, count 0 2006.201.19:56:20.51#ibcon#flushed, iclass 26, count 0 2006.201.19:56:20.51#ibcon#about to write, iclass 26, count 0 2006.201.19:56:20.51#ibcon#wrote, iclass 26, count 0 2006.201.19:56:20.51#ibcon#about to read 3, iclass 26, count 0 2006.201.19:56:20.54#ibcon#read 3, iclass 26, count 0 2006.201.19:56:20.54#ibcon#about to read 4, iclass 26, count 0 2006.201.19:56:20.54#ibcon#read 4, iclass 26, count 0 2006.201.19:56:20.54#ibcon#about to read 5, iclass 26, count 0 2006.201.19:56:20.54#ibcon#read 5, iclass 26, count 0 2006.201.19:56:20.54#ibcon#about to read 6, iclass 26, count 0 2006.201.19:56:20.54#ibcon#read 6, iclass 26, count 0 2006.201.19:56:20.54#ibcon#end of sib2, iclass 26, count 0 2006.201.19:56:20.54#ibcon#*after write, iclass 26, count 0 2006.201.19:56:20.54#ibcon#*before return 0, iclass 26, count 0 2006.201.19:56:20.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:20.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.19:56:20.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.19:56:20.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.19:56:20.54$vck44/vblo=4,679.99 2006.201.19:56:20.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.19:56:20.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.19:56:20.54#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:20.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:20.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:20.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:20.54#ibcon#enter wrdev, iclass 28, count 0 2006.201.19:56:20.54#ibcon#first serial, iclass 28, count 0 2006.201.19:56:20.54#ibcon#enter sib2, iclass 28, count 0 2006.201.19:56:20.54#ibcon#flushed, iclass 28, count 0 2006.201.19:56:20.54#ibcon#about to write, iclass 28, count 0 2006.201.19:56:20.54#ibcon#wrote, iclass 28, count 0 2006.201.19:56:20.54#ibcon#about to read 3, iclass 28, count 0 2006.201.19:56:20.56#ibcon#read 3, iclass 28, count 0 2006.201.19:56:20.56#ibcon#about to read 4, iclass 28, count 0 2006.201.19:56:20.56#ibcon#read 4, iclass 28, count 0 2006.201.19:56:20.56#ibcon#about to read 5, iclass 28, count 0 2006.201.19:56:20.56#ibcon#read 5, iclass 28, count 0 2006.201.19:56:20.56#ibcon#about to read 6, iclass 28, count 0 2006.201.19:56:20.56#ibcon#read 6, iclass 28, count 0 2006.201.19:56:20.56#ibcon#end of sib2, iclass 28, count 0 2006.201.19:56:20.56#ibcon#*mode == 0, iclass 28, count 0 2006.201.19:56:20.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.19:56:20.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:56:20.56#ibcon#*before write, iclass 28, count 0 2006.201.19:56:20.56#ibcon#enter sib2, iclass 28, count 0 2006.201.19:56:20.56#ibcon#flushed, iclass 28, count 0 2006.201.19:56:20.56#ibcon#about to write, iclass 28, count 0 2006.201.19:56:20.56#ibcon#wrote, iclass 28, count 0 2006.201.19:56:20.56#ibcon#about to read 3, iclass 28, count 0 2006.201.19:56:20.60#ibcon#read 3, iclass 28, count 0 2006.201.19:56:20.60#ibcon#about to read 4, iclass 28, count 0 2006.201.19:56:20.60#ibcon#read 4, iclass 28, count 0 2006.201.19:56:20.60#ibcon#about to read 5, iclass 28, count 0 2006.201.19:56:20.60#ibcon#read 5, iclass 28, count 0 2006.201.19:56:20.60#ibcon#about to read 6, iclass 28, count 0 2006.201.19:56:20.60#ibcon#read 6, iclass 28, count 0 2006.201.19:56:20.60#ibcon#end of sib2, iclass 28, count 0 2006.201.19:56:20.60#ibcon#*after write, iclass 28, count 0 2006.201.19:56:20.60#ibcon#*before return 0, iclass 28, count 0 2006.201.19:56:20.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:20.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.19:56:20.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.19:56:20.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.19:56:20.60$vck44/vb=4,5 2006.201.19:56:20.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.19:56:20.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.19:56:20.60#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:20.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:20.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:20.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:20.66#ibcon#enter wrdev, iclass 30, count 2 2006.201.19:56:20.66#ibcon#first serial, iclass 30, count 2 2006.201.19:56:20.66#ibcon#enter sib2, iclass 30, count 2 2006.201.19:56:20.66#ibcon#flushed, iclass 30, count 2 2006.201.19:56:20.66#ibcon#about to write, iclass 30, count 2 2006.201.19:56:20.66#ibcon#wrote, iclass 30, count 2 2006.201.19:56:20.66#ibcon#about to read 3, iclass 30, count 2 2006.201.19:56:20.68#ibcon#read 3, iclass 30, count 2 2006.201.19:56:20.68#ibcon#about to read 4, iclass 30, count 2 2006.201.19:56:20.68#ibcon#read 4, iclass 30, count 2 2006.201.19:56:20.68#ibcon#about to read 5, iclass 30, count 2 2006.201.19:56:20.68#ibcon#read 5, iclass 30, count 2 2006.201.19:56:20.68#ibcon#about to read 6, iclass 30, count 2 2006.201.19:56:20.68#ibcon#read 6, iclass 30, count 2 2006.201.19:56:20.68#ibcon#end of sib2, iclass 30, count 2 2006.201.19:56:20.68#ibcon#*mode == 0, iclass 30, count 2 2006.201.19:56:20.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.19:56:20.68#ibcon#[27=AT04-05\r\n] 2006.201.19:56:20.68#ibcon#*before write, iclass 30, count 2 2006.201.19:56:20.68#ibcon#enter sib2, iclass 30, count 2 2006.201.19:56:20.68#ibcon#flushed, iclass 30, count 2 2006.201.19:56:20.68#ibcon#about to write, iclass 30, count 2 2006.201.19:56:20.68#ibcon#wrote, iclass 30, count 2 2006.201.19:56:20.68#ibcon#about to read 3, iclass 30, count 2 2006.201.19:56:20.71#ibcon#read 3, iclass 30, count 2 2006.201.19:56:20.71#ibcon#about to read 4, iclass 30, count 2 2006.201.19:56:20.71#ibcon#read 4, iclass 30, count 2 2006.201.19:56:20.71#ibcon#about to read 5, iclass 30, count 2 2006.201.19:56:20.71#ibcon#read 5, iclass 30, count 2 2006.201.19:56:20.71#ibcon#about to read 6, iclass 30, count 2 2006.201.19:56:20.71#ibcon#read 6, iclass 30, count 2 2006.201.19:56:20.71#ibcon#end of sib2, iclass 30, count 2 2006.201.19:56:20.71#ibcon#*after write, iclass 30, count 2 2006.201.19:56:20.71#ibcon#*before return 0, iclass 30, count 2 2006.201.19:56:20.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:20.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.19:56:20.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.19:56:20.71#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:20.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:20.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:20.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:20.83#ibcon#enter wrdev, iclass 30, count 0 2006.201.19:56:20.83#ibcon#first serial, iclass 30, count 0 2006.201.19:56:20.83#ibcon#enter sib2, iclass 30, count 0 2006.201.19:56:20.83#ibcon#flushed, iclass 30, count 0 2006.201.19:56:20.83#ibcon#about to write, iclass 30, count 0 2006.201.19:56:20.83#ibcon#wrote, iclass 30, count 0 2006.201.19:56:20.83#ibcon#about to read 3, iclass 30, count 0 2006.201.19:56:20.85#ibcon#read 3, iclass 30, count 0 2006.201.19:56:20.85#ibcon#about to read 4, iclass 30, count 0 2006.201.19:56:20.85#ibcon#read 4, iclass 30, count 0 2006.201.19:56:20.85#ibcon#about to read 5, iclass 30, count 0 2006.201.19:56:20.85#ibcon#read 5, iclass 30, count 0 2006.201.19:56:20.85#ibcon#about to read 6, iclass 30, count 0 2006.201.19:56:20.85#ibcon#read 6, iclass 30, count 0 2006.201.19:56:20.85#ibcon#end of sib2, iclass 30, count 0 2006.201.19:56:20.85#ibcon#*mode == 0, iclass 30, count 0 2006.201.19:56:20.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.19:56:20.85#ibcon#[27=USB\r\n] 2006.201.19:56:20.85#ibcon#*before write, iclass 30, count 0 2006.201.19:56:20.85#ibcon#enter sib2, iclass 30, count 0 2006.201.19:56:20.85#ibcon#flushed, iclass 30, count 0 2006.201.19:56:20.85#ibcon#about to write, iclass 30, count 0 2006.201.19:56:20.85#ibcon#wrote, iclass 30, count 0 2006.201.19:56:20.85#ibcon#about to read 3, iclass 30, count 0 2006.201.19:56:20.88#ibcon#read 3, iclass 30, count 0 2006.201.19:56:20.88#ibcon#about to read 4, iclass 30, count 0 2006.201.19:56:20.88#ibcon#read 4, iclass 30, count 0 2006.201.19:56:20.88#ibcon#about to read 5, iclass 30, count 0 2006.201.19:56:20.88#ibcon#read 5, iclass 30, count 0 2006.201.19:56:20.88#ibcon#about to read 6, iclass 30, count 0 2006.201.19:56:20.88#ibcon#read 6, iclass 30, count 0 2006.201.19:56:20.88#ibcon#end of sib2, iclass 30, count 0 2006.201.19:56:20.88#ibcon#*after write, iclass 30, count 0 2006.201.19:56:20.88#ibcon#*before return 0, iclass 30, count 0 2006.201.19:56:20.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:20.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.19:56:20.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.19:56:20.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.19:56:20.88$vck44/vblo=5,709.99 2006.201.19:56:20.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.19:56:20.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.19:56:20.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:20.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:20.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:20.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:20.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.19:56:20.88#ibcon#first serial, iclass 32, count 0 2006.201.19:56:20.88#ibcon#enter sib2, iclass 32, count 0 2006.201.19:56:20.88#ibcon#flushed, iclass 32, count 0 2006.201.19:56:20.88#ibcon#about to write, iclass 32, count 0 2006.201.19:56:20.88#ibcon#wrote, iclass 32, count 0 2006.201.19:56:20.88#ibcon#about to read 3, iclass 32, count 0 2006.201.19:56:20.90#ibcon#read 3, iclass 32, count 0 2006.201.19:56:20.90#ibcon#about to read 4, iclass 32, count 0 2006.201.19:56:20.90#ibcon#read 4, iclass 32, count 0 2006.201.19:56:20.90#ibcon#about to read 5, iclass 32, count 0 2006.201.19:56:20.90#ibcon#read 5, iclass 32, count 0 2006.201.19:56:20.90#ibcon#about to read 6, iclass 32, count 0 2006.201.19:56:20.90#ibcon#read 6, iclass 32, count 0 2006.201.19:56:20.90#ibcon#end of sib2, iclass 32, count 0 2006.201.19:56:20.90#ibcon#*mode == 0, iclass 32, count 0 2006.201.19:56:20.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.19:56:20.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:56:20.90#ibcon#*before write, iclass 32, count 0 2006.201.19:56:20.90#ibcon#enter sib2, iclass 32, count 0 2006.201.19:56:20.90#ibcon#flushed, iclass 32, count 0 2006.201.19:56:20.90#ibcon#about to write, iclass 32, count 0 2006.201.19:56:20.90#ibcon#wrote, iclass 32, count 0 2006.201.19:56:20.90#ibcon#about to read 3, iclass 32, count 0 2006.201.19:56:20.95#ibcon#read 3, iclass 32, count 0 2006.201.19:56:20.95#ibcon#about to read 4, iclass 32, count 0 2006.201.19:56:20.95#ibcon#read 4, iclass 32, count 0 2006.201.19:56:20.95#ibcon#about to read 5, iclass 32, count 0 2006.201.19:56:20.95#ibcon#read 5, iclass 32, count 0 2006.201.19:56:20.95#ibcon#about to read 6, iclass 32, count 0 2006.201.19:56:20.95#ibcon#read 6, iclass 32, count 0 2006.201.19:56:20.95#ibcon#end of sib2, iclass 32, count 0 2006.201.19:56:20.95#ibcon#*after write, iclass 32, count 0 2006.201.19:56:20.95#ibcon#*before return 0, iclass 32, count 0 2006.201.19:56:20.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:20.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.19:56:20.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.19:56:20.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.19:56:20.95$vck44/vb=5,4 2006.201.19:56:20.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.19:56:20.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.19:56:20.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:20.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:21.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:21.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:21.00#ibcon#enter wrdev, iclass 34, count 2 2006.201.19:56:21.00#ibcon#first serial, iclass 34, count 2 2006.201.19:56:21.00#ibcon#enter sib2, iclass 34, count 2 2006.201.19:56:21.00#ibcon#flushed, iclass 34, count 2 2006.201.19:56:21.00#ibcon#about to write, iclass 34, count 2 2006.201.19:56:21.00#ibcon#wrote, iclass 34, count 2 2006.201.19:56:21.00#ibcon#about to read 3, iclass 34, count 2 2006.201.19:56:21.02#ibcon#read 3, iclass 34, count 2 2006.201.19:56:21.02#ibcon#about to read 4, iclass 34, count 2 2006.201.19:56:21.02#ibcon#read 4, iclass 34, count 2 2006.201.19:56:21.02#ibcon#about to read 5, iclass 34, count 2 2006.201.19:56:21.02#ibcon#read 5, iclass 34, count 2 2006.201.19:56:21.02#ibcon#about to read 6, iclass 34, count 2 2006.201.19:56:21.02#ibcon#read 6, iclass 34, count 2 2006.201.19:56:21.02#ibcon#end of sib2, iclass 34, count 2 2006.201.19:56:21.02#ibcon#*mode == 0, iclass 34, count 2 2006.201.19:56:21.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.19:56:21.02#ibcon#[27=AT05-04\r\n] 2006.201.19:56:21.02#ibcon#*before write, iclass 34, count 2 2006.201.19:56:21.02#ibcon#enter sib2, iclass 34, count 2 2006.201.19:56:21.02#ibcon#flushed, iclass 34, count 2 2006.201.19:56:21.02#ibcon#about to write, iclass 34, count 2 2006.201.19:56:21.02#ibcon#wrote, iclass 34, count 2 2006.201.19:56:21.02#ibcon#about to read 3, iclass 34, count 2 2006.201.19:56:21.05#ibcon#read 3, iclass 34, count 2 2006.201.19:56:21.05#ibcon#about to read 4, iclass 34, count 2 2006.201.19:56:21.05#ibcon#read 4, iclass 34, count 2 2006.201.19:56:21.05#ibcon#about to read 5, iclass 34, count 2 2006.201.19:56:21.05#ibcon#read 5, iclass 34, count 2 2006.201.19:56:21.05#ibcon#about to read 6, iclass 34, count 2 2006.201.19:56:21.05#ibcon#read 6, iclass 34, count 2 2006.201.19:56:21.05#ibcon#end of sib2, iclass 34, count 2 2006.201.19:56:21.05#ibcon#*after write, iclass 34, count 2 2006.201.19:56:21.05#ibcon#*before return 0, iclass 34, count 2 2006.201.19:56:21.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:21.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.19:56:21.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.19:56:21.05#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:21.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:21.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:21.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:21.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.19:56:21.17#ibcon#first serial, iclass 34, count 0 2006.201.19:56:21.17#ibcon#enter sib2, iclass 34, count 0 2006.201.19:56:21.17#ibcon#flushed, iclass 34, count 0 2006.201.19:56:21.17#ibcon#about to write, iclass 34, count 0 2006.201.19:56:21.17#ibcon#wrote, iclass 34, count 0 2006.201.19:56:21.17#ibcon#about to read 3, iclass 34, count 0 2006.201.19:56:21.19#ibcon#read 3, iclass 34, count 0 2006.201.19:56:21.19#ibcon#about to read 4, iclass 34, count 0 2006.201.19:56:21.19#ibcon#read 4, iclass 34, count 0 2006.201.19:56:21.19#ibcon#about to read 5, iclass 34, count 0 2006.201.19:56:21.19#ibcon#read 5, iclass 34, count 0 2006.201.19:56:21.19#ibcon#about to read 6, iclass 34, count 0 2006.201.19:56:21.19#ibcon#read 6, iclass 34, count 0 2006.201.19:56:21.19#ibcon#end of sib2, iclass 34, count 0 2006.201.19:56:21.19#ibcon#*mode == 0, iclass 34, count 0 2006.201.19:56:21.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.19:56:21.19#ibcon#[27=USB\r\n] 2006.201.19:56:21.19#ibcon#*before write, iclass 34, count 0 2006.201.19:56:21.19#ibcon#enter sib2, iclass 34, count 0 2006.201.19:56:21.19#ibcon#flushed, iclass 34, count 0 2006.201.19:56:21.19#ibcon#about to write, iclass 34, count 0 2006.201.19:56:21.19#ibcon#wrote, iclass 34, count 0 2006.201.19:56:21.19#ibcon#about to read 3, iclass 34, count 0 2006.201.19:56:21.22#ibcon#read 3, iclass 34, count 0 2006.201.19:56:21.22#ibcon#about to read 4, iclass 34, count 0 2006.201.19:56:21.22#ibcon#read 4, iclass 34, count 0 2006.201.19:56:21.22#ibcon#about to read 5, iclass 34, count 0 2006.201.19:56:21.22#ibcon#read 5, iclass 34, count 0 2006.201.19:56:21.22#ibcon#about to read 6, iclass 34, count 0 2006.201.19:56:21.22#ibcon#read 6, iclass 34, count 0 2006.201.19:56:21.22#ibcon#end of sib2, iclass 34, count 0 2006.201.19:56:21.22#ibcon#*after write, iclass 34, count 0 2006.201.19:56:21.22#ibcon#*before return 0, iclass 34, count 0 2006.201.19:56:21.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:21.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.19:56:21.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.19:56:21.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.19:56:21.22$vck44/vblo=6,719.99 2006.201.19:56:21.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.19:56:21.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.19:56:21.22#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:21.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:21.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:21.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:21.22#ibcon#enter wrdev, iclass 36, count 0 2006.201.19:56:21.22#ibcon#first serial, iclass 36, count 0 2006.201.19:56:21.22#ibcon#enter sib2, iclass 36, count 0 2006.201.19:56:21.22#ibcon#flushed, iclass 36, count 0 2006.201.19:56:21.22#ibcon#about to write, iclass 36, count 0 2006.201.19:56:21.22#ibcon#wrote, iclass 36, count 0 2006.201.19:56:21.22#ibcon#about to read 3, iclass 36, count 0 2006.201.19:56:21.24#ibcon#read 3, iclass 36, count 0 2006.201.19:56:21.24#ibcon#about to read 4, iclass 36, count 0 2006.201.19:56:21.24#ibcon#read 4, iclass 36, count 0 2006.201.19:56:21.24#ibcon#about to read 5, iclass 36, count 0 2006.201.19:56:21.24#ibcon#read 5, iclass 36, count 0 2006.201.19:56:21.24#ibcon#about to read 6, iclass 36, count 0 2006.201.19:56:21.24#ibcon#read 6, iclass 36, count 0 2006.201.19:56:21.24#ibcon#end of sib2, iclass 36, count 0 2006.201.19:56:21.24#ibcon#*mode == 0, iclass 36, count 0 2006.201.19:56:21.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.19:56:21.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:56:21.24#ibcon#*before write, iclass 36, count 0 2006.201.19:56:21.24#ibcon#enter sib2, iclass 36, count 0 2006.201.19:56:21.24#ibcon#flushed, iclass 36, count 0 2006.201.19:56:21.24#ibcon#about to write, iclass 36, count 0 2006.201.19:56:21.24#ibcon#wrote, iclass 36, count 0 2006.201.19:56:21.24#ibcon#about to read 3, iclass 36, count 0 2006.201.19:56:21.28#ibcon#read 3, iclass 36, count 0 2006.201.19:56:21.28#ibcon#about to read 4, iclass 36, count 0 2006.201.19:56:21.28#ibcon#read 4, iclass 36, count 0 2006.201.19:56:21.28#ibcon#about to read 5, iclass 36, count 0 2006.201.19:56:21.28#ibcon#read 5, iclass 36, count 0 2006.201.19:56:21.28#ibcon#about to read 6, iclass 36, count 0 2006.201.19:56:21.28#ibcon#read 6, iclass 36, count 0 2006.201.19:56:21.28#ibcon#end of sib2, iclass 36, count 0 2006.201.19:56:21.28#ibcon#*after write, iclass 36, count 0 2006.201.19:56:21.28#ibcon#*before return 0, iclass 36, count 0 2006.201.19:56:21.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:21.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.19:56:21.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.19:56:21.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.19:56:21.28$vck44/vb=6,4 2006.201.19:56:21.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.19:56:21.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.19:56:21.28#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:21.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:21.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:21.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:21.34#ibcon#enter wrdev, iclass 38, count 2 2006.201.19:56:21.34#ibcon#first serial, iclass 38, count 2 2006.201.19:56:21.34#ibcon#enter sib2, iclass 38, count 2 2006.201.19:56:21.34#ibcon#flushed, iclass 38, count 2 2006.201.19:56:21.34#ibcon#about to write, iclass 38, count 2 2006.201.19:56:21.34#ibcon#wrote, iclass 38, count 2 2006.201.19:56:21.34#ibcon#about to read 3, iclass 38, count 2 2006.201.19:56:21.36#ibcon#read 3, iclass 38, count 2 2006.201.19:56:21.36#ibcon#about to read 4, iclass 38, count 2 2006.201.19:56:21.36#ibcon#read 4, iclass 38, count 2 2006.201.19:56:21.36#ibcon#about to read 5, iclass 38, count 2 2006.201.19:56:21.36#ibcon#read 5, iclass 38, count 2 2006.201.19:56:21.36#ibcon#about to read 6, iclass 38, count 2 2006.201.19:56:21.36#ibcon#read 6, iclass 38, count 2 2006.201.19:56:21.36#ibcon#end of sib2, iclass 38, count 2 2006.201.19:56:21.36#ibcon#*mode == 0, iclass 38, count 2 2006.201.19:56:21.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.19:56:21.36#ibcon#[27=AT06-04\r\n] 2006.201.19:56:21.36#ibcon#*before write, iclass 38, count 2 2006.201.19:56:21.36#ibcon#enter sib2, iclass 38, count 2 2006.201.19:56:21.36#ibcon#flushed, iclass 38, count 2 2006.201.19:56:21.36#ibcon#about to write, iclass 38, count 2 2006.201.19:56:21.36#ibcon#wrote, iclass 38, count 2 2006.201.19:56:21.36#ibcon#about to read 3, iclass 38, count 2 2006.201.19:56:21.39#ibcon#read 3, iclass 38, count 2 2006.201.19:56:21.39#ibcon#about to read 4, iclass 38, count 2 2006.201.19:56:21.39#ibcon#read 4, iclass 38, count 2 2006.201.19:56:21.39#ibcon#about to read 5, iclass 38, count 2 2006.201.19:56:21.39#ibcon#read 5, iclass 38, count 2 2006.201.19:56:21.39#ibcon#about to read 6, iclass 38, count 2 2006.201.19:56:21.39#ibcon#read 6, iclass 38, count 2 2006.201.19:56:21.39#ibcon#end of sib2, iclass 38, count 2 2006.201.19:56:21.39#ibcon#*after write, iclass 38, count 2 2006.201.19:56:21.39#ibcon#*before return 0, iclass 38, count 2 2006.201.19:56:21.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:21.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.19:56:21.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.19:56:21.39#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:21.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:21.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:21.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:21.51#ibcon#enter wrdev, iclass 38, count 0 2006.201.19:56:21.51#ibcon#first serial, iclass 38, count 0 2006.201.19:56:21.51#ibcon#enter sib2, iclass 38, count 0 2006.201.19:56:21.51#ibcon#flushed, iclass 38, count 0 2006.201.19:56:21.51#ibcon#about to write, iclass 38, count 0 2006.201.19:56:21.51#ibcon#wrote, iclass 38, count 0 2006.201.19:56:21.51#ibcon#about to read 3, iclass 38, count 0 2006.201.19:56:21.53#ibcon#read 3, iclass 38, count 0 2006.201.19:56:21.53#ibcon#about to read 4, iclass 38, count 0 2006.201.19:56:21.53#ibcon#read 4, iclass 38, count 0 2006.201.19:56:21.53#ibcon#about to read 5, iclass 38, count 0 2006.201.19:56:21.53#ibcon#read 5, iclass 38, count 0 2006.201.19:56:21.53#ibcon#about to read 6, iclass 38, count 0 2006.201.19:56:21.53#ibcon#read 6, iclass 38, count 0 2006.201.19:56:21.53#ibcon#end of sib2, iclass 38, count 0 2006.201.19:56:21.53#ibcon#*mode == 0, iclass 38, count 0 2006.201.19:56:21.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.19:56:21.53#ibcon#[27=USB\r\n] 2006.201.19:56:21.53#ibcon#*before write, iclass 38, count 0 2006.201.19:56:21.53#ibcon#enter sib2, iclass 38, count 0 2006.201.19:56:21.53#ibcon#flushed, iclass 38, count 0 2006.201.19:56:21.53#ibcon#about to write, iclass 38, count 0 2006.201.19:56:21.53#ibcon#wrote, iclass 38, count 0 2006.201.19:56:21.53#ibcon#about to read 3, iclass 38, count 0 2006.201.19:56:21.56#ibcon#read 3, iclass 38, count 0 2006.201.19:56:21.56#ibcon#about to read 4, iclass 38, count 0 2006.201.19:56:21.56#ibcon#read 4, iclass 38, count 0 2006.201.19:56:21.56#ibcon#about to read 5, iclass 38, count 0 2006.201.19:56:21.56#ibcon#read 5, iclass 38, count 0 2006.201.19:56:21.56#ibcon#about to read 6, iclass 38, count 0 2006.201.19:56:21.56#ibcon#read 6, iclass 38, count 0 2006.201.19:56:21.56#ibcon#end of sib2, iclass 38, count 0 2006.201.19:56:21.56#ibcon#*after write, iclass 38, count 0 2006.201.19:56:21.56#ibcon#*before return 0, iclass 38, count 0 2006.201.19:56:21.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:21.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.19:56:21.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.19:56:21.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.19:56:21.56$vck44/vblo=7,734.99 2006.201.19:56:21.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.19:56:21.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.19:56:21.56#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:21.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:21.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:21.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:21.56#ibcon#enter wrdev, iclass 40, count 0 2006.201.19:56:21.56#ibcon#first serial, iclass 40, count 0 2006.201.19:56:21.56#ibcon#enter sib2, iclass 40, count 0 2006.201.19:56:21.56#ibcon#flushed, iclass 40, count 0 2006.201.19:56:21.56#ibcon#about to write, iclass 40, count 0 2006.201.19:56:21.56#ibcon#wrote, iclass 40, count 0 2006.201.19:56:21.56#ibcon#about to read 3, iclass 40, count 0 2006.201.19:56:21.58#ibcon#read 3, iclass 40, count 0 2006.201.19:56:21.58#ibcon#about to read 4, iclass 40, count 0 2006.201.19:56:21.58#ibcon#read 4, iclass 40, count 0 2006.201.19:56:21.58#ibcon#about to read 5, iclass 40, count 0 2006.201.19:56:21.58#ibcon#read 5, iclass 40, count 0 2006.201.19:56:21.58#ibcon#about to read 6, iclass 40, count 0 2006.201.19:56:21.58#ibcon#read 6, iclass 40, count 0 2006.201.19:56:21.58#ibcon#end of sib2, iclass 40, count 0 2006.201.19:56:21.58#ibcon#*mode == 0, iclass 40, count 0 2006.201.19:56:21.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.19:56:21.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:56:21.58#ibcon#*before write, iclass 40, count 0 2006.201.19:56:21.58#ibcon#enter sib2, iclass 40, count 0 2006.201.19:56:21.58#ibcon#flushed, iclass 40, count 0 2006.201.19:56:21.58#ibcon#about to write, iclass 40, count 0 2006.201.19:56:21.58#ibcon#wrote, iclass 40, count 0 2006.201.19:56:21.58#ibcon#about to read 3, iclass 40, count 0 2006.201.19:56:21.63#ibcon#read 3, iclass 40, count 0 2006.201.19:56:21.63#ibcon#about to read 4, iclass 40, count 0 2006.201.19:56:21.63#ibcon#read 4, iclass 40, count 0 2006.201.19:56:21.63#ibcon#about to read 5, iclass 40, count 0 2006.201.19:56:21.63#ibcon#read 5, iclass 40, count 0 2006.201.19:56:21.63#ibcon#about to read 6, iclass 40, count 0 2006.201.19:56:21.63#ibcon#read 6, iclass 40, count 0 2006.201.19:56:21.63#ibcon#end of sib2, iclass 40, count 0 2006.201.19:56:21.63#ibcon#*after write, iclass 40, count 0 2006.201.19:56:21.63#ibcon#*before return 0, iclass 40, count 0 2006.201.19:56:21.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:21.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.19:56:21.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.19:56:21.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.19:56:21.63$vck44/vb=7,4 2006.201.19:56:21.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.19:56:21.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.19:56:21.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:21.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:21.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:21.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:21.68#ibcon#enter wrdev, iclass 4, count 2 2006.201.19:56:21.68#ibcon#first serial, iclass 4, count 2 2006.201.19:56:21.68#ibcon#enter sib2, iclass 4, count 2 2006.201.19:56:21.68#ibcon#flushed, iclass 4, count 2 2006.201.19:56:21.68#ibcon#about to write, iclass 4, count 2 2006.201.19:56:21.68#ibcon#wrote, iclass 4, count 2 2006.201.19:56:21.68#ibcon#about to read 3, iclass 4, count 2 2006.201.19:56:21.70#ibcon#read 3, iclass 4, count 2 2006.201.19:56:21.70#ibcon#about to read 4, iclass 4, count 2 2006.201.19:56:21.70#ibcon#read 4, iclass 4, count 2 2006.201.19:56:21.70#ibcon#about to read 5, iclass 4, count 2 2006.201.19:56:21.70#ibcon#read 5, iclass 4, count 2 2006.201.19:56:21.70#ibcon#about to read 6, iclass 4, count 2 2006.201.19:56:21.70#ibcon#read 6, iclass 4, count 2 2006.201.19:56:21.70#ibcon#end of sib2, iclass 4, count 2 2006.201.19:56:21.70#ibcon#*mode == 0, iclass 4, count 2 2006.201.19:56:21.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.19:56:21.70#ibcon#[27=AT07-04\r\n] 2006.201.19:56:21.70#ibcon#*before write, iclass 4, count 2 2006.201.19:56:21.70#ibcon#enter sib2, iclass 4, count 2 2006.201.19:56:21.70#ibcon#flushed, iclass 4, count 2 2006.201.19:56:21.70#ibcon#about to write, iclass 4, count 2 2006.201.19:56:21.70#ibcon#wrote, iclass 4, count 2 2006.201.19:56:21.70#ibcon#about to read 3, iclass 4, count 2 2006.201.19:56:21.73#ibcon#read 3, iclass 4, count 2 2006.201.19:56:21.73#ibcon#about to read 4, iclass 4, count 2 2006.201.19:56:21.73#ibcon#read 4, iclass 4, count 2 2006.201.19:56:21.73#ibcon#about to read 5, iclass 4, count 2 2006.201.19:56:21.73#ibcon#read 5, iclass 4, count 2 2006.201.19:56:21.73#ibcon#about to read 6, iclass 4, count 2 2006.201.19:56:21.73#ibcon#read 6, iclass 4, count 2 2006.201.19:56:21.73#ibcon#end of sib2, iclass 4, count 2 2006.201.19:56:21.73#ibcon#*after write, iclass 4, count 2 2006.201.19:56:21.73#ibcon#*before return 0, iclass 4, count 2 2006.201.19:56:21.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:21.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.19:56:21.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.19:56:21.73#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:21.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:21.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:21.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:21.85#ibcon#enter wrdev, iclass 4, count 0 2006.201.19:56:21.85#ibcon#first serial, iclass 4, count 0 2006.201.19:56:21.85#ibcon#enter sib2, iclass 4, count 0 2006.201.19:56:21.85#ibcon#flushed, iclass 4, count 0 2006.201.19:56:21.85#ibcon#about to write, iclass 4, count 0 2006.201.19:56:21.85#ibcon#wrote, iclass 4, count 0 2006.201.19:56:21.85#ibcon#about to read 3, iclass 4, count 0 2006.201.19:56:21.87#ibcon#read 3, iclass 4, count 0 2006.201.19:56:21.87#ibcon#about to read 4, iclass 4, count 0 2006.201.19:56:21.87#ibcon#read 4, iclass 4, count 0 2006.201.19:56:21.87#ibcon#about to read 5, iclass 4, count 0 2006.201.19:56:21.87#ibcon#read 5, iclass 4, count 0 2006.201.19:56:21.87#ibcon#about to read 6, iclass 4, count 0 2006.201.19:56:21.87#ibcon#read 6, iclass 4, count 0 2006.201.19:56:21.87#ibcon#end of sib2, iclass 4, count 0 2006.201.19:56:21.87#ibcon#*mode == 0, iclass 4, count 0 2006.201.19:56:21.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.19:56:21.87#ibcon#[27=USB\r\n] 2006.201.19:56:21.87#ibcon#*before write, iclass 4, count 0 2006.201.19:56:21.87#ibcon#enter sib2, iclass 4, count 0 2006.201.19:56:21.87#ibcon#flushed, iclass 4, count 0 2006.201.19:56:21.87#ibcon#about to write, iclass 4, count 0 2006.201.19:56:21.87#ibcon#wrote, iclass 4, count 0 2006.201.19:56:21.87#ibcon#about to read 3, iclass 4, count 0 2006.201.19:56:21.90#ibcon#read 3, iclass 4, count 0 2006.201.19:56:21.90#ibcon#about to read 4, iclass 4, count 0 2006.201.19:56:21.90#ibcon#read 4, iclass 4, count 0 2006.201.19:56:21.90#ibcon#about to read 5, iclass 4, count 0 2006.201.19:56:21.90#ibcon#read 5, iclass 4, count 0 2006.201.19:56:21.90#ibcon#about to read 6, iclass 4, count 0 2006.201.19:56:21.90#ibcon#read 6, iclass 4, count 0 2006.201.19:56:21.90#ibcon#end of sib2, iclass 4, count 0 2006.201.19:56:21.90#ibcon#*after write, iclass 4, count 0 2006.201.19:56:21.90#ibcon#*before return 0, iclass 4, count 0 2006.201.19:56:21.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:21.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.19:56:21.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.19:56:21.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.19:56:21.90$vck44/vblo=8,744.99 2006.201.19:56:21.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.19:56:21.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.19:56:21.90#ibcon#ireg 17 cls_cnt 0 2006.201.19:56:21.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:21.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:21.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:21.90#ibcon#enter wrdev, iclass 6, count 0 2006.201.19:56:21.90#ibcon#first serial, iclass 6, count 0 2006.201.19:56:21.90#ibcon#enter sib2, iclass 6, count 0 2006.201.19:56:21.90#ibcon#flushed, iclass 6, count 0 2006.201.19:56:21.90#ibcon#about to write, iclass 6, count 0 2006.201.19:56:21.90#ibcon#wrote, iclass 6, count 0 2006.201.19:56:21.90#ibcon#about to read 3, iclass 6, count 0 2006.201.19:56:21.92#ibcon#read 3, iclass 6, count 0 2006.201.19:56:21.92#ibcon#about to read 4, iclass 6, count 0 2006.201.19:56:21.92#ibcon#read 4, iclass 6, count 0 2006.201.19:56:21.92#ibcon#about to read 5, iclass 6, count 0 2006.201.19:56:21.92#ibcon#read 5, iclass 6, count 0 2006.201.19:56:21.92#ibcon#about to read 6, iclass 6, count 0 2006.201.19:56:21.92#ibcon#read 6, iclass 6, count 0 2006.201.19:56:21.92#ibcon#end of sib2, iclass 6, count 0 2006.201.19:56:21.92#ibcon#*mode == 0, iclass 6, count 0 2006.201.19:56:21.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.19:56:21.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:56:21.92#ibcon#*before write, iclass 6, count 0 2006.201.19:56:21.92#ibcon#enter sib2, iclass 6, count 0 2006.201.19:56:21.92#ibcon#flushed, iclass 6, count 0 2006.201.19:56:21.92#ibcon#about to write, iclass 6, count 0 2006.201.19:56:21.92#ibcon#wrote, iclass 6, count 0 2006.201.19:56:21.92#ibcon#about to read 3, iclass 6, count 0 2006.201.19:56:21.96#ibcon#read 3, iclass 6, count 0 2006.201.19:56:21.96#ibcon#about to read 4, iclass 6, count 0 2006.201.19:56:21.96#ibcon#read 4, iclass 6, count 0 2006.201.19:56:21.96#ibcon#about to read 5, iclass 6, count 0 2006.201.19:56:21.96#ibcon#read 5, iclass 6, count 0 2006.201.19:56:21.96#ibcon#about to read 6, iclass 6, count 0 2006.201.19:56:21.96#ibcon#read 6, iclass 6, count 0 2006.201.19:56:21.96#ibcon#end of sib2, iclass 6, count 0 2006.201.19:56:21.96#ibcon#*after write, iclass 6, count 0 2006.201.19:56:21.96#ibcon#*before return 0, iclass 6, count 0 2006.201.19:56:21.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:21.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.19:56:21.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.19:56:21.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.19:56:21.96$vck44/vb=8,4 2006.201.19:56:21.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.19:56:21.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.19:56:21.96#ibcon#ireg 11 cls_cnt 2 2006.201.19:56:21.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:22.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:22.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:22.02#ibcon#enter wrdev, iclass 10, count 2 2006.201.19:56:22.02#ibcon#first serial, iclass 10, count 2 2006.201.19:56:22.02#ibcon#enter sib2, iclass 10, count 2 2006.201.19:56:22.02#ibcon#flushed, iclass 10, count 2 2006.201.19:56:22.02#ibcon#about to write, iclass 10, count 2 2006.201.19:56:22.02#ibcon#wrote, iclass 10, count 2 2006.201.19:56:22.02#ibcon#about to read 3, iclass 10, count 2 2006.201.19:56:22.04#ibcon#read 3, iclass 10, count 2 2006.201.19:56:22.04#ibcon#about to read 4, iclass 10, count 2 2006.201.19:56:22.04#ibcon#read 4, iclass 10, count 2 2006.201.19:56:22.04#ibcon#about to read 5, iclass 10, count 2 2006.201.19:56:22.04#ibcon#read 5, iclass 10, count 2 2006.201.19:56:22.04#ibcon#about to read 6, iclass 10, count 2 2006.201.19:56:22.04#ibcon#read 6, iclass 10, count 2 2006.201.19:56:22.04#ibcon#end of sib2, iclass 10, count 2 2006.201.19:56:22.04#ibcon#*mode == 0, iclass 10, count 2 2006.201.19:56:22.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.19:56:22.04#ibcon#[27=AT08-04\r\n] 2006.201.19:56:22.04#ibcon#*before write, iclass 10, count 2 2006.201.19:56:22.04#ibcon#enter sib2, iclass 10, count 2 2006.201.19:56:22.04#ibcon#flushed, iclass 10, count 2 2006.201.19:56:22.04#ibcon#about to write, iclass 10, count 2 2006.201.19:56:22.04#ibcon#wrote, iclass 10, count 2 2006.201.19:56:22.04#ibcon#about to read 3, iclass 10, count 2 2006.201.19:56:22.07#ibcon#read 3, iclass 10, count 2 2006.201.19:56:22.07#ibcon#about to read 4, iclass 10, count 2 2006.201.19:56:22.07#ibcon#read 4, iclass 10, count 2 2006.201.19:56:22.07#ibcon#about to read 5, iclass 10, count 2 2006.201.19:56:22.07#ibcon#read 5, iclass 10, count 2 2006.201.19:56:22.07#ibcon#about to read 6, iclass 10, count 2 2006.201.19:56:22.07#ibcon#read 6, iclass 10, count 2 2006.201.19:56:22.07#ibcon#end of sib2, iclass 10, count 2 2006.201.19:56:22.07#ibcon#*after write, iclass 10, count 2 2006.201.19:56:22.07#ibcon#*before return 0, iclass 10, count 2 2006.201.19:56:22.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:22.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.19:56:22.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.19:56:22.07#ibcon#ireg 7 cls_cnt 0 2006.201.19:56:22.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:22.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:22.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:22.19#ibcon#enter wrdev, iclass 10, count 0 2006.201.19:56:22.19#ibcon#first serial, iclass 10, count 0 2006.201.19:56:22.19#ibcon#enter sib2, iclass 10, count 0 2006.201.19:56:22.19#ibcon#flushed, iclass 10, count 0 2006.201.19:56:22.19#ibcon#about to write, iclass 10, count 0 2006.201.19:56:22.19#ibcon#wrote, iclass 10, count 0 2006.201.19:56:22.19#ibcon#about to read 3, iclass 10, count 0 2006.201.19:56:22.21#ibcon#read 3, iclass 10, count 0 2006.201.19:56:22.21#ibcon#about to read 4, iclass 10, count 0 2006.201.19:56:22.21#ibcon#read 4, iclass 10, count 0 2006.201.19:56:22.21#ibcon#about to read 5, iclass 10, count 0 2006.201.19:56:22.21#ibcon#read 5, iclass 10, count 0 2006.201.19:56:22.21#ibcon#about to read 6, iclass 10, count 0 2006.201.19:56:22.21#ibcon#read 6, iclass 10, count 0 2006.201.19:56:22.21#ibcon#end of sib2, iclass 10, count 0 2006.201.19:56:22.21#ibcon#*mode == 0, iclass 10, count 0 2006.201.19:56:22.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.19:56:22.21#ibcon#[27=USB\r\n] 2006.201.19:56:22.21#ibcon#*before write, iclass 10, count 0 2006.201.19:56:22.21#ibcon#enter sib2, iclass 10, count 0 2006.201.19:56:22.21#ibcon#flushed, iclass 10, count 0 2006.201.19:56:22.21#ibcon#about to write, iclass 10, count 0 2006.201.19:56:22.21#ibcon#wrote, iclass 10, count 0 2006.201.19:56:22.21#ibcon#about to read 3, iclass 10, count 0 2006.201.19:56:22.24#ibcon#read 3, iclass 10, count 0 2006.201.19:56:22.24#ibcon#about to read 4, iclass 10, count 0 2006.201.19:56:22.24#ibcon#read 4, iclass 10, count 0 2006.201.19:56:22.24#ibcon#about to read 5, iclass 10, count 0 2006.201.19:56:22.24#ibcon#read 5, iclass 10, count 0 2006.201.19:56:22.24#ibcon#about to read 6, iclass 10, count 0 2006.201.19:56:22.24#ibcon#read 6, iclass 10, count 0 2006.201.19:56:22.24#ibcon#end of sib2, iclass 10, count 0 2006.201.19:56:22.24#ibcon#*after write, iclass 10, count 0 2006.201.19:56:22.24#ibcon#*before return 0, iclass 10, count 0 2006.201.19:56:22.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:22.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.19:56:22.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.19:56:22.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.19:56:22.24$vck44/vabw=wide 2006.201.19:56:22.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.19:56:22.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.19:56:22.24#ibcon#ireg 8 cls_cnt 0 2006.201.19:56:22.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:22.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:22.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:22.24#ibcon#enter wrdev, iclass 12, count 0 2006.201.19:56:22.24#ibcon#first serial, iclass 12, count 0 2006.201.19:56:22.24#ibcon#enter sib2, iclass 12, count 0 2006.201.19:56:22.24#ibcon#flushed, iclass 12, count 0 2006.201.19:56:22.24#ibcon#about to write, iclass 12, count 0 2006.201.19:56:22.24#ibcon#wrote, iclass 12, count 0 2006.201.19:56:22.24#ibcon#about to read 3, iclass 12, count 0 2006.201.19:56:22.26#ibcon#read 3, iclass 12, count 0 2006.201.19:56:22.26#ibcon#about to read 4, iclass 12, count 0 2006.201.19:56:22.26#ibcon#read 4, iclass 12, count 0 2006.201.19:56:22.26#ibcon#about to read 5, iclass 12, count 0 2006.201.19:56:22.26#ibcon#read 5, iclass 12, count 0 2006.201.19:56:22.26#ibcon#about to read 6, iclass 12, count 0 2006.201.19:56:22.26#ibcon#read 6, iclass 12, count 0 2006.201.19:56:22.26#ibcon#end of sib2, iclass 12, count 0 2006.201.19:56:22.26#ibcon#*mode == 0, iclass 12, count 0 2006.201.19:56:22.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.19:56:22.26#ibcon#[25=BW32\r\n] 2006.201.19:56:22.26#ibcon#*before write, iclass 12, count 0 2006.201.19:56:22.26#ibcon#enter sib2, iclass 12, count 0 2006.201.19:56:22.26#ibcon#flushed, iclass 12, count 0 2006.201.19:56:22.26#ibcon#about to write, iclass 12, count 0 2006.201.19:56:22.26#ibcon#wrote, iclass 12, count 0 2006.201.19:56:22.26#ibcon#about to read 3, iclass 12, count 0 2006.201.19:56:22.29#ibcon#read 3, iclass 12, count 0 2006.201.19:56:22.29#ibcon#about to read 4, iclass 12, count 0 2006.201.19:56:22.29#ibcon#read 4, iclass 12, count 0 2006.201.19:56:22.29#ibcon#about to read 5, iclass 12, count 0 2006.201.19:56:22.29#ibcon#read 5, iclass 12, count 0 2006.201.19:56:22.29#ibcon#about to read 6, iclass 12, count 0 2006.201.19:56:22.29#ibcon#read 6, iclass 12, count 0 2006.201.19:56:22.29#ibcon#end of sib2, iclass 12, count 0 2006.201.19:56:22.29#ibcon#*after write, iclass 12, count 0 2006.201.19:56:22.29#ibcon#*before return 0, iclass 12, count 0 2006.201.19:56:22.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:22.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.19:56:22.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.19:56:22.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.19:56:22.29$vck44/vbbw=wide 2006.201.19:56:22.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.19:56:22.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.19:56:22.29#ibcon#ireg 8 cls_cnt 0 2006.201.19:56:22.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:56:22.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:56:22.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:56:22.36#ibcon#enter wrdev, iclass 14, count 0 2006.201.19:56:22.36#ibcon#first serial, iclass 14, count 0 2006.201.19:56:22.36#ibcon#enter sib2, iclass 14, count 0 2006.201.19:56:22.36#ibcon#flushed, iclass 14, count 0 2006.201.19:56:22.36#ibcon#about to write, iclass 14, count 0 2006.201.19:56:22.36#ibcon#wrote, iclass 14, count 0 2006.201.19:56:22.36#ibcon#about to read 3, iclass 14, count 0 2006.201.19:56:22.38#ibcon#read 3, iclass 14, count 0 2006.201.19:56:22.38#ibcon#about to read 4, iclass 14, count 0 2006.201.19:56:22.38#ibcon#read 4, iclass 14, count 0 2006.201.19:56:22.38#ibcon#about to read 5, iclass 14, count 0 2006.201.19:56:22.38#ibcon#read 5, iclass 14, count 0 2006.201.19:56:22.38#ibcon#about to read 6, iclass 14, count 0 2006.201.19:56:22.38#ibcon#read 6, iclass 14, count 0 2006.201.19:56:22.38#ibcon#end of sib2, iclass 14, count 0 2006.201.19:56:22.38#ibcon#*mode == 0, iclass 14, count 0 2006.201.19:56:22.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.19:56:22.38#ibcon#[27=BW32\r\n] 2006.201.19:56:22.38#ibcon#*before write, iclass 14, count 0 2006.201.19:56:22.38#ibcon#enter sib2, iclass 14, count 0 2006.201.19:56:22.38#ibcon#flushed, iclass 14, count 0 2006.201.19:56:22.38#ibcon#about to write, iclass 14, count 0 2006.201.19:56:22.38#ibcon#wrote, iclass 14, count 0 2006.201.19:56:22.38#ibcon#about to read 3, iclass 14, count 0 2006.201.19:56:22.41#ibcon#read 3, iclass 14, count 0 2006.201.19:56:22.41#ibcon#about to read 4, iclass 14, count 0 2006.201.19:56:22.41#ibcon#read 4, iclass 14, count 0 2006.201.19:56:22.41#ibcon#about to read 5, iclass 14, count 0 2006.201.19:56:22.41#ibcon#read 5, iclass 14, count 0 2006.201.19:56:22.41#ibcon#about to read 6, iclass 14, count 0 2006.201.19:56:22.41#ibcon#read 6, iclass 14, count 0 2006.201.19:56:22.41#ibcon#end of sib2, iclass 14, count 0 2006.201.19:56:22.41#ibcon#*after write, iclass 14, count 0 2006.201.19:56:22.41#ibcon#*before return 0, iclass 14, count 0 2006.201.19:56:22.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:56:22.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.19:56:22.41#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.19:56:22.41#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.19:56:22.41$setupk4/ifdk4 2006.201.19:56:22.41$ifdk4/lo= 2006.201.19:56:22.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:56:22.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:56:22.41$ifdk4/patch= 2006.201.19:56:22.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:56:22.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:56:22.41$setupk4/!*+20s 2006.201.19:56:24.50#abcon#<5=/04 2.1 3.9 20.331001002.1\r\n> 2006.201.19:56:24.52#abcon#{5=INTERFACE CLEAR} 2006.201.19:56:24.58#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:56:31.14#trakl#Source acquired 2006.201.19:56:33.14#flagr#flagr/antenna,acquired 2006.201.19:56:34.67#abcon#<5=/04 2.1 3.9 20.331001002.1\r\n> 2006.201.19:56:34.69#abcon#{5=INTERFACE CLEAR} 2006.201.19:56:34.75#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:56:36.90$setupk4/"tpicd 2006.201.19:56:36.90$setupk4/echo=off 2006.201.19:56:36.90$setupk4/xlog=off 2006.201.19:56:36.90:!2006.201.19:56:47 2006.201.19:56:47.00:preob 2006.201.19:56:47.14/onsource/TRACKING 2006.201.19:56:47.14:!2006.201.19:56:57 2006.201.19:56:57.00:"tape 2006.201.19:56:57.00:"st=record 2006.201.19:56:57.00:data_valid=on 2006.201.19:56:57.00:midob 2006.201.19:56:57.14/onsource/TRACKING 2006.201.19:56:57.14/wx/20.32,1002.1,100 2006.201.19:56:57.32/cable/+6.4824E-03 2006.201.19:56:58.41/va/01,08,usb,yes,45,48 2006.201.19:56:58.41/va/02,07,usb,yes,48,49 2006.201.19:56:58.41/va/03,08,usb,yes,44,45 2006.201.19:56:58.41/va/04,07,usb,yes,50,52 2006.201.19:56:58.41/va/05,04,usb,yes,44,45 2006.201.19:56:58.41/va/06,05,usb,yes,44,44 2006.201.19:56:58.41/va/07,05,usb,yes,43,45 2006.201.19:56:58.41/va/08,04,usb,yes,43,51 2006.201.19:56:58.64/valo/01,524.99,yes,locked 2006.201.19:56:58.64/valo/02,534.99,yes,locked 2006.201.19:56:58.64/valo/03,564.99,yes,locked 2006.201.19:56:58.64/valo/04,624.99,yes,locked 2006.201.19:56:58.64/valo/05,734.99,yes,locked 2006.201.19:56:58.64/valo/06,814.99,yes,locked 2006.201.19:56:58.64/valo/07,864.99,yes,locked 2006.201.19:56:58.64/valo/08,884.99,yes,locked 2006.201.19:56:59.73/vb/01,04,usb,yes,30,28 2006.201.19:56:59.73/vb/02,05,usb,yes,29,28 2006.201.19:56:59.73/vb/03,04,usb,yes,30,33 2006.201.19:56:59.73/vb/04,05,usb,yes,30,29 2006.201.19:56:59.73/vb/05,04,usb,yes,26,29 2006.201.19:56:59.73/vb/06,04,usb,yes,31,27 2006.201.19:56:59.73/vb/07,04,usb,yes,31,30 2006.201.19:56:59.73/vb/08,04,usb,yes,28,31 2006.201.19:56:59.96/vblo/01,629.99,yes,locked 2006.201.19:56:59.96/vblo/02,634.99,yes,locked 2006.201.19:56:59.96/vblo/03,649.99,yes,locked 2006.201.19:56:59.96/vblo/04,679.99,yes,locked 2006.201.19:56:59.96/vblo/05,709.99,yes,locked 2006.201.19:56:59.96/vblo/06,719.99,yes,locked 2006.201.19:56:59.96/vblo/07,734.99,yes,locked 2006.201.19:56:59.96/vblo/08,744.99,yes,locked 2006.201.19:57:00.11/vabw/8 2006.201.19:57:00.26/vbbw/8 2006.201.19:57:00.35/xfe/off,on,14.2 2006.201.19:57:00.74/ifatt/23,28,28,28 2006.201.19:57:01.06/fmout-gps/S +4.58E-07 2006.201.19:57:01.10:!2006.201.19:57:37 2006.201.19:57:37.00:data_valid=off 2006.201.19:57:37.00:"et 2006.201.19:57:37.00:!+3s 2006.201.19:57:40.02:"tape 2006.201.19:57:40.02:postob 2006.201.19:57:40.09/cable/+6.4816E-03 2006.201.19:57:40.09/wx/20.31,1002.0,100 2006.201.19:57:40.17/fmout-gps/S +4.57E-07 2006.201.19:57:40.17:scan_name=201-1958,jd0607,180 2006.201.19:57:40.18:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.201.19:57:42.14#flagr#flagr/antenna,new-source 2006.201.19:57:42.14:checkk5 2006.201.19:57:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.19:57:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.19:57:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.19:57:43.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.19:57:43.99/chk_obsdata//k5ts1/T2011956??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:57:44.36/chk_obsdata//k5ts2/T2011956??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:57:44.73/chk_obsdata//k5ts3/T2011956??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:57:45.09/chk_obsdata//k5ts4/T2011956??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.19:57:45.77/k5log//k5ts1_log_newline 2006.201.19:57:46.46/k5log//k5ts2_log_newline 2006.201.19:57:47.15/k5log//k5ts3_log_newline 2006.201.19:57:47.83/k5log//k5ts4_log_newline 2006.201.19:57:47.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.19:57:47.85:setupk4=1 2006.201.19:57:47.85$setupk4/echo=on 2006.201.19:57:47.85$setupk4/pcalon 2006.201.19:57:47.85$pcalon/"no phase cal control is implemented here 2006.201.19:57:47.85$setupk4/"tpicd=stop 2006.201.19:57:47.85$setupk4/"rec=synch_on 2006.201.19:57:47.85$setupk4/"rec_mode=128 2006.201.19:57:47.85$setupk4/!* 2006.201.19:57:47.85$setupk4/recpk4 2006.201.19:57:47.85$recpk4/recpatch= 2006.201.19:57:47.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.19:57:47.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.19:57:47.86$setupk4/vck44 2006.201.19:57:47.86$vck44/valo=1,524.99 2006.201.19:57:47.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.19:57:47.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.19:57:47.86#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:47.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:47.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:47.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:47.86#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:57:47.86#ibcon#first serial, iclass 19, count 0 2006.201.19:57:47.86#ibcon#enter sib2, iclass 19, count 0 2006.201.19:57:47.86#ibcon#flushed, iclass 19, count 0 2006.201.19:57:47.86#ibcon#about to write, iclass 19, count 0 2006.201.19:57:47.86#ibcon#wrote, iclass 19, count 0 2006.201.19:57:47.86#ibcon#about to read 3, iclass 19, count 0 2006.201.19:57:47.89#ibcon#read 3, iclass 19, count 0 2006.201.19:57:47.89#ibcon#about to read 4, iclass 19, count 0 2006.201.19:57:47.89#ibcon#read 4, iclass 19, count 0 2006.201.19:57:47.89#ibcon#about to read 5, iclass 19, count 0 2006.201.19:57:47.89#ibcon#read 5, iclass 19, count 0 2006.201.19:57:47.89#ibcon#about to read 6, iclass 19, count 0 2006.201.19:57:47.89#ibcon#read 6, iclass 19, count 0 2006.201.19:57:47.89#ibcon#end of sib2, iclass 19, count 0 2006.201.19:57:47.89#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:57:47.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:57:47.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.19:57:47.89#ibcon#*before write, iclass 19, count 0 2006.201.19:57:47.89#ibcon#enter sib2, iclass 19, count 0 2006.201.19:57:47.89#ibcon#flushed, iclass 19, count 0 2006.201.19:57:47.89#ibcon#about to write, iclass 19, count 0 2006.201.19:57:47.89#ibcon#wrote, iclass 19, count 0 2006.201.19:57:47.89#ibcon#about to read 3, iclass 19, count 0 2006.201.19:57:47.95#ibcon#read 3, iclass 19, count 0 2006.201.19:57:47.95#ibcon#about to read 4, iclass 19, count 0 2006.201.19:57:47.95#ibcon#read 4, iclass 19, count 0 2006.201.19:57:47.95#ibcon#about to read 5, iclass 19, count 0 2006.201.19:57:47.95#ibcon#read 5, iclass 19, count 0 2006.201.19:57:47.95#ibcon#about to read 6, iclass 19, count 0 2006.201.19:57:47.95#ibcon#read 6, iclass 19, count 0 2006.201.19:57:47.95#ibcon#end of sib2, iclass 19, count 0 2006.201.19:57:47.95#ibcon#*after write, iclass 19, count 0 2006.201.19:57:47.95#ibcon#*before return 0, iclass 19, count 0 2006.201.19:57:47.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:47.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:47.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:57:47.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:57:47.95$vck44/va=1,8 2006.201.19:57:47.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.19:57:47.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.19:57:47.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:47.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:47.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:47.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:47.95#ibcon#enter wrdev, iclass 21, count 2 2006.201.19:57:47.95#ibcon#first serial, iclass 21, count 2 2006.201.19:57:47.95#ibcon#enter sib2, iclass 21, count 2 2006.201.19:57:47.95#ibcon#flushed, iclass 21, count 2 2006.201.19:57:47.95#ibcon#about to write, iclass 21, count 2 2006.201.19:57:47.95#ibcon#wrote, iclass 21, count 2 2006.201.19:57:47.95#ibcon#about to read 3, iclass 21, count 2 2006.201.19:57:47.97#ibcon#read 3, iclass 21, count 2 2006.201.19:57:47.97#ibcon#about to read 4, iclass 21, count 2 2006.201.19:57:47.97#ibcon#read 4, iclass 21, count 2 2006.201.19:57:47.97#ibcon#about to read 5, iclass 21, count 2 2006.201.19:57:47.97#ibcon#read 5, iclass 21, count 2 2006.201.19:57:47.97#ibcon#about to read 6, iclass 21, count 2 2006.201.19:57:47.97#ibcon#read 6, iclass 21, count 2 2006.201.19:57:47.97#ibcon#end of sib2, iclass 21, count 2 2006.201.19:57:47.97#ibcon#*mode == 0, iclass 21, count 2 2006.201.19:57:47.97#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.19:57:47.97#ibcon#[25=AT01-08\r\n] 2006.201.19:57:47.97#ibcon#*before write, iclass 21, count 2 2006.201.19:57:47.97#ibcon#enter sib2, iclass 21, count 2 2006.201.19:57:47.97#ibcon#flushed, iclass 21, count 2 2006.201.19:57:47.97#ibcon#about to write, iclass 21, count 2 2006.201.19:57:47.97#ibcon#wrote, iclass 21, count 2 2006.201.19:57:47.97#ibcon#about to read 3, iclass 21, count 2 2006.201.19:57:48.01#ibcon#read 3, iclass 21, count 2 2006.201.19:57:48.01#ibcon#about to read 4, iclass 21, count 2 2006.201.19:57:48.01#ibcon#read 4, iclass 21, count 2 2006.201.19:57:48.01#ibcon#about to read 5, iclass 21, count 2 2006.201.19:57:48.01#ibcon#read 5, iclass 21, count 2 2006.201.19:57:48.01#ibcon#about to read 6, iclass 21, count 2 2006.201.19:57:48.01#ibcon#read 6, iclass 21, count 2 2006.201.19:57:48.01#ibcon#end of sib2, iclass 21, count 2 2006.201.19:57:48.01#ibcon#*after write, iclass 21, count 2 2006.201.19:57:48.01#ibcon#*before return 0, iclass 21, count 2 2006.201.19:57:48.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:48.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:48.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.19:57:48.01#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:48.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:48.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:48.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:48.13#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:57:48.13#ibcon#first serial, iclass 21, count 0 2006.201.19:57:48.13#ibcon#enter sib2, iclass 21, count 0 2006.201.19:57:48.13#ibcon#flushed, iclass 21, count 0 2006.201.19:57:48.13#ibcon#about to write, iclass 21, count 0 2006.201.19:57:48.13#ibcon#wrote, iclass 21, count 0 2006.201.19:57:48.13#ibcon#about to read 3, iclass 21, count 0 2006.201.19:57:48.15#ibcon#read 3, iclass 21, count 0 2006.201.19:57:48.15#ibcon#about to read 4, iclass 21, count 0 2006.201.19:57:48.15#ibcon#read 4, iclass 21, count 0 2006.201.19:57:48.15#ibcon#about to read 5, iclass 21, count 0 2006.201.19:57:48.15#ibcon#read 5, iclass 21, count 0 2006.201.19:57:48.15#ibcon#about to read 6, iclass 21, count 0 2006.201.19:57:48.15#ibcon#read 6, iclass 21, count 0 2006.201.19:57:48.15#ibcon#end of sib2, iclass 21, count 0 2006.201.19:57:48.15#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:57:48.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:57:48.15#ibcon#[25=USB\r\n] 2006.201.19:57:48.15#ibcon#*before write, iclass 21, count 0 2006.201.19:57:48.15#ibcon#enter sib2, iclass 21, count 0 2006.201.19:57:48.15#ibcon#flushed, iclass 21, count 0 2006.201.19:57:48.15#ibcon#about to write, iclass 21, count 0 2006.201.19:57:48.15#ibcon#wrote, iclass 21, count 0 2006.201.19:57:48.15#ibcon#about to read 3, iclass 21, count 0 2006.201.19:57:48.18#ibcon#read 3, iclass 21, count 0 2006.201.19:57:48.18#ibcon#about to read 4, iclass 21, count 0 2006.201.19:57:48.18#ibcon#read 4, iclass 21, count 0 2006.201.19:57:48.18#ibcon#about to read 5, iclass 21, count 0 2006.201.19:57:48.18#ibcon#read 5, iclass 21, count 0 2006.201.19:57:48.18#ibcon#about to read 6, iclass 21, count 0 2006.201.19:57:48.18#ibcon#read 6, iclass 21, count 0 2006.201.19:57:48.18#ibcon#end of sib2, iclass 21, count 0 2006.201.19:57:48.18#ibcon#*after write, iclass 21, count 0 2006.201.19:57:48.18#ibcon#*before return 0, iclass 21, count 0 2006.201.19:57:48.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:48.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:48.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:57:48.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:57:48.18$vck44/valo=2,534.99 2006.201.19:57:48.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.19:57:48.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.19:57:48.18#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:48.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:48.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:48.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:48.18#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:57:48.18#ibcon#first serial, iclass 23, count 0 2006.201.19:57:48.18#ibcon#enter sib2, iclass 23, count 0 2006.201.19:57:48.18#ibcon#flushed, iclass 23, count 0 2006.201.19:57:48.18#ibcon#about to write, iclass 23, count 0 2006.201.19:57:48.18#ibcon#wrote, iclass 23, count 0 2006.201.19:57:48.18#ibcon#about to read 3, iclass 23, count 0 2006.201.19:57:48.20#ibcon#read 3, iclass 23, count 0 2006.201.19:57:48.20#ibcon#about to read 4, iclass 23, count 0 2006.201.19:57:48.20#ibcon#read 4, iclass 23, count 0 2006.201.19:57:48.20#ibcon#about to read 5, iclass 23, count 0 2006.201.19:57:48.20#ibcon#read 5, iclass 23, count 0 2006.201.19:57:48.20#ibcon#about to read 6, iclass 23, count 0 2006.201.19:57:48.20#ibcon#read 6, iclass 23, count 0 2006.201.19:57:48.20#ibcon#end of sib2, iclass 23, count 0 2006.201.19:57:48.20#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:57:48.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:57:48.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.19:57:48.20#ibcon#*before write, iclass 23, count 0 2006.201.19:57:48.20#ibcon#enter sib2, iclass 23, count 0 2006.201.19:57:48.20#ibcon#flushed, iclass 23, count 0 2006.201.19:57:48.20#ibcon#about to write, iclass 23, count 0 2006.201.19:57:48.20#ibcon#wrote, iclass 23, count 0 2006.201.19:57:48.20#ibcon#about to read 3, iclass 23, count 0 2006.201.19:57:48.25#ibcon#read 3, iclass 23, count 0 2006.201.19:57:48.25#ibcon#about to read 4, iclass 23, count 0 2006.201.19:57:48.25#ibcon#read 4, iclass 23, count 0 2006.201.19:57:48.25#ibcon#about to read 5, iclass 23, count 0 2006.201.19:57:48.25#ibcon#read 5, iclass 23, count 0 2006.201.19:57:48.25#ibcon#about to read 6, iclass 23, count 0 2006.201.19:57:48.25#ibcon#read 6, iclass 23, count 0 2006.201.19:57:48.25#ibcon#end of sib2, iclass 23, count 0 2006.201.19:57:48.25#ibcon#*after write, iclass 23, count 0 2006.201.19:57:48.25#ibcon#*before return 0, iclass 23, count 0 2006.201.19:57:48.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:48.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:48.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:57:48.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:57:48.25$vck44/va=2,7 2006.201.19:57:48.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.19:57:48.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.19:57:48.25#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:48.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:48.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:48.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:48.30#ibcon#enter wrdev, iclass 25, count 2 2006.201.19:57:48.30#ibcon#first serial, iclass 25, count 2 2006.201.19:57:48.30#ibcon#enter sib2, iclass 25, count 2 2006.201.19:57:48.30#ibcon#flushed, iclass 25, count 2 2006.201.19:57:48.30#ibcon#about to write, iclass 25, count 2 2006.201.19:57:48.30#ibcon#wrote, iclass 25, count 2 2006.201.19:57:48.30#ibcon#about to read 3, iclass 25, count 2 2006.201.19:57:48.32#ibcon#read 3, iclass 25, count 2 2006.201.19:57:48.32#ibcon#about to read 4, iclass 25, count 2 2006.201.19:57:48.32#ibcon#read 4, iclass 25, count 2 2006.201.19:57:48.32#ibcon#about to read 5, iclass 25, count 2 2006.201.19:57:48.32#ibcon#read 5, iclass 25, count 2 2006.201.19:57:48.32#ibcon#about to read 6, iclass 25, count 2 2006.201.19:57:48.32#ibcon#read 6, iclass 25, count 2 2006.201.19:57:48.32#ibcon#end of sib2, iclass 25, count 2 2006.201.19:57:48.32#ibcon#*mode == 0, iclass 25, count 2 2006.201.19:57:48.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.19:57:48.32#ibcon#[25=AT02-07\r\n] 2006.201.19:57:48.32#ibcon#*before write, iclass 25, count 2 2006.201.19:57:48.32#ibcon#enter sib2, iclass 25, count 2 2006.201.19:57:48.32#ibcon#flushed, iclass 25, count 2 2006.201.19:57:48.32#ibcon#about to write, iclass 25, count 2 2006.201.19:57:48.32#ibcon#wrote, iclass 25, count 2 2006.201.19:57:48.32#ibcon#about to read 3, iclass 25, count 2 2006.201.19:57:48.35#ibcon#read 3, iclass 25, count 2 2006.201.19:57:48.35#ibcon#about to read 4, iclass 25, count 2 2006.201.19:57:48.35#ibcon#read 4, iclass 25, count 2 2006.201.19:57:48.35#ibcon#about to read 5, iclass 25, count 2 2006.201.19:57:48.35#ibcon#read 5, iclass 25, count 2 2006.201.19:57:48.35#ibcon#about to read 6, iclass 25, count 2 2006.201.19:57:48.35#ibcon#read 6, iclass 25, count 2 2006.201.19:57:48.35#ibcon#end of sib2, iclass 25, count 2 2006.201.19:57:48.35#ibcon#*after write, iclass 25, count 2 2006.201.19:57:48.35#ibcon#*before return 0, iclass 25, count 2 2006.201.19:57:48.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:48.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:48.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.19:57:48.35#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:48.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:48.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:48.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:48.47#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:57:48.47#ibcon#first serial, iclass 25, count 0 2006.201.19:57:48.47#ibcon#enter sib2, iclass 25, count 0 2006.201.19:57:48.47#ibcon#flushed, iclass 25, count 0 2006.201.19:57:48.47#ibcon#about to write, iclass 25, count 0 2006.201.19:57:48.47#ibcon#wrote, iclass 25, count 0 2006.201.19:57:48.47#ibcon#about to read 3, iclass 25, count 0 2006.201.19:57:48.49#ibcon#read 3, iclass 25, count 0 2006.201.19:57:48.49#ibcon#about to read 4, iclass 25, count 0 2006.201.19:57:48.49#ibcon#read 4, iclass 25, count 0 2006.201.19:57:48.49#ibcon#about to read 5, iclass 25, count 0 2006.201.19:57:48.49#ibcon#read 5, iclass 25, count 0 2006.201.19:57:48.49#ibcon#about to read 6, iclass 25, count 0 2006.201.19:57:48.49#ibcon#read 6, iclass 25, count 0 2006.201.19:57:48.49#ibcon#end of sib2, iclass 25, count 0 2006.201.19:57:48.49#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:57:48.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:57:48.49#ibcon#[25=USB\r\n] 2006.201.19:57:48.49#ibcon#*before write, iclass 25, count 0 2006.201.19:57:48.49#ibcon#enter sib2, iclass 25, count 0 2006.201.19:57:48.49#ibcon#flushed, iclass 25, count 0 2006.201.19:57:48.49#ibcon#about to write, iclass 25, count 0 2006.201.19:57:48.49#ibcon#wrote, iclass 25, count 0 2006.201.19:57:48.49#ibcon#about to read 3, iclass 25, count 0 2006.201.19:57:48.52#ibcon#read 3, iclass 25, count 0 2006.201.19:57:48.52#ibcon#about to read 4, iclass 25, count 0 2006.201.19:57:48.52#ibcon#read 4, iclass 25, count 0 2006.201.19:57:48.52#ibcon#about to read 5, iclass 25, count 0 2006.201.19:57:48.52#ibcon#read 5, iclass 25, count 0 2006.201.19:57:48.52#ibcon#about to read 6, iclass 25, count 0 2006.201.19:57:48.52#ibcon#read 6, iclass 25, count 0 2006.201.19:57:48.52#ibcon#end of sib2, iclass 25, count 0 2006.201.19:57:48.52#ibcon#*after write, iclass 25, count 0 2006.201.19:57:48.52#ibcon#*before return 0, iclass 25, count 0 2006.201.19:57:48.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:48.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:48.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:57:48.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:57:48.52$vck44/valo=3,564.99 2006.201.19:57:48.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.19:57:48.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.19:57:48.52#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:48.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:48.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:48.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:48.52#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:57:48.52#ibcon#first serial, iclass 27, count 0 2006.201.19:57:48.52#ibcon#enter sib2, iclass 27, count 0 2006.201.19:57:48.52#ibcon#flushed, iclass 27, count 0 2006.201.19:57:48.52#ibcon#about to write, iclass 27, count 0 2006.201.19:57:48.52#ibcon#wrote, iclass 27, count 0 2006.201.19:57:48.52#ibcon#about to read 3, iclass 27, count 0 2006.201.19:57:48.54#ibcon#read 3, iclass 27, count 0 2006.201.19:57:48.54#ibcon#about to read 4, iclass 27, count 0 2006.201.19:57:48.54#ibcon#read 4, iclass 27, count 0 2006.201.19:57:48.54#ibcon#about to read 5, iclass 27, count 0 2006.201.19:57:48.54#ibcon#read 5, iclass 27, count 0 2006.201.19:57:48.54#ibcon#about to read 6, iclass 27, count 0 2006.201.19:57:48.54#ibcon#read 6, iclass 27, count 0 2006.201.19:57:48.54#ibcon#end of sib2, iclass 27, count 0 2006.201.19:57:48.54#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:57:48.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:57:48.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.19:57:48.54#ibcon#*before write, iclass 27, count 0 2006.201.19:57:48.54#ibcon#enter sib2, iclass 27, count 0 2006.201.19:57:48.54#ibcon#flushed, iclass 27, count 0 2006.201.19:57:48.54#ibcon#about to write, iclass 27, count 0 2006.201.19:57:48.54#ibcon#wrote, iclass 27, count 0 2006.201.19:57:48.54#ibcon#about to read 3, iclass 27, count 0 2006.201.19:57:48.59#ibcon#read 3, iclass 27, count 0 2006.201.19:57:48.59#ibcon#about to read 4, iclass 27, count 0 2006.201.19:57:48.59#ibcon#read 4, iclass 27, count 0 2006.201.19:57:48.59#ibcon#about to read 5, iclass 27, count 0 2006.201.19:57:48.59#ibcon#read 5, iclass 27, count 0 2006.201.19:57:48.59#ibcon#about to read 6, iclass 27, count 0 2006.201.19:57:48.59#ibcon#read 6, iclass 27, count 0 2006.201.19:57:48.59#ibcon#end of sib2, iclass 27, count 0 2006.201.19:57:48.59#ibcon#*after write, iclass 27, count 0 2006.201.19:57:48.59#ibcon#*before return 0, iclass 27, count 0 2006.201.19:57:48.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:48.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:48.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:57:48.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:57:48.59$vck44/va=3,8 2006.201.19:57:48.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.19:57:48.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.19:57:48.59#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:48.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:48.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:48.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:48.64#ibcon#enter wrdev, iclass 29, count 2 2006.201.19:57:48.64#ibcon#first serial, iclass 29, count 2 2006.201.19:57:48.64#ibcon#enter sib2, iclass 29, count 2 2006.201.19:57:48.64#ibcon#flushed, iclass 29, count 2 2006.201.19:57:48.64#ibcon#about to write, iclass 29, count 2 2006.201.19:57:48.64#ibcon#wrote, iclass 29, count 2 2006.201.19:57:48.64#ibcon#about to read 3, iclass 29, count 2 2006.201.19:57:48.66#ibcon#read 3, iclass 29, count 2 2006.201.19:57:48.66#ibcon#about to read 4, iclass 29, count 2 2006.201.19:57:48.66#ibcon#read 4, iclass 29, count 2 2006.201.19:57:48.66#ibcon#about to read 5, iclass 29, count 2 2006.201.19:57:48.66#ibcon#read 5, iclass 29, count 2 2006.201.19:57:48.66#ibcon#about to read 6, iclass 29, count 2 2006.201.19:57:48.66#ibcon#read 6, iclass 29, count 2 2006.201.19:57:48.66#ibcon#end of sib2, iclass 29, count 2 2006.201.19:57:48.66#ibcon#*mode == 0, iclass 29, count 2 2006.201.19:57:48.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.19:57:48.66#ibcon#[25=AT03-08\r\n] 2006.201.19:57:48.66#ibcon#*before write, iclass 29, count 2 2006.201.19:57:48.66#ibcon#enter sib2, iclass 29, count 2 2006.201.19:57:48.66#ibcon#flushed, iclass 29, count 2 2006.201.19:57:48.66#ibcon#about to write, iclass 29, count 2 2006.201.19:57:48.66#ibcon#wrote, iclass 29, count 2 2006.201.19:57:48.66#ibcon#about to read 3, iclass 29, count 2 2006.201.19:57:48.69#ibcon#read 3, iclass 29, count 2 2006.201.19:57:48.69#ibcon#about to read 4, iclass 29, count 2 2006.201.19:57:48.69#ibcon#read 4, iclass 29, count 2 2006.201.19:57:48.69#ibcon#about to read 5, iclass 29, count 2 2006.201.19:57:48.69#ibcon#read 5, iclass 29, count 2 2006.201.19:57:48.69#ibcon#about to read 6, iclass 29, count 2 2006.201.19:57:48.69#ibcon#read 6, iclass 29, count 2 2006.201.19:57:48.69#ibcon#end of sib2, iclass 29, count 2 2006.201.19:57:48.69#ibcon#*after write, iclass 29, count 2 2006.201.19:57:48.69#ibcon#*before return 0, iclass 29, count 2 2006.201.19:57:48.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:48.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:48.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.19:57:48.69#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:48.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:48.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:48.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:48.81#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:57:48.81#ibcon#first serial, iclass 29, count 0 2006.201.19:57:48.81#ibcon#enter sib2, iclass 29, count 0 2006.201.19:57:48.81#ibcon#flushed, iclass 29, count 0 2006.201.19:57:48.81#ibcon#about to write, iclass 29, count 0 2006.201.19:57:48.81#ibcon#wrote, iclass 29, count 0 2006.201.19:57:48.81#ibcon#about to read 3, iclass 29, count 0 2006.201.19:57:48.83#ibcon#read 3, iclass 29, count 0 2006.201.19:57:48.83#ibcon#about to read 4, iclass 29, count 0 2006.201.19:57:48.83#ibcon#read 4, iclass 29, count 0 2006.201.19:57:48.83#ibcon#about to read 5, iclass 29, count 0 2006.201.19:57:48.83#ibcon#read 5, iclass 29, count 0 2006.201.19:57:48.83#ibcon#about to read 6, iclass 29, count 0 2006.201.19:57:48.83#ibcon#read 6, iclass 29, count 0 2006.201.19:57:48.83#ibcon#end of sib2, iclass 29, count 0 2006.201.19:57:48.83#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:57:48.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:57:48.83#ibcon#[25=USB\r\n] 2006.201.19:57:48.83#ibcon#*before write, iclass 29, count 0 2006.201.19:57:48.83#ibcon#enter sib2, iclass 29, count 0 2006.201.19:57:48.83#ibcon#flushed, iclass 29, count 0 2006.201.19:57:48.83#ibcon#about to write, iclass 29, count 0 2006.201.19:57:48.83#ibcon#wrote, iclass 29, count 0 2006.201.19:57:48.83#ibcon#about to read 3, iclass 29, count 0 2006.201.19:57:48.86#ibcon#read 3, iclass 29, count 0 2006.201.19:57:48.86#ibcon#about to read 4, iclass 29, count 0 2006.201.19:57:48.86#ibcon#read 4, iclass 29, count 0 2006.201.19:57:48.86#ibcon#about to read 5, iclass 29, count 0 2006.201.19:57:48.86#ibcon#read 5, iclass 29, count 0 2006.201.19:57:48.86#ibcon#about to read 6, iclass 29, count 0 2006.201.19:57:48.86#ibcon#read 6, iclass 29, count 0 2006.201.19:57:48.86#ibcon#end of sib2, iclass 29, count 0 2006.201.19:57:48.86#ibcon#*after write, iclass 29, count 0 2006.201.19:57:48.86#ibcon#*before return 0, iclass 29, count 0 2006.201.19:57:48.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:48.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:48.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:57:48.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:57:48.86$vck44/valo=4,624.99 2006.201.19:57:48.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.19:57:48.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.19:57:48.86#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:48.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:48.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:48.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:48.86#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:57:48.86#ibcon#first serial, iclass 31, count 0 2006.201.19:57:48.86#ibcon#enter sib2, iclass 31, count 0 2006.201.19:57:48.86#ibcon#flushed, iclass 31, count 0 2006.201.19:57:48.86#ibcon#about to write, iclass 31, count 0 2006.201.19:57:48.86#ibcon#wrote, iclass 31, count 0 2006.201.19:57:48.86#ibcon#about to read 3, iclass 31, count 0 2006.201.19:57:48.88#ibcon#read 3, iclass 31, count 0 2006.201.19:57:48.88#ibcon#about to read 4, iclass 31, count 0 2006.201.19:57:48.88#ibcon#read 4, iclass 31, count 0 2006.201.19:57:48.88#ibcon#about to read 5, iclass 31, count 0 2006.201.19:57:48.88#ibcon#read 5, iclass 31, count 0 2006.201.19:57:48.88#ibcon#about to read 6, iclass 31, count 0 2006.201.19:57:48.88#ibcon#read 6, iclass 31, count 0 2006.201.19:57:48.88#ibcon#end of sib2, iclass 31, count 0 2006.201.19:57:48.88#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:57:48.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:57:48.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.19:57:48.88#ibcon#*before write, iclass 31, count 0 2006.201.19:57:48.88#ibcon#enter sib2, iclass 31, count 0 2006.201.19:57:48.88#ibcon#flushed, iclass 31, count 0 2006.201.19:57:48.88#ibcon#about to write, iclass 31, count 0 2006.201.19:57:48.88#ibcon#wrote, iclass 31, count 0 2006.201.19:57:48.88#ibcon#about to read 3, iclass 31, count 0 2006.201.19:57:48.93#ibcon#read 3, iclass 31, count 0 2006.201.19:57:48.93#ibcon#about to read 4, iclass 31, count 0 2006.201.19:57:48.93#ibcon#read 4, iclass 31, count 0 2006.201.19:57:48.93#ibcon#about to read 5, iclass 31, count 0 2006.201.19:57:48.93#ibcon#read 5, iclass 31, count 0 2006.201.19:57:48.93#ibcon#about to read 6, iclass 31, count 0 2006.201.19:57:48.93#ibcon#read 6, iclass 31, count 0 2006.201.19:57:48.93#ibcon#end of sib2, iclass 31, count 0 2006.201.19:57:48.93#ibcon#*after write, iclass 31, count 0 2006.201.19:57:48.93#ibcon#*before return 0, iclass 31, count 0 2006.201.19:57:48.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:48.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:48.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:57:48.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:57:48.93$vck44/va=4,7 2006.201.19:57:48.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.19:57:48.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.19:57:48.93#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:48.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:48.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:48.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:48.98#ibcon#enter wrdev, iclass 33, count 2 2006.201.19:57:48.98#ibcon#first serial, iclass 33, count 2 2006.201.19:57:48.98#ibcon#enter sib2, iclass 33, count 2 2006.201.19:57:48.98#ibcon#flushed, iclass 33, count 2 2006.201.19:57:48.98#ibcon#about to write, iclass 33, count 2 2006.201.19:57:48.98#ibcon#wrote, iclass 33, count 2 2006.201.19:57:48.98#ibcon#about to read 3, iclass 33, count 2 2006.201.19:57:49.00#ibcon#read 3, iclass 33, count 2 2006.201.19:57:49.00#ibcon#about to read 4, iclass 33, count 2 2006.201.19:57:49.00#ibcon#read 4, iclass 33, count 2 2006.201.19:57:49.00#ibcon#about to read 5, iclass 33, count 2 2006.201.19:57:49.00#ibcon#read 5, iclass 33, count 2 2006.201.19:57:49.00#ibcon#about to read 6, iclass 33, count 2 2006.201.19:57:49.00#ibcon#read 6, iclass 33, count 2 2006.201.19:57:49.00#ibcon#end of sib2, iclass 33, count 2 2006.201.19:57:49.00#ibcon#*mode == 0, iclass 33, count 2 2006.201.19:57:49.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.19:57:49.00#ibcon#[25=AT04-07\r\n] 2006.201.19:57:49.00#ibcon#*before write, iclass 33, count 2 2006.201.19:57:49.00#ibcon#enter sib2, iclass 33, count 2 2006.201.19:57:49.00#ibcon#flushed, iclass 33, count 2 2006.201.19:57:49.00#ibcon#about to write, iclass 33, count 2 2006.201.19:57:49.00#ibcon#wrote, iclass 33, count 2 2006.201.19:57:49.00#ibcon#about to read 3, iclass 33, count 2 2006.201.19:57:49.03#ibcon#read 3, iclass 33, count 2 2006.201.19:57:49.03#ibcon#about to read 4, iclass 33, count 2 2006.201.19:57:49.03#ibcon#read 4, iclass 33, count 2 2006.201.19:57:49.03#ibcon#about to read 5, iclass 33, count 2 2006.201.19:57:49.03#ibcon#read 5, iclass 33, count 2 2006.201.19:57:49.03#ibcon#about to read 6, iclass 33, count 2 2006.201.19:57:49.03#ibcon#read 6, iclass 33, count 2 2006.201.19:57:49.03#ibcon#end of sib2, iclass 33, count 2 2006.201.19:57:49.03#ibcon#*after write, iclass 33, count 2 2006.201.19:57:49.03#ibcon#*before return 0, iclass 33, count 2 2006.201.19:57:49.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:49.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:49.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.19:57:49.03#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:49.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:49.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:49.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:49.15#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:57:49.15#ibcon#first serial, iclass 33, count 0 2006.201.19:57:49.15#ibcon#enter sib2, iclass 33, count 0 2006.201.19:57:49.15#ibcon#flushed, iclass 33, count 0 2006.201.19:57:49.15#ibcon#about to write, iclass 33, count 0 2006.201.19:57:49.15#ibcon#wrote, iclass 33, count 0 2006.201.19:57:49.15#ibcon#about to read 3, iclass 33, count 0 2006.201.19:57:49.17#ibcon#read 3, iclass 33, count 0 2006.201.19:57:49.17#ibcon#about to read 4, iclass 33, count 0 2006.201.19:57:49.17#ibcon#read 4, iclass 33, count 0 2006.201.19:57:49.17#ibcon#about to read 5, iclass 33, count 0 2006.201.19:57:49.17#ibcon#read 5, iclass 33, count 0 2006.201.19:57:49.17#ibcon#about to read 6, iclass 33, count 0 2006.201.19:57:49.17#ibcon#read 6, iclass 33, count 0 2006.201.19:57:49.17#ibcon#end of sib2, iclass 33, count 0 2006.201.19:57:49.17#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:57:49.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:57:49.17#ibcon#[25=USB\r\n] 2006.201.19:57:49.17#ibcon#*before write, iclass 33, count 0 2006.201.19:57:49.17#ibcon#enter sib2, iclass 33, count 0 2006.201.19:57:49.17#ibcon#flushed, iclass 33, count 0 2006.201.19:57:49.17#ibcon#about to write, iclass 33, count 0 2006.201.19:57:49.17#ibcon#wrote, iclass 33, count 0 2006.201.19:57:49.17#ibcon#about to read 3, iclass 33, count 0 2006.201.19:57:49.20#ibcon#read 3, iclass 33, count 0 2006.201.19:57:49.20#ibcon#about to read 4, iclass 33, count 0 2006.201.19:57:49.20#ibcon#read 4, iclass 33, count 0 2006.201.19:57:49.20#ibcon#about to read 5, iclass 33, count 0 2006.201.19:57:49.20#ibcon#read 5, iclass 33, count 0 2006.201.19:57:49.20#ibcon#about to read 6, iclass 33, count 0 2006.201.19:57:49.20#ibcon#read 6, iclass 33, count 0 2006.201.19:57:49.20#ibcon#end of sib2, iclass 33, count 0 2006.201.19:57:49.20#ibcon#*after write, iclass 33, count 0 2006.201.19:57:49.20#ibcon#*before return 0, iclass 33, count 0 2006.201.19:57:49.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:49.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:49.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:57:49.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:57:49.20$vck44/valo=5,734.99 2006.201.19:57:49.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.19:57:49.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.19:57:49.20#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:49.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:49.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:49.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:49.20#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:57:49.20#ibcon#first serial, iclass 35, count 0 2006.201.19:57:49.20#ibcon#enter sib2, iclass 35, count 0 2006.201.19:57:49.20#ibcon#flushed, iclass 35, count 0 2006.201.19:57:49.20#ibcon#about to write, iclass 35, count 0 2006.201.19:57:49.20#ibcon#wrote, iclass 35, count 0 2006.201.19:57:49.20#ibcon#about to read 3, iclass 35, count 0 2006.201.19:57:49.22#ibcon#read 3, iclass 35, count 0 2006.201.19:57:49.22#ibcon#about to read 4, iclass 35, count 0 2006.201.19:57:49.22#ibcon#read 4, iclass 35, count 0 2006.201.19:57:49.22#ibcon#about to read 5, iclass 35, count 0 2006.201.19:57:49.22#ibcon#read 5, iclass 35, count 0 2006.201.19:57:49.22#ibcon#about to read 6, iclass 35, count 0 2006.201.19:57:49.22#ibcon#read 6, iclass 35, count 0 2006.201.19:57:49.22#ibcon#end of sib2, iclass 35, count 0 2006.201.19:57:49.22#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:57:49.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:57:49.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.19:57:49.22#ibcon#*before write, iclass 35, count 0 2006.201.19:57:49.22#ibcon#enter sib2, iclass 35, count 0 2006.201.19:57:49.22#ibcon#flushed, iclass 35, count 0 2006.201.19:57:49.22#ibcon#about to write, iclass 35, count 0 2006.201.19:57:49.22#ibcon#wrote, iclass 35, count 0 2006.201.19:57:49.22#ibcon#about to read 3, iclass 35, count 0 2006.201.19:57:49.26#ibcon#read 3, iclass 35, count 0 2006.201.19:57:49.26#ibcon#about to read 4, iclass 35, count 0 2006.201.19:57:49.26#ibcon#read 4, iclass 35, count 0 2006.201.19:57:49.26#ibcon#about to read 5, iclass 35, count 0 2006.201.19:57:49.26#ibcon#read 5, iclass 35, count 0 2006.201.19:57:49.26#ibcon#about to read 6, iclass 35, count 0 2006.201.19:57:49.26#ibcon#read 6, iclass 35, count 0 2006.201.19:57:49.26#ibcon#end of sib2, iclass 35, count 0 2006.201.19:57:49.26#ibcon#*after write, iclass 35, count 0 2006.201.19:57:49.26#ibcon#*before return 0, iclass 35, count 0 2006.201.19:57:49.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:49.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:49.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:57:49.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:57:49.26$vck44/va=5,4 2006.201.19:57:49.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.19:57:49.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.19:57:49.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:49.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:49.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:49.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:49.32#ibcon#enter wrdev, iclass 37, count 2 2006.201.19:57:49.32#ibcon#first serial, iclass 37, count 2 2006.201.19:57:49.32#ibcon#enter sib2, iclass 37, count 2 2006.201.19:57:49.32#ibcon#flushed, iclass 37, count 2 2006.201.19:57:49.32#ibcon#about to write, iclass 37, count 2 2006.201.19:57:49.32#ibcon#wrote, iclass 37, count 2 2006.201.19:57:49.32#ibcon#about to read 3, iclass 37, count 2 2006.201.19:57:49.34#ibcon#read 3, iclass 37, count 2 2006.201.19:57:49.34#ibcon#about to read 4, iclass 37, count 2 2006.201.19:57:49.34#ibcon#read 4, iclass 37, count 2 2006.201.19:57:49.34#ibcon#about to read 5, iclass 37, count 2 2006.201.19:57:49.34#ibcon#read 5, iclass 37, count 2 2006.201.19:57:49.34#ibcon#about to read 6, iclass 37, count 2 2006.201.19:57:49.34#ibcon#read 6, iclass 37, count 2 2006.201.19:57:49.34#ibcon#end of sib2, iclass 37, count 2 2006.201.19:57:49.34#ibcon#*mode == 0, iclass 37, count 2 2006.201.19:57:49.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.19:57:49.34#ibcon#[25=AT05-04\r\n] 2006.201.19:57:49.34#ibcon#*before write, iclass 37, count 2 2006.201.19:57:49.34#ibcon#enter sib2, iclass 37, count 2 2006.201.19:57:49.34#ibcon#flushed, iclass 37, count 2 2006.201.19:57:49.34#ibcon#about to write, iclass 37, count 2 2006.201.19:57:49.34#ibcon#wrote, iclass 37, count 2 2006.201.19:57:49.34#ibcon#about to read 3, iclass 37, count 2 2006.201.19:57:49.37#ibcon#read 3, iclass 37, count 2 2006.201.19:57:49.37#ibcon#about to read 4, iclass 37, count 2 2006.201.19:57:49.37#ibcon#read 4, iclass 37, count 2 2006.201.19:57:49.37#ibcon#about to read 5, iclass 37, count 2 2006.201.19:57:49.37#ibcon#read 5, iclass 37, count 2 2006.201.19:57:49.37#ibcon#about to read 6, iclass 37, count 2 2006.201.19:57:49.37#ibcon#read 6, iclass 37, count 2 2006.201.19:57:49.37#ibcon#end of sib2, iclass 37, count 2 2006.201.19:57:49.37#ibcon#*after write, iclass 37, count 2 2006.201.19:57:49.37#ibcon#*before return 0, iclass 37, count 2 2006.201.19:57:49.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:49.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:49.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.19:57:49.37#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:49.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:49.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:49.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:49.49#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:57:49.49#ibcon#first serial, iclass 37, count 0 2006.201.19:57:49.49#ibcon#enter sib2, iclass 37, count 0 2006.201.19:57:49.49#ibcon#flushed, iclass 37, count 0 2006.201.19:57:49.49#ibcon#about to write, iclass 37, count 0 2006.201.19:57:49.49#ibcon#wrote, iclass 37, count 0 2006.201.19:57:49.49#ibcon#about to read 3, iclass 37, count 0 2006.201.19:57:49.51#ibcon#read 3, iclass 37, count 0 2006.201.19:57:49.51#ibcon#about to read 4, iclass 37, count 0 2006.201.19:57:49.51#ibcon#read 4, iclass 37, count 0 2006.201.19:57:49.51#ibcon#about to read 5, iclass 37, count 0 2006.201.19:57:49.51#ibcon#read 5, iclass 37, count 0 2006.201.19:57:49.51#ibcon#about to read 6, iclass 37, count 0 2006.201.19:57:49.51#ibcon#read 6, iclass 37, count 0 2006.201.19:57:49.51#ibcon#end of sib2, iclass 37, count 0 2006.201.19:57:49.51#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:57:49.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:57:49.51#ibcon#[25=USB\r\n] 2006.201.19:57:49.51#ibcon#*before write, iclass 37, count 0 2006.201.19:57:49.51#ibcon#enter sib2, iclass 37, count 0 2006.201.19:57:49.51#ibcon#flushed, iclass 37, count 0 2006.201.19:57:49.51#ibcon#about to write, iclass 37, count 0 2006.201.19:57:49.51#ibcon#wrote, iclass 37, count 0 2006.201.19:57:49.51#ibcon#about to read 3, iclass 37, count 0 2006.201.19:57:49.54#ibcon#read 3, iclass 37, count 0 2006.201.19:57:49.54#ibcon#about to read 4, iclass 37, count 0 2006.201.19:57:49.54#ibcon#read 4, iclass 37, count 0 2006.201.19:57:49.54#ibcon#about to read 5, iclass 37, count 0 2006.201.19:57:49.54#ibcon#read 5, iclass 37, count 0 2006.201.19:57:49.54#ibcon#about to read 6, iclass 37, count 0 2006.201.19:57:49.54#ibcon#read 6, iclass 37, count 0 2006.201.19:57:49.54#ibcon#end of sib2, iclass 37, count 0 2006.201.19:57:49.54#ibcon#*after write, iclass 37, count 0 2006.201.19:57:49.54#ibcon#*before return 0, iclass 37, count 0 2006.201.19:57:49.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:49.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:49.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:57:49.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:57:49.54$vck44/valo=6,814.99 2006.201.19:57:49.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.19:57:49.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.19:57:49.54#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:49.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:49.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:49.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:49.54#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:57:49.54#ibcon#first serial, iclass 39, count 0 2006.201.19:57:49.54#ibcon#enter sib2, iclass 39, count 0 2006.201.19:57:49.54#ibcon#flushed, iclass 39, count 0 2006.201.19:57:49.54#ibcon#about to write, iclass 39, count 0 2006.201.19:57:49.54#ibcon#wrote, iclass 39, count 0 2006.201.19:57:49.54#ibcon#about to read 3, iclass 39, count 0 2006.201.19:57:49.56#ibcon#read 3, iclass 39, count 0 2006.201.19:57:49.56#ibcon#about to read 4, iclass 39, count 0 2006.201.19:57:49.56#ibcon#read 4, iclass 39, count 0 2006.201.19:57:49.56#ibcon#about to read 5, iclass 39, count 0 2006.201.19:57:49.56#ibcon#read 5, iclass 39, count 0 2006.201.19:57:49.56#ibcon#about to read 6, iclass 39, count 0 2006.201.19:57:49.56#ibcon#read 6, iclass 39, count 0 2006.201.19:57:49.56#ibcon#end of sib2, iclass 39, count 0 2006.201.19:57:49.56#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:57:49.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:57:49.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.19:57:49.56#ibcon#*before write, iclass 39, count 0 2006.201.19:57:49.56#ibcon#enter sib2, iclass 39, count 0 2006.201.19:57:49.56#ibcon#flushed, iclass 39, count 0 2006.201.19:57:49.56#ibcon#about to write, iclass 39, count 0 2006.201.19:57:49.56#ibcon#wrote, iclass 39, count 0 2006.201.19:57:49.56#ibcon#about to read 3, iclass 39, count 0 2006.201.19:57:49.61#ibcon#read 3, iclass 39, count 0 2006.201.19:57:49.61#ibcon#about to read 4, iclass 39, count 0 2006.201.19:57:49.61#ibcon#read 4, iclass 39, count 0 2006.201.19:57:49.61#ibcon#about to read 5, iclass 39, count 0 2006.201.19:57:49.61#ibcon#read 5, iclass 39, count 0 2006.201.19:57:49.61#ibcon#about to read 6, iclass 39, count 0 2006.201.19:57:49.61#ibcon#read 6, iclass 39, count 0 2006.201.19:57:49.61#ibcon#end of sib2, iclass 39, count 0 2006.201.19:57:49.61#ibcon#*after write, iclass 39, count 0 2006.201.19:57:49.61#ibcon#*before return 0, iclass 39, count 0 2006.201.19:57:49.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:49.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:49.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:57:49.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:57:49.61$vck44/va=6,5 2006.201.19:57:49.61#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.19:57:49.61#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.19:57:49.61#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:49.61#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:49.66#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:49.66#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:49.66#ibcon#enter wrdev, iclass 2, count 2 2006.201.19:57:49.66#ibcon#first serial, iclass 2, count 2 2006.201.19:57:49.66#ibcon#enter sib2, iclass 2, count 2 2006.201.19:57:49.66#ibcon#flushed, iclass 2, count 2 2006.201.19:57:49.66#ibcon#about to write, iclass 2, count 2 2006.201.19:57:49.66#ibcon#wrote, iclass 2, count 2 2006.201.19:57:49.66#ibcon#about to read 3, iclass 2, count 2 2006.201.19:57:49.68#ibcon#read 3, iclass 2, count 2 2006.201.19:57:49.68#ibcon#about to read 4, iclass 2, count 2 2006.201.19:57:49.68#ibcon#read 4, iclass 2, count 2 2006.201.19:57:49.68#ibcon#about to read 5, iclass 2, count 2 2006.201.19:57:49.68#ibcon#read 5, iclass 2, count 2 2006.201.19:57:49.68#ibcon#about to read 6, iclass 2, count 2 2006.201.19:57:49.68#ibcon#read 6, iclass 2, count 2 2006.201.19:57:49.68#ibcon#end of sib2, iclass 2, count 2 2006.201.19:57:49.68#ibcon#*mode == 0, iclass 2, count 2 2006.201.19:57:49.68#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.19:57:49.68#ibcon#[25=AT06-05\r\n] 2006.201.19:57:49.68#ibcon#*before write, iclass 2, count 2 2006.201.19:57:49.68#ibcon#enter sib2, iclass 2, count 2 2006.201.19:57:49.68#ibcon#flushed, iclass 2, count 2 2006.201.19:57:49.68#ibcon#about to write, iclass 2, count 2 2006.201.19:57:49.68#ibcon#wrote, iclass 2, count 2 2006.201.19:57:49.68#ibcon#about to read 3, iclass 2, count 2 2006.201.19:57:49.71#ibcon#read 3, iclass 2, count 2 2006.201.19:57:49.71#ibcon#about to read 4, iclass 2, count 2 2006.201.19:57:49.71#ibcon#read 4, iclass 2, count 2 2006.201.19:57:49.71#ibcon#about to read 5, iclass 2, count 2 2006.201.19:57:49.71#ibcon#read 5, iclass 2, count 2 2006.201.19:57:49.71#ibcon#about to read 6, iclass 2, count 2 2006.201.19:57:49.71#ibcon#read 6, iclass 2, count 2 2006.201.19:57:49.71#ibcon#end of sib2, iclass 2, count 2 2006.201.19:57:49.71#ibcon#*after write, iclass 2, count 2 2006.201.19:57:49.71#ibcon#*before return 0, iclass 2, count 2 2006.201.19:57:49.71#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:49.71#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:49.71#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.19:57:49.71#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:49.71#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:49.83#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:49.83#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:49.83#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:57:49.83#ibcon#first serial, iclass 2, count 0 2006.201.19:57:49.83#ibcon#enter sib2, iclass 2, count 0 2006.201.19:57:49.83#ibcon#flushed, iclass 2, count 0 2006.201.19:57:49.83#ibcon#about to write, iclass 2, count 0 2006.201.19:57:49.83#ibcon#wrote, iclass 2, count 0 2006.201.19:57:49.83#ibcon#about to read 3, iclass 2, count 0 2006.201.19:57:49.85#ibcon#read 3, iclass 2, count 0 2006.201.19:57:49.85#ibcon#about to read 4, iclass 2, count 0 2006.201.19:57:49.85#ibcon#read 4, iclass 2, count 0 2006.201.19:57:49.85#ibcon#about to read 5, iclass 2, count 0 2006.201.19:57:49.85#ibcon#read 5, iclass 2, count 0 2006.201.19:57:49.85#ibcon#about to read 6, iclass 2, count 0 2006.201.19:57:49.85#ibcon#read 6, iclass 2, count 0 2006.201.19:57:49.85#ibcon#end of sib2, iclass 2, count 0 2006.201.19:57:49.85#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:57:49.85#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:57:49.85#ibcon#[25=USB\r\n] 2006.201.19:57:49.85#ibcon#*before write, iclass 2, count 0 2006.201.19:57:49.85#ibcon#enter sib2, iclass 2, count 0 2006.201.19:57:49.85#ibcon#flushed, iclass 2, count 0 2006.201.19:57:49.85#ibcon#about to write, iclass 2, count 0 2006.201.19:57:49.85#ibcon#wrote, iclass 2, count 0 2006.201.19:57:49.85#ibcon#about to read 3, iclass 2, count 0 2006.201.19:57:49.88#ibcon#read 3, iclass 2, count 0 2006.201.19:57:49.88#ibcon#about to read 4, iclass 2, count 0 2006.201.19:57:49.88#ibcon#read 4, iclass 2, count 0 2006.201.19:57:49.88#ibcon#about to read 5, iclass 2, count 0 2006.201.19:57:49.88#ibcon#read 5, iclass 2, count 0 2006.201.19:57:49.88#ibcon#about to read 6, iclass 2, count 0 2006.201.19:57:49.88#ibcon#read 6, iclass 2, count 0 2006.201.19:57:49.88#ibcon#end of sib2, iclass 2, count 0 2006.201.19:57:49.88#ibcon#*after write, iclass 2, count 0 2006.201.19:57:49.88#ibcon#*before return 0, iclass 2, count 0 2006.201.19:57:49.88#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:49.88#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:49.88#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:57:49.88#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:57:49.88$vck44/valo=7,864.99 2006.201.19:57:49.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.19:57:49.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.19:57:49.88#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:49.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:49.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:49.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:49.88#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:57:49.88#ibcon#first serial, iclass 5, count 0 2006.201.19:57:49.88#ibcon#enter sib2, iclass 5, count 0 2006.201.19:57:49.88#ibcon#flushed, iclass 5, count 0 2006.201.19:57:49.88#ibcon#about to write, iclass 5, count 0 2006.201.19:57:49.88#ibcon#wrote, iclass 5, count 0 2006.201.19:57:49.88#ibcon#about to read 3, iclass 5, count 0 2006.201.19:57:49.90#ibcon#read 3, iclass 5, count 0 2006.201.19:57:49.90#ibcon#about to read 4, iclass 5, count 0 2006.201.19:57:49.90#ibcon#read 4, iclass 5, count 0 2006.201.19:57:49.90#ibcon#about to read 5, iclass 5, count 0 2006.201.19:57:49.90#ibcon#read 5, iclass 5, count 0 2006.201.19:57:49.90#ibcon#about to read 6, iclass 5, count 0 2006.201.19:57:49.90#ibcon#read 6, iclass 5, count 0 2006.201.19:57:49.90#ibcon#end of sib2, iclass 5, count 0 2006.201.19:57:49.90#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:57:49.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:57:49.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.19:57:49.90#ibcon#*before write, iclass 5, count 0 2006.201.19:57:49.90#ibcon#enter sib2, iclass 5, count 0 2006.201.19:57:49.90#ibcon#flushed, iclass 5, count 0 2006.201.19:57:49.90#ibcon#about to write, iclass 5, count 0 2006.201.19:57:49.90#ibcon#wrote, iclass 5, count 0 2006.201.19:57:49.90#ibcon#about to read 3, iclass 5, count 0 2006.201.19:57:49.94#ibcon#read 3, iclass 5, count 0 2006.201.19:57:49.94#ibcon#about to read 4, iclass 5, count 0 2006.201.19:57:49.94#ibcon#read 4, iclass 5, count 0 2006.201.19:57:49.94#ibcon#about to read 5, iclass 5, count 0 2006.201.19:57:49.94#ibcon#read 5, iclass 5, count 0 2006.201.19:57:49.94#ibcon#about to read 6, iclass 5, count 0 2006.201.19:57:49.94#ibcon#read 6, iclass 5, count 0 2006.201.19:57:49.94#ibcon#end of sib2, iclass 5, count 0 2006.201.19:57:49.94#ibcon#*after write, iclass 5, count 0 2006.201.19:57:49.94#ibcon#*before return 0, iclass 5, count 0 2006.201.19:57:49.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:49.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:49.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:57:49.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:57:49.94$vck44/va=7,5 2006.201.19:57:49.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.19:57:49.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.19:57:49.94#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:49.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:50.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:50.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:50.00#ibcon#enter wrdev, iclass 7, count 2 2006.201.19:57:50.00#ibcon#first serial, iclass 7, count 2 2006.201.19:57:50.00#ibcon#enter sib2, iclass 7, count 2 2006.201.19:57:50.00#ibcon#flushed, iclass 7, count 2 2006.201.19:57:50.00#ibcon#about to write, iclass 7, count 2 2006.201.19:57:50.00#ibcon#wrote, iclass 7, count 2 2006.201.19:57:50.00#ibcon#about to read 3, iclass 7, count 2 2006.201.19:57:50.02#ibcon#read 3, iclass 7, count 2 2006.201.19:57:50.02#ibcon#about to read 4, iclass 7, count 2 2006.201.19:57:50.02#ibcon#read 4, iclass 7, count 2 2006.201.19:57:50.02#ibcon#about to read 5, iclass 7, count 2 2006.201.19:57:50.02#ibcon#read 5, iclass 7, count 2 2006.201.19:57:50.02#ibcon#about to read 6, iclass 7, count 2 2006.201.19:57:50.02#ibcon#read 6, iclass 7, count 2 2006.201.19:57:50.02#ibcon#end of sib2, iclass 7, count 2 2006.201.19:57:50.02#ibcon#*mode == 0, iclass 7, count 2 2006.201.19:57:50.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.19:57:50.02#ibcon#[25=AT07-05\r\n] 2006.201.19:57:50.02#ibcon#*before write, iclass 7, count 2 2006.201.19:57:50.02#ibcon#enter sib2, iclass 7, count 2 2006.201.19:57:50.02#ibcon#flushed, iclass 7, count 2 2006.201.19:57:50.02#ibcon#about to write, iclass 7, count 2 2006.201.19:57:50.02#ibcon#wrote, iclass 7, count 2 2006.201.19:57:50.02#ibcon#about to read 3, iclass 7, count 2 2006.201.19:57:50.05#ibcon#read 3, iclass 7, count 2 2006.201.19:57:50.05#ibcon#about to read 4, iclass 7, count 2 2006.201.19:57:50.05#ibcon#read 4, iclass 7, count 2 2006.201.19:57:50.05#ibcon#about to read 5, iclass 7, count 2 2006.201.19:57:50.05#ibcon#read 5, iclass 7, count 2 2006.201.19:57:50.05#ibcon#about to read 6, iclass 7, count 2 2006.201.19:57:50.05#ibcon#read 6, iclass 7, count 2 2006.201.19:57:50.05#ibcon#end of sib2, iclass 7, count 2 2006.201.19:57:50.05#ibcon#*after write, iclass 7, count 2 2006.201.19:57:50.05#ibcon#*before return 0, iclass 7, count 2 2006.201.19:57:50.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:50.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:50.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.19:57:50.05#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:50.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:50.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:50.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:50.17#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:57:50.17#ibcon#first serial, iclass 7, count 0 2006.201.19:57:50.17#ibcon#enter sib2, iclass 7, count 0 2006.201.19:57:50.17#ibcon#flushed, iclass 7, count 0 2006.201.19:57:50.17#ibcon#about to write, iclass 7, count 0 2006.201.19:57:50.17#ibcon#wrote, iclass 7, count 0 2006.201.19:57:50.17#ibcon#about to read 3, iclass 7, count 0 2006.201.19:57:50.20#ibcon#read 3, iclass 7, count 0 2006.201.19:57:50.20#ibcon#about to read 4, iclass 7, count 0 2006.201.19:57:50.20#ibcon#read 4, iclass 7, count 0 2006.201.19:57:50.20#ibcon#about to read 5, iclass 7, count 0 2006.201.19:57:50.20#ibcon#read 5, iclass 7, count 0 2006.201.19:57:50.20#ibcon#about to read 6, iclass 7, count 0 2006.201.19:57:50.20#ibcon#read 6, iclass 7, count 0 2006.201.19:57:50.20#ibcon#end of sib2, iclass 7, count 0 2006.201.19:57:50.20#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:57:50.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:57:50.20#ibcon#[25=USB\r\n] 2006.201.19:57:50.20#ibcon#*before write, iclass 7, count 0 2006.201.19:57:50.20#ibcon#enter sib2, iclass 7, count 0 2006.201.19:57:50.20#ibcon#flushed, iclass 7, count 0 2006.201.19:57:50.20#ibcon#about to write, iclass 7, count 0 2006.201.19:57:50.20#ibcon#wrote, iclass 7, count 0 2006.201.19:57:50.20#ibcon#about to read 3, iclass 7, count 0 2006.201.19:57:50.23#ibcon#read 3, iclass 7, count 0 2006.201.19:57:50.23#ibcon#about to read 4, iclass 7, count 0 2006.201.19:57:50.23#ibcon#read 4, iclass 7, count 0 2006.201.19:57:50.23#ibcon#about to read 5, iclass 7, count 0 2006.201.19:57:50.23#ibcon#read 5, iclass 7, count 0 2006.201.19:57:50.23#ibcon#about to read 6, iclass 7, count 0 2006.201.19:57:50.23#ibcon#read 6, iclass 7, count 0 2006.201.19:57:50.23#ibcon#end of sib2, iclass 7, count 0 2006.201.19:57:50.23#ibcon#*after write, iclass 7, count 0 2006.201.19:57:50.23#ibcon#*before return 0, iclass 7, count 0 2006.201.19:57:50.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:50.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:50.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:57:50.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:57:50.23$vck44/valo=8,884.99 2006.201.19:57:50.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.19:57:50.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.19:57:50.23#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:50.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:50.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:50.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:50.23#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:57:50.23#ibcon#first serial, iclass 11, count 0 2006.201.19:57:50.23#ibcon#enter sib2, iclass 11, count 0 2006.201.19:57:50.23#ibcon#flushed, iclass 11, count 0 2006.201.19:57:50.23#ibcon#about to write, iclass 11, count 0 2006.201.19:57:50.23#ibcon#wrote, iclass 11, count 0 2006.201.19:57:50.23#ibcon#about to read 3, iclass 11, count 0 2006.201.19:57:50.25#ibcon#read 3, iclass 11, count 0 2006.201.19:57:50.25#ibcon#about to read 4, iclass 11, count 0 2006.201.19:57:50.25#ibcon#read 4, iclass 11, count 0 2006.201.19:57:50.25#ibcon#about to read 5, iclass 11, count 0 2006.201.19:57:50.25#ibcon#read 5, iclass 11, count 0 2006.201.19:57:50.25#ibcon#about to read 6, iclass 11, count 0 2006.201.19:57:50.25#ibcon#read 6, iclass 11, count 0 2006.201.19:57:50.25#ibcon#end of sib2, iclass 11, count 0 2006.201.19:57:50.25#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:57:50.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:57:50.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.19:57:50.25#ibcon#*before write, iclass 11, count 0 2006.201.19:57:50.25#ibcon#enter sib2, iclass 11, count 0 2006.201.19:57:50.25#ibcon#flushed, iclass 11, count 0 2006.201.19:57:50.25#ibcon#about to write, iclass 11, count 0 2006.201.19:57:50.25#ibcon#wrote, iclass 11, count 0 2006.201.19:57:50.25#ibcon#about to read 3, iclass 11, count 0 2006.201.19:57:50.29#ibcon#read 3, iclass 11, count 0 2006.201.19:57:50.29#ibcon#about to read 4, iclass 11, count 0 2006.201.19:57:50.29#ibcon#read 4, iclass 11, count 0 2006.201.19:57:50.29#ibcon#about to read 5, iclass 11, count 0 2006.201.19:57:50.29#ibcon#read 5, iclass 11, count 0 2006.201.19:57:50.29#ibcon#about to read 6, iclass 11, count 0 2006.201.19:57:50.29#ibcon#read 6, iclass 11, count 0 2006.201.19:57:50.29#ibcon#end of sib2, iclass 11, count 0 2006.201.19:57:50.29#ibcon#*after write, iclass 11, count 0 2006.201.19:57:50.29#ibcon#*before return 0, iclass 11, count 0 2006.201.19:57:50.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:50.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:50.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:57:50.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:57:50.29$vck44/va=8,4 2006.201.19:57:50.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.19:57:50.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.19:57:50.29#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:50.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:57:50.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:57:50.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:57:50.35#ibcon#enter wrdev, iclass 13, count 2 2006.201.19:57:50.35#ibcon#first serial, iclass 13, count 2 2006.201.19:57:50.35#ibcon#enter sib2, iclass 13, count 2 2006.201.19:57:50.35#ibcon#flushed, iclass 13, count 2 2006.201.19:57:50.35#ibcon#about to write, iclass 13, count 2 2006.201.19:57:50.35#ibcon#wrote, iclass 13, count 2 2006.201.19:57:50.35#ibcon#about to read 3, iclass 13, count 2 2006.201.19:57:50.37#ibcon#read 3, iclass 13, count 2 2006.201.19:57:50.37#ibcon#about to read 4, iclass 13, count 2 2006.201.19:57:50.37#ibcon#read 4, iclass 13, count 2 2006.201.19:57:50.37#ibcon#about to read 5, iclass 13, count 2 2006.201.19:57:50.37#ibcon#read 5, iclass 13, count 2 2006.201.19:57:50.37#ibcon#about to read 6, iclass 13, count 2 2006.201.19:57:50.37#ibcon#read 6, iclass 13, count 2 2006.201.19:57:50.37#ibcon#end of sib2, iclass 13, count 2 2006.201.19:57:50.37#ibcon#*mode == 0, iclass 13, count 2 2006.201.19:57:50.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.19:57:50.37#ibcon#[25=AT08-04\r\n] 2006.201.19:57:50.37#ibcon#*before write, iclass 13, count 2 2006.201.19:57:50.37#ibcon#enter sib2, iclass 13, count 2 2006.201.19:57:50.37#ibcon#flushed, iclass 13, count 2 2006.201.19:57:50.37#ibcon#about to write, iclass 13, count 2 2006.201.19:57:50.37#ibcon#wrote, iclass 13, count 2 2006.201.19:57:50.37#ibcon#about to read 3, iclass 13, count 2 2006.201.19:57:50.40#ibcon#read 3, iclass 13, count 2 2006.201.19:57:50.40#ibcon#about to read 4, iclass 13, count 2 2006.201.19:57:50.40#ibcon#read 4, iclass 13, count 2 2006.201.19:57:50.40#ibcon#about to read 5, iclass 13, count 2 2006.201.19:57:50.40#ibcon#read 5, iclass 13, count 2 2006.201.19:57:50.40#ibcon#about to read 6, iclass 13, count 2 2006.201.19:57:50.40#ibcon#read 6, iclass 13, count 2 2006.201.19:57:50.40#ibcon#end of sib2, iclass 13, count 2 2006.201.19:57:50.40#ibcon#*after write, iclass 13, count 2 2006.201.19:57:50.40#ibcon#*before return 0, iclass 13, count 2 2006.201.19:57:50.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:57:50.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.19:57:50.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.19:57:50.40#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:50.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:57:50.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:57:50.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:57:50.52#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:57:50.52#ibcon#first serial, iclass 13, count 0 2006.201.19:57:50.52#ibcon#enter sib2, iclass 13, count 0 2006.201.19:57:50.52#ibcon#flushed, iclass 13, count 0 2006.201.19:57:50.52#ibcon#about to write, iclass 13, count 0 2006.201.19:57:50.52#ibcon#wrote, iclass 13, count 0 2006.201.19:57:50.52#ibcon#about to read 3, iclass 13, count 0 2006.201.19:57:50.54#ibcon#read 3, iclass 13, count 0 2006.201.19:57:50.54#ibcon#about to read 4, iclass 13, count 0 2006.201.19:57:50.54#ibcon#read 4, iclass 13, count 0 2006.201.19:57:50.54#ibcon#about to read 5, iclass 13, count 0 2006.201.19:57:50.54#ibcon#read 5, iclass 13, count 0 2006.201.19:57:50.54#ibcon#about to read 6, iclass 13, count 0 2006.201.19:57:50.54#ibcon#read 6, iclass 13, count 0 2006.201.19:57:50.54#ibcon#end of sib2, iclass 13, count 0 2006.201.19:57:50.54#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:57:50.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:57:50.54#ibcon#[25=USB\r\n] 2006.201.19:57:50.54#ibcon#*before write, iclass 13, count 0 2006.201.19:57:50.54#ibcon#enter sib2, iclass 13, count 0 2006.201.19:57:50.54#ibcon#flushed, iclass 13, count 0 2006.201.19:57:50.54#ibcon#about to write, iclass 13, count 0 2006.201.19:57:50.54#ibcon#wrote, iclass 13, count 0 2006.201.19:57:50.54#ibcon#about to read 3, iclass 13, count 0 2006.201.19:57:50.57#ibcon#read 3, iclass 13, count 0 2006.201.19:57:50.57#ibcon#about to read 4, iclass 13, count 0 2006.201.19:57:50.57#ibcon#read 4, iclass 13, count 0 2006.201.19:57:50.57#ibcon#about to read 5, iclass 13, count 0 2006.201.19:57:50.57#ibcon#read 5, iclass 13, count 0 2006.201.19:57:50.57#ibcon#about to read 6, iclass 13, count 0 2006.201.19:57:50.57#ibcon#read 6, iclass 13, count 0 2006.201.19:57:50.57#ibcon#end of sib2, iclass 13, count 0 2006.201.19:57:50.57#ibcon#*after write, iclass 13, count 0 2006.201.19:57:50.57#ibcon#*before return 0, iclass 13, count 0 2006.201.19:57:50.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:57:50.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.19:57:50.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:57:50.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:57:50.57$vck44/vblo=1,629.99 2006.201.19:57:50.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.19:57:50.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.19:57:50.57#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:50.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:57:50.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:57:50.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:57:50.57#ibcon#enter wrdev, iclass 15, count 0 2006.201.19:57:50.57#ibcon#first serial, iclass 15, count 0 2006.201.19:57:50.57#ibcon#enter sib2, iclass 15, count 0 2006.201.19:57:50.57#ibcon#flushed, iclass 15, count 0 2006.201.19:57:50.57#ibcon#about to write, iclass 15, count 0 2006.201.19:57:50.57#ibcon#wrote, iclass 15, count 0 2006.201.19:57:50.57#ibcon#about to read 3, iclass 15, count 0 2006.201.19:57:50.59#ibcon#read 3, iclass 15, count 0 2006.201.19:57:50.59#ibcon#about to read 4, iclass 15, count 0 2006.201.19:57:50.59#ibcon#read 4, iclass 15, count 0 2006.201.19:57:50.59#ibcon#about to read 5, iclass 15, count 0 2006.201.19:57:50.59#ibcon#read 5, iclass 15, count 0 2006.201.19:57:50.59#ibcon#about to read 6, iclass 15, count 0 2006.201.19:57:50.59#ibcon#read 6, iclass 15, count 0 2006.201.19:57:50.59#ibcon#end of sib2, iclass 15, count 0 2006.201.19:57:50.59#ibcon#*mode == 0, iclass 15, count 0 2006.201.19:57:50.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.19:57:50.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.19:57:50.59#ibcon#*before write, iclass 15, count 0 2006.201.19:57:50.59#ibcon#enter sib2, iclass 15, count 0 2006.201.19:57:50.59#ibcon#flushed, iclass 15, count 0 2006.201.19:57:50.59#ibcon#about to write, iclass 15, count 0 2006.201.19:57:50.59#ibcon#wrote, iclass 15, count 0 2006.201.19:57:50.59#ibcon#about to read 3, iclass 15, count 0 2006.201.19:57:50.63#ibcon#read 3, iclass 15, count 0 2006.201.19:57:50.63#ibcon#about to read 4, iclass 15, count 0 2006.201.19:57:50.63#ibcon#read 4, iclass 15, count 0 2006.201.19:57:50.63#ibcon#about to read 5, iclass 15, count 0 2006.201.19:57:50.63#ibcon#read 5, iclass 15, count 0 2006.201.19:57:50.63#ibcon#about to read 6, iclass 15, count 0 2006.201.19:57:50.63#ibcon#read 6, iclass 15, count 0 2006.201.19:57:50.63#ibcon#end of sib2, iclass 15, count 0 2006.201.19:57:50.63#ibcon#*after write, iclass 15, count 0 2006.201.19:57:50.63#ibcon#*before return 0, iclass 15, count 0 2006.201.19:57:50.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:57:50.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.19:57:50.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.19:57:50.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.19:57:50.63$vck44/vb=1,4 2006.201.19:57:50.63#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.19:57:50.63#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.19:57:50.63#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:50.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:57:50.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:57:50.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:57:50.63#ibcon#enter wrdev, iclass 17, count 2 2006.201.19:57:50.63#ibcon#first serial, iclass 17, count 2 2006.201.19:57:50.63#ibcon#enter sib2, iclass 17, count 2 2006.201.19:57:50.63#ibcon#flushed, iclass 17, count 2 2006.201.19:57:50.63#ibcon#about to write, iclass 17, count 2 2006.201.19:57:50.63#ibcon#wrote, iclass 17, count 2 2006.201.19:57:50.63#ibcon#about to read 3, iclass 17, count 2 2006.201.19:57:50.65#ibcon#read 3, iclass 17, count 2 2006.201.19:57:50.65#ibcon#about to read 4, iclass 17, count 2 2006.201.19:57:50.65#ibcon#read 4, iclass 17, count 2 2006.201.19:57:50.65#ibcon#about to read 5, iclass 17, count 2 2006.201.19:57:50.65#ibcon#read 5, iclass 17, count 2 2006.201.19:57:50.65#ibcon#about to read 6, iclass 17, count 2 2006.201.19:57:50.65#ibcon#read 6, iclass 17, count 2 2006.201.19:57:50.65#ibcon#end of sib2, iclass 17, count 2 2006.201.19:57:50.65#ibcon#*mode == 0, iclass 17, count 2 2006.201.19:57:50.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.19:57:50.65#ibcon#[27=AT01-04\r\n] 2006.201.19:57:50.65#ibcon#*before write, iclass 17, count 2 2006.201.19:57:50.65#ibcon#enter sib2, iclass 17, count 2 2006.201.19:57:50.65#ibcon#flushed, iclass 17, count 2 2006.201.19:57:50.65#ibcon#about to write, iclass 17, count 2 2006.201.19:57:50.65#ibcon#wrote, iclass 17, count 2 2006.201.19:57:50.65#ibcon#about to read 3, iclass 17, count 2 2006.201.19:57:50.68#ibcon#read 3, iclass 17, count 2 2006.201.19:57:50.68#ibcon#about to read 4, iclass 17, count 2 2006.201.19:57:50.68#ibcon#read 4, iclass 17, count 2 2006.201.19:57:50.68#ibcon#about to read 5, iclass 17, count 2 2006.201.19:57:50.68#ibcon#read 5, iclass 17, count 2 2006.201.19:57:50.68#ibcon#about to read 6, iclass 17, count 2 2006.201.19:57:50.68#ibcon#read 6, iclass 17, count 2 2006.201.19:57:50.68#ibcon#end of sib2, iclass 17, count 2 2006.201.19:57:50.68#ibcon#*after write, iclass 17, count 2 2006.201.19:57:50.68#ibcon#*before return 0, iclass 17, count 2 2006.201.19:57:50.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:57:50.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.19:57:50.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.19:57:50.68#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:50.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:57:50.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:57:50.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:57:50.80#ibcon#enter wrdev, iclass 17, count 0 2006.201.19:57:50.80#ibcon#first serial, iclass 17, count 0 2006.201.19:57:50.80#ibcon#enter sib2, iclass 17, count 0 2006.201.19:57:50.80#ibcon#flushed, iclass 17, count 0 2006.201.19:57:50.80#ibcon#about to write, iclass 17, count 0 2006.201.19:57:50.80#ibcon#wrote, iclass 17, count 0 2006.201.19:57:50.80#ibcon#about to read 3, iclass 17, count 0 2006.201.19:57:50.82#ibcon#read 3, iclass 17, count 0 2006.201.19:57:50.82#ibcon#about to read 4, iclass 17, count 0 2006.201.19:57:50.82#ibcon#read 4, iclass 17, count 0 2006.201.19:57:50.82#ibcon#about to read 5, iclass 17, count 0 2006.201.19:57:50.82#ibcon#read 5, iclass 17, count 0 2006.201.19:57:50.82#ibcon#about to read 6, iclass 17, count 0 2006.201.19:57:50.82#ibcon#read 6, iclass 17, count 0 2006.201.19:57:50.82#ibcon#end of sib2, iclass 17, count 0 2006.201.19:57:50.82#ibcon#*mode == 0, iclass 17, count 0 2006.201.19:57:50.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.19:57:50.82#ibcon#[27=USB\r\n] 2006.201.19:57:50.82#ibcon#*before write, iclass 17, count 0 2006.201.19:57:50.82#ibcon#enter sib2, iclass 17, count 0 2006.201.19:57:50.82#ibcon#flushed, iclass 17, count 0 2006.201.19:57:50.82#ibcon#about to write, iclass 17, count 0 2006.201.19:57:50.82#ibcon#wrote, iclass 17, count 0 2006.201.19:57:50.82#ibcon#about to read 3, iclass 17, count 0 2006.201.19:57:50.85#ibcon#read 3, iclass 17, count 0 2006.201.19:57:50.85#ibcon#about to read 4, iclass 17, count 0 2006.201.19:57:50.85#ibcon#read 4, iclass 17, count 0 2006.201.19:57:50.85#ibcon#about to read 5, iclass 17, count 0 2006.201.19:57:50.85#ibcon#read 5, iclass 17, count 0 2006.201.19:57:50.85#ibcon#about to read 6, iclass 17, count 0 2006.201.19:57:50.85#ibcon#read 6, iclass 17, count 0 2006.201.19:57:50.85#ibcon#end of sib2, iclass 17, count 0 2006.201.19:57:50.85#ibcon#*after write, iclass 17, count 0 2006.201.19:57:50.85#ibcon#*before return 0, iclass 17, count 0 2006.201.19:57:50.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:57:50.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.19:57:50.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.19:57:50.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.19:57:50.85$vck44/vblo=2,634.99 2006.201.19:57:50.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.19:57:50.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.19:57:50.85#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:50.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:50.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:50.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:50.85#ibcon#enter wrdev, iclass 19, count 0 2006.201.19:57:50.85#ibcon#first serial, iclass 19, count 0 2006.201.19:57:50.85#ibcon#enter sib2, iclass 19, count 0 2006.201.19:57:50.85#ibcon#flushed, iclass 19, count 0 2006.201.19:57:50.85#ibcon#about to write, iclass 19, count 0 2006.201.19:57:50.85#ibcon#wrote, iclass 19, count 0 2006.201.19:57:50.85#ibcon#about to read 3, iclass 19, count 0 2006.201.19:57:50.87#ibcon#read 3, iclass 19, count 0 2006.201.19:57:50.87#ibcon#about to read 4, iclass 19, count 0 2006.201.19:57:50.87#ibcon#read 4, iclass 19, count 0 2006.201.19:57:50.87#ibcon#about to read 5, iclass 19, count 0 2006.201.19:57:50.87#ibcon#read 5, iclass 19, count 0 2006.201.19:57:50.87#ibcon#about to read 6, iclass 19, count 0 2006.201.19:57:50.87#ibcon#read 6, iclass 19, count 0 2006.201.19:57:50.87#ibcon#end of sib2, iclass 19, count 0 2006.201.19:57:50.87#ibcon#*mode == 0, iclass 19, count 0 2006.201.19:57:50.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.19:57:50.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.19:57:50.87#ibcon#*before write, iclass 19, count 0 2006.201.19:57:50.87#ibcon#enter sib2, iclass 19, count 0 2006.201.19:57:50.87#ibcon#flushed, iclass 19, count 0 2006.201.19:57:50.87#ibcon#about to write, iclass 19, count 0 2006.201.19:57:50.87#ibcon#wrote, iclass 19, count 0 2006.201.19:57:50.87#ibcon#about to read 3, iclass 19, count 0 2006.201.19:57:50.92#ibcon#read 3, iclass 19, count 0 2006.201.19:57:50.92#ibcon#about to read 4, iclass 19, count 0 2006.201.19:57:50.92#ibcon#read 4, iclass 19, count 0 2006.201.19:57:50.92#ibcon#about to read 5, iclass 19, count 0 2006.201.19:57:50.92#ibcon#read 5, iclass 19, count 0 2006.201.19:57:50.92#ibcon#about to read 6, iclass 19, count 0 2006.201.19:57:50.92#ibcon#read 6, iclass 19, count 0 2006.201.19:57:50.92#ibcon#end of sib2, iclass 19, count 0 2006.201.19:57:50.92#ibcon#*after write, iclass 19, count 0 2006.201.19:57:50.92#ibcon#*before return 0, iclass 19, count 0 2006.201.19:57:50.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:50.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.19:57:50.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.19:57:50.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.19:57:50.92$vck44/vb=2,5 2006.201.19:57:50.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.19:57:50.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.19:57:50.92#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:50.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:50.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:50.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:50.97#ibcon#enter wrdev, iclass 21, count 2 2006.201.19:57:50.97#ibcon#first serial, iclass 21, count 2 2006.201.19:57:50.97#ibcon#enter sib2, iclass 21, count 2 2006.201.19:57:50.97#ibcon#flushed, iclass 21, count 2 2006.201.19:57:50.97#ibcon#about to write, iclass 21, count 2 2006.201.19:57:50.97#ibcon#wrote, iclass 21, count 2 2006.201.19:57:50.97#ibcon#about to read 3, iclass 21, count 2 2006.201.19:57:50.99#ibcon#read 3, iclass 21, count 2 2006.201.19:57:50.99#ibcon#about to read 4, iclass 21, count 2 2006.201.19:57:50.99#ibcon#read 4, iclass 21, count 2 2006.201.19:57:50.99#ibcon#about to read 5, iclass 21, count 2 2006.201.19:57:50.99#ibcon#read 5, iclass 21, count 2 2006.201.19:57:50.99#ibcon#about to read 6, iclass 21, count 2 2006.201.19:57:50.99#ibcon#read 6, iclass 21, count 2 2006.201.19:57:50.99#ibcon#end of sib2, iclass 21, count 2 2006.201.19:57:50.99#ibcon#*mode == 0, iclass 21, count 2 2006.201.19:57:50.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.19:57:50.99#ibcon#[27=AT02-05\r\n] 2006.201.19:57:50.99#ibcon#*before write, iclass 21, count 2 2006.201.19:57:50.99#ibcon#enter sib2, iclass 21, count 2 2006.201.19:57:50.99#ibcon#flushed, iclass 21, count 2 2006.201.19:57:50.99#ibcon#about to write, iclass 21, count 2 2006.201.19:57:50.99#ibcon#wrote, iclass 21, count 2 2006.201.19:57:50.99#ibcon#about to read 3, iclass 21, count 2 2006.201.19:57:51.02#ibcon#read 3, iclass 21, count 2 2006.201.19:57:51.02#ibcon#about to read 4, iclass 21, count 2 2006.201.19:57:51.02#ibcon#read 4, iclass 21, count 2 2006.201.19:57:51.02#ibcon#about to read 5, iclass 21, count 2 2006.201.19:57:51.02#ibcon#read 5, iclass 21, count 2 2006.201.19:57:51.02#ibcon#about to read 6, iclass 21, count 2 2006.201.19:57:51.02#ibcon#read 6, iclass 21, count 2 2006.201.19:57:51.02#ibcon#end of sib2, iclass 21, count 2 2006.201.19:57:51.02#ibcon#*after write, iclass 21, count 2 2006.201.19:57:51.02#ibcon#*before return 0, iclass 21, count 2 2006.201.19:57:51.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:51.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.19:57:51.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.19:57:51.02#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:51.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:51.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:51.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:51.14#ibcon#enter wrdev, iclass 21, count 0 2006.201.19:57:51.14#ibcon#first serial, iclass 21, count 0 2006.201.19:57:51.14#ibcon#enter sib2, iclass 21, count 0 2006.201.19:57:51.14#ibcon#flushed, iclass 21, count 0 2006.201.19:57:51.14#ibcon#about to write, iclass 21, count 0 2006.201.19:57:51.14#ibcon#wrote, iclass 21, count 0 2006.201.19:57:51.14#ibcon#about to read 3, iclass 21, count 0 2006.201.19:57:51.16#ibcon#read 3, iclass 21, count 0 2006.201.19:57:51.16#ibcon#about to read 4, iclass 21, count 0 2006.201.19:57:51.16#ibcon#read 4, iclass 21, count 0 2006.201.19:57:51.16#ibcon#about to read 5, iclass 21, count 0 2006.201.19:57:51.16#ibcon#read 5, iclass 21, count 0 2006.201.19:57:51.16#ibcon#about to read 6, iclass 21, count 0 2006.201.19:57:51.16#ibcon#read 6, iclass 21, count 0 2006.201.19:57:51.16#ibcon#end of sib2, iclass 21, count 0 2006.201.19:57:51.16#ibcon#*mode == 0, iclass 21, count 0 2006.201.19:57:51.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.19:57:51.16#ibcon#[27=USB\r\n] 2006.201.19:57:51.16#ibcon#*before write, iclass 21, count 0 2006.201.19:57:51.16#ibcon#enter sib2, iclass 21, count 0 2006.201.19:57:51.16#ibcon#flushed, iclass 21, count 0 2006.201.19:57:51.16#ibcon#about to write, iclass 21, count 0 2006.201.19:57:51.16#ibcon#wrote, iclass 21, count 0 2006.201.19:57:51.16#ibcon#about to read 3, iclass 21, count 0 2006.201.19:57:51.19#ibcon#read 3, iclass 21, count 0 2006.201.19:57:51.19#ibcon#about to read 4, iclass 21, count 0 2006.201.19:57:51.19#ibcon#read 4, iclass 21, count 0 2006.201.19:57:51.19#ibcon#about to read 5, iclass 21, count 0 2006.201.19:57:51.19#ibcon#read 5, iclass 21, count 0 2006.201.19:57:51.19#ibcon#about to read 6, iclass 21, count 0 2006.201.19:57:51.19#ibcon#read 6, iclass 21, count 0 2006.201.19:57:51.19#ibcon#end of sib2, iclass 21, count 0 2006.201.19:57:51.19#ibcon#*after write, iclass 21, count 0 2006.201.19:57:51.19#ibcon#*before return 0, iclass 21, count 0 2006.201.19:57:51.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:51.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.19:57:51.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.19:57:51.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.19:57:51.19$vck44/vblo=3,649.99 2006.201.19:57:51.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.19:57:51.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.19:57:51.19#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:51.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:51.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:51.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:51.19#ibcon#enter wrdev, iclass 23, count 0 2006.201.19:57:51.19#ibcon#first serial, iclass 23, count 0 2006.201.19:57:51.19#ibcon#enter sib2, iclass 23, count 0 2006.201.19:57:51.19#ibcon#flushed, iclass 23, count 0 2006.201.19:57:51.19#ibcon#about to write, iclass 23, count 0 2006.201.19:57:51.19#ibcon#wrote, iclass 23, count 0 2006.201.19:57:51.19#ibcon#about to read 3, iclass 23, count 0 2006.201.19:57:51.21#ibcon#read 3, iclass 23, count 0 2006.201.19:57:51.21#ibcon#about to read 4, iclass 23, count 0 2006.201.19:57:51.21#ibcon#read 4, iclass 23, count 0 2006.201.19:57:51.21#ibcon#about to read 5, iclass 23, count 0 2006.201.19:57:51.21#ibcon#read 5, iclass 23, count 0 2006.201.19:57:51.21#ibcon#about to read 6, iclass 23, count 0 2006.201.19:57:51.21#ibcon#read 6, iclass 23, count 0 2006.201.19:57:51.21#ibcon#end of sib2, iclass 23, count 0 2006.201.19:57:51.21#ibcon#*mode == 0, iclass 23, count 0 2006.201.19:57:51.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.19:57:51.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.19:57:51.21#ibcon#*before write, iclass 23, count 0 2006.201.19:57:51.21#ibcon#enter sib2, iclass 23, count 0 2006.201.19:57:51.21#ibcon#flushed, iclass 23, count 0 2006.201.19:57:51.21#ibcon#about to write, iclass 23, count 0 2006.201.19:57:51.21#ibcon#wrote, iclass 23, count 0 2006.201.19:57:51.21#ibcon#about to read 3, iclass 23, count 0 2006.201.19:57:51.26#ibcon#read 3, iclass 23, count 0 2006.201.19:57:51.26#ibcon#about to read 4, iclass 23, count 0 2006.201.19:57:51.26#ibcon#read 4, iclass 23, count 0 2006.201.19:57:51.26#ibcon#about to read 5, iclass 23, count 0 2006.201.19:57:51.26#ibcon#read 5, iclass 23, count 0 2006.201.19:57:51.26#ibcon#about to read 6, iclass 23, count 0 2006.201.19:57:51.26#ibcon#read 6, iclass 23, count 0 2006.201.19:57:51.26#ibcon#end of sib2, iclass 23, count 0 2006.201.19:57:51.26#ibcon#*after write, iclass 23, count 0 2006.201.19:57:51.26#ibcon#*before return 0, iclass 23, count 0 2006.201.19:57:51.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:51.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.19:57:51.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.19:57:51.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.19:57:51.26$vck44/vb=3,4 2006.201.19:57:51.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.19:57:51.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.19:57:51.26#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:51.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:51.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:51.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:51.31#ibcon#enter wrdev, iclass 25, count 2 2006.201.19:57:51.31#ibcon#first serial, iclass 25, count 2 2006.201.19:57:51.31#ibcon#enter sib2, iclass 25, count 2 2006.201.19:57:51.31#ibcon#flushed, iclass 25, count 2 2006.201.19:57:51.31#ibcon#about to write, iclass 25, count 2 2006.201.19:57:51.31#ibcon#wrote, iclass 25, count 2 2006.201.19:57:51.31#ibcon#about to read 3, iclass 25, count 2 2006.201.19:57:51.33#ibcon#read 3, iclass 25, count 2 2006.201.19:57:51.33#ibcon#about to read 4, iclass 25, count 2 2006.201.19:57:51.33#ibcon#read 4, iclass 25, count 2 2006.201.19:57:51.33#ibcon#about to read 5, iclass 25, count 2 2006.201.19:57:51.33#ibcon#read 5, iclass 25, count 2 2006.201.19:57:51.33#ibcon#about to read 6, iclass 25, count 2 2006.201.19:57:51.33#ibcon#read 6, iclass 25, count 2 2006.201.19:57:51.33#ibcon#end of sib2, iclass 25, count 2 2006.201.19:57:51.33#ibcon#*mode == 0, iclass 25, count 2 2006.201.19:57:51.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.19:57:51.33#ibcon#[27=AT03-04\r\n] 2006.201.19:57:51.33#ibcon#*before write, iclass 25, count 2 2006.201.19:57:51.33#ibcon#enter sib2, iclass 25, count 2 2006.201.19:57:51.33#ibcon#flushed, iclass 25, count 2 2006.201.19:57:51.33#ibcon#about to write, iclass 25, count 2 2006.201.19:57:51.33#ibcon#wrote, iclass 25, count 2 2006.201.19:57:51.33#ibcon#about to read 3, iclass 25, count 2 2006.201.19:57:51.36#ibcon#read 3, iclass 25, count 2 2006.201.19:57:51.36#ibcon#about to read 4, iclass 25, count 2 2006.201.19:57:51.36#ibcon#read 4, iclass 25, count 2 2006.201.19:57:51.36#ibcon#about to read 5, iclass 25, count 2 2006.201.19:57:51.36#ibcon#read 5, iclass 25, count 2 2006.201.19:57:51.36#ibcon#about to read 6, iclass 25, count 2 2006.201.19:57:51.36#ibcon#read 6, iclass 25, count 2 2006.201.19:57:51.36#ibcon#end of sib2, iclass 25, count 2 2006.201.19:57:51.36#ibcon#*after write, iclass 25, count 2 2006.201.19:57:51.36#ibcon#*before return 0, iclass 25, count 2 2006.201.19:57:51.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:51.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.19:57:51.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.19:57:51.36#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:51.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:51.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:51.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:51.48#ibcon#enter wrdev, iclass 25, count 0 2006.201.19:57:51.48#ibcon#first serial, iclass 25, count 0 2006.201.19:57:51.48#ibcon#enter sib2, iclass 25, count 0 2006.201.19:57:51.48#ibcon#flushed, iclass 25, count 0 2006.201.19:57:51.48#ibcon#about to write, iclass 25, count 0 2006.201.19:57:51.48#ibcon#wrote, iclass 25, count 0 2006.201.19:57:51.48#ibcon#about to read 3, iclass 25, count 0 2006.201.19:57:51.50#ibcon#read 3, iclass 25, count 0 2006.201.19:57:51.50#ibcon#about to read 4, iclass 25, count 0 2006.201.19:57:51.50#ibcon#read 4, iclass 25, count 0 2006.201.19:57:51.50#ibcon#about to read 5, iclass 25, count 0 2006.201.19:57:51.50#ibcon#read 5, iclass 25, count 0 2006.201.19:57:51.50#ibcon#about to read 6, iclass 25, count 0 2006.201.19:57:51.50#ibcon#read 6, iclass 25, count 0 2006.201.19:57:51.50#ibcon#end of sib2, iclass 25, count 0 2006.201.19:57:51.50#ibcon#*mode == 0, iclass 25, count 0 2006.201.19:57:51.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.19:57:51.50#ibcon#[27=USB\r\n] 2006.201.19:57:51.50#ibcon#*before write, iclass 25, count 0 2006.201.19:57:51.50#ibcon#enter sib2, iclass 25, count 0 2006.201.19:57:51.50#ibcon#flushed, iclass 25, count 0 2006.201.19:57:51.50#ibcon#about to write, iclass 25, count 0 2006.201.19:57:51.50#ibcon#wrote, iclass 25, count 0 2006.201.19:57:51.50#ibcon#about to read 3, iclass 25, count 0 2006.201.19:57:51.53#ibcon#read 3, iclass 25, count 0 2006.201.19:57:51.53#ibcon#about to read 4, iclass 25, count 0 2006.201.19:57:51.53#ibcon#read 4, iclass 25, count 0 2006.201.19:57:51.53#ibcon#about to read 5, iclass 25, count 0 2006.201.19:57:51.53#ibcon#read 5, iclass 25, count 0 2006.201.19:57:51.53#ibcon#about to read 6, iclass 25, count 0 2006.201.19:57:51.53#ibcon#read 6, iclass 25, count 0 2006.201.19:57:51.53#ibcon#end of sib2, iclass 25, count 0 2006.201.19:57:51.53#ibcon#*after write, iclass 25, count 0 2006.201.19:57:51.53#ibcon#*before return 0, iclass 25, count 0 2006.201.19:57:51.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:51.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.19:57:51.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.19:57:51.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.19:57:51.53$vck44/vblo=4,679.99 2006.201.19:57:51.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.19:57:51.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.19:57:51.53#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:51.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:51.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:51.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:51.53#ibcon#enter wrdev, iclass 27, count 0 2006.201.19:57:51.53#ibcon#first serial, iclass 27, count 0 2006.201.19:57:51.53#ibcon#enter sib2, iclass 27, count 0 2006.201.19:57:51.53#ibcon#flushed, iclass 27, count 0 2006.201.19:57:51.53#ibcon#about to write, iclass 27, count 0 2006.201.19:57:51.53#ibcon#wrote, iclass 27, count 0 2006.201.19:57:51.53#ibcon#about to read 3, iclass 27, count 0 2006.201.19:57:51.55#ibcon#read 3, iclass 27, count 0 2006.201.19:57:51.55#ibcon#about to read 4, iclass 27, count 0 2006.201.19:57:51.55#ibcon#read 4, iclass 27, count 0 2006.201.19:57:51.55#ibcon#about to read 5, iclass 27, count 0 2006.201.19:57:51.55#ibcon#read 5, iclass 27, count 0 2006.201.19:57:51.55#ibcon#about to read 6, iclass 27, count 0 2006.201.19:57:51.55#ibcon#read 6, iclass 27, count 0 2006.201.19:57:51.55#ibcon#end of sib2, iclass 27, count 0 2006.201.19:57:51.55#ibcon#*mode == 0, iclass 27, count 0 2006.201.19:57:51.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.19:57:51.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.19:57:51.55#ibcon#*before write, iclass 27, count 0 2006.201.19:57:51.55#ibcon#enter sib2, iclass 27, count 0 2006.201.19:57:51.55#ibcon#flushed, iclass 27, count 0 2006.201.19:57:51.55#ibcon#about to write, iclass 27, count 0 2006.201.19:57:51.55#ibcon#wrote, iclass 27, count 0 2006.201.19:57:51.55#ibcon#about to read 3, iclass 27, count 0 2006.201.19:57:51.60#ibcon#read 3, iclass 27, count 0 2006.201.19:57:51.60#ibcon#about to read 4, iclass 27, count 0 2006.201.19:57:51.60#ibcon#read 4, iclass 27, count 0 2006.201.19:57:51.60#ibcon#about to read 5, iclass 27, count 0 2006.201.19:57:51.60#ibcon#read 5, iclass 27, count 0 2006.201.19:57:51.60#ibcon#about to read 6, iclass 27, count 0 2006.201.19:57:51.60#ibcon#read 6, iclass 27, count 0 2006.201.19:57:51.60#ibcon#end of sib2, iclass 27, count 0 2006.201.19:57:51.60#ibcon#*after write, iclass 27, count 0 2006.201.19:57:51.60#ibcon#*before return 0, iclass 27, count 0 2006.201.19:57:51.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:51.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.19:57:51.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.19:57:51.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.19:57:51.60$vck44/vb=4,5 2006.201.19:57:51.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.19:57:51.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.19:57:51.60#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:51.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:51.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:51.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:51.65#ibcon#enter wrdev, iclass 29, count 2 2006.201.19:57:51.65#ibcon#first serial, iclass 29, count 2 2006.201.19:57:51.65#ibcon#enter sib2, iclass 29, count 2 2006.201.19:57:51.65#ibcon#flushed, iclass 29, count 2 2006.201.19:57:51.65#ibcon#about to write, iclass 29, count 2 2006.201.19:57:51.65#ibcon#wrote, iclass 29, count 2 2006.201.19:57:51.65#ibcon#about to read 3, iclass 29, count 2 2006.201.19:57:51.67#ibcon#read 3, iclass 29, count 2 2006.201.19:57:51.67#ibcon#about to read 4, iclass 29, count 2 2006.201.19:57:51.67#ibcon#read 4, iclass 29, count 2 2006.201.19:57:51.67#ibcon#about to read 5, iclass 29, count 2 2006.201.19:57:51.67#ibcon#read 5, iclass 29, count 2 2006.201.19:57:51.67#ibcon#about to read 6, iclass 29, count 2 2006.201.19:57:51.67#ibcon#read 6, iclass 29, count 2 2006.201.19:57:51.67#ibcon#end of sib2, iclass 29, count 2 2006.201.19:57:51.67#ibcon#*mode == 0, iclass 29, count 2 2006.201.19:57:51.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.19:57:51.67#ibcon#[27=AT04-05\r\n] 2006.201.19:57:51.67#ibcon#*before write, iclass 29, count 2 2006.201.19:57:51.67#ibcon#enter sib2, iclass 29, count 2 2006.201.19:57:51.67#ibcon#flushed, iclass 29, count 2 2006.201.19:57:51.67#ibcon#about to write, iclass 29, count 2 2006.201.19:57:51.67#ibcon#wrote, iclass 29, count 2 2006.201.19:57:51.67#ibcon#about to read 3, iclass 29, count 2 2006.201.19:57:51.70#ibcon#read 3, iclass 29, count 2 2006.201.19:57:51.70#ibcon#about to read 4, iclass 29, count 2 2006.201.19:57:51.70#ibcon#read 4, iclass 29, count 2 2006.201.19:57:51.70#ibcon#about to read 5, iclass 29, count 2 2006.201.19:57:51.70#ibcon#read 5, iclass 29, count 2 2006.201.19:57:51.70#ibcon#about to read 6, iclass 29, count 2 2006.201.19:57:51.70#ibcon#read 6, iclass 29, count 2 2006.201.19:57:51.70#ibcon#end of sib2, iclass 29, count 2 2006.201.19:57:51.70#ibcon#*after write, iclass 29, count 2 2006.201.19:57:51.70#ibcon#*before return 0, iclass 29, count 2 2006.201.19:57:51.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:51.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.19:57:51.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.19:57:51.70#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:51.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:51.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:51.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:51.82#ibcon#enter wrdev, iclass 29, count 0 2006.201.19:57:51.82#ibcon#first serial, iclass 29, count 0 2006.201.19:57:51.82#ibcon#enter sib2, iclass 29, count 0 2006.201.19:57:51.82#ibcon#flushed, iclass 29, count 0 2006.201.19:57:51.82#ibcon#about to write, iclass 29, count 0 2006.201.19:57:51.82#ibcon#wrote, iclass 29, count 0 2006.201.19:57:51.82#ibcon#about to read 3, iclass 29, count 0 2006.201.19:57:51.84#ibcon#read 3, iclass 29, count 0 2006.201.19:57:51.84#ibcon#about to read 4, iclass 29, count 0 2006.201.19:57:51.84#ibcon#read 4, iclass 29, count 0 2006.201.19:57:51.84#ibcon#about to read 5, iclass 29, count 0 2006.201.19:57:51.84#ibcon#read 5, iclass 29, count 0 2006.201.19:57:51.84#ibcon#about to read 6, iclass 29, count 0 2006.201.19:57:51.84#ibcon#read 6, iclass 29, count 0 2006.201.19:57:51.84#ibcon#end of sib2, iclass 29, count 0 2006.201.19:57:51.84#ibcon#*mode == 0, iclass 29, count 0 2006.201.19:57:51.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.19:57:51.84#ibcon#[27=USB\r\n] 2006.201.19:57:51.84#ibcon#*before write, iclass 29, count 0 2006.201.19:57:51.84#ibcon#enter sib2, iclass 29, count 0 2006.201.19:57:51.84#ibcon#flushed, iclass 29, count 0 2006.201.19:57:51.84#ibcon#about to write, iclass 29, count 0 2006.201.19:57:51.84#ibcon#wrote, iclass 29, count 0 2006.201.19:57:51.84#ibcon#about to read 3, iclass 29, count 0 2006.201.19:57:51.87#ibcon#read 3, iclass 29, count 0 2006.201.19:57:51.87#ibcon#about to read 4, iclass 29, count 0 2006.201.19:57:51.87#ibcon#read 4, iclass 29, count 0 2006.201.19:57:51.87#ibcon#about to read 5, iclass 29, count 0 2006.201.19:57:51.87#ibcon#read 5, iclass 29, count 0 2006.201.19:57:51.87#ibcon#about to read 6, iclass 29, count 0 2006.201.19:57:51.87#ibcon#read 6, iclass 29, count 0 2006.201.19:57:51.87#ibcon#end of sib2, iclass 29, count 0 2006.201.19:57:51.87#ibcon#*after write, iclass 29, count 0 2006.201.19:57:51.87#ibcon#*before return 0, iclass 29, count 0 2006.201.19:57:51.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:51.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.19:57:51.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.19:57:51.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.19:57:51.87$vck44/vblo=5,709.99 2006.201.19:57:51.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.19:57:51.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.19:57:51.87#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:51.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:51.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:51.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:51.87#ibcon#enter wrdev, iclass 31, count 0 2006.201.19:57:51.87#ibcon#first serial, iclass 31, count 0 2006.201.19:57:51.87#ibcon#enter sib2, iclass 31, count 0 2006.201.19:57:51.87#ibcon#flushed, iclass 31, count 0 2006.201.19:57:51.87#ibcon#about to write, iclass 31, count 0 2006.201.19:57:51.87#ibcon#wrote, iclass 31, count 0 2006.201.19:57:51.87#ibcon#about to read 3, iclass 31, count 0 2006.201.19:57:51.89#ibcon#read 3, iclass 31, count 0 2006.201.19:57:51.89#ibcon#about to read 4, iclass 31, count 0 2006.201.19:57:51.89#ibcon#read 4, iclass 31, count 0 2006.201.19:57:51.89#ibcon#about to read 5, iclass 31, count 0 2006.201.19:57:51.89#ibcon#read 5, iclass 31, count 0 2006.201.19:57:51.89#ibcon#about to read 6, iclass 31, count 0 2006.201.19:57:51.89#ibcon#read 6, iclass 31, count 0 2006.201.19:57:51.89#ibcon#end of sib2, iclass 31, count 0 2006.201.19:57:51.89#ibcon#*mode == 0, iclass 31, count 0 2006.201.19:57:51.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.19:57:51.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.19:57:51.89#ibcon#*before write, iclass 31, count 0 2006.201.19:57:51.89#ibcon#enter sib2, iclass 31, count 0 2006.201.19:57:51.89#ibcon#flushed, iclass 31, count 0 2006.201.19:57:51.89#ibcon#about to write, iclass 31, count 0 2006.201.19:57:51.89#ibcon#wrote, iclass 31, count 0 2006.201.19:57:51.89#ibcon#about to read 3, iclass 31, count 0 2006.201.19:57:51.94#ibcon#read 3, iclass 31, count 0 2006.201.19:57:51.94#ibcon#about to read 4, iclass 31, count 0 2006.201.19:57:51.94#ibcon#read 4, iclass 31, count 0 2006.201.19:57:51.94#ibcon#about to read 5, iclass 31, count 0 2006.201.19:57:51.94#ibcon#read 5, iclass 31, count 0 2006.201.19:57:51.94#ibcon#about to read 6, iclass 31, count 0 2006.201.19:57:51.94#ibcon#read 6, iclass 31, count 0 2006.201.19:57:51.94#ibcon#end of sib2, iclass 31, count 0 2006.201.19:57:51.94#ibcon#*after write, iclass 31, count 0 2006.201.19:57:51.94#ibcon#*before return 0, iclass 31, count 0 2006.201.19:57:51.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:51.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.19:57:51.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.19:57:51.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.19:57:51.94$vck44/vb=5,4 2006.201.19:57:51.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.19:57:51.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.19:57:51.94#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:51.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:51.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:51.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:51.99#ibcon#enter wrdev, iclass 33, count 2 2006.201.19:57:51.99#ibcon#first serial, iclass 33, count 2 2006.201.19:57:51.99#ibcon#enter sib2, iclass 33, count 2 2006.201.19:57:51.99#ibcon#flushed, iclass 33, count 2 2006.201.19:57:51.99#ibcon#about to write, iclass 33, count 2 2006.201.19:57:51.99#ibcon#wrote, iclass 33, count 2 2006.201.19:57:51.99#ibcon#about to read 3, iclass 33, count 2 2006.201.19:57:52.01#ibcon#read 3, iclass 33, count 2 2006.201.19:57:52.01#ibcon#about to read 4, iclass 33, count 2 2006.201.19:57:52.01#ibcon#read 4, iclass 33, count 2 2006.201.19:57:52.01#ibcon#about to read 5, iclass 33, count 2 2006.201.19:57:52.01#ibcon#read 5, iclass 33, count 2 2006.201.19:57:52.01#ibcon#about to read 6, iclass 33, count 2 2006.201.19:57:52.01#ibcon#read 6, iclass 33, count 2 2006.201.19:57:52.01#ibcon#end of sib2, iclass 33, count 2 2006.201.19:57:52.01#ibcon#*mode == 0, iclass 33, count 2 2006.201.19:57:52.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.19:57:52.01#ibcon#[27=AT05-04\r\n] 2006.201.19:57:52.01#ibcon#*before write, iclass 33, count 2 2006.201.19:57:52.01#ibcon#enter sib2, iclass 33, count 2 2006.201.19:57:52.01#ibcon#flushed, iclass 33, count 2 2006.201.19:57:52.01#ibcon#about to write, iclass 33, count 2 2006.201.19:57:52.01#ibcon#wrote, iclass 33, count 2 2006.201.19:57:52.01#ibcon#about to read 3, iclass 33, count 2 2006.201.19:57:52.04#ibcon#read 3, iclass 33, count 2 2006.201.19:57:52.04#ibcon#about to read 4, iclass 33, count 2 2006.201.19:57:52.04#ibcon#read 4, iclass 33, count 2 2006.201.19:57:52.04#ibcon#about to read 5, iclass 33, count 2 2006.201.19:57:52.04#ibcon#read 5, iclass 33, count 2 2006.201.19:57:52.04#ibcon#about to read 6, iclass 33, count 2 2006.201.19:57:52.04#ibcon#read 6, iclass 33, count 2 2006.201.19:57:52.04#ibcon#end of sib2, iclass 33, count 2 2006.201.19:57:52.04#ibcon#*after write, iclass 33, count 2 2006.201.19:57:52.04#ibcon#*before return 0, iclass 33, count 2 2006.201.19:57:52.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:52.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.19:57:52.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.19:57:52.04#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:52.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:52.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:52.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:52.16#ibcon#enter wrdev, iclass 33, count 0 2006.201.19:57:52.16#ibcon#first serial, iclass 33, count 0 2006.201.19:57:52.16#ibcon#enter sib2, iclass 33, count 0 2006.201.19:57:52.16#ibcon#flushed, iclass 33, count 0 2006.201.19:57:52.16#ibcon#about to write, iclass 33, count 0 2006.201.19:57:52.16#ibcon#wrote, iclass 33, count 0 2006.201.19:57:52.16#ibcon#about to read 3, iclass 33, count 0 2006.201.19:57:52.18#ibcon#read 3, iclass 33, count 0 2006.201.19:57:52.18#ibcon#about to read 4, iclass 33, count 0 2006.201.19:57:52.18#ibcon#read 4, iclass 33, count 0 2006.201.19:57:52.18#ibcon#about to read 5, iclass 33, count 0 2006.201.19:57:52.18#ibcon#read 5, iclass 33, count 0 2006.201.19:57:52.18#ibcon#about to read 6, iclass 33, count 0 2006.201.19:57:52.18#ibcon#read 6, iclass 33, count 0 2006.201.19:57:52.18#ibcon#end of sib2, iclass 33, count 0 2006.201.19:57:52.18#ibcon#*mode == 0, iclass 33, count 0 2006.201.19:57:52.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.19:57:52.18#ibcon#[27=USB\r\n] 2006.201.19:57:52.18#ibcon#*before write, iclass 33, count 0 2006.201.19:57:52.18#ibcon#enter sib2, iclass 33, count 0 2006.201.19:57:52.18#ibcon#flushed, iclass 33, count 0 2006.201.19:57:52.18#ibcon#about to write, iclass 33, count 0 2006.201.19:57:52.18#ibcon#wrote, iclass 33, count 0 2006.201.19:57:52.18#ibcon#about to read 3, iclass 33, count 0 2006.201.19:57:52.21#ibcon#read 3, iclass 33, count 0 2006.201.19:57:52.21#ibcon#about to read 4, iclass 33, count 0 2006.201.19:57:52.21#ibcon#read 4, iclass 33, count 0 2006.201.19:57:52.21#ibcon#about to read 5, iclass 33, count 0 2006.201.19:57:52.21#ibcon#read 5, iclass 33, count 0 2006.201.19:57:52.21#ibcon#about to read 6, iclass 33, count 0 2006.201.19:57:52.21#ibcon#read 6, iclass 33, count 0 2006.201.19:57:52.21#ibcon#end of sib2, iclass 33, count 0 2006.201.19:57:52.21#ibcon#*after write, iclass 33, count 0 2006.201.19:57:52.21#ibcon#*before return 0, iclass 33, count 0 2006.201.19:57:52.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:52.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.19:57:52.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.19:57:52.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.19:57:52.21$vck44/vblo=6,719.99 2006.201.19:57:52.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.19:57:52.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.19:57:52.21#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:52.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:52.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:52.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:52.21#ibcon#enter wrdev, iclass 35, count 0 2006.201.19:57:52.21#ibcon#first serial, iclass 35, count 0 2006.201.19:57:52.21#ibcon#enter sib2, iclass 35, count 0 2006.201.19:57:52.21#ibcon#flushed, iclass 35, count 0 2006.201.19:57:52.21#ibcon#about to write, iclass 35, count 0 2006.201.19:57:52.21#ibcon#wrote, iclass 35, count 0 2006.201.19:57:52.21#ibcon#about to read 3, iclass 35, count 0 2006.201.19:57:52.23#ibcon#read 3, iclass 35, count 0 2006.201.19:57:52.23#ibcon#about to read 4, iclass 35, count 0 2006.201.19:57:52.23#ibcon#read 4, iclass 35, count 0 2006.201.19:57:52.23#ibcon#about to read 5, iclass 35, count 0 2006.201.19:57:52.23#ibcon#read 5, iclass 35, count 0 2006.201.19:57:52.23#ibcon#about to read 6, iclass 35, count 0 2006.201.19:57:52.23#ibcon#read 6, iclass 35, count 0 2006.201.19:57:52.23#ibcon#end of sib2, iclass 35, count 0 2006.201.19:57:52.23#ibcon#*mode == 0, iclass 35, count 0 2006.201.19:57:52.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.19:57:52.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.19:57:52.23#ibcon#*before write, iclass 35, count 0 2006.201.19:57:52.23#ibcon#enter sib2, iclass 35, count 0 2006.201.19:57:52.23#ibcon#flushed, iclass 35, count 0 2006.201.19:57:52.23#ibcon#about to write, iclass 35, count 0 2006.201.19:57:52.23#ibcon#wrote, iclass 35, count 0 2006.201.19:57:52.23#ibcon#about to read 3, iclass 35, count 0 2006.201.19:57:52.27#ibcon#read 3, iclass 35, count 0 2006.201.19:57:52.27#ibcon#about to read 4, iclass 35, count 0 2006.201.19:57:52.27#ibcon#read 4, iclass 35, count 0 2006.201.19:57:52.27#ibcon#about to read 5, iclass 35, count 0 2006.201.19:57:52.27#ibcon#read 5, iclass 35, count 0 2006.201.19:57:52.27#ibcon#about to read 6, iclass 35, count 0 2006.201.19:57:52.27#ibcon#read 6, iclass 35, count 0 2006.201.19:57:52.27#ibcon#end of sib2, iclass 35, count 0 2006.201.19:57:52.27#ibcon#*after write, iclass 35, count 0 2006.201.19:57:52.27#ibcon#*before return 0, iclass 35, count 0 2006.201.19:57:52.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:52.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.19:57:52.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.19:57:52.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.19:57:52.27$vck44/vb=6,4 2006.201.19:57:52.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.19:57:52.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.19:57:52.27#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:52.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:52.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:52.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:52.33#ibcon#enter wrdev, iclass 37, count 2 2006.201.19:57:52.33#ibcon#first serial, iclass 37, count 2 2006.201.19:57:52.33#ibcon#enter sib2, iclass 37, count 2 2006.201.19:57:52.33#ibcon#flushed, iclass 37, count 2 2006.201.19:57:52.33#ibcon#about to write, iclass 37, count 2 2006.201.19:57:52.33#ibcon#wrote, iclass 37, count 2 2006.201.19:57:52.33#ibcon#about to read 3, iclass 37, count 2 2006.201.19:57:52.35#ibcon#read 3, iclass 37, count 2 2006.201.19:57:52.35#ibcon#about to read 4, iclass 37, count 2 2006.201.19:57:52.35#ibcon#read 4, iclass 37, count 2 2006.201.19:57:52.35#ibcon#about to read 5, iclass 37, count 2 2006.201.19:57:52.35#ibcon#read 5, iclass 37, count 2 2006.201.19:57:52.35#ibcon#about to read 6, iclass 37, count 2 2006.201.19:57:52.35#ibcon#read 6, iclass 37, count 2 2006.201.19:57:52.35#ibcon#end of sib2, iclass 37, count 2 2006.201.19:57:52.35#ibcon#*mode == 0, iclass 37, count 2 2006.201.19:57:52.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.19:57:52.35#ibcon#[27=AT06-04\r\n] 2006.201.19:57:52.35#ibcon#*before write, iclass 37, count 2 2006.201.19:57:52.35#ibcon#enter sib2, iclass 37, count 2 2006.201.19:57:52.35#ibcon#flushed, iclass 37, count 2 2006.201.19:57:52.35#ibcon#about to write, iclass 37, count 2 2006.201.19:57:52.35#ibcon#wrote, iclass 37, count 2 2006.201.19:57:52.35#ibcon#about to read 3, iclass 37, count 2 2006.201.19:57:52.38#ibcon#read 3, iclass 37, count 2 2006.201.19:57:52.38#ibcon#about to read 4, iclass 37, count 2 2006.201.19:57:52.38#ibcon#read 4, iclass 37, count 2 2006.201.19:57:52.38#ibcon#about to read 5, iclass 37, count 2 2006.201.19:57:52.38#ibcon#read 5, iclass 37, count 2 2006.201.19:57:52.38#ibcon#about to read 6, iclass 37, count 2 2006.201.19:57:52.38#ibcon#read 6, iclass 37, count 2 2006.201.19:57:52.38#ibcon#end of sib2, iclass 37, count 2 2006.201.19:57:52.38#ibcon#*after write, iclass 37, count 2 2006.201.19:57:52.38#ibcon#*before return 0, iclass 37, count 2 2006.201.19:57:52.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:52.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.19:57:52.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.19:57:52.38#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:52.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:52.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:52.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:52.50#ibcon#enter wrdev, iclass 37, count 0 2006.201.19:57:52.50#ibcon#first serial, iclass 37, count 0 2006.201.19:57:52.50#ibcon#enter sib2, iclass 37, count 0 2006.201.19:57:52.50#ibcon#flushed, iclass 37, count 0 2006.201.19:57:52.50#ibcon#about to write, iclass 37, count 0 2006.201.19:57:52.50#ibcon#wrote, iclass 37, count 0 2006.201.19:57:52.50#ibcon#about to read 3, iclass 37, count 0 2006.201.19:57:52.52#ibcon#read 3, iclass 37, count 0 2006.201.19:57:52.52#ibcon#about to read 4, iclass 37, count 0 2006.201.19:57:52.52#ibcon#read 4, iclass 37, count 0 2006.201.19:57:52.52#ibcon#about to read 5, iclass 37, count 0 2006.201.19:57:52.52#ibcon#read 5, iclass 37, count 0 2006.201.19:57:52.52#ibcon#about to read 6, iclass 37, count 0 2006.201.19:57:52.52#ibcon#read 6, iclass 37, count 0 2006.201.19:57:52.52#ibcon#end of sib2, iclass 37, count 0 2006.201.19:57:52.52#ibcon#*mode == 0, iclass 37, count 0 2006.201.19:57:52.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.19:57:52.52#ibcon#[27=USB\r\n] 2006.201.19:57:52.52#ibcon#*before write, iclass 37, count 0 2006.201.19:57:52.52#ibcon#enter sib2, iclass 37, count 0 2006.201.19:57:52.52#ibcon#flushed, iclass 37, count 0 2006.201.19:57:52.52#ibcon#about to write, iclass 37, count 0 2006.201.19:57:52.52#ibcon#wrote, iclass 37, count 0 2006.201.19:57:52.52#ibcon#about to read 3, iclass 37, count 0 2006.201.19:57:52.55#ibcon#read 3, iclass 37, count 0 2006.201.19:57:52.55#ibcon#about to read 4, iclass 37, count 0 2006.201.19:57:52.55#ibcon#read 4, iclass 37, count 0 2006.201.19:57:52.55#ibcon#about to read 5, iclass 37, count 0 2006.201.19:57:52.55#ibcon#read 5, iclass 37, count 0 2006.201.19:57:52.55#ibcon#about to read 6, iclass 37, count 0 2006.201.19:57:52.55#ibcon#read 6, iclass 37, count 0 2006.201.19:57:52.55#ibcon#end of sib2, iclass 37, count 0 2006.201.19:57:52.55#ibcon#*after write, iclass 37, count 0 2006.201.19:57:52.55#ibcon#*before return 0, iclass 37, count 0 2006.201.19:57:52.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:52.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.19:57:52.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.19:57:52.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.19:57:52.55$vck44/vblo=7,734.99 2006.201.19:57:52.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.19:57:52.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.19:57:52.55#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:52.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:52.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:52.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:52.55#ibcon#enter wrdev, iclass 39, count 0 2006.201.19:57:52.55#ibcon#first serial, iclass 39, count 0 2006.201.19:57:52.55#ibcon#enter sib2, iclass 39, count 0 2006.201.19:57:52.55#ibcon#flushed, iclass 39, count 0 2006.201.19:57:52.55#ibcon#about to write, iclass 39, count 0 2006.201.19:57:52.55#ibcon#wrote, iclass 39, count 0 2006.201.19:57:52.55#ibcon#about to read 3, iclass 39, count 0 2006.201.19:57:52.57#ibcon#read 3, iclass 39, count 0 2006.201.19:57:52.57#ibcon#about to read 4, iclass 39, count 0 2006.201.19:57:52.57#ibcon#read 4, iclass 39, count 0 2006.201.19:57:52.57#ibcon#about to read 5, iclass 39, count 0 2006.201.19:57:52.57#ibcon#read 5, iclass 39, count 0 2006.201.19:57:52.57#ibcon#about to read 6, iclass 39, count 0 2006.201.19:57:52.57#ibcon#read 6, iclass 39, count 0 2006.201.19:57:52.57#ibcon#end of sib2, iclass 39, count 0 2006.201.19:57:52.57#ibcon#*mode == 0, iclass 39, count 0 2006.201.19:57:52.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.19:57:52.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.19:57:52.57#ibcon#*before write, iclass 39, count 0 2006.201.19:57:52.57#ibcon#enter sib2, iclass 39, count 0 2006.201.19:57:52.57#ibcon#flushed, iclass 39, count 0 2006.201.19:57:52.57#ibcon#about to write, iclass 39, count 0 2006.201.19:57:52.57#ibcon#wrote, iclass 39, count 0 2006.201.19:57:52.57#ibcon#about to read 3, iclass 39, count 0 2006.201.19:57:52.62#ibcon#read 3, iclass 39, count 0 2006.201.19:57:52.62#ibcon#about to read 4, iclass 39, count 0 2006.201.19:57:52.62#ibcon#read 4, iclass 39, count 0 2006.201.19:57:52.62#ibcon#about to read 5, iclass 39, count 0 2006.201.19:57:52.62#ibcon#read 5, iclass 39, count 0 2006.201.19:57:52.62#ibcon#about to read 6, iclass 39, count 0 2006.201.19:57:52.62#ibcon#read 6, iclass 39, count 0 2006.201.19:57:52.62#ibcon#end of sib2, iclass 39, count 0 2006.201.19:57:52.62#ibcon#*after write, iclass 39, count 0 2006.201.19:57:52.62#ibcon#*before return 0, iclass 39, count 0 2006.201.19:57:52.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:52.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.19:57:52.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.19:57:52.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.19:57:52.62$vck44/vb=7,4 2006.201.19:57:52.62#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.19:57:52.62#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.19:57:52.62#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:52.62#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:52.67#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:52.67#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:52.67#ibcon#enter wrdev, iclass 2, count 2 2006.201.19:57:52.67#ibcon#first serial, iclass 2, count 2 2006.201.19:57:52.67#ibcon#enter sib2, iclass 2, count 2 2006.201.19:57:52.67#ibcon#flushed, iclass 2, count 2 2006.201.19:57:52.67#ibcon#about to write, iclass 2, count 2 2006.201.19:57:52.67#ibcon#wrote, iclass 2, count 2 2006.201.19:57:52.67#ibcon#about to read 3, iclass 2, count 2 2006.201.19:57:52.69#ibcon#read 3, iclass 2, count 2 2006.201.19:57:52.69#ibcon#about to read 4, iclass 2, count 2 2006.201.19:57:52.69#ibcon#read 4, iclass 2, count 2 2006.201.19:57:52.69#ibcon#about to read 5, iclass 2, count 2 2006.201.19:57:52.69#ibcon#read 5, iclass 2, count 2 2006.201.19:57:52.69#ibcon#about to read 6, iclass 2, count 2 2006.201.19:57:52.69#ibcon#read 6, iclass 2, count 2 2006.201.19:57:52.69#ibcon#end of sib2, iclass 2, count 2 2006.201.19:57:52.69#ibcon#*mode == 0, iclass 2, count 2 2006.201.19:57:52.69#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.19:57:52.69#ibcon#[27=AT07-04\r\n] 2006.201.19:57:52.69#ibcon#*before write, iclass 2, count 2 2006.201.19:57:52.69#ibcon#enter sib2, iclass 2, count 2 2006.201.19:57:52.69#ibcon#flushed, iclass 2, count 2 2006.201.19:57:52.69#ibcon#about to write, iclass 2, count 2 2006.201.19:57:52.69#ibcon#wrote, iclass 2, count 2 2006.201.19:57:52.69#ibcon#about to read 3, iclass 2, count 2 2006.201.19:57:52.72#ibcon#read 3, iclass 2, count 2 2006.201.19:57:52.72#ibcon#about to read 4, iclass 2, count 2 2006.201.19:57:52.72#ibcon#read 4, iclass 2, count 2 2006.201.19:57:52.72#ibcon#about to read 5, iclass 2, count 2 2006.201.19:57:52.72#ibcon#read 5, iclass 2, count 2 2006.201.19:57:52.72#ibcon#about to read 6, iclass 2, count 2 2006.201.19:57:52.72#ibcon#read 6, iclass 2, count 2 2006.201.19:57:52.72#ibcon#end of sib2, iclass 2, count 2 2006.201.19:57:52.72#ibcon#*after write, iclass 2, count 2 2006.201.19:57:52.72#ibcon#*before return 0, iclass 2, count 2 2006.201.19:57:52.72#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:52.72#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.19:57:52.72#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.19:57:52.72#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:52.72#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:52.84#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:52.84#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:52.84#ibcon#enter wrdev, iclass 2, count 0 2006.201.19:57:52.84#ibcon#first serial, iclass 2, count 0 2006.201.19:57:52.84#ibcon#enter sib2, iclass 2, count 0 2006.201.19:57:52.84#ibcon#flushed, iclass 2, count 0 2006.201.19:57:52.84#ibcon#about to write, iclass 2, count 0 2006.201.19:57:52.84#ibcon#wrote, iclass 2, count 0 2006.201.19:57:52.84#ibcon#about to read 3, iclass 2, count 0 2006.201.19:57:52.86#ibcon#read 3, iclass 2, count 0 2006.201.19:57:52.86#ibcon#about to read 4, iclass 2, count 0 2006.201.19:57:52.86#ibcon#read 4, iclass 2, count 0 2006.201.19:57:52.86#ibcon#about to read 5, iclass 2, count 0 2006.201.19:57:52.86#ibcon#read 5, iclass 2, count 0 2006.201.19:57:52.86#ibcon#about to read 6, iclass 2, count 0 2006.201.19:57:52.86#ibcon#read 6, iclass 2, count 0 2006.201.19:57:52.86#ibcon#end of sib2, iclass 2, count 0 2006.201.19:57:52.86#ibcon#*mode == 0, iclass 2, count 0 2006.201.19:57:52.86#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.19:57:52.86#ibcon#[27=USB\r\n] 2006.201.19:57:52.86#ibcon#*before write, iclass 2, count 0 2006.201.19:57:52.86#ibcon#enter sib2, iclass 2, count 0 2006.201.19:57:52.86#ibcon#flushed, iclass 2, count 0 2006.201.19:57:52.86#ibcon#about to write, iclass 2, count 0 2006.201.19:57:52.86#ibcon#wrote, iclass 2, count 0 2006.201.19:57:52.86#ibcon#about to read 3, iclass 2, count 0 2006.201.19:57:52.89#ibcon#read 3, iclass 2, count 0 2006.201.19:57:52.89#ibcon#about to read 4, iclass 2, count 0 2006.201.19:57:52.89#ibcon#read 4, iclass 2, count 0 2006.201.19:57:52.89#ibcon#about to read 5, iclass 2, count 0 2006.201.19:57:52.89#ibcon#read 5, iclass 2, count 0 2006.201.19:57:52.89#ibcon#about to read 6, iclass 2, count 0 2006.201.19:57:52.89#ibcon#read 6, iclass 2, count 0 2006.201.19:57:52.89#ibcon#end of sib2, iclass 2, count 0 2006.201.19:57:52.89#ibcon#*after write, iclass 2, count 0 2006.201.19:57:52.89#ibcon#*before return 0, iclass 2, count 0 2006.201.19:57:52.89#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:52.89#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.19:57:52.89#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.19:57:52.89#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.19:57:52.89$vck44/vblo=8,744.99 2006.201.19:57:52.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.19:57:52.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.19:57:52.89#ibcon#ireg 17 cls_cnt 0 2006.201.19:57:52.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:52.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:52.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:52.89#ibcon#enter wrdev, iclass 5, count 0 2006.201.19:57:52.89#ibcon#first serial, iclass 5, count 0 2006.201.19:57:52.89#ibcon#enter sib2, iclass 5, count 0 2006.201.19:57:52.89#ibcon#flushed, iclass 5, count 0 2006.201.19:57:52.89#ibcon#about to write, iclass 5, count 0 2006.201.19:57:52.89#ibcon#wrote, iclass 5, count 0 2006.201.19:57:52.89#ibcon#about to read 3, iclass 5, count 0 2006.201.19:57:52.91#ibcon#read 3, iclass 5, count 0 2006.201.19:57:52.91#ibcon#about to read 4, iclass 5, count 0 2006.201.19:57:52.91#ibcon#read 4, iclass 5, count 0 2006.201.19:57:52.91#ibcon#about to read 5, iclass 5, count 0 2006.201.19:57:52.91#ibcon#read 5, iclass 5, count 0 2006.201.19:57:52.91#ibcon#about to read 6, iclass 5, count 0 2006.201.19:57:52.91#ibcon#read 6, iclass 5, count 0 2006.201.19:57:52.91#ibcon#end of sib2, iclass 5, count 0 2006.201.19:57:52.91#ibcon#*mode == 0, iclass 5, count 0 2006.201.19:57:52.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.19:57:52.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.19:57:52.91#ibcon#*before write, iclass 5, count 0 2006.201.19:57:52.91#ibcon#enter sib2, iclass 5, count 0 2006.201.19:57:52.91#ibcon#flushed, iclass 5, count 0 2006.201.19:57:52.91#ibcon#about to write, iclass 5, count 0 2006.201.19:57:52.91#ibcon#wrote, iclass 5, count 0 2006.201.19:57:52.91#ibcon#about to read 3, iclass 5, count 0 2006.201.19:57:52.95#ibcon#read 3, iclass 5, count 0 2006.201.19:57:52.95#ibcon#about to read 4, iclass 5, count 0 2006.201.19:57:52.95#ibcon#read 4, iclass 5, count 0 2006.201.19:57:52.95#ibcon#about to read 5, iclass 5, count 0 2006.201.19:57:52.95#ibcon#read 5, iclass 5, count 0 2006.201.19:57:52.95#ibcon#about to read 6, iclass 5, count 0 2006.201.19:57:52.95#ibcon#read 6, iclass 5, count 0 2006.201.19:57:52.95#ibcon#end of sib2, iclass 5, count 0 2006.201.19:57:52.95#ibcon#*after write, iclass 5, count 0 2006.201.19:57:52.95#ibcon#*before return 0, iclass 5, count 0 2006.201.19:57:52.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:52.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.19:57:52.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.19:57:52.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.19:57:52.95$vck44/vb=8,4 2006.201.19:57:52.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.19:57:52.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.19:57:52.95#ibcon#ireg 11 cls_cnt 2 2006.201.19:57:52.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:53.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:53.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:53.01#ibcon#enter wrdev, iclass 7, count 2 2006.201.19:57:53.01#ibcon#first serial, iclass 7, count 2 2006.201.19:57:53.01#ibcon#enter sib2, iclass 7, count 2 2006.201.19:57:53.01#ibcon#flushed, iclass 7, count 2 2006.201.19:57:53.01#ibcon#about to write, iclass 7, count 2 2006.201.19:57:53.01#ibcon#wrote, iclass 7, count 2 2006.201.19:57:53.01#ibcon#about to read 3, iclass 7, count 2 2006.201.19:57:53.03#ibcon#read 3, iclass 7, count 2 2006.201.19:57:53.03#ibcon#about to read 4, iclass 7, count 2 2006.201.19:57:53.03#ibcon#read 4, iclass 7, count 2 2006.201.19:57:53.03#ibcon#about to read 5, iclass 7, count 2 2006.201.19:57:53.03#ibcon#read 5, iclass 7, count 2 2006.201.19:57:53.03#ibcon#about to read 6, iclass 7, count 2 2006.201.19:57:53.03#ibcon#read 6, iclass 7, count 2 2006.201.19:57:53.03#ibcon#end of sib2, iclass 7, count 2 2006.201.19:57:53.03#ibcon#*mode == 0, iclass 7, count 2 2006.201.19:57:53.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.19:57:53.03#ibcon#[27=AT08-04\r\n] 2006.201.19:57:53.03#ibcon#*before write, iclass 7, count 2 2006.201.19:57:53.03#ibcon#enter sib2, iclass 7, count 2 2006.201.19:57:53.03#ibcon#flushed, iclass 7, count 2 2006.201.19:57:53.03#ibcon#about to write, iclass 7, count 2 2006.201.19:57:53.03#ibcon#wrote, iclass 7, count 2 2006.201.19:57:53.03#ibcon#about to read 3, iclass 7, count 2 2006.201.19:57:53.06#ibcon#read 3, iclass 7, count 2 2006.201.19:57:53.06#ibcon#about to read 4, iclass 7, count 2 2006.201.19:57:53.06#ibcon#read 4, iclass 7, count 2 2006.201.19:57:53.06#ibcon#about to read 5, iclass 7, count 2 2006.201.19:57:53.06#ibcon#read 5, iclass 7, count 2 2006.201.19:57:53.06#ibcon#about to read 6, iclass 7, count 2 2006.201.19:57:53.06#ibcon#read 6, iclass 7, count 2 2006.201.19:57:53.06#ibcon#end of sib2, iclass 7, count 2 2006.201.19:57:53.06#ibcon#*after write, iclass 7, count 2 2006.201.19:57:53.06#ibcon#*before return 0, iclass 7, count 2 2006.201.19:57:53.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:53.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.19:57:53.06#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.19:57:53.06#ibcon#ireg 7 cls_cnt 0 2006.201.19:57:53.06#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:53.18#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:53.18#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:53.18#ibcon#enter wrdev, iclass 7, count 0 2006.201.19:57:53.18#ibcon#first serial, iclass 7, count 0 2006.201.19:57:53.18#ibcon#enter sib2, iclass 7, count 0 2006.201.19:57:53.18#ibcon#flushed, iclass 7, count 0 2006.201.19:57:53.18#ibcon#about to write, iclass 7, count 0 2006.201.19:57:53.18#ibcon#wrote, iclass 7, count 0 2006.201.19:57:53.18#ibcon#about to read 3, iclass 7, count 0 2006.201.19:57:53.20#ibcon#read 3, iclass 7, count 0 2006.201.19:57:53.20#ibcon#about to read 4, iclass 7, count 0 2006.201.19:57:53.20#ibcon#read 4, iclass 7, count 0 2006.201.19:57:53.20#ibcon#about to read 5, iclass 7, count 0 2006.201.19:57:53.20#ibcon#read 5, iclass 7, count 0 2006.201.19:57:53.20#ibcon#about to read 6, iclass 7, count 0 2006.201.19:57:53.20#ibcon#read 6, iclass 7, count 0 2006.201.19:57:53.20#ibcon#end of sib2, iclass 7, count 0 2006.201.19:57:53.20#ibcon#*mode == 0, iclass 7, count 0 2006.201.19:57:53.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.19:57:53.20#ibcon#[27=USB\r\n] 2006.201.19:57:53.20#ibcon#*before write, iclass 7, count 0 2006.201.19:57:53.20#ibcon#enter sib2, iclass 7, count 0 2006.201.19:57:53.20#ibcon#flushed, iclass 7, count 0 2006.201.19:57:53.20#ibcon#about to write, iclass 7, count 0 2006.201.19:57:53.20#ibcon#wrote, iclass 7, count 0 2006.201.19:57:53.20#ibcon#about to read 3, iclass 7, count 0 2006.201.19:57:53.23#ibcon#read 3, iclass 7, count 0 2006.201.19:57:53.23#ibcon#about to read 4, iclass 7, count 0 2006.201.19:57:53.23#ibcon#read 4, iclass 7, count 0 2006.201.19:57:53.23#ibcon#about to read 5, iclass 7, count 0 2006.201.19:57:53.23#ibcon#read 5, iclass 7, count 0 2006.201.19:57:53.23#ibcon#about to read 6, iclass 7, count 0 2006.201.19:57:53.23#ibcon#read 6, iclass 7, count 0 2006.201.19:57:53.23#ibcon#end of sib2, iclass 7, count 0 2006.201.19:57:53.23#ibcon#*after write, iclass 7, count 0 2006.201.19:57:53.23#ibcon#*before return 0, iclass 7, count 0 2006.201.19:57:53.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:53.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.19:57:53.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.19:57:53.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.19:57:53.23$vck44/vabw=wide 2006.201.19:57:53.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.19:57:53.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.19:57:53.23#ibcon#ireg 8 cls_cnt 0 2006.201.19:57:53.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:53.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:53.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:53.23#ibcon#enter wrdev, iclass 11, count 0 2006.201.19:57:53.23#ibcon#first serial, iclass 11, count 0 2006.201.19:57:53.23#ibcon#enter sib2, iclass 11, count 0 2006.201.19:57:53.23#ibcon#flushed, iclass 11, count 0 2006.201.19:57:53.23#ibcon#about to write, iclass 11, count 0 2006.201.19:57:53.23#ibcon#wrote, iclass 11, count 0 2006.201.19:57:53.23#ibcon#about to read 3, iclass 11, count 0 2006.201.19:57:53.25#ibcon#read 3, iclass 11, count 0 2006.201.19:57:53.25#ibcon#about to read 4, iclass 11, count 0 2006.201.19:57:53.25#ibcon#read 4, iclass 11, count 0 2006.201.19:57:53.25#ibcon#about to read 5, iclass 11, count 0 2006.201.19:57:53.25#ibcon#read 5, iclass 11, count 0 2006.201.19:57:53.25#ibcon#about to read 6, iclass 11, count 0 2006.201.19:57:53.25#ibcon#read 6, iclass 11, count 0 2006.201.19:57:53.25#ibcon#end of sib2, iclass 11, count 0 2006.201.19:57:53.25#ibcon#*mode == 0, iclass 11, count 0 2006.201.19:57:53.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.19:57:53.25#ibcon#[25=BW32\r\n] 2006.201.19:57:53.25#ibcon#*before write, iclass 11, count 0 2006.201.19:57:53.25#ibcon#enter sib2, iclass 11, count 0 2006.201.19:57:53.25#ibcon#flushed, iclass 11, count 0 2006.201.19:57:53.25#ibcon#about to write, iclass 11, count 0 2006.201.19:57:53.25#ibcon#wrote, iclass 11, count 0 2006.201.19:57:53.25#ibcon#about to read 3, iclass 11, count 0 2006.201.19:57:53.28#ibcon#read 3, iclass 11, count 0 2006.201.19:57:53.28#ibcon#about to read 4, iclass 11, count 0 2006.201.19:57:53.28#ibcon#read 4, iclass 11, count 0 2006.201.19:57:53.28#ibcon#about to read 5, iclass 11, count 0 2006.201.19:57:53.28#ibcon#read 5, iclass 11, count 0 2006.201.19:57:53.28#ibcon#about to read 6, iclass 11, count 0 2006.201.19:57:53.28#ibcon#read 6, iclass 11, count 0 2006.201.19:57:53.28#ibcon#end of sib2, iclass 11, count 0 2006.201.19:57:53.28#ibcon#*after write, iclass 11, count 0 2006.201.19:57:53.28#ibcon#*before return 0, iclass 11, count 0 2006.201.19:57:53.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:53.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.19:57:53.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.19:57:53.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.19:57:53.28$vck44/vbbw=wide 2006.201.19:57:53.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.19:57:53.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.19:57:53.28#ibcon#ireg 8 cls_cnt 0 2006.201.19:57:53.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:57:53.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:57:53.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:57:53.35#ibcon#enter wrdev, iclass 13, count 0 2006.201.19:57:53.35#ibcon#first serial, iclass 13, count 0 2006.201.19:57:53.35#ibcon#enter sib2, iclass 13, count 0 2006.201.19:57:53.35#ibcon#flushed, iclass 13, count 0 2006.201.19:57:53.35#ibcon#about to write, iclass 13, count 0 2006.201.19:57:53.35#ibcon#wrote, iclass 13, count 0 2006.201.19:57:53.35#ibcon#about to read 3, iclass 13, count 0 2006.201.19:57:53.37#ibcon#read 3, iclass 13, count 0 2006.201.19:57:53.37#ibcon#about to read 4, iclass 13, count 0 2006.201.19:57:53.37#ibcon#read 4, iclass 13, count 0 2006.201.19:57:53.37#ibcon#about to read 5, iclass 13, count 0 2006.201.19:57:53.37#ibcon#read 5, iclass 13, count 0 2006.201.19:57:53.37#ibcon#about to read 6, iclass 13, count 0 2006.201.19:57:53.37#ibcon#read 6, iclass 13, count 0 2006.201.19:57:53.37#ibcon#end of sib2, iclass 13, count 0 2006.201.19:57:53.37#ibcon#*mode == 0, iclass 13, count 0 2006.201.19:57:53.37#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.19:57:53.37#ibcon#[27=BW32\r\n] 2006.201.19:57:53.37#ibcon#*before write, iclass 13, count 0 2006.201.19:57:53.37#ibcon#enter sib2, iclass 13, count 0 2006.201.19:57:53.37#ibcon#flushed, iclass 13, count 0 2006.201.19:57:53.37#ibcon#about to write, iclass 13, count 0 2006.201.19:57:53.37#ibcon#wrote, iclass 13, count 0 2006.201.19:57:53.37#ibcon#about to read 3, iclass 13, count 0 2006.201.19:57:53.41#ibcon#read 3, iclass 13, count 0 2006.201.19:57:53.41#ibcon#about to read 4, iclass 13, count 0 2006.201.19:57:53.41#ibcon#read 4, iclass 13, count 0 2006.201.19:57:53.41#ibcon#about to read 5, iclass 13, count 0 2006.201.19:57:53.41#ibcon#read 5, iclass 13, count 0 2006.201.19:57:53.41#ibcon#about to read 6, iclass 13, count 0 2006.201.19:57:53.41#ibcon#read 6, iclass 13, count 0 2006.201.19:57:53.41#ibcon#end of sib2, iclass 13, count 0 2006.201.19:57:53.41#ibcon#*after write, iclass 13, count 0 2006.201.19:57:53.41#ibcon#*before return 0, iclass 13, count 0 2006.201.19:57:53.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:57:53.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.19:57:53.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.19:57:53.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.19:57:53.41$setupk4/ifdk4 2006.201.19:57:53.41$ifdk4/lo= 2006.201.19:57:53.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.19:57:53.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.19:57:53.41$ifdk4/patch= 2006.201.19:57:53.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.19:57:53.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.19:57:53.41$setupk4/!*+20s 2006.201.19:57:56.19#abcon#<5=/04 2.2 3.9 20.311001002.1\r\n> 2006.201.19:57:56.21#abcon#{5=INTERFACE CLEAR} 2006.201.19:57:56.27#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:57:58.14#trakl#Source acquired 2006.201.19:57:58.14#flagr#flagr/antenna,acquired 2006.201.19:58:06.36#abcon#<5=/04 2.3 4.0 20.311001002.0\r\n> 2006.201.19:58:06.38#abcon#{5=INTERFACE CLEAR} 2006.201.19:58:06.44#abcon#[5=S1D000X0/0*\r\n] 2006.201.19:58:07.86$setupk4/"tpicd 2006.201.19:58:07.86$setupk4/echo=off 2006.201.19:58:07.86$setupk4/xlog=off 2006.201.19:58:07.86:!2006.201.19:58:34 2006.201.19:58:34.00:preob 2006.201.19:58:35.14/onsource/TRACKING 2006.201.19:58:35.14:!2006.201.19:58:44 2006.201.19:58:44.00:"tape 2006.201.19:58:44.00:"st=record 2006.201.19:58:44.00:data_valid=on 2006.201.19:58:44.00:midob 2006.201.19:58:44.14/onsource/TRACKING 2006.201.19:58:44.14/wx/20.30,1002.0,100 2006.201.19:58:44.22/cable/+6.4799E-03 2006.201.19:58:45.31/va/01,08,usb,yes,42,44 2006.201.19:58:45.31/va/02,07,usb,yes,45,46 2006.201.19:58:45.31/va/03,08,usb,yes,41,43 2006.201.19:58:45.31/va/04,07,usb,yes,46,49 2006.201.19:58:45.31/va/05,04,usb,yes,41,42 2006.201.19:58:45.31/va/06,05,usb,yes,41,41 2006.201.19:58:45.31/va/07,05,usb,yes,41,42 2006.201.19:58:45.31/va/08,04,usb,yes,40,48 2006.201.19:58:45.54/valo/01,524.99,yes,locked 2006.201.19:58:45.54/valo/02,534.99,yes,locked 2006.201.19:58:45.54/valo/03,564.99,yes,locked 2006.201.19:58:45.54/valo/04,624.99,yes,locked 2006.201.19:58:45.54/valo/05,734.99,yes,locked 2006.201.19:58:45.54/valo/06,814.99,yes,locked 2006.201.19:58:45.54/valo/07,864.99,yes,locked 2006.201.19:58:45.54/valo/08,884.99,yes,locked 2006.201.19:58:46.63/vb/01,04,usb,yes,36,29 2006.201.19:58:46.63/vb/02,05,usb,yes,29,33 2006.201.19:58:46.63/vb/03,04,usb,yes,30,34 2006.201.19:58:46.63/vb/04,05,usb,yes,30,29 2006.201.19:58:46.63/vb/05,04,usb,yes,26,29 2006.201.19:58:46.63/vb/06,04,usb,yes,31,27 2006.201.19:58:46.63/vb/07,04,usb,yes,30,30 2006.201.19:58:46.63/vb/08,04,usb,yes,28,31 2006.201.19:58:46.86/vblo/01,629.99,yes,locked 2006.201.19:58:46.86/vblo/02,634.99,yes,locked 2006.201.19:58:46.86/vblo/03,649.99,yes,locked 2006.201.19:58:46.86/vblo/04,679.99,yes,locked 2006.201.19:58:46.86/vblo/05,709.99,yes,locked 2006.201.19:58:46.86/vblo/06,719.99,yes,locked 2006.201.19:58:46.86/vblo/07,734.99,yes,locked 2006.201.19:58:46.86/vblo/08,744.99,yes,locked 2006.201.19:58:47.01/vabw/8 2006.201.19:58:47.16/vbbw/8 2006.201.19:58:47.25/xfe/off,on,14.2 2006.201.19:58:47.68/ifatt/23,28,28,28 2006.201.19:58:48.06/fmout-gps/S +4.56E-07 2006.201.19:58:48.10:!2006.201.20:01:44 2006.201.20:01:44.00:data_valid=off 2006.201.20:01:44.00:"et 2006.201.20:01:44.00:!+3s 2006.201.20:01:47.02:"tape 2006.201.20:01:47.02:postob 2006.201.20:01:47.14/cable/+6.4811E-03 2006.201.20:01:47.14/wx/20.25,1002.1,100 2006.201.20:01:47.20/fmout-gps/S +4.56E-07 2006.201.20:01:47.20:scan_name=201-2005,jd0607,250 2006.201.20:01:47.20:source=1044+719,104827.62,714335.9,2000.0,cw 2006.201.20:01:48.13#flagr#flagr/antenna,new-source 2006.201.20:01:48.13:checkk5 2006.201.20:01:48.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:01:48.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:01:49.24/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:01:49.61/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:01:49.97/chk_obsdata//k5ts1/T2011958??a.dat file size is correct (nominal:720MB, actual:720MB). 2006.201.20:01:50.34/chk_obsdata//k5ts2/T2011958??b.dat file size is correct (nominal:720MB, actual:720MB). 2006.201.20:01:50.71/chk_obsdata//k5ts3/T2011958??c.dat file size is correct (nominal:720MB, actual:720MB). 2006.201.20:01:51.08/chk_obsdata//k5ts4/T2011958??d.dat file size is correct (nominal:720MB, actual:720MB). 2006.201.20:01:51.77/k5log//k5ts1_log_newline 2006.201.20:01:52.45/k5log//k5ts2_log_newline 2006.201.20:01:53.14/k5log//k5ts3_log_newline 2006.201.20:01:53.83/k5log//k5ts4_log_newline 2006.201.20:01:53.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:01:53.85:setupk4=1 2006.201.20:01:53.86$setupk4/echo=on 2006.201.20:01:53.86$setupk4/pcalon 2006.201.20:01:53.86$pcalon/"no phase cal control is implemented here 2006.201.20:01:53.86$setupk4/"tpicd=stop 2006.201.20:01:53.86$setupk4/"rec=synch_on 2006.201.20:01:53.86$setupk4/"rec_mode=128 2006.201.20:01:53.86$setupk4/!* 2006.201.20:01:53.86$setupk4/recpk4 2006.201.20:01:53.86$recpk4/recpatch= 2006.201.20:01:53.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:01:53.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:01:53.86$setupk4/vck44 2006.201.20:01:53.86$vck44/valo=1,524.99 2006.201.20:01:53.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.20:01:53.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.20:01:53.86#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:53.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:53.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:53.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:53.86#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:01:53.86#ibcon#first serial, iclass 4, count 0 2006.201.20:01:53.86#ibcon#enter sib2, iclass 4, count 0 2006.201.20:01:53.86#ibcon#flushed, iclass 4, count 0 2006.201.20:01:53.86#ibcon#about to write, iclass 4, count 0 2006.201.20:01:53.86#ibcon#wrote, iclass 4, count 0 2006.201.20:01:53.86#ibcon#about to read 3, iclass 4, count 0 2006.201.20:01:53.90#ibcon#read 3, iclass 4, count 0 2006.201.20:01:53.90#ibcon#about to read 4, iclass 4, count 0 2006.201.20:01:53.90#ibcon#read 4, iclass 4, count 0 2006.201.20:01:53.90#ibcon#about to read 5, iclass 4, count 0 2006.201.20:01:53.90#ibcon#read 5, iclass 4, count 0 2006.201.20:01:53.90#ibcon#about to read 6, iclass 4, count 0 2006.201.20:01:53.90#ibcon#read 6, iclass 4, count 0 2006.201.20:01:53.90#ibcon#end of sib2, iclass 4, count 0 2006.201.20:01:53.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:01:53.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:01:53.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:01:53.90#ibcon#*before write, iclass 4, count 0 2006.201.20:01:53.90#ibcon#enter sib2, iclass 4, count 0 2006.201.20:01:53.90#ibcon#flushed, iclass 4, count 0 2006.201.20:01:53.90#ibcon#about to write, iclass 4, count 0 2006.201.20:01:53.90#ibcon#wrote, iclass 4, count 0 2006.201.20:01:53.90#ibcon#about to read 3, iclass 4, count 0 2006.201.20:01:53.95#ibcon#read 3, iclass 4, count 0 2006.201.20:01:53.95#ibcon#about to read 4, iclass 4, count 0 2006.201.20:01:53.95#ibcon#read 4, iclass 4, count 0 2006.201.20:01:53.95#ibcon#about to read 5, iclass 4, count 0 2006.201.20:01:53.95#ibcon#read 5, iclass 4, count 0 2006.201.20:01:53.95#ibcon#about to read 6, iclass 4, count 0 2006.201.20:01:53.95#ibcon#read 6, iclass 4, count 0 2006.201.20:01:53.95#ibcon#end of sib2, iclass 4, count 0 2006.201.20:01:53.95#ibcon#*after write, iclass 4, count 0 2006.201.20:01:53.95#ibcon#*before return 0, iclass 4, count 0 2006.201.20:01:53.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:53.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:53.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:01:53.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:01:53.95$vck44/va=1,8 2006.201.20:01:53.95#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.20:01:53.95#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.20:01:53.95#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:53.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:53.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:53.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:53.95#ibcon#enter wrdev, iclass 6, count 2 2006.201.20:01:53.95#ibcon#first serial, iclass 6, count 2 2006.201.20:01:53.95#ibcon#enter sib2, iclass 6, count 2 2006.201.20:01:53.95#ibcon#flushed, iclass 6, count 2 2006.201.20:01:53.95#ibcon#about to write, iclass 6, count 2 2006.201.20:01:53.95#ibcon#wrote, iclass 6, count 2 2006.201.20:01:53.95#ibcon#about to read 3, iclass 6, count 2 2006.201.20:01:53.97#ibcon#read 3, iclass 6, count 2 2006.201.20:01:53.97#ibcon#about to read 4, iclass 6, count 2 2006.201.20:01:53.97#ibcon#read 4, iclass 6, count 2 2006.201.20:01:53.97#ibcon#about to read 5, iclass 6, count 2 2006.201.20:01:53.97#ibcon#read 5, iclass 6, count 2 2006.201.20:01:53.97#ibcon#about to read 6, iclass 6, count 2 2006.201.20:01:53.97#ibcon#read 6, iclass 6, count 2 2006.201.20:01:53.97#ibcon#end of sib2, iclass 6, count 2 2006.201.20:01:53.97#ibcon#*mode == 0, iclass 6, count 2 2006.201.20:01:53.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.20:01:53.97#ibcon#[25=AT01-08\r\n] 2006.201.20:01:53.97#ibcon#*before write, iclass 6, count 2 2006.201.20:01:53.97#ibcon#enter sib2, iclass 6, count 2 2006.201.20:01:53.97#ibcon#flushed, iclass 6, count 2 2006.201.20:01:53.97#ibcon#about to write, iclass 6, count 2 2006.201.20:01:53.97#ibcon#wrote, iclass 6, count 2 2006.201.20:01:53.97#ibcon#about to read 3, iclass 6, count 2 2006.201.20:01:54.00#ibcon#read 3, iclass 6, count 2 2006.201.20:01:54.00#ibcon#about to read 4, iclass 6, count 2 2006.201.20:01:54.00#ibcon#read 4, iclass 6, count 2 2006.201.20:01:54.00#ibcon#about to read 5, iclass 6, count 2 2006.201.20:01:54.00#ibcon#read 5, iclass 6, count 2 2006.201.20:01:54.00#ibcon#about to read 6, iclass 6, count 2 2006.201.20:01:54.00#ibcon#read 6, iclass 6, count 2 2006.201.20:01:54.00#ibcon#end of sib2, iclass 6, count 2 2006.201.20:01:54.00#ibcon#*after write, iclass 6, count 2 2006.201.20:01:54.00#ibcon#*before return 0, iclass 6, count 2 2006.201.20:01:54.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:54.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:54.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.20:01:54.00#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:54.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:54.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:54.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:54.12#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:01:54.12#ibcon#first serial, iclass 6, count 0 2006.201.20:01:54.12#ibcon#enter sib2, iclass 6, count 0 2006.201.20:01:54.12#ibcon#flushed, iclass 6, count 0 2006.201.20:01:54.12#ibcon#about to write, iclass 6, count 0 2006.201.20:01:54.12#ibcon#wrote, iclass 6, count 0 2006.201.20:01:54.12#ibcon#about to read 3, iclass 6, count 0 2006.201.20:01:54.14#ibcon#read 3, iclass 6, count 0 2006.201.20:01:54.14#ibcon#about to read 4, iclass 6, count 0 2006.201.20:01:54.14#ibcon#read 4, iclass 6, count 0 2006.201.20:01:54.14#ibcon#about to read 5, iclass 6, count 0 2006.201.20:01:54.14#ibcon#read 5, iclass 6, count 0 2006.201.20:01:54.14#ibcon#about to read 6, iclass 6, count 0 2006.201.20:01:54.14#ibcon#read 6, iclass 6, count 0 2006.201.20:01:54.14#ibcon#end of sib2, iclass 6, count 0 2006.201.20:01:54.14#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:01:54.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:01:54.14#ibcon#[25=USB\r\n] 2006.201.20:01:54.14#ibcon#*before write, iclass 6, count 0 2006.201.20:01:54.14#ibcon#enter sib2, iclass 6, count 0 2006.201.20:01:54.14#ibcon#flushed, iclass 6, count 0 2006.201.20:01:54.14#ibcon#about to write, iclass 6, count 0 2006.201.20:01:54.14#ibcon#wrote, iclass 6, count 0 2006.201.20:01:54.14#ibcon#about to read 3, iclass 6, count 0 2006.201.20:01:54.17#ibcon#read 3, iclass 6, count 0 2006.201.20:01:54.17#ibcon#about to read 4, iclass 6, count 0 2006.201.20:01:54.17#ibcon#read 4, iclass 6, count 0 2006.201.20:01:54.17#ibcon#about to read 5, iclass 6, count 0 2006.201.20:01:54.17#ibcon#read 5, iclass 6, count 0 2006.201.20:01:54.17#ibcon#about to read 6, iclass 6, count 0 2006.201.20:01:54.17#ibcon#read 6, iclass 6, count 0 2006.201.20:01:54.17#ibcon#end of sib2, iclass 6, count 0 2006.201.20:01:54.17#ibcon#*after write, iclass 6, count 0 2006.201.20:01:54.17#ibcon#*before return 0, iclass 6, count 0 2006.201.20:01:54.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:54.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:54.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:01:54.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:01:54.17$vck44/valo=2,534.99 2006.201.20:01:54.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.20:01:54.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.20:01:54.17#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:54.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:54.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:54.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:54.17#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:01:54.17#ibcon#first serial, iclass 10, count 0 2006.201.20:01:54.17#ibcon#enter sib2, iclass 10, count 0 2006.201.20:01:54.17#ibcon#flushed, iclass 10, count 0 2006.201.20:01:54.17#ibcon#about to write, iclass 10, count 0 2006.201.20:01:54.17#ibcon#wrote, iclass 10, count 0 2006.201.20:01:54.17#ibcon#about to read 3, iclass 10, count 0 2006.201.20:01:54.19#ibcon#read 3, iclass 10, count 0 2006.201.20:01:54.19#ibcon#about to read 4, iclass 10, count 0 2006.201.20:01:54.19#ibcon#read 4, iclass 10, count 0 2006.201.20:01:54.19#ibcon#about to read 5, iclass 10, count 0 2006.201.20:01:54.19#ibcon#read 5, iclass 10, count 0 2006.201.20:01:54.19#ibcon#about to read 6, iclass 10, count 0 2006.201.20:01:54.19#ibcon#read 6, iclass 10, count 0 2006.201.20:01:54.19#ibcon#end of sib2, iclass 10, count 0 2006.201.20:01:54.19#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:01:54.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:01:54.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:01:54.19#ibcon#*before write, iclass 10, count 0 2006.201.20:01:54.19#ibcon#enter sib2, iclass 10, count 0 2006.201.20:01:54.19#ibcon#flushed, iclass 10, count 0 2006.201.20:01:54.19#ibcon#about to write, iclass 10, count 0 2006.201.20:01:54.19#ibcon#wrote, iclass 10, count 0 2006.201.20:01:54.19#ibcon#about to read 3, iclass 10, count 0 2006.201.20:01:54.24#ibcon#read 3, iclass 10, count 0 2006.201.20:01:54.24#ibcon#about to read 4, iclass 10, count 0 2006.201.20:01:54.24#ibcon#read 4, iclass 10, count 0 2006.201.20:01:54.24#ibcon#about to read 5, iclass 10, count 0 2006.201.20:01:54.24#ibcon#read 5, iclass 10, count 0 2006.201.20:01:54.24#ibcon#about to read 6, iclass 10, count 0 2006.201.20:01:54.24#ibcon#read 6, iclass 10, count 0 2006.201.20:01:54.24#ibcon#end of sib2, iclass 10, count 0 2006.201.20:01:54.24#ibcon#*after write, iclass 10, count 0 2006.201.20:01:54.24#ibcon#*before return 0, iclass 10, count 0 2006.201.20:01:54.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:54.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:54.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:01:54.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:01:54.24$vck44/va=2,7 2006.201.20:01:54.24#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.20:01:54.24#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.20:01:54.24#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:54.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:54.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:54.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:54.29#ibcon#enter wrdev, iclass 12, count 2 2006.201.20:01:54.29#ibcon#first serial, iclass 12, count 2 2006.201.20:01:54.29#ibcon#enter sib2, iclass 12, count 2 2006.201.20:01:54.29#ibcon#flushed, iclass 12, count 2 2006.201.20:01:54.29#ibcon#about to write, iclass 12, count 2 2006.201.20:01:54.29#ibcon#wrote, iclass 12, count 2 2006.201.20:01:54.29#ibcon#about to read 3, iclass 12, count 2 2006.201.20:01:54.31#ibcon#read 3, iclass 12, count 2 2006.201.20:01:54.31#ibcon#about to read 4, iclass 12, count 2 2006.201.20:01:54.31#ibcon#read 4, iclass 12, count 2 2006.201.20:01:54.31#ibcon#about to read 5, iclass 12, count 2 2006.201.20:01:54.31#ibcon#read 5, iclass 12, count 2 2006.201.20:01:54.31#ibcon#about to read 6, iclass 12, count 2 2006.201.20:01:54.31#ibcon#read 6, iclass 12, count 2 2006.201.20:01:54.31#ibcon#end of sib2, iclass 12, count 2 2006.201.20:01:54.31#ibcon#*mode == 0, iclass 12, count 2 2006.201.20:01:54.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.20:01:54.31#ibcon#[25=AT02-07\r\n] 2006.201.20:01:54.31#ibcon#*before write, iclass 12, count 2 2006.201.20:01:54.31#ibcon#enter sib2, iclass 12, count 2 2006.201.20:01:54.31#ibcon#flushed, iclass 12, count 2 2006.201.20:01:54.31#ibcon#about to write, iclass 12, count 2 2006.201.20:01:54.31#ibcon#wrote, iclass 12, count 2 2006.201.20:01:54.31#ibcon#about to read 3, iclass 12, count 2 2006.201.20:01:54.34#ibcon#read 3, iclass 12, count 2 2006.201.20:01:54.34#ibcon#about to read 4, iclass 12, count 2 2006.201.20:01:54.34#ibcon#read 4, iclass 12, count 2 2006.201.20:01:54.34#ibcon#about to read 5, iclass 12, count 2 2006.201.20:01:54.34#ibcon#read 5, iclass 12, count 2 2006.201.20:01:54.34#ibcon#about to read 6, iclass 12, count 2 2006.201.20:01:54.34#ibcon#read 6, iclass 12, count 2 2006.201.20:01:54.34#ibcon#end of sib2, iclass 12, count 2 2006.201.20:01:54.34#ibcon#*after write, iclass 12, count 2 2006.201.20:01:54.34#ibcon#*before return 0, iclass 12, count 2 2006.201.20:01:54.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:54.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:54.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.20:01:54.34#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:54.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:54.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:54.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:54.46#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:01:54.46#ibcon#first serial, iclass 12, count 0 2006.201.20:01:54.46#ibcon#enter sib2, iclass 12, count 0 2006.201.20:01:54.46#ibcon#flushed, iclass 12, count 0 2006.201.20:01:54.46#ibcon#about to write, iclass 12, count 0 2006.201.20:01:54.46#ibcon#wrote, iclass 12, count 0 2006.201.20:01:54.46#ibcon#about to read 3, iclass 12, count 0 2006.201.20:01:54.48#ibcon#read 3, iclass 12, count 0 2006.201.20:01:54.48#ibcon#about to read 4, iclass 12, count 0 2006.201.20:01:54.48#ibcon#read 4, iclass 12, count 0 2006.201.20:01:54.48#ibcon#about to read 5, iclass 12, count 0 2006.201.20:01:54.48#ibcon#read 5, iclass 12, count 0 2006.201.20:01:54.48#ibcon#about to read 6, iclass 12, count 0 2006.201.20:01:54.48#ibcon#read 6, iclass 12, count 0 2006.201.20:01:54.48#ibcon#end of sib2, iclass 12, count 0 2006.201.20:01:54.48#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:01:54.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:01:54.48#ibcon#[25=USB\r\n] 2006.201.20:01:54.48#ibcon#*before write, iclass 12, count 0 2006.201.20:01:54.48#ibcon#enter sib2, iclass 12, count 0 2006.201.20:01:54.48#ibcon#flushed, iclass 12, count 0 2006.201.20:01:54.48#ibcon#about to write, iclass 12, count 0 2006.201.20:01:54.48#ibcon#wrote, iclass 12, count 0 2006.201.20:01:54.48#ibcon#about to read 3, iclass 12, count 0 2006.201.20:01:54.51#ibcon#read 3, iclass 12, count 0 2006.201.20:01:54.51#ibcon#about to read 4, iclass 12, count 0 2006.201.20:01:54.51#ibcon#read 4, iclass 12, count 0 2006.201.20:01:54.51#ibcon#about to read 5, iclass 12, count 0 2006.201.20:01:54.51#ibcon#read 5, iclass 12, count 0 2006.201.20:01:54.51#ibcon#about to read 6, iclass 12, count 0 2006.201.20:01:54.51#ibcon#read 6, iclass 12, count 0 2006.201.20:01:54.51#ibcon#end of sib2, iclass 12, count 0 2006.201.20:01:54.51#ibcon#*after write, iclass 12, count 0 2006.201.20:01:54.51#ibcon#*before return 0, iclass 12, count 0 2006.201.20:01:54.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:54.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:54.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:01:54.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:01:54.51$vck44/valo=3,564.99 2006.201.20:01:54.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.20:01:54.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.20:01:54.51#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:54.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:54.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:54.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:54.51#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:01:54.51#ibcon#first serial, iclass 14, count 0 2006.201.20:01:54.51#ibcon#enter sib2, iclass 14, count 0 2006.201.20:01:54.51#ibcon#flushed, iclass 14, count 0 2006.201.20:01:54.51#ibcon#about to write, iclass 14, count 0 2006.201.20:01:54.51#ibcon#wrote, iclass 14, count 0 2006.201.20:01:54.51#ibcon#about to read 3, iclass 14, count 0 2006.201.20:01:54.53#ibcon#read 3, iclass 14, count 0 2006.201.20:01:54.53#ibcon#about to read 4, iclass 14, count 0 2006.201.20:01:54.53#ibcon#read 4, iclass 14, count 0 2006.201.20:01:54.53#ibcon#about to read 5, iclass 14, count 0 2006.201.20:01:54.53#ibcon#read 5, iclass 14, count 0 2006.201.20:01:54.53#ibcon#about to read 6, iclass 14, count 0 2006.201.20:01:54.53#ibcon#read 6, iclass 14, count 0 2006.201.20:01:54.53#ibcon#end of sib2, iclass 14, count 0 2006.201.20:01:54.53#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:01:54.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:01:54.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:01:54.53#ibcon#*before write, iclass 14, count 0 2006.201.20:01:54.53#ibcon#enter sib2, iclass 14, count 0 2006.201.20:01:54.53#ibcon#flushed, iclass 14, count 0 2006.201.20:01:54.53#ibcon#about to write, iclass 14, count 0 2006.201.20:01:54.53#ibcon#wrote, iclass 14, count 0 2006.201.20:01:54.53#ibcon#about to read 3, iclass 14, count 0 2006.201.20:01:54.58#ibcon#read 3, iclass 14, count 0 2006.201.20:01:54.58#ibcon#about to read 4, iclass 14, count 0 2006.201.20:01:54.58#ibcon#read 4, iclass 14, count 0 2006.201.20:01:54.58#ibcon#about to read 5, iclass 14, count 0 2006.201.20:01:54.58#ibcon#read 5, iclass 14, count 0 2006.201.20:01:54.58#ibcon#about to read 6, iclass 14, count 0 2006.201.20:01:54.58#ibcon#read 6, iclass 14, count 0 2006.201.20:01:54.58#ibcon#end of sib2, iclass 14, count 0 2006.201.20:01:54.58#ibcon#*after write, iclass 14, count 0 2006.201.20:01:54.58#ibcon#*before return 0, iclass 14, count 0 2006.201.20:01:54.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:54.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:54.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:01:54.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:01:54.58$vck44/va=3,8 2006.201.20:01:54.58#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.20:01:54.58#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.20:01:54.58#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:54.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:54.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:54.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:54.63#ibcon#enter wrdev, iclass 16, count 2 2006.201.20:01:54.63#ibcon#first serial, iclass 16, count 2 2006.201.20:01:54.63#ibcon#enter sib2, iclass 16, count 2 2006.201.20:01:54.63#ibcon#flushed, iclass 16, count 2 2006.201.20:01:54.63#ibcon#about to write, iclass 16, count 2 2006.201.20:01:54.63#ibcon#wrote, iclass 16, count 2 2006.201.20:01:54.63#ibcon#about to read 3, iclass 16, count 2 2006.201.20:01:54.65#ibcon#read 3, iclass 16, count 2 2006.201.20:01:54.65#ibcon#about to read 4, iclass 16, count 2 2006.201.20:01:54.65#ibcon#read 4, iclass 16, count 2 2006.201.20:01:54.65#ibcon#about to read 5, iclass 16, count 2 2006.201.20:01:54.65#ibcon#read 5, iclass 16, count 2 2006.201.20:01:54.65#ibcon#about to read 6, iclass 16, count 2 2006.201.20:01:54.65#ibcon#read 6, iclass 16, count 2 2006.201.20:01:54.65#ibcon#end of sib2, iclass 16, count 2 2006.201.20:01:54.65#ibcon#*mode == 0, iclass 16, count 2 2006.201.20:01:54.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.20:01:54.65#ibcon#[25=AT03-08\r\n] 2006.201.20:01:54.65#ibcon#*before write, iclass 16, count 2 2006.201.20:01:54.65#ibcon#enter sib2, iclass 16, count 2 2006.201.20:01:54.65#ibcon#flushed, iclass 16, count 2 2006.201.20:01:54.65#ibcon#about to write, iclass 16, count 2 2006.201.20:01:54.65#ibcon#wrote, iclass 16, count 2 2006.201.20:01:54.65#ibcon#about to read 3, iclass 16, count 2 2006.201.20:01:54.68#ibcon#read 3, iclass 16, count 2 2006.201.20:01:54.68#ibcon#about to read 4, iclass 16, count 2 2006.201.20:01:54.68#ibcon#read 4, iclass 16, count 2 2006.201.20:01:54.68#ibcon#about to read 5, iclass 16, count 2 2006.201.20:01:54.68#ibcon#read 5, iclass 16, count 2 2006.201.20:01:54.68#ibcon#about to read 6, iclass 16, count 2 2006.201.20:01:54.68#ibcon#read 6, iclass 16, count 2 2006.201.20:01:54.68#ibcon#end of sib2, iclass 16, count 2 2006.201.20:01:54.68#ibcon#*after write, iclass 16, count 2 2006.201.20:01:54.68#ibcon#*before return 0, iclass 16, count 2 2006.201.20:01:54.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:54.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:54.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.20:01:54.68#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:54.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:54.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:54.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:54.80#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:01:54.80#ibcon#first serial, iclass 16, count 0 2006.201.20:01:54.80#ibcon#enter sib2, iclass 16, count 0 2006.201.20:01:54.80#ibcon#flushed, iclass 16, count 0 2006.201.20:01:54.80#ibcon#about to write, iclass 16, count 0 2006.201.20:01:54.80#ibcon#wrote, iclass 16, count 0 2006.201.20:01:54.80#ibcon#about to read 3, iclass 16, count 0 2006.201.20:01:54.82#ibcon#read 3, iclass 16, count 0 2006.201.20:01:54.82#ibcon#about to read 4, iclass 16, count 0 2006.201.20:01:54.82#ibcon#read 4, iclass 16, count 0 2006.201.20:01:54.82#ibcon#about to read 5, iclass 16, count 0 2006.201.20:01:54.82#ibcon#read 5, iclass 16, count 0 2006.201.20:01:54.82#ibcon#about to read 6, iclass 16, count 0 2006.201.20:01:54.82#ibcon#read 6, iclass 16, count 0 2006.201.20:01:54.82#ibcon#end of sib2, iclass 16, count 0 2006.201.20:01:54.82#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:01:54.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:01:54.82#ibcon#[25=USB\r\n] 2006.201.20:01:54.82#ibcon#*before write, iclass 16, count 0 2006.201.20:01:54.82#ibcon#enter sib2, iclass 16, count 0 2006.201.20:01:54.82#ibcon#flushed, iclass 16, count 0 2006.201.20:01:54.82#ibcon#about to write, iclass 16, count 0 2006.201.20:01:54.82#ibcon#wrote, iclass 16, count 0 2006.201.20:01:54.82#ibcon#about to read 3, iclass 16, count 0 2006.201.20:01:54.85#ibcon#read 3, iclass 16, count 0 2006.201.20:01:54.85#ibcon#about to read 4, iclass 16, count 0 2006.201.20:01:54.85#ibcon#read 4, iclass 16, count 0 2006.201.20:01:54.85#ibcon#about to read 5, iclass 16, count 0 2006.201.20:01:54.85#ibcon#read 5, iclass 16, count 0 2006.201.20:01:54.85#ibcon#about to read 6, iclass 16, count 0 2006.201.20:01:54.85#ibcon#read 6, iclass 16, count 0 2006.201.20:01:54.85#ibcon#end of sib2, iclass 16, count 0 2006.201.20:01:54.85#ibcon#*after write, iclass 16, count 0 2006.201.20:01:54.85#ibcon#*before return 0, iclass 16, count 0 2006.201.20:01:54.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:54.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:54.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:01:54.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:01:54.85$vck44/valo=4,624.99 2006.201.20:01:54.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.20:01:54.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.20:01:54.85#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:54.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:54.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:54.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:54.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:01:54.85#ibcon#first serial, iclass 18, count 0 2006.201.20:01:54.85#ibcon#enter sib2, iclass 18, count 0 2006.201.20:01:54.85#ibcon#flushed, iclass 18, count 0 2006.201.20:01:54.85#ibcon#about to write, iclass 18, count 0 2006.201.20:01:54.85#ibcon#wrote, iclass 18, count 0 2006.201.20:01:54.85#ibcon#about to read 3, iclass 18, count 0 2006.201.20:01:54.87#ibcon#read 3, iclass 18, count 0 2006.201.20:01:54.87#ibcon#about to read 4, iclass 18, count 0 2006.201.20:01:54.87#ibcon#read 4, iclass 18, count 0 2006.201.20:01:54.87#ibcon#about to read 5, iclass 18, count 0 2006.201.20:01:54.87#ibcon#read 5, iclass 18, count 0 2006.201.20:01:54.87#ibcon#about to read 6, iclass 18, count 0 2006.201.20:01:54.87#ibcon#read 6, iclass 18, count 0 2006.201.20:01:54.87#ibcon#end of sib2, iclass 18, count 0 2006.201.20:01:54.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:01:54.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:01:54.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:01:54.87#ibcon#*before write, iclass 18, count 0 2006.201.20:01:54.87#ibcon#enter sib2, iclass 18, count 0 2006.201.20:01:54.87#ibcon#flushed, iclass 18, count 0 2006.201.20:01:54.87#ibcon#about to write, iclass 18, count 0 2006.201.20:01:54.87#ibcon#wrote, iclass 18, count 0 2006.201.20:01:54.87#ibcon#about to read 3, iclass 18, count 0 2006.201.20:01:54.91#ibcon#read 3, iclass 18, count 0 2006.201.20:01:54.91#ibcon#about to read 4, iclass 18, count 0 2006.201.20:01:54.91#ibcon#read 4, iclass 18, count 0 2006.201.20:01:54.91#ibcon#about to read 5, iclass 18, count 0 2006.201.20:01:54.91#ibcon#read 5, iclass 18, count 0 2006.201.20:01:54.91#ibcon#about to read 6, iclass 18, count 0 2006.201.20:01:54.91#ibcon#read 6, iclass 18, count 0 2006.201.20:01:54.91#ibcon#end of sib2, iclass 18, count 0 2006.201.20:01:54.91#ibcon#*after write, iclass 18, count 0 2006.201.20:01:54.91#ibcon#*before return 0, iclass 18, count 0 2006.201.20:01:54.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:54.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:54.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:01:54.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:01:54.91$vck44/va=4,7 2006.201.20:01:54.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.20:01:54.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.20:01:54.91#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:54.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:54.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:54.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:54.97#ibcon#enter wrdev, iclass 20, count 2 2006.201.20:01:54.97#ibcon#first serial, iclass 20, count 2 2006.201.20:01:54.97#ibcon#enter sib2, iclass 20, count 2 2006.201.20:01:54.97#ibcon#flushed, iclass 20, count 2 2006.201.20:01:54.97#ibcon#about to write, iclass 20, count 2 2006.201.20:01:54.97#ibcon#wrote, iclass 20, count 2 2006.201.20:01:54.97#ibcon#about to read 3, iclass 20, count 2 2006.201.20:01:54.99#ibcon#read 3, iclass 20, count 2 2006.201.20:01:54.99#ibcon#about to read 4, iclass 20, count 2 2006.201.20:01:54.99#ibcon#read 4, iclass 20, count 2 2006.201.20:01:54.99#ibcon#about to read 5, iclass 20, count 2 2006.201.20:01:54.99#ibcon#read 5, iclass 20, count 2 2006.201.20:01:54.99#ibcon#about to read 6, iclass 20, count 2 2006.201.20:01:54.99#ibcon#read 6, iclass 20, count 2 2006.201.20:01:54.99#ibcon#end of sib2, iclass 20, count 2 2006.201.20:01:54.99#ibcon#*mode == 0, iclass 20, count 2 2006.201.20:01:54.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.20:01:54.99#ibcon#[25=AT04-07\r\n] 2006.201.20:01:54.99#ibcon#*before write, iclass 20, count 2 2006.201.20:01:54.99#ibcon#enter sib2, iclass 20, count 2 2006.201.20:01:54.99#ibcon#flushed, iclass 20, count 2 2006.201.20:01:54.99#ibcon#about to write, iclass 20, count 2 2006.201.20:01:54.99#ibcon#wrote, iclass 20, count 2 2006.201.20:01:54.99#ibcon#about to read 3, iclass 20, count 2 2006.201.20:01:55.02#ibcon#read 3, iclass 20, count 2 2006.201.20:01:55.02#ibcon#about to read 4, iclass 20, count 2 2006.201.20:01:55.02#ibcon#read 4, iclass 20, count 2 2006.201.20:01:55.02#ibcon#about to read 5, iclass 20, count 2 2006.201.20:01:55.02#ibcon#read 5, iclass 20, count 2 2006.201.20:01:55.02#ibcon#about to read 6, iclass 20, count 2 2006.201.20:01:55.02#ibcon#read 6, iclass 20, count 2 2006.201.20:01:55.02#ibcon#end of sib2, iclass 20, count 2 2006.201.20:01:55.02#ibcon#*after write, iclass 20, count 2 2006.201.20:01:55.02#ibcon#*before return 0, iclass 20, count 2 2006.201.20:01:55.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:55.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:55.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.20:01:55.02#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:55.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:55.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:55.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:55.14#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:01:55.14#ibcon#first serial, iclass 20, count 0 2006.201.20:01:55.14#ibcon#enter sib2, iclass 20, count 0 2006.201.20:01:55.14#ibcon#flushed, iclass 20, count 0 2006.201.20:01:55.14#ibcon#about to write, iclass 20, count 0 2006.201.20:01:55.14#ibcon#wrote, iclass 20, count 0 2006.201.20:01:55.14#ibcon#about to read 3, iclass 20, count 0 2006.201.20:01:55.16#ibcon#read 3, iclass 20, count 0 2006.201.20:01:55.16#ibcon#about to read 4, iclass 20, count 0 2006.201.20:01:55.16#ibcon#read 4, iclass 20, count 0 2006.201.20:01:55.16#ibcon#about to read 5, iclass 20, count 0 2006.201.20:01:55.16#ibcon#read 5, iclass 20, count 0 2006.201.20:01:55.16#ibcon#about to read 6, iclass 20, count 0 2006.201.20:01:55.16#ibcon#read 6, iclass 20, count 0 2006.201.20:01:55.16#ibcon#end of sib2, iclass 20, count 0 2006.201.20:01:55.16#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:01:55.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:01:55.16#ibcon#[25=USB\r\n] 2006.201.20:01:55.16#ibcon#*before write, iclass 20, count 0 2006.201.20:01:55.16#ibcon#enter sib2, iclass 20, count 0 2006.201.20:01:55.16#ibcon#flushed, iclass 20, count 0 2006.201.20:01:55.16#ibcon#about to write, iclass 20, count 0 2006.201.20:01:55.16#ibcon#wrote, iclass 20, count 0 2006.201.20:01:55.16#ibcon#about to read 3, iclass 20, count 0 2006.201.20:01:55.19#ibcon#read 3, iclass 20, count 0 2006.201.20:01:55.19#ibcon#about to read 4, iclass 20, count 0 2006.201.20:01:55.19#ibcon#read 4, iclass 20, count 0 2006.201.20:01:55.19#ibcon#about to read 5, iclass 20, count 0 2006.201.20:01:55.19#ibcon#read 5, iclass 20, count 0 2006.201.20:01:55.19#ibcon#about to read 6, iclass 20, count 0 2006.201.20:01:55.19#ibcon#read 6, iclass 20, count 0 2006.201.20:01:55.19#ibcon#end of sib2, iclass 20, count 0 2006.201.20:01:55.19#ibcon#*after write, iclass 20, count 0 2006.201.20:01:55.19#ibcon#*before return 0, iclass 20, count 0 2006.201.20:01:55.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:55.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:55.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:01:55.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:01:55.19$vck44/valo=5,734.99 2006.201.20:01:55.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.20:01:55.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.20:01:55.19#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:55.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:55.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:55.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:55.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:01:55.19#ibcon#first serial, iclass 22, count 0 2006.201.20:01:55.19#ibcon#enter sib2, iclass 22, count 0 2006.201.20:01:55.19#ibcon#flushed, iclass 22, count 0 2006.201.20:01:55.19#ibcon#about to write, iclass 22, count 0 2006.201.20:01:55.19#ibcon#wrote, iclass 22, count 0 2006.201.20:01:55.19#ibcon#about to read 3, iclass 22, count 0 2006.201.20:01:55.21#ibcon#read 3, iclass 22, count 0 2006.201.20:01:55.21#ibcon#about to read 4, iclass 22, count 0 2006.201.20:01:55.21#ibcon#read 4, iclass 22, count 0 2006.201.20:01:55.21#ibcon#about to read 5, iclass 22, count 0 2006.201.20:01:55.21#ibcon#read 5, iclass 22, count 0 2006.201.20:01:55.21#ibcon#about to read 6, iclass 22, count 0 2006.201.20:01:55.21#ibcon#read 6, iclass 22, count 0 2006.201.20:01:55.21#ibcon#end of sib2, iclass 22, count 0 2006.201.20:01:55.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:01:55.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:01:55.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:01:55.21#ibcon#*before write, iclass 22, count 0 2006.201.20:01:55.21#ibcon#enter sib2, iclass 22, count 0 2006.201.20:01:55.21#ibcon#flushed, iclass 22, count 0 2006.201.20:01:55.21#ibcon#about to write, iclass 22, count 0 2006.201.20:01:55.21#ibcon#wrote, iclass 22, count 0 2006.201.20:01:55.21#ibcon#about to read 3, iclass 22, count 0 2006.201.20:01:55.25#ibcon#read 3, iclass 22, count 0 2006.201.20:01:55.25#ibcon#about to read 4, iclass 22, count 0 2006.201.20:01:55.25#ibcon#read 4, iclass 22, count 0 2006.201.20:01:55.25#ibcon#about to read 5, iclass 22, count 0 2006.201.20:01:55.25#ibcon#read 5, iclass 22, count 0 2006.201.20:01:55.25#ibcon#about to read 6, iclass 22, count 0 2006.201.20:01:55.25#ibcon#read 6, iclass 22, count 0 2006.201.20:01:55.25#ibcon#end of sib2, iclass 22, count 0 2006.201.20:01:55.25#ibcon#*after write, iclass 22, count 0 2006.201.20:01:55.25#ibcon#*before return 0, iclass 22, count 0 2006.201.20:01:55.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:55.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:55.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:01:55.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:01:55.25$vck44/va=5,4 2006.201.20:01:55.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.20:01:55.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.20:01:55.25#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:55.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:55.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:55.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:55.31#ibcon#enter wrdev, iclass 24, count 2 2006.201.20:01:55.31#ibcon#first serial, iclass 24, count 2 2006.201.20:01:55.31#ibcon#enter sib2, iclass 24, count 2 2006.201.20:01:55.31#ibcon#flushed, iclass 24, count 2 2006.201.20:01:55.31#ibcon#about to write, iclass 24, count 2 2006.201.20:01:55.31#ibcon#wrote, iclass 24, count 2 2006.201.20:01:55.31#ibcon#about to read 3, iclass 24, count 2 2006.201.20:01:55.33#ibcon#read 3, iclass 24, count 2 2006.201.20:01:55.33#ibcon#about to read 4, iclass 24, count 2 2006.201.20:01:55.33#ibcon#read 4, iclass 24, count 2 2006.201.20:01:55.33#ibcon#about to read 5, iclass 24, count 2 2006.201.20:01:55.33#ibcon#read 5, iclass 24, count 2 2006.201.20:01:55.33#ibcon#about to read 6, iclass 24, count 2 2006.201.20:01:55.33#ibcon#read 6, iclass 24, count 2 2006.201.20:01:55.33#ibcon#end of sib2, iclass 24, count 2 2006.201.20:01:55.33#ibcon#*mode == 0, iclass 24, count 2 2006.201.20:01:55.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.20:01:55.33#ibcon#[25=AT05-04\r\n] 2006.201.20:01:55.33#ibcon#*before write, iclass 24, count 2 2006.201.20:01:55.33#ibcon#enter sib2, iclass 24, count 2 2006.201.20:01:55.33#ibcon#flushed, iclass 24, count 2 2006.201.20:01:55.33#ibcon#about to write, iclass 24, count 2 2006.201.20:01:55.33#ibcon#wrote, iclass 24, count 2 2006.201.20:01:55.33#ibcon#about to read 3, iclass 24, count 2 2006.201.20:01:55.36#ibcon#read 3, iclass 24, count 2 2006.201.20:01:55.36#ibcon#about to read 4, iclass 24, count 2 2006.201.20:01:55.36#ibcon#read 4, iclass 24, count 2 2006.201.20:01:55.36#ibcon#about to read 5, iclass 24, count 2 2006.201.20:01:55.36#ibcon#read 5, iclass 24, count 2 2006.201.20:01:55.36#ibcon#about to read 6, iclass 24, count 2 2006.201.20:01:55.36#ibcon#read 6, iclass 24, count 2 2006.201.20:01:55.36#ibcon#end of sib2, iclass 24, count 2 2006.201.20:01:55.36#ibcon#*after write, iclass 24, count 2 2006.201.20:01:55.36#ibcon#*before return 0, iclass 24, count 2 2006.201.20:01:55.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:55.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:55.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.20:01:55.36#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:55.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:55.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:55.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:55.48#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:01:55.48#ibcon#first serial, iclass 24, count 0 2006.201.20:01:55.48#ibcon#enter sib2, iclass 24, count 0 2006.201.20:01:55.48#ibcon#flushed, iclass 24, count 0 2006.201.20:01:55.48#ibcon#about to write, iclass 24, count 0 2006.201.20:01:55.48#ibcon#wrote, iclass 24, count 0 2006.201.20:01:55.48#ibcon#about to read 3, iclass 24, count 0 2006.201.20:01:55.50#ibcon#read 3, iclass 24, count 0 2006.201.20:01:55.50#ibcon#about to read 4, iclass 24, count 0 2006.201.20:01:55.50#ibcon#read 4, iclass 24, count 0 2006.201.20:01:55.50#ibcon#about to read 5, iclass 24, count 0 2006.201.20:01:55.50#ibcon#read 5, iclass 24, count 0 2006.201.20:01:55.50#ibcon#about to read 6, iclass 24, count 0 2006.201.20:01:55.50#ibcon#read 6, iclass 24, count 0 2006.201.20:01:55.50#ibcon#end of sib2, iclass 24, count 0 2006.201.20:01:55.50#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:01:55.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:01:55.50#ibcon#[25=USB\r\n] 2006.201.20:01:55.50#ibcon#*before write, iclass 24, count 0 2006.201.20:01:55.50#ibcon#enter sib2, iclass 24, count 0 2006.201.20:01:55.50#ibcon#flushed, iclass 24, count 0 2006.201.20:01:55.50#ibcon#about to write, iclass 24, count 0 2006.201.20:01:55.50#ibcon#wrote, iclass 24, count 0 2006.201.20:01:55.50#ibcon#about to read 3, iclass 24, count 0 2006.201.20:01:55.53#ibcon#read 3, iclass 24, count 0 2006.201.20:01:55.53#ibcon#about to read 4, iclass 24, count 0 2006.201.20:01:55.53#ibcon#read 4, iclass 24, count 0 2006.201.20:01:55.53#ibcon#about to read 5, iclass 24, count 0 2006.201.20:01:55.53#ibcon#read 5, iclass 24, count 0 2006.201.20:01:55.53#ibcon#about to read 6, iclass 24, count 0 2006.201.20:01:55.53#ibcon#read 6, iclass 24, count 0 2006.201.20:01:55.53#ibcon#end of sib2, iclass 24, count 0 2006.201.20:01:55.53#ibcon#*after write, iclass 24, count 0 2006.201.20:01:55.53#ibcon#*before return 0, iclass 24, count 0 2006.201.20:01:55.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:55.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:55.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:01:55.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:01:55.53$vck44/valo=6,814.99 2006.201.20:01:55.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.20:01:55.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.20:01:55.53#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:55.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:55.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:55.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:55.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:01:55.53#ibcon#first serial, iclass 26, count 0 2006.201.20:01:55.53#ibcon#enter sib2, iclass 26, count 0 2006.201.20:01:55.53#ibcon#flushed, iclass 26, count 0 2006.201.20:01:55.53#ibcon#about to write, iclass 26, count 0 2006.201.20:01:55.53#ibcon#wrote, iclass 26, count 0 2006.201.20:01:55.53#ibcon#about to read 3, iclass 26, count 0 2006.201.20:01:55.55#ibcon#read 3, iclass 26, count 0 2006.201.20:01:55.55#ibcon#about to read 4, iclass 26, count 0 2006.201.20:01:55.55#ibcon#read 4, iclass 26, count 0 2006.201.20:01:55.55#ibcon#about to read 5, iclass 26, count 0 2006.201.20:01:55.55#ibcon#read 5, iclass 26, count 0 2006.201.20:01:55.55#ibcon#about to read 6, iclass 26, count 0 2006.201.20:01:55.55#ibcon#read 6, iclass 26, count 0 2006.201.20:01:55.55#ibcon#end of sib2, iclass 26, count 0 2006.201.20:01:55.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:01:55.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:01:55.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:01:55.55#ibcon#*before write, iclass 26, count 0 2006.201.20:01:55.55#ibcon#enter sib2, iclass 26, count 0 2006.201.20:01:55.55#ibcon#flushed, iclass 26, count 0 2006.201.20:01:55.55#ibcon#about to write, iclass 26, count 0 2006.201.20:01:55.55#ibcon#wrote, iclass 26, count 0 2006.201.20:01:55.55#ibcon#about to read 3, iclass 26, count 0 2006.201.20:01:55.60#ibcon#read 3, iclass 26, count 0 2006.201.20:01:55.60#ibcon#about to read 4, iclass 26, count 0 2006.201.20:01:55.60#ibcon#read 4, iclass 26, count 0 2006.201.20:01:55.60#ibcon#about to read 5, iclass 26, count 0 2006.201.20:01:55.60#ibcon#read 5, iclass 26, count 0 2006.201.20:01:55.60#ibcon#about to read 6, iclass 26, count 0 2006.201.20:01:55.60#ibcon#read 6, iclass 26, count 0 2006.201.20:01:55.60#ibcon#end of sib2, iclass 26, count 0 2006.201.20:01:55.60#ibcon#*after write, iclass 26, count 0 2006.201.20:01:55.60#ibcon#*before return 0, iclass 26, count 0 2006.201.20:01:55.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:55.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:55.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:01:55.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:01:55.60$vck44/va=6,5 2006.201.20:01:55.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.20:01:55.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.20:01:55.60#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:55.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:55.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:55.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:55.65#ibcon#enter wrdev, iclass 28, count 2 2006.201.20:01:55.65#ibcon#first serial, iclass 28, count 2 2006.201.20:01:55.65#ibcon#enter sib2, iclass 28, count 2 2006.201.20:01:55.65#ibcon#flushed, iclass 28, count 2 2006.201.20:01:55.65#ibcon#about to write, iclass 28, count 2 2006.201.20:01:55.65#ibcon#wrote, iclass 28, count 2 2006.201.20:01:55.65#ibcon#about to read 3, iclass 28, count 2 2006.201.20:01:55.67#ibcon#read 3, iclass 28, count 2 2006.201.20:01:55.67#ibcon#about to read 4, iclass 28, count 2 2006.201.20:01:55.67#ibcon#read 4, iclass 28, count 2 2006.201.20:01:55.67#ibcon#about to read 5, iclass 28, count 2 2006.201.20:01:55.67#ibcon#read 5, iclass 28, count 2 2006.201.20:01:55.67#ibcon#about to read 6, iclass 28, count 2 2006.201.20:01:55.67#ibcon#read 6, iclass 28, count 2 2006.201.20:01:55.67#ibcon#end of sib2, iclass 28, count 2 2006.201.20:01:55.67#ibcon#*mode == 0, iclass 28, count 2 2006.201.20:01:55.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.20:01:55.67#ibcon#[25=AT06-05\r\n] 2006.201.20:01:55.67#ibcon#*before write, iclass 28, count 2 2006.201.20:01:55.67#ibcon#enter sib2, iclass 28, count 2 2006.201.20:01:55.67#ibcon#flushed, iclass 28, count 2 2006.201.20:01:55.67#ibcon#about to write, iclass 28, count 2 2006.201.20:01:55.67#ibcon#wrote, iclass 28, count 2 2006.201.20:01:55.67#ibcon#about to read 3, iclass 28, count 2 2006.201.20:01:55.70#ibcon#read 3, iclass 28, count 2 2006.201.20:01:55.70#ibcon#about to read 4, iclass 28, count 2 2006.201.20:01:55.70#ibcon#read 4, iclass 28, count 2 2006.201.20:01:55.70#ibcon#about to read 5, iclass 28, count 2 2006.201.20:01:55.70#ibcon#read 5, iclass 28, count 2 2006.201.20:01:55.70#ibcon#about to read 6, iclass 28, count 2 2006.201.20:01:55.70#ibcon#read 6, iclass 28, count 2 2006.201.20:01:55.70#ibcon#end of sib2, iclass 28, count 2 2006.201.20:01:55.70#ibcon#*after write, iclass 28, count 2 2006.201.20:01:55.70#ibcon#*before return 0, iclass 28, count 2 2006.201.20:01:55.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:55.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:55.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.20:01:55.70#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:55.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:55.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:55.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:55.82#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:01:55.82#ibcon#first serial, iclass 28, count 0 2006.201.20:01:55.82#ibcon#enter sib2, iclass 28, count 0 2006.201.20:01:55.82#ibcon#flushed, iclass 28, count 0 2006.201.20:01:55.82#ibcon#about to write, iclass 28, count 0 2006.201.20:01:55.82#ibcon#wrote, iclass 28, count 0 2006.201.20:01:55.82#ibcon#about to read 3, iclass 28, count 0 2006.201.20:01:55.84#ibcon#read 3, iclass 28, count 0 2006.201.20:01:55.84#ibcon#about to read 4, iclass 28, count 0 2006.201.20:01:55.84#ibcon#read 4, iclass 28, count 0 2006.201.20:01:55.84#ibcon#about to read 5, iclass 28, count 0 2006.201.20:01:55.84#ibcon#read 5, iclass 28, count 0 2006.201.20:01:55.84#ibcon#about to read 6, iclass 28, count 0 2006.201.20:01:55.84#ibcon#read 6, iclass 28, count 0 2006.201.20:01:55.84#ibcon#end of sib2, iclass 28, count 0 2006.201.20:01:55.84#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:01:55.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:01:55.84#ibcon#[25=USB\r\n] 2006.201.20:01:55.84#ibcon#*before write, iclass 28, count 0 2006.201.20:01:55.84#ibcon#enter sib2, iclass 28, count 0 2006.201.20:01:55.84#ibcon#flushed, iclass 28, count 0 2006.201.20:01:55.84#ibcon#about to write, iclass 28, count 0 2006.201.20:01:55.84#ibcon#wrote, iclass 28, count 0 2006.201.20:01:55.84#ibcon#about to read 3, iclass 28, count 0 2006.201.20:01:55.87#ibcon#read 3, iclass 28, count 0 2006.201.20:01:55.87#ibcon#about to read 4, iclass 28, count 0 2006.201.20:01:55.87#ibcon#read 4, iclass 28, count 0 2006.201.20:01:55.87#ibcon#about to read 5, iclass 28, count 0 2006.201.20:01:55.87#ibcon#read 5, iclass 28, count 0 2006.201.20:01:55.87#ibcon#about to read 6, iclass 28, count 0 2006.201.20:01:55.87#ibcon#read 6, iclass 28, count 0 2006.201.20:01:55.87#ibcon#end of sib2, iclass 28, count 0 2006.201.20:01:55.87#ibcon#*after write, iclass 28, count 0 2006.201.20:01:55.87#ibcon#*before return 0, iclass 28, count 0 2006.201.20:01:55.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:55.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:55.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:01:55.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:01:55.87$vck44/valo=7,864.99 2006.201.20:01:55.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.20:01:55.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.20:01:55.87#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:55.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:55.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:55.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:55.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:01:55.87#ibcon#first serial, iclass 30, count 0 2006.201.20:01:55.87#ibcon#enter sib2, iclass 30, count 0 2006.201.20:01:55.87#ibcon#flushed, iclass 30, count 0 2006.201.20:01:55.87#ibcon#about to write, iclass 30, count 0 2006.201.20:01:55.87#ibcon#wrote, iclass 30, count 0 2006.201.20:01:55.87#ibcon#about to read 3, iclass 30, count 0 2006.201.20:01:55.89#ibcon#read 3, iclass 30, count 0 2006.201.20:01:55.89#ibcon#about to read 4, iclass 30, count 0 2006.201.20:01:55.89#ibcon#read 4, iclass 30, count 0 2006.201.20:01:55.89#ibcon#about to read 5, iclass 30, count 0 2006.201.20:01:55.89#ibcon#read 5, iclass 30, count 0 2006.201.20:01:55.89#ibcon#about to read 6, iclass 30, count 0 2006.201.20:01:55.89#ibcon#read 6, iclass 30, count 0 2006.201.20:01:55.89#ibcon#end of sib2, iclass 30, count 0 2006.201.20:01:55.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:01:55.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:01:55.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:01:55.89#ibcon#*before write, iclass 30, count 0 2006.201.20:01:55.89#ibcon#enter sib2, iclass 30, count 0 2006.201.20:01:55.89#ibcon#flushed, iclass 30, count 0 2006.201.20:01:55.89#ibcon#about to write, iclass 30, count 0 2006.201.20:01:55.89#ibcon#wrote, iclass 30, count 0 2006.201.20:01:55.89#ibcon#about to read 3, iclass 30, count 0 2006.201.20:01:55.93#ibcon#read 3, iclass 30, count 0 2006.201.20:01:55.93#ibcon#about to read 4, iclass 30, count 0 2006.201.20:01:55.93#ibcon#read 4, iclass 30, count 0 2006.201.20:01:55.93#ibcon#about to read 5, iclass 30, count 0 2006.201.20:01:55.93#ibcon#read 5, iclass 30, count 0 2006.201.20:01:55.93#ibcon#about to read 6, iclass 30, count 0 2006.201.20:01:55.93#ibcon#read 6, iclass 30, count 0 2006.201.20:01:55.93#ibcon#end of sib2, iclass 30, count 0 2006.201.20:01:55.93#ibcon#*after write, iclass 30, count 0 2006.201.20:01:55.93#ibcon#*before return 0, iclass 30, count 0 2006.201.20:01:55.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:55.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:55.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:01:55.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:01:55.93$vck44/va=7,5 2006.201.20:01:55.93#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.20:01:55.93#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.20:01:55.93#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:55.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:55.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:55.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:55.99#ibcon#enter wrdev, iclass 32, count 2 2006.201.20:01:55.99#ibcon#first serial, iclass 32, count 2 2006.201.20:01:55.99#ibcon#enter sib2, iclass 32, count 2 2006.201.20:01:55.99#ibcon#flushed, iclass 32, count 2 2006.201.20:01:55.99#ibcon#about to write, iclass 32, count 2 2006.201.20:01:55.99#ibcon#wrote, iclass 32, count 2 2006.201.20:01:55.99#ibcon#about to read 3, iclass 32, count 2 2006.201.20:01:56.01#ibcon#read 3, iclass 32, count 2 2006.201.20:01:56.01#ibcon#about to read 4, iclass 32, count 2 2006.201.20:01:56.01#ibcon#read 4, iclass 32, count 2 2006.201.20:01:56.01#ibcon#about to read 5, iclass 32, count 2 2006.201.20:01:56.01#ibcon#read 5, iclass 32, count 2 2006.201.20:01:56.01#ibcon#about to read 6, iclass 32, count 2 2006.201.20:01:56.01#ibcon#read 6, iclass 32, count 2 2006.201.20:01:56.01#ibcon#end of sib2, iclass 32, count 2 2006.201.20:01:56.01#ibcon#*mode == 0, iclass 32, count 2 2006.201.20:01:56.01#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.20:01:56.01#ibcon#[25=AT07-05\r\n] 2006.201.20:01:56.01#ibcon#*before write, iclass 32, count 2 2006.201.20:01:56.01#ibcon#enter sib2, iclass 32, count 2 2006.201.20:01:56.01#ibcon#flushed, iclass 32, count 2 2006.201.20:01:56.01#ibcon#about to write, iclass 32, count 2 2006.201.20:01:56.01#ibcon#wrote, iclass 32, count 2 2006.201.20:01:56.01#ibcon#about to read 3, iclass 32, count 2 2006.201.20:01:56.04#ibcon#read 3, iclass 32, count 2 2006.201.20:01:56.04#ibcon#about to read 4, iclass 32, count 2 2006.201.20:01:56.04#ibcon#read 4, iclass 32, count 2 2006.201.20:01:56.04#ibcon#about to read 5, iclass 32, count 2 2006.201.20:01:56.04#ibcon#read 5, iclass 32, count 2 2006.201.20:01:56.04#ibcon#about to read 6, iclass 32, count 2 2006.201.20:01:56.04#ibcon#read 6, iclass 32, count 2 2006.201.20:01:56.04#ibcon#end of sib2, iclass 32, count 2 2006.201.20:01:56.04#ibcon#*after write, iclass 32, count 2 2006.201.20:01:56.04#ibcon#*before return 0, iclass 32, count 2 2006.201.20:01:56.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:56.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:56.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.20:01:56.04#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:56.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:56.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:56.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:56.16#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:01:56.16#ibcon#first serial, iclass 32, count 0 2006.201.20:01:56.16#ibcon#enter sib2, iclass 32, count 0 2006.201.20:01:56.16#ibcon#flushed, iclass 32, count 0 2006.201.20:01:56.16#ibcon#about to write, iclass 32, count 0 2006.201.20:01:56.16#ibcon#wrote, iclass 32, count 0 2006.201.20:01:56.16#ibcon#about to read 3, iclass 32, count 0 2006.201.20:01:56.18#ibcon#read 3, iclass 32, count 0 2006.201.20:01:56.18#ibcon#about to read 4, iclass 32, count 0 2006.201.20:01:56.18#ibcon#read 4, iclass 32, count 0 2006.201.20:01:56.18#ibcon#about to read 5, iclass 32, count 0 2006.201.20:01:56.18#ibcon#read 5, iclass 32, count 0 2006.201.20:01:56.18#ibcon#about to read 6, iclass 32, count 0 2006.201.20:01:56.18#ibcon#read 6, iclass 32, count 0 2006.201.20:01:56.18#ibcon#end of sib2, iclass 32, count 0 2006.201.20:01:56.18#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:01:56.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:01:56.18#ibcon#[25=USB\r\n] 2006.201.20:01:56.18#ibcon#*before write, iclass 32, count 0 2006.201.20:01:56.18#ibcon#enter sib2, iclass 32, count 0 2006.201.20:01:56.18#ibcon#flushed, iclass 32, count 0 2006.201.20:01:56.18#ibcon#about to write, iclass 32, count 0 2006.201.20:01:56.18#ibcon#wrote, iclass 32, count 0 2006.201.20:01:56.18#ibcon#about to read 3, iclass 32, count 0 2006.201.20:01:56.21#ibcon#read 3, iclass 32, count 0 2006.201.20:01:56.21#ibcon#about to read 4, iclass 32, count 0 2006.201.20:01:56.21#ibcon#read 4, iclass 32, count 0 2006.201.20:01:56.21#ibcon#about to read 5, iclass 32, count 0 2006.201.20:01:56.21#ibcon#read 5, iclass 32, count 0 2006.201.20:01:56.21#ibcon#about to read 6, iclass 32, count 0 2006.201.20:01:56.21#ibcon#read 6, iclass 32, count 0 2006.201.20:01:56.21#ibcon#end of sib2, iclass 32, count 0 2006.201.20:01:56.21#ibcon#*after write, iclass 32, count 0 2006.201.20:01:56.21#ibcon#*before return 0, iclass 32, count 0 2006.201.20:01:56.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:56.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:56.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:01:56.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:01:56.21$vck44/valo=8,884.99 2006.201.20:01:56.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.20:01:56.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.20:01:56.21#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:56.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:56.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:56.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:56.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:01:56.21#ibcon#first serial, iclass 34, count 0 2006.201.20:01:56.21#ibcon#enter sib2, iclass 34, count 0 2006.201.20:01:56.21#ibcon#flushed, iclass 34, count 0 2006.201.20:01:56.21#ibcon#about to write, iclass 34, count 0 2006.201.20:01:56.21#ibcon#wrote, iclass 34, count 0 2006.201.20:01:56.21#ibcon#about to read 3, iclass 34, count 0 2006.201.20:01:56.23#ibcon#read 3, iclass 34, count 0 2006.201.20:01:56.23#ibcon#about to read 4, iclass 34, count 0 2006.201.20:01:56.23#ibcon#read 4, iclass 34, count 0 2006.201.20:01:56.23#ibcon#about to read 5, iclass 34, count 0 2006.201.20:01:56.23#ibcon#read 5, iclass 34, count 0 2006.201.20:01:56.23#ibcon#about to read 6, iclass 34, count 0 2006.201.20:01:56.23#ibcon#read 6, iclass 34, count 0 2006.201.20:01:56.23#ibcon#end of sib2, iclass 34, count 0 2006.201.20:01:56.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:01:56.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:01:56.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:01:56.23#ibcon#*before write, iclass 34, count 0 2006.201.20:01:56.23#ibcon#enter sib2, iclass 34, count 0 2006.201.20:01:56.23#ibcon#flushed, iclass 34, count 0 2006.201.20:01:56.23#ibcon#about to write, iclass 34, count 0 2006.201.20:01:56.23#ibcon#wrote, iclass 34, count 0 2006.201.20:01:56.23#ibcon#about to read 3, iclass 34, count 0 2006.201.20:01:56.27#ibcon#read 3, iclass 34, count 0 2006.201.20:01:56.27#ibcon#about to read 4, iclass 34, count 0 2006.201.20:01:56.27#ibcon#read 4, iclass 34, count 0 2006.201.20:01:56.27#ibcon#about to read 5, iclass 34, count 0 2006.201.20:01:56.27#ibcon#read 5, iclass 34, count 0 2006.201.20:01:56.27#ibcon#about to read 6, iclass 34, count 0 2006.201.20:01:56.27#ibcon#read 6, iclass 34, count 0 2006.201.20:01:56.27#ibcon#end of sib2, iclass 34, count 0 2006.201.20:01:56.27#ibcon#*after write, iclass 34, count 0 2006.201.20:01:56.27#ibcon#*before return 0, iclass 34, count 0 2006.201.20:01:56.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:56.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:56.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:01:56.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:01:56.27$vck44/va=8,4 2006.201.20:01:56.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.20:01:56.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.20:01:56.27#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:56.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:01:56.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:01:56.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:01:56.33#ibcon#enter wrdev, iclass 36, count 2 2006.201.20:01:56.33#ibcon#first serial, iclass 36, count 2 2006.201.20:01:56.33#ibcon#enter sib2, iclass 36, count 2 2006.201.20:01:56.33#ibcon#flushed, iclass 36, count 2 2006.201.20:01:56.33#ibcon#about to write, iclass 36, count 2 2006.201.20:01:56.33#ibcon#wrote, iclass 36, count 2 2006.201.20:01:56.33#ibcon#about to read 3, iclass 36, count 2 2006.201.20:01:56.35#ibcon#read 3, iclass 36, count 2 2006.201.20:01:56.35#ibcon#about to read 4, iclass 36, count 2 2006.201.20:01:56.35#ibcon#read 4, iclass 36, count 2 2006.201.20:01:56.35#ibcon#about to read 5, iclass 36, count 2 2006.201.20:01:56.35#ibcon#read 5, iclass 36, count 2 2006.201.20:01:56.35#ibcon#about to read 6, iclass 36, count 2 2006.201.20:01:56.35#ibcon#read 6, iclass 36, count 2 2006.201.20:01:56.35#ibcon#end of sib2, iclass 36, count 2 2006.201.20:01:56.35#ibcon#*mode == 0, iclass 36, count 2 2006.201.20:01:56.35#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.20:01:56.35#ibcon#[25=AT08-04\r\n] 2006.201.20:01:56.35#ibcon#*before write, iclass 36, count 2 2006.201.20:01:56.35#ibcon#enter sib2, iclass 36, count 2 2006.201.20:01:56.35#ibcon#flushed, iclass 36, count 2 2006.201.20:01:56.35#ibcon#about to write, iclass 36, count 2 2006.201.20:01:56.35#ibcon#wrote, iclass 36, count 2 2006.201.20:01:56.35#ibcon#about to read 3, iclass 36, count 2 2006.201.20:01:56.38#ibcon#read 3, iclass 36, count 2 2006.201.20:01:56.38#ibcon#about to read 4, iclass 36, count 2 2006.201.20:01:56.38#ibcon#read 4, iclass 36, count 2 2006.201.20:01:56.38#ibcon#about to read 5, iclass 36, count 2 2006.201.20:01:56.38#ibcon#read 5, iclass 36, count 2 2006.201.20:01:56.38#ibcon#about to read 6, iclass 36, count 2 2006.201.20:01:56.38#ibcon#read 6, iclass 36, count 2 2006.201.20:01:56.38#ibcon#end of sib2, iclass 36, count 2 2006.201.20:01:56.38#ibcon#*after write, iclass 36, count 2 2006.201.20:01:56.38#ibcon#*before return 0, iclass 36, count 2 2006.201.20:01:56.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:01:56.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:01:56.38#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.20:01:56.38#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:56.38#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:01:56.50#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:01:56.50#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:01:56.50#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:01:56.50#ibcon#first serial, iclass 36, count 0 2006.201.20:01:56.50#ibcon#enter sib2, iclass 36, count 0 2006.201.20:01:56.50#ibcon#flushed, iclass 36, count 0 2006.201.20:01:56.50#ibcon#about to write, iclass 36, count 0 2006.201.20:01:56.50#ibcon#wrote, iclass 36, count 0 2006.201.20:01:56.50#ibcon#about to read 3, iclass 36, count 0 2006.201.20:01:56.52#ibcon#read 3, iclass 36, count 0 2006.201.20:01:56.52#ibcon#about to read 4, iclass 36, count 0 2006.201.20:01:56.52#ibcon#read 4, iclass 36, count 0 2006.201.20:01:56.52#ibcon#about to read 5, iclass 36, count 0 2006.201.20:01:56.52#ibcon#read 5, iclass 36, count 0 2006.201.20:01:56.52#ibcon#about to read 6, iclass 36, count 0 2006.201.20:01:56.52#ibcon#read 6, iclass 36, count 0 2006.201.20:01:56.52#ibcon#end of sib2, iclass 36, count 0 2006.201.20:01:56.52#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:01:56.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:01:56.52#ibcon#[25=USB\r\n] 2006.201.20:01:56.52#ibcon#*before write, iclass 36, count 0 2006.201.20:01:56.52#ibcon#enter sib2, iclass 36, count 0 2006.201.20:01:56.52#ibcon#flushed, iclass 36, count 0 2006.201.20:01:56.52#ibcon#about to write, iclass 36, count 0 2006.201.20:01:56.52#ibcon#wrote, iclass 36, count 0 2006.201.20:01:56.52#ibcon#about to read 3, iclass 36, count 0 2006.201.20:01:56.55#ibcon#read 3, iclass 36, count 0 2006.201.20:01:56.55#ibcon#about to read 4, iclass 36, count 0 2006.201.20:01:56.55#ibcon#read 4, iclass 36, count 0 2006.201.20:01:56.55#ibcon#about to read 5, iclass 36, count 0 2006.201.20:01:56.55#ibcon#read 5, iclass 36, count 0 2006.201.20:01:56.55#ibcon#about to read 6, iclass 36, count 0 2006.201.20:01:56.55#ibcon#read 6, iclass 36, count 0 2006.201.20:01:56.55#ibcon#end of sib2, iclass 36, count 0 2006.201.20:01:56.55#ibcon#*after write, iclass 36, count 0 2006.201.20:01:56.55#ibcon#*before return 0, iclass 36, count 0 2006.201.20:01:56.55#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:01:56.55#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:01:56.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:01:56.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:01:56.55$vck44/vblo=1,629.99 2006.201.20:01:56.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.20:01:56.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.20:01:56.55#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:56.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:01:56.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:01:56.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:01:56.55#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:01:56.55#ibcon#first serial, iclass 38, count 0 2006.201.20:01:56.55#ibcon#enter sib2, iclass 38, count 0 2006.201.20:01:56.55#ibcon#flushed, iclass 38, count 0 2006.201.20:01:56.55#ibcon#about to write, iclass 38, count 0 2006.201.20:01:56.55#ibcon#wrote, iclass 38, count 0 2006.201.20:01:56.55#ibcon#about to read 3, iclass 38, count 0 2006.201.20:01:56.57#ibcon#read 3, iclass 38, count 0 2006.201.20:01:56.57#ibcon#about to read 4, iclass 38, count 0 2006.201.20:01:56.57#ibcon#read 4, iclass 38, count 0 2006.201.20:01:56.57#ibcon#about to read 5, iclass 38, count 0 2006.201.20:01:56.57#ibcon#read 5, iclass 38, count 0 2006.201.20:01:56.57#ibcon#about to read 6, iclass 38, count 0 2006.201.20:01:56.57#ibcon#read 6, iclass 38, count 0 2006.201.20:01:56.57#ibcon#end of sib2, iclass 38, count 0 2006.201.20:01:56.57#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:01:56.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:01:56.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:01:56.57#ibcon#*before write, iclass 38, count 0 2006.201.20:01:56.57#ibcon#enter sib2, iclass 38, count 0 2006.201.20:01:56.57#ibcon#flushed, iclass 38, count 0 2006.201.20:01:56.57#ibcon#about to write, iclass 38, count 0 2006.201.20:01:56.57#ibcon#wrote, iclass 38, count 0 2006.201.20:01:56.57#ibcon#about to read 3, iclass 38, count 0 2006.201.20:01:56.61#ibcon#read 3, iclass 38, count 0 2006.201.20:01:56.61#ibcon#about to read 4, iclass 38, count 0 2006.201.20:01:56.61#ibcon#read 4, iclass 38, count 0 2006.201.20:01:56.61#ibcon#about to read 5, iclass 38, count 0 2006.201.20:01:56.61#ibcon#read 5, iclass 38, count 0 2006.201.20:01:56.61#ibcon#about to read 6, iclass 38, count 0 2006.201.20:01:56.61#ibcon#read 6, iclass 38, count 0 2006.201.20:01:56.61#ibcon#end of sib2, iclass 38, count 0 2006.201.20:01:56.61#ibcon#*after write, iclass 38, count 0 2006.201.20:01:56.61#ibcon#*before return 0, iclass 38, count 0 2006.201.20:01:56.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:01:56.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:01:56.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:01:56.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:01:56.61$vck44/vb=1,4 2006.201.20:01:56.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.20:01:56.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.20:01:56.61#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:56.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:01:56.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:01:56.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:01:56.61#ibcon#enter wrdev, iclass 40, count 2 2006.201.20:01:56.61#ibcon#first serial, iclass 40, count 2 2006.201.20:01:56.61#ibcon#enter sib2, iclass 40, count 2 2006.201.20:01:56.61#ibcon#flushed, iclass 40, count 2 2006.201.20:01:56.61#ibcon#about to write, iclass 40, count 2 2006.201.20:01:56.61#ibcon#wrote, iclass 40, count 2 2006.201.20:01:56.61#ibcon#about to read 3, iclass 40, count 2 2006.201.20:01:56.63#ibcon#read 3, iclass 40, count 2 2006.201.20:01:56.63#ibcon#about to read 4, iclass 40, count 2 2006.201.20:01:56.63#ibcon#read 4, iclass 40, count 2 2006.201.20:01:56.63#ibcon#about to read 5, iclass 40, count 2 2006.201.20:01:56.63#ibcon#read 5, iclass 40, count 2 2006.201.20:01:56.63#ibcon#about to read 6, iclass 40, count 2 2006.201.20:01:56.63#ibcon#read 6, iclass 40, count 2 2006.201.20:01:56.63#ibcon#end of sib2, iclass 40, count 2 2006.201.20:01:56.63#ibcon#*mode == 0, iclass 40, count 2 2006.201.20:01:56.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.20:01:56.63#ibcon#[27=AT01-04\r\n] 2006.201.20:01:56.63#ibcon#*before write, iclass 40, count 2 2006.201.20:01:56.63#ibcon#enter sib2, iclass 40, count 2 2006.201.20:01:56.63#ibcon#flushed, iclass 40, count 2 2006.201.20:01:56.63#ibcon#about to write, iclass 40, count 2 2006.201.20:01:56.63#ibcon#wrote, iclass 40, count 2 2006.201.20:01:56.63#ibcon#about to read 3, iclass 40, count 2 2006.201.20:01:56.66#ibcon#read 3, iclass 40, count 2 2006.201.20:01:56.66#ibcon#about to read 4, iclass 40, count 2 2006.201.20:01:56.66#ibcon#read 4, iclass 40, count 2 2006.201.20:01:56.66#ibcon#about to read 5, iclass 40, count 2 2006.201.20:01:56.66#ibcon#read 5, iclass 40, count 2 2006.201.20:01:56.66#ibcon#about to read 6, iclass 40, count 2 2006.201.20:01:56.66#ibcon#read 6, iclass 40, count 2 2006.201.20:01:56.66#ibcon#end of sib2, iclass 40, count 2 2006.201.20:01:56.66#ibcon#*after write, iclass 40, count 2 2006.201.20:01:56.66#ibcon#*before return 0, iclass 40, count 2 2006.201.20:01:56.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:01:56.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:01:56.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.20:01:56.66#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:56.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:01:56.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:01:56.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:01:56.78#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:01:56.78#ibcon#first serial, iclass 40, count 0 2006.201.20:01:56.78#ibcon#enter sib2, iclass 40, count 0 2006.201.20:01:56.78#ibcon#flushed, iclass 40, count 0 2006.201.20:01:56.78#ibcon#about to write, iclass 40, count 0 2006.201.20:01:56.78#ibcon#wrote, iclass 40, count 0 2006.201.20:01:56.78#ibcon#about to read 3, iclass 40, count 0 2006.201.20:01:56.80#ibcon#read 3, iclass 40, count 0 2006.201.20:01:56.80#ibcon#about to read 4, iclass 40, count 0 2006.201.20:01:56.80#ibcon#read 4, iclass 40, count 0 2006.201.20:01:56.80#ibcon#about to read 5, iclass 40, count 0 2006.201.20:01:56.80#ibcon#read 5, iclass 40, count 0 2006.201.20:01:56.80#ibcon#about to read 6, iclass 40, count 0 2006.201.20:01:56.80#ibcon#read 6, iclass 40, count 0 2006.201.20:01:56.80#ibcon#end of sib2, iclass 40, count 0 2006.201.20:01:56.80#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:01:56.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:01:56.80#ibcon#[27=USB\r\n] 2006.201.20:01:56.80#ibcon#*before write, iclass 40, count 0 2006.201.20:01:56.80#ibcon#enter sib2, iclass 40, count 0 2006.201.20:01:56.80#ibcon#flushed, iclass 40, count 0 2006.201.20:01:56.80#ibcon#about to write, iclass 40, count 0 2006.201.20:01:56.80#ibcon#wrote, iclass 40, count 0 2006.201.20:01:56.80#ibcon#about to read 3, iclass 40, count 0 2006.201.20:01:56.83#ibcon#read 3, iclass 40, count 0 2006.201.20:01:56.83#ibcon#about to read 4, iclass 40, count 0 2006.201.20:01:56.83#ibcon#read 4, iclass 40, count 0 2006.201.20:01:56.83#ibcon#about to read 5, iclass 40, count 0 2006.201.20:01:56.83#ibcon#read 5, iclass 40, count 0 2006.201.20:01:56.83#ibcon#about to read 6, iclass 40, count 0 2006.201.20:01:56.83#ibcon#read 6, iclass 40, count 0 2006.201.20:01:56.83#ibcon#end of sib2, iclass 40, count 0 2006.201.20:01:56.83#ibcon#*after write, iclass 40, count 0 2006.201.20:01:56.83#ibcon#*before return 0, iclass 40, count 0 2006.201.20:01:56.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:01:56.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:01:56.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:01:56.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:01:56.83$vck44/vblo=2,634.99 2006.201.20:01:56.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.20:01:56.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.20:01:56.83#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:56.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:56.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:56.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:56.83#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:01:56.83#ibcon#first serial, iclass 4, count 0 2006.201.20:01:56.83#ibcon#enter sib2, iclass 4, count 0 2006.201.20:01:56.83#ibcon#flushed, iclass 4, count 0 2006.201.20:01:56.83#ibcon#about to write, iclass 4, count 0 2006.201.20:01:56.83#ibcon#wrote, iclass 4, count 0 2006.201.20:01:56.83#ibcon#about to read 3, iclass 4, count 0 2006.201.20:01:56.85#ibcon#read 3, iclass 4, count 0 2006.201.20:01:56.85#ibcon#about to read 4, iclass 4, count 0 2006.201.20:01:56.85#ibcon#read 4, iclass 4, count 0 2006.201.20:01:56.85#ibcon#about to read 5, iclass 4, count 0 2006.201.20:01:56.85#ibcon#read 5, iclass 4, count 0 2006.201.20:01:56.85#ibcon#about to read 6, iclass 4, count 0 2006.201.20:01:56.85#ibcon#read 6, iclass 4, count 0 2006.201.20:01:56.85#ibcon#end of sib2, iclass 4, count 0 2006.201.20:01:56.85#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:01:56.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:01:56.85#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:01:56.85#ibcon#*before write, iclass 4, count 0 2006.201.20:01:56.85#ibcon#enter sib2, iclass 4, count 0 2006.201.20:01:56.85#ibcon#flushed, iclass 4, count 0 2006.201.20:01:56.85#ibcon#about to write, iclass 4, count 0 2006.201.20:01:56.85#ibcon#wrote, iclass 4, count 0 2006.201.20:01:56.85#ibcon#about to read 3, iclass 4, count 0 2006.201.20:01:56.89#ibcon#read 3, iclass 4, count 0 2006.201.20:01:56.89#ibcon#about to read 4, iclass 4, count 0 2006.201.20:01:56.89#ibcon#read 4, iclass 4, count 0 2006.201.20:01:56.89#ibcon#about to read 5, iclass 4, count 0 2006.201.20:01:56.89#ibcon#read 5, iclass 4, count 0 2006.201.20:01:56.89#ibcon#about to read 6, iclass 4, count 0 2006.201.20:01:56.89#ibcon#read 6, iclass 4, count 0 2006.201.20:01:56.89#ibcon#end of sib2, iclass 4, count 0 2006.201.20:01:56.89#ibcon#*after write, iclass 4, count 0 2006.201.20:01:56.89#ibcon#*before return 0, iclass 4, count 0 2006.201.20:01:56.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:56.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:01:56.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:01:56.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:01:56.89$vck44/vb=2,5 2006.201.20:01:56.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.20:01:56.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.20:01:56.89#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:56.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:56.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:56.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:56.95#ibcon#enter wrdev, iclass 6, count 2 2006.201.20:01:56.95#ibcon#first serial, iclass 6, count 2 2006.201.20:01:56.95#ibcon#enter sib2, iclass 6, count 2 2006.201.20:01:56.95#ibcon#flushed, iclass 6, count 2 2006.201.20:01:56.95#ibcon#about to write, iclass 6, count 2 2006.201.20:01:56.95#ibcon#wrote, iclass 6, count 2 2006.201.20:01:56.95#ibcon#about to read 3, iclass 6, count 2 2006.201.20:01:56.97#ibcon#read 3, iclass 6, count 2 2006.201.20:01:56.97#ibcon#about to read 4, iclass 6, count 2 2006.201.20:01:56.97#ibcon#read 4, iclass 6, count 2 2006.201.20:01:56.97#ibcon#about to read 5, iclass 6, count 2 2006.201.20:01:56.97#ibcon#read 5, iclass 6, count 2 2006.201.20:01:56.97#ibcon#about to read 6, iclass 6, count 2 2006.201.20:01:56.97#ibcon#read 6, iclass 6, count 2 2006.201.20:01:56.97#ibcon#end of sib2, iclass 6, count 2 2006.201.20:01:56.97#ibcon#*mode == 0, iclass 6, count 2 2006.201.20:01:56.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.20:01:56.97#ibcon#[27=AT02-05\r\n] 2006.201.20:01:56.97#ibcon#*before write, iclass 6, count 2 2006.201.20:01:56.97#ibcon#enter sib2, iclass 6, count 2 2006.201.20:01:56.97#ibcon#flushed, iclass 6, count 2 2006.201.20:01:56.97#ibcon#about to write, iclass 6, count 2 2006.201.20:01:56.97#ibcon#wrote, iclass 6, count 2 2006.201.20:01:56.97#ibcon#about to read 3, iclass 6, count 2 2006.201.20:01:57.00#ibcon#read 3, iclass 6, count 2 2006.201.20:01:57.00#ibcon#about to read 4, iclass 6, count 2 2006.201.20:01:57.00#ibcon#read 4, iclass 6, count 2 2006.201.20:01:57.00#ibcon#about to read 5, iclass 6, count 2 2006.201.20:01:57.00#ibcon#read 5, iclass 6, count 2 2006.201.20:01:57.00#ibcon#about to read 6, iclass 6, count 2 2006.201.20:01:57.00#ibcon#read 6, iclass 6, count 2 2006.201.20:01:57.00#ibcon#end of sib2, iclass 6, count 2 2006.201.20:01:57.00#ibcon#*after write, iclass 6, count 2 2006.201.20:01:57.00#ibcon#*before return 0, iclass 6, count 2 2006.201.20:01:57.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:57.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:01:57.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.20:01:57.00#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:57.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:57.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:57.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:57.12#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:01:57.12#ibcon#first serial, iclass 6, count 0 2006.201.20:01:57.12#ibcon#enter sib2, iclass 6, count 0 2006.201.20:01:57.12#ibcon#flushed, iclass 6, count 0 2006.201.20:01:57.12#ibcon#about to write, iclass 6, count 0 2006.201.20:01:57.12#ibcon#wrote, iclass 6, count 0 2006.201.20:01:57.12#ibcon#about to read 3, iclass 6, count 0 2006.201.20:01:57.14#ibcon#read 3, iclass 6, count 0 2006.201.20:01:57.14#ibcon#about to read 4, iclass 6, count 0 2006.201.20:01:57.14#ibcon#read 4, iclass 6, count 0 2006.201.20:01:57.14#ibcon#about to read 5, iclass 6, count 0 2006.201.20:01:57.14#ibcon#read 5, iclass 6, count 0 2006.201.20:01:57.14#ibcon#about to read 6, iclass 6, count 0 2006.201.20:01:57.14#ibcon#read 6, iclass 6, count 0 2006.201.20:01:57.14#ibcon#end of sib2, iclass 6, count 0 2006.201.20:01:57.14#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:01:57.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:01:57.14#ibcon#[27=USB\r\n] 2006.201.20:01:57.14#ibcon#*before write, iclass 6, count 0 2006.201.20:01:57.14#ibcon#enter sib2, iclass 6, count 0 2006.201.20:01:57.14#ibcon#flushed, iclass 6, count 0 2006.201.20:01:57.14#ibcon#about to write, iclass 6, count 0 2006.201.20:01:57.14#ibcon#wrote, iclass 6, count 0 2006.201.20:01:57.14#ibcon#about to read 3, iclass 6, count 0 2006.201.20:01:57.17#ibcon#read 3, iclass 6, count 0 2006.201.20:01:57.17#ibcon#about to read 4, iclass 6, count 0 2006.201.20:01:57.17#ibcon#read 4, iclass 6, count 0 2006.201.20:01:57.17#ibcon#about to read 5, iclass 6, count 0 2006.201.20:01:57.17#ibcon#read 5, iclass 6, count 0 2006.201.20:01:57.17#ibcon#about to read 6, iclass 6, count 0 2006.201.20:01:57.17#ibcon#read 6, iclass 6, count 0 2006.201.20:01:57.17#ibcon#end of sib2, iclass 6, count 0 2006.201.20:01:57.17#ibcon#*after write, iclass 6, count 0 2006.201.20:01:57.17#ibcon#*before return 0, iclass 6, count 0 2006.201.20:01:57.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:57.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:01:57.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:01:57.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:01:57.17$vck44/vblo=3,649.99 2006.201.20:01:57.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.20:01:57.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.20:01:57.17#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:57.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:57.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:57.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:57.17#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:01:57.17#ibcon#first serial, iclass 10, count 0 2006.201.20:01:57.17#ibcon#enter sib2, iclass 10, count 0 2006.201.20:01:57.17#ibcon#flushed, iclass 10, count 0 2006.201.20:01:57.17#ibcon#about to write, iclass 10, count 0 2006.201.20:01:57.17#ibcon#wrote, iclass 10, count 0 2006.201.20:01:57.17#ibcon#about to read 3, iclass 10, count 0 2006.201.20:01:57.19#ibcon#read 3, iclass 10, count 0 2006.201.20:01:57.19#ibcon#about to read 4, iclass 10, count 0 2006.201.20:01:57.19#ibcon#read 4, iclass 10, count 0 2006.201.20:01:57.19#ibcon#about to read 5, iclass 10, count 0 2006.201.20:01:57.19#ibcon#read 5, iclass 10, count 0 2006.201.20:01:57.19#ibcon#about to read 6, iclass 10, count 0 2006.201.20:01:57.19#ibcon#read 6, iclass 10, count 0 2006.201.20:01:57.19#ibcon#end of sib2, iclass 10, count 0 2006.201.20:01:57.19#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:01:57.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:01:57.19#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:01:57.19#ibcon#*before write, iclass 10, count 0 2006.201.20:01:57.19#ibcon#enter sib2, iclass 10, count 0 2006.201.20:01:57.19#ibcon#flushed, iclass 10, count 0 2006.201.20:01:57.19#ibcon#about to write, iclass 10, count 0 2006.201.20:01:57.19#ibcon#wrote, iclass 10, count 0 2006.201.20:01:57.19#ibcon#about to read 3, iclass 10, count 0 2006.201.20:01:57.24#ibcon#read 3, iclass 10, count 0 2006.201.20:01:57.24#ibcon#about to read 4, iclass 10, count 0 2006.201.20:01:57.24#ibcon#read 4, iclass 10, count 0 2006.201.20:01:57.24#ibcon#about to read 5, iclass 10, count 0 2006.201.20:01:57.24#ibcon#read 5, iclass 10, count 0 2006.201.20:01:57.24#ibcon#about to read 6, iclass 10, count 0 2006.201.20:01:57.24#ibcon#read 6, iclass 10, count 0 2006.201.20:01:57.24#ibcon#end of sib2, iclass 10, count 0 2006.201.20:01:57.24#ibcon#*after write, iclass 10, count 0 2006.201.20:01:57.24#ibcon#*before return 0, iclass 10, count 0 2006.201.20:01:57.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:57.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:01:57.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:01:57.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:01:57.24$vck44/vb=3,4 2006.201.20:01:57.24#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.20:01:57.24#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.20:01:57.24#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:57.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:57.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:57.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:57.29#ibcon#enter wrdev, iclass 12, count 2 2006.201.20:01:57.29#ibcon#first serial, iclass 12, count 2 2006.201.20:01:57.29#ibcon#enter sib2, iclass 12, count 2 2006.201.20:01:57.29#ibcon#flushed, iclass 12, count 2 2006.201.20:01:57.29#ibcon#about to write, iclass 12, count 2 2006.201.20:01:57.29#ibcon#wrote, iclass 12, count 2 2006.201.20:01:57.29#ibcon#about to read 3, iclass 12, count 2 2006.201.20:01:57.31#ibcon#read 3, iclass 12, count 2 2006.201.20:01:57.31#ibcon#about to read 4, iclass 12, count 2 2006.201.20:01:57.31#ibcon#read 4, iclass 12, count 2 2006.201.20:01:57.31#ibcon#about to read 5, iclass 12, count 2 2006.201.20:01:57.31#ibcon#read 5, iclass 12, count 2 2006.201.20:01:57.31#ibcon#about to read 6, iclass 12, count 2 2006.201.20:01:57.31#ibcon#read 6, iclass 12, count 2 2006.201.20:01:57.31#ibcon#end of sib2, iclass 12, count 2 2006.201.20:01:57.31#ibcon#*mode == 0, iclass 12, count 2 2006.201.20:01:57.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.20:01:57.31#ibcon#[27=AT03-04\r\n] 2006.201.20:01:57.31#ibcon#*before write, iclass 12, count 2 2006.201.20:01:57.31#ibcon#enter sib2, iclass 12, count 2 2006.201.20:01:57.31#ibcon#flushed, iclass 12, count 2 2006.201.20:01:57.31#ibcon#about to write, iclass 12, count 2 2006.201.20:01:57.31#ibcon#wrote, iclass 12, count 2 2006.201.20:01:57.31#ibcon#about to read 3, iclass 12, count 2 2006.201.20:01:57.34#ibcon#read 3, iclass 12, count 2 2006.201.20:01:57.34#ibcon#about to read 4, iclass 12, count 2 2006.201.20:01:57.34#ibcon#read 4, iclass 12, count 2 2006.201.20:01:57.34#ibcon#about to read 5, iclass 12, count 2 2006.201.20:01:57.34#ibcon#read 5, iclass 12, count 2 2006.201.20:01:57.34#ibcon#about to read 6, iclass 12, count 2 2006.201.20:01:57.34#ibcon#read 6, iclass 12, count 2 2006.201.20:01:57.34#ibcon#end of sib2, iclass 12, count 2 2006.201.20:01:57.34#ibcon#*after write, iclass 12, count 2 2006.201.20:01:57.34#ibcon#*before return 0, iclass 12, count 2 2006.201.20:01:57.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:57.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:01:57.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.20:01:57.34#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:57.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:57.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:57.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:57.46#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:01:57.46#ibcon#first serial, iclass 12, count 0 2006.201.20:01:57.46#ibcon#enter sib2, iclass 12, count 0 2006.201.20:01:57.46#ibcon#flushed, iclass 12, count 0 2006.201.20:01:57.46#ibcon#about to write, iclass 12, count 0 2006.201.20:01:57.46#ibcon#wrote, iclass 12, count 0 2006.201.20:01:57.46#ibcon#about to read 3, iclass 12, count 0 2006.201.20:01:57.48#ibcon#read 3, iclass 12, count 0 2006.201.20:01:57.48#ibcon#about to read 4, iclass 12, count 0 2006.201.20:01:57.48#ibcon#read 4, iclass 12, count 0 2006.201.20:01:57.48#ibcon#about to read 5, iclass 12, count 0 2006.201.20:01:57.48#ibcon#read 5, iclass 12, count 0 2006.201.20:01:57.48#ibcon#about to read 6, iclass 12, count 0 2006.201.20:01:57.48#ibcon#read 6, iclass 12, count 0 2006.201.20:01:57.48#ibcon#end of sib2, iclass 12, count 0 2006.201.20:01:57.48#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:01:57.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:01:57.48#ibcon#[27=USB\r\n] 2006.201.20:01:57.48#ibcon#*before write, iclass 12, count 0 2006.201.20:01:57.48#ibcon#enter sib2, iclass 12, count 0 2006.201.20:01:57.48#ibcon#flushed, iclass 12, count 0 2006.201.20:01:57.48#ibcon#about to write, iclass 12, count 0 2006.201.20:01:57.48#ibcon#wrote, iclass 12, count 0 2006.201.20:01:57.48#ibcon#about to read 3, iclass 12, count 0 2006.201.20:01:57.51#ibcon#read 3, iclass 12, count 0 2006.201.20:01:57.51#ibcon#about to read 4, iclass 12, count 0 2006.201.20:01:57.51#ibcon#read 4, iclass 12, count 0 2006.201.20:01:57.51#ibcon#about to read 5, iclass 12, count 0 2006.201.20:01:57.51#ibcon#read 5, iclass 12, count 0 2006.201.20:01:57.51#ibcon#about to read 6, iclass 12, count 0 2006.201.20:01:57.51#ibcon#read 6, iclass 12, count 0 2006.201.20:01:57.51#ibcon#end of sib2, iclass 12, count 0 2006.201.20:01:57.51#ibcon#*after write, iclass 12, count 0 2006.201.20:01:57.51#ibcon#*before return 0, iclass 12, count 0 2006.201.20:01:57.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:57.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:01:57.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:01:57.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:01:57.51$vck44/vblo=4,679.99 2006.201.20:01:57.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.20:01:57.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.20:01:57.51#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:57.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:57.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:57.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:57.51#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:01:57.51#ibcon#first serial, iclass 14, count 0 2006.201.20:01:57.51#ibcon#enter sib2, iclass 14, count 0 2006.201.20:01:57.51#ibcon#flushed, iclass 14, count 0 2006.201.20:01:57.51#ibcon#about to write, iclass 14, count 0 2006.201.20:01:57.51#ibcon#wrote, iclass 14, count 0 2006.201.20:01:57.51#ibcon#about to read 3, iclass 14, count 0 2006.201.20:01:57.53#ibcon#read 3, iclass 14, count 0 2006.201.20:01:57.53#ibcon#about to read 4, iclass 14, count 0 2006.201.20:01:57.53#ibcon#read 4, iclass 14, count 0 2006.201.20:01:57.53#ibcon#about to read 5, iclass 14, count 0 2006.201.20:01:57.53#ibcon#read 5, iclass 14, count 0 2006.201.20:01:57.53#ibcon#about to read 6, iclass 14, count 0 2006.201.20:01:57.53#ibcon#read 6, iclass 14, count 0 2006.201.20:01:57.53#ibcon#end of sib2, iclass 14, count 0 2006.201.20:01:57.53#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:01:57.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:01:57.53#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:01:57.53#ibcon#*before write, iclass 14, count 0 2006.201.20:01:57.53#ibcon#enter sib2, iclass 14, count 0 2006.201.20:01:57.53#ibcon#flushed, iclass 14, count 0 2006.201.20:01:57.53#ibcon#about to write, iclass 14, count 0 2006.201.20:01:57.53#ibcon#wrote, iclass 14, count 0 2006.201.20:01:57.53#ibcon#about to read 3, iclass 14, count 0 2006.201.20:01:57.57#ibcon#read 3, iclass 14, count 0 2006.201.20:01:57.57#ibcon#about to read 4, iclass 14, count 0 2006.201.20:01:57.57#ibcon#read 4, iclass 14, count 0 2006.201.20:01:57.57#ibcon#about to read 5, iclass 14, count 0 2006.201.20:01:57.57#ibcon#read 5, iclass 14, count 0 2006.201.20:01:57.57#ibcon#about to read 6, iclass 14, count 0 2006.201.20:01:57.57#ibcon#read 6, iclass 14, count 0 2006.201.20:01:57.57#ibcon#end of sib2, iclass 14, count 0 2006.201.20:01:57.57#ibcon#*after write, iclass 14, count 0 2006.201.20:01:57.57#ibcon#*before return 0, iclass 14, count 0 2006.201.20:01:57.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:57.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:01:57.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:01:57.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:01:57.57$vck44/vb=4,5 2006.201.20:01:57.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.20:01:57.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.20:01:57.57#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:57.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:57.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:57.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:57.63#ibcon#enter wrdev, iclass 16, count 2 2006.201.20:01:57.63#ibcon#first serial, iclass 16, count 2 2006.201.20:01:57.63#ibcon#enter sib2, iclass 16, count 2 2006.201.20:01:57.63#ibcon#flushed, iclass 16, count 2 2006.201.20:01:57.63#ibcon#about to write, iclass 16, count 2 2006.201.20:01:57.63#ibcon#wrote, iclass 16, count 2 2006.201.20:01:57.63#ibcon#about to read 3, iclass 16, count 2 2006.201.20:01:57.65#ibcon#read 3, iclass 16, count 2 2006.201.20:01:57.65#ibcon#about to read 4, iclass 16, count 2 2006.201.20:01:57.65#ibcon#read 4, iclass 16, count 2 2006.201.20:01:57.65#ibcon#about to read 5, iclass 16, count 2 2006.201.20:01:57.65#ibcon#read 5, iclass 16, count 2 2006.201.20:01:57.65#ibcon#about to read 6, iclass 16, count 2 2006.201.20:01:57.65#ibcon#read 6, iclass 16, count 2 2006.201.20:01:57.65#ibcon#end of sib2, iclass 16, count 2 2006.201.20:01:57.65#ibcon#*mode == 0, iclass 16, count 2 2006.201.20:01:57.65#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.20:01:57.65#ibcon#[27=AT04-05\r\n] 2006.201.20:01:57.65#ibcon#*before write, iclass 16, count 2 2006.201.20:01:57.65#ibcon#enter sib2, iclass 16, count 2 2006.201.20:01:57.65#ibcon#flushed, iclass 16, count 2 2006.201.20:01:57.65#ibcon#about to write, iclass 16, count 2 2006.201.20:01:57.65#ibcon#wrote, iclass 16, count 2 2006.201.20:01:57.65#ibcon#about to read 3, iclass 16, count 2 2006.201.20:01:57.68#ibcon#read 3, iclass 16, count 2 2006.201.20:01:57.68#ibcon#about to read 4, iclass 16, count 2 2006.201.20:01:57.68#ibcon#read 4, iclass 16, count 2 2006.201.20:01:57.68#ibcon#about to read 5, iclass 16, count 2 2006.201.20:01:57.68#ibcon#read 5, iclass 16, count 2 2006.201.20:01:57.68#ibcon#about to read 6, iclass 16, count 2 2006.201.20:01:57.68#ibcon#read 6, iclass 16, count 2 2006.201.20:01:57.68#ibcon#end of sib2, iclass 16, count 2 2006.201.20:01:57.68#ibcon#*after write, iclass 16, count 2 2006.201.20:01:57.68#ibcon#*before return 0, iclass 16, count 2 2006.201.20:01:57.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:57.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:01:57.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.20:01:57.68#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:57.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:57.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:57.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:57.80#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:01:57.80#ibcon#first serial, iclass 16, count 0 2006.201.20:01:57.80#ibcon#enter sib2, iclass 16, count 0 2006.201.20:01:57.80#ibcon#flushed, iclass 16, count 0 2006.201.20:01:57.80#ibcon#about to write, iclass 16, count 0 2006.201.20:01:57.80#ibcon#wrote, iclass 16, count 0 2006.201.20:01:57.80#ibcon#about to read 3, iclass 16, count 0 2006.201.20:01:57.82#ibcon#read 3, iclass 16, count 0 2006.201.20:01:57.82#ibcon#about to read 4, iclass 16, count 0 2006.201.20:01:57.82#ibcon#read 4, iclass 16, count 0 2006.201.20:01:57.82#ibcon#about to read 5, iclass 16, count 0 2006.201.20:01:57.82#ibcon#read 5, iclass 16, count 0 2006.201.20:01:57.82#ibcon#about to read 6, iclass 16, count 0 2006.201.20:01:57.82#ibcon#read 6, iclass 16, count 0 2006.201.20:01:57.82#ibcon#end of sib2, iclass 16, count 0 2006.201.20:01:57.82#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:01:57.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:01:57.82#ibcon#[27=USB\r\n] 2006.201.20:01:57.82#ibcon#*before write, iclass 16, count 0 2006.201.20:01:57.82#ibcon#enter sib2, iclass 16, count 0 2006.201.20:01:57.82#ibcon#flushed, iclass 16, count 0 2006.201.20:01:57.82#ibcon#about to write, iclass 16, count 0 2006.201.20:01:57.82#ibcon#wrote, iclass 16, count 0 2006.201.20:01:57.82#ibcon#about to read 3, iclass 16, count 0 2006.201.20:01:57.85#ibcon#read 3, iclass 16, count 0 2006.201.20:01:57.85#ibcon#about to read 4, iclass 16, count 0 2006.201.20:01:57.85#ibcon#read 4, iclass 16, count 0 2006.201.20:01:57.85#ibcon#about to read 5, iclass 16, count 0 2006.201.20:01:57.85#ibcon#read 5, iclass 16, count 0 2006.201.20:01:57.85#ibcon#about to read 6, iclass 16, count 0 2006.201.20:01:57.85#ibcon#read 6, iclass 16, count 0 2006.201.20:01:57.85#ibcon#end of sib2, iclass 16, count 0 2006.201.20:01:57.85#ibcon#*after write, iclass 16, count 0 2006.201.20:01:57.85#ibcon#*before return 0, iclass 16, count 0 2006.201.20:01:57.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:57.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:01:57.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:01:57.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:01:57.85$vck44/vblo=5,709.99 2006.201.20:01:57.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.20:01:57.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.20:01:57.85#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:57.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:57.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:57.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:57.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:01:57.85#ibcon#first serial, iclass 18, count 0 2006.201.20:01:57.85#ibcon#enter sib2, iclass 18, count 0 2006.201.20:01:57.85#ibcon#flushed, iclass 18, count 0 2006.201.20:01:57.85#ibcon#about to write, iclass 18, count 0 2006.201.20:01:57.85#ibcon#wrote, iclass 18, count 0 2006.201.20:01:57.85#ibcon#about to read 3, iclass 18, count 0 2006.201.20:01:57.87#ibcon#read 3, iclass 18, count 0 2006.201.20:01:57.87#ibcon#about to read 4, iclass 18, count 0 2006.201.20:01:57.87#ibcon#read 4, iclass 18, count 0 2006.201.20:01:57.87#ibcon#about to read 5, iclass 18, count 0 2006.201.20:01:57.87#ibcon#read 5, iclass 18, count 0 2006.201.20:01:57.87#ibcon#about to read 6, iclass 18, count 0 2006.201.20:01:57.87#ibcon#read 6, iclass 18, count 0 2006.201.20:01:57.87#ibcon#end of sib2, iclass 18, count 0 2006.201.20:01:57.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:01:57.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:01:57.87#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:01:57.87#ibcon#*before write, iclass 18, count 0 2006.201.20:01:57.87#ibcon#enter sib2, iclass 18, count 0 2006.201.20:01:57.87#ibcon#flushed, iclass 18, count 0 2006.201.20:01:57.87#ibcon#about to write, iclass 18, count 0 2006.201.20:01:57.87#ibcon#wrote, iclass 18, count 0 2006.201.20:01:57.87#ibcon#about to read 3, iclass 18, count 0 2006.201.20:01:57.92#ibcon#read 3, iclass 18, count 0 2006.201.20:01:57.92#ibcon#about to read 4, iclass 18, count 0 2006.201.20:01:57.92#ibcon#read 4, iclass 18, count 0 2006.201.20:01:57.92#ibcon#about to read 5, iclass 18, count 0 2006.201.20:01:57.92#ibcon#read 5, iclass 18, count 0 2006.201.20:01:57.92#ibcon#about to read 6, iclass 18, count 0 2006.201.20:01:57.92#ibcon#read 6, iclass 18, count 0 2006.201.20:01:57.92#ibcon#end of sib2, iclass 18, count 0 2006.201.20:01:57.92#ibcon#*after write, iclass 18, count 0 2006.201.20:01:57.92#ibcon#*before return 0, iclass 18, count 0 2006.201.20:01:57.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:57.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:01:57.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:01:57.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:01:57.92$vck44/vb=5,4 2006.201.20:01:57.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.20:01:57.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.20:01:57.92#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:57.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:57.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:57.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:57.97#ibcon#enter wrdev, iclass 20, count 2 2006.201.20:01:57.97#ibcon#first serial, iclass 20, count 2 2006.201.20:01:57.97#ibcon#enter sib2, iclass 20, count 2 2006.201.20:01:57.97#ibcon#flushed, iclass 20, count 2 2006.201.20:01:57.97#ibcon#about to write, iclass 20, count 2 2006.201.20:01:57.97#ibcon#wrote, iclass 20, count 2 2006.201.20:01:57.97#ibcon#about to read 3, iclass 20, count 2 2006.201.20:01:57.99#ibcon#read 3, iclass 20, count 2 2006.201.20:01:57.99#ibcon#about to read 4, iclass 20, count 2 2006.201.20:01:57.99#ibcon#read 4, iclass 20, count 2 2006.201.20:01:57.99#ibcon#about to read 5, iclass 20, count 2 2006.201.20:01:57.99#ibcon#read 5, iclass 20, count 2 2006.201.20:01:57.99#ibcon#about to read 6, iclass 20, count 2 2006.201.20:01:57.99#ibcon#read 6, iclass 20, count 2 2006.201.20:01:57.99#ibcon#end of sib2, iclass 20, count 2 2006.201.20:01:57.99#ibcon#*mode == 0, iclass 20, count 2 2006.201.20:01:57.99#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.20:01:57.99#ibcon#[27=AT05-04\r\n] 2006.201.20:01:57.99#ibcon#*before write, iclass 20, count 2 2006.201.20:01:57.99#ibcon#enter sib2, iclass 20, count 2 2006.201.20:01:57.99#ibcon#flushed, iclass 20, count 2 2006.201.20:01:57.99#ibcon#about to write, iclass 20, count 2 2006.201.20:01:57.99#ibcon#wrote, iclass 20, count 2 2006.201.20:01:57.99#ibcon#about to read 3, iclass 20, count 2 2006.201.20:01:58.02#ibcon#read 3, iclass 20, count 2 2006.201.20:01:58.02#ibcon#about to read 4, iclass 20, count 2 2006.201.20:01:58.02#ibcon#read 4, iclass 20, count 2 2006.201.20:01:58.02#ibcon#about to read 5, iclass 20, count 2 2006.201.20:01:58.02#ibcon#read 5, iclass 20, count 2 2006.201.20:01:58.02#ibcon#about to read 6, iclass 20, count 2 2006.201.20:01:58.02#ibcon#read 6, iclass 20, count 2 2006.201.20:01:58.02#ibcon#end of sib2, iclass 20, count 2 2006.201.20:01:58.02#ibcon#*after write, iclass 20, count 2 2006.201.20:01:58.02#ibcon#*before return 0, iclass 20, count 2 2006.201.20:01:58.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:58.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:01:58.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.20:01:58.02#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:58.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:58.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:58.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:58.14#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:01:58.14#ibcon#first serial, iclass 20, count 0 2006.201.20:01:58.14#ibcon#enter sib2, iclass 20, count 0 2006.201.20:01:58.14#ibcon#flushed, iclass 20, count 0 2006.201.20:01:58.14#ibcon#about to write, iclass 20, count 0 2006.201.20:01:58.14#ibcon#wrote, iclass 20, count 0 2006.201.20:01:58.14#ibcon#about to read 3, iclass 20, count 0 2006.201.20:01:58.16#ibcon#read 3, iclass 20, count 0 2006.201.20:01:58.16#ibcon#about to read 4, iclass 20, count 0 2006.201.20:01:58.16#ibcon#read 4, iclass 20, count 0 2006.201.20:01:58.16#ibcon#about to read 5, iclass 20, count 0 2006.201.20:01:58.16#ibcon#read 5, iclass 20, count 0 2006.201.20:01:58.16#ibcon#about to read 6, iclass 20, count 0 2006.201.20:01:58.16#ibcon#read 6, iclass 20, count 0 2006.201.20:01:58.16#ibcon#end of sib2, iclass 20, count 0 2006.201.20:01:58.16#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:01:58.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:01:58.16#ibcon#[27=USB\r\n] 2006.201.20:01:58.16#ibcon#*before write, iclass 20, count 0 2006.201.20:01:58.16#ibcon#enter sib2, iclass 20, count 0 2006.201.20:01:58.16#ibcon#flushed, iclass 20, count 0 2006.201.20:01:58.16#ibcon#about to write, iclass 20, count 0 2006.201.20:01:58.16#ibcon#wrote, iclass 20, count 0 2006.201.20:01:58.16#ibcon#about to read 3, iclass 20, count 0 2006.201.20:01:58.19#ibcon#read 3, iclass 20, count 0 2006.201.20:01:58.19#ibcon#about to read 4, iclass 20, count 0 2006.201.20:01:58.19#ibcon#read 4, iclass 20, count 0 2006.201.20:01:58.19#ibcon#about to read 5, iclass 20, count 0 2006.201.20:01:58.19#ibcon#read 5, iclass 20, count 0 2006.201.20:01:58.19#ibcon#about to read 6, iclass 20, count 0 2006.201.20:01:58.19#ibcon#read 6, iclass 20, count 0 2006.201.20:01:58.19#ibcon#end of sib2, iclass 20, count 0 2006.201.20:01:58.19#ibcon#*after write, iclass 20, count 0 2006.201.20:01:58.19#ibcon#*before return 0, iclass 20, count 0 2006.201.20:01:58.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:58.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:01:58.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:01:58.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:01:58.19$vck44/vblo=6,719.99 2006.201.20:01:58.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.20:01:58.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.20:01:58.19#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:58.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:58.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:58.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:58.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:01:58.19#ibcon#first serial, iclass 22, count 0 2006.201.20:01:58.19#ibcon#enter sib2, iclass 22, count 0 2006.201.20:01:58.19#ibcon#flushed, iclass 22, count 0 2006.201.20:01:58.19#ibcon#about to write, iclass 22, count 0 2006.201.20:01:58.19#ibcon#wrote, iclass 22, count 0 2006.201.20:01:58.19#ibcon#about to read 3, iclass 22, count 0 2006.201.20:01:58.21#ibcon#read 3, iclass 22, count 0 2006.201.20:01:58.21#ibcon#about to read 4, iclass 22, count 0 2006.201.20:01:58.21#ibcon#read 4, iclass 22, count 0 2006.201.20:01:58.21#ibcon#about to read 5, iclass 22, count 0 2006.201.20:01:58.21#ibcon#read 5, iclass 22, count 0 2006.201.20:01:58.21#ibcon#about to read 6, iclass 22, count 0 2006.201.20:01:58.21#ibcon#read 6, iclass 22, count 0 2006.201.20:01:58.21#ibcon#end of sib2, iclass 22, count 0 2006.201.20:01:58.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:01:58.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:01:58.21#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:01:58.21#ibcon#*before write, iclass 22, count 0 2006.201.20:01:58.21#ibcon#enter sib2, iclass 22, count 0 2006.201.20:01:58.21#ibcon#flushed, iclass 22, count 0 2006.201.20:01:58.21#ibcon#about to write, iclass 22, count 0 2006.201.20:01:58.21#ibcon#wrote, iclass 22, count 0 2006.201.20:01:58.21#ibcon#about to read 3, iclass 22, count 0 2006.201.20:01:58.25#ibcon#read 3, iclass 22, count 0 2006.201.20:01:58.25#ibcon#about to read 4, iclass 22, count 0 2006.201.20:01:58.25#ibcon#read 4, iclass 22, count 0 2006.201.20:01:58.25#ibcon#about to read 5, iclass 22, count 0 2006.201.20:01:58.25#ibcon#read 5, iclass 22, count 0 2006.201.20:01:58.25#ibcon#about to read 6, iclass 22, count 0 2006.201.20:01:58.25#ibcon#read 6, iclass 22, count 0 2006.201.20:01:58.25#ibcon#end of sib2, iclass 22, count 0 2006.201.20:01:58.25#ibcon#*after write, iclass 22, count 0 2006.201.20:01:58.25#ibcon#*before return 0, iclass 22, count 0 2006.201.20:01:58.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:58.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:01:58.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:01:58.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:01:58.25$vck44/vb=6,4 2006.201.20:01:58.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.20:01:58.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.20:01:58.25#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:58.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:58.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:58.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:58.31#ibcon#enter wrdev, iclass 24, count 2 2006.201.20:01:58.31#ibcon#first serial, iclass 24, count 2 2006.201.20:01:58.31#ibcon#enter sib2, iclass 24, count 2 2006.201.20:01:58.31#ibcon#flushed, iclass 24, count 2 2006.201.20:01:58.31#ibcon#about to write, iclass 24, count 2 2006.201.20:01:58.31#ibcon#wrote, iclass 24, count 2 2006.201.20:01:58.31#ibcon#about to read 3, iclass 24, count 2 2006.201.20:01:58.33#ibcon#read 3, iclass 24, count 2 2006.201.20:01:58.33#ibcon#about to read 4, iclass 24, count 2 2006.201.20:01:58.33#ibcon#read 4, iclass 24, count 2 2006.201.20:01:58.33#ibcon#about to read 5, iclass 24, count 2 2006.201.20:01:58.33#ibcon#read 5, iclass 24, count 2 2006.201.20:01:58.33#ibcon#about to read 6, iclass 24, count 2 2006.201.20:01:58.33#ibcon#read 6, iclass 24, count 2 2006.201.20:01:58.33#ibcon#end of sib2, iclass 24, count 2 2006.201.20:01:58.33#ibcon#*mode == 0, iclass 24, count 2 2006.201.20:01:58.33#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.20:01:58.33#ibcon#[27=AT06-04\r\n] 2006.201.20:01:58.33#ibcon#*before write, iclass 24, count 2 2006.201.20:01:58.33#ibcon#enter sib2, iclass 24, count 2 2006.201.20:01:58.33#ibcon#flushed, iclass 24, count 2 2006.201.20:01:58.33#ibcon#about to write, iclass 24, count 2 2006.201.20:01:58.33#ibcon#wrote, iclass 24, count 2 2006.201.20:01:58.33#ibcon#about to read 3, iclass 24, count 2 2006.201.20:01:58.36#ibcon#read 3, iclass 24, count 2 2006.201.20:01:58.36#ibcon#about to read 4, iclass 24, count 2 2006.201.20:01:58.36#ibcon#read 4, iclass 24, count 2 2006.201.20:01:58.36#ibcon#about to read 5, iclass 24, count 2 2006.201.20:01:58.36#ibcon#read 5, iclass 24, count 2 2006.201.20:01:58.36#ibcon#about to read 6, iclass 24, count 2 2006.201.20:01:58.36#ibcon#read 6, iclass 24, count 2 2006.201.20:01:58.36#ibcon#end of sib2, iclass 24, count 2 2006.201.20:01:58.36#ibcon#*after write, iclass 24, count 2 2006.201.20:01:58.36#ibcon#*before return 0, iclass 24, count 2 2006.201.20:01:58.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:58.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:01:58.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.20:01:58.36#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:58.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:58.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:58.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:58.48#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:01:58.48#ibcon#first serial, iclass 24, count 0 2006.201.20:01:58.48#ibcon#enter sib2, iclass 24, count 0 2006.201.20:01:58.48#ibcon#flushed, iclass 24, count 0 2006.201.20:01:58.48#ibcon#about to write, iclass 24, count 0 2006.201.20:01:58.48#ibcon#wrote, iclass 24, count 0 2006.201.20:01:58.48#ibcon#about to read 3, iclass 24, count 0 2006.201.20:01:58.50#ibcon#read 3, iclass 24, count 0 2006.201.20:01:58.50#ibcon#about to read 4, iclass 24, count 0 2006.201.20:01:58.50#ibcon#read 4, iclass 24, count 0 2006.201.20:01:58.50#ibcon#about to read 5, iclass 24, count 0 2006.201.20:01:58.50#ibcon#read 5, iclass 24, count 0 2006.201.20:01:58.50#ibcon#about to read 6, iclass 24, count 0 2006.201.20:01:58.50#ibcon#read 6, iclass 24, count 0 2006.201.20:01:58.50#ibcon#end of sib2, iclass 24, count 0 2006.201.20:01:58.50#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:01:58.50#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:01:58.50#ibcon#[27=USB\r\n] 2006.201.20:01:58.50#ibcon#*before write, iclass 24, count 0 2006.201.20:01:58.50#ibcon#enter sib2, iclass 24, count 0 2006.201.20:01:58.50#ibcon#flushed, iclass 24, count 0 2006.201.20:01:58.50#ibcon#about to write, iclass 24, count 0 2006.201.20:01:58.50#ibcon#wrote, iclass 24, count 0 2006.201.20:01:58.50#ibcon#about to read 3, iclass 24, count 0 2006.201.20:01:58.53#ibcon#read 3, iclass 24, count 0 2006.201.20:01:58.53#ibcon#about to read 4, iclass 24, count 0 2006.201.20:01:58.53#ibcon#read 4, iclass 24, count 0 2006.201.20:01:58.53#ibcon#about to read 5, iclass 24, count 0 2006.201.20:01:58.53#ibcon#read 5, iclass 24, count 0 2006.201.20:01:58.53#ibcon#about to read 6, iclass 24, count 0 2006.201.20:01:58.53#ibcon#read 6, iclass 24, count 0 2006.201.20:01:58.53#ibcon#end of sib2, iclass 24, count 0 2006.201.20:01:58.53#ibcon#*after write, iclass 24, count 0 2006.201.20:01:58.53#ibcon#*before return 0, iclass 24, count 0 2006.201.20:01:58.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:58.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:01:58.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:01:58.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:01:58.53$vck44/vblo=7,734.99 2006.201.20:01:58.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.20:01:58.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.20:01:58.53#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:58.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:58.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:58.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:58.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:01:58.53#ibcon#first serial, iclass 26, count 0 2006.201.20:01:58.53#ibcon#enter sib2, iclass 26, count 0 2006.201.20:01:58.53#ibcon#flushed, iclass 26, count 0 2006.201.20:01:58.53#ibcon#about to write, iclass 26, count 0 2006.201.20:01:58.53#ibcon#wrote, iclass 26, count 0 2006.201.20:01:58.53#ibcon#about to read 3, iclass 26, count 0 2006.201.20:01:58.55#ibcon#read 3, iclass 26, count 0 2006.201.20:01:58.55#ibcon#about to read 4, iclass 26, count 0 2006.201.20:01:58.55#ibcon#read 4, iclass 26, count 0 2006.201.20:01:58.55#ibcon#about to read 5, iclass 26, count 0 2006.201.20:01:58.55#ibcon#read 5, iclass 26, count 0 2006.201.20:01:58.55#ibcon#about to read 6, iclass 26, count 0 2006.201.20:01:58.55#ibcon#read 6, iclass 26, count 0 2006.201.20:01:58.55#ibcon#end of sib2, iclass 26, count 0 2006.201.20:01:58.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:01:58.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:01:58.55#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:01:58.55#ibcon#*before write, iclass 26, count 0 2006.201.20:01:58.55#ibcon#enter sib2, iclass 26, count 0 2006.201.20:01:58.55#ibcon#flushed, iclass 26, count 0 2006.201.20:01:58.55#ibcon#about to write, iclass 26, count 0 2006.201.20:01:58.55#ibcon#wrote, iclass 26, count 0 2006.201.20:01:58.55#ibcon#about to read 3, iclass 26, count 0 2006.201.20:01:58.60#ibcon#read 3, iclass 26, count 0 2006.201.20:01:58.60#ibcon#about to read 4, iclass 26, count 0 2006.201.20:01:58.60#ibcon#read 4, iclass 26, count 0 2006.201.20:01:58.60#ibcon#about to read 5, iclass 26, count 0 2006.201.20:01:58.60#ibcon#read 5, iclass 26, count 0 2006.201.20:01:58.60#ibcon#about to read 6, iclass 26, count 0 2006.201.20:01:58.60#ibcon#read 6, iclass 26, count 0 2006.201.20:01:58.60#ibcon#end of sib2, iclass 26, count 0 2006.201.20:01:58.60#ibcon#*after write, iclass 26, count 0 2006.201.20:01:58.60#ibcon#*before return 0, iclass 26, count 0 2006.201.20:01:58.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:58.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:01:58.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:01:58.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:01:58.60$vck44/vb=7,4 2006.201.20:01:58.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.20:01:58.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.20:01:58.60#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:58.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:58.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:58.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:58.65#ibcon#enter wrdev, iclass 28, count 2 2006.201.20:01:58.65#ibcon#first serial, iclass 28, count 2 2006.201.20:01:58.65#ibcon#enter sib2, iclass 28, count 2 2006.201.20:01:58.65#ibcon#flushed, iclass 28, count 2 2006.201.20:01:58.65#ibcon#about to write, iclass 28, count 2 2006.201.20:01:58.65#ibcon#wrote, iclass 28, count 2 2006.201.20:01:58.65#ibcon#about to read 3, iclass 28, count 2 2006.201.20:01:58.67#ibcon#read 3, iclass 28, count 2 2006.201.20:01:58.67#ibcon#about to read 4, iclass 28, count 2 2006.201.20:01:58.67#ibcon#read 4, iclass 28, count 2 2006.201.20:01:58.67#ibcon#about to read 5, iclass 28, count 2 2006.201.20:01:58.67#ibcon#read 5, iclass 28, count 2 2006.201.20:01:58.67#ibcon#about to read 6, iclass 28, count 2 2006.201.20:01:58.67#ibcon#read 6, iclass 28, count 2 2006.201.20:01:58.67#ibcon#end of sib2, iclass 28, count 2 2006.201.20:01:58.67#ibcon#*mode == 0, iclass 28, count 2 2006.201.20:01:58.67#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.20:01:58.67#ibcon#[27=AT07-04\r\n] 2006.201.20:01:58.67#ibcon#*before write, iclass 28, count 2 2006.201.20:01:58.67#ibcon#enter sib2, iclass 28, count 2 2006.201.20:01:58.67#ibcon#flushed, iclass 28, count 2 2006.201.20:01:58.67#ibcon#about to write, iclass 28, count 2 2006.201.20:01:58.67#ibcon#wrote, iclass 28, count 2 2006.201.20:01:58.67#ibcon#about to read 3, iclass 28, count 2 2006.201.20:01:58.70#ibcon#read 3, iclass 28, count 2 2006.201.20:01:58.70#ibcon#about to read 4, iclass 28, count 2 2006.201.20:01:58.70#ibcon#read 4, iclass 28, count 2 2006.201.20:01:58.70#ibcon#about to read 5, iclass 28, count 2 2006.201.20:01:58.70#ibcon#read 5, iclass 28, count 2 2006.201.20:01:58.70#ibcon#about to read 6, iclass 28, count 2 2006.201.20:01:58.70#ibcon#read 6, iclass 28, count 2 2006.201.20:01:58.70#ibcon#end of sib2, iclass 28, count 2 2006.201.20:01:58.70#ibcon#*after write, iclass 28, count 2 2006.201.20:01:58.70#ibcon#*before return 0, iclass 28, count 2 2006.201.20:01:58.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:58.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:01:58.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.20:01:58.70#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:58.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:58.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:58.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:58.82#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:01:58.82#ibcon#first serial, iclass 28, count 0 2006.201.20:01:58.82#ibcon#enter sib2, iclass 28, count 0 2006.201.20:01:58.82#ibcon#flushed, iclass 28, count 0 2006.201.20:01:58.82#ibcon#about to write, iclass 28, count 0 2006.201.20:01:58.82#ibcon#wrote, iclass 28, count 0 2006.201.20:01:58.82#ibcon#about to read 3, iclass 28, count 0 2006.201.20:01:58.84#ibcon#read 3, iclass 28, count 0 2006.201.20:01:58.84#ibcon#about to read 4, iclass 28, count 0 2006.201.20:01:58.84#ibcon#read 4, iclass 28, count 0 2006.201.20:01:58.84#ibcon#about to read 5, iclass 28, count 0 2006.201.20:01:58.84#ibcon#read 5, iclass 28, count 0 2006.201.20:01:58.84#ibcon#about to read 6, iclass 28, count 0 2006.201.20:01:58.84#ibcon#read 6, iclass 28, count 0 2006.201.20:01:58.84#ibcon#end of sib2, iclass 28, count 0 2006.201.20:01:58.84#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:01:58.84#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:01:58.84#ibcon#[27=USB\r\n] 2006.201.20:01:58.84#ibcon#*before write, iclass 28, count 0 2006.201.20:01:58.84#ibcon#enter sib2, iclass 28, count 0 2006.201.20:01:58.84#ibcon#flushed, iclass 28, count 0 2006.201.20:01:58.84#ibcon#about to write, iclass 28, count 0 2006.201.20:01:58.84#ibcon#wrote, iclass 28, count 0 2006.201.20:01:58.84#ibcon#about to read 3, iclass 28, count 0 2006.201.20:01:58.87#ibcon#read 3, iclass 28, count 0 2006.201.20:01:58.87#ibcon#about to read 4, iclass 28, count 0 2006.201.20:01:58.87#ibcon#read 4, iclass 28, count 0 2006.201.20:01:58.87#ibcon#about to read 5, iclass 28, count 0 2006.201.20:01:58.87#ibcon#read 5, iclass 28, count 0 2006.201.20:01:58.87#ibcon#about to read 6, iclass 28, count 0 2006.201.20:01:58.87#ibcon#read 6, iclass 28, count 0 2006.201.20:01:58.87#ibcon#end of sib2, iclass 28, count 0 2006.201.20:01:58.87#ibcon#*after write, iclass 28, count 0 2006.201.20:01:58.87#ibcon#*before return 0, iclass 28, count 0 2006.201.20:01:58.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:58.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:01:58.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:01:58.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:01:58.87$vck44/vblo=8,744.99 2006.201.20:01:58.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.20:01:58.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.20:01:58.87#ibcon#ireg 17 cls_cnt 0 2006.201.20:01:58.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:58.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:58.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:58.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:01:58.87#ibcon#first serial, iclass 30, count 0 2006.201.20:01:58.87#ibcon#enter sib2, iclass 30, count 0 2006.201.20:01:58.87#ibcon#flushed, iclass 30, count 0 2006.201.20:01:58.87#ibcon#about to write, iclass 30, count 0 2006.201.20:01:58.87#ibcon#wrote, iclass 30, count 0 2006.201.20:01:58.87#ibcon#about to read 3, iclass 30, count 0 2006.201.20:01:58.89#ibcon#read 3, iclass 30, count 0 2006.201.20:01:58.89#ibcon#about to read 4, iclass 30, count 0 2006.201.20:01:58.89#ibcon#read 4, iclass 30, count 0 2006.201.20:01:58.89#ibcon#about to read 5, iclass 30, count 0 2006.201.20:01:58.89#ibcon#read 5, iclass 30, count 0 2006.201.20:01:58.89#ibcon#about to read 6, iclass 30, count 0 2006.201.20:01:58.89#ibcon#read 6, iclass 30, count 0 2006.201.20:01:58.89#ibcon#end of sib2, iclass 30, count 0 2006.201.20:01:58.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:01:58.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:01:58.89#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:01:58.89#ibcon#*before write, iclass 30, count 0 2006.201.20:01:58.89#ibcon#enter sib2, iclass 30, count 0 2006.201.20:01:58.89#ibcon#flushed, iclass 30, count 0 2006.201.20:01:58.89#ibcon#about to write, iclass 30, count 0 2006.201.20:01:58.89#ibcon#wrote, iclass 30, count 0 2006.201.20:01:58.89#ibcon#about to read 3, iclass 30, count 0 2006.201.20:01:58.94#ibcon#read 3, iclass 30, count 0 2006.201.20:01:58.94#ibcon#about to read 4, iclass 30, count 0 2006.201.20:01:58.94#ibcon#read 4, iclass 30, count 0 2006.201.20:01:58.94#ibcon#about to read 5, iclass 30, count 0 2006.201.20:01:58.94#ibcon#read 5, iclass 30, count 0 2006.201.20:01:58.94#ibcon#about to read 6, iclass 30, count 0 2006.201.20:01:58.94#ibcon#read 6, iclass 30, count 0 2006.201.20:01:58.94#ibcon#end of sib2, iclass 30, count 0 2006.201.20:01:58.94#ibcon#*after write, iclass 30, count 0 2006.201.20:01:58.94#ibcon#*before return 0, iclass 30, count 0 2006.201.20:01:58.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:58.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:01:58.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:01:58.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:01:58.94$vck44/vb=8,4 2006.201.20:01:58.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.20:01:58.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.20:01:58.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:01:58.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:58.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:58.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:58.99#ibcon#enter wrdev, iclass 32, count 2 2006.201.20:01:58.99#ibcon#first serial, iclass 32, count 2 2006.201.20:01:58.99#ibcon#enter sib2, iclass 32, count 2 2006.201.20:01:58.99#ibcon#flushed, iclass 32, count 2 2006.201.20:01:58.99#ibcon#about to write, iclass 32, count 2 2006.201.20:01:58.99#ibcon#wrote, iclass 32, count 2 2006.201.20:01:58.99#ibcon#about to read 3, iclass 32, count 2 2006.201.20:01:59.01#ibcon#read 3, iclass 32, count 2 2006.201.20:01:59.01#ibcon#about to read 4, iclass 32, count 2 2006.201.20:01:59.01#ibcon#read 4, iclass 32, count 2 2006.201.20:01:59.01#ibcon#about to read 5, iclass 32, count 2 2006.201.20:01:59.01#ibcon#read 5, iclass 32, count 2 2006.201.20:01:59.01#ibcon#about to read 6, iclass 32, count 2 2006.201.20:01:59.01#ibcon#read 6, iclass 32, count 2 2006.201.20:01:59.01#ibcon#end of sib2, iclass 32, count 2 2006.201.20:01:59.01#ibcon#*mode == 0, iclass 32, count 2 2006.201.20:01:59.01#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.20:01:59.01#ibcon#[27=AT08-04\r\n] 2006.201.20:01:59.01#ibcon#*before write, iclass 32, count 2 2006.201.20:01:59.01#ibcon#enter sib2, iclass 32, count 2 2006.201.20:01:59.01#ibcon#flushed, iclass 32, count 2 2006.201.20:01:59.01#ibcon#about to write, iclass 32, count 2 2006.201.20:01:59.01#ibcon#wrote, iclass 32, count 2 2006.201.20:01:59.01#ibcon#about to read 3, iclass 32, count 2 2006.201.20:01:59.04#ibcon#read 3, iclass 32, count 2 2006.201.20:01:59.04#ibcon#about to read 4, iclass 32, count 2 2006.201.20:01:59.04#ibcon#read 4, iclass 32, count 2 2006.201.20:01:59.04#ibcon#about to read 5, iclass 32, count 2 2006.201.20:01:59.04#ibcon#read 5, iclass 32, count 2 2006.201.20:01:59.04#ibcon#about to read 6, iclass 32, count 2 2006.201.20:01:59.04#ibcon#read 6, iclass 32, count 2 2006.201.20:01:59.04#ibcon#end of sib2, iclass 32, count 2 2006.201.20:01:59.04#ibcon#*after write, iclass 32, count 2 2006.201.20:01:59.04#ibcon#*before return 0, iclass 32, count 2 2006.201.20:01:59.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:59.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:01:59.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.20:01:59.04#ibcon#ireg 7 cls_cnt 0 2006.201.20:01:59.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:59.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:59.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:59.16#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:01:59.16#ibcon#first serial, iclass 32, count 0 2006.201.20:01:59.16#ibcon#enter sib2, iclass 32, count 0 2006.201.20:01:59.16#ibcon#flushed, iclass 32, count 0 2006.201.20:01:59.16#ibcon#about to write, iclass 32, count 0 2006.201.20:01:59.16#ibcon#wrote, iclass 32, count 0 2006.201.20:01:59.16#ibcon#about to read 3, iclass 32, count 0 2006.201.20:01:59.18#ibcon#read 3, iclass 32, count 0 2006.201.20:01:59.18#ibcon#about to read 4, iclass 32, count 0 2006.201.20:01:59.18#ibcon#read 4, iclass 32, count 0 2006.201.20:01:59.18#ibcon#about to read 5, iclass 32, count 0 2006.201.20:01:59.18#ibcon#read 5, iclass 32, count 0 2006.201.20:01:59.18#ibcon#about to read 6, iclass 32, count 0 2006.201.20:01:59.18#ibcon#read 6, iclass 32, count 0 2006.201.20:01:59.18#ibcon#end of sib2, iclass 32, count 0 2006.201.20:01:59.18#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:01:59.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:01:59.18#ibcon#[27=USB\r\n] 2006.201.20:01:59.18#ibcon#*before write, iclass 32, count 0 2006.201.20:01:59.18#ibcon#enter sib2, iclass 32, count 0 2006.201.20:01:59.18#ibcon#flushed, iclass 32, count 0 2006.201.20:01:59.18#ibcon#about to write, iclass 32, count 0 2006.201.20:01:59.18#ibcon#wrote, iclass 32, count 0 2006.201.20:01:59.18#ibcon#about to read 3, iclass 32, count 0 2006.201.20:01:59.21#ibcon#read 3, iclass 32, count 0 2006.201.20:01:59.21#ibcon#about to read 4, iclass 32, count 0 2006.201.20:01:59.21#ibcon#read 4, iclass 32, count 0 2006.201.20:01:59.21#ibcon#about to read 5, iclass 32, count 0 2006.201.20:01:59.21#ibcon#read 5, iclass 32, count 0 2006.201.20:01:59.21#ibcon#about to read 6, iclass 32, count 0 2006.201.20:01:59.21#ibcon#read 6, iclass 32, count 0 2006.201.20:01:59.21#ibcon#end of sib2, iclass 32, count 0 2006.201.20:01:59.21#ibcon#*after write, iclass 32, count 0 2006.201.20:01:59.21#ibcon#*before return 0, iclass 32, count 0 2006.201.20:01:59.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:59.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:01:59.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:01:59.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:01:59.21$vck44/vabw=wide 2006.201.20:01:59.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.20:01:59.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.20:01:59.21#ibcon#ireg 8 cls_cnt 0 2006.201.20:01:59.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:59.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:59.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:59.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:01:59.21#ibcon#first serial, iclass 34, count 0 2006.201.20:01:59.21#ibcon#enter sib2, iclass 34, count 0 2006.201.20:01:59.21#ibcon#flushed, iclass 34, count 0 2006.201.20:01:59.21#ibcon#about to write, iclass 34, count 0 2006.201.20:01:59.21#ibcon#wrote, iclass 34, count 0 2006.201.20:01:59.21#ibcon#about to read 3, iclass 34, count 0 2006.201.20:01:59.23#ibcon#read 3, iclass 34, count 0 2006.201.20:01:59.23#ibcon#about to read 4, iclass 34, count 0 2006.201.20:01:59.23#ibcon#read 4, iclass 34, count 0 2006.201.20:01:59.23#ibcon#about to read 5, iclass 34, count 0 2006.201.20:01:59.23#ibcon#read 5, iclass 34, count 0 2006.201.20:01:59.23#ibcon#about to read 6, iclass 34, count 0 2006.201.20:01:59.23#ibcon#read 6, iclass 34, count 0 2006.201.20:01:59.23#ibcon#end of sib2, iclass 34, count 0 2006.201.20:01:59.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:01:59.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:01:59.23#ibcon#[25=BW32\r\n] 2006.201.20:01:59.23#ibcon#*before write, iclass 34, count 0 2006.201.20:01:59.23#ibcon#enter sib2, iclass 34, count 0 2006.201.20:01:59.23#ibcon#flushed, iclass 34, count 0 2006.201.20:01:59.23#ibcon#about to write, iclass 34, count 0 2006.201.20:01:59.23#ibcon#wrote, iclass 34, count 0 2006.201.20:01:59.23#ibcon#about to read 3, iclass 34, count 0 2006.201.20:01:59.26#ibcon#read 3, iclass 34, count 0 2006.201.20:01:59.26#ibcon#about to read 4, iclass 34, count 0 2006.201.20:01:59.26#ibcon#read 4, iclass 34, count 0 2006.201.20:01:59.26#ibcon#about to read 5, iclass 34, count 0 2006.201.20:01:59.26#ibcon#read 5, iclass 34, count 0 2006.201.20:01:59.26#ibcon#about to read 6, iclass 34, count 0 2006.201.20:01:59.26#ibcon#read 6, iclass 34, count 0 2006.201.20:01:59.26#ibcon#end of sib2, iclass 34, count 0 2006.201.20:01:59.26#ibcon#*after write, iclass 34, count 0 2006.201.20:01:59.26#ibcon#*before return 0, iclass 34, count 0 2006.201.20:01:59.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:59.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:01:59.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:01:59.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:01:59.26$vck44/vbbw=wide 2006.201.20:01:59.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.20:01:59.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.20:01:59.26#ibcon#ireg 8 cls_cnt 0 2006.201.20:01:59.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:01:59.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:01:59.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:01:59.33#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:01:59.33#ibcon#first serial, iclass 36, count 0 2006.201.20:01:59.33#ibcon#enter sib2, iclass 36, count 0 2006.201.20:01:59.33#ibcon#flushed, iclass 36, count 0 2006.201.20:01:59.33#ibcon#about to write, iclass 36, count 0 2006.201.20:01:59.33#ibcon#wrote, iclass 36, count 0 2006.201.20:01:59.33#ibcon#about to read 3, iclass 36, count 0 2006.201.20:01:59.35#ibcon#read 3, iclass 36, count 0 2006.201.20:01:59.35#ibcon#about to read 4, iclass 36, count 0 2006.201.20:01:59.35#ibcon#read 4, iclass 36, count 0 2006.201.20:01:59.35#ibcon#about to read 5, iclass 36, count 0 2006.201.20:01:59.35#ibcon#read 5, iclass 36, count 0 2006.201.20:01:59.35#ibcon#about to read 6, iclass 36, count 0 2006.201.20:01:59.35#ibcon#read 6, iclass 36, count 0 2006.201.20:01:59.35#ibcon#end of sib2, iclass 36, count 0 2006.201.20:01:59.35#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:01:59.35#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:01:59.35#ibcon#[27=BW32\r\n] 2006.201.20:01:59.35#ibcon#*before write, iclass 36, count 0 2006.201.20:01:59.35#ibcon#enter sib2, iclass 36, count 0 2006.201.20:01:59.35#ibcon#flushed, iclass 36, count 0 2006.201.20:01:59.35#ibcon#about to write, iclass 36, count 0 2006.201.20:01:59.35#ibcon#wrote, iclass 36, count 0 2006.201.20:01:59.35#ibcon#about to read 3, iclass 36, count 0 2006.201.20:01:59.38#ibcon#read 3, iclass 36, count 0 2006.201.20:01:59.38#ibcon#about to read 4, iclass 36, count 0 2006.201.20:01:59.38#ibcon#read 4, iclass 36, count 0 2006.201.20:01:59.38#ibcon#about to read 5, iclass 36, count 0 2006.201.20:01:59.38#ibcon#read 5, iclass 36, count 0 2006.201.20:01:59.38#ibcon#about to read 6, iclass 36, count 0 2006.201.20:01:59.38#ibcon#read 6, iclass 36, count 0 2006.201.20:01:59.38#ibcon#end of sib2, iclass 36, count 0 2006.201.20:01:59.38#ibcon#*after write, iclass 36, count 0 2006.201.20:01:59.38#ibcon#*before return 0, iclass 36, count 0 2006.201.20:01:59.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:01:59.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:01:59.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:01:59.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:01:59.38$setupk4/ifdk4 2006.201.20:01:59.38$ifdk4/lo= 2006.201.20:01:59.38$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:01:59.38$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:01:59.38$ifdk4/patch= 2006.201.20:01:59.38$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:01:59.38$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:01:59.38$setupk4/!*+20s 2006.201.20:02:00.53#abcon#<5=/04 2.5 5.5 20.241001002.0\r\n> 2006.201.20:02:00.55#abcon#{5=INTERFACE CLEAR} 2006.201.20:02:00.62#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:02:10.71#abcon#<5=/04 2.5 5.5 20.241001002.0\r\n> 2006.201.20:02:10.73#abcon#{5=INTERFACE CLEAR} 2006.201.20:02:10.79#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:02:13.87$setupk4/"tpicd 2006.201.20:02:13.87$setupk4/echo=off 2006.201.20:02:13.87$setupk4/xlog=off 2006.201.20:02:13.87:!2006.201.20:05:07 2006.201.20:02:45.14#trakl#Source acquired 2006.201.20:02:47.14#flagr#flagr/antenna,acquired 2006.201.20:05:07.00:preob 2006.201.20:05:07.14/onsource/TRACKING 2006.201.20:05:07.14:!2006.201.20:05:17 2006.201.20:05:17.00:"tape 2006.201.20:05:17.00:"st=record 2006.201.20:05:17.00:data_valid=on 2006.201.20:05:17.00:midob 2006.201.20:05:17.14/onsource/TRACKING 2006.201.20:05:17.14/wx/20.21,1001.9,100 2006.201.20:05:17.33/cable/+6.4810E-03 2006.201.20:05:18.42/va/01,08,usb,yes,40,43 2006.201.20:05:18.42/va/02,07,usb,yes,43,44 2006.201.20:05:18.42/va/03,08,usb,yes,39,41 2006.201.20:05:18.42/va/04,07,usb,yes,45,47 2006.201.20:05:18.42/va/05,04,usb,yes,40,41 2006.201.20:05:18.42/va/06,05,usb,yes,40,40 2006.201.20:05:18.42/va/07,05,usb,yes,39,41 2006.201.20:05:18.42/va/08,04,usb,yes,39,46 2006.201.20:05:18.65/valo/01,524.99,yes,locked 2006.201.20:05:18.65/valo/02,534.99,yes,locked 2006.201.20:05:18.65/valo/03,564.99,yes,locked 2006.201.20:05:18.65/valo/04,624.99,yes,locked 2006.201.20:05:18.65/valo/05,734.99,yes,locked 2006.201.20:05:18.65/valo/06,814.99,yes,locked 2006.201.20:05:18.65/valo/07,864.99,yes,locked 2006.201.20:05:18.65/valo/08,884.99,yes,locked 2006.201.20:05:19.74/vb/01,04,usb,yes,30,28 2006.201.20:05:19.74/vb/02,05,usb,yes,29,28 2006.201.20:05:19.74/vb/03,04,usb,yes,30,33 2006.201.20:05:19.74/vb/04,05,usb,yes,30,29 2006.201.20:05:19.74/vb/05,04,usb,yes,26,29 2006.201.20:05:19.74/vb/06,04,usb,yes,31,27 2006.201.20:05:19.74/vb/07,04,usb,yes,31,31 2006.201.20:05:19.74/vb/08,04,usb,yes,28,32 2006.201.20:05:19.97/vblo/01,629.99,yes,locked 2006.201.20:05:19.97/vblo/02,634.99,yes,locked 2006.201.20:05:19.97/vblo/03,649.99,yes,locked 2006.201.20:05:19.97/vblo/04,679.99,yes,locked 2006.201.20:05:19.97/vblo/05,709.99,yes,locked 2006.201.20:05:19.97/vblo/06,719.99,yes,locked 2006.201.20:05:19.97/vblo/07,734.99,yes,locked 2006.201.20:05:19.97/vblo/08,744.99,yes,locked 2006.201.20:05:20.12/vabw/8 2006.201.20:05:20.27/vbbw/8 2006.201.20:05:20.36/xfe/off,on,14.0 2006.201.20:05:20.73/ifatt/23,28,28,28 2006.201.20:05:21.07/fmout-gps/S +4.56E-07 2006.201.20:05:21.11:!2006.201.20:09:27 2006.201.20:09:27.00:data_valid=off 2006.201.20:09:27.00:"et 2006.201.20:09:27.00:!+3s 2006.201.20:09:30.02:"tape 2006.201.20:09:30.02:postob 2006.201.20:09:30.09/cable/+6.4797E-03 2006.201.20:09:30.09/wx/20.16,1001.9,100 2006.201.20:09:30.16/fmout-gps/S +4.53E-07 2006.201.20:09:30.16:scan_name=201-2014,jd0607,210 2006.201.20:09:30.16:source=0059+581,010245.76,582411.1,2000.0,neutral 2006.201.20:09:32.13#flagr#flagr/antenna,new-source 2006.201.20:09:32.13:checkk5 2006.201.20:09:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:09:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:09:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:09:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:09:34.04/chk_obsdata//k5ts1/T2012005??a.dat file size is correct (nominal:1000MB, actual:996MB). 2006.201.20:09:34.40/chk_obsdata//k5ts2/T2012005??b.dat file size is correct (nominal:1000MB, actual:996MB). 2006.201.20:09:34.77/chk_obsdata//k5ts3/T2012005??c.dat file size is correct (nominal:1000MB, actual:996MB). 2006.201.20:09:35.14/chk_obsdata//k5ts4/T2012005??d.dat file size is correct (nominal:1000MB, actual:996MB). 2006.201.20:09:35.83/k5log//k5ts1_log_newline 2006.201.20:09:36.52/k5log//k5ts2_log_newline 2006.201.20:09:37.21/k5log//k5ts3_log_newline 2006.201.20:09:37.89/k5log//k5ts4_log_newline 2006.201.20:09:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:09:37.92:setupk4=1 2006.201.20:09:37.92$setupk4/echo=on 2006.201.20:09:37.92$setupk4/pcalon 2006.201.20:09:37.92$pcalon/"no phase cal control is implemented here 2006.201.20:09:37.92$setupk4/"tpicd=stop 2006.201.20:09:37.92$setupk4/"rec=synch_on 2006.201.20:09:37.92$setupk4/"rec_mode=128 2006.201.20:09:37.92$setupk4/!* 2006.201.20:09:37.92$setupk4/recpk4 2006.201.20:09:37.92$recpk4/recpatch= 2006.201.20:09:37.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:09:37.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:09:37.92$setupk4/vck44 2006.201.20:09:37.92$vck44/valo=1,524.99 2006.201.20:09:37.92#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.20:09:37.92#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.20:09:37.92#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:37.92#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:37.92#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:37.92#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:37.92#ibcon#enter wrdev, iclass 2, count 0 2006.201.20:09:37.92#ibcon#first serial, iclass 2, count 0 2006.201.20:09:37.92#ibcon#enter sib2, iclass 2, count 0 2006.201.20:09:37.92#ibcon#flushed, iclass 2, count 0 2006.201.20:09:37.92#ibcon#about to write, iclass 2, count 0 2006.201.20:09:37.92#ibcon#wrote, iclass 2, count 0 2006.201.20:09:37.92#ibcon#about to read 3, iclass 2, count 0 2006.201.20:09:37.96#ibcon#read 3, iclass 2, count 0 2006.201.20:09:37.96#ibcon#about to read 4, iclass 2, count 0 2006.201.20:09:37.96#ibcon#read 4, iclass 2, count 0 2006.201.20:09:37.96#ibcon#about to read 5, iclass 2, count 0 2006.201.20:09:37.96#ibcon#read 5, iclass 2, count 0 2006.201.20:09:37.96#ibcon#about to read 6, iclass 2, count 0 2006.201.20:09:37.96#ibcon#read 6, iclass 2, count 0 2006.201.20:09:37.96#ibcon#end of sib2, iclass 2, count 0 2006.201.20:09:37.96#ibcon#*mode == 0, iclass 2, count 0 2006.201.20:09:37.96#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.20:09:37.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:09:37.96#ibcon#*before write, iclass 2, count 0 2006.201.20:09:37.96#ibcon#enter sib2, iclass 2, count 0 2006.201.20:09:37.96#ibcon#flushed, iclass 2, count 0 2006.201.20:09:37.96#ibcon#about to write, iclass 2, count 0 2006.201.20:09:37.96#ibcon#wrote, iclass 2, count 0 2006.201.20:09:37.96#ibcon#about to read 3, iclass 2, count 0 2006.201.20:09:38.01#ibcon#read 3, iclass 2, count 0 2006.201.20:09:38.01#ibcon#about to read 4, iclass 2, count 0 2006.201.20:09:38.01#ibcon#read 4, iclass 2, count 0 2006.201.20:09:38.01#ibcon#about to read 5, iclass 2, count 0 2006.201.20:09:38.01#ibcon#read 5, iclass 2, count 0 2006.201.20:09:38.01#ibcon#about to read 6, iclass 2, count 0 2006.201.20:09:38.01#ibcon#read 6, iclass 2, count 0 2006.201.20:09:38.01#ibcon#end of sib2, iclass 2, count 0 2006.201.20:09:38.01#ibcon#*after write, iclass 2, count 0 2006.201.20:09:38.01#ibcon#*before return 0, iclass 2, count 0 2006.201.20:09:38.01#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:38.01#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:38.01#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.20:09:38.01#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.20:09:38.01$vck44/va=1,8 2006.201.20:09:38.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.20:09:38.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.20:09:38.01#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:38.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:38.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:38.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:38.01#ibcon#enter wrdev, iclass 5, count 2 2006.201.20:09:38.01#ibcon#first serial, iclass 5, count 2 2006.201.20:09:38.01#ibcon#enter sib2, iclass 5, count 2 2006.201.20:09:38.01#ibcon#flushed, iclass 5, count 2 2006.201.20:09:38.01#ibcon#about to write, iclass 5, count 2 2006.201.20:09:38.01#ibcon#wrote, iclass 5, count 2 2006.201.20:09:38.01#ibcon#about to read 3, iclass 5, count 2 2006.201.20:09:38.03#ibcon#read 3, iclass 5, count 2 2006.201.20:09:38.03#ibcon#about to read 4, iclass 5, count 2 2006.201.20:09:38.03#ibcon#read 4, iclass 5, count 2 2006.201.20:09:38.03#ibcon#about to read 5, iclass 5, count 2 2006.201.20:09:38.03#ibcon#read 5, iclass 5, count 2 2006.201.20:09:38.03#ibcon#about to read 6, iclass 5, count 2 2006.201.20:09:38.03#ibcon#read 6, iclass 5, count 2 2006.201.20:09:38.03#ibcon#end of sib2, iclass 5, count 2 2006.201.20:09:38.03#ibcon#*mode == 0, iclass 5, count 2 2006.201.20:09:38.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.20:09:38.03#ibcon#[25=AT01-08\r\n] 2006.201.20:09:38.03#ibcon#*before write, iclass 5, count 2 2006.201.20:09:38.03#ibcon#enter sib2, iclass 5, count 2 2006.201.20:09:38.03#ibcon#flushed, iclass 5, count 2 2006.201.20:09:38.03#ibcon#about to write, iclass 5, count 2 2006.201.20:09:38.03#ibcon#wrote, iclass 5, count 2 2006.201.20:09:38.03#ibcon#about to read 3, iclass 5, count 2 2006.201.20:09:38.07#ibcon#read 3, iclass 5, count 2 2006.201.20:09:38.07#ibcon#about to read 4, iclass 5, count 2 2006.201.20:09:38.07#ibcon#read 4, iclass 5, count 2 2006.201.20:09:38.07#ibcon#about to read 5, iclass 5, count 2 2006.201.20:09:38.07#ibcon#read 5, iclass 5, count 2 2006.201.20:09:38.07#ibcon#about to read 6, iclass 5, count 2 2006.201.20:09:38.07#ibcon#read 6, iclass 5, count 2 2006.201.20:09:38.07#ibcon#end of sib2, iclass 5, count 2 2006.201.20:09:38.07#ibcon#*after write, iclass 5, count 2 2006.201.20:09:38.07#ibcon#*before return 0, iclass 5, count 2 2006.201.20:09:38.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:38.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:38.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.20:09:38.07#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:38.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:38.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:38.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:38.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.20:09:38.19#ibcon#first serial, iclass 5, count 0 2006.201.20:09:38.19#ibcon#enter sib2, iclass 5, count 0 2006.201.20:09:38.19#ibcon#flushed, iclass 5, count 0 2006.201.20:09:38.19#ibcon#about to write, iclass 5, count 0 2006.201.20:09:38.19#ibcon#wrote, iclass 5, count 0 2006.201.20:09:38.19#ibcon#about to read 3, iclass 5, count 0 2006.201.20:09:38.22#ibcon#read 3, iclass 5, count 0 2006.201.20:09:38.22#ibcon#about to read 4, iclass 5, count 0 2006.201.20:09:38.22#ibcon#read 4, iclass 5, count 0 2006.201.20:09:38.22#ibcon#about to read 5, iclass 5, count 0 2006.201.20:09:38.22#ibcon#read 5, iclass 5, count 0 2006.201.20:09:38.22#ibcon#about to read 6, iclass 5, count 0 2006.201.20:09:38.22#ibcon#read 6, iclass 5, count 0 2006.201.20:09:38.22#ibcon#end of sib2, iclass 5, count 0 2006.201.20:09:38.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.20:09:38.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.20:09:38.22#ibcon#[25=USB\r\n] 2006.201.20:09:38.22#ibcon#*before write, iclass 5, count 0 2006.201.20:09:38.22#ibcon#enter sib2, iclass 5, count 0 2006.201.20:09:38.22#ibcon#flushed, iclass 5, count 0 2006.201.20:09:38.22#ibcon#about to write, iclass 5, count 0 2006.201.20:09:38.22#ibcon#wrote, iclass 5, count 0 2006.201.20:09:38.22#ibcon#about to read 3, iclass 5, count 0 2006.201.20:09:38.25#ibcon#read 3, iclass 5, count 0 2006.201.20:09:38.25#ibcon#about to read 4, iclass 5, count 0 2006.201.20:09:38.25#ibcon#read 4, iclass 5, count 0 2006.201.20:09:38.25#ibcon#about to read 5, iclass 5, count 0 2006.201.20:09:38.25#ibcon#read 5, iclass 5, count 0 2006.201.20:09:38.25#ibcon#about to read 6, iclass 5, count 0 2006.201.20:09:38.25#ibcon#read 6, iclass 5, count 0 2006.201.20:09:38.25#ibcon#end of sib2, iclass 5, count 0 2006.201.20:09:38.25#ibcon#*after write, iclass 5, count 0 2006.201.20:09:38.25#ibcon#*before return 0, iclass 5, count 0 2006.201.20:09:38.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:38.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:38.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.20:09:38.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.20:09:38.25$vck44/valo=2,534.99 2006.201.20:09:38.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.20:09:38.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.20:09:38.25#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:38.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:38.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:38.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:38.25#ibcon#enter wrdev, iclass 7, count 0 2006.201.20:09:38.25#ibcon#first serial, iclass 7, count 0 2006.201.20:09:38.25#ibcon#enter sib2, iclass 7, count 0 2006.201.20:09:38.25#ibcon#flushed, iclass 7, count 0 2006.201.20:09:38.25#ibcon#about to write, iclass 7, count 0 2006.201.20:09:38.25#ibcon#wrote, iclass 7, count 0 2006.201.20:09:38.25#ibcon#about to read 3, iclass 7, count 0 2006.201.20:09:38.27#ibcon#read 3, iclass 7, count 0 2006.201.20:09:38.27#ibcon#about to read 4, iclass 7, count 0 2006.201.20:09:38.27#ibcon#read 4, iclass 7, count 0 2006.201.20:09:38.27#ibcon#about to read 5, iclass 7, count 0 2006.201.20:09:38.27#ibcon#read 5, iclass 7, count 0 2006.201.20:09:38.27#ibcon#about to read 6, iclass 7, count 0 2006.201.20:09:38.27#ibcon#read 6, iclass 7, count 0 2006.201.20:09:38.27#ibcon#end of sib2, iclass 7, count 0 2006.201.20:09:38.27#ibcon#*mode == 0, iclass 7, count 0 2006.201.20:09:38.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.20:09:38.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:09:38.27#ibcon#*before write, iclass 7, count 0 2006.201.20:09:38.27#ibcon#enter sib2, iclass 7, count 0 2006.201.20:09:38.27#ibcon#flushed, iclass 7, count 0 2006.201.20:09:38.27#ibcon#about to write, iclass 7, count 0 2006.201.20:09:38.27#ibcon#wrote, iclass 7, count 0 2006.201.20:09:38.27#ibcon#about to read 3, iclass 7, count 0 2006.201.20:09:38.31#ibcon#read 3, iclass 7, count 0 2006.201.20:09:38.31#ibcon#about to read 4, iclass 7, count 0 2006.201.20:09:38.31#ibcon#read 4, iclass 7, count 0 2006.201.20:09:38.31#ibcon#about to read 5, iclass 7, count 0 2006.201.20:09:38.31#ibcon#read 5, iclass 7, count 0 2006.201.20:09:38.31#ibcon#about to read 6, iclass 7, count 0 2006.201.20:09:38.31#ibcon#read 6, iclass 7, count 0 2006.201.20:09:38.31#ibcon#end of sib2, iclass 7, count 0 2006.201.20:09:38.31#ibcon#*after write, iclass 7, count 0 2006.201.20:09:38.31#ibcon#*before return 0, iclass 7, count 0 2006.201.20:09:38.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:38.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:38.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.20:09:38.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.20:09:38.31$vck44/va=2,7 2006.201.20:09:38.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.20:09:38.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.20:09:38.31#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:38.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:38.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:38.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:38.37#ibcon#enter wrdev, iclass 11, count 2 2006.201.20:09:38.37#ibcon#first serial, iclass 11, count 2 2006.201.20:09:38.37#ibcon#enter sib2, iclass 11, count 2 2006.201.20:09:38.37#ibcon#flushed, iclass 11, count 2 2006.201.20:09:38.37#ibcon#about to write, iclass 11, count 2 2006.201.20:09:38.37#ibcon#wrote, iclass 11, count 2 2006.201.20:09:38.37#ibcon#about to read 3, iclass 11, count 2 2006.201.20:09:38.39#ibcon#read 3, iclass 11, count 2 2006.201.20:09:38.39#ibcon#about to read 4, iclass 11, count 2 2006.201.20:09:38.39#ibcon#read 4, iclass 11, count 2 2006.201.20:09:38.39#ibcon#about to read 5, iclass 11, count 2 2006.201.20:09:38.39#ibcon#read 5, iclass 11, count 2 2006.201.20:09:38.39#ibcon#about to read 6, iclass 11, count 2 2006.201.20:09:38.39#ibcon#read 6, iclass 11, count 2 2006.201.20:09:38.39#ibcon#end of sib2, iclass 11, count 2 2006.201.20:09:38.39#ibcon#*mode == 0, iclass 11, count 2 2006.201.20:09:38.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.20:09:38.39#ibcon#[25=AT02-07\r\n] 2006.201.20:09:38.39#ibcon#*before write, iclass 11, count 2 2006.201.20:09:38.39#ibcon#enter sib2, iclass 11, count 2 2006.201.20:09:38.39#ibcon#flushed, iclass 11, count 2 2006.201.20:09:38.39#ibcon#about to write, iclass 11, count 2 2006.201.20:09:38.39#ibcon#wrote, iclass 11, count 2 2006.201.20:09:38.39#ibcon#about to read 3, iclass 11, count 2 2006.201.20:09:38.42#ibcon#read 3, iclass 11, count 2 2006.201.20:09:38.42#ibcon#about to read 4, iclass 11, count 2 2006.201.20:09:38.42#ibcon#read 4, iclass 11, count 2 2006.201.20:09:38.42#ibcon#about to read 5, iclass 11, count 2 2006.201.20:09:38.42#ibcon#read 5, iclass 11, count 2 2006.201.20:09:38.42#ibcon#about to read 6, iclass 11, count 2 2006.201.20:09:38.42#ibcon#read 6, iclass 11, count 2 2006.201.20:09:38.42#ibcon#end of sib2, iclass 11, count 2 2006.201.20:09:38.42#ibcon#*after write, iclass 11, count 2 2006.201.20:09:38.42#ibcon#*before return 0, iclass 11, count 2 2006.201.20:09:38.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:38.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:38.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.20:09:38.42#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:38.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:38.48#abcon#<5=/04 2.5 4.6 20.151001001.9\r\n> 2006.201.20:09:38.50#abcon#{5=INTERFACE CLEAR} 2006.201.20:09:38.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:38.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:38.54#ibcon#enter wrdev, iclass 11, count 0 2006.201.20:09:38.54#ibcon#first serial, iclass 11, count 0 2006.201.20:09:38.54#ibcon#enter sib2, iclass 11, count 0 2006.201.20:09:38.54#ibcon#flushed, iclass 11, count 0 2006.201.20:09:38.54#ibcon#about to write, iclass 11, count 0 2006.201.20:09:38.54#ibcon#wrote, iclass 11, count 0 2006.201.20:09:38.54#ibcon#about to read 3, iclass 11, count 0 2006.201.20:09:38.56#ibcon#read 3, iclass 11, count 0 2006.201.20:09:38.56#ibcon#about to read 4, iclass 11, count 0 2006.201.20:09:38.56#ibcon#read 4, iclass 11, count 0 2006.201.20:09:38.56#ibcon#about to read 5, iclass 11, count 0 2006.201.20:09:38.56#ibcon#read 5, iclass 11, count 0 2006.201.20:09:38.56#ibcon#about to read 6, iclass 11, count 0 2006.201.20:09:38.56#ibcon#read 6, iclass 11, count 0 2006.201.20:09:38.56#ibcon#end of sib2, iclass 11, count 0 2006.201.20:09:38.56#ibcon#*mode == 0, iclass 11, count 0 2006.201.20:09:38.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.20:09:38.56#ibcon#[25=USB\r\n] 2006.201.20:09:38.56#ibcon#*before write, iclass 11, count 0 2006.201.20:09:38.56#ibcon#enter sib2, iclass 11, count 0 2006.201.20:09:38.56#ibcon#flushed, iclass 11, count 0 2006.201.20:09:38.56#ibcon#about to write, iclass 11, count 0 2006.201.20:09:38.56#ibcon#wrote, iclass 11, count 0 2006.201.20:09:38.56#ibcon#about to read 3, iclass 11, count 0 2006.201.20:09:38.56#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:09:38.60#ibcon#read 3, iclass 11, count 0 2006.201.20:09:38.60#ibcon#about to read 4, iclass 11, count 0 2006.201.20:09:38.60#ibcon#read 4, iclass 11, count 0 2006.201.20:09:38.60#ibcon#about to read 5, iclass 11, count 0 2006.201.20:09:38.60#ibcon#read 5, iclass 11, count 0 2006.201.20:09:38.60#ibcon#about to read 6, iclass 11, count 0 2006.201.20:09:38.60#ibcon#read 6, iclass 11, count 0 2006.201.20:09:38.60#ibcon#end of sib2, iclass 11, count 0 2006.201.20:09:38.60#ibcon#*after write, iclass 11, count 0 2006.201.20:09:38.60#ibcon#*before return 0, iclass 11, count 0 2006.201.20:09:38.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:38.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:38.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.20:09:38.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.20:09:38.60$vck44/valo=3,564.99 2006.201.20:09:38.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.20:09:38.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.20:09:38.60#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:38.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:38.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:38.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:38.60#ibcon#enter wrdev, iclass 17, count 0 2006.201.20:09:38.60#ibcon#first serial, iclass 17, count 0 2006.201.20:09:38.60#ibcon#enter sib2, iclass 17, count 0 2006.201.20:09:38.60#ibcon#flushed, iclass 17, count 0 2006.201.20:09:38.60#ibcon#about to write, iclass 17, count 0 2006.201.20:09:38.60#ibcon#wrote, iclass 17, count 0 2006.201.20:09:38.60#ibcon#about to read 3, iclass 17, count 0 2006.201.20:09:38.62#ibcon#read 3, iclass 17, count 0 2006.201.20:09:38.62#ibcon#about to read 4, iclass 17, count 0 2006.201.20:09:38.62#ibcon#read 4, iclass 17, count 0 2006.201.20:09:38.62#ibcon#about to read 5, iclass 17, count 0 2006.201.20:09:38.62#ibcon#read 5, iclass 17, count 0 2006.201.20:09:38.62#ibcon#about to read 6, iclass 17, count 0 2006.201.20:09:38.62#ibcon#read 6, iclass 17, count 0 2006.201.20:09:38.62#ibcon#end of sib2, iclass 17, count 0 2006.201.20:09:38.62#ibcon#*mode == 0, iclass 17, count 0 2006.201.20:09:38.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.20:09:38.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:09:38.62#ibcon#*before write, iclass 17, count 0 2006.201.20:09:38.62#ibcon#enter sib2, iclass 17, count 0 2006.201.20:09:38.62#ibcon#flushed, iclass 17, count 0 2006.201.20:09:38.62#ibcon#about to write, iclass 17, count 0 2006.201.20:09:38.62#ibcon#wrote, iclass 17, count 0 2006.201.20:09:38.62#ibcon#about to read 3, iclass 17, count 0 2006.201.20:09:38.66#ibcon#read 3, iclass 17, count 0 2006.201.20:09:38.66#ibcon#about to read 4, iclass 17, count 0 2006.201.20:09:38.66#ibcon#read 4, iclass 17, count 0 2006.201.20:09:38.66#ibcon#about to read 5, iclass 17, count 0 2006.201.20:09:38.66#ibcon#read 5, iclass 17, count 0 2006.201.20:09:38.66#ibcon#about to read 6, iclass 17, count 0 2006.201.20:09:38.66#ibcon#read 6, iclass 17, count 0 2006.201.20:09:38.66#ibcon#end of sib2, iclass 17, count 0 2006.201.20:09:38.66#ibcon#*after write, iclass 17, count 0 2006.201.20:09:38.66#ibcon#*before return 0, iclass 17, count 0 2006.201.20:09:38.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:38.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:38.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.20:09:38.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.20:09:38.66$vck44/va=3,8 2006.201.20:09:38.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.20:09:38.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.20:09:38.66#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:38.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:38.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:38.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:38.72#ibcon#enter wrdev, iclass 19, count 2 2006.201.20:09:38.72#ibcon#first serial, iclass 19, count 2 2006.201.20:09:38.72#ibcon#enter sib2, iclass 19, count 2 2006.201.20:09:38.72#ibcon#flushed, iclass 19, count 2 2006.201.20:09:38.72#ibcon#about to write, iclass 19, count 2 2006.201.20:09:38.72#ibcon#wrote, iclass 19, count 2 2006.201.20:09:38.72#ibcon#about to read 3, iclass 19, count 2 2006.201.20:09:38.74#ibcon#read 3, iclass 19, count 2 2006.201.20:09:38.74#ibcon#about to read 4, iclass 19, count 2 2006.201.20:09:38.74#ibcon#read 4, iclass 19, count 2 2006.201.20:09:38.74#ibcon#about to read 5, iclass 19, count 2 2006.201.20:09:38.74#ibcon#read 5, iclass 19, count 2 2006.201.20:09:38.74#ibcon#about to read 6, iclass 19, count 2 2006.201.20:09:38.74#ibcon#read 6, iclass 19, count 2 2006.201.20:09:38.74#ibcon#end of sib2, iclass 19, count 2 2006.201.20:09:38.74#ibcon#*mode == 0, iclass 19, count 2 2006.201.20:09:38.74#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.20:09:38.74#ibcon#[25=AT03-08\r\n] 2006.201.20:09:38.74#ibcon#*before write, iclass 19, count 2 2006.201.20:09:38.74#ibcon#enter sib2, iclass 19, count 2 2006.201.20:09:38.74#ibcon#flushed, iclass 19, count 2 2006.201.20:09:38.74#ibcon#about to write, iclass 19, count 2 2006.201.20:09:38.74#ibcon#wrote, iclass 19, count 2 2006.201.20:09:38.74#ibcon#about to read 3, iclass 19, count 2 2006.201.20:09:38.77#ibcon#read 3, iclass 19, count 2 2006.201.20:09:38.77#ibcon#about to read 4, iclass 19, count 2 2006.201.20:09:38.77#ibcon#read 4, iclass 19, count 2 2006.201.20:09:38.77#ibcon#about to read 5, iclass 19, count 2 2006.201.20:09:38.77#ibcon#read 5, iclass 19, count 2 2006.201.20:09:38.77#ibcon#about to read 6, iclass 19, count 2 2006.201.20:09:38.77#ibcon#read 6, iclass 19, count 2 2006.201.20:09:38.77#ibcon#end of sib2, iclass 19, count 2 2006.201.20:09:38.77#ibcon#*after write, iclass 19, count 2 2006.201.20:09:38.77#ibcon#*before return 0, iclass 19, count 2 2006.201.20:09:38.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:38.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:38.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.20:09:38.77#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:38.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:38.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:38.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:38.89#ibcon#enter wrdev, iclass 19, count 0 2006.201.20:09:38.89#ibcon#first serial, iclass 19, count 0 2006.201.20:09:38.89#ibcon#enter sib2, iclass 19, count 0 2006.201.20:09:38.89#ibcon#flushed, iclass 19, count 0 2006.201.20:09:38.89#ibcon#about to write, iclass 19, count 0 2006.201.20:09:38.89#ibcon#wrote, iclass 19, count 0 2006.201.20:09:38.89#ibcon#about to read 3, iclass 19, count 0 2006.201.20:09:38.91#ibcon#read 3, iclass 19, count 0 2006.201.20:09:38.91#ibcon#about to read 4, iclass 19, count 0 2006.201.20:09:38.91#ibcon#read 4, iclass 19, count 0 2006.201.20:09:38.91#ibcon#about to read 5, iclass 19, count 0 2006.201.20:09:38.91#ibcon#read 5, iclass 19, count 0 2006.201.20:09:38.91#ibcon#about to read 6, iclass 19, count 0 2006.201.20:09:38.91#ibcon#read 6, iclass 19, count 0 2006.201.20:09:38.91#ibcon#end of sib2, iclass 19, count 0 2006.201.20:09:38.91#ibcon#*mode == 0, iclass 19, count 0 2006.201.20:09:38.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.20:09:38.91#ibcon#[25=USB\r\n] 2006.201.20:09:38.91#ibcon#*before write, iclass 19, count 0 2006.201.20:09:38.91#ibcon#enter sib2, iclass 19, count 0 2006.201.20:09:38.91#ibcon#flushed, iclass 19, count 0 2006.201.20:09:38.91#ibcon#about to write, iclass 19, count 0 2006.201.20:09:38.91#ibcon#wrote, iclass 19, count 0 2006.201.20:09:38.91#ibcon#about to read 3, iclass 19, count 0 2006.201.20:09:38.94#ibcon#read 3, iclass 19, count 0 2006.201.20:09:38.94#ibcon#about to read 4, iclass 19, count 0 2006.201.20:09:38.94#ibcon#read 4, iclass 19, count 0 2006.201.20:09:38.94#ibcon#about to read 5, iclass 19, count 0 2006.201.20:09:38.94#ibcon#read 5, iclass 19, count 0 2006.201.20:09:38.94#ibcon#about to read 6, iclass 19, count 0 2006.201.20:09:38.94#ibcon#read 6, iclass 19, count 0 2006.201.20:09:38.94#ibcon#end of sib2, iclass 19, count 0 2006.201.20:09:38.94#ibcon#*after write, iclass 19, count 0 2006.201.20:09:38.94#ibcon#*before return 0, iclass 19, count 0 2006.201.20:09:38.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:38.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:38.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.20:09:38.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.20:09:38.94$vck44/valo=4,624.99 2006.201.20:09:38.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.20:09:38.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.20:09:38.94#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:38.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:38.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:38.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:38.94#ibcon#enter wrdev, iclass 21, count 0 2006.201.20:09:38.94#ibcon#first serial, iclass 21, count 0 2006.201.20:09:38.94#ibcon#enter sib2, iclass 21, count 0 2006.201.20:09:38.94#ibcon#flushed, iclass 21, count 0 2006.201.20:09:38.94#ibcon#about to write, iclass 21, count 0 2006.201.20:09:38.94#ibcon#wrote, iclass 21, count 0 2006.201.20:09:38.94#ibcon#about to read 3, iclass 21, count 0 2006.201.20:09:38.96#ibcon#read 3, iclass 21, count 0 2006.201.20:09:38.96#ibcon#about to read 4, iclass 21, count 0 2006.201.20:09:38.96#ibcon#read 4, iclass 21, count 0 2006.201.20:09:38.96#ibcon#about to read 5, iclass 21, count 0 2006.201.20:09:38.96#ibcon#read 5, iclass 21, count 0 2006.201.20:09:38.96#ibcon#about to read 6, iclass 21, count 0 2006.201.20:09:38.96#ibcon#read 6, iclass 21, count 0 2006.201.20:09:38.96#ibcon#end of sib2, iclass 21, count 0 2006.201.20:09:38.96#ibcon#*mode == 0, iclass 21, count 0 2006.201.20:09:38.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.20:09:38.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:09:38.96#ibcon#*before write, iclass 21, count 0 2006.201.20:09:38.96#ibcon#enter sib2, iclass 21, count 0 2006.201.20:09:38.96#ibcon#flushed, iclass 21, count 0 2006.201.20:09:38.96#ibcon#about to write, iclass 21, count 0 2006.201.20:09:38.96#ibcon#wrote, iclass 21, count 0 2006.201.20:09:38.96#ibcon#about to read 3, iclass 21, count 0 2006.201.20:09:39.00#ibcon#read 3, iclass 21, count 0 2006.201.20:09:39.00#ibcon#about to read 4, iclass 21, count 0 2006.201.20:09:39.00#ibcon#read 4, iclass 21, count 0 2006.201.20:09:39.00#ibcon#about to read 5, iclass 21, count 0 2006.201.20:09:39.00#ibcon#read 5, iclass 21, count 0 2006.201.20:09:39.00#ibcon#about to read 6, iclass 21, count 0 2006.201.20:09:39.00#ibcon#read 6, iclass 21, count 0 2006.201.20:09:39.00#ibcon#end of sib2, iclass 21, count 0 2006.201.20:09:39.00#ibcon#*after write, iclass 21, count 0 2006.201.20:09:39.00#ibcon#*before return 0, iclass 21, count 0 2006.201.20:09:39.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:39.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:39.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.20:09:39.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.20:09:39.00$vck44/va=4,7 2006.201.20:09:39.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.20:09:39.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.20:09:39.00#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:39.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:39.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:39.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:39.06#ibcon#enter wrdev, iclass 23, count 2 2006.201.20:09:39.06#ibcon#first serial, iclass 23, count 2 2006.201.20:09:39.06#ibcon#enter sib2, iclass 23, count 2 2006.201.20:09:39.06#ibcon#flushed, iclass 23, count 2 2006.201.20:09:39.06#ibcon#about to write, iclass 23, count 2 2006.201.20:09:39.06#ibcon#wrote, iclass 23, count 2 2006.201.20:09:39.06#ibcon#about to read 3, iclass 23, count 2 2006.201.20:09:39.08#ibcon#read 3, iclass 23, count 2 2006.201.20:09:39.08#ibcon#about to read 4, iclass 23, count 2 2006.201.20:09:39.08#ibcon#read 4, iclass 23, count 2 2006.201.20:09:39.08#ibcon#about to read 5, iclass 23, count 2 2006.201.20:09:39.08#ibcon#read 5, iclass 23, count 2 2006.201.20:09:39.08#ibcon#about to read 6, iclass 23, count 2 2006.201.20:09:39.08#ibcon#read 6, iclass 23, count 2 2006.201.20:09:39.08#ibcon#end of sib2, iclass 23, count 2 2006.201.20:09:39.08#ibcon#*mode == 0, iclass 23, count 2 2006.201.20:09:39.08#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.20:09:39.08#ibcon#[25=AT04-07\r\n] 2006.201.20:09:39.08#ibcon#*before write, iclass 23, count 2 2006.201.20:09:39.08#ibcon#enter sib2, iclass 23, count 2 2006.201.20:09:39.08#ibcon#flushed, iclass 23, count 2 2006.201.20:09:39.08#ibcon#about to write, iclass 23, count 2 2006.201.20:09:39.08#ibcon#wrote, iclass 23, count 2 2006.201.20:09:39.08#ibcon#about to read 3, iclass 23, count 2 2006.201.20:09:39.11#ibcon#read 3, iclass 23, count 2 2006.201.20:09:39.11#ibcon#about to read 4, iclass 23, count 2 2006.201.20:09:39.11#ibcon#read 4, iclass 23, count 2 2006.201.20:09:39.11#ibcon#about to read 5, iclass 23, count 2 2006.201.20:09:39.11#ibcon#read 5, iclass 23, count 2 2006.201.20:09:39.11#ibcon#about to read 6, iclass 23, count 2 2006.201.20:09:39.11#ibcon#read 6, iclass 23, count 2 2006.201.20:09:39.11#ibcon#end of sib2, iclass 23, count 2 2006.201.20:09:39.11#ibcon#*after write, iclass 23, count 2 2006.201.20:09:39.11#ibcon#*before return 0, iclass 23, count 2 2006.201.20:09:39.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:39.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:39.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.20:09:39.11#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:39.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:39.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:39.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:39.23#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:09:39.23#ibcon#first serial, iclass 23, count 0 2006.201.20:09:39.23#ibcon#enter sib2, iclass 23, count 0 2006.201.20:09:39.23#ibcon#flushed, iclass 23, count 0 2006.201.20:09:39.23#ibcon#about to write, iclass 23, count 0 2006.201.20:09:39.23#ibcon#wrote, iclass 23, count 0 2006.201.20:09:39.23#ibcon#about to read 3, iclass 23, count 0 2006.201.20:09:39.25#ibcon#read 3, iclass 23, count 0 2006.201.20:09:39.25#ibcon#about to read 4, iclass 23, count 0 2006.201.20:09:39.25#ibcon#read 4, iclass 23, count 0 2006.201.20:09:39.25#ibcon#about to read 5, iclass 23, count 0 2006.201.20:09:39.25#ibcon#read 5, iclass 23, count 0 2006.201.20:09:39.25#ibcon#about to read 6, iclass 23, count 0 2006.201.20:09:39.25#ibcon#read 6, iclass 23, count 0 2006.201.20:09:39.25#ibcon#end of sib2, iclass 23, count 0 2006.201.20:09:39.25#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:09:39.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:09:39.25#ibcon#[25=USB\r\n] 2006.201.20:09:39.25#ibcon#*before write, iclass 23, count 0 2006.201.20:09:39.25#ibcon#enter sib2, iclass 23, count 0 2006.201.20:09:39.25#ibcon#flushed, iclass 23, count 0 2006.201.20:09:39.25#ibcon#about to write, iclass 23, count 0 2006.201.20:09:39.25#ibcon#wrote, iclass 23, count 0 2006.201.20:09:39.25#ibcon#about to read 3, iclass 23, count 0 2006.201.20:09:39.28#ibcon#read 3, iclass 23, count 0 2006.201.20:09:39.28#ibcon#about to read 4, iclass 23, count 0 2006.201.20:09:39.28#ibcon#read 4, iclass 23, count 0 2006.201.20:09:39.28#ibcon#about to read 5, iclass 23, count 0 2006.201.20:09:39.28#ibcon#read 5, iclass 23, count 0 2006.201.20:09:39.28#ibcon#about to read 6, iclass 23, count 0 2006.201.20:09:39.28#ibcon#read 6, iclass 23, count 0 2006.201.20:09:39.28#ibcon#end of sib2, iclass 23, count 0 2006.201.20:09:39.28#ibcon#*after write, iclass 23, count 0 2006.201.20:09:39.28#ibcon#*before return 0, iclass 23, count 0 2006.201.20:09:39.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:39.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:39.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:09:39.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:09:39.28$vck44/valo=5,734.99 2006.201.20:09:39.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.20:09:39.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.20:09:39.28#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:39.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:39.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:39.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:39.28#ibcon#enter wrdev, iclass 25, count 0 2006.201.20:09:39.28#ibcon#first serial, iclass 25, count 0 2006.201.20:09:39.28#ibcon#enter sib2, iclass 25, count 0 2006.201.20:09:39.28#ibcon#flushed, iclass 25, count 0 2006.201.20:09:39.28#ibcon#about to write, iclass 25, count 0 2006.201.20:09:39.28#ibcon#wrote, iclass 25, count 0 2006.201.20:09:39.28#ibcon#about to read 3, iclass 25, count 0 2006.201.20:09:39.30#ibcon#read 3, iclass 25, count 0 2006.201.20:09:39.30#ibcon#about to read 4, iclass 25, count 0 2006.201.20:09:39.30#ibcon#read 4, iclass 25, count 0 2006.201.20:09:39.30#ibcon#about to read 5, iclass 25, count 0 2006.201.20:09:39.30#ibcon#read 5, iclass 25, count 0 2006.201.20:09:39.30#ibcon#about to read 6, iclass 25, count 0 2006.201.20:09:39.30#ibcon#read 6, iclass 25, count 0 2006.201.20:09:39.30#ibcon#end of sib2, iclass 25, count 0 2006.201.20:09:39.30#ibcon#*mode == 0, iclass 25, count 0 2006.201.20:09:39.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.20:09:39.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:09:39.30#ibcon#*before write, iclass 25, count 0 2006.201.20:09:39.30#ibcon#enter sib2, iclass 25, count 0 2006.201.20:09:39.30#ibcon#flushed, iclass 25, count 0 2006.201.20:09:39.30#ibcon#about to write, iclass 25, count 0 2006.201.20:09:39.30#ibcon#wrote, iclass 25, count 0 2006.201.20:09:39.30#ibcon#about to read 3, iclass 25, count 0 2006.201.20:09:39.34#ibcon#read 3, iclass 25, count 0 2006.201.20:09:39.34#ibcon#about to read 4, iclass 25, count 0 2006.201.20:09:39.34#ibcon#read 4, iclass 25, count 0 2006.201.20:09:39.34#ibcon#about to read 5, iclass 25, count 0 2006.201.20:09:39.34#ibcon#read 5, iclass 25, count 0 2006.201.20:09:39.34#ibcon#about to read 6, iclass 25, count 0 2006.201.20:09:39.34#ibcon#read 6, iclass 25, count 0 2006.201.20:09:39.34#ibcon#end of sib2, iclass 25, count 0 2006.201.20:09:39.34#ibcon#*after write, iclass 25, count 0 2006.201.20:09:39.34#ibcon#*before return 0, iclass 25, count 0 2006.201.20:09:39.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:39.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:39.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.20:09:39.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.20:09:39.34$vck44/va=5,4 2006.201.20:09:39.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.20:09:39.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.20:09:39.34#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:39.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:39.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:39.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:39.40#ibcon#enter wrdev, iclass 27, count 2 2006.201.20:09:39.40#ibcon#first serial, iclass 27, count 2 2006.201.20:09:39.40#ibcon#enter sib2, iclass 27, count 2 2006.201.20:09:39.40#ibcon#flushed, iclass 27, count 2 2006.201.20:09:39.40#ibcon#about to write, iclass 27, count 2 2006.201.20:09:39.40#ibcon#wrote, iclass 27, count 2 2006.201.20:09:39.40#ibcon#about to read 3, iclass 27, count 2 2006.201.20:09:39.42#ibcon#read 3, iclass 27, count 2 2006.201.20:09:39.42#ibcon#about to read 4, iclass 27, count 2 2006.201.20:09:39.42#ibcon#read 4, iclass 27, count 2 2006.201.20:09:39.42#ibcon#about to read 5, iclass 27, count 2 2006.201.20:09:39.42#ibcon#read 5, iclass 27, count 2 2006.201.20:09:39.42#ibcon#about to read 6, iclass 27, count 2 2006.201.20:09:39.42#ibcon#read 6, iclass 27, count 2 2006.201.20:09:39.42#ibcon#end of sib2, iclass 27, count 2 2006.201.20:09:39.42#ibcon#*mode == 0, iclass 27, count 2 2006.201.20:09:39.42#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.20:09:39.42#ibcon#[25=AT05-04\r\n] 2006.201.20:09:39.42#ibcon#*before write, iclass 27, count 2 2006.201.20:09:39.42#ibcon#enter sib2, iclass 27, count 2 2006.201.20:09:39.42#ibcon#flushed, iclass 27, count 2 2006.201.20:09:39.42#ibcon#about to write, iclass 27, count 2 2006.201.20:09:39.42#ibcon#wrote, iclass 27, count 2 2006.201.20:09:39.42#ibcon#about to read 3, iclass 27, count 2 2006.201.20:09:39.45#ibcon#read 3, iclass 27, count 2 2006.201.20:09:39.45#ibcon#about to read 4, iclass 27, count 2 2006.201.20:09:39.45#ibcon#read 4, iclass 27, count 2 2006.201.20:09:39.45#ibcon#about to read 5, iclass 27, count 2 2006.201.20:09:39.45#ibcon#read 5, iclass 27, count 2 2006.201.20:09:39.45#ibcon#about to read 6, iclass 27, count 2 2006.201.20:09:39.45#ibcon#read 6, iclass 27, count 2 2006.201.20:09:39.45#ibcon#end of sib2, iclass 27, count 2 2006.201.20:09:39.45#ibcon#*after write, iclass 27, count 2 2006.201.20:09:39.45#ibcon#*before return 0, iclass 27, count 2 2006.201.20:09:39.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:39.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:39.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.20:09:39.45#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:39.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:39.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:39.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:39.57#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:09:39.57#ibcon#first serial, iclass 27, count 0 2006.201.20:09:39.57#ibcon#enter sib2, iclass 27, count 0 2006.201.20:09:39.57#ibcon#flushed, iclass 27, count 0 2006.201.20:09:39.57#ibcon#about to write, iclass 27, count 0 2006.201.20:09:39.57#ibcon#wrote, iclass 27, count 0 2006.201.20:09:39.57#ibcon#about to read 3, iclass 27, count 0 2006.201.20:09:39.59#ibcon#read 3, iclass 27, count 0 2006.201.20:09:39.59#ibcon#about to read 4, iclass 27, count 0 2006.201.20:09:39.59#ibcon#read 4, iclass 27, count 0 2006.201.20:09:39.59#ibcon#about to read 5, iclass 27, count 0 2006.201.20:09:39.59#ibcon#read 5, iclass 27, count 0 2006.201.20:09:39.59#ibcon#about to read 6, iclass 27, count 0 2006.201.20:09:39.59#ibcon#read 6, iclass 27, count 0 2006.201.20:09:39.59#ibcon#end of sib2, iclass 27, count 0 2006.201.20:09:39.59#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:09:39.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:09:39.59#ibcon#[25=USB\r\n] 2006.201.20:09:39.59#ibcon#*before write, iclass 27, count 0 2006.201.20:09:39.59#ibcon#enter sib2, iclass 27, count 0 2006.201.20:09:39.59#ibcon#flushed, iclass 27, count 0 2006.201.20:09:39.59#ibcon#about to write, iclass 27, count 0 2006.201.20:09:39.59#ibcon#wrote, iclass 27, count 0 2006.201.20:09:39.59#ibcon#about to read 3, iclass 27, count 0 2006.201.20:09:39.62#ibcon#read 3, iclass 27, count 0 2006.201.20:09:39.62#ibcon#about to read 4, iclass 27, count 0 2006.201.20:09:39.62#ibcon#read 4, iclass 27, count 0 2006.201.20:09:39.62#ibcon#about to read 5, iclass 27, count 0 2006.201.20:09:39.62#ibcon#read 5, iclass 27, count 0 2006.201.20:09:39.62#ibcon#about to read 6, iclass 27, count 0 2006.201.20:09:39.62#ibcon#read 6, iclass 27, count 0 2006.201.20:09:39.62#ibcon#end of sib2, iclass 27, count 0 2006.201.20:09:39.62#ibcon#*after write, iclass 27, count 0 2006.201.20:09:39.62#ibcon#*before return 0, iclass 27, count 0 2006.201.20:09:39.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:39.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:39.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:09:39.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:09:39.62$vck44/valo=6,814.99 2006.201.20:09:39.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.20:09:39.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.20:09:39.62#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:39.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:39.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:39.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:39.62#ibcon#enter wrdev, iclass 29, count 0 2006.201.20:09:39.62#ibcon#first serial, iclass 29, count 0 2006.201.20:09:39.62#ibcon#enter sib2, iclass 29, count 0 2006.201.20:09:39.62#ibcon#flushed, iclass 29, count 0 2006.201.20:09:39.62#ibcon#about to write, iclass 29, count 0 2006.201.20:09:39.62#ibcon#wrote, iclass 29, count 0 2006.201.20:09:39.62#ibcon#about to read 3, iclass 29, count 0 2006.201.20:09:39.64#ibcon#read 3, iclass 29, count 0 2006.201.20:09:39.64#ibcon#about to read 4, iclass 29, count 0 2006.201.20:09:39.64#ibcon#read 4, iclass 29, count 0 2006.201.20:09:39.64#ibcon#about to read 5, iclass 29, count 0 2006.201.20:09:39.64#ibcon#read 5, iclass 29, count 0 2006.201.20:09:39.64#ibcon#about to read 6, iclass 29, count 0 2006.201.20:09:39.64#ibcon#read 6, iclass 29, count 0 2006.201.20:09:39.64#ibcon#end of sib2, iclass 29, count 0 2006.201.20:09:39.64#ibcon#*mode == 0, iclass 29, count 0 2006.201.20:09:39.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.20:09:39.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:09:39.64#ibcon#*before write, iclass 29, count 0 2006.201.20:09:39.64#ibcon#enter sib2, iclass 29, count 0 2006.201.20:09:39.64#ibcon#flushed, iclass 29, count 0 2006.201.20:09:39.64#ibcon#about to write, iclass 29, count 0 2006.201.20:09:39.64#ibcon#wrote, iclass 29, count 0 2006.201.20:09:39.64#ibcon#about to read 3, iclass 29, count 0 2006.201.20:09:39.69#ibcon#read 3, iclass 29, count 0 2006.201.20:09:39.69#ibcon#about to read 4, iclass 29, count 0 2006.201.20:09:39.69#ibcon#read 4, iclass 29, count 0 2006.201.20:09:39.69#ibcon#about to read 5, iclass 29, count 0 2006.201.20:09:39.69#ibcon#read 5, iclass 29, count 0 2006.201.20:09:39.69#ibcon#about to read 6, iclass 29, count 0 2006.201.20:09:39.69#ibcon#read 6, iclass 29, count 0 2006.201.20:09:39.69#ibcon#end of sib2, iclass 29, count 0 2006.201.20:09:39.69#ibcon#*after write, iclass 29, count 0 2006.201.20:09:39.69#ibcon#*before return 0, iclass 29, count 0 2006.201.20:09:39.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:39.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:39.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.20:09:39.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.20:09:39.69$vck44/va=6,5 2006.201.20:09:39.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.20:09:39.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.20:09:39.69#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:39.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:39.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:39.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:39.74#ibcon#enter wrdev, iclass 31, count 2 2006.201.20:09:39.74#ibcon#first serial, iclass 31, count 2 2006.201.20:09:39.74#ibcon#enter sib2, iclass 31, count 2 2006.201.20:09:39.74#ibcon#flushed, iclass 31, count 2 2006.201.20:09:39.74#ibcon#about to write, iclass 31, count 2 2006.201.20:09:39.74#ibcon#wrote, iclass 31, count 2 2006.201.20:09:39.74#ibcon#about to read 3, iclass 31, count 2 2006.201.20:09:39.76#ibcon#read 3, iclass 31, count 2 2006.201.20:09:39.76#ibcon#about to read 4, iclass 31, count 2 2006.201.20:09:39.76#ibcon#read 4, iclass 31, count 2 2006.201.20:09:39.76#ibcon#about to read 5, iclass 31, count 2 2006.201.20:09:39.76#ibcon#read 5, iclass 31, count 2 2006.201.20:09:39.76#ibcon#about to read 6, iclass 31, count 2 2006.201.20:09:39.76#ibcon#read 6, iclass 31, count 2 2006.201.20:09:39.76#ibcon#end of sib2, iclass 31, count 2 2006.201.20:09:39.76#ibcon#*mode == 0, iclass 31, count 2 2006.201.20:09:39.76#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.20:09:39.76#ibcon#[25=AT06-05\r\n] 2006.201.20:09:39.76#ibcon#*before write, iclass 31, count 2 2006.201.20:09:39.76#ibcon#enter sib2, iclass 31, count 2 2006.201.20:09:39.76#ibcon#flushed, iclass 31, count 2 2006.201.20:09:39.76#ibcon#about to write, iclass 31, count 2 2006.201.20:09:39.76#ibcon#wrote, iclass 31, count 2 2006.201.20:09:39.76#ibcon#about to read 3, iclass 31, count 2 2006.201.20:09:39.79#ibcon#read 3, iclass 31, count 2 2006.201.20:09:39.79#ibcon#about to read 4, iclass 31, count 2 2006.201.20:09:39.79#ibcon#read 4, iclass 31, count 2 2006.201.20:09:39.79#ibcon#about to read 5, iclass 31, count 2 2006.201.20:09:39.79#ibcon#read 5, iclass 31, count 2 2006.201.20:09:39.79#ibcon#about to read 6, iclass 31, count 2 2006.201.20:09:39.79#ibcon#read 6, iclass 31, count 2 2006.201.20:09:39.79#ibcon#end of sib2, iclass 31, count 2 2006.201.20:09:39.79#ibcon#*after write, iclass 31, count 2 2006.201.20:09:39.79#ibcon#*before return 0, iclass 31, count 2 2006.201.20:09:39.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:39.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:39.79#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.20:09:39.79#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:39.79#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:39.91#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:39.91#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:39.91#ibcon#enter wrdev, iclass 31, count 0 2006.201.20:09:39.91#ibcon#first serial, iclass 31, count 0 2006.201.20:09:39.91#ibcon#enter sib2, iclass 31, count 0 2006.201.20:09:39.91#ibcon#flushed, iclass 31, count 0 2006.201.20:09:39.91#ibcon#about to write, iclass 31, count 0 2006.201.20:09:39.91#ibcon#wrote, iclass 31, count 0 2006.201.20:09:39.91#ibcon#about to read 3, iclass 31, count 0 2006.201.20:09:39.93#ibcon#read 3, iclass 31, count 0 2006.201.20:09:39.93#ibcon#about to read 4, iclass 31, count 0 2006.201.20:09:39.93#ibcon#read 4, iclass 31, count 0 2006.201.20:09:39.93#ibcon#about to read 5, iclass 31, count 0 2006.201.20:09:39.93#ibcon#read 5, iclass 31, count 0 2006.201.20:09:39.93#ibcon#about to read 6, iclass 31, count 0 2006.201.20:09:39.93#ibcon#read 6, iclass 31, count 0 2006.201.20:09:39.93#ibcon#end of sib2, iclass 31, count 0 2006.201.20:09:39.93#ibcon#*mode == 0, iclass 31, count 0 2006.201.20:09:39.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.20:09:39.93#ibcon#[25=USB\r\n] 2006.201.20:09:39.93#ibcon#*before write, iclass 31, count 0 2006.201.20:09:39.93#ibcon#enter sib2, iclass 31, count 0 2006.201.20:09:39.93#ibcon#flushed, iclass 31, count 0 2006.201.20:09:39.93#ibcon#about to write, iclass 31, count 0 2006.201.20:09:39.93#ibcon#wrote, iclass 31, count 0 2006.201.20:09:39.93#ibcon#about to read 3, iclass 31, count 0 2006.201.20:09:39.96#ibcon#read 3, iclass 31, count 0 2006.201.20:09:39.96#ibcon#about to read 4, iclass 31, count 0 2006.201.20:09:39.96#ibcon#read 4, iclass 31, count 0 2006.201.20:09:39.96#ibcon#about to read 5, iclass 31, count 0 2006.201.20:09:39.96#ibcon#read 5, iclass 31, count 0 2006.201.20:09:39.96#ibcon#about to read 6, iclass 31, count 0 2006.201.20:09:39.96#ibcon#read 6, iclass 31, count 0 2006.201.20:09:39.96#ibcon#end of sib2, iclass 31, count 0 2006.201.20:09:39.96#ibcon#*after write, iclass 31, count 0 2006.201.20:09:39.96#ibcon#*before return 0, iclass 31, count 0 2006.201.20:09:39.96#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:39.96#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:39.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.20:09:39.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.20:09:39.96$vck44/valo=7,864.99 2006.201.20:09:39.96#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.20:09:39.96#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.20:09:39.96#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:39.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:39.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:39.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:39.96#ibcon#enter wrdev, iclass 33, count 0 2006.201.20:09:39.96#ibcon#first serial, iclass 33, count 0 2006.201.20:09:39.96#ibcon#enter sib2, iclass 33, count 0 2006.201.20:09:39.96#ibcon#flushed, iclass 33, count 0 2006.201.20:09:39.96#ibcon#about to write, iclass 33, count 0 2006.201.20:09:39.96#ibcon#wrote, iclass 33, count 0 2006.201.20:09:39.96#ibcon#about to read 3, iclass 33, count 0 2006.201.20:09:39.98#ibcon#read 3, iclass 33, count 0 2006.201.20:09:39.98#ibcon#about to read 4, iclass 33, count 0 2006.201.20:09:39.98#ibcon#read 4, iclass 33, count 0 2006.201.20:09:39.98#ibcon#about to read 5, iclass 33, count 0 2006.201.20:09:39.98#ibcon#read 5, iclass 33, count 0 2006.201.20:09:39.98#ibcon#about to read 6, iclass 33, count 0 2006.201.20:09:39.98#ibcon#read 6, iclass 33, count 0 2006.201.20:09:39.98#ibcon#end of sib2, iclass 33, count 0 2006.201.20:09:39.98#ibcon#*mode == 0, iclass 33, count 0 2006.201.20:09:39.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.20:09:39.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:09:39.98#ibcon#*before write, iclass 33, count 0 2006.201.20:09:39.98#ibcon#enter sib2, iclass 33, count 0 2006.201.20:09:39.98#ibcon#flushed, iclass 33, count 0 2006.201.20:09:39.98#ibcon#about to write, iclass 33, count 0 2006.201.20:09:39.98#ibcon#wrote, iclass 33, count 0 2006.201.20:09:39.98#ibcon#about to read 3, iclass 33, count 0 2006.201.20:09:40.02#ibcon#read 3, iclass 33, count 0 2006.201.20:09:40.02#ibcon#about to read 4, iclass 33, count 0 2006.201.20:09:40.02#ibcon#read 4, iclass 33, count 0 2006.201.20:09:40.02#ibcon#about to read 5, iclass 33, count 0 2006.201.20:09:40.02#ibcon#read 5, iclass 33, count 0 2006.201.20:09:40.02#ibcon#about to read 6, iclass 33, count 0 2006.201.20:09:40.02#ibcon#read 6, iclass 33, count 0 2006.201.20:09:40.02#ibcon#end of sib2, iclass 33, count 0 2006.201.20:09:40.02#ibcon#*after write, iclass 33, count 0 2006.201.20:09:40.02#ibcon#*before return 0, iclass 33, count 0 2006.201.20:09:40.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:40.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:40.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.20:09:40.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.20:09:40.02$vck44/va=7,5 2006.201.20:09:40.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.20:09:40.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.20:09:40.02#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:40.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:40.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:40.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:40.08#ibcon#enter wrdev, iclass 35, count 2 2006.201.20:09:40.08#ibcon#first serial, iclass 35, count 2 2006.201.20:09:40.08#ibcon#enter sib2, iclass 35, count 2 2006.201.20:09:40.08#ibcon#flushed, iclass 35, count 2 2006.201.20:09:40.08#ibcon#about to write, iclass 35, count 2 2006.201.20:09:40.08#ibcon#wrote, iclass 35, count 2 2006.201.20:09:40.08#ibcon#about to read 3, iclass 35, count 2 2006.201.20:09:40.10#ibcon#read 3, iclass 35, count 2 2006.201.20:09:40.10#ibcon#about to read 4, iclass 35, count 2 2006.201.20:09:40.10#ibcon#read 4, iclass 35, count 2 2006.201.20:09:40.10#ibcon#about to read 5, iclass 35, count 2 2006.201.20:09:40.10#ibcon#read 5, iclass 35, count 2 2006.201.20:09:40.10#ibcon#about to read 6, iclass 35, count 2 2006.201.20:09:40.10#ibcon#read 6, iclass 35, count 2 2006.201.20:09:40.10#ibcon#end of sib2, iclass 35, count 2 2006.201.20:09:40.10#ibcon#*mode == 0, iclass 35, count 2 2006.201.20:09:40.10#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.20:09:40.10#ibcon#[25=AT07-05\r\n] 2006.201.20:09:40.10#ibcon#*before write, iclass 35, count 2 2006.201.20:09:40.10#ibcon#enter sib2, iclass 35, count 2 2006.201.20:09:40.10#ibcon#flushed, iclass 35, count 2 2006.201.20:09:40.10#ibcon#about to write, iclass 35, count 2 2006.201.20:09:40.10#ibcon#wrote, iclass 35, count 2 2006.201.20:09:40.10#ibcon#about to read 3, iclass 35, count 2 2006.201.20:09:40.13#ibcon#read 3, iclass 35, count 2 2006.201.20:09:40.13#ibcon#about to read 4, iclass 35, count 2 2006.201.20:09:40.13#ibcon#read 4, iclass 35, count 2 2006.201.20:09:40.13#ibcon#about to read 5, iclass 35, count 2 2006.201.20:09:40.13#ibcon#read 5, iclass 35, count 2 2006.201.20:09:40.13#ibcon#about to read 6, iclass 35, count 2 2006.201.20:09:40.13#ibcon#read 6, iclass 35, count 2 2006.201.20:09:40.13#ibcon#end of sib2, iclass 35, count 2 2006.201.20:09:40.13#ibcon#*after write, iclass 35, count 2 2006.201.20:09:40.13#ibcon#*before return 0, iclass 35, count 2 2006.201.20:09:40.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:40.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:40.13#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.20:09:40.13#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:40.13#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:40.25#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:40.25#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:40.25#ibcon#enter wrdev, iclass 35, count 0 2006.201.20:09:40.25#ibcon#first serial, iclass 35, count 0 2006.201.20:09:40.25#ibcon#enter sib2, iclass 35, count 0 2006.201.20:09:40.25#ibcon#flushed, iclass 35, count 0 2006.201.20:09:40.25#ibcon#about to write, iclass 35, count 0 2006.201.20:09:40.25#ibcon#wrote, iclass 35, count 0 2006.201.20:09:40.25#ibcon#about to read 3, iclass 35, count 0 2006.201.20:09:40.27#ibcon#read 3, iclass 35, count 0 2006.201.20:09:40.27#ibcon#about to read 4, iclass 35, count 0 2006.201.20:09:40.27#ibcon#read 4, iclass 35, count 0 2006.201.20:09:40.27#ibcon#about to read 5, iclass 35, count 0 2006.201.20:09:40.27#ibcon#read 5, iclass 35, count 0 2006.201.20:09:40.27#ibcon#about to read 6, iclass 35, count 0 2006.201.20:09:40.27#ibcon#read 6, iclass 35, count 0 2006.201.20:09:40.27#ibcon#end of sib2, iclass 35, count 0 2006.201.20:09:40.27#ibcon#*mode == 0, iclass 35, count 0 2006.201.20:09:40.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.20:09:40.27#ibcon#[25=USB\r\n] 2006.201.20:09:40.27#ibcon#*before write, iclass 35, count 0 2006.201.20:09:40.27#ibcon#enter sib2, iclass 35, count 0 2006.201.20:09:40.27#ibcon#flushed, iclass 35, count 0 2006.201.20:09:40.27#ibcon#about to write, iclass 35, count 0 2006.201.20:09:40.27#ibcon#wrote, iclass 35, count 0 2006.201.20:09:40.27#ibcon#about to read 3, iclass 35, count 0 2006.201.20:09:40.30#ibcon#read 3, iclass 35, count 0 2006.201.20:09:40.30#ibcon#about to read 4, iclass 35, count 0 2006.201.20:09:40.30#ibcon#read 4, iclass 35, count 0 2006.201.20:09:40.30#ibcon#about to read 5, iclass 35, count 0 2006.201.20:09:40.30#ibcon#read 5, iclass 35, count 0 2006.201.20:09:40.30#ibcon#about to read 6, iclass 35, count 0 2006.201.20:09:40.30#ibcon#read 6, iclass 35, count 0 2006.201.20:09:40.30#ibcon#end of sib2, iclass 35, count 0 2006.201.20:09:40.30#ibcon#*after write, iclass 35, count 0 2006.201.20:09:40.30#ibcon#*before return 0, iclass 35, count 0 2006.201.20:09:40.30#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:40.30#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:40.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.20:09:40.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.20:09:40.30$vck44/valo=8,884.99 2006.201.20:09:40.30#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.20:09:40.30#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.20:09:40.30#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:40.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:40.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:40.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:40.30#ibcon#enter wrdev, iclass 37, count 0 2006.201.20:09:40.30#ibcon#first serial, iclass 37, count 0 2006.201.20:09:40.30#ibcon#enter sib2, iclass 37, count 0 2006.201.20:09:40.30#ibcon#flushed, iclass 37, count 0 2006.201.20:09:40.30#ibcon#about to write, iclass 37, count 0 2006.201.20:09:40.30#ibcon#wrote, iclass 37, count 0 2006.201.20:09:40.30#ibcon#about to read 3, iclass 37, count 0 2006.201.20:09:40.32#ibcon#read 3, iclass 37, count 0 2006.201.20:09:40.32#ibcon#about to read 4, iclass 37, count 0 2006.201.20:09:40.32#ibcon#read 4, iclass 37, count 0 2006.201.20:09:40.32#ibcon#about to read 5, iclass 37, count 0 2006.201.20:09:40.32#ibcon#read 5, iclass 37, count 0 2006.201.20:09:40.32#ibcon#about to read 6, iclass 37, count 0 2006.201.20:09:40.32#ibcon#read 6, iclass 37, count 0 2006.201.20:09:40.32#ibcon#end of sib2, iclass 37, count 0 2006.201.20:09:40.32#ibcon#*mode == 0, iclass 37, count 0 2006.201.20:09:40.32#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.20:09:40.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:09:40.32#ibcon#*before write, iclass 37, count 0 2006.201.20:09:40.32#ibcon#enter sib2, iclass 37, count 0 2006.201.20:09:40.32#ibcon#flushed, iclass 37, count 0 2006.201.20:09:40.32#ibcon#about to write, iclass 37, count 0 2006.201.20:09:40.32#ibcon#wrote, iclass 37, count 0 2006.201.20:09:40.32#ibcon#about to read 3, iclass 37, count 0 2006.201.20:09:40.36#ibcon#read 3, iclass 37, count 0 2006.201.20:09:40.36#ibcon#about to read 4, iclass 37, count 0 2006.201.20:09:40.36#ibcon#read 4, iclass 37, count 0 2006.201.20:09:40.36#ibcon#about to read 5, iclass 37, count 0 2006.201.20:09:40.36#ibcon#read 5, iclass 37, count 0 2006.201.20:09:40.36#ibcon#about to read 6, iclass 37, count 0 2006.201.20:09:40.36#ibcon#read 6, iclass 37, count 0 2006.201.20:09:40.36#ibcon#end of sib2, iclass 37, count 0 2006.201.20:09:40.36#ibcon#*after write, iclass 37, count 0 2006.201.20:09:40.36#ibcon#*before return 0, iclass 37, count 0 2006.201.20:09:40.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:40.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:40.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.20:09:40.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.20:09:40.36$vck44/va=8,4 2006.201.20:09:40.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.20:09:40.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.20:09:40.36#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:40.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:09:40.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:09:40.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:09:40.42#ibcon#enter wrdev, iclass 39, count 2 2006.201.20:09:40.42#ibcon#first serial, iclass 39, count 2 2006.201.20:09:40.42#ibcon#enter sib2, iclass 39, count 2 2006.201.20:09:40.42#ibcon#flushed, iclass 39, count 2 2006.201.20:09:40.42#ibcon#about to write, iclass 39, count 2 2006.201.20:09:40.42#ibcon#wrote, iclass 39, count 2 2006.201.20:09:40.42#ibcon#about to read 3, iclass 39, count 2 2006.201.20:09:40.44#ibcon#read 3, iclass 39, count 2 2006.201.20:09:40.44#ibcon#about to read 4, iclass 39, count 2 2006.201.20:09:40.44#ibcon#read 4, iclass 39, count 2 2006.201.20:09:40.44#ibcon#about to read 5, iclass 39, count 2 2006.201.20:09:40.44#ibcon#read 5, iclass 39, count 2 2006.201.20:09:40.44#ibcon#about to read 6, iclass 39, count 2 2006.201.20:09:40.44#ibcon#read 6, iclass 39, count 2 2006.201.20:09:40.44#ibcon#end of sib2, iclass 39, count 2 2006.201.20:09:40.44#ibcon#*mode == 0, iclass 39, count 2 2006.201.20:09:40.44#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.20:09:40.44#ibcon#[25=AT08-04\r\n] 2006.201.20:09:40.44#ibcon#*before write, iclass 39, count 2 2006.201.20:09:40.44#ibcon#enter sib2, iclass 39, count 2 2006.201.20:09:40.44#ibcon#flushed, iclass 39, count 2 2006.201.20:09:40.44#ibcon#about to write, iclass 39, count 2 2006.201.20:09:40.44#ibcon#wrote, iclass 39, count 2 2006.201.20:09:40.44#ibcon#about to read 3, iclass 39, count 2 2006.201.20:09:40.47#ibcon#read 3, iclass 39, count 2 2006.201.20:09:40.47#ibcon#about to read 4, iclass 39, count 2 2006.201.20:09:40.47#ibcon#read 4, iclass 39, count 2 2006.201.20:09:40.47#ibcon#about to read 5, iclass 39, count 2 2006.201.20:09:40.47#ibcon#read 5, iclass 39, count 2 2006.201.20:09:40.47#ibcon#about to read 6, iclass 39, count 2 2006.201.20:09:40.47#ibcon#read 6, iclass 39, count 2 2006.201.20:09:40.47#ibcon#end of sib2, iclass 39, count 2 2006.201.20:09:40.47#ibcon#*after write, iclass 39, count 2 2006.201.20:09:40.47#ibcon#*before return 0, iclass 39, count 2 2006.201.20:09:40.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:09:40.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:09:40.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.20:09:40.47#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:40.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:09:40.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:09:40.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:09:40.59#ibcon#enter wrdev, iclass 39, count 0 2006.201.20:09:40.59#ibcon#first serial, iclass 39, count 0 2006.201.20:09:40.59#ibcon#enter sib2, iclass 39, count 0 2006.201.20:09:40.59#ibcon#flushed, iclass 39, count 0 2006.201.20:09:40.59#ibcon#about to write, iclass 39, count 0 2006.201.20:09:40.59#ibcon#wrote, iclass 39, count 0 2006.201.20:09:40.59#ibcon#about to read 3, iclass 39, count 0 2006.201.20:09:40.61#ibcon#read 3, iclass 39, count 0 2006.201.20:09:40.61#ibcon#about to read 4, iclass 39, count 0 2006.201.20:09:40.61#ibcon#read 4, iclass 39, count 0 2006.201.20:09:40.61#ibcon#about to read 5, iclass 39, count 0 2006.201.20:09:40.61#ibcon#read 5, iclass 39, count 0 2006.201.20:09:40.61#ibcon#about to read 6, iclass 39, count 0 2006.201.20:09:40.61#ibcon#read 6, iclass 39, count 0 2006.201.20:09:40.61#ibcon#end of sib2, iclass 39, count 0 2006.201.20:09:40.61#ibcon#*mode == 0, iclass 39, count 0 2006.201.20:09:40.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.20:09:40.61#ibcon#[25=USB\r\n] 2006.201.20:09:40.61#ibcon#*before write, iclass 39, count 0 2006.201.20:09:40.61#ibcon#enter sib2, iclass 39, count 0 2006.201.20:09:40.61#ibcon#flushed, iclass 39, count 0 2006.201.20:09:40.61#ibcon#about to write, iclass 39, count 0 2006.201.20:09:40.61#ibcon#wrote, iclass 39, count 0 2006.201.20:09:40.61#ibcon#about to read 3, iclass 39, count 0 2006.201.20:09:40.64#ibcon#read 3, iclass 39, count 0 2006.201.20:09:40.64#ibcon#about to read 4, iclass 39, count 0 2006.201.20:09:40.64#ibcon#read 4, iclass 39, count 0 2006.201.20:09:40.64#ibcon#about to read 5, iclass 39, count 0 2006.201.20:09:40.64#ibcon#read 5, iclass 39, count 0 2006.201.20:09:40.64#ibcon#about to read 6, iclass 39, count 0 2006.201.20:09:40.64#ibcon#read 6, iclass 39, count 0 2006.201.20:09:40.64#ibcon#end of sib2, iclass 39, count 0 2006.201.20:09:40.64#ibcon#*after write, iclass 39, count 0 2006.201.20:09:40.64#ibcon#*before return 0, iclass 39, count 0 2006.201.20:09:40.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:09:40.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:09:40.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.20:09:40.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.20:09:40.64$vck44/vblo=1,629.99 2006.201.20:09:40.64#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.20:09:40.64#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.20:09:40.64#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:40.64#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:40.64#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:40.64#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:40.64#ibcon#enter wrdev, iclass 2, count 0 2006.201.20:09:40.64#ibcon#first serial, iclass 2, count 0 2006.201.20:09:40.64#ibcon#enter sib2, iclass 2, count 0 2006.201.20:09:40.64#ibcon#flushed, iclass 2, count 0 2006.201.20:09:40.64#ibcon#about to write, iclass 2, count 0 2006.201.20:09:40.64#ibcon#wrote, iclass 2, count 0 2006.201.20:09:40.64#ibcon#about to read 3, iclass 2, count 0 2006.201.20:09:40.66#ibcon#read 3, iclass 2, count 0 2006.201.20:09:40.66#ibcon#about to read 4, iclass 2, count 0 2006.201.20:09:40.66#ibcon#read 4, iclass 2, count 0 2006.201.20:09:40.66#ibcon#about to read 5, iclass 2, count 0 2006.201.20:09:40.66#ibcon#read 5, iclass 2, count 0 2006.201.20:09:40.66#ibcon#about to read 6, iclass 2, count 0 2006.201.20:09:40.66#ibcon#read 6, iclass 2, count 0 2006.201.20:09:40.66#ibcon#end of sib2, iclass 2, count 0 2006.201.20:09:40.66#ibcon#*mode == 0, iclass 2, count 0 2006.201.20:09:40.66#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.20:09:40.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:09:40.66#ibcon#*before write, iclass 2, count 0 2006.201.20:09:40.66#ibcon#enter sib2, iclass 2, count 0 2006.201.20:09:40.66#ibcon#flushed, iclass 2, count 0 2006.201.20:09:40.66#ibcon#about to write, iclass 2, count 0 2006.201.20:09:40.66#ibcon#wrote, iclass 2, count 0 2006.201.20:09:40.66#ibcon#about to read 3, iclass 2, count 0 2006.201.20:09:40.71#ibcon#read 3, iclass 2, count 0 2006.201.20:09:40.71#ibcon#about to read 4, iclass 2, count 0 2006.201.20:09:40.71#ibcon#read 4, iclass 2, count 0 2006.201.20:09:40.71#ibcon#about to read 5, iclass 2, count 0 2006.201.20:09:40.71#ibcon#read 5, iclass 2, count 0 2006.201.20:09:40.71#ibcon#about to read 6, iclass 2, count 0 2006.201.20:09:40.71#ibcon#read 6, iclass 2, count 0 2006.201.20:09:40.71#ibcon#end of sib2, iclass 2, count 0 2006.201.20:09:40.71#ibcon#*after write, iclass 2, count 0 2006.201.20:09:40.71#ibcon#*before return 0, iclass 2, count 0 2006.201.20:09:40.71#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:40.71#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:09:40.71#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.20:09:40.71#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.20:09:40.71$vck44/vb=1,4 2006.201.20:09:40.71#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.20:09:40.71#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.20:09:40.71#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:40.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:40.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:40.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:40.71#ibcon#enter wrdev, iclass 5, count 2 2006.201.20:09:40.71#ibcon#first serial, iclass 5, count 2 2006.201.20:09:40.71#ibcon#enter sib2, iclass 5, count 2 2006.201.20:09:40.71#ibcon#flushed, iclass 5, count 2 2006.201.20:09:40.71#ibcon#about to write, iclass 5, count 2 2006.201.20:09:40.71#ibcon#wrote, iclass 5, count 2 2006.201.20:09:40.71#ibcon#about to read 3, iclass 5, count 2 2006.201.20:09:40.73#ibcon#read 3, iclass 5, count 2 2006.201.20:09:40.73#ibcon#about to read 4, iclass 5, count 2 2006.201.20:09:40.73#ibcon#read 4, iclass 5, count 2 2006.201.20:09:40.73#ibcon#about to read 5, iclass 5, count 2 2006.201.20:09:40.73#ibcon#read 5, iclass 5, count 2 2006.201.20:09:40.73#ibcon#about to read 6, iclass 5, count 2 2006.201.20:09:40.73#ibcon#read 6, iclass 5, count 2 2006.201.20:09:40.73#ibcon#end of sib2, iclass 5, count 2 2006.201.20:09:40.73#ibcon#*mode == 0, iclass 5, count 2 2006.201.20:09:40.73#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.20:09:40.73#ibcon#[27=AT01-04\r\n] 2006.201.20:09:40.73#ibcon#*before write, iclass 5, count 2 2006.201.20:09:40.73#ibcon#enter sib2, iclass 5, count 2 2006.201.20:09:40.73#ibcon#flushed, iclass 5, count 2 2006.201.20:09:40.73#ibcon#about to write, iclass 5, count 2 2006.201.20:09:40.73#ibcon#wrote, iclass 5, count 2 2006.201.20:09:40.73#ibcon#about to read 3, iclass 5, count 2 2006.201.20:09:40.76#ibcon#read 3, iclass 5, count 2 2006.201.20:09:40.76#ibcon#about to read 4, iclass 5, count 2 2006.201.20:09:40.76#ibcon#read 4, iclass 5, count 2 2006.201.20:09:40.76#ibcon#about to read 5, iclass 5, count 2 2006.201.20:09:40.76#ibcon#read 5, iclass 5, count 2 2006.201.20:09:40.76#ibcon#about to read 6, iclass 5, count 2 2006.201.20:09:40.76#ibcon#read 6, iclass 5, count 2 2006.201.20:09:40.76#ibcon#end of sib2, iclass 5, count 2 2006.201.20:09:40.76#ibcon#*after write, iclass 5, count 2 2006.201.20:09:40.76#ibcon#*before return 0, iclass 5, count 2 2006.201.20:09:40.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:40.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:09:40.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.20:09:40.76#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:40.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:40.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:40.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:40.88#ibcon#enter wrdev, iclass 5, count 0 2006.201.20:09:40.88#ibcon#first serial, iclass 5, count 0 2006.201.20:09:40.88#ibcon#enter sib2, iclass 5, count 0 2006.201.20:09:40.88#ibcon#flushed, iclass 5, count 0 2006.201.20:09:40.88#ibcon#about to write, iclass 5, count 0 2006.201.20:09:40.88#ibcon#wrote, iclass 5, count 0 2006.201.20:09:40.88#ibcon#about to read 3, iclass 5, count 0 2006.201.20:09:40.90#ibcon#read 3, iclass 5, count 0 2006.201.20:09:40.90#ibcon#about to read 4, iclass 5, count 0 2006.201.20:09:40.90#ibcon#read 4, iclass 5, count 0 2006.201.20:09:40.90#ibcon#about to read 5, iclass 5, count 0 2006.201.20:09:40.90#ibcon#read 5, iclass 5, count 0 2006.201.20:09:40.90#ibcon#about to read 6, iclass 5, count 0 2006.201.20:09:40.90#ibcon#read 6, iclass 5, count 0 2006.201.20:09:40.90#ibcon#end of sib2, iclass 5, count 0 2006.201.20:09:40.90#ibcon#*mode == 0, iclass 5, count 0 2006.201.20:09:40.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.20:09:40.90#ibcon#[27=USB\r\n] 2006.201.20:09:40.90#ibcon#*before write, iclass 5, count 0 2006.201.20:09:40.90#ibcon#enter sib2, iclass 5, count 0 2006.201.20:09:40.90#ibcon#flushed, iclass 5, count 0 2006.201.20:09:40.90#ibcon#about to write, iclass 5, count 0 2006.201.20:09:40.90#ibcon#wrote, iclass 5, count 0 2006.201.20:09:40.90#ibcon#about to read 3, iclass 5, count 0 2006.201.20:09:40.93#ibcon#read 3, iclass 5, count 0 2006.201.20:09:40.93#ibcon#about to read 4, iclass 5, count 0 2006.201.20:09:40.93#ibcon#read 4, iclass 5, count 0 2006.201.20:09:40.93#ibcon#about to read 5, iclass 5, count 0 2006.201.20:09:40.93#ibcon#read 5, iclass 5, count 0 2006.201.20:09:40.93#ibcon#about to read 6, iclass 5, count 0 2006.201.20:09:40.93#ibcon#read 6, iclass 5, count 0 2006.201.20:09:40.93#ibcon#end of sib2, iclass 5, count 0 2006.201.20:09:40.93#ibcon#*after write, iclass 5, count 0 2006.201.20:09:40.93#ibcon#*before return 0, iclass 5, count 0 2006.201.20:09:40.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:40.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:09:40.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.20:09:40.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.20:09:40.93$vck44/vblo=2,634.99 2006.201.20:09:40.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.20:09:40.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.20:09:40.93#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:40.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:40.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:40.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:40.93#ibcon#enter wrdev, iclass 7, count 0 2006.201.20:09:40.93#ibcon#first serial, iclass 7, count 0 2006.201.20:09:40.93#ibcon#enter sib2, iclass 7, count 0 2006.201.20:09:40.93#ibcon#flushed, iclass 7, count 0 2006.201.20:09:40.93#ibcon#about to write, iclass 7, count 0 2006.201.20:09:40.93#ibcon#wrote, iclass 7, count 0 2006.201.20:09:40.93#ibcon#about to read 3, iclass 7, count 0 2006.201.20:09:40.95#ibcon#read 3, iclass 7, count 0 2006.201.20:09:40.95#ibcon#about to read 4, iclass 7, count 0 2006.201.20:09:40.95#ibcon#read 4, iclass 7, count 0 2006.201.20:09:40.95#ibcon#about to read 5, iclass 7, count 0 2006.201.20:09:40.95#ibcon#read 5, iclass 7, count 0 2006.201.20:09:40.95#ibcon#about to read 6, iclass 7, count 0 2006.201.20:09:40.95#ibcon#read 6, iclass 7, count 0 2006.201.20:09:40.95#ibcon#end of sib2, iclass 7, count 0 2006.201.20:09:40.95#ibcon#*mode == 0, iclass 7, count 0 2006.201.20:09:40.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.20:09:40.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:09:40.95#ibcon#*before write, iclass 7, count 0 2006.201.20:09:40.95#ibcon#enter sib2, iclass 7, count 0 2006.201.20:09:40.95#ibcon#flushed, iclass 7, count 0 2006.201.20:09:40.95#ibcon#about to write, iclass 7, count 0 2006.201.20:09:40.95#ibcon#wrote, iclass 7, count 0 2006.201.20:09:40.95#ibcon#about to read 3, iclass 7, count 0 2006.201.20:09:40.99#ibcon#read 3, iclass 7, count 0 2006.201.20:09:40.99#ibcon#about to read 4, iclass 7, count 0 2006.201.20:09:40.99#ibcon#read 4, iclass 7, count 0 2006.201.20:09:40.99#ibcon#about to read 5, iclass 7, count 0 2006.201.20:09:40.99#ibcon#read 5, iclass 7, count 0 2006.201.20:09:40.99#ibcon#about to read 6, iclass 7, count 0 2006.201.20:09:40.99#ibcon#read 6, iclass 7, count 0 2006.201.20:09:40.99#ibcon#end of sib2, iclass 7, count 0 2006.201.20:09:40.99#ibcon#*after write, iclass 7, count 0 2006.201.20:09:40.99#ibcon#*before return 0, iclass 7, count 0 2006.201.20:09:40.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:40.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:09:40.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.20:09:40.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.20:09:40.99$vck44/vb=2,5 2006.201.20:09:40.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.20:09:40.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.20:09:40.99#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:40.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:41.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:41.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:41.05#ibcon#enter wrdev, iclass 11, count 2 2006.201.20:09:41.05#ibcon#first serial, iclass 11, count 2 2006.201.20:09:41.05#ibcon#enter sib2, iclass 11, count 2 2006.201.20:09:41.05#ibcon#flushed, iclass 11, count 2 2006.201.20:09:41.05#ibcon#about to write, iclass 11, count 2 2006.201.20:09:41.05#ibcon#wrote, iclass 11, count 2 2006.201.20:09:41.05#ibcon#about to read 3, iclass 11, count 2 2006.201.20:09:41.07#ibcon#read 3, iclass 11, count 2 2006.201.20:09:41.07#ibcon#about to read 4, iclass 11, count 2 2006.201.20:09:41.07#ibcon#read 4, iclass 11, count 2 2006.201.20:09:41.07#ibcon#about to read 5, iclass 11, count 2 2006.201.20:09:41.07#ibcon#read 5, iclass 11, count 2 2006.201.20:09:41.07#ibcon#about to read 6, iclass 11, count 2 2006.201.20:09:41.07#ibcon#read 6, iclass 11, count 2 2006.201.20:09:41.07#ibcon#end of sib2, iclass 11, count 2 2006.201.20:09:41.07#ibcon#*mode == 0, iclass 11, count 2 2006.201.20:09:41.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.20:09:41.07#ibcon#[27=AT02-05\r\n] 2006.201.20:09:41.07#ibcon#*before write, iclass 11, count 2 2006.201.20:09:41.07#ibcon#enter sib2, iclass 11, count 2 2006.201.20:09:41.07#ibcon#flushed, iclass 11, count 2 2006.201.20:09:41.07#ibcon#about to write, iclass 11, count 2 2006.201.20:09:41.07#ibcon#wrote, iclass 11, count 2 2006.201.20:09:41.07#ibcon#about to read 3, iclass 11, count 2 2006.201.20:09:41.10#ibcon#read 3, iclass 11, count 2 2006.201.20:09:41.10#ibcon#about to read 4, iclass 11, count 2 2006.201.20:09:41.10#ibcon#read 4, iclass 11, count 2 2006.201.20:09:41.10#ibcon#about to read 5, iclass 11, count 2 2006.201.20:09:41.10#ibcon#read 5, iclass 11, count 2 2006.201.20:09:41.10#ibcon#about to read 6, iclass 11, count 2 2006.201.20:09:41.10#ibcon#read 6, iclass 11, count 2 2006.201.20:09:41.10#ibcon#end of sib2, iclass 11, count 2 2006.201.20:09:41.10#ibcon#*after write, iclass 11, count 2 2006.201.20:09:41.10#ibcon#*before return 0, iclass 11, count 2 2006.201.20:09:41.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:41.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:09:41.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.20:09:41.10#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:41.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:41.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:41.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:41.22#ibcon#enter wrdev, iclass 11, count 0 2006.201.20:09:41.22#ibcon#first serial, iclass 11, count 0 2006.201.20:09:41.22#ibcon#enter sib2, iclass 11, count 0 2006.201.20:09:41.22#ibcon#flushed, iclass 11, count 0 2006.201.20:09:41.22#ibcon#about to write, iclass 11, count 0 2006.201.20:09:41.22#ibcon#wrote, iclass 11, count 0 2006.201.20:09:41.22#ibcon#about to read 3, iclass 11, count 0 2006.201.20:09:41.24#ibcon#read 3, iclass 11, count 0 2006.201.20:09:41.24#ibcon#about to read 4, iclass 11, count 0 2006.201.20:09:41.24#ibcon#read 4, iclass 11, count 0 2006.201.20:09:41.24#ibcon#about to read 5, iclass 11, count 0 2006.201.20:09:41.24#ibcon#read 5, iclass 11, count 0 2006.201.20:09:41.24#ibcon#about to read 6, iclass 11, count 0 2006.201.20:09:41.24#ibcon#read 6, iclass 11, count 0 2006.201.20:09:41.24#ibcon#end of sib2, iclass 11, count 0 2006.201.20:09:41.24#ibcon#*mode == 0, iclass 11, count 0 2006.201.20:09:41.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.20:09:41.24#ibcon#[27=USB\r\n] 2006.201.20:09:41.24#ibcon#*before write, iclass 11, count 0 2006.201.20:09:41.24#ibcon#enter sib2, iclass 11, count 0 2006.201.20:09:41.24#ibcon#flushed, iclass 11, count 0 2006.201.20:09:41.24#ibcon#about to write, iclass 11, count 0 2006.201.20:09:41.24#ibcon#wrote, iclass 11, count 0 2006.201.20:09:41.24#ibcon#about to read 3, iclass 11, count 0 2006.201.20:09:41.27#ibcon#read 3, iclass 11, count 0 2006.201.20:09:41.27#ibcon#about to read 4, iclass 11, count 0 2006.201.20:09:41.27#ibcon#read 4, iclass 11, count 0 2006.201.20:09:41.27#ibcon#about to read 5, iclass 11, count 0 2006.201.20:09:41.27#ibcon#read 5, iclass 11, count 0 2006.201.20:09:41.27#ibcon#about to read 6, iclass 11, count 0 2006.201.20:09:41.27#ibcon#read 6, iclass 11, count 0 2006.201.20:09:41.27#ibcon#end of sib2, iclass 11, count 0 2006.201.20:09:41.27#ibcon#*after write, iclass 11, count 0 2006.201.20:09:41.27#ibcon#*before return 0, iclass 11, count 0 2006.201.20:09:41.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:41.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:09:41.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.20:09:41.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.20:09:41.27$vck44/vblo=3,649.99 2006.201.20:09:41.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.20:09:41.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.20:09:41.27#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:41.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:09:41.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:09:41.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:09:41.27#ibcon#enter wrdev, iclass 13, count 0 2006.201.20:09:41.27#ibcon#first serial, iclass 13, count 0 2006.201.20:09:41.27#ibcon#enter sib2, iclass 13, count 0 2006.201.20:09:41.27#ibcon#flushed, iclass 13, count 0 2006.201.20:09:41.27#ibcon#about to write, iclass 13, count 0 2006.201.20:09:41.27#ibcon#wrote, iclass 13, count 0 2006.201.20:09:41.27#ibcon#about to read 3, iclass 13, count 0 2006.201.20:09:41.29#ibcon#read 3, iclass 13, count 0 2006.201.20:09:41.29#ibcon#about to read 4, iclass 13, count 0 2006.201.20:09:41.29#ibcon#read 4, iclass 13, count 0 2006.201.20:09:41.29#ibcon#about to read 5, iclass 13, count 0 2006.201.20:09:41.29#ibcon#read 5, iclass 13, count 0 2006.201.20:09:41.29#ibcon#about to read 6, iclass 13, count 0 2006.201.20:09:41.29#ibcon#read 6, iclass 13, count 0 2006.201.20:09:41.29#ibcon#end of sib2, iclass 13, count 0 2006.201.20:09:41.29#ibcon#*mode == 0, iclass 13, count 0 2006.201.20:09:41.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.20:09:41.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:09:41.29#ibcon#*before write, iclass 13, count 0 2006.201.20:09:41.29#ibcon#enter sib2, iclass 13, count 0 2006.201.20:09:41.29#ibcon#flushed, iclass 13, count 0 2006.201.20:09:41.29#ibcon#about to write, iclass 13, count 0 2006.201.20:09:41.29#ibcon#wrote, iclass 13, count 0 2006.201.20:09:41.29#ibcon#about to read 3, iclass 13, count 0 2006.201.20:09:41.33#ibcon#read 3, iclass 13, count 0 2006.201.20:09:41.33#ibcon#about to read 4, iclass 13, count 0 2006.201.20:09:41.33#ibcon#read 4, iclass 13, count 0 2006.201.20:09:41.33#ibcon#about to read 5, iclass 13, count 0 2006.201.20:09:41.33#ibcon#read 5, iclass 13, count 0 2006.201.20:09:41.33#ibcon#about to read 6, iclass 13, count 0 2006.201.20:09:41.33#ibcon#read 6, iclass 13, count 0 2006.201.20:09:41.33#ibcon#end of sib2, iclass 13, count 0 2006.201.20:09:41.33#ibcon#*after write, iclass 13, count 0 2006.201.20:09:41.33#ibcon#*before return 0, iclass 13, count 0 2006.201.20:09:41.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:09:41.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:09:41.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.20:09:41.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.20:09:41.33$vck44/vb=3,4 2006.201.20:09:41.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.20:09:41.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.20:09:41.33#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:41.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:09:41.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:09:41.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:09:41.39#ibcon#enter wrdev, iclass 15, count 2 2006.201.20:09:41.39#ibcon#first serial, iclass 15, count 2 2006.201.20:09:41.39#ibcon#enter sib2, iclass 15, count 2 2006.201.20:09:41.39#ibcon#flushed, iclass 15, count 2 2006.201.20:09:41.39#ibcon#about to write, iclass 15, count 2 2006.201.20:09:41.39#ibcon#wrote, iclass 15, count 2 2006.201.20:09:41.39#ibcon#about to read 3, iclass 15, count 2 2006.201.20:09:41.41#ibcon#read 3, iclass 15, count 2 2006.201.20:09:41.41#ibcon#about to read 4, iclass 15, count 2 2006.201.20:09:41.41#ibcon#read 4, iclass 15, count 2 2006.201.20:09:41.41#ibcon#about to read 5, iclass 15, count 2 2006.201.20:09:41.41#ibcon#read 5, iclass 15, count 2 2006.201.20:09:41.41#ibcon#about to read 6, iclass 15, count 2 2006.201.20:09:41.41#ibcon#read 6, iclass 15, count 2 2006.201.20:09:41.41#ibcon#end of sib2, iclass 15, count 2 2006.201.20:09:41.41#ibcon#*mode == 0, iclass 15, count 2 2006.201.20:09:41.41#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.20:09:41.41#ibcon#[27=AT03-04\r\n] 2006.201.20:09:41.41#ibcon#*before write, iclass 15, count 2 2006.201.20:09:41.41#ibcon#enter sib2, iclass 15, count 2 2006.201.20:09:41.41#ibcon#flushed, iclass 15, count 2 2006.201.20:09:41.41#ibcon#about to write, iclass 15, count 2 2006.201.20:09:41.41#ibcon#wrote, iclass 15, count 2 2006.201.20:09:41.41#ibcon#about to read 3, iclass 15, count 2 2006.201.20:09:41.44#ibcon#read 3, iclass 15, count 2 2006.201.20:09:41.44#ibcon#about to read 4, iclass 15, count 2 2006.201.20:09:41.44#ibcon#read 4, iclass 15, count 2 2006.201.20:09:41.44#ibcon#about to read 5, iclass 15, count 2 2006.201.20:09:41.44#ibcon#read 5, iclass 15, count 2 2006.201.20:09:41.44#ibcon#about to read 6, iclass 15, count 2 2006.201.20:09:41.44#ibcon#read 6, iclass 15, count 2 2006.201.20:09:41.44#ibcon#end of sib2, iclass 15, count 2 2006.201.20:09:41.44#ibcon#*after write, iclass 15, count 2 2006.201.20:09:41.44#ibcon#*before return 0, iclass 15, count 2 2006.201.20:09:41.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:09:41.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:09:41.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.20:09:41.44#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:41.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:09:41.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:09:41.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:09:41.56#ibcon#enter wrdev, iclass 15, count 0 2006.201.20:09:41.56#ibcon#first serial, iclass 15, count 0 2006.201.20:09:41.56#ibcon#enter sib2, iclass 15, count 0 2006.201.20:09:41.56#ibcon#flushed, iclass 15, count 0 2006.201.20:09:41.56#ibcon#about to write, iclass 15, count 0 2006.201.20:09:41.56#ibcon#wrote, iclass 15, count 0 2006.201.20:09:41.56#ibcon#about to read 3, iclass 15, count 0 2006.201.20:09:41.58#ibcon#read 3, iclass 15, count 0 2006.201.20:09:41.58#ibcon#about to read 4, iclass 15, count 0 2006.201.20:09:41.58#ibcon#read 4, iclass 15, count 0 2006.201.20:09:41.58#ibcon#about to read 5, iclass 15, count 0 2006.201.20:09:41.58#ibcon#read 5, iclass 15, count 0 2006.201.20:09:41.58#ibcon#about to read 6, iclass 15, count 0 2006.201.20:09:41.58#ibcon#read 6, iclass 15, count 0 2006.201.20:09:41.58#ibcon#end of sib2, iclass 15, count 0 2006.201.20:09:41.58#ibcon#*mode == 0, iclass 15, count 0 2006.201.20:09:41.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.20:09:41.58#ibcon#[27=USB\r\n] 2006.201.20:09:41.58#ibcon#*before write, iclass 15, count 0 2006.201.20:09:41.58#ibcon#enter sib2, iclass 15, count 0 2006.201.20:09:41.58#ibcon#flushed, iclass 15, count 0 2006.201.20:09:41.58#ibcon#about to write, iclass 15, count 0 2006.201.20:09:41.58#ibcon#wrote, iclass 15, count 0 2006.201.20:09:41.58#ibcon#about to read 3, iclass 15, count 0 2006.201.20:09:41.61#ibcon#read 3, iclass 15, count 0 2006.201.20:09:41.61#ibcon#about to read 4, iclass 15, count 0 2006.201.20:09:41.61#ibcon#read 4, iclass 15, count 0 2006.201.20:09:41.61#ibcon#about to read 5, iclass 15, count 0 2006.201.20:09:41.61#ibcon#read 5, iclass 15, count 0 2006.201.20:09:41.61#ibcon#about to read 6, iclass 15, count 0 2006.201.20:09:41.61#ibcon#read 6, iclass 15, count 0 2006.201.20:09:41.61#ibcon#end of sib2, iclass 15, count 0 2006.201.20:09:41.61#ibcon#*after write, iclass 15, count 0 2006.201.20:09:41.61#ibcon#*before return 0, iclass 15, count 0 2006.201.20:09:41.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:09:41.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:09:41.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.20:09:41.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.20:09:41.61$vck44/vblo=4,679.99 2006.201.20:09:41.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.20:09:41.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.20:09:41.61#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:41.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:41.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:41.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:41.61#ibcon#enter wrdev, iclass 17, count 0 2006.201.20:09:41.61#ibcon#first serial, iclass 17, count 0 2006.201.20:09:41.61#ibcon#enter sib2, iclass 17, count 0 2006.201.20:09:41.61#ibcon#flushed, iclass 17, count 0 2006.201.20:09:41.61#ibcon#about to write, iclass 17, count 0 2006.201.20:09:41.61#ibcon#wrote, iclass 17, count 0 2006.201.20:09:41.61#ibcon#about to read 3, iclass 17, count 0 2006.201.20:09:41.63#ibcon#read 3, iclass 17, count 0 2006.201.20:09:41.63#ibcon#about to read 4, iclass 17, count 0 2006.201.20:09:41.63#ibcon#read 4, iclass 17, count 0 2006.201.20:09:41.63#ibcon#about to read 5, iclass 17, count 0 2006.201.20:09:41.63#ibcon#read 5, iclass 17, count 0 2006.201.20:09:41.63#ibcon#about to read 6, iclass 17, count 0 2006.201.20:09:41.63#ibcon#read 6, iclass 17, count 0 2006.201.20:09:41.63#ibcon#end of sib2, iclass 17, count 0 2006.201.20:09:41.63#ibcon#*mode == 0, iclass 17, count 0 2006.201.20:09:41.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.20:09:41.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:09:41.63#ibcon#*before write, iclass 17, count 0 2006.201.20:09:41.63#ibcon#enter sib2, iclass 17, count 0 2006.201.20:09:41.63#ibcon#flushed, iclass 17, count 0 2006.201.20:09:41.63#ibcon#about to write, iclass 17, count 0 2006.201.20:09:41.63#ibcon#wrote, iclass 17, count 0 2006.201.20:09:41.63#ibcon#about to read 3, iclass 17, count 0 2006.201.20:09:41.68#ibcon#read 3, iclass 17, count 0 2006.201.20:09:41.68#ibcon#about to read 4, iclass 17, count 0 2006.201.20:09:41.68#ibcon#read 4, iclass 17, count 0 2006.201.20:09:41.68#ibcon#about to read 5, iclass 17, count 0 2006.201.20:09:41.68#ibcon#read 5, iclass 17, count 0 2006.201.20:09:41.68#ibcon#about to read 6, iclass 17, count 0 2006.201.20:09:41.68#ibcon#read 6, iclass 17, count 0 2006.201.20:09:41.68#ibcon#end of sib2, iclass 17, count 0 2006.201.20:09:41.68#ibcon#*after write, iclass 17, count 0 2006.201.20:09:41.68#ibcon#*before return 0, iclass 17, count 0 2006.201.20:09:41.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:41.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:09:41.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.20:09:41.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.20:09:41.68$vck44/vb=4,5 2006.201.20:09:41.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.20:09:41.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.20:09:41.68#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:41.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:41.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:41.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:41.73#ibcon#enter wrdev, iclass 19, count 2 2006.201.20:09:41.73#ibcon#first serial, iclass 19, count 2 2006.201.20:09:41.73#ibcon#enter sib2, iclass 19, count 2 2006.201.20:09:41.73#ibcon#flushed, iclass 19, count 2 2006.201.20:09:41.73#ibcon#about to write, iclass 19, count 2 2006.201.20:09:41.73#ibcon#wrote, iclass 19, count 2 2006.201.20:09:41.73#ibcon#about to read 3, iclass 19, count 2 2006.201.20:09:41.75#ibcon#read 3, iclass 19, count 2 2006.201.20:09:41.75#ibcon#about to read 4, iclass 19, count 2 2006.201.20:09:41.75#ibcon#read 4, iclass 19, count 2 2006.201.20:09:41.75#ibcon#about to read 5, iclass 19, count 2 2006.201.20:09:41.75#ibcon#read 5, iclass 19, count 2 2006.201.20:09:41.75#ibcon#about to read 6, iclass 19, count 2 2006.201.20:09:41.75#ibcon#read 6, iclass 19, count 2 2006.201.20:09:41.75#ibcon#end of sib2, iclass 19, count 2 2006.201.20:09:41.75#ibcon#*mode == 0, iclass 19, count 2 2006.201.20:09:41.75#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.20:09:41.75#ibcon#[27=AT04-05\r\n] 2006.201.20:09:41.75#ibcon#*before write, iclass 19, count 2 2006.201.20:09:41.75#ibcon#enter sib2, iclass 19, count 2 2006.201.20:09:41.75#ibcon#flushed, iclass 19, count 2 2006.201.20:09:41.75#ibcon#about to write, iclass 19, count 2 2006.201.20:09:41.75#ibcon#wrote, iclass 19, count 2 2006.201.20:09:41.75#ibcon#about to read 3, iclass 19, count 2 2006.201.20:09:41.78#ibcon#read 3, iclass 19, count 2 2006.201.20:09:41.78#ibcon#about to read 4, iclass 19, count 2 2006.201.20:09:41.78#ibcon#read 4, iclass 19, count 2 2006.201.20:09:41.78#ibcon#about to read 5, iclass 19, count 2 2006.201.20:09:41.78#ibcon#read 5, iclass 19, count 2 2006.201.20:09:41.78#ibcon#about to read 6, iclass 19, count 2 2006.201.20:09:41.78#ibcon#read 6, iclass 19, count 2 2006.201.20:09:41.78#ibcon#end of sib2, iclass 19, count 2 2006.201.20:09:41.78#ibcon#*after write, iclass 19, count 2 2006.201.20:09:41.78#ibcon#*before return 0, iclass 19, count 2 2006.201.20:09:41.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:41.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:09:41.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.20:09:41.78#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:41.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:41.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:41.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:41.90#ibcon#enter wrdev, iclass 19, count 0 2006.201.20:09:41.90#ibcon#first serial, iclass 19, count 0 2006.201.20:09:41.90#ibcon#enter sib2, iclass 19, count 0 2006.201.20:09:41.90#ibcon#flushed, iclass 19, count 0 2006.201.20:09:41.90#ibcon#about to write, iclass 19, count 0 2006.201.20:09:41.90#ibcon#wrote, iclass 19, count 0 2006.201.20:09:41.90#ibcon#about to read 3, iclass 19, count 0 2006.201.20:09:41.92#ibcon#read 3, iclass 19, count 0 2006.201.20:09:41.92#ibcon#about to read 4, iclass 19, count 0 2006.201.20:09:41.92#ibcon#read 4, iclass 19, count 0 2006.201.20:09:41.92#ibcon#about to read 5, iclass 19, count 0 2006.201.20:09:41.92#ibcon#read 5, iclass 19, count 0 2006.201.20:09:41.92#ibcon#about to read 6, iclass 19, count 0 2006.201.20:09:41.92#ibcon#read 6, iclass 19, count 0 2006.201.20:09:41.92#ibcon#end of sib2, iclass 19, count 0 2006.201.20:09:41.92#ibcon#*mode == 0, iclass 19, count 0 2006.201.20:09:41.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.20:09:41.92#ibcon#[27=USB\r\n] 2006.201.20:09:41.92#ibcon#*before write, iclass 19, count 0 2006.201.20:09:41.92#ibcon#enter sib2, iclass 19, count 0 2006.201.20:09:41.92#ibcon#flushed, iclass 19, count 0 2006.201.20:09:41.92#ibcon#about to write, iclass 19, count 0 2006.201.20:09:41.92#ibcon#wrote, iclass 19, count 0 2006.201.20:09:41.92#ibcon#about to read 3, iclass 19, count 0 2006.201.20:09:41.95#ibcon#read 3, iclass 19, count 0 2006.201.20:09:41.95#ibcon#about to read 4, iclass 19, count 0 2006.201.20:09:41.95#ibcon#read 4, iclass 19, count 0 2006.201.20:09:41.95#ibcon#about to read 5, iclass 19, count 0 2006.201.20:09:41.95#ibcon#read 5, iclass 19, count 0 2006.201.20:09:41.95#ibcon#about to read 6, iclass 19, count 0 2006.201.20:09:41.95#ibcon#read 6, iclass 19, count 0 2006.201.20:09:41.95#ibcon#end of sib2, iclass 19, count 0 2006.201.20:09:41.95#ibcon#*after write, iclass 19, count 0 2006.201.20:09:41.95#ibcon#*before return 0, iclass 19, count 0 2006.201.20:09:41.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:41.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:09:41.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.20:09:41.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.20:09:41.95$vck44/vblo=5,709.99 2006.201.20:09:41.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.20:09:41.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.20:09:41.95#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:41.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:41.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:41.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:41.95#ibcon#enter wrdev, iclass 21, count 0 2006.201.20:09:41.95#ibcon#first serial, iclass 21, count 0 2006.201.20:09:41.95#ibcon#enter sib2, iclass 21, count 0 2006.201.20:09:41.95#ibcon#flushed, iclass 21, count 0 2006.201.20:09:41.95#ibcon#about to write, iclass 21, count 0 2006.201.20:09:41.95#ibcon#wrote, iclass 21, count 0 2006.201.20:09:41.95#ibcon#about to read 3, iclass 21, count 0 2006.201.20:09:41.97#ibcon#read 3, iclass 21, count 0 2006.201.20:09:41.97#ibcon#about to read 4, iclass 21, count 0 2006.201.20:09:41.97#ibcon#read 4, iclass 21, count 0 2006.201.20:09:41.97#ibcon#about to read 5, iclass 21, count 0 2006.201.20:09:41.97#ibcon#read 5, iclass 21, count 0 2006.201.20:09:41.97#ibcon#about to read 6, iclass 21, count 0 2006.201.20:09:41.97#ibcon#read 6, iclass 21, count 0 2006.201.20:09:41.97#ibcon#end of sib2, iclass 21, count 0 2006.201.20:09:41.97#ibcon#*mode == 0, iclass 21, count 0 2006.201.20:09:41.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.20:09:41.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:09:41.97#ibcon#*before write, iclass 21, count 0 2006.201.20:09:41.97#ibcon#enter sib2, iclass 21, count 0 2006.201.20:09:41.97#ibcon#flushed, iclass 21, count 0 2006.201.20:09:41.97#ibcon#about to write, iclass 21, count 0 2006.201.20:09:41.97#ibcon#wrote, iclass 21, count 0 2006.201.20:09:41.97#ibcon#about to read 3, iclass 21, count 0 2006.201.20:09:42.01#ibcon#read 3, iclass 21, count 0 2006.201.20:09:42.01#ibcon#about to read 4, iclass 21, count 0 2006.201.20:09:42.01#ibcon#read 4, iclass 21, count 0 2006.201.20:09:42.01#ibcon#about to read 5, iclass 21, count 0 2006.201.20:09:42.01#ibcon#read 5, iclass 21, count 0 2006.201.20:09:42.01#ibcon#about to read 6, iclass 21, count 0 2006.201.20:09:42.01#ibcon#read 6, iclass 21, count 0 2006.201.20:09:42.01#ibcon#end of sib2, iclass 21, count 0 2006.201.20:09:42.01#ibcon#*after write, iclass 21, count 0 2006.201.20:09:42.01#ibcon#*before return 0, iclass 21, count 0 2006.201.20:09:42.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:42.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:09:42.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.20:09:42.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.20:09:42.01$vck44/vb=5,4 2006.201.20:09:42.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.20:09:42.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.20:09:42.01#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:42.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:42.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:42.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:42.07#ibcon#enter wrdev, iclass 23, count 2 2006.201.20:09:42.07#ibcon#first serial, iclass 23, count 2 2006.201.20:09:42.07#ibcon#enter sib2, iclass 23, count 2 2006.201.20:09:42.07#ibcon#flushed, iclass 23, count 2 2006.201.20:09:42.07#ibcon#about to write, iclass 23, count 2 2006.201.20:09:42.07#ibcon#wrote, iclass 23, count 2 2006.201.20:09:42.07#ibcon#about to read 3, iclass 23, count 2 2006.201.20:09:42.09#ibcon#read 3, iclass 23, count 2 2006.201.20:09:42.09#ibcon#about to read 4, iclass 23, count 2 2006.201.20:09:42.09#ibcon#read 4, iclass 23, count 2 2006.201.20:09:42.09#ibcon#about to read 5, iclass 23, count 2 2006.201.20:09:42.09#ibcon#read 5, iclass 23, count 2 2006.201.20:09:42.09#ibcon#about to read 6, iclass 23, count 2 2006.201.20:09:42.09#ibcon#read 6, iclass 23, count 2 2006.201.20:09:42.09#ibcon#end of sib2, iclass 23, count 2 2006.201.20:09:42.09#ibcon#*mode == 0, iclass 23, count 2 2006.201.20:09:42.09#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.20:09:42.09#ibcon#[27=AT05-04\r\n] 2006.201.20:09:42.09#ibcon#*before write, iclass 23, count 2 2006.201.20:09:42.09#ibcon#enter sib2, iclass 23, count 2 2006.201.20:09:42.09#ibcon#flushed, iclass 23, count 2 2006.201.20:09:42.09#ibcon#about to write, iclass 23, count 2 2006.201.20:09:42.09#ibcon#wrote, iclass 23, count 2 2006.201.20:09:42.09#ibcon#about to read 3, iclass 23, count 2 2006.201.20:09:42.12#ibcon#read 3, iclass 23, count 2 2006.201.20:09:42.12#ibcon#about to read 4, iclass 23, count 2 2006.201.20:09:42.12#ibcon#read 4, iclass 23, count 2 2006.201.20:09:42.12#ibcon#about to read 5, iclass 23, count 2 2006.201.20:09:42.12#ibcon#read 5, iclass 23, count 2 2006.201.20:09:42.12#ibcon#about to read 6, iclass 23, count 2 2006.201.20:09:42.12#ibcon#read 6, iclass 23, count 2 2006.201.20:09:42.12#ibcon#end of sib2, iclass 23, count 2 2006.201.20:09:42.12#ibcon#*after write, iclass 23, count 2 2006.201.20:09:42.12#ibcon#*before return 0, iclass 23, count 2 2006.201.20:09:42.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:42.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:09:42.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.20:09:42.12#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:42.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:42.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:42.24#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:42.24#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:09:42.24#ibcon#first serial, iclass 23, count 0 2006.201.20:09:42.24#ibcon#enter sib2, iclass 23, count 0 2006.201.20:09:42.24#ibcon#flushed, iclass 23, count 0 2006.201.20:09:42.24#ibcon#about to write, iclass 23, count 0 2006.201.20:09:42.24#ibcon#wrote, iclass 23, count 0 2006.201.20:09:42.24#ibcon#about to read 3, iclass 23, count 0 2006.201.20:09:42.26#ibcon#read 3, iclass 23, count 0 2006.201.20:09:42.26#ibcon#about to read 4, iclass 23, count 0 2006.201.20:09:42.26#ibcon#read 4, iclass 23, count 0 2006.201.20:09:42.26#ibcon#about to read 5, iclass 23, count 0 2006.201.20:09:42.26#ibcon#read 5, iclass 23, count 0 2006.201.20:09:42.26#ibcon#about to read 6, iclass 23, count 0 2006.201.20:09:42.26#ibcon#read 6, iclass 23, count 0 2006.201.20:09:42.26#ibcon#end of sib2, iclass 23, count 0 2006.201.20:09:42.26#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:09:42.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:09:42.26#ibcon#[27=USB\r\n] 2006.201.20:09:42.26#ibcon#*before write, iclass 23, count 0 2006.201.20:09:42.26#ibcon#enter sib2, iclass 23, count 0 2006.201.20:09:42.26#ibcon#flushed, iclass 23, count 0 2006.201.20:09:42.26#ibcon#about to write, iclass 23, count 0 2006.201.20:09:42.26#ibcon#wrote, iclass 23, count 0 2006.201.20:09:42.26#ibcon#about to read 3, iclass 23, count 0 2006.201.20:09:42.29#ibcon#read 3, iclass 23, count 0 2006.201.20:09:42.29#ibcon#about to read 4, iclass 23, count 0 2006.201.20:09:42.29#ibcon#read 4, iclass 23, count 0 2006.201.20:09:42.29#ibcon#about to read 5, iclass 23, count 0 2006.201.20:09:42.29#ibcon#read 5, iclass 23, count 0 2006.201.20:09:42.29#ibcon#about to read 6, iclass 23, count 0 2006.201.20:09:42.29#ibcon#read 6, iclass 23, count 0 2006.201.20:09:42.29#ibcon#end of sib2, iclass 23, count 0 2006.201.20:09:42.29#ibcon#*after write, iclass 23, count 0 2006.201.20:09:42.29#ibcon#*before return 0, iclass 23, count 0 2006.201.20:09:42.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:42.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:09:42.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:09:42.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:09:42.29$vck44/vblo=6,719.99 2006.201.20:09:42.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.20:09:42.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.20:09:42.29#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:42.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:42.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:42.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:42.29#ibcon#enter wrdev, iclass 25, count 0 2006.201.20:09:42.29#ibcon#first serial, iclass 25, count 0 2006.201.20:09:42.29#ibcon#enter sib2, iclass 25, count 0 2006.201.20:09:42.29#ibcon#flushed, iclass 25, count 0 2006.201.20:09:42.29#ibcon#about to write, iclass 25, count 0 2006.201.20:09:42.29#ibcon#wrote, iclass 25, count 0 2006.201.20:09:42.29#ibcon#about to read 3, iclass 25, count 0 2006.201.20:09:42.31#ibcon#read 3, iclass 25, count 0 2006.201.20:09:42.31#ibcon#about to read 4, iclass 25, count 0 2006.201.20:09:42.31#ibcon#read 4, iclass 25, count 0 2006.201.20:09:42.31#ibcon#about to read 5, iclass 25, count 0 2006.201.20:09:42.31#ibcon#read 5, iclass 25, count 0 2006.201.20:09:42.31#ibcon#about to read 6, iclass 25, count 0 2006.201.20:09:42.31#ibcon#read 6, iclass 25, count 0 2006.201.20:09:42.31#ibcon#end of sib2, iclass 25, count 0 2006.201.20:09:42.31#ibcon#*mode == 0, iclass 25, count 0 2006.201.20:09:42.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.20:09:42.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:09:42.31#ibcon#*before write, iclass 25, count 0 2006.201.20:09:42.31#ibcon#enter sib2, iclass 25, count 0 2006.201.20:09:42.31#ibcon#flushed, iclass 25, count 0 2006.201.20:09:42.31#ibcon#about to write, iclass 25, count 0 2006.201.20:09:42.31#ibcon#wrote, iclass 25, count 0 2006.201.20:09:42.31#ibcon#about to read 3, iclass 25, count 0 2006.201.20:09:42.36#ibcon#read 3, iclass 25, count 0 2006.201.20:09:42.36#ibcon#about to read 4, iclass 25, count 0 2006.201.20:09:42.36#ibcon#read 4, iclass 25, count 0 2006.201.20:09:42.36#ibcon#about to read 5, iclass 25, count 0 2006.201.20:09:42.36#ibcon#read 5, iclass 25, count 0 2006.201.20:09:42.36#ibcon#about to read 6, iclass 25, count 0 2006.201.20:09:42.36#ibcon#read 6, iclass 25, count 0 2006.201.20:09:42.36#ibcon#end of sib2, iclass 25, count 0 2006.201.20:09:42.36#ibcon#*after write, iclass 25, count 0 2006.201.20:09:42.36#ibcon#*before return 0, iclass 25, count 0 2006.201.20:09:42.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:42.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:09:42.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.20:09:42.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.20:09:42.36$vck44/vb=6,4 2006.201.20:09:42.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.20:09:42.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.20:09:42.36#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:42.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:42.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:42.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:42.41#ibcon#enter wrdev, iclass 27, count 2 2006.201.20:09:42.41#ibcon#first serial, iclass 27, count 2 2006.201.20:09:42.41#ibcon#enter sib2, iclass 27, count 2 2006.201.20:09:42.41#ibcon#flushed, iclass 27, count 2 2006.201.20:09:42.41#ibcon#about to write, iclass 27, count 2 2006.201.20:09:42.41#ibcon#wrote, iclass 27, count 2 2006.201.20:09:42.41#ibcon#about to read 3, iclass 27, count 2 2006.201.20:09:42.43#ibcon#read 3, iclass 27, count 2 2006.201.20:09:42.43#ibcon#about to read 4, iclass 27, count 2 2006.201.20:09:42.43#ibcon#read 4, iclass 27, count 2 2006.201.20:09:42.43#ibcon#about to read 5, iclass 27, count 2 2006.201.20:09:42.43#ibcon#read 5, iclass 27, count 2 2006.201.20:09:42.43#ibcon#about to read 6, iclass 27, count 2 2006.201.20:09:42.43#ibcon#read 6, iclass 27, count 2 2006.201.20:09:42.43#ibcon#end of sib2, iclass 27, count 2 2006.201.20:09:42.43#ibcon#*mode == 0, iclass 27, count 2 2006.201.20:09:42.43#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.20:09:42.43#ibcon#[27=AT06-04\r\n] 2006.201.20:09:42.43#ibcon#*before write, iclass 27, count 2 2006.201.20:09:42.43#ibcon#enter sib2, iclass 27, count 2 2006.201.20:09:42.43#ibcon#flushed, iclass 27, count 2 2006.201.20:09:42.43#ibcon#about to write, iclass 27, count 2 2006.201.20:09:42.43#ibcon#wrote, iclass 27, count 2 2006.201.20:09:42.43#ibcon#about to read 3, iclass 27, count 2 2006.201.20:09:42.46#ibcon#read 3, iclass 27, count 2 2006.201.20:09:42.46#ibcon#about to read 4, iclass 27, count 2 2006.201.20:09:42.46#ibcon#read 4, iclass 27, count 2 2006.201.20:09:42.46#ibcon#about to read 5, iclass 27, count 2 2006.201.20:09:42.46#ibcon#read 5, iclass 27, count 2 2006.201.20:09:42.46#ibcon#about to read 6, iclass 27, count 2 2006.201.20:09:42.46#ibcon#read 6, iclass 27, count 2 2006.201.20:09:42.46#ibcon#end of sib2, iclass 27, count 2 2006.201.20:09:42.46#ibcon#*after write, iclass 27, count 2 2006.201.20:09:42.46#ibcon#*before return 0, iclass 27, count 2 2006.201.20:09:42.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:42.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:09:42.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.20:09:42.46#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:42.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:42.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:42.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:42.58#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:09:42.58#ibcon#first serial, iclass 27, count 0 2006.201.20:09:42.58#ibcon#enter sib2, iclass 27, count 0 2006.201.20:09:42.58#ibcon#flushed, iclass 27, count 0 2006.201.20:09:42.58#ibcon#about to write, iclass 27, count 0 2006.201.20:09:42.58#ibcon#wrote, iclass 27, count 0 2006.201.20:09:42.58#ibcon#about to read 3, iclass 27, count 0 2006.201.20:09:42.60#ibcon#read 3, iclass 27, count 0 2006.201.20:09:42.60#ibcon#about to read 4, iclass 27, count 0 2006.201.20:09:42.60#ibcon#read 4, iclass 27, count 0 2006.201.20:09:42.60#ibcon#about to read 5, iclass 27, count 0 2006.201.20:09:42.60#ibcon#read 5, iclass 27, count 0 2006.201.20:09:42.60#ibcon#about to read 6, iclass 27, count 0 2006.201.20:09:42.60#ibcon#read 6, iclass 27, count 0 2006.201.20:09:42.60#ibcon#end of sib2, iclass 27, count 0 2006.201.20:09:42.60#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:09:42.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:09:42.60#ibcon#[27=USB\r\n] 2006.201.20:09:42.60#ibcon#*before write, iclass 27, count 0 2006.201.20:09:42.60#ibcon#enter sib2, iclass 27, count 0 2006.201.20:09:42.60#ibcon#flushed, iclass 27, count 0 2006.201.20:09:42.60#ibcon#about to write, iclass 27, count 0 2006.201.20:09:42.60#ibcon#wrote, iclass 27, count 0 2006.201.20:09:42.60#ibcon#about to read 3, iclass 27, count 0 2006.201.20:09:42.63#ibcon#read 3, iclass 27, count 0 2006.201.20:09:42.63#ibcon#about to read 4, iclass 27, count 0 2006.201.20:09:42.63#ibcon#read 4, iclass 27, count 0 2006.201.20:09:42.63#ibcon#about to read 5, iclass 27, count 0 2006.201.20:09:42.63#ibcon#read 5, iclass 27, count 0 2006.201.20:09:42.63#ibcon#about to read 6, iclass 27, count 0 2006.201.20:09:42.63#ibcon#read 6, iclass 27, count 0 2006.201.20:09:42.63#ibcon#end of sib2, iclass 27, count 0 2006.201.20:09:42.63#ibcon#*after write, iclass 27, count 0 2006.201.20:09:42.63#ibcon#*before return 0, iclass 27, count 0 2006.201.20:09:42.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:42.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:09:42.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:09:42.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:09:42.63$vck44/vblo=7,734.99 2006.201.20:09:42.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.20:09:42.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.20:09:42.63#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:42.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:42.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:42.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:42.63#ibcon#enter wrdev, iclass 29, count 0 2006.201.20:09:42.63#ibcon#first serial, iclass 29, count 0 2006.201.20:09:42.63#ibcon#enter sib2, iclass 29, count 0 2006.201.20:09:42.63#ibcon#flushed, iclass 29, count 0 2006.201.20:09:42.63#ibcon#about to write, iclass 29, count 0 2006.201.20:09:42.63#ibcon#wrote, iclass 29, count 0 2006.201.20:09:42.63#ibcon#about to read 3, iclass 29, count 0 2006.201.20:09:42.65#ibcon#read 3, iclass 29, count 0 2006.201.20:09:42.65#ibcon#about to read 4, iclass 29, count 0 2006.201.20:09:42.65#ibcon#read 4, iclass 29, count 0 2006.201.20:09:42.65#ibcon#about to read 5, iclass 29, count 0 2006.201.20:09:42.65#ibcon#read 5, iclass 29, count 0 2006.201.20:09:42.65#ibcon#about to read 6, iclass 29, count 0 2006.201.20:09:42.65#ibcon#read 6, iclass 29, count 0 2006.201.20:09:42.65#ibcon#end of sib2, iclass 29, count 0 2006.201.20:09:42.65#ibcon#*mode == 0, iclass 29, count 0 2006.201.20:09:42.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.20:09:42.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:09:42.65#ibcon#*before write, iclass 29, count 0 2006.201.20:09:42.65#ibcon#enter sib2, iclass 29, count 0 2006.201.20:09:42.65#ibcon#flushed, iclass 29, count 0 2006.201.20:09:42.65#ibcon#about to write, iclass 29, count 0 2006.201.20:09:42.65#ibcon#wrote, iclass 29, count 0 2006.201.20:09:42.65#ibcon#about to read 3, iclass 29, count 0 2006.201.20:09:42.69#ibcon#read 3, iclass 29, count 0 2006.201.20:09:42.69#ibcon#about to read 4, iclass 29, count 0 2006.201.20:09:42.69#ibcon#read 4, iclass 29, count 0 2006.201.20:09:42.69#ibcon#about to read 5, iclass 29, count 0 2006.201.20:09:42.69#ibcon#read 5, iclass 29, count 0 2006.201.20:09:42.69#ibcon#about to read 6, iclass 29, count 0 2006.201.20:09:42.69#ibcon#read 6, iclass 29, count 0 2006.201.20:09:42.69#ibcon#end of sib2, iclass 29, count 0 2006.201.20:09:42.69#ibcon#*after write, iclass 29, count 0 2006.201.20:09:42.69#ibcon#*before return 0, iclass 29, count 0 2006.201.20:09:42.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:42.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:09:42.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.20:09:42.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.20:09:42.69$vck44/vb=7,4 2006.201.20:09:42.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.20:09:42.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.20:09:42.69#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:42.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:42.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:42.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:42.75#ibcon#enter wrdev, iclass 31, count 2 2006.201.20:09:42.75#ibcon#first serial, iclass 31, count 2 2006.201.20:09:42.75#ibcon#enter sib2, iclass 31, count 2 2006.201.20:09:42.75#ibcon#flushed, iclass 31, count 2 2006.201.20:09:42.75#ibcon#about to write, iclass 31, count 2 2006.201.20:09:42.75#ibcon#wrote, iclass 31, count 2 2006.201.20:09:42.75#ibcon#about to read 3, iclass 31, count 2 2006.201.20:09:42.77#ibcon#read 3, iclass 31, count 2 2006.201.20:09:42.77#ibcon#about to read 4, iclass 31, count 2 2006.201.20:09:42.77#ibcon#read 4, iclass 31, count 2 2006.201.20:09:42.77#ibcon#about to read 5, iclass 31, count 2 2006.201.20:09:42.77#ibcon#read 5, iclass 31, count 2 2006.201.20:09:42.77#ibcon#about to read 6, iclass 31, count 2 2006.201.20:09:42.77#ibcon#read 6, iclass 31, count 2 2006.201.20:09:42.77#ibcon#end of sib2, iclass 31, count 2 2006.201.20:09:42.77#ibcon#*mode == 0, iclass 31, count 2 2006.201.20:09:42.77#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.20:09:42.77#ibcon#[27=AT07-04\r\n] 2006.201.20:09:42.77#ibcon#*before write, iclass 31, count 2 2006.201.20:09:42.77#ibcon#enter sib2, iclass 31, count 2 2006.201.20:09:42.77#ibcon#flushed, iclass 31, count 2 2006.201.20:09:42.77#ibcon#about to write, iclass 31, count 2 2006.201.20:09:42.77#ibcon#wrote, iclass 31, count 2 2006.201.20:09:42.77#ibcon#about to read 3, iclass 31, count 2 2006.201.20:09:42.80#ibcon#read 3, iclass 31, count 2 2006.201.20:09:42.80#ibcon#about to read 4, iclass 31, count 2 2006.201.20:09:42.80#ibcon#read 4, iclass 31, count 2 2006.201.20:09:42.80#ibcon#about to read 5, iclass 31, count 2 2006.201.20:09:42.80#ibcon#read 5, iclass 31, count 2 2006.201.20:09:42.80#ibcon#about to read 6, iclass 31, count 2 2006.201.20:09:42.80#ibcon#read 6, iclass 31, count 2 2006.201.20:09:42.80#ibcon#end of sib2, iclass 31, count 2 2006.201.20:09:42.80#ibcon#*after write, iclass 31, count 2 2006.201.20:09:42.80#ibcon#*before return 0, iclass 31, count 2 2006.201.20:09:42.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:42.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:09:42.80#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.20:09:42.80#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:42.80#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:42.92#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:42.92#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:42.92#ibcon#enter wrdev, iclass 31, count 0 2006.201.20:09:42.92#ibcon#first serial, iclass 31, count 0 2006.201.20:09:42.92#ibcon#enter sib2, iclass 31, count 0 2006.201.20:09:42.92#ibcon#flushed, iclass 31, count 0 2006.201.20:09:42.92#ibcon#about to write, iclass 31, count 0 2006.201.20:09:42.92#ibcon#wrote, iclass 31, count 0 2006.201.20:09:42.92#ibcon#about to read 3, iclass 31, count 0 2006.201.20:09:42.94#ibcon#read 3, iclass 31, count 0 2006.201.20:09:42.94#ibcon#about to read 4, iclass 31, count 0 2006.201.20:09:42.94#ibcon#read 4, iclass 31, count 0 2006.201.20:09:42.94#ibcon#about to read 5, iclass 31, count 0 2006.201.20:09:42.94#ibcon#read 5, iclass 31, count 0 2006.201.20:09:42.94#ibcon#about to read 6, iclass 31, count 0 2006.201.20:09:42.94#ibcon#read 6, iclass 31, count 0 2006.201.20:09:42.94#ibcon#end of sib2, iclass 31, count 0 2006.201.20:09:42.94#ibcon#*mode == 0, iclass 31, count 0 2006.201.20:09:42.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.20:09:42.94#ibcon#[27=USB\r\n] 2006.201.20:09:42.94#ibcon#*before write, iclass 31, count 0 2006.201.20:09:42.94#ibcon#enter sib2, iclass 31, count 0 2006.201.20:09:42.94#ibcon#flushed, iclass 31, count 0 2006.201.20:09:42.94#ibcon#about to write, iclass 31, count 0 2006.201.20:09:42.94#ibcon#wrote, iclass 31, count 0 2006.201.20:09:42.94#ibcon#about to read 3, iclass 31, count 0 2006.201.20:09:42.97#ibcon#read 3, iclass 31, count 0 2006.201.20:09:42.97#ibcon#about to read 4, iclass 31, count 0 2006.201.20:09:42.97#ibcon#read 4, iclass 31, count 0 2006.201.20:09:42.97#ibcon#about to read 5, iclass 31, count 0 2006.201.20:09:42.97#ibcon#read 5, iclass 31, count 0 2006.201.20:09:42.97#ibcon#about to read 6, iclass 31, count 0 2006.201.20:09:42.97#ibcon#read 6, iclass 31, count 0 2006.201.20:09:42.97#ibcon#end of sib2, iclass 31, count 0 2006.201.20:09:42.97#ibcon#*after write, iclass 31, count 0 2006.201.20:09:42.97#ibcon#*before return 0, iclass 31, count 0 2006.201.20:09:42.97#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:42.97#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:09:42.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.20:09:42.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.20:09:42.97$vck44/vblo=8,744.99 2006.201.20:09:42.97#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.20:09:42.97#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.20:09:42.97#ibcon#ireg 17 cls_cnt 0 2006.201.20:09:42.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:42.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:42.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:42.97#ibcon#enter wrdev, iclass 33, count 0 2006.201.20:09:42.97#ibcon#first serial, iclass 33, count 0 2006.201.20:09:42.97#ibcon#enter sib2, iclass 33, count 0 2006.201.20:09:42.97#ibcon#flushed, iclass 33, count 0 2006.201.20:09:42.97#ibcon#about to write, iclass 33, count 0 2006.201.20:09:42.97#ibcon#wrote, iclass 33, count 0 2006.201.20:09:42.97#ibcon#about to read 3, iclass 33, count 0 2006.201.20:09:42.99#ibcon#read 3, iclass 33, count 0 2006.201.20:09:42.99#ibcon#about to read 4, iclass 33, count 0 2006.201.20:09:42.99#ibcon#read 4, iclass 33, count 0 2006.201.20:09:42.99#ibcon#about to read 5, iclass 33, count 0 2006.201.20:09:42.99#ibcon#read 5, iclass 33, count 0 2006.201.20:09:42.99#ibcon#about to read 6, iclass 33, count 0 2006.201.20:09:42.99#ibcon#read 6, iclass 33, count 0 2006.201.20:09:42.99#ibcon#end of sib2, iclass 33, count 0 2006.201.20:09:42.99#ibcon#*mode == 0, iclass 33, count 0 2006.201.20:09:42.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.20:09:42.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:09:42.99#ibcon#*before write, iclass 33, count 0 2006.201.20:09:42.99#ibcon#enter sib2, iclass 33, count 0 2006.201.20:09:42.99#ibcon#flushed, iclass 33, count 0 2006.201.20:09:42.99#ibcon#about to write, iclass 33, count 0 2006.201.20:09:42.99#ibcon#wrote, iclass 33, count 0 2006.201.20:09:42.99#ibcon#about to read 3, iclass 33, count 0 2006.201.20:09:43.04#ibcon#read 3, iclass 33, count 0 2006.201.20:09:43.04#ibcon#about to read 4, iclass 33, count 0 2006.201.20:09:43.04#ibcon#read 4, iclass 33, count 0 2006.201.20:09:43.04#ibcon#about to read 5, iclass 33, count 0 2006.201.20:09:43.04#ibcon#read 5, iclass 33, count 0 2006.201.20:09:43.04#ibcon#about to read 6, iclass 33, count 0 2006.201.20:09:43.04#ibcon#read 6, iclass 33, count 0 2006.201.20:09:43.04#ibcon#end of sib2, iclass 33, count 0 2006.201.20:09:43.04#ibcon#*after write, iclass 33, count 0 2006.201.20:09:43.04#ibcon#*before return 0, iclass 33, count 0 2006.201.20:09:43.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:43.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:09:43.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.20:09:43.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.20:09:43.04$vck44/vb=8,4 2006.201.20:09:43.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.20:09:43.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.20:09:43.04#ibcon#ireg 11 cls_cnt 2 2006.201.20:09:43.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:43.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:43.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:43.09#ibcon#enter wrdev, iclass 35, count 2 2006.201.20:09:43.09#ibcon#first serial, iclass 35, count 2 2006.201.20:09:43.09#ibcon#enter sib2, iclass 35, count 2 2006.201.20:09:43.09#ibcon#flushed, iclass 35, count 2 2006.201.20:09:43.09#ibcon#about to write, iclass 35, count 2 2006.201.20:09:43.09#ibcon#wrote, iclass 35, count 2 2006.201.20:09:43.09#ibcon#about to read 3, iclass 35, count 2 2006.201.20:09:43.11#ibcon#read 3, iclass 35, count 2 2006.201.20:09:43.11#ibcon#about to read 4, iclass 35, count 2 2006.201.20:09:43.11#ibcon#read 4, iclass 35, count 2 2006.201.20:09:43.11#ibcon#about to read 5, iclass 35, count 2 2006.201.20:09:43.11#ibcon#read 5, iclass 35, count 2 2006.201.20:09:43.11#ibcon#about to read 6, iclass 35, count 2 2006.201.20:09:43.11#ibcon#read 6, iclass 35, count 2 2006.201.20:09:43.11#ibcon#end of sib2, iclass 35, count 2 2006.201.20:09:43.11#ibcon#*mode == 0, iclass 35, count 2 2006.201.20:09:43.11#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.20:09:43.11#ibcon#[27=AT08-04\r\n] 2006.201.20:09:43.11#ibcon#*before write, iclass 35, count 2 2006.201.20:09:43.11#ibcon#enter sib2, iclass 35, count 2 2006.201.20:09:43.11#ibcon#flushed, iclass 35, count 2 2006.201.20:09:43.11#ibcon#about to write, iclass 35, count 2 2006.201.20:09:43.11#ibcon#wrote, iclass 35, count 2 2006.201.20:09:43.11#ibcon#about to read 3, iclass 35, count 2 2006.201.20:09:43.14#ibcon#read 3, iclass 35, count 2 2006.201.20:09:43.14#ibcon#about to read 4, iclass 35, count 2 2006.201.20:09:43.14#ibcon#read 4, iclass 35, count 2 2006.201.20:09:43.14#ibcon#about to read 5, iclass 35, count 2 2006.201.20:09:43.14#ibcon#read 5, iclass 35, count 2 2006.201.20:09:43.14#ibcon#about to read 6, iclass 35, count 2 2006.201.20:09:43.14#ibcon#read 6, iclass 35, count 2 2006.201.20:09:43.14#ibcon#end of sib2, iclass 35, count 2 2006.201.20:09:43.14#ibcon#*after write, iclass 35, count 2 2006.201.20:09:43.14#ibcon#*before return 0, iclass 35, count 2 2006.201.20:09:43.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:43.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:09:43.14#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.20:09:43.14#ibcon#ireg 7 cls_cnt 0 2006.201.20:09:43.14#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:43.26#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:43.26#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:43.26#ibcon#enter wrdev, iclass 35, count 0 2006.201.20:09:43.26#ibcon#first serial, iclass 35, count 0 2006.201.20:09:43.26#ibcon#enter sib2, iclass 35, count 0 2006.201.20:09:43.26#ibcon#flushed, iclass 35, count 0 2006.201.20:09:43.26#ibcon#about to write, iclass 35, count 0 2006.201.20:09:43.26#ibcon#wrote, iclass 35, count 0 2006.201.20:09:43.26#ibcon#about to read 3, iclass 35, count 0 2006.201.20:09:43.28#ibcon#read 3, iclass 35, count 0 2006.201.20:09:43.28#ibcon#about to read 4, iclass 35, count 0 2006.201.20:09:43.28#ibcon#read 4, iclass 35, count 0 2006.201.20:09:43.28#ibcon#about to read 5, iclass 35, count 0 2006.201.20:09:43.28#ibcon#read 5, iclass 35, count 0 2006.201.20:09:43.28#ibcon#about to read 6, iclass 35, count 0 2006.201.20:09:43.28#ibcon#read 6, iclass 35, count 0 2006.201.20:09:43.28#ibcon#end of sib2, iclass 35, count 0 2006.201.20:09:43.28#ibcon#*mode == 0, iclass 35, count 0 2006.201.20:09:43.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.20:09:43.28#ibcon#[27=USB\r\n] 2006.201.20:09:43.28#ibcon#*before write, iclass 35, count 0 2006.201.20:09:43.28#ibcon#enter sib2, iclass 35, count 0 2006.201.20:09:43.28#ibcon#flushed, iclass 35, count 0 2006.201.20:09:43.28#ibcon#about to write, iclass 35, count 0 2006.201.20:09:43.28#ibcon#wrote, iclass 35, count 0 2006.201.20:09:43.28#ibcon#about to read 3, iclass 35, count 0 2006.201.20:09:43.31#ibcon#read 3, iclass 35, count 0 2006.201.20:09:43.31#ibcon#about to read 4, iclass 35, count 0 2006.201.20:09:43.31#ibcon#read 4, iclass 35, count 0 2006.201.20:09:43.31#ibcon#about to read 5, iclass 35, count 0 2006.201.20:09:43.31#ibcon#read 5, iclass 35, count 0 2006.201.20:09:43.31#ibcon#about to read 6, iclass 35, count 0 2006.201.20:09:43.31#ibcon#read 6, iclass 35, count 0 2006.201.20:09:43.31#ibcon#end of sib2, iclass 35, count 0 2006.201.20:09:43.31#ibcon#*after write, iclass 35, count 0 2006.201.20:09:43.31#ibcon#*before return 0, iclass 35, count 0 2006.201.20:09:43.31#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:43.31#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:09:43.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.20:09:43.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.20:09:43.31$vck44/vabw=wide 2006.201.20:09:43.31#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.20:09:43.31#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.20:09:43.31#ibcon#ireg 8 cls_cnt 0 2006.201.20:09:43.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:43.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:43.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:43.31#ibcon#enter wrdev, iclass 37, count 0 2006.201.20:09:43.31#ibcon#first serial, iclass 37, count 0 2006.201.20:09:43.31#ibcon#enter sib2, iclass 37, count 0 2006.201.20:09:43.31#ibcon#flushed, iclass 37, count 0 2006.201.20:09:43.31#ibcon#about to write, iclass 37, count 0 2006.201.20:09:43.31#ibcon#wrote, iclass 37, count 0 2006.201.20:09:43.31#ibcon#about to read 3, iclass 37, count 0 2006.201.20:09:43.33#ibcon#read 3, iclass 37, count 0 2006.201.20:09:43.33#ibcon#about to read 4, iclass 37, count 0 2006.201.20:09:43.33#ibcon#read 4, iclass 37, count 0 2006.201.20:09:43.33#ibcon#about to read 5, iclass 37, count 0 2006.201.20:09:43.33#ibcon#read 5, iclass 37, count 0 2006.201.20:09:43.33#ibcon#about to read 6, iclass 37, count 0 2006.201.20:09:43.33#ibcon#read 6, iclass 37, count 0 2006.201.20:09:43.33#ibcon#end of sib2, iclass 37, count 0 2006.201.20:09:43.33#ibcon#*mode == 0, iclass 37, count 0 2006.201.20:09:43.33#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.20:09:43.33#ibcon#[25=BW32\r\n] 2006.201.20:09:43.33#ibcon#*before write, iclass 37, count 0 2006.201.20:09:43.33#ibcon#enter sib2, iclass 37, count 0 2006.201.20:09:43.33#ibcon#flushed, iclass 37, count 0 2006.201.20:09:43.33#ibcon#about to write, iclass 37, count 0 2006.201.20:09:43.33#ibcon#wrote, iclass 37, count 0 2006.201.20:09:43.33#ibcon#about to read 3, iclass 37, count 0 2006.201.20:09:43.37#ibcon#read 3, iclass 37, count 0 2006.201.20:09:43.37#ibcon#about to read 4, iclass 37, count 0 2006.201.20:09:43.37#ibcon#read 4, iclass 37, count 0 2006.201.20:09:43.37#ibcon#about to read 5, iclass 37, count 0 2006.201.20:09:43.37#ibcon#read 5, iclass 37, count 0 2006.201.20:09:43.37#ibcon#about to read 6, iclass 37, count 0 2006.201.20:09:43.37#ibcon#read 6, iclass 37, count 0 2006.201.20:09:43.37#ibcon#end of sib2, iclass 37, count 0 2006.201.20:09:43.37#ibcon#*after write, iclass 37, count 0 2006.201.20:09:43.37#ibcon#*before return 0, iclass 37, count 0 2006.201.20:09:43.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:43.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:09:43.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.20:09:43.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.20:09:43.37$vck44/vbbw=wide 2006.201.20:09:43.37#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.20:09:43.37#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.20:09:43.37#ibcon#ireg 8 cls_cnt 0 2006.201.20:09:43.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:09:43.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:09:43.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:09:43.43#ibcon#enter wrdev, iclass 39, count 0 2006.201.20:09:43.43#ibcon#first serial, iclass 39, count 0 2006.201.20:09:43.43#ibcon#enter sib2, iclass 39, count 0 2006.201.20:09:43.43#ibcon#flushed, iclass 39, count 0 2006.201.20:09:43.43#ibcon#about to write, iclass 39, count 0 2006.201.20:09:43.43#ibcon#wrote, iclass 39, count 0 2006.201.20:09:43.43#ibcon#about to read 3, iclass 39, count 0 2006.201.20:09:43.45#ibcon#read 3, iclass 39, count 0 2006.201.20:09:43.45#ibcon#about to read 4, iclass 39, count 0 2006.201.20:09:43.45#ibcon#read 4, iclass 39, count 0 2006.201.20:09:43.45#ibcon#about to read 5, iclass 39, count 0 2006.201.20:09:43.45#ibcon#read 5, iclass 39, count 0 2006.201.20:09:43.45#ibcon#about to read 6, iclass 39, count 0 2006.201.20:09:43.45#ibcon#read 6, iclass 39, count 0 2006.201.20:09:43.45#ibcon#end of sib2, iclass 39, count 0 2006.201.20:09:43.45#ibcon#*mode == 0, iclass 39, count 0 2006.201.20:09:43.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.20:09:43.45#ibcon#[27=BW32\r\n] 2006.201.20:09:43.45#ibcon#*before write, iclass 39, count 0 2006.201.20:09:43.45#ibcon#enter sib2, iclass 39, count 0 2006.201.20:09:43.45#ibcon#flushed, iclass 39, count 0 2006.201.20:09:43.45#ibcon#about to write, iclass 39, count 0 2006.201.20:09:43.45#ibcon#wrote, iclass 39, count 0 2006.201.20:09:43.45#ibcon#about to read 3, iclass 39, count 0 2006.201.20:09:43.48#ibcon#read 3, iclass 39, count 0 2006.201.20:09:43.48#ibcon#about to read 4, iclass 39, count 0 2006.201.20:09:43.48#ibcon#read 4, iclass 39, count 0 2006.201.20:09:43.48#ibcon#about to read 5, iclass 39, count 0 2006.201.20:09:43.48#ibcon#read 5, iclass 39, count 0 2006.201.20:09:43.48#ibcon#about to read 6, iclass 39, count 0 2006.201.20:09:43.48#ibcon#read 6, iclass 39, count 0 2006.201.20:09:43.48#ibcon#end of sib2, iclass 39, count 0 2006.201.20:09:43.48#ibcon#*after write, iclass 39, count 0 2006.201.20:09:43.48#ibcon#*before return 0, iclass 39, count 0 2006.201.20:09:43.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:09:43.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:09:43.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.20:09:43.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.20:09:43.48$setupk4/ifdk4 2006.201.20:09:43.48$ifdk4/lo= 2006.201.20:09:43.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:09:43.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:09:43.48$ifdk4/patch= 2006.201.20:09:43.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:09:43.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:09:43.48$setupk4/!*+20s 2006.201.20:09:48.66#abcon#<5=/04 2.5 4.6 20.151001001.9\r\n> 2006.201.20:09:48.68#abcon#{5=INTERFACE CLEAR} 2006.201.20:09:48.74#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:09:57.13#trakl#Source acquired 2006.201.20:09:57.13#flagr#flagr/antenna,acquired 2006.201.20:09:57.93$setupk4/"tpicd 2006.201.20:09:57.93$setupk4/echo=off 2006.201.20:09:57.93$setupk4/xlog=off 2006.201.20:09:57.93:!2006.201.20:14:04 2006.201.20:14:04.00:preob 2006.201.20:14:04.14/onsource/TRACKING 2006.201.20:14:04.14:!2006.201.20:14:14 2006.201.20:14:14.00:"tape 2006.201.20:14:14.00:"st=record 2006.201.20:14:14.00:data_valid=on 2006.201.20:14:14.00:midob 2006.201.20:14:15.14/onsource/TRACKING 2006.201.20:14:15.14/wx/20.12,1002.0,100 2006.201.20:14:15.30/cable/+6.4793E-03 2006.201.20:14:16.39/va/01,08,usb,yes,37,40 2006.201.20:14:16.39/va/02,07,usb,yes,40,41 2006.201.20:14:16.39/va/03,08,usb,yes,36,38 2006.201.20:14:16.39/va/04,07,usb,yes,41,43 2006.201.20:14:16.39/va/05,04,usb,yes,37,38 2006.201.20:14:16.39/va/06,05,usb,yes,37,37 2006.201.20:14:16.39/va/07,05,usb,yes,36,37 2006.201.20:14:16.39/va/08,04,usb,yes,36,43 2006.201.20:14:16.62/valo/01,524.99,yes,locked 2006.201.20:14:16.62/valo/02,534.99,yes,locked 2006.201.20:14:16.62/valo/03,564.99,yes,locked 2006.201.20:14:16.62/valo/04,624.99,yes,locked 2006.201.20:14:16.62/valo/05,734.99,yes,locked 2006.201.20:14:16.62/valo/06,814.99,yes,locked 2006.201.20:14:16.62/valo/07,864.99,yes,locked 2006.201.20:14:16.62/valo/08,884.99,yes,locked 2006.201.20:14:17.71/vb/01,04,usb,yes,29,27 2006.201.20:14:17.71/vb/02,05,usb,yes,27,27 2006.201.20:14:17.71/vb/03,04,usb,yes,28,31 2006.201.20:14:17.71/vb/04,05,usb,yes,28,27 2006.201.20:14:17.71/vb/05,04,usb,yes,25,27 2006.201.20:14:17.71/vb/06,04,usb,yes,29,26 2006.201.20:14:17.71/vb/07,04,usb,yes,29,29 2006.201.20:14:17.71/vb/08,04,usb,yes,27,30 2006.201.20:14:17.95/vblo/01,629.99,yes,locked 2006.201.20:14:17.95/vblo/02,634.99,yes,locked 2006.201.20:14:17.95/vblo/03,649.99,yes,locked 2006.201.20:14:17.95/vblo/04,679.99,yes,locked 2006.201.20:14:17.95/vblo/05,709.99,yes,locked 2006.201.20:14:17.95/vblo/06,719.99,yes,locked 2006.201.20:14:17.95/vblo/07,734.99,yes,locked 2006.201.20:14:17.95/vblo/08,744.99,yes,locked 2006.201.20:14:18.10/vabw/8 2006.201.20:14:18.25/vbbw/8 2006.201.20:14:18.34/xfe/off,on,14.2 2006.201.20:14:18.72/ifatt/23,28,28,28 2006.201.20:14:19.07/fmout-gps/S +4.54E-07 2006.201.20:14:19.11:!2006.201.20:17:44 2006.201.20:17:44.00:data_valid=off 2006.201.20:17:44.00:"et 2006.201.20:17:44.00:!+3s 2006.201.20:17:47.02:"tape 2006.201.20:17:47.02:postob 2006.201.20:17:47.17/cable/+6.4816E-03 2006.201.20:17:47.20/wx/20.10,1002.2,100 2006.201.20:17:47.28/fmout-gps/S +4.55E-07 2006.201.20:17:47.28:scan_name=201-2021,jd0607,130 2006.201.20:17:47.28:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.201.20:17:48.13#flagr#flagr/antenna,new-source 2006.201.20:17:48.13:checkk5 2006.201.20:17:48.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:17:48.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:17:49.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:17:49.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:17:50.01/chk_obsdata//k5ts1/T2012014??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.20:17:50.38/chk_obsdata//k5ts2/T2012014??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.20:17:50.75/chk_obsdata//k5ts3/T2012014??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.20:17:51.11/chk_obsdata//k5ts4/T2012014??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.20:17:51.80/k5log//k5ts1_log_newline 2006.201.20:17:52.49/k5log//k5ts2_log_newline 2006.201.20:17:53.18/k5log//k5ts3_log_newline 2006.201.20:17:53.86/k5log//k5ts4_log_newline 2006.201.20:17:53.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:17:53.88:setupk4=1 2006.201.20:17:53.88$setupk4/echo=on 2006.201.20:17:53.88$setupk4/pcalon 2006.201.20:17:53.88$pcalon/"no phase cal control is implemented here 2006.201.20:17:53.88$setupk4/"tpicd=stop 2006.201.20:17:53.88$setupk4/"rec=synch_on 2006.201.20:17:53.88$setupk4/"rec_mode=128 2006.201.20:17:53.88$setupk4/!* 2006.201.20:17:53.88$setupk4/recpk4 2006.201.20:17:53.88$recpk4/recpatch= 2006.201.20:17:53.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:17:53.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:17:53.89$setupk4/vck44 2006.201.20:17:53.89$vck44/valo=1,524.99 2006.201.20:17:53.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.20:17:53.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.20:17:53.89#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:53.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:53.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:53.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:53.89#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:17:53.89#ibcon#first serial, iclass 20, count 0 2006.201.20:17:53.89#ibcon#enter sib2, iclass 20, count 0 2006.201.20:17:53.89#ibcon#flushed, iclass 20, count 0 2006.201.20:17:53.89#ibcon#about to write, iclass 20, count 0 2006.201.20:17:53.89#ibcon#wrote, iclass 20, count 0 2006.201.20:17:53.89#ibcon#about to read 3, iclass 20, count 0 2006.201.20:17:53.92#ibcon#read 3, iclass 20, count 0 2006.201.20:17:53.92#ibcon#about to read 4, iclass 20, count 0 2006.201.20:17:53.92#ibcon#read 4, iclass 20, count 0 2006.201.20:17:53.92#ibcon#about to read 5, iclass 20, count 0 2006.201.20:17:53.92#ibcon#read 5, iclass 20, count 0 2006.201.20:17:53.92#ibcon#about to read 6, iclass 20, count 0 2006.201.20:17:53.92#ibcon#read 6, iclass 20, count 0 2006.201.20:17:53.92#ibcon#end of sib2, iclass 20, count 0 2006.201.20:17:53.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:17:53.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:17:53.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:17:53.92#ibcon#*before write, iclass 20, count 0 2006.201.20:17:53.92#ibcon#enter sib2, iclass 20, count 0 2006.201.20:17:53.92#ibcon#flushed, iclass 20, count 0 2006.201.20:17:53.92#ibcon#about to write, iclass 20, count 0 2006.201.20:17:53.92#ibcon#wrote, iclass 20, count 0 2006.201.20:17:53.92#ibcon#about to read 3, iclass 20, count 0 2006.201.20:17:53.97#ibcon#read 3, iclass 20, count 0 2006.201.20:17:53.97#ibcon#about to read 4, iclass 20, count 0 2006.201.20:17:53.97#ibcon#read 4, iclass 20, count 0 2006.201.20:17:53.97#ibcon#about to read 5, iclass 20, count 0 2006.201.20:17:53.97#ibcon#read 5, iclass 20, count 0 2006.201.20:17:53.97#ibcon#about to read 6, iclass 20, count 0 2006.201.20:17:53.97#ibcon#read 6, iclass 20, count 0 2006.201.20:17:53.97#ibcon#end of sib2, iclass 20, count 0 2006.201.20:17:53.97#ibcon#*after write, iclass 20, count 0 2006.201.20:17:53.97#ibcon#*before return 0, iclass 20, count 0 2006.201.20:17:53.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:53.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:53.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:17:53.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:17:53.97$vck44/va=1,8 2006.201.20:17:53.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.20:17:53.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.20:17:53.97#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:53.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:53.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:53.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:53.97#ibcon#enter wrdev, iclass 22, count 2 2006.201.20:17:53.97#ibcon#first serial, iclass 22, count 2 2006.201.20:17:53.97#ibcon#enter sib2, iclass 22, count 2 2006.201.20:17:53.97#ibcon#flushed, iclass 22, count 2 2006.201.20:17:53.97#ibcon#about to write, iclass 22, count 2 2006.201.20:17:53.97#ibcon#wrote, iclass 22, count 2 2006.201.20:17:53.97#ibcon#about to read 3, iclass 22, count 2 2006.201.20:17:53.99#ibcon#read 3, iclass 22, count 2 2006.201.20:17:53.99#ibcon#about to read 4, iclass 22, count 2 2006.201.20:17:53.99#ibcon#read 4, iclass 22, count 2 2006.201.20:17:53.99#ibcon#about to read 5, iclass 22, count 2 2006.201.20:17:53.99#ibcon#read 5, iclass 22, count 2 2006.201.20:17:53.99#ibcon#about to read 6, iclass 22, count 2 2006.201.20:17:53.99#ibcon#read 6, iclass 22, count 2 2006.201.20:17:53.99#ibcon#end of sib2, iclass 22, count 2 2006.201.20:17:53.99#ibcon#*mode == 0, iclass 22, count 2 2006.201.20:17:53.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.20:17:53.99#ibcon#[25=AT01-08\r\n] 2006.201.20:17:53.99#ibcon#*before write, iclass 22, count 2 2006.201.20:17:53.99#ibcon#enter sib2, iclass 22, count 2 2006.201.20:17:53.99#ibcon#flushed, iclass 22, count 2 2006.201.20:17:53.99#ibcon#about to write, iclass 22, count 2 2006.201.20:17:53.99#ibcon#wrote, iclass 22, count 2 2006.201.20:17:53.99#ibcon#about to read 3, iclass 22, count 2 2006.201.20:17:54.02#ibcon#read 3, iclass 22, count 2 2006.201.20:17:54.02#ibcon#about to read 4, iclass 22, count 2 2006.201.20:17:54.02#ibcon#read 4, iclass 22, count 2 2006.201.20:17:54.02#ibcon#about to read 5, iclass 22, count 2 2006.201.20:17:54.02#ibcon#read 5, iclass 22, count 2 2006.201.20:17:54.02#ibcon#about to read 6, iclass 22, count 2 2006.201.20:17:54.02#ibcon#read 6, iclass 22, count 2 2006.201.20:17:54.02#ibcon#end of sib2, iclass 22, count 2 2006.201.20:17:54.02#ibcon#*after write, iclass 22, count 2 2006.201.20:17:54.02#ibcon#*before return 0, iclass 22, count 2 2006.201.20:17:54.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:54.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:54.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.20:17:54.02#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:54.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:54.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:54.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:54.14#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:17:54.14#ibcon#first serial, iclass 22, count 0 2006.201.20:17:54.14#ibcon#enter sib2, iclass 22, count 0 2006.201.20:17:54.14#ibcon#flushed, iclass 22, count 0 2006.201.20:17:54.14#ibcon#about to write, iclass 22, count 0 2006.201.20:17:54.14#ibcon#wrote, iclass 22, count 0 2006.201.20:17:54.14#ibcon#about to read 3, iclass 22, count 0 2006.201.20:17:54.16#ibcon#read 3, iclass 22, count 0 2006.201.20:17:54.16#ibcon#about to read 4, iclass 22, count 0 2006.201.20:17:54.16#ibcon#read 4, iclass 22, count 0 2006.201.20:17:54.16#ibcon#about to read 5, iclass 22, count 0 2006.201.20:17:54.16#ibcon#read 5, iclass 22, count 0 2006.201.20:17:54.16#ibcon#about to read 6, iclass 22, count 0 2006.201.20:17:54.16#ibcon#read 6, iclass 22, count 0 2006.201.20:17:54.16#ibcon#end of sib2, iclass 22, count 0 2006.201.20:17:54.16#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:17:54.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:17:54.16#ibcon#[25=USB\r\n] 2006.201.20:17:54.16#ibcon#*before write, iclass 22, count 0 2006.201.20:17:54.16#ibcon#enter sib2, iclass 22, count 0 2006.201.20:17:54.16#ibcon#flushed, iclass 22, count 0 2006.201.20:17:54.16#ibcon#about to write, iclass 22, count 0 2006.201.20:17:54.16#ibcon#wrote, iclass 22, count 0 2006.201.20:17:54.16#ibcon#about to read 3, iclass 22, count 0 2006.201.20:17:54.19#ibcon#read 3, iclass 22, count 0 2006.201.20:17:54.19#ibcon#about to read 4, iclass 22, count 0 2006.201.20:17:54.19#ibcon#read 4, iclass 22, count 0 2006.201.20:17:54.19#ibcon#about to read 5, iclass 22, count 0 2006.201.20:17:54.19#ibcon#read 5, iclass 22, count 0 2006.201.20:17:54.19#ibcon#about to read 6, iclass 22, count 0 2006.201.20:17:54.19#ibcon#read 6, iclass 22, count 0 2006.201.20:17:54.19#ibcon#end of sib2, iclass 22, count 0 2006.201.20:17:54.19#ibcon#*after write, iclass 22, count 0 2006.201.20:17:54.19#ibcon#*before return 0, iclass 22, count 0 2006.201.20:17:54.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:54.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:54.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:17:54.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:17:54.19$vck44/valo=2,534.99 2006.201.20:17:54.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.20:17:54.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.20:17:54.19#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:54.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:17:54.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:17:54.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:17:54.19#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:17:54.19#ibcon#first serial, iclass 24, count 0 2006.201.20:17:54.19#ibcon#enter sib2, iclass 24, count 0 2006.201.20:17:54.19#ibcon#flushed, iclass 24, count 0 2006.201.20:17:54.19#ibcon#about to write, iclass 24, count 0 2006.201.20:17:54.19#ibcon#wrote, iclass 24, count 0 2006.201.20:17:54.19#ibcon#about to read 3, iclass 24, count 0 2006.201.20:17:54.21#ibcon#read 3, iclass 24, count 0 2006.201.20:17:54.21#ibcon#about to read 4, iclass 24, count 0 2006.201.20:17:54.21#ibcon#read 4, iclass 24, count 0 2006.201.20:17:54.21#ibcon#about to read 5, iclass 24, count 0 2006.201.20:17:54.21#ibcon#read 5, iclass 24, count 0 2006.201.20:17:54.21#ibcon#about to read 6, iclass 24, count 0 2006.201.20:17:54.21#ibcon#read 6, iclass 24, count 0 2006.201.20:17:54.21#ibcon#end of sib2, iclass 24, count 0 2006.201.20:17:54.21#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:17:54.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:17:54.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:17:54.21#ibcon#*before write, iclass 24, count 0 2006.201.20:17:54.21#ibcon#enter sib2, iclass 24, count 0 2006.201.20:17:54.21#ibcon#flushed, iclass 24, count 0 2006.201.20:17:54.21#ibcon#about to write, iclass 24, count 0 2006.201.20:17:54.21#ibcon#wrote, iclass 24, count 0 2006.201.20:17:54.21#ibcon#about to read 3, iclass 24, count 0 2006.201.20:17:54.25#ibcon#read 3, iclass 24, count 0 2006.201.20:17:54.25#ibcon#about to read 4, iclass 24, count 0 2006.201.20:17:54.25#ibcon#read 4, iclass 24, count 0 2006.201.20:17:54.25#ibcon#about to read 5, iclass 24, count 0 2006.201.20:17:54.25#ibcon#read 5, iclass 24, count 0 2006.201.20:17:54.25#ibcon#about to read 6, iclass 24, count 0 2006.201.20:17:54.25#ibcon#read 6, iclass 24, count 0 2006.201.20:17:54.25#ibcon#end of sib2, iclass 24, count 0 2006.201.20:17:54.25#ibcon#*after write, iclass 24, count 0 2006.201.20:17:54.25#ibcon#*before return 0, iclass 24, count 0 2006.201.20:17:54.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:17:54.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:17:54.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:17:54.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:17:54.25$vck44/va=2,7 2006.201.20:17:54.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.20:17:54.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.20:17:54.25#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:54.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:17:54.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:17:54.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:17:54.31#ibcon#enter wrdev, iclass 26, count 2 2006.201.20:17:54.31#ibcon#first serial, iclass 26, count 2 2006.201.20:17:54.31#ibcon#enter sib2, iclass 26, count 2 2006.201.20:17:54.31#ibcon#flushed, iclass 26, count 2 2006.201.20:17:54.31#ibcon#about to write, iclass 26, count 2 2006.201.20:17:54.31#ibcon#wrote, iclass 26, count 2 2006.201.20:17:54.31#ibcon#about to read 3, iclass 26, count 2 2006.201.20:17:54.33#ibcon#read 3, iclass 26, count 2 2006.201.20:17:54.33#ibcon#about to read 4, iclass 26, count 2 2006.201.20:17:54.33#ibcon#read 4, iclass 26, count 2 2006.201.20:17:54.33#ibcon#about to read 5, iclass 26, count 2 2006.201.20:17:54.33#ibcon#read 5, iclass 26, count 2 2006.201.20:17:54.33#ibcon#about to read 6, iclass 26, count 2 2006.201.20:17:54.33#ibcon#read 6, iclass 26, count 2 2006.201.20:17:54.33#ibcon#end of sib2, iclass 26, count 2 2006.201.20:17:54.33#ibcon#*mode == 0, iclass 26, count 2 2006.201.20:17:54.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.20:17:54.33#ibcon#[25=AT02-07\r\n] 2006.201.20:17:54.33#ibcon#*before write, iclass 26, count 2 2006.201.20:17:54.33#ibcon#enter sib2, iclass 26, count 2 2006.201.20:17:54.33#ibcon#flushed, iclass 26, count 2 2006.201.20:17:54.33#ibcon#about to write, iclass 26, count 2 2006.201.20:17:54.33#ibcon#wrote, iclass 26, count 2 2006.201.20:17:54.33#ibcon#about to read 3, iclass 26, count 2 2006.201.20:17:54.36#ibcon#read 3, iclass 26, count 2 2006.201.20:17:54.36#ibcon#about to read 4, iclass 26, count 2 2006.201.20:17:54.36#ibcon#read 4, iclass 26, count 2 2006.201.20:17:54.36#ibcon#about to read 5, iclass 26, count 2 2006.201.20:17:54.36#ibcon#read 5, iclass 26, count 2 2006.201.20:17:54.36#ibcon#about to read 6, iclass 26, count 2 2006.201.20:17:54.36#ibcon#read 6, iclass 26, count 2 2006.201.20:17:54.36#ibcon#end of sib2, iclass 26, count 2 2006.201.20:17:54.36#ibcon#*after write, iclass 26, count 2 2006.201.20:17:54.36#ibcon#*before return 0, iclass 26, count 2 2006.201.20:17:54.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:17:54.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:17:54.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.20:17:54.36#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:54.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:17:54.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:17:54.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:17:54.48#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:17:54.48#ibcon#first serial, iclass 26, count 0 2006.201.20:17:54.48#ibcon#enter sib2, iclass 26, count 0 2006.201.20:17:54.48#ibcon#flushed, iclass 26, count 0 2006.201.20:17:54.48#ibcon#about to write, iclass 26, count 0 2006.201.20:17:54.48#ibcon#wrote, iclass 26, count 0 2006.201.20:17:54.48#ibcon#about to read 3, iclass 26, count 0 2006.201.20:17:54.50#ibcon#read 3, iclass 26, count 0 2006.201.20:17:54.50#ibcon#about to read 4, iclass 26, count 0 2006.201.20:17:54.50#ibcon#read 4, iclass 26, count 0 2006.201.20:17:54.50#ibcon#about to read 5, iclass 26, count 0 2006.201.20:17:54.50#ibcon#read 5, iclass 26, count 0 2006.201.20:17:54.50#ibcon#about to read 6, iclass 26, count 0 2006.201.20:17:54.50#ibcon#read 6, iclass 26, count 0 2006.201.20:17:54.50#ibcon#end of sib2, iclass 26, count 0 2006.201.20:17:54.50#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:17:54.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:17:54.50#ibcon#[25=USB\r\n] 2006.201.20:17:54.50#ibcon#*before write, iclass 26, count 0 2006.201.20:17:54.50#ibcon#enter sib2, iclass 26, count 0 2006.201.20:17:54.50#ibcon#flushed, iclass 26, count 0 2006.201.20:17:54.50#ibcon#about to write, iclass 26, count 0 2006.201.20:17:54.50#ibcon#wrote, iclass 26, count 0 2006.201.20:17:54.50#ibcon#about to read 3, iclass 26, count 0 2006.201.20:17:54.53#ibcon#read 3, iclass 26, count 0 2006.201.20:17:54.53#ibcon#about to read 4, iclass 26, count 0 2006.201.20:17:54.53#ibcon#read 4, iclass 26, count 0 2006.201.20:17:54.53#ibcon#about to read 5, iclass 26, count 0 2006.201.20:17:54.53#ibcon#read 5, iclass 26, count 0 2006.201.20:17:54.53#ibcon#about to read 6, iclass 26, count 0 2006.201.20:17:54.53#ibcon#read 6, iclass 26, count 0 2006.201.20:17:54.53#ibcon#end of sib2, iclass 26, count 0 2006.201.20:17:54.53#ibcon#*after write, iclass 26, count 0 2006.201.20:17:54.53#ibcon#*before return 0, iclass 26, count 0 2006.201.20:17:54.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:17:54.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:17:54.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:17:54.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:17:54.53$vck44/valo=3,564.99 2006.201.20:17:54.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.20:17:54.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.20:17:54.53#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:54.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:54.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:54.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:54.53#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:17:54.53#ibcon#first serial, iclass 28, count 0 2006.201.20:17:54.53#ibcon#enter sib2, iclass 28, count 0 2006.201.20:17:54.53#ibcon#flushed, iclass 28, count 0 2006.201.20:17:54.53#ibcon#about to write, iclass 28, count 0 2006.201.20:17:54.53#ibcon#wrote, iclass 28, count 0 2006.201.20:17:54.53#ibcon#about to read 3, iclass 28, count 0 2006.201.20:17:54.55#ibcon#read 3, iclass 28, count 0 2006.201.20:17:54.55#ibcon#about to read 4, iclass 28, count 0 2006.201.20:17:54.55#ibcon#read 4, iclass 28, count 0 2006.201.20:17:54.55#ibcon#about to read 5, iclass 28, count 0 2006.201.20:17:54.55#ibcon#read 5, iclass 28, count 0 2006.201.20:17:54.55#ibcon#about to read 6, iclass 28, count 0 2006.201.20:17:54.55#ibcon#read 6, iclass 28, count 0 2006.201.20:17:54.55#ibcon#end of sib2, iclass 28, count 0 2006.201.20:17:54.55#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:17:54.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:17:54.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:17:54.55#ibcon#*before write, iclass 28, count 0 2006.201.20:17:54.55#ibcon#enter sib2, iclass 28, count 0 2006.201.20:17:54.55#ibcon#flushed, iclass 28, count 0 2006.201.20:17:54.55#ibcon#about to write, iclass 28, count 0 2006.201.20:17:54.55#ibcon#wrote, iclass 28, count 0 2006.201.20:17:54.55#ibcon#about to read 3, iclass 28, count 0 2006.201.20:17:54.59#ibcon#read 3, iclass 28, count 0 2006.201.20:17:54.59#ibcon#about to read 4, iclass 28, count 0 2006.201.20:17:54.59#ibcon#read 4, iclass 28, count 0 2006.201.20:17:54.59#ibcon#about to read 5, iclass 28, count 0 2006.201.20:17:54.59#ibcon#read 5, iclass 28, count 0 2006.201.20:17:54.59#ibcon#about to read 6, iclass 28, count 0 2006.201.20:17:54.59#ibcon#read 6, iclass 28, count 0 2006.201.20:17:54.59#ibcon#end of sib2, iclass 28, count 0 2006.201.20:17:54.59#ibcon#*after write, iclass 28, count 0 2006.201.20:17:54.59#ibcon#*before return 0, iclass 28, count 0 2006.201.20:17:54.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:54.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:54.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:17:54.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:17:54.59$vck44/va=3,8 2006.201.20:17:54.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.20:17:54.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.20:17:54.59#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:54.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:54.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:54.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:54.65#ibcon#enter wrdev, iclass 30, count 2 2006.201.20:17:54.65#ibcon#first serial, iclass 30, count 2 2006.201.20:17:54.65#ibcon#enter sib2, iclass 30, count 2 2006.201.20:17:54.65#ibcon#flushed, iclass 30, count 2 2006.201.20:17:54.65#ibcon#about to write, iclass 30, count 2 2006.201.20:17:54.65#ibcon#wrote, iclass 30, count 2 2006.201.20:17:54.65#ibcon#about to read 3, iclass 30, count 2 2006.201.20:17:54.67#ibcon#read 3, iclass 30, count 2 2006.201.20:17:54.67#ibcon#about to read 4, iclass 30, count 2 2006.201.20:17:54.67#ibcon#read 4, iclass 30, count 2 2006.201.20:17:54.67#ibcon#about to read 5, iclass 30, count 2 2006.201.20:17:54.67#ibcon#read 5, iclass 30, count 2 2006.201.20:17:54.67#ibcon#about to read 6, iclass 30, count 2 2006.201.20:17:54.67#ibcon#read 6, iclass 30, count 2 2006.201.20:17:54.67#ibcon#end of sib2, iclass 30, count 2 2006.201.20:17:54.67#ibcon#*mode == 0, iclass 30, count 2 2006.201.20:17:54.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.20:17:54.67#ibcon#[25=AT03-08\r\n] 2006.201.20:17:54.67#ibcon#*before write, iclass 30, count 2 2006.201.20:17:54.67#ibcon#enter sib2, iclass 30, count 2 2006.201.20:17:54.67#ibcon#flushed, iclass 30, count 2 2006.201.20:17:54.67#ibcon#about to write, iclass 30, count 2 2006.201.20:17:54.67#ibcon#wrote, iclass 30, count 2 2006.201.20:17:54.67#ibcon#about to read 3, iclass 30, count 2 2006.201.20:17:54.70#ibcon#read 3, iclass 30, count 2 2006.201.20:17:54.70#ibcon#about to read 4, iclass 30, count 2 2006.201.20:17:54.70#ibcon#read 4, iclass 30, count 2 2006.201.20:17:54.70#ibcon#about to read 5, iclass 30, count 2 2006.201.20:17:54.70#ibcon#read 5, iclass 30, count 2 2006.201.20:17:54.70#ibcon#about to read 6, iclass 30, count 2 2006.201.20:17:54.70#ibcon#read 6, iclass 30, count 2 2006.201.20:17:54.70#ibcon#end of sib2, iclass 30, count 2 2006.201.20:17:54.70#ibcon#*after write, iclass 30, count 2 2006.201.20:17:54.70#ibcon#*before return 0, iclass 30, count 2 2006.201.20:17:54.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:54.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:54.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.20:17:54.70#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:54.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:54.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:54.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:54.82#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:17:54.82#ibcon#first serial, iclass 30, count 0 2006.201.20:17:54.82#ibcon#enter sib2, iclass 30, count 0 2006.201.20:17:54.82#ibcon#flushed, iclass 30, count 0 2006.201.20:17:54.82#ibcon#about to write, iclass 30, count 0 2006.201.20:17:54.82#ibcon#wrote, iclass 30, count 0 2006.201.20:17:54.82#ibcon#about to read 3, iclass 30, count 0 2006.201.20:17:54.84#ibcon#read 3, iclass 30, count 0 2006.201.20:17:54.84#ibcon#about to read 4, iclass 30, count 0 2006.201.20:17:54.84#ibcon#read 4, iclass 30, count 0 2006.201.20:17:54.84#ibcon#about to read 5, iclass 30, count 0 2006.201.20:17:54.84#ibcon#read 5, iclass 30, count 0 2006.201.20:17:54.84#ibcon#about to read 6, iclass 30, count 0 2006.201.20:17:54.84#ibcon#read 6, iclass 30, count 0 2006.201.20:17:54.84#ibcon#end of sib2, iclass 30, count 0 2006.201.20:17:54.84#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:17:54.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:17:54.84#ibcon#[25=USB\r\n] 2006.201.20:17:54.84#ibcon#*before write, iclass 30, count 0 2006.201.20:17:54.84#ibcon#enter sib2, iclass 30, count 0 2006.201.20:17:54.84#ibcon#flushed, iclass 30, count 0 2006.201.20:17:54.84#ibcon#about to write, iclass 30, count 0 2006.201.20:17:54.84#ibcon#wrote, iclass 30, count 0 2006.201.20:17:54.84#ibcon#about to read 3, iclass 30, count 0 2006.201.20:17:54.87#ibcon#read 3, iclass 30, count 0 2006.201.20:17:54.87#ibcon#about to read 4, iclass 30, count 0 2006.201.20:17:54.87#ibcon#read 4, iclass 30, count 0 2006.201.20:17:54.87#ibcon#about to read 5, iclass 30, count 0 2006.201.20:17:54.87#ibcon#read 5, iclass 30, count 0 2006.201.20:17:54.87#ibcon#about to read 6, iclass 30, count 0 2006.201.20:17:54.87#ibcon#read 6, iclass 30, count 0 2006.201.20:17:54.87#ibcon#end of sib2, iclass 30, count 0 2006.201.20:17:54.87#ibcon#*after write, iclass 30, count 0 2006.201.20:17:54.87#ibcon#*before return 0, iclass 30, count 0 2006.201.20:17:54.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:54.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:54.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:17:54.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:17:54.87$vck44/valo=4,624.99 2006.201.20:17:54.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.20:17:54.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.20:17:54.87#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:54.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:54.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:54.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:54.87#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:17:54.87#ibcon#first serial, iclass 32, count 0 2006.201.20:17:54.87#ibcon#enter sib2, iclass 32, count 0 2006.201.20:17:54.87#ibcon#flushed, iclass 32, count 0 2006.201.20:17:54.87#ibcon#about to write, iclass 32, count 0 2006.201.20:17:54.87#ibcon#wrote, iclass 32, count 0 2006.201.20:17:54.87#ibcon#about to read 3, iclass 32, count 0 2006.201.20:17:54.89#ibcon#read 3, iclass 32, count 0 2006.201.20:17:54.89#ibcon#about to read 4, iclass 32, count 0 2006.201.20:17:54.89#ibcon#read 4, iclass 32, count 0 2006.201.20:17:54.89#ibcon#about to read 5, iclass 32, count 0 2006.201.20:17:54.89#ibcon#read 5, iclass 32, count 0 2006.201.20:17:54.89#ibcon#about to read 6, iclass 32, count 0 2006.201.20:17:54.89#ibcon#read 6, iclass 32, count 0 2006.201.20:17:54.89#ibcon#end of sib2, iclass 32, count 0 2006.201.20:17:54.89#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:17:54.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:17:54.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:17:54.89#ibcon#*before write, iclass 32, count 0 2006.201.20:17:54.89#ibcon#enter sib2, iclass 32, count 0 2006.201.20:17:54.89#ibcon#flushed, iclass 32, count 0 2006.201.20:17:54.89#ibcon#about to write, iclass 32, count 0 2006.201.20:17:54.89#ibcon#wrote, iclass 32, count 0 2006.201.20:17:54.89#ibcon#about to read 3, iclass 32, count 0 2006.201.20:17:54.94#ibcon#read 3, iclass 32, count 0 2006.201.20:17:54.94#ibcon#about to read 4, iclass 32, count 0 2006.201.20:17:54.94#ibcon#read 4, iclass 32, count 0 2006.201.20:17:54.94#ibcon#about to read 5, iclass 32, count 0 2006.201.20:17:54.94#ibcon#read 5, iclass 32, count 0 2006.201.20:17:54.94#ibcon#about to read 6, iclass 32, count 0 2006.201.20:17:54.94#ibcon#read 6, iclass 32, count 0 2006.201.20:17:54.94#ibcon#end of sib2, iclass 32, count 0 2006.201.20:17:54.94#ibcon#*after write, iclass 32, count 0 2006.201.20:17:54.94#ibcon#*before return 0, iclass 32, count 0 2006.201.20:17:54.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:54.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:54.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:17:54.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:17:54.94$vck44/va=4,7 2006.201.20:17:54.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.20:17:54.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.20:17:54.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:54.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:54.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:54.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:54.99#ibcon#enter wrdev, iclass 34, count 2 2006.201.20:17:54.99#ibcon#first serial, iclass 34, count 2 2006.201.20:17:54.99#ibcon#enter sib2, iclass 34, count 2 2006.201.20:17:54.99#ibcon#flushed, iclass 34, count 2 2006.201.20:17:54.99#ibcon#about to write, iclass 34, count 2 2006.201.20:17:54.99#ibcon#wrote, iclass 34, count 2 2006.201.20:17:54.99#ibcon#about to read 3, iclass 34, count 2 2006.201.20:17:55.01#ibcon#read 3, iclass 34, count 2 2006.201.20:17:55.01#ibcon#about to read 4, iclass 34, count 2 2006.201.20:17:55.01#ibcon#read 4, iclass 34, count 2 2006.201.20:17:55.01#ibcon#about to read 5, iclass 34, count 2 2006.201.20:17:55.01#ibcon#read 5, iclass 34, count 2 2006.201.20:17:55.01#ibcon#about to read 6, iclass 34, count 2 2006.201.20:17:55.01#ibcon#read 6, iclass 34, count 2 2006.201.20:17:55.01#ibcon#end of sib2, iclass 34, count 2 2006.201.20:17:55.01#ibcon#*mode == 0, iclass 34, count 2 2006.201.20:17:55.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.20:17:55.01#ibcon#[25=AT04-07\r\n] 2006.201.20:17:55.01#ibcon#*before write, iclass 34, count 2 2006.201.20:17:55.01#ibcon#enter sib2, iclass 34, count 2 2006.201.20:17:55.01#ibcon#flushed, iclass 34, count 2 2006.201.20:17:55.01#ibcon#about to write, iclass 34, count 2 2006.201.20:17:55.01#ibcon#wrote, iclass 34, count 2 2006.201.20:17:55.01#ibcon#about to read 3, iclass 34, count 2 2006.201.20:17:55.04#ibcon#read 3, iclass 34, count 2 2006.201.20:17:55.04#ibcon#about to read 4, iclass 34, count 2 2006.201.20:17:55.04#ibcon#read 4, iclass 34, count 2 2006.201.20:17:55.04#ibcon#about to read 5, iclass 34, count 2 2006.201.20:17:55.04#ibcon#read 5, iclass 34, count 2 2006.201.20:17:55.04#ibcon#about to read 6, iclass 34, count 2 2006.201.20:17:55.04#ibcon#read 6, iclass 34, count 2 2006.201.20:17:55.04#ibcon#end of sib2, iclass 34, count 2 2006.201.20:17:55.04#ibcon#*after write, iclass 34, count 2 2006.201.20:17:55.04#ibcon#*before return 0, iclass 34, count 2 2006.201.20:17:55.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:55.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:55.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.20:17:55.04#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:55.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:55.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:55.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:55.16#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:17:55.16#ibcon#first serial, iclass 34, count 0 2006.201.20:17:55.16#ibcon#enter sib2, iclass 34, count 0 2006.201.20:17:55.16#ibcon#flushed, iclass 34, count 0 2006.201.20:17:55.16#ibcon#about to write, iclass 34, count 0 2006.201.20:17:55.16#ibcon#wrote, iclass 34, count 0 2006.201.20:17:55.16#ibcon#about to read 3, iclass 34, count 0 2006.201.20:17:55.18#ibcon#read 3, iclass 34, count 0 2006.201.20:17:55.18#ibcon#about to read 4, iclass 34, count 0 2006.201.20:17:55.18#ibcon#read 4, iclass 34, count 0 2006.201.20:17:55.18#ibcon#about to read 5, iclass 34, count 0 2006.201.20:17:55.18#ibcon#read 5, iclass 34, count 0 2006.201.20:17:55.18#ibcon#about to read 6, iclass 34, count 0 2006.201.20:17:55.18#ibcon#read 6, iclass 34, count 0 2006.201.20:17:55.18#ibcon#end of sib2, iclass 34, count 0 2006.201.20:17:55.18#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:17:55.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:17:55.18#ibcon#[25=USB\r\n] 2006.201.20:17:55.18#ibcon#*before write, iclass 34, count 0 2006.201.20:17:55.18#ibcon#enter sib2, iclass 34, count 0 2006.201.20:17:55.18#ibcon#flushed, iclass 34, count 0 2006.201.20:17:55.18#ibcon#about to write, iclass 34, count 0 2006.201.20:17:55.18#ibcon#wrote, iclass 34, count 0 2006.201.20:17:55.18#ibcon#about to read 3, iclass 34, count 0 2006.201.20:17:55.21#ibcon#read 3, iclass 34, count 0 2006.201.20:17:55.21#ibcon#about to read 4, iclass 34, count 0 2006.201.20:17:55.21#ibcon#read 4, iclass 34, count 0 2006.201.20:17:55.21#ibcon#about to read 5, iclass 34, count 0 2006.201.20:17:55.21#ibcon#read 5, iclass 34, count 0 2006.201.20:17:55.21#ibcon#about to read 6, iclass 34, count 0 2006.201.20:17:55.21#ibcon#read 6, iclass 34, count 0 2006.201.20:17:55.21#ibcon#end of sib2, iclass 34, count 0 2006.201.20:17:55.21#ibcon#*after write, iclass 34, count 0 2006.201.20:17:55.21#ibcon#*before return 0, iclass 34, count 0 2006.201.20:17:55.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:55.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:55.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:17:55.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:17:55.21$vck44/valo=5,734.99 2006.201.20:17:55.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.20:17:55.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.20:17:55.21#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:55.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:55.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:55.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:55.21#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:17:55.21#ibcon#first serial, iclass 36, count 0 2006.201.20:17:55.21#ibcon#enter sib2, iclass 36, count 0 2006.201.20:17:55.21#ibcon#flushed, iclass 36, count 0 2006.201.20:17:55.21#ibcon#about to write, iclass 36, count 0 2006.201.20:17:55.21#ibcon#wrote, iclass 36, count 0 2006.201.20:17:55.21#ibcon#about to read 3, iclass 36, count 0 2006.201.20:17:55.23#ibcon#read 3, iclass 36, count 0 2006.201.20:17:55.23#ibcon#about to read 4, iclass 36, count 0 2006.201.20:17:55.23#ibcon#read 4, iclass 36, count 0 2006.201.20:17:55.23#ibcon#about to read 5, iclass 36, count 0 2006.201.20:17:55.23#ibcon#read 5, iclass 36, count 0 2006.201.20:17:55.23#ibcon#about to read 6, iclass 36, count 0 2006.201.20:17:55.23#ibcon#read 6, iclass 36, count 0 2006.201.20:17:55.23#ibcon#end of sib2, iclass 36, count 0 2006.201.20:17:55.23#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:17:55.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:17:55.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:17:55.23#ibcon#*before write, iclass 36, count 0 2006.201.20:17:55.23#ibcon#enter sib2, iclass 36, count 0 2006.201.20:17:55.23#ibcon#flushed, iclass 36, count 0 2006.201.20:17:55.23#ibcon#about to write, iclass 36, count 0 2006.201.20:17:55.23#ibcon#wrote, iclass 36, count 0 2006.201.20:17:55.23#ibcon#about to read 3, iclass 36, count 0 2006.201.20:17:55.27#ibcon#read 3, iclass 36, count 0 2006.201.20:17:55.27#ibcon#about to read 4, iclass 36, count 0 2006.201.20:17:55.27#ibcon#read 4, iclass 36, count 0 2006.201.20:17:55.27#ibcon#about to read 5, iclass 36, count 0 2006.201.20:17:55.27#ibcon#read 5, iclass 36, count 0 2006.201.20:17:55.27#ibcon#about to read 6, iclass 36, count 0 2006.201.20:17:55.27#ibcon#read 6, iclass 36, count 0 2006.201.20:17:55.27#ibcon#end of sib2, iclass 36, count 0 2006.201.20:17:55.27#ibcon#*after write, iclass 36, count 0 2006.201.20:17:55.27#ibcon#*before return 0, iclass 36, count 0 2006.201.20:17:55.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:55.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:55.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:17:55.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:17:55.27$vck44/va=5,4 2006.201.20:17:55.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.20:17:55.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.20:17:55.27#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:55.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:55.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:55.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:55.33#ibcon#enter wrdev, iclass 38, count 2 2006.201.20:17:55.33#ibcon#first serial, iclass 38, count 2 2006.201.20:17:55.33#ibcon#enter sib2, iclass 38, count 2 2006.201.20:17:55.33#ibcon#flushed, iclass 38, count 2 2006.201.20:17:55.33#ibcon#about to write, iclass 38, count 2 2006.201.20:17:55.33#ibcon#wrote, iclass 38, count 2 2006.201.20:17:55.33#ibcon#about to read 3, iclass 38, count 2 2006.201.20:17:55.35#ibcon#read 3, iclass 38, count 2 2006.201.20:17:55.35#ibcon#about to read 4, iclass 38, count 2 2006.201.20:17:55.35#ibcon#read 4, iclass 38, count 2 2006.201.20:17:55.35#ibcon#about to read 5, iclass 38, count 2 2006.201.20:17:55.35#ibcon#read 5, iclass 38, count 2 2006.201.20:17:55.35#ibcon#about to read 6, iclass 38, count 2 2006.201.20:17:55.35#ibcon#read 6, iclass 38, count 2 2006.201.20:17:55.35#ibcon#end of sib2, iclass 38, count 2 2006.201.20:17:55.35#ibcon#*mode == 0, iclass 38, count 2 2006.201.20:17:55.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.20:17:55.35#ibcon#[25=AT05-04\r\n] 2006.201.20:17:55.35#ibcon#*before write, iclass 38, count 2 2006.201.20:17:55.35#ibcon#enter sib2, iclass 38, count 2 2006.201.20:17:55.35#ibcon#flushed, iclass 38, count 2 2006.201.20:17:55.35#ibcon#about to write, iclass 38, count 2 2006.201.20:17:55.35#ibcon#wrote, iclass 38, count 2 2006.201.20:17:55.35#ibcon#about to read 3, iclass 38, count 2 2006.201.20:17:55.38#ibcon#read 3, iclass 38, count 2 2006.201.20:17:55.38#ibcon#about to read 4, iclass 38, count 2 2006.201.20:17:55.38#ibcon#read 4, iclass 38, count 2 2006.201.20:17:55.38#ibcon#about to read 5, iclass 38, count 2 2006.201.20:17:55.38#ibcon#read 5, iclass 38, count 2 2006.201.20:17:55.38#ibcon#about to read 6, iclass 38, count 2 2006.201.20:17:55.38#ibcon#read 6, iclass 38, count 2 2006.201.20:17:55.38#ibcon#end of sib2, iclass 38, count 2 2006.201.20:17:55.38#ibcon#*after write, iclass 38, count 2 2006.201.20:17:55.38#ibcon#*before return 0, iclass 38, count 2 2006.201.20:17:55.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:55.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:55.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.20:17:55.38#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:55.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:55.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:55.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:55.50#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:17:55.50#ibcon#first serial, iclass 38, count 0 2006.201.20:17:55.50#ibcon#enter sib2, iclass 38, count 0 2006.201.20:17:55.50#ibcon#flushed, iclass 38, count 0 2006.201.20:17:55.50#ibcon#about to write, iclass 38, count 0 2006.201.20:17:55.50#ibcon#wrote, iclass 38, count 0 2006.201.20:17:55.50#ibcon#about to read 3, iclass 38, count 0 2006.201.20:17:55.52#ibcon#read 3, iclass 38, count 0 2006.201.20:17:55.52#ibcon#about to read 4, iclass 38, count 0 2006.201.20:17:55.52#ibcon#read 4, iclass 38, count 0 2006.201.20:17:55.52#ibcon#about to read 5, iclass 38, count 0 2006.201.20:17:55.52#ibcon#read 5, iclass 38, count 0 2006.201.20:17:55.52#ibcon#about to read 6, iclass 38, count 0 2006.201.20:17:55.52#ibcon#read 6, iclass 38, count 0 2006.201.20:17:55.52#ibcon#end of sib2, iclass 38, count 0 2006.201.20:17:55.52#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:17:55.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:17:55.52#ibcon#[25=USB\r\n] 2006.201.20:17:55.52#ibcon#*before write, iclass 38, count 0 2006.201.20:17:55.52#ibcon#enter sib2, iclass 38, count 0 2006.201.20:17:55.52#ibcon#flushed, iclass 38, count 0 2006.201.20:17:55.52#ibcon#about to write, iclass 38, count 0 2006.201.20:17:55.52#ibcon#wrote, iclass 38, count 0 2006.201.20:17:55.52#ibcon#about to read 3, iclass 38, count 0 2006.201.20:17:55.55#ibcon#read 3, iclass 38, count 0 2006.201.20:17:55.55#ibcon#about to read 4, iclass 38, count 0 2006.201.20:17:55.55#ibcon#read 4, iclass 38, count 0 2006.201.20:17:55.55#ibcon#about to read 5, iclass 38, count 0 2006.201.20:17:55.55#ibcon#read 5, iclass 38, count 0 2006.201.20:17:55.55#ibcon#about to read 6, iclass 38, count 0 2006.201.20:17:55.55#ibcon#read 6, iclass 38, count 0 2006.201.20:17:55.55#ibcon#end of sib2, iclass 38, count 0 2006.201.20:17:55.55#ibcon#*after write, iclass 38, count 0 2006.201.20:17:55.55#ibcon#*before return 0, iclass 38, count 0 2006.201.20:17:55.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:55.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:55.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:17:55.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:17:55.55$vck44/valo=6,814.99 2006.201.20:17:55.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.20:17:55.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.20:17:55.55#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:55.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:55.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:55.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:55.55#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:17:55.55#ibcon#first serial, iclass 40, count 0 2006.201.20:17:55.55#ibcon#enter sib2, iclass 40, count 0 2006.201.20:17:55.55#ibcon#flushed, iclass 40, count 0 2006.201.20:17:55.55#ibcon#about to write, iclass 40, count 0 2006.201.20:17:55.55#ibcon#wrote, iclass 40, count 0 2006.201.20:17:55.55#ibcon#about to read 3, iclass 40, count 0 2006.201.20:17:55.57#ibcon#read 3, iclass 40, count 0 2006.201.20:17:55.57#ibcon#about to read 4, iclass 40, count 0 2006.201.20:17:55.57#ibcon#read 4, iclass 40, count 0 2006.201.20:17:55.57#ibcon#about to read 5, iclass 40, count 0 2006.201.20:17:55.57#ibcon#read 5, iclass 40, count 0 2006.201.20:17:55.57#ibcon#about to read 6, iclass 40, count 0 2006.201.20:17:55.57#ibcon#read 6, iclass 40, count 0 2006.201.20:17:55.57#ibcon#end of sib2, iclass 40, count 0 2006.201.20:17:55.57#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:17:55.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:17:55.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:17:55.57#ibcon#*before write, iclass 40, count 0 2006.201.20:17:55.57#ibcon#enter sib2, iclass 40, count 0 2006.201.20:17:55.57#ibcon#flushed, iclass 40, count 0 2006.201.20:17:55.57#ibcon#about to write, iclass 40, count 0 2006.201.20:17:55.57#ibcon#wrote, iclass 40, count 0 2006.201.20:17:55.57#ibcon#about to read 3, iclass 40, count 0 2006.201.20:17:55.62#ibcon#read 3, iclass 40, count 0 2006.201.20:17:55.62#ibcon#about to read 4, iclass 40, count 0 2006.201.20:17:55.62#ibcon#read 4, iclass 40, count 0 2006.201.20:17:55.62#ibcon#about to read 5, iclass 40, count 0 2006.201.20:17:55.62#ibcon#read 5, iclass 40, count 0 2006.201.20:17:55.62#ibcon#about to read 6, iclass 40, count 0 2006.201.20:17:55.62#ibcon#read 6, iclass 40, count 0 2006.201.20:17:55.62#ibcon#end of sib2, iclass 40, count 0 2006.201.20:17:55.62#ibcon#*after write, iclass 40, count 0 2006.201.20:17:55.62#ibcon#*before return 0, iclass 40, count 0 2006.201.20:17:55.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:55.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:55.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:17:55.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:17:55.62$vck44/va=6,5 2006.201.20:17:55.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.20:17:55.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.20:17:55.62#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:55.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:55.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:55.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:55.67#ibcon#enter wrdev, iclass 4, count 2 2006.201.20:17:55.67#ibcon#first serial, iclass 4, count 2 2006.201.20:17:55.67#ibcon#enter sib2, iclass 4, count 2 2006.201.20:17:55.67#ibcon#flushed, iclass 4, count 2 2006.201.20:17:55.67#ibcon#about to write, iclass 4, count 2 2006.201.20:17:55.67#ibcon#wrote, iclass 4, count 2 2006.201.20:17:55.67#ibcon#about to read 3, iclass 4, count 2 2006.201.20:17:55.69#ibcon#read 3, iclass 4, count 2 2006.201.20:17:55.69#ibcon#about to read 4, iclass 4, count 2 2006.201.20:17:55.69#ibcon#read 4, iclass 4, count 2 2006.201.20:17:55.69#ibcon#about to read 5, iclass 4, count 2 2006.201.20:17:55.69#ibcon#read 5, iclass 4, count 2 2006.201.20:17:55.69#ibcon#about to read 6, iclass 4, count 2 2006.201.20:17:55.69#ibcon#read 6, iclass 4, count 2 2006.201.20:17:55.69#ibcon#end of sib2, iclass 4, count 2 2006.201.20:17:55.69#ibcon#*mode == 0, iclass 4, count 2 2006.201.20:17:55.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.20:17:55.69#ibcon#[25=AT06-05\r\n] 2006.201.20:17:55.69#ibcon#*before write, iclass 4, count 2 2006.201.20:17:55.69#ibcon#enter sib2, iclass 4, count 2 2006.201.20:17:55.69#ibcon#flushed, iclass 4, count 2 2006.201.20:17:55.69#ibcon#about to write, iclass 4, count 2 2006.201.20:17:55.69#ibcon#wrote, iclass 4, count 2 2006.201.20:17:55.69#ibcon#about to read 3, iclass 4, count 2 2006.201.20:17:55.72#ibcon#read 3, iclass 4, count 2 2006.201.20:17:55.72#ibcon#about to read 4, iclass 4, count 2 2006.201.20:17:55.72#ibcon#read 4, iclass 4, count 2 2006.201.20:17:55.72#ibcon#about to read 5, iclass 4, count 2 2006.201.20:17:55.72#ibcon#read 5, iclass 4, count 2 2006.201.20:17:55.72#ibcon#about to read 6, iclass 4, count 2 2006.201.20:17:55.72#ibcon#read 6, iclass 4, count 2 2006.201.20:17:55.72#ibcon#end of sib2, iclass 4, count 2 2006.201.20:17:55.72#ibcon#*after write, iclass 4, count 2 2006.201.20:17:55.72#ibcon#*before return 0, iclass 4, count 2 2006.201.20:17:55.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:55.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:55.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.20:17:55.72#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:55.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:55.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:55.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:55.84#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:17:55.84#ibcon#first serial, iclass 4, count 0 2006.201.20:17:55.84#ibcon#enter sib2, iclass 4, count 0 2006.201.20:17:55.84#ibcon#flushed, iclass 4, count 0 2006.201.20:17:55.84#ibcon#about to write, iclass 4, count 0 2006.201.20:17:55.84#ibcon#wrote, iclass 4, count 0 2006.201.20:17:55.84#ibcon#about to read 3, iclass 4, count 0 2006.201.20:17:55.86#ibcon#read 3, iclass 4, count 0 2006.201.20:17:55.86#ibcon#about to read 4, iclass 4, count 0 2006.201.20:17:55.86#ibcon#read 4, iclass 4, count 0 2006.201.20:17:55.86#ibcon#about to read 5, iclass 4, count 0 2006.201.20:17:55.86#ibcon#read 5, iclass 4, count 0 2006.201.20:17:55.86#ibcon#about to read 6, iclass 4, count 0 2006.201.20:17:55.86#ibcon#read 6, iclass 4, count 0 2006.201.20:17:55.86#ibcon#end of sib2, iclass 4, count 0 2006.201.20:17:55.86#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:17:55.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:17:55.86#ibcon#[25=USB\r\n] 2006.201.20:17:55.86#ibcon#*before write, iclass 4, count 0 2006.201.20:17:55.86#ibcon#enter sib2, iclass 4, count 0 2006.201.20:17:55.86#ibcon#flushed, iclass 4, count 0 2006.201.20:17:55.86#ibcon#about to write, iclass 4, count 0 2006.201.20:17:55.86#ibcon#wrote, iclass 4, count 0 2006.201.20:17:55.86#ibcon#about to read 3, iclass 4, count 0 2006.201.20:17:55.89#ibcon#read 3, iclass 4, count 0 2006.201.20:17:55.89#ibcon#about to read 4, iclass 4, count 0 2006.201.20:17:55.89#ibcon#read 4, iclass 4, count 0 2006.201.20:17:55.89#ibcon#about to read 5, iclass 4, count 0 2006.201.20:17:55.89#ibcon#read 5, iclass 4, count 0 2006.201.20:17:55.89#ibcon#about to read 6, iclass 4, count 0 2006.201.20:17:55.89#ibcon#read 6, iclass 4, count 0 2006.201.20:17:55.89#ibcon#end of sib2, iclass 4, count 0 2006.201.20:17:55.89#ibcon#*after write, iclass 4, count 0 2006.201.20:17:55.89#ibcon#*before return 0, iclass 4, count 0 2006.201.20:17:55.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:55.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:55.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:17:55.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:17:55.89$vck44/valo=7,864.99 2006.201.20:17:55.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.20:17:55.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.20:17:55.89#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:55.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:55.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:55.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:55.89#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:17:55.89#ibcon#first serial, iclass 6, count 0 2006.201.20:17:55.89#ibcon#enter sib2, iclass 6, count 0 2006.201.20:17:55.89#ibcon#flushed, iclass 6, count 0 2006.201.20:17:55.89#ibcon#about to write, iclass 6, count 0 2006.201.20:17:55.89#ibcon#wrote, iclass 6, count 0 2006.201.20:17:55.89#ibcon#about to read 3, iclass 6, count 0 2006.201.20:17:55.91#ibcon#read 3, iclass 6, count 0 2006.201.20:17:55.91#ibcon#about to read 4, iclass 6, count 0 2006.201.20:17:55.91#ibcon#read 4, iclass 6, count 0 2006.201.20:17:55.91#ibcon#about to read 5, iclass 6, count 0 2006.201.20:17:55.91#ibcon#read 5, iclass 6, count 0 2006.201.20:17:55.91#ibcon#about to read 6, iclass 6, count 0 2006.201.20:17:55.91#ibcon#read 6, iclass 6, count 0 2006.201.20:17:55.91#ibcon#end of sib2, iclass 6, count 0 2006.201.20:17:55.91#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:17:55.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:17:55.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:17:55.91#ibcon#*before write, iclass 6, count 0 2006.201.20:17:55.91#ibcon#enter sib2, iclass 6, count 0 2006.201.20:17:55.91#ibcon#flushed, iclass 6, count 0 2006.201.20:17:55.91#ibcon#about to write, iclass 6, count 0 2006.201.20:17:55.91#ibcon#wrote, iclass 6, count 0 2006.201.20:17:55.91#ibcon#about to read 3, iclass 6, count 0 2006.201.20:17:55.95#ibcon#read 3, iclass 6, count 0 2006.201.20:17:55.95#ibcon#about to read 4, iclass 6, count 0 2006.201.20:17:55.95#ibcon#read 4, iclass 6, count 0 2006.201.20:17:55.95#ibcon#about to read 5, iclass 6, count 0 2006.201.20:17:55.95#ibcon#read 5, iclass 6, count 0 2006.201.20:17:55.95#ibcon#about to read 6, iclass 6, count 0 2006.201.20:17:55.95#ibcon#read 6, iclass 6, count 0 2006.201.20:17:55.95#ibcon#end of sib2, iclass 6, count 0 2006.201.20:17:55.95#ibcon#*after write, iclass 6, count 0 2006.201.20:17:55.95#ibcon#*before return 0, iclass 6, count 0 2006.201.20:17:55.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:55.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:55.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:17:55.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:17:55.95$vck44/va=7,5 2006.201.20:17:55.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.20:17:55.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.20:17:55.95#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:55.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:56.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:56.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:56.01#ibcon#enter wrdev, iclass 10, count 2 2006.201.20:17:56.01#ibcon#first serial, iclass 10, count 2 2006.201.20:17:56.01#ibcon#enter sib2, iclass 10, count 2 2006.201.20:17:56.01#ibcon#flushed, iclass 10, count 2 2006.201.20:17:56.01#ibcon#about to write, iclass 10, count 2 2006.201.20:17:56.01#ibcon#wrote, iclass 10, count 2 2006.201.20:17:56.01#ibcon#about to read 3, iclass 10, count 2 2006.201.20:17:56.03#ibcon#read 3, iclass 10, count 2 2006.201.20:17:56.03#ibcon#about to read 4, iclass 10, count 2 2006.201.20:17:56.03#ibcon#read 4, iclass 10, count 2 2006.201.20:17:56.03#ibcon#about to read 5, iclass 10, count 2 2006.201.20:17:56.03#ibcon#read 5, iclass 10, count 2 2006.201.20:17:56.03#ibcon#about to read 6, iclass 10, count 2 2006.201.20:17:56.03#ibcon#read 6, iclass 10, count 2 2006.201.20:17:56.03#ibcon#end of sib2, iclass 10, count 2 2006.201.20:17:56.03#ibcon#*mode == 0, iclass 10, count 2 2006.201.20:17:56.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.20:17:56.03#ibcon#[25=AT07-05\r\n] 2006.201.20:17:56.03#ibcon#*before write, iclass 10, count 2 2006.201.20:17:56.03#ibcon#enter sib2, iclass 10, count 2 2006.201.20:17:56.03#ibcon#flushed, iclass 10, count 2 2006.201.20:17:56.03#ibcon#about to write, iclass 10, count 2 2006.201.20:17:56.03#ibcon#wrote, iclass 10, count 2 2006.201.20:17:56.03#ibcon#about to read 3, iclass 10, count 2 2006.201.20:17:56.06#ibcon#read 3, iclass 10, count 2 2006.201.20:17:56.06#ibcon#about to read 4, iclass 10, count 2 2006.201.20:17:56.06#ibcon#read 4, iclass 10, count 2 2006.201.20:17:56.06#ibcon#about to read 5, iclass 10, count 2 2006.201.20:17:56.06#ibcon#read 5, iclass 10, count 2 2006.201.20:17:56.06#ibcon#about to read 6, iclass 10, count 2 2006.201.20:17:56.06#ibcon#read 6, iclass 10, count 2 2006.201.20:17:56.06#ibcon#end of sib2, iclass 10, count 2 2006.201.20:17:56.06#ibcon#*after write, iclass 10, count 2 2006.201.20:17:56.06#ibcon#*before return 0, iclass 10, count 2 2006.201.20:17:56.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:56.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:56.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.20:17:56.06#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:56.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:56.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:56.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:56.18#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:17:56.18#ibcon#first serial, iclass 10, count 0 2006.201.20:17:56.18#ibcon#enter sib2, iclass 10, count 0 2006.201.20:17:56.18#ibcon#flushed, iclass 10, count 0 2006.201.20:17:56.18#ibcon#about to write, iclass 10, count 0 2006.201.20:17:56.18#ibcon#wrote, iclass 10, count 0 2006.201.20:17:56.18#ibcon#about to read 3, iclass 10, count 0 2006.201.20:17:56.20#ibcon#read 3, iclass 10, count 0 2006.201.20:17:56.20#ibcon#about to read 4, iclass 10, count 0 2006.201.20:17:56.20#ibcon#read 4, iclass 10, count 0 2006.201.20:17:56.20#ibcon#about to read 5, iclass 10, count 0 2006.201.20:17:56.20#ibcon#read 5, iclass 10, count 0 2006.201.20:17:56.20#ibcon#about to read 6, iclass 10, count 0 2006.201.20:17:56.20#ibcon#read 6, iclass 10, count 0 2006.201.20:17:56.20#ibcon#end of sib2, iclass 10, count 0 2006.201.20:17:56.20#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:17:56.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:17:56.20#ibcon#[25=USB\r\n] 2006.201.20:17:56.20#ibcon#*before write, iclass 10, count 0 2006.201.20:17:56.20#ibcon#enter sib2, iclass 10, count 0 2006.201.20:17:56.20#ibcon#flushed, iclass 10, count 0 2006.201.20:17:56.20#ibcon#about to write, iclass 10, count 0 2006.201.20:17:56.20#ibcon#wrote, iclass 10, count 0 2006.201.20:17:56.20#ibcon#about to read 3, iclass 10, count 0 2006.201.20:17:56.23#ibcon#read 3, iclass 10, count 0 2006.201.20:17:56.23#ibcon#about to read 4, iclass 10, count 0 2006.201.20:17:56.23#ibcon#read 4, iclass 10, count 0 2006.201.20:17:56.23#ibcon#about to read 5, iclass 10, count 0 2006.201.20:17:56.23#ibcon#read 5, iclass 10, count 0 2006.201.20:17:56.23#ibcon#about to read 6, iclass 10, count 0 2006.201.20:17:56.23#ibcon#read 6, iclass 10, count 0 2006.201.20:17:56.23#ibcon#end of sib2, iclass 10, count 0 2006.201.20:17:56.23#ibcon#*after write, iclass 10, count 0 2006.201.20:17:56.23#ibcon#*before return 0, iclass 10, count 0 2006.201.20:17:56.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:56.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:56.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:17:56.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:17:56.23$vck44/valo=8,884.99 2006.201.20:17:56.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.20:17:56.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.20:17:56.23#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:56.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:56.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:56.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:56.23#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:17:56.23#ibcon#first serial, iclass 12, count 0 2006.201.20:17:56.23#ibcon#enter sib2, iclass 12, count 0 2006.201.20:17:56.23#ibcon#flushed, iclass 12, count 0 2006.201.20:17:56.23#ibcon#about to write, iclass 12, count 0 2006.201.20:17:56.23#ibcon#wrote, iclass 12, count 0 2006.201.20:17:56.23#ibcon#about to read 3, iclass 12, count 0 2006.201.20:17:56.25#ibcon#read 3, iclass 12, count 0 2006.201.20:17:56.25#ibcon#about to read 4, iclass 12, count 0 2006.201.20:17:56.25#ibcon#read 4, iclass 12, count 0 2006.201.20:17:56.25#ibcon#about to read 5, iclass 12, count 0 2006.201.20:17:56.25#ibcon#read 5, iclass 12, count 0 2006.201.20:17:56.25#ibcon#about to read 6, iclass 12, count 0 2006.201.20:17:56.25#ibcon#read 6, iclass 12, count 0 2006.201.20:17:56.25#ibcon#end of sib2, iclass 12, count 0 2006.201.20:17:56.25#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:17:56.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:17:56.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:17:56.25#ibcon#*before write, iclass 12, count 0 2006.201.20:17:56.25#ibcon#enter sib2, iclass 12, count 0 2006.201.20:17:56.25#ibcon#flushed, iclass 12, count 0 2006.201.20:17:56.25#ibcon#about to write, iclass 12, count 0 2006.201.20:17:56.25#ibcon#wrote, iclass 12, count 0 2006.201.20:17:56.25#ibcon#about to read 3, iclass 12, count 0 2006.201.20:17:56.30#ibcon#read 3, iclass 12, count 0 2006.201.20:17:56.30#ibcon#about to read 4, iclass 12, count 0 2006.201.20:17:56.30#ibcon#read 4, iclass 12, count 0 2006.201.20:17:56.30#ibcon#about to read 5, iclass 12, count 0 2006.201.20:17:56.30#ibcon#read 5, iclass 12, count 0 2006.201.20:17:56.30#ibcon#about to read 6, iclass 12, count 0 2006.201.20:17:56.30#ibcon#read 6, iclass 12, count 0 2006.201.20:17:56.30#ibcon#end of sib2, iclass 12, count 0 2006.201.20:17:56.30#ibcon#*after write, iclass 12, count 0 2006.201.20:17:56.30#ibcon#*before return 0, iclass 12, count 0 2006.201.20:17:56.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:56.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:56.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:17:56.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:17:56.30$vck44/va=8,4 2006.201.20:17:56.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.20:17:56.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.20:17:56.30#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:56.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:56.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:56.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:56.35#ibcon#enter wrdev, iclass 14, count 2 2006.201.20:17:56.35#ibcon#first serial, iclass 14, count 2 2006.201.20:17:56.35#ibcon#enter sib2, iclass 14, count 2 2006.201.20:17:56.35#ibcon#flushed, iclass 14, count 2 2006.201.20:17:56.35#ibcon#about to write, iclass 14, count 2 2006.201.20:17:56.35#ibcon#wrote, iclass 14, count 2 2006.201.20:17:56.35#ibcon#about to read 3, iclass 14, count 2 2006.201.20:17:56.37#ibcon#read 3, iclass 14, count 2 2006.201.20:17:56.37#ibcon#about to read 4, iclass 14, count 2 2006.201.20:17:56.37#ibcon#read 4, iclass 14, count 2 2006.201.20:17:56.37#ibcon#about to read 5, iclass 14, count 2 2006.201.20:17:56.37#ibcon#read 5, iclass 14, count 2 2006.201.20:17:56.37#ibcon#about to read 6, iclass 14, count 2 2006.201.20:17:56.37#ibcon#read 6, iclass 14, count 2 2006.201.20:17:56.37#ibcon#end of sib2, iclass 14, count 2 2006.201.20:17:56.37#ibcon#*mode == 0, iclass 14, count 2 2006.201.20:17:56.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.20:17:56.37#ibcon#[25=AT08-04\r\n] 2006.201.20:17:56.37#ibcon#*before write, iclass 14, count 2 2006.201.20:17:56.37#ibcon#enter sib2, iclass 14, count 2 2006.201.20:17:56.37#ibcon#flushed, iclass 14, count 2 2006.201.20:17:56.37#ibcon#about to write, iclass 14, count 2 2006.201.20:17:56.37#ibcon#wrote, iclass 14, count 2 2006.201.20:17:56.37#ibcon#about to read 3, iclass 14, count 2 2006.201.20:17:56.40#ibcon#read 3, iclass 14, count 2 2006.201.20:17:56.40#ibcon#about to read 4, iclass 14, count 2 2006.201.20:17:56.40#ibcon#read 4, iclass 14, count 2 2006.201.20:17:56.40#ibcon#about to read 5, iclass 14, count 2 2006.201.20:17:56.40#ibcon#read 5, iclass 14, count 2 2006.201.20:17:56.40#ibcon#about to read 6, iclass 14, count 2 2006.201.20:17:56.40#ibcon#read 6, iclass 14, count 2 2006.201.20:17:56.40#ibcon#end of sib2, iclass 14, count 2 2006.201.20:17:56.40#ibcon#*after write, iclass 14, count 2 2006.201.20:17:56.40#ibcon#*before return 0, iclass 14, count 2 2006.201.20:17:56.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:56.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:56.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.20:17:56.40#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:56.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:56.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:56.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:56.52#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:17:56.52#ibcon#first serial, iclass 14, count 0 2006.201.20:17:56.52#ibcon#enter sib2, iclass 14, count 0 2006.201.20:17:56.52#ibcon#flushed, iclass 14, count 0 2006.201.20:17:56.52#ibcon#about to write, iclass 14, count 0 2006.201.20:17:56.52#ibcon#wrote, iclass 14, count 0 2006.201.20:17:56.52#ibcon#about to read 3, iclass 14, count 0 2006.201.20:17:56.54#ibcon#read 3, iclass 14, count 0 2006.201.20:17:56.54#ibcon#about to read 4, iclass 14, count 0 2006.201.20:17:56.54#ibcon#read 4, iclass 14, count 0 2006.201.20:17:56.54#ibcon#about to read 5, iclass 14, count 0 2006.201.20:17:56.54#ibcon#read 5, iclass 14, count 0 2006.201.20:17:56.54#ibcon#about to read 6, iclass 14, count 0 2006.201.20:17:56.54#ibcon#read 6, iclass 14, count 0 2006.201.20:17:56.54#ibcon#end of sib2, iclass 14, count 0 2006.201.20:17:56.54#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:17:56.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:17:56.54#ibcon#[25=USB\r\n] 2006.201.20:17:56.54#ibcon#*before write, iclass 14, count 0 2006.201.20:17:56.54#ibcon#enter sib2, iclass 14, count 0 2006.201.20:17:56.54#ibcon#flushed, iclass 14, count 0 2006.201.20:17:56.54#ibcon#about to write, iclass 14, count 0 2006.201.20:17:56.54#ibcon#wrote, iclass 14, count 0 2006.201.20:17:56.54#ibcon#about to read 3, iclass 14, count 0 2006.201.20:17:56.57#ibcon#read 3, iclass 14, count 0 2006.201.20:17:56.57#ibcon#about to read 4, iclass 14, count 0 2006.201.20:17:56.57#ibcon#read 4, iclass 14, count 0 2006.201.20:17:56.57#ibcon#about to read 5, iclass 14, count 0 2006.201.20:17:56.57#ibcon#read 5, iclass 14, count 0 2006.201.20:17:56.57#ibcon#about to read 6, iclass 14, count 0 2006.201.20:17:56.57#ibcon#read 6, iclass 14, count 0 2006.201.20:17:56.57#ibcon#end of sib2, iclass 14, count 0 2006.201.20:17:56.57#ibcon#*after write, iclass 14, count 0 2006.201.20:17:56.57#ibcon#*before return 0, iclass 14, count 0 2006.201.20:17:56.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:56.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:56.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:17:56.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:17:56.57$vck44/vblo=1,629.99 2006.201.20:17:56.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.20:17:56.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.20:17:56.57#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:56.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:56.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:56.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:56.57#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:17:56.57#ibcon#first serial, iclass 16, count 0 2006.201.20:17:56.57#ibcon#enter sib2, iclass 16, count 0 2006.201.20:17:56.57#ibcon#flushed, iclass 16, count 0 2006.201.20:17:56.57#ibcon#about to write, iclass 16, count 0 2006.201.20:17:56.57#ibcon#wrote, iclass 16, count 0 2006.201.20:17:56.57#ibcon#about to read 3, iclass 16, count 0 2006.201.20:17:56.59#ibcon#read 3, iclass 16, count 0 2006.201.20:17:56.59#ibcon#about to read 4, iclass 16, count 0 2006.201.20:17:56.59#ibcon#read 4, iclass 16, count 0 2006.201.20:17:56.59#ibcon#about to read 5, iclass 16, count 0 2006.201.20:17:56.59#ibcon#read 5, iclass 16, count 0 2006.201.20:17:56.59#ibcon#about to read 6, iclass 16, count 0 2006.201.20:17:56.59#ibcon#read 6, iclass 16, count 0 2006.201.20:17:56.59#ibcon#end of sib2, iclass 16, count 0 2006.201.20:17:56.59#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:17:56.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:17:56.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:17:56.59#ibcon#*before write, iclass 16, count 0 2006.201.20:17:56.59#ibcon#enter sib2, iclass 16, count 0 2006.201.20:17:56.59#ibcon#flushed, iclass 16, count 0 2006.201.20:17:56.59#ibcon#about to write, iclass 16, count 0 2006.201.20:17:56.59#ibcon#wrote, iclass 16, count 0 2006.201.20:17:56.59#ibcon#about to read 3, iclass 16, count 0 2006.201.20:17:56.63#ibcon#read 3, iclass 16, count 0 2006.201.20:17:56.63#ibcon#about to read 4, iclass 16, count 0 2006.201.20:17:56.63#ibcon#read 4, iclass 16, count 0 2006.201.20:17:56.63#ibcon#about to read 5, iclass 16, count 0 2006.201.20:17:56.63#ibcon#read 5, iclass 16, count 0 2006.201.20:17:56.63#ibcon#about to read 6, iclass 16, count 0 2006.201.20:17:56.63#ibcon#read 6, iclass 16, count 0 2006.201.20:17:56.63#ibcon#end of sib2, iclass 16, count 0 2006.201.20:17:56.63#ibcon#*after write, iclass 16, count 0 2006.201.20:17:56.63#ibcon#*before return 0, iclass 16, count 0 2006.201.20:17:56.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:56.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:56.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:17:56.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:17:56.63$vck44/vb=1,4 2006.201.20:17:56.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.20:17:56.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.20:17:56.63#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:56.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:17:56.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:17:56.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:17:56.63#ibcon#enter wrdev, iclass 18, count 2 2006.201.20:17:56.63#ibcon#first serial, iclass 18, count 2 2006.201.20:17:56.63#ibcon#enter sib2, iclass 18, count 2 2006.201.20:17:56.63#ibcon#flushed, iclass 18, count 2 2006.201.20:17:56.63#ibcon#about to write, iclass 18, count 2 2006.201.20:17:56.63#ibcon#wrote, iclass 18, count 2 2006.201.20:17:56.63#ibcon#about to read 3, iclass 18, count 2 2006.201.20:17:56.65#ibcon#read 3, iclass 18, count 2 2006.201.20:17:56.65#ibcon#about to read 4, iclass 18, count 2 2006.201.20:17:56.65#ibcon#read 4, iclass 18, count 2 2006.201.20:17:56.65#ibcon#about to read 5, iclass 18, count 2 2006.201.20:17:56.65#ibcon#read 5, iclass 18, count 2 2006.201.20:17:56.65#ibcon#about to read 6, iclass 18, count 2 2006.201.20:17:56.65#ibcon#read 6, iclass 18, count 2 2006.201.20:17:56.65#ibcon#end of sib2, iclass 18, count 2 2006.201.20:17:56.65#ibcon#*mode == 0, iclass 18, count 2 2006.201.20:17:56.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.20:17:56.65#ibcon#[27=AT01-04\r\n] 2006.201.20:17:56.65#ibcon#*before write, iclass 18, count 2 2006.201.20:17:56.65#ibcon#enter sib2, iclass 18, count 2 2006.201.20:17:56.65#ibcon#flushed, iclass 18, count 2 2006.201.20:17:56.65#ibcon#about to write, iclass 18, count 2 2006.201.20:17:56.65#ibcon#wrote, iclass 18, count 2 2006.201.20:17:56.65#ibcon#about to read 3, iclass 18, count 2 2006.201.20:17:56.68#ibcon#read 3, iclass 18, count 2 2006.201.20:17:56.68#ibcon#about to read 4, iclass 18, count 2 2006.201.20:17:56.68#ibcon#read 4, iclass 18, count 2 2006.201.20:17:56.68#ibcon#about to read 5, iclass 18, count 2 2006.201.20:17:56.68#ibcon#read 5, iclass 18, count 2 2006.201.20:17:56.68#ibcon#about to read 6, iclass 18, count 2 2006.201.20:17:56.68#ibcon#read 6, iclass 18, count 2 2006.201.20:17:56.68#ibcon#end of sib2, iclass 18, count 2 2006.201.20:17:56.68#ibcon#*after write, iclass 18, count 2 2006.201.20:17:56.68#ibcon#*before return 0, iclass 18, count 2 2006.201.20:17:56.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:17:56.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:17:56.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.20:17:56.68#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:56.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:17:56.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:17:56.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:17:56.80#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:17:56.80#ibcon#first serial, iclass 18, count 0 2006.201.20:17:56.80#ibcon#enter sib2, iclass 18, count 0 2006.201.20:17:56.80#ibcon#flushed, iclass 18, count 0 2006.201.20:17:56.80#ibcon#about to write, iclass 18, count 0 2006.201.20:17:56.80#ibcon#wrote, iclass 18, count 0 2006.201.20:17:56.80#ibcon#about to read 3, iclass 18, count 0 2006.201.20:17:56.82#ibcon#read 3, iclass 18, count 0 2006.201.20:17:56.82#ibcon#about to read 4, iclass 18, count 0 2006.201.20:17:56.82#ibcon#read 4, iclass 18, count 0 2006.201.20:17:56.82#ibcon#about to read 5, iclass 18, count 0 2006.201.20:17:56.82#ibcon#read 5, iclass 18, count 0 2006.201.20:17:56.82#ibcon#about to read 6, iclass 18, count 0 2006.201.20:17:56.82#ibcon#read 6, iclass 18, count 0 2006.201.20:17:56.82#ibcon#end of sib2, iclass 18, count 0 2006.201.20:17:56.82#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:17:56.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:17:56.82#ibcon#[27=USB\r\n] 2006.201.20:17:56.82#ibcon#*before write, iclass 18, count 0 2006.201.20:17:56.82#ibcon#enter sib2, iclass 18, count 0 2006.201.20:17:56.82#ibcon#flushed, iclass 18, count 0 2006.201.20:17:56.82#ibcon#about to write, iclass 18, count 0 2006.201.20:17:56.82#ibcon#wrote, iclass 18, count 0 2006.201.20:17:56.82#ibcon#about to read 3, iclass 18, count 0 2006.201.20:17:56.85#ibcon#read 3, iclass 18, count 0 2006.201.20:17:56.85#ibcon#about to read 4, iclass 18, count 0 2006.201.20:17:56.85#ibcon#read 4, iclass 18, count 0 2006.201.20:17:56.85#ibcon#about to read 5, iclass 18, count 0 2006.201.20:17:56.85#ibcon#read 5, iclass 18, count 0 2006.201.20:17:56.85#ibcon#about to read 6, iclass 18, count 0 2006.201.20:17:56.85#ibcon#read 6, iclass 18, count 0 2006.201.20:17:56.85#ibcon#end of sib2, iclass 18, count 0 2006.201.20:17:56.85#ibcon#*after write, iclass 18, count 0 2006.201.20:17:56.85#ibcon#*before return 0, iclass 18, count 0 2006.201.20:17:56.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:17:56.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:17:56.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:17:56.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:17:56.85$vck44/vblo=2,634.99 2006.201.20:17:56.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.20:17:56.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.20:17:56.85#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:56.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:56.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:56.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:56.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:17:56.85#ibcon#first serial, iclass 20, count 0 2006.201.20:17:56.85#ibcon#enter sib2, iclass 20, count 0 2006.201.20:17:56.85#ibcon#flushed, iclass 20, count 0 2006.201.20:17:56.85#ibcon#about to write, iclass 20, count 0 2006.201.20:17:56.85#ibcon#wrote, iclass 20, count 0 2006.201.20:17:56.85#ibcon#about to read 3, iclass 20, count 0 2006.201.20:17:56.87#ibcon#read 3, iclass 20, count 0 2006.201.20:17:56.87#ibcon#about to read 4, iclass 20, count 0 2006.201.20:17:56.87#ibcon#read 4, iclass 20, count 0 2006.201.20:17:56.87#ibcon#about to read 5, iclass 20, count 0 2006.201.20:17:56.87#ibcon#read 5, iclass 20, count 0 2006.201.20:17:56.87#ibcon#about to read 6, iclass 20, count 0 2006.201.20:17:56.87#ibcon#read 6, iclass 20, count 0 2006.201.20:17:56.87#ibcon#end of sib2, iclass 20, count 0 2006.201.20:17:56.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:17:56.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:17:56.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:17:56.87#ibcon#*before write, iclass 20, count 0 2006.201.20:17:56.87#ibcon#enter sib2, iclass 20, count 0 2006.201.20:17:56.87#ibcon#flushed, iclass 20, count 0 2006.201.20:17:56.87#ibcon#about to write, iclass 20, count 0 2006.201.20:17:56.87#ibcon#wrote, iclass 20, count 0 2006.201.20:17:56.87#ibcon#about to read 3, iclass 20, count 0 2006.201.20:17:56.91#ibcon#read 3, iclass 20, count 0 2006.201.20:17:56.91#ibcon#about to read 4, iclass 20, count 0 2006.201.20:17:56.91#ibcon#read 4, iclass 20, count 0 2006.201.20:17:56.91#ibcon#about to read 5, iclass 20, count 0 2006.201.20:17:56.91#ibcon#read 5, iclass 20, count 0 2006.201.20:17:56.91#ibcon#about to read 6, iclass 20, count 0 2006.201.20:17:56.91#ibcon#read 6, iclass 20, count 0 2006.201.20:17:56.91#ibcon#end of sib2, iclass 20, count 0 2006.201.20:17:56.91#ibcon#*after write, iclass 20, count 0 2006.201.20:17:56.91#ibcon#*before return 0, iclass 20, count 0 2006.201.20:17:56.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:56.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:17:56.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:17:56.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:17:56.91$vck44/vb=2,5 2006.201.20:17:56.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.20:17:56.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.20:17:56.91#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:56.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:56.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:56.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:56.97#ibcon#enter wrdev, iclass 22, count 2 2006.201.20:17:56.97#ibcon#first serial, iclass 22, count 2 2006.201.20:17:56.97#ibcon#enter sib2, iclass 22, count 2 2006.201.20:17:56.97#ibcon#flushed, iclass 22, count 2 2006.201.20:17:56.97#ibcon#about to write, iclass 22, count 2 2006.201.20:17:56.97#ibcon#wrote, iclass 22, count 2 2006.201.20:17:56.97#ibcon#about to read 3, iclass 22, count 2 2006.201.20:17:56.99#ibcon#read 3, iclass 22, count 2 2006.201.20:17:56.99#ibcon#about to read 4, iclass 22, count 2 2006.201.20:17:56.99#ibcon#read 4, iclass 22, count 2 2006.201.20:17:56.99#ibcon#about to read 5, iclass 22, count 2 2006.201.20:17:56.99#ibcon#read 5, iclass 22, count 2 2006.201.20:17:56.99#ibcon#about to read 6, iclass 22, count 2 2006.201.20:17:56.99#ibcon#read 6, iclass 22, count 2 2006.201.20:17:56.99#ibcon#end of sib2, iclass 22, count 2 2006.201.20:17:56.99#ibcon#*mode == 0, iclass 22, count 2 2006.201.20:17:56.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.20:17:56.99#ibcon#[27=AT02-05\r\n] 2006.201.20:17:56.99#ibcon#*before write, iclass 22, count 2 2006.201.20:17:56.99#ibcon#enter sib2, iclass 22, count 2 2006.201.20:17:56.99#ibcon#flushed, iclass 22, count 2 2006.201.20:17:56.99#ibcon#about to write, iclass 22, count 2 2006.201.20:17:56.99#ibcon#wrote, iclass 22, count 2 2006.201.20:17:56.99#ibcon#about to read 3, iclass 22, count 2 2006.201.20:17:57.02#ibcon#read 3, iclass 22, count 2 2006.201.20:17:57.02#ibcon#about to read 4, iclass 22, count 2 2006.201.20:17:57.02#ibcon#read 4, iclass 22, count 2 2006.201.20:17:57.02#ibcon#about to read 5, iclass 22, count 2 2006.201.20:17:57.02#ibcon#read 5, iclass 22, count 2 2006.201.20:17:57.02#ibcon#about to read 6, iclass 22, count 2 2006.201.20:17:57.02#ibcon#read 6, iclass 22, count 2 2006.201.20:17:57.02#ibcon#end of sib2, iclass 22, count 2 2006.201.20:17:57.02#ibcon#*after write, iclass 22, count 2 2006.201.20:17:57.02#ibcon#*before return 0, iclass 22, count 2 2006.201.20:17:57.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:57.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:17:57.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.20:17:57.02#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:57.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:57.03#abcon#<5=/03 2.0 3.8 20.101001002.2\r\n> 2006.201.20:17:57.05#abcon#{5=INTERFACE CLEAR} 2006.201.20:17:57.11#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:17:57.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:57.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:57.14#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:17:57.14#ibcon#first serial, iclass 22, count 0 2006.201.20:17:57.14#ibcon#enter sib2, iclass 22, count 0 2006.201.20:17:57.14#ibcon#flushed, iclass 22, count 0 2006.201.20:17:57.14#ibcon#about to write, iclass 22, count 0 2006.201.20:17:57.14#ibcon#wrote, iclass 22, count 0 2006.201.20:17:57.14#ibcon#about to read 3, iclass 22, count 0 2006.201.20:17:57.16#ibcon#read 3, iclass 22, count 0 2006.201.20:17:57.16#ibcon#about to read 4, iclass 22, count 0 2006.201.20:17:57.16#ibcon#read 4, iclass 22, count 0 2006.201.20:17:57.16#ibcon#about to read 5, iclass 22, count 0 2006.201.20:17:57.16#ibcon#read 5, iclass 22, count 0 2006.201.20:17:57.16#ibcon#about to read 6, iclass 22, count 0 2006.201.20:17:57.16#ibcon#read 6, iclass 22, count 0 2006.201.20:17:57.16#ibcon#end of sib2, iclass 22, count 0 2006.201.20:17:57.16#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:17:57.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:17:57.16#ibcon#[27=USB\r\n] 2006.201.20:17:57.16#ibcon#*before write, iclass 22, count 0 2006.201.20:17:57.16#ibcon#enter sib2, iclass 22, count 0 2006.201.20:17:57.16#ibcon#flushed, iclass 22, count 0 2006.201.20:17:57.16#ibcon#about to write, iclass 22, count 0 2006.201.20:17:57.16#ibcon#wrote, iclass 22, count 0 2006.201.20:17:57.16#ibcon#about to read 3, iclass 22, count 0 2006.201.20:17:57.19#ibcon#read 3, iclass 22, count 0 2006.201.20:17:57.19#ibcon#about to read 4, iclass 22, count 0 2006.201.20:17:57.19#ibcon#read 4, iclass 22, count 0 2006.201.20:17:57.19#ibcon#about to read 5, iclass 22, count 0 2006.201.20:17:57.19#ibcon#read 5, iclass 22, count 0 2006.201.20:17:57.19#ibcon#about to read 6, iclass 22, count 0 2006.201.20:17:57.19#ibcon#read 6, iclass 22, count 0 2006.201.20:17:57.19#ibcon#end of sib2, iclass 22, count 0 2006.201.20:17:57.19#ibcon#*after write, iclass 22, count 0 2006.201.20:17:57.19#ibcon#*before return 0, iclass 22, count 0 2006.201.20:17:57.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:57.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:17:57.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:17:57.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:17:57.19$vck44/vblo=3,649.99 2006.201.20:17:57.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.20:17:57.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.20:17:57.19#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:57.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:57.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:57.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:57.19#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:17:57.19#ibcon#first serial, iclass 28, count 0 2006.201.20:17:57.19#ibcon#enter sib2, iclass 28, count 0 2006.201.20:17:57.19#ibcon#flushed, iclass 28, count 0 2006.201.20:17:57.19#ibcon#about to write, iclass 28, count 0 2006.201.20:17:57.19#ibcon#wrote, iclass 28, count 0 2006.201.20:17:57.19#ibcon#about to read 3, iclass 28, count 0 2006.201.20:17:57.21#ibcon#read 3, iclass 28, count 0 2006.201.20:17:57.21#ibcon#about to read 4, iclass 28, count 0 2006.201.20:17:57.21#ibcon#read 4, iclass 28, count 0 2006.201.20:17:57.21#ibcon#about to read 5, iclass 28, count 0 2006.201.20:17:57.21#ibcon#read 5, iclass 28, count 0 2006.201.20:17:57.21#ibcon#about to read 6, iclass 28, count 0 2006.201.20:17:57.21#ibcon#read 6, iclass 28, count 0 2006.201.20:17:57.21#ibcon#end of sib2, iclass 28, count 0 2006.201.20:17:57.21#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:17:57.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:17:57.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:17:57.21#ibcon#*before write, iclass 28, count 0 2006.201.20:17:57.21#ibcon#enter sib2, iclass 28, count 0 2006.201.20:17:57.21#ibcon#flushed, iclass 28, count 0 2006.201.20:17:57.21#ibcon#about to write, iclass 28, count 0 2006.201.20:17:57.21#ibcon#wrote, iclass 28, count 0 2006.201.20:17:57.21#ibcon#about to read 3, iclass 28, count 0 2006.201.20:17:57.25#ibcon#read 3, iclass 28, count 0 2006.201.20:17:57.25#ibcon#about to read 4, iclass 28, count 0 2006.201.20:17:57.25#ibcon#read 4, iclass 28, count 0 2006.201.20:17:57.25#ibcon#about to read 5, iclass 28, count 0 2006.201.20:17:57.25#ibcon#read 5, iclass 28, count 0 2006.201.20:17:57.25#ibcon#about to read 6, iclass 28, count 0 2006.201.20:17:57.25#ibcon#read 6, iclass 28, count 0 2006.201.20:17:57.25#ibcon#end of sib2, iclass 28, count 0 2006.201.20:17:57.25#ibcon#*after write, iclass 28, count 0 2006.201.20:17:57.25#ibcon#*before return 0, iclass 28, count 0 2006.201.20:17:57.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:57.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:17:57.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:17:57.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:17:57.25$vck44/vb=3,4 2006.201.20:17:57.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.20:17:57.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.20:17:57.25#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:57.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:57.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:57.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:57.31#ibcon#enter wrdev, iclass 30, count 2 2006.201.20:17:57.31#ibcon#first serial, iclass 30, count 2 2006.201.20:17:57.31#ibcon#enter sib2, iclass 30, count 2 2006.201.20:17:57.31#ibcon#flushed, iclass 30, count 2 2006.201.20:17:57.31#ibcon#about to write, iclass 30, count 2 2006.201.20:17:57.31#ibcon#wrote, iclass 30, count 2 2006.201.20:17:57.31#ibcon#about to read 3, iclass 30, count 2 2006.201.20:17:57.33#ibcon#read 3, iclass 30, count 2 2006.201.20:17:57.33#ibcon#about to read 4, iclass 30, count 2 2006.201.20:17:57.33#ibcon#read 4, iclass 30, count 2 2006.201.20:17:57.33#ibcon#about to read 5, iclass 30, count 2 2006.201.20:17:57.33#ibcon#read 5, iclass 30, count 2 2006.201.20:17:57.33#ibcon#about to read 6, iclass 30, count 2 2006.201.20:17:57.33#ibcon#read 6, iclass 30, count 2 2006.201.20:17:57.33#ibcon#end of sib2, iclass 30, count 2 2006.201.20:17:57.33#ibcon#*mode == 0, iclass 30, count 2 2006.201.20:17:57.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.20:17:57.33#ibcon#[27=AT03-04\r\n] 2006.201.20:17:57.33#ibcon#*before write, iclass 30, count 2 2006.201.20:17:57.33#ibcon#enter sib2, iclass 30, count 2 2006.201.20:17:57.33#ibcon#flushed, iclass 30, count 2 2006.201.20:17:57.33#ibcon#about to write, iclass 30, count 2 2006.201.20:17:57.33#ibcon#wrote, iclass 30, count 2 2006.201.20:17:57.33#ibcon#about to read 3, iclass 30, count 2 2006.201.20:17:57.36#ibcon#read 3, iclass 30, count 2 2006.201.20:17:57.36#ibcon#about to read 4, iclass 30, count 2 2006.201.20:17:57.36#ibcon#read 4, iclass 30, count 2 2006.201.20:17:57.36#ibcon#about to read 5, iclass 30, count 2 2006.201.20:17:57.36#ibcon#read 5, iclass 30, count 2 2006.201.20:17:57.36#ibcon#about to read 6, iclass 30, count 2 2006.201.20:17:57.36#ibcon#read 6, iclass 30, count 2 2006.201.20:17:57.36#ibcon#end of sib2, iclass 30, count 2 2006.201.20:17:57.36#ibcon#*after write, iclass 30, count 2 2006.201.20:17:57.36#ibcon#*before return 0, iclass 30, count 2 2006.201.20:17:57.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:57.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:17:57.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.20:17:57.36#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:57.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:57.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:57.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:57.48#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:17:57.48#ibcon#first serial, iclass 30, count 0 2006.201.20:17:57.48#ibcon#enter sib2, iclass 30, count 0 2006.201.20:17:57.48#ibcon#flushed, iclass 30, count 0 2006.201.20:17:57.48#ibcon#about to write, iclass 30, count 0 2006.201.20:17:57.48#ibcon#wrote, iclass 30, count 0 2006.201.20:17:57.48#ibcon#about to read 3, iclass 30, count 0 2006.201.20:17:57.50#ibcon#read 3, iclass 30, count 0 2006.201.20:17:57.50#ibcon#about to read 4, iclass 30, count 0 2006.201.20:17:57.50#ibcon#read 4, iclass 30, count 0 2006.201.20:17:57.50#ibcon#about to read 5, iclass 30, count 0 2006.201.20:17:57.50#ibcon#read 5, iclass 30, count 0 2006.201.20:17:57.50#ibcon#about to read 6, iclass 30, count 0 2006.201.20:17:57.50#ibcon#read 6, iclass 30, count 0 2006.201.20:17:57.50#ibcon#end of sib2, iclass 30, count 0 2006.201.20:17:57.50#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:17:57.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:17:57.50#ibcon#[27=USB\r\n] 2006.201.20:17:57.50#ibcon#*before write, iclass 30, count 0 2006.201.20:17:57.50#ibcon#enter sib2, iclass 30, count 0 2006.201.20:17:57.50#ibcon#flushed, iclass 30, count 0 2006.201.20:17:57.50#ibcon#about to write, iclass 30, count 0 2006.201.20:17:57.50#ibcon#wrote, iclass 30, count 0 2006.201.20:17:57.50#ibcon#about to read 3, iclass 30, count 0 2006.201.20:17:57.53#ibcon#read 3, iclass 30, count 0 2006.201.20:17:57.53#ibcon#about to read 4, iclass 30, count 0 2006.201.20:17:57.53#ibcon#read 4, iclass 30, count 0 2006.201.20:17:57.53#ibcon#about to read 5, iclass 30, count 0 2006.201.20:17:57.53#ibcon#read 5, iclass 30, count 0 2006.201.20:17:57.53#ibcon#about to read 6, iclass 30, count 0 2006.201.20:17:57.53#ibcon#read 6, iclass 30, count 0 2006.201.20:17:57.53#ibcon#end of sib2, iclass 30, count 0 2006.201.20:17:57.53#ibcon#*after write, iclass 30, count 0 2006.201.20:17:57.53#ibcon#*before return 0, iclass 30, count 0 2006.201.20:17:57.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:57.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:17:57.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:17:57.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:17:57.53$vck44/vblo=4,679.99 2006.201.20:17:57.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.20:17:57.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.20:17:57.53#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:57.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:57.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:57.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:57.53#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:17:57.53#ibcon#first serial, iclass 32, count 0 2006.201.20:17:57.53#ibcon#enter sib2, iclass 32, count 0 2006.201.20:17:57.53#ibcon#flushed, iclass 32, count 0 2006.201.20:17:57.53#ibcon#about to write, iclass 32, count 0 2006.201.20:17:57.53#ibcon#wrote, iclass 32, count 0 2006.201.20:17:57.53#ibcon#about to read 3, iclass 32, count 0 2006.201.20:17:57.55#ibcon#read 3, iclass 32, count 0 2006.201.20:17:57.55#ibcon#about to read 4, iclass 32, count 0 2006.201.20:17:57.55#ibcon#read 4, iclass 32, count 0 2006.201.20:17:57.55#ibcon#about to read 5, iclass 32, count 0 2006.201.20:17:57.55#ibcon#read 5, iclass 32, count 0 2006.201.20:17:57.55#ibcon#about to read 6, iclass 32, count 0 2006.201.20:17:57.55#ibcon#read 6, iclass 32, count 0 2006.201.20:17:57.55#ibcon#end of sib2, iclass 32, count 0 2006.201.20:17:57.55#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:17:57.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:17:57.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:17:57.55#ibcon#*before write, iclass 32, count 0 2006.201.20:17:57.55#ibcon#enter sib2, iclass 32, count 0 2006.201.20:17:57.55#ibcon#flushed, iclass 32, count 0 2006.201.20:17:57.55#ibcon#about to write, iclass 32, count 0 2006.201.20:17:57.55#ibcon#wrote, iclass 32, count 0 2006.201.20:17:57.55#ibcon#about to read 3, iclass 32, count 0 2006.201.20:17:57.59#ibcon#read 3, iclass 32, count 0 2006.201.20:17:57.59#ibcon#about to read 4, iclass 32, count 0 2006.201.20:17:57.59#ibcon#read 4, iclass 32, count 0 2006.201.20:17:57.59#ibcon#about to read 5, iclass 32, count 0 2006.201.20:17:57.59#ibcon#read 5, iclass 32, count 0 2006.201.20:17:57.59#ibcon#about to read 6, iclass 32, count 0 2006.201.20:17:57.59#ibcon#read 6, iclass 32, count 0 2006.201.20:17:57.59#ibcon#end of sib2, iclass 32, count 0 2006.201.20:17:57.59#ibcon#*after write, iclass 32, count 0 2006.201.20:17:57.59#ibcon#*before return 0, iclass 32, count 0 2006.201.20:17:57.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:57.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:17:57.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:17:57.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:17:57.59$vck44/vb=4,5 2006.201.20:17:57.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.20:17:57.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.20:17:57.59#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:57.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:57.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:57.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:57.65#ibcon#enter wrdev, iclass 34, count 2 2006.201.20:17:57.65#ibcon#first serial, iclass 34, count 2 2006.201.20:17:57.65#ibcon#enter sib2, iclass 34, count 2 2006.201.20:17:57.65#ibcon#flushed, iclass 34, count 2 2006.201.20:17:57.65#ibcon#about to write, iclass 34, count 2 2006.201.20:17:57.65#ibcon#wrote, iclass 34, count 2 2006.201.20:17:57.65#ibcon#about to read 3, iclass 34, count 2 2006.201.20:17:57.67#ibcon#read 3, iclass 34, count 2 2006.201.20:17:57.67#ibcon#about to read 4, iclass 34, count 2 2006.201.20:17:57.67#ibcon#read 4, iclass 34, count 2 2006.201.20:17:57.67#ibcon#about to read 5, iclass 34, count 2 2006.201.20:17:57.67#ibcon#read 5, iclass 34, count 2 2006.201.20:17:57.67#ibcon#about to read 6, iclass 34, count 2 2006.201.20:17:57.67#ibcon#read 6, iclass 34, count 2 2006.201.20:17:57.67#ibcon#end of sib2, iclass 34, count 2 2006.201.20:17:57.67#ibcon#*mode == 0, iclass 34, count 2 2006.201.20:17:57.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.20:17:57.67#ibcon#[27=AT04-05\r\n] 2006.201.20:17:57.67#ibcon#*before write, iclass 34, count 2 2006.201.20:17:57.67#ibcon#enter sib2, iclass 34, count 2 2006.201.20:17:57.67#ibcon#flushed, iclass 34, count 2 2006.201.20:17:57.67#ibcon#about to write, iclass 34, count 2 2006.201.20:17:57.67#ibcon#wrote, iclass 34, count 2 2006.201.20:17:57.67#ibcon#about to read 3, iclass 34, count 2 2006.201.20:17:57.70#ibcon#read 3, iclass 34, count 2 2006.201.20:17:57.70#ibcon#about to read 4, iclass 34, count 2 2006.201.20:17:57.70#ibcon#read 4, iclass 34, count 2 2006.201.20:17:57.70#ibcon#about to read 5, iclass 34, count 2 2006.201.20:17:57.70#ibcon#read 5, iclass 34, count 2 2006.201.20:17:57.70#ibcon#about to read 6, iclass 34, count 2 2006.201.20:17:57.70#ibcon#read 6, iclass 34, count 2 2006.201.20:17:57.70#ibcon#end of sib2, iclass 34, count 2 2006.201.20:17:57.70#ibcon#*after write, iclass 34, count 2 2006.201.20:17:57.70#ibcon#*before return 0, iclass 34, count 2 2006.201.20:17:57.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:57.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:17:57.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.20:17:57.70#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:57.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:57.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:57.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:57.82#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:17:57.82#ibcon#first serial, iclass 34, count 0 2006.201.20:17:57.82#ibcon#enter sib2, iclass 34, count 0 2006.201.20:17:57.82#ibcon#flushed, iclass 34, count 0 2006.201.20:17:57.82#ibcon#about to write, iclass 34, count 0 2006.201.20:17:57.82#ibcon#wrote, iclass 34, count 0 2006.201.20:17:57.82#ibcon#about to read 3, iclass 34, count 0 2006.201.20:17:57.84#ibcon#read 3, iclass 34, count 0 2006.201.20:17:57.84#ibcon#about to read 4, iclass 34, count 0 2006.201.20:17:57.84#ibcon#read 4, iclass 34, count 0 2006.201.20:17:57.84#ibcon#about to read 5, iclass 34, count 0 2006.201.20:17:57.84#ibcon#read 5, iclass 34, count 0 2006.201.20:17:57.84#ibcon#about to read 6, iclass 34, count 0 2006.201.20:17:57.84#ibcon#read 6, iclass 34, count 0 2006.201.20:17:57.84#ibcon#end of sib2, iclass 34, count 0 2006.201.20:17:57.84#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:17:57.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:17:57.84#ibcon#[27=USB\r\n] 2006.201.20:17:57.84#ibcon#*before write, iclass 34, count 0 2006.201.20:17:57.84#ibcon#enter sib2, iclass 34, count 0 2006.201.20:17:57.84#ibcon#flushed, iclass 34, count 0 2006.201.20:17:57.84#ibcon#about to write, iclass 34, count 0 2006.201.20:17:57.84#ibcon#wrote, iclass 34, count 0 2006.201.20:17:57.84#ibcon#about to read 3, iclass 34, count 0 2006.201.20:17:57.87#ibcon#read 3, iclass 34, count 0 2006.201.20:17:57.87#ibcon#about to read 4, iclass 34, count 0 2006.201.20:17:57.87#ibcon#read 4, iclass 34, count 0 2006.201.20:17:57.87#ibcon#about to read 5, iclass 34, count 0 2006.201.20:17:57.87#ibcon#read 5, iclass 34, count 0 2006.201.20:17:57.87#ibcon#about to read 6, iclass 34, count 0 2006.201.20:17:57.87#ibcon#read 6, iclass 34, count 0 2006.201.20:17:57.87#ibcon#end of sib2, iclass 34, count 0 2006.201.20:17:57.87#ibcon#*after write, iclass 34, count 0 2006.201.20:17:57.87#ibcon#*before return 0, iclass 34, count 0 2006.201.20:17:57.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:57.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:17:57.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:17:57.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:17:57.87$vck44/vblo=5,709.99 2006.201.20:17:57.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.20:17:57.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.20:17:57.87#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:57.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:57.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:57.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:57.87#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:17:57.87#ibcon#first serial, iclass 36, count 0 2006.201.20:17:57.87#ibcon#enter sib2, iclass 36, count 0 2006.201.20:17:57.87#ibcon#flushed, iclass 36, count 0 2006.201.20:17:57.87#ibcon#about to write, iclass 36, count 0 2006.201.20:17:57.87#ibcon#wrote, iclass 36, count 0 2006.201.20:17:57.87#ibcon#about to read 3, iclass 36, count 0 2006.201.20:17:57.89#ibcon#read 3, iclass 36, count 0 2006.201.20:17:57.89#ibcon#about to read 4, iclass 36, count 0 2006.201.20:17:57.89#ibcon#read 4, iclass 36, count 0 2006.201.20:17:57.89#ibcon#about to read 5, iclass 36, count 0 2006.201.20:17:57.89#ibcon#read 5, iclass 36, count 0 2006.201.20:17:57.89#ibcon#about to read 6, iclass 36, count 0 2006.201.20:17:57.89#ibcon#read 6, iclass 36, count 0 2006.201.20:17:57.89#ibcon#end of sib2, iclass 36, count 0 2006.201.20:17:57.89#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:17:57.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:17:57.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:17:57.89#ibcon#*before write, iclass 36, count 0 2006.201.20:17:57.89#ibcon#enter sib2, iclass 36, count 0 2006.201.20:17:57.89#ibcon#flushed, iclass 36, count 0 2006.201.20:17:57.89#ibcon#about to write, iclass 36, count 0 2006.201.20:17:57.89#ibcon#wrote, iclass 36, count 0 2006.201.20:17:57.89#ibcon#about to read 3, iclass 36, count 0 2006.201.20:17:57.94#ibcon#read 3, iclass 36, count 0 2006.201.20:17:57.94#ibcon#about to read 4, iclass 36, count 0 2006.201.20:17:57.94#ibcon#read 4, iclass 36, count 0 2006.201.20:17:57.94#ibcon#about to read 5, iclass 36, count 0 2006.201.20:17:57.94#ibcon#read 5, iclass 36, count 0 2006.201.20:17:57.94#ibcon#about to read 6, iclass 36, count 0 2006.201.20:17:57.94#ibcon#read 6, iclass 36, count 0 2006.201.20:17:57.94#ibcon#end of sib2, iclass 36, count 0 2006.201.20:17:57.94#ibcon#*after write, iclass 36, count 0 2006.201.20:17:57.94#ibcon#*before return 0, iclass 36, count 0 2006.201.20:17:57.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:57.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:17:57.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:17:57.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:17:57.94$vck44/vb=5,4 2006.201.20:17:57.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.20:17:57.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.20:17:57.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:57.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:57.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:57.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:57.99#ibcon#enter wrdev, iclass 38, count 2 2006.201.20:17:57.99#ibcon#first serial, iclass 38, count 2 2006.201.20:17:57.99#ibcon#enter sib2, iclass 38, count 2 2006.201.20:17:57.99#ibcon#flushed, iclass 38, count 2 2006.201.20:17:57.99#ibcon#about to write, iclass 38, count 2 2006.201.20:17:57.99#ibcon#wrote, iclass 38, count 2 2006.201.20:17:57.99#ibcon#about to read 3, iclass 38, count 2 2006.201.20:17:58.01#ibcon#read 3, iclass 38, count 2 2006.201.20:17:58.01#ibcon#about to read 4, iclass 38, count 2 2006.201.20:17:58.01#ibcon#read 4, iclass 38, count 2 2006.201.20:17:58.01#ibcon#about to read 5, iclass 38, count 2 2006.201.20:17:58.01#ibcon#read 5, iclass 38, count 2 2006.201.20:17:58.01#ibcon#about to read 6, iclass 38, count 2 2006.201.20:17:58.01#ibcon#read 6, iclass 38, count 2 2006.201.20:17:58.01#ibcon#end of sib2, iclass 38, count 2 2006.201.20:17:58.01#ibcon#*mode == 0, iclass 38, count 2 2006.201.20:17:58.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.20:17:58.01#ibcon#[27=AT05-04\r\n] 2006.201.20:17:58.01#ibcon#*before write, iclass 38, count 2 2006.201.20:17:58.01#ibcon#enter sib2, iclass 38, count 2 2006.201.20:17:58.01#ibcon#flushed, iclass 38, count 2 2006.201.20:17:58.01#ibcon#about to write, iclass 38, count 2 2006.201.20:17:58.01#ibcon#wrote, iclass 38, count 2 2006.201.20:17:58.01#ibcon#about to read 3, iclass 38, count 2 2006.201.20:17:58.04#ibcon#read 3, iclass 38, count 2 2006.201.20:17:58.04#ibcon#about to read 4, iclass 38, count 2 2006.201.20:17:58.04#ibcon#read 4, iclass 38, count 2 2006.201.20:17:58.04#ibcon#about to read 5, iclass 38, count 2 2006.201.20:17:58.04#ibcon#read 5, iclass 38, count 2 2006.201.20:17:58.04#ibcon#about to read 6, iclass 38, count 2 2006.201.20:17:58.04#ibcon#read 6, iclass 38, count 2 2006.201.20:17:58.04#ibcon#end of sib2, iclass 38, count 2 2006.201.20:17:58.04#ibcon#*after write, iclass 38, count 2 2006.201.20:17:58.04#ibcon#*before return 0, iclass 38, count 2 2006.201.20:17:58.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:58.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:17:58.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.20:17:58.04#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:58.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:58.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:58.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:58.16#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:17:58.16#ibcon#first serial, iclass 38, count 0 2006.201.20:17:58.16#ibcon#enter sib2, iclass 38, count 0 2006.201.20:17:58.16#ibcon#flushed, iclass 38, count 0 2006.201.20:17:58.16#ibcon#about to write, iclass 38, count 0 2006.201.20:17:58.16#ibcon#wrote, iclass 38, count 0 2006.201.20:17:58.16#ibcon#about to read 3, iclass 38, count 0 2006.201.20:17:58.18#ibcon#read 3, iclass 38, count 0 2006.201.20:17:58.18#ibcon#about to read 4, iclass 38, count 0 2006.201.20:17:58.18#ibcon#read 4, iclass 38, count 0 2006.201.20:17:58.18#ibcon#about to read 5, iclass 38, count 0 2006.201.20:17:58.18#ibcon#read 5, iclass 38, count 0 2006.201.20:17:58.18#ibcon#about to read 6, iclass 38, count 0 2006.201.20:17:58.18#ibcon#read 6, iclass 38, count 0 2006.201.20:17:58.18#ibcon#end of sib2, iclass 38, count 0 2006.201.20:17:58.18#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:17:58.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:17:58.18#ibcon#[27=USB\r\n] 2006.201.20:17:58.18#ibcon#*before write, iclass 38, count 0 2006.201.20:17:58.18#ibcon#enter sib2, iclass 38, count 0 2006.201.20:17:58.18#ibcon#flushed, iclass 38, count 0 2006.201.20:17:58.18#ibcon#about to write, iclass 38, count 0 2006.201.20:17:58.18#ibcon#wrote, iclass 38, count 0 2006.201.20:17:58.18#ibcon#about to read 3, iclass 38, count 0 2006.201.20:17:58.21#ibcon#read 3, iclass 38, count 0 2006.201.20:17:58.21#ibcon#about to read 4, iclass 38, count 0 2006.201.20:17:58.21#ibcon#read 4, iclass 38, count 0 2006.201.20:17:58.21#ibcon#about to read 5, iclass 38, count 0 2006.201.20:17:58.21#ibcon#read 5, iclass 38, count 0 2006.201.20:17:58.21#ibcon#about to read 6, iclass 38, count 0 2006.201.20:17:58.21#ibcon#read 6, iclass 38, count 0 2006.201.20:17:58.21#ibcon#end of sib2, iclass 38, count 0 2006.201.20:17:58.21#ibcon#*after write, iclass 38, count 0 2006.201.20:17:58.21#ibcon#*before return 0, iclass 38, count 0 2006.201.20:17:58.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:58.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:17:58.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:17:58.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:17:58.21$vck44/vblo=6,719.99 2006.201.20:17:58.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.20:17:58.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.20:17:58.21#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:58.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:58.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:58.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:58.21#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:17:58.21#ibcon#first serial, iclass 40, count 0 2006.201.20:17:58.21#ibcon#enter sib2, iclass 40, count 0 2006.201.20:17:58.21#ibcon#flushed, iclass 40, count 0 2006.201.20:17:58.21#ibcon#about to write, iclass 40, count 0 2006.201.20:17:58.21#ibcon#wrote, iclass 40, count 0 2006.201.20:17:58.21#ibcon#about to read 3, iclass 40, count 0 2006.201.20:17:58.23#ibcon#read 3, iclass 40, count 0 2006.201.20:17:58.23#ibcon#about to read 4, iclass 40, count 0 2006.201.20:17:58.23#ibcon#read 4, iclass 40, count 0 2006.201.20:17:58.23#ibcon#about to read 5, iclass 40, count 0 2006.201.20:17:58.23#ibcon#read 5, iclass 40, count 0 2006.201.20:17:58.23#ibcon#about to read 6, iclass 40, count 0 2006.201.20:17:58.23#ibcon#read 6, iclass 40, count 0 2006.201.20:17:58.23#ibcon#end of sib2, iclass 40, count 0 2006.201.20:17:58.23#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:17:58.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:17:58.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:17:58.23#ibcon#*before write, iclass 40, count 0 2006.201.20:17:58.23#ibcon#enter sib2, iclass 40, count 0 2006.201.20:17:58.23#ibcon#flushed, iclass 40, count 0 2006.201.20:17:58.23#ibcon#about to write, iclass 40, count 0 2006.201.20:17:58.23#ibcon#wrote, iclass 40, count 0 2006.201.20:17:58.23#ibcon#about to read 3, iclass 40, count 0 2006.201.20:17:58.27#ibcon#read 3, iclass 40, count 0 2006.201.20:17:58.27#ibcon#about to read 4, iclass 40, count 0 2006.201.20:17:58.27#ibcon#read 4, iclass 40, count 0 2006.201.20:17:58.27#ibcon#about to read 5, iclass 40, count 0 2006.201.20:17:58.27#ibcon#read 5, iclass 40, count 0 2006.201.20:17:58.27#ibcon#about to read 6, iclass 40, count 0 2006.201.20:17:58.27#ibcon#read 6, iclass 40, count 0 2006.201.20:17:58.27#ibcon#end of sib2, iclass 40, count 0 2006.201.20:17:58.27#ibcon#*after write, iclass 40, count 0 2006.201.20:17:58.27#ibcon#*before return 0, iclass 40, count 0 2006.201.20:17:58.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:58.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:17:58.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:17:58.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:17:58.27$vck44/vb=6,4 2006.201.20:17:58.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.20:17:58.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.20:17:58.27#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:58.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:58.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:58.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:58.33#ibcon#enter wrdev, iclass 4, count 2 2006.201.20:17:58.33#ibcon#first serial, iclass 4, count 2 2006.201.20:17:58.33#ibcon#enter sib2, iclass 4, count 2 2006.201.20:17:58.33#ibcon#flushed, iclass 4, count 2 2006.201.20:17:58.33#ibcon#about to write, iclass 4, count 2 2006.201.20:17:58.33#ibcon#wrote, iclass 4, count 2 2006.201.20:17:58.33#ibcon#about to read 3, iclass 4, count 2 2006.201.20:17:58.35#ibcon#read 3, iclass 4, count 2 2006.201.20:17:58.35#ibcon#about to read 4, iclass 4, count 2 2006.201.20:17:58.35#ibcon#read 4, iclass 4, count 2 2006.201.20:17:58.35#ibcon#about to read 5, iclass 4, count 2 2006.201.20:17:58.35#ibcon#read 5, iclass 4, count 2 2006.201.20:17:58.35#ibcon#about to read 6, iclass 4, count 2 2006.201.20:17:58.35#ibcon#read 6, iclass 4, count 2 2006.201.20:17:58.35#ibcon#end of sib2, iclass 4, count 2 2006.201.20:17:58.35#ibcon#*mode == 0, iclass 4, count 2 2006.201.20:17:58.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.20:17:58.35#ibcon#[27=AT06-04\r\n] 2006.201.20:17:58.35#ibcon#*before write, iclass 4, count 2 2006.201.20:17:58.35#ibcon#enter sib2, iclass 4, count 2 2006.201.20:17:58.35#ibcon#flushed, iclass 4, count 2 2006.201.20:17:58.35#ibcon#about to write, iclass 4, count 2 2006.201.20:17:58.35#ibcon#wrote, iclass 4, count 2 2006.201.20:17:58.35#ibcon#about to read 3, iclass 4, count 2 2006.201.20:17:58.38#ibcon#read 3, iclass 4, count 2 2006.201.20:17:58.38#ibcon#about to read 4, iclass 4, count 2 2006.201.20:17:58.38#ibcon#read 4, iclass 4, count 2 2006.201.20:17:58.38#ibcon#about to read 5, iclass 4, count 2 2006.201.20:17:58.38#ibcon#read 5, iclass 4, count 2 2006.201.20:17:58.38#ibcon#about to read 6, iclass 4, count 2 2006.201.20:17:58.38#ibcon#read 6, iclass 4, count 2 2006.201.20:17:58.38#ibcon#end of sib2, iclass 4, count 2 2006.201.20:17:58.38#ibcon#*after write, iclass 4, count 2 2006.201.20:17:58.38#ibcon#*before return 0, iclass 4, count 2 2006.201.20:17:58.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:58.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:17:58.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.20:17:58.38#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:58.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:58.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:58.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:58.50#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:17:58.50#ibcon#first serial, iclass 4, count 0 2006.201.20:17:58.50#ibcon#enter sib2, iclass 4, count 0 2006.201.20:17:58.50#ibcon#flushed, iclass 4, count 0 2006.201.20:17:58.50#ibcon#about to write, iclass 4, count 0 2006.201.20:17:58.50#ibcon#wrote, iclass 4, count 0 2006.201.20:17:58.50#ibcon#about to read 3, iclass 4, count 0 2006.201.20:17:58.52#ibcon#read 3, iclass 4, count 0 2006.201.20:17:58.52#ibcon#about to read 4, iclass 4, count 0 2006.201.20:17:58.52#ibcon#read 4, iclass 4, count 0 2006.201.20:17:58.52#ibcon#about to read 5, iclass 4, count 0 2006.201.20:17:58.52#ibcon#read 5, iclass 4, count 0 2006.201.20:17:58.52#ibcon#about to read 6, iclass 4, count 0 2006.201.20:17:58.52#ibcon#read 6, iclass 4, count 0 2006.201.20:17:58.52#ibcon#end of sib2, iclass 4, count 0 2006.201.20:17:58.52#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:17:58.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:17:58.52#ibcon#[27=USB\r\n] 2006.201.20:17:58.52#ibcon#*before write, iclass 4, count 0 2006.201.20:17:58.52#ibcon#enter sib2, iclass 4, count 0 2006.201.20:17:58.52#ibcon#flushed, iclass 4, count 0 2006.201.20:17:58.52#ibcon#about to write, iclass 4, count 0 2006.201.20:17:58.52#ibcon#wrote, iclass 4, count 0 2006.201.20:17:58.52#ibcon#about to read 3, iclass 4, count 0 2006.201.20:17:58.55#ibcon#read 3, iclass 4, count 0 2006.201.20:17:58.55#ibcon#about to read 4, iclass 4, count 0 2006.201.20:17:58.55#ibcon#read 4, iclass 4, count 0 2006.201.20:17:58.55#ibcon#about to read 5, iclass 4, count 0 2006.201.20:17:58.55#ibcon#read 5, iclass 4, count 0 2006.201.20:17:58.55#ibcon#about to read 6, iclass 4, count 0 2006.201.20:17:58.55#ibcon#read 6, iclass 4, count 0 2006.201.20:17:58.55#ibcon#end of sib2, iclass 4, count 0 2006.201.20:17:58.55#ibcon#*after write, iclass 4, count 0 2006.201.20:17:58.55#ibcon#*before return 0, iclass 4, count 0 2006.201.20:17:58.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:58.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:17:58.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:17:58.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:17:58.55$vck44/vblo=7,734.99 2006.201.20:17:58.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.20:17:58.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.20:17:58.55#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:58.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:58.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:58.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:58.55#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:17:58.55#ibcon#first serial, iclass 6, count 0 2006.201.20:17:58.55#ibcon#enter sib2, iclass 6, count 0 2006.201.20:17:58.55#ibcon#flushed, iclass 6, count 0 2006.201.20:17:58.55#ibcon#about to write, iclass 6, count 0 2006.201.20:17:58.55#ibcon#wrote, iclass 6, count 0 2006.201.20:17:58.55#ibcon#about to read 3, iclass 6, count 0 2006.201.20:17:58.57#ibcon#read 3, iclass 6, count 0 2006.201.20:17:58.57#ibcon#about to read 4, iclass 6, count 0 2006.201.20:17:58.57#ibcon#read 4, iclass 6, count 0 2006.201.20:17:58.57#ibcon#about to read 5, iclass 6, count 0 2006.201.20:17:58.57#ibcon#read 5, iclass 6, count 0 2006.201.20:17:58.57#ibcon#about to read 6, iclass 6, count 0 2006.201.20:17:58.57#ibcon#read 6, iclass 6, count 0 2006.201.20:17:58.57#ibcon#end of sib2, iclass 6, count 0 2006.201.20:17:58.57#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:17:58.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:17:58.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:17:58.57#ibcon#*before write, iclass 6, count 0 2006.201.20:17:58.57#ibcon#enter sib2, iclass 6, count 0 2006.201.20:17:58.57#ibcon#flushed, iclass 6, count 0 2006.201.20:17:58.57#ibcon#about to write, iclass 6, count 0 2006.201.20:17:58.57#ibcon#wrote, iclass 6, count 0 2006.201.20:17:58.57#ibcon#about to read 3, iclass 6, count 0 2006.201.20:17:58.61#ibcon#read 3, iclass 6, count 0 2006.201.20:17:58.61#ibcon#about to read 4, iclass 6, count 0 2006.201.20:17:58.61#ibcon#read 4, iclass 6, count 0 2006.201.20:17:58.61#ibcon#about to read 5, iclass 6, count 0 2006.201.20:17:58.61#ibcon#read 5, iclass 6, count 0 2006.201.20:17:58.61#ibcon#about to read 6, iclass 6, count 0 2006.201.20:17:58.61#ibcon#read 6, iclass 6, count 0 2006.201.20:17:58.61#ibcon#end of sib2, iclass 6, count 0 2006.201.20:17:58.61#ibcon#*after write, iclass 6, count 0 2006.201.20:17:58.61#ibcon#*before return 0, iclass 6, count 0 2006.201.20:17:58.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:58.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:17:58.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:17:58.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:17:58.61$vck44/vb=7,4 2006.201.20:17:58.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.20:17:58.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.20:17:58.61#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:58.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:58.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:58.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:58.67#ibcon#enter wrdev, iclass 10, count 2 2006.201.20:17:58.67#ibcon#first serial, iclass 10, count 2 2006.201.20:17:58.67#ibcon#enter sib2, iclass 10, count 2 2006.201.20:17:58.67#ibcon#flushed, iclass 10, count 2 2006.201.20:17:58.67#ibcon#about to write, iclass 10, count 2 2006.201.20:17:58.67#ibcon#wrote, iclass 10, count 2 2006.201.20:17:58.67#ibcon#about to read 3, iclass 10, count 2 2006.201.20:17:58.69#ibcon#read 3, iclass 10, count 2 2006.201.20:17:58.69#ibcon#about to read 4, iclass 10, count 2 2006.201.20:17:58.69#ibcon#read 4, iclass 10, count 2 2006.201.20:17:58.69#ibcon#about to read 5, iclass 10, count 2 2006.201.20:17:58.69#ibcon#read 5, iclass 10, count 2 2006.201.20:17:58.69#ibcon#about to read 6, iclass 10, count 2 2006.201.20:17:58.69#ibcon#read 6, iclass 10, count 2 2006.201.20:17:58.69#ibcon#end of sib2, iclass 10, count 2 2006.201.20:17:58.69#ibcon#*mode == 0, iclass 10, count 2 2006.201.20:17:58.69#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.20:17:58.69#ibcon#[27=AT07-04\r\n] 2006.201.20:17:58.69#ibcon#*before write, iclass 10, count 2 2006.201.20:17:58.69#ibcon#enter sib2, iclass 10, count 2 2006.201.20:17:58.69#ibcon#flushed, iclass 10, count 2 2006.201.20:17:58.69#ibcon#about to write, iclass 10, count 2 2006.201.20:17:58.69#ibcon#wrote, iclass 10, count 2 2006.201.20:17:58.69#ibcon#about to read 3, iclass 10, count 2 2006.201.20:17:58.72#ibcon#read 3, iclass 10, count 2 2006.201.20:17:58.72#ibcon#about to read 4, iclass 10, count 2 2006.201.20:17:58.72#ibcon#read 4, iclass 10, count 2 2006.201.20:17:58.72#ibcon#about to read 5, iclass 10, count 2 2006.201.20:17:58.72#ibcon#read 5, iclass 10, count 2 2006.201.20:17:58.72#ibcon#about to read 6, iclass 10, count 2 2006.201.20:17:58.72#ibcon#read 6, iclass 10, count 2 2006.201.20:17:58.72#ibcon#end of sib2, iclass 10, count 2 2006.201.20:17:58.72#ibcon#*after write, iclass 10, count 2 2006.201.20:17:58.72#ibcon#*before return 0, iclass 10, count 2 2006.201.20:17:58.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:58.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:17:58.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.20:17:58.72#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:58.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:58.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:58.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:58.84#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:17:58.84#ibcon#first serial, iclass 10, count 0 2006.201.20:17:58.84#ibcon#enter sib2, iclass 10, count 0 2006.201.20:17:58.84#ibcon#flushed, iclass 10, count 0 2006.201.20:17:58.84#ibcon#about to write, iclass 10, count 0 2006.201.20:17:58.84#ibcon#wrote, iclass 10, count 0 2006.201.20:17:58.84#ibcon#about to read 3, iclass 10, count 0 2006.201.20:17:58.86#ibcon#read 3, iclass 10, count 0 2006.201.20:17:58.86#ibcon#about to read 4, iclass 10, count 0 2006.201.20:17:58.86#ibcon#read 4, iclass 10, count 0 2006.201.20:17:58.86#ibcon#about to read 5, iclass 10, count 0 2006.201.20:17:58.86#ibcon#read 5, iclass 10, count 0 2006.201.20:17:58.86#ibcon#about to read 6, iclass 10, count 0 2006.201.20:17:58.86#ibcon#read 6, iclass 10, count 0 2006.201.20:17:58.86#ibcon#end of sib2, iclass 10, count 0 2006.201.20:17:58.86#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:17:58.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:17:58.86#ibcon#[27=USB\r\n] 2006.201.20:17:58.86#ibcon#*before write, iclass 10, count 0 2006.201.20:17:58.86#ibcon#enter sib2, iclass 10, count 0 2006.201.20:17:58.86#ibcon#flushed, iclass 10, count 0 2006.201.20:17:58.86#ibcon#about to write, iclass 10, count 0 2006.201.20:17:58.86#ibcon#wrote, iclass 10, count 0 2006.201.20:17:58.86#ibcon#about to read 3, iclass 10, count 0 2006.201.20:17:58.89#ibcon#read 3, iclass 10, count 0 2006.201.20:17:58.89#ibcon#about to read 4, iclass 10, count 0 2006.201.20:17:58.89#ibcon#read 4, iclass 10, count 0 2006.201.20:17:58.89#ibcon#about to read 5, iclass 10, count 0 2006.201.20:17:58.89#ibcon#read 5, iclass 10, count 0 2006.201.20:17:58.89#ibcon#about to read 6, iclass 10, count 0 2006.201.20:17:58.89#ibcon#read 6, iclass 10, count 0 2006.201.20:17:58.89#ibcon#end of sib2, iclass 10, count 0 2006.201.20:17:58.89#ibcon#*after write, iclass 10, count 0 2006.201.20:17:58.89#ibcon#*before return 0, iclass 10, count 0 2006.201.20:17:58.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:58.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:17:58.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:17:58.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:17:58.89$vck44/vblo=8,744.99 2006.201.20:17:58.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.20:17:58.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.20:17:58.89#ibcon#ireg 17 cls_cnt 0 2006.201.20:17:58.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:58.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:58.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:58.89#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:17:58.89#ibcon#first serial, iclass 12, count 0 2006.201.20:17:58.89#ibcon#enter sib2, iclass 12, count 0 2006.201.20:17:58.89#ibcon#flushed, iclass 12, count 0 2006.201.20:17:58.89#ibcon#about to write, iclass 12, count 0 2006.201.20:17:58.89#ibcon#wrote, iclass 12, count 0 2006.201.20:17:58.89#ibcon#about to read 3, iclass 12, count 0 2006.201.20:17:58.91#ibcon#read 3, iclass 12, count 0 2006.201.20:17:58.91#ibcon#about to read 4, iclass 12, count 0 2006.201.20:17:58.91#ibcon#read 4, iclass 12, count 0 2006.201.20:17:58.91#ibcon#about to read 5, iclass 12, count 0 2006.201.20:17:58.91#ibcon#read 5, iclass 12, count 0 2006.201.20:17:58.91#ibcon#about to read 6, iclass 12, count 0 2006.201.20:17:58.91#ibcon#read 6, iclass 12, count 0 2006.201.20:17:58.91#ibcon#end of sib2, iclass 12, count 0 2006.201.20:17:58.91#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:17:58.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:17:58.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:17:58.91#ibcon#*before write, iclass 12, count 0 2006.201.20:17:58.91#ibcon#enter sib2, iclass 12, count 0 2006.201.20:17:58.91#ibcon#flushed, iclass 12, count 0 2006.201.20:17:58.91#ibcon#about to write, iclass 12, count 0 2006.201.20:17:58.91#ibcon#wrote, iclass 12, count 0 2006.201.20:17:58.91#ibcon#about to read 3, iclass 12, count 0 2006.201.20:17:58.95#ibcon#read 3, iclass 12, count 0 2006.201.20:17:58.95#ibcon#about to read 4, iclass 12, count 0 2006.201.20:17:58.95#ibcon#read 4, iclass 12, count 0 2006.201.20:17:58.95#ibcon#about to read 5, iclass 12, count 0 2006.201.20:17:58.95#ibcon#read 5, iclass 12, count 0 2006.201.20:17:58.95#ibcon#about to read 6, iclass 12, count 0 2006.201.20:17:58.95#ibcon#read 6, iclass 12, count 0 2006.201.20:17:58.95#ibcon#end of sib2, iclass 12, count 0 2006.201.20:17:58.95#ibcon#*after write, iclass 12, count 0 2006.201.20:17:58.95#ibcon#*before return 0, iclass 12, count 0 2006.201.20:17:58.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:58.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:17:58.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:17:58.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:17:58.95$vck44/vb=8,4 2006.201.20:17:58.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.20:17:58.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.20:17:58.95#ibcon#ireg 11 cls_cnt 2 2006.201.20:17:58.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:59.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:59.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:59.01#ibcon#enter wrdev, iclass 14, count 2 2006.201.20:17:59.01#ibcon#first serial, iclass 14, count 2 2006.201.20:17:59.01#ibcon#enter sib2, iclass 14, count 2 2006.201.20:17:59.01#ibcon#flushed, iclass 14, count 2 2006.201.20:17:59.01#ibcon#about to write, iclass 14, count 2 2006.201.20:17:59.01#ibcon#wrote, iclass 14, count 2 2006.201.20:17:59.01#ibcon#about to read 3, iclass 14, count 2 2006.201.20:17:59.03#ibcon#read 3, iclass 14, count 2 2006.201.20:17:59.03#ibcon#about to read 4, iclass 14, count 2 2006.201.20:17:59.03#ibcon#read 4, iclass 14, count 2 2006.201.20:17:59.03#ibcon#about to read 5, iclass 14, count 2 2006.201.20:17:59.03#ibcon#read 5, iclass 14, count 2 2006.201.20:17:59.03#ibcon#about to read 6, iclass 14, count 2 2006.201.20:17:59.03#ibcon#read 6, iclass 14, count 2 2006.201.20:17:59.03#ibcon#end of sib2, iclass 14, count 2 2006.201.20:17:59.03#ibcon#*mode == 0, iclass 14, count 2 2006.201.20:17:59.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.20:17:59.03#ibcon#[27=AT08-04\r\n] 2006.201.20:17:59.03#ibcon#*before write, iclass 14, count 2 2006.201.20:17:59.03#ibcon#enter sib2, iclass 14, count 2 2006.201.20:17:59.03#ibcon#flushed, iclass 14, count 2 2006.201.20:17:59.03#ibcon#about to write, iclass 14, count 2 2006.201.20:17:59.03#ibcon#wrote, iclass 14, count 2 2006.201.20:17:59.03#ibcon#about to read 3, iclass 14, count 2 2006.201.20:17:59.06#ibcon#read 3, iclass 14, count 2 2006.201.20:17:59.06#ibcon#about to read 4, iclass 14, count 2 2006.201.20:17:59.06#ibcon#read 4, iclass 14, count 2 2006.201.20:17:59.06#ibcon#about to read 5, iclass 14, count 2 2006.201.20:17:59.06#ibcon#read 5, iclass 14, count 2 2006.201.20:17:59.06#ibcon#about to read 6, iclass 14, count 2 2006.201.20:17:59.06#ibcon#read 6, iclass 14, count 2 2006.201.20:17:59.06#ibcon#end of sib2, iclass 14, count 2 2006.201.20:17:59.06#ibcon#*after write, iclass 14, count 2 2006.201.20:17:59.06#ibcon#*before return 0, iclass 14, count 2 2006.201.20:17:59.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:59.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:17:59.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.20:17:59.06#ibcon#ireg 7 cls_cnt 0 2006.201.20:17:59.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:59.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:59.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:59.18#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:17:59.18#ibcon#first serial, iclass 14, count 0 2006.201.20:17:59.18#ibcon#enter sib2, iclass 14, count 0 2006.201.20:17:59.18#ibcon#flushed, iclass 14, count 0 2006.201.20:17:59.18#ibcon#about to write, iclass 14, count 0 2006.201.20:17:59.18#ibcon#wrote, iclass 14, count 0 2006.201.20:17:59.18#ibcon#about to read 3, iclass 14, count 0 2006.201.20:17:59.20#ibcon#read 3, iclass 14, count 0 2006.201.20:17:59.20#ibcon#about to read 4, iclass 14, count 0 2006.201.20:17:59.20#ibcon#read 4, iclass 14, count 0 2006.201.20:17:59.20#ibcon#about to read 5, iclass 14, count 0 2006.201.20:17:59.20#ibcon#read 5, iclass 14, count 0 2006.201.20:17:59.20#ibcon#about to read 6, iclass 14, count 0 2006.201.20:17:59.20#ibcon#read 6, iclass 14, count 0 2006.201.20:17:59.20#ibcon#end of sib2, iclass 14, count 0 2006.201.20:17:59.20#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:17:59.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:17:59.20#ibcon#[27=USB\r\n] 2006.201.20:17:59.20#ibcon#*before write, iclass 14, count 0 2006.201.20:17:59.20#ibcon#enter sib2, iclass 14, count 0 2006.201.20:17:59.20#ibcon#flushed, iclass 14, count 0 2006.201.20:17:59.20#ibcon#about to write, iclass 14, count 0 2006.201.20:17:59.20#ibcon#wrote, iclass 14, count 0 2006.201.20:17:59.20#ibcon#about to read 3, iclass 14, count 0 2006.201.20:17:59.23#ibcon#read 3, iclass 14, count 0 2006.201.20:17:59.23#ibcon#about to read 4, iclass 14, count 0 2006.201.20:17:59.23#ibcon#read 4, iclass 14, count 0 2006.201.20:17:59.23#ibcon#about to read 5, iclass 14, count 0 2006.201.20:17:59.23#ibcon#read 5, iclass 14, count 0 2006.201.20:17:59.23#ibcon#about to read 6, iclass 14, count 0 2006.201.20:17:59.23#ibcon#read 6, iclass 14, count 0 2006.201.20:17:59.23#ibcon#end of sib2, iclass 14, count 0 2006.201.20:17:59.23#ibcon#*after write, iclass 14, count 0 2006.201.20:17:59.23#ibcon#*before return 0, iclass 14, count 0 2006.201.20:17:59.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:59.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:17:59.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:17:59.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:17:59.23$vck44/vabw=wide 2006.201.20:17:59.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.20:17:59.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.20:17:59.23#ibcon#ireg 8 cls_cnt 0 2006.201.20:17:59.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:59.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:59.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:59.23#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:17:59.23#ibcon#first serial, iclass 16, count 0 2006.201.20:17:59.23#ibcon#enter sib2, iclass 16, count 0 2006.201.20:17:59.23#ibcon#flushed, iclass 16, count 0 2006.201.20:17:59.23#ibcon#about to write, iclass 16, count 0 2006.201.20:17:59.23#ibcon#wrote, iclass 16, count 0 2006.201.20:17:59.23#ibcon#about to read 3, iclass 16, count 0 2006.201.20:17:59.25#ibcon#read 3, iclass 16, count 0 2006.201.20:17:59.25#ibcon#about to read 4, iclass 16, count 0 2006.201.20:17:59.25#ibcon#read 4, iclass 16, count 0 2006.201.20:17:59.25#ibcon#about to read 5, iclass 16, count 0 2006.201.20:17:59.25#ibcon#read 5, iclass 16, count 0 2006.201.20:17:59.25#ibcon#about to read 6, iclass 16, count 0 2006.201.20:17:59.25#ibcon#read 6, iclass 16, count 0 2006.201.20:17:59.25#ibcon#end of sib2, iclass 16, count 0 2006.201.20:17:59.25#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:17:59.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:17:59.25#ibcon#[25=BW32\r\n] 2006.201.20:17:59.25#ibcon#*before write, iclass 16, count 0 2006.201.20:17:59.25#ibcon#enter sib2, iclass 16, count 0 2006.201.20:17:59.25#ibcon#flushed, iclass 16, count 0 2006.201.20:17:59.25#ibcon#about to write, iclass 16, count 0 2006.201.20:17:59.25#ibcon#wrote, iclass 16, count 0 2006.201.20:17:59.25#ibcon#about to read 3, iclass 16, count 0 2006.201.20:17:59.28#ibcon#read 3, iclass 16, count 0 2006.201.20:17:59.28#ibcon#about to read 4, iclass 16, count 0 2006.201.20:17:59.28#ibcon#read 4, iclass 16, count 0 2006.201.20:17:59.28#ibcon#about to read 5, iclass 16, count 0 2006.201.20:17:59.28#ibcon#read 5, iclass 16, count 0 2006.201.20:17:59.28#ibcon#about to read 6, iclass 16, count 0 2006.201.20:17:59.28#ibcon#read 6, iclass 16, count 0 2006.201.20:17:59.28#ibcon#end of sib2, iclass 16, count 0 2006.201.20:17:59.28#ibcon#*after write, iclass 16, count 0 2006.201.20:17:59.28#ibcon#*before return 0, iclass 16, count 0 2006.201.20:17:59.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:59.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:17:59.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:17:59.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:17:59.28$vck44/vbbw=wide 2006.201.20:17:59.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.20:17:59.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.20:17:59.28#ibcon#ireg 8 cls_cnt 0 2006.201.20:17:59.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:17:59.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:17:59.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:17:59.35#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:17:59.35#ibcon#first serial, iclass 18, count 0 2006.201.20:17:59.35#ibcon#enter sib2, iclass 18, count 0 2006.201.20:17:59.35#ibcon#flushed, iclass 18, count 0 2006.201.20:17:59.35#ibcon#about to write, iclass 18, count 0 2006.201.20:17:59.35#ibcon#wrote, iclass 18, count 0 2006.201.20:17:59.35#ibcon#about to read 3, iclass 18, count 0 2006.201.20:17:59.37#ibcon#read 3, iclass 18, count 0 2006.201.20:17:59.37#ibcon#about to read 4, iclass 18, count 0 2006.201.20:17:59.37#ibcon#read 4, iclass 18, count 0 2006.201.20:17:59.37#ibcon#about to read 5, iclass 18, count 0 2006.201.20:17:59.37#ibcon#read 5, iclass 18, count 0 2006.201.20:17:59.37#ibcon#about to read 6, iclass 18, count 0 2006.201.20:17:59.37#ibcon#read 6, iclass 18, count 0 2006.201.20:17:59.37#ibcon#end of sib2, iclass 18, count 0 2006.201.20:17:59.37#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:17:59.37#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:17:59.37#ibcon#[27=BW32\r\n] 2006.201.20:17:59.37#ibcon#*before write, iclass 18, count 0 2006.201.20:17:59.37#ibcon#enter sib2, iclass 18, count 0 2006.201.20:17:59.37#ibcon#flushed, iclass 18, count 0 2006.201.20:17:59.37#ibcon#about to write, iclass 18, count 0 2006.201.20:17:59.37#ibcon#wrote, iclass 18, count 0 2006.201.20:17:59.37#ibcon#about to read 3, iclass 18, count 0 2006.201.20:17:59.41#ibcon#read 3, iclass 18, count 0 2006.201.20:17:59.41#ibcon#about to read 4, iclass 18, count 0 2006.201.20:17:59.41#ibcon#read 4, iclass 18, count 0 2006.201.20:17:59.41#ibcon#about to read 5, iclass 18, count 0 2006.201.20:17:59.41#ibcon#read 5, iclass 18, count 0 2006.201.20:17:59.41#ibcon#about to read 6, iclass 18, count 0 2006.201.20:17:59.41#ibcon#read 6, iclass 18, count 0 2006.201.20:17:59.41#ibcon#end of sib2, iclass 18, count 0 2006.201.20:17:59.41#ibcon#*after write, iclass 18, count 0 2006.201.20:17:59.41#ibcon#*before return 0, iclass 18, count 0 2006.201.20:17:59.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:17:59.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:17:59.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:17:59.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:17:59.41$setupk4/ifdk4 2006.201.20:17:59.41$ifdk4/lo= 2006.201.20:17:59.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:17:59.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:17:59.41$ifdk4/patch= 2006.201.20:17:59.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:17:59.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:17:59.41$setupk4/!*+20s 2006.201.20:18:07.20#abcon#<5=/03 2.0 3.8 20.101001002.2\r\n> 2006.201.20:18:07.22#abcon#{5=INTERFACE CLEAR} 2006.201.20:18:07.28#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:18:13.89$setupk4/"tpicd 2006.201.20:18:13.89$setupk4/echo=off 2006.201.20:18:13.89$setupk4/xlog=off 2006.201.20:18:13.89:!2006.201.20:21:07 2006.201.20:18:19.13#trakl#Source acquired 2006.201.20:18:20.13#flagr#flagr/antenna,acquired 2006.201.20:21:07.00:preob 2006.201.20:21:07.14/onsource/TRACKING 2006.201.20:21:07.14:!2006.201.20:21:17 2006.201.20:21:17.00:"tape 2006.201.20:21:17.00:"st=record 2006.201.20:21:17.00:data_valid=on 2006.201.20:21:17.00:midob 2006.201.20:21:17.14/onsource/TRACKING 2006.201.20:21:17.14/wx/20.10,1002.3,100 2006.201.20:21:17.32/cable/+6.4817E-03 2006.201.20:21:18.41/va/01,08,usb,yes,39,42 2006.201.20:21:18.41/va/02,07,usb,yes,42,43 2006.201.20:21:18.41/va/03,08,usb,yes,38,40 2006.201.20:21:18.41/va/04,07,usb,yes,43,46 2006.201.20:21:18.41/va/05,04,usb,yes,39,39 2006.201.20:21:18.41/va/06,05,usb,yes,39,39 2006.201.20:21:18.41/va/07,05,usb,yes,38,39 2006.201.20:21:18.41/va/08,04,usb,yes,38,45 2006.201.20:21:18.64/valo/01,524.99,yes,locked 2006.201.20:21:18.64/valo/02,534.99,yes,locked 2006.201.20:21:18.64/valo/03,564.99,yes,locked 2006.201.20:21:18.64/valo/04,624.99,yes,locked 2006.201.20:21:18.64/valo/05,734.99,yes,locked 2006.201.20:21:18.64/valo/06,814.99,yes,locked 2006.201.20:21:18.64/valo/07,864.99,yes,locked 2006.201.20:21:18.64/valo/08,884.99,yes,locked 2006.201.20:21:19.73/vb/01,04,usb,yes,29,27 2006.201.20:21:19.73/vb/02,05,usb,yes,27,27 2006.201.20:21:19.73/vb/03,04,usb,yes,28,31 2006.201.20:21:19.73/vb/04,05,usb,yes,28,27 2006.201.20:21:19.73/vb/05,04,usb,yes,25,27 2006.201.20:21:19.73/vb/06,04,usb,yes,29,25 2006.201.20:21:19.73/vb/07,04,usb,yes,29,29 2006.201.20:21:19.73/vb/08,04,usb,yes,26,30 2006.201.20:21:19.96/vblo/01,629.99,yes,locked 2006.201.20:21:19.96/vblo/02,634.99,yes,locked 2006.201.20:21:19.96/vblo/03,649.99,yes,locked 2006.201.20:21:19.96/vblo/04,679.99,yes,locked 2006.201.20:21:19.96/vblo/05,709.99,yes,locked 2006.201.20:21:19.96/vblo/06,719.99,yes,locked 2006.201.20:21:19.96/vblo/07,734.99,yes,locked 2006.201.20:21:19.96/vblo/08,744.99,yes,locked 2006.201.20:21:20.11/vabw/8 2006.201.20:21:20.26/vbbw/8 2006.201.20:21:20.37/xfe/off,on,14.2 2006.201.20:21:20.77/ifatt/23,28,28,28 2006.201.20:21:21.05/fmout-gps/S +4.55E-07 2006.201.20:21:21.12:!2006.201.20:23:27 2006.201.20:23:27.00:data_valid=off 2006.201.20:23:27.00:"et 2006.201.20:23:27.00:!+3s 2006.201.20:23:30.02:"tape 2006.201.20:23:30.02:postob 2006.201.20:23:30.12/cable/+6.4818E-03 2006.201.20:23:30.12/wx/20.10,1002.3,100 2006.201.20:23:30.20/fmout-gps/S +4.54E-07 2006.201.20:23:30.20:scan_name=201-2029,jd0607,80 2006.201.20:23:30.21:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.201.20:23:32.14#flagr#flagr/antenna,new-source 2006.201.20:23:32.14:checkk5 2006.201.20:23:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:23:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:23:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:23:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:23:34.00/chk_obsdata//k5ts1/T2012021??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.20:23:34.37/chk_obsdata//k5ts2/T2012021??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.20:23:34.73/chk_obsdata//k5ts3/T2012021??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.20:23:35.10/chk_obsdata//k5ts4/T2012021??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.20:23:35.79/k5log//k5ts1_log_newline 2006.201.20:23:36.48/k5log//k5ts2_log_newline 2006.201.20:23:37.16/k5log//k5ts3_log_newline 2006.201.20:23:37.85/k5log//k5ts4_log_newline 2006.201.20:23:37.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:23:37.87:setupk4=1 2006.201.20:23:37.87$setupk4/echo=on 2006.201.20:23:37.87$setupk4/pcalon 2006.201.20:23:37.87$pcalon/"no phase cal control is implemented here 2006.201.20:23:37.87$setupk4/"tpicd=stop 2006.201.20:23:37.87$setupk4/"rec=synch_on 2006.201.20:23:37.87$setupk4/"rec_mode=128 2006.201.20:23:37.87$setupk4/!* 2006.201.20:23:37.87$setupk4/recpk4 2006.201.20:23:37.87$recpk4/recpatch= 2006.201.20:23:37.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:23:37.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:23:37.88$setupk4/vck44 2006.201.20:23:37.88$vck44/valo=1,524.99 2006.201.20:23:37.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.20:23:37.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.20:23:37.88#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:37.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:37.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:37.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:37.88#ibcon#enter wrdev, iclass 11, count 0 2006.201.20:23:37.88#ibcon#first serial, iclass 11, count 0 2006.201.20:23:37.88#ibcon#enter sib2, iclass 11, count 0 2006.201.20:23:37.88#ibcon#flushed, iclass 11, count 0 2006.201.20:23:37.88#ibcon#about to write, iclass 11, count 0 2006.201.20:23:37.88#ibcon#wrote, iclass 11, count 0 2006.201.20:23:37.88#ibcon#about to read 3, iclass 11, count 0 2006.201.20:23:37.92#ibcon#read 3, iclass 11, count 0 2006.201.20:23:37.92#ibcon#about to read 4, iclass 11, count 0 2006.201.20:23:37.92#ibcon#read 4, iclass 11, count 0 2006.201.20:23:37.92#ibcon#about to read 5, iclass 11, count 0 2006.201.20:23:37.92#ibcon#read 5, iclass 11, count 0 2006.201.20:23:37.92#ibcon#about to read 6, iclass 11, count 0 2006.201.20:23:37.92#ibcon#read 6, iclass 11, count 0 2006.201.20:23:37.92#ibcon#end of sib2, iclass 11, count 0 2006.201.20:23:37.92#ibcon#*mode == 0, iclass 11, count 0 2006.201.20:23:37.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.20:23:37.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:23:37.92#ibcon#*before write, iclass 11, count 0 2006.201.20:23:37.92#ibcon#enter sib2, iclass 11, count 0 2006.201.20:23:37.92#ibcon#flushed, iclass 11, count 0 2006.201.20:23:37.92#ibcon#about to write, iclass 11, count 0 2006.201.20:23:37.92#ibcon#wrote, iclass 11, count 0 2006.201.20:23:37.92#ibcon#about to read 3, iclass 11, count 0 2006.201.20:23:37.97#ibcon#read 3, iclass 11, count 0 2006.201.20:23:37.97#ibcon#about to read 4, iclass 11, count 0 2006.201.20:23:37.97#ibcon#read 4, iclass 11, count 0 2006.201.20:23:37.97#ibcon#about to read 5, iclass 11, count 0 2006.201.20:23:37.97#ibcon#read 5, iclass 11, count 0 2006.201.20:23:37.97#ibcon#about to read 6, iclass 11, count 0 2006.201.20:23:37.97#ibcon#read 6, iclass 11, count 0 2006.201.20:23:37.97#ibcon#end of sib2, iclass 11, count 0 2006.201.20:23:37.97#ibcon#*after write, iclass 11, count 0 2006.201.20:23:37.97#ibcon#*before return 0, iclass 11, count 0 2006.201.20:23:37.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:37.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:37.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.20:23:37.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.20:23:37.97$vck44/va=1,8 2006.201.20:23:37.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.20:23:37.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.20:23:37.97#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:37.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:37.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:37.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:37.97#ibcon#enter wrdev, iclass 13, count 2 2006.201.20:23:37.97#ibcon#first serial, iclass 13, count 2 2006.201.20:23:37.97#ibcon#enter sib2, iclass 13, count 2 2006.201.20:23:37.97#ibcon#flushed, iclass 13, count 2 2006.201.20:23:37.97#ibcon#about to write, iclass 13, count 2 2006.201.20:23:37.97#ibcon#wrote, iclass 13, count 2 2006.201.20:23:37.97#ibcon#about to read 3, iclass 13, count 2 2006.201.20:23:37.99#ibcon#read 3, iclass 13, count 2 2006.201.20:23:37.99#ibcon#about to read 4, iclass 13, count 2 2006.201.20:23:37.99#ibcon#read 4, iclass 13, count 2 2006.201.20:23:37.99#ibcon#about to read 5, iclass 13, count 2 2006.201.20:23:37.99#ibcon#read 5, iclass 13, count 2 2006.201.20:23:37.99#ibcon#about to read 6, iclass 13, count 2 2006.201.20:23:37.99#ibcon#read 6, iclass 13, count 2 2006.201.20:23:37.99#ibcon#end of sib2, iclass 13, count 2 2006.201.20:23:37.99#ibcon#*mode == 0, iclass 13, count 2 2006.201.20:23:37.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.20:23:37.99#ibcon#[25=AT01-08\r\n] 2006.201.20:23:37.99#ibcon#*before write, iclass 13, count 2 2006.201.20:23:37.99#ibcon#enter sib2, iclass 13, count 2 2006.201.20:23:37.99#ibcon#flushed, iclass 13, count 2 2006.201.20:23:37.99#ibcon#about to write, iclass 13, count 2 2006.201.20:23:37.99#ibcon#wrote, iclass 13, count 2 2006.201.20:23:37.99#ibcon#about to read 3, iclass 13, count 2 2006.201.20:23:38.02#ibcon#read 3, iclass 13, count 2 2006.201.20:23:38.02#ibcon#about to read 4, iclass 13, count 2 2006.201.20:23:38.02#ibcon#read 4, iclass 13, count 2 2006.201.20:23:38.02#ibcon#about to read 5, iclass 13, count 2 2006.201.20:23:38.02#ibcon#read 5, iclass 13, count 2 2006.201.20:23:38.02#ibcon#about to read 6, iclass 13, count 2 2006.201.20:23:38.02#ibcon#read 6, iclass 13, count 2 2006.201.20:23:38.02#ibcon#end of sib2, iclass 13, count 2 2006.201.20:23:38.02#ibcon#*after write, iclass 13, count 2 2006.201.20:23:38.02#ibcon#*before return 0, iclass 13, count 2 2006.201.20:23:38.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:38.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:38.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.20:23:38.02#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:38.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:38.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:38.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:38.14#ibcon#enter wrdev, iclass 13, count 0 2006.201.20:23:38.14#ibcon#first serial, iclass 13, count 0 2006.201.20:23:38.14#ibcon#enter sib2, iclass 13, count 0 2006.201.20:23:38.14#ibcon#flushed, iclass 13, count 0 2006.201.20:23:38.14#ibcon#about to write, iclass 13, count 0 2006.201.20:23:38.14#ibcon#wrote, iclass 13, count 0 2006.201.20:23:38.14#ibcon#about to read 3, iclass 13, count 0 2006.201.20:23:38.16#ibcon#read 3, iclass 13, count 0 2006.201.20:23:38.16#ibcon#about to read 4, iclass 13, count 0 2006.201.20:23:38.16#ibcon#read 4, iclass 13, count 0 2006.201.20:23:38.16#ibcon#about to read 5, iclass 13, count 0 2006.201.20:23:38.16#ibcon#read 5, iclass 13, count 0 2006.201.20:23:38.16#ibcon#about to read 6, iclass 13, count 0 2006.201.20:23:38.16#ibcon#read 6, iclass 13, count 0 2006.201.20:23:38.16#ibcon#end of sib2, iclass 13, count 0 2006.201.20:23:38.16#ibcon#*mode == 0, iclass 13, count 0 2006.201.20:23:38.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.20:23:38.16#ibcon#[25=USB\r\n] 2006.201.20:23:38.16#ibcon#*before write, iclass 13, count 0 2006.201.20:23:38.16#ibcon#enter sib2, iclass 13, count 0 2006.201.20:23:38.16#ibcon#flushed, iclass 13, count 0 2006.201.20:23:38.16#ibcon#about to write, iclass 13, count 0 2006.201.20:23:38.16#ibcon#wrote, iclass 13, count 0 2006.201.20:23:38.16#ibcon#about to read 3, iclass 13, count 0 2006.201.20:23:38.19#ibcon#read 3, iclass 13, count 0 2006.201.20:23:38.19#ibcon#about to read 4, iclass 13, count 0 2006.201.20:23:38.19#ibcon#read 4, iclass 13, count 0 2006.201.20:23:38.19#ibcon#about to read 5, iclass 13, count 0 2006.201.20:23:38.19#ibcon#read 5, iclass 13, count 0 2006.201.20:23:38.19#ibcon#about to read 6, iclass 13, count 0 2006.201.20:23:38.19#ibcon#read 6, iclass 13, count 0 2006.201.20:23:38.19#ibcon#end of sib2, iclass 13, count 0 2006.201.20:23:38.19#ibcon#*after write, iclass 13, count 0 2006.201.20:23:38.19#ibcon#*before return 0, iclass 13, count 0 2006.201.20:23:38.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:38.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:38.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.20:23:38.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.20:23:38.19$vck44/valo=2,534.99 2006.201.20:23:38.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.20:23:38.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.20:23:38.19#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:38.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:38.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:38.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:38.19#ibcon#enter wrdev, iclass 15, count 0 2006.201.20:23:38.19#ibcon#first serial, iclass 15, count 0 2006.201.20:23:38.19#ibcon#enter sib2, iclass 15, count 0 2006.201.20:23:38.19#ibcon#flushed, iclass 15, count 0 2006.201.20:23:38.19#ibcon#about to write, iclass 15, count 0 2006.201.20:23:38.19#ibcon#wrote, iclass 15, count 0 2006.201.20:23:38.19#ibcon#about to read 3, iclass 15, count 0 2006.201.20:23:38.21#ibcon#read 3, iclass 15, count 0 2006.201.20:23:38.21#ibcon#about to read 4, iclass 15, count 0 2006.201.20:23:38.21#ibcon#read 4, iclass 15, count 0 2006.201.20:23:38.21#ibcon#about to read 5, iclass 15, count 0 2006.201.20:23:38.21#ibcon#read 5, iclass 15, count 0 2006.201.20:23:38.21#ibcon#about to read 6, iclass 15, count 0 2006.201.20:23:38.21#ibcon#read 6, iclass 15, count 0 2006.201.20:23:38.21#ibcon#end of sib2, iclass 15, count 0 2006.201.20:23:38.21#ibcon#*mode == 0, iclass 15, count 0 2006.201.20:23:38.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.20:23:38.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:23:38.21#ibcon#*before write, iclass 15, count 0 2006.201.20:23:38.21#ibcon#enter sib2, iclass 15, count 0 2006.201.20:23:38.21#ibcon#flushed, iclass 15, count 0 2006.201.20:23:38.21#ibcon#about to write, iclass 15, count 0 2006.201.20:23:38.21#ibcon#wrote, iclass 15, count 0 2006.201.20:23:38.21#ibcon#about to read 3, iclass 15, count 0 2006.201.20:23:38.26#ibcon#read 3, iclass 15, count 0 2006.201.20:23:38.26#ibcon#about to read 4, iclass 15, count 0 2006.201.20:23:38.26#ibcon#read 4, iclass 15, count 0 2006.201.20:23:38.26#ibcon#about to read 5, iclass 15, count 0 2006.201.20:23:38.26#ibcon#read 5, iclass 15, count 0 2006.201.20:23:38.26#ibcon#about to read 6, iclass 15, count 0 2006.201.20:23:38.26#ibcon#read 6, iclass 15, count 0 2006.201.20:23:38.26#ibcon#end of sib2, iclass 15, count 0 2006.201.20:23:38.26#ibcon#*after write, iclass 15, count 0 2006.201.20:23:38.26#ibcon#*before return 0, iclass 15, count 0 2006.201.20:23:38.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:38.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:38.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.20:23:38.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.20:23:38.26$vck44/va=2,7 2006.201.20:23:38.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.20:23:38.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.20:23:38.26#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:38.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:38.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:38.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:38.31#ibcon#enter wrdev, iclass 17, count 2 2006.201.20:23:38.31#ibcon#first serial, iclass 17, count 2 2006.201.20:23:38.31#ibcon#enter sib2, iclass 17, count 2 2006.201.20:23:38.31#ibcon#flushed, iclass 17, count 2 2006.201.20:23:38.31#ibcon#about to write, iclass 17, count 2 2006.201.20:23:38.31#ibcon#wrote, iclass 17, count 2 2006.201.20:23:38.31#ibcon#about to read 3, iclass 17, count 2 2006.201.20:23:38.33#ibcon#read 3, iclass 17, count 2 2006.201.20:23:38.33#ibcon#about to read 4, iclass 17, count 2 2006.201.20:23:38.33#ibcon#read 4, iclass 17, count 2 2006.201.20:23:38.33#ibcon#about to read 5, iclass 17, count 2 2006.201.20:23:38.33#ibcon#read 5, iclass 17, count 2 2006.201.20:23:38.33#ibcon#about to read 6, iclass 17, count 2 2006.201.20:23:38.33#ibcon#read 6, iclass 17, count 2 2006.201.20:23:38.33#ibcon#end of sib2, iclass 17, count 2 2006.201.20:23:38.33#ibcon#*mode == 0, iclass 17, count 2 2006.201.20:23:38.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.20:23:38.33#ibcon#[25=AT02-07\r\n] 2006.201.20:23:38.33#ibcon#*before write, iclass 17, count 2 2006.201.20:23:38.33#ibcon#enter sib2, iclass 17, count 2 2006.201.20:23:38.33#ibcon#flushed, iclass 17, count 2 2006.201.20:23:38.33#ibcon#about to write, iclass 17, count 2 2006.201.20:23:38.33#ibcon#wrote, iclass 17, count 2 2006.201.20:23:38.33#ibcon#about to read 3, iclass 17, count 2 2006.201.20:23:38.36#ibcon#read 3, iclass 17, count 2 2006.201.20:23:38.36#ibcon#about to read 4, iclass 17, count 2 2006.201.20:23:38.36#ibcon#read 4, iclass 17, count 2 2006.201.20:23:38.36#ibcon#about to read 5, iclass 17, count 2 2006.201.20:23:38.36#ibcon#read 5, iclass 17, count 2 2006.201.20:23:38.36#ibcon#about to read 6, iclass 17, count 2 2006.201.20:23:38.36#ibcon#read 6, iclass 17, count 2 2006.201.20:23:38.36#ibcon#end of sib2, iclass 17, count 2 2006.201.20:23:38.36#ibcon#*after write, iclass 17, count 2 2006.201.20:23:38.36#ibcon#*before return 0, iclass 17, count 2 2006.201.20:23:38.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:38.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:38.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.20:23:38.36#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:38.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:38.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:38.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:38.48#ibcon#enter wrdev, iclass 17, count 0 2006.201.20:23:38.48#ibcon#first serial, iclass 17, count 0 2006.201.20:23:38.48#ibcon#enter sib2, iclass 17, count 0 2006.201.20:23:38.48#ibcon#flushed, iclass 17, count 0 2006.201.20:23:38.48#ibcon#about to write, iclass 17, count 0 2006.201.20:23:38.48#ibcon#wrote, iclass 17, count 0 2006.201.20:23:38.48#ibcon#about to read 3, iclass 17, count 0 2006.201.20:23:38.50#ibcon#read 3, iclass 17, count 0 2006.201.20:23:38.50#ibcon#about to read 4, iclass 17, count 0 2006.201.20:23:38.50#ibcon#read 4, iclass 17, count 0 2006.201.20:23:38.50#ibcon#about to read 5, iclass 17, count 0 2006.201.20:23:38.50#ibcon#read 5, iclass 17, count 0 2006.201.20:23:38.50#ibcon#about to read 6, iclass 17, count 0 2006.201.20:23:38.50#ibcon#read 6, iclass 17, count 0 2006.201.20:23:38.50#ibcon#end of sib2, iclass 17, count 0 2006.201.20:23:38.50#ibcon#*mode == 0, iclass 17, count 0 2006.201.20:23:38.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.20:23:38.50#ibcon#[25=USB\r\n] 2006.201.20:23:38.50#ibcon#*before write, iclass 17, count 0 2006.201.20:23:38.50#ibcon#enter sib2, iclass 17, count 0 2006.201.20:23:38.50#ibcon#flushed, iclass 17, count 0 2006.201.20:23:38.50#ibcon#about to write, iclass 17, count 0 2006.201.20:23:38.50#ibcon#wrote, iclass 17, count 0 2006.201.20:23:38.50#ibcon#about to read 3, iclass 17, count 0 2006.201.20:23:38.53#ibcon#read 3, iclass 17, count 0 2006.201.20:23:38.53#ibcon#about to read 4, iclass 17, count 0 2006.201.20:23:38.53#ibcon#read 4, iclass 17, count 0 2006.201.20:23:38.53#ibcon#about to read 5, iclass 17, count 0 2006.201.20:23:38.53#ibcon#read 5, iclass 17, count 0 2006.201.20:23:38.53#ibcon#about to read 6, iclass 17, count 0 2006.201.20:23:38.53#ibcon#read 6, iclass 17, count 0 2006.201.20:23:38.53#ibcon#end of sib2, iclass 17, count 0 2006.201.20:23:38.53#ibcon#*after write, iclass 17, count 0 2006.201.20:23:38.53#ibcon#*before return 0, iclass 17, count 0 2006.201.20:23:38.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:38.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:38.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.20:23:38.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.20:23:38.53$vck44/valo=3,564.99 2006.201.20:23:38.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.20:23:38.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.20:23:38.53#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:38.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:38.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:38.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:38.53#ibcon#enter wrdev, iclass 19, count 0 2006.201.20:23:38.53#ibcon#first serial, iclass 19, count 0 2006.201.20:23:38.53#ibcon#enter sib2, iclass 19, count 0 2006.201.20:23:38.53#ibcon#flushed, iclass 19, count 0 2006.201.20:23:38.53#ibcon#about to write, iclass 19, count 0 2006.201.20:23:38.53#ibcon#wrote, iclass 19, count 0 2006.201.20:23:38.53#ibcon#about to read 3, iclass 19, count 0 2006.201.20:23:38.55#ibcon#read 3, iclass 19, count 0 2006.201.20:23:38.55#ibcon#about to read 4, iclass 19, count 0 2006.201.20:23:38.55#ibcon#read 4, iclass 19, count 0 2006.201.20:23:38.55#ibcon#about to read 5, iclass 19, count 0 2006.201.20:23:38.55#ibcon#read 5, iclass 19, count 0 2006.201.20:23:38.55#ibcon#about to read 6, iclass 19, count 0 2006.201.20:23:38.55#ibcon#read 6, iclass 19, count 0 2006.201.20:23:38.55#ibcon#end of sib2, iclass 19, count 0 2006.201.20:23:38.55#ibcon#*mode == 0, iclass 19, count 0 2006.201.20:23:38.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.20:23:38.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:23:38.55#ibcon#*before write, iclass 19, count 0 2006.201.20:23:38.55#ibcon#enter sib2, iclass 19, count 0 2006.201.20:23:38.55#ibcon#flushed, iclass 19, count 0 2006.201.20:23:38.55#ibcon#about to write, iclass 19, count 0 2006.201.20:23:38.55#ibcon#wrote, iclass 19, count 0 2006.201.20:23:38.55#ibcon#about to read 3, iclass 19, count 0 2006.201.20:23:38.60#ibcon#read 3, iclass 19, count 0 2006.201.20:23:38.60#ibcon#about to read 4, iclass 19, count 0 2006.201.20:23:38.60#ibcon#read 4, iclass 19, count 0 2006.201.20:23:38.60#ibcon#about to read 5, iclass 19, count 0 2006.201.20:23:38.60#ibcon#read 5, iclass 19, count 0 2006.201.20:23:38.60#ibcon#about to read 6, iclass 19, count 0 2006.201.20:23:38.60#ibcon#read 6, iclass 19, count 0 2006.201.20:23:38.60#ibcon#end of sib2, iclass 19, count 0 2006.201.20:23:38.60#ibcon#*after write, iclass 19, count 0 2006.201.20:23:38.60#ibcon#*before return 0, iclass 19, count 0 2006.201.20:23:38.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:38.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:38.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.20:23:38.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.20:23:38.60$vck44/va=3,8 2006.201.20:23:38.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.20:23:38.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.20:23:38.60#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:38.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:38.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:38.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:38.65#ibcon#enter wrdev, iclass 21, count 2 2006.201.20:23:38.65#ibcon#first serial, iclass 21, count 2 2006.201.20:23:38.65#ibcon#enter sib2, iclass 21, count 2 2006.201.20:23:38.65#ibcon#flushed, iclass 21, count 2 2006.201.20:23:38.65#ibcon#about to write, iclass 21, count 2 2006.201.20:23:38.65#ibcon#wrote, iclass 21, count 2 2006.201.20:23:38.65#ibcon#about to read 3, iclass 21, count 2 2006.201.20:23:38.67#ibcon#read 3, iclass 21, count 2 2006.201.20:23:38.67#ibcon#about to read 4, iclass 21, count 2 2006.201.20:23:38.67#ibcon#read 4, iclass 21, count 2 2006.201.20:23:38.67#ibcon#about to read 5, iclass 21, count 2 2006.201.20:23:38.67#ibcon#read 5, iclass 21, count 2 2006.201.20:23:38.67#ibcon#about to read 6, iclass 21, count 2 2006.201.20:23:38.67#ibcon#read 6, iclass 21, count 2 2006.201.20:23:38.67#ibcon#end of sib2, iclass 21, count 2 2006.201.20:23:38.67#ibcon#*mode == 0, iclass 21, count 2 2006.201.20:23:38.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.20:23:38.67#ibcon#[25=AT03-08\r\n] 2006.201.20:23:38.67#ibcon#*before write, iclass 21, count 2 2006.201.20:23:38.67#ibcon#enter sib2, iclass 21, count 2 2006.201.20:23:38.67#ibcon#flushed, iclass 21, count 2 2006.201.20:23:38.67#ibcon#about to write, iclass 21, count 2 2006.201.20:23:38.67#ibcon#wrote, iclass 21, count 2 2006.201.20:23:38.67#ibcon#about to read 3, iclass 21, count 2 2006.201.20:23:38.70#ibcon#read 3, iclass 21, count 2 2006.201.20:23:38.70#ibcon#about to read 4, iclass 21, count 2 2006.201.20:23:38.70#ibcon#read 4, iclass 21, count 2 2006.201.20:23:38.70#ibcon#about to read 5, iclass 21, count 2 2006.201.20:23:38.70#ibcon#read 5, iclass 21, count 2 2006.201.20:23:38.70#ibcon#about to read 6, iclass 21, count 2 2006.201.20:23:38.70#ibcon#read 6, iclass 21, count 2 2006.201.20:23:38.70#ibcon#end of sib2, iclass 21, count 2 2006.201.20:23:38.70#ibcon#*after write, iclass 21, count 2 2006.201.20:23:38.70#ibcon#*before return 0, iclass 21, count 2 2006.201.20:23:38.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:38.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:38.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.20:23:38.70#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:38.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:38.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:38.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:38.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.20:23:38.82#ibcon#first serial, iclass 21, count 0 2006.201.20:23:38.82#ibcon#enter sib2, iclass 21, count 0 2006.201.20:23:38.82#ibcon#flushed, iclass 21, count 0 2006.201.20:23:38.82#ibcon#about to write, iclass 21, count 0 2006.201.20:23:38.82#ibcon#wrote, iclass 21, count 0 2006.201.20:23:38.82#ibcon#about to read 3, iclass 21, count 0 2006.201.20:23:38.84#ibcon#read 3, iclass 21, count 0 2006.201.20:23:38.84#ibcon#about to read 4, iclass 21, count 0 2006.201.20:23:38.84#ibcon#read 4, iclass 21, count 0 2006.201.20:23:38.84#ibcon#about to read 5, iclass 21, count 0 2006.201.20:23:38.84#ibcon#read 5, iclass 21, count 0 2006.201.20:23:38.84#ibcon#about to read 6, iclass 21, count 0 2006.201.20:23:38.84#ibcon#read 6, iclass 21, count 0 2006.201.20:23:38.84#ibcon#end of sib2, iclass 21, count 0 2006.201.20:23:38.84#ibcon#*mode == 0, iclass 21, count 0 2006.201.20:23:38.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.20:23:38.84#ibcon#[25=USB\r\n] 2006.201.20:23:38.84#ibcon#*before write, iclass 21, count 0 2006.201.20:23:38.84#ibcon#enter sib2, iclass 21, count 0 2006.201.20:23:38.84#ibcon#flushed, iclass 21, count 0 2006.201.20:23:38.84#ibcon#about to write, iclass 21, count 0 2006.201.20:23:38.84#ibcon#wrote, iclass 21, count 0 2006.201.20:23:38.84#ibcon#about to read 3, iclass 21, count 0 2006.201.20:23:38.87#ibcon#read 3, iclass 21, count 0 2006.201.20:23:38.87#ibcon#about to read 4, iclass 21, count 0 2006.201.20:23:38.87#ibcon#read 4, iclass 21, count 0 2006.201.20:23:38.87#ibcon#about to read 5, iclass 21, count 0 2006.201.20:23:38.87#ibcon#read 5, iclass 21, count 0 2006.201.20:23:38.87#ibcon#about to read 6, iclass 21, count 0 2006.201.20:23:38.87#ibcon#read 6, iclass 21, count 0 2006.201.20:23:38.87#ibcon#end of sib2, iclass 21, count 0 2006.201.20:23:38.87#ibcon#*after write, iclass 21, count 0 2006.201.20:23:38.87#ibcon#*before return 0, iclass 21, count 0 2006.201.20:23:38.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:38.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:38.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.20:23:38.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.20:23:38.87$vck44/valo=4,624.99 2006.201.20:23:38.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.20:23:38.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.20:23:38.87#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:38.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:38.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:38.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:38.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:23:38.87#ibcon#first serial, iclass 23, count 0 2006.201.20:23:38.87#ibcon#enter sib2, iclass 23, count 0 2006.201.20:23:38.87#ibcon#flushed, iclass 23, count 0 2006.201.20:23:38.87#ibcon#about to write, iclass 23, count 0 2006.201.20:23:38.87#ibcon#wrote, iclass 23, count 0 2006.201.20:23:38.87#ibcon#about to read 3, iclass 23, count 0 2006.201.20:23:38.89#ibcon#read 3, iclass 23, count 0 2006.201.20:23:38.89#ibcon#about to read 4, iclass 23, count 0 2006.201.20:23:38.89#ibcon#read 4, iclass 23, count 0 2006.201.20:23:38.89#ibcon#about to read 5, iclass 23, count 0 2006.201.20:23:38.89#ibcon#read 5, iclass 23, count 0 2006.201.20:23:38.89#ibcon#about to read 6, iclass 23, count 0 2006.201.20:23:38.89#ibcon#read 6, iclass 23, count 0 2006.201.20:23:38.89#ibcon#end of sib2, iclass 23, count 0 2006.201.20:23:38.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:23:38.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:23:38.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:23:38.89#ibcon#*before write, iclass 23, count 0 2006.201.20:23:38.89#ibcon#enter sib2, iclass 23, count 0 2006.201.20:23:38.89#ibcon#flushed, iclass 23, count 0 2006.201.20:23:38.89#ibcon#about to write, iclass 23, count 0 2006.201.20:23:38.89#ibcon#wrote, iclass 23, count 0 2006.201.20:23:38.89#ibcon#about to read 3, iclass 23, count 0 2006.201.20:23:38.94#ibcon#read 3, iclass 23, count 0 2006.201.20:23:38.94#ibcon#about to read 4, iclass 23, count 0 2006.201.20:23:38.94#ibcon#read 4, iclass 23, count 0 2006.201.20:23:38.94#ibcon#about to read 5, iclass 23, count 0 2006.201.20:23:38.94#ibcon#read 5, iclass 23, count 0 2006.201.20:23:38.94#ibcon#about to read 6, iclass 23, count 0 2006.201.20:23:38.94#ibcon#read 6, iclass 23, count 0 2006.201.20:23:38.94#ibcon#end of sib2, iclass 23, count 0 2006.201.20:23:38.94#ibcon#*after write, iclass 23, count 0 2006.201.20:23:38.94#ibcon#*before return 0, iclass 23, count 0 2006.201.20:23:38.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:38.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:38.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:23:38.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:23:38.94$vck44/va=4,7 2006.201.20:23:38.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.20:23:38.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.20:23:38.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:38.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:38.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:38.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:38.99#ibcon#enter wrdev, iclass 25, count 2 2006.201.20:23:38.99#ibcon#first serial, iclass 25, count 2 2006.201.20:23:38.99#ibcon#enter sib2, iclass 25, count 2 2006.201.20:23:38.99#ibcon#flushed, iclass 25, count 2 2006.201.20:23:38.99#ibcon#about to write, iclass 25, count 2 2006.201.20:23:38.99#ibcon#wrote, iclass 25, count 2 2006.201.20:23:38.99#ibcon#about to read 3, iclass 25, count 2 2006.201.20:23:39.01#ibcon#read 3, iclass 25, count 2 2006.201.20:23:39.01#ibcon#about to read 4, iclass 25, count 2 2006.201.20:23:39.01#ibcon#read 4, iclass 25, count 2 2006.201.20:23:39.01#ibcon#about to read 5, iclass 25, count 2 2006.201.20:23:39.01#ibcon#read 5, iclass 25, count 2 2006.201.20:23:39.01#ibcon#about to read 6, iclass 25, count 2 2006.201.20:23:39.01#ibcon#read 6, iclass 25, count 2 2006.201.20:23:39.01#ibcon#end of sib2, iclass 25, count 2 2006.201.20:23:39.01#ibcon#*mode == 0, iclass 25, count 2 2006.201.20:23:39.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.20:23:39.01#ibcon#[25=AT04-07\r\n] 2006.201.20:23:39.01#ibcon#*before write, iclass 25, count 2 2006.201.20:23:39.01#ibcon#enter sib2, iclass 25, count 2 2006.201.20:23:39.01#ibcon#flushed, iclass 25, count 2 2006.201.20:23:39.01#ibcon#about to write, iclass 25, count 2 2006.201.20:23:39.01#ibcon#wrote, iclass 25, count 2 2006.201.20:23:39.01#ibcon#about to read 3, iclass 25, count 2 2006.201.20:23:39.04#ibcon#read 3, iclass 25, count 2 2006.201.20:23:39.04#ibcon#about to read 4, iclass 25, count 2 2006.201.20:23:39.04#ibcon#read 4, iclass 25, count 2 2006.201.20:23:39.04#ibcon#about to read 5, iclass 25, count 2 2006.201.20:23:39.04#ibcon#read 5, iclass 25, count 2 2006.201.20:23:39.04#ibcon#about to read 6, iclass 25, count 2 2006.201.20:23:39.04#ibcon#read 6, iclass 25, count 2 2006.201.20:23:39.04#ibcon#end of sib2, iclass 25, count 2 2006.201.20:23:39.04#ibcon#*after write, iclass 25, count 2 2006.201.20:23:39.04#ibcon#*before return 0, iclass 25, count 2 2006.201.20:23:39.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:39.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:39.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.20:23:39.04#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:39.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:39.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:39.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:39.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.20:23:39.16#ibcon#first serial, iclass 25, count 0 2006.201.20:23:39.16#ibcon#enter sib2, iclass 25, count 0 2006.201.20:23:39.16#ibcon#flushed, iclass 25, count 0 2006.201.20:23:39.16#ibcon#about to write, iclass 25, count 0 2006.201.20:23:39.16#ibcon#wrote, iclass 25, count 0 2006.201.20:23:39.16#ibcon#about to read 3, iclass 25, count 0 2006.201.20:23:39.18#ibcon#read 3, iclass 25, count 0 2006.201.20:23:39.18#ibcon#about to read 4, iclass 25, count 0 2006.201.20:23:39.18#ibcon#read 4, iclass 25, count 0 2006.201.20:23:39.18#ibcon#about to read 5, iclass 25, count 0 2006.201.20:23:39.18#ibcon#read 5, iclass 25, count 0 2006.201.20:23:39.18#ibcon#about to read 6, iclass 25, count 0 2006.201.20:23:39.18#ibcon#read 6, iclass 25, count 0 2006.201.20:23:39.18#ibcon#end of sib2, iclass 25, count 0 2006.201.20:23:39.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.20:23:39.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.20:23:39.18#ibcon#[25=USB\r\n] 2006.201.20:23:39.18#ibcon#*before write, iclass 25, count 0 2006.201.20:23:39.18#ibcon#enter sib2, iclass 25, count 0 2006.201.20:23:39.18#ibcon#flushed, iclass 25, count 0 2006.201.20:23:39.18#ibcon#about to write, iclass 25, count 0 2006.201.20:23:39.18#ibcon#wrote, iclass 25, count 0 2006.201.20:23:39.18#ibcon#about to read 3, iclass 25, count 0 2006.201.20:23:39.21#ibcon#read 3, iclass 25, count 0 2006.201.20:23:39.21#ibcon#about to read 4, iclass 25, count 0 2006.201.20:23:39.21#ibcon#read 4, iclass 25, count 0 2006.201.20:23:39.21#ibcon#about to read 5, iclass 25, count 0 2006.201.20:23:39.21#ibcon#read 5, iclass 25, count 0 2006.201.20:23:39.21#ibcon#about to read 6, iclass 25, count 0 2006.201.20:23:39.21#ibcon#read 6, iclass 25, count 0 2006.201.20:23:39.21#ibcon#end of sib2, iclass 25, count 0 2006.201.20:23:39.21#ibcon#*after write, iclass 25, count 0 2006.201.20:23:39.21#ibcon#*before return 0, iclass 25, count 0 2006.201.20:23:39.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:39.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:39.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.20:23:39.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.20:23:39.21$vck44/valo=5,734.99 2006.201.20:23:39.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.20:23:39.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.20:23:39.21#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:39.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:39.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:39.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:39.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:23:39.21#ibcon#first serial, iclass 27, count 0 2006.201.20:23:39.21#ibcon#enter sib2, iclass 27, count 0 2006.201.20:23:39.21#ibcon#flushed, iclass 27, count 0 2006.201.20:23:39.21#ibcon#about to write, iclass 27, count 0 2006.201.20:23:39.21#ibcon#wrote, iclass 27, count 0 2006.201.20:23:39.21#ibcon#about to read 3, iclass 27, count 0 2006.201.20:23:39.23#ibcon#read 3, iclass 27, count 0 2006.201.20:23:39.23#ibcon#about to read 4, iclass 27, count 0 2006.201.20:23:39.23#ibcon#read 4, iclass 27, count 0 2006.201.20:23:39.23#ibcon#about to read 5, iclass 27, count 0 2006.201.20:23:39.23#ibcon#read 5, iclass 27, count 0 2006.201.20:23:39.23#ibcon#about to read 6, iclass 27, count 0 2006.201.20:23:39.23#ibcon#read 6, iclass 27, count 0 2006.201.20:23:39.23#ibcon#end of sib2, iclass 27, count 0 2006.201.20:23:39.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:23:39.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:23:39.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:23:39.23#ibcon#*before write, iclass 27, count 0 2006.201.20:23:39.23#ibcon#enter sib2, iclass 27, count 0 2006.201.20:23:39.23#ibcon#flushed, iclass 27, count 0 2006.201.20:23:39.23#ibcon#about to write, iclass 27, count 0 2006.201.20:23:39.23#ibcon#wrote, iclass 27, count 0 2006.201.20:23:39.23#ibcon#about to read 3, iclass 27, count 0 2006.201.20:23:39.27#ibcon#read 3, iclass 27, count 0 2006.201.20:23:39.27#ibcon#about to read 4, iclass 27, count 0 2006.201.20:23:39.27#ibcon#read 4, iclass 27, count 0 2006.201.20:23:39.27#ibcon#about to read 5, iclass 27, count 0 2006.201.20:23:39.27#ibcon#read 5, iclass 27, count 0 2006.201.20:23:39.27#ibcon#about to read 6, iclass 27, count 0 2006.201.20:23:39.27#ibcon#read 6, iclass 27, count 0 2006.201.20:23:39.27#ibcon#end of sib2, iclass 27, count 0 2006.201.20:23:39.27#ibcon#*after write, iclass 27, count 0 2006.201.20:23:39.27#ibcon#*before return 0, iclass 27, count 0 2006.201.20:23:39.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:39.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:39.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:23:39.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:23:39.27$vck44/va=5,4 2006.201.20:23:39.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.20:23:39.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.20:23:39.27#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:39.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:39.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:39.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:39.33#ibcon#enter wrdev, iclass 29, count 2 2006.201.20:23:39.33#ibcon#first serial, iclass 29, count 2 2006.201.20:23:39.33#ibcon#enter sib2, iclass 29, count 2 2006.201.20:23:39.33#ibcon#flushed, iclass 29, count 2 2006.201.20:23:39.33#ibcon#about to write, iclass 29, count 2 2006.201.20:23:39.33#ibcon#wrote, iclass 29, count 2 2006.201.20:23:39.33#ibcon#about to read 3, iclass 29, count 2 2006.201.20:23:39.35#ibcon#read 3, iclass 29, count 2 2006.201.20:23:39.35#ibcon#about to read 4, iclass 29, count 2 2006.201.20:23:39.35#ibcon#read 4, iclass 29, count 2 2006.201.20:23:39.35#ibcon#about to read 5, iclass 29, count 2 2006.201.20:23:39.35#ibcon#read 5, iclass 29, count 2 2006.201.20:23:39.35#ibcon#about to read 6, iclass 29, count 2 2006.201.20:23:39.35#ibcon#read 6, iclass 29, count 2 2006.201.20:23:39.35#ibcon#end of sib2, iclass 29, count 2 2006.201.20:23:39.35#ibcon#*mode == 0, iclass 29, count 2 2006.201.20:23:39.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.20:23:39.35#ibcon#[25=AT05-04\r\n] 2006.201.20:23:39.35#ibcon#*before write, iclass 29, count 2 2006.201.20:23:39.35#ibcon#enter sib2, iclass 29, count 2 2006.201.20:23:39.35#ibcon#flushed, iclass 29, count 2 2006.201.20:23:39.35#ibcon#about to write, iclass 29, count 2 2006.201.20:23:39.35#ibcon#wrote, iclass 29, count 2 2006.201.20:23:39.35#ibcon#about to read 3, iclass 29, count 2 2006.201.20:23:39.38#ibcon#read 3, iclass 29, count 2 2006.201.20:23:39.38#ibcon#about to read 4, iclass 29, count 2 2006.201.20:23:39.38#ibcon#read 4, iclass 29, count 2 2006.201.20:23:39.38#ibcon#about to read 5, iclass 29, count 2 2006.201.20:23:39.38#ibcon#read 5, iclass 29, count 2 2006.201.20:23:39.38#ibcon#about to read 6, iclass 29, count 2 2006.201.20:23:39.38#ibcon#read 6, iclass 29, count 2 2006.201.20:23:39.38#ibcon#end of sib2, iclass 29, count 2 2006.201.20:23:39.38#ibcon#*after write, iclass 29, count 2 2006.201.20:23:39.38#ibcon#*before return 0, iclass 29, count 2 2006.201.20:23:39.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:39.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:39.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.20:23:39.38#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:39.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:39.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:39.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:39.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.20:23:39.50#ibcon#first serial, iclass 29, count 0 2006.201.20:23:39.50#ibcon#enter sib2, iclass 29, count 0 2006.201.20:23:39.50#ibcon#flushed, iclass 29, count 0 2006.201.20:23:39.50#ibcon#about to write, iclass 29, count 0 2006.201.20:23:39.50#ibcon#wrote, iclass 29, count 0 2006.201.20:23:39.50#ibcon#about to read 3, iclass 29, count 0 2006.201.20:23:39.52#ibcon#read 3, iclass 29, count 0 2006.201.20:23:39.52#ibcon#about to read 4, iclass 29, count 0 2006.201.20:23:39.52#ibcon#read 4, iclass 29, count 0 2006.201.20:23:39.52#ibcon#about to read 5, iclass 29, count 0 2006.201.20:23:39.52#ibcon#read 5, iclass 29, count 0 2006.201.20:23:39.52#ibcon#about to read 6, iclass 29, count 0 2006.201.20:23:39.52#ibcon#read 6, iclass 29, count 0 2006.201.20:23:39.52#ibcon#end of sib2, iclass 29, count 0 2006.201.20:23:39.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.20:23:39.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.20:23:39.52#ibcon#[25=USB\r\n] 2006.201.20:23:39.52#ibcon#*before write, iclass 29, count 0 2006.201.20:23:39.52#ibcon#enter sib2, iclass 29, count 0 2006.201.20:23:39.52#ibcon#flushed, iclass 29, count 0 2006.201.20:23:39.52#ibcon#about to write, iclass 29, count 0 2006.201.20:23:39.52#ibcon#wrote, iclass 29, count 0 2006.201.20:23:39.52#ibcon#about to read 3, iclass 29, count 0 2006.201.20:23:39.55#ibcon#read 3, iclass 29, count 0 2006.201.20:23:39.55#ibcon#about to read 4, iclass 29, count 0 2006.201.20:23:39.55#ibcon#read 4, iclass 29, count 0 2006.201.20:23:39.55#ibcon#about to read 5, iclass 29, count 0 2006.201.20:23:39.55#ibcon#read 5, iclass 29, count 0 2006.201.20:23:39.55#ibcon#about to read 6, iclass 29, count 0 2006.201.20:23:39.55#ibcon#read 6, iclass 29, count 0 2006.201.20:23:39.55#ibcon#end of sib2, iclass 29, count 0 2006.201.20:23:39.55#ibcon#*after write, iclass 29, count 0 2006.201.20:23:39.55#ibcon#*before return 0, iclass 29, count 0 2006.201.20:23:39.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:39.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:39.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.20:23:39.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.20:23:39.55$vck44/valo=6,814.99 2006.201.20:23:39.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.20:23:39.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.20:23:39.55#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:39.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:39.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:39.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:39.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.20:23:39.55#ibcon#first serial, iclass 31, count 0 2006.201.20:23:39.55#ibcon#enter sib2, iclass 31, count 0 2006.201.20:23:39.55#ibcon#flushed, iclass 31, count 0 2006.201.20:23:39.55#ibcon#about to write, iclass 31, count 0 2006.201.20:23:39.55#ibcon#wrote, iclass 31, count 0 2006.201.20:23:39.55#ibcon#about to read 3, iclass 31, count 0 2006.201.20:23:39.57#ibcon#read 3, iclass 31, count 0 2006.201.20:23:39.57#ibcon#about to read 4, iclass 31, count 0 2006.201.20:23:39.57#ibcon#read 4, iclass 31, count 0 2006.201.20:23:39.57#ibcon#about to read 5, iclass 31, count 0 2006.201.20:23:39.57#ibcon#read 5, iclass 31, count 0 2006.201.20:23:39.57#ibcon#about to read 6, iclass 31, count 0 2006.201.20:23:39.57#ibcon#read 6, iclass 31, count 0 2006.201.20:23:39.57#ibcon#end of sib2, iclass 31, count 0 2006.201.20:23:39.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.20:23:39.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.20:23:39.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:23:39.57#ibcon#*before write, iclass 31, count 0 2006.201.20:23:39.57#ibcon#enter sib2, iclass 31, count 0 2006.201.20:23:39.57#ibcon#flushed, iclass 31, count 0 2006.201.20:23:39.57#ibcon#about to write, iclass 31, count 0 2006.201.20:23:39.57#ibcon#wrote, iclass 31, count 0 2006.201.20:23:39.57#ibcon#about to read 3, iclass 31, count 0 2006.201.20:23:39.61#ibcon#read 3, iclass 31, count 0 2006.201.20:23:39.61#ibcon#about to read 4, iclass 31, count 0 2006.201.20:23:39.61#ibcon#read 4, iclass 31, count 0 2006.201.20:23:39.61#ibcon#about to read 5, iclass 31, count 0 2006.201.20:23:39.61#ibcon#read 5, iclass 31, count 0 2006.201.20:23:39.61#ibcon#about to read 6, iclass 31, count 0 2006.201.20:23:39.61#ibcon#read 6, iclass 31, count 0 2006.201.20:23:39.61#ibcon#end of sib2, iclass 31, count 0 2006.201.20:23:39.61#ibcon#*after write, iclass 31, count 0 2006.201.20:23:39.61#ibcon#*before return 0, iclass 31, count 0 2006.201.20:23:39.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:39.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:39.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.20:23:39.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.20:23:39.61$vck44/va=6,5 2006.201.20:23:39.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.20:23:39.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.20:23:39.61#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:39.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:39.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:39.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:39.67#ibcon#enter wrdev, iclass 33, count 2 2006.201.20:23:39.67#ibcon#first serial, iclass 33, count 2 2006.201.20:23:39.67#ibcon#enter sib2, iclass 33, count 2 2006.201.20:23:39.67#ibcon#flushed, iclass 33, count 2 2006.201.20:23:39.67#ibcon#about to write, iclass 33, count 2 2006.201.20:23:39.67#ibcon#wrote, iclass 33, count 2 2006.201.20:23:39.67#ibcon#about to read 3, iclass 33, count 2 2006.201.20:23:39.69#ibcon#read 3, iclass 33, count 2 2006.201.20:23:39.69#ibcon#about to read 4, iclass 33, count 2 2006.201.20:23:39.69#ibcon#read 4, iclass 33, count 2 2006.201.20:23:39.69#ibcon#about to read 5, iclass 33, count 2 2006.201.20:23:39.69#ibcon#read 5, iclass 33, count 2 2006.201.20:23:39.69#ibcon#about to read 6, iclass 33, count 2 2006.201.20:23:39.69#ibcon#read 6, iclass 33, count 2 2006.201.20:23:39.69#ibcon#end of sib2, iclass 33, count 2 2006.201.20:23:39.69#ibcon#*mode == 0, iclass 33, count 2 2006.201.20:23:39.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.20:23:39.69#ibcon#[25=AT06-05\r\n] 2006.201.20:23:39.69#ibcon#*before write, iclass 33, count 2 2006.201.20:23:39.69#ibcon#enter sib2, iclass 33, count 2 2006.201.20:23:39.69#ibcon#flushed, iclass 33, count 2 2006.201.20:23:39.69#ibcon#about to write, iclass 33, count 2 2006.201.20:23:39.69#ibcon#wrote, iclass 33, count 2 2006.201.20:23:39.69#ibcon#about to read 3, iclass 33, count 2 2006.201.20:23:39.72#ibcon#read 3, iclass 33, count 2 2006.201.20:23:39.72#ibcon#about to read 4, iclass 33, count 2 2006.201.20:23:39.72#ibcon#read 4, iclass 33, count 2 2006.201.20:23:39.72#ibcon#about to read 5, iclass 33, count 2 2006.201.20:23:39.72#ibcon#read 5, iclass 33, count 2 2006.201.20:23:39.72#ibcon#about to read 6, iclass 33, count 2 2006.201.20:23:39.72#ibcon#read 6, iclass 33, count 2 2006.201.20:23:39.72#ibcon#end of sib2, iclass 33, count 2 2006.201.20:23:39.72#ibcon#*after write, iclass 33, count 2 2006.201.20:23:39.72#ibcon#*before return 0, iclass 33, count 2 2006.201.20:23:39.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:39.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:39.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.20:23:39.72#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:39.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:39.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:39.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:39.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.20:23:39.84#ibcon#first serial, iclass 33, count 0 2006.201.20:23:39.84#ibcon#enter sib2, iclass 33, count 0 2006.201.20:23:39.84#ibcon#flushed, iclass 33, count 0 2006.201.20:23:39.84#ibcon#about to write, iclass 33, count 0 2006.201.20:23:39.84#ibcon#wrote, iclass 33, count 0 2006.201.20:23:39.84#ibcon#about to read 3, iclass 33, count 0 2006.201.20:23:39.86#ibcon#read 3, iclass 33, count 0 2006.201.20:23:39.86#ibcon#about to read 4, iclass 33, count 0 2006.201.20:23:39.86#ibcon#read 4, iclass 33, count 0 2006.201.20:23:39.86#ibcon#about to read 5, iclass 33, count 0 2006.201.20:23:39.86#ibcon#read 5, iclass 33, count 0 2006.201.20:23:39.86#ibcon#about to read 6, iclass 33, count 0 2006.201.20:23:39.86#ibcon#read 6, iclass 33, count 0 2006.201.20:23:39.86#ibcon#end of sib2, iclass 33, count 0 2006.201.20:23:39.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.20:23:39.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.20:23:39.86#ibcon#[25=USB\r\n] 2006.201.20:23:39.86#ibcon#*before write, iclass 33, count 0 2006.201.20:23:39.86#ibcon#enter sib2, iclass 33, count 0 2006.201.20:23:39.86#ibcon#flushed, iclass 33, count 0 2006.201.20:23:39.86#ibcon#about to write, iclass 33, count 0 2006.201.20:23:39.86#ibcon#wrote, iclass 33, count 0 2006.201.20:23:39.86#ibcon#about to read 3, iclass 33, count 0 2006.201.20:23:39.89#ibcon#read 3, iclass 33, count 0 2006.201.20:23:39.89#ibcon#about to read 4, iclass 33, count 0 2006.201.20:23:39.89#ibcon#read 4, iclass 33, count 0 2006.201.20:23:39.89#ibcon#about to read 5, iclass 33, count 0 2006.201.20:23:39.89#ibcon#read 5, iclass 33, count 0 2006.201.20:23:39.89#ibcon#about to read 6, iclass 33, count 0 2006.201.20:23:39.89#ibcon#read 6, iclass 33, count 0 2006.201.20:23:39.89#ibcon#end of sib2, iclass 33, count 0 2006.201.20:23:39.89#ibcon#*after write, iclass 33, count 0 2006.201.20:23:39.89#ibcon#*before return 0, iclass 33, count 0 2006.201.20:23:39.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:39.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:39.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.20:23:39.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.20:23:39.89$vck44/valo=7,864.99 2006.201.20:23:39.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.20:23:39.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.20:23:39.89#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:39.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:39.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:39.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:39.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.20:23:39.89#ibcon#first serial, iclass 35, count 0 2006.201.20:23:39.89#ibcon#enter sib2, iclass 35, count 0 2006.201.20:23:39.89#ibcon#flushed, iclass 35, count 0 2006.201.20:23:39.89#ibcon#about to write, iclass 35, count 0 2006.201.20:23:39.89#ibcon#wrote, iclass 35, count 0 2006.201.20:23:39.89#ibcon#about to read 3, iclass 35, count 0 2006.201.20:23:39.91#ibcon#read 3, iclass 35, count 0 2006.201.20:23:39.91#ibcon#about to read 4, iclass 35, count 0 2006.201.20:23:39.91#ibcon#read 4, iclass 35, count 0 2006.201.20:23:39.91#ibcon#about to read 5, iclass 35, count 0 2006.201.20:23:39.91#ibcon#read 5, iclass 35, count 0 2006.201.20:23:39.91#ibcon#about to read 6, iclass 35, count 0 2006.201.20:23:39.91#ibcon#read 6, iclass 35, count 0 2006.201.20:23:39.91#ibcon#end of sib2, iclass 35, count 0 2006.201.20:23:39.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.20:23:39.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.20:23:39.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:23:39.91#ibcon#*before write, iclass 35, count 0 2006.201.20:23:39.91#ibcon#enter sib2, iclass 35, count 0 2006.201.20:23:39.91#ibcon#flushed, iclass 35, count 0 2006.201.20:23:39.91#ibcon#about to write, iclass 35, count 0 2006.201.20:23:39.91#ibcon#wrote, iclass 35, count 0 2006.201.20:23:39.91#ibcon#about to read 3, iclass 35, count 0 2006.201.20:23:39.95#ibcon#read 3, iclass 35, count 0 2006.201.20:23:39.95#ibcon#about to read 4, iclass 35, count 0 2006.201.20:23:39.95#ibcon#read 4, iclass 35, count 0 2006.201.20:23:39.95#ibcon#about to read 5, iclass 35, count 0 2006.201.20:23:39.95#ibcon#read 5, iclass 35, count 0 2006.201.20:23:39.95#ibcon#about to read 6, iclass 35, count 0 2006.201.20:23:39.95#ibcon#read 6, iclass 35, count 0 2006.201.20:23:39.95#ibcon#end of sib2, iclass 35, count 0 2006.201.20:23:39.95#ibcon#*after write, iclass 35, count 0 2006.201.20:23:39.95#ibcon#*before return 0, iclass 35, count 0 2006.201.20:23:39.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:39.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:39.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.20:23:39.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.20:23:39.95$vck44/va=7,5 2006.201.20:23:39.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.20:23:39.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.20:23:39.95#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:39.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:40.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:40.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:40.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.20:23:40.01#ibcon#first serial, iclass 37, count 2 2006.201.20:23:40.01#ibcon#enter sib2, iclass 37, count 2 2006.201.20:23:40.01#ibcon#flushed, iclass 37, count 2 2006.201.20:23:40.01#ibcon#about to write, iclass 37, count 2 2006.201.20:23:40.01#ibcon#wrote, iclass 37, count 2 2006.201.20:23:40.01#ibcon#about to read 3, iclass 37, count 2 2006.201.20:23:40.03#ibcon#read 3, iclass 37, count 2 2006.201.20:23:40.03#ibcon#about to read 4, iclass 37, count 2 2006.201.20:23:40.03#ibcon#read 4, iclass 37, count 2 2006.201.20:23:40.03#ibcon#about to read 5, iclass 37, count 2 2006.201.20:23:40.03#ibcon#read 5, iclass 37, count 2 2006.201.20:23:40.03#ibcon#about to read 6, iclass 37, count 2 2006.201.20:23:40.03#ibcon#read 6, iclass 37, count 2 2006.201.20:23:40.03#ibcon#end of sib2, iclass 37, count 2 2006.201.20:23:40.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.20:23:40.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.20:23:40.03#ibcon#[25=AT07-05\r\n] 2006.201.20:23:40.03#ibcon#*before write, iclass 37, count 2 2006.201.20:23:40.03#ibcon#enter sib2, iclass 37, count 2 2006.201.20:23:40.03#ibcon#flushed, iclass 37, count 2 2006.201.20:23:40.03#ibcon#about to write, iclass 37, count 2 2006.201.20:23:40.03#ibcon#wrote, iclass 37, count 2 2006.201.20:23:40.03#ibcon#about to read 3, iclass 37, count 2 2006.201.20:23:40.06#ibcon#read 3, iclass 37, count 2 2006.201.20:23:40.06#ibcon#about to read 4, iclass 37, count 2 2006.201.20:23:40.06#ibcon#read 4, iclass 37, count 2 2006.201.20:23:40.06#ibcon#about to read 5, iclass 37, count 2 2006.201.20:23:40.06#ibcon#read 5, iclass 37, count 2 2006.201.20:23:40.06#ibcon#about to read 6, iclass 37, count 2 2006.201.20:23:40.06#ibcon#read 6, iclass 37, count 2 2006.201.20:23:40.06#ibcon#end of sib2, iclass 37, count 2 2006.201.20:23:40.06#ibcon#*after write, iclass 37, count 2 2006.201.20:23:40.06#ibcon#*before return 0, iclass 37, count 2 2006.201.20:23:40.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:40.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:40.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.20:23:40.06#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:40.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:40.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:40.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:40.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.20:23:40.18#ibcon#first serial, iclass 37, count 0 2006.201.20:23:40.18#ibcon#enter sib2, iclass 37, count 0 2006.201.20:23:40.18#ibcon#flushed, iclass 37, count 0 2006.201.20:23:40.18#ibcon#about to write, iclass 37, count 0 2006.201.20:23:40.18#ibcon#wrote, iclass 37, count 0 2006.201.20:23:40.18#ibcon#about to read 3, iclass 37, count 0 2006.201.20:23:40.20#ibcon#read 3, iclass 37, count 0 2006.201.20:23:40.20#ibcon#about to read 4, iclass 37, count 0 2006.201.20:23:40.20#ibcon#read 4, iclass 37, count 0 2006.201.20:23:40.20#ibcon#about to read 5, iclass 37, count 0 2006.201.20:23:40.20#ibcon#read 5, iclass 37, count 0 2006.201.20:23:40.20#ibcon#about to read 6, iclass 37, count 0 2006.201.20:23:40.20#ibcon#read 6, iclass 37, count 0 2006.201.20:23:40.20#ibcon#end of sib2, iclass 37, count 0 2006.201.20:23:40.20#ibcon#*mode == 0, iclass 37, count 0 2006.201.20:23:40.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.20:23:40.20#ibcon#[25=USB\r\n] 2006.201.20:23:40.20#ibcon#*before write, iclass 37, count 0 2006.201.20:23:40.20#ibcon#enter sib2, iclass 37, count 0 2006.201.20:23:40.20#ibcon#flushed, iclass 37, count 0 2006.201.20:23:40.20#ibcon#about to write, iclass 37, count 0 2006.201.20:23:40.20#ibcon#wrote, iclass 37, count 0 2006.201.20:23:40.20#ibcon#about to read 3, iclass 37, count 0 2006.201.20:23:40.23#ibcon#read 3, iclass 37, count 0 2006.201.20:23:40.23#ibcon#about to read 4, iclass 37, count 0 2006.201.20:23:40.23#ibcon#read 4, iclass 37, count 0 2006.201.20:23:40.23#ibcon#about to read 5, iclass 37, count 0 2006.201.20:23:40.23#ibcon#read 5, iclass 37, count 0 2006.201.20:23:40.23#ibcon#about to read 6, iclass 37, count 0 2006.201.20:23:40.23#ibcon#read 6, iclass 37, count 0 2006.201.20:23:40.23#ibcon#end of sib2, iclass 37, count 0 2006.201.20:23:40.23#ibcon#*after write, iclass 37, count 0 2006.201.20:23:40.23#ibcon#*before return 0, iclass 37, count 0 2006.201.20:23:40.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:40.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:40.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.20:23:40.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.20:23:40.23$vck44/valo=8,884.99 2006.201.20:23:40.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.20:23:40.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.20:23:40.23#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:40.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:40.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:40.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:40.23#ibcon#enter wrdev, iclass 39, count 0 2006.201.20:23:40.23#ibcon#first serial, iclass 39, count 0 2006.201.20:23:40.23#ibcon#enter sib2, iclass 39, count 0 2006.201.20:23:40.23#ibcon#flushed, iclass 39, count 0 2006.201.20:23:40.23#ibcon#about to write, iclass 39, count 0 2006.201.20:23:40.23#ibcon#wrote, iclass 39, count 0 2006.201.20:23:40.23#ibcon#about to read 3, iclass 39, count 0 2006.201.20:23:40.25#ibcon#read 3, iclass 39, count 0 2006.201.20:23:40.25#ibcon#about to read 4, iclass 39, count 0 2006.201.20:23:40.25#ibcon#read 4, iclass 39, count 0 2006.201.20:23:40.25#ibcon#about to read 5, iclass 39, count 0 2006.201.20:23:40.25#ibcon#read 5, iclass 39, count 0 2006.201.20:23:40.25#ibcon#about to read 6, iclass 39, count 0 2006.201.20:23:40.25#ibcon#read 6, iclass 39, count 0 2006.201.20:23:40.25#ibcon#end of sib2, iclass 39, count 0 2006.201.20:23:40.25#ibcon#*mode == 0, iclass 39, count 0 2006.201.20:23:40.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.20:23:40.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:23:40.25#ibcon#*before write, iclass 39, count 0 2006.201.20:23:40.25#ibcon#enter sib2, iclass 39, count 0 2006.201.20:23:40.25#ibcon#flushed, iclass 39, count 0 2006.201.20:23:40.25#ibcon#about to write, iclass 39, count 0 2006.201.20:23:40.25#ibcon#wrote, iclass 39, count 0 2006.201.20:23:40.25#ibcon#about to read 3, iclass 39, count 0 2006.201.20:23:40.29#ibcon#read 3, iclass 39, count 0 2006.201.20:23:40.29#ibcon#about to read 4, iclass 39, count 0 2006.201.20:23:40.29#ibcon#read 4, iclass 39, count 0 2006.201.20:23:40.29#ibcon#about to read 5, iclass 39, count 0 2006.201.20:23:40.29#ibcon#read 5, iclass 39, count 0 2006.201.20:23:40.29#ibcon#about to read 6, iclass 39, count 0 2006.201.20:23:40.29#ibcon#read 6, iclass 39, count 0 2006.201.20:23:40.29#ibcon#end of sib2, iclass 39, count 0 2006.201.20:23:40.29#ibcon#*after write, iclass 39, count 0 2006.201.20:23:40.29#ibcon#*before return 0, iclass 39, count 0 2006.201.20:23:40.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:40.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:40.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.20:23:40.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.20:23:40.29$vck44/va=8,4 2006.201.20:23:40.29#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.20:23:40.29#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.20:23:40.29#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:40.29#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:23:40.35#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:23:40.35#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:23:40.35#ibcon#enter wrdev, iclass 2, count 2 2006.201.20:23:40.35#ibcon#first serial, iclass 2, count 2 2006.201.20:23:40.35#ibcon#enter sib2, iclass 2, count 2 2006.201.20:23:40.35#ibcon#flushed, iclass 2, count 2 2006.201.20:23:40.35#ibcon#about to write, iclass 2, count 2 2006.201.20:23:40.35#ibcon#wrote, iclass 2, count 2 2006.201.20:23:40.35#ibcon#about to read 3, iclass 2, count 2 2006.201.20:23:40.37#ibcon#read 3, iclass 2, count 2 2006.201.20:23:40.37#ibcon#about to read 4, iclass 2, count 2 2006.201.20:23:40.37#ibcon#read 4, iclass 2, count 2 2006.201.20:23:40.37#ibcon#about to read 5, iclass 2, count 2 2006.201.20:23:40.37#ibcon#read 5, iclass 2, count 2 2006.201.20:23:40.37#ibcon#about to read 6, iclass 2, count 2 2006.201.20:23:40.37#ibcon#read 6, iclass 2, count 2 2006.201.20:23:40.37#ibcon#end of sib2, iclass 2, count 2 2006.201.20:23:40.37#ibcon#*mode == 0, iclass 2, count 2 2006.201.20:23:40.37#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.20:23:40.37#ibcon#[25=AT08-04\r\n] 2006.201.20:23:40.37#ibcon#*before write, iclass 2, count 2 2006.201.20:23:40.37#ibcon#enter sib2, iclass 2, count 2 2006.201.20:23:40.37#ibcon#flushed, iclass 2, count 2 2006.201.20:23:40.37#ibcon#about to write, iclass 2, count 2 2006.201.20:23:40.37#ibcon#wrote, iclass 2, count 2 2006.201.20:23:40.37#ibcon#about to read 3, iclass 2, count 2 2006.201.20:23:40.40#ibcon#read 3, iclass 2, count 2 2006.201.20:23:40.40#ibcon#about to read 4, iclass 2, count 2 2006.201.20:23:40.40#ibcon#read 4, iclass 2, count 2 2006.201.20:23:40.40#ibcon#about to read 5, iclass 2, count 2 2006.201.20:23:40.40#ibcon#read 5, iclass 2, count 2 2006.201.20:23:40.40#ibcon#about to read 6, iclass 2, count 2 2006.201.20:23:40.40#ibcon#read 6, iclass 2, count 2 2006.201.20:23:40.40#ibcon#end of sib2, iclass 2, count 2 2006.201.20:23:40.40#ibcon#*after write, iclass 2, count 2 2006.201.20:23:40.40#ibcon#*before return 0, iclass 2, count 2 2006.201.20:23:40.40#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:23:40.40#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:23:40.40#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.20:23:40.40#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:40.40#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:23:40.52#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:23:40.52#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:23:40.52#ibcon#enter wrdev, iclass 2, count 0 2006.201.20:23:40.52#ibcon#first serial, iclass 2, count 0 2006.201.20:23:40.52#ibcon#enter sib2, iclass 2, count 0 2006.201.20:23:40.52#ibcon#flushed, iclass 2, count 0 2006.201.20:23:40.52#ibcon#about to write, iclass 2, count 0 2006.201.20:23:40.52#ibcon#wrote, iclass 2, count 0 2006.201.20:23:40.52#ibcon#about to read 3, iclass 2, count 0 2006.201.20:23:40.54#ibcon#read 3, iclass 2, count 0 2006.201.20:23:40.54#ibcon#about to read 4, iclass 2, count 0 2006.201.20:23:40.54#ibcon#read 4, iclass 2, count 0 2006.201.20:23:40.54#ibcon#about to read 5, iclass 2, count 0 2006.201.20:23:40.54#ibcon#read 5, iclass 2, count 0 2006.201.20:23:40.54#ibcon#about to read 6, iclass 2, count 0 2006.201.20:23:40.54#ibcon#read 6, iclass 2, count 0 2006.201.20:23:40.54#ibcon#end of sib2, iclass 2, count 0 2006.201.20:23:40.54#ibcon#*mode == 0, iclass 2, count 0 2006.201.20:23:40.54#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.20:23:40.54#ibcon#[25=USB\r\n] 2006.201.20:23:40.54#ibcon#*before write, iclass 2, count 0 2006.201.20:23:40.54#ibcon#enter sib2, iclass 2, count 0 2006.201.20:23:40.54#ibcon#flushed, iclass 2, count 0 2006.201.20:23:40.54#ibcon#about to write, iclass 2, count 0 2006.201.20:23:40.54#ibcon#wrote, iclass 2, count 0 2006.201.20:23:40.54#ibcon#about to read 3, iclass 2, count 0 2006.201.20:23:40.57#ibcon#read 3, iclass 2, count 0 2006.201.20:23:40.57#ibcon#about to read 4, iclass 2, count 0 2006.201.20:23:40.57#ibcon#read 4, iclass 2, count 0 2006.201.20:23:40.57#ibcon#about to read 5, iclass 2, count 0 2006.201.20:23:40.57#ibcon#read 5, iclass 2, count 0 2006.201.20:23:40.57#ibcon#about to read 6, iclass 2, count 0 2006.201.20:23:40.57#ibcon#read 6, iclass 2, count 0 2006.201.20:23:40.57#ibcon#end of sib2, iclass 2, count 0 2006.201.20:23:40.57#ibcon#*after write, iclass 2, count 0 2006.201.20:23:40.57#ibcon#*before return 0, iclass 2, count 0 2006.201.20:23:40.57#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:23:40.57#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:23:40.57#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.20:23:40.57#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.20:23:40.57$vck44/vblo=1,629.99 2006.201.20:23:40.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.20:23:40.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.20:23:40.57#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:40.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:23:40.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:23:40.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:23:40.57#ibcon#enter wrdev, iclass 5, count 0 2006.201.20:23:40.57#ibcon#first serial, iclass 5, count 0 2006.201.20:23:40.57#ibcon#enter sib2, iclass 5, count 0 2006.201.20:23:40.57#ibcon#flushed, iclass 5, count 0 2006.201.20:23:40.57#ibcon#about to write, iclass 5, count 0 2006.201.20:23:40.57#ibcon#wrote, iclass 5, count 0 2006.201.20:23:40.57#ibcon#about to read 3, iclass 5, count 0 2006.201.20:23:40.59#ibcon#read 3, iclass 5, count 0 2006.201.20:23:40.59#ibcon#about to read 4, iclass 5, count 0 2006.201.20:23:40.59#ibcon#read 4, iclass 5, count 0 2006.201.20:23:40.59#ibcon#about to read 5, iclass 5, count 0 2006.201.20:23:40.59#ibcon#read 5, iclass 5, count 0 2006.201.20:23:40.59#ibcon#about to read 6, iclass 5, count 0 2006.201.20:23:40.59#ibcon#read 6, iclass 5, count 0 2006.201.20:23:40.59#ibcon#end of sib2, iclass 5, count 0 2006.201.20:23:40.59#ibcon#*mode == 0, iclass 5, count 0 2006.201.20:23:40.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.20:23:40.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:23:40.59#ibcon#*before write, iclass 5, count 0 2006.201.20:23:40.59#ibcon#enter sib2, iclass 5, count 0 2006.201.20:23:40.59#ibcon#flushed, iclass 5, count 0 2006.201.20:23:40.59#ibcon#about to write, iclass 5, count 0 2006.201.20:23:40.59#ibcon#wrote, iclass 5, count 0 2006.201.20:23:40.59#ibcon#about to read 3, iclass 5, count 0 2006.201.20:23:40.63#ibcon#read 3, iclass 5, count 0 2006.201.20:23:40.63#ibcon#about to read 4, iclass 5, count 0 2006.201.20:23:40.63#ibcon#read 4, iclass 5, count 0 2006.201.20:23:40.63#ibcon#about to read 5, iclass 5, count 0 2006.201.20:23:40.63#ibcon#read 5, iclass 5, count 0 2006.201.20:23:40.63#ibcon#about to read 6, iclass 5, count 0 2006.201.20:23:40.63#ibcon#read 6, iclass 5, count 0 2006.201.20:23:40.63#ibcon#end of sib2, iclass 5, count 0 2006.201.20:23:40.63#ibcon#*after write, iclass 5, count 0 2006.201.20:23:40.63#ibcon#*before return 0, iclass 5, count 0 2006.201.20:23:40.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:23:40.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:23:40.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.20:23:40.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.20:23:40.63$vck44/vb=1,4 2006.201.20:23:40.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.20:23:40.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.20:23:40.63#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:40.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:23:40.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:23:40.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:23:40.63#ibcon#enter wrdev, iclass 7, count 2 2006.201.20:23:40.63#ibcon#first serial, iclass 7, count 2 2006.201.20:23:40.63#ibcon#enter sib2, iclass 7, count 2 2006.201.20:23:40.63#ibcon#flushed, iclass 7, count 2 2006.201.20:23:40.63#ibcon#about to write, iclass 7, count 2 2006.201.20:23:40.63#ibcon#wrote, iclass 7, count 2 2006.201.20:23:40.63#ibcon#about to read 3, iclass 7, count 2 2006.201.20:23:40.65#ibcon#read 3, iclass 7, count 2 2006.201.20:23:40.65#ibcon#about to read 4, iclass 7, count 2 2006.201.20:23:40.65#ibcon#read 4, iclass 7, count 2 2006.201.20:23:40.65#ibcon#about to read 5, iclass 7, count 2 2006.201.20:23:40.65#ibcon#read 5, iclass 7, count 2 2006.201.20:23:40.65#ibcon#about to read 6, iclass 7, count 2 2006.201.20:23:40.65#ibcon#read 6, iclass 7, count 2 2006.201.20:23:40.65#ibcon#end of sib2, iclass 7, count 2 2006.201.20:23:40.65#ibcon#*mode == 0, iclass 7, count 2 2006.201.20:23:40.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.20:23:40.65#ibcon#[27=AT01-04\r\n] 2006.201.20:23:40.65#ibcon#*before write, iclass 7, count 2 2006.201.20:23:40.65#ibcon#enter sib2, iclass 7, count 2 2006.201.20:23:40.65#ibcon#flushed, iclass 7, count 2 2006.201.20:23:40.65#ibcon#about to write, iclass 7, count 2 2006.201.20:23:40.65#ibcon#wrote, iclass 7, count 2 2006.201.20:23:40.65#ibcon#about to read 3, iclass 7, count 2 2006.201.20:23:40.68#ibcon#read 3, iclass 7, count 2 2006.201.20:23:40.68#ibcon#about to read 4, iclass 7, count 2 2006.201.20:23:40.68#ibcon#read 4, iclass 7, count 2 2006.201.20:23:40.68#ibcon#about to read 5, iclass 7, count 2 2006.201.20:23:40.68#ibcon#read 5, iclass 7, count 2 2006.201.20:23:40.68#ibcon#about to read 6, iclass 7, count 2 2006.201.20:23:40.68#ibcon#read 6, iclass 7, count 2 2006.201.20:23:40.68#ibcon#end of sib2, iclass 7, count 2 2006.201.20:23:40.68#ibcon#*after write, iclass 7, count 2 2006.201.20:23:40.68#ibcon#*before return 0, iclass 7, count 2 2006.201.20:23:40.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:23:40.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:23:40.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.20:23:40.68#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:40.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:23:40.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:23:40.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:23:40.80#ibcon#enter wrdev, iclass 7, count 0 2006.201.20:23:40.80#ibcon#first serial, iclass 7, count 0 2006.201.20:23:40.80#ibcon#enter sib2, iclass 7, count 0 2006.201.20:23:40.80#ibcon#flushed, iclass 7, count 0 2006.201.20:23:40.80#ibcon#about to write, iclass 7, count 0 2006.201.20:23:40.80#ibcon#wrote, iclass 7, count 0 2006.201.20:23:40.80#ibcon#about to read 3, iclass 7, count 0 2006.201.20:23:40.82#ibcon#read 3, iclass 7, count 0 2006.201.20:23:40.82#ibcon#about to read 4, iclass 7, count 0 2006.201.20:23:40.82#ibcon#read 4, iclass 7, count 0 2006.201.20:23:40.82#ibcon#about to read 5, iclass 7, count 0 2006.201.20:23:40.82#ibcon#read 5, iclass 7, count 0 2006.201.20:23:40.82#ibcon#about to read 6, iclass 7, count 0 2006.201.20:23:40.82#ibcon#read 6, iclass 7, count 0 2006.201.20:23:40.82#ibcon#end of sib2, iclass 7, count 0 2006.201.20:23:40.82#ibcon#*mode == 0, iclass 7, count 0 2006.201.20:23:40.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.20:23:40.82#ibcon#[27=USB\r\n] 2006.201.20:23:40.82#ibcon#*before write, iclass 7, count 0 2006.201.20:23:40.82#ibcon#enter sib2, iclass 7, count 0 2006.201.20:23:40.82#ibcon#flushed, iclass 7, count 0 2006.201.20:23:40.82#ibcon#about to write, iclass 7, count 0 2006.201.20:23:40.82#ibcon#wrote, iclass 7, count 0 2006.201.20:23:40.82#ibcon#about to read 3, iclass 7, count 0 2006.201.20:23:40.85#ibcon#read 3, iclass 7, count 0 2006.201.20:23:40.85#ibcon#about to read 4, iclass 7, count 0 2006.201.20:23:40.85#ibcon#read 4, iclass 7, count 0 2006.201.20:23:40.85#ibcon#about to read 5, iclass 7, count 0 2006.201.20:23:40.85#ibcon#read 5, iclass 7, count 0 2006.201.20:23:40.85#ibcon#about to read 6, iclass 7, count 0 2006.201.20:23:40.85#ibcon#read 6, iclass 7, count 0 2006.201.20:23:40.85#ibcon#end of sib2, iclass 7, count 0 2006.201.20:23:40.85#ibcon#*after write, iclass 7, count 0 2006.201.20:23:40.85#ibcon#*before return 0, iclass 7, count 0 2006.201.20:23:40.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:23:40.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:23:40.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.20:23:40.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.20:23:40.85$vck44/vblo=2,634.99 2006.201.20:23:40.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.20:23:40.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.20:23:40.85#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:40.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:40.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:40.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:40.85#ibcon#enter wrdev, iclass 11, count 0 2006.201.20:23:40.85#ibcon#first serial, iclass 11, count 0 2006.201.20:23:40.85#ibcon#enter sib2, iclass 11, count 0 2006.201.20:23:40.85#ibcon#flushed, iclass 11, count 0 2006.201.20:23:40.85#ibcon#about to write, iclass 11, count 0 2006.201.20:23:40.85#ibcon#wrote, iclass 11, count 0 2006.201.20:23:40.85#ibcon#about to read 3, iclass 11, count 0 2006.201.20:23:40.87#ibcon#read 3, iclass 11, count 0 2006.201.20:23:40.87#ibcon#about to read 4, iclass 11, count 0 2006.201.20:23:40.87#ibcon#read 4, iclass 11, count 0 2006.201.20:23:40.87#ibcon#about to read 5, iclass 11, count 0 2006.201.20:23:40.87#ibcon#read 5, iclass 11, count 0 2006.201.20:23:40.87#ibcon#about to read 6, iclass 11, count 0 2006.201.20:23:40.87#ibcon#read 6, iclass 11, count 0 2006.201.20:23:40.87#ibcon#end of sib2, iclass 11, count 0 2006.201.20:23:40.87#ibcon#*mode == 0, iclass 11, count 0 2006.201.20:23:40.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.20:23:40.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:23:40.87#ibcon#*before write, iclass 11, count 0 2006.201.20:23:40.87#ibcon#enter sib2, iclass 11, count 0 2006.201.20:23:40.87#ibcon#flushed, iclass 11, count 0 2006.201.20:23:40.87#ibcon#about to write, iclass 11, count 0 2006.201.20:23:40.87#ibcon#wrote, iclass 11, count 0 2006.201.20:23:40.87#ibcon#about to read 3, iclass 11, count 0 2006.201.20:23:40.91#ibcon#read 3, iclass 11, count 0 2006.201.20:23:40.91#ibcon#about to read 4, iclass 11, count 0 2006.201.20:23:40.91#ibcon#read 4, iclass 11, count 0 2006.201.20:23:40.91#ibcon#about to read 5, iclass 11, count 0 2006.201.20:23:40.91#ibcon#read 5, iclass 11, count 0 2006.201.20:23:40.91#ibcon#about to read 6, iclass 11, count 0 2006.201.20:23:40.91#ibcon#read 6, iclass 11, count 0 2006.201.20:23:40.91#ibcon#end of sib2, iclass 11, count 0 2006.201.20:23:40.91#ibcon#*after write, iclass 11, count 0 2006.201.20:23:40.91#ibcon#*before return 0, iclass 11, count 0 2006.201.20:23:40.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:40.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:23:40.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.20:23:40.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.20:23:40.91$vck44/vb=2,5 2006.201.20:23:40.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.20:23:40.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.20:23:40.91#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:40.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:40.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:40.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:40.97#ibcon#enter wrdev, iclass 13, count 2 2006.201.20:23:40.97#ibcon#first serial, iclass 13, count 2 2006.201.20:23:40.97#ibcon#enter sib2, iclass 13, count 2 2006.201.20:23:40.97#ibcon#flushed, iclass 13, count 2 2006.201.20:23:40.97#ibcon#about to write, iclass 13, count 2 2006.201.20:23:40.97#ibcon#wrote, iclass 13, count 2 2006.201.20:23:40.97#ibcon#about to read 3, iclass 13, count 2 2006.201.20:23:40.99#ibcon#read 3, iclass 13, count 2 2006.201.20:23:40.99#ibcon#about to read 4, iclass 13, count 2 2006.201.20:23:40.99#ibcon#read 4, iclass 13, count 2 2006.201.20:23:40.99#ibcon#about to read 5, iclass 13, count 2 2006.201.20:23:40.99#ibcon#read 5, iclass 13, count 2 2006.201.20:23:40.99#ibcon#about to read 6, iclass 13, count 2 2006.201.20:23:40.99#ibcon#read 6, iclass 13, count 2 2006.201.20:23:40.99#ibcon#end of sib2, iclass 13, count 2 2006.201.20:23:40.99#ibcon#*mode == 0, iclass 13, count 2 2006.201.20:23:40.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.20:23:40.99#ibcon#[27=AT02-05\r\n] 2006.201.20:23:40.99#ibcon#*before write, iclass 13, count 2 2006.201.20:23:40.99#ibcon#enter sib2, iclass 13, count 2 2006.201.20:23:40.99#ibcon#flushed, iclass 13, count 2 2006.201.20:23:40.99#ibcon#about to write, iclass 13, count 2 2006.201.20:23:40.99#ibcon#wrote, iclass 13, count 2 2006.201.20:23:40.99#ibcon#about to read 3, iclass 13, count 2 2006.201.20:23:41.02#ibcon#read 3, iclass 13, count 2 2006.201.20:23:41.02#ibcon#about to read 4, iclass 13, count 2 2006.201.20:23:41.02#ibcon#read 4, iclass 13, count 2 2006.201.20:23:41.02#ibcon#about to read 5, iclass 13, count 2 2006.201.20:23:41.02#ibcon#read 5, iclass 13, count 2 2006.201.20:23:41.02#ibcon#about to read 6, iclass 13, count 2 2006.201.20:23:41.02#ibcon#read 6, iclass 13, count 2 2006.201.20:23:41.02#ibcon#end of sib2, iclass 13, count 2 2006.201.20:23:41.02#ibcon#*after write, iclass 13, count 2 2006.201.20:23:41.02#ibcon#*before return 0, iclass 13, count 2 2006.201.20:23:41.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:41.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:23:41.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.20:23:41.02#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:41.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:41.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:41.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:41.14#ibcon#enter wrdev, iclass 13, count 0 2006.201.20:23:41.14#ibcon#first serial, iclass 13, count 0 2006.201.20:23:41.14#ibcon#enter sib2, iclass 13, count 0 2006.201.20:23:41.14#ibcon#flushed, iclass 13, count 0 2006.201.20:23:41.14#ibcon#about to write, iclass 13, count 0 2006.201.20:23:41.14#ibcon#wrote, iclass 13, count 0 2006.201.20:23:41.14#ibcon#about to read 3, iclass 13, count 0 2006.201.20:23:41.16#ibcon#read 3, iclass 13, count 0 2006.201.20:23:41.16#ibcon#about to read 4, iclass 13, count 0 2006.201.20:23:41.16#ibcon#read 4, iclass 13, count 0 2006.201.20:23:41.16#ibcon#about to read 5, iclass 13, count 0 2006.201.20:23:41.16#ibcon#read 5, iclass 13, count 0 2006.201.20:23:41.16#ibcon#about to read 6, iclass 13, count 0 2006.201.20:23:41.16#ibcon#read 6, iclass 13, count 0 2006.201.20:23:41.16#ibcon#end of sib2, iclass 13, count 0 2006.201.20:23:41.16#ibcon#*mode == 0, iclass 13, count 0 2006.201.20:23:41.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.20:23:41.16#ibcon#[27=USB\r\n] 2006.201.20:23:41.16#ibcon#*before write, iclass 13, count 0 2006.201.20:23:41.16#ibcon#enter sib2, iclass 13, count 0 2006.201.20:23:41.16#ibcon#flushed, iclass 13, count 0 2006.201.20:23:41.16#ibcon#about to write, iclass 13, count 0 2006.201.20:23:41.16#ibcon#wrote, iclass 13, count 0 2006.201.20:23:41.16#ibcon#about to read 3, iclass 13, count 0 2006.201.20:23:41.19#ibcon#read 3, iclass 13, count 0 2006.201.20:23:41.19#ibcon#about to read 4, iclass 13, count 0 2006.201.20:23:41.19#ibcon#read 4, iclass 13, count 0 2006.201.20:23:41.19#ibcon#about to read 5, iclass 13, count 0 2006.201.20:23:41.19#ibcon#read 5, iclass 13, count 0 2006.201.20:23:41.19#ibcon#about to read 6, iclass 13, count 0 2006.201.20:23:41.19#ibcon#read 6, iclass 13, count 0 2006.201.20:23:41.19#ibcon#end of sib2, iclass 13, count 0 2006.201.20:23:41.19#ibcon#*after write, iclass 13, count 0 2006.201.20:23:41.19#ibcon#*before return 0, iclass 13, count 0 2006.201.20:23:41.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:41.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:23:41.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.20:23:41.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.20:23:41.19$vck44/vblo=3,649.99 2006.201.20:23:41.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.20:23:41.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.20:23:41.19#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:41.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:41.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:41.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:41.19#ibcon#enter wrdev, iclass 15, count 0 2006.201.20:23:41.19#ibcon#first serial, iclass 15, count 0 2006.201.20:23:41.19#ibcon#enter sib2, iclass 15, count 0 2006.201.20:23:41.19#ibcon#flushed, iclass 15, count 0 2006.201.20:23:41.19#ibcon#about to write, iclass 15, count 0 2006.201.20:23:41.19#ibcon#wrote, iclass 15, count 0 2006.201.20:23:41.19#ibcon#about to read 3, iclass 15, count 0 2006.201.20:23:41.21#ibcon#read 3, iclass 15, count 0 2006.201.20:23:41.21#ibcon#about to read 4, iclass 15, count 0 2006.201.20:23:41.21#ibcon#read 4, iclass 15, count 0 2006.201.20:23:41.21#ibcon#about to read 5, iclass 15, count 0 2006.201.20:23:41.21#ibcon#read 5, iclass 15, count 0 2006.201.20:23:41.21#ibcon#about to read 6, iclass 15, count 0 2006.201.20:23:41.21#ibcon#read 6, iclass 15, count 0 2006.201.20:23:41.21#ibcon#end of sib2, iclass 15, count 0 2006.201.20:23:41.21#ibcon#*mode == 0, iclass 15, count 0 2006.201.20:23:41.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.20:23:41.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:23:41.21#ibcon#*before write, iclass 15, count 0 2006.201.20:23:41.21#ibcon#enter sib2, iclass 15, count 0 2006.201.20:23:41.21#ibcon#flushed, iclass 15, count 0 2006.201.20:23:41.21#ibcon#about to write, iclass 15, count 0 2006.201.20:23:41.21#ibcon#wrote, iclass 15, count 0 2006.201.20:23:41.21#ibcon#about to read 3, iclass 15, count 0 2006.201.20:23:41.25#ibcon#read 3, iclass 15, count 0 2006.201.20:23:41.25#ibcon#about to read 4, iclass 15, count 0 2006.201.20:23:41.25#ibcon#read 4, iclass 15, count 0 2006.201.20:23:41.25#ibcon#about to read 5, iclass 15, count 0 2006.201.20:23:41.25#ibcon#read 5, iclass 15, count 0 2006.201.20:23:41.25#ibcon#about to read 6, iclass 15, count 0 2006.201.20:23:41.25#ibcon#read 6, iclass 15, count 0 2006.201.20:23:41.25#ibcon#end of sib2, iclass 15, count 0 2006.201.20:23:41.25#ibcon#*after write, iclass 15, count 0 2006.201.20:23:41.25#ibcon#*before return 0, iclass 15, count 0 2006.201.20:23:41.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:41.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:23:41.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.20:23:41.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.20:23:41.25$vck44/vb=3,4 2006.201.20:23:41.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.20:23:41.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.20:23:41.25#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:41.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:41.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:41.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:41.31#ibcon#enter wrdev, iclass 17, count 2 2006.201.20:23:41.31#ibcon#first serial, iclass 17, count 2 2006.201.20:23:41.31#ibcon#enter sib2, iclass 17, count 2 2006.201.20:23:41.31#ibcon#flushed, iclass 17, count 2 2006.201.20:23:41.31#ibcon#about to write, iclass 17, count 2 2006.201.20:23:41.31#ibcon#wrote, iclass 17, count 2 2006.201.20:23:41.31#ibcon#about to read 3, iclass 17, count 2 2006.201.20:23:41.33#ibcon#read 3, iclass 17, count 2 2006.201.20:23:41.33#ibcon#about to read 4, iclass 17, count 2 2006.201.20:23:41.33#ibcon#read 4, iclass 17, count 2 2006.201.20:23:41.33#ibcon#about to read 5, iclass 17, count 2 2006.201.20:23:41.33#ibcon#read 5, iclass 17, count 2 2006.201.20:23:41.33#ibcon#about to read 6, iclass 17, count 2 2006.201.20:23:41.33#ibcon#read 6, iclass 17, count 2 2006.201.20:23:41.33#ibcon#end of sib2, iclass 17, count 2 2006.201.20:23:41.33#ibcon#*mode == 0, iclass 17, count 2 2006.201.20:23:41.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.20:23:41.33#ibcon#[27=AT03-04\r\n] 2006.201.20:23:41.33#ibcon#*before write, iclass 17, count 2 2006.201.20:23:41.33#ibcon#enter sib2, iclass 17, count 2 2006.201.20:23:41.33#ibcon#flushed, iclass 17, count 2 2006.201.20:23:41.33#ibcon#about to write, iclass 17, count 2 2006.201.20:23:41.33#ibcon#wrote, iclass 17, count 2 2006.201.20:23:41.33#ibcon#about to read 3, iclass 17, count 2 2006.201.20:23:41.36#ibcon#read 3, iclass 17, count 2 2006.201.20:23:41.36#ibcon#about to read 4, iclass 17, count 2 2006.201.20:23:41.36#ibcon#read 4, iclass 17, count 2 2006.201.20:23:41.36#ibcon#about to read 5, iclass 17, count 2 2006.201.20:23:41.36#ibcon#read 5, iclass 17, count 2 2006.201.20:23:41.36#ibcon#about to read 6, iclass 17, count 2 2006.201.20:23:41.36#ibcon#read 6, iclass 17, count 2 2006.201.20:23:41.36#ibcon#end of sib2, iclass 17, count 2 2006.201.20:23:41.36#ibcon#*after write, iclass 17, count 2 2006.201.20:23:41.36#ibcon#*before return 0, iclass 17, count 2 2006.201.20:23:41.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:41.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:23:41.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.20:23:41.36#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:41.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:41.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:41.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:41.48#ibcon#enter wrdev, iclass 17, count 0 2006.201.20:23:41.48#ibcon#first serial, iclass 17, count 0 2006.201.20:23:41.48#ibcon#enter sib2, iclass 17, count 0 2006.201.20:23:41.48#ibcon#flushed, iclass 17, count 0 2006.201.20:23:41.48#ibcon#about to write, iclass 17, count 0 2006.201.20:23:41.48#ibcon#wrote, iclass 17, count 0 2006.201.20:23:41.48#ibcon#about to read 3, iclass 17, count 0 2006.201.20:23:41.50#ibcon#read 3, iclass 17, count 0 2006.201.20:23:41.50#ibcon#about to read 4, iclass 17, count 0 2006.201.20:23:41.50#ibcon#read 4, iclass 17, count 0 2006.201.20:23:41.50#ibcon#about to read 5, iclass 17, count 0 2006.201.20:23:41.50#ibcon#read 5, iclass 17, count 0 2006.201.20:23:41.50#ibcon#about to read 6, iclass 17, count 0 2006.201.20:23:41.50#ibcon#read 6, iclass 17, count 0 2006.201.20:23:41.50#ibcon#end of sib2, iclass 17, count 0 2006.201.20:23:41.50#ibcon#*mode == 0, iclass 17, count 0 2006.201.20:23:41.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.20:23:41.50#ibcon#[27=USB\r\n] 2006.201.20:23:41.50#ibcon#*before write, iclass 17, count 0 2006.201.20:23:41.50#ibcon#enter sib2, iclass 17, count 0 2006.201.20:23:41.50#ibcon#flushed, iclass 17, count 0 2006.201.20:23:41.50#ibcon#about to write, iclass 17, count 0 2006.201.20:23:41.50#ibcon#wrote, iclass 17, count 0 2006.201.20:23:41.50#ibcon#about to read 3, iclass 17, count 0 2006.201.20:23:41.53#ibcon#read 3, iclass 17, count 0 2006.201.20:23:41.53#ibcon#about to read 4, iclass 17, count 0 2006.201.20:23:41.53#ibcon#read 4, iclass 17, count 0 2006.201.20:23:41.53#ibcon#about to read 5, iclass 17, count 0 2006.201.20:23:41.53#ibcon#read 5, iclass 17, count 0 2006.201.20:23:41.53#ibcon#about to read 6, iclass 17, count 0 2006.201.20:23:41.53#ibcon#read 6, iclass 17, count 0 2006.201.20:23:41.53#ibcon#end of sib2, iclass 17, count 0 2006.201.20:23:41.53#ibcon#*after write, iclass 17, count 0 2006.201.20:23:41.53#ibcon#*before return 0, iclass 17, count 0 2006.201.20:23:41.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:41.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:23:41.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.20:23:41.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.20:23:41.53$vck44/vblo=4,679.99 2006.201.20:23:41.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.20:23:41.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.20:23:41.53#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:41.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:41.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:41.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:41.53#ibcon#enter wrdev, iclass 19, count 0 2006.201.20:23:41.53#ibcon#first serial, iclass 19, count 0 2006.201.20:23:41.53#ibcon#enter sib2, iclass 19, count 0 2006.201.20:23:41.53#ibcon#flushed, iclass 19, count 0 2006.201.20:23:41.53#ibcon#about to write, iclass 19, count 0 2006.201.20:23:41.53#ibcon#wrote, iclass 19, count 0 2006.201.20:23:41.53#ibcon#about to read 3, iclass 19, count 0 2006.201.20:23:41.55#ibcon#read 3, iclass 19, count 0 2006.201.20:23:41.55#ibcon#about to read 4, iclass 19, count 0 2006.201.20:23:41.55#ibcon#read 4, iclass 19, count 0 2006.201.20:23:41.55#ibcon#about to read 5, iclass 19, count 0 2006.201.20:23:41.55#ibcon#read 5, iclass 19, count 0 2006.201.20:23:41.55#ibcon#about to read 6, iclass 19, count 0 2006.201.20:23:41.55#ibcon#read 6, iclass 19, count 0 2006.201.20:23:41.55#ibcon#end of sib2, iclass 19, count 0 2006.201.20:23:41.55#ibcon#*mode == 0, iclass 19, count 0 2006.201.20:23:41.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.20:23:41.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:23:41.55#ibcon#*before write, iclass 19, count 0 2006.201.20:23:41.55#ibcon#enter sib2, iclass 19, count 0 2006.201.20:23:41.55#ibcon#flushed, iclass 19, count 0 2006.201.20:23:41.55#ibcon#about to write, iclass 19, count 0 2006.201.20:23:41.55#ibcon#wrote, iclass 19, count 0 2006.201.20:23:41.55#ibcon#about to read 3, iclass 19, count 0 2006.201.20:23:41.60#ibcon#read 3, iclass 19, count 0 2006.201.20:23:41.60#ibcon#about to read 4, iclass 19, count 0 2006.201.20:23:41.60#ibcon#read 4, iclass 19, count 0 2006.201.20:23:41.60#ibcon#about to read 5, iclass 19, count 0 2006.201.20:23:41.60#ibcon#read 5, iclass 19, count 0 2006.201.20:23:41.60#ibcon#about to read 6, iclass 19, count 0 2006.201.20:23:41.60#ibcon#read 6, iclass 19, count 0 2006.201.20:23:41.60#ibcon#end of sib2, iclass 19, count 0 2006.201.20:23:41.60#ibcon#*after write, iclass 19, count 0 2006.201.20:23:41.60#ibcon#*before return 0, iclass 19, count 0 2006.201.20:23:41.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:41.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:23:41.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.20:23:41.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.20:23:41.60$vck44/vb=4,5 2006.201.20:23:41.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.20:23:41.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.20:23:41.60#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:41.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:41.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:41.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:41.65#ibcon#enter wrdev, iclass 21, count 2 2006.201.20:23:41.65#ibcon#first serial, iclass 21, count 2 2006.201.20:23:41.65#ibcon#enter sib2, iclass 21, count 2 2006.201.20:23:41.65#ibcon#flushed, iclass 21, count 2 2006.201.20:23:41.65#ibcon#about to write, iclass 21, count 2 2006.201.20:23:41.65#ibcon#wrote, iclass 21, count 2 2006.201.20:23:41.65#ibcon#about to read 3, iclass 21, count 2 2006.201.20:23:41.67#ibcon#read 3, iclass 21, count 2 2006.201.20:23:41.67#ibcon#about to read 4, iclass 21, count 2 2006.201.20:23:41.67#ibcon#read 4, iclass 21, count 2 2006.201.20:23:41.67#ibcon#about to read 5, iclass 21, count 2 2006.201.20:23:41.67#ibcon#read 5, iclass 21, count 2 2006.201.20:23:41.67#ibcon#about to read 6, iclass 21, count 2 2006.201.20:23:41.67#ibcon#read 6, iclass 21, count 2 2006.201.20:23:41.67#ibcon#end of sib2, iclass 21, count 2 2006.201.20:23:41.67#ibcon#*mode == 0, iclass 21, count 2 2006.201.20:23:41.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.20:23:41.67#ibcon#[27=AT04-05\r\n] 2006.201.20:23:41.67#ibcon#*before write, iclass 21, count 2 2006.201.20:23:41.67#ibcon#enter sib2, iclass 21, count 2 2006.201.20:23:41.67#ibcon#flushed, iclass 21, count 2 2006.201.20:23:41.67#ibcon#about to write, iclass 21, count 2 2006.201.20:23:41.67#ibcon#wrote, iclass 21, count 2 2006.201.20:23:41.67#ibcon#about to read 3, iclass 21, count 2 2006.201.20:23:41.70#ibcon#read 3, iclass 21, count 2 2006.201.20:23:41.70#ibcon#about to read 4, iclass 21, count 2 2006.201.20:23:41.70#ibcon#read 4, iclass 21, count 2 2006.201.20:23:41.70#ibcon#about to read 5, iclass 21, count 2 2006.201.20:23:41.70#ibcon#read 5, iclass 21, count 2 2006.201.20:23:41.70#ibcon#about to read 6, iclass 21, count 2 2006.201.20:23:41.70#ibcon#read 6, iclass 21, count 2 2006.201.20:23:41.70#ibcon#end of sib2, iclass 21, count 2 2006.201.20:23:41.70#ibcon#*after write, iclass 21, count 2 2006.201.20:23:41.70#ibcon#*before return 0, iclass 21, count 2 2006.201.20:23:41.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:41.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:23:41.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.20:23:41.70#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:41.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:41.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:41.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:41.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.20:23:41.82#ibcon#first serial, iclass 21, count 0 2006.201.20:23:41.82#ibcon#enter sib2, iclass 21, count 0 2006.201.20:23:41.82#ibcon#flushed, iclass 21, count 0 2006.201.20:23:41.82#ibcon#about to write, iclass 21, count 0 2006.201.20:23:41.82#ibcon#wrote, iclass 21, count 0 2006.201.20:23:41.82#ibcon#about to read 3, iclass 21, count 0 2006.201.20:23:41.84#ibcon#read 3, iclass 21, count 0 2006.201.20:23:41.84#ibcon#about to read 4, iclass 21, count 0 2006.201.20:23:41.84#ibcon#read 4, iclass 21, count 0 2006.201.20:23:41.84#ibcon#about to read 5, iclass 21, count 0 2006.201.20:23:41.84#ibcon#read 5, iclass 21, count 0 2006.201.20:23:41.84#ibcon#about to read 6, iclass 21, count 0 2006.201.20:23:41.84#ibcon#read 6, iclass 21, count 0 2006.201.20:23:41.84#ibcon#end of sib2, iclass 21, count 0 2006.201.20:23:41.84#ibcon#*mode == 0, iclass 21, count 0 2006.201.20:23:41.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.20:23:41.84#ibcon#[27=USB\r\n] 2006.201.20:23:41.84#ibcon#*before write, iclass 21, count 0 2006.201.20:23:41.84#ibcon#enter sib2, iclass 21, count 0 2006.201.20:23:41.84#ibcon#flushed, iclass 21, count 0 2006.201.20:23:41.84#ibcon#about to write, iclass 21, count 0 2006.201.20:23:41.84#ibcon#wrote, iclass 21, count 0 2006.201.20:23:41.84#ibcon#about to read 3, iclass 21, count 0 2006.201.20:23:41.87#ibcon#read 3, iclass 21, count 0 2006.201.20:23:41.87#ibcon#about to read 4, iclass 21, count 0 2006.201.20:23:41.87#ibcon#read 4, iclass 21, count 0 2006.201.20:23:41.87#ibcon#about to read 5, iclass 21, count 0 2006.201.20:23:41.87#ibcon#read 5, iclass 21, count 0 2006.201.20:23:41.87#ibcon#about to read 6, iclass 21, count 0 2006.201.20:23:41.87#ibcon#read 6, iclass 21, count 0 2006.201.20:23:41.87#ibcon#end of sib2, iclass 21, count 0 2006.201.20:23:41.87#ibcon#*after write, iclass 21, count 0 2006.201.20:23:41.87#ibcon#*before return 0, iclass 21, count 0 2006.201.20:23:41.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:41.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:23:41.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.20:23:41.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.20:23:41.87$vck44/vblo=5,709.99 2006.201.20:23:41.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.20:23:41.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.20:23:41.87#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:41.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:41.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:41.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:41.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:23:41.87#ibcon#first serial, iclass 23, count 0 2006.201.20:23:41.87#ibcon#enter sib2, iclass 23, count 0 2006.201.20:23:41.87#ibcon#flushed, iclass 23, count 0 2006.201.20:23:41.87#ibcon#about to write, iclass 23, count 0 2006.201.20:23:41.87#ibcon#wrote, iclass 23, count 0 2006.201.20:23:41.87#ibcon#about to read 3, iclass 23, count 0 2006.201.20:23:41.89#ibcon#read 3, iclass 23, count 0 2006.201.20:23:41.89#ibcon#about to read 4, iclass 23, count 0 2006.201.20:23:41.89#ibcon#read 4, iclass 23, count 0 2006.201.20:23:41.89#ibcon#about to read 5, iclass 23, count 0 2006.201.20:23:41.89#ibcon#read 5, iclass 23, count 0 2006.201.20:23:41.89#ibcon#about to read 6, iclass 23, count 0 2006.201.20:23:41.89#ibcon#read 6, iclass 23, count 0 2006.201.20:23:41.89#ibcon#end of sib2, iclass 23, count 0 2006.201.20:23:41.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:23:41.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:23:41.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:23:41.89#ibcon#*before write, iclass 23, count 0 2006.201.20:23:41.89#ibcon#enter sib2, iclass 23, count 0 2006.201.20:23:41.89#ibcon#flushed, iclass 23, count 0 2006.201.20:23:41.89#ibcon#about to write, iclass 23, count 0 2006.201.20:23:41.89#ibcon#wrote, iclass 23, count 0 2006.201.20:23:41.89#ibcon#about to read 3, iclass 23, count 0 2006.201.20:23:41.93#ibcon#read 3, iclass 23, count 0 2006.201.20:23:41.93#ibcon#about to read 4, iclass 23, count 0 2006.201.20:23:41.93#ibcon#read 4, iclass 23, count 0 2006.201.20:23:41.93#ibcon#about to read 5, iclass 23, count 0 2006.201.20:23:41.93#ibcon#read 5, iclass 23, count 0 2006.201.20:23:41.93#ibcon#about to read 6, iclass 23, count 0 2006.201.20:23:41.93#ibcon#read 6, iclass 23, count 0 2006.201.20:23:41.93#ibcon#end of sib2, iclass 23, count 0 2006.201.20:23:41.93#ibcon#*after write, iclass 23, count 0 2006.201.20:23:41.93#ibcon#*before return 0, iclass 23, count 0 2006.201.20:23:41.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:41.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:23:41.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:23:41.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:23:41.93$vck44/vb=5,4 2006.201.20:23:41.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.20:23:41.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.20:23:41.93#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:41.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:41.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:41.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:41.99#ibcon#enter wrdev, iclass 25, count 2 2006.201.20:23:41.99#ibcon#first serial, iclass 25, count 2 2006.201.20:23:41.99#ibcon#enter sib2, iclass 25, count 2 2006.201.20:23:41.99#ibcon#flushed, iclass 25, count 2 2006.201.20:23:41.99#ibcon#about to write, iclass 25, count 2 2006.201.20:23:41.99#ibcon#wrote, iclass 25, count 2 2006.201.20:23:41.99#ibcon#about to read 3, iclass 25, count 2 2006.201.20:23:42.01#ibcon#read 3, iclass 25, count 2 2006.201.20:23:42.01#ibcon#about to read 4, iclass 25, count 2 2006.201.20:23:42.01#ibcon#read 4, iclass 25, count 2 2006.201.20:23:42.01#ibcon#about to read 5, iclass 25, count 2 2006.201.20:23:42.01#ibcon#read 5, iclass 25, count 2 2006.201.20:23:42.01#ibcon#about to read 6, iclass 25, count 2 2006.201.20:23:42.01#ibcon#read 6, iclass 25, count 2 2006.201.20:23:42.01#ibcon#end of sib2, iclass 25, count 2 2006.201.20:23:42.01#ibcon#*mode == 0, iclass 25, count 2 2006.201.20:23:42.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.20:23:42.01#ibcon#[27=AT05-04\r\n] 2006.201.20:23:42.01#ibcon#*before write, iclass 25, count 2 2006.201.20:23:42.01#ibcon#enter sib2, iclass 25, count 2 2006.201.20:23:42.01#ibcon#flushed, iclass 25, count 2 2006.201.20:23:42.01#ibcon#about to write, iclass 25, count 2 2006.201.20:23:42.01#ibcon#wrote, iclass 25, count 2 2006.201.20:23:42.01#ibcon#about to read 3, iclass 25, count 2 2006.201.20:23:42.04#ibcon#read 3, iclass 25, count 2 2006.201.20:23:42.04#ibcon#about to read 4, iclass 25, count 2 2006.201.20:23:42.04#ibcon#read 4, iclass 25, count 2 2006.201.20:23:42.04#ibcon#about to read 5, iclass 25, count 2 2006.201.20:23:42.04#ibcon#read 5, iclass 25, count 2 2006.201.20:23:42.04#ibcon#about to read 6, iclass 25, count 2 2006.201.20:23:42.04#ibcon#read 6, iclass 25, count 2 2006.201.20:23:42.04#ibcon#end of sib2, iclass 25, count 2 2006.201.20:23:42.04#ibcon#*after write, iclass 25, count 2 2006.201.20:23:42.04#ibcon#*before return 0, iclass 25, count 2 2006.201.20:23:42.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:42.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:23:42.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.20:23:42.04#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:42.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:42.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:42.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:42.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.20:23:42.16#ibcon#first serial, iclass 25, count 0 2006.201.20:23:42.16#ibcon#enter sib2, iclass 25, count 0 2006.201.20:23:42.16#ibcon#flushed, iclass 25, count 0 2006.201.20:23:42.16#ibcon#about to write, iclass 25, count 0 2006.201.20:23:42.16#ibcon#wrote, iclass 25, count 0 2006.201.20:23:42.16#ibcon#about to read 3, iclass 25, count 0 2006.201.20:23:42.18#ibcon#read 3, iclass 25, count 0 2006.201.20:23:42.18#ibcon#about to read 4, iclass 25, count 0 2006.201.20:23:42.18#ibcon#read 4, iclass 25, count 0 2006.201.20:23:42.18#ibcon#about to read 5, iclass 25, count 0 2006.201.20:23:42.18#ibcon#read 5, iclass 25, count 0 2006.201.20:23:42.18#ibcon#about to read 6, iclass 25, count 0 2006.201.20:23:42.18#ibcon#read 6, iclass 25, count 0 2006.201.20:23:42.18#ibcon#end of sib2, iclass 25, count 0 2006.201.20:23:42.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.20:23:42.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.20:23:42.18#ibcon#[27=USB\r\n] 2006.201.20:23:42.18#ibcon#*before write, iclass 25, count 0 2006.201.20:23:42.18#ibcon#enter sib2, iclass 25, count 0 2006.201.20:23:42.18#ibcon#flushed, iclass 25, count 0 2006.201.20:23:42.18#ibcon#about to write, iclass 25, count 0 2006.201.20:23:42.18#ibcon#wrote, iclass 25, count 0 2006.201.20:23:42.18#ibcon#about to read 3, iclass 25, count 0 2006.201.20:23:42.21#ibcon#read 3, iclass 25, count 0 2006.201.20:23:42.21#ibcon#about to read 4, iclass 25, count 0 2006.201.20:23:42.21#ibcon#read 4, iclass 25, count 0 2006.201.20:23:42.21#ibcon#about to read 5, iclass 25, count 0 2006.201.20:23:42.21#ibcon#read 5, iclass 25, count 0 2006.201.20:23:42.21#ibcon#about to read 6, iclass 25, count 0 2006.201.20:23:42.21#ibcon#read 6, iclass 25, count 0 2006.201.20:23:42.21#ibcon#end of sib2, iclass 25, count 0 2006.201.20:23:42.21#ibcon#*after write, iclass 25, count 0 2006.201.20:23:42.21#ibcon#*before return 0, iclass 25, count 0 2006.201.20:23:42.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:42.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:23:42.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.20:23:42.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.20:23:42.21$vck44/vblo=6,719.99 2006.201.20:23:42.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.20:23:42.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.20:23:42.21#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:42.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:42.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:42.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:42.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:23:42.21#ibcon#first serial, iclass 27, count 0 2006.201.20:23:42.21#ibcon#enter sib2, iclass 27, count 0 2006.201.20:23:42.21#ibcon#flushed, iclass 27, count 0 2006.201.20:23:42.21#ibcon#about to write, iclass 27, count 0 2006.201.20:23:42.21#ibcon#wrote, iclass 27, count 0 2006.201.20:23:42.21#ibcon#about to read 3, iclass 27, count 0 2006.201.20:23:42.23#ibcon#read 3, iclass 27, count 0 2006.201.20:23:42.23#ibcon#about to read 4, iclass 27, count 0 2006.201.20:23:42.23#ibcon#read 4, iclass 27, count 0 2006.201.20:23:42.23#ibcon#about to read 5, iclass 27, count 0 2006.201.20:23:42.23#ibcon#read 5, iclass 27, count 0 2006.201.20:23:42.23#ibcon#about to read 6, iclass 27, count 0 2006.201.20:23:42.23#ibcon#read 6, iclass 27, count 0 2006.201.20:23:42.23#ibcon#end of sib2, iclass 27, count 0 2006.201.20:23:42.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:23:42.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:23:42.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:23:42.23#ibcon#*before write, iclass 27, count 0 2006.201.20:23:42.23#ibcon#enter sib2, iclass 27, count 0 2006.201.20:23:42.23#ibcon#flushed, iclass 27, count 0 2006.201.20:23:42.23#ibcon#about to write, iclass 27, count 0 2006.201.20:23:42.23#ibcon#wrote, iclass 27, count 0 2006.201.20:23:42.23#ibcon#about to read 3, iclass 27, count 0 2006.201.20:23:42.27#ibcon#read 3, iclass 27, count 0 2006.201.20:23:42.27#ibcon#about to read 4, iclass 27, count 0 2006.201.20:23:42.27#ibcon#read 4, iclass 27, count 0 2006.201.20:23:42.27#ibcon#about to read 5, iclass 27, count 0 2006.201.20:23:42.27#ibcon#read 5, iclass 27, count 0 2006.201.20:23:42.27#ibcon#about to read 6, iclass 27, count 0 2006.201.20:23:42.27#ibcon#read 6, iclass 27, count 0 2006.201.20:23:42.27#ibcon#end of sib2, iclass 27, count 0 2006.201.20:23:42.27#ibcon#*after write, iclass 27, count 0 2006.201.20:23:42.27#ibcon#*before return 0, iclass 27, count 0 2006.201.20:23:42.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:42.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:23:42.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:23:42.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:23:42.27$vck44/vb=6,4 2006.201.20:23:42.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.20:23:42.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.20:23:42.27#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:42.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:42.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:42.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:42.33#ibcon#enter wrdev, iclass 29, count 2 2006.201.20:23:42.33#ibcon#first serial, iclass 29, count 2 2006.201.20:23:42.33#ibcon#enter sib2, iclass 29, count 2 2006.201.20:23:42.33#ibcon#flushed, iclass 29, count 2 2006.201.20:23:42.33#ibcon#about to write, iclass 29, count 2 2006.201.20:23:42.33#ibcon#wrote, iclass 29, count 2 2006.201.20:23:42.33#ibcon#about to read 3, iclass 29, count 2 2006.201.20:23:42.35#ibcon#read 3, iclass 29, count 2 2006.201.20:23:42.35#ibcon#about to read 4, iclass 29, count 2 2006.201.20:23:42.35#ibcon#read 4, iclass 29, count 2 2006.201.20:23:42.35#ibcon#about to read 5, iclass 29, count 2 2006.201.20:23:42.35#ibcon#read 5, iclass 29, count 2 2006.201.20:23:42.35#ibcon#about to read 6, iclass 29, count 2 2006.201.20:23:42.35#ibcon#read 6, iclass 29, count 2 2006.201.20:23:42.35#ibcon#end of sib2, iclass 29, count 2 2006.201.20:23:42.35#ibcon#*mode == 0, iclass 29, count 2 2006.201.20:23:42.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.20:23:42.35#ibcon#[27=AT06-04\r\n] 2006.201.20:23:42.35#ibcon#*before write, iclass 29, count 2 2006.201.20:23:42.35#ibcon#enter sib2, iclass 29, count 2 2006.201.20:23:42.35#ibcon#flushed, iclass 29, count 2 2006.201.20:23:42.35#ibcon#about to write, iclass 29, count 2 2006.201.20:23:42.35#ibcon#wrote, iclass 29, count 2 2006.201.20:23:42.35#ibcon#about to read 3, iclass 29, count 2 2006.201.20:23:42.38#ibcon#read 3, iclass 29, count 2 2006.201.20:23:42.38#ibcon#about to read 4, iclass 29, count 2 2006.201.20:23:42.38#ibcon#read 4, iclass 29, count 2 2006.201.20:23:42.38#ibcon#about to read 5, iclass 29, count 2 2006.201.20:23:42.38#ibcon#read 5, iclass 29, count 2 2006.201.20:23:42.38#ibcon#about to read 6, iclass 29, count 2 2006.201.20:23:42.38#ibcon#read 6, iclass 29, count 2 2006.201.20:23:42.38#ibcon#end of sib2, iclass 29, count 2 2006.201.20:23:42.38#ibcon#*after write, iclass 29, count 2 2006.201.20:23:42.38#ibcon#*before return 0, iclass 29, count 2 2006.201.20:23:42.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:42.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:23:42.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.20:23:42.38#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:42.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:42.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:42.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:42.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.20:23:42.50#ibcon#first serial, iclass 29, count 0 2006.201.20:23:42.50#ibcon#enter sib2, iclass 29, count 0 2006.201.20:23:42.50#ibcon#flushed, iclass 29, count 0 2006.201.20:23:42.50#ibcon#about to write, iclass 29, count 0 2006.201.20:23:42.50#ibcon#wrote, iclass 29, count 0 2006.201.20:23:42.50#ibcon#about to read 3, iclass 29, count 0 2006.201.20:23:42.52#ibcon#read 3, iclass 29, count 0 2006.201.20:23:42.52#ibcon#about to read 4, iclass 29, count 0 2006.201.20:23:42.52#ibcon#read 4, iclass 29, count 0 2006.201.20:23:42.52#ibcon#about to read 5, iclass 29, count 0 2006.201.20:23:42.52#ibcon#read 5, iclass 29, count 0 2006.201.20:23:42.52#ibcon#about to read 6, iclass 29, count 0 2006.201.20:23:42.52#ibcon#read 6, iclass 29, count 0 2006.201.20:23:42.52#ibcon#end of sib2, iclass 29, count 0 2006.201.20:23:42.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.20:23:42.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.20:23:42.52#ibcon#[27=USB\r\n] 2006.201.20:23:42.52#ibcon#*before write, iclass 29, count 0 2006.201.20:23:42.52#ibcon#enter sib2, iclass 29, count 0 2006.201.20:23:42.52#ibcon#flushed, iclass 29, count 0 2006.201.20:23:42.52#ibcon#about to write, iclass 29, count 0 2006.201.20:23:42.52#ibcon#wrote, iclass 29, count 0 2006.201.20:23:42.52#ibcon#about to read 3, iclass 29, count 0 2006.201.20:23:42.55#ibcon#read 3, iclass 29, count 0 2006.201.20:23:42.55#ibcon#about to read 4, iclass 29, count 0 2006.201.20:23:42.55#ibcon#read 4, iclass 29, count 0 2006.201.20:23:42.55#ibcon#about to read 5, iclass 29, count 0 2006.201.20:23:42.55#ibcon#read 5, iclass 29, count 0 2006.201.20:23:42.55#ibcon#about to read 6, iclass 29, count 0 2006.201.20:23:42.55#ibcon#read 6, iclass 29, count 0 2006.201.20:23:42.55#ibcon#end of sib2, iclass 29, count 0 2006.201.20:23:42.55#ibcon#*after write, iclass 29, count 0 2006.201.20:23:42.55#ibcon#*before return 0, iclass 29, count 0 2006.201.20:23:42.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:42.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:23:42.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.20:23:42.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.20:23:42.55$vck44/vblo=7,734.99 2006.201.20:23:42.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.20:23:42.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.20:23:42.55#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:42.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:42.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:42.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:42.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.20:23:42.55#ibcon#first serial, iclass 31, count 0 2006.201.20:23:42.55#ibcon#enter sib2, iclass 31, count 0 2006.201.20:23:42.55#ibcon#flushed, iclass 31, count 0 2006.201.20:23:42.55#ibcon#about to write, iclass 31, count 0 2006.201.20:23:42.55#ibcon#wrote, iclass 31, count 0 2006.201.20:23:42.55#ibcon#about to read 3, iclass 31, count 0 2006.201.20:23:42.57#ibcon#read 3, iclass 31, count 0 2006.201.20:23:42.57#ibcon#about to read 4, iclass 31, count 0 2006.201.20:23:42.57#ibcon#read 4, iclass 31, count 0 2006.201.20:23:42.57#ibcon#about to read 5, iclass 31, count 0 2006.201.20:23:42.57#ibcon#read 5, iclass 31, count 0 2006.201.20:23:42.57#ibcon#about to read 6, iclass 31, count 0 2006.201.20:23:42.57#ibcon#read 6, iclass 31, count 0 2006.201.20:23:42.57#ibcon#end of sib2, iclass 31, count 0 2006.201.20:23:42.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.20:23:42.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.20:23:42.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:23:42.57#ibcon#*before write, iclass 31, count 0 2006.201.20:23:42.57#ibcon#enter sib2, iclass 31, count 0 2006.201.20:23:42.57#ibcon#flushed, iclass 31, count 0 2006.201.20:23:42.57#ibcon#about to write, iclass 31, count 0 2006.201.20:23:42.57#ibcon#wrote, iclass 31, count 0 2006.201.20:23:42.57#ibcon#about to read 3, iclass 31, count 0 2006.201.20:23:42.61#ibcon#read 3, iclass 31, count 0 2006.201.20:23:42.61#ibcon#about to read 4, iclass 31, count 0 2006.201.20:23:42.61#ibcon#read 4, iclass 31, count 0 2006.201.20:23:42.61#ibcon#about to read 5, iclass 31, count 0 2006.201.20:23:42.61#ibcon#read 5, iclass 31, count 0 2006.201.20:23:42.61#ibcon#about to read 6, iclass 31, count 0 2006.201.20:23:42.61#ibcon#read 6, iclass 31, count 0 2006.201.20:23:42.61#ibcon#end of sib2, iclass 31, count 0 2006.201.20:23:42.61#ibcon#*after write, iclass 31, count 0 2006.201.20:23:42.61#ibcon#*before return 0, iclass 31, count 0 2006.201.20:23:42.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:42.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:23:42.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.20:23:42.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.20:23:42.61$vck44/vb=7,4 2006.201.20:23:42.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.20:23:42.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.20:23:42.61#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:42.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:42.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:42.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:42.67#ibcon#enter wrdev, iclass 33, count 2 2006.201.20:23:42.67#ibcon#first serial, iclass 33, count 2 2006.201.20:23:42.67#ibcon#enter sib2, iclass 33, count 2 2006.201.20:23:42.67#ibcon#flushed, iclass 33, count 2 2006.201.20:23:42.67#ibcon#about to write, iclass 33, count 2 2006.201.20:23:42.67#ibcon#wrote, iclass 33, count 2 2006.201.20:23:42.67#ibcon#about to read 3, iclass 33, count 2 2006.201.20:23:42.69#ibcon#read 3, iclass 33, count 2 2006.201.20:23:42.69#ibcon#about to read 4, iclass 33, count 2 2006.201.20:23:42.69#ibcon#read 4, iclass 33, count 2 2006.201.20:23:42.69#ibcon#about to read 5, iclass 33, count 2 2006.201.20:23:42.69#ibcon#read 5, iclass 33, count 2 2006.201.20:23:42.69#ibcon#about to read 6, iclass 33, count 2 2006.201.20:23:42.69#ibcon#read 6, iclass 33, count 2 2006.201.20:23:42.69#ibcon#end of sib2, iclass 33, count 2 2006.201.20:23:42.69#ibcon#*mode == 0, iclass 33, count 2 2006.201.20:23:42.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.20:23:42.69#ibcon#[27=AT07-04\r\n] 2006.201.20:23:42.69#ibcon#*before write, iclass 33, count 2 2006.201.20:23:42.69#ibcon#enter sib2, iclass 33, count 2 2006.201.20:23:42.69#ibcon#flushed, iclass 33, count 2 2006.201.20:23:42.69#ibcon#about to write, iclass 33, count 2 2006.201.20:23:42.69#ibcon#wrote, iclass 33, count 2 2006.201.20:23:42.69#ibcon#about to read 3, iclass 33, count 2 2006.201.20:23:42.72#ibcon#read 3, iclass 33, count 2 2006.201.20:23:42.72#ibcon#about to read 4, iclass 33, count 2 2006.201.20:23:42.72#ibcon#read 4, iclass 33, count 2 2006.201.20:23:42.72#ibcon#about to read 5, iclass 33, count 2 2006.201.20:23:42.72#ibcon#read 5, iclass 33, count 2 2006.201.20:23:42.72#ibcon#about to read 6, iclass 33, count 2 2006.201.20:23:42.72#ibcon#read 6, iclass 33, count 2 2006.201.20:23:42.72#ibcon#end of sib2, iclass 33, count 2 2006.201.20:23:42.72#ibcon#*after write, iclass 33, count 2 2006.201.20:23:42.72#ibcon#*before return 0, iclass 33, count 2 2006.201.20:23:42.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:42.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:23:42.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.20:23:42.72#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:42.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:42.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:42.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:42.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.20:23:42.84#ibcon#first serial, iclass 33, count 0 2006.201.20:23:42.84#ibcon#enter sib2, iclass 33, count 0 2006.201.20:23:42.84#ibcon#flushed, iclass 33, count 0 2006.201.20:23:42.84#ibcon#about to write, iclass 33, count 0 2006.201.20:23:42.84#ibcon#wrote, iclass 33, count 0 2006.201.20:23:42.84#ibcon#about to read 3, iclass 33, count 0 2006.201.20:23:42.86#ibcon#read 3, iclass 33, count 0 2006.201.20:23:42.86#ibcon#about to read 4, iclass 33, count 0 2006.201.20:23:42.86#ibcon#read 4, iclass 33, count 0 2006.201.20:23:42.86#ibcon#about to read 5, iclass 33, count 0 2006.201.20:23:42.86#ibcon#read 5, iclass 33, count 0 2006.201.20:23:42.86#ibcon#about to read 6, iclass 33, count 0 2006.201.20:23:42.86#ibcon#read 6, iclass 33, count 0 2006.201.20:23:42.86#ibcon#end of sib2, iclass 33, count 0 2006.201.20:23:42.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.20:23:42.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.20:23:42.86#ibcon#[27=USB\r\n] 2006.201.20:23:42.86#ibcon#*before write, iclass 33, count 0 2006.201.20:23:42.86#ibcon#enter sib2, iclass 33, count 0 2006.201.20:23:42.86#ibcon#flushed, iclass 33, count 0 2006.201.20:23:42.86#ibcon#about to write, iclass 33, count 0 2006.201.20:23:42.86#ibcon#wrote, iclass 33, count 0 2006.201.20:23:42.86#ibcon#about to read 3, iclass 33, count 0 2006.201.20:23:42.89#ibcon#read 3, iclass 33, count 0 2006.201.20:23:42.89#ibcon#about to read 4, iclass 33, count 0 2006.201.20:23:42.89#ibcon#read 4, iclass 33, count 0 2006.201.20:23:42.89#ibcon#about to read 5, iclass 33, count 0 2006.201.20:23:42.89#ibcon#read 5, iclass 33, count 0 2006.201.20:23:42.89#ibcon#about to read 6, iclass 33, count 0 2006.201.20:23:42.89#ibcon#read 6, iclass 33, count 0 2006.201.20:23:42.89#ibcon#end of sib2, iclass 33, count 0 2006.201.20:23:42.89#ibcon#*after write, iclass 33, count 0 2006.201.20:23:42.89#ibcon#*before return 0, iclass 33, count 0 2006.201.20:23:42.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:42.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:23:42.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.20:23:42.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.20:23:42.89$vck44/vblo=8,744.99 2006.201.20:23:42.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.20:23:42.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.20:23:42.89#ibcon#ireg 17 cls_cnt 0 2006.201.20:23:42.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:42.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:42.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:42.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.20:23:42.89#ibcon#first serial, iclass 35, count 0 2006.201.20:23:42.89#ibcon#enter sib2, iclass 35, count 0 2006.201.20:23:42.89#ibcon#flushed, iclass 35, count 0 2006.201.20:23:42.89#ibcon#about to write, iclass 35, count 0 2006.201.20:23:42.89#ibcon#wrote, iclass 35, count 0 2006.201.20:23:42.89#ibcon#about to read 3, iclass 35, count 0 2006.201.20:23:42.91#ibcon#read 3, iclass 35, count 0 2006.201.20:23:42.91#ibcon#about to read 4, iclass 35, count 0 2006.201.20:23:42.91#ibcon#read 4, iclass 35, count 0 2006.201.20:23:42.91#ibcon#about to read 5, iclass 35, count 0 2006.201.20:23:42.91#ibcon#read 5, iclass 35, count 0 2006.201.20:23:42.91#ibcon#about to read 6, iclass 35, count 0 2006.201.20:23:42.91#ibcon#read 6, iclass 35, count 0 2006.201.20:23:42.91#ibcon#end of sib2, iclass 35, count 0 2006.201.20:23:42.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.20:23:42.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.20:23:42.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:23:42.91#ibcon#*before write, iclass 35, count 0 2006.201.20:23:42.91#ibcon#enter sib2, iclass 35, count 0 2006.201.20:23:42.91#ibcon#flushed, iclass 35, count 0 2006.201.20:23:42.91#ibcon#about to write, iclass 35, count 0 2006.201.20:23:42.91#ibcon#wrote, iclass 35, count 0 2006.201.20:23:42.91#ibcon#about to read 3, iclass 35, count 0 2006.201.20:23:42.95#ibcon#read 3, iclass 35, count 0 2006.201.20:23:42.95#ibcon#about to read 4, iclass 35, count 0 2006.201.20:23:42.95#ibcon#read 4, iclass 35, count 0 2006.201.20:23:42.95#ibcon#about to read 5, iclass 35, count 0 2006.201.20:23:42.95#ibcon#read 5, iclass 35, count 0 2006.201.20:23:42.95#ibcon#about to read 6, iclass 35, count 0 2006.201.20:23:42.95#ibcon#read 6, iclass 35, count 0 2006.201.20:23:42.95#ibcon#end of sib2, iclass 35, count 0 2006.201.20:23:42.95#ibcon#*after write, iclass 35, count 0 2006.201.20:23:42.95#ibcon#*before return 0, iclass 35, count 0 2006.201.20:23:42.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:42.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:23:42.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.20:23:42.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.20:23:42.95$vck44/vb=8,4 2006.201.20:23:42.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.20:23:42.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.20:23:42.95#ibcon#ireg 11 cls_cnt 2 2006.201.20:23:42.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:43.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:43.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:43.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.20:23:43.01#ibcon#first serial, iclass 37, count 2 2006.201.20:23:43.01#ibcon#enter sib2, iclass 37, count 2 2006.201.20:23:43.01#ibcon#flushed, iclass 37, count 2 2006.201.20:23:43.01#ibcon#about to write, iclass 37, count 2 2006.201.20:23:43.01#ibcon#wrote, iclass 37, count 2 2006.201.20:23:43.01#ibcon#about to read 3, iclass 37, count 2 2006.201.20:23:43.03#ibcon#read 3, iclass 37, count 2 2006.201.20:23:43.03#ibcon#about to read 4, iclass 37, count 2 2006.201.20:23:43.03#ibcon#read 4, iclass 37, count 2 2006.201.20:23:43.03#ibcon#about to read 5, iclass 37, count 2 2006.201.20:23:43.03#ibcon#read 5, iclass 37, count 2 2006.201.20:23:43.03#ibcon#about to read 6, iclass 37, count 2 2006.201.20:23:43.03#ibcon#read 6, iclass 37, count 2 2006.201.20:23:43.03#ibcon#end of sib2, iclass 37, count 2 2006.201.20:23:43.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.20:23:43.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.20:23:43.03#ibcon#[27=AT08-04\r\n] 2006.201.20:23:43.03#ibcon#*before write, iclass 37, count 2 2006.201.20:23:43.03#ibcon#enter sib2, iclass 37, count 2 2006.201.20:23:43.03#ibcon#flushed, iclass 37, count 2 2006.201.20:23:43.03#ibcon#about to write, iclass 37, count 2 2006.201.20:23:43.03#ibcon#wrote, iclass 37, count 2 2006.201.20:23:43.03#ibcon#about to read 3, iclass 37, count 2 2006.201.20:23:43.06#ibcon#read 3, iclass 37, count 2 2006.201.20:23:43.06#ibcon#about to read 4, iclass 37, count 2 2006.201.20:23:43.06#ibcon#read 4, iclass 37, count 2 2006.201.20:23:43.06#ibcon#about to read 5, iclass 37, count 2 2006.201.20:23:43.06#ibcon#read 5, iclass 37, count 2 2006.201.20:23:43.06#ibcon#about to read 6, iclass 37, count 2 2006.201.20:23:43.06#ibcon#read 6, iclass 37, count 2 2006.201.20:23:43.06#ibcon#end of sib2, iclass 37, count 2 2006.201.20:23:43.06#ibcon#*after write, iclass 37, count 2 2006.201.20:23:43.06#ibcon#*before return 0, iclass 37, count 2 2006.201.20:23:43.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:43.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:23:43.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.20:23:43.06#ibcon#ireg 7 cls_cnt 0 2006.201.20:23:43.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:43.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:43.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:43.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.20:23:43.18#ibcon#first serial, iclass 37, count 0 2006.201.20:23:43.18#ibcon#enter sib2, iclass 37, count 0 2006.201.20:23:43.18#ibcon#flushed, iclass 37, count 0 2006.201.20:23:43.18#ibcon#about to write, iclass 37, count 0 2006.201.20:23:43.18#ibcon#wrote, iclass 37, count 0 2006.201.20:23:43.18#ibcon#about to read 3, iclass 37, count 0 2006.201.20:23:43.21#ibcon#read 3, iclass 37, count 0 2006.201.20:23:43.21#ibcon#about to read 4, iclass 37, count 0 2006.201.20:23:43.21#ibcon#read 4, iclass 37, count 0 2006.201.20:23:43.21#ibcon#about to read 5, iclass 37, count 0 2006.201.20:23:43.21#ibcon#read 5, iclass 37, count 0 2006.201.20:23:43.21#ibcon#about to read 6, iclass 37, count 0 2006.201.20:23:43.21#ibcon#read 6, iclass 37, count 0 2006.201.20:23:43.21#ibcon#end of sib2, iclass 37, count 0 2006.201.20:23:43.21#ibcon#*mode == 0, iclass 37, count 0 2006.201.20:23:43.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.20:23:43.21#ibcon#[27=USB\r\n] 2006.201.20:23:43.21#ibcon#*before write, iclass 37, count 0 2006.201.20:23:43.21#ibcon#enter sib2, iclass 37, count 0 2006.201.20:23:43.21#ibcon#flushed, iclass 37, count 0 2006.201.20:23:43.21#ibcon#about to write, iclass 37, count 0 2006.201.20:23:43.21#ibcon#wrote, iclass 37, count 0 2006.201.20:23:43.21#ibcon#about to read 3, iclass 37, count 0 2006.201.20:23:43.24#ibcon#read 3, iclass 37, count 0 2006.201.20:23:43.24#ibcon#about to read 4, iclass 37, count 0 2006.201.20:23:43.24#ibcon#read 4, iclass 37, count 0 2006.201.20:23:43.24#ibcon#about to read 5, iclass 37, count 0 2006.201.20:23:43.24#ibcon#read 5, iclass 37, count 0 2006.201.20:23:43.24#ibcon#about to read 6, iclass 37, count 0 2006.201.20:23:43.24#ibcon#read 6, iclass 37, count 0 2006.201.20:23:43.24#ibcon#end of sib2, iclass 37, count 0 2006.201.20:23:43.24#ibcon#*after write, iclass 37, count 0 2006.201.20:23:43.24#ibcon#*before return 0, iclass 37, count 0 2006.201.20:23:43.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:43.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:23:43.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.20:23:43.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.20:23:43.24$vck44/vabw=wide 2006.201.20:23:43.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.20:23:43.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.20:23:43.24#ibcon#ireg 8 cls_cnt 0 2006.201.20:23:43.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:43.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:43.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:43.24#ibcon#enter wrdev, iclass 39, count 0 2006.201.20:23:43.24#ibcon#first serial, iclass 39, count 0 2006.201.20:23:43.24#ibcon#enter sib2, iclass 39, count 0 2006.201.20:23:43.24#ibcon#flushed, iclass 39, count 0 2006.201.20:23:43.24#ibcon#about to write, iclass 39, count 0 2006.201.20:23:43.24#ibcon#wrote, iclass 39, count 0 2006.201.20:23:43.24#ibcon#about to read 3, iclass 39, count 0 2006.201.20:23:43.26#ibcon#read 3, iclass 39, count 0 2006.201.20:23:43.26#ibcon#about to read 4, iclass 39, count 0 2006.201.20:23:43.26#ibcon#read 4, iclass 39, count 0 2006.201.20:23:43.26#ibcon#about to read 5, iclass 39, count 0 2006.201.20:23:43.26#ibcon#read 5, iclass 39, count 0 2006.201.20:23:43.26#ibcon#about to read 6, iclass 39, count 0 2006.201.20:23:43.26#ibcon#read 6, iclass 39, count 0 2006.201.20:23:43.26#ibcon#end of sib2, iclass 39, count 0 2006.201.20:23:43.26#ibcon#*mode == 0, iclass 39, count 0 2006.201.20:23:43.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.20:23:43.26#ibcon#[25=BW32\r\n] 2006.201.20:23:43.26#ibcon#*before write, iclass 39, count 0 2006.201.20:23:43.26#ibcon#enter sib2, iclass 39, count 0 2006.201.20:23:43.26#ibcon#flushed, iclass 39, count 0 2006.201.20:23:43.26#ibcon#about to write, iclass 39, count 0 2006.201.20:23:43.26#ibcon#wrote, iclass 39, count 0 2006.201.20:23:43.26#ibcon#about to read 3, iclass 39, count 0 2006.201.20:23:43.29#abcon#<5=/03 1.7 3.2 20.101001002.3\r\n> 2006.201.20:23:43.29#ibcon#read 3, iclass 39, count 0 2006.201.20:23:43.29#ibcon#about to read 4, iclass 39, count 0 2006.201.20:23:43.29#ibcon#read 4, iclass 39, count 0 2006.201.20:23:43.29#ibcon#about to read 5, iclass 39, count 0 2006.201.20:23:43.29#ibcon#read 5, iclass 39, count 0 2006.201.20:23:43.29#ibcon#about to read 6, iclass 39, count 0 2006.201.20:23:43.29#ibcon#read 6, iclass 39, count 0 2006.201.20:23:43.29#ibcon#end of sib2, iclass 39, count 0 2006.201.20:23:43.29#ibcon#*after write, iclass 39, count 0 2006.201.20:23:43.29#ibcon#*before return 0, iclass 39, count 0 2006.201.20:23:43.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:43.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:23:43.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.20:23:43.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.20:23:43.29$vck44/vbbw=wide 2006.201.20:23:43.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.20:23:43.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.20:23:43.29#ibcon#ireg 8 cls_cnt 0 2006.201.20:23:43.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:23:43.31#abcon#{5=INTERFACE CLEAR} 2006.201.20:23:43.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:23:43.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:23:43.36#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:23:43.36#ibcon#first serial, iclass 6, count 0 2006.201.20:23:43.36#ibcon#enter sib2, iclass 6, count 0 2006.201.20:23:43.36#ibcon#flushed, iclass 6, count 0 2006.201.20:23:43.36#ibcon#about to write, iclass 6, count 0 2006.201.20:23:43.36#ibcon#wrote, iclass 6, count 0 2006.201.20:23:43.36#ibcon#about to read 3, iclass 6, count 0 2006.201.20:23:43.37#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:23:43.38#ibcon#read 3, iclass 6, count 0 2006.201.20:23:43.38#ibcon#about to read 4, iclass 6, count 0 2006.201.20:23:43.38#ibcon#read 4, iclass 6, count 0 2006.201.20:23:43.38#ibcon#about to read 5, iclass 6, count 0 2006.201.20:23:43.38#ibcon#read 5, iclass 6, count 0 2006.201.20:23:43.38#ibcon#about to read 6, iclass 6, count 0 2006.201.20:23:43.38#ibcon#read 6, iclass 6, count 0 2006.201.20:23:43.38#ibcon#end of sib2, iclass 6, count 0 2006.201.20:23:43.38#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:23:43.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:23:43.38#ibcon#[27=BW32\r\n] 2006.201.20:23:43.38#ibcon#*before write, iclass 6, count 0 2006.201.20:23:43.38#ibcon#enter sib2, iclass 6, count 0 2006.201.20:23:43.38#ibcon#flushed, iclass 6, count 0 2006.201.20:23:43.38#ibcon#about to write, iclass 6, count 0 2006.201.20:23:43.38#ibcon#wrote, iclass 6, count 0 2006.201.20:23:43.38#ibcon#about to read 3, iclass 6, count 0 2006.201.20:23:43.41#ibcon#read 3, iclass 6, count 0 2006.201.20:23:43.41#ibcon#about to read 4, iclass 6, count 0 2006.201.20:23:43.41#ibcon#read 4, iclass 6, count 0 2006.201.20:23:43.41#ibcon#about to read 5, iclass 6, count 0 2006.201.20:23:43.41#ibcon#read 5, iclass 6, count 0 2006.201.20:23:43.41#ibcon#about to read 6, iclass 6, count 0 2006.201.20:23:43.41#ibcon#read 6, iclass 6, count 0 2006.201.20:23:43.41#ibcon#end of sib2, iclass 6, count 0 2006.201.20:23:43.41#ibcon#*after write, iclass 6, count 0 2006.201.20:23:43.41#ibcon#*before return 0, iclass 6, count 0 2006.201.20:23:43.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:23:43.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:23:43.41#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:23:43.41#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:23:43.41$setupk4/ifdk4 2006.201.20:23:43.41$ifdk4/lo= 2006.201.20:23:43.41$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:23:43.41$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:23:43.41$ifdk4/patch= 2006.201.20:23:43.41$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:23:43.41$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:23:43.41$setupk4/!*+20s 2006.201.20:23:49.14#trakl#Source acquired 2006.201.20:23:51.14#flagr#flagr/antenna,acquired 2006.201.20:23:53.47#abcon#<5=/03 1.7 3.2 20.101001002.3\r\n> 2006.201.20:23:53.49#abcon#{5=INTERFACE CLEAR} 2006.201.20:23:53.55#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:23:57.88$setupk4/"tpicd 2006.201.20:23:57.88$setupk4/echo=off 2006.201.20:23:57.88$setupk4/xlog=off 2006.201.20:23:57.88:!2006.201.20:29:14 2006.201.20:29:14.00:preob 2006.201.20:29:14.14/onsource/TRACKING 2006.201.20:29:14.14:!2006.201.20:29:24 2006.201.20:29:24.00:"tape 2006.201.20:29:24.00:"st=record 2006.201.20:29:24.00:data_valid=on 2006.201.20:29:24.00:midob 2006.201.20:29:24.14/onsource/TRACKING 2006.201.20:29:24.14/wx/20.09,1002.3,100 2006.201.20:29:24.28/cable/+6.4821E-03 2006.201.20:29:25.37/va/01,08,usb,yes,42,45 2006.201.20:29:25.37/va/02,07,usb,yes,45,46 2006.201.20:29:25.37/va/03,08,usb,yes,41,43 2006.201.20:29:25.37/va/04,07,usb,yes,47,49 2006.201.20:29:25.37/va/05,04,usb,yes,42,43 2006.201.20:29:25.37/va/06,05,usb,yes,42,42 2006.201.20:29:25.37/va/07,05,usb,yes,41,43 2006.201.20:29:25.37/va/08,04,usb,yes,41,48 2006.201.20:29:25.60/valo/01,524.99,yes,locked 2006.201.20:29:25.60/valo/02,534.99,yes,locked 2006.201.20:29:25.60/valo/03,564.99,yes,locked 2006.201.20:29:25.60/valo/04,624.99,yes,locked 2006.201.20:29:25.60/valo/05,734.99,yes,locked 2006.201.20:29:25.60/valo/06,814.99,yes,locked 2006.201.20:29:25.60/valo/07,864.99,yes,locked 2006.201.20:29:25.60/valo/08,884.99,yes,locked 2006.201.20:29:26.69/vb/01,04,usb,yes,30,28 2006.201.20:29:26.69/vb/02,05,usb,yes,28,28 2006.201.20:29:26.69/vb/03,04,usb,yes,29,32 2006.201.20:29:26.69/vb/04,05,usb,yes,30,28 2006.201.20:29:26.69/vb/05,04,usb,yes,26,28 2006.201.20:29:26.69/vb/06,04,usb,yes,30,27 2006.201.20:29:26.69/vb/07,04,usb,yes,30,30 2006.201.20:29:26.69/vb/08,04,usb,yes,28,31 2006.201.20:29:26.92/vblo/01,629.99,yes,locked 2006.201.20:29:26.92/vblo/02,634.99,yes,locked 2006.201.20:29:26.92/vblo/03,649.99,yes,locked 2006.201.20:29:26.92/vblo/04,679.99,yes,locked 2006.201.20:29:26.92/vblo/05,709.99,yes,locked 2006.201.20:29:26.92/vblo/06,719.99,yes,locked 2006.201.20:29:26.92/vblo/07,734.99,yes,locked 2006.201.20:29:26.92/vblo/08,744.99,yes,locked 2006.201.20:29:27.07/vabw/8 2006.201.20:29:27.22/vbbw/8 2006.201.20:29:27.31/xfe/off,on,15.2 2006.201.20:29:27.69/ifatt/23,28,28,28 2006.201.20:29:28.06/fmout-gps/S +4.57E-07 2006.201.20:29:28.10:!2006.201.20:30:44 2006.201.20:30:44.00:data_valid=off 2006.201.20:30:44.00:"et 2006.201.20:30:44.00:!+3s 2006.201.20:30:47.02:"tape 2006.201.20:30:47.02:postob 2006.201.20:30:47.12/cable/+6.4822E-03 2006.201.20:30:47.12/wx/20.08,1002.4,100 2006.201.20:30:47.19/fmout-gps/S +4.57E-07 2006.201.20:30:47.19:scan_name=201-2034,jd0607,80 2006.201.20:30:47.19:source=2121+053,212344.52,053522.1,2000.0,ccw 2006.201.20:30:48.14#flagr#flagr/antenna,new-source 2006.201.20:30:48.14:checkk5 2006.201.20:30:48.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:30:48.92/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:30:49.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:30:49.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:30:50.04/chk_obsdata//k5ts1/T2012029??a.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.20:30:50.40/chk_obsdata//k5ts2/T2012029??b.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.20:30:50.77/chk_obsdata//k5ts3/T2012029??c.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.20:30:51.14/chk_obsdata//k5ts4/T2012029??d.dat file size is correct (nominal:320MB, actual:320MB). 2006.201.20:30:51.84/k5log//k5ts1_log_newline 2006.201.20:30:52.53/k5log//k5ts2_log_newline 2006.201.20:30:53.23/k5log//k5ts3_log_newline 2006.201.20:30:53.93/k5log//k5ts4_log_newline 2006.201.20:30:53.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:30:53.96:setupk4=1 2006.201.20:30:53.96$setupk4/echo=on 2006.201.20:30:53.96$setupk4/pcalon 2006.201.20:30:53.96$pcalon/"no phase cal control is implemented here 2006.201.20:30:53.96$setupk4/"tpicd=stop 2006.201.20:30:53.96$setupk4/"rec=synch_on 2006.201.20:30:53.96$setupk4/"rec_mode=128 2006.201.20:30:53.96$setupk4/!* 2006.201.20:30:53.96$setupk4/recpk4 2006.201.20:30:53.96$recpk4/recpatch= 2006.201.20:30:53.96$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:30:53.96$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:30:53.96$setupk4/vck44 2006.201.20:30:53.96$vck44/valo=1,524.99 2006.201.20:30:53.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.20:30:53.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.20:30:53.96#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:53.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:53.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:53.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:53.96#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:30:53.96#ibcon#first serial, iclass 38, count 0 2006.201.20:30:53.96#ibcon#enter sib2, iclass 38, count 0 2006.201.20:30:53.96#ibcon#flushed, iclass 38, count 0 2006.201.20:30:53.96#ibcon#about to write, iclass 38, count 0 2006.201.20:30:53.96#ibcon#wrote, iclass 38, count 0 2006.201.20:30:53.96#ibcon#about to read 3, iclass 38, count 0 2006.201.20:30:53.98#ibcon#read 3, iclass 38, count 0 2006.201.20:30:53.98#ibcon#about to read 4, iclass 38, count 0 2006.201.20:30:53.98#ibcon#read 4, iclass 38, count 0 2006.201.20:30:53.98#ibcon#about to read 5, iclass 38, count 0 2006.201.20:30:53.98#ibcon#read 5, iclass 38, count 0 2006.201.20:30:53.98#ibcon#about to read 6, iclass 38, count 0 2006.201.20:30:53.98#ibcon#read 6, iclass 38, count 0 2006.201.20:30:53.98#ibcon#end of sib2, iclass 38, count 0 2006.201.20:30:53.98#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:30:53.98#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:30:53.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:30:53.98#ibcon#*before write, iclass 38, count 0 2006.201.20:30:53.98#ibcon#enter sib2, iclass 38, count 0 2006.201.20:30:53.98#ibcon#flushed, iclass 38, count 0 2006.201.20:30:53.98#ibcon#about to write, iclass 38, count 0 2006.201.20:30:53.98#ibcon#wrote, iclass 38, count 0 2006.201.20:30:53.98#ibcon#about to read 3, iclass 38, count 0 2006.201.20:30:54.03#ibcon#read 3, iclass 38, count 0 2006.201.20:30:54.03#ibcon#about to read 4, iclass 38, count 0 2006.201.20:30:54.03#ibcon#read 4, iclass 38, count 0 2006.201.20:30:54.03#ibcon#about to read 5, iclass 38, count 0 2006.201.20:30:54.03#ibcon#read 5, iclass 38, count 0 2006.201.20:30:54.03#ibcon#about to read 6, iclass 38, count 0 2006.201.20:30:54.03#ibcon#read 6, iclass 38, count 0 2006.201.20:30:54.03#ibcon#end of sib2, iclass 38, count 0 2006.201.20:30:54.03#ibcon#*after write, iclass 38, count 0 2006.201.20:30:54.03#ibcon#*before return 0, iclass 38, count 0 2006.201.20:30:54.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:54.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:54.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:30:54.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:30:54.03$vck44/va=1,8 2006.201.20:30:54.03#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.20:30:54.03#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.20:30:54.03#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:54.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:54.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:54.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:54.03#ibcon#enter wrdev, iclass 40, count 2 2006.201.20:30:54.03#ibcon#first serial, iclass 40, count 2 2006.201.20:30:54.03#ibcon#enter sib2, iclass 40, count 2 2006.201.20:30:54.03#ibcon#flushed, iclass 40, count 2 2006.201.20:30:54.03#ibcon#about to write, iclass 40, count 2 2006.201.20:30:54.03#ibcon#wrote, iclass 40, count 2 2006.201.20:30:54.03#ibcon#about to read 3, iclass 40, count 2 2006.201.20:30:54.05#ibcon#read 3, iclass 40, count 2 2006.201.20:30:54.05#ibcon#about to read 4, iclass 40, count 2 2006.201.20:30:54.05#ibcon#read 4, iclass 40, count 2 2006.201.20:30:54.05#ibcon#about to read 5, iclass 40, count 2 2006.201.20:30:54.05#ibcon#read 5, iclass 40, count 2 2006.201.20:30:54.05#ibcon#about to read 6, iclass 40, count 2 2006.201.20:30:54.05#ibcon#read 6, iclass 40, count 2 2006.201.20:30:54.05#ibcon#end of sib2, iclass 40, count 2 2006.201.20:30:54.05#ibcon#*mode == 0, iclass 40, count 2 2006.201.20:30:54.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.20:30:54.05#ibcon#[25=AT01-08\r\n] 2006.201.20:30:54.05#ibcon#*before write, iclass 40, count 2 2006.201.20:30:54.05#ibcon#enter sib2, iclass 40, count 2 2006.201.20:30:54.05#ibcon#flushed, iclass 40, count 2 2006.201.20:30:54.05#ibcon#about to write, iclass 40, count 2 2006.201.20:30:54.05#ibcon#wrote, iclass 40, count 2 2006.201.20:30:54.05#ibcon#about to read 3, iclass 40, count 2 2006.201.20:30:54.08#ibcon#read 3, iclass 40, count 2 2006.201.20:30:54.08#ibcon#about to read 4, iclass 40, count 2 2006.201.20:30:54.08#ibcon#read 4, iclass 40, count 2 2006.201.20:30:54.08#ibcon#about to read 5, iclass 40, count 2 2006.201.20:30:54.08#ibcon#read 5, iclass 40, count 2 2006.201.20:30:54.08#ibcon#about to read 6, iclass 40, count 2 2006.201.20:30:54.08#ibcon#read 6, iclass 40, count 2 2006.201.20:30:54.08#ibcon#end of sib2, iclass 40, count 2 2006.201.20:30:54.08#ibcon#*after write, iclass 40, count 2 2006.201.20:30:54.08#ibcon#*before return 0, iclass 40, count 2 2006.201.20:30:54.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:54.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:54.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.20:30:54.08#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:54.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:54.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:54.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:54.20#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:30:54.20#ibcon#first serial, iclass 40, count 0 2006.201.20:30:54.20#ibcon#enter sib2, iclass 40, count 0 2006.201.20:30:54.20#ibcon#flushed, iclass 40, count 0 2006.201.20:30:54.20#ibcon#about to write, iclass 40, count 0 2006.201.20:30:54.20#ibcon#wrote, iclass 40, count 0 2006.201.20:30:54.20#ibcon#about to read 3, iclass 40, count 0 2006.201.20:30:54.22#ibcon#read 3, iclass 40, count 0 2006.201.20:30:54.22#ibcon#about to read 4, iclass 40, count 0 2006.201.20:30:54.22#ibcon#read 4, iclass 40, count 0 2006.201.20:30:54.22#ibcon#about to read 5, iclass 40, count 0 2006.201.20:30:54.22#ibcon#read 5, iclass 40, count 0 2006.201.20:30:54.22#ibcon#about to read 6, iclass 40, count 0 2006.201.20:30:54.22#ibcon#read 6, iclass 40, count 0 2006.201.20:30:54.22#ibcon#end of sib2, iclass 40, count 0 2006.201.20:30:54.22#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:30:54.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:30:54.22#ibcon#[25=USB\r\n] 2006.201.20:30:54.22#ibcon#*before write, iclass 40, count 0 2006.201.20:30:54.22#ibcon#enter sib2, iclass 40, count 0 2006.201.20:30:54.22#ibcon#flushed, iclass 40, count 0 2006.201.20:30:54.22#ibcon#about to write, iclass 40, count 0 2006.201.20:30:54.22#ibcon#wrote, iclass 40, count 0 2006.201.20:30:54.22#ibcon#about to read 3, iclass 40, count 0 2006.201.20:30:54.25#ibcon#read 3, iclass 40, count 0 2006.201.20:30:54.25#ibcon#about to read 4, iclass 40, count 0 2006.201.20:30:54.25#ibcon#read 4, iclass 40, count 0 2006.201.20:30:54.25#ibcon#about to read 5, iclass 40, count 0 2006.201.20:30:54.25#ibcon#read 5, iclass 40, count 0 2006.201.20:30:54.25#ibcon#about to read 6, iclass 40, count 0 2006.201.20:30:54.25#ibcon#read 6, iclass 40, count 0 2006.201.20:30:54.25#ibcon#end of sib2, iclass 40, count 0 2006.201.20:30:54.25#ibcon#*after write, iclass 40, count 0 2006.201.20:30:54.25#ibcon#*before return 0, iclass 40, count 0 2006.201.20:30:54.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:54.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:54.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:30:54.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:30:54.25$vck44/valo=2,534.99 2006.201.20:30:54.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.20:30:54.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.20:30:54.25#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:54.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:54.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:54.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:54.25#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:30:54.25#ibcon#first serial, iclass 4, count 0 2006.201.20:30:54.25#ibcon#enter sib2, iclass 4, count 0 2006.201.20:30:54.25#ibcon#flushed, iclass 4, count 0 2006.201.20:30:54.25#ibcon#about to write, iclass 4, count 0 2006.201.20:30:54.25#ibcon#wrote, iclass 4, count 0 2006.201.20:30:54.25#ibcon#about to read 3, iclass 4, count 0 2006.201.20:30:54.27#ibcon#read 3, iclass 4, count 0 2006.201.20:30:54.27#ibcon#about to read 4, iclass 4, count 0 2006.201.20:30:54.27#ibcon#read 4, iclass 4, count 0 2006.201.20:30:54.27#ibcon#about to read 5, iclass 4, count 0 2006.201.20:30:54.27#ibcon#read 5, iclass 4, count 0 2006.201.20:30:54.27#ibcon#about to read 6, iclass 4, count 0 2006.201.20:30:54.27#ibcon#read 6, iclass 4, count 0 2006.201.20:30:54.27#ibcon#end of sib2, iclass 4, count 0 2006.201.20:30:54.27#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:30:54.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:30:54.27#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:30:54.27#ibcon#*before write, iclass 4, count 0 2006.201.20:30:54.27#ibcon#enter sib2, iclass 4, count 0 2006.201.20:30:54.27#ibcon#flushed, iclass 4, count 0 2006.201.20:30:54.27#ibcon#about to write, iclass 4, count 0 2006.201.20:30:54.27#ibcon#wrote, iclass 4, count 0 2006.201.20:30:54.27#ibcon#about to read 3, iclass 4, count 0 2006.201.20:30:54.32#ibcon#read 3, iclass 4, count 0 2006.201.20:30:54.32#ibcon#about to read 4, iclass 4, count 0 2006.201.20:30:54.32#ibcon#read 4, iclass 4, count 0 2006.201.20:30:54.32#ibcon#about to read 5, iclass 4, count 0 2006.201.20:30:54.32#ibcon#read 5, iclass 4, count 0 2006.201.20:30:54.32#ibcon#about to read 6, iclass 4, count 0 2006.201.20:30:54.32#ibcon#read 6, iclass 4, count 0 2006.201.20:30:54.32#ibcon#end of sib2, iclass 4, count 0 2006.201.20:30:54.32#ibcon#*after write, iclass 4, count 0 2006.201.20:30:54.32#ibcon#*before return 0, iclass 4, count 0 2006.201.20:30:54.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:54.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:54.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:30:54.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:30:54.32$vck44/va=2,7 2006.201.20:30:54.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.20:30:54.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.20:30:54.32#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:54.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:54.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:54.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:54.37#ibcon#enter wrdev, iclass 6, count 2 2006.201.20:30:54.37#ibcon#first serial, iclass 6, count 2 2006.201.20:30:54.37#ibcon#enter sib2, iclass 6, count 2 2006.201.20:30:54.37#ibcon#flushed, iclass 6, count 2 2006.201.20:30:54.37#ibcon#about to write, iclass 6, count 2 2006.201.20:30:54.37#ibcon#wrote, iclass 6, count 2 2006.201.20:30:54.37#ibcon#about to read 3, iclass 6, count 2 2006.201.20:30:54.39#ibcon#read 3, iclass 6, count 2 2006.201.20:30:54.39#ibcon#about to read 4, iclass 6, count 2 2006.201.20:30:54.39#ibcon#read 4, iclass 6, count 2 2006.201.20:30:54.39#ibcon#about to read 5, iclass 6, count 2 2006.201.20:30:54.39#ibcon#read 5, iclass 6, count 2 2006.201.20:30:54.39#ibcon#about to read 6, iclass 6, count 2 2006.201.20:30:54.39#ibcon#read 6, iclass 6, count 2 2006.201.20:30:54.39#ibcon#end of sib2, iclass 6, count 2 2006.201.20:30:54.39#ibcon#*mode == 0, iclass 6, count 2 2006.201.20:30:54.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.20:30:54.39#ibcon#[25=AT02-07\r\n] 2006.201.20:30:54.39#ibcon#*before write, iclass 6, count 2 2006.201.20:30:54.39#ibcon#enter sib2, iclass 6, count 2 2006.201.20:30:54.39#ibcon#flushed, iclass 6, count 2 2006.201.20:30:54.39#ibcon#about to write, iclass 6, count 2 2006.201.20:30:54.39#ibcon#wrote, iclass 6, count 2 2006.201.20:30:54.39#ibcon#about to read 3, iclass 6, count 2 2006.201.20:30:54.42#ibcon#read 3, iclass 6, count 2 2006.201.20:30:54.42#ibcon#about to read 4, iclass 6, count 2 2006.201.20:30:54.42#ibcon#read 4, iclass 6, count 2 2006.201.20:30:54.42#ibcon#about to read 5, iclass 6, count 2 2006.201.20:30:54.42#ibcon#read 5, iclass 6, count 2 2006.201.20:30:54.42#ibcon#about to read 6, iclass 6, count 2 2006.201.20:30:54.42#ibcon#read 6, iclass 6, count 2 2006.201.20:30:54.42#ibcon#end of sib2, iclass 6, count 2 2006.201.20:30:54.42#ibcon#*after write, iclass 6, count 2 2006.201.20:30:54.42#ibcon#*before return 0, iclass 6, count 2 2006.201.20:30:54.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:54.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:54.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.20:30:54.42#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:54.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:54.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:54.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:54.54#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:30:54.54#ibcon#first serial, iclass 6, count 0 2006.201.20:30:54.54#ibcon#enter sib2, iclass 6, count 0 2006.201.20:30:54.54#ibcon#flushed, iclass 6, count 0 2006.201.20:30:54.54#ibcon#about to write, iclass 6, count 0 2006.201.20:30:54.54#ibcon#wrote, iclass 6, count 0 2006.201.20:30:54.54#ibcon#about to read 3, iclass 6, count 0 2006.201.20:30:54.56#ibcon#read 3, iclass 6, count 0 2006.201.20:30:54.56#ibcon#about to read 4, iclass 6, count 0 2006.201.20:30:54.56#ibcon#read 4, iclass 6, count 0 2006.201.20:30:54.56#ibcon#about to read 5, iclass 6, count 0 2006.201.20:30:54.56#ibcon#read 5, iclass 6, count 0 2006.201.20:30:54.56#ibcon#about to read 6, iclass 6, count 0 2006.201.20:30:54.56#ibcon#read 6, iclass 6, count 0 2006.201.20:30:54.56#ibcon#end of sib2, iclass 6, count 0 2006.201.20:30:54.56#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:30:54.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:30:54.56#ibcon#[25=USB\r\n] 2006.201.20:30:54.56#ibcon#*before write, iclass 6, count 0 2006.201.20:30:54.56#ibcon#enter sib2, iclass 6, count 0 2006.201.20:30:54.56#ibcon#flushed, iclass 6, count 0 2006.201.20:30:54.56#ibcon#about to write, iclass 6, count 0 2006.201.20:30:54.56#ibcon#wrote, iclass 6, count 0 2006.201.20:30:54.56#ibcon#about to read 3, iclass 6, count 0 2006.201.20:30:54.59#ibcon#read 3, iclass 6, count 0 2006.201.20:30:54.59#ibcon#about to read 4, iclass 6, count 0 2006.201.20:30:54.59#ibcon#read 4, iclass 6, count 0 2006.201.20:30:54.59#ibcon#about to read 5, iclass 6, count 0 2006.201.20:30:54.59#ibcon#read 5, iclass 6, count 0 2006.201.20:30:54.59#ibcon#about to read 6, iclass 6, count 0 2006.201.20:30:54.59#ibcon#read 6, iclass 6, count 0 2006.201.20:30:54.59#ibcon#end of sib2, iclass 6, count 0 2006.201.20:30:54.59#ibcon#*after write, iclass 6, count 0 2006.201.20:30:54.59#ibcon#*before return 0, iclass 6, count 0 2006.201.20:30:54.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:54.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:54.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:30:54.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:30:54.59$vck44/valo=3,564.99 2006.201.20:30:54.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.20:30:54.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.20:30:54.59#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:54.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:54.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:54.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:54.59#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:30:54.59#ibcon#first serial, iclass 10, count 0 2006.201.20:30:54.59#ibcon#enter sib2, iclass 10, count 0 2006.201.20:30:54.59#ibcon#flushed, iclass 10, count 0 2006.201.20:30:54.59#ibcon#about to write, iclass 10, count 0 2006.201.20:30:54.59#ibcon#wrote, iclass 10, count 0 2006.201.20:30:54.59#ibcon#about to read 3, iclass 10, count 0 2006.201.20:30:54.61#ibcon#read 3, iclass 10, count 0 2006.201.20:30:54.61#ibcon#about to read 4, iclass 10, count 0 2006.201.20:30:54.61#ibcon#read 4, iclass 10, count 0 2006.201.20:30:54.61#ibcon#about to read 5, iclass 10, count 0 2006.201.20:30:54.61#ibcon#read 5, iclass 10, count 0 2006.201.20:30:54.61#ibcon#about to read 6, iclass 10, count 0 2006.201.20:30:54.61#ibcon#read 6, iclass 10, count 0 2006.201.20:30:54.61#ibcon#end of sib2, iclass 10, count 0 2006.201.20:30:54.61#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:30:54.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:30:54.61#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:30:54.61#ibcon#*before write, iclass 10, count 0 2006.201.20:30:54.61#ibcon#enter sib2, iclass 10, count 0 2006.201.20:30:54.61#ibcon#flushed, iclass 10, count 0 2006.201.20:30:54.61#ibcon#about to write, iclass 10, count 0 2006.201.20:30:54.61#ibcon#wrote, iclass 10, count 0 2006.201.20:30:54.61#ibcon#about to read 3, iclass 10, count 0 2006.201.20:30:54.66#ibcon#read 3, iclass 10, count 0 2006.201.20:30:54.66#ibcon#about to read 4, iclass 10, count 0 2006.201.20:30:54.66#ibcon#read 4, iclass 10, count 0 2006.201.20:30:54.66#ibcon#about to read 5, iclass 10, count 0 2006.201.20:30:54.66#ibcon#read 5, iclass 10, count 0 2006.201.20:30:54.66#ibcon#about to read 6, iclass 10, count 0 2006.201.20:30:54.66#ibcon#read 6, iclass 10, count 0 2006.201.20:30:54.66#ibcon#end of sib2, iclass 10, count 0 2006.201.20:30:54.66#ibcon#*after write, iclass 10, count 0 2006.201.20:30:54.66#ibcon#*before return 0, iclass 10, count 0 2006.201.20:30:54.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:54.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:54.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:30:54.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:30:54.66$vck44/va=3,8 2006.201.20:30:54.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.20:30:54.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.20:30:54.66#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:54.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:54.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:54.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:54.71#ibcon#enter wrdev, iclass 12, count 2 2006.201.20:30:54.71#ibcon#first serial, iclass 12, count 2 2006.201.20:30:54.71#ibcon#enter sib2, iclass 12, count 2 2006.201.20:30:54.71#ibcon#flushed, iclass 12, count 2 2006.201.20:30:54.71#ibcon#about to write, iclass 12, count 2 2006.201.20:30:54.71#ibcon#wrote, iclass 12, count 2 2006.201.20:30:54.71#ibcon#about to read 3, iclass 12, count 2 2006.201.20:30:54.73#ibcon#read 3, iclass 12, count 2 2006.201.20:30:54.73#ibcon#about to read 4, iclass 12, count 2 2006.201.20:30:54.73#ibcon#read 4, iclass 12, count 2 2006.201.20:30:54.73#ibcon#about to read 5, iclass 12, count 2 2006.201.20:30:54.73#ibcon#read 5, iclass 12, count 2 2006.201.20:30:54.73#ibcon#about to read 6, iclass 12, count 2 2006.201.20:30:54.73#ibcon#read 6, iclass 12, count 2 2006.201.20:30:54.73#ibcon#end of sib2, iclass 12, count 2 2006.201.20:30:54.73#ibcon#*mode == 0, iclass 12, count 2 2006.201.20:30:54.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.20:30:54.73#ibcon#[25=AT03-08\r\n] 2006.201.20:30:54.73#ibcon#*before write, iclass 12, count 2 2006.201.20:30:54.73#ibcon#enter sib2, iclass 12, count 2 2006.201.20:30:54.73#ibcon#flushed, iclass 12, count 2 2006.201.20:30:54.73#ibcon#about to write, iclass 12, count 2 2006.201.20:30:54.73#ibcon#wrote, iclass 12, count 2 2006.201.20:30:54.73#ibcon#about to read 3, iclass 12, count 2 2006.201.20:30:54.76#ibcon#read 3, iclass 12, count 2 2006.201.20:30:54.76#ibcon#about to read 4, iclass 12, count 2 2006.201.20:30:54.76#ibcon#read 4, iclass 12, count 2 2006.201.20:30:54.76#ibcon#about to read 5, iclass 12, count 2 2006.201.20:30:54.76#ibcon#read 5, iclass 12, count 2 2006.201.20:30:54.76#ibcon#about to read 6, iclass 12, count 2 2006.201.20:30:54.76#ibcon#read 6, iclass 12, count 2 2006.201.20:30:54.76#ibcon#end of sib2, iclass 12, count 2 2006.201.20:30:54.76#ibcon#*after write, iclass 12, count 2 2006.201.20:30:54.76#ibcon#*before return 0, iclass 12, count 2 2006.201.20:30:54.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:54.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:54.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.20:30:54.76#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:54.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:54.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:54.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:54.88#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:30:54.88#ibcon#first serial, iclass 12, count 0 2006.201.20:30:54.88#ibcon#enter sib2, iclass 12, count 0 2006.201.20:30:54.88#ibcon#flushed, iclass 12, count 0 2006.201.20:30:54.88#ibcon#about to write, iclass 12, count 0 2006.201.20:30:54.88#ibcon#wrote, iclass 12, count 0 2006.201.20:30:54.88#ibcon#about to read 3, iclass 12, count 0 2006.201.20:30:54.90#ibcon#read 3, iclass 12, count 0 2006.201.20:30:54.90#ibcon#about to read 4, iclass 12, count 0 2006.201.20:30:54.90#ibcon#read 4, iclass 12, count 0 2006.201.20:30:54.90#ibcon#about to read 5, iclass 12, count 0 2006.201.20:30:54.90#ibcon#read 5, iclass 12, count 0 2006.201.20:30:54.90#ibcon#about to read 6, iclass 12, count 0 2006.201.20:30:54.90#ibcon#read 6, iclass 12, count 0 2006.201.20:30:54.90#ibcon#end of sib2, iclass 12, count 0 2006.201.20:30:54.90#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:30:54.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:30:54.90#ibcon#[25=USB\r\n] 2006.201.20:30:54.90#ibcon#*before write, iclass 12, count 0 2006.201.20:30:54.90#ibcon#enter sib2, iclass 12, count 0 2006.201.20:30:54.90#ibcon#flushed, iclass 12, count 0 2006.201.20:30:54.90#ibcon#about to write, iclass 12, count 0 2006.201.20:30:54.90#ibcon#wrote, iclass 12, count 0 2006.201.20:30:54.90#ibcon#about to read 3, iclass 12, count 0 2006.201.20:30:54.93#ibcon#read 3, iclass 12, count 0 2006.201.20:30:54.93#ibcon#about to read 4, iclass 12, count 0 2006.201.20:30:54.93#ibcon#read 4, iclass 12, count 0 2006.201.20:30:54.93#ibcon#about to read 5, iclass 12, count 0 2006.201.20:30:54.93#ibcon#read 5, iclass 12, count 0 2006.201.20:30:54.93#ibcon#about to read 6, iclass 12, count 0 2006.201.20:30:54.93#ibcon#read 6, iclass 12, count 0 2006.201.20:30:54.93#ibcon#end of sib2, iclass 12, count 0 2006.201.20:30:54.93#ibcon#*after write, iclass 12, count 0 2006.201.20:30:54.93#ibcon#*before return 0, iclass 12, count 0 2006.201.20:30:54.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:54.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:54.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:30:54.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:30:54.93$vck44/valo=4,624.99 2006.201.20:30:54.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.20:30:54.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.20:30:54.93#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:54.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:54.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:54.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:54.93#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:30:54.93#ibcon#first serial, iclass 14, count 0 2006.201.20:30:54.93#ibcon#enter sib2, iclass 14, count 0 2006.201.20:30:54.93#ibcon#flushed, iclass 14, count 0 2006.201.20:30:54.93#ibcon#about to write, iclass 14, count 0 2006.201.20:30:54.93#ibcon#wrote, iclass 14, count 0 2006.201.20:30:54.93#ibcon#about to read 3, iclass 14, count 0 2006.201.20:30:54.95#ibcon#read 3, iclass 14, count 0 2006.201.20:30:54.95#ibcon#about to read 4, iclass 14, count 0 2006.201.20:30:54.95#ibcon#read 4, iclass 14, count 0 2006.201.20:30:54.95#ibcon#about to read 5, iclass 14, count 0 2006.201.20:30:54.95#ibcon#read 5, iclass 14, count 0 2006.201.20:30:54.95#ibcon#about to read 6, iclass 14, count 0 2006.201.20:30:54.95#ibcon#read 6, iclass 14, count 0 2006.201.20:30:54.95#ibcon#end of sib2, iclass 14, count 0 2006.201.20:30:54.95#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:30:54.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:30:54.95#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:30:54.95#ibcon#*before write, iclass 14, count 0 2006.201.20:30:54.95#ibcon#enter sib2, iclass 14, count 0 2006.201.20:30:54.95#ibcon#flushed, iclass 14, count 0 2006.201.20:30:54.95#ibcon#about to write, iclass 14, count 0 2006.201.20:30:54.95#ibcon#wrote, iclass 14, count 0 2006.201.20:30:54.95#ibcon#about to read 3, iclass 14, count 0 2006.201.20:30:55.00#ibcon#read 3, iclass 14, count 0 2006.201.20:30:55.00#ibcon#about to read 4, iclass 14, count 0 2006.201.20:30:55.00#ibcon#read 4, iclass 14, count 0 2006.201.20:30:55.00#ibcon#about to read 5, iclass 14, count 0 2006.201.20:30:55.00#ibcon#read 5, iclass 14, count 0 2006.201.20:30:55.00#ibcon#about to read 6, iclass 14, count 0 2006.201.20:30:55.00#ibcon#read 6, iclass 14, count 0 2006.201.20:30:55.00#ibcon#end of sib2, iclass 14, count 0 2006.201.20:30:55.00#ibcon#*after write, iclass 14, count 0 2006.201.20:30:55.00#ibcon#*before return 0, iclass 14, count 0 2006.201.20:30:55.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:55.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:55.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:30:55.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:30:55.00$vck44/va=4,7 2006.201.20:30:55.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.20:30:55.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.20:30:55.00#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:55.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:55.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:55.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:55.05#ibcon#enter wrdev, iclass 16, count 2 2006.201.20:30:55.05#ibcon#first serial, iclass 16, count 2 2006.201.20:30:55.05#ibcon#enter sib2, iclass 16, count 2 2006.201.20:30:55.05#ibcon#flushed, iclass 16, count 2 2006.201.20:30:55.05#ibcon#about to write, iclass 16, count 2 2006.201.20:30:55.05#ibcon#wrote, iclass 16, count 2 2006.201.20:30:55.05#ibcon#about to read 3, iclass 16, count 2 2006.201.20:30:55.07#ibcon#read 3, iclass 16, count 2 2006.201.20:30:55.07#ibcon#about to read 4, iclass 16, count 2 2006.201.20:30:55.07#ibcon#read 4, iclass 16, count 2 2006.201.20:30:55.07#ibcon#about to read 5, iclass 16, count 2 2006.201.20:30:55.07#ibcon#read 5, iclass 16, count 2 2006.201.20:30:55.07#ibcon#about to read 6, iclass 16, count 2 2006.201.20:30:55.07#ibcon#read 6, iclass 16, count 2 2006.201.20:30:55.07#ibcon#end of sib2, iclass 16, count 2 2006.201.20:30:55.07#ibcon#*mode == 0, iclass 16, count 2 2006.201.20:30:55.07#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.20:30:55.07#ibcon#[25=AT04-07\r\n] 2006.201.20:30:55.07#ibcon#*before write, iclass 16, count 2 2006.201.20:30:55.07#ibcon#enter sib2, iclass 16, count 2 2006.201.20:30:55.07#ibcon#flushed, iclass 16, count 2 2006.201.20:30:55.07#ibcon#about to write, iclass 16, count 2 2006.201.20:30:55.07#ibcon#wrote, iclass 16, count 2 2006.201.20:30:55.07#ibcon#about to read 3, iclass 16, count 2 2006.201.20:30:55.10#ibcon#read 3, iclass 16, count 2 2006.201.20:30:55.10#ibcon#about to read 4, iclass 16, count 2 2006.201.20:30:55.10#ibcon#read 4, iclass 16, count 2 2006.201.20:30:55.10#ibcon#about to read 5, iclass 16, count 2 2006.201.20:30:55.10#ibcon#read 5, iclass 16, count 2 2006.201.20:30:55.10#ibcon#about to read 6, iclass 16, count 2 2006.201.20:30:55.10#ibcon#read 6, iclass 16, count 2 2006.201.20:30:55.10#ibcon#end of sib2, iclass 16, count 2 2006.201.20:30:55.10#ibcon#*after write, iclass 16, count 2 2006.201.20:30:55.10#ibcon#*before return 0, iclass 16, count 2 2006.201.20:30:55.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:55.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:55.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.20:30:55.10#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:55.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:55.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:55.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:55.22#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:30:55.22#ibcon#first serial, iclass 16, count 0 2006.201.20:30:55.22#ibcon#enter sib2, iclass 16, count 0 2006.201.20:30:55.22#ibcon#flushed, iclass 16, count 0 2006.201.20:30:55.22#ibcon#about to write, iclass 16, count 0 2006.201.20:30:55.22#ibcon#wrote, iclass 16, count 0 2006.201.20:30:55.22#ibcon#about to read 3, iclass 16, count 0 2006.201.20:30:55.24#ibcon#read 3, iclass 16, count 0 2006.201.20:30:55.24#ibcon#about to read 4, iclass 16, count 0 2006.201.20:30:55.24#ibcon#read 4, iclass 16, count 0 2006.201.20:30:55.24#ibcon#about to read 5, iclass 16, count 0 2006.201.20:30:55.24#ibcon#read 5, iclass 16, count 0 2006.201.20:30:55.24#ibcon#about to read 6, iclass 16, count 0 2006.201.20:30:55.24#ibcon#read 6, iclass 16, count 0 2006.201.20:30:55.24#ibcon#end of sib2, iclass 16, count 0 2006.201.20:30:55.24#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:30:55.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:30:55.24#ibcon#[25=USB\r\n] 2006.201.20:30:55.24#ibcon#*before write, iclass 16, count 0 2006.201.20:30:55.24#ibcon#enter sib2, iclass 16, count 0 2006.201.20:30:55.24#ibcon#flushed, iclass 16, count 0 2006.201.20:30:55.24#ibcon#about to write, iclass 16, count 0 2006.201.20:30:55.24#ibcon#wrote, iclass 16, count 0 2006.201.20:30:55.24#ibcon#about to read 3, iclass 16, count 0 2006.201.20:30:55.27#ibcon#read 3, iclass 16, count 0 2006.201.20:30:55.27#ibcon#about to read 4, iclass 16, count 0 2006.201.20:30:55.27#ibcon#read 4, iclass 16, count 0 2006.201.20:30:55.27#ibcon#about to read 5, iclass 16, count 0 2006.201.20:30:55.27#ibcon#read 5, iclass 16, count 0 2006.201.20:30:55.27#ibcon#about to read 6, iclass 16, count 0 2006.201.20:30:55.27#ibcon#read 6, iclass 16, count 0 2006.201.20:30:55.27#ibcon#end of sib2, iclass 16, count 0 2006.201.20:30:55.27#ibcon#*after write, iclass 16, count 0 2006.201.20:30:55.27#ibcon#*before return 0, iclass 16, count 0 2006.201.20:30:55.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:55.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:55.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:30:55.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:30:55.27$vck44/valo=5,734.99 2006.201.20:30:55.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.20:30:55.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.20:30:55.27#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:55.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:55.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:55.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:55.27#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:30:55.27#ibcon#first serial, iclass 18, count 0 2006.201.20:30:55.27#ibcon#enter sib2, iclass 18, count 0 2006.201.20:30:55.27#ibcon#flushed, iclass 18, count 0 2006.201.20:30:55.27#ibcon#about to write, iclass 18, count 0 2006.201.20:30:55.27#ibcon#wrote, iclass 18, count 0 2006.201.20:30:55.27#ibcon#about to read 3, iclass 18, count 0 2006.201.20:30:55.29#ibcon#read 3, iclass 18, count 0 2006.201.20:30:55.29#ibcon#about to read 4, iclass 18, count 0 2006.201.20:30:55.29#ibcon#read 4, iclass 18, count 0 2006.201.20:30:55.29#ibcon#about to read 5, iclass 18, count 0 2006.201.20:30:55.29#ibcon#read 5, iclass 18, count 0 2006.201.20:30:55.29#ibcon#about to read 6, iclass 18, count 0 2006.201.20:30:55.29#ibcon#read 6, iclass 18, count 0 2006.201.20:30:55.29#ibcon#end of sib2, iclass 18, count 0 2006.201.20:30:55.29#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:30:55.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:30:55.29#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:30:55.29#ibcon#*before write, iclass 18, count 0 2006.201.20:30:55.29#ibcon#enter sib2, iclass 18, count 0 2006.201.20:30:55.29#ibcon#flushed, iclass 18, count 0 2006.201.20:30:55.29#ibcon#about to write, iclass 18, count 0 2006.201.20:30:55.29#ibcon#wrote, iclass 18, count 0 2006.201.20:30:55.29#ibcon#about to read 3, iclass 18, count 0 2006.201.20:30:55.33#ibcon#read 3, iclass 18, count 0 2006.201.20:30:55.33#ibcon#about to read 4, iclass 18, count 0 2006.201.20:30:55.33#ibcon#read 4, iclass 18, count 0 2006.201.20:30:55.33#ibcon#about to read 5, iclass 18, count 0 2006.201.20:30:55.33#ibcon#read 5, iclass 18, count 0 2006.201.20:30:55.33#ibcon#about to read 6, iclass 18, count 0 2006.201.20:30:55.33#ibcon#read 6, iclass 18, count 0 2006.201.20:30:55.33#ibcon#end of sib2, iclass 18, count 0 2006.201.20:30:55.33#ibcon#*after write, iclass 18, count 0 2006.201.20:30:55.33#ibcon#*before return 0, iclass 18, count 0 2006.201.20:30:55.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:55.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:55.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:30:55.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:30:55.33$vck44/va=5,4 2006.201.20:30:55.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.20:30:55.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.20:30:55.33#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:55.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:55.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:55.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:55.39#ibcon#enter wrdev, iclass 20, count 2 2006.201.20:30:55.39#ibcon#first serial, iclass 20, count 2 2006.201.20:30:55.39#ibcon#enter sib2, iclass 20, count 2 2006.201.20:30:55.39#ibcon#flushed, iclass 20, count 2 2006.201.20:30:55.39#ibcon#about to write, iclass 20, count 2 2006.201.20:30:55.39#ibcon#wrote, iclass 20, count 2 2006.201.20:30:55.39#ibcon#about to read 3, iclass 20, count 2 2006.201.20:30:55.41#ibcon#read 3, iclass 20, count 2 2006.201.20:30:55.41#ibcon#about to read 4, iclass 20, count 2 2006.201.20:30:55.41#ibcon#read 4, iclass 20, count 2 2006.201.20:30:55.41#ibcon#about to read 5, iclass 20, count 2 2006.201.20:30:55.41#ibcon#read 5, iclass 20, count 2 2006.201.20:30:55.41#ibcon#about to read 6, iclass 20, count 2 2006.201.20:30:55.41#ibcon#read 6, iclass 20, count 2 2006.201.20:30:55.41#ibcon#end of sib2, iclass 20, count 2 2006.201.20:30:55.41#ibcon#*mode == 0, iclass 20, count 2 2006.201.20:30:55.41#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.20:30:55.41#ibcon#[25=AT05-04\r\n] 2006.201.20:30:55.41#ibcon#*before write, iclass 20, count 2 2006.201.20:30:55.41#ibcon#enter sib2, iclass 20, count 2 2006.201.20:30:55.41#ibcon#flushed, iclass 20, count 2 2006.201.20:30:55.41#ibcon#about to write, iclass 20, count 2 2006.201.20:30:55.41#ibcon#wrote, iclass 20, count 2 2006.201.20:30:55.41#ibcon#about to read 3, iclass 20, count 2 2006.201.20:30:55.44#ibcon#read 3, iclass 20, count 2 2006.201.20:30:55.44#ibcon#about to read 4, iclass 20, count 2 2006.201.20:30:55.44#ibcon#read 4, iclass 20, count 2 2006.201.20:30:55.44#ibcon#about to read 5, iclass 20, count 2 2006.201.20:30:55.44#ibcon#read 5, iclass 20, count 2 2006.201.20:30:55.44#ibcon#about to read 6, iclass 20, count 2 2006.201.20:30:55.44#ibcon#read 6, iclass 20, count 2 2006.201.20:30:55.44#ibcon#end of sib2, iclass 20, count 2 2006.201.20:30:55.44#ibcon#*after write, iclass 20, count 2 2006.201.20:30:55.44#ibcon#*before return 0, iclass 20, count 2 2006.201.20:30:55.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:55.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:55.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.20:30:55.44#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:55.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:55.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:55.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:55.56#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:30:55.56#ibcon#first serial, iclass 20, count 0 2006.201.20:30:55.56#ibcon#enter sib2, iclass 20, count 0 2006.201.20:30:55.56#ibcon#flushed, iclass 20, count 0 2006.201.20:30:55.56#ibcon#about to write, iclass 20, count 0 2006.201.20:30:55.56#ibcon#wrote, iclass 20, count 0 2006.201.20:30:55.56#ibcon#about to read 3, iclass 20, count 0 2006.201.20:30:55.58#ibcon#read 3, iclass 20, count 0 2006.201.20:30:55.58#ibcon#about to read 4, iclass 20, count 0 2006.201.20:30:55.58#ibcon#read 4, iclass 20, count 0 2006.201.20:30:55.58#ibcon#about to read 5, iclass 20, count 0 2006.201.20:30:55.58#ibcon#read 5, iclass 20, count 0 2006.201.20:30:55.58#ibcon#about to read 6, iclass 20, count 0 2006.201.20:30:55.58#ibcon#read 6, iclass 20, count 0 2006.201.20:30:55.58#ibcon#end of sib2, iclass 20, count 0 2006.201.20:30:55.58#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:30:55.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:30:55.58#ibcon#[25=USB\r\n] 2006.201.20:30:55.58#ibcon#*before write, iclass 20, count 0 2006.201.20:30:55.58#ibcon#enter sib2, iclass 20, count 0 2006.201.20:30:55.58#ibcon#flushed, iclass 20, count 0 2006.201.20:30:55.58#ibcon#about to write, iclass 20, count 0 2006.201.20:30:55.58#ibcon#wrote, iclass 20, count 0 2006.201.20:30:55.58#ibcon#about to read 3, iclass 20, count 0 2006.201.20:30:55.61#ibcon#read 3, iclass 20, count 0 2006.201.20:30:55.61#ibcon#about to read 4, iclass 20, count 0 2006.201.20:30:55.61#ibcon#read 4, iclass 20, count 0 2006.201.20:30:55.61#ibcon#about to read 5, iclass 20, count 0 2006.201.20:30:55.61#ibcon#read 5, iclass 20, count 0 2006.201.20:30:55.61#ibcon#about to read 6, iclass 20, count 0 2006.201.20:30:55.61#ibcon#read 6, iclass 20, count 0 2006.201.20:30:55.61#ibcon#end of sib2, iclass 20, count 0 2006.201.20:30:55.61#ibcon#*after write, iclass 20, count 0 2006.201.20:30:55.61#ibcon#*before return 0, iclass 20, count 0 2006.201.20:30:55.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:55.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:55.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:30:55.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:30:55.61$vck44/valo=6,814.99 2006.201.20:30:55.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.20:30:55.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.20:30:55.61#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:55.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:55.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:55.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:55.61#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:30:55.61#ibcon#first serial, iclass 22, count 0 2006.201.20:30:55.61#ibcon#enter sib2, iclass 22, count 0 2006.201.20:30:55.61#ibcon#flushed, iclass 22, count 0 2006.201.20:30:55.61#ibcon#about to write, iclass 22, count 0 2006.201.20:30:55.61#ibcon#wrote, iclass 22, count 0 2006.201.20:30:55.61#ibcon#about to read 3, iclass 22, count 0 2006.201.20:30:55.63#ibcon#read 3, iclass 22, count 0 2006.201.20:30:55.63#ibcon#about to read 4, iclass 22, count 0 2006.201.20:30:55.63#ibcon#read 4, iclass 22, count 0 2006.201.20:30:55.63#ibcon#about to read 5, iclass 22, count 0 2006.201.20:30:55.63#ibcon#read 5, iclass 22, count 0 2006.201.20:30:55.63#ibcon#about to read 6, iclass 22, count 0 2006.201.20:30:55.63#ibcon#read 6, iclass 22, count 0 2006.201.20:30:55.63#ibcon#end of sib2, iclass 22, count 0 2006.201.20:30:55.63#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:30:55.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:30:55.63#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:30:55.63#ibcon#*before write, iclass 22, count 0 2006.201.20:30:55.63#ibcon#enter sib2, iclass 22, count 0 2006.201.20:30:55.63#ibcon#flushed, iclass 22, count 0 2006.201.20:30:55.63#ibcon#about to write, iclass 22, count 0 2006.201.20:30:55.63#ibcon#wrote, iclass 22, count 0 2006.201.20:30:55.63#ibcon#about to read 3, iclass 22, count 0 2006.201.20:30:55.68#ibcon#read 3, iclass 22, count 0 2006.201.20:30:55.68#ibcon#about to read 4, iclass 22, count 0 2006.201.20:30:55.68#ibcon#read 4, iclass 22, count 0 2006.201.20:30:55.68#ibcon#about to read 5, iclass 22, count 0 2006.201.20:30:55.68#ibcon#read 5, iclass 22, count 0 2006.201.20:30:55.68#ibcon#about to read 6, iclass 22, count 0 2006.201.20:30:55.68#ibcon#read 6, iclass 22, count 0 2006.201.20:30:55.68#ibcon#end of sib2, iclass 22, count 0 2006.201.20:30:55.68#ibcon#*after write, iclass 22, count 0 2006.201.20:30:55.68#ibcon#*before return 0, iclass 22, count 0 2006.201.20:30:55.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:55.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:55.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:30:55.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:30:55.68$vck44/va=6,5 2006.201.20:30:55.68#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.20:30:55.68#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.20:30:55.68#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:55.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:55.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:55.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:55.73#ibcon#enter wrdev, iclass 24, count 2 2006.201.20:30:55.73#ibcon#first serial, iclass 24, count 2 2006.201.20:30:55.73#ibcon#enter sib2, iclass 24, count 2 2006.201.20:30:55.73#ibcon#flushed, iclass 24, count 2 2006.201.20:30:55.73#ibcon#about to write, iclass 24, count 2 2006.201.20:30:55.73#ibcon#wrote, iclass 24, count 2 2006.201.20:30:55.73#ibcon#about to read 3, iclass 24, count 2 2006.201.20:30:55.75#ibcon#read 3, iclass 24, count 2 2006.201.20:30:55.75#ibcon#about to read 4, iclass 24, count 2 2006.201.20:30:55.75#ibcon#read 4, iclass 24, count 2 2006.201.20:30:55.75#ibcon#about to read 5, iclass 24, count 2 2006.201.20:30:55.75#ibcon#read 5, iclass 24, count 2 2006.201.20:30:55.75#ibcon#about to read 6, iclass 24, count 2 2006.201.20:30:55.75#ibcon#read 6, iclass 24, count 2 2006.201.20:30:55.75#ibcon#end of sib2, iclass 24, count 2 2006.201.20:30:55.75#ibcon#*mode == 0, iclass 24, count 2 2006.201.20:30:55.75#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.20:30:55.75#ibcon#[25=AT06-05\r\n] 2006.201.20:30:55.75#ibcon#*before write, iclass 24, count 2 2006.201.20:30:55.75#ibcon#enter sib2, iclass 24, count 2 2006.201.20:30:55.75#ibcon#flushed, iclass 24, count 2 2006.201.20:30:55.75#ibcon#about to write, iclass 24, count 2 2006.201.20:30:55.75#ibcon#wrote, iclass 24, count 2 2006.201.20:30:55.75#ibcon#about to read 3, iclass 24, count 2 2006.201.20:30:55.78#ibcon#read 3, iclass 24, count 2 2006.201.20:30:55.78#ibcon#about to read 4, iclass 24, count 2 2006.201.20:30:55.78#ibcon#read 4, iclass 24, count 2 2006.201.20:30:55.78#ibcon#about to read 5, iclass 24, count 2 2006.201.20:30:55.78#ibcon#read 5, iclass 24, count 2 2006.201.20:30:55.78#ibcon#about to read 6, iclass 24, count 2 2006.201.20:30:55.78#ibcon#read 6, iclass 24, count 2 2006.201.20:30:55.78#ibcon#end of sib2, iclass 24, count 2 2006.201.20:30:55.78#ibcon#*after write, iclass 24, count 2 2006.201.20:30:55.78#ibcon#*before return 0, iclass 24, count 2 2006.201.20:30:55.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:55.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:55.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.20:30:55.78#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:55.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:55.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:55.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:55.90#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:30:55.90#ibcon#first serial, iclass 24, count 0 2006.201.20:30:55.90#ibcon#enter sib2, iclass 24, count 0 2006.201.20:30:55.90#ibcon#flushed, iclass 24, count 0 2006.201.20:30:55.90#ibcon#about to write, iclass 24, count 0 2006.201.20:30:55.90#ibcon#wrote, iclass 24, count 0 2006.201.20:30:55.90#ibcon#about to read 3, iclass 24, count 0 2006.201.20:30:55.92#ibcon#read 3, iclass 24, count 0 2006.201.20:30:55.92#ibcon#about to read 4, iclass 24, count 0 2006.201.20:30:55.92#ibcon#read 4, iclass 24, count 0 2006.201.20:30:55.92#ibcon#about to read 5, iclass 24, count 0 2006.201.20:30:55.92#ibcon#read 5, iclass 24, count 0 2006.201.20:30:55.92#ibcon#about to read 6, iclass 24, count 0 2006.201.20:30:55.92#ibcon#read 6, iclass 24, count 0 2006.201.20:30:55.92#ibcon#end of sib2, iclass 24, count 0 2006.201.20:30:55.92#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:30:55.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:30:55.92#ibcon#[25=USB\r\n] 2006.201.20:30:55.92#ibcon#*before write, iclass 24, count 0 2006.201.20:30:55.92#ibcon#enter sib2, iclass 24, count 0 2006.201.20:30:55.92#ibcon#flushed, iclass 24, count 0 2006.201.20:30:55.92#ibcon#about to write, iclass 24, count 0 2006.201.20:30:55.92#ibcon#wrote, iclass 24, count 0 2006.201.20:30:55.92#ibcon#about to read 3, iclass 24, count 0 2006.201.20:30:55.95#ibcon#read 3, iclass 24, count 0 2006.201.20:30:55.95#ibcon#about to read 4, iclass 24, count 0 2006.201.20:30:55.95#ibcon#read 4, iclass 24, count 0 2006.201.20:30:55.95#ibcon#about to read 5, iclass 24, count 0 2006.201.20:30:55.95#ibcon#read 5, iclass 24, count 0 2006.201.20:30:55.95#ibcon#about to read 6, iclass 24, count 0 2006.201.20:30:55.95#ibcon#read 6, iclass 24, count 0 2006.201.20:30:55.95#ibcon#end of sib2, iclass 24, count 0 2006.201.20:30:55.95#ibcon#*after write, iclass 24, count 0 2006.201.20:30:55.95#ibcon#*before return 0, iclass 24, count 0 2006.201.20:30:55.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:55.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:55.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:30:55.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:30:55.95$vck44/valo=7,864.99 2006.201.20:30:55.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.20:30:55.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.20:30:55.95#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:55.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:55.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:55.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:55.95#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:30:55.95#ibcon#first serial, iclass 26, count 0 2006.201.20:30:55.95#ibcon#enter sib2, iclass 26, count 0 2006.201.20:30:55.95#ibcon#flushed, iclass 26, count 0 2006.201.20:30:55.95#ibcon#about to write, iclass 26, count 0 2006.201.20:30:55.95#ibcon#wrote, iclass 26, count 0 2006.201.20:30:55.95#ibcon#about to read 3, iclass 26, count 0 2006.201.20:30:55.97#ibcon#read 3, iclass 26, count 0 2006.201.20:30:55.97#ibcon#about to read 4, iclass 26, count 0 2006.201.20:30:55.97#ibcon#read 4, iclass 26, count 0 2006.201.20:30:55.97#ibcon#about to read 5, iclass 26, count 0 2006.201.20:30:55.97#ibcon#read 5, iclass 26, count 0 2006.201.20:30:55.97#ibcon#about to read 6, iclass 26, count 0 2006.201.20:30:55.97#ibcon#read 6, iclass 26, count 0 2006.201.20:30:55.97#ibcon#end of sib2, iclass 26, count 0 2006.201.20:30:55.97#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:30:55.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:30:55.97#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:30:55.97#ibcon#*before write, iclass 26, count 0 2006.201.20:30:55.97#ibcon#enter sib2, iclass 26, count 0 2006.201.20:30:55.97#ibcon#flushed, iclass 26, count 0 2006.201.20:30:55.97#ibcon#about to write, iclass 26, count 0 2006.201.20:30:55.97#ibcon#wrote, iclass 26, count 0 2006.201.20:30:55.97#ibcon#about to read 3, iclass 26, count 0 2006.201.20:30:56.01#ibcon#read 3, iclass 26, count 0 2006.201.20:30:56.01#ibcon#about to read 4, iclass 26, count 0 2006.201.20:30:56.01#ibcon#read 4, iclass 26, count 0 2006.201.20:30:56.01#ibcon#about to read 5, iclass 26, count 0 2006.201.20:30:56.01#ibcon#read 5, iclass 26, count 0 2006.201.20:30:56.01#ibcon#about to read 6, iclass 26, count 0 2006.201.20:30:56.01#ibcon#read 6, iclass 26, count 0 2006.201.20:30:56.01#ibcon#end of sib2, iclass 26, count 0 2006.201.20:30:56.01#ibcon#*after write, iclass 26, count 0 2006.201.20:30:56.01#ibcon#*before return 0, iclass 26, count 0 2006.201.20:30:56.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:56.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:56.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:30:56.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:30:56.01$vck44/va=7,5 2006.201.20:30:56.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.20:30:56.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.20:30:56.01#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:56.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:56.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:56.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:56.07#ibcon#enter wrdev, iclass 28, count 2 2006.201.20:30:56.07#ibcon#first serial, iclass 28, count 2 2006.201.20:30:56.07#ibcon#enter sib2, iclass 28, count 2 2006.201.20:30:56.07#ibcon#flushed, iclass 28, count 2 2006.201.20:30:56.07#ibcon#about to write, iclass 28, count 2 2006.201.20:30:56.07#ibcon#wrote, iclass 28, count 2 2006.201.20:30:56.07#ibcon#about to read 3, iclass 28, count 2 2006.201.20:30:56.09#ibcon#read 3, iclass 28, count 2 2006.201.20:30:56.09#ibcon#about to read 4, iclass 28, count 2 2006.201.20:30:56.09#ibcon#read 4, iclass 28, count 2 2006.201.20:30:56.09#ibcon#about to read 5, iclass 28, count 2 2006.201.20:30:56.09#ibcon#read 5, iclass 28, count 2 2006.201.20:30:56.09#ibcon#about to read 6, iclass 28, count 2 2006.201.20:30:56.09#ibcon#read 6, iclass 28, count 2 2006.201.20:30:56.09#ibcon#end of sib2, iclass 28, count 2 2006.201.20:30:56.09#ibcon#*mode == 0, iclass 28, count 2 2006.201.20:30:56.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.20:30:56.09#ibcon#[25=AT07-05\r\n] 2006.201.20:30:56.09#ibcon#*before write, iclass 28, count 2 2006.201.20:30:56.09#ibcon#enter sib2, iclass 28, count 2 2006.201.20:30:56.09#ibcon#flushed, iclass 28, count 2 2006.201.20:30:56.09#ibcon#about to write, iclass 28, count 2 2006.201.20:30:56.09#ibcon#wrote, iclass 28, count 2 2006.201.20:30:56.09#ibcon#about to read 3, iclass 28, count 2 2006.201.20:30:56.12#ibcon#read 3, iclass 28, count 2 2006.201.20:30:56.12#ibcon#about to read 4, iclass 28, count 2 2006.201.20:30:56.12#ibcon#read 4, iclass 28, count 2 2006.201.20:30:56.12#ibcon#about to read 5, iclass 28, count 2 2006.201.20:30:56.12#ibcon#read 5, iclass 28, count 2 2006.201.20:30:56.12#ibcon#about to read 6, iclass 28, count 2 2006.201.20:30:56.12#ibcon#read 6, iclass 28, count 2 2006.201.20:30:56.12#ibcon#end of sib2, iclass 28, count 2 2006.201.20:30:56.12#ibcon#*after write, iclass 28, count 2 2006.201.20:30:56.12#ibcon#*before return 0, iclass 28, count 2 2006.201.20:30:56.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:56.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:56.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.20:30:56.12#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:56.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:56.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:56.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:56.24#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:30:56.24#ibcon#first serial, iclass 28, count 0 2006.201.20:30:56.24#ibcon#enter sib2, iclass 28, count 0 2006.201.20:30:56.24#ibcon#flushed, iclass 28, count 0 2006.201.20:30:56.24#ibcon#about to write, iclass 28, count 0 2006.201.20:30:56.24#ibcon#wrote, iclass 28, count 0 2006.201.20:30:56.24#ibcon#about to read 3, iclass 28, count 0 2006.201.20:30:56.26#ibcon#read 3, iclass 28, count 0 2006.201.20:30:56.26#ibcon#about to read 4, iclass 28, count 0 2006.201.20:30:56.26#ibcon#read 4, iclass 28, count 0 2006.201.20:30:56.26#ibcon#about to read 5, iclass 28, count 0 2006.201.20:30:56.26#ibcon#read 5, iclass 28, count 0 2006.201.20:30:56.26#ibcon#about to read 6, iclass 28, count 0 2006.201.20:30:56.26#ibcon#read 6, iclass 28, count 0 2006.201.20:30:56.26#ibcon#end of sib2, iclass 28, count 0 2006.201.20:30:56.26#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:30:56.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:30:56.26#ibcon#[25=USB\r\n] 2006.201.20:30:56.26#ibcon#*before write, iclass 28, count 0 2006.201.20:30:56.26#ibcon#enter sib2, iclass 28, count 0 2006.201.20:30:56.26#ibcon#flushed, iclass 28, count 0 2006.201.20:30:56.26#ibcon#about to write, iclass 28, count 0 2006.201.20:30:56.26#ibcon#wrote, iclass 28, count 0 2006.201.20:30:56.26#ibcon#about to read 3, iclass 28, count 0 2006.201.20:30:56.29#ibcon#read 3, iclass 28, count 0 2006.201.20:30:56.29#ibcon#about to read 4, iclass 28, count 0 2006.201.20:30:56.29#ibcon#read 4, iclass 28, count 0 2006.201.20:30:56.29#ibcon#about to read 5, iclass 28, count 0 2006.201.20:30:56.29#ibcon#read 5, iclass 28, count 0 2006.201.20:30:56.29#ibcon#about to read 6, iclass 28, count 0 2006.201.20:30:56.29#ibcon#read 6, iclass 28, count 0 2006.201.20:30:56.29#ibcon#end of sib2, iclass 28, count 0 2006.201.20:30:56.29#ibcon#*after write, iclass 28, count 0 2006.201.20:30:56.29#ibcon#*before return 0, iclass 28, count 0 2006.201.20:30:56.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:56.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:56.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:30:56.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:30:56.29$vck44/valo=8,884.99 2006.201.20:30:56.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.20:30:56.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.20:30:56.29#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:56.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:56.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:56.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:56.29#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:30:56.29#ibcon#first serial, iclass 30, count 0 2006.201.20:30:56.29#ibcon#enter sib2, iclass 30, count 0 2006.201.20:30:56.29#ibcon#flushed, iclass 30, count 0 2006.201.20:30:56.29#ibcon#about to write, iclass 30, count 0 2006.201.20:30:56.29#ibcon#wrote, iclass 30, count 0 2006.201.20:30:56.29#ibcon#about to read 3, iclass 30, count 0 2006.201.20:30:56.31#ibcon#read 3, iclass 30, count 0 2006.201.20:30:56.31#ibcon#about to read 4, iclass 30, count 0 2006.201.20:30:56.31#ibcon#read 4, iclass 30, count 0 2006.201.20:30:56.31#ibcon#about to read 5, iclass 30, count 0 2006.201.20:30:56.31#ibcon#read 5, iclass 30, count 0 2006.201.20:30:56.31#ibcon#about to read 6, iclass 30, count 0 2006.201.20:30:56.31#ibcon#read 6, iclass 30, count 0 2006.201.20:30:56.31#ibcon#end of sib2, iclass 30, count 0 2006.201.20:30:56.31#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:30:56.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:30:56.31#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:30:56.31#ibcon#*before write, iclass 30, count 0 2006.201.20:30:56.31#ibcon#enter sib2, iclass 30, count 0 2006.201.20:30:56.31#ibcon#flushed, iclass 30, count 0 2006.201.20:30:56.31#ibcon#about to write, iclass 30, count 0 2006.201.20:30:56.31#ibcon#wrote, iclass 30, count 0 2006.201.20:30:56.31#ibcon#about to read 3, iclass 30, count 0 2006.201.20:30:56.35#ibcon#read 3, iclass 30, count 0 2006.201.20:30:56.35#ibcon#about to read 4, iclass 30, count 0 2006.201.20:30:56.35#ibcon#read 4, iclass 30, count 0 2006.201.20:30:56.35#ibcon#about to read 5, iclass 30, count 0 2006.201.20:30:56.35#ibcon#read 5, iclass 30, count 0 2006.201.20:30:56.35#ibcon#about to read 6, iclass 30, count 0 2006.201.20:30:56.35#ibcon#read 6, iclass 30, count 0 2006.201.20:30:56.35#ibcon#end of sib2, iclass 30, count 0 2006.201.20:30:56.35#ibcon#*after write, iclass 30, count 0 2006.201.20:30:56.35#ibcon#*before return 0, iclass 30, count 0 2006.201.20:30:56.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:56.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:56.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:30:56.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:30:56.35$vck44/va=8,4 2006.201.20:30:56.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.20:30:56.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.20:30:56.35#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:56.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:30:56.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:30:56.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:30:56.41#ibcon#enter wrdev, iclass 32, count 2 2006.201.20:30:56.41#ibcon#first serial, iclass 32, count 2 2006.201.20:30:56.41#ibcon#enter sib2, iclass 32, count 2 2006.201.20:30:56.41#ibcon#flushed, iclass 32, count 2 2006.201.20:30:56.41#ibcon#about to write, iclass 32, count 2 2006.201.20:30:56.41#ibcon#wrote, iclass 32, count 2 2006.201.20:30:56.41#ibcon#about to read 3, iclass 32, count 2 2006.201.20:30:56.43#ibcon#read 3, iclass 32, count 2 2006.201.20:30:56.43#ibcon#about to read 4, iclass 32, count 2 2006.201.20:30:56.43#ibcon#read 4, iclass 32, count 2 2006.201.20:30:56.43#ibcon#about to read 5, iclass 32, count 2 2006.201.20:30:56.43#ibcon#read 5, iclass 32, count 2 2006.201.20:30:56.43#ibcon#about to read 6, iclass 32, count 2 2006.201.20:30:56.43#ibcon#read 6, iclass 32, count 2 2006.201.20:30:56.43#ibcon#end of sib2, iclass 32, count 2 2006.201.20:30:56.43#ibcon#*mode == 0, iclass 32, count 2 2006.201.20:30:56.43#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.20:30:56.43#ibcon#[25=AT08-04\r\n] 2006.201.20:30:56.43#ibcon#*before write, iclass 32, count 2 2006.201.20:30:56.43#ibcon#enter sib2, iclass 32, count 2 2006.201.20:30:56.43#ibcon#flushed, iclass 32, count 2 2006.201.20:30:56.43#ibcon#about to write, iclass 32, count 2 2006.201.20:30:56.43#ibcon#wrote, iclass 32, count 2 2006.201.20:30:56.43#ibcon#about to read 3, iclass 32, count 2 2006.201.20:30:56.46#ibcon#read 3, iclass 32, count 2 2006.201.20:30:56.46#ibcon#about to read 4, iclass 32, count 2 2006.201.20:30:56.46#ibcon#read 4, iclass 32, count 2 2006.201.20:30:56.46#ibcon#about to read 5, iclass 32, count 2 2006.201.20:30:56.46#ibcon#read 5, iclass 32, count 2 2006.201.20:30:56.46#ibcon#about to read 6, iclass 32, count 2 2006.201.20:30:56.46#ibcon#read 6, iclass 32, count 2 2006.201.20:30:56.46#ibcon#end of sib2, iclass 32, count 2 2006.201.20:30:56.46#ibcon#*after write, iclass 32, count 2 2006.201.20:30:56.46#ibcon#*before return 0, iclass 32, count 2 2006.201.20:30:56.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:30:56.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:30:56.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.20:30:56.46#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:56.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:30:56.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:30:56.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:30:56.58#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:30:56.58#ibcon#first serial, iclass 32, count 0 2006.201.20:30:56.58#ibcon#enter sib2, iclass 32, count 0 2006.201.20:30:56.58#ibcon#flushed, iclass 32, count 0 2006.201.20:30:56.58#ibcon#about to write, iclass 32, count 0 2006.201.20:30:56.58#ibcon#wrote, iclass 32, count 0 2006.201.20:30:56.58#ibcon#about to read 3, iclass 32, count 0 2006.201.20:30:56.60#ibcon#read 3, iclass 32, count 0 2006.201.20:30:56.60#ibcon#about to read 4, iclass 32, count 0 2006.201.20:30:56.60#ibcon#read 4, iclass 32, count 0 2006.201.20:30:56.60#ibcon#about to read 5, iclass 32, count 0 2006.201.20:30:56.60#ibcon#read 5, iclass 32, count 0 2006.201.20:30:56.60#ibcon#about to read 6, iclass 32, count 0 2006.201.20:30:56.60#ibcon#read 6, iclass 32, count 0 2006.201.20:30:56.60#ibcon#end of sib2, iclass 32, count 0 2006.201.20:30:56.60#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:30:56.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:30:56.60#ibcon#[25=USB\r\n] 2006.201.20:30:56.60#ibcon#*before write, iclass 32, count 0 2006.201.20:30:56.60#ibcon#enter sib2, iclass 32, count 0 2006.201.20:30:56.60#ibcon#flushed, iclass 32, count 0 2006.201.20:30:56.60#ibcon#about to write, iclass 32, count 0 2006.201.20:30:56.60#ibcon#wrote, iclass 32, count 0 2006.201.20:30:56.60#ibcon#about to read 3, iclass 32, count 0 2006.201.20:30:56.63#ibcon#read 3, iclass 32, count 0 2006.201.20:30:56.63#ibcon#about to read 4, iclass 32, count 0 2006.201.20:30:56.63#ibcon#read 4, iclass 32, count 0 2006.201.20:30:56.63#ibcon#about to read 5, iclass 32, count 0 2006.201.20:30:56.63#ibcon#read 5, iclass 32, count 0 2006.201.20:30:56.63#ibcon#about to read 6, iclass 32, count 0 2006.201.20:30:56.63#ibcon#read 6, iclass 32, count 0 2006.201.20:30:56.63#ibcon#end of sib2, iclass 32, count 0 2006.201.20:30:56.63#ibcon#*after write, iclass 32, count 0 2006.201.20:30:56.63#ibcon#*before return 0, iclass 32, count 0 2006.201.20:30:56.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:30:56.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:30:56.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:30:56.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:30:56.63$vck44/vblo=1,629.99 2006.201.20:30:56.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.20:30:56.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.20:30:56.63#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:56.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:30:56.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:30:56.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:30:56.63#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:30:56.63#ibcon#first serial, iclass 34, count 0 2006.201.20:30:56.63#ibcon#enter sib2, iclass 34, count 0 2006.201.20:30:56.63#ibcon#flushed, iclass 34, count 0 2006.201.20:30:56.63#ibcon#about to write, iclass 34, count 0 2006.201.20:30:56.63#ibcon#wrote, iclass 34, count 0 2006.201.20:30:56.63#ibcon#about to read 3, iclass 34, count 0 2006.201.20:30:56.65#ibcon#read 3, iclass 34, count 0 2006.201.20:30:56.65#ibcon#about to read 4, iclass 34, count 0 2006.201.20:30:56.65#ibcon#read 4, iclass 34, count 0 2006.201.20:30:56.65#ibcon#about to read 5, iclass 34, count 0 2006.201.20:30:56.65#ibcon#read 5, iclass 34, count 0 2006.201.20:30:56.65#ibcon#about to read 6, iclass 34, count 0 2006.201.20:30:56.65#ibcon#read 6, iclass 34, count 0 2006.201.20:30:56.65#ibcon#end of sib2, iclass 34, count 0 2006.201.20:30:56.65#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:30:56.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:30:56.65#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:30:56.65#ibcon#*before write, iclass 34, count 0 2006.201.20:30:56.65#ibcon#enter sib2, iclass 34, count 0 2006.201.20:30:56.65#ibcon#flushed, iclass 34, count 0 2006.201.20:30:56.65#ibcon#about to write, iclass 34, count 0 2006.201.20:30:56.65#ibcon#wrote, iclass 34, count 0 2006.201.20:30:56.65#ibcon#about to read 3, iclass 34, count 0 2006.201.20:30:56.70#ibcon#read 3, iclass 34, count 0 2006.201.20:30:56.70#ibcon#about to read 4, iclass 34, count 0 2006.201.20:30:56.70#ibcon#read 4, iclass 34, count 0 2006.201.20:30:56.70#ibcon#about to read 5, iclass 34, count 0 2006.201.20:30:56.70#ibcon#read 5, iclass 34, count 0 2006.201.20:30:56.70#ibcon#about to read 6, iclass 34, count 0 2006.201.20:30:56.70#ibcon#read 6, iclass 34, count 0 2006.201.20:30:56.70#ibcon#end of sib2, iclass 34, count 0 2006.201.20:30:56.70#ibcon#*after write, iclass 34, count 0 2006.201.20:30:56.70#ibcon#*before return 0, iclass 34, count 0 2006.201.20:30:56.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:30:56.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:30:56.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:30:56.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:30:56.70$vck44/vb=1,4 2006.201.20:30:56.70#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.20:30:56.70#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.20:30:56.70#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:56.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:30:56.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:30:56.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:30:56.70#ibcon#enter wrdev, iclass 36, count 2 2006.201.20:30:56.70#ibcon#first serial, iclass 36, count 2 2006.201.20:30:56.70#ibcon#enter sib2, iclass 36, count 2 2006.201.20:30:56.70#ibcon#flushed, iclass 36, count 2 2006.201.20:30:56.70#ibcon#about to write, iclass 36, count 2 2006.201.20:30:56.70#ibcon#wrote, iclass 36, count 2 2006.201.20:30:56.70#ibcon#about to read 3, iclass 36, count 2 2006.201.20:30:56.72#ibcon#read 3, iclass 36, count 2 2006.201.20:30:56.72#ibcon#about to read 4, iclass 36, count 2 2006.201.20:30:56.72#ibcon#read 4, iclass 36, count 2 2006.201.20:30:56.72#ibcon#about to read 5, iclass 36, count 2 2006.201.20:30:56.72#ibcon#read 5, iclass 36, count 2 2006.201.20:30:56.72#ibcon#about to read 6, iclass 36, count 2 2006.201.20:30:56.72#ibcon#read 6, iclass 36, count 2 2006.201.20:30:56.72#ibcon#end of sib2, iclass 36, count 2 2006.201.20:30:56.72#ibcon#*mode == 0, iclass 36, count 2 2006.201.20:30:56.72#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.20:30:56.72#ibcon#[27=AT01-04\r\n] 2006.201.20:30:56.72#ibcon#*before write, iclass 36, count 2 2006.201.20:30:56.72#ibcon#enter sib2, iclass 36, count 2 2006.201.20:30:56.72#ibcon#flushed, iclass 36, count 2 2006.201.20:30:56.72#ibcon#about to write, iclass 36, count 2 2006.201.20:30:56.72#ibcon#wrote, iclass 36, count 2 2006.201.20:30:56.72#ibcon#about to read 3, iclass 36, count 2 2006.201.20:30:56.75#ibcon#read 3, iclass 36, count 2 2006.201.20:30:56.75#ibcon#about to read 4, iclass 36, count 2 2006.201.20:30:56.75#ibcon#read 4, iclass 36, count 2 2006.201.20:30:56.75#ibcon#about to read 5, iclass 36, count 2 2006.201.20:30:56.75#ibcon#read 5, iclass 36, count 2 2006.201.20:30:56.75#ibcon#about to read 6, iclass 36, count 2 2006.201.20:30:56.75#ibcon#read 6, iclass 36, count 2 2006.201.20:30:56.75#ibcon#end of sib2, iclass 36, count 2 2006.201.20:30:56.75#ibcon#*after write, iclass 36, count 2 2006.201.20:30:56.75#ibcon#*before return 0, iclass 36, count 2 2006.201.20:30:56.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:30:56.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:30:56.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.20:30:56.75#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:56.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:30:56.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:30:56.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:30:56.87#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:30:56.87#ibcon#first serial, iclass 36, count 0 2006.201.20:30:56.87#ibcon#enter sib2, iclass 36, count 0 2006.201.20:30:56.87#ibcon#flushed, iclass 36, count 0 2006.201.20:30:56.87#ibcon#about to write, iclass 36, count 0 2006.201.20:30:56.87#ibcon#wrote, iclass 36, count 0 2006.201.20:30:56.87#ibcon#about to read 3, iclass 36, count 0 2006.201.20:30:56.89#ibcon#read 3, iclass 36, count 0 2006.201.20:30:56.89#ibcon#about to read 4, iclass 36, count 0 2006.201.20:30:56.89#ibcon#read 4, iclass 36, count 0 2006.201.20:30:56.89#ibcon#about to read 5, iclass 36, count 0 2006.201.20:30:56.89#ibcon#read 5, iclass 36, count 0 2006.201.20:30:56.89#ibcon#about to read 6, iclass 36, count 0 2006.201.20:30:56.89#ibcon#read 6, iclass 36, count 0 2006.201.20:30:56.89#ibcon#end of sib2, iclass 36, count 0 2006.201.20:30:56.89#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:30:56.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:30:56.89#ibcon#[27=USB\r\n] 2006.201.20:30:56.89#ibcon#*before write, iclass 36, count 0 2006.201.20:30:56.89#ibcon#enter sib2, iclass 36, count 0 2006.201.20:30:56.89#ibcon#flushed, iclass 36, count 0 2006.201.20:30:56.89#ibcon#about to write, iclass 36, count 0 2006.201.20:30:56.89#ibcon#wrote, iclass 36, count 0 2006.201.20:30:56.89#ibcon#about to read 3, iclass 36, count 0 2006.201.20:30:56.92#ibcon#read 3, iclass 36, count 0 2006.201.20:30:56.92#ibcon#about to read 4, iclass 36, count 0 2006.201.20:30:56.92#ibcon#read 4, iclass 36, count 0 2006.201.20:30:56.92#ibcon#about to read 5, iclass 36, count 0 2006.201.20:30:56.92#ibcon#read 5, iclass 36, count 0 2006.201.20:30:56.92#ibcon#about to read 6, iclass 36, count 0 2006.201.20:30:56.92#ibcon#read 6, iclass 36, count 0 2006.201.20:30:56.92#ibcon#end of sib2, iclass 36, count 0 2006.201.20:30:56.92#ibcon#*after write, iclass 36, count 0 2006.201.20:30:56.92#ibcon#*before return 0, iclass 36, count 0 2006.201.20:30:56.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:30:56.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:30:56.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:30:56.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:30:56.92$vck44/vblo=2,634.99 2006.201.20:30:56.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.20:30:56.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.20:30:56.92#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:56.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:56.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:56.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:56.92#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:30:56.92#ibcon#first serial, iclass 38, count 0 2006.201.20:30:56.92#ibcon#enter sib2, iclass 38, count 0 2006.201.20:30:56.92#ibcon#flushed, iclass 38, count 0 2006.201.20:30:56.92#ibcon#about to write, iclass 38, count 0 2006.201.20:30:56.92#ibcon#wrote, iclass 38, count 0 2006.201.20:30:56.92#ibcon#about to read 3, iclass 38, count 0 2006.201.20:30:56.94#ibcon#read 3, iclass 38, count 0 2006.201.20:30:56.94#ibcon#about to read 4, iclass 38, count 0 2006.201.20:30:56.94#ibcon#read 4, iclass 38, count 0 2006.201.20:30:56.94#ibcon#about to read 5, iclass 38, count 0 2006.201.20:30:56.94#ibcon#read 5, iclass 38, count 0 2006.201.20:30:56.94#ibcon#about to read 6, iclass 38, count 0 2006.201.20:30:56.94#ibcon#read 6, iclass 38, count 0 2006.201.20:30:56.94#ibcon#end of sib2, iclass 38, count 0 2006.201.20:30:56.94#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:30:56.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:30:56.94#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:30:56.94#ibcon#*before write, iclass 38, count 0 2006.201.20:30:56.94#ibcon#enter sib2, iclass 38, count 0 2006.201.20:30:56.94#ibcon#flushed, iclass 38, count 0 2006.201.20:30:56.94#ibcon#about to write, iclass 38, count 0 2006.201.20:30:56.94#ibcon#wrote, iclass 38, count 0 2006.201.20:30:56.94#ibcon#about to read 3, iclass 38, count 0 2006.201.20:30:56.98#ibcon#read 3, iclass 38, count 0 2006.201.20:30:56.98#ibcon#about to read 4, iclass 38, count 0 2006.201.20:30:56.98#ibcon#read 4, iclass 38, count 0 2006.201.20:30:56.98#ibcon#about to read 5, iclass 38, count 0 2006.201.20:30:56.98#ibcon#read 5, iclass 38, count 0 2006.201.20:30:56.98#ibcon#about to read 6, iclass 38, count 0 2006.201.20:30:56.98#ibcon#read 6, iclass 38, count 0 2006.201.20:30:56.98#ibcon#end of sib2, iclass 38, count 0 2006.201.20:30:56.98#ibcon#*after write, iclass 38, count 0 2006.201.20:30:56.98#ibcon#*before return 0, iclass 38, count 0 2006.201.20:30:56.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:56.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:30:56.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:30:56.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:30:56.98$vck44/vb=2,5 2006.201.20:30:56.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.20:30:56.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.20:30:56.98#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:56.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:57.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:57.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:57.04#ibcon#enter wrdev, iclass 40, count 2 2006.201.20:30:57.04#ibcon#first serial, iclass 40, count 2 2006.201.20:30:57.04#ibcon#enter sib2, iclass 40, count 2 2006.201.20:30:57.04#ibcon#flushed, iclass 40, count 2 2006.201.20:30:57.04#ibcon#about to write, iclass 40, count 2 2006.201.20:30:57.04#ibcon#wrote, iclass 40, count 2 2006.201.20:30:57.04#ibcon#about to read 3, iclass 40, count 2 2006.201.20:30:57.06#ibcon#read 3, iclass 40, count 2 2006.201.20:30:57.06#ibcon#about to read 4, iclass 40, count 2 2006.201.20:30:57.06#ibcon#read 4, iclass 40, count 2 2006.201.20:30:57.06#ibcon#about to read 5, iclass 40, count 2 2006.201.20:30:57.06#ibcon#read 5, iclass 40, count 2 2006.201.20:30:57.06#ibcon#about to read 6, iclass 40, count 2 2006.201.20:30:57.06#ibcon#read 6, iclass 40, count 2 2006.201.20:30:57.06#ibcon#end of sib2, iclass 40, count 2 2006.201.20:30:57.06#ibcon#*mode == 0, iclass 40, count 2 2006.201.20:30:57.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.20:30:57.06#ibcon#[27=AT02-05\r\n] 2006.201.20:30:57.06#ibcon#*before write, iclass 40, count 2 2006.201.20:30:57.06#ibcon#enter sib2, iclass 40, count 2 2006.201.20:30:57.06#ibcon#flushed, iclass 40, count 2 2006.201.20:30:57.06#ibcon#about to write, iclass 40, count 2 2006.201.20:30:57.06#ibcon#wrote, iclass 40, count 2 2006.201.20:30:57.06#ibcon#about to read 3, iclass 40, count 2 2006.201.20:30:57.09#ibcon#read 3, iclass 40, count 2 2006.201.20:30:57.09#ibcon#about to read 4, iclass 40, count 2 2006.201.20:30:57.09#ibcon#read 4, iclass 40, count 2 2006.201.20:30:57.09#ibcon#about to read 5, iclass 40, count 2 2006.201.20:30:57.09#ibcon#read 5, iclass 40, count 2 2006.201.20:30:57.09#ibcon#about to read 6, iclass 40, count 2 2006.201.20:30:57.09#ibcon#read 6, iclass 40, count 2 2006.201.20:30:57.09#ibcon#end of sib2, iclass 40, count 2 2006.201.20:30:57.09#ibcon#*after write, iclass 40, count 2 2006.201.20:30:57.09#ibcon#*before return 0, iclass 40, count 2 2006.201.20:30:57.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:57.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:30:57.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.20:30:57.09#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:57.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:57.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:57.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:57.21#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:30:57.21#ibcon#first serial, iclass 40, count 0 2006.201.20:30:57.21#ibcon#enter sib2, iclass 40, count 0 2006.201.20:30:57.21#ibcon#flushed, iclass 40, count 0 2006.201.20:30:57.21#ibcon#about to write, iclass 40, count 0 2006.201.20:30:57.21#ibcon#wrote, iclass 40, count 0 2006.201.20:30:57.21#ibcon#about to read 3, iclass 40, count 0 2006.201.20:30:57.23#ibcon#read 3, iclass 40, count 0 2006.201.20:30:57.23#ibcon#about to read 4, iclass 40, count 0 2006.201.20:30:57.23#ibcon#read 4, iclass 40, count 0 2006.201.20:30:57.23#ibcon#about to read 5, iclass 40, count 0 2006.201.20:30:57.23#ibcon#read 5, iclass 40, count 0 2006.201.20:30:57.23#ibcon#about to read 6, iclass 40, count 0 2006.201.20:30:57.23#ibcon#read 6, iclass 40, count 0 2006.201.20:30:57.23#ibcon#end of sib2, iclass 40, count 0 2006.201.20:30:57.23#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:30:57.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:30:57.23#ibcon#[27=USB\r\n] 2006.201.20:30:57.23#ibcon#*before write, iclass 40, count 0 2006.201.20:30:57.23#ibcon#enter sib2, iclass 40, count 0 2006.201.20:30:57.23#ibcon#flushed, iclass 40, count 0 2006.201.20:30:57.23#ibcon#about to write, iclass 40, count 0 2006.201.20:30:57.23#ibcon#wrote, iclass 40, count 0 2006.201.20:30:57.23#ibcon#about to read 3, iclass 40, count 0 2006.201.20:30:57.26#ibcon#read 3, iclass 40, count 0 2006.201.20:30:57.26#ibcon#about to read 4, iclass 40, count 0 2006.201.20:30:57.26#ibcon#read 4, iclass 40, count 0 2006.201.20:30:57.26#ibcon#about to read 5, iclass 40, count 0 2006.201.20:30:57.26#ibcon#read 5, iclass 40, count 0 2006.201.20:30:57.26#ibcon#about to read 6, iclass 40, count 0 2006.201.20:30:57.26#ibcon#read 6, iclass 40, count 0 2006.201.20:30:57.26#ibcon#end of sib2, iclass 40, count 0 2006.201.20:30:57.26#ibcon#*after write, iclass 40, count 0 2006.201.20:30:57.26#ibcon#*before return 0, iclass 40, count 0 2006.201.20:30:57.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:57.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:30:57.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:30:57.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:30:57.26$vck44/vblo=3,649.99 2006.201.20:30:57.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.20:30:57.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.20:30:57.26#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:57.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:57.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:57.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:57.26#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:30:57.26#ibcon#first serial, iclass 4, count 0 2006.201.20:30:57.26#ibcon#enter sib2, iclass 4, count 0 2006.201.20:30:57.26#ibcon#flushed, iclass 4, count 0 2006.201.20:30:57.26#ibcon#about to write, iclass 4, count 0 2006.201.20:30:57.26#ibcon#wrote, iclass 4, count 0 2006.201.20:30:57.26#ibcon#about to read 3, iclass 4, count 0 2006.201.20:30:57.28#ibcon#read 3, iclass 4, count 0 2006.201.20:30:57.28#ibcon#about to read 4, iclass 4, count 0 2006.201.20:30:57.28#ibcon#read 4, iclass 4, count 0 2006.201.20:30:57.28#ibcon#about to read 5, iclass 4, count 0 2006.201.20:30:57.28#ibcon#read 5, iclass 4, count 0 2006.201.20:30:57.28#ibcon#about to read 6, iclass 4, count 0 2006.201.20:30:57.28#ibcon#read 6, iclass 4, count 0 2006.201.20:30:57.28#ibcon#end of sib2, iclass 4, count 0 2006.201.20:30:57.28#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:30:57.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:30:57.28#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:30:57.28#ibcon#*before write, iclass 4, count 0 2006.201.20:30:57.28#ibcon#enter sib2, iclass 4, count 0 2006.201.20:30:57.28#ibcon#flushed, iclass 4, count 0 2006.201.20:30:57.28#ibcon#about to write, iclass 4, count 0 2006.201.20:30:57.28#ibcon#wrote, iclass 4, count 0 2006.201.20:30:57.28#ibcon#about to read 3, iclass 4, count 0 2006.201.20:30:57.32#ibcon#read 3, iclass 4, count 0 2006.201.20:30:57.32#ibcon#about to read 4, iclass 4, count 0 2006.201.20:30:57.32#ibcon#read 4, iclass 4, count 0 2006.201.20:30:57.32#ibcon#about to read 5, iclass 4, count 0 2006.201.20:30:57.32#ibcon#read 5, iclass 4, count 0 2006.201.20:30:57.32#ibcon#about to read 6, iclass 4, count 0 2006.201.20:30:57.32#ibcon#read 6, iclass 4, count 0 2006.201.20:30:57.32#ibcon#end of sib2, iclass 4, count 0 2006.201.20:30:57.32#ibcon#*after write, iclass 4, count 0 2006.201.20:30:57.32#ibcon#*before return 0, iclass 4, count 0 2006.201.20:30:57.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:57.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:30:57.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:30:57.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:30:57.32$vck44/vb=3,4 2006.201.20:30:57.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.20:30:57.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.20:30:57.32#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:57.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:57.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:57.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:57.38#ibcon#enter wrdev, iclass 6, count 2 2006.201.20:30:57.38#ibcon#first serial, iclass 6, count 2 2006.201.20:30:57.38#ibcon#enter sib2, iclass 6, count 2 2006.201.20:30:57.38#ibcon#flushed, iclass 6, count 2 2006.201.20:30:57.38#ibcon#about to write, iclass 6, count 2 2006.201.20:30:57.38#ibcon#wrote, iclass 6, count 2 2006.201.20:30:57.38#ibcon#about to read 3, iclass 6, count 2 2006.201.20:30:57.40#ibcon#read 3, iclass 6, count 2 2006.201.20:30:57.40#ibcon#about to read 4, iclass 6, count 2 2006.201.20:30:57.40#ibcon#read 4, iclass 6, count 2 2006.201.20:30:57.40#ibcon#about to read 5, iclass 6, count 2 2006.201.20:30:57.40#ibcon#read 5, iclass 6, count 2 2006.201.20:30:57.40#ibcon#about to read 6, iclass 6, count 2 2006.201.20:30:57.40#ibcon#read 6, iclass 6, count 2 2006.201.20:30:57.40#ibcon#end of sib2, iclass 6, count 2 2006.201.20:30:57.40#ibcon#*mode == 0, iclass 6, count 2 2006.201.20:30:57.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.20:30:57.40#ibcon#[27=AT03-04\r\n] 2006.201.20:30:57.40#ibcon#*before write, iclass 6, count 2 2006.201.20:30:57.40#ibcon#enter sib2, iclass 6, count 2 2006.201.20:30:57.40#ibcon#flushed, iclass 6, count 2 2006.201.20:30:57.40#ibcon#about to write, iclass 6, count 2 2006.201.20:30:57.40#ibcon#wrote, iclass 6, count 2 2006.201.20:30:57.40#ibcon#about to read 3, iclass 6, count 2 2006.201.20:30:57.44#ibcon#read 3, iclass 6, count 2 2006.201.20:30:57.44#ibcon#about to read 4, iclass 6, count 2 2006.201.20:30:57.44#ibcon#read 4, iclass 6, count 2 2006.201.20:30:57.44#ibcon#about to read 5, iclass 6, count 2 2006.201.20:30:57.44#ibcon#read 5, iclass 6, count 2 2006.201.20:30:57.44#ibcon#about to read 6, iclass 6, count 2 2006.201.20:30:57.44#ibcon#read 6, iclass 6, count 2 2006.201.20:30:57.44#ibcon#end of sib2, iclass 6, count 2 2006.201.20:30:57.44#ibcon#*after write, iclass 6, count 2 2006.201.20:30:57.44#ibcon#*before return 0, iclass 6, count 2 2006.201.20:30:57.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:57.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:30:57.44#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.20:30:57.44#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:57.44#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:57.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:57.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:57.56#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:30:57.56#ibcon#first serial, iclass 6, count 0 2006.201.20:30:57.56#ibcon#enter sib2, iclass 6, count 0 2006.201.20:30:57.56#ibcon#flushed, iclass 6, count 0 2006.201.20:30:57.56#ibcon#about to write, iclass 6, count 0 2006.201.20:30:57.56#ibcon#wrote, iclass 6, count 0 2006.201.20:30:57.56#ibcon#about to read 3, iclass 6, count 0 2006.201.20:30:57.58#ibcon#read 3, iclass 6, count 0 2006.201.20:30:57.58#ibcon#about to read 4, iclass 6, count 0 2006.201.20:30:57.58#ibcon#read 4, iclass 6, count 0 2006.201.20:30:57.58#ibcon#about to read 5, iclass 6, count 0 2006.201.20:30:57.58#ibcon#read 5, iclass 6, count 0 2006.201.20:30:57.58#ibcon#about to read 6, iclass 6, count 0 2006.201.20:30:57.58#ibcon#read 6, iclass 6, count 0 2006.201.20:30:57.58#ibcon#end of sib2, iclass 6, count 0 2006.201.20:30:57.58#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:30:57.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:30:57.58#ibcon#[27=USB\r\n] 2006.201.20:30:57.58#ibcon#*before write, iclass 6, count 0 2006.201.20:30:57.58#ibcon#enter sib2, iclass 6, count 0 2006.201.20:30:57.58#ibcon#flushed, iclass 6, count 0 2006.201.20:30:57.58#ibcon#about to write, iclass 6, count 0 2006.201.20:30:57.58#ibcon#wrote, iclass 6, count 0 2006.201.20:30:57.58#ibcon#about to read 3, iclass 6, count 0 2006.201.20:30:57.61#ibcon#read 3, iclass 6, count 0 2006.201.20:30:57.61#ibcon#about to read 4, iclass 6, count 0 2006.201.20:30:57.61#ibcon#read 4, iclass 6, count 0 2006.201.20:30:57.61#ibcon#about to read 5, iclass 6, count 0 2006.201.20:30:57.61#ibcon#read 5, iclass 6, count 0 2006.201.20:30:57.61#ibcon#about to read 6, iclass 6, count 0 2006.201.20:30:57.61#ibcon#read 6, iclass 6, count 0 2006.201.20:30:57.61#ibcon#end of sib2, iclass 6, count 0 2006.201.20:30:57.61#ibcon#*after write, iclass 6, count 0 2006.201.20:30:57.61#ibcon#*before return 0, iclass 6, count 0 2006.201.20:30:57.61#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:57.61#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:30:57.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:30:57.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:30:57.61$vck44/vblo=4,679.99 2006.201.20:30:57.61#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.20:30:57.61#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.20:30:57.61#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:57.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:57.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:57.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:57.61#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:30:57.61#ibcon#first serial, iclass 10, count 0 2006.201.20:30:57.61#ibcon#enter sib2, iclass 10, count 0 2006.201.20:30:57.61#ibcon#flushed, iclass 10, count 0 2006.201.20:30:57.61#ibcon#about to write, iclass 10, count 0 2006.201.20:30:57.61#ibcon#wrote, iclass 10, count 0 2006.201.20:30:57.61#ibcon#about to read 3, iclass 10, count 0 2006.201.20:30:57.63#ibcon#read 3, iclass 10, count 0 2006.201.20:30:57.63#ibcon#about to read 4, iclass 10, count 0 2006.201.20:30:57.63#ibcon#read 4, iclass 10, count 0 2006.201.20:30:57.63#ibcon#about to read 5, iclass 10, count 0 2006.201.20:30:57.63#ibcon#read 5, iclass 10, count 0 2006.201.20:30:57.63#ibcon#about to read 6, iclass 10, count 0 2006.201.20:30:57.63#ibcon#read 6, iclass 10, count 0 2006.201.20:30:57.63#ibcon#end of sib2, iclass 10, count 0 2006.201.20:30:57.63#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:30:57.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:30:57.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:30:57.63#ibcon#*before write, iclass 10, count 0 2006.201.20:30:57.63#ibcon#enter sib2, iclass 10, count 0 2006.201.20:30:57.63#ibcon#flushed, iclass 10, count 0 2006.201.20:30:57.63#ibcon#about to write, iclass 10, count 0 2006.201.20:30:57.63#ibcon#wrote, iclass 10, count 0 2006.201.20:30:57.63#ibcon#about to read 3, iclass 10, count 0 2006.201.20:30:57.67#ibcon#read 3, iclass 10, count 0 2006.201.20:30:57.67#ibcon#about to read 4, iclass 10, count 0 2006.201.20:30:57.67#ibcon#read 4, iclass 10, count 0 2006.201.20:30:57.67#ibcon#about to read 5, iclass 10, count 0 2006.201.20:30:57.67#ibcon#read 5, iclass 10, count 0 2006.201.20:30:57.67#ibcon#about to read 6, iclass 10, count 0 2006.201.20:30:57.67#ibcon#read 6, iclass 10, count 0 2006.201.20:30:57.67#ibcon#end of sib2, iclass 10, count 0 2006.201.20:30:57.67#ibcon#*after write, iclass 10, count 0 2006.201.20:30:57.67#ibcon#*before return 0, iclass 10, count 0 2006.201.20:30:57.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:57.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:30:57.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:30:57.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:30:57.67$vck44/vb=4,5 2006.201.20:30:57.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.20:30:57.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.20:30:57.67#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:57.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:57.73#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:57.73#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:57.73#ibcon#enter wrdev, iclass 12, count 2 2006.201.20:30:57.73#ibcon#first serial, iclass 12, count 2 2006.201.20:30:57.73#ibcon#enter sib2, iclass 12, count 2 2006.201.20:30:57.73#ibcon#flushed, iclass 12, count 2 2006.201.20:30:57.73#ibcon#about to write, iclass 12, count 2 2006.201.20:30:57.73#ibcon#wrote, iclass 12, count 2 2006.201.20:30:57.73#ibcon#about to read 3, iclass 12, count 2 2006.201.20:30:57.75#ibcon#read 3, iclass 12, count 2 2006.201.20:30:57.75#ibcon#about to read 4, iclass 12, count 2 2006.201.20:30:57.75#ibcon#read 4, iclass 12, count 2 2006.201.20:30:57.75#ibcon#about to read 5, iclass 12, count 2 2006.201.20:30:57.75#ibcon#read 5, iclass 12, count 2 2006.201.20:30:57.75#ibcon#about to read 6, iclass 12, count 2 2006.201.20:30:57.75#ibcon#read 6, iclass 12, count 2 2006.201.20:30:57.75#ibcon#end of sib2, iclass 12, count 2 2006.201.20:30:57.75#ibcon#*mode == 0, iclass 12, count 2 2006.201.20:30:57.75#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.20:30:57.75#ibcon#[27=AT04-05\r\n] 2006.201.20:30:57.75#ibcon#*before write, iclass 12, count 2 2006.201.20:30:57.75#ibcon#enter sib2, iclass 12, count 2 2006.201.20:30:57.75#ibcon#flushed, iclass 12, count 2 2006.201.20:30:57.75#ibcon#about to write, iclass 12, count 2 2006.201.20:30:57.75#ibcon#wrote, iclass 12, count 2 2006.201.20:30:57.75#ibcon#about to read 3, iclass 12, count 2 2006.201.20:30:57.78#ibcon#read 3, iclass 12, count 2 2006.201.20:30:57.78#ibcon#about to read 4, iclass 12, count 2 2006.201.20:30:57.78#ibcon#read 4, iclass 12, count 2 2006.201.20:30:57.78#ibcon#about to read 5, iclass 12, count 2 2006.201.20:30:57.78#ibcon#read 5, iclass 12, count 2 2006.201.20:30:57.78#ibcon#about to read 6, iclass 12, count 2 2006.201.20:30:57.78#ibcon#read 6, iclass 12, count 2 2006.201.20:30:57.78#ibcon#end of sib2, iclass 12, count 2 2006.201.20:30:57.78#ibcon#*after write, iclass 12, count 2 2006.201.20:30:57.78#ibcon#*before return 0, iclass 12, count 2 2006.201.20:30:57.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:57.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:30:57.78#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.20:30:57.78#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:57.78#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:57.90#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:57.90#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:57.90#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:30:57.90#ibcon#first serial, iclass 12, count 0 2006.201.20:30:57.90#ibcon#enter sib2, iclass 12, count 0 2006.201.20:30:57.90#ibcon#flushed, iclass 12, count 0 2006.201.20:30:57.90#ibcon#about to write, iclass 12, count 0 2006.201.20:30:57.90#ibcon#wrote, iclass 12, count 0 2006.201.20:30:57.90#ibcon#about to read 3, iclass 12, count 0 2006.201.20:30:57.92#ibcon#read 3, iclass 12, count 0 2006.201.20:30:57.92#ibcon#about to read 4, iclass 12, count 0 2006.201.20:30:57.92#ibcon#read 4, iclass 12, count 0 2006.201.20:30:57.92#ibcon#about to read 5, iclass 12, count 0 2006.201.20:30:57.92#ibcon#read 5, iclass 12, count 0 2006.201.20:30:57.92#ibcon#about to read 6, iclass 12, count 0 2006.201.20:30:57.92#ibcon#read 6, iclass 12, count 0 2006.201.20:30:57.92#ibcon#end of sib2, iclass 12, count 0 2006.201.20:30:57.92#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:30:57.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:30:57.92#ibcon#[27=USB\r\n] 2006.201.20:30:57.92#ibcon#*before write, iclass 12, count 0 2006.201.20:30:57.92#ibcon#enter sib2, iclass 12, count 0 2006.201.20:30:57.92#ibcon#flushed, iclass 12, count 0 2006.201.20:30:57.92#ibcon#about to write, iclass 12, count 0 2006.201.20:30:57.92#ibcon#wrote, iclass 12, count 0 2006.201.20:30:57.92#ibcon#about to read 3, iclass 12, count 0 2006.201.20:30:57.95#ibcon#read 3, iclass 12, count 0 2006.201.20:30:57.95#ibcon#about to read 4, iclass 12, count 0 2006.201.20:30:57.95#ibcon#read 4, iclass 12, count 0 2006.201.20:30:57.95#ibcon#about to read 5, iclass 12, count 0 2006.201.20:30:57.95#ibcon#read 5, iclass 12, count 0 2006.201.20:30:57.95#ibcon#about to read 6, iclass 12, count 0 2006.201.20:30:57.95#ibcon#read 6, iclass 12, count 0 2006.201.20:30:57.95#ibcon#end of sib2, iclass 12, count 0 2006.201.20:30:57.95#ibcon#*after write, iclass 12, count 0 2006.201.20:30:57.95#ibcon#*before return 0, iclass 12, count 0 2006.201.20:30:57.95#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:57.95#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:30:57.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:30:57.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:30:57.95$vck44/vblo=5,709.99 2006.201.20:30:57.95#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.20:30:57.95#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.20:30:57.95#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:57.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:57.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:57.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:57.95#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:30:57.95#ibcon#first serial, iclass 14, count 0 2006.201.20:30:57.95#ibcon#enter sib2, iclass 14, count 0 2006.201.20:30:57.95#ibcon#flushed, iclass 14, count 0 2006.201.20:30:57.95#ibcon#about to write, iclass 14, count 0 2006.201.20:30:57.95#ibcon#wrote, iclass 14, count 0 2006.201.20:30:57.95#ibcon#about to read 3, iclass 14, count 0 2006.201.20:30:57.97#ibcon#read 3, iclass 14, count 0 2006.201.20:30:57.97#ibcon#about to read 4, iclass 14, count 0 2006.201.20:30:57.97#ibcon#read 4, iclass 14, count 0 2006.201.20:30:57.97#ibcon#about to read 5, iclass 14, count 0 2006.201.20:30:57.97#ibcon#read 5, iclass 14, count 0 2006.201.20:30:57.97#ibcon#about to read 6, iclass 14, count 0 2006.201.20:30:57.97#ibcon#read 6, iclass 14, count 0 2006.201.20:30:57.97#ibcon#end of sib2, iclass 14, count 0 2006.201.20:30:57.97#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:30:57.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:30:57.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:30:57.97#ibcon#*before write, iclass 14, count 0 2006.201.20:30:57.97#ibcon#enter sib2, iclass 14, count 0 2006.201.20:30:57.97#ibcon#flushed, iclass 14, count 0 2006.201.20:30:57.97#ibcon#about to write, iclass 14, count 0 2006.201.20:30:57.97#ibcon#wrote, iclass 14, count 0 2006.201.20:30:57.97#ibcon#about to read 3, iclass 14, count 0 2006.201.20:30:58.01#ibcon#read 3, iclass 14, count 0 2006.201.20:30:58.01#ibcon#about to read 4, iclass 14, count 0 2006.201.20:30:58.01#ibcon#read 4, iclass 14, count 0 2006.201.20:30:58.01#ibcon#about to read 5, iclass 14, count 0 2006.201.20:30:58.01#ibcon#read 5, iclass 14, count 0 2006.201.20:30:58.01#ibcon#about to read 6, iclass 14, count 0 2006.201.20:30:58.01#ibcon#read 6, iclass 14, count 0 2006.201.20:30:58.01#ibcon#end of sib2, iclass 14, count 0 2006.201.20:30:58.01#ibcon#*after write, iclass 14, count 0 2006.201.20:30:58.01#ibcon#*before return 0, iclass 14, count 0 2006.201.20:30:58.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:58.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:30:58.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:30:58.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:30:58.01$vck44/vb=5,4 2006.201.20:30:58.01#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.20:30:58.01#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.20:30:58.01#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:58.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:58.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:58.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:58.07#ibcon#enter wrdev, iclass 16, count 2 2006.201.20:30:58.07#ibcon#first serial, iclass 16, count 2 2006.201.20:30:58.07#ibcon#enter sib2, iclass 16, count 2 2006.201.20:30:58.07#ibcon#flushed, iclass 16, count 2 2006.201.20:30:58.07#ibcon#about to write, iclass 16, count 2 2006.201.20:30:58.07#ibcon#wrote, iclass 16, count 2 2006.201.20:30:58.07#ibcon#about to read 3, iclass 16, count 2 2006.201.20:30:58.09#ibcon#read 3, iclass 16, count 2 2006.201.20:30:58.09#ibcon#about to read 4, iclass 16, count 2 2006.201.20:30:58.09#ibcon#read 4, iclass 16, count 2 2006.201.20:30:58.09#ibcon#about to read 5, iclass 16, count 2 2006.201.20:30:58.09#ibcon#read 5, iclass 16, count 2 2006.201.20:30:58.09#ibcon#about to read 6, iclass 16, count 2 2006.201.20:30:58.09#ibcon#read 6, iclass 16, count 2 2006.201.20:30:58.09#ibcon#end of sib2, iclass 16, count 2 2006.201.20:30:58.09#ibcon#*mode == 0, iclass 16, count 2 2006.201.20:30:58.09#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.20:30:58.09#ibcon#[27=AT05-04\r\n] 2006.201.20:30:58.09#ibcon#*before write, iclass 16, count 2 2006.201.20:30:58.09#ibcon#enter sib2, iclass 16, count 2 2006.201.20:30:58.09#ibcon#flushed, iclass 16, count 2 2006.201.20:30:58.09#ibcon#about to write, iclass 16, count 2 2006.201.20:30:58.09#ibcon#wrote, iclass 16, count 2 2006.201.20:30:58.09#ibcon#about to read 3, iclass 16, count 2 2006.201.20:30:58.12#ibcon#read 3, iclass 16, count 2 2006.201.20:30:58.12#ibcon#about to read 4, iclass 16, count 2 2006.201.20:30:58.12#ibcon#read 4, iclass 16, count 2 2006.201.20:30:58.12#ibcon#about to read 5, iclass 16, count 2 2006.201.20:30:58.12#ibcon#read 5, iclass 16, count 2 2006.201.20:30:58.12#ibcon#about to read 6, iclass 16, count 2 2006.201.20:30:58.12#ibcon#read 6, iclass 16, count 2 2006.201.20:30:58.12#ibcon#end of sib2, iclass 16, count 2 2006.201.20:30:58.12#ibcon#*after write, iclass 16, count 2 2006.201.20:30:58.12#ibcon#*before return 0, iclass 16, count 2 2006.201.20:30:58.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:58.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:30:58.12#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.20:30:58.12#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:58.12#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:58.24#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:58.24#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:58.24#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:30:58.24#ibcon#first serial, iclass 16, count 0 2006.201.20:30:58.24#ibcon#enter sib2, iclass 16, count 0 2006.201.20:30:58.24#ibcon#flushed, iclass 16, count 0 2006.201.20:30:58.24#ibcon#about to write, iclass 16, count 0 2006.201.20:30:58.24#ibcon#wrote, iclass 16, count 0 2006.201.20:30:58.24#ibcon#about to read 3, iclass 16, count 0 2006.201.20:30:58.26#ibcon#read 3, iclass 16, count 0 2006.201.20:30:58.26#ibcon#about to read 4, iclass 16, count 0 2006.201.20:30:58.26#ibcon#read 4, iclass 16, count 0 2006.201.20:30:58.26#ibcon#about to read 5, iclass 16, count 0 2006.201.20:30:58.26#ibcon#read 5, iclass 16, count 0 2006.201.20:30:58.26#ibcon#about to read 6, iclass 16, count 0 2006.201.20:30:58.26#ibcon#read 6, iclass 16, count 0 2006.201.20:30:58.26#ibcon#end of sib2, iclass 16, count 0 2006.201.20:30:58.26#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:30:58.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:30:58.26#ibcon#[27=USB\r\n] 2006.201.20:30:58.26#ibcon#*before write, iclass 16, count 0 2006.201.20:30:58.26#ibcon#enter sib2, iclass 16, count 0 2006.201.20:30:58.26#ibcon#flushed, iclass 16, count 0 2006.201.20:30:58.26#ibcon#about to write, iclass 16, count 0 2006.201.20:30:58.26#ibcon#wrote, iclass 16, count 0 2006.201.20:30:58.26#ibcon#about to read 3, iclass 16, count 0 2006.201.20:30:58.29#ibcon#read 3, iclass 16, count 0 2006.201.20:30:58.29#ibcon#about to read 4, iclass 16, count 0 2006.201.20:30:58.29#ibcon#read 4, iclass 16, count 0 2006.201.20:30:58.29#ibcon#about to read 5, iclass 16, count 0 2006.201.20:30:58.29#ibcon#read 5, iclass 16, count 0 2006.201.20:30:58.29#ibcon#about to read 6, iclass 16, count 0 2006.201.20:30:58.29#ibcon#read 6, iclass 16, count 0 2006.201.20:30:58.29#ibcon#end of sib2, iclass 16, count 0 2006.201.20:30:58.29#ibcon#*after write, iclass 16, count 0 2006.201.20:30:58.29#ibcon#*before return 0, iclass 16, count 0 2006.201.20:30:58.29#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:58.29#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:30:58.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:30:58.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:30:58.29$vck44/vblo=6,719.99 2006.201.20:30:58.29#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.20:30:58.29#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.20:30:58.29#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:58.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:58.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:58.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:58.29#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:30:58.29#ibcon#first serial, iclass 18, count 0 2006.201.20:30:58.29#ibcon#enter sib2, iclass 18, count 0 2006.201.20:30:58.29#ibcon#flushed, iclass 18, count 0 2006.201.20:30:58.29#ibcon#about to write, iclass 18, count 0 2006.201.20:30:58.29#ibcon#wrote, iclass 18, count 0 2006.201.20:30:58.29#ibcon#about to read 3, iclass 18, count 0 2006.201.20:30:58.31#ibcon#read 3, iclass 18, count 0 2006.201.20:30:58.31#ibcon#about to read 4, iclass 18, count 0 2006.201.20:30:58.31#ibcon#read 4, iclass 18, count 0 2006.201.20:30:58.31#ibcon#about to read 5, iclass 18, count 0 2006.201.20:30:58.31#ibcon#read 5, iclass 18, count 0 2006.201.20:30:58.31#ibcon#about to read 6, iclass 18, count 0 2006.201.20:30:58.31#ibcon#read 6, iclass 18, count 0 2006.201.20:30:58.31#ibcon#end of sib2, iclass 18, count 0 2006.201.20:30:58.31#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:30:58.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:30:58.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:30:58.31#ibcon#*before write, iclass 18, count 0 2006.201.20:30:58.31#ibcon#enter sib2, iclass 18, count 0 2006.201.20:30:58.31#ibcon#flushed, iclass 18, count 0 2006.201.20:30:58.31#ibcon#about to write, iclass 18, count 0 2006.201.20:30:58.31#ibcon#wrote, iclass 18, count 0 2006.201.20:30:58.31#ibcon#about to read 3, iclass 18, count 0 2006.201.20:30:58.36#ibcon#read 3, iclass 18, count 0 2006.201.20:30:58.36#ibcon#about to read 4, iclass 18, count 0 2006.201.20:30:58.36#ibcon#read 4, iclass 18, count 0 2006.201.20:30:58.36#ibcon#about to read 5, iclass 18, count 0 2006.201.20:30:58.36#ibcon#read 5, iclass 18, count 0 2006.201.20:30:58.36#ibcon#about to read 6, iclass 18, count 0 2006.201.20:30:58.36#ibcon#read 6, iclass 18, count 0 2006.201.20:30:58.36#ibcon#end of sib2, iclass 18, count 0 2006.201.20:30:58.36#ibcon#*after write, iclass 18, count 0 2006.201.20:30:58.36#ibcon#*before return 0, iclass 18, count 0 2006.201.20:30:58.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:58.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:30:58.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:30:58.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:30:58.36$vck44/vb=6,4 2006.201.20:30:58.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.20:30:58.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.20:30:58.36#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:58.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:58.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:58.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:58.41#ibcon#enter wrdev, iclass 20, count 2 2006.201.20:30:58.41#ibcon#first serial, iclass 20, count 2 2006.201.20:30:58.41#ibcon#enter sib2, iclass 20, count 2 2006.201.20:30:58.41#ibcon#flushed, iclass 20, count 2 2006.201.20:30:58.41#ibcon#about to write, iclass 20, count 2 2006.201.20:30:58.41#ibcon#wrote, iclass 20, count 2 2006.201.20:30:58.41#ibcon#about to read 3, iclass 20, count 2 2006.201.20:30:58.43#ibcon#read 3, iclass 20, count 2 2006.201.20:30:58.43#ibcon#about to read 4, iclass 20, count 2 2006.201.20:30:58.43#ibcon#read 4, iclass 20, count 2 2006.201.20:30:58.43#ibcon#about to read 5, iclass 20, count 2 2006.201.20:30:58.43#ibcon#read 5, iclass 20, count 2 2006.201.20:30:58.43#ibcon#about to read 6, iclass 20, count 2 2006.201.20:30:58.43#ibcon#read 6, iclass 20, count 2 2006.201.20:30:58.43#ibcon#end of sib2, iclass 20, count 2 2006.201.20:30:58.43#ibcon#*mode == 0, iclass 20, count 2 2006.201.20:30:58.43#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.20:30:58.43#ibcon#[27=AT06-04\r\n] 2006.201.20:30:58.43#ibcon#*before write, iclass 20, count 2 2006.201.20:30:58.43#ibcon#enter sib2, iclass 20, count 2 2006.201.20:30:58.43#ibcon#flushed, iclass 20, count 2 2006.201.20:30:58.43#ibcon#about to write, iclass 20, count 2 2006.201.20:30:58.43#ibcon#wrote, iclass 20, count 2 2006.201.20:30:58.43#ibcon#about to read 3, iclass 20, count 2 2006.201.20:30:58.46#ibcon#read 3, iclass 20, count 2 2006.201.20:30:58.46#ibcon#about to read 4, iclass 20, count 2 2006.201.20:30:58.46#ibcon#read 4, iclass 20, count 2 2006.201.20:30:58.46#ibcon#about to read 5, iclass 20, count 2 2006.201.20:30:58.46#ibcon#read 5, iclass 20, count 2 2006.201.20:30:58.46#ibcon#about to read 6, iclass 20, count 2 2006.201.20:30:58.46#ibcon#read 6, iclass 20, count 2 2006.201.20:30:58.46#ibcon#end of sib2, iclass 20, count 2 2006.201.20:30:58.46#ibcon#*after write, iclass 20, count 2 2006.201.20:30:58.46#ibcon#*before return 0, iclass 20, count 2 2006.201.20:30:58.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:58.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:30:58.46#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.20:30:58.46#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:58.46#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:58.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:58.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:58.58#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:30:58.58#ibcon#first serial, iclass 20, count 0 2006.201.20:30:58.58#ibcon#enter sib2, iclass 20, count 0 2006.201.20:30:58.58#ibcon#flushed, iclass 20, count 0 2006.201.20:30:58.58#ibcon#about to write, iclass 20, count 0 2006.201.20:30:58.58#ibcon#wrote, iclass 20, count 0 2006.201.20:30:58.58#ibcon#about to read 3, iclass 20, count 0 2006.201.20:30:58.60#ibcon#read 3, iclass 20, count 0 2006.201.20:30:58.60#ibcon#about to read 4, iclass 20, count 0 2006.201.20:30:58.60#ibcon#read 4, iclass 20, count 0 2006.201.20:30:58.60#ibcon#about to read 5, iclass 20, count 0 2006.201.20:30:58.60#ibcon#read 5, iclass 20, count 0 2006.201.20:30:58.60#ibcon#about to read 6, iclass 20, count 0 2006.201.20:30:58.60#ibcon#read 6, iclass 20, count 0 2006.201.20:30:58.60#ibcon#end of sib2, iclass 20, count 0 2006.201.20:30:58.60#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:30:58.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:30:58.60#ibcon#[27=USB\r\n] 2006.201.20:30:58.60#ibcon#*before write, iclass 20, count 0 2006.201.20:30:58.60#ibcon#enter sib2, iclass 20, count 0 2006.201.20:30:58.60#ibcon#flushed, iclass 20, count 0 2006.201.20:30:58.60#ibcon#about to write, iclass 20, count 0 2006.201.20:30:58.60#ibcon#wrote, iclass 20, count 0 2006.201.20:30:58.60#ibcon#about to read 3, iclass 20, count 0 2006.201.20:30:58.63#ibcon#read 3, iclass 20, count 0 2006.201.20:30:58.63#ibcon#about to read 4, iclass 20, count 0 2006.201.20:30:58.63#ibcon#read 4, iclass 20, count 0 2006.201.20:30:58.63#ibcon#about to read 5, iclass 20, count 0 2006.201.20:30:58.63#ibcon#read 5, iclass 20, count 0 2006.201.20:30:58.63#ibcon#about to read 6, iclass 20, count 0 2006.201.20:30:58.63#ibcon#read 6, iclass 20, count 0 2006.201.20:30:58.63#ibcon#end of sib2, iclass 20, count 0 2006.201.20:30:58.63#ibcon#*after write, iclass 20, count 0 2006.201.20:30:58.63#ibcon#*before return 0, iclass 20, count 0 2006.201.20:30:58.63#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:58.63#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:30:58.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:30:58.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:30:58.63$vck44/vblo=7,734.99 2006.201.20:30:58.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.20:30:58.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.20:30:58.63#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:58.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:58.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:58.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:58.63#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:30:58.63#ibcon#first serial, iclass 22, count 0 2006.201.20:30:58.63#ibcon#enter sib2, iclass 22, count 0 2006.201.20:30:58.63#ibcon#flushed, iclass 22, count 0 2006.201.20:30:58.63#ibcon#about to write, iclass 22, count 0 2006.201.20:30:58.63#ibcon#wrote, iclass 22, count 0 2006.201.20:30:58.63#ibcon#about to read 3, iclass 22, count 0 2006.201.20:30:58.65#ibcon#read 3, iclass 22, count 0 2006.201.20:30:58.65#ibcon#about to read 4, iclass 22, count 0 2006.201.20:30:58.65#ibcon#read 4, iclass 22, count 0 2006.201.20:30:58.65#ibcon#about to read 5, iclass 22, count 0 2006.201.20:30:58.65#ibcon#read 5, iclass 22, count 0 2006.201.20:30:58.65#ibcon#about to read 6, iclass 22, count 0 2006.201.20:30:58.65#ibcon#read 6, iclass 22, count 0 2006.201.20:30:58.65#ibcon#end of sib2, iclass 22, count 0 2006.201.20:30:58.65#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:30:58.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:30:58.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:30:58.65#ibcon#*before write, iclass 22, count 0 2006.201.20:30:58.65#ibcon#enter sib2, iclass 22, count 0 2006.201.20:30:58.65#ibcon#flushed, iclass 22, count 0 2006.201.20:30:58.65#ibcon#about to write, iclass 22, count 0 2006.201.20:30:58.65#ibcon#wrote, iclass 22, count 0 2006.201.20:30:58.65#ibcon#about to read 3, iclass 22, count 0 2006.201.20:30:58.69#ibcon#read 3, iclass 22, count 0 2006.201.20:30:58.69#ibcon#about to read 4, iclass 22, count 0 2006.201.20:30:58.69#ibcon#read 4, iclass 22, count 0 2006.201.20:30:58.69#ibcon#about to read 5, iclass 22, count 0 2006.201.20:30:58.69#ibcon#read 5, iclass 22, count 0 2006.201.20:30:58.69#ibcon#about to read 6, iclass 22, count 0 2006.201.20:30:58.69#ibcon#read 6, iclass 22, count 0 2006.201.20:30:58.69#ibcon#end of sib2, iclass 22, count 0 2006.201.20:30:58.69#ibcon#*after write, iclass 22, count 0 2006.201.20:30:58.69#ibcon#*before return 0, iclass 22, count 0 2006.201.20:30:58.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:58.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:30:58.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:30:58.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:30:58.69$vck44/vb=7,4 2006.201.20:30:58.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.20:30:58.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.20:30:58.69#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:58.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:58.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:58.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:58.75#ibcon#enter wrdev, iclass 24, count 2 2006.201.20:30:58.75#ibcon#first serial, iclass 24, count 2 2006.201.20:30:58.75#ibcon#enter sib2, iclass 24, count 2 2006.201.20:30:58.75#ibcon#flushed, iclass 24, count 2 2006.201.20:30:58.75#ibcon#about to write, iclass 24, count 2 2006.201.20:30:58.75#ibcon#wrote, iclass 24, count 2 2006.201.20:30:58.75#ibcon#about to read 3, iclass 24, count 2 2006.201.20:30:58.77#ibcon#read 3, iclass 24, count 2 2006.201.20:30:58.77#ibcon#about to read 4, iclass 24, count 2 2006.201.20:30:58.77#ibcon#read 4, iclass 24, count 2 2006.201.20:30:58.77#ibcon#about to read 5, iclass 24, count 2 2006.201.20:30:58.77#ibcon#read 5, iclass 24, count 2 2006.201.20:30:58.77#ibcon#about to read 6, iclass 24, count 2 2006.201.20:30:58.77#ibcon#read 6, iclass 24, count 2 2006.201.20:30:58.77#ibcon#end of sib2, iclass 24, count 2 2006.201.20:30:58.77#ibcon#*mode == 0, iclass 24, count 2 2006.201.20:30:58.77#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.20:30:58.77#ibcon#[27=AT07-04\r\n] 2006.201.20:30:58.77#ibcon#*before write, iclass 24, count 2 2006.201.20:30:58.77#ibcon#enter sib2, iclass 24, count 2 2006.201.20:30:58.77#ibcon#flushed, iclass 24, count 2 2006.201.20:30:58.77#ibcon#about to write, iclass 24, count 2 2006.201.20:30:58.77#ibcon#wrote, iclass 24, count 2 2006.201.20:30:58.77#ibcon#about to read 3, iclass 24, count 2 2006.201.20:30:58.80#ibcon#read 3, iclass 24, count 2 2006.201.20:30:58.80#ibcon#about to read 4, iclass 24, count 2 2006.201.20:30:58.80#ibcon#read 4, iclass 24, count 2 2006.201.20:30:58.80#ibcon#about to read 5, iclass 24, count 2 2006.201.20:30:58.80#ibcon#read 5, iclass 24, count 2 2006.201.20:30:58.80#ibcon#about to read 6, iclass 24, count 2 2006.201.20:30:58.80#ibcon#read 6, iclass 24, count 2 2006.201.20:30:58.80#ibcon#end of sib2, iclass 24, count 2 2006.201.20:30:58.80#ibcon#*after write, iclass 24, count 2 2006.201.20:30:58.80#ibcon#*before return 0, iclass 24, count 2 2006.201.20:30:58.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:58.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:30:58.80#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.20:30:58.80#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:58.80#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:58.92#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:58.92#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:58.92#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:30:58.92#ibcon#first serial, iclass 24, count 0 2006.201.20:30:58.92#ibcon#enter sib2, iclass 24, count 0 2006.201.20:30:58.92#ibcon#flushed, iclass 24, count 0 2006.201.20:30:58.92#ibcon#about to write, iclass 24, count 0 2006.201.20:30:58.92#ibcon#wrote, iclass 24, count 0 2006.201.20:30:58.92#ibcon#about to read 3, iclass 24, count 0 2006.201.20:30:58.94#ibcon#read 3, iclass 24, count 0 2006.201.20:30:58.94#ibcon#about to read 4, iclass 24, count 0 2006.201.20:30:58.94#ibcon#read 4, iclass 24, count 0 2006.201.20:30:58.94#ibcon#about to read 5, iclass 24, count 0 2006.201.20:30:58.94#ibcon#read 5, iclass 24, count 0 2006.201.20:30:58.94#ibcon#about to read 6, iclass 24, count 0 2006.201.20:30:58.94#ibcon#read 6, iclass 24, count 0 2006.201.20:30:58.94#ibcon#end of sib2, iclass 24, count 0 2006.201.20:30:58.94#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:30:58.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:30:58.94#ibcon#[27=USB\r\n] 2006.201.20:30:58.94#ibcon#*before write, iclass 24, count 0 2006.201.20:30:58.94#ibcon#enter sib2, iclass 24, count 0 2006.201.20:30:58.94#ibcon#flushed, iclass 24, count 0 2006.201.20:30:58.94#ibcon#about to write, iclass 24, count 0 2006.201.20:30:58.94#ibcon#wrote, iclass 24, count 0 2006.201.20:30:58.94#ibcon#about to read 3, iclass 24, count 0 2006.201.20:30:58.97#ibcon#read 3, iclass 24, count 0 2006.201.20:30:58.97#ibcon#about to read 4, iclass 24, count 0 2006.201.20:30:58.97#ibcon#read 4, iclass 24, count 0 2006.201.20:30:58.97#ibcon#about to read 5, iclass 24, count 0 2006.201.20:30:58.97#ibcon#read 5, iclass 24, count 0 2006.201.20:30:58.97#ibcon#about to read 6, iclass 24, count 0 2006.201.20:30:58.97#ibcon#read 6, iclass 24, count 0 2006.201.20:30:58.97#ibcon#end of sib2, iclass 24, count 0 2006.201.20:30:58.97#ibcon#*after write, iclass 24, count 0 2006.201.20:30:58.97#ibcon#*before return 0, iclass 24, count 0 2006.201.20:30:58.97#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:58.97#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:30:58.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:30:58.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:30:58.97$vck44/vblo=8,744.99 2006.201.20:30:58.97#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.20:30:58.97#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.20:30:58.97#ibcon#ireg 17 cls_cnt 0 2006.201.20:30:58.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:58.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:58.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:58.97#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:30:58.97#ibcon#first serial, iclass 26, count 0 2006.201.20:30:58.97#ibcon#enter sib2, iclass 26, count 0 2006.201.20:30:58.97#ibcon#flushed, iclass 26, count 0 2006.201.20:30:58.97#ibcon#about to write, iclass 26, count 0 2006.201.20:30:58.97#ibcon#wrote, iclass 26, count 0 2006.201.20:30:58.97#ibcon#about to read 3, iclass 26, count 0 2006.201.20:30:58.99#ibcon#read 3, iclass 26, count 0 2006.201.20:30:58.99#ibcon#about to read 4, iclass 26, count 0 2006.201.20:30:58.99#ibcon#read 4, iclass 26, count 0 2006.201.20:30:58.99#ibcon#about to read 5, iclass 26, count 0 2006.201.20:30:58.99#ibcon#read 5, iclass 26, count 0 2006.201.20:30:58.99#ibcon#about to read 6, iclass 26, count 0 2006.201.20:30:58.99#ibcon#read 6, iclass 26, count 0 2006.201.20:30:58.99#ibcon#end of sib2, iclass 26, count 0 2006.201.20:30:58.99#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:30:58.99#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:30:58.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:30:58.99#ibcon#*before write, iclass 26, count 0 2006.201.20:30:58.99#ibcon#enter sib2, iclass 26, count 0 2006.201.20:30:58.99#ibcon#flushed, iclass 26, count 0 2006.201.20:30:58.99#ibcon#about to write, iclass 26, count 0 2006.201.20:30:58.99#ibcon#wrote, iclass 26, count 0 2006.201.20:30:58.99#ibcon#about to read 3, iclass 26, count 0 2006.201.20:30:59.04#ibcon#read 3, iclass 26, count 0 2006.201.20:30:59.04#ibcon#about to read 4, iclass 26, count 0 2006.201.20:30:59.04#ibcon#read 4, iclass 26, count 0 2006.201.20:30:59.04#ibcon#about to read 5, iclass 26, count 0 2006.201.20:30:59.04#ibcon#read 5, iclass 26, count 0 2006.201.20:30:59.04#ibcon#about to read 6, iclass 26, count 0 2006.201.20:30:59.04#ibcon#read 6, iclass 26, count 0 2006.201.20:30:59.04#ibcon#end of sib2, iclass 26, count 0 2006.201.20:30:59.04#ibcon#*after write, iclass 26, count 0 2006.201.20:30:59.04#ibcon#*before return 0, iclass 26, count 0 2006.201.20:30:59.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:59.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:30:59.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:30:59.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:30:59.04$vck44/vb=8,4 2006.201.20:30:59.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.20:30:59.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.20:30:59.04#ibcon#ireg 11 cls_cnt 2 2006.201.20:30:59.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:59.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:59.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:59.09#ibcon#enter wrdev, iclass 28, count 2 2006.201.20:30:59.09#ibcon#first serial, iclass 28, count 2 2006.201.20:30:59.09#ibcon#enter sib2, iclass 28, count 2 2006.201.20:30:59.09#ibcon#flushed, iclass 28, count 2 2006.201.20:30:59.09#ibcon#about to write, iclass 28, count 2 2006.201.20:30:59.09#ibcon#wrote, iclass 28, count 2 2006.201.20:30:59.09#ibcon#about to read 3, iclass 28, count 2 2006.201.20:30:59.11#ibcon#read 3, iclass 28, count 2 2006.201.20:30:59.11#ibcon#about to read 4, iclass 28, count 2 2006.201.20:30:59.11#ibcon#read 4, iclass 28, count 2 2006.201.20:30:59.11#ibcon#about to read 5, iclass 28, count 2 2006.201.20:30:59.11#ibcon#read 5, iclass 28, count 2 2006.201.20:30:59.11#ibcon#about to read 6, iclass 28, count 2 2006.201.20:30:59.11#ibcon#read 6, iclass 28, count 2 2006.201.20:30:59.11#ibcon#end of sib2, iclass 28, count 2 2006.201.20:30:59.11#ibcon#*mode == 0, iclass 28, count 2 2006.201.20:30:59.11#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.20:30:59.11#ibcon#[27=AT08-04\r\n] 2006.201.20:30:59.11#ibcon#*before write, iclass 28, count 2 2006.201.20:30:59.11#ibcon#enter sib2, iclass 28, count 2 2006.201.20:30:59.11#ibcon#flushed, iclass 28, count 2 2006.201.20:30:59.11#ibcon#about to write, iclass 28, count 2 2006.201.20:30:59.11#ibcon#wrote, iclass 28, count 2 2006.201.20:30:59.11#ibcon#about to read 3, iclass 28, count 2 2006.201.20:30:59.14#ibcon#read 3, iclass 28, count 2 2006.201.20:30:59.14#ibcon#about to read 4, iclass 28, count 2 2006.201.20:30:59.14#ibcon#read 4, iclass 28, count 2 2006.201.20:30:59.14#ibcon#about to read 5, iclass 28, count 2 2006.201.20:30:59.14#ibcon#read 5, iclass 28, count 2 2006.201.20:30:59.14#ibcon#about to read 6, iclass 28, count 2 2006.201.20:30:59.14#ibcon#read 6, iclass 28, count 2 2006.201.20:30:59.14#ibcon#end of sib2, iclass 28, count 2 2006.201.20:30:59.14#ibcon#*after write, iclass 28, count 2 2006.201.20:30:59.14#ibcon#*before return 0, iclass 28, count 2 2006.201.20:30:59.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:59.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:30:59.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.20:30:59.14#ibcon#ireg 7 cls_cnt 0 2006.201.20:30:59.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:59.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:59.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:59.26#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:30:59.26#ibcon#first serial, iclass 28, count 0 2006.201.20:30:59.26#ibcon#enter sib2, iclass 28, count 0 2006.201.20:30:59.26#ibcon#flushed, iclass 28, count 0 2006.201.20:30:59.26#ibcon#about to write, iclass 28, count 0 2006.201.20:30:59.26#ibcon#wrote, iclass 28, count 0 2006.201.20:30:59.26#ibcon#about to read 3, iclass 28, count 0 2006.201.20:30:59.28#ibcon#read 3, iclass 28, count 0 2006.201.20:30:59.28#ibcon#about to read 4, iclass 28, count 0 2006.201.20:30:59.28#ibcon#read 4, iclass 28, count 0 2006.201.20:30:59.28#ibcon#about to read 5, iclass 28, count 0 2006.201.20:30:59.28#ibcon#read 5, iclass 28, count 0 2006.201.20:30:59.28#ibcon#about to read 6, iclass 28, count 0 2006.201.20:30:59.28#ibcon#read 6, iclass 28, count 0 2006.201.20:30:59.28#ibcon#end of sib2, iclass 28, count 0 2006.201.20:30:59.28#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:30:59.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:30:59.28#ibcon#[27=USB\r\n] 2006.201.20:30:59.28#ibcon#*before write, iclass 28, count 0 2006.201.20:30:59.28#ibcon#enter sib2, iclass 28, count 0 2006.201.20:30:59.28#ibcon#flushed, iclass 28, count 0 2006.201.20:30:59.28#ibcon#about to write, iclass 28, count 0 2006.201.20:30:59.28#ibcon#wrote, iclass 28, count 0 2006.201.20:30:59.28#ibcon#about to read 3, iclass 28, count 0 2006.201.20:30:59.31#ibcon#read 3, iclass 28, count 0 2006.201.20:30:59.31#ibcon#about to read 4, iclass 28, count 0 2006.201.20:30:59.31#ibcon#read 4, iclass 28, count 0 2006.201.20:30:59.31#ibcon#about to read 5, iclass 28, count 0 2006.201.20:30:59.31#ibcon#read 5, iclass 28, count 0 2006.201.20:30:59.31#ibcon#about to read 6, iclass 28, count 0 2006.201.20:30:59.31#ibcon#read 6, iclass 28, count 0 2006.201.20:30:59.31#ibcon#end of sib2, iclass 28, count 0 2006.201.20:30:59.31#ibcon#*after write, iclass 28, count 0 2006.201.20:30:59.31#ibcon#*before return 0, iclass 28, count 0 2006.201.20:30:59.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:59.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:30:59.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:30:59.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:30:59.31$vck44/vabw=wide 2006.201.20:30:59.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.20:30:59.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.20:30:59.31#ibcon#ireg 8 cls_cnt 0 2006.201.20:30:59.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:59.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:59.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:59.31#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:30:59.31#ibcon#first serial, iclass 30, count 0 2006.201.20:30:59.31#ibcon#enter sib2, iclass 30, count 0 2006.201.20:30:59.31#ibcon#flushed, iclass 30, count 0 2006.201.20:30:59.31#ibcon#about to write, iclass 30, count 0 2006.201.20:30:59.31#ibcon#wrote, iclass 30, count 0 2006.201.20:30:59.31#ibcon#about to read 3, iclass 30, count 0 2006.201.20:30:59.33#ibcon#read 3, iclass 30, count 0 2006.201.20:30:59.33#ibcon#about to read 4, iclass 30, count 0 2006.201.20:30:59.33#ibcon#read 4, iclass 30, count 0 2006.201.20:30:59.33#ibcon#about to read 5, iclass 30, count 0 2006.201.20:30:59.33#ibcon#read 5, iclass 30, count 0 2006.201.20:30:59.33#ibcon#about to read 6, iclass 30, count 0 2006.201.20:30:59.33#ibcon#read 6, iclass 30, count 0 2006.201.20:30:59.33#ibcon#end of sib2, iclass 30, count 0 2006.201.20:30:59.33#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:30:59.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:30:59.33#ibcon#[25=BW32\r\n] 2006.201.20:30:59.33#ibcon#*before write, iclass 30, count 0 2006.201.20:30:59.33#ibcon#enter sib2, iclass 30, count 0 2006.201.20:30:59.33#ibcon#flushed, iclass 30, count 0 2006.201.20:30:59.33#ibcon#about to write, iclass 30, count 0 2006.201.20:30:59.33#ibcon#wrote, iclass 30, count 0 2006.201.20:30:59.33#ibcon#about to read 3, iclass 30, count 0 2006.201.20:30:59.36#ibcon#read 3, iclass 30, count 0 2006.201.20:30:59.36#ibcon#about to read 4, iclass 30, count 0 2006.201.20:30:59.36#ibcon#read 4, iclass 30, count 0 2006.201.20:30:59.36#ibcon#about to read 5, iclass 30, count 0 2006.201.20:30:59.36#ibcon#read 5, iclass 30, count 0 2006.201.20:30:59.36#ibcon#about to read 6, iclass 30, count 0 2006.201.20:30:59.36#ibcon#read 6, iclass 30, count 0 2006.201.20:30:59.36#ibcon#end of sib2, iclass 30, count 0 2006.201.20:30:59.36#ibcon#*after write, iclass 30, count 0 2006.201.20:30:59.36#ibcon#*before return 0, iclass 30, count 0 2006.201.20:30:59.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:59.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:30:59.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:30:59.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:30:59.36$vck44/vbbw=wide 2006.201.20:30:59.36#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.20:30:59.36#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.20:30:59.36#ibcon#ireg 8 cls_cnt 0 2006.201.20:30:59.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:30:59.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:30:59.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:30:59.43#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:30:59.43#ibcon#first serial, iclass 32, count 0 2006.201.20:30:59.43#ibcon#enter sib2, iclass 32, count 0 2006.201.20:30:59.43#ibcon#flushed, iclass 32, count 0 2006.201.20:30:59.43#ibcon#about to write, iclass 32, count 0 2006.201.20:30:59.43#ibcon#wrote, iclass 32, count 0 2006.201.20:30:59.43#ibcon#about to read 3, iclass 32, count 0 2006.201.20:30:59.45#ibcon#read 3, iclass 32, count 0 2006.201.20:30:59.45#ibcon#about to read 4, iclass 32, count 0 2006.201.20:30:59.45#ibcon#read 4, iclass 32, count 0 2006.201.20:30:59.45#ibcon#about to read 5, iclass 32, count 0 2006.201.20:30:59.45#ibcon#read 5, iclass 32, count 0 2006.201.20:30:59.45#ibcon#about to read 6, iclass 32, count 0 2006.201.20:30:59.45#ibcon#read 6, iclass 32, count 0 2006.201.20:30:59.45#ibcon#end of sib2, iclass 32, count 0 2006.201.20:30:59.45#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:30:59.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:30:59.45#ibcon#[27=BW32\r\n] 2006.201.20:30:59.45#ibcon#*before write, iclass 32, count 0 2006.201.20:30:59.45#ibcon#enter sib2, iclass 32, count 0 2006.201.20:30:59.45#ibcon#flushed, iclass 32, count 0 2006.201.20:30:59.45#ibcon#about to write, iclass 32, count 0 2006.201.20:30:59.45#ibcon#wrote, iclass 32, count 0 2006.201.20:30:59.45#ibcon#about to read 3, iclass 32, count 0 2006.201.20:30:59.48#ibcon#read 3, iclass 32, count 0 2006.201.20:30:59.48#ibcon#about to read 4, iclass 32, count 0 2006.201.20:30:59.48#ibcon#read 4, iclass 32, count 0 2006.201.20:30:59.48#ibcon#about to read 5, iclass 32, count 0 2006.201.20:30:59.48#ibcon#read 5, iclass 32, count 0 2006.201.20:30:59.48#ibcon#about to read 6, iclass 32, count 0 2006.201.20:30:59.48#ibcon#read 6, iclass 32, count 0 2006.201.20:30:59.48#ibcon#end of sib2, iclass 32, count 0 2006.201.20:30:59.48#ibcon#*after write, iclass 32, count 0 2006.201.20:30:59.48#ibcon#*before return 0, iclass 32, count 0 2006.201.20:30:59.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:30:59.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:30:59.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:30:59.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:30:59.48$setupk4/ifdk4 2006.201.20:30:59.48$ifdk4/lo= 2006.201.20:30:59.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:30:59.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:30:59.48$ifdk4/patch= 2006.201.20:30:59.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:30:59.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:30:59.48$setupk4/!*+20s 2006.201.20:31:00.77#abcon#<5=/04 1.2 2.3 20.081001002.4\r\n> 2006.201.20:31:00.79#abcon#{5=INTERFACE CLEAR} 2006.201.20:31:00.86#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:31:03.14#trakl#Source acquired 2006.201.20:31:04.14#flagr#flagr/antenna,acquired 2006.201.20:31:10.95#abcon#<5=/04 1.2 2.3 20.081001002.4\r\n> 2006.201.20:31:10.97#abcon#{5=INTERFACE CLEAR} 2006.201.20:31:11.03#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:31:13.97$setupk4/"tpicd 2006.201.20:31:13.97$setupk4/echo=off 2006.201.20:31:13.97$setupk4/xlog=off 2006.201.20:31:13.97:!2006.201.20:34:41 2006.201.20:34:41.00:preob 2006.201.20:34:41.13/onsource/TRACKING 2006.201.20:34:41.13:!2006.201.20:34:51 2006.201.20:34:51.00:"tape 2006.201.20:34:51.00:"st=record 2006.201.20:34:51.00:data_valid=on 2006.201.20:34:51.00:midob 2006.201.20:34:52.13/onsource/TRACKING 2006.201.20:34:52.13/wx/20.08,1002.4,100 2006.201.20:34:52.22/cable/+6.4818E-03 2006.201.20:34:53.31/va/01,08,usb,yes,43,45 2006.201.20:34:53.31/va/02,07,usb,yes,46,47 2006.201.20:34:53.31/va/03,08,usb,yes,42,43 2006.201.20:34:53.31/va/04,07,usb,yes,47,50 2006.201.20:34:53.31/va/05,04,usb,yes,42,43 2006.201.20:34:53.31/va/06,05,usb,yes,43,42 2006.201.20:34:53.31/va/07,05,usb,yes,42,43 2006.201.20:34:53.31/va/08,04,usb,yes,41,49 2006.201.20:34:53.54/valo/01,524.99,yes,locked 2006.201.20:34:53.54/valo/02,534.99,yes,locked 2006.201.20:34:53.54/valo/03,564.99,yes,locked 2006.201.20:34:53.54/valo/04,624.99,yes,locked 2006.201.20:34:53.54/valo/05,734.99,yes,locked 2006.201.20:34:53.54/valo/06,814.99,yes,locked 2006.201.20:34:53.54/valo/07,864.99,yes,locked 2006.201.20:34:53.54/valo/08,884.99,yes,locked 2006.201.20:34:54.63/vb/01,04,usb,yes,29,27 2006.201.20:34:54.63/vb/02,05,usb,yes,27,27 2006.201.20:34:54.63/vb/03,04,usb,yes,28,31 2006.201.20:34:54.63/vb/04,05,usb,yes,29,28 2006.201.20:34:54.63/vb/05,04,usb,yes,25,28 2006.201.20:34:54.63/vb/06,04,usb,yes,30,26 2006.201.20:34:54.63/vb/07,04,usb,yes,30,29 2006.201.20:34:54.63/vb/08,04,usb,yes,27,30 2006.201.20:34:54.86/vblo/01,629.99,yes,locked 2006.201.20:34:54.86/vblo/02,634.99,yes,locked 2006.201.20:34:54.86/vblo/03,649.99,yes,locked 2006.201.20:34:54.86/vblo/04,679.99,yes,locked 2006.201.20:34:54.86/vblo/05,709.99,yes,locked 2006.201.20:34:54.86/vblo/06,719.99,yes,locked 2006.201.20:34:54.86/vblo/07,734.99,yes,locked 2006.201.20:34:54.86/vblo/08,744.99,yes,locked 2006.201.20:34:55.01/vabw/8 2006.201.20:34:55.16/vbbw/8 2006.201.20:34:55.25/xfe/off,on,16.5 2006.201.20:34:55.64/ifatt/23,28,28,28 2006.201.20:34:56.06/fmout-gps/S +4.57E-07 2006.201.20:34:56.13:!2006.201.20:36:11 2006.201.20:36:11.00:data_valid=off 2006.201.20:36:11.00:"et 2006.201.20:36:11.00:!+3s 2006.201.20:36:14.02:"tape 2006.201.20:36:14.02:postob 2006.201.20:36:14.21/cable/+6.4804E-03 2006.201.20:36:14.21/wx/20.10,1002.3,100 2006.201.20:36:14.28/fmout-gps/S +4.56E-07 2006.201.20:36:14.28:scan_name=201-2038,jd0607,40 2006.201.20:36:14.28:source=3c454.3,225357.75,160853.6,2000.0,ccw 2006.201.20:36:15.14#flagr#flagr/antenna,new-source 2006.201.20:36:15.14:checkk5 2006.201.20:36:15.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:36:15.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:36:16.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:36:16.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:36:16.99/chk_obsdata//k5ts1/T2012034??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.20:36:17.36/chk_obsdata//k5ts2/T2012034??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.20:36:17.72/chk_obsdata//k5ts3/T2012034??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.20:36:18.09/chk_obsdata//k5ts4/T2012034??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.201.20:36:18.77/k5log//k5ts1_log_newline 2006.201.20:36:19.45/k5log//k5ts2_log_newline 2006.201.20:36:20.14/k5log//k5ts3_log_newline 2006.201.20:36:20.83/k5log//k5ts4_log_newline 2006.201.20:36:20.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:36:20.85:setupk4=1 2006.201.20:36:20.85$setupk4/echo=on 2006.201.20:36:20.85$setupk4/pcalon 2006.201.20:36:20.85$pcalon/"no phase cal control is implemented here 2006.201.20:36:20.85$setupk4/"tpicd=stop 2006.201.20:36:20.85$setupk4/"rec=synch_on 2006.201.20:36:20.85$setupk4/"rec_mode=128 2006.201.20:36:20.85$setupk4/!* 2006.201.20:36:20.85$setupk4/recpk4 2006.201.20:36:20.85$recpk4/recpatch= 2006.201.20:36:20.86$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:36:20.86$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:36:20.86$setupk4/vck44 2006.201.20:36:20.86$vck44/valo=1,524.99 2006.201.20:36:20.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.20:36:20.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.20:36:20.86#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:20.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:20.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:20.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:20.86#ibcon#enter wrdev, iclass 21, count 0 2006.201.20:36:20.86#ibcon#first serial, iclass 21, count 0 2006.201.20:36:20.86#ibcon#enter sib2, iclass 21, count 0 2006.201.20:36:20.86#ibcon#flushed, iclass 21, count 0 2006.201.20:36:20.86#ibcon#about to write, iclass 21, count 0 2006.201.20:36:20.86#ibcon#wrote, iclass 21, count 0 2006.201.20:36:20.86#ibcon#about to read 3, iclass 21, count 0 2006.201.20:36:20.89#ibcon#read 3, iclass 21, count 0 2006.201.20:36:20.89#ibcon#about to read 4, iclass 21, count 0 2006.201.20:36:20.89#ibcon#read 4, iclass 21, count 0 2006.201.20:36:20.89#ibcon#about to read 5, iclass 21, count 0 2006.201.20:36:20.89#ibcon#read 5, iclass 21, count 0 2006.201.20:36:20.89#ibcon#about to read 6, iclass 21, count 0 2006.201.20:36:20.89#ibcon#read 6, iclass 21, count 0 2006.201.20:36:20.89#ibcon#end of sib2, iclass 21, count 0 2006.201.20:36:20.89#ibcon#*mode == 0, iclass 21, count 0 2006.201.20:36:20.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.20:36:20.89#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:36:20.89#ibcon#*before write, iclass 21, count 0 2006.201.20:36:20.89#ibcon#enter sib2, iclass 21, count 0 2006.201.20:36:20.89#ibcon#flushed, iclass 21, count 0 2006.201.20:36:20.89#ibcon#about to write, iclass 21, count 0 2006.201.20:36:20.89#ibcon#wrote, iclass 21, count 0 2006.201.20:36:20.89#ibcon#about to read 3, iclass 21, count 0 2006.201.20:36:20.94#ibcon#read 3, iclass 21, count 0 2006.201.20:36:20.94#ibcon#about to read 4, iclass 21, count 0 2006.201.20:36:20.94#ibcon#read 4, iclass 21, count 0 2006.201.20:36:20.94#ibcon#about to read 5, iclass 21, count 0 2006.201.20:36:20.94#ibcon#read 5, iclass 21, count 0 2006.201.20:36:20.94#ibcon#about to read 6, iclass 21, count 0 2006.201.20:36:20.94#ibcon#read 6, iclass 21, count 0 2006.201.20:36:20.94#ibcon#end of sib2, iclass 21, count 0 2006.201.20:36:20.94#ibcon#*after write, iclass 21, count 0 2006.201.20:36:20.94#ibcon#*before return 0, iclass 21, count 0 2006.201.20:36:20.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:20.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:20.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.20:36:20.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.20:36:20.94$vck44/va=1,8 2006.201.20:36:20.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.20:36:20.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.20:36:20.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:20.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:20.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:20.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:20.94#ibcon#enter wrdev, iclass 23, count 2 2006.201.20:36:20.94#ibcon#first serial, iclass 23, count 2 2006.201.20:36:20.94#ibcon#enter sib2, iclass 23, count 2 2006.201.20:36:20.94#ibcon#flushed, iclass 23, count 2 2006.201.20:36:20.94#ibcon#about to write, iclass 23, count 2 2006.201.20:36:20.94#ibcon#wrote, iclass 23, count 2 2006.201.20:36:20.94#ibcon#about to read 3, iclass 23, count 2 2006.201.20:36:20.96#ibcon#read 3, iclass 23, count 2 2006.201.20:36:20.96#ibcon#about to read 4, iclass 23, count 2 2006.201.20:36:20.96#ibcon#read 4, iclass 23, count 2 2006.201.20:36:20.96#ibcon#about to read 5, iclass 23, count 2 2006.201.20:36:20.96#ibcon#read 5, iclass 23, count 2 2006.201.20:36:20.96#ibcon#about to read 6, iclass 23, count 2 2006.201.20:36:20.96#ibcon#read 6, iclass 23, count 2 2006.201.20:36:20.96#ibcon#end of sib2, iclass 23, count 2 2006.201.20:36:20.96#ibcon#*mode == 0, iclass 23, count 2 2006.201.20:36:20.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.20:36:20.96#ibcon#[25=AT01-08\r\n] 2006.201.20:36:20.96#ibcon#*before write, iclass 23, count 2 2006.201.20:36:20.96#ibcon#enter sib2, iclass 23, count 2 2006.201.20:36:20.96#ibcon#flushed, iclass 23, count 2 2006.201.20:36:20.96#ibcon#about to write, iclass 23, count 2 2006.201.20:36:20.96#ibcon#wrote, iclass 23, count 2 2006.201.20:36:20.96#ibcon#about to read 3, iclass 23, count 2 2006.201.20:36:20.99#ibcon#read 3, iclass 23, count 2 2006.201.20:36:20.99#ibcon#about to read 4, iclass 23, count 2 2006.201.20:36:20.99#ibcon#read 4, iclass 23, count 2 2006.201.20:36:20.99#ibcon#about to read 5, iclass 23, count 2 2006.201.20:36:20.99#ibcon#read 5, iclass 23, count 2 2006.201.20:36:20.99#ibcon#about to read 6, iclass 23, count 2 2006.201.20:36:20.99#ibcon#read 6, iclass 23, count 2 2006.201.20:36:20.99#ibcon#end of sib2, iclass 23, count 2 2006.201.20:36:20.99#ibcon#*after write, iclass 23, count 2 2006.201.20:36:20.99#ibcon#*before return 0, iclass 23, count 2 2006.201.20:36:20.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:20.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:20.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.20:36:20.99#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:20.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:21.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:21.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:21.11#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:36:21.11#ibcon#first serial, iclass 23, count 0 2006.201.20:36:21.11#ibcon#enter sib2, iclass 23, count 0 2006.201.20:36:21.11#ibcon#flushed, iclass 23, count 0 2006.201.20:36:21.11#ibcon#about to write, iclass 23, count 0 2006.201.20:36:21.11#ibcon#wrote, iclass 23, count 0 2006.201.20:36:21.11#ibcon#about to read 3, iclass 23, count 0 2006.201.20:36:21.13#ibcon#read 3, iclass 23, count 0 2006.201.20:36:21.13#ibcon#about to read 4, iclass 23, count 0 2006.201.20:36:21.13#ibcon#read 4, iclass 23, count 0 2006.201.20:36:21.13#ibcon#about to read 5, iclass 23, count 0 2006.201.20:36:21.13#ibcon#read 5, iclass 23, count 0 2006.201.20:36:21.13#ibcon#about to read 6, iclass 23, count 0 2006.201.20:36:21.13#ibcon#read 6, iclass 23, count 0 2006.201.20:36:21.13#ibcon#end of sib2, iclass 23, count 0 2006.201.20:36:21.13#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:36:21.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:36:21.13#ibcon#[25=USB\r\n] 2006.201.20:36:21.13#ibcon#*before write, iclass 23, count 0 2006.201.20:36:21.13#ibcon#enter sib2, iclass 23, count 0 2006.201.20:36:21.13#ibcon#flushed, iclass 23, count 0 2006.201.20:36:21.13#ibcon#about to write, iclass 23, count 0 2006.201.20:36:21.13#ibcon#wrote, iclass 23, count 0 2006.201.20:36:21.13#ibcon#about to read 3, iclass 23, count 0 2006.201.20:36:21.16#ibcon#read 3, iclass 23, count 0 2006.201.20:36:21.16#ibcon#about to read 4, iclass 23, count 0 2006.201.20:36:21.16#ibcon#read 4, iclass 23, count 0 2006.201.20:36:21.16#ibcon#about to read 5, iclass 23, count 0 2006.201.20:36:21.16#ibcon#read 5, iclass 23, count 0 2006.201.20:36:21.16#ibcon#about to read 6, iclass 23, count 0 2006.201.20:36:21.16#ibcon#read 6, iclass 23, count 0 2006.201.20:36:21.16#ibcon#end of sib2, iclass 23, count 0 2006.201.20:36:21.16#ibcon#*after write, iclass 23, count 0 2006.201.20:36:21.16#ibcon#*before return 0, iclass 23, count 0 2006.201.20:36:21.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:21.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:21.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:36:21.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:36:21.16$vck44/valo=2,534.99 2006.201.20:36:21.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.20:36:21.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.20:36:21.16#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:21.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:21.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:21.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:21.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.20:36:21.16#ibcon#first serial, iclass 25, count 0 2006.201.20:36:21.16#ibcon#enter sib2, iclass 25, count 0 2006.201.20:36:21.16#ibcon#flushed, iclass 25, count 0 2006.201.20:36:21.16#ibcon#about to write, iclass 25, count 0 2006.201.20:36:21.16#ibcon#wrote, iclass 25, count 0 2006.201.20:36:21.16#ibcon#about to read 3, iclass 25, count 0 2006.201.20:36:21.18#ibcon#read 3, iclass 25, count 0 2006.201.20:36:21.18#ibcon#about to read 4, iclass 25, count 0 2006.201.20:36:21.18#ibcon#read 4, iclass 25, count 0 2006.201.20:36:21.18#ibcon#about to read 5, iclass 25, count 0 2006.201.20:36:21.18#ibcon#read 5, iclass 25, count 0 2006.201.20:36:21.18#ibcon#about to read 6, iclass 25, count 0 2006.201.20:36:21.18#ibcon#read 6, iclass 25, count 0 2006.201.20:36:21.18#ibcon#end of sib2, iclass 25, count 0 2006.201.20:36:21.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.20:36:21.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.20:36:21.18#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:36:21.18#ibcon#*before write, iclass 25, count 0 2006.201.20:36:21.18#ibcon#enter sib2, iclass 25, count 0 2006.201.20:36:21.18#ibcon#flushed, iclass 25, count 0 2006.201.20:36:21.18#ibcon#about to write, iclass 25, count 0 2006.201.20:36:21.18#ibcon#wrote, iclass 25, count 0 2006.201.20:36:21.18#ibcon#about to read 3, iclass 25, count 0 2006.201.20:36:21.22#ibcon#read 3, iclass 25, count 0 2006.201.20:36:21.22#ibcon#about to read 4, iclass 25, count 0 2006.201.20:36:21.22#ibcon#read 4, iclass 25, count 0 2006.201.20:36:21.22#ibcon#about to read 5, iclass 25, count 0 2006.201.20:36:21.22#ibcon#read 5, iclass 25, count 0 2006.201.20:36:21.22#ibcon#about to read 6, iclass 25, count 0 2006.201.20:36:21.22#ibcon#read 6, iclass 25, count 0 2006.201.20:36:21.22#ibcon#end of sib2, iclass 25, count 0 2006.201.20:36:21.22#ibcon#*after write, iclass 25, count 0 2006.201.20:36:21.22#ibcon#*before return 0, iclass 25, count 0 2006.201.20:36:21.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:21.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:21.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.20:36:21.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.20:36:21.22$vck44/va=2,7 2006.201.20:36:21.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.20:36:21.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.20:36:21.22#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:21.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:21.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:21.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:21.28#ibcon#enter wrdev, iclass 27, count 2 2006.201.20:36:21.28#ibcon#first serial, iclass 27, count 2 2006.201.20:36:21.28#ibcon#enter sib2, iclass 27, count 2 2006.201.20:36:21.28#ibcon#flushed, iclass 27, count 2 2006.201.20:36:21.28#ibcon#about to write, iclass 27, count 2 2006.201.20:36:21.28#ibcon#wrote, iclass 27, count 2 2006.201.20:36:21.28#ibcon#about to read 3, iclass 27, count 2 2006.201.20:36:21.30#ibcon#read 3, iclass 27, count 2 2006.201.20:36:21.30#ibcon#about to read 4, iclass 27, count 2 2006.201.20:36:21.30#ibcon#read 4, iclass 27, count 2 2006.201.20:36:21.30#ibcon#about to read 5, iclass 27, count 2 2006.201.20:36:21.30#ibcon#read 5, iclass 27, count 2 2006.201.20:36:21.30#ibcon#about to read 6, iclass 27, count 2 2006.201.20:36:21.30#ibcon#read 6, iclass 27, count 2 2006.201.20:36:21.30#ibcon#end of sib2, iclass 27, count 2 2006.201.20:36:21.30#ibcon#*mode == 0, iclass 27, count 2 2006.201.20:36:21.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.20:36:21.30#ibcon#[25=AT02-07\r\n] 2006.201.20:36:21.30#ibcon#*before write, iclass 27, count 2 2006.201.20:36:21.30#ibcon#enter sib2, iclass 27, count 2 2006.201.20:36:21.30#ibcon#flushed, iclass 27, count 2 2006.201.20:36:21.30#ibcon#about to write, iclass 27, count 2 2006.201.20:36:21.30#ibcon#wrote, iclass 27, count 2 2006.201.20:36:21.30#ibcon#about to read 3, iclass 27, count 2 2006.201.20:36:21.33#ibcon#read 3, iclass 27, count 2 2006.201.20:36:21.33#ibcon#about to read 4, iclass 27, count 2 2006.201.20:36:21.33#ibcon#read 4, iclass 27, count 2 2006.201.20:36:21.33#ibcon#about to read 5, iclass 27, count 2 2006.201.20:36:21.33#ibcon#read 5, iclass 27, count 2 2006.201.20:36:21.33#ibcon#about to read 6, iclass 27, count 2 2006.201.20:36:21.33#ibcon#read 6, iclass 27, count 2 2006.201.20:36:21.33#ibcon#end of sib2, iclass 27, count 2 2006.201.20:36:21.33#ibcon#*after write, iclass 27, count 2 2006.201.20:36:21.33#ibcon#*before return 0, iclass 27, count 2 2006.201.20:36:21.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:21.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:21.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.20:36:21.33#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:21.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:21.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:21.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:21.45#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:36:21.45#ibcon#first serial, iclass 27, count 0 2006.201.20:36:21.45#ibcon#enter sib2, iclass 27, count 0 2006.201.20:36:21.45#ibcon#flushed, iclass 27, count 0 2006.201.20:36:21.45#ibcon#about to write, iclass 27, count 0 2006.201.20:36:21.45#ibcon#wrote, iclass 27, count 0 2006.201.20:36:21.45#ibcon#about to read 3, iclass 27, count 0 2006.201.20:36:21.47#ibcon#read 3, iclass 27, count 0 2006.201.20:36:21.47#ibcon#about to read 4, iclass 27, count 0 2006.201.20:36:21.47#ibcon#read 4, iclass 27, count 0 2006.201.20:36:21.47#ibcon#about to read 5, iclass 27, count 0 2006.201.20:36:21.47#ibcon#read 5, iclass 27, count 0 2006.201.20:36:21.47#ibcon#about to read 6, iclass 27, count 0 2006.201.20:36:21.47#ibcon#read 6, iclass 27, count 0 2006.201.20:36:21.47#ibcon#end of sib2, iclass 27, count 0 2006.201.20:36:21.47#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:36:21.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:36:21.47#ibcon#[25=USB\r\n] 2006.201.20:36:21.47#ibcon#*before write, iclass 27, count 0 2006.201.20:36:21.47#ibcon#enter sib2, iclass 27, count 0 2006.201.20:36:21.47#ibcon#flushed, iclass 27, count 0 2006.201.20:36:21.47#ibcon#about to write, iclass 27, count 0 2006.201.20:36:21.47#ibcon#wrote, iclass 27, count 0 2006.201.20:36:21.47#ibcon#about to read 3, iclass 27, count 0 2006.201.20:36:21.50#ibcon#read 3, iclass 27, count 0 2006.201.20:36:21.50#ibcon#about to read 4, iclass 27, count 0 2006.201.20:36:21.50#ibcon#read 4, iclass 27, count 0 2006.201.20:36:21.50#ibcon#about to read 5, iclass 27, count 0 2006.201.20:36:21.50#ibcon#read 5, iclass 27, count 0 2006.201.20:36:21.50#ibcon#about to read 6, iclass 27, count 0 2006.201.20:36:21.50#ibcon#read 6, iclass 27, count 0 2006.201.20:36:21.50#ibcon#end of sib2, iclass 27, count 0 2006.201.20:36:21.50#ibcon#*after write, iclass 27, count 0 2006.201.20:36:21.50#ibcon#*before return 0, iclass 27, count 0 2006.201.20:36:21.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:21.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:21.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:36:21.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:36:21.50$vck44/valo=3,564.99 2006.201.20:36:21.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.20:36:21.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.20:36:21.50#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:21.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:21.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:21.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:21.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.20:36:21.50#ibcon#first serial, iclass 29, count 0 2006.201.20:36:21.50#ibcon#enter sib2, iclass 29, count 0 2006.201.20:36:21.50#ibcon#flushed, iclass 29, count 0 2006.201.20:36:21.50#ibcon#about to write, iclass 29, count 0 2006.201.20:36:21.50#ibcon#wrote, iclass 29, count 0 2006.201.20:36:21.50#ibcon#about to read 3, iclass 29, count 0 2006.201.20:36:21.52#ibcon#read 3, iclass 29, count 0 2006.201.20:36:21.52#ibcon#about to read 4, iclass 29, count 0 2006.201.20:36:21.52#ibcon#read 4, iclass 29, count 0 2006.201.20:36:21.52#ibcon#about to read 5, iclass 29, count 0 2006.201.20:36:21.52#ibcon#read 5, iclass 29, count 0 2006.201.20:36:21.52#ibcon#about to read 6, iclass 29, count 0 2006.201.20:36:21.52#ibcon#read 6, iclass 29, count 0 2006.201.20:36:21.52#ibcon#end of sib2, iclass 29, count 0 2006.201.20:36:21.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.20:36:21.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.20:36:21.52#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:36:21.52#ibcon#*before write, iclass 29, count 0 2006.201.20:36:21.52#ibcon#enter sib2, iclass 29, count 0 2006.201.20:36:21.52#ibcon#flushed, iclass 29, count 0 2006.201.20:36:21.52#ibcon#about to write, iclass 29, count 0 2006.201.20:36:21.52#ibcon#wrote, iclass 29, count 0 2006.201.20:36:21.52#ibcon#about to read 3, iclass 29, count 0 2006.201.20:36:21.57#ibcon#read 3, iclass 29, count 0 2006.201.20:36:21.57#ibcon#about to read 4, iclass 29, count 0 2006.201.20:36:21.57#ibcon#read 4, iclass 29, count 0 2006.201.20:36:21.57#ibcon#about to read 5, iclass 29, count 0 2006.201.20:36:21.57#ibcon#read 5, iclass 29, count 0 2006.201.20:36:21.57#ibcon#about to read 6, iclass 29, count 0 2006.201.20:36:21.57#ibcon#read 6, iclass 29, count 0 2006.201.20:36:21.57#ibcon#end of sib2, iclass 29, count 0 2006.201.20:36:21.57#ibcon#*after write, iclass 29, count 0 2006.201.20:36:21.57#ibcon#*before return 0, iclass 29, count 0 2006.201.20:36:21.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:21.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:21.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.20:36:21.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.20:36:21.57$vck44/va=3,8 2006.201.20:36:21.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.20:36:21.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.20:36:21.57#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:21.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:21.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:21.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:21.62#ibcon#enter wrdev, iclass 31, count 2 2006.201.20:36:21.62#ibcon#first serial, iclass 31, count 2 2006.201.20:36:21.62#ibcon#enter sib2, iclass 31, count 2 2006.201.20:36:21.62#ibcon#flushed, iclass 31, count 2 2006.201.20:36:21.62#ibcon#about to write, iclass 31, count 2 2006.201.20:36:21.62#ibcon#wrote, iclass 31, count 2 2006.201.20:36:21.62#ibcon#about to read 3, iclass 31, count 2 2006.201.20:36:21.64#ibcon#read 3, iclass 31, count 2 2006.201.20:36:21.64#ibcon#about to read 4, iclass 31, count 2 2006.201.20:36:21.64#ibcon#read 4, iclass 31, count 2 2006.201.20:36:21.64#ibcon#about to read 5, iclass 31, count 2 2006.201.20:36:21.64#ibcon#read 5, iclass 31, count 2 2006.201.20:36:21.64#ibcon#about to read 6, iclass 31, count 2 2006.201.20:36:21.64#ibcon#read 6, iclass 31, count 2 2006.201.20:36:21.64#ibcon#end of sib2, iclass 31, count 2 2006.201.20:36:21.64#ibcon#*mode == 0, iclass 31, count 2 2006.201.20:36:21.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.20:36:21.64#ibcon#[25=AT03-08\r\n] 2006.201.20:36:21.64#ibcon#*before write, iclass 31, count 2 2006.201.20:36:21.64#ibcon#enter sib2, iclass 31, count 2 2006.201.20:36:21.64#ibcon#flushed, iclass 31, count 2 2006.201.20:36:21.64#ibcon#about to write, iclass 31, count 2 2006.201.20:36:21.64#ibcon#wrote, iclass 31, count 2 2006.201.20:36:21.64#ibcon#about to read 3, iclass 31, count 2 2006.201.20:36:21.67#ibcon#read 3, iclass 31, count 2 2006.201.20:36:21.67#ibcon#about to read 4, iclass 31, count 2 2006.201.20:36:21.67#ibcon#read 4, iclass 31, count 2 2006.201.20:36:21.67#ibcon#about to read 5, iclass 31, count 2 2006.201.20:36:21.67#ibcon#read 5, iclass 31, count 2 2006.201.20:36:21.67#ibcon#about to read 6, iclass 31, count 2 2006.201.20:36:21.67#ibcon#read 6, iclass 31, count 2 2006.201.20:36:21.67#ibcon#end of sib2, iclass 31, count 2 2006.201.20:36:21.67#ibcon#*after write, iclass 31, count 2 2006.201.20:36:21.67#ibcon#*before return 0, iclass 31, count 2 2006.201.20:36:21.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:21.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:21.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.20:36:21.67#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:21.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:21.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:21.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:21.79#ibcon#enter wrdev, iclass 31, count 0 2006.201.20:36:21.79#ibcon#first serial, iclass 31, count 0 2006.201.20:36:21.79#ibcon#enter sib2, iclass 31, count 0 2006.201.20:36:21.79#ibcon#flushed, iclass 31, count 0 2006.201.20:36:21.79#ibcon#about to write, iclass 31, count 0 2006.201.20:36:21.79#ibcon#wrote, iclass 31, count 0 2006.201.20:36:21.79#ibcon#about to read 3, iclass 31, count 0 2006.201.20:36:21.81#ibcon#read 3, iclass 31, count 0 2006.201.20:36:21.81#ibcon#about to read 4, iclass 31, count 0 2006.201.20:36:21.81#ibcon#read 4, iclass 31, count 0 2006.201.20:36:21.81#ibcon#about to read 5, iclass 31, count 0 2006.201.20:36:21.81#ibcon#read 5, iclass 31, count 0 2006.201.20:36:21.81#ibcon#about to read 6, iclass 31, count 0 2006.201.20:36:21.81#ibcon#read 6, iclass 31, count 0 2006.201.20:36:21.81#ibcon#end of sib2, iclass 31, count 0 2006.201.20:36:21.81#ibcon#*mode == 0, iclass 31, count 0 2006.201.20:36:21.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.20:36:21.81#ibcon#[25=USB\r\n] 2006.201.20:36:21.81#ibcon#*before write, iclass 31, count 0 2006.201.20:36:21.81#ibcon#enter sib2, iclass 31, count 0 2006.201.20:36:21.81#ibcon#flushed, iclass 31, count 0 2006.201.20:36:21.81#ibcon#about to write, iclass 31, count 0 2006.201.20:36:21.81#ibcon#wrote, iclass 31, count 0 2006.201.20:36:21.81#ibcon#about to read 3, iclass 31, count 0 2006.201.20:36:21.84#ibcon#read 3, iclass 31, count 0 2006.201.20:36:21.84#ibcon#about to read 4, iclass 31, count 0 2006.201.20:36:21.84#ibcon#read 4, iclass 31, count 0 2006.201.20:36:21.84#ibcon#about to read 5, iclass 31, count 0 2006.201.20:36:21.84#ibcon#read 5, iclass 31, count 0 2006.201.20:36:21.84#ibcon#about to read 6, iclass 31, count 0 2006.201.20:36:21.84#ibcon#read 6, iclass 31, count 0 2006.201.20:36:21.84#ibcon#end of sib2, iclass 31, count 0 2006.201.20:36:21.84#ibcon#*after write, iclass 31, count 0 2006.201.20:36:21.84#ibcon#*before return 0, iclass 31, count 0 2006.201.20:36:21.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:21.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:21.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.20:36:21.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.20:36:21.84$vck44/valo=4,624.99 2006.201.20:36:21.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.20:36:21.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.20:36:21.84#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:21.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:21.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:21.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:21.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.20:36:21.84#ibcon#first serial, iclass 33, count 0 2006.201.20:36:21.84#ibcon#enter sib2, iclass 33, count 0 2006.201.20:36:21.84#ibcon#flushed, iclass 33, count 0 2006.201.20:36:21.84#ibcon#about to write, iclass 33, count 0 2006.201.20:36:21.84#ibcon#wrote, iclass 33, count 0 2006.201.20:36:21.84#ibcon#about to read 3, iclass 33, count 0 2006.201.20:36:21.86#ibcon#read 3, iclass 33, count 0 2006.201.20:36:21.86#ibcon#about to read 4, iclass 33, count 0 2006.201.20:36:21.86#ibcon#read 4, iclass 33, count 0 2006.201.20:36:21.86#ibcon#about to read 5, iclass 33, count 0 2006.201.20:36:21.86#ibcon#read 5, iclass 33, count 0 2006.201.20:36:21.86#ibcon#about to read 6, iclass 33, count 0 2006.201.20:36:21.86#ibcon#read 6, iclass 33, count 0 2006.201.20:36:21.86#ibcon#end of sib2, iclass 33, count 0 2006.201.20:36:21.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.20:36:21.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.20:36:21.86#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:36:21.86#ibcon#*before write, iclass 33, count 0 2006.201.20:36:21.86#ibcon#enter sib2, iclass 33, count 0 2006.201.20:36:21.86#ibcon#flushed, iclass 33, count 0 2006.201.20:36:21.86#ibcon#about to write, iclass 33, count 0 2006.201.20:36:21.86#ibcon#wrote, iclass 33, count 0 2006.201.20:36:21.86#ibcon#about to read 3, iclass 33, count 0 2006.201.20:36:21.90#ibcon#read 3, iclass 33, count 0 2006.201.20:36:21.90#ibcon#about to read 4, iclass 33, count 0 2006.201.20:36:21.90#ibcon#read 4, iclass 33, count 0 2006.201.20:36:21.90#ibcon#about to read 5, iclass 33, count 0 2006.201.20:36:21.90#ibcon#read 5, iclass 33, count 0 2006.201.20:36:21.90#ibcon#about to read 6, iclass 33, count 0 2006.201.20:36:21.90#ibcon#read 6, iclass 33, count 0 2006.201.20:36:21.90#ibcon#end of sib2, iclass 33, count 0 2006.201.20:36:21.90#ibcon#*after write, iclass 33, count 0 2006.201.20:36:21.90#ibcon#*before return 0, iclass 33, count 0 2006.201.20:36:21.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:21.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:21.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.20:36:21.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.20:36:21.90$vck44/va=4,7 2006.201.20:36:21.90#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.20:36:21.90#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.20:36:21.90#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:21.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:21.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:21.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:21.96#ibcon#enter wrdev, iclass 35, count 2 2006.201.20:36:21.96#ibcon#first serial, iclass 35, count 2 2006.201.20:36:21.96#ibcon#enter sib2, iclass 35, count 2 2006.201.20:36:21.96#ibcon#flushed, iclass 35, count 2 2006.201.20:36:21.96#ibcon#about to write, iclass 35, count 2 2006.201.20:36:21.96#ibcon#wrote, iclass 35, count 2 2006.201.20:36:21.96#ibcon#about to read 3, iclass 35, count 2 2006.201.20:36:21.98#ibcon#read 3, iclass 35, count 2 2006.201.20:36:21.98#ibcon#about to read 4, iclass 35, count 2 2006.201.20:36:21.98#ibcon#read 4, iclass 35, count 2 2006.201.20:36:21.98#ibcon#about to read 5, iclass 35, count 2 2006.201.20:36:21.98#ibcon#read 5, iclass 35, count 2 2006.201.20:36:21.98#ibcon#about to read 6, iclass 35, count 2 2006.201.20:36:21.98#ibcon#read 6, iclass 35, count 2 2006.201.20:36:21.98#ibcon#end of sib2, iclass 35, count 2 2006.201.20:36:21.98#ibcon#*mode == 0, iclass 35, count 2 2006.201.20:36:21.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.20:36:21.98#ibcon#[25=AT04-07\r\n] 2006.201.20:36:21.98#ibcon#*before write, iclass 35, count 2 2006.201.20:36:21.98#ibcon#enter sib2, iclass 35, count 2 2006.201.20:36:21.98#ibcon#flushed, iclass 35, count 2 2006.201.20:36:21.98#ibcon#about to write, iclass 35, count 2 2006.201.20:36:21.98#ibcon#wrote, iclass 35, count 2 2006.201.20:36:21.98#ibcon#about to read 3, iclass 35, count 2 2006.201.20:36:22.01#ibcon#read 3, iclass 35, count 2 2006.201.20:36:22.01#ibcon#about to read 4, iclass 35, count 2 2006.201.20:36:22.01#ibcon#read 4, iclass 35, count 2 2006.201.20:36:22.01#ibcon#about to read 5, iclass 35, count 2 2006.201.20:36:22.01#ibcon#read 5, iclass 35, count 2 2006.201.20:36:22.01#ibcon#about to read 6, iclass 35, count 2 2006.201.20:36:22.01#ibcon#read 6, iclass 35, count 2 2006.201.20:36:22.01#ibcon#end of sib2, iclass 35, count 2 2006.201.20:36:22.01#ibcon#*after write, iclass 35, count 2 2006.201.20:36:22.01#ibcon#*before return 0, iclass 35, count 2 2006.201.20:36:22.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:22.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:22.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.20:36:22.01#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:22.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:22.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:22.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:22.13#ibcon#enter wrdev, iclass 35, count 0 2006.201.20:36:22.13#ibcon#first serial, iclass 35, count 0 2006.201.20:36:22.13#ibcon#enter sib2, iclass 35, count 0 2006.201.20:36:22.13#ibcon#flushed, iclass 35, count 0 2006.201.20:36:22.13#ibcon#about to write, iclass 35, count 0 2006.201.20:36:22.13#ibcon#wrote, iclass 35, count 0 2006.201.20:36:22.13#ibcon#about to read 3, iclass 35, count 0 2006.201.20:36:22.15#ibcon#read 3, iclass 35, count 0 2006.201.20:36:22.15#ibcon#about to read 4, iclass 35, count 0 2006.201.20:36:22.15#ibcon#read 4, iclass 35, count 0 2006.201.20:36:22.15#ibcon#about to read 5, iclass 35, count 0 2006.201.20:36:22.15#ibcon#read 5, iclass 35, count 0 2006.201.20:36:22.15#ibcon#about to read 6, iclass 35, count 0 2006.201.20:36:22.15#ibcon#read 6, iclass 35, count 0 2006.201.20:36:22.15#ibcon#end of sib2, iclass 35, count 0 2006.201.20:36:22.15#ibcon#*mode == 0, iclass 35, count 0 2006.201.20:36:22.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.20:36:22.15#ibcon#[25=USB\r\n] 2006.201.20:36:22.15#ibcon#*before write, iclass 35, count 0 2006.201.20:36:22.15#ibcon#enter sib2, iclass 35, count 0 2006.201.20:36:22.15#ibcon#flushed, iclass 35, count 0 2006.201.20:36:22.15#ibcon#about to write, iclass 35, count 0 2006.201.20:36:22.15#ibcon#wrote, iclass 35, count 0 2006.201.20:36:22.15#ibcon#about to read 3, iclass 35, count 0 2006.201.20:36:22.18#ibcon#read 3, iclass 35, count 0 2006.201.20:36:22.18#ibcon#about to read 4, iclass 35, count 0 2006.201.20:36:22.18#ibcon#read 4, iclass 35, count 0 2006.201.20:36:22.18#ibcon#about to read 5, iclass 35, count 0 2006.201.20:36:22.18#ibcon#read 5, iclass 35, count 0 2006.201.20:36:22.18#ibcon#about to read 6, iclass 35, count 0 2006.201.20:36:22.18#ibcon#read 6, iclass 35, count 0 2006.201.20:36:22.18#ibcon#end of sib2, iclass 35, count 0 2006.201.20:36:22.18#ibcon#*after write, iclass 35, count 0 2006.201.20:36:22.18#ibcon#*before return 0, iclass 35, count 0 2006.201.20:36:22.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:22.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:22.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.20:36:22.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.20:36:22.18$vck44/valo=5,734.99 2006.201.20:36:22.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.20:36:22.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.20:36:22.18#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:22.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:22.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:22.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:22.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.20:36:22.18#ibcon#first serial, iclass 37, count 0 2006.201.20:36:22.18#ibcon#enter sib2, iclass 37, count 0 2006.201.20:36:22.18#ibcon#flushed, iclass 37, count 0 2006.201.20:36:22.18#ibcon#about to write, iclass 37, count 0 2006.201.20:36:22.18#ibcon#wrote, iclass 37, count 0 2006.201.20:36:22.18#ibcon#about to read 3, iclass 37, count 0 2006.201.20:36:22.20#ibcon#read 3, iclass 37, count 0 2006.201.20:36:22.20#ibcon#about to read 4, iclass 37, count 0 2006.201.20:36:22.20#ibcon#read 4, iclass 37, count 0 2006.201.20:36:22.20#ibcon#about to read 5, iclass 37, count 0 2006.201.20:36:22.20#ibcon#read 5, iclass 37, count 0 2006.201.20:36:22.20#ibcon#about to read 6, iclass 37, count 0 2006.201.20:36:22.20#ibcon#read 6, iclass 37, count 0 2006.201.20:36:22.20#ibcon#end of sib2, iclass 37, count 0 2006.201.20:36:22.20#ibcon#*mode == 0, iclass 37, count 0 2006.201.20:36:22.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.20:36:22.20#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:36:22.20#ibcon#*before write, iclass 37, count 0 2006.201.20:36:22.20#ibcon#enter sib2, iclass 37, count 0 2006.201.20:36:22.20#ibcon#flushed, iclass 37, count 0 2006.201.20:36:22.20#ibcon#about to write, iclass 37, count 0 2006.201.20:36:22.20#ibcon#wrote, iclass 37, count 0 2006.201.20:36:22.20#ibcon#about to read 3, iclass 37, count 0 2006.201.20:36:22.24#ibcon#read 3, iclass 37, count 0 2006.201.20:36:22.24#ibcon#about to read 4, iclass 37, count 0 2006.201.20:36:22.24#ibcon#read 4, iclass 37, count 0 2006.201.20:36:22.24#ibcon#about to read 5, iclass 37, count 0 2006.201.20:36:22.24#ibcon#read 5, iclass 37, count 0 2006.201.20:36:22.24#ibcon#about to read 6, iclass 37, count 0 2006.201.20:36:22.24#ibcon#read 6, iclass 37, count 0 2006.201.20:36:22.24#ibcon#end of sib2, iclass 37, count 0 2006.201.20:36:22.24#ibcon#*after write, iclass 37, count 0 2006.201.20:36:22.24#ibcon#*before return 0, iclass 37, count 0 2006.201.20:36:22.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:22.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:22.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.20:36:22.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.20:36:22.24$vck44/va=5,4 2006.201.20:36:22.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.20:36:22.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.20:36:22.24#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:22.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:22.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:22.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:22.30#ibcon#enter wrdev, iclass 39, count 2 2006.201.20:36:22.30#ibcon#first serial, iclass 39, count 2 2006.201.20:36:22.30#ibcon#enter sib2, iclass 39, count 2 2006.201.20:36:22.30#ibcon#flushed, iclass 39, count 2 2006.201.20:36:22.30#ibcon#about to write, iclass 39, count 2 2006.201.20:36:22.30#ibcon#wrote, iclass 39, count 2 2006.201.20:36:22.30#ibcon#about to read 3, iclass 39, count 2 2006.201.20:36:22.32#ibcon#read 3, iclass 39, count 2 2006.201.20:36:22.32#ibcon#about to read 4, iclass 39, count 2 2006.201.20:36:22.32#ibcon#read 4, iclass 39, count 2 2006.201.20:36:22.32#ibcon#about to read 5, iclass 39, count 2 2006.201.20:36:22.32#ibcon#read 5, iclass 39, count 2 2006.201.20:36:22.32#ibcon#about to read 6, iclass 39, count 2 2006.201.20:36:22.32#ibcon#read 6, iclass 39, count 2 2006.201.20:36:22.32#ibcon#end of sib2, iclass 39, count 2 2006.201.20:36:22.32#ibcon#*mode == 0, iclass 39, count 2 2006.201.20:36:22.32#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.20:36:22.32#ibcon#[25=AT05-04\r\n] 2006.201.20:36:22.32#ibcon#*before write, iclass 39, count 2 2006.201.20:36:22.32#ibcon#enter sib2, iclass 39, count 2 2006.201.20:36:22.32#ibcon#flushed, iclass 39, count 2 2006.201.20:36:22.32#ibcon#about to write, iclass 39, count 2 2006.201.20:36:22.32#ibcon#wrote, iclass 39, count 2 2006.201.20:36:22.32#ibcon#about to read 3, iclass 39, count 2 2006.201.20:36:22.35#ibcon#read 3, iclass 39, count 2 2006.201.20:36:22.35#ibcon#about to read 4, iclass 39, count 2 2006.201.20:36:22.35#ibcon#read 4, iclass 39, count 2 2006.201.20:36:22.35#ibcon#about to read 5, iclass 39, count 2 2006.201.20:36:22.35#ibcon#read 5, iclass 39, count 2 2006.201.20:36:22.35#ibcon#about to read 6, iclass 39, count 2 2006.201.20:36:22.35#ibcon#read 6, iclass 39, count 2 2006.201.20:36:22.35#ibcon#end of sib2, iclass 39, count 2 2006.201.20:36:22.35#ibcon#*after write, iclass 39, count 2 2006.201.20:36:22.35#ibcon#*before return 0, iclass 39, count 2 2006.201.20:36:22.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:22.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:22.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.20:36:22.35#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:22.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:22.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:22.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:22.47#ibcon#enter wrdev, iclass 39, count 0 2006.201.20:36:22.47#ibcon#first serial, iclass 39, count 0 2006.201.20:36:22.47#ibcon#enter sib2, iclass 39, count 0 2006.201.20:36:22.47#ibcon#flushed, iclass 39, count 0 2006.201.20:36:22.47#ibcon#about to write, iclass 39, count 0 2006.201.20:36:22.47#ibcon#wrote, iclass 39, count 0 2006.201.20:36:22.47#ibcon#about to read 3, iclass 39, count 0 2006.201.20:36:22.49#ibcon#read 3, iclass 39, count 0 2006.201.20:36:22.49#ibcon#about to read 4, iclass 39, count 0 2006.201.20:36:22.49#ibcon#read 4, iclass 39, count 0 2006.201.20:36:22.49#ibcon#about to read 5, iclass 39, count 0 2006.201.20:36:22.49#ibcon#read 5, iclass 39, count 0 2006.201.20:36:22.49#ibcon#about to read 6, iclass 39, count 0 2006.201.20:36:22.49#ibcon#read 6, iclass 39, count 0 2006.201.20:36:22.49#ibcon#end of sib2, iclass 39, count 0 2006.201.20:36:22.49#ibcon#*mode == 0, iclass 39, count 0 2006.201.20:36:22.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.20:36:22.49#ibcon#[25=USB\r\n] 2006.201.20:36:22.49#ibcon#*before write, iclass 39, count 0 2006.201.20:36:22.49#ibcon#enter sib2, iclass 39, count 0 2006.201.20:36:22.49#ibcon#flushed, iclass 39, count 0 2006.201.20:36:22.49#ibcon#about to write, iclass 39, count 0 2006.201.20:36:22.49#ibcon#wrote, iclass 39, count 0 2006.201.20:36:22.49#ibcon#about to read 3, iclass 39, count 0 2006.201.20:36:22.52#ibcon#read 3, iclass 39, count 0 2006.201.20:36:22.52#ibcon#about to read 4, iclass 39, count 0 2006.201.20:36:22.52#ibcon#read 4, iclass 39, count 0 2006.201.20:36:22.52#ibcon#about to read 5, iclass 39, count 0 2006.201.20:36:22.52#ibcon#read 5, iclass 39, count 0 2006.201.20:36:22.52#ibcon#about to read 6, iclass 39, count 0 2006.201.20:36:22.52#ibcon#read 6, iclass 39, count 0 2006.201.20:36:22.52#ibcon#end of sib2, iclass 39, count 0 2006.201.20:36:22.52#ibcon#*after write, iclass 39, count 0 2006.201.20:36:22.52#ibcon#*before return 0, iclass 39, count 0 2006.201.20:36:22.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:22.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:22.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.20:36:22.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.20:36:22.52$vck44/valo=6,814.99 2006.201.20:36:22.52#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.20:36:22.52#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.20:36:22.52#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:22.52#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:22.52#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:22.52#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:22.52#ibcon#enter wrdev, iclass 2, count 0 2006.201.20:36:22.52#ibcon#first serial, iclass 2, count 0 2006.201.20:36:22.52#ibcon#enter sib2, iclass 2, count 0 2006.201.20:36:22.52#ibcon#flushed, iclass 2, count 0 2006.201.20:36:22.52#ibcon#about to write, iclass 2, count 0 2006.201.20:36:22.52#ibcon#wrote, iclass 2, count 0 2006.201.20:36:22.52#ibcon#about to read 3, iclass 2, count 0 2006.201.20:36:22.54#ibcon#read 3, iclass 2, count 0 2006.201.20:36:22.54#ibcon#about to read 4, iclass 2, count 0 2006.201.20:36:22.54#ibcon#read 4, iclass 2, count 0 2006.201.20:36:22.54#ibcon#about to read 5, iclass 2, count 0 2006.201.20:36:22.54#ibcon#read 5, iclass 2, count 0 2006.201.20:36:22.54#ibcon#about to read 6, iclass 2, count 0 2006.201.20:36:22.54#ibcon#read 6, iclass 2, count 0 2006.201.20:36:22.54#ibcon#end of sib2, iclass 2, count 0 2006.201.20:36:22.54#ibcon#*mode == 0, iclass 2, count 0 2006.201.20:36:22.54#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.20:36:22.54#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:36:22.54#ibcon#*before write, iclass 2, count 0 2006.201.20:36:22.54#ibcon#enter sib2, iclass 2, count 0 2006.201.20:36:22.54#ibcon#flushed, iclass 2, count 0 2006.201.20:36:22.54#ibcon#about to write, iclass 2, count 0 2006.201.20:36:22.54#ibcon#wrote, iclass 2, count 0 2006.201.20:36:22.54#ibcon#about to read 3, iclass 2, count 0 2006.201.20:36:22.58#ibcon#read 3, iclass 2, count 0 2006.201.20:36:22.58#ibcon#about to read 4, iclass 2, count 0 2006.201.20:36:22.58#ibcon#read 4, iclass 2, count 0 2006.201.20:36:22.58#ibcon#about to read 5, iclass 2, count 0 2006.201.20:36:22.58#ibcon#read 5, iclass 2, count 0 2006.201.20:36:22.58#ibcon#about to read 6, iclass 2, count 0 2006.201.20:36:22.58#ibcon#read 6, iclass 2, count 0 2006.201.20:36:22.58#ibcon#end of sib2, iclass 2, count 0 2006.201.20:36:22.58#ibcon#*after write, iclass 2, count 0 2006.201.20:36:22.58#ibcon#*before return 0, iclass 2, count 0 2006.201.20:36:22.58#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:22.58#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:22.58#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.20:36:22.58#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.20:36:22.58$vck44/va=6,5 2006.201.20:36:22.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.20:36:22.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.20:36:22.58#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:22.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:22.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:22.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:22.64#ibcon#enter wrdev, iclass 5, count 2 2006.201.20:36:22.64#ibcon#first serial, iclass 5, count 2 2006.201.20:36:22.64#ibcon#enter sib2, iclass 5, count 2 2006.201.20:36:22.64#ibcon#flushed, iclass 5, count 2 2006.201.20:36:22.64#ibcon#about to write, iclass 5, count 2 2006.201.20:36:22.64#ibcon#wrote, iclass 5, count 2 2006.201.20:36:22.64#ibcon#about to read 3, iclass 5, count 2 2006.201.20:36:22.66#ibcon#read 3, iclass 5, count 2 2006.201.20:36:22.66#ibcon#about to read 4, iclass 5, count 2 2006.201.20:36:22.66#ibcon#read 4, iclass 5, count 2 2006.201.20:36:22.66#ibcon#about to read 5, iclass 5, count 2 2006.201.20:36:22.66#ibcon#read 5, iclass 5, count 2 2006.201.20:36:22.66#ibcon#about to read 6, iclass 5, count 2 2006.201.20:36:22.66#ibcon#read 6, iclass 5, count 2 2006.201.20:36:22.66#ibcon#end of sib2, iclass 5, count 2 2006.201.20:36:22.66#ibcon#*mode == 0, iclass 5, count 2 2006.201.20:36:22.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.20:36:22.66#ibcon#[25=AT06-05\r\n] 2006.201.20:36:22.66#ibcon#*before write, iclass 5, count 2 2006.201.20:36:22.66#ibcon#enter sib2, iclass 5, count 2 2006.201.20:36:22.66#ibcon#flushed, iclass 5, count 2 2006.201.20:36:22.66#ibcon#about to write, iclass 5, count 2 2006.201.20:36:22.66#ibcon#wrote, iclass 5, count 2 2006.201.20:36:22.66#ibcon#about to read 3, iclass 5, count 2 2006.201.20:36:22.69#ibcon#read 3, iclass 5, count 2 2006.201.20:36:22.69#ibcon#about to read 4, iclass 5, count 2 2006.201.20:36:22.69#ibcon#read 4, iclass 5, count 2 2006.201.20:36:22.69#ibcon#about to read 5, iclass 5, count 2 2006.201.20:36:22.69#ibcon#read 5, iclass 5, count 2 2006.201.20:36:22.69#ibcon#about to read 6, iclass 5, count 2 2006.201.20:36:22.69#ibcon#read 6, iclass 5, count 2 2006.201.20:36:22.69#ibcon#end of sib2, iclass 5, count 2 2006.201.20:36:22.69#ibcon#*after write, iclass 5, count 2 2006.201.20:36:22.69#ibcon#*before return 0, iclass 5, count 2 2006.201.20:36:22.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:22.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:22.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.20:36:22.69#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:22.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:22.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:22.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:22.81#ibcon#enter wrdev, iclass 5, count 0 2006.201.20:36:22.81#ibcon#first serial, iclass 5, count 0 2006.201.20:36:22.81#ibcon#enter sib2, iclass 5, count 0 2006.201.20:36:22.81#ibcon#flushed, iclass 5, count 0 2006.201.20:36:22.81#ibcon#about to write, iclass 5, count 0 2006.201.20:36:22.81#ibcon#wrote, iclass 5, count 0 2006.201.20:36:22.81#ibcon#about to read 3, iclass 5, count 0 2006.201.20:36:22.83#ibcon#read 3, iclass 5, count 0 2006.201.20:36:22.83#ibcon#about to read 4, iclass 5, count 0 2006.201.20:36:22.83#ibcon#read 4, iclass 5, count 0 2006.201.20:36:22.83#ibcon#about to read 5, iclass 5, count 0 2006.201.20:36:22.83#ibcon#read 5, iclass 5, count 0 2006.201.20:36:22.83#ibcon#about to read 6, iclass 5, count 0 2006.201.20:36:22.83#ibcon#read 6, iclass 5, count 0 2006.201.20:36:22.83#ibcon#end of sib2, iclass 5, count 0 2006.201.20:36:22.83#ibcon#*mode == 0, iclass 5, count 0 2006.201.20:36:22.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.20:36:22.83#ibcon#[25=USB\r\n] 2006.201.20:36:22.83#ibcon#*before write, iclass 5, count 0 2006.201.20:36:22.83#ibcon#enter sib2, iclass 5, count 0 2006.201.20:36:22.83#ibcon#flushed, iclass 5, count 0 2006.201.20:36:22.83#ibcon#about to write, iclass 5, count 0 2006.201.20:36:22.83#ibcon#wrote, iclass 5, count 0 2006.201.20:36:22.83#ibcon#about to read 3, iclass 5, count 0 2006.201.20:36:22.86#ibcon#read 3, iclass 5, count 0 2006.201.20:36:22.86#ibcon#about to read 4, iclass 5, count 0 2006.201.20:36:22.86#ibcon#read 4, iclass 5, count 0 2006.201.20:36:22.86#ibcon#about to read 5, iclass 5, count 0 2006.201.20:36:22.86#ibcon#read 5, iclass 5, count 0 2006.201.20:36:22.86#ibcon#about to read 6, iclass 5, count 0 2006.201.20:36:22.86#ibcon#read 6, iclass 5, count 0 2006.201.20:36:22.86#ibcon#end of sib2, iclass 5, count 0 2006.201.20:36:22.86#ibcon#*after write, iclass 5, count 0 2006.201.20:36:22.86#ibcon#*before return 0, iclass 5, count 0 2006.201.20:36:22.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:22.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:22.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.20:36:22.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.20:36:22.86$vck44/valo=7,864.99 2006.201.20:36:22.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.20:36:22.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.20:36:22.86#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:22.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:22.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:22.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:22.86#ibcon#enter wrdev, iclass 7, count 0 2006.201.20:36:22.86#ibcon#first serial, iclass 7, count 0 2006.201.20:36:22.86#ibcon#enter sib2, iclass 7, count 0 2006.201.20:36:22.86#ibcon#flushed, iclass 7, count 0 2006.201.20:36:22.86#ibcon#about to write, iclass 7, count 0 2006.201.20:36:22.86#ibcon#wrote, iclass 7, count 0 2006.201.20:36:22.86#ibcon#about to read 3, iclass 7, count 0 2006.201.20:36:22.88#ibcon#read 3, iclass 7, count 0 2006.201.20:36:22.88#ibcon#about to read 4, iclass 7, count 0 2006.201.20:36:22.88#ibcon#read 4, iclass 7, count 0 2006.201.20:36:22.88#ibcon#about to read 5, iclass 7, count 0 2006.201.20:36:22.88#ibcon#read 5, iclass 7, count 0 2006.201.20:36:22.88#ibcon#about to read 6, iclass 7, count 0 2006.201.20:36:22.88#ibcon#read 6, iclass 7, count 0 2006.201.20:36:22.88#ibcon#end of sib2, iclass 7, count 0 2006.201.20:36:22.88#ibcon#*mode == 0, iclass 7, count 0 2006.201.20:36:22.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.20:36:22.88#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:36:22.88#ibcon#*before write, iclass 7, count 0 2006.201.20:36:22.88#ibcon#enter sib2, iclass 7, count 0 2006.201.20:36:22.88#ibcon#flushed, iclass 7, count 0 2006.201.20:36:22.88#ibcon#about to write, iclass 7, count 0 2006.201.20:36:22.88#ibcon#wrote, iclass 7, count 0 2006.201.20:36:22.88#ibcon#about to read 3, iclass 7, count 0 2006.201.20:36:22.92#ibcon#read 3, iclass 7, count 0 2006.201.20:36:22.92#ibcon#about to read 4, iclass 7, count 0 2006.201.20:36:22.92#ibcon#read 4, iclass 7, count 0 2006.201.20:36:22.92#ibcon#about to read 5, iclass 7, count 0 2006.201.20:36:22.92#ibcon#read 5, iclass 7, count 0 2006.201.20:36:22.92#ibcon#about to read 6, iclass 7, count 0 2006.201.20:36:22.92#ibcon#read 6, iclass 7, count 0 2006.201.20:36:22.92#ibcon#end of sib2, iclass 7, count 0 2006.201.20:36:22.92#ibcon#*after write, iclass 7, count 0 2006.201.20:36:22.92#ibcon#*before return 0, iclass 7, count 0 2006.201.20:36:22.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:22.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:22.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.20:36:22.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.20:36:22.92$vck44/va=7,5 2006.201.20:36:22.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.20:36:22.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.20:36:22.92#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:22.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:22.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:22.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:22.98#ibcon#enter wrdev, iclass 11, count 2 2006.201.20:36:22.98#ibcon#first serial, iclass 11, count 2 2006.201.20:36:22.98#ibcon#enter sib2, iclass 11, count 2 2006.201.20:36:22.98#ibcon#flushed, iclass 11, count 2 2006.201.20:36:22.98#ibcon#about to write, iclass 11, count 2 2006.201.20:36:22.98#ibcon#wrote, iclass 11, count 2 2006.201.20:36:22.98#ibcon#about to read 3, iclass 11, count 2 2006.201.20:36:23.00#ibcon#read 3, iclass 11, count 2 2006.201.20:36:23.00#ibcon#about to read 4, iclass 11, count 2 2006.201.20:36:23.00#ibcon#read 4, iclass 11, count 2 2006.201.20:36:23.00#ibcon#about to read 5, iclass 11, count 2 2006.201.20:36:23.00#ibcon#read 5, iclass 11, count 2 2006.201.20:36:23.00#ibcon#about to read 6, iclass 11, count 2 2006.201.20:36:23.00#ibcon#read 6, iclass 11, count 2 2006.201.20:36:23.00#ibcon#end of sib2, iclass 11, count 2 2006.201.20:36:23.00#ibcon#*mode == 0, iclass 11, count 2 2006.201.20:36:23.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.20:36:23.00#ibcon#[25=AT07-05\r\n] 2006.201.20:36:23.00#ibcon#*before write, iclass 11, count 2 2006.201.20:36:23.00#ibcon#enter sib2, iclass 11, count 2 2006.201.20:36:23.00#ibcon#flushed, iclass 11, count 2 2006.201.20:36:23.00#ibcon#about to write, iclass 11, count 2 2006.201.20:36:23.00#ibcon#wrote, iclass 11, count 2 2006.201.20:36:23.00#ibcon#about to read 3, iclass 11, count 2 2006.201.20:36:23.03#ibcon#read 3, iclass 11, count 2 2006.201.20:36:23.03#ibcon#about to read 4, iclass 11, count 2 2006.201.20:36:23.03#ibcon#read 4, iclass 11, count 2 2006.201.20:36:23.03#ibcon#about to read 5, iclass 11, count 2 2006.201.20:36:23.03#ibcon#read 5, iclass 11, count 2 2006.201.20:36:23.03#ibcon#about to read 6, iclass 11, count 2 2006.201.20:36:23.03#ibcon#read 6, iclass 11, count 2 2006.201.20:36:23.03#ibcon#end of sib2, iclass 11, count 2 2006.201.20:36:23.03#ibcon#*after write, iclass 11, count 2 2006.201.20:36:23.03#ibcon#*before return 0, iclass 11, count 2 2006.201.20:36:23.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:23.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:23.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.20:36:23.03#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:23.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:23.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:23.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:23.15#ibcon#enter wrdev, iclass 11, count 0 2006.201.20:36:23.15#ibcon#first serial, iclass 11, count 0 2006.201.20:36:23.15#ibcon#enter sib2, iclass 11, count 0 2006.201.20:36:23.15#ibcon#flushed, iclass 11, count 0 2006.201.20:36:23.15#ibcon#about to write, iclass 11, count 0 2006.201.20:36:23.15#ibcon#wrote, iclass 11, count 0 2006.201.20:36:23.15#ibcon#about to read 3, iclass 11, count 0 2006.201.20:36:23.17#ibcon#read 3, iclass 11, count 0 2006.201.20:36:23.17#ibcon#about to read 4, iclass 11, count 0 2006.201.20:36:23.17#ibcon#read 4, iclass 11, count 0 2006.201.20:36:23.17#ibcon#about to read 5, iclass 11, count 0 2006.201.20:36:23.17#ibcon#read 5, iclass 11, count 0 2006.201.20:36:23.17#ibcon#about to read 6, iclass 11, count 0 2006.201.20:36:23.17#ibcon#read 6, iclass 11, count 0 2006.201.20:36:23.17#ibcon#end of sib2, iclass 11, count 0 2006.201.20:36:23.17#ibcon#*mode == 0, iclass 11, count 0 2006.201.20:36:23.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.20:36:23.17#ibcon#[25=USB\r\n] 2006.201.20:36:23.17#ibcon#*before write, iclass 11, count 0 2006.201.20:36:23.17#ibcon#enter sib2, iclass 11, count 0 2006.201.20:36:23.17#ibcon#flushed, iclass 11, count 0 2006.201.20:36:23.17#ibcon#about to write, iclass 11, count 0 2006.201.20:36:23.17#ibcon#wrote, iclass 11, count 0 2006.201.20:36:23.17#ibcon#about to read 3, iclass 11, count 0 2006.201.20:36:23.20#ibcon#read 3, iclass 11, count 0 2006.201.20:36:23.20#ibcon#about to read 4, iclass 11, count 0 2006.201.20:36:23.20#ibcon#read 4, iclass 11, count 0 2006.201.20:36:23.20#ibcon#about to read 5, iclass 11, count 0 2006.201.20:36:23.20#ibcon#read 5, iclass 11, count 0 2006.201.20:36:23.20#ibcon#about to read 6, iclass 11, count 0 2006.201.20:36:23.20#ibcon#read 6, iclass 11, count 0 2006.201.20:36:23.20#ibcon#end of sib2, iclass 11, count 0 2006.201.20:36:23.20#ibcon#*after write, iclass 11, count 0 2006.201.20:36:23.20#ibcon#*before return 0, iclass 11, count 0 2006.201.20:36:23.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:23.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:23.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.20:36:23.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.20:36:23.20$vck44/valo=8,884.99 2006.201.20:36:23.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.20:36:23.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.20:36:23.20#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:23.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:23.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:23.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:23.20#ibcon#enter wrdev, iclass 13, count 0 2006.201.20:36:23.20#ibcon#first serial, iclass 13, count 0 2006.201.20:36:23.20#ibcon#enter sib2, iclass 13, count 0 2006.201.20:36:23.20#ibcon#flushed, iclass 13, count 0 2006.201.20:36:23.20#ibcon#about to write, iclass 13, count 0 2006.201.20:36:23.20#ibcon#wrote, iclass 13, count 0 2006.201.20:36:23.20#ibcon#about to read 3, iclass 13, count 0 2006.201.20:36:23.22#ibcon#read 3, iclass 13, count 0 2006.201.20:36:23.22#ibcon#about to read 4, iclass 13, count 0 2006.201.20:36:23.22#ibcon#read 4, iclass 13, count 0 2006.201.20:36:23.22#ibcon#about to read 5, iclass 13, count 0 2006.201.20:36:23.22#ibcon#read 5, iclass 13, count 0 2006.201.20:36:23.22#ibcon#about to read 6, iclass 13, count 0 2006.201.20:36:23.22#ibcon#read 6, iclass 13, count 0 2006.201.20:36:23.22#ibcon#end of sib2, iclass 13, count 0 2006.201.20:36:23.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.20:36:23.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.20:36:23.22#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:36:23.22#ibcon#*before write, iclass 13, count 0 2006.201.20:36:23.22#ibcon#enter sib2, iclass 13, count 0 2006.201.20:36:23.22#ibcon#flushed, iclass 13, count 0 2006.201.20:36:23.22#ibcon#about to write, iclass 13, count 0 2006.201.20:36:23.22#ibcon#wrote, iclass 13, count 0 2006.201.20:36:23.22#ibcon#about to read 3, iclass 13, count 0 2006.201.20:36:23.26#ibcon#read 3, iclass 13, count 0 2006.201.20:36:23.26#ibcon#about to read 4, iclass 13, count 0 2006.201.20:36:23.26#ibcon#read 4, iclass 13, count 0 2006.201.20:36:23.26#ibcon#about to read 5, iclass 13, count 0 2006.201.20:36:23.26#ibcon#read 5, iclass 13, count 0 2006.201.20:36:23.26#ibcon#about to read 6, iclass 13, count 0 2006.201.20:36:23.26#ibcon#read 6, iclass 13, count 0 2006.201.20:36:23.26#ibcon#end of sib2, iclass 13, count 0 2006.201.20:36:23.26#ibcon#*after write, iclass 13, count 0 2006.201.20:36:23.26#ibcon#*before return 0, iclass 13, count 0 2006.201.20:36:23.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:23.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:23.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.20:36:23.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.20:36:23.26$vck44/va=8,4 2006.201.20:36:23.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.20:36:23.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.20:36:23.26#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:23.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:36:23.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:36:23.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:36:23.32#ibcon#enter wrdev, iclass 15, count 2 2006.201.20:36:23.32#ibcon#first serial, iclass 15, count 2 2006.201.20:36:23.32#ibcon#enter sib2, iclass 15, count 2 2006.201.20:36:23.32#ibcon#flushed, iclass 15, count 2 2006.201.20:36:23.32#ibcon#about to write, iclass 15, count 2 2006.201.20:36:23.32#ibcon#wrote, iclass 15, count 2 2006.201.20:36:23.32#ibcon#about to read 3, iclass 15, count 2 2006.201.20:36:23.34#ibcon#read 3, iclass 15, count 2 2006.201.20:36:23.34#ibcon#about to read 4, iclass 15, count 2 2006.201.20:36:23.34#ibcon#read 4, iclass 15, count 2 2006.201.20:36:23.34#ibcon#about to read 5, iclass 15, count 2 2006.201.20:36:23.34#ibcon#read 5, iclass 15, count 2 2006.201.20:36:23.34#ibcon#about to read 6, iclass 15, count 2 2006.201.20:36:23.34#ibcon#read 6, iclass 15, count 2 2006.201.20:36:23.34#ibcon#end of sib2, iclass 15, count 2 2006.201.20:36:23.34#ibcon#*mode == 0, iclass 15, count 2 2006.201.20:36:23.34#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.20:36:23.34#ibcon#[25=AT08-04\r\n] 2006.201.20:36:23.34#ibcon#*before write, iclass 15, count 2 2006.201.20:36:23.34#ibcon#enter sib2, iclass 15, count 2 2006.201.20:36:23.34#ibcon#flushed, iclass 15, count 2 2006.201.20:36:23.34#ibcon#about to write, iclass 15, count 2 2006.201.20:36:23.34#ibcon#wrote, iclass 15, count 2 2006.201.20:36:23.34#ibcon#about to read 3, iclass 15, count 2 2006.201.20:36:23.37#ibcon#read 3, iclass 15, count 2 2006.201.20:36:23.37#ibcon#about to read 4, iclass 15, count 2 2006.201.20:36:23.37#ibcon#read 4, iclass 15, count 2 2006.201.20:36:23.37#ibcon#about to read 5, iclass 15, count 2 2006.201.20:36:23.37#ibcon#read 5, iclass 15, count 2 2006.201.20:36:23.37#ibcon#about to read 6, iclass 15, count 2 2006.201.20:36:23.37#ibcon#read 6, iclass 15, count 2 2006.201.20:36:23.37#ibcon#end of sib2, iclass 15, count 2 2006.201.20:36:23.37#ibcon#*after write, iclass 15, count 2 2006.201.20:36:23.37#ibcon#*before return 0, iclass 15, count 2 2006.201.20:36:23.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:36:23.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.20:36:23.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.20:36:23.37#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:23.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:36:23.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:36:23.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:36:23.49#ibcon#enter wrdev, iclass 15, count 0 2006.201.20:36:23.49#ibcon#first serial, iclass 15, count 0 2006.201.20:36:23.49#ibcon#enter sib2, iclass 15, count 0 2006.201.20:36:23.49#ibcon#flushed, iclass 15, count 0 2006.201.20:36:23.49#ibcon#about to write, iclass 15, count 0 2006.201.20:36:23.49#ibcon#wrote, iclass 15, count 0 2006.201.20:36:23.49#ibcon#about to read 3, iclass 15, count 0 2006.201.20:36:23.51#ibcon#read 3, iclass 15, count 0 2006.201.20:36:23.51#ibcon#about to read 4, iclass 15, count 0 2006.201.20:36:23.51#ibcon#read 4, iclass 15, count 0 2006.201.20:36:23.51#ibcon#about to read 5, iclass 15, count 0 2006.201.20:36:23.51#ibcon#read 5, iclass 15, count 0 2006.201.20:36:23.51#ibcon#about to read 6, iclass 15, count 0 2006.201.20:36:23.51#ibcon#read 6, iclass 15, count 0 2006.201.20:36:23.51#ibcon#end of sib2, iclass 15, count 0 2006.201.20:36:23.51#ibcon#*mode == 0, iclass 15, count 0 2006.201.20:36:23.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.20:36:23.51#ibcon#[25=USB\r\n] 2006.201.20:36:23.51#ibcon#*before write, iclass 15, count 0 2006.201.20:36:23.51#ibcon#enter sib2, iclass 15, count 0 2006.201.20:36:23.51#ibcon#flushed, iclass 15, count 0 2006.201.20:36:23.51#ibcon#about to write, iclass 15, count 0 2006.201.20:36:23.51#ibcon#wrote, iclass 15, count 0 2006.201.20:36:23.51#ibcon#about to read 3, iclass 15, count 0 2006.201.20:36:23.54#ibcon#read 3, iclass 15, count 0 2006.201.20:36:23.54#ibcon#about to read 4, iclass 15, count 0 2006.201.20:36:23.54#ibcon#read 4, iclass 15, count 0 2006.201.20:36:23.54#ibcon#about to read 5, iclass 15, count 0 2006.201.20:36:23.54#ibcon#read 5, iclass 15, count 0 2006.201.20:36:23.54#ibcon#about to read 6, iclass 15, count 0 2006.201.20:36:23.54#ibcon#read 6, iclass 15, count 0 2006.201.20:36:23.54#ibcon#end of sib2, iclass 15, count 0 2006.201.20:36:23.54#ibcon#*after write, iclass 15, count 0 2006.201.20:36:23.54#ibcon#*before return 0, iclass 15, count 0 2006.201.20:36:23.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:36:23.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.20:36:23.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.20:36:23.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.20:36:23.54$vck44/vblo=1,629.99 2006.201.20:36:23.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.20:36:23.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.20:36:23.54#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:23.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:36:23.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:36:23.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:36:23.54#ibcon#enter wrdev, iclass 17, count 0 2006.201.20:36:23.54#ibcon#first serial, iclass 17, count 0 2006.201.20:36:23.54#ibcon#enter sib2, iclass 17, count 0 2006.201.20:36:23.54#ibcon#flushed, iclass 17, count 0 2006.201.20:36:23.54#ibcon#about to write, iclass 17, count 0 2006.201.20:36:23.54#ibcon#wrote, iclass 17, count 0 2006.201.20:36:23.54#ibcon#about to read 3, iclass 17, count 0 2006.201.20:36:23.56#ibcon#read 3, iclass 17, count 0 2006.201.20:36:23.56#ibcon#about to read 4, iclass 17, count 0 2006.201.20:36:23.56#ibcon#read 4, iclass 17, count 0 2006.201.20:36:23.56#ibcon#about to read 5, iclass 17, count 0 2006.201.20:36:23.56#ibcon#read 5, iclass 17, count 0 2006.201.20:36:23.56#ibcon#about to read 6, iclass 17, count 0 2006.201.20:36:23.56#ibcon#read 6, iclass 17, count 0 2006.201.20:36:23.56#ibcon#end of sib2, iclass 17, count 0 2006.201.20:36:23.56#ibcon#*mode == 0, iclass 17, count 0 2006.201.20:36:23.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.20:36:23.56#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:36:23.56#ibcon#*before write, iclass 17, count 0 2006.201.20:36:23.56#ibcon#enter sib2, iclass 17, count 0 2006.201.20:36:23.56#ibcon#flushed, iclass 17, count 0 2006.201.20:36:23.56#ibcon#about to write, iclass 17, count 0 2006.201.20:36:23.56#ibcon#wrote, iclass 17, count 0 2006.201.20:36:23.56#ibcon#about to read 3, iclass 17, count 0 2006.201.20:36:23.60#ibcon#read 3, iclass 17, count 0 2006.201.20:36:23.60#ibcon#about to read 4, iclass 17, count 0 2006.201.20:36:23.60#ibcon#read 4, iclass 17, count 0 2006.201.20:36:23.60#ibcon#about to read 5, iclass 17, count 0 2006.201.20:36:23.60#ibcon#read 5, iclass 17, count 0 2006.201.20:36:23.60#ibcon#about to read 6, iclass 17, count 0 2006.201.20:36:23.60#ibcon#read 6, iclass 17, count 0 2006.201.20:36:23.60#ibcon#end of sib2, iclass 17, count 0 2006.201.20:36:23.60#ibcon#*after write, iclass 17, count 0 2006.201.20:36:23.60#ibcon#*before return 0, iclass 17, count 0 2006.201.20:36:23.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:36:23.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:36:23.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.20:36:23.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.20:36:23.60$vck44/vb=1,4 2006.201.20:36:23.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.20:36:23.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.20:36:23.60#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:23.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:36:23.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:36:23.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:36:23.60#ibcon#enter wrdev, iclass 19, count 2 2006.201.20:36:23.60#ibcon#first serial, iclass 19, count 2 2006.201.20:36:23.60#ibcon#enter sib2, iclass 19, count 2 2006.201.20:36:23.60#ibcon#flushed, iclass 19, count 2 2006.201.20:36:23.60#ibcon#about to write, iclass 19, count 2 2006.201.20:36:23.60#ibcon#wrote, iclass 19, count 2 2006.201.20:36:23.60#ibcon#about to read 3, iclass 19, count 2 2006.201.20:36:23.62#ibcon#read 3, iclass 19, count 2 2006.201.20:36:23.62#ibcon#about to read 4, iclass 19, count 2 2006.201.20:36:23.62#ibcon#read 4, iclass 19, count 2 2006.201.20:36:23.62#ibcon#about to read 5, iclass 19, count 2 2006.201.20:36:23.62#ibcon#read 5, iclass 19, count 2 2006.201.20:36:23.62#ibcon#about to read 6, iclass 19, count 2 2006.201.20:36:23.62#ibcon#read 6, iclass 19, count 2 2006.201.20:36:23.62#ibcon#end of sib2, iclass 19, count 2 2006.201.20:36:23.62#ibcon#*mode == 0, iclass 19, count 2 2006.201.20:36:23.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.20:36:23.62#ibcon#[27=AT01-04\r\n] 2006.201.20:36:23.62#ibcon#*before write, iclass 19, count 2 2006.201.20:36:23.62#ibcon#enter sib2, iclass 19, count 2 2006.201.20:36:23.62#ibcon#flushed, iclass 19, count 2 2006.201.20:36:23.62#ibcon#about to write, iclass 19, count 2 2006.201.20:36:23.62#ibcon#wrote, iclass 19, count 2 2006.201.20:36:23.62#ibcon#about to read 3, iclass 19, count 2 2006.201.20:36:23.65#ibcon#read 3, iclass 19, count 2 2006.201.20:36:23.65#ibcon#about to read 4, iclass 19, count 2 2006.201.20:36:23.65#ibcon#read 4, iclass 19, count 2 2006.201.20:36:23.65#ibcon#about to read 5, iclass 19, count 2 2006.201.20:36:23.65#ibcon#read 5, iclass 19, count 2 2006.201.20:36:23.65#ibcon#about to read 6, iclass 19, count 2 2006.201.20:36:23.65#ibcon#read 6, iclass 19, count 2 2006.201.20:36:23.65#ibcon#end of sib2, iclass 19, count 2 2006.201.20:36:23.65#ibcon#*after write, iclass 19, count 2 2006.201.20:36:23.65#ibcon#*before return 0, iclass 19, count 2 2006.201.20:36:23.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:36:23.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.20:36:23.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.20:36:23.65#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:23.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:36:23.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:36:23.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:36:23.77#ibcon#enter wrdev, iclass 19, count 0 2006.201.20:36:23.77#ibcon#first serial, iclass 19, count 0 2006.201.20:36:23.77#ibcon#enter sib2, iclass 19, count 0 2006.201.20:36:23.77#ibcon#flushed, iclass 19, count 0 2006.201.20:36:23.77#ibcon#about to write, iclass 19, count 0 2006.201.20:36:23.77#ibcon#wrote, iclass 19, count 0 2006.201.20:36:23.77#ibcon#about to read 3, iclass 19, count 0 2006.201.20:36:23.79#ibcon#read 3, iclass 19, count 0 2006.201.20:36:23.79#ibcon#about to read 4, iclass 19, count 0 2006.201.20:36:23.79#ibcon#read 4, iclass 19, count 0 2006.201.20:36:23.79#ibcon#about to read 5, iclass 19, count 0 2006.201.20:36:23.79#ibcon#read 5, iclass 19, count 0 2006.201.20:36:23.79#ibcon#about to read 6, iclass 19, count 0 2006.201.20:36:23.79#ibcon#read 6, iclass 19, count 0 2006.201.20:36:23.79#ibcon#end of sib2, iclass 19, count 0 2006.201.20:36:23.79#ibcon#*mode == 0, iclass 19, count 0 2006.201.20:36:23.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.20:36:23.79#ibcon#[27=USB\r\n] 2006.201.20:36:23.79#ibcon#*before write, iclass 19, count 0 2006.201.20:36:23.79#ibcon#enter sib2, iclass 19, count 0 2006.201.20:36:23.79#ibcon#flushed, iclass 19, count 0 2006.201.20:36:23.79#ibcon#about to write, iclass 19, count 0 2006.201.20:36:23.79#ibcon#wrote, iclass 19, count 0 2006.201.20:36:23.79#ibcon#about to read 3, iclass 19, count 0 2006.201.20:36:23.82#ibcon#read 3, iclass 19, count 0 2006.201.20:36:23.82#ibcon#about to read 4, iclass 19, count 0 2006.201.20:36:23.82#ibcon#read 4, iclass 19, count 0 2006.201.20:36:23.82#ibcon#about to read 5, iclass 19, count 0 2006.201.20:36:23.82#ibcon#read 5, iclass 19, count 0 2006.201.20:36:23.82#ibcon#about to read 6, iclass 19, count 0 2006.201.20:36:23.82#ibcon#read 6, iclass 19, count 0 2006.201.20:36:23.82#ibcon#end of sib2, iclass 19, count 0 2006.201.20:36:23.82#ibcon#*after write, iclass 19, count 0 2006.201.20:36:23.82#ibcon#*before return 0, iclass 19, count 0 2006.201.20:36:23.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:36:23.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.20:36:23.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.20:36:23.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.20:36:23.82$vck44/vblo=2,634.99 2006.201.20:36:23.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.20:36:23.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.20:36:23.82#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:23.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:23.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:23.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:23.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.20:36:23.82#ibcon#first serial, iclass 21, count 0 2006.201.20:36:23.82#ibcon#enter sib2, iclass 21, count 0 2006.201.20:36:23.82#ibcon#flushed, iclass 21, count 0 2006.201.20:36:23.82#ibcon#about to write, iclass 21, count 0 2006.201.20:36:23.82#ibcon#wrote, iclass 21, count 0 2006.201.20:36:23.82#ibcon#about to read 3, iclass 21, count 0 2006.201.20:36:23.84#ibcon#read 3, iclass 21, count 0 2006.201.20:36:23.84#ibcon#about to read 4, iclass 21, count 0 2006.201.20:36:23.84#ibcon#read 4, iclass 21, count 0 2006.201.20:36:23.84#ibcon#about to read 5, iclass 21, count 0 2006.201.20:36:23.84#ibcon#read 5, iclass 21, count 0 2006.201.20:36:23.84#ibcon#about to read 6, iclass 21, count 0 2006.201.20:36:23.84#ibcon#read 6, iclass 21, count 0 2006.201.20:36:23.84#ibcon#end of sib2, iclass 21, count 0 2006.201.20:36:23.84#ibcon#*mode == 0, iclass 21, count 0 2006.201.20:36:23.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.20:36:23.84#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:36:23.84#ibcon#*before write, iclass 21, count 0 2006.201.20:36:23.84#ibcon#enter sib2, iclass 21, count 0 2006.201.20:36:23.84#ibcon#flushed, iclass 21, count 0 2006.201.20:36:23.84#ibcon#about to write, iclass 21, count 0 2006.201.20:36:23.84#ibcon#wrote, iclass 21, count 0 2006.201.20:36:23.84#ibcon#about to read 3, iclass 21, count 0 2006.201.20:36:23.88#ibcon#read 3, iclass 21, count 0 2006.201.20:36:23.88#ibcon#about to read 4, iclass 21, count 0 2006.201.20:36:23.88#ibcon#read 4, iclass 21, count 0 2006.201.20:36:23.88#ibcon#about to read 5, iclass 21, count 0 2006.201.20:36:23.88#ibcon#read 5, iclass 21, count 0 2006.201.20:36:23.88#ibcon#about to read 6, iclass 21, count 0 2006.201.20:36:23.88#ibcon#read 6, iclass 21, count 0 2006.201.20:36:23.88#ibcon#end of sib2, iclass 21, count 0 2006.201.20:36:23.88#ibcon#*after write, iclass 21, count 0 2006.201.20:36:23.88#ibcon#*before return 0, iclass 21, count 0 2006.201.20:36:23.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:23.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.20:36:23.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.20:36:23.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.20:36:23.88$vck44/vb=2,5 2006.201.20:36:23.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.20:36:23.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.20:36:23.88#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:23.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:23.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:23.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:23.94#ibcon#enter wrdev, iclass 23, count 2 2006.201.20:36:23.94#ibcon#first serial, iclass 23, count 2 2006.201.20:36:23.94#ibcon#enter sib2, iclass 23, count 2 2006.201.20:36:23.94#ibcon#flushed, iclass 23, count 2 2006.201.20:36:23.94#ibcon#about to write, iclass 23, count 2 2006.201.20:36:23.94#ibcon#wrote, iclass 23, count 2 2006.201.20:36:23.94#ibcon#about to read 3, iclass 23, count 2 2006.201.20:36:23.96#ibcon#read 3, iclass 23, count 2 2006.201.20:36:23.96#ibcon#about to read 4, iclass 23, count 2 2006.201.20:36:23.96#ibcon#read 4, iclass 23, count 2 2006.201.20:36:23.96#ibcon#about to read 5, iclass 23, count 2 2006.201.20:36:23.96#ibcon#read 5, iclass 23, count 2 2006.201.20:36:23.96#ibcon#about to read 6, iclass 23, count 2 2006.201.20:36:23.96#ibcon#read 6, iclass 23, count 2 2006.201.20:36:23.96#ibcon#end of sib2, iclass 23, count 2 2006.201.20:36:23.96#ibcon#*mode == 0, iclass 23, count 2 2006.201.20:36:23.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.20:36:23.96#ibcon#[27=AT02-05\r\n] 2006.201.20:36:23.96#ibcon#*before write, iclass 23, count 2 2006.201.20:36:23.96#ibcon#enter sib2, iclass 23, count 2 2006.201.20:36:23.96#ibcon#flushed, iclass 23, count 2 2006.201.20:36:23.96#ibcon#about to write, iclass 23, count 2 2006.201.20:36:23.96#ibcon#wrote, iclass 23, count 2 2006.201.20:36:23.96#ibcon#about to read 3, iclass 23, count 2 2006.201.20:36:23.99#ibcon#read 3, iclass 23, count 2 2006.201.20:36:23.99#ibcon#about to read 4, iclass 23, count 2 2006.201.20:36:23.99#ibcon#read 4, iclass 23, count 2 2006.201.20:36:23.99#ibcon#about to read 5, iclass 23, count 2 2006.201.20:36:23.99#ibcon#read 5, iclass 23, count 2 2006.201.20:36:23.99#ibcon#about to read 6, iclass 23, count 2 2006.201.20:36:23.99#ibcon#read 6, iclass 23, count 2 2006.201.20:36:23.99#ibcon#end of sib2, iclass 23, count 2 2006.201.20:36:23.99#ibcon#*after write, iclass 23, count 2 2006.201.20:36:23.99#ibcon#*before return 0, iclass 23, count 2 2006.201.20:36:23.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:23.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.20:36:23.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.20:36:23.99#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:23.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:24.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:24.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:24.11#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:36:24.11#ibcon#first serial, iclass 23, count 0 2006.201.20:36:24.11#ibcon#enter sib2, iclass 23, count 0 2006.201.20:36:24.11#ibcon#flushed, iclass 23, count 0 2006.201.20:36:24.11#ibcon#about to write, iclass 23, count 0 2006.201.20:36:24.11#ibcon#wrote, iclass 23, count 0 2006.201.20:36:24.11#ibcon#about to read 3, iclass 23, count 0 2006.201.20:36:24.13#ibcon#read 3, iclass 23, count 0 2006.201.20:36:24.13#ibcon#about to read 4, iclass 23, count 0 2006.201.20:36:24.13#ibcon#read 4, iclass 23, count 0 2006.201.20:36:24.13#ibcon#about to read 5, iclass 23, count 0 2006.201.20:36:24.13#ibcon#read 5, iclass 23, count 0 2006.201.20:36:24.13#ibcon#about to read 6, iclass 23, count 0 2006.201.20:36:24.13#ibcon#read 6, iclass 23, count 0 2006.201.20:36:24.13#ibcon#end of sib2, iclass 23, count 0 2006.201.20:36:24.13#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:36:24.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:36:24.13#ibcon#[27=USB\r\n] 2006.201.20:36:24.13#ibcon#*before write, iclass 23, count 0 2006.201.20:36:24.13#ibcon#enter sib2, iclass 23, count 0 2006.201.20:36:24.13#ibcon#flushed, iclass 23, count 0 2006.201.20:36:24.13#ibcon#about to write, iclass 23, count 0 2006.201.20:36:24.13#ibcon#wrote, iclass 23, count 0 2006.201.20:36:24.13#ibcon#about to read 3, iclass 23, count 0 2006.201.20:36:24.16#ibcon#read 3, iclass 23, count 0 2006.201.20:36:24.16#ibcon#about to read 4, iclass 23, count 0 2006.201.20:36:24.16#ibcon#read 4, iclass 23, count 0 2006.201.20:36:24.16#ibcon#about to read 5, iclass 23, count 0 2006.201.20:36:24.16#ibcon#read 5, iclass 23, count 0 2006.201.20:36:24.16#ibcon#about to read 6, iclass 23, count 0 2006.201.20:36:24.16#ibcon#read 6, iclass 23, count 0 2006.201.20:36:24.16#ibcon#end of sib2, iclass 23, count 0 2006.201.20:36:24.16#ibcon#*after write, iclass 23, count 0 2006.201.20:36:24.16#ibcon#*before return 0, iclass 23, count 0 2006.201.20:36:24.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:24.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.20:36:24.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:36:24.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:36:24.16$vck44/vblo=3,649.99 2006.201.20:36:24.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.20:36:24.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.20:36:24.16#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:24.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:24.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:24.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:24.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.20:36:24.16#ibcon#first serial, iclass 25, count 0 2006.201.20:36:24.16#ibcon#enter sib2, iclass 25, count 0 2006.201.20:36:24.16#ibcon#flushed, iclass 25, count 0 2006.201.20:36:24.16#ibcon#about to write, iclass 25, count 0 2006.201.20:36:24.16#ibcon#wrote, iclass 25, count 0 2006.201.20:36:24.16#ibcon#about to read 3, iclass 25, count 0 2006.201.20:36:24.18#ibcon#read 3, iclass 25, count 0 2006.201.20:36:24.18#ibcon#about to read 4, iclass 25, count 0 2006.201.20:36:24.18#ibcon#read 4, iclass 25, count 0 2006.201.20:36:24.18#ibcon#about to read 5, iclass 25, count 0 2006.201.20:36:24.18#ibcon#read 5, iclass 25, count 0 2006.201.20:36:24.18#ibcon#about to read 6, iclass 25, count 0 2006.201.20:36:24.18#ibcon#read 6, iclass 25, count 0 2006.201.20:36:24.18#ibcon#end of sib2, iclass 25, count 0 2006.201.20:36:24.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.20:36:24.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.20:36:24.18#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:36:24.18#ibcon#*before write, iclass 25, count 0 2006.201.20:36:24.18#ibcon#enter sib2, iclass 25, count 0 2006.201.20:36:24.18#ibcon#flushed, iclass 25, count 0 2006.201.20:36:24.18#ibcon#about to write, iclass 25, count 0 2006.201.20:36:24.18#ibcon#wrote, iclass 25, count 0 2006.201.20:36:24.18#ibcon#about to read 3, iclass 25, count 0 2006.201.20:36:24.22#ibcon#read 3, iclass 25, count 0 2006.201.20:36:24.22#ibcon#about to read 4, iclass 25, count 0 2006.201.20:36:24.22#ibcon#read 4, iclass 25, count 0 2006.201.20:36:24.22#ibcon#about to read 5, iclass 25, count 0 2006.201.20:36:24.22#ibcon#read 5, iclass 25, count 0 2006.201.20:36:24.22#ibcon#about to read 6, iclass 25, count 0 2006.201.20:36:24.22#ibcon#read 6, iclass 25, count 0 2006.201.20:36:24.22#ibcon#end of sib2, iclass 25, count 0 2006.201.20:36:24.22#ibcon#*after write, iclass 25, count 0 2006.201.20:36:24.22#ibcon#*before return 0, iclass 25, count 0 2006.201.20:36:24.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:24.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.20:36:24.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.20:36:24.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.20:36:24.22$vck44/vb=3,4 2006.201.20:36:24.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.20:36:24.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.20:36:24.22#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:24.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:24.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:24.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:24.28#ibcon#enter wrdev, iclass 27, count 2 2006.201.20:36:24.28#ibcon#first serial, iclass 27, count 2 2006.201.20:36:24.28#ibcon#enter sib2, iclass 27, count 2 2006.201.20:36:24.28#ibcon#flushed, iclass 27, count 2 2006.201.20:36:24.28#ibcon#about to write, iclass 27, count 2 2006.201.20:36:24.28#ibcon#wrote, iclass 27, count 2 2006.201.20:36:24.28#ibcon#about to read 3, iclass 27, count 2 2006.201.20:36:24.30#ibcon#read 3, iclass 27, count 2 2006.201.20:36:24.30#ibcon#about to read 4, iclass 27, count 2 2006.201.20:36:24.30#ibcon#read 4, iclass 27, count 2 2006.201.20:36:24.30#ibcon#about to read 5, iclass 27, count 2 2006.201.20:36:24.30#ibcon#read 5, iclass 27, count 2 2006.201.20:36:24.30#ibcon#about to read 6, iclass 27, count 2 2006.201.20:36:24.30#ibcon#read 6, iclass 27, count 2 2006.201.20:36:24.30#ibcon#end of sib2, iclass 27, count 2 2006.201.20:36:24.30#ibcon#*mode == 0, iclass 27, count 2 2006.201.20:36:24.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.20:36:24.30#ibcon#[27=AT03-04\r\n] 2006.201.20:36:24.30#ibcon#*before write, iclass 27, count 2 2006.201.20:36:24.30#ibcon#enter sib2, iclass 27, count 2 2006.201.20:36:24.30#ibcon#flushed, iclass 27, count 2 2006.201.20:36:24.30#ibcon#about to write, iclass 27, count 2 2006.201.20:36:24.30#ibcon#wrote, iclass 27, count 2 2006.201.20:36:24.30#ibcon#about to read 3, iclass 27, count 2 2006.201.20:36:24.33#ibcon#read 3, iclass 27, count 2 2006.201.20:36:24.33#ibcon#about to read 4, iclass 27, count 2 2006.201.20:36:24.33#ibcon#read 4, iclass 27, count 2 2006.201.20:36:24.33#ibcon#about to read 5, iclass 27, count 2 2006.201.20:36:24.33#ibcon#read 5, iclass 27, count 2 2006.201.20:36:24.33#ibcon#about to read 6, iclass 27, count 2 2006.201.20:36:24.33#ibcon#read 6, iclass 27, count 2 2006.201.20:36:24.33#ibcon#end of sib2, iclass 27, count 2 2006.201.20:36:24.33#ibcon#*after write, iclass 27, count 2 2006.201.20:36:24.33#ibcon#*before return 0, iclass 27, count 2 2006.201.20:36:24.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:24.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:36:24.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.20:36:24.33#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:24.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:24.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:24.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:24.45#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:36:24.45#ibcon#first serial, iclass 27, count 0 2006.201.20:36:24.45#ibcon#enter sib2, iclass 27, count 0 2006.201.20:36:24.45#ibcon#flushed, iclass 27, count 0 2006.201.20:36:24.45#ibcon#about to write, iclass 27, count 0 2006.201.20:36:24.45#ibcon#wrote, iclass 27, count 0 2006.201.20:36:24.45#ibcon#about to read 3, iclass 27, count 0 2006.201.20:36:24.47#ibcon#read 3, iclass 27, count 0 2006.201.20:36:24.47#ibcon#about to read 4, iclass 27, count 0 2006.201.20:36:24.47#ibcon#read 4, iclass 27, count 0 2006.201.20:36:24.47#ibcon#about to read 5, iclass 27, count 0 2006.201.20:36:24.47#ibcon#read 5, iclass 27, count 0 2006.201.20:36:24.47#ibcon#about to read 6, iclass 27, count 0 2006.201.20:36:24.47#ibcon#read 6, iclass 27, count 0 2006.201.20:36:24.47#ibcon#end of sib2, iclass 27, count 0 2006.201.20:36:24.47#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:36:24.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:36:24.47#ibcon#[27=USB\r\n] 2006.201.20:36:24.47#ibcon#*before write, iclass 27, count 0 2006.201.20:36:24.47#ibcon#enter sib2, iclass 27, count 0 2006.201.20:36:24.47#ibcon#flushed, iclass 27, count 0 2006.201.20:36:24.47#ibcon#about to write, iclass 27, count 0 2006.201.20:36:24.47#ibcon#wrote, iclass 27, count 0 2006.201.20:36:24.47#ibcon#about to read 3, iclass 27, count 0 2006.201.20:36:24.50#ibcon#read 3, iclass 27, count 0 2006.201.20:36:24.50#ibcon#about to read 4, iclass 27, count 0 2006.201.20:36:24.50#ibcon#read 4, iclass 27, count 0 2006.201.20:36:24.50#ibcon#about to read 5, iclass 27, count 0 2006.201.20:36:24.50#ibcon#read 5, iclass 27, count 0 2006.201.20:36:24.50#ibcon#about to read 6, iclass 27, count 0 2006.201.20:36:24.50#ibcon#read 6, iclass 27, count 0 2006.201.20:36:24.50#ibcon#end of sib2, iclass 27, count 0 2006.201.20:36:24.50#ibcon#*after write, iclass 27, count 0 2006.201.20:36:24.50#ibcon#*before return 0, iclass 27, count 0 2006.201.20:36:24.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:24.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:36:24.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:36:24.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:36:24.50$vck44/vblo=4,679.99 2006.201.20:36:24.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.20:36:24.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.20:36:24.50#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:24.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:24.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:24.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:24.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.20:36:24.50#ibcon#first serial, iclass 29, count 0 2006.201.20:36:24.50#ibcon#enter sib2, iclass 29, count 0 2006.201.20:36:24.50#ibcon#flushed, iclass 29, count 0 2006.201.20:36:24.50#ibcon#about to write, iclass 29, count 0 2006.201.20:36:24.50#ibcon#wrote, iclass 29, count 0 2006.201.20:36:24.50#ibcon#about to read 3, iclass 29, count 0 2006.201.20:36:24.52#ibcon#read 3, iclass 29, count 0 2006.201.20:36:24.52#ibcon#about to read 4, iclass 29, count 0 2006.201.20:36:24.52#ibcon#read 4, iclass 29, count 0 2006.201.20:36:24.52#ibcon#about to read 5, iclass 29, count 0 2006.201.20:36:24.52#ibcon#read 5, iclass 29, count 0 2006.201.20:36:24.52#ibcon#about to read 6, iclass 29, count 0 2006.201.20:36:24.52#ibcon#read 6, iclass 29, count 0 2006.201.20:36:24.52#ibcon#end of sib2, iclass 29, count 0 2006.201.20:36:24.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.20:36:24.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.20:36:24.52#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:36:24.52#ibcon#*before write, iclass 29, count 0 2006.201.20:36:24.52#ibcon#enter sib2, iclass 29, count 0 2006.201.20:36:24.52#ibcon#flushed, iclass 29, count 0 2006.201.20:36:24.52#ibcon#about to write, iclass 29, count 0 2006.201.20:36:24.52#ibcon#wrote, iclass 29, count 0 2006.201.20:36:24.52#ibcon#about to read 3, iclass 29, count 0 2006.201.20:36:24.56#ibcon#read 3, iclass 29, count 0 2006.201.20:36:24.56#ibcon#about to read 4, iclass 29, count 0 2006.201.20:36:24.56#ibcon#read 4, iclass 29, count 0 2006.201.20:36:24.56#ibcon#about to read 5, iclass 29, count 0 2006.201.20:36:24.56#ibcon#read 5, iclass 29, count 0 2006.201.20:36:24.56#ibcon#about to read 6, iclass 29, count 0 2006.201.20:36:24.56#ibcon#read 6, iclass 29, count 0 2006.201.20:36:24.56#ibcon#end of sib2, iclass 29, count 0 2006.201.20:36:24.56#ibcon#*after write, iclass 29, count 0 2006.201.20:36:24.56#ibcon#*before return 0, iclass 29, count 0 2006.201.20:36:24.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:24.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.20:36:24.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.20:36:24.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.20:36:24.56$vck44/vb=4,5 2006.201.20:36:24.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.20:36:24.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.20:36:24.56#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:24.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:24.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:24.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:24.62#ibcon#enter wrdev, iclass 31, count 2 2006.201.20:36:24.62#ibcon#first serial, iclass 31, count 2 2006.201.20:36:24.62#ibcon#enter sib2, iclass 31, count 2 2006.201.20:36:24.62#ibcon#flushed, iclass 31, count 2 2006.201.20:36:24.62#ibcon#about to write, iclass 31, count 2 2006.201.20:36:24.62#ibcon#wrote, iclass 31, count 2 2006.201.20:36:24.62#ibcon#about to read 3, iclass 31, count 2 2006.201.20:36:24.64#ibcon#read 3, iclass 31, count 2 2006.201.20:36:24.64#ibcon#about to read 4, iclass 31, count 2 2006.201.20:36:24.64#ibcon#read 4, iclass 31, count 2 2006.201.20:36:24.64#ibcon#about to read 5, iclass 31, count 2 2006.201.20:36:24.64#ibcon#read 5, iclass 31, count 2 2006.201.20:36:24.64#ibcon#about to read 6, iclass 31, count 2 2006.201.20:36:24.64#ibcon#read 6, iclass 31, count 2 2006.201.20:36:24.64#ibcon#end of sib2, iclass 31, count 2 2006.201.20:36:24.64#ibcon#*mode == 0, iclass 31, count 2 2006.201.20:36:24.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.20:36:24.64#ibcon#[27=AT04-05\r\n] 2006.201.20:36:24.64#ibcon#*before write, iclass 31, count 2 2006.201.20:36:24.64#ibcon#enter sib2, iclass 31, count 2 2006.201.20:36:24.64#ibcon#flushed, iclass 31, count 2 2006.201.20:36:24.64#ibcon#about to write, iclass 31, count 2 2006.201.20:36:24.64#ibcon#wrote, iclass 31, count 2 2006.201.20:36:24.64#ibcon#about to read 3, iclass 31, count 2 2006.201.20:36:24.67#ibcon#read 3, iclass 31, count 2 2006.201.20:36:24.67#ibcon#about to read 4, iclass 31, count 2 2006.201.20:36:24.67#ibcon#read 4, iclass 31, count 2 2006.201.20:36:24.67#ibcon#about to read 5, iclass 31, count 2 2006.201.20:36:24.67#ibcon#read 5, iclass 31, count 2 2006.201.20:36:24.67#ibcon#about to read 6, iclass 31, count 2 2006.201.20:36:24.67#ibcon#read 6, iclass 31, count 2 2006.201.20:36:24.67#ibcon#end of sib2, iclass 31, count 2 2006.201.20:36:24.67#ibcon#*after write, iclass 31, count 2 2006.201.20:36:24.67#ibcon#*before return 0, iclass 31, count 2 2006.201.20:36:24.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:24.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.20:36:24.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.20:36:24.67#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:24.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:24.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:24.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:24.79#ibcon#enter wrdev, iclass 31, count 0 2006.201.20:36:24.79#ibcon#first serial, iclass 31, count 0 2006.201.20:36:24.79#ibcon#enter sib2, iclass 31, count 0 2006.201.20:36:24.79#ibcon#flushed, iclass 31, count 0 2006.201.20:36:24.79#ibcon#about to write, iclass 31, count 0 2006.201.20:36:24.79#ibcon#wrote, iclass 31, count 0 2006.201.20:36:24.79#ibcon#about to read 3, iclass 31, count 0 2006.201.20:36:24.81#ibcon#read 3, iclass 31, count 0 2006.201.20:36:24.81#ibcon#about to read 4, iclass 31, count 0 2006.201.20:36:24.81#ibcon#read 4, iclass 31, count 0 2006.201.20:36:24.81#ibcon#about to read 5, iclass 31, count 0 2006.201.20:36:24.81#ibcon#read 5, iclass 31, count 0 2006.201.20:36:24.81#ibcon#about to read 6, iclass 31, count 0 2006.201.20:36:24.81#ibcon#read 6, iclass 31, count 0 2006.201.20:36:24.81#ibcon#end of sib2, iclass 31, count 0 2006.201.20:36:24.81#ibcon#*mode == 0, iclass 31, count 0 2006.201.20:36:24.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.20:36:24.81#ibcon#[27=USB\r\n] 2006.201.20:36:24.81#ibcon#*before write, iclass 31, count 0 2006.201.20:36:24.81#ibcon#enter sib2, iclass 31, count 0 2006.201.20:36:24.81#ibcon#flushed, iclass 31, count 0 2006.201.20:36:24.81#ibcon#about to write, iclass 31, count 0 2006.201.20:36:24.81#ibcon#wrote, iclass 31, count 0 2006.201.20:36:24.81#ibcon#about to read 3, iclass 31, count 0 2006.201.20:36:24.84#ibcon#read 3, iclass 31, count 0 2006.201.20:36:24.84#ibcon#about to read 4, iclass 31, count 0 2006.201.20:36:24.84#ibcon#read 4, iclass 31, count 0 2006.201.20:36:24.84#ibcon#about to read 5, iclass 31, count 0 2006.201.20:36:24.84#ibcon#read 5, iclass 31, count 0 2006.201.20:36:24.84#ibcon#about to read 6, iclass 31, count 0 2006.201.20:36:24.84#ibcon#read 6, iclass 31, count 0 2006.201.20:36:24.84#ibcon#end of sib2, iclass 31, count 0 2006.201.20:36:24.84#ibcon#*after write, iclass 31, count 0 2006.201.20:36:24.84#ibcon#*before return 0, iclass 31, count 0 2006.201.20:36:24.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:24.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.20:36:24.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.20:36:24.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.20:36:24.84$vck44/vblo=5,709.99 2006.201.20:36:24.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.20:36:24.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.20:36:24.84#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:24.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:24.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:24.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:24.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.20:36:24.84#ibcon#first serial, iclass 33, count 0 2006.201.20:36:24.84#ibcon#enter sib2, iclass 33, count 0 2006.201.20:36:24.84#ibcon#flushed, iclass 33, count 0 2006.201.20:36:24.84#ibcon#about to write, iclass 33, count 0 2006.201.20:36:24.84#ibcon#wrote, iclass 33, count 0 2006.201.20:36:24.84#ibcon#about to read 3, iclass 33, count 0 2006.201.20:36:24.86#ibcon#read 3, iclass 33, count 0 2006.201.20:36:24.86#ibcon#about to read 4, iclass 33, count 0 2006.201.20:36:24.86#ibcon#read 4, iclass 33, count 0 2006.201.20:36:24.86#ibcon#about to read 5, iclass 33, count 0 2006.201.20:36:24.86#ibcon#read 5, iclass 33, count 0 2006.201.20:36:24.86#ibcon#about to read 6, iclass 33, count 0 2006.201.20:36:24.86#ibcon#read 6, iclass 33, count 0 2006.201.20:36:24.86#ibcon#end of sib2, iclass 33, count 0 2006.201.20:36:24.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.20:36:24.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.20:36:24.86#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:36:24.86#ibcon#*before write, iclass 33, count 0 2006.201.20:36:24.86#ibcon#enter sib2, iclass 33, count 0 2006.201.20:36:24.86#ibcon#flushed, iclass 33, count 0 2006.201.20:36:24.86#ibcon#about to write, iclass 33, count 0 2006.201.20:36:24.86#ibcon#wrote, iclass 33, count 0 2006.201.20:36:24.86#ibcon#about to read 3, iclass 33, count 0 2006.201.20:36:24.91#ibcon#read 3, iclass 33, count 0 2006.201.20:36:24.91#ibcon#about to read 4, iclass 33, count 0 2006.201.20:36:24.91#ibcon#read 4, iclass 33, count 0 2006.201.20:36:24.91#ibcon#about to read 5, iclass 33, count 0 2006.201.20:36:24.91#ibcon#read 5, iclass 33, count 0 2006.201.20:36:24.91#ibcon#about to read 6, iclass 33, count 0 2006.201.20:36:24.91#ibcon#read 6, iclass 33, count 0 2006.201.20:36:24.91#ibcon#end of sib2, iclass 33, count 0 2006.201.20:36:24.91#ibcon#*after write, iclass 33, count 0 2006.201.20:36:24.91#ibcon#*before return 0, iclass 33, count 0 2006.201.20:36:24.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:24.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.20:36:24.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.20:36:24.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.20:36:24.91$vck44/vb=5,4 2006.201.20:36:24.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.20:36:24.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.20:36:24.91#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:24.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:24.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:24.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:24.96#ibcon#enter wrdev, iclass 35, count 2 2006.201.20:36:24.96#ibcon#first serial, iclass 35, count 2 2006.201.20:36:24.96#ibcon#enter sib2, iclass 35, count 2 2006.201.20:36:24.96#ibcon#flushed, iclass 35, count 2 2006.201.20:36:24.96#ibcon#about to write, iclass 35, count 2 2006.201.20:36:24.96#ibcon#wrote, iclass 35, count 2 2006.201.20:36:24.96#ibcon#about to read 3, iclass 35, count 2 2006.201.20:36:24.98#ibcon#read 3, iclass 35, count 2 2006.201.20:36:24.98#ibcon#about to read 4, iclass 35, count 2 2006.201.20:36:24.98#ibcon#read 4, iclass 35, count 2 2006.201.20:36:24.98#ibcon#about to read 5, iclass 35, count 2 2006.201.20:36:24.98#ibcon#read 5, iclass 35, count 2 2006.201.20:36:24.98#ibcon#about to read 6, iclass 35, count 2 2006.201.20:36:24.98#ibcon#read 6, iclass 35, count 2 2006.201.20:36:24.98#ibcon#end of sib2, iclass 35, count 2 2006.201.20:36:24.98#ibcon#*mode == 0, iclass 35, count 2 2006.201.20:36:24.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.20:36:24.98#ibcon#[27=AT05-04\r\n] 2006.201.20:36:24.98#ibcon#*before write, iclass 35, count 2 2006.201.20:36:24.98#ibcon#enter sib2, iclass 35, count 2 2006.201.20:36:24.98#ibcon#flushed, iclass 35, count 2 2006.201.20:36:24.98#ibcon#about to write, iclass 35, count 2 2006.201.20:36:24.98#ibcon#wrote, iclass 35, count 2 2006.201.20:36:24.98#ibcon#about to read 3, iclass 35, count 2 2006.201.20:36:25.01#ibcon#read 3, iclass 35, count 2 2006.201.20:36:25.01#ibcon#about to read 4, iclass 35, count 2 2006.201.20:36:25.01#ibcon#read 4, iclass 35, count 2 2006.201.20:36:25.01#ibcon#about to read 5, iclass 35, count 2 2006.201.20:36:25.01#ibcon#read 5, iclass 35, count 2 2006.201.20:36:25.01#ibcon#about to read 6, iclass 35, count 2 2006.201.20:36:25.01#ibcon#read 6, iclass 35, count 2 2006.201.20:36:25.01#ibcon#end of sib2, iclass 35, count 2 2006.201.20:36:25.01#ibcon#*after write, iclass 35, count 2 2006.201.20:36:25.01#ibcon#*before return 0, iclass 35, count 2 2006.201.20:36:25.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:25.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.20:36:25.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.20:36:25.01#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:25.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:25.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:25.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:25.13#ibcon#enter wrdev, iclass 35, count 0 2006.201.20:36:25.13#ibcon#first serial, iclass 35, count 0 2006.201.20:36:25.13#ibcon#enter sib2, iclass 35, count 0 2006.201.20:36:25.13#ibcon#flushed, iclass 35, count 0 2006.201.20:36:25.13#ibcon#about to write, iclass 35, count 0 2006.201.20:36:25.13#ibcon#wrote, iclass 35, count 0 2006.201.20:36:25.13#ibcon#about to read 3, iclass 35, count 0 2006.201.20:36:25.15#ibcon#read 3, iclass 35, count 0 2006.201.20:36:25.15#ibcon#about to read 4, iclass 35, count 0 2006.201.20:36:25.15#ibcon#read 4, iclass 35, count 0 2006.201.20:36:25.15#ibcon#about to read 5, iclass 35, count 0 2006.201.20:36:25.15#ibcon#read 5, iclass 35, count 0 2006.201.20:36:25.15#ibcon#about to read 6, iclass 35, count 0 2006.201.20:36:25.15#ibcon#read 6, iclass 35, count 0 2006.201.20:36:25.15#ibcon#end of sib2, iclass 35, count 0 2006.201.20:36:25.15#ibcon#*mode == 0, iclass 35, count 0 2006.201.20:36:25.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.20:36:25.15#ibcon#[27=USB\r\n] 2006.201.20:36:25.15#ibcon#*before write, iclass 35, count 0 2006.201.20:36:25.15#ibcon#enter sib2, iclass 35, count 0 2006.201.20:36:25.15#ibcon#flushed, iclass 35, count 0 2006.201.20:36:25.15#ibcon#about to write, iclass 35, count 0 2006.201.20:36:25.15#ibcon#wrote, iclass 35, count 0 2006.201.20:36:25.15#ibcon#about to read 3, iclass 35, count 0 2006.201.20:36:25.18#ibcon#read 3, iclass 35, count 0 2006.201.20:36:25.18#ibcon#about to read 4, iclass 35, count 0 2006.201.20:36:25.18#ibcon#read 4, iclass 35, count 0 2006.201.20:36:25.18#ibcon#about to read 5, iclass 35, count 0 2006.201.20:36:25.18#ibcon#read 5, iclass 35, count 0 2006.201.20:36:25.18#ibcon#about to read 6, iclass 35, count 0 2006.201.20:36:25.18#ibcon#read 6, iclass 35, count 0 2006.201.20:36:25.18#ibcon#end of sib2, iclass 35, count 0 2006.201.20:36:25.18#ibcon#*after write, iclass 35, count 0 2006.201.20:36:25.18#ibcon#*before return 0, iclass 35, count 0 2006.201.20:36:25.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:25.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.20:36:25.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.20:36:25.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.20:36:25.18$vck44/vblo=6,719.99 2006.201.20:36:25.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.20:36:25.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.20:36:25.18#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:25.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:25.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:25.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:25.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.20:36:25.18#ibcon#first serial, iclass 37, count 0 2006.201.20:36:25.18#ibcon#enter sib2, iclass 37, count 0 2006.201.20:36:25.18#ibcon#flushed, iclass 37, count 0 2006.201.20:36:25.18#ibcon#about to write, iclass 37, count 0 2006.201.20:36:25.18#ibcon#wrote, iclass 37, count 0 2006.201.20:36:25.18#ibcon#about to read 3, iclass 37, count 0 2006.201.20:36:25.20#ibcon#read 3, iclass 37, count 0 2006.201.20:36:25.20#ibcon#about to read 4, iclass 37, count 0 2006.201.20:36:25.20#ibcon#read 4, iclass 37, count 0 2006.201.20:36:25.20#ibcon#about to read 5, iclass 37, count 0 2006.201.20:36:25.20#ibcon#read 5, iclass 37, count 0 2006.201.20:36:25.20#ibcon#about to read 6, iclass 37, count 0 2006.201.20:36:25.20#ibcon#read 6, iclass 37, count 0 2006.201.20:36:25.20#ibcon#end of sib2, iclass 37, count 0 2006.201.20:36:25.20#ibcon#*mode == 0, iclass 37, count 0 2006.201.20:36:25.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.20:36:25.20#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:36:25.20#ibcon#*before write, iclass 37, count 0 2006.201.20:36:25.20#ibcon#enter sib2, iclass 37, count 0 2006.201.20:36:25.20#ibcon#flushed, iclass 37, count 0 2006.201.20:36:25.20#ibcon#about to write, iclass 37, count 0 2006.201.20:36:25.20#ibcon#wrote, iclass 37, count 0 2006.201.20:36:25.20#ibcon#about to read 3, iclass 37, count 0 2006.201.20:36:25.24#ibcon#read 3, iclass 37, count 0 2006.201.20:36:25.24#ibcon#about to read 4, iclass 37, count 0 2006.201.20:36:25.24#ibcon#read 4, iclass 37, count 0 2006.201.20:36:25.24#ibcon#about to read 5, iclass 37, count 0 2006.201.20:36:25.24#ibcon#read 5, iclass 37, count 0 2006.201.20:36:25.24#ibcon#about to read 6, iclass 37, count 0 2006.201.20:36:25.24#ibcon#read 6, iclass 37, count 0 2006.201.20:36:25.24#ibcon#end of sib2, iclass 37, count 0 2006.201.20:36:25.24#ibcon#*after write, iclass 37, count 0 2006.201.20:36:25.24#ibcon#*before return 0, iclass 37, count 0 2006.201.20:36:25.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:25.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.20:36:25.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.20:36:25.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.20:36:25.24$vck44/vb=6,4 2006.201.20:36:25.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.20:36:25.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.20:36:25.24#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:25.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:25.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:25.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:25.30#ibcon#enter wrdev, iclass 39, count 2 2006.201.20:36:25.30#ibcon#first serial, iclass 39, count 2 2006.201.20:36:25.30#ibcon#enter sib2, iclass 39, count 2 2006.201.20:36:25.30#ibcon#flushed, iclass 39, count 2 2006.201.20:36:25.30#ibcon#about to write, iclass 39, count 2 2006.201.20:36:25.30#ibcon#wrote, iclass 39, count 2 2006.201.20:36:25.30#ibcon#about to read 3, iclass 39, count 2 2006.201.20:36:25.32#ibcon#read 3, iclass 39, count 2 2006.201.20:36:25.32#ibcon#about to read 4, iclass 39, count 2 2006.201.20:36:25.32#ibcon#read 4, iclass 39, count 2 2006.201.20:36:25.32#ibcon#about to read 5, iclass 39, count 2 2006.201.20:36:25.32#ibcon#read 5, iclass 39, count 2 2006.201.20:36:25.32#ibcon#about to read 6, iclass 39, count 2 2006.201.20:36:25.32#ibcon#read 6, iclass 39, count 2 2006.201.20:36:25.32#ibcon#end of sib2, iclass 39, count 2 2006.201.20:36:25.32#ibcon#*mode == 0, iclass 39, count 2 2006.201.20:36:25.32#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.20:36:25.32#ibcon#[27=AT06-04\r\n] 2006.201.20:36:25.32#ibcon#*before write, iclass 39, count 2 2006.201.20:36:25.32#ibcon#enter sib2, iclass 39, count 2 2006.201.20:36:25.32#ibcon#flushed, iclass 39, count 2 2006.201.20:36:25.32#ibcon#about to write, iclass 39, count 2 2006.201.20:36:25.32#ibcon#wrote, iclass 39, count 2 2006.201.20:36:25.32#ibcon#about to read 3, iclass 39, count 2 2006.201.20:36:25.35#ibcon#read 3, iclass 39, count 2 2006.201.20:36:25.35#ibcon#about to read 4, iclass 39, count 2 2006.201.20:36:25.35#ibcon#read 4, iclass 39, count 2 2006.201.20:36:25.35#ibcon#about to read 5, iclass 39, count 2 2006.201.20:36:25.35#ibcon#read 5, iclass 39, count 2 2006.201.20:36:25.35#ibcon#about to read 6, iclass 39, count 2 2006.201.20:36:25.35#ibcon#read 6, iclass 39, count 2 2006.201.20:36:25.35#ibcon#end of sib2, iclass 39, count 2 2006.201.20:36:25.35#ibcon#*after write, iclass 39, count 2 2006.201.20:36:25.35#ibcon#*before return 0, iclass 39, count 2 2006.201.20:36:25.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:25.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.20:36:25.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.20:36:25.35#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:25.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:25.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:25.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:25.47#ibcon#enter wrdev, iclass 39, count 0 2006.201.20:36:25.47#ibcon#first serial, iclass 39, count 0 2006.201.20:36:25.47#ibcon#enter sib2, iclass 39, count 0 2006.201.20:36:25.47#ibcon#flushed, iclass 39, count 0 2006.201.20:36:25.47#ibcon#about to write, iclass 39, count 0 2006.201.20:36:25.47#ibcon#wrote, iclass 39, count 0 2006.201.20:36:25.47#ibcon#about to read 3, iclass 39, count 0 2006.201.20:36:25.49#ibcon#read 3, iclass 39, count 0 2006.201.20:36:25.49#ibcon#about to read 4, iclass 39, count 0 2006.201.20:36:25.49#ibcon#read 4, iclass 39, count 0 2006.201.20:36:25.49#ibcon#about to read 5, iclass 39, count 0 2006.201.20:36:25.49#ibcon#read 5, iclass 39, count 0 2006.201.20:36:25.49#ibcon#about to read 6, iclass 39, count 0 2006.201.20:36:25.49#ibcon#read 6, iclass 39, count 0 2006.201.20:36:25.49#ibcon#end of sib2, iclass 39, count 0 2006.201.20:36:25.49#ibcon#*mode == 0, iclass 39, count 0 2006.201.20:36:25.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.20:36:25.49#ibcon#[27=USB\r\n] 2006.201.20:36:25.49#ibcon#*before write, iclass 39, count 0 2006.201.20:36:25.49#ibcon#enter sib2, iclass 39, count 0 2006.201.20:36:25.49#ibcon#flushed, iclass 39, count 0 2006.201.20:36:25.49#ibcon#about to write, iclass 39, count 0 2006.201.20:36:25.49#ibcon#wrote, iclass 39, count 0 2006.201.20:36:25.49#ibcon#about to read 3, iclass 39, count 0 2006.201.20:36:25.52#ibcon#read 3, iclass 39, count 0 2006.201.20:36:25.52#ibcon#about to read 4, iclass 39, count 0 2006.201.20:36:25.52#ibcon#read 4, iclass 39, count 0 2006.201.20:36:25.52#ibcon#about to read 5, iclass 39, count 0 2006.201.20:36:25.52#ibcon#read 5, iclass 39, count 0 2006.201.20:36:25.52#ibcon#about to read 6, iclass 39, count 0 2006.201.20:36:25.52#ibcon#read 6, iclass 39, count 0 2006.201.20:36:25.52#ibcon#end of sib2, iclass 39, count 0 2006.201.20:36:25.52#ibcon#*after write, iclass 39, count 0 2006.201.20:36:25.52#ibcon#*before return 0, iclass 39, count 0 2006.201.20:36:25.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:25.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.20:36:25.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.20:36:25.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.20:36:25.52$vck44/vblo=7,734.99 2006.201.20:36:25.52#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.20:36:25.52#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.20:36:25.52#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:25.52#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:25.52#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:25.52#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:25.52#ibcon#enter wrdev, iclass 2, count 0 2006.201.20:36:25.52#ibcon#first serial, iclass 2, count 0 2006.201.20:36:25.52#ibcon#enter sib2, iclass 2, count 0 2006.201.20:36:25.52#ibcon#flushed, iclass 2, count 0 2006.201.20:36:25.52#ibcon#about to write, iclass 2, count 0 2006.201.20:36:25.52#ibcon#wrote, iclass 2, count 0 2006.201.20:36:25.52#ibcon#about to read 3, iclass 2, count 0 2006.201.20:36:25.54#ibcon#read 3, iclass 2, count 0 2006.201.20:36:25.54#ibcon#about to read 4, iclass 2, count 0 2006.201.20:36:25.54#ibcon#read 4, iclass 2, count 0 2006.201.20:36:25.54#ibcon#about to read 5, iclass 2, count 0 2006.201.20:36:25.54#ibcon#read 5, iclass 2, count 0 2006.201.20:36:25.54#ibcon#about to read 6, iclass 2, count 0 2006.201.20:36:25.54#ibcon#read 6, iclass 2, count 0 2006.201.20:36:25.54#ibcon#end of sib2, iclass 2, count 0 2006.201.20:36:25.54#ibcon#*mode == 0, iclass 2, count 0 2006.201.20:36:25.54#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.20:36:25.54#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:36:25.54#ibcon#*before write, iclass 2, count 0 2006.201.20:36:25.54#ibcon#enter sib2, iclass 2, count 0 2006.201.20:36:25.54#ibcon#flushed, iclass 2, count 0 2006.201.20:36:25.54#ibcon#about to write, iclass 2, count 0 2006.201.20:36:25.54#ibcon#wrote, iclass 2, count 0 2006.201.20:36:25.54#ibcon#about to read 3, iclass 2, count 0 2006.201.20:36:25.59#ibcon#read 3, iclass 2, count 0 2006.201.20:36:25.59#ibcon#about to read 4, iclass 2, count 0 2006.201.20:36:25.59#ibcon#read 4, iclass 2, count 0 2006.201.20:36:25.59#ibcon#about to read 5, iclass 2, count 0 2006.201.20:36:25.59#ibcon#read 5, iclass 2, count 0 2006.201.20:36:25.59#ibcon#about to read 6, iclass 2, count 0 2006.201.20:36:25.59#ibcon#read 6, iclass 2, count 0 2006.201.20:36:25.59#ibcon#end of sib2, iclass 2, count 0 2006.201.20:36:25.59#ibcon#*after write, iclass 2, count 0 2006.201.20:36:25.59#ibcon#*before return 0, iclass 2, count 0 2006.201.20:36:25.59#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:25.59#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.20:36:25.59#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.20:36:25.59#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.20:36:25.59$vck44/vb=7,4 2006.201.20:36:25.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.20:36:25.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.20:36:25.59#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:25.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:25.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:25.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:25.64#ibcon#enter wrdev, iclass 5, count 2 2006.201.20:36:25.64#ibcon#first serial, iclass 5, count 2 2006.201.20:36:25.64#ibcon#enter sib2, iclass 5, count 2 2006.201.20:36:25.64#ibcon#flushed, iclass 5, count 2 2006.201.20:36:25.64#ibcon#about to write, iclass 5, count 2 2006.201.20:36:25.64#ibcon#wrote, iclass 5, count 2 2006.201.20:36:25.64#ibcon#about to read 3, iclass 5, count 2 2006.201.20:36:25.66#ibcon#read 3, iclass 5, count 2 2006.201.20:36:25.66#ibcon#about to read 4, iclass 5, count 2 2006.201.20:36:25.66#ibcon#read 4, iclass 5, count 2 2006.201.20:36:25.66#ibcon#about to read 5, iclass 5, count 2 2006.201.20:36:25.66#ibcon#read 5, iclass 5, count 2 2006.201.20:36:25.66#ibcon#about to read 6, iclass 5, count 2 2006.201.20:36:25.66#ibcon#read 6, iclass 5, count 2 2006.201.20:36:25.66#ibcon#end of sib2, iclass 5, count 2 2006.201.20:36:25.66#ibcon#*mode == 0, iclass 5, count 2 2006.201.20:36:25.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.20:36:25.66#ibcon#[27=AT07-04\r\n] 2006.201.20:36:25.66#ibcon#*before write, iclass 5, count 2 2006.201.20:36:25.66#ibcon#enter sib2, iclass 5, count 2 2006.201.20:36:25.66#ibcon#flushed, iclass 5, count 2 2006.201.20:36:25.66#ibcon#about to write, iclass 5, count 2 2006.201.20:36:25.66#ibcon#wrote, iclass 5, count 2 2006.201.20:36:25.66#ibcon#about to read 3, iclass 5, count 2 2006.201.20:36:25.69#ibcon#read 3, iclass 5, count 2 2006.201.20:36:25.69#ibcon#about to read 4, iclass 5, count 2 2006.201.20:36:25.69#ibcon#read 4, iclass 5, count 2 2006.201.20:36:25.69#ibcon#about to read 5, iclass 5, count 2 2006.201.20:36:25.69#ibcon#read 5, iclass 5, count 2 2006.201.20:36:25.69#ibcon#about to read 6, iclass 5, count 2 2006.201.20:36:25.69#ibcon#read 6, iclass 5, count 2 2006.201.20:36:25.69#ibcon#end of sib2, iclass 5, count 2 2006.201.20:36:25.69#ibcon#*after write, iclass 5, count 2 2006.201.20:36:25.69#ibcon#*before return 0, iclass 5, count 2 2006.201.20:36:25.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:25.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.20:36:25.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.20:36:25.69#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:25.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:25.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:25.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:25.81#ibcon#enter wrdev, iclass 5, count 0 2006.201.20:36:25.81#ibcon#first serial, iclass 5, count 0 2006.201.20:36:25.81#ibcon#enter sib2, iclass 5, count 0 2006.201.20:36:25.81#ibcon#flushed, iclass 5, count 0 2006.201.20:36:25.81#ibcon#about to write, iclass 5, count 0 2006.201.20:36:25.81#ibcon#wrote, iclass 5, count 0 2006.201.20:36:25.81#ibcon#about to read 3, iclass 5, count 0 2006.201.20:36:25.83#ibcon#read 3, iclass 5, count 0 2006.201.20:36:25.83#ibcon#about to read 4, iclass 5, count 0 2006.201.20:36:25.83#ibcon#read 4, iclass 5, count 0 2006.201.20:36:25.83#ibcon#about to read 5, iclass 5, count 0 2006.201.20:36:25.83#ibcon#read 5, iclass 5, count 0 2006.201.20:36:25.83#ibcon#about to read 6, iclass 5, count 0 2006.201.20:36:25.83#ibcon#read 6, iclass 5, count 0 2006.201.20:36:25.83#ibcon#end of sib2, iclass 5, count 0 2006.201.20:36:25.83#ibcon#*mode == 0, iclass 5, count 0 2006.201.20:36:25.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.20:36:25.83#ibcon#[27=USB\r\n] 2006.201.20:36:25.83#ibcon#*before write, iclass 5, count 0 2006.201.20:36:25.83#ibcon#enter sib2, iclass 5, count 0 2006.201.20:36:25.83#ibcon#flushed, iclass 5, count 0 2006.201.20:36:25.83#ibcon#about to write, iclass 5, count 0 2006.201.20:36:25.83#ibcon#wrote, iclass 5, count 0 2006.201.20:36:25.83#ibcon#about to read 3, iclass 5, count 0 2006.201.20:36:25.86#ibcon#read 3, iclass 5, count 0 2006.201.20:36:25.86#ibcon#about to read 4, iclass 5, count 0 2006.201.20:36:25.86#ibcon#read 4, iclass 5, count 0 2006.201.20:36:25.86#ibcon#about to read 5, iclass 5, count 0 2006.201.20:36:25.86#ibcon#read 5, iclass 5, count 0 2006.201.20:36:25.86#ibcon#about to read 6, iclass 5, count 0 2006.201.20:36:25.86#ibcon#read 6, iclass 5, count 0 2006.201.20:36:25.86#ibcon#end of sib2, iclass 5, count 0 2006.201.20:36:25.86#ibcon#*after write, iclass 5, count 0 2006.201.20:36:25.86#ibcon#*before return 0, iclass 5, count 0 2006.201.20:36:25.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:25.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.20:36:25.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.20:36:25.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.20:36:25.86$vck44/vblo=8,744.99 2006.201.20:36:25.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.20:36:25.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.20:36:25.86#ibcon#ireg 17 cls_cnt 0 2006.201.20:36:25.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:25.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:25.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:25.86#ibcon#enter wrdev, iclass 7, count 0 2006.201.20:36:25.86#ibcon#first serial, iclass 7, count 0 2006.201.20:36:25.86#ibcon#enter sib2, iclass 7, count 0 2006.201.20:36:25.86#ibcon#flushed, iclass 7, count 0 2006.201.20:36:25.86#ibcon#about to write, iclass 7, count 0 2006.201.20:36:25.86#ibcon#wrote, iclass 7, count 0 2006.201.20:36:25.86#ibcon#about to read 3, iclass 7, count 0 2006.201.20:36:25.88#ibcon#read 3, iclass 7, count 0 2006.201.20:36:25.88#ibcon#about to read 4, iclass 7, count 0 2006.201.20:36:25.88#ibcon#read 4, iclass 7, count 0 2006.201.20:36:25.88#ibcon#about to read 5, iclass 7, count 0 2006.201.20:36:25.88#ibcon#read 5, iclass 7, count 0 2006.201.20:36:25.88#ibcon#about to read 6, iclass 7, count 0 2006.201.20:36:25.88#ibcon#read 6, iclass 7, count 0 2006.201.20:36:25.88#ibcon#end of sib2, iclass 7, count 0 2006.201.20:36:25.88#ibcon#*mode == 0, iclass 7, count 0 2006.201.20:36:25.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.20:36:25.88#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:36:25.88#ibcon#*before write, iclass 7, count 0 2006.201.20:36:25.88#ibcon#enter sib2, iclass 7, count 0 2006.201.20:36:25.88#ibcon#flushed, iclass 7, count 0 2006.201.20:36:25.88#ibcon#about to write, iclass 7, count 0 2006.201.20:36:25.88#ibcon#wrote, iclass 7, count 0 2006.201.20:36:25.88#ibcon#about to read 3, iclass 7, count 0 2006.201.20:36:25.92#ibcon#read 3, iclass 7, count 0 2006.201.20:36:25.92#ibcon#about to read 4, iclass 7, count 0 2006.201.20:36:25.92#ibcon#read 4, iclass 7, count 0 2006.201.20:36:25.92#ibcon#about to read 5, iclass 7, count 0 2006.201.20:36:25.92#ibcon#read 5, iclass 7, count 0 2006.201.20:36:25.92#ibcon#about to read 6, iclass 7, count 0 2006.201.20:36:25.92#ibcon#read 6, iclass 7, count 0 2006.201.20:36:25.92#ibcon#end of sib2, iclass 7, count 0 2006.201.20:36:25.92#ibcon#*after write, iclass 7, count 0 2006.201.20:36:25.92#ibcon#*before return 0, iclass 7, count 0 2006.201.20:36:25.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:25.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.20:36:25.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.20:36:25.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.20:36:25.92$vck44/vb=8,4 2006.201.20:36:25.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.20:36:25.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.20:36:25.92#ibcon#ireg 11 cls_cnt 2 2006.201.20:36:25.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:25.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:25.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:25.98#ibcon#enter wrdev, iclass 11, count 2 2006.201.20:36:25.98#ibcon#first serial, iclass 11, count 2 2006.201.20:36:25.98#ibcon#enter sib2, iclass 11, count 2 2006.201.20:36:25.98#ibcon#flushed, iclass 11, count 2 2006.201.20:36:25.98#ibcon#about to write, iclass 11, count 2 2006.201.20:36:25.98#ibcon#wrote, iclass 11, count 2 2006.201.20:36:25.98#ibcon#about to read 3, iclass 11, count 2 2006.201.20:36:26.00#ibcon#read 3, iclass 11, count 2 2006.201.20:36:26.00#ibcon#about to read 4, iclass 11, count 2 2006.201.20:36:26.00#ibcon#read 4, iclass 11, count 2 2006.201.20:36:26.00#ibcon#about to read 5, iclass 11, count 2 2006.201.20:36:26.00#ibcon#read 5, iclass 11, count 2 2006.201.20:36:26.00#ibcon#about to read 6, iclass 11, count 2 2006.201.20:36:26.00#ibcon#read 6, iclass 11, count 2 2006.201.20:36:26.00#ibcon#end of sib2, iclass 11, count 2 2006.201.20:36:26.00#ibcon#*mode == 0, iclass 11, count 2 2006.201.20:36:26.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.20:36:26.00#ibcon#[27=AT08-04\r\n] 2006.201.20:36:26.00#ibcon#*before write, iclass 11, count 2 2006.201.20:36:26.00#ibcon#enter sib2, iclass 11, count 2 2006.201.20:36:26.00#ibcon#flushed, iclass 11, count 2 2006.201.20:36:26.00#ibcon#about to write, iclass 11, count 2 2006.201.20:36:26.00#ibcon#wrote, iclass 11, count 2 2006.201.20:36:26.00#ibcon#about to read 3, iclass 11, count 2 2006.201.20:36:26.03#ibcon#read 3, iclass 11, count 2 2006.201.20:36:26.03#ibcon#about to read 4, iclass 11, count 2 2006.201.20:36:26.03#ibcon#read 4, iclass 11, count 2 2006.201.20:36:26.03#ibcon#about to read 5, iclass 11, count 2 2006.201.20:36:26.03#ibcon#read 5, iclass 11, count 2 2006.201.20:36:26.03#ibcon#about to read 6, iclass 11, count 2 2006.201.20:36:26.03#ibcon#read 6, iclass 11, count 2 2006.201.20:36:26.03#ibcon#end of sib2, iclass 11, count 2 2006.201.20:36:26.03#ibcon#*after write, iclass 11, count 2 2006.201.20:36:26.03#ibcon#*before return 0, iclass 11, count 2 2006.201.20:36:26.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:26.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.20:36:26.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.20:36:26.03#ibcon#ireg 7 cls_cnt 0 2006.201.20:36:26.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:26.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:26.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:26.15#ibcon#enter wrdev, iclass 11, count 0 2006.201.20:36:26.15#ibcon#first serial, iclass 11, count 0 2006.201.20:36:26.15#ibcon#enter sib2, iclass 11, count 0 2006.201.20:36:26.15#ibcon#flushed, iclass 11, count 0 2006.201.20:36:26.15#ibcon#about to write, iclass 11, count 0 2006.201.20:36:26.15#ibcon#wrote, iclass 11, count 0 2006.201.20:36:26.15#ibcon#about to read 3, iclass 11, count 0 2006.201.20:36:26.17#ibcon#read 3, iclass 11, count 0 2006.201.20:36:26.17#ibcon#about to read 4, iclass 11, count 0 2006.201.20:36:26.17#ibcon#read 4, iclass 11, count 0 2006.201.20:36:26.17#ibcon#about to read 5, iclass 11, count 0 2006.201.20:36:26.17#ibcon#read 5, iclass 11, count 0 2006.201.20:36:26.17#ibcon#about to read 6, iclass 11, count 0 2006.201.20:36:26.17#ibcon#read 6, iclass 11, count 0 2006.201.20:36:26.17#ibcon#end of sib2, iclass 11, count 0 2006.201.20:36:26.17#ibcon#*mode == 0, iclass 11, count 0 2006.201.20:36:26.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.20:36:26.17#ibcon#[27=USB\r\n] 2006.201.20:36:26.17#ibcon#*before write, iclass 11, count 0 2006.201.20:36:26.17#ibcon#enter sib2, iclass 11, count 0 2006.201.20:36:26.17#ibcon#flushed, iclass 11, count 0 2006.201.20:36:26.17#ibcon#about to write, iclass 11, count 0 2006.201.20:36:26.17#ibcon#wrote, iclass 11, count 0 2006.201.20:36:26.17#ibcon#about to read 3, iclass 11, count 0 2006.201.20:36:26.20#ibcon#read 3, iclass 11, count 0 2006.201.20:36:26.20#ibcon#about to read 4, iclass 11, count 0 2006.201.20:36:26.20#ibcon#read 4, iclass 11, count 0 2006.201.20:36:26.20#ibcon#about to read 5, iclass 11, count 0 2006.201.20:36:26.20#ibcon#read 5, iclass 11, count 0 2006.201.20:36:26.20#ibcon#about to read 6, iclass 11, count 0 2006.201.20:36:26.20#ibcon#read 6, iclass 11, count 0 2006.201.20:36:26.20#ibcon#end of sib2, iclass 11, count 0 2006.201.20:36:26.20#ibcon#*after write, iclass 11, count 0 2006.201.20:36:26.20#ibcon#*before return 0, iclass 11, count 0 2006.201.20:36:26.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:26.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.20:36:26.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.20:36:26.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.20:36:26.20$vck44/vabw=wide 2006.201.20:36:26.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.20:36:26.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.20:36:26.20#ibcon#ireg 8 cls_cnt 0 2006.201.20:36:26.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:26.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:26.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:26.20#ibcon#enter wrdev, iclass 13, count 0 2006.201.20:36:26.20#ibcon#first serial, iclass 13, count 0 2006.201.20:36:26.20#ibcon#enter sib2, iclass 13, count 0 2006.201.20:36:26.20#ibcon#flushed, iclass 13, count 0 2006.201.20:36:26.20#ibcon#about to write, iclass 13, count 0 2006.201.20:36:26.20#ibcon#wrote, iclass 13, count 0 2006.201.20:36:26.20#ibcon#about to read 3, iclass 13, count 0 2006.201.20:36:26.22#ibcon#read 3, iclass 13, count 0 2006.201.20:36:26.22#ibcon#about to read 4, iclass 13, count 0 2006.201.20:36:26.22#ibcon#read 4, iclass 13, count 0 2006.201.20:36:26.22#ibcon#about to read 5, iclass 13, count 0 2006.201.20:36:26.22#ibcon#read 5, iclass 13, count 0 2006.201.20:36:26.22#ibcon#about to read 6, iclass 13, count 0 2006.201.20:36:26.22#ibcon#read 6, iclass 13, count 0 2006.201.20:36:26.22#ibcon#end of sib2, iclass 13, count 0 2006.201.20:36:26.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.20:36:26.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.20:36:26.22#ibcon#[25=BW32\r\n] 2006.201.20:36:26.22#ibcon#*before write, iclass 13, count 0 2006.201.20:36:26.22#ibcon#enter sib2, iclass 13, count 0 2006.201.20:36:26.22#ibcon#flushed, iclass 13, count 0 2006.201.20:36:26.22#ibcon#about to write, iclass 13, count 0 2006.201.20:36:26.22#ibcon#wrote, iclass 13, count 0 2006.201.20:36:26.22#ibcon#about to read 3, iclass 13, count 0 2006.201.20:36:26.25#ibcon#read 3, iclass 13, count 0 2006.201.20:36:26.25#ibcon#about to read 4, iclass 13, count 0 2006.201.20:36:26.25#ibcon#read 4, iclass 13, count 0 2006.201.20:36:26.25#ibcon#about to read 5, iclass 13, count 0 2006.201.20:36:26.25#ibcon#read 5, iclass 13, count 0 2006.201.20:36:26.25#ibcon#about to read 6, iclass 13, count 0 2006.201.20:36:26.25#ibcon#read 6, iclass 13, count 0 2006.201.20:36:26.25#ibcon#end of sib2, iclass 13, count 0 2006.201.20:36:26.25#ibcon#*after write, iclass 13, count 0 2006.201.20:36:26.25#ibcon#*before return 0, iclass 13, count 0 2006.201.20:36:26.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:26.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.20:36:26.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.20:36:26.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.20:36:26.25$vck44/vbbw=wide 2006.201.20:36:26.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.20:36:26.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.20:36:26.25#ibcon#ireg 8 cls_cnt 0 2006.201.20:36:26.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:36:26.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:36:26.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:36:26.32#ibcon#enter wrdev, iclass 15, count 0 2006.201.20:36:26.32#ibcon#first serial, iclass 15, count 0 2006.201.20:36:26.32#ibcon#enter sib2, iclass 15, count 0 2006.201.20:36:26.32#ibcon#flushed, iclass 15, count 0 2006.201.20:36:26.32#ibcon#about to write, iclass 15, count 0 2006.201.20:36:26.32#ibcon#wrote, iclass 15, count 0 2006.201.20:36:26.32#ibcon#about to read 3, iclass 15, count 0 2006.201.20:36:26.34#ibcon#read 3, iclass 15, count 0 2006.201.20:36:26.34#ibcon#about to read 4, iclass 15, count 0 2006.201.20:36:26.34#ibcon#read 4, iclass 15, count 0 2006.201.20:36:26.34#ibcon#about to read 5, iclass 15, count 0 2006.201.20:36:26.34#ibcon#read 5, iclass 15, count 0 2006.201.20:36:26.34#ibcon#about to read 6, iclass 15, count 0 2006.201.20:36:26.34#ibcon#read 6, iclass 15, count 0 2006.201.20:36:26.34#ibcon#end of sib2, iclass 15, count 0 2006.201.20:36:26.34#ibcon#*mode == 0, iclass 15, count 0 2006.201.20:36:26.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.20:36:26.34#ibcon#[27=BW32\r\n] 2006.201.20:36:26.34#ibcon#*before write, iclass 15, count 0 2006.201.20:36:26.34#ibcon#enter sib2, iclass 15, count 0 2006.201.20:36:26.34#ibcon#flushed, iclass 15, count 0 2006.201.20:36:26.34#ibcon#about to write, iclass 15, count 0 2006.201.20:36:26.34#ibcon#wrote, iclass 15, count 0 2006.201.20:36:26.34#ibcon#about to read 3, iclass 15, count 0 2006.201.20:36:26.36#abcon#<5=/04 0.9 2.3 20.101001002.3\r\n> 2006.201.20:36:26.37#ibcon#read 3, iclass 15, count 0 2006.201.20:36:26.37#ibcon#about to read 4, iclass 15, count 0 2006.201.20:36:26.37#ibcon#read 4, iclass 15, count 0 2006.201.20:36:26.37#ibcon#about to read 5, iclass 15, count 0 2006.201.20:36:26.37#ibcon#read 5, iclass 15, count 0 2006.201.20:36:26.37#ibcon#about to read 6, iclass 15, count 0 2006.201.20:36:26.37#ibcon#read 6, iclass 15, count 0 2006.201.20:36:26.37#ibcon#end of sib2, iclass 15, count 0 2006.201.20:36:26.37#ibcon#*after write, iclass 15, count 0 2006.201.20:36:26.37#ibcon#*before return 0, iclass 15, count 0 2006.201.20:36:26.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:36:26.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:36:26.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.20:36:26.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.20:36:26.37$setupk4/ifdk4 2006.201.20:36:26.37$ifdk4/lo= 2006.201.20:36:26.37$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:36:26.37$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:36:26.37$ifdk4/patch= 2006.201.20:36:26.37$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:36:26.37$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:36:26.37$setupk4/!*+20s 2006.201.20:36:26.38#abcon#{5=INTERFACE CLEAR} 2006.201.20:36:26.44#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:36:33.14#trakl#Source acquired 2006.201.20:36:34.14#flagr#flagr/antenna,acquired 2006.201.20:36:36.53#abcon#<5=/04 0.9 2.2 20.101001002.3\r\n> 2006.201.20:36:36.55#abcon#{5=INTERFACE CLEAR} 2006.201.20:36:36.61#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:36:40.86$setupk4/"tpicd 2006.201.20:36:40.86$setupk4/echo=off 2006.201.20:36:40.86$setupk4/xlog=off 2006.201.20:36:40.86:!2006.201.20:38:48 2006.201.20:38:48.00:preob 2006.201.20:38:48.14/onsource/TRACKING 2006.201.20:38:48.14:!2006.201.20:38:58 2006.201.20:38:58.00:"tape 2006.201.20:38:58.00:"st=record 2006.201.20:38:58.00:data_valid=on 2006.201.20:38:58.00:midob 2006.201.20:38:58.14/onsource/TRACKING 2006.201.20:38:58.14/wx/20.11,1002.3,100 2006.201.20:38:58.28/cable/+6.4809E-03 2006.201.20:38:59.37/va/01,08,usb,yes,50,53 2006.201.20:38:59.37/va/02,07,usb,yes,53,55 2006.201.20:38:59.37/va/03,08,usb,yes,49,51 2006.201.20:38:59.37/va/04,07,usb,yes,55,58 2006.201.20:38:59.37/va/05,04,usb,yes,49,51 2006.201.20:38:59.37/va/06,05,usb,yes,50,50 2006.201.20:38:59.37/va/07,05,usb,yes,49,50 2006.201.20:38:59.37/va/08,04,usb,yes,48,57 2006.201.20:38:59.60/valo/01,524.99,yes,locked 2006.201.20:38:59.60/valo/02,534.99,yes,locked 2006.201.20:38:59.60/valo/03,564.99,yes,locked 2006.201.20:38:59.60/valo/04,624.99,yes,locked 2006.201.20:38:59.60/valo/05,734.99,yes,locked 2006.201.20:38:59.60/valo/06,814.99,yes,locked 2006.201.20:38:59.60/valo/07,864.99,yes,locked 2006.201.20:38:59.60/valo/08,884.99,yes,locked 2006.201.20:39:00.69/vb/01,04,usb,yes,31,29 2006.201.20:39:00.69/vb/02,05,usb,yes,29,29 2006.201.20:39:00.69/vb/03,04,usb,yes,31,33 2006.201.20:39:00.69/vb/04,05,usb,yes,31,30 2006.201.20:39:00.69/vb/05,04,usb,yes,27,30 2006.201.20:39:00.69/vb/06,04,usb,yes,32,28 2006.201.20:39:00.69/vb/07,04,usb,yes,32,31 2006.201.20:39:00.69/vb/08,04,usb,yes,29,33 2006.201.20:39:00.93/vblo/01,629.99,yes,locked 2006.201.20:39:00.93/vblo/02,634.99,yes,locked 2006.201.20:39:00.93/vblo/03,649.99,yes,locked 2006.201.20:39:00.93/vblo/04,679.99,yes,locked 2006.201.20:39:00.93/vblo/05,709.99,yes,locked 2006.201.20:39:00.93/vblo/06,719.99,yes,locked 2006.201.20:39:00.93/vblo/07,734.99,yes,locked 2006.201.20:39:00.93/vblo/08,744.99,yes,locked 2006.201.20:39:01.08/vabw/8 2006.201.20:39:01.23/vbbw/8 2006.201.20:39:01.32/xfe/off,on,16.5 2006.201.20:39:01.71/ifatt/23,28,28,28 2006.201.20:39:02.06/fmout-gps/S +4.57E-07 2006.201.20:39:02.13:!2006.201.20:39:38 2006.201.20:39:38.00:data_valid=off 2006.201.20:39:38.00:"et 2006.201.20:39:38.00:!+3s 2006.201.20:39:41.02:"tape 2006.201.20:39:41.02:postob 2006.201.20:39:41.10/cable/+6.4815E-03 2006.201.20:39:41.10/wx/20.11,1002.3,100 2006.201.20:39:41.17/fmout-gps/S +4.56E-07 2006.201.20:39:41.17:scan_name=201-2042,jd0607,90 2006.201.20:39:41.18:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.201.20:39:43.14#flagr#flagr/antenna,new-source 2006.201.20:39:43.14:checkk5 2006.201.20:39:43.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:39:43.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:39:44.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:39:44.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:39:45.01/chk_obsdata//k5ts1/T2012038??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.20:39:45.38/chk_obsdata//k5ts2/T2012038??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.20:39:45.75/chk_obsdata//k5ts3/T2012038??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.20:39:46.12/chk_obsdata//k5ts4/T2012038??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.20:39:46.81/k5log//k5ts1_log_newline 2006.201.20:39:47.50/k5log//k5ts2_log_newline 2006.201.20:39:48.21/k5log//k5ts3_log_newline 2006.201.20:39:48.89/k5log//k5ts4_log_newline 2006.201.20:39:48.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:39:48.91:setupk4=1 2006.201.20:39:48.91$setupk4/echo=on 2006.201.20:39:48.91$setupk4/pcalon 2006.201.20:39:48.91$pcalon/"no phase cal control is implemented here 2006.201.20:39:48.91$setupk4/"tpicd=stop 2006.201.20:39:48.91$setupk4/"rec=synch_on 2006.201.20:39:48.91$setupk4/"rec_mode=128 2006.201.20:39:48.91$setupk4/!* 2006.201.20:39:48.91$setupk4/recpk4 2006.201.20:39:48.91$recpk4/recpatch= 2006.201.20:39:48.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:39:48.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:39:48.92$setupk4/vck44 2006.201.20:39:48.92$vck44/valo=1,524.99 2006.201.20:39:48.92#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.20:39:48.92#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.20:39:48.92#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:48.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:48.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:48.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:48.92#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:39:48.92#ibcon#first serial, iclass 28, count 0 2006.201.20:39:48.92#ibcon#enter sib2, iclass 28, count 0 2006.201.20:39:48.92#ibcon#flushed, iclass 28, count 0 2006.201.20:39:48.92#ibcon#about to write, iclass 28, count 0 2006.201.20:39:48.92#ibcon#wrote, iclass 28, count 0 2006.201.20:39:48.92#ibcon#about to read 3, iclass 28, count 0 2006.201.20:39:48.95#ibcon#read 3, iclass 28, count 0 2006.201.20:39:48.95#ibcon#about to read 4, iclass 28, count 0 2006.201.20:39:48.95#ibcon#read 4, iclass 28, count 0 2006.201.20:39:48.95#ibcon#about to read 5, iclass 28, count 0 2006.201.20:39:48.95#ibcon#read 5, iclass 28, count 0 2006.201.20:39:48.95#ibcon#about to read 6, iclass 28, count 0 2006.201.20:39:48.95#ibcon#read 6, iclass 28, count 0 2006.201.20:39:48.95#ibcon#end of sib2, iclass 28, count 0 2006.201.20:39:48.95#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:39:48.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:39:48.95#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:39:48.95#ibcon#*before write, iclass 28, count 0 2006.201.20:39:48.95#ibcon#enter sib2, iclass 28, count 0 2006.201.20:39:48.95#ibcon#flushed, iclass 28, count 0 2006.201.20:39:48.95#ibcon#about to write, iclass 28, count 0 2006.201.20:39:48.95#ibcon#wrote, iclass 28, count 0 2006.201.20:39:48.95#ibcon#about to read 3, iclass 28, count 0 2006.201.20:39:49.00#ibcon#read 3, iclass 28, count 0 2006.201.20:39:49.00#ibcon#about to read 4, iclass 28, count 0 2006.201.20:39:49.00#ibcon#read 4, iclass 28, count 0 2006.201.20:39:49.00#ibcon#about to read 5, iclass 28, count 0 2006.201.20:39:49.00#ibcon#read 5, iclass 28, count 0 2006.201.20:39:49.00#ibcon#about to read 6, iclass 28, count 0 2006.201.20:39:49.00#ibcon#read 6, iclass 28, count 0 2006.201.20:39:49.00#ibcon#end of sib2, iclass 28, count 0 2006.201.20:39:49.00#ibcon#*after write, iclass 28, count 0 2006.201.20:39:49.00#ibcon#*before return 0, iclass 28, count 0 2006.201.20:39:49.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:49.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:49.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:39:49.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:39:49.00$vck44/va=1,8 2006.201.20:39:49.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.20:39:49.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.20:39:49.00#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:49.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:49.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:49.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:49.00#ibcon#enter wrdev, iclass 30, count 2 2006.201.20:39:49.00#ibcon#first serial, iclass 30, count 2 2006.201.20:39:49.00#ibcon#enter sib2, iclass 30, count 2 2006.201.20:39:49.00#ibcon#flushed, iclass 30, count 2 2006.201.20:39:49.00#ibcon#about to write, iclass 30, count 2 2006.201.20:39:49.00#ibcon#wrote, iclass 30, count 2 2006.201.20:39:49.00#ibcon#about to read 3, iclass 30, count 2 2006.201.20:39:49.02#ibcon#read 3, iclass 30, count 2 2006.201.20:39:49.02#ibcon#about to read 4, iclass 30, count 2 2006.201.20:39:49.02#ibcon#read 4, iclass 30, count 2 2006.201.20:39:49.02#ibcon#about to read 5, iclass 30, count 2 2006.201.20:39:49.02#ibcon#read 5, iclass 30, count 2 2006.201.20:39:49.02#ibcon#about to read 6, iclass 30, count 2 2006.201.20:39:49.02#ibcon#read 6, iclass 30, count 2 2006.201.20:39:49.02#ibcon#end of sib2, iclass 30, count 2 2006.201.20:39:49.02#ibcon#*mode == 0, iclass 30, count 2 2006.201.20:39:49.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.20:39:49.02#ibcon#[25=AT01-08\r\n] 2006.201.20:39:49.02#ibcon#*before write, iclass 30, count 2 2006.201.20:39:49.02#ibcon#enter sib2, iclass 30, count 2 2006.201.20:39:49.02#ibcon#flushed, iclass 30, count 2 2006.201.20:39:49.02#ibcon#about to write, iclass 30, count 2 2006.201.20:39:49.02#ibcon#wrote, iclass 30, count 2 2006.201.20:39:49.02#ibcon#about to read 3, iclass 30, count 2 2006.201.20:39:49.05#ibcon#read 3, iclass 30, count 2 2006.201.20:39:49.05#ibcon#about to read 4, iclass 30, count 2 2006.201.20:39:49.05#ibcon#read 4, iclass 30, count 2 2006.201.20:39:49.05#ibcon#about to read 5, iclass 30, count 2 2006.201.20:39:49.05#ibcon#read 5, iclass 30, count 2 2006.201.20:39:49.05#ibcon#about to read 6, iclass 30, count 2 2006.201.20:39:49.05#ibcon#read 6, iclass 30, count 2 2006.201.20:39:49.05#ibcon#end of sib2, iclass 30, count 2 2006.201.20:39:49.05#ibcon#*after write, iclass 30, count 2 2006.201.20:39:49.05#ibcon#*before return 0, iclass 30, count 2 2006.201.20:39:49.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:49.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:49.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.20:39:49.05#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:49.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:49.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:49.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:49.17#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:39:49.17#ibcon#first serial, iclass 30, count 0 2006.201.20:39:49.17#ibcon#enter sib2, iclass 30, count 0 2006.201.20:39:49.17#ibcon#flushed, iclass 30, count 0 2006.201.20:39:49.17#ibcon#about to write, iclass 30, count 0 2006.201.20:39:49.17#ibcon#wrote, iclass 30, count 0 2006.201.20:39:49.17#ibcon#about to read 3, iclass 30, count 0 2006.201.20:39:49.19#ibcon#read 3, iclass 30, count 0 2006.201.20:39:49.19#ibcon#about to read 4, iclass 30, count 0 2006.201.20:39:49.19#ibcon#read 4, iclass 30, count 0 2006.201.20:39:49.19#ibcon#about to read 5, iclass 30, count 0 2006.201.20:39:49.19#ibcon#read 5, iclass 30, count 0 2006.201.20:39:49.19#ibcon#about to read 6, iclass 30, count 0 2006.201.20:39:49.19#ibcon#read 6, iclass 30, count 0 2006.201.20:39:49.19#ibcon#end of sib2, iclass 30, count 0 2006.201.20:39:49.19#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:39:49.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:39:49.19#ibcon#[25=USB\r\n] 2006.201.20:39:49.19#ibcon#*before write, iclass 30, count 0 2006.201.20:39:49.19#ibcon#enter sib2, iclass 30, count 0 2006.201.20:39:49.19#ibcon#flushed, iclass 30, count 0 2006.201.20:39:49.19#ibcon#about to write, iclass 30, count 0 2006.201.20:39:49.19#ibcon#wrote, iclass 30, count 0 2006.201.20:39:49.19#ibcon#about to read 3, iclass 30, count 0 2006.201.20:39:49.22#ibcon#read 3, iclass 30, count 0 2006.201.20:39:49.22#ibcon#about to read 4, iclass 30, count 0 2006.201.20:39:49.22#ibcon#read 4, iclass 30, count 0 2006.201.20:39:49.22#ibcon#about to read 5, iclass 30, count 0 2006.201.20:39:49.22#ibcon#read 5, iclass 30, count 0 2006.201.20:39:49.22#ibcon#about to read 6, iclass 30, count 0 2006.201.20:39:49.22#ibcon#read 6, iclass 30, count 0 2006.201.20:39:49.22#ibcon#end of sib2, iclass 30, count 0 2006.201.20:39:49.22#ibcon#*after write, iclass 30, count 0 2006.201.20:39:49.22#ibcon#*before return 0, iclass 30, count 0 2006.201.20:39:49.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:49.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:49.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:39:49.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:39:49.22$vck44/valo=2,534.99 2006.201.20:39:49.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.20:39:49.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.20:39:49.22#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:49.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:49.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:49.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:49.22#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:39:49.22#ibcon#first serial, iclass 32, count 0 2006.201.20:39:49.22#ibcon#enter sib2, iclass 32, count 0 2006.201.20:39:49.22#ibcon#flushed, iclass 32, count 0 2006.201.20:39:49.22#ibcon#about to write, iclass 32, count 0 2006.201.20:39:49.22#ibcon#wrote, iclass 32, count 0 2006.201.20:39:49.22#ibcon#about to read 3, iclass 32, count 0 2006.201.20:39:49.24#ibcon#read 3, iclass 32, count 0 2006.201.20:39:49.24#ibcon#about to read 4, iclass 32, count 0 2006.201.20:39:49.24#ibcon#read 4, iclass 32, count 0 2006.201.20:39:49.24#ibcon#about to read 5, iclass 32, count 0 2006.201.20:39:49.24#ibcon#read 5, iclass 32, count 0 2006.201.20:39:49.24#ibcon#about to read 6, iclass 32, count 0 2006.201.20:39:49.24#ibcon#read 6, iclass 32, count 0 2006.201.20:39:49.24#ibcon#end of sib2, iclass 32, count 0 2006.201.20:39:49.24#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:39:49.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:39:49.24#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:39:49.24#ibcon#*before write, iclass 32, count 0 2006.201.20:39:49.24#ibcon#enter sib2, iclass 32, count 0 2006.201.20:39:49.24#ibcon#flushed, iclass 32, count 0 2006.201.20:39:49.24#ibcon#about to write, iclass 32, count 0 2006.201.20:39:49.24#ibcon#wrote, iclass 32, count 0 2006.201.20:39:49.24#ibcon#about to read 3, iclass 32, count 0 2006.201.20:39:49.28#ibcon#read 3, iclass 32, count 0 2006.201.20:39:49.28#ibcon#about to read 4, iclass 32, count 0 2006.201.20:39:49.28#ibcon#read 4, iclass 32, count 0 2006.201.20:39:49.28#ibcon#about to read 5, iclass 32, count 0 2006.201.20:39:49.28#ibcon#read 5, iclass 32, count 0 2006.201.20:39:49.28#ibcon#about to read 6, iclass 32, count 0 2006.201.20:39:49.28#ibcon#read 6, iclass 32, count 0 2006.201.20:39:49.28#ibcon#end of sib2, iclass 32, count 0 2006.201.20:39:49.28#ibcon#*after write, iclass 32, count 0 2006.201.20:39:49.28#ibcon#*before return 0, iclass 32, count 0 2006.201.20:39:49.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:49.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:49.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:39:49.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:39:49.28$vck44/va=2,7 2006.201.20:39:49.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.20:39:49.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.20:39:49.28#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:49.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:49.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:49.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:49.34#ibcon#enter wrdev, iclass 34, count 2 2006.201.20:39:49.34#ibcon#first serial, iclass 34, count 2 2006.201.20:39:49.34#ibcon#enter sib2, iclass 34, count 2 2006.201.20:39:49.34#ibcon#flushed, iclass 34, count 2 2006.201.20:39:49.34#ibcon#about to write, iclass 34, count 2 2006.201.20:39:49.34#ibcon#wrote, iclass 34, count 2 2006.201.20:39:49.34#ibcon#about to read 3, iclass 34, count 2 2006.201.20:39:49.36#ibcon#read 3, iclass 34, count 2 2006.201.20:39:49.36#ibcon#about to read 4, iclass 34, count 2 2006.201.20:39:49.36#ibcon#read 4, iclass 34, count 2 2006.201.20:39:49.36#ibcon#about to read 5, iclass 34, count 2 2006.201.20:39:49.36#ibcon#read 5, iclass 34, count 2 2006.201.20:39:49.36#ibcon#about to read 6, iclass 34, count 2 2006.201.20:39:49.36#ibcon#read 6, iclass 34, count 2 2006.201.20:39:49.36#ibcon#end of sib2, iclass 34, count 2 2006.201.20:39:49.36#ibcon#*mode == 0, iclass 34, count 2 2006.201.20:39:49.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.20:39:49.36#ibcon#[25=AT02-07\r\n] 2006.201.20:39:49.36#ibcon#*before write, iclass 34, count 2 2006.201.20:39:49.36#ibcon#enter sib2, iclass 34, count 2 2006.201.20:39:49.36#ibcon#flushed, iclass 34, count 2 2006.201.20:39:49.36#ibcon#about to write, iclass 34, count 2 2006.201.20:39:49.36#ibcon#wrote, iclass 34, count 2 2006.201.20:39:49.36#ibcon#about to read 3, iclass 34, count 2 2006.201.20:39:49.39#ibcon#read 3, iclass 34, count 2 2006.201.20:39:49.39#ibcon#about to read 4, iclass 34, count 2 2006.201.20:39:49.39#ibcon#read 4, iclass 34, count 2 2006.201.20:39:49.39#ibcon#about to read 5, iclass 34, count 2 2006.201.20:39:49.39#ibcon#read 5, iclass 34, count 2 2006.201.20:39:49.39#ibcon#about to read 6, iclass 34, count 2 2006.201.20:39:49.39#ibcon#read 6, iclass 34, count 2 2006.201.20:39:49.39#ibcon#end of sib2, iclass 34, count 2 2006.201.20:39:49.39#ibcon#*after write, iclass 34, count 2 2006.201.20:39:49.39#ibcon#*before return 0, iclass 34, count 2 2006.201.20:39:49.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:49.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:49.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.20:39:49.39#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:49.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:49.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:49.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:49.51#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:39:49.51#ibcon#first serial, iclass 34, count 0 2006.201.20:39:49.51#ibcon#enter sib2, iclass 34, count 0 2006.201.20:39:49.51#ibcon#flushed, iclass 34, count 0 2006.201.20:39:49.51#ibcon#about to write, iclass 34, count 0 2006.201.20:39:49.51#ibcon#wrote, iclass 34, count 0 2006.201.20:39:49.51#ibcon#about to read 3, iclass 34, count 0 2006.201.20:39:49.53#ibcon#read 3, iclass 34, count 0 2006.201.20:39:49.53#ibcon#about to read 4, iclass 34, count 0 2006.201.20:39:49.53#ibcon#read 4, iclass 34, count 0 2006.201.20:39:49.53#ibcon#about to read 5, iclass 34, count 0 2006.201.20:39:49.53#ibcon#read 5, iclass 34, count 0 2006.201.20:39:49.53#ibcon#about to read 6, iclass 34, count 0 2006.201.20:39:49.53#ibcon#read 6, iclass 34, count 0 2006.201.20:39:49.53#ibcon#end of sib2, iclass 34, count 0 2006.201.20:39:49.53#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:39:49.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:39:49.53#ibcon#[25=USB\r\n] 2006.201.20:39:49.53#ibcon#*before write, iclass 34, count 0 2006.201.20:39:49.53#ibcon#enter sib2, iclass 34, count 0 2006.201.20:39:49.53#ibcon#flushed, iclass 34, count 0 2006.201.20:39:49.53#ibcon#about to write, iclass 34, count 0 2006.201.20:39:49.53#ibcon#wrote, iclass 34, count 0 2006.201.20:39:49.53#ibcon#about to read 3, iclass 34, count 0 2006.201.20:39:49.56#ibcon#read 3, iclass 34, count 0 2006.201.20:39:49.56#ibcon#about to read 4, iclass 34, count 0 2006.201.20:39:49.56#ibcon#read 4, iclass 34, count 0 2006.201.20:39:49.56#ibcon#about to read 5, iclass 34, count 0 2006.201.20:39:49.56#ibcon#read 5, iclass 34, count 0 2006.201.20:39:49.56#ibcon#about to read 6, iclass 34, count 0 2006.201.20:39:49.56#ibcon#read 6, iclass 34, count 0 2006.201.20:39:49.56#ibcon#end of sib2, iclass 34, count 0 2006.201.20:39:49.56#ibcon#*after write, iclass 34, count 0 2006.201.20:39:49.56#ibcon#*before return 0, iclass 34, count 0 2006.201.20:39:49.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:49.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:49.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:39:49.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:39:49.56$vck44/valo=3,564.99 2006.201.20:39:49.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.20:39:49.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.20:39:49.56#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:49.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:49.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:49.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:49.56#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:39:49.56#ibcon#first serial, iclass 36, count 0 2006.201.20:39:49.56#ibcon#enter sib2, iclass 36, count 0 2006.201.20:39:49.56#ibcon#flushed, iclass 36, count 0 2006.201.20:39:49.56#ibcon#about to write, iclass 36, count 0 2006.201.20:39:49.56#ibcon#wrote, iclass 36, count 0 2006.201.20:39:49.56#ibcon#about to read 3, iclass 36, count 0 2006.201.20:39:49.58#ibcon#read 3, iclass 36, count 0 2006.201.20:39:49.58#ibcon#about to read 4, iclass 36, count 0 2006.201.20:39:49.58#ibcon#read 4, iclass 36, count 0 2006.201.20:39:49.58#ibcon#about to read 5, iclass 36, count 0 2006.201.20:39:49.58#ibcon#read 5, iclass 36, count 0 2006.201.20:39:49.58#ibcon#about to read 6, iclass 36, count 0 2006.201.20:39:49.58#ibcon#read 6, iclass 36, count 0 2006.201.20:39:49.58#ibcon#end of sib2, iclass 36, count 0 2006.201.20:39:49.58#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:39:49.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:39:49.58#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:39:49.58#ibcon#*before write, iclass 36, count 0 2006.201.20:39:49.58#ibcon#enter sib2, iclass 36, count 0 2006.201.20:39:49.58#ibcon#flushed, iclass 36, count 0 2006.201.20:39:49.58#ibcon#about to write, iclass 36, count 0 2006.201.20:39:49.58#ibcon#wrote, iclass 36, count 0 2006.201.20:39:49.58#ibcon#about to read 3, iclass 36, count 0 2006.201.20:39:49.62#ibcon#read 3, iclass 36, count 0 2006.201.20:39:49.62#ibcon#about to read 4, iclass 36, count 0 2006.201.20:39:49.62#ibcon#read 4, iclass 36, count 0 2006.201.20:39:49.62#ibcon#about to read 5, iclass 36, count 0 2006.201.20:39:49.62#ibcon#read 5, iclass 36, count 0 2006.201.20:39:49.62#ibcon#about to read 6, iclass 36, count 0 2006.201.20:39:49.62#ibcon#read 6, iclass 36, count 0 2006.201.20:39:49.62#ibcon#end of sib2, iclass 36, count 0 2006.201.20:39:49.62#ibcon#*after write, iclass 36, count 0 2006.201.20:39:49.62#ibcon#*before return 0, iclass 36, count 0 2006.201.20:39:49.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:49.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:49.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:39:49.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:39:49.62$vck44/va=3,8 2006.201.20:39:49.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.20:39:49.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.20:39:49.62#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:49.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:49.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:49.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:49.68#ibcon#enter wrdev, iclass 38, count 2 2006.201.20:39:49.68#ibcon#first serial, iclass 38, count 2 2006.201.20:39:49.68#ibcon#enter sib2, iclass 38, count 2 2006.201.20:39:49.68#ibcon#flushed, iclass 38, count 2 2006.201.20:39:49.68#ibcon#about to write, iclass 38, count 2 2006.201.20:39:49.68#ibcon#wrote, iclass 38, count 2 2006.201.20:39:49.68#ibcon#about to read 3, iclass 38, count 2 2006.201.20:39:49.70#ibcon#read 3, iclass 38, count 2 2006.201.20:39:49.70#ibcon#about to read 4, iclass 38, count 2 2006.201.20:39:49.70#ibcon#read 4, iclass 38, count 2 2006.201.20:39:49.70#ibcon#about to read 5, iclass 38, count 2 2006.201.20:39:49.70#ibcon#read 5, iclass 38, count 2 2006.201.20:39:49.70#ibcon#about to read 6, iclass 38, count 2 2006.201.20:39:49.70#ibcon#read 6, iclass 38, count 2 2006.201.20:39:49.70#ibcon#end of sib2, iclass 38, count 2 2006.201.20:39:49.70#ibcon#*mode == 0, iclass 38, count 2 2006.201.20:39:49.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.20:39:49.70#ibcon#[25=AT03-08\r\n] 2006.201.20:39:49.70#ibcon#*before write, iclass 38, count 2 2006.201.20:39:49.70#ibcon#enter sib2, iclass 38, count 2 2006.201.20:39:49.70#ibcon#flushed, iclass 38, count 2 2006.201.20:39:49.70#ibcon#about to write, iclass 38, count 2 2006.201.20:39:49.70#ibcon#wrote, iclass 38, count 2 2006.201.20:39:49.70#ibcon#about to read 3, iclass 38, count 2 2006.201.20:39:49.73#ibcon#read 3, iclass 38, count 2 2006.201.20:39:49.73#ibcon#about to read 4, iclass 38, count 2 2006.201.20:39:49.73#ibcon#read 4, iclass 38, count 2 2006.201.20:39:49.73#ibcon#about to read 5, iclass 38, count 2 2006.201.20:39:49.73#ibcon#read 5, iclass 38, count 2 2006.201.20:39:49.73#ibcon#about to read 6, iclass 38, count 2 2006.201.20:39:49.73#ibcon#read 6, iclass 38, count 2 2006.201.20:39:49.73#ibcon#end of sib2, iclass 38, count 2 2006.201.20:39:49.73#ibcon#*after write, iclass 38, count 2 2006.201.20:39:49.73#ibcon#*before return 0, iclass 38, count 2 2006.201.20:39:49.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:49.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:49.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.20:39:49.73#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:49.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:49.76#abcon#<5=/04 0.8 1.6 20.111001002.3\r\n> 2006.201.20:39:49.78#abcon#{5=INTERFACE CLEAR} 2006.201.20:39:49.84#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:39:49.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:49.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:49.85#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:39:49.85#ibcon#first serial, iclass 38, count 0 2006.201.20:39:49.85#ibcon#enter sib2, iclass 38, count 0 2006.201.20:39:49.85#ibcon#flushed, iclass 38, count 0 2006.201.20:39:49.85#ibcon#about to write, iclass 38, count 0 2006.201.20:39:49.85#ibcon#wrote, iclass 38, count 0 2006.201.20:39:49.85#ibcon#about to read 3, iclass 38, count 0 2006.201.20:39:49.87#ibcon#read 3, iclass 38, count 0 2006.201.20:39:49.87#ibcon#about to read 4, iclass 38, count 0 2006.201.20:39:49.87#ibcon#read 4, iclass 38, count 0 2006.201.20:39:49.87#ibcon#about to read 5, iclass 38, count 0 2006.201.20:39:49.87#ibcon#read 5, iclass 38, count 0 2006.201.20:39:49.87#ibcon#about to read 6, iclass 38, count 0 2006.201.20:39:49.87#ibcon#read 6, iclass 38, count 0 2006.201.20:39:49.87#ibcon#end of sib2, iclass 38, count 0 2006.201.20:39:49.87#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:39:49.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:39:49.87#ibcon#[25=USB\r\n] 2006.201.20:39:49.87#ibcon#*before write, iclass 38, count 0 2006.201.20:39:49.87#ibcon#enter sib2, iclass 38, count 0 2006.201.20:39:49.87#ibcon#flushed, iclass 38, count 0 2006.201.20:39:49.87#ibcon#about to write, iclass 38, count 0 2006.201.20:39:49.87#ibcon#wrote, iclass 38, count 0 2006.201.20:39:49.87#ibcon#about to read 3, iclass 38, count 0 2006.201.20:39:49.90#ibcon#read 3, iclass 38, count 0 2006.201.20:39:49.90#ibcon#about to read 4, iclass 38, count 0 2006.201.20:39:49.90#ibcon#read 4, iclass 38, count 0 2006.201.20:39:49.90#ibcon#about to read 5, iclass 38, count 0 2006.201.20:39:49.90#ibcon#read 5, iclass 38, count 0 2006.201.20:39:49.90#ibcon#about to read 6, iclass 38, count 0 2006.201.20:39:49.90#ibcon#read 6, iclass 38, count 0 2006.201.20:39:49.90#ibcon#end of sib2, iclass 38, count 0 2006.201.20:39:49.90#ibcon#*after write, iclass 38, count 0 2006.201.20:39:49.90#ibcon#*before return 0, iclass 38, count 0 2006.201.20:39:49.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:49.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:49.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:39:49.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:39:49.90$vck44/valo=4,624.99 2006.201.20:39:49.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.20:39:49.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.20:39:49.90#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:49.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:49.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:49.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:49.90#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:39:49.90#ibcon#first serial, iclass 6, count 0 2006.201.20:39:49.90#ibcon#enter sib2, iclass 6, count 0 2006.201.20:39:49.90#ibcon#flushed, iclass 6, count 0 2006.201.20:39:49.90#ibcon#about to write, iclass 6, count 0 2006.201.20:39:49.90#ibcon#wrote, iclass 6, count 0 2006.201.20:39:49.90#ibcon#about to read 3, iclass 6, count 0 2006.201.20:39:49.92#ibcon#read 3, iclass 6, count 0 2006.201.20:39:49.92#ibcon#about to read 4, iclass 6, count 0 2006.201.20:39:49.92#ibcon#read 4, iclass 6, count 0 2006.201.20:39:49.92#ibcon#about to read 5, iclass 6, count 0 2006.201.20:39:49.92#ibcon#read 5, iclass 6, count 0 2006.201.20:39:49.92#ibcon#about to read 6, iclass 6, count 0 2006.201.20:39:49.92#ibcon#read 6, iclass 6, count 0 2006.201.20:39:49.92#ibcon#end of sib2, iclass 6, count 0 2006.201.20:39:49.92#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:39:49.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:39:49.92#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:39:49.92#ibcon#*before write, iclass 6, count 0 2006.201.20:39:49.92#ibcon#enter sib2, iclass 6, count 0 2006.201.20:39:49.92#ibcon#flushed, iclass 6, count 0 2006.201.20:39:49.92#ibcon#about to write, iclass 6, count 0 2006.201.20:39:49.92#ibcon#wrote, iclass 6, count 0 2006.201.20:39:49.92#ibcon#about to read 3, iclass 6, count 0 2006.201.20:39:49.96#ibcon#read 3, iclass 6, count 0 2006.201.20:39:49.96#ibcon#about to read 4, iclass 6, count 0 2006.201.20:39:49.96#ibcon#read 4, iclass 6, count 0 2006.201.20:39:49.96#ibcon#about to read 5, iclass 6, count 0 2006.201.20:39:49.96#ibcon#read 5, iclass 6, count 0 2006.201.20:39:49.96#ibcon#about to read 6, iclass 6, count 0 2006.201.20:39:49.96#ibcon#read 6, iclass 6, count 0 2006.201.20:39:49.96#ibcon#end of sib2, iclass 6, count 0 2006.201.20:39:49.96#ibcon#*after write, iclass 6, count 0 2006.201.20:39:49.96#ibcon#*before return 0, iclass 6, count 0 2006.201.20:39:49.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:49.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:49.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:39:49.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:39:49.96$vck44/va=4,7 2006.201.20:39:49.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.20:39:49.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.20:39:49.96#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:49.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:50.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:50.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:50.02#ibcon#enter wrdev, iclass 10, count 2 2006.201.20:39:50.02#ibcon#first serial, iclass 10, count 2 2006.201.20:39:50.02#ibcon#enter sib2, iclass 10, count 2 2006.201.20:39:50.02#ibcon#flushed, iclass 10, count 2 2006.201.20:39:50.02#ibcon#about to write, iclass 10, count 2 2006.201.20:39:50.02#ibcon#wrote, iclass 10, count 2 2006.201.20:39:50.02#ibcon#about to read 3, iclass 10, count 2 2006.201.20:39:50.04#ibcon#read 3, iclass 10, count 2 2006.201.20:39:50.04#ibcon#about to read 4, iclass 10, count 2 2006.201.20:39:50.04#ibcon#read 4, iclass 10, count 2 2006.201.20:39:50.04#ibcon#about to read 5, iclass 10, count 2 2006.201.20:39:50.04#ibcon#read 5, iclass 10, count 2 2006.201.20:39:50.04#ibcon#about to read 6, iclass 10, count 2 2006.201.20:39:50.04#ibcon#read 6, iclass 10, count 2 2006.201.20:39:50.04#ibcon#end of sib2, iclass 10, count 2 2006.201.20:39:50.04#ibcon#*mode == 0, iclass 10, count 2 2006.201.20:39:50.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.20:39:50.04#ibcon#[25=AT04-07\r\n] 2006.201.20:39:50.04#ibcon#*before write, iclass 10, count 2 2006.201.20:39:50.04#ibcon#enter sib2, iclass 10, count 2 2006.201.20:39:50.04#ibcon#flushed, iclass 10, count 2 2006.201.20:39:50.04#ibcon#about to write, iclass 10, count 2 2006.201.20:39:50.04#ibcon#wrote, iclass 10, count 2 2006.201.20:39:50.04#ibcon#about to read 3, iclass 10, count 2 2006.201.20:39:50.07#ibcon#read 3, iclass 10, count 2 2006.201.20:39:50.07#ibcon#about to read 4, iclass 10, count 2 2006.201.20:39:50.07#ibcon#read 4, iclass 10, count 2 2006.201.20:39:50.07#ibcon#about to read 5, iclass 10, count 2 2006.201.20:39:50.07#ibcon#read 5, iclass 10, count 2 2006.201.20:39:50.07#ibcon#about to read 6, iclass 10, count 2 2006.201.20:39:50.07#ibcon#read 6, iclass 10, count 2 2006.201.20:39:50.07#ibcon#end of sib2, iclass 10, count 2 2006.201.20:39:50.07#ibcon#*after write, iclass 10, count 2 2006.201.20:39:50.07#ibcon#*before return 0, iclass 10, count 2 2006.201.20:39:50.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:50.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:50.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.20:39:50.07#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:50.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:50.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:50.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:50.19#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:39:50.19#ibcon#first serial, iclass 10, count 0 2006.201.20:39:50.19#ibcon#enter sib2, iclass 10, count 0 2006.201.20:39:50.19#ibcon#flushed, iclass 10, count 0 2006.201.20:39:50.19#ibcon#about to write, iclass 10, count 0 2006.201.20:39:50.19#ibcon#wrote, iclass 10, count 0 2006.201.20:39:50.19#ibcon#about to read 3, iclass 10, count 0 2006.201.20:39:50.21#ibcon#read 3, iclass 10, count 0 2006.201.20:39:50.21#ibcon#about to read 4, iclass 10, count 0 2006.201.20:39:50.21#ibcon#read 4, iclass 10, count 0 2006.201.20:39:50.21#ibcon#about to read 5, iclass 10, count 0 2006.201.20:39:50.21#ibcon#read 5, iclass 10, count 0 2006.201.20:39:50.21#ibcon#about to read 6, iclass 10, count 0 2006.201.20:39:50.21#ibcon#read 6, iclass 10, count 0 2006.201.20:39:50.21#ibcon#end of sib2, iclass 10, count 0 2006.201.20:39:50.21#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:39:50.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:39:50.21#ibcon#[25=USB\r\n] 2006.201.20:39:50.21#ibcon#*before write, iclass 10, count 0 2006.201.20:39:50.21#ibcon#enter sib2, iclass 10, count 0 2006.201.20:39:50.21#ibcon#flushed, iclass 10, count 0 2006.201.20:39:50.21#ibcon#about to write, iclass 10, count 0 2006.201.20:39:50.21#ibcon#wrote, iclass 10, count 0 2006.201.20:39:50.21#ibcon#about to read 3, iclass 10, count 0 2006.201.20:39:50.24#ibcon#read 3, iclass 10, count 0 2006.201.20:39:50.24#ibcon#about to read 4, iclass 10, count 0 2006.201.20:39:50.24#ibcon#read 4, iclass 10, count 0 2006.201.20:39:50.24#ibcon#about to read 5, iclass 10, count 0 2006.201.20:39:50.24#ibcon#read 5, iclass 10, count 0 2006.201.20:39:50.24#ibcon#about to read 6, iclass 10, count 0 2006.201.20:39:50.24#ibcon#read 6, iclass 10, count 0 2006.201.20:39:50.24#ibcon#end of sib2, iclass 10, count 0 2006.201.20:39:50.24#ibcon#*after write, iclass 10, count 0 2006.201.20:39:50.24#ibcon#*before return 0, iclass 10, count 0 2006.201.20:39:50.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:50.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:50.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:39:50.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:39:50.24$vck44/valo=5,734.99 2006.201.20:39:50.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.20:39:50.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.20:39:50.24#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:50.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:50.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:50.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:50.24#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:39:50.24#ibcon#first serial, iclass 12, count 0 2006.201.20:39:50.24#ibcon#enter sib2, iclass 12, count 0 2006.201.20:39:50.24#ibcon#flushed, iclass 12, count 0 2006.201.20:39:50.24#ibcon#about to write, iclass 12, count 0 2006.201.20:39:50.24#ibcon#wrote, iclass 12, count 0 2006.201.20:39:50.24#ibcon#about to read 3, iclass 12, count 0 2006.201.20:39:50.26#ibcon#read 3, iclass 12, count 0 2006.201.20:39:50.26#ibcon#about to read 4, iclass 12, count 0 2006.201.20:39:50.26#ibcon#read 4, iclass 12, count 0 2006.201.20:39:50.26#ibcon#about to read 5, iclass 12, count 0 2006.201.20:39:50.26#ibcon#read 5, iclass 12, count 0 2006.201.20:39:50.26#ibcon#about to read 6, iclass 12, count 0 2006.201.20:39:50.26#ibcon#read 6, iclass 12, count 0 2006.201.20:39:50.26#ibcon#end of sib2, iclass 12, count 0 2006.201.20:39:50.26#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:39:50.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:39:50.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:39:50.26#ibcon#*before write, iclass 12, count 0 2006.201.20:39:50.26#ibcon#enter sib2, iclass 12, count 0 2006.201.20:39:50.26#ibcon#flushed, iclass 12, count 0 2006.201.20:39:50.26#ibcon#about to write, iclass 12, count 0 2006.201.20:39:50.26#ibcon#wrote, iclass 12, count 0 2006.201.20:39:50.26#ibcon#about to read 3, iclass 12, count 0 2006.201.20:39:50.30#ibcon#read 3, iclass 12, count 0 2006.201.20:39:50.30#ibcon#about to read 4, iclass 12, count 0 2006.201.20:39:50.30#ibcon#read 4, iclass 12, count 0 2006.201.20:39:50.30#ibcon#about to read 5, iclass 12, count 0 2006.201.20:39:50.30#ibcon#read 5, iclass 12, count 0 2006.201.20:39:50.30#ibcon#about to read 6, iclass 12, count 0 2006.201.20:39:50.30#ibcon#read 6, iclass 12, count 0 2006.201.20:39:50.30#ibcon#end of sib2, iclass 12, count 0 2006.201.20:39:50.30#ibcon#*after write, iclass 12, count 0 2006.201.20:39:50.30#ibcon#*before return 0, iclass 12, count 0 2006.201.20:39:50.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:50.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:50.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:39:50.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:39:50.30$vck44/va=5,4 2006.201.20:39:50.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.20:39:50.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.20:39:50.30#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:50.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:50.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:50.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:50.36#ibcon#enter wrdev, iclass 14, count 2 2006.201.20:39:50.36#ibcon#first serial, iclass 14, count 2 2006.201.20:39:50.36#ibcon#enter sib2, iclass 14, count 2 2006.201.20:39:50.36#ibcon#flushed, iclass 14, count 2 2006.201.20:39:50.36#ibcon#about to write, iclass 14, count 2 2006.201.20:39:50.36#ibcon#wrote, iclass 14, count 2 2006.201.20:39:50.36#ibcon#about to read 3, iclass 14, count 2 2006.201.20:39:50.38#ibcon#read 3, iclass 14, count 2 2006.201.20:39:50.38#ibcon#about to read 4, iclass 14, count 2 2006.201.20:39:50.38#ibcon#read 4, iclass 14, count 2 2006.201.20:39:50.38#ibcon#about to read 5, iclass 14, count 2 2006.201.20:39:50.38#ibcon#read 5, iclass 14, count 2 2006.201.20:39:50.38#ibcon#about to read 6, iclass 14, count 2 2006.201.20:39:50.38#ibcon#read 6, iclass 14, count 2 2006.201.20:39:50.38#ibcon#end of sib2, iclass 14, count 2 2006.201.20:39:50.38#ibcon#*mode == 0, iclass 14, count 2 2006.201.20:39:50.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.20:39:50.38#ibcon#[25=AT05-04\r\n] 2006.201.20:39:50.38#ibcon#*before write, iclass 14, count 2 2006.201.20:39:50.38#ibcon#enter sib2, iclass 14, count 2 2006.201.20:39:50.38#ibcon#flushed, iclass 14, count 2 2006.201.20:39:50.38#ibcon#about to write, iclass 14, count 2 2006.201.20:39:50.38#ibcon#wrote, iclass 14, count 2 2006.201.20:39:50.38#ibcon#about to read 3, iclass 14, count 2 2006.201.20:39:50.41#ibcon#read 3, iclass 14, count 2 2006.201.20:39:50.41#ibcon#about to read 4, iclass 14, count 2 2006.201.20:39:50.41#ibcon#read 4, iclass 14, count 2 2006.201.20:39:50.41#ibcon#about to read 5, iclass 14, count 2 2006.201.20:39:50.41#ibcon#read 5, iclass 14, count 2 2006.201.20:39:50.41#ibcon#about to read 6, iclass 14, count 2 2006.201.20:39:50.41#ibcon#read 6, iclass 14, count 2 2006.201.20:39:50.41#ibcon#end of sib2, iclass 14, count 2 2006.201.20:39:50.41#ibcon#*after write, iclass 14, count 2 2006.201.20:39:50.41#ibcon#*before return 0, iclass 14, count 2 2006.201.20:39:50.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:50.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:50.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.20:39:50.41#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:50.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:50.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:50.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:50.53#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:39:50.53#ibcon#first serial, iclass 14, count 0 2006.201.20:39:50.53#ibcon#enter sib2, iclass 14, count 0 2006.201.20:39:50.53#ibcon#flushed, iclass 14, count 0 2006.201.20:39:50.53#ibcon#about to write, iclass 14, count 0 2006.201.20:39:50.53#ibcon#wrote, iclass 14, count 0 2006.201.20:39:50.53#ibcon#about to read 3, iclass 14, count 0 2006.201.20:39:50.55#ibcon#read 3, iclass 14, count 0 2006.201.20:39:50.55#ibcon#about to read 4, iclass 14, count 0 2006.201.20:39:50.55#ibcon#read 4, iclass 14, count 0 2006.201.20:39:50.55#ibcon#about to read 5, iclass 14, count 0 2006.201.20:39:50.55#ibcon#read 5, iclass 14, count 0 2006.201.20:39:50.55#ibcon#about to read 6, iclass 14, count 0 2006.201.20:39:50.55#ibcon#read 6, iclass 14, count 0 2006.201.20:39:50.55#ibcon#end of sib2, iclass 14, count 0 2006.201.20:39:50.55#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:39:50.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:39:50.55#ibcon#[25=USB\r\n] 2006.201.20:39:50.55#ibcon#*before write, iclass 14, count 0 2006.201.20:39:50.55#ibcon#enter sib2, iclass 14, count 0 2006.201.20:39:50.55#ibcon#flushed, iclass 14, count 0 2006.201.20:39:50.55#ibcon#about to write, iclass 14, count 0 2006.201.20:39:50.55#ibcon#wrote, iclass 14, count 0 2006.201.20:39:50.55#ibcon#about to read 3, iclass 14, count 0 2006.201.20:39:50.58#ibcon#read 3, iclass 14, count 0 2006.201.20:39:50.58#ibcon#about to read 4, iclass 14, count 0 2006.201.20:39:50.58#ibcon#read 4, iclass 14, count 0 2006.201.20:39:50.58#ibcon#about to read 5, iclass 14, count 0 2006.201.20:39:50.58#ibcon#read 5, iclass 14, count 0 2006.201.20:39:50.58#ibcon#about to read 6, iclass 14, count 0 2006.201.20:39:50.58#ibcon#read 6, iclass 14, count 0 2006.201.20:39:50.58#ibcon#end of sib2, iclass 14, count 0 2006.201.20:39:50.58#ibcon#*after write, iclass 14, count 0 2006.201.20:39:50.58#ibcon#*before return 0, iclass 14, count 0 2006.201.20:39:50.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:50.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:50.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:39:50.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:39:50.58$vck44/valo=6,814.99 2006.201.20:39:50.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.20:39:50.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.20:39:50.58#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:50.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:50.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:50.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:50.58#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:39:50.58#ibcon#first serial, iclass 16, count 0 2006.201.20:39:50.58#ibcon#enter sib2, iclass 16, count 0 2006.201.20:39:50.58#ibcon#flushed, iclass 16, count 0 2006.201.20:39:50.58#ibcon#about to write, iclass 16, count 0 2006.201.20:39:50.58#ibcon#wrote, iclass 16, count 0 2006.201.20:39:50.58#ibcon#about to read 3, iclass 16, count 0 2006.201.20:39:50.60#ibcon#read 3, iclass 16, count 0 2006.201.20:39:50.60#ibcon#about to read 4, iclass 16, count 0 2006.201.20:39:50.60#ibcon#read 4, iclass 16, count 0 2006.201.20:39:50.60#ibcon#about to read 5, iclass 16, count 0 2006.201.20:39:50.60#ibcon#read 5, iclass 16, count 0 2006.201.20:39:50.60#ibcon#about to read 6, iclass 16, count 0 2006.201.20:39:50.60#ibcon#read 6, iclass 16, count 0 2006.201.20:39:50.60#ibcon#end of sib2, iclass 16, count 0 2006.201.20:39:50.60#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:39:50.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:39:50.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:39:50.60#ibcon#*before write, iclass 16, count 0 2006.201.20:39:50.60#ibcon#enter sib2, iclass 16, count 0 2006.201.20:39:50.60#ibcon#flushed, iclass 16, count 0 2006.201.20:39:50.60#ibcon#about to write, iclass 16, count 0 2006.201.20:39:50.60#ibcon#wrote, iclass 16, count 0 2006.201.20:39:50.60#ibcon#about to read 3, iclass 16, count 0 2006.201.20:39:50.64#ibcon#read 3, iclass 16, count 0 2006.201.20:39:50.64#ibcon#about to read 4, iclass 16, count 0 2006.201.20:39:50.64#ibcon#read 4, iclass 16, count 0 2006.201.20:39:50.64#ibcon#about to read 5, iclass 16, count 0 2006.201.20:39:50.64#ibcon#read 5, iclass 16, count 0 2006.201.20:39:50.64#ibcon#about to read 6, iclass 16, count 0 2006.201.20:39:50.64#ibcon#read 6, iclass 16, count 0 2006.201.20:39:50.64#ibcon#end of sib2, iclass 16, count 0 2006.201.20:39:50.64#ibcon#*after write, iclass 16, count 0 2006.201.20:39:50.64#ibcon#*before return 0, iclass 16, count 0 2006.201.20:39:50.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:50.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:50.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:39:50.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:39:50.64$vck44/va=6,5 2006.201.20:39:50.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.20:39:50.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.20:39:50.64#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:50.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:50.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:50.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:50.70#ibcon#enter wrdev, iclass 18, count 2 2006.201.20:39:50.70#ibcon#first serial, iclass 18, count 2 2006.201.20:39:50.70#ibcon#enter sib2, iclass 18, count 2 2006.201.20:39:50.70#ibcon#flushed, iclass 18, count 2 2006.201.20:39:50.70#ibcon#about to write, iclass 18, count 2 2006.201.20:39:50.70#ibcon#wrote, iclass 18, count 2 2006.201.20:39:50.70#ibcon#about to read 3, iclass 18, count 2 2006.201.20:39:50.72#ibcon#read 3, iclass 18, count 2 2006.201.20:39:50.72#ibcon#about to read 4, iclass 18, count 2 2006.201.20:39:50.72#ibcon#read 4, iclass 18, count 2 2006.201.20:39:50.72#ibcon#about to read 5, iclass 18, count 2 2006.201.20:39:50.72#ibcon#read 5, iclass 18, count 2 2006.201.20:39:50.72#ibcon#about to read 6, iclass 18, count 2 2006.201.20:39:50.72#ibcon#read 6, iclass 18, count 2 2006.201.20:39:50.72#ibcon#end of sib2, iclass 18, count 2 2006.201.20:39:50.72#ibcon#*mode == 0, iclass 18, count 2 2006.201.20:39:50.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.20:39:50.72#ibcon#[25=AT06-05\r\n] 2006.201.20:39:50.72#ibcon#*before write, iclass 18, count 2 2006.201.20:39:50.72#ibcon#enter sib2, iclass 18, count 2 2006.201.20:39:50.72#ibcon#flushed, iclass 18, count 2 2006.201.20:39:50.72#ibcon#about to write, iclass 18, count 2 2006.201.20:39:50.72#ibcon#wrote, iclass 18, count 2 2006.201.20:39:50.72#ibcon#about to read 3, iclass 18, count 2 2006.201.20:39:50.75#ibcon#read 3, iclass 18, count 2 2006.201.20:39:50.75#ibcon#about to read 4, iclass 18, count 2 2006.201.20:39:50.75#ibcon#read 4, iclass 18, count 2 2006.201.20:39:50.75#ibcon#about to read 5, iclass 18, count 2 2006.201.20:39:50.75#ibcon#read 5, iclass 18, count 2 2006.201.20:39:50.75#ibcon#about to read 6, iclass 18, count 2 2006.201.20:39:50.75#ibcon#read 6, iclass 18, count 2 2006.201.20:39:50.75#ibcon#end of sib2, iclass 18, count 2 2006.201.20:39:50.75#ibcon#*after write, iclass 18, count 2 2006.201.20:39:50.75#ibcon#*before return 0, iclass 18, count 2 2006.201.20:39:50.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:50.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:50.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.20:39:50.75#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:50.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:50.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:50.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:50.87#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:39:50.87#ibcon#first serial, iclass 18, count 0 2006.201.20:39:50.87#ibcon#enter sib2, iclass 18, count 0 2006.201.20:39:50.87#ibcon#flushed, iclass 18, count 0 2006.201.20:39:50.87#ibcon#about to write, iclass 18, count 0 2006.201.20:39:50.87#ibcon#wrote, iclass 18, count 0 2006.201.20:39:50.87#ibcon#about to read 3, iclass 18, count 0 2006.201.20:39:50.89#ibcon#read 3, iclass 18, count 0 2006.201.20:39:50.89#ibcon#about to read 4, iclass 18, count 0 2006.201.20:39:50.89#ibcon#read 4, iclass 18, count 0 2006.201.20:39:50.89#ibcon#about to read 5, iclass 18, count 0 2006.201.20:39:50.89#ibcon#read 5, iclass 18, count 0 2006.201.20:39:50.89#ibcon#about to read 6, iclass 18, count 0 2006.201.20:39:50.89#ibcon#read 6, iclass 18, count 0 2006.201.20:39:50.89#ibcon#end of sib2, iclass 18, count 0 2006.201.20:39:50.89#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:39:50.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:39:50.89#ibcon#[25=USB\r\n] 2006.201.20:39:50.89#ibcon#*before write, iclass 18, count 0 2006.201.20:39:50.89#ibcon#enter sib2, iclass 18, count 0 2006.201.20:39:50.89#ibcon#flushed, iclass 18, count 0 2006.201.20:39:50.89#ibcon#about to write, iclass 18, count 0 2006.201.20:39:50.89#ibcon#wrote, iclass 18, count 0 2006.201.20:39:50.89#ibcon#about to read 3, iclass 18, count 0 2006.201.20:39:50.92#ibcon#read 3, iclass 18, count 0 2006.201.20:39:50.92#ibcon#about to read 4, iclass 18, count 0 2006.201.20:39:50.92#ibcon#read 4, iclass 18, count 0 2006.201.20:39:50.92#ibcon#about to read 5, iclass 18, count 0 2006.201.20:39:50.92#ibcon#read 5, iclass 18, count 0 2006.201.20:39:50.92#ibcon#about to read 6, iclass 18, count 0 2006.201.20:39:50.92#ibcon#read 6, iclass 18, count 0 2006.201.20:39:50.92#ibcon#end of sib2, iclass 18, count 0 2006.201.20:39:50.92#ibcon#*after write, iclass 18, count 0 2006.201.20:39:50.92#ibcon#*before return 0, iclass 18, count 0 2006.201.20:39:50.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:50.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:50.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:39:50.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:39:50.92$vck44/valo=7,864.99 2006.201.20:39:50.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.20:39:50.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.20:39:50.92#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:50.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:50.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:50.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:50.92#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:39:50.92#ibcon#first serial, iclass 20, count 0 2006.201.20:39:50.92#ibcon#enter sib2, iclass 20, count 0 2006.201.20:39:50.92#ibcon#flushed, iclass 20, count 0 2006.201.20:39:50.92#ibcon#about to write, iclass 20, count 0 2006.201.20:39:50.92#ibcon#wrote, iclass 20, count 0 2006.201.20:39:50.92#ibcon#about to read 3, iclass 20, count 0 2006.201.20:39:50.94#ibcon#read 3, iclass 20, count 0 2006.201.20:39:50.94#ibcon#about to read 4, iclass 20, count 0 2006.201.20:39:50.94#ibcon#read 4, iclass 20, count 0 2006.201.20:39:50.94#ibcon#about to read 5, iclass 20, count 0 2006.201.20:39:50.94#ibcon#read 5, iclass 20, count 0 2006.201.20:39:50.94#ibcon#about to read 6, iclass 20, count 0 2006.201.20:39:50.94#ibcon#read 6, iclass 20, count 0 2006.201.20:39:50.94#ibcon#end of sib2, iclass 20, count 0 2006.201.20:39:50.94#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:39:50.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:39:50.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:39:50.94#ibcon#*before write, iclass 20, count 0 2006.201.20:39:50.94#ibcon#enter sib2, iclass 20, count 0 2006.201.20:39:50.94#ibcon#flushed, iclass 20, count 0 2006.201.20:39:50.94#ibcon#about to write, iclass 20, count 0 2006.201.20:39:50.94#ibcon#wrote, iclass 20, count 0 2006.201.20:39:50.94#ibcon#about to read 3, iclass 20, count 0 2006.201.20:39:50.98#ibcon#read 3, iclass 20, count 0 2006.201.20:39:50.98#ibcon#about to read 4, iclass 20, count 0 2006.201.20:39:50.98#ibcon#read 4, iclass 20, count 0 2006.201.20:39:50.98#ibcon#about to read 5, iclass 20, count 0 2006.201.20:39:50.98#ibcon#read 5, iclass 20, count 0 2006.201.20:39:50.98#ibcon#about to read 6, iclass 20, count 0 2006.201.20:39:50.98#ibcon#read 6, iclass 20, count 0 2006.201.20:39:50.98#ibcon#end of sib2, iclass 20, count 0 2006.201.20:39:50.98#ibcon#*after write, iclass 20, count 0 2006.201.20:39:50.98#ibcon#*before return 0, iclass 20, count 0 2006.201.20:39:50.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:50.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:50.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:39:50.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:39:50.98$vck44/va=7,5 2006.201.20:39:50.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.20:39:50.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.20:39:50.98#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:50.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:51.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:51.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:51.04#ibcon#enter wrdev, iclass 22, count 2 2006.201.20:39:51.04#ibcon#first serial, iclass 22, count 2 2006.201.20:39:51.04#ibcon#enter sib2, iclass 22, count 2 2006.201.20:39:51.04#ibcon#flushed, iclass 22, count 2 2006.201.20:39:51.04#ibcon#about to write, iclass 22, count 2 2006.201.20:39:51.04#ibcon#wrote, iclass 22, count 2 2006.201.20:39:51.04#ibcon#about to read 3, iclass 22, count 2 2006.201.20:39:51.06#ibcon#read 3, iclass 22, count 2 2006.201.20:39:51.06#ibcon#about to read 4, iclass 22, count 2 2006.201.20:39:51.06#ibcon#read 4, iclass 22, count 2 2006.201.20:39:51.06#ibcon#about to read 5, iclass 22, count 2 2006.201.20:39:51.06#ibcon#read 5, iclass 22, count 2 2006.201.20:39:51.06#ibcon#about to read 6, iclass 22, count 2 2006.201.20:39:51.06#ibcon#read 6, iclass 22, count 2 2006.201.20:39:51.06#ibcon#end of sib2, iclass 22, count 2 2006.201.20:39:51.06#ibcon#*mode == 0, iclass 22, count 2 2006.201.20:39:51.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.20:39:51.06#ibcon#[25=AT07-05\r\n] 2006.201.20:39:51.06#ibcon#*before write, iclass 22, count 2 2006.201.20:39:51.06#ibcon#enter sib2, iclass 22, count 2 2006.201.20:39:51.06#ibcon#flushed, iclass 22, count 2 2006.201.20:39:51.06#ibcon#about to write, iclass 22, count 2 2006.201.20:39:51.06#ibcon#wrote, iclass 22, count 2 2006.201.20:39:51.06#ibcon#about to read 3, iclass 22, count 2 2006.201.20:39:51.09#ibcon#read 3, iclass 22, count 2 2006.201.20:39:51.09#ibcon#about to read 4, iclass 22, count 2 2006.201.20:39:51.09#ibcon#read 4, iclass 22, count 2 2006.201.20:39:51.09#ibcon#about to read 5, iclass 22, count 2 2006.201.20:39:51.09#ibcon#read 5, iclass 22, count 2 2006.201.20:39:51.09#ibcon#about to read 6, iclass 22, count 2 2006.201.20:39:51.09#ibcon#read 6, iclass 22, count 2 2006.201.20:39:51.09#ibcon#end of sib2, iclass 22, count 2 2006.201.20:39:51.09#ibcon#*after write, iclass 22, count 2 2006.201.20:39:51.09#ibcon#*before return 0, iclass 22, count 2 2006.201.20:39:51.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:51.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:51.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.20:39:51.09#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:51.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:51.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:51.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:51.21#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:39:51.21#ibcon#first serial, iclass 22, count 0 2006.201.20:39:51.21#ibcon#enter sib2, iclass 22, count 0 2006.201.20:39:51.21#ibcon#flushed, iclass 22, count 0 2006.201.20:39:51.21#ibcon#about to write, iclass 22, count 0 2006.201.20:39:51.21#ibcon#wrote, iclass 22, count 0 2006.201.20:39:51.21#ibcon#about to read 3, iclass 22, count 0 2006.201.20:39:51.23#ibcon#read 3, iclass 22, count 0 2006.201.20:39:51.23#ibcon#about to read 4, iclass 22, count 0 2006.201.20:39:51.23#ibcon#read 4, iclass 22, count 0 2006.201.20:39:51.23#ibcon#about to read 5, iclass 22, count 0 2006.201.20:39:51.23#ibcon#read 5, iclass 22, count 0 2006.201.20:39:51.23#ibcon#about to read 6, iclass 22, count 0 2006.201.20:39:51.23#ibcon#read 6, iclass 22, count 0 2006.201.20:39:51.23#ibcon#end of sib2, iclass 22, count 0 2006.201.20:39:51.23#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:39:51.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:39:51.23#ibcon#[25=USB\r\n] 2006.201.20:39:51.23#ibcon#*before write, iclass 22, count 0 2006.201.20:39:51.23#ibcon#enter sib2, iclass 22, count 0 2006.201.20:39:51.23#ibcon#flushed, iclass 22, count 0 2006.201.20:39:51.23#ibcon#about to write, iclass 22, count 0 2006.201.20:39:51.23#ibcon#wrote, iclass 22, count 0 2006.201.20:39:51.23#ibcon#about to read 3, iclass 22, count 0 2006.201.20:39:51.26#ibcon#read 3, iclass 22, count 0 2006.201.20:39:51.26#ibcon#about to read 4, iclass 22, count 0 2006.201.20:39:51.26#ibcon#read 4, iclass 22, count 0 2006.201.20:39:51.26#ibcon#about to read 5, iclass 22, count 0 2006.201.20:39:51.26#ibcon#read 5, iclass 22, count 0 2006.201.20:39:51.26#ibcon#about to read 6, iclass 22, count 0 2006.201.20:39:51.26#ibcon#read 6, iclass 22, count 0 2006.201.20:39:51.26#ibcon#end of sib2, iclass 22, count 0 2006.201.20:39:51.26#ibcon#*after write, iclass 22, count 0 2006.201.20:39:51.26#ibcon#*before return 0, iclass 22, count 0 2006.201.20:39:51.26#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:51.26#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:51.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:39:51.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:39:51.26$vck44/valo=8,884.99 2006.201.20:39:51.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.20:39:51.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.20:39:51.26#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:51.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:51.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:51.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:51.26#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:39:51.26#ibcon#first serial, iclass 24, count 0 2006.201.20:39:51.26#ibcon#enter sib2, iclass 24, count 0 2006.201.20:39:51.26#ibcon#flushed, iclass 24, count 0 2006.201.20:39:51.26#ibcon#about to write, iclass 24, count 0 2006.201.20:39:51.26#ibcon#wrote, iclass 24, count 0 2006.201.20:39:51.26#ibcon#about to read 3, iclass 24, count 0 2006.201.20:39:51.28#ibcon#read 3, iclass 24, count 0 2006.201.20:39:51.28#ibcon#about to read 4, iclass 24, count 0 2006.201.20:39:51.28#ibcon#read 4, iclass 24, count 0 2006.201.20:39:51.28#ibcon#about to read 5, iclass 24, count 0 2006.201.20:39:51.28#ibcon#read 5, iclass 24, count 0 2006.201.20:39:51.28#ibcon#about to read 6, iclass 24, count 0 2006.201.20:39:51.28#ibcon#read 6, iclass 24, count 0 2006.201.20:39:51.28#ibcon#end of sib2, iclass 24, count 0 2006.201.20:39:51.28#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:39:51.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:39:51.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:39:51.28#ibcon#*before write, iclass 24, count 0 2006.201.20:39:51.28#ibcon#enter sib2, iclass 24, count 0 2006.201.20:39:51.28#ibcon#flushed, iclass 24, count 0 2006.201.20:39:51.28#ibcon#about to write, iclass 24, count 0 2006.201.20:39:51.28#ibcon#wrote, iclass 24, count 0 2006.201.20:39:51.28#ibcon#about to read 3, iclass 24, count 0 2006.201.20:39:51.32#ibcon#read 3, iclass 24, count 0 2006.201.20:39:51.32#ibcon#about to read 4, iclass 24, count 0 2006.201.20:39:51.32#ibcon#read 4, iclass 24, count 0 2006.201.20:39:51.32#ibcon#about to read 5, iclass 24, count 0 2006.201.20:39:51.32#ibcon#read 5, iclass 24, count 0 2006.201.20:39:51.32#ibcon#about to read 6, iclass 24, count 0 2006.201.20:39:51.32#ibcon#read 6, iclass 24, count 0 2006.201.20:39:51.32#ibcon#end of sib2, iclass 24, count 0 2006.201.20:39:51.32#ibcon#*after write, iclass 24, count 0 2006.201.20:39:51.32#ibcon#*before return 0, iclass 24, count 0 2006.201.20:39:51.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:51.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:51.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:39:51.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:39:51.32$vck44/va=8,4 2006.201.20:39:51.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.20:39:51.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.20:39:51.32#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:51.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:39:51.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:39:51.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:39:51.38#ibcon#enter wrdev, iclass 26, count 2 2006.201.20:39:51.38#ibcon#first serial, iclass 26, count 2 2006.201.20:39:51.38#ibcon#enter sib2, iclass 26, count 2 2006.201.20:39:51.38#ibcon#flushed, iclass 26, count 2 2006.201.20:39:51.38#ibcon#about to write, iclass 26, count 2 2006.201.20:39:51.38#ibcon#wrote, iclass 26, count 2 2006.201.20:39:51.38#ibcon#about to read 3, iclass 26, count 2 2006.201.20:39:51.40#ibcon#read 3, iclass 26, count 2 2006.201.20:39:51.40#ibcon#about to read 4, iclass 26, count 2 2006.201.20:39:51.40#ibcon#read 4, iclass 26, count 2 2006.201.20:39:51.40#ibcon#about to read 5, iclass 26, count 2 2006.201.20:39:51.40#ibcon#read 5, iclass 26, count 2 2006.201.20:39:51.40#ibcon#about to read 6, iclass 26, count 2 2006.201.20:39:51.40#ibcon#read 6, iclass 26, count 2 2006.201.20:39:51.40#ibcon#end of sib2, iclass 26, count 2 2006.201.20:39:51.40#ibcon#*mode == 0, iclass 26, count 2 2006.201.20:39:51.40#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.20:39:51.40#ibcon#[25=AT08-04\r\n] 2006.201.20:39:51.40#ibcon#*before write, iclass 26, count 2 2006.201.20:39:51.40#ibcon#enter sib2, iclass 26, count 2 2006.201.20:39:51.40#ibcon#flushed, iclass 26, count 2 2006.201.20:39:51.40#ibcon#about to write, iclass 26, count 2 2006.201.20:39:51.40#ibcon#wrote, iclass 26, count 2 2006.201.20:39:51.40#ibcon#about to read 3, iclass 26, count 2 2006.201.20:39:51.43#ibcon#read 3, iclass 26, count 2 2006.201.20:39:51.43#ibcon#about to read 4, iclass 26, count 2 2006.201.20:39:51.43#ibcon#read 4, iclass 26, count 2 2006.201.20:39:51.43#ibcon#about to read 5, iclass 26, count 2 2006.201.20:39:51.43#ibcon#read 5, iclass 26, count 2 2006.201.20:39:51.43#ibcon#about to read 6, iclass 26, count 2 2006.201.20:39:51.43#ibcon#read 6, iclass 26, count 2 2006.201.20:39:51.43#ibcon#end of sib2, iclass 26, count 2 2006.201.20:39:51.43#ibcon#*after write, iclass 26, count 2 2006.201.20:39:51.43#ibcon#*before return 0, iclass 26, count 2 2006.201.20:39:51.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:39:51.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:39:51.43#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.20:39:51.43#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:51.43#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:39:51.55#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:39:51.55#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:39:51.55#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:39:51.55#ibcon#first serial, iclass 26, count 0 2006.201.20:39:51.55#ibcon#enter sib2, iclass 26, count 0 2006.201.20:39:51.55#ibcon#flushed, iclass 26, count 0 2006.201.20:39:51.55#ibcon#about to write, iclass 26, count 0 2006.201.20:39:51.55#ibcon#wrote, iclass 26, count 0 2006.201.20:39:51.55#ibcon#about to read 3, iclass 26, count 0 2006.201.20:39:51.57#ibcon#read 3, iclass 26, count 0 2006.201.20:39:51.57#ibcon#about to read 4, iclass 26, count 0 2006.201.20:39:51.57#ibcon#read 4, iclass 26, count 0 2006.201.20:39:51.57#ibcon#about to read 5, iclass 26, count 0 2006.201.20:39:51.57#ibcon#read 5, iclass 26, count 0 2006.201.20:39:51.57#ibcon#about to read 6, iclass 26, count 0 2006.201.20:39:51.57#ibcon#read 6, iclass 26, count 0 2006.201.20:39:51.57#ibcon#end of sib2, iclass 26, count 0 2006.201.20:39:51.57#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:39:51.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:39:51.57#ibcon#[25=USB\r\n] 2006.201.20:39:51.57#ibcon#*before write, iclass 26, count 0 2006.201.20:39:51.57#ibcon#enter sib2, iclass 26, count 0 2006.201.20:39:51.57#ibcon#flushed, iclass 26, count 0 2006.201.20:39:51.57#ibcon#about to write, iclass 26, count 0 2006.201.20:39:51.57#ibcon#wrote, iclass 26, count 0 2006.201.20:39:51.57#ibcon#about to read 3, iclass 26, count 0 2006.201.20:39:51.60#ibcon#read 3, iclass 26, count 0 2006.201.20:39:51.60#ibcon#about to read 4, iclass 26, count 0 2006.201.20:39:51.60#ibcon#read 4, iclass 26, count 0 2006.201.20:39:51.60#ibcon#about to read 5, iclass 26, count 0 2006.201.20:39:51.60#ibcon#read 5, iclass 26, count 0 2006.201.20:39:51.60#ibcon#about to read 6, iclass 26, count 0 2006.201.20:39:51.60#ibcon#read 6, iclass 26, count 0 2006.201.20:39:51.60#ibcon#end of sib2, iclass 26, count 0 2006.201.20:39:51.60#ibcon#*after write, iclass 26, count 0 2006.201.20:39:51.60#ibcon#*before return 0, iclass 26, count 0 2006.201.20:39:51.60#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:39:51.60#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:39:51.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:39:51.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:39:51.60$vck44/vblo=1,629.99 2006.201.20:39:51.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.20:39:51.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.20:39:51.60#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:51.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:51.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:51.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:51.60#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:39:51.60#ibcon#first serial, iclass 28, count 0 2006.201.20:39:51.60#ibcon#enter sib2, iclass 28, count 0 2006.201.20:39:51.60#ibcon#flushed, iclass 28, count 0 2006.201.20:39:51.60#ibcon#about to write, iclass 28, count 0 2006.201.20:39:51.60#ibcon#wrote, iclass 28, count 0 2006.201.20:39:51.60#ibcon#about to read 3, iclass 28, count 0 2006.201.20:39:51.62#ibcon#read 3, iclass 28, count 0 2006.201.20:39:51.62#ibcon#about to read 4, iclass 28, count 0 2006.201.20:39:51.62#ibcon#read 4, iclass 28, count 0 2006.201.20:39:51.62#ibcon#about to read 5, iclass 28, count 0 2006.201.20:39:51.62#ibcon#read 5, iclass 28, count 0 2006.201.20:39:51.62#ibcon#about to read 6, iclass 28, count 0 2006.201.20:39:51.62#ibcon#read 6, iclass 28, count 0 2006.201.20:39:51.62#ibcon#end of sib2, iclass 28, count 0 2006.201.20:39:51.62#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:39:51.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:39:51.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:39:51.62#ibcon#*before write, iclass 28, count 0 2006.201.20:39:51.62#ibcon#enter sib2, iclass 28, count 0 2006.201.20:39:51.62#ibcon#flushed, iclass 28, count 0 2006.201.20:39:51.62#ibcon#about to write, iclass 28, count 0 2006.201.20:39:51.62#ibcon#wrote, iclass 28, count 0 2006.201.20:39:51.62#ibcon#about to read 3, iclass 28, count 0 2006.201.20:39:51.66#ibcon#read 3, iclass 28, count 0 2006.201.20:39:51.66#ibcon#about to read 4, iclass 28, count 0 2006.201.20:39:51.66#ibcon#read 4, iclass 28, count 0 2006.201.20:39:51.66#ibcon#about to read 5, iclass 28, count 0 2006.201.20:39:51.66#ibcon#read 5, iclass 28, count 0 2006.201.20:39:51.66#ibcon#about to read 6, iclass 28, count 0 2006.201.20:39:51.66#ibcon#read 6, iclass 28, count 0 2006.201.20:39:51.66#ibcon#end of sib2, iclass 28, count 0 2006.201.20:39:51.66#ibcon#*after write, iclass 28, count 0 2006.201.20:39:51.66#ibcon#*before return 0, iclass 28, count 0 2006.201.20:39:51.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:51.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:39:51.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:39:51.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:39:51.66$vck44/vb=1,4 2006.201.20:39:51.66#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.20:39:51.66#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.20:39:51.66#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:51.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:51.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:51.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:51.66#ibcon#enter wrdev, iclass 30, count 2 2006.201.20:39:51.66#ibcon#first serial, iclass 30, count 2 2006.201.20:39:51.66#ibcon#enter sib2, iclass 30, count 2 2006.201.20:39:51.66#ibcon#flushed, iclass 30, count 2 2006.201.20:39:51.66#ibcon#about to write, iclass 30, count 2 2006.201.20:39:51.66#ibcon#wrote, iclass 30, count 2 2006.201.20:39:51.66#ibcon#about to read 3, iclass 30, count 2 2006.201.20:39:51.68#ibcon#read 3, iclass 30, count 2 2006.201.20:39:51.68#ibcon#about to read 4, iclass 30, count 2 2006.201.20:39:51.68#ibcon#read 4, iclass 30, count 2 2006.201.20:39:51.68#ibcon#about to read 5, iclass 30, count 2 2006.201.20:39:51.68#ibcon#read 5, iclass 30, count 2 2006.201.20:39:51.68#ibcon#about to read 6, iclass 30, count 2 2006.201.20:39:51.68#ibcon#read 6, iclass 30, count 2 2006.201.20:39:51.68#ibcon#end of sib2, iclass 30, count 2 2006.201.20:39:51.68#ibcon#*mode == 0, iclass 30, count 2 2006.201.20:39:51.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.20:39:51.68#ibcon#[27=AT01-04\r\n] 2006.201.20:39:51.68#ibcon#*before write, iclass 30, count 2 2006.201.20:39:51.68#ibcon#enter sib2, iclass 30, count 2 2006.201.20:39:51.68#ibcon#flushed, iclass 30, count 2 2006.201.20:39:51.68#ibcon#about to write, iclass 30, count 2 2006.201.20:39:51.68#ibcon#wrote, iclass 30, count 2 2006.201.20:39:51.68#ibcon#about to read 3, iclass 30, count 2 2006.201.20:39:51.71#ibcon#read 3, iclass 30, count 2 2006.201.20:39:51.71#ibcon#about to read 4, iclass 30, count 2 2006.201.20:39:51.71#ibcon#read 4, iclass 30, count 2 2006.201.20:39:51.71#ibcon#about to read 5, iclass 30, count 2 2006.201.20:39:51.71#ibcon#read 5, iclass 30, count 2 2006.201.20:39:51.71#ibcon#about to read 6, iclass 30, count 2 2006.201.20:39:51.71#ibcon#read 6, iclass 30, count 2 2006.201.20:39:51.71#ibcon#end of sib2, iclass 30, count 2 2006.201.20:39:51.71#ibcon#*after write, iclass 30, count 2 2006.201.20:39:51.71#ibcon#*before return 0, iclass 30, count 2 2006.201.20:39:51.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:51.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:39:51.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.20:39:51.71#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:51.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:51.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:51.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:51.83#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:39:51.83#ibcon#first serial, iclass 30, count 0 2006.201.20:39:51.83#ibcon#enter sib2, iclass 30, count 0 2006.201.20:39:51.83#ibcon#flushed, iclass 30, count 0 2006.201.20:39:51.83#ibcon#about to write, iclass 30, count 0 2006.201.20:39:51.83#ibcon#wrote, iclass 30, count 0 2006.201.20:39:51.83#ibcon#about to read 3, iclass 30, count 0 2006.201.20:39:51.85#ibcon#read 3, iclass 30, count 0 2006.201.20:39:51.85#ibcon#about to read 4, iclass 30, count 0 2006.201.20:39:51.85#ibcon#read 4, iclass 30, count 0 2006.201.20:39:51.85#ibcon#about to read 5, iclass 30, count 0 2006.201.20:39:51.85#ibcon#read 5, iclass 30, count 0 2006.201.20:39:51.85#ibcon#about to read 6, iclass 30, count 0 2006.201.20:39:51.85#ibcon#read 6, iclass 30, count 0 2006.201.20:39:51.85#ibcon#end of sib2, iclass 30, count 0 2006.201.20:39:51.85#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:39:51.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:39:51.85#ibcon#[27=USB\r\n] 2006.201.20:39:51.85#ibcon#*before write, iclass 30, count 0 2006.201.20:39:51.85#ibcon#enter sib2, iclass 30, count 0 2006.201.20:39:51.85#ibcon#flushed, iclass 30, count 0 2006.201.20:39:51.85#ibcon#about to write, iclass 30, count 0 2006.201.20:39:51.85#ibcon#wrote, iclass 30, count 0 2006.201.20:39:51.85#ibcon#about to read 3, iclass 30, count 0 2006.201.20:39:51.88#ibcon#read 3, iclass 30, count 0 2006.201.20:39:51.88#ibcon#about to read 4, iclass 30, count 0 2006.201.20:39:51.88#ibcon#read 4, iclass 30, count 0 2006.201.20:39:51.88#ibcon#about to read 5, iclass 30, count 0 2006.201.20:39:51.88#ibcon#read 5, iclass 30, count 0 2006.201.20:39:51.88#ibcon#about to read 6, iclass 30, count 0 2006.201.20:39:51.88#ibcon#read 6, iclass 30, count 0 2006.201.20:39:51.88#ibcon#end of sib2, iclass 30, count 0 2006.201.20:39:51.88#ibcon#*after write, iclass 30, count 0 2006.201.20:39:51.88#ibcon#*before return 0, iclass 30, count 0 2006.201.20:39:51.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:51.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:39:51.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:39:51.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:39:51.88$vck44/vblo=2,634.99 2006.201.20:39:51.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.20:39:51.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.20:39:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:51.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:51.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:51.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:51.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:39:51.88#ibcon#first serial, iclass 32, count 0 2006.201.20:39:51.88#ibcon#enter sib2, iclass 32, count 0 2006.201.20:39:51.88#ibcon#flushed, iclass 32, count 0 2006.201.20:39:51.88#ibcon#about to write, iclass 32, count 0 2006.201.20:39:51.88#ibcon#wrote, iclass 32, count 0 2006.201.20:39:51.88#ibcon#about to read 3, iclass 32, count 0 2006.201.20:39:51.90#ibcon#read 3, iclass 32, count 0 2006.201.20:39:51.90#ibcon#about to read 4, iclass 32, count 0 2006.201.20:39:51.90#ibcon#read 4, iclass 32, count 0 2006.201.20:39:51.90#ibcon#about to read 5, iclass 32, count 0 2006.201.20:39:51.90#ibcon#read 5, iclass 32, count 0 2006.201.20:39:51.90#ibcon#about to read 6, iclass 32, count 0 2006.201.20:39:51.90#ibcon#read 6, iclass 32, count 0 2006.201.20:39:51.90#ibcon#end of sib2, iclass 32, count 0 2006.201.20:39:51.90#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:39:51.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:39:51.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:39:51.90#ibcon#*before write, iclass 32, count 0 2006.201.20:39:51.90#ibcon#enter sib2, iclass 32, count 0 2006.201.20:39:51.90#ibcon#flushed, iclass 32, count 0 2006.201.20:39:51.90#ibcon#about to write, iclass 32, count 0 2006.201.20:39:51.90#ibcon#wrote, iclass 32, count 0 2006.201.20:39:51.90#ibcon#about to read 3, iclass 32, count 0 2006.201.20:39:51.94#ibcon#read 3, iclass 32, count 0 2006.201.20:39:51.94#ibcon#about to read 4, iclass 32, count 0 2006.201.20:39:51.94#ibcon#read 4, iclass 32, count 0 2006.201.20:39:51.94#ibcon#about to read 5, iclass 32, count 0 2006.201.20:39:51.94#ibcon#read 5, iclass 32, count 0 2006.201.20:39:51.94#ibcon#about to read 6, iclass 32, count 0 2006.201.20:39:51.94#ibcon#read 6, iclass 32, count 0 2006.201.20:39:51.94#ibcon#end of sib2, iclass 32, count 0 2006.201.20:39:51.94#ibcon#*after write, iclass 32, count 0 2006.201.20:39:51.94#ibcon#*before return 0, iclass 32, count 0 2006.201.20:39:51.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:51.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:39:51.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:39:51.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:39:51.94$vck44/vb=2,5 2006.201.20:39:51.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.20:39:51.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.20:39:51.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:51.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:52.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:52.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:52.00#ibcon#enter wrdev, iclass 34, count 2 2006.201.20:39:52.00#ibcon#first serial, iclass 34, count 2 2006.201.20:39:52.00#ibcon#enter sib2, iclass 34, count 2 2006.201.20:39:52.00#ibcon#flushed, iclass 34, count 2 2006.201.20:39:52.00#ibcon#about to write, iclass 34, count 2 2006.201.20:39:52.00#ibcon#wrote, iclass 34, count 2 2006.201.20:39:52.00#ibcon#about to read 3, iclass 34, count 2 2006.201.20:39:52.02#ibcon#read 3, iclass 34, count 2 2006.201.20:39:52.02#ibcon#about to read 4, iclass 34, count 2 2006.201.20:39:52.02#ibcon#read 4, iclass 34, count 2 2006.201.20:39:52.02#ibcon#about to read 5, iclass 34, count 2 2006.201.20:39:52.02#ibcon#read 5, iclass 34, count 2 2006.201.20:39:52.02#ibcon#about to read 6, iclass 34, count 2 2006.201.20:39:52.02#ibcon#read 6, iclass 34, count 2 2006.201.20:39:52.02#ibcon#end of sib2, iclass 34, count 2 2006.201.20:39:52.02#ibcon#*mode == 0, iclass 34, count 2 2006.201.20:39:52.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.20:39:52.02#ibcon#[27=AT02-05\r\n] 2006.201.20:39:52.02#ibcon#*before write, iclass 34, count 2 2006.201.20:39:52.02#ibcon#enter sib2, iclass 34, count 2 2006.201.20:39:52.02#ibcon#flushed, iclass 34, count 2 2006.201.20:39:52.02#ibcon#about to write, iclass 34, count 2 2006.201.20:39:52.02#ibcon#wrote, iclass 34, count 2 2006.201.20:39:52.02#ibcon#about to read 3, iclass 34, count 2 2006.201.20:39:52.05#ibcon#read 3, iclass 34, count 2 2006.201.20:39:52.05#ibcon#about to read 4, iclass 34, count 2 2006.201.20:39:52.05#ibcon#read 4, iclass 34, count 2 2006.201.20:39:52.05#ibcon#about to read 5, iclass 34, count 2 2006.201.20:39:52.05#ibcon#read 5, iclass 34, count 2 2006.201.20:39:52.05#ibcon#about to read 6, iclass 34, count 2 2006.201.20:39:52.05#ibcon#read 6, iclass 34, count 2 2006.201.20:39:52.05#ibcon#end of sib2, iclass 34, count 2 2006.201.20:39:52.05#ibcon#*after write, iclass 34, count 2 2006.201.20:39:52.05#ibcon#*before return 0, iclass 34, count 2 2006.201.20:39:52.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:52.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:39:52.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.20:39:52.05#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:52.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:52.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:52.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:52.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:39:52.17#ibcon#first serial, iclass 34, count 0 2006.201.20:39:52.17#ibcon#enter sib2, iclass 34, count 0 2006.201.20:39:52.17#ibcon#flushed, iclass 34, count 0 2006.201.20:39:52.17#ibcon#about to write, iclass 34, count 0 2006.201.20:39:52.17#ibcon#wrote, iclass 34, count 0 2006.201.20:39:52.17#ibcon#about to read 3, iclass 34, count 0 2006.201.20:39:52.19#ibcon#read 3, iclass 34, count 0 2006.201.20:39:52.19#ibcon#about to read 4, iclass 34, count 0 2006.201.20:39:52.19#ibcon#read 4, iclass 34, count 0 2006.201.20:39:52.19#ibcon#about to read 5, iclass 34, count 0 2006.201.20:39:52.19#ibcon#read 5, iclass 34, count 0 2006.201.20:39:52.19#ibcon#about to read 6, iclass 34, count 0 2006.201.20:39:52.19#ibcon#read 6, iclass 34, count 0 2006.201.20:39:52.19#ibcon#end of sib2, iclass 34, count 0 2006.201.20:39:52.19#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:39:52.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:39:52.19#ibcon#[27=USB\r\n] 2006.201.20:39:52.19#ibcon#*before write, iclass 34, count 0 2006.201.20:39:52.19#ibcon#enter sib2, iclass 34, count 0 2006.201.20:39:52.19#ibcon#flushed, iclass 34, count 0 2006.201.20:39:52.19#ibcon#about to write, iclass 34, count 0 2006.201.20:39:52.19#ibcon#wrote, iclass 34, count 0 2006.201.20:39:52.19#ibcon#about to read 3, iclass 34, count 0 2006.201.20:39:52.22#ibcon#read 3, iclass 34, count 0 2006.201.20:39:52.22#ibcon#about to read 4, iclass 34, count 0 2006.201.20:39:52.22#ibcon#read 4, iclass 34, count 0 2006.201.20:39:52.22#ibcon#about to read 5, iclass 34, count 0 2006.201.20:39:52.22#ibcon#read 5, iclass 34, count 0 2006.201.20:39:52.22#ibcon#about to read 6, iclass 34, count 0 2006.201.20:39:52.22#ibcon#read 6, iclass 34, count 0 2006.201.20:39:52.22#ibcon#end of sib2, iclass 34, count 0 2006.201.20:39:52.22#ibcon#*after write, iclass 34, count 0 2006.201.20:39:52.22#ibcon#*before return 0, iclass 34, count 0 2006.201.20:39:52.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:52.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:39:52.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:39:52.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:39:52.22$vck44/vblo=3,649.99 2006.201.20:39:52.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.20:39:52.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.20:39:52.22#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:52.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:52.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:52.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:52.22#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:39:52.22#ibcon#first serial, iclass 36, count 0 2006.201.20:39:52.22#ibcon#enter sib2, iclass 36, count 0 2006.201.20:39:52.22#ibcon#flushed, iclass 36, count 0 2006.201.20:39:52.22#ibcon#about to write, iclass 36, count 0 2006.201.20:39:52.22#ibcon#wrote, iclass 36, count 0 2006.201.20:39:52.22#ibcon#about to read 3, iclass 36, count 0 2006.201.20:39:52.24#ibcon#read 3, iclass 36, count 0 2006.201.20:39:52.24#ibcon#about to read 4, iclass 36, count 0 2006.201.20:39:52.24#ibcon#read 4, iclass 36, count 0 2006.201.20:39:52.24#ibcon#about to read 5, iclass 36, count 0 2006.201.20:39:52.24#ibcon#read 5, iclass 36, count 0 2006.201.20:39:52.24#ibcon#about to read 6, iclass 36, count 0 2006.201.20:39:52.24#ibcon#read 6, iclass 36, count 0 2006.201.20:39:52.24#ibcon#end of sib2, iclass 36, count 0 2006.201.20:39:52.24#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:39:52.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:39:52.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:39:52.24#ibcon#*before write, iclass 36, count 0 2006.201.20:39:52.24#ibcon#enter sib2, iclass 36, count 0 2006.201.20:39:52.24#ibcon#flushed, iclass 36, count 0 2006.201.20:39:52.24#ibcon#about to write, iclass 36, count 0 2006.201.20:39:52.24#ibcon#wrote, iclass 36, count 0 2006.201.20:39:52.24#ibcon#about to read 3, iclass 36, count 0 2006.201.20:39:52.28#ibcon#read 3, iclass 36, count 0 2006.201.20:39:52.28#ibcon#about to read 4, iclass 36, count 0 2006.201.20:39:52.28#ibcon#read 4, iclass 36, count 0 2006.201.20:39:52.28#ibcon#about to read 5, iclass 36, count 0 2006.201.20:39:52.28#ibcon#read 5, iclass 36, count 0 2006.201.20:39:52.28#ibcon#about to read 6, iclass 36, count 0 2006.201.20:39:52.28#ibcon#read 6, iclass 36, count 0 2006.201.20:39:52.28#ibcon#end of sib2, iclass 36, count 0 2006.201.20:39:52.28#ibcon#*after write, iclass 36, count 0 2006.201.20:39:52.28#ibcon#*before return 0, iclass 36, count 0 2006.201.20:39:52.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:52.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:39:52.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:39:52.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:39:52.28$vck44/vb=3,4 2006.201.20:39:52.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.20:39:52.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.20:39:52.28#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:52.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:52.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:52.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:52.34#ibcon#enter wrdev, iclass 38, count 2 2006.201.20:39:52.34#ibcon#first serial, iclass 38, count 2 2006.201.20:39:52.34#ibcon#enter sib2, iclass 38, count 2 2006.201.20:39:52.34#ibcon#flushed, iclass 38, count 2 2006.201.20:39:52.34#ibcon#about to write, iclass 38, count 2 2006.201.20:39:52.34#ibcon#wrote, iclass 38, count 2 2006.201.20:39:52.34#ibcon#about to read 3, iclass 38, count 2 2006.201.20:39:52.36#ibcon#read 3, iclass 38, count 2 2006.201.20:39:52.36#ibcon#about to read 4, iclass 38, count 2 2006.201.20:39:52.36#ibcon#read 4, iclass 38, count 2 2006.201.20:39:52.36#ibcon#about to read 5, iclass 38, count 2 2006.201.20:39:52.36#ibcon#read 5, iclass 38, count 2 2006.201.20:39:52.36#ibcon#about to read 6, iclass 38, count 2 2006.201.20:39:52.36#ibcon#read 6, iclass 38, count 2 2006.201.20:39:52.36#ibcon#end of sib2, iclass 38, count 2 2006.201.20:39:52.36#ibcon#*mode == 0, iclass 38, count 2 2006.201.20:39:52.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.20:39:52.36#ibcon#[27=AT03-04\r\n] 2006.201.20:39:52.36#ibcon#*before write, iclass 38, count 2 2006.201.20:39:52.36#ibcon#enter sib2, iclass 38, count 2 2006.201.20:39:52.36#ibcon#flushed, iclass 38, count 2 2006.201.20:39:52.36#ibcon#about to write, iclass 38, count 2 2006.201.20:39:52.36#ibcon#wrote, iclass 38, count 2 2006.201.20:39:52.36#ibcon#about to read 3, iclass 38, count 2 2006.201.20:39:52.39#ibcon#read 3, iclass 38, count 2 2006.201.20:39:52.39#ibcon#about to read 4, iclass 38, count 2 2006.201.20:39:52.39#ibcon#read 4, iclass 38, count 2 2006.201.20:39:52.39#ibcon#about to read 5, iclass 38, count 2 2006.201.20:39:52.39#ibcon#read 5, iclass 38, count 2 2006.201.20:39:52.39#ibcon#about to read 6, iclass 38, count 2 2006.201.20:39:52.39#ibcon#read 6, iclass 38, count 2 2006.201.20:39:52.39#ibcon#end of sib2, iclass 38, count 2 2006.201.20:39:52.39#ibcon#*after write, iclass 38, count 2 2006.201.20:39:52.39#ibcon#*before return 0, iclass 38, count 2 2006.201.20:39:52.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:52.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:39:52.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.20:39:52.39#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:52.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:52.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:52.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:52.51#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:39:52.51#ibcon#first serial, iclass 38, count 0 2006.201.20:39:52.51#ibcon#enter sib2, iclass 38, count 0 2006.201.20:39:52.51#ibcon#flushed, iclass 38, count 0 2006.201.20:39:52.51#ibcon#about to write, iclass 38, count 0 2006.201.20:39:52.51#ibcon#wrote, iclass 38, count 0 2006.201.20:39:52.51#ibcon#about to read 3, iclass 38, count 0 2006.201.20:39:52.53#ibcon#read 3, iclass 38, count 0 2006.201.20:39:52.53#ibcon#about to read 4, iclass 38, count 0 2006.201.20:39:52.53#ibcon#read 4, iclass 38, count 0 2006.201.20:39:52.53#ibcon#about to read 5, iclass 38, count 0 2006.201.20:39:52.53#ibcon#read 5, iclass 38, count 0 2006.201.20:39:52.53#ibcon#about to read 6, iclass 38, count 0 2006.201.20:39:52.53#ibcon#read 6, iclass 38, count 0 2006.201.20:39:52.53#ibcon#end of sib2, iclass 38, count 0 2006.201.20:39:52.53#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:39:52.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:39:52.53#ibcon#[27=USB\r\n] 2006.201.20:39:52.53#ibcon#*before write, iclass 38, count 0 2006.201.20:39:52.53#ibcon#enter sib2, iclass 38, count 0 2006.201.20:39:52.53#ibcon#flushed, iclass 38, count 0 2006.201.20:39:52.53#ibcon#about to write, iclass 38, count 0 2006.201.20:39:52.53#ibcon#wrote, iclass 38, count 0 2006.201.20:39:52.53#ibcon#about to read 3, iclass 38, count 0 2006.201.20:39:52.56#ibcon#read 3, iclass 38, count 0 2006.201.20:39:52.56#ibcon#about to read 4, iclass 38, count 0 2006.201.20:39:52.56#ibcon#read 4, iclass 38, count 0 2006.201.20:39:52.56#ibcon#about to read 5, iclass 38, count 0 2006.201.20:39:52.56#ibcon#read 5, iclass 38, count 0 2006.201.20:39:52.56#ibcon#about to read 6, iclass 38, count 0 2006.201.20:39:52.56#ibcon#read 6, iclass 38, count 0 2006.201.20:39:52.56#ibcon#end of sib2, iclass 38, count 0 2006.201.20:39:52.56#ibcon#*after write, iclass 38, count 0 2006.201.20:39:52.56#ibcon#*before return 0, iclass 38, count 0 2006.201.20:39:52.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:52.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:39:52.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:39:52.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:39:52.56$vck44/vblo=4,679.99 2006.201.20:39:52.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.20:39:52.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.20:39:52.56#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:52.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:39:52.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:39:52.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:39:52.56#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:39:52.56#ibcon#first serial, iclass 40, count 0 2006.201.20:39:52.56#ibcon#enter sib2, iclass 40, count 0 2006.201.20:39:52.56#ibcon#flushed, iclass 40, count 0 2006.201.20:39:52.56#ibcon#about to write, iclass 40, count 0 2006.201.20:39:52.56#ibcon#wrote, iclass 40, count 0 2006.201.20:39:52.56#ibcon#about to read 3, iclass 40, count 0 2006.201.20:39:52.58#ibcon#read 3, iclass 40, count 0 2006.201.20:39:52.58#ibcon#about to read 4, iclass 40, count 0 2006.201.20:39:52.58#ibcon#read 4, iclass 40, count 0 2006.201.20:39:52.58#ibcon#about to read 5, iclass 40, count 0 2006.201.20:39:52.58#ibcon#read 5, iclass 40, count 0 2006.201.20:39:52.58#ibcon#about to read 6, iclass 40, count 0 2006.201.20:39:52.58#ibcon#read 6, iclass 40, count 0 2006.201.20:39:52.58#ibcon#end of sib2, iclass 40, count 0 2006.201.20:39:52.58#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:39:52.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:39:52.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:39:52.58#ibcon#*before write, iclass 40, count 0 2006.201.20:39:52.58#ibcon#enter sib2, iclass 40, count 0 2006.201.20:39:52.58#ibcon#flushed, iclass 40, count 0 2006.201.20:39:52.58#ibcon#about to write, iclass 40, count 0 2006.201.20:39:52.58#ibcon#wrote, iclass 40, count 0 2006.201.20:39:52.58#ibcon#about to read 3, iclass 40, count 0 2006.201.20:39:52.62#ibcon#read 3, iclass 40, count 0 2006.201.20:39:52.62#ibcon#about to read 4, iclass 40, count 0 2006.201.20:39:52.62#ibcon#read 4, iclass 40, count 0 2006.201.20:39:52.62#ibcon#about to read 5, iclass 40, count 0 2006.201.20:39:52.62#ibcon#read 5, iclass 40, count 0 2006.201.20:39:52.62#ibcon#about to read 6, iclass 40, count 0 2006.201.20:39:52.62#ibcon#read 6, iclass 40, count 0 2006.201.20:39:52.62#ibcon#end of sib2, iclass 40, count 0 2006.201.20:39:52.62#ibcon#*after write, iclass 40, count 0 2006.201.20:39:52.62#ibcon#*before return 0, iclass 40, count 0 2006.201.20:39:52.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:39:52.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:39:52.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:39:52.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:39:52.62$vck44/vb=4,5 2006.201.20:39:52.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.20:39:52.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.20:39:52.62#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:52.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:39:52.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:39:52.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:39:52.68#ibcon#enter wrdev, iclass 4, count 2 2006.201.20:39:52.68#ibcon#first serial, iclass 4, count 2 2006.201.20:39:52.68#ibcon#enter sib2, iclass 4, count 2 2006.201.20:39:52.68#ibcon#flushed, iclass 4, count 2 2006.201.20:39:52.68#ibcon#about to write, iclass 4, count 2 2006.201.20:39:52.68#ibcon#wrote, iclass 4, count 2 2006.201.20:39:52.68#ibcon#about to read 3, iclass 4, count 2 2006.201.20:39:52.70#ibcon#read 3, iclass 4, count 2 2006.201.20:39:52.70#ibcon#about to read 4, iclass 4, count 2 2006.201.20:39:52.70#ibcon#read 4, iclass 4, count 2 2006.201.20:39:52.70#ibcon#about to read 5, iclass 4, count 2 2006.201.20:39:52.70#ibcon#read 5, iclass 4, count 2 2006.201.20:39:52.70#ibcon#about to read 6, iclass 4, count 2 2006.201.20:39:52.70#ibcon#read 6, iclass 4, count 2 2006.201.20:39:52.70#ibcon#end of sib2, iclass 4, count 2 2006.201.20:39:52.70#ibcon#*mode == 0, iclass 4, count 2 2006.201.20:39:52.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.20:39:52.70#ibcon#[27=AT04-05\r\n] 2006.201.20:39:52.70#ibcon#*before write, iclass 4, count 2 2006.201.20:39:52.70#ibcon#enter sib2, iclass 4, count 2 2006.201.20:39:52.70#ibcon#flushed, iclass 4, count 2 2006.201.20:39:52.70#ibcon#about to write, iclass 4, count 2 2006.201.20:39:52.70#ibcon#wrote, iclass 4, count 2 2006.201.20:39:52.70#ibcon#about to read 3, iclass 4, count 2 2006.201.20:39:52.73#ibcon#read 3, iclass 4, count 2 2006.201.20:39:52.73#ibcon#about to read 4, iclass 4, count 2 2006.201.20:39:52.73#ibcon#read 4, iclass 4, count 2 2006.201.20:39:52.73#ibcon#about to read 5, iclass 4, count 2 2006.201.20:39:52.73#ibcon#read 5, iclass 4, count 2 2006.201.20:39:52.73#ibcon#about to read 6, iclass 4, count 2 2006.201.20:39:52.73#ibcon#read 6, iclass 4, count 2 2006.201.20:39:52.73#ibcon#end of sib2, iclass 4, count 2 2006.201.20:39:52.73#ibcon#*after write, iclass 4, count 2 2006.201.20:39:52.73#ibcon#*before return 0, iclass 4, count 2 2006.201.20:39:52.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:39:52.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:39:52.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.20:39:52.73#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:52.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:39:52.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:39:52.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:39:52.85#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:39:52.85#ibcon#first serial, iclass 4, count 0 2006.201.20:39:52.85#ibcon#enter sib2, iclass 4, count 0 2006.201.20:39:52.85#ibcon#flushed, iclass 4, count 0 2006.201.20:39:52.85#ibcon#about to write, iclass 4, count 0 2006.201.20:39:52.85#ibcon#wrote, iclass 4, count 0 2006.201.20:39:52.85#ibcon#about to read 3, iclass 4, count 0 2006.201.20:39:52.87#ibcon#read 3, iclass 4, count 0 2006.201.20:39:52.87#ibcon#about to read 4, iclass 4, count 0 2006.201.20:39:52.87#ibcon#read 4, iclass 4, count 0 2006.201.20:39:52.87#ibcon#about to read 5, iclass 4, count 0 2006.201.20:39:52.87#ibcon#read 5, iclass 4, count 0 2006.201.20:39:52.87#ibcon#about to read 6, iclass 4, count 0 2006.201.20:39:52.87#ibcon#read 6, iclass 4, count 0 2006.201.20:39:52.87#ibcon#end of sib2, iclass 4, count 0 2006.201.20:39:52.87#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:39:52.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:39:52.87#ibcon#[27=USB\r\n] 2006.201.20:39:52.87#ibcon#*before write, iclass 4, count 0 2006.201.20:39:52.87#ibcon#enter sib2, iclass 4, count 0 2006.201.20:39:52.87#ibcon#flushed, iclass 4, count 0 2006.201.20:39:52.87#ibcon#about to write, iclass 4, count 0 2006.201.20:39:52.87#ibcon#wrote, iclass 4, count 0 2006.201.20:39:52.87#ibcon#about to read 3, iclass 4, count 0 2006.201.20:39:52.90#ibcon#read 3, iclass 4, count 0 2006.201.20:39:52.90#ibcon#about to read 4, iclass 4, count 0 2006.201.20:39:52.90#ibcon#read 4, iclass 4, count 0 2006.201.20:39:52.90#ibcon#about to read 5, iclass 4, count 0 2006.201.20:39:52.90#ibcon#read 5, iclass 4, count 0 2006.201.20:39:52.90#ibcon#about to read 6, iclass 4, count 0 2006.201.20:39:52.90#ibcon#read 6, iclass 4, count 0 2006.201.20:39:52.90#ibcon#end of sib2, iclass 4, count 0 2006.201.20:39:52.90#ibcon#*after write, iclass 4, count 0 2006.201.20:39:52.90#ibcon#*before return 0, iclass 4, count 0 2006.201.20:39:52.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:39:52.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:39:52.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:39:52.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:39:52.90$vck44/vblo=5,709.99 2006.201.20:39:52.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.20:39:52.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.20:39:52.90#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:52.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:52.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:52.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:52.90#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:39:52.90#ibcon#first serial, iclass 6, count 0 2006.201.20:39:52.90#ibcon#enter sib2, iclass 6, count 0 2006.201.20:39:52.90#ibcon#flushed, iclass 6, count 0 2006.201.20:39:52.90#ibcon#about to write, iclass 6, count 0 2006.201.20:39:52.90#ibcon#wrote, iclass 6, count 0 2006.201.20:39:52.90#ibcon#about to read 3, iclass 6, count 0 2006.201.20:39:52.92#ibcon#read 3, iclass 6, count 0 2006.201.20:39:52.92#ibcon#about to read 4, iclass 6, count 0 2006.201.20:39:52.92#ibcon#read 4, iclass 6, count 0 2006.201.20:39:52.92#ibcon#about to read 5, iclass 6, count 0 2006.201.20:39:52.92#ibcon#read 5, iclass 6, count 0 2006.201.20:39:52.92#ibcon#about to read 6, iclass 6, count 0 2006.201.20:39:52.92#ibcon#read 6, iclass 6, count 0 2006.201.20:39:52.92#ibcon#end of sib2, iclass 6, count 0 2006.201.20:39:52.92#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:39:52.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:39:52.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:39:52.92#ibcon#*before write, iclass 6, count 0 2006.201.20:39:52.92#ibcon#enter sib2, iclass 6, count 0 2006.201.20:39:52.92#ibcon#flushed, iclass 6, count 0 2006.201.20:39:52.92#ibcon#about to write, iclass 6, count 0 2006.201.20:39:52.92#ibcon#wrote, iclass 6, count 0 2006.201.20:39:52.92#ibcon#about to read 3, iclass 6, count 0 2006.201.20:39:52.96#ibcon#read 3, iclass 6, count 0 2006.201.20:39:52.96#ibcon#about to read 4, iclass 6, count 0 2006.201.20:39:52.96#ibcon#read 4, iclass 6, count 0 2006.201.20:39:52.96#ibcon#about to read 5, iclass 6, count 0 2006.201.20:39:52.96#ibcon#read 5, iclass 6, count 0 2006.201.20:39:52.96#ibcon#about to read 6, iclass 6, count 0 2006.201.20:39:52.96#ibcon#read 6, iclass 6, count 0 2006.201.20:39:52.96#ibcon#end of sib2, iclass 6, count 0 2006.201.20:39:52.96#ibcon#*after write, iclass 6, count 0 2006.201.20:39:52.96#ibcon#*before return 0, iclass 6, count 0 2006.201.20:39:52.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:52.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:39:52.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:39:52.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:39:52.96$vck44/vb=5,4 2006.201.20:39:52.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.20:39:52.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.20:39:52.96#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:52.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:53.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:53.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:53.02#ibcon#enter wrdev, iclass 10, count 2 2006.201.20:39:53.02#ibcon#first serial, iclass 10, count 2 2006.201.20:39:53.02#ibcon#enter sib2, iclass 10, count 2 2006.201.20:39:53.02#ibcon#flushed, iclass 10, count 2 2006.201.20:39:53.02#ibcon#about to write, iclass 10, count 2 2006.201.20:39:53.02#ibcon#wrote, iclass 10, count 2 2006.201.20:39:53.02#ibcon#about to read 3, iclass 10, count 2 2006.201.20:39:53.04#ibcon#read 3, iclass 10, count 2 2006.201.20:39:53.04#ibcon#about to read 4, iclass 10, count 2 2006.201.20:39:53.04#ibcon#read 4, iclass 10, count 2 2006.201.20:39:53.04#ibcon#about to read 5, iclass 10, count 2 2006.201.20:39:53.04#ibcon#read 5, iclass 10, count 2 2006.201.20:39:53.04#ibcon#about to read 6, iclass 10, count 2 2006.201.20:39:53.04#ibcon#read 6, iclass 10, count 2 2006.201.20:39:53.04#ibcon#end of sib2, iclass 10, count 2 2006.201.20:39:53.04#ibcon#*mode == 0, iclass 10, count 2 2006.201.20:39:53.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.20:39:53.04#ibcon#[27=AT05-04\r\n] 2006.201.20:39:53.04#ibcon#*before write, iclass 10, count 2 2006.201.20:39:53.04#ibcon#enter sib2, iclass 10, count 2 2006.201.20:39:53.04#ibcon#flushed, iclass 10, count 2 2006.201.20:39:53.04#ibcon#about to write, iclass 10, count 2 2006.201.20:39:53.04#ibcon#wrote, iclass 10, count 2 2006.201.20:39:53.04#ibcon#about to read 3, iclass 10, count 2 2006.201.20:39:53.07#ibcon#read 3, iclass 10, count 2 2006.201.20:39:53.07#ibcon#about to read 4, iclass 10, count 2 2006.201.20:39:53.07#ibcon#read 4, iclass 10, count 2 2006.201.20:39:53.07#ibcon#about to read 5, iclass 10, count 2 2006.201.20:39:53.07#ibcon#read 5, iclass 10, count 2 2006.201.20:39:53.07#ibcon#about to read 6, iclass 10, count 2 2006.201.20:39:53.07#ibcon#read 6, iclass 10, count 2 2006.201.20:39:53.07#ibcon#end of sib2, iclass 10, count 2 2006.201.20:39:53.07#ibcon#*after write, iclass 10, count 2 2006.201.20:39:53.07#ibcon#*before return 0, iclass 10, count 2 2006.201.20:39:53.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:53.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:39:53.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.20:39:53.07#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:53.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:53.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:53.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:53.19#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:39:53.19#ibcon#first serial, iclass 10, count 0 2006.201.20:39:53.19#ibcon#enter sib2, iclass 10, count 0 2006.201.20:39:53.19#ibcon#flushed, iclass 10, count 0 2006.201.20:39:53.19#ibcon#about to write, iclass 10, count 0 2006.201.20:39:53.19#ibcon#wrote, iclass 10, count 0 2006.201.20:39:53.19#ibcon#about to read 3, iclass 10, count 0 2006.201.20:39:53.21#ibcon#read 3, iclass 10, count 0 2006.201.20:39:53.21#ibcon#about to read 4, iclass 10, count 0 2006.201.20:39:53.21#ibcon#read 4, iclass 10, count 0 2006.201.20:39:53.21#ibcon#about to read 5, iclass 10, count 0 2006.201.20:39:53.21#ibcon#read 5, iclass 10, count 0 2006.201.20:39:53.21#ibcon#about to read 6, iclass 10, count 0 2006.201.20:39:53.21#ibcon#read 6, iclass 10, count 0 2006.201.20:39:53.21#ibcon#end of sib2, iclass 10, count 0 2006.201.20:39:53.21#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:39:53.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:39:53.21#ibcon#[27=USB\r\n] 2006.201.20:39:53.21#ibcon#*before write, iclass 10, count 0 2006.201.20:39:53.21#ibcon#enter sib2, iclass 10, count 0 2006.201.20:39:53.21#ibcon#flushed, iclass 10, count 0 2006.201.20:39:53.21#ibcon#about to write, iclass 10, count 0 2006.201.20:39:53.21#ibcon#wrote, iclass 10, count 0 2006.201.20:39:53.21#ibcon#about to read 3, iclass 10, count 0 2006.201.20:39:53.24#ibcon#read 3, iclass 10, count 0 2006.201.20:39:53.24#ibcon#about to read 4, iclass 10, count 0 2006.201.20:39:53.24#ibcon#read 4, iclass 10, count 0 2006.201.20:39:53.24#ibcon#about to read 5, iclass 10, count 0 2006.201.20:39:53.24#ibcon#read 5, iclass 10, count 0 2006.201.20:39:53.24#ibcon#about to read 6, iclass 10, count 0 2006.201.20:39:53.24#ibcon#read 6, iclass 10, count 0 2006.201.20:39:53.24#ibcon#end of sib2, iclass 10, count 0 2006.201.20:39:53.24#ibcon#*after write, iclass 10, count 0 2006.201.20:39:53.24#ibcon#*before return 0, iclass 10, count 0 2006.201.20:39:53.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:53.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:39:53.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:39:53.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:39:53.24$vck44/vblo=6,719.99 2006.201.20:39:53.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.20:39:53.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.20:39:53.24#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:53.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:53.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:53.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:53.24#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:39:53.24#ibcon#first serial, iclass 12, count 0 2006.201.20:39:53.24#ibcon#enter sib2, iclass 12, count 0 2006.201.20:39:53.24#ibcon#flushed, iclass 12, count 0 2006.201.20:39:53.24#ibcon#about to write, iclass 12, count 0 2006.201.20:39:53.24#ibcon#wrote, iclass 12, count 0 2006.201.20:39:53.24#ibcon#about to read 3, iclass 12, count 0 2006.201.20:39:53.26#ibcon#read 3, iclass 12, count 0 2006.201.20:39:53.26#ibcon#about to read 4, iclass 12, count 0 2006.201.20:39:53.26#ibcon#read 4, iclass 12, count 0 2006.201.20:39:53.26#ibcon#about to read 5, iclass 12, count 0 2006.201.20:39:53.26#ibcon#read 5, iclass 12, count 0 2006.201.20:39:53.26#ibcon#about to read 6, iclass 12, count 0 2006.201.20:39:53.26#ibcon#read 6, iclass 12, count 0 2006.201.20:39:53.26#ibcon#end of sib2, iclass 12, count 0 2006.201.20:39:53.26#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:39:53.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:39:53.26#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:39:53.26#ibcon#*before write, iclass 12, count 0 2006.201.20:39:53.26#ibcon#enter sib2, iclass 12, count 0 2006.201.20:39:53.26#ibcon#flushed, iclass 12, count 0 2006.201.20:39:53.26#ibcon#about to write, iclass 12, count 0 2006.201.20:39:53.26#ibcon#wrote, iclass 12, count 0 2006.201.20:39:53.26#ibcon#about to read 3, iclass 12, count 0 2006.201.20:39:53.31#ibcon#read 3, iclass 12, count 0 2006.201.20:39:53.31#ibcon#about to read 4, iclass 12, count 0 2006.201.20:39:53.31#ibcon#read 4, iclass 12, count 0 2006.201.20:39:53.31#ibcon#about to read 5, iclass 12, count 0 2006.201.20:39:53.31#ibcon#read 5, iclass 12, count 0 2006.201.20:39:53.31#ibcon#about to read 6, iclass 12, count 0 2006.201.20:39:53.31#ibcon#read 6, iclass 12, count 0 2006.201.20:39:53.31#ibcon#end of sib2, iclass 12, count 0 2006.201.20:39:53.31#ibcon#*after write, iclass 12, count 0 2006.201.20:39:53.31#ibcon#*before return 0, iclass 12, count 0 2006.201.20:39:53.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:53.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:39:53.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:39:53.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:39:53.31$vck44/vb=6,4 2006.201.20:39:53.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.20:39:53.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.20:39:53.31#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:53.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:53.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:53.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:53.36#ibcon#enter wrdev, iclass 14, count 2 2006.201.20:39:53.36#ibcon#first serial, iclass 14, count 2 2006.201.20:39:53.36#ibcon#enter sib2, iclass 14, count 2 2006.201.20:39:53.36#ibcon#flushed, iclass 14, count 2 2006.201.20:39:53.36#ibcon#about to write, iclass 14, count 2 2006.201.20:39:53.36#ibcon#wrote, iclass 14, count 2 2006.201.20:39:53.36#ibcon#about to read 3, iclass 14, count 2 2006.201.20:39:53.38#ibcon#read 3, iclass 14, count 2 2006.201.20:39:53.38#ibcon#about to read 4, iclass 14, count 2 2006.201.20:39:53.38#ibcon#read 4, iclass 14, count 2 2006.201.20:39:53.38#ibcon#about to read 5, iclass 14, count 2 2006.201.20:39:53.38#ibcon#read 5, iclass 14, count 2 2006.201.20:39:53.38#ibcon#about to read 6, iclass 14, count 2 2006.201.20:39:53.38#ibcon#read 6, iclass 14, count 2 2006.201.20:39:53.38#ibcon#end of sib2, iclass 14, count 2 2006.201.20:39:53.38#ibcon#*mode == 0, iclass 14, count 2 2006.201.20:39:53.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.20:39:53.38#ibcon#[27=AT06-04\r\n] 2006.201.20:39:53.38#ibcon#*before write, iclass 14, count 2 2006.201.20:39:53.38#ibcon#enter sib2, iclass 14, count 2 2006.201.20:39:53.38#ibcon#flushed, iclass 14, count 2 2006.201.20:39:53.38#ibcon#about to write, iclass 14, count 2 2006.201.20:39:53.38#ibcon#wrote, iclass 14, count 2 2006.201.20:39:53.38#ibcon#about to read 3, iclass 14, count 2 2006.201.20:39:53.41#ibcon#read 3, iclass 14, count 2 2006.201.20:39:53.41#ibcon#about to read 4, iclass 14, count 2 2006.201.20:39:53.41#ibcon#read 4, iclass 14, count 2 2006.201.20:39:53.41#ibcon#about to read 5, iclass 14, count 2 2006.201.20:39:53.41#ibcon#read 5, iclass 14, count 2 2006.201.20:39:53.41#ibcon#about to read 6, iclass 14, count 2 2006.201.20:39:53.41#ibcon#read 6, iclass 14, count 2 2006.201.20:39:53.41#ibcon#end of sib2, iclass 14, count 2 2006.201.20:39:53.41#ibcon#*after write, iclass 14, count 2 2006.201.20:39:53.41#ibcon#*before return 0, iclass 14, count 2 2006.201.20:39:53.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:53.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:39:53.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.20:39:53.41#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:53.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:53.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:53.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:53.53#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:39:53.53#ibcon#first serial, iclass 14, count 0 2006.201.20:39:53.53#ibcon#enter sib2, iclass 14, count 0 2006.201.20:39:53.53#ibcon#flushed, iclass 14, count 0 2006.201.20:39:53.53#ibcon#about to write, iclass 14, count 0 2006.201.20:39:53.53#ibcon#wrote, iclass 14, count 0 2006.201.20:39:53.53#ibcon#about to read 3, iclass 14, count 0 2006.201.20:39:53.55#ibcon#read 3, iclass 14, count 0 2006.201.20:39:53.55#ibcon#about to read 4, iclass 14, count 0 2006.201.20:39:53.55#ibcon#read 4, iclass 14, count 0 2006.201.20:39:53.55#ibcon#about to read 5, iclass 14, count 0 2006.201.20:39:53.55#ibcon#read 5, iclass 14, count 0 2006.201.20:39:53.55#ibcon#about to read 6, iclass 14, count 0 2006.201.20:39:53.55#ibcon#read 6, iclass 14, count 0 2006.201.20:39:53.55#ibcon#end of sib2, iclass 14, count 0 2006.201.20:39:53.55#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:39:53.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:39:53.55#ibcon#[27=USB\r\n] 2006.201.20:39:53.55#ibcon#*before write, iclass 14, count 0 2006.201.20:39:53.55#ibcon#enter sib2, iclass 14, count 0 2006.201.20:39:53.55#ibcon#flushed, iclass 14, count 0 2006.201.20:39:53.55#ibcon#about to write, iclass 14, count 0 2006.201.20:39:53.55#ibcon#wrote, iclass 14, count 0 2006.201.20:39:53.55#ibcon#about to read 3, iclass 14, count 0 2006.201.20:39:53.58#ibcon#read 3, iclass 14, count 0 2006.201.20:39:53.58#ibcon#about to read 4, iclass 14, count 0 2006.201.20:39:53.58#ibcon#read 4, iclass 14, count 0 2006.201.20:39:53.58#ibcon#about to read 5, iclass 14, count 0 2006.201.20:39:53.58#ibcon#read 5, iclass 14, count 0 2006.201.20:39:53.58#ibcon#about to read 6, iclass 14, count 0 2006.201.20:39:53.58#ibcon#read 6, iclass 14, count 0 2006.201.20:39:53.58#ibcon#end of sib2, iclass 14, count 0 2006.201.20:39:53.58#ibcon#*after write, iclass 14, count 0 2006.201.20:39:53.58#ibcon#*before return 0, iclass 14, count 0 2006.201.20:39:53.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:53.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:39:53.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:39:53.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:39:53.58$vck44/vblo=7,734.99 2006.201.20:39:53.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.20:39:53.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.20:39:53.58#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:53.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:53.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:53.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:53.58#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:39:53.58#ibcon#first serial, iclass 16, count 0 2006.201.20:39:53.58#ibcon#enter sib2, iclass 16, count 0 2006.201.20:39:53.58#ibcon#flushed, iclass 16, count 0 2006.201.20:39:53.58#ibcon#about to write, iclass 16, count 0 2006.201.20:39:53.58#ibcon#wrote, iclass 16, count 0 2006.201.20:39:53.58#ibcon#about to read 3, iclass 16, count 0 2006.201.20:39:53.60#ibcon#read 3, iclass 16, count 0 2006.201.20:39:53.60#ibcon#about to read 4, iclass 16, count 0 2006.201.20:39:53.60#ibcon#read 4, iclass 16, count 0 2006.201.20:39:53.60#ibcon#about to read 5, iclass 16, count 0 2006.201.20:39:53.60#ibcon#read 5, iclass 16, count 0 2006.201.20:39:53.60#ibcon#about to read 6, iclass 16, count 0 2006.201.20:39:53.60#ibcon#read 6, iclass 16, count 0 2006.201.20:39:53.60#ibcon#end of sib2, iclass 16, count 0 2006.201.20:39:53.60#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:39:53.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:39:53.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:39:53.60#ibcon#*before write, iclass 16, count 0 2006.201.20:39:53.60#ibcon#enter sib2, iclass 16, count 0 2006.201.20:39:53.60#ibcon#flushed, iclass 16, count 0 2006.201.20:39:53.60#ibcon#about to write, iclass 16, count 0 2006.201.20:39:53.60#ibcon#wrote, iclass 16, count 0 2006.201.20:39:53.60#ibcon#about to read 3, iclass 16, count 0 2006.201.20:39:53.64#ibcon#read 3, iclass 16, count 0 2006.201.20:39:53.64#ibcon#about to read 4, iclass 16, count 0 2006.201.20:39:53.64#ibcon#read 4, iclass 16, count 0 2006.201.20:39:53.64#ibcon#about to read 5, iclass 16, count 0 2006.201.20:39:53.64#ibcon#read 5, iclass 16, count 0 2006.201.20:39:53.64#ibcon#about to read 6, iclass 16, count 0 2006.201.20:39:53.64#ibcon#read 6, iclass 16, count 0 2006.201.20:39:53.64#ibcon#end of sib2, iclass 16, count 0 2006.201.20:39:53.64#ibcon#*after write, iclass 16, count 0 2006.201.20:39:53.64#ibcon#*before return 0, iclass 16, count 0 2006.201.20:39:53.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:53.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:39:53.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:39:53.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:39:53.64$vck44/vb=7,4 2006.201.20:39:53.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.20:39:53.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.20:39:53.64#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:53.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:53.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:53.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:53.70#ibcon#enter wrdev, iclass 18, count 2 2006.201.20:39:53.70#ibcon#first serial, iclass 18, count 2 2006.201.20:39:53.70#ibcon#enter sib2, iclass 18, count 2 2006.201.20:39:53.70#ibcon#flushed, iclass 18, count 2 2006.201.20:39:53.70#ibcon#about to write, iclass 18, count 2 2006.201.20:39:53.70#ibcon#wrote, iclass 18, count 2 2006.201.20:39:53.70#ibcon#about to read 3, iclass 18, count 2 2006.201.20:39:53.72#ibcon#read 3, iclass 18, count 2 2006.201.20:39:53.72#ibcon#about to read 4, iclass 18, count 2 2006.201.20:39:53.72#ibcon#read 4, iclass 18, count 2 2006.201.20:39:53.72#ibcon#about to read 5, iclass 18, count 2 2006.201.20:39:53.72#ibcon#read 5, iclass 18, count 2 2006.201.20:39:53.72#ibcon#about to read 6, iclass 18, count 2 2006.201.20:39:53.72#ibcon#read 6, iclass 18, count 2 2006.201.20:39:53.72#ibcon#end of sib2, iclass 18, count 2 2006.201.20:39:53.72#ibcon#*mode == 0, iclass 18, count 2 2006.201.20:39:53.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.20:39:53.72#ibcon#[27=AT07-04\r\n] 2006.201.20:39:53.72#ibcon#*before write, iclass 18, count 2 2006.201.20:39:53.72#ibcon#enter sib2, iclass 18, count 2 2006.201.20:39:53.72#ibcon#flushed, iclass 18, count 2 2006.201.20:39:53.72#ibcon#about to write, iclass 18, count 2 2006.201.20:39:53.72#ibcon#wrote, iclass 18, count 2 2006.201.20:39:53.72#ibcon#about to read 3, iclass 18, count 2 2006.201.20:39:53.75#ibcon#read 3, iclass 18, count 2 2006.201.20:39:53.75#ibcon#about to read 4, iclass 18, count 2 2006.201.20:39:53.75#ibcon#read 4, iclass 18, count 2 2006.201.20:39:53.75#ibcon#about to read 5, iclass 18, count 2 2006.201.20:39:53.75#ibcon#read 5, iclass 18, count 2 2006.201.20:39:53.75#ibcon#about to read 6, iclass 18, count 2 2006.201.20:39:53.75#ibcon#read 6, iclass 18, count 2 2006.201.20:39:53.75#ibcon#end of sib2, iclass 18, count 2 2006.201.20:39:53.75#ibcon#*after write, iclass 18, count 2 2006.201.20:39:53.75#ibcon#*before return 0, iclass 18, count 2 2006.201.20:39:53.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:53.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:39:53.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.20:39:53.75#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:53.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:53.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:53.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:53.87#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:39:53.87#ibcon#first serial, iclass 18, count 0 2006.201.20:39:53.87#ibcon#enter sib2, iclass 18, count 0 2006.201.20:39:53.87#ibcon#flushed, iclass 18, count 0 2006.201.20:39:53.87#ibcon#about to write, iclass 18, count 0 2006.201.20:39:53.87#ibcon#wrote, iclass 18, count 0 2006.201.20:39:53.87#ibcon#about to read 3, iclass 18, count 0 2006.201.20:39:53.89#ibcon#read 3, iclass 18, count 0 2006.201.20:39:53.89#ibcon#about to read 4, iclass 18, count 0 2006.201.20:39:53.89#ibcon#read 4, iclass 18, count 0 2006.201.20:39:53.89#ibcon#about to read 5, iclass 18, count 0 2006.201.20:39:53.89#ibcon#read 5, iclass 18, count 0 2006.201.20:39:53.89#ibcon#about to read 6, iclass 18, count 0 2006.201.20:39:53.89#ibcon#read 6, iclass 18, count 0 2006.201.20:39:53.89#ibcon#end of sib2, iclass 18, count 0 2006.201.20:39:53.89#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:39:53.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:39:53.89#ibcon#[27=USB\r\n] 2006.201.20:39:53.89#ibcon#*before write, iclass 18, count 0 2006.201.20:39:53.89#ibcon#enter sib2, iclass 18, count 0 2006.201.20:39:53.89#ibcon#flushed, iclass 18, count 0 2006.201.20:39:53.89#ibcon#about to write, iclass 18, count 0 2006.201.20:39:53.89#ibcon#wrote, iclass 18, count 0 2006.201.20:39:53.89#ibcon#about to read 3, iclass 18, count 0 2006.201.20:39:53.92#ibcon#read 3, iclass 18, count 0 2006.201.20:39:53.92#ibcon#about to read 4, iclass 18, count 0 2006.201.20:39:53.92#ibcon#read 4, iclass 18, count 0 2006.201.20:39:53.92#ibcon#about to read 5, iclass 18, count 0 2006.201.20:39:53.92#ibcon#read 5, iclass 18, count 0 2006.201.20:39:53.92#ibcon#about to read 6, iclass 18, count 0 2006.201.20:39:53.92#ibcon#read 6, iclass 18, count 0 2006.201.20:39:53.92#ibcon#end of sib2, iclass 18, count 0 2006.201.20:39:53.92#ibcon#*after write, iclass 18, count 0 2006.201.20:39:53.92#ibcon#*before return 0, iclass 18, count 0 2006.201.20:39:53.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:53.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:39:53.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:39:53.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:39:53.92$vck44/vblo=8,744.99 2006.201.20:39:53.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.20:39:53.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.20:39:53.92#ibcon#ireg 17 cls_cnt 0 2006.201.20:39:53.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:53.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:53.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:53.92#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:39:53.92#ibcon#first serial, iclass 20, count 0 2006.201.20:39:53.92#ibcon#enter sib2, iclass 20, count 0 2006.201.20:39:53.92#ibcon#flushed, iclass 20, count 0 2006.201.20:39:53.92#ibcon#about to write, iclass 20, count 0 2006.201.20:39:53.92#ibcon#wrote, iclass 20, count 0 2006.201.20:39:53.92#ibcon#about to read 3, iclass 20, count 0 2006.201.20:39:53.94#ibcon#read 3, iclass 20, count 0 2006.201.20:39:53.94#ibcon#about to read 4, iclass 20, count 0 2006.201.20:39:53.94#ibcon#read 4, iclass 20, count 0 2006.201.20:39:53.94#ibcon#about to read 5, iclass 20, count 0 2006.201.20:39:53.94#ibcon#read 5, iclass 20, count 0 2006.201.20:39:53.94#ibcon#about to read 6, iclass 20, count 0 2006.201.20:39:53.94#ibcon#read 6, iclass 20, count 0 2006.201.20:39:53.94#ibcon#end of sib2, iclass 20, count 0 2006.201.20:39:53.94#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:39:53.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:39:53.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:39:53.94#ibcon#*before write, iclass 20, count 0 2006.201.20:39:53.94#ibcon#enter sib2, iclass 20, count 0 2006.201.20:39:53.94#ibcon#flushed, iclass 20, count 0 2006.201.20:39:53.94#ibcon#about to write, iclass 20, count 0 2006.201.20:39:53.94#ibcon#wrote, iclass 20, count 0 2006.201.20:39:53.94#ibcon#about to read 3, iclass 20, count 0 2006.201.20:39:53.99#ibcon#read 3, iclass 20, count 0 2006.201.20:39:53.99#ibcon#about to read 4, iclass 20, count 0 2006.201.20:39:53.99#ibcon#read 4, iclass 20, count 0 2006.201.20:39:53.99#ibcon#about to read 5, iclass 20, count 0 2006.201.20:39:53.99#ibcon#read 5, iclass 20, count 0 2006.201.20:39:53.99#ibcon#about to read 6, iclass 20, count 0 2006.201.20:39:53.99#ibcon#read 6, iclass 20, count 0 2006.201.20:39:53.99#ibcon#end of sib2, iclass 20, count 0 2006.201.20:39:53.99#ibcon#*after write, iclass 20, count 0 2006.201.20:39:53.99#ibcon#*before return 0, iclass 20, count 0 2006.201.20:39:53.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:53.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:39:53.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:39:53.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:39:53.99$vck44/vb=8,4 2006.201.20:39:53.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.20:39:53.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.20:39:53.99#ibcon#ireg 11 cls_cnt 2 2006.201.20:39:53.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:54.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:54.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:54.04#ibcon#enter wrdev, iclass 22, count 2 2006.201.20:39:54.04#ibcon#first serial, iclass 22, count 2 2006.201.20:39:54.04#ibcon#enter sib2, iclass 22, count 2 2006.201.20:39:54.04#ibcon#flushed, iclass 22, count 2 2006.201.20:39:54.04#ibcon#about to write, iclass 22, count 2 2006.201.20:39:54.04#ibcon#wrote, iclass 22, count 2 2006.201.20:39:54.04#ibcon#about to read 3, iclass 22, count 2 2006.201.20:39:54.06#ibcon#read 3, iclass 22, count 2 2006.201.20:39:54.06#ibcon#about to read 4, iclass 22, count 2 2006.201.20:39:54.06#ibcon#read 4, iclass 22, count 2 2006.201.20:39:54.06#ibcon#about to read 5, iclass 22, count 2 2006.201.20:39:54.06#ibcon#read 5, iclass 22, count 2 2006.201.20:39:54.06#ibcon#about to read 6, iclass 22, count 2 2006.201.20:39:54.06#ibcon#read 6, iclass 22, count 2 2006.201.20:39:54.06#ibcon#end of sib2, iclass 22, count 2 2006.201.20:39:54.06#ibcon#*mode == 0, iclass 22, count 2 2006.201.20:39:54.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.20:39:54.06#ibcon#[27=AT08-04\r\n] 2006.201.20:39:54.06#ibcon#*before write, iclass 22, count 2 2006.201.20:39:54.06#ibcon#enter sib2, iclass 22, count 2 2006.201.20:39:54.06#ibcon#flushed, iclass 22, count 2 2006.201.20:39:54.06#ibcon#about to write, iclass 22, count 2 2006.201.20:39:54.06#ibcon#wrote, iclass 22, count 2 2006.201.20:39:54.06#ibcon#about to read 3, iclass 22, count 2 2006.201.20:39:54.09#ibcon#read 3, iclass 22, count 2 2006.201.20:39:54.09#ibcon#about to read 4, iclass 22, count 2 2006.201.20:39:54.09#ibcon#read 4, iclass 22, count 2 2006.201.20:39:54.09#ibcon#about to read 5, iclass 22, count 2 2006.201.20:39:54.09#ibcon#read 5, iclass 22, count 2 2006.201.20:39:54.09#ibcon#about to read 6, iclass 22, count 2 2006.201.20:39:54.09#ibcon#read 6, iclass 22, count 2 2006.201.20:39:54.09#ibcon#end of sib2, iclass 22, count 2 2006.201.20:39:54.09#ibcon#*after write, iclass 22, count 2 2006.201.20:39:54.09#ibcon#*before return 0, iclass 22, count 2 2006.201.20:39:54.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:54.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:39:54.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.20:39:54.09#ibcon#ireg 7 cls_cnt 0 2006.201.20:39:54.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:54.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:54.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:54.21#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:39:54.21#ibcon#first serial, iclass 22, count 0 2006.201.20:39:54.21#ibcon#enter sib2, iclass 22, count 0 2006.201.20:39:54.21#ibcon#flushed, iclass 22, count 0 2006.201.20:39:54.21#ibcon#about to write, iclass 22, count 0 2006.201.20:39:54.21#ibcon#wrote, iclass 22, count 0 2006.201.20:39:54.21#ibcon#about to read 3, iclass 22, count 0 2006.201.20:39:54.23#ibcon#read 3, iclass 22, count 0 2006.201.20:39:54.23#ibcon#about to read 4, iclass 22, count 0 2006.201.20:39:54.23#ibcon#read 4, iclass 22, count 0 2006.201.20:39:54.23#ibcon#about to read 5, iclass 22, count 0 2006.201.20:39:54.23#ibcon#read 5, iclass 22, count 0 2006.201.20:39:54.23#ibcon#about to read 6, iclass 22, count 0 2006.201.20:39:54.23#ibcon#read 6, iclass 22, count 0 2006.201.20:39:54.23#ibcon#end of sib2, iclass 22, count 0 2006.201.20:39:54.23#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:39:54.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:39:54.23#ibcon#[27=USB\r\n] 2006.201.20:39:54.23#ibcon#*before write, iclass 22, count 0 2006.201.20:39:54.23#ibcon#enter sib2, iclass 22, count 0 2006.201.20:39:54.23#ibcon#flushed, iclass 22, count 0 2006.201.20:39:54.23#ibcon#about to write, iclass 22, count 0 2006.201.20:39:54.23#ibcon#wrote, iclass 22, count 0 2006.201.20:39:54.23#ibcon#about to read 3, iclass 22, count 0 2006.201.20:39:54.26#ibcon#read 3, iclass 22, count 0 2006.201.20:39:54.26#ibcon#about to read 4, iclass 22, count 0 2006.201.20:39:54.26#ibcon#read 4, iclass 22, count 0 2006.201.20:39:54.26#ibcon#about to read 5, iclass 22, count 0 2006.201.20:39:54.26#ibcon#read 5, iclass 22, count 0 2006.201.20:39:54.26#ibcon#about to read 6, iclass 22, count 0 2006.201.20:39:54.26#ibcon#read 6, iclass 22, count 0 2006.201.20:39:54.26#ibcon#end of sib2, iclass 22, count 0 2006.201.20:39:54.26#ibcon#*after write, iclass 22, count 0 2006.201.20:39:54.26#ibcon#*before return 0, iclass 22, count 0 2006.201.20:39:54.26#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:54.26#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:39:54.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:39:54.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:39:54.26$vck44/vabw=wide 2006.201.20:39:54.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.20:39:54.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.20:39:54.26#ibcon#ireg 8 cls_cnt 0 2006.201.20:39:54.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:54.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:54.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:54.26#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:39:54.26#ibcon#first serial, iclass 24, count 0 2006.201.20:39:54.26#ibcon#enter sib2, iclass 24, count 0 2006.201.20:39:54.26#ibcon#flushed, iclass 24, count 0 2006.201.20:39:54.26#ibcon#about to write, iclass 24, count 0 2006.201.20:39:54.26#ibcon#wrote, iclass 24, count 0 2006.201.20:39:54.26#ibcon#about to read 3, iclass 24, count 0 2006.201.20:39:54.28#ibcon#read 3, iclass 24, count 0 2006.201.20:39:54.28#ibcon#about to read 4, iclass 24, count 0 2006.201.20:39:54.28#ibcon#read 4, iclass 24, count 0 2006.201.20:39:54.28#ibcon#about to read 5, iclass 24, count 0 2006.201.20:39:54.28#ibcon#read 5, iclass 24, count 0 2006.201.20:39:54.28#ibcon#about to read 6, iclass 24, count 0 2006.201.20:39:54.28#ibcon#read 6, iclass 24, count 0 2006.201.20:39:54.28#ibcon#end of sib2, iclass 24, count 0 2006.201.20:39:54.28#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:39:54.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:39:54.28#ibcon#[25=BW32\r\n] 2006.201.20:39:54.28#ibcon#*before write, iclass 24, count 0 2006.201.20:39:54.28#ibcon#enter sib2, iclass 24, count 0 2006.201.20:39:54.28#ibcon#flushed, iclass 24, count 0 2006.201.20:39:54.28#ibcon#about to write, iclass 24, count 0 2006.201.20:39:54.28#ibcon#wrote, iclass 24, count 0 2006.201.20:39:54.28#ibcon#about to read 3, iclass 24, count 0 2006.201.20:39:54.31#ibcon#read 3, iclass 24, count 0 2006.201.20:39:54.31#ibcon#about to read 4, iclass 24, count 0 2006.201.20:39:54.31#ibcon#read 4, iclass 24, count 0 2006.201.20:39:54.31#ibcon#about to read 5, iclass 24, count 0 2006.201.20:39:54.31#ibcon#read 5, iclass 24, count 0 2006.201.20:39:54.31#ibcon#about to read 6, iclass 24, count 0 2006.201.20:39:54.31#ibcon#read 6, iclass 24, count 0 2006.201.20:39:54.31#ibcon#end of sib2, iclass 24, count 0 2006.201.20:39:54.31#ibcon#*after write, iclass 24, count 0 2006.201.20:39:54.31#ibcon#*before return 0, iclass 24, count 0 2006.201.20:39:54.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:54.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:39:54.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:39:54.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:39:54.31$vck44/vbbw=wide 2006.201.20:39:54.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.20:39:54.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.20:39:54.31#ibcon#ireg 8 cls_cnt 0 2006.201.20:39:54.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:39:54.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:39:54.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:39:54.38#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:39:54.38#ibcon#first serial, iclass 26, count 0 2006.201.20:39:54.38#ibcon#enter sib2, iclass 26, count 0 2006.201.20:39:54.38#ibcon#flushed, iclass 26, count 0 2006.201.20:39:54.38#ibcon#about to write, iclass 26, count 0 2006.201.20:39:54.38#ibcon#wrote, iclass 26, count 0 2006.201.20:39:54.38#ibcon#about to read 3, iclass 26, count 0 2006.201.20:39:54.40#ibcon#read 3, iclass 26, count 0 2006.201.20:39:54.40#ibcon#about to read 4, iclass 26, count 0 2006.201.20:39:54.40#ibcon#read 4, iclass 26, count 0 2006.201.20:39:54.40#ibcon#about to read 5, iclass 26, count 0 2006.201.20:39:54.40#ibcon#read 5, iclass 26, count 0 2006.201.20:39:54.40#ibcon#about to read 6, iclass 26, count 0 2006.201.20:39:54.40#ibcon#read 6, iclass 26, count 0 2006.201.20:39:54.40#ibcon#end of sib2, iclass 26, count 0 2006.201.20:39:54.40#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:39:54.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:39:54.40#ibcon#[27=BW32\r\n] 2006.201.20:39:54.40#ibcon#*before write, iclass 26, count 0 2006.201.20:39:54.40#ibcon#enter sib2, iclass 26, count 0 2006.201.20:39:54.40#ibcon#flushed, iclass 26, count 0 2006.201.20:39:54.40#ibcon#about to write, iclass 26, count 0 2006.201.20:39:54.40#ibcon#wrote, iclass 26, count 0 2006.201.20:39:54.40#ibcon#about to read 3, iclass 26, count 0 2006.201.20:39:54.43#ibcon#read 3, iclass 26, count 0 2006.201.20:39:54.43#ibcon#about to read 4, iclass 26, count 0 2006.201.20:39:54.43#ibcon#read 4, iclass 26, count 0 2006.201.20:39:54.43#ibcon#about to read 5, iclass 26, count 0 2006.201.20:39:54.43#ibcon#read 5, iclass 26, count 0 2006.201.20:39:54.43#ibcon#about to read 6, iclass 26, count 0 2006.201.20:39:54.43#ibcon#read 6, iclass 26, count 0 2006.201.20:39:54.43#ibcon#end of sib2, iclass 26, count 0 2006.201.20:39:54.43#ibcon#*after write, iclass 26, count 0 2006.201.20:39:54.43#ibcon#*before return 0, iclass 26, count 0 2006.201.20:39:54.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:39:54.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:39:54.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:39:54.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:39:54.43$setupk4/ifdk4 2006.201.20:39:54.43$ifdk4/lo= 2006.201.20:39:54.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:39:54.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:39:54.43$ifdk4/patch= 2006.201.20:39:54.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:39:54.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:39:54.43$setupk4/!*+20s 2006.201.20:39:59.93#abcon#<5=/04 0.8 1.6 20.111001002.3\r\n> 2006.201.20:39:59.95#abcon#{5=INTERFACE CLEAR} 2006.201.20:40:00.01#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:40:08.92$setupk4/"tpicd 2006.201.20:40:08.92$setupk4/echo=off 2006.201.20:40:08.92$setupk4/xlog=off 2006.201.20:40:08.92:!2006.201.20:42:17 2006.201.20:40:42.14#trakl#Source acquired 2006.201.20:40:44.14#flagr#flagr/antenna,acquired 2006.201.20:42:17.00:preob 2006.201.20:42:18.13/onsource/TRACKING 2006.201.20:42:18.13:!2006.201.20:42:27 2006.201.20:42:27.00:"tape 2006.201.20:42:27.00:"st=record 2006.201.20:42:27.00:data_valid=on 2006.201.20:42:27.00:midob 2006.201.20:42:27.13/onsource/TRACKING 2006.201.20:42:27.13/wx/20.11,1002.4,100 2006.201.20:42:27.29/cable/+6.4812E-03 2006.201.20:42:28.38/va/01,08,usb,yes,54,57 2006.201.20:42:28.38/va/02,07,usb,yes,58,59 2006.201.20:42:28.38/va/03,08,usb,yes,53,55 2006.201.20:42:28.38/va/04,07,usb,yes,60,63 2006.201.20:42:28.38/va/05,04,usb,yes,54,55 2006.201.20:42:28.38/va/06,05,usb,yes,54,54 2006.201.20:42:28.38/va/07,05,usb,yes,53,54 2006.201.20:42:28.38/va/08,04,usb,yes,52,61 2006.201.20:42:28.61/valo/01,524.99,yes,locked 2006.201.20:42:28.61/valo/02,534.99,yes,locked 2006.201.20:42:28.61/valo/03,564.99,yes,locked 2006.201.20:42:28.61/valo/04,624.99,yes,locked 2006.201.20:42:28.61/valo/05,734.99,yes,locked 2006.201.20:42:28.61/valo/06,814.99,yes,locked 2006.201.20:42:28.61/valo/07,864.99,yes,locked 2006.201.20:42:28.61/valo/08,884.99,yes,locked 2006.201.20:42:29.70/vb/01,04,usb,yes,32,29 2006.201.20:42:29.70/vb/02,05,usb,yes,30,30 2006.201.20:42:29.70/vb/03,04,usb,yes,31,34 2006.201.20:42:29.70/vb/04,05,usb,yes,31,30 2006.201.20:42:29.70/vb/05,04,usb,yes,28,30 2006.201.20:42:29.70/vb/06,04,usb,yes,33,29 2006.201.20:42:29.70/vb/07,04,usb,yes,32,32 2006.201.20:42:29.70/vb/08,04,usb,yes,30,33 2006.201.20:42:29.93/vblo/01,629.99,yes,locked 2006.201.20:42:29.93/vblo/02,634.99,yes,locked 2006.201.20:42:29.93/vblo/03,649.99,yes,locked 2006.201.20:42:29.93/vblo/04,679.99,yes,locked 2006.201.20:42:29.93/vblo/05,709.99,yes,locked 2006.201.20:42:29.93/vblo/06,719.99,yes,locked 2006.201.20:42:29.93/vblo/07,734.99,yes,locked 2006.201.20:42:29.93/vblo/08,744.99,yes,locked 2006.201.20:42:30.08/vabw/8 2006.201.20:42:30.23/vbbw/8 2006.201.20:42:30.32/xfe/off,on,16.5 2006.201.20:42:30.69/ifatt/23,28,28,28 2006.201.20:42:31.06/fmout-gps/S +4.56E-07 2006.201.20:42:31.13:!2006.201.20:43:57 2006.201.20:43:57.00:data_valid=off 2006.201.20:43:57.00:"et 2006.201.20:43:57.00:!+3s 2006.201.20:44:00.02:"tape 2006.201.20:44:00.02:postob 2006.201.20:44:00.22/cable/+6.4818E-03 2006.201.20:44:00.22/wx/20.11,1002.4,100 2006.201.20:44:00.29/fmout-gps/S +4.55E-07 2006.201.20:44:00.29:scan_name=201-2047,jd0607,50 2006.201.20:44:00.29:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.201.20:44:01.13#flagr#flagr/antenna,new-source 2006.201.20:44:01.13:checkk5 2006.201.20:44:01.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:44:01.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:44:02.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:44:02.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:44:02.99/chk_obsdata//k5ts1/T2012042??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.20:44:03.35/chk_obsdata//k5ts2/T2012042??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.20:44:03.72/chk_obsdata//k5ts3/T2012042??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.20:44:04.09/chk_obsdata//k5ts4/T2012042??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.20:44:04.79/k5log//k5ts1_log_newline 2006.201.20:44:05.47/k5log//k5ts2_log_newline 2006.201.20:44:06.16/k5log//k5ts3_log_newline 2006.201.20:44:06.85/k5log//k5ts4_log_newline 2006.201.20:44:06.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:44:06.87:setupk4=1 2006.201.20:44:06.87$setupk4/echo=on 2006.201.20:44:06.87$setupk4/pcalon 2006.201.20:44:06.87$pcalon/"no phase cal control is implemented here 2006.201.20:44:06.87$setupk4/"tpicd=stop 2006.201.20:44:06.87$setupk4/"rec=synch_on 2006.201.20:44:06.87$setupk4/"rec_mode=128 2006.201.20:44:06.87$setupk4/!* 2006.201.20:44:06.87$setupk4/recpk4 2006.201.20:44:06.87$recpk4/recpatch= 2006.201.20:44:06.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:44:06.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:44:06.88$setupk4/vck44 2006.201.20:44:06.88$vck44/valo=1,524.99 2006.201.20:44:06.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.20:44:06.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.20:44:06.88#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:06.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:06.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:06.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:06.88#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:44:06.88#ibcon#first serial, iclass 23, count 0 2006.201.20:44:06.88#ibcon#enter sib2, iclass 23, count 0 2006.201.20:44:06.88#ibcon#flushed, iclass 23, count 0 2006.201.20:44:06.88#ibcon#about to write, iclass 23, count 0 2006.201.20:44:06.88#ibcon#wrote, iclass 23, count 0 2006.201.20:44:06.88#ibcon#about to read 3, iclass 23, count 0 2006.201.20:44:06.91#ibcon#read 3, iclass 23, count 0 2006.201.20:44:06.91#ibcon#about to read 4, iclass 23, count 0 2006.201.20:44:06.91#ibcon#read 4, iclass 23, count 0 2006.201.20:44:06.91#ibcon#about to read 5, iclass 23, count 0 2006.201.20:44:06.91#ibcon#read 5, iclass 23, count 0 2006.201.20:44:06.91#ibcon#about to read 6, iclass 23, count 0 2006.201.20:44:06.91#ibcon#read 6, iclass 23, count 0 2006.201.20:44:06.91#ibcon#end of sib2, iclass 23, count 0 2006.201.20:44:06.91#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:44:06.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:44:06.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:44:06.91#ibcon#*before write, iclass 23, count 0 2006.201.20:44:06.91#ibcon#enter sib2, iclass 23, count 0 2006.201.20:44:06.91#ibcon#flushed, iclass 23, count 0 2006.201.20:44:06.91#ibcon#about to write, iclass 23, count 0 2006.201.20:44:06.91#ibcon#wrote, iclass 23, count 0 2006.201.20:44:06.91#ibcon#about to read 3, iclass 23, count 0 2006.201.20:44:06.97#ibcon#read 3, iclass 23, count 0 2006.201.20:44:06.97#ibcon#about to read 4, iclass 23, count 0 2006.201.20:44:06.97#ibcon#read 4, iclass 23, count 0 2006.201.20:44:06.97#ibcon#about to read 5, iclass 23, count 0 2006.201.20:44:06.97#ibcon#read 5, iclass 23, count 0 2006.201.20:44:06.97#ibcon#about to read 6, iclass 23, count 0 2006.201.20:44:06.97#ibcon#read 6, iclass 23, count 0 2006.201.20:44:06.97#ibcon#end of sib2, iclass 23, count 0 2006.201.20:44:06.97#ibcon#*after write, iclass 23, count 0 2006.201.20:44:06.97#ibcon#*before return 0, iclass 23, count 0 2006.201.20:44:06.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:06.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:06.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:44:06.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:44:06.97$vck44/va=1,8 2006.201.20:44:06.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.20:44:06.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.20:44:06.97#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:06.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:06.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:06.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:06.97#ibcon#enter wrdev, iclass 25, count 2 2006.201.20:44:06.97#ibcon#first serial, iclass 25, count 2 2006.201.20:44:06.97#ibcon#enter sib2, iclass 25, count 2 2006.201.20:44:06.97#ibcon#flushed, iclass 25, count 2 2006.201.20:44:06.97#ibcon#about to write, iclass 25, count 2 2006.201.20:44:06.97#ibcon#wrote, iclass 25, count 2 2006.201.20:44:06.97#ibcon#about to read 3, iclass 25, count 2 2006.201.20:44:06.99#ibcon#read 3, iclass 25, count 2 2006.201.20:44:06.99#ibcon#about to read 4, iclass 25, count 2 2006.201.20:44:06.99#ibcon#read 4, iclass 25, count 2 2006.201.20:44:06.99#ibcon#about to read 5, iclass 25, count 2 2006.201.20:44:06.99#ibcon#read 5, iclass 25, count 2 2006.201.20:44:06.99#ibcon#about to read 6, iclass 25, count 2 2006.201.20:44:06.99#ibcon#read 6, iclass 25, count 2 2006.201.20:44:06.99#ibcon#end of sib2, iclass 25, count 2 2006.201.20:44:06.99#ibcon#*mode == 0, iclass 25, count 2 2006.201.20:44:06.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.20:44:06.99#ibcon#[25=AT01-08\r\n] 2006.201.20:44:06.99#ibcon#*before write, iclass 25, count 2 2006.201.20:44:06.99#ibcon#enter sib2, iclass 25, count 2 2006.201.20:44:06.99#ibcon#flushed, iclass 25, count 2 2006.201.20:44:06.99#ibcon#about to write, iclass 25, count 2 2006.201.20:44:06.99#ibcon#wrote, iclass 25, count 2 2006.201.20:44:06.99#ibcon#about to read 3, iclass 25, count 2 2006.201.20:44:07.03#ibcon#read 3, iclass 25, count 2 2006.201.20:44:07.03#ibcon#about to read 4, iclass 25, count 2 2006.201.20:44:07.03#ibcon#read 4, iclass 25, count 2 2006.201.20:44:07.03#ibcon#about to read 5, iclass 25, count 2 2006.201.20:44:07.03#ibcon#read 5, iclass 25, count 2 2006.201.20:44:07.03#ibcon#about to read 6, iclass 25, count 2 2006.201.20:44:07.03#ibcon#read 6, iclass 25, count 2 2006.201.20:44:07.03#ibcon#end of sib2, iclass 25, count 2 2006.201.20:44:07.03#ibcon#*after write, iclass 25, count 2 2006.201.20:44:07.03#ibcon#*before return 0, iclass 25, count 2 2006.201.20:44:07.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:07.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:07.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.20:44:07.03#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:07.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:07.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:07.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:07.15#ibcon#enter wrdev, iclass 25, count 0 2006.201.20:44:07.15#ibcon#first serial, iclass 25, count 0 2006.201.20:44:07.15#ibcon#enter sib2, iclass 25, count 0 2006.201.20:44:07.15#ibcon#flushed, iclass 25, count 0 2006.201.20:44:07.15#ibcon#about to write, iclass 25, count 0 2006.201.20:44:07.15#ibcon#wrote, iclass 25, count 0 2006.201.20:44:07.15#ibcon#about to read 3, iclass 25, count 0 2006.201.20:44:07.17#ibcon#read 3, iclass 25, count 0 2006.201.20:44:07.17#ibcon#about to read 4, iclass 25, count 0 2006.201.20:44:07.17#ibcon#read 4, iclass 25, count 0 2006.201.20:44:07.17#ibcon#about to read 5, iclass 25, count 0 2006.201.20:44:07.17#ibcon#read 5, iclass 25, count 0 2006.201.20:44:07.17#ibcon#about to read 6, iclass 25, count 0 2006.201.20:44:07.17#ibcon#read 6, iclass 25, count 0 2006.201.20:44:07.17#ibcon#end of sib2, iclass 25, count 0 2006.201.20:44:07.17#ibcon#*mode == 0, iclass 25, count 0 2006.201.20:44:07.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.20:44:07.17#ibcon#[25=USB\r\n] 2006.201.20:44:07.17#ibcon#*before write, iclass 25, count 0 2006.201.20:44:07.17#ibcon#enter sib2, iclass 25, count 0 2006.201.20:44:07.17#ibcon#flushed, iclass 25, count 0 2006.201.20:44:07.17#ibcon#about to write, iclass 25, count 0 2006.201.20:44:07.17#ibcon#wrote, iclass 25, count 0 2006.201.20:44:07.17#ibcon#about to read 3, iclass 25, count 0 2006.201.20:44:07.20#ibcon#read 3, iclass 25, count 0 2006.201.20:44:07.20#ibcon#about to read 4, iclass 25, count 0 2006.201.20:44:07.20#ibcon#read 4, iclass 25, count 0 2006.201.20:44:07.20#ibcon#about to read 5, iclass 25, count 0 2006.201.20:44:07.20#ibcon#read 5, iclass 25, count 0 2006.201.20:44:07.20#ibcon#about to read 6, iclass 25, count 0 2006.201.20:44:07.20#ibcon#read 6, iclass 25, count 0 2006.201.20:44:07.20#ibcon#end of sib2, iclass 25, count 0 2006.201.20:44:07.20#ibcon#*after write, iclass 25, count 0 2006.201.20:44:07.20#ibcon#*before return 0, iclass 25, count 0 2006.201.20:44:07.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:07.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:07.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.20:44:07.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.20:44:07.20$vck44/valo=2,534.99 2006.201.20:44:07.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.20:44:07.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.20:44:07.20#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:07.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:07.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:07.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:07.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:44:07.20#ibcon#first serial, iclass 27, count 0 2006.201.20:44:07.20#ibcon#enter sib2, iclass 27, count 0 2006.201.20:44:07.20#ibcon#flushed, iclass 27, count 0 2006.201.20:44:07.20#ibcon#about to write, iclass 27, count 0 2006.201.20:44:07.20#ibcon#wrote, iclass 27, count 0 2006.201.20:44:07.20#ibcon#about to read 3, iclass 27, count 0 2006.201.20:44:07.22#ibcon#read 3, iclass 27, count 0 2006.201.20:44:07.22#ibcon#about to read 4, iclass 27, count 0 2006.201.20:44:07.22#ibcon#read 4, iclass 27, count 0 2006.201.20:44:07.22#ibcon#about to read 5, iclass 27, count 0 2006.201.20:44:07.22#ibcon#read 5, iclass 27, count 0 2006.201.20:44:07.22#ibcon#about to read 6, iclass 27, count 0 2006.201.20:44:07.22#ibcon#read 6, iclass 27, count 0 2006.201.20:44:07.22#ibcon#end of sib2, iclass 27, count 0 2006.201.20:44:07.22#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:44:07.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:44:07.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:44:07.22#ibcon#*before write, iclass 27, count 0 2006.201.20:44:07.22#ibcon#enter sib2, iclass 27, count 0 2006.201.20:44:07.22#ibcon#flushed, iclass 27, count 0 2006.201.20:44:07.22#ibcon#about to write, iclass 27, count 0 2006.201.20:44:07.22#ibcon#wrote, iclass 27, count 0 2006.201.20:44:07.22#ibcon#about to read 3, iclass 27, count 0 2006.201.20:44:07.26#ibcon#read 3, iclass 27, count 0 2006.201.20:44:07.26#ibcon#about to read 4, iclass 27, count 0 2006.201.20:44:07.26#ibcon#read 4, iclass 27, count 0 2006.201.20:44:07.26#ibcon#about to read 5, iclass 27, count 0 2006.201.20:44:07.26#ibcon#read 5, iclass 27, count 0 2006.201.20:44:07.26#ibcon#about to read 6, iclass 27, count 0 2006.201.20:44:07.26#ibcon#read 6, iclass 27, count 0 2006.201.20:44:07.26#ibcon#end of sib2, iclass 27, count 0 2006.201.20:44:07.26#ibcon#*after write, iclass 27, count 0 2006.201.20:44:07.26#ibcon#*before return 0, iclass 27, count 0 2006.201.20:44:07.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:07.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:07.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:44:07.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:44:07.26$vck44/va=2,7 2006.201.20:44:07.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.20:44:07.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.20:44:07.26#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:07.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:07.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:07.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:07.32#ibcon#enter wrdev, iclass 29, count 2 2006.201.20:44:07.32#ibcon#first serial, iclass 29, count 2 2006.201.20:44:07.32#ibcon#enter sib2, iclass 29, count 2 2006.201.20:44:07.32#ibcon#flushed, iclass 29, count 2 2006.201.20:44:07.32#ibcon#about to write, iclass 29, count 2 2006.201.20:44:07.32#ibcon#wrote, iclass 29, count 2 2006.201.20:44:07.32#ibcon#about to read 3, iclass 29, count 2 2006.201.20:44:07.34#ibcon#read 3, iclass 29, count 2 2006.201.20:44:07.34#ibcon#about to read 4, iclass 29, count 2 2006.201.20:44:07.34#ibcon#read 4, iclass 29, count 2 2006.201.20:44:07.34#ibcon#about to read 5, iclass 29, count 2 2006.201.20:44:07.34#ibcon#read 5, iclass 29, count 2 2006.201.20:44:07.34#ibcon#about to read 6, iclass 29, count 2 2006.201.20:44:07.34#ibcon#read 6, iclass 29, count 2 2006.201.20:44:07.34#ibcon#end of sib2, iclass 29, count 2 2006.201.20:44:07.34#ibcon#*mode == 0, iclass 29, count 2 2006.201.20:44:07.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.20:44:07.34#ibcon#[25=AT02-07\r\n] 2006.201.20:44:07.34#ibcon#*before write, iclass 29, count 2 2006.201.20:44:07.34#ibcon#enter sib2, iclass 29, count 2 2006.201.20:44:07.34#ibcon#flushed, iclass 29, count 2 2006.201.20:44:07.34#ibcon#about to write, iclass 29, count 2 2006.201.20:44:07.34#ibcon#wrote, iclass 29, count 2 2006.201.20:44:07.34#ibcon#about to read 3, iclass 29, count 2 2006.201.20:44:07.37#ibcon#read 3, iclass 29, count 2 2006.201.20:44:07.37#ibcon#about to read 4, iclass 29, count 2 2006.201.20:44:07.37#ibcon#read 4, iclass 29, count 2 2006.201.20:44:07.37#ibcon#about to read 5, iclass 29, count 2 2006.201.20:44:07.37#ibcon#read 5, iclass 29, count 2 2006.201.20:44:07.37#ibcon#about to read 6, iclass 29, count 2 2006.201.20:44:07.37#ibcon#read 6, iclass 29, count 2 2006.201.20:44:07.37#ibcon#end of sib2, iclass 29, count 2 2006.201.20:44:07.37#ibcon#*after write, iclass 29, count 2 2006.201.20:44:07.37#ibcon#*before return 0, iclass 29, count 2 2006.201.20:44:07.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:07.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:07.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.20:44:07.37#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:07.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:07.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:07.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:07.49#ibcon#enter wrdev, iclass 29, count 0 2006.201.20:44:07.49#ibcon#first serial, iclass 29, count 0 2006.201.20:44:07.49#ibcon#enter sib2, iclass 29, count 0 2006.201.20:44:07.49#ibcon#flushed, iclass 29, count 0 2006.201.20:44:07.49#ibcon#about to write, iclass 29, count 0 2006.201.20:44:07.49#ibcon#wrote, iclass 29, count 0 2006.201.20:44:07.49#ibcon#about to read 3, iclass 29, count 0 2006.201.20:44:07.51#ibcon#read 3, iclass 29, count 0 2006.201.20:44:07.51#ibcon#about to read 4, iclass 29, count 0 2006.201.20:44:07.51#ibcon#read 4, iclass 29, count 0 2006.201.20:44:07.51#ibcon#about to read 5, iclass 29, count 0 2006.201.20:44:07.51#ibcon#read 5, iclass 29, count 0 2006.201.20:44:07.51#ibcon#about to read 6, iclass 29, count 0 2006.201.20:44:07.51#ibcon#read 6, iclass 29, count 0 2006.201.20:44:07.51#ibcon#end of sib2, iclass 29, count 0 2006.201.20:44:07.51#ibcon#*mode == 0, iclass 29, count 0 2006.201.20:44:07.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.20:44:07.51#ibcon#[25=USB\r\n] 2006.201.20:44:07.51#ibcon#*before write, iclass 29, count 0 2006.201.20:44:07.51#ibcon#enter sib2, iclass 29, count 0 2006.201.20:44:07.51#ibcon#flushed, iclass 29, count 0 2006.201.20:44:07.51#ibcon#about to write, iclass 29, count 0 2006.201.20:44:07.51#ibcon#wrote, iclass 29, count 0 2006.201.20:44:07.51#ibcon#about to read 3, iclass 29, count 0 2006.201.20:44:07.54#ibcon#read 3, iclass 29, count 0 2006.201.20:44:07.54#ibcon#about to read 4, iclass 29, count 0 2006.201.20:44:07.54#ibcon#read 4, iclass 29, count 0 2006.201.20:44:07.54#ibcon#about to read 5, iclass 29, count 0 2006.201.20:44:07.54#ibcon#read 5, iclass 29, count 0 2006.201.20:44:07.54#ibcon#about to read 6, iclass 29, count 0 2006.201.20:44:07.54#ibcon#read 6, iclass 29, count 0 2006.201.20:44:07.54#ibcon#end of sib2, iclass 29, count 0 2006.201.20:44:07.54#ibcon#*after write, iclass 29, count 0 2006.201.20:44:07.54#ibcon#*before return 0, iclass 29, count 0 2006.201.20:44:07.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:07.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:07.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.20:44:07.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.20:44:07.54$vck44/valo=3,564.99 2006.201.20:44:07.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.20:44:07.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.20:44:07.54#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:07.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:07.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:07.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:07.54#ibcon#enter wrdev, iclass 31, count 0 2006.201.20:44:07.54#ibcon#first serial, iclass 31, count 0 2006.201.20:44:07.54#ibcon#enter sib2, iclass 31, count 0 2006.201.20:44:07.54#ibcon#flushed, iclass 31, count 0 2006.201.20:44:07.54#ibcon#about to write, iclass 31, count 0 2006.201.20:44:07.54#ibcon#wrote, iclass 31, count 0 2006.201.20:44:07.54#ibcon#about to read 3, iclass 31, count 0 2006.201.20:44:07.56#ibcon#read 3, iclass 31, count 0 2006.201.20:44:07.56#ibcon#about to read 4, iclass 31, count 0 2006.201.20:44:07.56#ibcon#read 4, iclass 31, count 0 2006.201.20:44:07.56#ibcon#about to read 5, iclass 31, count 0 2006.201.20:44:07.56#ibcon#read 5, iclass 31, count 0 2006.201.20:44:07.56#ibcon#about to read 6, iclass 31, count 0 2006.201.20:44:07.56#ibcon#read 6, iclass 31, count 0 2006.201.20:44:07.56#ibcon#end of sib2, iclass 31, count 0 2006.201.20:44:07.56#ibcon#*mode == 0, iclass 31, count 0 2006.201.20:44:07.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.20:44:07.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:44:07.56#ibcon#*before write, iclass 31, count 0 2006.201.20:44:07.56#ibcon#enter sib2, iclass 31, count 0 2006.201.20:44:07.56#ibcon#flushed, iclass 31, count 0 2006.201.20:44:07.56#ibcon#about to write, iclass 31, count 0 2006.201.20:44:07.56#ibcon#wrote, iclass 31, count 0 2006.201.20:44:07.56#ibcon#about to read 3, iclass 31, count 0 2006.201.20:44:07.60#ibcon#read 3, iclass 31, count 0 2006.201.20:44:07.60#ibcon#about to read 4, iclass 31, count 0 2006.201.20:44:07.60#ibcon#read 4, iclass 31, count 0 2006.201.20:44:07.60#ibcon#about to read 5, iclass 31, count 0 2006.201.20:44:07.60#ibcon#read 5, iclass 31, count 0 2006.201.20:44:07.60#ibcon#about to read 6, iclass 31, count 0 2006.201.20:44:07.60#ibcon#read 6, iclass 31, count 0 2006.201.20:44:07.60#ibcon#end of sib2, iclass 31, count 0 2006.201.20:44:07.60#ibcon#*after write, iclass 31, count 0 2006.201.20:44:07.60#ibcon#*before return 0, iclass 31, count 0 2006.201.20:44:07.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:07.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:07.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.20:44:07.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.20:44:07.60$vck44/va=3,8 2006.201.20:44:07.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.20:44:07.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.20:44:07.60#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:07.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:07.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:07.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:07.66#ibcon#enter wrdev, iclass 33, count 2 2006.201.20:44:07.66#ibcon#first serial, iclass 33, count 2 2006.201.20:44:07.66#ibcon#enter sib2, iclass 33, count 2 2006.201.20:44:07.66#ibcon#flushed, iclass 33, count 2 2006.201.20:44:07.66#ibcon#about to write, iclass 33, count 2 2006.201.20:44:07.66#ibcon#wrote, iclass 33, count 2 2006.201.20:44:07.66#ibcon#about to read 3, iclass 33, count 2 2006.201.20:44:07.68#ibcon#read 3, iclass 33, count 2 2006.201.20:44:07.68#ibcon#about to read 4, iclass 33, count 2 2006.201.20:44:07.68#ibcon#read 4, iclass 33, count 2 2006.201.20:44:07.68#ibcon#about to read 5, iclass 33, count 2 2006.201.20:44:07.68#ibcon#read 5, iclass 33, count 2 2006.201.20:44:07.68#ibcon#about to read 6, iclass 33, count 2 2006.201.20:44:07.68#ibcon#read 6, iclass 33, count 2 2006.201.20:44:07.68#ibcon#end of sib2, iclass 33, count 2 2006.201.20:44:07.68#ibcon#*mode == 0, iclass 33, count 2 2006.201.20:44:07.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.20:44:07.68#ibcon#[25=AT03-08\r\n] 2006.201.20:44:07.68#ibcon#*before write, iclass 33, count 2 2006.201.20:44:07.68#ibcon#enter sib2, iclass 33, count 2 2006.201.20:44:07.68#ibcon#flushed, iclass 33, count 2 2006.201.20:44:07.68#ibcon#about to write, iclass 33, count 2 2006.201.20:44:07.68#ibcon#wrote, iclass 33, count 2 2006.201.20:44:07.68#ibcon#about to read 3, iclass 33, count 2 2006.201.20:44:07.71#ibcon#read 3, iclass 33, count 2 2006.201.20:44:07.71#ibcon#about to read 4, iclass 33, count 2 2006.201.20:44:07.71#ibcon#read 4, iclass 33, count 2 2006.201.20:44:07.71#ibcon#about to read 5, iclass 33, count 2 2006.201.20:44:07.71#ibcon#read 5, iclass 33, count 2 2006.201.20:44:07.71#ibcon#about to read 6, iclass 33, count 2 2006.201.20:44:07.71#ibcon#read 6, iclass 33, count 2 2006.201.20:44:07.71#ibcon#end of sib2, iclass 33, count 2 2006.201.20:44:07.71#ibcon#*after write, iclass 33, count 2 2006.201.20:44:07.71#ibcon#*before return 0, iclass 33, count 2 2006.201.20:44:07.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:07.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:07.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.20:44:07.71#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:07.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:07.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:07.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:07.83#ibcon#enter wrdev, iclass 33, count 0 2006.201.20:44:07.83#ibcon#first serial, iclass 33, count 0 2006.201.20:44:07.83#ibcon#enter sib2, iclass 33, count 0 2006.201.20:44:07.83#ibcon#flushed, iclass 33, count 0 2006.201.20:44:07.83#ibcon#about to write, iclass 33, count 0 2006.201.20:44:07.83#ibcon#wrote, iclass 33, count 0 2006.201.20:44:07.83#ibcon#about to read 3, iclass 33, count 0 2006.201.20:44:07.85#ibcon#read 3, iclass 33, count 0 2006.201.20:44:07.85#ibcon#about to read 4, iclass 33, count 0 2006.201.20:44:07.85#ibcon#read 4, iclass 33, count 0 2006.201.20:44:07.85#ibcon#about to read 5, iclass 33, count 0 2006.201.20:44:07.85#ibcon#read 5, iclass 33, count 0 2006.201.20:44:07.85#ibcon#about to read 6, iclass 33, count 0 2006.201.20:44:07.85#ibcon#read 6, iclass 33, count 0 2006.201.20:44:07.85#ibcon#end of sib2, iclass 33, count 0 2006.201.20:44:07.85#ibcon#*mode == 0, iclass 33, count 0 2006.201.20:44:07.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.20:44:07.85#ibcon#[25=USB\r\n] 2006.201.20:44:07.85#ibcon#*before write, iclass 33, count 0 2006.201.20:44:07.85#ibcon#enter sib2, iclass 33, count 0 2006.201.20:44:07.85#ibcon#flushed, iclass 33, count 0 2006.201.20:44:07.85#ibcon#about to write, iclass 33, count 0 2006.201.20:44:07.85#ibcon#wrote, iclass 33, count 0 2006.201.20:44:07.85#ibcon#about to read 3, iclass 33, count 0 2006.201.20:44:07.88#ibcon#read 3, iclass 33, count 0 2006.201.20:44:07.88#ibcon#about to read 4, iclass 33, count 0 2006.201.20:44:07.88#ibcon#read 4, iclass 33, count 0 2006.201.20:44:07.88#ibcon#about to read 5, iclass 33, count 0 2006.201.20:44:07.88#ibcon#read 5, iclass 33, count 0 2006.201.20:44:07.88#ibcon#about to read 6, iclass 33, count 0 2006.201.20:44:07.88#ibcon#read 6, iclass 33, count 0 2006.201.20:44:07.88#ibcon#end of sib2, iclass 33, count 0 2006.201.20:44:07.88#ibcon#*after write, iclass 33, count 0 2006.201.20:44:07.88#ibcon#*before return 0, iclass 33, count 0 2006.201.20:44:07.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:07.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:07.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.20:44:07.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.20:44:07.88$vck44/valo=4,624.99 2006.201.20:44:07.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.20:44:07.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.20:44:07.88#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:07.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:07.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:07.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:07.88#ibcon#enter wrdev, iclass 35, count 0 2006.201.20:44:07.88#ibcon#first serial, iclass 35, count 0 2006.201.20:44:07.88#ibcon#enter sib2, iclass 35, count 0 2006.201.20:44:07.88#ibcon#flushed, iclass 35, count 0 2006.201.20:44:07.88#ibcon#about to write, iclass 35, count 0 2006.201.20:44:07.88#ibcon#wrote, iclass 35, count 0 2006.201.20:44:07.88#ibcon#about to read 3, iclass 35, count 0 2006.201.20:44:07.90#ibcon#read 3, iclass 35, count 0 2006.201.20:44:07.90#ibcon#about to read 4, iclass 35, count 0 2006.201.20:44:07.90#ibcon#read 4, iclass 35, count 0 2006.201.20:44:07.90#ibcon#about to read 5, iclass 35, count 0 2006.201.20:44:07.90#ibcon#read 5, iclass 35, count 0 2006.201.20:44:07.90#ibcon#about to read 6, iclass 35, count 0 2006.201.20:44:07.90#ibcon#read 6, iclass 35, count 0 2006.201.20:44:07.90#ibcon#end of sib2, iclass 35, count 0 2006.201.20:44:07.90#ibcon#*mode == 0, iclass 35, count 0 2006.201.20:44:07.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.20:44:07.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:44:07.90#ibcon#*before write, iclass 35, count 0 2006.201.20:44:07.90#ibcon#enter sib2, iclass 35, count 0 2006.201.20:44:07.90#ibcon#flushed, iclass 35, count 0 2006.201.20:44:07.90#ibcon#about to write, iclass 35, count 0 2006.201.20:44:07.90#ibcon#wrote, iclass 35, count 0 2006.201.20:44:07.90#ibcon#about to read 3, iclass 35, count 0 2006.201.20:44:07.95#ibcon#read 3, iclass 35, count 0 2006.201.20:44:07.95#ibcon#about to read 4, iclass 35, count 0 2006.201.20:44:07.95#ibcon#read 4, iclass 35, count 0 2006.201.20:44:07.95#ibcon#about to read 5, iclass 35, count 0 2006.201.20:44:07.95#ibcon#read 5, iclass 35, count 0 2006.201.20:44:07.95#ibcon#about to read 6, iclass 35, count 0 2006.201.20:44:07.95#ibcon#read 6, iclass 35, count 0 2006.201.20:44:07.95#ibcon#end of sib2, iclass 35, count 0 2006.201.20:44:07.95#ibcon#*after write, iclass 35, count 0 2006.201.20:44:07.95#ibcon#*before return 0, iclass 35, count 0 2006.201.20:44:07.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:07.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:07.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.20:44:07.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.20:44:07.95$vck44/va=4,7 2006.201.20:44:07.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.20:44:07.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.20:44:07.95#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:07.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:08.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:08.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:08.00#ibcon#enter wrdev, iclass 37, count 2 2006.201.20:44:08.00#ibcon#first serial, iclass 37, count 2 2006.201.20:44:08.00#ibcon#enter sib2, iclass 37, count 2 2006.201.20:44:08.00#ibcon#flushed, iclass 37, count 2 2006.201.20:44:08.00#ibcon#about to write, iclass 37, count 2 2006.201.20:44:08.00#ibcon#wrote, iclass 37, count 2 2006.201.20:44:08.00#ibcon#about to read 3, iclass 37, count 2 2006.201.20:44:08.02#ibcon#read 3, iclass 37, count 2 2006.201.20:44:08.02#ibcon#about to read 4, iclass 37, count 2 2006.201.20:44:08.02#ibcon#read 4, iclass 37, count 2 2006.201.20:44:08.02#ibcon#about to read 5, iclass 37, count 2 2006.201.20:44:08.02#ibcon#read 5, iclass 37, count 2 2006.201.20:44:08.02#ibcon#about to read 6, iclass 37, count 2 2006.201.20:44:08.02#ibcon#read 6, iclass 37, count 2 2006.201.20:44:08.02#ibcon#end of sib2, iclass 37, count 2 2006.201.20:44:08.02#ibcon#*mode == 0, iclass 37, count 2 2006.201.20:44:08.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.20:44:08.02#ibcon#[25=AT04-07\r\n] 2006.201.20:44:08.02#ibcon#*before write, iclass 37, count 2 2006.201.20:44:08.02#ibcon#enter sib2, iclass 37, count 2 2006.201.20:44:08.02#ibcon#flushed, iclass 37, count 2 2006.201.20:44:08.02#ibcon#about to write, iclass 37, count 2 2006.201.20:44:08.02#ibcon#wrote, iclass 37, count 2 2006.201.20:44:08.02#ibcon#about to read 3, iclass 37, count 2 2006.201.20:44:08.05#ibcon#read 3, iclass 37, count 2 2006.201.20:44:08.05#ibcon#about to read 4, iclass 37, count 2 2006.201.20:44:08.05#ibcon#read 4, iclass 37, count 2 2006.201.20:44:08.05#ibcon#about to read 5, iclass 37, count 2 2006.201.20:44:08.05#ibcon#read 5, iclass 37, count 2 2006.201.20:44:08.05#ibcon#about to read 6, iclass 37, count 2 2006.201.20:44:08.05#ibcon#read 6, iclass 37, count 2 2006.201.20:44:08.05#ibcon#end of sib2, iclass 37, count 2 2006.201.20:44:08.05#ibcon#*after write, iclass 37, count 2 2006.201.20:44:08.05#ibcon#*before return 0, iclass 37, count 2 2006.201.20:44:08.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:08.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:08.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.20:44:08.05#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:08.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:08.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:08.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:08.17#ibcon#enter wrdev, iclass 37, count 0 2006.201.20:44:08.17#ibcon#first serial, iclass 37, count 0 2006.201.20:44:08.17#ibcon#enter sib2, iclass 37, count 0 2006.201.20:44:08.17#ibcon#flushed, iclass 37, count 0 2006.201.20:44:08.17#ibcon#about to write, iclass 37, count 0 2006.201.20:44:08.17#ibcon#wrote, iclass 37, count 0 2006.201.20:44:08.17#ibcon#about to read 3, iclass 37, count 0 2006.201.20:44:08.19#ibcon#read 3, iclass 37, count 0 2006.201.20:44:08.19#ibcon#about to read 4, iclass 37, count 0 2006.201.20:44:08.19#ibcon#read 4, iclass 37, count 0 2006.201.20:44:08.19#ibcon#about to read 5, iclass 37, count 0 2006.201.20:44:08.19#ibcon#read 5, iclass 37, count 0 2006.201.20:44:08.19#ibcon#about to read 6, iclass 37, count 0 2006.201.20:44:08.19#ibcon#read 6, iclass 37, count 0 2006.201.20:44:08.19#ibcon#end of sib2, iclass 37, count 0 2006.201.20:44:08.19#ibcon#*mode == 0, iclass 37, count 0 2006.201.20:44:08.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.20:44:08.19#ibcon#[25=USB\r\n] 2006.201.20:44:08.19#ibcon#*before write, iclass 37, count 0 2006.201.20:44:08.19#ibcon#enter sib2, iclass 37, count 0 2006.201.20:44:08.19#ibcon#flushed, iclass 37, count 0 2006.201.20:44:08.19#ibcon#about to write, iclass 37, count 0 2006.201.20:44:08.19#ibcon#wrote, iclass 37, count 0 2006.201.20:44:08.19#ibcon#about to read 3, iclass 37, count 0 2006.201.20:44:08.22#ibcon#read 3, iclass 37, count 0 2006.201.20:44:08.22#ibcon#about to read 4, iclass 37, count 0 2006.201.20:44:08.22#ibcon#read 4, iclass 37, count 0 2006.201.20:44:08.22#ibcon#about to read 5, iclass 37, count 0 2006.201.20:44:08.22#ibcon#read 5, iclass 37, count 0 2006.201.20:44:08.22#ibcon#about to read 6, iclass 37, count 0 2006.201.20:44:08.22#ibcon#read 6, iclass 37, count 0 2006.201.20:44:08.22#ibcon#end of sib2, iclass 37, count 0 2006.201.20:44:08.22#ibcon#*after write, iclass 37, count 0 2006.201.20:44:08.22#ibcon#*before return 0, iclass 37, count 0 2006.201.20:44:08.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:08.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:08.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.20:44:08.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.20:44:08.22$vck44/valo=5,734.99 2006.201.20:44:08.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.20:44:08.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.20:44:08.22#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:08.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:08.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:08.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:08.22#ibcon#enter wrdev, iclass 39, count 0 2006.201.20:44:08.22#ibcon#first serial, iclass 39, count 0 2006.201.20:44:08.22#ibcon#enter sib2, iclass 39, count 0 2006.201.20:44:08.22#ibcon#flushed, iclass 39, count 0 2006.201.20:44:08.22#ibcon#about to write, iclass 39, count 0 2006.201.20:44:08.22#ibcon#wrote, iclass 39, count 0 2006.201.20:44:08.22#ibcon#about to read 3, iclass 39, count 0 2006.201.20:44:08.24#ibcon#read 3, iclass 39, count 0 2006.201.20:44:08.24#ibcon#about to read 4, iclass 39, count 0 2006.201.20:44:08.24#ibcon#read 4, iclass 39, count 0 2006.201.20:44:08.24#ibcon#about to read 5, iclass 39, count 0 2006.201.20:44:08.24#ibcon#read 5, iclass 39, count 0 2006.201.20:44:08.24#ibcon#about to read 6, iclass 39, count 0 2006.201.20:44:08.24#ibcon#read 6, iclass 39, count 0 2006.201.20:44:08.24#ibcon#end of sib2, iclass 39, count 0 2006.201.20:44:08.24#ibcon#*mode == 0, iclass 39, count 0 2006.201.20:44:08.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.20:44:08.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:44:08.24#ibcon#*before write, iclass 39, count 0 2006.201.20:44:08.24#ibcon#enter sib2, iclass 39, count 0 2006.201.20:44:08.24#ibcon#flushed, iclass 39, count 0 2006.201.20:44:08.24#ibcon#about to write, iclass 39, count 0 2006.201.20:44:08.24#ibcon#wrote, iclass 39, count 0 2006.201.20:44:08.24#ibcon#about to read 3, iclass 39, count 0 2006.201.20:44:08.28#ibcon#read 3, iclass 39, count 0 2006.201.20:44:08.28#ibcon#about to read 4, iclass 39, count 0 2006.201.20:44:08.28#ibcon#read 4, iclass 39, count 0 2006.201.20:44:08.28#ibcon#about to read 5, iclass 39, count 0 2006.201.20:44:08.28#ibcon#read 5, iclass 39, count 0 2006.201.20:44:08.28#ibcon#about to read 6, iclass 39, count 0 2006.201.20:44:08.28#ibcon#read 6, iclass 39, count 0 2006.201.20:44:08.28#ibcon#end of sib2, iclass 39, count 0 2006.201.20:44:08.28#ibcon#*after write, iclass 39, count 0 2006.201.20:44:08.28#ibcon#*before return 0, iclass 39, count 0 2006.201.20:44:08.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:08.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:08.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.20:44:08.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.20:44:08.28$vck44/va=5,4 2006.201.20:44:08.28#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.20:44:08.28#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.20:44:08.28#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:08.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:08.34#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:08.34#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:08.34#ibcon#enter wrdev, iclass 2, count 2 2006.201.20:44:08.34#ibcon#first serial, iclass 2, count 2 2006.201.20:44:08.34#ibcon#enter sib2, iclass 2, count 2 2006.201.20:44:08.34#ibcon#flushed, iclass 2, count 2 2006.201.20:44:08.34#ibcon#about to write, iclass 2, count 2 2006.201.20:44:08.34#ibcon#wrote, iclass 2, count 2 2006.201.20:44:08.34#ibcon#about to read 3, iclass 2, count 2 2006.201.20:44:08.36#ibcon#read 3, iclass 2, count 2 2006.201.20:44:08.36#ibcon#about to read 4, iclass 2, count 2 2006.201.20:44:08.36#ibcon#read 4, iclass 2, count 2 2006.201.20:44:08.36#ibcon#about to read 5, iclass 2, count 2 2006.201.20:44:08.36#ibcon#read 5, iclass 2, count 2 2006.201.20:44:08.36#ibcon#about to read 6, iclass 2, count 2 2006.201.20:44:08.36#ibcon#read 6, iclass 2, count 2 2006.201.20:44:08.36#ibcon#end of sib2, iclass 2, count 2 2006.201.20:44:08.36#ibcon#*mode == 0, iclass 2, count 2 2006.201.20:44:08.36#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.20:44:08.36#ibcon#[25=AT05-04\r\n] 2006.201.20:44:08.36#ibcon#*before write, iclass 2, count 2 2006.201.20:44:08.36#ibcon#enter sib2, iclass 2, count 2 2006.201.20:44:08.36#ibcon#flushed, iclass 2, count 2 2006.201.20:44:08.36#ibcon#about to write, iclass 2, count 2 2006.201.20:44:08.36#ibcon#wrote, iclass 2, count 2 2006.201.20:44:08.36#ibcon#about to read 3, iclass 2, count 2 2006.201.20:44:08.40#ibcon#read 3, iclass 2, count 2 2006.201.20:44:08.40#ibcon#about to read 4, iclass 2, count 2 2006.201.20:44:08.40#ibcon#read 4, iclass 2, count 2 2006.201.20:44:08.40#ibcon#about to read 5, iclass 2, count 2 2006.201.20:44:08.40#ibcon#read 5, iclass 2, count 2 2006.201.20:44:08.40#ibcon#about to read 6, iclass 2, count 2 2006.201.20:44:08.40#ibcon#read 6, iclass 2, count 2 2006.201.20:44:08.40#ibcon#end of sib2, iclass 2, count 2 2006.201.20:44:08.40#ibcon#*after write, iclass 2, count 2 2006.201.20:44:08.40#ibcon#*before return 0, iclass 2, count 2 2006.201.20:44:08.40#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:08.40#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:08.40#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.20:44:08.40#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:08.40#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:08.52#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:08.52#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:08.52#ibcon#enter wrdev, iclass 2, count 0 2006.201.20:44:08.52#ibcon#first serial, iclass 2, count 0 2006.201.20:44:08.52#ibcon#enter sib2, iclass 2, count 0 2006.201.20:44:08.52#ibcon#flushed, iclass 2, count 0 2006.201.20:44:08.52#ibcon#about to write, iclass 2, count 0 2006.201.20:44:08.52#ibcon#wrote, iclass 2, count 0 2006.201.20:44:08.52#ibcon#about to read 3, iclass 2, count 0 2006.201.20:44:08.54#ibcon#read 3, iclass 2, count 0 2006.201.20:44:08.54#ibcon#about to read 4, iclass 2, count 0 2006.201.20:44:08.54#ibcon#read 4, iclass 2, count 0 2006.201.20:44:08.54#ibcon#about to read 5, iclass 2, count 0 2006.201.20:44:08.54#ibcon#read 5, iclass 2, count 0 2006.201.20:44:08.54#ibcon#about to read 6, iclass 2, count 0 2006.201.20:44:08.54#ibcon#read 6, iclass 2, count 0 2006.201.20:44:08.54#ibcon#end of sib2, iclass 2, count 0 2006.201.20:44:08.54#ibcon#*mode == 0, iclass 2, count 0 2006.201.20:44:08.54#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.20:44:08.54#ibcon#[25=USB\r\n] 2006.201.20:44:08.54#ibcon#*before write, iclass 2, count 0 2006.201.20:44:08.54#ibcon#enter sib2, iclass 2, count 0 2006.201.20:44:08.54#ibcon#flushed, iclass 2, count 0 2006.201.20:44:08.54#ibcon#about to write, iclass 2, count 0 2006.201.20:44:08.54#ibcon#wrote, iclass 2, count 0 2006.201.20:44:08.54#ibcon#about to read 3, iclass 2, count 0 2006.201.20:44:08.57#ibcon#read 3, iclass 2, count 0 2006.201.20:44:08.57#ibcon#about to read 4, iclass 2, count 0 2006.201.20:44:08.57#ibcon#read 4, iclass 2, count 0 2006.201.20:44:08.57#ibcon#about to read 5, iclass 2, count 0 2006.201.20:44:08.57#ibcon#read 5, iclass 2, count 0 2006.201.20:44:08.57#ibcon#about to read 6, iclass 2, count 0 2006.201.20:44:08.57#ibcon#read 6, iclass 2, count 0 2006.201.20:44:08.57#ibcon#end of sib2, iclass 2, count 0 2006.201.20:44:08.57#ibcon#*after write, iclass 2, count 0 2006.201.20:44:08.57#ibcon#*before return 0, iclass 2, count 0 2006.201.20:44:08.57#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:08.57#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:08.57#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.20:44:08.57#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.20:44:08.57$vck44/valo=6,814.99 2006.201.20:44:08.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.20:44:08.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.20:44:08.57#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:08.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:08.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:08.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:08.57#ibcon#enter wrdev, iclass 5, count 0 2006.201.20:44:08.57#ibcon#first serial, iclass 5, count 0 2006.201.20:44:08.57#ibcon#enter sib2, iclass 5, count 0 2006.201.20:44:08.57#ibcon#flushed, iclass 5, count 0 2006.201.20:44:08.57#ibcon#about to write, iclass 5, count 0 2006.201.20:44:08.57#ibcon#wrote, iclass 5, count 0 2006.201.20:44:08.57#ibcon#about to read 3, iclass 5, count 0 2006.201.20:44:08.59#ibcon#read 3, iclass 5, count 0 2006.201.20:44:08.59#ibcon#about to read 4, iclass 5, count 0 2006.201.20:44:08.59#ibcon#read 4, iclass 5, count 0 2006.201.20:44:08.59#ibcon#about to read 5, iclass 5, count 0 2006.201.20:44:08.59#ibcon#read 5, iclass 5, count 0 2006.201.20:44:08.59#ibcon#about to read 6, iclass 5, count 0 2006.201.20:44:08.59#ibcon#read 6, iclass 5, count 0 2006.201.20:44:08.59#ibcon#end of sib2, iclass 5, count 0 2006.201.20:44:08.59#ibcon#*mode == 0, iclass 5, count 0 2006.201.20:44:08.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.20:44:08.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:44:08.59#ibcon#*before write, iclass 5, count 0 2006.201.20:44:08.59#ibcon#enter sib2, iclass 5, count 0 2006.201.20:44:08.59#ibcon#flushed, iclass 5, count 0 2006.201.20:44:08.59#ibcon#about to write, iclass 5, count 0 2006.201.20:44:08.59#ibcon#wrote, iclass 5, count 0 2006.201.20:44:08.59#ibcon#about to read 3, iclass 5, count 0 2006.201.20:44:08.63#ibcon#read 3, iclass 5, count 0 2006.201.20:44:08.63#ibcon#about to read 4, iclass 5, count 0 2006.201.20:44:08.63#ibcon#read 4, iclass 5, count 0 2006.201.20:44:08.63#ibcon#about to read 5, iclass 5, count 0 2006.201.20:44:08.63#ibcon#read 5, iclass 5, count 0 2006.201.20:44:08.63#ibcon#about to read 6, iclass 5, count 0 2006.201.20:44:08.63#ibcon#read 6, iclass 5, count 0 2006.201.20:44:08.63#ibcon#end of sib2, iclass 5, count 0 2006.201.20:44:08.63#ibcon#*after write, iclass 5, count 0 2006.201.20:44:08.63#ibcon#*before return 0, iclass 5, count 0 2006.201.20:44:08.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:08.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:08.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.20:44:08.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.20:44:08.63$vck44/va=6,5 2006.201.20:44:08.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.20:44:08.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.20:44:08.63#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:08.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:08.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:08.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:08.69#ibcon#enter wrdev, iclass 7, count 2 2006.201.20:44:08.69#ibcon#first serial, iclass 7, count 2 2006.201.20:44:08.69#ibcon#enter sib2, iclass 7, count 2 2006.201.20:44:08.69#ibcon#flushed, iclass 7, count 2 2006.201.20:44:08.69#ibcon#about to write, iclass 7, count 2 2006.201.20:44:08.69#ibcon#wrote, iclass 7, count 2 2006.201.20:44:08.69#ibcon#about to read 3, iclass 7, count 2 2006.201.20:44:08.71#ibcon#read 3, iclass 7, count 2 2006.201.20:44:08.71#ibcon#about to read 4, iclass 7, count 2 2006.201.20:44:08.71#ibcon#read 4, iclass 7, count 2 2006.201.20:44:08.71#ibcon#about to read 5, iclass 7, count 2 2006.201.20:44:08.71#ibcon#read 5, iclass 7, count 2 2006.201.20:44:08.71#ibcon#about to read 6, iclass 7, count 2 2006.201.20:44:08.71#ibcon#read 6, iclass 7, count 2 2006.201.20:44:08.71#ibcon#end of sib2, iclass 7, count 2 2006.201.20:44:08.71#ibcon#*mode == 0, iclass 7, count 2 2006.201.20:44:08.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.20:44:08.71#ibcon#[25=AT06-05\r\n] 2006.201.20:44:08.71#ibcon#*before write, iclass 7, count 2 2006.201.20:44:08.71#ibcon#enter sib2, iclass 7, count 2 2006.201.20:44:08.71#ibcon#flushed, iclass 7, count 2 2006.201.20:44:08.71#ibcon#about to write, iclass 7, count 2 2006.201.20:44:08.71#ibcon#wrote, iclass 7, count 2 2006.201.20:44:08.71#ibcon#about to read 3, iclass 7, count 2 2006.201.20:44:08.74#ibcon#read 3, iclass 7, count 2 2006.201.20:44:08.74#ibcon#about to read 4, iclass 7, count 2 2006.201.20:44:08.74#ibcon#read 4, iclass 7, count 2 2006.201.20:44:08.74#ibcon#about to read 5, iclass 7, count 2 2006.201.20:44:08.74#ibcon#read 5, iclass 7, count 2 2006.201.20:44:08.74#ibcon#about to read 6, iclass 7, count 2 2006.201.20:44:08.74#ibcon#read 6, iclass 7, count 2 2006.201.20:44:08.74#ibcon#end of sib2, iclass 7, count 2 2006.201.20:44:08.74#ibcon#*after write, iclass 7, count 2 2006.201.20:44:08.74#ibcon#*before return 0, iclass 7, count 2 2006.201.20:44:08.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:08.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:08.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.20:44:08.74#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:08.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:08.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:08.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:08.86#ibcon#enter wrdev, iclass 7, count 0 2006.201.20:44:08.86#ibcon#first serial, iclass 7, count 0 2006.201.20:44:08.86#ibcon#enter sib2, iclass 7, count 0 2006.201.20:44:08.86#ibcon#flushed, iclass 7, count 0 2006.201.20:44:08.86#ibcon#about to write, iclass 7, count 0 2006.201.20:44:08.86#ibcon#wrote, iclass 7, count 0 2006.201.20:44:08.86#ibcon#about to read 3, iclass 7, count 0 2006.201.20:44:08.88#ibcon#read 3, iclass 7, count 0 2006.201.20:44:08.88#ibcon#about to read 4, iclass 7, count 0 2006.201.20:44:08.88#ibcon#read 4, iclass 7, count 0 2006.201.20:44:08.88#ibcon#about to read 5, iclass 7, count 0 2006.201.20:44:08.88#ibcon#read 5, iclass 7, count 0 2006.201.20:44:08.88#ibcon#about to read 6, iclass 7, count 0 2006.201.20:44:08.88#ibcon#read 6, iclass 7, count 0 2006.201.20:44:08.88#ibcon#end of sib2, iclass 7, count 0 2006.201.20:44:08.88#ibcon#*mode == 0, iclass 7, count 0 2006.201.20:44:08.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.20:44:08.88#ibcon#[25=USB\r\n] 2006.201.20:44:08.88#ibcon#*before write, iclass 7, count 0 2006.201.20:44:08.88#ibcon#enter sib2, iclass 7, count 0 2006.201.20:44:08.88#ibcon#flushed, iclass 7, count 0 2006.201.20:44:08.88#ibcon#about to write, iclass 7, count 0 2006.201.20:44:08.88#ibcon#wrote, iclass 7, count 0 2006.201.20:44:08.88#ibcon#about to read 3, iclass 7, count 0 2006.201.20:44:08.91#ibcon#read 3, iclass 7, count 0 2006.201.20:44:08.91#ibcon#about to read 4, iclass 7, count 0 2006.201.20:44:08.91#ibcon#read 4, iclass 7, count 0 2006.201.20:44:08.91#ibcon#about to read 5, iclass 7, count 0 2006.201.20:44:08.91#ibcon#read 5, iclass 7, count 0 2006.201.20:44:08.91#ibcon#about to read 6, iclass 7, count 0 2006.201.20:44:08.91#ibcon#read 6, iclass 7, count 0 2006.201.20:44:08.91#ibcon#end of sib2, iclass 7, count 0 2006.201.20:44:08.91#ibcon#*after write, iclass 7, count 0 2006.201.20:44:08.91#ibcon#*before return 0, iclass 7, count 0 2006.201.20:44:08.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:08.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:08.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.20:44:08.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.20:44:08.91$vck44/valo=7,864.99 2006.201.20:44:08.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.20:44:08.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.20:44:08.91#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:08.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:08.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:08.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:08.91#ibcon#enter wrdev, iclass 11, count 0 2006.201.20:44:08.91#ibcon#first serial, iclass 11, count 0 2006.201.20:44:08.91#ibcon#enter sib2, iclass 11, count 0 2006.201.20:44:08.91#ibcon#flushed, iclass 11, count 0 2006.201.20:44:08.91#ibcon#about to write, iclass 11, count 0 2006.201.20:44:08.91#ibcon#wrote, iclass 11, count 0 2006.201.20:44:08.91#ibcon#about to read 3, iclass 11, count 0 2006.201.20:44:08.93#ibcon#read 3, iclass 11, count 0 2006.201.20:44:08.93#ibcon#about to read 4, iclass 11, count 0 2006.201.20:44:08.93#ibcon#read 4, iclass 11, count 0 2006.201.20:44:08.93#ibcon#about to read 5, iclass 11, count 0 2006.201.20:44:08.93#ibcon#read 5, iclass 11, count 0 2006.201.20:44:08.93#ibcon#about to read 6, iclass 11, count 0 2006.201.20:44:08.93#ibcon#read 6, iclass 11, count 0 2006.201.20:44:08.93#ibcon#end of sib2, iclass 11, count 0 2006.201.20:44:08.93#ibcon#*mode == 0, iclass 11, count 0 2006.201.20:44:08.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.20:44:08.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:44:08.93#ibcon#*before write, iclass 11, count 0 2006.201.20:44:08.93#ibcon#enter sib2, iclass 11, count 0 2006.201.20:44:08.93#ibcon#flushed, iclass 11, count 0 2006.201.20:44:08.93#ibcon#about to write, iclass 11, count 0 2006.201.20:44:08.93#ibcon#wrote, iclass 11, count 0 2006.201.20:44:08.93#ibcon#about to read 3, iclass 11, count 0 2006.201.20:44:08.97#ibcon#read 3, iclass 11, count 0 2006.201.20:44:08.97#ibcon#about to read 4, iclass 11, count 0 2006.201.20:44:08.97#ibcon#read 4, iclass 11, count 0 2006.201.20:44:08.97#ibcon#about to read 5, iclass 11, count 0 2006.201.20:44:08.97#ibcon#read 5, iclass 11, count 0 2006.201.20:44:08.97#ibcon#about to read 6, iclass 11, count 0 2006.201.20:44:08.97#ibcon#read 6, iclass 11, count 0 2006.201.20:44:08.97#ibcon#end of sib2, iclass 11, count 0 2006.201.20:44:08.97#ibcon#*after write, iclass 11, count 0 2006.201.20:44:08.97#ibcon#*before return 0, iclass 11, count 0 2006.201.20:44:08.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:08.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:08.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.20:44:08.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.20:44:08.97$vck44/va=7,5 2006.201.20:44:08.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.20:44:08.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.20:44:08.97#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:08.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:09.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:09.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:09.03#ibcon#enter wrdev, iclass 13, count 2 2006.201.20:44:09.03#ibcon#first serial, iclass 13, count 2 2006.201.20:44:09.03#ibcon#enter sib2, iclass 13, count 2 2006.201.20:44:09.03#ibcon#flushed, iclass 13, count 2 2006.201.20:44:09.03#ibcon#about to write, iclass 13, count 2 2006.201.20:44:09.03#ibcon#wrote, iclass 13, count 2 2006.201.20:44:09.03#ibcon#about to read 3, iclass 13, count 2 2006.201.20:44:09.05#ibcon#read 3, iclass 13, count 2 2006.201.20:44:09.05#ibcon#about to read 4, iclass 13, count 2 2006.201.20:44:09.05#ibcon#read 4, iclass 13, count 2 2006.201.20:44:09.05#ibcon#about to read 5, iclass 13, count 2 2006.201.20:44:09.05#ibcon#read 5, iclass 13, count 2 2006.201.20:44:09.05#ibcon#about to read 6, iclass 13, count 2 2006.201.20:44:09.05#ibcon#read 6, iclass 13, count 2 2006.201.20:44:09.05#ibcon#end of sib2, iclass 13, count 2 2006.201.20:44:09.05#ibcon#*mode == 0, iclass 13, count 2 2006.201.20:44:09.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.20:44:09.05#ibcon#[25=AT07-05\r\n] 2006.201.20:44:09.05#ibcon#*before write, iclass 13, count 2 2006.201.20:44:09.05#ibcon#enter sib2, iclass 13, count 2 2006.201.20:44:09.05#ibcon#flushed, iclass 13, count 2 2006.201.20:44:09.05#ibcon#about to write, iclass 13, count 2 2006.201.20:44:09.05#ibcon#wrote, iclass 13, count 2 2006.201.20:44:09.05#ibcon#about to read 3, iclass 13, count 2 2006.201.20:44:09.08#ibcon#read 3, iclass 13, count 2 2006.201.20:44:09.08#ibcon#about to read 4, iclass 13, count 2 2006.201.20:44:09.08#ibcon#read 4, iclass 13, count 2 2006.201.20:44:09.08#ibcon#about to read 5, iclass 13, count 2 2006.201.20:44:09.08#ibcon#read 5, iclass 13, count 2 2006.201.20:44:09.08#ibcon#about to read 6, iclass 13, count 2 2006.201.20:44:09.08#ibcon#read 6, iclass 13, count 2 2006.201.20:44:09.08#ibcon#end of sib2, iclass 13, count 2 2006.201.20:44:09.08#ibcon#*after write, iclass 13, count 2 2006.201.20:44:09.08#ibcon#*before return 0, iclass 13, count 2 2006.201.20:44:09.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:09.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:09.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.20:44:09.08#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:09.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:09.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:09.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:09.20#ibcon#enter wrdev, iclass 13, count 0 2006.201.20:44:09.20#ibcon#first serial, iclass 13, count 0 2006.201.20:44:09.20#ibcon#enter sib2, iclass 13, count 0 2006.201.20:44:09.20#ibcon#flushed, iclass 13, count 0 2006.201.20:44:09.20#ibcon#about to write, iclass 13, count 0 2006.201.20:44:09.20#ibcon#wrote, iclass 13, count 0 2006.201.20:44:09.20#ibcon#about to read 3, iclass 13, count 0 2006.201.20:44:09.22#ibcon#read 3, iclass 13, count 0 2006.201.20:44:09.22#ibcon#about to read 4, iclass 13, count 0 2006.201.20:44:09.22#ibcon#read 4, iclass 13, count 0 2006.201.20:44:09.22#ibcon#about to read 5, iclass 13, count 0 2006.201.20:44:09.22#ibcon#read 5, iclass 13, count 0 2006.201.20:44:09.22#ibcon#about to read 6, iclass 13, count 0 2006.201.20:44:09.22#ibcon#read 6, iclass 13, count 0 2006.201.20:44:09.22#ibcon#end of sib2, iclass 13, count 0 2006.201.20:44:09.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.20:44:09.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.20:44:09.22#ibcon#[25=USB\r\n] 2006.201.20:44:09.22#ibcon#*before write, iclass 13, count 0 2006.201.20:44:09.22#ibcon#enter sib2, iclass 13, count 0 2006.201.20:44:09.22#ibcon#flushed, iclass 13, count 0 2006.201.20:44:09.22#ibcon#about to write, iclass 13, count 0 2006.201.20:44:09.22#ibcon#wrote, iclass 13, count 0 2006.201.20:44:09.22#ibcon#about to read 3, iclass 13, count 0 2006.201.20:44:09.25#ibcon#read 3, iclass 13, count 0 2006.201.20:44:09.25#ibcon#about to read 4, iclass 13, count 0 2006.201.20:44:09.25#ibcon#read 4, iclass 13, count 0 2006.201.20:44:09.25#ibcon#about to read 5, iclass 13, count 0 2006.201.20:44:09.25#ibcon#read 5, iclass 13, count 0 2006.201.20:44:09.25#ibcon#about to read 6, iclass 13, count 0 2006.201.20:44:09.25#ibcon#read 6, iclass 13, count 0 2006.201.20:44:09.25#ibcon#end of sib2, iclass 13, count 0 2006.201.20:44:09.25#ibcon#*after write, iclass 13, count 0 2006.201.20:44:09.25#ibcon#*before return 0, iclass 13, count 0 2006.201.20:44:09.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:09.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:09.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.20:44:09.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.20:44:09.25$vck44/valo=8,884.99 2006.201.20:44:09.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.20:44:09.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.20:44:09.25#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:09.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:09.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:09.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:09.25#ibcon#enter wrdev, iclass 15, count 0 2006.201.20:44:09.25#ibcon#first serial, iclass 15, count 0 2006.201.20:44:09.25#ibcon#enter sib2, iclass 15, count 0 2006.201.20:44:09.25#ibcon#flushed, iclass 15, count 0 2006.201.20:44:09.25#ibcon#about to write, iclass 15, count 0 2006.201.20:44:09.25#ibcon#wrote, iclass 15, count 0 2006.201.20:44:09.25#ibcon#about to read 3, iclass 15, count 0 2006.201.20:44:09.27#ibcon#read 3, iclass 15, count 0 2006.201.20:44:09.27#ibcon#about to read 4, iclass 15, count 0 2006.201.20:44:09.27#ibcon#read 4, iclass 15, count 0 2006.201.20:44:09.27#ibcon#about to read 5, iclass 15, count 0 2006.201.20:44:09.27#ibcon#read 5, iclass 15, count 0 2006.201.20:44:09.27#ibcon#about to read 6, iclass 15, count 0 2006.201.20:44:09.27#ibcon#read 6, iclass 15, count 0 2006.201.20:44:09.27#ibcon#end of sib2, iclass 15, count 0 2006.201.20:44:09.27#ibcon#*mode == 0, iclass 15, count 0 2006.201.20:44:09.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.20:44:09.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:44:09.27#ibcon#*before write, iclass 15, count 0 2006.201.20:44:09.27#ibcon#enter sib2, iclass 15, count 0 2006.201.20:44:09.27#ibcon#flushed, iclass 15, count 0 2006.201.20:44:09.27#ibcon#about to write, iclass 15, count 0 2006.201.20:44:09.27#ibcon#wrote, iclass 15, count 0 2006.201.20:44:09.27#ibcon#about to read 3, iclass 15, count 0 2006.201.20:44:09.31#ibcon#read 3, iclass 15, count 0 2006.201.20:44:09.31#ibcon#about to read 4, iclass 15, count 0 2006.201.20:44:09.31#ibcon#read 4, iclass 15, count 0 2006.201.20:44:09.31#ibcon#about to read 5, iclass 15, count 0 2006.201.20:44:09.31#ibcon#read 5, iclass 15, count 0 2006.201.20:44:09.31#ibcon#about to read 6, iclass 15, count 0 2006.201.20:44:09.31#ibcon#read 6, iclass 15, count 0 2006.201.20:44:09.31#ibcon#end of sib2, iclass 15, count 0 2006.201.20:44:09.31#ibcon#*after write, iclass 15, count 0 2006.201.20:44:09.31#ibcon#*before return 0, iclass 15, count 0 2006.201.20:44:09.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:09.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:09.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.20:44:09.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.20:44:09.31$vck44/va=8,4 2006.201.20:44:09.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.20:44:09.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.20:44:09.31#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:09.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:44:09.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:44:09.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:44:09.37#ibcon#enter wrdev, iclass 17, count 2 2006.201.20:44:09.37#ibcon#first serial, iclass 17, count 2 2006.201.20:44:09.37#ibcon#enter sib2, iclass 17, count 2 2006.201.20:44:09.37#ibcon#flushed, iclass 17, count 2 2006.201.20:44:09.37#ibcon#about to write, iclass 17, count 2 2006.201.20:44:09.37#ibcon#wrote, iclass 17, count 2 2006.201.20:44:09.37#ibcon#about to read 3, iclass 17, count 2 2006.201.20:44:09.39#ibcon#read 3, iclass 17, count 2 2006.201.20:44:09.39#ibcon#about to read 4, iclass 17, count 2 2006.201.20:44:09.39#ibcon#read 4, iclass 17, count 2 2006.201.20:44:09.39#ibcon#about to read 5, iclass 17, count 2 2006.201.20:44:09.39#ibcon#read 5, iclass 17, count 2 2006.201.20:44:09.39#ibcon#about to read 6, iclass 17, count 2 2006.201.20:44:09.39#ibcon#read 6, iclass 17, count 2 2006.201.20:44:09.39#ibcon#end of sib2, iclass 17, count 2 2006.201.20:44:09.39#ibcon#*mode == 0, iclass 17, count 2 2006.201.20:44:09.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.20:44:09.39#ibcon#[25=AT08-04\r\n] 2006.201.20:44:09.39#ibcon#*before write, iclass 17, count 2 2006.201.20:44:09.39#ibcon#enter sib2, iclass 17, count 2 2006.201.20:44:09.39#ibcon#flushed, iclass 17, count 2 2006.201.20:44:09.39#ibcon#about to write, iclass 17, count 2 2006.201.20:44:09.39#ibcon#wrote, iclass 17, count 2 2006.201.20:44:09.39#ibcon#about to read 3, iclass 17, count 2 2006.201.20:44:09.42#ibcon#read 3, iclass 17, count 2 2006.201.20:44:09.42#ibcon#about to read 4, iclass 17, count 2 2006.201.20:44:09.42#ibcon#read 4, iclass 17, count 2 2006.201.20:44:09.42#ibcon#about to read 5, iclass 17, count 2 2006.201.20:44:09.42#ibcon#read 5, iclass 17, count 2 2006.201.20:44:09.42#ibcon#about to read 6, iclass 17, count 2 2006.201.20:44:09.42#ibcon#read 6, iclass 17, count 2 2006.201.20:44:09.42#ibcon#end of sib2, iclass 17, count 2 2006.201.20:44:09.42#ibcon#*after write, iclass 17, count 2 2006.201.20:44:09.42#ibcon#*before return 0, iclass 17, count 2 2006.201.20:44:09.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:44:09.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.20:44:09.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.20:44:09.42#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:09.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:44:09.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:44:09.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:44:09.54#ibcon#enter wrdev, iclass 17, count 0 2006.201.20:44:09.54#ibcon#first serial, iclass 17, count 0 2006.201.20:44:09.54#ibcon#enter sib2, iclass 17, count 0 2006.201.20:44:09.54#ibcon#flushed, iclass 17, count 0 2006.201.20:44:09.54#ibcon#about to write, iclass 17, count 0 2006.201.20:44:09.54#ibcon#wrote, iclass 17, count 0 2006.201.20:44:09.54#ibcon#about to read 3, iclass 17, count 0 2006.201.20:44:09.56#ibcon#read 3, iclass 17, count 0 2006.201.20:44:09.56#ibcon#about to read 4, iclass 17, count 0 2006.201.20:44:09.56#ibcon#read 4, iclass 17, count 0 2006.201.20:44:09.56#ibcon#about to read 5, iclass 17, count 0 2006.201.20:44:09.56#ibcon#read 5, iclass 17, count 0 2006.201.20:44:09.56#ibcon#about to read 6, iclass 17, count 0 2006.201.20:44:09.56#ibcon#read 6, iclass 17, count 0 2006.201.20:44:09.56#ibcon#end of sib2, iclass 17, count 0 2006.201.20:44:09.56#ibcon#*mode == 0, iclass 17, count 0 2006.201.20:44:09.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.20:44:09.56#ibcon#[25=USB\r\n] 2006.201.20:44:09.56#ibcon#*before write, iclass 17, count 0 2006.201.20:44:09.56#ibcon#enter sib2, iclass 17, count 0 2006.201.20:44:09.56#ibcon#flushed, iclass 17, count 0 2006.201.20:44:09.56#ibcon#about to write, iclass 17, count 0 2006.201.20:44:09.56#ibcon#wrote, iclass 17, count 0 2006.201.20:44:09.56#ibcon#about to read 3, iclass 17, count 0 2006.201.20:44:09.59#ibcon#read 3, iclass 17, count 0 2006.201.20:44:09.59#ibcon#about to read 4, iclass 17, count 0 2006.201.20:44:09.59#ibcon#read 4, iclass 17, count 0 2006.201.20:44:09.59#ibcon#about to read 5, iclass 17, count 0 2006.201.20:44:09.59#ibcon#read 5, iclass 17, count 0 2006.201.20:44:09.59#ibcon#about to read 6, iclass 17, count 0 2006.201.20:44:09.59#ibcon#read 6, iclass 17, count 0 2006.201.20:44:09.59#ibcon#end of sib2, iclass 17, count 0 2006.201.20:44:09.59#ibcon#*after write, iclass 17, count 0 2006.201.20:44:09.59#ibcon#*before return 0, iclass 17, count 0 2006.201.20:44:09.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:44:09.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.20:44:09.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.20:44:09.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.20:44:09.59$vck44/vblo=1,629.99 2006.201.20:44:09.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.20:44:09.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.20:44:09.59#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:09.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:44:09.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:44:09.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:44:09.59#ibcon#enter wrdev, iclass 19, count 0 2006.201.20:44:09.59#ibcon#first serial, iclass 19, count 0 2006.201.20:44:09.59#ibcon#enter sib2, iclass 19, count 0 2006.201.20:44:09.59#ibcon#flushed, iclass 19, count 0 2006.201.20:44:09.59#ibcon#about to write, iclass 19, count 0 2006.201.20:44:09.59#ibcon#wrote, iclass 19, count 0 2006.201.20:44:09.59#ibcon#about to read 3, iclass 19, count 0 2006.201.20:44:09.61#ibcon#read 3, iclass 19, count 0 2006.201.20:44:09.61#ibcon#about to read 4, iclass 19, count 0 2006.201.20:44:09.61#ibcon#read 4, iclass 19, count 0 2006.201.20:44:09.61#ibcon#about to read 5, iclass 19, count 0 2006.201.20:44:09.61#ibcon#read 5, iclass 19, count 0 2006.201.20:44:09.61#ibcon#about to read 6, iclass 19, count 0 2006.201.20:44:09.61#ibcon#read 6, iclass 19, count 0 2006.201.20:44:09.61#ibcon#end of sib2, iclass 19, count 0 2006.201.20:44:09.61#ibcon#*mode == 0, iclass 19, count 0 2006.201.20:44:09.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.20:44:09.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:44:09.61#ibcon#*before write, iclass 19, count 0 2006.201.20:44:09.61#ibcon#enter sib2, iclass 19, count 0 2006.201.20:44:09.61#ibcon#flushed, iclass 19, count 0 2006.201.20:44:09.61#ibcon#about to write, iclass 19, count 0 2006.201.20:44:09.61#ibcon#wrote, iclass 19, count 0 2006.201.20:44:09.61#ibcon#about to read 3, iclass 19, count 0 2006.201.20:44:09.65#ibcon#read 3, iclass 19, count 0 2006.201.20:44:09.65#ibcon#about to read 4, iclass 19, count 0 2006.201.20:44:09.65#ibcon#read 4, iclass 19, count 0 2006.201.20:44:09.65#ibcon#about to read 5, iclass 19, count 0 2006.201.20:44:09.65#ibcon#read 5, iclass 19, count 0 2006.201.20:44:09.65#ibcon#about to read 6, iclass 19, count 0 2006.201.20:44:09.65#ibcon#read 6, iclass 19, count 0 2006.201.20:44:09.65#ibcon#end of sib2, iclass 19, count 0 2006.201.20:44:09.65#ibcon#*after write, iclass 19, count 0 2006.201.20:44:09.65#ibcon#*before return 0, iclass 19, count 0 2006.201.20:44:09.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:44:09.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.20:44:09.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.20:44:09.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.20:44:09.65$vck44/vb=1,4 2006.201.20:44:09.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.20:44:09.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.20:44:09.65#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:09.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:44:09.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:44:09.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:44:09.65#ibcon#enter wrdev, iclass 21, count 2 2006.201.20:44:09.65#ibcon#first serial, iclass 21, count 2 2006.201.20:44:09.65#ibcon#enter sib2, iclass 21, count 2 2006.201.20:44:09.65#ibcon#flushed, iclass 21, count 2 2006.201.20:44:09.65#ibcon#about to write, iclass 21, count 2 2006.201.20:44:09.65#ibcon#wrote, iclass 21, count 2 2006.201.20:44:09.65#ibcon#about to read 3, iclass 21, count 2 2006.201.20:44:09.67#ibcon#read 3, iclass 21, count 2 2006.201.20:44:09.67#ibcon#about to read 4, iclass 21, count 2 2006.201.20:44:09.67#ibcon#read 4, iclass 21, count 2 2006.201.20:44:09.67#ibcon#about to read 5, iclass 21, count 2 2006.201.20:44:09.67#ibcon#read 5, iclass 21, count 2 2006.201.20:44:09.67#ibcon#about to read 6, iclass 21, count 2 2006.201.20:44:09.67#ibcon#read 6, iclass 21, count 2 2006.201.20:44:09.67#ibcon#end of sib2, iclass 21, count 2 2006.201.20:44:09.67#ibcon#*mode == 0, iclass 21, count 2 2006.201.20:44:09.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.20:44:09.67#ibcon#[27=AT01-04\r\n] 2006.201.20:44:09.67#ibcon#*before write, iclass 21, count 2 2006.201.20:44:09.67#ibcon#enter sib2, iclass 21, count 2 2006.201.20:44:09.67#ibcon#flushed, iclass 21, count 2 2006.201.20:44:09.67#ibcon#about to write, iclass 21, count 2 2006.201.20:44:09.67#ibcon#wrote, iclass 21, count 2 2006.201.20:44:09.67#ibcon#about to read 3, iclass 21, count 2 2006.201.20:44:09.70#ibcon#read 3, iclass 21, count 2 2006.201.20:44:09.70#ibcon#about to read 4, iclass 21, count 2 2006.201.20:44:09.70#ibcon#read 4, iclass 21, count 2 2006.201.20:44:09.70#ibcon#about to read 5, iclass 21, count 2 2006.201.20:44:09.70#ibcon#read 5, iclass 21, count 2 2006.201.20:44:09.70#ibcon#about to read 6, iclass 21, count 2 2006.201.20:44:09.70#ibcon#read 6, iclass 21, count 2 2006.201.20:44:09.70#ibcon#end of sib2, iclass 21, count 2 2006.201.20:44:09.70#ibcon#*after write, iclass 21, count 2 2006.201.20:44:09.70#ibcon#*before return 0, iclass 21, count 2 2006.201.20:44:09.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:44:09.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.20:44:09.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.20:44:09.70#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:09.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:44:09.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:44:09.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:44:09.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.20:44:09.82#ibcon#first serial, iclass 21, count 0 2006.201.20:44:09.82#ibcon#enter sib2, iclass 21, count 0 2006.201.20:44:09.82#ibcon#flushed, iclass 21, count 0 2006.201.20:44:09.82#ibcon#about to write, iclass 21, count 0 2006.201.20:44:09.82#ibcon#wrote, iclass 21, count 0 2006.201.20:44:09.82#ibcon#about to read 3, iclass 21, count 0 2006.201.20:44:09.84#ibcon#read 3, iclass 21, count 0 2006.201.20:44:09.84#ibcon#about to read 4, iclass 21, count 0 2006.201.20:44:09.84#ibcon#read 4, iclass 21, count 0 2006.201.20:44:09.84#ibcon#about to read 5, iclass 21, count 0 2006.201.20:44:09.84#ibcon#read 5, iclass 21, count 0 2006.201.20:44:09.84#ibcon#about to read 6, iclass 21, count 0 2006.201.20:44:09.84#ibcon#read 6, iclass 21, count 0 2006.201.20:44:09.84#ibcon#end of sib2, iclass 21, count 0 2006.201.20:44:09.84#ibcon#*mode == 0, iclass 21, count 0 2006.201.20:44:09.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.20:44:09.84#ibcon#[27=USB\r\n] 2006.201.20:44:09.84#ibcon#*before write, iclass 21, count 0 2006.201.20:44:09.84#ibcon#enter sib2, iclass 21, count 0 2006.201.20:44:09.84#ibcon#flushed, iclass 21, count 0 2006.201.20:44:09.84#ibcon#about to write, iclass 21, count 0 2006.201.20:44:09.84#ibcon#wrote, iclass 21, count 0 2006.201.20:44:09.84#ibcon#about to read 3, iclass 21, count 0 2006.201.20:44:09.87#ibcon#read 3, iclass 21, count 0 2006.201.20:44:09.87#ibcon#about to read 4, iclass 21, count 0 2006.201.20:44:09.87#ibcon#read 4, iclass 21, count 0 2006.201.20:44:09.87#ibcon#about to read 5, iclass 21, count 0 2006.201.20:44:09.87#ibcon#read 5, iclass 21, count 0 2006.201.20:44:09.87#ibcon#about to read 6, iclass 21, count 0 2006.201.20:44:09.87#ibcon#read 6, iclass 21, count 0 2006.201.20:44:09.87#ibcon#end of sib2, iclass 21, count 0 2006.201.20:44:09.87#ibcon#*after write, iclass 21, count 0 2006.201.20:44:09.87#ibcon#*before return 0, iclass 21, count 0 2006.201.20:44:09.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:44:09.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.20:44:09.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.20:44:09.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.20:44:09.87$vck44/vblo=2,634.99 2006.201.20:44:09.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.20:44:09.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.20:44:09.87#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:09.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:09.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:09.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:09.87#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:44:09.87#ibcon#first serial, iclass 23, count 0 2006.201.20:44:09.87#ibcon#enter sib2, iclass 23, count 0 2006.201.20:44:09.87#ibcon#flushed, iclass 23, count 0 2006.201.20:44:09.87#ibcon#about to write, iclass 23, count 0 2006.201.20:44:09.87#ibcon#wrote, iclass 23, count 0 2006.201.20:44:09.87#ibcon#about to read 3, iclass 23, count 0 2006.201.20:44:09.89#ibcon#read 3, iclass 23, count 0 2006.201.20:44:09.89#ibcon#about to read 4, iclass 23, count 0 2006.201.20:44:09.89#ibcon#read 4, iclass 23, count 0 2006.201.20:44:09.89#ibcon#about to read 5, iclass 23, count 0 2006.201.20:44:09.89#ibcon#read 5, iclass 23, count 0 2006.201.20:44:09.89#ibcon#about to read 6, iclass 23, count 0 2006.201.20:44:09.89#ibcon#read 6, iclass 23, count 0 2006.201.20:44:09.89#ibcon#end of sib2, iclass 23, count 0 2006.201.20:44:09.89#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:44:09.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:44:09.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:44:09.89#ibcon#*before write, iclass 23, count 0 2006.201.20:44:09.89#ibcon#enter sib2, iclass 23, count 0 2006.201.20:44:09.89#ibcon#flushed, iclass 23, count 0 2006.201.20:44:09.89#ibcon#about to write, iclass 23, count 0 2006.201.20:44:09.89#ibcon#wrote, iclass 23, count 0 2006.201.20:44:09.89#ibcon#about to read 3, iclass 23, count 0 2006.201.20:44:09.94#ibcon#read 3, iclass 23, count 0 2006.201.20:44:09.94#ibcon#about to read 4, iclass 23, count 0 2006.201.20:44:09.94#ibcon#read 4, iclass 23, count 0 2006.201.20:44:09.94#ibcon#about to read 5, iclass 23, count 0 2006.201.20:44:09.94#ibcon#read 5, iclass 23, count 0 2006.201.20:44:09.94#ibcon#about to read 6, iclass 23, count 0 2006.201.20:44:09.94#ibcon#read 6, iclass 23, count 0 2006.201.20:44:09.94#ibcon#end of sib2, iclass 23, count 0 2006.201.20:44:09.94#ibcon#*after write, iclass 23, count 0 2006.201.20:44:09.94#ibcon#*before return 0, iclass 23, count 0 2006.201.20:44:09.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:09.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:44:09.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:44:09.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:44:09.94$vck44/vb=2,5 2006.201.20:44:09.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.20:44:09.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.20:44:09.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:09.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:09.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:09.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:09.99#ibcon#enter wrdev, iclass 25, count 2 2006.201.20:44:09.99#ibcon#first serial, iclass 25, count 2 2006.201.20:44:09.99#ibcon#enter sib2, iclass 25, count 2 2006.201.20:44:09.99#ibcon#flushed, iclass 25, count 2 2006.201.20:44:09.99#ibcon#about to write, iclass 25, count 2 2006.201.20:44:09.99#ibcon#wrote, iclass 25, count 2 2006.201.20:44:09.99#ibcon#about to read 3, iclass 25, count 2 2006.201.20:44:10.01#ibcon#read 3, iclass 25, count 2 2006.201.20:44:10.01#ibcon#about to read 4, iclass 25, count 2 2006.201.20:44:10.01#ibcon#read 4, iclass 25, count 2 2006.201.20:44:10.01#ibcon#about to read 5, iclass 25, count 2 2006.201.20:44:10.01#ibcon#read 5, iclass 25, count 2 2006.201.20:44:10.01#ibcon#about to read 6, iclass 25, count 2 2006.201.20:44:10.01#ibcon#read 6, iclass 25, count 2 2006.201.20:44:10.01#ibcon#end of sib2, iclass 25, count 2 2006.201.20:44:10.01#ibcon#*mode == 0, iclass 25, count 2 2006.201.20:44:10.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.20:44:10.01#ibcon#[27=AT02-05\r\n] 2006.201.20:44:10.01#ibcon#*before write, iclass 25, count 2 2006.201.20:44:10.01#ibcon#enter sib2, iclass 25, count 2 2006.201.20:44:10.01#ibcon#flushed, iclass 25, count 2 2006.201.20:44:10.01#ibcon#about to write, iclass 25, count 2 2006.201.20:44:10.01#ibcon#wrote, iclass 25, count 2 2006.201.20:44:10.01#ibcon#about to read 3, iclass 25, count 2 2006.201.20:44:10.04#ibcon#read 3, iclass 25, count 2 2006.201.20:44:10.04#ibcon#about to read 4, iclass 25, count 2 2006.201.20:44:10.04#ibcon#read 4, iclass 25, count 2 2006.201.20:44:10.04#ibcon#about to read 5, iclass 25, count 2 2006.201.20:44:10.04#ibcon#read 5, iclass 25, count 2 2006.201.20:44:10.04#ibcon#about to read 6, iclass 25, count 2 2006.201.20:44:10.04#ibcon#read 6, iclass 25, count 2 2006.201.20:44:10.04#ibcon#end of sib2, iclass 25, count 2 2006.201.20:44:10.04#ibcon#*after write, iclass 25, count 2 2006.201.20:44:10.04#ibcon#*before return 0, iclass 25, count 2 2006.201.20:44:10.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:10.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.20:44:10.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.20:44:10.04#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:10.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:10.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:10.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:10.16#ibcon#enter wrdev, iclass 25, count 0 2006.201.20:44:10.16#ibcon#first serial, iclass 25, count 0 2006.201.20:44:10.16#ibcon#enter sib2, iclass 25, count 0 2006.201.20:44:10.16#ibcon#flushed, iclass 25, count 0 2006.201.20:44:10.16#ibcon#about to write, iclass 25, count 0 2006.201.20:44:10.16#ibcon#wrote, iclass 25, count 0 2006.201.20:44:10.16#ibcon#about to read 3, iclass 25, count 0 2006.201.20:44:10.18#ibcon#read 3, iclass 25, count 0 2006.201.20:44:10.18#ibcon#about to read 4, iclass 25, count 0 2006.201.20:44:10.18#ibcon#read 4, iclass 25, count 0 2006.201.20:44:10.18#ibcon#about to read 5, iclass 25, count 0 2006.201.20:44:10.18#ibcon#read 5, iclass 25, count 0 2006.201.20:44:10.18#ibcon#about to read 6, iclass 25, count 0 2006.201.20:44:10.18#ibcon#read 6, iclass 25, count 0 2006.201.20:44:10.18#ibcon#end of sib2, iclass 25, count 0 2006.201.20:44:10.18#ibcon#*mode == 0, iclass 25, count 0 2006.201.20:44:10.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.20:44:10.18#ibcon#[27=USB\r\n] 2006.201.20:44:10.18#ibcon#*before write, iclass 25, count 0 2006.201.20:44:10.18#ibcon#enter sib2, iclass 25, count 0 2006.201.20:44:10.18#ibcon#flushed, iclass 25, count 0 2006.201.20:44:10.18#ibcon#about to write, iclass 25, count 0 2006.201.20:44:10.18#ibcon#wrote, iclass 25, count 0 2006.201.20:44:10.18#ibcon#about to read 3, iclass 25, count 0 2006.201.20:44:10.21#ibcon#read 3, iclass 25, count 0 2006.201.20:44:10.21#ibcon#about to read 4, iclass 25, count 0 2006.201.20:44:10.21#ibcon#read 4, iclass 25, count 0 2006.201.20:44:10.21#ibcon#about to read 5, iclass 25, count 0 2006.201.20:44:10.21#ibcon#read 5, iclass 25, count 0 2006.201.20:44:10.21#ibcon#about to read 6, iclass 25, count 0 2006.201.20:44:10.21#ibcon#read 6, iclass 25, count 0 2006.201.20:44:10.21#ibcon#end of sib2, iclass 25, count 0 2006.201.20:44:10.21#ibcon#*after write, iclass 25, count 0 2006.201.20:44:10.21#ibcon#*before return 0, iclass 25, count 0 2006.201.20:44:10.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:10.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.20:44:10.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.20:44:10.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.20:44:10.21$vck44/vblo=3,649.99 2006.201.20:44:10.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.20:44:10.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.20:44:10.21#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:10.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:10.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:10.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:10.21#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:44:10.21#ibcon#first serial, iclass 27, count 0 2006.201.20:44:10.21#ibcon#enter sib2, iclass 27, count 0 2006.201.20:44:10.21#ibcon#flushed, iclass 27, count 0 2006.201.20:44:10.21#ibcon#about to write, iclass 27, count 0 2006.201.20:44:10.21#ibcon#wrote, iclass 27, count 0 2006.201.20:44:10.21#ibcon#about to read 3, iclass 27, count 0 2006.201.20:44:10.23#ibcon#read 3, iclass 27, count 0 2006.201.20:44:10.23#ibcon#about to read 4, iclass 27, count 0 2006.201.20:44:10.23#ibcon#read 4, iclass 27, count 0 2006.201.20:44:10.23#ibcon#about to read 5, iclass 27, count 0 2006.201.20:44:10.23#ibcon#read 5, iclass 27, count 0 2006.201.20:44:10.23#ibcon#about to read 6, iclass 27, count 0 2006.201.20:44:10.23#ibcon#read 6, iclass 27, count 0 2006.201.20:44:10.23#ibcon#end of sib2, iclass 27, count 0 2006.201.20:44:10.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:44:10.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:44:10.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:44:10.23#ibcon#*before write, iclass 27, count 0 2006.201.20:44:10.23#ibcon#enter sib2, iclass 27, count 0 2006.201.20:44:10.23#ibcon#flushed, iclass 27, count 0 2006.201.20:44:10.23#ibcon#about to write, iclass 27, count 0 2006.201.20:44:10.23#ibcon#wrote, iclass 27, count 0 2006.201.20:44:10.23#ibcon#about to read 3, iclass 27, count 0 2006.201.20:44:10.27#ibcon#read 3, iclass 27, count 0 2006.201.20:44:10.27#ibcon#about to read 4, iclass 27, count 0 2006.201.20:44:10.27#ibcon#read 4, iclass 27, count 0 2006.201.20:44:10.27#ibcon#about to read 5, iclass 27, count 0 2006.201.20:44:10.27#ibcon#read 5, iclass 27, count 0 2006.201.20:44:10.27#ibcon#about to read 6, iclass 27, count 0 2006.201.20:44:10.27#ibcon#read 6, iclass 27, count 0 2006.201.20:44:10.27#ibcon#end of sib2, iclass 27, count 0 2006.201.20:44:10.27#ibcon#*after write, iclass 27, count 0 2006.201.20:44:10.27#ibcon#*before return 0, iclass 27, count 0 2006.201.20:44:10.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:10.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.20:44:10.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:44:10.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:44:10.27$vck44/vb=3,4 2006.201.20:44:10.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.20:44:10.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.20:44:10.27#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:10.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:10.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:10.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:10.33#ibcon#enter wrdev, iclass 29, count 2 2006.201.20:44:10.33#ibcon#first serial, iclass 29, count 2 2006.201.20:44:10.33#ibcon#enter sib2, iclass 29, count 2 2006.201.20:44:10.33#ibcon#flushed, iclass 29, count 2 2006.201.20:44:10.33#ibcon#about to write, iclass 29, count 2 2006.201.20:44:10.33#ibcon#wrote, iclass 29, count 2 2006.201.20:44:10.33#ibcon#about to read 3, iclass 29, count 2 2006.201.20:44:10.35#ibcon#read 3, iclass 29, count 2 2006.201.20:44:10.35#ibcon#about to read 4, iclass 29, count 2 2006.201.20:44:10.35#ibcon#read 4, iclass 29, count 2 2006.201.20:44:10.35#ibcon#about to read 5, iclass 29, count 2 2006.201.20:44:10.35#ibcon#read 5, iclass 29, count 2 2006.201.20:44:10.35#ibcon#about to read 6, iclass 29, count 2 2006.201.20:44:10.35#ibcon#read 6, iclass 29, count 2 2006.201.20:44:10.35#ibcon#end of sib2, iclass 29, count 2 2006.201.20:44:10.35#ibcon#*mode == 0, iclass 29, count 2 2006.201.20:44:10.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.20:44:10.35#ibcon#[27=AT03-04\r\n] 2006.201.20:44:10.35#ibcon#*before write, iclass 29, count 2 2006.201.20:44:10.35#ibcon#enter sib2, iclass 29, count 2 2006.201.20:44:10.35#ibcon#flushed, iclass 29, count 2 2006.201.20:44:10.35#ibcon#about to write, iclass 29, count 2 2006.201.20:44:10.35#ibcon#wrote, iclass 29, count 2 2006.201.20:44:10.35#ibcon#about to read 3, iclass 29, count 2 2006.201.20:44:10.38#ibcon#read 3, iclass 29, count 2 2006.201.20:44:10.38#ibcon#about to read 4, iclass 29, count 2 2006.201.20:44:10.38#ibcon#read 4, iclass 29, count 2 2006.201.20:44:10.38#ibcon#about to read 5, iclass 29, count 2 2006.201.20:44:10.38#ibcon#read 5, iclass 29, count 2 2006.201.20:44:10.38#ibcon#about to read 6, iclass 29, count 2 2006.201.20:44:10.38#ibcon#read 6, iclass 29, count 2 2006.201.20:44:10.38#ibcon#end of sib2, iclass 29, count 2 2006.201.20:44:10.38#ibcon#*after write, iclass 29, count 2 2006.201.20:44:10.38#ibcon#*before return 0, iclass 29, count 2 2006.201.20:44:10.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:10.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.20:44:10.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.20:44:10.38#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:10.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:10.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:10.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:10.50#ibcon#enter wrdev, iclass 29, count 0 2006.201.20:44:10.50#ibcon#first serial, iclass 29, count 0 2006.201.20:44:10.50#ibcon#enter sib2, iclass 29, count 0 2006.201.20:44:10.50#ibcon#flushed, iclass 29, count 0 2006.201.20:44:10.50#ibcon#about to write, iclass 29, count 0 2006.201.20:44:10.50#ibcon#wrote, iclass 29, count 0 2006.201.20:44:10.50#ibcon#about to read 3, iclass 29, count 0 2006.201.20:44:10.52#ibcon#read 3, iclass 29, count 0 2006.201.20:44:10.52#ibcon#about to read 4, iclass 29, count 0 2006.201.20:44:10.52#ibcon#read 4, iclass 29, count 0 2006.201.20:44:10.52#ibcon#about to read 5, iclass 29, count 0 2006.201.20:44:10.52#ibcon#read 5, iclass 29, count 0 2006.201.20:44:10.52#ibcon#about to read 6, iclass 29, count 0 2006.201.20:44:10.52#ibcon#read 6, iclass 29, count 0 2006.201.20:44:10.52#ibcon#end of sib2, iclass 29, count 0 2006.201.20:44:10.52#ibcon#*mode == 0, iclass 29, count 0 2006.201.20:44:10.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.20:44:10.52#ibcon#[27=USB\r\n] 2006.201.20:44:10.52#ibcon#*before write, iclass 29, count 0 2006.201.20:44:10.52#ibcon#enter sib2, iclass 29, count 0 2006.201.20:44:10.52#ibcon#flushed, iclass 29, count 0 2006.201.20:44:10.52#ibcon#about to write, iclass 29, count 0 2006.201.20:44:10.52#ibcon#wrote, iclass 29, count 0 2006.201.20:44:10.52#ibcon#about to read 3, iclass 29, count 0 2006.201.20:44:10.55#ibcon#read 3, iclass 29, count 0 2006.201.20:44:10.55#ibcon#about to read 4, iclass 29, count 0 2006.201.20:44:10.55#ibcon#read 4, iclass 29, count 0 2006.201.20:44:10.55#ibcon#about to read 5, iclass 29, count 0 2006.201.20:44:10.55#ibcon#read 5, iclass 29, count 0 2006.201.20:44:10.55#ibcon#about to read 6, iclass 29, count 0 2006.201.20:44:10.55#ibcon#read 6, iclass 29, count 0 2006.201.20:44:10.55#ibcon#end of sib2, iclass 29, count 0 2006.201.20:44:10.55#ibcon#*after write, iclass 29, count 0 2006.201.20:44:10.55#ibcon#*before return 0, iclass 29, count 0 2006.201.20:44:10.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:10.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.20:44:10.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.20:44:10.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.20:44:10.55$vck44/vblo=4,679.99 2006.201.20:44:10.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.20:44:10.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.20:44:10.55#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:10.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:10.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:10.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:10.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.20:44:10.55#ibcon#first serial, iclass 31, count 0 2006.201.20:44:10.55#ibcon#enter sib2, iclass 31, count 0 2006.201.20:44:10.55#ibcon#flushed, iclass 31, count 0 2006.201.20:44:10.55#ibcon#about to write, iclass 31, count 0 2006.201.20:44:10.55#ibcon#wrote, iclass 31, count 0 2006.201.20:44:10.55#ibcon#about to read 3, iclass 31, count 0 2006.201.20:44:10.57#ibcon#read 3, iclass 31, count 0 2006.201.20:44:10.57#ibcon#about to read 4, iclass 31, count 0 2006.201.20:44:10.57#ibcon#read 4, iclass 31, count 0 2006.201.20:44:10.57#ibcon#about to read 5, iclass 31, count 0 2006.201.20:44:10.57#ibcon#read 5, iclass 31, count 0 2006.201.20:44:10.57#ibcon#about to read 6, iclass 31, count 0 2006.201.20:44:10.57#ibcon#read 6, iclass 31, count 0 2006.201.20:44:10.57#ibcon#end of sib2, iclass 31, count 0 2006.201.20:44:10.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.20:44:10.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.20:44:10.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:44:10.57#ibcon#*before write, iclass 31, count 0 2006.201.20:44:10.57#ibcon#enter sib2, iclass 31, count 0 2006.201.20:44:10.57#ibcon#flushed, iclass 31, count 0 2006.201.20:44:10.57#ibcon#about to write, iclass 31, count 0 2006.201.20:44:10.57#ibcon#wrote, iclass 31, count 0 2006.201.20:44:10.57#ibcon#about to read 3, iclass 31, count 0 2006.201.20:44:10.61#ibcon#read 3, iclass 31, count 0 2006.201.20:44:10.61#ibcon#about to read 4, iclass 31, count 0 2006.201.20:44:10.61#ibcon#read 4, iclass 31, count 0 2006.201.20:44:10.61#ibcon#about to read 5, iclass 31, count 0 2006.201.20:44:10.61#ibcon#read 5, iclass 31, count 0 2006.201.20:44:10.61#ibcon#about to read 6, iclass 31, count 0 2006.201.20:44:10.61#ibcon#read 6, iclass 31, count 0 2006.201.20:44:10.61#ibcon#end of sib2, iclass 31, count 0 2006.201.20:44:10.61#ibcon#*after write, iclass 31, count 0 2006.201.20:44:10.61#ibcon#*before return 0, iclass 31, count 0 2006.201.20:44:10.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:10.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.20:44:10.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.20:44:10.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.20:44:10.61$vck44/vb=4,5 2006.201.20:44:10.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.20:44:10.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.20:44:10.61#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:10.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:10.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:10.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:10.67#ibcon#enter wrdev, iclass 33, count 2 2006.201.20:44:10.67#ibcon#first serial, iclass 33, count 2 2006.201.20:44:10.67#ibcon#enter sib2, iclass 33, count 2 2006.201.20:44:10.67#ibcon#flushed, iclass 33, count 2 2006.201.20:44:10.67#ibcon#about to write, iclass 33, count 2 2006.201.20:44:10.67#ibcon#wrote, iclass 33, count 2 2006.201.20:44:10.67#ibcon#about to read 3, iclass 33, count 2 2006.201.20:44:10.69#ibcon#read 3, iclass 33, count 2 2006.201.20:44:10.69#ibcon#about to read 4, iclass 33, count 2 2006.201.20:44:10.69#ibcon#read 4, iclass 33, count 2 2006.201.20:44:10.69#ibcon#about to read 5, iclass 33, count 2 2006.201.20:44:10.69#ibcon#read 5, iclass 33, count 2 2006.201.20:44:10.69#ibcon#about to read 6, iclass 33, count 2 2006.201.20:44:10.69#ibcon#read 6, iclass 33, count 2 2006.201.20:44:10.69#ibcon#end of sib2, iclass 33, count 2 2006.201.20:44:10.69#ibcon#*mode == 0, iclass 33, count 2 2006.201.20:44:10.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.20:44:10.69#ibcon#[27=AT04-05\r\n] 2006.201.20:44:10.69#ibcon#*before write, iclass 33, count 2 2006.201.20:44:10.69#ibcon#enter sib2, iclass 33, count 2 2006.201.20:44:10.69#ibcon#flushed, iclass 33, count 2 2006.201.20:44:10.69#ibcon#about to write, iclass 33, count 2 2006.201.20:44:10.69#ibcon#wrote, iclass 33, count 2 2006.201.20:44:10.69#ibcon#about to read 3, iclass 33, count 2 2006.201.20:44:10.72#ibcon#read 3, iclass 33, count 2 2006.201.20:44:10.72#ibcon#about to read 4, iclass 33, count 2 2006.201.20:44:10.72#ibcon#read 4, iclass 33, count 2 2006.201.20:44:10.72#ibcon#about to read 5, iclass 33, count 2 2006.201.20:44:10.72#ibcon#read 5, iclass 33, count 2 2006.201.20:44:10.72#ibcon#about to read 6, iclass 33, count 2 2006.201.20:44:10.72#ibcon#read 6, iclass 33, count 2 2006.201.20:44:10.72#ibcon#end of sib2, iclass 33, count 2 2006.201.20:44:10.72#ibcon#*after write, iclass 33, count 2 2006.201.20:44:10.72#ibcon#*before return 0, iclass 33, count 2 2006.201.20:44:10.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:10.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.20:44:10.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.20:44:10.72#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:10.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:10.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:10.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:10.84#ibcon#enter wrdev, iclass 33, count 0 2006.201.20:44:10.84#ibcon#first serial, iclass 33, count 0 2006.201.20:44:10.84#ibcon#enter sib2, iclass 33, count 0 2006.201.20:44:10.84#ibcon#flushed, iclass 33, count 0 2006.201.20:44:10.84#ibcon#about to write, iclass 33, count 0 2006.201.20:44:10.84#ibcon#wrote, iclass 33, count 0 2006.201.20:44:10.84#ibcon#about to read 3, iclass 33, count 0 2006.201.20:44:10.86#ibcon#read 3, iclass 33, count 0 2006.201.20:44:10.86#ibcon#about to read 4, iclass 33, count 0 2006.201.20:44:10.86#ibcon#read 4, iclass 33, count 0 2006.201.20:44:10.86#ibcon#about to read 5, iclass 33, count 0 2006.201.20:44:10.86#ibcon#read 5, iclass 33, count 0 2006.201.20:44:10.86#ibcon#about to read 6, iclass 33, count 0 2006.201.20:44:10.86#ibcon#read 6, iclass 33, count 0 2006.201.20:44:10.86#ibcon#end of sib2, iclass 33, count 0 2006.201.20:44:10.86#ibcon#*mode == 0, iclass 33, count 0 2006.201.20:44:10.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.20:44:10.86#ibcon#[27=USB\r\n] 2006.201.20:44:10.86#ibcon#*before write, iclass 33, count 0 2006.201.20:44:10.86#ibcon#enter sib2, iclass 33, count 0 2006.201.20:44:10.86#ibcon#flushed, iclass 33, count 0 2006.201.20:44:10.86#ibcon#about to write, iclass 33, count 0 2006.201.20:44:10.86#ibcon#wrote, iclass 33, count 0 2006.201.20:44:10.86#ibcon#about to read 3, iclass 33, count 0 2006.201.20:44:10.89#ibcon#read 3, iclass 33, count 0 2006.201.20:44:10.89#ibcon#about to read 4, iclass 33, count 0 2006.201.20:44:10.89#ibcon#read 4, iclass 33, count 0 2006.201.20:44:10.89#ibcon#about to read 5, iclass 33, count 0 2006.201.20:44:10.89#ibcon#read 5, iclass 33, count 0 2006.201.20:44:10.89#ibcon#about to read 6, iclass 33, count 0 2006.201.20:44:10.89#ibcon#read 6, iclass 33, count 0 2006.201.20:44:10.89#ibcon#end of sib2, iclass 33, count 0 2006.201.20:44:10.89#ibcon#*after write, iclass 33, count 0 2006.201.20:44:10.89#ibcon#*before return 0, iclass 33, count 0 2006.201.20:44:10.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:10.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.20:44:10.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.20:44:10.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.20:44:10.89$vck44/vblo=5,709.99 2006.201.20:44:10.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.20:44:10.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.20:44:10.89#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:10.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:10.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:10.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:10.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.20:44:10.89#ibcon#first serial, iclass 35, count 0 2006.201.20:44:10.89#ibcon#enter sib2, iclass 35, count 0 2006.201.20:44:10.89#ibcon#flushed, iclass 35, count 0 2006.201.20:44:10.89#ibcon#about to write, iclass 35, count 0 2006.201.20:44:10.89#ibcon#wrote, iclass 35, count 0 2006.201.20:44:10.89#ibcon#about to read 3, iclass 35, count 0 2006.201.20:44:10.91#ibcon#read 3, iclass 35, count 0 2006.201.20:44:10.91#ibcon#about to read 4, iclass 35, count 0 2006.201.20:44:10.91#ibcon#read 4, iclass 35, count 0 2006.201.20:44:10.91#ibcon#about to read 5, iclass 35, count 0 2006.201.20:44:10.91#ibcon#read 5, iclass 35, count 0 2006.201.20:44:10.91#ibcon#about to read 6, iclass 35, count 0 2006.201.20:44:10.91#ibcon#read 6, iclass 35, count 0 2006.201.20:44:10.91#ibcon#end of sib2, iclass 35, count 0 2006.201.20:44:10.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.20:44:10.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.20:44:10.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:44:10.91#ibcon#*before write, iclass 35, count 0 2006.201.20:44:10.91#ibcon#enter sib2, iclass 35, count 0 2006.201.20:44:10.91#ibcon#flushed, iclass 35, count 0 2006.201.20:44:10.91#ibcon#about to write, iclass 35, count 0 2006.201.20:44:10.91#ibcon#wrote, iclass 35, count 0 2006.201.20:44:10.91#ibcon#about to read 3, iclass 35, count 0 2006.201.20:44:10.95#ibcon#read 3, iclass 35, count 0 2006.201.20:44:10.95#ibcon#about to read 4, iclass 35, count 0 2006.201.20:44:10.95#ibcon#read 4, iclass 35, count 0 2006.201.20:44:10.95#ibcon#about to read 5, iclass 35, count 0 2006.201.20:44:10.95#ibcon#read 5, iclass 35, count 0 2006.201.20:44:10.95#ibcon#about to read 6, iclass 35, count 0 2006.201.20:44:10.95#ibcon#read 6, iclass 35, count 0 2006.201.20:44:10.95#ibcon#end of sib2, iclass 35, count 0 2006.201.20:44:10.95#ibcon#*after write, iclass 35, count 0 2006.201.20:44:10.95#ibcon#*before return 0, iclass 35, count 0 2006.201.20:44:10.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:10.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.20:44:10.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.20:44:10.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.20:44:10.95$vck44/vb=5,4 2006.201.20:44:10.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.20:44:10.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.20:44:10.95#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:10.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:11.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:11.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:11.01#ibcon#enter wrdev, iclass 37, count 2 2006.201.20:44:11.01#ibcon#first serial, iclass 37, count 2 2006.201.20:44:11.01#ibcon#enter sib2, iclass 37, count 2 2006.201.20:44:11.01#ibcon#flushed, iclass 37, count 2 2006.201.20:44:11.01#ibcon#about to write, iclass 37, count 2 2006.201.20:44:11.01#ibcon#wrote, iclass 37, count 2 2006.201.20:44:11.01#ibcon#about to read 3, iclass 37, count 2 2006.201.20:44:11.03#ibcon#read 3, iclass 37, count 2 2006.201.20:44:11.03#ibcon#about to read 4, iclass 37, count 2 2006.201.20:44:11.03#ibcon#read 4, iclass 37, count 2 2006.201.20:44:11.03#ibcon#about to read 5, iclass 37, count 2 2006.201.20:44:11.03#ibcon#read 5, iclass 37, count 2 2006.201.20:44:11.03#ibcon#about to read 6, iclass 37, count 2 2006.201.20:44:11.03#ibcon#read 6, iclass 37, count 2 2006.201.20:44:11.03#ibcon#end of sib2, iclass 37, count 2 2006.201.20:44:11.03#ibcon#*mode == 0, iclass 37, count 2 2006.201.20:44:11.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.20:44:11.03#ibcon#[27=AT05-04\r\n] 2006.201.20:44:11.03#ibcon#*before write, iclass 37, count 2 2006.201.20:44:11.03#ibcon#enter sib2, iclass 37, count 2 2006.201.20:44:11.03#ibcon#flushed, iclass 37, count 2 2006.201.20:44:11.03#ibcon#about to write, iclass 37, count 2 2006.201.20:44:11.03#ibcon#wrote, iclass 37, count 2 2006.201.20:44:11.03#ibcon#about to read 3, iclass 37, count 2 2006.201.20:44:11.06#ibcon#read 3, iclass 37, count 2 2006.201.20:44:11.06#ibcon#about to read 4, iclass 37, count 2 2006.201.20:44:11.06#ibcon#read 4, iclass 37, count 2 2006.201.20:44:11.06#ibcon#about to read 5, iclass 37, count 2 2006.201.20:44:11.06#ibcon#read 5, iclass 37, count 2 2006.201.20:44:11.06#ibcon#about to read 6, iclass 37, count 2 2006.201.20:44:11.06#ibcon#read 6, iclass 37, count 2 2006.201.20:44:11.06#ibcon#end of sib2, iclass 37, count 2 2006.201.20:44:11.06#ibcon#*after write, iclass 37, count 2 2006.201.20:44:11.06#ibcon#*before return 0, iclass 37, count 2 2006.201.20:44:11.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:11.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.20:44:11.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.20:44:11.06#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:11.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:11.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:11.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:11.18#ibcon#enter wrdev, iclass 37, count 0 2006.201.20:44:11.18#ibcon#first serial, iclass 37, count 0 2006.201.20:44:11.18#ibcon#enter sib2, iclass 37, count 0 2006.201.20:44:11.18#ibcon#flushed, iclass 37, count 0 2006.201.20:44:11.18#ibcon#about to write, iclass 37, count 0 2006.201.20:44:11.18#ibcon#wrote, iclass 37, count 0 2006.201.20:44:11.18#ibcon#about to read 3, iclass 37, count 0 2006.201.20:44:11.20#ibcon#read 3, iclass 37, count 0 2006.201.20:44:11.20#ibcon#about to read 4, iclass 37, count 0 2006.201.20:44:11.20#ibcon#read 4, iclass 37, count 0 2006.201.20:44:11.20#ibcon#about to read 5, iclass 37, count 0 2006.201.20:44:11.20#ibcon#read 5, iclass 37, count 0 2006.201.20:44:11.20#ibcon#about to read 6, iclass 37, count 0 2006.201.20:44:11.20#ibcon#read 6, iclass 37, count 0 2006.201.20:44:11.20#ibcon#end of sib2, iclass 37, count 0 2006.201.20:44:11.20#ibcon#*mode == 0, iclass 37, count 0 2006.201.20:44:11.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.20:44:11.20#ibcon#[27=USB\r\n] 2006.201.20:44:11.20#ibcon#*before write, iclass 37, count 0 2006.201.20:44:11.20#ibcon#enter sib2, iclass 37, count 0 2006.201.20:44:11.20#ibcon#flushed, iclass 37, count 0 2006.201.20:44:11.20#ibcon#about to write, iclass 37, count 0 2006.201.20:44:11.20#ibcon#wrote, iclass 37, count 0 2006.201.20:44:11.20#ibcon#about to read 3, iclass 37, count 0 2006.201.20:44:11.23#ibcon#read 3, iclass 37, count 0 2006.201.20:44:11.23#ibcon#about to read 4, iclass 37, count 0 2006.201.20:44:11.23#ibcon#read 4, iclass 37, count 0 2006.201.20:44:11.23#ibcon#about to read 5, iclass 37, count 0 2006.201.20:44:11.23#ibcon#read 5, iclass 37, count 0 2006.201.20:44:11.23#ibcon#about to read 6, iclass 37, count 0 2006.201.20:44:11.23#ibcon#read 6, iclass 37, count 0 2006.201.20:44:11.23#ibcon#end of sib2, iclass 37, count 0 2006.201.20:44:11.23#ibcon#*after write, iclass 37, count 0 2006.201.20:44:11.23#ibcon#*before return 0, iclass 37, count 0 2006.201.20:44:11.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:11.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.20:44:11.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.20:44:11.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.20:44:11.23$vck44/vblo=6,719.99 2006.201.20:44:11.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.20:44:11.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.20:44:11.23#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:11.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:11.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:11.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:11.23#ibcon#enter wrdev, iclass 39, count 0 2006.201.20:44:11.23#ibcon#first serial, iclass 39, count 0 2006.201.20:44:11.23#ibcon#enter sib2, iclass 39, count 0 2006.201.20:44:11.23#ibcon#flushed, iclass 39, count 0 2006.201.20:44:11.23#ibcon#about to write, iclass 39, count 0 2006.201.20:44:11.23#ibcon#wrote, iclass 39, count 0 2006.201.20:44:11.23#ibcon#about to read 3, iclass 39, count 0 2006.201.20:44:11.25#ibcon#read 3, iclass 39, count 0 2006.201.20:44:11.25#ibcon#about to read 4, iclass 39, count 0 2006.201.20:44:11.25#ibcon#read 4, iclass 39, count 0 2006.201.20:44:11.25#ibcon#about to read 5, iclass 39, count 0 2006.201.20:44:11.25#ibcon#read 5, iclass 39, count 0 2006.201.20:44:11.25#ibcon#about to read 6, iclass 39, count 0 2006.201.20:44:11.25#ibcon#read 6, iclass 39, count 0 2006.201.20:44:11.25#ibcon#end of sib2, iclass 39, count 0 2006.201.20:44:11.25#ibcon#*mode == 0, iclass 39, count 0 2006.201.20:44:11.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.20:44:11.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:44:11.25#ibcon#*before write, iclass 39, count 0 2006.201.20:44:11.25#ibcon#enter sib2, iclass 39, count 0 2006.201.20:44:11.25#ibcon#flushed, iclass 39, count 0 2006.201.20:44:11.25#ibcon#about to write, iclass 39, count 0 2006.201.20:44:11.25#ibcon#wrote, iclass 39, count 0 2006.201.20:44:11.25#ibcon#about to read 3, iclass 39, count 0 2006.201.20:44:11.29#ibcon#read 3, iclass 39, count 0 2006.201.20:44:11.29#ibcon#about to read 4, iclass 39, count 0 2006.201.20:44:11.29#ibcon#read 4, iclass 39, count 0 2006.201.20:44:11.29#ibcon#about to read 5, iclass 39, count 0 2006.201.20:44:11.29#ibcon#read 5, iclass 39, count 0 2006.201.20:44:11.29#ibcon#about to read 6, iclass 39, count 0 2006.201.20:44:11.29#ibcon#read 6, iclass 39, count 0 2006.201.20:44:11.29#ibcon#end of sib2, iclass 39, count 0 2006.201.20:44:11.29#ibcon#*after write, iclass 39, count 0 2006.201.20:44:11.29#ibcon#*before return 0, iclass 39, count 0 2006.201.20:44:11.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:11.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.20:44:11.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.20:44:11.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.20:44:11.29$vck44/vb=6,4 2006.201.20:44:11.29#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.20:44:11.29#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.20:44:11.29#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:11.29#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:11.35#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:11.35#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:11.35#ibcon#enter wrdev, iclass 2, count 2 2006.201.20:44:11.35#ibcon#first serial, iclass 2, count 2 2006.201.20:44:11.35#ibcon#enter sib2, iclass 2, count 2 2006.201.20:44:11.35#ibcon#flushed, iclass 2, count 2 2006.201.20:44:11.35#ibcon#about to write, iclass 2, count 2 2006.201.20:44:11.35#ibcon#wrote, iclass 2, count 2 2006.201.20:44:11.35#ibcon#about to read 3, iclass 2, count 2 2006.201.20:44:11.37#ibcon#read 3, iclass 2, count 2 2006.201.20:44:11.37#ibcon#about to read 4, iclass 2, count 2 2006.201.20:44:11.37#ibcon#read 4, iclass 2, count 2 2006.201.20:44:11.37#ibcon#about to read 5, iclass 2, count 2 2006.201.20:44:11.37#ibcon#read 5, iclass 2, count 2 2006.201.20:44:11.37#ibcon#about to read 6, iclass 2, count 2 2006.201.20:44:11.37#ibcon#read 6, iclass 2, count 2 2006.201.20:44:11.37#ibcon#end of sib2, iclass 2, count 2 2006.201.20:44:11.37#ibcon#*mode == 0, iclass 2, count 2 2006.201.20:44:11.37#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.20:44:11.37#ibcon#[27=AT06-04\r\n] 2006.201.20:44:11.37#ibcon#*before write, iclass 2, count 2 2006.201.20:44:11.37#ibcon#enter sib2, iclass 2, count 2 2006.201.20:44:11.37#ibcon#flushed, iclass 2, count 2 2006.201.20:44:11.37#ibcon#about to write, iclass 2, count 2 2006.201.20:44:11.37#ibcon#wrote, iclass 2, count 2 2006.201.20:44:11.37#ibcon#about to read 3, iclass 2, count 2 2006.201.20:44:11.40#ibcon#read 3, iclass 2, count 2 2006.201.20:44:11.40#ibcon#about to read 4, iclass 2, count 2 2006.201.20:44:11.40#ibcon#read 4, iclass 2, count 2 2006.201.20:44:11.40#ibcon#about to read 5, iclass 2, count 2 2006.201.20:44:11.40#ibcon#read 5, iclass 2, count 2 2006.201.20:44:11.40#ibcon#about to read 6, iclass 2, count 2 2006.201.20:44:11.40#ibcon#read 6, iclass 2, count 2 2006.201.20:44:11.40#ibcon#end of sib2, iclass 2, count 2 2006.201.20:44:11.40#ibcon#*after write, iclass 2, count 2 2006.201.20:44:11.40#ibcon#*before return 0, iclass 2, count 2 2006.201.20:44:11.40#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:11.40#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.20:44:11.40#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.20:44:11.40#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:11.40#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:11.52#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:11.52#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:11.52#ibcon#enter wrdev, iclass 2, count 0 2006.201.20:44:11.52#ibcon#first serial, iclass 2, count 0 2006.201.20:44:11.52#ibcon#enter sib2, iclass 2, count 0 2006.201.20:44:11.52#ibcon#flushed, iclass 2, count 0 2006.201.20:44:11.52#ibcon#about to write, iclass 2, count 0 2006.201.20:44:11.52#ibcon#wrote, iclass 2, count 0 2006.201.20:44:11.52#ibcon#about to read 3, iclass 2, count 0 2006.201.20:44:11.54#ibcon#read 3, iclass 2, count 0 2006.201.20:44:11.54#ibcon#about to read 4, iclass 2, count 0 2006.201.20:44:11.54#ibcon#read 4, iclass 2, count 0 2006.201.20:44:11.54#ibcon#about to read 5, iclass 2, count 0 2006.201.20:44:11.54#ibcon#read 5, iclass 2, count 0 2006.201.20:44:11.54#ibcon#about to read 6, iclass 2, count 0 2006.201.20:44:11.54#ibcon#read 6, iclass 2, count 0 2006.201.20:44:11.54#ibcon#end of sib2, iclass 2, count 0 2006.201.20:44:11.54#ibcon#*mode == 0, iclass 2, count 0 2006.201.20:44:11.54#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.20:44:11.54#ibcon#[27=USB\r\n] 2006.201.20:44:11.54#ibcon#*before write, iclass 2, count 0 2006.201.20:44:11.54#ibcon#enter sib2, iclass 2, count 0 2006.201.20:44:11.54#ibcon#flushed, iclass 2, count 0 2006.201.20:44:11.54#ibcon#about to write, iclass 2, count 0 2006.201.20:44:11.54#ibcon#wrote, iclass 2, count 0 2006.201.20:44:11.54#ibcon#about to read 3, iclass 2, count 0 2006.201.20:44:11.57#ibcon#read 3, iclass 2, count 0 2006.201.20:44:11.57#ibcon#about to read 4, iclass 2, count 0 2006.201.20:44:11.57#ibcon#read 4, iclass 2, count 0 2006.201.20:44:11.57#ibcon#about to read 5, iclass 2, count 0 2006.201.20:44:11.57#ibcon#read 5, iclass 2, count 0 2006.201.20:44:11.57#ibcon#about to read 6, iclass 2, count 0 2006.201.20:44:11.57#ibcon#read 6, iclass 2, count 0 2006.201.20:44:11.57#ibcon#end of sib2, iclass 2, count 0 2006.201.20:44:11.57#ibcon#*after write, iclass 2, count 0 2006.201.20:44:11.57#ibcon#*before return 0, iclass 2, count 0 2006.201.20:44:11.57#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:11.57#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.20:44:11.57#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.20:44:11.57#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.20:44:11.57$vck44/vblo=7,734.99 2006.201.20:44:11.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.20:44:11.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.20:44:11.57#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:11.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:11.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:11.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:11.57#ibcon#enter wrdev, iclass 5, count 0 2006.201.20:44:11.57#ibcon#first serial, iclass 5, count 0 2006.201.20:44:11.57#ibcon#enter sib2, iclass 5, count 0 2006.201.20:44:11.57#ibcon#flushed, iclass 5, count 0 2006.201.20:44:11.57#ibcon#about to write, iclass 5, count 0 2006.201.20:44:11.57#ibcon#wrote, iclass 5, count 0 2006.201.20:44:11.57#ibcon#about to read 3, iclass 5, count 0 2006.201.20:44:11.59#ibcon#read 3, iclass 5, count 0 2006.201.20:44:11.59#ibcon#about to read 4, iclass 5, count 0 2006.201.20:44:11.59#ibcon#read 4, iclass 5, count 0 2006.201.20:44:11.59#ibcon#about to read 5, iclass 5, count 0 2006.201.20:44:11.59#ibcon#read 5, iclass 5, count 0 2006.201.20:44:11.59#ibcon#about to read 6, iclass 5, count 0 2006.201.20:44:11.59#ibcon#read 6, iclass 5, count 0 2006.201.20:44:11.59#ibcon#end of sib2, iclass 5, count 0 2006.201.20:44:11.59#ibcon#*mode == 0, iclass 5, count 0 2006.201.20:44:11.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.20:44:11.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:44:11.59#ibcon#*before write, iclass 5, count 0 2006.201.20:44:11.59#ibcon#enter sib2, iclass 5, count 0 2006.201.20:44:11.59#ibcon#flushed, iclass 5, count 0 2006.201.20:44:11.59#ibcon#about to write, iclass 5, count 0 2006.201.20:44:11.59#ibcon#wrote, iclass 5, count 0 2006.201.20:44:11.59#ibcon#about to read 3, iclass 5, count 0 2006.201.20:44:11.63#ibcon#read 3, iclass 5, count 0 2006.201.20:44:11.63#ibcon#about to read 4, iclass 5, count 0 2006.201.20:44:11.63#ibcon#read 4, iclass 5, count 0 2006.201.20:44:11.63#ibcon#about to read 5, iclass 5, count 0 2006.201.20:44:11.63#ibcon#read 5, iclass 5, count 0 2006.201.20:44:11.63#ibcon#about to read 6, iclass 5, count 0 2006.201.20:44:11.63#ibcon#read 6, iclass 5, count 0 2006.201.20:44:11.63#ibcon#end of sib2, iclass 5, count 0 2006.201.20:44:11.63#ibcon#*after write, iclass 5, count 0 2006.201.20:44:11.63#ibcon#*before return 0, iclass 5, count 0 2006.201.20:44:11.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:11.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.20:44:11.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.20:44:11.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.20:44:11.63$vck44/vb=7,4 2006.201.20:44:11.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.20:44:11.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.20:44:11.63#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:11.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:11.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:11.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:11.69#ibcon#enter wrdev, iclass 7, count 2 2006.201.20:44:11.69#ibcon#first serial, iclass 7, count 2 2006.201.20:44:11.69#ibcon#enter sib2, iclass 7, count 2 2006.201.20:44:11.69#ibcon#flushed, iclass 7, count 2 2006.201.20:44:11.69#ibcon#about to write, iclass 7, count 2 2006.201.20:44:11.69#ibcon#wrote, iclass 7, count 2 2006.201.20:44:11.69#ibcon#about to read 3, iclass 7, count 2 2006.201.20:44:11.71#ibcon#read 3, iclass 7, count 2 2006.201.20:44:11.71#ibcon#about to read 4, iclass 7, count 2 2006.201.20:44:11.71#ibcon#read 4, iclass 7, count 2 2006.201.20:44:11.71#ibcon#about to read 5, iclass 7, count 2 2006.201.20:44:11.71#ibcon#read 5, iclass 7, count 2 2006.201.20:44:11.71#ibcon#about to read 6, iclass 7, count 2 2006.201.20:44:11.71#ibcon#read 6, iclass 7, count 2 2006.201.20:44:11.71#ibcon#end of sib2, iclass 7, count 2 2006.201.20:44:11.71#ibcon#*mode == 0, iclass 7, count 2 2006.201.20:44:11.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.20:44:11.71#ibcon#[27=AT07-04\r\n] 2006.201.20:44:11.71#ibcon#*before write, iclass 7, count 2 2006.201.20:44:11.71#ibcon#enter sib2, iclass 7, count 2 2006.201.20:44:11.71#ibcon#flushed, iclass 7, count 2 2006.201.20:44:11.71#ibcon#about to write, iclass 7, count 2 2006.201.20:44:11.71#ibcon#wrote, iclass 7, count 2 2006.201.20:44:11.71#ibcon#about to read 3, iclass 7, count 2 2006.201.20:44:11.74#ibcon#read 3, iclass 7, count 2 2006.201.20:44:11.74#ibcon#about to read 4, iclass 7, count 2 2006.201.20:44:11.74#ibcon#read 4, iclass 7, count 2 2006.201.20:44:11.74#ibcon#about to read 5, iclass 7, count 2 2006.201.20:44:11.74#ibcon#read 5, iclass 7, count 2 2006.201.20:44:11.74#ibcon#about to read 6, iclass 7, count 2 2006.201.20:44:11.74#ibcon#read 6, iclass 7, count 2 2006.201.20:44:11.74#ibcon#end of sib2, iclass 7, count 2 2006.201.20:44:11.74#ibcon#*after write, iclass 7, count 2 2006.201.20:44:11.74#ibcon#*before return 0, iclass 7, count 2 2006.201.20:44:11.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:11.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.20:44:11.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.20:44:11.74#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:11.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:11.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:11.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:11.86#ibcon#enter wrdev, iclass 7, count 0 2006.201.20:44:11.86#ibcon#first serial, iclass 7, count 0 2006.201.20:44:11.86#ibcon#enter sib2, iclass 7, count 0 2006.201.20:44:11.86#ibcon#flushed, iclass 7, count 0 2006.201.20:44:11.86#ibcon#about to write, iclass 7, count 0 2006.201.20:44:11.86#ibcon#wrote, iclass 7, count 0 2006.201.20:44:11.86#ibcon#about to read 3, iclass 7, count 0 2006.201.20:44:11.88#ibcon#read 3, iclass 7, count 0 2006.201.20:44:11.88#ibcon#about to read 4, iclass 7, count 0 2006.201.20:44:11.88#ibcon#read 4, iclass 7, count 0 2006.201.20:44:11.88#ibcon#about to read 5, iclass 7, count 0 2006.201.20:44:11.88#ibcon#read 5, iclass 7, count 0 2006.201.20:44:11.88#ibcon#about to read 6, iclass 7, count 0 2006.201.20:44:11.88#ibcon#read 6, iclass 7, count 0 2006.201.20:44:11.88#ibcon#end of sib2, iclass 7, count 0 2006.201.20:44:11.88#ibcon#*mode == 0, iclass 7, count 0 2006.201.20:44:11.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.20:44:11.88#ibcon#[27=USB\r\n] 2006.201.20:44:11.88#ibcon#*before write, iclass 7, count 0 2006.201.20:44:11.88#ibcon#enter sib2, iclass 7, count 0 2006.201.20:44:11.88#ibcon#flushed, iclass 7, count 0 2006.201.20:44:11.88#ibcon#about to write, iclass 7, count 0 2006.201.20:44:11.88#ibcon#wrote, iclass 7, count 0 2006.201.20:44:11.88#ibcon#about to read 3, iclass 7, count 0 2006.201.20:44:11.91#ibcon#read 3, iclass 7, count 0 2006.201.20:44:11.91#ibcon#about to read 4, iclass 7, count 0 2006.201.20:44:11.91#ibcon#read 4, iclass 7, count 0 2006.201.20:44:11.91#ibcon#about to read 5, iclass 7, count 0 2006.201.20:44:11.91#ibcon#read 5, iclass 7, count 0 2006.201.20:44:11.91#ibcon#about to read 6, iclass 7, count 0 2006.201.20:44:11.91#ibcon#read 6, iclass 7, count 0 2006.201.20:44:11.91#ibcon#end of sib2, iclass 7, count 0 2006.201.20:44:11.91#ibcon#*after write, iclass 7, count 0 2006.201.20:44:11.91#ibcon#*before return 0, iclass 7, count 0 2006.201.20:44:11.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:11.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.20:44:11.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.20:44:11.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.20:44:11.91$vck44/vblo=8,744.99 2006.201.20:44:11.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.20:44:11.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.20:44:11.91#ibcon#ireg 17 cls_cnt 0 2006.201.20:44:11.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:11.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:11.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:11.91#ibcon#enter wrdev, iclass 11, count 0 2006.201.20:44:11.91#ibcon#first serial, iclass 11, count 0 2006.201.20:44:11.91#ibcon#enter sib2, iclass 11, count 0 2006.201.20:44:11.91#ibcon#flushed, iclass 11, count 0 2006.201.20:44:11.91#ibcon#about to write, iclass 11, count 0 2006.201.20:44:11.91#ibcon#wrote, iclass 11, count 0 2006.201.20:44:11.91#ibcon#about to read 3, iclass 11, count 0 2006.201.20:44:11.93#ibcon#read 3, iclass 11, count 0 2006.201.20:44:11.93#ibcon#about to read 4, iclass 11, count 0 2006.201.20:44:11.93#ibcon#read 4, iclass 11, count 0 2006.201.20:44:11.93#ibcon#about to read 5, iclass 11, count 0 2006.201.20:44:11.93#ibcon#read 5, iclass 11, count 0 2006.201.20:44:11.93#ibcon#about to read 6, iclass 11, count 0 2006.201.20:44:11.93#ibcon#read 6, iclass 11, count 0 2006.201.20:44:11.93#ibcon#end of sib2, iclass 11, count 0 2006.201.20:44:11.93#ibcon#*mode == 0, iclass 11, count 0 2006.201.20:44:11.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.20:44:11.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:44:11.93#ibcon#*before write, iclass 11, count 0 2006.201.20:44:11.93#ibcon#enter sib2, iclass 11, count 0 2006.201.20:44:11.93#ibcon#flushed, iclass 11, count 0 2006.201.20:44:11.93#ibcon#about to write, iclass 11, count 0 2006.201.20:44:11.93#ibcon#wrote, iclass 11, count 0 2006.201.20:44:11.93#ibcon#about to read 3, iclass 11, count 0 2006.201.20:44:11.97#ibcon#read 3, iclass 11, count 0 2006.201.20:44:11.97#ibcon#about to read 4, iclass 11, count 0 2006.201.20:44:11.97#ibcon#read 4, iclass 11, count 0 2006.201.20:44:11.97#ibcon#about to read 5, iclass 11, count 0 2006.201.20:44:11.97#ibcon#read 5, iclass 11, count 0 2006.201.20:44:11.97#ibcon#about to read 6, iclass 11, count 0 2006.201.20:44:11.97#ibcon#read 6, iclass 11, count 0 2006.201.20:44:11.97#ibcon#end of sib2, iclass 11, count 0 2006.201.20:44:11.97#ibcon#*after write, iclass 11, count 0 2006.201.20:44:11.97#ibcon#*before return 0, iclass 11, count 0 2006.201.20:44:11.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:11.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.20:44:11.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.20:44:11.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.20:44:11.97$vck44/vb=8,4 2006.201.20:44:11.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.20:44:11.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.20:44:11.97#ibcon#ireg 11 cls_cnt 2 2006.201.20:44:11.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:12.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:12.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:12.03#ibcon#enter wrdev, iclass 13, count 2 2006.201.20:44:12.03#ibcon#first serial, iclass 13, count 2 2006.201.20:44:12.03#ibcon#enter sib2, iclass 13, count 2 2006.201.20:44:12.03#ibcon#flushed, iclass 13, count 2 2006.201.20:44:12.03#ibcon#about to write, iclass 13, count 2 2006.201.20:44:12.03#ibcon#wrote, iclass 13, count 2 2006.201.20:44:12.03#ibcon#about to read 3, iclass 13, count 2 2006.201.20:44:12.05#ibcon#read 3, iclass 13, count 2 2006.201.20:44:12.05#ibcon#about to read 4, iclass 13, count 2 2006.201.20:44:12.05#ibcon#read 4, iclass 13, count 2 2006.201.20:44:12.05#ibcon#about to read 5, iclass 13, count 2 2006.201.20:44:12.05#ibcon#read 5, iclass 13, count 2 2006.201.20:44:12.05#ibcon#about to read 6, iclass 13, count 2 2006.201.20:44:12.05#ibcon#read 6, iclass 13, count 2 2006.201.20:44:12.05#ibcon#end of sib2, iclass 13, count 2 2006.201.20:44:12.05#ibcon#*mode == 0, iclass 13, count 2 2006.201.20:44:12.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.20:44:12.05#ibcon#[27=AT08-04\r\n] 2006.201.20:44:12.05#ibcon#*before write, iclass 13, count 2 2006.201.20:44:12.05#ibcon#enter sib2, iclass 13, count 2 2006.201.20:44:12.05#ibcon#flushed, iclass 13, count 2 2006.201.20:44:12.05#ibcon#about to write, iclass 13, count 2 2006.201.20:44:12.05#ibcon#wrote, iclass 13, count 2 2006.201.20:44:12.05#ibcon#about to read 3, iclass 13, count 2 2006.201.20:44:12.08#ibcon#read 3, iclass 13, count 2 2006.201.20:44:12.08#ibcon#about to read 4, iclass 13, count 2 2006.201.20:44:12.08#ibcon#read 4, iclass 13, count 2 2006.201.20:44:12.08#ibcon#about to read 5, iclass 13, count 2 2006.201.20:44:12.08#ibcon#read 5, iclass 13, count 2 2006.201.20:44:12.08#ibcon#about to read 6, iclass 13, count 2 2006.201.20:44:12.08#ibcon#read 6, iclass 13, count 2 2006.201.20:44:12.08#ibcon#end of sib2, iclass 13, count 2 2006.201.20:44:12.08#ibcon#*after write, iclass 13, count 2 2006.201.20:44:12.08#ibcon#*before return 0, iclass 13, count 2 2006.201.20:44:12.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:12.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.20:44:12.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.20:44:12.08#ibcon#ireg 7 cls_cnt 0 2006.201.20:44:12.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:12.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:12.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:12.20#ibcon#enter wrdev, iclass 13, count 0 2006.201.20:44:12.20#ibcon#first serial, iclass 13, count 0 2006.201.20:44:12.20#ibcon#enter sib2, iclass 13, count 0 2006.201.20:44:12.20#ibcon#flushed, iclass 13, count 0 2006.201.20:44:12.20#ibcon#about to write, iclass 13, count 0 2006.201.20:44:12.20#ibcon#wrote, iclass 13, count 0 2006.201.20:44:12.20#ibcon#about to read 3, iclass 13, count 0 2006.201.20:44:12.22#ibcon#read 3, iclass 13, count 0 2006.201.20:44:12.22#ibcon#about to read 4, iclass 13, count 0 2006.201.20:44:12.22#ibcon#read 4, iclass 13, count 0 2006.201.20:44:12.22#ibcon#about to read 5, iclass 13, count 0 2006.201.20:44:12.22#ibcon#read 5, iclass 13, count 0 2006.201.20:44:12.22#ibcon#about to read 6, iclass 13, count 0 2006.201.20:44:12.22#ibcon#read 6, iclass 13, count 0 2006.201.20:44:12.22#ibcon#end of sib2, iclass 13, count 0 2006.201.20:44:12.22#ibcon#*mode == 0, iclass 13, count 0 2006.201.20:44:12.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.20:44:12.22#ibcon#[27=USB\r\n] 2006.201.20:44:12.22#ibcon#*before write, iclass 13, count 0 2006.201.20:44:12.22#ibcon#enter sib2, iclass 13, count 0 2006.201.20:44:12.22#ibcon#flushed, iclass 13, count 0 2006.201.20:44:12.22#ibcon#about to write, iclass 13, count 0 2006.201.20:44:12.22#ibcon#wrote, iclass 13, count 0 2006.201.20:44:12.22#ibcon#about to read 3, iclass 13, count 0 2006.201.20:44:12.25#ibcon#read 3, iclass 13, count 0 2006.201.20:44:12.25#ibcon#about to read 4, iclass 13, count 0 2006.201.20:44:12.25#ibcon#read 4, iclass 13, count 0 2006.201.20:44:12.25#ibcon#about to read 5, iclass 13, count 0 2006.201.20:44:12.25#ibcon#read 5, iclass 13, count 0 2006.201.20:44:12.25#ibcon#about to read 6, iclass 13, count 0 2006.201.20:44:12.25#ibcon#read 6, iclass 13, count 0 2006.201.20:44:12.25#ibcon#end of sib2, iclass 13, count 0 2006.201.20:44:12.25#ibcon#*after write, iclass 13, count 0 2006.201.20:44:12.25#ibcon#*before return 0, iclass 13, count 0 2006.201.20:44:12.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:12.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.20:44:12.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.20:44:12.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.20:44:12.25$vck44/vabw=wide 2006.201.20:44:12.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.20:44:12.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.20:44:12.25#ibcon#ireg 8 cls_cnt 0 2006.201.20:44:12.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:12.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:12.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:12.25#ibcon#enter wrdev, iclass 15, count 0 2006.201.20:44:12.25#ibcon#first serial, iclass 15, count 0 2006.201.20:44:12.25#ibcon#enter sib2, iclass 15, count 0 2006.201.20:44:12.25#ibcon#flushed, iclass 15, count 0 2006.201.20:44:12.25#ibcon#about to write, iclass 15, count 0 2006.201.20:44:12.25#ibcon#wrote, iclass 15, count 0 2006.201.20:44:12.25#ibcon#about to read 3, iclass 15, count 0 2006.201.20:44:12.27#ibcon#read 3, iclass 15, count 0 2006.201.20:44:12.27#ibcon#about to read 4, iclass 15, count 0 2006.201.20:44:12.27#ibcon#read 4, iclass 15, count 0 2006.201.20:44:12.27#ibcon#about to read 5, iclass 15, count 0 2006.201.20:44:12.27#ibcon#read 5, iclass 15, count 0 2006.201.20:44:12.27#ibcon#about to read 6, iclass 15, count 0 2006.201.20:44:12.27#ibcon#read 6, iclass 15, count 0 2006.201.20:44:12.27#ibcon#end of sib2, iclass 15, count 0 2006.201.20:44:12.27#ibcon#*mode == 0, iclass 15, count 0 2006.201.20:44:12.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.20:44:12.27#ibcon#[25=BW32\r\n] 2006.201.20:44:12.27#ibcon#*before write, iclass 15, count 0 2006.201.20:44:12.27#ibcon#enter sib2, iclass 15, count 0 2006.201.20:44:12.27#ibcon#flushed, iclass 15, count 0 2006.201.20:44:12.27#ibcon#about to write, iclass 15, count 0 2006.201.20:44:12.27#ibcon#wrote, iclass 15, count 0 2006.201.20:44:12.27#ibcon#about to read 3, iclass 15, count 0 2006.201.20:44:12.30#ibcon#read 3, iclass 15, count 0 2006.201.20:44:12.30#ibcon#about to read 4, iclass 15, count 0 2006.201.20:44:12.30#ibcon#read 4, iclass 15, count 0 2006.201.20:44:12.30#ibcon#about to read 5, iclass 15, count 0 2006.201.20:44:12.30#ibcon#read 5, iclass 15, count 0 2006.201.20:44:12.30#ibcon#about to read 6, iclass 15, count 0 2006.201.20:44:12.30#ibcon#read 6, iclass 15, count 0 2006.201.20:44:12.30#ibcon#end of sib2, iclass 15, count 0 2006.201.20:44:12.30#ibcon#*after write, iclass 15, count 0 2006.201.20:44:12.30#ibcon#*before return 0, iclass 15, count 0 2006.201.20:44:12.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:12.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.20:44:12.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.20:44:12.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.20:44:12.30$vck44/vbbw=wide 2006.201.20:44:12.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.20:44:12.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.20:44:12.30#ibcon#ireg 8 cls_cnt 0 2006.201.20:44:12.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:44:12.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:44:12.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:44:12.37#ibcon#enter wrdev, iclass 17, count 0 2006.201.20:44:12.37#ibcon#first serial, iclass 17, count 0 2006.201.20:44:12.37#ibcon#enter sib2, iclass 17, count 0 2006.201.20:44:12.37#ibcon#flushed, iclass 17, count 0 2006.201.20:44:12.37#ibcon#about to write, iclass 17, count 0 2006.201.20:44:12.37#ibcon#wrote, iclass 17, count 0 2006.201.20:44:12.37#ibcon#about to read 3, iclass 17, count 0 2006.201.20:44:12.39#ibcon#read 3, iclass 17, count 0 2006.201.20:44:12.39#ibcon#about to read 4, iclass 17, count 0 2006.201.20:44:12.39#ibcon#read 4, iclass 17, count 0 2006.201.20:44:12.39#ibcon#about to read 5, iclass 17, count 0 2006.201.20:44:12.39#ibcon#read 5, iclass 17, count 0 2006.201.20:44:12.39#ibcon#about to read 6, iclass 17, count 0 2006.201.20:44:12.39#ibcon#read 6, iclass 17, count 0 2006.201.20:44:12.39#ibcon#end of sib2, iclass 17, count 0 2006.201.20:44:12.39#ibcon#*mode == 0, iclass 17, count 0 2006.201.20:44:12.39#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.20:44:12.39#ibcon#[27=BW32\r\n] 2006.201.20:44:12.39#ibcon#*before write, iclass 17, count 0 2006.201.20:44:12.39#ibcon#enter sib2, iclass 17, count 0 2006.201.20:44:12.39#ibcon#flushed, iclass 17, count 0 2006.201.20:44:12.39#ibcon#about to write, iclass 17, count 0 2006.201.20:44:12.39#ibcon#wrote, iclass 17, count 0 2006.201.20:44:12.39#ibcon#about to read 3, iclass 17, count 0 2006.201.20:44:12.42#ibcon#read 3, iclass 17, count 0 2006.201.20:44:12.42#ibcon#about to read 4, iclass 17, count 0 2006.201.20:44:12.42#ibcon#read 4, iclass 17, count 0 2006.201.20:44:12.42#ibcon#about to read 5, iclass 17, count 0 2006.201.20:44:12.42#ibcon#read 5, iclass 17, count 0 2006.201.20:44:12.42#ibcon#about to read 6, iclass 17, count 0 2006.201.20:44:12.42#ibcon#read 6, iclass 17, count 0 2006.201.20:44:12.42#ibcon#end of sib2, iclass 17, count 0 2006.201.20:44:12.42#ibcon#*after write, iclass 17, count 0 2006.201.20:44:12.42#ibcon#*before return 0, iclass 17, count 0 2006.201.20:44:12.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:44:12.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.20:44:12.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.20:44:12.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.20:44:12.42$setupk4/ifdk4 2006.201.20:44:12.42$ifdk4/lo= 2006.201.20:44:12.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:44:12.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:44:12.42$ifdk4/patch= 2006.201.20:44:12.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:44:12.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:44:12.42$setupk4/!*+20s 2006.201.20:44:14.19#abcon#<5=/05 0.8 1.5 20.111001002.4\r\n> 2006.201.20:44:14.21#abcon#{5=INTERFACE CLEAR} 2006.201.20:44:14.27#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:44:23.13#trakl#Source acquired 2006.201.20:44:24.14#flagr#flagr/antenna,acquired 2006.201.20:44:24.36#abcon#<5=/05 0.8 1.5 20.111001002.4\r\n> 2006.201.20:44:24.38#abcon#{5=INTERFACE CLEAR} 2006.201.20:44:24.44#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:44:26.88$setupk4/"tpicd 2006.201.20:44:26.88$setupk4/echo=off 2006.201.20:44:26.88$setupk4/xlog=off 2006.201.20:44:26.88:!2006.201.20:46:54 2006.201.20:46:54.00:preob 2006.201.20:46:55.14/onsource/TRACKING 2006.201.20:46:55.14:!2006.201.20:47:04 2006.201.20:47:04.00:"tape 2006.201.20:47:04.00:"st=record 2006.201.20:47:04.00:data_valid=on 2006.201.20:47:04.00:midob 2006.201.20:47:04.14/onsource/TRACKING 2006.201.20:47:04.14/wx/20.13,1002.5,100 2006.201.20:47:04.30/cable/+6.4810E-03 2006.201.20:47:05.39/va/01,08,usb,yes,55,59 2006.201.20:47:05.39/va/02,07,usb,yes,59,60 2006.201.20:47:05.39/va/03,08,usb,yes,54,56 2006.201.20:47:05.39/va/04,07,usb,yes,61,64 2006.201.20:47:05.39/va/05,04,usb,yes,54,56 2006.201.20:47:05.39/va/06,05,usb,yes,55,55 2006.201.20:47:05.39/va/07,05,usb,yes,54,55 2006.201.20:47:05.39/va/08,04,usb,yes,53,62 2006.201.20:47:05.62/valo/01,524.99,yes,locked 2006.201.20:47:05.62/valo/02,534.99,yes,locked 2006.201.20:47:05.62/valo/03,564.99,yes,locked 2006.201.20:47:05.62/valo/04,624.99,yes,locked 2006.201.20:47:05.62/valo/05,734.99,yes,locked 2006.201.20:47:05.62/valo/06,814.99,yes,locked 2006.201.20:47:05.62/valo/07,864.99,yes,locked 2006.201.20:47:05.62/valo/08,884.99,yes,locked 2006.201.20:47:06.71/vb/01,04,usb,yes,32,30 2006.201.20:47:06.71/vb/02,05,usb,yes,30,30 2006.201.20:47:06.71/vb/03,04,usb,yes,32,35 2006.201.20:47:06.71/vb/04,05,usb,yes,32,31 2006.201.20:47:06.71/vb/05,04,usb,yes,28,31 2006.201.20:47:06.71/vb/06,04,usb,yes,33,29 2006.201.20:47:06.71/vb/07,04,usb,yes,33,33 2006.201.20:47:06.71/vb/08,04,usb,yes,30,34 2006.201.20:47:06.94/vblo/01,629.99,yes,locked 2006.201.20:47:06.94/vblo/02,634.99,yes,locked 2006.201.20:47:06.94/vblo/03,649.99,yes,locked 2006.201.20:47:06.94/vblo/04,679.99,yes,locked 2006.201.20:47:06.94/vblo/05,709.99,yes,locked 2006.201.20:47:06.94/vblo/06,719.99,yes,locked 2006.201.20:47:06.94/vblo/07,734.99,yes,locked 2006.201.20:47:06.94/vblo/08,744.99,yes,locked 2006.201.20:47:07.09/vabw/8 2006.201.20:47:07.24/vbbw/8 2006.201.20:47:07.33/xfe/off,on,16.0 2006.201.20:47:07.75/ifatt/23,28,28,28 2006.201.20:47:08.06/fmout-gps/S +4.56E-07 2006.201.20:47:08.10:!2006.201.20:47:54 2006.201.20:47:54.00:data_valid=off 2006.201.20:47:54.00:"et 2006.201.20:47:54.00:!+3s 2006.201.20:47:57.02:"tape 2006.201.20:47:57.02:postob 2006.201.20:47:57.18/cable/+6.4800E-03 2006.201.20:47:57.18/wx/20.13,1002.4,100 2006.201.20:47:57.26/fmout-gps/S +4.55E-07 2006.201.20:47:57.26:scan_name=201-2050,jd0607,310 2006.201.20:47:57.26:source=nrao150,035929.75,505750.2,2000.0,ccw 2006.201.20:47:58.14#flagr#flagr/antenna,new-source 2006.201.20:47:58.14:checkk5 2006.201.20:47:58.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:47:58.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:47:59.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:47:59.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:48:00.01/chk_obsdata//k5ts1/T2012047??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.20:48:00.37/chk_obsdata//k5ts2/T2012047??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.20:48:00.75/chk_obsdata//k5ts3/T2012047??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.20:48:01.11/chk_obsdata//k5ts4/T2012047??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.20:48:01.80/k5log//k5ts1_log_newline 2006.201.20:48:02.49/k5log//k5ts2_log_newline 2006.201.20:48:03.18/k5log//k5ts3_log_newline 2006.201.20:48:03.87/k5log//k5ts4_log_newline 2006.201.20:48:03.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:48:03.90:setupk4=1 2006.201.20:48:03.90$setupk4/echo=on 2006.201.20:48:03.90$setupk4/pcalon 2006.201.20:48:03.90$pcalon/"no phase cal control is implemented here 2006.201.20:48:03.90$setupk4/"tpicd=stop 2006.201.20:48:03.90$setupk4/"rec=synch_on 2006.201.20:48:03.90$setupk4/"rec_mode=128 2006.201.20:48:03.90$setupk4/!* 2006.201.20:48:03.90$setupk4/recpk4 2006.201.20:48:03.90$recpk4/recpatch= 2006.201.20:48:03.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:48:03.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:48:03.90$setupk4/vck44 2006.201.20:48:03.90$vck44/valo=1,524.99 2006.201.20:48:03.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.20:48:03.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.20:48:03.90#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:03.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:03.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:03.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:03.90#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:48:03.90#ibcon#first serial, iclass 4, count 0 2006.201.20:48:03.90#ibcon#enter sib2, iclass 4, count 0 2006.201.20:48:03.90#ibcon#flushed, iclass 4, count 0 2006.201.20:48:03.90#ibcon#about to write, iclass 4, count 0 2006.201.20:48:03.90#ibcon#wrote, iclass 4, count 0 2006.201.20:48:03.90#ibcon#about to read 3, iclass 4, count 0 2006.201.20:48:03.94#ibcon#read 3, iclass 4, count 0 2006.201.20:48:03.94#ibcon#about to read 4, iclass 4, count 0 2006.201.20:48:03.94#ibcon#read 4, iclass 4, count 0 2006.201.20:48:03.94#ibcon#about to read 5, iclass 4, count 0 2006.201.20:48:03.94#ibcon#read 5, iclass 4, count 0 2006.201.20:48:03.94#ibcon#about to read 6, iclass 4, count 0 2006.201.20:48:03.94#ibcon#read 6, iclass 4, count 0 2006.201.20:48:03.94#ibcon#end of sib2, iclass 4, count 0 2006.201.20:48:03.94#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:48:03.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:48:03.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:48:03.94#ibcon#*before write, iclass 4, count 0 2006.201.20:48:03.94#ibcon#enter sib2, iclass 4, count 0 2006.201.20:48:03.94#ibcon#flushed, iclass 4, count 0 2006.201.20:48:03.94#ibcon#about to write, iclass 4, count 0 2006.201.20:48:03.94#ibcon#wrote, iclass 4, count 0 2006.201.20:48:03.94#ibcon#about to read 3, iclass 4, count 0 2006.201.20:48:03.99#ibcon#read 3, iclass 4, count 0 2006.201.20:48:03.99#ibcon#about to read 4, iclass 4, count 0 2006.201.20:48:03.99#ibcon#read 4, iclass 4, count 0 2006.201.20:48:03.99#ibcon#about to read 5, iclass 4, count 0 2006.201.20:48:03.99#ibcon#read 5, iclass 4, count 0 2006.201.20:48:03.99#ibcon#about to read 6, iclass 4, count 0 2006.201.20:48:03.99#ibcon#read 6, iclass 4, count 0 2006.201.20:48:03.99#ibcon#end of sib2, iclass 4, count 0 2006.201.20:48:03.99#ibcon#*after write, iclass 4, count 0 2006.201.20:48:03.99#ibcon#*before return 0, iclass 4, count 0 2006.201.20:48:03.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:03.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:03.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:48:03.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:48:03.99$vck44/va=1,8 2006.201.20:48:03.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.20:48:03.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.20:48:03.99#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:03.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:03.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:03.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:03.99#ibcon#enter wrdev, iclass 6, count 2 2006.201.20:48:03.99#ibcon#first serial, iclass 6, count 2 2006.201.20:48:03.99#ibcon#enter sib2, iclass 6, count 2 2006.201.20:48:03.99#ibcon#flushed, iclass 6, count 2 2006.201.20:48:03.99#ibcon#about to write, iclass 6, count 2 2006.201.20:48:03.99#ibcon#wrote, iclass 6, count 2 2006.201.20:48:03.99#ibcon#about to read 3, iclass 6, count 2 2006.201.20:48:04.01#ibcon#read 3, iclass 6, count 2 2006.201.20:48:04.01#ibcon#about to read 4, iclass 6, count 2 2006.201.20:48:04.01#ibcon#read 4, iclass 6, count 2 2006.201.20:48:04.01#ibcon#about to read 5, iclass 6, count 2 2006.201.20:48:04.01#ibcon#read 5, iclass 6, count 2 2006.201.20:48:04.01#ibcon#about to read 6, iclass 6, count 2 2006.201.20:48:04.01#ibcon#read 6, iclass 6, count 2 2006.201.20:48:04.01#ibcon#end of sib2, iclass 6, count 2 2006.201.20:48:04.01#ibcon#*mode == 0, iclass 6, count 2 2006.201.20:48:04.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.20:48:04.01#ibcon#[25=AT01-08\r\n] 2006.201.20:48:04.01#ibcon#*before write, iclass 6, count 2 2006.201.20:48:04.01#ibcon#enter sib2, iclass 6, count 2 2006.201.20:48:04.01#ibcon#flushed, iclass 6, count 2 2006.201.20:48:04.01#ibcon#about to write, iclass 6, count 2 2006.201.20:48:04.01#ibcon#wrote, iclass 6, count 2 2006.201.20:48:04.01#ibcon#about to read 3, iclass 6, count 2 2006.201.20:48:04.04#ibcon#read 3, iclass 6, count 2 2006.201.20:48:04.04#ibcon#about to read 4, iclass 6, count 2 2006.201.20:48:04.04#ibcon#read 4, iclass 6, count 2 2006.201.20:48:04.04#ibcon#about to read 5, iclass 6, count 2 2006.201.20:48:04.04#ibcon#read 5, iclass 6, count 2 2006.201.20:48:04.04#ibcon#about to read 6, iclass 6, count 2 2006.201.20:48:04.04#ibcon#read 6, iclass 6, count 2 2006.201.20:48:04.04#ibcon#end of sib2, iclass 6, count 2 2006.201.20:48:04.04#ibcon#*after write, iclass 6, count 2 2006.201.20:48:04.04#ibcon#*before return 0, iclass 6, count 2 2006.201.20:48:04.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:04.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:04.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.20:48:04.04#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:04.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:04.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:04.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:04.16#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:48:04.16#ibcon#first serial, iclass 6, count 0 2006.201.20:48:04.16#ibcon#enter sib2, iclass 6, count 0 2006.201.20:48:04.16#ibcon#flushed, iclass 6, count 0 2006.201.20:48:04.16#ibcon#about to write, iclass 6, count 0 2006.201.20:48:04.16#ibcon#wrote, iclass 6, count 0 2006.201.20:48:04.16#ibcon#about to read 3, iclass 6, count 0 2006.201.20:48:04.18#ibcon#read 3, iclass 6, count 0 2006.201.20:48:04.18#ibcon#about to read 4, iclass 6, count 0 2006.201.20:48:04.18#ibcon#read 4, iclass 6, count 0 2006.201.20:48:04.18#ibcon#about to read 5, iclass 6, count 0 2006.201.20:48:04.18#ibcon#read 5, iclass 6, count 0 2006.201.20:48:04.18#ibcon#about to read 6, iclass 6, count 0 2006.201.20:48:04.18#ibcon#read 6, iclass 6, count 0 2006.201.20:48:04.18#ibcon#end of sib2, iclass 6, count 0 2006.201.20:48:04.18#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:48:04.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:48:04.18#ibcon#[25=USB\r\n] 2006.201.20:48:04.18#ibcon#*before write, iclass 6, count 0 2006.201.20:48:04.18#ibcon#enter sib2, iclass 6, count 0 2006.201.20:48:04.18#ibcon#flushed, iclass 6, count 0 2006.201.20:48:04.18#ibcon#about to write, iclass 6, count 0 2006.201.20:48:04.18#ibcon#wrote, iclass 6, count 0 2006.201.20:48:04.18#ibcon#about to read 3, iclass 6, count 0 2006.201.20:48:04.21#ibcon#read 3, iclass 6, count 0 2006.201.20:48:04.21#ibcon#about to read 4, iclass 6, count 0 2006.201.20:48:04.21#ibcon#read 4, iclass 6, count 0 2006.201.20:48:04.21#ibcon#about to read 5, iclass 6, count 0 2006.201.20:48:04.21#ibcon#read 5, iclass 6, count 0 2006.201.20:48:04.21#ibcon#about to read 6, iclass 6, count 0 2006.201.20:48:04.21#ibcon#read 6, iclass 6, count 0 2006.201.20:48:04.21#ibcon#end of sib2, iclass 6, count 0 2006.201.20:48:04.21#ibcon#*after write, iclass 6, count 0 2006.201.20:48:04.21#ibcon#*before return 0, iclass 6, count 0 2006.201.20:48:04.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:04.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:04.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:48:04.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:48:04.21$vck44/valo=2,534.99 2006.201.20:48:04.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.20:48:04.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.20:48:04.21#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:04.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:04.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:04.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:04.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:48:04.21#ibcon#first serial, iclass 10, count 0 2006.201.20:48:04.21#ibcon#enter sib2, iclass 10, count 0 2006.201.20:48:04.21#ibcon#flushed, iclass 10, count 0 2006.201.20:48:04.21#ibcon#about to write, iclass 10, count 0 2006.201.20:48:04.21#ibcon#wrote, iclass 10, count 0 2006.201.20:48:04.21#ibcon#about to read 3, iclass 10, count 0 2006.201.20:48:04.23#ibcon#read 3, iclass 10, count 0 2006.201.20:48:04.23#ibcon#about to read 4, iclass 10, count 0 2006.201.20:48:04.23#ibcon#read 4, iclass 10, count 0 2006.201.20:48:04.23#ibcon#about to read 5, iclass 10, count 0 2006.201.20:48:04.23#ibcon#read 5, iclass 10, count 0 2006.201.20:48:04.23#ibcon#about to read 6, iclass 10, count 0 2006.201.20:48:04.23#ibcon#read 6, iclass 10, count 0 2006.201.20:48:04.23#ibcon#end of sib2, iclass 10, count 0 2006.201.20:48:04.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:48:04.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:48:04.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:48:04.23#ibcon#*before write, iclass 10, count 0 2006.201.20:48:04.23#ibcon#enter sib2, iclass 10, count 0 2006.201.20:48:04.23#ibcon#flushed, iclass 10, count 0 2006.201.20:48:04.23#ibcon#about to write, iclass 10, count 0 2006.201.20:48:04.23#ibcon#wrote, iclass 10, count 0 2006.201.20:48:04.23#ibcon#about to read 3, iclass 10, count 0 2006.201.20:48:04.27#ibcon#read 3, iclass 10, count 0 2006.201.20:48:04.27#ibcon#about to read 4, iclass 10, count 0 2006.201.20:48:04.27#ibcon#read 4, iclass 10, count 0 2006.201.20:48:04.27#ibcon#about to read 5, iclass 10, count 0 2006.201.20:48:04.27#ibcon#read 5, iclass 10, count 0 2006.201.20:48:04.27#ibcon#about to read 6, iclass 10, count 0 2006.201.20:48:04.27#ibcon#read 6, iclass 10, count 0 2006.201.20:48:04.27#ibcon#end of sib2, iclass 10, count 0 2006.201.20:48:04.27#ibcon#*after write, iclass 10, count 0 2006.201.20:48:04.27#ibcon#*before return 0, iclass 10, count 0 2006.201.20:48:04.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:04.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:04.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:48:04.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:48:04.27$vck44/va=2,7 2006.201.20:48:04.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.20:48:04.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.20:48:04.27#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:04.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:04.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:04.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:04.33#ibcon#enter wrdev, iclass 12, count 2 2006.201.20:48:04.33#ibcon#first serial, iclass 12, count 2 2006.201.20:48:04.33#ibcon#enter sib2, iclass 12, count 2 2006.201.20:48:04.33#ibcon#flushed, iclass 12, count 2 2006.201.20:48:04.33#ibcon#about to write, iclass 12, count 2 2006.201.20:48:04.33#ibcon#wrote, iclass 12, count 2 2006.201.20:48:04.33#ibcon#about to read 3, iclass 12, count 2 2006.201.20:48:04.35#ibcon#read 3, iclass 12, count 2 2006.201.20:48:04.35#ibcon#about to read 4, iclass 12, count 2 2006.201.20:48:04.35#ibcon#read 4, iclass 12, count 2 2006.201.20:48:04.35#ibcon#about to read 5, iclass 12, count 2 2006.201.20:48:04.35#ibcon#read 5, iclass 12, count 2 2006.201.20:48:04.35#ibcon#about to read 6, iclass 12, count 2 2006.201.20:48:04.35#ibcon#read 6, iclass 12, count 2 2006.201.20:48:04.35#ibcon#end of sib2, iclass 12, count 2 2006.201.20:48:04.35#ibcon#*mode == 0, iclass 12, count 2 2006.201.20:48:04.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.20:48:04.35#ibcon#[25=AT02-07\r\n] 2006.201.20:48:04.35#ibcon#*before write, iclass 12, count 2 2006.201.20:48:04.35#ibcon#enter sib2, iclass 12, count 2 2006.201.20:48:04.35#ibcon#flushed, iclass 12, count 2 2006.201.20:48:04.35#ibcon#about to write, iclass 12, count 2 2006.201.20:48:04.35#ibcon#wrote, iclass 12, count 2 2006.201.20:48:04.35#ibcon#about to read 3, iclass 12, count 2 2006.201.20:48:04.38#ibcon#read 3, iclass 12, count 2 2006.201.20:48:04.38#ibcon#about to read 4, iclass 12, count 2 2006.201.20:48:04.38#ibcon#read 4, iclass 12, count 2 2006.201.20:48:04.38#ibcon#about to read 5, iclass 12, count 2 2006.201.20:48:04.38#ibcon#read 5, iclass 12, count 2 2006.201.20:48:04.38#ibcon#about to read 6, iclass 12, count 2 2006.201.20:48:04.38#ibcon#read 6, iclass 12, count 2 2006.201.20:48:04.38#ibcon#end of sib2, iclass 12, count 2 2006.201.20:48:04.38#ibcon#*after write, iclass 12, count 2 2006.201.20:48:04.38#ibcon#*before return 0, iclass 12, count 2 2006.201.20:48:04.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:04.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:04.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.20:48:04.38#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:04.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:04.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:04.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:04.50#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:48:04.50#ibcon#first serial, iclass 12, count 0 2006.201.20:48:04.50#ibcon#enter sib2, iclass 12, count 0 2006.201.20:48:04.50#ibcon#flushed, iclass 12, count 0 2006.201.20:48:04.50#ibcon#about to write, iclass 12, count 0 2006.201.20:48:04.50#ibcon#wrote, iclass 12, count 0 2006.201.20:48:04.50#ibcon#about to read 3, iclass 12, count 0 2006.201.20:48:04.52#ibcon#read 3, iclass 12, count 0 2006.201.20:48:04.52#ibcon#about to read 4, iclass 12, count 0 2006.201.20:48:04.52#ibcon#read 4, iclass 12, count 0 2006.201.20:48:04.52#ibcon#about to read 5, iclass 12, count 0 2006.201.20:48:04.52#ibcon#read 5, iclass 12, count 0 2006.201.20:48:04.52#ibcon#about to read 6, iclass 12, count 0 2006.201.20:48:04.52#ibcon#read 6, iclass 12, count 0 2006.201.20:48:04.52#ibcon#end of sib2, iclass 12, count 0 2006.201.20:48:04.52#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:48:04.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:48:04.52#ibcon#[25=USB\r\n] 2006.201.20:48:04.52#ibcon#*before write, iclass 12, count 0 2006.201.20:48:04.52#ibcon#enter sib2, iclass 12, count 0 2006.201.20:48:04.52#ibcon#flushed, iclass 12, count 0 2006.201.20:48:04.52#ibcon#about to write, iclass 12, count 0 2006.201.20:48:04.52#ibcon#wrote, iclass 12, count 0 2006.201.20:48:04.52#ibcon#about to read 3, iclass 12, count 0 2006.201.20:48:04.55#ibcon#read 3, iclass 12, count 0 2006.201.20:48:04.55#ibcon#about to read 4, iclass 12, count 0 2006.201.20:48:04.55#ibcon#read 4, iclass 12, count 0 2006.201.20:48:04.55#ibcon#about to read 5, iclass 12, count 0 2006.201.20:48:04.55#ibcon#read 5, iclass 12, count 0 2006.201.20:48:04.55#ibcon#about to read 6, iclass 12, count 0 2006.201.20:48:04.55#ibcon#read 6, iclass 12, count 0 2006.201.20:48:04.55#ibcon#end of sib2, iclass 12, count 0 2006.201.20:48:04.55#ibcon#*after write, iclass 12, count 0 2006.201.20:48:04.55#ibcon#*before return 0, iclass 12, count 0 2006.201.20:48:04.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:04.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:04.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:48:04.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:48:04.55$vck44/valo=3,564.99 2006.201.20:48:04.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.20:48:04.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.20:48:04.55#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:04.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:04.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:04.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:04.55#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:48:04.55#ibcon#first serial, iclass 14, count 0 2006.201.20:48:04.55#ibcon#enter sib2, iclass 14, count 0 2006.201.20:48:04.55#ibcon#flushed, iclass 14, count 0 2006.201.20:48:04.55#ibcon#about to write, iclass 14, count 0 2006.201.20:48:04.55#ibcon#wrote, iclass 14, count 0 2006.201.20:48:04.55#ibcon#about to read 3, iclass 14, count 0 2006.201.20:48:04.57#ibcon#read 3, iclass 14, count 0 2006.201.20:48:04.57#ibcon#about to read 4, iclass 14, count 0 2006.201.20:48:04.57#ibcon#read 4, iclass 14, count 0 2006.201.20:48:04.57#ibcon#about to read 5, iclass 14, count 0 2006.201.20:48:04.57#ibcon#read 5, iclass 14, count 0 2006.201.20:48:04.57#ibcon#about to read 6, iclass 14, count 0 2006.201.20:48:04.57#ibcon#read 6, iclass 14, count 0 2006.201.20:48:04.57#ibcon#end of sib2, iclass 14, count 0 2006.201.20:48:04.57#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:48:04.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:48:04.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:48:04.57#ibcon#*before write, iclass 14, count 0 2006.201.20:48:04.57#ibcon#enter sib2, iclass 14, count 0 2006.201.20:48:04.57#ibcon#flushed, iclass 14, count 0 2006.201.20:48:04.57#ibcon#about to write, iclass 14, count 0 2006.201.20:48:04.57#ibcon#wrote, iclass 14, count 0 2006.201.20:48:04.57#ibcon#about to read 3, iclass 14, count 0 2006.201.20:48:04.62#ibcon#read 3, iclass 14, count 0 2006.201.20:48:04.62#ibcon#about to read 4, iclass 14, count 0 2006.201.20:48:04.62#ibcon#read 4, iclass 14, count 0 2006.201.20:48:04.62#ibcon#about to read 5, iclass 14, count 0 2006.201.20:48:04.62#ibcon#read 5, iclass 14, count 0 2006.201.20:48:04.62#ibcon#about to read 6, iclass 14, count 0 2006.201.20:48:04.62#ibcon#read 6, iclass 14, count 0 2006.201.20:48:04.62#ibcon#end of sib2, iclass 14, count 0 2006.201.20:48:04.62#ibcon#*after write, iclass 14, count 0 2006.201.20:48:04.62#ibcon#*before return 0, iclass 14, count 0 2006.201.20:48:04.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:04.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:04.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:48:04.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:48:04.62$vck44/va=3,8 2006.201.20:48:04.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.20:48:04.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.20:48:04.62#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:04.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:04.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:04.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:04.67#ibcon#enter wrdev, iclass 16, count 2 2006.201.20:48:04.67#ibcon#first serial, iclass 16, count 2 2006.201.20:48:04.67#ibcon#enter sib2, iclass 16, count 2 2006.201.20:48:04.67#ibcon#flushed, iclass 16, count 2 2006.201.20:48:04.67#ibcon#about to write, iclass 16, count 2 2006.201.20:48:04.67#ibcon#wrote, iclass 16, count 2 2006.201.20:48:04.67#ibcon#about to read 3, iclass 16, count 2 2006.201.20:48:04.69#ibcon#read 3, iclass 16, count 2 2006.201.20:48:04.69#ibcon#about to read 4, iclass 16, count 2 2006.201.20:48:04.69#ibcon#read 4, iclass 16, count 2 2006.201.20:48:04.69#ibcon#about to read 5, iclass 16, count 2 2006.201.20:48:04.69#ibcon#read 5, iclass 16, count 2 2006.201.20:48:04.69#ibcon#about to read 6, iclass 16, count 2 2006.201.20:48:04.69#ibcon#read 6, iclass 16, count 2 2006.201.20:48:04.69#ibcon#end of sib2, iclass 16, count 2 2006.201.20:48:04.69#ibcon#*mode == 0, iclass 16, count 2 2006.201.20:48:04.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.20:48:04.69#ibcon#[25=AT03-08\r\n] 2006.201.20:48:04.69#ibcon#*before write, iclass 16, count 2 2006.201.20:48:04.69#ibcon#enter sib2, iclass 16, count 2 2006.201.20:48:04.69#ibcon#flushed, iclass 16, count 2 2006.201.20:48:04.69#ibcon#about to write, iclass 16, count 2 2006.201.20:48:04.69#ibcon#wrote, iclass 16, count 2 2006.201.20:48:04.69#ibcon#about to read 3, iclass 16, count 2 2006.201.20:48:04.72#ibcon#read 3, iclass 16, count 2 2006.201.20:48:04.72#ibcon#about to read 4, iclass 16, count 2 2006.201.20:48:04.72#ibcon#read 4, iclass 16, count 2 2006.201.20:48:04.72#ibcon#about to read 5, iclass 16, count 2 2006.201.20:48:04.72#ibcon#read 5, iclass 16, count 2 2006.201.20:48:04.72#ibcon#about to read 6, iclass 16, count 2 2006.201.20:48:04.72#ibcon#read 6, iclass 16, count 2 2006.201.20:48:04.72#ibcon#end of sib2, iclass 16, count 2 2006.201.20:48:04.72#ibcon#*after write, iclass 16, count 2 2006.201.20:48:04.72#ibcon#*before return 0, iclass 16, count 2 2006.201.20:48:04.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:04.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:04.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.20:48:04.72#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:04.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:04.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:04.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:04.84#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:48:04.84#ibcon#first serial, iclass 16, count 0 2006.201.20:48:04.84#ibcon#enter sib2, iclass 16, count 0 2006.201.20:48:04.84#ibcon#flushed, iclass 16, count 0 2006.201.20:48:04.84#ibcon#about to write, iclass 16, count 0 2006.201.20:48:04.84#ibcon#wrote, iclass 16, count 0 2006.201.20:48:04.84#ibcon#about to read 3, iclass 16, count 0 2006.201.20:48:04.86#ibcon#read 3, iclass 16, count 0 2006.201.20:48:04.86#ibcon#about to read 4, iclass 16, count 0 2006.201.20:48:04.86#ibcon#read 4, iclass 16, count 0 2006.201.20:48:04.86#ibcon#about to read 5, iclass 16, count 0 2006.201.20:48:04.86#ibcon#read 5, iclass 16, count 0 2006.201.20:48:04.86#ibcon#about to read 6, iclass 16, count 0 2006.201.20:48:04.86#ibcon#read 6, iclass 16, count 0 2006.201.20:48:04.86#ibcon#end of sib2, iclass 16, count 0 2006.201.20:48:04.86#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:48:04.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:48:04.86#ibcon#[25=USB\r\n] 2006.201.20:48:04.86#ibcon#*before write, iclass 16, count 0 2006.201.20:48:04.86#ibcon#enter sib2, iclass 16, count 0 2006.201.20:48:04.86#ibcon#flushed, iclass 16, count 0 2006.201.20:48:04.86#ibcon#about to write, iclass 16, count 0 2006.201.20:48:04.86#ibcon#wrote, iclass 16, count 0 2006.201.20:48:04.86#ibcon#about to read 3, iclass 16, count 0 2006.201.20:48:04.89#ibcon#read 3, iclass 16, count 0 2006.201.20:48:04.89#ibcon#about to read 4, iclass 16, count 0 2006.201.20:48:04.89#ibcon#read 4, iclass 16, count 0 2006.201.20:48:04.89#ibcon#about to read 5, iclass 16, count 0 2006.201.20:48:04.89#ibcon#read 5, iclass 16, count 0 2006.201.20:48:04.89#ibcon#about to read 6, iclass 16, count 0 2006.201.20:48:04.89#ibcon#read 6, iclass 16, count 0 2006.201.20:48:04.89#ibcon#end of sib2, iclass 16, count 0 2006.201.20:48:04.89#ibcon#*after write, iclass 16, count 0 2006.201.20:48:04.89#ibcon#*before return 0, iclass 16, count 0 2006.201.20:48:04.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:04.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:04.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:48:04.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:48:04.89$vck44/valo=4,624.99 2006.201.20:48:04.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.20:48:04.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.20:48:04.89#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:04.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:04.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:04.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:04.89#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:48:04.89#ibcon#first serial, iclass 18, count 0 2006.201.20:48:04.89#ibcon#enter sib2, iclass 18, count 0 2006.201.20:48:04.89#ibcon#flushed, iclass 18, count 0 2006.201.20:48:04.89#ibcon#about to write, iclass 18, count 0 2006.201.20:48:04.89#ibcon#wrote, iclass 18, count 0 2006.201.20:48:04.89#ibcon#about to read 3, iclass 18, count 0 2006.201.20:48:04.91#ibcon#read 3, iclass 18, count 0 2006.201.20:48:04.91#ibcon#about to read 4, iclass 18, count 0 2006.201.20:48:04.91#ibcon#read 4, iclass 18, count 0 2006.201.20:48:04.91#ibcon#about to read 5, iclass 18, count 0 2006.201.20:48:04.91#ibcon#read 5, iclass 18, count 0 2006.201.20:48:04.91#ibcon#about to read 6, iclass 18, count 0 2006.201.20:48:04.91#ibcon#read 6, iclass 18, count 0 2006.201.20:48:04.91#ibcon#end of sib2, iclass 18, count 0 2006.201.20:48:04.91#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:48:04.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:48:04.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:48:04.91#ibcon#*before write, iclass 18, count 0 2006.201.20:48:04.91#ibcon#enter sib2, iclass 18, count 0 2006.201.20:48:04.91#ibcon#flushed, iclass 18, count 0 2006.201.20:48:04.91#ibcon#about to write, iclass 18, count 0 2006.201.20:48:04.91#ibcon#wrote, iclass 18, count 0 2006.201.20:48:04.91#ibcon#about to read 3, iclass 18, count 0 2006.201.20:48:04.96#ibcon#read 3, iclass 18, count 0 2006.201.20:48:04.96#ibcon#about to read 4, iclass 18, count 0 2006.201.20:48:04.96#ibcon#read 4, iclass 18, count 0 2006.201.20:48:04.96#ibcon#about to read 5, iclass 18, count 0 2006.201.20:48:04.96#ibcon#read 5, iclass 18, count 0 2006.201.20:48:04.96#ibcon#about to read 6, iclass 18, count 0 2006.201.20:48:04.96#ibcon#read 6, iclass 18, count 0 2006.201.20:48:04.96#ibcon#end of sib2, iclass 18, count 0 2006.201.20:48:04.96#ibcon#*after write, iclass 18, count 0 2006.201.20:48:04.96#ibcon#*before return 0, iclass 18, count 0 2006.201.20:48:04.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:04.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:04.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:48:04.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:48:04.96$vck44/va=4,7 2006.201.20:48:04.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.20:48:04.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.20:48:04.96#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:04.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:05.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:05.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:05.01#ibcon#enter wrdev, iclass 20, count 2 2006.201.20:48:05.01#ibcon#first serial, iclass 20, count 2 2006.201.20:48:05.01#ibcon#enter sib2, iclass 20, count 2 2006.201.20:48:05.01#ibcon#flushed, iclass 20, count 2 2006.201.20:48:05.01#ibcon#about to write, iclass 20, count 2 2006.201.20:48:05.01#ibcon#wrote, iclass 20, count 2 2006.201.20:48:05.01#ibcon#about to read 3, iclass 20, count 2 2006.201.20:48:05.03#ibcon#read 3, iclass 20, count 2 2006.201.20:48:05.03#ibcon#about to read 4, iclass 20, count 2 2006.201.20:48:05.03#ibcon#read 4, iclass 20, count 2 2006.201.20:48:05.03#ibcon#about to read 5, iclass 20, count 2 2006.201.20:48:05.03#ibcon#read 5, iclass 20, count 2 2006.201.20:48:05.03#ibcon#about to read 6, iclass 20, count 2 2006.201.20:48:05.03#ibcon#read 6, iclass 20, count 2 2006.201.20:48:05.03#ibcon#end of sib2, iclass 20, count 2 2006.201.20:48:05.03#ibcon#*mode == 0, iclass 20, count 2 2006.201.20:48:05.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.20:48:05.03#ibcon#[25=AT04-07\r\n] 2006.201.20:48:05.03#ibcon#*before write, iclass 20, count 2 2006.201.20:48:05.03#ibcon#enter sib2, iclass 20, count 2 2006.201.20:48:05.03#ibcon#flushed, iclass 20, count 2 2006.201.20:48:05.03#ibcon#about to write, iclass 20, count 2 2006.201.20:48:05.03#ibcon#wrote, iclass 20, count 2 2006.201.20:48:05.03#ibcon#about to read 3, iclass 20, count 2 2006.201.20:48:05.06#ibcon#read 3, iclass 20, count 2 2006.201.20:48:05.06#ibcon#about to read 4, iclass 20, count 2 2006.201.20:48:05.06#ibcon#read 4, iclass 20, count 2 2006.201.20:48:05.06#ibcon#about to read 5, iclass 20, count 2 2006.201.20:48:05.06#ibcon#read 5, iclass 20, count 2 2006.201.20:48:05.06#ibcon#about to read 6, iclass 20, count 2 2006.201.20:48:05.06#ibcon#read 6, iclass 20, count 2 2006.201.20:48:05.06#ibcon#end of sib2, iclass 20, count 2 2006.201.20:48:05.06#ibcon#*after write, iclass 20, count 2 2006.201.20:48:05.06#ibcon#*before return 0, iclass 20, count 2 2006.201.20:48:05.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:05.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:05.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.20:48:05.06#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:05.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:05.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:05.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:05.18#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:48:05.18#ibcon#first serial, iclass 20, count 0 2006.201.20:48:05.18#ibcon#enter sib2, iclass 20, count 0 2006.201.20:48:05.18#ibcon#flushed, iclass 20, count 0 2006.201.20:48:05.18#ibcon#about to write, iclass 20, count 0 2006.201.20:48:05.18#ibcon#wrote, iclass 20, count 0 2006.201.20:48:05.18#ibcon#about to read 3, iclass 20, count 0 2006.201.20:48:05.20#ibcon#read 3, iclass 20, count 0 2006.201.20:48:05.20#ibcon#about to read 4, iclass 20, count 0 2006.201.20:48:05.20#ibcon#read 4, iclass 20, count 0 2006.201.20:48:05.20#ibcon#about to read 5, iclass 20, count 0 2006.201.20:48:05.20#ibcon#read 5, iclass 20, count 0 2006.201.20:48:05.20#ibcon#about to read 6, iclass 20, count 0 2006.201.20:48:05.20#ibcon#read 6, iclass 20, count 0 2006.201.20:48:05.20#ibcon#end of sib2, iclass 20, count 0 2006.201.20:48:05.20#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:48:05.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:48:05.20#ibcon#[25=USB\r\n] 2006.201.20:48:05.20#ibcon#*before write, iclass 20, count 0 2006.201.20:48:05.20#ibcon#enter sib2, iclass 20, count 0 2006.201.20:48:05.20#ibcon#flushed, iclass 20, count 0 2006.201.20:48:05.20#ibcon#about to write, iclass 20, count 0 2006.201.20:48:05.20#ibcon#wrote, iclass 20, count 0 2006.201.20:48:05.20#ibcon#about to read 3, iclass 20, count 0 2006.201.20:48:05.23#ibcon#read 3, iclass 20, count 0 2006.201.20:48:05.23#ibcon#about to read 4, iclass 20, count 0 2006.201.20:48:05.23#ibcon#read 4, iclass 20, count 0 2006.201.20:48:05.23#ibcon#about to read 5, iclass 20, count 0 2006.201.20:48:05.23#ibcon#read 5, iclass 20, count 0 2006.201.20:48:05.23#ibcon#about to read 6, iclass 20, count 0 2006.201.20:48:05.23#ibcon#read 6, iclass 20, count 0 2006.201.20:48:05.23#ibcon#end of sib2, iclass 20, count 0 2006.201.20:48:05.23#ibcon#*after write, iclass 20, count 0 2006.201.20:48:05.23#ibcon#*before return 0, iclass 20, count 0 2006.201.20:48:05.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:05.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:05.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:48:05.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:48:05.23$vck44/valo=5,734.99 2006.201.20:48:05.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.20:48:05.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.20:48:05.23#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:05.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:48:05.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:48:05.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:48:05.23#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:48:05.23#ibcon#first serial, iclass 22, count 0 2006.201.20:48:05.23#ibcon#enter sib2, iclass 22, count 0 2006.201.20:48:05.23#ibcon#flushed, iclass 22, count 0 2006.201.20:48:05.23#ibcon#about to write, iclass 22, count 0 2006.201.20:48:05.23#ibcon#wrote, iclass 22, count 0 2006.201.20:48:05.23#ibcon#about to read 3, iclass 22, count 0 2006.201.20:48:05.25#ibcon#read 3, iclass 22, count 0 2006.201.20:48:05.25#ibcon#about to read 4, iclass 22, count 0 2006.201.20:48:05.25#ibcon#read 4, iclass 22, count 0 2006.201.20:48:05.25#ibcon#about to read 5, iclass 22, count 0 2006.201.20:48:05.25#ibcon#read 5, iclass 22, count 0 2006.201.20:48:05.25#ibcon#about to read 6, iclass 22, count 0 2006.201.20:48:05.25#ibcon#read 6, iclass 22, count 0 2006.201.20:48:05.25#ibcon#end of sib2, iclass 22, count 0 2006.201.20:48:05.25#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:48:05.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:48:05.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:48:05.25#ibcon#*before write, iclass 22, count 0 2006.201.20:48:05.25#ibcon#enter sib2, iclass 22, count 0 2006.201.20:48:05.25#ibcon#flushed, iclass 22, count 0 2006.201.20:48:05.25#ibcon#about to write, iclass 22, count 0 2006.201.20:48:05.25#ibcon#wrote, iclass 22, count 0 2006.201.20:48:05.25#ibcon#about to read 3, iclass 22, count 0 2006.201.20:48:05.29#ibcon#read 3, iclass 22, count 0 2006.201.20:48:05.29#ibcon#about to read 4, iclass 22, count 0 2006.201.20:48:05.29#ibcon#read 4, iclass 22, count 0 2006.201.20:48:05.29#ibcon#about to read 5, iclass 22, count 0 2006.201.20:48:05.29#ibcon#read 5, iclass 22, count 0 2006.201.20:48:05.29#ibcon#about to read 6, iclass 22, count 0 2006.201.20:48:05.29#ibcon#read 6, iclass 22, count 0 2006.201.20:48:05.29#ibcon#end of sib2, iclass 22, count 0 2006.201.20:48:05.29#ibcon#*after write, iclass 22, count 0 2006.201.20:48:05.29#ibcon#*before return 0, iclass 22, count 0 2006.201.20:48:05.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:48:05.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.20:48:05.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:48:05.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:48:05.29$vck44/va=5,4 2006.201.20:48:05.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.20:48:05.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.20:48:05.29#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:05.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:48:05.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:48:05.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:48:05.35#ibcon#enter wrdev, iclass 24, count 2 2006.201.20:48:05.35#ibcon#first serial, iclass 24, count 2 2006.201.20:48:05.35#ibcon#enter sib2, iclass 24, count 2 2006.201.20:48:05.35#ibcon#flushed, iclass 24, count 2 2006.201.20:48:05.35#ibcon#about to write, iclass 24, count 2 2006.201.20:48:05.35#ibcon#wrote, iclass 24, count 2 2006.201.20:48:05.35#ibcon#about to read 3, iclass 24, count 2 2006.201.20:48:05.37#ibcon#read 3, iclass 24, count 2 2006.201.20:48:05.37#ibcon#about to read 4, iclass 24, count 2 2006.201.20:48:05.37#ibcon#read 4, iclass 24, count 2 2006.201.20:48:05.37#ibcon#about to read 5, iclass 24, count 2 2006.201.20:48:05.37#ibcon#read 5, iclass 24, count 2 2006.201.20:48:05.37#ibcon#about to read 6, iclass 24, count 2 2006.201.20:48:05.37#ibcon#read 6, iclass 24, count 2 2006.201.20:48:05.37#ibcon#end of sib2, iclass 24, count 2 2006.201.20:48:05.37#ibcon#*mode == 0, iclass 24, count 2 2006.201.20:48:05.37#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.20:48:05.37#ibcon#[25=AT05-04\r\n] 2006.201.20:48:05.37#ibcon#*before write, iclass 24, count 2 2006.201.20:48:05.37#ibcon#enter sib2, iclass 24, count 2 2006.201.20:48:05.37#ibcon#flushed, iclass 24, count 2 2006.201.20:48:05.37#ibcon#about to write, iclass 24, count 2 2006.201.20:48:05.37#ibcon#wrote, iclass 24, count 2 2006.201.20:48:05.37#ibcon#about to read 3, iclass 24, count 2 2006.201.20:48:05.40#ibcon#read 3, iclass 24, count 2 2006.201.20:48:05.40#ibcon#about to read 4, iclass 24, count 2 2006.201.20:48:05.40#ibcon#read 4, iclass 24, count 2 2006.201.20:48:05.40#ibcon#about to read 5, iclass 24, count 2 2006.201.20:48:05.40#ibcon#read 5, iclass 24, count 2 2006.201.20:48:05.40#ibcon#about to read 6, iclass 24, count 2 2006.201.20:48:05.40#ibcon#read 6, iclass 24, count 2 2006.201.20:48:05.40#ibcon#end of sib2, iclass 24, count 2 2006.201.20:48:05.40#ibcon#*after write, iclass 24, count 2 2006.201.20:48:05.40#ibcon#*before return 0, iclass 24, count 2 2006.201.20:48:05.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:48:05.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.20:48:05.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.20:48:05.40#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:05.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:48:05.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:48:05.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:48:05.52#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:48:05.52#ibcon#first serial, iclass 24, count 0 2006.201.20:48:05.52#ibcon#enter sib2, iclass 24, count 0 2006.201.20:48:05.52#ibcon#flushed, iclass 24, count 0 2006.201.20:48:05.52#ibcon#about to write, iclass 24, count 0 2006.201.20:48:05.52#ibcon#wrote, iclass 24, count 0 2006.201.20:48:05.52#ibcon#about to read 3, iclass 24, count 0 2006.201.20:48:05.54#ibcon#read 3, iclass 24, count 0 2006.201.20:48:05.54#ibcon#about to read 4, iclass 24, count 0 2006.201.20:48:05.54#ibcon#read 4, iclass 24, count 0 2006.201.20:48:05.54#ibcon#about to read 5, iclass 24, count 0 2006.201.20:48:05.54#ibcon#read 5, iclass 24, count 0 2006.201.20:48:05.54#ibcon#about to read 6, iclass 24, count 0 2006.201.20:48:05.54#ibcon#read 6, iclass 24, count 0 2006.201.20:48:05.54#ibcon#end of sib2, iclass 24, count 0 2006.201.20:48:05.54#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:48:05.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:48:05.54#ibcon#[25=USB\r\n] 2006.201.20:48:05.54#ibcon#*before write, iclass 24, count 0 2006.201.20:48:05.54#ibcon#enter sib2, iclass 24, count 0 2006.201.20:48:05.54#ibcon#flushed, iclass 24, count 0 2006.201.20:48:05.54#ibcon#about to write, iclass 24, count 0 2006.201.20:48:05.54#ibcon#wrote, iclass 24, count 0 2006.201.20:48:05.54#ibcon#about to read 3, iclass 24, count 0 2006.201.20:48:05.57#ibcon#read 3, iclass 24, count 0 2006.201.20:48:05.57#ibcon#about to read 4, iclass 24, count 0 2006.201.20:48:05.57#ibcon#read 4, iclass 24, count 0 2006.201.20:48:05.57#ibcon#about to read 5, iclass 24, count 0 2006.201.20:48:05.57#ibcon#read 5, iclass 24, count 0 2006.201.20:48:05.57#ibcon#about to read 6, iclass 24, count 0 2006.201.20:48:05.57#ibcon#read 6, iclass 24, count 0 2006.201.20:48:05.57#ibcon#end of sib2, iclass 24, count 0 2006.201.20:48:05.57#ibcon#*after write, iclass 24, count 0 2006.201.20:48:05.57#ibcon#*before return 0, iclass 24, count 0 2006.201.20:48:05.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:48:05.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.20:48:05.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:48:05.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:48:05.57$vck44/valo=6,814.99 2006.201.20:48:05.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.20:48:05.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.20:48:05.57#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:05.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:48:05.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:48:05.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:48:05.57#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:48:05.57#ibcon#first serial, iclass 26, count 0 2006.201.20:48:05.57#ibcon#enter sib2, iclass 26, count 0 2006.201.20:48:05.57#ibcon#flushed, iclass 26, count 0 2006.201.20:48:05.57#ibcon#about to write, iclass 26, count 0 2006.201.20:48:05.57#ibcon#wrote, iclass 26, count 0 2006.201.20:48:05.57#ibcon#about to read 3, iclass 26, count 0 2006.201.20:48:05.59#ibcon#read 3, iclass 26, count 0 2006.201.20:48:05.59#ibcon#about to read 4, iclass 26, count 0 2006.201.20:48:05.59#ibcon#read 4, iclass 26, count 0 2006.201.20:48:05.59#ibcon#about to read 5, iclass 26, count 0 2006.201.20:48:05.59#ibcon#read 5, iclass 26, count 0 2006.201.20:48:05.59#ibcon#about to read 6, iclass 26, count 0 2006.201.20:48:05.59#ibcon#read 6, iclass 26, count 0 2006.201.20:48:05.59#ibcon#end of sib2, iclass 26, count 0 2006.201.20:48:05.59#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:48:05.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:48:05.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:48:05.59#ibcon#*before write, iclass 26, count 0 2006.201.20:48:05.59#ibcon#enter sib2, iclass 26, count 0 2006.201.20:48:05.59#ibcon#flushed, iclass 26, count 0 2006.201.20:48:05.59#ibcon#about to write, iclass 26, count 0 2006.201.20:48:05.59#ibcon#wrote, iclass 26, count 0 2006.201.20:48:05.59#ibcon#about to read 3, iclass 26, count 0 2006.201.20:48:05.64#ibcon#read 3, iclass 26, count 0 2006.201.20:48:05.64#ibcon#about to read 4, iclass 26, count 0 2006.201.20:48:05.64#ibcon#read 4, iclass 26, count 0 2006.201.20:48:05.64#ibcon#about to read 5, iclass 26, count 0 2006.201.20:48:05.64#ibcon#read 5, iclass 26, count 0 2006.201.20:48:05.64#ibcon#about to read 6, iclass 26, count 0 2006.201.20:48:05.64#ibcon#read 6, iclass 26, count 0 2006.201.20:48:05.64#ibcon#end of sib2, iclass 26, count 0 2006.201.20:48:05.64#ibcon#*after write, iclass 26, count 0 2006.201.20:48:05.64#ibcon#*before return 0, iclass 26, count 0 2006.201.20:48:05.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:48:05.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.20:48:05.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:48:05.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:48:05.64$vck44/va=6,5 2006.201.20:48:05.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.20:48:05.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.20:48:05.64#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:05.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:48:05.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:48:05.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:48:05.69#ibcon#enter wrdev, iclass 28, count 2 2006.201.20:48:05.69#ibcon#first serial, iclass 28, count 2 2006.201.20:48:05.69#ibcon#enter sib2, iclass 28, count 2 2006.201.20:48:05.69#ibcon#flushed, iclass 28, count 2 2006.201.20:48:05.69#ibcon#about to write, iclass 28, count 2 2006.201.20:48:05.69#ibcon#wrote, iclass 28, count 2 2006.201.20:48:05.69#ibcon#about to read 3, iclass 28, count 2 2006.201.20:48:05.71#ibcon#read 3, iclass 28, count 2 2006.201.20:48:05.71#ibcon#about to read 4, iclass 28, count 2 2006.201.20:48:05.71#ibcon#read 4, iclass 28, count 2 2006.201.20:48:05.71#ibcon#about to read 5, iclass 28, count 2 2006.201.20:48:05.71#ibcon#read 5, iclass 28, count 2 2006.201.20:48:05.71#ibcon#about to read 6, iclass 28, count 2 2006.201.20:48:05.71#ibcon#read 6, iclass 28, count 2 2006.201.20:48:05.71#ibcon#end of sib2, iclass 28, count 2 2006.201.20:48:05.71#ibcon#*mode == 0, iclass 28, count 2 2006.201.20:48:05.71#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.20:48:05.71#ibcon#[25=AT06-05\r\n] 2006.201.20:48:05.71#ibcon#*before write, iclass 28, count 2 2006.201.20:48:05.71#ibcon#enter sib2, iclass 28, count 2 2006.201.20:48:05.71#ibcon#flushed, iclass 28, count 2 2006.201.20:48:05.71#ibcon#about to write, iclass 28, count 2 2006.201.20:48:05.71#ibcon#wrote, iclass 28, count 2 2006.201.20:48:05.71#ibcon#about to read 3, iclass 28, count 2 2006.201.20:48:05.74#ibcon#read 3, iclass 28, count 2 2006.201.20:48:05.74#ibcon#about to read 4, iclass 28, count 2 2006.201.20:48:05.74#ibcon#read 4, iclass 28, count 2 2006.201.20:48:05.74#ibcon#about to read 5, iclass 28, count 2 2006.201.20:48:05.74#ibcon#read 5, iclass 28, count 2 2006.201.20:48:05.74#ibcon#about to read 6, iclass 28, count 2 2006.201.20:48:05.74#ibcon#read 6, iclass 28, count 2 2006.201.20:48:05.74#ibcon#end of sib2, iclass 28, count 2 2006.201.20:48:05.74#ibcon#*after write, iclass 28, count 2 2006.201.20:48:05.74#ibcon#*before return 0, iclass 28, count 2 2006.201.20:48:05.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:48:05.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.20:48:05.74#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.20:48:05.74#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:05.74#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:48:05.86#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:48:05.86#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:48:05.86#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:48:05.86#ibcon#first serial, iclass 28, count 0 2006.201.20:48:05.86#ibcon#enter sib2, iclass 28, count 0 2006.201.20:48:05.86#ibcon#flushed, iclass 28, count 0 2006.201.20:48:05.86#ibcon#about to write, iclass 28, count 0 2006.201.20:48:05.86#ibcon#wrote, iclass 28, count 0 2006.201.20:48:05.86#ibcon#about to read 3, iclass 28, count 0 2006.201.20:48:05.88#ibcon#read 3, iclass 28, count 0 2006.201.20:48:05.88#ibcon#about to read 4, iclass 28, count 0 2006.201.20:48:05.88#ibcon#read 4, iclass 28, count 0 2006.201.20:48:05.88#ibcon#about to read 5, iclass 28, count 0 2006.201.20:48:05.88#ibcon#read 5, iclass 28, count 0 2006.201.20:48:05.88#ibcon#about to read 6, iclass 28, count 0 2006.201.20:48:05.88#ibcon#read 6, iclass 28, count 0 2006.201.20:48:05.88#ibcon#end of sib2, iclass 28, count 0 2006.201.20:48:05.88#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:48:05.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:48:05.88#ibcon#[25=USB\r\n] 2006.201.20:48:05.88#ibcon#*before write, iclass 28, count 0 2006.201.20:48:05.88#ibcon#enter sib2, iclass 28, count 0 2006.201.20:48:05.88#ibcon#flushed, iclass 28, count 0 2006.201.20:48:05.88#ibcon#about to write, iclass 28, count 0 2006.201.20:48:05.88#ibcon#wrote, iclass 28, count 0 2006.201.20:48:05.88#ibcon#about to read 3, iclass 28, count 0 2006.201.20:48:05.91#ibcon#read 3, iclass 28, count 0 2006.201.20:48:05.91#ibcon#about to read 4, iclass 28, count 0 2006.201.20:48:05.91#ibcon#read 4, iclass 28, count 0 2006.201.20:48:05.91#ibcon#about to read 5, iclass 28, count 0 2006.201.20:48:05.91#ibcon#read 5, iclass 28, count 0 2006.201.20:48:05.91#ibcon#about to read 6, iclass 28, count 0 2006.201.20:48:05.91#ibcon#read 6, iclass 28, count 0 2006.201.20:48:05.91#ibcon#end of sib2, iclass 28, count 0 2006.201.20:48:05.91#ibcon#*after write, iclass 28, count 0 2006.201.20:48:05.91#ibcon#*before return 0, iclass 28, count 0 2006.201.20:48:05.91#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:48:05.91#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.20:48:05.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:48:05.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:48:05.91$vck44/valo=7,864.99 2006.201.20:48:05.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.20:48:05.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.20:48:05.91#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:05.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:05.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:05.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:05.91#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:48:05.91#ibcon#first serial, iclass 30, count 0 2006.201.20:48:05.91#ibcon#enter sib2, iclass 30, count 0 2006.201.20:48:05.91#ibcon#flushed, iclass 30, count 0 2006.201.20:48:05.91#ibcon#about to write, iclass 30, count 0 2006.201.20:48:05.91#ibcon#wrote, iclass 30, count 0 2006.201.20:48:05.91#ibcon#about to read 3, iclass 30, count 0 2006.201.20:48:05.93#ibcon#read 3, iclass 30, count 0 2006.201.20:48:05.93#ibcon#about to read 4, iclass 30, count 0 2006.201.20:48:05.93#ibcon#read 4, iclass 30, count 0 2006.201.20:48:05.93#ibcon#about to read 5, iclass 30, count 0 2006.201.20:48:05.93#ibcon#read 5, iclass 30, count 0 2006.201.20:48:05.93#ibcon#about to read 6, iclass 30, count 0 2006.201.20:48:05.93#ibcon#read 6, iclass 30, count 0 2006.201.20:48:05.93#ibcon#end of sib2, iclass 30, count 0 2006.201.20:48:05.93#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:48:05.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:48:05.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:48:05.93#ibcon#*before write, iclass 30, count 0 2006.201.20:48:05.93#ibcon#enter sib2, iclass 30, count 0 2006.201.20:48:05.93#ibcon#flushed, iclass 30, count 0 2006.201.20:48:05.93#ibcon#about to write, iclass 30, count 0 2006.201.20:48:05.93#ibcon#wrote, iclass 30, count 0 2006.201.20:48:05.93#ibcon#about to read 3, iclass 30, count 0 2006.201.20:48:05.98#ibcon#read 3, iclass 30, count 0 2006.201.20:48:05.98#ibcon#about to read 4, iclass 30, count 0 2006.201.20:48:05.98#ibcon#read 4, iclass 30, count 0 2006.201.20:48:05.98#ibcon#about to read 5, iclass 30, count 0 2006.201.20:48:05.98#ibcon#read 5, iclass 30, count 0 2006.201.20:48:05.98#ibcon#about to read 6, iclass 30, count 0 2006.201.20:48:05.98#ibcon#read 6, iclass 30, count 0 2006.201.20:48:05.98#ibcon#end of sib2, iclass 30, count 0 2006.201.20:48:05.98#ibcon#*after write, iclass 30, count 0 2006.201.20:48:05.98#ibcon#*before return 0, iclass 30, count 0 2006.201.20:48:05.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:05.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:05.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:48:05.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:48:05.98$vck44/va=7,5 2006.201.20:48:05.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.20:48:05.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.20:48:05.98#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:05.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:06.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:06.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:06.03#ibcon#enter wrdev, iclass 32, count 2 2006.201.20:48:06.03#ibcon#first serial, iclass 32, count 2 2006.201.20:48:06.03#ibcon#enter sib2, iclass 32, count 2 2006.201.20:48:06.03#ibcon#flushed, iclass 32, count 2 2006.201.20:48:06.03#ibcon#about to write, iclass 32, count 2 2006.201.20:48:06.03#ibcon#wrote, iclass 32, count 2 2006.201.20:48:06.03#ibcon#about to read 3, iclass 32, count 2 2006.201.20:48:06.05#ibcon#read 3, iclass 32, count 2 2006.201.20:48:06.05#ibcon#about to read 4, iclass 32, count 2 2006.201.20:48:06.05#ibcon#read 4, iclass 32, count 2 2006.201.20:48:06.05#ibcon#about to read 5, iclass 32, count 2 2006.201.20:48:06.05#ibcon#read 5, iclass 32, count 2 2006.201.20:48:06.05#ibcon#about to read 6, iclass 32, count 2 2006.201.20:48:06.05#ibcon#read 6, iclass 32, count 2 2006.201.20:48:06.05#ibcon#end of sib2, iclass 32, count 2 2006.201.20:48:06.05#ibcon#*mode == 0, iclass 32, count 2 2006.201.20:48:06.05#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.20:48:06.05#ibcon#[25=AT07-05\r\n] 2006.201.20:48:06.05#ibcon#*before write, iclass 32, count 2 2006.201.20:48:06.05#ibcon#enter sib2, iclass 32, count 2 2006.201.20:48:06.05#ibcon#flushed, iclass 32, count 2 2006.201.20:48:06.05#ibcon#about to write, iclass 32, count 2 2006.201.20:48:06.05#ibcon#wrote, iclass 32, count 2 2006.201.20:48:06.05#ibcon#about to read 3, iclass 32, count 2 2006.201.20:48:06.08#ibcon#read 3, iclass 32, count 2 2006.201.20:48:06.08#ibcon#about to read 4, iclass 32, count 2 2006.201.20:48:06.08#ibcon#read 4, iclass 32, count 2 2006.201.20:48:06.08#ibcon#about to read 5, iclass 32, count 2 2006.201.20:48:06.08#ibcon#read 5, iclass 32, count 2 2006.201.20:48:06.08#ibcon#about to read 6, iclass 32, count 2 2006.201.20:48:06.08#ibcon#read 6, iclass 32, count 2 2006.201.20:48:06.08#ibcon#end of sib2, iclass 32, count 2 2006.201.20:48:06.08#ibcon#*after write, iclass 32, count 2 2006.201.20:48:06.08#ibcon#*before return 0, iclass 32, count 2 2006.201.20:48:06.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:06.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:06.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.20:48:06.08#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:06.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:06.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:06.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:06.20#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:48:06.20#ibcon#first serial, iclass 32, count 0 2006.201.20:48:06.20#ibcon#enter sib2, iclass 32, count 0 2006.201.20:48:06.20#ibcon#flushed, iclass 32, count 0 2006.201.20:48:06.20#ibcon#about to write, iclass 32, count 0 2006.201.20:48:06.20#ibcon#wrote, iclass 32, count 0 2006.201.20:48:06.20#ibcon#about to read 3, iclass 32, count 0 2006.201.20:48:06.22#ibcon#read 3, iclass 32, count 0 2006.201.20:48:06.22#ibcon#about to read 4, iclass 32, count 0 2006.201.20:48:06.22#ibcon#read 4, iclass 32, count 0 2006.201.20:48:06.22#ibcon#about to read 5, iclass 32, count 0 2006.201.20:48:06.22#ibcon#read 5, iclass 32, count 0 2006.201.20:48:06.22#ibcon#about to read 6, iclass 32, count 0 2006.201.20:48:06.22#ibcon#read 6, iclass 32, count 0 2006.201.20:48:06.22#ibcon#end of sib2, iclass 32, count 0 2006.201.20:48:06.22#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:48:06.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:48:06.22#ibcon#[25=USB\r\n] 2006.201.20:48:06.22#ibcon#*before write, iclass 32, count 0 2006.201.20:48:06.22#ibcon#enter sib2, iclass 32, count 0 2006.201.20:48:06.22#ibcon#flushed, iclass 32, count 0 2006.201.20:48:06.22#ibcon#about to write, iclass 32, count 0 2006.201.20:48:06.22#ibcon#wrote, iclass 32, count 0 2006.201.20:48:06.22#ibcon#about to read 3, iclass 32, count 0 2006.201.20:48:06.25#ibcon#read 3, iclass 32, count 0 2006.201.20:48:06.25#ibcon#about to read 4, iclass 32, count 0 2006.201.20:48:06.25#ibcon#read 4, iclass 32, count 0 2006.201.20:48:06.25#ibcon#about to read 5, iclass 32, count 0 2006.201.20:48:06.25#ibcon#read 5, iclass 32, count 0 2006.201.20:48:06.25#ibcon#about to read 6, iclass 32, count 0 2006.201.20:48:06.25#ibcon#read 6, iclass 32, count 0 2006.201.20:48:06.25#ibcon#end of sib2, iclass 32, count 0 2006.201.20:48:06.25#ibcon#*after write, iclass 32, count 0 2006.201.20:48:06.25#ibcon#*before return 0, iclass 32, count 0 2006.201.20:48:06.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:06.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:06.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:48:06.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:48:06.25$vck44/valo=8,884.99 2006.201.20:48:06.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.20:48:06.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.20:48:06.25#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:06.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:06.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:06.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:06.25#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:48:06.25#ibcon#first serial, iclass 34, count 0 2006.201.20:48:06.25#ibcon#enter sib2, iclass 34, count 0 2006.201.20:48:06.25#ibcon#flushed, iclass 34, count 0 2006.201.20:48:06.25#ibcon#about to write, iclass 34, count 0 2006.201.20:48:06.25#ibcon#wrote, iclass 34, count 0 2006.201.20:48:06.25#ibcon#about to read 3, iclass 34, count 0 2006.201.20:48:06.27#ibcon#read 3, iclass 34, count 0 2006.201.20:48:06.27#ibcon#about to read 4, iclass 34, count 0 2006.201.20:48:06.27#ibcon#read 4, iclass 34, count 0 2006.201.20:48:06.27#ibcon#about to read 5, iclass 34, count 0 2006.201.20:48:06.27#ibcon#read 5, iclass 34, count 0 2006.201.20:48:06.27#ibcon#about to read 6, iclass 34, count 0 2006.201.20:48:06.27#ibcon#read 6, iclass 34, count 0 2006.201.20:48:06.27#ibcon#end of sib2, iclass 34, count 0 2006.201.20:48:06.27#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:48:06.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:48:06.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:48:06.27#ibcon#*before write, iclass 34, count 0 2006.201.20:48:06.27#ibcon#enter sib2, iclass 34, count 0 2006.201.20:48:06.27#ibcon#flushed, iclass 34, count 0 2006.201.20:48:06.27#ibcon#about to write, iclass 34, count 0 2006.201.20:48:06.27#ibcon#wrote, iclass 34, count 0 2006.201.20:48:06.27#ibcon#about to read 3, iclass 34, count 0 2006.201.20:48:06.31#ibcon#read 3, iclass 34, count 0 2006.201.20:48:06.31#ibcon#about to read 4, iclass 34, count 0 2006.201.20:48:06.31#ibcon#read 4, iclass 34, count 0 2006.201.20:48:06.31#ibcon#about to read 5, iclass 34, count 0 2006.201.20:48:06.31#ibcon#read 5, iclass 34, count 0 2006.201.20:48:06.31#ibcon#about to read 6, iclass 34, count 0 2006.201.20:48:06.31#ibcon#read 6, iclass 34, count 0 2006.201.20:48:06.31#ibcon#end of sib2, iclass 34, count 0 2006.201.20:48:06.31#ibcon#*after write, iclass 34, count 0 2006.201.20:48:06.31#ibcon#*before return 0, iclass 34, count 0 2006.201.20:48:06.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:06.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:06.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:48:06.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:48:06.31$vck44/va=8,4 2006.201.20:48:06.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.20:48:06.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.20:48:06.31#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:06.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:06.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:06.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:06.37#ibcon#enter wrdev, iclass 36, count 2 2006.201.20:48:06.37#ibcon#first serial, iclass 36, count 2 2006.201.20:48:06.37#ibcon#enter sib2, iclass 36, count 2 2006.201.20:48:06.37#ibcon#flushed, iclass 36, count 2 2006.201.20:48:06.37#ibcon#about to write, iclass 36, count 2 2006.201.20:48:06.37#ibcon#wrote, iclass 36, count 2 2006.201.20:48:06.37#ibcon#about to read 3, iclass 36, count 2 2006.201.20:48:06.39#ibcon#read 3, iclass 36, count 2 2006.201.20:48:06.39#ibcon#about to read 4, iclass 36, count 2 2006.201.20:48:06.39#ibcon#read 4, iclass 36, count 2 2006.201.20:48:06.39#ibcon#about to read 5, iclass 36, count 2 2006.201.20:48:06.39#ibcon#read 5, iclass 36, count 2 2006.201.20:48:06.39#ibcon#about to read 6, iclass 36, count 2 2006.201.20:48:06.39#ibcon#read 6, iclass 36, count 2 2006.201.20:48:06.39#ibcon#end of sib2, iclass 36, count 2 2006.201.20:48:06.39#ibcon#*mode == 0, iclass 36, count 2 2006.201.20:48:06.39#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.20:48:06.39#ibcon#[25=AT08-04\r\n] 2006.201.20:48:06.39#ibcon#*before write, iclass 36, count 2 2006.201.20:48:06.39#ibcon#enter sib2, iclass 36, count 2 2006.201.20:48:06.39#ibcon#flushed, iclass 36, count 2 2006.201.20:48:06.39#ibcon#about to write, iclass 36, count 2 2006.201.20:48:06.39#ibcon#wrote, iclass 36, count 2 2006.201.20:48:06.39#ibcon#about to read 3, iclass 36, count 2 2006.201.20:48:06.42#ibcon#read 3, iclass 36, count 2 2006.201.20:48:06.42#ibcon#about to read 4, iclass 36, count 2 2006.201.20:48:06.42#ibcon#read 4, iclass 36, count 2 2006.201.20:48:06.42#ibcon#about to read 5, iclass 36, count 2 2006.201.20:48:06.42#ibcon#read 5, iclass 36, count 2 2006.201.20:48:06.42#ibcon#about to read 6, iclass 36, count 2 2006.201.20:48:06.42#ibcon#read 6, iclass 36, count 2 2006.201.20:48:06.42#ibcon#end of sib2, iclass 36, count 2 2006.201.20:48:06.42#ibcon#*after write, iclass 36, count 2 2006.201.20:48:06.42#ibcon#*before return 0, iclass 36, count 2 2006.201.20:48:06.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:06.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:06.42#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.20:48:06.42#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:06.42#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:06.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:06.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:06.54#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:48:06.54#ibcon#first serial, iclass 36, count 0 2006.201.20:48:06.54#ibcon#enter sib2, iclass 36, count 0 2006.201.20:48:06.54#ibcon#flushed, iclass 36, count 0 2006.201.20:48:06.54#ibcon#about to write, iclass 36, count 0 2006.201.20:48:06.54#ibcon#wrote, iclass 36, count 0 2006.201.20:48:06.54#ibcon#about to read 3, iclass 36, count 0 2006.201.20:48:06.56#ibcon#read 3, iclass 36, count 0 2006.201.20:48:06.56#ibcon#about to read 4, iclass 36, count 0 2006.201.20:48:06.56#ibcon#read 4, iclass 36, count 0 2006.201.20:48:06.56#ibcon#about to read 5, iclass 36, count 0 2006.201.20:48:06.56#ibcon#read 5, iclass 36, count 0 2006.201.20:48:06.56#ibcon#about to read 6, iclass 36, count 0 2006.201.20:48:06.56#ibcon#read 6, iclass 36, count 0 2006.201.20:48:06.56#ibcon#end of sib2, iclass 36, count 0 2006.201.20:48:06.56#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:48:06.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:48:06.56#ibcon#[25=USB\r\n] 2006.201.20:48:06.56#ibcon#*before write, iclass 36, count 0 2006.201.20:48:06.56#ibcon#enter sib2, iclass 36, count 0 2006.201.20:48:06.56#ibcon#flushed, iclass 36, count 0 2006.201.20:48:06.56#ibcon#about to write, iclass 36, count 0 2006.201.20:48:06.56#ibcon#wrote, iclass 36, count 0 2006.201.20:48:06.56#ibcon#about to read 3, iclass 36, count 0 2006.201.20:48:06.59#ibcon#read 3, iclass 36, count 0 2006.201.20:48:06.59#ibcon#about to read 4, iclass 36, count 0 2006.201.20:48:06.59#ibcon#read 4, iclass 36, count 0 2006.201.20:48:06.59#ibcon#about to read 5, iclass 36, count 0 2006.201.20:48:06.59#ibcon#read 5, iclass 36, count 0 2006.201.20:48:06.59#ibcon#about to read 6, iclass 36, count 0 2006.201.20:48:06.59#ibcon#read 6, iclass 36, count 0 2006.201.20:48:06.59#ibcon#end of sib2, iclass 36, count 0 2006.201.20:48:06.59#ibcon#*after write, iclass 36, count 0 2006.201.20:48:06.59#ibcon#*before return 0, iclass 36, count 0 2006.201.20:48:06.59#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:06.59#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:06.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:48:06.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:48:06.59$vck44/vblo=1,629.99 2006.201.20:48:06.59#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.20:48:06.59#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.20:48:06.59#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:06.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:06.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:06.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:06.59#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:48:06.59#ibcon#first serial, iclass 38, count 0 2006.201.20:48:06.59#ibcon#enter sib2, iclass 38, count 0 2006.201.20:48:06.59#ibcon#flushed, iclass 38, count 0 2006.201.20:48:06.59#ibcon#about to write, iclass 38, count 0 2006.201.20:48:06.59#ibcon#wrote, iclass 38, count 0 2006.201.20:48:06.59#ibcon#about to read 3, iclass 38, count 0 2006.201.20:48:06.61#ibcon#read 3, iclass 38, count 0 2006.201.20:48:06.61#ibcon#about to read 4, iclass 38, count 0 2006.201.20:48:06.61#ibcon#read 4, iclass 38, count 0 2006.201.20:48:06.61#ibcon#about to read 5, iclass 38, count 0 2006.201.20:48:06.61#ibcon#read 5, iclass 38, count 0 2006.201.20:48:06.61#ibcon#about to read 6, iclass 38, count 0 2006.201.20:48:06.61#ibcon#read 6, iclass 38, count 0 2006.201.20:48:06.61#ibcon#end of sib2, iclass 38, count 0 2006.201.20:48:06.61#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:48:06.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:48:06.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:48:06.61#ibcon#*before write, iclass 38, count 0 2006.201.20:48:06.61#ibcon#enter sib2, iclass 38, count 0 2006.201.20:48:06.61#ibcon#flushed, iclass 38, count 0 2006.201.20:48:06.61#ibcon#about to write, iclass 38, count 0 2006.201.20:48:06.61#ibcon#wrote, iclass 38, count 0 2006.201.20:48:06.61#ibcon#about to read 3, iclass 38, count 0 2006.201.20:48:06.66#ibcon#read 3, iclass 38, count 0 2006.201.20:48:06.66#ibcon#about to read 4, iclass 38, count 0 2006.201.20:48:06.66#ibcon#read 4, iclass 38, count 0 2006.201.20:48:06.66#ibcon#about to read 5, iclass 38, count 0 2006.201.20:48:06.66#ibcon#read 5, iclass 38, count 0 2006.201.20:48:06.66#ibcon#about to read 6, iclass 38, count 0 2006.201.20:48:06.66#ibcon#read 6, iclass 38, count 0 2006.201.20:48:06.66#ibcon#end of sib2, iclass 38, count 0 2006.201.20:48:06.66#ibcon#*after write, iclass 38, count 0 2006.201.20:48:06.66#ibcon#*before return 0, iclass 38, count 0 2006.201.20:48:06.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:06.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:06.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:48:06.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:48:06.66$vck44/vb=1,4 2006.201.20:48:06.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.20:48:06.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.20:48:06.66#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:06.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:48:06.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:48:06.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:48:06.66#ibcon#enter wrdev, iclass 40, count 2 2006.201.20:48:06.66#ibcon#first serial, iclass 40, count 2 2006.201.20:48:06.66#ibcon#enter sib2, iclass 40, count 2 2006.201.20:48:06.66#ibcon#flushed, iclass 40, count 2 2006.201.20:48:06.66#ibcon#about to write, iclass 40, count 2 2006.201.20:48:06.66#ibcon#wrote, iclass 40, count 2 2006.201.20:48:06.66#ibcon#about to read 3, iclass 40, count 2 2006.201.20:48:06.68#ibcon#read 3, iclass 40, count 2 2006.201.20:48:06.68#ibcon#about to read 4, iclass 40, count 2 2006.201.20:48:06.68#ibcon#read 4, iclass 40, count 2 2006.201.20:48:06.68#ibcon#about to read 5, iclass 40, count 2 2006.201.20:48:06.68#ibcon#read 5, iclass 40, count 2 2006.201.20:48:06.68#ibcon#about to read 6, iclass 40, count 2 2006.201.20:48:06.68#ibcon#read 6, iclass 40, count 2 2006.201.20:48:06.68#ibcon#end of sib2, iclass 40, count 2 2006.201.20:48:06.68#ibcon#*mode == 0, iclass 40, count 2 2006.201.20:48:06.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.20:48:06.68#ibcon#[27=AT01-04\r\n] 2006.201.20:48:06.68#ibcon#*before write, iclass 40, count 2 2006.201.20:48:06.68#ibcon#enter sib2, iclass 40, count 2 2006.201.20:48:06.68#ibcon#flushed, iclass 40, count 2 2006.201.20:48:06.68#ibcon#about to write, iclass 40, count 2 2006.201.20:48:06.68#ibcon#wrote, iclass 40, count 2 2006.201.20:48:06.68#ibcon#about to read 3, iclass 40, count 2 2006.201.20:48:06.71#ibcon#read 3, iclass 40, count 2 2006.201.20:48:06.71#ibcon#about to read 4, iclass 40, count 2 2006.201.20:48:06.71#ibcon#read 4, iclass 40, count 2 2006.201.20:48:06.71#ibcon#about to read 5, iclass 40, count 2 2006.201.20:48:06.71#ibcon#read 5, iclass 40, count 2 2006.201.20:48:06.71#ibcon#about to read 6, iclass 40, count 2 2006.201.20:48:06.71#ibcon#read 6, iclass 40, count 2 2006.201.20:48:06.71#ibcon#end of sib2, iclass 40, count 2 2006.201.20:48:06.71#ibcon#*after write, iclass 40, count 2 2006.201.20:48:06.71#ibcon#*before return 0, iclass 40, count 2 2006.201.20:48:06.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:48:06.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.20:48:06.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.20:48:06.71#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:06.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:48:06.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:48:06.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:48:06.83#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:48:06.83#ibcon#first serial, iclass 40, count 0 2006.201.20:48:06.83#ibcon#enter sib2, iclass 40, count 0 2006.201.20:48:06.83#ibcon#flushed, iclass 40, count 0 2006.201.20:48:06.83#ibcon#about to write, iclass 40, count 0 2006.201.20:48:06.83#ibcon#wrote, iclass 40, count 0 2006.201.20:48:06.83#ibcon#about to read 3, iclass 40, count 0 2006.201.20:48:06.85#ibcon#read 3, iclass 40, count 0 2006.201.20:48:06.85#ibcon#about to read 4, iclass 40, count 0 2006.201.20:48:06.85#ibcon#read 4, iclass 40, count 0 2006.201.20:48:06.85#ibcon#about to read 5, iclass 40, count 0 2006.201.20:48:06.85#ibcon#read 5, iclass 40, count 0 2006.201.20:48:06.85#ibcon#about to read 6, iclass 40, count 0 2006.201.20:48:06.85#ibcon#read 6, iclass 40, count 0 2006.201.20:48:06.85#ibcon#end of sib2, iclass 40, count 0 2006.201.20:48:06.85#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:48:06.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:48:06.85#ibcon#[27=USB\r\n] 2006.201.20:48:06.85#ibcon#*before write, iclass 40, count 0 2006.201.20:48:06.85#ibcon#enter sib2, iclass 40, count 0 2006.201.20:48:06.85#ibcon#flushed, iclass 40, count 0 2006.201.20:48:06.85#ibcon#about to write, iclass 40, count 0 2006.201.20:48:06.85#ibcon#wrote, iclass 40, count 0 2006.201.20:48:06.85#ibcon#about to read 3, iclass 40, count 0 2006.201.20:48:06.88#ibcon#read 3, iclass 40, count 0 2006.201.20:48:06.88#ibcon#about to read 4, iclass 40, count 0 2006.201.20:48:06.88#ibcon#read 4, iclass 40, count 0 2006.201.20:48:06.88#ibcon#about to read 5, iclass 40, count 0 2006.201.20:48:06.88#ibcon#read 5, iclass 40, count 0 2006.201.20:48:06.88#ibcon#about to read 6, iclass 40, count 0 2006.201.20:48:06.88#ibcon#read 6, iclass 40, count 0 2006.201.20:48:06.88#ibcon#end of sib2, iclass 40, count 0 2006.201.20:48:06.88#ibcon#*after write, iclass 40, count 0 2006.201.20:48:06.88#ibcon#*before return 0, iclass 40, count 0 2006.201.20:48:06.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:48:06.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.20:48:06.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:48:06.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:48:06.88$vck44/vblo=2,634.99 2006.201.20:48:06.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.20:48:06.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.20:48:06.88#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:06.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:06.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:06.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:06.88#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:48:06.88#ibcon#first serial, iclass 4, count 0 2006.201.20:48:06.88#ibcon#enter sib2, iclass 4, count 0 2006.201.20:48:06.88#ibcon#flushed, iclass 4, count 0 2006.201.20:48:06.88#ibcon#about to write, iclass 4, count 0 2006.201.20:48:06.88#ibcon#wrote, iclass 4, count 0 2006.201.20:48:06.88#ibcon#about to read 3, iclass 4, count 0 2006.201.20:48:06.90#ibcon#read 3, iclass 4, count 0 2006.201.20:48:06.90#ibcon#about to read 4, iclass 4, count 0 2006.201.20:48:06.90#ibcon#read 4, iclass 4, count 0 2006.201.20:48:06.90#ibcon#about to read 5, iclass 4, count 0 2006.201.20:48:06.90#ibcon#read 5, iclass 4, count 0 2006.201.20:48:06.90#ibcon#about to read 6, iclass 4, count 0 2006.201.20:48:06.90#ibcon#read 6, iclass 4, count 0 2006.201.20:48:06.90#ibcon#end of sib2, iclass 4, count 0 2006.201.20:48:06.90#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:48:06.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:48:06.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:48:06.90#ibcon#*before write, iclass 4, count 0 2006.201.20:48:06.90#ibcon#enter sib2, iclass 4, count 0 2006.201.20:48:06.90#ibcon#flushed, iclass 4, count 0 2006.201.20:48:06.90#ibcon#about to write, iclass 4, count 0 2006.201.20:48:06.90#ibcon#wrote, iclass 4, count 0 2006.201.20:48:06.90#ibcon#about to read 3, iclass 4, count 0 2006.201.20:48:06.94#ibcon#read 3, iclass 4, count 0 2006.201.20:48:06.94#ibcon#about to read 4, iclass 4, count 0 2006.201.20:48:06.94#ibcon#read 4, iclass 4, count 0 2006.201.20:48:06.94#ibcon#about to read 5, iclass 4, count 0 2006.201.20:48:06.94#ibcon#read 5, iclass 4, count 0 2006.201.20:48:06.94#ibcon#about to read 6, iclass 4, count 0 2006.201.20:48:06.94#ibcon#read 6, iclass 4, count 0 2006.201.20:48:06.94#ibcon#end of sib2, iclass 4, count 0 2006.201.20:48:06.94#ibcon#*after write, iclass 4, count 0 2006.201.20:48:06.94#ibcon#*before return 0, iclass 4, count 0 2006.201.20:48:06.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:06.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.20:48:06.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:48:06.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:48:06.94$vck44/vb=2,5 2006.201.20:48:06.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.20:48:06.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.20:48:06.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:06.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:07.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:07.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:07.00#ibcon#enter wrdev, iclass 6, count 2 2006.201.20:48:07.00#ibcon#first serial, iclass 6, count 2 2006.201.20:48:07.00#ibcon#enter sib2, iclass 6, count 2 2006.201.20:48:07.00#ibcon#flushed, iclass 6, count 2 2006.201.20:48:07.00#ibcon#about to write, iclass 6, count 2 2006.201.20:48:07.00#ibcon#wrote, iclass 6, count 2 2006.201.20:48:07.00#ibcon#about to read 3, iclass 6, count 2 2006.201.20:48:07.02#ibcon#read 3, iclass 6, count 2 2006.201.20:48:07.02#ibcon#about to read 4, iclass 6, count 2 2006.201.20:48:07.02#ibcon#read 4, iclass 6, count 2 2006.201.20:48:07.02#ibcon#about to read 5, iclass 6, count 2 2006.201.20:48:07.02#ibcon#read 5, iclass 6, count 2 2006.201.20:48:07.02#ibcon#about to read 6, iclass 6, count 2 2006.201.20:48:07.02#ibcon#read 6, iclass 6, count 2 2006.201.20:48:07.02#ibcon#end of sib2, iclass 6, count 2 2006.201.20:48:07.02#ibcon#*mode == 0, iclass 6, count 2 2006.201.20:48:07.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.20:48:07.02#ibcon#[27=AT02-05\r\n] 2006.201.20:48:07.02#ibcon#*before write, iclass 6, count 2 2006.201.20:48:07.02#ibcon#enter sib2, iclass 6, count 2 2006.201.20:48:07.02#ibcon#flushed, iclass 6, count 2 2006.201.20:48:07.02#ibcon#about to write, iclass 6, count 2 2006.201.20:48:07.02#ibcon#wrote, iclass 6, count 2 2006.201.20:48:07.02#ibcon#about to read 3, iclass 6, count 2 2006.201.20:48:07.05#ibcon#read 3, iclass 6, count 2 2006.201.20:48:07.05#ibcon#about to read 4, iclass 6, count 2 2006.201.20:48:07.05#ibcon#read 4, iclass 6, count 2 2006.201.20:48:07.05#ibcon#about to read 5, iclass 6, count 2 2006.201.20:48:07.05#ibcon#read 5, iclass 6, count 2 2006.201.20:48:07.05#ibcon#about to read 6, iclass 6, count 2 2006.201.20:48:07.05#ibcon#read 6, iclass 6, count 2 2006.201.20:48:07.05#ibcon#end of sib2, iclass 6, count 2 2006.201.20:48:07.05#ibcon#*after write, iclass 6, count 2 2006.201.20:48:07.05#ibcon#*before return 0, iclass 6, count 2 2006.201.20:48:07.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:07.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.20:48:07.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.20:48:07.05#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:07.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:07.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:07.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:07.17#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:48:07.17#ibcon#first serial, iclass 6, count 0 2006.201.20:48:07.17#ibcon#enter sib2, iclass 6, count 0 2006.201.20:48:07.17#ibcon#flushed, iclass 6, count 0 2006.201.20:48:07.17#ibcon#about to write, iclass 6, count 0 2006.201.20:48:07.17#ibcon#wrote, iclass 6, count 0 2006.201.20:48:07.17#ibcon#about to read 3, iclass 6, count 0 2006.201.20:48:07.19#ibcon#read 3, iclass 6, count 0 2006.201.20:48:07.19#ibcon#about to read 4, iclass 6, count 0 2006.201.20:48:07.19#ibcon#read 4, iclass 6, count 0 2006.201.20:48:07.19#ibcon#about to read 5, iclass 6, count 0 2006.201.20:48:07.19#ibcon#read 5, iclass 6, count 0 2006.201.20:48:07.19#ibcon#about to read 6, iclass 6, count 0 2006.201.20:48:07.19#ibcon#read 6, iclass 6, count 0 2006.201.20:48:07.19#ibcon#end of sib2, iclass 6, count 0 2006.201.20:48:07.19#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:48:07.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:48:07.19#ibcon#[27=USB\r\n] 2006.201.20:48:07.19#ibcon#*before write, iclass 6, count 0 2006.201.20:48:07.19#ibcon#enter sib2, iclass 6, count 0 2006.201.20:48:07.19#ibcon#flushed, iclass 6, count 0 2006.201.20:48:07.19#ibcon#about to write, iclass 6, count 0 2006.201.20:48:07.19#ibcon#wrote, iclass 6, count 0 2006.201.20:48:07.19#ibcon#about to read 3, iclass 6, count 0 2006.201.20:48:07.22#ibcon#read 3, iclass 6, count 0 2006.201.20:48:07.22#ibcon#about to read 4, iclass 6, count 0 2006.201.20:48:07.22#ibcon#read 4, iclass 6, count 0 2006.201.20:48:07.22#ibcon#about to read 5, iclass 6, count 0 2006.201.20:48:07.22#ibcon#read 5, iclass 6, count 0 2006.201.20:48:07.22#ibcon#about to read 6, iclass 6, count 0 2006.201.20:48:07.22#ibcon#read 6, iclass 6, count 0 2006.201.20:48:07.22#ibcon#end of sib2, iclass 6, count 0 2006.201.20:48:07.22#ibcon#*after write, iclass 6, count 0 2006.201.20:48:07.22#ibcon#*before return 0, iclass 6, count 0 2006.201.20:48:07.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:07.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.20:48:07.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:48:07.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:48:07.22$vck44/vblo=3,649.99 2006.201.20:48:07.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.20:48:07.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.20:48:07.22#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:07.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:07.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:07.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:07.22#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:48:07.22#ibcon#first serial, iclass 10, count 0 2006.201.20:48:07.22#ibcon#enter sib2, iclass 10, count 0 2006.201.20:48:07.22#ibcon#flushed, iclass 10, count 0 2006.201.20:48:07.22#ibcon#about to write, iclass 10, count 0 2006.201.20:48:07.22#ibcon#wrote, iclass 10, count 0 2006.201.20:48:07.22#ibcon#about to read 3, iclass 10, count 0 2006.201.20:48:07.24#ibcon#read 3, iclass 10, count 0 2006.201.20:48:07.24#ibcon#about to read 4, iclass 10, count 0 2006.201.20:48:07.24#ibcon#read 4, iclass 10, count 0 2006.201.20:48:07.24#ibcon#about to read 5, iclass 10, count 0 2006.201.20:48:07.24#ibcon#read 5, iclass 10, count 0 2006.201.20:48:07.24#ibcon#about to read 6, iclass 10, count 0 2006.201.20:48:07.24#ibcon#read 6, iclass 10, count 0 2006.201.20:48:07.24#ibcon#end of sib2, iclass 10, count 0 2006.201.20:48:07.24#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:48:07.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:48:07.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:48:07.24#ibcon#*before write, iclass 10, count 0 2006.201.20:48:07.24#ibcon#enter sib2, iclass 10, count 0 2006.201.20:48:07.24#ibcon#flushed, iclass 10, count 0 2006.201.20:48:07.24#ibcon#about to write, iclass 10, count 0 2006.201.20:48:07.24#ibcon#wrote, iclass 10, count 0 2006.201.20:48:07.24#ibcon#about to read 3, iclass 10, count 0 2006.201.20:48:07.28#ibcon#read 3, iclass 10, count 0 2006.201.20:48:07.28#ibcon#about to read 4, iclass 10, count 0 2006.201.20:48:07.28#ibcon#read 4, iclass 10, count 0 2006.201.20:48:07.28#ibcon#about to read 5, iclass 10, count 0 2006.201.20:48:07.28#ibcon#read 5, iclass 10, count 0 2006.201.20:48:07.28#ibcon#about to read 6, iclass 10, count 0 2006.201.20:48:07.28#ibcon#read 6, iclass 10, count 0 2006.201.20:48:07.28#ibcon#end of sib2, iclass 10, count 0 2006.201.20:48:07.28#ibcon#*after write, iclass 10, count 0 2006.201.20:48:07.28#ibcon#*before return 0, iclass 10, count 0 2006.201.20:48:07.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:07.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.20:48:07.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:48:07.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:48:07.28$vck44/vb=3,4 2006.201.20:48:07.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.20:48:07.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.20:48:07.28#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:07.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:07.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:07.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:07.34#ibcon#enter wrdev, iclass 12, count 2 2006.201.20:48:07.34#ibcon#first serial, iclass 12, count 2 2006.201.20:48:07.34#ibcon#enter sib2, iclass 12, count 2 2006.201.20:48:07.34#ibcon#flushed, iclass 12, count 2 2006.201.20:48:07.34#ibcon#about to write, iclass 12, count 2 2006.201.20:48:07.34#ibcon#wrote, iclass 12, count 2 2006.201.20:48:07.34#ibcon#about to read 3, iclass 12, count 2 2006.201.20:48:07.36#ibcon#read 3, iclass 12, count 2 2006.201.20:48:07.36#ibcon#about to read 4, iclass 12, count 2 2006.201.20:48:07.36#ibcon#read 4, iclass 12, count 2 2006.201.20:48:07.36#ibcon#about to read 5, iclass 12, count 2 2006.201.20:48:07.36#ibcon#read 5, iclass 12, count 2 2006.201.20:48:07.36#ibcon#about to read 6, iclass 12, count 2 2006.201.20:48:07.36#ibcon#read 6, iclass 12, count 2 2006.201.20:48:07.36#ibcon#end of sib2, iclass 12, count 2 2006.201.20:48:07.36#ibcon#*mode == 0, iclass 12, count 2 2006.201.20:48:07.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.20:48:07.36#ibcon#[27=AT03-04\r\n] 2006.201.20:48:07.36#ibcon#*before write, iclass 12, count 2 2006.201.20:48:07.36#ibcon#enter sib2, iclass 12, count 2 2006.201.20:48:07.36#ibcon#flushed, iclass 12, count 2 2006.201.20:48:07.36#ibcon#about to write, iclass 12, count 2 2006.201.20:48:07.36#ibcon#wrote, iclass 12, count 2 2006.201.20:48:07.36#ibcon#about to read 3, iclass 12, count 2 2006.201.20:48:07.39#ibcon#read 3, iclass 12, count 2 2006.201.20:48:07.39#ibcon#about to read 4, iclass 12, count 2 2006.201.20:48:07.39#ibcon#read 4, iclass 12, count 2 2006.201.20:48:07.39#ibcon#about to read 5, iclass 12, count 2 2006.201.20:48:07.39#ibcon#read 5, iclass 12, count 2 2006.201.20:48:07.39#ibcon#about to read 6, iclass 12, count 2 2006.201.20:48:07.39#ibcon#read 6, iclass 12, count 2 2006.201.20:48:07.39#ibcon#end of sib2, iclass 12, count 2 2006.201.20:48:07.39#ibcon#*after write, iclass 12, count 2 2006.201.20:48:07.39#ibcon#*before return 0, iclass 12, count 2 2006.201.20:48:07.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:07.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.20:48:07.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.20:48:07.39#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:07.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:07.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:07.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:07.51#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:48:07.51#ibcon#first serial, iclass 12, count 0 2006.201.20:48:07.51#ibcon#enter sib2, iclass 12, count 0 2006.201.20:48:07.51#ibcon#flushed, iclass 12, count 0 2006.201.20:48:07.51#ibcon#about to write, iclass 12, count 0 2006.201.20:48:07.51#ibcon#wrote, iclass 12, count 0 2006.201.20:48:07.51#ibcon#about to read 3, iclass 12, count 0 2006.201.20:48:07.53#ibcon#read 3, iclass 12, count 0 2006.201.20:48:07.53#ibcon#about to read 4, iclass 12, count 0 2006.201.20:48:07.53#ibcon#read 4, iclass 12, count 0 2006.201.20:48:07.53#ibcon#about to read 5, iclass 12, count 0 2006.201.20:48:07.53#ibcon#read 5, iclass 12, count 0 2006.201.20:48:07.53#ibcon#about to read 6, iclass 12, count 0 2006.201.20:48:07.53#ibcon#read 6, iclass 12, count 0 2006.201.20:48:07.53#ibcon#end of sib2, iclass 12, count 0 2006.201.20:48:07.53#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:48:07.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:48:07.53#ibcon#[27=USB\r\n] 2006.201.20:48:07.53#ibcon#*before write, iclass 12, count 0 2006.201.20:48:07.53#ibcon#enter sib2, iclass 12, count 0 2006.201.20:48:07.53#ibcon#flushed, iclass 12, count 0 2006.201.20:48:07.53#ibcon#about to write, iclass 12, count 0 2006.201.20:48:07.53#ibcon#wrote, iclass 12, count 0 2006.201.20:48:07.53#ibcon#about to read 3, iclass 12, count 0 2006.201.20:48:07.56#ibcon#read 3, iclass 12, count 0 2006.201.20:48:07.56#ibcon#about to read 4, iclass 12, count 0 2006.201.20:48:07.56#ibcon#read 4, iclass 12, count 0 2006.201.20:48:07.56#ibcon#about to read 5, iclass 12, count 0 2006.201.20:48:07.56#ibcon#read 5, iclass 12, count 0 2006.201.20:48:07.56#ibcon#about to read 6, iclass 12, count 0 2006.201.20:48:07.56#ibcon#read 6, iclass 12, count 0 2006.201.20:48:07.56#ibcon#end of sib2, iclass 12, count 0 2006.201.20:48:07.56#ibcon#*after write, iclass 12, count 0 2006.201.20:48:07.56#ibcon#*before return 0, iclass 12, count 0 2006.201.20:48:07.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:07.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.20:48:07.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:48:07.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:48:07.56$vck44/vblo=4,679.99 2006.201.20:48:07.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.20:48:07.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.20:48:07.56#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:07.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:07.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:07.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:07.56#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:48:07.56#ibcon#first serial, iclass 14, count 0 2006.201.20:48:07.56#ibcon#enter sib2, iclass 14, count 0 2006.201.20:48:07.56#ibcon#flushed, iclass 14, count 0 2006.201.20:48:07.56#ibcon#about to write, iclass 14, count 0 2006.201.20:48:07.56#ibcon#wrote, iclass 14, count 0 2006.201.20:48:07.56#ibcon#about to read 3, iclass 14, count 0 2006.201.20:48:07.58#ibcon#read 3, iclass 14, count 0 2006.201.20:48:07.58#ibcon#about to read 4, iclass 14, count 0 2006.201.20:48:07.58#ibcon#read 4, iclass 14, count 0 2006.201.20:48:07.58#ibcon#about to read 5, iclass 14, count 0 2006.201.20:48:07.58#ibcon#read 5, iclass 14, count 0 2006.201.20:48:07.58#ibcon#about to read 6, iclass 14, count 0 2006.201.20:48:07.58#ibcon#read 6, iclass 14, count 0 2006.201.20:48:07.58#ibcon#end of sib2, iclass 14, count 0 2006.201.20:48:07.58#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:48:07.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:48:07.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:48:07.58#ibcon#*before write, iclass 14, count 0 2006.201.20:48:07.58#ibcon#enter sib2, iclass 14, count 0 2006.201.20:48:07.58#ibcon#flushed, iclass 14, count 0 2006.201.20:48:07.58#ibcon#about to write, iclass 14, count 0 2006.201.20:48:07.58#ibcon#wrote, iclass 14, count 0 2006.201.20:48:07.58#ibcon#about to read 3, iclass 14, count 0 2006.201.20:48:07.63#ibcon#read 3, iclass 14, count 0 2006.201.20:48:07.63#ibcon#about to read 4, iclass 14, count 0 2006.201.20:48:07.63#ibcon#read 4, iclass 14, count 0 2006.201.20:48:07.63#ibcon#about to read 5, iclass 14, count 0 2006.201.20:48:07.63#ibcon#read 5, iclass 14, count 0 2006.201.20:48:07.63#ibcon#about to read 6, iclass 14, count 0 2006.201.20:48:07.63#ibcon#read 6, iclass 14, count 0 2006.201.20:48:07.63#ibcon#end of sib2, iclass 14, count 0 2006.201.20:48:07.63#ibcon#*after write, iclass 14, count 0 2006.201.20:48:07.63#ibcon#*before return 0, iclass 14, count 0 2006.201.20:48:07.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:07.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.20:48:07.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:48:07.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:48:07.63$vck44/vb=4,5 2006.201.20:48:07.63#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.20:48:07.63#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.20:48:07.63#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:07.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:07.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:07.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:07.68#ibcon#enter wrdev, iclass 16, count 2 2006.201.20:48:07.68#ibcon#first serial, iclass 16, count 2 2006.201.20:48:07.68#ibcon#enter sib2, iclass 16, count 2 2006.201.20:48:07.68#ibcon#flushed, iclass 16, count 2 2006.201.20:48:07.68#ibcon#about to write, iclass 16, count 2 2006.201.20:48:07.68#ibcon#wrote, iclass 16, count 2 2006.201.20:48:07.68#ibcon#about to read 3, iclass 16, count 2 2006.201.20:48:07.70#ibcon#read 3, iclass 16, count 2 2006.201.20:48:07.70#ibcon#about to read 4, iclass 16, count 2 2006.201.20:48:07.70#ibcon#read 4, iclass 16, count 2 2006.201.20:48:07.70#ibcon#about to read 5, iclass 16, count 2 2006.201.20:48:07.70#ibcon#read 5, iclass 16, count 2 2006.201.20:48:07.70#ibcon#about to read 6, iclass 16, count 2 2006.201.20:48:07.70#ibcon#read 6, iclass 16, count 2 2006.201.20:48:07.70#ibcon#end of sib2, iclass 16, count 2 2006.201.20:48:07.70#ibcon#*mode == 0, iclass 16, count 2 2006.201.20:48:07.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.20:48:07.70#ibcon#[27=AT04-05\r\n] 2006.201.20:48:07.70#ibcon#*before write, iclass 16, count 2 2006.201.20:48:07.70#ibcon#enter sib2, iclass 16, count 2 2006.201.20:48:07.70#ibcon#flushed, iclass 16, count 2 2006.201.20:48:07.70#ibcon#about to write, iclass 16, count 2 2006.201.20:48:07.70#ibcon#wrote, iclass 16, count 2 2006.201.20:48:07.70#ibcon#about to read 3, iclass 16, count 2 2006.201.20:48:07.73#ibcon#read 3, iclass 16, count 2 2006.201.20:48:07.73#ibcon#about to read 4, iclass 16, count 2 2006.201.20:48:07.73#ibcon#read 4, iclass 16, count 2 2006.201.20:48:07.73#ibcon#about to read 5, iclass 16, count 2 2006.201.20:48:07.73#ibcon#read 5, iclass 16, count 2 2006.201.20:48:07.73#ibcon#about to read 6, iclass 16, count 2 2006.201.20:48:07.73#ibcon#read 6, iclass 16, count 2 2006.201.20:48:07.73#ibcon#end of sib2, iclass 16, count 2 2006.201.20:48:07.73#ibcon#*after write, iclass 16, count 2 2006.201.20:48:07.73#ibcon#*before return 0, iclass 16, count 2 2006.201.20:48:07.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:07.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.20:48:07.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.20:48:07.73#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:07.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:07.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:07.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:07.85#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:48:07.85#ibcon#first serial, iclass 16, count 0 2006.201.20:48:07.85#ibcon#enter sib2, iclass 16, count 0 2006.201.20:48:07.85#ibcon#flushed, iclass 16, count 0 2006.201.20:48:07.85#ibcon#about to write, iclass 16, count 0 2006.201.20:48:07.85#ibcon#wrote, iclass 16, count 0 2006.201.20:48:07.85#ibcon#about to read 3, iclass 16, count 0 2006.201.20:48:07.87#ibcon#read 3, iclass 16, count 0 2006.201.20:48:07.87#ibcon#about to read 4, iclass 16, count 0 2006.201.20:48:07.87#ibcon#read 4, iclass 16, count 0 2006.201.20:48:07.87#ibcon#about to read 5, iclass 16, count 0 2006.201.20:48:07.87#ibcon#read 5, iclass 16, count 0 2006.201.20:48:07.87#ibcon#about to read 6, iclass 16, count 0 2006.201.20:48:07.87#ibcon#read 6, iclass 16, count 0 2006.201.20:48:07.87#ibcon#end of sib2, iclass 16, count 0 2006.201.20:48:07.87#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:48:07.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:48:07.87#ibcon#[27=USB\r\n] 2006.201.20:48:07.87#ibcon#*before write, iclass 16, count 0 2006.201.20:48:07.87#ibcon#enter sib2, iclass 16, count 0 2006.201.20:48:07.87#ibcon#flushed, iclass 16, count 0 2006.201.20:48:07.87#ibcon#about to write, iclass 16, count 0 2006.201.20:48:07.87#ibcon#wrote, iclass 16, count 0 2006.201.20:48:07.87#ibcon#about to read 3, iclass 16, count 0 2006.201.20:48:07.90#ibcon#read 3, iclass 16, count 0 2006.201.20:48:07.90#ibcon#about to read 4, iclass 16, count 0 2006.201.20:48:07.90#ibcon#read 4, iclass 16, count 0 2006.201.20:48:07.90#ibcon#about to read 5, iclass 16, count 0 2006.201.20:48:07.90#ibcon#read 5, iclass 16, count 0 2006.201.20:48:07.90#ibcon#about to read 6, iclass 16, count 0 2006.201.20:48:07.90#ibcon#read 6, iclass 16, count 0 2006.201.20:48:07.90#ibcon#end of sib2, iclass 16, count 0 2006.201.20:48:07.90#ibcon#*after write, iclass 16, count 0 2006.201.20:48:07.90#ibcon#*before return 0, iclass 16, count 0 2006.201.20:48:07.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:07.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.20:48:07.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:48:07.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:48:07.90$vck44/vblo=5,709.99 2006.201.20:48:07.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.20:48:07.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.20:48:07.90#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:07.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:07.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:07.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:07.90#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:48:07.90#ibcon#first serial, iclass 18, count 0 2006.201.20:48:07.90#ibcon#enter sib2, iclass 18, count 0 2006.201.20:48:07.90#ibcon#flushed, iclass 18, count 0 2006.201.20:48:07.90#ibcon#about to write, iclass 18, count 0 2006.201.20:48:07.90#ibcon#wrote, iclass 18, count 0 2006.201.20:48:07.90#ibcon#about to read 3, iclass 18, count 0 2006.201.20:48:07.92#ibcon#read 3, iclass 18, count 0 2006.201.20:48:07.92#ibcon#about to read 4, iclass 18, count 0 2006.201.20:48:07.92#ibcon#read 4, iclass 18, count 0 2006.201.20:48:07.92#ibcon#about to read 5, iclass 18, count 0 2006.201.20:48:07.92#ibcon#read 5, iclass 18, count 0 2006.201.20:48:07.92#ibcon#about to read 6, iclass 18, count 0 2006.201.20:48:07.92#ibcon#read 6, iclass 18, count 0 2006.201.20:48:07.92#ibcon#end of sib2, iclass 18, count 0 2006.201.20:48:07.92#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:48:07.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:48:07.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:48:07.92#ibcon#*before write, iclass 18, count 0 2006.201.20:48:07.92#ibcon#enter sib2, iclass 18, count 0 2006.201.20:48:07.92#ibcon#flushed, iclass 18, count 0 2006.201.20:48:07.92#ibcon#about to write, iclass 18, count 0 2006.201.20:48:07.92#ibcon#wrote, iclass 18, count 0 2006.201.20:48:07.92#ibcon#about to read 3, iclass 18, count 0 2006.201.20:48:07.96#ibcon#read 3, iclass 18, count 0 2006.201.20:48:07.96#ibcon#about to read 4, iclass 18, count 0 2006.201.20:48:07.96#ibcon#read 4, iclass 18, count 0 2006.201.20:48:07.96#ibcon#about to read 5, iclass 18, count 0 2006.201.20:48:07.96#ibcon#read 5, iclass 18, count 0 2006.201.20:48:07.96#ibcon#about to read 6, iclass 18, count 0 2006.201.20:48:07.96#ibcon#read 6, iclass 18, count 0 2006.201.20:48:07.96#ibcon#end of sib2, iclass 18, count 0 2006.201.20:48:07.96#ibcon#*after write, iclass 18, count 0 2006.201.20:48:07.96#ibcon#*before return 0, iclass 18, count 0 2006.201.20:48:07.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:07.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.20:48:07.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:48:07.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:48:07.96$vck44/vb=5,4 2006.201.20:48:07.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.20:48:07.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.20:48:07.96#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:07.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:08.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:08.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:08.02#ibcon#enter wrdev, iclass 20, count 2 2006.201.20:48:08.02#ibcon#first serial, iclass 20, count 2 2006.201.20:48:08.02#ibcon#enter sib2, iclass 20, count 2 2006.201.20:48:08.02#ibcon#flushed, iclass 20, count 2 2006.201.20:48:08.02#ibcon#about to write, iclass 20, count 2 2006.201.20:48:08.02#ibcon#wrote, iclass 20, count 2 2006.201.20:48:08.02#ibcon#about to read 3, iclass 20, count 2 2006.201.20:48:08.04#ibcon#read 3, iclass 20, count 2 2006.201.20:48:08.04#ibcon#about to read 4, iclass 20, count 2 2006.201.20:48:08.04#ibcon#read 4, iclass 20, count 2 2006.201.20:48:08.04#ibcon#about to read 5, iclass 20, count 2 2006.201.20:48:08.04#ibcon#read 5, iclass 20, count 2 2006.201.20:48:08.04#ibcon#about to read 6, iclass 20, count 2 2006.201.20:48:08.04#ibcon#read 6, iclass 20, count 2 2006.201.20:48:08.04#ibcon#end of sib2, iclass 20, count 2 2006.201.20:48:08.04#ibcon#*mode == 0, iclass 20, count 2 2006.201.20:48:08.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.20:48:08.04#ibcon#[27=AT05-04\r\n] 2006.201.20:48:08.04#ibcon#*before write, iclass 20, count 2 2006.201.20:48:08.04#ibcon#enter sib2, iclass 20, count 2 2006.201.20:48:08.04#ibcon#flushed, iclass 20, count 2 2006.201.20:48:08.04#ibcon#about to write, iclass 20, count 2 2006.201.20:48:08.04#ibcon#wrote, iclass 20, count 2 2006.201.20:48:08.04#ibcon#about to read 3, iclass 20, count 2 2006.201.20:48:08.07#ibcon#read 3, iclass 20, count 2 2006.201.20:48:08.07#ibcon#about to read 4, iclass 20, count 2 2006.201.20:48:08.07#ibcon#read 4, iclass 20, count 2 2006.201.20:48:08.07#ibcon#about to read 5, iclass 20, count 2 2006.201.20:48:08.07#ibcon#read 5, iclass 20, count 2 2006.201.20:48:08.07#ibcon#about to read 6, iclass 20, count 2 2006.201.20:48:08.07#ibcon#read 6, iclass 20, count 2 2006.201.20:48:08.07#ibcon#end of sib2, iclass 20, count 2 2006.201.20:48:08.07#ibcon#*after write, iclass 20, count 2 2006.201.20:48:08.07#ibcon#*before return 0, iclass 20, count 2 2006.201.20:48:08.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:08.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.20:48:08.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.20:48:08.07#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:08.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:08.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:08.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:08.19#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:48:08.19#ibcon#first serial, iclass 20, count 0 2006.201.20:48:08.19#ibcon#enter sib2, iclass 20, count 0 2006.201.20:48:08.19#ibcon#flushed, iclass 20, count 0 2006.201.20:48:08.19#ibcon#about to write, iclass 20, count 0 2006.201.20:48:08.19#ibcon#wrote, iclass 20, count 0 2006.201.20:48:08.19#ibcon#about to read 3, iclass 20, count 0 2006.201.20:48:08.22#ibcon#read 3, iclass 20, count 0 2006.201.20:48:08.22#ibcon#about to read 4, iclass 20, count 0 2006.201.20:48:08.22#ibcon#read 4, iclass 20, count 0 2006.201.20:48:08.22#ibcon#about to read 5, iclass 20, count 0 2006.201.20:48:08.22#ibcon#read 5, iclass 20, count 0 2006.201.20:48:08.22#ibcon#about to read 6, iclass 20, count 0 2006.201.20:48:08.22#ibcon#read 6, iclass 20, count 0 2006.201.20:48:08.22#ibcon#end of sib2, iclass 20, count 0 2006.201.20:48:08.22#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:48:08.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:48:08.22#ibcon#[27=USB\r\n] 2006.201.20:48:08.22#ibcon#*before write, iclass 20, count 0 2006.201.20:48:08.22#ibcon#enter sib2, iclass 20, count 0 2006.201.20:48:08.22#ibcon#flushed, iclass 20, count 0 2006.201.20:48:08.22#ibcon#about to write, iclass 20, count 0 2006.201.20:48:08.22#ibcon#wrote, iclass 20, count 0 2006.201.20:48:08.22#ibcon#about to read 3, iclass 20, count 0 2006.201.20:48:08.25#ibcon#read 3, iclass 20, count 0 2006.201.20:48:08.25#ibcon#about to read 4, iclass 20, count 0 2006.201.20:48:08.25#ibcon#read 4, iclass 20, count 0 2006.201.20:48:08.25#ibcon#about to read 5, iclass 20, count 0 2006.201.20:48:08.25#ibcon#read 5, iclass 20, count 0 2006.201.20:48:08.25#ibcon#about to read 6, iclass 20, count 0 2006.201.20:48:08.25#ibcon#read 6, iclass 20, count 0 2006.201.20:48:08.25#ibcon#end of sib2, iclass 20, count 0 2006.201.20:48:08.25#ibcon#*after write, iclass 20, count 0 2006.201.20:48:08.25#ibcon#*before return 0, iclass 20, count 0 2006.201.20:48:08.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:08.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.20:48:08.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:48:08.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:48:08.25$vck44/vblo=6,719.99 2006.201.20:48:08.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.20:48:08.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.20:48:08.25#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:08.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:48:08.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:48:08.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:48:08.25#ibcon#enter wrdev, iclass 23, count 0 2006.201.20:48:08.25#ibcon#first serial, iclass 23, count 0 2006.201.20:48:08.25#ibcon#enter sib2, iclass 23, count 0 2006.201.20:48:08.25#ibcon#flushed, iclass 23, count 0 2006.201.20:48:08.25#ibcon#about to write, iclass 23, count 0 2006.201.20:48:08.25#ibcon#wrote, iclass 23, count 0 2006.201.20:48:08.25#ibcon#about to read 3, iclass 23, count 0 2006.201.20:48:08.27#ibcon#read 3, iclass 23, count 0 2006.201.20:48:08.27#ibcon#about to read 4, iclass 23, count 0 2006.201.20:48:08.27#ibcon#read 4, iclass 23, count 0 2006.201.20:48:08.27#ibcon#about to read 5, iclass 23, count 0 2006.201.20:48:08.27#ibcon#read 5, iclass 23, count 0 2006.201.20:48:08.27#ibcon#about to read 6, iclass 23, count 0 2006.201.20:48:08.27#ibcon#read 6, iclass 23, count 0 2006.201.20:48:08.27#ibcon#end of sib2, iclass 23, count 0 2006.201.20:48:08.27#ibcon#*mode == 0, iclass 23, count 0 2006.201.20:48:08.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.20:48:08.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:48:08.27#ibcon#*before write, iclass 23, count 0 2006.201.20:48:08.27#ibcon#enter sib2, iclass 23, count 0 2006.201.20:48:08.27#ibcon#flushed, iclass 23, count 0 2006.201.20:48:08.27#ibcon#about to write, iclass 23, count 0 2006.201.20:48:08.27#ibcon#wrote, iclass 23, count 0 2006.201.20:48:08.27#ibcon#about to read 3, iclass 23, count 0 2006.201.20:48:08.29#abcon#<5=/05 0.4 1.2 20.131001002.5\r\n> 2006.201.20:48:08.31#abcon#{5=INTERFACE CLEAR} 2006.201.20:48:08.31#ibcon#read 3, iclass 23, count 0 2006.201.20:48:08.31#ibcon#about to read 4, iclass 23, count 0 2006.201.20:48:08.31#ibcon#read 4, iclass 23, count 0 2006.201.20:48:08.31#ibcon#about to read 5, iclass 23, count 0 2006.201.20:48:08.31#ibcon#read 5, iclass 23, count 0 2006.201.20:48:08.31#ibcon#about to read 6, iclass 23, count 0 2006.201.20:48:08.31#ibcon#read 6, iclass 23, count 0 2006.201.20:48:08.31#ibcon#end of sib2, iclass 23, count 0 2006.201.20:48:08.31#ibcon#*after write, iclass 23, count 0 2006.201.20:48:08.31#ibcon#*before return 0, iclass 23, count 0 2006.201.20:48:08.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:48:08.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.20:48:08.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.20:48:08.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.20:48:08.31$vck44/vb=6,4 2006.201.20:48:08.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.20:48:08.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.20:48:08.31#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:08.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:48:08.37#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:48:08.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:48:08.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:48:08.37#ibcon#enter wrdev, iclass 27, count 2 2006.201.20:48:08.37#ibcon#first serial, iclass 27, count 2 2006.201.20:48:08.37#ibcon#enter sib2, iclass 27, count 2 2006.201.20:48:08.37#ibcon#flushed, iclass 27, count 2 2006.201.20:48:08.37#ibcon#about to write, iclass 27, count 2 2006.201.20:48:08.37#ibcon#wrote, iclass 27, count 2 2006.201.20:48:08.37#ibcon#about to read 3, iclass 27, count 2 2006.201.20:48:08.39#ibcon#read 3, iclass 27, count 2 2006.201.20:48:08.39#ibcon#about to read 4, iclass 27, count 2 2006.201.20:48:08.39#ibcon#read 4, iclass 27, count 2 2006.201.20:48:08.39#ibcon#about to read 5, iclass 27, count 2 2006.201.20:48:08.39#ibcon#read 5, iclass 27, count 2 2006.201.20:48:08.39#ibcon#about to read 6, iclass 27, count 2 2006.201.20:48:08.39#ibcon#read 6, iclass 27, count 2 2006.201.20:48:08.39#ibcon#end of sib2, iclass 27, count 2 2006.201.20:48:08.39#ibcon#*mode == 0, iclass 27, count 2 2006.201.20:48:08.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.20:48:08.39#ibcon#[27=AT06-04\r\n] 2006.201.20:48:08.39#ibcon#*before write, iclass 27, count 2 2006.201.20:48:08.39#ibcon#enter sib2, iclass 27, count 2 2006.201.20:48:08.39#ibcon#flushed, iclass 27, count 2 2006.201.20:48:08.39#ibcon#about to write, iclass 27, count 2 2006.201.20:48:08.39#ibcon#wrote, iclass 27, count 2 2006.201.20:48:08.39#ibcon#about to read 3, iclass 27, count 2 2006.201.20:48:08.42#ibcon#read 3, iclass 27, count 2 2006.201.20:48:08.42#ibcon#about to read 4, iclass 27, count 2 2006.201.20:48:08.42#ibcon#read 4, iclass 27, count 2 2006.201.20:48:08.42#ibcon#about to read 5, iclass 27, count 2 2006.201.20:48:08.42#ibcon#read 5, iclass 27, count 2 2006.201.20:48:08.42#ibcon#about to read 6, iclass 27, count 2 2006.201.20:48:08.42#ibcon#read 6, iclass 27, count 2 2006.201.20:48:08.42#ibcon#end of sib2, iclass 27, count 2 2006.201.20:48:08.42#ibcon#*after write, iclass 27, count 2 2006.201.20:48:08.42#ibcon#*before return 0, iclass 27, count 2 2006.201.20:48:08.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:48:08.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.20:48:08.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.20:48:08.42#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:08.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:48:08.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:48:08.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:48:08.54#ibcon#enter wrdev, iclass 27, count 0 2006.201.20:48:08.54#ibcon#first serial, iclass 27, count 0 2006.201.20:48:08.54#ibcon#enter sib2, iclass 27, count 0 2006.201.20:48:08.54#ibcon#flushed, iclass 27, count 0 2006.201.20:48:08.54#ibcon#about to write, iclass 27, count 0 2006.201.20:48:08.54#ibcon#wrote, iclass 27, count 0 2006.201.20:48:08.54#ibcon#about to read 3, iclass 27, count 0 2006.201.20:48:08.56#ibcon#read 3, iclass 27, count 0 2006.201.20:48:08.56#ibcon#about to read 4, iclass 27, count 0 2006.201.20:48:08.56#ibcon#read 4, iclass 27, count 0 2006.201.20:48:08.56#ibcon#about to read 5, iclass 27, count 0 2006.201.20:48:08.56#ibcon#read 5, iclass 27, count 0 2006.201.20:48:08.56#ibcon#about to read 6, iclass 27, count 0 2006.201.20:48:08.56#ibcon#read 6, iclass 27, count 0 2006.201.20:48:08.56#ibcon#end of sib2, iclass 27, count 0 2006.201.20:48:08.56#ibcon#*mode == 0, iclass 27, count 0 2006.201.20:48:08.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.20:48:08.56#ibcon#[27=USB\r\n] 2006.201.20:48:08.56#ibcon#*before write, iclass 27, count 0 2006.201.20:48:08.56#ibcon#enter sib2, iclass 27, count 0 2006.201.20:48:08.56#ibcon#flushed, iclass 27, count 0 2006.201.20:48:08.56#ibcon#about to write, iclass 27, count 0 2006.201.20:48:08.56#ibcon#wrote, iclass 27, count 0 2006.201.20:48:08.56#ibcon#about to read 3, iclass 27, count 0 2006.201.20:48:08.59#ibcon#read 3, iclass 27, count 0 2006.201.20:48:08.59#ibcon#about to read 4, iclass 27, count 0 2006.201.20:48:08.59#ibcon#read 4, iclass 27, count 0 2006.201.20:48:08.59#ibcon#about to read 5, iclass 27, count 0 2006.201.20:48:08.59#ibcon#read 5, iclass 27, count 0 2006.201.20:48:08.59#ibcon#about to read 6, iclass 27, count 0 2006.201.20:48:08.59#ibcon#read 6, iclass 27, count 0 2006.201.20:48:08.59#ibcon#end of sib2, iclass 27, count 0 2006.201.20:48:08.59#ibcon#*after write, iclass 27, count 0 2006.201.20:48:08.59#ibcon#*before return 0, iclass 27, count 0 2006.201.20:48:08.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:48:08.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.20:48:08.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.20:48:08.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.20:48:08.59$vck44/vblo=7,734.99 2006.201.20:48:08.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.20:48:08.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.20:48:08.59#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:08.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:08.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:08.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:08.59#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:48:08.59#ibcon#first serial, iclass 30, count 0 2006.201.20:48:08.59#ibcon#enter sib2, iclass 30, count 0 2006.201.20:48:08.59#ibcon#flushed, iclass 30, count 0 2006.201.20:48:08.59#ibcon#about to write, iclass 30, count 0 2006.201.20:48:08.59#ibcon#wrote, iclass 30, count 0 2006.201.20:48:08.59#ibcon#about to read 3, iclass 30, count 0 2006.201.20:48:08.61#ibcon#read 3, iclass 30, count 0 2006.201.20:48:08.61#ibcon#about to read 4, iclass 30, count 0 2006.201.20:48:08.61#ibcon#read 4, iclass 30, count 0 2006.201.20:48:08.61#ibcon#about to read 5, iclass 30, count 0 2006.201.20:48:08.61#ibcon#read 5, iclass 30, count 0 2006.201.20:48:08.61#ibcon#about to read 6, iclass 30, count 0 2006.201.20:48:08.61#ibcon#read 6, iclass 30, count 0 2006.201.20:48:08.61#ibcon#end of sib2, iclass 30, count 0 2006.201.20:48:08.61#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:48:08.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:48:08.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:48:08.61#ibcon#*before write, iclass 30, count 0 2006.201.20:48:08.61#ibcon#enter sib2, iclass 30, count 0 2006.201.20:48:08.61#ibcon#flushed, iclass 30, count 0 2006.201.20:48:08.61#ibcon#about to write, iclass 30, count 0 2006.201.20:48:08.61#ibcon#wrote, iclass 30, count 0 2006.201.20:48:08.61#ibcon#about to read 3, iclass 30, count 0 2006.201.20:48:08.65#ibcon#read 3, iclass 30, count 0 2006.201.20:48:08.65#ibcon#about to read 4, iclass 30, count 0 2006.201.20:48:08.65#ibcon#read 4, iclass 30, count 0 2006.201.20:48:08.65#ibcon#about to read 5, iclass 30, count 0 2006.201.20:48:08.65#ibcon#read 5, iclass 30, count 0 2006.201.20:48:08.65#ibcon#about to read 6, iclass 30, count 0 2006.201.20:48:08.65#ibcon#read 6, iclass 30, count 0 2006.201.20:48:08.65#ibcon#end of sib2, iclass 30, count 0 2006.201.20:48:08.65#ibcon#*after write, iclass 30, count 0 2006.201.20:48:08.65#ibcon#*before return 0, iclass 30, count 0 2006.201.20:48:08.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:08.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.20:48:08.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:48:08.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:48:08.65$vck44/vb=7,4 2006.201.20:48:08.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.20:48:08.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.20:48:08.65#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:08.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:08.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:08.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:08.71#ibcon#enter wrdev, iclass 32, count 2 2006.201.20:48:08.71#ibcon#first serial, iclass 32, count 2 2006.201.20:48:08.71#ibcon#enter sib2, iclass 32, count 2 2006.201.20:48:08.71#ibcon#flushed, iclass 32, count 2 2006.201.20:48:08.71#ibcon#about to write, iclass 32, count 2 2006.201.20:48:08.71#ibcon#wrote, iclass 32, count 2 2006.201.20:48:08.71#ibcon#about to read 3, iclass 32, count 2 2006.201.20:48:08.73#ibcon#read 3, iclass 32, count 2 2006.201.20:48:08.73#ibcon#about to read 4, iclass 32, count 2 2006.201.20:48:08.73#ibcon#read 4, iclass 32, count 2 2006.201.20:48:08.73#ibcon#about to read 5, iclass 32, count 2 2006.201.20:48:08.73#ibcon#read 5, iclass 32, count 2 2006.201.20:48:08.73#ibcon#about to read 6, iclass 32, count 2 2006.201.20:48:08.73#ibcon#read 6, iclass 32, count 2 2006.201.20:48:08.73#ibcon#end of sib2, iclass 32, count 2 2006.201.20:48:08.73#ibcon#*mode == 0, iclass 32, count 2 2006.201.20:48:08.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.20:48:08.73#ibcon#[27=AT07-04\r\n] 2006.201.20:48:08.73#ibcon#*before write, iclass 32, count 2 2006.201.20:48:08.73#ibcon#enter sib2, iclass 32, count 2 2006.201.20:48:08.73#ibcon#flushed, iclass 32, count 2 2006.201.20:48:08.73#ibcon#about to write, iclass 32, count 2 2006.201.20:48:08.73#ibcon#wrote, iclass 32, count 2 2006.201.20:48:08.73#ibcon#about to read 3, iclass 32, count 2 2006.201.20:48:08.76#ibcon#read 3, iclass 32, count 2 2006.201.20:48:08.76#ibcon#about to read 4, iclass 32, count 2 2006.201.20:48:08.76#ibcon#read 4, iclass 32, count 2 2006.201.20:48:08.76#ibcon#about to read 5, iclass 32, count 2 2006.201.20:48:08.76#ibcon#read 5, iclass 32, count 2 2006.201.20:48:08.76#ibcon#about to read 6, iclass 32, count 2 2006.201.20:48:08.76#ibcon#read 6, iclass 32, count 2 2006.201.20:48:08.76#ibcon#end of sib2, iclass 32, count 2 2006.201.20:48:08.76#ibcon#*after write, iclass 32, count 2 2006.201.20:48:08.76#ibcon#*before return 0, iclass 32, count 2 2006.201.20:48:08.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:08.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.20:48:08.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.20:48:08.76#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:08.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:08.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:08.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:08.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:48:08.88#ibcon#first serial, iclass 32, count 0 2006.201.20:48:08.88#ibcon#enter sib2, iclass 32, count 0 2006.201.20:48:08.88#ibcon#flushed, iclass 32, count 0 2006.201.20:48:08.88#ibcon#about to write, iclass 32, count 0 2006.201.20:48:08.88#ibcon#wrote, iclass 32, count 0 2006.201.20:48:08.88#ibcon#about to read 3, iclass 32, count 0 2006.201.20:48:08.90#ibcon#read 3, iclass 32, count 0 2006.201.20:48:08.90#ibcon#about to read 4, iclass 32, count 0 2006.201.20:48:08.90#ibcon#read 4, iclass 32, count 0 2006.201.20:48:08.90#ibcon#about to read 5, iclass 32, count 0 2006.201.20:48:08.90#ibcon#read 5, iclass 32, count 0 2006.201.20:48:08.90#ibcon#about to read 6, iclass 32, count 0 2006.201.20:48:08.90#ibcon#read 6, iclass 32, count 0 2006.201.20:48:08.90#ibcon#end of sib2, iclass 32, count 0 2006.201.20:48:08.90#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:48:08.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:48:08.90#ibcon#[27=USB\r\n] 2006.201.20:48:08.90#ibcon#*before write, iclass 32, count 0 2006.201.20:48:08.90#ibcon#enter sib2, iclass 32, count 0 2006.201.20:48:08.90#ibcon#flushed, iclass 32, count 0 2006.201.20:48:08.90#ibcon#about to write, iclass 32, count 0 2006.201.20:48:08.90#ibcon#wrote, iclass 32, count 0 2006.201.20:48:08.90#ibcon#about to read 3, iclass 32, count 0 2006.201.20:48:08.93#ibcon#read 3, iclass 32, count 0 2006.201.20:48:08.93#ibcon#about to read 4, iclass 32, count 0 2006.201.20:48:08.93#ibcon#read 4, iclass 32, count 0 2006.201.20:48:08.93#ibcon#about to read 5, iclass 32, count 0 2006.201.20:48:08.93#ibcon#read 5, iclass 32, count 0 2006.201.20:48:08.93#ibcon#about to read 6, iclass 32, count 0 2006.201.20:48:08.93#ibcon#read 6, iclass 32, count 0 2006.201.20:48:08.93#ibcon#end of sib2, iclass 32, count 0 2006.201.20:48:08.93#ibcon#*after write, iclass 32, count 0 2006.201.20:48:08.93#ibcon#*before return 0, iclass 32, count 0 2006.201.20:48:08.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:08.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.20:48:08.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:48:08.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:48:08.93$vck44/vblo=8,744.99 2006.201.20:48:08.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.20:48:08.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.20:48:08.93#ibcon#ireg 17 cls_cnt 0 2006.201.20:48:08.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:08.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:08.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:08.93#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:48:08.93#ibcon#first serial, iclass 34, count 0 2006.201.20:48:08.93#ibcon#enter sib2, iclass 34, count 0 2006.201.20:48:08.93#ibcon#flushed, iclass 34, count 0 2006.201.20:48:08.93#ibcon#about to write, iclass 34, count 0 2006.201.20:48:08.93#ibcon#wrote, iclass 34, count 0 2006.201.20:48:08.93#ibcon#about to read 3, iclass 34, count 0 2006.201.20:48:08.95#ibcon#read 3, iclass 34, count 0 2006.201.20:48:08.95#ibcon#about to read 4, iclass 34, count 0 2006.201.20:48:08.95#ibcon#read 4, iclass 34, count 0 2006.201.20:48:08.95#ibcon#about to read 5, iclass 34, count 0 2006.201.20:48:08.95#ibcon#read 5, iclass 34, count 0 2006.201.20:48:08.95#ibcon#about to read 6, iclass 34, count 0 2006.201.20:48:08.95#ibcon#read 6, iclass 34, count 0 2006.201.20:48:08.95#ibcon#end of sib2, iclass 34, count 0 2006.201.20:48:08.95#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:48:08.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:48:08.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:48:08.95#ibcon#*before write, iclass 34, count 0 2006.201.20:48:08.95#ibcon#enter sib2, iclass 34, count 0 2006.201.20:48:08.95#ibcon#flushed, iclass 34, count 0 2006.201.20:48:08.95#ibcon#about to write, iclass 34, count 0 2006.201.20:48:08.95#ibcon#wrote, iclass 34, count 0 2006.201.20:48:08.95#ibcon#about to read 3, iclass 34, count 0 2006.201.20:48:09.00#ibcon#read 3, iclass 34, count 0 2006.201.20:48:09.00#ibcon#about to read 4, iclass 34, count 0 2006.201.20:48:09.00#ibcon#read 4, iclass 34, count 0 2006.201.20:48:09.00#ibcon#about to read 5, iclass 34, count 0 2006.201.20:48:09.00#ibcon#read 5, iclass 34, count 0 2006.201.20:48:09.00#ibcon#about to read 6, iclass 34, count 0 2006.201.20:48:09.00#ibcon#read 6, iclass 34, count 0 2006.201.20:48:09.00#ibcon#end of sib2, iclass 34, count 0 2006.201.20:48:09.00#ibcon#*after write, iclass 34, count 0 2006.201.20:48:09.00#ibcon#*before return 0, iclass 34, count 0 2006.201.20:48:09.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:09.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:48:09.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:48:09.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:48:09.00$vck44/vb=8,4 2006.201.20:48:09.00#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.20:48:09.00#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.20:48:09.00#ibcon#ireg 11 cls_cnt 2 2006.201.20:48:09.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:09.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:09.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:09.05#ibcon#enter wrdev, iclass 36, count 2 2006.201.20:48:09.05#ibcon#first serial, iclass 36, count 2 2006.201.20:48:09.05#ibcon#enter sib2, iclass 36, count 2 2006.201.20:48:09.05#ibcon#flushed, iclass 36, count 2 2006.201.20:48:09.05#ibcon#about to write, iclass 36, count 2 2006.201.20:48:09.05#ibcon#wrote, iclass 36, count 2 2006.201.20:48:09.05#ibcon#about to read 3, iclass 36, count 2 2006.201.20:48:09.07#ibcon#read 3, iclass 36, count 2 2006.201.20:48:09.07#ibcon#about to read 4, iclass 36, count 2 2006.201.20:48:09.07#ibcon#read 4, iclass 36, count 2 2006.201.20:48:09.07#ibcon#about to read 5, iclass 36, count 2 2006.201.20:48:09.07#ibcon#read 5, iclass 36, count 2 2006.201.20:48:09.07#ibcon#about to read 6, iclass 36, count 2 2006.201.20:48:09.07#ibcon#read 6, iclass 36, count 2 2006.201.20:48:09.07#ibcon#end of sib2, iclass 36, count 2 2006.201.20:48:09.07#ibcon#*mode == 0, iclass 36, count 2 2006.201.20:48:09.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.20:48:09.07#ibcon#[27=AT08-04\r\n] 2006.201.20:48:09.07#ibcon#*before write, iclass 36, count 2 2006.201.20:48:09.07#ibcon#enter sib2, iclass 36, count 2 2006.201.20:48:09.07#ibcon#flushed, iclass 36, count 2 2006.201.20:48:09.07#ibcon#about to write, iclass 36, count 2 2006.201.20:48:09.07#ibcon#wrote, iclass 36, count 2 2006.201.20:48:09.07#ibcon#about to read 3, iclass 36, count 2 2006.201.20:48:09.10#ibcon#read 3, iclass 36, count 2 2006.201.20:48:09.10#ibcon#about to read 4, iclass 36, count 2 2006.201.20:48:09.10#ibcon#read 4, iclass 36, count 2 2006.201.20:48:09.10#ibcon#about to read 5, iclass 36, count 2 2006.201.20:48:09.10#ibcon#read 5, iclass 36, count 2 2006.201.20:48:09.10#ibcon#about to read 6, iclass 36, count 2 2006.201.20:48:09.10#ibcon#read 6, iclass 36, count 2 2006.201.20:48:09.10#ibcon#end of sib2, iclass 36, count 2 2006.201.20:48:09.10#ibcon#*after write, iclass 36, count 2 2006.201.20:48:09.10#ibcon#*before return 0, iclass 36, count 2 2006.201.20:48:09.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:09.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.20:48:09.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.20:48:09.10#ibcon#ireg 7 cls_cnt 0 2006.201.20:48:09.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:09.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:09.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:09.22#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:48:09.22#ibcon#first serial, iclass 36, count 0 2006.201.20:48:09.22#ibcon#enter sib2, iclass 36, count 0 2006.201.20:48:09.22#ibcon#flushed, iclass 36, count 0 2006.201.20:48:09.22#ibcon#about to write, iclass 36, count 0 2006.201.20:48:09.22#ibcon#wrote, iclass 36, count 0 2006.201.20:48:09.22#ibcon#about to read 3, iclass 36, count 0 2006.201.20:48:09.25#ibcon#read 3, iclass 36, count 0 2006.201.20:48:09.25#ibcon#about to read 4, iclass 36, count 0 2006.201.20:48:09.25#ibcon#read 4, iclass 36, count 0 2006.201.20:48:09.25#ibcon#about to read 5, iclass 36, count 0 2006.201.20:48:09.25#ibcon#read 5, iclass 36, count 0 2006.201.20:48:09.25#ibcon#about to read 6, iclass 36, count 0 2006.201.20:48:09.25#ibcon#read 6, iclass 36, count 0 2006.201.20:48:09.25#ibcon#end of sib2, iclass 36, count 0 2006.201.20:48:09.25#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:48:09.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:48:09.25#ibcon#[27=USB\r\n] 2006.201.20:48:09.25#ibcon#*before write, iclass 36, count 0 2006.201.20:48:09.25#ibcon#enter sib2, iclass 36, count 0 2006.201.20:48:09.25#ibcon#flushed, iclass 36, count 0 2006.201.20:48:09.25#ibcon#about to write, iclass 36, count 0 2006.201.20:48:09.25#ibcon#wrote, iclass 36, count 0 2006.201.20:48:09.25#ibcon#about to read 3, iclass 36, count 0 2006.201.20:48:09.28#ibcon#read 3, iclass 36, count 0 2006.201.20:48:09.28#ibcon#about to read 4, iclass 36, count 0 2006.201.20:48:09.28#ibcon#read 4, iclass 36, count 0 2006.201.20:48:09.28#ibcon#about to read 5, iclass 36, count 0 2006.201.20:48:09.28#ibcon#read 5, iclass 36, count 0 2006.201.20:48:09.28#ibcon#about to read 6, iclass 36, count 0 2006.201.20:48:09.28#ibcon#read 6, iclass 36, count 0 2006.201.20:48:09.28#ibcon#end of sib2, iclass 36, count 0 2006.201.20:48:09.28#ibcon#*after write, iclass 36, count 0 2006.201.20:48:09.28#ibcon#*before return 0, iclass 36, count 0 2006.201.20:48:09.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:09.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.20:48:09.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:48:09.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:48:09.28$vck44/vabw=wide 2006.201.20:48:09.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.20:48:09.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.20:48:09.28#ibcon#ireg 8 cls_cnt 0 2006.201.20:48:09.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:09.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:09.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:09.28#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:48:09.28#ibcon#first serial, iclass 38, count 0 2006.201.20:48:09.28#ibcon#enter sib2, iclass 38, count 0 2006.201.20:48:09.28#ibcon#flushed, iclass 38, count 0 2006.201.20:48:09.28#ibcon#about to write, iclass 38, count 0 2006.201.20:48:09.28#ibcon#wrote, iclass 38, count 0 2006.201.20:48:09.28#ibcon#about to read 3, iclass 38, count 0 2006.201.20:48:09.30#ibcon#read 3, iclass 38, count 0 2006.201.20:48:09.30#ibcon#about to read 4, iclass 38, count 0 2006.201.20:48:09.30#ibcon#read 4, iclass 38, count 0 2006.201.20:48:09.30#ibcon#about to read 5, iclass 38, count 0 2006.201.20:48:09.30#ibcon#read 5, iclass 38, count 0 2006.201.20:48:09.30#ibcon#about to read 6, iclass 38, count 0 2006.201.20:48:09.30#ibcon#read 6, iclass 38, count 0 2006.201.20:48:09.30#ibcon#end of sib2, iclass 38, count 0 2006.201.20:48:09.30#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:48:09.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:48:09.30#ibcon#[25=BW32\r\n] 2006.201.20:48:09.30#ibcon#*before write, iclass 38, count 0 2006.201.20:48:09.30#ibcon#enter sib2, iclass 38, count 0 2006.201.20:48:09.30#ibcon#flushed, iclass 38, count 0 2006.201.20:48:09.30#ibcon#about to write, iclass 38, count 0 2006.201.20:48:09.30#ibcon#wrote, iclass 38, count 0 2006.201.20:48:09.30#ibcon#about to read 3, iclass 38, count 0 2006.201.20:48:09.33#ibcon#read 3, iclass 38, count 0 2006.201.20:48:09.33#ibcon#about to read 4, iclass 38, count 0 2006.201.20:48:09.33#ibcon#read 4, iclass 38, count 0 2006.201.20:48:09.33#ibcon#about to read 5, iclass 38, count 0 2006.201.20:48:09.33#ibcon#read 5, iclass 38, count 0 2006.201.20:48:09.33#ibcon#about to read 6, iclass 38, count 0 2006.201.20:48:09.33#ibcon#read 6, iclass 38, count 0 2006.201.20:48:09.33#ibcon#end of sib2, iclass 38, count 0 2006.201.20:48:09.33#ibcon#*after write, iclass 38, count 0 2006.201.20:48:09.33#ibcon#*before return 0, iclass 38, count 0 2006.201.20:48:09.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:09.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.20:48:09.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:48:09.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:48:09.33$vck44/vbbw=wide 2006.201.20:48:09.33#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.20:48:09.33#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.20:48:09.33#ibcon#ireg 8 cls_cnt 0 2006.201.20:48:09.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:48:09.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:48:09.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:48:09.40#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:48:09.40#ibcon#first serial, iclass 40, count 0 2006.201.20:48:09.40#ibcon#enter sib2, iclass 40, count 0 2006.201.20:48:09.40#ibcon#flushed, iclass 40, count 0 2006.201.20:48:09.40#ibcon#about to write, iclass 40, count 0 2006.201.20:48:09.40#ibcon#wrote, iclass 40, count 0 2006.201.20:48:09.40#ibcon#about to read 3, iclass 40, count 0 2006.201.20:48:09.42#ibcon#read 3, iclass 40, count 0 2006.201.20:48:09.42#ibcon#about to read 4, iclass 40, count 0 2006.201.20:48:09.42#ibcon#read 4, iclass 40, count 0 2006.201.20:48:09.42#ibcon#about to read 5, iclass 40, count 0 2006.201.20:48:09.42#ibcon#read 5, iclass 40, count 0 2006.201.20:48:09.42#ibcon#about to read 6, iclass 40, count 0 2006.201.20:48:09.42#ibcon#read 6, iclass 40, count 0 2006.201.20:48:09.42#ibcon#end of sib2, iclass 40, count 0 2006.201.20:48:09.42#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:48:09.42#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:48:09.42#ibcon#[27=BW32\r\n] 2006.201.20:48:09.42#ibcon#*before write, iclass 40, count 0 2006.201.20:48:09.42#ibcon#enter sib2, iclass 40, count 0 2006.201.20:48:09.42#ibcon#flushed, iclass 40, count 0 2006.201.20:48:09.42#ibcon#about to write, iclass 40, count 0 2006.201.20:48:09.42#ibcon#wrote, iclass 40, count 0 2006.201.20:48:09.42#ibcon#about to read 3, iclass 40, count 0 2006.201.20:48:09.45#ibcon#read 3, iclass 40, count 0 2006.201.20:48:09.45#ibcon#about to read 4, iclass 40, count 0 2006.201.20:48:09.45#ibcon#read 4, iclass 40, count 0 2006.201.20:48:09.45#ibcon#about to read 5, iclass 40, count 0 2006.201.20:48:09.45#ibcon#read 5, iclass 40, count 0 2006.201.20:48:09.45#ibcon#about to read 6, iclass 40, count 0 2006.201.20:48:09.45#ibcon#read 6, iclass 40, count 0 2006.201.20:48:09.45#ibcon#end of sib2, iclass 40, count 0 2006.201.20:48:09.45#ibcon#*after write, iclass 40, count 0 2006.201.20:48:09.45#ibcon#*before return 0, iclass 40, count 0 2006.201.20:48:09.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:48:09.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:48:09.45#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:48:09.45#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:48:09.45$setupk4/ifdk4 2006.201.20:48:09.45$ifdk4/lo= 2006.201.20:48:09.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:48:09.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:48:09.45$ifdk4/patch= 2006.201.20:48:09.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:48:09.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:48:09.45$setupk4/!*+20s 2006.201.20:48:15.14#trakl#Source acquired 2006.201.20:48:17.14#flagr#flagr/antenna,acquired 2006.201.20:48:18.46#abcon#<5=/06 0.5 1.2 20.141001002.5\r\n> 2006.201.20:48:18.48#abcon#{5=INTERFACE CLEAR} 2006.201.20:48:18.54#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:48:23.91$setupk4/"tpicd 2006.201.20:48:23.91$setupk4/echo=off 2006.201.20:48:23.91$setupk4/xlog=off 2006.201.20:48:23.91:!2006.201.20:50:21 2006.201.20:50:21.00:preob 2006.201.20:50:21.14/onsource/TRACKING 2006.201.20:50:21.14:!2006.201.20:50:31 2006.201.20:50:31.00:"tape 2006.201.20:50:31.00:"st=record 2006.201.20:50:31.00:data_valid=on 2006.201.20:50:31.00:midob 2006.201.20:50:32.14/onsource/TRACKING 2006.201.20:50:32.14/wx/20.15,1002.4,100 2006.201.20:50:32.37/cable/+6.4786E-03 2006.201.20:50:33.46/va/01,08,usb,yes,56,59 2006.201.20:50:33.46/va/02,07,usb,yes,60,61 2006.201.20:50:33.46/va/03,08,usb,yes,55,57 2006.201.20:50:33.46/va/04,07,usb,yes,62,65 2006.201.20:50:33.46/va/05,04,usb,yes,55,57 2006.201.20:50:33.46/va/06,05,usb,yes,56,56 2006.201.20:50:33.46/va/07,05,usb,yes,54,56 2006.201.20:50:33.46/va/08,04,usb,yes,54,63 2006.201.20:50:33.69/valo/01,524.99,yes,locked 2006.201.20:50:33.69/valo/02,534.99,yes,locked 2006.201.20:50:33.69/valo/03,564.99,yes,locked 2006.201.20:50:33.69/valo/04,624.99,yes,locked 2006.201.20:50:33.69/valo/05,734.99,yes,locked 2006.201.20:50:33.69/valo/06,814.99,yes,locked 2006.201.20:50:33.69/valo/07,864.99,yes,locked 2006.201.20:50:33.69/valo/08,884.99,yes,locked 2006.201.20:50:34.78/vb/01,04,usb,yes,32,30 2006.201.20:50:34.78/vb/02,05,usb,yes,30,30 2006.201.20:50:34.78/vb/03,04,usb,yes,32,34 2006.201.20:50:34.78/vb/04,05,usb,yes,32,31 2006.201.20:50:34.78/vb/05,04,usb,yes,28,31 2006.201.20:50:34.78/vb/06,04,usb,yes,33,29 2006.201.20:50:34.78/vb/07,04,usb,yes,32,32 2006.201.20:50:34.78/vb/08,04,usb,yes,30,33 2006.201.20:50:35.01/vblo/01,629.99,yes,locked 2006.201.20:50:35.01/vblo/02,634.99,yes,locked 2006.201.20:50:35.01/vblo/03,649.99,yes,locked 2006.201.20:50:35.01/vblo/04,679.99,yes,locked 2006.201.20:50:35.01/vblo/05,709.99,yes,locked 2006.201.20:50:35.01/vblo/06,719.99,yes,locked 2006.201.20:50:35.01/vblo/07,734.99,yes,locked 2006.201.20:50:35.01/vblo/08,744.99,yes,locked 2006.201.20:50:35.16/vabw/8 2006.201.20:50:35.31/vbbw/8 2006.201.20:50:35.40/xfe/off,on,16.0 2006.201.20:50:35.78/ifatt/23,28,28,28 2006.201.20:50:36.06/fmout-gps/S +4.55E-07 2006.201.20:50:36.10:!2006.201.20:55:41 2006.201.20:55:41.00:data_valid=off 2006.201.20:55:41.00:"et 2006.201.20:55:41.00:!+3s 2006.201.20:55:44.02:"tape 2006.201.20:55:44.02:postob 2006.201.20:55:44.14/cable/+6.4801E-03 2006.201.20:55:44.14/wx/20.19,1002.4,100 2006.201.20:55:44.22/fmout-gps/S +4.54E-07 2006.201.20:55:44.22:scan_name=201-2100,jd0607,230 2006.201.20:55:44.23:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.201.20:55:46.14#flagr#flagr/antenna,new-source 2006.201.20:55:46.14:checkk5 2006.201.20:55:46.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.20:55:46.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.20:55:47.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.20:55:47.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.20:55:48.03/chk_obsdata//k5ts1/T2012050??a.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.201.20:55:48.40/chk_obsdata//k5ts2/T2012050??b.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.201.20:55:48.76/chk_obsdata//k5ts3/T2012050??c.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.201.20:55:49.13/chk_obsdata//k5ts4/T2012050??d.dat file size is correct (nominal:1240MB, actual:1240MB). 2006.201.20:55:49.81/k5log//k5ts1_log_newline 2006.201.20:55:50.50/k5log//k5ts2_log_newline 2006.201.20:55:51.18/k5log//k5ts3_log_newline 2006.201.20:55:51.86/k5log//k5ts4_log_newline 2006.201.20:55:51.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.20:55:51.89:setupk4=1 2006.201.20:55:51.89$setupk4/echo=on 2006.201.20:55:51.89$setupk4/pcalon 2006.201.20:55:51.89$pcalon/"no phase cal control is implemented here 2006.201.20:55:51.89$setupk4/"tpicd=stop 2006.201.20:55:51.89$setupk4/"rec=synch_on 2006.201.20:55:51.89$setupk4/"rec_mode=128 2006.201.20:55:51.89$setupk4/!* 2006.201.20:55:51.89$setupk4/recpk4 2006.201.20:55:51.89$recpk4/recpatch= 2006.201.20:55:51.89$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.20:55:51.89$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.20:55:51.89$setupk4/vck44 2006.201.20:55:51.89$vck44/valo=1,524.99 2006.201.20:55:51.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.20:55:51.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.20:55:51.89#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:51.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:51.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:51.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:51.89#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:55:51.89#ibcon#first serial, iclass 40, count 0 2006.201.20:55:51.89#ibcon#enter sib2, iclass 40, count 0 2006.201.20:55:51.89#ibcon#flushed, iclass 40, count 0 2006.201.20:55:51.89#ibcon#about to write, iclass 40, count 0 2006.201.20:55:51.89#ibcon#wrote, iclass 40, count 0 2006.201.20:55:51.89#ibcon#about to read 3, iclass 40, count 0 2006.201.20:55:51.93#ibcon#read 3, iclass 40, count 0 2006.201.20:55:51.93#ibcon#about to read 4, iclass 40, count 0 2006.201.20:55:51.93#ibcon#read 4, iclass 40, count 0 2006.201.20:55:51.93#ibcon#about to read 5, iclass 40, count 0 2006.201.20:55:51.93#ibcon#read 5, iclass 40, count 0 2006.201.20:55:51.93#ibcon#about to read 6, iclass 40, count 0 2006.201.20:55:51.93#ibcon#read 6, iclass 40, count 0 2006.201.20:55:51.93#ibcon#end of sib2, iclass 40, count 0 2006.201.20:55:51.93#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:55:51.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:55:51.93#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.20:55:51.93#ibcon#*before write, iclass 40, count 0 2006.201.20:55:51.93#ibcon#enter sib2, iclass 40, count 0 2006.201.20:55:51.93#ibcon#flushed, iclass 40, count 0 2006.201.20:55:51.93#ibcon#about to write, iclass 40, count 0 2006.201.20:55:51.93#ibcon#wrote, iclass 40, count 0 2006.201.20:55:51.93#ibcon#about to read 3, iclass 40, count 0 2006.201.20:55:51.98#ibcon#read 3, iclass 40, count 0 2006.201.20:55:51.98#ibcon#about to read 4, iclass 40, count 0 2006.201.20:55:51.98#ibcon#read 4, iclass 40, count 0 2006.201.20:55:51.98#ibcon#about to read 5, iclass 40, count 0 2006.201.20:55:51.98#ibcon#read 5, iclass 40, count 0 2006.201.20:55:51.98#ibcon#about to read 6, iclass 40, count 0 2006.201.20:55:51.98#ibcon#read 6, iclass 40, count 0 2006.201.20:55:51.98#ibcon#end of sib2, iclass 40, count 0 2006.201.20:55:51.98#ibcon#*after write, iclass 40, count 0 2006.201.20:55:51.98#ibcon#*before return 0, iclass 40, count 0 2006.201.20:55:51.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:51.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:51.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:55:51.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:55:51.98$vck44/va=1,8 2006.201.20:55:51.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.20:55:51.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.20:55:51.98#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:51.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:51.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:51.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:51.98#ibcon#enter wrdev, iclass 4, count 2 2006.201.20:55:51.98#ibcon#first serial, iclass 4, count 2 2006.201.20:55:51.98#ibcon#enter sib2, iclass 4, count 2 2006.201.20:55:51.98#ibcon#flushed, iclass 4, count 2 2006.201.20:55:51.98#ibcon#about to write, iclass 4, count 2 2006.201.20:55:51.98#ibcon#wrote, iclass 4, count 2 2006.201.20:55:51.98#ibcon#about to read 3, iclass 4, count 2 2006.201.20:55:52.00#ibcon#read 3, iclass 4, count 2 2006.201.20:55:52.00#ibcon#about to read 4, iclass 4, count 2 2006.201.20:55:52.00#ibcon#read 4, iclass 4, count 2 2006.201.20:55:52.00#ibcon#about to read 5, iclass 4, count 2 2006.201.20:55:52.00#ibcon#read 5, iclass 4, count 2 2006.201.20:55:52.00#ibcon#about to read 6, iclass 4, count 2 2006.201.20:55:52.00#ibcon#read 6, iclass 4, count 2 2006.201.20:55:52.00#ibcon#end of sib2, iclass 4, count 2 2006.201.20:55:52.00#ibcon#*mode == 0, iclass 4, count 2 2006.201.20:55:52.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.20:55:52.00#ibcon#[25=AT01-08\r\n] 2006.201.20:55:52.00#ibcon#*before write, iclass 4, count 2 2006.201.20:55:52.00#ibcon#enter sib2, iclass 4, count 2 2006.201.20:55:52.00#ibcon#flushed, iclass 4, count 2 2006.201.20:55:52.00#ibcon#about to write, iclass 4, count 2 2006.201.20:55:52.00#ibcon#wrote, iclass 4, count 2 2006.201.20:55:52.00#ibcon#about to read 3, iclass 4, count 2 2006.201.20:55:52.03#ibcon#read 3, iclass 4, count 2 2006.201.20:55:52.03#ibcon#about to read 4, iclass 4, count 2 2006.201.20:55:52.03#ibcon#read 4, iclass 4, count 2 2006.201.20:55:52.03#ibcon#about to read 5, iclass 4, count 2 2006.201.20:55:52.03#ibcon#read 5, iclass 4, count 2 2006.201.20:55:52.03#ibcon#about to read 6, iclass 4, count 2 2006.201.20:55:52.03#ibcon#read 6, iclass 4, count 2 2006.201.20:55:52.03#ibcon#end of sib2, iclass 4, count 2 2006.201.20:55:52.03#ibcon#*after write, iclass 4, count 2 2006.201.20:55:52.03#ibcon#*before return 0, iclass 4, count 2 2006.201.20:55:52.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:52.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:52.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.20:55:52.03#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:52.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:52.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:52.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:52.15#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:55:52.15#ibcon#first serial, iclass 4, count 0 2006.201.20:55:52.15#ibcon#enter sib2, iclass 4, count 0 2006.201.20:55:52.15#ibcon#flushed, iclass 4, count 0 2006.201.20:55:52.15#ibcon#about to write, iclass 4, count 0 2006.201.20:55:52.15#ibcon#wrote, iclass 4, count 0 2006.201.20:55:52.15#ibcon#about to read 3, iclass 4, count 0 2006.201.20:55:52.17#ibcon#read 3, iclass 4, count 0 2006.201.20:55:52.17#ibcon#about to read 4, iclass 4, count 0 2006.201.20:55:52.17#ibcon#read 4, iclass 4, count 0 2006.201.20:55:52.17#ibcon#about to read 5, iclass 4, count 0 2006.201.20:55:52.17#ibcon#read 5, iclass 4, count 0 2006.201.20:55:52.17#ibcon#about to read 6, iclass 4, count 0 2006.201.20:55:52.17#ibcon#read 6, iclass 4, count 0 2006.201.20:55:52.17#ibcon#end of sib2, iclass 4, count 0 2006.201.20:55:52.17#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:55:52.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:55:52.17#ibcon#[25=USB\r\n] 2006.201.20:55:52.17#ibcon#*before write, iclass 4, count 0 2006.201.20:55:52.17#ibcon#enter sib2, iclass 4, count 0 2006.201.20:55:52.17#ibcon#flushed, iclass 4, count 0 2006.201.20:55:52.17#ibcon#about to write, iclass 4, count 0 2006.201.20:55:52.17#ibcon#wrote, iclass 4, count 0 2006.201.20:55:52.17#ibcon#about to read 3, iclass 4, count 0 2006.201.20:55:52.20#ibcon#read 3, iclass 4, count 0 2006.201.20:55:52.20#ibcon#about to read 4, iclass 4, count 0 2006.201.20:55:52.20#ibcon#read 4, iclass 4, count 0 2006.201.20:55:52.20#ibcon#about to read 5, iclass 4, count 0 2006.201.20:55:52.20#ibcon#read 5, iclass 4, count 0 2006.201.20:55:52.20#ibcon#about to read 6, iclass 4, count 0 2006.201.20:55:52.20#ibcon#read 6, iclass 4, count 0 2006.201.20:55:52.20#ibcon#end of sib2, iclass 4, count 0 2006.201.20:55:52.20#ibcon#*after write, iclass 4, count 0 2006.201.20:55:52.20#ibcon#*before return 0, iclass 4, count 0 2006.201.20:55:52.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:52.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:52.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:55:52.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:55:52.20$vck44/valo=2,534.99 2006.201.20:55:52.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.20:55:52.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.20:55:52.20#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:52.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:52.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:52.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:52.20#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:55:52.20#ibcon#first serial, iclass 6, count 0 2006.201.20:55:52.20#ibcon#enter sib2, iclass 6, count 0 2006.201.20:55:52.20#ibcon#flushed, iclass 6, count 0 2006.201.20:55:52.20#ibcon#about to write, iclass 6, count 0 2006.201.20:55:52.20#ibcon#wrote, iclass 6, count 0 2006.201.20:55:52.20#ibcon#about to read 3, iclass 6, count 0 2006.201.20:55:52.22#ibcon#read 3, iclass 6, count 0 2006.201.20:55:52.22#ibcon#about to read 4, iclass 6, count 0 2006.201.20:55:52.22#ibcon#read 4, iclass 6, count 0 2006.201.20:55:52.22#ibcon#about to read 5, iclass 6, count 0 2006.201.20:55:52.22#ibcon#read 5, iclass 6, count 0 2006.201.20:55:52.22#ibcon#about to read 6, iclass 6, count 0 2006.201.20:55:52.22#ibcon#read 6, iclass 6, count 0 2006.201.20:55:52.22#ibcon#end of sib2, iclass 6, count 0 2006.201.20:55:52.22#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:55:52.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:55:52.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.20:55:52.22#ibcon#*before write, iclass 6, count 0 2006.201.20:55:52.22#ibcon#enter sib2, iclass 6, count 0 2006.201.20:55:52.22#ibcon#flushed, iclass 6, count 0 2006.201.20:55:52.22#ibcon#about to write, iclass 6, count 0 2006.201.20:55:52.22#ibcon#wrote, iclass 6, count 0 2006.201.20:55:52.22#ibcon#about to read 3, iclass 6, count 0 2006.201.20:55:52.26#ibcon#read 3, iclass 6, count 0 2006.201.20:55:52.26#ibcon#about to read 4, iclass 6, count 0 2006.201.20:55:52.26#ibcon#read 4, iclass 6, count 0 2006.201.20:55:52.26#ibcon#about to read 5, iclass 6, count 0 2006.201.20:55:52.26#ibcon#read 5, iclass 6, count 0 2006.201.20:55:52.26#ibcon#about to read 6, iclass 6, count 0 2006.201.20:55:52.26#ibcon#read 6, iclass 6, count 0 2006.201.20:55:52.26#ibcon#end of sib2, iclass 6, count 0 2006.201.20:55:52.26#ibcon#*after write, iclass 6, count 0 2006.201.20:55:52.26#ibcon#*before return 0, iclass 6, count 0 2006.201.20:55:52.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:52.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:52.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:55:52.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:55:52.26$vck44/va=2,7 2006.201.20:55:52.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.20:55:52.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.20:55:52.26#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:52.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:52.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:52.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:52.32#ibcon#enter wrdev, iclass 10, count 2 2006.201.20:55:52.32#ibcon#first serial, iclass 10, count 2 2006.201.20:55:52.32#ibcon#enter sib2, iclass 10, count 2 2006.201.20:55:52.32#ibcon#flushed, iclass 10, count 2 2006.201.20:55:52.32#ibcon#about to write, iclass 10, count 2 2006.201.20:55:52.32#ibcon#wrote, iclass 10, count 2 2006.201.20:55:52.32#ibcon#about to read 3, iclass 10, count 2 2006.201.20:55:52.34#ibcon#read 3, iclass 10, count 2 2006.201.20:55:52.34#ibcon#about to read 4, iclass 10, count 2 2006.201.20:55:52.34#ibcon#read 4, iclass 10, count 2 2006.201.20:55:52.34#ibcon#about to read 5, iclass 10, count 2 2006.201.20:55:52.34#ibcon#read 5, iclass 10, count 2 2006.201.20:55:52.34#ibcon#about to read 6, iclass 10, count 2 2006.201.20:55:52.34#ibcon#read 6, iclass 10, count 2 2006.201.20:55:52.34#ibcon#end of sib2, iclass 10, count 2 2006.201.20:55:52.34#ibcon#*mode == 0, iclass 10, count 2 2006.201.20:55:52.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.20:55:52.34#ibcon#[25=AT02-07\r\n] 2006.201.20:55:52.34#ibcon#*before write, iclass 10, count 2 2006.201.20:55:52.34#ibcon#enter sib2, iclass 10, count 2 2006.201.20:55:52.34#ibcon#flushed, iclass 10, count 2 2006.201.20:55:52.34#ibcon#about to write, iclass 10, count 2 2006.201.20:55:52.34#ibcon#wrote, iclass 10, count 2 2006.201.20:55:52.34#ibcon#about to read 3, iclass 10, count 2 2006.201.20:55:52.37#ibcon#read 3, iclass 10, count 2 2006.201.20:55:52.37#ibcon#about to read 4, iclass 10, count 2 2006.201.20:55:52.37#ibcon#read 4, iclass 10, count 2 2006.201.20:55:52.37#ibcon#about to read 5, iclass 10, count 2 2006.201.20:55:52.37#ibcon#read 5, iclass 10, count 2 2006.201.20:55:52.37#ibcon#about to read 6, iclass 10, count 2 2006.201.20:55:52.37#ibcon#read 6, iclass 10, count 2 2006.201.20:55:52.37#ibcon#end of sib2, iclass 10, count 2 2006.201.20:55:52.37#ibcon#*after write, iclass 10, count 2 2006.201.20:55:52.37#ibcon#*before return 0, iclass 10, count 2 2006.201.20:55:52.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:52.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:52.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.20:55:52.37#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:52.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:52.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:52.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:52.49#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:55:52.49#ibcon#first serial, iclass 10, count 0 2006.201.20:55:52.49#ibcon#enter sib2, iclass 10, count 0 2006.201.20:55:52.49#ibcon#flushed, iclass 10, count 0 2006.201.20:55:52.49#ibcon#about to write, iclass 10, count 0 2006.201.20:55:52.49#ibcon#wrote, iclass 10, count 0 2006.201.20:55:52.49#ibcon#about to read 3, iclass 10, count 0 2006.201.20:55:52.51#ibcon#read 3, iclass 10, count 0 2006.201.20:55:52.51#ibcon#about to read 4, iclass 10, count 0 2006.201.20:55:52.51#ibcon#read 4, iclass 10, count 0 2006.201.20:55:52.51#ibcon#about to read 5, iclass 10, count 0 2006.201.20:55:52.51#ibcon#read 5, iclass 10, count 0 2006.201.20:55:52.51#ibcon#about to read 6, iclass 10, count 0 2006.201.20:55:52.51#ibcon#read 6, iclass 10, count 0 2006.201.20:55:52.51#ibcon#end of sib2, iclass 10, count 0 2006.201.20:55:52.51#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:55:52.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:55:52.51#ibcon#[25=USB\r\n] 2006.201.20:55:52.51#ibcon#*before write, iclass 10, count 0 2006.201.20:55:52.51#ibcon#enter sib2, iclass 10, count 0 2006.201.20:55:52.51#ibcon#flushed, iclass 10, count 0 2006.201.20:55:52.51#ibcon#about to write, iclass 10, count 0 2006.201.20:55:52.51#ibcon#wrote, iclass 10, count 0 2006.201.20:55:52.51#ibcon#about to read 3, iclass 10, count 0 2006.201.20:55:52.54#ibcon#read 3, iclass 10, count 0 2006.201.20:55:52.54#ibcon#about to read 4, iclass 10, count 0 2006.201.20:55:52.54#ibcon#read 4, iclass 10, count 0 2006.201.20:55:52.54#ibcon#about to read 5, iclass 10, count 0 2006.201.20:55:52.54#ibcon#read 5, iclass 10, count 0 2006.201.20:55:52.54#ibcon#about to read 6, iclass 10, count 0 2006.201.20:55:52.54#ibcon#read 6, iclass 10, count 0 2006.201.20:55:52.54#ibcon#end of sib2, iclass 10, count 0 2006.201.20:55:52.54#ibcon#*after write, iclass 10, count 0 2006.201.20:55:52.54#ibcon#*before return 0, iclass 10, count 0 2006.201.20:55:52.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:52.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:52.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:55:52.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:55:52.54$vck44/valo=3,564.99 2006.201.20:55:52.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.20:55:52.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.20:55:52.54#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:52.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:52.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:52.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:52.54#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:55:52.54#ibcon#first serial, iclass 12, count 0 2006.201.20:55:52.54#ibcon#enter sib2, iclass 12, count 0 2006.201.20:55:52.54#ibcon#flushed, iclass 12, count 0 2006.201.20:55:52.54#ibcon#about to write, iclass 12, count 0 2006.201.20:55:52.54#ibcon#wrote, iclass 12, count 0 2006.201.20:55:52.54#ibcon#about to read 3, iclass 12, count 0 2006.201.20:55:52.56#ibcon#read 3, iclass 12, count 0 2006.201.20:55:52.56#ibcon#about to read 4, iclass 12, count 0 2006.201.20:55:52.56#ibcon#read 4, iclass 12, count 0 2006.201.20:55:52.56#ibcon#about to read 5, iclass 12, count 0 2006.201.20:55:52.56#ibcon#read 5, iclass 12, count 0 2006.201.20:55:52.56#ibcon#about to read 6, iclass 12, count 0 2006.201.20:55:52.56#ibcon#read 6, iclass 12, count 0 2006.201.20:55:52.56#ibcon#end of sib2, iclass 12, count 0 2006.201.20:55:52.56#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:55:52.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:55:52.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.20:55:52.56#ibcon#*before write, iclass 12, count 0 2006.201.20:55:52.56#ibcon#enter sib2, iclass 12, count 0 2006.201.20:55:52.56#ibcon#flushed, iclass 12, count 0 2006.201.20:55:52.56#ibcon#about to write, iclass 12, count 0 2006.201.20:55:52.56#ibcon#wrote, iclass 12, count 0 2006.201.20:55:52.56#ibcon#about to read 3, iclass 12, count 0 2006.201.20:55:52.61#ibcon#read 3, iclass 12, count 0 2006.201.20:55:52.61#ibcon#about to read 4, iclass 12, count 0 2006.201.20:55:52.61#ibcon#read 4, iclass 12, count 0 2006.201.20:55:52.61#ibcon#about to read 5, iclass 12, count 0 2006.201.20:55:52.61#ibcon#read 5, iclass 12, count 0 2006.201.20:55:52.61#ibcon#about to read 6, iclass 12, count 0 2006.201.20:55:52.61#ibcon#read 6, iclass 12, count 0 2006.201.20:55:52.61#ibcon#end of sib2, iclass 12, count 0 2006.201.20:55:52.61#ibcon#*after write, iclass 12, count 0 2006.201.20:55:52.61#ibcon#*before return 0, iclass 12, count 0 2006.201.20:55:52.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:52.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:52.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:55:52.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:55:52.61$vck44/va=3,8 2006.201.20:55:52.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.20:55:52.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.20:55:52.61#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:52.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:52.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:52.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:52.66#ibcon#enter wrdev, iclass 14, count 2 2006.201.20:55:52.66#ibcon#first serial, iclass 14, count 2 2006.201.20:55:52.66#ibcon#enter sib2, iclass 14, count 2 2006.201.20:55:52.66#ibcon#flushed, iclass 14, count 2 2006.201.20:55:52.66#ibcon#about to write, iclass 14, count 2 2006.201.20:55:52.66#ibcon#wrote, iclass 14, count 2 2006.201.20:55:52.66#ibcon#about to read 3, iclass 14, count 2 2006.201.20:55:52.68#ibcon#read 3, iclass 14, count 2 2006.201.20:55:52.68#ibcon#about to read 4, iclass 14, count 2 2006.201.20:55:52.68#ibcon#read 4, iclass 14, count 2 2006.201.20:55:52.68#ibcon#about to read 5, iclass 14, count 2 2006.201.20:55:52.68#ibcon#read 5, iclass 14, count 2 2006.201.20:55:52.68#ibcon#about to read 6, iclass 14, count 2 2006.201.20:55:52.68#ibcon#read 6, iclass 14, count 2 2006.201.20:55:52.68#ibcon#end of sib2, iclass 14, count 2 2006.201.20:55:52.68#ibcon#*mode == 0, iclass 14, count 2 2006.201.20:55:52.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.20:55:52.68#ibcon#[25=AT03-08\r\n] 2006.201.20:55:52.68#ibcon#*before write, iclass 14, count 2 2006.201.20:55:52.68#ibcon#enter sib2, iclass 14, count 2 2006.201.20:55:52.68#ibcon#flushed, iclass 14, count 2 2006.201.20:55:52.68#ibcon#about to write, iclass 14, count 2 2006.201.20:55:52.68#ibcon#wrote, iclass 14, count 2 2006.201.20:55:52.68#ibcon#about to read 3, iclass 14, count 2 2006.201.20:55:52.71#ibcon#read 3, iclass 14, count 2 2006.201.20:55:52.71#ibcon#about to read 4, iclass 14, count 2 2006.201.20:55:52.71#ibcon#read 4, iclass 14, count 2 2006.201.20:55:52.71#ibcon#about to read 5, iclass 14, count 2 2006.201.20:55:52.71#ibcon#read 5, iclass 14, count 2 2006.201.20:55:52.71#ibcon#about to read 6, iclass 14, count 2 2006.201.20:55:52.71#ibcon#read 6, iclass 14, count 2 2006.201.20:55:52.71#ibcon#end of sib2, iclass 14, count 2 2006.201.20:55:52.71#ibcon#*after write, iclass 14, count 2 2006.201.20:55:52.71#ibcon#*before return 0, iclass 14, count 2 2006.201.20:55:52.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:52.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:52.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.20:55:52.71#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:52.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:52.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:52.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:52.83#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:55:52.83#ibcon#first serial, iclass 14, count 0 2006.201.20:55:52.83#ibcon#enter sib2, iclass 14, count 0 2006.201.20:55:52.83#ibcon#flushed, iclass 14, count 0 2006.201.20:55:52.83#ibcon#about to write, iclass 14, count 0 2006.201.20:55:52.83#ibcon#wrote, iclass 14, count 0 2006.201.20:55:52.83#ibcon#about to read 3, iclass 14, count 0 2006.201.20:55:52.85#ibcon#read 3, iclass 14, count 0 2006.201.20:55:52.85#ibcon#about to read 4, iclass 14, count 0 2006.201.20:55:52.85#ibcon#read 4, iclass 14, count 0 2006.201.20:55:52.85#ibcon#about to read 5, iclass 14, count 0 2006.201.20:55:52.85#ibcon#read 5, iclass 14, count 0 2006.201.20:55:52.85#ibcon#about to read 6, iclass 14, count 0 2006.201.20:55:52.85#ibcon#read 6, iclass 14, count 0 2006.201.20:55:52.85#ibcon#end of sib2, iclass 14, count 0 2006.201.20:55:52.85#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:55:52.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:55:52.85#ibcon#[25=USB\r\n] 2006.201.20:55:52.85#ibcon#*before write, iclass 14, count 0 2006.201.20:55:52.85#ibcon#enter sib2, iclass 14, count 0 2006.201.20:55:52.85#ibcon#flushed, iclass 14, count 0 2006.201.20:55:52.85#ibcon#about to write, iclass 14, count 0 2006.201.20:55:52.85#ibcon#wrote, iclass 14, count 0 2006.201.20:55:52.85#ibcon#about to read 3, iclass 14, count 0 2006.201.20:55:52.88#ibcon#read 3, iclass 14, count 0 2006.201.20:55:52.88#ibcon#about to read 4, iclass 14, count 0 2006.201.20:55:52.88#ibcon#read 4, iclass 14, count 0 2006.201.20:55:52.88#ibcon#about to read 5, iclass 14, count 0 2006.201.20:55:52.88#ibcon#read 5, iclass 14, count 0 2006.201.20:55:52.88#ibcon#about to read 6, iclass 14, count 0 2006.201.20:55:52.88#ibcon#read 6, iclass 14, count 0 2006.201.20:55:52.88#ibcon#end of sib2, iclass 14, count 0 2006.201.20:55:52.88#ibcon#*after write, iclass 14, count 0 2006.201.20:55:52.88#ibcon#*before return 0, iclass 14, count 0 2006.201.20:55:52.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:52.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:52.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:55:52.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:55:52.88$vck44/valo=4,624.99 2006.201.20:55:52.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.20:55:52.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.20:55:52.88#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:52.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:52.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:52.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:52.88#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:55:52.88#ibcon#first serial, iclass 16, count 0 2006.201.20:55:52.88#ibcon#enter sib2, iclass 16, count 0 2006.201.20:55:52.88#ibcon#flushed, iclass 16, count 0 2006.201.20:55:52.88#ibcon#about to write, iclass 16, count 0 2006.201.20:55:52.88#ibcon#wrote, iclass 16, count 0 2006.201.20:55:52.88#ibcon#about to read 3, iclass 16, count 0 2006.201.20:55:52.90#ibcon#read 3, iclass 16, count 0 2006.201.20:55:52.90#ibcon#about to read 4, iclass 16, count 0 2006.201.20:55:52.90#ibcon#read 4, iclass 16, count 0 2006.201.20:55:52.90#ibcon#about to read 5, iclass 16, count 0 2006.201.20:55:52.90#ibcon#read 5, iclass 16, count 0 2006.201.20:55:52.90#ibcon#about to read 6, iclass 16, count 0 2006.201.20:55:52.90#ibcon#read 6, iclass 16, count 0 2006.201.20:55:52.90#ibcon#end of sib2, iclass 16, count 0 2006.201.20:55:52.90#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:55:52.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:55:52.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.20:55:52.90#ibcon#*before write, iclass 16, count 0 2006.201.20:55:52.90#ibcon#enter sib2, iclass 16, count 0 2006.201.20:55:52.90#ibcon#flushed, iclass 16, count 0 2006.201.20:55:52.90#ibcon#about to write, iclass 16, count 0 2006.201.20:55:52.90#ibcon#wrote, iclass 16, count 0 2006.201.20:55:52.90#ibcon#about to read 3, iclass 16, count 0 2006.201.20:55:52.95#ibcon#read 3, iclass 16, count 0 2006.201.20:55:52.95#ibcon#about to read 4, iclass 16, count 0 2006.201.20:55:52.95#ibcon#read 4, iclass 16, count 0 2006.201.20:55:52.95#ibcon#about to read 5, iclass 16, count 0 2006.201.20:55:52.95#ibcon#read 5, iclass 16, count 0 2006.201.20:55:52.95#ibcon#about to read 6, iclass 16, count 0 2006.201.20:55:52.95#ibcon#read 6, iclass 16, count 0 2006.201.20:55:52.95#ibcon#end of sib2, iclass 16, count 0 2006.201.20:55:52.95#ibcon#*after write, iclass 16, count 0 2006.201.20:55:52.95#ibcon#*before return 0, iclass 16, count 0 2006.201.20:55:52.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:52.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:52.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:55:52.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:55:52.95$vck44/va=4,7 2006.201.20:55:52.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.20:55:52.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.20:55:52.95#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:52.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:53.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:53.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:53.00#ibcon#enter wrdev, iclass 18, count 2 2006.201.20:55:53.00#ibcon#first serial, iclass 18, count 2 2006.201.20:55:53.00#ibcon#enter sib2, iclass 18, count 2 2006.201.20:55:53.00#ibcon#flushed, iclass 18, count 2 2006.201.20:55:53.00#ibcon#about to write, iclass 18, count 2 2006.201.20:55:53.00#ibcon#wrote, iclass 18, count 2 2006.201.20:55:53.00#ibcon#about to read 3, iclass 18, count 2 2006.201.20:55:53.02#ibcon#read 3, iclass 18, count 2 2006.201.20:55:53.02#ibcon#about to read 4, iclass 18, count 2 2006.201.20:55:53.02#ibcon#read 4, iclass 18, count 2 2006.201.20:55:53.02#ibcon#about to read 5, iclass 18, count 2 2006.201.20:55:53.02#ibcon#read 5, iclass 18, count 2 2006.201.20:55:53.02#ibcon#about to read 6, iclass 18, count 2 2006.201.20:55:53.02#ibcon#read 6, iclass 18, count 2 2006.201.20:55:53.02#ibcon#end of sib2, iclass 18, count 2 2006.201.20:55:53.02#ibcon#*mode == 0, iclass 18, count 2 2006.201.20:55:53.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.20:55:53.02#ibcon#[25=AT04-07\r\n] 2006.201.20:55:53.02#ibcon#*before write, iclass 18, count 2 2006.201.20:55:53.02#ibcon#enter sib2, iclass 18, count 2 2006.201.20:55:53.02#ibcon#flushed, iclass 18, count 2 2006.201.20:55:53.02#ibcon#about to write, iclass 18, count 2 2006.201.20:55:53.02#ibcon#wrote, iclass 18, count 2 2006.201.20:55:53.02#ibcon#about to read 3, iclass 18, count 2 2006.201.20:55:53.05#ibcon#read 3, iclass 18, count 2 2006.201.20:55:53.05#ibcon#about to read 4, iclass 18, count 2 2006.201.20:55:53.05#ibcon#read 4, iclass 18, count 2 2006.201.20:55:53.05#ibcon#about to read 5, iclass 18, count 2 2006.201.20:55:53.05#ibcon#read 5, iclass 18, count 2 2006.201.20:55:53.05#ibcon#about to read 6, iclass 18, count 2 2006.201.20:55:53.05#ibcon#read 6, iclass 18, count 2 2006.201.20:55:53.05#ibcon#end of sib2, iclass 18, count 2 2006.201.20:55:53.05#ibcon#*after write, iclass 18, count 2 2006.201.20:55:53.05#ibcon#*before return 0, iclass 18, count 2 2006.201.20:55:53.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:53.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:53.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.20:55:53.05#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:53.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:53.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:53.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:53.17#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:55:53.17#ibcon#first serial, iclass 18, count 0 2006.201.20:55:53.17#ibcon#enter sib2, iclass 18, count 0 2006.201.20:55:53.17#ibcon#flushed, iclass 18, count 0 2006.201.20:55:53.17#ibcon#about to write, iclass 18, count 0 2006.201.20:55:53.17#ibcon#wrote, iclass 18, count 0 2006.201.20:55:53.17#ibcon#about to read 3, iclass 18, count 0 2006.201.20:55:53.19#ibcon#read 3, iclass 18, count 0 2006.201.20:55:53.19#ibcon#about to read 4, iclass 18, count 0 2006.201.20:55:53.19#ibcon#read 4, iclass 18, count 0 2006.201.20:55:53.19#ibcon#about to read 5, iclass 18, count 0 2006.201.20:55:53.19#ibcon#read 5, iclass 18, count 0 2006.201.20:55:53.19#ibcon#about to read 6, iclass 18, count 0 2006.201.20:55:53.19#ibcon#read 6, iclass 18, count 0 2006.201.20:55:53.19#ibcon#end of sib2, iclass 18, count 0 2006.201.20:55:53.19#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:55:53.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:55:53.19#ibcon#[25=USB\r\n] 2006.201.20:55:53.19#ibcon#*before write, iclass 18, count 0 2006.201.20:55:53.19#ibcon#enter sib2, iclass 18, count 0 2006.201.20:55:53.19#ibcon#flushed, iclass 18, count 0 2006.201.20:55:53.19#ibcon#about to write, iclass 18, count 0 2006.201.20:55:53.19#ibcon#wrote, iclass 18, count 0 2006.201.20:55:53.19#ibcon#about to read 3, iclass 18, count 0 2006.201.20:55:53.22#ibcon#read 3, iclass 18, count 0 2006.201.20:55:53.22#ibcon#about to read 4, iclass 18, count 0 2006.201.20:55:53.22#ibcon#read 4, iclass 18, count 0 2006.201.20:55:53.22#ibcon#about to read 5, iclass 18, count 0 2006.201.20:55:53.22#ibcon#read 5, iclass 18, count 0 2006.201.20:55:53.22#ibcon#about to read 6, iclass 18, count 0 2006.201.20:55:53.22#ibcon#read 6, iclass 18, count 0 2006.201.20:55:53.22#ibcon#end of sib2, iclass 18, count 0 2006.201.20:55:53.22#ibcon#*after write, iclass 18, count 0 2006.201.20:55:53.22#ibcon#*before return 0, iclass 18, count 0 2006.201.20:55:53.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:53.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:53.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:55:53.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:55:53.22$vck44/valo=5,734.99 2006.201.20:55:53.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.20:55:53.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.20:55:53.22#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:53.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:53.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:53.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:53.22#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:55:53.22#ibcon#first serial, iclass 20, count 0 2006.201.20:55:53.22#ibcon#enter sib2, iclass 20, count 0 2006.201.20:55:53.22#ibcon#flushed, iclass 20, count 0 2006.201.20:55:53.22#ibcon#about to write, iclass 20, count 0 2006.201.20:55:53.22#ibcon#wrote, iclass 20, count 0 2006.201.20:55:53.22#ibcon#about to read 3, iclass 20, count 0 2006.201.20:55:53.24#ibcon#read 3, iclass 20, count 0 2006.201.20:55:53.24#ibcon#about to read 4, iclass 20, count 0 2006.201.20:55:53.24#ibcon#read 4, iclass 20, count 0 2006.201.20:55:53.24#ibcon#about to read 5, iclass 20, count 0 2006.201.20:55:53.24#ibcon#read 5, iclass 20, count 0 2006.201.20:55:53.24#ibcon#about to read 6, iclass 20, count 0 2006.201.20:55:53.24#ibcon#read 6, iclass 20, count 0 2006.201.20:55:53.24#ibcon#end of sib2, iclass 20, count 0 2006.201.20:55:53.24#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:55:53.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:55:53.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.20:55:53.24#ibcon#*before write, iclass 20, count 0 2006.201.20:55:53.24#ibcon#enter sib2, iclass 20, count 0 2006.201.20:55:53.24#ibcon#flushed, iclass 20, count 0 2006.201.20:55:53.24#ibcon#about to write, iclass 20, count 0 2006.201.20:55:53.24#ibcon#wrote, iclass 20, count 0 2006.201.20:55:53.24#ibcon#about to read 3, iclass 20, count 0 2006.201.20:55:53.28#ibcon#read 3, iclass 20, count 0 2006.201.20:55:53.28#ibcon#about to read 4, iclass 20, count 0 2006.201.20:55:53.28#ibcon#read 4, iclass 20, count 0 2006.201.20:55:53.28#ibcon#about to read 5, iclass 20, count 0 2006.201.20:55:53.28#ibcon#read 5, iclass 20, count 0 2006.201.20:55:53.28#ibcon#about to read 6, iclass 20, count 0 2006.201.20:55:53.28#ibcon#read 6, iclass 20, count 0 2006.201.20:55:53.28#ibcon#end of sib2, iclass 20, count 0 2006.201.20:55:53.28#ibcon#*after write, iclass 20, count 0 2006.201.20:55:53.28#ibcon#*before return 0, iclass 20, count 0 2006.201.20:55:53.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:53.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:53.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:55:53.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:55:53.28$vck44/va=5,4 2006.201.20:55:53.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.20:55:53.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.20:55:53.28#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:53.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:53.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:53.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:53.34#ibcon#enter wrdev, iclass 22, count 2 2006.201.20:55:53.34#ibcon#first serial, iclass 22, count 2 2006.201.20:55:53.34#ibcon#enter sib2, iclass 22, count 2 2006.201.20:55:53.34#ibcon#flushed, iclass 22, count 2 2006.201.20:55:53.34#ibcon#about to write, iclass 22, count 2 2006.201.20:55:53.34#ibcon#wrote, iclass 22, count 2 2006.201.20:55:53.34#ibcon#about to read 3, iclass 22, count 2 2006.201.20:55:53.36#ibcon#read 3, iclass 22, count 2 2006.201.20:55:53.36#ibcon#about to read 4, iclass 22, count 2 2006.201.20:55:53.36#ibcon#read 4, iclass 22, count 2 2006.201.20:55:53.36#ibcon#about to read 5, iclass 22, count 2 2006.201.20:55:53.36#ibcon#read 5, iclass 22, count 2 2006.201.20:55:53.36#ibcon#about to read 6, iclass 22, count 2 2006.201.20:55:53.36#ibcon#read 6, iclass 22, count 2 2006.201.20:55:53.36#ibcon#end of sib2, iclass 22, count 2 2006.201.20:55:53.36#ibcon#*mode == 0, iclass 22, count 2 2006.201.20:55:53.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.20:55:53.36#ibcon#[25=AT05-04\r\n] 2006.201.20:55:53.36#ibcon#*before write, iclass 22, count 2 2006.201.20:55:53.36#ibcon#enter sib2, iclass 22, count 2 2006.201.20:55:53.36#ibcon#flushed, iclass 22, count 2 2006.201.20:55:53.36#ibcon#about to write, iclass 22, count 2 2006.201.20:55:53.36#ibcon#wrote, iclass 22, count 2 2006.201.20:55:53.36#ibcon#about to read 3, iclass 22, count 2 2006.201.20:55:53.39#ibcon#read 3, iclass 22, count 2 2006.201.20:55:53.39#ibcon#about to read 4, iclass 22, count 2 2006.201.20:55:53.39#ibcon#read 4, iclass 22, count 2 2006.201.20:55:53.39#ibcon#about to read 5, iclass 22, count 2 2006.201.20:55:53.39#ibcon#read 5, iclass 22, count 2 2006.201.20:55:53.39#ibcon#about to read 6, iclass 22, count 2 2006.201.20:55:53.39#ibcon#read 6, iclass 22, count 2 2006.201.20:55:53.39#ibcon#end of sib2, iclass 22, count 2 2006.201.20:55:53.39#ibcon#*after write, iclass 22, count 2 2006.201.20:55:53.39#ibcon#*before return 0, iclass 22, count 2 2006.201.20:55:53.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:53.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:53.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.20:55:53.39#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:53.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:53.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:53.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:53.51#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:55:53.51#ibcon#first serial, iclass 22, count 0 2006.201.20:55:53.51#ibcon#enter sib2, iclass 22, count 0 2006.201.20:55:53.51#ibcon#flushed, iclass 22, count 0 2006.201.20:55:53.51#ibcon#about to write, iclass 22, count 0 2006.201.20:55:53.51#ibcon#wrote, iclass 22, count 0 2006.201.20:55:53.51#ibcon#about to read 3, iclass 22, count 0 2006.201.20:55:53.53#ibcon#read 3, iclass 22, count 0 2006.201.20:55:53.53#ibcon#about to read 4, iclass 22, count 0 2006.201.20:55:53.53#ibcon#read 4, iclass 22, count 0 2006.201.20:55:53.53#ibcon#about to read 5, iclass 22, count 0 2006.201.20:55:53.53#ibcon#read 5, iclass 22, count 0 2006.201.20:55:53.53#ibcon#about to read 6, iclass 22, count 0 2006.201.20:55:53.53#ibcon#read 6, iclass 22, count 0 2006.201.20:55:53.53#ibcon#end of sib2, iclass 22, count 0 2006.201.20:55:53.53#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:55:53.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:55:53.53#ibcon#[25=USB\r\n] 2006.201.20:55:53.53#ibcon#*before write, iclass 22, count 0 2006.201.20:55:53.53#ibcon#enter sib2, iclass 22, count 0 2006.201.20:55:53.53#ibcon#flushed, iclass 22, count 0 2006.201.20:55:53.53#ibcon#about to write, iclass 22, count 0 2006.201.20:55:53.53#ibcon#wrote, iclass 22, count 0 2006.201.20:55:53.53#ibcon#about to read 3, iclass 22, count 0 2006.201.20:55:53.56#ibcon#read 3, iclass 22, count 0 2006.201.20:55:53.56#ibcon#about to read 4, iclass 22, count 0 2006.201.20:55:53.56#ibcon#read 4, iclass 22, count 0 2006.201.20:55:53.56#ibcon#about to read 5, iclass 22, count 0 2006.201.20:55:53.56#ibcon#read 5, iclass 22, count 0 2006.201.20:55:53.56#ibcon#about to read 6, iclass 22, count 0 2006.201.20:55:53.56#ibcon#read 6, iclass 22, count 0 2006.201.20:55:53.56#ibcon#end of sib2, iclass 22, count 0 2006.201.20:55:53.56#ibcon#*after write, iclass 22, count 0 2006.201.20:55:53.56#ibcon#*before return 0, iclass 22, count 0 2006.201.20:55:53.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:53.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:53.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:55:53.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:55:53.56$vck44/valo=6,814.99 2006.201.20:55:53.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.20:55:53.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.20:55:53.56#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:53.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:53.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:53.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:53.56#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:55:53.56#ibcon#first serial, iclass 24, count 0 2006.201.20:55:53.56#ibcon#enter sib2, iclass 24, count 0 2006.201.20:55:53.56#ibcon#flushed, iclass 24, count 0 2006.201.20:55:53.56#ibcon#about to write, iclass 24, count 0 2006.201.20:55:53.56#ibcon#wrote, iclass 24, count 0 2006.201.20:55:53.56#ibcon#about to read 3, iclass 24, count 0 2006.201.20:55:53.58#ibcon#read 3, iclass 24, count 0 2006.201.20:55:53.58#ibcon#about to read 4, iclass 24, count 0 2006.201.20:55:53.58#ibcon#read 4, iclass 24, count 0 2006.201.20:55:53.58#ibcon#about to read 5, iclass 24, count 0 2006.201.20:55:53.58#ibcon#read 5, iclass 24, count 0 2006.201.20:55:53.58#ibcon#about to read 6, iclass 24, count 0 2006.201.20:55:53.58#ibcon#read 6, iclass 24, count 0 2006.201.20:55:53.58#ibcon#end of sib2, iclass 24, count 0 2006.201.20:55:53.58#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:55:53.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:55:53.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.20:55:53.58#ibcon#*before write, iclass 24, count 0 2006.201.20:55:53.58#ibcon#enter sib2, iclass 24, count 0 2006.201.20:55:53.58#ibcon#flushed, iclass 24, count 0 2006.201.20:55:53.58#ibcon#about to write, iclass 24, count 0 2006.201.20:55:53.58#ibcon#wrote, iclass 24, count 0 2006.201.20:55:53.58#ibcon#about to read 3, iclass 24, count 0 2006.201.20:55:53.63#ibcon#read 3, iclass 24, count 0 2006.201.20:55:53.63#ibcon#about to read 4, iclass 24, count 0 2006.201.20:55:53.63#ibcon#read 4, iclass 24, count 0 2006.201.20:55:53.63#ibcon#about to read 5, iclass 24, count 0 2006.201.20:55:53.63#ibcon#read 5, iclass 24, count 0 2006.201.20:55:53.63#ibcon#about to read 6, iclass 24, count 0 2006.201.20:55:53.63#ibcon#read 6, iclass 24, count 0 2006.201.20:55:53.63#ibcon#end of sib2, iclass 24, count 0 2006.201.20:55:53.63#ibcon#*after write, iclass 24, count 0 2006.201.20:55:53.63#ibcon#*before return 0, iclass 24, count 0 2006.201.20:55:53.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:53.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:53.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:55:53.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:55:53.63$vck44/va=6,5 2006.201.20:55:53.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.20:55:53.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.20:55:53.63#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:53.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:53.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:53.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:53.68#ibcon#enter wrdev, iclass 26, count 2 2006.201.20:55:53.68#ibcon#first serial, iclass 26, count 2 2006.201.20:55:53.68#ibcon#enter sib2, iclass 26, count 2 2006.201.20:55:53.68#ibcon#flushed, iclass 26, count 2 2006.201.20:55:53.68#ibcon#about to write, iclass 26, count 2 2006.201.20:55:53.68#ibcon#wrote, iclass 26, count 2 2006.201.20:55:53.68#ibcon#about to read 3, iclass 26, count 2 2006.201.20:55:53.70#ibcon#read 3, iclass 26, count 2 2006.201.20:55:53.70#ibcon#about to read 4, iclass 26, count 2 2006.201.20:55:53.70#ibcon#read 4, iclass 26, count 2 2006.201.20:55:53.70#ibcon#about to read 5, iclass 26, count 2 2006.201.20:55:53.70#ibcon#read 5, iclass 26, count 2 2006.201.20:55:53.70#ibcon#about to read 6, iclass 26, count 2 2006.201.20:55:53.70#ibcon#read 6, iclass 26, count 2 2006.201.20:55:53.70#ibcon#end of sib2, iclass 26, count 2 2006.201.20:55:53.70#ibcon#*mode == 0, iclass 26, count 2 2006.201.20:55:53.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.20:55:53.70#ibcon#[25=AT06-05\r\n] 2006.201.20:55:53.70#ibcon#*before write, iclass 26, count 2 2006.201.20:55:53.70#ibcon#enter sib2, iclass 26, count 2 2006.201.20:55:53.70#ibcon#flushed, iclass 26, count 2 2006.201.20:55:53.70#ibcon#about to write, iclass 26, count 2 2006.201.20:55:53.70#ibcon#wrote, iclass 26, count 2 2006.201.20:55:53.70#ibcon#about to read 3, iclass 26, count 2 2006.201.20:55:53.73#ibcon#read 3, iclass 26, count 2 2006.201.20:55:53.73#ibcon#about to read 4, iclass 26, count 2 2006.201.20:55:53.73#ibcon#read 4, iclass 26, count 2 2006.201.20:55:53.73#ibcon#about to read 5, iclass 26, count 2 2006.201.20:55:53.73#ibcon#read 5, iclass 26, count 2 2006.201.20:55:53.73#ibcon#about to read 6, iclass 26, count 2 2006.201.20:55:53.73#ibcon#read 6, iclass 26, count 2 2006.201.20:55:53.73#ibcon#end of sib2, iclass 26, count 2 2006.201.20:55:53.73#ibcon#*after write, iclass 26, count 2 2006.201.20:55:53.73#ibcon#*before return 0, iclass 26, count 2 2006.201.20:55:53.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:53.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:53.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.20:55:53.73#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:53.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:53.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:53.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:53.85#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:55:53.85#ibcon#first serial, iclass 26, count 0 2006.201.20:55:53.85#ibcon#enter sib2, iclass 26, count 0 2006.201.20:55:53.85#ibcon#flushed, iclass 26, count 0 2006.201.20:55:53.85#ibcon#about to write, iclass 26, count 0 2006.201.20:55:53.85#ibcon#wrote, iclass 26, count 0 2006.201.20:55:53.85#ibcon#about to read 3, iclass 26, count 0 2006.201.20:55:53.87#ibcon#read 3, iclass 26, count 0 2006.201.20:55:53.87#ibcon#about to read 4, iclass 26, count 0 2006.201.20:55:53.87#ibcon#read 4, iclass 26, count 0 2006.201.20:55:53.87#ibcon#about to read 5, iclass 26, count 0 2006.201.20:55:53.87#ibcon#read 5, iclass 26, count 0 2006.201.20:55:53.87#ibcon#about to read 6, iclass 26, count 0 2006.201.20:55:53.87#ibcon#read 6, iclass 26, count 0 2006.201.20:55:53.87#ibcon#end of sib2, iclass 26, count 0 2006.201.20:55:53.87#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:55:53.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:55:53.87#ibcon#[25=USB\r\n] 2006.201.20:55:53.87#ibcon#*before write, iclass 26, count 0 2006.201.20:55:53.87#ibcon#enter sib2, iclass 26, count 0 2006.201.20:55:53.87#ibcon#flushed, iclass 26, count 0 2006.201.20:55:53.87#ibcon#about to write, iclass 26, count 0 2006.201.20:55:53.87#ibcon#wrote, iclass 26, count 0 2006.201.20:55:53.87#ibcon#about to read 3, iclass 26, count 0 2006.201.20:55:53.90#ibcon#read 3, iclass 26, count 0 2006.201.20:55:53.90#ibcon#about to read 4, iclass 26, count 0 2006.201.20:55:53.90#ibcon#read 4, iclass 26, count 0 2006.201.20:55:53.90#ibcon#about to read 5, iclass 26, count 0 2006.201.20:55:53.90#ibcon#read 5, iclass 26, count 0 2006.201.20:55:53.90#ibcon#about to read 6, iclass 26, count 0 2006.201.20:55:53.90#ibcon#read 6, iclass 26, count 0 2006.201.20:55:53.90#ibcon#end of sib2, iclass 26, count 0 2006.201.20:55:53.90#ibcon#*after write, iclass 26, count 0 2006.201.20:55:53.90#ibcon#*before return 0, iclass 26, count 0 2006.201.20:55:53.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:53.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:53.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:55:53.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:55:53.90$vck44/valo=7,864.99 2006.201.20:55:53.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.20:55:53.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.20:55:53.90#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:53.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:53.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:53.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:53.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:55:53.90#ibcon#first serial, iclass 28, count 0 2006.201.20:55:53.90#ibcon#enter sib2, iclass 28, count 0 2006.201.20:55:53.90#ibcon#flushed, iclass 28, count 0 2006.201.20:55:53.90#ibcon#about to write, iclass 28, count 0 2006.201.20:55:53.90#ibcon#wrote, iclass 28, count 0 2006.201.20:55:53.90#ibcon#about to read 3, iclass 28, count 0 2006.201.20:55:53.92#ibcon#read 3, iclass 28, count 0 2006.201.20:55:53.92#ibcon#about to read 4, iclass 28, count 0 2006.201.20:55:53.92#ibcon#read 4, iclass 28, count 0 2006.201.20:55:53.92#ibcon#about to read 5, iclass 28, count 0 2006.201.20:55:53.92#ibcon#read 5, iclass 28, count 0 2006.201.20:55:53.92#ibcon#about to read 6, iclass 28, count 0 2006.201.20:55:53.92#ibcon#read 6, iclass 28, count 0 2006.201.20:55:53.92#ibcon#end of sib2, iclass 28, count 0 2006.201.20:55:53.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:55:53.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:55:53.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.20:55:53.92#ibcon#*before write, iclass 28, count 0 2006.201.20:55:53.92#ibcon#enter sib2, iclass 28, count 0 2006.201.20:55:53.92#ibcon#flushed, iclass 28, count 0 2006.201.20:55:53.92#ibcon#about to write, iclass 28, count 0 2006.201.20:55:53.92#ibcon#wrote, iclass 28, count 0 2006.201.20:55:53.92#ibcon#about to read 3, iclass 28, count 0 2006.201.20:55:53.96#ibcon#read 3, iclass 28, count 0 2006.201.20:55:53.96#ibcon#about to read 4, iclass 28, count 0 2006.201.20:55:53.96#ibcon#read 4, iclass 28, count 0 2006.201.20:55:53.96#ibcon#about to read 5, iclass 28, count 0 2006.201.20:55:53.96#ibcon#read 5, iclass 28, count 0 2006.201.20:55:53.96#ibcon#about to read 6, iclass 28, count 0 2006.201.20:55:53.96#ibcon#read 6, iclass 28, count 0 2006.201.20:55:53.96#ibcon#end of sib2, iclass 28, count 0 2006.201.20:55:53.96#ibcon#*after write, iclass 28, count 0 2006.201.20:55:53.96#ibcon#*before return 0, iclass 28, count 0 2006.201.20:55:53.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:53.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:53.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:55:53.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:55:53.96$vck44/va=7,5 2006.201.20:55:53.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.20:55:53.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.20:55:53.96#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:53.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:54.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:54.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:54.02#ibcon#enter wrdev, iclass 30, count 2 2006.201.20:55:54.02#ibcon#first serial, iclass 30, count 2 2006.201.20:55:54.02#ibcon#enter sib2, iclass 30, count 2 2006.201.20:55:54.02#ibcon#flushed, iclass 30, count 2 2006.201.20:55:54.02#ibcon#about to write, iclass 30, count 2 2006.201.20:55:54.02#ibcon#wrote, iclass 30, count 2 2006.201.20:55:54.02#ibcon#about to read 3, iclass 30, count 2 2006.201.20:55:54.04#ibcon#read 3, iclass 30, count 2 2006.201.20:55:54.04#ibcon#about to read 4, iclass 30, count 2 2006.201.20:55:54.04#ibcon#read 4, iclass 30, count 2 2006.201.20:55:54.04#ibcon#about to read 5, iclass 30, count 2 2006.201.20:55:54.04#ibcon#read 5, iclass 30, count 2 2006.201.20:55:54.04#ibcon#about to read 6, iclass 30, count 2 2006.201.20:55:54.04#ibcon#read 6, iclass 30, count 2 2006.201.20:55:54.04#ibcon#end of sib2, iclass 30, count 2 2006.201.20:55:54.04#ibcon#*mode == 0, iclass 30, count 2 2006.201.20:55:54.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.20:55:54.04#ibcon#[25=AT07-05\r\n] 2006.201.20:55:54.04#ibcon#*before write, iclass 30, count 2 2006.201.20:55:54.04#ibcon#enter sib2, iclass 30, count 2 2006.201.20:55:54.04#ibcon#flushed, iclass 30, count 2 2006.201.20:55:54.04#ibcon#about to write, iclass 30, count 2 2006.201.20:55:54.04#ibcon#wrote, iclass 30, count 2 2006.201.20:55:54.04#ibcon#about to read 3, iclass 30, count 2 2006.201.20:55:54.07#ibcon#read 3, iclass 30, count 2 2006.201.20:55:54.07#ibcon#about to read 4, iclass 30, count 2 2006.201.20:55:54.07#ibcon#read 4, iclass 30, count 2 2006.201.20:55:54.07#ibcon#about to read 5, iclass 30, count 2 2006.201.20:55:54.07#ibcon#read 5, iclass 30, count 2 2006.201.20:55:54.07#ibcon#about to read 6, iclass 30, count 2 2006.201.20:55:54.07#ibcon#read 6, iclass 30, count 2 2006.201.20:55:54.07#ibcon#end of sib2, iclass 30, count 2 2006.201.20:55:54.07#ibcon#*after write, iclass 30, count 2 2006.201.20:55:54.07#ibcon#*before return 0, iclass 30, count 2 2006.201.20:55:54.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:54.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:54.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.20:55:54.07#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:54.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:54.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:54.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:54.19#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:55:54.19#ibcon#first serial, iclass 30, count 0 2006.201.20:55:54.19#ibcon#enter sib2, iclass 30, count 0 2006.201.20:55:54.19#ibcon#flushed, iclass 30, count 0 2006.201.20:55:54.19#ibcon#about to write, iclass 30, count 0 2006.201.20:55:54.19#ibcon#wrote, iclass 30, count 0 2006.201.20:55:54.19#ibcon#about to read 3, iclass 30, count 0 2006.201.20:55:54.21#ibcon#read 3, iclass 30, count 0 2006.201.20:55:54.21#ibcon#about to read 4, iclass 30, count 0 2006.201.20:55:54.21#ibcon#read 4, iclass 30, count 0 2006.201.20:55:54.21#ibcon#about to read 5, iclass 30, count 0 2006.201.20:55:54.21#ibcon#read 5, iclass 30, count 0 2006.201.20:55:54.21#ibcon#about to read 6, iclass 30, count 0 2006.201.20:55:54.21#ibcon#read 6, iclass 30, count 0 2006.201.20:55:54.21#ibcon#end of sib2, iclass 30, count 0 2006.201.20:55:54.21#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:55:54.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:55:54.21#ibcon#[25=USB\r\n] 2006.201.20:55:54.21#ibcon#*before write, iclass 30, count 0 2006.201.20:55:54.21#ibcon#enter sib2, iclass 30, count 0 2006.201.20:55:54.21#ibcon#flushed, iclass 30, count 0 2006.201.20:55:54.21#ibcon#about to write, iclass 30, count 0 2006.201.20:55:54.21#ibcon#wrote, iclass 30, count 0 2006.201.20:55:54.21#ibcon#about to read 3, iclass 30, count 0 2006.201.20:55:54.24#ibcon#read 3, iclass 30, count 0 2006.201.20:55:54.24#ibcon#about to read 4, iclass 30, count 0 2006.201.20:55:54.24#ibcon#read 4, iclass 30, count 0 2006.201.20:55:54.24#ibcon#about to read 5, iclass 30, count 0 2006.201.20:55:54.24#ibcon#read 5, iclass 30, count 0 2006.201.20:55:54.24#ibcon#about to read 6, iclass 30, count 0 2006.201.20:55:54.24#ibcon#read 6, iclass 30, count 0 2006.201.20:55:54.24#ibcon#end of sib2, iclass 30, count 0 2006.201.20:55:54.24#ibcon#*after write, iclass 30, count 0 2006.201.20:55:54.24#ibcon#*before return 0, iclass 30, count 0 2006.201.20:55:54.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:54.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:54.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:55:54.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:55:54.24$vck44/valo=8,884.99 2006.201.20:55:54.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.20:55:54.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.20:55:54.24#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:54.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:54.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:54.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:54.24#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:55:54.24#ibcon#first serial, iclass 32, count 0 2006.201.20:55:54.24#ibcon#enter sib2, iclass 32, count 0 2006.201.20:55:54.24#ibcon#flushed, iclass 32, count 0 2006.201.20:55:54.24#ibcon#about to write, iclass 32, count 0 2006.201.20:55:54.24#ibcon#wrote, iclass 32, count 0 2006.201.20:55:54.24#ibcon#about to read 3, iclass 32, count 0 2006.201.20:55:54.26#ibcon#read 3, iclass 32, count 0 2006.201.20:55:54.26#ibcon#about to read 4, iclass 32, count 0 2006.201.20:55:54.26#ibcon#read 4, iclass 32, count 0 2006.201.20:55:54.26#ibcon#about to read 5, iclass 32, count 0 2006.201.20:55:54.26#ibcon#read 5, iclass 32, count 0 2006.201.20:55:54.26#ibcon#about to read 6, iclass 32, count 0 2006.201.20:55:54.26#ibcon#read 6, iclass 32, count 0 2006.201.20:55:54.26#ibcon#end of sib2, iclass 32, count 0 2006.201.20:55:54.26#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:55:54.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:55:54.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.20:55:54.26#ibcon#*before write, iclass 32, count 0 2006.201.20:55:54.26#ibcon#enter sib2, iclass 32, count 0 2006.201.20:55:54.26#ibcon#flushed, iclass 32, count 0 2006.201.20:55:54.26#ibcon#about to write, iclass 32, count 0 2006.201.20:55:54.26#ibcon#wrote, iclass 32, count 0 2006.201.20:55:54.26#ibcon#about to read 3, iclass 32, count 0 2006.201.20:55:54.30#ibcon#read 3, iclass 32, count 0 2006.201.20:55:54.30#ibcon#about to read 4, iclass 32, count 0 2006.201.20:55:54.30#ibcon#read 4, iclass 32, count 0 2006.201.20:55:54.30#ibcon#about to read 5, iclass 32, count 0 2006.201.20:55:54.30#ibcon#read 5, iclass 32, count 0 2006.201.20:55:54.30#ibcon#about to read 6, iclass 32, count 0 2006.201.20:55:54.30#ibcon#read 6, iclass 32, count 0 2006.201.20:55:54.30#ibcon#end of sib2, iclass 32, count 0 2006.201.20:55:54.30#ibcon#*after write, iclass 32, count 0 2006.201.20:55:54.30#ibcon#*before return 0, iclass 32, count 0 2006.201.20:55:54.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:54.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:54.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:55:54.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:55:54.30$vck44/va=8,4 2006.201.20:55:54.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.20:55:54.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.20:55:54.30#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:54.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:55:54.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:55:54.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:55:54.36#ibcon#enter wrdev, iclass 34, count 2 2006.201.20:55:54.36#ibcon#first serial, iclass 34, count 2 2006.201.20:55:54.36#ibcon#enter sib2, iclass 34, count 2 2006.201.20:55:54.36#ibcon#flushed, iclass 34, count 2 2006.201.20:55:54.36#ibcon#about to write, iclass 34, count 2 2006.201.20:55:54.36#ibcon#wrote, iclass 34, count 2 2006.201.20:55:54.36#ibcon#about to read 3, iclass 34, count 2 2006.201.20:55:54.38#ibcon#read 3, iclass 34, count 2 2006.201.20:55:54.38#ibcon#about to read 4, iclass 34, count 2 2006.201.20:55:54.38#ibcon#read 4, iclass 34, count 2 2006.201.20:55:54.38#ibcon#about to read 5, iclass 34, count 2 2006.201.20:55:54.38#ibcon#read 5, iclass 34, count 2 2006.201.20:55:54.38#ibcon#about to read 6, iclass 34, count 2 2006.201.20:55:54.38#ibcon#read 6, iclass 34, count 2 2006.201.20:55:54.38#ibcon#end of sib2, iclass 34, count 2 2006.201.20:55:54.38#ibcon#*mode == 0, iclass 34, count 2 2006.201.20:55:54.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.20:55:54.38#ibcon#[25=AT08-04\r\n] 2006.201.20:55:54.38#ibcon#*before write, iclass 34, count 2 2006.201.20:55:54.38#ibcon#enter sib2, iclass 34, count 2 2006.201.20:55:54.38#ibcon#flushed, iclass 34, count 2 2006.201.20:55:54.38#ibcon#about to write, iclass 34, count 2 2006.201.20:55:54.38#ibcon#wrote, iclass 34, count 2 2006.201.20:55:54.38#ibcon#about to read 3, iclass 34, count 2 2006.201.20:55:54.41#ibcon#read 3, iclass 34, count 2 2006.201.20:55:54.41#ibcon#about to read 4, iclass 34, count 2 2006.201.20:55:54.41#ibcon#read 4, iclass 34, count 2 2006.201.20:55:54.41#ibcon#about to read 5, iclass 34, count 2 2006.201.20:55:54.41#ibcon#read 5, iclass 34, count 2 2006.201.20:55:54.41#ibcon#about to read 6, iclass 34, count 2 2006.201.20:55:54.41#ibcon#read 6, iclass 34, count 2 2006.201.20:55:54.41#ibcon#end of sib2, iclass 34, count 2 2006.201.20:55:54.41#ibcon#*after write, iclass 34, count 2 2006.201.20:55:54.41#ibcon#*before return 0, iclass 34, count 2 2006.201.20:55:54.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:55:54.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.20:55:54.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.20:55:54.41#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:54.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:55:54.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:55:54.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:55:54.53#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:55:54.53#ibcon#first serial, iclass 34, count 0 2006.201.20:55:54.53#ibcon#enter sib2, iclass 34, count 0 2006.201.20:55:54.53#ibcon#flushed, iclass 34, count 0 2006.201.20:55:54.53#ibcon#about to write, iclass 34, count 0 2006.201.20:55:54.53#ibcon#wrote, iclass 34, count 0 2006.201.20:55:54.53#ibcon#about to read 3, iclass 34, count 0 2006.201.20:55:54.55#ibcon#read 3, iclass 34, count 0 2006.201.20:55:54.55#ibcon#about to read 4, iclass 34, count 0 2006.201.20:55:54.55#ibcon#read 4, iclass 34, count 0 2006.201.20:55:54.55#ibcon#about to read 5, iclass 34, count 0 2006.201.20:55:54.55#ibcon#read 5, iclass 34, count 0 2006.201.20:55:54.55#ibcon#about to read 6, iclass 34, count 0 2006.201.20:55:54.55#ibcon#read 6, iclass 34, count 0 2006.201.20:55:54.55#ibcon#end of sib2, iclass 34, count 0 2006.201.20:55:54.55#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:55:54.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:55:54.55#ibcon#[25=USB\r\n] 2006.201.20:55:54.55#ibcon#*before write, iclass 34, count 0 2006.201.20:55:54.55#ibcon#enter sib2, iclass 34, count 0 2006.201.20:55:54.55#ibcon#flushed, iclass 34, count 0 2006.201.20:55:54.55#ibcon#about to write, iclass 34, count 0 2006.201.20:55:54.55#ibcon#wrote, iclass 34, count 0 2006.201.20:55:54.55#ibcon#about to read 3, iclass 34, count 0 2006.201.20:55:54.58#ibcon#read 3, iclass 34, count 0 2006.201.20:55:54.58#ibcon#about to read 4, iclass 34, count 0 2006.201.20:55:54.58#ibcon#read 4, iclass 34, count 0 2006.201.20:55:54.58#ibcon#about to read 5, iclass 34, count 0 2006.201.20:55:54.58#ibcon#read 5, iclass 34, count 0 2006.201.20:55:54.58#ibcon#about to read 6, iclass 34, count 0 2006.201.20:55:54.58#ibcon#read 6, iclass 34, count 0 2006.201.20:55:54.58#ibcon#end of sib2, iclass 34, count 0 2006.201.20:55:54.58#ibcon#*after write, iclass 34, count 0 2006.201.20:55:54.58#ibcon#*before return 0, iclass 34, count 0 2006.201.20:55:54.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:55:54.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.20:55:54.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:55:54.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:55:54.58$vck44/vblo=1,629.99 2006.201.20:55:54.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.20:55:54.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.20:55:54.58#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:54.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:55:54.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:55:54.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:55:54.58#ibcon#enter wrdev, iclass 36, count 0 2006.201.20:55:54.58#ibcon#first serial, iclass 36, count 0 2006.201.20:55:54.58#ibcon#enter sib2, iclass 36, count 0 2006.201.20:55:54.58#ibcon#flushed, iclass 36, count 0 2006.201.20:55:54.58#ibcon#about to write, iclass 36, count 0 2006.201.20:55:54.58#ibcon#wrote, iclass 36, count 0 2006.201.20:55:54.58#ibcon#about to read 3, iclass 36, count 0 2006.201.20:55:54.60#ibcon#read 3, iclass 36, count 0 2006.201.20:55:54.60#ibcon#about to read 4, iclass 36, count 0 2006.201.20:55:54.60#ibcon#read 4, iclass 36, count 0 2006.201.20:55:54.60#ibcon#about to read 5, iclass 36, count 0 2006.201.20:55:54.60#ibcon#read 5, iclass 36, count 0 2006.201.20:55:54.60#ibcon#about to read 6, iclass 36, count 0 2006.201.20:55:54.60#ibcon#read 6, iclass 36, count 0 2006.201.20:55:54.60#ibcon#end of sib2, iclass 36, count 0 2006.201.20:55:54.60#ibcon#*mode == 0, iclass 36, count 0 2006.201.20:55:54.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.20:55:54.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.20:55:54.60#ibcon#*before write, iclass 36, count 0 2006.201.20:55:54.60#ibcon#enter sib2, iclass 36, count 0 2006.201.20:55:54.60#ibcon#flushed, iclass 36, count 0 2006.201.20:55:54.60#ibcon#about to write, iclass 36, count 0 2006.201.20:55:54.60#ibcon#wrote, iclass 36, count 0 2006.201.20:55:54.60#ibcon#about to read 3, iclass 36, count 0 2006.201.20:55:54.64#ibcon#read 3, iclass 36, count 0 2006.201.20:55:54.64#ibcon#about to read 4, iclass 36, count 0 2006.201.20:55:54.64#ibcon#read 4, iclass 36, count 0 2006.201.20:55:54.64#ibcon#about to read 5, iclass 36, count 0 2006.201.20:55:54.64#ibcon#read 5, iclass 36, count 0 2006.201.20:55:54.64#ibcon#about to read 6, iclass 36, count 0 2006.201.20:55:54.64#ibcon#read 6, iclass 36, count 0 2006.201.20:55:54.64#ibcon#end of sib2, iclass 36, count 0 2006.201.20:55:54.64#ibcon#*after write, iclass 36, count 0 2006.201.20:55:54.64#ibcon#*before return 0, iclass 36, count 0 2006.201.20:55:54.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:55:54.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.20:55:54.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.20:55:54.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.20:55:54.64$vck44/vb=1,4 2006.201.20:55:54.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.20:55:54.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.20:55:54.64#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:54.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:55:54.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:55:54.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:55:54.64#ibcon#enter wrdev, iclass 38, count 2 2006.201.20:55:54.64#ibcon#first serial, iclass 38, count 2 2006.201.20:55:54.64#ibcon#enter sib2, iclass 38, count 2 2006.201.20:55:54.64#ibcon#flushed, iclass 38, count 2 2006.201.20:55:54.64#ibcon#about to write, iclass 38, count 2 2006.201.20:55:54.64#ibcon#wrote, iclass 38, count 2 2006.201.20:55:54.64#ibcon#about to read 3, iclass 38, count 2 2006.201.20:55:54.66#ibcon#read 3, iclass 38, count 2 2006.201.20:55:54.66#ibcon#about to read 4, iclass 38, count 2 2006.201.20:55:54.66#ibcon#read 4, iclass 38, count 2 2006.201.20:55:54.66#ibcon#about to read 5, iclass 38, count 2 2006.201.20:55:54.66#ibcon#read 5, iclass 38, count 2 2006.201.20:55:54.66#ibcon#about to read 6, iclass 38, count 2 2006.201.20:55:54.66#ibcon#read 6, iclass 38, count 2 2006.201.20:55:54.66#ibcon#end of sib2, iclass 38, count 2 2006.201.20:55:54.66#ibcon#*mode == 0, iclass 38, count 2 2006.201.20:55:54.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.20:55:54.66#ibcon#[27=AT01-04\r\n] 2006.201.20:55:54.66#ibcon#*before write, iclass 38, count 2 2006.201.20:55:54.66#ibcon#enter sib2, iclass 38, count 2 2006.201.20:55:54.66#ibcon#flushed, iclass 38, count 2 2006.201.20:55:54.66#ibcon#about to write, iclass 38, count 2 2006.201.20:55:54.66#ibcon#wrote, iclass 38, count 2 2006.201.20:55:54.66#ibcon#about to read 3, iclass 38, count 2 2006.201.20:55:54.69#ibcon#read 3, iclass 38, count 2 2006.201.20:55:54.69#ibcon#about to read 4, iclass 38, count 2 2006.201.20:55:54.69#ibcon#read 4, iclass 38, count 2 2006.201.20:55:54.69#ibcon#about to read 5, iclass 38, count 2 2006.201.20:55:54.69#ibcon#read 5, iclass 38, count 2 2006.201.20:55:54.69#ibcon#about to read 6, iclass 38, count 2 2006.201.20:55:54.69#ibcon#read 6, iclass 38, count 2 2006.201.20:55:54.69#ibcon#end of sib2, iclass 38, count 2 2006.201.20:55:54.69#ibcon#*after write, iclass 38, count 2 2006.201.20:55:54.69#ibcon#*before return 0, iclass 38, count 2 2006.201.20:55:54.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:55:54.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.20:55:54.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.20:55:54.69#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:54.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:55:54.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:55:54.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:55:54.81#ibcon#enter wrdev, iclass 38, count 0 2006.201.20:55:54.81#ibcon#first serial, iclass 38, count 0 2006.201.20:55:54.81#ibcon#enter sib2, iclass 38, count 0 2006.201.20:55:54.81#ibcon#flushed, iclass 38, count 0 2006.201.20:55:54.81#ibcon#about to write, iclass 38, count 0 2006.201.20:55:54.81#ibcon#wrote, iclass 38, count 0 2006.201.20:55:54.81#ibcon#about to read 3, iclass 38, count 0 2006.201.20:55:54.83#ibcon#read 3, iclass 38, count 0 2006.201.20:55:54.83#ibcon#about to read 4, iclass 38, count 0 2006.201.20:55:54.83#ibcon#read 4, iclass 38, count 0 2006.201.20:55:54.83#ibcon#about to read 5, iclass 38, count 0 2006.201.20:55:54.83#ibcon#read 5, iclass 38, count 0 2006.201.20:55:54.83#ibcon#about to read 6, iclass 38, count 0 2006.201.20:55:54.83#ibcon#read 6, iclass 38, count 0 2006.201.20:55:54.83#ibcon#end of sib2, iclass 38, count 0 2006.201.20:55:54.83#ibcon#*mode == 0, iclass 38, count 0 2006.201.20:55:54.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.20:55:54.83#ibcon#[27=USB\r\n] 2006.201.20:55:54.83#ibcon#*before write, iclass 38, count 0 2006.201.20:55:54.83#ibcon#enter sib2, iclass 38, count 0 2006.201.20:55:54.83#ibcon#flushed, iclass 38, count 0 2006.201.20:55:54.83#ibcon#about to write, iclass 38, count 0 2006.201.20:55:54.83#ibcon#wrote, iclass 38, count 0 2006.201.20:55:54.83#ibcon#about to read 3, iclass 38, count 0 2006.201.20:55:54.86#ibcon#read 3, iclass 38, count 0 2006.201.20:55:54.86#ibcon#about to read 4, iclass 38, count 0 2006.201.20:55:54.86#ibcon#read 4, iclass 38, count 0 2006.201.20:55:54.86#ibcon#about to read 5, iclass 38, count 0 2006.201.20:55:54.86#ibcon#read 5, iclass 38, count 0 2006.201.20:55:54.86#ibcon#about to read 6, iclass 38, count 0 2006.201.20:55:54.86#ibcon#read 6, iclass 38, count 0 2006.201.20:55:54.86#ibcon#end of sib2, iclass 38, count 0 2006.201.20:55:54.86#ibcon#*after write, iclass 38, count 0 2006.201.20:55:54.86#ibcon#*before return 0, iclass 38, count 0 2006.201.20:55:54.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:55:54.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.20:55:54.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.20:55:54.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.20:55:54.86$vck44/vblo=2,634.99 2006.201.20:55:54.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.20:55:54.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.20:55:54.86#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:54.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:54.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:54.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:54.86#ibcon#enter wrdev, iclass 40, count 0 2006.201.20:55:54.86#ibcon#first serial, iclass 40, count 0 2006.201.20:55:54.86#ibcon#enter sib2, iclass 40, count 0 2006.201.20:55:54.86#ibcon#flushed, iclass 40, count 0 2006.201.20:55:54.86#ibcon#about to write, iclass 40, count 0 2006.201.20:55:54.86#ibcon#wrote, iclass 40, count 0 2006.201.20:55:54.86#ibcon#about to read 3, iclass 40, count 0 2006.201.20:55:54.88#ibcon#read 3, iclass 40, count 0 2006.201.20:55:54.88#ibcon#about to read 4, iclass 40, count 0 2006.201.20:55:54.88#ibcon#read 4, iclass 40, count 0 2006.201.20:55:54.88#ibcon#about to read 5, iclass 40, count 0 2006.201.20:55:54.88#ibcon#read 5, iclass 40, count 0 2006.201.20:55:54.88#ibcon#about to read 6, iclass 40, count 0 2006.201.20:55:54.88#ibcon#read 6, iclass 40, count 0 2006.201.20:55:54.88#ibcon#end of sib2, iclass 40, count 0 2006.201.20:55:54.88#ibcon#*mode == 0, iclass 40, count 0 2006.201.20:55:54.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.20:55:54.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.20:55:54.88#ibcon#*before write, iclass 40, count 0 2006.201.20:55:54.88#ibcon#enter sib2, iclass 40, count 0 2006.201.20:55:54.88#ibcon#flushed, iclass 40, count 0 2006.201.20:55:54.88#ibcon#about to write, iclass 40, count 0 2006.201.20:55:54.88#ibcon#wrote, iclass 40, count 0 2006.201.20:55:54.88#ibcon#about to read 3, iclass 40, count 0 2006.201.20:55:54.92#ibcon#read 3, iclass 40, count 0 2006.201.20:55:54.92#ibcon#about to read 4, iclass 40, count 0 2006.201.20:55:54.92#ibcon#read 4, iclass 40, count 0 2006.201.20:55:54.92#ibcon#about to read 5, iclass 40, count 0 2006.201.20:55:54.92#ibcon#read 5, iclass 40, count 0 2006.201.20:55:54.92#ibcon#about to read 6, iclass 40, count 0 2006.201.20:55:54.92#ibcon#read 6, iclass 40, count 0 2006.201.20:55:54.92#ibcon#end of sib2, iclass 40, count 0 2006.201.20:55:54.92#ibcon#*after write, iclass 40, count 0 2006.201.20:55:54.92#ibcon#*before return 0, iclass 40, count 0 2006.201.20:55:54.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:54.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.20:55:54.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.20:55:54.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.20:55:54.92$vck44/vb=2,5 2006.201.20:55:54.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.20:55:54.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.20:55:54.92#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:54.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:54.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:54.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:54.98#ibcon#enter wrdev, iclass 4, count 2 2006.201.20:55:54.98#ibcon#first serial, iclass 4, count 2 2006.201.20:55:54.98#ibcon#enter sib2, iclass 4, count 2 2006.201.20:55:54.98#ibcon#flushed, iclass 4, count 2 2006.201.20:55:54.98#ibcon#about to write, iclass 4, count 2 2006.201.20:55:54.98#ibcon#wrote, iclass 4, count 2 2006.201.20:55:54.98#ibcon#about to read 3, iclass 4, count 2 2006.201.20:55:55.00#ibcon#read 3, iclass 4, count 2 2006.201.20:55:55.00#ibcon#about to read 4, iclass 4, count 2 2006.201.20:55:55.00#ibcon#read 4, iclass 4, count 2 2006.201.20:55:55.00#ibcon#about to read 5, iclass 4, count 2 2006.201.20:55:55.00#ibcon#read 5, iclass 4, count 2 2006.201.20:55:55.00#ibcon#about to read 6, iclass 4, count 2 2006.201.20:55:55.00#ibcon#read 6, iclass 4, count 2 2006.201.20:55:55.00#ibcon#end of sib2, iclass 4, count 2 2006.201.20:55:55.00#ibcon#*mode == 0, iclass 4, count 2 2006.201.20:55:55.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.20:55:55.00#ibcon#[27=AT02-05\r\n] 2006.201.20:55:55.00#ibcon#*before write, iclass 4, count 2 2006.201.20:55:55.00#ibcon#enter sib2, iclass 4, count 2 2006.201.20:55:55.00#ibcon#flushed, iclass 4, count 2 2006.201.20:55:55.00#ibcon#about to write, iclass 4, count 2 2006.201.20:55:55.00#ibcon#wrote, iclass 4, count 2 2006.201.20:55:55.00#ibcon#about to read 3, iclass 4, count 2 2006.201.20:55:55.03#ibcon#read 3, iclass 4, count 2 2006.201.20:55:55.03#ibcon#about to read 4, iclass 4, count 2 2006.201.20:55:55.03#ibcon#read 4, iclass 4, count 2 2006.201.20:55:55.03#ibcon#about to read 5, iclass 4, count 2 2006.201.20:55:55.03#ibcon#read 5, iclass 4, count 2 2006.201.20:55:55.03#ibcon#about to read 6, iclass 4, count 2 2006.201.20:55:55.03#ibcon#read 6, iclass 4, count 2 2006.201.20:55:55.03#ibcon#end of sib2, iclass 4, count 2 2006.201.20:55:55.03#ibcon#*after write, iclass 4, count 2 2006.201.20:55:55.03#ibcon#*before return 0, iclass 4, count 2 2006.201.20:55:55.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:55.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.20:55:55.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.20:55:55.03#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:55.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:55.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:55.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:55.15#ibcon#enter wrdev, iclass 4, count 0 2006.201.20:55:55.15#ibcon#first serial, iclass 4, count 0 2006.201.20:55:55.15#ibcon#enter sib2, iclass 4, count 0 2006.201.20:55:55.15#ibcon#flushed, iclass 4, count 0 2006.201.20:55:55.15#ibcon#about to write, iclass 4, count 0 2006.201.20:55:55.15#ibcon#wrote, iclass 4, count 0 2006.201.20:55:55.15#ibcon#about to read 3, iclass 4, count 0 2006.201.20:55:55.17#ibcon#read 3, iclass 4, count 0 2006.201.20:55:55.17#ibcon#about to read 4, iclass 4, count 0 2006.201.20:55:55.17#ibcon#read 4, iclass 4, count 0 2006.201.20:55:55.17#ibcon#about to read 5, iclass 4, count 0 2006.201.20:55:55.17#ibcon#read 5, iclass 4, count 0 2006.201.20:55:55.17#ibcon#about to read 6, iclass 4, count 0 2006.201.20:55:55.17#ibcon#read 6, iclass 4, count 0 2006.201.20:55:55.17#ibcon#end of sib2, iclass 4, count 0 2006.201.20:55:55.17#ibcon#*mode == 0, iclass 4, count 0 2006.201.20:55:55.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.20:55:55.17#ibcon#[27=USB\r\n] 2006.201.20:55:55.17#ibcon#*before write, iclass 4, count 0 2006.201.20:55:55.17#ibcon#enter sib2, iclass 4, count 0 2006.201.20:55:55.17#ibcon#flushed, iclass 4, count 0 2006.201.20:55:55.17#ibcon#about to write, iclass 4, count 0 2006.201.20:55:55.17#ibcon#wrote, iclass 4, count 0 2006.201.20:55:55.17#ibcon#about to read 3, iclass 4, count 0 2006.201.20:55:55.20#ibcon#read 3, iclass 4, count 0 2006.201.20:55:55.20#ibcon#about to read 4, iclass 4, count 0 2006.201.20:55:55.20#ibcon#read 4, iclass 4, count 0 2006.201.20:55:55.20#ibcon#about to read 5, iclass 4, count 0 2006.201.20:55:55.20#ibcon#read 5, iclass 4, count 0 2006.201.20:55:55.20#ibcon#about to read 6, iclass 4, count 0 2006.201.20:55:55.20#ibcon#read 6, iclass 4, count 0 2006.201.20:55:55.20#ibcon#end of sib2, iclass 4, count 0 2006.201.20:55:55.20#ibcon#*after write, iclass 4, count 0 2006.201.20:55:55.20#ibcon#*before return 0, iclass 4, count 0 2006.201.20:55:55.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:55.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.20:55:55.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.20:55:55.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.20:55:55.20$vck44/vblo=3,649.99 2006.201.20:55:55.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.20:55:55.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.20:55:55.20#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:55.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:55.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:55.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:55.20#ibcon#enter wrdev, iclass 6, count 0 2006.201.20:55:55.20#ibcon#first serial, iclass 6, count 0 2006.201.20:55:55.20#ibcon#enter sib2, iclass 6, count 0 2006.201.20:55:55.20#ibcon#flushed, iclass 6, count 0 2006.201.20:55:55.20#ibcon#about to write, iclass 6, count 0 2006.201.20:55:55.20#ibcon#wrote, iclass 6, count 0 2006.201.20:55:55.20#ibcon#about to read 3, iclass 6, count 0 2006.201.20:55:55.22#ibcon#read 3, iclass 6, count 0 2006.201.20:55:55.22#ibcon#about to read 4, iclass 6, count 0 2006.201.20:55:55.22#ibcon#read 4, iclass 6, count 0 2006.201.20:55:55.22#ibcon#about to read 5, iclass 6, count 0 2006.201.20:55:55.22#ibcon#read 5, iclass 6, count 0 2006.201.20:55:55.22#ibcon#about to read 6, iclass 6, count 0 2006.201.20:55:55.22#ibcon#read 6, iclass 6, count 0 2006.201.20:55:55.22#ibcon#end of sib2, iclass 6, count 0 2006.201.20:55:55.22#ibcon#*mode == 0, iclass 6, count 0 2006.201.20:55:55.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.20:55:55.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.20:55:55.22#ibcon#*before write, iclass 6, count 0 2006.201.20:55:55.22#ibcon#enter sib2, iclass 6, count 0 2006.201.20:55:55.22#ibcon#flushed, iclass 6, count 0 2006.201.20:55:55.22#ibcon#about to write, iclass 6, count 0 2006.201.20:55:55.22#ibcon#wrote, iclass 6, count 0 2006.201.20:55:55.22#ibcon#about to read 3, iclass 6, count 0 2006.201.20:55:55.26#ibcon#read 3, iclass 6, count 0 2006.201.20:55:55.26#ibcon#about to read 4, iclass 6, count 0 2006.201.20:55:55.26#ibcon#read 4, iclass 6, count 0 2006.201.20:55:55.26#ibcon#about to read 5, iclass 6, count 0 2006.201.20:55:55.26#ibcon#read 5, iclass 6, count 0 2006.201.20:55:55.26#ibcon#about to read 6, iclass 6, count 0 2006.201.20:55:55.26#ibcon#read 6, iclass 6, count 0 2006.201.20:55:55.26#ibcon#end of sib2, iclass 6, count 0 2006.201.20:55:55.26#ibcon#*after write, iclass 6, count 0 2006.201.20:55:55.26#ibcon#*before return 0, iclass 6, count 0 2006.201.20:55:55.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:55.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.20:55:55.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.20:55:55.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.20:55:55.26$vck44/vb=3,4 2006.201.20:55:55.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.20:55:55.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.20:55:55.26#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:55.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:55.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:55.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:55.32#ibcon#enter wrdev, iclass 10, count 2 2006.201.20:55:55.32#ibcon#first serial, iclass 10, count 2 2006.201.20:55:55.32#ibcon#enter sib2, iclass 10, count 2 2006.201.20:55:55.32#ibcon#flushed, iclass 10, count 2 2006.201.20:55:55.32#ibcon#about to write, iclass 10, count 2 2006.201.20:55:55.32#ibcon#wrote, iclass 10, count 2 2006.201.20:55:55.32#ibcon#about to read 3, iclass 10, count 2 2006.201.20:55:55.34#ibcon#read 3, iclass 10, count 2 2006.201.20:55:55.34#ibcon#about to read 4, iclass 10, count 2 2006.201.20:55:55.34#ibcon#read 4, iclass 10, count 2 2006.201.20:55:55.34#ibcon#about to read 5, iclass 10, count 2 2006.201.20:55:55.34#ibcon#read 5, iclass 10, count 2 2006.201.20:55:55.34#ibcon#about to read 6, iclass 10, count 2 2006.201.20:55:55.34#ibcon#read 6, iclass 10, count 2 2006.201.20:55:55.34#ibcon#end of sib2, iclass 10, count 2 2006.201.20:55:55.34#ibcon#*mode == 0, iclass 10, count 2 2006.201.20:55:55.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.20:55:55.34#ibcon#[27=AT03-04\r\n] 2006.201.20:55:55.34#ibcon#*before write, iclass 10, count 2 2006.201.20:55:55.34#ibcon#enter sib2, iclass 10, count 2 2006.201.20:55:55.34#ibcon#flushed, iclass 10, count 2 2006.201.20:55:55.34#ibcon#about to write, iclass 10, count 2 2006.201.20:55:55.34#ibcon#wrote, iclass 10, count 2 2006.201.20:55:55.34#ibcon#about to read 3, iclass 10, count 2 2006.201.20:55:55.37#ibcon#read 3, iclass 10, count 2 2006.201.20:55:55.37#ibcon#about to read 4, iclass 10, count 2 2006.201.20:55:55.37#ibcon#read 4, iclass 10, count 2 2006.201.20:55:55.37#ibcon#about to read 5, iclass 10, count 2 2006.201.20:55:55.37#ibcon#read 5, iclass 10, count 2 2006.201.20:55:55.37#ibcon#about to read 6, iclass 10, count 2 2006.201.20:55:55.37#ibcon#read 6, iclass 10, count 2 2006.201.20:55:55.37#ibcon#end of sib2, iclass 10, count 2 2006.201.20:55:55.37#ibcon#*after write, iclass 10, count 2 2006.201.20:55:55.37#ibcon#*before return 0, iclass 10, count 2 2006.201.20:55:55.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:55.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.20:55:55.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.20:55:55.37#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:55.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:55.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:55.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:55.49#ibcon#enter wrdev, iclass 10, count 0 2006.201.20:55:55.49#ibcon#first serial, iclass 10, count 0 2006.201.20:55:55.49#ibcon#enter sib2, iclass 10, count 0 2006.201.20:55:55.49#ibcon#flushed, iclass 10, count 0 2006.201.20:55:55.49#ibcon#about to write, iclass 10, count 0 2006.201.20:55:55.49#ibcon#wrote, iclass 10, count 0 2006.201.20:55:55.49#ibcon#about to read 3, iclass 10, count 0 2006.201.20:55:55.51#ibcon#read 3, iclass 10, count 0 2006.201.20:55:55.51#ibcon#about to read 4, iclass 10, count 0 2006.201.20:55:55.51#ibcon#read 4, iclass 10, count 0 2006.201.20:55:55.51#ibcon#about to read 5, iclass 10, count 0 2006.201.20:55:55.51#ibcon#read 5, iclass 10, count 0 2006.201.20:55:55.51#ibcon#about to read 6, iclass 10, count 0 2006.201.20:55:55.51#ibcon#read 6, iclass 10, count 0 2006.201.20:55:55.51#ibcon#end of sib2, iclass 10, count 0 2006.201.20:55:55.51#ibcon#*mode == 0, iclass 10, count 0 2006.201.20:55:55.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.20:55:55.51#ibcon#[27=USB\r\n] 2006.201.20:55:55.51#ibcon#*before write, iclass 10, count 0 2006.201.20:55:55.51#ibcon#enter sib2, iclass 10, count 0 2006.201.20:55:55.51#ibcon#flushed, iclass 10, count 0 2006.201.20:55:55.51#ibcon#about to write, iclass 10, count 0 2006.201.20:55:55.51#ibcon#wrote, iclass 10, count 0 2006.201.20:55:55.51#ibcon#about to read 3, iclass 10, count 0 2006.201.20:55:55.54#ibcon#read 3, iclass 10, count 0 2006.201.20:55:55.54#ibcon#about to read 4, iclass 10, count 0 2006.201.20:55:55.54#ibcon#read 4, iclass 10, count 0 2006.201.20:55:55.54#ibcon#about to read 5, iclass 10, count 0 2006.201.20:55:55.54#ibcon#read 5, iclass 10, count 0 2006.201.20:55:55.54#ibcon#about to read 6, iclass 10, count 0 2006.201.20:55:55.54#ibcon#read 6, iclass 10, count 0 2006.201.20:55:55.54#ibcon#end of sib2, iclass 10, count 0 2006.201.20:55:55.54#ibcon#*after write, iclass 10, count 0 2006.201.20:55:55.54#ibcon#*before return 0, iclass 10, count 0 2006.201.20:55:55.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:55.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.20:55:55.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.20:55:55.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.20:55:55.54$vck44/vblo=4,679.99 2006.201.20:55:55.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.20:55:55.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.20:55:55.54#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:55.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:55.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:55.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:55.54#ibcon#enter wrdev, iclass 12, count 0 2006.201.20:55:55.54#ibcon#first serial, iclass 12, count 0 2006.201.20:55:55.54#ibcon#enter sib2, iclass 12, count 0 2006.201.20:55:55.54#ibcon#flushed, iclass 12, count 0 2006.201.20:55:55.54#ibcon#about to write, iclass 12, count 0 2006.201.20:55:55.54#ibcon#wrote, iclass 12, count 0 2006.201.20:55:55.54#ibcon#about to read 3, iclass 12, count 0 2006.201.20:55:55.56#ibcon#read 3, iclass 12, count 0 2006.201.20:55:55.56#ibcon#about to read 4, iclass 12, count 0 2006.201.20:55:55.56#ibcon#read 4, iclass 12, count 0 2006.201.20:55:55.56#ibcon#about to read 5, iclass 12, count 0 2006.201.20:55:55.56#ibcon#read 5, iclass 12, count 0 2006.201.20:55:55.56#ibcon#about to read 6, iclass 12, count 0 2006.201.20:55:55.56#ibcon#read 6, iclass 12, count 0 2006.201.20:55:55.56#ibcon#end of sib2, iclass 12, count 0 2006.201.20:55:55.56#ibcon#*mode == 0, iclass 12, count 0 2006.201.20:55:55.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.20:55:55.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.20:55:55.56#ibcon#*before write, iclass 12, count 0 2006.201.20:55:55.56#ibcon#enter sib2, iclass 12, count 0 2006.201.20:55:55.56#ibcon#flushed, iclass 12, count 0 2006.201.20:55:55.56#ibcon#about to write, iclass 12, count 0 2006.201.20:55:55.56#ibcon#wrote, iclass 12, count 0 2006.201.20:55:55.56#ibcon#about to read 3, iclass 12, count 0 2006.201.20:55:55.61#ibcon#read 3, iclass 12, count 0 2006.201.20:55:55.61#ibcon#about to read 4, iclass 12, count 0 2006.201.20:55:55.61#ibcon#read 4, iclass 12, count 0 2006.201.20:55:55.61#ibcon#about to read 5, iclass 12, count 0 2006.201.20:55:55.61#ibcon#read 5, iclass 12, count 0 2006.201.20:55:55.61#ibcon#about to read 6, iclass 12, count 0 2006.201.20:55:55.61#ibcon#read 6, iclass 12, count 0 2006.201.20:55:55.61#ibcon#end of sib2, iclass 12, count 0 2006.201.20:55:55.61#ibcon#*after write, iclass 12, count 0 2006.201.20:55:55.61#ibcon#*before return 0, iclass 12, count 0 2006.201.20:55:55.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:55.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.20:55:55.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.20:55:55.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.20:55:55.61$vck44/vb=4,5 2006.201.20:55:55.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.20:55:55.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.20:55:55.61#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:55.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:55.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:55.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:55.66#ibcon#enter wrdev, iclass 14, count 2 2006.201.20:55:55.66#ibcon#first serial, iclass 14, count 2 2006.201.20:55:55.66#ibcon#enter sib2, iclass 14, count 2 2006.201.20:55:55.66#ibcon#flushed, iclass 14, count 2 2006.201.20:55:55.66#ibcon#about to write, iclass 14, count 2 2006.201.20:55:55.66#ibcon#wrote, iclass 14, count 2 2006.201.20:55:55.66#ibcon#about to read 3, iclass 14, count 2 2006.201.20:55:55.68#ibcon#read 3, iclass 14, count 2 2006.201.20:55:55.68#ibcon#about to read 4, iclass 14, count 2 2006.201.20:55:55.68#ibcon#read 4, iclass 14, count 2 2006.201.20:55:55.68#ibcon#about to read 5, iclass 14, count 2 2006.201.20:55:55.68#ibcon#read 5, iclass 14, count 2 2006.201.20:55:55.68#ibcon#about to read 6, iclass 14, count 2 2006.201.20:55:55.68#ibcon#read 6, iclass 14, count 2 2006.201.20:55:55.68#ibcon#end of sib2, iclass 14, count 2 2006.201.20:55:55.68#ibcon#*mode == 0, iclass 14, count 2 2006.201.20:55:55.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.20:55:55.68#ibcon#[27=AT04-05\r\n] 2006.201.20:55:55.68#ibcon#*before write, iclass 14, count 2 2006.201.20:55:55.68#ibcon#enter sib2, iclass 14, count 2 2006.201.20:55:55.68#ibcon#flushed, iclass 14, count 2 2006.201.20:55:55.68#ibcon#about to write, iclass 14, count 2 2006.201.20:55:55.68#ibcon#wrote, iclass 14, count 2 2006.201.20:55:55.68#ibcon#about to read 3, iclass 14, count 2 2006.201.20:55:55.71#ibcon#read 3, iclass 14, count 2 2006.201.20:55:55.71#ibcon#about to read 4, iclass 14, count 2 2006.201.20:55:55.71#ibcon#read 4, iclass 14, count 2 2006.201.20:55:55.71#ibcon#about to read 5, iclass 14, count 2 2006.201.20:55:55.71#ibcon#read 5, iclass 14, count 2 2006.201.20:55:55.71#ibcon#about to read 6, iclass 14, count 2 2006.201.20:55:55.71#ibcon#read 6, iclass 14, count 2 2006.201.20:55:55.71#ibcon#end of sib2, iclass 14, count 2 2006.201.20:55:55.71#ibcon#*after write, iclass 14, count 2 2006.201.20:55:55.71#ibcon#*before return 0, iclass 14, count 2 2006.201.20:55:55.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:55.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.20:55:55.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.20:55:55.71#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:55.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:55.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:55.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:55.83#ibcon#enter wrdev, iclass 14, count 0 2006.201.20:55:55.83#ibcon#first serial, iclass 14, count 0 2006.201.20:55:55.83#ibcon#enter sib2, iclass 14, count 0 2006.201.20:55:55.83#ibcon#flushed, iclass 14, count 0 2006.201.20:55:55.83#ibcon#about to write, iclass 14, count 0 2006.201.20:55:55.83#ibcon#wrote, iclass 14, count 0 2006.201.20:55:55.83#ibcon#about to read 3, iclass 14, count 0 2006.201.20:55:55.85#ibcon#read 3, iclass 14, count 0 2006.201.20:55:55.85#ibcon#about to read 4, iclass 14, count 0 2006.201.20:55:55.85#ibcon#read 4, iclass 14, count 0 2006.201.20:55:55.85#ibcon#about to read 5, iclass 14, count 0 2006.201.20:55:55.85#ibcon#read 5, iclass 14, count 0 2006.201.20:55:55.85#ibcon#about to read 6, iclass 14, count 0 2006.201.20:55:55.85#ibcon#read 6, iclass 14, count 0 2006.201.20:55:55.85#ibcon#end of sib2, iclass 14, count 0 2006.201.20:55:55.85#ibcon#*mode == 0, iclass 14, count 0 2006.201.20:55:55.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.20:55:55.85#ibcon#[27=USB\r\n] 2006.201.20:55:55.85#ibcon#*before write, iclass 14, count 0 2006.201.20:55:55.85#ibcon#enter sib2, iclass 14, count 0 2006.201.20:55:55.85#ibcon#flushed, iclass 14, count 0 2006.201.20:55:55.85#ibcon#about to write, iclass 14, count 0 2006.201.20:55:55.85#ibcon#wrote, iclass 14, count 0 2006.201.20:55:55.85#ibcon#about to read 3, iclass 14, count 0 2006.201.20:55:55.88#ibcon#read 3, iclass 14, count 0 2006.201.20:55:55.88#ibcon#about to read 4, iclass 14, count 0 2006.201.20:55:55.88#ibcon#read 4, iclass 14, count 0 2006.201.20:55:55.88#ibcon#about to read 5, iclass 14, count 0 2006.201.20:55:55.88#ibcon#read 5, iclass 14, count 0 2006.201.20:55:55.88#ibcon#about to read 6, iclass 14, count 0 2006.201.20:55:55.88#ibcon#read 6, iclass 14, count 0 2006.201.20:55:55.88#ibcon#end of sib2, iclass 14, count 0 2006.201.20:55:55.88#ibcon#*after write, iclass 14, count 0 2006.201.20:55:55.88#ibcon#*before return 0, iclass 14, count 0 2006.201.20:55:55.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:55.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.20:55:55.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.20:55:55.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.20:55:55.88$vck44/vblo=5,709.99 2006.201.20:55:55.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.20:55:55.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.20:55:55.88#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:55.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:55.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:55.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:55.88#ibcon#enter wrdev, iclass 16, count 0 2006.201.20:55:55.88#ibcon#first serial, iclass 16, count 0 2006.201.20:55:55.88#ibcon#enter sib2, iclass 16, count 0 2006.201.20:55:55.88#ibcon#flushed, iclass 16, count 0 2006.201.20:55:55.88#ibcon#about to write, iclass 16, count 0 2006.201.20:55:55.88#ibcon#wrote, iclass 16, count 0 2006.201.20:55:55.88#ibcon#about to read 3, iclass 16, count 0 2006.201.20:55:55.90#ibcon#read 3, iclass 16, count 0 2006.201.20:55:55.90#ibcon#about to read 4, iclass 16, count 0 2006.201.20:55:55.90#ibcon#read 4, iclass 16, count 0 2006.201.20:55:55.90#ibcon#about to read 5, iclass 16, count 0 2006.201.20:55:55.90#ibcon#read 5, iclass 16, count 0 2006.201.20:55:55.90#ibcon#about to read 6, iclass 16, count 0 2006.201.20:55:55.90#ibcon#read 6, iclass 16, count 0 2006.201.20:55:55.90#ibcon#end of sib2, iclass 16, count 0 2006.201.20:55:55.90#ibcon#*mode == 0, iclass 16, count 0 2006.201.20:55:55.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.20:55:55.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.20:55:55.90#ibcon#*before write, iclass 16, count 0 2006.201.20:55:55.90#ibcon#enter sib2, iclass 16, count 0 2006.201.20:55:55.90#ibcon#flushed, iclass 16, count 0 2006.201.20:55:55.90#ibcon#about to write, iclass 16, count 0 2006.201.20:55:55.90#ibcon#wrote, iclass 16, count 0 2006.201.20:55:55.90#ibcon#about to read 3, iclass 16, count 0 2006.201.20:55:55.94#ibcon#read 3, iclass 16, count 0 2006.201.20:55:55.94#ibcon#about to read 4, iclass 16, count 0 2006.201.20:55:55.94#ibcon#read 4, iclass 16, count 0 2006.201.20:55:55.94#ibcon#about to read 5, iclass 16, count 0 2006.201.20:55:55.94#ibcon#read 5, iclass 16, count 0 2006.201.20:55:55.94#ibcon#about to read 6, iclass 16, count 0 2006.201.20:55:55.94#ibcon#read 6, iclass 16, count 0 2006.201.20:55:55.94#ibcon#end of sib2, iclass 16, count 0 2006.201.20:55:55.94#ibcon#*after write, iclass 16, count 0 2006.201.20:55:55.94#ibcon#*before return 0, iclass 16, count 0 2006.201.20:55:55.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:55.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.20:55:55.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.20:55:55.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.20:55:55.94$vck44/vb=5,4 2006.201.20:55:55.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.20:55:55.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.20:55:55.94#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:55.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:56.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:56.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:56.00#ibcon#enter wrdev, iclass 18, count 2 2006.201.20:55:56.00#ibcon#first serial, iclass 18, count 2 2006.201.20:55:56.00#ibcon#enter sib2, iclass 18, count 2 2006.201.20:55:56.00#ibcon#flushed, iclass 18, count 2 2006.201.20:55:56.00#ibcon#about to write, iclass 18, count 2 2006.201.20:55:56.00#ibcon#wrote, iclass 18, count 2 2006.201.20:55:56.00#ibcon#about to read 3, iclass 18, count 2 2006.201.20:55:56.02#ibcon#read 3, iclass 18, count 2 2006.201.20:55:56.02#ibcon#about to read 4, iclass 18, count 2 2006.201.20:55:56.02#ibcon#read 4, iclass 18, count 2 2006.201.20:55:56.02#ibcon#about to read 5, iclass 18, count 2 2006.201.20:55:56.02#ibcon#read 5, iclass 18, count 2 2006.201.20:55:56.02#ibcon#about to read 6, iclass 18, count 2 2006.201.20:55:56.02#ibcon#read 6, iclass 18, count 2 2006.201.20:55:56.02#ibcon#end of sib2, iclass 18, count 2 2006.201.20:55:56.02#ibcon#*mode == 0, iclass 18, count 2 2006.201.20:55:56.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.20:55:56.02#ibcon#[27=AT05-04\r\n] 2006.201.20:55:56.02#ibcon#*before write, iclass 18, count 2 2006.201.20:55:56.02#ibcon#enter sib2, iclass 18, count 2 2006.201.20:55:56.02#ibcon#flushed, iclass 18, count 2 2006.201.20:55:56.02#ibcon#about to write, iclass 18, count 2 2006.201.20:55:56.02#ibcon#wrote, iclass 18, count 2 2006.201.20:55:56.02#ibcon#about to read 3, iclass 18, count 2 2006.201.20:55:56.05#ibcon#read 3, iclass 18, count 2 2006.201.20:55:56.05#ibcon#about to read 4, iclass 18, count 2 2006.201.20:55:56.05#ibcon#read 4, iclass 18, count 2 2006.201.20:55:56.05#ibcon#about to read 5, iclass 18, count 2 2006.201.20:55:56.05#ibcon#read 5, iclass 18, count 2 2006.201.20:55:56.05#ibcon#about to read 6, iclass 18, count 2 2006.201.20:55:56.05#ibcon#read 6, iclass 18, count 2 2006.201.20:55:56.05#ibcon#end of sib2, iclass 18, count 2 2006.201.20:55:56.05#ibcon#*after write, iclass 18, count 2 2006.201.20:55:56.05#ibcon#*before return 0, iclass 18, count 2 2006.201.20:55:56.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:56.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.20:55:56.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.20:55:56.05#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:56.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:56.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:56.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:56.17#ibcon#enter wrdev, iclass 18, count 0 2006.201.20:55:56.17#ibcon#first serial, iclass 18, count 0 2006.201.20:55:56.17#ibcon#enter sib2, iclass 18, count 0 2006.201.20:55:56.17#ibcon#flushed, iclass 18, count 0 2006.201.20:55:56.17#ibcon#about to write, iclass 18, count 0 2006.201.20:55:56.17#ibcon#wrote, iclass 18, count 0 2006.201.20:55:56.17#ibcon#about to read 3, iclass 18, count 0 2006.201.20:55:56.19#ibcon#read 3, iclass 18, count 0 2006.201.20:55:56.19#ibcon#about to read 4, iclass 18, count 0 2006.201.20:55:56.19#ibcon#read 4, iclass 18, count 0 2006.201.20:55:56.19#ibcon#about to read 5, iclass 18, count 0 2006.201.20:55:56.19#ibcon#read 5, iclass 18, count 0 2006.201.20:55:56.19#ibcon#about to read 6, iclass 18, count 0 2006.201.20:55:56.19#ibcon#read 6, iclass 18, count 0 2006.201.20:55:56.19#ibcon#end of sib2, iclass 18, count 0 2006.201.20:55:56.19#ibcon#*mode == 0, iclass 18, count 0 2006.201.20:55:56.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.20:55:56.19#ibcon#[27=USB\r\n] 2006.201.20:55:56.19#ibcon#*before write, iclass 18, count 0 2006.201.20:55:56.19#ibcon#enter sib2, iclass 18, count 0 2006.201.20:55:56.19#ibcon#flushed, iclass 18, count 0 2006.201.20:55:56.19#ibcon#about to write, iclass 18, count 0 2006.201.20:55:56.19#ibcon#wrote, iclass 18, count 0 2006.201.20:55:56.19#ibcon#about to read 3, iclass 18, count 0 2006.201.20:55:56.22#ibcon#read 3, iclass 18, count 0 2006.201.20:55:56.22#ibcon#about to read 4, iclass 18, count 0 2006.201.20:55:56.22#ibcon#read 4, iclass 18, count 0 2006.201.20:55:56.22#ibcon#about to read 5, iclass 18, count 0 2006.201.20:55:56.22#ibcon#read 5, iclass 18, count 0 2006.201.20:55:56.22#ibcon#about to read 6, iclass 18, count 0 2006.201.20:55:56.22#ibcon#read 6, iclass 18, count 0 2006.201.20:55:56.22#ibcon#end of sib2, iclass 18, count 0 2006.201.20:55:56.22#ibcon#*after write, iclass 18, count 0 2006.201.20:55:56.22#ibcon#*before return 0, iclass 18, count 0 2006.201.20:55:56.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:56.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.20:55:56.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.20:55:56.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.20:55:56.22$vck44/vblo=6,719.99 2006.201.20:55:56.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.20:55:56.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.20:55:56.22#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:56.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:56.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:56.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:56.22#ibcon#enter wrdev, iclass 20, count 0 2006.201.20:55:56.22#ibcon#first serial, iclass 20, count 0 2006.201.20:55:56.22#ibcon#enter sib2, iclass 20, count 0 2006.201.20:55:56.22#ibcon#flushed, iclass 20, count 0 2006.201.20:55:56.22#ibcon#about to write, iclass 20, count 0 2006.201.20:55:56.22#ibcon#wrote, iclass 20, count 0 2006.201.20:55:56.22#ibcon#about to read 3, iclass 20, count 0 2006.201.20:55:56.24#ibcon#read 3, iclass 20, count 0 2006.201.20:55:56.24#ibcon#about to read 4, iclass 20, count 0 2006.201.20:55:56.24#ibcon#read 4, iclass 20, count 0 2006.201.20:55:56.24#ibcon#about to read 5, iclass 20, count 0 2006.201.20:55:56.24#ibcon#read 5, iclass 20, count 0 2006.201.20:55:56.24#ibcon#about to read 6, iclass 20, count 0 2006.201.20:55:56.24#ibcon#read 6, iclass 20, count 0 2006.201.20:55:56.24#ibcon#end of sib2, iclass 20, count 0 2006.201.20:55:56.24#ibcon#*mode == 0, iclass 20, count 0 2006.201.20:55:56.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.20:55:56.24#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.20:55:56.24#ibcon#*before write, iclass 20, count 0 2006.201.20:55:56.24#ibcon#enter sib2, iclass 20, count 0 2006.201.20:55:56.24#ibcon#flushed, iclass 20, count 0 2006.201.20:55:56.24#ibcon#about to write, iclass 20, count 0 2006.201.20:55:56.24#ibcon#wrote, iclass 20, count 0 2006.201.20:55:56.24#ibcon#about to read 3, iclass 20, count 0 2006.201.20:55:56.28#ibcon#read 3, iclass 20, count 0 2006.201.20:55:56.28#ibcon#about to read 4, iclass 20, count 0 2006.201.20:55:56.28#ibcon#read 4, iclass 20, count 0 2006.201.20:55:56.28#ibcon#about to read 5, iclass 20, count 0 2006.201.20:55:56.28#ibcon#read 5, iclass 20, count 0 2006.201.20:55:56.28#ibcon#about to read 6, iclass 20, count 0 2006.201.20:55:56.28#ibcon#read 6, iclass 20, count 0 2006.201.20:55:56.28#ibcon#end of sib2, iclass 20, count 0 2006.201.20:55:56.28#ibcon#*after write, iclass 20, count 0 2006.201.20:55:56.28#ibcon#*before return 0, iclass 20, count 0 2006.201.20:55:56.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:56.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.20:55:56.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.20:55:56.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.20:55:56.28$vck44/vb=6,4 2006.201.20:55:56.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.20:55:56.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.20:55:56.28#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:56.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:56.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:56.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:56.34#ibcon#enter wrdev, iclass 22, count 2 2006.201.20:55:56.34#ibcon#first serial, iclass 22, count 2 2006.201.20:55:56.34#ibcon#enter sib2, iclass 22, count 2 2006.201.20:55:56.34#ibcon#flushed, iclass 22, count 2 2006.201.20:55:56.34#ibcon#about to write, iclass 22, count 2 2006.201.20:55:56.34#ibcon#wrote, iclass 22, count 2 2006.201.20:55:56.34#ibcon#about to read 3, iclass 22, count 2 2006.201.20:55:56.36#ibcon#read 3, iclass 22, count 2 2006.201.20:55:56.36#ibcon#about to read 4, iclass 22, count 2 2006.201.20:55:56.36#ibcon#read 4, iclass 22, count 2 2006.201.20:55:56.36#ibcon#about to read 5, iclass 22, count 2 2006.201.20:55:56.36#ibcon#read 5, iclass 22, count 2 2006.201.20:55:56.36#ibcon#about to read 6, iclass 22, count 2 2006.201.20:55:56.36#ibcon#read 6, iclass 22, count 2 2006.201.20:55:56.36#ibcon#end of sib2, iclass 22, count 2 2006.201.20:55:56.36#ibcon#*mode == 0, iclass 22, count 2 2006.201.20:55:56.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.20:55:56.36#ibcon#[27=AT06-04\r\n] 2006.201.20:55:56.36#ibcon#*before write, iclass 22, count 2 2006.201.20:55:56.36#ibcon#enter sib2, iclass 22, count 2 2006.201.20:55:56.36#ibcon#flushed, iclass 22, count 2 2006.201.20:55:56.36#ibcon#about to write, iclass 22, count 2 2006.201.20:55:56.36#ibcon#wrote, iclass 22, count 2 2006.201.20:55:56.36#ibcon#about to read 3, iclass 22, count 2 2006.201.20:55:56.39#ibcon#read 3, iclass 22, count 2 2006.201.20:55:56.39#ibcon#about to read 4, iclass 22, count 2 2006.201.20:55:56.39#ibcon#read 4, iclass 22, count 2 2006.201.20:55:56.39#ibcon#about to read 5, iclass 22, count 2 2006.201.20:55:56.39#ibcon#read 5, iclass 22, count 2 2006.201.20:55:56.39#ibcon#about to read 6, iclass 22, count 2 2006.201.20:55:56.39#ibcon#read 6, iclass 22, count 2 2006.201.20:55:56.39#ibcon#end of sib2, iclass 22, count 2 2006.201.20:55:56.39#ibcon#*after write, iclass 22, count 2 2006.201.20:55:56.39#ibcon#*before return 0, iclass 22, count 2 2006.201.20:55:56.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:56.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.20:55:56.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.20:55:56.39#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:56.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:56.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:56.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:56.51#ibcon#enter wrdev, iclass 22, count 0 2006.201.20:55:56.51#ibcon#first serial, iclass 22, count 0 2006.201.20:55:56.51#ibcon#enter sib2, iclass 22, count 0 2006.201.20:55:56.51#ibcon#flushed, iclass 22, count 0 2006.201.20:55:56.51#ibcon#about to write, iclass 22, count 0 2006.201.20:55:56.51#ibcon#wrote, iclass 22, count 0 2006.201.20:55:56.51#ibcon#about to read 3, iclass 22, count 0 2006.201.20:55:56.53#ibcon#read 3, iclass 22, count 0 2006.201.20:55:56.53#ibcon#about to read 4, iclass 22, count 0 2006.201.20:55:56.53#ibcon#read 4, iclass 22, count 0 2006.201.20:55:56.53#ibcon#about to read 5, iclass 22, count 0 2006.201.20:55:56.53#ibcon#read 5, iclass 22, count 0 2006.201.20:55:56.53#ibcon#about to read 6, iclass 22, count 0 2006.201.20:55:56.53#ibcon#read 6, iclass 22, count 0 2006.201.20:55:56.53#ibcon#end of sib2, iclass 22, count 0 2006.201.20:55:56.53#ibcon#*mode == 0, iclass 22, count 0 2006.201.20:55:56.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.20:55:56.53#ibcon#[27=USB\r\n] 2006.201.20:55:56.53#ibcon#*before write, iclass 22, count 0 2006.201.20:55:56.53#ibcon#enter sib2, iclass 22, count 0 2006.201.20:55:56.53#ibcon#flushed, iclass 22, count 0 2006.201.20:55:56.53#ibcon#about to write, iclass 22, count 0 2006.201.20:55:56.53#ibcon#wrote, iclass 22, count 0 2006.201.20:55:56.53#ibcon#about to read 3, iclass 22, count 0 2006.201.20:55:56.56#ibcon#read 3, iclass 22, count 0 2006.201.20:55:56.56#ibcon#about to read 4, iclass 22, count 0 2006.201.20:55:56.56#ibcon#read 4, iclass 22, count 0 2006.201.20:55:56.56#ibcon#about to read 5, iclass 22, count 0 2006.201.20:55:56.56#ibcon#read 5, iclass 22, count 0 2006.201.20:55:56.56#ibcon#about to read 6, iclass 22, count 0 2006.201.20:55:56.56#ibcon#read 6, iclass 22, count 0 2006.201.20:55:56.56#ibcon#end of sib2, iclass 22, count 0 2006.201.20:55:56.56#ibcon#*after write, iclass 22, count 0 2006.201.20:55:56.56#ibcon#*before return 0, iclass 22, count 0 2006.201.20:55:56.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:56.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.20:55:56.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.20:55:56.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.20:55:56.56$vck44/vblo=7,734.99 2006.201.20:55:56.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.20:55:56.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.20:55:56.56#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:56.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:56.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:56.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:56.56#ibcon#enter wrdev, iclass 24, count 0 2006.201.20:55:56.56#ibcon#first serial, iclass 24, count 0 2006.201.20:55:56.56#ibcon#enter sib2, iclass 24, count 0 2006.201.20:55:56.56#ibcon#flushed, iclass 24, count 0 2006.201.20:55:56.56#ibcon#about to write, iclass 24, count 0 2006.201.20:55:56.56#ibcon#wrote, iclass 24, count 0 2006.201.20:55:56.56#ibcon#about to read 3, iclass 24, count 0 2006.201.20:55:56.58#ibcon#read 3, iclass 24, count 0 2006.201.20:55:56.58#ibcon#about to read 4, iclass 24, count 0 2006.201.20:55:56.58#ibcon#read 4, iclass 24, count 0 2006.201.20:55:56.58#ibcon#about to read 5, iclass 24, count 0 2006.201.20:55:56.58#ibcon#read 5, iclass 24, count 0 2006.201.20:55:56.58#ibcon#about to read 6, iclass 24, count 0 2006.201.20:55:56.58#ibcon#read 6, iclass 24, count 0 2006.201.20:55:56.58#ibcon#end of sib2, iclass 24, count 0 2006.201.20:55:56.58#ibcon#*mode == 0, iclass 24, count 0 2006.201.20:55:56.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.20:55:56.58#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.20:55:56.58#ibcon#*before write, iclass 24, count 0 2006.201.20:55:56.58#ibcon#enter sib2, iclass 24, count 0 2006.201.20:55:56.58#ibcon#flushed, iclass 24, count 0 2006.201.20:55:56.58#ibcon#about to write, iclass 24, count 0 2006.201.20:55:56.58#ibcon#wrote, iclass 24, count 0 2006.201.20:55:56.58#ibcon#about to read 3, iclass 24, count 0 2006.201.20:55:56.63#ibcon#read 3, iclass 24, count 0 2006.201.20:55:56.63#ibcon#about to read 4, iclass 24, count 0 2006.201.20:55:56.63#ibcon#read 4, iclass 24, count 0 2006.201.20:55:56.63#ibcon#about to read 5, iclass 24, count 0 2006.201.20:55:56.63#ibcon#read 5, iclass 24, count 0 2006.201.20:55:56.63#ibcon#about to read 6, iclass 24, count 0 2006.201.20:55:56.63#ibcon#read 6, iclass 24, count 0 2006.201.20:55:56.63#ibcon#end of sib2, iclass 24, count 0 2006.201.20:55:56.63#ibcon#*after write, iclass 24, count 0 2006.201.20:55:56.63#ibcon#*before return 0, iclass 24, count 0 2006.201.20:55:56.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:56.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.20:55:56.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.20:55:56.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.20:55:56.63$vck44/vb=7,4 2006.201.20:55:56.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.20:55:56.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.20:55:56.63#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:56.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:56.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:56.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:56.68#ibcon#enter wrdev, iclass 26, count 2 2006.201.20:55:56.68#ibcon#first serial, iclass 26, count 2 2006.201.20:55:56.68#ibcon#enter sib2, iclass 26, count 2 2006.201.20:55:56.68#ibcon#flushed, iclass 26, count 2 2006.201.20:55:56.68#ibcon#about to write, iclass 26, count 2 2006.201.20:55:56.68#ibcon#wrote, iclass 26, count 2 2006.201.20:55:56.68#ibcon#about to read 3, iclass 26, count 2 2006.201.20:55:56.70#ibcon#read 3, iclass 26, count 2 2006.201.20:55:56.70#ibcon#about to read 4, iclass 26, count 2 2006.201.20:55:56.70#ibcon#read 4, iclass 26, count 2 2006.201.20:55:56.70#ibcon#about to read 5, iclass 26, count 2 2006.201.20:55:56.70#ibcon#read 5, iclass 26, count 2 2006.201.20:55:56.70#ibcon#about to read 6, iclass 26, count 2 2006.201.20:55:56.70#ibcon#read 6, iclass 26, count 2 2006.201.20:55:56.70#ibcon#end of sib2, iclass 26, count 2 2006.201.20:55:56.70#ibcon#*mode == 0, iclass 26, count 2 2006.201.20:55:56.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.20:55:56.70#ibcon#[27=AT07-04\r\n] 2006.201.20:55:56.70#ibcon#*before write, iclass 26, count 2 2006.201.20:55:56.70#ibcon#enter sib2, iclass 26, count 2 2006.201.20:55:56.70#ibcon#flushed, iclass 26, count 2 2006.201.20:55:56.70#ibcon#about to write, iclass 26, count 2 2006.201.20:55:56.70#ibcon#wrote, iclass 26, count 2 2006.201.20:55:56.70#ibcon#about to read 3, iclass 26, count 2 2006.201.20:55:56.73#ibcon#read 3, iclass 26, count 2 2006.201.20:55:56.73#ibcon#about to read 4, iclass 26, count 2 2006.201.20:55:56.73#ibcon#read 4, iclass 26, count 2 2006.201.20:55:56.73#ibcon#about to read 5, iclass 26, count 2 2006.201.20:55:56.73#ibcon#read 5, iclass 26, count 2 2006.201.20:55:56.73#ibcon#about to read 6, iclass 26, count 2 2006.201.20:55:56.73#ibcon#read 6, iclass 26, count 2 2006.201.20:55:56.73#ibcon#end of sib2, iclass 26, count 2 2006.201.20:55:56.73#ibcon#*after write, iclass 26, count 2 2006.201.20:55:56.73#ibcon#*before return 0, iclass 26, count 2 2006.201.20:55:56.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:56.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.20:55:56.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.20:55:56.73#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:56.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:56.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:56.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:56.85#ibcon#enter wrdev, iclass 26, count 0 2006.201.20:55:56.85#ibcon#first serial, iclass 26, count 0 2006.201.20:55:56.85#ibcon#enter sib2, iclass 26, count 0 2006.201.20:55:56.85#ibcon#flushed, iclass 26, count 0 2006.201.20:55:56.85#ibcon#about to write, iclass 26, count 0 2006.201.20:55:56.85#ibcon#wrote, iclass 26, count 0 2006.201.20:55:56.85#ibcon#about to read 3, iclass 26, count 0 2006.201.20:55:56.87#ibcon#read 3, iclass 26, count 0 2006.201.20:55:56.87#ibcon#about to read 4, iclass 26, count 0 2006.201.20:55:56.87#ibcon#read 4, iclass 26, count 0 2006.201.20:55:56.87#ibcon#about to read 5, iclass 26, count 0 2006.201.20:55:56.87#ibcon#read 5, iclass 26, count 0 2006.201.20:55:56.87#ibcon#about to read 6, iclass 26, count 0 2006.201.20:55:56.87#ibcon#read 6, iclass 26, count 0 2006.201.20:55:56.87#ibcon#end of sib2, iclass 26, count 0 2006.201.20:55:56.87#ibcon#*mode == 0, iclass 26, count 0 2006.201.20:55:56.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.20:55:56.87#ibcon#[27=USB\r\n] 2006.201.20:55:56.87#ibcon#*before write, iclass 26, count 0 2006.201.20:55:56.87#ibcon#enter sib2, iclass 26, count 0 2006.201.20:55:56.87#ibcon#flushed, iclass 26, count 0 2006.201.20:55:56.87#ibcon#about to write, iclass 26, count 0 2006.201.20:55:56.87#ibcon#wrote, iclass 26, count 0 2006.201.20:55:56.87#ibcon#about to read 3, iclass 26, count 0 2006.201.20:55:56.90#ibcon#read 3, iclass 26, count 0 2006.201.20:55:56.90#ibcon#about to read 4, iclass 26, count 0 2006.201.20:55:56.90#ibcon#read 4, iclass 26, count 0 2006.201.20:55:56.90#ibcon#about to read 5, iclass 26, count 0 2006.201.20:55:56.90#ibcon#read 5, iclass 26, count 0 2006.201.20:55:56.90#ibcon#about to read 6, iclass 26, count 0 2006.201.20:55:56.90#ibcon#read 6, iclass 26, count 0 2006.201.20:55:56.90#ibcon#end of sib2, iclass 26, count 0 2006.201.20:55:56.90#ibcon#*after write, iclass 26, count 0 2006.201.20:55:56.90#ibcon#*before return 0, iclass 26, count 0 2006.201.20:55:56.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:56.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.20:55:56.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.20:55:56.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.20:55:56.90$vck44/vblo=8,744.99 2006.201.20:55:56.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.20:55:56.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.20:55:56.90#ibcon#ireg 17 cls_cnt 0 2006.201.20:55:56.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:56.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:56.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:56.90#ibcon#enter wrdev, iclass 28, count 0 2006.201.20:55:56.90#ibcon#first serial, iclass 28, count 0 2006.201.20:55:56.90#ibcon#enter sib2, iclass 28, count 0 2006.201.20:55:56.90#ibcon#flushed, iclass 28, count 0 2006.201.20:55:56.90#ibcon#about to write, iclass 28, count 0 2006.201.20:55:56.90#ibcon#wrote, iclass 28, count 0 2006.201.20:55:56.90#ibcon#about to read 3, iclass 28, count 0 2006.201.20:55:56.92#ibcon#read 3, iclass 28, count 0 2006.201.20:55:56.92#ibcon#about to read 4, iclass 28, count 0 2006.201.20:55:56.92#ibcon#read 4, iclass 28, count 0 2006.201.20:55:56.92#ibcon#about to read 5, iclass 28, count 0 2006.201.20:55:56.92#ibcon#read 5, iclass 28, count 0 2006.201.20:55:56.92#ibcon#about to read 6, iclass 28, count 0 2006.201.20:55:56.92#ibcon#read 6, iclass 28, count 0 2006.201.20:55:56.92#ibcon#end of sib2, iclass 28, count 0 2006.201.20:55:56.92#ibcon#*mode == 0, iclass 28, count 0 2006.201.20:55:56.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.20:55:56.92#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.20:55:56.92#ibcon#*before write, iclass 28, count 0 2006.201.20:55:56.92#ibcon#enter sib2, iclass 28, count 0 2006.201.20:55:56.92#ibcon#flushed, iclass 28, count 0 2006.201.20:55:56.92#ibcon#about to write, iclass 28, count 0 2006.201.20:55:56.92#ibcon#wrote, iclass 28, count 0 2006.201.20:55:56.92#ibcon#about to read 3, iclass 28, count 0 2006.201.20:55:56.96#ibcon#read 3, iclass 28, count 0 2006.201.20:55:56.96#ibcon#about to read 4, iclass 28, count 0 2006.201.20:55:56.96#ibcon#read 4, iclass 28, count 0 2006.201.20:55:56.96#ibcon#about to read 5, iclass 28, count 0 2006.201.20:55:56.96#ibcon#read 5, iclass 28, count 0 2006.201.20:55:56.96#ibcon#about to read 6, iclass 28, count 0 2006.201.20:55:56.96#ibcon#read 6, iclass 28, count 0 2006.201.20:55:56.96#ibcon#end of sib2, iclass 28, count 0 2006.201.20:55:56.96#ibcon#*after write, iclass 28, count 0 2006.201.20:55:56.96#ibcon#*before return 0, iclass 28, count 0 2006.201.20:55:56.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:56.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.20:55:56.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.20:55:56.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.20:55:56.96$vck44/vb=8,4 2006.201.20:55:56.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.20:55:56.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.20:55:56.96#ibcon#ireg 11 cls_cnt 2 2006.201.20:55:56.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:57.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:57.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:57.02#ibcon#enter wrdev, iclass 30, count 2 2006.201.20:55:57.02#ibcon#first serial, iclass 30, count 2 2006.201.20:55:57.02#ibcon#enter sib2, iclass 30, count 2 2006.201.20:55:57.02#ibcon#flushed, iclass 30, count 2 2006.201.20:55:57.02#ibcon#about to write, iclass 30, count 2 2006.201.20:55:57.02#ibcon#wrote, iclass 30, count 2 2006.201.20:55:57.02#ibcon#about to read 3, iclass 30, count 2 2006.201.20:55:57.04#ibcon#read 3, iclass 30, count 2 2006.201.20:55:57.04#ibcon#about to read 4, iclass 30, count 2 2006.201.20:55:57.04#ibcon#read 4, iclass 30, count 2 2006.201.20:55:57.04#ibcon#about to read 5, iclass 30, count 2 2006.201.20:55:57.04#ibcon#read 5, iclass 30, count 2 2006.201.20:55:57.04#ibcon#about to read 6, iclass 30, count 2 2006.201.20:55:57.04#ibcon#read 6, iclass 30, count 2 2006.201.20:55:57.04#ibcon#end of sib2, iclass 30, count 2 2006.201.20:55:57.04#ibcon#*mode == 0, iclass 30, count 2 2006.201.20:55:57.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.20:55:57.04#ibcon#[27=AT08-04\r\n] 2006.201.20:55:57.04#ibcon#*before write, iclass 30, count 2 2006.201.20:55:57.04#ibcon#enter sib2, iclass 30, count 2 2006.201.20:55:57.04#ibcon#flushed, iclass 30, count 2 2006.201.20:55:57.04#ibcon#about to write, iclass 30, count 2 2006.201.20:55:57.04#ibcon#wrote, iclass 30, count 2 2006.201.20:55:57.04#ibcon#about to read 3, iclass 30, count 2 2006.201.20:55:57.07#ibcon#read 3, iclass 30, count 2 2006.201.20:55:57.07#ibcon#about to read 4, iclass 30, count 2 2006.201.20:55:57.07#ibcon#read 4, iclass 30, count 2 2006.201.20:55:57.07#ibcon#about to read 5, iclass 30, count 2 2006.201.20:55:57.07#ibcon#read 5, iclass 30, count 2 2006.201.20:55:57.07#ibcon#about to read 6, iclass 30, count 2 2006.201.20:55:57.07#ibcon#read 6, iclass 30, count 2 2006.201.20:55:57.07#ibcon#end of sib2, iclass 30, count 2 2006.201.20:55:57.07#ibcon#*after write, iclass 30, count 2 2006.201.20:55:57.07#ibcon#*before return 0, iclass 30, count 2 2006.201.20:55:57.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:57.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.20:55:57.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.20:55:57.07#ibcon#ireg 7 cls_cnt 0 2006.201.20:55:57.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:57.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:57.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:57.19#ibcon#enter wrdev, iclass 30, count 0 2006.201.20:55:57.19#ibcon#first serial, iclass 30, count 0 2006.201.20:55:57.19#ibcon#enter sib2, iclass 30, count 0 2006.201.20:55:57.19#ibcon#flushed, iclass 30, count 0 2006.201.20:55:57.19#ibcon#about to write, iclass 30, count 0 2006.201.20:55:57.19#ibcon#wrote, iclass 30, count 0 2006.201.20:55:57.19#ibcon#about to read 3, iclass 30, count 0 2006.201.20:55:57.22#ibcon#read 3, iclass 30, count 0 2006.201.20:55:57.22#ibcon#about to read 4, iclass 30, count 0 2006.201.20:55:57.22#ibcon#read 4, iclass 30, count 0 2006.201.20:55:57.22#ibcon#about to read 5, iclass 30, count 0 2006.201.20:55:57.22#ibcon#read 5, iclass 30, count 0 2006.201.20:55:57.22#ibcon#about to read 6, iclass 30, count 0 2006.201.20:55:57.22#ibcon#read 6, iclass 30, count 0 2006.201.20:55:57.22#ibcon#end of sib2, iclass 30, count 0 2006.201.20:55:57.22#ibcon#*mode == 0, iclass 30, count 0 2006.201.20:55:57.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.20:55:57.22#ibcon#[27=USB\r\n] 2006.201.20:55:57.22#ibcon#*before write, iclass 30, count 0 2006.201.20:55:57.22#ibcon#enter sib2, iclass 30, count 0 2006.201.20:55:57.22#ibcon#flushed, iclass 30, count 0 2006.201.20:55:57.22#ibcon#about to write, iclass 30, count 0 2006.201.20:55:57.22#ibcon#wrote, iclass 30, count 0 2006.201.20:55:57.22#ibcon#about to read 3, iclass 30, count 0 2006.201.20:55:57.25#ibcon#read 3, iclass 30, count 0 2006.201.20:55:57.25#ibcon#about to read 4, iclass 30, count 0 2006.201.20:55:57.25#ibcon#read 4, iclass 30, count 0 2006.201.20:55:57.25#ibcon#about to read 5, iclass 30, count 0 2006.201.20:55:57.25#ibcon#read 5, iclass 30, count 0 2006.201.20:55:57.25#ibcon#about to read 6, iclass 30, count 0 2006.201.20:55:57.25#ibcon#read 6, iclass 30, count 0 2006.201.20:55:57.25#ibcon#end of sib2, iclass 30, count 0 2006.201.20:55:57.25#ibcon#*after write, iclass 30, count 0 2006.201.20:55:57.25#ibcon#*before return 0, iclass 30, count 0 2006.201.20:55:57.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:57.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.20:55:57.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.20:55:57.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.20:55:57.25$vck44/vabw=wide 2006.201.20:55:57.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.20:55:57.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.20:55:57.25#ibcon#ireg 8 cls_cnt 0 2006.201.20:55:57.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:57.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:57.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:57.25#ibcon#enter wrdev, iclass 32, count 0 2006.201.20:55:57.25#ibcon#first serial, iclass 32, count 0 2006.201.20:55:57.25#ibcon#enter sib2, iclass 32, count 0 2006.201.20:55:57.25#ibcon#flushed, iclass 32, count 0 2006.201.20:55:57.25#ibcon#about to write, iclass 32, count 0 2006.201.20:55:57.25#ibcon#wrote, iclass 32, count 0 2006.201.20:55:57.25#ibcon#about to read 3, iclass 32, count 0 2006.201.20:55:57.27#ibcon#read 3, iclass 32, count 0 2006.201.20:55:57.27#ibcon#about to read 4, iclass 32, count 0 2006.201.20:55:57.27#ibcon#read 4, iclass 32, count 0 2006.201.20:55:57.27#ibcon#about to read 5, iclass 32, count 0 2006.201.20:55:57.27#ibcon#read 5, iclass 32, count 0 2006.201.20:55:57.27#ibcon#about to read 6, iclass 32, count 0 2006.201.20:55:57.27#ibcon#read 6, iclass 32, count 0 2006.201.20:55:57.27#ibcon#end of sib2, iclass 32, count 0 2006.201.20:55:57.27#ibcon#*mode == 0, iclass 32, count 0 2006.201.20:55:57.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.20:55:57.27#ibcon#[25=BW32\r\n] 2006.201.20:55:57.27#ibcon#*before write, iclass 32, count 0 2006.201.20:55:57.27#ibcon#enter sib2, iclass 32, count 0 2006.201.20:55:57.27#ibcon#flushed, iclass 32, count 0 2006.201.20:55:57.27#ibcon#about to write, iclass 32, count 0 2006.201.20:55:57.27#ibcon#wrote, iclass 32, count 0 2006.201.20:55:57.27#ibcon#about to read 3, iclass 32, count 0 2006.201.20:55:57.30#ibcon#read 3, iclass 32, count 0 2006.201.20:55:57.30#ibcon#about to read 4, iclass 32, count 0 2006.201.20:55:57.30#ibcon#read 4, iclass 32, count 0 2006.201.20:55:57.30#ibcon#about to read 5, iclass 32, count 0 2006.201.20:55:57.30#ibcon#read 5, iclass 32, count 0 2006.201.20:55:57.30#ibcon#about to read 6, iclass 32, count 0 2006.201.20:55:57.30#ibcon#read 6, iclass 32, count 0 2006.201.20:55:57.30#ibcon#end of sib2, iclass 32, count 0 2006.201.20:55:57.30#ibcon#*after write, iclass 32, count 0 2006.201.20:55:57.30#ibcon#*before return 0, iclass 32, count 0 2006.201.20:55:57.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:57.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.20:55:57.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.20:55:57.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.20:55:57.30$vck44/vbbw=wide 2006.201.20:55:57.30#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.20:55:57.30#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.20:55:57.30#ibcon#ireg 8 cls_cnt 0 2006.201.20:55:57.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:55:57.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:55:57.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:55:57.37#ibcon#enter wrdev, iclass 34, count 0 2006.201.20:55:57.37#ibcon#first serial, iclass 34, count 0 2006.201.20:55:57.37#ibcon#enter sib2, iclass 34, count 0 2006.201.20:55:57.37#ibcon#flushed, iclass 34, count 0 2006.201.20:55:57.37#ibcon#about to write, iclass 34, count 0 2006.201.20:55:57.37#ibcon#wrote, iclass 34, count 0 2006.201.20:55:57.37#ibcon#about to read 3, iclass 34, count 0 2006.201.20:55:57.39#ibcon#read 3, iclass 34, count 0 2006.201.20:55:57.39#ibcon#about to read 4, iclass 34, count 0 2006.201.20:55:57.39#ibcon#read 4, iclass 34, count 0 2006.201.20:55:57.39#ibcon#about to read 5, iclass 34, count 0 2006.201.20:55:57.39#ibcon#read 5, iclass 34, count 0 2006.201.20:55:57.39#ibcon#about to read 6, iclass 34, count 0 2006.201.20:55:57.39#ibcon#read 6, iclass 34, count 0 2006.201.20:55:57.39#ibcon#end of sib2, iclass 34, count 0 2006.201.20:55:57.39#ibcon#*mode == 0, iclass 34, count 0 2006.201.20:55:57.39#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.20:55:57.39#ibcon#[27=BW32\r\n] 2006.201.20:55:57.39#ibcon#*before write, iclass 34, count 0 2006.201.20:55:57.39#ibcon#enter sib2, iclass 34, count 0 2006.201.20:55:57.39#ibcon#flushed, iclass 34, count 0 2006.201.20:55:57.39#ibcon#about to write, iclass 34, count 0 2006.201.20:55:57.39#ibcon#wrote, iclass 34, count 0 2006.201.20:55:57.39#ibcon#about to read 3, iclass 34, count 0 2006.201.20:55:57.42#ibcon#read 3, iclass 34, count 0 2006.201.20:55:57.42#ibcon#about to read 4, iclass 34, count 0 2006.201.20:55:57.42#ibcon#read 4, iclass 34, count 0 2006.201.20:55:57.42#ibcon#about to read 5, iclass 34, count 0 2006.201.20:55:57.42#ibcon#read 5, iclass 34, count 0 2006.201.20:55:57.42#ibcon#about to read 6, iclass 34, count 0 2006.201.20:55:57.42#ibcon#read 6, iclass 34, count 0 2006.201.20:55:57.42#ibcon#end of sib2, iclass 34, count 0 2006.201.20:55:57.42#ibcon#*after write, iclass 34, count 0 2006.201.20:55:57.42#ibcon#*before return 0, iclass 34, count 0 2006.201.20:55:57.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:55:57.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.20:55:57.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.20:55:57.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.20:55:57.42$setupk4/ifdk4 2006.201.20:55:57.42$ifdk4/lo= 2006.201.20:55:57.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.20:55:57.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.20:55:57.42$ifdk4/patch= 2006.201.20:55:57.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.20:55:57.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.20:55:57.42$setupk4/!*+20s 2006.201.20:55:58.94#abcon#<5=/07 0.4 1.4 20.201001002.4\r\n> 2006.201.20:55:58.96#abcon#{5=INTERFACE CLEAR} 2006.201.20:55:59.02#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:56:09.11#abcon#<5=/07 0.4 1.4 20.201001002.4\r\n> 2006.201.20:56:09.13#abcon#{5=INTERFACE CLEAR} 2006.201.20:56:09.19#abcon#[5=S1D000X0/0*\r\n] 2006.201.20:56:11.90$setupk4/"tpicd 2006.201.20:56:11.90$setupk4/echo=off 2006.201.20:56:11.90$setupk4/xlog=off 2006.201.20:56:11.90:!2006.201.21:00:25 2006.201.20:56:29.14#trakl#Source acquired 2006.201.20:56:29.14#flagr#flagr/antenna,acquired 2006.201.21:00:25.00:preob 2006.201.21:00:25.13/onsource/TRACKING 2006.201.21:00:25.13:!2006.201.21:00:35 2006.201.21:00:35.00:"tape 2006.201.21:00:35.00:"st=record 2006.201.21:00:35.00:data_valid=on 2006.201.21:00:35.00:midob 2006.201.21:00:35.13/onsource/TRACKING 2006.201.21:00:35.13/wx/20.22,1002.4,100 2006.201.21:00:35.33/cable/+6.4821E-03 2006.201.21:00:36.42/va/01,08,usb,yes,67,71 2006.201.21:00:36.42/va/02,07,usb,yes,71,73 2006.201.21:00:36.42/va/03,08,usb,yes,65,68 2006.201.21:00:36.42/va/04,07,usb,yes,74,77 2006.201.21:00:36.42/va/05,04,usb,yes,66,68 2006.201.21:00:36.42/va/06,05,usb,yes,67,67 2006.201.21:00:36.42/va/07,05,usb,yes,65,67 2006.201.21:00:36.42/va/08,04,usb,yes,65,75 2006.201.21:00:36.65/valo/01,524.99,yes,locked 2006.201.21:00:36.65/valo/02,534.99,yes,locked 2006.201.21:00:36.65/valo/03,564.99,yes,locked 2006.201.21:00:36.65/valo/04,624.99,yes,locked 2006.201.21:00:36.65/valo/05,734.99,yes,locked 2006.201.21:00:36.65/valo/06,814.99,yes,locked 2006.201.21:00:36.65/valo/07,864.99,yes,locked 2006.201.21:00:36.65/valo/08,884.99,yes,locked 2006.201.21:00:37.74/vb/01,04,usb,yes,34,32 2006.201.21:00:37.74/vb/02,05,usb,yes,33,32 2006.201.21:00:37.74/vb/03,04,usb,yes,34,37 2006.201.21:00:37.74/vb/04,05,usb,yes,34,33 2006.201.21:00:37.74/vb/05,04,usb,yes,30,33 2006.201.21:00:37.74/vb/06,04,usb,yes,35,31 2006.201.21:00:37.74/vb/07,04,usb,yes,35,35 2006.201.21:00:37.74/vb/08,04,usb,yes,32,36 2006.201.21:00:37.98/vblo/01,629.99,yes,locked 2006.201.21:00:37.98/vblo/02,634.99,yes,locked 2006.201.21:00:37.98/vblo/03,649.99,yes,locked 2006.201.21:00:37.98/vblo/04,679.99,yes,locked 2006.201.21:00:37.98/vblo/05,709.99,yes,locked 2006.201.21:00:37.98/vblo/06,719.99,yes,locked 2006.201.21:00:37.98/vblo/07,734.99,yes,locked 2006.201.21:00:37.98/vblo/08,744.99,yes,locked 2006.201.21:00:38.13/vabw/8 2006.201.21:00:38.29/vbbw/8 2006.201.21:00:38.38/xfe/off,on,15.5 2006.201.21:00:38.75/ifatt/23,28,28,28 2006.201.21:00:39.06/fmout-gps/S +4.53E-07 2006.201.21:00:39.11:!2006.201.21:04:25 2006.201.21:04:25.00:data_valid=off 2006.201.21:04:25.00:"et 2006.201.21:04:25.00:!+3s 2006.201.21:04:28.02:"tape 2006.201.21:04:28.02:postob 2006.201.21:04:28.25/cable/+6.4815E-03 2006.201.21:04:28.25/wx/20.16,1002.4,100 2006.201.21:04:28.33/fmout-gps/S +4.52E-07 2006.201.21:04:28.33:scan_name=201-2114,jd0607,90 2006.201.21:04:28.33:source=2136+141,213901.31,142336.0,2000.0,ccw 2006.201.21:04:29.14#flagr#flagr/antenna,new-source 2006.201.21:04:29.14:checkk5 2006.201.21:04:29.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.21:04:29.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.21:04:30.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.21:04:30.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.21:04:31.02/chk_obsdata//k5ts1/T2012100??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.21:04:31.38/chk_obsdata//k5ts2/T2012100??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.21:04:31.75/chk_obsdata//k5ts3/T2012100??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.21:04:32.12/chk_obsdata//k5ts4/T2012100??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.21:04:32.80/k5log//k5ts1_log_newline 2006.201.21:04:33.50/k5log//k5ts2_log_newline 2006.201.21:04:34.19/k5log//k5ts3_log_newline 2006.201.21:04:34.88/k5log//k5ts4_log_newline 2006.201.21:04:34.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.21:04:34.90:setupk4=1 2006.201.21:04:34.90$setupk4/echo=on 2006.201.21:04:34.90$setupk4/pcalon 2006.201.21:04:34.90$pcalon/"no phase cal control is implemented here 2006.201.21:04:34.90$setupk4/"tpicd=stop 2006.201.21:04:34.90$setupk4/"rec=synch_on 2006.201.21:04:34.90$setupk4/"rec_mode=128 2006.201.21:04:34.90$setupk4/!* 2006.201.21:04:34.90$setupk4/recpk4 2006.201.21:04:34.90$recpk4/recpatch= 2006.201.21:04:34.91$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.21:04:34.91$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.21:04:34.91$setupk4/vck44 2006.201.21:04:34.91$vck44/valo=1,524.99 2006.201.21:04:34.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.21:04:34.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.21:04:34.91#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:34.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:34.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:34.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:34.91#ibcon#enter wrdev, iclass 22, count 0 2006.201.21:04:34.91#ibcon#first serial, iclass 22, count 0 2006.201.21:04:34.91#ibcon#enter sib2, iclass 22, count 0 2006.201.21:04:34.91#ibcon#flushed, iclass 22, count 0 2006.201.21:04:34.91#ibcon#about to write, iclass 22, count 0 2006.201.21:04:34.91#ibcon#wrote, iclass 22, count 0 2006.201.21:04:34.91#ibcon#about to read 3, iclass 22, count 0 2006.201.21:04:34.94#ibcon#read 3, iclass 22, count 0 2006.201.21:04:34.94#ibcon#about to read 4, iclass 22, count 0 2006.201.21:04:34.94#ibcon#read 4, iclass 22, count 0 2006.201.21:04:34.94#ibcon#about to read 5, iclass 22, count 0 2006.201.21:04:34.94#ibcon#read 5, iclass 22, count 0 2006.201.21:04:34.94#ibcon#about to read 6, iclass 22, count 0 2006.201.21:04:34.94#ibcon#read 6, iclass 22, count 0 2006.201.21:04:34.94#ibcon#end of sib2, iclass 22, count 0 2006.201.21:04:34.94#ibcon#*mode == 0, iclass 22, count 0 2006.201.21:04:34.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.21:04:34.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.21:04:34.94#ibcon#*before write, iclass 22, count 0 2006.201.21:04:34.94#ibcon#enter sib2, iclass 22, count 0 2006.201.21:04:34.94#ibcon#flushed, iclass 22, count 0 2006.201.21:04:34.94#ibcon#about to write, iclass 22, count 0 2006.201.21:04:34.94#ibcon#wrote, iclass 22, count 0 2006.201.21:04:34.94#ibcon#about to read 3, iclass 22, count 0 2006.201.21:04:34.99#ibcon#read 3, iclass 22, count 0 2006.201.21:04:34.99#ibcon#about to read 4, iclass 22, count 0 2006.201.21:04:34.99#ibcon#read 4, iclass 22, count 0 2006.201.21:04:34.99#ibcon#about to read 5, iclass 22, count 0 2006.201.21:04:34.99#ibcon#read 5, iclass 22, count 0 2006.201.21:04:34.99#ibcon#about to read 6, iclass 22, count 0 2006.201.21:04:34.99#ibcon#read 6, iclass 22, count 0 2006.201.21:04:34.99#ibcon#end of sib2, iclass 22, count 0 2006.201.21:04:34.99#ibcon#*after write, iclass 22, count 0 2006.201.21:04:34.99#ibcon#*before return 0, iclass 22, count 0 2006.201.21:04:34.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:34.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:34.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.21:04:34.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.21:04:34.99$vck44/va=1,8 2006.201.21:04:34.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.21:04:34.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.21:04:34.99#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:34.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:34.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:34.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:34.99#ibcon#enter wrdev, iclass 24, count 2 2006.201.21:04:34.99#ibcon#first serial, iclass 24, count 2 2006.201.21:04:34.99#ibcon#enter sib2, iclass 24, count 2 2006.201.21:04:34.99#ibcon#flushed, iclass 24, count 2 2006.201.21:04:34.99#ibcon#about to write, iclass 24, count 2 2006.201.21:04:34.99#ibcon#wrote, iclass 24, count 2 2006.201.21:04:34.99#ibcon#about to read 3, iclass 24, count 2 2006.201.21:04:35.01#ibcon#read 3, iclass 24, count 2 2006.201.21:04:35.01#ibcon#about to read 4, iclass 24, count 2 2006.201.21:04:35.01#ibcon#read 4, iclass 24, count 2 2006.201.21:04:35.01#ibcon#about to read 5, iclass 24, count 2 2006.201.21:04:35.01#ibcon#read 5, iclass 24, count 2 2006.201.21:04:35.01#ibcon#about to read 6, iclass 24, count 2 2006.201.21:04:35.01#ibcon#read 6, iclass 24, count 2 2006.201.21:04:35.01#ibcon#end of sib2, iclass 24, count 2 2006.201.21:04:35.01#ibcon#*mode == 0, iclass 24, count 2 2006.201.21:04:35.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.21:04:35.01#ibcon#[25=AT01-08\r\n] 2006.201.21:04:35.01#ibcon#*before write, iclass 24, count 2 2006.201.21:04:35.01#ibcon#enter sib2, iclass 24, count 2 2006.201.21:04:35.01#ibcon#flushed, iclass 24, count 2 2006.201.21:04:35.01#ibcon#about to write, iclass 24, count 2 2006.201.21:04:35.01#ibcon#wrote, iclass 24, count 2 2006.201.21:04:35.01#ibcon#about to read 3, iclass 24, count 2 2006.201.21:04:35.04#ibcon#read 3, iclass 24, count 2 2006.201.21:04:35.04#ibcon#about to read 4, iclass 24, count 2 2006.201.21:04:35.04#ibcon#read 4, iclass 24, count 2 2006.201.21:04:35.04#ibcon#about to read 5, iclass 24, count 2 2006.201.21:04:35.04#ibcon#read 5, iclass 24, count 2 2006.201.21:04:35.04#ibcon#about to read 6, iclass 24, count 2 2006.201.21:04:35.04#ibcon#read 6, iclass 24, count 2 2006.201.21:04:35.04#ibcon#end of sib2, iclass 24, count 2 2006.201.21:04:35.04#ibcon#*after write, iclass 24, count 2 2006.201.21:04:35.04#ibcon#*before return 0, iclass 24, count 2 2006.201.21:04:35.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:35.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:35.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.21:04:35.04#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:35.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:35.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:35.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:35.16#ibcon#enter wrdev, iclass 24, count 0 2006.201.21:04:35.16#ibcon#first serial, iclass 24, count 0 2006.201.21:04:35.16#ibcon#enter sib2, iclass 24, count 0 2006.201.21:04:35.16#ibcon#flushed, iclass 24, count 0 2006.201.21:04:35.16#ibcon#about to write, iclass 24, count 0 2006.201.21:04:35.16#ibcon#wrote, iclass 24, count 0 2006.201.21:04:35.16#ibcon#about to read 3, iclass 24, count 0 2006.201.21:04:35.18#ibcon#read 3, iclass 24, count 0 2006.201.21:04:35.18#ibcon#about to read 4, iclass 24, count 0 2006.201.21:04:35.18#ibcon#read 4, iclass 24, count 0 2006.201.21:04:35.18#ibcon#about to read 5, iclass 24, count 0 2006.201.21:04:35.18#ibcon#read 5, iclass 24, count 0 2006.201.21:04:35.18#ibcon#about to read 6, iclass 24, count 0 2006.201.21:04:35.18#ibcon#read 6, iclass 24, count 0 2006.201.21:04:35.18#ibcon#end of sib2, iclass 24, count 0 2006.201.21:04:35.18#ibcon#*mode == 0, iclass 24, count 0 2006.201.21:04:35.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.21:04:35.18#ibcon#[25=USB\r\n] 2006.201.21:04:35.18#ibcon#*before write, iclass 24, count 0 2006.201.21:04:35.18#ibcon#enter sib2, iclass 24, count 0 2006.201.21:04:35.18#ibcon#flushed, iclass 24, count 0 2006.201.21:04:35.18#ibcon#about to write, iclass 24, count 0 2006.201.21:04:35.18#ibcon#wrote, iclass 24, count 0 2006.201.21:04:35.18#ibcon#about to read 3, iclass 24, count 0 2006.201.21:04:35.21#ibcon#read 3, iclass 24, count 0 2006.201.21:04:35.21#ibcon#about to read 4, iclass 24, count 0 2006.201.21:04:35.21#ibcon#read 4, iclass 24, count 0 2006.201.21:04:35.21#ibcon#about to read 5, iclass 24, count 0 2006.201.21:04:35.21#ibcon#read 5, iclass 24, count 0 2006.201.21:04:35.21#ibcon#about to read 6, iclass 24, count 0 2006.201.21:04:35.21#ibcon#read 6, iclass 24, count 0 2006.201.21:04:35.21#ibcon#end of sib2, iclass 24, count 0 2006.201.21:04:35.21#ibcon#*after write, iclass 24, count 0 2006.201.21:04:35.21#ibcon#*before return 0, iclass 24, count 0 2006.201.21:04:35.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:35.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:35.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.21:04:35.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.21:04:35.21$vck44/valo=2,534.99 2006.201.21:04:35.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.21:04:35.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.21:04:35.21#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:35.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:35.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:35.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:35.21#ibcon#enter wrdev, iclass 26, count 0 2006.201.21:04:35.21#ibcon#first serial, iclass 26, count 0 2006.201.21:04:35.21#ibcon#enter sib2, iclass 26, count 0 2006.201.21:04:35.21#ibcon#flushed, iclass 26, count 0 2006.201.21:04:35.21#ibcon#about to write, iclass 26, count 0 2006.201.21:04:35.21#ibcon#wrote, iclass 26, count 0 2006.201.21:04:35.21#ibcon#about to read 3, iclass 26, count 0 2006.201.21:04:35.23#ibcon#read 3, iclass 26, count 0 2006.201.21:04:35.23#ibcon#about to read 4, iclass 26, count 0 2006.201.21:04:35.23#ibcon#read 4, iclass 26, count 0 2006.201.21:04:35.23#ibcon#about to read 5, iclass 26, count 0 2006.201.21:04:35.23#ibcon#read 5, iclass 26, count 0 2006.201.21:04:35.23#ibcon#about to read 6, iclass 26, count 0 2006.201.21:04:35.23#ibcon#read 6, iclass 26, count 0 2006.201.21:04:35.23#ibcon#end of sib2, iclass 26, count 0 2006.201.21:04:35.23#ibcon#*mode == 0, iclass 26, count 0 2006.201.21:04:35.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.21:04:35.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.21:04:35.23#ibcon#*before write, iclass 26, count 0 2006.201.21:04:35.23#ibcon#enter sib2, iclass 26, count 0 2006.201.21:04:35.23#ibcon#flushed, iclass 26, count 0 2006.201.21:04:35.23#ibcon#about to write, iclass 26, count 0 2006.201.21:04:35.23#ibcon#wrote, iclass 26, count 0 2006.201.21:04:35.23#ibcon#about to read 3, iclass 26, count 0 2006.201.21:04:35.28#ibcon#read 3, iclass 26, count 0 2006.201.21:04:35.28#ibcon#about to read 4, iclass 26, count 0 2006.201.21:04:35.28#ibcon#read 4, iclass 26, count 0 2006.201.21:04:35.28#ibcon#about to read 5, iclass 26, count 0 2006.201.21:04:35.28#ibcon#read 5, iclass 26, count 0 2006.201.21:04:35.28#ibcon#about to read 6, iclass 26, count 0 2006.201.21:04:35.28#ibcon#read 6, iclass 26, count 0 2006.201.21:04:35.28#ibcon#end of sib2, iclass 26, count 0 2006.201.21:04:35.28#ibcon#*after write, iclass 26, count 0 2006.201.21:04:35.28#ibcon#*before return 0, iclass 26, count 0 2006.201.21:04:35.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:35.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:35.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.21:04:35.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.21:04:35.28$vck44/va=2,7 2006.201.21:04:35.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.21:04:35.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.21:04:35.28#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:35.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:35.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:35.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:35.33#ibcon#enter wrdev, iclass 28, count 2 2006.201.21:04:35.33#ibcon#first serial, iclass 28, count 2 2006.201.21:04:35.33#ibcon#enter sib2, iclass 28, count 2 2006.201.21:04:35.33#ibcon#flushed, iclass 28, count 2 2006.201.21:04:35.33#ibcon#about to write, iclass 28, count 2 2006.201.21:04:35.33#ibcon#wrote, iclass 28, count 2 2006.201.21:04:35.33#ibcon#about to read 3, iclass 28, count 2 2006.201.21:04:35.35#ibcon#read 3, iclass 28, count 2 2006.201.21:04:35.35#ibcon#about to read 4, iclass 28, count 2 2006.201.21:04:35.35#ibcon#read 4, iclass 28, count 2 2006.201.21:04:35.35#ibcon#about to read 5, iclass 28, count 2 2006.201.21:04:35.35#ibcon#read 5, iclass 28, count 2 2006.201.21:04:35.35#ibcon#about to read 6, iclass 28, count 2 2006.201.21:04:35.35#ibcon#read 6, iclass 28, count 2 2006.201.21:04:35.35#ibcon#end of sib2, iclass 28, count 2 2006.201.21:04:35.35#ibcon#*mode == 0, iclass 28, count 2 2006.201.21:04:35.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.21:04:35.35#ibcon#[25=AT02-07\r\n] 2006.201.21:04:35.35#ibcon#*before write, iclass 28, count 2 2006.201.21:04:35.35#ibcon#enter sib2, iclass 28, count 2 2006.201.21:04:35.35#ibcon#flushed, iclass 28, count 2 2006.201.21:04:35.35#ibcon#about to write, iclass 28, count 2 2006.201.21:04:35.35#ibcon#wrote, iclass 28, count 2 2006.201.21:04:35.35#ibcon#about to read 3, iclass 28, count 2 2006.201.21:04:35.38#ibcon#read 3, iclass 28, count 2 2006.201.21:04:35.38#ibcon#about to read 4, iclass 28, count 2 2006.201.21:04:35.38#ibcon#read 4, iclass 28, count 2 2006.201.21:04:35.38#ibcon#about to read 5, iclass 28, count 2 2006.201.21:04:35.38#ibcon#read 5, iclass 28, count 2 2006.201.21:04:35.38#ibcon#about to read 6, iclass 28, count 2 2006.201.21:04:35.38#ibcon#read 6, iclass 28, count 2 2006.201.21:04:35.38#ibcon#end of sib2, iclass 28, count 2 2006.201.21:04:35.38#ibcon#*after write, iclass 28, count 2 2006.201.21:04:35.38#ibcon#*before return 0, iclass 28, count 2 2006.201.21:04:35.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:35.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:35.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.21:04:35.38#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:35.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:35.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:35.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:35.50#ibcon#enter wrdev, iclass 28, count 0 2006.201.21:04:35.50#ibcon#first serial, iclass 28, count 0 2006.201.21:04:35.50#ibcon#enter sib2, iclass 28, count 0 2006.201.21:04:35.50#ibcon#flushed, iclass 28, count 0 2006.201.21:04:35.50#ibcon#about to write, iclass 28, count 0 2006.201.21:04:35.50#ibcon#wrote, iclass 28, count 0 2006.201.21:04:35.50#ibcon#about to read 3, iclass 28, count 0 2006.201.21:04:35.52#ibcon#read 3, iclass 28, count 0 2006.201.21:04:35.52#ibcon#about to read 4, iclass 28, count 0 2006.201.21:04:35.52#ibcon#read 4, iclass 28, count 0 2006.201.21:04:35.52#ibcon#about to read 5, iclass 28, count 0 2006.201.21:04:35.52#ibcon#read 5, iclass 28, count 0 2006.201.21:04:35.52#ibcon#about to read 6, iclass 28, count 0 2006.201.21:04:35.52#ibcon#read 6, iclass 28, count 0 2006.201.21:04:35.52#ibcon#end of sib2, iclass 28, count 0 2006.201.21:04:35.52#ibcon#*mode == 0, iclass 28, count 0 2006.201.21:04:35.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.21:04:35.52#ibcon#[25=USB\r\n] 2006.201.21:04:35.52#ibcon#*before write, iclass 28, count 0 2006.201.21:04:35.52#ibcon#enter sib2, iclass 28, count 0 2006.201.21:04:35.52#ibcon#flushed, iclass 28, count 0 2006.201.21:04:35.52#ibcon#about to write, iclass 28, count 0 2006.201.21:04:35.52#ibcon#wrote, iclass 28, count 0 2006.201.21:04:35.52#ibcon#about to read 3, iclass 28, count 0 2006.201.21:04:35.55#ibcon#read 3, iclass 28, count 0 2006.201.21:04:35.55#ibcon#about to read 4, iclass 28, count 0 2006.201.21:04:35.55#ibcon#read 4, iclass 28, count 0 2006.201.21:04:35.55#ibcon#about to read 5, iclass 28, count 0 2006.201.21:04:35.55#ibcon#read 5, iclass 28, count 0 2006.201.21:04:35.55#ibcon#about to read 6, iclass 28, count 0 2006.201.21:04:35.55#ibcon#read 6, iclass 28, count 0 2006.201.21:04:35.55#ibcon#end of sib2, iclass 28, count 0 2006.201.21:04:35.55#ibcon#*after write, iclass 28, count 0 2006.201.21:04:35.55#ibcon#*before return 0, iclass 28, count 0 2006.201.21:04:35.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:35.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:35.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.21:04:35.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.21:04:35.55$vck44/valo=3,564.99 2006.201.21:04:35.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.21:04:35.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.21:04:35.55#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:35.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:35.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:35.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:35.55#ibcon#enter wrdev, iclass 30, count 0 2006.201.21:04:35.55#ibcon#first serial, iclass 30, count 0 2006.201.21:04:35.55#ibcon#enter sib2, iclass 30, count 0 2006.201.21:04:35.55#ibcon#flushed, iclass 30, count 0 2006.201.21:04:35.55#ibcon#about to write, iclass 30, count 0 2006.201.21:04:35.55#ibcon#wrote, iclass 30, count 0 2006.201.21:04:35.55#ibcon#about to read 3, iclass 30, count 0 2006.201.21:04:35.57#ibcon#read 3, iclass 30, count 0 2006.201.21:04:35.57#ibcon#about to read 4, iclass 30, count 0 2006.201.21:04:35.57#ibcon#read 4, iclass 30, count 0 2006.201.21:04:35.57#ibcon#about to read 5, iclass 30, count 0 2006.201.21:04:35.57#ibcon#read 5, iclass 30, count 0 2006.201.21:04:35.57#ibcon#about to read 6, iclass 30, count 0 2006.201.21:04:35.57#ibcon#read 6, iclass 30, count 0 2006.201.21:04:35.57#ibcon#end of sib2, iclass 30, count 0 2006.201.21:04:35.57#ibcon#*mode == 0, iclass 30, count 0 2006.201.21:04:35.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.21:04:35.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.21:04:35.57#ibcon#*before write, iclass 30, count 0 2006.201.21:04:35.57#ibcon#enter sib2, iclass 30, count 0 2006.201.21:04:35.57#ibcon#flushed, iclass 30, count 0 2006.201.21:04:35.57#ibcon#about to write, iclass 30, count 0 2006.201.21:04:35.57#ibcon#wrote, iclass 30, count 0 2006.201.21:04:35.57#ibcon#about to read 3, iclass 30, count 0 2006.201.21:04:35.61#ibcon#read 3, iclass 30, count 0 2006.201.21:04:35.61#ibcon#about to read 4, iclass 30, count 0 2006.201.21:04:35.61#ibcon#read 4, iclass 30, count 0 2006.201.21:04:35.61#ibcon#about to read 5, iclass 30, count 0 2006.201.21:04:35.61#ibcon#read 5, iclass 30, count 0 2006.201.21:04:35.61#ibcon#about to read 6, iclass 30, count 0 2006.201.21:04:35.61#ibcon#read 6, iclass 30, count 0 2006.201.21:04:35.61#ibcon#end of sib2, iclass 30, count 0 2006.201.21:04:35.61#ibcon#*after write, iclass 30, count 0 2006.201.21:04:35.61#ibcon#*before return 0, iclass 30, count 0 2006.201.21:04:35.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:35.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:35.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.21:04:35.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.21:04:35.61$vck44/va=3,8 2006.201.21:04:35.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.21:04:35.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.21:04:35.61#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:35.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:35.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:35.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:35.67#ibcon#enter wrdev, iclass 32, count 2 2006.201.21:04:35.67#ibcon#first serial, iclass 32, count 2 2006.201.21:04:35.67#ibcon#enter sib2, iclass 32, count 2 2006.201.21:04:35.67#ibcon#flushed, iclass 32, count 2 2006.201.21:04:35.67#ibcon#about to write, iclass 32, count 2 2006.201.21:04:35.67#ibcon#wrote, iclass 32, count 2 2006.201.21:04:35.67#ibcon#about to read 3, iclass 32, count 2 2006.201.21:04:35.69#ibcon#read 3, iclass 32, count 2 2006.201.21:04:35.69#ibcon#about to read 4, iclass 32, count 2 2006.201.21:04:35.69#ibcon#read 4, iclass 32, count 2 2006.201.21:04:35.69#ibcon#about to read 5, iclass 32, count 2 2006.201.21:04:35.69#ibcon#read 5, iclass 32, count 2 2006.201.21:04:35.69#ibcon#about to read 6, iclass 32, count 2 2006.201.21:04:35.69#ibcon#read 6, iclass 32, count 2 2006.201.21:04:35.69#ibcon#end of sib2, iclass 32, count 2 2006.201.21:04:35.69#ibcon#*mode == 0, iclass 32, count 2 2006.201.21:04:35.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.21:04:35.69#ibcon#[25=AT03-08\r\n] 2006.201.21:04:35.69#ibcon#*before write, iclass 32, count 2 2006.201.21:04:35.69#ibcon#enter sib2, iclass 32, count 2 2006.201.21:04:35.69#ibcon#flushed, iclass 32, count 2 2006.201.21:04:35.69#ibcon#about to write, iclass 32, count 2 2006.201.21:04:35.69#ibcon#wrote, iclass 32, count 2 2006.201.21:04:35.69#ibcon#about to read 3, iclass 32, count 2 2006.201.21:04:35.72#ibcon#read 3, iclass 32, count 2 2006.201.21:04:35.72#ibcon#about to read 4, iclass 32, count 2 2006.201.21:04:35.72#ibcon#read 4, iclass 32, count 2 2006.201.21:04:35.72#ibcon#about to read 5, iclass 32, count 2 2006.201.21:04:35.72#ibcon#read 5, iclass 32, count 2 2006.201.21:04:35.72#ibcon#about to read 6, iclass 32, count 2 2006.201.21:04:35.72#ibcon#read 6, iclass 32, count 2 2006.201.21:04:35.72#ibcon#end of sib2, iclass 32, count 2 2006.201.21:04:35.72#ibcon#*after write, iclass 32, count 2 2006.201.21:04:35.72#ibcon#*before return 0, iclass 32, count 2 2006.201.21:04:35.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:35.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:35.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.21:04:35.72#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:35.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:35.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:35.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:35.84#ibcon#enter wrdev, iclass 32, count 0 2006.201.21:04:35.84#ibcon#first serial, iclass 32, count 0 2006.201.21:04:35.84#ibcon#enter sib2, iclass 32, count 0 2006.201.21:04:35.84#ibcon#flushed, iclass 32, count 0 2006.201.21:04:35.84#ibcon#about to write, iclass 32, count 0 2006.201.21:04:35.84#ibcon#wrote, iclass 32, count 0 2006.201.21:04:35.84#ibcon#about to read 3, iclass 32, count 0 2006.201.21:04:35.86#ibcon#read 3, iclass 32, count 0 2006.201.21:04:35.86#ibcon#about to read 4, iclass 32, count 0 2006.201.21:04:35.86#ibcon#read 4, iclass 32, count 0 2006.201.21:04:35.86#ibcon#about to read 5, iclass 32, count 0 2006.201.21:04:35.86#ibcon#read 5, iclass 32, count 0 2006.201.21:04:35.86#ibcon#about to read 6, iclass 32, count 0 2006.201.21:04:35.86#ibcon#read 6, iclass 32, count 0 2006.201.21:04:35.86#ibcon#end of sib2, iclass 32, count 0 2006.201.21:04:35.86#ibcon#*mode == 0, iclass 32, count 0 2006.201.21:04:35.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.21:04:35.86#ibcon#[25=USB\r\n] 2006.201.21:04:35.86#ibcon#*before write, iclass 32, count 0 2006.201.21:04:35.86#ibcon#enter sib2, iclass 32, count 0 2006.201.21:04:35.86#ibcon#flushed, iclass 32, count 0 2006.201.21:04:35.86#ibcon#about to write, iclass 32, count 0 2006.201.21:04:35.86#ibcon#wrote, iclass 32, count 0 2006.201.21:04:35.86#ibcon#about to read 3, iclass 32, count 0 2006.201.21:04:35.89#ibcon#read 3, iclass 32, count 0 2006.201.21:04:35.89#ibcon#about to read 4, iclass 32, count 0 2006.201.21:04:35.89#ibcon#read 4, iclass 32, count 0 2006.201.21:04:35.89#ibcon#about to read 5, iclass 32, count 0 2006.201.21:04:35.89#ibcon#read 5, iclass 32, count 0 2006.201.21:04:35.89#ibcon#about to read 6, iclass 32, count 0 2006.201.21:04:35.89#ibcon#read 6, iclass 32, count 0 2006.201.21:04:35.89#ibcon#end of sib2, iclass 32, count 0 2006.201.21:04:35.89#ibcon#*after write, iclass 32, count 0 2006.201.21:04:35.89#ibcon#*before return 0, iclass 32, count 0 2006.201.21:04:35.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:35.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:35.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.21:04:35.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.21:04:35.89$vck44/valo=4,624.99 2006.201.21:04:35.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.21:04:35.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.21:04:35.89#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:35.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:35.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:35.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:35.89#ibcon#enter wrdev, iclass 34, count 0 2006.201.21:04:35.89#ibcon#first serial, iclass 34, count 0 2006.201.21:04:35.89#ibcon#enter sib2, iclass 34, count 0 2006.201.21:04:35.89#ibcon#flushed, iclass 34, count 0 2006.201.21:04:35.89#ibcon#about to write, iclass 34, count 0 2006.201.21:04:35.89#ibcon#wrote, iclass 34, count 0 2006.201.21:04:35.89#ibcon#about to read 3, iclass 34, count 0 2006.201.21:04:35.91#ibcon#read 3, iclass 34, count 0 2006.201.21:04:35.91#ibcon#about to read 4, iclass 34, count 0 2006.201.21:04:35.91#ibcon#read 4, iclass 34, count 0 2006.201.21:04:35.91#ibcon#about to read 5, iclass 34, count 0 2006.201.21:04:35.91#ibcon#read 5, iclass 34, count 0 2006.201.21:04:35.91#ibcon#about to read 6, iclass 34, count 0 2006.201.21:04:35.91#ibcon#read 6, iclass 34, count 0 2006.201.21:04:35.91#ibcon#end of sib2, iclass 34, count 0 2006.201.21:04:35.91#ibcon#*mode == 0, iclass 34, count 0 2006.201.21:04:35.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.21:04:35.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.21:04:35.91#ibcon#*before write, iclass 34, count 0 2006.201.21:04:35.91#ibcon#enter sib2, iclass 34, count 0 2006.201.21:04:35.91#ibcon#flushed, iclass 34, count 0 2006.201.21:04:35.91#ibcon#about to write, iclass 34, count 0 2006.201.21:04:35.91#ibcon#wrote, iclass 34, count 0 2006.201.21:04:35.91#ibcon#about to read 3, iclass 34, count 0 2006.201.21:04:35.95#ibcon#read 3, iclass 34, count 0 2006.201.21:04:35.95#ibcon#about to read 4, iclass 34, count 0 2006.201.21:04:35.95#ibcon#read 4, iclass 34, count 0 2006.201.21:04:35.95#ibcon#about to read 5, iclass 34, count 0 2006.201.21:04:35.95#ibcon#read 5, iclass 34, count 0 2006.201.21:04:35.95#ibcon#about to read 6, iclass 34, count 0 2006.201.21:04:35.95#ibcon#read 6, iclass 34, count 0 2006.201.21:04:35.95#ibcon#end of sib2, iclass 34, count 0 2006.201.21:04:35.95#ibcon#*after write, iclass 34, count 0 2006.201.21:04:35.95#ibcon#*before return 0, iclass 34, count 0 2006.201.21:04:35.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:35.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:35.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.21:04:35.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.21:04:35.95$vck44/va=4,7 2006.201.21:04:35.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.21:04:35.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.21:04:35.95#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:35.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:36.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:36.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:36.01#ibcon#enter wrdev, iclass 36, count 2 2006.201.21:04:36.01#ibcon#first serial, iclass 36, count 2 2006.201.21:04:36.01#ibcon#enter sib2, iclass 36, count 2 2006.201.21:04:36.01#ibcon#flushed, iclass 36, count 2 2006.201.21:04:36.01#ibcon#about to write, iclass 36, count 2 2006.201.21:04:36.01#ibcon#wrote, iclass 36, count 2 2006.201.21:04:36.01#ibcon#about to read 3, iclass 36, count 2 2006.201.21:04:36.03#ibcon#read 3, iclass 36, count 2 2006.201.21:04:36.03#ibcon#about to read 4, iclass 36, count 2 2006.201.21:04:36.03#ibcon#read 4, iclass 36, count 2 2006.201.21:04:36.03#ibcon#about to read 5, iclass 36, count 2 2006.201.21:04:36.03#ibcon#read 5, iclass 36, count 2 2006.201.21:04:36.03#ibcon#about to read 6, iclass 36, count 2 2006.201.21:04:36.03#ibcon#read 6, iclass 36, count 2 2006.201.21:04:36.03#ibcon#end of sib2, iclass 36, count 2 2006.201.21:04:36.03#ibcon#*mode == 0, iclass 36, count 2 2006.201.21:04:36.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.21:04:36.03#ibcon#[25=AT04-07\r\n] 2006.201.21:04:36.03#ibcon#*before write, iclass 36, count 2 2006.201.21:04:36.03#ibcon#enter sib2, iclass 36, count 2 2006.201.21:04:36.03#ibcon#flushed, iclass 36, count 2 2006.201.21:04:36.03#ibcon#about to write, iclass 36, count 2 2006.201.21:04:36.03#ibcon#wrote, iclass 36, count 2 2006.201.21:04:36.03#ibcon#about to read 3, iclass 36, count 2 2006.201.21:04:36.06#ibcon#read 3, iclass 36, count 2 2006.201.21:04:36.06#ibcon#about to read 4, iclass 36, count 2 2006.201.21:04:36.06#ibcon#read 4, iclass 36, count 2 2006.201.21:04:36.06#ibcon#about to read 5, iclass 36, count 2 2006.201.21:04:36.06#ibcon#read 5, iclass 36, count 2 2006.201.21:04:36.06#ibcon#about to read 6, iclass 36, count 2 2006.201.21:04:36.06#ibcon#read 6, iclass 36, count 2 2006.201.21:04:36.06#ibcon#end of sib2, iclass 36, count 2 2006.201.21:04:36.06#ibcon#*after write, iclass 36, count 2 2006.201.21:04:36.06#ibcon#*before return 0, iclass 36, count 2 2006.201.21:04:36.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:36.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:36.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.21:04:36.06#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:36.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:36.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:36.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:36.18#ibcon#enter wrdev, iclass 36, count 0 2006.201.21:04:36.18#ibcon#first serial, iclass 36, count 0 2006.201.21:04:36.18#ibcon#enter sib2, iclass 36, count 0 2006.201.21:04:36.18#ibcon#flushed, iclass 36, count 0 2006.201.21:04:36.18#ibcon#about to write, iclass 36, count 0 2006.201.21:04:36.18#ibcon#wrote, iclass 36, count 0 2006.201.21:04:36.18#ibcon#about to read 3, iclass 36, count 0 2006.201.21:04:36.20#ibcon#read 3, iclass 36, count 0 2006.201.21:04:36.20#ibcon#about to read 4, iclass 36, count 0 2006.201.21:04:36.20#ibcon#read 4, iclass 36, count 0 2006.201.21:04:36.20#ibcon#about to read 5, iclass 36, count 0 2006.201.21:04:36.20#ibcon#read 5, iclass 36, count 0 2006.201.21:04:36.20#ibcon#about to read 6, iclass 36, count 0 2006.201.21:04:36.20#ibcon#read 6, iclass 36, count 0 2006.201.21:04:36.20#ibcon#end of sib2, iclass 36, count 0 2006.201.21:04:36.20#ibcon#*mode == 0, iclass 36, count 0 2006.201.21:04:36.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.21:04:36.20#ibcon#[25=USB\r\n] 2006.201.21:04:36.20#ibcon#*before write, iclass 36, count 0 2006.201.21:04:36.20#ibcon#enter sib2, iclass 36, count 0 2006.201.21:04:36.20#ibcon#flushed, iclass 36, count 0 2006.201.21:04:36.20#ibcon#about to write, iclass 36, count 0 2006.201.21:04:36.20#ibcon#wrote, iclass 36, count 0 2006.201.21:04:36.20#ibcon#about to read 3, iclass 36, count 0 2006.201.21:04:36.23#ibcon#read 3, iclass 36, count 0 2006.201.21:04:36.23#ibcon#about to read 4, iclass 36, count 0 2006.201.21:04:36.23#ibcon#read 4, iclass 36, count 0 2006.201.21:04:36.23#ibcon#about to read 5, iclass 36, count 0 2006.201.21:04:36.23#ibcon#read 5, iclass 36, count 0 2006.201.21:04:36.23#ibcon#about to read 6, iclass 36, count 0 2006.201.21:04:36.23#ibcon#read 6, iclass 36, count 0 2006.201.21:04:36.23#ibcon#end of sib2, iclass 36, count 0 2006.201.21:04:36.23#ibcon#*after write, iclass 36, count 0 2006.201.21:04:36.23#ibcon#*before return 0, iclass 36, count 0 2006.201.21:04:36.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:36.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:36.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.21:04:36.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.21:04:36.23$vck44/valo=5,734.99 2006.201.21:04:36.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.21:04:36.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.21:04:36.23#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:36.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:36.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:36.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:36.23#ibcon#enter wrdev, iclass 38, count 0 2006.201.21:04:36.23#ibcon#first serial, iclass 38, count 0 2006.201.21:04:36.23#ibcon#enter sib2, iclass 38, count 0 2006.201.21:04:36.23#ibcon#flushed, iclass 38, count 0 2006.201.21:04:36.23#ibcon#about to write, iclass 38, count 0 2006.201.21:04:36.23#ibcon#wrote, iclass 38, count 0 2006.201.21:04:36.23#ibcon#about to read 3, iclass 38, count 0 2006.201.21:04:36.25#ibcon#read 3, iclass 38, count 0 2006.201.21:04:36.25#ibcon#about to read 4, iclass 38, count 0 2006.201.21:04:36.25#ibcon#read 4, iclass 38, count 0 2006.201.21:04:36.25#ibcon#about to read 5, iclass 38, count 0 2006.201.21:04:36.25#ibcon#read 5, iclass 38, count 0 2006.201.21:04:36.25#ibcon#about to read 6, iclass 38, count 0 2006.201.21:04:36.25#ibcon#read 6, iclass 38, count 0 2006.201.21:04:36.25#ibcon#end of sib2, iclass 38, count 0 2006.201.21:04:36.25#ibcon#*mode == 0, iclass 38, count 0 2006.201.21:04:36.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.21:04:36.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.21:04:36.25#ibcon#*before write, iclass 38, count 0 2006.201.21:04:36.25#ibcon#enter sib2, iclass 38, count 0 2006.201.21:04:36.25#ibcon#flushed, iclass 38, count 0 2006.201.21:04:36.25#ibcon#about to write, iclass 38, count 0 2006.201.21:04:36.25#ibcon#wrote, iclass 38, count 0 2006.201.21:04:36.25#ibcon#about to read 3, iclass 38, count 0 2006.201.21:04:36.29#ibcon#read 3, iclass 38, count 0 2006.201.21:04:36.29#ibcon#about to read 4, iclass 38, count 0 2006.201.21:04:36.29#ibcon#read 4, iclass 38, count 0 2006.201.21:04:36.29#ibcon#about to read 5, iclass 38, count 0 2006.201.21:04:36.29#ibcon#read 5, iclass 38, count 0 2006.201.21:04:36.29#ibcon#about to read 6, iclass 38, count 0 2006.201.21:04:36.29#ibcon#read 6, iclass 38, count 0 2006.201.21:04:36.29#ibcon#end of sib2, iclass 38, count 0 2006.201.21:04:36.29#ibcon#*after write, iclass 38, count 0 2006.201.21:04:36.29#ibcon#*before return 0, iclass 38, count 0 2006.201.21:04:36.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:36.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:36.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.21:04:36.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.21:04:36.29$vck44/va=5,4 2006.201.21:04:36.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.21:04:36.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.21:04:36.29#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:36.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:36.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:36.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:36.35#ibcon#enter wrdev, iclass 40, count 2 2006.201.21:04:36.35#ibcon#first serial, iclass 40, count 2 2006.201.21:04:36.35#ibcon#enter sib2, iclass 40, count 2 2006.201.21:04:36.35#ibcon#flushed, iclass 40, count 2 2006.201.21:04:36.35#ibcon#about to write, iclass 40, count 2 2006.201.21:04:36.35#ibcon#wrote, iclass 40, count 2 2006.201.21:04:36.35#ibcon#about to read 3, iclass 40, count 2 2006.201.21:04:36.37#ibcon#read 3, iclass 40, count 2 2006.201.21:04:36.37#ibcon#about to read 4, iclass 40, count 2 2006.201.21:04:36.37#ibcon#read 4, iclass 40, count 2 2006.201.21:04:36.37#ibcon#about to read 5, iclass 40, count 2 2006.201.21:04:36.37#ibcon#read 5, iclass 40, count 2 2006.201.21:04:36.37#ibcon#about to read 6, iclass 40, count 2 2006.201.21:04:36.37#ibcon#read 6, iclass 40, count 2 2006.201.21:04:36.37#ibcon#end of sib2, iclass 40, count 2 2006.201.21:04:36.37#ibcon#*mode == 0, iclass 40, count 2 2006.201.21:04:36.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.21:04:36.37#ibcon#[25=AT05-04\r\n] 2006.201.21:04:36.37#ibcon#*before write, iclass 40, count 2 2006.201.21:04:36.37#ibcon#enter sib2, iclass 40, count 2 2006.201.21:04:36.37#ibcon#flushed, iclass 40, count 2 2006.201.21:04:36.37#ibcon#about to write, iclass 40, count 2 2006.201.21:04:36.37#ibcon#wrote, iclass 40, count 2 2006.201.21:04:36.37#ibcon#about to read 3, iclass 40, count 2 2006.201.21:04:36.40#ibcon#read 3, iclass 40, count 2 2006.201.21:04:36.40#ibcon#about to read 4, iclass 40, count 2 2006.201.21:04:36.40#ibcon#read 4, iclass 40, count 2 2006.201.21:04:36.40#ibcon#about to read 5, iclass 40, count 2 2006.201.21:04:36.40#ibcon#read 5, iclass 40, count 2 2006.201.21:04:36.40#ibcon#about to read 6, iclass 40, count 2 2006.201.21:04:36.40#ibcon#read 6, iclass 40, count 2 2006.201.21:04:36.40#ibcon#end of sib2, iclass 40, count 2 2006.201.21:04:36.40#ibcon#*after write, iclass 40, count 2 2006.201.21:04:36.40#ibcon#*before return 0, iclass 40, count 2 2006.201.21:04:36.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:36.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:36.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.21:04:36.40#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:36.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:36.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:36.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:36.52#ibcon#enter wrdev, iclass 40, count 0 2006.201.21:04:36.52#ibcon#first serial, iclass 40, count 0 2006.201.21:04:36.52#ibcon#enter sib2, iclass 40, count 0 2006.201.21:04:36.52#ibcon#flushed, iclass 40, count 0 2006.201.21:04:36.52#ibcon#about to write, iclass 40, count 0 2006.201.21:04:36.52#ibcon#wrote, iclass 40, count 0 2006.201.21:04:36.52#ibcon#about to read 3, iclass 40, count 0 2006.201.21:04:36.54#ibcon#read 3, iclass 40, count 0 2006.201.21:04:36.54#ibcon#about to read 4, iclass 40, count 0 2006.201.21:04:36.54#ibcon#read 4, iclass 40, count 0 2006.201.21:04:36.54#ibcon#about to read 5, iclass 40, count 0 2006.201.21:04:36.54#ibcon#read 5, iclass 40, count 0 2006.201.21:04:36.54#ibcon#about to read 6, iclass 40, count 0 2006.201.21:04:36.54#ibcon#read 6, iclass 40, count 0 2006.201.21:04:36.54#ibcon#end of sib2, iclass 40, count 0 2006.201.21:04:36.54#ibcon#*mode == 0, iclass 40, count 0 2006.201.21:04:36.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.21:04:36.54#ibcon#[25=USB\r\n] 2006.201.21:04:36.54#ibcon#*before write, iclass 40, count 0 2006.201.21:04:36.54#ibcon#enter sib2, iclass 40, count 0 2006.201.21:04:36.54#ibcon#flushed, iclass 40, count 0 2006.201.21:04:36.54#ibcon#about to write, iclass 40, count 0 2006.201.21:04:36.54#ibcon#wrote, iclass 40, count 0 2006.201.21:04:36.54#ibcon#about to read 3, iclass 40, count 0 2006.201.21:04:36.57#ibcon#read 3, iclass 40, count 0 2006.201.21:04:36.57#ibcon#about to read 4, iclass 40, count 0 2006.201.21:04:36.57#ibcon#read 4, iclass 40, count 0 2006.201.21:04:36.57#ibcon#about to read 5, iclass 40, count 0 2006.201.21:04:36.57#ibcon#read 5, iclass 40, count 0 2006.201.21:04:36.57#ibcon#about to read 6, iclass 40, count 0 2006.201.21:04:36.57#ibcon#read 6, iclass 40, count 0 2006.201.21:04:36.57#ibcon#end of sib2, iclass 40, count 0 2006.201.21:04:36.57#ibcon#*after write, iclass 40, count 0 2006.201.21:04:36.57#ibcon#*before return 0, iclass 40, count 0 2006.201.21:04:36.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:36.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:36.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.21:04:36.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.21:04:36.57$vck44/valo=6,814.99 2006.201.21:04:36.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.21:04:36.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.21:04:36.57#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:36.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:36.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:36.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:36.57#ibcon#enter wrdev, iclass 4, count 0 2006.201.21:04:36.57#ibcon#first serial, iclass 4, count 0 2006.201.21:04:36.57#ibcon#enter sib2, iclass 4, count 0 2006.201.21:04:36.57#ibcon#flushed, iclass 4, count 0 2006.201.21:04:36.57#ibcon#about to write, iclass 4, count 0 2006.201.21:04:36.57#ibcon#wrote, iclass 4, count 0 2006.201.21:04:36.57#ibcon#about to read 3, iclass 4, count 0 2006.201.21:04:36.59#ibcon#read 3, iclass 4, count 0 2006.201.21:04:36.59#ibcon#about to read 4, iclass 4, count 0 2006.201.21:04:36.59#ibcon#read 4, iclass 4, count 0 2006.201.21:04:36.59#ibcon#about to read 5, iclass 4, count 0 2006.201.21:04:36.59#ibcon#read 5, iclass 4, count 0 2006.201.21:04:36.59#ibcon#about to read 6, iclass 4, count 0 2006.201.21:04:36.59#ibcon#read 6, iclass 4, count 0 2006.201.21:04:36.59#ibcon#end of sib2, iclass 4, count 0 2006.201.21:04:36.59#ibcon#*mode == 0, iclass 4, count 0 2006.201.21:04:36.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.21:04:36.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.21:04:36.59#ibcon#*before write, iclass 4, count 0 2006.201.21:04:36.59#ibcon#enter sib2, iclass 4, count 0 2006.201.21:04:36.59#ibcon#flushed, iclass 4, count 0 2006.201.21:04:36.59#ibcon#about to write, iclass 4, count 0 2006.201.21:04:36.59#ibcon#wrote, iclass 4, count 0 2006.201.21:04:36.59#ibcon#about to read 3, iclass 4, count 0 2006.201.21:04:36.63#ibcon#read 3, iclass 4, count 0 2006.201.21:04:36.63#ibcon#about to read 4, iclass 4, count 0 2006.201.21:04:36.63#ibcon#read 4, iclass 4, count 0 2006.201.21:04:36.63#ibcon#about to read 5, iclass 4, count 0 2006.201.21:04:36.63#ibcon#read 5, iclass 4, count 0 2006.201.21:04:36.63#ibcon#about to read 6, iclass 4, count 0 2006.201.21:04:36.63#ibcon#read 6, iclass 4, count 0 2006.201.21:04:36.63#ibcon#end of sib2, iclass 4, count 0 2006.201.21:04:36.63#ibcon#*after write, iclass 4, count 0 2006.201.21:04:36.63#ibcon#*before return 0, iclass 4, count 0 2006.201.21:04:36.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:36.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:36.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.21:04:36.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.21:04:36.63$vck44/va=6,5 2006.201.21:04:36.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.21:04:36.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.21:04:36.63#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:36.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:36.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:36.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:36.69#ibcon#enter wrdev, iclass 6, count 2 2006.201.21:04:36.69#ibcon#first serial, iclass 6, count 2 2006.201.21:04:36.69#ibcon#enter sib2, iclass 6, count 2 2006.201.21:04:36.69#ibcon#flushed, iclass 6, count 2 2006.201.21:04:36.69#ibcon#about to write, iclass 6, count 2 2006.201.21:04:36.69#ibcon#wrote, iclass 6, count 2 2006.201.21:04:36.69#ibcon#about to read 3, iclass 6, count 2 2006.201.21:04:36.71#ibcon#read 3, iclass 6, count 2 2006.201.21:04:36.71#ibcon#about to read 4, iclass 6, count 2 2006.201.21:04:36.71#ibcon#read 4, iclass 6, count 2 2006.201.21:04:36.71#ibcon#about to read 5, iclass 6, count 2 2006.201.21:04:36.71#ibcon#read 5, iclass 6, count 2 2006.201.21:04:36.71#ibcon#about to read 6, iclass 6, count 2 2006.201.21:04:36.71#ibcon#read 6, iclass 6, count 2 2006.201.21:04:36.71#ibcon#end of sib2, iclass 6, count 2 2006.201.21:04:36.71#ibcon#*mode == 0, iclass 6, count 2 2006.201.21:04:36.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.21:04:36.71#ibcon#[25=AT06-05\r\n] 2006.201.21:04:36.71#ibcon#*before write, iclass 6, count 2 2006.201.21:04:36.71#ibcon#enter sib2, iclass 6, count 2 2006.201.21:04:36.71#ibcon#flushed, iclass 6, count 2 2006.201.21:04:36.71#ibcon#about to write, iclass 6, count 2 2006.201.21:04:36.71#ibcon#wrote, iclass 6, count 2 2006.201.21:04:36.71#ibcon#about to read 3, iclass 6, count 2 2006.201.21:04:36.74#ibcon#read 3, iclass 6, count 2 2006.201.21:04:36.74#ibcon#about to read 4, iclass 6, count 2 2006.201.21:04:36.74#ibcon#read 4, iclass 6, count 2 2006.201.21:04:36.74#ibcon#about to read 5, iclass 6, count 2 2006.201.21:04:36.74#ibcon#read 5, iclass 6, count 2 2006.201.21:04:36.74#ibcon#about to read 6, iclass 6, count 2 2006.201.21:04:36.74#ibcon#read 6, iclass 6, count 2 2006.201.21:04:36.74#ibcon#end of sib2, iclass 6, count 2 2006.201.21:04:36.74#ibcon#*after write, iclass 6, count 2 2006.201.21:04:36.74#ibcon#*before return 0, iclass 6, count 2 2006.201.21:04:36.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:36.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:36.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.21:04:36.74#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:36.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:36.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:36.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:36.86#ibcon#enter wrdev, iclass 6, count 0 2006.201.21:04:36.86#ibcon#first serial, iclass 6, count 0 2006.201.21:04:36.86#ibcon#enter sib2, iclass 6, count 0 2006.201.21:04:36.86#ibcon#flushed, iclass 6, count 0 2006.201.21:04:36.86#ibcon#about to write, iclass 6, count 0 2006.201.21:04:36.86#ibcon#wrote, iclass 6, count 0 2006.201.21:04:36.86#ibcon#about to read 3, iclass 6, count 0 2006.201.21:04:36.88#ibcon#read 3, iclass 6, count 0 2006.201.21:04:36.88#ibcon#about to read 4, iclass 6, count 0 2006.201.21:04:36.88#ibcon#read 4, iclass 6, count 0 2006.201.21:04:36.88#ibcon#about to read 5, iclass 6, count 0 2006.201.21:04:36.88#ibcon#read 5, iclass 6, count 0 2006.201.21:04:36.88#ibcon#about to read 6, iclass 6, count 0 2006.201.21:04:36.88#ibcon#read 6, iclass 6, count 0 2006.201.21:04:36.88#ibcon#end of sib2, iclass 6, count 0 2006.201.21:04:36.88#ibcon#*mode == 0, iclass 6, count 0 2006.201.21:04:36.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.21:04:36.88#ibcon#[25=USB\r\n] 2006.201.21:04:36.88#ibcon#*before write, iclass 6, count 0 2006.201.21:04:36.88#ibcon#enter sib2, iclass 6, count 0 2006.201.21:04:36.88#ibcon#flushed, iclass 6, count 0 2006.201.21:04:36.88#ibcon#about to write, iclass 6, count 0 2006.201.21:04:36.88#ibcon#wrote, iclass 6, count 0 2006.201.21:04:36.88#ibcon#about to read 3, iclass 6, count 0 2006.201.21:04:36.91#ibcon#read 3, iclass 6, count 0 2006.201.21:04:36.91#ibcon#about to read 4, iclass 6, count 0 2006.201.21:04:36.91#ibcon#read 4, iclass 6, count 0 2006.201.21:04:36.91#ibcon#about to read 5, iclass 6, count 0 2006.201.21:04:36.91#ibcon#read 5, iclass 6, count 0 2006.201.21:04:36.91#ibcon#about to read 6, iclass 6, count 0 2006.201.21:04:36.91#ibcon#read 6, iclass 6, count 0 2006.201.21:04:36.91#ibcon#end of sib2, iclass 6, count 0 2006.201.21:04:36.91#ibcon#*after write, iclass 6, count 0 2006.201.21:04:36.91#ibcon#*before return 0, iclass 6, count 0 2006.201.21:04:36.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:36.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:36.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.21:04:36.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.21:04:36.91$vck44/valo=7,864.99 2006.201.21:04:36.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.21:04:36.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.21:04:36.91#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:36.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:36.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:36.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:36.91#ibcon#enter wrdev, iclass 10, count 0 2006.201.21:04:36.91#ibcon#first serial, iclass 10, count 0 2006.201.21:04:36.91#ibcon#enter sib2, iclass 10, count 0 2006.201.21:04:36.91#ibcon#flushed, iclass 10, count 0 2006.201.21:04:36.91#ibcon#about to write, iclass 10, count 0 2006.201.21:04:36.91#ibcon#wrote, iclass 10, count 0 2006.201.21:04:36.91#ibcon#about to read 3, iclass 10, count 0 2006.201.21:04:36.93#ibcon#read 3, iclass 10, count 0 2006.201.21:04:36.93#ibcon#about to read 4, iclass 10, count 0 2006.201.21:04:36.93#ibcon#read 4, iclass 10, count 0 2006.201.21:04:36.93#ibcon#about to read 5, iclass 10, count 0 2006.201.21:04:36.93#ibcon#read 5, iclass 10, count 0 2006.201.21:04:36.93#ibcon#about to read 6, iclass 10, count 0 2006.201.21:04:36.93#ibcon#read 6, iclass 10, count 0 2006.201.21:04:36.93#ibcon#end of sib2, iclass 10, count 0 2006.201.21:04:36.93#ibcon#*mode == 0, iclass 10, count 0 2006.201.21:04:36.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.21:04:36.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.21:04:36.93#ibcon#*before write, iclass 10, count 0 2006.201.21:04:36.93#ibcon#enter sib2, iclass 10, count 0 2006.201.21:04:36.93#ibcon#flushed, iclass 10, count 0 2006.201.21:04:36.93#ibcon#about to write, iclass 10, count 0 2006.201.21:04:36.93#ibcon#wrote, iclass 10, count 0 2006.201.21:04:36.93#ibcon#about to read 3, iclass 10, count 0 2006.201.21:04:36.97#ibcon#read 3, iclass 10, count 0 2006.201.21:04:36.97#ibcon#about to read 4, iclass 10, count 0 2006.201.21:04:36.97#ibcon#read 4, iclass 10, count 0 2006.201.21:04:36.97#ibcon#about to read 5, iclass 10, count 0 2006.201.21:04:36.97#ibcon#read 5, iclass 10, count 0 2006.201.21:04:36.97#ibcon#about to read 6, iclass 10, count 0 2006.201.21:04:36.97#ibcon#read 6, iclass 10, count 0 2006.201.21:04:36.97#ibcon#end of sib2, iclass 10, count 0 2006.201.21:04:36.97#ibcon#*after write, iclass 10, count 0 2006.201.21:04:36.97#ibcon#*before return 0, iclass 10, count 0 2006.201.21:04:36.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:36.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:36.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.21:04:36.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.21:04:36.97$vck44/va=7,5 2006.201.21:04:36.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.21:04:36.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.21:04:36.97#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:36.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:37.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:37.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:37.03#ibcon#enter wrdev, iclass 12, count 2 2006.201.21:04:37.03#ibcon#first serial, iclass 12, count 2 2006.201.21:04:37.03#ibcon#enter sib2, iclass 12, count 2 2006.201.21:04:37.03#ibcon#flushed, iclass 12, count 2 2006.201.21:04:37.03#ibcon#about to write, iclass 12, count 2 2006.201.21:04:37.03#ibcon#wrote, iclass 12, count 2 2006.201.21:04:37.03#ibcon#about to read 3, iclass 12, count 2 2006.201.21:04:37.05#ibcon#read 3, iclass 12, count 2 2006.201.21:04:37.05#ibcon#about to read 4, iclass 12, count 2 2006.201.21:04:37.05#ibcon#read 4, iclass 12, count 2 2006.201.21:04:37.05#ibcon#about to read 5, iclass 12, count 2 2006.201.21:04:37.05#ibcon#read 5, iclass 12, count 2 2006.201.21:04:37.05#ibcon#about to read 6, iclass 12, count 2 2006.201.21:04:37.05#ibcon#read 6, iclass 12, count 2 2006.201.21:04:37.05#ibcon#end of sib2, iclass 12, count 2 2006.201.21:04:37.05#ibcon#*mode == 0, iclass 12, count 2 2006.201.21:04:37.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.21:04:37.05#ibcon#[25=AT07-05\r\n] 2006.201.21:04:37.05#ibcon#*before write, iclass 12, count 2 2006.201.21:04:37.05#ibcon#enter sib2, iclass 12, count 2 2006.201.21:04:37.05#ibcon#flushed, iclass 12, count 2 2006.201.21:04:37.05#ibcon#about to write, iclass 12, count 2 2006.201.21:04:37.05#ibcon#wrote, iclass 12, count 2 2006.201.21:04:37.05#ibcon#about to read 3, iclass 12, count 2 2006.201.21:04:37.08#ibcon#read 3, iclass 12, count 2 2006.201.21:04:37.08#ibcon#about to read 4, iclass 12, count 2 2006.201.21:04:37.08#ibcon#read 4, iclass 12, count 2 2006.201.21:04:37.08#ibcon#about to read 5, iclass 12, count 2 2006.201.21:04:37.08#ibcon#read 5, iclass 12, count 2 2006.201.21:04:37.08#ibcon#about to read 6, iclass 12, count 2 2006.201.21:04:37.08#ibcon#read 6, iclass 12, count 2 2006.201.21:04:37.08#ibcon#end of sib2, iclass 12, count 2 2006.201.21:04:37.08#ibcon#*after write, iclass 12, count 2 2006.201.21:04:37.08#ibcon#*before return 0, iclass 12, count 2 2006.201.21:04:37.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:37.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:37.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.21:04:37.08#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:37.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:37.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:37.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:37.20#ibcon#enter wrdev, iclass 12, count 0 2006.201.21:04:37.20#ibcon#first serial, iclass 12, count 0 2006.201.21:04:37.20#ibcon#enter sib2, iclass 12, count 0 2006.201.21:04:37.20#ibcon#flushed, iclass 12, count 0 2006.201.21:04:37.20#ibcon#about to write, iclass 12, count 0 2006.201.21:04:37.20#ibcon#wrote, iclass 12, count 0 2006.201.21:04:37.20#ibcon#about to read 3, iclass 12, count 0 2006.201.21:04:37.22#ibcon#read 3, iclass 12, count 0 2006.201.21:04:37.22#ibcon#about to read 4, iclass 12, count 0 2006.201.21:04:37.22#ibcon#read 4, iclass 12, count 0 2006.201.21:04:37.22#ibcon#about to read 5, iclass 12, count 0 2006.201.21:04:37.22#ibcon#read 5, iclass 12, count 0 2006.201.21:04:37.22#ibcon#about to read 6, iclass 12, count 0 2006.201.21:04:37.22#ibcon#read 6, iclass 12, count 0 2006.201.21:04:37.22#ibcon#end of sib2, iclass 12, count 0 2006.201.21:04:37.22#ibcon#*mode == 0, iclass 12, count 0 2006.201.21:04:37.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.21:04:37.22#ibcon#[25=USB\r\n] 2006.201.21:04:37.22#ibcon#*before write, iclass 12, count 0 2006.201.21:04:37.22#ibcon#enter sib2, iclass 12, count 0 2006.201.21:04:37.22#ibcon#flushed, iclass 12, count 0 2006.201.21:04:37.22#ibcon#about to write, iclass 12, count 0 2006.201.21:04:37.22#ibcon#wrote, iclass 12, count 0 2006.201.21:04:37.22#ibcon#about to read 3, iclass 12, count 0 2006.201.21:04:37.25#ibcon#read 3, iclass 12, count 0 2006.201.21:04:37.25#ibcon#about to read 4, iclass 12, count 0 2006.201.21:04:37.25#ibcon#read 4, iclass 12, count 0 2006.201.21:04:37.25#ibcon#about to read 5, iclass 12, count 0 2006.201.21:04:37.25#ibcon#read 5, iclass 12, count 0 2006.201.21:04:37.25#ibcon#about to read 6, iclass 12, count 0 2006.201.21:04:37.25#ibcon#read 6, iclass 12, count 0 2006.201.21:04:37.25#ibcon#end of sib2, iclass 12, count 0 2006.201.21:04:37.25#ibcon#*after write, iclass 12, count 0 2006.201.21:04:37.25#ibcon#*before return 0, iclass 12, count 0 2006.201.21:04:37.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:37.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:37.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.21:04:37.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.21:04:37.25$vck44/valo=8,884.99 2006.201.21:04:37.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.21:04:37.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.21:04:37.25#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:37.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:37.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:37.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:37.25#ibcon#enter wrdev, iclass 14, count 0 2006.201.21:04:37.25#ibcon#first serial, iclass 14, count 0 2006.201.21:04:37.25#ibcon#enter sib2, iclass 14, count 0 2006.201.21:04:37.25#ibcon#flushed, iclass 14, count 0 2006.201.21:04:37.25#ibcon#about to write, iclass 14, count 0 2006.201.21:04:37.25#ibcon#wrote, iclass 14, count 0 2006.201.21:04:37.25#ibcon#about to read 3, iclass 14, count 0 2006.201.21:04:37.27#ibcon#read 3, iclass 14, count 0 2006.201.21:04:37.27#ibcon#about to read 4, iclass 14, count 0 2006.201.21:04:37.27#ibcon#read 4, iclass 14, count 0 2006.201.21:04:37.27#ibcon#about to read 5, iclass 14, count 0 2006.201.21:04:37.27#ibcon#read 5, iclass 14, count 0 2006.201.21:04:37.27#ibcon#about to read 6, iclass 14, count 0 2006.201.21:04:37.27#ibcon#read 6, iclass 14, count 0 2006.201.21:04:37.27#ibcon#end of sib2, iclass 14, count 0 2006.201.21:04:37.27#ibcon#*mode == 0, iclass 14, count 0 2006.201.21:04:37.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.21:04:37.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.21:04:37.27#ibcon#*before write, iclass 14, count 0 2006.201.21:04:37.27#ibcon#enter sib2, iclass 14, count 0 2006.201.21:04:37.27#ibcon#flushed, iclass 14, count 0 2006.201.21:04:37.27#ibcon#about to write, iclass 14, count 0 2006.201.21:04:37.27#ibcon#wrote, iclass 14, count 0 2006.201.21:04:37.27#ibcon#about to read 3, iclass 14, count 0 2006.201.21:04:37.31#ibcon#read 3, iclass 14, count 0 2006.201.21:04:37.31#ibcon#about to read 4, iclass 14, count 0 2006.201.21:04:37.31#ibcon#read 4, iclass 14, count 0 2006.201.21:04:37.31#ibcon#about to read 5, iclass 14, count 0 2006.201.21:04:37.31#ibcon#read 5, iclass 14, count 0 2006.201.21:04:37.31#ibcon#about to read 6, iclass 14, count 0 2006.201.21:04:37.31#ibcon#read 6, iclass 14, count 0 2006.201.21:04:37.31#ibcon#end of sib2, iclass 14, count 0 2006.201.21:04:37.31#ibcon#*after write, iclass 14, count 0 2006.201.21:04:37.31#ibcon#*before return 0, iclass 14, count 0 2006.201.21:04:37.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:37.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:37.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.21:04:37.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.21:04:37.31$vck44/va=8,4 2006.201.21:04:37.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.21:04:37.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.21:04:37.31#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:37.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:04:37.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:04:37.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:04:37.37#ibcon#enter wrdev, iclass 16, count 2 2006.201.21:04:37.37#ibcon#first serial, iclass 16, count 2 2006.201.21:04:37.37#ibcon#enter sib2, iclass 16, count 2 2006.201.21:04:37.37#ibcon#flushed, iclass 16, count 2 2006.201.21:04:37.37#ibcon#about to write, iclass 16, count 2 2006.201.21:04:37.37#ibcon#wrote, iclass 16, count 2 2006.201.21:04:37.37#ibcon#about to read 3, iclass 16, count 2 2006.201.21:04:37.39#ibcon#read 3, iclass 16, count 2 2006.201.21:04:37.39#ibcon#about to read 4, iclass 16, count 2 2006.201.21:04:37.39#ibcon#read 4, iclass 16, count 2 2006.201.21:04:37.39#ibcon#about to read 5, iclass 16, count 2 2006.201.21:04:37.39#ibcon#read 5, iclass 16, count 2 2006.201.21:04:37.39#ibcon#about to read 6, iclass 16, count 2 2006.201.21:04:37.39#ibcon#read 6, iclass 16, count 2 2006.201.21:04:37.39#ibcon#end of sib2, iclass 16, count 2 2006.201.21:04:37.39#ibcon#*mode == 0, iclass 16, count 2 2006.201.21:04:37.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.21:04:37.39#ibcon#[25=AT08-04\r\n] 2006.201.21:04:37.39#ibcon#*before write, iclass 16, count 2 2006.201.21:04:37.39#ibcon#enter sib2, iclass 16, count 2 2006.201.21:04:37.39#ibcon#flushed, iclass 16, count 2 2006.201.21:04:37.39#ibcon#about to write, iclass 16, count 2 2006.201.21:04:37.39#ibcon#wrote, iclass 16, count 2 2006.201.21:04:37.39#ibcon#about to read 3, iclass 16, count 2 2006.201.21:04:37.42#ibcon#read 3, iclass 16, count 2 2006.201.21:04:37.42#ibcon#about to read 4, iclass 16, count 2 2006.201.21:04:37.42#ibcon#read 4, iclass 16, count 2 2006.201.21:04:37.42#ibcon#about to read 5, iclass 16, count 2 2006.201.21:04:37.42#ibcon#read 5, iclass 16, count 2 2006.201.21:04:37.42#ibcon#about to read 6, iclass 16, count 2 2006.201.21:04:37.42#ibcon#read 6, iclass 16, count 2 2006.201.21:04:37.42#ibcon#end of sib2, iclass 16, count 2 2006.201.21:04:37.42#ibcon#*after write, iclass 16, count 2 2006.201.21:04:37.42#ibcon#*before return 0, iclass 16, count 2 2006.201.21:04:37.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:04:37.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:04:37.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.21:04:37.42#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:37.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:04:37.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:04:37.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:04:37.54#ibcon#enter wrdev, iclass 16, count 0 2006.201.21:04:37.54#ibcon#first serial, iclass 16, count 0 2006.201.21:04:37.54#ibcon#enter sib2, iclass 16, count 0 2006.201.21:04:37.54#ibcon#flushed, iclass 16, count 0 2006.201.21:04:37.54#ibcon#about to write, iclass 16, count 0 2006.201.21:04:37.54#ibcon#wrote, iclass 16, count 0 2006.201.21:04:37.54#ibcon#about to read 3, iclass 16, count 0 2006.201.21:04:37.56#ibcon#read 3, iclass 16, count 0 2006.201.21:04:37.56#ibcon#about to read 4, iclass 16, count 0 2006.201.21:04:37.56#ibcon#read 4, iclass 16, count 0 2006.201.21:04:37.56#ibcon#about to read 5, iclass 16, count 0 2006.201.21:04:37.56#ibcon#read 5, iclass 16, count 0 2006.201.21:04:37.56#ibcon#about to read 6, iclass 16, count 0 2006.201.21:04:37.56#ibcon#read 6, iclass 16, count 0 2006.201.21:04:37.56#ibcon#end of sib2, iclass 16, count 0 2006.201.21:04:37.56#ibcon#*mode == 0, iclass 16, count 0 2006.201.21:04:37.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.21:04:37.56#ibcon#[25=USB\r\n] 2006.201.21:04:37.56#ibcon#*before write, iclass 16, count 0 2006.201.21:04:37.56#ibcon#enter sib2, iclass 16, count 0 2006.201.21:04:37.56#ibcon#flushed, iclass 16, count 0 2006.201.21:04:37.56#ibcon#about to write, iclass 16, count 0 2006.201.21:04:37.56#ibcon#wrote, iclass 16, count 0 2006.201.21:04:37.56#ibcon#about to read 3, iclass 16, count 0 2006.201.21:04:37.59#ibcon#read 3, iclass 16, count 0 2006.201.21:04:37.59#ibcon#about to read 4, iclass 16, count 0 2006.201.21:04:37.59#ibcon#read 4, iclass 16, count 0 2006.201.21:04:37.59#ibcon#about to read 5, iclass 16, count 0 2006.201.21:04:37.59#ibcon#read 5, iclass 16, count 0 2006.201.21:04:37.59#ibcon#about to read 6, iclass 16, count 0 2006.201.21:04:37.59#ibcon#read 6, iclass 16, count 0 2006.201.21:04:37.59#ibcon#end of sib2, iclass 16, count 0 2006.201.21:04:37.59#ibcon#*after write, iclass 16, count 0 2006.201.21:04:37.59#ibcon#*before return 0, iclass 16, count 0 2006.201.21:04:37.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:04:37.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:04:37.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.21:04:37.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.21:04:37.59$vck44/vblo=1,629.99 2006.201.21:04:37.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.21:04:37.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.21:04:37.59#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:37.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:04:37.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:04:37.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:04:37.59#ibcon#enter wrdev, iclass 18, count 0 2006.201.21:04:37.59#ibcon#first serial, iclass 18, count 0 2006.201.21:04:37.59#ibcon#enter sib2, iclass 18, count 0 2006.201.21:04:37.59#ibcon#flushed, iclass 18, count 0 2006.201.21:04:37.59#ibcon#about to write, iclass 18, count 0 2006.201.21:04:37.59#ibcon#wrote, iclass 18, count 0 2006.201.21:04:37.59#ibcon#about to read 3, iclass 18, count 0 2006.201.21:04:37.61#ibcon#read 3, iclass 18, count 0 2006.201.21:04:37.61#ibcon#about to read 4, iclass 18, count 0 2006.201.21:04:37.61#ibcon#read 4, iclass 18, count 0 2006.201.21:04:37.61#ibcon#about to read 5, iclass 18, count 0 2006.201.21:04:37.61#ibcon#read 5, iclass 18, count 0 2006.201.21:04:37.61#ibcon#about to read 6, iclass 18, count 0 2006.201.21:04:37.61#ibcon#read 6, iclass 18, count 0 2006.201.21:04:37.61#ibcon#end of sib2, iclass 18, count 0 2006.201.21:04:37.61#ibcon#*mode == 0, iclass 18, count 0 2006.201.21:04:37.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.21:04:37.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.21:04:37.61#ibcon#*before write, iclass 18, count 0 2006.201.21:04:37.61#ibcon#enter sib2, iclass 18, count 0 2006.201.21:04:37.61#ibcon#flushed, iclass 18, count 0 2006.201.21:04:37.61#ibcon#about to write, iclass 18, count 0 2006.201.21:04:37.61#ibcon#wrote, iclass 18, count 0 2006.201.21:04:37.61#ibcon#about to read 3, iclass 18, count 0 2006.201.21:04:37.65#ibcon#read 3, iclass 18, count 0 2006.201.21:04:37.65#ibcon#about to read 4, iclass 18, count 0 2006.201.21:04:37.65#ibcon#read 4, iclass 18, count 0 2006.201.21:04:37.65#ibcon#about to read 5, iclass 18, count 0 2006.201.21:04:37.65#ibcon#read 5, iclass 18, count 0 2006.201.21:04:37.65#ibcon#about to read 6, iclass 18, count 0 2006.201.21:04:37.65#ibcon#read 6, iclass 18, count 0 2006.201.21:04:37.65#ibcon#end of sib2, iclass 18, count 0 2006.201.21:04:37.65#ibcon#*after write, iclass 18, count 0 2006.201.21:04:37.65#ibcon#*before return 0, iclass 18, count 0 2006.201.21:04:37.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:04:37.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:04:37.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.21:04:37.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.21:04:37.65$vck44/vb=1,4 2006.201.21:04:37.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.21:04:37.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.21:04:37.65#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:37.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:04:37.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:04:37.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:04:37.65#ibcon#enter wrdev, iclass 20, count 2 2006.201.21:04:37.65#ibcon#first serial, iclass 20, count 2 2006.201.21:04:37.65#ibcon#enter sib2, iclass 20, count 2 2006.201.21:04:37.65#ibcon#flushed, iclass 20, count 2 2006.201.21:04:37.65#ibcon#about to write, iclass 20, count 2 2006.201.21:04:37.65#ibcon#wrote, iclass 20, count 2 2006.201.21:04:37.65#ibcon#about to read 3, iclass 20, count 2 2006.201.21:04:37.67#ibcon#read 3, iclass 20, count 2 2006.201.21:04:37.67#ibcon#about to read 4, iclass 20, count 2 2006.201.21:04:37.67#ibcon#read 4, iclass 20, count 2 2006.201.21:04:37.67#ibcon#about to read 5, iclass 20, count 2 2006.201.21:04:37.67#ibcon#read 5, iclass 20, count 2 2006.201.21:04:37.67#ibcon#about to read 6, iclass 20, count 2 2006.201.21:04:37.67#ibcon#read 6, iclass 20, count 2 2006.201.21:04:37.67#ibcon#end of sib2, iclass 20, count 2 2006.201.21:04:37.67#ibcon#*mode == 0, iclass 20, count 2 2006.201.21:04:37.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.21:04:37.67#ibcon#[27=AT01-04\r\n] 2006.201.21:04:37.67#ibcon#*before write, iclass 20, count 2 2006.201.21:04:37.67#ibcon#enter sib2, iclass 20, count 2 2006.201.21:04:37.67#ibcon#flushed, iclass 20, count 2 2006.201.21:04:37.67#ibcon#about to write, iclass 20, count 2 2006.201.21:04:37.67#ibcon#wrote, iclass 20, count 2 2006.201.21:04:37.67#ibcon#about to read 3, iclass 20, count 2 2006.201.21:04:37.70#ibcon#read 3, iclass 20, count 2 2006.201.21:04:37.70#ibcon#about to read 4, iclass 20, count 2 2006.201.21:04:37.70#ibcon#read 4, iclass 20, count 2 2006.201.21:04:37.70#ibcon#about to read 5, iclass 20, count 2 2006.201.21:04:37.70#ibcon#read 5, iclass 20, count 2 2006.201.21:04:37.70#ibcon#about to read 6, iclass 20, count 2 2006.201.21:04:37.70#ibcon#read 6, iclass 20, count 2 2006.201.21:04:37.70#ibcon#end of sib2, iclass 20, count 2 2006.201.21:04:37.70#ibcon#*after write, iclass 20, count 2 2006.201.21:04:37.70#ibcon#*before return 0, iclass 20, count 2 2006.201.21:04:37.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:04:37.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:04:37.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.21:04:37.70#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:37.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:04:37.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:04:37.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:04:37.82#ibcon#enter wrdev, iclass 20, count 0 2006.201.21:04:37.82#ibcon#first serial, iclass 20, count 0 2006.201.21:04:37.82#ibcon#enter sib2, iclass 20, count 0 2006.201.21:04:37.82#ibcon#flushed, iclass 20, count 0 2006.201.21:04:37.82#ibcon#about to write, iclass 20, count 0 2006.201.21:04:37.82#ibcon#wrote, iclass 20, count 0 2006.201.21:04:37.82#ibcon#about to read 3, iclass 20, count 0 2006.201.21:04:37.84#ibcon#read 3, iclass 20, count 0 2006.201.21:04:37.84#ibcon#about to read 4, iclass 20, count 0 2006.201.21:04:37.84#ibcon#read 4, iclass 20, count 0 2006.201.21:04:37.84#ibcon#about to read 5, iclass 20, count 0 2006.201.21:04:37.84#ibcon#read 5, iclass 20, count 0 2006.201.21:04:37.84#ibcon#about to read 6, iclass 20, count 0 2006.201.21:04:37.84#ibcon#read 6, iclass 20, count 0 2006.201.21:04:37.84#ibcon#end of sib2, iclass 20, count 0 2006.201.21:04:37.84#ibcon#*mode == 0, iclass 20, count 0 2006.201.21:04:37.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.21:04:37.84#ibcon#[27=USB\r\n] 2006.201.21:04:37.84#ibcon#*before write, iclass 20, count 0 2006.201.21:04:37.84#ibcon#enter sib2, iclass 20, count 0 2006.201.21:04:37.84#ibcon#flushed, iclass 20, count 0 2006.201.21:04:37.84#ibcon#about to write, iclass 20, count 0 2006.201.21:04:37.84#ibcon#wrote, iclass 20, count 0 2006.201.21:04:37.84#ibcon#about to read 3, iclass 20, count 0 2006.201.21:04:37.87#ibcon#read 3, iclass 20, count 0 2006.201.21:04:37.87#ibcon#about to read 4, iclass 20, count 0 2006.201.21:04:37.87#ibcon#read 4, iclass 20, count 0 2006.201.21:04:37.87#ibcon#about to read 5, iclass 20, count 0 2006.201.21:04:37.87#ibcon#read 5, iclass 20, count 0 2006.201.21:04:37.87#ibcon#about to read 6, iclass 20, count 0 2006.201.21:04:37.87#ibcon#read 6, iclass 20, count 0 2006.201.21:04:37.87#ibcon#end of sib2, iclass 20, count 0 2006.201.21:04:37.87#ibcon#*after write, iclass 20, count 0 2006.201.21:04:37.87#ibcon#*before return 0, iclass 20, count 0 2006.201.21:04:37.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:04:37.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:04:37.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.21:04:37.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.21:04:37.87$vck44/vblo=2,634.99 2006.201.21:04:37.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.21:04:37.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.21:04:37.87#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:37.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:37.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:37.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:37.87#ibcon#enter wrdev, iclass 22, count 0 2006.201.21:04:37.87#ibcon#first serial, iclass 22, count 0 2006.201.21:04:37.87#ibcon#enter sib2, iclass 22, count 0 2006.201.21:04:37.87#ibcon#flushed, iclass 22, count 0 2006.201.21:04:37.87#ibcon#about to write, iclass 22, count 0 2006.201.21:04:37.87#ibcon#wrote, iclass 22, count 0 2006.201.21:04:37.87#ibcon#about to read 3, iclass 22, count 0 2006.201.21:04:37.89#ibcon#read 3, iclass 22, count 0 2006.201.21:04:37.89#ibcon#about to read 4, iclass 22, count 0 2006.201.21:04:37.89#ibcon#read 4, iclass 22, count 0 2006.201.21:04:37.89#ibcon#about to read 5, iclass 22, count 0 2006.201.21:04:37.89#ibcon#read 5, iclass 22, count 0 2006.201.21:04:37.89#ibcon#about to read 6, iclass 22, count 0 2006.201.21:04:37.89#ibcon#read 6, iclass 22, count 0 2006.201.21:04:37.89#ibcon#end of sib2, iclass 22, count 0 2006.201.21:04:37.89#ibcon#*mode == 0, iclass 22, count 0 2006.201.21:04:37.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.21:04:37.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.21:04:37.89#ibcon#*before write, iclass 22, count 0 2006.201.21:04:37.89#ibcon#enter sib2, iclass 22, count 0 2006.201.21:04:37.89#ibcon#flushed, iclass 22, count 0 2006.201.21:04:37.89#ibcon#about to write, iclass 22, count 0 2006.201.21:04:37.89#ibcon#wrote, iclass 22, count 0 2006.201.21:04:37.89#ibcon#about to read 3, iclass 22, count 0 2006.201.21:04:37.93#ibcon#read 3, iclass 22, count 0 2006.201.21:04:37.93#ibcon#about to read 4, iclass 22, count 0 2006.201.21:04:37.93#ibcon#read 4, iclass 22, count 0 2006.201.21:04:37.93#ibcon#about to read 5, iclass 22, count 0 2006.201.21:04:37.93#ibcon#read 5, iclass 22, count 0 2006.201.21:04:37.93#ibcon#about to read 6, iclass 22, count 0 2006.201.21:04:37.93#ibcon#read 6, iclass 22, count 0 2006.201.21:04:37.93#ibcon#end of sib2, iclass 22, count 0 2006.201.21:04:37.93#ibcon#*after write, iclass 22, count 0 2006.201.21:04:37.93#ibcon#*before return 0, iclass 22, count 0 2006.201.21:04:37.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:37.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:04:37.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.21:04:37.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.21:04:37.93$vck44/vb=2,5 2006.201.21:04:37.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.21:04:37.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.21:04:37.93#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:37.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:37.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:37.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:37.99#ibcon#enter wrdev, iclass 24, count 2 2006.201.21:04:37.99#ibcon#first serial, iclass 24, count 2 2006.201.21:04:37.99#ibcon#enter sib2, iclass 24, count 2 2006.201.21:04:37.99#ibcon#flushed, iclass 24, count 2 2006.201.21:04:37.99#ibcon#about to write, iclass 24, count 2 2006.201.21:04:37.99#ibcon#wrote, iclass 24, count 2 2006.201.21:04:37.99#ibcon#about to read 3, iclass 24, count 2 2006.201.21:04:38.01#ibcon#read 3, iclass 24, count 2 2006.201.21:04:38.01#ibcon#about to read 4, iclass 24, count 2 2006.201.21:04:38.01#ibcon#read 4, iclass 24, count 2 2006.201.21:04:38.01#ibcon#about to read 5, iclass 24, count 2 2006.201.21:04:38.01#ibcon#read 5, iclass 24, count 2 2006.201.21:04:38.01#ibcon#about to read 6, iclass 24, count 2 2006.201.21:04:38.01#ibcon#read 6, iclass 24, count 2 2006.201.21:04:38.01#ibcon#end of sib2, iclass 24, count 2 2006.201.21:04:38.01#ibcon#*mode == 0, iclass 24, count 2 2006.201.21:04:38.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.21:04:38.01#ibcon#[27=AT02-05\r\n] 2006.201.21:04:38.01#ibcon#*before write, iclass 24, count 2 2006.201.21:04:38.01#ibcon#enter sib2, iclass 24, count 2 2006.201.21:04:38.01#ibcon#flushed, iclass 24, count 2 2006.201.21:04:38.01#ibcon#about to write, iclass 24, count 2 2006.201.21:04:38.01#ibcon#wrote, iclass 24, count 2 2006.201.21:04:38.01#ibcon#about to read 3, iclass 24, count 2 2006.201.21:04:38.04#ibcon#read 3, iclass 24, count 2 2006.201.21:04:38.04#ibcon#about to read 4, iclass 24, count 2 2006.201.21:04:38.04#ibcon#read 4, iclass 24, count 2 2006.201.21:04:38.04#ibcon#about to read 5, iclass 24, count 2 2006.201.21:04:38.04#ibcon#read 5, iclass 24, count 2 2006.201.21:04:38.04#ibcon#about to read 6, iclass 24, count 2 2006.201.21:04:38.04#ibcon#read 6, iclass 24, count 2 2006.201.21:04:38.04#ibcon#end of sib2, iclass 24, count 2 2006.201.21:04:38.04#ibcon#*after write, iclass 24, count 2 2006.201.21:04:38.04#ibcon#*before return 0, iclass 24, count 2 2006.201.21:04:38.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:38.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:04:38.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.21:04:38.04#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:38.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:38.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:38.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:38.16#ibcon#enter wrdev, iclass 24, count 0 2006.201.21:04:38.16#ibcon#first serial, iclass 24, count 0 2006.201.21:04:38.16#ibcon#enter sib2, iclass 24, count 0 2006.201.21:04:38.16#ibcon#flushed, iclass 24, count 0 2006.201.21:04:38.16#ibcon#about to write, iclass 24, count 0 2006.201.21:04:38.16#ibcon#wrote, iclass 24, count 0 2006.201.21:04:38.16#ibcon#about to read 3, iclass 24, count 0 2006.201.21:04:38.18#ibcon#read 3, iclass 24, count 0 2006.201.21:04:38.18#ibcon#about to read 4, iclass 24, count 0 2006.201.21:04:38.18#ibcon#read 4, iclass 24, count 0 2006.201.21:04:38.18#ibcon#about to read 5, iclass 24, count 0 2006.201.21:04:38.18#ibcon#read 5, iclass 24, count 0 2006.201.21:04:38.18#ibcon#about to read 6, iclass 24, count 0 2006.201.21:04:38.18#ibcon#read 6, iclass 24, count 0 2006.201.21:04:38.18#ibcon#end of sib2, iclass 24, count 0 2006.201.21:04:38.18#ibcon#*mode == 0, iclass 24, count 0 2006.201.21:04:38.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.21:04:38.18#ibcon#[27=USB\r\n] 2006.201.21:04:38.18#ibcon#*before write, iclass 24, count 0 2006.201.21:04:38.18#ibcon#enter sib2, iclass 24, count 0 2006.201.21:04:38.18#ibcon#flushed, iclass 24, count 0 2006.201.21:04:38.18#ibcon#about to write, iclass 24, count 0 2006.201.21:04:38.18#ibcon#wrote, iclass 24, count 0 2006.201.21:04:38.18#ibcon#about to read 3, iclass 24, count 0 2006.201.21:04:38.21#ibcon#read 3, iclass 24, count 0 2006.201.21:04:38.21#ibcon#about to read 4, iclass 24, count 0 2006.201.21:04:38.21#ibcon#read 4, iclass 24, count 0 2006.201.21:04:38.21#ibcon#about to read 5, iclass 24, count 0 2006.201.21:04:38.21#ibcon#read 5, iclass 24, count 0 2006.201.21:04:38.21#ibcon#about to read 6, iclass 24, count 0 2006.201.21:04:38.21#ibcon#read 6, iclass 24, count 0 2006.201.21:04:38.21#ibcon#end of sib2, iclass 24, count 0 2006.201.21:04:38.21#ibcon#*after write, iclass 24, count 0 2006.201.21:04:38.21#ibcon#*before return 0, iclass 24, count 0 2006.201.21:04:38.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:38.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:04:38.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.21:04:38.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.21:04:38.21$vck44/vblo=3,649.99 2006.201.21:04:38.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.21:04:38.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.21:04:38.21#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:38.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:38.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:38.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:38.21#ibcon#enter wrdev, iclass 26, count 0 2006.201.21:04:38.21#ibcon#first serial, iclass 26, count 0 2006.201.21:04:38.21#ibcon#enter sib2, iclass 26, count 0 2006.201.21:04:38.21#ibcon#flushed, iclass 26, count 0 2006.201.21:04:38.21#ibcon#about to write, iclass 26, count 0 2006.201.21:04:38.21#ibcon#wrote, iclass 26, count 0 2006.201.21:04:38.21#ibcon#about to read 3, iclass 26, count 0 2006.201.21:04:38.23#ibcon#read 3, iclass 26, count 0 2006.201.21:04:38.23#ibcon#about to read 4, iclass 26, count 0 2006.201.21:04:38.23#ibcon#read 4, iclass 26, count 0 2006.201.21:04:38.23#ibcon#about to read 5, iclass 26, count 0 2006.201.21:04:38.23#ibcon#read 5, iclass 26, count 0 2006.201.21:04:38.23#ibcon#about to read 6, iclass 26, count 0 2006.201.21:04:38.23#ibcon#read 6, iclass 26, count 0 2006.201.21:04:38.23#ibcon#end of sib2, iclass 26, count 0 2006.201.21:04:38.23#ibcon#*mode == 0, iclass 26, count 0 2006.201.21:04:38.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.21:04:38.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.21:04:38.23#ibcon#*before write, iclass 26, count 0 2006.201.21:04:38.23#ibcon#enter sib2, iclass 26, count 0 2006.201.21:04:38.23#ibcon#flushed, iclass 26, count 0 2006.201.21:04:38.23#ibcon#about to write, iclass 26, count 0 2006.201.21:04:38.23#ibcon#wrote, iclass 26, count 0 2006.201.21:04:38.23#ibcon#about to read 3, iclass 26, count 0 2006.201.21:04:38.27#ibcon#read 3, iclass 26, count 0 2006.201.21:04:38.27#ibcon#about to read 4, iclass 26, count 0 2006.201.21:04:38.27#ibcon#read 4, iclass 26, count 0 2006.201.21:04:38.27#ibcon#about to read 5, iclass 26, count 0 2006.201.21:04:38.27#ibcon#read 5, iclass 26, count 0 2006.201.21:04:38.27#ibcon#about to read 6, iclass 26, count 0 2006.201.21:04:38.27#ibcon#read 6, iclass 26, count 0 2006.201.21:04:38.27#ibcon#end of sib2, iclass 26, count 0 2006.201.21:04:38.27#ibcon#*after write, iclass 26, count 0 2006.201.21:04:38.27#ibcon#*before return 0, iclass 26, count 0 2006.201.21:04:38.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:38.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:04:38.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.21:04:38.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.21:04:38.27$vck44/vb=3,4 2006.201.21:04:38.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.21:04:38.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.21:04:38.27#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:38.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:38.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:38.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:38.33#ibcon#enter wrdev, iclass 28, count 2 2006.201.21:04:38.33#ibcon#first serial, iclass 28, count 2 2006.201.21:04:38.33#ibcon#enter sib2, iclass 28, count 2 2006.201.21:04:38.33#ibcon#flushed, iclass 28, count 2 2006.201.21:04:38.33#ibcon#about to write, iclass 28, count 2 2006.201.21:04:38.33#ibcon#wrote, iclass 28, count 2 2006.201.21:04:38.33#ibcon#about to read 3, iclass 28, count 2 2006.201.21:04:38.35#ibcon#read 3, iclass 28, count 2 2006.201.21:04:38.35#ibcon#about to read 4, iclass 28, count 2 2006.201.21:04:38.35#ibcon#read 4, iclass 28, count 2 2006.201.21:04:38.35#ibcon#about to read 5, iclass 28, count 2 2006.201.21:04:38.35#ibcon#read 5, iclass 28, count 2 2006.201.21:04:38.35#ibcon#about to read 6, iclass 28, count 2 2006.201.21:04:38.35#ibcon#read 6, iclass 28, count 2 2006.201.21:04:38.35#ibcon#end of sib2, iclass 28, count 2 2006.201.21:04:38.35#ibcon#*mode == 0, iclass 28, count 2 2006.201.21:04:38.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.21:04:38.35#ibcon#[27=AT03-04\r\n] 2006.201.21:04:38.35#ibcon#*before write, iclass 28, count 2 2006.201.21:04:38.35#ibcon#enter sib2, iclass 28, count 2 2006.201.21:04:38.35#ibcon#flushed, iclass 28, count 2 2006.201.21:04:38.35#ibcon#about to write, iclass 28, count 2 2006.201.21:04:38.35#ibcon#wrote, iclass 28, count 2 2006.201.21:04:38.35#ibcon#about to read 3, iclass 28, count 2 2006.201.21:04:38.38#ibcon#read 3, iclass 28, count 2 2006.201.21:04:38.38#ibcon#about to read 4, iclass 28, count 2 2006.201.21:04:38.38#ibcon#read 4, iclass 28, count 2 2006.201.21:04:38.38#ibcon#about to read 5, iclass 28, count 2 2006.201.21:04:38.38#ibcon#read 5, iclass 28, count 2 2006.201.21:04:38.38#ibcon#about to read 6, iclass 28, count 2 2006.201.21:04:38.38#ibcon#read 6, iclass 28, count 2 2006.201.21:04:38.38#ibcon#end of sib2, iclass 28, count 2 2006.201.21:04:38.38#ibcon#*after write, iclass 28, count 2 2006.201.21:04:38.38#ibcon#*before return 0, iclass 28, count 2 2006.201.21:04:38.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:38.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:04:38.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.21:04:38.38#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:38.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:38.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:38.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:38.50#ibcon#enter wrdev, iclass 28, count 0 2006.201.21:04:38.50#ibcon#first serial, iclass 28, count 0 2006.201.21:04:38.50#ibcon#enter sib2, iclass 28, count 0 2006.201.21:04:38.50#ibcon#flushed, iclass 28, count 0 2006.201.21:04:38.50#ibcon#about to write, iclass 28, count 0 2006.201.21:04:38.50#ibcon#wrote, iclass 28, count 0 2006.201.21:04:38.50#ibcon#about to read 3, iclass 28, count 0 2006.201.21:04:38.52#ibcon#read 3, iclass 28, count 0 2006.201.21:04:38.52#ibcon#about to read 4, iclass 28, count 0 2006.201.21:04:38.52#ibcon#read 4, iclass 28, count 0 2006.201.21:04:38.52#ibcon#about to read 5, iclass 28, count 0 2006.201.21:04:38.52#ibcon#read 5, iclass 28, count 0 2006.201.21:04:38.52#ibcon#about to read 6, iclass 28, count 0 2006.201.21:04:38.52#ibcon#read 6, iclass 28, count 0 2006.201.21:04:38.52#ibcon#end of sib2, iclass 28, count 0 2006.201.21:04:38.52#ibcon#*mode == 0, iclass 28, count 0 2006.201.21:04:38.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.21:04:38.52#ibcon#[27=USB\r\n] 2006.201.21:04:38.52#ibcon#*before write, iclass 28, count 0 2006.201.21:04:38.52#ibcon#enter sib2, iclass 28, count 0 2006.201.21:04:38.52#ibcon#flushed, iclass 28, count 0 2006.201.21:04:38.52#ibcon#about to write, iclass 28, count 0 2006.201.21:04:38.52#ibcon#wrote, iclass 28, count 0 2006.201.21:04:38.52#ibcon#about to read 3, iclass 28, count 0 2006.201.21:04:38.55#ibcon#read 3, iclass 28, count 0 2006.201.21:04:38.55#ibcon#about to read 4, iclass 28, count 0 2006.201.21:04:38.55#ibcon#read 4, iclass 28, count 0 2006.201.21:04:38.55#ibcon#about to read 5, iclass 28, count 0 2006.201.21:04:38.55#ibcon#read 5, iclass 28, count 0 2006.201.21:04:38.55#ibcon#about to read 6, iclass 28, count 0 2006.201.21:04:38.55#ibcon#read 6, iclass 28, count 0 2006.201.21:04:38.55#ibcon#end of sib2, iclass 28, count 0 2006.201.21:04:38.55#ibcon#*after write, iclass 28, count 0 2006.201.21:04:38.55#ibcon#*before return 0, iclass 28, count 0 2006.201.21:04:38.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:38.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:04:38.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.21:04:38.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.21:04:38.55$vck44/vblo=4,679.99 2006.201.21:04:38.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.21:04:38.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.21:04:38.55#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:38.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:38.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:38.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:38.55#ibcon#enter wrdev, iclass 30, count 0 2006.201.21:04:38.55#ibcon#first serial, iclass 30, count 0 2006.201.21:04:38.55#ibcon#enter sib2, iclass 30, count 0 2006.201.21:04:38.55#ibcon#flushed, iclass 30, count 0 2006.201.21:04:38.55#ibcon#about to write, iclass 30, count 0 2006.201.21:04:38.55#ibcon#wrote, iclass 30, count 0 2006.201.21:04:38.55#ibcon#about to read 3, iclass 30, count 0 2006.201.21:04:38.57#ibcon#read 3, iclass 30, count 0 2006.201.21:04:38.57#ibcon#about to read 4, iclass 30, count 0 2006.201.21:04:38.57#ibcon#read 4, iclass 30, count 0 2006.201.21:04:38.57#ibcon#about to read 5, iclass 30, count 0 2006.201.21:04:38.57#ibcon#read 5, iclass 30, count 0 2006.201.21:04:38.57#ibcon#about to read 6, iclass 30, count 0 2006.201.21:04:38.57#ibcon#read 6, iclass 30, count 0 2006.201.21:04:38.57#ibcon#end of sib2, iclass 30, count 0 2006.201.21:04:38.57#ibcon#*mode == 0, iclass 30, count 0 2006.201.21:04:38.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.21:04:38.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.21:04:38.57#ibcon#*before write, iclass 30, count 0 2006.201.21:04:38.57#ibcon#enter sib2, iclass 30, count 0 2006.201.21:04:38.57#ibcon#flushed, iclass 30, count 0 2006.201.21:04:38.57#ibcon#about to write, iclass 30, count 0 2006.201.21:04:38.57#ibcon#wrote, iclass 30, count 0 2006.201.21:04:38.57#ibcon#about to read 3, iclass 30, count 0 2006.201.21:04:38.61#ibcon#read 3, iclass 30, count 0 2006.201.21:04:38.61#ibcon#about to read 4, iclass 30, count 0 2006.201.21:04:38.61#ibcon#read 4, iclass 30, count 0 2006.201.21:04:38.61#ibcon#about to read 5, iclass 30, count 0 2006.201.21:04:38.61#ibcon#read 5, iclass 30, count 0 2006.201.21:04:38.61#ibcon#about to read 6, iclass 30, count 0 2006.201.21:04:38.61#ibcon#read 6, iclass 30, count 0 2006.201.21:04:38.61#ibcon#end of sib2, iclass 30, count 0 2006.201.21:04:38.61#ibcon#*after write, iclass 30, count 0 2006.201.21:04:38.61#ibcon#*before return 0, iclass 30, count 0 2006.201.21:04:38.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:38.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:04:38.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.21:04:38.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.21:04:38.61$vck44/vb=4,5 2006.201.21:04:38.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.21:04:38.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.21:04:38.61#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:38.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:38.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:38.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:38.67#ibcon#enter wrdev, iclass 32, count 2 2006.201.21:04:38.67#ibcon#first serial, iclass 32, count 2 2006.201.21:04:38.67#ibcon#enter sib2, iclass 32, count 2 2006.201.21:04:38.67#ibcon#flushed, iclass 32, count 2 2006.201.21:04:38.67#ibcon#about to write, iclass 32, count 2 2006.201.21:04:38.67#ibcon#wrote, iclass 32, count 2 2006.201.21:04:38.67#ibcon#about to read 3, iclass 32, count 2 2006.201.21:04:38.69#ibcon#read 3, iclass 32, count 2 2006.201.21:04:38.69#ibcon#about to read 4, iclass 32, count 2 2006.201.21:04:38.69#ibcon#read 4, iclass 32, count 2 2006.201.21:04:38.69#ibcon#about to read 5, iclass 32, count 2 2006.201.21:04:38.69#ibcon#read 5, iclass 32, count 2 2006.201.21:04:38.69#ibcon#about to read 6, iclass 32, count 2 2006.201.21:04:38.69#ibcon#read 6, iclass 32, count 2 2006.201.21:04:38.69#ibcon#end of sib2, iclass 32, count 2 2006.201.21:04:38.69#ibcon#*mode == 0, iclass 32, count 2 2006.201.21:04:38.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.21:04:38.69#ibcon#[27=AT04-05\r\n] 2006.201.21:04:38.69#ibcon#*before write, iclass 32, count 2 2006.201.21:04:38.69#ibcon#enter sib2, iclass 32, count 2 2006.201.21:04:38.69#ibcon#flushed, iclass 32, count 2 2006.201.21:04:38.69#ibcon#about to write, iclass 32, count 2 2006.201.21:04:38.69#ibcon#wrote, iclass 32, count 2 2006.201.21:04:38.69#ibcon#about to read 3, iclass 32, count 2 2006.201.21:04:38.72#ibcon#read 3, iclass 32, count 2 2006.201.21:04:38.72#ibcon#about to read 4, iclass 32, count 2 2006.201.21:04:38.72#ibcon#read 4, iclass 32, count 2 2006.201.21:04:38.72#ibcon#about to read 5, iclass 32, count 2 2006.201.21:04:38.72#ibcon#read 5, iclass 32, count 2 2006.201.21:04:38.72#ibcon#about to read 6, iclass 32, count 2 2006.201.21:04:38.72#ibcon#read 6, iclass 32, count 2 2006.201.21:04:38.72#ibcon#end of sib2, iclass 32, count 2 2006.201.21:04:38.72#ibcon#*after write, iclass 32, count 2 2006.201.21:04:38.72#ibcon#*before return 0, iclass 32, count 2 2006.201.21:04:38.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:38.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:04:38.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.21:04:38.72#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:38.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:38.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:38.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:38.84#ibcon#enter wrdev, iclass 32, count 0 2006.201.21:04:38.84#ibcon#first serial, iclass 32, count 0 2006.201.21:04:38.84#ibcon#enter sib2, iclass 32, count 0 2006.201.21:04:38.84#ibcon#flushed, iclass 32, count 0 2006.201.21:04:38.84#ibcon#about to write, iclass 32, count 0 2006.201.21:04:38.84#ibcon#wrote, iclass 32, count 0 2006.201.21:04:38.84#ibcon#about to read 3, iclass 32, count 0 2006.201.21:04:38.86#ibcon#read 3, iclass 32, count 0 2006.201.21:04:38.86#ibcon#about to read 4, iclass 32, count 0 2006.201.21:04:38.86#ibcon#read 4, iclass 32, count 0 2006.201.21:04:38.86#ibcon#about to read 5, iclass 32, count 0 2006.201.21:04:38.86#ibcon#read 5, iclass 32, count 0 2006.201.21:04:38.86#ibcon#about to read 6, iclass 32, count 0 2006.201.21:04:38.86#ibcon#read 6, iclass 32, count 0 2006.201.21:04:38.86#ibcon#end of sib2, iclass 32, count 0 2006.201.21:04:38.86#ibcon#*mode == 0, iclass 32, count 0 2006.201.21:04:38.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.21:04:38.86#ibcon#[27=USB\r\n] 2006.201.21:04:38.86#ibcon#*before write, iclass 32, count 0 2006.201.21:04:38.86#ibcon#enter sib2, iclass 32, count 0 2006.201.21:04:38.86#ibcon#flushed, iclass 32, count 0 2006.201.21:04:38.86#ibcon#about to write, iclass 32, count 0 2006.201.21:04:38.86#ibcon#wrote, iclass 32, count 0 2006.201.21:04:38.86#ibcon#about to read 3, iclass 32, count 0 2006.201.21:04:38.89#ibcon#read 3, iclass 32, count 0 2006.201.21:04:38.89#ibcon#about to read 4, iclass 32, count 0 2006.201.21:04:38.89#ibcon#read 4, iclass 32, count 0 2006.201.21:04:38.89#ibcon#about to read 5, iclass 32, count 0 2006.201.21:04:38.89#ibcon#read 5, iclass 32, count 0 2006.201.21:04:38.89#ibcon#about to read 6, iclass 32, count 0 2006.201.21:04:38.89#ibcon#read 6, iclass 32, count 0 2006.201.21:04:38.89#ibcon#end of sib2, iclass 32, count 0 2006.201.21:04:38.89#ibcon#*after write, iclass 32, count 0 2006.201.21:04:38.89#ibcon#*before return 0, iclass 32, count 0 2006.201.21:04:38.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:38.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:04:38.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.21:04:38.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.21:04:38.89$vck44/vblo=5,709.99 2006.201.21:04:38.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.21:04:38.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.21:04:38.89#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:38.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:38.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:38.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:38.89#ibcon#enter wrdev, iclass 34, count 0 2006.201.21:04:38.89#ibcon#first serial, iclass 34, count 0 2006.201.21:04:38.89#ibcon#enter sib2, iclass 34, count 0 2006.201.21:04:38.89#ibcon#flushed, iclass 34, count 0 2006.201.21:04:38.89#ibcon#about to write, iclass 34, count 0 2006.201.21:04:38.89#ibcon#wrote, iclass 34, count 0 2006.201.21:04:38.89#ibcon#about to read 3, iclass 34, count 0 2006.201.21:04:38.91#ibcon#read 3, iclass 34, count 0 2006.201.21:04:38.91#ibcon#about to read 4, iclass 34, count 0 2006.201.21:04:38.91#ibcon#read 4, iclass 34, count 0 2006.201.21:04:38.91#ibcon#about to read 5, iclass 34, count 0 2006.201.21:04:38.91#ibcon#read 5, iclass 34, count 0 2006.201.21:04:38.91#ibcon#about to read 6, iclass 34, count 0 2006.201.21:04:38.91#ibcon#read 6, iclass 34, count 0 2006.201.21:04:38.91#ibcon#end of sib2, iclass 34, count 0 2006.201.21:04:38.91#ibcon#*mode == 0, iclass 34, count 0 2006.201.21:04:38.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.21:04:38.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.21:04:38.91#ibcon#*before write, iclass 34, count 0 2006.201.21:04:38.91#ibcon#enter sib2, iclass 34, count 0 2006.201.21:04:38.91#ibcon#flushed, iclass 34, count 0 2006.201.21:04:38.91#ibcon#about to write, iclass 34, count 0 2006.201.21:04:38.91#ibcon#wrote, iclass 34, count 0 2006.201.21:04:38.91#ibcon#about to read 3, iclass 34, count 0 2006.201.21:04:38.95#ibcon#read 3, iclass 34, count 0 2006.201.21:04:38.95#ibcon#about to read 4, iclass 34, count 0 2006.201.21:04:38.95#ibcon#read 4, iclass 34, count 0 2006.201.21:04:38.95#ibcon#about to read 5, iclass 34, count 0 2006.201.21:04:38.95#ibcon#read 5, iclass 34, count 0 2006.201.21:04:38.95#ibcon#about to read 6, iclass 34, count 0 2006.201.21:04:38.95#ibcon#read 6, iclass 34, count 0 2006.201.21:04:38.95#ibcon#end of sib2, iclass 34, count 0 2006.201.21:04:38.95#ibcon#*after write, iclass 34, count 0 2006.201.21:04:38.95#ibcon#*before return 0, iclass 34, count 0 2006.201.21:04:38.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:38.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:04:38.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.21:04:38.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.21:04:38.95$vck44/vb=5,4 2006.201.21:04:38.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.21:04:38.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.21:04:38.95#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:38.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:39.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:39.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:39.01#ibcon#enter wrdev, iclass 36, count 2 2006.201.21:04:39.01#ibcon#first serial, iclass 36, count 2 2006.201.21:04:39.01#ibcon#enter sib2, iclass 36, count 2 2006.201.21:04:39.01#ibcon#flushed, iclass 36, count 2 2006.201.21:04:39.01#ibcon#about to write, iclass 36, count 2 2006.201.21:04:39.01#ibcon#wrote, iclass 36, count 2 2006.201.21:04:39.01#ibcon#about to read 3, iclass 36, count 2 2006.201.21:04:39.03#ibcon#read 3, iclass 36, count 2 2006.201.21:04:39.03#ibcon#about to read 4, iclass 36, count 2 2006.201.21:04:39.03#ibcon#read 4, iclass 36, count 2 2006.201.21:04:39.03#ibcon#about to read 5, iclass 36, count 2 2006.201.21:04:39.03#ibcon#read 5, iclass 36, count 2 2006.201.21:04:39.03#ibcon#about to read 6, iclass 36, count 2 2006.201.21:04:39.03#ibcon#read 6, iclass 36, count 2 2006.201.21:04:39.03#ibcon#end of sib2, iclass 36, count 2 2006.201.21:04:39.03#ibcon#*mode == 0, iclass 36, count 2 2006.201.21:04:39.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.21:04:39.03#ibcon#[27=AT05-04\r\n] 2006.201.21:04:39.03#ibcon#*before write, iclass 36, count 2 2006.201.21:04:39.03#ibcon#enter sib2, iclass 36, count 2 2006.201.21:04:39.03#ibcon#flushed, iclass 36, count 2 2006.201.21:04:39.03#ibcon#about to write, iclass 36, count 2 2006.201.21:04:39.03#ibcon#wrote, iclass 36, count 2 2006.201.21:04:39.03#ibcon#about to read 3, iclass 36, count 2 2006.201.21:04:39.06#ibcon#read 3, iclass 36, count 2 2006.201.21:04:39.06#ibcon#about to read 4, iclass 36, count 2 2006.201.21:04:39.06#ibcon#read 4, iclass 36, count 2 2006.201.21:04:39.06#ibcon#about to read 5, iclass 36, count 2 2006.201.21:04:39.06#ibcon#read 5, iclass 36, count 2 2006.201.21:04:39.06#ibcon#about to read 6, iclass 36, count 2 2006.201.21:04:39.06#ibcon#read 6, iclass 36, count 2 2006.201.21:04:39.06#ibcon#end of sib2, iclass 36, count 2 2006.201.21:04:39.06#ibcon#*after write, iclass 36, count 2 2006.201.21:04:39.06#ibcon#*before return 0, iclass 36, count 2 2006.201.21:04:39.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:39.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:04:39.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.21:04:39.06#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:39.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:39.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:39.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:39.18#ibcon#enter wrdev, iclass 36, count 0 2006.201.21:04:39.18#ibcon#first serial, iclass 36, count 0 2006.201.21:04:39.18#ibcon#enter sib2, iclass 36, count 0 2006.201.21:04:39.18#ibcon#flushed, iclass 36, count 0 2006.201.21:04:39.18#ibcon#about to write, iclass 36, count 0 2006.201.21:04:39.18#ibcon#wrote, iclass 36, count 0 2006.201.21:04:39.18#ibcon#about to read 3, iclass 36, count 0 2006.201.21:04:39.20#ibcon#read 3, iclass 36, count 0 2006.201.21:04:39.20#ibcon#about to read 4, iclass 36, count 0 2006.201.21:04:39.20#ibcon#read 4, iclass 36, count 0 2006.201.21:04:39.20#ibcon#about to read 5, iclass 36, count 0 2006.201.21:04:39.20#ibcon#read 5, iclass 36, count 0 2006.201.21:04:39.20#ibcon#about to read 6, iclass 36, count 0 2006.201.21:04:39.20#ibcon#read 6, iclass 36, count 0 2006.201.21:04:39.20#ibcon#end of sib2, iclass 36, count 0 2006.201.21:04:39.20#ibcon#*mode == 0, iclass 36, count 0 2006.201.21:04:39.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.21:04:39.20#ibcon#[27=USB\r\n] 2006.201.21:04:39.20#ibcon#*before write, iclass 36, count 0 2006.201.21:04:39.20#ibcon#enter sib2, iclass 36, count 0 2006.201.21:04:39.20#ibcon#flushed, iclass 36, count 0 2006.201.21:04:39.20#ibcon#about to write, iclass 36, count 0 2006.201.21:04:39.20#ibcon#wrote, iclass 36, count 0 2006.201.21:04:39.20#ibcon#about to read 3, iclass 36, count 0 2006.201.21:04:39.23#ibcon#read 3, iclass 36, count 0 2006.201.21:04:39.23#ibcon#about to read 4, iclass 36, count 0 2006.201.21:04:39.23#ibcon#read 4, iclass 36, count 0 2006.201.21:04:39.23#ibcon#about to read 5, iclass 36, count 0 2006.201.21:04:39.23#ibcon#read 5, iclass 36, count 0 2006.201.21:04:39.23#ibcon#about to read 6, iclass 36, count 0 2006.201.21:04:39.23#ibcon#read 6, iclass 36, count 0 2006.201.21:04:39.23#ibcon#end of sib2, iclass 36, count 0 2006.201.21:04:39.23#ibcon#*after write, iclass 36, count 0 2006.201.21:04:39.23#ibcon#*before return 0, iclass 36, count 0 2006.201.21:04:39.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:39.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:04:39.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.21:04:39.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.21:04:39.23$vck44/vblo=6,719.99 2006.201.21:04:39.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.21:04:39.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.21:04:39.23#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:39.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:39.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:39.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:39.23#ibcon#enter wrdev, iclass 38, count 0 2006.201.21:04:39.23#ibcon#first serial, iclass 38, count 0 2006.201.21:04:39.23#ibcon#enter sib2, iclass 38, count 0 2006.201.21:04:39.23#ibcon#flushed, iclass 38, count 0 2006.201.21:04:39.23#ibcon#about to write, iclass 38, count 0 2006.201.21:04:39.23#ibcon#wrote, iclass 38, count 0 2006.201.21:04:39.23#ibcon#about to read 3, iclass 38, count 0 2006.201.21:04:39.25#ibcon#read 3, iclass 38, count 0 2006.201.21:04:39.25#ibcon#about to read 4, iclass 38, count 0 2006.201.21:04:39.25#ibcon#read 4, iclass 38, count 0 2006.201.21:04:39.25#ibcon#about to read 5, iclass 38, count 0 2006.201.21:04:39.25#ibcon#read 5, iclass 38, count 0 2006.201.21:04:39.25#ibcon#about to read 6, iclass 38, count 0 2006.201.21:04:39.25#ibcon#read 6, iclass 38, count 0 2006.201.21:04:39.25#ibcon#end of sib2, iclass 38, count 0 2006.201.21:04:39.25#ibcon#*mode == 0, iclass 38, count 0 2006.201.21:04:39.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.21:04:39.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.21:04:39.25#ibcon#*before write, iclass 38, count 0 2006.201.21:04:39.25#ibcon#enter sib2, iclass 38, count 0 2006.201.21:04:39.25#ibcon#flushed, iclass 38, count 0 2006.201.21:04:39.25#ibcon#about to write, iclass 38, count 0 2006.201.21:04:39.25#ibcon#wrote, iclass 38, count 0 2006.201.21:04:39.25#ibcon#about to read 3, iclass 38, count 0 2006.201.21:04:39.29#ibcon#read 3, iclass 38, count 0 2006.201.21:04:39.29#ibcon#about to read 4, iclass 38, count 0 2006.201.21:04:39.29#ibcon#read 4, iclass 38, count 0 2006.201.21:04:39.29#ibcon#about to read 5, iclass 38, count 0 2006.201.21:04:39.29#ibcon#read 5, iclass 38, count 0 2006.201.21:04:39.29#ibcon#about to read 6, iclass 38, count 0 2006.201.21:04:39.29#ibcon#read 6, iclass 38, count 0 2006.201.21:04:39.29#ibcon#end of sib2, iclass 38, count 0 2006.201.21:04:39.29#ibcon#*after write, iclass 38, count 0 2006.201.21:04:39.29#ibcon#*before return 0, iclass 38, count 0 2006.201.21:04:39.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:39.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:04:39.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.21:04:39.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.21:04:39.29$vck44/vb=6,4 2006.201.21:04:39.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.21:04:39.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.21:04:39.29#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:39.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:39.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:39.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:39.35#ibcon#enter wrdev, iclass 40, count 2 2006.201.21:04:39.35#ibcon#first serial, iclass 40, count 2 2006.201.21:04:39.35#ibcon#enter sib2, iclass 40, count 2 2006.201.21:04:39.35#ibcon#flushed, iclass 40, count 2 2006.201.21:04:39.35#ibcon#about to write, iclass 40, count 2 2006.201.21:04:39.35#ibcon#wrote, iclass 40, count 2 2006.201.21:04:39.35#ibcon#about to read 3, iclass 40, count 2 2006.201.21:04:39.37#ibcon#read 3, iclass 40, count 2 2006.201.21:04:39.37#ibcon#about to read 4, iclass 40, count 2 2006.201.21:04:39.37#ibcon#read 4, iclass 40, count 2 2006.201.21:04:39.37#ibcon#about to read 5, iclass 40, count 2 2006.201.21:04:39.37#ibcon#read 5, iclass 40, count 2 2006.201.21:04:39.37#ibcon#about to read 6, iclass 40, count 2 2006.201.21:04:39.37#ibcon#read 6, iclass 40, count 2 2006.201.21:04:39.37#ibcon#end of sib2, iclass 40, count 2 2006.201.21:04:39.37#ibcon#*mode == 0, iclass 40, count 2 2006.201.21:04:39.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.21:04:39.37#ibcon#[27=AT06-04\r\n] 2006.201.21:04:39.37#ibcon#*before write, iclass 40, count 2 2006.201.21:04:39.37#ibcon#enter sib2, iclass 40, count 2 2006.201.21:04:39.37#ibcon#flushed, iclass 40, count 2 2006.201.21:04:39.37#ibcon#about to write, iclass 40, count 2 2006.201.21:04:39.37#ibcon#wrote, iclass 40, count 2 2006.201.21:04:39.37#ibcon#about to read 3, iclass 40, count 2 2006.201.21:04:39.40#ibcon#read 3, iclass 40, count 2 2006.201.21:04:39.40#ibcon#about to read 4, iclass 40, count 2 2006.201.21:04:39.40#ibcon#read 4, iclass 40, count 2 2006.201.21:04:39.40#ibcon#about to read 5, iclass 40, count 2 2006.201.21:04:39.40#ibcon#read 5, iclass 40, count 2 2006.201.21:04:39.40#ibcon#about to read 6, iclass 40, count 2 2006.201.21:04:39.40#ibcon#read 6, iclass 40, count 2 2006.201.21:04:39.40#ibcon#end of sib2, iclass 40, count 2 2006.201.21:04:39.40#ibcon#*after write, iclass 40, count 2 2006.201.21:04:39.40#ibcon#*before return 0, iclass 40, count 2 2006.201.21:04:39.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:39.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:04:39.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.21:04:39.40#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:39.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:39.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:39.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:39.52#ibcon#enter wrdev, iclass 40, count 0 2006.201.21:04:39.52#ibcon#first serial, iclass 40, count 0 2006.201.21:04:39.52#ibcon#enter sib2, iclass 40, count 0 2006.201.21:04:39.52#ibcon#flushed, iclass 40, count 0 2006.201.21:04:39.52#ibcon#about to write, iclass 40, count 0 2006.201.21:04:39.52#ibcon#wrote, iclass 40, count 0 2006.201.21:04:39.52#ibcon#about to read 3, iclass 40, count 0 2006.201.21:04:39.54#ibcon#read 3, iclass 40, count 0 2006.201.21:04:39.54#ibcon#about to read 4, iclass 40, count 0 2006.201.21:04:39.54#ibcon#read 4, iclass 40, count 0 2006.201.21:04:39.54#ibcon#about to read 5, iclass 40, count 0 2006.201.21:04:39.54#ibcon#read 5, iclass 40, count 0 2006.201.21:04:39.54#ibcon#about to read 6, iclass 40, count 0 2006.201.21:04:39.54#ibcon#read 6, iclass 40, count 0 2006.201.21:04:39.54#ibcon#end of sib2, iclass 40, count 0 2006.201.21:04:39.54#ibcon#*mode == 0, iclass 40, count 0 2006.201.21:04:39.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.21:04:39.54#ibcon#[27=USB\r\n] 2006.201.21:04:39.54#ibcon#*before write, iclass 40, count 0 2006.201.21:04:39.54#ibcon#enter sib2, iclass 40, count 0 2006.201.21:04:39.54#ibcon#flushed, iclass 40, count 0 2006.201.21:04:39.54#ibcon#about to write, iclass 40, count 0 2006.201.21:04:39.54#ibcon#wrote, iclass 40, count 0 2006.201.21:04:39.54#ibcon#about to read 3, iclass 40, count 0 2006.201.21:04:39.57#ibcon#read 3, iclass 40, count 0 2006.201.21:04:39.57#ibcon#about to read 4, iclass 40, count 0 2006.201.21:04:39.57#ibcon#read 4, iclass 40, count 0 2006.201.21:04:39.57#ibcon#about to read 5, iclass 40, count 0 2006.201.21:04:39.57#ibcon#read 5, iclass 40, count 0 2006.201.21:04:39.57#ibcon#about to read 6, iclass 40, count 0 2006.201.21:04:39.57#ibcon#read 6, iclass 40, count 0 2006.201.21:04:39.57#ibcon#end of sib2, iclass 40, count 0 2006.201.21:04:39.57#ibcon#*after write, iclass 40, count 0 2006.201.21:04:39.57#ibcon#*before return 0, iclass 40, count 0 2006.201.21:04:39.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:39.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:04:39.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.21:04:39.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.21:04:39.57$vck44/vblo=7,734.99 2006.201.21:04:39.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.21:04:39.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.21:04:39.57#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:39.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:39.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:39.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:39.57#ibcon#enter wrdev, iclass 4, count 0 2006.201.21:04:39.57#ibcon#first serial, iclass 4, count 0 2006.201.21:04:39.57#ibcon#enter sib2, iclass 4, count 0 2006.201.21:04:39.57#ibcon#flushed, iclass 4, count 0 2006.201.21:04:39.57#ibcon#about to write, iclass 4, count 0 2006.201.21:04:39.57#ibcon#wrote, iclass 4, count 0 2006.201.21:04:39.57#ibcon#about to read 3, iclass 4, count 0 2006.201.21:04:39.59#ibcon#read 3, iclass 4, count 0 2006.201.21:04:39.59#ibcon#about to read 4, iclass 4, count 0 2006.201.21:04:39.59#ibcon#read 4, iclass 4, count 0 2006.201.21:04:39.59#ibcon#about to read 5, iclass 4, count 0 2006.201.21:04:39.59#ibcon#read 5, iclass 4, count 0 2006.201.21:04:39.59#ibcon#about to read 6, iclass 4, count 0 2006.201.21:04:39.59#ibcon#read 6, iclass 4, count 0 2006.201.21:04:39.59#ibcon#end of sib2, iclass 4, count 0 2006.201.21:04:39.59#ibcon#*mode == 0, iclass 4, count 0 2006.201.21:04:39.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.21:04:39.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.21:04:39.59#ibcon#*before write, iclass 4, count 0 2006.201.21:04:39.59#ibcon#enter sib2, iclass 4, count 0 2006.201.21:04:39.59#ibcon#flushed, iclass 4, count 0 2006.201.21:04:39.59#ibcon#about to write, iclass 4, count 0 2006.201.21:04:39.59#ibcon#wrote, iclass 4, count 0 2006.201.21:04:39.59#ibcon#about to read 3, iclass 4, count 0 2006.201.21:04:39.63#ibcon#read 3, iclass 4, count 0 2006.201.21:04:39.63#ibcon#about to read 4, iclass 4, count 0 2006.201.21:04:39.63#ibcon#read 4, iclass 4, count 0 2006.201.21:04:39.63#ibcon#about to read 5, iclass 4, count 0 2006.201.21:04:39.63#ibcon#read 5, iclass 4, count 0 2006.201.21:04:39.63#ibcon#about to read 6, iclass 4, count 0 2006.201.21:04:39.63#ibcon#read 6, iclass 4, count 0 2006.201.21:04:39.63#ibcon#end of sib2, iclass 4, count 0 2006.201.21:04:39.63#ibcon#*after write, iclass 4, count 0 2006.201.21:04:39.63#ibcon#*before return 0, iclass 4, count 0 2006.201.21:04:39.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:39.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:04:39.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.21:04:39.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.21:04:39.63$vck44/vb=7,4 2006.201.21:04:39.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.21:04:39.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.21:04:39.63#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:39.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:39.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:39.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:39.69#ibcon#enter wrdev, iclass 6, count 2 2006.201.21:04:39.69#ibcon#first serial, iclass 6, count 2 2006.201.21:04:39.69#ibcon#enter sib2, iclass 6, count 2 2006.201.21:04:39.69#ibcon#flushed, iclass 6, count 2 2006.201.21:04:39.69#ibcon#about to write, iclass 6, count 2 2006.201.21:04:39.69#ibcon#wrote, iclass 6, count 2 2006.201.21:04:39.69#ibcon#about to read 3, iclass 6, count 2 2006.201.21:04:39.71#ibcon#read 3, iclass 6, count 2 2006.201.21:04:39.71#ibcon#about to read 4, iclass 6, count 2 2006.201.21:04:39.71#ibcon#read 4, iclass 6, count 2 2006.201.21:04:39.71#ibcon#about to read 5, iclass 6, count 2 2006.201.21:04:39.71#ibcon#read 5, iclass 6, count 2 2006.201.21:04:39.71#ibcon#about to read 6, iclass 6, count 2 2006.201.21:04:39.71#ibcon#read 6, iclass 6, count 2 2006.201.21:04:39.71#ibcon#end of sib2, iclass 6, count 2 2006.201.21:04:39.71#ibcon#*mode == 0, iclass 6, count 2 2006.201.21:04:39.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.21:04:39.71#ibcon#[27=AT07-04\r\n] 2006.201.21:04:39.71#ibcon#*before write, iclass 6, count 2 2006.201.21:04:39.71#ibcon#enter sib2, iclass 6, count 2 2006.201.21:04:39.71#ibcon#flushed, iclass 6, count 2 2006.201.21:04:39.71#ibcon#about to write, iclass 6, count 2 2006.201.21:04:39.71#ibcon#wrote, iclass 6, count 2 2006.201.21:04:39.71#ibcon#about to read 3, iclass 6, count 2 2006.201.21:04:39.74#ibcon#read 3, iclass 6, count 2 2006.201.21:04:39.74#ibcon#about to read 4, iclass 6, count 2 2006.201.21:04:39.74#ibcon#read 4, iclass 6, count 2 2006.201.21:04:39.74#ibcon#about to read 5, iclass 6, count 2 2006.201.21:04:39.74#ibcon#read 5, iclass 6, count 2 2006.201.21:04:39.74#ibcon#about to read 6, iclass 6, count 2 2006.201.21:04:39.74#ibcon#read 6, iclass 6, count 2 2006.201.21:04:39.74#ibcon#end of sib2, iclass 6, count 2 2006.201.21:04:39.74#ibcon#*after write, iclass 6, count 2 2006.201.21:04:39.74#ibcon#*before return 0, iclass 6, count 2 2006.201.21:04:39.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:39.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:04:39.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.21:04:39.74#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:39.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:39.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:39.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:39.86#ibcon#enter wrdev, iclass 6, count 0 2006.201.21:04:39.86#ibcon#first serial, iclass 6, count 0 2006.201.21:04:39.86#ibcon#enter sib2, iclass 6, count 0 2006.201.21:04:39.86#ibcon#flushed, iclass 6, count 0 2006.201.21:04:39.86#ibcon#about to write, iclass 6, count 0 2006.201.21:04:39.86#ibcon#wrote, iclass 6, count 0 2006.201.21:04:39.86#ibcon#about to read 3, iclass 6, count 0 2006.201.21:04:39.88#ibcon#read 3, iclass 6, count 0 2006.201.21:04:39.88#ibcon#about to read 4, iclass 6, count 0 2006.201.21:04:39.88#ibcon#read 4, iclass 6, count 0 2006.201.21:04:39.88#ibcon#about to read 5, iclass 6, count 0 2006.201.21:04:39.88#ibcon#read 5, iclass 6, count 0 2006.201.21:04:39.88#ibcon#about to read 6, iclass 6, count 0 2006.201.21:04:39.88#ibcon#read 6, iclass 6, count 0 2006.201.21:04:39.88#ibcon#end of sib2, iclass 6, count 0 2006.201.21:04:39.88#ibcon#*mode == 0, iclass 6, count 0 2006.201.21:04:39.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.21:04:39.88#ibcon#[27=USB\r\n] 2006.201.21:04:39.88#ibcon#*before write, iclass 6, count 0 2006.201.21:04:39.88#ibcon#enter sib2, iclass 6, count 0 2006.201.21:04:39.88#ibcon#flushed, iclass 6, count 0 2006.201.21:04:39.88#ibcon#about to write, iclass 6, count 0 2006.201.21:04:39.88#ibcon#wrote, iclass 6, count 0 2006.201.21:04:39.88#ibcon#about to read 3, iclass 6, count 0 2006.201.21:04:39.91#ibcon#read 3, iclass 6, count 0 2006.201.21:04:39.91#ibcon#about to read 4, iclass 6, count 0 2006.201.21:04:39.91#ibcon#read 4, iclass 6, count 0 2006.201.21:04:39.91#ibcon#about to read 5, iclass 6, count 0 2006.201.21:04:39.91#ibcon#read 5, iclass 6, count 0 2006.201.21:04:39.91#ibcon#about to read 6, iclass 6, count 0 2006.201.21:04:39.91#ibcon#read 6, iclass 6, count 0 2006.201.21:04:39.91#ibcon#end of sib2, iclass 6, count 0 2006.201.21:04:39.91#ibcon#*after write, iclass 6, count 0 2006.201.21:04:39.91#ibcon#*before return 0, iclass 6, count 0 2006.201.21:04:39.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:39.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:04:39.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.21:04:39.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.21:04:39.91$vck44/vblo=8,744.99 2006.201.21:04:39.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.21:04:39.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.21:04:39.91#ibcon#ireg 17 cls_cnt 0 2006.201.21:04:39.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:39.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:39.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:39.91#ibcon#enter wrdev, iclass 10, count 0 2006.201.21:04:39.91#ibcon#first serial, iclass 10, count 0 2006.201.21:04:39.91#ibcon#enter sib2, iclass 10, count 0 2006.201.21:04:39.91#ibcon#flushed, iclass 10, count 0 2006.201.21:04:39.91#ibcon#about to write, iclass 10, count 0 2006.201.21:04:39.91#ibcon#wrote, iclass 10, count 0 2006.201.21:04:39.91#ibcon#about to read 3, iclass 10, count 0 2006.201.21:04:39.93#ibcon#read 3, iclass 10, count 0 2006.201.21:04:39.93#ibcon#about to read 4, iclass 10, count 0 2006.201.21:04:39.93#ibcon#read 4, iclass 10, count 0 2006.201.21:04:39.93#ibcon#about to read 5, iclass 10, count 0 2006.201.21:04:39.93#ibcon#read 5, iclass 10, count 0 2006.201.21:04:39.93#ibcon#about to read 6, iclass 10, count 0 2006.201.21:04:39.93#ibcon#read 6, iclass 10, count 0 2006.201.21:04:39.93#ibcon#end of sib2, iclass 10, count 0 2006.201.21:04:39.93#ibcon#*mode == 0, iclass 10, count 0 2006.201.21:04:39.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.21:04:39.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.21:04:39.93#ibcon#*before write, iclass 10, count 0 2006.201.21:04:39.93#ibcon#enter sib2, iclass 10, count 0 2006.201.21:04:39.93#ibcon#flushed, iclass 10, count 0 2006.201.21:04:39.93#ibcon#about to write, iclass 10, count 0 2006.201.21:04:39.93#ibcon#wrote, iclass 10, count 0 2006.201.21:04:39.93#ibcon#about to read 3, iclass 10, count 0 2006.201.21:04:39.97#ibcon#read 3, iclass 10, count 0 2006.201.21:04:39.97#ibcon#about to read 4, iclass 10, count 0 2006.201.21:04:39.97#ibcon#read 4, iclass 10, count 0 2006.201.21:04:39.97#ibcon#about to read 5, iclass 10, count 0 2006.201.21:04:39.97#ibcon#read 5, iclass 10, count 0 2006.201.21:04:39.97#ibcon#about to read 6, iclass 10, count 0 2006.201.21:04:39.97#ibcon#read 6, iclass 10, count 0 2006.201.21:04:39.97#ibcon#end of sib2, iclass 10, count 0 2006.201.21:04:39.97#ibcon#*after write, iclass 10, count 0 2006.201.21:04:39.97#ibcon#*before return 0, iclass 10, count 0 2006.201.21:04:39.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:39.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:04:39.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.21:04:39.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.21:04:39.97$vck44/vb=8,4 2006.201.21:04:39.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.21:04:39.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.21:04:39.97#ibcon#ireg 11 cls_cnt 2 2006.201.21:04:39.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:40.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:40.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:40.03#ibcon#enter wrdev, iclass 12, count 2 2006.201.21:04:40.03#ibcon#first serial, iclass 12, count 2 2006.201.21:04:40.03#ibcon#enter sib2, iclass 12, count 2 2006.201.21:04:40.03#ibcon#flushed, iclass 12, count 2 2006.201.21:04:40.03#ibcon#about to write, iclass 12, count 2 2006.201.21:04:40.03#ibcon#wrote, iclass 12, count 2 2006.201.21:04:40.03#ibcon#about to read 3, iclass 12, count 2 2006.201.21:04:40.05#ibcon#read 3, iclass 12, count 2 2006.201.21:04:40.05#ibcon#about to read 4, iclass 12, count 2 2006.201.21:04:40.05#ibcon#read 4, iclass 12, count 2 2006.201.21:04:40.05#ibcon#about to read 5, iclass 12, count 2 2006.201.21:04:40.05#ibcon#read 5, iclass 12, count 2 2006.201.21:04:40.05#ibcon#about to read 6, iclass 12, count 2 2006.201.21:04:40.05#ibcon#read 6, iclass 12, count 2 2006.201.21:04:40.05#ibcon#end of sib2, iclass 12, count 2 2006.201.21:04:40.05#ibcon#*mode == 0, iclass 12, count 2 2006.201.21:04:40.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.21:04:40.05#ibcon#[27=AT08-04\r\n] 2006.201.21:04:40.05#ibcon#*before write, iclass 12, count 2 2006.201.21:04:40.05#ibcon#enter sib2, iclass 12, count 2 2006.201.21:04:40.05#ibcon#flushed, iclass 12, count 2 2006.201.21:04:40.05#ibcon#about to write, iclass 12, count 2 2006.201.21:04:40.05#ibcon#wrote, iclass 12, count 2 2006.201.21:04:40.05#ibcon#about to read 3, iclass 12, count 2 2006.201.21:04:40.08#ibcon#read 3, iclass 12, count 2 2006.201.21:04:40.08#ibcon#about to read 4, iclass 12, count 2 2006.201.21:04:40.08#ibcon#read 4, iclass 12, count 2 2006.201.21:04:40.08#ibcon#about to read 5, iclass 12, count 2 2006.201.21:04:40.08#ibcon#read 5, iclass 12, count 2 2006.201.21:04:40.08#ibcon#about to read 6, iclass 12, count 2 2006.201.21:04:40.08#ibcon#read 6, iclass 12, count 2 2006.201.21:04:40.08#ibcon#end of sib2, iclass 12, count 2 2006.201.21:04:40.08#ibcon#*after write, iclass 12, count 2 2006.201.21:04:40.08#ibcon#*before return 0, iclass 12, count 2 2006.201.21:04:40.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:40.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:04:40.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.21:04:40.08#ibcon#ireg 7 cls_cnt 0 2006.201.21:04:40.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:40.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:40.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:40.20#ibcon#enter wrdev, iclass 12, count 0 2006.201.21:04:40.20#ibcon#first serial, iclass 12, count 0 2006.201.21:04:40.20#ibcon#enter sib2, iclass 12, count 0 2006.201.21:04:40.20#ibcon#flushed, iclass 12, count 0 2006.201.21:04:40.20#ibcon#about to write, iclass 12, count 0 2006.201.21:04:40.20#ibcon#wrote, iclass 12, count 0 2006.201.21:04:40.20#ibcon#about to read 3, iclass 12, count 0 2006.201.21:04:40.22#ibcon#read 3, iclass 12, count 0 2006.201.21:04:40.22#ibcon#about to read 4, iclass 12, count 0 2006.201.21:04:40.22#ibcon#read 4, iclass 12, count 0 2006.201.21:04:40.22#ibcon#about to read 5, iclass 12, count 0 2006.201.21:04:40.22#ibcon#read 5, iclass 12, count 0 2006.201.21:04:40.22#ibcon#about to read 6, iclass 12, count 0 2006.201.21:04:40.22#ibcon#read 6, iclass 12, count 0 2006.201.21:04:40.22#ibcon#end of sib2, iclass 12, count 0 2006.201.21:04:40.22#ibcon#*mode == 0, iclass 12, count 0 2006.201.21:04:40.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.21:04:40.22#ibcon#[27=USB\r\n] 2006.201.21:04:40.22#ibcon#*before write, iclass 12, count 0 2006.201.21:04:40.22#ibcon#enter sib2, iclass 12, count 0 2006.201.21:04:40.22#ibcon#flushed, iclass 12, count 0 2006.201.21:04:40.22#ibcon#about to write, iclass 12, count 0 2006.201.21:04:40.22#ibcon#wrote, iclass 12, count 0 2006.201.21:04:40.22#ibcon#about to read 3, iclass 12, count 0 2006.201.21:04:40.25#ibcon#read 3, iclass 12, count 0 2006.201.21:04:40.25#ibcon#about to read 4, iclass 12, count 0 2006.201.21:04:40.25#ibcon#read 4, iclass 12, count 0 2006.201.21:04:40.25#ibcon#about to read 5, iclass 12, count 0 2006.201.21:04:40.25#ibcon#read 5, iclass 12, count 0 2006.201.21:04:40.25#ibcon#about to read 6, iclass 12, count 0 2006.201.21:04:40.25#ibcon#read 6, iclass 12, count 0 2006.201.21:04:40.25#ibcon#end of sib2, iclass 12, count 0 2006.201.21:04:40.25#ibcon#*after write, iclass 12, count 0 2006.201.21:04:40.25#ibcon#*before return 0, iclass 12, count 0 2006.201.21:04:40.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:40.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:04:40.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.21:04:40.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.21:04:40.25$vck44/vabw=wide 2006.201.21:04:40.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.21:04:40.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.21:04:40.25#ibcon#ireg 8 cls_cnt 0 2006.201.21:04:40.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:40.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:40.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:40.25#ibcon#enter wrdev, iclass 14, count 0 2006.201.21:04:40.25#ibcon#first serial, iclass 14, count 0 2006.201.21:04:40.25#ibcon#enter sib2, iclass 14, count 0 2006.201.21:04:40.25#ibcon#flushed, iclass 14, count 0 2006.201.21:04:40.25#ibcon#about to write, iclass 14, count 0 2006.201.21:04:40.25#ibcon#wrote, iclass 14, count 0 2006.201.21:04:40.25#ibcon#about to read 3, iclass 14, count 0 2006.201.21:04:40.27#ibcon#read 3, iclass 14, count 0 2006.201.21:04:40.27#ibcon#about to read 4, iclass 14, count 0 2006.201.21:04:40.27#ibcon#read 4, iclass 14, count 0 2006.201.21:04:40.27#ibcon#about to read 5, iclass 14, count 0 2006.201.21:04:40.27#ibcon#read 5, iclass 14, count 0 2006.201.21:04:40.27#ibcon#about to read 6, iclass 14, count 0 2006.201.21:04:40.27#ibcon#read 6, iclass 14, count 0 2006.201.21:04:40.27#ibcon#end of sib2, iclass 14, count 0 2006.201.21:04:40.27#ibcon#*mode == 0, iclass 14, count 0 2006.201.21:04:40.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.21:04:40.27#ibcon#[25=BW32\r\n] 2006.201.21:04:40.27#ibcon#*before write, iclass 14, count 0 2006.201.21:04:40.27#ibcon#enter sib2, iclass 14, count 0 2006.201.21:04:40.27#ibcon#flushed, iclass 14, count 0 2006.201.21:04:40.27#ibcon#about to write, iclass 14, count 0 2006.201.21:04:40.27#ibcon#wrote, iclass 14, count 0 2006.201.21:04:40.27#ibcon#about to read 3, iclass 14, count 0 2006.201.21:04:40.30#ibcon#read 3, iclass 14, count 0 2006.201.21:04:40.30#ibcon#about to read 4, iclass 14, count 0 2006.201.21:04:40.30#ibcon#read 4, iclass 14, count 0 2006.201.21:04:40.30#ibcon#about to read 5, iclass 14, count 0 2006.201.21:04:40.30#ibcon#read 5, iclass 14, count 0 2006.201.21:04:40.30#ibcon#about to read 6, iclass 14, count 0 2006.201.21:04:40.30#ibcon#read 6, iclass 14, count 0 2006.201.21:04:40.30#ibcon#end of sib2, iclass 14, count 0 2006.201.21:04:40.30#ibcon#*after write, iclass 14, count 0 2006.201.21:04:40.30#ibcon#*before return 0, iclass 14, count 0 2006.201.21:04:40.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:40.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:04:40.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.21:04:40.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.21:04:40.30$vck44/vbbw=wide 2006.201.21:04:40.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.21:04:40.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.21:04:40.30#ibcon#ireg 8 cls_cnt 0 2006.201.21:04:40.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:04:40.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:04:40.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:04:40.37#ibcon#enter wrdev, iclass 16, count 0 2006.201.21:04:40.37#ibcon#first serial, iclass 16, count 0 2006.201.21:04:40.37#ibcon#enter sib2, iclass 16, count 0 2006.201.21:04:40.37#ibcon#flushed, iclass 16, count 0 2006.201.21:04:40.37#ibcon#about to write, iclass 16, count 0 2006.201.21:04:40.37#ibcon#wrote, iclass 16, count 0 2006.201.21:04:40.37#ibcon#about to read 3, iclass 16, count 0 2006.201.21:04:40.39#ibcon#read 3, iclass 16, count 0 2006.201.21:04:40.39#ibcon#about to read 4, iclass 16, count 0 2006.201.21:04:40.39#ibcon#read 4, iclass 16, count 0 2006.201.21:04:40.39#ibcon#about to read 5, iclass 16, count 0 2006.201.21:04:40.39#ibcon#read 5, iclass 16, count 0 2006.201.21:04:40.39#ibcon#about to read 6, iclass 16, count 0 2006.201.21:04:40.39#ibcon#read 6, iclass 16, count 0 2006.201.21:04:40.39#ibcon#end of sib2, iclass 16, count 0 2006.201.21:04:40.39#ibcon#*mode == 0, iclass 16, count 0 2006.201.21:04:40.39#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.21:04:40.39#ibcon#[27=BW32\r\n] 2006.201.21:04:40.39#ibcon#*before write, iclass 16, count 0 2006.201.21:04:40.39#ibcon#enter sib2, iclass 16, count 0 2006.201.21:04:40.39#ibcon#flushed, iclass 16, count 0 2006.201.21:04:40.39#ibcon#about to write, iclass 16, count 0 2006.201.21:04:40.39#ibcon#wrote, iclass 16, count 0 2006.201.21:04:40.39#ibcon#about to read 3, iclass 16, count 0 2006.201.21:04:40.42#ibcon#read 3, iclass 16, count 0 2006.201.21:04:40.42#ibcon#about to read 4, iclass 16, count 0 2006.201.21:04:40.42#ibcon#read 4, iclass 16, count 0 2006.201.21:04:40.42#ibcon#about to read 5, iclass 16, count 0 2006.201.21:04:40.42#ibcon#read 5, iclass 16, count 0 2006.201.21:04:40.42#ibcon#about to read 6, iclass 16, count 0 2006.201.21:04:40.42#ibcon#read 6, iclass 16, count 0 2006.201.21:04:40.42#ibcon#end of sib2, iclass 16, count 0 2006.201.21:04:40.42#ibcon#*after write, iclass 16, count 0 2006.201.21:04:40.42#ibcon#*before return 0, iclass 16, count 0 2006.201.21:04:40.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:04:40.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:04:40.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.21:04:40.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.21:04:40.42$setupk4/ifdk4 2006.201.21:04:40.42$ifdk4/lo= 2006.201.21:04:40.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.21:04:40.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.21:04:40.42$ifdk4/patch= 2006.201.21:04:40.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.21:04:40.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.21:04:40.42$setupk4/!*+20s 2006.201.21:04:40.44#abcon#<5=/00 0.2 0.8 20.161001002.4\r\n> 2006.201.21:04:40.46#abcon#{5=INTERFACE CLEAR} 2006.201.21:04:40.52#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:04:50.61#abcon#<5=/00 0.2 0.9 20.161001002.4\r\n> 2006.201.21:04:50.63#abcon#{5=INTERFACE CLEAR} 2006.201.21:04:50.69#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:04:54.91$setupk4/"tpicd 2006.201.21:04:54.91$setupk4/echo=off 2006.201.21:04:54.91$setupk4/xlog=off 2006.201.21:04:54.91:!2006.201.21:14:39 2006.201.21:05:21.14#trakl#Source acquired 2006.201.21:05:21.14#flagr#flagr/antenna,acquired 2006.201.21:14:39.00:preob 2006.201.21:14:40.14/onsource/TRACKING 2006.201.21:14:40.14:!2006.201.21:14:49 2006.201.21:14:49.00:"tape 2006.201.21:14:49.00:"st=record 2006.201.21:14:49.00:data_valid=on 2006.201.21:14:49.00:midob 2006.201.21:14:49.14/onsource/TRACKING 2006.201.21:14:49.14/wx/20.10,1002.2,100 2006.201.21:14:49.21/cable/+6.4818E-03 2006.201.21:14:50.30/va/01,08,usb,yes,54,57 2006.201.21:14:50.30/va/02,07,usb,yes,58,59 2006.201.21:14:50.30/va/03,08,usb,yes,53,55 2006.201.21:14:50.30/va/04,07,usb,yes,60,63 2006.201.21:14:50.30/va/05,04,usb,yes,54,55 2006.201.21:14:50.30/va/06,05,usb,yes,54,54 2006.201.21:14:50.30/va/07,05,usb,yes,53,55 2006.201.21:14:50.30/va/08,04,usb,yes,53,62 2006.201.21:14:50.53/valo/01,524.99,yes,locked 2006.201.21:14:50.53/valo/02,534.99,yes,locked 2006.201.21:14:50.53/valo/03,564.99,yes,locked 2006.201.21:14:50.53/valo/04,624.99,yes,locked 2006.201.21:14:50.53/valo/05,734.99,yes,locked 2006.201.21:14:50.53/valo/06,814.99,yes,locked 2006.201.21:14:50.53/valo/07,864.99,yes,locked 2006.201.21:14:50.53/valo/08,884.99,yes,locked 2006.201.21:14:51.62/vb/01,04,usb,yes,31,29 2006.201.21:14:51.62/vb/02,05,usb,yes,30,30 2006.201.21:14:51.62/vb/03,04,usb,yes,31,34 2006.201.21:14:51.62/vb/04,05,usb,yes,31,30 2006.201.21:14:51.62/vb/05,04,usb,yes,28,30 2006.201.21:14:51.62/vb/06,04,usb,yes,32,28 2006.201.21:14:51.62/vb/07,04,usb,yes,32,32 2006.201.21:14:51.62/vb/08,04,usb,yes,29,33 2006.201.21:14:51.85/vblo/01,629.99,yes,locked 2006.201.21:14:51.85/vblo/02,634.99,yes,locked 2006.201.21:14:51.85/vblo/03,649.99,yes,locked 2006.201.21:14:51.85/vblo/04,679.99,yes,locked 2006.201.21:14:51.85/vblo/05,709.99,yes,locked 2006.201.21:14:51.85/vblo/06,719.99,yes,locked 2006.201.21:14:51.85/vblo/07,734.99,yes,locked 2006.201.21:14:51.85/vblo/08,744.99,yes,locked 2006.201.21:14:52.00/vabw/8 2006.201.21:14:52.15/vbbw/8 2006.201.21:14:52.24/xfe/off,on,15.5 2006.201.21:14:52.62/ifatt/23,28,28,28 2006.201.21:14:53.06/fmout-gps/S +4.57E-07 2006.201.21:14:53.12:!2006.201.21:16:19 2006.201.21:16:19.00:data_valid=off 2006.201.21:16:19.00:"et 2006.201.21:16:19.00:!+3s 2006.201.21:16:22.02:"tape 2006.201.21:16:22.02:postob 2006.201.21:16:22.13/cable/+6.4820E-03 2006.201.21:16:22.13/wx/20.10,1002.2,100 2006.201.21:16:22.21/fmout-gps/S +4.57E-07 2006.201.21:16:22.21:scan_name=201-2120,jd0607,220 2006.201.21:16:22.22:source=3c446,222547.26,-045701.4,2000.0,ccw 2006.201.21:16:23.13#flagr#flagr/antenna,new-source 2006.201.21:16:23.13:checkk5 2006.201.21:16:23.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.21:16:23.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.21:16:24.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.21:16:24.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.21:16:25.01/chk_obsdata//k5ts1/T2012114??a.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.21:16:25.38/chk_obsdata//k5ts2/T2012114??b.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.21:16:25.75/chk_obsdata//k5ts3/T2012114??c.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.21:16:26.11/chk_obsdata//k5ts4/T2012114??d.dat file size is correct (nominal:360MB, actual:360MB). 2006.201.21:16:26.80/k5log//k5ts1_log_newline 2006.201.21:16:27.48/k5log//k5ts2_log_newline 2006.201.21:16:28.17/k5log//k5ts3_log_newline 2006.201.21:16:28.85/k5log//k5ts4_log_newline 2006.201.21:16:28.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.21:16:28.88:setupk4=1 2006.201.21:16:28.88$setupk4/echo=on 2006.201.21:16:28.88$setupk4/pcalon 2006.201.21:16:28.88$pcalon/"no phase cal control is implemented here 2006.201.21:16:28.88$setupk4/"tpicd=stop 2006.201.21:16:28.88$setupk4/"rec=synch_on 2006.201.21:16:28.88$setupk4/"rec_mode=128 2006.201.21:16:28.88$setupk4/!* 2006.201.21:16:28.88$setupk4/recpk4 2006.201.21:16:28.88$recpk4/recpatch= 2006.201.21:16:28.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.21:16:28.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.21:16:28.88$setupk4/vck44 2006.201.21:16:28.88$vck44/valo=1,524.99 2006.201.21:16:28.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.21:16:28.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.21:16:28.88#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:28.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:28.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:28.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:28.88#ibcon#enter wrdev, iclass 13, count 0 2006.201.21:16:28.88#ibcon#first serial, iclass 13, count 0 2006.201.21:16:28.88#ibcon#enter sib2, iclass 13, count 0 2006.201.21:16:28.88#ibcon#flushed, iclass 13, count 0 2006.201.21:16:28.88#ibcon#about to write, iclass 13, count 0 2006.201.21:16:28.88#ibcon#wrote, iclass 13, count 0 2006.201.21:16:28.88#ibcon#about to read 3, iclass 13, count 0 2006.201.21:16:28.92#ibcon#read 3, iclass 13, count 0 2006.201.21:16:28.92#ibcon#about to read 4, iclass 13, count 0 2006.201.21:16:28.92#ibcon#read 4, iclass 13, count 0 2006.201.21:16:28.92#ibcon#about to read 5, iclass 13, count 0 2006.201.21:16:28.92#ibcon#read 5, iclass 13, count 0 2006.201.21:16:28.92#ibcon#about to read 6, iclass 13, count 0 2006.201.21:16:28.92#ibcon#read 6, iclass 13, count 0 2006.201.21:16:28.92#ibcon#end of sib2, iclass 13, count 0 2006.201.21:16:28.92#ibcon#*mode == 0, iclass 13, count 0 2006.201.21:16:28.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.21:16:28.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.21:16:28.92#ibcon#*before write, iclass 13, count 0 2006.201.21:16:28.92#ibcon#enter sib2, iclass 13, count 0 2006.201.21:16:28.92#ibcon#flushed, iclass 13, count 0 2006.201.21:16:28.92#ibcon#about to write, iclass 13, count 0 2006.201.21:16:28.92#ibcon#wrote, iclass 13, count 0 2006.201.21:16:28.92#ibcon#about to read 3, iclass 13, count 0 2006.201.21:16:28.97#ibcon#read 3, iclass 13, count 0 2006.201.21:16:28.97#ibcon#about to read 4, iclass 13, count 0 2006.201.21:16:28.97#ibcon#read 4, iclass 13, count 0 2006.201.21:16:28.97#ibcon#about to read 5, iclass 13, count 0 2006.201.21:16:28.97#ibcon#read 5, iclass 13, count 0 2006.201.21:16:28.97#ibcon#about to read 6, iclass 13, count 0 2006.201.21:16:28.97#ibcon#read 6, iclass 13, count 0 2006.201.21:16:28.97#ibcon#end of sib2, iclass 13, count 0 2006.201.21:16:28.97#ibcon#*after write, iclass 13, count 0 2006.201.21:16:28.97#ibcon#*before return 0, iclass 13, count 0 2006.201.21:16:28.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:28.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:28.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.21:16:28.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.21:16:28.97$vck44/va=1,8 2006.201.21:16:28.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.21:16:28.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.21:16:28.97#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:28.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:28.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:28.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:28.97#ibcon#enter wrdev, iclass 15, count 2 2006.201.21:16:28.97#ibcon#first serial, iclass 15, count 2 2006.201.21:16:28.97#ibcon#enter sib2, iclass 15, count 2 2006.201.21:16:28.97#ibcon#flushed, iclass 15, count 2 2006.201.21:16:28.97#ibcon#about to write, iclass 15, count 2 2006.201.21:16:28.97#ibcon#wrote, iclass 15, count 2 2006.201.21:16:28.97#ibcon#about to read 3, iclass 15, count 2 2006.201.21:16:28.99#ibcon#read 3, iclass 15, count 2 2006.201.21:16:28.99#ibcon#about to read 4, iclass 15, count 2 2006.201.21:16:28.99#ibcon#read 4, iclass 15, count 2 2006.201.21:16:28.99#ibcon#about to read 5, iclass 15, count 2 2006.201.21:16:28.99#ibcon#read 5, iclass 15, count 2 2006.201.21:16:28.99#ibcon#about to read 6, iclass 15, count 2 2006.201.21:16:28.99#ibcon#read 6, iclass 15, count 2 2006.201.21:16:28.99#ibcon#end of sib2, iclass 15, count 2 2006.201.21:16:28.99#ibcon#*mode == 0, iclass 15, count 2 2006.201.21:16:28.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.21:16:28.99#ibcon#[25=AT01-08\r\n] 2006.201.21:16:28.99#ibcon#*before write, iclass 15, count 2 2006.201.21:16:28.99#ibcon#enter sib2, iclass 15, count 2 2006.201.21:16:28.99#ibcon#flushed, iclass 15, count 2 2006.201.21:16:28.99#ibcon#about to write, iclass 15, count 2 2006.201.21:16:28.99#ibcon#wrote, iclass 15, count 2 2006.201.21:16:28.99#ibcon#about to read 3, iclass 15, count 2 2006.201.21:16:29.03#ibcon#read 3, iclass 15, count 2 2006.201.21:16:29.03#ibcon#about to read 4, iclass 15, count 2 2006.201.21:16:29.03#ibcon#read 4, iclass 15, count 2 2006.201.21:16:29.03#ibcon#about to read 5, iclass 15, count 2 2006.201.21:16:29.03#ibcon#read 5, iclass 15, count 2 2006.201.21:16:29.03#ibcon#about to read 6, iclass 15, count 2 2006.201.21:16:29.03#ibcon#read 6, iclass 15, count 2 2006.201.21:16:29.03#ibcon#end of sib2, iclass 15, count 2 2006.201.21:16:29.03#ibcon#*after write, iclass 15, count 2 2006.201.21:16:29.03#ibcon#*before return 0, iclass 15, count 2 2006.201.21:16:29.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:29.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:29.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.21:16:29.03#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:29.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:29.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:29.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:29.15#ibcon#enter wrdev, iclass 15, count 0 2006.201.21:16:29.15#ibcon#first serial, iclass 15, count 0 2006.201.21:16:29.15#ibcon#enter sib2, iclass 15, count 0 2006.201.21:16:29.15#ibcon#flushed, iclass 15, count 0 2006.201.21:16:29.15#ibcon#about to write, iclass 15, count 0 2006.201.21:16:29.15#ibcon#wrote, iclass 15, count 0 2006.201.21:16:29.15#ibcon#about to read 3, iclass 15, count 0 2006.201.21:16:29.17#ibcon#read 3, iclass 15, count 0 2006.201.21:16:29.17#ibcon#about to read 4, iclass 15, count 0 2006.201.21:16:29.17#ibcon#read 4, iclass 15, count 0 2006.201.21:16:29.17#ibcon#about to read 5, iclass 15, count 0 2006.201.21:16:29.17#ibcon#read 5, iclass 15, count 0 2006.201.21:16:29.17#ibcon#about to read 6, iclass 15, count 0 2006.201.21:16:29.17#ibcon#read 6, iclass 15, count 0 2006.201.21:16:29.17#ibcon#end of sib2, iclass 15, count 0 2006.201.21:16:29.17#ibcon#*mode == 0, iclass 15, count 0 2006.201.21:16:29.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.21:16:29.17#ibcon#[25=USB\r\n] 2006.201.21:16:29.17#ibcon#*before write, iclass 15, count 0 2006.201.21:16:29.17#ibcon#enter sib2, iclass 15, count 0 2006.201.21:16:29.17#ibcon#flushed, iclass 15, count 0 2006.201.21:16:29.17#ibcon#about to write, iclass 15, count 0 2006.201.21:16:29.17#ibcon#wrote, iclass 15, count 0 2006.201.21:16:29.17#ibcon#about to read 3, iclass 15, count 0 2006.201.21:16:29.20#ibcon#read 3, iclass 15, count 0 2006.201.21:16:29.20#ibcon#about to read 4, iclass 15, count 0 2006.201.21:16:29.20#ibcon#read 4, iclass 15, count 0 2006.201.21:16:29.20#ibcon#about to read 5, iclass 15, count 0 2006.201.21:16:29.20#ibcon#read 5, iclass 15, count 0 2006.201.21:16:29.20#ibcon#about to read 6, iclass 15, count 0 2006.201.21:16:29.20#ibcon#read 6, iclass 15, count 0 2006.201.21:16:29.20#ibcon#end of sib2, iclass 15, count 0 2006.201.21:16:29.20#ibcon#*after write, iclass 15, count 0 2006.201.21:16:29.20#ibcon#*before return 0, iclass 15, count 0 2006.201.21:16:29.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:29.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:29.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.21:16:29.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.21:16:29.20$vck44/valo=2,534.99 2006.201.21:16:29.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.21:16:29.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.21:16:29.20#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:29.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:29.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:29.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:29.20#ibcon#enter wrdev, iclass 17, count 0 2006.201.21:16:29.20#ibcon#first serial, iclass 17, count 0 2006.201.21:16:29.20#ibcon#enter sib2, iclass 17, count 0 2006.201.21:16:29.20#ibcon#flushed, iclass 17, count 0 2006.201.21:16:29.20#ibcon#about to write, iclass 17, count 0 2006.201.21:16:29.20#ibcon#wrote, iclass 17, count 0 2006.201.21:16:29.20#ibcon#about to read 3, iclass 17, count 0 2006.201.21:16:29.22#ibcon#read 3, iclass 17, count 0 2006.201.21:16:29.22#ibcon#about to read 4, iclass 17, count 0 2006.201.21:16:29.22#ibcon#read 4, iclass 17, count 0 2006.201.21:16:29.22#ibcon#about to read 5, iclass 17, count 0 2006.201.21:16:29.22#ibcon#read 5, iclass 17, count 0 2006.201.21:16:29.22#ibcon#about to read 6, iclass 17, count 0 2006.201.21:16:29.22#ibcon#read 6, iclass 17, count 0 2006.201.21:16:29.22#ibcon#end of sib2, iclass 17, count 0 2006.201.21:16:29.22#ibcon#*mode == 0, iclass 17, count 0 2006.201.21:16:29.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.21:16:29.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.21:16:29.22#ibcon#*before write, iclass 17, count 0 2006.201.21:16:29.22#ibcon#enter sib2, iclass 17, count 0 2006.201.21:16:29.22#ibcon#flushed, iclass 17, count 0 2006.201.21:16:29.22#ibcon#about to write, iclass 17, count 0 2006.201.21:16:29.22#ibcon#wrote, iclass 17, count 0 2006.201.21:16:29.22#ibcon#about to read 3, iclass 17, count 0 2006.201.21:16:29.26#ibcon#read 3, iclass 17, count 0 2006.201.21:16:29.26#ibcon#about to read 4, iclass 17, count 0 2006.201.21:16:29.26#ibcon#read 4, iclass 17, count 0 2006.201.21:16:29.26#ibcon#about to read 5, iclass 17, count 0 2006.201.21:16:29.26#ibcon#read 5, iclass 17, count 0 2006.201.21:16:29.26#ibcon#about to read 6, iclass 17, count 0 2006.201.21:16:29.26#ibcon#read 6, iclass 17, count 0 2006.201.21:16:29.26#ibcon#end of sib2, iclass 17, count 0 2006.201.21:16:29.26#ibcon#*after write, iclass 17, count 0 2006.201.21:16:29.26#ibcon#*before return 0, iclass 17, count 0 2006.201.21:16:29.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:29.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:29.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.21:16:29.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.21:16:29.26$vck44/va=2,7 2006.201.21:16:29.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.21:16:29.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.21:16:29.26#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:29.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:29.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:29.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:29.32#ibcon#enter wrdev, iclass 19, count 2 2006.201.21:16:29.32#ibcon#first serial, iclass 19, count 2 2006.201.21:16:29.32#ibcon#enter sib2, iclass 19, count 2 2006.201.21:16:29.32#ibcon#flushed, iclass 19, count 2 2006.201.21:16:29.32#ibcon#about to write, iclass 19, count 2 2006.201.21:16:29.32#ibcon#wrote, iclass 19, count 2 2006.201.21:16:29.32#ibcon#about to read 3, iclass 19, count 2 2006.201.21:16:29.34#ibcon#read 3, iclass 19, count 2 2006.201.21:16:29.34#ibcon#about to read 4, iclass 19, count 2 2006.201.21:16:29.34#ibcon#read 4, iclass 19, count 2 2006.201.21:16:29.34#ibcon#about to read 5, iclass 19, count 2 2006.201.21:16:29.34#ibcon#read 5, iclass 19, count 2 2006.201.21:16:29.34#ibcon#about to read 6, iclass 19, count 2 2006.201.21:16:29.34#ibcon#read 6, iclass 19, count 2 2006.201.21:16:29.34#ibcon#end of sib2, iclass 19, count 2 2006.201.21:16:29.34#ibcon#*mode == 0, iclass 19, count 2 2006.201.21:16:29.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.21:16:29.34#ibcon#[25=AT02-07\r\n] 2006.201.21:16:29.34#ibcon#*before write, iclass 19, count 2 2006.201.21:16:29.34#ibcon#enter sib2, iclass 19, count 2 2006.201.21:16:29.34#ibcon#flushed, iclass 19, count 2 2006.201.21:16:29.34#ibcon#about to write, iclass 19, count 2 2006.201.21:16:29.34#ibcon#wrote, iclass 19, count 2 2006.201.21:16:29.34#ibcon#about to read 3, iclass 19, count 2 2006.201.21:16:29.37#ibcon#read 3, iclass 19, count 2 2006.201.21:16:29.37#ibcon#about to read 4, iclass 19, count 2 2006.201.21:16:29.37#ibcon#read 4, iclass 19, count 2 2006.201.21:16:29.37#ibcon#about to read 5, iclass 19, count 2 2006.201.21:16:29.37#ibcon#read 5, iclass 19, count 2 2006.201.21:16:29.37#ibcon#about to read 6, iclass 19, count 2 2006.201.21:16:29.37#ibcon#read 6, iclass 19, count 2 2006.201.21:16:29.37#ibcon#end of sib2, iclass 19, count 2 2006.201.21:16:29.37#ibcon#*after write, iclass 19, count 2 2006.201.21:16:29.37#ibcon#*before return 0, iclass 19, count 2 2006.201.21:16:29.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:29.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:29.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.21:16:29.37#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:29.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:29.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:29.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:29.49#ibcon#enter wrdev, iclass 19, count 0 2006.201.21:16:29.49#ibcon#first serial, iclass 19, count 0 2006.201.21:16:29.49#ibcon#enter sib2, iclass 19, count 0 2006.201.21:16:29.49#ibcon#flushed, iclass 19, count 0 2006.201.21:16:29.49#ibcon#about to write, iclass 19, count 0 2006.201.21:16:29.49#ibcon#wrote, iclass 19, count 0 2006.201.21:16:29.49#ibcon#about to read 3, iclass 19, count 0 2006.201.21:16:29.51#ibcon#read 3, iclass 19, count 0 2006.201.21:16:29.51#ibcon#about to read 4, iclass 19, count 0 2006.201.21:16:29.51#ibcon#read 4, iclass 19, count 0 2006.201.21:16:29.51#ibcon#about to read 5, iclass 19, count 0 2006.201.21:16:29.51#ibcon#read 5, iclass 19, count 0 2006.201.21:16:29.51#ibcon#about to read 6, iclass 19, count 0 2006.201.21:16:29.51#ibcon#read 6, iclass 19, count 0 2006.201.21:16:29.51#ibcon#end of sib2, iclass 19, count 0 2006.201.21:16:29.51#ibcon#*mode == 0, iclass 19, count 0 2006.201.21:16:29.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.21:16:29.51#ibcon#[25=USB\r\n] 2006.201.21:16:29.51#ibcon#*before write, iclass 19, count 0 2006.201.21:16:29.51#ibcon#enter sib2, iclass 19, count 0 2006.201.21:16:29.51#ibcon#flushed, iclass 19, count 0 2006.201.21:16:29.51#ibcon#about to write, iclass 19, count 0 2006.201.21:16:29.51#ibcon#wrote, iclass 19, count 0 2006.201.21:16:29.51#ibcon#about to read 3, iclass 19, count 0 2006.201.21:16:29.54#ibcon#read 3, iclass 19, count 0 2006.201.21:16:29.54#ibcon#about to read 4, iclass 19, count 0 2006.201.21:16:29.54#ibcon#read 4, iclass 19, count 0 2006.201.21:16:29.54#ibcon#about to read 5, iclass 19, count 0 2006.201.21:16:29.54#ibcon#read 5, iclass 19, count 0 2006.201.21:16:29.54#ibcon#about to read 6, iclass 19, count 0 2006.201.21:16:29.54#ibcon#read 6, iclass 19, count 0 2006.201.21:16:29.54#ibcon#end of sib2, iclass 19, count 0 2006.201.21:16:29.54#ibcon#*after write, iclass 19, count 0 2006.201.21:16:29.54#ibcon#*before return 0, iclass 19, count 0 2006.201.21:16:29.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:29.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:29.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.21:16:29.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.21:16:29.54$vck44/valo=3,564.99 2006.201.21:16:29.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.21:16:29.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.21:16:29.54#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:29.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:16:29.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:16:29.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:16:29.54#ibcon#enter wrdev, iclass 21, count 0 2006.201.21:16:29.54#ibcon#first serial, iclass 21, count 0 2006.201.21:16:29.54#ibcon#enter sib2, iclass 21, count 0 2006.201.21:16:29.54#ibcon#flushed, iclass 21, count 0 2006.201.21:16:29.54#ibcon#about to write, iclass 21, count 0 2006.201.21:16:29.54#ibcon#wrote, iclass 21, count 0 2006.201.21:16:29.54#ibcon#about to read 3, iclass 21, count 0 2006.201.21:16:29.56#ibcon#read 3, iclass 21, count 0 2006.201.21:16:29.56#ibcon#about to read 4, iclass 21, count 0 2006.201.21:16:29.56#ibcon#read 4, iclass 21, count 0 2006.201.21:16:29.56#ibcon#about to read 5, iclass 21, count 0 2006.201.21:16:29.56#ibcon#read 5, iclass 21, count 0 2006.201.21:16:29.56#ibcon#about to read 6, iclass 21, count 0 2006.201.21:16:29.56#ibcon#read 6, iclass 21, count 0 2006.201.21:16:29.56#ibcon#end of sib2, iclass 21, count 0 2006.201.21:16:29.56#ibcon#*mode == 0, iclass 21, count 0 2006.201.21:16:29.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.21:16:29.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.21:16:29.56#ibcon#*before write, iclass 21, count 0 2006.201.21:16:29.56#ibcon#enter sib2, iclass 21, count 0 2006.201.21:16:29.56#ibcon#flushed, iclass 21, count 0 2006.201.21:16:29.56#ibcon#about to write, iclass 21, count 0 2006.201.21:16:29.56#ibcon#wrote, iclass 21, count 0 2006.201.21:16:29.56#ibcon#about to read 3, iclass 21, count 0 2006.201.21:16:29.60#ibcon#read 3, iclass 21, count 0 2006.201.21:16:29.60#ibcon#about to read 4, iclass 21, count 0 2006.201.21:16:29.60#ibcon#read 4, iclass 21, count 0 2006.201.21:16:29.60#ibcon#about to read 5, iclass 21, count 0 2006.201.21:16:29.60#ibcon#read 5, iclass 21, count 0 2006.201.21:16:29.60#ibcon#about to read 6, iclass 21, count 0 2006.201.21:16:29.60#ibcon#read 6, iclass 21, count 0 2006.201.21:16:29.60#ibcon#end of sib2, iclass 21, count 0 2006.201.21:16:29.60#ibcon#*after write, iclass 21, count 0 2006.201.21:16:29.60#ibcon#*before return 0, iclass 21, count 0 2006.201.21:16:29.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:16:29.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:16:29.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.21:16:29.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.21:16:29.60$vck44/va=3,8 2006.201.21:16:29.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.21:16:29.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.21:16:29.60#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:29.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:16:29.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:16:29.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:16:29.66#ibcon#enter wrdev, iclass 23, count 2 2006.201.21:16:29.66#ibcon#first serial, iclass 23, count 2 2006.201.21:16:29.66#ibcon#enter sib2, iclass 23, count 2 2006.201.21:16:29.66#ibcon#flushed, iclass 23, count 2 2006.201.21:16:29.66#ibcon#about to write, iclass 23, count 2 2006.201.21:16:29.66#ibcon#wrote, iclass 23, count 2 2006.201.21:16:29.66#ibcon#about to read 3, iclass 23, count 2 2006.201.21:16:29.68#ibcon#read 3, iclass 23, count 2 2006.201.21:16:29.68#ibcon#about to read 4, iclass 23, count 2 2006.201.21:16:29.68#ibcon#read 4, iclass 23, count 2 2006.201.21:16:29.68#ibcon#about to read 5, iclass 23, count 2 2006.201.21:16:29.68#ibcon#read 5, iclass 23, count 2 2006.201.21:16:29.68#ibcon#about to read 6, iclass 23, count 2 2006.201.21:16:29.68#ibcon#read 6, iclass 23, count 2 2006.201.21:16:29.68#ibcon#end of sib2, iclass 23, count 2 2006.201.21:16:29.68#ibcon#*mode == 0, iclass 23, count 2 2006.201.21:16:29.68#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.21:16:29.68#ibcon#[25=AT03-08\r\n] 2006.201.21:16:29.68#ibcon#*before write, iclass 23, count 2 2006.201.21:16:29.68#ibcon#enter sib2, iclass 23, count 2 2006.201.21:16:29.68#ibcon#flushed, iclass 23, count 2 2006.201.21:16:29.68#ibcon#about to write, iclass 23, count 2 2006.201.21:16:29.68#ibcon#wrote, iclass 23, count 2 2006.201.21:16:29.68#ibcon#about to read 3, iclass 23, count 2 2006.201.21:16:29.71#ibcon#read 3, iclass 23, count 2 2006.201.21:16:29.71#ibcon#about to read 4, iclass 23, count 2 2006.201.21:16:29.71#ibcon#read 4, iclass 23, count 2 2006.201.21:16:29.71#ibcon#about to read 5, iclass 23, count 2 2006.201.21:16:29.71#ibcon#read 5, iclass 23, count 2 2006.201.21:16:29.71#ibcon#about to read 6, iclass 23, count 2 2006.201.21:16:29.71#ibcon#read 6, iclass 23, count 2 2006.201.21:16:29.71#ibcon#end of sib2, iclass 23, count 2 2006.201.21:16:29.71#ibcon#*after write, iclass 23, count 2 2006.201.21:16:29.71#ibcon#*before return 0, iclass 23, count 2 2006.201.21:16:29.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:16:29.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:16:29.71#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.21:16:29.71#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:29.71#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:16:29.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:16:29.83#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:16:29.83#ibcon#enter wrdev, iclass 23, count 0 2006.201.21:16:29.83#ibcon#first serial, iclass 23, count 0 2006.201.21:16:29.83#ibcon#enter sib2, iclass 23, count 0 2006.201.21:16:29.83#ibcon#flushed, iclass 23, count 0 2006.201.21:16:29.83#ibcon#about to write, iclass 23, count 0 2006.201.21:16:29.83#ibcon#wrote, iclass 23, count 0 2006.201.21:16:29.83#ibcon#about to read 3, iclass 23, count 0 2006.201.21:16:29.85#ibcon#read 3, iclass 23, count 0 2006.201.21:16:29.85#ibcon#about to read 4, iclass 23, count 0 2006.201.21:16:29.85#ibcon#read 4, iclass 23, count 0 2006.201.21:16:29.85#ibcon#about to read 5, iclass 23, count 0 2006.201.21:16:29.85#ibcon#read 5, iclass 23, count 0 2006.201.21:16:29.85#ibcon#about to read 6, iclass 23, count 0 2006.201.21:16:29.85#ibcon#read 6, iclass 23, count 0 2006.201.21:16:29.85#ibcon#end of sib2, iclass 23, count 0 2006.201.21:16:29.85#ibcon#*mode == 0, iclass 23, count 0 2006.201.21:16:29.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.21:16:29.85#ibcon#[25=USB\r\n] 2006.201.21:16:29.85#ibcon#*before write, iclass 23, count 0 2006.201.21:16:29.85#ibcon#enter sib2, iclass 23, count 0 2006.201.21:16:29.85#ibcon#flushed, iclass 23, count 0 2006.201.21:16:29.85#ibcon#about to write, iclass 23, count 0 2006.201.21:16:29.85#ibcon#wrote, iclass 23, count 0 2006.201.21:16:29.85#ibcon#about to read 3, iclass 23, count 0 2006.201.21:16:29.88#ibcon#read 3, iclass 23, count 0 2006.201.21:16:29.88#ibcon#about to read 4, iclass 23, count 0 2006.201.21:16:29.88#ibcon#read 4, iclass 23, count 0 2006.201.21:16:29.88#ibcon#about to read 5, iclass 23, count 0 2006.201.21:16:29.88#ibcon#read 5, iclass 23, count 0 2006.201.21:16:29.88#ibcon#about to read 6, iclass 23, count 0 2006.201.21:16:29.88#ibcon#read 6, iclass 23, count 0 2006.201.21:16:29.88#ibcon#end of sib2, iclass 23, count 0 2006.201.21:16:29.88#ibcon#*after write, iclass 23, count 0 2006.201.21:16:29.88#ibcon#*before return 0, iclass 23, count 0 2006.201.21:16:29.88#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:16:29.88#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:16:29.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.21:16:29.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.21:16:29.88$vck44/valo=4,624.99 2006.201.21:16:29.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.21:16:29.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.21:16:29.88#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:29.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:29.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:29.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:29.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.21:16:29.88#ibcon#first serial, iclass 25, count 0 2006.201.21:16:29.88#ibcon#enter sib2, iclass 25, count 0 2006.201.21:16:29.88#ibcon#flushed, iclass 25, count 0 2006.201.21:16:29.88#ibcon#about to write, iclass 25, count 0 2006.201.21:16:29.88#ibcon#wrote, iclass 25, count 0 2006.201.21:16:29.88#ibcon#about to read 3, iclass 25, count 0 2006.201.21:16:29.90#ibcon#read 3, iclass 25, count 0 2006.201.21:16:29.90#ibcon#about to read 4, iclass 25, count 0 2006.201.21:16:29.90#ibcon#read 4, iclass 25, count 0 2006.201.21:16:29.90#ibcon#about to read 5, iclass 25, count 0 2006.201.21:16:29.90#ibcon#read 5, iclass 25, count 0 2006.201.21:16:29.90#ibcon#about to read 6, iclass 25, count 0 2006.201.21:16:29.90#ibcon#read 6, iclass 25, count 0 2006.201.21:16:29.90#ibcon#end of sib2, iclass 25, count 0 2006.201.21:16:29.90#ibcon#*mode == 0, iclass 25, count 0 2006.201.21:16:29.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.21:16:29.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.21:16:29.90#ibcon#*before write, iclass 25, count 0 2006.201.21:16:29.90#ibcon#enter sib2, iclass 25, count 0 2006.201.21:16:29.90#ibcon#flushed, iclass 25, count 0 2006.201.21:16:29.90#ibcon#about to write, iclass 25, count 0 2006.201.21:16:29.90#ibcon#wrote, iclass 25, count 0 2006.201.21:16:29.90#ibcon#about to read 3, iclass 25, count 0 2006.201.21:16:29.94#ibcon#read 3, iclass 25, count 0 2006.201.21:16:29.94#ibcon#about to read 4, iclass 25, count 0 2006.201.21:16:29.94#ibcon#read 4, iclass 25, count 0 2006.201.21:16:29.94#ibcon#about to read 5, iclass 25, count 0 2006.201.21:16:29.94#ibcon#read 5, iclass 25, count 0 2006.201.21:16:29.94#ibcon#about to read 6, iclass 25, count 0 2006.201.21:16:29.94#ibcon#read 6, iclass 25, count 0 2006.201.21:16:29.94#ibcon#end of sib2, iclass 25, count 0 2006.201.21:16:29.94#ibcon#*after write, iclass 25, count 0 2006.201.21:16:29.94#ibcon#*before return 0, iclass 25, count 0 2006.201.21:16:29.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:29.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:29.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.21:16:29.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.21:16:29.94$vck44/va=4,7 2006.201.21:16:29.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.21:16:29.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.21:16:29.94#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:29.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:30.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:30.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:30.00#ibcon#enter wrdev, iclass 27, count 2 2006.201.21:16:30.00#ibcon#first serial, iclass 27, count 2 2006.201.21:16:30.00#ibcon#enter sib2, iclass 27, count 2 2006.201.21:16:30.00#ibcon#flushed, iclass 27, count 2 2006.201.21:16:30.00#ibcon#about to write, iclass 27, count 2 2006.201.21:16:30.00#ibcon#wrote, iclass 27, count 2 2006.201.21:16:30.00#ibcon#about to read 3, iclass 27, count 2 2006.201.21:16:30.02#ibcon#read 3, iclass 27, count 2 2006.201.21:16:30.02#ibcon#about to read 4, iclass 27, count 2 2006.201.21:16:30.02#ibcon#read 4, iclass 27, count 2 2006.201.21:16:30.02#ibcon#about to read 5, iclass 27, count 2 2006.201.21:16:30.02#ibcon#read 5, iclass 27, count 2 2006.201.21:16:30.02#ibcon#about to read 6, iclass 27, count 2 2006.201.21:16:30.02#ibcon#read 6, iclass 27, count 2 2006.201.21:16:30.02#ibcon#end of sib2, iclass 27, count 2 2006.201.21:16:30.02#ibcon#*mode == 0, iclass 27, count 2 2006.201.21:16:30.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.21:16:30.02#ibcon#[25=AT04-07\r\n] 2006.201.21:16:30.02#ibcon#*before write, iclass 27, count 2 2006.201.21:16:30.02#ibcon#enter sib2, iclass 27, count 2 2006.201.21:16:30.02#ibcon#flushed, iclass 27, count 2 2006.201.21:16:30.02#ibcon#about to write, iclass 27, count 2 2006.201.21:16:30.02#ibcon#wrote, iclass 27, count 2 2006.201.21:16:30.02#ibcon#about to read 3, iclass 27, count 2 2006.201.21:16:30.05#ibcon#read 3, iclass 27, count 2 2006.201.21:16:30.05#ibcon#about to read 4, iclass 27, count 2 2006.201.21:16:30.05#ibcon#read 4, iclass 27, count 2 2006.201.21:16:30.05#ibcon#about to read 5, iclass 27, count 2 2006.201.21:16:30.05#ibcon#read 5, iclass 27, count 2 2006.201.21:16:30.05#ibcon#about to read 6, iclass 27, count 2 2006.201.21:16:30.05#ibcon#read 6, iclass 27, count 2 2006.201.21:16:30.05#ibcon#end of sib2, iclass 27, count 2 2006.201.21:16:30.05#ibcon#*after write, iclass 27, count 2 2006.201.21:16:30.05#ibcon#*before return 0, iclass 27, count 2 2006.201.21:16:30.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:30.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:30.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.21:16:30.05#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:30.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:30.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:30.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:30.17#ibcon#enter wrdev, iclass 27, count 0 2006.201.21:16:30.17#ibcon#first serial, iclass 27, count 0 2006.201.21:16:30.17#ibcon#enter sib2, iclass 27, count 0 2006.201.21:16:30.17#ibcon#flushed, iclass 27, count 0 2006.201.21:16:30.17#ibcon#about to write, iclass 27, count 0 2006.201.21:16:30.17#ibcon#wrote, iclass 27, count 0 2006.201.21:16:30.17#ibcon#about to read 3, iclass 27, count 0 2006.201.21:16:30.19#ibcon#read 3, iclass 27, count 0 2006.201.21:16:30.19#ibcon#about to read 4, iclass 27, count 0 2006.201.21:16:30.19#ibcon#read 4, iclass 27, count 0 2006.201.21:16:30.19#ibcon#about to read 5, iclass 27, count 0 2006.201.21:16:30.19#ibcon#read 5, iclass 27, count 0 2006.201.21:16:30.19#ibcon#about to read 6, iclass 27, count 0 2006.201.21:16:30.19#ibcon#read 6, iclass 27, count 0 2006.201.21:16:30.19#ibcon#end of sib2, iclass 27, count 0 2006.201.21:16:30.19#ibcon#*mode == 0, iclass 27, count 0 2006.201.21:16:30.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.21:16:30.19#ibcon#[25=USB\r\n] 2006.201.21:16:30.19#ibcon#*before write, iclass 27, count 0 2006.201.21:16:30.19#ibcon#enter sib2, iclass 27, count 0 2006.201.21:16:30.19#ibcon#flushed, iclass 27, count 0 2006.201.21:16:30.19#ibcon#about to write, iclass 27, count 0 2006.201.21:16:30.19#ibcon#wrote, iclass 27, count 0 2006.201.21:16:30.19#ibcon#about to read 3, iclass 27, count 0 2006.201.21:16:30.22#ibcon#read 3, iclass 27, count 0 2006.201.21:16:30.22#ibcon#about to read 4, iclass 27, count 0 2006.201.21:16:30.22#ibcon#read 4, iclass 27, count 0 2006.201.21:16:30.22#ibcon#about to read 5, iclass 27, count 0 2006.201.21:16:30.22#ibcon#read 5, iclass 27, count 0 2006.201.21:16:30.22#ibcon#about to read 6, iclass 27, count 0 2006.201.21:16:30.22#ibcon#read 6, iclass 27, count 0 2006.201.21:16:30.22#ibcon#end of sib2, iclass 27, count 0 2006.201.21:16:30.22#ibcon#*after write, iclass 27, count 0 2006.201.21:16:30.22#ibcon#*before return 0, iclass 27, count 0 2006.201.21:16:30.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:30.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:30.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.21:16:30.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.21:16:30.22$vck44/valo=5,734.99 2006.201.21:16:30.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.21:16:30.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.21:16:30.22#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:30.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:30.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:30.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:30.22#ibcon#enter wrdev, iclass 29, count 0 2006.201.21:16:30.22#ibcon#first serial, iclass 29, count 0 2006.201.21:16:30.22#ibcon#enter sib2, iclass 29, count 0 2006.201.21:16:30.22#ibcon#flushed, iclass 29, count 0 2006.201.21:16:30.22#ibcon#about to write, iclass 29, count 0 2006.201.21:16:30.22#ibcon#wrote, iclass 29, count 0 2006.201.21:16:30.22#ibcon#about to read 3, iclass 29, count 0 2006.201.21:16:30.24#ibcon#read 3, iclass 29, count 0 2006.201.21:16:30.24#ibcon#about to read 4, iclass 29, count 0 2006.201.21:16:30.24#ibcon#read 4, iclass 29, count 0 2006.201.21:16:30.24#ibcon#about to read 5, iclass 29, count 0 2006.201.21:16:30.24#ibcon#read 5, iclass 29, count 0 2006.201.21:16:30.24#ibcon#about to read 6, iclass 29, count 0 2006.201.21:16:30.24#ibcon#read 6, iclass 29, count 0 2006.201.21:16:30.24#ibcon#end of sib2, iclass 29, count 0 2006.201.21:16:30.24#ibcon#*mode == 0, iclass 29, count 0 2006.201.21:16:30.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.21:16:30.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.21:16:30.24#ibcon#*before write, iclass 29, count 0 2006.201.21:16:30.24#ibcon#enter sib2, iclass 29, count 0 2006.201.21:16:30.24#ibcon#flushed, iclass 29, count 0 2006.201.21:16:30.24#ibcon#about to write, iclass 29, count 0 2006.201.21:16:30.24#ibcon#wrote, iclass 29, count 0 2006.201.21:16:30.24#ibcon#about to read 3, iclass 29, count 0 2006.201.21:16:30.28#ibcon#read 3, iclass 29, count 0 2006.201.21:16:30.28#ibcon#about to read 4, iclass 29, count 0 2006.201.21:16:30.28#ibcon#read 4, iclass 29, count 0 2006.201.21:16:30.28#ibcon#about to read 5, iclass 29, count 0 2006.201.21:16:30.28#ibcon#read 5, iclass 29, count 0 2006.201.21:16:30.28#ibcon#about to read 6, iclass 29, count 0 2006.201.21:16:30.28#ibcon#read 6, iclass 29, count 0 2006.201.21:16:30.28#ibcon#end of sib2, iclass 29, count 0 2006.201.21:16:30.28#ibcon#*after write, iclass 29, count 0 2006.201.21:16:30.28#ibcon#*before return 0, iclass 29, count 0 2006.201.21:16:30.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:30.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:30.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.21:16:30.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.21:16:30.28$vck44/va=5,4 2006.201.21:16:30.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.21:16:30.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.21:16:30.28#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:30.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:30.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:30.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:30.34#ibcon#enter wrdev, iclass 31, count 2 2006.201.21:16:30.34#ibcon#first serial, iclass 31, count 2 2006.201.21:16:30.34#ibcon#enter sib2, iclass 31, count 2 2006.201.21:16:30.34#ibcon#flushed, iclass 31, count 2 2006.201.21:16:30.34#ibcon#about to write, iclass 31, count 2 2006.201.21:16:30.34#ibcon#wrote, iclass 31, count 2 2006.201.21:16:30.34#ibcon#about to read 3, iclass 31, count 2 2006.201.21:16:30.36#ibcon#read 3, iclass 31, count 2 2006.201.21:16:30.36#ibcon#about to read 4, iclass 31, count 2 2006.201.21:16:30.36#ibcon#read 4, iclass 31, count 2 2006.201.21:16:30.36#ibcon#about to read 5, iclass 31, count 2 2006.201.21:16:30.36#ibcon#read 5, iclass 31, count 2 2006.201.21:16:30.36#ibcon#about to read 6, iclass 31, count 2 2006.201.21:16:30.36#ibcon#read 6, iclass 31, count 2 2006.201.21:16:30.36#ibcon#end of sib2, iclass 31, count 2 2006.201.21:16:30.36#ibcon#*mode == 0, iclass 31, count 2 2006.201.21:16:30.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.21:16:30.36#ibcon#[25=AT05-04\r\n] 2006.201.21:16:30.36#ibcon#*before write, iclass 31, count 2 2006.201.21:16:30.36#ibcon#enter sib2, iclass 31, count 2 2006.201.21:16:30.36#ibcon#flushed, iclass 31, count 2 2006.201.21:16:30.36#ibcon#about to write, iclass 31, count 2 2006.201.21:16:30.36#ibcon#wrote, iclass 31, count 2 2006.201.21:16:30.36#ibcon#about to read 3, iclass 31, count 2 2006.201.21:16:30.39#ibcon#read 3, iclass 31, count 2 2006.201.21:16:30.39#ibcon#about to read 4, iclass 31, count 2 2006.201.21:16:30.39#ibcon#read 4, iclass 31, count 2 2006.201.21:16:30.39#ibcon#about to read 5, iclass 31, count 2 2006.201.21:16:30.39#ibcon#read 5, iclass 31, count 2 2006.201.21:16:30.39#ibcon#about to read 6, iclass 31, count 2 2006.201.21:16:30.39#ibcon#read 6, iclass 31, count 2 2006.201.21:16:30.39#ibcon#end of sib2, iclass 31, count 2 2006.201.21:16:30.39#ibcon#*after write, iclass 31, count 2 2006.201.21:16:30.39#ibcon#*before return 0, iclass 31, count 2 2006.201.21:16:30.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:30.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:30.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.21:16:30.39#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:30.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:30.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:30.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:30.51#ibcon#enter wrdev, iclass 31, count 0 2006.201.21:16:30.51#ibcon#first serial, iclass 31, count 0 2006.201.21:16:30.51#ibcon#enter sib2, iclass 31, count 0 2006.201.21:16:30.51#ibcon#flushed, iclass 31, count 0 2006.201.21:16:30.51#ibcon#about to write, iclass 31, count 0 2006.201.21:16:30.51#ibcon#wrote, iclass 31, count 0 2006.201.21:16:30.51#ibcon#about to read 3, iclass 31, count 0 2006.201.21:16:30.53#ibcon#read 3, iclass 31, count 0 2006.201.21:16:30.53#ibcon#about to read 4, iclass 31, count 0 2006.201.21:16:30.53#ibcon#read 4, iclass 31, count 0 2006.201.21:16:30.53#ibcon#about to read 5, iclass 31, count 0 2006.201.21:16:30.53#ibcon#read 5, iclass 31, count 0 2006.201.21:16:30.53#ibcon#about to read 6, iclass 31, count 0 2006.201.21:16:30.53#ibcon#read 6, iclass 31, count 0 2006.201.21:16:30.53#ibcon#end of sib2, iclass 31, count 0 2006.201.21:16:30.53#ibcon#*mode == 0, iclass 31, count 0 2006.201.21:16:30.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.21:16:30.53#ibcon#[25=USB\r\n] 2006.201.21:16:30.53#ibcon#*before write, iclass 31, count 0 2006.201.21:16:30.53#ibcon#enter sib2, iclass 31, count 0 2006.201.21:16:30.53#ibcon#flushed, iclass 31, count 0 2006.201.21:16:30.53#ibcon#about to write, iclass 31, count 0 2006.201.21:16:30.53#ibcon#wrote, iclass 31, count 0 2006.201.21:16:30.53#ibcon#about to read 3, iclass 31, count 0 2006.201.21:16:30.56#ibcon#read 3, iclass 31, count 0 2006.201.21:16:30.56#ibcon#about to read 4, iclass 31, count 0 2006.201.21:16:30.56#ibcon#read 4, iclass 31, count 0 2006.201.21:16:30.56#ibcon#about to read 5, iclass 31, count 0 2006.201.21:16:30.56#ibcon#read 5, iclass 31, count 0 2006.201.21:16:30.56#ibcon#about to read 6, iclass 31, count 0 2006.201.21:16:30.56#ibcon#read 6, iclass 31, count 0 2006.201.21:16:30.56#ibcon#end of sib2, iclass 31, count 0 2006.201.21:16:30.56#ibcon#*after write, iclass 31, count 0 2006.201.21:16:30.56#ibcon#*before return 0, iclass 31, count 0 2006.201.21:16:30.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:30.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:30.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.21:16:30.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.21:16:30.56$vck44/valo=6,814.99 2006.201.21:16:30.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.21:16:30.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.21:16:30.56#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:30.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:30.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:30.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:30.56#ibcon#enter wrdev, iclass 33, count 0 2006.201.21:16:30.56#ibcon#first serial, iclass 33, count 0 2006.201.21:16:30.56#ibcon#enter sib2, iclass 33, count 0 2006.201.21:16:30.56#ibcon#flushed, iclass 33, count 0 2006.201.21:16:30.56#ibcon#about to write, iclass 33, count 0 2006.201.21:16:30.56#ibcon#wrote, iclass 33, count 0 2006.201.21:16:30.56#ibcon#about to read 3, iclass 33, count 0 2006.201.21:16:30.58#ibcon#read 3, iclass 33, count 0 2006.201.21:16:30.58#ibcon#about to read 4, iclass 33, count 0 2006.201.21:16:30.58#ibcon#read 4, iclass 33, count 0 2006.201.21:16:30.58#ibcon#about to read 5, iclass 33, count 0 2006.201.21:16:30.58#ibcon#read 5, iclass 33, count 0 2006.201.21:16:30.58#ibcon#about to read 6, iclass 33, count 0 2006.201.21:16:30.58#ibcon#read 6, iclass 33, count 0 2006.201.21:16:30.58#ibcon#end of sib2, iclass 33, count 0 2006.201.21:16:30.58#ibcon#*mode == 0, iclass 33, count 0 2006.201.21:16:30.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.21:16:30.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.21:16:30.58#ibcon#*before write, iclass 33, count 0 2006.201.21:16:30.58#ibcon#enter sib2, iclass 33, count 0 2006.201.21:16:30.58#ibcon#flushed, iclass 33, count 0 2006.201.21:16:30.58#ibcon#about to write, iclass 33, count 0 2006.201.21:16:30.58#ibcon#wrote, iclass 33, count 0 2006.201.21:16:30.58#ibcon#about to read 3, iclass 33, count 0 2006.201.21:16:30.62#ibcon#read 3, iclass 33, count 0 2006.201.21:16:30.62#ibcon#about to read 4, iclass 33, count 0 2006.201.21:16:30.62#ibcon#read 4, iclass 33, count 0 2006.201.21:16:30.62#ibcon#about to read 5, iclass 33, count 0 2006.201.21:16:30.62#ibcon#read 5, iclass 33, count 0 2006.201.21:16:30.62#ibcon#about to read 6, iclass 33, count 0 2006.201.21:16:30.62#ibcon#read 6, iclass 33, count 0 2006.201.21:16:30.62#ibcon#end of sib2, iclass 33, count 0 2006.201.21:16:30.62#ibcon#*after write, iclass 33, count 0 2006.201.21:16:30.62#ibcon#*before return 0, iclass 33, count 0 2006.201.21:16:30.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:30.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:30.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.21:16:30.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.21:16:30.62$vck44/va=6,5 2006.201.21:16:30.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.21:16:30.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.21:16:30.62#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:30.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:30.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:30.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:30.68#ibcon#enter wrdev, iclass 35, count 2 2006.201.21:16:30.68#ibcon#first serial, iclass 35, count 2 2006.201.21:16:30.68#ibcon#enter sib2, iclass 35, count 2 2006.201.21:16:30.68#ibcon#flushed, iclass 35, count 2 2006.201.21:16:30.68#ibcon#about to write, iclass 35, count 2 2006.201.21:16:30.68#ibcon#wrote, iclass 35, count 2 2006.201.21:16:30.68#ibcon#about to read 3, iclass 35, count 2 2006.201.21:16:30.70#ibcon#read 3, iclass 35, count 2 2006.201.21:16:30.70#ibcon#about to read 4, iclass 35, count 2 2006.201.21:16:30.70#ibcon#read 4, iclass 35, count 2 2006.201.21:16:30.70#ibcon#about to read 5, iclass 35, count 2 2006.201.21:16:30.70#ibcon#read 5, iclass 35, count 2 2006.201.21:16:30.70#ibcon#about to read 6, iclass 35, count 2 2006.201.21:16:30.70#ibcon#read 6, iclass 35, count 2 2006.201.21:16:30.70#ibcon#end of sib2, iclass 35, count 2 2006.201.21:16:30.70#ibcon#*mode == 0, iclass 35, count 2 2006.201.21:16:30.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.21:16:30.70#ibcon#[25=AT06-05\r\n] 2006.201.21:16:30.70#ibcon#*before write, iclass 35, count 2 2006.201.21:16:30.70#ibcon#enter sib2, iclass 35, count 2 2006.201.21:16:30.70#ibcon#flushed, iclass 35, count 2 2006.201.21:16:30.70#ibcon#about to write, iclass 35, count 2 2006.201.21:16:30.70#ibcon#wrote, iclass 35, count 2 2006.201.21:16:30.70#ibcon#about to read 3, iclass 35, count 2 2006.201.21:16:30.73#ibcon#read 3, iclass 35, count 2 2006.201.21:16:30.73#ibcon#about to read 4, iclass 35, count 2 2006.201.21:16:30.73#ibcon#read 4, iclass 35, count 2 2006.201.21:16:30.73#ibcon#about to read 5, iclass 35, count 2 2006.201.21:16:30.73#ibcon#read 5, iclass 35, count 2 2006.201.21:16:30.73#ibcon#about to read 6, iclass 35, count 2 2006.201.21:16:30.73#ibcon#read 6, iclass 35, count 2 2006.201.21:16:30.73#ibcon#end of sib2, iclass 35, count 2 2006.201.21:16:30.73#ibcon#*after write, iclass 35, count 2 2006.201.21:16:30.73#ibcon#*before return 0, iclass 35, count 2 2006.201.21:16:30.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:30.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:30.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.21:16:30.73#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:30.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:30.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:30.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:30.85#ibcon#enter wrdev, iclass 35, count 0 2006.201.21:16:30.85#ibcon#first serial, iclass 35, count 0 2006.201.21:16:30.85#ibcon#enter sib2, iclass 35, count 0 2006.201.21:16:30.85#ibcon#flushed, iclass 35, count 0 2006.201.21:16:30.85#ibcon#about to write, iclass 35, count 0 2006.201.21:16:30.85#ibcon#wrote, iclass 35, count 0 2006.201.21:16:30.85#ibcon#about to read 3, iclass 35, count 0 2006.201.21:16:30.87#ibcon#read 3, iclass 35, count 0 2006.201.21:16:30.87#ibcon#about to read 4, iclass 35, count 0 2006.201.21:16:30.87#ibcon#read 4, iclass 35, count 0 2006.201.21:16:30.87#ibcon#about to read 5, iclass 35, count 0 2006.201.21:16:30.87#ibcon#read 5, iclass 35, count 0 2006.201.21:16:30.87#ibcon#about to read 6, iclass 35, count 0 2006.201.21:16:30.87#ibcon#read 6, iclass 35, count 0 2006.201.21:16:30.87#ibcon#end of sib2, iclass 35, count 0 2006.201.21:16:30.87#ibcon#*mode == 0, iclass 35, count 0 2006.201.21:16:30.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.21:16:30.87#ibcon#[25=USB\r\n] 2006.201.21:16:30.87#ibcon#*before write, iclass 35, count 0 2006.201.21:16:30.87#ibcon#enter sib2, iclass 35, count 0 2006.201.21:16:30.87#ibcon#flushed, iclass 35, count 0 2006.201.21:16:30.87#ibcon#about to write, iclass 35, count 0 2006.201.21:16:30.87#ibcon#wrote, iclass 35, count 0 2006.201.21:16:30.87#ibcon#about to read 3, iclass 35, count 0 2006.201.21:16:30.90#ibcon#read 3, iclass 35, count 0 2006.201.21:16:30.90#ibcon#about to read 4, iclass 35, count 0 2006.201.21:16:30.90#ibcon#read 4, iclass 35, count 0 2006.201.21:16:30.90#ibcon#about to read 5, iclass 35, count 0 2006.201.21:16:30.90#ibcon#read 5, iclass 35, count 0 2006.201.21:16:30.90#ibcon#about to read 6, iclass 35, count 0 2006.201.21:16:30.90#ibcon#read 6, iclass 35, count 0 2006.201.21:16:30.90#ibcon#end of sib2, iclass 35, count 0 2006.201.21:16:30.90#ibcon#*after write, iclass 35, count 0 2006.201.21:16:30.90#ibcon#*before return 0, iclass 35, count 0 2006.201.21:16:30.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:30.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:30.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.21:16:30.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.21:16:30.90$vck44/valo=7,864.99 2006.201.21:16:30.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.21:16:30.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.21:16:30.90#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:30.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:30.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:30.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:30.90#ibcon#enter wrdev, iclass 37, count 0 2006.201.21:16:30.90#ibcon#first serial, iclass 37, count 0 2006.201.21:16:30.90#ibcon#enter sib2, iclass 37, count 0 2006.201.21:16:30.90#ibcon#flushed, iclass 37, count 0 2006.201.21:16:30.90#ibcon#about to write, iclass 37, count 0 2006.201.21:16:30.90#ibcon#wrote, iclass 37, count 0 2006.201.21:16:30.90#ibcon#about to read 3, iclass 37, count 0 2006.201.21:16:30.92#ibcon#read 3, iclass 37, count 0 2006.201.21:16:30.92#ibcon#about to read 4, iclass 37, count 0 2006.201.21:16:30.92#ibcon#read 4, iclass 37, count 0 2006.201.21:16:30.92#ibcon#about to read 5, iclass 37, count 0 2006.201.21:16:30.92#ibcon#read 5, iclass 37, count 0 2006.201.21:16:30.92#ibcon#about to read 6, iclass 37, count 0 2006.201.21:16:30.92#ibcon#read 6, iclass 37, count 0 2006.201.21:16:30.92#ibcon#end of sib2, iclass 37, count 0 2006.201.21:16:30.92#ibcon#*mode == 0, iclass 37, count 0 2006.201.21:16:30.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.21:16:30.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.21:16:30.92#ibcon#*before write, iclass 37, count 0 2006.201.21:16:30.92#ibcon#enter sib2, iclass 37, count 0 2006.201.21:16:30.92#ibcon#flushed, iclass 37, count 0 2006.201.21:16:30.92#ibcon#about to write, iclass 37, count 0 2006.201.21:16:30.92#ibcon#wrote, iclass 37, count 0 2006.201.21:16:30.92#ibcon#about to read 3, iclass 37, count 0 2006.201.21:16:30.96#ibcon#read 3, iclass 37, count 0 2006.201.21:16:30.96#ibcon#about to read 4, iclass 37, count 0 2006.201.21:16:30.96#ibcon#read 4, iclass 37, count 0 2006.201.21:16:30.96#ibcon#about to read 5, iclass 37, count 0 2006.201.21:16:30.96#ibcon#read 5, iclass 37, count 0 2006.201.21:16:30.96#ibcon#about to read 6, iclass 37, count 0 2006.201.21:16:30.96#ibcon#read 6, iclass 37, count 0 2006.201.21:16:30.96#ibcon#end of sib2, iclass 37, count 0 2006.201.21:16:30.96#ibcon#*after write, iclass 37, count 0 2006.201.21:16:30.96#ibcon#*before return 0, iclass 37, count 0 2006.201.21:16:30.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:30.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:30.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.21:16:30.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.21:16:30.96$vck44/va=7,5 2006.201.21:16:30.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.21:16:30.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.21:16:30.96#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:30.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:31.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:31.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:31.02#ibcon#enter wrdev, iclass 39, count 2 2006.201.21:16:31.02#ibcon#first serial, iclass 39, count 2 2006.201.21:16:31.02#ibcon#enter sib2, iclass 39, count 2 2006.201.21:16:31.02#ibcon#flushed, iclass 39, count 2 2006.201.21:16:31.02#ibcon#about to write, iclass 39, count 2 2006.201.21:16:31.02#ibcon#wrote, iclass 39, count 2 2006.201.21:16:31.02#ibcon#about to read 3, iclass 39, count 2 2006.201.21:16:31.04#ibcon#read 3, iclass 39, count 2 2006.201.21:16:31.04#ibcon#about to read 4, iclass 39, count 2 2006.201.21:16:31.04#ibcon#read 4, iclass 39, count 2 2006.201.21:16:31.04#ibcon#about to read 5, iclass 39, count 2 2006.201.21:16:31.04#ibcon#read 5, iclass 39, count 2 2006.201.21:16:31.04#ibcon#about to read 6, iclass 39, count 2 2006.201.21:16:31.04#ibcon#read 6, iclass 39, count 2 2006.201.21:16:31.04#ibcon#end of sib2, iclass 39, count 2 2006.201.21:16:31.04#ibcon#*mode == 0, iclass 39, count 2 2006.201.21:16:31.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.21:16:31.04#ibcon#[25=AT07-05\r\n] 2006.201.21:16:31.04#ibcon#*before write, iclass 39, count 2 2006.201.21:16:31.04#ibcon#enter sib2, iclass 39, count 2 2006.201.21:16:31.04#ibcon#flushed, iclass 39, count 2 2006.201.21:16:31.04#ibcon#about to write, iclass 39, count 2 2006.201.21:16:31.04#ibcon#wrote, iclass 39, count 2 2006.201.21:16:31.04#ibcon#about to read 3, iclass 39, count 2 2006.201.21:16:31.07#ibcon#read 3, iclass 39, count 2 2006.201.21:16:31.07#ibcon#about to read 4, iclass 39, count 2 2006.201.21:16:31.07#ibcon#read 4, iclass 39, count 2 2006.201.21:16:31.07#ibcon#about to read 5, iclass 39, count 2 2006.201.21:16:31.07#ibcon#read 5, iclass 39, count 2 2006.201.21:16:31.07#ibcon#about to read 6, iclass 39, count 2 2006.201.21:16:31.07#ibcon#read 6, iclass 39, count 2 2006.201.21:16:31.07#ibcon#end of sib2, iclass 39, count 2 2006.201.21:16:31.07#ibcon#*after write, iclass 39, count 2 2006.201.21:16:31.07#ibcon#*before return 0, iclass 39, count 2 2006.201.21:16:31.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:31.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:31.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.21:16:31.07#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:31.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:31.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:31.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:31.19#ibcon#enter wrdev, iclass 39, count 0 2006.201.21:16:31.19#ibcon#first serial, iclass 39, count 0 2006.201.21:16:31.19#ibcon#enter sib2, iclass 39, count 0 2006.201.21:16:31.19#ibcon#flushed, iclass 39, count 0 2006.201.21:16:31.19#ibcon#about to write, iclass 39, count 0 2006.201.21:16:31.19#ibcon#wrote, iclass 39, count 0 2006.201.21:16:31.19#ibcon#about to read 3, iclass 39, count 0 2006.201.21:16:31.21#ibcon#read 3, iclass 39, count 0 2006.201.21:16:31.21#ibcon#about to read 4, iclass 39, count 0 2006.201.21:16:31.21#ibcon#read 4, iclass 39, count 0 2006.201.21:16:31.21#ibcon#about to read 5, iclass 39, count 0 2006.201.21:16:31.21#ibcon#read 5, iclass 39, count 0 2006.201.21:16:31.21#ibcon#about to read 6, iclass 39, count 0 2006.201.21:16:31.21#ibcon#read 6, iclass 39, count 0 2006.201.21:16:31.21#ibcon#end of sib2, iclass 39, count 0 2006.201.21:16:31.21#ibcon#*mode == 0, iclass 39, count 0 2006.201.21:16:31.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.21:16:31.21#ibcon#[25=USB\r\n] 2006.201.21:16:31.21#ibcon#*before write, iclass 39, count 0 2006.201.21:16:31.21#ibcon#enter sib2, iclass 39, count 0 2006.201.21:16:31.21#ibcon#flushed, iclass 39, count 0 2006.201.21:16:31.21#ibcon#about to write, iclass 39, count 0 2006.201.21:16:31.21#ibcon#wrote, iclass 39, count 0 2006.201.21:16:31.21#ibcon#about to read 3, iclass 39, count 0 2006.201.21:16:31.24#ibcon#read 3, iclass 39, count 0 2006.201.21:16:31.24#ibcon#about to read 4, iclass 39, count 0 2006.201.21:16:31.24#ibcon#read 4, iclass 39, count 0 2006.201.21:16:31.24#ibcon#about to read 5, iclass 39, count 0 2006.201.21:16:31.24#ibcon#read 5, iclass 39, count 0 2006.201.21:16:31.24#ibcon#about to read 6, iclass 39, count 0 2006.201.21:16:31.24#ibcon#read 6, iclass 39, count 0 2006.201.21:16:31.24#ibcon#end of sib2, iclass 39, count 0 2006.201.21:16:31.24#ibcon#*after write, iclass 39, count 0 2006.201.21:16:31.24#ibcon#*before return 0, iclass 39, count 0 2006.201.21:16:31.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:31.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:31.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.21:16:31.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.21:16:31.24$vck44/valo=8,884.99 2006.201.21:16:31.24#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.21:16:31.24#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.21:16:31.24#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:31.24#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:31.24#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:31.24#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:31.24#ibcon#enter wrdev, iclass 2, count 0 2006.201.21:16:31.24#ibcon#first serial, iclass 2, count 0 2006.201.21:16:31.24#ibcon#enter sib2, iclass 2, count 0 2006.201.21:16:31.24#ibcon#flushed, iclass 2, count 0 2006.201.21:16:31.24#ibcon#about to write, iclass 2, count 0 2006.201.21:16:31.24#ibcon#wrote, iclass 2, count 0 2006.201.21:16:31.24#ibcon#about to read 3, iclass 2, count 0 2006.201.21:16:31.26#ibcon#read 3, iclass 2, count 0 2006.201.21:16:31.26#ibcon#about to read 4, iclass 2, count 0 2006.201.21:16:31.26#ibcon#read 4, iclass 2, count 0 2006.201.21:16:31.26#ibcon#about to read 5, iclass 2, count 0 2006.201.21:16:31.26#ibcon#read 5, iclass 2, count 0 2006.201.21:16:31.26#ibcon#about to read 6, iclass 2, count 0 2006.201.21:16:31.26#ibcon#read 6, iclass 2, count 0 2006.201.21:16:31.26#ibcon#end of sib2, iclass 2, count 0 2006.201.21:16:31.26#ibcon#*mode == 0, iclass 2, count 0 2006.201.21:16:31.26#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.21:16:31.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.21:16:31.26#ibcon#*before write, iclass 2, count 0 2006.201.21:16:31.26#ibcon#enter sib2, iclass 2, count 0 2006.201.21:16:31.26#ibcon#flushed, iclass 2, count 0 2006.201.21:16:31.26#ibcon#about to write, iclass 2, count 0 2006.201.21:16:31.26#ibcon#wrote, iclass 2, count 0 2006.201.21:16:31.26#ibcon#about to read 3, iclass 2, count 0 2006.201.21:16:31.30#ibcon#read 3, iclass 2, count 0 2006.201.21:16:31.30#ibcon#about to read 4, iclass 2, count 0 2006.201.21:16:31.30#ibcon#read 4, iclass 2, count 0 2006.201.21:16:31.30#ibcon#about to read 5, iclass 2, count 0 2006.201.21:16:31.30#ibcon#read 5, iclass 2, count 0 2006.201.21:16:31.30#ibcon#about to read 6, iclass 2, count 0 2006.201.21:16:31.30#ibcon#read 6, iclass 2, count 0 2006.201.21:16:31.30#ibcon#end of sib2, iclass 2, count 0 2006.201.21:16:31.30#ibcon#*after write, iclass 2, count 0 2006.201.21:16:31.30#ibcon#*before return 0, iclass 2, count 0 2006.201.21:16:31.30#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:31.30#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:31.30#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.21:16:31.30#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.21:16:31.30$vck44/va=8,4 2006.201.21:16:31.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.21:16:31.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.21:16:31.30#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:31.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:31.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:31.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:31.36#ibcon#enter wrdev, iclass 5, count 2 2006.201.21:16:31.36#ibcon#first serial, iclass 5, count 2 2006.201.21:16:31.36#ibcon#enter sib2, iclass 5, count 2 2006.201.21:16:31.36#ibcon#flushed, iclass 5, count 2 2006.201.21:16:31.36#ibcon#about to write, iclass 5, count 2 2006.201.21:16:31.36#ibcon#wrote, iclass 5, count 2 2006.201.21:16:31.36#ibcon#about to read 3, iclass 5, count 2 2006.201.21:16:31.38#ibcon#read 3, iclass 5, count 2 2006.201.21:16:31.38#ibcon#about to read 4, iclass 5, count 2 2006.201.21:16:31.38#ibcon#read 4, iclass 5, count 2 2006.201.21:16:31.38#ibcon#about to read 5, iclass 5, count 2 2006.201.21:16:31.38#ibcon#read 5, iclass 5, count 2 2006.201.21:16:31.38#ibcon#about to read 6, iclass 5, count 2 2006.201.21:16:31.38#ibcon#read 6, iclass 5, count 2 2006.201.21:16:31.38#ibcon#end of sib2, iclass 5, count 2 2006.201.21:16:31.38#ibcon#*mode == 0, iclass 5, count 2 2006.201.21:16:31.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.21:16:31.38#ibcon#[25=AT08-04\r\n] 2006.201.21:16:31.38#ibcon#*before write, iclass 5, count 2 2006.201.21:16:31.38#ibcon#enter sib2, iclass 5, count 2 2006.201.21:16:31.38#ibcon#flushed, iclass 5, count 2 2006.201.21:16:31.38#ibcon#about to write, iclass 5, count 2 2006.201.21:16:31.38#ibcon#wrote, iclass 5, count 2 2006.201.21:16:31.38#ibcon#about to read 3, iclass 5, count 2 2006.201.21:16:31.41#ibcon#read 3, iclass 5, count 2 2006.201.21:16:31.41#ibcon#about to read 4, iclass 5, count 2 2006.201.21:16:31.41#ibcon#read 4, iclass 5, count 2 2006.201.21:16:31.41#ibcon#about to read 5, iclass 5, count 2 2006.201.21:16:31.41#ibcon#read 5, iclass 5, count 2 2006.201.21:16:31.41#ibcon#about to read 6, iclass 5, count 2 2006.201.21:16:31.41#ibcon#read 6, iclass 5, count 2 2006.201.21:16:31.41#ibcon#end of sib2, iclass 5, count 2 2006.201.21:16:31.41#ibcon#*after write, iclass 5, count 2 2006.201.21:16:31.41#ibcon#*before return 0, iclass 5, count 2 2006.201.21:16:31.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:31.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:31.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.21:16:31.41#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:31.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:31.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:31.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:31.53#ibcon#enter wrdev, iclass 5, count 0 2006.201.21:16:31.53#ibcon#first serial, iclass 5, count 0 2006.201.21:16:31.53#ibcon#enter sib2, iclass 5, count 0 2006.201.21:16:31.53#ibcon#flushed, iclass 5, count 0 2006.201.21:16:31.53#ibcon#about to write, iclass 5, count 0 2006.201.21:16:31.53#ibcon#wrote, iclass 5, count 0 2006.201.21:16:31.53#ibcon#about to read 3, iclass 5, count 0 2006.201.21:16:31.55#ibcon#read 3, iclass 5, count 0 2006.201.21:16:31.55#ibcon#about to read 4, iclass 5, count 0 2006.201.21:16:31.55#ibcon#read 4, iclass 5, count 0 2006.201.21:16:31.55#ibcon#about to read 5, iclass 5, count 0 2006.201.21:16:31.55#ibcon#read 5, iclass 5, count 0 2006.201.21:16:31.55#ibcon#about to read 6, iclass 5, count 0 2006.201.21:16:31.55#ibcon#read 6, iclass 5, count 0 2006.201.21:16:31.55#ibcon#end of sib2, iclass 5, count 0 2006.201.21:16:31.55#ibcon#*mode == 0, iclass 5, count 0 2006.201.21:16:31.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.21:16:31.55#ibcon#[25=USB\r\n] 2006.201.21:16:31.55#ibcon#*before write, iclass 5, count 0 2006.201.21:16:31.55#ibcon#enter sib2, iclass 5, count 0 2006.201.21:16:31.55#ibcon#flushed, iclass 5, count 0 2006.201.21:16:31.55#ibcon#about to write, iclass 5, count 0 2006.201.21:16:31.55#ibcon#wrote, iclass 5, count 0 2006.201.21:16:31.55#ibcon#about to read 3, iclass 5, count 0 2006.201.21:16:31.58#ibcon#read 3, iclass 5, count 0 2006.201.21:16:31.58#ibcon#about to read 4, iclass 5, count 0 2006.201.21:16:31.58#ibcon#read 4, iclass 5, count 0 2006.201.21:16:31.58#ibcon#about to read 5, iclass 5, count 0 2006.201.21:16:31.58#ibcon#read 5, iclass 5, count 0 2006.201.21:16:31.58#ibcon#about to read 6, iclass 5, count 0 2006.201.21:16:31.58#ibcon#read 6, iclass 5, count 0 2006.201.21:16:31.58#ibcon#end of sib2, iclass 5, count 0 2006.201.21:16:31.58#ibcon#*after write, iclass 5, count 0 2006.201.21:16:31.58#ibcon#*before return 0, iclass 5, count 0 2006.201.21:16:31.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:31.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:31.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.21:16:31.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.21:16:31.58$vck44/vblo=1,629.99 2006.201.21:16:31.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.21:16:31.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.21:16:31.58#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:31.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:31.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:31.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:31.58#ibcon#enter wrdev, iclass 7, count 0 2006.201.21:16:31.58#ibcon#first serial, iclass 7, count 0 2006.201.21:16:31.58#ibcon#enter sib2, iclass 7, count 0 2006.201.21:16:31.58#ibcon#flushed, iclass 7, count 0 2006.201.21:16:31.58#ibcon#about to write, iclass 7, count 0 2006.201.21:16:31.58#ibcon#wrote, iclass 7, count 0 2006.201.21:16:31.58#ibcon#about to read 3, iclass 7, count 0 2006.201.21:16:31.60#ibcon#read 3, iclass 7, count 0 2006.201.21:16:31.60#ibcon#about to read 4, iclass 7, count 0 2006.201.21:16:31.60#ibcon#read 4, iclass 7, count 0 2006.201.21:16:31.60#ibcon#about to read 5, iclass 7, count 0 2006.201.21:16:31.60#ibcon#read 5, iclass 7, count 0 2006.201.21:16:31.60#ibcon#about to read 6, iclass 7, count 0 2006.201.21:16:31.60#ibcon#read 6, iclass 7, count 0 2006.201.21:16:31.60#ibcon#end of sib2, iclass 7, count 0 2006.201.21:16:31.60#ibcon#*mode == 0, iclass 7, count 0 2006.201.21:16:31.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.21:16:31.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.21:16:31.60#ibcon#*before write, iclass 7, count 0 2006.201.21:16:31.60#ibcon#enter sib2, iclass 7, count 0 2006.201.21:16:31.60#ibcon#flushed, iclass 7, count 0 2006.201.21:16:31.60#ibcon#about to write, iclass 7, count 0 2006.201.21:16:31.60#ibcon#wrote, iclass 7, count 0 2006.201.21:16:31.60#ibcon#about to read 3, iclass 7, count 0 2006.201.21:16:31.65#ibcon#read 3, iclass 7, count 0 2006.201.21:16:31.65#ibcon#about to read 4, iclass 7, count 0 2006.201.21:16:31.65#ibcon#read 4, iclass 7, count 0 2006.201.21:16:31.65#ibcon#about to read 5, iclass 7, count 0 2006.201.21:16:31.65#ibcon#read 5, iclass 7, count 0 2006.201.21:16:31.65#ibcon#about to read 6, iclass 7, count 0 2006.201.21:16:31.65#ibcon#read 6, iclass 7, count 0 2006.201.21:16:31.65#ibcon#end of sib2, iclass 7, count 0 2006.201.21:16:31.65#ibcon#*after write, iclass 7, count 0 2006.201.21:16:31.65#ibcon#*before return 0, iclass 7, count 0 2006.201.21:16:31.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:31.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:31.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.21:16:31.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.21:16:31.65$vck44/vb=1,4 2006.201.21:16:31.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.21:16:31.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.21:16:31.65#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:31.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:16:31.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:16:31.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:16:31.65#ibcon#enter wrdev, iclass 11, count 2 2006.201.21:16:31.65#ibcon#first serial, iclass 11, count 2 2006.201.21:16:31.65#ibcon#enter sib2, iclass 11, count 2 2006.201.21:16:31.65#ibcon#flushed, iclass 11, count 2 2006.201.21:16:31.65#ibcon#about to write, iclass 11, count 2 2006.201.21:16:31.65#ibcon#wrote, iclass 11, count 2 2006.201.21:16:31.65#ibcon#about to read 3, iclass 11, count 2 2006.201.21:16:31.67#ibcon#read 3, iclass 11, count 2 2006.201.21:16:31.67#ibcon#about to read 4, iclass 11, count 2 2006.201.21:16:31.67#ibcon#read 4, iclass 11, count 2 2006.201.21:16:31.67#ibcon#about to read 5, iclass 11, count 2 2006.201.21:16:31.67#ibcon#read 5, iclass 11, count 2 2006.201.21:16:31.67#ibcon#about to read 6, iclass 11, count 2 2006.201.21:16:31.67#ibcon#read 6, iclass 11, count 2 2006.201.21:16:31.67#ibcon#end of sib2, iclass 11, count 2 2006.201.21:16:31.67#ibcon#*mode == 0, iclass 11, count 2 2006.201.21:16:31.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.21:16:31.67#ibcon#[27=AT01-04\r\n] 2006.201.21:16:31.67#ibcon#*before write, iclass 11, count 2 2006.201.21:16:31.67#ibcon#enter sib2, iclass 11, count 2 2006.201.21:16:31.67#ibcon#flushed, iclass 11, count 2 2006.201.21:16:31.67#ibcon#about to write, iclass 11, count 2 2006.201.21:16:31.67#ibcon#wrote, iclass 11, count 2 2006.201.21:16:31.67#ibcon#about to read 3, iclass 11, count 2 2006.201.21:16:31.70#ibcon#read 3, iclass 11, count 2 2006.201.21:16:31.70#ibcon#about to read 4, iclass 11, count 2 2006.201.21:16:31.70#ibcon#read 4, iclass 11, count 2 2006.201.21:16:31.70#ibcon#about to read 5, iclass 11, count 2 2006.201.21:16:31.70#ibcon#read 5, iclass 11, count 2 2006.201.21:16:31.70#ibcon#about to read 6, iclass 11, count 2 2006.201.21:16:31.70#ibcon#read 6, iclass 11, count 2 2006.201.21:16:31.70#ibcon#end of sib2, iclass 11, count 2 2006.201.21:16:31.70#ibcon#*after write, iclass 11, count 2 2006.201.21:16:31.70#ibcon#*before return 0, iclass 11, count 2 2006.201.21:16:31.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:16:31.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:16:31.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.21:16:31.70#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:31.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:16:31.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:16:31.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:16:31.82#ibcon#enter wrdev, iclass 11, count 0 2006.201.21:16:31.82#ibcon#first serial, iclass 11, count 0 2006.201.21:16:31.82#ibcon#enter sib2, iclass 11, count 0 2006.201.21:16:31.82#ibcon#flushed, iclass 11, count 0 2006.201.21:16:31.82#ibcon#about to write, iclass 11, count 0 2006.201.21:16:31.82#ibcon#wrote, iclass 11, count 0 2006.201.21:16:31.82#ibcon#about to read 3, iclass 11, count 0 2006.201.21:16:31.84#ibcon#read 3, iclass 11, count 0 2006.201.21:16:31.84#ibcon#about to read 4, iclass 11, count 0 2006.201.21:16:31.84#ibcon#read 4, iclass 11, count 0 2006.201.21:16:31.84#ibcon#about to read 5, iclass 11, count 0 2006.201.21:16:31.84#ibcon#read 5, iclass 11, count 0 2006.201.21:16:31.84#ibcon#about to read 6, iclass 11, count 0 2006.201.21:16:31.84#ibcon#read 6, iclass 11, count 0 2006.201.21:16:31.84#ibcon#end of sib2, iclass 11, count 0 2006.201.21:16:31.84#ibcon#*mode == 0, iclass 11, count 0 2006.201.21:16:31.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.21:16:31.84#ibcon#[27=USB\r\n] 2006.201.21:16:31.84#ibcon#*before write, iclass 11, count 0 2006.201.21:16:31.84#ibcon#enter sib2, iclass 11, count 0 2006.201.21:16:31.84#ibcon#flushed, iclass 11, count 0 2006.201.21:16:31.84#ibcon#about to write, iclass 11, count 0 2006.201.21:16:31.84#ibcon#wrote, iclass 11, count 0 2006.201.21:16:31.84#ibcon#about to read 3, iclass 11, count 0 2006.201.21:16:31.87#ibcon#read 3, iclass 11, count 0 2006.201.21:16:31.87#ibcon#about to read 4, iclass 11, count 0 2006.201.21:16:31.87#ibcon#read 4, iclass 11, count 0 2006.201.21:16:31.87#ibcon#about to read 5, iclass 11, count 0 2006.201.21:16:31.87#ibcon#read 5, iclass 11, count 0 2006.201.21:16:31.87#ibcon#about to read 6, iclass 11, count 0 2006.201.21:16:31.87#ibcon#read 6, iclass 11, count 0 2006.201.21:16:31.87#ibcon#end of sib2, iclass 11, count 0 2006.201.21:16:31.87#ibcon#*after write, iclass 11, count 0 2006.201.21:16:31.87#ibcon#*before return 0, iclass 11, count 0 2006.201.21:16:31.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:16:31.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:16:31.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.21:16:31.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.21:16:31.87$vck44/vblo=2,634.99 2006.201.21:16:31.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.21:16:31.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.21:16:31.87#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:31.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:31.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:31.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:31.87#ibcon#enter wrdev, iclass 13, count 0 2006.201.21:16:31.87#ibcon#first serial, iclass 13, count 0 2006.201.21:16:31.87#ibcon#enter sib2, iclass 13, count 0 2006.201.21:16:31.87#ibcon#flushed, iclass 13, count 0 2006.201.21:16:31.87#ibcon#about to write, iclass 13, count 0 2006.201.21:16:31.87#ibcon#wrote, iclass 13, count 0 2006.201.21:16:31.87#ibcon#about to read 3, iclass 13, count 0 2006.201.21:16:31.89#ibcon#read 3, iclass 13, count 0 2006.201.21:16:31.89#ibcon#about to read 4, iclass 13, count 0 2006.201.21:16:31.89#ibcon#read 4, iclass 13, count 0 2006.201.21:16:31.89#ibcon#about to read 5, iclass 13, count 0 2006.201.21:16:31.89#ibcon#read 5, iclass 13, count 0 2006.201.21:16:31.89#ibcon#about to read 6, iclass 13, count 0 2006.201.21:16:31.89#ibcon#read 6, iclass 13, count 0 2006.201.21:16:31.89#ibcon#end of sib2, iclass 13, count 0 2006.201.21:16:31.89#ibcon#*mode == 0, iclass 13, count 0 2006.201.21:16:31.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.21:16:31.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.21:16:31.89#ibcon#*before write, iclass 13, count 0 2006.201.21:16:31.89#ibcon#enter sib2, iclass 13, count 0 2006.201.21:16:31.89#ibcon#flushed, iclass 13, count 0 2006.201.21:16:31.89#ibcon#about to write, iclass 13, count 0 2006.201.21:16:31.89#ibcon#wrote, iclass 13, count 0 2006.201.21:16:31.89#ibcon#about to read 3, iclass 13, count 0 2006.201.21:16:31.93#ibcon#read 3, iclass 13, count 0 2006.201.21:16:31.93#ibcon#about to read 4, iclass 13, count 0 2006.201.21:16:31.93#ibcon#read 4, iclass 13, count 0 2006.201.21:16:31.93#ibcon#about to read 5, iclass 13, count 0 2006.201.21:16:31.93#ibcon#read 5, iclass 13, count 0 2006.201.21:16:31.93#ibcon#about to read 6, iclass 13, count 0 2006.201.21:16:31.93#ibcon#read 6, iclass 13, count 0 2006.201.21:16:31.93#ibcon#end of sib2, iclass 13, count 0 2006.201.21:16:31.93#ibcon#*after write, iclass 13, count 0 2006.201.21:16:31.93#ibcon#*before return 0, iclass 13, count 0 2006.201.21:16:31.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:31.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:16:31.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.21:16:31.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.21:16:31.93$vck44/vb=2,5 2006.201.21:16:31.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.21:16:31.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.21:16:31.93#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:31.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:31.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:31.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:31.99#ibcon#enter wrdev, iclass 15, count 2 2006.201.21:16:31.99#ibcon#first serial, iclass 15, count 2 2006.201.21:16:31.99#ibcon#enter sib2, iclass 15, count 2 2006.201.21:16:31.99#ibcon#flushed, iclass 15, count 2 2006.201.21:16:31.99#ibcon#about to write, iclass 15, count 2 2006.201.21:16:31.99#ibcon#wrote, iclass 15, count 2 2006.201.21:16:31.99#ibcon#about to read 3, iclass 15, count 2 2006.201.21:16:32.01#ibcon#read 3, iclass 15, count 2 2006.201.21:16:32.01#ibcon#about to read 4, iclass 15, count 2 2006.201.21:16:32.01#ibcon#read 4, iclass 15, count 2 2006.201.21:16:32.01#ibcon#about to read 5, iclass 15, count 2 2006.201.21:16:32.01#ibcon#read 5, iclass 15, count 2 2006.201.21:16:32.01#ibcon#about to read 6, iclass 15, count 2 2006.201.21:16:32.01#ibcon#read 6, iclass 15, count 2 2006.201.21:16:32.01#ibcon#end of sib2, iclass 15, count 2 2006.201.21:16:32.01#ibcon#*mode == 0, iclass 15, count 2 2006.201.21:16:32.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.21:16:32.01#ibcon#[27=AT02-05\r\n] 2006.201.21:16:32.01#ibcon#*before write, iclass 15, count 2 2006.201.21:16:32.01#ibcon#enter sib2, iclass 15, count 2 2006.201.21:16:32.01#ibcon#flushed, iclass 15, count 2 2006.201.21:16:32.01#ibcon#about to write, iclass 15, count 2 2006.201.21:16:32.01#ibcon#wrote, iclass 15, count 2 2006.201.21:16:32.01#ibcon#about to read 3, iclass 15, count 2 2006.201.21:16:32.04#ibcon#read 3, iclass 15, count 2 2006.201.21:16:32.04#ibcon#about to read 4, iclass 15, count 2 2006.201.21:16:32.04#ibcon#read 4, iclass 15, count 2 2006.201.21:16:32.04#ibcon#about to read 5, iclass 15, count 2 2006.201.21:16:32.04#ibcon#read 5, iclass 15, count 2 2006.201.21:16:32.04#ibcon#about to read 6, iclass 15, count 2 2006.201.21:16:32.04#ibcon#read 6, iclass 15, count 2 2006.201.21:16:32.04#ibcon#end of sib2, iclass 15, count 2 2006.201.21:16:32.04#ibcon#*after write, iclass 15, count 2 2006.201.21:16:32.04#ibcon#*before return 0, iclass 15, count 2 2006.201.21:16:32.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:32.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:16:32.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.21:16:32.04#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:32.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:32.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:32.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:32.16#ibcon#enter wrdev, iclass 15, count 0 2006.201.21:16:32.16#ibcon#first serial, iclass 15, count 0 2006.201.21:16:32.16#ibcon#enter sib2, iclass 15, count 0 2006.201.21:16:32.16#ibcon#flushed, iclass 15, count 0 2006.201.21:16:32.16#ibcon#about to write, iclass 15, count 0 2006.201.21:16:32.16#ibcon#wrote, iclass 15, count 0 2006.201.21:16:32.16#ibcon#about to read 3, iclass 15, count 0 2006.201.21:16:32.18#ibcon#read 3, iclass 15, count 0 2006.201.21:16:32.18#ibcon#about to read 4, iclass 15, count 0 2006.201.21:16:32.18#ibcon#read 4, iclass 15, count 0 2006.201.21:16:32.18#ibcon#about to read 5, iclass 15, count 0 2006.201.21:16:32.18#ibcon#read 5, iclass 15, count 0 2006.201.21:16:32.18#ibcon#about to read 6, iclass 15, count 0 2006.201.21:16:32.18#ibcon#read 6, iclass 15, count 0 2006.201.21:16:32.18#ibcon#end of sib2, iclass 15, count 0 2006.201.21:16:32.18#ibcon#*mode == 0, iclass 15, count 0 2006.201.21:16:32.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.21:16:32.18#ibcon#[27=USB\r\n] 2006.201.21:16:32.18#ibcon#*before write, iclass 15, count 0 2006.201.21:16:32.18#ibcon#enter sib2, iclass 15, count 0 2006.201.21:16:32.18#ibcon#flushed, iclass 15, count 0 2006.201.21:16:32.18#ibcon#about to write, iclass 15, count 0 2006.201.21:16:32.18#ibcon#wrote, iclass 15, count 0 2006.201.21:16:32.18#ibcon#about to read 3, iclass 15, count 0 2006.201.21:16:32.21#ibcon#read 3, iclass 15, count 0 2006.201.21:16:32.21#ibcon#about to read 4, iclass 15, count 0 2006.201.21:16:32.21#ibcon#read 4, iclass 15, count 0 2006.201.21:16:32.21#ibcon#about to read 5, iclass 15, count 0 2006.201.21:16:32.21#ibcon#read 5, iclass 15, count 0 2006.201.21:16:32.21#ibcon#about to read 6, iclass 15, count 0 2006.201.21:16:32.21#ibcon#read 6, iclass 15, count 0 2006.201.21:16:32.21#ibcon#end of sib2, iclass 15, count 0 2006.201.21:16:32.21#ibcon#*after write, iclass 15, count 0 2006.201.21:16:32.21#ibcon#*before return 0, iclass 15, count 0 2006.201.21:16:32.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:32.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:16:32.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.21:16:32.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.21:16:32.21$vck44/vblo=3,649.99 2006.201.21:16:32.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.21:16:32.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.21:16:32.21#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:32.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:32.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:32.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:32.21#ibcon#enter wrdev, iclass 17, count 0 2006.201.21:16:32.21#ibcon#first serial, iclass 17, count 0 2006.201.21:16:32.21#ibcon#enter sib2, iclass 17, count 0 2006.201.21:16:32.21#ibcon#flushed, iclass 17, count 0 2006.201.21:16:32.21#ibcon#about to write, iclass 17, count 0 2006.201.21:16:32.21#ibcon#wrote, iclass 17, count 0 2006.201.21:16:32.21#ibcon#about to read 3, iclass 17, count 0 2006.201.21:16:32.23#ibcon#read 3, iclass 17, count 0 2006.201.21:16:32.23#ibcon#about to read 4, iclass 17, count 0 2006.201.21:16:32.23#ibcon#read 4, iclass 17, count 0 2006.201.21:16:32.23#ibcon#about to read 5, iclass 17, count 0 2006.201.21:16:32.23#ibcon#read 5, iclass 17, count 0 2006.201.21:16:32.23#ibcon#about to read 6, iclass 17, count 0 2006.201.21:16:32.23#ibcon#read 6, iclass 17, count 0 2006.201.21:16:32.23#ibcon#end of sib2, iclass 17, count 0 2006.201.21:16:32.23#ibcon#*mode == 0, iclass 17, count 0 2006.201.21:16:32.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.21:16:32.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.21:16:32.23#ibcon#*before write, iclass 17, count 0 2006.201.21:16:32.23#ibcon#enter sib2, iclass 17, count 0 2006.201.21:16:32.23#ibcon#flushed, iclass 17, count 0 2006.201.21:16:32.23#ibcon#about to write, iclass 17, count 0 2006.201.21:16:32.23#ibcon#wrote, iclass 17, count 0 2006.201.21:16:32.23#ibcon#about to read 3, iclass 17, count 0 2006.201.21:16:32.28#ibcon#read 3, iclass 17, count 0 2006.201.21:16:32.28#ibcon#about to read 4, iclass 17, count 0 2006.201.21:16:32.28#ibcon#read 4, iclass 17, count 0 2006.201.21:16:32.28#ibcon#about to read 5, iclass 17, count 0 2006.201.21:16:32.28#ibcon#read 5, iclass 17, count 0 2006.201.21:16:32.28#ibcon#about to read 6, iclass 17, count 0 2006.201.21:16:32.28#ibcon#read 6, iclass 17, count 0 2006.201.21:16:32.28#ibcon#end of sib2, iclass 17, count 0 2006.201.21:16:32.28#ibcon#*after write, iclass 17, count 0 2006.201.21:16:32.28#ibcon#*before return 0, iclass 17, count 0 2006.201.21:16:32.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:32.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:16:32.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.21:16:32.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.21:16:32.28$vck44/vb=3,4 2006.201.21:16:32.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.21:16:32.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.21:16:32.28#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:32.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:32.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:32.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:32.33#ibcon#enter wrdev, iclass 19, count 2 2006.201.21:16:32.33#ibcon#first serial, iclass 19, count 2 2006.201.21:16:32.33#ibcon#enter sib2, iclass 19, count 2 2006.201.21:16:32.33#ibcon#flushed, iclass 19, count 2 2006.201.21:16:32.33#ibcon#about to write, iclass 19, count 2 2006.201.21:16:32.33#ibcon#wrote, iclass 19, count 2 2006.201.21:16:32.33#ibcon#about to read 3, iclass 19, count 2 2006.201.21:16:32.35#ibcon#read 3, iclass 19, count 2 2006.201.21:16:32.35#ibcon#about to read 4, iclass 19, count 2 2006.201.21:16:32.35#ibcon#read 4, iclass 19, count 2 2006.201.21:16:32.35#ibcon#about to read 5, iclass 19, count 2 2006.201.21:16:32.35#ibcon#read 5, iclass 19, count 2 2006.201.21:16:32.35#ibcon#about to read 6, iclass 19, count 2 2006.201.21:16:32.35#ibcon#read 6, iclass 19, count 2 2006.201.21:16:32.35#ibcon#end of sib2, iclass 19, count 2 2006.201.21:16:32.35#ibcon#*mode == 0, iclass 19, count 2 2006.201.21:16:32.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.21:16:32.35#ibcon#[27=AT03-04\r\n] 2006.201.21:16:32.35#ibcon#*before write, iclass 19, count 2 2006.201.21:16:32.35#ibcon#enter sib2, iclass 19, count 2 2006.201.21:16:32.35#ibcon#flushed, iclass 19, count 2 2006.201.21:16:32.35#ibcon#about to write, iclass 19, count 2 2006.201.21:16:32.35#ibcon#wrote, iclass 19, count 2 2006.201.21:16:32.35#ibcon#about to read 3, iclass 19, count 2 2006.201.21:16:32.38#ibcon#read 3, iclass 19, count 2 2006.201.21:16:32.38#ibcon#about to read 4, iclass 19, count 2 2006.201.21:16:32.38#ibcon#read 4, iclass 19, count 2 2006.201.21:16:32.38#ibcon#about to read 5, iclass 19, count 2 2006.201.21:16:32.38#ibcon#read 5, iclass 19, count 2 2006.201.21:16:32.38#ibcon#about to read 6, iclass 19, count 2 2006.201.21:16:32.38#ibcon#read 6, iclass 19, count 2 2006.201.21:16:32.38#ibcon#end of sib2, iclass 19, count 2 2006.201.21:16:32.38#ibcon#*after write, iclass 19, count 2 2006.201.21:16:32.38#ibcon#*before return 0, iclass 19, count 2 2006.201.21:16:32.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:32.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:16:32.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.21:16:32.38#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:32.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:32.46#abcon#<5=/04 1.4 2.8 20.101001002.2\r\n> 2006.201.21:16:32.48#abcon#{5=INTERFACE CLEAR} 2006.201.21:16:32.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:32.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:32.50#ibcon#enter wrdev, iclass 19, count 0 2006.201.21:16:32.50#ibcon#first serial, iclass 19, count 0 2006.201.21:16:32.50#ibcon#enter sib2, iclass 19, count 0 2006.201.21:16:32.50#ibcon#flushed, iclass 19, count 0 2006.201.21:16:32.50#ibcon#about to write, iclass 19, count 0 2006.201.21:16:32.50#ibcon#wrote, iclass 19, count 0 2006.201.21:16:32.50#ibcon#about to read 3, iclass 19, count 0 2006.201.21:16:32.52#ibcon#read 3, iclass 19, count 0 2006.201.21:16:32.52#ibcon#about to read 4, iclass 19, count 0 2006.201.21:16:32.52#ibcon#read 4, iclass 19, count 0 2006.201.21:16:32.52#ibcon#about to read 5, iclass 19, count 0 2006.201.21:16:32.52#ibcon#read 5, iclass 19, count 0 2006.201.21:16:32.52#ibcon#about to read 6, iclass 19, count 0 2006.201.21:16:32.52#ibcon#read 6, iclass 19, count 0 2006.201.21:16:32.52#ibcon#end of sib2, iclass 19, count 0 2006.201.21:16:32.52#ibcon#*mode == 0, iclass 19, count 0 2006.201.21:16:32.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.21:16:32.52#ibcon#[27=USB\r\n] 2006.201.21:16:32.52#ibcon#*before write, iclass 19, count 0 2006.201.21:16:32.52#ibcon#enter sib2, iclass 19, count 0 2006.201.21:16:32.52#ibcon#flushed, iclass 19, count 0 2006.201.21:16:32.52#ibcon#about to write, iclass 19, count 0 2006.201.21:16:32.52#ibcon#wrote, iclass 19, count 0 2006.201.21:16:32.52#ibcon#about to read 3, iclass 19, count 0 2006.201.21:16:32.54#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:16:32.55#ibcon#read 3, iclass 19, count 0 2006.201.21:16:32.55#ibcon#about to read 4, iclass 19, count 0 2006.201.21:16:32.55#ibcon#read 4, iclass 19, count 0 2006.201.21:16:32.55#ibcon#about to read 5, iclass 19, count 0 2006.201.21:16:32.55#ibcon#read 5, iclass 19, count 0 2006.201.21:16:32.55#ibcon#about to read 6, iclass 19, count 0 2006.201.21:16:32.55#ibcon#read 6, iclass 19, count 0 2006.201.21:16:32.55#ibcon#end of sib2, iclass 19, count 0 2006.201.21:16:32.55#ibcon#*after write, iclass 19, count 0 2006.201.21:16:32.55#ibcon#*before return 0, iclass 19, count 0 2006.201.21:16:32.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:32.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:16:32.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.21:16:32.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.21:16:32.55$vck44/vblo=4,679.99 2006.201.21:16:32.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.21:16:32.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.21:16:32.55#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:32.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:32.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:32.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:32.55#ibcon#enter wrdev, iclass 25, count 0 2006.201.21:16:32.55#ibcon#first serial, iclass 25, count 0 2006.201.21:16:32.55#ibcon#enter sib2, iclass 25, count 0 2006.201.21:16:32.55#ibcon#flushed, iclass 25, count 0 2006.201.21:16:32.55#ibcon#about to write, iclass 25, count 0 2006.201.21:16:32.55#ibcon#wrote, iclass 25, count 0 2006.201.21:16:32.55#ibcon#about to read 3, iclass 25, count 0 2006.201.21:16:32.57#ibcon#read 3, iclass 25, count 0 2006.201.21:16:32.57#ibcon#about to read 4, iclass 25, count 0 2006.201.21:16:32.57#ibcon#read 4, iclass 25, count 0 2006.201.21:16:32.57#ibcon#about to read 5, iclass 25, count 0 2006.201.21:16:32.57#ibcon#read 5, iclass 25, count 0 2006.201.21:16:32.57#ibcon#about to read 6, iclass 25, count 0 2006.201.21:16:32.57#ibcon#read 6, iclass 25, count 0 2006.201.21:16:32.57#ibcon#end of sib2, iclass 25, count 0 2006.201.21:16:32.57#ibcon#*mode == 0, iclass 25, count 0 2006.201.21:16:32.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.21:16:32.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.21:16:32.57#ibcon#*before write, iclass 25, count 0 2006.201.21:16:32.57#ibcon#enter sib2, iclass 25, count 0 2006.201.21:16:32.57#ibcon#flushed, iclass 25, count 0 2006.201.21:16:32.57#ibcon#about to write, iclass 25, count 0 2006.201.21:16:32.57#ibcon#wrote, iclass 25, count 0 2006.201.21:16:32.57#ibcon#about to read 3, iclass 25, count 0 2006.201.21:16:32.61#ibcon#read 3, iclass 25, count 0 2006.201.21:16:32.61#ibcon#about to read 4, iclass 25, count 0 2006.201.21:16:32.61#ibcon#read 4, iclass 25, count 0 2006.201.21:16:32.61#ibcon#about to read 5, iclass 25, count 0 2006.201.21:16:32.61#ibcon#read 5, iclass 25, count 0 2006.201.21:16:32.61#ibcon#about to read 6, iclass 25, count 0 2006.201.21:16:32.61#ibcon#read 6, iclass 25, count 0 2006.201.21:16:32.61#ibcon#end of sib2, iclass 25, count 0 2006.201.21:16:32.61#ibcon#*after write, iclass 25, count 0 2006.201.21:16:32.61#ibcon#*before return 0, iclass 25, count 0 2006.201.21:16:32.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:32.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:16:32.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.21:16:32.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.21:16:32.61$vck44/vb=4,5 2006.201.21:16:32.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.21:16:32.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.21:16:32.61#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:32.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:32.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:32.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:32.67#ibcon#enter wrdev, iclass 27, count 2 2006.201.21:16:32.67#ibcon#first serial, iclass 27, count 2 2006.201.21:16:32.67#ibcon#enter sib2, iclass 27, count 2 2006.201.21:16:32.67#ibcon#flushed, iclass 27, count 2 2006.201.21:16:32.67#ibcon#about to write, iclass 27, count 2 2006.201.21:16:32.67#ibcon#wrote, iclass 27, count 2 2006.201.21:16:32.67#ibcon#about to read 3, iclass 27, count 2 2006.201.21:16:32.69#ibcon#read 3, iclass 27, count 2 2006.201.21:16:32.69#ibcon#about to read 4, iclass 27, count 2 2006.201.21:16:32.69#ibcon#read 4, iclass 27, count 2 2006.201.21:16:32.69#ibcon#about to read 5, iclass 27, count 2 2006.201.21:16:32.69#ibcon#read 5, iclass 27, count 2 2006.201.21:16:32.69#ibcon#about to read 6, iclass 27, count 2 2006.201.21:16:32.69#ibcon#read 6, iclass 27, count 2 2006.201.21:16:32.69#ibcon#end of sib2, iclass 27, count 2 2006.201.21:16:32.69#ibcon#*mode == 0, iclass 27, count 2 2006.201.21:16:32.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.21:16:32.69#ibcon#[27=AT04-05\r\n] 2006.201.21:16:32.69#ibcon#*before write, iclass 27, count 2 2006.201.21:16:32.69#ibcon#enter sib2, iclass 27, count 2 2006.201.21:16:32.69#ibcon#flushed, iclass 27, count 2 2006.201.21:16:32.69#ibcon#about to write, iclass 27, count 2 2006.201.21:16:32.69#ibcon#wrote, iclass 27, count 2 2006.201.21:16:32.69#ibcon#about to read 3, iclass 27, count 2 2006.201.21:16:32.72#ibcon#read 3, iclass 27, count 2 2006.201.21:16:32.72#ibcon#about to read 4, iclass 27, count 2 2006.201.21:16:32.72#ibcon#read 4, iclass 27, count 2 2006.201.21:16:32.72#ibcon#about to read 5, iclass 27, count 2 2006.201.21:16:32.72#ibcon#read 5, iclass 27, count 2 2006.201.21:16:32.72#ibcon#about to read 6, iclass 27, count 2 2006.201.21:16:32.72#ibcon#read 6, iclass 27, count 2 2006.201.21:16:32.72#ibcon#end of sib2, iclass 27, count 2 2006.201.21:16:32.72#ibcon#*after write, iclass 27, count 2 2006.201.21:16:32.72#ibcon#*before return 0, iclass 27, count 2 2006.201.21:16:32.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:32.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:16:32.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.21:16:32.72#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:32.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:32.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:32.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:32.84#ibcon#enter wrdev, iclass 27, count 0 2006.201.21:16:32.84#ibcon#first serial, iclass 27, count 0 2006.201.21:16:32.84#ibcon#enter sib2, iclass 27, count 0 2006.201.21:16:32.84#ibcon#flushed, iclass 27, count 0 2006.201.21:16:32.84#ibcon#about to write, iclass 27, count 0 2006.201.21:16:32.84#ibcon#wrote, iclass 27, count 0 2006.201.21:16:32.84#ibcon#about to read 3, iclass 27, count 0 2006.201.21:16:32.86#ibcon#read 3, iclass 27, count 0 2006.201.21:16:32.86#ibcon#about to read 4, iclass 27, count 0 2006.201.21:16:32.86#ibcon#read 4, iclass 27, count 0 2006.201.21:16:32.86#ibcon#about to read 5, iclass 27, count 0 2006.201.21:16:32.86#ibcon#read 5, iclass 27, count 0 2006.201.21:16:32.86#ibcon#about to read 6, iclass 27, count 0 2006.201.21:16:32.86#ibcon#read 6, iclass 27, count 0 2006.201.21:16:32.86#ibcon#end of sib2, iclass 27, count 0 2006.201.21:16:32.86#ibcon#*mode == 0, iclass 27, count 0 2006.201.21:16:32.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.21:16:32.86#ibcon#[27=USB\r\n] 2006.201.21:16:32.86#ibcon#*before write, iclass 27, count 0 2006.201.21:16:32.86#ibcon#enter sib2, iclass 27, count 0 2006.201.21:16:32.86#ibcon#flushed, iclass 27, count 0 2006.201.21:16:32.86#ibcon#about to write, iclass 27, count 0 2006.201.21:16:32.86#ibcon#wrote, iclass 27, count 0 2006.201.21:16:32.86#ibcon#about to read 3, iclass 27, count 0 2006.201.21:16:32.89#ibcon#read 3, iclass 27, count 0 2006.201.21:16:32.89#ibcon#about to read 4, iclass 27, count 0 2006.201.21:16:32.89#ibcon#read 4, iclass 27, count 0 2006.201.21:16:32.89#ibcon#about to read 5, iclass 27, count 0 2006.201.21:16:32.89#ibcon#read 5, iclass 27, count 0 2006.201.21:16:32.89#ibcon#about to read 6, iclass 27, count 0 2006.201.21:16:32.89#ibcon#read 6, iclass 27, count 0 2006.201.21:16:32.89#ibcon#end of sib2, iclass 27, count 0 2006.201.21:16:32.89#ibcon#*after write, iclass 27, count 0 2006.201.21:16:32.89#ibcon#*before return 0, iclass 27, count 0 2006.201.21:16:32.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:32.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:16:32.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.21:16:32.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.21:16:32.89$vck44/vblo=5,709.99 2006.201.21:16:32.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.21:16:32.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.21:16:32.89#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:32.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:32.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:32.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:32.89#ibcon#enter wrdev, iclass 29, count 0 2006.201.21:16:32.89#ibcon#first serial, iclass 29, count 0 2006.201.21:16:32.89#ibcon#enter sib2, iclass 29, count 0 2006.201.21:16:32.89#ibcon#flushed, iclass 29, count 0 2006.201.21:16:32.89#ibcon#about to write, iclass 29, count 0 2006.201.21:16:32.89#ibcon#wrote, iclass 29, count 0 2006.201.21:16:32.89#ibcon#about to read 3, iclass 29, count 0 2006.201.21:16:32.91#ibcon#read 3, iclass 29, count 0 2006.201.21:16:32.91#ibcon#about to read 4, iclass 29, count 0 2006.201.21:16:32.91#ibcon#read 4, iclass 29, count 0 2006.201.21:16:32.91#ibcon#about to read 5, iclass 29, count 0 2006.201.21:16:32.91#ibcon#read 5, iclass 29, count 0 2006.201.21:16:32.91#ibcon#about to read 6, iclass 29, count 0 2006.201.21:16:32.91#ibcon#read 6, iclass 29, count 0 2006.201.21:16:32.91#ibcon#end of sib2, iclass 29, count 0 2006.201.21:16:32.91#ibcon#*mode == 0, iclass 29, count 0 2006.201.21:16:32.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.21:16:32.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.21:16:32.91#ibcon#*before write, iclass 29, count 0 2006.201.21:16:32.91#ibcon#enter sib2, iclass 29, count 0 2006.201.21:16:32.91#ibcon#flushed, iclass 29, count 0 2006.201.21:16:32.91#ibcon#about to write, iclass 29, count 0 2006.201.21:16:32.91#ibcon#wrote, iclass 29, count 0 2006.201.21:16:32.91#ibcon#about to read 3, iclass 29, count 0 2006.201.21:16:32.95#ibcon#read 3, iclass 29, count 0 2006.201.21:16:32.95#ibcon#about to read 4, iclass 29, count 0 2006.201.21:16:32.95#ibcon#read 4, iclass 29, count 0 2006.201.21:16:32.95#ibcon#about to read 5, iclass 29, count 0 2006.201.21:16:32.95#ibcon#read 5, iclass 29, count 0 2006.201.21:16:32.95#ibcon#about to read 6, iclass 29, count 0 2006.201.21:16:32.95#ibcon#read 6, iclass 29, count 0 2006.201.21:16:32.95#ibcon#end of sib2, iclass 29, count 0 2006.201.21:16:32.95#ibcon#*after write, iclass 29, count 0 2006.201.21:16:32.95#ibcon#*before return 0, iclass 29, count 0 2006.201.21:16:32.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:32.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:16:32.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.21:16:32.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.21:16:32.95$vck44/vb=5,4 2006.201.21:16:32.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.21:16:32.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.21:16:32.95#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:32.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:33.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:33.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:33.01#ibcon#enter wrdev, iclass 31, count 2 2006.201.21:16:33.01#ibcon#first serial, iclass 31, count 2 2006.201.21:16:33.01#ibcon#enter sib2, iclass 31, count 2 2006.201.21:16:33.01#ibcon#flushed, iclass 31, count 2 2006.201.21:16:33.01#ibcon#about to write, iclass 31, count 2 2006.201.21:16:33.01#ibcon#wrote, iclass 31, count 2 2006.201.21:16:33.01#ibcon#about to read 3, iclass 31, count 2 2006.201.21:16:33.03#ibcon#read 3, iclass 31, count 2 2006.201.21:16:33.03#ibcon#about to read 4, iclass 31, count 2 2006.201.21:16:33.03#ibcon#read 4, iclass 31, count 2 2006.201.21:16:33.03#ibcon#about to read 5, iclass 31, count 2 2006.201.21:16:33.03#ibcon#read 5, iclass 31, count 2 2006.201.21:16:33.03#ibcon#about to read 6, iclass 31, count 2 2006.201.21:16:33.03#ibcon#read 6, iclass 31, count 2 2006.201.21:16:33.03#ibcon#end of sib2, iclass 31, count 2 2006.201.21:16:33.03#ibcon#*mode == 0, iclass 31, count 2 2006.201.21:16:33.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.21:16:33.03#ibcon#[27=AT05-04\r\n] 2006.201.21:16:33.03#ibcon#*before write, iclass 31, count 2 2006.201.21:16:33.03#ibcon#enter sib2, iclass 31, count 2 2006.201.21:16:33.03#ibcon#flushed, iclass 31, count 2 2006.201.21:16:33.03#ibcon#about to write, iclass 31, count 2 2006.201.21:16:33.03#ibcon#wrote, iclass 31, count 2 2006.201.21:16:33.03#ibcon#about to read 3, iclass 31, count 2 2006.201.21:16:33.06#ibcon#read 3, iclass 31, count 2 2006.201.21:16:33.06#ibcon#about to read 4, iclass 31, count 2 2006.201.21:16:33.06#ibcon#read 4, iclass 31, count 2 2006.201.21:16:33.06#ibcon#about to read 5, iclass 31, count 2 2006.201.21:16:33.06#ibcon#read 5, iclass 31, count 2 2006.201.21:16:33.06#ibcon#about to read 6, iclass 31, count 2 2006.201.21:16:33.06#ibcon#read 6, iclass 31, count 2 2006.201.21:16:33.06#ibcon#end of sib2, iclass 31, count 2 2006.201.21:16:33.06#ibcon#*after write, iclass 31, count 2 2006.201.21:16:33.06#ibcon#*before return 0, iclass 31, count 2 2006.201.21:16:33.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:33.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:16:33.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.21:16:33.06#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:33.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:33.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:33.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:33.18#ibcon#enter wrdev, iclass 31, count 0 2006.201.21:16:33.18#ibcon#first serial, iclass 31, count 0 2006.201.21:16:33.18#ibcon#enter sib2, iclass 31, count 0 2006.201.21:16:33.18#ibcon#flushed, iclass 31, count 0 2006.201.21:16:33.18#ibcon#about to write, iclass 31, count 0 2006.201.21:16:33.18#ibcon#wrote, iclass 31, count 0 2006.201.21:16:33.18#ibcon#about to read 3, iclass 31, count 0 2006.201.21:16:33.20#ibcon#read 3, iclass 31, count 0 2006.201.21:16:33.20#ibcon#about to read 4, iclass 31, count 0 2006.201.21:16:33.20#ibcon#read 4, iclass 31, count 0 2006.201.21:16:33.20#ibcon#about to read 5, iclass 31, count 0 2006.201.21:16:33.20#ibcon#read 5, iclass 31, count 0 2006.201.21:16:33.20#ibcon#about to read 6, iclass 31, count 0 2006.201.21:16:33.20#ibcon#read 6, iclass 31, count 0 2006.201.21:16:33.20#ibcon#end of sib2, iclass 31, count 0 2006.201.21:16:33.20#ibcon#*mode == 0, iclass 31, count 0 2006.201.21:16:33.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.21:16:33.20#ibcon#[27=USB\r\n] 2006.201.21:16:33.20#ibcon#*before write, iclass 31, count 0 2006.201.21:16:33.20#ibcon#enter sib2, iclass 31, count 0 2006.201.21:16:33.20#ibcon#flushed, iclass 31, count 0 2006.201.21:16:33.20#ibcon#about to write, iclass 31, count 0 2006.201.21:16:33.20#ibcon#wrote, iclass 31, count 0 2006.201.21:16:33.20#ibcon#about to read 3, iclass 31, count 0 2006.201.21:16:33.23#ibcon#read 3, iclass 31, count 0 2006.201.21:16:33.23#ibcon#about to read 4, iclass 31, count 0 2006.201.21:16:33.23#ibcon#read 4, iclass 31, count 0 2006.201.21:16:33.23#ibcon#about to read 5, iclass 31, count 0 2006.201.21:16:33.23#ibcon#read 5, iclass 31, count 0 2006.201.21:16:33.23#ibcon#about to read 6, iclass 31, count 0 2006.201.21:16:33.23#ibcon#read 6, iclass 31, count 0 2006.201.21:16:33.23#ibcon#end of sib2, iclass 31, count 0 2006.201.21:16:33.23#ibcon#*after write, iclass 31, count 0 2006.201.21:16:33.23#ibcon#*before return 0, iclass 31, count 0 2006.201.21:16:33.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:33.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:16:33.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.21:16:33.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.21:16:33.23$vck44/vblo=6,719.99 2006.201.21:16:33.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.21:16:33.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.21:16:33.23#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:33.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:33.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:33.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:33.23#ibcon#enter wrdev, iclass 33, count 0 2006.201.21:16:33.23#ibcon#first serial, iclass 33, count 0 2006.201.21:16:33.23#ibcon#enter sib2, iclass 33, count 0 2006.201.21:16:33.23#ibcon#flushed, iclass 33, count 0 2006.201.21:16:33.23#ibcon#about to write, iclass 33, count 0 2006.201.21:16:33.23#ibcon#wrote, iclass 33, count 0 2006.201.21:16:33.23#ibcon#about to read 3, iclass 33, count 0 2006.201.21:16:33.25#ibcon#read 3, iclass 33, count 0 2006.201.21:16:33.25#ibcon#about to read 4, iclass 33, count 0 2006.201.21:16:33.25#ibcon#read 4, iclass 33, count 0 2006.201.21:16:33.25#ibcon#about to read 5, iclass 33, count 0 2006.201.21:16:33.25#ibcon#read 5, iclass 33, count 0 2006.201.21:16:33.25#ibcon#about to read 6, iclass 33, count 0 2006.201.21:16:33.25#ibcon#read 6, iclass 33, count 0 2006.201.21:16:33.25#ibcon#end of sib2, iclass 33, count 0 2006.201.21:16:33.25#ibcon#*mode == 0, iclass 33, count 0 2006.201.21:16:33.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.21:16:33.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.21:16:33.25#ibcon#*before write, iclass 33, count 0 2006.201.21:16:33.25#ibcon#enter sib2, iclass 33, count 0 2006.201.21:16:33.25#ibcon#flushed, iclass 33, count 0 2006.201.21:16:33.25#ibcon#about to write, iclass 33, count 0 2006.201.21:16:33.25#ibcon#wrote, iclass 33, count 0 2006.201.21:16:33.25#ibcon#about to read 3, iclass 33, count 0 2006.201.21:16:33.29#ibcon#read 3, iclass 33, count 0 2006.201.21:16:33.29#ibcon#about to read 4, iclass 33, count 0 2006.201.21:16:33.29#ibcon#read 4, iclass 33, count 0 2006.201.21:16:33.29#ibcon#about to read 5, iclass 33, count 0 2006.201.21:16:33.29#ibcon#read 5, iclass 33, count 0 2006.201.21:16:33.29#ibcon#about to read 6, iclass 33, count 0 2006.201.21:16:33.29#ibcon#read 6, iclass 33, count 0 2006.201.21:16:33.29#ibcon#end of sib2, iclass 33, count 0 2006.201.21:16:33.29#ibcon#*after write, iclass 33, count 0 2006.201.21:16:33.29#ibcon#*before return 0, iclass 33, count 0 2006.201.21:16:33.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:33.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:16:33.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.21:16:33.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.21:16:33.29$vck44/vb=6,4 2006.201.21:16:33.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.21:16:33.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.21:16:33.29#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:33.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:33.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:33.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:33.35#ibcon#enter wrdev, iclass 35, count 2 2006.201.21:16:33.35#ibcon#first serial, iclass 35, count 2 2006.201.21:16:33.35#ibcon#enter sib2, iclass 35, count 2 2006.201.21:16:33.35#ibcon#flushed, iclass 35, count 2 2006.201.21:16:33.35#ibcon#about to write, iclass 35, count 2 2006.201.21:16:33.35#ibcon#wrote, iclass 35, count 2 2006.201.21:16:33.35#ibcon#about to read 3, iclass 35, count 2 2006.201.21:16:33.37#ibcon#read 3, iclass 35, count 2 2006.201.21:16:33.37#ibcon#about to read 4, iclass 35, count 2 2006.201.21:16:33.37#ibcon#read 4, iclass 35, count 2 2006.201.21:16:33.37#ibcon#about to read 5, iclass 35, count 2 2006.201.21:16:33.37#ibcon#read 5, iclass 35, count 2 2006.201.21:16:33.37#ibcon#about to read 6, iclass 35, count 2 2006.201.21:16:33.37#ibcon#read 6, iclass 35, count 2 2006.201.21:16:33.37#ibcon#end of sib2, iclass 35, count 2 2006.201.21:16:33.37#ibcon#*mode == 0, iclass 35, count 2 2006.201.21:16:33.37#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.21:16:33.37#ibcon#[27=AT06-04\r\n] 2006.201.21:16:33.37#ibcon#*before write, iclass 35, count 2 2006.201.21:16:33.37#ibcon#enter sib2, iclass 35, count 2 2006.201.21:16:33.37#ibcon#flushed, iclass 35, count 2 2006.201.21:16:33.37#ibcon#about to write, iclass 35, count 2 2006.201.21:16:33.37#ibcon#wrote, iclass 35, count 2 2006.201.21:16:33.37#ibcon#about to read 3, iclass 35, count 2 2006.201.21:16:33.40#ibcon#read 3, iclass 35, count 2 2006.201.21:16:33.40#ibcon#about to read 4, iclass 35, count 2 2006.201.21:16:33.40#ibcon#read 4, iclass 35, count 2 2006.201.21:16:33.40#ibcon#about to read 5, iclass 35, count 2 2006.201.21:16:33.40#ibcon#read 5, iclass 35, count 2 2006.201.21:16:33.40#ibcon#about to read 6, iclass 35, count 2 2006.201.21:16:33.40#ibcon#read 6, iclass 35, count 2 2006.201.21:16:33.40#ibcon#end of sib2, iclass 35, count 2 2006.201.21:16:33.40#ibcon#*after write, iclass 35, count 2 2006.201.21:16:33.40#ibcon#*before return 0, iclass 35, count 2 2006.201.21:16:33.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:33.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:16:33.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.21:16:33.40#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:33.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:33.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:33.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:33.52#ibcon#enter wrdev, iclass 35, count 0 2006.201.21:16:33.52#ibcon#first serial, iclass 35, count 0 2006.201.21:16:33.52#ibcon#enter sib2, iclass 35, count 0 2006.201.21:16:33.52#ibcon#flushed, iclass 35, count 0 2006.201.21:16:33.52#ibcon#about to write, iclass 35, count 0 2006.201.21:16:33.52#ibcon#wrote, iclass 35, count 0 2006.201.21:16:33.52#ibcon#about to read 3, iclass 35, count 0 2006.201.21:16:33.54#ibcon#read 3, iclass 35, count 0 2006.201.21:16:33.54#ibcon#about to read 4, iclass 35, count 0 2006.201.21:16:33.54#ibcon#read 4, iclass 35, count 0 2006.201.21:16:33.54#ibcon#about to read 5, iclass 35, count 0 2006.201.21:16:33.54#ibcon#read 5, iclass 35, count 0 2006.201.21:16:33.54#ibcon#about to read 6, iclass 35, count 0 2006.201.21:16:33.54#ibcon#read 6, iclass 35, count 0 2006.201.21:16:33.54#ibcon#end of sib2, iclass 35, count 0 2006.201.21:16:33.54#ibcon#*mode == 0, iclass 35, count 0 2006.201.21:16:33.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.21:16:33.54#ibcon#[27=USB\r\n] 2006.201.21:16:33.54#ibcon#*before write, iclass 35, count 0 2006.201.21:16:33.54#ibcon#enter sib2, iclass 35, count 0 2006.201.21:16:33.54#ibcon#flushed, iclass 35, count 0 2006.201.21:16:33.54#ibcon#about to write, iclass 35, count 0 2006.201.21:16:33.54#ibcon#wrote, iclass 35, count 0 2006.201.21:16:33.54#ibcon#about to read 3, iclass 35, count 0 2006.201.21:16:33.57#ibcon#read 3, iclass 35, count 0 2006.201.21:16:33.57#ibcon#about to read 4, iclass 35, count 0 2006.201.21:16:33.57#ibcon#read 4, iclass 35, count 0 2006.201.21:16:33.57#ibcon#about to read 5, iclass 35, count 0 2006.201.21:16:33.57#ibcon#read 5, iclass 35, count 0 2006.201.21:16:33.57#ibcon#about to read 6, iclass 35, count 0 2006.201.21:16:33.57#ibcon#read 6, iclass 35, count 0 2006.201.21:16:33.57#ibcon#end of sib2, iclass 35, count 0 2006.201.21:16:33.57#ibcon#*after write, iclass 35, count 0 2006.201.21:16:33.57#ibcon#*before return 0, iclass 35, count 0 2006.201.21:16:33.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:33.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:16:33.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.21:16:33.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.21:16:33.57$vck44/vblo=7,734.99 2006.201.21:16:33.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.21:16:33.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.21:16:33.57#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:33.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:33.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:33.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:33.57#ibcon#enter wrdev, iclass 37, count 0 2006.201.21:16:33.57#ibcon#first serial, iclass 37, count 0 2006.201.21:16:33.57#ibcon#enter sib2, iclass 37, count 0 2006.201.21:16:33.57#ibcon#flushed, iclass 37, count 0 2006.201.21:16:33.57#ibcon#about to write, iclass 37, count 0 2006.201.21:16:33.57#ibcon#wrote, iclass 37, count 0 2006.201.21:16:33.57#ibcon#about to read 3, iclass 37, count 0 2006.201.21:16:33.59#ibcon#read 3, iclass 37, count 0 2006.201.21:16:33.59#ibcon#about to read 4, iclass 37, count 0 2006.201.21:16:33.59#ibcon#read 4, iclass 37, count 0 2006.201.21:16:33.59#ibcon#about to read 5, iclass 37, count 0 2006.201.21:16:33.59#ibcon#read 5, iclass 37, count 0 2006.201.21:16:33.59#ibcon#about to read 6, iclass 37, count 0 2006.201.21:16:33.59#ibcon#read 6, iclass 37, count 0 2006.201.21:16:33.59#ibcon#end of sib2, iclass 37, count 0 2006.201.21:16:33.59#ibcon#*mode == 0, iclass 37, count 0 2006.201.21:16:33.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.21:16:33.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.21:16:33.59#ibcon#*before write, iclass 37, count 0 2006.201.21:16:33.59#ibcon#enter sib2, iclass 37, count 0 2006.201.21:16:33.59#ibcon#flushed, iclass 37, count 0 2006.201.21:16:33.59#ibcon#about to write, iclass 37, count 0 2006.201.21:16:33.59#ibcon#wrote, iclass 37, count 0 2006.201.21:16:33.59#ibcon#about to read 3, iclass 37, count 0 2006.201.21:16:33.63#ibcon#read 3, iclass 37, count 0 2006.201.21:16:33.63#ibcon#about to read 4, iclass 37, count 0 2006.201.21:16:33.63#ibcon#read 4, iclass 37, count 0 2006.201.21:16:33.63#ibcon#about to read 5, iclass 37, count 0 2006.201.21:16:33.63#ibcon#read 5, iclass 37, count 0 2006.201.21:16:33.63#ibcon#about to read 6, iclass 37, count 0 2006.201.21:16:33.63#ibcon#read 6, iclass 37, count 0 2006.201.21:16:33.63#ibcon#end of sib2, iclass 37, count 0 2006.201.21:16:33.63#ibcon#*after write, iclass 37, count 0 2006.201.21:16:33.63#ibcon#*before return 0, iclass 37, count 0 2006.201.21:16:33.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:33.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:16:33.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.21:16:33.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.21:16:33.63$vck44/vb=7,4 2006.201.21:16:33.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.21:16:33.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.21:16:33.63#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:33.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:33.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:33.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:33.69#ibcon#enter wrdev, iclass 39, count 2 2006.201.21:16:33.69#ibcon#first serial, iclass 39, count 2 2006.201.21:16:33.69#ibcon#enter sib2, iclass 39, count 2 2006.201.21:16:33.69#ibcon#flushed, iclass 39, count 2 2006.201.21:16:33.69#ibcon#about to write, iclass 39, count 2 2006.201.21:16:33.69#ibcon#wrote, iclass 39, count 2 2006.201.21:16:33.69#ibcon#about to read 3, iclass 39, count 2 2006.201.21:16:33.71#ibcon#read 3, iclass 39, count 2 2006.201.21:16:33.71#ibcon#about to read 4, iclass 39, count 2 2006.201.21:16:33.71#ibcon#read 4, iclass 39, count 2 2006.201.21:16:33.71#ibcon#about to read 5, iclass 39, count 2 2006.201.21:16:33.71#ibcon#read 5, iclass 39, count 2 2006.201.21:16:33.71#ibcon#about to read 6, iclass 39, count 2 2006.201.21:16:33.71#ibcon#read 6, iclass 39, count 2 2006.201.21:16:33.71#ibcon#end of sib2, iclass 39, count 2 2006.201.21:16:33.71#ibcon#*mode == 0, iclass 39, count 2 2006.201.21:16:33.71#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.21:16:33.71#ibcon#[27=AT07-04\r\n] 2006.201.21:16:33.71#ibcon#*before write, iclass 39, count 2 2006.201.21:16:33.71#ibcon#enter sib2, iclass 39, count 2 2006.201.21:16:33.71#ibcon#flushed, iclass 39, count 2 2006.201.21:16:33.71#ibcon#about to write, iclass 39, count 2 2006.201.21:16:33.71#ibcon#wrote, iclass 39, count 2 2006.201.21:16:33.71#ibcon#about to read 3, iclass 39, count 2 2006.201.21:16:33.74#ibcon#read 3, iclass 39, count 2 2006.201.21:16:33.74#ibcon#about to read 4, iclass 39, count 2 2006.201.21:16:33.74#ibcon#read 4, iclass 39, count 2 2006.201.21:16:33.74#ibcon#about to read 5, iclass 39, count 2 2006.201.21:16:33.74#ibcon#read 5, iclass 39, count 2 2006.201.21:16:33.74#ibcon#about to read 6, iclass 39, count 2 2006.201.21:16:33.74#ibcon#read 6, iclass 39, count 2 2006.201.21:16:33.74#ibcon#end of sib2, iclass 39, count 2 2006.201.21:16:33.74#ibcon#*after write, iclass 39, count 2 2006.201.21:16:33.74#ibcon#*before return 0, iclass 39, count 2 2006.201.21:16:33.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:33.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:16:33.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.21:16:33.74#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:33.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:33.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:33.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:33.86#ibcon#enter wrdev, iclass 39, count 0 2006.201.21:16:33.86#ibcon#first serial, iclass 39, count 0 2006.201.21:16:33.86#ibcon#enter sib2, iclass 39, count 0 2006.201.21:16:33.86#ibcon#flushed, iclass 39, count 0 2006.201.21:16:33.86#ibcon#about to write, iclass 39, count 0 2006.201.21:16:33.86#ibcon#wrote, iclass 39, count 0 2006.201.21:16:33.86#ibcon#about to read 3, iclass 39, count 0 2006.201.21:16:33.88#ibcon#read 3, iclass 39, count 0 2006.201.21:16:33.88#ibcon#about to read 4, iclass 39, count 0 2006.201.21:16:33.88#ibcon#read 4, iclass 39, count 0 2006.201.21:16:33.88#ibcon#about to read 5, iclass 39, count 0 2006.201.21:16:33.88#ibcon#read 5, iclass 39, count 0 2006.201.21:16:33.88#ibcon#about to read 6, iclass 39, count 0 2006.201.21:16:33.88#ibcon#read 6, iclass 39, count 0 2006.201.21:16:33.88#ibcon#end of sib2, iclass 39, count 0 2006.201.21:16:33.88#ibcon#*mode == 0, iclass 39, count 0 2006.201.21:16:33.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.21:16:33.88#ibcon#[27=USB\r\n] 2006.201.21:16:33.88#ibcon#*before write, iclass 39, count 0 2006.201.21:16:33.88#ibcon#enter sib2, iclass 39, count 0 2006.201.21:16:33.88#ibcon#flushed, iclass 39, count 0 2006.201.21:16:33.88#ibcon#about to write, iclass 39, count 0 2006.201.21:16:33.88#ibcon#wrote, iclass 39, count 0 2006.201.21:16:33.88#ibcon#about to read 3, iclass 39, count 0 2006.201.21:16:33.91#ibcon#read 3, iclass 39, count 0 2006.201.21:16:33.91#ibcon#about to read 4, iclass 39, count 0 2006.201.21:16:33.91#ibcon#read 4, iclass 39, count 0 2006.201.21:16:33.91#ibcon#about to read 5, iclass 39, count 0 2006.201.21:16:33.91#ibcon#read 5, iclass 39, count 0 2006.201.21:16:33.91#ibcon#about to read 6, iclass 39, count 0 2006.201.21:16:33.91#ibcon#read 6, iclass 39, count 0 2006.201.21:16:33.91#ibcon#end of sib2, iclass 39, count 0 2006.201.21:16:33.91#ibcon#*after write, iclass 39, count 0 2006.201.21:16:33.91#ibcon#*before return 0, iclass 39, count 0 2006.201.21:16:33.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:33.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:16:33.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.21:16:33.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.21:16:33.91$vck44/vblo=8,744.99 2006.201.21:16:33.91#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.21:16:33.91#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.21:16:33.91#ibcon#ireg 17 cls_cnt 0 2006.201.21:16:33.91#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:33.91#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:33.91#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:33.91#ibcon#enter wrdev, iclass 2, count 0 2006.201.21:16:33.91#ibcon#first serial, iclass 2, count 0 2006.201.21:16:33.91#ibcon#enter sib2, iclass 2, count 0 2006.201.21:16:33.91#ibcon#flushed, iclass 2, count 0 2006.201.21:16:33.91#ibcon#about to write, iclass 2, count 0 2006.201.21:16:33.91#ibcon#wrote, iclass 2, count 0 2006.201.21:16:33.91#ibcon#about to read 3, iclass 2, count 0 2006.201.21:16:33.93#ibcon#read 3, iclass 2, count 0 2006.201.21:16:33.93#ibcon#about to read 4, iclass 2, count 0 2006.201.21:16:33.93#ibcon#read 4, iclass 2, count 0 2006.201.21:16:33.93#ibcon#about to read 5, iclass 2, count 0 2006.201.21:16:33.93#ibcon#read 5, iclass 2, count 0 2006.201.21:16:33.93#ibcon#about to read 6, iclass 2, count 0 2006.201.21:16:33.93#ibcon#read 6, iclass 2, count 0 2006.201.21:16:33.93#ibcon#end of sib2, iclass 2, count 0 2006.201.21:16:33.93#ibcon#*mode == 0, iclass 2, count 0 2006.201.21:16:33.93#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.21:16:33.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.21:16:33.93#ibcon#*before write, iclass 2, count 0 2006.201.21:16:33.93#ibcon#enter sib2, iclass 2, count 0 2006.201.21:16:33.93#ibcon#flushed, iclass 2, count 0 2006.201.21:16:33.93#ibcon#about to write, iclass 2, count 0 2006.201.21:16:33.93#ibcon#wrote, iclass 2, count 0 2006.201.21:16:33.93#ibcon#about to read 3, iclass 2, count 0 2006.201.21:16:33.98#ibcon#read 3, iclass 2, count 0 2006.201.21:16:33.98#ibcon#about to read 4, iclass 2, count 0 2006.201.21:16:33.98#ibcon#read 4, iclass 2, count 0 2006.201.21:16:33.98#ibcon#about to read 5, iclass 2, count 0 2006.201.21:16:33.98#ibcon#read 5, iclass 2, count 0 2006.201.21:16:33.98#ibcon#about to read 6, iclass 2, count 0 2006.201.21:16:33.98#ibcon#read 6, iclass 2, count 0 2006.201.21:16:33.98#ibcon#end of sib2, iclass 2, count 0 2006.201.21:16:33.98#ibcon#*after write, iclass 2, count 0 2006.201.21:16:33.98#ibcon#*before return 0, iclass 2, count 0 2006.201.21:16:33.98#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:33.98#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:16:33.98#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.21:16:33.98#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.21:16:33.98$vck44/vb=8,4 2006.201.21:16:33.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.21:16:33.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.21:16:33.98#ibcon#ireg 11 cls_cnt 2 2006.201.21:16:33.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:34.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:34.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:34.03#ibcon#enter wrdev, iclass 5, count 2 2006.201.21:16:34.03#ibcon#first serial, iclass 5, count 2 2006.201.21:16:34.03#ibcon#enter sib2, iclass 5, count 2 2006.201.21:16:34.03#ibcon#flushed, iclass 5, count 2 2006.201.21:16:34.03#ibcon#about to write, iclass 5, count 2 2006.201.21:16:34.03#ibcon#wrote, iclass 5, count 2 2006.201.21:16:34.03#ibcon#about to read 3, iclass 5, count 2 2006.201.21:16:34.05#ibcon#read 3, iclass 5, count 2 2006.201.21:16:34.05#ibcon#about to read 4, iclass 5, count 2 2006.201.21:16:34.05#ibcon#read 4, iclass 5, count 2 2006.201.21:16:34.05#ibcon#about to read 5, iclass 5, count 2 2006.201.21:16:34.05#ibcon#read 5, iclass 5, count 2 2006.201.21:16:34.05#ibcon#about to read 6, iclass 5, count 2 2006.201.21:16:34.05#ibcon#read 6, iclass 5, count 2 2006.201.21:16:34.05#ibcon#end of sib2, iclass 5, count 2 2006.201.21:16:34.05#ibcon#*mode == 0, iclass 5, count 2 2006.201.21:16:34.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.21:16:34.05#ibcon#[27=AT08-04\r\n] 2006.201.21:16:34.05#ibcon#*before write, iclass 5, count 2 2006.201.21:16:34.05#ibcon#enter sib2, iclass 5, count 2 2006.201.21:16:34.05#ibcon#flushed, iclass 5, count 2 2006.201.21:16:34.05#ibcon#about to write, iclass 5, count 2 2006.201.21:16:34.05#ibcon#wrote, iclass 5, count 2 2006.201.21:16:34.05#ibcon#about to read 3, iclass 5, count 2 2006.201.21:16:34.08#ibcon#read 3, iclass 5, count 2 2006.201.21:16:34.08#ibcon#about to read 4, iclass 5, count 2 2006.201.21:16:34.08#ibcon#read 4, iclass 5, count 2 2006.201.21:16:34.08#ibcon#about to read 5, iclass 5, count 2 2006.201.21:16:34.08#ibcon#read 5, iclass 5, count 2 2006.201.21:16:34.08#ibcon#about to read 6, iclass 5, count 2 2006.201.21:16:34.08#ibcon#read 6, iclass 5, count 2 2006.201.21:16:34.08#ibcon#end of sib2, iclass 5, count 2 2006.201.21:16:34.08#ibcon#*after write, iclass 5, count 2 2006.201.21:16:34.08#ibcon#*before return 0, iclass 5, count 2 2006.201.21:16:34.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:34.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:16:34.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.21:16:34.08#ibcon#ireg 7 cls_cnt 0 2006.201.21:16:34.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:34.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:34.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:34.20#ibcon#enter wrdev, iclass 5, count 0 2006.201.21:16:34.20#ibcon#first serial, iclass 5, count 0 2006.201.21:16:34.20#ibcon#enter sib2, iclass 5, count 0 2006.201.21:16:34.20#ibcon#flushed, iclass 5, count 0 2006.201.21:16:34.20#ibcon#about to write, iclass 5, count 0 2006.201.21:16:34.20#ibcon#wrote, iclass 5, count 0 2006.201.21:16:34.20#ibcon#about to read 3, iclass 5, count 0 2006.201.21:16:34.22#ibcon#read 3, iclass 5, count 0 2006.201.21:16:34.22#ibcon#about to read 4, iclass 5, count 0 2006.201.21:16:34.22#ibcon#read 4, iclass 5, count 0 2006.201.21:16:34.22#ibcon#about to read 5, iclass 5, count 0 2006.201.21:16:34.22#ibcon#read 5, iclass 5, count 0 2006.201.21:16:34.22#ibcon#about to read 6, iclass 5, count 0 2006.201.21:16:34.22#ibcon#read 6, iclass 5, count 0 2006.201.21:16:34.22#ibcon#end of sib2, iclass 5, count 0 2006.201.21:16:34.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.21:16:34.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.21:16:34.22#ibcon#[27=USB\r\n] 2006.201.21:16:34.22#ibcon#*before write, iclass 5, count 0 2006.201.21:16:34.22#ibcon#enter sib2, iclass 5, count 0 2006.201.21:16:34.22#ibcon#flushed, iclass 5, count 0 2006.201.21:16:34.22#ibcon#about to write, iclass 5, count 0 2006.201.21:16:34.22#ibcon#wrote, iclass 5, count 0 2006.201.21:16:34.22#ibcon#about to read 3, iclass 5, count 0 2006.201.21:16:34.25#ibcon#read 3, iclass 5, count 0 2006.201.21:16:34.25#ibcon#about to read 4, iclass 5, count 0 2006.201.21:16:34.25#ibcon#read 4, iclass 5, count 0 2006.201.21:16:34.25#ibcon#about to read 5, iclass 5, count 0 2006.201.21:16:34.25#ibcon#read 5, iclass 5, count 0 2006.201.21:16:34.25#ibcon#about to read 6, iclass 5, count 0 2006.201.21:16:34.25#ibcon#read 6, iclass 5, count 0 2006.201.21:16:34.25#ibcon#end of sib2, iclass 5, count 0 2006.201.21:16:34.25#ibcon#*after write, iclass 5, count 0 2006.201.21:16:34.25#ibcon#*before return 0, iclass 5, count 0 2006.201.21:16:34.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:34.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:16:34.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.21:16:34.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.21:16:34.25$vck44/vabw=wide 2006.201.21:16:34.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.21:16:34.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.21:16:34.25#ibcon#ireg 8 cls_cnt 0 2006.201.21:16:34.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:34.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:34.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:34.25#ibcon#enter wrdev, iclass 7, count 0 2006.201.21:16:34.25#ibcon#first serial, iclass 7, count 0 2006.201.21:16:34.25#ibcon#enter sib2, iclass 7, count 0 2006.201.21:16:34.25#ibcon#flushed, iclass 7, count 0 2006.201.21:16:34.25#ibcon#about to write, iclass 7, count 0 2006.201.21:16:34.25#ibcon#wrote, iclass 7, count 0 2006.201.21:16:34.25#ibcon#about to read 3, iclass 7, count 0 2006.201.21:16:34.27#ibcon#read 3, iclass 7, count 0 2006.201.21:16:34.27#ibcon#about to read 4, iclass 7, count 0 2006.201.21:16:34.27#ibcon#read 4, iclass 7, count 0 2006.201.21:16:34.27#ibcon#about to read 5, iclass 7, count 0 2006.201.21:16:34.27#ibcon#read 5, iclass 7, count 0 2006.201.21:16:34.27#ibcon#about to read 6, iclass 7, count 0 2006.201.21:16:34.27#ibcon#read 6, iclass 7, count 0 2006.201.21:16:34.27#ibcon#end of sib2, iclass 7, count 0 2006.201.21:16:34.27#ibcon#*mode == 0, iclass 7, count 0 2006.201.21:16:34.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.21:16:34.27#ibcon#[25=BW32\r\n] 2006.201.21:16:34.27#ibcon#*before write, iclass 7, count 0 2006.201.21:16:34.27#ibcon#enter sib2, iclass 7, count 0 2006.201.21:16:34.27#ibcon#flushed, iclass 7, count 0 2006.201.21:16:34.27#ibcon#about to write, iclass 7, count 0 2006.201.21:16:34.27#ibcon#wrote, iclass 7, count 0 2006.201.21:16:34.27#ibcon#about to read 3, iclass 7, count 0 2006.201.21:16:34.30#ibcon#read 3, iclass 7, count 0 2006.201.21:16:34.30#ibcon#about to read 4, iclass 7, count 0 2006.201.21:16:34.30#ibcon#read 4, iclass 7, count 0 2006.201.21:16:34.30#ibcon#about to read 5, iclass 7, count 0 2006.201.21:16:34.30#ibcon#read 5, iclass 7, count 0 2006.201.21:16:34.30#ibcon#about to read 6, iclass 7, count 0 2006.201.21:16:34.30#ibcon#read 6, iclass 7, count 0 2006.201.21:16:34.30#ibcon#end of sib2, iclass 7, count 0 2006.201.21:16:34.30#ibcon#*after write, iclass 7, count 0 2006.201.21:16:34.30#ibcon#*before return 0, iclass 7, count 0 2006.201.21:16:34.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:34.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:16:34.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.21:16:34.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.21:16:34.30$vck44/vbbw=wide 2006.201.21:16:34.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.21:16:34.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.21:16:34.30#ibcon#ireg 8 cls_cnt 0 2006.201.21:16:34.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:16:34.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:16:34.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:16:34.37#ibcon#enter wrdev, iclass 11, count 0 2006.201.21:16:34.37#ibcon#first serial, iclass 11, count 0 2006.201.21:16:34.37#ibcon#enter sib2, iclass 11, count 0 2006.201.21:16:34.37#ibcon#flushed, iclass 11, count 0 2006.201.21:16:34.37#ibcon#about to write, iclass 11, count 0 2006.201.21:16:34.37#ibcon#wrote, iclass 11, count 0 2006.201.21:16:34.37#ibcon#about to read 3, iclass 11, count 0 2006.201.21:16:34.39#ibcon#read 3, iclass 11, count 0 2006.201.21:16:34.39#ibcon#about to read 4, iclass 11, count 0 2006.201.21:16:34.39#ibcon#read 4, iclass 11, count 0 2006.201.21:16:34.39#ibcon#about to read 5, iclass 11, count 0 2006.201.21:16:34.39#ibcon#read 5, iclass 11, count 0 2006.201.21:16:34.39#ibcon#about to read 6, iclass 11, count 0 2006.201.21:16:34.39#ibcon#read 6, iclass 11, count 0 2006.201.21:16:34.39#ibcon#end of sib2, iclass 11, count 0 2006.201.21:16:34.39#ibcon#*mode == 0, iclass 11, count 0 2006.201.21:16:34.39#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.21:16:34.39#ibcon#[27=BW32\r\n] 2006.201.21:16:34.39#ibcon#*before write, iclass 11, count 0 2006.201.21:16:34.39#ibcon#enter sib2, iclass 11, count 0 2006.201.21:16:34.39#ibcon#flushed, iclass 11, count 0 2006.201.21:16:34.39#ibcon#about to write, iclass 11, count 0 2006.201.21:16:34.39#ibcon#wrote, iclass 11, count 0 2006.201.21:16:34.39#ibcon#about to read 3, iclass 11, count 0 2006.201.21:16:34.42#ibcon#read 3, iclass 11, count 0 2006.201.21:16:34.42#ibcon#about to read 4, iclass 11, count 0 2006.201.21:16:34.42#ibcon#read 4, iclass 11, count 0 2006.201.21:16:34.42#ibcon#about to read 5, iclass 11, count 0 2006.201.21:16:34.42#ibcon#read 5, iclass 11, count 0 2006.201.21:16:34.42#ibcon#about to read 6, iclass 11, count 0 2006.201.21:16:34.42#ibcon#read 6, iclass 11, count 0 2006.201.21:16:34.42#ibcon#end of sib2, iclass 11, count 0 2006.201.21:16:34.42#ibcon#*after write, iclass 11, count 0 2006.201.21:16:34.42#ibcon#*before return 0, iclass 11, count 0 2006.201.21:16:34.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:16:34.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:16:34.42#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.21:16:34.42#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.21:16:34.42$setupk4/ifdk4 2006.201.21:16:34.42$ifdk4/lo= 2006.201.21:16:34.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.21:16:34.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.21:16:34.42$ifdk4/patch= 2006.201.21:16:34.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.21:16:34.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.21:16:34.42$setupk4/!*+20s 2006.201.21:16:42.63#abcon#<5=/04 1.5 2.8 20.091001002.2\r\n> 2006.201.21:16:42.65#abcon#{5=INTERFACE CLEAR} 2006.201.21:16:42.71#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:16:43.13#trakl#Source acquired 2006.201.21:16:43.13#flagr#flagr/antenna,acquired 2006.201.21:16:48.89$setupk4/"tpicd 2006.201.21:16:48.89$setupk4/echo=off 2006.201.21:16:48.89$setupk4/xlog=off 2006.201.21:16:48.89:!2006.201.21:20:46 2006.201.21:20:46.00:preob 2006.201.21:20:47.14/onsource/TRACKING 2006.201.21:20:47.14:!2006.201.21:20:56 2006.201.21:20:56.00:"tape 2006.201.21:20:56.00:"st=record 2006.201.21:20:56.00:data_valid=on 2006.201.21:20:56.00:midob 2006.201.21:20:56.14/onsource/TRACKING 2006.201.21:20:56.14/wx/20.06,1002.2,100 2006.201.21:20:56.37/cable/+6.4822E-03 2006.201.21:20:57.46/va/01,08,usb,yes,51,54 2006.201.21:20:57.46/va/02,07,usb,yes,55,56 2006.201.21:20:57.46/va/03,08,usb,yes,50,52 2006.201.21:20:57.46/va/04,07,usb,yes,56,59 2006.201.21:20:57.46/va/05,04,usb,yes,51,52 2006.201.21:20:57.46/va/06,05,usb,yes,51,51 2006.201.21:20:57.46/va/07,05,usb,yes,50,52 2006.201.21:20:57.46/va/08,04,usb,yes,50,58 2006.201.21:20:57.69/valo/01,524.99,yes,locked 2006.201.21:20:57.69/valo/02,534.99,yes,locked 2006.201.21:20:57.69/valo/03,564.99,yes,locked 2006.201.21:20:57.69/valo/04,624.99,yes,locked 2006.201.21:20:57.69/valo/05,734.99,yes,locked 2006.201.21:20:57.69/valo/06,814.99,yes,locked 2006.201.21:20:57.69/valo/07,864.99,yes,locked 2006.201.21:20:57.69/valo/08,884.99,yes,locked 2006.201.21:20:58.78/vb/01,04,usb,yes,31,29 2006.201.21:20:58.78/vb/02,05,usb,yes,30,30 2006.201.21:20:58.78/vb/03,04,usb,yes,31,34 2006.201.21:20:58.78/vb/04,05,usb,yes,31,30 2006.201.21:20:58.78/vb/05,04,usb,yes,27,30 2006.201.21:20:58.78/vb/06,04,usb,yes,32,28 2006.201.21:20:58.78/vb/07,04,usb,yes,32,32 2006.201.21:20:58.78/vb/08,04,usb,yes,29,33 2006.201.21:20:59.02/vblo/01,629.99,yes,locked 2006.201.21:20:59.02/vblo/02,634.99,yes,locked 2006.201.21:20:59.02/vblo/03,649.99,yes,locked 2006.201.21:20:59.02/vblo/04,679.99,yes,locked 2006.201.21:20:59.02/vblo/05,709.99,yes,locked 2006.201.21:20:59.02/vblo/06,719.99,yes,locked 2006.201.21:20:59.02/vblo/07,734.99,yes,locked 2006.201.21:20:59.02/vblo/08,744.99,yes,locked 2006.201.21:20:59.17/vabw/8 2006.201.21:20:59.32/vbbw/8 2006.201.21:20:59.41/xfe/off,on,15.5 2006.201.21:20:59.81/ifatt/23,28,28,28 2006.201.21:21:00.07/fmout-gps/S +4.57E-07 2006.201.21:21:00.14:!2006.201.21:24:36 2006.201.21:24:36.00:data_valid=off 2006.201.21:24:36.00:"et 2006.201.21:24:36.00:!+3s 2006.201.21:24:39.02:"tape 2006.201.21:24:39.02:postob 2006.201.21:24:39.14/cable/+6.4825E-03 2006.201.21:24:39.14/wx/20.05,1002.2,100 2006.201.21:24:39.22/fmout-gps/S +4.55E-07 2006.201.21:24:39.22:scan_name=201-2127,jd0607,130 2006.201.21:24:39.23:source=2201+315,220314.98,314538.3,2000.0,ccw 2006.201.21:24:41.13#flagr#flagr/antenna,new-source 2006.201.21:24:41.13:checkk5 2006.201.21:24:41.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.21:24:41.87/chk_autoobs//k5ts2/ autoobs is running! 2006.201.21:24:42.25/chk_autoobs//k5ts3/ autoobs is running! 2006.201.21:24:42.62/chk_autoobs//k5ts4/ autoobs is running! 2006.201.21:24:42.98/chk_obsdata//k5ts1/T2012120??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.21:24:43.35/chk_obsdata//k5ts2/T2012120??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.21:24:43.72/chk_obsdata//k5ts3/T2012120??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.21:24:44.09/chk_obsdata//k5ts4/T2012120??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.21:24:44.77/k5log//k5ts1_log_newline 2006.201.21:24:45.46/k5log//k5ts2_log_newline 2006.201.21:24:46.15/k5log//k5ts3_log_newline 2006.201.21:24:46.84/k5log//k5ts4_log_newline 2006.201.21:24:46.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.21:24:46.86:setupk4=1 2006.201.21:24:46.86$setupk4/echo=on 2006.201.21:24:46.86$setupk4/pcalon 2006.201.21:24:46.86$pcalon/"no phase cal control is implemented here 2006.201.21:24:46.86$setupk4/"tpicd=stop 2006.201.21:24:46.86$setupk4/"rec=synch_on 2006.201.21:24:46.86$setupk4/"rec_mode=128 2006.201.21:24:46.86$setupk4/!* 2006.201.21:24:46.86$setupk4/recpk4 2006.201.21:24:46.86$recpk4/recpatch= 2006.201.21:24:46.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.21:24:46.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.21:24:46.87$setupk4/vck44 2006.201.21:24:46.87$vck44/valo=1,524.99 2006.201.21:24:46.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.21:24:46.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.21:24:46.87#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:46.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:46.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:46.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:46.87#ibcon#enter wrdev, iclass 28, count 0 2006.201.21:24:46.87#ibcon#first serial, iclass 28, count 0 2006.201.21:24:46.87#ibcon#enter sib2, iclass 28, count 0 2006.201.21:24:46.87#ibcon#flushed, iclass 28, count 0 2006.201.21:24:46.87#ibcon#about to write, iclass 28, count 0 2006.201.21:24:46.87#ibcon#wrote, iclass 28, count 0 2006.201.21:24:46.87#ibcon#about to read 3, iclass 28, count 0 2006.201.21:24:46.90#ibcon#read 3, iclass 28, count 0 2006.201.21:24:46.90#ibcon#about to read 4, iclass 28, count 0 2006.201.21:24:46.90#ibcon#read 4, iclass 28, count 0 2006.201.21:24:46.90#ibcon#about to read 5, iclass 28, count 0 2006.201.21:24:46.90#ibcon#read 5, iclass 28, count 0 2006.201.21:24:46.90#ibcon#about to read 6, iclass 28, count 0 2006.201.21:24:46.90#ibcon#read 6, iclass 28, count 0 2006.201.21:24:46.90#ibcon#end of sib2, iclass 28, count 0 2006.201.21:24:46.90#ibcon#*mode == 0, iclass 28, count 0 2006.201.21:24:46.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.21:24:46.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.21:24:46.90#ibcon#*before write, iclass 28, count 0 2006.201.21:24:46.90#ibcon#enter sib2, iclass 28, count 0 2006.201.21:24:46.90#ibcon#flushed, iclass 28, count 0 2006.201.21:24:46.90#ibcon#about to write, iclass 28, count 0 2006.201.21:24:46.90#ibcon#wrote, iclass 28, count 0 2006.201.21:24:46.90#ibcon#about to read 3, iclass 28, count 0 2006.201.21:24:46.95#ibcon#read 3, iclass 28, count 0 2006.201.21:24:46.95#ibcon#about to read 4, iclass 28, count 0 2006.201.21:24:46.95#ibcon#read 4, iclass 28, count 0 2006.201.21:24:46.95#ibcon#about to read 5, iclass 28, count 0 2006.201.21:24:46.95#ibcon#read 5, iclass 28, count 0 2006.201.21:24:46.95#ibcon#about to read 6, iclass 28, count 0 2006.201.21:24:46.95#ibcon#read 6, iclass 28, count 0 2006.201.21:24:46.95#ibcon#end of sib2, iclass 28, count 0 2006.201.21:24:46.95#ibcon#*after write, iclass 28, count 0 2006.201.21:24:46.95#ibcon#*before return 0, iclass 28, count 0 2006.201.21:24:46.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:46.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:46.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.21:24:46.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.21:24:46.95$vck44/va=1,8 2006.201.21:24:46.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.21:24:46.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.21:24:46.95#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:46.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:46.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:46.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:46.95#ibcon#enter wrdev, iclass 30, count 2 2006.201.21:24:46.95#ibcon#first serial, iclass 30, count 2 2006.201.21:24:46.95#ibcon#enter sib2, iclass 30, count 2 2006.201.21:24:46.95#ibcon#flushed, iclass 30, count 2 2006.201.21:24:46.95#ibcon#about to write, iclass 30, count 2 2006.201.21:24:46.95#ibcon#wrote, iclass 30, count 2 2006.201.21:24:46.95#ibcon#about to read 3, iclass 30, count 2 2006.201.21:24:46.97#ibcon#read 3, iclass 30, count 2 2006.201.21:24:46.97#ibcon#about to read 4, iclass 30, count 2 2006.201.21:24:46.97#ibcon#read 4, iclass 30, count 2 2006.201.21:24:46.97#ibcon#about to read 5, iclass 30, count 2 2006.201.21:24:46.97#ibcon#read 5, iclass 30, count 2 2006.201.21:24:46.97#ibcon#about to read 6, iclass 30, count 2 2006.201.21:24:46.97#ibcon#read 6, iclass 30, count 2 2006.201.21:24:46.97#ibcon#end of sib2, iclass 30, count 2 2006.201.21:24:46.97#ibcon#*mode == 0, iclass 30, count 2 2006.201.21:24:46.97#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.21:24:46.97#ibcon#[25=AT01-08\r\n] 2006.201.21:24:46.97#ibcon#*before write, iclass 30, count 2 2006.201.21:24:46.97#ibcon#enter sib2, iclass 30, count 2 2006.201.21:24:46.97#ibcon#flushed, iclass 30, count 2 2006.201.21:24:46.97#ibcon#about to write, iclass 30, count 2 2006.201.21:24:46.97#ibcon#wrote, iclass 30, count 2 2006.201.21:24:46.97#ibcon#about to read 3, iclass 30, count 2 2006.201.21:24:47.00#ibcon#read 3, iclass 30, count 2 2006.201.21:24:47.00#ibcon#about to read 4, iclass 30, count 2 2006.201.21:24:47.00#ibcon#read 4, iclass 30, count 2 2006.201.21:24:47.00#ibcon#about to read 5, iclass 30, count 2 2006.201.21:24:47.00#ibcon#read 5, iclass 30, count 2 2006.201.21:24:47.00#ibcon#about to read 6, iclass 30, count 2 2006.201.21:24:47.00#ibcon#read 6, iclass 30, count 2 2006.201.21:24:47.00#ibcon#end of sib2, iclass 30, count 2 2006.201.21:24:47.00#ibcon#*after write, iclass 30, count 2 2006.201.21:24:47.00#ibcon#*before return 0, iclass 30, count 2 2006.201.21:24:47.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:47.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:47.00#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.21:24:47.00#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:47.00#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:47.12#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:47.12#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:47.12#ibcon#enter wrdev, iclass 30, count 0 2006.201.21:24:47.12#ibcon#first serial, iclass 30, count 0 2006.201.21:24:47.12#ibcon#enter sib2, iclass 30, count 0 2006.201.21:24:47.12#ibcon#flushed, iclass 30, count 0 2006.201.21:24:47.12#ibcon#about to write, iclass 30, count 0 2006.201.21:24:47.12#ibcon#wrote, iclass 30, count 0 2006.201.21:24:47.12#ibcon#about to read 3, iclass 30, count 0 2006.201.21:24:47.14#ibcon#read 3, iclass 30, count 0 2006.201.21:24:47.14#ibcon#about to read 4, iclass 30, count 0 2006.201.21:24:47.14#ibcon#read 4, iclass 30, count 0 2006.201.21:24:47.14#ibcon#about to read 5, iclass 30, count 0 2006.201.21:24:47.14#ibcon#read 5, iclass 30, count 0 2006.201.21:24:47.14#ibcon#about to read 6, iclass 30, count 0 2006.201.21:24:47.14#ibcon#read 6, iclass 30, count 0 2006.201.21:24:47.14#ibcon#end of sib2, iclass 30, count 0 2006.201.21:24:47.14#ibcon#*mode == 0, iclass 30, count 0 2006.201.21:24:47.14#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.21:24:47.14#ibcon#[25=USB\r\n] 2006.201.21:24:47.14#ibcon#*before write, iclass 30, count 0 2006.201.21:24:47.14#ibcon#enter sib2, iclass 30, count 0 2006.201.21:24:47.14#ibcon#flushed, iclass 30, count 0 2006.201.21:24:47.14#ibcon#about to write, iclass 30, count 0 2006.201.21:24:47.14#ibcon#wrote, iclass 30, count 0 2006.201.21:24:47.14#ibcon#about to read 3, iclass 30, count 0 2006.201.21:24:47.17#ibcon#read 3, iclass 30, count 0 2006.201.21:24:47.17#ibcon#about to read 4, iclass 30, count 0 2006.201.21:24:47.17#ibcon#read 4, iclass 30, count 0 2006.201.21:24:47.17#ibcon#about to read 5, iclass 30, count 0 2006.201.21:24:47.17#ibcon#read 5, iclass 30, count 0 2006.201.21:24:47.17#ibcon#about to read 6, iclass 30, count 0 2006.201.21:24:47.17#ibcon#read 6, iclass 30, count 0 2006.201.21:24:47.17#ibcon#end of sib2, iclass 30, count 0 2006.201.21:24:47.17#ibcon#*after write, iclass 30, count 0 2006.201.21:24:47.17#ibcon#*before return 0, iclass 30, count 0 2006.201.21:24:47.17#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:47.17#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:47.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.21:24:47.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.21:24:47.17$vck44/valo=2,534.99 2006.201.21:24:47.17#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.21:24:47.17#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.21:24:47.17#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:47.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:47.17#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:47.17#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:47.17#ibcon#enter wrdev, iclass 32, count 0 2006.201.21:24:47.17#ibcon#first serial, iclass 32, count 0 2006.201.21:24:47.17#ibcon#enter sib2, iclass 32, count 0 2006.201.21:24:47.17#ibcon#flushed, iclass 32, count 0 2006.201.21:24:47.17#ibcon#about to write, iclass 32, count 0 2006.201.21:24:47.17#ibcon#wrote, iclass 32, count 0 2006.201.21:24:47.17#ibcon#about to read 3, iclass 32, count 0 2006.201.21:24:47.19#ibcon#read 3, iclass 32, count 0 2006.201.21:24:47.19#ibcon#about to read 4, iclass 32, count 0 2006.201.21:24:47.19#ibcon#read 4, iclass 32, count 0 2006.201.21:24:47.19#ibcon#about to read 5, iclass 32, count 0 2006.201.21:24:47.19#ibcon#read 5, iclass 32, count 0 2006.201.21:24:47.19#ibcon#about to read 6, iclass 32, count 0 2006.201.21:24:47.19#ibcon#read 6, iclass 32, count 0 2006.201.21:24:47.19#ibcon#end of sib2, iclass 32, count 0 2006.201.21:24:47.19#ibcon#*mode == 0, iclass 32, count 0 2006.201.21:24:47.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.21:24:47.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.21:24:47.19#ibcon#*before write, iclass 32, count 0 2006.201.21:24:47.19#ibcon#enter sib2, iclass 32, count 0 2006.201.21:24:47.19#ibcon#flushed, iclass 32, count 0 2006.201.21:24:47.19#ibcon#about to write, iclass 32, count 0 2006.201.21:24:47.19#ibcon#wrote, iclass 32, count 0 2006.201.21:24:47.19#ibcon#about to read 3, iclass 32, count 0 2006.201.21:24:47.24#ibcon#read 3, iclass 32, count 0 2006.201.21:24:47.24#ibcon#about to read 4, iclass 32, count 0 2006.201.21:24:47.24#ibcon#read 4, iclass 32, count 0 2006.201.21:24:47.24#ibcon#about to read 5, iclass 32, count 0 2006.201.21:24:47.24#ibcon#read 5, iclass 32, count 0 2006.201.21:24:47.24#ibcon#about to read 6, iclass 32, count 0 2006.201.21:24:47.24#ibcon#read 6, iclass 32, count 0 2006.201.21:24:47.24#ibcon#end of sib2, iclass 32, count 0 2006.201.21:24:47.24#ibcon#*after write, iclass 32, count 0 2006.201.21:24:47.24#ibcon#*before return 0, iclass 32, count 0 2006.201.21:24:47.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:47.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:47.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.21:24:47.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.21:24:47.24$vck44/va=2,7 2006.201.21:24:47.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.21:24:47.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.21:24:47.24#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:47.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:47.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:47.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:47.29#ibcon#enter wrdev, iclass 34, count 2 2006.201.21:24:47.29#ibcon#first serial, iclass 34, count 2 2006.201.21:24:47.29#ibcon#enter sib2, iclass 34, count 2 2006.201.21:24:47.29#ibcon#flushed, iclass 34, count 2 2006.201.21:24:47.29#ibcon#about to write, iclass 34, count 2 2006.201.21:24:47.29#ibcon#wrote, iclass 34, count 2 2006.201.21:24:47.29#ibcon#about to read 3, iclass 34, count 2 2006.201.21:24:47.31#ibcon#read 3, iclass 34, count 2 2006.201.21:24:47.31#ibcon#about to read 4, iclass 34, count 2 2006.201.21:24:47.31#ibcon#read 4, iclass 34, count 2 2006.201.21:24:47.31#ibcon#about to read 5, iclass 34, count 2 2006.201.21:24:47.31#ibcon#read 5, iclass 34, count 2 2006.201.21:24:47.31#ibcon#about to read 6, iclass 34, count 2 2006.201.21:24:47.31#ibcon#read 6, iclass 34, count 2 2006.201.21:24:47.31#ibcon#end of sib2, iclass 34, count 2 2006.201.21:24:47.31#ibcon#*mode == 0, iclass 34, count 2 2006.201.21:24:47.31#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.21:24:47.31#ibcon#[25=AT02-07\r\n] 2006.201.21:24:47.31#ibcon#*before write, iclass 34, count 2 2006.201.21:24:47.31#ibcon#enter sib2, iclass 34, count 2 2006.201.21:24:47.31#ibcon#flushed, iclass 34, count 2 2006.201.21:24:47.31#ibcon#about to write, iclass 34, count 2 2006.201.21:24:47.31#ibcon#wrote, iclass 34, count 2 2006.201.21:24:47.31#ibcon#about to read 3, iclass 34, count 2 2006.201.21:24:47.34#ibcon#read 3, iclass 34, count 2 2006.201.21:24:47.34#ibcon#about to read 4, iclass 34, count 2 2006.201.21:24:47.34#ibcon#read 4, iclass 34, count 2 2006.201.21:24:47.34#ibcon#about to read 5, iclass 34, count 2 2006.201.21:24:47.34#ibcon#read 5, iclass 34, count 2 2006.201.21:24:47.34#ibcon#about to read 6, iclass 34, count 2 2006.201.21:24:47.34#ibcon#read 6, iclass 34, count 2 2006.201.21:24:47.34#ibcon#end of sib2, iclass 34, count 2 2006.201.21:24:47.34#ibcon#*after write, iclass 34, count 2 2006.201.21:24:47.34#ibcon#*before return 0, iclass 34, count 2 2006.201.21:24:47.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:47.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:47.34#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.21:24:47.34#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:47.34#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:47.46#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:47.46#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:47.46#ibcon#enter wrdev, iclass 34, count 0 2006.201.21:24:47.46#ibcon#first serial, iclass 34, count 0 2006.201.21:24:47.46#ibcon#enter sib2, iclass 34, count 0 2006.201.21:24:47.46#ibcon#flushed, iclass 34, count 0 2006.201.21:24:47.46#ibcon#about to write, iclass 34, count 0 2006.201.21:24:47.46#ibcon#wrote, iclass 34, count 0 2006.201.21:24:47.46#ibcon#about to read 3, iclass 34, count 0 2006.201.21:24:47.48#ibcon#read 3, iclass 34, count 0 2006.201.21:24:47.48#ibcon#about to read 4, iclass 34, count 0 2006.201.21:24:47.48#ibcon#read 4, iclass 34, count 0 2006.201.21:24:47.48#ibcon#about to read 5, iclass 34, count 0 2006.201.21:24:47.48#ibcon#read 5, iclass 34, count 0 2006.201.21:24:47.48#ibcon#about to read 6, iclass 34, count 0 2006.201.21:24:47.48#ibcon#read 6, iclass 34, count 0 2006.201.21:24:47.48#ibcon#end of sib2, iclass 34, count 0 2006.201.21:24:47.48#ibcon#*mode == 0, iclass 34, count 0 2006.201.21:24:47.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.21:24:47.48#ibcon#[25=USB\r\n] 2006.201.21:24:47.48#ibcon#*before write, iclass 34, count 0 2006.201.21:24:47.48#ibcon#enter sib2, iclass 34, count 0 2006.201.21:24:47.48#ibcon#flushed, iclass 34, count 0 2006.201.21:24:47.48#ibcon#about to write, iclass 34, count 0 2006.201.21:24:47.48#ibcon#wrote, iclass 34, count 0 2006.201.21:24:47.48#ibcon#about to read 3, iclass 34, count 0 2006.201.21:24:47.51#ibcon#read 3, iclass 34, count 0 2006.201.21:24:47.51#ibcon#about to read 4, iclass 34, count 0 2006.201.21:24:47.51#ibcon#read 4, iclass 34, count 0 2006.201.21:24:47.51#ibcon#about to read 5, iclass 34, count 0 2006.201.21:24:47.51#ibcon#read 5, iclass 34, count 0 2006.201.21:24:47.51#ibcon#about to read 6, iclass 34, count 0 2006.201.21:24:47.51#ibcon#read 6, iclass 34, count 0 2006.201.21:24:47.51#ibcon#end of sib2, iclass 34, count 0 2006.201.21:24:47.51#ibcon#*after write, iclass 34, count 0 2006.201.21:24:47.51#ibcon#*before return 0, iclass 34, count 0 2006.201.21:24:47.51#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:47.51#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:47.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.21:24:47.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.21:24:47.51$vck44/valo=3,564.99 2006.201.21:24:47.51#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.21:24:47.51#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.21:24:47.51#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:47.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:47.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:47.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:47.51#ibcon#enter wrdev, iclass 36, count 0 2006.201.21:24:47.51#ibcon#first serial, iclass 36, count 0 2006.201.21:24:47.51#ibcon#enter sib2, iclass 36, count 0 2006.201.21:24:47.51#ibcon#flushed, iclass 36, count 0 2006.201.21:24:47.51#ibcon#about to write, iclass 36, count 0 2006.201.21:24:47.51#ibcon#wrote, iclass 36, count 0 2006.201.21:24:47.51#ibcon#about to read 3, iclass 36, count 0 2006.201.21:24:47.53#ibcon#read 3, iclass 36, count 0 2006.201.21:24:47.53#ibcon#about to read 4, iclass 36, count 0 2006.201.21:24:47.53#ibcon#read 4, iclass 36, count 0 2006.201.21:24:47.53#ibcon#about to read 5, iclass 36, count 0 2006.201.21:24:47.53#ibcon#read 5, iclass 36, count 0 2006.201.21:24:47.53#ibcon#about to read 6, iclass 36, count 0 2006.201.21:24:47.53#ibcon#read 6, iclass 36, count 0 2006.201.21:24:47.53#ibcon#end of sib2, iclass 36, count 0 2006.201.21:24:47.53#ibcon#*mode == 0, iclass 36, count 0 2006.201.21:24:47.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.21:24:47.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.21:24:47.53#ibcon#*before write, iclass 36, count 0 2006.201.21:24:47.53#ibcon#enter sib2, iclass 36, count 0 2006.201.21:24:47.53#ibcon#flushed, iclass 36, count 0 2006.201.21:24:47.53#ibcon#about to write, iclass 36, count 0 2006.201.21:24:47.53#ibcon#wrote, iclass 36, count 0 2006.201.21:24:47.53#ibcon#about to read 3, iclass 36, count 0 2006.201.21:24:47.58#ibcon#read 3, iclass 36, count 0 2006.201.21:24:47.58#ibcon#about to read 4, iclass 36, count 0 2006.201.21:24:47.58#ibcon#read 4, iclass 36, count 0 2006.201.21:24:47.58#ibcon#about to read 5, iclass 36, count 0 2006.201.21:24:47.58#ibcon#read 5, iclass 36, count 0 2006.201.21:24:47.58#ibcon#about to read 6, iclass 36, count 0 2006.201.21:24:47.58#ibcon#read 6, iclass 36, count 0 2006.201.21:24:47.58#ibcon#end of sib2, iclass 36, count 0 2006.201.21:24:47.58#ibcon#*after write, iclass 36, count 0 2006.201.21:24:47.58#ibcon#*before return 0, iclass 36, count 0 2006.201.21:24:47.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:47.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:47.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.21:24:47.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.21:24:47.58$vck44/va=3,8 2006.201.21:24:47.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.21:24:47.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.21:24:47.58#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:47.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:47.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:47.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:47.63#ibcon#enter wrdev, iclass 38, count 2 2006.201.21:24:47.63#ibcon#first serial, iclass 38, count 2 2006.201.21:24:47.63#ibcon#enter sib2, iclass 38, count 2 2006.201.21:24:47.63#ibcon#flushed, iclass 38, count 2 2006.201.21:24:47.63#ibcon#about to write, iclass 38, count 2 2006.201.21:24:47.63#ibcon#wrote, iclass 38, count 2 2006.201.21:24:47.63#ibcon#about to read 3, iclass 38, count 2 2006.201.21:24:47.65#ibcon#read 3, iclass 38, count 2 2006.201.21:24:47.65#ibcon#about to read 4, iclass 38, count 2 2006.201.21:24:47.65#ibcon#read 4, iclass 38, count 2 2006.201.21:24:47.65#ibcon#about to read 5, iclass 38, count 2 2006.201.21:24:47.65#ibcon#read 5, iclass 38, count 2 2006.201.21:24:47.65#ibcon#about to read 6, iclass 38, count 2 2006.201.21:24:47.65#ibcon#read 6, iclass 38, count 2 2006.201.21:24:47.65#ibcon#end of sib2, iclass 38, count 2 2006.201.21:24:47.65#ibcon#*mode == 0, iclass 38, count 2 2006.201.21:24:47.65#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.21:24:47.65#ibcon#[25=AT03-08\r\n] 2006.201.21:24:47.65#ibcon#*before write, iclass 38, count 2 2006.201.21:24:47.65#ibcon#enter sib2, iclass 38, count 2 2006.201.21:24:47.65#ibcon#flushed, iclass 38, count 2 2006.201.21:24:47.65#ibcon#about to write, iclass 38, count 2 2006.201.21:24:47.65#ibcon#wrote, iclass 38, count 2 2006.201.21:24:47.65#ibcon#about to read 3, iclass 38, count 2 2006.201.21:24:47.68#ibcon#read 3, iclass 38, count 2 2006.201.21:24:47.68#ibcon#about to read 4, iclass 38, count 2 2006.201.21:24:47.68#ibcon#read 4, iclass 38, count 2 2006.201.21:24:47.68#ibcon#about to read 5, iclass 38, count 2 2006.201.21:24:47.68#ibcon#read 5, iclass 38, count 2 2006.201.21:24:47.68#ibcon#about to read 6, iclass 38, count 2 2006.201.21:24:47.68#ibcon#read 6, iclass 38, count 2 2006.201.21:24:47.68#ibcon#end of sib2, iclass 38, count 2 2006.201.21:24:47.68#ibcon#*after write, iclass 38, count 2 2006.201.21:24:47.68#ibcon#*before return 0, iclass 38, count 2 2006.201.21:24:47.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:47.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:47.68#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.21:24:47.68#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:47.68#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:47.80#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:47.80#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:47.80#ibcon#enter wrdev, iclass 38, count 0 2006.201.21:24:47.80#ibcon#first serial, iclass 38, count 0 2006.201.21:24:47.80#ibcon#enter sib2, iclass 38, count 0 2006.201.21:24:47.80#ibcon#flushed, iclass 38, count 0 2006.201.21:24:47.80#ibcon#about to write, iclass 38, count 0 2006.201.21:24:47.80#ibcon#wrote, iclass 38, count 0 2006.201.21:24:47.80#ibcon#about to read 3, iclass 38, count 0 2006.201.21:24:47.82#ibcon#read 3, iclass 38, count 0 2006.201.21:24:47.82#ibcon#about to read 4, iclass 38, count 0 2006.201.21:24:47.82#ibcon#read 4, iclass 38, count 0 2006.201.21:24:47.82#ibcon#about to read 5, iclass 38, count 0 2006.201.21:24:47.82#ibcon#read 5, iclass 38, count 0 2006.201.21:24:47.82#ibcon#about to read 6, iclass 38, count 0 2006.201.21:24:47.82#ibcon#read 6, iclass 38, count 0 2006.201.21:24:47.82#ibcon#end of sib2, iclass 38, count 0 2006.201.21:24:47.82#ibcon#*mode == 0, iclass 38, count 0 2006.201.21:24:47.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.21:24:47.82#ibcon#[25=USB\r\n] 2006.201.21:24:47.82#ibcon#*before write, iclass 38, count 0 2006.201.21:24:47.82#ibcon#enter sib2, iclass 38, count 0 2006.201.21:24:47.82#ibcon#flushed, iclass 38, count 0 2006.201.21:24:47.82#ibcon#about to write, iclass 38, count 0 2006.201.21:24:47.82#ibcon#wrote, iclass 38, count 0 2006.201.21:24:47.82#ibcon#about to read 3, iclass 38, count 0 2006.201.21:24:47.85#ibcon#read 3, iclass 38, count 0 2006.201.21:24:47.85#ibcon#about to read 4, iclass 38, count 0 2006.201.21:24:47.85#ibcon#read 4, iclass 38, count 0 2006.201.21:24:47.85#ibcon#about to read 5, iclass 38, count 0 2006.201.21:24:47.85#ibcon#read 5, iclass 38, count 0 2006.201.21:24:47.85#ibcon#about to read 6, iclass 38, count 0 2006.201.21:24:47.85#ibcon#read 6, iclass 38, count 0 2006.201.21:24:47.85#ibcon#end of sib2, iclass 38, count 0 2006.201.21:24:47.85#ibcon#*after write, iclass 38, count 0 2006.201.21:24:47.85#ibcon#*before return 0, iclass 38, count 0 2006.201.21:24:47.85#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:47.85#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:47.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.21:24:47.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.21:24:47.85$vck44/valo=4,624.99 2006.201.21:24:47.85#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.21:24:47.85#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.21:24:47.85#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:47.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:47.85#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:47.85#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:47.85#ibcon#enter wrdev, iclass 40, count 0 2006.201.21:24:47.85#ibcon#first serial, iclass 40, count 0 2006.201.21:24:47.85#ibcon#enter sib2, iclass 40, count 0 2006.201.21:24:47.85#ibcon#flushed, iclass 40, count 0 2006.201.21:24:47.85#ibcon#about to write, iclass 40, count 0 2006.201.21:24:47.85#ibcon#wrote, iclass 40, count 0 2006.201.21:24:47.85#ibcon#about to read 3, iclass 40, count 0 2006.201.21:24:47.87#ibcon#read 3, iclass 40, count 0 2006.201.21:24:47.87#ibcon#about to read 4, iclass 40, count 0 2006.201.21:24:47.87#ibcon#read 4, iclass 40, count 0 2006.201.21:24:47.87#ibcon#about to read 5, iclass 40, count 0 2006.201.21:24:47.87#ibcon#read 5, iclass 40, count 0 2006.201.21:24:47.87#ibcon#about to read 6, iclass 40, count 0 2006.201.21:24:47.87#ibcon#read 6, iclass 40, count 0 2006.201.21:24:47.87#ibcon#end of sib2, iclass 40, count 0 2006.201.21:24:47.87#ibcon#*mode == 0, iclass 40, count 0 2006.201.21:24:47.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.21:24:47.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.21:24:47.87#ibcon#*before write, iclass 40, count 0 2006.201.21:24:47.87#ibcon#enter sib2, iclass 40, count 0 2006.201.21:24:47.87#ibcon#flushed, iclass 40, count 0 2006.201.21:24:47.87#ibcon#about to write, iclass 40, count 0 2006.201.21:24:47.87#ibcon#wrote, iclass 40, count 0 2006.201.21:24:47.87#ibcon#about to read 3, iclass 40, count 0 2006.201.21:24:47.92#ibcon#read 3, iclass 40, count 0 2006.201.21:24:47.92#ibcon#about to read 4, iclass 40, count 0 2006.201.21:24:47.92#ibcon#read 4, iclass 40, count 0 2006.201.21:24:47.92#ibcon#about to read 5, iclass 40, count 0 2006.201.21:24:47.92#ibcon#read 5, iclass 40, count 0 2006.201.21:24:47.92#ibcon#about to read 6, iclass 40, count 0 2006.201.21:24:47.92#ibcon#read 6, iclass 40, count 0 2006.201.21:24:47.92#ibcon#end of sib2, iclass 40, count 0 2006.201.21:24:47.92#ibcon#*after write, iclass 40, count 0 2006.201.21:24:47.92#ibcon#*before return 0, iclass 40, count 0 2006.201.21:24:47.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:47.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:47.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.21:24:47.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.21:24:47.92$vck44/va=4,7 2006.201.21:24:47.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.21:24:47.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.21:24:47.92#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:47.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:24:47.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:24:47.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:24:47.97#ibcon#enter wrdev, iclass 4, count 2 2006.201.21:24:47.97#ibcon#first serial, iclass 4, count 2 2006.201.21:24:47.97#ibcon#enter sib2, iclass 4, count 2 2006.201.21:24:47.97#ibcon#flushed, iclass 4, count 2 2006.201.21:24:47.97#ibcon#about to write, iclass 4, count 2 2006.201.21:24:47.97#ibcon#wrote, iclass 4, count 2 2006.201.21:24:47.97#ibcon#about to read 3, iclass 4, count 2 2006.201.21:24:47.99#ibcon#read 3, iclass 4, count 2 2006.201.21:24:47.99#ibcon#about to read 4, iclass 4, count 2 2006.201.21:24:47.99#ibcon#read 4, iclass 4, count 2 2006.201.21:24:47.99#ibcon#about to read 5, iclass 4, count 2 2006.201.21:24:47.99#ibcon#read 5, iclass 4, count 2 2006.201.21:24:47.99#ibcon#about to read 6, iclass 4, count 2 2006.201.21:24:47.99#ibcon#read 6, iclass 4, count 2 2006.201.21:24:47.99#ibcon#end of sib2, iclass 4, count 2 2006.201.21:24:47.99#ibcon#*mode == 0, iclass 4, count 2 2006.201.21:24:47.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.21:24:47.99#ibcon#[25=AT04-07\r\n] 2006.201.21:24:47.99#ibcon#*before write, iclass 4, count 2 2006.201.21:24:47.99#ibcon#enter sib2, iclass 4, count 2 2006.201.21:24:47.99#ibcon#flushed, iclass 4, count 2 2006.201.21:24:47.99#ibcon#about to write, iclass 4, count 2 2006.201.21:24:47.99#ibcon#wrote, iclass 4, count 2 2006.201.21:24:47.99#ibcon#about to read 3, iclass 4, count 2 2006.201.21:24:48.02#ibcon#read 3, iclass 4, count 2 2006.201.21:24:48.02#ibcon#about to read 4, iclass 4, count 2 2006.201.21:24:48.02#ibcon#read 4, iclass 4, count 2 2006.201.21:24:48.02#ibcon#about to read 5, iclass 4, count 2 2006.201.21:24:48.02#ibcon#read 5, iclass 4, count 2 2006.201.21:24:48.02#ibcon#about to read 6, iclass 4, count 2 2006.201.21:24:48.02#ibcon#read 6, iclass 4, count 2 2006.201.21:24:48.02#ibcon#end of sib2, iclass 4, count 2 2006.201.21:24:48.02#ibcon#*after write, iclass 4, count 2 2006.201.21:24:48.02#ibcon#*before return 0, iclass 4, count 2 2006.201.21:24:48.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:24:48.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:24:48.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.21:24:48.02#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:48.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:24:48.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:24:48.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:24:48.14#ibcon#enter wrdev, iclass 4, count 0 2006.201.21:24:48.14#ibcon#first serial, iclass 4, count 0 2006.201.21:24:48.14#ibcon#enter sib2, iclass 4, count 0 2006.201.21:24:48.14#ibcon#flushed, iclass 4, count 0 2006.201.21:24:48.14#ibcon#about to write, iclass 4, count 0 2006.201.21:24:48.14#ibcon#wrote, iclass 4, count 0 2006.201.21:24:48.14#ibcon#about to read 3, iclass 4, count 0 2006.201.21:24:48.16#ibcon#read 3, iclass 4, count 0 2006.201.21:24:48.16#ibcon#about to read 4, iclass 4, count 0 2006.201.21:24:48.16#ibcon#read 4, iclass 4, count 0 2006.201.21:24:48.16#ibcon#about to read 5, iclass 4, count 0 2006.201.21:24:48.16#ibcon#read 5, iclass 4, count 0 2006.201.21:24:48.16#ibcon#about to read 6, iclass 4, count 0 2006.201.21:24:48.16#ibcon#read 6, iclass 4, count 0 2006.201.21:24:48.16#ibcon#end of sib2, iclass 4, count 0 2006.201.21:24:48.16#ibcon#*mode == 0, iclass 4, count 0 2006.201.21:24:48.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.21:24:48.16#ibcon#[25=USB\r\n] 2006.201.21:24:48.16#ibcon#*before write, iclass 4, count 0 2006.201.21:24:48.16#ibcon#enter sib2, iclass 4, count 0 2006.201.21:24:48.16#ibcon#flushed, iclass 4, count 0 2006.201.21:24:48.16#ibcon#about to write, iclass 4, count 0 2006.201.21:24:48.16#ibcon#wrote, iclass 4, count 0 2006.201.21:24:48.16#ibcon#about to read 3, iclass 4, count 0 2006.201.21:24:48.19#ibcon#read 3, iclass 4, count 0 2006.201.21:24:48.19#ibcon#about to read 4, iclass 4, count 0 2006.201.21:24:48.19#ibcon#read 4, iclass 4, count 0 2006.201.21:24:48.19#ibcon#about to read 5, iclass 4, count 0 2006.201.21:24:48.19#ibcon#read 5, iclass 4, count 0 2006.201.21:24:48.19#ibcon#about to read 6, iclass 4, count 0 2006.201.21:24:48.19#ibcon#read 6, iclass 4, count 0 2006.201.21:24:48.19#ibcon#end of sib2, iclass 4, count 0 2006.201.21:24:48.19#ibcon#*after write, iclass 4, count 0 2006.201.21:24:48.19#ibcon#*before return 0, iclass 4, count 0 2006.201.21:24:48.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:24:48.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:24:48.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.21:24:48.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.21:24:48.19$vck44/valo=5,734.99 2006.201.21:24:48.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.21:24:48.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.21:24:48.19#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:48.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:24:48.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:24:48.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:24:48.19#ibcon#enter wrdev, iclass 6, count 0 2006.201.21:24:48.19#ibcon#first serial, iclass 6, count 0 2006.201.21:24:48.19#ibcon#enter sib2, iclass 6, count 0 2006.201.21:24:48.19#ibcon#flushed, iclass 6, count 0 2006.201.21:24:48.19#ibcon#about to write, iclass 6, count 0 2006.201.21:24:48.19#ibcon#wrote, iclass 6, count 0 2006.201.21:24:48.19#ibcon#about to read 3, iclass 6, count 0 2006.201.21:24:48.21#ibcon#read 3, iclass 6, count 0 2006.201.21:24:48.21#ibcon#about to read 4, iclass 6, count 0 2006.201.21:24:48.21#ibcon#read 4, iclass 6, count 0 2006.201.21:24:48.21#ibcon#about to read 5, iclass 6, count 0 2006.201.21:24:48.21#ibcon#read 5, iclass 6, count 0 2006.201.21:24:48.21#ibcon#about to read 6, iclass 6, count 0 2006.201.21:24:48.21#ibcon#read 6, iclass 6, count 0 2006.201.21:24:48.21#ibcon#end of sib2, iclass 6, count 0 2006.201.21:24:48.21#ibcon#*mode == 0, iclass 6, count 0 2006.201.21:24:48.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.21:24:48.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.21:24:48.21#ibcon#*before write, iclass 6, count 0 2006.201.21:24:48.21#ibcon#enter sib2, iclass 6, count 0 2006.201.21:24:48.21#ibcon#flushed, iclass 6, count 0 2006.201.21:24:48.21#ibcon#about to write, iclass 6, count 0 2006.201.21:24:48.21#ibcon#wrote, iclass 6, count 0 2006.201.21:24:48.21#ibcon#about to read 3, iclass 6, count 0 2006.201.21:24:48.25#ibcon#read 3, iclass 6, count 0 2006.201.21:24:48.25#ibcon#about to read 4, iclass 6, count 0 2006.201.21:24:48.25#ibcon#read 4, iclass 6, count 0 2006.201.21:24:48.25#ibcon#about to read 5, iclass 6, count 0 2006.201.21:24:48.25#ibcon#read 5, iclass 6, count 0 2006.201.21:24:48.25#ibcon#about to read 6, iclass 6, count 0 2006.201.21:24:48.25#ibcon#read 6, iclass 6, count 0 2006.201.21:24:48.25#ibcon#end of sib2, iclass 6, count 0 2006.201.21:24:48.25#ibcon#*after write, iclass 6, count 0 2006.201.21:24:48.25#ibcon#*before return 0, iclass 6, count 0 2006.201.21:24:48.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:24:48.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:24:48.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.21:24:48.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.21:24:48.25$vck44/va=5,4 2006.201.21:24:48.25#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.21:24:48.25#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.21:24:48.25#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:48.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:24:48.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:24:48.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:24:48.31#ibcon#enter wrdev, iclass 10, count 2 2006.201.21:24:48.31#ibcon#first serial, iclass 10, count 2 2006.201.21:24:48.31#ibcon#enter sib2, iclass 10, count 2 2006.201.21:24:48.31#ibcon#flushed, iclass 10, count 2 2006.201.21:24:48.31#ibcon#about to write, iclass 10, count 2 2006.201.21:24:48.31#ibcon#wrote, iclass 10, count 2 2006.201.21:24:48.31#ibcon#about to read 3, iclass 10, count 2 2006.201.21:24:48.33#ibcon#read 3, iclass 10, count 2 2006.201.21:24:48.33#ibcon#about to read 4, iclass 10, count 2 2006.201.21:24:48.33#ibcon#read 4, iclass 10, count 2 2006.201.21:24:48.33#ibcon#about to read 5, iclass 10, count 2 2006.201.21:24:48.33#ibcon#read 5, iclass 10, count 2 2006.201.21:24:48.33#ibcon#about to read 6, iclass 10, count 2 2006.201.21:24:48.33#ibcon#read 6, iclass 10, count 2 2006.201.21:24:48.33#ibcon#end of sib2, iclass 10, count 2 2006.201.21:24:48.33#ibcon#*mode == 0, iclass 10, count 2 2006.201.21:24:48.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.21:24:48.33#ibcon#[25=AT05-04\r\n] 2006.201.21:24:48.33#ibcon#*before write, iclass 10, count 2 2006.201.21:24:48.33#ibcon#enter sib2, iclass 10, count 2 2006.201.21:24:48.33#ibcon#flushed, iclass 10, count 2 2006.201.21:24:48.33#ibcon#about to write, iclass 10, count 2 2006.201.21:24:48.33#ibcon#wrote, iclass 10, count 2 2006.201.21:24:48.33#ibcon#about to read 3, iclass 10, count 2 2006.201.21:24:48.36#ibcon#read 3, iclass 10, count 2 2006.201.21:24:48.36#ibcon#about to read 4, iclass 10, count 2 2006.201.21:24:48.36#ibcon#read 4, iclass 10, count 2 2006.201.21:24:48.36#ibcon#about to read 5, iclass 10, count 2 2006.201.21:24:48.36#ibcon#read 5, iclass 10, count 2 2006.201.21:24:48.36#ibcon#about to read 6, iclass 10, count 2 2006.201.21:24:48.36#ibcon#read 6, iclass 10, count 2 2006.201.21:24:48.36#ibcon#end of sib2, iclass 10, count 2 2006.201.21:24:48.36#ibcon#*after write, iclass 10, count 2 2006.201.21:24:48.36#ibcon#*before return 0, iclass 10, count 2 2006.201.21:24:48.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:24:48.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:24:48.36#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.21:24:48.36#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:48.36#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:24:48.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:24:48.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:24:48.48#ibcon#enter wrdev, iclass 10, count 0 2006.201.21:24:48.48#ibcon#first serial, iclass 10, count 0 2006.201.21:24:48.48#ibcon#enter sib2, iclass 10, count 0 2006.201.21:24:48.48#ibcon#flushed, iclass 10, count 0 2006.201.21:24:48.48#ibcon#about to write, iclass 10, count 0 2006.201.21:24:48.48#ibcon#wrote, iclass 10, count 0 2006.201.21:24:48.48#ibcon#about to read 3, iclass 10, count 0 2006.201.21:24:48.50#ibcon#read 3, iclass 10, count 0 2006.201.21:24:48.50#ibcon#about to read 4, iclass 10, count 0 2006.201.21:24:48.50#ibcon#read 4, iclass 10, count 0 2006.201.21:24:48.50#ibcon#about to read 5, iclass 10, count 0 2006.201.21:24:48.50#ibcon#read 5, iclass 10, count 0 2006.201.21:24:48.50#ibcon#about to read 6, iclass 10, count 0 2006.201.21:24:48.50#ibcon#read 6, iclass 10, count 0 2006.201.21:24:48.50#ibcon#end of sib2, iclass 10, count 0 2006.201.21:24:48.50#ibcon#*mode == 0, iclass 10, count 0 2006.201.21:24:48.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.21:24:48.50#ibcon#[25=USB\r\n] 2006.201.21:24:48.50#ibcon#*before write, iclass 10, count 0 2006.201.21:24:48.50#ibcon#enter sib2, iclass 10, count 0 2006.201.21:24:48.50#ibcon#flushed, iclass 10, count 0 2006.201.21:24:48.50#ibcon#about to write, iclass 10, count 0 2006.201.21:24:48.50#ibcon#wrote, iclass 10, count 0 2006.201.21:24:48.50#ibcon#about to read 3, iclass 10, count 0 2006.201.21:24:48.53#ibcon#read 3, iclass 10, count 0 2006.201.21:24:48.53#ibcon#about to read 4, iclass 10, count 0 2006.201.21:24:48.53#ibcon#read 4, iclass 10, count 0 2006.201.21:24:48.53#ibcon#about to read 5, iclass 10, count 0 2006.201.21:24:48.53#ibcon#read 5, iclass 10, count 0 2006.201.21:24:48.53#ibcon#about to read 6, iclass 10, count 0 2006.201.21:24:48.53#ibcon#read 6, iclass 10, count 0 2006.201.21:24:48.53#ibcon#end of sib2, iclass 10, count 0 2006.201.21:24:48.53#ibcon#*after write, iclass 10, count 0 2006.201.21:24:48.53#ibcon#*before return 0, iclass 10, count 0 2006.201.21:24:48.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:24:48.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:24:48.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.21:24:48.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.21:24:48.53$vck44/valo=6,814.99 2006.201.21:24:48.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.21:24:48.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.21:24:48.53#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:48.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:48.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:48.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:48.53#ibcon#enter wrdev, iclass 12, count 0 2006.201.21:24:48.53#ibcon#first serial, iclass 12, count 0 2006.201.21:24:48.53#ibcon#enter sib2, iclass 12, count 0 2006.201.21:24:48.53#ibcon#flushed, iclass 12, count 0 2006.201.21:24:48.53#ibcon#about to write, iclass 12, count 0 2006.201.21:24:48.53#ibcon#wrote, iclass 12, count 0 2006.201.21:24:48.53#ibcon#about to read 3, iclass 12, count 0 2006.201.21:24:48.55#ibcon#read 3, iclass 12, count 0 2006.201.21:24:48.55#ibcon#about to read 4, iclass 12, count 0 2006.201.21:24:48.55#ibcon#read 4, iclass 12, count 0 2006.201.21:24:48.55#ibcon#about to read 5, iclass 12, count 0 2006.201.21:24:48.55#ibcon#read 5, iclass 12, count 0 2006.201.21:24:48.55#ibcon#about to read 6, iclass 12, count 0 2006.201.21:24:48.55#ibcon#read 6, iclass 12, count 0 2006.201.21:24:48.55#ibcon#end of sib2, iclass 12, count 0 2006.201.21:24:48.55#ibcon#*mode == 0, iclass 12, count 0 2006.201.21:24:48.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.21:24:48.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.21:24:48.55#ibcon#*before write, iclass 12, count 0 2006.201.21:24:48.55#ibcon#enter sib2, iclass 12, count 0 2006.201.21:24:48.55#ibcon#flushed, iclass 12, count 0 2006.201.21:24:48.55#ibcon#about to write, iclass 12, count 0 2006.201.21:24:48.55#ibcon#wrote, iclass 12, count 0 2006.201.21:24:48.55#ibcon#about to read 3, iclass 12, count 0 2006.201.21:24:48.60#ibcon#read 3, iclass 12, count 0 2006.201.21:24:48.60#ibcon#about to read 4, iclass 12, count 0 2006.201.21:24:48.60#ibcon#read 4, iclass 12, count 0 2006.201.21:24:48.60#ibcon#about to read 5, iclass 12, count 0 2006.201.21:24:48.60#ibcon#read 5, iclass 12, count 0 2006.201.21:24:48.60#ibcon#about to read 6, iclass 12, count 0 2006.201.21:24:48.60#ibcon#read 6, iclass 12, count 0 2006.201.21:24:48.60#ibcon#end of sib2, iclass 12, count 0 2006.201.21:24:48.60#ibcon#*after write, iclass 12, count 0 2006.201.21:24:48.60#ibcon#*before return 0, iclass 12, count 0 2006.201.21:24:48.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:48.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:48.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.21:24:48.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.21:24:48.60$vck44/va=6,5 2006.201.21:24:48.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.21:24:48.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.21:24:48.60#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:48.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:48.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:48.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:48.65#ibcon#enter wrdev, iclass 14, count 2 2006.201.21:24:48.65#ibcon#first serial, iclass 14, count 2 2006.201.21:24:48.65#ibcon#enter sib2, iclass 14, count 2 2006.201.21:24:48.65#ibcon#flushed, iclass 14, count 2 2006.201.21:24:48.65#ibcon#about to write, iclass 14, count 2 2006.201.21:24:48.65#ibcon#wrote, iclass 14, count 2 2006.201.21:24:48.65#ibcon#about to read 3, iclass 14, count 2 2006.201.21:24:48.67#ibcon#read 3, iclass 14, count 2 2006.201.21:24:48.67#ibcon#about to read 4, iclass 14, count 2 2006.201.21:24:48.67#ibcon#read 4, iclass 14, count 2 2006.201.21:24:48.67#ibcon#about to read 5, iclass 14, count 2 2006.201.21:24:48.67#ibcon#read 5, iclass 14, count 2 2006.201.21:24:48.67#ibcon#about to read 6, iclass 14, count 2 2006.201.21:24:48.67#ibcon#read 6, iclass 14, count 2 2006.201.21:24:48.67#ibcon#end of sib2, iclass 14, count 2 2006.201.21:24:48.67#ibcon#*mode == 0, iclass 14, count 2 2006.201.21:24:48.67#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.21:24:48.67#ibcon#[25=AT06-05\r\n] 2006.201.21:24:48.67#ibcon#*before write, iclass 14, count 2 2006.201.21:24:48.67#ibcon#enter sib2, iclass 14, count 2 2006.201.21:24:48.67#ibcon#flushed, iclass 14, count 2 2006.201.21:24:48.67#ibcon#about to write, iclass 14, count 2 2006.201.21:24:48.67#ibcon#wrote, iclass 14, count 2 2006.201.21:24:48.67#ibcon#about to read 3, iclass 14, count 2 2006.201.21:24:48.70#ibcon#read 3, iclass 14, count 2 2006.201.21:24:48.70#ibcon#about to read 4, iclass 14, count 2 2006.201.21:24:48.70#ibcon#read 4, iclass 14, count 2 2006.201.21:24:48.70#ibcon#about to read 5, iclass 14, count 2 2006.201.21:24:48.70#ibcon#read 5, iclass 14, count 2 2006.201.21:24:48.70#ibcon#about to read 6, iclass 14, count 2 2006.201.21:24:48.70#ibcon#read 6, iclass 14, count 2 2006.201.21:24:48.70#ibcon#end of sib2, iclass 14, count 2 2006.201.21:24:48.70#ibcon#*after write, iclass 14, count 2 2006.201.21:24:48.70#ibcon#*before return 0, iclass 14, count 2 2006.201.21:24:48.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:48.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:48.70#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.21:24:48.70#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:48.70#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:48.82#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:48.82#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:48.82#ibcon#enter wrdev, iclass 14, count 0 2006.201.21:24:48.82#ibcon#first serial, iclass 14, count 0 2006.201.21:24:48.82#ibcon#enter sib2, iclass 14, count 0 2006.201.21:24:48.82#ibcon#flushed, iclass 14, count 0 2006.201.21:24:48.82#ibcon#about to write, iclass 14, count 0 2006.201.21:24:48.82#ibcon#wrote, iclass 14, count 0 2006.201.21:24:48.82#ibcon#about to read 3, iclass 14, count 0 2006.201.21:24:48.84#ibcon#read 3, iclass 14, count 0 2006.201.21:24:48.84#ibcon#about to read 4, iclass 14, count 0 2006.201.21:24:48.84#ibcon#read 4, iclass 14, count 0 2006.201.21:24:48.84#ibcon#about to read 5, iclass 14, count 0 2006.201.21:24:48.84#ibcon#read 5, iclass 14, count 0 2006.201.21:24:48.84#ibcon#about to read 6, iclass 14, count 0 2006.201.21:24:48.84#ibcon#read 6, iclass 14, count 0 2006.201.21:24:48.84#ibcon#end of sib2, iclass 14, count 0 2006.201.21:24:48.84#ibcon#*mode == 0, iclass 14, count 0 2006.201.21:24:48.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.21:24:48.84#ibcon#[25=USB\r\n] 2006.201.21:24:48.84#ibcon#*before write, iclass 14, count 0 2006.201.21:24:48.84#ibcon#enter sib2, iclass 14, count 0 2006.201.21:24:48.84#ibcon#flushed, iclass 14, count 0 2006.201.21:24:48.84#ibcon#about to write, iclass 14, count 0 2006.201.21:24:48.84#ibcon#wrote, iclass 14, count 0 2006.201.21:24:48.84#ibcon#about to read 3, iclass 14, count 0 2006.201.21:24:48.87#ibcon#read 3, iclass 14, count 0 2006.201.21:24:48.87#ibcon#about to read 4, iclass 14, count 0 2006.201.21:24:48.87#ibcon#read 4, iclass 14, count 0 2006.201.21:24:48.87#ibcon#about to read 5, iclass 14, count 0 2006.201.21:24:48.87#ibcon#read 5, iclass 14, count 0 2006.201.21:24:48.87#ibcon#about to read 6, iclass 14, count 0 2006.201.21:24:48.87#ibcon#read 6, iclass 14, count 0 2006.201.21:24:48.87#ibcon#end of sib2, iclass 14, count 0 2006.201.21:24:48.87#ibcon#*after write, iclass 14, count 0 2006.201.21:24:48.87#ibcon#*before return 0, iclass 14, count 0 2006.201.21:24:48.87#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:48.87#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:48.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.21:24:48.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.21:24:48.87$vck44/valo=7,864.99 2006.201.21:24:48.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.21:24:48.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.21:24:48.87#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:48.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:48.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:48.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:48.87#ibcon#enter wrdev, iclass 16, count 0 2006.201.21:24:48.87#ibcon#first serial, iclass 16, count 0 2006.201.21:24:48.87#ibcon#enter sib2, iclass 16, count 0 2006.201.21:24:48.87#ibcon#flushed, iclass 16, count 0 2006.201.21:24:48.87#ibcon#about to write, iclass 16, count 0 2006.201.21:24:48.87#ibcon#wrote, iclass 16, count 0 2006.201.21:24:48.87#ibcon#about to read 3, iclass 16, count 0 2006.201.21:24:48.89#ibcon#read 3, iclass 16, count 0 2006.201.21:24:48.89#ibcon#about to read 4, iclass 16, count 0 2006.201.21:24:48.89#ibcon#read 4, iclass 16, count 0 2006.201.21:24:48.89#ibcon#about to read 5, iclass 16, count 0 2006.201.21:24:48.89#ibcon#read 5, iclass 16, count 0 2006.201.21:24:48.89#ibcon#about to read 6, iclass 16, count 0 2006.201.21:24:48.89#ibcon#read 6, iclass 16, count 0 2006.201.21:24:48.89#ibcon#end of sib2, iclass 16, count 0 2006.201.21:24:48.89#ibcon#*mode == 0, iclass 16, count 0 2006.201.21:24:48.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.21:24:48.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.21:24:48.89#ibcon#*before write, iclass 16, count 0 2006.201.21:24:48.89#ibcon#enter sib2, iclass 16, count 0 2006.201.21:24:48.89#ibcon#flushed, iclass 16, count 0 2006.201.21:24:48.89#ibcon#about to write, iclass 16, count 0 2006.201.21:24:48.89#ibcon#wrote, iclass 16, count 0 2006.201.21:24:48.89#ibcon#about to read 3, iclass 16, count 0 2006.201.21:24:48.93#ibcon#read 3, iclass 16, count 0 2006.201.21:24:48.93#ibcon#about to read 4, iclass 16, count 0 2006.201.21:24:48.93#ibcon#read 4, iclass 16, count 0 2006.201.21:24:48.93#ibcon#about to read 5, iclass 16, count 0 2006.201.21:24:48.93#ibcon#read 5, iclass 16, count 0 2006.201.21:24:48.93#ibcon#about to read 6, iclass 16, count 0 2006.201.21:24:48.93#ibcon#read 6, iclass 16, count 0 2006.201.21:24:48.93#ibcon#end of sib2, iclass 16, count 0 2006.201.21:24:48.93#ibcon#*after write, iclass 16, count 0 2006.201.21:24:48.93#ibcon#*before return 0, iclass 16, count 0 2006.201.21:24:48.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:48.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:48.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.21:24:48.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.21:24:48.93$vck44/va=7,5 2006.201.21:24:48.93#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.21:24:48.93#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.21:24:48.93#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:48.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:48.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:48.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:48.99#ibcon#enter wrdev, iclass 18, count 2 2006.201.21:24:48.99#ibcon#first serial, iclass 18, count 2 2006.201.21:24:48.99#ibcon#enter sib2, iclass 18, count 2 2006.201.21:24:48.99#ibcon#flushed, iclass 18, count 2 2006.201.21:24:48.99#ibcon#about to write, iclass 18, count 2 2006.201.21:24:48.99#ibcon#wrote, iclass 18, count 2 2006.201.21:24:48.99#ibcon#about to read 3, iclass 18, count 2 2006.201.21:24:49.01#ibcon#read 3, iclass 18, count 2 2006.201.21:24:49.01#ibcon#about to read 4, iclass 18, count 2 2006.201.21:24:49.01#ibcon#read 4, iclass 18, count 2 2006.201.21:24:49.01#ibcon#about to read 5, iclass 18, count 2 2006.201.21:24:49.01#ibcon#read 5, iclass 18, count 2 2006.201.21:24:49.01#ibcon#about to read 6, iclass 18, count 2 2006.201.21:24:49.01#ibcon#read 6, iclass 18, count 2 2006.201.21:24:49.01#ibcon#end of sib2, iclass 18, count 2 2006.201.21:24:49.01#ibcon#*mode == 0, iclass 18, count 2 2006.201.21:24:49.01#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.21:24:49.01#ibcon#[25=AT07-05\r\n] 2006.201.21:24:49.01#ibcon#*before write, iclass 18, count 2 2006.201.21:24:49.01#ibcon#enter sib2, iclass 18, count 2 2006.201.21:24:49.01#ibcon#flushed, iclass 18, count 2 2006.201.21:24:49.01#ibcon#about to write, iclass 18, count 2 2006.201.21:24:49.01#ibcon#wrote, iclass 18, count 2 2006.201.21:24:49.01#ibcon#about to read 3, iclass 18, count 2 2006.201.21:24:49.04#ibcon#read 3, iclass 18, count 2 2006.201.21:24:49.04#ibcon#about to read 4, iclass 18, count 2 2006.201.21:24:49.04#ibcon#read 4, iclass 18, count 2 2006.201.21:24:49.04#ibcon#about to read 5, iclass 18, count 2 2006.201.21:24:49.04#ibcon#read 5, iclass 18, count 2 2006.201.21:24:49.04#ibcon#about to read 6, iclass 18, count 2 2006.201.21:24:49.04#ibcon#read 6, iclass 18, count 2 2006.201.21:24:49.04#ibcon#end of sib2, iclass 18, count 2 2006.201.21:24:49.04#ibcon#*after write, iclass 18, count 2 2006.201.21:24:49.04#ibcon#*before return 0, iclass 18, count 2 2006.201.21:24:49.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:49.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:49.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.21:24:49.04#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:49.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:49.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:49.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:49.16#ibcon#enter wrdev, iclass 18, count 0 2006.201.21:24:49.16#ibcon#first serial, iclass 18, count 0 2006.201.21:24:49.16#ibcon#enter sib2, iclass 18, count 0 2006.201.21:24:49.16#ibcon#flushed, iclass 18, count 0 2006.201.21:24:49.16#ibcon#about to write, iclass 18, count 0 2006.201.21:24:49.16#ibcon#wrote, iclass 18, count 0 2006.201.21:24:49.16#ibcon#about to read 3, iclass 18, count 0 2006.201.21:24:49.18#ibcon#read 3, iclass 18, count 0 2006.201.21:24:49.18#ibcon#about to read 4, iclass 18, count 0 2006.201.21:24:49.18#ibcon#read 4, iclass 18, count 0 2006.201.21:24:49.18#ibcon#about to read 5, iclass 18, count 0 2006.201.21:24:49.18#ibcon#read 5, iclass 18, count 0 2006.201.21:24:49.18#ibcon#about to read 6, iclass 18, count 0 2006.201.21:24:49.18#ibcon#read 6, iclass 18, count 0 2006.201.21:24:49.18#ibcon#end of sib2, iclass 18, count 0 2006.201.21:24:49.18#ibcon#*mode == 0, iclass 18, count 0 2006.201.21:24:49.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.21:24:49.18#ibcon#[25=USB\r\n] 2006.201.21:24:49.18#ibcon#*before write, iclass 18, count 0 2006.201.21:24:49.18#ibcon#enter sib2, iclass 18, count 0 2006.201.21:24:49.18#ibcon#flushed, iclass 18, count 0 2006.201.21:24:49.18#ibcon#about to write, iclass 18, count 0 2006.201.21:24:49.18#ibcon#wrote, iclass 18, count 0 2006.201.21:24:49.18#ibcon#about to read 3, iclass 18, count 0 2006.201.21:24:49.21#ibcon#read 3, iclass 18, count 0 2006.201.21:24:49.21#ibcon#about to read 4, iclass 18, count 0 2006.201.21:24:49.21#ibcon#read 4, iclass 18, count 0 2006.201.21:24:49.21#ibcon#about to read 5, iclass 18, count 0 2006.201.21:24:49.21#ibcon#read 5, iclass 18, count 0 2006.201.21:24:49.21#ibcon#about to read 6, iclass 18, count 0 2006.201.21:24:49.21#ibcon#read 6, iclass 18, count 0 2006.201.21:24:49.21#ibcon#end of sib2, iclass 18, count 0 2006.201.21:24:49.21#ibcon#*after write, iclass 18, count 0 2006.201.21:24:49.21#ibcon#*before return 0, iclass 18, count 0 2006.201.21:24:49.21#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:49.21#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:49.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.21:24:49.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.21:24:49.21$vck44/valo=8,884.99 2006.201.21:24:49.21#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.21:24:49.21#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.21:24:49.21#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:49.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:49.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:49.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:49.21#ibcon#enter wrdev, iclass 20, count 0 2006.201.21:24:49.21#ibcon#first serial, iclass 20, count 0 2006.201.21:24:49.21#ibcon#enter sib2, iclass 20, count 0 2006.201.21:24:49.21#ibcon#flushed, iclass 20, count 0 2006.201.21:24:49.21#ibcon#about to write, iclass 20, count 0 2006.201.21:24:49.21#ibcon#wrote, iclass 20, count 0 2006.201.21:24:49.21#ibcon#about to read 3, iclass 20, count 0 2006.201.21:24:49.23#ibcon#read 3, iclass 20, count 0 2006.201.21:24:49.23#ibcon#about to read 4, iclass 20, count 0 2006.201.21:24:49.23#ibcon#read 4, iclass 20, count 0 2006.201.21:24:49.23#ibcon#about to read 5, iclass 20, count 0 2006.201.21:24:49.23#ibcon#read 5, iclass 20, count 0 2006.201.21:24:49.23#ibcon#about to read 6, iclass 20, count 0 2006.201.21:24:49.23#ibcon#read 6, iclass 20, count 0 2006.201.21:24:49.23#ibcon#end of sib2, iclass 20, count 0 2006.201.21:24:49.23#ibcon#*mode == 0, iclass 20, count 0 2006.201.21:24:49.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.21:24:49.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.21:24:49.23#ibcon#*before write, iclass 20, count 0 2006.201.21:24:49.23#ibcon#enter sib2, iclass 20, count 0 2006.201.21:24:49.23#ibcon#flushed, iclass 20, count 0 2006.201.21:24:49.23#ibcon#about to write, iclass 20, count 0 2006.201.21:24:49.23#ibcon#wrote, iclass 20, count 0 2006.201.21:24:49.23#ibcon#about to read 3, iclass 20, count 0 2006.201.21:24:49.27#ibcon#read 3, iclass 20, count 0 2006.201.21:24:49.27#ibcon#about to read 4, iclass 20, count 0 2006.201.21:24:49.27#ibcon#read 4, iclass 20, count 0 2006.201.21:24:49.27#ibcon#about to read 5, iclass 20, count 0 2006.201.21:24:49.27#ibcon#read 5, iclass 20, count 0 2006.201.21:24:49.27#ibcon#about to read 6, iclass 20, count 0 2006.201.21:24:49.27#ibcon#read 6, iclass 20, count 0 2006.201.21:24:49.27#ibcon#end of sib2, iclass 20, count 0 2006.201.21:24:49.27#ibcon#*after write, iclass 20, count 0 2006.201.21:24:49.27#ibcon#*before return 0, iclass 20, count 0 2006.201.21:24:49.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:49.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:49.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.21:24:49.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.21:24:49.27$vck44/va=8,4 2006.201.21:24:49.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.21:24:49.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.21:24:49.27#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:49.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:49.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:49.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:49.33#ibcon#enter wrdev, iclass 22, count 2 2006.201.21:24:49.33#ibcon#first serial, iclass 22, count 2 2006.201.21:24:49.33#ibcon#enter sib2, iclass 22, count 2 2006.201.21:24:49.33#ibcon#flushed, iclass 22, count 2 2006.201.21:24:49.33#ibcon#about to write, iclass 22, count 2 2006.201.21:24:49.33#ibcon#wrote, iclass 22, count 2 2006.201.21:24:49.33#ibcon#about to read 3, iclass 22, count 2 2006.201.21:24:49.35#ibcon#read 3, iclass 22, count 2 2006.201.21:24:49.35#ibcon#about to read 4, iclass 22, count 2 2006.201.21:24:49.35#ibcon#read 4, iclass 22, count 2 2006.201.21:24:49.35#ibcon#about to read 5, iclass 22, count 2 2006.201.21:24:49.35#ibcon#read 5, iclass 22, count 2 2006.201.21:24:49.35#ibcon#about to read 6, iclass 22, count 2 2006.201.21:24:49.35#ibcon#read 6, iclass 22, count 2 2006.201.21:24:49.35#ibcon#end of sib2, iclass 22, count 2 2006.201.21:24:49.35#ibcon#*mode == 0, iclass 22, count 2 2006.201.21:24:49.35#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.21:24:49.35#ibcon#[25=AT08-04\r\n] 2006.201.21:24:49.35#ibcon#*before write, iclass 22, count 2 2006.201.21:24:49.35#ibcon#enter sib2, iclass 22, count 2 2006.201.21:24:49.35#ibcon#flushed, iclass 22, count 2 2006.201.21:24:49.35#ibcon#about to write, iclass 22, count 2 2006.201.21:24:49.35#ibcon#wrote, iclass 22, count 2 2006.201.21:24:49.35#ibcon#about to read 3, iclass 22, count 2 2006.201.21:24:49.38#ibcon#read 3, iclass 22, count 2 2006.201.21:24:49.38#ibcon#about to read 4, iclass 22, count 2 2006.201.21:24:49.38#ibcon#read 4, iclass 22, count 2 2006.201.21:24:49.38#ibcon#about to read 5, iclass 22, count 2 2006.201.21:24:49.38#ibcon#read 5, iclass 22, count 2 2006.201.21:24:49.38#ibcon#about to read 6, iclass 22, count 2 2006.201.21:24:49.38#ibcon#read 6, iclass 22, count 2 2006.201.21:24:49.38#ibcon#end of sib2, iclass 22, count 2 2006.201.21:24:49.38#ibcon#*after write, iclass 22, count 2 2006.201.21:24:49.38#ibcon#*before return 0, iclass 22, count 2 2006.201.21:24:49.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:49.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:49.38#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.21:24:49.38#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:49.38#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:49.50#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:49.50#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:49.50#ibcon#enter wrdev, iclass 22, count 0 2006.201.21:24:49.50#ibcon#first serial, iclass 22, count 0 2006.201.21:24:49.50#ibcon#enter sib2, iclass 22, count 0 2006.201.21:24:49.50#ibcon#flushed, iclass 22, count 0 2006.201.21:24:49.50#ibcon#about to write, iclass 22, count 0 2006.201.21:24:49.50#ibcon#wrote, iclass 22, count 0 2006.201.21:24:49.50#ibcon#about to read 3, iclass 22, count 0 2006.201.21:24:49.52#ibcon#read 3, iclass 22, count 0 2006.201.21:24:49.52#ibcon#about to read 4, iclass 22, count 0 2006.201.21:24:49.52#ibcon#read 4, iclass 22, count 0 2006.201.21:24:49.52#ibcon#about to read 5, iclass 22, count 0 2006.201.21:24:49.52#ibcon#read 5, iclass 22, count 0 2006.201.21:24:49.52#ibcon#about to read 6, iclass 22, count 0 2006.201.21:24:49.52#ibcon#read 6, iclass 22, count 0 2006.201.21:24:49.52#ibcon#end of sib2, iclass 22, count 0 2006.201.21:24:49.52#ibcon#*mode == 0, iclass 22, count 0 2006.201.21:24:49.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.21:24:49.52#ibcon#[25=USB\r\n] 2006.201.21:24:49.52#ibcon#*before write, iclass 22, count 0 2006.201.21:24:49.52#ibcon#enter sib2, iclass 22, count 0 2006.201.21:24:49.52#ibcon#flushed, iclass 22, count 0 2006.201.21:24:49.52#ibcon#about to write, iclass 22, count 0 2006.201.21:24:49.52#ibcon#wrote, iclass 22, count 0 2006.201.21:24:49.52#ibcon#about to read 3, iclass 22, count 0 2006.201.21:24:49.55#ibcon#read 3, iclass 22, count 0 2006.201.21:24:49.55#ibcon#about to read 4, iclass 22, count 0 2006.201.21:24:49.55#ibcon#read 4, iclass 22, count 0 2006.201.21:24:49.55#ibcon#about to read 5, iclass 22, count 0 2006.201.21:24:49.55#ibcon#read 5, iclass 22, count 0 2006.201.21:24:49.55#ibcon#about to read 6, iclass 22, count 0 2006.201.21:24:49.55#ibcon#read 6, iclass 22, count 0 2006.201.21:24:49.55#ibcon#end of sib2, iclass 22, count 0 2006.201.21:24:49.55#ibcon#*after write, iclass 22, count 0 2006.201.21:24:49.55#ibcon#*before return 0, iclass 22, count 0 2006.201.21:24:49.55#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:49.55#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:49.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.21:24:49.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.21:24:49.55$vck44/vblo=1,629.99 2006.201.21:24:49.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.21:24:49.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.21:24:49.55#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:49.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:49.55#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:49.55#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:49.55#ibcon#enter wrdev, iclass 24, count 0 2006.201.21:24:49.55#ibcon#first serial, iclass 24, count 0 2006.201.21:24:49.55#ibcon#enter sib2, iclass 24, count 0 2006.201.21:24:49.55#ibcon#flushed, iclass 24, count 0 2006.201.21:24:49.55#ibcon#about to write, iclass 24, count 0 2006.201.21:24:49.55#ibcon#wrote, iclass 24, count 0 2006.201.21:24:49.55#ibcon#about to read 3, iclass 24, count 0 2006.201.21:24:49.57#ibcon#read 3, iclass 24, count 0 2006.201.21:24:49.57#ibcon#about to read 4, iclass 24, count 0 2006.201.21:24:49.57#ibcon#read 4, iclass 24, count 0 2006.201.21:24:49.57#ibcon#about to read 5, iclass 24, count 0 2006.201.21:24:49.57#ibcon#read 5, iclass 24, count 0 2006.201.21:24:49.57#ibcon#about to read 6, iclass 24, count 0 2006.201.21:24:49.57#ibcon#read 6, iclass 24, count 0 2006.201.21:24:49.57#ibcon#end of sib2, iclass 24, count 0 2006.201.21:24:49.57#ibcon#*mode == 0, iclass 24, count 0 2006.201.21:24:49.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.21:24:49.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.21:24:49.57#ibcon#*before write, iclass 24, count 0 2006.201.21:24:49.57#ibcon#enter sib2, iclass 24, count 0 2006.201.21:24:49.57#ibcon#flushed, iclass 24, count 0 2006.201.21:24:49.57#ibcon#about to write, iclass 24, count 0 2006.201.21:24:49.57#ibcon#wrote, iclass 24, count 0 2006.201.21:24:49.57#ibcon#about to read 3, iclass 24, count 0 2006.201.21:24:49.62#ibcon#read 3, iclass 24, count 0 2006.201.21:24:49.62#ibcon#about to read 4, iclass 24, count 0 2006.201.21:24:49.62#ibcon#read 4, iclass 24, count 0 2006.201.21:24:49.62#ibcon#about to read 5, iclass 24, count 0 2006.201.21:24:49.62#ibcon#read 5, iclass 24, count 0 2006.201.21:24:49.62#ibcon#about to read 6, iclass 24, count 0 2006.201.21:24:49.62#ibcon#read 6, iclass 24, count 0 2006.201.21:24:49.62#ibcon#end of sib2, iclass 24, count 0 2006.201.21:24:49.62#ibcon#*after write, iclass 24, count 0 2006.201.21:24:49.62#ibcon#*before return 0, iclass 24, count 0 2006.201.21:24:49.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:49.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:49.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.21:24:49.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.21:24:49.62$vck44/vb=1,4 2006.201.21:24:49.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.21:24:49.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.21:24:49.62#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:49.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:24:49.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:24:49.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:24:49.62#ibcon#enter wrdev, iclass 26, count 2 2006.201.21:24:49.62#ibcon#first serial, iclass 26, count 2 2006.201.21:24:49.62#ibcon#enter sib2, iclass 26, count 2 2006.201.21:24:49.62#ibcon#flushed, iclass 26, count 2 2006.201.21:24:49.62#ibcon#about to write, iclass 26, count 2 2006.201.21:24:49.62#ibcon#wrote, iclass 26, count 2 2006.201.21:24:49.62#ibcon#about to read 3, iclass 26, count 2 2006.201.21:24:49.64#ibcon#read 3, iclass 26, count 2 2006.201.21:24:49.64#ibcon#about to read 4, iclass 26, count 2 2006.201.21:24:49.64#ibcon#read 4, iclass 26, count 2 2006.201.21:24:49.64#ibcon#about to read 5, iclass 26, count 2 2006.201.21:24:49.64#ibcon#read 5, iclass 26, count 2 2006.201.21:24:49.64#ibcon#about to read 6, iclass 26, count 2 2006.201.21:24:49.64#ibcon#read 6, iclass 26, count 2 2006.201.21:24:49.64#ibcon#end of sib2, iclass 26, count 2 2006.201.21:24:49.64#ibcon#*mode == 0, iclass 26, count 2 2006.201.21:24:49.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.21:24:49.64#ibcon#[27=AT01-04\r\n] 2006.201.21:24:49.64#ibcon#*before write, iclass 26, count 2 2006.201.21:24:49.64#ibcon#enter sib2, iclass 26, count 2 2006.201.21:24:49.64#ibcon#flushed, iclass 26, count 2 2006.201.21:24:49.64#ibcon#about to write, iclass 26, count 2 2006.201.21:24:49.64#ibcon#wrote, iclass 26, count 2 2006.201.21:24:49.64#ibcon#about to read 3, iclass 26, count 2 2006.201.21:24:49.67#ibcon#read 3, iclass 26, count 2 2006.201.21:24:49.67#ibcon#about to read 4, iclass 26, count 2 2006.201.21:24:49.67#ibcon#read 4, iclass 26, count 2 2006.201.21:24:49.67#ibcon#about to read 5, iclass 26, count 2 2006.201.21:24:49.67#ibcon#read 5, iclass 26, count 2 2006.201.21:24:49.67#ibcon#about to read 6, iclass 26, count 2 2006.201.21:24:49.67#ibcon#read 6, iclass 26, count 2 2006.201.21:24:49.67#ibcon#end of sib2, iclass 26, count 2 2006.201.21:24:49.67#ibcon#*after write, iclass 26, count 2 2006.201.21:24:49.67#ibcon#*before return 0, iclass 26, count 2 2006.201.21:24:49.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:24:49.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:24:49.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.21:24:49.67#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:49.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:24:49.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:24:49.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:24:49.79#ibcon#enter wrdev, iclass 26, count 0 2006.201.21:24:49.79#ibcon#first serial, iclass 26, count 0 2006.201.21:24:49.79#ibcon#enter sib2, iclass 26, count 0 2006.201.21:24:49.79#ibcon#flushed, iclass 26, count 0 2006.201.21:24:49.79#ibcon#about to write, iclass 26, count 0 2006.201.21:24:49.79#ibcon#wrote, iclass 26, count 0 2006.201.21:24:49.79#ibcon#about to read 3, iclass 26, count 0 2006.201.21:24:49.81#ibcon#read 3, iclass 26, count 0 2006.201.21:24:49.81#ibcon#about to read 4, iclass 26, count 0 2006.201.21:24:49.81#ibcon#read 4, iclass 26, count 0 2006.201.21:24:49.81#ibcon#about to read 5, iclass 26, count 0 2006.201.21:24:49.81#ibcon#read 5, iclass 26, count 0 2006.201.21:24:49.81#ibcon#about to read 6, iclass 26, count 0 2006.201.21:24:49.81#ibcon#read 6, iclass 26, count 0 2006.201.21:24:49.81#ibcon#end of sib2, iclass 26, count 0 2006.201.21:24:49.81#ibcon#*mode == 0, iclass 26, count 0 2006.201.21:24:49.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.21:24:49.81#ibcon#[27=USB\r\n] 2006.201.21:24:49.81#ibcon#*before write, iclass 26, count 0 2006.201.21:24:49.81#ibcon#enter sib2, iclass 26, count 0 2006.201.21:24:49.81#ibcon#flushed, iclass 26, count 0 2006.201.21:24:49.81#ibcon#about to write, iclass 26, count 0 2006.201.21:24:49.81#ibcon#wrote, iclass 26, count 0 2006.201.21:24:49.81#ibcon#about to read 3, iclass 26, count 0 2006.201.21:24:49.84#ibcon#read 3, iclass 26, count 0 2006.201.21:24:49.84#ibcon#about to read 4, iclass 26, count 0 2006.201.21:24:49.84#ibcon#read 4, iclass 26, count 0 2006.201.21:24:49.84#ibcon#about to read 5, iclass 26, count 0 2006.201.21:24:49.84#ibcon#read 5, iclass 26, count 0 2006.201.21:24:49.84#ibcon#about to read 6, iclass 26, count 0 2006.201.21:24:49.84#ibcon#read 6, iclass 26, count 0 2006.201.21:24:49.84#ibcon#end of sib2, iclass 26, count 0 2006.201.21:24:49.84#ibcon#*after write, iclass 26, count 0 2006.201.21:24:49.84#ibcon#*before return 0, iclass 26, count 0 2006.201.21:24:49.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:24:49.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:24:49.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.21:24:49.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.21:24:49.84$vck44/vblo=2,634.99 2006.201.21:24:49.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.21:24:49.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.21:24:49.84#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:49.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:49.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:49.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:49.84#ibcon#enter wrdev, iclass 28, count 0 2006.201.21:24:49.84#ibcon#first serial, iclass 28, count 0 2006.201.21:24:49.84#ibcon#enter sib2, iclass 28, count 0 2006.201.21:24:49.84#ibcon#flushed, iclass 28, count 0 2006.201.21:24:49.84#ibcon#about to write, iclass 28, count 0 2006.201.21:24:49.84#ibcon#wrote, iclass 28, count 0 2006.201.21:24:49.84#ibcon#about to read 3, iclass 28, count 0 2006.201.21:24:49.86#ibcon#read 3, iclass 28, count 0 2006.201.21:24:49.86#ibcon#about to read 4, iclass 28, count 0 2006.201.21:24:49.86#ibcon#read 4, iclass 28, count 0 2006.201.21:24:49.86#ibcon#about to read 5, iclass 28, count 0 2006.201.21:24:49.86#ibcon#read 5, iclass 28, count 0 2006.201.21:24:49.86#ibcon#about to read 6, iclass 28, count 0 2006.201.21:24:49.86#ibcon#read 6, iclass 28, count 0 2006.201.21:24:49.86#ibcon#end of sib2, iclass 28, count 0 2006.201.21:24:49.86#ibcon#*mode == 0, iclass 28, count 0 2006.201.21:24:49.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.21:24:49.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.21:24:49.86#ibcon#*before write, iclass 28, count 0 2006.201.21:24:49.86#ibcon#enter sib2, iclass 28, count 0 2006.201.21:24:49.86#ibcon#flushed, iclass 28, count 0 2006.201.21:24:49.86#ibcon#about to write, iclass 28, count 0 2006.201.21:24:49.86#ibcon#wrote, iclass 28, count 0 2006.201.21:24:49.86#ibcon#about to read 3, iclass 28, count 0 2006.201.21:24:49.90#ibcon#read 3, iclass 28, count 0 2006.201.21:24:49.90#ibcon#about to read 4, iclass 28, count 0 2006.201.21:24:49.90#ibcon#read 4, iclass 28, count 0 2006.201.21:24:49.90#ibcon#about to read 5, iclass 28, count 0 2006.201.21:24:49.90#ibcon#read 5, iclass 28, count 0 2006.201.21:24:49.90#ibcon#about to read 6, iclass 28, count 0 2006.201.21:24:49.90#ibcon#read 6, iclass 28, count 0 2006.201.21:24:49.90#ibcon#end of sib2, iclass 28, count 0 2006.201.21:24:49.90#ibcon#*after write, iclass 28, count 0 2006.201.21:24:49.90#ibcon#*before return 0, iclass 28, count 0 2006.201.21:24:49.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:49.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:24:49.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.21:24:49.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.21:24:49.90$vck44/vb=2,5 2006.201.21:24:49.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.21:24:49.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.21:24:49.90#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:49.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:49.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:49.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:49.96#ibcon#enter wrdev, iclass 30, count 2 2006.201.21:24:49.96#ibcon#first serial, iclass 30, count 2 2006.201.21:24:49.96#ibcon#enter sib2, iclass 30, count 2 2006.201.21:24:49.96#ibcon#flushed, iclass 30, count 2 2006.201.21:24:49.96#ibcon#about to write, iclass 30, count 2 2006.201.21:24:49.96#ibcon#wrote, iclass 30, count 2 2006.201.21:24:49.96#ibcon#about to read 3, iclass 30, count 2 2006.201.21:24:49.98#ibcon#read 3, iclass 30, count 2 2006.201.21:24:49.98#ibcon#about to read 4, iclass 30, count 2 2006.201.21:24:49.98#ibcon#read 4, iclass 30, count 2 2006.201.21:24:49.98#ibcon#about to read 5, iclass 30, count 2 2006.201.21:24:49.98#ibcon#read 5, iclass 30, count 2 2006.201.21:24:49.98#ibcon#about to read 6, iclass 30, count 2 2006.201.21:24:49.98#ibcon#read 6, iclass 30, count 2 2006.201.21:24:49.98#ibcon#end of sib2, iclass 30, count 2 2006.201.21:24:49.98#ibcon#*mode == 0, iclass 30, count 2 2006.201.21:24:49.98#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.21:24:49.98#ibcon#[27=AT02-05\r\n] 2006.201.21:24:49.98#ibcon#*before write, iclass 30, count 2 2006.201.21:24:49.98#ibcon#enter sib2, iclass 30, count 2 2006.201.21:24:49.98#ibcon#flushed, iclass 30, count 2 2006.201.21:24:49.98#ibcon#about to write, iclass 30, count 2 2006.201.21:24:49.98#ibcon#wrote, iclass 30, count 2 2006.201.21:24:49.98#ibcon#about to read 3, iclass 30, count 2 2006.201.21:24:50.01#ibcon#read 3, iclass 30, count 2 2006.201.21:24:50.01#ibcon#about to read 4, iclass 30, count 2 2006.201.21:24:50.01#ibcon#read 4, iclass 30, count 2 2006.201.21:24:50.01#ibcon#about to read 5, iclass 30, count 2 2006.201.21:24:50.01#ibcon#read 5, iclass 30, count 2 2006.201.21:24:50.01#ibcon#about to read 6, iclass 30, count 2 2006.201.21:24:50.01#ibcon#read 6, iclass 30, count 2 2006.201.21:24:50.01#ibcon#end of sib2, iclass 30, count 2 2006.201.21:24:50.01#ibcon#*after write, iclass 30, count 2 2006.201.21:24:50.01#ibcon#*before return 0, iclass 30, count 2 2006.201.21:24:50.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:50.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:24:50.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.21:24:50.01#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:50.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:50.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:50.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:50.13#ibcon#enter wrdev, iclass 30, count 0 2006.201.21:24:50.13#ibcon#first serial, iclass 30, count 0 2006.201.21:24:50.13#ibcon#enter sib2, iclass 30, count 0 2006.201.21:24:50.13#ibcon#flushed, iclass 30, count 0 2006.201.21:24:50.13#ibcon#about to write, iclass 30, count 0 2006.201.21:24:50.13#ibcon#wrote, iclass 30, count 0 2006.201.21:24:50.13#ibcon#about to read 3, iclass 30, count 0 2006.201.21:24:50.15#ibcon#read 3, iclass 30, count 0 2006.201.21:24:50.15#ibcon#about to read 4, iclass 30, count 0 2006.201.21:24:50.15#ibcon#read 4, iclass 30, count 0 2006.201.21:24:50.15#ibcon#about to read 5, iclass 30, count 0 2006.201.21:24:50.15#ibcon#read 5, iclass 30, count 0 2006.201.21:24:50.15#ibcon#about to read 6, iclass 30, count 0 2006.201.21:24:50.15#ibcon#read 6, iclass 30, count 0 2006.201.21:24:50.15#ibcon#end of sib2, iclass 30, count 0 2006.201.21:24:50.15#ibcon#*mode == 0, iclass 30, count 0 2006.201.21:24:50.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.21:24:50.15#ibcon#[27=USB\r\n] 2006.201.21:24:50.15#ibcon#*before write, iclass 30, count 0 2006.201.21:24:50.15#ibcon#enter sib2, iclass 30, count 0 2006.201.21:24:50.15#ibcon#flushed, iclass 30, count 0 2006.201.21:24:50.15#ibcon#about to write, iclass 30, count 0 2006.201.21:24:50.15#ibcon#wrote, iclass 30, count 0 2006.201.21:24:50.15#ibcon#about to read 3, iclass 30, count 0 2006.201.21:24:50.18#ibcon#read 3, iclass 30, count 0 2006.201.21:24:50.18#ibcon#about to read 4, iclass 30, count 0 2006.201.21:24:50.18#ibcon#read 4, iclass 30, count 0 2006.201.21:24:50.18#ibcon#about to read 5, iclass 30, count 0 2006.201.21:24:50.18#ibcon#read 5, iclass 30, count 0 2006.201.21:24:50.18#ibcon#about to read 6, iclass 30, count 0 2006.201.21:24:50.18#ibcon#read 6, iclass 30, count 0 2006.201.21:24:50.18#ibcon#end of sib2, iclass 30, count 0 2006.201.21:24:50.18#ibcon#*after write, iclass 30, count 0 2006.201.21:24:50.18#ibcon#*before return 0, iclass 30, count 0 2006.201.21:24:50.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:50.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:24:50.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.21:24:50.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.21:24:50.18$vck44/vblo=3,649.99 2006.201.21:24:50.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.21:24:50.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.21:24:50.18#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:50.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:50.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:50.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:50.18#ibcon#enter wrdev, iclass 32, count 0 2006.201.21:24:50.18#ibcon#first serial, iclass 32, count 0 2006.201.21:24:50.18#ibcon#enter sib2, iclass 32, count 0 2006.201.21:24:50.18#ibcon#flushed, iclass 32, count 0 2006.201.21:24:50.18#ibcon#about to write, iclass 32, count 0 2006.201.21:24:50.18#ibcon#wrote, iclass 32, count 0 2006.201.21:24:50.18#ibcon#about to read 3, iclass 32, count 0 2006.201.21:24:50.20#ibcon#read 3, iclass 32, count 0 2006.201.21:24:50.20#ibcon#about to read 4, iclass 32, count 0 2006.201.21:24:50.20#ibcon#read 4, iclass 32, count 0 2006.201.21:24:50.20#ibcon#about to read 5, iclass 32, count 0 2006.201.21:24:50.20#ibcon#read 5, iclass 32, count 0 2006.201.21:24:50.20#ibcon#about to read 6, iclass 32, count 0 2006.201.21:24:50.20#ibcon#read 6, iclass 32, count 0 2006.201.21:24:50.20#ibcon#end of sib2, iclass 32, count 0 2006.201.21:24:50.20#ibcon#*mode == 0, iclass 32, count 0 2006.201.21:24:50.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.21:24:50.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.21:24:50.20#ibcon#*before write, iclass 32, count 0 2006.201.21:24:50.20#ibcon#enter sib2, iclass 32, count 0 2006.201.21:24:50.20#ibcon#flushed, iclass 32, count 0 2006.201.21:24:50.20#ibcon#about to write, iclass 32, count 0 2006.201.21:24:50.20#ibcon#wrote, iclass 32, count 0 2006.201.21:24:50.20#ibcon#about to read 3, iclass 32, count 0 2006.201.21:24:50.24#ibcon#read 3, iclass 32, count 0 2006.201.21:24:50.24#ibcon#about to read 4, iclass 32, count 0 2006.201.21:24:50.24#ibcon#read 4, iclass 32, count 0 2006.201.21:24:50.24#ibcon#about to read 5, iclass 32, count 0 2006.201.21:24:50.24#ibcon#read 5, iclass 32, count 0 2006.201.21:24:50.24#ibcon#about to read 6, iclass 32, count 0 2006.201.21:24:50.24#ibcon#read 6, iclass 32, count 0 2006.201.21:24:50.24#ibcon#end of sib2, iclass 32, count 0 2006.201.21:24:50.24#ibcon#*after write, iclass 32, count 0 2006.201.21:24:50.24#ibcon#*before return 0, iclass 32, count 0 2006.201.21:24:50.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:50.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:24:50.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.21:24:50.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.21:24:50.24$vck44/vb=3,4 2006.201.21:24:50.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.21:24:50.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.21:24:50.24#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:50.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:50.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:50.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:50.30#ibcon#enter wrdev, iclass 34, count 2 2006.201.21:24:50.30#ibcon#first serial, iclass 34, count 2 2006.201.21:24:50.30#ibcon#enter sib2, iclass 34, count 2 2006.201.21:24:50.30#ibcon#flushed, iclass 34, count 2 2006.201.21:24:50.30#ibcon#about to write, iclass 34, count 2 2006.201.21:24:50.30#ibcon#wrote, iclass 34, count 2 2006.201.21:24:50.30#ibcon#about to read 3, iclass 34, count 2 2006.201.21:24:50.32#ibcon#read 3, iclass 34, count 2 2006.201.21:24:50.32#ibcon#about to read 4, iclass 34, count 2 2006.201.21:24:50.32#ibcon#read 4, iclass 34, count 2 2006.201.21:24:50.32#ibcon#about to read 5, iclass 34, count 2 2006.201.21:24:50.32#ibcon#read 5, iclass 34, count 2 2006.201.21:24:50.32#ibcon#about to read 6, iclass 34, count 2 2006.201.21:24:50.32#ibcon#read 6, iclass 34, count 2 2006.201.21:24:50.32#ibcon#end of sib2, iclass 34, count 2 2006.201.21:24:50.32#ibcon#*mode == 0, iclass 34, count 2 2006.201.21:24:50.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.21:24:50.32#ibcon#[27=AT03-04\r\n] 2006.201.21:24:50.32#ibcon#*before write, iclass 34, count 2 2006.201.21:24:50.32#ibcon#enter sib2, iclass 34, count 2 2006.201.21:24:50.32#ibcon#flushed, iclass 34, count 2 2006.201.21:24:50.32#ibcon#about to write, iclass 34, count 2 2006.201.21:24:50.32#ibcon#wrote, iclass 34, count 2 2006.201.21:24:50.32#ibcon#about to read 3, iclass 34, count 2 2006.201.21:24:50.35#ibcon#read 3, iclass 34, count 2 2006.201.21:24:50.35#ibcon#about to read 4, iclass 34, count 2 2006.201.21:24:50.35#ibcon#read 4, iclass 34, count 2 2006.201.21:24:50.35#ibcon#about to read 5, iclass 34, count 2 2006.201.21:24:50.35#ibcon#read 5, iclass 34, count 2 2006.201.21:24:50.35#ibcon#about to read 6, iclass 34, count 2 2006.201.21:24:50.35#ibcon#read 6, iclass 34, count 2 2006.201.21:24:50.35#ibcon#end of sib2, iclass 34, count 2 2006.201.21:24:50.35#ibcon#*after write, iclass 34, count 2 2006.201.21:24:50.35#ibcon#*before return 0, iclass 34, count 2 2006.201.21:24:50.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:50.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:24:50.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.21:24:50.35#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:50.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:50.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:50.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:50.47#ibcon#enter wrdev, iclass 34, count 0 2006.201.21:24:50.47#ibcon#first serial, iclass 34, count 0 2006.201.21:24:50.47#ibcon#enter sib2, iclass 34, count 0 2006.201.21:24:50.47#ibcon#flushed, iclass 34, count 0 2006.201.21:24:50.47#ibcon#about to write, iclass 34, count 0 2006.201.21:24:50.47#ibcon#wrote, iclass 34, count 0 2006.201.21:24:50.47#ibcon#about to read 3, iclass 34, count 0 2006.201.21:24:50.49#ibcon#read 3, iclass 34, count 0 2006.201.21:24:50.49#ibcon#about to read 4, iclass 34, count 0 2006.201.21:24:50.49#ibcon#read 4, iclass 34, count 0 2006.201.21:24:50.49#ibcon#about to read 5, iclass 34, count 0 2006.201.21:24:50.49#ibcon#read 5, iclass 34, count 0 2006.201.21:24:50.49#ibcon#about to read 6, iclass 34, count 0 2006.201.21:24:50.49#ibcon#read 6, iclass 34, count 0 2006.201.21:24:50.49#ibcon#end of sib2, iclass 34, count 0 2006.201.21:24:50.49#ibcon#*mode == 0, iclass 34, count 0 2006.201.21:24:50.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.21:24:50.49#ibcon#[27=USB\r\n] 2006.201.21:24:50.49#ibcon#*before write, iclass 34, count 0 2006.201.21:24:50.49#ibcon#enter sib2, iclass 34, count 0 2006.201.21:24:50.49#ibcon#flushed, iclass 34, count 0 2006.201.21:24:50.49#ibcon#about to write, iclass 34, count 0 2006.201.21:24:50.49#ibcon#wrote, iclass 34, count 0 2006.201.21:24:50.49#ibcon#about to read 3, iclass 34, count 0 2006.201.21:24:50.52#ibcon#read 3, iclass 34, count 0 2006.201.21:24:50.52#ibcon#about to read 4, iclass 34, count 0 2006.201.21:24:50.52#ibcon#read 4, iclass 34, count 0 2006.201.21:24:50.52#ibcon#about to read 5, iclass 34, count 0 2006.201.21:24:50.52#ibcon#read 5, iclass 34, count 0 2006.201.21:24:50.52#ibcon#about to read 6, iclass 34, count 0 2006.201.21:24:50.52#ibcon#read 6, iclass 34, count 0 2006.201.21:24:50.52#ibcon#end of sib2, iclass 34, count 0 2006.201.21:24:50.52#ibcon#*after write, iclass 34, count 0 2006.201.21:24:50.52#ibcon#*before return 0, iclass 34, count 0 2006.201.21:24:50.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:50.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:24:50.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.21:24:50.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.21:24:50.52$vck44/vblo=4,679.99 2006.201.21:24:50.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.21:24:50.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.21:24:50.52#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:50.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:50.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:50.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:50.52#ibcon#enter wrdev, iclass 36, count 0 2006.201.21:24:50.52#ibcon#first serial, iclass 36, count 0 2006.201.21:24:50.52#ibcon#enter sib2, iclass 36, count 0 2006.201.21:24:50.52#ibcon#flushed, iclass 36, count 0 2006.201.21:24:50.52#ibcon#about to write, iclass 36, count 0 2006.201.21:24:50.52#ibcon#wrote, iclass 36, count 0 2006.201.21:24:50.52#ibcon#about to read 3, iclass 36, count 0 2006.201.21:24:50.54#ibcon#read 3, iclass 36, count 0 2006.201.21:24:50.54#ibcon#about to read 4, iclass 36, count 0 2006.201.21:24:50.54#ibcon#read 4, iclass 36, count 0 2006.201.21:24:50.54#ibcon#about to read 5, iclass 36, count 0 2006.201.21:24:50.54#ibcon#read 5, iclass 36, count 0 2006.201.21:24:50.54#ibcon#about to read 6, iclass 36, count 0 2006.201.21:24:50.54#ibcon#read 6, iclass 36, count 0 2006.201.21:24:50.54#ibcon#end of sib2, iclass 36, count 0 2006.201.21:24:50.54#ibcon#*mode == 0, iclass 36, count 0 2006.201.21:24:50.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.21:24:50.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.21:24:50.54#ibcon#*before write, iclass 36, count 0 2006.201.21:24:50.54#ibcon#enter sib2, iclass 36, count 0 2006.201.21:24:50.54#ibcon#flushed, iclass 36, count 0 2006.201.21:24:50.54#ibcon#about to write, iclass 36, count 0 2006.201.21:24:50.54#ibcon#wrote, iclass 36, count 0 2006.201.21:24:50.54#ibcon#about to read 3, iclass 36, count 0 2006.201.21:24:50.59#ibcon#read 3, iclass 36, count 0 2006.201.21:24:50.59#ibcon#about to read 4, iclass 36, count 0 2006.201.21:24:50.59#ibcon#read 4, iclass 36, count 0 2006.201.21:24:50.59#ibcon#about to read 5, iclass 36, count 0 2006.201.21:24:50.59#ibcon#read 5, iclass 36, count 0 2006.201.21:24:50.59#ibcon#about to read 6, iclass 36, count 0 2006.201.21:24:50.59#ibcon#read 6, iclass 36, count 0 2006.201.21:24:50.59#ibcon#end of sib2, iclass 36, count 0 2006.201.21:24:50.59#ibcon#*after write, iclass 36, count 0 2006.201.21:24:50.59#ibcon#*before return 0, iclass 36, count 0 2006.201.21:24:50.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:50.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:24:50.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.21:24:50.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.21:24:50.59$vck44/vb=4,5 2006.201.21:24:50.59#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.21:24:50.59#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.21:24:50.59#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:50.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:50.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:50.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:50.64#ibcon#enter wrdev, iclass 38, count 2 2006.201.21:24:50.64#ibcon#first serial, iclass 38, count 2 2006.201.21:24:50.64#ibcon#enter sib2, iclass 38, count 2 2006.201.21:24:50.64#ibcon#flushed, iclass 38, count 2 2006.201.21:24:50.64#ibcon#about to write, iclass 38, count 2 2006.201.21:24:50.64#ibcon#wrote, iclass 38, count 2 2006.201.21:24:50.64#ibcon#about to read 3, iclass 38, count 2 2006.201.21:24:50.66#ibcon#read 3, iclass 38, count 2 2006.201.21:24:50.66#ibcon#about to read 4, iclass 38, count 2 2006.201.21:24:50.66#ibcon#read 4, iclass 38, count 2 2006.201.21:24:50.66#ibcon#about to read 5, iclass 38, count 2 2006.201.21:24:50.66#ibcon#read 5, iclass 38, count 2 2006.201.21:24:50.66#ibcon#about to read 6, iclass 38, count 2 2006.201.21:24:50.66#ibcon#read 6, iclass 38, count 2 2006.201.21:24:50.66#ibcon#end of sib2, iclass 38, count 2 2006.201.21:24:50.66#ibcon#*mode == 0, iclass 38, count 2 2006.201.21:24:50.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.21:24:50.66#ibcon#[27=AT04-05\r\n] 2006.201.21:24:50.66#ibcon#*before write, iclass 38, count 2 2006.201.21:24:50.66#ibcon#enter sib2, iclass 38, count 2 2006.201.21:24:50.66#ibcon#flushed, iclass 38, count 2 2006.201.21:24:50.66#ibcon#about to write, iclass 38, count 2 2006.201.21:24:50.66#ibcon#wrote, iclass 38, count 2 2006.201.21:24:50.66#ibcon#about to read 3, iclass 38, count 2 2006.201.21:24:50.69#ibcon#read 3, iclass 38, count 2 2006.201.21:24:50.69#ibcon#about to read 4, iclass 38, count 2 2006.201.21:24:50.69#ibcon#read 4, iclass 38, count 2 2006.201.21:24:50.69#ibcon#about to read 5, iclass 38, count 2 2006.201.21:24:50.69#ibcon#read 5, iclass 38, count 2 2006.201.21:24:50.69#ibcon#about to read 6, iclass 38, count 2 2006.201.21:24:50.69#ibcon#read 6, iclass 38, count 2 2006.201.21:24:50.69#ibcon#end of sib2, iclass 38, count 2 2006.201.21:24:50.69#ibcon#*after write, iclass 38, count 2 2006.201.21:24:50.69#ibcon#*before return 0, iclass 38, count 2 2006.201.21:24:50.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:50.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:24:50.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.21:24:50.69#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:50.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:50.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:50.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:50.81#ibcon#enter wrdev, iclass 38, count 0 2006.201.21:24:50.81#ibcon#first serial, iclass 38, count 0 2006.201.21:24:50.81#ibcon#enter sib2, iclass 38, count 0 2006.201.21:24:50.81#ibcon#flushed, iclass 38, count 0 2006.201.21:24:50.81#ibcon#about to write, iclass 38, count 0 2006.201.21:24:50.81#ibcon#wrote, iclass 38, count 0 2006.201.21:24:50.81#ibcon#about to read 3, iclass 38, count 0 2006.201.21:24:50.83#ibcon#read 3, iclass 38, count 0 2006.201.21:24:50.83#ibcon#about to read 4, iclass 38, count 0 2006.201.21:24:50.83#ibcon#read 4, iclass 38, count 0 2006.201.21:24:50.83#ibcon#about to read 5, iclass 38, count 0 2006.201.21:24:50.83#ibcon#read 5, iclass 38, count 0 2006.201.21:24:50.83#ibcon#about to read 6, iclass 38, count 0 2006.201.21:24:50.83#ibcon#read 6, iclass 38, count 0 2006.201.21:24:50.83#ibcon#end of sib2, iclass 38, count 0 2006.201.21:24:50.83#ibcon#*mode == 0, iclass 38, count 0 2006.201.21:24:50.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.21:24:50.83#ibcon#[27=USB\r\n] 2006.201.21:24:50.83#ibcon#*before write, iclass 38, count 0 2006.201.21:24:50.83#ibcon#enter sib2, iclass 38, count 0 2006.201.21:24:50.83#ibcon#flushed, iclass 38, count 0 2006.201.21:24:50.83#ibcon#about to write, iclass 38, count 0 2006.201.21:24:50.83#ibcon#wrote, iclass 38, count 0 2006.201.21:24:50.83#ibcon#about to read 3, iclass 38, count 0 2006.201.21:24:50.86#ibcon#read 3, iclass 38, count 0 2006.201.21:24:50.86#ibcon#about to read 4, iclass 38, count 0 2006.201.21:24:50.86#ibcon#read 4, iclass 38, count 0 2006.201.21:24:50.86#ibcon#about to read 5, iclass 38, count 0 2006.201.21:24:50.86#ibcon#read 5, iclass 38, count 0 2006.201.21:24:50.86#ibcon#about to read 6, iclass 38, count 0 2006.201.21:24:50.86#ibcon#read 6, iclass 38, count 0 2006.201.21:24:50.86#ibcon#end of sib2, iclass 38, count 0 2006.201.21:24:50.86#ibcon#*after write, iclass 38, count 0 2006.201.21:24:50.86#ibcon#*before return 0, iclass 38, count 0 2006.201.21:24:50.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:50.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:24:50.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.21:24:50.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.21:24:50.86$vck44/vblo=5,709.99 2006.201.21:24:50.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.21:24:50.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.21:24:50.86#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:50.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:50.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:50.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:50.86#ibcon#enter wrdev, iclass 40, count 0 2006.201.21:24:50.86#ibcon#first serial, iclass 40, count 0 2006.201.21:24:50.86#ibcon#enter sib2, iclass 40, count 0 2006.201.21:24:50.86#ibcon#flushed, iclass 40, count 0 2006.201.21:24:50.86#ibcon#about to write, iclass 40, count 0 2006.201.21:24:50.86#ibcon#wrote, iclass 40, count 0 2006.201.21:24:50.86#ibcon#about to read 3, iclass 40, count 0 2006.201.21:24:50.88#ibcon#read 3, iclass 40, count 0 2006.201.21:24:50.88#ibcon#about to read 4, iclass 40, count 0 2006.201.21:24:50.88#ibcon#read 4, iclass 40, count 0 2006.201.21:24:50.88#ibcon#about to read 5, iclass 40, count 0 2006.201.21:24:50.88#ibcon#read 5, iclass 40, count 0 2006.201.21:24:50.88#ibcon#about to read 6, iclass 40, count 0 2006.201.21:24:50.88#ibcon#read 6, iclass 40, count 0 2006.201.21:24:50.88#ibcon#end of sib2, iclass 40, count 0 2006.201.21:24:50.88#ibcon#*mode == 0, iclass 40, count 0 2006.201.21:24:50.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.21:24:50.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.21:24:50.88#ibcon#*before write, iclass 40, count 0 2006.201.21:24:50.88#ibcon#enter sib2, iclass 40, count 0 2006.201.21:24:50.88#ibcon#flushed, iclass 40, count 0 2006.201.21:24:50.88#ibcon#about to write, iclass 40, count 0 2006.201.21:24:50.88#ibcon#wrote, iclass 40, count 0 2006.201.21:24:50.88#ibcon#about to read 3, iclass 40, count 0 2006.201.21:24:50.92#ibcon#read 3, iclass 40, count 0 2006.201.21:24:50.92#ibcon#about to read 4, iclass 40, count 0 2006.201.21:24:50.92#ibcon#read 4, iclass 40, count 0 2006.201.21:24:50.92#ibcon#about to read 5, iclass 40, count 0 2006.201.21:24:50.92#ibcon#read 5, iclass 40, count 0 2006.201.21:24:50.92#ibcon#about to read 6, iclass 40, count 0 2006.201.21:24:50.92#ibcon#read 6, iclass 40, count 0 2006.201.21:24:50.92#ibcon#end of sib2, iclass 40, count 0 2006.201.21:24:50.92#ibcon#*after write, iclass 40, count 0 2006.201.21:24:50.92#ibcon#*before return 0, iclass 40, count 0 2006.201.21:24:50.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:50.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:24:50.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.21:24:50.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.21:24:50.92$vck44/vb=5,4 2006.201.21:24:50.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.21:24:50.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.21:24:50.92#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:50.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:24:50.93#abcon#<5=/04 1.7 3.2 20.051001002.2\r\n> 2006.201.21:24:50.95#abcon#{5=INTERFACE CLEAR} 2006.201.21:24:50.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:24:50.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:24:50.98#ibcon#enter wrdev, iclass 5, count 2 2006.201.21:24:50.98#ibcon#first serial, iclass 5, count 2 2006.201.21:24:50.98#ibcon#enter sib2, iclass 5, count 2 2006.201.21:24:50.98#ibcon#flushed, iclass 5, count 2 2006.201.21:24:50.98#ibcon#about to write, iclass 5, count 2 2006.201.21:24:50.98#ibcon#wrote, iclass 5, count 2 2006.201.21:24:50.98#ibcon#about to read 3, iclass 5, count 2 2006.201.21:24:51.00#ibcon#read 3, iclass 5, count 2 2006.201.21:24:51.00#ibcon#about to read 4, iclass 5, count 2 2006.201.21:24:51.00#ibcon#read 4, iclass 5, count 2 2006.201.21:24:51.00#ibcon#about to read 5, iclass 5, count 2 2006.201.21:24:51.00#ibcon#read 5, iclass 5, count 2 2006.201.21:24:51.00#ibcon#about to read 6, iclass 5, count 2 2006.201.21:24:51.00#ibcon#read 6, iclass 5, count 2 2006.201.21:24:51.00#ibcon#end of sib2, iclass 5, count 2 2006.201.21:24:51.00#ibcon#*mode == 0, iclass 5, count 2 2006.201.21:24:51.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.21:24:51.00#ibcon#[27=AT05-04\r\n] 2006.201.21:24:51.00#ibcon#*before write, iclass 5, count 2 2006.201.21:24:51.00#ibcon#enter sib2, iclass 5, count 2 2006.201.21:24:51.00#ibcon#flushed, iclass 5, count 2 2006.201.21:24:51.00#ibcon#about to write, iclass 5, count 2 2006.201.21:24:51.00#ibcon#wrote, iclass 5, count 2 2006.201.21:24:51.00#ibcon#about to read 3, iclass 5, count 2 2006.201.21:24:51.01#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:24:51.03#ibcon#read 3, iclass 5, count 2 2006.201.21:24:51.03#ibcon#about to read 4, iclass 5, count 2 2006.201.21:24:51.03#ibcon#read 4, iclass 5, count 2 2006.201.21:24:51.03#ibcon#about to read 5, iclass 5, count 2 2006.201.21:24:51.03#ibcon#read 5, iclass 5, count 2 2006.201.21:24:51.03#ibcon#about to read 6, iclass 5, count 2 2006.201.21:24:51.03#ibcon#read 6, iclass 5, count 2 2006.201.21:24:51.03#ibcon#end of sib2, iclass 5, count 2 2006.201.21:24:51.03#ibcon#*after write, iclass 5, count 2 2006.201.21:24:51.03#ibcon#*before return 0, iclass 5, count 2 2006.201.21:24:51.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:24:51.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:24:51.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.21:24:51.03#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:51.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:24:51.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:24:51.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:24:51.15#ibcon#enter wrdev, iclass 5, count 0 2006.201.21:24:51.15#ibcon#first serial, iclass 5, count 0 2006.201.21:24:51.15#ibcon#enter sib2, iclass 5, count 0 2006.201.21:24:51.15#ibcon#flushed, iclass 5, count 0 2006.201.21:24:51.15#ibcon#about to write, iclass 5, count 0 2006.201.21:24:51.15#ibcon#wrote, iclass 5, count 0 2006.201.21:24:51.15#ibcon#about to read 3, iclass 5, count 0 2006.201.21:24:51.17#ibcon#read 3, iclass 5, count 0 2006.201.21:24:51.17#ibcon#about to read 4, iclass 5, count 0 2006.201.21:24:51.17#ibcon#read 4, iclass 5, count 0 2006.201.21:24:51.17#ibcon#about to read 5, iclass 5, count 0 2006.201.21:24:51.17#ibcon#read 5, iclass 5, count 0 2006.201.21:24:51.17#ibcon#about to read 6, iclass 5, count 0 2006.201.21:24:51.17#ibcon#read 6, iclass 5, count 0 2006.201.21:24:51.17#ibcon#end of sib2, iclass 5, count 0 2006.201.21:24:51.17#ibcon#*mode == 0, iclass 5, count 0 2006.201.21:24:51.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.21:24:51.17#ibcon#[27=USB\r\n] 2006.201.21:24:51.17#ibcon#*before write, iclass 5, count 0 2006.201.21:24:51.17#ibcon#enter sib2, iclass 5, count 0 2006.201.21:24:51.17#ibcon#flushed, iclass 5, count 0 2006.201.21:24:51.17#ibcon#about to write, iclass 5, count 0 2006.201.21:24:51.17#ibcon#wrote, iclass 5, count 0 2006.201.21:24:51.17#ibcon#about to read 3, iclass 5, count 0 2006.201.21:24:51.20#ibcon#read 3, iclass 5, count 0 2006.201.21:24:51.20#ibcon#about to read 4, iclass 5, count 0 2006.201.21:24:51.20#ibcon#read 4, iclass 5, count 0 2006.201.21:24:51.20#ibcon#about to read 5, iclass 5, count 0 2006.201.21:24:51.20#ibcon#read 5, iclass 5, count 0 2006.201.21:24:51.20#ibcon#about to read 6, iclass 5, count 0 2006.201.21:24:51.20#ibcon#read 6, iclass 5, count 0 2006.201.21:24:51.20#ibcon#end of sib2, iclass 5, count 0 2006.201.21:24:51.20#ibcon#*after write, iclass 5, count 0 2006.201.21:24:51.20#ibcon#*before return 0, iclass 5, count 0 2006.201.21:24:51.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:24:51.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:24:51.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.21:24:51.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.21:24:51.20$vck44/vblo=6,719.99 2006.201.21:24:51.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.21:24:51.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.21:24:51.20#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:51.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:51.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:51.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:51.20#ibcon#enter wrdev, iclass 12, count 0 2006.201.21:24:51.20#ibcon#first serial, iclass 12, count 0 2006.201.21:24:51.20#ibcon#enter sib2, iclass 12, count 0 2006.201.21:24:51.20#ibcon#flushed, iclass 12, count 0 2006.201.21:24:51.20#ibcon#about to write, iclass 12, count 0 2006.201.21:24:51.20#ibcon#wrote, iclass 12, count 0 2006.201.21:24:51.20#ibcon#about to read 3, iclass 12, count 0 2006.201.21:24:51.22#ibcon#read 3, iclass 12, count 0 2006.201.21:24:51.22#ibcon#about to read 4, iclass 12, count 0 2006.201.21:24:51.22#ibcon#read 4, iclass 12, count 0 2006.201.21:24:51.22#ibcon#about to read 5, iclass 12, count 0 2006.201.21:24:51.22#ibcon#read 5, iclass 12, count 0 2006.201.21:24:51.22#ibcon#about to read 6, iclass 12, count 0 2006.201.21:24:51.22#ibcon#read 6, iclass 12, count 0 2006.201.21:24:51.22#ibcon#end of sib2, iclass 12, count 0 2006.201.21:24:51.22#ibcon#*mode == 0, iclass 12, count 0 2006.201.21:24:51.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.21:24:51.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.21:24:51.22#ibcon#*before write, iclass 12, count 0 2006.201.21:24:51.22#ibcon#enter sib2, iclass 12, count 0 2006.201.21:24:51.22#ibcon#flushed, iclass 12, count 0 2006.201.21:24:51.22#ibcon#about to write, iclass 12, count 0 2006.201.21:24:51.22#ibcon#wrote, iclass 12, count 0 2006.201.21:24:51.22#ibcon#about to read 3, iclass 12, count 0 2006.201.21:24:51.26#ibcon#read 3, iclass 12, count 0 2006.201.21:24:51.26#ibcon#about to read 4, iclass 12, count 0 2006.201.21:24:51.26#ibcon#read 4, iclass 12, count 0 2006.201.21:24:51.26#ibcon#about to read 5, iclass 12, count 0 2006.201.21:24:51.26#ibcon#read 5, iclass 12, count 0 2006.201.21:24:51.26#ibcon#about to read 6, iclass 12, count 0 2006.201.21:24:51.26#ibcon#read 6, iclass 12, count 0 2006.201.21:24:51.26#ibcon#end of sib2, iclass 12, count 0 2006.201.21:24:51.26#ibcon#*after write, iclass 12, count 0 2006.201.21:24:51.26#ibcon#*before return 0, iclass 12, count 0 2006.201.21:24:51.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:51.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:24:51.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.21:24:51.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.21:24:51.26$vck44/vb=6,4 2006.201.21:24:51.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.21:24:51.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.21:24:51.26#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:51.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:51.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:51.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:51.32#ibcon#enter wrdev, iclass 14, count 2 2006.201.21:24:51.32#ibcon#first serial, iclass 14, count 2 2006.201.21:24:51.32#ibcon#enter sib2, iclass 14, count 2 2006.201.21:24:51.32#ibcon#flushed, iclass 14, count 2 2006.201.21:24:51.32#ibcon#about to write, iclass 14, count 2 2006.201.21:24:51.32#ibcon#wrote, iclass 14, count 2 2006.201.21:24:51.32#ibcon#about to read 3, iclass 14, count 2 2006.201.21:24:51.34#ibcon#read 3, iclass 14, count 2 2006.201.21:24:51.34#ibcon#about to read 4, iclass 14, count 2 2006.201.21:24:51.34#ibcon#read 4, iclass 14, count 2 2006.201.21:24:51.34#ibcon#about to read 5, iclass 14, count 2 2006.201.21:24:51.34#ibcon#read 5, iclass 14, count 2 2006.201.21:24:51.34#ibcon#about to read 6, iclass 14, count 2 2006.201.21:24:51.34#ibcon#read 6, iclass 14, count 2 2006.201.21:24:51.34#ibcon#end of sib2, iclass 14, count 2 2006.201.21:24:51.34#ibcon#*mode == 0, iclass 14, count 2 2006.201.21:24:51.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.21:24:51.34#ibcon#[27=AT06-04\r\n] 2006.201.21:24:51.34#ibcon#*before write, iclass 14, count 2 2006.201.21:24:51.34#ibcon#enter sib2, iclass 14, count 2 2006.201.21:24:51.34#ibcon#flushed, iclass 14, count 2 2006.201.21:24:51.34#ibcon#about to write, iclass 14, count 2 2006.201.21:24:51.34#ibcon#wrote, iclass 14, count 2 2006.201.21:24:51.34#ibcon#about to read 3, iclass 14, count 2 2006.201.21:24:51.37#ibcon#read 3, iclass 14, count 2 2006.201.21:24:51.37#ibcon#about to read 4, iclass 14, count 2 2006.201.21:24:51.37#ibcon#read 4, iclass 14, count 2 2006.201.21:24:51.37#ibcon#about to read 5, iclass 14, count 2 2006.201.21:24:51.37#ibcon#read 5, iclass 14, count 2 2006.201.21:24:51.37#ibcon#about to read 6, iclass 14, count 2 2006.201.21:24:51.37#ibcon#read 6, iclass 14, count 2 2006.201.21:24:51.37#ibcon#end of sib2, iclass 14, count 2 2006.201.21:24:51.37#ibcon#*after write, iclass 14, count 2 2006.201.21:24:51.37#ibcon#*before return 0, iclass 14, count 2 2006.201.21:24:51.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:51.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:24:51.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.21:24:51.37#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:51.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:51.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:51.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:51.49#ibcon#enter wrdev, iclass 14, count 0 2006.201.21:24:51.49#ibcon#first serial, iclass 14, count 0 2006.201.21:24:51.49#ibcon#enter sib2, iclass 14, count 0 2006.201.21:24:51.49#ibcon#flushed, iclass 14, count 0 2006.201.21:24:51.49#ibcon#about to write, iclass 14, count 0 2006.201.21:24:51.49#ibcon#wrote, iclass 14, count 0 2006.201.21:24:51.49#ibcon#about to read 3, iclass 14, count 0 2006.201.21:24:51.51#ibcon#read 3, iclass 14, count 0 2006.201.21:24:51.51#ibcon#about to read 4, iclass 14, count 0 2006.201.21:24:51.51#ibcon#read 4, iclass 14, count 0 2006.201.21:24:51.51#ibcon#about to read 5, iclass 14, count 0 2006.201.21:24:51.51#ibcon#read 5, iclass 14, count 0 2006.201.21:24:51.51#ibcon#about to read 6, iclass 14, count 0 2006.201.21:24:51.51#ibcon#read 6, iclass 14, count 0 2006.201.21:24:51.51#ibcon#end of sib2, iclass 14, count 0 2006.201.21:24:51.51#ibcon#*mode == 0, iclass 14, count 0 2006.201.21:24:51.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.21:24:51.51#ibcon#[27=USB\r\n] 2006.201.21:24:51.51#ibcon#*before write, iclass 14, count 0 2006.201.21:24:51.51#ibcon#enter sib2, iclass 14, count 0 2006.201.21:24:51.51#ibcon#flushed, iclass 14, count 0 2006.201.21:24:51.51#ibcon#about to write, iclass 14, count 0 2006.201.21:24:51.51#ibcon#wrote, iclass 14, count 0 2006.201.21:24:51.51#ibcon#about to read 3, iclass 14, count 0 2006.201.21:24:51.54#ibcon#read 3, iclass 14, count 0 2006.201.21:24:51.54#ibcon#about to read 4, iclass 14, count 0 2006.201.21:24:51.54#ibcon#read 4, iclass 14, count 0 2006.201.21:24:51.54#ibcon#about to read 5, iclass 14, count 0 2006.201.21:24:51.54#ibcon#read 5, iclass 14, count 0 2006.201.21:24:51.54#ibcon#about to read 6, iclass 14, count 0 2006.201.21:24:51.54#ibcon#read 6, iclass 14, count 0 2006.201.21:24:51.54#ibcon#end of sib2, iclass 14, count 0 2006.201.21:24:51.54#ibcon#*after write, iclass 14, count 0 2006.201.21:24:51.54#ibcon#*before return 0, iclass 14, count 0 2006.201.21:24:51.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:51.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:24:51.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.21:24:51.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.21:24:51.54$vck44/vblo=7,734.99 2006.201.21:24:51.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.21:24:51.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.21:24:51.54#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:51.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:51.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:51.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:51.54#ibcon#enter wrdev, iclass 16, count 0 2006.201.21:24:51.54#ibcon#first serial, iclass 16, count 0 2006.201.21:24:51.54#ibcon#enter sib2, iclass 16, count 0 2006.201.21:24:51.54#ibcon#flushed, iclass 16, count 0 2006.201.21:24:51.54#ibcon#about to write, iclass 16, count 0 2006.201.21:24:51.54#ibcon#wrote, iclass 16, count 0 2006.201.21:24:51.54#ibcon#about to read 3, iclass 16, count 0 2006.201.21:24:51.56#ibcon#read 3, iclass 16, count 0 2006.201.21:24:51.56#ibcon#about to read 4, iclass 16, count 0 2006.201.21:24:51.56#ibcon#read 4, iclass 16, count 0 2006.201.21:24:51.56#ibcon#about to read 5, iclass 16, count 0 2006.201.21:24:51.56#ibcon#read 5, iclass 16, count 0 2006.201.21:24:51.56#ibcon#about to read 6, iclass 16, count 0 2006.201.21:24:51.56#ibcon#read 6, iclass 16, count 0 2006.201.21:24:51.56#ibcon#end of sib2, iclass 16, count 0 2006.201.21:24:51.56#ibcon#*mode == 0, iclass 16, count 0 2006.201.21:24:51.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.21:24:51.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.21:24:51.56#ibcon#*before write, iclass 16, count 0 2006.201.21:24:51.56#ibcon#enter sib2, iclass 16, count 0 2006.201.21:24:51.56#ibcon#flushed, iclass 16, count 0 2006.201.21:24:51.56#ibcon#about to write, iclass 16, count 0 2006.201.21:24:51.56#ibcon#wrote, iclass 16, count 0 2006.201.21:24:51.56#ibcon#about to read 3, iclass 16, count 0 2006.201.21:24:51.60#ibcon#read 3, iclass 16, count 0 2006.201.21:24:51.60#ibcon#about to read 4, iclass 16, count 0 2006.201.21:24:51.60#ibcon#read 4, iclass 16, count 0 2006.201.21:24:51.60#ibcon#about to read 5, iclass 16, count 0 2006.201.21:24:51.60#ibcon#read 5, iclass 16, count 0 2006.201.21:24:51.60#ibcon#about to read 6, iclass 16, count 0 2006.201.21:24:51.60#ibcon#read 6, iclass 16, count 0 2006.201.21:24:51.60#ibcon#end of sib2, iclass 16, count 0 2006.201.21:24:51.60#ibcon#*after write, iclass 16, count 0 2006.201.21:24:51.60#ibcon#*before return 0, iclass 16, count 0 2006.201.21:24:51.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:51.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:24:51.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.21:24:51.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.21:24:51.60$vck44/vb=7,4 2006.201.21:24:51.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.21:24:51.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.21:24:51.60#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:51.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:51.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:51.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:51.66#ibcon#enter wrdev, iclass 18, count 2 2006.201.21:24:51.66#ibcon#first serial, iclass 18, count 2 2006.201.21:24:51.66#ibcon#enter sib2, iclass 18, count 2 2006.201.21:24:51.66#ibcon#flushed, iclass 18, count 2 2006.201.21:24:51.66#ibcon#about to write, iclass 18, count 2 2006.201.21:24:51.66#ibcon#wrote, iclass 18, count 2 2006.201.21:24:51.66#ibcon#about to read 3, iclass 18, count 2 2006.201.21:24:51.68#ibcon#read 3, iclass 18, count 2 2006.201.21:24:51.68#ibcon#about to read 4, iclass 18, count 2 2006.201.21:24:51.68#ibcon#read 4, iclass 18, count 2 2006.201.21:24:51.68#ibcon#about to read 5, iclass 18, count 2 2006.201.21:24:51.68#ibcon#read 5, iclass 18, count 2 2006.201.21:24:51.68#ibcon#about to read 6, iclass 18, count 2 2006.201.21:24:51.68#ibcon#read 6, iclass 18, count 2 2006.201.21:24:51.68#ibcon#end of sib2, iclass 18, count 2 2006.201.21:24:51.68#ibcon#*mode == 0, iclass 18, count 2 2006.201.21:24:51.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.21:24:51.68#ibcon#[27=AT07-04\r\n] 2006.201.21:24:51.68#ibcon#*before write, iclass 18, count 2 2006.201.21:24:51.68#ibcon#enter sib2, iclass 18, count 2 2006.201.21:24:51.68#ibcon#flushed, iclass 18, count 2 2006.201.21:24:51.68#ibcon#about to write, iclass 18, count 2 2006.201.21:24:51.68#ibcon#wrote, iclass 18, count 2 2006.201.21:24:51.68#ibcon#about to read 3, iclass 18, count 2 2006.201.21:24:51.71#ibcon#read 3, iclass 18, count 2 2006.201.21:24:51.71#ibcon#about to read 4, iclass 18, count 2 2006.201.21:24:51.71#ibcon#read 4, iclass 18, count 2 2006.201.21:24:51.71#ibcon#about to read 5, iclass 18, count 2 2006.201.21:24:51.71#ibcon#read 5, iclass 18, count 2 2006.201.21:24:51.71#ibcon#about to read 6, iclass 18, count 2 2006.201.21:24:51.71#ibcon#read 6, iclass 18, count 2 2006.201.21:24:51.71#ibcon#end of sib2, iclass 18, count 2 2006.201.21:24:51.71#ibcon#*after write, iclass 18, count 2 2006.201.21:24:51.71#ibcon#*before return 0, iclass 18, count 2 2006.201.21:24:51.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:51.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:24:51.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.21:24:51.71#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:51.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:51.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:51.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:51.83#ibcon#enter wrdev, iclass 18, count 0 2006.201.21:24:51.83#ibcon#first serial, iclass 18, count 0 2006.201.21:24:51.83#ibcon#enter sib2, iclass 18, count 0 2006.201.21:24:51.83#ibcon#flushed, iclass 18, count 0 2006.201.21:24:51.83#ibcon#about to write, iclass 18, count 0 2006.201.21:24:51.83#ibcon#wrote, iclass 18, count 0 2006.201.21:24:51.83#ibcon#about to read 3, iclass 18, count 0 2006.201.21:24:51.85#ibcon#read 3, iclass 18, count 0 2006.201.21:24:51.85#ibcon#about to read 4, iclass 18, count 0 2006.201.21:24:51.85#ibcon#read 4, iclass 18, count 0 2006.201.21:24:51.85#ibcon#about to read 5, iclass 18, count 0 2006.201.21:24:51.85#ibcon#read 5, iclass 18, count 0 2006.201.21:24:51.85#ibcon#about to read 6, iclass 18, count 0 2006.201.21:24:51.85#ibcon#read 6, iclass 18, count 0 2006.201.21:24:51.85#ibcon#end of sib2, iclass 18, count 0 2006.201.21:24:51.85#ibcon#*mode == 0, iclass 18, count 0 2006.201.21:24:51.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.21:24:51.85#ibcon#[27=USB\r\n] 2006.201.21:24:51.85#ibcon#*before write, iclass 18, count 0 2006.201.21:24:51.85#ibcon#enter sib2, iclass 18, count 0 2006.201.21:24:51.85#ibcon#flushed, iclass 18, count 0 2006.201.21:24:51.85#ibcon#about to write, iclass 18, count 0 2006.201.21:24:51.85#ibcon#wrote, iclass 18, count 0 2006.201.21:24:51.85#ibcon#about to read 3, iclass 18, count 0 2006.201.21:24:51.88#ibcon#read 3, iclass 18, count 0 2006.201.21:24:51.88#ibcon#about to read 4, iclass 18, count 0 2006.201.21:24:51.88#ibcon#read 4, iclass 18, count 0 2006.201.21:24:51.88#ibcon#about to read 5, iclass 18, count 0 2006.201.21:24:51.88#ibcon#read 5, iclass 18, count 0 2006.201.21:24:51.88#ibcon#about to read 6, iclass 18, count 0 2006.201.21:24:51.88#ibcon#read 6, iclass 18, count 0 2006.201.21:24:51.88#ibcon#end of sib2, iclass 18, count 0 2006.201.21:24:51.88#ibcon#*after write, iclass 18, count 0 2006.201.21:24:51.88#ibcon#*before return 0, iclass 18, count 0 2006.201.21:24:51.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:51.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:24:51.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.21:24:51.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.21:24:51.88$vck44/vblo=8,744.99 2006.201.21:24:51.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.21:24:51.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.21:24:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.21:24:51.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:51.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:51.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:51.88#ibcon#enter wrdev, iclass 20, count 0 2006.201.21:24:51.88#ibcon#first serial, iclass 20, count 0 2006.201.21:24:51.88#ibcon#enter sib2, iclass 20, count 0 2006.201.21:24:51.88#ibcon#flushed, iclass 20, count 0 2006.201.21:24:51.88#ibcon#about to write, iclass 20, count 0 2006.201.21:24:51.88#ibcon#wrote, iclass 20, count 0 2006.201.21:24:51.88#ibcon#about to read 3, iclass 20, count 0 2006.201.21:24:51.90#ibcon#read 3, iclass 20, count 0 2006.201.21:24:51.90#ibcon#about to read 4, iclass 20, count 0 2006.201.21:24:51.90#ibcon#read 4, iclass 20, count 0 2006.201.21:24:51.90#ibcon#about to read 5, iclass 20, count 0 2006.201.21:24:51.90#ibcon#read 5, iclass 20, count 0 2006.201.21:24:51.90#ibcon#about to read 6, iclass 20, count 0 2006.201.21:24:51.90#ibcon#read 6, iclass 20, count 0 2006.201.21:24:51.90#ibcon#end of sib2, iclass 20, count 0 2006.201.21:24:51.90#ibcon#*mode == 0, iclass 20, count 0 2006.201.21:24:51.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.21:24:51.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.21:24:51.90#ibcon#*before write, iclass 20, count 0 2006.201.21:24:51.90#ibcon#enter sib2, iclass 20, count 0 2006.201.21:24:51.90#ibcon#flushed, iclass 20, count 0 2006.201.21:24:51.90#ibcon#about to write, iclass 20, count 0 2006.201.21:24:51.90#ibcon#wrote, iclass 20, count 0 2006.201.21:24:51.90#ibcon#about to read 3, iclass 20, count 0 2006.201.21:24:51.94#ibcon#read 3, iclass 20, count 0 2006.201.21:24:51.94#ibcon#about to read 4, iclass 20, count 0 2006.201.21:24:51.94#ibcon#read 4, iclass 20, count 0 2006.201.21:24:51.94#ibcon#about to read 5, iclass 20, count 0 2006.201.21:24:51.94#ibcon#read 5, iclass 20, count 0 2006.201.21:24:51.94#ibcon#about to read 6, iclass 20, count 0 2006.201.21:24:51.94#ibcon#read 6, iclass 20, count 0 2006.201.21:24:51.94#ibcon#end of sib2, iclass 20, count 0 2006.201.21:24:51.94#ibcon#*after write, iclass 20, count 0 2006.201.21:24:51.94#ibcon#*before return 0, iclass 20, count 0 2006.201.21:24:51.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:51.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:24:51.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.21:24:51.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.21:24:51.94$vck44/vb=8,4 2006.201.21:24:51.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.21:24:51.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.21:24:51.94#ibcon#ireg 11 cls_cnt 2 2006.201.21:24:51.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:52.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:52.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:52.00#ibcon#enter wrdev, iclass 22, count 2 2006.201.21:24:52.00#ibcon#first serial, iclass 22, count 2 2006.201.21:24:52.00#ibcon#enter sib2, iclass 22, count 2 2006.201.21:24:52.00#ibcon#flushed, iclass 22, count 2 2006.201.21:24:52.00#ibcon#about to write, iclass 22, count 2 2006.201.21:24:52.00#ibcon#wrote, iclass 22, count 2 2006.201.21:24:52.00#ibcon#about to read 3, iclass 22, count 2 2006.201.21:24:52.02#ibcon#read 3, iclass 22, count 2 2006.201.21:24:52.02#ibcon#about to read 4, iclass 22, count 2 2006.201.21:24:52.02#ibcon#read 4, iclass 22, count 2 2006.201.21:24:52.02#ibcon#about to read 5, iclass 22, count 2 2006.201.21:24:52.02#ibcon#read 5, iclass 22, count 2 2006.201.21:24:52.02#ibcon#about to read 6, iclass 22, count 2 2006.201.21:24:52.02#ibcon#read 6, iclass 22, count 2 2006.201.21:24:52.02#ibcon#end of sib2, iclass 22, count 2 2006.201.21:24:52.02#ibcon#*mode == 0, iclass 22, count 2 2006.201.21:24:52.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.21:24:52.02#ibcon#[27=AT08-04\r\n] 2006.201.21:24:52.02#ibcon#*before write, iclass 22, count 2 2006.201.21:24:52.02#ibcon#enter sib2, iclass 22, count 2 2006.201.21:24:52.02#ibcon#flushed, iclass 22, count 2 2006.201.21:24:52.02#ibcon#about to write, iclass 22, count 2 2006.201.21:24:52.02#ibcon#wrote, iclass 22, count 2 2006.201.21:24:52.02#ibcon#about to read 3, iclass 22, count 2 2006.201.21:24:52.05#ibcon#read 3, iclass 22, count 2 2006.201.21:24:52.05#ibcon#about to read 4, iclass 22, count 2 2006.201.21:24:52.05#ibcon#read 4, iclass 22, count 2 2006.201.21:24:52.05#ibcon#about to read 5, iclass 22, count 2 2006.201.21:24:52.05#ibcon#read 5, iclass 22, count 2 2006.201.21:24:52.05#ibcon#about to read 6, iclass 22, count 2 2006.201.21:24:52.05#ibcon#read 6, iclass 22, count 2 2006.201.21:24:52.05#ibcon#end of sib2, iclass 22, count 2 2006.201.21:24:52.05#ibcon#*after write, iclass 22, count 2 2006.201.21:24:52.05#ibcon#*before return 0, iclass 22, count 2 2006.201.21:24:52.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:52.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:24:52.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.21:24:52.05#ibcon#ireg 7 cls_cnt 0 2006.201.21:24:52.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:52.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:52.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:52.17#ibcon#enter wrdev, iclass 22, count 0 2006.201.21:24:52.17#ibcon#first serial, iclass 22, count 0 2006.201.21:24:52.17#ibcon#enter sib2, iclass 22, count 0 2006.201.21:24:52.17#ibcon#flushed, iclass 22, count 0 2006.201.21:24:52.17#ibcon#about to write, iclass 22, count 0 2006.201.21:24:52.17#ibcon#wrote, iclass 22, count 0 2006.201.21:24:52.17#ibcon#about to read 3, iclass 22, count 0 2006.201.21:24:52.20#ibcon#read 3, iclass 22, count 0 2006.201.21:24:52.20#ibcon#about to read 4, iclass 22, count 0 2006.201.21:24:52.20#ibcon#read 4, iclass 22, count 0 2006.201.21:24:52.20#ibcon#about to read 5, iclass 22, count 0 2006.201.21:24:52.20#ibcon#read 5, iclass 22, count 0 2006.201.21:24:52.20#ibcon#about to read 6, iclass 22, count 0 2006.201.21:24:52.20#ibcon#read 6, iclass 22, count 0 2006.201.21:24:52.20#ibcon#end of sib2, iclass 22, count 0 2006.201.21:24:52.20#ibcon#*mode == 0, iclass 22, count 0 2006.201.21:24:52.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.21:24:52.20#ibcon#[27=USB\r\n] 2006.201.21:24:52.20#ibcon#*before write, iclass 22, count 0 2006.201.21:24:52.20#ibcon#enter sib2, iclass 22, count 0 2006.201.21:24:52.20#ibcon#flushed, iclass 22, count 0 2006.201.21:24:52.20#ibcon#about to write, iclass 22, count 0 2006.201.21:24:52.20#ibcon#wrote, iclass 22, count 0 2006.201.21:24:52.20#ibcon#about to read 3, iclass 22, count 0 2006.201.21:24:52.23#ibcon#read 3, iclass 22, count 0 2006.201.21:24:52.23#ibcon#about to read 4, iclass 22, count 0 2006.201.21:24:52.23#ibcon#read 4, iclass 22, count 0 2006.201.21:24:52.23#ibcon#about to read 5, iclass 22, count 0 2006.201.21:24:52.23#ibcon#read 5, iclass 22, count 0 2006.201.21:24:52.23#ibcon#about to read 6, iclass 22, count 0 2006.201.21:24:52.23#ibcon#read 6, iclass 22, count 0 2006.201.21:24:52.23#ibcon#end of sib2, iclass 22, count 0 2006.201.21:24:52.23#ibcon#*after write, iclass 22, count 0 2006.201.21:24:52.23#ibcon#*before return 0, iclass 22, count 0 2006.201.21:24:52.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:52.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:24:52.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.21:24:52.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.21:24:52.23$vck44/vabw=wide 2006.201.21:24:52.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.21:24:52.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.21:24:52.23#ibcon#ireg 8 cls_cnt 0 2006.201.21:24:52.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:52.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:52.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:52.23#ibcon#enter wrdev, iclass 24, count 0 2006.201.21:24:52.23#ibcon#first serial, iclass 24, count 0 2006.201.21:24:52.23#ibcon#enter sib2, iclass 24, count 0 2006.201.21:24:52.23#ibcon#flushed, iclass 24, count 0 2006.201.21:24:52.23#ibcon#about to write, iclass 24, count 0 2006.201.21:24:52.23#ibcon#wrote, iclass 24, count 0 2006.201.21:24:52.23#ibcon#about to read 3, iclass 24, count 0 2006.201.21:24:52.25#ibcon#read 3, iclass 24, count 0 2006.201.21:24:52.25#ibcon#about to read 4, iclass 24, count 0 2006.201.21:24:52.25#ibcon#read 4, iclass 24, count 0 2006.201.21:24:52.25#ibcon#about to read 5, iclass 24, count 0 2006.201.21:24:52.25#ibcon#read 5, iclass 24, count 0 2006.201.21:24:52.25#ibcon#about to read 6, iclass 24, count 0 2006.201.21:24:52.25#ibcon#read 6, iclass 24, count 0 2006.201.21:24:52.25#ibcon#end of sib2, iclass 24, count 0 2006.201.21:24:52.25#ibcon#*mode == 0, iclass 24, count 0 2006.201.21:24:52.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.21:24:52.25#ibcon#[25=BW32\r\n] 2006.201.21:24:52.25#ibcon#*before write, iclass 24, count 0 2006.201.21:24:52.25#ibcon#enter sib2, iclass 24, count 0 2006.201.21:24:52.25#ibcon#flushed, iclass 24, count 0 2006.201.21:24:52.25#ibcon#about to write, iclass 24, count 0 2006.201.21:24:52.25#ibcon#wrote, iclass 24, count 0 2006.201.21:24:52.25#ibcon#about to read 3, iclass 24, count 0 2006.201.21:24:52.28#ibcon#read 3, iclass 24, count 0 2006.201.21:24:52.28#ibcon#about to read 4, iclass 24, count 0 2006.201.21:24:52.28#ibcon#read 4, iclass 24, count 0 2006.201.21:24:52.28#ibcon#about to read 5, iclass 24, count 0 2006.201.21:24:52.28#ibcon#read 5, iclass 24, count 0 2006.201.21:24:52.28#ibcon#about to read 6, iclass 24, count 0 2006.201.21:24:52.28#ibcon#read 6, iclass 24, count 0 2006.201.21:24:52.28#ibcon#end of sib2, iclass 24, count 0 2006.201.21:24:52.28#ibcon#*after write, iclass 24, count 0 2006.201.21:24:52.28#ibcon#*before return 0, iclass 24, count 0 2006.201.21:24:52.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:52.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:24:52.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.21:24:52.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.21:24:52.28$vck44/vbbw=wide 2006.201.21:24:52.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.21:24:52.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.21:24:52.28#ibcon#ireg 8 cls_cnt 0 2006.201.21:24:52.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:24:52.35#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:24:52.35#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:24:52.35#ibcon#enter wrdev, iclass 26, count 0 2006.201.21:24:52.35#ibcon#first serial, iclass 26, count 0 2006.201.21:24:52.35#ibcon#enter sib2, iclass 26, count 0 2006.201.21:24:52.35#ibcon#flushed, iclass 26, count 0 2006.201.21:24:52.35#ibcon#about to write, iclass 26, count 0 2006.201.21:24:52.35#ibcon#wrote, iclass 26, count 0 2006.201.21:24:52.35#ibcon#about to read 3, iclass 26, count 0 2006.201.21:24:52.37#ibcon#read 3, iclass 26, count 0 2006.201.21:24:52.37#ibcon#about to read 4, iclass 26, count 0 2006.201.21:24:52.37#ibcon#read 4, iclass 26, count 0 2006.201.21:24:52.37#ibcon#about to read 5, iclass 26, count 0 2006.201.21:24:52.37#ibcon#read 5, iclass 26, count 0 2006.201.21:24:52.37#ibcon#about to read 6, iclass 26, count 0 2006.201.21:24:52.37#ibcon#read 6, iclass 26, count 0 2006.201.21:24:52.37#ibcon#end of sib2, iclass 26, count 0 2006.201.21:24:52.37#ibcon#*mode == 0, iclass 26, count 0 2006.201.21:24:52.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.21:24:52.37#ibcon#[27=BW32\r\n] 2006.201.21:24:52.37#ibcon#*before write, iclass 26, count 0 2006.201.21:24:52.37#ibcon#enter sib2, iclass 26, count 0 2006.201.21:24:52.37#ibcon#flushed, iclass 26, count 0 2006.201.21:24:52.37#ibcon#about to write, iclass 26, count 0 2006.201.21:24:52.37#ibcon#wrote, iclass 26, count 0 2006.201.21:24:52.37#ibcon#about to read 3, iclass 26, count 0 2006.201.21:24:52.40#ibcon#read 3, iclass 26, count 0 2006.201.21:24:52.40#ibcon#about to read 4, iclass 26, count 0 2006.201.21:24:52.40#ibcon#read 4, iclass 26, count 0 2006.201.21:24:52.40#ibcon#about to read 5, iclass 26, count 0 2006.201.21:24:52.40#ibcon#read 5, iclass 26, count 0 2006.201.21:24:52.40#ibcon#about to read 6, iclass 26, count 0 2006.201.21:24:52.40#ibcon#read 6, iclass 26, count 0 2006.201.21:24:52.40#ibcon#end of sib2, iclass 26, count 0 2006.201.21:24:52.40#ibcon#*after write, iclass 26, count 0 2006.201.21:24:52.40#ibcon#*before return 0, iclass 26, count 0 2006.201.21:24:52.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:24:52.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:24:52.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.21:24:52.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.21:24:52.40$setupk4/ifdk4 2006.201.21:24:52.40$ifdk4/lo= 2006.201.21:24:52.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.21:24:52.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.21:24:52.40$ifdk4/patch= 2006.201.21:24:52.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.21:24:52.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.21:24:52.40$setupk4/!*+20s 2006.201.21:25:01.10#abcon#<5=/04 1.7 3.2 20.051001002.2\r\n> 2006.201.21:25:01.12#abcon#{5=INTERFACE CLEAR} 2006.201.21:25:01.18#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:25:04.13#trakl#Source acquired 2006.201.21:25:06.13#flagr#flagr/antenna,acquired 2006.201.21:25:06.87$setupk4/"tpicd 2006.201.21:25:06.87$setupk4/echo=off 2006.201.21:25:06.87$setupk4/xlog=off 2006.201.21:25:06.87:!2006.201.21:27:03 2006.201.21:27:03.00:preob 2006.201.21:27:04.14/onsource/TRACKING 2006.201.21:27:04.14:!2006.201.21:27:13 2006.201.21:27:13.00:"tape 2006.201.21:27:13.00:"st=record 2006.201.21:27:13.00:data_valid=on 2006.201.21:27:13.00:midob 2006.201.21:27:13.14/onsource/TRACKING 2006.201.21:27:13.14/wx/20.05,1002.2,100 2006.201.21:27:13.22/cable/+6.4825E-03 2006.201.21:27:14.31/va/01,08,usb,yes,56,60 2006.201.21:27:14.31/va/02,07,usb,yes,61,62 2006.201.21:27:14.31/va/03,08,usb,yes,55,58 2006.201.21:27:14.31/va/04,07,usb,yes,63,66 2006.201.21:27:14.31/va/05,04,usb,yes,56,57 2006.201.21:27:14.31/va/06,05,usb,yes,56,57 2006.201.21:27:14.31/va/07,05,usb,yes,55,57 2006.201.21:27:14.31/va/08,04,usb,yes,55,64 2006.201.21:27:14.54/valo/01,524.99,yes,locked 2006.201.21:27:14.54/valo/02,534.99,yes,locked 2006.201.21:27:14.54/valo/03,564.99,yes,locked 2006.201.21:27:14.54/valo/04,624.99,yes,locked 2006.201.21:27:14.54/valo/05,734.99,yes,locked 2006.201.21:27:14.54/valo/06,814.99,yes,locked 2006.201.21:27:14.54/valo/07,864.99,yes,locked 2006.201.21:27:14.54/valo/08,884.99,yes,locked 2006.201.21:27:15.63/vb/01,04,usb,yes,32,30 2006.201.21:27:15.63/vb/02,05,usb,yes,30,30 2006.201.21:27:15.63/vb/03,04,usb,yes,32,35 2006.201.21:27:15.63/vb/04,05,usb,yes,32,31 2006.201.21:27:15.63/vb/05,04,usb,yes,28,31 2006.201.21:27:15.63/vb/06,04,usb,yes,33,29 2006.201.21:27:15.63/vb/07,04,usb,yes,33,33 2006.201.21:27:15.63/vb/08,04,usb,yes,30,34 2006.201.21:27:15.87/vblo/01,629.99,yes,locked 2006.201.21:27:15.87/vblo/02,634.99,yes,locked 2006.201.21:27:15.87/vblo/03,649.99,yes,locked 2006.201.21:27:15.87/vblo/04,679.99,yes,locked 2006.201.21:27:15.87/vblo/05,709.99,yes,locked 2006.201.21:27:15.87/vblo/06,719.99,yes,locked 2006.201.21:27:15.87/vblo/07,734.99,yes,locked 2006.201.21:27:15.87/vblo/08,744.99,yes,locked 2006.201.21:27:16.02/vabw/8 2006.201.21:27:16.17/vbbw/8 2006.201.21:27:16.26/xfe/off,on,16.0 2006.201.21:27:16.64/ifatt/23,28,28,28 2006.201.21:27:17.07/fmout-gps/S +4.55E-07 2006.201.21:27:17.11:!2006.201.21:29:23 2006.201.21:29:23.00:data_valid=off 2006.201.21:29:23.00:"et 2006.201.21:29:23.00:!+3s 2006.201.21:29:26.02:"tape 2006.201.21:29:26.02:postob 2006.201.21:29:26.18/cable/+6.4824E-03 2006.201.21:29:26.18/wx/20.05,1002.1,100 2006.201.21:29:26.24/fmout-gps/S +4.56E-07 2006.201.21:29:26.24:scan_name=201-2136,jd0607,570 2006.201.21:29:26.24:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.201.21:29:28.14#flagr#flagr/antenna,new-source 2006.201.21:29:28.14:checkk5 2006.201.21:29:28.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.21:29:28.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.21:29:29.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.21:29:29.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.21:29:30.04/chk_obsdata//k5ts1/T2012127??a.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.21:29:30.41/chk_obsdata//k5ts2/T2012127??b.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.21:29:30.78/chk_obsdata//k5ts3/T2012127??c.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.21:29:31.15/chk_obsdata//k5ts4/T2012127??d.dat file size is correct (nominal:520MB, actual:516MB). 2006.201.21:29:31.84/k5log//k5ts1_log_newline 2006.201.21:29:32.52/k5log//k5ts2_log_newline 2006.201.21:29:33.21/k5log//k5ts3_log_newline 2006.201.21:29:33.91/k5log//k5ts4_log_newline 2006.201.21:29:33.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.21:29:33.93:setupk4=1 2006.201.21:29:33.93$setupk4/echo=on 2006.201.21:29:33.93$setupk4/pcalon 2006.201.21:29:33.93$pcalon/"no phase cal control is implemented here 2006.201.21:29:33.93$setupk4/"tpicd=stop 2006.201.21:29:33.93$setupk4/"rec=synch_on 2006.201.21:29:33.93$setupk4/"rec_mode=128 2006.201.21:29:33.93$setupk4/!* 2006.201.21:29:33.93$setupk4/recpk4 2006.201.21:29:33.93$recpk4/recpatch= 2006.201.21:29:33.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.21:29:33.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.21:29:33.94$setupk4/vck44 2006.201.21:29:33.94$vck44/valo=1,524.99 2006.201.21:29:33.94#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.21:29:33.94#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.21:29:33.94#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:33.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:33.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:33.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:33.94#ibcon#enter wrdev, iclass 31, count 0 2006.201.21:29:33.94#ibcon#first serial, iclass 31, count 0 2006.201.21:29:33.94#ibcon#enter sib2, iclass 31, count 0 2006.201.21:29:33.94#ibcon#flushed, iclass 31, count 0 2006.201.21:29:33.94#ibcon#about to write, iclass 31, count 0 2006.201.21:29:33.94#ibcon#wrote, iclass 31, count 0 2006.201.21:29:33.94#ibcon#about to read 3, iclass 31, count 0 2006.201.21:29:33.97#ibcon#read 3, iclass 31, count 0 2006.201.21:29:33.97#ibcon#about to read 4, iclass 31, count 0 2006.201.21:29:33.97#ibcon#read 4, iclass 31, count 0 2006.201.21:29:33.97#ibcon#about to read 5, iclass 31, count 0 2006.201.21:29:33.97#ibcon#read 5, iclass 31, count 0 2006.201.21:29:33.97#ibcon#about to read 6, iclass 31, count 0 2006.201.21:29:33.97#ibcon#read 6, iclass 31, count 0 2006.201.21:29:33.97#ibcon#end of sib2, iclass 31, count 0 2006.201.21:29:33.97#ibcon#*mode == 0, iclass 31, count 0 2006.201.21:29:33.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.21:29:33.97#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.21:29:33.97#ibcon#*before write, iclass 31, count 0 2006.201.21:29:33.97#ibcon#enter sib2, iclass 31, count 0 2006.201.21:29:33.97#ibcon#flushed, iclass 31, count 0 2006.201.21:29:33.97#ibcon#about to write, iclass 31, count 0 2006.201.21:29:33.97#ibcon#wrote, iclass 31, count 0 2006.201.21:29:33.97#ibcon#about to read 3, iclass 31, count 0 2006.201.21:29:34.03#ibcon#read 3, iclass 31, count 0 2006.201.21:29:34.03#ibcon#about to read 4, iclass 31, count 0 2006.201.21:29:34.03#ibcon#read 4, iclass 31, count 0 2006.201.21:29:34.03#ibcon#about to read 5, iclass 31, count 0 2006.201.21:29:34.03#ibcon#read 5, iclass 31, count 0 2006.201.21:29:34.03#ibcon#about to read 6, iclass 31, count 0 2006.201.21:29:34.03#ibcon#read 6, iclass 31, count 0 2006.201.21:29:34.03#ibcon#end of sib2, iclass 31, count 0 2006.201.21:29:34.03#ibcon#*after write, iclass 31, count 0 2006.201.21:29:34.03#ibcon#*before return 0, iclass 31, count 0 2006.201.21:29:34.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:34.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:34.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.21:29:34.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.21:29:34.03$vck44/va=1,8 2006.201.21:29:34.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.21:29:34.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.21:29:34.03#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:34.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:34.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:34.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:34.03#ibcon#enter wrdev, iclass 33, count 2 2006.201.21:29:34.03#ibcon#first serial, iclass 33, count 2 2006.201.21:29:34.03#ibcon#enter sib2, iclass 33, count 2 2006.201.21:29:34.03#ibcon#flushed, iclass 33, count 2 2006.201.21:29:34.03#ibcon#about to write, iclass 33, count 2 2006.201.21:29:34.03#ibcon#wrote, iclass 33, count 2 2006.201.21:29:34.03#ibcon#about to read 3, iclass 33, count 2 2006.201.21:29:34.05#ibcon#read 3, iclass 33, count 2 2006.201.21:29:34.05#ibcon#about to read 4, iclass 33, count 2 2006.201.21:29:34.05#ibcon#read 4, iclass 33, count 2 2006.201.21:29:34.05#ibcon#about to read 5, iclass 33, count 2 2006.201.21:29:34.05#ibcon#read 5, iclass 33, count 2 2006.201.21:29:34.05#ibcon#about to read 6, iclass 33, count 2 2006.201.21:29:34.05#ibcon#read 6, iclass 33, count 2 2006.201.21:29:34.05#ibcon#end of sib2, iclass 33, count 2 2006.201.21:29:34.05#ibcon#*mode == 0, iclass 33, count 2 2006.201.21:29:34.05#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.21:29:34.05#ibcon#[25=AT01-08\r\n] 2006.201.21:29:34.05#ibcon#*before write, iclass 33, count 2 2006.201.21:29:34.05#ibcon#enter sib2, iclass 33, count 2 2006.201.21:29:34.05#ibcon#flushed, iclass 33, count 2 2006.201.21:29:34.05#ibcon#about to write, iclass 33, count 2 2006.201.21:29:34.05#ibcon#wrote, iclass 33, count 2 2006.201.21:29:34.05#ibcon#about to read 3, iclass 33, count 2 2006.201.21:29:34.09#ibcon#read 3, iclass 33, count 2 2006.201.21:29:34.09#ibcon#about to read 4, iclass 33, count 2 2006.201.21:29:34.09#ibcon#read 4, iclass 33, count 2 2006.201.21:29:34.09#ibcon#about to read 5, iclass 33, count 2 2006.201.21:29:34.09#ibcon#read 5, iclass 33, count 2 2006.201.21:29:34.09#ibcon#about to read 6, iclass 33, count 2 2006.201.21:29:34.09#ibcon#read 6, iclass 33, count 2 2006.201.21:29:34.09#ibcon#end of sib2, iclass 33, count 2 2006.201.21:29:34.09#ibcon#*after write, iclass 33, count 2 2006.201.21:29:34.09#ibcon#*before return 0, iclass 33, count 2 2006.201.21:29:34.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:34.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:34.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.21:29:34.09#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:34.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:34.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:34.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:34.21#ibcon#enter wrdev, iclass 33, count 0 2006.201.21:29:34.21#ibcon#first serial, iclass 33, count 0 2006.201.21:29:34.21#ibcon#enter sib2, iclass 33, count 0 2006.201.21:29:34.21#ibcon#flushed, iclass 33, count 0 2006.201.21:29:34.21#ibcon#about to write, iclass 33, count 0 2006.201.21:29:34.21#ibcon#wrote, iclass 33, count 0 2006.201.21:29:34.21#ibcon#about to read 3, iclass 33, count 0 2006.201.21:29:34.24#ibcon#read 3, iclass 33, count 0 2006.201.21:29:34.24#ibcon#about to read 4, iclass 33, count 0 2006.201.21:29:34.24#ibcon#read 4, iclass 33, count 0 2006.201.21:29:34.24#ibcon#about to read 5, iclass 33, count 0 2006.201.21:29:34.24#ibcon#read 5, iclass 33, count 0 2006.201.21:29:34.24#ibcon#about to read 6, iclass 33, count 0 2006.201.21:29:34.24#ibcon#read 6, iclass 33, count 0 2006.201.21:29:34.24#ibcon#end of sib2, iclass 33, count 0 2006.201.21:29:34.24#ibcon#*mode == 0, iclass 33, count 0 2006.201.21:29:34.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.21:29:34.24#ibcon#[25=USB\r\n] 2006.201.21:29:34.24#ibcon#*before write, iclass 33, count 0 2006.201.21:29:34.24#ibcon#enter sib2, iclass 33, count 0 2006.201.21:29:34.24#ibcon#flushed, iclass 33, count 0 2006.201.21:29:34.24#ibcon#about to write, iclass 33, count 0 2006.201.21:29:34.24#ibcon#wrote, iclass 33, count 0 2006.201.21:29:34.24#ibcon#about to read 3, iclass 33, count 0 2006.201.21:29:34.27#ibcon#read 3, iclass 33, count 0 2006.201.21:29:34.27#ibcon#about to read 4, iclass 33, count 0 2006.201.21:29:34.27#ibcon#read 4, iclass 33, count 0 2006.201.21:29:34.27#ibcon#about to read 5, iclass 33, count 0 2006.201.21:29:34.27#ibcon#read 5, iclass 33, count 0 2006.201.21:29:34.27#ibcon#about to read 6, iclass 33, count 0 2006.201.21:29:34.27#ibcon#read 6, iclass 33, count 0 2006.201.21:29:34.27#ibcon#end of sib2, iclass 33, count 0 2006.201.21:29:34.27#ibcon#*after write, iclass 33, count 0 2006.201.21:29:34.27#ibcon#*before return 0, iclass 33, count 0 2006.201.21:29:34.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:34.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:34.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.21:29:34.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.21:29:34.27$vck44/valo=2,534.99 2006.201.21:29:34.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.21:29:34.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.21:29:34.27#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:34.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:34.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:34.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:34.27#ibcon#enter wrdev, iclass 35, count 0 2006.201.21:29:34.27#ibcon#first serial, iclass 35, count 0 2006.201.21:29:34.27#ibcon#enter sib2, iclass 35, count 0 2006.201.21:29:34.27#ibcon#flushed, iclass 35, count 0 2006.201.21:29:34.27#ibcon#about to write, iclass 35, count 0 2006.201.21:29:34.27#ibcon#wrote, iclass 35, count 0 2006.201.21:29:34.27#ibcon#about to read 3, iclass 35, count 0 2006.201.21:29:34.29#ibcon#read 3, iclass 35, count 0 2006.201.21:29:34.29#ibcon#about to read 4, iclass 35, count 0 2006.201.21:29:34.29#ibcon#read 4, iclass 35, count 0 2006.201.21:29:34.29#ibcon#about to read 5, iclass 35, count 0 2006.201.21:29:34.29#ibcon#read 5, iclass 35, count 0 2006.201.21:29:34.29#ibcon#about to read 6, iclass 35, count 0 2006.201.21:29:34.29#ibcon#read 6, iclass 35, count 0 2006.201.21:29:34.29#ibcon#end of sib2, iclass 35, count 0 2006.201.21:29:34.29#ibcon#*mode == 0, iclass 35, count 0 2006.201.21:29:34.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.21:29:34.29#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.21:29:34.29#ibcon#*before write, iclass 35, count 0 2006.201.21:29:34.29#ibcon#enter sib2, iclass 35, count 0 2006.201.21:29:34.29#ibcon#flushed, iclass 35, count 0 2006.201.21:29:34.29#ibcon#about to write, iclass 35, count 0 2006.201.21:29:34.29#ibcon#wrote, iclass 35, count 0 2006.201.21:29:34.29#ibcon#about to read 3, iclass 35, count 0 2006.201.21:29:34.33#ibcon#read 3, iclass 35, count 0 2006.201.21:29:34.33#ibcon#about to read 4, iclass 35, count 0 2006.201.21:29:34.33#ibcon#read 4, iclass 35, count 0 2006.201.21:29:34.33#ibcon#about to read 5, iclass 35, count 0 2006.201.21:29:34.33#ibcon#read 5, iclass 35, count 0 2006.201.21:29:34.33#ibcon#about to read 6, iclass 35, count 0 2006.201.21:29:34.33#ibcon#read 6, iclass 35, count 0 2006.201.21:29:34.33#ibcon#end of sib2, iclass 35, count 0 2006.201.21:29:34.33#ibcon#*after write, iclass 35, count 0 2006.201.21:29:34.33#ibcon#*before return 0, iclass 35, count 0 2006.201.21:29:34.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:34.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:34.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.21:29:34.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.21:29:34.33$vck44/va=2,7 2006.201.21:29:34.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.21:29:34.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.21:29:34.33#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:34.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:34.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:34.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:34.39#ibcon#enter wrdev, iclass 37, count 2 2006.201.21:29:34.39#ibcon#first serial, iclass 37, count 2 2006.201.21:29:34.39#ibcon#enter sib2, iclass 37, count 2 2006.201.21:29:34.39#ibcon#flushed, iclass 37, count 2 2006.201.21:29:34.39#ibcon#about to write, iclass 37, count 2 2006.201.21:29:34.39#ibcon#wrote, iclass 37, count 2 2006.201.21:29:34.39#ibcon#about to read 3, iclass 37, count 2 2006.201.21:29:34.41#ibcon#read 3, iclass 37, count 2 2006.201.21:29:34.41#ibcon#about to read 4, iclass 37, count 2 2006.201.21:29:34.41#ibcon#read 4, iclass 37, count 2 2006.201.21:29:34.41#ibcon#about to read 5, iclass 37, count 2 2006.201.21:29:34.41#ibcon#read 5, iclass 37, count 2 2006.201.21:29:34.41#ibcon#about to read 6, iclass 37, count 2 2006.201.21:29:34.41#ibcon#read 6, iclass 37, count 2 2006.201.21:29:34.41#ibcon#end of sib2, iclass 37, count 2 2006.201.21:29:34.41#ibcon#*mode == 0, iclass 37, count 2 2006.201.21:29:34.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.21:29:34.41#ibcon#[25=AT02-07\r\n] 2006.201.21:29:34.41#ibcon#*before write, iclass 37, count 2 2006.201.21:29:34.41#ibcon#enter sib2, iclass 37, count 2 2006.201.21:29:34.41#ibcon#flushed, iclass 37, count 2 2006.201.21:29:34.41#ibcon#about to write, iclass 37, count 2 2006.201.21:29:34.41#ibcon#wrote, iclass 37, count 2 2006.201.21:29:34.41#ibcon#about to read 3, iclass 37, count 2 2006.201.21:29:34.44#ibcon#read 3, iclass 37, count 2 2006.201.21:29:34.44#ibcon#about to read 4, iclass 37, count 2 2006.201.21:29:34.44#ibcon#read 4, iclass 37, count 2 2006.201.21:29:34.44#ibcon#about to read 5, iclass 37, count 2 2006.201.21:29:34.44#ibcon#read 5, iclass 37, count 2 2006.201.21:29:34.44#ibcon#about to read 6, iclass 37, count 2 2006.201.21:29:34.44#ibcon#read 6, iclass 37, count 2 2006.201.21:29:34.44#ibcon#end of sib2, iclass 37, count 2 2006.201.21:29:34.44#ibcon#*after write, iclass 37, count 2 2006.201.21:29:34.44#ibcon#*before return 0, iclass 37, count 2 2006.201.21:29:34.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:34.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:34.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.21:29:34.44#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:34.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:34.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:34.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:34.56#ibcon#enter wrdev, iclass 37, count 0 2006.201.21:29:34.56#ibcon#first serial, iclass 37, count 0 2006.201.21:29:34.56#ibcon#enter sib2, iclass 37, count 0 2006.201.21:29:34.56#ibcon#flushed, iclass 37, count 0 2006.201.21:29:34.56#ibcon#about to write, iclass 37, count 0 2006.201.21:29:34.56#ibcon#wrote, iclass 37, count 0 2006.201.21:29:34.56#ibcon#about to read 3, iclass 37, count 0 2006.201.21:29:34.58#ibcon#read 3, iclass 37, count 0 2006.201.21:29:34.58#ibcon#about to read 4, iclass 37, count 0 2006.201.21:29:34.58#ibcon#read 4, iclass 37, count 0 2006.201.21:29:34.58#ibcon#about to read 5, iclass 37, count 0 2006.201.21:29:34.58#ibcon#read 5, iclass 37, count 0 2006.201.21:29:34.58#ibcon#about to read 6, iclass 37, count 0 2006.201.21:29:34.58#ibcon#read 6, iclass 37, count 0 2006.201.21:29:34.58#ibcon#end of sib2, iclass 37, count 0 2006.201.21:29:34.58#ibcon#*mode == 0, iclass 37, count 0 2006.201.21:29:34.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.21:29:34.58#ibcon#[25=USB\r\n] 2006.201.21:29:34.58#ibcon#*before write, iclass 37, count 0 2006.201.21:29:34.58#ibcon#enter sib2, iclass 37, count 0 2006.201.21:29:34.58#ibcon#flushed, iclass 37, count 0 2006.201.21:29:34.58#ibcon#about to write, iclass 37, count 0 2006.201.21:29:34.58#ibcon#wrote, iclass 37, count 0 2006.201.21:29:34.58#ibcon#about to read 3, iclass 37, count 0 2006.201.21:29:34.61#ibcon#read 3, iclass 37, count 0 2006.201.21:29:34.61#ibcon#about to read 4, iclass 37, count 0 2006.201.21:29:34.61#ibcon#read 4, iclass 37, count 0 2006.201.21:29:34.61#ibcon#about to read 5, iclass 37, count 0 2006.201.21:29:34.61#ibcon#read 5, iclass 37, count 0 2006.201.21:29:34.61#ibcon#about to read 6, iclass 37, count 0 2006.201.21:29:34.61#ibcon#read 6, iclass 37, count 0 2006.201.21:29:34.61#ibcon#end of sib2, iclass 37, count 0 2006.201.21:29:34.61#ibcon#*after write, iclass 37, count 0 2006.201.21:29:34.61#ibcon#*before return 0, iclass 37, count 0 2006.201.21:29:34.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:34.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:34.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.21:29:34.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.21:29:34.61$vck44/valo=3,564.99 2006.201.21:29:34.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.21:29:34.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.21:29:34.61#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:34.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:34.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:34.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:34.61#ibcon#enter wrdev, iclass 39, count 0 2006.201.21:29:34.61#ibcon#first serial, iclass 39, count 0 2006.201.21:29:34.61#ibcon#enter sib2, iclass 39, count 0 2006.201.21:29:34.61#ibcon#flushed, iclass 39, count 0 2006.201.21:29:34.61#ibcon#about to write, iclass 39, count 0 2006.201.21:29:34.61#ibcon#wrote, iclass 39, count 0 2006.201.21:29:34.61#ibcon#about to read 3, iclass 39, count 0 2006.201.21:29:34.63#ibcon#read 3, iclass 39, count 0 2006.201.21:29:34.63#ibcon#about to read 4, iclass 39, count 0 2006.201.21:29:34.63#ibcon#read 4, iclass 39, count 0 2006.201.21:29:34.63#ibcon#about to read 5, iclass 39, count 0 2006.201.21:29:34.63#ibcon#read 5, iclass 39, count 0 2006.201.21:29:34.63#ibcon#about to read 6, iclass 39, count 0 2006.201.21:29:34.63#ibcon#read 6, iclass 39, count 0 2006.201.21:29:34.63#ibcon#end of sib2, iclass 39, count 0 2006.201.21:29:34.63#ibcon#*mode == 0, iclass 39, count 0 2006.201.21:29:34.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.21:29:34.63#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.21:29:34.63#ibcon#*before write, iclass 39, count 0 2006.201.21:29:34.63#ibcon#enter sib2, iclass 39, count 0 2006.201.21:29:34.63#ibcon#flushed, iclass 39, count 0 2006.201.21:29:34.63#ibcon#about to write, iclass 39, count 0 2006.201.21:29:34.63#ibcon#wrote, iclass 39, count 0 2006.201.21:29:34.63#ibcon#about to read 3, iclass 39, count 0 2006.201.21:29:34.68#ibcon#read 3, iclass 39, count 0 2006.201.21:29:34.68#ibcon#about to read 4, iclass 39, count 0 2006.201.21:29:34.68#ibcon#read 4, iclass 39, count 0 2006.201.21:29:34.68#ibcon#about to read 5, iclass 39, count 0 2006.201.21:29:34.68#ibcon#read 5, iclass 39, count 0 2006.201.21:29:34.68#ibcon#about to read 6, iclass 39, count 0 2006.201.21:29:34.68#ibcon#read 6, iclass 39, count 0 2006.201.21:29:34.68#ibcon#end of sib2, iclass 39, count 0 2006.201.21:29:34.68#ibcon#*after write, iclass 39, count 0 2006.201.21:29:34.68#ibcon#*before return 0, iclass 39, count 0 2006.201.21:29:34.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:34.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:34.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.21:29:34.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.21:29:34.68$vck44/va=3,8 2006.201.21:29:34.68#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.21:29:34.68#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.21:29:34.68#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:34.68#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:34.73#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:34.73#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:34.73#ibcon#enter wrdev, iclass 2, count 2 2006.201.21:29:34.73#ibcon#first serial, iclass 2, count 2 2006.201.21:29:34.73#ibcon#enter sib2, iclass 2, count 2 2006.201.21:29:34.73#ibcon#flushed, iclass 2, count 2 2006.201.21:29:34.73#ibcon#about to write, iclass 2, count 2 2006.201.21:29:34.73#ibcon#wrote, iclass 2, count 2 2006.201.21:29:34.73#ibcon#about to read 3, iclass 2, count 2 2006.201.21:29:34.75#ibcon#read 3, iclass 2, count 2 2006.201.21:29:34.75#ibcon#about to read 4, iclass 2, count 2 2006.201.21:29:34.75#ibcon#read 4, iclass 2, count 2 2006.201.21:29:34.75#ibcon#about to read 5, iclass 2, count 2 2006.201.21:29:34.75#ibcon#read 5, iclass 2, count 2 2006.201.21:29:34.75#ibcon#about to read 6, iclass 2, count 2 2006.201.21:29:34.75#ibcon#read 6, iclass 2, count 2 2006.201.21:29:34.75#ibcon#end of sib2, iclass 2, count 2 2006.201.21:29:34.75#ibcon#*mode == 0, iclass 2, count 2 2006.201.21:29:34.75#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.21:29:34.75#ibcon#[25=AT03-08\r\n] 2006.201.21:29:34.75#ibcon#*before write, iclass 2, count 2 2006.201.21:29:34.75#ibcon#enter sib2, iclass 2, count 2 2006.201.21:29:34.75#ibcon#flushed, iclass 2, count 2 2006.201.21:29:34.75#ibcon#about to write, iclass 2, count 2 2006.201.21:29:34.75#ibcon#wrote, iclass 2, count 2 2006.201.21:29:34.75#ibcon#about to read 3, iclass 2, count 2 2006.201.21:29:34.78#ibcon#read 3, iclass 2, count 2 2006.201.21:29:34.78#ibcon#about to read 4, iclass 2, count 2 2006.201.21:29:34.78#ibcon#read 4, iclass 2, count 2 2006.201.21:29:34.78#ibcon#about to read 5, iclass 2, count 2 2006.201.21:29:34.78#ibcon#read 5, iclass 2, count 2 2006.201.21:29:34.78#ibcon#about to read 6, iclass 2, count 2 2006.201.21:29:34.78#ibcon#read 6, iclass 2, count 2 2006.201.21:29:34.78#ibcon#end of sib2, iclass 2, count 2 2006.201.21:29:34.78#ibcon#*after write, iclass 2, count 2 2006.201.21:29:34.78#ibcon#*before return 0, iclass 2, count 2 2006.201.21:29:34.78#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:34.78#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:34.78#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.21:29:34.78#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:34.78#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:34.90#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:34.90#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:34.90#ibcon#enter wrdev, iclass 2, count 0 2006.201.21:29:34.90#ibcon#first serial, iclass 2, count 0 2006.201.21:29:34.90#ibcon#enter sib2, iclass 2, count 0 2006.201.21:29:34.90#ibcon#flushed, iclass 2, count 0 2006.201.21:29:34.90#ibcon#about to write, iclass 2, count 0 2006.201.21:29:34.90#ibcon#wrote, iclass 2, count 0 2006.201.21:29:34.90#ibcon#about to read 3, iclass 2, count 0 2006.201.21:29:34.92#ibcon#read 3, iclass 2, count 0 2006.201.21:29:34.92#ibcon#about to read 4, iclass 2, count 0 2006.201.21:29:34.92#ibcon#read 4, iclass 2, count 0 2006.201.21:29:34.92#ibcon#about to read 5, iclass 2, count 0 2006.201.21:29:34.92#ibcon#read 5, iclass 2, count 0 2006.201.21:29:34.92#ibcon#about to read 6, iclass 2, count 0 2006.201.21:29:34.92#ibcon#read 6, iclass 2, count 0 2006.201.21:29:34.92#ibcon#end of sib2, iclass 2, count 0 2006.201.21:29:34.92#ibcon#*mode == 0, iclass 2, count 0 2006.201.21:29:34.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.21:29:34.92#ibcon#[25=USB\r\n] 2006.201.21:29:34.92#ibcon#*before write, iclass 2, count 0 2006.201.21:29:34.92#ibcon#enter sib2, iclass 2, count 0 2006.201.21:29:34.92#ibcon#flushed, iclass 2, count 0 2006.201.21:29:34.92#ibcon#about to write, iclass 2, count 0 2006.201.21:29:34.92#ibcon#wrote, iclass 2, count 0 2006.201.21:29:34.92#ibcon#about to read 3, iclass 2, count 0 2006.201.21:29:34.95#ibcon#read 3, iclass 2, count 0 2006.201.21:29:34.95#ibcon#about to read 4, iclass 2, count 0 2006.201.21:29:34.95#ibcon#read 4, iclass 2, count 0 2006.201.21:29:34.95#ibcon#about to read 5, iclass 2, count 0 2006.201.21:29:34.95#ibcon#read 5, iclass 2, count 0 2006.201.21:29:34.95#ibcon#about to read 6, iclass 2, count 0 2006.201.21:29:34.95#ibcon#read 6, iclass 2, count 0 2006.201.21:29:34.95#ibcon#end of sib2, iclass 2, count 0 2006.201.21:29:34.95#ibcon#*after write, iclass 2, count 0 2006.201.21:29:34.95#ibcon#*before return 0, iclass 2, count 0 2006.201.21:29:34.95#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:34.95#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:34.95#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.21:29:34.95#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.21:29:34.95$vck44/valo=4,624.99 2006.201.21:29:34.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.21:29:34.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.21:29:34.95#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:34.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:34.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:34.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:34.95#ibcon#enter wrdev, iclass 5, count 0 2006.201.21:29:34.95#ibcon#first serial, iclass 5, count 0 2006.201.21:29:34.95#ibcon#enter sib2, iclass 5, count 0 2006.201.21:29:34.95#ibcon#flushed, iclass 5, count 0 2006.201.21:29:34.95#ibcon#about to write, iclass 5, count 0 2006.201.21:29:34.95#ibcon#wrote, iclass 5, count 0 2006.201.21:29:34.95#ibcon#about to read 3, iclass 5, count 0 2006.201.21:29:34.97#ibcon#read 3, iclass 5, count 0 2006.201.21:29:34.97#ibcon#about to read 4, iclass 5, count 0 2006.201.21:29:34.97#ibcon#read 4, iclass 5, count 0 2006.201.21:29:34.97#ibcon#about to read 5, iclass 5, count 0 2006.201.21:29:34.97#ibcon#read 5, iclass 5, count 0 2006.201.21:29:34.97#ibcon#about to read 6, iclass 5, count 0 2006.201.21:29:34.97#ibcon#read 6, iclass 5, count 0 2006.201.21:29:34.97#ibcon#end of sib2, iclass 5, count 0 2006.201.21:29:34.97#ibcon#*mode == 0, iclass 5, count 0 2006.201.21:29:34.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.21:29:34.97#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.21:29:34.97#ibcon#*before write, iclass 5, count 0 2006.201.21:29:34.97#ibcon#enter sib2, iclass 5, count 0 2006.201.21:29:34.97#ibcon#flushed, iclass 5, count 0 2006.201.21:29:34.97#ibcon#about to write, iclass 5, count 0 2006.201.21:29:34.97#ibcon#wrote, iclass 5, count 0 2006.201.21:29:34.97#ibcon#about to read 3, iclass 5, count 0 2006.201.21:29:35.02#ibcon#read 3, iclass 5, count 0 2006.201.21:29:35.02#ibcon#about to read 4, iclass 5, count 0 2006.201.21:29:35.02#ibcon#read 4, iclass 5, count 0 2006.201.21:29:35.02#ibcon#about to read 5, iclass 5, count 0 2006.201.21:29:35.02#ibcon#read 5, iclass 5, count 0 2006.201.21:29:35.02#ibcon#about to read 6, iclass 5, count 0 2006.201.21:29:35.02#ibcon#read 6, iclass 5, count 0 2006.201.21:29:35.02#ibcon#end of sib2, iclass 5, count 0 2006.201.21:29:35.02#ibcon#*after write, iclass 5, count 0 2006.201.21:29:35.02#ibcon#*before return 0, iclass 5, count 0 2006.201.21:29:35.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:35.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:35.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.21:29:35.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.21:29:35.02$vck44/va=4,7 2006.201.21:29:35.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.21:29:35.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.21:29:35.02#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:35.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:35.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:35.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:35.07#ibcon#enter wrdev, iclass 7, count 2 2006.201.21:29:35.07#ibcon#first serial, iclass 7, count 2 2006.201.21:29:35.07#ibcon#enter sib2, iclass 7, count 2 2006.201.21:29:35.07#ibcon#flushed, iclass 7, count 2 2006.201.21:29:35.07#ibcon#about to write, iclass 7, count 2 2006.201.21:29:35.07#ibcon#wrote, iclass 7, count 2 2006.201.21:29:35.07#ibcon#about to read 3, iclass 7, count 2 2006.201.21:29:35.09#ibcon#read 3, iclass 7, count 2 2006.201.21:29:35.09#ibcon#about to read 4, iclass 7, count 2 2006.201.21:29:35.09#ibcon#read 4, iclass 7, count 2 2006.201.21:29:35.09#ibcon#about to read 5, iclass 7, count 2 2006.201.21:29:35.09#ibcon#read 5, iclass 7, count 2 2006.201.21:29:35.09#ibcon#about to read 6, iclass 7, count 2 2006.201.21:29:35.09#ibcon#read 6, iclass 7, count 2 2006.201.21:29:35.09#ibcon#end of sib2, iclass 7, count 2 2006.201.21:29:35.09#ibcon#*mode == 0, iclass 7, count 2 2006.201.21:29:35.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.21:29:35.09#ibcon#[25=AT04-07\r\n] 2006.201.21:29:35.09#ibcon#*before write, iclass 7, count 2 2006.201.21:29:35.09#ibcon#enter sib2, iclass 7, count 2 2006.201.21:29:35.09#ibcon#flushed, iclass 7, count 2 2006.201.21:29:35.09#ibcon#about to write, iclass 7, count 2 2006.201.21:29:35.09#ibcon#wrote, iclass 7, count 2 2006.201.21:29:35.09#ibcon#about to read 3, iclass 7, count 2 2006.201.21:29:35.12#ibcon#read 3, iclass 7, count 2 2006.201.21:29:35.12#ibcon#about to read 4, iclass 7, count 2 2006.201.21:29:35.12#ibcon#read 4, iclass 7, count 2 2006.201.21:29:35.12#ibcon#about to read 5, iclass 7, count 2 2006.201.21:29:35.12#ibcon#read 5, iclass 7, count 2 2006.201.21:29:35.12#ibcon#about to read 6, iclass 7, count 2 2006.201.21:29:35.12#ibcon#read 6, iclass 7, count 2 2006.201.21:29:35.12#ibcon#end of sib2, iclass 7, count 2 2006.201.21:29:35.12#ibcon#*after write, iclass 7, count 2 2006.201.21:29:35.12#ibcon#*before return 0, iclass 7, count 2 2006.201.21:29:35.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:35.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:35.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.21:29:35.12#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:35.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:35.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:35.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:35.24#ibcon#enter wrdev, iclass 7, count 0 2006.201.21:29:35.24#ibcon#first serial, iclass 7, count 0 2006.201.21:29:35.24#ibcon#enter sib2, iclass 7, count 0 2006.201.21:29:35.24#ibcon#flushed, iclass 7, count 0 2006.201.21:29:35.24#ibcon#about to write, iclass 7, count 0 2006.201.21:29:35.24#ibcon#wrote, iclass 7, count 0 2006.201.21:29:35.24#ibcon#about to read 3, iclass 7, count 0 2006.201.21:29:35.26#ibcon#read 3, iclass 7, count 0 2006.201.21:29:35.26#ibcon#about to read 4, iclass 7, count 0 2006.201.21:29:35.26#ibcon#read 4, iclass 7, count 0 2006.201.21:29:35.26#ibcon#about to read 5, iclass 7, count 0 2006.201.21:29:35.26#ibcon#read 5, iclass 7, count 0 2006.201.21:29:35.26#ibcon#about to read 6, iclass 7, count 0 2006.201.21:29:35.26#ibcon#read 6, iclass 7, count 0 2006.201.21:29:35.26#ibcon#end of sib2, iclass 7, count 0 2006.201.21:29:35.26#ibcon#*mode == 0, iclass 7, count 0 2006.201.21:29:35.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.21:29:35.26#ibcon#[25=USB\r\n] 2006.201.21:29:35.26#ibcon#*before write, iclass 7, count 0 2006.201.21:29:35.26#ibcon#enter sib2, iclass 7, count 0 2006.201.21:29:35.26#ibcon#flushed, iclass 7, count 0 2006.201.21:29:35.26#ibcon#about to write, iclass 7, count 0 2006.201.21:29:35.26#ibcon#wrote, iclass 7, count 0 2006.201.21:29:35.26#ibcon#about to read 3, iclass 7, count 0 2006.201.21:29:35.29#ibcon#read 3, iclass 7, count 0 2006.201.21:29:35.29#ibcon#about to read 4, iclass 7, count 0 2006.201.21:29:35.29#ibcon#read 4, iclass 7, count 0 2006.201.21:29:35.29#ibcon#about to read 5, iclass 7, count 0 2006.201.21:29:35.29#ibcon#read 5, iclass 7, count 0 2006.201.21:29:35.29#ibcon#about to read 6, iclass 7, count 0 2006.201.21:29:35.29#ibcon#read 6, iclass 7, count 0 2006.201.21:29:35.29#ibcon#end of sib2, iclass 7, count 0 2006.201.21:29:35.29#ibcon#*after write, iclass 7, count 0 2006.201.21:29:35.29#ibcon#*before return 0, iclass 7, count 0 2006.201.21:29:35.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:35.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:35.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.21:29:35.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.21:29:35.29$vck44/valo=5,734.99 2006.201.21:29:35.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.21:29:35.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.21:29:35.29#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:35.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:35.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:35.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:35.29#ibcon#enter wrdev, iclass 11, count 0 2006.201.21:29:35.29#ibcon#first serial, iclass 11, count 0 2006.201.21:29:35.29#ibcon#enter sib2, iclass 11, count 0 2006.201.21:29:35.29#ibcon#flushed, iclass 11, count 0 2006.201.21:29:35.29#ibcon#about to write, iclass 11, count 0 2006.201.21:29:35.29#ibcon#wrote, iclass 11, count 0 2006.201.21:29:35.29#ibcon#about to read 3, iclass 11, count 0 2006.201.21:29:35.31#ibcon#read 3, iclass 11, count 0 2006.201.21:29:35.31#ibcon#about to read 4, iclass 11, count 0 2006.201.21:29:35.31#ibcon#read 4, iclass 11, count 0 2006.201.21:29:35.31#ibcon#about to read 5, iclass 11, count 0 2006.201.21:29:35.31#ibcon#read 5, iclass 11, count 0 2006.201.21:29:35.31#ibcon#about to read 6, iclass 11, count 0 2006.201.21:29:35.31#ibcon#read 6, iclass 11, count 0 2006.201.21:29:35.31#ibcon#end of sib2, iclass 11, count 0 2006.201.21:29:35.31#ibcon#*mode == 0, iclass 11, count 0 2006.201.21:29:35.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.21:29:35.31#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.21:29:35.31#ibcon#*before write, iclass 11, count 0 2006.201.21:29:35.31#ibcon#enter sib2, iclass 11, count 0 2006.201.21:29:35.31#ibcon#flushed, iclass 11, count 0 2006.201.21:29:35.31#ibcon#about to write, iclass 11, count 0 2006.201.21:29:35.31#ibcon#wrote, iclass 11, count 0 2006.201.21:29:35.31#ibcon#about to read 3, iclass 11, count 0 2006.201.21:29:35.35#ibcon#read 3, iclass 11, count 0 2006.201.21:29:35.35#ibcon#about to read 4, iclass 11, count 0 2006.201.21:29:35.35#ibcon#read 4, iclass 11, count 0 2006.201.21:29:35.35#ibcon#about to read 5, iclass 11, count 0 2006.201.21:29:35.35#ibcon#read 5, iclass 11, count 0 2006.201.21:29:35.35#ibcon#about to read 6, iclass 11, count 0 2006.201.21:29:35.35#ibcon#read 6, iclass 11, count 0 2006.201.21:29:35.35#ibcon#end of sib2, iclass 11, count 0 2006.201.21:29:35.35#ibcon#*after write, iclass 11, count 0 2006.201.21:29:35.35#ibcon#*before return 0, iclass 11, count 0 2006.201.21:29:35.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:35.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:35.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.21:29:35.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.21:29:35.35$vck44/va=5,4 2006.201.21:29:35.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.21:29:35.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.21:29:35.35#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:35.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:35.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:35.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:35.41#ibcon#enter wrdev, iclass 13, count 2 2006.201.21:29:35.41#ibcon#first serial, iclass 13, count 2 2006.201.21:29:35.41#ibcon#enter sib2, iclass 13, count 2 2006.201.21:29:35.41#ibcon#flushed, iclass 13, count 2 2006.201.21:29:35.41#ibcon#about to write, iclass 13, count 2 2006.201.21:29:35.41#ibcon#wrote, iclass 13, count 2 2006.201.21:29:35.41#ibcon#about to read 3, iclass 13, count 2 2006.201.21:29:35.43#ibcon#read 3, iclass 13, count 2 2006.201.21:29:35.43#ibcon#about to read 4, iclass 13, count 2 2006.201.21:29:35.43#ibcon#read 4, iclass 13, count 2 2006.201.21:29:35.43#ibcon#about to read 5, iclass 13, count 2 2006.201.21:29:35.43#ibcon#read 5, iclass 13, count 2 2006.201.21:29:35.43#ibcon#about to read 6, iclass 13, count 2 2006.201.21:29:35.43#ibcon#read 6, iclass 13, count 2 2006.201.21:29:35.43#ibcon#end of sib2, iclass 13, count 2 2006.201.21:29:35.43#ibcon#*mode == 0, iclass 13, count 2 2006.201.21:29:35.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.21:29:35.43#ibcon#[25=AT05-04\r\n] 2006.201.21:29:35.43#ibcon#*before write, iclass 13, count 2 2006.201.21:29:35.43#ibcon#enter sib2, iclass 13, count 2 2006.201.21:29:35.43#ibcon#flushed, iclass 13, count 2 2006.201.21:29:35.43#ibcon#about to write, iclass 13, count 2 2006.201.21:29:35.43#ibcon#wrote, iclass 13, count 2 2006.201.21:29:35.43#ibcon#about to read 3, iclass 13, count 2 2006.201.21:29:35.46#ibcon#read 3, iclass 13, count 2 2006.201.21:29:35.46#ibcon#about to read 4, iclass 13, count 2 2006.201.21:29:35.46#ibcon#read 4, iclass 13, count 2 2006.201.21:29:35.46#ibcon#about to read 5, iclass 13, count 2 2006.201.21:29:35.46#ibcon#read 5, iclass 13, count 2 2006.201.21:29:35.46#ibcon#about to read 6, iclass 13, count 2 2006.201.21:29:35.46#ibcon#read 6, iclass 13, count 2 2006.201.21:29:35.46#ibcon#end of sib2, iclass 13, count 2 2006.201.21:29:35.46#ibcon#*after write, iclass 13, count 2 2006.201.21:29:35.46#ibcon#*before return 0, iclass 13, count 2 2006.201.21:29:35.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:35.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:35.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.21:29:35.46#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:35.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:35.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:35.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:35.58#ibcon#enter wrdev, iclass 13, count 0 2006.201.21:29:35.58#ibcon#first serial, iclass 13, count 0 2006.201.21:29:35.58#ibcon#enter sib2, iclass 13, count 0 2006.201.21:29:35.58#ibcon#flushed, iclass 13, count 0 2006.201.21:29:35.58#ibcon#about to write, iclass 13, count 0 2006.201.21:29:35.58#ibcon#wrote, iclass 13, count 0 2006.201.21:29:35.58#ibcon#about to read 3, iclass 13, count 0 2006.201.21:29:35.60#ibcon#read 3, iclass 13, count 0 2006.201.21:29:35.60#ibcon#about to read 4, iclass 13, count 0 2006.201.21:29:35.60#ibcon#read 4, iclass 13, count 0 2006.201.21:29:35.60#ibcon#about to read 5, iclass 13, count 0 2006.201.21:29:35.60#ibcon#read 5, iclass 13, count 0 2006.201.21:29:35.60#ibcon#about to read 6, iclass 13, count 0 2006.201.21:29:35.60#ibcon#read 6, iclass 13, count 0 2006.201.21:29:35.60#ibcon#end of sib2, iclass 13, count 0 2006.201.21:29:35.60#ibcon#*mode == 0, iclass 13, count 0 2006.201.21:29:35.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.21:29:35.60#ibcon#[25=USB\r\n] 2006.201.21:29:35.60#ibcon#*before write, iclass 13, count 0 2006.201.21:29:35.60#ibcon#enter sib2, iclass 13, count 0 2006.201.21:29:35.60#ibcon#flushed, iclass 13, count 0 2006.201.21:29:35.60#ibcon#about to write, iclass 13, count 0 2006.201.21:29:35.60#ibcon#wrote, iclass 13, count 0 2006.201.21:29:35.60#ibcon#about to read 3, iclass 13, count 0 2006.201.21:29:35.63#ibcon#read 3, iclass 13, count 0 2006.201.21:29:35.63#ibcon#about to read 4, iclass 13, count 0 2006.201.21:29:35.63#ibcon#read 4, iclass 13, count 0 2006.201.21:29:35.63#ibcon#about to read 5, iclass 13, count 0 2006.201.21:29:35.63#ibcon#read 5, iclass 13, count 0 2006.201.21:29:35.63#ibcon#about to read 6, iclass 13, count 0 2006.201.21:29:35.63#ibcon#read 6, iclass 13, count 0 2006.201.21:29:35.63#ibcon#end of sib2, iclass 13, count 0 2006.201.21:29:35.63#ibcon#*after write, iclass 13, count 0 2006.201.21:29:35.63#ibcon#*before return 0, iclass 13, count 0 2006.201.21:29:35.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:35.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:35.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.21:29:35.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.21:29:35.63$vck44/valo=6,814.99 2006.201.21:29:35.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.21:29:35.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.21:29:35.63#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:35.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:35.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:35.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:35.63#ibcon#enter wrdev, iclass 15, count 0 2006.201.21:29:35.63#ibcon#first serial, iclass 15, count 0 2006.201.21:29:35.63#ibcon#enter sib2, iclass 15, count 0 2006.201.21:29:35.63#ibcon#flushed, iclass 15, count 0 2006.201.21:29:35.63#ibcon#about to write, iclass 15, count 0 2006.201.21:29:35.63#ibcon#wrote, iclass 15, count 0 2006.201.21:29:35.63#ibcon#about to read 3, iclass 15, count 0 2006.201.21:29:35.65#ibcon#read 3, iclass 15, count 0 2006.201.21:29:35.65#ibcon#about to read 4, iclass 15, count 0 2006.201.21:29:35.65#ibcon#read 4, iclass 15, count 0 2006.201.21:29:35.65#ibcon#about to read 5, iclass 15, count 0 2006.201.21:29:35.65#ibcon#read 5, iclass 15, count 0 2006.201.21:29:35.65#ibcon#about to read 6, iclass 15, count 0 2006.201.21:29:35.65#ibcon#read 6, iclass 15, count 0 2006.201.21:29:35.65#ibcon#end of sib2, iclass 15, count 0 2006.201.21:29:35.65#ibcon#*mode == 0, iclass 15, count 0 2006.201.21:29:35.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.21:29:35.65#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.21:29:35.65#ibcon#*before write, iclass 15, count 0 2006.201.21:29:35.65#ibcon#enter sib2, iclass 15, count 0 2006.201.21:29:35.65#ibcon#flushed, iclass 15, count 0 2006.201.21:29:35.65#ibcon#about to write, iclass 15, count 0 2006.201.21:29:35.65#ibcon#wrote, iclass 15, count 0 2006.201.21:29:35.65#ibcon#about to read 3, iclass 15, count 0 2006.201.21:29:35.69#ibcon#read 3, iclass 15, count 0 2006.201.21:29:35.69#ibcon#about to read 4, iclass 15, count 0 2006.201.21:29:35.69#ibcon#read 4, iclass 15, count 0 2006.201.21:29:35.69#ibcon#about to read 5, iclass 15, count 0 2006.201.21:29:35.69#ibcon#read 5, iclass 15, count 0 2006.201.21:29:35.69#ibcon#about to read 6, iclass 15, count 0 2006.201.21:29:35.69#ibcon#read 6, iclass 15, count 0 2006.201.21:29:35.69#ibcon#end of sib2, iclass 15, count 0 2006.201.21:29:35.69#ibcon#*after write, iclass 15, count 0 2006.201.21:29:35.69#ibcon#*before return 0, iclass 15, count 0 2006.201.21:29:35.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:35.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:35.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.21:29:35.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.21:29:35.69$vck44/va=6,5 2006.201.21:29:35.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.21:29:35.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.21:29:35.69#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:35.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:35.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:35.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:35.75#ibcon#enter wrdev, iclass 17, count 2 2006.201.21:29:35.75#ibcon#first serial, iclass 17, count 2 2006.201.21:29:35.75#ibcon#enter sib2, iclass 17, count 2 2006.201.21:29:35.75#ibcon#flushed, iclass 17, count 2 2006.201.21:29:35.75#ibcon#about to write, iclass 17, count 2 2006.201.21:29:35.75#ibcon#wrote, iclass 17, count 2 2006.201.21:29:35.75#ibcon#about to read 3, iclass 17, count 2 2006.201.21:29:35.77#ibcon#read 3, iclass 17, count 2 2006.201.21:29:35.77#ibcon#about to read 4, iclass 17, count 2 2006.201.21:29:35.77#ibcon#read 4, iclass 17, count 2 2006.201.21:29:35.77#ibcon#about to read 5, iclass 17, count 2 2006.201.21:29:35.77#ibcon#read 5, iclass 17, count 2 2006.201.21:29:35.77#ibcon#about to read 6, iclass 17, count 2 2006.201.21:29:35.77#ibcon#read 6, iclass 17, count 2 2006.201.21:29:35.77#ibcon#end of sib2, iclass 17, count 2 2006.201.21:29:35.77#ibcon#*mode == 0, iclass 17, count 2 2006.201.21:29:35.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.21:29:35.77#ibcon#[25=AT06-05\r\n] 2006.201.21:29:35.77#ibcon#*before write, iclass 17, count 2 2006.201.21:29:35.77#ibcon#enter sib2, iclass 17, count 2 2006.201.21:29:35.77#ibcon#flushed, iclass 17, count 2 2006.201.21:29:35.77#ibcon#about to write, iclass 17, count 2 2006.201.21:29:35.77#ibcon#wrote, iclass 17, count 2 2006.201.21:29:35.77#ibcon#about to read 3, iclass 17, count 2 2006.201.21:29:35.80#ibcon#read 3, iclass 17, count 2 2006.201.21:29:35.80#ibcon#about to read 4, iclass 17, count 2 2006.201.21:29:35.80#ibcon#read 4, iclass 17, count 2 2006.201.21:29:35.80#ibcon#about to read 5, iclass 17, count 2 2006.201.21:29:35.80#ibcon#read 5, iclass 17, count 2 2006.201.21:29:35.80#ibcon#about to read 6, iclass 17, count 2 2006.201.21:29:35.80#ibcon#read 6, iclass 17, count 2 2006.201.21:29:35.80#ibcon#end of sib2, iclass 17, count 2 2006.201.21:29:35.80#ibcon#*after write, iclass 17, count 2 2006.201.21:29:35.80#ibcon#*before return 0, iclass 17, count 2 2006.201.21:29:35.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:35.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:35.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.21:29:35.80#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:35.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:35.83#abcon#<5=/04 1.8 3.0 20.041001002.1\r\n> 2006.201.21:29:35.85#abcon#{5=INTERFACE CLEAR} 2006.201.21:29:35.91#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:29:35.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:35.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:35.93#ibcon#enter wrdev, iclass 17, count 0 2006.201.21:29:35.93#ibcon#first serial, iclass 17, count 0 2006.201.21:29:35.93#ibcon#enter sib2, iclass 17, count 0 2006.201.21:29:35.93#ibcon#flushed, iclass 17, count 0 2006.201.21:29:35.93#ibcon#about to write, iclass 17, count 0 2006.201.21:29:35.93#ibcon#wrote, iclass 17, count 0 2006.201.21:29:35.93#ibcon#about to read 3, iclass 17, count 0 2006.201.21:29:35.96#ibcon#read 3, iclass 17, count 0 2006.201.21:29:35.96#ibcon#about to read 4, iclass 17, count 0 2006.201.21:29:35.96#ibcon#read 4, iclass 17, count 0 2006.201.21:29:35.96#ibcon#about to read 5, iclass 17, count 0 2006.201.21:29:35.96#ibcon#read 5, iclass 17, count 0 2006.201.21:29:35.96#ibcon#about to read 6, iclass 17, count 0 2006.201.21:29:35.96#ibcon#read 6, iclass 17, count 0 2006.201.21:29:35.96#ibcon#end of sib2, iclass 17, count 0 2006.201.21:29:35.96#ibcon#*mode == 0, iclass 17, count 0 2006.201.21:29:35.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.21:29:35.96#ibcon#[25=USB\r\n] 2006.201.21:29:35.96#ibcon#*before write, iclass 17, count 0 2006.201.21:29:35.96#ibcon#enter sib2, iclass 17, count 0 2006.201.21:29:35.96#ibcon#flushed, iclass 17, count 0 2006.201.21:29:35.96#ibcon#about to write, iclass 17, count 0 2006.201.21:29:35.96#ibcon#wrote, iclass 17, count 0 2006.201.21:29:35.96#ibcon#about to read 3, iclass 17, count 0 2006.201.21:29:35.99#ibcon#read 3, iclass 17, count 0 2006.201.21:29:35.99#ibcon#about to read 4, iclass 17, count 0 2006.201.21:29:35.99#ibcon#read 4, iclass 17, count 0 2006.201.21:29:35.99#ibcon#about to read 5, iclass 17, count 0 2006.201.21:29:35.99#ibcon#read 5, iclass 17, count 0 2006.201.21:29:35.99#ibcon#about to read 6, iclass 17, count 0 2006.201.21:29:35.99#ibcon#read 6, iclass 17, count 0 2006.201.21:29:35.99#ibcon#end of sib2, iclass 17, count 0 2006.201.21:29:35.99#ibcon#*after write, iclass 17, count 0 2006.201.21:29:35.99#ibcon#*before return 0, iclass 17, count 0 2006.201.21:29:35.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:35.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:35.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.21:29:35.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.21:29:35.99$vck44/valo=7,864.99 2006.201.21:29:35.99#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.21:29:35.99#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.21:29:35.99#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:35.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:35.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:35.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:35.99#ibcon#enter wrdev, iclass 23, count 0 2006.201.21:29:35.99#ibcon#first serial, iclass 23, count 0 2006.201.21:29:35.99#ibcon#enter sib2, iclass 23, count 0 2006.201.21:29:35.99#ibcon#flushed, iclass 23, count 0 2006.201.21:29:35.99#ibcon#about to write, iclass 23, count 0 2006.201.21:29:35.99#ibcon#wrote, iclass 23, count 0 2006.201.21:29:35.99#ibcon#about to read 3, iclass 23, count 0 2006.201.21:29:36.01#ibcon#read 3, iclass 23, count 0 2006.201.21:29:36.01#ibcon#about to read 4, iclass 23, count 0 2006.201.21:29:36.01#ibcon#read 4, iclass 23, count 0 2006.201.21:29:36.01#ibcon#about to read 5, iclass 23, count 0 2006.201.21:29:36.01#ibcon#read 5, iclass 23, count 0 2006.201.21:29:36.01#ibcon#about to read 6, iclass 23, count 0 2006.201.21:29:36.01#ibcon#read 6, iclass 23, count 0 2006.201.21:29:36.01#ibcon#end of sib2, iclass 23, count 0 2006.201.21:29:36.01#ibcon#*mode == 0, iclass 23, count 0 2006.201.21:29:36.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.21:29:36.01#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.21:29:36.01#ibcon#*before write, iclass 23, count 0 2006.201.21:29:36.01#ibcon#enter sib2, iclass 23, count 0 2006.201.21:29:36.01#ibcon#flushed, iclass 23, count 0 2006.201.21:29:36.01#ibcon#about to write, iclass 23, count 0 2006.201.21:29:36.01#ibcon#wrote, iclass 23, count 0 2006.201.21:29:36.01#ibcon#about to read 3, iclass 23, count 0 2006.201.21:29:36.05#ibcon#read 3, iclass 23, count 0 2006.201.21:29:36.05#ibcon#about to read 4, iclass 23, count 0 2006.201.21:29:36.05#ibcon#read 4, iclass 23, count 0 2006.201.21:29:36.05#ibcon#about to read 5, iclass 23, count 0 2006.201.21:29:36.05#ibcon#read 5, iclass 23, count 0 2006.201.21:29:36.05#ibcon#about to read 6, iclass 23, count 0 2006.201.21:29:36.05#ibcon#read 6, iclass 23, count 0 2006.201.21:29:36.05#ibcon#end of sib2, iclass 23, count 0 2006.201.21:29:36.05#ibcon#*after write, iclass 23, count 0 2006.201.21:29:36.05#ibcon#*before return 0, iclass 23, count 0 2006.201.21:29:36.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:36.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:36.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.21:29:36.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.21:29:36.05$vck44/va=7,5 2006.201.21:29:36.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.21:29:36.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.21:29:36.05#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:36.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:36.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:36.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:36.11#ibcon#enter wrdev, iclass 25, count 2 2006.201.21:29:36.11#ibcon#first serial, iclass 25, count 2 2006.201.21:29:36.11#ibcon#enter sib2, iclass 25, count 2 2006.201.21:29:36.11#ibcon#flushed, iclass 25, count 2 2006.201.21:29:36.11#ibcon#about to write, iclass 25, count 2 2006.201.21:29:36.11#ibcon#wrote, iclass 25, count 2 2006.201.21:29:36.11#ibcon#about to read 3, iclass 25, count 2 2006.201.21:29:36.13#ibcon#read 3, iclass 25, count 2 2006.201.21:29:36.13#ibcon#about to read 4, iclass 25, count 2 2006.201.21:29:36.13#ibcon#read 4, iclass 25, count 2 2006.201.21:29:36.13#ibcon#about to read 5, iclass 25, count 2 2006.201.21:29:36.13#ibcon#read 5, iclass 25, count 2 2006.201.21:29:36.13#ibcon#about to read 6, iclass 25, count 2 2006.201.21:29:36.13#ibcon#read 6, iclass 25, count 2 2006.201.21:29:36.13#ibcon#end of sib2, iclass 25, count 2 2006.201.21:29:36.13#ibcon#*mode == 0, iclass 25, count 2 2006.201.21:29:36.13#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.21:29:36.13#ibcon#[25=AT07-05\r\n] 2006.201.21:29:36.13#ibcon#*before write, iclass 25, count 2 2006.201.21:29:36.13#ibcon#enter sib2, iclass 25, count 2 2006.201.21:29:36.13#ibcon#flushed, iclass 25, count 2 2006.201.21:29:36.13#ibcon#about to write, iclass 25, count 2 2006.201.21:29:36.13#ibcon#wrote, iclass 25, count 2 2006.201.21:29:36.13#ibcon#about to read 3, iclass 25, count 2 2006.201.21:29:36.16#ibcon#read 3, iclass 25, count 2 2006.201.21:29:36.16#ibcon#about to read 4, iclass 25, count 2 2006.201.21:29:36.16#ibcon#read 4, iclass 25, count 2 2006.201.21:29:36.16#ibcon#about to read 5, iclass 25, count 2 2006.201.21:29:36.16#ibcon#read 5, iclass 25, count 2 2006.201.21:29:36.16#ibcon#about to read 6, iclass 25, count 2 2006.201.21:29:36.16#ibcon#read 6, iclass 25, count 2 2006.201.21:29:36.16#ibcon#end of sib2, iclass 25, count 2 2006.201.21:29:36.16#ibcon#*after write, iclass 25, count 2 2006.201.21:29:36.16#ibcon#*before return 0, iclass 25, count 2 2006.201.21:29:36.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:36.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:36.16#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.21:29:36.16#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:36.16#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:36.28#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:36.28#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:36.28#ibcon#enter wrdev, iclass 25, count 0 2006.201.21:29:36.28#ibcon#first serial, iclass 25, count 0 2006.201.21:29:36.28#ibcon#enter sib2, iclass 25, count 0 2006.201.21:29:36.28#ibcon#flushed, iclass 25, count 0 2006.201.21:29:36.28#ibcon#about to write, iclass 25, count 0 2006.201.21:29:36.28#ibcon#wrote, iclass 25, count 0 2006.201.21:29:36.28#ibcon#about to read 3, iclass 25, count 0 2006.201.21:29:36.30#ibcon#read 3, iclass 25, count 0 2006.201.21:29:36.30#ibcon#about to read 4, iclass 25, count 0 2006.201.21:29:36.30#ibcon#read 4, iclass 25, count 0 2006.201.21:29:36.30#ibcon#about to read 5, iclass 25, count 0 2006.201.21:29:36.30#ibcon#read 5, iclass 25, count 0 2006.201.21:29:36.30#ibcon#about to read 6, iclass 25, count 0 2006.201.21:29:36.30#ibcon#read 6, iclass 25, count 0 2006.201.21:29:36.30#ibcon#end of sib2, iclass 25, count 0 2006.201.21:29:36.30#ibcon#*mode == 0, iclass 25, count 0 2006.201.21:29:36.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.21:29:36.30#ibcon#[25=USB\r\n] 2006.201.21:29:36.30#ibcon#*before write, iclass 25, count 0 2006.201.21:29:36.30#ibcon#enter sib2, iclass 25, count 0 2006.201.21:29:36.30#ibcon#flushed, iclass 25, count 0 2006.201.21:29:36.30#ibcon#about to write, iclass 25, count 0 2006.201.21:29:36.30#ibcon#wrote, iclass 25, count 0 2006.201.21:29:36.30#ibcon#about to read 3, iclass 25, count 0 2006.201.21:29:36.33#ibcon#read 3, iclass 25, count 0 2006.201.21:29:36.33#ibcon#about to read 4, iclass 25, count 0 2006.201.21:29:36.33#ibcon#read 4, iclass 25, count 0 2006.201.21:29:36.33#ibcon#about to read 5, iclass 25, count 0 2006.201.21:29:36.33#ibcon#read 5, iclass 25, count 0 2006.201.21:29:36.33#ibcon#about to read 6, iclass 25, count 0 2006.201.21:29:36.33#ibcon#read 6, iclass 25, count 0 2006.201.21:29:36.33#ibcon#end of sib2, iclass 25, count 0 2006.201.21:29:36.33#ibcon#*after write, iclass 25, count 0 2006.201.21:29:36.33#ibcon#*before return 0, iclass 25, count 0 2006.201.21:29:36.33#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:36.33#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:36.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.21:29:36.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.21:29:36.33$vck44/valo=8,884.99 2006.201.21:29:36.33#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.21:29:36.33#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.21:29:36.33#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:36.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:36.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:36.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:36.33#ibcon#enter wrdev, iclass 27, count 0 2006.201.21:29:36.33#ibcon#first serial, iclass 27, count 0 2006.201.21:29:36.33#ibcon#enter sib2, iclass 27, count 0 2006.201.21:29:36.33#ibcon#flushed, iclass 27, count 0 2006.201.21:29:36.33#ibcon#about to write, iclass 27, count 0 2006.201.21:29:36.33#ibcon#wrote, iclass 27, count 0 2006.201.21:29:36.33#ibcon#about to read 3, iclass 27, count 0 2006.201.21:29:36.35#ibcon#read 3, iclass 27, count 0 2006.201.21:29:36.35#ibcon#about to read 4, iclass 27, count 0 2006.201.21:29:36.35#ibcon#read 4, iclass 27, count 0 2006.201.21:29:36.35#ibcon#about to read 5, iclass 27, count 0 2006.201.21:29:36.35#ibcon#read 5, iclass 27, count 0 2006.201.21:29:36.35#ibcon#about to read 6, iclass 27, count 0 2006.201.21:29:36.35#ibcon#read 6, iclass 27, count 0 2006.201.21:29:36.35#ibcon#end of sib2, iclass 27, count 0 2006.201.21:29:36.35#ibcon#*mode == 0, iclass 27, count 0 2006.201.21:29:36.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.21:29:36.35#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.21:29:36.35#ibcon#*before write, iclass 27, count 0 2006.201.21:29:36.35#ibcon#enter sib2, iclass 27, count 0 2006.201.21:29:36.35#ibcon#flushed, iclass 27, count 0 2006.201.21:29:36.35#ibcon#about to write, iclass 27, count 0 2006.201.21:29:36.35#ibcon#wrote, iclass 27, count 0 2006.201.21:29:36.35#ibcon#about to read 3, iclass 27, count 0 2006.201.21:29:36.39#ibcon#read 3, iclass 27, count 0 2006.201.21:29:36.39#ibcon#about to read 4, iclass 27, count 0 2006.201.21:29:36.39#ibcon#read 4, iclass 27, count 0 2006.201.21:29:36.39#ibcon#about to read 5, iclass 27, count 0 2006.201.21:29:36.39#ibcon#read 5, iclass 27, count 0 2006.201.21:29:36.39#ibcon#about to read 6, iclass 27, count 0 2006.201.21:29:36.39#ibcon#read 6, iclass 27, count 0 2006.201.21:29:36.39#ibcon#end of sib2, iclass 27, count 0 2006.201.21:29:36.39#ibcon#*after write, iclass 27, count 0 2006.201.21:29:36.39#ibcon#*before return 0, iclass 27, count 0 2006.201.21:29:36.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:36.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:36.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.21:29:36.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.21:29:36.39$vck44/va=8,4 2006.201.21:29:36.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.21:29:36.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.21:29:36.39#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:36.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.21:29:36.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.21:29:36.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.21:29:36.45#ibcon#enter wrdev, iclass 29, count 2 2006.201.21:29:36.45#ibcon#first serial, iclass 29, count 2 2006.201.21:29:36.45#ibcon#enter sib2, iclass 29, count 2 2006.201.21:29:36.45#ibcon#flushed, iclass 29, count 2 2006.201.21:29:36.45#ibcon#about to write, iclass 29, count 2 2006.201.21:29:36.45#ibcon#wrote, iclass 29, count 2 2006.201.21:29:36.45#ibcon#about to read 3, iclass 29, count 2 2006.201.21:29:36.47#ibcon#read 3, iclass 29, count 2 2006.201.21:29:36.47#ibcon#about to read 4, iclass 29, count 2 2006.201.21:29:36.47#ibcon#read 4, iclass 29, count 2 2006.201.21:29:36.47#ibcon#about to read 5, iclass 29, count 2 2006.201.21:29:36.47#ibcon#read 5, iclass 29, count 2 2006.201.21:29:36.47#ibcon#about to read 6, iclass 29, count 2 2006.201.21:29:36.47#ibcon#read 6, iclass 29, count 2 2006.201.21:29:36.47#ibcon#end of sib2, iclass 29, count 2 2006.201.21:29:36.47#ibcon#*mode == 0, iclass 29, count 2 2006.201.21:29:36.47#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.21:29:36.47#ibcon#[25=AT08-04\r\n] 2006.201.21:29:36.47#ibcon#*before write, iclass 29, count 2 2006.201.21:29:36.47#ibcon#enter sib2, iclass 29, count 2 2006.201.21:29:36.47#ibcon#flushed, iclass 29, count 2 2006.201.21:29:36.47#ibcon#about to write, iclass 29, count 2 2006.201.21:29:36.47#ibcon#wrote, iclass 29, count 2 2006.201.21:29:36.47#ibcon#about to read 3, iclass 29, count 2 2006.201.21:29:36.50#ibcon#read 3, iclass 29, count 2 2006.201.21:29:36.50#ibcon#about to read 4, iclass 29, count 2 2006.201.21:29:36.50#ibcon#read 4, iclass 29, count 2 2006.201.21:29:36.50#ibcon#about to read 5, iclass 29, count 2 2006.201.21:29:36.50#ibcon#read 5, iclass 29, count 2 2006.201.21:29:36.50#ibcon#about to read 6, iclass 29, count 2 2006.201.21:29:36.50#ibcon#read 6, iclass 29, count 2 2006.201.21:29:36.50#ibcon#end of sib2, iclass 29, count 2 2006.201.21:29:36.50#ibcon#*after write, iclass 29, count 2 2006.201.21:29:36.50#ibcon#*before return 0, iclass 29, count 2 2006.201.21:29:36.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.21:29:36.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.21:29:36.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.21:29:36.50#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:36.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.21:29:36.62#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.21:29:36.62#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.21:29:36.62#ibcon#enter wrdev, iclass 29, count 0 2006.201.21:29:36.62#ibcon#first serial, iclass 29, count 0 2006.201.21:29:36.62#ibcon#enter sib2, iclass 29, count 0 2006.201.21:29:36.62#ibcon#flushed, iclass 29, count 0 2006.201.21:29:36.62#ibcon#about to write, iclass 29, count 0 2006.201.21:29:36.62#ibcon#wrote, iclass 29, count 0 2006.201.21:29:36.62#ibcon#about to read 3, iclass 29, count 0 2006.201.21:29:36.64#ibcon#read 3, iclass 29, count 0 2006.201.21:29:36.64#ibcon#about to read 4, iclass 29, count 0 2006.201.21:29:36.64#ibcon#read 4, iclass 29, count 0 2006.201.21:29:36.64#ibcon#about to read 5, iclass 29, count 0 2006.201.21:29:36.64#ibcon#read 5, iclass 29, count 0 2006.201.21:29:36.64#ibcon#about to read 6, iclass 29, count 0 2006.201.21:29:36.64#ibcon#read 6, iclass 29, count 0 2006.201.21:29:36.64#ibcon#end of sib2, iclass 29, count 0 2006.201.21:29:36.64#ibcon#*mode == 0, iclass 29, count 0 2006.201.21:29:36.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.21:29:36.64#ibcon#[25=USB\r\n] 2006.201.21:29:36.64#ibcon#*before write, iclass 29, count 0 2006.201.21:29:36.64#ibcon#enter sib2, iclass 29, count 0 2006.201.21:29:36.64#ibcon#flushed, iclass 29, count 0 2006.201.21:29:36.64#ibcon#about to write, iclass 29, count 0 2006.201.21:29:36.64#ibcon#wrote, iclass 29, count 0 2006.201.21:29:36.64#ibcon#about to read 3, iclass 29, count 0 2006.201.21:29:36.67#ibcon#read 3, iclass 29, count 0 2006.201.21:29:36.67#ibcon#about to read 4, iclass 29, count 0 2006.201.21:29:36.67#ibcon#read 4, iclass 29, count 0 2006.201.21:29:36.67#ibcon#about to read 5, iclass 29, count 0 2006.201.21:29:36.67#ibcon#read 5, iclass 29, count 0 2006.201.21:29:36.67#ibcon#about to read 6, iclass 29, count 0 2006.201.21:29:36.67#ibcon#read 6, iclass 29, count 0 2006.201.21:29:36.67#ibcon#end of sib2, iclass 29, count 0 2006.201.21:29:36.67#ibcon#*after write, iclass 29, count 0 2006.201.21:29:36.67#ibcon#*before return 0, iclass 29, count 0 2006.201.21:29:36.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.21:29:36.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.21:29:36.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.21:29:36.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.21:29:36.67$vck44/vblo=1,629.99 2006.201.21:29:36.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.21:29:36.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.21:29:36.67#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:36.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:36.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:36.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:36.67#ibcon#enter wrdev, iclass 31, count 0 2006.201.21:29:36.67#ibcon#first serial, iclass 31, count 0 2006.201.21:29:36.67#ibcon#enter sib2, iclass 31, count 0 2006.201.21:29:36.67#ibcon#flushed, iclass 31, count 0 2006.201.21:29:36.67#ibcon#about to write, iclass 31, count 0 2006.201.21:29:36.67#ibcon#wrote, iclass 31, count 0 2006.201.21:29:36.67#ibcon#about to read 3, iclass 31, count 0 2006.201.21:29:36.69#ibcon#read 3, iclass 31, count 0 2006.201.21:29:36.69#ibcon#about to read 4, iclass 31, count 0 2006.201.21:29:36.69#ibcon#read 4, iclass 31, count 0 2006.201.21:29:36.69#ibcon#about to read 5, iclass 31, count 0 2006.201.21:29:36.69#ibcon#read 5, iclass 31, count 0 2006.201.21:29:36.69#ibcon#about to read 6, iclass 31, count 0 2006.201.21:29:36.69#ibcon#read 6, iclass 31, count 0 2006.201.21:29:36.69#ibcon#end of sib2, iclass 31, count 0 2006.201.21:29:36.69#ibcon#*mode == 0, iclass 31, count 0 2006.201.21:29:36.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.21:29:36.69#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.21:29:36.69#ibcon#*before write, iclass 31, count 0 2006.201.21:29:36.69#ibcon#enter sib2, iclass 31, count 0 2006.201.21:29:36.69#ibcon#flushed, iclass 31, count 0 2006.201.21:29:36.69#ibcon#about to write, iclass 31, count 0 2006.201.21:29:36.69#ibcon#wrote, iclass 31, count 0 2006.201.21:29:36.69#ibcon#about to read 3, iclass 31, count 0 2006.201.21:29:36.74#ibcon#read 3, iclass 31, count 0 2006.201.21:29:36.74#ibcon#about to read 4, iclass 31, count 0 2006.201.21:29:36.74#ibcon#read 4, iclass 31, count 0 2006.201.21:29:36.74#ibcon#about to read 5, iclass 31, count 0 2006.201.21:29:36.74#ibcon#read 5, iclass 31, count 0 2006.201.21:29:36.74#ibcon#about to read 6, iclass 31, count 0 2006.201.21:29:36.74#ibcon#read 6, iclass 31, count 0 2006.201.21:29:36.74#ibcon#end of sib2, iclass 31, count 0 2006.201.21:29:36.74#ibcon#*after write, iclass 31, count 0 2006.201.21:29:36.74#ibcon#*before return 0, iclass 31, count 0 2006.201.21:29:36.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:36.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.21:29:36.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.21:29:36.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.21:29:36.74$vck44/vb=1,4 2006.201.21:29:36.74#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.21:29:36.74#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.21:29:36.74#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:36.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:36.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:36.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:36.74#ibcon#enter wrdev, iclass 33, count 2 2006.201.21:29:36.74#ibcon#first serial, iclass 33, count 2 2006.201.21:29:36.74#ibcon#enter sib2, iclass 33, count 2 2006.201.21:29:36.74#ibcon#flushed, iclass 33, count 2 2006.201.21:29:36.74#ibcon#about to write, iclass 33, count 2 2006.201.21:29:36.74#ibcon#wrote, iclass 33, count 2 2006.201.21:29:36.74#ibcon#about to read 3, iclass 33, count 2 2006.201.21:29:36.76#ibcon#read 3, iclass 33, count 2 2006.201.21:29:36.76#ibcon#about to read 4, iclass 33, count 2 2006.201.21:29:36.76#ibcon#read 4, iclass 33, count 2 2006.201.21:29:36.76#ibcon#about to read 5, iclass 33, count 2 2006.201.21:29:36.76#ibcon#read 5, iclass 33, count 2 2006.201.21:29:36.76#ibcon#about to read 6, iclass 33, count 2 2006.201.21:29:36.76#ibcon#read 6, iclass 33, count 2 2006.201.21:29:36.76#ibcon#end of sib2, iclass 33, count 2 2006.201.21:29:36.76#ibcon#*mode == 0, iclass 33, count 2 2006.201.21:29:36.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.21:29:36.76#ibcon#[27=AT01-04\r\n] 2006.201.21:29:36.76#ibcon#*before write, iclass 33, count 2 2006.201.21:29:36.76#ibcon#enter sib2, iclass 33, count 2 2006.201.21:29:36.76#ibcon#flushed, iclass 33, count 2 2006.201.21:29:36.76#ibcon#about to write, iclass 33, count 2 2006.201.21:29:36.76#ibcon#wrote, iclass 33, count 2 2006.201.21:29:36.76#ibcon#about to read 3, iclass 33, count 2 2006.201.21:29:36.79#ibcon#read 3, iclass 33, count 2 2006.201.21:29:36.79#ibcon#about to read 4, iclass 33, count 2 2006.201.21:29:36.79#ibcon#read 4, iclass 33, count 2 2006.201.21:29:36.79#ibcon#about to read 5, iclass 33, count 2 2006.201.21:29:36.79#ibcon#read 5, iclass 33, count 2 2006.201.21:29:36.79#ibcon#about to read 6, iclass 33, count 2 2006.201.21:29:36.79#ibcon#read 6, iclass 33, count 2 2006.201.21:29:36.79#ibcon#end of sib2, iclass 33, count 2 2006.201.21:29:36.79#ibcon#*after write, iclass 33, count 2 2006.201.21:29:36.79#ibcon#*before return 0, iclass 33, count 2 2006.201.21:29:36.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:36.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.21:29:36.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.21:29:36.79#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:36.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:36.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:36.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:36.91#ibcon#enter wrdev, iclass 33, count 0 2006.201.21:29:36.91#ibcon#first serial, iclass 33, count 0 2006.201.21:29:36.91#ibcon#enter sib2, iclass 33, count 0 2006.201.21:29:36.91#ibcon#flushed, iclass 33, count 0 2006.201.21:29:36.91#ibcon#about to write, iclass 33, count 0 2006.201.21:29:36.91#ibcon#wrote, iclass 33, count 0 2006.201.21:29:36.91#ibcon#about to read 3, iclass 33, count 0 2006.201.21:29:36.93#ibcon#read 3, iclass 33, count 0 2006.201.21:29:36.93#ibcon#about to read 4, iclass 33, count 0 2006.201.21:29:36.93#ibcon#read 4, iclass 33, count 0 2006.201.21:29:36.93#ibcon#about to read 5, iclass 33, count 0 2006.201.21:29:36.93#ibcon#read 5, iclass 33, count 0 2006.201.21:29:36.93#ibcon#about to read 6, iclass 33, count 0 2006.201.21:29:36.93#ibcon#read 6, iclass 33, count 0 2006.201.21:29:36.93#ibcon#end of sib2, iclass 33, count 0 2006.201.21:29:36.93#ibcon#*mode == 0, iclass 33, count 0 2006.201.21:29:36.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.21:29:36.93#ibcon#[27=USB\r\n] 2006.201.21:29:36.93#ibcon#*before write, iclass 33, count 0 2006.201.21:29:36.93#ibcon#enter sib2, iclass 33, count 0 2006.201.21:29:36.93#ibcon#flushed, iclass 33, count 0 2006.201.21:29:36.93#ibcon#about to write, iclass 33, count 0 2006.201.21:29:36.93#ibcon#wrote, iclass 33, count 0 2006.201.21:29:36.93#ibcon#about to read 3, iclass 33, count 0 2006.201.21:29:36.96#ibcon#read 3, iclass 33, count 0 2006.201.21:29:36.96#ibcon#about to read 4, iclass 33, count 0 2006.201.21:29:36.96#ibcon#read 4, iclass 33, count 0 2006.201.21:29:36.96#ibcon#about to read 5, iclass 33, count 0 2006.201.21:29:36.96#ibcon#read 5, iclass 33, count 0 2006.201.21:29:36.96#ibcon#about to read 6, iclass 33, count 0 2006.201.21:29:36.96#ibcon#read 6, iclass 33, count 0 2006.201.21:29:36.96#ibcon#end of sib2, iclass 33, count 0 2006.201.21:29:36.96#ibcon#*after write, iclass 33, count 0 2006.201.21:29:36.96#ibcon#*before return 0, iclass 33, count 0 2006.201.21:29:36.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:36.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.21:29:36.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.21:29:36.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.21:29:36.96$vck44/vblo=2,634.99 2006.201.21:29:36.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.21:29:36.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.21:29:36.96#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:36.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:36.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:36.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:36.96#ibcon#enter wrdev, iclass 35, count 0 2006.201.21:29:36.96#ibcon#first serial, iclass 35, count 0 2006.201.21:29:36.96#ibcon#enter sib2, iclass 35, count 0 2006.201.21:29:36.96#ibcon#flushed, iclass 35, count 0 2006.201.21:29:36.96#ibcon#about to write, iclass 35, count 0 2006.201.21:29:36.96#ibcon#wrote, iclass 35, count 0 2006.201.21:29:36.96#ibcon#about to read 3, iclass 35, count 0 2006.201.21:29:36.98#ibcon#read 3, iclass 35, count 0 2006.201.21:29:36.98#ibcon#about to read 4, iclass 35, count 0 2006.201.21:29:36.98#ibcon#read 4, iclass 35, count 0 2006.201.21:29:36.98#ibcon#about to read 5, iclass 35, count 0 2006.201.21:29:36.98#ibcon#read 5, iclass 35, count 0 2006.201.21:29:36.98#ibcon#about to read 6, iclass 35, count 0 2006.201.21:29:36.98#ibcon#read 6, iclass 35, count 0 2006.201.21:29:36.98#ibcon#end of sib2, iclass 35, count 0 2006.201.21:29:36.98#ibcon#*mode == 0, iclass 35, count 0 2006.201.21:29:36.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.21:29:36.98#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.21:29:36.98#ibcon#*before write, iclass 35, count 0 2006.201.21:29:36.98#ibcon#enter sib2, iclass 35, count 0 2006.201.21:29:36.98#ibcon#flushed, iclass 35, count 0 2006.201.21:29:36.98#ibcon#about to write, iclass 35, count 0 2006.201.21:29:36.98#ibcon#wrote, iclass 35, count 0 2006.201.21:29:36.98#ibcon#about to read 3, iclass 35, count 0 2006.201.21:29:37.02#ibcon#read 3, iclass 35, count 0 2006.201.21:29:37.02#ibcon#about to read 4, iclass 35, count 0 2006.201.21:29:37.02#ibcon#read 4, iclass 35, count 0 2006.201.21:29:37.02#ibcon#about to read 5, iclass 35, count 0 2006.201.21:29:37.02#ibcon#read 5, iclass 35, count 0 2006.201.21:29:37.02#ibcon#about to read 6, iclass 35, count 0 2006.201.21:29:37.02#ibcon#read 6, iclass 35, count 0 2006.201.21:29:37.02#ibcon#end of sib2, iclass 35, count 0 2006.201.21:29:37.02#ibcon#*after write, iclass 35, count 0 2006.201.21:29:37.02#ibcon#*before return 0, iclass 35, count 0 2006.201.21:29:37.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:37.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.21:29:37.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.21:29:37.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.21:29:37.02$vck44/vb=2,5 2006.201.21:29:37.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.21:29:37.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.21:29:37.02#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:37.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:37.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:37.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:37.08#ibcon#enter wrdev, iclass 37, count 2 2006.201.21:29:37.08#ibcon#first serial, iclass 37, count 2 2006.201.21:29:37.08#ibcon#enter sib2, iclass 37, count 2 2006.201.21:29:37.08#ibcon#flushed, iclass 37, count 2 2006.201.21:29:37.08#ibcon#about to write, iclass 37, count 2 2006.201.21:29:37.08#ibcon#wrote, iclass 37, count 2 2006.201.21:29:37.08#ibcon#about to read 3, iclass 37, count 2 2006.201.21:29:37.10#ibcon#read 3, iclass 37, count 2 2006.201.21:29:37.10#ibcon#about to read 4, iclass 37, count 2 2006.201.21:29:37.10#ibcon#read 4, iclass 37, count 2 2006.201.21:29:37.10#ibcon#about to read 5, iclass 37, count 2 2006.201.21:29:37.10#ibcon#read 5, iclass 37, count 2 2006.201.21:29:37.10#ibcon#about to read 6, iclass 37, count 2 2006.201.21:29:37.10#ibcon#read 6, iclass 37, count 2 2006.201.21:29:37.10#ibcon#end of sib2, iclass 37, count 2 2006.201.21:29:37.10#ibcon#*mode == 0, iclass 37, count 2 2006.201.21:29:37.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.21:29:37.10#ibcon#[27=AT02-05\r\n] 2006.201.21:29:37.10#ibcon#*before write, iclass 37, count 2 2006.201.21:29:37.10#ibcon#enter sib2, iclass 37, count 2 2006.201.21:29:37.10#ibcon#flushed, iclass 37, count 2 2006.201.21:29:37.10#ibcon#about to write, iclass 37, count 2 2006.201.21:29:37.10#ibcon#wrote, iclass 37, count 2 2006.201.21:29:37.10#ibcon#about to read 3, iclass 37, count 2 2006.201.21:29:37.13#ibcon#read 3, iclass 37, count 2 2006.201.21:29:37.13#ibcon#about to read 4, iclass 37, count 2 2006.201.21:29:37.13#ibcon#read 4, iclass 37, count 2 2006.201.21:29:37.13#ibcon#about to read 5, iclass 37, count 2 2006.201.21:29:37.13#ibcon#read 5, iclass 37, count 2 2006.201.21:29:37.13#ibcon#about to read 6, iclass 37, count 2 2006.201.21:29:37.13#ibcon#read 6, iclass 37, count 2 2006.201.21:29:37.13#ibcon#end of sib2, iclass 37, count 2 2006.201.21:29:37.13#ibcon#*after write, iclass 37, count 2 2006.201.21:29:37.13#ibcon#*before return 0, iclass 37, count 2 2006.201.21:29:37.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:37.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.21:29:37.13#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.21:29:37.13#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:37.13#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:37.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:37.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:37.25#ibcon#enter wrdev, iclass 37, count 0 2006.201.21:29:37.25#ibcon#first serial, iclass 37, count 0 2006.201.21:29:37.25#ibcon#enter sib2, iclass 37, count 0 2006.201.21:29:37.25#ibcon#flushed, iclass 37, count 0 2006.201.21:29:37.25#ibcon#about to write, iclass 37, count 0 2006.201.21:29:37.25#ibcon#wrote, iclass 37, count 0 2006.201.21:29:37.25#ibcon#about to read 3, iclass 37, count 0 2006.201.21:29:37.27#ibcon#read 3, iclass 37, count 0 2006.201.21:29:37.27#ibcon#about to read 4, iclass 37, count 0 2006.201.21:29:37.27#ibcon#read 4, iclass 37, count 0 2006.201.21:29:37.27#ibcon#about to read 5, iclass 37, count 0 2006.201.21:29:37.27#ibcon#read 5, iclass 37, count 0 2006.201.21:29:37.27#ibcon#about to read 6, iclass 37, count 0 2006.201.21:29:37.27#ibcon#read 6, iclass 37, count 0 2006.201.21:29:37.27#ibcon#end of sib2, iclass 37, count 0 2006.201.21:29:37.27#ibcon#*mode == 0, iclass 37, count 0 2006.201.21:29:37.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.21:29:37.27#ibcon#[27=USB\r\n] 2006.201.21:29:37.27#ibcon#*before write, iclass 37, count 0 2006.201.21:29:37.27#ibcon#enter sib2, iclass 37, count 0 2006.201.21:29:37.27#ibcon#flushed, iclass 37, count 0 2006.201.21:29:37.27#ibcon#about to write, iclass 37, count 0 2006.201.21:29:37.27#ibcon#wrote, iclass 37, count 0 2006.201.21:29:37.27#ibcon#about to read 3, iclass 37, count 0 2006.201.21:29:37.30#ibcon#read 3, iclass 37, count 0 2006.201.21:29:37.30#ibcon#about to read 4, iclass 37, count 0 2006.201.21:29:37.30#ibcon#read 4, iclass 37, count 0 2006.201.21:29:37.30#ibcon#about to read 5, iclass 37, count 0 2006.201.21:29:37.30#ibcon#read 5, iclass 37, count 0 2006.201.21:29:37.30#ibcon#about to read 6, iclass 37, count 0 2006.201.21:29:37.30#ibcon#read 6, iclass 37, count 0 2006.201.21:29:37.30#ibcon#end of sib2, iclass 37, count 0 2006.201.21:29:37.30#ibcon#*after write, iclass 37, count 0 2006.201.21:29:37.30#ibcon#*before return 0, iclass 37, count 0 2006.201.21:29:37.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:37.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.21:29:37.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.21:29:37.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.21:29:37.30$vck44/vblo=3,649.99 2006.201.21:29:37.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.21:29:37.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.21:29:37.30#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:37.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:37.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:37.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:37.30#ibcon#enter wrdev, iclass 39, count 0 2006.201.21:29:37.30#ibcon#first serial, iclass 39, count 0 2006.201.21:29:37.30#ibcon#enter sib2, iclass 39, count 0 2006.201.21:29:37.30#ibcon#flushed, iclass 39, count 0 2006.201.21:29:37.30#ibcon#about to write, iclass 39, count 0 2006.201.21:29:37.30#ibcon#wrote, iclass 39, count 0 2006.201.21:29:37.30#ibcon#about to read 3, iclass 39, count 0 2006.201.21:29:37.32#ibcon#read 3, iclass 39, count 0 2006.201.21:29:37.32#ibcon#about to read 4, iclass 39, count 0 2006.201.21:29:37.32#ibcon#read 4, iclass 39, count 0 2006.201.21:29:37.32#ibcon#about to read 5, iclass 39, count 0 2006.201.21:29:37.32#ibcon#read 5, iclass 39, count 0 2006.201.21:29:37.32#ibcon#about to read 6, iclass 39, count 0 2006.201.21:29:37.32#ibcon#read 6, iclass 39, count 0 2006.201.21:29:37.32#ibcon#end of sib2, iclass 39, count 0 2006.201.21:29:37.32#ibcon#*mode == 0, iclass 39, count 0 2006.201.21:29:37.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.21:29:37.32#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.21:29:37.32#ibcon#*before write, iclass 39, count 0 2006.201.21:29:37.32#ibcon#enter sib2, iclass 39, count 0 2006.201.21:29:37.32#ibcon#flushed, iclass 39, count 0 2006.201.21:29:37.32#ibcon#about to write, iclass 39, count 0 2006.201.21:29:37.32#ibcon#wrote, iclass 39, count 0 2006.201.21:29:37.32#ibcon#about to read 3, iclass 39, count 0 2006.201.21:29:37.37#ibcon#read 3, iclass 39, count 0 2006.201.21:29:37.37#ibcon#about to read 4, iclass 39, count 0 2006.201.21:29:37.37#ibcon#read 4, iclass 39, count 0 2006.201.21:29:37.37#ibcon#about to read 5, iclass 39, count 0 2006.201.21:29:37.37#ibcon#read 5, iclass 39, count 0 2006.201.21:29:37.37#ibcon#about to read 6, iclass 39, count 0 2006.201.21:29:37.37#ibcon#read 6, iclass 39, count 0 2006.201.21:29:37.37#ibcon#end of sib2, iclass 39, count 0 2006.201.21:29:37.37#ibcon#*after write, iclass 39, count 0 2006.201.21:29:37.37#ibcon#*before return 0, iclass 39, count 0 2006.201.21:29:37.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:37.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.21:29:37.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.21:29:37.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.21:29:37.37$vck44/vb=3,4 2006.201.21:29:37.37#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.21:29:37.37#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.21:29:37.37#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:37.37#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:37.42#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:37.42#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:37.42#ibcon#enter wrdev, iclass 2, count 2 2006.201.21:29:37.42#ibcon#first serial, iclass 2, count 2 2006.201.21:29:37.42#ibcon#enter sib2, iclass 2, count 2 2006.201.21:29:37.42#ibcon#flushed, iclass 2, count 2 2006.201.21:29:37.42#ibcon#about to write, iclass 2, count 2 2006.201.21:29:37.42#ibcon#wrote, iclass 2, count 2 2006.201.21:29:37.42#ibcon#about to read 3, iclass 2, count 2 2006.201.21:29:37.44#ibcon#read 3, iclass 2, count 2 2006.201.21:29:37.44#ibcon#about to read 4, iclass 2, count 2 2006.201.21:29:37.44#ibcon#read 4, iclass 2, count 2 2006.201.21:29:37.44#ibcon#about to read 5, iclass 2, count 2 2006.201.21:29:37.44#ibcon#read 5, iclass 2, count 2 2006.201.21:29:37.44#ibcon#about to read 6, iclass 2, count 2 2006.201.21:29:37.44#ibcon#read 6, iclass 2, count 2 2006.201.21:29:37.44#ibcon#end of sib2, iclass 2, count 2 2006.201.21:29:37.44#ibcon#*mode == 0, iclass 2, count 2 2006.201.21:29:37.44#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.21:29:37.44#ibcon#[27=AT03-04\r\n] 2006.201.21:29:37.44#ibcon#*before write, iclass 2, count 2 2006.201.21:29:37.44#ibcon#enter sib2, iclass 2, count 2 2006.201.21:29:37.44#ibcon#flushed, iclass 2, count 2 2006.201.21:29:37.44#ibcon#about to write, iclass 2, count 2 2006.201.21:29:37.44#ibcon#wrote, iclass 2, count 2 2006.201.21:29:37.44#ibcon#about to read 3, iclass 2, count 2 2006.201.21:29:37.47#ibcon#read 3, iclass 2, count 2 2006.201.21:29:37.47#ibcon#about to read 4, iclass 2, count 2 2006.201.21:29:37.47#ibcon#read 4, iclass 2, count 2 2006.201.21:29:37.47#ibcon#about to read 5, iclass 2, count 2 2006.201.21:29:37.47#ibcon#read 5, iclass 2, count 2 2006.201.21:29:37.47#ibcon#about to read 6, iclass 2, count 2 2006.201.21:29:37.47#ibcon#read 6, iclass 2, count 2 2006.201.21:29:37.47#ibcon#end of sib2, iclass 2, count 2 2006.201.21:29:37.47#ibcon#*after write, iclass 2, count 2 2006.201.21:29:37.47#ibcon#*before return 0, iclass 2, count 2 2006.201.21:29:37.47#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:37.47#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.21:29:37.47#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.21:29:37.47#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:37.47#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:37.59#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:37.59#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:37.59#ibcon#enter wrdev, iclass 2, count 0 2006.201.21:29:37.59#ibcon#first serial, iclass 2, count 0 2006.201.21:29:37.59#ibcon#enter sib2, iclass 2, count 0 2006.201.21:29:37.59#ibcon#flushed, iclass 2, count 0 2006.201.21:29:37.59#ibcon#about to write, iclass 2, count 0 2006.201.21:29:37.59#ibcon#wrote, iclass 2, count 0 2006.201.21:29:37.59#ibcon#about to read 3, iclass 2, count 0 2006.201.21:29:37.61#ibcon#read 3, iclass 2, count 0 2006.201.21:29:37.61#ibcon#about to read 4, iclass 2, count 0 2006.201.21:29:37.61#ibcon#read 4, iclass 2, count 0 2006.201.21:29:37.61#ibcon#about to read 5, iclass 2, count 0 2006.201.21:29:37.61#ibcon#read 5, iclass 2, count 0 2006.201.21:29:37.61#ibcon#about to read 6, iclass 2, count 0 2006.201.21:29:37.61#ibcon#read 6, iclass 2, count 0 2006.201.21:29:37.61#ibcon#end of sib2, iclass 2, count 0 2006.201.21:29:37.61#ibcon#*mode == 0, iclass 2, count 0 2006.201.21:29:37.61#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.21:29:37.61#ibcon#[27=USB\r\n] 2006.201.21:29:37.61#ibcon#*before write, iclass 2, count 0 2006.201.21:29:37.61#ibcon#enter sib2, iclass 2, count 0 2006.201.21:29:37.61#ibcon#flushed, iclass 2, count 0 2006.201.21:29:37.61#ibcon#about to write, iclass 2, count 0 2006.201.21:29:37.61#ibcon#wrote, iclass 2, count 0 2006.201.21:29:37.61#ibcon#about to read 3, iclass 2, count 0 2006.201.21:29:37.64#ibcon#read 3, iclass 2, count 0 2006.201.21:29:37.64#ibcon#about to read 4, iclass 2, count 0 2006.201.21:29:37.64#ibcon#read 4, iclass 2, count 0 2006.201.21:29:37.64#ibcon#about to read 5, iclass 2, count 0 2006.201.21:29:37.64#ibcon#read 5, iclass 2, count 0 2006.201.21:29:37.64#ibcon#about to read 6, iclass 2, count 0 2006.201.21:29:37.64#ibcon#read 6, iclass 2, count 0 2006.201.21:29:37.64#ibcon#end of sib2, iclass 2, count 0 2006.201.21:29:37.64#ibcon#*after write, iclass 2, count 0 2006.201.21:29:37.64#ibcon#*before return 0, iclass 2, count 0 2006.201.21:29:37.64#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:37.64#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.21:29:37.64#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.21:29:37.64#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.21:29:37.64$vck44/vblo=4,679.99 2006.201.21:29:37.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.21:29:37.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.21:29:37.64#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:37.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:37.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:37.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:37.64#ibcon#enter wrdev, iclass 5, count 0 2006.201.21:29:37.64#ibcon#first serial, iclass 5, count 0 2006.201.21:29:37.64#ibcon#enter sib2, iclass 5, count 0 2006.201.21:29:37.64#ibcon#flushed, iclass 5, count 0 2006.201.21:29:37.64#ibcon#about to write, iclass 5, count 0 2006.201.21:29:37.64#ibcon#wrote, iclass 5, count 0 2006.201.21:29:37.64#ibcon#about to read 3, iclass 5, count 0 2006.201.21:29:37.66#ibcon#read 3, iclass 5, count 0 2006.201.21:29:37.66#ibcon#about to read 4, iclass 5, count 0 2006.201.21:29:37.66#ibcon#read 4, iclass 5, count 0 2006.201.21:29:37.66#ibcon#about to read 5, iclass 5, count 0 2006.201.21:29:37.66#ibcon#read 5, iclass 5, count 0 2006.201.21:29:37.66#ibcon#about to read 6, iclass 5, count 0 2006.201.21:29:37.66#ibcon#read 6, iclass 5, count 0 2006.201.21:29:37.66#ibcon#end of sib2, iclass 5, count 0 2006.201.21:29:37.66#ibcon#*mode == 0, iclass 5, count 0 2006.201.21:29:37.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.21:29:37.66#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.21:29:37.66#ibcon#*before write, iclass 5, count 0 2006.201.21:29:37.66#ibcon#enter sib2, iclass 5, count 0 2006.201.21:29:37.66#ibcon#flushed, iclass 5, count 0 2006.201.21:29:37.66#ibcon#about to write, iclass 5, count 0 2006.201.21:29:37.66#ibcon#wrote, iclass 5, count 0 2006.201.21:29:37.66#ibcon#about to read 3, iclass 5, count 0 2006.201.21:29:37.71#ibcon#read 3, iclass 5, count 0 2006.201.21:29:37.71#ibcon#about to read 4, iclass 5, count 0 2006.201.21:29:37.71#ibcon#read 4, iclass 5, count 0 2006.201.21:29:37.71#ibcon#about to read 5, iclass 5, count 0 2006.201.21:29:37.71#ibcon#read 5, iclass 5, count 0 2006.201.21:29:37.71#ibcon#about to read 6, iclass 5, count 0 2006.201.21:29:37.71#ibcon#read 6, iclass 5, count 0 2006.201.21:29:37.71#ibcon#end of sib2, iclass 5, count 0 2006.201.21:29:37.71#ibcon#*after write, iclass 5, count 0 2006.201.21:29:37.71#ibcon#*before return 0, iclass 5, count 0 2006.201.21:29:37.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:37.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.21:29:37.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.21:29:37.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.21:29:37.71$vck44/vb=4,5 2006.201.21:29:37.71#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.21:29:37.71#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.21:29:37.71#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:37.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:37.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:37.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:37.76#ibcon#enter wrdev, iclass 7, count 2 2006.201.21:29:37.76#ibcon#first serial, iclass 7, count 2 2006.201.21:29:37.76#ibcon#enter sib2, iclass 7, count 2 2006.201.21:29:37.76#ibcon#flushed, iclass 7, count 2 2006.201.21:29:37.76#ibcon#about to write, iclass 7, count 2 2006.201.21:29:37.76#ibcon#wrote, iclass 7, count 2 2006.201.21:29:37.76#ibcon#about to read 3, iclass 7, count 2 2006.201.21:29:37.78#ibcon#read 3, iclass 7, count 2 2006.201.21:29:37.78#ibcon#about to read 4, iclass 7, count 2 2006.201.21:29:37.78#ibcon#read 4, iclass 7, count 2 2006.201.21:29:37.78#ibcon#about to read 5, iclass 7, count 2 2006.201.21:29:37.78#ibcon#read 5, iclass 7, count 2 2006.201.21:29:37.78#ibcon#about to read 6, iclass 7, count 2 2006.201.21:29:37.78#ibcon#read 6, iclass 7, count 2 2006.201.21:29:37.78#ibcon#end of sib2, iclass 7, count 2 2006.201.21:29:37.78#ibcon#*mode == 0, iclass 7, count 2 2006.201.21:29:37.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.21:29:37.78#ibcon#[27=AT04-05\r\n] 2006.201.21:29:37.78#ibcon#*before write, iclass 7, count 2 2006.201.21:29:37.78#ibcon#enter sib2, iclass 7, count 2 2006.201.21:29:37.78#ibcon#flushed, iclass 7, count 2 2006.201.21:29:37.78#ibcon#about to write, iclass 7, count 2 2006.201.21:29:37.78#ibcon#wrote, iclass 7, count 2 2006.201.21:29:37.78#ibcon#about to read 3, iclass 7, count 2 2006.201.21:29:37.81#ibcon#read 3, iclass 7, count 2 2006.201.21:29:37.81#ibcon#about to read 4, iclass 7, count 2 2006.201.21:29:37.81#ibcon#read 4, iclass 7, count 2 2006.201.21:29:37.81#ibcon#about to read 5, iclass 7, count 2 2006.201.21:29:37.81#ibcon#read 5, iclass 7, count 2 2006.201.21:29:37.81#ibcon#about to read 6, iclass 7, count 2 2006.201.21:29:37.81#ibcon#read 6, iclass 7, count 2 2006.201.21:29:37.81#ibcon#end of sib2, iclass 7, count 2 2006.201.21:29:37.81#ibcon#*after write, iclass 7, count 2 2006.201.21:29:37.81#ibcon#*before return 0, iclass 7, count 2 2006.201.21:29:37.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:37.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.21:29:37.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.21:29:37.81#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:37.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:37.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:37.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:37.93#ibcon#enter wrdev, iclass 7, count 0 2006.201.21:29:37.93#ibcon#first serial, iclass 7, count 0 2006.201.21:29:37.93#ibcon#enter sib2, iclass 7, count 0 2006.201.21:29:37.93#ibcon#flushed, iclass 7, count 0 2006.201.21:29:37.93#ibcon#about to write, iclass 7, count 0 2006.201.21:29:37.93#ibcon#wrote, iclass 7, count 0 2006.201.21:29:37.93#ibcon#about to read 3, iclass 7, count 0 2006.201.21:29:37.95#ibcon#read 3, iclass 7, count 0 2006.201.21:29:37.95#ibcon#about to read 4, iclass 7, count 0 2006.201.21:29:37.95#ibcon#read 4, iclass 7, count 0 2006.201.21:29:37.95#ibcon#about to read 5, iclass 7, count 0 2006.201.21:29:37.95#ibcon#read 5, iclass 7, count 0 2006.201.21:29:37.95#ibcon#about to read 6, iclass 7, count 0 2006.201.21:29:37.95#ibcon#read 6, iclass 7, count 0 2006.201.21:29:37.95#ibcon#end of sib2, iclass 7, count 0 2006.201.21:29:37.95#ibcon#*mode == 0, iclass 7, count 0 2006.201.21:29:37.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.21:29:37.95#ibcon#[27=USB\r\n] 2006.201.21:29:37.95#ibcon#*before write, iclass 7, count 0 2006.201.21:29:37.95#ibcon#enter sib2, iclass 7, count 0 2006.201.21:29:37.95#ibcon#flushed, iclass 7, count 0 2006.201.21:29:37.95#ibcon#about to write, iclass 7, count 0 2006.201.21:29:37.95#ibcon#wrote, iclass 7, count 0 2006.201.21:29:37.95#ibcon#about to read 3, iclass 7, count 0 2006.201.21:29:37.98#ibcon#read 3, iclass 7, count 0 2006.201.21:29:37.98#ibcon#about to read 4, iclass 7, count 0 2006.201.21:29:37.98#ibcon#read 4, iclass 7, count 0 2006.201.21:29:37.98#ibcon#about to read 5, iclass 7, count 0 2006.201.21:29:37.98#ibcon#read 5, iclass 7, count 0 2006.201.21:29:37.98#ibcon#about to read 6, iclass 7, count 0 2006.201.21:29:37.98#ibcon#read 6, iclass 7, count 0 2006.201.21:29:37.98#ibcon#end of sib2, iclass 7, count 0 2006.201.21:29:37.98#ibcon#*after write, iclass 7, count 0 2006.201.21:29:37.98#ibcon#*before return 0, iclass 7, count 0 2006.201.21:29:37.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:37.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.21:29:37.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.21:29:37.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.21:29:37.98$vck44/vblo=5,709.99 2006.201.21:29:37.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.21:29:37.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.21:29:37.98#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:37.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:37.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:37.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:37.98#ibcon#enter wrdev, iclass 11, count 0 2006.201.21:29:37.98#ibcon#first serial, iclass 11, count 0 2006.201.21:29:37.98#ibcon#enter sib2, iclass 11, count 0 2006.201.21:29:37.98#ibcon#flushed, iclass 11, count 0 2006.201.21:29:37.98#ibcon#about to write, iclass 11, count 0 2006.201.21:29:37.98#ibcon#wrote, iclass 11, count 0 2006.201.21:29:37.98#ibcon#about to read 3, iclass 11, count 0 2006.201.21:29:38.00#ibcon#read 3, iclass 11, count 0 2006.201.21:29:38.00#ibcon#about to read 4, iclass 11, count 0 2006.201.21:29:38.00#ibcon#read 4, iclass 11, count 0 2006.201.21:29:38.00#ibcon#about to read 5, iclass 11, count 0 2006.201.21:29:38.00#ibcon#read 5, iclass 11, count 0 2006.201.21:29:38.00#ibcon#about to read 6, iclass 11, count 0 2006.201.21:29:38.00#ibcon#read 6, iclass 11, count 0 2006.201.21:29:38.00#ibcon#end of sib2, iclass 11, count 0 2006.201.21:29:38.00#ibcon#*mode == 0, iclass 11, count 0 2006.201.21:29:38.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.21:29:38.00#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.21:29:38.00#ibcon#*before write, iclass 11, count 0 2006.201.21:29:38.00#ibcon#enter sib2, iclass 11, count 0 2006.201.21:29:38.00#ibcon#flushed, iclass 11, count 0 2006.201.21:29:38.00#ibcon#about to write, iclass 11, count 0 2006.201.21:29:38.00#ibcon#wrote, iclass 11, count 0 2006.201.21:29:38.00#ibcon#about to read 3, iclass 11, count 0 2006.201.21:29:38.04#ibcon#read 3, iclass 11, count 0 2006.201.21:29:38.04#ibcon#about to read 4, iclass 11, count 0 2006.201.21:29:38.04#ibcon#read 4, iclass 11, count 0 2006.201.21:29:38.04#ibcon#about to read 5, iclass 11, count 0 2006.201.21:29:38.04#ibcon#read 5, iclass 11, count 0 2006.201.21:29:38.04#ibcon#about to read 6, iclass 11, count 0 2006.201.21:29:38.04#ibcon#read 6, iclass 11, count 0 2006.201.21:29:38.04#ibcon#end of sib2, iclass 11, count 0 2006.201.21:29:38.04#ibcon#*after write, iclass 11, count 0 2006.201.21:29:38.04#ibcon#*before return 0, iclass 11, count 0 2006.201.21:29:38.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:38.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.21:29:38.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.21:29:38.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.21:29:38.04$vck44/vb=5,4 2006.201.21:29:38.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.21:29:38.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.21:29:38.04#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:38.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:38.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:38.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:38.10#ibcon#enter wrdev, iclass 13, count 2 2006.201.21:29:38.10#ibcon#first serial, iclass 13, count 2 2006.201.21:29:38.10#ibcon#enter sib2, iclass 13, count 2 2006.201.21:29:38.10#ibcon#flushed, iclass 13, count 2 2006.201.21:29:38.10#ibcon#about to write, iclass 13, count 2 2006.201.21:29:38.10#ibcon#wrote, iclass 13, count 2 2006.201.21:29:38.10#ibcon#about to read 3, iclass 13, count 2 2006.201.21:29:38.12#ibcon#read 3, iclass 13, count 2 2006.201.21:29:38.12#ibcon#about to read 4, iclass 13, count 2 2006.201.21:29:38.12#ibcon#read 4, iclass 13, count 2 2006.201.21:29:38.12#ibcon#about to read 5, iclass 13, count 2 2006.201.21:29:38.12#ibcon#read 5, iclass 13, count 2 2006.201.21:29:38.12#ibcon#about to read 6, iclass 13, count 2 2006.201.21:29:38.12#ibcon#read 6, iclass 13, count 2 2006.201.21:29:38.12#ibcon#end of sib2, iclass 13, count 2 2006.201.21:29:38.12#ibcon#*mode == 0, iclass 13, count 2 2006.201.21:29:38.12#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.21:29:38.12#ibcon#[27=AT05-04\r\n] 2006.201.21:29:38.12#ibcon#*before write, iclass 13, count 2 2006.201.21:29:38.12#ibcon#enter sib2, iclass 13, count 2 2006.201.21:29:38.12#ibcon#flushed, iclass 13, count 2 2006.201.21:29:38.12#ibcon#about to write, iclass 13, count 2 2006.201.21:29:38.12#ibcon#wrote, iclass 13, count 2 2006.201.21:29:38.12#ibcon#about to read 3, iclass 13, count 2 2006.201.21:29:38.15#ibcon#read 3, iclass 13, count 2 2006.201.21:29:38.15#ibcon#about to read 4, iclass 13, count 2 2006.201.21:29:38.15#ibcon#read 4, iclass 13, count 2 2006.201.21:29:38.15#ibcon#about to read 5, iclass 13, count 2 2006.201.21:29:38.15#ibcon#read 5, iclass 13, count 2 2006.201.21:29:38.15#ibcon#about to read 6, iclass 13, count 2 2006.201.21:29:38.15#ibcon#read 6, iclass 13, count 2 2006.201.21:29:38.15#ibcon#end of sib2, iclass 13, count 2 2006.201.21:29:38.15#ibcon#*after write, iclass 13, count 2 2006.201.21:29:38.15#ibcon#*before return 0, iclass 13, count 2 2006.201.21:29:38.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:38.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.21:29:38.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.21:29:38.15#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:38.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:38.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:38.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:38.27#ibcon#enter wrdev, iclass 13, count 0 2006.201.21:29:38.27#ibcon#first serial, iclass 13, count 0 2006.201.21:29:38.27#ibcon#enter sib2, iclass 13, count 0 2006.201.21:29:38.27#ibcon#flushed, iclass 13, count 0 2006.201.21:29:38.27#ibcon#about to write, iclass 13, count 0 2006.201.21:29:38.27#ibcon#wrote, iclass 13, count 0 2006.201.21:29:38.27#ibcon#about to read 3, iclass 13, count 0 2006.201.21:29:38.29#ibcon#read 3, iclass 13, count 0 2006.201.21:29:38.29#ibcon#about to read 4, iclass 13, count 0 2006.201.21:29:38.29#ibcon#read 4, iclass 13, count 0 2006.201.21:29:38.29#ibcon#about to read 5, iclass 13, count 0 2006.201.21:29:38.29#ibcon#read 5, iclass 13, count 0 2006.201.21:29:38.29#ibcon#about to read 6, iclass 13, count 0 2006.201.21:29:38.29#ibcon#read 6, iclass 13, count 0 2006.201.21:29:38.29#ibcon#end of sib2, iclass 13, count 0 2006.201.21:29:38.29#ibcon#*mode == 0, iclass 13, count 0 2006.201.21:29:38.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.21:29:38.29#ibcon#[27=USB\r\n] 2006.201.21:29:38.29#ibcon#*before write, iclass 13, count 0 2006.201.21:29:38.29#ibcon#enter sib2, iclass 13, count 0 2006.201.21:29:38.29#ibcon#flushed, iclass 13, count 0 2006.201.21:29:38.29#ibcon#about to write, iclass 13, count 0 2006.201.21:29:38.29#ibcon#wrote, iclass 13, count 0 2006.201.21:29:38.29#ibcon#about to read 3, iclass 13, count 0 2006.201.21:29:38.32#ibcon#read 3, iclass 13, count 0 2006.201.21:29:38.32#ibcon#about to read 4, iclass 13, count 0 2006.201.21:29:38.32#ibcon#read 4, iclass 13, count 0 2006.201.21:29:38.32#ibcon#about to read 5, iclass 13, count 0 2006.201.21:29:38.32#ibcon#read 5, iclass 13, count 0 2006.201.21:29:38.32#ibcon#about to read 6, iclass 13, count 0 2006.201.21:29:38.32#ibcon#read 6, iclass 13, count 0 2006.201.21:29:38.32#ibcon#end of sib2, iclass 13, count 0 2006.201.21:29:38.32#ibcon#*after write, iclass 13, count 0 2006.201.21:29:38.32#ibcon#*before return 0, iclass 13, count 0 2006.201.21:29:38.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:38.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.21:29:38.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.21:29:38.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.21:29:38.32$vck44/vblo=6,719.99 2006.201.21:29:38.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.21:29:38.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.21:29:38.32#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:38.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:38.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:38.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:38.32#ibcon#enter wrdev, iclass 15, count 0 2006.201.21:29:38.32#ibcon#first serial, iclass 15, count 0 2006.201.21:29:38.32#ibcon#enter sib2, iclass 15, count 0 2006.201.21:29:38.32#ibcon#flushed, iclass 15, count 0 2006.201.21:29:38.32#ibcon#about to write, iclass 15, count 0 2006.201.21:29:38.32#ibcon#wrote, iclass 15, count 0 2006.201.21:29:38.32#ibcon#about to read 3, iclass 15, count 0 2006.201.21:29:38.34#ibcon#read 3, iclass 15, count 0 2006.201.21:29:38.34#ibcon#about to read 4, iclass 15, count 0 2006.201.21:29:38.34#ibcon#read 4, iclass 15, count 0 2006.201.21:29:38.34#ibcon#about to read 5, iclass 15, count 0 2006.201.21:29:38.34#ibcon#read 5, iclass 15, count 0 2006.201.21:29:38.34#ibcon#about to read 6, iclass 15, count 0 2006.201.21:29:38.34#ibcon#read 6, iclass 15, count 0 2006.201.21:29:38.34#ibcon#end of sib2, iclass 15, count 0 2006.201.21:29:38.34#ibcon#*mode == 0, iclass 15, count 0 2006.201.21:29:38.34#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.21:29:38.34#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.21:29:38.34#ibcon#*before write, iclass 15, count 0 2006.201.21:29:38.34#ibcon#enter sib2, iclass 15, count 0 2006.201.21:29:38.34#ibcon#flushed, iclass 15, count 0 2006.201.21:29:38.34#ibcon#about to write, iclass 15, count 0 2006.201.21:29:38.34#ibcon#wrote, iclass 15, count 0 2006.201.21:29:38.34#ibcon#about to read 3, iclass 15, count 0 2006.201.21:29:38.39#ibcon#read 3, iclass 15, count 0 2006.201.21:29:38.39#ibcon#about to read 4, iclass 15, count 0 2006.201.21:29:38.39#ibcon#read 4, iclass 15, count 0 2006.201.21:29:38.39#ibcon#about to read 5, iclass 15, count 0 2006.201.21:29:38.39#ibcon#read 5, iclass 15, count 0 2006.201.21:29:38.39#ibcon#about to read 6, iclass 15, count 0 2006.201.21:29:38.39#ibcon#read 6, iclass 15, count 0 2006.201.21:29:38.39#ibcon#end of sib2, iclass 15, count 0 2006.201.21:29:38.39#ibcon#*after write, iclass 15, count 0 2006.201.21:29:38.39#ibcon#*before return 0, iclass 15, count 0 2006.201.21:29:38.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:38.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.21:29:38.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.21:29:38.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.21:29:38.39$vck44/vb=6,4 2006.201.21:29:38.39#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.21:29:38.39#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.21:29:38.39#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:38.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:38.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:38.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:38.44#ibcon#enter wrdev, iclass 17, count 2 2006.201.21:29:38.44#ibcon#first serial, iclass 17, count 2 2006.201.21:29:38.44#ibcon#enter sib2, iclass 17, count 2 2006.201.21:29:38.44#ibcon#flushed, iclass 17, count 2 2006.201.21:29:38.44#ibcon#about to write, iclass 17, count 2 2006.201.21:29:38.44#ibcon#wrote, iclass 17, count 2 2006.201.21:29:38.44#ibcon#about to read 3, iclass 17, count 2 2006.201.21:29:38.46#ibcon#read 3, iclass 17, count 2 2006.201.21:29:38.46#ibcon#about to read 4, iclass 17, count 2 2006.201.21:29:38.46#ibcon#read 4, iclass 17, count 2 2006.201.21:29:38.46#ibcon#about to read 5, iclass 17, count 2 2006.201.21:29:38.46#ibcon#read 5, iclass 17, count 2 2006.201.21:29:38.46#ibcon#about to read 6, iclass 17, count 2 2006.201.21:29:38.46#ibcon#read 6, iclass 17, count 2 2006.201.21:29:38.46#ibcon#end of sib2, iclass 17, count 2 2006.201.21:29:38.46#ibcon#*mode == 0, iclass 17, count 2 2006.201.21:29:38.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.21:29:38.46#ibcon#[27=AT06-04\r\n] 2006.201.21:29:38.46#ibcon#*before write, iclass 17, count 2 2006.201.21:29:38.46#ibcon#enter sib2, iclass 17, count 2 2006.201.21:29:38.46#ibcon#flushed, iclass 17, count 2 2006.201.21:29:38.46#ibcon#about to write, iclass 17, count 2 2006.201.21:29:38.46#ibcon#wrote, iclass 17, count 2 2006.201.21:29:38.46#ibcon#about to read 3, iclass 17, count 2 2006.201.21:29:38.49#ibcon#read 3, iclass 17, count 2 2006.201.21:29:38.49#ibcon#about to read 4, iclass 17, count 2 2006.201.21:29:38.49#ibcon#read 4, iclass 17, count 2 2006.201.21:29:38.49#ibcon#about to read 5, iclass 17, count 2 2006.201.21:29:38.49#ibcon#read 5, iclass 17, count 2 2006.201.21:29:38.49#ibcon#about to read 6, iclass 17, count 2 2006.201.21:29:38.49#ibcon#read 6, iclass 17, count 2 2006.201.21:29:38.49#ibcon#end of sib2, iclass 17, count 2 2006.201.21:29:38.49#ibcon#*after write, iclass 17, count 2 2006.201.21:29:38.49#ibcon#*before return 0, iclass 17, count 2 2006.201.21:29:38.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:38.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.21:29:38.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.21:29:38.49#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:38.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:38.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:38.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:38.61#ibcon#enter wrdev, iclass 17, count 0 2006.201.21:29:38.61#ibcon#first serial, iclass 17, count 0 2006.201.21:29:38.61#ibcon#enter sib2, iclass 17, count 0 2006.201.21:29:38.61#ibcon#flushed, iclass 17, count 0 2006.201.21:29:38.61#ibcon#about to write, iclass 17, count 0 2006.201.21:29:38.61#ibcon#wrote, iclass 17, count 0 2006.201.21:29:38.61#ibcon#about to read 3, iclass 17, count 0 2006.201.21:29:38.63#ibcon#read 3, iclass 17, count 0 2006.201.21:29:38.63#ibcon#about to read 4, iclass 17, count 0 2006.201.21:29:38.63#ibcon#read 4, iclass 17, count 0 2006.201.21:29:38.63#ibcon#about to read 5, iclass 17, count 0 2006.201.21:29:38.63#ibcon#read 5, iclass 17, count 0 2006.201.21:29:38.63#ibcon#about to read 6, iclass 17, count 0 2006.201.21:29:38.63#ibcon#read 6, iclass 17, count 0 2006.201.21:29:38.63#ibcon#end of sib2, iclass 17, count 0 2006.201.21:29:38.63#ibcon#*mode == 0, iclass 17, count 0 2006.201.21:29:38.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.21:29:38.63#ibcon#[27=USB\r\n] 2006.201.21:29:38.63#ibcon#*before write, iclass 17, count 0 2006.201.21:29:38.63#ibcon#enter sib2, iclass 17, count 0 2006.201.21:29:38.63#ibcon#flushed, iclass 17, count 0 2006.201.21:29:38.63#ibcon#about to write, iclass 17, count 0 2006.201.21:29:38.63#ibcon#wrote, iclass 17, count 0 2006.201.21:29:38.63#ibcon#about to read 3, iclass 17, count 0 2006.201.21:29:38.66#ibcon#read 3, iclass 17, count 0 2006.201.21:29:38.66#ibcon#about to read 4, iclass 17, count 0 2006.201.21:29:38.66#ibcon#read 4, iclass 17, count 0 2006.201.21:29:38.66#ibcon#about to read 5, iclass 17, count 0 2006.201.21:29:38.66#ibcon#read 5, iclass 17, count 0 2006.201.21:29:38.66#ibcon#about to read 6, iclass 17, count 0 2006.201.21:29:38.66#ibcon#read 6, iclass 17, count 0 2006.201.21:29:38.66#ibcon#end of sib2, iclass 17, count 0 2006.201.21:29:38.66#ibcon#*after write, iclass 17, count 0 2006.201.21:29:38.66#ibcon#*before return 0, iclass 17, count 0 2006.201.21:29:38.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:38.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.21:29:38.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.21:29:38.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.21:29:38.66$vck44/vblo=7,734.99 2006.201.21:29:38.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.21:29:38.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.21:29:38.66#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:38.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:29:38.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:29:38.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:29:38.66#ibcon#enter wrdev, iclass 19, count 0 2006.201.21:29:38.66#ibcon#first serial, iclass 19, count 0 2006.201.21:29:38.66#ibcon#enter sib2, iclass 19, count 0 2006.201.21:29:38.66#ibcon#flushed, iclass 19, count 0 2006.201.21:29:38.66#ibcon#about to write, iclass 19, count 0 2006.201.21:29:38.66#ibcon#wrote, iclass 19, count 0 2006.201.21:29:38.66#ibcon#about to read 3, iclass 19, count 0 2006.201.21:29:38.68#ibcon#read 3, iclass 19, count 0 2006.201.21:29:38.68#ibcon#about to read 4, iclass 19, count 0 2006.201.21:29:38.68#ibcon#read 4, iclass 19, count 0 2006.201.21:29:38.68#ibcon#about to read 5, iclass 19, count 0 2006.201.21:29:38.68#ibcon#read 5, iclass 19, count 0 2006.201.21:29:38.68#ibcon#about to read 6, iclass 19, count 0 2006.201.21:29:38.68#ibcon#read 6, iclass 19, count 0 2006.201.21:29:38.68#ibcon#end of sib2, iclass 19, count 0 2006.201.21:29:38.68#ibcon#*mode == 0, iclass 19, count 0 2006.201.21:29:38.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.21:29:38.68#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.21:29:38.68#ibcon#*before write, iclass 19, count 0 2006.201.21:29:38.68#ibcon#enter sib2, iclass 19, count 0 2006.201.21:29:38.68#ibcon#flushed, iclass 19, count 0 2006.201.21:29:38.68#ibcon#about to write, iclass 19, count 0 2006.201.21:29:38.68#ibcon#wrote, iclass 19, count 0 2006.201.21:29:38.68#ibcon#about to read 3, iclass 19, count 0 2006.201.21:29:38.72#ibcon#read 3, iclass 19, count 0 2006.201.21:29:38.72#ibcon#about to read 4, iclass 19, count 0 2006.201.21:29:38.72#ibcon#read 4, iclass 19, count 0 2006.201.21:29:38.72#ibcon#about to read 5, iclass 19, count 0 2006.201.21:29:38.72#ibcon#read 5, iclass 19, count 0 2006.201.21:29:38.72#ibcon#about to read 6, iclass 19, count 0 2006.201.21:29:38.72#ibcon#read 6, iclass 19, count 0 2006.201.21:29:38.72#ibcon#end of sib2, iclass 19, count 0 2006.201.21:29:38.72#ibcon#*after write, iclass 19, count 0 2006.201.21:29:38.72#ibcon#*before return 0, iclass 19, count 0 2006.201.21:29:38.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:29:38.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:29:38.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.21:29:38.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.21:29:38.72$vck44/vb=7,4 2006.201.21:29:38.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.21:29:38.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.21:29:38.72#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:38.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.21:29:38.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.21:29:38.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.21:29:38.78#ibcon#enter wrdev, iclass 21, count 2 2006.201.21:29:38.78#ibcon#first serial, iclass 21, count 2 2006.201.21:29:38.78#ibcon#enter sib2, iclass 21, count 2 2006.201.21:29:38.78#ibcon#flushed, iclass 21, count 2 2006.201.21:29:38.78#ibcon#about to write, iclass 21, count 2 2006.201.21:29:38.78#ibcon#wrote, iclass 21, count 2 2006.201.21:29:38.78#ibcon#about to read 3, iclass 21, count 2 2006.201.21:29:38.80#ibcon#read 3, iclass 21, count 2 2006.201.21:29:38.80#ibcon#about to read 4, iclass 21, count 2 2006.201.21:29:38.80#ibcon#read 4, iclass 21, count 2 2006.201.21:29:38.80#ibcon#about to read 5, iclass 21, count 2 2006.201.21:29:38.80#ibcon#read 5, iclass 21, count 2 2006.201.21:29:38.80#ibcon#about to read 6, iclass 21, count 2 2006.201.21:29:38.80#ibcon#read 6, iclass 21, count 2 2006.201.21:29:38.80#ibcon#end of sib2, iclass 21, count 2 2006.201.21:29:38.80#ibcon#*mode == 0, iclass 21, count 2 2006.201.21:29:38.80#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.21:29:38.80#ibcon#[27=AT07-04\r\n] 2006.201.21:29:38.80#ibcon#*before write, iclass 21, count 2 2006.201.21:29:38.80#ibcon#enter sib2, iclass 21, count 2 2006.201.21:29:38.80#ibcon#flushed, iclass 21, count 2 2006.201.21:29:38.80#ibcon#about to write, iclass 21, count 2 2006.201.21:29:38.80#ibcon#wrote, iclass 21, count 2 2006.201.21:29:38.80#ibcon#about to read 3, iclass 21, count 2 2006.201.21:29:38.83#ibcon#read 3, iclass 21, count 2 2006.201.21:29:38.83#ibcon#about to read 4, iclass 21, count 2 2006.201.21:29:38.83#ibcon#read 4, iclass 21, count 2 2006.201.21:29:38.83#ibcon#about to read 5, iclass 21, count 2 2006.201.21:29:38.83#ibcon#read 5, iclass 21, count 2 2006.201.21:29:38.83#ibcon#about to read 6, iclass 21, count 2 2006.201.21:29:38.83#ibcon#read 6, iclass 21, count 2 2006.201.21:29:38.83#ibcon#end of sib2, iclass 21, count 2 2006.201.21:29:38.83#ibcon#*after write, iclass 21, count 2 2006.201.21:29:38.83#ibcon#*before return 0, iclass 21, count 2 2006.201.21:29:38.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.21:29:38.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.21:29:38.83#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.21:29:38.83#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:38.83#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.21:29:38.95#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.21:29:38.95#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.21:29:38.95#ibcon#enter wrdev, iclass 21, count 0 2006.201.21:29:38.95#ibcon#first serial, iclass 21, count 0 2006.201.21:29:38.95#ibcon#enter sib2, iclass 21, count 0 2006.201.21:29:38.95#ibcon#flushed, iclass 21, count 0 2006.201.21:29:38.95#ibcon#about to write, iclass 21, count 0 2006.201.21:29:38.95#ibcon#wrote, iclass 21, count 0 2006.201.21:29:38.95#ibcon#about to read 3, iclass 21, count 0 2006.201.21:29:38.97#ibcon#read 3, iclass 21, count 0 2006.201.21:29:38.97#ibcon#about to read 4, iclass 21, count 0 2006.201.21:29:38.97#ibcon#read 4, iclass 21, count 0 2006.201.21:29:38.97#ibcon#about to read 5, iclass 21, count 0 2006.201.21:29:38.97#ibcon#read 5, iclass 21, count 0 2006.201.21:29:38.97#ibcon#about to read 6, iclass 21, count 0 2006.201.21:29:38.97#ibcon#read 6, iclass 21, count 0 2006.201.21:29:38.97#ibcon#end of sib2, iclass 21, count 0 2006.201.21:29:38.97#ibcon#*mode == 0, iclass 21, count 0 2006.201.21:29:38.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.21:29:38.97#ibcon#[27=USB\r\n] 2006.201.21:29:38.97#ibcon#*before write, iclass 21, count 0 2006.201.21:29:38.97#ibcon#enter sib2, iclass 21, count 0 2006.201.21:29:38.97#ibcon#flushed, iclass 21, count 0 2006.201.21:29:38.97#ibcon#about to write, iclass 21, count 0 2006.201.21:29:38.97#ibcon#wrote, iclass 21, count 0 2006.201.21:29:38.97#ibcon#about to read 3, iclass 21, count 0 2006.201.21:29:39.00#ibcon#read 3, iclass 21, count 0 2006.201.21:29:39.00#ibcon#about to read 4, iclass 21, count 0 2006.201.21:29:39.00#ibcon#read 4, iclass 21, count 0 2006.201.21:29:39.00#ibcon#about to read 5, iclass 21, count 0 2006.201.21:29:39.00#ibcon#read 5, iclass 21, count 0 2006.201.21:29:39.00#ibcon#about to read 6, iclass 21, count 0 2006.201.21:29:39.00#ibcon#read 6, iclass 21, count 0 2006.201.21:29:39.00#ibcon#end of sib2, iclass 21, count 0 2006.201.21:29:39.00#ibcon#*after write, iclass 21, count 0 2006.201.21:29:39.00#ibcon#*before return 0, iclass 21, count 0 2006.201.21:29:39.00#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.21:29:39.00#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.21:29:39.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.21:29:39.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.21:29:39.00$vck44/vblo=8,744.99 2006.201.21:29:39.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.21:29:39.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.21:29:39.00#ibcon#ireg 17 cls_cnt 0 2006.201.21:29:39.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:39.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:39.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:39.00#ibcon#enter wrdev, iclass 23, count 0 2006.201.21:29:39.00#ibcon#first serial, iclass 23, count 0 2006.201.21:29:39.00#ibcon#enter sib2, iclass 23, count 0 2006.201.21:29:39.00#ibcon#flushed, iclass 23, count 0 2006.201.21:29:39.00#ibcon#about to write, iclass 23, count 0 2006.201.21:29:39.00#ibcon#wrote, iclass 23, count 0 2006.201.21:29:39.00#ibcon#about to read 3, iclass 23, count 0 2006.201.21:29:39.02#ibcon#read 3, iclass 23, count 0 2006.201.21:29:39.02#ibcon#about to read 4, iclass 23, count 0 2006.201.21:29:39.02#ibcon#read 4, iclass 23, count 0 2006.201.21:29:39.02#ibcon#about to read 5, iclass 23, count 0 2006.201.21:29:39.02#ibcon#read 5, iclass 23, count 0 2006.201.21:29:39.02#ibcon#about to read 6, iclass 23, count 0 2006.201.21:29:39.02#ibcon#read 6, iclass 23, count 0 2006.201.21:29:39.02#ibcon#end of sib2, iclass 23, count 0 2006.201.21:29:39.02#ibcon#*mode == 0, iclass 23, count 0 2006.201.21:29:39.02#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.21:29:39.02#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.21:29:39.02#ibcon#*before write, iclass 23, count 0 2006.201.21:29:39.02#ibcon#enter sib2, iclass 23, count 0 2006.201.21:29:39.02#ibcon#flushed, iclass 23, count 0 2006.201.21:29:39.02#ibcon#about to write, iclass 23, count 0 2006.201.21:29:39.02#ibcon#wrote, iclass 23, count 0 2006.201.21:29:39.02#ibcon#about to read 3, iclass 23, count 0 2006.201.21:29:39.06#ibcon#read 3, iclass 23, count 0 2006.201.21:29:39.06#ibcon#about to read 4, iclass 23, count 0 2006.201.21:29:39.06#ibcon#read 4, iclass 23, count 0 2006.201.21:29:39.06#ibcon#about to read 5, iclass 23, count 0 2006.201.21:29:39.06#ibcon#read 5, iclass 23, count 0 2006.201.21:29:39.06#ibcon#about to read 6, iclass 23, count 0 2006.201.21:29:39.06#ibcon#read 6, iclass 23, count 0 2006.201.21:29:39.06#ibcon#end of sib2, iclass 23, count 0 2006.201.21:29:39.06#ibcon#*after write, iclass 23, count 0 2006.201.21:29:39.06#ibcon#*before return 0, iclass 23, count 0 2006.201.21:29:39.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:39.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.21:29:39.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.21:29:39.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.21:29:39.06$vck44/vb=8,4 2006.201.21:29:39.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.21:29:39.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.21:29:39.06#ibcon#ireg 11 cls_cnt 2 2006.201.21:29:39.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:39.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:39.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:39.12#ibcon#enter wrdev, iclass 25, count 2 2006.201.21:29:39.12#ibcon#first serial, iclass 25, count 2 2006.201.21:29:39.12#ibcon#enter sib2, iclass 25, count 2 2006.201.21:29:39.12#ibcon#flushed, iclass 25, count 2 2006.201.21:29:39.12#ibcon#about to write, iclass 25, count 2 2006.201.21:29:39.12#ibcon#wrote, iclass 25, count 2 2006.201.21:29:39.12#ibcon#about to read 3, iclass 25, count 2 2006.201.21:29:39.14#ibcon#read 3, iclass 25, count 2 2006.201.21:29:39.14#ibcon#about to read 4, iclass 25, count 2 2006.201.21:29:39.14#ibcon#read 4, iclass 25, count 2 2006.201.21:29:39.14#ibcon#about to read 5, iclass 25, count 2 2006.201.21:29:39.14#ibcon#read 5, iclass 25, count 2 2006.201.21:29:39.14#ibcon#about to read 6, iclass 25, count 2 2006.201.21:29:39.14#ibcon#read 6, iclass 25, count 2 2006.201.21:29:39.14#ibcon#end of sib2, iclass 25, count 2 2006.201.21:29:39.14#ibcon#*mode == 0, iclass 25, count 2 2006.201.21:29:39.14#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.21:29:39.14#ibcon#[27=AT08-04\r\n] 2006.201.21:29:39.14#ibcon#*before write, iclass 25, count 2 2006.201.21:29:39.14#ibcon#enter sib2, iclass 25, count 2 2006.201.21:29:39.14#ibcon#flushed, iclass 25, count 2 2006.201.21:29:39.14#ibcon#about to write, iclass 25, count 2 2006.201.21:29:39.14#ibcon#wrote, iclass 25, count 2 2006.201.21:29:39.14#ibcon#about to read 3, iclass 25, count 2 2006.201.21:29:39.17#ibcon#read 3, iclass 25, count 2 2006.201.21:29:39.17#ibcon#about to read 4, iclass 25, count 2 2006.201.21:29:39.17#ibcon#read 4, iclass 25, count 2 2006.201.21:29:39.17#ibcon#about to read 5, iclass 25, count 2 2006.201.21:29:39.17#ibcon#read 5, iclass 25, count 2 2006.201.21:29:39.17#ibcon#about to read 6, iclass 25, count 2 2006.201.21:29:39.17#ibcon#read 6, iclass 25, count 2 2006.201.21:29:39.17#ibcon#end of sib2, iclass 25, count 2 2006.201.21:29:39.17#ibcon#*after write, iclass 25, count 2 2006.201.21:29:39.17#ibcon#*before return 0, iclass 25, count 2 2006.201.21:29:39.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:39.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.21:29:39.17#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.21:29:39.17#ibcon#ireg 7 cls_cnt 0 2006.201.21:29:39.17#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:39.29#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:39.29#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:39.29#ibcon#enter wrdev, iclass 25, count 0 2006.201.21:29:39.29#ibcon#first serial, iclass 25, count 0 2006.201.21:29:39.29#ibcon#enter sib2, iclass 25, count 0 2006.201.21:29:39.29#ibcon#flushed, iclass 25, count 0 2006.201.21:29:39.29#ibcon#about to write, iclass 25, count 0 2006.201.21:29:39.29#ibcon#wrote, iclass 25, count 0 2006.201.21:29:39.29#ibcon#about to read 3, iclass 25, count 0 2006.201.21:29:39.31#ibcon#read 3, iclass 25, count 0 2006.201.21:29:39.31#ibcon#about to read 4, iclass 25, count 0 2006.201.21:29:39.31#ibcon#read 4, iclass 25, count 0 2006.201.21:29:39.31#ibcon#about to read 5, iclass 25, count 0 2006.201.21:29:39.31#ibcon#read 5, iclass 25, count 0 2006.201.21:29:39.31#ibcon#about to read 6, iclass 25, count 0 2006.201.21:29:39.31#ibcon#read 6, iclass 25, count 0 2006.201.21:29:39.31#ibcon#end of sib2, iclass 25, count 0 2006.201.21:29:39.31#ibcon#*mode == 0, iclass 25, count 0 2006.201.21:29:39.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.21:29:39.31#ibcon#[27=USB\r\n] 2006.201.21:29:39.31#ibcon#*before write, iclass 25, count 0 2006.201.21:29:39.31#ibcon#enter sib2, iclass 25, count 0 2006.201.21:29:39.31#ibcon#flushed, iclass 25, count 0 2006.201.21:29:39.31#ibcon#about to write, iclass 25, count 0 2006.201.21:29:39.31#ibcon#wrote, iclass 25, count 0 2006.201.21:29:39.31#ibcon#about to read 3, iclass 25, count 0 2006.201.21:29:39.34#ibcon#read 3, iclass 25, count 0 2006.201.21:29:39.34#ibcon#about to read 4, iclass 25, count 0 2006.201.21:29:39.34#ibcon#read 4, iclass 25, count 0 2006.201.21:29:39.34#ibcon#about to read 5, iclass 25, count 0 2006.201.21:29:39.34#ibcon#read 5, iclass 25, count 0 2006.201.21:29:39.34#ibcon#about to read 6, iclass 25, count 0 2006.201.21:29:39.34#ibcon#read 6, iclass 25, count 0 2006.201.21:29:39.34#ibcon#end of sib2, iclass 25, count 0 2006.201.21:29:39.34#ibcon#*after write, iclass 25, count 0 2006.201.21:29:39.34#ibcon#*before return 0, iclass 25, count 0 2006.201.21:29:39.34#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:39.34#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.21:29:39.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.21:29:39.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.21:29:39.34$vck44/vabw=wide 2006.201.21:29:39.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.21:29:39.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.21:29:39.34#ibcon#ireg 8 cls_cnt 0 2006.201.21:29:39.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:39.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:39.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:39.34#ibcon#enter wrdev, iclass 27, count 0 2006.201.21:29:39.34#ibcon#first serial, iclass 27, count 0 2006.201.21:29:39.34#ibcon#enter sib2, iclass 27, count 0 2006.201.21:29:39.34#ibcon#flushed, iclass 27, count 0 2006.201.21:29:39.34#ibcon#about to write, iclass 27, count 0 2006.201.21:29:39.34#ibcon#wrote, iclass 27, count 0 2006.201.21:29:39.34#ibcon#about to read 3, iclass 27, count 0 2006.201.21:29:39.36#ibcon#read 3, iclass 27, count 0 2006.201.21:29:39.36#ibcon#about to read 4, iclass 27, count 0 2006.201.21:29:39.36#ibcon#read 4, iclass 27, count 0 2006.201.21:29:39.36#ibcon#about to read 5, iclass 27, count 0 2006.201.21:29:39.36#ibcon#read 5, iclass 27, count 0 2006.201.21:29:39.36#ibcon#about to read 6, iclass 27, count 0 2006.201.21:29:39.36#ibcon#read 6, iclass 27, count 0 2006.201.21:29:39.36#ibcon#end of sib2, iclass 27, count 0 2006.201.21:29:39.36#ibcon#*mode == 0, iclass 27, count 0 2006.201.21:29:39.36#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.21:29:39.36#ibcon#[25=BW32\r\n] 2006.201.21:29:39.36#ibcon#*before write, iclass 27, count 0 2006.201.21:29:39.36#ibcon#enter sib2, iclass 27, count 0 2006.201.21:29:39.36#ibcon#flushed, iclass 27, count 0 2006.201.21:29:39.36#ibcon#about to write, iclass 27, count 0 2006.201.21:29:39.36#ibcon#wrote, iclass 27, count 0 2006.201.21:29:39.36#ibcon#about to read 3, iclass 27, count 0 2006.201.21:29:39.40#ibcon#read 3, iclass 27, count 0 2006.201.21:29:39.40#ibcon#about to read 4, iclass 27, count 0 2006.201.21:29:39.40#ibcon#read 4, iclass 27, count 0 2006.201.21:29:39.40#ibcon#about to read 5, iclass 27, count 0 2006.201.21:29:39.40#ibcon#read 5, iclass 27, count 0 2006.201.21:29:39.40#ibcon#about to read 6, iclass 27, count 0 2006.201.21:29:39.40#ibcon#read 6, iclass 27, count 0 2006.201.21:29:39.40#ibcon#end of sib2, iclass 27, count 0 2006.201.21:29:39.40#ibcon#*after write, iclass 27, count 0 2006.201.21:29:39.40#ibcon#*before return 0, iclass 27, count 0 2006.201.21:29:39.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:39.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.21:29:39.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.21:29:39.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.21:29:39.40$vck44/vbbw=wide 2006.201.21:29:39.40#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.21:29:39.40#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.21:29:39.40#ibcon#ireg 8 cls_cnt 0 2006.201.21:29:39.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:29:39.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:29:39.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:29:39.46#ibcon#enter wrdev, iclass 29, count 0 2006.201.21:29:39.46#ibcon#first serial, iclass 29, count 0 2006.201.21:29:39.46#ibcon#enter sib2, iclass 29, count 0 2006.201.21:29:39.46#ibcon#flushed, iclass 29, count 0 2006.201.21:29:39.46#ibcon#about to write, iclass 29, count 0 2006.201.21:29:39.46#ibcon#wrote, iclass 29, count 0 2006.201.21:29:39.46#ibcon#about to read 3, iclass 29, count 0 2006.201.21:29:39.48#ibcon#read 3, iclass 29, count 0 2006.201.21:29:39.48#ibcon#about to read 4, iclass 29, count 0 2006.201.21:29:39.48#ibcon#read 4, iclass 29, count 0 2006.201.21:29:39.48#ibcon#about to read 5, iclass 29, count 0 2006.201.21:29:39.48#ibcon#read 5, iclass 29, count 0 2006.201.21:29:39.48#ibcon#about to read 6, iclass 29, count 0 2006.201.21:29:39.48#ibcon#read 6, iclass 29, count 0 2006.201.21:29:39.48#ibcon#end of sib2, iclass 29, count 0 2006.201.21:29:39.48#ibcon#*mode == 0, iclass 29, count 0 2006.201.21:29:39.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.21:29:39.48#ibcon#[27=BW32\r\n] 2006.201.21:29:39.48#ibcon#*before write, iclass 29, count 0 2006.201.21:29:39.48#ibcon#enter sib2, iclass 29, count 0 2006.201.21:29:39.48#ibcon#flushed, iclass 29, count 0 2006.201.21:29:39.48#ibcon#about to write, iclass 29, count 0 2006.201.21:29:39.48#ibcon#wrote, iclass 29, count 0 2006.201.21:29:39.48#ibcon#about to read 3, iclass 29, count 0 2006.201.21:29:39.51#ibcon#read 3, iclass 29, count 0 2006.201.21:29:39.51#ibcon#about to read 4, iclass 29, count 0 2006.201.21:29:39.51#ibcon#read 4, iclass 29, count 0 2006.201.21:29:39.51#ibcon#about to read 5, iclass 29, count 0 2006.201.21:29:39.51#ibcon#read 5, iclass 29, count 0 2006.201.21:29:39.51#ibcon#about to read 6, iclass 29, count 0 2006.201.21:29:39.51#ibcon#read 6, iclass 29, count 0 2006.201.21:29:39.51#ibcon#end of sib2, iclass 29, count 0 2006.201.21:29:39.51#ibcon#*after write, iclass 29, count 0 2006.201.21:29:39.51#ibcon#*before return 0, iclass 29, count 0 2006.201.21:29:39.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:29:39.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:29:39.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.21:29:39.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.21:29:39.51$setupk4/ifdk4 2006.201.21:29:39.51$ifdk4/lo= 2006.201.21:29:39.51$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.21:29:39.51$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.21:29:39.51$ifdk4/patch= 2006.201.21:29:39.51$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.21:29:39.51$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.21:29:39.51$setupk4/!*+20s 2006.201.21:29:46.00#abcon#<5=/04 1.8 3.0 20.041001002.1\r\n> 2006.201.21:29:46.02#abcon#{5=INTERFACE CLEAR} 2006.201.21:29:46.08#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:29:51.14#trakl#Source acquired 2006.201.21:29:53.14#flagr#flagr/antenna,acquired 2006.201.21:29:53.94$setupk4/"tpicd 2006.201.21:29:53.94$setupk4/echo=off 2006.201.21:29:53.94$setupk4/xlog=off 2006.201.21:29:53.94:!2006.201.21:36:00 2006.201.21:36:00.00:preob 2006.201.21:36:00.14/onsource/TRACKING 2006.201.21:36:00.14:!2006.201.21:36:10 2006.201.21:36:10.00:"tape 2006.201.21:36:10.00:"st=record 2006.201.21:36:10.00:data_valid=on 2006.201.21:36:10.00:midob 2006.201.21:36:11.14/onsource/TRACKING 2006.201.21:36:11.14/wx/20.05,1002.0,100 2006.201.21:36:11.22/cable/+6.4831E-03 2006.201.21:36:12.31/va/01,08,usb,yes,62,66 2006.201.21:36:12.31/va/02,07,usb,yes,67,68 2006.201.21:36:12.31/va/03,08,usb,yes,61,64 2006.201.21:36:12.31/va/04,07,usb,yes,69,72 2006.201.21:36:12.31/va/05,04,usb,yes,61,63 2006.201.21:36:12.31/va/06,05,usb,yes,62,62 2006.201.21:36:12.31/va/07,05,usb,yes,61,62 2006.201.21:36:12.31/va/08,04,usb,yes,60,70 2006.201.21:36:12.54/valo/01,524.99,yes,locked 2006.201.21:36:12.54/valo/02,534.99,yes,locked 2006.201.21:36:12.54/valo/03,564.99,yes,locked 2006.201.21:36:12.54/valo/04,624.99,yes,locked 2006.201.21:36:12.54/valo/05,734.99,yes,locked 2006.201.21:36:12.54/valo/06,814.99,yes,locked 2006.201.21:36:12.54/valo/07,864.99,yes,locked 2006.201.21:36:12.54/valo/08,884.99,yes,locked 2006.201.21:36:13.63/vb/01,04,usb,yes,34,31 2006.201.21:36:13.63/vb/02,05,usb,yes,32,32 2006.201.21:36:13.63/vb/03,04,usb,yes,33,36 2006.201.21:36:13.63/vb/04,05,usb,yes,34,32 2006.201.21:36:13.63/vb/05,04,usb,yes,30,32 2006.201.21:36:13.63/vb/06,04,usb,yes,35,31 2006.201.21:36:13.63/vb/07,04,usb,yes,34,34 2006.201.21:36:13.63/vb/08,04,usb,yes,32,35 2006.201.21:36:13.87/vblo/01,629.99,yes,locked 2006.201.21:36:13.87/vblo/02,634.99,yes,locked 2006.201.21:36:13.87/vblo/03,649.99,yes,locked 2006.201.21:36:13.87/vblo/04,679.99,yes,locked 2006.201.21:36:13.87/vblo/05,709.99,yes,locked 2006.201.21:36:13.87/vblo/06,719.99,yes,locked 2006.201.21:36:13.87/vblo/07,734.99,yes,locked 2006.201.21:36:13.87/vblo/08,744.99,yes,locked 2006.201.21:36:14.02/vabw/8 2006.201.21:36:14.17/vbbw/8 2006.201.21:36:14.27/xfe/off,on,15.5 2006.201.21:36:14.64/ifatt/23,28,28,28 2006.201.21:36:15.07/fmout-gps/S +4.58E-07 2006.201.21:36:15.14:!2006.201.21:45:40 2006.201.21:45:40.00:data_valid=off 2006.201.21:45:40.00:"et 2006.201.21:45:40.00:!+3s 2006.201.21:45:43.02:"tape 2006.201.21:45:43.02:postob 2006.201.21:45:43.21/cable/+6.4821E-03 2006.201.21:45:43.21/wx/20.05,1001.9,100 2006.201.21:45:43.28/fmout-gps/S +4.53E-07 2006.201.21:45:43.28:scan_name=201-2150,jd0607,210 2006.201.21:45:43.28:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.201.21:45:44.14#flagr#flagr/antenna,new-source 2006.201.21:45:44.14:checkk5 2006.201.21:45:44.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.21:45:44.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.21:45:45.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.21:45:45.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.21:45:46.36/chk_obsdata//k5ts1/T2012136??a.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.201.21:45:47.04/chk_obsdata//k5ts2/T2012136??b.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.201.21:45:47.71/chk_obsdata//k5ts3/T2012136??c.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.201.21:45:48.38/chk_obsdata//k5ts4/T2012136??d.dat file size is correct (nominal:2280MB, actual:2276MB). 2006.201.21:45:49.07/k5log//k5ts1_log_newline 2006.201.21:45:49.76/k5log//k5ts2_log_newline 2006.201.21:45:50.44/k5log//k5ts3_log_newline 2006.201.21:45:51.13/k5log//k5ts4_log_newline 2006.201.21:45:51.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.21:45:51.16:setupk4=1 2006.201.21:45:51.16$setupk4/echo=on 2006.201.21:45:51.16$setupk4/pcalon 2006.201.21:45:51.16$pcalon/"no phase cal control is implemented here 2006.201.21:45:51.16$setupk4/"tpicd=stop 2006.201.21:45:51.16$setupk4/"rec=synch_on 2006.201.21:45:51.16$setupk4/"rec_mode=128 2006.201.21:45:51.16$setupk4/!* 2006.201.21:45:51.16$setupk4/recpk4 2006.201.21:45:51.16$recpk4/recpatch= 2006.201.21:45:51.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.21:45:51.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.21:45:51.16$setupk4/vck44 2006.201.21:45:51.16$vck44/valo=1,524.99 2006.201.21:45:51.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.21:45:51.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.21:45:51.16#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:51.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:51.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:51.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:51.16#ibcon#enter wrdev, iclass 18, count 0 2006.201.21:45:51.16#ibcon#first serial, iclass 18, count 0 2006.201.21:45:51.16#ibcon#enter sib2, iclass 18, count 0 2006.201.21:45:51.16#ibcon#flushed, iclass 18, count 0 2006.201.21:45:51.16#ibcon#about to write, iclass 18, count 0 2006.201.21:45:51.16#ibcon#wrote, iclass 18, count 0 2006.201.21:45:51.16#ibcon#about to read 3, iclass 18, count 0 2006.201.21:45:51.18#ibcon#read 3, iclass 18, count 0 2006.201.21:45:51.18#ibcon#about to read 4, iclass 18, count 0 2006.201.21:45:51.18#ibcon#read 4, iclass 18, count 0 2006.201.21:45:51.18#ibcon#about to read 5, iclass 18, count 0 2006.201.21:45:51.18#ibcon#read 5, iclass 18, count 0 2006.201.21:45:51.18#ibcon#about to read 6, iclass 18, count 0 2006.201.21:45:51.18#ibcon#read 6, iclass 18, count 0 2006.201.21:45:51.18#ibcon#end of sib2, iclass 18, count 0 2006.201.21:45:51.18#ibcon#*mode == 0, iclass 18, count 0 2006.201.21:45:51.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.21:45:51.18#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.21:45:51.18#ibcon#*before write, iclass 18, count 0 2006.201.21:45:51.18#ibcon#enter sib2, iclass 18, count 0 2006.201.21:45:51.18#ibcon#flushed, iclass 18, count 0 2006.201.21:45:51.18#ibcon#about to write, iclass 18, count 0 2006.201.21:45:51.18#ibcon#wrote, iclass 18, count 0 2006.201.21:45:51.18#ibcon#about to read 3, iclass 18, count 0 2006.201.21:45:51.23#ibcon#read 3, iclass 18, count 0 2006.201.21:45:51.23#ibcon#about to read 4, iclass 18, count 0 2006.201.21:45:51.23#ibcon#read 4, iclass 18, count 0 2006.201.21:45:51.23#ibcon#about to read 5, iclass 18, count 0 2006.201.21:45:51.23#ibcon#read 5, iclass 18, count 0 2006.201.21:45:51.23#ibcon#about to read 6, iclass 18, count 0 2006.201.21:45:51.23#ibcon#read 6, iclass 18, count 0 2006.201.21:45:51.23#ibcon#end of sib2, iclass 18, count 0 2006.201.21:45:51.23#ibcon#*after write, iclass 18, count 0 2006.201.21:45:51.23#ibcon#*before return 0, iclass 18, count 0 2006.201.21:45:51.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:51.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:51.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.21:45:51.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.21:45:51.23$vck44/va=1,8 2006.201.21:45:51.23#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.21:45:51.23#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.21:45:51.23#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:51.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:51.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:51.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:51.23#ibcon#enter wrdev, iclass 20, count 2 2006.201.21:45:51.23#ibcon#first serial, iclass 20, count 2 2006.201.21:45:51.23#ibcon#enter sib2, iclass 20, count 2 2006.201.21:45:51.23#ibcon#flushed, iclass 20, count 2 2006.201.21:45:51.23#ibcon#about to write, iclass 20, count 2 2006.201.21:45:51.23#ibcon#wrote, iclass 20, count 2 2006.201.21:45:51.23#ibcon#about to read 3, iclass 20, count 2 2006.201.21:45:51.25#ibcon#read 3, iclass 20, count 2 2006.201.21:45:51.25#ibcon#about to read 4, iclass 20, count 2 2006.201.21:45:51.25#ibcon#read 4, iclass 20, count 2 2006.201.21:45:51.25#ibcon#about to read 5, iclass 20, count 2 2006.201.21:45:51.25#ibcon#read 5, iclass 20, count 2 2006.201.21:45:51.25#ibcon#about to read 6, iclass 20, count 2 2006.201.21:45:51.25#ibcon#read 6, iclass 20, count 2 2006.201.21:45:51.25#ibcon#end of sib2, iclass 20, count 2 2006.201.21:45:51.25#ibcon#*mode == 0, iclass 20, count 2 2006.201.21:45:51.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.21:45:51.25#ibcon#[25=AT01-08\r\n] 2006.201.21:45:51.25#ibcon#*before write, iclass 20, count 2 2006.201.21:45:51.25#ibcon#enter sib2, iclass 20, count 2 2006.201.21:45:51.25#ibcon#flushed, iclass 20, count 2 2006.201.21:45:51.25#ibcon#about to write, iclass 20, count 2 2006.201.21:45:51.25#ibcon#wrote, iclass 20, count 2 2006.201.21:45:51.25#ibcon#about to read 3, iclass 20, count 2 2006.201.21:45:51.28#ibcon#read 3, iclass 20, count 2 2006.201.21:45:51.28#ibcon#about to read 4, iclass 20, count 2 2006.201.21:45:51.28#ibcon#read 4, iclass 20, count 2 2006.201.21:45:51.28#ibcon#about to read 5, iclass 20, count 2 2006.201.21:45:51.28#ibcon#read 5, iclass 20, count 2 2006.201.21:45:51.28#ibcon#about to read 6, iclass 20, count 2 2006.201.21:45:51.28#ibcon#read 6, iclass 20, count 2 2006.201.21:45:51.28#ibcon#end of sib2, iclass 20, count 2 2006.201.21:45:51.28#ibcon#*after write, iclass 20, count 2 2006.201.21:45:51.28#ibcon#*before return 0, iclass 20, count 2 2006.201.21:45:51.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:51.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:51.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.21:45:51.28#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:51.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:51.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:51.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:51.40#ibcon#enter wrdev, iclass 20, count 0 2006.201.21:45:51.40#ibcon#first serial, iclass 20, count 0 2006.201.21:45:51.40#ibcon#enter sib2, iclass 20, count 0 2006.201.21:45:51.40#ibcon#flushed, iclass 20, count 0 2006.201.21:45:51.40#ibcon#about to write, iclass 20, count 0 2006.201.21:45:51.40#ibcon#wrote, iclass 20, count 0 2006.201.21:45:51.40#ibcon#about to read 3, iclass 20, count 0 2006.201.21:45:51.42#ibcon#read 3, iclass 20, count 0 2006.201.21:45:51.42#ibcon#about to read 4, iclass 20, count 0 2006.201.21:45:51.42#ibcon#read 4, iclass 20, count 0 2006.201.21:45:51.42#ibcon#about to read 5, iclass 20, count 0 2006.201.21:45:51.42#ibcon#read 5, iclass 20, count 0 2006.201.21:45:51.42#ibcon#about to read 6, iclass 20, count 0 2006.201.21:45:51.42#ibcon#read 6, iclass 20, count 0 2006.201.21:45:51.42#ibcon#end of sib2, iclass 20, count 0 2006.201.21:45:51.42#ibcon#*mode == 0, iclass 20, count 0 2006.201.21:45:51.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.21:45:51.42#ibcon#[25=USB\r\n] 2006.201.21:45:51.42#ibcon#*before write, iclass 20, count 0 2006.201.21:45:51.42#ibcon#enter sib2, iclass 20, count 0 2006.201.21:45:51.42#ibcon#flushed, iclass 20, count 0 2006.201.21:45:51.42#ibcon#about to write, iclass 20, count 0 2006.201.21:45:51.42#ibcon#wrote, iclass 20, count 0 2006.201.21:45:51.42#ibcon#about to read 3, iclass 20, count 0 2006.201.21:45:51.45#ibcon#read 3, iclass 20, count 0 2006.201.21:45:51.45#ibcon#about to read 4, iclass 20, count 0 2006.201.21:45:51.45#ibcon#read 4, iclass 20, count 0 2006.201.21:45:51.45#ibcon#about to read 5, iclass 20, count 0 2006.201.21:45:51.45#ibcon#read 5, iclass 20, count 0 2006.201.21:45:51.45#ibcon#about to read 6, iclass 20, count 0 2006.201.21:45:51.45#ibcon#read 6, iclass 20, count 0 2006.201.21:45:51.45#ibcon#end of sib2, iclass 20, count 0 2006.201.21:45:51.45#ibcon#*after write, iclass 20, count 0 2006.201.21:45:51.45#ibcon#*before return 0, iclass 20, count 0 2006.201.21:45:51.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:51.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:51.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.21:45:51.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.21:45:51.45$vck44/valo=2,534.99 2006.201.21:45:51.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.21:45:51.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.21:45:51.45#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:51.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:51.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:51.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:51.45#ibcon#enter wrdev, iclass 22, count 0 2006.201.21:45:51.45#ibcon#first serial, iclass 22, count 0 2006.201.21:45:51.45#ibcon#enter sib2, iclass 22, count 0 2006.201.21:45:51.45#ibcon#flushed, iclass 22, count 0 2006.201.21:45:51.45#ibcon#about to write, iclass 22, count 0 2006.201.21:45:51.45#ibcon#wrote, iclass 22, count 0 2006.201.21:45:51.45#ibcon#about to read 3, iclass 22, count 0 2006.201.21:45:51.47#ibcon#read 3, iclass 22, count 0 2006.201.21:45:51.47#ibcon#about to read 4, iclass 22, count 0 2006.201.21:45:51.47#ibcon#read 4, iclass 22, count 0 2006.201.21:45:51.47#ibcon#about to read 5, iclass 22, count 0 2006.201.21:45:51.47#ibcon#read 5, iclass 22, count 0 2006.201.21:45:51.47#ibcon#about to read 6, iclass 22, count 0 2006.201.21:45:51.47#ibcon#read 6, iclass 22, count 0 2006.201.21:45:51.47#ibcon#end of sib2, iclass 22, count 0 2006.201.21:45:51.47#ibcon#*mode == 0, iclass 22, count 0 2006.201.21:45:51.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.21:45:51.47#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.21:45:51.47#ibcon#*before write, iclass 22, count 0 2006.201.21:45:51.47#ibcon#enter sib2, iclass 22, count 0 2006.201.21:45:51.47#ibcon#flushed, iclass 22, count 0 2006.201.21:45:51.47#ibcon#about to write, iclass 22, count 0 2006.201.21:45:51.47#ibcon#wrote, iclass 22, count 0 2006.201.21:45:51.47#ibcon#about to read 3, iclass 22, count 0 2006.201.21:45:51.52#ibcon#read 3, iclass 22, count 0 2006.201.21:45:51.52#ibcon#about to read 4, iclass 22, count 0 2006.201.21:45:51.52#ibcon#read 4, iclass 22, count 0 2006.201.21:45:51.52#ibcon#about to read 5, iclass 22, count 0 2006.201.21:45:51.52#ibcon#read 5, iclass 22, count 0 2006.201.21:45:51.52#ibcon#about to read 6, iclass 22, count 0 2006.201.21:45:51.52#ibcon#read 6, iclass 22, count 0 2006.201.21:45:51.52#ibcon#end of sib2, iclass 22, count 0 2006.201.21:45:51.52#ibcon#*after write, iclass 22, count 0 2006.201.21:45:51.52#ibcon#*before return 0, iclass 22, count 0 2006.201.21:45:51.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:51.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:51.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.21:45:51.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.21:45:51.52$vck44/va=2,7 2006.201.21:45:51.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.21:45:51.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.21:45:51.52#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:51.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:51.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:51.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:51.57#ibcon#enter wrdev, iclass 24, count 2 2006.201.21:45:51.57#ibcon#first serial, iclass 24, count 2 2006.201.21:45:51.57#ibcon#enter sib2, iclass 24, count 2 2006.201.21:45:51.57#ibcon#flushed, iclass 24, count 2 2006.201.21:45:51.57#ibcon#about to write, iclass 24, count 2 2006.201.21:45:51.57#ibcon#wrote, iclass 24, count 2 2006.201.21:45:51.57#ibcon#about to read 3, iclass 24, count 2 2006.201.21:45:51.59#ibcon#read 3, iclass 24, count 2 2006.201.21:45:51.59#ibcon#about to read 4, iclass 24, count 2 2006.201.21:45:51.59#ibcon#read 4, iclass 24, count 2 2006.201.21:45:51.59#ibcon#about to read 5, iclass 24, count 2 2006.201.21:45:51.59#ibcon#read 5, iclass 24, count 2 2006.201.21:45:51.59#ibcon#about to read 6, iclass 24, count 2 2006.201.21:45:51.59#ibcon#read 6, iclass 24, count 2 2006.201.21:45:51.59#ibcon#end of sib2, iclass 24, count 2 2006.201.21:45:51.59#ibcon#*mode == 0, iclass 24, count 2 2006.201.21:45:51.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.21:45:51.59#ibcon#[25=AT02-07\r\n] 2006.201.21:45:51.59#ibcon#*before write, iclass 24, count 2 2006.201.21:45:51.59#ibcon#enter sib2, iclass 24, count 2 2006.201.21:45:51.59#ibcon#flushed, iclass 24, count 2 2006.201.21:45:51.59#ibcon#about to write, iclass 24, count 2 2006.201.21:45:51.59#ibcon#wrote, iclass 24, count 2 2006.201.21:45:51.59#ibcon#about to read 3, iclass 24, count 2 2006.201.21:45:51.62#ibcon#read 3, iclass 24, count 2 2006.201.21:45:51.62#ibcon#about to read 4, iclass 24, count 2 2006.201.21:45:51.62#ibcon#read 4, iclass 24, count 2 2006.201.21:45:51.62#ibcon#about to read 5, iclass 24, count 2 2006.201.21:45:51.62#ibcon#read 5, iclass 24, count 2 2006.201.21:45:51.62#ibcon#about to read 6, iclass 24, count 2 2006.201.21:45:51.62#ibcon#read 6, iclass 24, count 2 2006.201.21:45:51.62#ibcon#end of sib2, iclass 24, count 2 2006.201.21:45:51.62#ibcon#*after write, iclass 24, count 2 2006.201.21:45:51.62#ibcon#*before return 0, iclass 24, count 2 2006.201.21:45:51.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:51.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:51.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.21:45:51.62#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:51.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:51.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:51.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:51.74#ibcon#enter wrdev, iclass 24, count 0 2006.201.21:45:51.74#ibcon#first serial, iclass 24, count 0 2006.201.21:45:51.74#ibcon#enter sib2, iclass 24, count 0 2006.201.21:45:51.74#ibcon#flushed, iclass 24, count 0 2006.201.21:45:51.74#ibcon#about to write, iclass 24, count 0 2006.201.21:45:51.74#ibcon#wrote, iclass 24, count 0 2006.201.21:45:51.74#ibcon#about to read 3, iclass 24, count 0 2006.201.21:45:51.76#ibcon#read 3, iclass 24, count 0 2006.201.21:45:51.76#ibcon#about to read 4, iclass 24, count 0 2006.201.21:45:51.76#ibcon#read 4, iclass 24, count 0 2006.201.21:45:51.76#ibcon#about to read 5, iclass 24, count 0 2006.201.21:45:51.76#ibcon#read 5, iclass 24, count 0 2006.201.21:45:51.76#ibcon#about to read 6, iclass 24, count 0 2006.201.21:45:51.76#ibcon#read 6, iclass 24, count 0 2006.201.21:45:51.76#ibcon#end of sib2, iclass 24, count 0 2006.201.21:45:51.76#ibcon#*mode == 0, iclass 24, count 0 2006.201.21:45:51.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.21:45:51.76#ibcon#[25=USB\r\n] 2006.201.21:45:51.76#ibcon#*before write, iclass 24, count 0 2006.201.21:45:51.76#ibcon#enter sib2, iclass 24, count 0 2006.201.21:45:51.76#ibcon#flushed, iclass 24, count 0 2006.201.21:45:51.76#ibcon#about to write, iclass 24, count 0 2006.201.21:45:51.76#ibcon#wrote, iclass 24, count 0 2006.201.21:45:51.76#ibcon#about to read 3, iclass 24, count 0 2006.201.21:45:51.79#ibcon#read 3, iclass 24, count 0 2006.201.21:45:51.79#ibcon#about to read 4, iclass 24, count 0 2006.201.21:45:51.79#ibcon#read 4, iclass 24, count 0 2006.201.21:45:51.79#ibcon#about to read 5, iclass 24, count 0 2006.201.21:45:51.79#ibcon#read 5, iclass 24, count 0 2006.201.21:45:51.79#ibcon#about to read 6, iclass 24, count 0 2006.201.21:45:51.79#ibcon#read 6, iclass 24, count 0 2006.201.21:45:51.79#ibcon#end of sib2, iclass 24, count 0 2006.201.21:45:51.79#ibcon#*after write, iclass 24, count 0 2006.201.21:45:51.79#ibcon#*before return 0, iclass 24, count 0 2006.201.21:45:51.79#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:51.79#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:51.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.21:45:51.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.21:45:51.79$vck44/valo=3,564.99 2006.201.21:45:51.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.21:45:51.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.21:45:51.79#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:51.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:51.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:51.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:51.79#ibcon#enter wrdev, iclass 26, count 0 2006.201.21:45:51.79#ibcon#first serial, iclass 26, count 0 2006.201.21:45:51.79#ibcon#enter sib2, iclass 26, count 0 2006.201.21:45:51.79#ibcon#flushed, iclass 26, count 0 2006.201.21:45:51.79#ibcon#about to write, iclass 26, count 0 2006.201.21:45:51.79#ibcon#wrote, iclass 26, count 0 2006.201.21:45:51.79#ibcon#about to read 3, iclass 26, count 0 2006.201.21:45:51.81#ibcon#read 3, iclass 26, count 0 2006.201.21:45:51.81#ibcon#about to read 4, iclass 26, count 0 2006.201.21:45:51.81#ibcon#read 4, iclass 26, count 0 2006.201.21:45:51.81#ibcon#about to read 5, iclass 26, count 0 2006.201.21:45:51.81#ibcon#read 5, iclass 26, count 0 2006.201.21:45:51.81#ibcon#about to read 6, iclass 26, count 0 2006.201.21:45:51.81#ibcon#read 6, iclass 26, count 0 2006.201.21:45:51.81#ibcon#end of sib2, iclass 26, count 0 2006.201.21:45:51.81#ibcon#*mode == 0, iclass 26, count 0 2006.201.21:45:51.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.21:45:51.81#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.21:45:51.81#ibcon#*before write, iclass 26, count 0 2006.201.21:45:51.81#ibcon#enter sib2, iclass 26, count 0 2006.201.21:45:51.81#ibcon#flushed, iclass 26, count 0 2006.201.21:45:51.81#ibcon#about to write, iclass 26, count 0 2006.201.21:45:51.81#ibcon#wrote, iclass 26, count 0 2006.201.21:45:51.81#ibcon#about to read 3, iclass 26, count 0 2006.201.21:45:51.85#ibcon#read 3, iclass 26, count 0 2006.201.21:45:51.85#ibcon#about to read 4, iclass 26, count 0 2006.201.21:45:51.85#ibcon#read 4, iclass 26, count 0 2006.201.21:45:51.85#ibcon#about to read 5, iclass 26, count 0 2006.201.21:45:51.85#ibcon#read 5, iclass 26, count 0 2006.201.21:45:51.85#ibcon#about to read 6, iclass 26, count 0 2006.201.21:45:51.85#ibcon#read 6, iclass 26, count 0 2006.201.21:45:51.85#ibcon#end of sib2, iclass 26, count 0 2006.201.21:45:51.85#ibcon#*after write, iclass 26, count 0 2006.201.21:45:51.85#ibcon#*before return 0, iclass 26, count 0 2006.201.21:45:51.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:51.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:51.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.21:45:51.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.21:45:51.85$vck44/va=3,8 2006.201.21:45:51.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.21:45:51.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.21:45:51.85#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:51.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:51.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:51.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:51.91#ibcon#enter wrdev, iclass 28, count 2 2006.201.21:45:51.91#ibcon#first serial, iclass 28, count 2 2006.201.21:45:51.91#ibcon#enter sib2, iclass 28, count 2 2006.201.21:45:51.91#ibcon#flushed, iclass 28, count 2 2006.201.21:45:51.91#ibcon#about to write, iclass 28, count 2 2006.201.21:45:51.91#ibcon#wrote, iclass 28, count 2 2006.201.21:45:51.91#ibcon#about to read 3, iclass 28, count 2 2006.201.21:45:51.93#ibcon#read 3, iclass 28, count 2 2006.201.21:45:51.93#ibcon#about to read 4, iclass 28, count 2 2006.201.21:45:51.93#ibcon#read 4, iclass 28, count 2 2006.201.21:45:51.93#ibcon#about to read 5, iclass 28, count 2 2006.201.21:45:51.93#ibcon#read 5, iclass 28, count 2 2006.201.21:45:51.93#ibcon#about to read 6, iclass 28, count 2 2006.201.21:45:51.93#ibcon#read 6, iclass 28, count 2 2006.201.21:45:51.93#ibcon#end of sib2, iclass 28, count 2 2006.201.21:45:51.93#ibcon#*mode == 0, iclass 28, count 2 2006.201.21:45:51.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.21:45:51.93#ibcon#[25=AT03-08\r\n] 2006.201.21:45:51.93#ibcon#*before write, iclass 28, count 2 2006.201.21:45:51.93#ibcon#enter sib2, iclass 28, count 2 2006.201.21:45:51.93#ibcon#flushed, iclass 28, count 2 2006.201.21:45:51.93#ibcon#about to write, iclass 28, count 2 2006.201.21:45:51.93#ibcon#wrote, iclass 28, count 2 2006.201.21:45:51.93#ibcon#about to read 3, iclass 28, count 2 2006.201.21:45:51.96#ibcon#read 3, iclass 28, count 2 2006.201.21:45:51.96#ibcon#about to read 4, iclass 28, count 2 2006.201.21:45:51.96#ibcon#read 4, iclass 28, count 2 2006.201.21:45:51.96#ibcon#about to read 5, iclass 28, count 2 2006.201.21:45:51.96#ibcon#read 5, iclass 28, count 2 2006.201.21:45:51.96#ibcon#about to read 6, iclass 28, count 2 2006.201.21:45:51.96#ibcon#read 6, iclass 28, count 2 2006.201.21:45:51.96#ibcon#end of sib2, iclass 28, count 2 2006.201.21:45:51.96#ibcon#*after write, iclass 28, count 2 2006.201.21:45:51.96#ibcon#*before return 0, iclass 28, count 2 2006.201.21:45:51.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:51.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:51.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.21:45:51.96#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:51.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:52.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:52.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:52.08#ibcon#enter wrdev, iclass 28, count 0 2006.201.21:45:52.08#ibcon#first serial, iclass 28, count 0 2006.201.21:45:52.08#ibcon#enter sib2, iclass 28, count 0 2006.201.21:45:52.08#ibcon#flushed, iclass 28, count 0 2006.201.21:45:52.08#ibcon#about to write, iclass 28, count 0 2006.201.21:45:52.08#ibcon#wrote, iclass 28, count 0 2006.201.21:45:52.08#ibcon#about to read 3, iclass 28, count 0 2006.201.21:45:52.10#ibcon#read 3, iclass 28, count 0 2006.201.21:45:52.10#ibcon#about to read 4, iclass 28, count 0 2006.201.21:45:52.10#ibcon#read 4, iclass 28, count 0 2006.201.21:45:52.10#ibcon#about to read 5, iclass 28, count 0 2006.201.21:45:52.10#ibcon#read 5, iclass 28, count 0 2006.201.21:45:52.10#ibcon#about to read 6, iclass 28, count 0 2006.201.21:45:52.10#ibcon#read 6, iclass 28, count 0 2006.201.21:45:52.10#ibcon#end of sib2, iclass 28, count 0 2006.201.21:45:52.10#ibcon#*mode == 0, iclass 28, count 0 2006.201.21:45:52.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.21:45:52.10#ibcon#[25=USB\r\n] 2006.201.21:45:52.10#ibcon#*before write, iclass 28, count 0 2006.201.21:45:52.10#ibcon#enter sib2, iclass 28, count 0 2006.201.21:45:52.10#ibcon#flushed, iclass 28, count 0 2006.201.21:45:52.10#ibcon#about to write, iclass 28, count 0 2006.201.21:45:52.10#ibcon#wrote, iclass 28, count 0 2006.201.21:45:52.10#ibcon#about to read 3, iclass 28, count 0 2006.201.21:45:52.13#ibcon#read 3, iclass 28, count 0 2006.201.21:45:52.13#ibcon#about to read 4, iclass 28, count 0 2006.201.21:45:52.13#ibcon#read 4, iclass 28, count 0 2006.201.21:45:52.13#ibcon#about to read 5, iclass 28, count 0 2006.201.21:45:52.13#ibcon#read 5, iclass 28, count 0 2006.201.21:45:52.13#ibcon#about to read 6, iclass 28, count 0 2006.201.21:45:52.13#ibcon#read 6, iclass 28, count 0 2006.201.21:45:52.13#ibcon#end of sib2, iclass 28, count 0 2006.201.21:45:52.13#ibcon#*after write, iclass 28, count 0 2006.201.21:45:52.13#ibcon#*before return 0, iclass 28, count 0 2006.201.21:45:52.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:52.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:52.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.21:45:52.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.21:45:52.13$vck44/valo=4,624.99 2006.201.21:45:52.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.21:45:52.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.21:45:52.13#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:52.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:52.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:52.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:52.13#ibcon#enter wrdev, iclass 30, count 0 2006.201.21:45:52.13#ibcon#first serial, iclass 30, count 0 2006.201.21:45:52.13#ibcon#enter sib2, iclass 30, count 0 2006.201.21:45:52.13#ibcon#flushed, iclass 30, count 0 2006.201.21:45:52.13#ibcon#about to write, iclass 30, count 0 2006.201.21:45:52.13#ibcon#wrote, iclass 30, count 0 2006.201.21:45:52.13#ibcon#about to read 3, iclass 30, count 0 2006.201.21:45:52.15#ibcon#read 3, iclass 30, count 0 2006.201.21:45:52.15#ibcon#about to read 4, iclass 30, count 0 2006.201.21:45:52.15#ibcon#read 4, iclass 30, count 0 2006.201.21:45:52.15#ibcon#about to read 5, iclass 30, count 0 2006.201.21:45:52.15#ibcon#read 5, iclass 30, count 0 2006.201.21:45:52.15#ibcon#about to read 6, iclass 30, count 0 2006.201.21:45:52.15#ibcon#read 6, iclass 30, count 0 2006.201.21:45:52.15#ibcon#end of sib2, iclass 30, count 0 2006.201.21:45:52.15#ibcon#*mode == 0, iclass 30, count 0 2006.201.21:45:52.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.21:45:52.15#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.21:45:52.15#ibcon#*before write, iclass 30, count 0 2006.201.21:45:52.15#ibcon#enter sib2, iclass 30, count 0 2006.201.21:45:52.15#ibcon#flushed, iclass 30, count 0 2006.201.21:45:52.15#ibcon#about to write, iclass 30, count 0 2006.201.21:45:52.15#ibcon#wrote, iclass 30, count 0 2006.201.21:45:52.15#ibcon#about to read 3, iclass 30, count 0 2006.201.21:45:52.19#ibcon#read 3, iclass 30, count 0 2006.201.21:45:52.19#ibcon#about to read 4, iclass 30, count 0 2006.201.21:45:52.19#ibcon#read 4, iclass 30, count 0 2006.201.21:45:52.19#ibcon#about to read 5, iclass 30, count 0 2006.201.21:45:52.19#ibcon#read 5, iclass 30, count 0 2006.201.21:45:52.19#ibcon#about to read 6, iclass 30, count 0 2006.201.21:45:52.19#ibcon#read 6, iclass 30, count 0 2006.201.21:45:52.19#ibcon#end of sib2, iclass 30, count 0 2006.201.21:45:52.19#ibcon#*after write, iclass 30, count 0 2006.201.21:45:52.19#ibcon#*before return 0, iclass 30, count 0 2006.201.21:45:52.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:52.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:52.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.21:45:52.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.21:45:52.19$vck44/va=4,7 2006.201.21:45:52.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.21:45:52.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.21:45:52.19#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:52.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:52.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:52.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:52.25#ibcon#enter wrdev, iclass 32, count 2 2006.201.21:45:52.25#ibcon#first serial, iclass 32, count 2 2006.201.21:45:52.25#ibcon#enter sib2, iclass 32, count 2 2006.201.21:45:52.25#ibcon#flushed, iclass 32, count 2 2006.201.21:45:52.25#ibcon#about to write, iclass 32, count 2 2006.201.21:45:52.25#ibcon#wrote, iclass 32, count 2 2006.201.21:45:52.25#ibcon#about to read 3, iclass 32, count 2 2006.201.21:45:52.27#ibcon#read 3, iclass 32, count 2 2006.201.21:45:52.27#ibcon#about to read 4, iclass 32, count 2 2006.201.21:45:52.27#ibcon#read 4, iclass 32, count 2 2006.201.21:45:52.27#ibcon#about to read 5, iclass 32, count 2 2006.201.21:45:52.27#ibcon#read 5, iclass 32, count 2 2006.201.21:45:52.27#ibcon#about to read 6, iclass 32, count 2 2006.201.21:45:52.27#ibcon#read 6, iclass 32, count 2 2006.201.21:45:52.27#ibcon#end of sib2, iclass 32, count 2 2006.201.21:45:52.27#ibcon#*mode == 0, iclass 32, count 2 2006.201.21:45:52.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.21:45:52.27#ibcon#[25=AT04-07\r\n] 2006.201.21:45:52.27#ibcon#*before write, iclass 32, count 2 2006.201.21:45:52.27#ibcon#enter sib2, iclass 32, count 2 2006.201.21:45:52.27#ibcon#flushed, iclass 32, count 2 2006.201.21:45:52.27#ibcon#about to write, iclass 32, count 2 2006.201.21:45:52.27#ibcon#wrote, iclass 32, count 2 2006.201.21:45:52.27#ibcon#about to read 3, iclass 32, count 2 2006.201.21:45:52.28#abcon#<5=/05 1.3 2.3 20.051001001.9\r\n> 2006.201.21:45:52.30#abcon#{5=INTERFACE CLEAR} 2006.201.21:45:52.30#ibcon#read 3, iclass 32, count 2 2006.201.21:45:52.30#ibcon#about to read 4, iclass 32, count 2 2006.201.21:45:52.30#ibcon#read 4, iclass 32, count 2 2006.201.21:45:52.30#ibcon#about to read 5, iclass 32, count 2 2006.201.21:45:52.30#ibcon#read 5, iclass 32, count 2 2006.201.21:45:52.30#ibcon#about to read 6, iclass 32, count 2 2006.201.21:45:52.30#ibcon#read 6, iclass 32, count 2 2006.201.21:45:52.30#ibcon#end of sib2, iclass 32, count 2 2006.201.21:45:52.30#ibcon#*after write, iclass 32, count 2 2006.201.21:45:52.30#ibcon#*before return 0, iclass 32, count 2 2006.201.21:45:52.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:52.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:52.30#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.21:45:52.30#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:52.30#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:52.36#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:45:52.42#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:52.42#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:52.42#ibcon#enter wrdev, iclass 32, count 0 2006.201.21:45:52.42#ibcon#first serial, iclass 32, count 0 2006.201.21:45:52.42#ibcon#enter sib2, iclass 32, count 0 2006.201.21:45:52.42#ibcon#flushed, iclass 32, count 0 2006.201.21:45:52.42#ibcon#about to write, iclass 32, count 0 2006.201.21:45:52.42#ibcon#wrote, iclass 32, count 0 2006.201.21:45:52.42#ibcon#about to read 3, iclass 32, count 0 2006.201.21:45:52.44#ibcon#read 3, iclass 32, count 0 2006.201.21:45:52.44#ibcon#about to read 4, iclass 32, count 0 2006.201.21:45:52.44#ibcon#read 4, iclass 32, count 0 2006.201.21:45:52.44#ibcon#about to read 5, iclass 32, count 0 2006.201.21:45:52.44#ibcon#read 5, iclass 32, count 0 2006.201.21:45:52.44#ibcon#about to read 6, iclass 32, count 0 2006.201.21:45:52.44#ibcon#read 6, iclass 32, count 0 2006.201.21:45:52.44#ibcon#end of sib2, iclass 32, count 0 2006.201.21:45:52.44#ibcon#*mode == 0, iclass 32, count 0 2006.201.21:45:52.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.21:45:52.44#ibcon#[25=USB\r\n] 2006.201.21:45:52.44#ibcon#*before write, iclass 32, count 0 2006.201.21:45:52.44#ibcon#enter sib2, iclass 32, count 0 2006.201.21:45:52.44#ibcon#flushed, iclass 32, count 0 2006.201.21:45:52.44#ibcon#about to write, iclass 32, count 0 2006.201.21:45:52.44#ibcon#wrote, iclass 32, count 0 2006.201.21:45:52.44#ibcon#about to read 3, iclass 32, count 0 2006.201.21:45:52.47#ibcon#read 3, iclass 32, count 0 2006.201.21:45:52.47#ibcon#about to read 4, iclass 32, count 0 2006.201.21:45:52.47#ibcon#read 4, iclass 32, count 0 2006.201.21:45:52.47#ibcon#about to read 5, iclass 32, count 0 2006.201.21:45:52.47#ibcon#read 5, iclass 32, count 0 2006.201.21:45:52.47#ibcon#about to read 6, iclass 32, count 0 2006.201.21:45:52.47#ibcon#read 6, iclass 32, count 0 2006.201.21:45:52.47#ibcon#end of sib2, iclass 32, count 0 2006.201.21:45:52.47#ibcon#*after write, iclass 32, count 0 2006.201.21:45:52.47#ibcon#*before return 0, iclass 32, count 0 2006.201.21:45:52.47#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:52.47#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:52.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.21:45:52.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.21:45:52.47$vck44/valo=5,734.99 2006.201.21:45:52.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.21:45:52.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.21:45:52.47#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:52.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:52.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:52.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:52.47#ibcon#enter wrdev, iclass 38, count 0 2006.201.21:45:52.47#ibcon#first serial, iclass 38, count 0 2006.201.21:45:52.47#ibcon#enter sib2, iclass 38, count 0 2006.201.21:45:52.47#ibcon#flushed, iclass 38, count 0 2006.201.21:45:52.47#ibcon#about to write, iclass 38, count 0 2006.201.21:45:52.47#ibcon#wrote, iclass 38, count 0 2006.201.21:45:52.47#ibcon#about to read 3, iclass 38, count 0 2006.201.21:45:52.49#ibcon#read 3, iclass 38, count 0 2006.201.21:45:52.49#ibcon#about to read 4, iclass 38, count 0 2006.201.21:45:52.49#ibcon#read 4, iclass 38, count 0 2006.201.21:45:52.49#ibcon#about to read 5, iclass 38, count 0 2006.201.21:45:52.49#ibcon#read 5, iclass 38, count 0 2006.201.21:45:52.49#ibcon#about to read 6, iclass 38, count 0 2006.201.21:45:52.49#ibcon#read 6, iclass 38, count 0 2006.201.21:45:52.49#ibcon#end of sib2, iclass 38, count 0 2006.201.21:45:52.49#ibcon#*mode == 0, iclass 38, count 0 2006.201.21:45:52.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.21:45:52.49#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.21:45:52.49#ibcon#*before write, iclass 38, count 0 2006.201.21:45:52.49#ibcon#enter sib2, iclass 38, count 0 2006.201.21:45:52.49#ibcon#flushed, iclass 38, count 0 2006.201.21:45:52.49#ibcon#about to write, iclass 38, count 0 2006.201.21:45:52.49#ibcon#wrote, iclass 38, count 0 2006.201.21:45:52.49#ibcon#about to read 3, iclass 38, count 0 2006.201.21:45:52.53#ibcon#read 3, iclass 38, count 0 2006.201.21:45:52.53#ibcon#about to read 4, iclass 38, count 0 2006.201.21:45:52.53#ibcon#read 4, iclass 38, count 0 2006.201.21:45:52.53#ibcon#about to read 5, iclass 38, count 0 2006.201.21:45:52.53#ibcon#read 5, iclass 38, count 0 2006.201.21:45:52.53#ibcon#about to read 6, iclass 38, count 0 2006.201.21:45:52.53#ibcon#read 6, iclass 38, count 0 2006.201.21:45:52.53#ibcon#end of sib2, iclass 38, count 0 2006.201.21:45:52.53#ibcon#*after write, iclass 38, count 0 2006.201.21:45:52.53#ibcon#*before return 0, iclass 38, count 0 2006.201.21:45:52.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:52.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:52.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.21:45:52.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.21:45:52.53$vck44/va=5,4 2006.201.21:45:52.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.21:45:52.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.21:45:52.53#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:52.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:52.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:52.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:52.59#ibcon#enter wrdev, iclass 40, count 2 2006.201.21:45:52.59#ibcon#first serial, iclass 40, count 2 2006.201.21:45:52.59#ibcon#enter sib2, iclass 40, count 2 2006.201.21:45:52.59#ibcon#flushed, iclass 40, count 2 2006.201.21:45:52.59#ibcon#about to write, iclass 40, count 2 2006.201.21:45:52.59#ibcon#wrote, iclass 40, count 2 2006.201.21:45:52.59#ibcon#about to read 3, iclass 40, count 2 2006.201.21:45:52.61#ibcon#read 3, iclass 40, count 2 2006.201.21:45:52.61#ibcon#about to read 4, iclass 40, count 2 2006.201.21:45:52.61#ibcon#read 4, iclass 40, count 2 2006.201.21:45:52.61#ibcon#about to read 5, iclass 40, count 2 2006.201.21:45:52.61#ibcon#read 5, iclass 40, count 2 2006.201.21:45:52.61#ibcon#about to read 6, iclass 40, count 2 2006.201.21:45:52.61#ibcon#read 6, iclass 40, count 2 2006.201.21:45:52.61#ibcon#end of sib2, iclass 40, count 2 2006.201.21:45:52.61#ibcon#*mode == 0, iclass 40, count 2 2006.201.21:45:52.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.21:45:52.61#ibcon#[25=AT05-04\r\n] 2006.201.21:45:52.61#ibcon#*before write, iclass 40, count 2 2006.201.21:45:52.61#ibcon#enter sib2, iclass 40, count 2 2006.201.21:45:52.61#ibcon#flushed, iclass 40, count 2 2006.201.21:45:52.61#ibcon#about to write, iclass 40, count 2 2006.201.21:45:52.61#ibcon#wrote, iclass 40, count 2 2006.201.21:45:52.61#ibcon#about to read 3, iclass 40, count 2 2006.201.21:45:52.64#ibcon#read 3, iclass 40, count 2 2006.201.21:45:52.64#ibcon#about to read 4, iclass 40, count 2 2006.201.21:45:52.64#ibcon#read 4, iclass 40, count 2 2006.201.21:45:52.64#ibcon#about to read 5, iclass 40, count 2 2006.201.21:45:52.64#ibcon#read 5, iclass 40, count 2 2006.201.21:45:52.64#ibcon#about to read 6, iclass 40, count 2 2006.201.21:45:52.64#ibcon#read 6, iclass 40, count 2 2006.201.21:45:52.64#ibcon#end of sib2, iclass 40, count 2 2006.201.21:45:52.64#ibcon#*after write, iclass 40, count 2 2006.201.21:45:52.64#ibcon#*before return 0, iclass 40, count 2 2006.201.21:45:52.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:52.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:52.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.21:45:52.64#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:52.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:52.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:52.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:52.76#ibcon#enter wrdev, iclass 40, count 0 2006.201.21:45:52.76#ibcon#first serial, iclass 40, count 0 2006.201.21:45:52.76#ibcon#enter sib2, iclass 40, count 0 2006.201.21:45:52.76#ibcon#flushed, iclass 40, count 0 2006.201.21:45:52.76#ibcon#about to write, iclass 40, count 0 2006.201.21:45:52.76#ibcon#wrote, iclass 40, count 0 2006.201.21:45:52.76#ibcon#about to read 3, iclass 40, count 0 2006.201.21:45:52.78#ibcon#read 3, iclass 40, count 0 2006.201.21:45:52.78#ibcon#about to read 4, iclass 40, count 0 2006.201.21:45:52.78#ibcon#read 4, iclass 40, count 0 2006.201.21:45:52.78#ibcon#about to read 5, iclass 40, count 0 2006.201.21:45:52.78#ibcon#read 5, iclass 40, count 0 2006.201.21:45:52.78#ibcon#about to read 6, iclass 40, count 0 2006.201.21:45:52.78#ibcon#read 6, iclass 40, count 0 2006.201.21:45:52.78#ibcon#end of sib2, iclass 40, count 0 2006.201.21:45:52.78#ibcon#*mode == 0, iclass 40, count 0 2006.201.21:45:52.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.21:45:52.78#ibcon#[25=USB\r\n] 2006.201.21:45:52.78#ibcon#*before write, iclass 40, count 0 2006.201.21:45:52.78#ibcon#enter sib2, iclass 40, count 0 2006.201.21:45:52.78#ibcon#flushed, iclass 40, count 0 2006.201.21:45:52.78#ibcon#about to write, iclass 40, count 0 2006.201.21:45:52.78#ibcon#wrote, iclass 40, count 0 2006.201.21:45:52.78#ibcon#about to read 3, iclass 40, count 0 2006.201.21:45:52.81#ibcon#read 3, iclass 40, count 0 2006.201.21:45:52.81#ibcon#about to read 4, iclass 40, count 0 2006.201.21:45:52.81#ibcon#read 4, iclass 40, count 0 2006.201.21:45:52.81#ibcon#about to read 5, iclass 40, count 0 2006.201.21:45:52.81#ibcon#read 5, iclass 40, count 0 2006.201.21:45:52.81#ibcon#about to read 6, iclass 40, count 0 2006.201.21:45:52.81#ibcon#read 6, iclass 40, count 0 2006.201.21:45:52.81#ibcon#end of sib2, iclass 40, count 0 2006.201.21:45:52.81#ibcon#*after write, iclass 40, count 0 2006.201.21:45:52.81#ibcon#*before return 0, iclass 40, count 0 2006.201.21:45:52.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:52.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:52.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.21:45:52.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.21:45:52.81$vck44/valo=6,814.99 2006.201.21:45:52.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.21:45:52.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.21:45:52.81#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:52.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:52.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:52.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:52.81#ibcon#enter wrdev, iclass 4, count 0 2006.201.21:45:52.81#ibcon#first serial, iclass 4, count 0 2006.201.21:45:52.81#ibcon#enter sib2, iclass 4, count 0 2006.201.21:45:52.81#ibcon#flushed, iclass 4, count 0 2006.201.21:45:52.81#ibcon#about to write, iclass 4, count 0 2006.201.21:45:52.81#ibcon#wrote, iclass 4, count 0 2006.201.21:45:52.81#ibcon#about to read 3, iclass 4, count 0 2006.201.21:45:52.83#ibcon#read 3, iclass 4, count 0 2006.201.21:45:52.83#ibcon#about to read 4, iclass 4, count 0 2006.201.21:45:52.83#ibcon#read 4, iclass 4, count 0 2006.201.21:45:52.83#ibcon#about to read 5, iclass 4, count 0 2006.201.21:45:52.83#ibcon#read 5, iclass 4, count 0 2006.201.21:45:52.83#ibcon#about to read 6, iclass 4, count 0 2006.201.21:45:52.83#ibcon#read 6, iclass 4, count 0 2006.201.21:45:52.83#ibcon#end of sib2, iclass 4, count 0 2006.201.21:45:52.83#ibcon#*mode == 0, iclass 4, count 0 2006.201.21:45:52.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.21:45:52.83#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.21:45:52.83#ibcon#*before write, iclass 4, count 0 2006.201.21:45:52.83#ibcon#enter sib2, iclass 4, count 0 2006.201.21:45:52.83#ibcon#flushed, iclass 4, count 0 2006.201.21:45:52.83#ibcon#about to write, iclass 4, count 0 2006.201.21:45:52.83#ibcon#wrote, iclass 4, count 0 2006.201.21:45:52.83#ibcon#about to read 3, iclass 4, count 0 2006.201.21:45:52.87#ibcon#read 3, iclass 4, count 0 2006.201.21:45:52.87#ibcon#about to read 4, iclass 4, count 0 2006.201.21:45:52.87#ibcon#read 4, iclass 4, count 0 2006.201.21:45:52.87#ibcon#about to read 5, iclass 4, count 0 2006.201.21:45:52.87#ibcon#read 5, iclass 4, count 0 2006.201.21:45:52.87#ibcon#about to read 6, iclass 4, count 0 2006.201.21:45:52.87#ibcon#read 6, iclass 4, count 0 2006.201.21:45:52.87#ibcon#end of sib2, iclass 4, count 0 2006.201.21:45:52.87#ibcon#*after write, iclass 4, count 0 2006.201.21:45:52.87#ibcon#*before return 0, iclass 4, count 0 2006.201.21:45:52.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:52.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:52.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.21:45:52.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.21:45:52.87$vck44/va=6,5 2006.201.21:45:52.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.21:45:52.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.21:45:52.87#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:52.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:52.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:52.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:52.93#ibcon#enter wrdev, iclass 6, count 2 2006.201.21:45:52.93#ibcon#first serial, iclass 6, count 2 2006.201.21:45:52.93#ibcon#enter sib2, iclass 6, count 2 2006.201.21:45:52.93#ibcon#flushed, iclass 6, count 2 2006.201.21:45:52.93#ibcon#about to write, iclass 6, count 2 2006.201.21:45:52.93#ibcon#wrote, iclass 6, count 2 2006.201.21:45:52.93#ibcon#about to read 3, iclass 6, count 2 2006.201.21:45:52.95#ibcon#read 3, iclass 6, count 2 2006.201.21:45:52.95#ibcon#about to read 4, iclass 6, count 2 2006.201.21:45:52.95#ibcon#read 4, iclass 6, count 2 2006.201.21:45:52.95#ibcon#about to read 5, iclass 6, count 2 2006.201.21:45:52.95#ibcon#read 5, iclass 6, count 2 2006.201.21:45:52.95#ibcon#about to read 6, iclass 6, count 2 2006.201.21:45:52.95#ibcon#read 6, iclass 6, count 2 2006.201.21:45:52.95#ibcon#end of sib2, iclass 6, count 2 2006.201.21:45:52.95#ibcon#*mode == 0, iclass 6, count 2 2006.201.21:45:52.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.21:45:52.95#ibcon#[25=AT06-05\r\n] 2006.201.21:45:52.95#ibcon#*before write, iclass 6, count 2 2006.201.21:45:52.95#ibcon#enter sib2, iclass 6, count 2 2006.201.21:45:52.95#ibcon#flushed, iclass 6, count 2 2006.201.21:45:52.95#ibcon#about to write, iclass 6, count 2 2006.201.21:45:52.95#ibcon#wrote, iclass 6, count 2 2006.201.21:45:52.95#ibcon#about to read 3, iclass 6, count 2 2006.201.21:45:52.98#ibcon#read 3, iclass 6, count 2 2006.201.21:45:52.98#ibcon#about to read 4, iclass 6, count 2 2006.201.21:45:52.98#ibcon#read 4, iclass 6, count 2 2006.201.21:45:52.98#ibcon#about to read 5, iclass 6, count 2 2006.201.21:45:52.98#ibcon#read 5, iclass 6, count 2 2006.201.21:45:52.98#ibcon#about to read 6, iclass 6, count 2 2006.201.21:45:52.98#ibcon#read 6, iclass 6, count 2 2006.201.21:45:52.98#ibcon#end of sib2, iclass 6, count 2 2006.201.21:45:52.98#ibcon#*after write, iclass 6, count 2 2006.201.21:45:52.98#ibcon#*before return 0, iclass 6, count 2 2006.201.21:45:52.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:52.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:52.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.21:45:52.98#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:52.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:53.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:53.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:53.10#ibcon#enter wrdev, iclass 6, count 0 2006.201.21:45:53.10#ibcon#first serial, iclass 6, count 0 2006.201.21:45:53.10#ibcon#enter sib2, iclass 6, count 0 2006.201.21:45:53.10#ibcon#flushed, iclass 6, count 0 2006.201.21:45:53.10#ibcon#about to write, iclass 6, count 0 2006.201.21:45:53.10#ibcon#wrote, iclass 6, count 0 2006.201.21:45:53.10#ibcon#about to read 3, iclass 6, count 0 2006.201.21:45:53.12#ibcon#read 3, iclass 6, count 0 2006.201.21:45:53.12#ibcon#about to read 4, iclass 6, count 0 2006.201.21:45:53.12#ibcon#read 4, iclass 6, count 0 2006.201.21:45:53.12#ibcon#about to read 5, iclass 6, count 0 2006.201.21:45:53.12#ibcon#read 5, iclass 6, count 0 2006.201.21:45:53.12#ibcon#about to read 6, iclass 6, count 0 2006.201.21:45:53.12#ibcon#read 6, iclass 6, count 0 2006.201.21:45:53.12#ibcon#end of sib2, iclass 6, count 0 2006.201.21:45:53.12#ibcon#*mode == 0, iclass 6, count 0 2006.201.21:45:53.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.21:45:53.12#ibcon#[25=USB\r\n] 2006.201.21:45:53.12#ibcon#*before write, iclass 6, count 0 2006.201.21:45:53.12#ibcon#enter sib2, iclass 6, count 0 2006.201.21:45:53.12#ibcon#flushed, iclass 6, count 0 2006.201.21:45:53.12#ibcon#about to write, iclass 6, count 0 2006.201.21:45:53.12#ibcon#wrote, iclass 6, count 0 2006.201.21:45:53.12#ibcon#about to read 3, iclass 6, count 0 2006.201.21:45:53.15#ibcon#read 3, iclass 6, count 0 2006.201.21:45:53.15#ibcon#about to read 4, iclass 6, count 0 2006.201.21:45:53.15#ibcon#read 4, iclass 6, count 0 2006.201.21:45:53.15#ibcon#about to read 5, iclass 6, count 0 2006.201.21:45:53.15#ibcon#read 5, iclass 6, count 0 2006.201.21:45:53.15#ibcon#about to read 6, iclass 6, count 0 2006.201.21:45:53.15#ibcon#read 6, iclass 6, count 0 2006.201.21:45:53.15#ibcon#end of sib2, iclass 6, count 0 2006.201.21:45:53.15#ibcon#*after write, iclass 6, count 0 2006.201.21:45:53.15#ibcon#*before return 0, iclass 6, count 0 2006.201.21:45:53.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:53.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:53.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.21:45:53.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.21:45:53.15$vck44/valo=7,864.99 2006.201.21:45:53.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.21:45:53.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.21:45:53.15#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:53.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:53.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:53.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:53.15#ibcon#enter wrdev, iclass 10, count 0 2006.201.21:45:53.15#ibcon#first serial, iclass 10, count 0 2006.201.21:45:53.15#ibcon#enter sib2, iclass 10, count 0 2006.201.21:45:53.15#ibcon#flushed, iclass 10, count 0 2006.201.21:45:53.15#ibcon#about to write, iclass 10, count 0 2006.201.21:45:53.15#ibcon#wrote, iclass 10, count 0 2006.201.21:45:53.15#ibcon#about to read 3, iclass 10, count 0 2006.201.21:45:53.17#ibcon#read 3, iclass 10, count 0 2006.201.21:45:53.17#ibcon#about to read 4, iclass 10, count 0 2006.201.21:45:53.17#ibcon#read 4, iclass 10, count 0 2006.201.21:45:53.17#ibcon#about to read 5, iclass 10, count 0 2006.201.21:45:53.17#ibcon#read 5, iclass 10, count 0 2006.201.21:45:53.17#ibcon#about to read 6, iclass 10, count 0 2006.201.21:45:53.17#ibcon#read 6, iclass 10, count 0 2006.201.21:45:53.17#ibcon#end of sib2, iclass 10, count 0 2006.201.21:45:53.17#ibcon#*mode == 0, iclass 10, count 0 2006.201.21:45:53.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.21:45:53.17#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.21:45:53.17#ibcon#*before write, iclass 10, count 0 2006.201.21:45:53.17#ibcon#enter sib2, iclass 10, count 0 2006.201.21:45:53.17#ibcon#flushed, iclass 10, count 0 2006.201.21:45:53.17#ibcon#about to write, iclass 10, count 0 2006.201.21:45:53.17#ibcon#wrote, iclass 10, count 0 2006.201.21:45:53.17#ibcon#about to read 3, iclass 10, count 0 2006.201.21:45:53.21#ibcon#read 3, iclass 10, count 0 2006.201.21:45:53.21#ibcon#about to read 4, iclass 10, count 0 2006.201.21:45:53.21#ibcon#read 4, iclass 10, count 0 2006.201.21:45:53.21#ibcon#about to read 5, iclass 10, count 0 2006.201.21:45:53.21#ibcon#read 5, iclass 10, count 0 2006.201.21:45:53.21#ibcon#about to read 6, iclass 10, count 0 2006.201.21:45:53.21#ibcon#read 6, iclass 10, count 0 2006.201.21:45:53.21#ibcon#end of sib2, iclass 10, count 0 2006.201.21:45:53.21#ibcon#*after write, iclass 10, count 0 2006.201.21:45:53.21#ibcon#*before return 0, iclass 10, count 0 2006.201.21:45:53.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:53.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:53.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.21:45:53.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.21:45:53.21$vck44/va=7,5 2006.201.21:45:53.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.21:45:53.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.21:45:53.21#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:53.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:53.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:53.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:53.27#ibcon#enter wrdev, iclass 12, count 2 2006.201.21:45:53.27#ibcon#first serial, iclass 12, count 2 2006.201.21:45:53.27#ibcon#enter sib2, iclass 12, count 2 2006.201.21:45:53.27#ibcon#flushed, iclass 12, count 2 2006.201.21:45:53.27#ibcon#about to write, iclass 12, count 2 2006.201.21:45:53.27#ibcon#wrote, iclass 12, count 2 2006.201.21:45:53.27#ibcon#about to read 3, iclass 12, count 2 2006.201.21:45:53.29#ibcon#read 3, iclass 12, count 2 2006.201.21:45:53.29#ibcon#about to read 4, iclass 12, count 2 2006.201.21:45:53.29#ibcon#read 4, iclass 12, count 2 2006.201.21:45:53.29#ibcon#about to read 5, iclass 12, count 2 2006.201.21:45:53.29#ibcon#read 5, iclass 12, count 2 2006.201.21:45:53.29#ibcon#about to read 6, iclass 12, count 2 2006.201.21:45:53.29#ibcon#read 6, iclass 12, count 2 2006.201.21:45:53.29#ibcon#end of sib2, iclass 12, count 2 2006.201.21:45:53.29#ibcon#*mode == 0, iclass 12, count 2 2006.201.21:45:53.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.21:45:53.29#ibcon#[25=AT07-05\r\n] 2006.201.21:45:53.29#ibcon#*before write, iclass 12, count 2 2006.201.21:45:53.29#ibcon#enter sib2, iclass 12, count 2 2006.201.21:45:53.29#ibcon#flushed, iclass 12, count 2 2006.201.21:45:53.29#ibcon#about to write, iclass 12, count 2 2006.201.21:45:53.29#ibcon#wrote, iclass 12, count 2 2006.201.21:45:53.29#ibcon#about to read 3, iclass 12, count 2 2006.201.21:45:53.32#ibcon#read 3, iclass 12, count 2 2006.201.21:45:53.32#ibcon#about to read 4, iclass 12, count 2 2006.201.21:45:53.32#ibcon#read 4, iclass 12, count 2 2006.201.21:45:53.32#ibcon#about to read 5, iclass 12, count 2 2006.201.21:45:53.32#ibcon#read 5, iclass 12, count 2 2006.201.21:45:53.32#ibcon#about to read 6, iclass 12, count 2 2006.201.21:45:53.32#ibcon#read 6, iclass 12, count 2 2006.201.21:45:53.32#ibcon#end of sib2, iclass 12, count 2 2006.201.21:45:53.32#ibcon#*after write, iclass 12, count 2 2006.201.21:45:53.32#ibcon#*before return 0, iclass 12, count 2 2006.201.21:45:53.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:53.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:53.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.21:45:53.32#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:53.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:53.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:53.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:53.44#ibcon#enter wrdev, iclass 12, count 0 2006.201.21:45:53.44#ibcon#first serial, iclass 12, count 0 2006.201.21:45:53.44#ibcon#enter sib2, iclass 12, count 0 2006.201.21:45:53.44#ibcon#flushed, iclass 12, count 0 2006.201.21:45:53.44#ibcon#about to write, iclass 12, count 0 2006.201.21:45:53.44#ibcon#wrote, iclass 12, count 0 2006.201.21:45:53.44#ibcon#about to read 3, iclass 12, count 0 2006.201.21:45:53.46#ibcon#read 3, iclass 12, count 0 2006.201.21:45:53.46#ibcon#about to read 4, iclass 12, count 0 2006.201.21:45:53.46#ibcon#read 4, iclass 12, count 0 2006.201.21:45:53.46#ibcon#about to read 5, iclass 12, count 0 2006.201.21:45:53.46#ibcon#read 5, iclass 12, count 0 2006.201.21:45:53.46#ibcon#about to read 6, iclass 12, count 0 2006.201.21:45:53.46#ibcon#read 6, iclass 12, count 0 2006.201.21:45:53.46#ibcon#end of sib2, iclass 12, count 0 2006.201.21:45:53.46#ibcon#*mode == 0, iclass 12, count 0 2006.201.21:45:53.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.21:45:53.46#ibcon#[25=USB\r\n] 2006.201.21:45:53.46#ibcon#*before write, iclass 12, count 0 2006.201.21:45:53.46#ibcon#enter sib2, iclass 12, count 0 2006.201.21:45:53.46#ibcon#flushed, iclass 12, count 0 2006.201.21:45:53.46#ibcon#about to write, iclass 12, count 0 2006.201.21:45:53.46#ibcon#wrote, iclass 12, count 0 2006.201.21:45:53.46#ibcon#about to read 3, iclass 12, count 0 2006.201.21:45:53.49#ibcon#read 3, iclass 12, count 0 2006.201.21:45:53.49#ibcon#about to read 4, iclass 12, count 0 2006.201.21:45:53.49#ibcon#read 4, iclass 12, count 0 2006.201.21:45:53.49#ibcon#about to read 5, iclass 12, count 0 2006.201.21:45:53.49#ibcon#read 5, iclass 12, count 0 2006.201.21:45:53.49#ibcon#about to read 6, iclass 12, count 0 2006.201.21:45:53.49#ibcon#read 6, iclass 12, count 0 2006.201.21:45:53.49#ibcon#end of sib2, iclass 12, count 0 2006.201.21:45:53.49#ibcon#*after write, iclass 12, count 0 2006.201.21:45:53.49#ibcon#*before return 0, iclass 12, count 0 2006.201.21:45:53.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:53.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:53.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.21:45:53.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.21:45:53.49$vck44/valo=8,884.99 2006.201.21:45:53.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.21:45:53.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.21:45:53.49#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:53.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:53.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:53.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:53.49#ibcon#enter wrdev, iclass 14, count 0 2006.201.21:45:53.49#ibcon#first serial, iclass 14, count 0 2006.201.21:45:53.49#ibcon#enter sib2, iclass 14, count 0 2006.201.21:45:53.49#ibcon#flushed, iclass 14, count 0 2006.201.21:45:53.49#ibcon#about to write, iclass 14, count 0 2006.201.21:45:53.49#ibcon#wrote, iclass 14, count 0 2006.201.21:45:53.49#ibcon#about to read 3, iclass 14, count 0 2006.201.21:45:53.51#ibcon#read 3, iclass 14, count 0 2006.201.21:45:53.51#ibcon#about to read 4, iclass 14, count 0 2006.201.21:45:53.51#ibcon#read 4, iclass 14, count 0 2006.201.21:45:53.51#ibcon#about to read 5, iclass 14, count 0 2006.201.21:45:53.51#ibcon#read 5, iclass 14, count 0 2006.201.21:45:53.51#ibcon#about to read 6, iclass 14, count 0 2006.201.21:45:53.51#ibcon#read 6, iclass 14, count 0 2006.201.21:45:53.51#ibcon#end of sib2, iclass 14, count 0 2006.201.21:45:53.51#ibcon#*mode == 0, iclass 14, count 0 2006.201.21:45:53.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.21:45:53.51#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.21:45:53.51#ibcon#*before write, iclass 14, count 0 2006.201.21:45:53.51#ibcon#enter sib2, iclass 14, count 0 2006.201.21:45:53.51#ibcon#flushed, iclass 14, count 0 2006.201.21:45:53.51#ibcon#about to write, iclass 14, count 0 2006.201.21:45:53.51#ibcon#wrote, iclass 14, count 0 2006.201.21:45:53.51#ibcon#about to read 3, iclass 14, count 0 2006.201.21:45:53.55#ibcon#read 3, iclass 14, count 0 2006.201.21:45:53.55#ibcon#about to read 4, iclass 14, count 0 2006.201.21:45:53.55#ibcon#read 4, iclass 14, count 0 2006.201.21:45:53.55#ibcon#about to read 5, iclass 14, count 0 2006.201.21:45:53.55#ibcon#read 5, iclass 14, count 0 2006.201.21:45:53.55#ibcon#about to read 6, iclass 14, count 0 2006.201.21:45:53.55#ibcon#read 6, iclass 14, count 0 2006.201.21:45:53.55#ibcon#end of sib2, iclass 14, count 0 2006.201.21:45:53.55#ibcon#*after write, iclass 14, count 0 2006.201.21:45:53.55#ibcon#*before return 0, iclass 14, count 0 2006.201.21:45:53.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:53.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:53.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.21:45:53.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.21:45:53.55$vck44/va=8,4 2006.201.21:45:53.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.21:45:53.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.21:45:53.55#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:53.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:45:53.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:45:53.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:45:53.61#ibcon#enter wrdev, iclass 16, count 2 2006.201.21:45:53.61#ibcon#first serial, iclass 16, count 2 2006.201.21:45:53.61#ibcon#enter sib2, iclass 16, count 2 2006.201.21:45:53.61#ibcon#flushed, iclass 16, count 2 2006.201.21:45:53.61#ibcon#about to write, iclass 16, count 2 2006.201.21:45:53.61#ibcon#wrote, iclass 16, count 2 2006.201.21:45:53.61#ibcon#about to read 3, iclass 16, count 2 2006.201.21:45:53.63#ibcon#read 3, iclass 16, count 2 2006.201.21:45:53.63#ibcon#about to read 4, iclass 16, count 2 2006.201.21:45:53.63#ibcon#read 4, iclass 16, count 2 2006.201.21:45:53.63#ibcon#about to read 5, iclass 16, count 2 2006.201.21:45:53.63#ibcon#read 5, iclass 16, count 2 2006.201.21:45:53.63#ibcon#about to read 6, iclass 16, count 2 2006.201.21:45:53.63#ibcon#read 6, iclass 16, count 2 2006.201.21:45:53.63#ibcon#end of sib2, iclass 16, count 2 2006.201.21:45:53.63#ibcon#*mode == 0, iclass 16, count 2 2006.201.21:45:53.63#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.21:45:53.63#ibcon#[25=AT08-04\r\n] 2006.201.21:45:53.63#ibcon#*before write, iclass 16, count 2 2006.201.21:45:53.63#ibcon#enter sib2, iclass 16, count 2 2006.201.21:45:53.63#ibcon#flushed, iclass 16, count 2 2006.201.21:45:53.63#ibcon#about to write, iclass 16, count 2 2006.201.21:45:53.63#ibcon#wrote, iclass 16, count 2 2006.201.21:45:53.63#ibcon#about to read 3, iclass 16, count 2 2006.201.21:45:53.66#ibcon#read 3, iclass 16, count 2 2006.201.21:45:53.66#ibcon#about to read 4, iclass 16, count 2 2006.201.21:45:53.66#ibcon#read 4, iclass 16, count 2 2006.201.21:45:53.66#ibcon#about to read 5, iclass 16, count 2 2006.201.21:45:53.66#ibcon#read 5, iclass 16, count 2 2006.201.21:45:53.66#ibcon#about to read 6, iclass 16, count 2 2006.201.21:45:53.66#ibcon#read 6, iclass 16, count 2 2006.201.21:45:53.66#ibcon#end of sib2, iclass 16, count 2 2006.201.21:45:53.66#ibcon#*after write, iclass 16, count 2 2006.201.21:45:53.66#ibcon#*before return 0, iclass 16, count 2 2006.201.21:45:53.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:45:53.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.21:45:53.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.21:45:53.66#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:53.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:45:53.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:45:53.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:45:53.78#ibcon#enter wrdev, iclass 16, count 0 2006.201.21:45:53.78#ibcon#first serial, iclass 16, count 0 2006.201.21:45:53.78#ibcon#enter sib2, iclass 16, count 0 2006.201.21:45:53.78#ibcon#flushed, iclass 16, count 0 2006.201.21:45:53.78#ibcon#about to write, iclass 16, count 0 2006.201.21:45:53.78#ibcon#wrote, iclass 16, count 0 2006.201.21:45:53.78#ibcon#about to read 3, iclass 16, count 0 2006.201.21:45:53.80#ibcon#read 3, iclass 16, count 0 2006.201.21:45:53.80#ibcon#about to read 4, iclass 16, count 0 2006.201.21:45:53.80#ibcon#read 4, iclass 16, count 0 2006.201.21:45:53.80#ibcon#about to read 5, iclass 16, count 0 2006.201.21:45:53.80#ibcon#read 5, iclass 16, count 0 2006.201.21:45:53.80#ibcon#about to read 6, iclass 16, count 0 2006.201.21:45:53.80#ibcon#read 6, iclass 16, count 0 2006.201.21:45:53.80#ibcon#end of sib2, iclass 16, count 0 2006.201.21:45:53.80#ibcon#*mode == 0, iclass 16, count 0 2006.201.21:45:53.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.21:45:53.80#ibcon#[25=USB\r\n] 2006.201.21:45:53.80#ibcon#*before write, iclass 16, count 0 2006.201.21:45:53.80#ibcon#enter sib2, iclass 16, count 0 2006.201.21:45:53.80#ibcon#flushed, iclass 16, count 0 2006.201.21:45:53.80#ibcon#about to write, iclass 16, count 0 2006.201.21:45:53.80#ibcon#wrote, iclass 16, count 0 2006.201.21:45:53.80#ibcon#about to read 3, iclass 16, count 0 2006.201.21:45:53.83#ibcon#read 3, iclass 16, count 0 2006.201.21:45:53.83#ibcon#about to read 4, iclass 16, count 0 2006.201.21:45:53.83#ibcon#read 4, iclass 16, count 0 2006.201.21:45:53.83#ibcon#about to read 5, iclass 16, count 0 2006.201.21:45:53.83#ibcon#read 5, iclass 16, count 0 2006.201.21:45:53.83#ibcon#about to read 6, iclass 16, count 0 2006.201.21:45:53.83#ibcon#read 6, iclass 16, count 0 2006.201.21:45:53.83#ibcon#end of sib2, iclass 16, count 0 2006.201.21:45:53.83#ibcon#*after write, iclass 16, count 0 2006.201.21:45:53.83#ibcon#*before return 0, iclass 16, count 0 2006.201.21:45:53.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:45:53.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.21:45:53.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.21:45:53.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.21:45:53.83$vck44/vblo=1,629.99 2006.201.21:45:53.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.21:45:53.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.21:45:53.83#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:53.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:53.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:53.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:53.83#ibcon#enter wrdev, iclass 18, count 0 2006.201.21:45:53.83#ibcon#first serial, iclass 18, count 0 2006.201.21:45:53.83#ibcon#enter sib2, iclass 18, count 0 2006.201.21:45:53.83#ibcon#flushed, iclass 18, count 0 2006.201.21:45:53.83#ibcon#about to write, iclass 18, count 0 2006.201.21:45:53.83#ibcon#wrote, iclass 18, count 0 2006.201.21:45:53.83#ibcon#about to read 3, iclass 18, count 0 2006.201.21:45:53.85#ibcon#read 3, iclass 18, count 0 2006.201.21:45:53.85#ibcon#about to read 4, iclass 18, count 0 2006.201.21:45:53.85#ibcon#read 4, iclass 18, count 0 2006.201.21:45:53.85#ibcon#about to read 5, iclass 18, count 0 2006.201.21:45:53.85#ibcon#read 5, iclass 18, count 0 2006.201.21:45:53.85#ibcon#about to read 6, iclass 18, count 0 2006.201.21:45:53.85#ibcon#read 6, iclass 18, count 0 2006.201.21:45:53.85#ibcon#end of sib2, iclass 18, count 0 2006.201.21:45:53.85#ibcon#*mode == 0, iclass 18, count 0 2006.201.21:45:53.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.21:45:53.85#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.21:45:53.85#ibcon#*before write, iclass 18, count 0 2006.201.21:45:53.85#ibcon#enter sib2, iclass 18, count 0 2006.201.21:45:53.85#ibcon#flushed, iclass 18, count 0 2006.201.21:45:53.85#ibcon#about to write, iclass 18, count 0 2006.201.21:45:53.85#ibcon#wrote, iclass 18, count 0 2006.201.21:45:53.85#ibcon#about to read 3, iclass 18, count 0 2006.201.21:45:53.89#ibcon#read 3, iclass 18, count 0 2006.201.21:45:53.89#ibcon#about to read 4, iclass 18, count 0 2006.201.21:45:53.89#ibcon#read 4, iclass 18, count 0 2006.201.21:45:53.89#ibcon#about to read 5, iclass 18, count 0 2006.201.21:45:53.89#ibcon#read 5, iclass 18, count 0 2006.201.21:45:53.89#ibcon#about to read 6, iclass 18, count 0 2006.201.21:45:53.89#ibcon#read 6, iclass 18, count 0 2006.201.21:45:53.89#ibcon#end of sib2, iclass 18, count 0 2006.201.21:45:53.89#ibcon#*after write, iclass 18, count 0 2006.201.21:45:53.89#ibcon#*before return 0, iclass 18, count 0 2006.201.21:45:53.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:53.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.21:45:53.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.21:45:53.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.21:45:53.89$vck44/vb=1,4 2006.201.21:45:53.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.21:45:53.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.21:45:53.89#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:53.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:53.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:53.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:53.89#ibcon#enter wrdev, iclass 20, count 2 2006.201.21:45:53.89#ibcon#first serial, iclass 20, count 2 2006.201.21:45:53.89#ibcon#enter sib2, iclass 20, count 2 2006.201.21:45:53.89#ibcon#flushed, iclass 20, count 2 2006.201.21:45:53.89#ibcon#about to write, iclass 20, count 2 2006.201.21:45:53.89#ibcon#wrote, iclass 20, count 2 2006.201.21:45:53.89#ibcon#about to read 3, iclass 20, count 2 2006.201.21:45:53.91#ibcon#read 3, iclass 20, count 2 2006.201.21:45:53.91#ibcon#about to read 4, iclass 20, count 2 2006.201.21:45:53.91#ibcon#read 4, iclass 20, count 2 2006.201.21:45:53.91#ibcon#about to read 5, iclass 20, count 2 2006.201.21:45:53.91#ibcon#read 5, iclass 20, count 2 2006.201.21:45:53.91#ibcon#about to read 6, iclass 20, count 2 2006.201.21:45:53.91#ibcon#read 6, iclass 20, count 2 2006.201.21:45:53.91#ibcon#end of sib2, iclass 20, count 2 2006.201.21:45:53.91#ibcon#*mode == 0, iclass 20, count 2 2006.201.21:45:53.91#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.21:45:53.91#ibcon#[27=AT01-04\r\n] 2006.201.21:45:53.91#ibcon#*before write, iclass 20, count 2 2006.201.21:45:53.91#ibcon#enter sib2, iclass 20, count 2 2006.201.21:45:53.91#ibcon#flushed, iclass 20, count 2 2006.201.21:45:53.91#ibcon#about to write, iclass 20, count 2 2006.201.21:45:53.91#ibcon#wrote, iclass 20, count 2 2006.201.21:45:53.91#ibcon#about to read 3, iclass 20, count 2 2006.201.21:45:53.94#ibcon#read 3, iclass 20, count 2 2006.201.21:45:53.94#ibcon#about to read 4, iclass 20, count 2 2006.201.21:45:53.94#ibcon#read 4, iclass 20, count 2 2006.201.21:45:53.94#ibcon#about to read 5, iclass 20, count 2 2006.201.21:45:53.94#ibcon#read 5, iclass 20, count 2 2006.201.21:45:53.94#ibcon#about to read 6, iclass 20, count 2 2006.201.21:45:53.94#ibcon#read 6, iclass 20, count 2 2006.201.21:45:53.94#ibcon#end of sib2, iclass 20, count 2 2006.201.21:45:53.94#ibcon#*after write, iclass 20, count 2 2006.201.21:45:53.94#ibcon#*before return 0, iclass 20, count 2 2006.201.21:45:53.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:53.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.21:45:53.94#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.21:45:53.94#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:53.94#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:54.06#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:54.06#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:54.06#ibcon#enter wrdev, iclass 20, count 0 2006.201.21:45:54.06#ibcon#first serial, iclass 20, count 0 2006.201.21:45:54.06#ibcon#enter sib2, iclass 20, count 0 2006.201.21:45:54.06#ibcon#flushed, iclass 20, count 0 2006.201.21:45:54.06#ibcon#about to write, iclass 20, count 0 2006.201.21:45:54.06#ibcon#wrote, iclass 20, count 0 2006.201.21:45:54.06#ibcon#about to read 3, iclass 20, count 0 2006.201.21:45:54.08#ibcon#read 3, iclass 20, count 0 2006.201.21:45:54.08#ibcon#about to read 4, iclass 20, count 0 2006.201.21:45:54.08#ibcon#read 4, iclass 20, count 0 2006.201.21:45:54.08#ibcon#about to read 5, iclass 20, count 0 2006.201.21:45:54.08#ibcon#read 5, iclass 20, count 0 2006.201.21:45:54.08#ibcon#about to read 6, iclass 20, count 0 2006.201.21:45:54.08#ibcon#read 6, iclass 20, count 0 2006.201.21:45:54.08#ibcon#end of sib2, iclass 20, count 0 2006.201.21:45:54.08#ibcon#*mode == 0, iclass 20, count 0 2006.201.21:45:54.08#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.21:45:54.08#ibcon#[27=USB\r\n] 2006.201.21:45:54.08#ibcon#*before write, iclass 20, count 0 2006.201.21:45:54.08#ibcon#enter sib2, iclass 20, count 0 2006.201.21:45:54.08#ibcon#flushed, iclass 20, count 0 2006.201.21:45:54.08#ibcon#about to write, iclass 20, count 0 2006.201.21:45:54.08#ibcon#wrote, iclass 20, count 0 2006.201.21:45:54.08#ibcon#about to read 3, iclass 20, count 0 2006.201.21:45:54.11#ibcon#read 3, iclass 20, count 0 2006.201.21:45:54.11#ibcon#about to read 4, iclass 20, count 0 2006.201.21:45:54.11#ibcon#read 4, iclass 20, count 0 2006.201.21:45:54.11#ibcon#about to read 5, iclass 20, count 0 2006.201.21:45:54.11#ibcon#read 5, iclass 20, count 0 2006.201.21:45:54.11#ibcon#about to read 6, iclass 20, count 0 2006.201.21:45:54.11#ibcon#read 6, iclass 20, count 0 2006.201.21:45:54.11#ibcon#end of sib2, iclass 20, count 0 2006.201.21:45:54.11#ibcon#*after write, iclass 20, count 0 2006.201.21:45:54.11#ibcon#*before return 0, iclass 20, count 0 2006.201.21:45:54.11#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:54.11#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.21:45:54.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.21:45:54.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.21:45:54.11$vck44/vblo=2,634.99 2006.201.21:45:54.11#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.21:45:54.11#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.21:45:54.11#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:54.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:54.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:54.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:54.11#ibcon#enter wrdev, iclass 22, count 0 2006.201.21:45:54.11#ibcon#first serial, iclass 22, count 0 2006.201.21:45:54.11#ibcon#enter sib2, iclass 22, count 0 2006.201.21:45:54.11#ibcon#flushed, iclass 22, count 0 2006.201.21:45:54.11#ibcon#about to write, iclass 22, count 0 2006.201.21:45:54.11#ibcon#wrote, iclass 22, count 0 2006.201.21:45:54.11#ibcon#about to read 3, iclass 22, count 0 2006.201.21:45:54.13#ibcon#read 3, iclass 22, count 0 2006.201.21:45:54.13#ibcon#about to read 4, iclass 22, count 0 2006.201.21:45:54.13#ibcon#read 4, iclass 22, count 0 2006.201.21:45:54.13#ibcon#about to read 5, iclass 22, count 0 2006.201.21:45:54.13#ibcon#read 5, iclass 22, count 0 2006.201.21:45:54.13#ibcon#about to read 6, iclass 22, count 0 2006.201.21:45:54.13#ibcon#read 6, iclass 22, count 0 2006.201.21:45:54.13#ibcon#end of sib2, iclass 22, count 0 2006.201.21:45:54.13#ibcon#*mode == 0, iclass 22, count 0 2006.201.21:45:54.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.21:45:54.13#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.21:45:54.13#ibcon#*before write, iclass 22, count 0 2006.201.21:45:54.13#ibcon#enter sib2, iclass 22, count 0 2006.201.21:45:54.13#ibcon#flushed, iclass 22, count 0 2006.201.21:45:54.13#ibcon#about to write, iclass 22, count 0 2006.201.21:45:54.13#ibcon#wrote, iclass 22, count 0 2006.201.21:45:54.13#ibcon#about to read 3, iclass 22, count 0 2006.201.21:45:54.17#ibcon#read 3, iclass 22, count 0 2006.201.21:45:54.17#ibcon#about to read 4, iclass 22, count 0 2006.201.21:45:54.17#ibcon#read 4, iclass 22, count 0 2006.201.21:45:54.17#ibcon#about to read 5, iclass 22, count 0 2006.201.21:45:54.17#ibcon#read 5, iclass 22, count 0 2006.201.21:45:54.17#ibcon#about to read 6, iclass 22, count 0 2006.201.21:45:54.17#ibcon#read 6, iclass 22, count 0 2006.201.21:45:54.17#ibcon#end of sib2, iclass 22, count 0 2006.201.21:45:54.17#ibcon#*after write, iclass 22, count 0 2006.201.21:45:54.17#ibcon#*before return 0, iclass 22, count 0 2006.201.21:45:54.17#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:54.17#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.21:45:54.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.21:45:54.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.21:45:54.17$vck44/vb=2,5 2006.201.21:45:54.17#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.21:45:54.17#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.21:45:54.17#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:54.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:54.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:54.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:54.23#ibcon#enter wrdev, iclass 24, count 2 2006.201.21:45:54.23#ibcon#first serial, iclass 24, count 2 2006.201.21:45:54.23#ibcon#enter sib2, iclass 24, count 2 2006.201.21:45:54.23#ibcon#flushed, iclass 24, count 2 2006.201.21:45:54.23#ibcon#about to write, iclass 24, count 2 2006.201.21:45:54.23#ibcon#wrote, iclass 24, count 2 2006.201.21:45:54.23#ibcon#about to read 3, iclass 24, count 2 2006.201.21:45:54.25#ibcon#read 3, iclass 24, count 2 2006.201.21:45:54.25#ibcon#about to read 4, iclass 24, count 2 2006.201.21:45:54.25#ibcon#read 4, iclass 24, count 2 2006.201.21:45:54.25#ibcon#about to read 5, iclass 24, count 2 2006.201.21:45:54.25#ibcon#read 5, iclass 24, count 2 2006.201.21:45:54.25#ibcon#about to read 6, iclass 24, count 2 2006.201.21:45:54.25#ibcon#read 6, iclass 24, count 2 2006.201.21:45:54.25#ibcon#end of sib2, iclass 24, count 2 2006.201.21:45:54.25#ibcon#*mode == 0, iclass 24, count 2 2006.201.21:45:54.25#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.21:45:54.25#ibcon#[27=AT02-05\r\n] 2006.201.21:45:54.25#ibcon#*before write, iclass 24, count 2 2006.201.21:45:54.25#ibcon#enter sib2, iclass 24, count 2 2006.201.21:45:54.25#ibcon#flushed, iclass 24, count 2 2006.201.21:45:54.25#ibcon#about to write, iclass 24, count 2 2006.201.21:45:54.25#ibcon#wrote, iclass 24, count 2 2006.201.21:45:54.25#ibcon#about to read 3, iclass 24, count 2 2006.201.21:45:54.28#ibcon#read 3, iclass 24, count 2 2006.201.21:45:54.28#ibcon#about to read 4, iclass 24, count 2 2006.201.21:45:54.28#ibcon#read 4, iclass 24, count 2 2006.201.21:45:54.28#ibcon#about to read 5, iclass 24, count 2 2006.201.21:45:54.28#ibcon#read 5, iclass 24, count 2 2006.201.21:45:54.28#ibcon#about to read 6, iclass 24, count 2 2006.201.21:45:54.28#ibcon#read 6, iclass 24, count 2 2006.201.21:45:54.28#ibcon#end of sib2, iclass 24, count 2 2006.201.21:45:54.28#ibcon#*after write, iclass 24, count 2 2006.201.21:45:54.28#ibcon#*before return 0, iclass 24, count 2 2006.201.21:45:54.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:54.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.21:45:54.28#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.21:45:54.28#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:54.28#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:54.40#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:54.40#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:54.40#ibcon#enter wrdev, iclass 24, count 0 2006.201.21:45:54.40#ibcon#first serial, iclass 24, count 0 2006.201.21:45:54.40#ibcon#enter sib2, iclass 24, count 0 2006.201.21:45:54.40#ibcon#flushed, iclass 24, count 0 2006.201.21:45:54.40#ibcon#about to write, iclass 24, count 0 2006.201.21:45:54.40#ibcon#wrote, iclass 24, count 0 2006.201.21:45:54.40#ibcon#about to read 3, iclass 24, count 0 2006.201.21:45:54.42#ibcon#read 3, iclass 24, count 0 2006.201.21:45:54.42#ibcon#about to read 4, iclass 24, count 0 2006.201.21:45:54.42#ibcon#read 4, iclass 24, count 0 2006.201.21:45:54.42#ibcon#about to read 5, iclass 24, count 0 2006.201.21:45:54.42#ibcon#read 5, iclass 24, count 0 2006.201.21:45:54.42#ibcon#about to read 6, iclass 24, count 0 2006.201.21:45:54.42#ibcon#read 6, iclass 24, count 0 2006.201.21:45:54.42#ibcon#end of sib2, iclass 24, count 0 2006.201.21:45:54.42#ibcon#*mode == 0, iclass 24, count 0 2006.201.21:45:54.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.21:45:54.42#ibcon#[27=USB\r\n] 2006.201.21:45:54.42#ibcon#*before write, iclass 24, count 0 2006.201.21:45:54.42#ibcon#enter sib2, iclass 24, count 0 2006.201.21:45:54.42#ibcon#flushed, iclass 24, count 0 2006.201.21:45:54.42#ibcon#about to write, iclass 24, count 0 2006.201.21:45:54.42#ibcon#wrote, iclass 24, count 0 2006.201.21:45:54.42#ibcon#about to read 3, iclass 24, count 0 2006.201.21:45:54.45#ibcon#read 3, iclass 24, count 0 2006.201.21:45:54.45#ibcon#about to read 4, iclass 24, count 0 2006.201.21:45:54.45#ibcon#read 4, iclass 24, count 0 2006.201.21:45:54.45#ibcon#about to read 5, iclass 24, count 0 2006.201.21:45:54.45#ibcon#read 5, iclass 24, count 0 2006.201.21:45:54.45#ibcon#about to read 6, iclass 24, count 0 2006.201.21:45:54.45#ibcon#read 6, iclass 24, count 0 2006.201.21:45:54.45#ibcon#end of sib2, iclass 24, count 0 2006.201.21:45:54.45#ibcon#*after write, iclass 24, count 0 2006.201.21:45:54.45#ibcon#*before return 0, iclass 24, count 0 2006.201.21:45:54.45#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:54.45#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.21:45:54.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.21:45:54.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.21:45:54.45$vck44/vblo=3,649.99 2006.201.21:45:54.45#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.21:45:54.45#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.21:45:54.45#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:54.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:54.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:54.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:54.45#ibcon#enter wrdev, iclass 26, count 0 2006.201.21:45:54.45#ibcon#first serial, iclass 26, count 0 2006.201.21:45:54.45#ibcon#enter sib2, iclass 26, count 0 2006.201.21:45:54.45#ibcon#flushed, iclass 26, count 0 2006.201.21:45:54.45#ibcon#about to write, iclass 26, count 0 2006.201.21:45:54.45#ibcon#wrote, iclass 26, count 0 2006.201.21:45:54.45#ibcon#about to read 3, iclass 26, count 0 2006.201.21:45:54.47#ibcon#read 3, iclass 26, count 0 2006.201.21:45:54.47#ibcon#about to read 4, iclass 26, count 0 2006.201.21:45:54.47#ibcon#read 4, iclass 26, count 0 2006.201.21:45:54.47#ibcon#about to read 5, iclass 26, count 0 2006.201.21:45:54.47#ibcon#read 5, iclass 26, count 0 2006.201.21:45:54.47#ibcon#about to read 6, iclass 26, count 0 2006.201.21:45:54.47#ibcon#read 6, iclass 26, count 0 2006.201.21:45:54.47#ibcon#end of sib2, iclass 26, count 0 2006.201.21:45:54.47#ibcon#*mode == 0, iclass 26, count 0 2006.201.21:45:54.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.21:45:54.47#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.21:45:54.47#ibcon#*before write, iclass 26, count 0 2006.201.21:45:54.47#ibcon#enter sib2, iclass 26, count 0 2006.201.21:45:54.47#ibcon#flushed, iclass 26, count 0 2006.201.21:45:54.47#ibcon#about to write, iclass 26, count 0 2006.201.21:45:54.47#ibcon#wrote, iclass 26, count 0 2006.201.21:45:54.47#ibcon#about to read 3, iclass 26, count 0 2006.201.21:45:54.52#ibcon#read 3, iclass 26, count 0 2006.201.21:45:54.52#ibcon#about to read 4, iclass 26, count 0 2006.201.21:45:54.52#ibcon#read 4, iclass 26, count 0 2006.201.21:45:54.52#ibcon#about to read 5, iclass 26, count 0 2006.201.21:45:54.52#ibcon#read 5, iclass 26, count 0 2006.201.21:45:54.52#ibcon#about to read 6, iclass 26, count 0 2006.201.21:45:54.52#ibcon#read 6, iclass 26, count 0 2006.201.21:45:54.52#ibcon#end of sib2, iclass 26, count 0 2006.201.21:45:54.52#ibcon#*after write, iclass 26, count 0 2006.201.21:45:54.52#ibcon#*before return 0, iclass 26, count 0 2006.201.21:45:54.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:54.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.21:45:54.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.21:45:54.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.21:45:54.52$vck44/vb=3,4 2006.201.21:45:54.52#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.21:45:54.52#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.21:45:54.52#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:54.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:54.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:54.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:54.57#ibcon#enter wrdev, iclass 28, count 2 2006.201.21:45:54.57#ibcon#first serial, iclass 28, count 2 2006.201.21:45:54.57#ibcon#enter sib2, iclass 28, count 2 2006.201.21:45:54.57#ibcon#flushed, iclass 28, count 2 2006.201.21:45:54.57#ibcon#about to write, iclass 28, count 2 2006.201.21:45:54.57#ibcon#wrote, iclass 28, count 2 2006.201.21:45:54.57#ibcon#about to read 3, iclass 28, count 2 2006.201.21:45:54.59#ibcon#read 3, iclass 28, count 2 2006.201.21:45:54.59#ibcon#about to read 4, iclass 28, count 2 2006.201.21:45:54.59#ibcon#read 4, iclass 28, count 2 2006.201.21:45:54.59#ibcon#about to read 5, iclass 28, count 2 2006.201.21:45:54.59#ibcon#read 5, iclass 28, count 2 2006.201.21:45:54.59#ibcon#about to read 6, iclass 28, count 2 2006.201.21:45:54.59#ibcon#read 6, iclass 28, count 2 2006.201.21:45:54.59#ibcon#end of sib2, iclass 28, count 2 2006.201.21:45:54.59#ibcon#*mode == 0, iclass 28, count 2 2006.201.21:45:54.59#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.21:45:54.59#ibcon#[27=AT03-04\r\n] 2006.201.21:45:54.59#ibcon#*before write, iclass 28, count 2 2006.201.21:45:54.59#ibcon#enter sib2, iclass 28, count 2 2006.201.21:45:54.59#ibcon#flushed, iclass 28, count 2 2006.201.21:45:54.59#ibcon#about to write, iclass 28, count 2 2006.201.21:45:54.59#ibcon#wrote, iclass 28, count 2 2006.201.21:45:54.59#ibcon#about to read 3, iclass 28, count 2 2006.201.21:45:54.62#ibcon#read 3, iclass 28, count 2 2006.201.21:45:54.62#ibcon#about to read 4, iclass 28, count 2 2006.201.21:45:54.62#ibcon#read 4, iclass 28, count 2 2006.201.21:45:54.62#ibcon#about to read 5, iclass 28, count 2 2006.201.21:45:54.62#ibcon#read 5, iclass 28, count 2 2006.201.21:45:54.62#ibcon#about to read 6, iclass 28, count 2 2006.201.21:45:54.62#ibcon#read 6, iclass 28, count 2 2006.201.21:45:54.62#ibcon#end of sib2, iclass 28, count 2 2006.201.21:45:54.62#ibcon#*after write, iclass 28, count 2 2006.201.21:45:54.62#ibcon#*before return 0, iclass 28, count 2 2006.201.21:45:54.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:54.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.21:45:54.62#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.21:45:54.62#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:54.62#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:54.74#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:54.74#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:54.74#ibcon#enter wrdev, iclass 28, count 0 2006.201.21:45:54.74#ibcon#first serial, iclass 28, count 0 2006.201.21:45:54.74#ibcon#enter sib2, iclass 28, count 0 2006.201.21:45:54.74#ibcon#flushed, iclass 28, count 0 2006.201.21:45:54.74#ibcon#about to write, iclass 28, count 0 2006.201.21:45:54.74#ibcon#wrote, iclass 28, count 0 2006.201.21:45:54.74#ibcon#about to read 3, iclass 28, count 0 2006.201.21:45:54.76#ibcon#read 3, iclass 28, count 0 2006.201.21:45:54.76#ibcon#about to read 4, iclass 28, count 0 2006.201.21:45:54.76#ibcon#read 4, iclass 28, count 0 2006.201.21:45:54.76#ibcon#about to read 5, iclass 28, count 0 2006.201.21:45:54.76#ibcon#read 5, iclass 28, count 0 2006.201.21:45:54.76#ibcon#about to read 6, iclass 28, count 0 2006.201.21:45:54.76#ibcon#read 6, iclass 28, count 0 2006.201.21:45:54.76#ibcon#end of sib2, iclass 28, count 0 2006.201.21:45:54.76#ibcon#*mode == 0, iclass 28, count 0 2006.201.21:45:54.76#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.21:45:54.76#ibcon#[27=USB\r\n] 2006.201.21:45:54.76#ibcon#*before write, iclass 28, count 0 2006.201.21:45:54.76#ibcon#enter sib2, iclass 28, count 0 2006.201.21:45:54.76#ibcon#flushed, iclass 28, count 0 2006.201.21:45:54.76#ibcon#about to write, iclass 28, count 0 2006.201.21:45:54.76#ibcon#wrote, iclass 28, count 0 2006.201.21:45:54.76#ibcon#about to read 3, iclass 28, count 0 2006.201.21:45:54.79#ibcon#read 3, iclass 28, count 0 2006.201.21:45:54.79#ibcon#about to read 4, iclass 28, count 0 2006.201.21:45:54.79#ibcon#read 4, iclass 28, count 0 2006.201.21:45:54.79#ibcon#about to read 5, iclass 28, count 0 2006.201.21:45:54.79#ibcon#read 5, iclass 28, count 0 2006.201.21:45:54.79#ibcon#about to read 6, iclass 28, count 0 2006.201.21:45:54.79#ibcon#read 6, iclass 28, count 0 2006.201.21:45:54.79#ibcon#end of sib2, iclass 28, count 0 2006.201.21:45:54.79#ibcon#*after write, iclass 28, count 0 2006.201.21:45:54.79#ibcon#*before return 0, iclass 28, count 0 2006.201.21:45:54.79#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:54.79#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.21:45:54.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.21:45:54.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.21:45:54.79$vck44/vblo=4,679.99 2006.201.21:45:54.79#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.21:45:54.79#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.21:45:54.79#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:54.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:54.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:54.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:54.79#ibcon#enter wrdev, iclass 30, count 0 2006.201.21:45:54.79#ibcon#first serial, iclass 30, count 0 2006.201.21:45:54.79#ibcon#enter sib2, iclass 30, count 0 2006.201.21:45:54.79#ibcon#flushed, iclass 30, count 0 2006.201.21:45:54.79#ibcon#about to write, iclass 30, count 0 2006.201.21:45:54.79#ibcon#wrote, iclass 30, count 0 2006.201.21:45:54.79#ibcon#about to read 3, iclass 30, count 0 2006.201.21:45:54.81#ibcon#read 3, iclass 30, count 0 2006.201.21:45:54.81#ibcon#about to read 4, iclass 30, count 0 2006.201.21:45:54.81#ibcon#read 4, iclass 30, count 0 2006.201.21:45:54.81#ibcon#about to read 5, iclass 30, count 0 2006.201.21:45:54.81#ibcon#read 5, iclass 30, count 0 2006.201.21:45:54.81#ibcon#about to read 6, iclass 30, count 0 2006.201.21:45:54.81#ibcon#read 6, iclass 30, count 0 2006.201.21:45:54.81#ibcon#end of sib2, iclass 30, count 0 2006.201.21:45:54.81#ibcon#*mode == 0, iclass 30, count 0 2006.201.21:45:54.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.21:45:54.81#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.21:45:54.81#ibcon#*before write, iclass 30, count 0 2006.201.21:45:54.81#ibcon#enter sib2, iclass 30, count 0 2006.201.21:45:54.81#ibcon#flushed, iclass 30, count 0 2006.201.21:45:54.81#ibcon#about to write, iclass 30, count 0 2006.201.21:45:54.81#ibcon#wrote, iclass 30, count 0 2006.201.21:45:54.81#ibcon#about to read 3, iclass 30, count 0 2006.201.21:45:54.85#ibcon#read 3, iclass 30, count 0 2006.201.21:45:54.85#ibcon#about to read 4, iclass 30, count 0 2006.201.21:45:54.85#ibcon#read 4, iclass 30, count 0 2006.201.21:45:54.85#ibcon#about to read 5, iclass 30, count 0 2006.201.21:45:54.85#ibcon#read 5, iclass 30, count 0 2006.201.21:45:54.85#ibcon#about to read 6, iclass 30, count 0 2006.201.21:45:54.85#ibcon#read 6, iclass 30, count 0 2006.201.21:45:54.85#ibcon#end of sib2, iclass 30, count 0 2006.201.21:45:54.85#ibcon#*after write, iclass 30, count 0 2006.201.21:45:54.85#ibcon#*before return 0, iclass 30, count 0 2006.201.21:45:54.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:54.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.21:45:54.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.21:45:54.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.21:45:54.85$vck44/vb=4,5 2006.201.21:45:54.85#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.21:45:54.85#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.21:45:54.85#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:54.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:54.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:54.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:54.91#ibcon#enter wrdev, iclass 32, count 2 2006.201.21:45:54.91#ibcon#first serial, iclass 32, count 2 2006.201.21:45:54.91#ibcon#enter sib2, iclass 32, count 2 2006.201.21:45:54.91#ibcon#flushed, iclass 32, count 2 2006.201.21:45:54.91#ibcon#about to write, iclass 32, count 2 2006.201.21:45:54.91#ibcon#wrote, iclass 32, count 2 2006.201.21:45:54.91#ibcon#about to read 3, iclass 32, count 2 2006.201.21:45:54.93#ibcon#read 3, iclass 32, count 2 2006.201.21:45:54.93#ibcon#about to read 4, iclass 32, count 2 2006.201.21:45:54.93#ibcon#read 4, iclass 32, count 2 2006.201.21:45:54.93#ibcon#about to read 5, iclass 32, count 2 2006.201.21:45:54.93#ibcon#read 5, iclass 32, count 2 2006.201.21:45:54.93#ibcon#about to read 6, iclass 32, count 2 2006.201.21:45:54.93#ibcon#read 6, iclass 32, count 2 2006.201.21:45:54.93#ibcon#end of sib2, iclass 32, count 2 2006.201.21:45:54.93#ibcon#*mode == 0, iclass 32, count 2 2006.201.21:45:54.93#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.21:45:54.93#ibcon#[27=AT04-05\r\n] 2006.201.21:45:54.93#ibcon#*before write, iclass 32, count 2 2006.201.21:45:54.93#ibcon#enter sib2, iclass 32, count 2 2006.201.21:45:54.93#ibcon#flushed, iclass 32, count 2 2006.201.21:45:54.93#ibcon#about to write, iclass 32, count 2 2006.201.21:45:54.93#ibcon#wrote, iclass 32, count 2 2006.201.21:45:54.93#ibcon#about to read 3, iclass 32, count 2 2006.201.21:45:54.96#ibcon#read 3, iclass 32, count 2 2006.201.21:45:54.96#ibcon#about to read 4, iclass 32, count 2 2006.201.21:45:54.96#ibcon#read 4, iclass 32, count 2 2006.201.21:45:54.96#ibcon#about to read 5, iclass 32, count 2 2006.201.21:45:54.96#ibcon#read 5, iclass 32, count 2 2006.201.21:45:54.96#ibcon#about to read 6, iclass 32, count 2 2006.201.21:45:54.96#ibcon#read 6, iclass 32, count 2 2006.201.21:45:54.96#ibcon#end of sib2, iclass 32, count 2 2006.201.21:45:54.96#ibcon#*after write, iclass 32, count 2 2006.201.21:45:54.96#ibcon#*before return 0, iclass 32, count 2 2006.201.21:45:54.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:54.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.21:45:54.96#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.21:45:54.96#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:54.96#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:55.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:55.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:55.08#ibcon#enter wrdev, iclass 32, count 0 2006.201.21:45:55.08#ibcon#first serial, iclass 32, count 0 2006.201.21:45:55.08#ibcon#enter sib2, iclass 32, count 0 2006.201.21:45:55.08#ibcon#flushed, iclass 32, count 0 2006.201.21:45:55.08#ibcon#about to write, iclass 32, count 0 2006.201.21:45:55.08#ibcon#wrote, iclass 32, count 0 2006.201.21:45:55.08#ibcon#about to read 3, iclass 32, count 0 2006.201.21:45:55.10#ibcon#read 3, iclass 32, count 0 2006.201.21:45:55.10#ibcon#about to read 4, iclass 32, count 0 2006.201.21:45:55.10#ibcon#read 4, iclass 32, count 0 2006.201.21:45:55.10#ibcon#about to read 5, iclass 32, count 0 2006.201.21:45:55.10#ibcon#read 5, iclass 32, count 0 2006.201.21:45:55.10#ibcon#about to read 6, iclass 32, count 0 2006.201.21:45:55.10#ibcon#read 6, iclass 32, count 0 2006.201.21:45:55.10#ibcon#end of sib2, iclass 32, count 0 2006.201.21:45:55.10#ibcon#*mode == 0, iclass 32, count 0 2006.201.21:45:55.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.21:45:55.10#ibcon#[27=USB\r\n] 2006.201.21:45:55.10#ibcon#*before write, iclass 32, count 0 2006.201.21:45:55.10#ibcon#enter sib2, iclass 32, count 0 2006.201.21:45:55.10#ibcon#flushed, iclass 32, count 0 2006.201.21:45:55.10#ibcon#about to write, iclass 32, count 0 2006.201.21:45:55.10#ibcon#wrote, iclass 32, count 0 2006.201.21:45:55.10#ibcon#about to read 3, iclass 32, count 0 2006.201.21:45:55.13#ibcon#read 3, iclass 32, count 0 2006.201.21:45:55.13#ibcon#about to read 4, iclass 32, count 0 2006.201.21:45:55.13#ibcon#read 4, iclass 32, count 0 2006.201.21:45:55.13#ibcon#about to read 5, iclass 32, count 0 2006.201.21:45:55.13#ibcon#read 5, iclass 32, count 0 2006.201.21:45:55.13#ibcon#about to read 6, iclass 32, count 0 2006.201.21:45:55.13#ibcon#read 6, iclass 32, count 0 2006.201.21:45:55.13#ibcon#end of sib2, iclass 32, count 0 2006.201.21:45:55.13#ibcon#*after write, iclass 32, count 0 2006.201.21:45:55.13#ibcon#*before return 0, iclass 32, count 0 2006.201.21:45:55.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:55.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.21:45:55.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.21:45:55.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.21:45:55.13$vck44/vblo=5,709.99 2006.201.21:45:55.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.21:45:55.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.21:45:55.13#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:55.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:45:55.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:45:55.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:45:55.13#ibcon#enter wrdev, iclass 34, count 0 2006.201.21:45:55.13#ibcon#first serial, iclass 34, count 0 2006.201.21:45:55.13#ibcon#enter sib2, iclass 34, count 0 2006.201.21:45:55.13#ibcon#flushed, iclass 34, count 0 2006.201.21:45:55.13#ibcon#about to write, iclass 34, count 0 2006.201.21:45:55.13#ibcon#wrote, iclass 34, count 0 2006.201.21:45:55.13#ibcon#about to read 3, iclass 34, count 0 2006.201.21:45:55.15#ibcon#read 3, iclass 34, count 0 2006.201.21:45:55.15#ibcon#about to read 4, iclass 34, count 0 2006.201.21:45:55.15#ibcon#read 4, iclass 34, count 0 2006.201.21:45:55.15#ibcon#about to read 5, iclass 34, count 0 2006.201.21:45:55.15#ibcon#read 5, iclass 34, count 0 2006.201.21:45:55.15#ibcon#about to read 6, iclass 34, count 0 2006.201.21:45:55.15#ibcon#read 6, iclass 34, count 0 2006.201.21:45:55.15#ibcon#end of sib2, iclass 34, count 0 2006.201.21:45:55.15#ibcon#*mode == 0, iclass 34, count 0 2006.201.21:45:55.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.21:45:55.15#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.21:45:55.15#ibcon#*before write, iclass 34, count 0 2006.201.21:45:55.15#ibcon#enter sib2, iclass 34, count 0 2006.201.21:45:55.15#ibcon#flushed, iclass 34, count 0 2006.201.21:45:55.15#ibcon#about to write, iclass 34, count 0 2006.201.21:45:55.15#ibcon#wrote, iclass 34, count 0 2006.201.21:45:55.15#ibcon#about to read 3, iclass 34, count 0 2006.201.21:45:55.20#ibcon#read 3, iclass 34, count 0 2006.201.21:45:55.20#ibcon#about to read 4, iclass 34, count 0 2006.201.21:45:55.20#ibcon#read 4, iclass 34, count 0 2006.201.21:45:55.20#ibcon#about to read 5, iclass 34, count 0 2006.201.21:45:55.20#ibcon#read 5, iclass 34, count 0 2006.201.21:45:55.20#ibcon#about to read 6, iclass 34, count 0 2006.201.21:45:55.20#ibcon#read 6, iclass 34, count 0 2006.201.21:45:55.20#ibcon#end of sib2, iclass 34, count 0 2006.201.21:45:55.20#ibcon#*after write, iclass 34, count 0 2006.201.21:45:55.20#ibcon#*before return 0, iclass 34, count 0 2006.201.21:45:55.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:45:55.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.21:45:55.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.21:45:55.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.21:45:55.20$vck44/vb=5,4 2006.201.21:45:55.20#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.21:45:55.20#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.21:45:55.20#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:55.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:45:55.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:45:55.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:45:55.25#ibcon#enter wrdev, iclass 36, count 2 2006.201.21:45:55.25#ibcon#first serial, iclass 36, count 2 2006.201.21:45:55.25#ibcon#enter sib2, iclass 36, count 2 2006.201.21:45:55.25#ibcon#flushed, iclass 36, count 2 2006.201.21:45:55.25#ibcon#about to write, iclass 36, count 2 2006.201.21:45:55.25#ibcon#wrote, iclass 36, count 2 2006.201.21:45:55.25#ibcon#about to read 3, iclass 36, count 2 2006.201.21:45:55.27#ibcon#read 3, iclass 36, count 2 2006.201.21:45:55.27#ibcon#about to read 4, iclass 36, count 2 2006.201.21:45:55.27#ibcon#read 4, iclass 36, count 2 2006.201.21:45:55.27#ibcon#about to read 5, iclass 36, count 2 2006.201.21:45:55.27#ibcon#read 5, iclass 36, count 2 2006.201.21:45:55.27#ibcon#about to read 6, iclass 36, count 2 2006.201.21:45:55.27#ibcon#read 6, iclass 36, count 2 2006.201.21:45:55.27#ibcon#end of sib2, iclass 36, count 2 2006.201.21:45:55.27#ibcon#*mode == 0, iclass 36, count 2 2006.201.21:45:55.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.21:45:55.27#ibcon#[27=AT05-04\r\n] 2006.201.21:45:55.27#ibcon#*before write, iclass 36, count 2 2006.201.21:45:55.27#ibcon#enter sib2, iclass 36, count 2 2006.201.21:45:55.27#ibcon#flushed, iclass 36, count 2 2006.201.21:45:55.27#ibcon#about to write, iclass 36, count 2 2006.201.21:45:55.27#ibcon#wrote, iclass 36, count 2 2006.201.21:45:55.27#ibcon#about to read 3, iclass 36, count 2 2006.201.21:45:55.30#ibcon#read 3, iclass 36, count 2 2006.201.21:45:55.30#ibcon#about to read 4, iclass 36, count 2 2006.201.21:45:55.30#ibcon#read 4, iclass 36, count 2 2006.201.21:45:55.30#ibcon#about to read 5, iclass 36, count 2 2006.201.21:45:55.30#ibcon#read 5, iclass 36, count 2 2006.201.21:45:55.30#ibcon#about to read 6, iclass 36, count 2 2006.201.21:45:55.30#ibcon#read 6, iclass 36, count 2 2006.201.21:45:55.30#ibcon#end of sib2, iclass 36, count 2 2006.201.21:45:55.30#ibcon#*after write, iclass 36, count 2 2006.201.21:45:55.30#ibcon#*before return 0, iclass 36, count 2 2006.201.21:45:55.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:45:55.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.21:45:55.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.21:45:55.30#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:55.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:45:55.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:45:55.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:45:55.42#ibcon#enter wrdev, iclass 36, count 0 2006.201.21:45:55.42#ibcon#first serial, iclass 36, count 0 2006.201.21:45:55.42#ibcon#enter sib2, iclass 36, count 0 2006.201.21:45:55.42#ibcon#flushed, iclass 36, count 0 2006.201.21:45:55.42#ibcon#about to write, iclass 36, count 0 2006.201.21:45:55.42#ibcon#wrote, iclass 36, count 0 2006.201.21:45:55.42#ibcon#about to read 3, iclass 36, count 0 2006.201.21:45:55.44#ibcon#read 3, iclass 36, count 0 2006.201.21:45:55.44#ibcon#about to read 4, iclass 36, count 0 2006.201.21:45:55.44#ibcon#read 4, iclass 36, count 0 2006.201.21:45:55.44#ibcon#about to read 5, iclass 36, count 0 2006.201.21:45:55.44#ibcon#read 5, iclass 36, count 0 2006.201.21:45:55.44#ibcon#about to read 6, iclass 36, count 0 2006.201.21:45:55.44#ibcon#read 6, iclass 36, count 0 2006.201.21:45:55.44#ibcon#end of sib2, iclass 36, count 0 2006.201.21:45:55.44#ibcon#*mode == 0, iclass 36, count 0 2006.201.21:45:55.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.21:45:55.44#ibcon#[27=USB\r\n] 2006.201.21:45:55.44#ibcon#*before write, iclass 36, count 0 2006.201.21:45:55.44#ibcon#enter sib2, iclass 36, count 0 2006.201.21:45:55.44#ibcon#flushed, iclass 36, count 0 2006.201.21:45:55.44#ibcon#about to write, iclass 36, count 0 2006.201.21:45:55.44#ibcon#wrote, iclass 36, count 0 2006.201.21:45:55.44#ibcon#about to read 3, iclass 36, count 0 2006.201.21:45:55.47#ibcon#read 3, iclass 36, count 0 2006.201.21:45:55.47#ibcon#about to read 4, iclass 36, count 0 2006.201.21:45:55.47#ibcon#read 4, iclass 36, count 0 2006.201.21:45:55.47#ibcon#about to read 5, iclass 36, count 0 2006.201.21:45:55.47#ibcon#read 5, iclass 36, count 0 2006.201.21:45:55.47#ibcon#about to read 6, iclass 36, count 0 2006.201.21:45:55.47#ibcon#read 6, iclass 36, count 0 2006.201.21:45:55.47#ibcon#end of sib2, iclass 36, count 0 2006.201.21:45:55.47#ibcon#*after write, iclass 36, count 0 2006.201.21:45:55.47#ibcon#*before return 0, iclass 36, count 0 2006.201.21:45:55.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:45:55.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.21:45:55.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.21:45:55.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.21:45:55.47$vck44/vblo=6,719.99 2006.201.21:45:55.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.21:45:55.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.21:45:55.47#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:55.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:55.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:55.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:55.47#ibcon#enter wrdev, iclass 38, count 0 2006.201.21:45:55.47#ibcon#first serial, iclass 38, count 0 2006.201.21:45:55.47#ibcon#enter sib2, iclass 38, count 0 2006.201.21:45:55.47#ibcon#flushed, iclass 38, count 0 2006.201.21:45:55.47#ibcon#about to write, iclass 38, count 0 2006.201.21:45:55.47#ibcon#wrote, iclass 38, count 0 2006.201.21:45:55.47#ibcon#about to read 3, iclass 38, count 0 2006.201.21:45:55.49#ibcon#read 3, iclass 38, count 0 2006.201.21:45:55.49#ibcon#about to read 4, iclass 38, count 0 2006.201.21:45:55.49#ibcon#read 4, iclass 38, count 0 2006.201.21:45:55.49#ibcon#about to read 5, iclass 38, count 0 2006.201.21:45:55.49#ibcon#read 5, iclass 38, count 0 2006.201.21:45:55.49#ibcon#about to read 6, iclass 38, count 0 2006.201.21:45:55.49#ibcon#read 6, iclass 38, count 0 2006.201.21:45:55.49#ibcon#end of sib2, iclass 38, count 0 2006.201.21:45:55.49#ibcon#*mode == 0, iclass 38, count 0 2006.201.21:45:55.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.21:45:55.49#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.21:45:55.49#ibcon#*before write, iclass 38, count 0 2006.201.21:45:55.49#ibcon#enter sib2, iclass 38, count 0 2006.201.21:45:55.49#ibcon#flushed, iclass 38, count 0 2006.201.21:45:55.49#ibcon#about to write, iclass 38, count 0 2006.201.21:45:55.49#ibcon#wrote, iclass 38, count 0 2006.201.21:45:55.49#ibcon#about to read 3, iclass 38, count 0 2006.201.21:45:55.53#ibcon#read 3, iclass 38, count 0 2006.201.21:45:55.53#ibcon#about to read 4, iclass 38, count 0 2006.201.21:45:55.53#ibcon#read 4, iclass 38, count 0 2006.201.21:45:55.53#ibcon#about to read 5, iclass 38, count 0 2006.201.21:45:55.53#ibcon#read 5, iclass 38, count 0 2006.201.21:45:55.53#ibcon#about to read 6, iclass 38, count 0 2006.201.21:45:55.53#ibcon#read 6, iclass 38, count 0 2006.201.21:45:55.53#ibcon#end of sib2, iclass 38, count 0 2006.201.21:45:55.53#ibcon#*after write, iclass 38, count 0 2006.201.21:45:55.53#ibcon#*before return 0, iclass 38, count 0 2006.201.21:45:55.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:55.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.21:45:55.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.21:45:55.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.21:45:55.53$vck44/vb=6,4 2006.201.21:45:55.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.21:45:55.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.21:45:55.53#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:55.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:55.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:55.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:55.59#ibcon#enter wrdev, iclass 40, count 2 2006.201.21:45:55.59#ibcon#first serial, iclass 40, count 2 2006.201.21:45:55.59#ibcon#enter sib2, iclass 40, count 2 2006.201.21:45:55.59#ibcon#flushed, iclass 40, count 2 2006.201.21:45:55.59#ibcon#about to write, iclass 40, count 2 2006.201.21:45:55.59#ibcon#wrote, iclass 40, count 2 2006.201.21:45:55.59#ibcon#about to read 3, iclass 40, count 2 2006.201.21:45:55.61#ibcon#read 3, iclass 40, count 2 2006.201.21:45:55.61#ibcon#about to read 4, iclass 40, count 2 2006.201.21:45:55.61#ibcon#read 4, iclass 40, count 2 2006.201.21:45:55.61#ibcon#about to read 5, iclass 40, count 2 2006.201.21:45:55.61#ibcon#read 5, iclass 40, count 2 2006.201.21:45:55.61#ibcon#about to read 6, iclass 40, count 2 2006.201.21:45:55.61#ibcon#read 6, iclass 40, count 2 2006.201.21:45:55.61#ibcon#end of sib2, iclass 40, count 2 2006.201.21:45:55.61#ibcon#*mode == 0, iclass 40, count 2 2006.201.21:45:55.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.21:45:55.61#ibcon#[27=AT06-04\r\n] 2006.201.21:45:55.61#ibcon#*before write, iclass 40, count 2 2006.201.21:45:55.61#ibcon#enter sib2, iclass 40, count 2 2006.201.21:45:55.61#ibcon#flushed, iclass 40, count 2 2006.201.21:45:55.61#ibcon#about to write, iclass 40, count 2 2006.201.21:45:55.61#ibcon#wrote, iclass 40, count 2 2006.201.21:45:55.61#ibcon#about to read 3, iclass 40, count 2 2006.201.21:45:55.64#ibcon#read 3, iclass 40, count 2 2006.201.21:45:55.64#ibcon#about to read 4, iclass 40, count 2 2006.201.21:45:55.64#ibcon#read 4, iclass 40, count 2 2006.201.21:45:55.64#ibcon#about to read 5, iclass 40, count 2 2006.201.21:45:55.64#ibcon#read 5, iclass 40, count 2 2006.201.21:45:55.64#ibcon#about to read 6, iclass 40, count 2 2006.201.21:45:55.64#ibcon#read 6, iclass 40, count 2 2006.201.21:45:55.64#ibcon#end of sib2, iclass 40, count 2 2006.201.21:45:55.64#ibcon#*after write, iclass 40, count 2 2006.201.21:45:55.64#ibcon#*before return 0, iclass 40, count 2 2006.201.21:45:55.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:55.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.21:45:55.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.21:45:55.64#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:55.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:55.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:55.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:55.76#ibcon#enter wrdev, iclass 40, count 0 2006.201.21:45:55.76#ibcon#first serial, iclass 40, count 0 2006.201.21:45:55.76#ibcon#enter sib2, iclass 40, count 0 2006.201.21:45:55.76#ibcon#flushed, iclass 40, count 0 2006.201.21:45:55.76#ibcon#about to write, iclass 40, count 0 2006.201.21:45:55.76#ibcon#wrote, iclass 40, count 0 2006.201.21:45:55.76#ibcon#about to read 3, iclass 40, count 0 2006.201.21:45:55.78#ibcon#read 3, iclass 40, count 0 2006.201.21:45:55.78#ibcon#about to read 4, iclass 40, count 0 2006.201.21:45:55.78#ibcon#read 4, iclass 40, count 0 2006.201.21:45:55.78#ibcon#about to read 5, iclass 40, count 0 2006.201.21:45:55.78#ibcon#read 5, iclass 40, count 0 2006.201.21:45:55.78#ibcon#about to read 6, iclass 40, count 0 2006.201.21:45:55.78#ibcon#read 6, iclass 40, count 0 2006.201.21:45:55.78#ibcon#end of sib2, iclass 40, count 0 2006.201.21:45:55.78#ibcon#*mode == 0, iclass 40, count 0 2006.201.21:45:55.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.21:45:55.78#ibcon#[27=USB\r\n] 2006.201.21:45:55.78#ibcon#*before write, iclass 40, count 0 2006.201.21:45:55.78#ibcon#enter sib2, iclass 40, count 0 2006.201.21:45:55.78#ibcon#flushed, iclass 40, count 0 2006.201.21:45:55.78#ibcon#about to write, iclass 40, count 0 2006.201.21:45:55.78#ibcon#wrote, iclass 40, count 0 2006.201.21:45:55.78#ibcon#about to read 3, iclass 40, count 0 2006.201.21:45:55.81#ibcon#read 3, iclass 40, count 0 2006.201.21:45:55.81#ibcon#about to read 4, iclass 40, count 0 2006.201.21:45:55.81#ibcon#read 4, iclass 40, count 0 2006.201.21:45:55.81#ibcon#about to read 5, iclass 40, count 0 2006.201.21:45:55.81#ibcon#read 5, iclass 40, count 0 2006.201.21:45:55.81#ibcon#about to read 6, iclass 40, count 0 2006.201.21:45:55.81#ibcon#read 6, iclass 40, count 0 2006.201.21:45:55.81#ibcon#end of sib2, iclass 40, count 0 2006.201.21:45:55.81#ibcon#*after write, iclass 40, count 0 2006.201.21:45:55.81#ibcon#*before return 0, iclass 40, count 0 2006.201.21:45:55.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:55.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.21:45:55.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.21:45:55.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.21:45:55.81$vck44/vblo=7,734.99 2006.201.21:45:55.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.21:45:55.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.21:45:55.81#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:55.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:55.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:55.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:55.81#ibcon#enter wrdev, iclass 4, count 0 2006.201.21:45:55.81#ibcon#first serial, iclass 4, count 0 2006.201.21:45:55.81#ibcon#enter sib2, iclass 4, count 0 2006.201.21:45:55.81#ibcon#flushed, iclass 4, count 0 2006.201.21:45:55.81#ibcon#about to write, iclass 4, count 0 2006.201.21:45:55.81#ibcon#wrote, iclass 4, count 0 2006.201.21:45:55.81#ibcon#about to read 3, iclass 4, count 0 2006.201.21:45:55.83#ibcon#read 3, iclass 4, count 0 2006.201.21:45:55.83#ibcon#about to read 4, iclass 4, count 0 2006.201.21:45:55.83#ibcon#read 4, iclass 4, count 0 2006.201.21:45:55.83#ibcon#about to read 5, iclass 4, count 0 2006.201.21:45:55.83#ibcon#read 5, iclass 4, count 0 2006.201.21:45:55.83#ibcon#about to read 6, iclass 4, count 0 2006.201.21:45:55.83#ibcon#read 6, iclass 4, count 0 2006.201.21:45:55.83#ibcon#end of sib2, iclass 4, count 0 2006.201.21:45:55.83#ibcon#*mode == 0, iclass 4, count 0 2006.201.21:45:55.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.21:45:55.83#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.21:45:55.83#ibcon#*before write, iclass 4, count 0 2006.201.21:45:55.83#ibcon#enter sib2, iclass 4, count 0 2006.201.21:45:55.83#ibcon#flushed, iclass 4, count 0 2006.201.21:45:55.83#ibcon#about to write, iclass 4, count 0 2006.201.21:45:55.83#ibcon#wrote, iclass 4, count 0 2006.201.21:45:55.83#ibcon#about to read 3, iclass 4, count 0 2006.201.21:45:55.88#ibcon#read 3, iclass 4, count 0 2006.201.21:45:55.88#ibcon#about to read 4, iclass 4, count 0 2006.201.21:45:55.88#ibcon#read 4, iclass 4, count 0 2006.201.21:45:55.88#ibcon#about to read 5, iclass 4, count 0 2006.201.21:45:55.88#ibcon#read 5, iclass 4, count 0 2006.201.21:45:55.88#ibcon#about to read 6, iclass 4, count 0 2006.201.21:45:55.88#ibcon#read 6, iclass 4, count 0 2006.201.21:45:55.88#ibcon#end of sib2, iclass 4, count 0 2006.201.21:45:55.88#ibcon#*after write, iclass 4, count 0 2006.201.21:45:55.88#ibcon#*before return 0, iclass 4, count 0 2006.201.21:45:55.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:55.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.21:45:55.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.21:45:55.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.21:45:55.88$vck44/vb=7,4 2006.201.21:45:55.88#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.21:45:55.88#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.21:45:55.88#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:55.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:55.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:55.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:55.93#ibcon#enter wrdev, iclass 6, count 2 2006.201.21:45:55.93#ibcon#first serial, iclass 6, count 2 2006.201.21:45:55.93#ibcon#enter sib2, iclass 6, count 2 2006.201.21:45:55.93#ibcon#flushed, iclass 6, count 2 2006.201.21:45:55.93#ibcon#about to write, iclass 6, count 2 2006.201.21:45:55.93#ibcon#wrote, iclass 6, count 2 2006.201.21:45:55.93#ibcon#about to read 3, iclass 6, count 2 2006.201.21:45:55.95#ibcon#read 3, iclass 6, count 2 2006.201.21:45:55.95#ibcon#about to read 4, iclass 6, count 2 2006.201.21:45:55.95#ibcon#read 4, iclass 6, count 2 2006.201.21:45:55.95#ibcon#about to read 5, iclass 6, count 2 2006.201.21:45:55.95#ibcon#read 5, iclass 6, count 2 2006.201.21:45:55.95#ibcon#about to read 6, iclass 6, count 2 2006.201.21:45:55.95#ibcon#read 6, iclass 6, count 2 2006.201.21:45:55.95#ibcon#end of sib2, iclass 6, count 2 2006.201.21:45:55.95#ibcon#*mode == 0, iclass 6, count 2 2006.201.21:45:55.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.21:45:55.95#ibcon#[27=AT07-04\r\n] 2006.201.21:45:55.95#ibcon#*before write, iclass 6, count 2 2006.201.21:45:55.95#ibcon#enter sib2, iclass 6, count 2 2006.201.21:45:55.95#ibcon#flushed, iclass 6, count 2 2006.201.21:45:55.95#ibcon#about to write, iclass 6, count 2 2006.201.21:45:55.95#ibcon#wrote, iclass 6, count 2 2006.201.21:45:55.95#ibcon#about to read 3, iclass 6, count 2 2006.201.21:45:55.98#ibcon#read 3, iclass 6, count 2 2006.201.21:45:55.98#ibcon#about to read 4, iclass 6, count 2 2006.201.21:45:55.98#ibcon#read 4, iclass 6, count 2 2006.201.21:45:55.98#ibcon#about to read 5, iclass 6, count 2 2006.201.21:45:55.98#ibcon#read 5, iclass 6, count 2 2006.201.21:45:55.98#ibcon#about to read 6, iclass 6, count 2 2006.201.21:45:55.98#ibcon#read 6, iclass 6, count 2 2006.201.21:45:55.98#ibcon#end of sib2, iclass 6, count 2 2006.201.21:45:55.98#ibcon#*after write, iclass 6, count 2 2006.201.21:45:55.98#ibcon#*before return 0, iclass 6, count 2 2006.201.21:45:55.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:55.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.21:45:55.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.21:45:55.98#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:55.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:56.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:56.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:56.10#ibcon#enter wrdev, iclass 6, count 0 2006.201.21:45:56.10#ibcon#first serial, iclass 6, count 0 2006.201.21:45:56.10#ibcon#enter sib2, iclass 6, count 0 2006.201.21:45:56.10#ibcon#flushed, iclass 6, count 0 2006.201.21:45:56.10#ibcon#about to write, iclass 6, count 0 2006.201.21:45:56.10#ibcon#wrote, iclass 6, count 0 2006.201.21:45:56.10#ibcon#about to read 3, iclass 6, count 0 2006.201.21:45:56.12#ibcon#read 3, iclass 6, count 0 2006.201.21:45:56.12#ibcon#about to read 4, iclass 6, count 0 2006.201.21:45:56.12#ibcon#read 4, iclass 6, count 0 2006.201.21:45:56.12#ibcon#about to read 5, iclass 6, count 0 2006.201.21:45:56.12#ibcon#read 5, iclass 6, count 0 2006.201.21:45:56.12#ibcon#about to read 6, iclass 6, count 0 2006.201.21:45:56.12#ibcon#read 6, iclass 6, count 0 2006.201.21:45:56.12#ibcon#end of sib2, iclass 6, count 0 2006.201.21:45:56.12#ibcon#*mode == 0, iclass 6, count 0 2006.201.21:45:56.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.21:45:56.12#ibcon#[27=USB\r\n] 2006.201.21:45:56.12#ibcon#*before write, iclass 6, count 0 2006.201.21:45:56.12#ibcon#enter sib2, iclass 6, count 0 2006.201.21:45:56.12#ibcon#flushed, iclass 6, count 0 2006.201.21:45:56.12#ibcon#about to write, iclass 6, count 0 2006.201.21:45:56.12#ibcon#wrote, iclass 6, count 0 2006.201.21:45:56.12#ibcon#about to read 3, iclass 6, count 0 2006.201.21:45:56.15#ibcon#read 3, iclass 6, count 0 2006.201.21:45:56.15#ibcon#about to read 4, iclass 6, count 0 2006.201.21:45:56.15#ibcon#read 4, iclass 6, count 0 2006.201.21:45:56.15#ibcon#about to read 5, iclass 6, count 0 2006.201.21:45:56.15#ibcon#read 5, iclass 6, count 0 2006.201.21:45:56.15#ibcon#about to read 6, iclass 6, count 0 2006.201.21:45:56.15#ibcon#read 6, iclass 6, count 0 2006.201.21:45:56.15#ibcon#end of sib2, iclass 6, count 0 2006.201.21:45:56.15#ibcon#*after write, iclass 6, count 0 2006.201.21:45:56.15#ibcon#*before return 0, iclass 6, count 0 2006.201.21:45:56.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:56.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.21:45:56.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.21:45:56.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.21:45:56.15$vck44/vblo=8,744.99 2006.201.21:45:56.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.21:45:56.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.21:45:56.15#ibcon#ireg 17 cls_cnt 0 2006.201.21:45:56.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:56.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:56.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:56.15#ibcon#enter wrdev, iclass 10, count 0 2006.201.21:45:56.15#ibcon#first serial, iclass 10, count 0 2006.201.21:45:56.15#ibcon#enter sib2, iclass 10, count 0 2006.201.21:45:56.15#ibcon#flushed, iclass 10, count 0 2006.201.21:45:56.15#ibcon#about to write, iclass 10, count 0 2006.201.21:45:56.15#ibcon#wrote, iclass 10, count 0 2006.201.21:45:56.15#ibcon#about to read 3, iclass 10, count 0 2006.201.21:45:56.17#ibcon#read 3, iclass 10, count 0 2006.201.21:45:56.17#ibcon#about to read 4, iclass 10, count 0 2006.201.21:45:56.17#ibcon#read 4, iclass 10, count 0 2006.201.21:45:56.17#ibcon#about to read 5, iclass 10, count 0 2006.201.21:45:56.17#ibcon#read 5, iclass 10, count 0 2006.201.21:45:56.17#ibcon#about to read 6, iclass 10, count 0 2006.201.21:45:56.17#ibcon#read 6, iclass 10, count 0 2006.201.21:45:56.17#ibcon#end of sib2, iclass 10, count 0 2006.201.21:45:56.17#ibcon#*mode == 0, iclass 10, count 0 2006.201.21:45:56.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.21:45:56.17#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.21:45:56.17#ibcon#*before write, iclass 10, count 0 2006.201.21:45:56.17#ibcon#enter sib2, iclass 10, count 0 2006.201.21:45:56.17#ibcon#flushed, iclass 10, count 0 2006.201.21:45:56.17#ibcon#about to write, iclass 10, count 0 2006.201.21:45:56.17#ibcon#wrote, iclass 10, count 0 2006.201.21:45:56.17#ibcon#about to read 3, iclass 10, count 0 2006.201.21:45:56.21#ibcon#read 3, iclass 10, count 0 2006.201.21:45:56.21#ibcon#about to read 4, iclass 10, count 0 2006.201.21:45:56.21#ibcon#read 4, iclass 10, count 0 2006.201.21:45:56.21#ibcon#about to read 5, iclass 10, count 0 2006.201.21:45:56.21#ibcon#read 5, iclass 10, count 0 2006.201.21:45:56.21#ibcon#about to read 6, iclass 10, count 0 2006.201.21:45:56.21#ibcon#read 6, iclass 10, count 0 2006.201.21:45:56.21#ibcon#end of sib2, iclass 10, count 0 2006.201.21:45:56.21#ibcon#*after write, iclass 10, count 0 2006.201.21:45:56.21#ibcon#*before return 0, iclass 10, count 0 2006.201.21:45:56.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:56.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.21:45:56.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.21:45:56.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.21:45:56.21$vck44/vb=8,4 2006.201.21:45:56.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.21:45:56.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.21:45:56.21#ibcon#ireg 11 cls_cnt 2 2006.201.21:45:56.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:56.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:56.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:56.27#ibcon#enter wrdev, iclass 12, count 2 2006.201.21:45:56.27#ibcon#first serial, iclass 12, count 2 2006.201.21:45:56.27#ibcon#enter sib2, iclass 12, count 2 2006.201.21:45:56.27#ibcon#flushed, iclass 12, count 2 2006.201.21:45:56.27#ibcon#about to write, iclass 12, count 2 2006.201.21:45:56.27#ibcon#wrote, iclass 12, count 2 2006.201.21:45:56.27#ibcon#about to read 3, iclass 12, count 2 2006.201.21:45:56.29#ibcon#read 3, iclass 12, count 2 2006.201.21:45:56.29#ibcon#about to read 4, iclass 12, count 2 2006.201.21:45:56.29#ibcon#read 4, iclass 12, count 2 2006.201.21:45:56.29#ibcon#about to read 5, iclass 12, count 2 2006.201.21:45:56.29#ibcon#read 5, iclass 12, count 2 2006.201.21:45:56.29#ibcon#about to read 6, iclass 12, count 2 2006.201.21:45:56.29#ibcon#read 6, iclass 12, count 2 2006.201.21:45:56.29#ibcon#end of sib2, iclass 12, count 2 2006.201.21:45:56.29#ibcon#*mode == 0, iclass 12, count 2 2006.201.21:45:56.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.21:45:56.29#ibcon#[27=AT08-04\r\n] 2006.201.21:45:56.29#ibcon#*before write, iclass 12, count 2 2006.201.21:45:56.29#ibcon#enter sib2, iclass 12, count 2 2006.201.21:45:56.29#ibcon#flushed, iclass 12, count 2 2006.201.21:45:56.29#ibcon#about to write, iclass 12, count 2 2006.201.21:45:56.29#ibcon#wrote, iclass 12, count 2 2006.201.21:45:56.29#ibcon#about to read 3, iclass 12, count 2 2006.201.21:45:56.32#ibcon#read 3, iclass 12, count 2 2006.201.21:45:56.32#ibcon#about to read 4, iclass 12, count 2 2006.201.21:45:56.32#ibcon#read 4, iclass 12, count 2 2006.201.21:45:56.32#ibcon#about to read 5, iclass 12, count 2 2006.201.21:45:56.32#ibcon#read 5, iclass 12, count 2 2006.201.21:45:56.32#ibcon#about to read 6, iclass 12, count 2 2006.201.21:45:56.32#ibcon#read 6, iclass 12, count 2 2006.201.21:45:56.32#ibcon#end of sib2, iclass 12, count 2 2006.201.21:45:56.32#ibcon#*after write, iclass 12, count 2 2006.201.21:45:56.32#ibcon#*before return 0, iclass 12, count 2 2006.201.21:45:56.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:56.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.21:45:56.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.21:45:56.32#ibcon#ireg 7 cls_cnt 0 2006.201.21:45:56.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:56.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:56.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:56.44#ibcon#enter wrdev, iclass 12, count 0 2006.201.21:45:56.44#ibcon#first serial, iclass 12, count 0 2006.201.21:45:56.44#ibcon#enter sib2, iclass 12, count 0 2006.201.21:45:56.44#ibcon#flushed, iclass 12, count 0 2006.201.21:45:56.44#ibcon#about to write, iclass 12, count 0 2006.201.21:45:56.44#ibcon#wrote, iclass 12, count 0 2006.201.21:45:56.44#ibcon#about to read 3, iclass 12, count 0 2006.201.21:45:56.46#ibcon#read 3, iclass 12, count 0 2006.201.21:45:56.46#ibcon#about to read 4, iclass 12, count 0 2006.201.21:45:56.46#ibcon#read 4, iclass 12, count 0 2006.201.21:45:56.46#ibcon#about to read 5, iclass 12, count 0 2006.201.21:45:56.46#ibcon#read 5, iclass 12, count 0 2006.201.21:45:56.46#ibcon#about to read 6, iclass 12, count 0 2006.201.21:45:56.46#ibcon#read 6, iclass 12, count 0 2006.201.21:45:56.46#ibcon#end of sib2, iclass 12, count 0 2006.201.21:45:56.46#ibcon#*mode == 0, iclass 12, count 0 2006.201.21:45:56.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.21:45:56.46#ibcon#[27=USB\r\n] 2006.201.21:45:56.46#ibcon#*before write, iclass 12, count 0 2006.201.21:45:56.46#ibcon#enter sib2, iclass 12, count 0 2006.201.21:45:56.46#ibcon#flushed, iclass 12, count 0 2006.201.21:45:56.46#ibcon#about to write, iclass 12, count 0 2006.201.21:45:56.46#ibcon#wrote, iclass 12, count 0 2006.201.21:45:56.46#ibcon#about to read 3, iclass 12, count 0 2006.201.21:45:56.49#ibcon#read 3, iclass 12, count 0 2006.201.21:45:56.49#ibcon#about to read 4, iclass 12, count 0 2006.201.21:45:56.49#ibcon#read 4, iclass 12, count 0 2006.201.21:45:56.49#ibcon#about to read 5, iclass 12, count 0 2006.201.21:45:56.49#ibcon#read 5, iclass 12, count 0 2006.201.21:45:56.49#ibcon#about to read 6, iclass 12, count 0 2006.201.21:45:56.49#ibcon#read 6, iclass 12, count 0 2006.201.21:45:56.49#ibcon#end of sib2, iclass 12, count 0 2006.201.21:45:56.49#ibcon#*after write, iclass 12, count 0 2006.201.21:45:56.49#ibcon#*before return 0, iclass 12, count 0 2006.201.21:45:56.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:56.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.21:45:56.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.21:45:56.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.21:45:56.49$vck44/vabw=wide 2006.201.21:45:56.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.21:45:56.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.21:45:56.49#ibcon#ireg 8 cls_cnt 0 2006.201.21:45:56.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:56.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:56.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:56.49#ibcon#enter wrdev, iclass 14, count 0 2006.201.21:45:56.49#ibcon#first serial, iclass 14, count 0 2006.201.21:45:56.49#ibcon#enter sib2, iclass 14, count 0 2006.201.21:45:56.49#ibcon#flushed, iclass 14, count 0 2006.201.21:45:56.49#ibcon#about to write, iclass 14, count 0 2006.201.21:45:56.49#ibcon#wrote, iclass 14, count 0 2006.201.21:45:56.49#ibcon#about to read 3, iclass 14, count 0 2006.201.21:45:56.51#ibcon#read 3, iclass 14, count 0 2006.201.21:45:56.51#ibcon#about to read 4, iclass 14, count 0 2006.201.21:45:56.51#ibcon#read 4, iclass 14, count 0 2006.201.21:45:56.51#ibcon#about to read 5, iclass 14, count 0 2006.201.21:45:56.51#ibcon#read 5, iclass 14, count 0 2006.201.21:45:56.51#ibcon#about to read 6, iclass 14, count 0 2006.201.21:45:56.51#ibcon#read 6, iclass 14, count 0 2006.201.21:45:56.51#ibcon#end of sib2, iclass 14, count 0 2006.201.21:45:56.51#ibcon#*mode == 0, iclass 14, count 0 2006.201.21:45:56.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.21:45:56.51#ibcon#[25=BW32\r\n] 2006.201.21:45:56.51#ibcon#*before write, iclass 14, count 0 2006.201.21:45:56.51#ibcon#enter sib2, iclass 14, count 0 2006.201.21:45:56.51#ibcon#flushed, iclass 14, count 0 2006.201.21:45:56.51#ibcon#about to write, iclass 14, count 0 2006.201.21:45:56.51#ibcon#wrote, iclass 14, count 0 2006.201.21:45:56.51#ibcon#about to read 3, iclass 14, count 0 2006.201.21:45:56.54#ibcon#read 3, iclass 14, count 0 2006.201.21:45:56.54#ibcon#about to read 4, iclass 14, count 0 2006.201.21:45:56.54#ibcon#read 4, iclass 14, count 0 2006.201.21:45:56.54#ibcon#about to read 5, iclass 14, count 0 2006.201.21:45:56.54#ibcon#read 5, iclass 14, count 0 2006.201.21:45:56.54#ibcon#about to read 6, iclass 14, count 0 2006.201.21:45:56.54#ibcon#read 6, iclass 14, count 0 2006.201.21:45:56.54#ibcon#end of sib2, iclass 14, count 0 2006.201.21:45:56.54#ibcon#*after write, iclass 14, count 0 2006.201.21:45:56.54#ibcon#*before return 0, iclass 14, count 0 2006.201.21:45:56.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:56.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:45:56.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.21:45:56.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.21:45:56.54$vck44/vbbw=wide 2006.201.21:45:56.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.21:45:56.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.21:45:56.54#ibcon#ireg 8 cls_cnt 0 2006.201.21:45:56.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:45:56.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:45:56.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:45:56.61#ibcon#enter wrdev, iclass 16, count 0 2006.201.21:45:56.61#ibcon#first serial, iclass 16, count 0 2006.201.21:45:56.61#ibcon#enter sib2, iclass 16, count 0 2006.201.21:45:56.61#ibcon#flushed, iclass 16, count 0 2006.201.21:45:56.61#ibcon#about to write, iclass 16, count 0 2006.201.21:45:56.61#ibcon#wrote, iclass 16, count 0 2006.201.21:45:56.61#ibcon#about to read 3, iclass 16, count 0 2006.201.21:45:56.63#ibcon#read 3, iclass 16, count 0 2006.201.21:45:56.63#ibcon#about to read 4, iclass 16, count 0 2006.201.21:45:56.63#ibcon#read 4, iclass 16, count 0 2006.201.21:45:56.63#ibcon#about to read 5, iclass 16, count 0 2006.201.21:45:56.63#ibcon#read 5, iclass 16, count 0 2006.201.21:45:56.63#ibcon#about to read 6, iclass 16, count 0 2006.201.21:45:56.63#ibcon#read 6, iclass 16, count 0 2006.201.21:45:56.63#ibcon#end of sib2, iclass 16, count 0 2006.201.21:45:56.63#ibcon#*mode == 0, iclass 16, count 0 2006.201.21:45:56.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.21:45:56.63#ibcon#[27=BW32\r\n] 2006.201.21:45:56.63#ibcon#*before write, iclass 16, count 0 2006.201.21:45:56.63#ibcon#enter sib2, iclass 16, count 0 2006.201.21:45:56.63#ibcon#flushed, iclass 16, count 0 2006.201.21:45:56.63#ibcon#about to write, iclass 16, count 0 2006.201.21:45:56.63#ibcon#wrote, iclass 16, count 0 2006.201.21:45:56.63#ibcon#about to read 3, iclass 16, count 0 2006.201.21:45:56.66#ibcon#read 3, iclass 16, count 0 2006.201.21:45:56.66#ibcon#about to read 4, iclass 16, count 0 2006.201.21:45:56.66#ibcon#read 4, iclass 16, count 0 2006.201.21:45:56.66#ibcon#about to read 5, iclass 16, count 0 2006.201.21:45:56.66#ibcon#read 5, iclass 16, count 0 2006.201.21:45:56.66#ibcon#about to read 6, iclass 16, count 0 2006.201.21:45:56.66#ibcon#read 6, iclass 16, count 0 2006.201.21:45:56.66#ibcon#end of sib2, iclass 16, count 0 2006.201.21:45:56.66#ibcon#*after write, iclass 16, count 0 2006.201.21:45:56.66#ibcon#*before return 0, iclass 16, count 0 2006.201.21:45:56.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:45:56.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:45:56.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.21:45:56.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.21:45:56.66$setupk4/ifdk4 2006.201.21:45:56.66$ifdk4/lo= 2006.201.21:45:56.66$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.21:45:56.66$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.21:45:56.66$ifdk4/patch= 2006.201.21:45:56.66$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.21:45:56.66$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.21:45:56.66$setupk4/!*+20s 2006.201.21:46:00.14#trakl#Source acquired 2006.201.21:46:01.14#flagr#flagr/antenna,acquired 2006.201.21:46:02.45#abcon#<5=/05 1.3 2.3 20.051001001.9\r\n> 2006.201.21:46:02.47#abcon#{5=INTERFACE CLEAR} 2006.201.21:46:02.53#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:46:11.17$setupk4/"tpicd 2006.201.21:46:11.17$setupk4/echo=off 2006.201.21:46:11.17$setupk4/xlog=off 2006.201.21:46:11.17:!2006.201.21:49:51 2006.201.21:49:51.00:preob 2006.201.21:49:51.14/onsource/TRACKING 2006.201.21:49:51.14:!2006.201.21:50:01 2006.201.21:50:01.00:"tape 2006.201.21:50:01.00:"st=record 2006.201.21:50:01.00:data_valid=on 2006.201.21:50:01.00:midob 2006.201.21:50:01.14/onsource/TRACKING 2006.201.21:50:01.14/wx/20.00,1001.9,100 2006.201.21:50:01.29/cable/+6.4812E-03 2006.201.21:50:02.38/va/01,08,usb,yes,55,58 2006.201.21:50:02.38/va/02,07,usb,yes,59,60 2006.201.21:50:02.38/va/03,08,usb,yes,54,56 2006.201.21:50:02.38/va/04,07,usb,yes,61,64 2006.201.21:50:02.38/va/05,04,usb,yes,54,56 2006.201.21:50:02.38/va/06,05,usb,yes,55,55 2006.201.21:50:02.38/va/07,05,usb,yes,53,55 2006.201.21:50:02.38/va/08,04,usb,yes,53,62 2006.201.21:50:02.61/valo/01,524.99,yes,locked 2006.201.21:50:02.61/valo/02,534.99,yes,locked 2006.201.21:50:02.61/valo/03,564.99,yes,locked 2006.201.21:50:02.61/valo/04,624.99,yes,locked 2006.201.21:50:02.61/valo/05,734.99,yes,locked 2006.201.21:50:02.61/valo/06,814.99,yes,locked 2006.201.21:50:02.61/valo/07,864.99,yes,locked 2006.201.21:50:02.61/valo/08,884.99,yes,locked 2006.201.21:50:03.70/vb/01,04,usb,yes,32,30 2006.201.21:50:03.70/vb/02,05,usb,yes,30,30 2006.201.21:50:03.70/vb/03,04,usb,yes,31,34 2006.201.21:50:03.70/vb/04,05,usb,yes,32,30 2006.201.21:50:03.70/vb/05,04,usb,yes,28,31 2006.201.21:50:03.70/vb/06,04,usb,yes,33,29 2006.201.21:50:03.70/vb/07,04,usb,yes,32,32 2006.201.21:50:03.70/vb/08,04,usb,yes,30,33 2006.201.21:50:03.94/vblo/01,629.99,yes,locked 2006.201.21:50:03.94/vblo/02,634.99,yes,locked 2006.201.21:50:03.94/vblo/03,649.99,yes,locked 2006.201.21:50:03.94/vblo/04,679.99,yes,locked 2006.201.21:50:03.94/vblo/05,709.99,yes,locked 2006.201.21:50:03.94/vblo/06,719.99,yes,locked 2006.201.21:50:03.94/vblo/07,734.99,yes,locked 2006.201.21:50:03.94/vblo/08,744.99,yes,locked 2006.201.21:50:04.09/vabw/8 2006.201.21:50:04.24/vbbw/8 2006.201.21:50:04.33/xfe/off,on,16.0 2006.201.21:50:04.71/ifatt/23,28,28,28 2006.201.21:50:05.07/fmout-gps/S +4.53E-07 2006.201.21:50:05.14:!2006.201.21:53:31 2006.201.21:53:31.00:data_valid=off 2006.201.21:53:31.00:"et 2006.201.21:53:31.00:!+3s 2006.201.21:53:34.02:"tape 2006.201.21:53:34.02:postob 2006.201.21:53:34.13/cable/+6.4835E-03 2006.201.21:53:34.13/wx/19.97,1001.7,100 2006.201.21:53:34.21/fmout-gps/S +4.56E-07 2006.201.21:53:34.21:scan_name=201-2157,jd0607,50 2006.201.21:53:34.22:source=0552+398,055530.81,394849.2,2000.0,cw 2006.201.21:53:35.14#flagr#flagr/antenna,new-source 2006.201.21:53:35.14:checkk5 2006.201.21:53:35.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.21:53:35.92/chk_autoobs//k5ts2/ autoobs is running! 2006.201.21:53:36.30/chk_autoobs//k5ts3/ autoobs is running! 2006.201.21:53:36.67/chk_autoobs//k5ts4/ autoobs is running! 2006.201.21:53:37.04/chk_obsdata//k5ts1/T2012150??a.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.21:53:37.41/chk_obsdata//k5ts2/T2012150??b.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.21:53:37.77/chk_obsdata//k5ts3/T2012150??c.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.21:53:38.14/chk_obsdata//k5ts4/T2012150??d.dat file size is correct (nominal:840MB, actual:836MB). 2006.201.21:53:38.84/k5log//k5ts1_log_newline 2006.201.21:53:39.52/k5log//k5ts2_log_newline 2006.201.21:53:40.21/k5log//k5ts3_log_newline 2006.201.21:53:40.90/k5log//k5ts4_log_newline 2006.201.21:53:40.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.21:53:40.92:setupk4=1 2006.201.21:53:40.92$setupk4/echo=on 2006.201.21:53:40.92$setupk4/pcalon 2006.201.21:53:40.92$pcalon/"no phase cal control is implemented here 2006.201.21:53:40.92$setupk4/"tpicd=stop 2006.201.21:53:40.92$setupk4/"rec=synch_on 2006.201.21:53:40.92$setupk4/"rec_mode=128 2006.201.21:53:40.92$setupk4/!* 2006.201.21:53:40.92$setupk4/recpk4 2006.201.21:53:40.92$recpk4/recpatch= 2006.201.21:53:40.93$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.21:53:40.93$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.21:53:40.93$setupk4/vck44 2006.201.21:53:40.93$vck44/valo=1,524.99 2006.201.21:53:40.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.21:53:40.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.21:53:40.93#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:40.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:40.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:40.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:40.93#ibcon#enter wrdev, iclass 25, count 0 2006.201.21:53:40.93#ibcon#first serial, iclass 25, count 0 2006.201.21:53:40.93#ibcon#enter sib2, iclass 25, count 0 2006.201.21:53:40.93#ibcon#flushed, iclass 25, count 0 2006.201.21:53:40.93#ibcon#about to write, iclass 25, count 0 2006.201.21:53:40.93#ibcon#wrote, iclass 25, count 0 2006.201.21:53:40.93#ibcon#about to read 3, iclass 25, count 0 2006.201.21:53:40.96#ibcon#read 3, iclass 25, count 0 2006.201.21:53:40.96#ibcon#about to read 4, iclass 25, count 0 2006.201.21:53:40.96#ibcon#read 4, iclass 25, count 0 2006.201.21:53:40.96#ibcon#about to read 5, iclass 25, count 0 2006.201.21:53:40.96#ibcon#read 5, iclass 25, count 0 2006.201.21:53:40.96#ibcon#about to read 6, iclass 25, count 0 2006.201.21:53:40.96#ibcon#read 6, iclass 25, count 0 2006.201.21:53:40.96#ibcon#end of sib2, iclass 25, count 0 2006.201.21:53:40.96#ibcon#*mode == 0, iclass 25, count 0 2006.201.21:53:40.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.21:53:40.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.21:53:40.96#ibcon#*before write, iclass 25, count 0 2006.201.21:53:40.96#ibcon#enter sib2, iclass 25, count 0 2006.201.21:53:40.96#ibcon#flushed, iclass 25, count 0 2006.201.21:53:40.96#ibcon#about to write, iclass 25, count 0 2006.201.21:53:40.96#ibcon#wrote, iclass 25, count 0 2006.201.21:53:40.96#ibcon#about to read 3, iclass 25, count 0 2006.201.21:53:41.02#ibcon#read 3, iclass 25, count 0 2006.201.21:53:41.02#ibcon#about to read 4, iclass 25, count 0 2006.201.21:53:41.02#ibcon#read 4, iclass 25, count 0 2006.201.21:53:41.02#ibcon#about to read 5, iclass 25, count 0 2006.201.21:53:41.02#ibcon#read 5, iclass 25, count 0 2006.201.21:53:41.02#ibcon#about to read 6, iclass 25, count 0 2006.201.21:53:41.02#ibcon#read 6, iclass 25, count 0 2006.201.21:53:41.02#ibcon#end of sib2, iclass 25, count 0 2006.201.21:53:41.02#ibcon#*after write, iclass 25, count 0 2006.201.21:53:41.02#ibcon#*before return 0, iclass 25, count 0 2006.201.21:53:41.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:41.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:41.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.21:53:41.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.21:53:41.02$vck44/va=1,8 2006.201.21:53:41.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.21:53:41.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.21:53:41.02#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:41.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:41.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:41.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:41.02#ibcon#enter wrdev, iclass 27, count 2 2006.201.21:53:41.02#ibcon#first serial, iclass 27, count 2 2006.201.21:53:41.02#ibcon#enter sib2, iclass 27, count 2 2006.201.21:53:41.02#ibcon#flushed, iclass 27, count 2 2006.201.21:53:41.02#ibcon#about to write, iclass 27, count 2 2006.201.21:53:41.02#ibcon#wrote, iclass 27, count 2 2006.201.21:53:41.02#ibcon#about to read 3, iclass 27, count 2 2006.201.21:53:41.04#ibcon#read 3, iclass 27, count 2 2006.201.21:53:41.04#ibcon#about to read 4, iclass 27, count 2 2006.201.21:53:41.04#ibcon#read 4, iclass 27, count 2 2006.201.21:53:41.04#ibcon#about to read 5, iclass 27, count 2 2006.201.21:53:41.04#ibcon#read 5, iclass 27, count 2 2006.201.21:53:41.04#ibcon#about to read 6, iclass 27, count 2 2006.201.21:53:41.04#ibcon#read 6, iclass 27, count 2 2006.201.21:53:41.04#ibcon#end of sib2, iclass 27, count 2 2006.201.21:53:41.04#ibcon#*mode == 0, iclass 27, count 2 2006.201.21:53:41.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.21:53:41.04#ibcon#[25=AT01-08\r\n] 2006.201.21:53:41.04#ibcon#*before write, iclass 27, count 2 2006.201.21:53:41.04#ibcon#enter sib2, iclass 27, count 2 2006.201.21:53:41.04#ibcon#flushed, iclass 27, count 2 2006.201.21:53:41.04#ibcon#about to write, iclass 27, count 2 2006.201.21:53:41.04#ibcon#wrote, iclass 27, count 2 2006.201.21:53:41.04#ibcon#about to read 3, iclass 27, count 2 2006.201.21:53:41.08#ibcon#read 3, iclass 27, count 2 2006.201.21:53:41.08#ibcon#about to read 4, iclass 27, count 2 2006.201.21:53:41.08#ibcon#read 4, iclass 27, count 2 2006.201.21:53:41.08#ibcon#about to read 5, iclass 27, count 2 2006.201.21:53:41.08#ibcon#read 5, iclass 27, count 2 2006.201.21:53:41.08#ibcon#about to read 6, iclass 27, count 2 2006.201.21:53:41.08#ibcon#read 6, iclass 27, count 2 2006.201.21:53:41.08#ibcon#end of sib2, iclass 27, count 2 2006.201.21:53:41.08#ibcon#*after write, iclass 27, count 2 2006.201.21:53:41.08#ibcon#*before return 0, iclass 27, count 2 2006.201.21:53:41.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:41.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:41.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.21:53:41.08#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:41.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:41.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:41.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:41.20#ibcon#enter wrdev, iclass 27, count 0 2006.201.21:53:41.20#ibcon#first serial, iclass 27, count 0 2006.201.21:53:41.20#ibcon#enter sib2, iclass 27, count 0 2006.201.21:53:41.20#ibcon#flushed, iclass 27, count 0 2006.201.21:53:41.20#ibcon#about to write, iclass 27, count 0 2006.201.21:53:41.20#ibcon#wrote, iclass 27, count 0 2006.201.21:53:41.20#ibcon#about to read 3, iclass 27, count 0 2006.201.21:53:41.23#ibcon#read 3, iclass 27, count 0 2006.201.21:53:41.23#ibcon#about to read 4, iclass 27, count 0 2006.201.21:53:41.23#ibcon#read 4, iclass 27, count 0 2006.201.21:53:41.23#ibcon#about to read 5, iclass 27, count 0 2006.201.21:53:41.23#ibcon#read 5, iclass 27, count 0 2006.201.21:53:41.23#ibcon#about to read 6, iclass 27, count 0 2006.201.21:53:41.23#ibcon#read 6, iclass 27, count 0 2006.201.21:53:41.23#ibcon#end of sib2, iclass 27, count 0 2006.201.21:53:41.23#ibcon#*mode == 0, iclass 27, count 0 2006.201.21:53:41.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.21:53:41.23#ibcon#[25=USB\r\n] 2006.201.21:53:41.23#ibcon#*before write, iclass 27, count 0 2006.201.21:53:41.23#ibcon#enter sib2, iclass 27, count 0 2006.201.21:53:41.23#ibcon#flushed, iclass 27, count 0 2006.201.21:53:41.23#ibcon#about to write, iclass 27, count 0 2006.201.21:53:41.23#ibcon#wrote, iclass 27, count 0 2006.201.21:53:41.23#ibcon#about to read 3, iclass 27, count 0 2006.201.21:53:41.26#ibcon#read 3, iclass 27, count 0 2006.201.21:53:41.26#ibcon#about to read 4, iclass 27, count 0 2006.201.21:53:41.26#ibcon#read 4, iclass 27, count 0 2006.201.21:53:41.26#ibcon#about to read 5, iclass 27, count 0 2006.201.21:53:41.26#ibcon#read 5, iclass 27, count 0 2006.201.21:53:41.26#ibcon#about to read 6, iclass 27, count 0 2006.201.21:53:41.26#ibcon#read 6, iclass 27, count 0 2006.201.21:53:41.26#ibcon#end of sib2, iclass 27, count 0 2006.201.21:53:41.26#ibcon#*after write, iclass 27, count 0 2006.201.21:53:41.26#ibcon#*before return 0, iclass 27, count 0 2006.201.21:53:41.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:41.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:41.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.21:53:41.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.21:53:41.26$vck44/valo=2,534.99 2006.201.21:53:41.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.21:53:41.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.21:53:41.26#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:41.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:41.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:41.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:41.26#ibcon#enter wrdev, iclass 29, count 0 2006.201.21:53:41.26#ibcon#first serial, iclass 29, count 0 2006.201.21:53:41.26#ibcon#enter sib2, iclass 29, count 0 2006.201.21:53:41.26#ibcon#flushed, iclass 29, count 0 2006.201.21:53:41.26#ibcon#about to write, iclass 29, count 0 2006.201.21:53:41.26#ibcon#wrote, iclass 29, count 0 2006.201.21:53:41.26#ibcon#about to read 3, iclass 29, count 0 2006.201.21:53:41.28#ibcon#read 3, iclass 29, count 0 2006.201.21:53:41.28#ibcon#about to read 4, iclass 29, count 0 2006.201.21:53:41.28#ibcon#read 4, iclass 29, count 0 2006.201.21:53:41.28#ibcon#about to read 5, iclass 29, count 0 2006.201.21:53:41.28#ibcon#read 5, iclass 29, count 0 2006.201.21:53:41.28#ibcon#about to read 6, iclass 29, count 0 2006.201.21:53:41.28#ibcon#read 6, iclass 29, count 0 2006.201.21:53:41.28#ibcon#end of sib2, iclass 29, count 0 2006.201.21:53:41.28#ibcon#*mode == 0, iclass 29, count 0 2006.201.21:53:41.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.21:53:41.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.21:53:41.28#ibcon#*before write, iclass 29, count 0 2006.201.21:53:41.28#ibcon#enter sib2, iclass 29, count 0 2006.201.21:53:41.28#ibcon#flushed, iclass 29, count 0 2006.201.21:53:41.28#ibcon#about to write, iclass 29, count 0 2006.201.21:53:41.28#ibcon#wrote, iclass 29, count 0 2006.201.21:53:41.28#ibcon#about to read 3, iclass 29, count 0 2006.201.21:53:41.32#ibcon#read 3, iclass 29, count 0 2006.201.21:53:41.32#ibcon#about to read 4, iclass 29, count 0 2006.201.21:53:41.32#ibcon#read 4, iclass 29, count 0 2006.201.21:53:41.32#ibcon#about to read 5, iclass 29, count 0 2006.201.21:53:41.32#ibcon#read 5, iclass 29, count 0 2006.201.21:53:41.32#ibcon#about to read 6, iclass 29, count 0 2006.201.21:53:41.32#ibcon#read 6, iclass 29, count 0 2006.201.21:53:41.32#ibcon#end of sib2, iclass 29, count 0 2006.201.21:53:41.32#ibcon#*after write, iclass 29, count 0 2006.201.21:53:41.32#ibcon#*before return 0, iclass 29, count 0 2006.201.21:53:41.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:41.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:41.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.21:53:41.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.21:53:41.32$vck44/va=2,7 2006.201.21:53:41.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.21:53:41.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.21:53:41.32#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:41.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:41.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:41.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:41.38#ibcon#enter wrdev, iclass 31, count 2 2006.201.21:53:41.38#ibcon#first serial, iclass 31, count 2 2006.201.21:53:41.38#ibcon#enter sib2, iclass 31, count 2 2006.201.21:53:41.38#ibcon#flushed, iclass 31, count 2 2006.201.21:53:41.38#ibcon#about to write, iclass 31, count 2 2006.201.21:53:41.38#ibcon#wrote, iclass 31, count 2 2006.201.21:53:41.38#ibcon#about to read 3, iclass 31, count 2 2006.201.21:53:41.40#ibcon#read 3, iclass 31, count 2 2006.201.21:53:41.40#ibcon#about to read 4, iclass 31, count 2 2006.201.21:53:41.40#ibcon#read 4, iclass 31, count 2 2006.201.21:53:41.40#ibcon#about to read 5, iclass 31, count 2 2006.201.21:53:41.40#ibcon#read 5, iclass 31, count 2 2006.201.21:53:41.40#ibcon#about to read 6, iclass 31, count 2 2006.201.21:53:41.40#ibcon#read 6, iclass 31, count 2 2006.201.21:53:41.40#ibcon#end of sib2, iclass 31, count 2 2006.201.21:53:41.40#ibcon#*mode == 0, iclass 31, count 2 2006.201.21:53:41.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.21:53:41.40#ibcon#[25=AT02-07\r\n] 2006.201.21:53:41.40#ibcon#*before write, iclass 31, count 2 2006.201.21:53:41.40#ibcon#enter sib2, iclass 31, count 2 2006.201.21:53:41.40#ibcon#flushed, iclass 31, count 2 2006.201.21:53:41.40#ibcon#about to write, iclass 31, count 2 2006.201.21:53:41.40#ibcon#wrote, iclass 31, count 2 2006.201.21:53:41.40#ibcon#about to read 3, iclass 31, count 2 2006.201.21:53:41.43#ibcon#read 3, iclass 31, count 2 2006.201.21:53:41.43#ibcon#about to read 4, iclass 31, count 2 2006.201.21:53:41.43#ibcon#read 4, iclass 31, count 2 2006.201.21:53:41.43#ibcon#about to read 5, iclass 31, count 2 2006.201.21:53:41.43#ibcon#read 5, iclass 31, count 2 2006.201.21:53:41.43#ibcon#about to read 6, iclass 31, count 2 2006.201.21:53:41.43#ibcon#read 6, iclass 31, count 2 2006.201.21:53:41.43#ibcon#end of sib2, iclass 31, count 2 2006.201.21:53:41.43#ibcon#*after write, iclass 31, count 2 2006.201.21:53:41.43#ibcon#*before return 0, iclass 31, count 2 2006.201.21:53:41.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:41.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:41.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.21:53:41.43#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:41.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:41.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:41.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:41.55#ibcon#enter wrdev, iclass 31, count 0 2006.201.21:53:41.55#ibcon#first serial, iclass 31, count 0 2006.201.21:53:41.55#ibcon#enter sib2, iclass 31, count 0 2006.201.21:53:41.55#ibcon#flushed, iclass 31, count 0 2006.201.21:53:41.55#ibcon#about to write, iclass 31, count 0 2006.201.21:53:41.55#ibcon#wrote, iclass 31, count 0 2006.201.21:53:41.55#ibcon#about to read 3, iclass 31, count 0 2006.201.21:53:41.57#ibcon#read 3, iclass 31, count 0 2006.201.21:53:41.57#ibcon#about to read 4, iclass 31, count 0 2006.201.21:53:41.57#ibcon#read 4, iclass 31, count 0 2006.201.21:53:41.57#ibcon#about to read 5, iclass 31, count 0 2006.201.21:53:41.57#ibcon#read 5, iclass 31, count 0 2006.201.21:53:41.57#ibcon#about to read 6, iclass 31, count 0 2006.201.21:53:41.57#ibcon#read 6, iclass 31, count 0 2006.201.21:53:41.57#ibcon#end of sib2, iclass 31, count 0 2006.201.21:53:41.57#ibcon#*mode == 0, iclass 31, count 0 2006.201.21:53:41.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.21:53:41.57#ibcon#[25=USB\r\n] 2006.201.21:53:41.57#ibcon#*before write, iclass 31, count 0 2006.201.21:53:41.57#ibcon#enter sib2, iclass 31, count 0 2006.201.21:53:41.57#ibcon#flushed, iclass 31, count 0 2006.201.21:53:41.57#ibcon#about to write, iclass 31, count 0 2006.201.21:53:41.57#ibcon#wrote, iclass 31, count 0 2006.201.21:53:41.57#ibcon#about to read 3, iclass 31, count 0 2006.201.21:53:41.60#ibcon#read 3, iclass 31, count 0 2006.201.21:53:41.60#ibcon#about to read 4, iclass 31, count 0 2006.201.21:53:41.60#ibcon#read 4, iclass 31, count 0 2006.201.21:53:41.60#ibcon#about to read 5, iclass 31, count 0 2006.201.21:53:41.60#ibcon#read 5, iclass 31, count 0 2006.201.21:53:41.60#ibcon#about to read 6, iclass 31, count 0 2006.201.21:53:41.60#ibcon#read 6, iclass 31, count 0 2006.201.21:53:41.60#ibcon#end of sib2, iclass 31, count 0 2006.201.21:53:41.60#ibcon#*after write, iclass 31, count 0 2006.201.21:53:41.60#ibcon#*before return 0, iclass 31, count 0 2006.201.21:53:41.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:41.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:41.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.21:53:41.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.21:53:41.60$vck44/valo=3,564.99 2006.201.21:53:41.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.21:53:41.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.21:53:41.60#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:41.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:41.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:41.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:41.60#ibcon#enter wrdev, iclass 33, count 0 2006.201.21:53:41.60#ibcon#first serial, iclass 33, count 0 2006.201.21:53:41.60#ibcon#enter sib2, iclass 33, count 0 2006.201.21:53:41.60#ibcon#flushed, iclass 33, count 0 2006.201.21:53:41.60#ibcon#about to write, iclass 33, count 0 2006.201.21:53:41.60#ibcon#wrote, iclass 33, count 0 2006.201.21:53:41.60#ibcon#about to read 3, iclass 33, count 0 2006.201.21:53:41.62#ibcon#read 3, iclass 33, count 0 2006.201.21:53:41.62#ibcon#about to read 4, iclass 33, count 0 2006.201.21:53:41.62#ibcon#read 4, iclass 33, count 0 2006.201.21:53:41.62#ibcon#about to read 5, iclass 33, count 0 2006.201.21:53:41.62#ibcon#read 5, iclass 33, count 0 2006.201.21:53:41.62#ibcon#about to read 6, iclass 33, count 0 2006.201.21:53:41.62#ibcon#read 6, iclass 33, count 0 2006.201.21:53:41.62#ibcon#end of sib2, iclass 33, count 0 2006.201.21:53:41.62#ibcon#*mode == 0, iclass 33, count 0 2006.201.21:53:41.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.21:53:41.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.21:53:41.62#ibcon#*before write, iclass 33, count 0 2006.201.21:53:41.62#ibcon#enter sib2, iclass 33, count 0 2006.201.21:53:41.62#ibcon#flushed, iclass 33, count 0 2006.201.21:53:41.62#ibcon#about to write, iclass 33, count 0 2006.201.21:53:41.62#ibcon#wrote, iclass 33, count 0 2006.201.21:53:41.62#ibcon#about to read 3, iclass 33, count 0 2006.201.21:53:41.67#ibcon#read 3, iclass 33, count 0 2006.201.21:53:41.67#ibcon#about to read 4, iclass 33, count 0 2006.201.21:53:41.67#ibcon#read 4, iclass 33, count 0 2006.201.21:53:41.67#ibcon#about to read 5, iclass 33, count 0 2006.201.21:53:41.67#ibcon#read 5, iclass 33, count 0 2006.201.21:53:41.67#ibcon#about to read 6, iclass 33, count 0 2006.201.21:53:41.67#ibcon#read 6, iclass 33, count 0 2006.201.21:53:41.67#ibcon#end of sib2, iclass 33, count 0 2006.201.21:53:41.67#ibcon#*after write, iclass 33, count 0 2006.201.21:53:41.67#ibcon#*before return 0, iclass 33, count 0 2006.201.21:53:41.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:41.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:41.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.21:53:41.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.21:53:41.67$vck44/va=3,8 2006.201.21:53:41.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.21:53:41.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.21:53:41.67#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:41.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:41.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:41.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:41.72#ibcon#enter wrdev, iclass 35, count 2 2006.201.21:53:41.72#ibcon#first serial, iclass 35, count 2 2006.201.21:53:41.72#ibcon#enter sib2, iclass 35, count 2 2006.201.21:53:41.72#ibcon#flushed, iclass 35, count 2 2006.201.21:53:41.72#ibcon#about to write, iclass 35, count 2 2006.201.21:53:41.72#ibcon#wrote, iclass 35, count 2 2006.201.21:53:41.72#ibcon#about to read 3, iclass 35, count 2 2006.201.21:53:41.74#ibcon#read 3, iclass 35, count 2 2006.201.21:53:41.74#ibcon#about to read 4, iclass 35, count 2 2006.201.21:53:41.74#ibcon#read 4, iclass 35, count 2 2006.201.21:53:41.74#ibcon#about to read 5, iclass 35, count 2 2006.201.21:53:41.74#ibcon#read 5, iclass 35, count 2 2006.201.21:53:41.74#ibcon#about to read 6, iclass 35, count 2 2006.201.21:53:41.74#ibcon#read 6, iclass 35, count 2 2006.201.21:53:41.74#ibcon#end of sib2, iclass 35, count 2 2006.201.21:53:41.74#ibcon#*mode == 0, iclass 35, count 2 2006.201.21:53:41.74#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.21:53:41.74#ibcon#[25=AT03-08\r\n] 2006.201.21:53:41.74#ibcon#*before write, iclass 35, count 2 2006.201.21:53:41.74#ibcon#enter sib2, iclass 35, count 2 2006.201.21:53:41.74#ibcon#flushed, iclass 35, count 2 2006.201.21:53:41.74#ibcon#about to write, iclass 35, count 2 2006.201.21:53:41.74#ibcon#wrote, iclass 35, count 2 2006.201.21:53:41.74#ibcon#about to read 3, iclass 35, count 2 2006.201.21:53:41.77#ibcon#read 3, iclass 35, count 2 2006.201.21:53:41.77#ibcon#about to read 4, iclass 35, count 2 2006.201.21:53:41.77#ibcon#read 4, iclass 35, count 2 2006.201.21:53:41.77#ibcon#about to read 5, iclass 35, count 2 2006.201.21:53:41.77#ibcon#read 5, iclass 35, count 2 2006.201.21:53:41.77#ibcon#about to read 6, iclass 35, count 2 2006.201.21:53:41.77#ibcon#read 6, iclass 35, count 2 2006.201.21:53:41.77#ibcon#end of sib2, iclass 35, count 2 2006.201.21:53:41.77#ibcon#*after write, iclass 35, count 2 2006.201.21:53:41.77#ibcon#*before return 0, iclass 35, count 2 2006.201.21:53:41.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:41.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:41.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.21:53:41.77#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:41.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:41.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:41.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:41.89#ibcon#enter wrdev, iclass 35, count 0 2006.201.21:53:41.89#ibcon#first serial, iclass 35, count 0 2006.201.21:53:41.89#ibcon#enter sib2, iclass 35, count 0 2006.201.21:53:41.89#ibcon#flushed, iclass 35, count 0 2006.201.21:53:41.89#ibcon#about to write, iclass 35, count 0 2006.201.21:53:41.89#ibcon#wrote, iclass 35, count 0 2006.201.21:53:41.89#ibcon#about to read 3, iclass 35, count 0 2006.201.21:53:41.91#ibcon#read 3, iclass 35, count 0 2006.201.21:53:41.91#ibcon#about to read 4, iclass 35, count 0 2006.201.21:53:41.91#ibcon#read 4, iclass 35, count 0 2006.201.21:53:41.91#ibcon#about to read 5, iclass 35, count 0 2006.201.21:53:41.91#ibcon#read 5, iclass 35, count 0 2006.201.21:53:41.91#ibcon#about to read 6, iclass 35, count 0 2006.201.21:53:41.91#ibcon#read 6, iclass 35, count 0 2006.201.21:53:41.91#ibcon#end of sib2, iclass 35, count 0 2006.201.21:53:41.91#ibcon#*mode == 0, iclass 35, count 0 2006.201.21:53:41.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.21:53:41.91#ibcon#[25=USB\r\n] 2006.201.21:53:41.91#ibcon#*before write, iclass 35, count 0 2006.201.21:53:41.91#ibcon#enter sib2, iclass 35, count 0 2006.201.21:53:41.91#ibcon#flushed, iclass 35, count 0 2006.201.21:53:41.91#ibcon#about to write, iclass 35, count 0 2006.201.21:53:41.91#ibcon#wrote, iclass 35, count 0 2006.201.21:53:41.91#ibcon#about to read 3, iclass 35, count 0 2006.201.21:53:41.94#ibcon#read 3, iclass 35, count 0 2006.201.21:53:41.94#ibcon#about to read 4, iclass 35, count 0 2006.201.21:53:41.94#ibcon#read 4, iclass 35, count 0 2006.201.21:53:41.94#ibcon#about to read 5, iclass 35, count 0 2006.201.21:53:41.94#ibcon#read 5, iclass 35, count 0 2006.201.21:53:41.94#ibcon#about to read 6, iclass 35, count 0 2006.201.21:53:41.94#ibcon#read 6, iclass 35, count 0 2006.201.21:53:41.94#ibcon#end of sib2, iclass 35, count 0 2006.201.21:53:41.94#ibcon#*after write, iclass 35, count 0 2006.201.21:53:41.94#ibcon#*before return 0, iclass 35, count 0 2006.201.21:53:41.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:41.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:41.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.21:53:41.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.21:53:41.94$vck44/valo=4,624.99 2006.201.21:53:41.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.21:53:41.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.21:53:41.94#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:41.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:41.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:41.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:41.94#ibcon#enter wrdev, iclass 37, count 0 2006.201.21:53:41.94#ibcon#first serial, iclass 37, count 0 2006.201.21:53:41.94#ibcon#enter sib2, iclass 37, count 0 2006.201.21:53:41.94#ibcon#flushed, iclass 37, count 0 2006.201.21:53:41.94#ibcon#about to write, iclass 37, count 0 2006.201.21:53:41.94#ibcon#wrote, iclass 37, count 0 2006.201.21:53:41.94#ibcon#about to read 3, iclass 37, count 0 2006.201.21:53:41.96#ibcon#read 3, iclass 37, count 0 2006.201.21:53:41.96#ibcon#about to read 4, iclass 37, count 0 2006.201.21:53:41.96#ibcon#read 4, iclass 37, count 0 2006.201.21:53:41.96#ibcon#about to read 5, iclass 37, count 0 2006.201.21:53:41.96#ibcon#read 5, iclass 37, count 0 2006.201.21:53:41.96#ibcon#about to read 6, iclass 37, count 0 2006.201.21:53:41.96#ibcon#read 6, iclass 37, count 0 2006.201.21:53:41.96#ibcon#end of sib2, iclass 37, count 0 2006.201.21:53:41.96#ibcon#*mode == 0, iclass 37, count 0 2006.201.21:53:41.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.21:53:41.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.21:53:41.96#ibcon#*before write, iclass 37, count 0 2006.201.21:53:41.96#ibcon#enter sib2, iclass 37, count 0 2006.201.21:53:41.96#ibcon#flushed, iclass 37, count 0 2006.201.21:53:41.96#ibcon#about to write, iclass 37, count 0 2006.201.21:53:41.96#ibcon#wrote, iclass 37, count 0 2006.201.21:53:41.96#ibcon#about to read 3, iclass 37, count 0 2006.201.21:53:42.01#ibcon#read 3, iclass 37, count 0 2006.201.21:53:42.01#ibcon#about to read 4, iclass 37, count 0 2006.201.21:53:42.01#ibcon#read 4, iclass 37, count 0 2006.201.21:53:42.01#ibcon#about to read 5, iclass 37, count 0 2006.201.21:53:42.01#ibcon#read 5, iclass 37, count 0 2006.201.21:53:42.01#ibcon#about to read 6, iclass 37, count 0 2006.201.21:53:42.01#ibcon#read 6, iclass 37, count 0 2006.201.21:53:42.01#ibcon#end of sib2, iclass 37, count 0 2006.201.21:53:42.01#ibcon#*after write, iclass 37, count 0 2006.201.21:53:42.01#ibcon#*before return 0, iclass 37, count 0 2006.201.21:53:42.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:42.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:42.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.21:53:42.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.21:53:42.01$vck44/va=4,7 2006.201.21:53:42.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.21:53:42.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.21:53:42.01#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:42.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:42.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:42.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:42.06#ibcon#enter wrdev, iclass 39, count 2 2006.201.21:53:42.06#ibcon#first serial, iclass 39, count 2 2006.201.21:53:42.06#ibcon#enter sib2, iclass 39, count 2 2006.201.21:53:42.06#ibcon#flushed, iclass 39, count 2 2006.201.21:53:42.06#ibcon#about to write, iclass 39, count 2 2006.201.21:53:42.06#ibcon#wrote, iclass 39, count 2 2006.201.21:53:42.06#ibcon#about to read 3, iclass 39, count 2 2006.201.21:53:42.08#ibcon#read 3, iclass 39, count 2 2006.201.21:53:42.08#ibcon#about to read 4, iclass 39, count 2 2006.201.21:53:42.08#ibcon#read 4, iclass 39, count 2 2006.201.21:53:42.08#ibcon#about to read 5, iclass 39, count 2 2006.201.21:53:42.08#ibcon#read 5, iclass 39, count 2 2006.201.21:53:42.08#ibcon#about to read 6, iclass 39, count 2 2006.201.21:53:42.08#ibcon#read 6, iclass 39, count 2 2006.201.21:53:42.08#ibcon#end of sib2, iclass 39, count 2 2006.201.21:53:42.08#ibcon#*mode == 0, iclass 39, count 2 2006.201.21:53:42.08#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.21:53:42.08#ibcon#[25=AT04-07\r\n] 2006.201.21:53:42.08#ibcon#*before write, iclass 39, count 2 2006.201.21:53:42.08#ibcon#enter sib2, iclass 39, count 2 2006.201.21:53:42.08#ibcon#flushed, iclass 39, count 2 2006.201.21:53:42.08#ibcon#about to write, iclass 39, count 2 2006.201.21:53:42.08#ibcon#wrote, iclass 39, count 2 2006.201.21:53:42.08#ibcon#about to read 3, iclass 39, count 2 2006.201.21:53:42.11#ibcon#read 3, iclass 39, count 2 2006.201.21:53:42.11#ibcon#about to read 4, iclass 39, count 2 2006.201.21:53:42.11#ibcon#read 4, iclass 39, count 2 2006.201.21:53:42.11#ibcon#about to read 5, iclass 39, count 2 2006.201.21:53:42.11#ibcon#read 5, iclass 39, count 2 2006.201.21:53:42.11#ibcon#about to read 6, iclass 39, count 2 2006.201.21:53:42.11#ibcon#read 6, iclass 39, count 2 2006.201.21:53:42.11#ibcon#end of sib2, iclass 39, count 2 2006.201.21:53:42.11#ibcon#*after write, iclass 39, count 2 2006.201.21:53:42.11#ibcon#*before return 0, iclass 39, count 2 2006.201.21:53:42.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:42.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:42.11#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.21:53:42.11#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:42.11#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:42.23#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:42.23#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:42.23#ibcon#enter wrdev, iclass 39, count 0 2006.201.21:53:42.23#ibcon#first serial, iclass 39, count 0 2006.201.21:53:42.23#ibcon#enter sib2, iclass 39, count 0 2006.201.21:53:42.23#ibcon#flushed, iclass 39, count 0 2006.201.21:53:42.23#ibcon#about to write, iclass 39, count 0 2006.201.21:53:42.23#ibcon#wrote, iclass 39, count 0 2006.201.21:53:42.23#ibcon#about to read 3, iclass 39, count 0 2006.201.21:53:42.25#ibcon#read 3, iclass 39, count 0 2006.201.21:53:42.25#ibcon#about to read 4, iclass 39, count 0 2006.201.21:53:42.25#ibcon#read 4, iclass 39, count 0 2006.201.21:53:42.25#ibcon#about to read 5, iclass 39, count 0 2006.201.21:53:42.25#ibcon#read 5, iclass 39, count 0 2006.201.21:53:42.25#ibcon#about to read 6, iclass 39, count 0 2006.201.21:53:42.25#ibcon#read 6, iclass 39, count 0 2006.201.21:53:42.25#ibcon#end of sib2, iclass 39, count 0 2006.201.21:53:42.25#ibcon#*mode == 0, iclass 39, count 0 2006.201.21:53:42.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.21:53:42.25#ibcon#[25=USB\r\n] 2006.201.21:53:42.25#ibcon#*before write, iclass 39, count 0 2006.201.21:53:42.25#ibcon#enter sib2, iclass 39, count 0 2006.201.21:53:42.25#ibcon#flushed, iclass 39, count 0 2006.201.21:53:42.25#ibcon#about to write, iclass 39, count 0 2006.201.21:53:42.25#ibcon#wrote, iclass 39, count 0 2006.201.21:53:42.25#ibcon#about to read 3, iclass 39, count 0 2006.201.21:53:42.28#ibcon#read 3, iclass 39, count 0 2006.201.21:53:42.28#ibcon#about to read 4, iclass 39, count 0 2006.201.21:53:42.28#ibcon#read 4, iclass 39, count 0 2006.201.21:53:42.28#ibcon#about to read 5, iclass 39, count 0 2006.201.21:53:42.28#ibcon#read 5, iclass 39, count 0 2006.201.21:53:42.28#ibcon#about to read 6, iclass 39, count 0 2006.201.21:53:42.28#ibcon#read 6, iclass 39, count 0 2006.201.21:53:42.28#ibcon#end of sib2, iclass 39, count 0 2006.201.21:53:42.28#ibcon#*after write, iclass 39, count 0 2006.201.21:53:42.28#ibcon#*before return 0, iclass 39, count 0 2006.201.21:53:42.28#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:42.28#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:42.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.21:53:42.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.21:53:42.28$vck44/valo=5,734.99 2006.201.21:53:42.28#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.21:53:42.28#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.21:53:42.28#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:42.28#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:42.28#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:42.28#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:42.28#ibcon#enter wrdev, iclass 2, count 0 2006.201.21:53:42.28#ibcon#first serial, iclass 2, count 0 2006.201.21:53:42.28#ibcon#enter sib2, iclass 2, count 0 2006.201.21:53:42.28#ibcon#flushed, iclass 2, count 0 2006.201.21:53:42.28#ibcon#about to write, iclass 2, count 0 2006.201.21:53:42.28#ibcon#wrote, iclass 2, count 0 2006.201.21:53:42.28#ibcon#about to read 3, iclass 2, count 0 2006.201.21:53:42.30#ibcon#read 3, iclass 2, count 0 2006.201.21:53:42.30#ibcon#about to read 4, iclass 2, count 0 2006.201.21:53:42.30#ibcon#read 4, iclass 2, count 0 2006.201.21:53:42.30#ibcon#about to read 5, iclass 2, count 0 2006.201.21:53:42.30#ibcon#read 5, iclass 2, count 0 2006.201.21:53:42.30#ibcon#about to read 6, iclass 2, count 0 2006.201.21:53:42.30#ibcon#read 6, iclass 2, count 0 2006.201.21:53:42.30#ibcon#end of sib2, iclass 2, count 0 2006.201.21:53:42.30#ibcon#*mode == 0, iclass 2, count 0 2006.201.21:53:42.30#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.21:53:42.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.21:53:42.30#ibcon#*before write, iclass 2, count 0 2006.201.21:53:42.30#ibcon#enter sib2, iclass 2, count 0 2006.201.21:53:42.30#ibcon#flushed, iclass 2, count 0 2006.201.21:53:42.30#ibcon#about to write, iclass 2, count 0 2006.201.21:53:42.30#ibcon#wrote, iclass 2, count 0 2006.201.21:53:42.30#ibcon#about to read 3, iclass 2, count 0 2006.201.21:53:42.34#ibcon#read 3, iclass 2, count 0 2006.201.21:53:42.34#ibcon#about to read 4, iclass 2, count 0 2006.201.21:53:42.34#ibcon#read 4, iclass 2, count 0 2006.201.21:53:42.34#ibcon#about to read 5, iclass 2, count 0 2006.201.21:53:42.34#ibcon#read 5, iclass 2, count 0 2006.201.21:53:42.34#ibcon#about to read 6, iclass 2, count 0 2006.201.21:53:42.34#ibcon#read 6, iclass 2, count 0 2006.201.21:53:42.34#ibcon#end of sib2, iclass 2, count 0 2006.201.21:53:42.34#ibcon#*after write, iclass 2, count 0 2006.201.21:53:42.34#ibcon#*before return 0, iclass 2, count 0 2006.201.21:53:42.34#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:42.34#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:42.34#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.21:53:42.34#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.21:53:42.34$vck44/va=5,4 2006.201.21:53:42.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.21:53:42.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.21:53:42.34#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:42.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:42.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:42.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:42.40#ibcon#enter wrdev, iclass 5, count 2 2006.201.21:53:42.40#ibcon#first serial, iclass 5, count 2 2006.201.21:53:42.40#ibcon#enter sib2, iclass 5, count 2 2006.201.21:53:42.40#ibcon#flushed, iclass 5, count 2 2006.201.21:53:42.40#ibcon#about to write, iclass 5, count 2 2006.201.21:53:42.40#ibcon#wrote, iclass 5, count 2 2006.201.21:53:42.40#ibcon#about to read 3, iclass 5, count 2 2006.201.21:53:42.42#ibcon#read 3, iclass 5, count 2 2006.201.21:53:42.42#ibcon#about to read 4, iclass 5, count 2 2006.201.21:53:42.42#ibcon#read 4, iclass 5, count 2 2006.201.21:53:42.42#ibcon#about to read 5, iclass 5, count 2 2006.201.21:53:42.42#ibcon#read 5, iclass 5, count 2 2006.201.21:53:42.42#ibcon#about to read 6, iclass 5, count 2 2006.201.21:53:42.42#ibcon#read 6, iclass 5, count 2 2006.201.21:53:42.42#ibcon#end of sib2, iclass 5, count 2 2006.201.21:53:42.42#ibcon#*mode == 0, iclass 5, count 2 2006.201.21:53:42.42#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.21:53:42.42#ibcon#[25=AT05-04\r\n] 2006.201.21:53:42.42#ibcon#*before write, iclass 5, count 2 2006.201.21:53:42.42#ibcon#enter sib2, iclass 5, count 2 2006.201.21:53:42.42#ibcon#flushed, iclass 5, count 2 2006.201.21:53:42.42#ibcon#about to write, iclass 5, count 2 2006.201.21:53:42.42#ibcon#wrote, iclass 5, count 2 2006.201.21:53:42.42#ibcon#about to read 3, iclass 5, count 2 2006.201.21:53:42.45#ibcon#read 3, iclass 5, count 2 2006.201.21:53:42.45#ibcon#about to read 4, iclass 5, count 2 2006.201.21:53:42.45#ibcon#read 4, iclass 5, count 2 2006.201.21:53:42.45#ibcon#about to read 5, iclass 5, count 2 2006.201.21:53:42.45#ibcon#read 5, iclass 5, count 2 2006.201.21:53:42.45#ibcon#about to read 6, iclass 5, count 2 2006.201.21:53:42.45#ibcon#read 6, iclass 5, count 2 2006.201.21:53:42.45#ibcon#end of sib2, iclass 5, count 2 2006.201.21:53:42.45#ibcon#*after write, iclass 5, count 2 2006.201.21:53:42.45#ibcon#*before return 0, iclass 5, count 2 2006.201.21:53:42.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:42.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:42.45#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.21:53:42.45#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:42.45#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:42.57#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:42.57#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:42.57#ibcon#enter wrdev, iclass 5, count 0 2006.201.21:53:42.57#ibcon#first serial, iclass 5, count 0 2006.201.21:53:42.57#ibcon#enter sib2, iclass 5, count 0 2006.201.21:53:42.57#ibcon#flushed, iclass 5, count 0 2006.201.21:53:42.57#ibcon#about to write, iclass 5, count 0 2006.201.21:53:42.57#ibcon#wrote, iclass 5, count 0 2006.201.21:53:42.57#ibcon#about to read 3, iclass 5, count 0 2006.201.21:53:42.59#ibcon#read 3, iclass 5, count 0 2006.201.21:53:42.59#ibcon#about to read 4, iclass 5, count 0 2006.201.21:53:42.59#ibcon#read 4, iclass 5, count 0 2006.201.21:53:42.59#ibcon#about to read 5, iclass 5, count 0 2006.201.21:53:42.59#ibcon#read 5, iclass 5, count 0 2006.201.21:53:42.59#ibcon#about to read 6, iclass 5, count 0 2006.201.21:53:42.59#ibcon#read 6, iclass 5, count 0 2006.201.21:53:42.59#ibcon#end of sib2, iclass 5, count 0 2006.201.21:53:42.59#ibcon#*mode == 0, iclass 5, count 0 2006.201.21:53:42.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.21:53:42.59#ibcon#[25=USB\r\n] 2006.201.21:53:42.59#ibcon#*before write, iclass 5, count 0 2006.201.21:53:42.59#ibcon#enter sib2, iclass 5, count 0 2006.201.21:53:42.59#ibcon#flushed, iclass 5, count 0 2006.201.21:53:42.59#ibcon#about to write, iclass 5, count 0 2006.201.21:53:42.59#ibcon#wrote, iclass 5, count 0 2006.201.21:53:42.59#ibcon#about to read 3, iclass 5, count 0 2006.201.21:53:42.62#ibcon#read 3, iclass 5, count 0 2006.201.21:53:42.62#ibcon#about to read 4, iclass 5, count 0 2006.201.21:53:42.62#ibcon#read 4, iclass 5, count 0 2006.201.21:53:42.62#ibcon#about to read 5, iclass 5, count 0 2006.201.21:53:42.62#ibcon#read 5, iclass 5, count 0 2006.201.21:53:42.62#ibcon#about to read 6, iclass 5, count 0 2006.201.21:53:42.62#ibcon#read 6, iclass 5, count 0 2006.201.21:53:42.62#ibcon#end of sib2, iclass 5, count 0 2006.201.21:53:42.62#ibcon#*after write, iclass 5, count 0 2006.201.21:53:42.62#ibcon#*before return 0, iclass 5, count 0 2006.201.21:53:42.62#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:42.62#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:42.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.21:53:42.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.21:53:42.62$vck44/valo=6,814.99 2006.201.21:53:42.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.21:53:42.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.21:53:42.62#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:42.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:42.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:42.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:42.62#ibcon#enter wrdev, iclass 7, count 0 2006.201.21:53:42.62#ibcon#first serial, iclass 7, count 0 2006.201.21:53:42.62#ibcon#enter sib2, iclass 7, count 0 2006.201.21:53:42.62#ibcon#flushed, iclass 7, count 0 2006.201.21:53:42.62#ibcon#about to write, iclass 7, count 0 2006.201.21:53:42.62#ibcon#wrote, iclass 7, count 0 2006.201.21:53:42.62#ibcon#about to read 3, iclass 7, count 0 2006.201.21:53:42.64#ibcon#read 3, iclass 7, count 0 2006.201.21:53:42.64#ibcon#about to read 4, iclass 7, count 0 2006.201.21:53:42.64#ibcon#read 4, iclass 7, count 0 2006.201.21:53:42.64#ibcon#about to read 5, iclass 7, count 0 2006.201.21:53:42.64#ibcon#read 5, iclass 7, count 0 2006.201.21:53:42.64#ibcon#about to read 6, iclass 7, count 0 2006.201.21:53:42.64#ibcon#read 6, iclass 7, count 0 2006.201.21:53:42.64#ibcon#end of sib2, iclass 7, count 0 2006.201.21:53:42.64#ibcon#*mode == 0, iclass 7, count 0 2006.201.21:53:42.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.21:53:42.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.21:53:42.64#ibcon#*before write, iclass 7, count 0 2006.201.21:53:42.64#ibcon#enter sib2, iclass 7, count 0 2006.201.21:53:42.64#ibcon#flushed, iclass 7, count 0 2006.201.21:53:42.64#ibcon#about to write, iclass 7, count 0 2006.201.21:53:42.64#ibcon#wrote, iclass 7, count 0 2006.201.21:53:42.64#ibcon#about to read 3, iclass 7, count 0 2006.201.21:53:42.68#ibcon#read 3, iclass 7, count 0 2006.201.21:53:42.68#ibcon#about to read 4, iclass 7, count 0 2006.201.21:53:42.68#ibcon#read 4, iclass 7, count 0 2006.201.21:53:42.68#ibcon#about to read 5, iclass 7, count 0 2006.201.21:53:42.68#ibcon#read 5, iclass 7, count 0 2006.201.21:53:42.68#ibcon#about to read 6, iclass 7, count 0 2006.201.21:53:42.68#ibcon#read 6, iclass 7, count 0 2006.201.21:53:42.68#ibcon#end of sib2, iclass 7, count 0 2006.201.21:53:42.68#ibcon#*after write, iclass 7, count 0 2006.201.21:53:42.68#ibcon#*before return 0, iclass 7, count 0 2006.201.21:53:42.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:42.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:42.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.21:53:42.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.21:53:42.68$vck44/va=6,5 2006.201.21:53:42.68#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.21:53:42.68#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.21:53:42.68#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:42.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:42.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:42.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:42.74#ibcon#enter wrdev, iclass 11, count 2 2006.201.21:53:42.74#ibcon#first serial, iclass 11, count 2 2006.201.21:53:42.74#ibcon#enter sib2, iclass 11, count 2 2006.201.21:53:42.74#ibcon#flushed, iclass 11, count 2 2006.201.21:53:42.74#ibcon#about to write, iclass 11, count 2 2006.201.21:53:42.74#ibcon#wrote, iclass 11, count 2 2006.201.21:53:42.74#ibcon#about to read 3, iclass 11, count 2 2006.201.21:53:42.76#ibcon#read 3, iclass 11, count 2 2006.201.21:53:42.76#ibcon#about to read 4, iclass 11, count 2 2006.201.21:53:42.76#ibcon#read 4, iclass 11, count 2 2006.201.21:53:42.76#ibcon#about to read 5, iclass 11, count 2 2006.201.21:53:42.76#ibcon#read 5, iclass 11, count 2 2006.201.21:53:42.76#ibcon#about to read 6, iclass 11, count 2 2006.201.21:53:42.76#ibcon#read 6, iclass 11, count 2 2006.201.21:53:42.76#ibcon#end of sib2, iclass 11, count 2 2006.201.21:53:42.76#ibcon#*mode == 0, iclass 11, count 2 2006.201.21:53:42.76#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.21:53:42.76#ibcon#[25=AT06-05\r\n] 2006.201.21:53:42.76#ibcon#*before write, iclass 11, count 2 2006.201.21:53:42.76#ibcon#enter sib2, iclass 11, count 2 2006.201.21:53:42.76#ibcon#flushed, iclass 11, count 2 2006.201.21:53:42.76#ibcon#about to write, iclass 11, count 2 2006.201.21:53:42.76#ibcon#wrote, iclass 11, count 2 2006.201.21:53:42.76#ibcon#about to read 3, iclass 11, count 2 2006.201.21:53:42.79#ibcon#read 3, iclass 11, count 2 2006.201.21:53:42.79#ibcon#about to read 4, iclass 11, count 2 2006.201.21:53:42.79#ibcon#read 4, iclass 11, count 2 2006.201.21:53:42.79#ibcon#about to read 5, iclass 11, count 2 2006.201.21:53:42.79#ibcon#read 5, iclass 11, count 2 2006.201.21:53:42.79#ibcon#about to read 6, iclass 11, count 2 2006.201.21:53:42.79#ibcon#read 6, iclass 11, count 2 2006.201.21:53:42.79#ibcon#end of sib2, iclass 11, count 2 2006.201.21:53:42.79#ibcon#*after write, iclass 11, count 2 2006.201.21:53:42.79#ibcon#*before return 0, iclass 11, count 2 2006.201.21:53:42.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:42.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:42.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.21:53:42.79#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:42.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:42.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:42.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:42.91#ibcon#enter wrdev, iclass 11, count 0 2006.201.21:53:42.91#ibcon#first serial, iclass 11, count 0 2006.201.21:53:42.91#ibcon#enter sib2, iclass 11, count 0 2006.201.21:53:42.91#ibcon#flushed, iclass 11, count 0 2006.201.21:53:42.91#ibcon#about to write, iclass 11, count 0 2006.201.21:53:42.91#ibcon#wrote, iclass 11, count 0 2006.201.21:53:42.91#ibcon#about to read 3, iclass 11, count 0 2006.201.21:53:42.93#ibcon#read 3, iclass 11, count 0 2006.201.21:53:42.93#ibcon#about to read 4, iclass 11, count 0 2006.201.21:53:42.93#ibcon#read 4, iclass 11, count 0 2006.201.21:53:42.93#ibcon#about to read 5, iclass 11, count 0 2006.201.21:53:42.93#ibcon#read 5, iclass 11, count 0 2006.201.21:53:42.93#ibcon#about to read 6, iclass 11, count 0 2006.201.21:53:42.93#ibcon#read 6, iclass 11, count 0 2006.201.21:53:42.93#ibcon#end of sib2, iclass 11, count 0 2006.201.21:53:42.93#ibcon#*mode == 0, iclass 11, count 0 2006.201.21:53:42.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.21:53:42.93#ibcon#[25=USB\r\n] 2006.201.21:53:42.93#ibcon#*before write, iclass 11, count 0 2006.201.21:53:42.93#ibcon#enter sib2, iclass 11, count 0 2006.201.21:53:42.93#ibcon#flushed, iclass 11, count 0 2006.201.21:53:42.93#ibcon#about to write, iclass 11, count 0 2006.201.21:53:42.93#ibcon#wrote, iclass 11, count 0 2006.201.21:53:42.93#ibcon#about to read 3, iclass 11, count 0 2006.201.21:53:42.96#ibcon#read 3, iclass 11, count 0 2006.201.21:53:42.96#ibcon#about to read 4, iclass 11, count 0 2006.201.21:53:42.96#ibcon#read 4, iclass 11, count 0 2006.201.21:53:42.96#ibcon#about to read 5, iclass 11, count 0 2006.201.21:53:42.96#ibcon#read 5, iclass 11, count 0 2006.201.21:53:42.96#ibcon#about to read 6, iclass 11, count 0 2006.201.21:53:42.96#ibcon#read 6, iclass 11, count 0 2006.201.21:53:42.96#ibcon#end of sib2, iclass 11, count 0 2006.201.21:53:42.96#ibcon#*after write, iclass 11, count 0 2006.201.21:53:42.96#ibcon#*before return 0, iclass 11, count 0 2006.201.21:53:42.96#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:42.96#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:42.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.21:53:42.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.21:53:42.96$vck44/valo=7,864.99 2006.201.21:53:42.96#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.21:53:42.96#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.21:53:42.96#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:42.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:42.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:42.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:42.96#ibcon#enter wrdev, iclass 13, count 0 2006.201.21:53:42.96#ibcon#first serial, iclass 13, count 0 2006.201.21:53:42.96#ibcon#enter sib2, iclass 13, count 0 2006.201.21:53:42.96#ibcon#flushed, iclass 13, count 0 2006.201.21:53:42.96#ibcon#about to write, iclass 13, count 0 2006.201.21:53:42.96#ibcon#wrote, iclass 13, count 0 2006.201.21:53:42.96#ibcon#about to read 3, iclass 13, count 0 2006.201.21:53:42.98#ibcon#read 3, iclass 13, count 0 2006.201.21:53:42.98#ibcon#about to read 4, iclass 13, count 0 2006.201.21:53:42.98#ibcon#read 4, iclass 13, count 0 2006.201.21:53:42.98#ibcon#about to read 5, iclass 13, count 0 2006.201.21:53:42.98#ibcon#read 5, iclass 13, count 0 2006.201.21:53:42.98#ibcon#about to read 6, iclass 13, count 0 2006.201.21:53:42.98#ibcon#read 6, iclass 13, count 0 2006.201.21:53:42.98#ibcon#end of sib2, iclass 13, count 0 2006.201.21:53:42.98#ibcon#*mode == 0, iclass 13, count 0 2006.201.21:53:42.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.21:53:42.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.21:53:42.98#ibcon#*before write, iclass 13, count 0 2006.201.21:53:42.98#ibcon#enter sib2, iclass 13, count 0 2006.201.21:53:42.98#ibcon#flushed, iclass 13, count 0 2006.201.21:53:42.98#ibcon#about to write, iclass 13, count 0 2006.201.21:53:42.98#ibcon#wrote, iclass 13, count 0 2006.201.21:53:42.98#ibcon#about to read 3, iclass 13, count 0 2006.201.21:53:43.03#ibcon#read 3, iclass 13, count 0 2006.201.21:53:43.03#ibcon#about to read 4, iclass 13, count 0 2006.201.21:53:43.03#ibcon#read 4, iclass 13, count 0 2006.201.21:53:43.03#ibcon#about to read 5, iclass 13, count 0 2006.201.21:53:43.03#ibcon#read 5, iclass 13, count 0 2006.201.21:53:43.03#ibcon#about to read 6, iclass 13, count 0 2006.201.21:53:43.03#ibcon#read 6, iclass 13, count 0 2006.201.21:53:43.03#ibcon#end of sib2, iclass 13, count 0 2006.201.21:53:43.03#ibcon#*after write, iclass 13, count 0 2006.201.21:53:43.03#ibcon#*before return 0, iclass 13, count 0 2006.201.21:53:43.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:43.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:43.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.21:53:43.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.21:53:43.03$vck44/va=7,5 2006.201.21:53:43.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.21:53:43.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.21:53:43.03#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:43.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:43.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:43.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:43.08#ibcon#enter wrdev, iclass 15, count 2 2006.201.21:53:43.08#ibcon#first serial, iclass 15, count 2 2006.201.21:53:43.08#ibcon#enter sib2, iclass 15, count 2 2006.201.21:53:43.08#ibcon#flushed, iclass 15, count 2 2006.201.21:53:43.08#ibcon#about to write, iclass 15, count 2 2006.201.21:53:43.08#ibcon#wrote, iclass 15, count 2 2006.201.21:53:43.08#ibcon#about to read 3, iclass 15, count 2 2006.201.21:53:43.10#ibcon#read 3, iclass 15, count 2 2006.201.21:53:43.10#ibcon#about to read 4, iclass 15, count 2 2006.201.21:53:43.10#ibcon#read 4, iclass 15, count 2 2006.201.21:53:43.10#ibcon#about to read 5, iclass 15, count 2 2006.201.21:53:43.10#ibcon#read 5, iclass 15, count 2 2006.201.21:53:43.10#ibcon#about to read 6, iclass 15, count 2 2006.201.21:53:43.10#ibcon#read 6, iclass 15, count 2 2006.201.21:53:43.10#ibcon#end of sib2, iclass 15, count 2 2006.201.21:53:43.10#ibcon#*mode == 0, iclass 15, count 2 2006.201.21:53:43.10#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.21:53:43.10#ibcon#[25=AT07-05\r\n] 2006.201.21:53:43.10#ibcon#*before write, iclass 15, count 2 2006.201.21:53:43.10#ibcon#enter sib2, iclass 15, count 2 2006.201.21:53:43.10#ibcon#flushed, iclass 15, count 2 2006.201.21:53:43.10#ibcon#about to write, iclass 15, count 2 2006.201.21:53:43.10#ibcon#wrote, iclass 15, count 2 2006.201.21:53:43.10#ibcon#about to read 3, iclass 15, count 2 2006.201.21:53:43.13#ibcon#read 3, iclass 15, count 2 2006.201.21:53:43.13#ibcon#about to read 4, iclass 15, count 2 2006.201.21:53:43.13#ibcon#read 4, iclass 15, count 2 2006.201.21:53:43.13#ibcon#about to read 5, iclass 15, count 2 2006.201.21:53:43.13#ibcon#read 5, iclass 15, count 2 2006.201.21:53:43.13#ibcon#about to read 6, iclass 15, count 2 2006.201.21:53:43.13#ibcon#read 6, iclass 15, count 2 2006.201.21:53:43.13#ibcon#end of sib2, iclass 15, count 2 2006.201.21:53:43.13#ibcon#*after write, iclass 15, count 2 2006.201.21:53:43.13#ibcon#*before return 0, iclass 15, count 2 2006.201.21:53:43.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:43.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:43.13#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.21:53:43.13#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:43.13#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:43.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:43.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:43.25#ibcon#enter wrdev, iclass 15, count 0 2006.201.21:53:43.25#ibcon#first serial, iclass 15, count 0 2006.201.21:53:43.25#ibcon#enter sib2, iclass 15, count 0 2006.201.21:53:43.25#ibcon#flushed, iclass 15, count 0 2006.201.21:53:43.25#ibcon#about to write, iclass 15, count 0 2006.201.21:53:43.25#ibcon#wrote, iclass 15, count 0 2006.201.21:53:43.25#ibcon#about to read 3, iclass 15, count 0 2006.201.21:53:43.27#ibcon#read 3, iclass 15, count 0 2006.201.21:53:43.27#ibcon#about to read 4, iclass 15, count 0 2006.201.21:53:43.27#ibcon#read 4, iclass 15, count 0 2006.201.21:53:43.27#ibcon#about to read 5, iclass 15, count 0 2006.201.21:53:43.27#ibcon#read 5, iclass 15, count 0 2006.201.21:53:43.27#ibcon#about to read 6, iclass 15, count 0 2006.201.21:53:43.27#ibcon#read 6, iclass 15, count 0 2006.201.21:53:43.27#ibcon#end of sib2, iclass 15, count 0 2006.201.21:53:43.27#ibcon#*mode == 0, iclass 15, count 0 2006.201.21:53:43.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.21:53:43.27#ibcon#[25=USB\r\n] 2006.201.21:53:43.27#ibcon#*before write, iclass 15, count 0 2006.201.21:53:43.27#ibcon#enter sib2, iclass 15, count 0 2006.201.21:53:43.27#ibcon#flushed, iclass 15, count 0 2006.201.21:53:43.27#ibcon#about to write, iclass 15, count 0 2006.201.21:53:43.27#ibcon#wrote, iclass 15, count 0 2006.201.21:53:43.27#ibcon#about to read 3, iclass 15, count 0 2006.201.21:53:43.30#ibcon#read 3, iclass 15, count 0 2006.201.21:53:43.30#ibcon#about to read 4, iclass 15, count 0 2006.201.21:53:43.30#ibcon#read 4, iclass 15, count 0 2006.201.21:53:43.30#ibcon#about to read 5, iclass 15, count 0 2006.201.21:53:43.30#ibcon#read 5, iclass 15, count 0 2006.201.21:53:43.30#ibcon#about to read 6, iclass 15, count 0 2006.201.21:53:43.30#ibcon#read 6, iclass 15, count 0 2006.201.21:53:43.30#ibcon#end of sib2, iclass 15, count 0 2006.201.21:53:43.30#ibcon#*after write, iclass 15, count 0 2006.201.21:53:43.30#ibcon#*before return 0, iclass 15, count 0 2006.201.21:53:43.30#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:43.30#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:43.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.21:53:43.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.21:53:43.30$vck44/valo=8,884.99 2006.201.21:53:43.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.21:53:43.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.21:53:43.30#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:43.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:43.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:43.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:43.30#ibcon#enter wrdev, iclass 17, count 0 2006.201.21:53:43.30#ibcon#first serial, iclass 17, count 0 2006.201.21:53:43.30#ibcon#enter sib2, iclass 17, count 0 2006.201.21:53:43.30#ibcon#flushed, iclass 17, count 0 2006.201.21:53:43.30#ibcon#about to write, iclass 17, count 0 2006.201.21:53:43.30#ibcon#wrote, iclass 17, count 0 2006.201.21:53:43.30#ibcon#about to read 3, iclass 17, count 0 2006.201.21:53:43.32#ibcon#read 3, iclass 17, count 0 2006.201.21:53:43.32#ibcon#about to read 4, iclass 17, count 0 2006.201.21:53:43.32#ibcon#read 4, iclass 17, count 0 2006.201.21:53:43.32#ibcon#about to read 5, iclass 17, count 0 2006.201.21:53:43.32#ibcon#read 5, iclass 17, count 0 2006.201.21:53:43.32#ibcon#about to read 6, iclass 17, count 0 2006.201.21:53:43.32#ibcon#read 6, iclass 17, count 0 2006.201.21:53:43.32#ibcon#end of sib2, iclass 17, count 0 2006.201.21:53:43.32#ibcon#*mode == 0, iclass 17, count 0 2006.201.21:53:43.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.21:53:43.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.21:53:43.32#ibcon#*before write, iclass 17, count 0 2006.201.21:53:43.32#ibcon#enter sib2, iclass 17, count 0 2006.201.21:53:43.32#ibcon#flushed, iclass 17, count 0 2006.201.21:53:43.32#ibcon#about to write, iclass 17, count 0 2006.201.21:53:43.32#ibcon#wrote, iclass 17, count 0 2006.201.21:53:43.32#ibcon#about to read 3, iclass 17, count 0 2006.201.21:53:43.36#ibcon#read 3, iclass 17, count 0 2006.201.21:53:43.36#ibcon#about to read 4, iclass 17, count 0 2006.201.21:53:43.36#ibcon#read 4, iclass 17, count 0 2006.201.21:53:43.36#ibcon#about to read 5, iclass 17, count 0 2006.201.21:53:43.36#ibcon#read 5, iclass 17, count 0 2006.201.21:53:43.36#ibcon#about to read 6, iclass 17, count 0 2006.201.21:53:43.36#ibcon#read 6, iclass 17, count 0 2006.201.21:53:43.36#ibcon#end of sib2, iclass 17, count 0 2006.201.21:53:43.36#ibcon#*after write, iclass 17, count 0 2006.201.21:53:43.36#ibcon#*before return 0, iclass 17, count 0 2006.201.21:53:43.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:43.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:43.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.21:53:43.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.21:53:43.36$vck44/va=8,4 2006.201.21:53:43.36#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.21:53:43.36#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.21:53:43.36#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:43.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:53:43.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:53:43.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:53:43.42#ibcon#enter wrdev, iclass 19, count 2 2006.201.21:53:43.42#ibcon#first serial, iclass 19, count 2 2006.201.21:53:43.42#ibcon#enter sib2, iclass 19, count 2 2006.201.21:53:43.42#ibcon#flushed, iclass 19, count 2 2006.201.21:53:43.42#ibcon#about to write, iclass 19, count 2 2006.201.21:53:43.42#ibcon#wrote, iclass 19, count 2 2006.201.21:53:43.42#ibcon#about to read 3, iclass 19, count 2 2006.201.21:53:43.44#ibcon#read 3, iclass 19, count 2 2006.201.21:53:43.44#ibcon#about to read 4, iclass 19, count 2 2006.201.21:53:43.44#ibcon#read 4, iclass 19, count 2 2006.201.21:53:43.44#ibcon#about to read 5, iclass 19, count 2 2006.201.21:53:43.44#ibcon#read 5, iclass 19, count 2 2006.201.21:53:43.44#ibcon#about to read 6, iclass 19, count 2 2006.201.21:53:43.44#ibcon#read 6, iclass 19, count 2 2006.201.21:53:43.44#ibcon#end of sib2, iclass 19, count 2 2006.201.21:53:43.44#ibcon#*mode == 0, iclass 19, count 2 2006.201.21:53:43.44#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.21:53:43.44#ibcon#[25=AT08-04\r\n] 2006.201.21:53:43.44#ibcon#*before write, iclass 19, count 2 2006.201.21:53:43.44#ibcon#enter sib2, iclass 19, count 2 2006.201.21:53:43.44#ibcon#flushed, iclass 19, count 2 2006.201.21:53:43.44#ibcon#about to write, iclass 19, count 2 2006.201.21:53:43.44#ibcon#wrote, iclass 19, count 2 2006.201.21:53:43.44#ibcon#about to read 3, iclass 19, count 2 2006.201.21:53:43.47#ibcon#read 3, iclass 19, count 2 2006.201.21:53:43.47#ibcon#about to read 4, iclass 19, count 2 2006.201.21:53:43.47#ibcon#read 4, iclass 19, count 2 2006.201.21:53:43.47#ibcon#about to read 5, iclass 19, count 2 2006.201.21:53:43.47#ibcon#read 5, iclass 19, count 2 2006.201.21:53:43.47#ibcon#about to read 6, iclass 19, count 2 2006.201.21:53:43.47#ibcon#read 6, iclass 19, count 2 2006.201.21:53:43.47#ibcon#end of sib2, iclass 19, count 2 2006.201.21:53:43.47#ibcon#*after write, iclass 19, count 2 2006.201.21:53:43.47#ibcon#*before return 0, iclass 19, count 2 2006.201.21:53:43.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:53:43.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.21:53:43.47#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.21:53:43.47#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:43.47#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:53:43.59#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:53:43.59#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:53:43.59#ibcon#enter wrdev, iclass 19, count 0 2006.201.21:53:43.59#ibcon#first serial, iclass 19, count 0 2006.201.21:53:43.59#ibcon#enter sib2, iclass 19, count 0 2006.201.21:53:43.59#ibcon#flushed, iclass 19, count 0 2006.201.21:53:43.59#ibcon#about to write, iclass 19, count 0 2006.201.21:53:43.59#ibcon#wrote, iclass 19, count 0 2006.201.21:53:43.59#ibcon#about to read 3, iclass 19, count 0 2006.201.21:53:43.61#ibcon#read 3, iclass 19, count 0 2006.201.21:53:43.61#ibcon#about to read 4, iclass 19, count 0 2006.201.21:53:43.61#ibcon#read 4, iclass 19, count 0 2006.201.21:53:43.61#ibcon#about to read 5, iclass 19, count 0 2006.201.21:53:43.61#ibcon#read 5, iclass 19, count 0 2006.201.21:53:43.61#ibcon#about to read 6, iclass 19, count 0 2006.201.21:53:43.61#ibcon#read 6, iclass 19, count 0 2006.201.21:53:43.61#ibcon#end of sib2, iclass 19, count 0 2006.201.21:53:43.61#ibcon#*mode == 0, iclass 19, count 0 2006.201.21:53:43.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.21:53:43.61#ibcon#[25=USB\r\n] 2006.201.21:53:43.61#ibcon#*before write, iclass 19, count 0 2006.201.21:53:43.61#ibcon#enter sib2, iclass 19, count 0 2006.201.21:53:43.61#ibcon#flushed, iclass 19, count 0 2006.201.21:53:43.61#ibcon#about to write, iclass 19, count 0 2006.201.21:53:43.61#ibcon#wrote, iclass 19, count 0 2006.201.21:53:43.61#ibcon#about to read 3, iclass 19, count 0 2006.201.21:53:43.64#ibcon#read 3, iclass 19, count 0 2006.201.21:53:43.64#ibcon#about to read 4, iclass 19, count 0 2006.201.21:53:43.64#ibcon#read 4, iclass 19, count 0 2006.201.21:53:43.64#ibcon#about to read 5, iclass 19, count 0 2006.201.21:53:43.64#ibcon#read 5, iclass 19, count 0 2006.201.21:53:43.64#ibcon#about to read 6, iclass 19, count 0 2006.201.21:53:43.64#ibcon#read 6, iclass 19, count 0 2006.201.21:53:43.64#ibcon#end of sib2, iclass 19, count 0 2006.201.21:53:43.64#ibcon#*after write, iclass 19, count 0 2006.201.21:53:43.64#ibcon#*before return 0, iclass 19, count 0 2006.201.21:53:43.64#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:53:43.64#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.21:53:43.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.21:53:43.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.21:53:43.64$vck44/vblo=1,629.99 2006.201.21:53:43.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.21:53:43.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.21:53:43.64#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:43.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:53:43.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:53:43.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:53:43.64#ibcon#enter wrdev, iclass 21, count 0 2006.201.21:53:43.64#ibcon#first serial, iclass 21, count 0 2006.201.21:53:43.64#ibcon#enter sib2, iclass 21, count 0 2006.201.21:53:43.64#ibcon#flushed, iclass 21, count 0 2006.201.21:53:43.64#ibcon#about to write, iclass 21, count 0 2006.201.21:53:43.64#ibcon#wrote, iclass 21, count 0 2006.201.21:53:43.64#ibcon#about to read 3, iclass 21, count 0 2006.201.21:53:43.66#ibcon#read 3, iclass 21, count 0 2006.201.21:53:43.66#ibcon#about to read 4, iclass 21, count 0 2006.201.21:53:43.66#ibcon#read 4, iclass 21, count 0 2006.201.21:53:43.66#ibcon#about to read 5, iclass 21, count 0 2006.201.21:53:43.66#ibcon#read 5, iclass 21, count 0 2006.201.21:53:43.66#ibcon#about to read 6, iclass 21, count 0 2006.201.21:53:43.66#ibcon#read 6, iclass 21, count 0 2006.201.21:53:43.66#ibcon#end of sib2, iclass 21, count 0 2006.201.21:53:43.66#ibcon#*mode == 0, iclass 21, count 0 2006.201.21:53:43.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.21:53:43.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.21:53:43.66#ibcon#*before write, iclass 21, count 0 2006.201.21:53:43.66#ibcon#enter sib2, iclass 21, count 0 2006.201.21:53:43.66#ibcon#flushed, iclass 21, count 0 2006.201.21:53:43.66#ibcon#about to write, iclass 21, count 0 2006.201.21:53:43.66#ibcon#wrote, iclass 21, count 0 2006.201.21:53:43.66#ibcon#about to read 3, iclass 21, count 0 2006.201.21:53:43.71#ibcon#read 3, iclass 21, count 0 2006.201.21:53:43.71#ibcon#about to read 4, iclass 21, count 0 2006.201.21:53:43.71#ibcon#read 4, iclass 21, count 0 2006.201.21:53:43.71#ibcon#about to read 5, iclass 21, count 0 2006.201.21:53:43.71#ibcon#read 5, iclass 21, count 0 2006.201.21:53:43.71#ibcon#about to read 6, iclass 21, count 0 2006.201.21:53:43.71#ibcon#read 6, iclass 21, count 0 2006.201.21:53:43.71#ibcon#end of sib2, iclass 21, count 0 2006.201.21:53:43.71#ibcon#*after write, iclass 21, count 0 2006.201.21:53:43.71#ibcon#*before return 0, iclass 21, count 0 2006.201.21:53:43.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:53:43.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.21:53:43.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.21:53:43.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.21:53:43.71$vck44/vb=1,4 2006.201.21:53:43.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.21:53:43.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.21:53:43.71#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:43.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:53:43.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:53:43.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:53:43.71#ibcon#enter wrdev, iclass 23, count 2 2006.201.21:53:43.71#ibcon#first serial, iclass 23, count 2 2006.201.21:53:43.71#ibcon#enter sib2, iclass 23, count 2 2006.201.21:53:43.71#ibcon#flushed, iclass 23, count 2 2006.201.21:53:43.71#ibcon#about to write, iclass 23, count 2 2006.201.21:53:43.71#ibcon#wrote, iclass 23, count 2 2006.201.21:53:43.71#ibcon#about to read 3, iclass 23, count 2 2006.201.21:53:43.73#ibcon#read 3, iclass 23, count 2 2006.201.21:53:43.73#ibcon#about to read 4, iclass 23, count 2 2006.201.21:53:43.73#ibcon#read 4, iclass 23, count 2 2006.201.21:53:43.73#ibcon#about to read 5, iclass 23, count 2 2006.201.21:53:43.73#ibcon#read 5, iclass 23, count 2 2006.201.21:53:43.73#ibcon#about to read 6, iclass 23, count 2 2006.201.21:53:43.73#ibcon#read 6, iclass 23, count 2 2006.201.21:53:43.73#ibcon#end of sib2, iclass 23, count 2 2006.201.21:53:43.73#ibcon#*mode == 0, iclass 23, count 2 2006.201.21:53:43.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.21:53:43.73#ibcon#[27=AT01-04\r\n] 2006.201.21:53:43.73#ibcon#*before write, iclass 23, count 2 2006.201.21:53:43.73#ibcon#enter sib2, iclass 23, count 2 2006.201.21:53:43.73#ibcon#flushed, iclass 23, count 2 2006.201.21:53:43.73#ibcon#about to write, iclass 23, count 2 2006.201.21:53:43.73#ibcon#wrote, iclass 23, count 2 2006.201.21:53:43.73#ibcon#about to read 3, iclass 23, count 2 2006.201.21:53:43.76#ibcon#read 3, iclass 23, count 2 2006.201.21:53:43.76#ibcon#about to read 4, iclass 23, count 2 2006.201.21:53:43.76#ibcon#read 4, iclass 23, count 2 2006.201.21:53:43.76#ibcon#about to read 5, iclass 23, count 2 2006.201.21:53:43.76#ibcon#read 5, iclass 23, count 2 2006.201.21:53:43.76#ibcon#about to read 6, iclass 23, count 2 2006.201.21:53:43.76#ibcon#read 6, iclass 23, count 2 2006.201.21:53:43.76#ibcon#end of sib2, iclass 23, count 2 2006.201.21:53:43.76#ibcon#*after write, iclass 23, count 2 2006.201.21:53:43.76#ibcon#*before return 0, iclass 23, count 2 2006.201.21:53:43.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:53:43.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.21:53:43.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.21:53:43.76#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:43.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:53:43.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:53:43.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:53:43.88#ibcon#enter wrdev, iclass 23, count 0 2006.201.21:53:43.88#ibcon#first serial, iclass 23, count 0 2006.201.21:53:43.88#ibcon#enter sib2, iclass 23, count 0 2006.201.21:53:43.88#ibcon#flushed, iclass 23, count 0 2006.201.21:53:43.88#ibcon#about to write, iclass 23, count 0 2006.201.21:53:43.88#ibcon#wrote, iclass 23, count 0 2006.201.21:53:43.88#ibcon#about to read 3, iclass 23, count 0 2006.201.21:53:43.90#ibcon#read 3, iclass 23, count 0 2006.201.21:53:43.90#ibcon#about to read 4, iclass 23, count 0 2006.201.21:53:43.90#ibcon#read 4, iclass 23, count 0 2006.201.21:53:43.90#ibcon#about to read 5, iclass 23, count 0 2006.201.21:53:43.90#ibcon#read 5, iclass 23, count 0 2006.201.21:53:43.90#ibcon#about to read 6, iclass 23, count 0 2006.201.21:53:43.90#ibcon#read 6, iclass 23, count 0 2006.201.21:53:43.90#ibcon#end of sib2, iclass 23, count 0 2006.201.21:53:43.90#ibcon#*mode == 0, iclass 23, count 0 2006.201.21:53:43.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.21:53:43.90#ibcon#[27=USB\r\n] 2006.201.21:53:43.90#ibcon#*before write, iclass 23, count 0 2006.201.21:53:43.90#ibcon#enter sib2, iclass 23, count 0 2006.201.21:53:43.90#ibcon#flushed, iclass 23, count 0 2006.201.21:53:43.90#ibcon#about to write, iclass 23, count 0 2006.201.21:53:43.90#ibcon#wrote, iclass 23, count 0 2006.201.21:53:43.90#ibcon#about to read 3, iclass 23, count 0 2006.201.21:53:43.93#ibcon#read 3, iclass 23, count 0 2006.201.21:53:43.93#ibcon#about to read 4, iclass 23, count 0 2006.201.21:53:43.93#ibcon#read 4, iclass 23, count 0 2006.201.21:53:43.93#ibcon#about to read 5, iclass 23, count 0 2006.201.21:53:43.93#ibcon#read 5, iclass 23, count 0 2006.201.21:53:43.93#ibcon#about to read 6, iclass 23, count 0 2006.201.21:53:43.93#ibcon#read 6, iclass 23, count 0 2006.201.21:53:43.93#ibcon#end of sib2, iclass 23, count 0 2006.201.21:53:43.93#ibcon#*after write, iclass 23, count 0 2006.201.21:53:43.93#ibcon#*before return 0, iclass 23, count 0 2006.201.21:53:43.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:53:43.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.21:53:43.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.21:53:43.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.21:53:43.93$vck44/vblo=2,634.99 2006.201.21:53:43.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.21:53:43.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.21:53:43.93#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:43.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:43.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:43.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:43.93#ibcon#enter wrdev, iclass 25, count 0 2006.201.21:53:43.93#ibcon#first serial, iclass 25, count 0 2006.201.21:53:43.93#ibcon#enter sib2, iclass 25, count 0 2006.201.21:53:43.93#ibcon#flushed, iclass 25, count 0 2006.201.21:53:43.93#ibcon#about to write, iclass 25, count 0 2006.201.21:53:43.93#ibcon#wrote, iclass 25, count 0 2006.201.21:53:43.93#ibcon#about to read 3, iclass 25, count 0 2006.201.21:53:43.95#ibcon#read 3, iclass 25, count 0 2006.201.21:53:43.95#ibcon#about to read 4, iclass 25, count 0 2006.201.21:53:43.95#ibcon#read 4, iclass 25, count 0 2006.201.21:53:43.95#ibcon#about to read 5, iclass 25, count 0 2006.201.21:53:43.95#ibcon#read 5, iclass 25, count 0 2006.201.21:53:43.95#ibcon#about to read 6, iclass 25, count 0 2006.201.21:53:43.95#ibcon#read 6, iclass 25, count 0 2006.201.21:53:43.95#ibcon#end of sib2, iclass 25, count 0 2006.201.21:53:43.95#ibcon#*mode == 0, iclass 25, count 0 2006.201.21:53:43.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.21:53:43.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.21:53:43.95#ibcon#*before write, iclass 25, count 0 2006.201.21:53:43.95#ibcon#enter sib2, iclass 25, count 0 2006.201.21:53:43.95#ibcon#flushed, iclass 25, count 0 2006.201.21:53:43.95#ibcon#about to write, iclass 25, count 0 2006.201.21:53:43.95#ibcon#wrote, iclass 25, count 0 2006.201.21:53:43.95#ibcon#about to read 3, iclass 25, count 0 2006.201.21:53:43.99#ibcon#read 3, iclass 25, count 0 2006.201.21:53:43.99#ibcon#about to read 4, iclass 25, count 0 2006.201.21:53:43.99#ibcon#read 4, iclass 25, count 0 2006.201.21:53:43.99#ibcon#about to read 5, iclass 25, count 0 2006.201.21:53:43.99#ibcon#read 5, iclass 25, count 0 2006.201.21:53:43.99#ibcon#about to read 6, iclass 25, count 0 2006.201.21:53:43.99#ibcon#read 6, iclass 25, count 0 2006.201.21:53:43.99#ibcon#end of sib2, iclass 25, count 0 2006.201.21:53:43.99#ibcon#*after write, iclass 25, count 0 2006.201.21:53:43.99#ibcon#*before return 0, iclass 25, count 0 2006.201.21:53:43.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:43.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.21:53:43.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.21:53:43.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.21:53:43.99$vck44/vb=2,5 2006.201.21:53:43.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.21:53:43.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.21:53:43.99#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:43.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:44.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:44.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:44.05#ibcon#enter wrdev, iclass 27, count 2 2006.201.21:53:44.05#ibcon#first serial, iclass 27, count 2 2006.201.21:53:44.05#ibcon#enter sib2, iclass 27, count 2 2006.201.21:53:44.05#ibcon#flushed, iclass 27, count 2 2006.201.21:53:44.05#ibcon#about to write, iclass 27, count 2 2006.201.21:53:44.05#ibcon#wrote, iclass 27, count 2 2006.201.21:53:44.05#ibcon#about to read 3, iclass 27, count 2 2006.201.21:53:44.07#ibcon#read 3, iclass 27, count 2 2006.201.21:53:44.07#ibcon#about to read 4, iclass 27, count 2 2006.201.21:53:44.07#ibcon#read 4, iclass 27, count 2 2006.201.21:53:44.07#ibcon#about to read 5, iclass 27, count 2 2006.201.21:53:44.07#ibcon#read 5, iclass 27, count 2 2006.201.21:53:44.07#ibcon#about to read 6, iclass 27, count 2 2006.201.21:53:44.07#ibcon#read 6, iclass 27, count 2 2006.201.21:53:44.07#ibcon#end of sib2, iclass 27, count 2 2006.201.21:53:44.07#ibcon#*mode == 0, iclass 27, count 2 2006.201.21:53:44.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.21:53:44.07#ibcon#[27=AT02-05\r\n] 2006.201.21:53:44.07#ibcon#*before write, iclass 27, count 2 2006.201.21:53:44.07#ibcon#enter sib2, iclass 27, count 2 2006.201.21:53:44.07#ibcon#flushed, iclass 27, count 2 2006.201.21:53:44.07#ibcon#about to write, iclass 27, count 2 2006.201.21:53:44.07#ibcon#wrote, iclass 27, count 2 2006.201.21:53:44.07#ibcon#about to read 3, iclass 27, count 2 2006.201.21:53:44.10#ibcon#read 3, iclass 27, count 2 2006.201.21:53:44.10#ibcon#about to read 4, iclass 27, count 2 2006.201.21:53:44.10#ibcon#read 4, iclass 27, count 2 2006.201.21:53:44.10#ibcon#about to read 5, iclass 27, count 2 2006.201.21:53:44.10#ibcon#read 5, iclass 27, count 2 2006.201.21:53:44.10#ibcon#about to read 6, iclass 27, count 2 2006.201.21:53:44.10#ibcon#read 6, iclass 27, count 2 2006.201.21:53:44.10#ibcon#end of sib2, iclass 27, count 2 2006.201.21:53:44.10#ibcon#*after write, iclass 27, count 2 2006.201.21:53:44.10#ibcon#*before return 0, iclass 27, count 2 2006.201.21:53:44.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:44.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.21:53:44.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.21:53:44.10#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:44.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:44.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:44.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:44.22#ibcon#enter wrdev, iclass 27, count 0 2006.201.21:53:44.22#ibcon#first serial, iclass 27, count 0 2006.201.21:53:44.22#ibcon#enter sib2, iclass 27, count 0 2006.201.21:53:44.22#ibcon#flushed, iclass 27, count 0 2006.201.21:53:44.22#ibcon#about to write, iclass 27, count 0 2006.201.21:53:44.22#ibcon#wrote, iclass 27, count 0 2006.201.21:53:44.22#ibcon#about to read 3, iclass 27, count 0 2006.201.21:53:44.24#ibcon#read 3, iclass 27, count 0 2006.201.21:53:44.24#ibcon#about to read 4, iclass 27, count 0 2006.201.21:53:44.24#ibcon#read 4, iclass 27, count 0 2006.201.21:53:44.24#ibcon#about to read 5, iclass 27, count 0 2006.201.21:53:44.24#ibcon#read 5, iclass 27, count 0 2006.201.21:53:44.24#ibcon#about to read 6, iclass 27, count 0 2006.201.21:53:44.24#ibcon#read 6, iclass 27, count 0 2006.201.21:53:44.24#ibcon#end of sib2, iclass 27, count 0 2006.201.21:53:44.24#ibcon#*mode == 0, iclass 27, count 0 2006.201.21:53:44.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.21:53:44.24#ibcon#[27=USB\r\n] 2006.201.21:53:44.24#ibcon#*before write, iclass 27, count 0 2006.201.21:53:44.24#ibcon#enter sib2, iclass 27, count 0 2006.201.21:53:44.24#ibcon#flushed, iclass 27, count 0 2006.201.21:53:44.24#ibcon#about to write, iclass 27, count 0 2006.201.21:53:44.24#ibcon#wrote, iclass 27, count 0 2006.201.21:53:44.24#ibcon#about to read 3, iclass 27, count 0 2006.201.21:53:44.27#ibcon#read 3, iclass 27, count 0 2006.201.21:53:44.27#ibcon#about to read 4, iclass 27, count 0 2006.201.21:53:44.27#ibcon#read 4, iclass 27, count 0 2006.201.21:53:44.27#ibcon#about to read 5, iclass 27, count 0 2006.201.21:53:44.27#ibcon#read 5, iclass 27, count 0 2006.201.21:53:44.27#ibcon#about to read 6, iclass 27, count 0 2006.201.21:53:44.27#ibcon#read 6, iclass 27, count 0 2006.201.21:53:44.27#ibcon#end of sib2, iclass 27, count 0 2006.201.21:53:44.27#ibcon#*after write, iclass 27, count 0 2006.201.21:53:44.27#ibcon#*before return 0, iclass 27, count 0 2006.201.21:53:44.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:44.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.21:53:44.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.21:53:44.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.21:53:44.27$vck44/vblo=3,649.99 2006.201.21:53:44.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.21:53:44.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.21:53:44.27#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:44.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:44.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:44.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:44.27#ibcon#enter wrdev, iclass 29, count 0 2006.201.21:53:44.27#ibcon#first serial, iclass 29, count 0 2006.201.21:53:44.27#ibcon#enter sib2, iclass 29, count 0 2006.201.21:53:44.27#ibcon#flushed, iclass 29, count 0 2006.201.21:53:44.27#ibcon#about to write, iclass 29, count 0 2006.201.21:53:44.27#ibcon#wrote, iclass 29, count 0 2006.201.21:53:44.27#ibcon#about to read 3, iclass 29, count 0 2006.201.21:53:44.29#ibcon#read 3, iclass 29, count 0 2006.201.21:53:44.29#ibcon#about to read 4, iclass 29, count 0 2006.201.21:53:44.29#ibcon#read 4, iclass 29, count 0 2006.201.21:53:44.29#ibcon#about to read 5, iclass 29, count 0 2006.201.21:53:44.29#ibcon#read 5, iclass 29, count 0 2006.201.21:53:44.29#ibcon#about to read 6, iclass 29, count 0 2006.201.21:53:44.29#ibcon#read 6, iclass 29, count 0 2006.201.21:53:44.29#ibcon#end of sib2, iclass 29, count 0 2006.201.21:53:44.29#ibcon#*mode == 0, iclass 29, count 0 2006.201.21:53:44.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.21:53:44.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.21:53:44.29#ibcon#*before write, iclass 29, count 0 2006.201.21:53:44.29#ibcon#enter sib2, iclass 29, count 0 2006.201.21:53:44.29#ibcon#flushed, iclass 29, count 0 2006.201.21:53:44.29#ibcon#about to write, iclass 29, count 0 2006.201.21:53:44.29#ibcon#wrote, iclass 29, count 0 2006.201.21:53:44.29#ibcon#about to read 3, iclass 29, count 0 2006.201.21:53:44.33#ibcon#read 3, iclass 29, count 0 2006.201.21:53:44.33#ibcon#about to read 4, iclass 29, count 0 2006.201.21:53:44.33#ibcon#read 4, iclass 29, count 0 2006.201.21:53:44.33#ibcon#about to read 5, iclass 29, count 0 2006.201.21:53:44.33#ibcon#read 5, iclass 29, count 0 2006.201.21:53:44.33#ibcon#about to read 6, iclass 29, count 0 2006.201.21:53:44.33#ibcon#read 6, iclass 29, count 0 2006.201.21:53:44.33#ibcon#end of sib2, iclass 29, count 0 2006.201.21:53:44.33#ibcon#*after write, iclass 29, count 0 2006.201.21:53:44.33#ibcon#*before return 0, iclass 29, count 0 2006.201.21:53:44.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:44.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.21:53:44.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.21:53:44.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.21:53:44.33$vck44/vb=3,4 2006.201.21:53:44.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.21:53:44.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.21:53:44.33#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:44.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:44.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:44.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:44.39#ibcon#enter wrdev, iclass 31, count 2 2006.201.21:53:44.39#ibcon#first serial, iclass 31, count 2 2006.201.21:53:44.39#ibcon#enter sib2, iclass 31, count 2 2006.201.21:53:44.39#ibcon#flushed, iclass 31, count 2 2006.201.21:53:44.39#ibcon#about to write, iclass 31, count 2 2006.201.21:53:44.39#ibcon#wrote, iclass 31, count 2 2006.201.21:53:44.39#ibcon#about to read 3, iclass 31, count 2 2006.201.21:53:44.41#ibcon#read 3, iclass 31, count 2 2006.201.21:53:44.41#ibcon#about to read 4, iclass 31, count 2 2006.201.21:53:44.41#ibcon#read 4, iclass 31, count 2 2006.201.21:53:44.41#ibcon#about to read 5, iclass 31, count 2 2006.201.21:53:44.41#ibcon#read 5, iclass 31, count 2 2006.201.21:53:44.41#ibcon#about to read 6, iclass 31, count 2 2006.201.21:53:44.41#ibcon#read 6, iclass 31, count 2 2006.201.21:53:44.41#ibcon#end of sib2, iclass 31, count 2 2006.201.21:53:44.41#ibcon#*mode == 0, iclass 31, count 2 2006.201.21:53:44.41#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.21:53:44.41#ibcon#[27=AT03-04\r\n] 2006.201.21:53:44.41#ibcon#*before write, iclass 31, count 2 2006.201.21:53:44.41#ibcon#enter sib2, iclass 31, count 2 2006.201.21:53:44.41#ibcon#flushed, iclass 31, count 2 2006.201.21:53:44.41#ibcon#about to write, iclass 31, count 2 2006.201.21:53:44.41#ibcon#wrote, iclass 31, count 2 2006.201.21:53:44.41#ibcon#about to read 3, iclass 31, count 2 2006.201.21:53:44.44#ibcon#read 3, iclass 31, count 2 2006.201.21:53:44.44#ibcon#about to read 4, iclass 31, count 2 2006.201.21:53:44.44#ibcon#read 4, iclass 31, count 2 2006.201.21:53:44.44#ibcon#about to read 5, iclass 31, count 2 2006.201.21:53:44.44#ibcon#read 5, iclass 31, count 2 2006.201.21:53:44.44#ibcon#about to read 6, iclass 31, count 2 2006.201.21:53:44.44#ibcon#read 6, iclass 31, count 2 2006.201.21:53:44.44#ibcon#end of sib2, iclass 31, count 2 2006.201.21:53:44.44#ibcon#*after write, iclass 31, count 2 2006.201.21:53:44.44#ibcon#*before return 0, iclass 31, count 2 2006.201.21:53:44.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:44.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.21:53:44.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.21:53:44.44#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:44.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:44.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:44.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:44.56#ibcon#enter wrdev, iclass 31, count 0 2006.201.21:53:44.56#ibcon#first serial, iclass 31, count 0 2006.201.21:53:44.56#ibcon#enter sib2, iclass 31, count 0 2006.201.21:53:44.56#ibcon#flushed, iclass 31, count 0 2006.201.21:53:44.56#ibcon#about to write, iclass 31, count 0 2006.201.21:53:44.56#ibcon#wrote, iclass 31, count 0 2006.201.21:53:44.56#ibcon#about to read 3, iclass 31, count 0 2006.201.21:53:44.58#ibcon#read 3, iclass 31, count 0 2006.201.21:53:44.58#ibcon#about to read 4, iclass 31, count 0 2006.201.21:53:44.58#ibcon#read 4, iclass 31, count 0 2006.201.21:53:44.58#ibcon#about to read 5, iclass 31, count 0 2006.201.21:53:44.58#ibcon#read 5, iclass 31, count 0 2006.201.21:53:44.58#ibcon#about to read 6, iclass 31, count 0 2006.201.21:53:44.58#ibcon#read 6, iclass 31, count 0 2006.201.21:53:44.58#ibcon#end of sib2, iclass 31, count 0 2006.201.21:53:44.58#ibcon#*mode == 0, iclass 31, count 0 2006.201.21:53:44.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.21:53:44.58#ibcon#[27=USB\r\n] 2006.201.21:53:44.58#ibcon#*before write, iclass 31, count 0 2006.201.21:53:44.58#ibcon#enter sib2, iclass 31, count 0 2006.201.21:53:44.58#ibcon#flushed, iclass 31, count 0 2006.201.21:53:44.58#ibcon#about to write, iclass 31, count 0 2006.201.21:53:44.58#ibcon#wrote, iclass 31, count 0 2006.201.21:53:44.58#ibcon#about to read 3, iclass 31, count 0 2006.201.21:53:44.61#ibcon#read 3, iclass 31, count 0 2006.201.21:53:44.61#ibcon#about to read 4, iclass 31, count 0 2006.201.21:53:44.61#ibcon#read 4, iclass 31, count 0 2006.201.21:53:44.61#ibcon#about to read 5, iclass 31, count 0 2006.201.21:53:44.61#ibcon#read 5, iclass 31, count 0 2006.201.21:53:44.61#ibcon#about to read 6, iclass 31, count 0 2006.201.21:53:44.61#ibcon#read 6, iclass 31, count 0 2006.201.21:53:44.61#ibcon#end of sib2, iclass 31, count 0 2006.201.21:53:44.61#ibcon#*after write, iclass 31, count 0 2006.201.21:53:44.61#ibcon#*before return 0, iclass 31, count 0 2006.201.21:53:44.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:44.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.21:53:44.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.21:53:44.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.21:53:44.61$vck44/vblo=4,679.99 2006.201.21:53:44.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.21:53:44.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.21:53:44.61#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:44.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:44.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:44.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:44.61#ibcon#enter wrdev, iclass 33, count 0 2006.201.21:53:44.61#ibcon#first serial, iclass 33, count 0 2006.201.21:53:44.61#ibcon#enter sib2, iclass 33, count 0 2006.201.21:53:44.61#ibcon#flushed, iclass 33, count 0 2006.201.21:53:44.61#ibcon#about to write, iclass 33, count 0 2006.201.21:53:44.61#ibcon#wrote, iclass 33, count 0 2006.201.21:53:44.61#ibcon#about to read 3, iclass 33, count 0 2006.201.21:53:44.63#ibcon#read 3, iclass 33, count 0 2006.201.21:53:44.63#ibcon#about to read 4, iclass 33, count 0 2006.201.21:53:44.63#ibcon#read 4, iclass 33, count 0 2006.201.21:53:44.63#ibcon#about to read 5, iclass 33, count 0 2006.201.21:53:44.63#ibcon#read 5, iclass 33, count 0 2006.201.21:53:44.63#ibcon#about to read 6, iclass 33, count 0 2006.201.21:53:44.63#ibcon#read 6, iclass 33, count 0 2006.201.21:53:44.63#ibcon#end of sib2, iclass 33, count 0 2006.201.21:53:44.63#ibcon#*mode == 0, iclass 33, count 0 2006.201.21:53:44.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.21:53:44.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.21:53:44.63#ibcon#*before write, iclass 33, count 0 2006.201.21:53:44.63#ibcon#enter sib2, iclass 33, count 0 2006.201.21:53:44.63#ibcon#flushed, iclass 33, count 0 2006.201.21:53:44.63#ibcon#about to write, iclass 33, count 0 2006.201.21:53:44.63#ibcon#wrote, iclass 33, count 0 2006.201.21:53:44.63#ibcon#about to read 3, iclass 33, count 0 2006.201.21:53:44.68#ibcon#read 3, iclass 33, count 0 2006.201.21:53:44.68#ibcon#about to read 4, iclass 33, count 0 2006.201.21:53:44.68#ibcon#read 4, iclass 33, count 0 2006.201.21:53:44.68#ibcon#about to read 5, iclass 33, count 0 2006.201.21:53:44.68#ibcon#read 5, iclass 33, count 0 2006.201.21:53:44.68#ibcon#about to read 6, iclass 33, count 0 2006.201.21:53:44.68#ibcon#read 6, iclass 33, count 0 2006.201.21:53:44.68#ibcon#end of sib2, iclass 33, count 0 2006.201.21:53:44.68#ibcon#*after write, iclass 33, count 0 2006.201.21:53:44.68#ibcon#*before return 0, iclass 33, count 0 2006.201.21:53:44.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:44.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.21:53:44.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.21:53:44.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.21:53:44.68$vck44/vb=4,5 2006.201.21:53:44.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.21:53:44.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.21:53:44.68#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:44.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:44.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:44.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:44.73#ibcon#enter wrdev, iclass 35, count 2 2006.201.21:53:44.73#ibcon#first serial, iclass 35, count 2 2006.201.21:53:44.73#ibcon#enter sib2, iclass 35, count 2 2006.201.21:53:44.73#ibcon#flushed, iclass 35, count 2 2006.201.21:53:44.73#ibcon#about to write, iclass 35, count 2 2006.201.21:53:44.73#ibcon#wrote, iclass 35, count 2 2006.201.21:53:44.73#ibcon#about to read 3, iclass 35, count 2 2006.201.21:53:44.75#ibcon#read 3, iclass 35, count 2 2006.201.21:53:44.75#ibcon#about to read 4, iclass 35, count 2 2006.201.21:53:44.75#ibcon#read 4, iclass 35, count 2 2006.201.21:53:44.75#ibcon#about to read 5, iclass 35, count 2 2006.201.21:53:44.75#ibcon#read 5, iclass 35, count 2 2006.201.21:53:44.75#ibcon#about to read 6, iclass 35, count 2 2006.201.21:53:44.75#ibcon#read 6, iclass 35, count 2 2006.201.21:53:44.75#ibcon#end of sib2, iclass 35, count 2 2006.201.21:53:44.75#ibcon#*mode == 0, iclass 35, count 2 2006.201.21:53:44.75#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.21:53:44.75#ibcon#[27=AT04-05\r\n] 2006.201.21:53:44.75#ibcon#*before write, iclass 35, count 2 2006.201.21:53:44.75#ibcon#enter sib2, iclass 35, count 2 2006.201.21:53:44.75#ibcon#flushed, iclass 35, count 2 2006.201.21:53:44.75#ibcon#about to write, iclass 35, count 2 2006.201.21:53:44.75#ibcon#wrote, iclass 35, count 2 2006.201.21:53:44.75#ibcon#about to read 3, iclass 35, count 2 2006.201.21:53:44.78#ibcon#read 3, iclass 35, count 2 2006.201.21:53:44.78#ibcon#about to read 4, iclass 35, count 2 2006.201.21:53:44.78#ibcon#read 4, iclass 35, count 2 2006.201.21:53:44.78#ibcon#about to read 5, iclass 35, count 2 2006.201.21:53:44.78#ibcon#read 5, iclass 35, count 2 2006.201.21:53:44.78#ibcon#about to read 6, iclass 35, count 2 2006.201.21:53:44.78#ibcon#read 6, iclass 35, count 2 2006.201.21:53:44.78#ibcon#end of sib2, iclass 35, count 2 2006.201.21:53:44.78#ibcon#*after write, iclass 35, count 2 2006.201.21:53:44.78#ibcon#*before return 0, iclass 35, count 2 2006.201.21:53:44.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:44.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.21:53:44.78#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.21:53:44.78#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:44.78#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:44.90#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:44.90#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:44.90#ibcon#enter wrdev, iclass 35, count 0 2006.201.21:53:44.90#ibcon#first serial, iclass 35, count 0 2006.201.21:53:44.90#ibcon#enter sib2, iclass 35, count 0 2006.201.21:53:44.90#ibcon#flushed, iclass 35, count 0 2006.201.21:53:44.90#ibcon#about to write, iclass 35, count 0 2006.201.21:53:44.90#ibcon#wrote, iclass 35, count 0 2006.201.21:53:44.90#ibcon#about to read 3, iclass 35, count 0 2006.201.21:53:44.92#ibcon#read 3, iclass 35, count 0 2006.201.21:53:44.92#ibcon#about to read 4, iclass 35, count 0 2006.201.21:53:44.92#ibcon#read 4, iclass 35, count 0 2006.201.21:53:44.92#ibcon#about to read 5, iclass 35, count 0 2006.201.21:53:44.92#ibcon#read 5, iclass 35, count 0 2006.201.21:53:44.92#ibcon#about to read 6, iclass 35, count 0 2006.201.21:53:44.92#ibcon#read 6, iclass 35, count 0 2006.201.21:53:44.92#ibcon#end of sib2, iclass 35, count 0 2006.201.21:53:44.92#ibcon#*mode == 0, iclass 35, count 0 2006.201.21:53:44.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.21:53:44.92#ibcon#[27=USB\r\n] 2006.201.21:53:44.92#ibcon#*before write, iclass 35, count 0 2006.201.21:53:44.92#ibcon#enter sib2, iclass 35, count 0 2006.201.21:53:44.92#ibcon#flushed, iclass 35, count 0 2006.201.21:53:44.92#ibcon#about to write, iclass 35, count 0 2006.201.21:53:44.92#ibcon#wrote, iclass 35, count 0 2006.201.21:53:44.92#ibcon#about to read 3, iclass 35, count 0 2006.201.21:53:44.95#ibcon#read 3, iclass 35, count 0 2006.201.21:53:44.95#ibcon#about to read 4, iclass 35, count 0 2006.201.21:53:44.95#ibcon#read 4, iclass 35, count 0 2006.201.21:53:44.95#ibcon#about to read 5, iclass 35, count 0 2006.201.21:53:44.95#ibcon#read 5, iclass 35, count 0 2006.201.21:53:44.95#ibcon#about to read 6, iclass 35, count 0 2006.201.21:53:44.95#ibcon#read 6, iclass 35, count 0 2006.201.21:53:44.95#ibcon#end of sib2, iclass 35, count 0 2006.201.21:53:44.95#ibcon#*after write, iclass 35, count 0 2006.201.21:53:44.95#ibcon#*before return 0, iclass 35, count 0 2006.201.21:53:44.95#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:44.95#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.21:53:44.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.21:53:44.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.21:53:44.95$vck44/vblo=5,709.99 2006.201.21:53:44.95#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.21:53:44.95#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.21:53:44.95#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:44.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:44.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:44.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:44.95#ibcon#enter wrdev, iclass 37, count 0 2006.201.21:53:44.95#ibcon#first serial, iclass 37, count 0 2006.201.21:53:44.95#ibcon#enter sib2, iclass 37, count 0 2006.201.21:53:44.95#ibcon#flushed, iclass 37, count 0 2006.201.21:53:44.95#ibcon#about to write, iclass 37, count 0 2006.201.21:53:44.95#ibcon#wrote, iclass 37, count 0 2006.201.21:53:44.95#ibcon#about to read 3, iclass 37, count 0 2006.201.21:53:44.97#ibcon#read 3, iclass 37, count 0 2006.201.21:53:44.97#ibcon#about to read 4, iclass 37, count 0 2006.201.21:53:44.97#ibcon#read 4, iclass 37, count 0 2006.201.21:53:44.97#ibcon#about to read 5, iclass 37, count 0 2006.201.21:53:44.97#ibcon#read 5, iclass 37, count 0 2006.201.21:53:44.97#ibcon#about to read 6, iclass 37, count 0 2006.201.21:53:44.97#ibcon#read 6, iclass 37, count 0 2006.201.21:53:44.97#ibcon#end of sib2, iclass 37, count 0 2006.201.21:53:44.97#ibcon#*mode == 0, iclass 37, count 0 2006.201.21:53:44.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.21:53:44.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.21:53:44.97#ibcon#*before write, iclass 37, count 0 2006.201.21:53:44.97#ibcon#enter sib2, iclass 37, count 0 2006.201.21:53:44.97#ibcon#flushed, iclass 37, count 0 2006.201.21:53:44.97#ibcon#about to write, iclass 37, count 0 2006.201.21:53:44.97#ibcon#wrote, iclass 37, count 0 2006.201.21:53:44.97#ibcon#about to read 3, iclass 37, count 0 2006.201.21:53:45.01#ibcon#read 3, iclass 37, count 0 2006.201.21:53:45.01#ibcon#about to read 4, iclass 37, count 0 2006.201.21:53:45.01#ibcon#read 4, iclass 37, count 0 2006.201.21:53:45.01#ibcon#about to read 5, iclass 37, count 0 2006.201.21:53:45.01#ibcon#read 5, iclass 37, count 0 2006.201.21:53:45.01#ibcon#about to read 6, iclass 37, count 0 2006.201.21:53:45.01#ibcon#read 6, iclass 37, count 0 2006.201.21:53:45.01#ibcon#end of sib2, iclass 37, count 0 2006.201.21:53:45.01#ibcon#*after write, iclass 37, count 0 2006.201.21:53:45.01#ibcon#*before return 0, iclass 37, count 0 2006.201.21:53:45.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:45.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.21:53:45.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.21:53:45.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.21:53:45.01$vck44/vb=5,4 2006.201.21:53:45.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.21:53:45.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.21:53:45.01#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:45.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:45.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:45.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:45.07#ibcon#enter wrdev, iclass 39, count 2 2006.201.21:53:45.07#ibcon#first serial, iclass 39, count 2 2006.201.21:53:45.07#ibcon#enter sib2, iclass 39, count 2 2006.201.21:53:45.07#ibcon#flushed, iclass 39, count 2 2006.201.21:53:45.07#ibcon#about to write, iclass 39, count 2 2006.201.21:53:45.07#ibcon#wrote, iclass 39, count 2 2006.201.21:53:45.07#ibcon#about to read 3, iclass 39, count 2 2006.201.21:53:45.09#ibcon#read 3, iclass 39, count 2 2006.201.21:53:45.09#ibcon#about to read 4, iclass 39, count 2 2006.201.21:53:45.09#ibcon#read 4, iclass 39, count 2 2006.201.21:53:45.09#ibcon#about to read 5, iclass 39, count 2 2006.201.21:53:45.09#ibcon#read 5, iclass 39, count 2 2006.201.21:53:45.09#ibcon#about to read 6, iclass 39, count 2 2006.201.21:53:45.09#ibcon#read 6, iclass 39, count 2 2006.201.21:53:45.09#ibcon#end of sib2, iclass 39, count 2 2006.201.21:53:45.09#ibcon#*mode == 0, iclass 39, count 2 2006.201.21:53:45.09#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.21:53:45.09#ibcon#[27=AT05-04\r\n] 2006.201.21:53:45.09#ibcon#*before write, iclass 39, count 2 2006.201.21:53:45.09#ibcon#enter sib2, iclass 39, count 2 2006.201.21:53:45.09#ibcon#flushed, iclass 39, count 2 2006.201.21:53:45.09#ibcon#about to write, iclass 39, count 2 2006.201.21:53:45.09#ibcon#wrote, iclass 39, count 2 2006.201.21:53:45.09#ibcon#about to read 3, iclass 39, count 2 2006.201.21:53:45.12#ibcon#read 3, iclass 39, count 2 2006.201.21:53:45.12#ibcon#about to read 4, iclass 39, count 2 2006.201.21:53:45.12#ibcon#read 4, iclass 39, count 2 2006.201.21:53:45.12#ibcon#about to read 5, iclass 39, count 2 2006.201.21:53:45.12#ibcon#read 5, iclass 39, count 2 2006.201.21:53:45.12#ibcon#about to read 6, iclass 39, count 2 2006.201.21:53:45.12#ibcon#read 6, iclass 39, count 2 2006.201.21:53:45.12#ibcon#end of sib2, iclass 39, count 2 2006.201.21:53:45.12#ibcon#*after write, iclass 39, count 2 2006.201.21:53:45.12#ibcon#*before return 0, iclass 39, count 2 2006.201.21:53:45.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:45.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.21:53:45.12#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.21:53:45.12#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:45.12#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:45.24#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:45.24#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:45.24#ibcon#enter wrdev, iclass 39, count 0 2006.201.21:53:45.24#ibcon#first serial, iclass 39, count 0 2006.201.21:53:45.24#ibcon#enter sib2, iclass 39, count 0 2006.201.21:53:45.24#ibcon#flushed, iclass 39, count 0 2006.201.21:53:45.24#ibcon#about to write, iclass 39, count 0 2006.201.21:53:45.24#ibcon#wrote, iclass 39, count 0 2006.201.21:53:45.24#ibcon#about to read 3, iclass 39, count 0 2006.201.21:53:45.26#ibcon#read 3, iclass 39, count 0 2006.201.21:53:45.26#ibcon#about to read 4, iclass 39, count 0 2006.201.21:53:45.26#ibcon#read 4, iclass 39, count 0 2006.201.21:53:45.26#ibcon#about to read 5, iclass 39, count 0 2006.201.21:53:45.26#ibcon#read 5, iclass 39, count 0 2006.201.21:53:45.26#ibcon#about to read 6, iclass 39, count 0 2006.201.21:53:45.26#ibcon#read 6, iclass 39, count 0 2006.201.21:53:45.26#ibcon#end of sib2, iclass 39, count 0 2006.201.21:53:45.26#ibcon#*mode == 0, iclass 39, count 0 2006.201.21:53:45.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.21:53:45.26#ibcon#[27=USB\r\n] 2006.201.21:53:45.26#ibcon#*before write, iclass 39, count 0 2006.201.21:53:45.26#ibcon#enter sib2, iclass 39, count 0 2006.201.21:53:45.26#ibcon#flushed, iclass 39, count 0 2006.201.21:53:45.26#ibcon#about to write, iclass 39, count 0 2006.201.21:53:45.26#ibcon#wrote, iclass 39, count 0 2006.201.21:53:45.26#ibcon#about to read 3, iclass 39, count 0 2006.201.21:53:45.29#ibcon#read 3, iclass 39, count 0 2006.201.21:53:45.29#ibcon#about to read 4, iclass 39, count 0 2006.201.21:53:45.29#ibcon#read 4, iclass 39, count 0 2006.201.21:53:45.29#ibcon#about to read 5, iclass 39, count 0 2006.201.21:53:45.29#ibcon#read 5, iclass 39, count 0 2006.201.21:53:45.29#ibcon#about to read 6, iclass 39, count 0 2006.201.21:53:45.29#ibcon#read 6, iclass 39, count 0 2006.201.21:53:45.29#ibcon#end of sib2, iclass 39, count 0 2006.201.21:53:45.29#ibcon#*after write, iclass 39, count 0 2006.201.21:53:45.29#ibcon#*before return 0, iclass 39, count 0 2006.201.21:53:45.29#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:45.29#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.21:53:45.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.21:53:45.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.21:53:45.29$vck44/vblo=6,719.99 2006.201.21:53:45.29#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.21:53:45.29#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.21:53:45.29#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:45.29#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:45.29#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:45.29#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:45.29#ibcon#enter wrdev, iclass 2, count 0 2006.201.21:53:45.29#ibcon#first serial, iclass 2, count 0 2006.201.21:53:45.29#ibcon#enter sib2, iclass 2, count 0 2006.201.21:53:45.29#ibcon#flushed, iclass 2, count 0 2006.201.21:53:45.29#ibcon#about to write, iclass 2, count 0 2006.201.21:53:45.29#ibcon#wrote, iclass 2, count 0 2006.201.21:53:45.29#ibcon#about to read 3, iclass 2, count 0 2006.201.21:53:45.31#ibcon#read 3, iclass 2, count 0 2006.201.21:53:45.31#ibcon#about to read 4, iclass 2, count 0 2006.201.21:53:45.31#ibcon#read 4, iclass 2, count 0 2006.201.21:53:45.31#ibcon#about to read 5, iclass 2, count 0 2006.201.21:53:45.31#ibcon#read 5, iclass 2, count 0 2006.201.21:53:45.31#ibcon#about to read 6, iclass 2, count 0 2006.201.21:53:45.31#ibcon#read 6, iclass 2, count 0 2006.201.21:53:45.31#ibcon#end of sib2, iclass 2, count 0 2006.201.21:53:45.31#ibcon#*mode == 0, iclass 2, count 0 2006.201.21:53:45.31#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.21:53:45.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.21:53:45.31#ibcon#*before write, iclass 2, count 0 2006.201.21:53:45.31#ibcon#enter sib2, iclass 2, count 0 2006.201.21:53:45.31#ibcon#flushed, iclass 2, count 0 2006.201.21:53:45.31#ibcon#about to write, iclass 2, count 0 2006.201.21:53:45.31#ibcon#wrote, iclass 2, count 0 2006.201.21:53:45.31#ibcon#about to read 3, iclass 2, count 0 2006.201.21:53:45.35#ibcon#read 3, iclass 2, count 0 2006.201.21:53:45.35#ibcon#about to read 4, iclass 2, count 0 2006.201.21:53:45.35#ibcon#read 4, iclass 2, count 0 2006.201.21:53:45.35#ibcon#about to read 5, iclass 2, count 0 2006.201.21:53:45.35#ibcon#read 5, iclass 2, count 0 2006.201.21:53:45.35#ibcon#about to read 6, iclass 2, count 0 2006.201.21:53:45.35#ibcon#read 6, iclass 2, count 0 2006.201.21:53:45.35#ibcon#end of sib2, iclass 2, count 0 2006.201.21:53:45.35#ibcon#*after write, iclass 2, count 0 2006.201.21:53:45.35#ibcon#*before return 0, iclass 2, count 0 2006.201.21:53:45.35#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:45.35#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.21:53:45.35#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.21:53:45.35#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.21:53:45.35$vck44/vb=6,4 2006.201.21:53:45.35#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.21:53:45.35#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.21:53:45.35#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:45.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:45.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:45.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:45.41#ibcon#enter wrdev, iclass 5, count 2 2006.201.21:53:45.41#ibcon#first serial, iclass 5, count 2 2006.201.21:53:45.41#ibcon#enter sib2, iclass 5, count 2 2006.201.21:53:45.41#ibcon#flushed, iclass 5, count 2 2006.201.21:53:45.41#ibcon#about to write, iclass 5, count 2 2006.201.21:53:45.41#ibcon#wrote, iclass 5, count 2 2006.201.21:53:45.41#ibcon#about to read 3, iclass 5, count 2 2006.201.21:53:45.43#ibcon#read 3, iclass 5, count 2 2006.201.21:53:45.43#ibcon#about to read 4, iclass 5, count 2 2006.201.21:53:45.43#ibcon#read 4, iclass 5, count 2 2006.201.21:53:45.43#ibcon#about to read 5, iclass 5, count 2 2006.201.21:53:45.43#ibcon#read 5, iclass 5, count 2 2006.201.21:53:45.43#ibcon#about to read 6, iclass 5, count 2 2006.201.21:53:45.43#ibcon#read 6, iclass 5, count 2 2006.201.21:53:45.43#ibcon#end of sib2, iclass 5, count 2 2006.201.21:53:45.43#ibcon#*mode == 0, iclass 5, count 2 2006.201.21:53:45.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.21:53:45.43#ibcon#[27=AT06-04\r\n] 2006.201.21:53:45.43#ibcon#*before write, iclass 5, count 2 2006.201.21:53:45.43#ibcon#enter sib2, iclass 5, count 2 2006.201.21:53:45.43#ibcon#flushed, iclass 5, count 2 2006.201.21:53:45.43#ibcon#about to write, iclass 5, count 2 2006.201.21:53:45.43#ibcon#wrote, iclass 5, count 2 2006.201.21:53:45.43#ibcon#about to read 3, iclass 5, count 2 2006.201.21:53:45.46#ibcon#read 3, iclass 5, count 2 2006.201.21:53:45.46#ibcon#about to read 4, iclass 5, count 2 2006.201.21:53:45.46#ibcon#read 4, iclass 5, count 2 2006.201.21:53:45.46#ibcon#about to read 5, iclass 5, count 2 2006.201.21:53:45.46#ibcon#read 5, iclass 5, count 2 2006.201.21:53:45.46#ibcon#about to read 6, iclass 5, count 2 2006.201.21:53:45.46#ibcon#read 6, iclass 5, count 2 2006.201.21:53:45.46#ibcon#end of sib2, iclass 5, count 2 2006.201.21:53:45.46#ibcon#*after write, iclass 5, count 2 2006.201.21:53:45.46#ibcon#*before return 0, iclass 5, count 2 2006.201.21:53:45.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:45.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.21:53:45.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.21:53:45.46#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:45.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:45.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:45.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:45.58#ibcon#enter wrdev, iclass 5, count 0 2006.201.21:53:45.58#ibcon#first serial, iclass 5, count 0 2006.201.21:53:45.58#ibcon#enter sib2, iclass 5, count 0 2006.201.21:53:45.58#ibcon#flushed, iclass 5, count 0 2006.201.21:53:45.58#ibcon#about to write, iclass 5, count 0 2006.201.21:53:45.58#ibcon#wrote, iclass 5, count 0 2006.201.21:53:45.58#ibcon#about to read 3, iclass 5, count 0 2006.201.21:53:45.60#ibcon#read 3, iclass 5, count 0 2006.201.21:53:45.60#ibcon#about to read 4, iclass 5, count 0 2006.201.21:53:45.60#ibcon#read 4, iclass 5, count 0 2006.201.21:53:45.60#ibcon#about to read 5, iclass 5, count 0 2006.201.21:53:45.60#ibcon#read 5, iclass 5, count 0 2006.201.21:53:45.60#ibcon#about to read 6, iclass 5, count 0 2006.201.21:53:45.60#ibcon#read 6, iclass 5, count 0 2006.201.21:53:45.60#ibcon#end of sib2, iclass 5, count 0 2006.201.21:53:45.60#ibcon#*mode == 0, iclass 5, count 0 2006.201.21:53:45.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.21:53:45.60#ibcon#[27=USB\r\n] 2006.201.21:53:45.60#ibcon#*before write, iclass 5, count 0 2006.201.21:53:45.60#ibcon#enter sib2, iclass 5, count 0 2006.201.21:53:45.60#ibcon#flushed, iclass 5, count 0 2006.201.21:53:45.60#ibcon#about to write, iclass 5, count 0 2006.201.21:53:45.60#ibcon#wrote, iclass 5, count 0 2006.201.21:53:45.60#ibcon#about to read 3, iclass 5, count 0 2006.201.21:53:45.63#ibcon#read 3, iclass 5, count 0 2006.201.21:53:45.63#ibcon#about to read 4, iclass 5, count 0 2006.201.21:53:45.63#ibcon#read 4, iclass 5, count 0 2006.201.21:53:45.63#ibcon#about to read 5, iclass 5, count 0 2006.201.21:53:45.63#ibcon#read 5, iclass 5, count 0 2006.201.21:53:45.63#ibcon#about to read 6, iclass 5, count 0 2006.201.21:53:45.63#ibcon#read 6, iclass 5, count 0 2006.201.21:53:45.63#ibcon#end of sib2, iclass 5, count 0 2006.201.21:53:45.63#ibcon#*after write, iclass 5, count 0 2006.201.21:53:45.63#ibcon#*before return 0, iclass 5, count 0 2006.201.21:53:45.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:45.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.21:53:45.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.21:53:45.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.21:53:45.63$vck44/vblo=7,734.99 2006.201.21:53:45.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.21:53:45.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.21:53:45.63#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:45.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:45.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:45.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:45.63#ibcon#enter wrdev, iclass 7, count 0 2006.201.21:53:45.63#ibcon#first serial, iclass 7, count 0 2006.201.21:53:45.63#ibcon#enter sib2, iclass 7, count 0 2006.201.21:53:45.63#ibcon#flushed, iclass 7, count 0 2006.201.21:53:45.63#ibcon#about to write, iclass 7, count 0 2006.201.21:53:45.63#ibcon#wrote, iclass 7, count 0 2006.201.21:53:45.63#ibcon#about to read 3, iclass 7, count 0 2006.201.21:53:45.65#ibcon#read 3, iclass 7, count 0 2006.201.21:53:45.65#ibcon#about to read 4, iclass 7, count 0 2006.201.21:53:45.65#ibcon#read 4, iclass 7, count 0 2006.201.21:53:45.65#ibcon#about to read 5, iclass 7, count 0 2006.201.21:53:45.65#ibcon#read 5, iclass 7, count 0 2006.201.21:53:45.65#ibcon#about to read 6, iclass 7, count 0 2006.201.21:53:45.65#ibcon#read 6, iclass 7, count 0 2006.201.21:53:45.65#ibcon#end of sib2, iclass 7, count 0 2006.201.21:53:45.65#ibcon#*mode == 0, iclass 7, count 0 2006.201.21:53:45.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.21:53:45.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.21:53:45.65#ibcon#*before write, iclass 7, count 0 2006.201.21:53:45.65#ibcon#enter sib2, iclass 7, count 0 2006.201.21:53:45.65#ibcon#flushed, iclass 7, count 0 2006.201.21:53:45.65#ibcon#about to write, iclass 7, count 0 2006.201.21:53:45.65#ibcon#wrote, iclass 7, count 0 2006.201.21:53:45.65#ibcon#about to read 3, iclass 7, count 0 2006.201.21:53:45.69#ibcon#read 3, iclass 7, count 0 2006.201.21:53:45.69#ibcon#about to read 4, iclass 7, count 0 2006.201.21:53:45.69#ibcon#read 4, iclass 7, count 0 2006.201.21:53:45.69#ibcon#about to read 5, iclass 7, count 0 2006.201.21:53:45.69#ibcon#read 5, iclass 7, count 0 2006.201.21:53:45.69#ibcon#about to read 6, iclass 7, count 0 2006.201.21:53:45.69#ibcon#read 6, iclass 7, count 0 2006.201.21:53:45.69#ibcon#end of sib2, iclass 7, count 0 2006.201.21:53:45.69#ibcon#*after write, iclass 7, count 0 2006.201.21:53:45.69#ibcon#*before return 0, iclass 7, count 0 2006.201.21:53:45.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:45.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.21:53:45.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.21:53:45.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.21:53:45.69$vck44/vb=7,4 2006.201.21:53:45.69#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.21:53:45.69#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.21:53:45.69#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:45.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:45.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:45.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:45.75#ibcon#enter wrdev, iclass 11, count 2 2006.201.21:53:45.75#ibcon#first serial, iclass 11, count 2 2006.201.21:53:45.75#ibcon#enter sib2, iclass 11, count 2 2006.201.21:53:45.75#ibcon#flushed, iclass 11, count 2 2006.201.21:53:45.75#ibcon#about to write, iclass 11, count 2 2006.201.21:53:45.75#ibcon#wrote, iclass 11, count 2 2006.201.21:53:45.75#ibcon#about to read 3, iclass 11, count 2 2006.201.21:53:45.77#ibcon#read 3, iclass 11, count 2 2006.201.21:53:45.77#ibcon#about to read 4, iclass 11, count 2 2006.201.21:53:45.77#ibcon#read 4, iclass 11, count 2 2006.201.21:53:45.77#ibcon#about to read 5, iclass 11, count 2 2006.201.21:53:45.77#ibcon#read 5, iclass 11, count 2 2006.201.21:53:45.77#ibcon#about to read 6, iclass 11, count 2 2006.201.21:53:45.77#ibcon#read 6, iclass 11, count 2 2006.201.21:53:45.77#ibcon#end of sib2, iclass 11, count 2 2006.201.21:53:45.77#ibcon#*mode == 0, iclass 11, count 2 2006.201.21:53:45.77#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.21:53:45.77#ibcon#[27=AT07-04\r\n] 2006.201.21:53:45.77#ibcon#*before write, iclass 11, count 2 2006.201.21:53:45.77#ibcon#enter sib2, iclass 11, count 2 2006.201.21:53:45.77#ibcon#flushed, iclass 11, count 2 2006.201.21:53:45.77#ibcon#about to write, iclass 11, count 2 2006.201.21:53:45.77#ibcon#wrote, iclass 11, count 2 2006.201.21:53:45.77#ibcon#about to read 3, iclass 11, count 2 2006.201.21:53:45.80#ibcon#read 3, iclass 11, count 2 2006.201.21:53:45.80#ibcon#about to read 4, iclass 11, count 2 2006.201.21:53:45.80#ibcon#read 4, iclass 11, count 2 2006.201.21:53:45.80#ibcon#about to read 5, iclass 11, count 2 2006.201.21:53:45.80#ibcon#read 5, iclass 11, count 2 2006.201.21:53:45.80#ibcon#about to read 6, iclass 11, count 2 2006.201.21:53:45.80#ibcon#read 6, iclass 11, count 2 2006.201.21:53:45.80#ibcon#end of sib2, iclass 11, count 2 2006.201.21:53:45.80#ibcon#*after write, iclass 11, count 2 2006.201.21:53:45.80#ibcon#*before return 0, iclass 11, count 2 2006.201.21:53:45.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:45.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.21:53:45.80#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.21:53:45.80#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:45.80#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:45.92#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:45.92#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:45.92#ibcon#enter wrdev, iclass 11, count 0 2006.201.21:53:45.92#ibcon#first serial, iclass 11, count 0 2006.201.21:53:45.92#ibcon#enter sib2, iclass 11, count 0 2006.201.21:53:45.92#ibcon#flushed, iclass 11, count 0 2006.201.21:53:45.92#ibcon#about to write, iclass 11, count 0 2006.201.21:53:45.92#ibcon#wrote, iclass 11, count 0 2006.201.21:53:45.92#ibcon#about to read 3, iclass 11, count 0 2006.201.21:53:45.94#ibcon#read 3, iclass 11, count 0 2006.201.21:53:45.94#ibcon#about to read 4, iclass 11, count 0 2006.201.21:53:45.94#ibcon#read 4, iclass 11, count 0 2006.201.21:53:45.94#ibcon#about to read 5, iclass 11, count 0 2006.201.21:53:45.94#ibcon#read 5, iclass 11, count 0 2006.201.21:53:45.94#ibcon#about to read 6, iclass 11, count 0 2006.201.21:53:45.94#ibcon#read 6, iclass 11, count 0 2006.201.21:53:45.94#ibcon#end of sib2, iclass 11, count 0 2006.201.21:53:45.94#ibcon#*mode == 0, iclass 11, count 0 2006.201.21:53:45.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.21:53:45.94#ibcon#[27=USB\r\n] 2006.201.21:53:45.94#ibcon#*before write, iclass 11, count 0 2006.201.21:53:45.94#ibcon#enter sib2, iclass 11, count 0 2006.201.21:53:45.94#ibcon#flushed, iclass 11, count 0 2006.201.21:53:45.94#ibcon#about to write, iclass 11, count 0 2006.201.21:53:45.94#ibcon#wrote, iclass 11, count 0 2006.201.21:53:45.94#ibcon#about to read 3, iclass 11, count 0 2006.201.21:53:45.97#ibcon#read 3, iclass 11, count 0 2006.201.21:53:45.97#ibcon#about to read 4, iclass 11, count 0 2006.201.21:53:45.97#ibcon#read 4, iclass 11, count 0 2006.201.21:53:45.97#ibcon#about to read 5, iclass 11, count 0 2006.201.21:53:45.97#ibcon#read 5, iclass 11, count 0 2006.201.21:53:45.97#ibcon#about to read 6, iclass 11, count 0 2006.201.21:53:45.97#ibcon#read 6, iclass 11, count 0 2006.201.21:53:45.97#ibcon#end of sib2, iclass 11, count 0 2006.201.21:53:45.97#ibcon#*after write, iclass 11, count 0 2006.201.21:53:45.97#ibcon#*before return 0, iclass 11, count 0 2006.201.21:53:45.97#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:45.97#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.21:53:45.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.21:53:45.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.21:53:45.97$vck44/vblo=8,744.99 2006.201.21:53:45.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.21:53:45.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.21:53:45.97#ibcon#ireg 17 cls_cnt 0 2006.201.21:53:45.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:45.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:45.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:45.97#ibcon#enter wrdev, iclass 13, count 0 2006.201.21:53:45.97#ibcon#first serial, iclass 13, count 0 2006.201.21:53:45.97#ibcon#enter sib2, iclass 13, count 0 2006.201.21:53:45.97#ibcon#flushed, iclass 13, count 0 2006.201.21:53:45.97#ibcon#about to write, iclass 13, count 0 2006.201.21:53:45.97#ibcon#wrote, iclass 13, count 0 2006.201.21:53:45.97#ibcon#about to read 3, iclass 13, count 0 2006.201.21:53:45.99#ibcon#read 3, iclass 13, count 0 2006.201.21:53:45.99#ibcon#about to read 4, iclass 13, count 0 2006.201.21:53:45.99#ibcon#read 4, iclass 13, count 0 2006.201.21:53:45.99#ibcon#about to read 5, iclass 13, count 0 2006.201.21:53:45.99#ibcon#read 5, iclass 13, count 0 2006.201.21:53:45.99#ibcon#about to read 6, iclass 13, count 0 2006.201.21:53:45.99#ibcon#read 6, iclass 13, count 0 2006.201.21:53:45.99#ibcon#end of sib2, iclass 13, count 0 2006.201.21:53:45.99#ibcon#*mode == 0, iclass 13, count 0 2006.201.21:53:45.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.21:53:45.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.21:53:45.99#ibcon#*before write, iclass 13, count 0 2006.201.21:53:45.99#ibcon#enter sib2, iclass 13, count 0 2006.201.21:53:45.99#ibcon#flushed, iclass 13, count 0 2006.201.21:53:45.99#ibcon#about to write, iclass 13, count 0 2006.201.21:53:45.99#ibcon#wrote, iclass 13, count 0 2006.201.21:53:45.99#ibcon#about to read 3, iclass 13, count 0 2006.201.21:53:46.03#ibcon#read 3, iclass 13, count 0 2006.201.21:53:46.03#ibcon#about to read 4, iclass 13, count 0 2006.201.21:53:46.03#ibcon#read 4, iclass 13, count 0 2006.201.21:53:46.03#ibcon#about to read 5, iclass 13, count 0 2006.201.21:53:46.03#ibcon#read 5, iclass 13, count 0 2006.201.21:53:46.03#ibcon#about to read 6, iclass 13, count 0 2006.201.21:53:46.03#ibcon#read 6, iclass 13, count 0 2006.201.21:53:46.03#ibcon#end of sib2, iclass 13, count 0 2006.201.21:53:46.03#ibcon#*after write, iclass 13, count 0 2006.201.21:53:46.03#ibcon#*before return 0, iclass 13, count 0 2006.201.21:53:46.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:46.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.21:53:46.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.21:53:46.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.21:53:46.03$vck44/vb=8,4 2006.201.21:53:46.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.21:53:46.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.21:53:46.03#ibcon#ireg 11 cls_cnt 2 2006.201.21:53:46.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:46.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:46.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:46.09#ibcon#enter wrdev, iclass 15, count 2 2006.201.21:53:46.09#ibcon#first serial, iclass 15, count 2 2006.201.21:53:46.09#ibcon#enter sib2, iclass 15, count 2 2006.201.21:53:46.09#ibcon#flushed, iclass 15, count 2 2006.201.21:53:46.09#ibcon#about to write, iclass 15, count 2 2006.201.21:53:46.09#ibcon#wrote, iclass 15, count 2 2006.201.21:53:46.09#ibcon#about to read 3, iclass 15, count 2 2006.201.21:53:46.11#ibcon#read 3, iclass 15, count 2 2006.201.21:53:46.11#ibcon#about to read 4, iclass 15, count 2 2006.201.21:53:46.11#ibcon#read 4, iclass 15, count 2 2006.201.21:53:46.11#ibcon#about to read 5, iclass 15, count 2 2006.201.21:53:46.11#ibcon#read 5, iclass 15, count 2 2006.201.21:53:46.11#ibcon#about to read 6, iclass 15, count 2 2006.201.21:53:46.11#ibcon#read 6, iclass 15, count 2 2006.201.21:53:46.11#ibcon#end of sib2, iclass 15, count 2 2006.201.21:53:46.11#ibcon#*mode == 0, iclass 15, count 2 2006.201.21:53:46.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.21:53:46.11#ibcon#[27=AT08-04\r\n] 2006.201.21:53:46.11#ibcon#*before write, iclass 15, count 2 2006.201.21:53:46.11#ibcon#enter sib2, iclass 15, count 2 2006.201.21:53:46.11#ibcon#flushed, iclass 15, count 2 2006.201.21:53:46.11#ibcon#about to write, iclass 15, count 2 2006.201.21:53:46.11#ibcon#wrote, iclass 15, count 2 2006.201.21:53:46.11#ibcon#about to read 3, iclass 15, count 2 2006.201.21:53:46.14#ibcon#read 3, iclass 15, count 2 2006.201.21:53:46.14#ibcon#about to read 4, iclass 15, count 2 2006.201.21:53:46.14#ibcon#read 4, iclass 15, count 2 2006.201.21:53:46.14#ibcon#about to read 5, iclass 15, count 2 2006.201.21:53:46.14#ibcon#read 5, iclass 15, count 2 2006.201.21:53:46.14#ibcon#about to read 6, iclass 15, count 2 2006.201.21:53:46.14#ibcon#read 6, iclass 15, count 2 2006.201.21:53:46.14#ibcon#end of sib2, iclass 15, count 2 2006.201.21:53:46.14#ibcon#*after write, iclass 15, count 2 2006.201.21:53:46.14#ibcon#*before return 0, iclass 15, count 2 2006.201.21:53:46.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:46.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.21:53:46.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.21:53:46.14#ibcon#ireg 7 cls_cnt 0 2006.201.21:53:46.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:46.26#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:46.26#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:46.26#ibcon#enter wrdev, iclass 15, count 0 2006.201.21:53:46.26#ibcon#first serial, iclass 15, count 0 2006.201.21:53:46.26#ibcon#enter sib2, iclass 15, count 0 2006.201.21:53:46.26#ibcon#flushed, iclass 15, count 0 2006.201.21:53:46.26#ibcon#about to write, iclass 15, count 0 2006.201.21:53:46.26#ibcon#wrote, iclass 15, count 0 2006.201.21:53:46.26#ibcon#about to read 3, iclass 15, count 0 2006.201.21:53:46.28#ibcon#read 3, iclass 15, count 0 2006.201.21:53:46.28#ibcon#about to read 4, iclass 15, count 0 2006.201.21:53:46.28#ibcon#read 4, iclass 15, count 0 2006.201.21:53:46.28#ibcon#about to read 5, iclass 15, count 0 2006.201.21:53:46.28#ibcon#read 5, iclass 15, count 0 2006.201.21:53:46.28#ibcon#about to read 6, iclass 15, count 0 2006.201.21:53:46.28#ibcon#read 6, iclass 15, count 0 2006.201.21:53:46.28#ibcon#end of sib2, iclass 15, count 0 2006.201.21:53:46.28#ibcon#*mode == 0, iclass 15, count 0 2006.201.21:53:46.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.21:53:46.28#ibcon#[27=USB\r\n] 2006.201.21:53:46.28#ibcon#*before write, iclass 15, count 0 2006.201.21:53:46.28#ibcon#enter sib2, iclass 15, count 0 2006.201.21:53:46.28#ibcon#flushed, iclass 15, count 0 2006.201.21:53:46.28#ibcon#about to write, iclass 15, count 0 2006.201.21:53:46.28#ibcon#wrote, iclass 15, count 0 2006.201.21:53:46.28#ibcon#about to read 3, iclass 15, count 0 2006.201.21:53:46.31#ibcon#read 3, iclass 15, count 0 2006.201.21:53:46.31#ibcon#about to read 4, iclass 15, count 0 2006.201.21:53:46.31#ibcon#read 4, iclass 15, count 0 2006.201.21:53:46.31#ibcon#about to read 5, iclass 15, count 0 2006.201.21:53:46.31#ibcon#read 5, iclass 15, count 0 2006.201.21:53:46.31#ibcon#about to read 6, iclass 15, count 0 2006.201.21:53:46.31#ibcon#read 6, iclass 15, count 0 2006.201.21:53:46.31#ibcon#end of sib2, iclass 15, count 0 2006.201.21:53:46.31#ibcon#*after write, iclass 15, count 0 2006.201.21:53:46.31#ibcon#*before return 0, iclass 15, count 0 2006.201.21:53:46.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:46.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.21:53:46.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.21:53:46.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.21:53:46.31$vck44/vabw=wide 2006.201.21:53:46.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.21:53:46.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.21:53:46.31#ibcon#ireg 8 cls_cnt 0 2006.201.21:53:46.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:46.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:46.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:46.31#ibcon#enter wrdev, iclass 17, count 0 2006.201.21:53:46.31#ibcon#first serial, iclass 17, count 0 2006.201.21:53:46.31#ibcon#enter sib2, iclass 17, count 0 2006.201.21:53:46.31#ibcon#flushed, iclass 17, count 0 2006.201.21:53:46.31#ibcon#about to write, iclass 17, count 0 2006.201.21:53:46.31#ibcon#wrote, iclass 17, count 0 2006.201.21:53:46.31#ibcon#about to read 3, iclass 17, count 0 2006.201.21:53:46.33#ibcon#read 3, iclass 17, count 0 2006.201.21:53:46.33#ibcon#about to read 4, iclass 17, count 0 2006.201.21:53:46.33#ibcon#read 4, iclass 17, count 0 2006.201.21:53:46.33#ibcon#about to read 5, iclass 17, count 0 2006.201.21:53:46.33#ibcon#read 5, iclass 17, count 0 2006.201.21:53:46.33#ibcon#about to read 6, iclass 17, count 0 2006.201.21:53:46.33#ibcon#read 6, iclass 17, count 0 2006.201.21:53:46.33#ibcon#end of sib2, iclass 17, count 0 2006.201.21:53:46.33#ibcon#*mode == 0, iclass 17, count 0 2006.201.21:53:46.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.21:53:46.33#ibcon#[25=BW32\r\n] 2006.201.21:53:46.33#ibcon#*before write, iclass 17, count 0 2006.201.21:53:46.33#ibcon#enter sib2, iclass 17, count 0 2006.201.21:53:46.33#ibcon#flushed, iclass 17, count 0 2006.201.21:53:46.33#ibcon#about to write, iclass 17, count 0 2006.201.21:53:46.33#ibcon#wrote, iclass 17, count 0 2006.201.21:53:46.33#ibcon#about to read 3, iclass 17, count 0 2006.201.21:53:46.37#ibcon#read 3, iclass 17, count 0 2006.201.21:53:46.37#ibcon#about to read 4, iclass 17, count 0 2006.201.21:53:46.37#ibcon#read 4, iclass 17, count 0 2006.201.21:53:46.37#ibcon#about to read 5, iclass 17, count 0 2006.201.21:53:46.37#ibcon#read 5, iclass 17, count 0 2006.201.21:53:46.37#ibcon#about to read 6, iclass 17, count 0 2006.201.21:53:46.37#ibcon#read 6, iclass 17, count 0 2006.201.21:53:46.37#ibcon#end of sib2, iclass 17, count 0 2006.201.21:53:46.37#ibcon#*after write, iclass 17, count 0 2006.201.21:53:46.37#ibcon#*before return 0, iclass 17, count 0 2006.201.21:53:46.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:46.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.21:53:46.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.21:53:46.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.21:53:46.37$vck44/vbbw=wide 2006.201.21:53:46.37#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.21:53:46.37#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.21:53:46.37#ibcon#ireg 8 cls_cnt 0 2006.201.21:53:46.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:53:46.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:53:46.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:53:46.43#ibcon#enter wrdev, iclass 19, count 0 2006.201.21:53:46.43#ibcon#first serial, iclass 19, count 0 2006.201.21:53:46.43#ibcon#enter sib2, iclass 19, count 0 2006.201.21:53:46.43#ibcon#flushed, iclass 19, count 0 2006.201.21:53:46.43#ibcon#about to write, iclass 19, count 0 2006.201.21:53:46.43#ibcon#wrote, iclass 19, count 0 2006.201.21:53:46.43#ibcon#about to read 3, iclass 19, count 0 2006.201.21:53:46.45#ibcon#read 3, iclass 19, count 0 2006.201.21:53:46.45#ibcon#about to read 4, iclass 19, count 0 2006.201.21:53:46.45#ibcon#read 4, iclass 19, count 0 2006.201.21:53:46.45#ibcon#about to read 5, iclass 19, count 0 2006.201.21:53:46.45#ibcon#read 5, iclass 19, count 0 2006.201.21:53:46.45#ibcon#about to read 6, iclass 19, count 0 2006.201.21:53:46.45#ibcon#read 6, iclass 19, count 0 2006.201.21:53:46.45#ibcon#end of sib2, iclass 19, count 0 2006.201.21:53:46.45#ibcon#*mode == 0, iclass 19, count 0 2006.201.21:53:46.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.21:53:46.45#ibcon#[27=BW32\r\n] 2006.201.21:53:46.45#ibcon#*before write, iclass 19, count 0 2006.201.21:53:46.45#ibcon#enter sib2, iclass 19, count 0 2006.201.21:53:46.45#ibcon#flushed, iclass 19, count 0 2006.201.21:53:46.45#ibcon#about to write, iclass 19, count 0 2006.201.21:53:46.45#ibcon#wrote, iclass 19, count 0 2006.201.21:53:46.45#ibcon#about to read 3, iclass 19, count 0 2006.201.21:53:46.48#ibcon#read 3, iclass 19, count 0 2006.201.21:53:46.48#ibcon#about to read 4, iclass 19, count 0 2006.201.21:53:46.48#ibcon#read 4, iclass 19, count 0 2006.201.21:53:46.48#ibcon#about to read 5, iclass 19, count 0 2006.201.21:53:46.48#ibcon#read 5, iclass 19, count 0 2006.201.21:53:46.48#ibcon#about to read 6, iclass 19, count 0 2006.201.21:53:46.48#ibcon#read 6, iclass 19, count 0 2006.201.21:53:46.48#ibcon#end of sib2, iclass 19, count 0 2006.201.21:53:46.48#ibcon#*after write, iclass 19, count 0 2006.201.21:53:46.48#ibcon#*before return 0, iclass 19, count 0 2006.201.21:53:46.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:53:46.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.21:53:46.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.21:53:46.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.21:53:46.48$setupk4/ifdk4 2006.201.21:53:46.48$ifdk4/lo= 2006.201.21:53:46.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.21:53:46.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.21:53:46.48$ifdk4/patch= 2006.201.21:53:46.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.21:53:46.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.21:53:46.48$setupk4/!*+20s 2006.201.21:53:50.51#abcon#<5=/05 1.6 3.0 19.961001001.7\r\n> 2006.201.21:53:50.53#abcon#{5=INTERFACE CLEAR} 2006.201.21:53:50.59#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:54:00.68#abcon#<5=/05 1.6 3.0 19.961001001.7\r\n> 2006.201.21:54:00.70#abcon#{5=INTERFACE CLEAR} 2006.201.21:54:00.76#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:54:00.93$setupk4/"tpicd 2006.201.21:54:00.93$setupk4/echo=off 2006.201.21:54:00.93$setupk4/xlog=off 2006.201.21:54:00.93:!2006.201.21:56:57 2006.201.21:54:18.14#trakl#Source acquired 2006.201.21:54:19.14#flagr#flagr/antenna,acquired 2006.201.21:56:57.00:preob 2006.201.21:56:57.14/onsource/TRACKING 2006.201.21:56:57.14:!2006.201.21:57:07 2006.201.21:57:07.00:"tape 2006.201.21:57:07.00:"st=record 2006.201.21:57:07.00:data_valid=on 2006.201.21:57:07.00:midob 2006.201.21:57:07.14/onsource/TRACKING 2006.201.21:57:07.14/wx/19.94,1001.7,100 2006.201.21:57:07.21/cable/+6.4820E-03 2006.201.21:57:08.30/va/01,08,usb,yes,55,58 2006.201.21:57:08.30/va/02,07,usb,yes,59,60 2006.201.21:57:08.30/va/03,08,usb,yes,54,56 2006.201.21:57:08.30/va/04,07,usb,yes,61,64 2006.201.21:57:08.30/va/05,04,usb,yes,54,56 2006.201.21:57:08.30/va/06,05,usb,yes,55,55 2006.201.21:57:08.30/va/07,05,usb,yes,54,55 2006.201.21:57:08.30/va/08,04,usb,yes,53,62 2006.201.21:57:08.53/valo/01,524.99,yes,locked 2006.201.21:57:08.53/valo/02,534.99,yes,locked 2006.201.21:57:08.53/valo/03,564.99,yes,locked 2006.201.21:57:08.53/valo/04,624.99,yes,locked 2006.201.21:57:08.53/valo/05,734.99,yes,locked 2006.201.21:57:08.53/valo/06,814.99,yes,locked 2006.201.21:57:08.53/valo/07,864.99,yes,locked 2006.201.21:57:08.53/valo/08,884.99,yes,locked 2006.201.21:57:09.62/vb/01,04,usb,yes,32,29 2006.201.21:57:09.62/vb/02,05,usb,yes,30,30 2006.201.21:57:09.62/vb/03,04,usb,yes,31,34 2006.201.21:57:09.62/vb/04,05,usb,yes,31,30 2006.201.21:57:09.62/vb/05,04,usb,yes,28,30 2006.201.21:57:09.62/vb/06,04,usb,yes,33,29 2006.201.21:57:09.62/vb/07,04,usb,yes,32,32 2006.201.21:57:09.62/vb/08,04,usb,yes,30,33 2006.201.21:57:09.85/vblo/01,629.99,yes,locked 2006.201.21:57:09.85/vblo/02,634.99,yes,locked 2006.201.21:57:09.85/vblo/03,649.99,yes,locked 2006.201.21:57:09.85/vblo/04,679.99,yes,locked 2006.201.21:57:09.85/vblo/05,709.99,yes,locked 2006.201.21:57:09.85/vblo/06,719.99,yes,locked 2006.201.21:57:09.85/vblo/07,734.99,yes,locked 2006.201.21:57:09.85/vblo/08,744.99,yes,locked 2006.201.21:57:10.00/vabw/8 2006.201.21:57:10.15/vbbw/8 2006.201.21:57:10.36/xfe/off,on,15.5 2006.201.21:57:10.74/ifatt/23,28,28,28 2006.201.21:57:11.07/fmout-gps/S +4.55E-07 2006.201.21:57:11.14:!2006.201.21:57:57 2006.201.21:57:57.00:data_valid=off 2006.201.21:57:57.00:"et 2006.201.21:57:57.00:!+3s 2006.201.21:58:00.02:"tape 2006.201.21:58:00.02:postob 2006.201.21:58:00.14/cable/+6.4805E-03 2006.201.21:58:00.14/wx/19.93,1001.6,100 2006.201.21:58:00.22/fmout-gps/S +4.54E-07 2006.201.21:58:00.22:scan_name=201-2200,jd0607,90 2006.201.21:58:00.22:source=0528+134,053056.42,133155.1,2000.0,cw 2006.201.21:58:01.14#flagr#flagr/antenna,new-source 2006.201.21:58:01.14:checkk5 2006.201.21:58:01.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.21:58:01.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.21:58:02.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.21:58:02.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.21:58:03.01/chk_obsdata//k5ts1/T2012157??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.21:58:03.37/chk_obsdata//k5ts2/T2012157??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.21:58:03.74/chk_obsdata//k5ts3/T2012157??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.21:58:04.10/chk_obsdata//k5ts4/T2012157??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.21:58:04.79/k5log//k5ts1_log_newline 2006.201.21:58:05.48/k5log//k5ts2_log_newline 2006.201.21:58:06.17/k5log//k5ts3_log_newline 2006.201.21:58:06.85/k5log//k5ts4_log_newline 2006.201.21:58:06.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.21:58:06.87:setupk4=1 2006.201.21:58:06.87$setupk4/echo=on 2006.201.21:58:06.87$setupk4/pcalon 2006.201.21:58:06.87$pcalon/"no phase cal control is implemented here 2006.201.21:58:06.87$setupk4/"tpicd=stop 2006.201.21:58:06.87$setupk4/"rec=synch_on 2006.201.21:58:06.87$setupk4/"rec_mode=128 2006.201.21:58:06.87$setupk4/!* 2006.201.21:58:06.87$setupk4/recpk4 2006.201.21:58:06.87$recpk4/recpatch= 2006.201.21:58:06.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.21:58:06.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.21:58:06.88$setupk4/vck44 2006.201.21:58:06.88$vck44/valo=1,524.99 2006.201.21:58:06.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.21:58:06.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.21:58:06.88#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:06.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:06.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:06.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:06.88#ibcon#enter wrdev, iclass 20, count 0 2006.201.21:58:06.88#ibcon#first serial, iclass 20, count 0 2006.201.21:58:06.88#ibcon#enter sib2, iclass 20, count 0 2006.201.21:58:06.88#ibcon#flushed, iclass 20, count 0 2006.201.21:58:06.88#ibcon#about to write, iclass 20, count 0 2006.201.21:58:06.88#ibcon#wrote, iclass 20, count 0 2006.201.21:58:06.88#ibcon#about to read 3, iclass 20, count 0 2006.201.21:58:06.91#ibcon#read 3, iclass 20, count 0 2006.201.21:58:06.92#ibcon#about to read 4, iclass 20, count 0 2006.201.21:58:06.92#ibcon#read 4, iclass 20, count 0 2006.201.21:58:06.92#ibcon#about to read 5, iclass 20, count 0 2006.201.21:58:06.92#ibcon#read 5, iclass 20, count 0 2006.201.21:58:06.92#ibcon#about to read 6, iclass 20, count 0 2006.201.21:58:06.92#ibcon#read 6, iclass 20, count 0 2006.201.21:58:06.92#ibcon#end of sib2, iclass 20, count 0 2006.201.21:58:06.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.21:58:06.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.21:58:06.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.21:58:06.92#ibcon#*before write, iclass 20, count 0 2006.201.21:58:06.92#ibcon#enter sib2, iclass 20, count 0 2006.201.21:58:06.92#ibcon#flushed, iclass 20, count 0 2006.201.21:58:06.92#ibcon#about to write, iclass 20, count 0 2006.201.21:58:06.92#ibcon#wrote, iclass 20, count 0 2006.201.21:58:06.92#ibcon#about to read 3, iclass 20, count 0 2006.201.21:58:06.97#ibcon#read 3, iclass 20, count 0 2006.201.21:58:06.97#ibcon#about to read 4, iclass 20, count 0 2006.201.21:58:06.97#ibcon#read 4, iclass 20, count 0 2006.201.21:58:06.97#ibcon#about to read 5, iclass 20, count 0 2006.201.21:58:06.97#ibcon#read 5, iclass 20, count 0 2006.201.21:58:06.97#ibcon#about to read 6, iclass 20, count 0 2006.201.21:58:06.97#ibcon#read 6, iclass 20, count 0 2006.201.21:58:06.97#ibcon#end of sib2, iclass 20, count 0 2006.201.21:58:06.97#ibcon#*after write, iclass 20, count 0 2006.201.21:58:06.97#ibcon#*before return 0, iclass 20, count 0 2006.201.21:58:06.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:06.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:06.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.21:58:06.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.21:58:06.97$vck44/va=1,8 2006.201.21:58:06.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.21:58:06.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.21:58:06.97#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:06.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:06.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:06.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:06.97#ibcon#enter wrdev, iclass 22, count 2 2006.201.21:58:06.97#ibcon#first serial, iclass 22, count 2 2006.201.21:58:06.97#ibcon#enter sib2, iclass 22, count 2 2006.201.21:58:06.97#ibcon#flushed, iclass 22, count 2 2006.201.21:58:06.97#ibcon#about to write, iclass 22, count 2 2006.201.21:58:06.97#ibcon#wrote, iclass 22, count 2 2006.201.21:58:06.97#ibcon#about to read 3, iclass 22, count 2 2006.201.21:58:06.99#ibcon#read 3, iclass 22, count 2 2006.201.21:58:06.99#ibcon#about to read 4, iclass 22, count 2 2006.201.21:58:06.99#ibcon#read 4, iclass 22, count 2 2006.201.21:58:06.99#ibcon#about to read 5, iclass 22, count 2 2006.201.21:58:06.99#ibcon#read 5, iclass 22, count 2 2006.201.21:58:06.99#ibcon#about to read 6, iclass 22, count 2 2006.201.21:58:06.99#ibcon#read 6, iclass 22, count 2 2006.201.21:58:06.99#ibcon#end of sib2, iclass 22, count 2 2006.201.21:58:06.99#ibcon#*mode == 0, iclass 22, count 2 2006.201.21:58:06.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.21:58:06.99#ibcon#[25=AT01-08\r\n] 2006.201.21:58:06.99#ibcon#*before write, iclass 22, count 2 2006.201.21:58:06.99#ibcon#enter sib2, iclass 22, count 2 2006.201.21:58:06.99#ibcon#flushed, iclass 22, count 2 2006.201.21:58:06.99#ibcon#about to write, iclass 22, count 2 2006.201.21:58:06.99#ibcon#wrote, iclass 22, count 2 2006.201.21:58:06.99#ibcon#about to read 3, iclass 22, count 2 2006.201.21:58:07.03#ibcon#read 3, iclass 22, count 2 2006.201.21:58:07.03#ibcon#about to read 4, iclass 22, count 2 2006.201.21:58:07.03#ibcon#read 4, iclass 22, count 2 2006.201.21:58:07.03#ibcon#about to read 5, iclass 22, count 2 2006.201.21:58:07.03#ibcon#read 5, iclass 22, count 2 2006.201.21:58:07.03#ibcon#about to read 6, iclass 22, count 2 2006.201.21:58:07.03#ibcon#read 6, iclass 22, count 2 2006.201.21:58:07.03#ibcon#end of sib2, iclass 22, count 2 2006.201.21:58:07.03#ibcon#*after write, iclass 22, count 2 2006.201.21:58:07.03#ibcon#*before return 0, iclass 22, count 2 2006.201.21:58:07.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:07.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:07.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.21:58:07.03#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:07.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:07.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:07.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:07.15#ibcon#enter wrdev, iclass 22, count 0 2006.201.21:58:07.15#ibcon#first serial, iclass 22, count 0 2006.201.21:58:07.15#ibcon#enter sib2, iclass 22, count 0 2006.201.21:58:07.15#ibcon#flushed, iclass 22, count 0 2006.201.21:58:07.15#ibcon#about to write, iclass 22, count 0 2006.201.21:58:07.15#ibcon#wrote, iclass 22, count 0 2006.201.21:58:07.15#ibcon#about to read 3, iclass 22, count 0 2006.201.21:58:07.17#ibcon#read 3, iclass 22, count 0 2006.201.21:58:07.17#ibcon#about to read 4, iclass 22, count 0 2006.201.21:58:07.17#ibcon#read 4, iclass 22, count 0 2006.201.21:58:07.17#ibcon#about to read 5, iclass 22, count 0 2006.201.21:58:07.17#ibcon#read 5, iclass 22, count 0 2006.201.21:58:07.17#ibcon#about to read 6, iclass 22, count 0 2006.201.21:58:07.17#ibcon#read 6, iclass 22, count 0 2006.201.21:58:07.17#ibcon#end of sib2, iclass 22, count 0 2006.201.21:58:07.17#ibcon#*mode == 0, iclass 22, count 0 2006.201.21:58:07.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.21:58:07.17#ibcon#[25=USB\r\n] 2006.201.21:58:07.17#ibcon#*before write, iclass 22, count 0 2006.201.21:58:07.17#ibcon#enter sib2, iclass 22, count 0 2006.201.21:58:07.17#ibcon#flushed, iclass 22, count 0 2006.201.21:58:07.17#ibcon#about to write, iclass 22, count 0 2006.201.21:58:07.17#ibcon#wrote, iclass 22, count 0 2006.201.21:58:07.17#ibcon#about to read 3, iclass 22, count 0 2006.201.21:58:07.20#ibcon#read 3, iclass 22, count 0 2006.201.21:58:07.20#ibcon#about to read 4, iclass 22, count 0 2006.201.21:58:07.20#ibcon#read 4, iclass 22, count 0 2006.201.21:58:07.20#ibcon#about to read 5, iclass 22, count 0 2006.201.21:58:07.20#ibcon#read 5, iclass 22, count 0 2006.201.21:58:07.20#ibcon#about to read 6, iclass 22, count 0 2006.201.21:58:07.20#ibcon#read 6, iclass 22, count 0 2006.201.21:58:07.20#ibcon#end of sib2, iclass 22, count 0 2006.201.21:58:07.20#ibcon#*after write, iclass 22, count 0 2006.201.21:58:07.20#ibcon#*before return 0, iclass 22, count 0 2006.201.21:58:07.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:07.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:07.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.21:58:07.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.21:58:07.20$vck44/valo=2,534.99 2006.201.21:58:07.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.21:58:07.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.21:58:07.20#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:07.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:07.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:07.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:07.20#ibcon#enter wrdev, iclass 24, count 0 2006.201.21:58:07.20#ibcon#first serial, iclass 24, count 0 2006.201.21:58:07.20#ibcon#enter sib2, iclass 24, count 0 2006.201.21:58:07.20#ibcon#flushed, iclass 24, count 0 2006.201.21:58:07.20#ibcon#about to write, iclass 24, count 0 2006.201.21:58:07.20#ibcon#wrote, iclass 24, count 0 2006.201.21:58:07.20#ibcon#about to read 3, iclass 24, count 0 2006.201.21:58:07.22#ibcon#read 3, iclass 24, count 0 2006.201.21:58:07.22#ibcon#about to read 4, iclass 24, count 0 2006.201.21:58:07.22#ibcon#read 4, iclass 24, count 0 2006.201.21:58:07.22#ibcon#about to read 5, iclass 24, count 0 2006.201.21:58:07.22#ibcon#read 5, iclass 24, count 0 2006.201.21:58:07.22#ibcon#about to read 6, iclass 24, count 0 2006.201.21:58:07.22#ibcon#read 6, iclass 24, count 0 2006.201.21:58:07.22#ibcon#end of sib2, iclass 24, count 0 2006.201.21:58:07.22#ibcon#*mode == 0, iclass 24, count 0 2006.201.21:58:07.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.21:58:07.22#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.21:58:07.22#ibcon#*before write, iclass 24, count 0 2006.201.21:58:07.22#ibcon#enter sib2, iclass 24, count 0 2006.201.21:58:07.22#ibcon#flushed, iclass 24, count 0 2006.201.21:58:07.22#ibcon#about to write, iclass 24, count 0 2006.201.21:58:07.22#ibcon#wrote, iclass 24, count 0 2006.201.21:58:07.22#ibcon#about to read 3, iclass 24, count 0 2006.201.21:58:07.26#ibcon#read 3, iclass 24, count 0 2006.201.21:58:07.26#ibcon#about to read 4, iclass 24, count 0 2006.201.21:58:07.26#ibcon#read 4, iclass 24, count 0 2006.201.21:58:07.26#ibcon#about to read 5, iclass 24, count 0 2006.201.21:58:07.26#ibcon#read 5, iclass 24, count 0 2006.201.21:58:07.26#ibcon#about to read 6, iclass 24, count 0 2006.201.21:58:07.26#ibcon#read 6, iclass 24, count 0 2006.201.21:58:07.26#ibcon#end of sib2, iclass 24, count 0 2006.201.21:58:07.26#ibcon#*after write, iclass 24, count 0 2006.201.21:58:07.26#ibcon#*before return 0, iclass 24, count 0 2006.201.21:58:07.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:07.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:07.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.21:58:07.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.21:58:07.26$vck44/va=2,7 2006.201.21:58:07.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.21:58:07.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.21:58:07.26#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:07.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:07.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:07.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:07.32#ibcon#enter wrdev, iclass 26, count 2 2006.201.21:58:07.32#ibcon#first serial, iclass 26, count 2 2006.201.21:58:07.32#ibcon#enter sib2, iclass 26, count 2 2006.201.21:58:07.32#ibcon#flushed, iclass 26, count 2 2006.201.21:58:07.32#ibcon#about to write, iclass 26, count 2 2006.201.21:58:07.32#ibcon#wrote, iclass 26, count 2 2006.201.21:58:07.32#ibcon#about to read 3, iclass 26, count 2 2006.201.21:58:07.34#ibcon#read 3, iclass 26, count 2 2006.201.21:58:07.34#ibcon#about to read 4, iclass 26, count 2 2006.201.21:58:07.34#ibcon#read 4, iclass 26, count 2 2006.201.21:58:07.34#ibcon#about to read 5, iclass 26, count 2 2006.201.21:58:07.34#ibcon#read 5, iclass 26, count 2 2006.201.21:58:07.34#ibcon#about to read 6, iclass 26, count 2 2006.201.21:58:07.34#ibcon#read 6, iclass 26, count 2 2006.201.21:58:07.34#ibcon#end of sib2, iclass 26, count 2 2006.201.21:58:07.34#ibcon#*mode == 0, iclass 26, count 2 2006.201.21:58:07.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.21:58:07.34#ibcon#[25=AT02-07\r\n] 2006.201.21:58:07.34#ibcon#*before write, iclass 26, count 2 2006.201.21:58:07.34#ibcon#enter sib2, iclass 26, count 2 2006.201.21:58:07.34#ibcon#flushed, iclass 26, count 2 2006.201.21:58:07.34#ibcon#about to write, iclass 26, count 2 2006.201.21:58:07.34#ibcon#wrote, iclass 26, count 2 2006.201.21:58:07.34#ibcon#about to read 3, iclass 26, count 2 2006.201.21:58:07.37#ibcon#read 3, iclass 26, count 2 2006.201.21:58:07.37#ibcon#about to read 4, iclass 26, count 2 2006.201.21:58:07.37#ibcon#read 4, iclass 26, count 2 2006.201.21:58:07.37#ibcon#about to read 5, iclass 26, count 2 2006.201.21:58:07.37#ibcon#read 5, iclass 26, count 2 2006.201.21:58:07.37#ibcon#about to read 6, iclass 26, count 2 2006.201.21:58:07.37#ibcon#read 6, iclass 26, count 2 2006.201.21:58:07.37#ibcon#end of sib2, iclass 26, count 2 2006.201.21:58:07.37#ibcon#*after write, iclass 26, count 2 2006.201.21:58:07.37#ibcon#*before return 0, iclass 26, count 2 2006.201.21:58:07.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:07.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:07.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.21:58:07.37#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:07.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:07.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:07.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:07.49#ibcon#enter wrdev, iclass 26, count 0 2006.201.21:58:07.49#ibcon#first serial, iclass 26, count 0 2006.201.21:58:07.49#ibcon#enter sib2, iclass 26, count 0 2006.201.21:58:07.49#ibcon#flushed, iclass 26, count 0 2006.201.21:58:07.49#ibcon#about to write, iclass 26, count 0 2006.201.21:58:07.49#ibcon#wrote, iclass 26, count 0 2006.201.21:58:07.49#ibcon#about to read 3, iclass 26, count 0 2006.201.21:58:07.51#ibcon#read 3, iclass 26, count 0 2006.201.21:58:07.51#ibcon#about to read 4, iclass 26, count 0 2006.201.21:58:07.51#ibcon#read 4, iclass 26, count 0 2006.201.21:58:07.51#ibcon#about to read 5, iclass 26, count 0 2006.201.21:58:07.51#ibcon#read 5, iclass 26, count 0 2006.201.21:58:07.51#ibcon#about to read 6, iclass 26, count 0 2006.201.21:58:07.51#ibcon#read 6, iclass 26, count 0 2006.201.21:58:07.51#ibcon#end of sib2, iclass 26, count 0 2006.201.21:58:07.51#ibcon#*mode == 0, iclass 26, count 0 2006.201.21:58:07.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.21:58:07.51#ibcon#[25=USB\r\n] 2006.201.21:58:07.51#ibcon#*before write, iclass 26, count 0 2006.201.21:58:07.51#ibcon#enter sib2, iclass 26, count 0 2006.201.21:58:07.51#ibcon#flushed, iclass 26, count 0 2006.201.21:58:07.51#ibcon#about to write, iclass 26, count 0 2006.201.21:58:07.51#ibcon#wrote, iclass 26, count 0 2006.201.21:58:07.51#ibcon#about to read 3, iclass 26, count 0 2006.201.21:58:07.54#ibcon#read 3, iclass 26, count 0 2006.201.21:58:07.54#ibcon#about to read 4, iclass 26, count 0 2006.201.21:58:07.54#ibcon#read 4, iclass 26, count 0 2006.201.21:58:07.54#ibcon#about to read 5, iclass 26, count 0 2006.201.21:58:07.54#ibcon#read 5, iclass 26, count 0 2006.201.21:58:07.54#ibcon#about to read 6, iclass 26, count 0 2006.201.21:58:07.54#ibcon#read 6, iclass 26, count 0 2006.201.21:58:07.54#ibcon#end of sib2, iclass 26, count 0 2006.201.21:58:07.54#ibcon#*after write, iclass 26, count 0 2006.201.21:58:07.54#ibcon#*before return 0, iclass 26, count 0 2006.201.21:58:07.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:07.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:07.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.21:58:07.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.21:58:07.54$vck44/valo=3,564.99 2006.201.21:58:07.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.21:58:07.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.21:58:07.54#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:07.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:07.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:07.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:07.54#ibcon#enter wrdev, iclass 28, count 0 2006.201.21:58:07.54#ibcon#first serial, iclass 28, count 0 2006.201.21:58:07.54#ibcon#enter sib2, iclass 28, count 0 2006.201.21:58:07.54#ibcon#flushed, iclass 28, count 0 2006.201.21:58:07.54#ibcon#about to write, iclass 28, count 0 2006.201.21:58:07.54#ibcon#wrote, iclass 28, count 0 2006.201.21:58:07.54#ibcon#about to read 3, iclass 28, count 0 2006.201.21:58:07.56#ibcon#read 3, iclass 28, count 0 2006.201.21:58:07.56#ibcon#about to read 4, iclass 28, count 0 2006.201.21:58:07.56#ibcon#read 4, iclass 28, count 0 2006.201.21:58:07.56#ibcon#about to read 5, iclass 28, count 0 2006.201.21:58:07.56#ibcon#read 5, iclass 28, count 0 2006.201.21:58:07.56#ibcon#about to read 6, iclass 28, count 0 2006.201.21:58:07.56#ibcon#read 6, iclass 28, count 0 2006.201.21:58:07.56#ibcon#end of sib2, iclass 28, count 0 2006.201.21:58:07.56#ibcon#*mode == 0, iclass 28, count 0 2006.201.21:58:07.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.21:58:07.56#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.21:58:07.56#ibcon#*before write, iclass 28, count 0 2006.201.21:58:07.56#ibcon#enter sib2, iclass 28, count 0 2006.201.21:58:07.56#ibcon#flushed, iclass 28, count 0 2006.201.21:58:07.56#ibcon#about to write, iclass 28, count 0 2006.201.21:58:07.56#ibcon#wrote, iclass 28, count 0 2006.201.21:58:07.56#ibcon#about to read 3, iclass 28, count 0 2006.201.21:58:07.61#ibcon#read 3, iclass 28, count 0 2006.201.21:58:07.61#ibcon#about to read 4, iclass 28, count 0 2006.201.21:58:07.61#ibcon#read 4, iclass 28, count 0 2006.201.21:58:07.61#ibcon#about to read 5, iclass 28, count 0 2006.201.21:58:07.61#ibcon#read 5, iclass 28, count 0 2006.201.21:58:07.61#ibcon#about to read 6, iclass 28, count 0 2006.201.21:58:07.61#ibcon#read 6, iclass 28, count 0 2006.201.21:58:07.61#ibcon#end of sib2, iclass 28, count 0 2006.201.21:58:07.61#ibcon#*after write, iclass 28, count 0 2006.201.21:58:07.61#ibcon#*before return 0, iclass 28, count 0 2006.201.21:58:07.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:07.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:07.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.21:58:07.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.21:58:07.61$vck44/va=3,8 2006.201.21:58:07.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.21:58:07.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.21:58:07.61#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:07.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:07.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:07.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:07.66#ibcon#enter wrdev, iclass 30, count 2 2006.201.21:58:07.66#ibcon#first serial, iclass 30, count 2 2006.201.21:58:07.66#ibcon#enter sib2, iclass 30, count 2 2006.201.21:58:07.66#ibcon#flushed, iclass 30, count 2 2006.201.21:58:07.66#ibcon#about to write, iclass 30, count 2 2006.201.21:58:07.66#ibcon#wrote, iclass 30, count 2 2006.201.21:58:07.66#ibcon#about to read 3, iclass 30, count 2 2006.201.21:58:07.68#ibcon#read 3, iclass 30, count 2 2006.201.21:58:07.68#ibcon#about to read 4, iclass 30, count 2 2006.201.21:58:07.68#ibcon#read 4, iclass 30, count 2 2006.201.21:58:07.68#ibcon#about to read 5, iclass 30, count 2 2006.201.21:58:07.68#ibcon#read 5, iclass 30, count 2 2006.201.21:58:07.68#ibcon#about to read 6, iclass 30, count 2 2006.201.21:58:07.68#ibcon#read 6, iclass 30, count 2 2006.201.21:58:07.68#ibcon#end of sib2, iclass 30, count 2 2006.201.21:58:07.68#ibcon#*mode == 0, iclass 30, count 2 2006.201.21:58:07.68#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.21:58:07.68#ibcon#[25=AT03-08\r\n] 2006.201.21:58:07.68#ibcon#*before write, iclass 30, count 2 2006.201.21:58:07.68#ibcon#enter sib2, iclass 30, count 2 2006.201.21:58:07.68#ibcon#flushed, iclass 30, count 2 2006.201.21:58:07.68#ibcon#about to write, iclass 30, count 2 2006.201.21:58:07.68#ibcon#wrote, iclass 30, count 2 2006.201.21:58:07.68#ibcon#about to read 3, iclass 30, count 2 2006.201.21:58:07.71#ibcon#read 3, iclass 30, count 2 2006.201.21:58:07.71#ibcon#about to read 4, iclass 30, count 2 2006.201.21:58:07.71#ibcon#read 4, iclass 30, count 2 2006.201.21:58:07.71#ibcon#about to read 5, iclass 30, count 2 2006.201.21:58:07.71#ibcon#read 5, iclass 30, count 2 2006.201.21:58:07.71#ibcon#about to read 6, iclass 30, count 2 2006.201.21:58:07.71#ibcon#read 6, iclass 30, count 2 2006.201.21:58:07.71#ibcon#end of sib2, iclass 30, count 2 2006.201.21:58:07.71#ibcon#*after write, iclass 30, count 2 2006.201.21:58:07.71#ibcon#*before return 0, iclass 30, count 2 2006.201.21:58:07.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:07.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:07.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.21:58:07.71#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:07.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:07.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:07.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:07.83#ibcon#enter wrdev, iclass 30, count 0 2006.201.21:58:07.83#ibcon#first serial, iclass 30, count 0 2006.201.21:58:07.83#ibcon#enter sib2, iclass 30, count 0 2006.201.21:58:07.83#ibcon#flushed, iclass 30, count 0 2006.201.21:58:07.83#ibcon#about to write, iclass 30, count 0 2006.201.21:58:07.83#ibcon#wrote, iclass 30, count 0 2006.201.21:58:07.83#ibcon#about to read 3, iclass 30, count 0 2006.201.21:58:07.85#ibcon#read 3, iclass 30, count 0 2006.201.21:58:07.85#ibcon#about to read 4, iclass 30, count 0 2006.201.21:58:07.85#ibcon#read 4, iclass 30, count 0 2006.201.21:58:07.85#ibcon#about to read 5, iclass 30, count 0 2006.201.21:58:07.85#ibcon#read 5, iclass 30, count 0 2006.201.21:58:07.85#ibcon#about to read 6, iclass 30, count 0 2006.201.21:58:07.85#ibcon#read 6, iclass 30, count 0 2006.201.21:58:07.85#ibcon#end of sib2, iclass 30, count 0 2006.201.21:58:07.85#ibcon#*mode == 0, iclass 30, count 0 2006.201.21:58:07.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.21:58:07.85#ibcon#[25=USB\r\n] 2006.201.21:58:07.85#ibcon#*before write, iclass 30, count 0 2006.201.21:58:07.85#ibcon#enter sib2, iclass 30, count 0 2006.201.21:58:07.85#ibcon#flushed, iclass 30, count 0 2006.201.21:58:07.85#ibcon#about to write, iclass 30, count 0 2006.201.21:58:07.85#ibcon#wrote, iclass 30, count 0 2006.201.21:58:07.85#ibcon#about to read 3, iclass 30, count 0 2006.201.21:58:07.88#ibcon#read 3, iclass 30, count 0 2006.201.21:58:07.88#ibcon#about to read 4, iclass 30, count 0 2006.201.21:58:07.88#ibcon#read 4, iclass 30, count 0 2006.201.21:58:07.88#ibcon#about to read 5, iclass 30, count 0 2006.201.21:58:07.88#ibcon#read 5, iclass 30, count 0 2006.201.21:58:07.88#ibcon#about to read 6, iclass 30, count 0 2006.201.21:58:07.88#ibcon#read 6, iclass 30, count 0 2006.201.21:58:07.88#ibcon#end of sib2, iclass 30, count 0 2006.201.21:58:07.88#ibcon#*after write, iclass 30, count 0 2006.201.21:58:07.88#ibcon#*before return 0, iclass 30, count 0 2006.201.21:58:07.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:07.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:07.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.21:58:07.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.21:58:07.88$vck44/valo=4,624.99 2006.201.21:58:07.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.21:58:07.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.21:58:07.88#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:07.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:07.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:07.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:07.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.21:58:07.88#ibcon#first serial, iclass 32, count 0 2006.201.21:58:07.88#ibcon#enter sib2, iclass 32, count 0 2006.201.21:58:07.88#ibcon#flushed, iclass 32, count 0 2006.201.21:58:07.88#ibcon#about to write, iclass 32, count 0 2006.201.21:58:07.88#ibcon#wrote, iclass 32, count 0 2006.201.21:58:07.88#ibcon#about to read 3, iclass 32, count 0 2006.201.21:58:07.90#ibcon#read 3, iclass 32, count 0 2006.201.21:58:07.90#ibcon#about to read 4, iclass 32, count 0 2006.201.21:58:07.90#ibcon#read 4, iclass 32, count 0 2006.201.21:58:07.90#ibcon#about to read 5, iclass 32, count 0 2006.201.21:58:07.90#ibcon#read 5, iclass 32, count 0 2006.201.21:58:07.90#ibcon#about to read 6, iclass 32, count 0 2006.201.21:58:07.90#ibcon#read 6, iclass 32, count 0 2006.201.21:58:07.90#ibcon#end of sib2, iclass 32, count 0 2006.201.21:58:07.90#ibcon#*mode == 0, iclass 32, count 0 2006.201.21:58:07.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.21:58:07.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.21:58:07.90#ibcon#*before write, iclass 32, count 0 2006.201.21:58:07.90#ibcon#enter sib2, iclass 32, count 0 2006.201.21:58:07.90#ibcon#flushed, iclass 32, count 0 2006.201.21:58:07.90#ibcon#about to write, iclass 32, count 0 2006.201.21:58:07.90#ibcon#wrote, iclass 32, count 0 2006.201.21:58:07.90#ibcon#about to read 3, iclass 32, count 0 2006.201.21:58:07.95#ibcon#read 3, iclass 32, count 0 2006.201.21:58:07.95#ibcon#about to read 4, iclass 32, count 0 2006.201.21:58:07.95#ibcon#read 4, iclass 32, count 0 2006.201.21:58:07.95#ibcon#about to read 5, iclass 32, count 0 2006.201.21:58:07.95#ibcon#read 5, iclass 32, count 0 2006.201.21:58:07.95#ibcon#about to read 6, iclass 32, count 0 2006.201.21:58:07.95#ibcon#read 6, iclass 32, count 0 2006.201.21:58:07.95#ibcon#end of sib2, iclass 32, count 0 2006.201.21:58:07.95#ibcon#*after write, iclass 32, count 0 2006.201.21:58:07.95#ibcon#*before return 0, iclass 32, count 0 2006.201.21:58:07.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:07.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:07.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.21:58:07.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.21:58:07.95$vck44/va=4,7 2006.201.21:58:07.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.21:58:07.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.21:58:07.95#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:07.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:08.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:08.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:08.00#ibcon#enter wrdev, iclass 34, count 2 2006.201.21:58:08.00#ibcon#first serial, iclass 34, count 2 2006.201.21:58:08.00#ibcon#enter sib2, iclass 34, count 2 2006.201.21:58:08.00#ibcon#flushed, iclass 34, count 2 2006.201.21:58:08.00#ibcon#about to write, iclass 34, count 2 2006.201.21:58:08.00#ibcon#wrote, iclass 34, count 2 2006.201.21:58:08.00#ibcon#about to read 3, iclass 34, count 2 2006.201.21:58:08.02#ibcon#read 3, iclass 34, count 2 2006.201.21:58:08.02#ibcon#about to read 4, iclass 34, count 2 2006.201.21:58:08.02#ibcon#read 4, iclass 34, count 2 2006.201.21:58:08.02#ibcon#about to read 5, iclass 34, count 2 2006.201.21:58:08.02#ibcon#read 5, iclass 34, count 2 2006.201.21:58:08.02#ibcon#about to read 6, iclass 34, count 2 2006.201.21:58:08.02#ibcon#read 6, iclass 34, count 2 2006.201.21:58:08.02#ibcon#end of sib2, iclass 34, count 2 2006.201.21:58:08.02#ibcon#*mode == 0, iclass 34, count 2 2006.201.21:58:08.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.21:58:08.02#ibcon#[25=AT04-07\r\n] 2006.201.21:58:08.02#ibcon#*before write, iclass 34, count 2 2006.201.21:58:08.02#ibcon#enter sib2, iclass 34, count 2 2006.201.21:58:08.02#ibcon#flushed, iclass 34, count 2 2006.201.21:58:08.02#ibcon#about to write, iclass 34, count 2 2006.201.21:58:08.02#ibcon#wrote, iclass 34, count 2 2006.201.21:58:08.02#ibcon#about to read 3, iclass 34, count 2 2006.201.21:58:08.05#ibcon#read 3, iclass 34, count 2 2006.201.21:58:08.05#ibcon#about to read 4, iclass 34, count 2 2006.201.21:58:08.05#ibcon#read 4, iclass 34, count 2 2006.201.21:58:08.05#ibcon#about to read 5, iclass 34, count 2 2006.201.21:58:08.05#ibcon#read 5, iclass 34, count 2 2006.201.21:58:08.05#ibcon#about to read 6, iclass 34, count 2 2006.201.21:58:08.05#ibcon#read 6, iclass 34, count 2 2006.201.21:58:08.05#ibcon#end of sib2, iclass 34, count 2 2006.201.21:58:08.05#ibcon#*after write, iclass 34, count 2 2006.201.21:58:08.05#ibcon#*before return 0, iclass 34, count 2 2006.201.21:58:08.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:08.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:08.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.21:58:08.05#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:08.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:08.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:08.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:08.17#ibcon#enter wrdev, iclass 34, count 0 2006.201.21:58:08.17#ibcon#first serial, iclass 34, count 0 2006.201.21:58:08.17#ibcon#enter sib2, iclass 34, count 0 2006.201.21:58:08.17#ibcon#flushed, iclass 34, count 0 2006.201.21:58:08.17#ibcon#about to write, iclass 34, count 0 2006.201.21:58:08.17#ibcon#wrote, iclass 34, count 0 2006.201.21:58:08.17#ibcon#about to read 3, iclass 34, count 0 2006.201.21:58:08.19#ibcon#read 3, iclass 34, count 0 2006.201.21:58:08.19#ibcon#about to read 4, iclass 34, count 0 2006.201.21:58:08.19#ibcon#read 4, iclass 34, count 0 2006.201.21:58:08.19#ibcon#about to read 5, iclass 34, count 0 2006.201.21:58:08.19#ibcon#read 5, iclass 34, count 0 2006.201.21:58:08.19#ibcon#about to read 6, iclass 34, count 0 2006.201.21:58:08.19#ibcon#read 6, iclass 34, count 0 2006.201.21:58:08.19#ibcon#end of sib2, iclass 34, count 0 2006.201.21:58:08.19#ibcon#*mode == 0, iclass 34, count 0 2006.201.21:58:08.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.21:58:08.19#ibcon#[25=USB\r\n] 2006.201.21:58:08.19#ibcon#*before write, iclass 34, count 0 2006.201.21:58:08.19#ibcon#enter sib2, iclass 34, count 0 2006.201.21:58:08.19#ibcon#flushed, iclass 34, count 0 2006.201.21:58:08.19#ibcon#about to write, iclass 34, count 0 2006.201.21:58:08.19#ibcon#wrote, iclass 34, count 0 2006.201.21:58:08.19#ibcon#about to read 3, iclass 34, count 0 2006.201.21:58:08.22#ibcon#read 3, iclass 34, count 0 2006.201.21:58:08.22#ibcon#about to read 4, iclass 34, count 0 2006.201.21:58:08.22#ibcon#read 4, iclass 34, count 0 2006.201.21:58:08.22#ibcon#about to read 5, iclass 34, count 0 2006.201.21:58:08.22#ibcon#read 5, iclass 34, count 0 2006.201.21:58:08.22#ibcon#about to read 6, iclass 34, count 0 2006.201.21:58:08.22#ibcon#read 6, iclass 34, count 0 2006.201.21:58:08.22#ibcon#end of sib2, iclass 34, count 0 2006.201.21:58:08.22#ibcon#*after write, iclass 34, count 0 2006.201.21:58:08.22#ibcon#*before return 0, iclass 34, count 0 2006.201.21:58:08.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:08.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:08.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.21:58:08.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.21:58:08.22$vck44/valo=5,734.99 2006.201.21:58:08.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.21:58:08.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.21:58:08.22#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:08.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:08.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:08.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:08.22#ibcon#enter wrdev, iclass 36, count 0 2006.201.21:58:08.22#ibcon#first serial, iclass 36, count 0 2006.201.21:58:08.22#ibcon#enter sib2, iclass 36, count 0 2006.201.21:58:08.22#ibcon#flushed, iclass 36, count 0 2006.201.21:58:08.22#ibcon#about to write, iclass 36, count 0 2006.201.21:58:08.22#ibcon#wrote, iclass 36, count 0 2006.201.21:58:08.22#ibcon#about to read 3, iclass 36, count 0 2006.201.21:58:08.24#ibcon#read 3, iclass 36, count 0 2006.201.21:58:08.24#ibcon#about to read 4, iclass 36, count 0 2006.201.21:58:08.24#ibcon#read 4, iclass 36, count 0 2006.201.21:58:08.24#ibcon#about to read 5, iclass 36, count 0 2006.201.21:58:08.24#ibcon#read 5, iclass 36, count 0 2006.201.21:58:08.24#ibcon#about to read 6, iclass 36, count 0 2006.201.21:58:08.24#ibcon#read 6, iclass 36, count 0 2006.201.21:58:08.24#ibcon#end of sib2, iclass 36, count 0 2006.201.21:58:08.24#ibcon#*mode == 0, iclass 36, count 0 2006.201.21:58:08.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.21:58:08.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.21:58:08.24#ibcon#*before write, iclass 36, count 0 2006.201.21:58:08.24#ibcon#enter sib2, iclass 36, count 0 2006.201.21:58:08.24#ibcon#flushed, iclass 36, count 0 2006.201.21:58:08.24#ibcon#about to write, iclass 36, count 0 2006.201.21:58:08.24#ibcon#wrote, iclass 36, count 0 2006.201.21:58:08.24#ibcon#about to read 3, iclass 36, count 0 2006.201.21:58:08.28#ibcon#read 3, iclass 36, count 0 2006.201.21:58:08.28#ibcon#about to read 4, iclass 36, count 0 2006.201.21:58:08.28#ibcon#read 4, iclass 36, count 0 2006.201.21:58:08.28#ibcon#about to read 5, iclass 36, count 0 2006.201.21:58:08.28#ibcon#read 5, iclass 36, count 0 2006.201.21:58:08.28#ibcon#about to read 6, iclass 36, count 0 2006.201.21:58:08.28#ibcon#read 6, iclass 36, count 0 2006.201.21:58:08.28#ibcon#end of sib2, iclass 36, count 0 2006.201.21:58:08.28#ibcon#*after write, iclass 36, count 0 2006.201.21:58:08.28#ibcon#*before return 0, iclass 36, count 0 2006.201.21:58:08.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:08.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:08.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.21:58:08.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.21:58:08.28$vck44/va=5,4 2006.201.21:58:08.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.21:58:08.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.21:58:08.28#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:08.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:08.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:08.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:08.34#ibcon#enter wrdev, iclass 38, count 2 2006.201.21:58:08.34#ibcon#first serial, iclass 38, count 2 2006.201.21:58:08.34#ibcon#enter sib2, iclass 38, count 2 2006.201.21:58:08.34#ibcon#flushed, iclass 38, count 2 2006.201.21:58:08.34#ibcon#about to write, iclass 38, count 2 2006.201.21:58:08.34#ibcon#wrote, iclass 38, count 2 2006.201.21:58:08.34#ibcon#about to read 3, iclass 38, count 2 2006.201.21:58:08.36#ibcon#read 3, iclass 38, count 2 2006.201.21:58:08.36#ibcon#about to read 4, iclass 38, count 2 2006.201.21:58:08.36#ibcon#read 4, iclass 38, count 2 2006.201.21:58:08.36#ibcon#about to read 5, iclass 38, count 2 2006.201.21:58:08.36#ibcon#read 5, iclass 38, count 2 2006.201.21:58:08.36#ibcon#about to read 6, iclass 38, count 2 2006.201.21:58:08.36#ibcon#read 6, iclass 38, count 2 2006.201.21:58:08.36#ibcon#end of sib2, iclass 38, count 2 2006.201.21:58:08.36#ibcon#*mode == 0, iclass 38, count 2 2006.201.21:58:08.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.21:58:08.36#ibcon#[25=AT05-04\r\n] 2006.201.21:58:08.36#ibcon#*before write, iclass 38, count 2 2006.201.21:58:08.36#ibcon#enter sib2, iclass 38, count 2 2006.201.21:58:08.36#ibcon#flushed, iclass 38, count 2 2006.201.21:58:08.36#ibcon#about to write, iclass 38, count 2 2006.201.21:58:08.36#ibcon#wrote, iclass 38, count 2 2006.201.21:58:08.36#ibcon#about to read 3, iclass 38, count 2 2006.201.21:58:08.39#ibcon#read 3, iclass 38, count 2 2006.201.21:58:08.39#ibcon#about to read 4, iclass 38, count 2 2006.201.21:58:08.39#ibcon#read 4, iclass 38, count 2 2006.201.21:58:08.39#ibcon#about to read 5, iclass 38, count 2 2006.201.21:58:08.39#ibcon#read 5, iclass 38, count 2 2006.201.21:58:08.39#ibcon#about to read 6, iclass 38, count 2 2006.201.21:58:08.39#ibcon#read 6, iclass 38, count 2 2006.201.21:58:08.39#ibcon#end of sib2, iclass 38, count 2 2006.201.21:58:08.39#ibcon#*after write, iclass 38, count 2 2006.201.21:58:08.39#ibcon#*before return 0, iclass 38, count 2 2006.201.21:58:08.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:08.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:08.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.21:58:08.39#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:08.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:08.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:08.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:08.51#ibcon#enter wrdev, iclass 38, count 0 2006.201.21:58:08.51#ibcon#first serial, iclass 38, count 0 2006.201.21:58:08.51#ibcon#enter sib2, iclass 38, count 0 2006.201.21:58:08.51#ibcon#flushed, iclass 38, count 0 2006.201.21:58:08.51#ibcon#about to write, iclass 38, count 0 2006.201.21:58:08.51#ibcon#wrote, iclass 38, count 0 2006.201.21:58:08.51#ibcon#about to read 3, iclass 38, count 0 2006.201.21:58:08.53#ibcon#read 3, iclass 38, count 0 2006.201.21:58:08.53#ibcon#about to read 4, iclass 38, count 0 2006.201.21:58:08.53#ibcon#read 4, iclass 38, count 0 2006.201.21:58:08.53#ibcon#about to read 5, iclass 38, count 0 2006.201.21:58:08.53#ibcon#read 5, iclass 38, count 0 2006.201.21:58:08.53#ibcon#about to read 6, iclass 38, count 0 2006.201.21:58:08.53#ibcon#read 6, iclass 38, count 0 2006.201.21:58:08.53#ibcon#end of sib2, iclass 38, count 0 2006.201.21:58:08.53#ibcon#*mode == 0, iclass 38, count 0 2006.201.21:58:08.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.21:58:08.53#ibcon#[25=USB\r\n] 2006.201.21:58:08.53#ibcon#*before write, iclass 38, count 0 2006.201.21:58:08.53#ibcon#enter sib2, iclass 38, count 0 2006.201.21:58:08.53#ibcon#flushed, iclass 38, count 0 2006.201.21:58:08.53#ibcon#about to write, iclass 38, count 0 2006.201.21:58:08.53#ibcon#wrote, iclass 38, count 0 2006.201.21:58:08.53#ibcon#about to read 3, iclass 38, count 0 2006.201.21:58:08.56#ibcon#read 3, iclass 38, count 0 2006.201.21:58:08.56#ibcon#about to read 4, iclass 38, count 0 2006.201.21:58:08.56#ibcon#read 4, iclass 38, count 0 2006.201.21:58:08.56#ibcon#about to read 5, iclass 38, count 0 2006.201.21:58:08.56#ibcon#read 5, iclass 38, count 0 2006.201.21:58:08.56#ibcon#about to read 6, iclass 38, count 0 2006.201.21:58:08.56#ibcon#read 6, iclass 38, count 0 2006.201.21:58:08.56#ibcon#end of sib2, iclass 38, count 0 2006.201.21:58:08.56#ibcon#*after write, iclass 38, count 0 2006.201.21:58:08.56#ibcon#*before return 0, iclass 38, count 0 2006.201.21:58:08.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:08.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:08.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.21:58:08.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.21:58:08.56$vck44/valo=6,814.99 2006.201.21:58:08.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.21:58:08.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.21:58:08.56#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:08.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:08.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:08.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:08.56#ibcon#enter wrdev, iclass 40, count 0 2006.201.21:58:08.56#ibcon#first serial, iclass 40, count 0 2006.201.21:58:08.56#ibcon#enter sib2, iclass 40, count 0 2006.201.21:58:08.56#ibcon#flushed, iclass 40, count 0 2006.201.21:58:08.56#ibcon#about to write, iclass 40, count 0 2006.201.21:58:08.56#ibcon#wrote, iclass 40, count 0 2006.201.21:58:08.56#ibcon#about to read 3, iclass 40, count 0 2006.201.21:58:08.58#ibcon#read 3, iclass 40, count 0 2006.201.21:58:08.58#ibcon#about to read 4, iclass 40, count 0 2006.201.21:58:08.58#ibcon#read 4, iclass 40, count 0 2006.201.21:58:08.58#ibcon#about to read 5, iclass 40, count 0 2006.201.21:58:08.58#ibcon#read 5, iclass 40, count 0 2006.201.21:58:08.58#ibcon#about to read 6, iclass 40, count 0 2006.201.21:58:08.58#ibcon#read 6, iclass 40, count 0 2006.201.21:58:08.58#ibcon#end of sib2, iclass 40, count 0 2006.201.21:58:08.58#ibcon#*mode == 0, iclass 40, count 0 2006.201.21:58:08.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.21:58:08.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.21:58:08.58#ibcon#*before write, iclass 40, count 0 2006.201.21:58:08.58#ibcon#enter sib2, iclass 40, count 0 2006.201.21:58:08.58#ibcon#flushed, iclass 40, count 0 2006.201.21:58:08.58#ibcon#about to write, iclass 40, count 0 2006.201.21:58:08.58#ibcon#wrote, iclass 40, count 0 2006.201.21:58:08.58#ibcon#about to read 3, iclass 40, count 0 2006.201.21:58:08.63#ibcon#read 3, iclass 40, count 0 2006.201.21:58:08.63#ibcon#about to read 4, iclass 40, count 0 2006.201.21:58:08.63#ibcon#read 4, iclass 40, count 0 2006.201.21:58:08.63#ibcon#about to read 5, iclass 40, count 0 2006.201.21:58:08.63#ibcon#read 5, iclass 40, count 0 2006.201.21:58:08.63#ibcon#about to read 6, iclass 40, count 0 2006.201.21:58:08.63#ibcon#read 6, iclass 40, count 0 2006.201.21:58:08.63#ibcon#end of sib2, iclass 40, count 0 2006.201.21:58:08.63#ibcon#*after write, iclass 40, count 0 2006.201.21:58:08.63#ibcon#*before return 0, iclass 40, count 0 2006.201.21:58:08.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:08.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:08.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.21:58:08.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.21:58:08.63$vck44/va=6,5 2006.201.21:58:08.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.21:58:08.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.21:58:08.63#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:08.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:08.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:08.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:08.68#ibcon#enter wrdev, iclass 4, count 2 2006.201.21:58:08.68#ibcon#first serial, iclass 4, count 2 2006.201.21:58:08.68#ibcon#enter sib2, iclass 4, count 2 2006.201.21:58:08.68#ibcon#flushed, iclass 4, count 2 2006.201.21:58:08.68#ibcon#about to write, iclass 4, count 2 2006.201.21:58:08.68#ibcon#wrote, iclass 4, count 2 2006.201.21:58:08.68#ibcon#about to read 3, iclass 4, count 2 2006.201.21:58:08.70#ibcon#read 3, iclass 4, count 2 2006.201.21:58:08.70#ibcon#about to read 4, iclass 4, count 2 2006.201.21:58:08.70#ibcon#read 4, iclass 4, count 2 2006.201.21:58:08.70#ibcon#about to read 5, iclass 4, count 2 2006.201.21:58:08.70#ibcon#read 5, iclass 4, count 2 2006.201.21:58:08.70#ibcon#about to read 6, iclass 4, count 2 2006.201.21:58:08.70#ibcon#read 6, iclass 4, count 2 2006.201.21:58:08.70#ibcon#end of sib2, iclass 4, count 2 2006.201.21:58:08.70#ibcon#*mode == 0, iclass 4, count 2 2006.201.21:58:08.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.21:58:08.70#ibcon#[25=AT06-05\r\n] 2006.201.21:58:08.70#ibcon#*before write, iclass 4, count 2 2006.201.21:58:08.70#ibcon#enter sib2, iclass 4, count 2 2006.201.21:58:08.70#ibcon#flushed, iclass 4, count 2 2006.201.21:58:08.70#ibcon#about to write, iclass 4, count 2 2006.201.21:58:08.70#ibcon#wrote, iclass 4, count 2 2006.201.21:58:08.70#ibcon#about to read 3, iclass 4, count 2 2006.201.21:58:08.73#ibcon#read 3, iclass 4, count 2 2006.201.21:58:08.73#ibcon#about to read 4, iclass 4, count 2 2006.201.21:58:08.73#ibcon#read 4, iclass 4, count 2 2006.201.21:58:08.73#ibcon#about to read 5, iclass 4, count 2 2006.201.21:58:08.73#ibcon#read 5, iclass 4, count 2 2006.201.21:58:08.73#ibcon#about to read 6, iclass 4, count 2 2006.201.21:58:08.73#ibcon#read 6, iclass 4, count 2 2006.201.21:58:08.73#ibcon#end of sib2, iclass 4, count 2 2006.201.21:58:08.73#ibcon#*after write, iclass 4, count 2 2006.201.21:58:08.73#ibcon#*before return 0, iclass 4, count 2 2006.201.21:58:08.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:08.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:08.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.21:58:08.73#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:08.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:08.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:08.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:08.85#ibcon#enter wrdev, iclass 4, count 0 2006.201.21:58:08.85#ibcon#first serial, iclass 4, count 0 2006.201.21:58:08.85#ibcon#enter sib2, iclass 4, count 0 2006.201.21:58:08.85#ibcon#flushed, iclass 4, count 0 2006.201.21:58:08.85#ibcon#about to write, iclass 4, count 0 2006.201.21:58:08.85#ibcon#wrote, iclass 4, count 0 2006.201.21:58:08.85#ibcon#about to read 3, iclass 4, count 0 2006.201.21:58:08.87#ibcon#read 3, iclass 4, count 0 2006.201.21:58:08.87#ibcon#about to read 4, iclass 4, count 0 2006.201.21:58:08.87#ibcon#read 4, iclass 4, count 0 2006.201.21:58:08.87#ibcon#about to read 5, iclass 4, count 0 2006.201.21:58:08.87#ibcon#read 5, iclass 4, count 0 2006.201.21:58:08.87#ibcon#about to read 6, iclass 4, count 0 2006.201.21:58:08.87#ibcon#read 6, iclass 4, count 0 2006.201.21:58:08.87#ibcon#end of sib2, iclass 4, count 0 2006.201.21:58:08.87#ibcon#*mode == 0, iclass 4, count 0 2006.201.21:58:08.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.21:58:08.87#ibcon#[25=USB\r\n] 2006.201.21:58:08.87#ibcon#*before write, iclass 4, count 0 2006.201.21:58:08.87#ibcon#enter sib2, iclass 4, count 0 2006.201.21:58:08.87#ibcon#flushed, iclass 4, count 0 2006.201.21:58:08.87#ibcon#about to write, iclass 4, count 0 2006.201.21:58:08.87#ibcon#wrote, iclass 4, count 0 2006.201.21:58:08.87#ibcon#about to read 3, iclass 4, count 0 2006.201.21:58:08.90#ibcon#read 3, iclass 4, count 0 2006.201.21:58:08.90#ibcon#about to read 4, iclass 4, count 0 2006.201.21:58:08.90#ibcon#read 4, iclass 4, count 0 2006.201.21:58:08.90#ibcon#about to read 5, iclass 4, count 0 2006.201.21:58:08.90#ibcon#read 5, iclass 4, count 0 2006.201.21:58:08.90#ibcon#about to read 6, iclass 4, count 0 2006.201.21:58:08.90#ibcon#read 6, iclass 4, count 0 2006.201.21:58:08.90#ibcon#end of sib2, iclass 4, count 0 2006.201.21:58:08.90#ibcon#*after write, iclass 4, count 0 2006.201.21:58:08.90#ibcon#*before return 0, iclass 4, count 0 2006.201.21:58:08.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:08.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:08.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.21:58:08.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.21:58:08.90$vck44/valo=7,864.99 2006.201.21:58:08.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.21:58:08.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.21:58:08.90#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:08.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:08.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:08.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:08.90#ibcon#enter wrdev, iclass 6, count 0 2006.201.21:58:08.90#ibcon#first serial, iclass 6, count 0 2006.201.21:58:08.90#ibcon#enter sib2, iclass 6, count 0 2006.201.21:58:08.90#ibcon#flushed, iclass 6, count 0 2006.201.21:58:08.90#ibcon#about to write, iclass 6, count 0 2006.201.21:58:08.90#ibcon#wrote, iclass 6, count 0 2006.201.21:58:08.90#ibcon#about to read 3, iclass 6, count 0 2006.201.21:58:08.92#ibcon#read 3, iclass 6, count 0 2006.201.21:58:08.92#ibcon#about to read 4, iclass 6, count 0 2006.201.21:58:08.92#ibcon#read 4, iclass 6, count 0 2006.201.21:58:08.92#ibcon#about to read 5, iclass 6, count 0 2006.201.21:58:08.92#ibcon#read 5, iclass 6, count 0 2006.201.21:58:08.92#ibcon#about to read 6, iclass 6, count 0 2006.201.21:58:08.92#ibcon#read 6, iclass 6, count 0 2006.201.21:58:08.92#ibcon#end of sib2, iclass 6, count 0 2006.201.21:58:08.92#ibcon#*mode == 0, iclass 6, count 0 2006.201.21:58:08.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.21:58:08.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.21:58:08.92#ibcon#*before write, iclass 6, count 0 2006.201.21:58:08.92#ibcon#enter sib2, iclass 6, count 0 2006.201.21:58:08.92#ibcon#flushed, iclass 6, count 0 2006.201.21:58:08.92#ibcon#about to write, iclass 6, count 0 2006.201.21:58:08.92#ibcon#wrote, iclass 6, count 0 2006.201.21:58:08.92#ibcon#about to read 3, iclass 6, count 0 2006.201.21:58:08.97#ibcon#read 3, iclass 6, count 0 2006.201.21:58:08.97#ibcon#about to read 4, iclass 6, count 0 2006.201.21:58:08.97#ibcon#read 4, iclass 6, count 0 2006.201.21:58:08.97#ibcon#about to read 5, iclass 6, count 0 2006.201.21:58:08.97#ibcon#read 5, iclass 6, count 0 2006.201.21:58:08.97#ibcon#about to read 6, iclass 6, count 0 2006.201.21:58:08.97#ibcon#read 6, iclass 6, count 0 2006.201.21:58:08.97#ibcon#end of sib2, iclass 6, count 0 2006.201.21:58:08.97#ibcon#*after write, iclass 6, count 0 2006.201.21:58:08.97#ibcon#*before return 0, iclass 6, count 0 2006.201.21:58:08.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:08.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:08.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.21:58:08.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.21:58:08.97$vck44/va=7,5 2006.201.21:58:08.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.21:58:08.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.21:58:08.97#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:08.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:09.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:09.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:09.02#ibcon#enter wrdev, iclass 10, count 2 2006.201.21:58:09.02#ibcon#first serial, iclass 10, count 2 2006.201.21:58:09.02#ibcon#enter sib2, iclass 10, count 2 2006.201.21:58:09.02#ibcon#flushed, iclass 10, count 2 2006.201.21:58:09.02#ibcon#about to write, iclass 10, count 2 2006.201.21:58:09.02#ibcon#wrote, iclass 10, count 2 2006.201.21:58:09.02#ibcon#about to read 3, iclass 10, count 2 2006.201.21:58:09.04#ibcon#read 3, iclass 10, count 2 2006.201.21:58:09.04#ibcon#about to read 4, iclass 10, count 2 2006.201.21:58:09.04#ibcon#read 4, iclass 10, count 2 2006.201.21:58:09.04#ibcon#about to read 5, iclass 10, count 2 2006.201.21:58:09.04#ibcon#read 5, iclass 10, count 2 2006.201.21:58:09.04#ibcon#about to read 6, iclass 10, count 2 2006.201.21:58:09.04#ibcon#read 6, iclass 10, count 2 2006.201.21:58:09.04#ibcon#end of sib2, iclass 10, count 2 2006.201.21:58:09.04#ibcon#*mode == 0, iclass 10, count 2 2006.201.21:58:09.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.21:58:09.04#ibcon#[25=AT07-05\r\n] 2006.201.21:58:09.04#ibcon#*before write, iclass 10, count 2 2006.201.21:58:09.04#ibcon#enter sib2, iclass 10, count 2 2006.201.21:58:09.04#ibcon#flushed, iclass 10, count 2 2006.201.21:58:09.04#ibcon#about to write, iclass 10, count 2 2006.201.21:58:09.04#ibcon#wrote, iclass 10, count 2 2006.201.21:58:09.04#ibcon#about to read 3, iclass 10, count 2 2006.201.21:58:09.07#ibcon#read 3, iclass 10, count 2 2006.201.21:58:09.07#ibcon#about to read 4, iclass 10, count 2 2006.201.21:58:09.07#ibcon#read 4, iclass 10, count 2 2006.201.21:58:09.07#ibcon#about to read 5, iclass 10, count 2 2006.201.21:58:09.07#ibcon#read 5, iclass 10, count 2 2006.201.21:58:09.07#ibcon#about to read 6, iclass 10, count 2 2006.201.21:58:09.07#ibcon#read 6, iclass 10, count 2 2006.201.21:58:09.07#ibcon#end of sib2, iclass 10, count 2 2006.201.21:58:09.07#ibcon#*after write, iclass 10, count 2 2006.201.21:58:09.07#ibcon#*before return 0, iclass 10, count 2 2006.201.21:58:09.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:09.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:09.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.21:58:09.07#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:09.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:09.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:09.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:09.19#ibcon#enter wrdev, iclass 10, count 0 2006.201.21:58:09.19#ibcon#first serial, iclass 10, count 0 2006.201.21:58:09.19#ibcon#enter sib2, iclass 10, count 0 2006.201.21:58:09.19#ibcon#flushed, iclass 10, count 0 2006.201.21:58:09.19#ibcon#about to write, iclass 10, count 0 2006.201.21:58:09.19#ibcon#wrote, iclass 10, count 0 2006.201.21:58:09.19#ibcon#about to read 3, iclass 10, count 0 2006.201.21:58:09.21#ibcon#read 3, iclass 10, count 0 2006.201.21:58:09.21#ibcon#about to read 4, iclass 10, count 0 2006.201.21:58:09.21#ibcon#read 4, iclass 10, count 0 2006.201.21:58:09.21#ibcon#about to read 5, iclass 10, count 0 2006.201.21:58:09.21#ibcon#read 5, iclass 10, count 0 2006.201.21:58:09.21#ibcon#about to read 6, iclass 10, count 0 2006.201.21:58:09.21#ibcon#read 6, iclass 10, count 0 2006.201.21:58:09.21#ibcon#end of sib2, iclass 10, count 0 2006.201.21:58:09.21#ibcon#*mode == 0, iclass 10, count 0 2006.201.21:58:09.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.21:58:09.21#ibcon#[25=USB\r\n] 2006.201.21:58:09.21#ibcon#*before write, iclass 10, count 0 2006.201.21:58:09.21#ibcon#enter sib2, iclass 10, count 0 2006.201.21:58:09.21#ibcon#flushed, iclass 10, count 0 2006.201.21:58:09.21#ibcon#about to write, iclass 10, count 0 2006.201.21:58:09.21#ibcon#wrote, iclass 10, count 0 2006.201.21:58:09.21#ibcon#about to read 3, iclass 10, count 0 2006.201.21:58:09.24#ibcon#read 3, iclass 10, count 0 2006.201.21:58:09.24#ibcon#about to read 4, iclass 10, count 0 2006.201.21:58:09.24#ibcon#read 4, iclass 10, count 0 2006.201.21:58:09.24#ibcon#about to read 5, iclass 10, count 0 2006.201.21:58:09.24#ibcon#read 5, iclass 10, count 0 2006.201.21:58:09.24#ibcon#about to read 6, iclass 10, count 0 2006.201.21:58:09.24#ibcon#read 6, iclass 10, count 0 2006.201.21:58:09.24#ibcon#end of sib2, iclass 10, count 0 2006.201.21:58:09.24#ibcon#*after write, iclass 10, count 0 2006.201.21:58:09.24#ibcon#*before return 0, iclass 10, count 0 2006.201.21:58:09.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:09.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:09.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.21:58:09.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.21:58:09.24$vck44/valo=8,884.99 2006.201.21:58:09.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.21:58:09.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.21:58:09.24#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:09.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:09.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:09.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:09.24#ibcon#enter wrdev, iclass 12, count 0 2006.201.21:58:09.24#ibcon#first serial, iclass 12, count 0 2006.201.21:58:09.24#ibcon#enter sib2, iclass 12, count 0 2006.201.21:58:09.24#ibcon#flushed, iclass 12, count 0 2006.201.21:58:09.24#ibcon#about to write, iclass 12, count 0 2006.201.21:58:09.24#ibcon#wrote, iclass 12, count 0 2006.201.21:58:09.24#ibcon#about to read 3, iclass 12, count 0 2006.201.21:58:09.26#ibcon#read 3, iclass 12, count 0 2006.201.21:58:09.26#ibcon#about to read 4, iclass 12, count 0 2006.201.21:58:09.26#ibcon#read 4, iclass 12, count 0 2006.201.21:58:09.26#ibcon#about to read 5, iclass 12, count 0 2006.201.21:58:09.26#ibcon#read 5, iclass 12, count 0 2006.201.21:58:09.26#ibcon#about to read 6, iclass 12, count 0 2006.201.21:58:09.26#ibcon#read 6, iclass 12, count 0 2006.201.21:58:09.26#ibcon#end of sib2, iclass 12, count 0 2006.201.21:58:09.26#ibcon#*mode == 0, iclass 12, count 0 2006.201.21:58:09.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.21:58:09.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.21:58:09.26#ibcon#*before write, iclass 12, count 0 2006.201.21:58:09.26#ibcon#enter sib2, iclass 12, count 0 2006.201.21:58:09.26#ibcon#flushed, iclass 12, count 0 2006.201.21:58:09.26#ibcon#about to write, iclass 12, count 0 2006.201.21:58:09.26#ibcon#wrote, iclass 12, count 0 2006.201.21:58:09.26#ibcon#about to read 3, iclass 12, count 0 2006.201.21:58:09.30#ibcon#read 3, iclass 12, count 0 2006.201.21:58:09.30#ibcon#about to read 4, iclass 12, count 0 2006.201.21:58:09.30#ibcon#read 4, iclass 12, count 0 2006.201.21:58:09.30#ibcon#about to read 5, iclass 12, count 0 2006.201.21:58:09.30#ibcon#read 5, iclass 12, count 0 2006.201.21:58:09.30#ibcon#about to read 6, iclass 12, count 0 2006.201.21:58:09.30#ibcon#read 6, iclass 12, count 0 2006.201.21:58:09.30#ibcon#end of sib2, iclass 12, count 0 2006.201.21:58:09.30#ibcon#*after write, iclass 12, count 0 2006.201.21:58:09.30#ibcon#*before return 0, iclass 12, count 0 2006.201.21:58:09.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:09.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:09.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.21:58:09.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.21:58:09.30$vck44/va=8,4 2006.201.21:58:09.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.21:58:09.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.21:58:09.30#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:09.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:58:09.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:58:09.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:58:09.36#ibcon#enter wrdev, iclass 14, count 2 2006.201.21:58:09.36#ibcon#first serial, iclass 14, count 2 2006.201.21:58:09.36#ibcon#enter sib2, iclass 14, count 2 2006.201.21:58:09.36#ibcon#flushed, iclass 14, count 2 2006.201.21:58:09.36#ibcon#about to write, iclass 14, count 2 2006.201.21:58:09.36#ibcon#wrote, iclass 14, count 2 2006.201.21:58:09.36#ibcon#about to read 3, iclass 14, count 2 2006.201.21:58:09.38#ibcon#read 3, iclass 14, count 2 2006.201.21:58:09.38#ibcon#about to read 4, iclass 14, count 2 2006.201.21:58:09.38#ibcon#read 4, iclass 14, count 2 2006.201.21:58:09.38#ibcon#about to read 5, iclass 14, count 2 2006.201.21:58:09.38#ibcon#read 5, iclass 14, count 2 2006.201.21:58:09.38#ibcon#about to read 6, iclass 14, count 2 2006.201.21:58:09.38#ibcon#read 6, iclass 14, count 2 2006.201.21:58:09.38#ibcon#end of sib2, iclass 14, count 2 2006.201.21:58:09.38#ibcon#*mode == 0, iclass 14, count 2 2006.201.21:58:09.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.21:58:09.38#ibcon#[25=AT08-04\r\n] 2006.201.21:58:09.38#ibcon#*before write, iclass 14, count 2 2006.201.21:58:09.38#ibcon#enter sib2, iclass 14, count 2 2006.201.21:58:09.38#ibcon#flushed, iclass 14, count 2 2006.201.21:58:09.38#ibcon#about to write, iclass 14, count 2 2006.201.21:58:09.38#ibcon#wrote, iclass 14, count 2 2006.201.21:58:09.38#ibcon#about to read 3, iclass 14, count 2 2006.201.21:58:09.41#ibcon#read 3, iclass 14, count 2 2006.201.21:58:09.41#ibcon#about to read 4, iclass 14, count 2 2006.201.21:58:09.41#ibcon#read 4, iclass 14, count 2 2006.201.21:58:09.41#ibcon#about to read 5, iclass 14, count 2 2006.201.21:58:09.41#ibcon#read 5, iclass 14, count 2 2006.201.21:58:09.41#ibcon#about to read 6, iclass 14, count 2 2006.201.21:58:09.41#ibcon#read 6, iclass 14, count 2 2006.201.21:58:09.41#ibcon#end of sib2, iclass 14, count 2 2006.201.21:58:09.41#ibcon#*after write, iclass 14, count 2 2006.201.21:58:09.41#ibcon#*before return 0, iclass 14, count 2 2006.201.21:58:09.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:58:09.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.21:58:09.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.21:58:09.41#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:09.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:58:09.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:58:09.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:58:09.53#ibcon#enter wrdev, iclass 14, count 0 2006.201.21:58:09.53#ibcon#first serial, iclass 14, count 0 2006.201.21:58:09.53#ibcon#enter sib2, iclass 14, count 0 2006.201.21:58:09.53#ibcon#flushed, iclass 14, count 0 2006.201.21:58:09.53#ibcon#about to write, iclass 14, count 0 2006.201.21:58:09.53#ibcon#wrote, iclass 14, count 0 2006.201.21:58:09.53#ibcon#about to read 3, iclass 14, count 0 2006.201.21:58:09.55#ibcon#read 3, iclass 14, count 0 2006.201.21:58:09.55#ibcon#about to read 4, iclass 14, count 0 2006.201.21:58:09.55#ibcon#read 4, iclass 14, count 0 2006.201.21:58:09.55#ibcon#about to read 5, iclass 14, count 0 2006.201.21:58:09.55#ibcon#read 5, iclass 14, count 0 2006.201.21:58:09.55#ibcon#about to read 6, iclass 14, count 0 2006.201.21:58:09.55#ibcon#read 6, iclass 14, count 0 2006.201.21:58:09.55#ibcon#end of sib2, iclass 14, count 0 2006.201.21:58:09.55#ibcon#*mode == 0, iclass 14, count 0 2006.201.21:58:09.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.21:58:09.55#ibcon#[25=USB\r\n] 2006.201.21:58:09.55#ibcon#*before write, iclass 14, count 0 2006.201.21:58:09.55#ibcon#enter sib2, iclass 14, count 0 2006.201.21:58:09.55#ibcon#flushed, iclass 14, count 0 2006.201.21:58:09.55#ibcon#about to write, iclass 14, count 0 2006.201.21:58:09.55#ibcon#wrote, iclass 14, count 0 2006.201.21:58:09.55#ibcon#about to read 3, iclass 14, count 0 2006.201.21:58:09.58#ibcon#read 3, iclass 14, count 0 2006.201.21:58:09.58#ibcon#about to read 4, iclass 14, count 0 2006.201.21:58:09.58#ibcon#read 4, iclass 14, count 0 2006.201.21:58:09.58#ibcon#about to read 5, iclass 14, count 0 2006.201.21:58:09.58#ibcon#read 5, iclass 14, count 0 2006.201.21:58:09.58#ibcon#about to read 6, iclass 14, count 0 2006.201.21:58:09.58#ibcon#read 6, iclass 14, count 0 2006.201.21:58:09.58#ibcon#end of sib2, iclass 14, count 0 2006.201.21:58:09.58#ibcon#*after write, iclass 14, count 0 2006.201.21:58:09.58#ibcon#*before return 0, iclass 14, count 0 2006.201.21:58:09.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:58:09.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.21:58:09.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.21:58:09.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.21:58:09.58$vck44/vblo=1,629.99 2006.201.21:58:09.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.21:58:09.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.21:58:09.58#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:09.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:58:09.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:58:09.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:58:09.58#ibcon#enter wrdev, iclass 16, count 0 2006.201.21:58:09.58#ibcon#first serial, iclass 16, count 0 2006.201.21:58:09.58#ibcon#enter sib2, iclass 16, count 0 2006.201.21:58:09.58#ibcon#flushed, iclass 16, count 0 2006.201.21:58:09.58#ibcon#about to write, iclass 16, count 0 2006.201.21:58:09.58#ibcon#wrote, iclass 16, count 0 2006.201.21:58:09.58#ibcon#about to read 3, iclass 16, count 0 2006.201.21:58:09.60#ibcon#read 3, iclass 16, count 0 2006.201.21:58:09.60#ibcon#about to read 4, iclass 16, count 0 2006.201.21:58:09.60#ibcon#read 4, iclass 16, count 0 2006.201.21:58:09.60#ibcon#about to read 5, iclass 16, count 0 2006.201.21:58:09.60#ibcon#read 5, iclass 16, count 0 2006.201.21:58:09.60#ibcon#about to read 6, iclass 16, count 0 2006.201.21:58:09.60#ibcon#read 6, iclass 16, count 0 2006.201.21:58:09.60#ibcon#end of sib2, iclass 16, count 0 2006.201.21:58:09.60#ibcon#*mode == 0, iclass 16, count 0 2006.201.21:58:09.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.21:58:09.60#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.21:58:09.60#ibcon#*before write, iclass 16, count 0 2006.201.21:58:09.60#ibcon#enter sib2, iclass 16, count 0 2006.201.21:58:09.60#ibcon#flushed, iclass 16, count 0 2006.201.21:58:09.60#ibcon#about to write, iclass 16, count 0 2006.201.21:58:09.60#ibcon#wrote, iclass 16, count 0 2006.201.21:58:09.60#ibcon#about to read 3, iclass 16, count 0 2006.201.21:58:09.65#ibcon#read 3, iclass 16, count 0 2006.201.21:58:09.65#ibcon#about to read 4, iclass 16, count 0 2006.201.21:58:09.65#ibcon#read 4, iclass 16, count 0 2006.201.21:58:09.65#ibcon#about to read 5, iclass 16, count 0 2006.201.21:58:09.65#ibcon#read 5, iclass 16, count 0 2006.201.21:58:09.65#ibcon#about to read 6, iclass 16, count 0 2006.201.21:58:09.65#ibcon#read 6, iclass 16, count 0 2006.201.21:58:09.65#ibcon#end of sib2, iclass 16, count 0 2006.201.21:58:09.65#ibcon#*after write, iclass 16, count 0 2006.201.21:58:09.65#ibcon#*before return 0, iclass 16, count 0 2006.201.21:58:09.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:58:09.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.21:58:09.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.21:58:09.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.21:58:09.65$vck44/vb=1,4 2006.201.21:58:09.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.21:58:09.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.21:58:09.65#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:09.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:58:09.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:58:09.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:58:09.65#ibcon#enter wrdev, iclass 18, count 2 2006.201.21:58:09.65#ibcon#first serial, iclass 18, count 2 2006.201.21:58:09.65#ibcon#enter sib2, iclass 18, count 2 2006.201.21:58:09.65#ibcon#flushed, iclass 18, count 2 2006.201.21:58:09.65#ibcon#about to write, iclass 18, count 2 2006.201.21:58:09.65#ibcon#wrote, iclass 18, count 2 2006.201.21:58:09.65#ibcon#about to read 3, iclass 18, count 2 2006.201.21:58:09.67#ibcon#read 3, iclass 18, count 2 2006.201.21:58:09.67#ibcon#about to read 4, iclass 18, count 2 2006.201.21:58:09.67#ibcon#read 4, iclass 18, count 2 2006.201.21:58:09.67#ibcon#about to read 5, iclass 18, count 2 2006.201.21:58:09.67#ibcon#read 5, iclass 18, count 2 2006.201.21:58:09.67#ibcon#about to read 6, iclass 18, count 2 2006.201.21:58:09.67#ibcon#read 6, iclass 18, count 2 2006.201.21:58:09.67#ibcon#end of sib2, iclass 18, count 2 2006.201.21:58:09.67#ibcon#*mode == 0, iclass 18, count 2 2006.201.21:58:09.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.21:58:09.67#ibcon#[27=AT01-04\r\n] 2006.201.21:58:09.67#ibcon#*before write, iclass 18, count 2 2006.201.21:58:09.67#ibcon#enter sib2, iclass 18, count 2 2006.201.21:58:09.67#ibcon#flushed, iclass 18, count 2 2006.201.21:58:09.67#ibcon#about to write, iclass 18, count 2 2006.201.21:58:09.67#ibcon#wrote, iclass 18, count 2 2006.201.21:58:09.67#ibcon#about to read 3, iclass 18, count 2 2006.201.21:58:09.70#ibcon#read 3, iclass 18, count 2 2006.201.21:58:09.70#ibcon#about to read 4, iclass 18, count 2 2006.201.21:58:09.70#ibcon#read 4, iclass 18, count 2 2006.201.21:58:09.70#ibcon#about to read 5, iclass 18, count 2 2006.201.21:58:09.70#ibcon#read 5, iclass 18, count 2 2006.201.21:58:09.70#ibcon#about to read 6, iclass 18, count 2 2006.201.21:58:09.70#ibcon#read 6, iclass 18, count 2 2006.201.21:58:09.70#ibcon#end of sib2, iclass 18, count 2 2006.201.21:58:09.70#ibcon#*after write, iclass 18, count 2 2006.201.21:58:09.70#ibcon#*before return 0, iclass 18, count 2 2006.201.21:58:09.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:58:09.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.21:58:09.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.21:58:09.70#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:09.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:58:09.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:58:09.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:58:09.82#ibcon#enter wrdev, iclass 18, count 0 2006.201.21:58:09.82#ibcon#first serial, iclass 18, count 0 2006.201.21:58:09.82#ibcon#enter sib2, iclass 18, count 0 2006.201.21:58:09.82#ibcon#flushed, iclass 18, count 0 2006.201.21:58:09.82#ibcon#about to write, iclass 18, count 0 2006.201.21:58:09.82#ibcon#wrote, iclass 18, count 0 2006.201.21:58:09.82#ibcon#about to read 3, iclass 18, count 0 2006.201.21:58:09.84#ibcon#read 3, iclass 18, count 0 2006.201.21:58:09.84#ibcon#about to read 4, iclass 18, count 0 2006.201.21:58:09.84#ibcon#read 4, iclass 18, count 0 2006.201.21:58:09.84#ibcon#about to read 5, iclass 18, count 0 2006.201.21:58:09.84#ibcon#read 5, iclass 18, count 0 2006.201.21:58:09.84#ibcon#about to read 6, iclass 18, count 0 2006.201.21:58:09.84#ibcon#read 6, iclass 18, count 0 2006.201.21:58:09.84#ibcon#end of sib2, iclass 18, count 0 2006.201.21:58:09.84#ibcon#*mode == 0, iclass 18, count 0 2006.201.21:58:09.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.21:58:09.84#ibcon#[27=USB\r\n] 2006.201.21:58:09.84#ibcon#*before write, iclass 18, count 0 2006.201.21:58:09.84#ibcon#enter sib2, iclass 18, count 0 2006.201.21:58:09.84#ibcon#flushed, iclass 18, count 0 2006.201.21:58:09.84#ibcon#about to write, iclass 18, count 0 2006.201.21:58:09.84#ibcon#wrote, iclass 18, count 0 2006.201.21:58:09.84#ibcon#about to read 3, iclass 18, count 0 2006.201.21:58:09.87#ibcon#read 3, iclass 18, count 0 2006.201.21:58:09.87#ibcon#about to read 4, iclass 18, count 0 2006.201.21:58:09.87#ibcon#read 4, iclass 18, count 0 2006.201.21:58:09.87#ibcon#about to read 5, iclass 18, count 0 2006.201.21:58:09.87#ibcon#read 5, iclass 18, count 0 2006.201.21:58:09.87#ibcon#about to read 6, iclass 18, count 0 2006.201.21:58:09.87#ibcon#read 6, iclass 18, count 0 2006.201.21:58:09.87#ibcon#end of sib2, iclass 18, count 0 2006.201.21:58:09.87#ibcon#*after write, iclass 18, count 0 2006.201.21:58:09.87#ibcon#*before return 0, iclass 18, count 0 2006.201.21:58:09.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:58:09.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.21:58:09.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.21:58:09.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.21:58:09.87$vck44/vblo=2,634.99 2006.201.21:58:09.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.21:58:09.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.21:58:09.87#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:09.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:09.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:09.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:09.87#ibcon#enter wrdev, iclass 20, count 0 2006.201.21:58:09.87#ibcon#first serial, iclass 20, count 0 2006.201.21:58:09.87#ibcon#enter sib2, iclass 20, count 0 2006.201.21:58:09.87#ibcon#flushed, iclass 20, count 0 2006.201.21:58:09.87#ibcon#about to write, iclass 20, count 0 2006.201.21:58:09.87#ibcon#wrote, iclass 20, count 0 2006.201.21:58:09.87#ibcon#about to read 3, iclass 20, count 0 2006.201.21:58:09.89#ibcon#read 3, iclass 20, count 0 2006.201.21:58:09.89#ibcon#about to read 4, iclass 20, count 0 2006.201.21:58:09.89#ibcon#read 4, iclass 20, count 0 2006.201.21:58:09.89#ibcon#about to read 5, iclass 20, count 0 2006.201.21:58:09.89#ibcon#read 5, iclass 20, count 0 2006.201.21:58:09.89#ibcon#about to read 6, iclass 20, count 0 2006.201.21:58:09.89#ibcon#read 6, iclass 20, count 0 2006.201.21:58:09.89#ibcon#end of sib2, iclass 20, count 0 2006.201.21:58:09.89#ibcon#*mode == 0, iclass 20, count 0 2006.201.21:58:09.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.21:58:09.89#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.21:58:09.89#ibcon#*before write, iclass 20, count 0 2006.201.21:58:09.89#ibcon#enter sib2, iclass 20, count 0 2006.201.21:58:09.89#ibcon#flushed, iclass 20, count 0 2006.201.21:58:09.89#ibcon#about to write, iclass 20, count 0 2006.201.21:58:09.89#ibcon#wrote, iclass 20, count 0 2006.201.21:58:09.89#ibcon#about to read 3, iclass 20, count 0 2006.201.21:58:09.93#ibcon#read 3, iclass 20, count 0 2006.201.21:58:09.93#ibcon#about to read 4, iclass 20, count 0 2006.201.21:58:09.93#ibcon#read 4, iclass 20, count 0 2006.201.21:58:09.93#ibcon#about to read 5, iclass 20, count 0 2006.201.21:58:09.93#ibcon#read 5, iclass 20, count 0 2006.201.21:58:09.93#ibcon#about to read 6, iclass 20, count 0 2006.201.21:58:09.93#ibcon#read 6, iclass 20, count 0 2006.201.21:58:09.93#ibcon#end of sib2, iclass 20, count 0 2006.201.21:58:09.93#ibcon#*after write, iclass 20, count 0 2006.201.21:58:09.93#ibcon#*before return 0, iclass 20, count 0 2006.201.21:58:09.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:09.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.21:58:09.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.21:58:09.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.21:58:09.93$vck44/vb=2,5 2006.201.21:58:09.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.21:58:09.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.21:58:09.93#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:09.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:09.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:09.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:09.99#ibcon#enter wrdev, iclass 22, count 2 2006.201.21:58:09.99#ibcon#first serial, iclass 22, count 2 2006.201.21:58:09.99#ibcon#enter sib2, iclass 22, count 2 2006.201.21:58:09.99#ibcon#flushed, iclass 22, count 2 2006.201.21:58:09.99#ibcon#about to write, iclass 22, count 2 2006.201.21:58:09.99#ibcon#wrote, iclass 22, count 2 2006.201.21:58:09.99#ibcon#about to read 3, iclass 22, count 2 2006.201.21:58:10.01#ibcon#read 3, iclass 22, count 2 2006.201.21:58:10.01#ibcon#about to read 4, iclass 22, count 2 2006.201.21:58:10.01#ibcon#read 4, iclass 22, count 2 2006.201.21:58:10.01#ibcon#about to read 5, iclass 22, count 2 2006.201.21:58:10.01#ibcon#read 5, iclass 22, count 2 2006.201.21:58:10.01#ibcon#about to read 6, iclass 22, count 2 2006.201.21:58:10.01#ibcon#read 6, iclass 22, count 2 2006.201.21:58:10.01#ibcon#end of sib2, iclass 22, count 2 2006.201.21:58:10.01#ibcon#*mode == 0, iclass 22, count 2 2006.201.21:58:10.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.21:58:10.01#ibcon#[27=AT02-05\r\n] 2006.201.21:58:10.01#ibcon#*before write, iclass 22, count 2 2006.201.21:58:10.01#ibcon#enter sib2, iclass 22, count 2 2006.201.21:58:10.01#ibcon#flushed, iclass 22, count 2 2006.201.21:58:10.01#ibcon#about to write, iclass 22, count 2 2006.201.21:58:10.01#ibcon#wrote, iclass 22, count 2 2006.201.21:58:10.01#ibcon#about to read 3, iclass 22, count 2 2006.201.21:58:10.04#ibcon#read 3, iclass 22, count 2 2006.201.21:58:10.04#ibcon#about to read 4, iclass 22, count 2 2006.201.21:58:10.04#ibcon#read 4, iclass 22, count 2 2006.201.21:58:10.04#ibcon#about to read 5, iclass 22, count 2 2006.201.21:58:10.04#ibcon#read 5, iclass 22, count 2 2006.201.21:58:10.04#ibcon#about to read 6, iclass 22, count 2 2006.201.21:58:10.04#ibcon#read 6, iclass 22, count 2 2006.201.21:58:10.04#ibcon#end of sib2, iclass 22, count 2 2006.201.21:58:10.04#ibcon#*after write, iclass 22, count 2 2006.201.21:58:10.04#ibcon#*before return 0, iclass 22, count 2 2006.201.21:58:10.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:10.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.21:58:10.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.21:58:10.04#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:10.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:10.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:10.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:10.16#ibcon#enter wrdev, iclass 22, count 0 2006.201.21:58:10.16#ibcon#first serial, iclass 22, count 0 2006.201.21:58:10.16#ibcon#enter sib2, iclass 22, count 0 2006.201.21:58:10.16#ibcon#flushed, iclass 22, count 0 2006.201.21:58:10.16#ibcon#about to write, iclass 22, count 0 2006.201.21:58:10.16#ibcon#wrote, iclass 22, count 0 2006.201.21:58:10.16#ibcon#about to read 3, iclass 22, count 0 2006.201.21:58:10.18#ibcon#read 3, iclass 22, count 0 2006.201.21:58:10.18#ibcon#about to read 4, iclass 22, count 0 2006.201.21:58:10.18#ibcon#read 4, iclass 22, count 0 2006.201.21:58:10.18#ibcon#about to read 5, iclass 22, count 0 2006.201.21:58:10.18#ibcon#read 5, iclass 22, count 0 2006.201.21:58:10.18#ibcon#about to read 6, iclass 22, count 0 2006.201.21:58:10.18#ibcon#read 6, iclass 22, count 0 2006.201.21:58:10.18#ibcon#end of sib2, iclass 22, count 0 2006.201.21:58:10.18#ibcon#*mode == 0, iclass 22, count 0 2006.201.21:58:10.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.21:58:10.18#ibcon#[27=USB\r\n] 2006.201.21:58:10.18#ibcon#*before write, iclass 22, count 0 2006.201.21:58:10.18#ibcon#enter sib2, iclass 22, count 0 2006.201.21:58:10.18#ibcon#flushed, iclass 22, count 0 2006.201.21:58:10.18#ibcon#about to write, iclass 22, count 0 2006.201.21:58:10.18#ibcon#wrote, iclass 22, count 0 2006.201.21:58:10.18#ibcon#about to read 3, iclass 22, count 0 2006.201.21:58:10.21#ibcon#read 3, iclass 22, count 0 2006.201.21:58:10.21#ibcon#about to read 4, iclass 22, count 0 2006.201.21:58:10.21#ibcon#read 4, iclass 22, count 0 2006.201.21:58:10.21#ibcon#about to read 5, iclass 22, count 0 2006.201.21:58:10.21#ibcon#read 5, iclass 22, count 0 2006.201.21:58:10.21#ibcon#about to read 6, iclass 22, count 0 2006.201.21:58:10.21#ibcon#read 6, iclass 22, count 0 2006.201.21:58:10.21#ibcon#end of sib2, iclass 22, count 0 2006.201.21:58:10.21#ibcon#*after write, iclass 22, count 0 2006.201.21:58:10.21#ibcon#*before return 0, iclass 22, count 0 2006.201.21:58:10.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:10.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.21:58:10.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.21:58:10.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.21:58:10.21$vck44/vblo=3,649.99 2006.201.21:58:10.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.21:58:10.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.21:58:10.21#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:10.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:10.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:10.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:10.21#ibcon#enter wrdev, iclass 24, count 0 2006.201.21:58:10.21#ibcon#first serial, iclass 24, count 0 2006.201.21:58:10.21#ibcon#enter sib2, iclass 24, count 0 2006.201.21:58:10.21#ibcon#flushed, iclass 24, count 0 2006.201.21:58:10.21#ibcon#about to write, iclass 24, count 0 2006.201.21:58:10.21#ibcon#wrote, iclass 24, count 0 2006.201.21:58:10.21#ibcon#about to read 3, iclass 24, count 0 2006.201.21:58:10.23#ibcon#read 3, iclass 24, count 0 2006.201.21:58:10.23#ibcon#about to read 4, iclass 24, count 0 2006.201.21:58:10.23#ibcon#read 4, iclass 24, count 0 2006.201.21:58:10.23#ibcon#about to read 5, iclass 24, count 0 2006.201.21:58:10.23#ibcon#read 5, iclass 24, count 0 2006.201.21:58:10.23#ibcon#about to read 6, iclass 24, count 0 2006.201.21:58:10.23#ibcon#read 6, iclass 24, count 0 2006.201.21:58:10.23#ibcon#end of sib2, iclass 24, count 0 2006.201.21:58:10.23#ibcon#*mode == 0, iclass 24, count 0 2006.201.21:58:10.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.21:58:10.23#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.21:58:10.23#ibcon#*before write, iclass 24, count 0 2006.201.21:58:10.23#ibcon#enter sib2, iclass 24, count 0 2006.201.21:58:10.23#ibcon#flushed, iclass 24, count 0 2006.201.21:58:10.23#ibcon#about to write, iclass 24, count 0 2006.201.21:58:10.23#ibcon#wrote, iclass 24, count 0 2006.201.21:58:10.23#ibcon#about to read 3, iclass 24, count 0 2006.201.21:58:10.27#ibcon#read 3, iclass 24, count 0 2006.201.21:58:10.27#ibcon#about to read 4, iclass 24, count 0 2006.201.21:58:10.27#ibcon#read 4, iclass 24, count 0 2006.201.21:58:10.27#ibcon#about to read 5, iclass 24, count 0 2006.201.21:58:10.27#ibcon#read 5, iclass 24, count 0 2006.201.21:58:10.27#ibcon#about to read 6, iclass 24, count 0 2006.201.21:58:10.27#ibcon#read 6, iclass 24, count 0 2006.201.21:58:10.27#ibcon#end of sib2, iclass 24, count 0 2006.201.21:58:10.27#ibcon#*after write, iclass 24, count 0 2006.201.21:58:10.27#ibcon#*before return 0, iclass 24, count 0 2006.201.21:58:10.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:10.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.21:58:10.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.21:58:10.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.21:58:10.27$vck44/vb=3,4 2006.201.21:58:10.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.21:58:10.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.21:58:10.27#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:10.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:10.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:10.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:10.33#ibcon#enter wrdev, iclass 26, count 2 2006.201.21:58:10.33#ibcon#first serial, iclass 26, count 2 2006.201.21:58:10.33#ibcon#enter sib2, iclass 26, count 2 2006.201.21:58:10.33#ibcon#flushed, iclass 26, count 2 2006.201.21:58:10.33#ibcon#about to write, iclass 26, count 2 2006.201.21:58:10.33#ibcon#wrote, iclass 26, count 2 2006.201.21:58:10.33#ibcon#about to read 3, iclass 26, count 2 2006.201.21:58:10.35#ibcon#read 3, iclass 26, count 2 2006.201.21:58:10.35#ibcon#about to read 4, iclass 26, count 2 2006.201.21:58:10.35#ibcon#read 4, iclass 26, count 2 2006.201.21:58:10.35#ibcon#about to read 5, iclass 26, count 2 2006.201.21:58:10.35#ibcon#read 5, iclass 26, count 2 2006.201.21:58:10.35#ibcon#about to read 6, iclass 26, count 2 2006.201.21:58:10.35#ibcon#read 6, iclass 26, count 2 2006.201.21:58:10.35#ibcon#end of sib2, iclass 26, count 2 2006.201.21:58:10.35#ibcon#*mode == 0, iclass 26, count 2 2006.201.21:58:10.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.21:58:10.35#ibcon#[27=AT03-04\r\n] 2006.201.21:58:10.35#ibcon#*before write, iclass 26, count 2 2006.201.21:58:10.35#ibcon#enter sib2, iclass 26, count 2 2006.201.21:58:10.35#ibcon#flushed, iclass 26, count 2 2006.201.21:58:10.35#ibcon#about to write, iclass 26, count 2 2006.201.21:58:10.35#ibcon#wrote, iclass 26, count 2 2006.201.21:58:10.35#ibcon#about to read 3, iclass 26, count 2 2006.201.21:58:10.38#ibcon#read 3, iclass 26, count 2 2006.201.21:58:10.38#ibcon#about to read 4, iclass 26, count 2 2006.201.21:58:10.38#ibcon#read 4, iclass 26, count 2 2006.201.21:58:10.38#ibcon#about to read 5, iclass 26, count 2 2006.201.21:58:10.38#ibcon#read 5, iclass 26, count 2 2006.201.21:58:10.38#ibcon#about to read 6, iclass 26, count 2 2006.201.21:58:10.38#ibcon#read 6, iclass 26, count 2 2006.201.21:58:10.38#ibcon#end of sib2, iclass 26, count 2 2006.201.21:58:10.38#ibcon#*after write, iclass 26, count 2 2006.201.21:58:10.38#ibcon#*before return 0, iclass 26, count 2 2006.201.21:58:10.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:10.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.21:58:10.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.21:58:10.38#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:10.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:10.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:10.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:10.50#ibcon#enter wrdev, iclass 26, count 0 2006.201.21:58:10.50#ibcon#first serial, iclass 26, count 0 2006.201.21:58:10.50#ibcon#enter sib2, iclass 26, count 0 2006.201.21:58:10.50#ibcon#flushed, iclass 26, count 0 2006.201.21:58:10.50#ibcon#about to write, iclass 26, count 0 2006.201.21:58:10.50#ibcon#wrote, iclass 26, count 0 2006.201.21:58:10.50#ibcon#about to read 3, iclass 26, count 0 2006.201.21:58:10.52#ibcon#read 3, iclass 26, count 0 2006.201.21:58:10.52#ibcon#about to read 4, iclass 26, count 0 2006.201.21:58:10.52#ibcon#read 4, iclass 26, count 0 2006.201.21:58:10.52#ibcon#about to read 5, iclass 26, count 0 2006.201.21:58:10.52#ibcon#read 5, iclass 26, count 0 2006.201.21:58:10.52#ibcon#about to read 6, iclass 26, count 0 2006.201.21:58:10.52#ibcon#read 6, iclass 26, count 0 2006.201.21:58:10.52#ibcon#end of sib2, iclass 26, count 0 2006.201.21:58:10.52#ibcon#*mode == 0, iclass 26, count 0 2006.201.21:58:10.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.21:58:10.52#ibcon#[27=USB\r\n] 2006.201.21:58:10.52#ibcon#*before write, iclass 26, count 0 2006.201.21:58:10.52#ibcon#enter sib2, iclass 26, count 0 2006.201.21:58:10.52#ibcon#flushed, iclass 26, count 0 2006.201.21:58:10.52#ibcon#about to write, iclass 26, count 0 2006.201.21:58:10.52#ibcon#wrote, iclass 26, count 0 2006.201.21:58:10.52#ibcon#about to read 3, iclass 26, count 0 2006.201.21:58:10.55#ibcon#read 3, iclass 26, count 0 2006.201.21:58:10.55#ibcon#about to read 4, iclass 26, count 0 2006.201.21:58:10.55#ibcon#read 4, iclass 26, count 0 2006.201.21:58:10.55#ibcon#about to read 5, iclass 26, count 0 2006.201.21:58:10.55#ibcon#read 5, iclass 26, count 0 2006.201.21:58:10.55#ibcon#about to read 6, iclass 26, count 0 2006.201.21:58:10.55#ibcon#read 6, iclass 26, count 0 2006.201.21:58:10.55#ibcon#end of sib2, iclass 26, count 0 2006.201.21:58:10.55#ibcon#*after write, iclass 26, count 0 2006.201.21:58:10.55#ibcon#*before return 0, iclass 26, count 0 2006.201.21:58:10.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:10.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.21:58:10.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.21:58:10.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.21:58:10.55$vck44/vblo=4,679.99 2006.201.21:58:10.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.21:58:10.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.21:58:10.55#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:10.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:10.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:10.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:10.55#ibcon#enter wrdev, iclass 28, count 0 2006.201.21:58:10.55#ibcon#first serial, iclass 28, count 0 2006.201.21:58:10.55#ibcon#enter sib2, iclass 28, count 0 2006.201.21:58:10.55#ibcon#flushed, iclass 28, count 0 2006.201.21:58:10.55#ibcon#about to write, iclass 28, count 0 2006.201.21:58:10.55#ibcon#wrote, iclass 28, count 0 2006.201.21:58:10.55#ibcon#about to read 3, iclass 28, count 0 2006.201.21:58:10.57#ibcon#read 3, iclass 28, count 0 2006.201.21:58:10.57#ibcon#about to read 4, iclass 28, count 0 2006.201.21:58:10.57#ibcon#read 4, iclass 28, count 0 2006.201.21:58:10.57#ibcon#about to read 5, iclass 28, count 0 2006.201.21:58:10.57#ibcon#read 5, iclass 28, count 0 2006.201.21:58:10.57#ibcon#about to read 6, iclass 28, count 0 2006.201.21:58:10.57#ibcon#read 6, iclass 28, count 0 2006.201.21:58:10.57#ibcon#end of sib2, iclass 28, count 0 2006.201.21:58:10.57#ibcon#*mode == 0, iclass 28, count 0 2006.201.21:58:10.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.21:58:10.57#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.21:58:10.57#ibcon#*before write, iclass 28, count 0 2006.201.21:58:10.57#ibcon#enter sib2, iclass 28, count 0 2006.201.21:58:10.57#ibcon#flushed, iclass 28, count 0 2006.201.21:58:10.57#ibcon#about to write, iclass 28, count 0 2006.201.21:58:10.57#ibcon#wrote, iclass 28, count 0 2006.201.21:58:10.57#ibcon#about to read 3, iclass 28, count 0 2006.201.21:58:10.62#ibcon#read 3, iclass 28, count 0 2006.201.21:58:10.62#ibcon#about to read 4, iclass 28, count 0 2006.201.21:58:10.62#ibcon#read 4, iclass 28, count 0 2006.201.21:58:10.62#ibcon#about to read 5, iclass 28, count 0 2006.201.21:58:10.62#ibcon#read 5, iclass 28, count 0 2006.201.21:58:10.62#ibcon#about to read 6, iclass 28, count 0 2006.201.21:58:10.62#ibcon#read 6, iclass 28, count 0 2006.201.21:58:10.62#ibcon#end of sib2, iclass 28, count 0 2006.201.21:58:10.62#ibcon#*after write, iclass 28, count 0 2006.201.21:58:10.62#ibcon#*before return 0, iclass 28, count 0 2006.201.21:58:10.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:10.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.21:58:10.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.21:58:10.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.21:58:10.62$vck44/vb=4,5 2006.201.21:58:10.62#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.21:58:10.62#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.21:58:10.62#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:10.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:10.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:10.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:10.67#ibcon#enter wrdev, iclass 30, count 2 2006.201.21:58:10.67#ibcon#first serial, iclass 30, count 2 2006.201.21:58:10.67#ibcon#enter sib2, iclass 30, count 2 2006.201.21:58:10.67#ibcon#flushed, iclass 30, count 2 2006.201.21:58:10.67#ibcon#about to write, iclass 30, count 2 2006.201.21:58:10.67#ibcon#wrote, iclass 30, count 2 2006.201.21:58:10.67#ibcon#about to read 3, iclass 30, count 2 2006.201.21:58:10.69#ibcon#read 3, iclass 30, count 2 2006.201.21:58:10.69#ibcon#about to read 4, iclass 30, count 2 2006.201.21:58:10.69#ibcon#read 4, iclass 30, count 2 2006.201.21:58:10.69#ibcon#about to read 5, iclass 30, count 2 2006.201.21:58:10.69#ibcon#read 5, iclass 30, count 2 2006.201.21:58:10.69#ibcon#about to read 6, iclass 30, count 2 2006.201.21:58:10.69#ibcon#read 6, iclass 30, count 2 2006.201.21:58:10.69#ibcon#end of sib2, iclass 30, count 2 2006.201.21:58:10.69#ibcon#*mode == 0, iclass 30, count 2 2006.201.21:58:10.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.21:58:10.69#ibcon#[27=AT04-05\r\n] 2006.201.21:58:10.69#ibcon#*before write, iclass 30, count 2 2006.201.21:58:10.69#ibcon#enter sib2, iclass 30, count 2 2006.201.21:58:10.69#ibcon#flushed, iclass 30, count 2 2006.201.21:58:10.69#ibcon#about to write, iclass 30, count 2 2006.201.21:58:10.69#ibcon#wrote, iclass 30, count 2 2006.201.21:58:10.69#ibcon#about to read 3, iclass 30, count 2 2006.201.21:58:10.72#ibcon#read 3, iclass 30, count 2 2006.201.21:58:10.72#ibcon#about to read 4, iclass 30, count 2 2006.201.21:58:10.72#ibcon#read 4, iclass 30, count 2 2006.201.21:58:10.72#ibcon#about to read 5, iclass 30, count 2 2006.201.21:58:10.72#ibcon#read 5, iclass 30, count 2 2006.201.21:58:10.72#ibcon#about to read 6, iclass 30, count 2 2006.201.21:58:10.72#ibcon#read 6, iclass 30, count 2 2006.201.21:58:10.72#ibcon#end of sib2, iclass 30, count 2 2006.201.21:58:10.72#ibcon#*after write, iclass 30, count 2 2006.201.21:58:10.72#ibcon#*before return 0, iclass 30, count 2 2006.201.21:58:10.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:10.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.21:58:10.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.21:58:10.72#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:10.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:10.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:10.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:10.84#ibcon#enter wrdev, iclass 30, count 0 2006.201.21:58:10.84#ibcon#first serial, iclass 30, count 0 2006.201.21:58:10.84#ibcon#enter sib2, iclass 30, count 0 2006.201.21:58:10.84#ibcon#flushed, iclass 30, count 0 2006.201.21:58:10.84#ibcon#about to write, iclass 30, count 0 2006.201.21:58:10.84#ibcon#wrote, iclass 30, count 0 2006.201.21:58:10.84#ibcon#about to read 3, iclass 30, count 0 2006.201.21:58:10.86#ibcon#read 3, iclass 30, count 0 2006.201.21:58:10.86#ibcon#about to read 4, iclass 30, count 0 2006.201.21:58:10.86#ibcon#read 4, iclass 30, count 0 2006.201.21:58:10.86#ibcon#about to read 5, iclass 30, count 0 2006.201.21:58:10.86#ibcon#read 5, iclass 30, count 0 2006.201.21:58:10.86#ibcon#about to read 6, iclass 30, count 0 2006.201.21:58:10.86#ibcon#read 6, iclass 30, count 0 2006.201.21:58:10.86#ibcon#end of sib2, iclass 30, count 0 2006.201.21:58:10.86#ibcon#*mode == 0, iclass 30, count 0 2006.201.21:58:10.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.21:58:10.86#ibcon#[27=USB\r\n] 2006.201.21:58:10.86#ibcon#*before write, iclass 30, count 0 2006.201.21:58:10.86#ibcon#enter sib2, iclass 30, count 0 2006.201.21:58:10.86#ibcon#flushed, iclass 30, count 0 2006.201.21:58:10.86#ibcon#about to write, iclass 30, count 0 2006.201.21:58:10.86#ibcon#wrote, iclass 30, count 0 2006.201.21:58:10.86#ibcon#about to read 3, iclass 30, count 0 2006.201.21:58:10.89#ibcon#read 3, iclass 30, count 0 2006.201.21:58:10.89#ibcon#about to read 4, iclass 30, count 0 2006.201.21:58:10.89#ibcon#read 4, iclass 30, count 0 2006.201.21:58:10.89#ibcon#about to read 5, iclass 30, count 0 2006.201.21:58:10.89#ibcon#read 5, iclass 30, count 0 2006.201.21:58:10.89#ibcon#about to read 6, iclass 30, count 0 2006.201.21:58:10.89#ibcon#read 6, iclass 30, count 0 2006.201.21:58:10.89#ibcon#end of sib2, iclass 30, count 0 2006.201.21:58:10.89#ibcon#*after write, iclass 30, count 0 2006.201.21:58:10.89#ibcon#*before return 0, iclass 30, count 0 2006.201.21:58:10.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:10.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.21:58:10.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.21:58:10.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.21:58:10.89$vck44/vblo=5,709.99 2006.201.21:58:10.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.21:58:10.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.21:58:10.89#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:10.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:10.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:10.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:10.89#ibcon#enter wrdev, iclass 32, count 0 2006.201.21:58:10.89#ibcon#first serial, iclass 32, count 0 2006.201.21:58:10.89#ibcon#enter sib2, iclass 32, count 0 2006.201.21:58:10.89#ibcon#flushed, iclass 32, count 0 2006.201.21:58:10.89#ibcon#about to write, iclass 32, count 0 2006.201.21:58:10.89#ibcon#wrote, iclass 32, count 0 2006.201.21:58:10.89#ibcon#about to read 3, iclass 32, count 0 2006.201.21:58:10.91#ibcon#read 3, iclass 32, count 0 2006.201.21:58:10.91#ibcon#about to read 4, iclass 32, count 0 2006.201.21:58:10.91#ibcon#read 4, iclass 32, count 0 2006.201.21:58:10.91#ibcon#about to read 5, iclass 32, count 0 2006.201.21:58:10.91#ibcon#read 5, iclass 32, count 0 2006.201.21:58:10.91#ibcon#about to read 6, iclass 32, count 0 2006.201.21:58:10.91#ibcon#read 6, iclass 32, count 0 2006.201.21:58:10.91#ibcon#end of sib2, iclass 32, count 0 2006.201.21:58:10.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.21:58:10.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.21:58:10.91#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.21:58:10.91#ibcon#*before write, iclass 32, count 0 2006.201.21:58:10.91#ibcon#enter sib2, iclass 32, count 0 2006.201.21:58:10.91#ibcon#flushed, iclass 32, count 0 2006.201.21:58:10.91#ibcon#about to write, iclass 32, count 0 2006.201.21:58:10.91#ibcon#wrote, iclass 32, count 0 2006.201.21:58:10.91#ibcon#about to read 3, iclass 32, count 0 2006.201.21:58:10.95#ibcon#read 3, iclass 32, count 0 2006.201.21:58:10.95#ibcon#about to read 4, iclass 32, count 0 2006.201.21:58:10.95#ibcon#read 4, iclass 32, count 0 2006.201.21:58:10.95#ibcon#about to read 5, iclass 32, count 0 2006.201.21:58:10.95#ibcon#read 5, iclass 32, count 0 2006.201.21:58:10.95#ibcon#about to read 6, iclass 32, count 0 2006.201.21:58:10.95#ibcon#read 6, iclass 32, count 0 2006.201.21:58:10.95#ibcon#end of sib2, iclass 32, count 0 2006.201.21:58:10.95#ibcon#*after write, iclass 32, count 0 2006.201.21:58:10.95#ibcon#*before return 0, iclass 32, count 0 2006.201.21:58:10.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:10.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.21:58:10.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.21:58:10.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.21:58:10.95$vck44/vb=5,4 2006.201.21:58:10.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.21:58:10.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.21:58:10.95#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:10.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:11.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:11.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:11.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.21:58:11.01#ibcon#first serial, iclass 34, count 2 2006.201.21:58:11.01#ibcon#enter sib2, iclass 34, count 2 2006.201.21:58:11.01#ibcon#flushed, iclass 34, count 2 2006.201.21:58:11.01#ibcon#about to write, iclass 34, count 2 2006.201.21:58:11.01#ibcon#wrote, iclass 34, count 2 2006.201.21:58:11.01#ibcon#about to read 3, iclass 34, count 2 2006.201.21:58:11.03#ibcon#read 3, iclass 34, count 2 2006.201.21:58:11.03#ibcon#about to read 4, iclass 34, count 2 2006.201.21:58:11.03#ibcon#read 4, iclass 34, count 2 2006.201.21:58:11.03#ibcon#about to read 5, iclass 34, count 2 2006.201.21:58:11.03#ibcon#read 5, iclass 34, count 2 2006.201.21:58:11.03#ibcon#about to read 6, iclass 34, count 2 2006.201.21:58:11.03#ibcon#read 6, iclass 34, count 2 2006.201.21:58:11.03#ibcon#end of sib2, iclass 34, count 2 2006.201.21:58:11.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.21:58:11.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.21:58:11.03#ibcon#[27=AT05-04\r\n] 2006.201.21:58:11.03#ibcon#*before write, iclass 34, count 2 2006.201.21:58:11.03#ibcon#enter sib2, iclass 34, count 2 2006.201.21:58:11.03#ibcon#flushed, iclass 34, count 2 2006.201.21:58:11.03#ibcon#about to write, iclass 34, count 2 2006.201.21:58:11.03#ibcon#wrote, iclass 34, count 2 2006.201.21:58:11.03#ibcon#about to read 3, iclass 34, count 2 2006.201.21:58:11.06#ibcon#read 3, iclass 34, count 2 2006.201.21:58:11.06#ibcon#about to read 4, iclass 34, count 2 2006.201.21:58:11.06#ibcon#read 4, iclass 34, count 2 2006.201.21:58:11.06#ibcon#about to read 5, iclass 34, count 2 2006.201.21:58:11.06#ibcon#read 5, iclass 34, count 2 2006.201.21:58:11.06#ibcon#about to read 6, iclass 34, count 2 2006.201.21:58:11.06#ibcon#read 6, iclass 34, count 2 2006.201.21:58:11.06#ibcon#end of sib2, iclass 34, count 2 2006.201.21:58:11.06#ibcon#*after write, iclass 34, count 2 2006.201.21:58:11.06#ibcon#*before return 0, iclass 34, count 2 2006.201.21:58:11.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:11.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.21:58:11.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.21:58:11.06#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:11.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:11.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:11.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:11.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.21:58:11.18#ibcon#first serial, iclass 34, count 0 2006.201.21:58:11.18#ibcon#enter sib2, iclass 34, count 0 2006.201.21:58:11.18#ibcon#flushed, iclass 34, count 0 2006.201.21:58:11.18#ibcon#about to write, iclass 34, count 0 2006.201.21:58:11.18#ibcon#wrote, iclass 34, count 0 2006.201.21:58:11.18#ibcon#about to read 3, iclass 34, count 0 2006.201.21:58:11.20#ibcon#read 3, iclass 34, count 0 2006.201.21:58:11.20#ibcon#about to read 4, iclass 34, count 0 2006.201.21:58:11.20#ibcon#read 4, iclass 34, count 0 2006.201.21:58:11.20#ibcon#about to read 5, iclass 34, count 0 2006.201.21:58:11.20#ibcon#read 5, iclass 34, count 0 2006.201.21:58:11.20#ibcon#about to read 6, iclass 34, count 0 2006.201.21:58:11.20#ibcon#read 6, iclass 34, count 0 2006.201.21:58:11.20#ibcon#end of sib2, iclass 34, count 0 2006.201.21:58:11.20#ibcon#*mode == 0, iclass 34, count 0 2006.201.21:58:11.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.21:58:11.20#ibcon#[27=USB\r\n] 2006.201.21:58:11.20#ibcon#*before write, iclass 34, count 0 2006.201.21:58:11.20#ibcon#enter sib2, iclass 34, count 0 2006.201.21:58:11.20#ibcon#flushed, iclass 34, count 0 2006.201.21:58:11.20#ibcon#about to write, iclass 34, count 0 2006.201.21:58:11.20#ibcon#wrote, iclass 34, count 0 2006.201.21:58:11.20#ibcon#about to read 3, iclass 34, count 0 2006.201.21:58:11.23#ibcon#read 3, iclass 34, count 0 2006.201.21:58:11.23#ibcon#about to read 4, iclass 34, count 0 2006.201.21:58:11.23#ibcon#read 4, iclass 34, count 0 2006.201.21:58:11.23#ibcon#about to read 5, iclass 34, count 0 2006.201.21:58:11.23#ibcon#read 5, iclass 34, count 0 2006.201.21:58:11.23#ibcon#about to read 6, iclass 34, count 0 2006.201.21:58:11.23#ibcon#read 6, iclass 34, count 0 2006.201.21:58:11.23#ibcon#end of sib2, iclass 34, count 0 2006.201.21:58:11.23#ibcon#*after write, iclass 34, count 0 2006.201.21:58:11.23#ibcon#*before return 0, iclass 34, count 0 2006.201.21:58:11.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:11.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.21:58:11.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.21:58:11.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.21:58:11.23$vck44/vblo=6,719.99 2006.201.21:58:11.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.21:58:11.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.21:58:11.23#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:11.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:11.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:11.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:11.23#ibcon#enter wrdev, iclass 36, count 0 2006.201.21:58:11.23#ibcon#first serial, iclass 36, count 0 2006.201.21:58:11.23#ibcon#enter sib2, iclass 36, count 0 2006.201.21:58:11.23#ibcon#flushed, iclass 36, count 0 2006.201.21:58:11.23#ibcon#about to write, iclass 36, count 0 2006.201.21:58:11.23#ibcon#wrote, iclass 36, count 0 2006.201.21:58:11.23#ibcon#about to read 3, iclass 36, count 0 2006.201.21:58:11.25#ibcon#read 3, iclass 36, count 0 2006.201.21:58:11.25#ibcon#about to read 4, iclass 36, count 0 2006.201.21:58:11.25#ibcon#read 4, iclass 36, count 0 2006.201.21:58:11.25#ibcon#about to read 5, iclass 36, count 0 2006.201.21:58:11.25#ibcon#read 5, iclass 36, count 0 2006.201.21:58:11.25#ibcon#about to read 6, iclass 36, count 0 2006.201.21:58:11.25#ibcon#read 6, iclass 36, count 0 2006.201.21:58:11.25#ibcon#end of sib2, iclass 36, count 0 2006.201.21:58:11.25#ibcon#*mode == 0, iclass 36, count 0 2006.201.21:58:11.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.21:58:11.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.21:58:11.25#ibcon#*before write, iclass 36, count 0 2006.201.21:58:11.25#ibcon#enter sib2, iclass 36, count 0 2006.201.21:58:11.25#ibcon#flushed, iclass 36, count 0 2006.201.21:58:11.25#ibcon#about to write, iclass 36, count 0 2006.201.21:58:11.25#ibcon#wrote, iclass 36, count 0 2006.201.21:58:11.25#ibcon#about to read 3, iclass 36, count 0 2006.201.21:58:11.29#ibcon#read 3, iclass 36, count 0 2006.201.21:58:11.29#ibcon#about to read 4, iclass 36, count 0 2006.201.21:58:11.29#ibcon#read 4, iclass 36, count 0 2006.201.21:58:11.29#ibcon#about to read 5, iclass 36, count 0 2006.201.21:58:11.29#ibcon#read 5, iclass 36, count 0 2006.201.21:58:11.29#ibcon#about to read 6, iclass 36, count 0 2006.201.21:58:11.29#ibcon#read 6, iclass 36, count 0 2006.201.21:58:11.29#ibcon#end of sib2, iclass 36, count 0 2006.201.21:58:11.29#ibcon#*after write, iclass 36, count 0 2006.201.21:58:11.29#ibcon#*before return 0, iclass 36, count 0 2006.201.21:58:11.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:11.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.21:58:11.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.21:58:11.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.21:58:11.29$vck44/vb=6,4 2006.201.21:58:11.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.21:58:11.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.21:58:11.29#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:11.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:11.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:11.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:11.35#ibcon#enter wrdev, iclass 38, count 2 2006.201.21:58:11.35#ibcon#first serial, iclass 38, count 2 2006.201.21:58:11.35#ibcon#enter sib2, iclass 38, count 2 2006.201.21:58:11.35#ibcon#flushed, iclass 38, count 2 2006.201.21:58:11.35#ibcon#about to write, iclass 38, count 2 2006.201.21:58:11.35#ibcon#wrote, iclass 38, count 2 2006.201.21:58:11.35#ibcon#about to read 3, iclass 38, count 2 2006.201.21:58:11.37#ibcon#read 3, iclass 38, count 2 2006.201.21:58:11.37#ibcon#about to read 4, iclass 38, count 2 2006.201.21:58:11.37#ibcon#read 4, iclass 38, count 2 2006.201.21:58:11.37#ibcon#about to read 5, iclass 38, count 2 2006.201.21:58:11.37#ibcon#read 5, iclass 38, count 2 2006.201.21:58:11.37#ibcon#about to read 6, iclass 38, count 2 2006.201.21:58:11.37#ibcon#read 6, iclass 38, count 2 2006.201.21:58:11.37#ibcon#end of sib2, iclass 38, count 2 2006.201.21:58:11.37#ibcon#*mode == 0, iclass 38, count 2 2006.201.21:58:11.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.21:58:11.37#ibcon#[27=AT06-04\r\n] 2006.201.21:58:11.37#ibcon#*before write, iclass 38, count 2 2006.201.21:58:11.37#ibcon#enter sib2, iclass 38, count 2 2006.201.21:58:11.37#ibcon#flushed, iclass 38, count 2 2006.201.21:58:11.37#ibcon#about to write, iclass 38, count 2 2006.201.21:58:11.37#ibcon#wrote, iclass 38, count 2 2006.201.21:58:11.37#ibcon#about to read 3, iclass 38, count 2 2006.201.21:58:11.41#ibcon#read 3, iclass 38, count 2 2006.201.21:58:11.41#ibcon#about to read 4, iclass 38, count 2 2006.201.21:58:11.41#ibcon#read 4, iclass 38, count 2 2006.201.21:58:11.41#ibcon#about to read 5, iclass 38, count 2 2006.201.21:58:11.41#ibcon#read 5, iclass 38, count 2 2006.201.21:58:11.41#ibcon#about to read 6, iclass 38, count 2 2006.201.21:58:11.41#ibcon#read 6, iclass 38, count 2 2006.201.21:58:11.41#ibcon#end of sib2, iclass 38, count 2 2006.201.21:58:11.41#ibcon#*after write, iclass 38, count 2 2006.201.21:58:11.41#ibcon#*before return 0, iclass 38, count 2 2006.201.21:58:11.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:11.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.21:58:11.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.21:58:11.41#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:11.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:11.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:11.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:11.53#ibcon#enter wrdev, iclass 38, count 0 2006.201.21:58:11.53#ibcon#first serial, iclass 38, count 0 2006.201.21:58:11.53#ibcon#enter sib2, iclass 38, count 0 2006.201.21:58:11.53#ibcon#flushed, iclass 38, count 0 2006.201.21:58:11.53#ibcon#about to write, iclass 38, count 0 2006.201.21:58:11.53#ibcon#wrote, iclass 38, count 0 2006.201.21:58:11.53#ibcon#about to read 3, iclass 38, count 0 2006.201.21:58:11.55#ibcon#read 3, iclass 38, count 0 2006.201.21:58:11.55#ibcon#about to read 4, iclass 38, count 0 2006.201.21:58:11.55#ibcon#read 4, iclass 38, count 0 2006.201.21:58:11.55#ibcon#about to read 5, iclass 38, count 0 2006.201.21:58:11.55#ibcon#read 5, iclass 38, count 0 2006.201.21:58:11.55#ibcon#about to read 6, iclass 38, count 0 2006.201.21:58:11.55#ibcon#read 6, iclass 38, count 0 2006.201.21:58:11.55#ibcon#end of sib2, iclass 38, count 0 2006.201.21:58:11.55#ibcon#*mode == 0, iclass 38, count 0 2006.201.21:58:11.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.21:58:11.55#ibcon#[27=USB\r\n] 2006.201.21:58:11.55#ibcon#*before write, iclass 38, count 0 2006.201.21:58:11.55#ibcon#enter sib2, iclass 38, count 0 2006.201.21:58:11.55#ibcon#flushed, iclass 38, count 0 2006.201.21:58:11.55#ibcon#about to write, iclass 38, count 0 2006.201.21:58:11.55#ibcon#wrote, iclass 38, count 0 2006.201.21:58:11.55#ibcon#about to read 3, iclass 38, count 0 2006.201.21:58:11.58#ibcon#read 3, iclass 38, count 0 2006.201.21:58:11.58#ibcon#about to read 4, iclass 38, count 0 2006.201.21:58:11.58#ibcon#read 4, iclass 38, count 0 2006.201.21:58:11.58#ibcon#about to read 5, iclass 38, count 0 2006.201.21:58:11.58#ibcon#read 5, iclass 38, count 0 2006.201.21:58:11.58#ibcon#about to read 6, iclass 38, count 0 2006.201.21:58:11.58#ibcon#read 6, iclass 38, count 0 2006.201.21:58:11.58#ibcon#end of sib2, iclass 38, count 0 2006.201.21:58:11.58#ibcon#*after write, iclass 38, count 0 2006.201.21:58:11.58#ibcon#*before return 0, iclass 38, count 0 2006.201.21:58:11.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:11.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.21:58:11.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.21:58:11.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.21:58:11.58$vck44/vblo=7,734.99 2006.201.21:58:11.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.21:58:11.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.21:58:11.58#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:11.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:11.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:11.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:11.58#ibcon#enter wrdev, iclass 40, count 0 2006.201.21:58:11.58#ibcon#first serial, iclass 40, count 0 2006.201.21:58:11.58#ibcon#enter sib2, iclass 40, count 0 2006.201.21:58:11.58#ibcon#flushed, iclass 40, count 0 2006.201.21:58:11.58#ibcon#about to write, iclass 40, count 0 2006.201.21:58:11.58#ibcon#wrote, iclass 40, count 0 2006.201.21:58:11.58#ibcon#about to read 3, iclass 40, count 0 2006.201.21:58:11.60#ibcon#read 3, iclass 40, count 0 2006.201.21:58:11.60#ibcon#about to read 4, iclass 40, count 0 2006.201.21:58:11.60#ibcon#read 4, iclass 40, count 0 2006.201.21:58:11.60#ibcon#about to read 5, iclass 40, count 0 2006.201.21:58:11.60#ibcon#read 5, iclass 40, count 0 2006.201.21:58:11.60#ibcon#about to read 6, iclass 40, count 0 2006.201.21:58:11.60#ibcon#read 6, iclass 40, count 0 2006.201.21:58:11.60#ibcon#end of sib2, iclass 40, count 0 2006.201.21:58:11.60#ibcon#*mode == 0, iclass 40, count 0 2006.201.21:58:11.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.21:58:11.60#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.21:58:11.60#ibcon#*before write, iclass 40, count 0 2006.201.21:58:11.60#ibcon#enter sib2, iclass 40, count 0 2006.201.21:58:11.60#ibcon#flushed, iclass 40, count 0 2006.201.21:58:11.60#ibcon#about to write, iclass 40, count 0 2006.201.21:58:11.60#ibcon#wrote, iclass 40, count 0 2006.201.21:58:11.60#ibcon#about to read 3, iclass 40, count 0 2006.201.21:58:11.64#ibcon#read 3, iclass 40, count 0 2006.201.21:58:11.64#ibcon#about to read 4, iclass 40, count 0 2006.201.21:58:11.64#ibcon#read 4, iclass 40, count 0 2006.201.21:58:11.64#ibcon#about to read 5, iclass 40, count 0 2006.201.21:58:11.64#ibcon#read 5, iclass 40, count 0 2006.201.21:58:11.64#ibcon#about to read 6, iclass 40, count 0 2006.201.21:58:11.64#ibcon#read 6, iclass 40, count 0 2006.201.21:58:11.64#ibcon#end of sib2, iclass 40, count 0 2006.201.21:58:11.64#ibcon#*after write, iclass 40, count 0 2006.201.21:58:11.64#ibcon#*before return 0, iclass 40, count 0 2006.201.21:58:11.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:11.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.21:58:11.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.21:58:11.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.21:58:11.64$vck44/vb=7,4 2006.201.21:58:11.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.21:58:11.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.21:58:11.64#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:11.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:11.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:11.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:11.70#ibcon#enter wrdev, iclass 4, count 2 2006.201.21:58:11.70#ibcon#first serial, iclass 4, count 2 2006.201.21:58:11.70#ibcon#enter sib2, iclass 4, count 2 2006.201.21:58:11.70#ibcon#flushed, iclass 4, count 2 2006.201.21:58:11.70#ibcon#about to write, iclass 4, count 2 2006.201.21:58:11.70#ibcon#wrote, iclass 4, count 2 2006.201.21:58:11.70#ibcon#about to read 3, iclass 4, count 2 2006.201.21:58:11.72#ibcon#read 3, iclass 4, count 2 2006.201.21:58:11.72#ibcon#about to read 4, iclass 4, count 2 2006.201.21:58:11.72#ibcon#read 4, iclass 4, count 2 2006.201.21:58:11.72#ibcon#about to read 5, iclass 4, count 2 2006.201.21:58:11.72#ibcon#read 5, iclass 4, count 2 2006.201.21:58:11.72#ibcon#about to read 6, iclass 4, count 2 2006.201.21:58:11.72#ibcon#read 6, iclass 4, count 2 2006.201.21:58:11.72#ibcon#end of sib2, iclass 4, count 2 2006.201.21:58:11.72#ibcon#*mode == 0, iclass 4, count 2 2006.201.21:58:11.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.21:58:11.72#ibcon#[27=AT07-04\r\n] 2006.201.21:58:11.72#ibcon#*before write, iclass 4, count 2 2006.201.21:58:11.72#ibcon#enter sib2, iclass 4, count 2 2006.201.21:58:11.72#ibcon#flushed, iclass 4, count 2 2006.201.21:58:11.72#ibcon#about to write, iclass 4, count 2 2006.201.21:58:11.72#ibcon#wrote, iclass 4, count 2 2006.201.21:58:11.72#ibcon#about to read 3, iclass 4, count 2 2006.201.21:58:11.75#ibcon#read 3, iclass 4, count 2 2006.201.21:58:11.75#ibcon#about to read 4, iclass 4, count 2 2006.201.21:58:11.75#ibcon#read 4, iclass 4, count 2 2006.201.21:58:11.75#ibcon#about to read 5, iclass 4, count 2 2006.201.21:58:11.75#ibcon#read 5, iclass 4, count 2 2006.201.21:58:11.75#ibcon#about to read 6, iclass 4, count 2 2006.201.21:58:11.75#ibcon#read 6, iclass 4, count 2 2006.201.21:58:11.75#ibcon#end of sib2, iclass 4, count 2 2006.201.21:58:11.75#ibcon#*after write, iclass 4, count 2 2006.201.21:58:11.75#ibcon#*before return 0, iclass 4, count 2 2006.201.21:58:11.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:11.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.21:58:11.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.21:58:11.75#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:11.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:11.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:11.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:11.87#ibcon#enter wrdev, iclass 4, count 0 2006.201.21:58:11.87#ibcon#first serial, iclass 4, count 0 2006.201.21:58:11.87#ibcon#enter sib2, iclass 4, count 0 2006.201.21:58:11.87#ibcon#flushed, iclass 4, count 0 2006.201.21:58:11.87#ibcon#about to write, iclass 4, count 0 2006.201.21:58:11.87#ibcon#wrote, iclass 4, count 0 2006.201.21:58:11.87#ibcon#about to read 3, iclass 4, count 0 2006.201.21:58:11.89#ibcon#read 3, iclass 4, count 0 2006.201.21:58:11.89#ibcon#about to read 4, iclass 4, count 0 2006.201.21:58:11.89#ibcon#read 4, iclass 4, count 0 2006.201.21:58:11.89#ibcon#about to read 5, iclass 4, count 0 2006.201.21:58:11.89#ibcon#read 5, iclass 4, count 0 2006.201.21:58:11.89#ibcon#about to read 6, iclass 4, count 0 2006.201.21:58:11.89#ibcon#read 6, iclass 4, count 0 2006.201.21:58:11.89#ibcon#end of sib2, iclass 4, count 0 2006.201.21:58:11.89#ibcon#*mode == 0, iclass 4, count 0 2006.201.21:58:11.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.21:58:11.89#ibcon#[27=USB\r\n] 2006.201.21:58:11.89#ibcon#*before write, iclass 4, count 0 2006.201.21:58:11.89#ibcon#enter sib2, iclass 4, count 0 2006.201.21:58:11.89#ibcon#flushed, iclass 4, count 0 2006.201.21:58:11.89#ibcon#about to write, iclass 4, count 0 2006.201.21:58:11.89#ibcon#wrote, iclass 4, count 0 2006.201.21:58:11.89#ibcon#about to read 3, iclass 4, count 0 2006.201.21:58:11.92#ibcon#read 3, iclass 4, count 0 2006.201.21:58:11.92#ibcon#about to read 4, iclass 4, count 0 2006.201.21:58:11.92#ibcon#read 4, iclass 4, count 0 2006.201.21:58:11.92#ibcon#about to read 5, iclass 4, count 0 2006.201.21:58:11.92#ibcon#read 5, iclass 4, count 0 2006.201.21:58:11.92#ibcon#about to read 6, iclass 4, count 0 2006.201.21:58:11.92#ibcon#read 6, iclass 4, count 0 2006.201.21:58:11.92#ibcon#end of sib2, iclass 4, count 0 2006.201.21:58:11.92#ibcon#*after write, iclass 4, count 0 2006.201.21:58:11.92#ibcon#*before return 0, iclass 4, count 0 2006.201.21:58:11.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:11.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.21:58:11.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.21:58:11.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.21:58:11.92$vck44/vblo=8,744.99 2006.201.21:58:11.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.21:58:11.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.21:58:11.92#ibcon#ireg 17 cls_cnt 0 2006.201.21:58:11.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:11.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:11.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:11.92#ibcon#enter wrdev, iclass 6, count 0 2006.201.21:58:11.92#ibcon#first serial, iclass 6, count 0 2006.201.21:58:11.92#ibcon#enter sib2, iclass 6, count 0 2006.201.21:58:11.92#ibcon#flushed, iclass 6, count 0 2006.201.21:58:11.92#ibcon#about to write, iclass 6, count 0 2006.201.21:58:11.92#ibcon#wrote, iclass 6, count 0 2006.201.21:58:11.92#ibcon#about to read 3, iclass 6, count 0 2006.201.21:58:11.94#ibcon#read 3, iclass 6, count 0 2006.201.21:58:11.94#ibcon#about to read 4, iclass 6, count 0 2006.201.21:58:11.94#ibcon#read 4, iclass 6, count 0 2006.201.21:58:11.94#ibcon#about to read 5, iclass 6, count 0 2006.201.21:58:11.94#ibcon#read 5, iclass 6, count 0 2006.201.21:58:11.94#ibcon#about to read 6, iclass 6, count 0 2006.201.21:58:11.94#ibcon#read 6, iclass 6, count 0 2006.201.21:58:11.94#ibcon#end of sib2, iclass 6, count 0 2006.201.21:58:11.94#ibcon#*mode == 0, iclass 6, count 0 2006.201.21:58:11.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.21:58:11.94#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.21:58:11.94#ibcon#*before write, iclass 6, count 0 2006.201.21:58:11.94#ibcon#enter sib2, iclass 6, count 0 2006.201.21:58:11.94#ibcon#flushed, iclass 6, count 0 2006.201.21:58:11.94#ibcon#about to write, iclass 6, count 0 2006.201.21:58:11.94#ibcon#wrote, iclass 6, count 0 2006.201.21:58:11.94#ibcon#about to read 3, iclass 6, count 0 2006.201.21:58:11.98#ibcon#read 3, iclass 6, count 0 2006.201.21:58:11.98#ibcon#about to read 4, iclass 6, count 0 2006.201.21:58:11.98#ibcon#read 4, iclass 6, count 0 2006.201.21:58:11.98#ibcon#about to read 5, iclass 6, count 0 2006.201.21:58:11.98#ibcon#read 5, iclass 6, count 0 2006.201.21:58:11.98#ibcon#about to read 6, iclass 6, count 0 2006.201.21:58:11.98#ibcon#read 6, iclass 6, count 0 2006.201.21:58:11.98#ibcon#end of sib2, iclass 6, count 0 2006.201.21:58:11.98#ibcon#*after write, iclass 6, count 0 2006.201.21:58:11.98#ibcon#*before return 0, iclass 6, count 0 2006.201.21:58:11.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:11.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.21:58:11.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.21:58:11.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.21:58:11.98$vck44/vb=8,4 2006.201.21:58:11.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.21:58:11.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.21:58:11.98#ibcon#ireg 11 cls_cnt 2 2006.201.21:58:11.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:12.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:12.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:12.04#ibcon#enter wrdev, iclass 10, count 2 2006.201.21:58:12.04#ibcon#first serial, iclass 10, count 2 2006.201.21:58:12.04#ibcon#enter sib2, iclass 10, count 2 2006.201.21:58:12.04#ibcon#flushed, iclass 10, count 2 2006.201.21:58:12.04#ibcon#about to write, iclass 10, count 2 2006.201.21:58:12.04#ibcon#wrote, iclass 10, count 2 2006.201.21:58:12.04#ibcon#about to read 3, iclass 10, count 2 2006.201.21:58:12.06#ibcon#read 3, iclass 10, count 2 2006.201.21:58:12.06#ibcon#about to read 4, iclass 10, count 2 2006.201.21:58:12.06#ibcon#read 4, iclass 10, count 2 2006.201.21:58:12.06#ibcon#about to read 5, iclass 10, count 2 2006.201.21:58:12.06#ibcon#read 5, iclass 10, count 2 2006.201.21:58:12.06#ibcon#about to read 6, iclass 10, count 2 2006.201.21:58:12.06#ibcon#read 6, iclass 10, count 2 2006.201.21:58:12.06#ibcon#end of sib2, iclass 10, count 2 2006.201.21:58:12.06#ibcon#*mode == 0, iclass 10, count 2 2006.201.21:58:12.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.21:58:12.06#ibcon#[27=AT08-04\r\n] 2006.201.21:58:12.06#ibcon#*before write, iclass 10, count 2 2006.201.21:58:12.06#ibcon#enter sib2, iclass 10, count 2 2006.201.21:58:12.06#ibcon#flushed, iclass 10, count 2 2006.201.21:58:12.06#ibcon#about to write, iclass 10, count 2 2006.201.21:58:12.06#ibcon#wrote, iclass 10, count 2 2006.201.21:58:12.06#ibcon#about to read 3, iclass 10, count 2 2006.201.21:58:12.09#ibcon#read 3, iclass 10, count 2 2006.201.21:58:12.09#ibcon#about to read 4, iclass 10, count 2 2006.201.21:58:12.09#ibcon#read 4, iclass 10, count 2 2006.201.21:58:12.09#ibcon#about to read 5, iclass 10, count 2 2006.201.21:58:12.09#ibcon#read 5, iclass 10, count 2 2006.201.21:58:12.09#ibcon#about to read 6, iclass 10, count 2 2006.201.21:58:12.09#ibcon#read 6, iclass 10, count 2 2006.201.21:58:12.09#ibcon#end of sib2, iclass 10, count 2 2006.201.21:58:12.09#ibcon#*after write, iclass 10, count 2 2006.201.21:58:12.09#ibcon#*before return 0, iclass 10, count 2 2006.201.21:58:12.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:12.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.21:58:12.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.21:58:12.09#ibcon#ireg 7 cls_cnt 0 2006.201.21:58:12.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:12.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:12.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:12.21#ibcon#enter wrdev, iclass 10, count 0 2006.201.21:58:12.21#ibcon#first serial, iclass 10, count 0 2006.201.21:58:12.21#ibcon#enter sib2, iclass 10, count 0 2006.201.21:58:12.21#ibcon#flushed, iclass 10, count 0 2006.201.21:58:12.21#ibcon#about to write, iclass 10, count 0 2006.201.21:58:12.21#ibcon#wrote, iclass 10, count 0 2006.201.21:58:12.21#ibcon#about to read 3, iclass 10, count 0 2006.201.21:58:12.23#ibcon#read 3, iclass 10, count 0 2006.201.21:58:12.23#ibcon#about to read 4, iclass 10, count 0 2006.201.21:58:12.23#ibcon#read 4, iclass 10, count 0 2006.201.21:58:12.23#ibcon#about to read 5, iclass 10, count 0 2006.201.21:58:12.23#ibcon#read 5, iclass 10, count 0 2006.201.21:58:12.23#ibcon#about to read 6, iclass 10, count 0 2006.201.21:58:12.23#ibcon#read 6, iclass 10, count 0 2006.201.21:58:12.23#ibcon#end of sib2, iclass 10, count 0 2006.201.21:58:12.23#ibcon#*mode == 0, iclass 10, count 0 2006.201.21:58:12.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.21:58:12.23#ibcon#[27=USB\r\n] 2006.201.21:58:12.23#ibcon#*before write, iclass 10, count 0 2006.201.21:58:12.23#ibcon#enter sib2, iclass 10, count 0 2006.201.21:58:12.23#ibcon#flushed, iclass 10, count 0 2006.201.21:58:12.23#ibcon#about to write, iclass 10, count 0 2006.201.21:58:12.23#ibcon#wrote, iclass 10, count 0 2006.201.21:58:12.23#ibcon#about to read 3, iclass 10, count 0 2006.201.21:58:12.26#ibcon#read 3, iclass 10, count 0 2006.201.21:58:12.26#ibcon#about to read 4, iclass 10, count 0 2006.201.21:58:12.26#ibcon#read 4, iclass 10, count 0 2006.201.21:58:12.26#ibcon#about to read 5, iclass 10, count 0 2006.201.21:58:12.26#ibcon#read 5, iclass 10, count 0 2006.201.21:58:12.26#ibcon#about to read 6, iclass 10, count 0 2006.201.21:58:12.26#ibcon#read 6, iclass 10, count 0 2006.201.21:58:12.26#ibcon#end of sib2, iclass 10, count 0 2006.201.21:58:12.26#ibcon#*after write, iclass 10, count 0 2006.201.21:58:12.26#ibcon#*before return 0, iclass 10, count 0 2006.201.21:58:12.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:12.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.21:58:12.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.21:58:12.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.21:58:12.26$vck44/vabw=wide 2006.201.21:58:12.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.21:58:12.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.21:58:12.26#ibcon#ireg 8 cls_cnt 0 2006.201.21:58:12.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:12.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:12.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:12.26#ibcon#enter wrdev, iclass 12, count 0 2006.201.21:58:12.26#ibcon#first serial, iclass 12, count 0 2006.201.21:58:12.26#ibcon#enter sib2, iclass 12, count 0 2006.201.21:58:12.26#ibcon#flushed, iclass 12, count 0 2006.201.21:58:12.26#ibcon#about to write, iclass 12, count 0 2006.201.21:58:12.26#ibcon#wrote, iclass 12, count 0 2006.201.21:58:12.26#ibcon#about to read 3, iclass 12, count 0 2006.201.21:58:12.28#ibcon#read 3, iclass 12, count 0 2006.201.21:58:12.28#ibcon#about to read 4, iclass 12, count 0 2006.201.21:58:12.28#ibcon#read 4, iclass 12, count 0 2006.201.21:58:12.28#ibcon#about to read 5, iclass 12, count 0 2006.201.21:58:12.28#ibcon#read 5, iclass 12, count 0 2006.201.21:58:12.28#ibcon#about to read 6, iclass 12, count 0 2006.201.21:58:12.28#ibcon#read 6, iclass 12, count 0 2006.201.21:58:12.28#ibcon#end of sib2, iclass 12, count 0 2006.201.21:58:12.28#ibcon#*mode == 0, iclass 12, count 0 2006.201.21:58:12.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.21:58:12.28#ibcon#[25=BW32\r\n] 2006.201.21:58:12.28#ibcon#*before write, iclass 12, count 0 2006.201.21:58:12.28#ibcon#enter sib2, iclass 12, count 0 2006.201.21:58:12.28#ibcon#flushed, iclass 12, count 0 2006.201.21:58:12.28#ibcon#about to write, iclass 12, count 0 2006.201.21:58:12.28#ibcon#wrote, iclass 12, count 0 2006.201.21:58:12.28#ibcon#about to read 3, iclass 12, count 0 2006.201.21:58:12.32#ibcon#read 3, iclass 12, count 0 2006.201.21:58:12.32#ibcon#about to read 4, iclass 12, count 0 2006.201.21:58:12.32#ibcon#read 4, iclass 12, count 0 2006.201.21:58:12.32#ibcon#about to read 5, iclass 12, count 0 2006.201.21:58:12.32#ibcon#read 5, iclass 12, count 0 2006.201.21:58:12.32#ibcon#about to read 6, iclass 12, count 0 2006.201.21:58:12.32#ibcon#read 6, iclass 12, count 0 2006.201.21:58:12.32#ibcon#end of sib2, iclass 12, count 0 2006.201.21:58:12.32#ibcon#*after write, iclass 12, count 0 2006.201.21:58:12.32#ibcon#*before return 0, iclass 12, count 0 2006.201.21:58:12.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:12.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.21:58:12.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.21:58:12.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.21:58:12.32$vck44/vbbw=wide 2006.201.21:58:12.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.21:58:12.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.21:58:12.32#ibcon#ireg 8 cls_cnt 0 2006.201.21:58:12.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:58:12.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:58:12.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:58:12.38#ibcon#enter wrdev, iclass 14, count 0 2006.201.21:58:12.38#ibcon#first serial, iclass 14, count 0 2006.201.21:58:12.38#ibcon#enter sib2, iclass 14, count 0 2006.201.21:58:12.38#ibcon#flushed, iclass 14, count 0 2006.201.21:58:12.38#ibcon#about to write, iclass 14, count 0 2006.201.21:58:12.38#ibcon#wrote, iclass 14, count 0 2006.201.21:58:12.38#ibcon#about to read 3, iclass 14, count 0 2006.201.21:58:12.40#ibcon#read 3, iclass 14, count 0 2006.201.21:58:12.40#ibcon#about to read 4, iclass 14, count 0 2006.201.21:58:12.40#ibcon#read 4, iclass 14, count 0 2006.201.21:58:12.40#ibcon#about to read 5, iclass 14, count 0 2006.201.21:58:12.40#ibcon#read 5, iclass 14, count 0 2006.201.21:58:12.40#ibcon#about to read 6, iclass 14, count 0 2006.201.21:58:12.40#ibcon#read 6, iclass 14, count 0 2006.201.21:58:12.40#ibcon#end of sib2, iclass 14, count 0 2006.201.21:58:12.40#ibcon#*mode == 0, iclass 14, count 0 2006.201.21:58:12.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.21:58:12.40#ibcon#[27=BW32\r\n] 2006.201.21:58:12.40#ibcon#*before write, iclass 14, count 0 2006.201.21:58:12.40#ibcon#enter sib2, iclass 14, count 0 2006.201.21:58:12.40#ibcon#flushed, iclass 14, count 0 2006.201.21:58:12.40#ibcon#about to write, iclass 14, count 0 2006.201.21:58:12.40#ibcon#wrote, iclass 14, count 0 2006.201.21:58:12.40#ibcon#about to read 3, iclass 14, count 0 2006.201.21:58:12.43#ibcon#read 3, iclass 14, count 0 2006.201.21:58:12.43#ibcon#about to read 4, iclass 14, count 0 2006.201.21:58:12.43#ibcon#read 4, iclass 14, count 0 2006.201.21:58:12.43#ibcon#about to read 5, iclass 14, count 0 2006.201.21:58:12.43#ibcon#read 5, iclass 14, count 0 2006.201.21:58:12.43#ibcon#about to read 6, iclass 14, count 0 2006.201.21:58:12.43#ibcon#read 6, iclass 14, count 0 2006.201.21:58:12.43#ibcon#end of sib2, iclass 14, count 0 2006.201.21:58:12.43#ibcon#*after write, iclass 14, count 0 2006.201.21:58:12.43#ibcon#*before return 0, iclass 14, count 0 2006.201.21:58:12.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:58:12.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.21:58:12.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.21:58:12.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.21:58:12.43$setupk4/ifdk4 2006.201.21:58:12.43$ifdk4/lo= 2006.201.21:58:12.43$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.21:58:12.43$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.21:58:12.43$ifdk4/patch= 2006.201.21:58:12.43$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.21:58:12.43$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.21:58:12.43$setupk4/!*+20s 2006.201.21:58:15.15#abcon#<5=/05 1.7 2.9 19.931001001.6\r\n> 2006.201.21:58:15.17#abcon#{5=INTERFACE CLEAR} 2006.201.21:58:15.23#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:58:25.32#abcon#<5=/05 1.6 2.9 19.931001001.6\r\n> 2006.201.21:58:25.34#abcon#{5=INTERFACE CLEAR} 2006.201.21:58:25.40#abcon#[5=S1D000X0/0*\r\n] 2006.201.21:58:26.88$setupk4/"tpicd 2006.201.21:58:26.88$setupk4/echo=off 2006.201.21:58:26.88$setupk4/xlog=off 2006.201.21:58:26.88:!2006.201.22:00:14 2006.201.21:58:27.14#trakl#Source acquired 2006.201.21:58:29.13#flagr#flagr/antenna,acquired 2006.201.22:00:14.00:preob 2006.201.22:00:15.13/onsource/TRACKING 2006.201.22:00:15.13:!2006.201.22:00:24 2006.201.22:00:24.00:"tape 2006.201.22:00:24.00:"st=record 2006.201.22:00:24.00:data_valid=on 2006.201.22:00:24.00:midob 2006.201.22:00:24.13/onsource/TRACKING 2006.201.22:00:24.13/wx/19.94,1001.5,100 2006.201.22:00:24.30/cable/+6.4824E-03 2006.201.22:00:25.39/va/01,08,usb,yes,53,56 2006.201.22:00:25.39/va/02,07,usb,yes,57,58 2006.201.22:00:25.39/va/03,08,usb,yes,52,54 2006.201.22:00:25.39/va/04,07,usb,yes,59,62 2006.201.22:00:25.39/va/05,04,usb,yes,52,54 2006.201.22:00:25.39/va/06,05,usb,yes,53,53 2006.201.22:00:25.39/va/07,05,usb,yes,52,53 2006.201.22:00:25.39/va/08,04,usb,yes,51,60 2006.201.22:00:25.62/valo/01,524.99,yes,locked 2006.201.22:00:25.62/valo/02,534.99,yes,locked 2006.201.22:00:25.62/valo/03,564.99,yes,locked 2006.201.22:00:25.62/valo/04,624.99,yes,locked 2006.201.22:00:25.62/valo/05,734.99,yes,locked 2006.201.22:00:25.62/valo/06,814.99,yes,locked 2006.201.22:00:25.62/valo/07,864.99,yes,locked 2006.201.22:00:25.62/valo/08,884.99,yes,locked 2006.201.22:00:26.71/vb/01,04,usb,yes,31,28 2006.201.22:00:26.71/vb/02,05,usb,yes,29,29 2006.201.22:00:26.71/vb/03,04,usb,yes,30,33 2006.201.22:00:26.71/vb/04,05,usb,yes,30,29 2006.201.22:00:26.71/vb/05,04,usb,yes,27,30 2006.201.22:00:26.71/vb/06,04,usb,yes,32,28 2006.201.22:00:26.71/vb/07,04,usb,yes,31,31 2006.201.22:00:26.71/vb/08,04,usb,yes,29,32 2006.201.22:00:26.95/vblo/01,629.99,yes,locked 2006.201.22:00:26.95/vblo/02,634.99,yes,locked 2006.201.22:00:26.95/vblo/03,649.99,yes,locked 2006.201.22:00:26.95/vblo/04,679.99,yes,locked 2006.201.22:00:26.95/vblo/05,709.99,yes,locked 2006.201.22:00:26.95/vblo/06,719.99,yes,locked 2006.201.22:00:26.95/vblo/07,734.99,yes,locked 2006.201.22:00:26.95/vblo/08,744.99,yes,locked 2006.201.22:00:27.10/vabw/8 2006.201.22:00:27.25/vbbw/8 2006.201.22:00:27.34/xfe/off,on,16.0 2006.201.22:00:27.78/ifatt/23,28,28,28 2006.201.22:00:28.07/fmout-gps/S +4.54E-07 2006.201.22:00:28.11:!2006.201.22:01:54 2006.201.22:01:54.00:data_valid=off 2006.201.22:01:54.00:"et 2006.201.22:01:54.00:!+3s 2006.201.22:01:57.02:"tape 2006.201.22:01:57.02:postob 2006.201.22:01:57.25/cable/+6.4798E-03 2006.201.22:01:57.25/wx/19.96,1001.4,100 2006.201.22:01:57.33/fmout-gps/S +4.54E-07 2006.201.22:01:57.33:scan_name=201-2204,jd0607,230 2006.201.22:01:57.33:source=cta26,033930.94,-014635.8,2000.0,cw 2006.201.22:01:58.14#flagr#flagr/antenna,new-source 2006.201.22:01:58.14:checkk5 2006.201.22:01:58.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.22:01:58.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.22:01:59.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.22:01:59.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.22:02:00.00/chk_obsdata//k5ts1/T2012200??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.22:02:00.37/chk_obsdata//k5ts2/T2012200??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.22:02:00.74/chk_obsdata//k5ts3/T2012200??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.22:02:01.10/chk_obsdata//k5ts4/T2012200??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.22:02:01.79/k5log//k5ts1_log_newline 2006.201.22:02:02.48/k5log//k5ts2_log_newline 2006.201.22:02:03.17/k5log//k5ts3_log_newline 2006.201.22:02:03.85/k5log//k5ts4_log_newline 2006.201.22:02:03.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.22:02:03.88:setupk4=1 2006.201.22:02:03.88$setupk4/echo=on 2006.201.22:02:03.88$setupk4/pcalon 2006.201.22:02:03.88$pcalon/"no phase cal control is implemented here 2006.201.22:02:03.88$setupk4/"tpicd=stop 2006.201.22:02:03.88$setupk4/"rec=synch_on 2006.201.22:02:03.88$setupk4/"rec_mode=128 2006.201.22:02:03.88$setupk4/!* 2006.201.22:02:03.88$setupk4/recpk4 2006.201.22:02:03.88$recpk4/recpatch= 2006.201.22:02:03.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.22:02:03.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.22:02:03.88$setupk4/vck44 2006.201.22:02:03.88$vck44/valo=1,524.99 2006.201.22:02:03.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.22:02:03.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.22:02:03.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:03.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:03.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:03.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:03.88#ibcon#enter wrdev, iclass 39, count 0 2006.201.22:02:03.88#ibcon#first serial, iclass 39, count 0 2006.201.22:02:03.88#ibcon#enter sib2, iclass 39, count 0 2006.201.22:02:03.88#ibcon#flushed, iclass 39, count 0 2006.201.22:02:03.88#ibcon#about to write, iclass 39, count 0 2006.201.22:02:03.88#ibcon#wrote, iclass 39, count 0 2006.201.22:02:03.88#ibcon#about to read 3, iclass 39, count 0 2006.201.22:02:03.92#ibcon#read 3, iclass 39, count 0 2006.201.22:02:03.92#ibcon#about to read 4, iclass 39, count 0 2006.201.22:02:03.92#ibcon#read 4, iclass 39, count 0 2006.201.22:02:03.92#ibcon#about to read 5, iclass 39, count 0 2006.201.22:02:03.92#ibcon#read 5, iclass 39, count 0 2006.201.22:02:03.92#ibcon#about to read 6, iclass 39, count 0 2006.201.22:02:03.92#ibcon#read 6, iclass 39, count 0 2006.201.22:02:03.92#ibcon#end of sib2, iclass 39, count 0 2006.201.22:02:03.92#ibcon#*mode == 0, iclass 39, count 0 2006.201.22:02:03.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.22:02:03.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.22:02:03.92#ibcon#*before write, iclass 39, count 0 2006.201.22:02:03.92#ibcon#enter sib2, iclass 39, count 0 2006.201.22:02:03.92#ibcon#flushed, iclass 39, count 0 2006.201.22:02:03.92#ibcon#about to write, iclass 39, count 0 2006.201.22:02:03.92#ibcon#wrote, iclass 39, count 0 2006.201.22:02:03.92#ibcon#about to read 3, iclass 39, count 0 2006.201.22:02:03.97#ibcon#read 3, iclass 39, count 0 2006.201.22:02:03.97#ibcon#about to read 4, iclass 39, count 0 2006.201.22:02:03.97#ibcon#read 4, iclass 39, count 0 2006.201.22:02:03.97#ibcon#about to read 5, iclass 39, count 0 2006.201.22:02:03.97#ibcon#read 5, iclass 39, count 0 2006.201.22:02:03.97#ibcon#about to read 6, iclass 39, count 0 2006.201.22:02:03.97#ibcon#read 6, iclass 39, count 0 2006.201.22:02:03.97#ibcon#end of sib2, iclass 39, count 0 2006.201.22:02:03.97#ibcon#*after write, iclass 39, count 0 2006.201.22:02:03.97#ibcon#*before return 0, iclass 39, count 0 2006.201.22:02:03.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:03.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:03.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.22:02:03.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.22:02:03.97$vck44/va=1,8 2006.201.22:02:03.97#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.22:02:03.97#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.22:02:03.97#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:03.97#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:03.97#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:03.97#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:03.97#ibcon#enter wrdev, iclass 2, count 2 2006.201.22:02:03.97#ibcon#first serial, iclass 2, count 2 2006.201.22:02:03.97#ibcon#enter sib2, iclass 2, count 2 2006.201.22:02:03.97#ibcon#flushed, iclass 2, count 2 2006.201.22:02:03.97#ibcon#about to write, iclass 2, count 2 2006.201.22:02:03.97#ibcon#wrote, iclass 2, count 2 2006.201.22:02:03.97#ibcon#about to read 3, iclass 2, count 2 2006.201.22:02:03.99#ibcon#read 3, iclass 2, count 2 2006.201.22:02:03.99#ibcon#about to read 4, iclass 2, count 2 2006.201.22:02:03.99#ibcon#read 4, iclass 2, count 2 2006.201.22:02:03.99#ibcon#about to read 5, iclass 2, count 2 2006.201.22:02:03.99#ibcon#read 5, iclass 2, count 2 2006.201.22:02:03.99#ibcon#about to read 6, iclass 2, count 2 2006.201.22:02:03.99#ibcon#read 6, iclass 2, count 2 2006.201.22:02:03.99#ibcon#end of sib2, iclass 2, count 2 2006.201.22:02:03.99#ibcon#*mode == 0, iclass 2, count 2 2006.201.22:02:03.99#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.22:02:03.99#ibcon#[25=AT01-08\r\n] 2006.201.22:02:03.99#ibcon#*before write, iclass 2, count 2 2006.201.22:02:03.99#ibcon#enter sib2, iclass 2, count 2 2006.201.22:02:03.99#ibcon#flushed, iclass 2, count 2 2006.201.22:02:03.99#ibcon#about to write, iclass 2, count 2 2006.201.22:02:03.99#ibcon#wrote, iclass 2, count 2 2006.201.22:02:03.99#ibcon#about to read 3, iclass 2, count 2 2006.201.22:02:04.02#ibcon#read 3, iclass 2, count 2 2006.201.22:02:04.02#ibcon#about to read 4, iclass 2, count 2 2006.201.22:02:04.02#ibcon#read 4, iclass 2, count 2 2006.201.22:02:04.02#ibcon#about to read 5, iclass 2, count 2 2006.201.22:02:04.02#ibcon#read 5, iclass 2, count 2 2006.201.22:02:04.02#ibcon#about to read 6, iclass 2, count 2 2006.201.22:02:04.02#ibcon#read 6, iclass 2, count 2 2006.201.22:02:04.02#ibcon#end of sib2, iclass 2, count 2 2006.201.22:02:04.02#ibcon#*after write, iclass 2, count 2 2006.201.22:02:04.02#ibcon#*before return 0, iclass 2, count 2 2006.201.22:02:04.02#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:04.02#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:04.02#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.22:02:04.02#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:04.02#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:04.14#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:04.14#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:04.14#ibcon#enter wrdev, iclass 2, count 0 2006.201.22:02:04.14#ibcon#first serial, iclass 2, count 0 2006.201.22:02:04.14#ibcon#enter sib2, iclass 2, count 0 2006.201.22:02:04.14#ibcon#flushed, iclass 2, count 0 2006.201.22:02:04.14#ibcon#about to write, iclass 2, count 0 2006.201.22:02:04.14#ibcon#wrote, iclass 2, count 0 2006.201.22:02:04.14#ibcon#about to read 3, iclass 2, count 0 2006.201.22:02:04.16#ibcon#read 3, iclass 2, count 0 2006.201.22:02:04.16#ibcon#about to read 4, iclass 2, count 0 2006.201.22:02:04.16#ibcon#read 4, iclass 2, count 0 2006.201.22:02:04.16#ibcon#about to read 5, iclass 2, count 0 2006.201.22:02:04.16#ibcon#read 5, iclass 2, count 0 2006.201.22:02:04.16#ibcon#about to read 6, iclass 2, count 0 2006.201.22:02:04.16#ibcon#read 6, iclass 2, count 0 2006.201.22:02:04.16#ibcon#end of sib2, iclass 2, count 0 2006.201.22:02:04.16#ibcon#*mode == 0, iclass 2, count 0 2006.201.22:02:04.16#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.22:02:04.16#ibcon#[25=USB\r\n] 2006.201.22:02:04.16#ibcon#*before write, iclass 2, count 0 2006.201.22:02:04.16#ibcon#enter sib2, iclass 2, count 0 2006.201.22:02:04.16#ibcon#flushed, iclass 2, count 0 2006.201.22:02:04.16#ibcon#about to write, iclass 2, count 0 2006.201.22:02:04.16#ibcon#wrote, iclass 2, count 0 2006.201.22:02:04.16#ibcon#about to read 3, iclass 2, count 0 2006.201.22:02:04.19#ibcon#read 3, iclass 2, count 0 2006.201.22:02:04.19#ibcon#about to read 4, iclass 2, count 0 2006.201.22:02:04.19#ibcon#read 4, iclass 2, count 0 2006.201.22:02:04.19#ibcon#about to read 5, iclass 2, count 0 2006.201.22:02:04.19#ibcon#read 5, iclass 2, count 0 2006.201.22:02:04.19#ibcon#about to read 6, iclass 2, count 0 2006.201.22:02:04.19#ibcon#read 6, iclass 2, count 0 2006.201.22:02:04.19#ibcon#end of sib2, iclass 2, count 0 2006.201.22:02:04.19#ibcon#*after write, iclass 2, count 0 2006.201.22:02:04.19#ibcon#*before return 0, iclass 2, count 0 2006.201.22:02:04.19#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:04.19#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:04.19#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.22:02:04.19#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.22:02:04.19$vck44/valo=2,534.99 2006.201.22:02:04.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.22:02:04.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.22:02:04.19#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:04.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:04.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:04.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:04.19#ibcon#enter wrdev, iclass 5, count 0 2006.201.22:02:04.19#ibcon#first serial, iclass 5, count 0 2006.201.22:02:04.19#ibcon#enter sib2, iclass 5, count 0 2006.201.22:02:04.19#ibcon#flushed, iclass 5, count 0 2006.201.22:02:04.19#ibcon#about to write, iclass 5, count 0 2006.201.22:02:04.19#ibcon#wrote, iclass 5, count 0 2006.201.22:02:04.19#ibcon#about to read 3, iclass 5, count 0 2006.201.22:02:04.21#ibcon#read 3, iclass 5, count 0 2006.201.22:02:04.21#ibcon#about to read 4, iclass 5, count 0 2006.201.22:02:04.21#ibcon#read 4, iclass 5, count 0 2006.201.22:02:04.21#ibcon#about to read 5, iclass 5, count 0 2006.201.22:02:04.21#ibcon#read 5, iclass 5, count 0 2006.201.22:02:04.21#ibcon#about to read 6, iclass 5, count 0 2006.201.22:02:04.21#ibcon#read 6, iclass 5, count 0 2006.201.22:02:04.21#ibcon#end of sib2, iclass 5, count 0 2006.201.22:02:04.21#ibcon#*mode == 0, iclass 5, count 0 2006.201.22:02:04.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.22:02:04.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.22:02:04.21#ibcon#*before write, iclass 5, count 0 2006.201.22:02:04.21#ibcon#enter sib2, iclass 5, count 0 2006.201.22:02:04.21#ibcon#flushed, iclass 5, count 0 2006.201.22:02:04.21#ibcon#about to write, iclass 5, count 0 2006.201.22:02:04.21#ibcon#wrote, iclass 5, count 0 2006.201.22:02:04.21#ibcon#about to read 3, iclass 5, count 0 2006.201.22:02:04.26#ibcon#read 3, iclass 5, count 0 2006.201.22:02:04.26#ibcon#about to read 4, iclass 5, count 0 2006.201.22:02:04.26#ibcon#read 4, iclass 5, count 0 2006.201.22:02:04.26#ibcon#about to read 5, iclass 5, count 0 2006.201.22:02:04.26#ibcon#read 5, iclass 5, count 0 2006.201.22:02:04.26#ibcon#about to read 6, iclass 5, count 0 2006.201.22:02:04.26#ibcon#read 6, iclass 5, count 0 2006.201.22:02:04.26#ibcon#end of sib2, iclass 5, count 0 2006.201.22:02:04.26#ibcon#*after write, iclass 5, count 0 2006.201.22:02:04.26#ibcon#*before return 0, iclass 5, count 0 2006.201.22:02:04.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:04.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:04.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.22:02:04.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.22:02:04.26$vck44/va=2,7 2006.201.22:02:04.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.22:02:04.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.22:02:04.26#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:04.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:04.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:04.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:04.31#ibcon#enter wrdev, iclass 7, count 2 2006.201.22:02:04.31#ibcon#first serial, iclass 7, count 2 2006.201.22:02:04.31#ibcon#enter sib2, iclass 7, count 2 2006.201.22:02:04.31#ibcon#flushed, iclass 7, count 2 2006.201.22:02:04.31#ibcon#about to write, iclass 7, count 2 2006.201.22:02:04.31#ibcon#wrote, iclass 7, count 2 2006.201.22:02:04.31#ibcon#about to read 3, iclass 7, count 2 2006.201.22:02:04.33#ibcon#read 3, iclass 7, count 2 2006.201.22:02:04.33#ibcon#about to read 4, iclass 7, count 2 2006.201.22:02:04.33#ibcon#read 4, iclass 7, count 2 2006.201.22:02:04.33#ibcon#about to read 5, iclass 7, count 2 2006.201.22:02:04.33#ibcon#read 5, iclass 7, count 2 2006.201.22:02:04.33#ibcon#about to read 6, iclass 7, count 2 2006.201.22:02:04.33#ibcon#read 6, iclass 7, count 2 2006.201.22:02:04.33#ibcon#end of sib2, iclass 7, count 2 2006.201.22:02:04.33#ibcon#*mode == 0, iclass 7, count 2 2006.201.22:02:04.33#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.22:02:04.33#ibcon#[25=AT02-07\r\n] 2006.201.22:02:04.33#ibcon#*before write, iclass 7, count 2 2006.201.22:02:04.33#ibcon#enter sib2, iclass 7, count 2 2006.201.22:02:04.33#ibcon#flushed, iclass 7, count 2 2006.201.22:02:04.33#ibcon#about to write, iclass 7, count 2 2006.201.22:02:04.33#ibcon#wrote, iclass 7, count 2 2006.201.22:02:04.33#ibcon#about to read 3, iclass 7, count 2 2006.201.22:02:04.36#ibcon#read 3, iclass 7, count 2 2006.201.22:02:04.36#ibcon#about to read 4, iclass 7, count 2 2006.201.22:02:04.36#ibcon#read 4, iclass 7, count 2 2006.201.22:02:04.36#ibcon#about to read 5, iclass 7, count 2 2006.201.22:02:04.36#ibcon#read 5, iclass 7, count 2 2006.201.22:02:04.36#ibcon#about to read 6, iclass 7, count 2 2006.201.22:02:04.36#ibcon#read 6, iclass 7, count 2 2006.201.22:02:04.36#ibcon#end of sib2, iclass 7, count 2 2006.201.22:02:04.36#ibcon#*after write, iclass 7, count 2 2006.201.22:02:04.36#ibcon#*before return 0, iclass 7, count 2 2006.201.22:02:04.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:04.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:04.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.22:02:04.36#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:04.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:04.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:04.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:04.48#ibcon#enter wrdev, iclass 7, count 0 2006.201.22:02:04.48#ibcon#first serial, iclass 7, count 0 2006.201.22:02:04.48#ibcon#enter sib2, iclass 7, count 0 2006.201.22:02:04.48#ibcon#flushed, iclass 7, count 0 2006.201.22:02:04.48#ibcon#about to write, iclass 7, count 0 2006.201.22:02:04.48#ibcon#wrote, iclass 7, count 0 2006.201.22:02:04.48#ibcon#about to read 3, iclass 7, count 0 2006.201.22:02:04.50#ibcon#read 3, iclass 7, count 0 2006.201.22:02:04.50#ibcon#about to read 4, iclass 7, count 0 2006.201.22:02:04.50#ibcon#read 4, iclass 7, count 0 2006.201.22:02:04.50#ibcon#about to read 5, iclass 7, count 0 2006.201.22:02:04.50#ibcon#read 5, iclass 7, count 0 2006.201.22:02:04.50#ibcon#about to read 6, iclass 7, count 0 2006.201.22:02:04.50#ibcon#read 6, iclass 7, count 0 2006.201.22:02:04.50#ibcon#end of sib2, iclass 7, count 0 2006.201.22:02:04.50#ibcon#*mode == 0, iclass 7, count 0 2006.201.22:02:04.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.22:02:04.50#ibcon#[25=USB\r\n] 2006.201.22:02:04.50#ibcon#*before write, iclass 7, count 0 2006.201.22:02:04.50#ibcon#enter sib2, iclass 7, count 0 2006.201.22:02:04.50#ibcon#flushed, iclass 7, count 0 2006.201.22:02:04.50#ibcon#about to write, iclass 7, count 0 2006.201.22:02:04.50#ibcon#wrote, iclass 7, count 0 2006.201.22:02:04.50#ibcon#about to read 3, iclass 7, count 0 2006.201.22:02:04.53#ibcon#read 3, iclass 7, count 0 2006.201.22:02:04.53#ibcon#about to read 4, iclass 7, count 0 2006.201.22:02:04.53#ibcon#read 4, iclass 7, count 0 2006.201.22:02:04.53#ibcon#about to read 5, iclass 7, count 0 2006.201.22:02:04.53#ibcon#read 5, iclass 7, count 0 2006.201.22:02:04.53#ibcon#about to read 6, iclass 7, count 0 2006.201.22:02:04.53#ibcon#read 6, iclass 7, count 0 2006.201.22:02:04.53#ibcon#end of sib2, iclass 7, count 0 2006.201.22:02:04.53#ibcon#*after write, iclass 7, count 0 2006.201.22:02:04.53#ibcon#*before return 0, iclass 7, count 0 2006.201.22:02:04.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:04.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:04.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.22:02:04.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.22:02:04.53$vck44/valo=3,564.99 2006.201.22:02:04.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.22:02:04.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.22:02:04.53#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:04.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:04.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:04.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:04.53#ibcon#enter wrdev, iclass 11, count 0 2006.201.22:02:04.53#ibcon#first serial, iclass 11, count 0 2006.201.22:02:04.53#ibcon#enter sib2, iclass 11, count 0 2006.201.22:02:04.53#ibcon#flushed, iclass 11, count 0 2006.201.22:02:04.53#ibcon#about to write, iclass 11, count 0 2006.201.22:02:04.53#ibcon#wrote, iclass 11, count 0 2006.201.22:02:04.53#ibcon#about to read 3, iclass 11, count 0 2006.201.22:02:04.55#ibcon#read 3, iclass 11, count 0 2006.201.22:02:04.55#ibcon#about to read 4, iclass 11, count 0 2006.201.22:02:04.55#ibcon#read 4, iclass 11, count 0 2006.201.22:02:04.55#ibcon#about to read 5, iclass 11, count 0 2006.201.22:02:04.55#ibcon#read 5, iclass 11, count 0 2006.201.22:02:04.55#ibcon#about to read 6, iclass 11, count 0 2006.201.22:02:04.55#ibcon#read 6, iclass 11, count 0 2006.201.22:02:04.55#ibcon#end of sib2, iclass 11, count 0 2006.201.22:02:04.55#ibcon#*mode == 0, iclass 11, count 0 2006.201.22:02:04.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.22:02:04.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.22:02:04.55#ibcon#*before write, iclass 11, count 0 2006.201.22:02:04.55#ibcon#enter sib2, iclass 11, count 0 2006.201.22:02:04.55#ibcon#flushed, iclass 11, count 0 2006.201.22:02:04.55#ibcon#about to write, iclass 11, count 0 2006.201.22:02:04.55#ibcon#wrote, iclass 11, count 0 2006.201.22:02:04.55#ibcon#about to read 3, iclass 11, count 0 2006.201.22:02:04.60#ibcon#read 3, iclass 11, count 0 2006.201.22:02:04.60#ibcon#about to read 4, iclass 11, count 0 2006.201.22:02:04.60#ibcon#read 4, iclass 11, count 0 2006.201.22:02:04.60#ibcon#about to read 5, iclass 11, count 0 2006.201.22:02:04.60#ibcon#read 5, iclass 11, count 0 2006.201.22:02:04.60#ibcon#about to read 6, iclass 11, count 0 2006.201.22:02:04.60#ibcon#read 6, iclass 11, count 0 2006.201.22:02:04.60#ibcon#end of sib2, iclass 11, count 0 2006.201.22:02:04.60#ibcon#*after write, iclass 11, count 0 2006.201.22:02:04.60#ibcon#*before return 0, iclass 11, count 0 2006.201.22:02:04.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:04.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:04.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.22:02:04.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.22:02:04.60$vck44/va=3,8 2006.201.22:02:04.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.22:02:04.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.22:02:04.60#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:04.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:04.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:04.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:04.65#ibcon#enter wrdev, iclass 13, count 2 2006.201.22:02:04.65#ibcon#first serial, iclass 13, count 2 2006.201.22:02:04.65#ibcon#enter sib2, iclass 13, count 2 2006.201.22:02:04.65#ibcon#flushed, iclass 13, count 2 2006.201.22:02:04.65#ibcon#about to write, iclass 13, count 2 2006.201.22:02:04.65#ibcon#wrote, iclass 13, count 2 2006.201.22:02:04.65#ibcon#about to read 3, iclass 13, count 2 2006.201.22:02:04.67#ibcon#read 3, iclass 13, count 2 2006.201.22:02:04.67#ibcon#about to read 4, iclass 13, count 2 2006.201.22:02:04.67#ibcon#read 4, iclass 13, count 2 2006.201.22:02:04.67#ibcon#about to read 5, iclass 13, count 2 2006.201.22:02:04.67#ibcon#read 5, iclass 13, count 2 2006.201.22:02:04.67#ibcon#about to read 6, iclass 13, count 2 2006.201.22:02:04.67#ibcon#read 6, iclass 13, count 2 2006.201.22:02:04.67#ibcon#end of sib2, iclass 13, count 2 2006.201.22:02:04.67#ibcon#*mode == 0, iclass 13, count 2 2006.201.22:02:04.67#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.22:02:04.67#ibcon#[25=AT03-08\r\n] 2006.201.22:02:04.67#ibcon#*before write, iclass 13, count 2 2006.201.22:02:04.67#ibcon#enter sib2, iclass 13, count 2 2006.201.22:02:04.67#ibcon#flushed, iclass 13, count 2 2006.201.22:02:04.67#ibcon#about to write, iclass 13, count 2 2006.201.22:02:04.67#ibcon#wrote, iclass 13, count 2 2006.201.22:02:04.67#ibcon#about to read 3, iclass 13, count 2 2006.201.22:02:04.70#ibcon#read 3, iclass 13, count 2 2006.201.22:02:04.70#ibcon#about to read 4, iclass 13, count 2 2006.201.22:02:04.70#ibcon#read 4, iclass 13, count 2 2006.201.22:02:04.70#ibcon#about to read 5, iclass 13, count 2 2006.201.22:02:04.70#ibcon#read 5, iclass 13, count 2 2006.201.22:02:04.70#ibcon#about to read 6, iclass 13, count 2 2006.201.22:02:04.70#ibcon#read 6, iclass 13, count 2 2006.201.22:02:04.70#ibcon#end of sib2, iclass 13, count 2 2006.201.22:02:04.70#ibcon#*after write, iclass 13, count 2 2006.201.22:02:04.70#ibcon#*before return 0, iclass 13, count 2 2006.201.22:02:04.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:04.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:04.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.22:02:04.70#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:04.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:04.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:04.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:04.82#ibcon#enter wrdev, iclass 13, count 0 2006.201.22:02:04.82#ibcon#first serial, iclass 13, count 0 2006.201.22:02:04.82#ibcon#enter sib2, iclass 13, count 0 2006.201.22:02:04.82#ibcon#flushed, iclass 13, count 0 2006.201.22:02:04.82#ibcon#about to write, iclass 13, count 0 2006.201.22:02:04.82#ibcon#wrote, iclass 13, count 0 2006.201.22:02:04.82#ibcon#about to read 3, iclass 13, count 0 2006.201.22:02:04.84#ibcon#read 3, iclass 13, count 0 2006.201.22:02:04.84#ibcon#about to read 4, iclass 13, count 0 2006.201.22:02:04.84#ibcon#read 4, iclass 13, count 0 2006.201.22:02:04.84#ibcon#about to read 5, iclass 13, count 0 2006.201.22:02:04.84#ibcon#read 5, iclass 13, count 0 2006.201.22:02:04.84#ibcon#about to read 6, iclass 13, count 0 2006.201.22:02:04.84#ibcon#read 6, iclass 13, count 0 2006.201.22:02:04.84#ibcon#end of sib2, iclass 13, count 0 2006.201.22:02:04.84#ibcon#*mode == 0, iclass 13, count 0 2006.201.22:02:04.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.22:02:04.84#ibcon#[25=USB\r\n] 2006.201.22:02:04.84#ibcon#*before write, iclass 13, count 0 2006.201.22:02:04.84#ibcon#enter sib2, iclass 13, count 0 2006.201.22:02:04.84#ibcon#flushed, iclass 13, count 0 2006.201.22:02:04.84#ibcon#about to write, iclass 13, count 0 2006.201.22:02:04.84#ibcon#wrote, iclass 13, count 0 2006.201.22:02:04.84#ibcon#about to read 3, iclass 13, count 0 2006.201.22:02:04.87#ibcon#read 3, iclass 13, count 0 2006.201.22:02:04.87#ibcon#about to read 4, iclass 13, count 0 2006.201.22:02:04.87#ibcon#read 4, iclass 13, count 0 2006.201.22:02:04.87#ibcon#about to read 5, iclass 13, count 0 2006.201.22:02:04.87#ibcon#read 5, iclass 13, count 0 2006.201.22:02:04.87#ibcon#about to read 6, iclass 13, count 0 2006.201.22:02:04.87#ibcon#read 6, iclass 13, count 0 2006.201.22:02:04.87#ibcon#end of sib2, iclass 13, count 0 2006.201.22:02:04.87#ibcon#*after write, iclass 13, count 0 2006.201.22:02:04.87#ibcon#*before return 0, iclass 13, count 0 2006.201.22:02:04.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:04.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:04.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.22:02:04.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.22:02:04.87$vck44/valo=4,624.99 2006.201.22:02:04.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.22:02:04.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.22:02:04.87#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:04.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:04.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:04.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:04.87#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:02:04.87#ibcon#first serial, iclass 15, count 0 2006.201.22:02:04.87#ibcon#enter sib2, iclass 15, count 0 2006.201.22:02:04.87#ibcon#flushed, iclass 15, count 0 2006.201.22:02:04.87#ibcon#about to write, iclass 15, count 0 2006.201.22:02:04.87#ibcon#wrote, iclass 15, count 0 2006.201.22:02:04.87#ibcon#about to read 3, iclass 15, count 0 2006.201.22:02:04.89#ibcon#read 3, iclass 15, count 0 2006.201.22:02:04.89#ibcon#about to read 4, iclass 15, count 0 2006.201.22:02:04.89#ibcon#read 4, iclass 15, count 0 2006.201.22:02:04.89#ibcon#about to read 5, iclass 15, count 0 2006.201.22:02:04.89#ibcon#read 5, iclass 15, count 0 2006.201.22:02:04.89#ibcon#about to read 6, iclass 15, count 0 2006.201.22:02:04.89#ibcon#read 6, iclass 15, count 0 2006.201.22:02:04.89#ibcon#end of sib2, iclass 15, count 0 2006.201.22:02:04.89#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:02:04.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:02:04.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.22:02:04.89#ibcon#*before write, iclass 15, count 0 2006.201.22:02:04.89#ibcon#enter sib2, iclass 15, count 0 2006.201.22:02:04.89#ibcon#flushed, iclass 15, count 0 2006.201.22:02:04.89#ibcon#about to write, iclass 15, count 0 2006.201.22:02:04.89#ibcon#wrote, iclass 15, count 0 2006.201.22:02:04.89#ibcon#about to read 3, iclass 15, count 0 2006.201.22:02:04.94#ibcon#read 3, iclass 15, count 0 2006.201.22:02:04.94#ibcon#about to read 4, iclass 15, count 0 2006.201.22:02:04.94#ibcon#read 4, iclass 15, count 0 2006.201.22:02:04.94#ibcon#about to read 5, iclass 15, count 0 2006.201.22:02:04.94#ibcon#read 5, iclass 15, count 0 2006.201.22:02:04.94#ibcon#about to read 6, iclass 15, count 0 2006.201.22:02:04.94#ibcon#read 6, iclass 15, count 0 2006.201.22:02:04.94#ibcon#end of sib2, iclass 15, count 0 2006.201.22:02:04.94#ibcon#*after write, iclass 15, count 0 2006.201.22:02:04.94#ibcon#*before return 0, iclass 15, count 0 2006.201.22:02:04.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:04.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:04.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:02:04.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:02:04.94$vck44/va=4,7 2006.201.22:02:04.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.22:02:04.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.22:02:04.94#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:04.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:04.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:04.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:04.99#ibcon#enter wrdev, iclass 17, count 2 2006.201.22:02:04.99#ibcon#first serial, iclass 17, count 2 2006.201.22:02:04.99#ibcon#enter sib2, iclass 17, count 2 2006.201.22:02:04.99#ibcon#flushed, iclass 17, count 2 2006.201.22:02:04.99#ibcon#about to write, iclass 17, count 2 2006.201.22:02:04.99#ibcon#wrote, iclass 17, count 2 2006.201.22:02:04.99#ibcon#about to read 3, iclass 17, count 2 2006.201.22:02:05.01#ibcon#read 3, iclass 17, count 2 2006.201.22:02:05.01#ibcon#about to read 4, iclass 17, count 2 2006.201.22:02:05.01#ibcon#read 4, iclass 17, count 2 2006.201.22:02:05.01#ibcon#about to read 5, iclass 17, count 2 2006.201.22:02:05.01#ibcon#read 5, iclass 17, count 2 2006.201.22:02:05.01#ibcon#about to read 6, iclass 17, count 2 2006.201.22:02:05.01#ibcon#read 6, iclass 17, count 2 2006.201.22:02:05.01#ibcon#end of sib2, iclass 17, count 2 2006.201.22:02:05.01#ibcon#*mode == 0, iclass 17, count 2 2006.201.22:02:05.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.22:02:05.01#ibcon#[25=AT04-07\r\n] 2006.201.22:02:05.01#ibcon#*before write, iclass 17, count 2 2006.201.22:02:05.01#ibcon#enter sib2, iclass 17, count 2 2006.201.22:02:05.01#ibcon#flushed, iclass 17, count 2 2006.201.22:02:05.01#ibcon#about to write, iclass 17, count 2 2006.201.22:02:05.01#ibcon#wrote, iclass 17, count 2 2006.201.22:02:05.01#ibcon#about to read 3, iclass 17, count 2 2006.201.22:02:05.04#ibcon#read 3, iclass 17, count 2 2006.201.22:02:05.04#ibcon#about to read 4, iclass 17, count 2 2006.201.22:02:05.04#ibcon#read 4, iclass 17, count 2 2006.201.22:02:05.04#ibcon#about to read 5, iclass 17, count 2 2006.201.22:02:05.04#ibcon#read 5, iclass 17, count 2 2006.201.22:02:05.04#ibcon#about to read 6, iclass 17, count 2 2006.201.22:02:05.04#ibcon#read 6, iclass 17, count 2 2006.201.22:02:05.04#ibcon#end of sib2, iclass 17, count 2 2006.201.22:02:05.04#ibcon#*after write, iclass 17, count 2 2006.201.22:02:05.04#ibcon#*before return 0, iclass 17, count 2 2006.201.22:02:05.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:05.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:05.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.22:02:05.04#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:05.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:05.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:05.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:05.16#ibcon#enter wrdev, iclass 17, count 0 2006.201.22:02:05.16#ibcon#first serial, iclass 17, count 0 2006.201.22:02:05.16#ibcon#enter sib2, iclass 17, count 0 2006.201.22:02:05.16#ibcon#flushed, iclass 17, count 0 2006.201.22:02:05.16#ibcon#about to write, iclass 17, count 0 2006.201.22:02:05.16#ibcon#wrote, iclass 17, count 0 2006.201.22:02:05.16#ibcon#about to read 3, iclass 17, count 0 2006.201.22:02:05.18#ibcon#read 3, iclass 17, count 0 2006.201.22:02:05.18#ibcon#about to read 4, iclass 17, count 0 2006.201.22:02:05.18#ibcon#read 4, iclass 17, count 0 2006.201.22:02:05.18#ibcon#about to read 5, iclass 17, count 0 2006.201.22:02:05.18#ibcon#read 5, iclass 17, count 0 2006.201.22:02:05.18#ibcon#about to read 6, iclass 17, count 0 2006.201.22:02:05.18#ibcon#read 6, iclass 17, count 0 2006.201.22:02:05.18#ibcon#end of sib2, iclass 17, count 0 2006.201.22:02:05.18#ibcon#*mode == 0, iclass 17, count 0 2006.201.22:02:05.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.22:02:05.18#ibcon#[25=USB\r\n] 2006.201.22:02:05.18#ibcon#*before write, iclass 17, count 0 2006.201.22:02:05.18#ibcon#enter sib2, iclass 17, count 0 2006.201.22:02:05.18#ibcon#flushed, iclass 17, count 0 2006.201.22:02:05.18#ibcon#about to write, iclass 17, count 0 2006.201.22:02:05.18#ibcon#wrote, iclass 17, count 0 2006.201.22:02:05.18#ibcon#about to read 3, iclass 17, count 0 2006.201.22:02:05.21#ibcon#read 3, iclass 17, count 0 2006.201.22:02:05.21#ibcon#about to read 4, iclass 17, count 0 2006.201.22:02:05.21#ibcon#read 4, iclass 17, count 0 2006.201.22:02:05.21#ibcon#about to read 5, iclass 17, count 0 2006.201.22:02:05.21#ibcon#read 5, iclass 17, count 0 2006.201.22:02:05.21#ibcon#about to read 6, iclass 17, count 0 2006.201.22:02:05.21#ibcon#read 6, iclass 17, count 0 2006.201.22:02:05.21#ibcon#end of sib2, iclass 17, count 0 2006.201.22:02:05.21#ibcon#*after write, iclass 17, count 0 2006.201.22:02:05.21#ibcon#*before return 0, iclass 17, count 0 2006.201.22:02:05.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:05.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:05.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.22:02:05.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.22:02:05.21$vck44/valo=5,734.99 2006.201.22:02:05.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.22:02:05.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.22:02:05.21#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:05.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:05.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:05.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:05.21#ibcon#enter wrdev, iclass 19, count 0 2006.201.22:02:05.21#ibcon#first serial, iclass 19, count 0 2006.201.22:02:05.21#ibcon#enter sib2, iclass 19, count 0 2006.201.22:02:05.21#ibcon#flushed, iclass 19, count 0 2006.201.22:02:05.21#ibcon#about to write, iclass 19, count 0 2006.201.22:02:05.21#ibcon#wrote, iclass 19, count 0 2006.201.22:02:05.21#ibcon#about to read 3, iclass 19, count 0 2006.201.22:02:05.23#ibcon#read 3, iclass 19, count 0 2006.201.22:02:05.23#ibcon#about to read 4, iclass 19, count 0 2006.201.22:02:05.23#ibcon#read 4, iclass 19, count 0 2006.201.22:02:05.23#ibcon#about to read 5, iclass 19, count 0 2006.201.22:02:05.23#ibcon#read 5, iclass 19, count 0 2006.201.22:02:05.23#ibcon#about to read 6, iclass 19, count 0 2006.201.22:02:05.23#ibcon#read 6, iclass 19, count 0 2006.201.22:02:05.23#ibcon#end of sib2, iclass 19, count 0 2006.201.22:02:05.23#ibcon#*mode == 0, iclass 19, count 0 2006.201.22:02:05.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.22:02:05.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.22:02:05.23#ibcon#*before write, iclass 19, count 0 2006.201.22:02:05.23#ibcon#enter sib2, iclass 19, count 0 2006.201.22:02:05.23#ibcon#flushed, iclass 19, count 0 2006.201.22:02:05.23#ibcon#about to write, iclass 19, count 0 2006.201.22:02:05.23#ibcon#wrote, iclass 19, count 0 2006.201.22:02:05.23#ibcon#about to read 3, iclass 19, count 0 2006.201.22:02:05.27#ibcon#read 3, iclass 19, count 0 2006.201.22:02:05.27#ibcon#about to read 4, iclass 19, count 0 2006.201.22:02:05.27#ibcon#read 4, iclass 19, count 0 2006.201.22:02:05.27#ibcon#about to read 5, iclass 19, count 0 2006.201.22:02:05.27#ibcon#read 5, iclass 19, count 0 2006.201.22:02:05.27#ibcon#about to read 6, iclass 19, count 0 2006.201.22:02:05.27#ibcon#read 6, iclass 19, count 0 2006.201.22:02:05.27#ibcon#end of sib2, iclass 19, count 0 2006.201.22:02:05.27#ibcon#*after write, iclass 19, count 0 2006.201.22:02:05.27#ibcon#*before return 0, iclass 19, count 0 2006.201.22:02:05.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:05.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:05.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.22:02:05.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.22:02:05.27$vck44/va=5,4 2006.201.22:02:05.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.22:02:05.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.22:02:05.27#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:05.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:05.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:05.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:05.33#ibcon#enter wrdev, iclass 21, count 2 2006.201.22:02:05.33#ibcon#first serial, iclass 21, count 2 2006.201.22:02:05.33#ibcon#enter sib2, iclass 21, count 2 2006.201.22:02:05.33#ibcon#flushed, iclass 21, count 2 2006.201.22:02:05.33#ibcon#about to write, iclass 21, count 2 2006.201.22:02:05.33#ibcon#wrote, iclass 21, count 2 2006.201.22:02:05.33#ibcon#about to read 3, iclass 21, count 2 2006.201.22:02:05.35#ibcon#read 3, iclass 21, count 2 2006.201.22:02:05.35#ibcon#about to read 4, iclass 21, count 2 2006.201.22:02:05.35#ibcon#read 4, iclass 21, count 2 2006.201.22:02:05.35#ibcon#about to read 5, iclass 21, count 2 2006.201.22:02:05.35#ibcon#read 5, iclass 21, count 2 2006.201.22:02:05.35#ibcon#about to read 6, iclass 21, count 2 2006.201.22:02:05.35#ibcon#read 6, iclass 21, count 2 2006.201.22:02:05.35#ibcon#end of sib2, iclass 21, count 2 2006.201.22:02:05.35#ibcon#*mode == 0, iclass 21, count 2 2006.201.22:02:05.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.22:02:05.35#ibcon#[25=AT05-04\r\n] 2006.201.22:02:05.35#ibcon#*before write, iclass 21, count 2 2006.201.22:02:05.35#ibcon#enter sib2, iclass 21, count 2 2006.201.22:02:05.35#ibcon#flushed, iclass 21, count 2 2006.201.22:02:05.35#ibcon#about to write, iclass 21, count 2 2006.201.22:02:05.35#ibcon#wrote, iclass 21, count 2 2006.201.22:02:05.35#ibcon#about to read 3, iclass 21, count 2 2006.201.22:02:05.38#ibcon#read 3, iclass 21, count 2 2006.201.22:02:05.38#ibcon#about to read 4, iclass 21, count 2 2006.201.22:02:05.38#ibcon#read 4, iclass 21, count 2 2006.201.22:02:05.38#ibcon#about to read 5, iclass 21, count 2 2006.201.22:02:05.38#ibcon#read 5, iclass 21, count 2 2006.201.22:02:05.38#ibcon#about to read 6, iclass 21, count 2 2006.201.22:02:05.38#ibcon#read 6, iclass 21, count 2 2006.201.22:02:05.38#ibcon#end of sib2, iclass 21, count 2 2006.201.22:02:05.38#ibcon#*after write, iclass 21, count 2 2006.201.22:02:05.38#ibcon#*before return 0, iclass 21, count 2 2006.201.22:02:05.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:05.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:05.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.22:02:05.38#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:05.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:05.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:05.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:05.50#ibcon#enter wrdev, iclass 21, count 0 2006.201.22:02:05.50#ibcon#first serial, iclass 21, count 0 2006.201.22:02:05.50#ibcon#enter sib2, iclass 21, count 0 2006.201.22:02:05.50#ibcon#flushed, iclass 21, count 0 2006.201.22:02:05.50#ibcon#about to write, iclass 21, count 0 2006.201.22:02:05.50#ibcon#wrote, iclass 21, count 0 2006.201.22:02:05.50#ibcon#about to read 3, iclass 21, count 0 2006.201.22:02:05.52#ibcon#read 3, iclass 21, count 0 2006.201.22:02:05.52#ibcon#about to read 4, iclass 21, count 0 2006.201.22:02:05.52#ibcon#read 4, iclass 21, count 0 2006.201.22:02:05.52#ibcon#about to read 5, iclass 21, count 0 2006.201.22:02:05.52#ibcon#read 5, iclass 21, count 0 2006.201.22:02:05.52#ibcon#about to read 6, iclass 21, count 0 2006.201.22:02:05.52#ibcon#read 6, iclass 21, count 0 2006.201.22:02:05.52#ibcon#end of sib2, iclass 21, count 0 2006.201.22:02:05.52#ibcon#*mode == 0, iclass 21, count 0 2006.201.22:02:05.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.22:02:05.52#ibcon#[25=USB\r\n] 2006.201.22:02:05.52#ibcon#*before write, iclass 21, count 0 2006.201.22:02:05.52#ibcon#enter sib2, iclass 21, count 0 2006.201.22:02:05.52#ibcon#flushed, iclass 21, count 0 2006.201.22:02:05.52#ibcon#about to write, iclass 21, count 0 2006.201.22:02:05.52#ibcon#wrote, iclass 21, count 0 2006.201.22:02:05.52#ibcon#about to read 3, iclass 21, count 0 2006.201.22:02:05.55#ibcon#read 3, iclass 21, count 0 2006.201.22:02:05.55#ibcon#about to read 4, iclass 21, count 0 2006.201.22:02:05.55#ibcon#read 4, iclass 21, count 0 2006.201.22:02:05.55#ibcon#about to read 5, iclass 21, count 0 2006.201.22:02:05.55#ibcon#read 5, iclass 21, count 0 2006.201.22:02:05.55#ibcon#about to read 6, iclass 21, count 0 2006.201.22:02:05.55#ibcon#read 6, iclass 21, count 0 2006.201.22:02:05.55#ibcon#end of sib2, iclass 21, count 0 2006.201.22:02:05.55#ibcon#*after write, iclass 21, count 0 2006.201.22:02:05.55#ibcon#*before return 0, iclass 21, count 0 2006.201.22:02:05.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:05.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:05.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.22:02:05.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.22:02:05.55$vck44/valo=6,814.99 2006.201.22:02:05.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.22:02:05.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.22:02:05.55#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:05.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:05.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:05.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:05.55#ibcon#enter wrdev, iclass 23, count 0 2006.201.22:02:05.55#ibcon#first serial, iclass 23, count 0 2006.201.22:02:05.55#ibcon#enter sib2, iclass 23, count 0 2006.201.22:02:05.55#ibcon#flushed, iclass 23, count 0 2006.201.22:02:05.55#ibcon#about to write, iclass 23, count 0 2006.201.22:02:05.55#ibcon#wrote, iclass 23, count 0 2006.201.22:02:05.55#ibcon#about to read 3, iclass 23, count 0 2006.201.22:02:05.57#ibcon#read 3, iclass 23, count 0 2006.201.22:02:05.57#ibcon#about to read 4, iclass 23, count 0 2006.201.22:02:05.57#ibcon#read 4, iclass 23, count 0 2006.201.22:02:05.57#ibcon#about to read 5, iclass 23, count 0 2006.201.22:02:05.57#ibcon#read 5, iclass 23, count 0 2006.201.22:02:05.57#ibcon#about to read 6, iclass 23, count 0 2006.201.22:02:05.57#ibcon#read 6, iclass 23, count 0 2006.201.22:02:05.57#ibcon#end of sib2, iclass 23, count 0 2006.201.22:02:05.57#ibcon#*mode == 0, iclass 23, count 0 2006.201.22:02:05.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.22:02:05.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.22:02:05.57#ibcon#*before write, iclass 23, count 0 2006.201.22:02:05.57#ibcon#enter sib2, iclass 23, count 0 2006.201.22:02:05.57#ibcon#flushed, iclass 23, count 0 2006.201.22:02:05.57#ibcon#about to write, iclass 23, count 0 2006.201.22:02:05.57#ibcon#wrote, iclass 23, count 0 2006.201.22:02:05.57#ibcon#about to read 3, iclass 23, count 0 2006.201.22:02:05.62#ibcon#read 3, iclass 23, count 0 2006.201.22:02:05.62#ibcon#about to read 4, iclass 23, count 0 2006.201.22:02:05.62#ibcon#read 4, iclass 23, count 0 2006.201.22:02:05.62#ibcon#about to read 5, iclass 23, count 0 2006.201.22:02:05.62#ibcon#read 5, iclass 23, count 0 2006.201.22:02:05.62#ibcon#about to read 6, iclass 23, count 0 2006.201.22:02:05.62#ibcon#read 6, iclass 23, count 0 2006.201.22:02:05.62#ibcon#end of sib2, iclass 23, count 0 2006.201.22:02:05.62#ibcon#*after write, iclass 23, count 0 2006.201.22:02:05.62#ibcon#*before return 0, iclass 23, count 0 2006.201.22:02:05.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:05.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:05.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.22:02:05.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.22:02:05.62$vck44/va=6,5 2006.201.22:02:05.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.22:02:05.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.22:02:05.62#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:05.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:05.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:05.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:05.67#ibcon#enter wrdev, iclass 25, count 2 2006.201.22:02:05.67#ibcon#first serial, iclass 25, count 2 2006.201.22:02:05.67#ibcon#enter sib2, iclass 25, count 2 2006.201.22:02:05.67#ibcon#flushed, iclass 25, count 2 2006.201.22:02:05.67#ibcon#about to write, iclass 25, count 2 2006.201.22:02:05.67#ibcon#wrote, iclass 25, count 2 2006.201.22:02:05.67#ibcon#about to read 3, iclass 25, count 2 2006.201.22:02:05.69#ibcon#read 3, iclass 25, count 2 2006.201.22:02:05.69#ibcon#about to read 4, iclass 25, count 2 2006.201.22:02:05.69#ibcon#read 4, iclass 25, count 2 2006.201.22:02:05.69#ibcon#about to read 5, iclass 25, count 2 2006.201.22:02:05.69#ibcon#read 5, iclass 25, count 2 2006.201.22:02:05.69#ibcon#about to read 6, iclass 25, count 2 2006.201.22:02:05.69#ibcon#read 6, iclass 25, count 2 2006.201.22:02:05.69#ibcon#end of sib2, iclass 25, count 2 2006.201.22:02:05.69#ibcon#*mode == 0, iclass 25, count 2 2006.201.22:02:05.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.22:02:05.69#ibcon#[25=AT06-05\r\n] 2006.201.22:02:05.69#ibcon#*before write, iclass 25, count 2 2006.201.22:02:05.69#ibcon#enter sib2, iclass 25, count 2 2006.201.22:02:05.69#ibcon#flushed, iclass 25, count 2 2006.201.22:02:05.69#ibcon#about to write, iclass 25, count 2 2006.201.22:02:05.69#ibcon#wrote, iclass 25, count 2 2006.201.22:02:05.69#ibcon#about to read 3, iclass 25, count 2 2006.201.22:02:05.72#ibcon#read 3, iclass 25, count 2 2006.201.22:02:05.72#ibcon#about to read 4, iclass 25, count 2 2006.201.22:02:05.72#ibcon#read 4, iclass 25, count 2 2006.201.22:02:05.72#ibcon#about to read 5, iclass 25, count 2 2006.201.22:02:05.72#ibcon#read 5, iclass 25, count 2 2006.201.22:02:05.72#ibcon#about to read 6, iclass 25, count 2 2006.201.22:02:05.72#ibcon#read 6, iclass 25, count 2 2006.201.22:02:05.72#ibcon#end of sib2, iclass 25, count 2 2006.201.22:02:05.72#ibcon#*after write, iclass 25, count 2 2006.201.22:02:05.72#ibcon#*before return 0, iclass 25, count 2 2006.201.22:02:05.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:05.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:05.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.22:02:05.72#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:05.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:05.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:05.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:05.84#ibcon#enter wrdev, iclass 25, count 0 2006.201.22:02:05.84#ibcon#first serial, iclass 25, count 0 2006.201.22:02:05.84#ibcon#enter sib2, iclass 25, count 0 2006.201.22:02:05.84#ibcon#flushed, iclass 25, count 0 2006.201.22:02:05.84#ibcon#about to write, iclass 25, count 0 2006.201.22:02:05.84#ibcon#wrote, iclass 25, count 0 2006.201.22:02:05.84#ibcon#about to read 3, iclass 25, count 0 2006.201.22:02:05.86#ibcon#read 3, iclass 25, count 0 2006.201.22:02:05.86#ibcon#about to read 4, iclass 25, count 0 2006.201.22:02:05.86#ibcon#read 4, iclass 25, count 0 2006.201.22:02:05.86#ibcon#about to read 5, iclass 25, count 0 2006.201.22:02:05.86#ibcon#read 5, iclass 25, count 0 2006.201.22:02:05.86#ibcon#about to read 6, iclass 25, count 0 2006.201.22:02:05.86#ibcon#read 6, iclass 25, count 0 2006.201.22:02:05.86#ibcon#end of sib2, iclass 25, count 0 2006.201.22:02:05.86#ibcon#*mode == 0, iclass 25, count 0 2006.201.22:02:05.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.22:02:05.86#ibcon#[25=USB\r\n] 2006.201.22:02:05.86#ibcon#*before write, iclass 25, count 0 2006.201.22:02:05.86#ibcon#enter sib2, iclass 25, count 0 2006.201.22:02:05.86#ibcon#flushed, iclass 25, count 0 2006.201.22:02:05.86#ibcon#about to write, iclass 25, count 0 2006.201.22:02:05.86#ibcon#wrote, iclass 25, count 0 2006.201.22:02:05.86#ibcon#about to read 3, iclass 25, count 0 2006.201.22:02:05.89#ibcon#read 3, iclass 25, count 0 2006.201.22:02:05.89#ibcon#about to read 4, iclass 25, count 0 2006.201.22:02:05.89#ibcon#read 4, iclass 25, count 0 2006.201.22:02:05.89#ibcon#about to read 5, iclass 25, count 0 2006.201.22:02:05.89#ibcon#read 5, iclass 25, count 0 2006.201.22:02:05.89#ibcon#about to read 6, iclass 25, count 0 2006.201.22:02:05.89#ibcon#read 6, iclass 25, count 0 2006.201.22:02:05.89#ibcon#end of sib2, iclass 25, count 0 2006.201.22:02:05.89#ibcon#*after write, iclass 25, count 0 2006.201.22:02:05.89#ibcon#*before return 0, iclass 25, count 0 2006.201.22:02:05.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:05.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:05.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.22:02:05.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.22:02:05.89$vck44/valo=7,864.99 2006.201.22:02:05.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.22:02:05.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.22:02:05.89#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:05.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:05.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:05.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:05.89#ibcon#enter wrdev, iclass 27, count 0 2006.201.22:02:05.89#ibcon#first serial, iclass 27, count 0 2006.201.22:02:05.89#ibcon#enter sib2, iclass 27, count 0 2006.201.22:02:05.89#ibcon#flushed, iclass 27, count 0 2006.201.22:02:05.89#ibcon#about to write, iclass 27, count 0 2006.201.22:02:05.89#ibcon#wrote, iclass 27, count 0 2006.201.22:02:05.89#ibcon#about to read 3, iclass 27, count 0 2006.201.22:02:05.91#ibcon#read 3, iclass 27, count 0 2006.201.22:02:05.91#ibcon#about to read 4, iclass 27, count 0 2006.201.22:02:05.91#ibcon#read 4, iclass 27, count 0 2006.201.22:02:05.91#ibcon#about to read 5, iclass 27, count 0 2006.201.22:02:05.91#ibcon#read 5, iclass 27, count 0 2006.201.22:02:05.91#ibcon#about to read 6, iclass 27, count 0 2006.201.22:02:05.91#ibcon#read 6, iclass 27, count 0 2006.201.22:02:05.91#ibcon#end of sib2, iclass 27, count 0 2006.201.22:02:05.91#ibcon#*mode == 0, iclass 27, count 0 2006.201.22:02:05.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.22:02:05.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.22:02:05.91#ibcon#*before write, iclass 27, count 0 2006.201.22:02:05.91#ibcon#enter sib2, iclass 27, count 0 2006.201.22:02:05.91#ibcon#flushed, iclass 27, count 0 2006.201.22:02:05.91#ibcon#about to write, iclass 27, count 0 2006.201.22:02:05.91#ibcon#wrote, iclass 27, count 0 2006.201.22:02:05.91#ibcon#about to read 3, iclass 27, count 0 2006.201.22:02:05.95#ibcon#read 3, iclass 27, count 0 2006.201.22:02:05.95#ibcon#about to read 4, iclass 27, count 0 2006.201.22:02:05.95#ibcon#read 4, iclass 27, count 0 2006.201.22:02:05.95#ibcon#about to read 5, iclass 27, count 0 2006.201.22:02:05.95#ibcon#read 5, iclass 27, count 0 2006.201.22:02:05.95#ibcon#about to read 6, iclass 27, count 0 2006.201.22:02:05.95#ibcon#read 6, iclass 27, count 0 2006.201.22:02:05.95#ibcon#end of sib2, iclass 27, count 0 2006.201.22:02:05.95#ibcon#*after write, iclass 27, count 0 2006.201.22:02:05.95#ibcon#*before return 0, iclass 27, count 0 2006.201.22:02:05.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:05.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:05.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.22:02:05.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.22:02:05.95$vck44/va=7,5 2006.201.22:02:05.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.22:02:05.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.22:02:05.95#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:05.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:06.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:06.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:06.01#ibcon#enter wrdev, iclass 29, count 2 2006.201.22:02:06.01#ibcon#first serial, iclass 29, count 2 2006.201.22:02:06.01#ibcon#enter sib2, iclass 29, count 2 2006.201.22:02:06.01#ibcon#flushed, iclass 29, count 2 2006.201.22:02:06.01#ibcon#about to write, iclass 29, count 2 2006.201.22:02:06.01#ibcon#wrote, iclass 29, count 2 2006.201.22:02:06.01#ibcon#about to read 3, iclass 29, count 2 2006.201.22:02:06.03#ibcon#read 3, iclass 29, count 2 2006.201.22:02:06.03#ibcon#about to read 4, iclass 29, count 2 2006.201.22:02:06.03#ibcon#read 4, iclass 29, count 2 2006.201.22:02:06.03#ibcon#about to read 5, iclass 29, count 2 2006.201.22:02:06.03#ibcon#read 5, iclass 29, count 2 2006.201.22:02:06.03#ibcon#about to read 6, iclass 29, count 2 2006.201.22:02:06.03#ibcon#read 6, iclass 29, count 2 2006.201.22:02:06.03#ibcon#end of sib2, iclass 29, count 2 2006.201.22:02:06.03#ibcon#*mode == 0, iclass 29, count 2 2006.201.22:02:06.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.22:02:06.03#ibcon#[25=AT07-05\r\n] 2006.201.22:02:06.03#ibcon#*before write, iclass 29, count 2 2006.201.22:02:06.03#ibcon#enter sib2, iclass 29, count 2 2006.201.22:02:06.03#ibcon#flushed, iclass 29, count 2 2006.201.22:02:06.03#ibcon#about to write, iclass 29, count 2 2006.201.22:02:06.03#ibcon#wrote, iclass 29, count 2 2006.201.22:02:06.03#ibcon#about to read 3, iclass 29, count 2 2006.201.22:02:06.06#ibcon#read 3, iclass 29, count 2 2006.201.22:02:06.06#ibcon#about to read 4, iclass 29, count 2 2006.201.22:02:06.06#ibcon#read 4, iclass 29, count 2 2006.201.22:02:06.06#ibcon#about to read 5, iclass 29, count 2 2006.201.22:02:06.06#ibcon#read 5, iclass 29, count 2 2006.201.22:02:06.06#ibcon#about to read 6, iclass 29, count 2 2006.201.22:02:06.06#ibcon#read 6, iclass 29, count 2 2006.201.22:02:06.06#ibcon#end of sib2, iclass 29, count 2 2006.201.22:02:06.06#ibcon#*after write, iclass 29, count 2 2006.201.22:02:06.06#ibcon#*before return 0, iclass 29, count 2 2006.201.22:02:06.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:06.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:06.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.22:02:06.06#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:06.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:06.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:06.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:06.18#ibcon#enter wrdev, iclass 29, count 0 2006.201.22:02:06.18#ibcon#first serial, iclass 29, count 0 2006.201.22:02:06.18#ibcon#enter sib2, iclass 29, count 0 2006.201.22:02:06.18#ibcon#flushed, iclass 29, count 0 2006.201.22:02:06.18#ibcon#about to write, iclass 29, count 0 2006.201.22:02:06.18#ibcon#wrote, iclass 29, count 0 2006.201.22:02:06.18#ibcon#about to read 3, iclass 29, count 0 2006.201.22:02:06.20#ibcon#read 3, iclass 29, count 0 2006.201.22:02:06.20#ibcon#about to read 4, iclass 29, count 0 2006.201.22:02:06.20#ibcon#read 4, iclass 29, count 0 2006.201.22:02:06.20#ibcon#about to read 5, iclass 29, count 0 2006.201.22:02:06.20#ibcon#read 5, iclass 29, count 0 2006.201.22:02:06.20#ibcon#about to read 6, iclass 29, count 0 2006.201.22:02:06.20#ibcon#read 6, iclass 29, count 0 2006.201.22:02:06.20#ibcon#end of sib2, iclass 29, count 0 2006.201.22:02:06.20#ibcon#*mode == 0, iclass 29, count 0 2006.201.22:02:06.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.22:02:06.20#ibcon#[25=USB\r\n] 2006.201.22:02:06.20#ibcon#*before write, iclass 29, count 0 2006.201.22:02:06.20#ibcon#enter sib2, iclass 29, count 0 2006.201.22:02:06.20#ibcon#flushed, iclass 29, count 0 2006.201.22:02:06.20#ibcon#about to write, iclass 29, count 0 2006.201.22:02:06.20#ibcon#wrote, iclass 29, count 0 2006.201.22:02:06.20#ibcon#about to read 3, iclass 29, count 0 2006.201.22:02:06.23#ibcon#read 3, iclass 29, count 0 2006.201.22:02:06.23#ibcon#about to read 4, iclass 29, count 0 2006.201.22:02:06.23#ibcon#read 4, iclass 29, count 0 2006.201.22:02:06.23#ibcon#about to read 5, iclass 29, count 0 2006.201.22:02:06.23#ibcon#read 5, iclass 29, count 0 2006.201.22:02:06.23#ibcon#about to read 6, iclass 29, count 0 2006.201.22:02:06.23#ibcon#read 6, iclass 29, count 0 2006.201.22:02:06.23#ibcon#end of sib2, iclass 29, count 0 2006.201.22:02:06.23#ibcon#*after write, iclass 29, count 0 2006.201.22:02:06.23#ibcon#*before return 0, iclass 29, count 0 2006.201.22:02:06.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:06.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:06.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.22:02:06.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.22:02:06.23$vck44/valo=8,884.99 2006.201.22:02:06.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.22:02:06.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.22:02:06.23#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:06.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:06.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:06.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:06.23#ibcon#enter wrdev, iclass 31, count 0 2006.201.22:02:06.23#ibcon#first serial, iclass 31, count 0 2006.201.22:02:06.23#ibcon#enter sib2, iclass 31, count 0 2006.201.22:02:06.23#ibcon#flushed, iclass 31, count 0 2006.201.22:02:06.23#ibcon#about to write, iclass 31, count 0 2006.201.22:02:06.23#ibcon#wrote, iclass 31, count 0 2006.201.22:02:06.23#ibcon#about to read 3, iclass 31, count 0 2006.201.22:02:06.25#ibcon#read 3, iclass 31, count 0 2006.201.22:02:06.25#ibcon#about to read 4, iclass 31, count 0 2006.201.22:02:06.25#ibcon#read 4, iclass 31, count 0 2006.201.22:02:06.25#ibcon#about to read 5, iclass 31, count 0 2006.201.22:02:06.25#ibcon#read 5, iclass 31, count 0 2006.201.22:02:06.25#ibcon#about to read 6, iclass 31, count 0 2006.201.22:02:06.25#ibcon#read 6, iclass 31, count 0 2006.201.22:02:06.25#ibcon#end of sib2, iclass 31, count 0 2006.201.22:02:06.25#ibcon#*mode == 0, iclass 31, count 0 2006.201.22:02:06.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.22:02:06.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.22:02:06.25#ibcon#*before write, iclass 31, count 0 2006.201.22:02:06.25#ibcon#enter sib2, iclass 31, count 0 2006.201.22:02:06.25#ibcon#flushed, iclass 31, count 0 2006.201.22:02:06.25#ibcon#about to write, iclass 31, count 0 2006.201.22:02:06.25#ibcon#wrote, iclass 31, count 0 2006.201.22:02:06.25#ibcon#about to read 3, iclass 31, count 0 2006.201.22:02:06.29#ibcon#read 3, iclass 31, count 0 2006.201.22:02:06.29#ibcon#about to read 4, iclass 31, count 0 2006.201.22:02:06.29#ibcon#read 4, iclass 31, count 0 2006.201.22:02:06.29#ibcon#about to read 5, iclass 31, count 0 2006.201.22:02:06.29#ibcon#read 5, iclass 31, count 0 2006.201.22:02:06.29#ibcon#about to read 6, iclass 31, count 0 2006.201.22:02:06.29#ibcon#read 6, iclass 31, count 0 2006.201.22:02:06.29#ibcon#end of sib2, iclass 31, count 0 2006.201.22:02:06.29#ibcon#*after write, iclass 31, count 0 2006.201.22:02:06.29#ibcon#*before return 0, iclass 31, count 0 2006.201.22:02:06.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:06.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:06.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.22:02:06.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.22:02:06.29$vck44/va=8,4 2006.201.22:02:06.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.22:02:06.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.22:02:06.29#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:06.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:02:06.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:02:06.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:02:06.35#ibcon#enter wrdev, iclass 33, count 2 2006.201.22:02:06.35#ibcon#first serial, iclass 33, count 2 2006.201.22:02:06.35#ibcon#enter sib2, iclass 33, count 2 2006.201.22:02:06.35#ibcon#flushed, iclass 33, count 2 2006.201.22:02:06.35#ibcon#about to write, iclass 33, count 2 2006.201.22:02:06.35#ibcon#wrote, iclass 33, count 2 2006.201.22:02:06.35#ibcon#about to read 3, iclass 33, count 2 2006.201.22:02:06.37#ibcon#read 3, iclass 33, count 2 2006.201.22:02:06.37#ibcon#about to read 4, iclass 33, count 2 2006.201.22:02:06.37#ibcon#read 4, iclass 33, count 2 2006.201.22:02:06.37#ibcon#about to read 5, iclass 33, count 2 2006.201.22:02:06.37#ibcon#read 5, iclass 33, count 2 2006.201.22:02:06.37#ibcon#about to read 6, iclass 33, count 2 2006.201.22:02:06.37#ibcon#read 6, iclass 33, count 2 2006.201.22:02:06.37#ibcon#end of sib2, iclass 33, count 2 2006.201.22:02:06.37#ibcon#*mode == 0, iclass 33, count 2 2006.201.22:02:06.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.22:02:06.37#ibcon#[25=AT08-04\r\n] 2006.201.22:02:06.37#ibcon#*before write, iclass 33, count 2 2006.201.22:02:06.37#ibcon#enter sib2, iclass 33, count 2 2006.201.22:02:06.37#ibcon#flushed, iclass 33, count 2 2006.201.22:02:06.37#ibcon#about to write, iclass 33, count 2 2006.201.22:02:06.37#ibcon#wrote, iclass 33, count 2 2006.201.22:02:06.37#ibcon#about to read 3, iclass 33, count 2 2006.201.22:02:06.40#ibcon#read 3, iclass 33, count 2 2006.201.22:02:06.40#ibcon#about to read 4, iclass 33, count 2 2006.201.22:02:06.40#ibcon#read 4, iclass 33, count 2 2006.201.22:02:06.40#ibcon#about to read 5, iclass 33, count 2 2006.201.22:02:06.40#ibcon#read 5, iclass 33, count 2 2006.201.22:02:06.40#ibcon#about to read 6, iclass 33, count 2 2006.201.22:02:06.40#ibcon#read 6, iclass 33, count 2 2006.201.22:02:06.40#ibcon#end of sib2, iclass 33, count 2 2006.201.22:02:06.40#ibcon#*after write, iclass 33, count 2 2006.201.22:02:06.40#ibcon#*before return 0, iclass 33, count 2 2006.201.22:02:06.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:02:06.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:02:06.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.22:02:06.40#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:06.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:02:06.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:02:06.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:02:06.52#ibcon#enter wrdev, iclass 33, count 0 2006.201.22:02:06.52#ibcon#first serial, iclass 33, count 0 2006.201.22:02:06.52#ibcon#enter sib2, iclass 33, count 0 2006.201.22:02:06.52#ibcon#flushed, iclass 33, count 0 2006.201.22:02:06.52#ibcon#about to write, iclass 33, count 0 2006.201.22:02:06.52#ibcon#wrote, iclass 33, count 0 2006.201.22:02:06.52#ibcon#about to read 3, iclass 33, count 0 2006.201.22:02:06.54#ibcon#read 3, iclass 33, count 0 2006.201.22:02:06.54#ibcon#about to read 4, iclass 33, count 0 2006.201.22:02:06.54#ibcon#read 4, iclass 33, count 0 2006.201.22:02:06.54#ibcon#about to read 5, iclass 33, count 0 2006.201.22:02:06.54#ibcon#read 5, iclass 33, count 0 2006.201.22:02:06.54#ibcon#about to read 6, iclass 33, count 0 2006.201.22:02:06.54#ibcon#read 6, iclass 33, count 0 2006.201.22:02:06.54#ibcon#end of sib2, iclass 33, count 0 2006.201.22:02:06.54#ibcon#*mode == 0, iclass 33, count 0 2006.201.22:02:06.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.22:02:06.54#ibcon#[25=USB\r\n] 2006.201.22:02:06.54#ibcon#*before write, iclass 33, count 0 2006.201.22:02:06.54#ibcon#enter sib2, iclass 33, count 0 2006.201.22:02:06.54#ibcon#flushed, iclass 33, count 0 2006.201.22:02:06.54#ibcon#about to write, iclass 33, count 0 2006.201.22:02:06.54#ibcon#wrote, iclass 33, count 0 2006.201.22:02:06.54#ibcon#about to read 3, iclass 33, count 0 2006.201.22:02:06.57#ibcon#read 3, iclass 33, count 0 2006.201.22:02:06.57#ibcon#about to read 4, iclass 33, count 0 2006.201.22:02:06.57#ibcon#read 4, iclass 33, count 0 2006.201.22:02:06.57#ibcon#about to read 5, iclass 33, count 0 2006.201.22:02:06.57#ibcon#read 5, iclass 33, count 0 2006.201.22:02:06.57#ibcon#about to read 6, iclass 33, count 0 2006.201.22:02:06.57#ibcon#read 6, iclass 33, count 0 2006.201.22:02:06.57#ibcon#end of sib2, iclass 33, count 0 2006.201.22:02:06.57#ibcon#*after write, iclass 33, count 0 2006.201.22:02:06.57#ibcon#*before return 0, iclass 33, count 0 2006.201.22:02:06.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:02:06.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:02:06.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.22:02:06.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.22:02:06.57$vck44/vblo=1,629.99 2006.201.22:02:06.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.22:02:06.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.22:02:06.57#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:06.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:02:06.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:02:06.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:02:06.57#ibcon#enter wrdev, iclass 35, count 0 2006.201.22:02:06.57#ibcon#first serial, iclass 35, count 0 2006.201.22:02:06.57#ibcon#enter sib2, iclass 35, count 0 2006.201.22:02:06.57#ibcon#flushed, iclass 35, count 0 2006.201.22:02:06.57#ibcon#about to write, iclass 35, count 0 2006.201.22:02:06.57#ibcon#wrote, iclass 35, count 0 2006.201.22:02:06.57#ibcon#about to read 3, iclass 35, count 0 2006.201.22:02:06.59#ibcon#read 3, iclass 35, count 0 2006.201.22:02:06.59#ibcon#about to read 4, iclass 35, count 0 2006.201.22:02:06.59#ibcon#read 4, iclass 35, count 0 2006.201.22:02:06.59#ibcon#about to read 5, iclass 35, count 0 2006.201.22:02:06.59#ibcon#read 5, iclass 35, count 0 2006.201.22:02:06.59#ibcon#about to read 6, iclass 35, count 0 2006.201.22:02:06.59#ibcon#read 6, iclass 35, count 0 2006.201.22:02:06.59#ibcon#end of sib2, iclass 35, count 0 2006.201.22:02:06.59#ibcon#*mode == 0, iclass 35, count 0 2006.201.22:02:06.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.22:02:06.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.22:02:06.59#ibcon#*before write, iclass 35, count 0 2006.201.22:02:06.59#ibcon#enter sib2, iclass 35, count 0 2006.201.22:02:06.59#ibcon#flushed, iclass 35, count 0 2006.201.22:02:06.59#ibcon#about to write, iclass 35, count 0 2006.201.22:02:06.59#ibcon#wrote, iclass 35, count 0 2006.201.22:02:06.59#ibcon#about to read 3, iclass 35, count 0 2006.201.22:02:06.64#ibcon#read 3, iclass 35, count 0 2006.201.22:02:06.64#ibcon#about to read 4, iclass 35, count 0 2006.201.22:02:06.64#ibcon#read 4, iclass 35, count 0 2006.201.22:02:06.64#ibcon#about to read 5, iclass 35, count 0 2006.201.22:02:06.64#ibcon#read 5, iclass 35, count 0 2006.201.22:02:06.64#ibcon#about to read 6, iclass 35, count 0 2006.201.22:02:06.64#ibcon#read 6, iclass 35, count 0 2006.201.22:02:06.64#ibcon#end of sib2, iclass 35, count 0 2006.201.22:02:06.64#ibcon#*after write, iclass 35, count 0 2006.201.22:02:06.64#ibcon#*before return 0, iclass 35, count 0 2006.201.22:02:06.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:02:06.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:02:06.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.22:02:06.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.22:02:06.64$vck44/vb=1,4 2006.201.22:02:06.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.22:02:06.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.22:02:06.64#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:06.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:02:06.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:02:06.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:02:06.64#ibcon#enter wrdev, iclass 37, count 2 2006.201.22:02:06.64#ibcon#first serial, iclass 37, count 2 2006.201.22:02:06.64#ibcon#enter sib2, iclass 37, count 2 2006.201.22:02:06.64#ibcon#flushed, iclass 37, count 2 2006.201.22:02:06.64#ibcon#about to write, iclass 37, count 2 2006.201.22:02:06.64#ibcon#wrote, iclass 37, count 2 2006.201.22:02:06.64#ibcon#about to read 3, iclass 37, count 2 2006.201.22:02:06.66#ibcon#read 3, iclass 37, count 2 2006.201.22:02:06.66#ibcon#about to read 4, iclass 37, count 2 2006.201.22:02:06.66#ibcon#read 4, iclass 37, count 2 2006.201.22:02:06.66#ibcon#about to read 5, iclass 37, count 2 2006.201.22:02:06.66#ibcon#read 5, iclass 37, count 2 2006.201.22:02:06.66#ibcon#about to read 6, iclass 37, count 2 2006.201.22:02:06.66#ibcon#read 6, iclass 37, count 2 2006.201.22:02:06.66#ibcon#end of sib2, iclass 37, count 2 2006.201.22:02:06.66#ibcon#*mode == 0, iclass 37, count 2 2006.201.22:02:06.66#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.22:02:06.66#ibcon#[27=AT01-04\r\n] 2006.201.22:02:06.66#ibcon#*before write, iclass 37, count 2 2006.201.22:02:06.66#ibcon#enter sib2, iclass 37, count 2 2006.201.22:02:06.66#ibcon#flushed, iclass 37, count 2 2006.201.22:02:06.66#ibcon#about to write, iclass 37, count 2 2006.201.22:02:06.66#ibcon#wrote, iclass 37, count 2 2006.201.22:02:06.66#ibcon#about to read 3, iclass 37, count 2 2006.201.22:02:06.69#ibcon#read 3, iclass 37, count 2 2006.201.22:02:06.69#ibcon#about to read 4, iclass 37, count 2 2006.201.22:02:06.69#ibcon#read 4, iclass 37, count 2 2006.201.22:02:06.69#ibcon#about to read 5, iclass 37, count 2 2006.201.22:02:06.69#ibcon#read 5, iclass 37, count 2 2006.201.22:02:06.69#ibcon#about to read 6, iclass 37, count 2 2006.201.22:02:06.69#ibcon#read 6, iclass 37, count 2 2006.201.22:02:06.69#ibcon#end of sib2, iclass 37, count 2 2006.201.22:02:06.69#ibcon#*after write, iclass 37, count 2 2006.201.22:02:06.69#ibcon#*before return 0, iclass 37, count 2 2006.201.22:02:06.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:02:06.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:02:06.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.22:02:06.69#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:06.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:02:06.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:02:06.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:02:06.81#ibcon#enter wrdev, iclass 37, count 0 2006.201.22:02:06.81#ibcon#first serial, iclass 37, count 0 2006.201.22:02:06.81#ibcon#enter sib2, iclass 37, count 0 2006.201.22:02:06.81#ibcon#flushed, iclass 37, count 0 2006.201.22:02:06.81#ibcon#about to write, iclass 37, count 0 2006.201.22:02:06.81#ibcon#wrote, iclass 37, count 0 2006.201.22:02:06.81#ibcon#about to read 3, iclass 37, count 0 2006.201.22:02:06.83#ibcon#read 3, iclass 37, count 0 2006.201.22:02:06.83#ibcon#about to read 4, iclass 37, count 0 2006.201.22:02:06.83#ibcon#read 4, iclass 37, count 0 2006.201.22:02:06.83#ibcon#about to read 5, iclass 37, count 0 2006.201.22:02:06.83#ibcon#read 5, iclass 37, count 0 2006.201.22:02:06.83#ibcon#about to read 6, iclass 37, count 0 2006.201.22:02:06.83#ibcon#read 6, iclass 37, count 0 2006.201.22:02:06.83#ibcon#end of sib2, iclass 37, count 0 2006.201.22:02:06.83#ibcon#*mode == 0, iclass 37, count 0 2006.201.22:02:06.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.22:02:06.83#ibcon#[27=USB\r\n] 2006.201.22:02:06.83#ibcon#*before write, iclass 37, count 0 2006.201.22:02:06.83#ibcon#enter sib2, iclass 37, count 0 2006.201.22:02:06.83#ibcon#flushed, iclass 37, count 0 2006.201.22:02:06.83#ibcon#about to write, iclass 37, count 0 2006.201.22:02:06.83#ibcon#wrote, iclass 37, count 0 2006.201.22:02:06.83#ibcon#about to read 3, iclass 37, count 0 2006.201.22:02:06.86#ibcon#read 3, iclass 37, count 0 2006.201.22:02:06.86#ibcon#about to read 4, iclass 37, count 0 2006.201.22:02:06.86#ibcon#read 4, iclass 37, count 0 2006.201.22:02:06.86#ibcon#about to read 5, iclass 37, count 0 2006.201.22:02:06.86#ibcon#read 5, iclass 37, count 0 2006.201.22:02:06.86#ibcon#about to read 6, iclass 37, count 0 2006.201.22:02:06.86#ibcon#read 6, iclass 37, count 0 2006.201.22:02:06.86#ibcon#end of sib2, iclass 37, count 0 2006.201.22:02:06.86#ibcon#*after write, iclass 37, count 0 2006.201.22:02:06.86#ibcon#*before return 0, iclass 37, count 0 2006.201.22:02:06.86#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:02:06.86#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:02:06.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.22:02:06.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.22:02:06.86$vck44/vblo=2,634.99 2006.201.22:02:06.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.22:02:06.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.22:02:06.86#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:06.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:06.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:06.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:06.86#ibcon#enter wrdev, iclass 39, count 0 2006.201.22:02:06.86#ibcon#first serial, iclass 39, count 0 2006.201.22:02:06.86#ibcon#enter sib2, iclass 39, count 0 2006.201.22:02:06.86#ibcon#flushed, iclass 39, count 0 2006.201.22:02:06.86#ibcon#about to write, iclass 39, count 0 2006.201.22:02:06.86#ibcon#wrote, iclass 39, count 0 2006.201.22:02:06.86#ibcon#about to read 3, iclass 39, count 0 2006.201.22:02:06.88#ibcon#read 3, iclass 39, count 0 2006.201.22:02:06.88#ibcon#about to read 4, iclass 39, count 0 2006.201.22:02:06.88#ibcon#read 4, iclass 39, count 0 2006.201.22:02:06.88#ibcon#about to read 5, iclass 39, count 0 2006.201.22:02:06.88#ibcon#read 5, iclass 39, count 0 2006.201.22:02:06.88#ibcon#about to read 6, iclass 39, count 0 2006.201.22:02:06.88#ibcon#read 6, iclass 39, count 0 2006.201.22:02:06.88#ibcon#end of sib2, iclass 39, count 0 2006.201.22:02:06.88#ibcon#*mode == 0, iclass 39, count 0 2006.201.22:02:06.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.22:02:06.88#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.22:02:06.88#ibcon#*before write, iclass 39, count 0 2006.201.22:02:06.88#ibcon#enter sib2, iclass 39, count 0 2006.201.22:02:06.88#ibcon#flushed, iclass 39, count 0 2006.201.22:02:06.88#ibcon#about to write, iclass 39, count 0 2006.201.22:02:06.88#ibcon#wrote, iclass 39, count 0 2006.201.22:02:06.88#ibcon#about to read 3, iclass 39, count 0 2006.201.22:02:06.92#ibcon#read 3, iclass 39, count 0 2006.201.22:02:06.92#ibcon#about to read 4, iclass 39, count 0 2006.201.22:02:06.92#ibcon#read 4, iclass 39, count 0 2006.201.22:02:06.92#ibcon#about to read 5, iclass 39, count 0 2006.201.22:02:06.92#ibcon#read 5, iclass 39, count 0 2006.201.22:02:06.92#ibcon#about to read 6, iclass 39, count 0 2006.201.22:02:06.92#ibcon#read 6, iclass 39, count 0 2006.201.22:02:06.92#ibcon#end of sib2, iclass 39, count 0 2006.201.22:02:06.92#ibcon#*after write, iclass 39, count 0 2006.201.22:02:06.92#ibcon#*before return 0, iclass 39, count 0 2006.201.22:02:06.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:06.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:02:06.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.22:02:06.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.22:02:06.92$vck44/vb=2,5 2006.201.22:02:06.92#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.22:02:06.92#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.22:02:06.92#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:06.92#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:06.98#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:06.98#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:06.98#ibcon#enter wrdev, iclass 2, count 2 2006.201.22:02:06.98#ibcon#first serial, iclass 2, count 2 2006.201.22:02:06.98#ibcon#enter sib2, iclass 2, count 2 2006.201.22:02:06.98#ibcon#flushed, iclass 2, count 2 2006.201.22:02:06.98#ibcon#about to write, iclass 2, count 2 2006.201.22:02:06.98#ibcon#wrote, iclass 2, count 2 2006.201.22:02:06.98#ibcon#about to read 3, iclass 2, count 2 2006.201.22:02:07.00#ibcon#read 3, iclass 2, count 2 2006.201.22:02:07.00#ibcon#about to read 4, iclass 2, count 2 2006.201.22:02:07.00#ibcon#read 4, iclass 2, count 2 2006.201.22:02:07.00#ibcon#about to read 5, iclass 2, count 2 2006.201.22:02:07.00#ibcon#read 5, iclass 2, count 2 2006.201.22:02:07.00#ibcon#about to read 6, iclass 2, count 2 2006.201.22:02:07.00#ibcon#read 6, iclass 2, count 2 2006.201.22:02:07.00#ibcon#end of sib2, iclass 2, count 2 2006.201.22:02:07.00#ibcon#*mode == 0, iclass 2, count 2 2006.201.22:02:07.00#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.22:02:07.00#ibcon#[27=AT02-05\r\n] 2006.201.22:02:07.00#ibcon#*before write, iclass 2, count 2 2006.201.22:02:07.00#ibcon#enter sib2, iclass 2, count 2 2006.201.22:02:07.00#ibcon#flushed, iclass 2, count 2 2006.201.22:02:07.00#ibcon#about to write, iclass 2, count 2 2006.201.22:02:07.00#ibcon#wrote, iclass 2, count 2 2006.201.22:02:07.00#ibcon#about to read 3, iclass 2, count 2 2006.201.22:02:07.03#ibcon#read 3, iclass 2, count 2 2006.201.22:02:07.03#ibcon#about to read 4, iclass 2, count 2 2006.201.22:02:07.03#ibcon#read 4, iclass 2, count 2 2006.201.22:02:07.03#ibcon#about to read 5, iclass 2, count 2 2006.201.22:02:07.03#ibcon#read 5, iclass 2, count 2 2006.201.22:02:07.03#ibcon#about to read 6, iclass 2, count 2 2006.201.22:02:07.03#ibcon#read 6, iclass 2, count 2 2006.201.22:02:07.03#ibcon#end of sib2, iclass 2, count 2 2006.201.22:02:07.03#ibcon#*after write, iclass 2, count 2 2006.201.22:02:07.03#ibcon#*before return 0, iclass 2, count 2 2006.201.22:02:07.03#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:07.03#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:02:07.03#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.22:02:07.03#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:07.03#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:07.15#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:07.15#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:07.15#ibcon#enter wrdev, iclass 2, count 0 2006.201.22:02:07.15#ibcon#first serial, iclass 2, count 0 2006.201.22:02:07.15#ibcon#enter sib2, iclass 2, count 0 2006.201.22:02:07.15#ibcon#flushed, iclass 2, count 0 2006.201.22:02:07.15#ibcon#about to write, iclass 2, count 0 2006.201.22:02:07.15#ibcon#wrote, iclass 2, count 0 2006.201.22:02:07.15#ibcon#about to read 3, iclass 2, count 0 2006.201.22:02:07.17#ibcon#read 3, iclass 2, count 0 2006.201.22:02:07.17#ibcon#about to read 4, iclass 2, count 0 2006.201.22:02:07.17#ibcon#read 4, iclass 2, count 0 2006.201.22:02:07.17#ibcon#about to read 5, iclass 2, count 0 2006.201.22:02:07.17#ibcon#read 5, iclass 2, count 0 2006.201.22:02:07.17#ibcon#about to read 6, iclass 2, count 0 2006.201.22:02:07.17#ibcon#read 6, iclass 2, count 0 2006.201.22:02:07.17#ibcon#end of sib2, iclass 2, count 0 2006.201.22:02:07.17#ibcon#*mode == 0, iclass 2, count 0 2006.201.22:02:07.17#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.22:02:07.17#ibcon#[27=USB\r\n] 2006.201.22:02:07.17#ibcon#*before write, iclass 2, count 0 2006.201.22:02:07.17#ibcon#enter sib2, iclass 2, count 0 2006.201.22:02:07.17#ibcon#flushed, iclass 2, count 0 2006.201.22:02:07.17#ibcon#about to write, iclass 2, count 0 2006.201.22:02:07.17#ibcon#wrote, iclass 2, count 0 2006.201.22:02:07.17#ibcon#about to read 3, iclass 2, count 0 2006.201.22:02:07.20#ibcon#read 3, iclass 2, count 0 2006.201.22:02:07.20#ibcon#about to read 4, iclass 2, count 0 2006.201.22:02:07.20#ibcon#read 4, iclass 2, count 0 2006.201.22:02:07.20#ibcon#about to read 5, iclass 2, count 0 2006.201.22:02:07.20#ibcon#read 5, iclass 2, count 0 2006.201.22:02:07.20#ibcon#about to read 6, iclass 2, count 0 2006.201.22:02:07.20#ibcon#read 6, iclass 2, count 0 2006.201.22:02:07.20#ibcon#end of sib2, iclass 2, count 0 2006.201.22:02:07.20#ibcon#*after write, iclass 2, count 0 2006.201.22:02:07.20#ibcon#*before return 0, iclass 2, count 0 2006.201.22:02:07.20#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:07.20#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:02:07.20#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.22:02:07.20#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.22:02:07.20$vck44/vblo=3,649.99 2006.201.22:02:07.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.22:02:07.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.22:02:07.20#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:07.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:07.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:07.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:07.20#ibcon#enter wrdev, iclass 5, count 0 2006.201.22:02:07.20#ibcon#first serial, iclass 5, count 0 2006.201.22:02:07.20#ibcon#enter sib2, iclass 5, count 0 2006.201.22:02:07.20#ibcon#flushed, iclass 5, count 0 2006.201.22:02:07.20#ibcon#about to write, iclass 5, count 0 2006.201.22:02:07.20#ibcon#wrote, iclass 5, count 0 2006.201.22:02:07.20#ibcon#about to read 3, iclass 5, count 0 2006.201.22:02:07.22#ibcon#read 3, iclass 5, count 0 2006.201.22:02:07.22#ibcon#about to read 4, iclass 5, count 0 2006.201.22:02:07.22#ibcon#read 4, iclass 5, count 0 2006.201.22:02:07.22#ibcon#about to read 5, iclass 5, count 0 2006.201.22:02:07.22#ibcon#read 5, iclass 5, count 0 2006.201.22:02:07.22#ibcon#about to read 6, iclass 5, count 0 2006.201.22:02:07.22#ibcon#read 6, iclass 5, count 0 2006.201.22:02:07.22#ibcon#end of sib2, iclass 5, count 0 2006.201.22:02:07.22#ibcon#*mode == 0, iclass 5, count 0 2006.201.22:02:07.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.22:02:07.22#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.22:02:07.22#ibcon#*before write, iclass 5, count 0 2006.201.22:02:07.22#ibcon#enter sib2, iclass 5, count 0 2006.201.22:02:07.22#ibcon#flushed, iclass 5, count 0 2006.201.22:02:07.22#ibcon#about to write, iclass 5, count 0 2006.201.22:02:07.22#ibcon#wrote, iclass 5, count 0 2006.201.22:02:07.22#ibcon#about to read 3, iclass 5, count 0 2006.201.22:02:07.26#ibcon#read 3, iclass 5, count 0 2006.201.22:02:07.26#ibcon#about to read 4, iclass 5, count 0 2006.201.22:02:07.26#ibcon#read 4, iclass 5, count 0 2006.201.22:02:07.26#ibcon#about to read 5, iclass 5, count 0 2006.201.22:02:07.26#ibcon#read 5, iclass 5, count 0 2006.201.22:02:07.26#ibcon#about to read 6, iclass 5, count 0 2006.201.22:02:07.26#ibcon#read 6, iclass 5, count 0 2006.201.22:02:07.26#ibcon#end of sib2, iclass 5, count 0 2006.201.22:02:07.26#ibcon#*after write, iclass 5, count 0 2006.201.22:02:07.26#ibcon#*before return 0, iclass 5, count 0 2006.201.22:02:07.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:07.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:02:07.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.22:02:07.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.22:02:07.26$vck44/vb=3,4 2006.201.22:02:07.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.22:02:07.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.22:02:07.26#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:07.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:07.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:07.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:07.32#ibcon#enter wrdev, iclass 7, count 2 2006.201.22:02:07.32#ibcon#first serial, iclass 7, count 2 2006.201.22:02:07.32#ibcon#enter sib2, iclass 7, count 2 2006.201.22:02:07.32#ibcon#flushed, iclass 7, count 2 2006.201.22:02:07.32#ibcon#about to write, iclass 7, count 2 2006.201.22:02:07.32#ibcon#wrote, iclass 7, count 2 2006.201.22:02:07.32#ibcon#about to read 3, iclass 7, count 2 2006.201.22:02:07.34#ibcon#read 3, iclass 7, count 2 2006.201.22:02:07.34#ibcon#about to read 4, iclass 7, count 2 2006.201.22:02:07.34#ibcon#read 4, iclass 7, count 2 2006.201.22:02:07.34#ibcon#about to read 5, iclass 7, count 2 2006.201.22:02:07.34#ibcon#read 5, iclass 7, count 2 2006.201.22:02:07.34#ibcon#about to read 6, iclass 7, count 2 2006.201.22:02:07.34#ibcon#read 6, iclass 7, count 2 2006.201.22:02:07.34#ibcon#end of sib2, iclass 7, count 2 2006.201.22:02:07.34#ibcon#*mode == 0, iclass 7, count 2 2006.201.22:02:07.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.22:02:07.34#ibcon#[27=AT03-04\r\n] 2006.201.22:02:07.34#ibcon#*before write, iclass 7, count 2 2006.201.22:02:07.34#ibcon#enter sib2, iclass 7, count 2 2006.201.22:02:07.34#ibcon#flushed, iclass 7, count 2 2006.201.22:02:07.34#ibcon#about to write, iclass 7, count 2 2006.201.22:02:07.34#ibcon#wrote, iclass 7, count 2 2006.201.22:02:07.34#ibcon#about to read 3, iclass 7, count 2 2006.201.22:02:07.37#ibcon#read 3, iclass 7, count 2 2006.201.22:02:07.37#ibcon#about to read 4, iclass 7, count 2 2006.201.22:02:07.37#ibcon#read 4, iclass 7, count 2 2006.201.22:02:07.37#ibcon#about to read 5, iclass 7, count 2 2006.201.22:02:07.37#ibcon#read 5, iclass 7, count 2 2006.201.22:02:07.37#ibcon#about to read 6, iclass 7, count 2 2006.201.22:02:07.37#ibcon#read 6, iclass 7, count 2 2006.201.22:02:07.37#ibcon#end of sib2, iclass 7, count 2 2006.201.22:02:07.37#ibcon#*after write, iclass 7, count 2 2006.201.22:02:07.37#ibcon#*before return 0, iclass 7, count 2 2006.201.22:02:07.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:07.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:02:07.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.22:02:07.37#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:07.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:07.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:07.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:07.49#ibcon#enter wrdev, iclass 7, count 0 2006.201.22:02:07.49#ibcon#first serial, iclass 7, count 0 2006.201.22:02:07.49#ibcon#enter sib2, iclass 7, count 0 2006.201.22:02:07.49#ibcon#flushed, iclass 7, count 0 2006.201.22:02:07.49#ibcon#about to write, iclass 7, count 0 2006.201.22:02:07.49#ibcon#wrote, iclass 7, count 0 2006.201.22:02:07.49#ibcon#about to read 3, iclass 7, count 0 2006.201.22:02:07.51#ibcon#read 3, iclass 7, count 0 2006.201.22:02:07.51#ibcon#about to read 4, iclass 7, count 0 2006.201.22:02:07.51#ibcon#read 4, iclass 7, count 0 2006.201.22:02:07.51#ibcon#about to read 5, iclass 7, count 0 2006.201.22:02:07.51#ibcon#read 5, iclass 7, count 0 2006.201.22:02:07.51#ibcon#about to read 6, iclass 7, count 0 2006.201.22:02:07.51#ibcon#read 6, iclass 7, count 0 2006.201.22:02:07.51#ibcon#end of sib2, iclass 7, count 0 2006.201.22:02:07.51#ibcon#*mode == 0, iclass 7, count 0 2006.201.22:02:07.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.22:02:07.51#ibcon#[27=USB\r\n] 2006.201.22:02:07.51#ibcon#*before write, iclass 7, count 0 2006.201.22:02:07.51#ibcon#enter sib2, iclass 7, count 0 2006.201.22:02:07.51#ibcon#flushed, iclass 7, count 0 2006.201.22:02:07.51#ibcon#about to write, iclass 7, count 0 2006.201.22:02:07.51#ibcon#wrote, iclass 7, count 0 2006.201.22:02:07.51#ibcon#about to read 3, iclass 7, count 0 2006.201.22:02:07.54#ibcon#read 3, iclass 7, count 0 2006.201.22:02:07.54#ibcon#about to read 4, iclass 7, count 0 2006.201.22:02:07.54#ibcon#read 4, iclass 7, count 0 2006.201.22:02:07.54#ibcon#about to read 5, iclass 7, count 0 2006.201.22:02:07.54#ibcon#read 5, iclass 7, count 0 2006.201.22:02:07.54#ibcon#about to read 6, iclass 7, count 0 2006.201.22:02:07.54#ibcon#read 6, iclass 7, count 0 2006.201.22:02:07.54#ibcon#end of sib2, iclass 7, count 0 2006.201.22:02:07.54#ibcon#*after write, iclass 7, count 0 2006.201.22:02:07.54#ibcon#*before return 0, iclass 7, count 0 2006.201.22:02:07.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:07.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:02:07.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.22:02:07.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.22:02:07.54$vck44/vblo=4,679.99 2006.201.22:02:07.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.22:02:07.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.22:02:07.54#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:07.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:07.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:07.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:07.54#ibcon#enter wrdev, iclass 11, count 0 2006.201.22:02:07.54#ibcon#first serial, iclass 11, count 0 2006.201.22:02:07.54#ibcon#enter sib2, iclass 11, count 0 2006.201.22:02:07.54#ibcon#flushed, iclass 11, count 0 2006.201.22:02:07.54#ibcon#about to write, iclass 11, count 0 2006.201.22:02:07.54#ibcon#wrote, iclass 11, count 0 2006.201.22:02:07.54#ibcon#about to read 3, iclass 11, count 0 2006.201.22:02:07.56#ibcon#read 3, iclass 11, count 0 2006.201.22:02:07.56#ibcon#about to read 4, iclass 11, count 0 2006.201.22:02:07.56#ibcon#read 4, iclass 11, count 0 2006.201.22:02:07.56#ibcon#about to read 5, iclass 11, count 0 2006.201.22:02:07.56#ibcon#read 5, iclass 11, count 0 2006.201.22:02:07.56#ibcon#about to read 6, iclass 11, count 0 2006.201.22:02:07.56#ibcon#read 6, iclass 11, count 0 2006.201.22:02:07.56#ibcon#end of sib2, iclass 11, count 0 2006.201.22:02:07.56#ibcon#*mode == 0, iclass 11, count 0 2006.201.22:02:07.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.22:02:07.56#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.22:02:07.56#ibcon#*before write, iclass 11, count 0 2006.201.22:02:07.56#ibcon#enter sib2, iclass 11, count 0 2006.201.22:02:07.56#ibcon#flushed, iclass 11, count 0 2006.201.22:02:07.56#ibcon#about to write, iclass 11, count 0 2006.201.22:02:07.56#ibcon#wrote, iclass 11, count 0 2006.201.22:02:07.56#ibcon#about to read 3, iclass 11, count 0 2006.201.22:02:07.61#ibcon#read 3, iclass 11, count 0 2006.201.22:02:07.61#ibcon#about to read 4, iclass 11, count 0 2006.201.22:02:07.61#ibcon#read 4, iclass 11, count 0 2006.201.22:02:07.61#ibcon#about to read 5, iclass 11, count 0 2006.201.22:02:07.61#ibcon#read 5, iclass 11, count 0 2006.201.22:02:07.61#ibcon#about to read 6, iclass 11, count 0 2006.201.22:02:07.61#ibcon#read 6, iclass 11, count 0 2006.201.22:02:07.61#ibcon#end of sib2, iclass 11, count 0 2006.201.22:02:07.61#ibcon#*after write, iclass 11, count 0 2006.201.22:02:07.61#ibcon#*before return 0, iclass 11, count 0 2006.201.22:02:07.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:07.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:02:07.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.22:02:07.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.22:02:07.61$vck44/vb=4,5 2006.201.22:02:07.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.22:02:07.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.22:02:07.61#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:07.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:07.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:07.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:07.66#ibcon#enter wrdev, iclass 13, count 2 2006.201.22:02:07.66#ibcon#first serial, iclass 13, count 2 2006.201.22:02:07.66#ibcon#enter sib2, iclass 13, count 2 2006.201.22:02:07.66#ibcon#flushed, iclass 13, count 2 2006.201.22:02:07.66#ibcon#about to write, iclass 13, count 2 2006.201.22:02:07.66#ibcon#wrote, iclass 13, count 2 2006.201.22:02:07.66#ibcon#about to read 3, iclass 13, count 2 2006.201.22:02:07.68#ibcon#read 3, iclass 13, count 2 2006.201.22:02:07.68#ibcon#about to read 4, iclass 13, count 2 2006.201.22:02:07.68#ibcon#read 4, iclass 13, count 2 2006.201.22:02:07.68#ibcon#about to read 5, iclass 13, count 2 2006.201.22:02:07.68#ibcon#read 5, iclass 13, count 2 2006.201.22:02:07.68#ibcon#about to read 6, iclass 13, count 2 2006.201.22:02:07.68#ibcon#read 6, iclass 13, count 2 2006.201.22:02:07.68#ibcon#end of sib2, iclass 13, count 2 2006.201.22:02:07.68#ibcon#*mode == 0, iclass 13, count 2 2006.201.22:02:07.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.22:02:07.68#ibcon#[27=AT04-05\r\n] 2006.201.22:02:07.68#ibcon#*before write, iclass 13, count 2 2006.201.22:02:07.68#ibcon#enter sib2, iclass 13, count 2 2006.201.22:02:07.68#ibcon#flushed, iclass 13, count 2 2006.201.22:02:07.68#ibcon#about to write, iclass 13, count 2 2006.201.22:02:07.68#ibcon#wrote, iclass 13, count 2 2006.201.22:02:07.68#ibcon#about to read 3, iclass 13, count 2 2006.201.22:02:07.71#ibcon#read 3, iclass 13, count 2 2006.201.22:02:07.71#ibcon#about to read 4, iclass 13, count 2 2006.201.22:02:07.71#ibcon#read 4, iclass 13, count 2 2006.201.22:02:07.71#ibcon#about to read 5, iclass 13, count 2 2006.201.22:02:07.71#ibcon#read 5, iclass 13, count 2 2006.201.22:02:07.71#ibcon#about to read 6, iclass 13, count 2 2006.201.22:02:07.71#ibcon#read 6, iclass 13, count 2 2006.201.22:02:07.71#ibcon#end of sib2, iclass 13, count 2 2006.201.22:02:07.71#ibcon#*after write, iclass 13, count 2 2006.201.22:02:07.71#ibcon#*before return 0, iclass 13, count 2 2006.201.22:02:07.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:07.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:02:07.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.22:02:07.71#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:07.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:07.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:07.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:07.83#ibcon#enter wrdev, iclass 13, count 0 2006.201.22:02:07.83#ibcon#first serial, iclass 13, count 0 2006.201.22:02:07.83#ibcon#enter sib2, iclass 13, count 0 2006.201.22:02:07.83#ibcon#flushed, iclass 13, count 0 2006.201.22:02:07.83#ibcon#about to write, iclass 13, count 0 2006.201.22:02:07.83#ibcon#wrote, iclass 13, count 0 2006.201.22:02:07.83#ibcon#about to read 3, iclass 13, count 0 2006.201.22:02:07.85#ibcon#read 3, iclass 13, count 0 2006.201.22:02:07.85#ibcon#about to read 4, iclass 13, count 0 2006.201.22:02:07.85#ibcon#read 4, iclass 13, count 0 2006.201.22:02:07.85#ibcon#about to read 5, iclass 13, count 0 2006.201.22:02:07.85#ibcon#read 5, iclass 13, count 0 2006.201.22:02:07.85#ibcon#about to read 6, iclass 13, count 0 2006.201.22:02:07.85#ibcon#read 6, iclass 13, count 0 2006.201.22:02:07.85#ibcon#end of sib2, iclass 13, count 0 2006.201.22:02:07.85#ibcon#*mode == 0, iclass 13, count 0 2006.201.22:02:07.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.22:02:07.85#ibcon#[27=USB\r\n] 2006.201.22:02:07.85#ibcon#*before write, iclass 13, count 0 2006.201.22:02:07.85#ibcon#enter sib2, iclass 13, count 0 2006.201.22:02:07.85#ibcon#flushed, iclass 13, count 0 2006.201.22:02:07.85#ibcon#about to write, iclass 13, count 0 2006.201.22:02:07.85#ibcon#wrote, iclass 13, count 0 2006.201.22:02:07.85#ibcon#about to read 3, iclass 13, count 0 2006.201.22:02:07.88#ibcon#read 3, iclass 13, count 0 2006.201.22:02:07.88#ibcon#about to read 4, iclass 13, count 0 2006.201.22:02:07.88#ibcon#read 4, iclass 13, count 0 2006.201.22:02:07.88#ibcon#about to read 5, iclass 13, count 0 2006.201.22:02:07.88#ibcon#read 5, iclass 13, count 0 2006.201.22:02:07.88#ibcon#about to read 6, iclass 13, count 0 2006.201.22:02:07.88#ibcon#read 6, iclass 13, count 0 2006.201.22:02:07.88#ibcon#end of sib2, iclass 13, count 0 2006.201.22:02:07.88#ibcon#*after write, iclass 13, count 0 2006.201.22:02:07.88#ibcon#*before return 0, iclass 13, count 0 2006.201.22:02:07.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:07.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:02:07.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.22:02:07.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.22:02:07.88$vck44/vblo=5,709.99 2006.201.22:02:07.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.22:02:07.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.22:02:07.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:07.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:07.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:07.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:07.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:02:07.88#ibcon#first serial, iclass 15, count 0 2006.201.22:02:07.88#ibcon#enter sib2, iclass 15, count 0 2006.201.22:02:07.88#ibcon#flushed, iclass 15, count 0 2006.201.22:02:07.88#ibcon#about to write, iclass 15, count 0 2006.201.22:02:07.88#ibcon#wrote, iclass 15, count 0 2006.201.22:02:07.88#ibcon#about to read 3, iclass 15, count 0 2006.201.22:02:07.90#ibcon#read 3, iclass 15, count 0 2006.201.22:02:07.90#ibcon#about to read 4, iclass 15, count 0 2006.201.22:02:07.90#ibcon#read 4, iclass 15, count 0 2006.201.22:02:07.90#ibcon#about to read 5, iclass 15, count 0 2006.201.22:02:07.90#ibcon#read 5, iclass 15, count 0 2006.201.22:02:07.90#ibcon#about to read 6, iclass 15, count 0 2006.201.22:02:07.90#ibcon#read 6, iclass 15, count 0 2006.201.22:02:07.90#ibcon#end of sib2, iclass 15, count 0 2006.201.22:02:07.90#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:02:07.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:02:07.90#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.22:02:07.90#ibcon#*before write, iclass 15, count 0 2006.201.22:02:07.90#ibcon#enter sib2, iclass 15, count 0 2006.201.22:02:07.90#ibcon#flushed, iclass 15, count 0 2006.201.22:02:07.90#ibcon#about to write, iclass 15, count 0 2006.201.22:02:07.90#ibcon#wrote, iclass 15, count 0 2006.201.22:02:07.90#ibcon#about to read 3, iclass 15, count 0 2006.201.22:02:07.94#ibcon#read 3, iclass 15, count 0 2006.201.22:02:07.94#ibcon#about to read 4, iclass 15, count 0 2006.201.22:02:07.94#ibcon#read 4, iclass 15, count 0 2006.201.22:02:07.94#ibcon#about to read 5, iclass 15, count 0 2006.201.22:02:07.94#ibcon#read 5, iclass 15, count 0 2006.201.22:02:07.94#ibcon#about to read 6, iclass 15, count 0 2006.201.22:02:07.94#ibcon#read 6, iclass 15, count 0 2006.201.22:02:07.94#ibcon#end of sib2, iclass 15, count 0 2006.201.22:02:07.94#ibcon#*after write, iclass 15, count 0 2006.201.22:02:07.94#ibcon#*before return 0, iclass 15, count 0 2006.201.22:02:07.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:07.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:02:07.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:02:07.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:02:07.94$vck44/vb=5,4 2006.201.22:02:07.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.22:02:07.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.22:02:07.94#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:07.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:08.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:08.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:08.00#ibcon#enter wrdev, iclass 17, count 2 2006.201.22:02:08.00#ibcon#first serial, iclass 17, count 2 2006.201.22:02:08.00#ibcon#enter sib2, iclass 17, count 2 2006.201.22:02:08.00#ibcon#flushed, iclass 17, count 2 2006.201.22:02:08.00#ibcon#about to write, iclass 17, count 2 2006.201.22:02:08.00#ibcon#wrote, iclass 17, count 2 2006.201.22:02:08.00#ibcon#about to read 3, iclass 17, count 2 2006.201.22:02:08.02#ibcon#read 3, iclass 17, count 2 2006.201.22:02:08.02#ibcon#about to read 4, iclass 17, count 2 2006.201.22:02:08.02#ibcon#read 4, iclass 17, count 2 2006.201.22:02:08.02#ibcon#about to read 5, iclass 17, count 2 2006.201.22:02:08.02#ibcon#read 5, iclass 17, count 2 2006.201.22:02:08.02#ibcon#about to read 6, iclass 17, count 2 2006.201.22:02:08.02#ibcon#read 6, iclass 17, count 2 2006.201.22:02:08.02#ibcon#end of sib2, iclass 17, count 2 2006.201.22:02:08.02#ibcon#*mode == 0, iclass 17, count 2 2006.201.22:02:08.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.22:02:08.02#ibcon#[27=AT05-04\r\n] 2006.201.22:02:08.02#ibcon#*before write, iclass 17, count 2 2006.201.22:02:08.02#ibcon#enter sib2, iclass 17, count 2 2006.201.22:02:08.02#ibcon#flushed, iclass 17, count 2 2006.201.22:02:08.02#ibcon#about to write, iclass 17, count 2 2006.201.22:02:08.02#ibcon#wrote, iclass 17, count 2 2006.201.22:02:08.02#ibcon#about to read 3, iclass 17, count 2 2006.201.22:02:08.05#ibcon#read 3, iclass 17, count 2 2006.201.22:02:08.05#ibcon#about to read 4, iclass 17, count 2 2006.201.22:02:08.05#ibcon#read 4, iclass 17, count 2 2006.201.22:02:08.05#ibcon#about to read 5, iclass 17, count 2 2006.201.22:02:08.05#ibcon#read 5, iclass 17, count 2 2006.201.22:02:08.05#ibcon#about to read 6, iclass 17, count 2 2006.201.22:02:08.05#ibcon#read 6, iclass 17, count 2 2006.201.22:02:08.05#ibcon#end of sib2, iclass 17, count 2 2006.201.22:02:08.05#ibcon#*after write, iclass 17, count 2 2006.201.22:02:08.05#ibcon#*before return 0, iclass 17, count 2 2006.201.22:02:08.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:08.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:02:08.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.22:02:08.05#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:08.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:08.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:08.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:08.17#ibcon#enter wrdev, iclass 17, count 0 2006.201.22:02:08.17#ibcon#first serial, iclass 17, count 0 2006.201.22:02:08.17#ibcon#enter sib2, iclass 17, count 0 2006.201.22:02:08.17#ibcon#flushed, iclass 17, count 0 2006.201.22:02:08.17#ibcon#about to write, iclass 17, count 0 2006.201.22:02:08.17#ibcon#wrote, iclass 17, count 0 2006.201.22:02:08.17#ibcon#about to read 3, iclass 17, count 0 2006.201.22:02:08.20#ibcon#read 3, iclass 17, count 0 2006.201.22:02:08.20#ibcon#about to read 4, iclass 17, count 0 2006.201.22:02:08.20#ibcon#read 4, iclass 17, count 0 2006.201.22:02:08.20#ibcon#about to read 5, iclass 17, count 0 2006.201.22:02:08.20#ibcon#read 5, iclass 17, count 0 2006.201.22:02:08.20#ibcon#about to read 6, iclass 17, count 0 2006.201.22:02:08.20#ibcon#read 6, iclass 17, count 0 2006.201.22:02:08.20#ibcon#end of sib2, iclass 17, count 0 2006.201.22:02:08.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.22:02:08.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.22:02:08.20#ibcon#[27=USB\r\n] 2006.201.22:02:08.20#ibcon#*before write, iclass 17, count 0 2006.201.22:02:08.20#ibcon#enter sib2, iclass 17, count 0 2006.201.22:02:08.20#ibcon#flushed, iclass 17, count 0 2006.201.22:02:08.20#ibcon#about to write, iclass 17, count 0 2006.201.22:02:08.20#ibcon#wrote, iclass 17, count 0 2006.201.22:02:08.20#ibcon#about to read 3, iclass 17, count 0 2006.201.22:02:08.23#ibcon#read 3, iclass 17, count 0 2006.201.22:02:08.23#ibcon#about to read 4, iclass 17, count 0 2006.201.22:02:08.23#ibcon#read 4, iclass 17, count 0 2006.201.22:02:08.23#ibcon#about to read 5, iclass 17, count 0 2006.201.22:02:08.23#ibcon#read 5, iclass 17, count 0 2006.201.22:02:08.23#ibcon#about to read 6, iclass 17, count 0 2006.201.22:02:08.23#ibcon#read 6, iclass 17, count 0 2006.201.22:02:08.23#ibcon#end of sib2, iclass 17, count 0 2006.201.22:02:08.23#ibcon#*after write, iclass 17, count 0 2006.201.22:02:08.23#ibcon#*before return 0, iclass 17, count 0 2006.201.22:02:08.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:08.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:02:08.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.22:02:08.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.22:02:08.23$vck44/vblo=6,719.99 2006.201.22:02:08.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.22:02:08.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.22:02:08.23#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:08.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:08.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:08.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:08.23#ibcon#enter wrdev, iclass 19, count 0 2006.201.22:02:08.23#ibcon#first serial, iclass 19, count 0 2006.201.22:02:08.23#ibcon#enter sib2, iclass 19, count 0 2006.201.22:02:08.23#ibcon#flushed, iclass 19, count 0 2006.201.22:02:08.23#ibcon#about to write, iclass 19, count 0 2006.201.22:02:08.23#ibcon#wrote, iclass 19, count 0 2006.201.22:02:08.23#ibcon#about to read 3, iclass 19, count 0 2006.201.22:02:08.25#ibcon#read 3, iclass 19, count 0 2006.201.22:02:08.25#ibcon#about to read 4, iclass 19, count 0 2006.201.22:02:08.25#ibcon#read 4, iclass 19, count 0 2006.201.22:02:08.25#ibcon#about to read 5, iclass 19, count 0 2006.201.22:02:08.25#ibcon#read 5, iclass 19, count 0 2006.201.22:02:08.25#ibcon#about to read 6, iclass 19, count 0 2006.201.22:02:08.25#ibcon#read 6, iclass 19, count 0 2006.201.22:02:08.25#ibcon#end of sib2, iclass 19, count 0 2006.201.22:02:08.25#ibcon#*mode == 0, iclass 19, count 0 2006.201.22:02:08.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.22:02:08.25#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.22:02:08.25#ibcon#*before write, iclass 19, count 0 2006.201.22:02:08.25#ibcon#enter sib2, iclass 19, count 0 2006.201.22:02:08.25#ibcon#flushed, iclass 19, count 0 2006.201.22:02:08.25#ibcon#about to write, iclass 19, count 0 2006.201.22:02:08.25#ibcon#wrote, iclass 19, count 0 2006.201.22:02:08.25#ibcon#about to read 3, iclass 19, count 0 2006.201.22:02:08.29#ibcon#read 3, iclass 19, count 0 2006.201.22:02:08.29#ibcon#about to read 4, iclass 19, count 0 2006.201.22:02:08.29#ibcon#read 4, iclass 19, count 0 2006.201.22:02:08.29#ibcon#about to read 5, iclass 19, count 0 2006.201.22:02:08.29#ibcon#read 5, iclass 19, count 0 2006.201.22:02:08.29#ibcon#about to read 6, iclass 19, count 0 2006.201.22:02:08.29#ibcon#read 6, iclass 19, count 0 2006.201.22:02:08.29#ibcon#end of sib2, iclass 19, count 0 2006.201.22:02:08.29#ibcon#*after write, iclass 19, count 0 2006.201.22:02:08.29#ibcon#*before return 0, iclass 19, count 0 2006.201.22:02:08.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:08.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:02:08.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.22:02:08.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.22:02:08.29$vck44/vb=6,4 2006.201.22:02:08.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.22:02:08.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.22:02:08.29#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:08.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:08.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:08.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:08.35#ibcon#enter wrdev, iclass 21, count 2 2006.201.22:02:08.35#ibcon#first serial, iclass 21, count 2 2006.201.22:02:08.35#ibcon#enter sib2, iclass 21, count 2 2006.201.22:02:08.35#ibcon#flushed, iclass 21, count 2 2006.201.22:02:08.35#ibcon#about to write, iclass 21, count 2 2006.201.22:02:08.35#ibcon#wrote, iclass 21, count 2 2006.201.22:02:08.35#ibcon#about to read 3, iclass 21, count 2 2006.201.22:02:08.37#ibcon#read 3, iclass 21, count 2 2006.201.22:02:08.37#ibcon#about to read 4, iclass 21, count 2 2006.201.22:02:08.37#ibcon#read 4, iclass 21, count 2 2006.201.22:02:08.37#ibcon#about to read 5, iclass 21, count 2 2006.201.22:02:08.37#ibcon#read 5, iclass 21, count 2 2006.201.22:02:08.37#ibcon#about to read 6, iclass 21, count 2 2006.201.22:02:08.37#ibcon#read 6, iclass 21, count 2 2006.201.22:02:08.37#ibcon#end of sib2, iclass 21, count 2 2006.201.22:02:08.37#ibcon#*mode == 0, iclass 21, count 2 2006.201.22:02:08.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.22:02:08.37#ibcon#[27=AT06-04\r\n] 2006.201.22:02:08.37#ibcon#*before write, iclass 21, count 2 2006.201.22:02:08.37#ibcon#enter sib2, iclass 21, count 2 2006.201.22:02:08.37#ibcon#flushed, iclass 21, count 2 2006.201.22:02:08.37#ibcon#about to write, iclass 21, count 2 2006.201.22:02:08.37#ibcon#wrote, iclass 21, count 2 2006.201.22:02:08.37#ibcon#about to read 3, iclass 21, count 2 2006.201.22:02:08.40#ibcon#read 3, iclass 21, count 2 2006.201.22:02:08.40#ibcon#about to read 4, iclass 21, count 2 2006.201.22:02:08.40#ibcon#read 4, iclass 21, count 2 2006.201.22:02:08.40#ibcon#about to read 5, iclass 21, count 2 2006.201.22:02:08.40#ibcon#read 5, iclass 21, count 2 2006.201.22:02:08.40#ibcon#about to read 6, iclass 21, count 2 2006.201.22:02:08.40#ibcon#read 6, iclass 21, count 2 2006.201.22:02:08.40#ibcon#end of sib2, iclass 21, count 2 2006.201.22:02:08.40#ibcon#*after write, iclass 21, count 2 2006.201.22:02:08.40#ibcon#*before return 0, iclass 21, count 2 2006.201.22:02:08.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:08.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:02:08.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.22:02:08.40#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:08.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:08.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:08.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:08.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.22:02:08.52#ibcon#first serial, iclass 21, count 0 2006.201.22:02:08.52#ibcon#enter sib2, iclass 21, count 0 2006.201.22:02:08.52#ibcon#flushed, iclass 21, count 0 2006.201.22:02:08.52#ibcon#about to write, iclass 21, count 0 2006.201.22:02:08.52#ibcon#wrote, iclass 21, count 0 2006.201.22:02:08.52#ibcon#about to read 3, iclass 21, count 0 2006.201.22:02:08.54#ibcon#read 3, iclass 21, count 0 2006.201.22:02:08.54#ibcon#about to read 4, iclass 21, count 0 2006.201.22:02:08.54#ibcon#read 4, iclass 21, count 0 2006.201.22:02:08.54#ibcon#about to read 5, iclass 21, count 0 2006.201.22:02:08.54#ibcon#read 5, iclass 21, count 0 2006.201.22:02:08.54#ibcon#about to read 6, iclass 21, count 0 2006.201.22:02:08.54#ibcon#read 6, iclass 21, count 0 2006.201.22:02:08.54#ibcon#end of sib2, iclass 21, count 0 2006.201.22:02:08.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.22:02:08.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.22:02:08.54#ibcon#[27=USB\r\n] 2006.201.22:02:08.54#ibcon#*before write, iclass 21, count 0 2006.201.22:02:08.54#ibcon#enter sib2, iclass 21, count 0 2006.201.22:02:08.54#ibcon#flushed, iclass 21, count 0 2006.201.22:02:08.54#ibcon#about to write, iclass 21, count 0 2006.201.22:02:08.54#ibcon#wrote, iclass 21, count 0 2006.201.22:02:08.54#ibcon#about to read 3, iclass 21, count 0 2006.201.22:02:08.57#ibcon#read 3, iclass 21, count 0 2006.201.22:02:08.57#ibcon#about to read 4, iclass 21, count 0 2006.201.22:02:08.57#ibcon#read 4, iclass 21, count 0 2006.201.22:02:08.57#ibcon#about to read 5, iclass 21, count 0 2006.201.22:02:08.57#ibcon#read 5, iclass 21, count 0 2006.201.22:02:08.57#ibcon#about to read 6, iclass 21, count 0 2006.201.22:02:08.57#ibcon#read 6, iclass 21, count 0 2006.201.22:02:08.57#ibcon#end of sib2, iclass 21, count 0 2006.201.22:02:08.57#ibcon#*after write, iclass 21, count 0 2006.201.22:02:08.57#ibcon#*before return 0, iclass 21, count 0 2006.201.22:02:08.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:08.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:02:08.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.22:02:08.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.22:02:08.57$vck44/vblo=7,734.99 2006.201.22:02:08.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.22:02:08.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.22:02:08.57#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:08.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:08.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:08.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:08.57#ibcon#enter wrdev, iclass 23, count 0 2006.201.22:02:08.57#ibcon#first serial, iclass 23, count 0 2006.201.22:02:08.57#ibcon#enter sib2, iclass 23, count 0 2006.201.22:02:08.57#ibcon#flushed, iclass 23, count 0 2006.201.22:02:08.57#ibcon#about to write, iclass 23, count 0 2006.201.22:02:08.57#ibcon#wrote, iclass 23, count 0 2006.201.22:02:08.57#ibcon#about to read 3, iclass 23, count 0 2006.201.22:02:08.59#ibcon#read 3, iclass 23, count 0 2006.201.22:02:08.59#ibcon#about to read 4, iclass 23, count 0 2006.201.22:02:08.59#ibcon#read 4, iclass 23, count 0 2006.201.22:02:08.59#ibcon#about to read 5, iclass 23, count 0 2006.201.22:02:08.59#ibcon#read 5, iclass 23, count 0 2006.201.22:02:08.59#ibcon#about to read 6, iclass 23, count 0 2006.201.22:02:08.59#ibcon#read 6, iclass 23, count 0 2006.201.22:02:08.59#ibcon#end of sib2, iclass 23, count 0 2006.201.22:02:08.59#ibcon#*mode == 0, iclass 23, count 0 2006.201.22:02:08.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.22:02:08.59#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.22:02:08.59#ibcon#*before write, iclass 23, count 0 2006.201.22:02:08.59#ibcon#enter sib2, iclass 23, count 0 2006.201.22:02:08.59#ibcon#flushed, iclass 23, count 0 2006.201.22:02:08.59#ibcon#about to write, iclass 23, count 0 2006.201.22:02:08.59#ibcon#wrote, iclass 23, count 0 2006.201.22:02:08.59#ibcon#about to read 3, iclass 23, count 0 2006.201.22:02:08.63#ibcon#read 3, iclass 23, count 0 2006.201.22:02:08.63#ibcon#about to read 4, iclass 23, count 0 2006.201.22:02:08.63#ibcon#read 4, iclass 23, count 0 2006.201.22:02:08.63#ibcon#about to read 5, iclass 23, count 0 2006.201.22:02:08.63#ibcon#read 5, iclass 23, count 0 2006.201.22:02:08.63#ibcon#about to read 6, iclass 23, count 0 2006.201.22:02:08.63#ibcon#read 6, iclass 23, count 0 2006.201.22:02:08.63#ibcon#end of sib2, iclass 23, count 0 2006.201.22:02:08.63#ibcon#*after write, iclass 23, count 0 2006.201.22:02:08.63#ibcon#*before return 0, iclass 23, count 0 2006.201.22:02:08.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:08.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:02:08.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.22:02:08.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.22:02:08.63$vck44/vb=7,4 2006.201.22:02:08.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.22:02:08.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.22:02:08.63#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:08.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:08.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:08.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:08.69#ibcon#enter wrdev, iclass 25, count 2 2006.201.22:02:08.69#ibcon#first serial, iclass 25, count 2 2006.201.22:02:08.69#ibcon#enter sib2, iclass 25, count 2 2006.201.22:02:08.69#ibcon#flushed, iclass 25, count 2 2006.201.22:02:08.69#ibcon#about to write, iclass 25, count 2 2006.201.22:02:08.69#ibcon#wrote, iclass 25, count 2 2006.201.22:02:08.69#ibcon#about to read 3, iclass 25, count 2 2006.201.22:02:08.71#ibcon#read 3, iclass 25, count 2 2006.201.22:02:08.71#ibcon#about to read 4, iclass 25, count 2 2006.201.22:02:08.71#ibcon#read 4, iclass 25, count 2 2006.201.22:02:08.71#ibcon#about to read 5, iclass 25, count 2 2006.201.22:02:08.71#ibcon#read 5, iclass 25, count 2 2006.201.22:02:08.71#ibcon#about to read 6, iclass 25, count 2 2006.201.22:02:08.71#ibcon#read 6, iclass 25, count 2 2006.201.22:02:08.71#ibcon#end of sib2, iclass 25, count 2 2006.201.22:02:08.71#ibcon#*mode == 0, iclass 25, count 2 2006.201.22:02:08.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.22:02:08.71#ibcon#[27=AT07-04\r\n] 2006.201.22:02:08.71#ibcon#*before write, iclass 25, count 2 2006.201.22:02:08.71#ibcon#enter sib2, iclass 25, count 2 2006.201.22:02:08.71#ibcon#flushed, iclass 25, count 2 2006.201.22:02:08.71#ibcon#about to write, iclass 25, count 2 2006.201.22:02:08.71#ibcon#wrote, iclass 25, count 2 2006.201.22:02:08.71#ibcon#about to read 3, iclass 25, count 2 2006.201.22:02:08.74#ibcon#read 3, iclass 25, count 2 2006.201.22:02:08.74#ibcon#about to read 4, iclass 25, count 2 2006.201.22:02:08.74#ibcon#read 4, iclass 25, count 2 2006.201.22:02:08.74#ibcon#about to read 5, iclass 25, count 2 2006.201.22:02:08.74#ibcon#read 5, iclass 25, count 2 2006.201.22:02:08.74#ibcon#about to read 6, iclass 25, count 2 2006.201.22:02:08.74#ibcon#read 6, iclass 25, count 2 2006.201.22:02:08.74#ibcon#end of sib2, iclass 25, count 2 2006.201.22:02:08.74#ibcon#*after write, iclass 25, count 2 2006.201.22:02:08.74#ibcon#*before return 0, iclass 25, count 2 2006.201.22:02:08.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:08.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:02:08.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.22:02:08.74#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:08.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:08.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:08.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:08.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.22:02:08.86#ibcon#first serial, iclass 25, count 0 2006.201.22:02:08.86#ibcon#enter sib2, iclass 25, count 0 2006.201.22:02:08.86#ibcon#flushed, iclass 25, count 0 2006.201.22:02:08.86#ibcon#about to write, iclass 25, count 0 2006.201.22:02:08.86#ibcon#wrote, iclass 25, count 0 2006.201.22:02:08.86#ibcon#about to read 3, iclass 25, count 0 2006.201.22:02:08.88#ibcon#read 3, iclass 25, count 0 2006.201.22:02:08.88#ibcon#about to read 4, iclass 25, count 0 2006.201.22:02:08.88#ibcon#read 4, iclass 25, count 0 2006.201.22:02:08.88#ibcon#about to read 5, iclass 25, count 0 2006.201.22:02:08.88#ibcon#read 5, iclass 25, count 0 2006.201.22:02:08.88#ibcon#about to read 6, iclass 25, count 0 2006.201.22:02:08.88#ibcon#read 6, iclass 25, count 0 2006.201.22:02:08.88#ibcon#end of sib2, iclass 25, count 0 2006.201.22:02:08.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.22:02:08.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.22:02:08.88#ibcon#[27=USB\r\n] 2006.201.22:02:08.88#ibcon#*before write, iclass 25, count 0 2006.201.22:02:08.88#ibcon#enter sib2, iclass 25, count 0 2006.201.22:02:08.88#ibcon#flushed, iclass 25, count 0 2006.201.22:02:08.88#ibcon#about to write, iclass 25, count 0 2006.201.22:02:08.88#ibcon#wrote, iclass 25, count 0 2006.201.22:02:08.88#ibcon#about to read 3, iclass 25, count 0 2006.201.22:02:08.91#ibcon#read 3, iclass 25, count 0 2006.201.22:02:08.91#ibcon#about to read 4, iclass 25, count 0 2006.201.22:02:08.91#ibcon#read 4, iclass 25, count 0 2006.201.22:02:08.91#ibcon#about to read 5, iclass 25, count 0 2006.201.22:02:08.91#ibcon#read 5, iclass 25, count 0 2006.201.22:02:08.91#ibcon#about to read 6, iclass 25, count 0 2006.201.22:02:08.91#ibcon#read 6, iclass 25, count 0 2006.201.22:02:08.91#ibcon#end of sib2, iclass 25, count 0 2006.201.22:02:08.91#ibcon#*after write, iclass 25, count 0 2006.201.22:02:08.91#ibcon#*before return 0, iclass 25, count 0 2006.201.22:02:08.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:08.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:02:08.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.22:02:08.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.22:02:08.91$vck44/vblo=8,744.99 2006.201.22:02:08.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.22:02:08.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.22:02:08.91#ibcon#ireg 17 cls_cnt 0 2006.201.22:02:08.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:08.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:08.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:08.91#ibcon#enter wrdev, iclass 27, count 0 2006.201.22:02:08.91#ibcon#first serial, iclass 27, count 0 2006.201.22:02:08.91#ibcon#enter sib2, iclass 27, count 0 2006.201.22:02:08.91#ibcon#flushed, iclass 27, count 0 2006.201.22:02:08.91#ibcon#about to write, iclass 27, count 0 2006.201.22:02:08.91#ibcon#wrote, iclass 27, count 0 2006.201.22:02:08.91#ibcon#about to read 3, iclass 27, count 0 2006.201.22:02:08.93#ibcon#read 3, iclass 27, count 0 2006.201.22:02:08.93#ibcon#about to read 4, iclass 27, count 0 2006.201.22:02:08.93#ibcon#read 4, iclass 27, count 0 2006.201.22:02:08.93#ibcon#about to read 5, iclass 27, count 0 2006.201.22:02:08.93#ibcon#read 5, iclass 27, count 0 2006.201.22:02:08.93#ibcon#about to read 6, iclass 27, count 0 2006.201.22:02:08.93#ibcon#read 6, iclass 27, count 0 2006.201.22:02:08.93#ibcon#end of sib2, iclass 27, count 0 2006.201.22:02:08.93#ibcon#*mode == 0, iclass 27, count 0 2006.201.22:02:08.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.22:02:08.93#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.22:02:08.93#ibcon#*before write, iclass 27, count 0 2006.201.22:02:08.93#ibcon#enter sib2, iclass 27, count 0 2006.201.22:02:08.93#ibcon#flushed, iclass 27, count 0 2006.201.22:02:08.93#ibcon#about to write, iclass 27, count 0 2006.201.22:02:08.93#ibcon#wrote, iclass 27, count 0 2006.201.22:02:08.93#ibcon#about to read 3, iclass 27, count 0 2006.201.22:02:08.98#ibcon#read 3, iclass 27, count 0 2006.201.22:02:08.98#ibcon#about to read 4, iclass 27, count 0 2006.201.22:02:08.98#ibcon#read 4, iclass 27, count 0 2006.201.22:02:08.98#ibcon#about to read 5, iclass 27, count 0 2006.201.22:02:08.98#ibcon#read 5, iclass 27, count 0 2006.201.22:02:08.98#ibcon#about to read 6, iclass 27, count 0 2006.201.22:02:08.98#ibcon#read 6, iclass 27, count 0 2006.201.22:02:08.98#ibcon#end of sib2, iclass 27, count 0 2006.201.22:02:08.98#ibcon#*after write, iclass 27, count 0 2006.201.22:02:08.98#ibcon#*before return 0, iclass 27, count 0 2006.201.22:02:08.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:08.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:02:08.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.22:02:08.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.22:02:08.98$vck44/vb=8,4 2006.201.22:02:08.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.22:02:08.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.22:02:08.98#ibcon#ireg 11 cls_cnt 2 2006.201.22:02:08.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:09.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:09.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:09.03#ibcon#enter wrdev, iclass 29, count 2 2006.201.22:02:09.03#ibcon#first serial, iclass 29, count 2 2006.201.22:02:09.03#ibcon#enter sib2, iclass 29, count 2 2006.201.22:02:09.03#ibcon#flushed, iclass 29, count 2 2006.201.22:02:09.03#ibcon#about to write, iclass 29, count 2 2006.201.22:02:09.03#ibcon#wrote, iclass 29, count 2 2006.201.22:02:09.03#ibcon#about to read 3, iclass 29, count 2 2006.201.22:02:09.05#ibcon#read 3, iclass 29, count 2 2006.201.22:02:09.05#ibcon#about to read 4, iclass 29, count 2 2006.201.22:02:09.05#ibcon#read 4, iclass 29, count 2 2006.201.22:02:09.05#ibcon#about to read 5, iclass 29, count 2 2006.201.22:02:09.05#ibcon#read 5, iclass 29, count 2 2006.201.22:02:09.05#ibcon#about to read 6, iclass 29, count 2 2006.201.22:02:09.05#ibcon#read 6, iclass 29, count 2 2006.201.22:02:09.05#ibcon#end of sib2, iclass 29, count 2 2006.201.22:02:09.05#ibcon#*mode == 0, iclass 29, count 2 2006.201.22:02:09.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.22:02:09.05#ibcon#[27=AT08-04\r\n] 2006.201.22:02:09.05#ibcon#*before write, iclass 29, count 2 2006.201.22:02:09.05#ibcon#enter sib2, iclass 29, count 2 2006.201.22:02:09.05#ibcon#flushed, iclass 29, count 2 2006.201.22:02:09.05#ibcon#about to write, iclass 29, count 2 2006.201.22:02:09.05#ibcon#wrote, iclass 29, count 2 2006.201.22:02:09.05#ibcon#about to read 3, iclass 29, count 2 2006.201.22:02:09.08#ibcon#read 3, iclass 29, count 2 2006.201.22:02:09.08#ibcon#about to read 4, iclass 29, count 2 2006.201.22:02:09.08#ibcon#read 4, iclass 29, count 2 2006.201.22:02:09.08#ibcon#about to read 5, iclass 29, count 2 2006.201.22:02:09.08#ibcon#read 5, iclass 29, count 2 2006.201.22:02:09.08#ibcon#about to read 6, iclass 29, count 2 2006.201.22:02:09.08#ibcon#read 6, iclass 29, count 2 2006.201.22:02:09.08#ibcon#end of sib2, iclass 29, count 2 2006.201.22:02:09.08#ibcon#*after write, iclass 29, count 2 2006.201.22:02:09.08#ibcon#*before return 0, iclass 29, count 2 2006.201.22:02:09.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:09.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:02:09.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.22:02:09.08#ibcon#ireg 7 cls_cnt 0 2006.201.22:02:09.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:09.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:09.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:09.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.22:02:09.20#ibcon#first serial, iclass 29, count 0 2006.201.22:02:09.20#ibcon#enter sib2, iclass 29, count 0 2006.201.22:02:09.20#ibcon#flushed, iclass 29, count 0 2006.201.22:02:09.20#ibcon#about to write, iclass 29, count 0 2006.201.22:02:09.20#ibcon#wrote, iclass 29, count 0 2006.201.22:02:09.20#ibcon#about to read 3, iclass 29, count 0 2006.201.22:02:09.22#ibcon#read 3, iclass 29, count 0 2006.201.22:02:09.22#ibcon#about to read 4, iclass 29, count 0 2006.201.22:02:09.22#ibcon#read 4, iclass 29, count 0 2006.201.22:02:09.22#ibcon#about to read 5, iclass 29, count 0 2006.201.22:02:09.22#ibcon#read 5, iclass 29, count 0 2006.201.22:02:09.22#ibcon#about to read 6, iclass 29, count 0 2006.201.22:02:09.22#ibcon#read 6, iclass 29, count 0 2006.201.22:02:09.22#ibcon#end of sib2, iclass 29, count 0 2006.201.22:02:09.22#ibcon#*mode == 0, iclass 29, count 0 2006.201.22:02:09.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.22:02:09.22#ibcon#[27=USB\r\n] 2006.201.22:02:09.22#ibcon#*before write, iclass 29, count 0 2006.201.22:02:09.22#ibcon#enter sib2, iclass 29, count 0 2006.201.22:02:09.22#ibcon#flushed, iclass 29, count 0 2006.201.22:02:09.22#ibcon#about to write, iclass 29, count 0 2006.201.22:02:09.22#ibcon#wrote, iclass 29, count 0 2006.201.22:02:09.22#ibcon#about to read 3, iclass 29, count 0 2006.201.22:02:09.25#ibcon#read 3, iclass 29, count 0 2006.201.22:02:09.25#ibcon#about to read 4, iclass 29, count 0 2006.201.22:02:09.25#ibcon#read 4, iclass 29, count 0 2006.201.22:02:09.25#ibcon#about to read 5, iclass 29, count 0 2006.201.22:02:09.25#ibcon#read 5, iclass 29, count 0 2006.201.22:02:09.25#ibcon#about to read 6, iclass 29, count 0 2006.201.22:02:09.25#ibcon#read 6, iclass 29, count 0 2006.201.22:02:09.25#ibcon#end of sib2, iclass 29, count 0 2006.201.22:02:09.25#ibcon#*after write, iclass 29, count 0 2006.201.22:02:09.25#ibcon#*before return 0, iclass 29, count 0 2006.201.22:02:09.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:09.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:02:09.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.22:02:09.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.22:02:09.25$vck44/vabw=wide 2006.201.22:02:09.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.22:02:09.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.22:02:09.25#ibcon#ireg 8 cls_cnt 0 2006.201.22:02:09.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:09.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:09.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:09.25#ibcon#enter wrdev, iclass 31, count 0 2006.201.22:02:09.25#ibcon#first serial, iclass 31, count 0 2006.201.22:02:09.25#ibcon#enter sib2, iclass 31, count 0 2006.201.22:02:09.25#ibcon#flushed, iclass 31, count 0 2006.201.22:02:09.25#ibcon#about to write, iclass 31, count 0 2006.201.22:02:09.25#ibcon#wrote, iclass 31, count 0 2006.201.22:02:09.25#ibcon#about to read 3, iclass 31, count 0 2006.201.22:02:09.27#ibcon#read 3, iclass 31, count 0 2006.201.22:02:09.27#ibcon#about to read 4, iclass 31, count 0 2006.201.22:02:09.27#ibcon#read 4, iclass 31, count 0 2006.201.22:02:09.27#ibcon#about to read 5, iclass 31, count 0 2006.201.22:02:09.27#ibcon#read 5, iclass 31, count 0 2006.201.22:02:09.27#ibcon#about to read 6, iclass 31, count 0 2006.201.22:02:09.27#ibcon#read 6, iclass 31, count 0 2006.201.22:02:09.27#ibcon#end of sib2, iclass 31, count 0 2006.201.22:02:09.27#ibcon#*mode == 0, iclass 31, count 0 2006.201.22:02:09.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.22:02:09.27#ibcon#[25=BW32\r\n] 2006.201.22:02:09.27#ibcon#*before write, iclass 31, count 0 2006.201.22:02:09.27#ibcon#enter sib2, iclass 31, count 0 2006.201.22:02:09.27#ibcon#flushed, iclass 31, count 0 2006.201.22:02:09.27#ibcon#about to write, iclass 31, count 0 2006.201.22:02:09.27#ibcon#wrote, iclass 31, count 0 2006.201.22:02:09.27#ibcon#about to read 3, iclass 31, count 0 2006.201.22:02:09.30#ibcon#read 3, iclass 31, count 0 2006.201.22:02:09.30#ibcon#about to read 4, iclass 31, count 0 2006.201.22:02:09.30#ibcon#read 4, iclass 31, count 0 2006.201.22:02:09.30#ibcon#about to read 5, iclass 31, count 0 2006.201.22:02:09.30#ibcon#read 5, iclass 31, count 0 2006.201.22:02:09.30#ibcon#about to read 6, iclass 31, count 0 2006.201.22:02:09.30#ibcon#read 6, iclass 31, count 0 2006.201.22:02:09.30#ibcon#end of sib2, iclass 31, count 0 2006.201.22:02:09.30#ibcon#*after write, iclass 31, count 0 2006.201.22:02:09.30#ibcon#*before return 0, iclass 31, count 0 2006.201.22:02:09.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:09.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:02:09.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.22:02:09.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.22:02:09.30$vck44/vbbw=wide 2006.201.22:02:09.30#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.22:02:09.30#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.22:02:09.30#ibcon#ireg 8 cls_cnt 0 2006.201.22:02:09.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:02:09.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:02:09.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:02:09.37#ibcon#enter wrdev, iclass 33, count 0 2006.201.22:02:09.37#ibcon#first serial, iclass 33, count 0 2006.201.22:02:09.37#ibcon#enter sib2, iclass 33, count 0 2006.201.22:02:09.37#ibcon#flushed, iclass 33, count 0 2006.201.22:02:09.37#ibcon#about to write, iclass 33, count 0 2006.201.22:02:09.37#ibcon#wrote, iclass 33, count 0 2006.201.22:02:09.37#ibcon#about to read 3, iclass 33, count 0 2006.201.22:02:09.39#ibcon#read 3, iclass 33, count 0 2006.201.22:02:09.39#ibcon#about to read 4, iclass 33, count 0 2006.201.22:02:09.39#ibcon#read 4, iclass 33, count 0 2006.201.22:02:09.39#ibcon#about to read 5, iclass 33, count 0 2006.201.22:02:09.39#ibcon#read 5, iclass 33, count 0 2006.201.22:02:09.39#ibcon#about to read 6, iclass 33, count 0 2006.201.22:02:09.39#ibcon#read 6, iclass 33, count 0 2006.201.22:02:09.39#ibcon#end of sib2, iclass 33, count 0 2006.201.22:02:09.39#ibcon#*mode == 0, iclass 33, count 0 2006.201.22:02:09.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.22:02:09.39#ibcon#[27=BW32\r\n] 2006.201.22:02:09.39#ibcon#*before write, iclass 33, count 0 2006.201.22:02:09.39#ibcon#enter sib2, iclass 33, count 0 2006.201.22:02:09.39#ibcon#flushed, iclass 33, count 0 2006.201.22:02:09.39#ibcon#about to write, iclass 33, count 0 2006.201.22:02:09.39#ibcon#wrote, iclass 33, count 0 2006.201.22:02:09.39#ibcon#about to read 3, iclass 33, count 0 2006.201.22:02:09.42#ibcon#read 3, iclass 33, count 0 2006.201.22:02:09.42#ibcon#about to read 4, iclass 33, count 0 2006.201.22:02:09.42#ibcon#read 4, iclass 33, count 0 2006.201.22:02:09.42#ibcon#about to read 5, iclass 33, count 0 2006.201.22:02:09.42#ibcon#read 5, iclass 33, count 0 2006.201.22:02:09.42#ibcon#about to read 6, iclass 33, count 0 2006.201.22:02:09.42#ibcon#read 6, iclass 33, count 0 2006.201.22:02:09.42#ibcon#end of sib2, iclass 33, count 0 2006.201.22:02:09.42#ibcon#*after write, iclass 33, count 0 2006.201.22:02:09.42#ibcon#*before return 0, iclass 33, count 0 2006.201.22:02:09.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:02:09.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:02:09.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.22:02:09.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.22:02:09.42$setupk4/ifdk4 2006.201.22:02:09.42$ifdk4/lo= 2006.201.22:02:09.42$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.22:02:09.42$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.22:02:09.42$ifdk4/patch= 2006.201.22:02:09.42$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.22:02:09.42$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.22:02:09.42$setupk4/!*+20s 2006.201.22:02:09.50#abcon#<5=/05 1.9 2.9 19.961001001.4\r\n> 2006.201.22:02:09.52#abcon#{5=INTERFACE CLEAR} 2006.201.22:02:09.58#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:02:19.67#abcon#<5=/05 1.9 2.9 19.961001001.4\r\n> 2006.201.22:02:19.69#abcon#{5=INTERFACE CLEAR} 2006.201.22:02:19.75#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:02:23.89$setupk4/"tpicd 2006.201.22:02:23.89$setupk4/echo=off 2006.201.22:02:23.89$setupk4/xlog=off 2006.201.22:02:23.89:!2006.201.22:04:32 2006.201.22:02:25.14#trakl#Source acquired 2006.201.22:02:27.14#flagr#flagr/antenna,acquired 2006.201.22:04:32.00:preob 2006.201.22:04:32.14/onsource/TRACKING 2006.201.22:04:32.14:!2006.201.22:04:42 2006.201.22:04:42.00:"tape 2006.201.22:04:42.00:"st=record 2006.201.22:04:42.00:data_valid=on 2006.201.22:04:42.00:midob 2006.201.22:04:42.14/onsource/TRACKING 2006.201.22:04:42.14/wx/19.97,1001.4,100 2006.201.22:04:42.26/cable/+6.4831E-03 2006.201.22:04:43.35/va/01,08,usb,yes,55,59 2006.201.22:04:43.35/va/02,07,usb,yes,60,61 2006.201.22:04:43.35/va/03,08,usb,yes,54,57 2006.201.22:04:43.35/va/04,07,usb,yes,61,65 2006.201.22:04:43.35/va/05,04,usb,yes,55,56 2006.201.22:04:43.35/va/06,05,usb,yes,55,55 2006.201.22:04:43.35/va/07,05,usb,yes,54,56 2006.201.22:04:43.35/va/08,04,usb,yes,54,63 2006.201.22:04:43.58/valo/01,524.99,yes,locked 2006.201.22:04:43.58/valo/02,534.99,yes,locked 2006.201.22:04:43.58/valo/03,564.99,yes,locked 2006.201.22:04:43.58/valo/04,624.99,yes,locked 2006.201.22:04:43.58/valo/05,734.99,yes,locked 2006.201.22:04:43.58/valo/06,814.99,yes,locked 2006.201.22:04:43.58/valo/07,864.99,yes,locked 2006.201.22:04:43.58/valo/08,884.99,yes,locked 2006.201.22:04:44.67/vb/01,04,usb,yes,32,29 2006.201.22:04:44.67/vb/02,05,usb,yes,30,30 2006.201.22:04:44.67/vb/03,04,usb,yes,31,34 2006.201.22:04:44.67/vb/04,05,usb,yes,31,30 2006.201.22:04:44.67/vb/05,04,usb,yes,28,30 2006.201.22:04:44.67/vb/06,04,usb,yes,32,28 2006.201.22:04:44.67/vb/07,04,usb,yes,32,32 2006.201.22:04:44.67/vb/08,04,usb,yes,30,33 2006.201.22:04:44.90/vblo/01,629.99,yes,locked 2006.201.22:04:44.90/vblo/02,634.99,yes,locked 2006.201.22:04:44.90/vblo/03,649.99,yes,locked 2006.201.22:04:44.90/vblo/04,679.99,yes,locked 2006.201.22:04:44.90/vblo/05,709.99,yes,locked 2006.201.22:04:44.90/vblo/06,719.99,yes,locked 2006.201.22:04:44.90/vblo/07,734.99,yes,locked 2006.201.22:04:44.90/vblo/08,744.99,yes,locked 2006.201.22:04:45.05/vabw/8 2006.201.22:04:45.20/vbbw/8 2006.201.22:04:45.31/xfe/off,on,15.0 2006.201.22:04:45.69/ifatt/23,28,28,28 2006.201.22:04:46.07/fmout-gps/S +4.56E-07 2006.201.22:04:46.14:!2006.201.22:08:32 2006.201.22:08:32.00:data_valid=off 2006.201.22:08:32.00:"et 2006.201.22:08:32.00:!+3s 2006.201.22:08:35.02:"tape 2006.201.22:08:35.02:postob 2006.201.22:08:35.22/cable/+6.4818E-03 2006.201.22:08:35.22/wx/19.98,1001.6,100 2006.201.22:08:35.30/fmout-gps/S +4.59E-07 2006.201.22:08:35.30:scan_name=201-2225,jd0607,150 2006.201.22:08:35.30:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.22:08:36.13#flagr#flagr/antenna,new-source 2006.201.22:08:36.13:checkk5 2006.201.22:08:36.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.22:08:36.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.22:08:37.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.22:08:37.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.22:08:38.01/chk_obsdata//k5ts1/T2012204??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.22:08:38.37/chk_obsdata//k5ts2/T2012204??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.22:08:38.74/chk_obsdata//k5ts3/T2012204??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.22:08:39.12/chk_obsdata//k5ts4/T2012204??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.22:08:39.82/k5log//k5ts1_log_newline 2006.201.22:08:40.52/k5log//k5ts2_log_newline 2006.201.22:08:41.22/k5log//k5ts3_log_newline 2006.201.22:08:41.91/k5log//k5ts4_log_newline 2006.201.22:08:41.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.22:08:41.93:setupk4=1 2006.201.22:08:41.93$setupk4/echo=on 2006.201.22:08:41.93$setupk4/pcalon 2006.201.22:08:41.93$pcalon/"no phase cal control is implemented here 2006.201.22:08:41.93$setupk4/"tpicd=stop 2006.201.22:08:41.93$setupk4/"rec=synch_on 2006.201.22:08:41.93$setupk4/"rec_mode=128 2006.201.22:08:41.93$setupk4/!* 2006.201.22:08:41.94$setupk4/recpk4 2006.201.22:08:41.94$recpk4/recpatch= 2006.201.22:08:41.94$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.22:08:41.94$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.22:08:41.94$setupk4/vck44 2006.201.22:08:41.94$vck44/valo=1,524.99 2006.201.22:08:41.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.22:08:41.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.22:08:41.94#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:41.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:41.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:41.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:41.94#ibcon#enter wrdev, iclass 14, count 0 2006.201.22:08:41.94#ibcon#first serial, iclass 14, count 0 2006.201.22:08:41.94#ibcon#enter sib2, iclass 14, count 0 2006.201.22:08:41.94#ibcon#flushed, iclass 14, count 0 2006.201.22:08:41.94#ibcon#about to write, iclass 14, count 0 2006.201.22:08:41.94#ibcon#wrote, iclass 14, count 0 2006.201.22:08:41.94#ibcon#about to read 3, iclass 14, count 0 2006.201.22:08:41.98#ibcon#read 3, iclass 14, count 0 2006.201.22:08:41.98#ibcon#about to read 4, iclass 14, count 0 2006.201.22:08:41.98#ibcon#read 4, iclass 14, count 0 2006.201.22:08:41.98#ibcon#about to read 5, iclass 14, count 0 2006.201.22:08:41.98#ibcon#read 5, iclass 14, count 0 2006.201.22:08:41.98#ibcon#about to read 6, iclass 14, count 0 2006.201.22:08:41.98#ibcon#read 6, iclass 14, count 0 2006.201.22:08:41.98#ibcon#end of sib2, iclass 14, count 0 2006.201.22:08:41.98#ibcon#*mode == 0, iclass 14, count 0 2006.201.22:08:41.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.22:08:41.98#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.22:08:41.98#ibcon#*before write, iclass 14, count 0 2006.201.22:08:41.98#ibcon#enter sib2, iclass 14, count 0 2006.201.22:08:41.98#ibcon#flushed, iclass 14, count 0 2006.201.22:08:41.98#ibcon#about to write, iclass 14, count 0 2006.201.22:08:41.98#ibcon#wrote, iclass 14, count 0 2006.201.22:08:41.98#ibcon#about to read 3, iclass 14, count 0 2006.201.22:08:42.03#ibcon#read 3, iclass 14, count 0 2006.201.22:08:42.03#ibcon#about to read 4, iclass 14, count 0 2006.201.22:08:42.03#ibcon#read 4, iclass 14, count 0 2006.201.22:08:42.03#ibcon#about to read 5, iclass 14, count 0 2006.201.22:08:42.03#ibcon#read 5, iclass 14, count 0 2006.201.22:08:42.03#ibcon#about to read 6, iclass 14, count 0 2006.201.22:08:42.03#ibcon#read 6, iclass 14, count 0 2006.201.22:08:42.03#ibcon#end of sib2, iclass 14, count 0 2006.201.22:08:42.03#ibcon#*after write, iclass 14, count 0 2006.201.22:08:42.03#ibcon#*before return 0, iclass 14, count 0 2006.201.22:08:42.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:42.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:42.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.22:08:42.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.22:08:42.03$vck44/va=1,8 2006.201.22:08:42.03#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.22:08:42.03#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.22:08:42.03#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:42.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:42.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:42.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:42.03#ibcon#enter wrdev, iclass 16, count 2 2006.201.22:08:42.03#ibcon#first serial, iclass 16, count 2 2006.201.22:08:42.03#ibcon#enter sib2, iclass 16, count 2 2006.201.22:08:42.03#ibcon#flushed, iclass 16, count 2 2006.201.22:08:42.03#ibcon#about to write, iclass 16, count 2 2006.201.22:08:42.03#ibcon#wrote, iclass 16, count 2 2006.201.22:08:42.03#ibcon#about to read 3, iclass 16, count 2 2006.201.22:08:42.05#ibcon#read 3, iclass 16, count 2 2006.201.22:08:42.05#ibcon#about to read 4, iclass 16, count 2 2006.201.22:08:42.05#ibcon#read 4, iclass 16, count 2 2006.201.22:08:42.05#ibcon#about to read 5, iclass 16, count 2 2006.201.22:08:42.05#ibcon#read 5, iclass 16, count 2 2006.201.22:08:42.05#ibcon#about to read 6, iclass 16, count 2 2006.201.22:08:42.05#ibcon#read 6, iclass 16, count 2 2006.201.22:08:42.05#ibcon#end of sib2, iclass 16, count 2 2006.201.22:08:42.05#ibcon#*mode == 0, iclass 16, count 2 2006.201.22:08:42.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.22:08:42.05#ibcon#[25=AT01-08\r\n] 2006.201.22:08:42.05#ibcon#*before write, iclass 16, count 2 2006.201.22:08:42.05#ibcon#enter sib2, iclass 16, count 2 2006.201.22:08:42.05#ibcon#flushed, iclass 16, count 2 2006.201.22:08:42.05#ibcon#about to write, iclass 16, count 2 2006.201.22:08:42.05#ibcon#wrote, iclass 16, count 2 2006.201.22:08:42.05#ibcon#about to read 3, iclass 16, count 2 2006.201.22:08:42.09#ibcon#read 3, iclass 16, count 2 2006.201.22:08:42.09#ibcon#about to read 4, iclass 16, count 2 2006.201.22:08:42.09#ibcon#read 4, iclass 16, count 2 2006.201.22:08:42.09#ibcon#about to read 5, iclass 16, count 2 2006.201.22:08:42.09#ibcon#read 5, iclass 16, count 2 2006.201.22:08:42.09#ibcon#about to read 6, iclass 16, count 2 2006.201.22:08:42.09#ibcon#read 6, iclass 16, count 2 2006.201.22:08:42.09#ibcon#end of sib2, iclass 16, count 2 2006.201.22:08:42.09#ibcon#*after write, iclass 16, count 2 2006.201.22:08:42.09#ibcon#*before return 0, iclass 16, count 2 2006.201.22:08:42.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:42.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:42.09#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.22:08:42.09#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:42.09#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:42.21#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:42.21#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:42.21#ibcon#enter wrdev, iclass 16, count 0 2006.201.22:08:42.21#ibcon#first serial, iclass 16, count 0 2006.201.22:08:42.21#ibcon#enter sib2, iclass 16, count 0 2006.201.22:08:42.21#ibcon#flushed, iclass 16, count 0 2006.201.22:08:42.21#ibcon#about to write, iclass 16, count 0 2006.201.22:08:42.21#ibcon#wrote, iclass 16, count 0 2006.201.22:08:42.21#ibcon#about to read 3, iclass 16, count 0 2006.201.22:08:42.23#ibcon#read 3, iclass 16, count 0 2006.201.22:08:42.23#ibcon#about to read 4, iclass 16, count 0 2006.201.22:08:42.23#ibcon#read 4, iclass 16, count 0 2006.201.22:08:42.23#ibcon#about to read 5, iclass 16, count 0 2006.201.22:08:42.23#ibcon#read 5, iclass 16, count 0 2006.201.22:08:42.23#ibcon#about to read 6, iclass 16, count 0 2006.201.22:08:42.23#ibcon#read 6, iclass 16, count 0 2006.201.22:08:42.23#ibcon#end of sib2, iclass 16, count 0 2006.201.22:08:42.23#ibcon#*mode == 0, iclass 16, count 0 2006.201.22:08:42.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.22:08:42.23#ibcon#[25=USB\r\n] 2006.201.22:08:42.23#ibcon#*before write, iclass 16, count 0 2006.201.22:08:42.23#ibcon#enter sib2, iclass 16, count 0 2006.201.22:08:42.23#ibcon#flushed, iclass 16, count 0 2006.201.22:08:42.23#ibcon#about to write, iclass 16, count 0 2006.201.22:08:42.23#ibcon#wrote, iclass 16, count 0 2006.201.22:08:42.23#ibcon#about to read 3, iclass 16, count 0 2006.201.22:08:42.26#ibcon#read 3, iclass 16, count 0 2006.201.22:08:42.26#ibcon#about to read 4, iclass 16, count 0 2006.201.22:08:42.26#ibcon#read 4, iclass 16, count 0 2006.201.22:08:42.26#ibcon#about to read 5, iclass 16, count 0 2006.201.22:08:42.26#ibcon#read 5, iclass 16, count 0 2006.201.22:08:42.26#ibcon#about to read 6, iclass 16, count 0 2006.201.22:08:42.26#ibcon#read 6, iclass 16, count 0 2006.201.22:08:42.26#ibcon#end of sib2, iclass 16, count 0 2006.201.22:08:42.26#ibcon#*after write, iclass 16, count 0 2006.201.22:08:42.26#ibcon#*before return 0, iclass 16, count 0 2006.201.22:08:42.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:42.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:42.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.22:08:42.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.22:08:42.26$vck44/valo=2,534.99 2006.201.22:08:42.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.22:08:42.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.22:08:42.26#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:42.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:42.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:42.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:42.26#ibcon#enter wrdev, iclass 18, count 0 2006.201.22:08:42.26#ibcon#first serial, iclass 18, count 0 2006.201.22:08:42.26#ibcon#enter sib2, iclass 18, count 0 2006.201.22:08:42.26#ibcon#flushed, iclass 18, count 0 2006.201.22:08:42.26#ibcon#about to write, iclass 18, count 0 2006.201.22:08:42.26#ibcon#wrote, iclass 18, count 0 2006.201.22:08:42.26#ibcon#about to read 3, iclass 18, count 0 2006.201.22:08:42.28#ibcon#read 3, iclass 18, count 0 2006.201.22:08:42.28#ibcon#about to read 4, iclass 18, count 0 2006.201.22:08:42.28#ibcon#read 4, iclass 18, count 0 2006.201.22:08:42.28#ibcon#about to read 5, iclass 18, count 0 2006.201.22:08:42.28#ibcon#read 5, iclass 18, count 0 2006.201.22:08:42.28#ibcon#about to read 6, iclass 18, count 0 2006.201.22:08:42.28#ibcon#read 6, iclass 18, count 0 2006.201.22:08:42.28#ibcon#end of sib2, iclass 18, count 0 2006.201.22:08:42.28#ibcon#*mode == 0, iclass 18, count 0 2006.201.22:08:42.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.22:08:42.28#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.22:08:42.28#ibcon#*before write, iclass 18, count 0 2006.201.22:08:42.28#ibcon#enter sib2, iclass 18, count 0 2006.201.22:08:42.28#ibcon#flushed, iclass 18, count 0 2006.201.22:08:42.28#ibcon#about to write, iclass 18, count 0 2006.201.22:08:42.28#ibcon#wrote, iclass 18, count 0 2006.201.22:08:42.28#ibcon#about to read 3, iclass 18, count 0 2006.201.22:08:42.33#ibcon#read 3, iclass 18, count 0 2006.201.22:08:42.33#ibcon#about to read 4, iclass 18, count 0 2006.201.22:08:42.33#ibcon#read 4, iclass 18, count 0 2006.201.22:08:42.33#ibcon#about to read 5, iclass 18, count 0 2006.201.22:08:42.33#ibcon#read 5, iclass 18, count 0 2006.201.22:08:42.33#ibcon#about to read 6, iclass 18, count 0 2006.201.22:08:42.33#ibcon#read 6, iclass 18, count 0 2006.201.22:08:42.33#ibcon#end of sib2, iclass 18, count 0 2006.201.22:08:42.33#ibcon#*after write, iclass 18, count 0 2006.201.22:08:42.33#ibcon#*before return 0, iclass 18, count 0 2006.201.22:08:42.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:42.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:42.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.22:08:42.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.22:08:42.33$vck44/va=2,7 2006.201.22:08:42.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.22:08:42.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.22:08:42.33#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:42.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:42.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:42.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:42.38#ibcon#enter wrdev, iclass 20, count 2 2006.201.22:08:42.38#ibcon#first serial, iclass 20, count 2 2006.201.22:08:42.38#ibcon#enter sib2, iclass 20, count 2 2006.201.22:08:42.38#ibcon#flushed, iclass 20, count 2 2006.201.22:08:42.38#ibcon#about to write, iclass 20, count 2 2006.201.22:08:42.38#ibcon#wrote, iclass 20, count 2 2006.201.22:08:42.38#ibcon#about to read 3, iclass 20, count 2 2006.201.22:08:42.40#ibcon#read 3, iclass 20, count 2 2006.201.22:08:42.40#ibcon#about to read 4, iclass 20, count 2 2006.201.22:08:42.40#ibcon#read 4, iclass 20, count 2 2006.201.22:08:42.40#ibcon#about to read 5, iclass 20, count 2 2006.201.22:08:42.40#ibcon#read 5, iclass 20, count 2 2006.201.22:08:42.40#ibcon#about to read 6, iclass 20, count 2 2006.201.22:08:42.40#ibcon#read 6, iclass 20, count 2 2006.201.22:08:42.40#ibcon#end of sib2, iclass 20, count 2 2006.201.22:08:42.40#ibcon#*mode == 0, iclass 20, count 2 2006.201.22:08:42.40#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.22:08:42.40#ibcon#[25=AT02-07\r\n] 2006.201.22:08:42.40#ibcon#*before write, iclass 20, count 2 2006.201.22:08:42.40#ibcon#enter sib2, iclass 20, count 2 2006.201.22:08:42.40#ibcon#flushed, iclass 20, count 2 2006.201.22:08:42.40#ibcon#about to write, iclass 20, count 2 2006.201.22:08:42.40#ibcon#wrote, iclass 20, count 2 2006.201.22:08:42.40#ibcon#about to read 3, iclass 20, count 2 2006.201.22:08:42.43#ibcon#read 3, iclass 20, count 2 2006.201.22:08:42.43#ibcon#about to read 4, iclass 20, count 2 2006.201.22:08:42.43#ibcon#read 4, iclass 20, count 2 2006.201.22:08:42.43#ibcon#about to read 5, iclass 20, count 2 2006.201.22:08:42.43#ibcon#read 5, iclass 20, count 2 2006.201.22:08:42.43#ibcon#about to read 6, iclass 20, count 2 2006.201.22:08:42.43#ibcon#read 6, iclass 20, count 2 2006.201.22:08:42.43#ibcon#end of sib2, iclass 20, count 2 2006.201.22:08:42.43#ibcon#*after write, iclass 20, count 2 2006.201.22:08:42.43#ibcon#*before return 0, iclass 20, count 2 2006.201.22:08:42.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:42.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:42.43#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.22:08:42.43#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:42.43#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:42.55#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:42.55#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:42.55#ibcon#enter wrdev, iclass 20, count 0 2006.201.22:08:42.55#ibcon#first serial, iclass 20, count 0 2006.201.22:08:42.55#ibcon#enter sib2, iclass 20, count 0 2006.201.22:08:42.55#ibcon#flushed, iclass 20, count 0 2006.201.22:08:42.55#ibcon#about to write, iclass 20, count 0 2006.201.22:08:42.55#ibcon#wrote, iclass 20, count 0 2006.201.22:08:42.55#ibcon#about to read 3, iclass 20, count 0 2006.201.22:08:42.57#ibcon#read 3, iclass 20, count 0 2006.201.22:08:42.57#ibcon#about to read 4, iclass 20, count 0 2006.201.22:08:42.57#ibcon#read 4, iclass 20, count 0 2006.201.22:08:42.57#ibcon#about to read 5, iclass 20, count 0 2006.201.22:08:42.57#ibcon#read 5, iclass 20, count 0 2006.201.22:08:42.57#ibcon#about to read 6, iclass 20, count 0 2006.201.22:08:42.57#ibcon#read 6, iclass 20, count 0 2006.201.22:08:42.57#ibcon#end of sib2, iclass 20, count 0 2006.201.22:08:42.57#ibcon#*mode == 0, iclass 20, count 0 2006.201.22:08:42.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.22:08:42.57#ibcon#[25=USB\r\n] 2006.201.22:08:42.57#ibcon#*before write, iclass 20, count 0 2006.201.22:08:42.57#ibcon#enter sib2, iclass 20, count 0 2006.201.22:08:42.57#ibcon#flushed, iclass 20, count 0 2006.201.22:08:42.57#ibcon#about to write, iclass 20, count 0 2006.201.22:08:42.57#ibcon#wrote, iclass 20, count 0 2006.201.22:08:42.57#ibcon#about to read 3, iclass 20, count 0 2006.201.22:08:42.60#ibcon#read 3, iclass 20, count 0 2006.201.22:08:42.60#ibcon#about to read 4, iclass 20, count 0 2006.201.22:08:42.60#ibcon#read 4, iclass 20, count 0 2006.201.22:08:42.60#ibcon#about to read 5, iclass 20, count 0 2006.201.22:08:42.60#ibcon#read 5, iclass 20, count 0 2006.201.22:08:42.60#ibcon#about to read 6, iclass 20, count 0 2006.201.22:08:42.60#ibcon#read 6, iclass 20, count 0 2006.201.22:08:42.60#ibcon#end of sib2, iclass 20, count 0 2006.201.22:08:42.60#ibcon#*after write, iclass 20, count 0 2006.201.22:08:42.60#ibcon#*before return 0, iclass 20, count 0 2006.201.22:08:42.60#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:42.60#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:42.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.22:08:42.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.22:08:42.60$vck44/valo=3,564.99 2006.201.22:08:42.60#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.22:08:42.60#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.22:08:42.60#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:42.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:42.60#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:42.60#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:42.60#ibcon#enter wrdev, iclass 22, count 0 2006.201.22:08:42.60#ibcon#first serial, iclass 22, count 0 2006.201.22:08:42.60#ibcon#enter sib2, iclass 22, count 0 2006.201.22:08:42.60#ibcon#flushed, iclass 22, count 0 2006.201.22:08:42.60#ibcon#about to write, iclass 22, count 0 2006.201.22:08:42.60#ibcon#wrote, iclass 22, count 0 2006.201.22:08:42.60#ibcon#about to read 3, iclass 22, count 0 2006.201.22:08:42.62#ibcon#read 3, iclass 22, count 0 2006.201.22:08:42.62#ibcon#about to read 4, iclass 22, count 0 2006.201.22:08:42.62#ibcon#read 4, iclass 22, count 0 2006.201.22:08:42.62#ibcon#about to read 5, iclass 22, count 0 2006.201.22:08:42.62#ibcon#read 5, iclass 22, count 0 2006.201.22:08:42.62#ibcon#about to read 6, iclass 22, count 0 2006.201.22:08:42.62#ibcon#read 6, iclass 22, count 0 2006.201.22:08:42.62#ibcon#end of sib2, iclass 22, count 0 2006.201.22:08:42.62#ibcon#*mode == 0, iclass 22, count 0 2006.201.22:08:42.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.22:08:42.62#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.22:08:42.62#ibcon#*before write, iclass 22, count 0 2006.201.22:08:42.62#ibcon#enter sib2, iclass 22, count 0 2006.201.22:08:42.62#ibcon#flushed, iclass 22, count 0 2006.201.22:08:42.62#ibcon#about to write, iclass 22, count 0 2006.201.22:08:42.62#ibcon#wrote, iclass 22, count 0 2006.201.22:08:42.62#ibcon#about to read 3, iclass 22, count 0 2006.201.22:08:42.67#ibcon#read 3, iclass 22, count 0 2006.201.22:08:42.67#ibcon#about to read 4, iclass 22, count 0 2006.201.22:08:42.67#ibcon#read 4, iclass 22, count 0 2006.201.22:08:42.67#ibcon#about to read 5, iclass 22, count 0 2006.201.22:08:42.67#ibcon#read 5, iclass 22, count 0 2006.201.22:08:42.67#ibcon#about to read 6, iclass 22, count 0 2006.201.22:08:42.67#ibcon#read 6, iclass 22, count 0 2006.201.22:08:42.67#ibcon#end of sib2, iclass 22, count 0 2006.201.22:08:42.67#ibcon#*after write, iclass 22, count 0 2006.201.22:08:42.67#ibcon#*before return 0, iclass 22, count 0 2006.201.22:08:42.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:42.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:42.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.22:08:42.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.22:08:42.67$vck44/va=3,8 2006.201.22:08:42.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.22:08:42.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.22:08:42.67#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:42.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:42.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:42.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:42.72#ibcon#enter wrdev, iclass 24, count 2 2006.201.22:08:42.72#ibcon#first serial, iclass 24, count 2 2006.201.22:08:42.72#ibcon#enter sib2, iclass 24, count 2 2006.201.22:08:42.72#ibcon#flushed, iclass 24, count 2 2006.201.22:08:42.72#ibcon#about to write, iclass 24, count 2 2006.201.22:08:42.72#ibcon#wrote, iclass 24, count 2 2006.201.22:08:42.72#ibcon#about to read 3, iclass 24, count 2 2006.201.22:08:42.74#ibcon#read 3, iclass 24, count 2 2006.201.22:08:42.74#ibcon#about to read 4, iclass 24, count 2 2006.201.22:08:42.74#ibcon#read 4, iclass 24, count 2 2006.201.22:08:42.74#ibcon#about to read 5, iclass 24, count 2 2006.201.22:08:42.74#ibcon#read 5, iclass 24, count 2 2006.201.22:08:42.74#ibcon#about to read 6, iclass 24, count 2 2006.201.22:08:42.74#ibcon#read 6, iclass 24, count 2 2006.201.22:08:42.74#ibcon#end of sib2, iclass 24, count 2 2006.201.22:08:42.74#ibcon#*mode == 0, iclass 24, count 2 2006.201.22:08:42.74#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.22:08:42.74#ibcon#[25=AT03-08\r\n] 2006.201.22:08:42.74#ibcon#*before write, iclass 24, count 2 2006.201.22:08:42.74#ibcon#enter sib2, iclass 24, count 2 2006.201.22:08:42.74#ibcon#flushed, iclass 24, count 2 2006.201.22:08:42.74#ibcon#about to write, iclass 24, count 2 2006.201.22:08:42.74#ibcon#wrote, iclass 24, count 2 2006.201.22:08:42.74#ibcon#about to read 3, iclass 24, count 2 2006.201.22:08:42.77#ibcon#read 3, iclass 24, count 2 2006.201.22:08:42.77#ibcon#about to read 4, iclass 24, count 2 2006.201.22:08:42.77#ibcon#read 4, iclass 24, count 2 2006.201.22:08:42.77#ibcon#about to read 5, iclass 24, count 2 2006.201.22:08:42.77#ibcon#read 5, iclass 24, count 2 2006.201.22:08:42.77#ibcon#about to read 6, iclass 24, count 2 2006.201.22:08:42.77#ibcon#read 6, iclass 24, count 2 2006.201.22:08:42.77#ibcon#end of sib2, iclass 24, count 2 2006.201.22:08:42.77#ibcon#*after write, iclass 24, count 2 2006.201.22:08:42.77#ibcon#*before return 0, iclass 24, count 2 2006.201.22:08:42.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:42.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:42.77#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.22:08:42.77#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:42.77#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:42.89#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:42.89#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:42.89#ibcon#enter wrdev, iclass 24, count 0 2006.201.22:08:42.89#ibcon#first serial, iclass 24, count 0 2006.201.22:08:42.89#ibcon#enter sib2, iclass 24, count 0 2006.201.22:08:42.89#ibcon#flushed, iclass 24, count 0 2006.201.22:08:42.89#ibcon#about to write, iclass 24, count 0 2006.201.22:08:42.89#ibcon#wrote, iclass 24, count 0 2006.201.22:08:42.89#ibcon#about to read 3, iclass 24, count 0 2006.201.22:08:42.91#ibcon#read 3, iclass 24, count 0 2006.201.22:08:42.91#ibcon#about to read 4, iclass 24, count 0 2006.201.22:08:42.91#ibcon#read 4, iclass 24, count 0 2006.201.22:08:42.91#ibcon#about to read 5, iclass 24, count 0 2006.201.22:08:42.91#ibcon#read 5, iclass 24, count 0 2006.201.22:08:42.91#ibcon#about to read 6, iclass 24, count 0 2006.201.22:08:42.91#ibcon#read 6, iclass 24, count 0 2006.201.22:08:42.91#ibcon#end of sib2, iclass 24, count 0 2006.201.22:08:42.91#ibcon#*mode == 0, iclass 24, count 0 2006.201.22:08:42.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.22:08:42.91#ibcon#[25=USB\r\n] 2006.201.22:08:42.91#ibcon#*before write, iclass 24, count 0 2006.201.22:08:42.91#ibcon#enter sib2, iclass 24, count 0 2006.201.22:08:42.91#ibcon#flushed, iclass 24, count 0 2006.201.22:08:42.91#ibcon#about to write, iclass 24, count 0 2006.201.22:08:42.91#ibcon#wrote, iclass 24, count 0 2006.201.22:08:42.91#ibcon#about to read 3, iclass 24, count 0 2006.201.22:08:42.94#ibcon#read 3, iclass 24, count 0 2006.201.22:08:42.94#ibcon#about to read 4, iclass 24, count 0 2006.201.22:08:42.94#ibcon#read 4, iclass 24, count 0 2006.201.22:08:42.94#ibcon#about to read 5, iclass 24, count 0 2006.201.22:08:42.94#ibcon#read 5, iclass 24, count 0 2006.201.22:08:42.94#ibcon#about to read 6, iclass 24, count 0 2006.201.22:08:42.94#ibcon#read 6, iclass 24, count 0 2006.201.22:08:42.94#ibcon#end of sib2, iclass 24, count 0 2006.201.22:08:42.94#ibcon#*after write, iclass 24, count 0 2006.201.22:08:42.94#ibcon#*before return 0, iclass 24, count 0 2006.201.22:08:42.94#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:42.94#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:42.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.22:08:42.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.22:08:42.94$vck44/valo=4,624.99 2006.201.22:08:42.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.22:08:42.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.22:08:42.94#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:42.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:42.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:42.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:42.94#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:08:42.94#ibcon#first serial, iclass 26, count 0 2006.201.22:08:42.94#ibcon#enter sib2, iclass 26, count 0 2006.201.22:08:42.94#ibcon#flushed, iclass 26, count 0 2006.201.22:08:42.94#ibcon#about to write, iclass 26, count 0 2006.201.22:08:42.94#ibcon#wrote, iclass 26, count 0 2006.201.22:08:42.94#ibcon#about to read 3, iclass 26, count 0 2006.201.22:08:42.96#ibcon#read 3, iclass 26, count 0 2006.201.22:08:42.96#ibcon#about to read 4, iclass 26, count 0 2006.201.22:08:42.96#ibcon#read 4, iclass 26, count 0 2006.201.22:08:42.96#ibcon#about to read 5, iclass 26, count 0 2006.201.22:08:42.96#ibcon#read 5, iclass 26, count 0 2006.201.22:08:42.96#ibcon#about to read 6, iclass 26, count 0 2006.201.22:08:42.96#ibcon#read 6, iclass 26, count 0 2006.201.22:08:42.96#ibcon#end of sib2, iclass 26, count 0 2006.201.22:08:42.96#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:08:42.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:08:42.96#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.22:08:42.96#ibcon#*before write, iclass 26, count 0 2006.201.22:08:42.96#ibcon#enter sib2, iclass 26, count 0 2006.201.22:08:42.96#ibcon#flushed, iclass 26, count 0 2006.201.22:08:42.96#ibcon#about to write, iclass 26, count 0 2006.201.22:08:42.96#ibcon#wrote, iclass 26, count 0 2006.201.22:08:42.96#ibcon#about to read 3, iclass 26, count 0 2006.201.22:08:43.00#ibcon#read 3, iclass 26, count 0 2006.201.22:08:43.00#ibcon#about to read 4, iclass 26, count 0 2006.201.22:08:43.00#ibcon#read 4, iclass 26, count 0 2006.201.22:08:43.00#ibcon#about to read 5, iclass 26, count 0 2006.201.22:08:43.00#ibcon#read 5, iclass 26, count 0 2006.201.22:08:43.00#ibcon#about to read 6, iclass 26, count 0 2006.201.22:08:43.00#ibcon#read 6, iclass 26, count 0 2006.201.22:08:43.00#ibcon#end of sib2, iclass 26, count 0 2006.201.22:08:43.00#ibcon#*after write, iclass 26, count 0 2006.201.22:08:43.00#ibcon#*before return 0, iclass 26, count 0 2006.201.22:08:43.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:43.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:43.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:08:43.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:08:43.00$vck44/va=4,7 2006.201.22:08:43.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.22:08:43.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.22:08:43.00#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:43.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:43.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:43.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:43.06#ibcon#enter wrdev, iclass 28, count 2 2006.201.22:08:43.06#ibcon#first serial, iclass 28, count 2 2006.201.22:08:43.06#ibcon#enter sib2, iclass 28, count 2 2006.201.22:08:43.06#ibcon#flushed, iclass 28, count 2 2006.201.22:08:43.06#ibcon#about to write, iclass 28, count 2 2006.201.22:08:43.06#ibcon#wrote, iclass 28, count 2 2006.201.22:08:43.06#ibcon#about to read 3, iclass 28, count 2 2006.201.22:08:43.08#ibcon#read 3, iclass 28, count 2 2006.201.22:08:43.08#ibcon#about to read 4, iclass 28, count 2 2006.201.22:08:43.08#ibcon#read 4, iclass 28, count 2 2006.201.22:08:43.08#ibcon#about to read 5, iclass 28, count 2 2006.201.22:08:43.08#ibcon#read 5, iclass 28, count 2 2006.201.22:08:43.08#ibcon#about to read 6, iclass 28, count 2 2006.201.22:08:43.08#ibcon#read 6, iclass 28, count 2 2006.201.22:08:43.08#ibcon#end of sib2, iclass 28, count 2 2006.201.22:08:43.08#ibcon#*mode == 0, iclass 28, count 2 2006.201.22:08:43.08#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.22:08:43.08#ibcon#[25=AT04-07\r\n] 2006.201.22:08:43.08#ibcon#*before write, iclass 28, count 2 2006.201.22:08:43.08#ibcon#enter sib2, iclass 28, count 2 2006.201.22:08:43.08#ibcon#flushed, iclass 28, count 2 2006.201.22:08:43.08#ibcon#about to write, iclass 28, count 2 2006.201.22:08:43.08#ibcon#wrote, iclass 28, count 2 2006.201.22:08:43.08#ibcon#about to read 3, iclass 28, count 2 2006.201.22:08:43.11#ibcon#read 3, iclass 28, count 2 2006.201.22:08:43.11#ibcon#about to read 4, iclass 28, count 2 2006.201.22:08:43.11#ibcon#read 4, iclass 28, count 2 2006.201.22:08:43.11#ibcon#about to read 5, iclass 28, count 2 2006.201.22:08:43.11#ibcon#read 5, iclass 28, count 2 2006.201.22:08:43.11#ibcon#about to read 6, iclass 28, count 2 2006.201.22:08:43.11#ibcon#read 6, iclass 28, count 2 2006.201.22:08:43.11#ibcon#end of sib2, iclass 28, count 2 2006.201.22:08:43.11#ibcon#*after write, iclass 28, count 2 2006.201.22:08:43.11#ibcon#*before return 0, iclass 28, count 2 2006.201.22:08:43.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:43.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:43.11#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.22:08:43.11#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:43.11#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:43.23#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:43.23#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:43.23#ibcon#enter wrdev, iclass 28, count 0 2006.201.22:08:43.23#ibcon#first serial, iclass 28, count 0 2006.201.22:08:43.23#ibcon#enter sib2, iclass 28, count 0 2006.201.22:08:43.23#ibcon#flushed, iclass 28, count 0 2006.201.22:08:43.23#ibcon#about to write, iclass 28, count 0 2006.201.22:08:43.23#ibcon#wrote, iclass 28, count 0 2006.201.22:08:43.23#ibcon#about to read 3, iclass 28, count 0 2006.201.22:08:43.25#ibcon#read 3, iclass 28, count 0 2006.201.22:08:43.25#ibcon#about to read 4, iclass 28, count 0 2006.201.22:08:43.25#ibcon#read 4, iclass 28, count 0 2006.201.22:08:43.25#ibcon#about to read 5, iclass 28, count 0 2006.201.22:08:43.25#ibcon#read 5, iclass 28, count 0 2006.201.22:08:43.25#ibcon#about to read 6, iclass 28, count 0 2006.201.22:08:43.25#ibcon#read 6, iclass 28, count 0 2006.201.22:08:43.25#ibcon#end of sib2, iclass 28, count 0 2006.201.22:08:43.25#ibcon#*mode == 0, iclass 28, count 0 2006.201.22:08:43.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.22:08:43.25#ibcon#[25=USB\r\n] 2006.201.22:08:43.25#ibcon#*before write, iclass 28, count 0 2006.201.22:08:43.25#ibcon#enter sib2, iclass 28, count 0 2006.201.22:08:43.25#ibcon#flushed, iclass 28, count 0 2006.201.22:08:43.25#ibcon#about to write, iclass 28, count 0 2006.201.22:08:43.25#ibcon#wrote, iclass 28, count 0 2006.201.22:08:43.25#ibcon#about to read 3, iclass 28, count 0 2006.201.22:08:43.28#ibcon#read 3, iclass 28, count 0 2006.201.22:08:43.28#ibcon#about to read 4, iclass 28, count 0 2006.201.22:08:43.28#ibcon#read 4, iclass 28, count 0 2006.201.22:08:43.28#ibcon#about to read 5, iclass 28, count 0 2006.201.22:08:43.28#ibcon#read 5, iclass 28, count 0 2006.201.22:08:43.28#ibcon#about to read 6, iclass 28, count 0 2006.201.22:08:43.28#ibcon#read 6, iclass 28, count 0 2006.201.22:08:43.28#ibcon#end of sib2, iclass 28, count 0 2006.201.22:08:43.28#ibcon#*after write, iclass 28, count 0 2006.201.22:08:43.28#ibcon#*before return 0, iclass 28, count 0 2006.201.22:08:43.28#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:43.28#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:43.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.22:08:43.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.22:08:43.28$vck44/valo=5,734.99 2006.201.22:08:43.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.22:08:43.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.22:08:43.28#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:43.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:43.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:43.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:43.28#ibcon#enter wrdev, iclass 30, count 0 2006.201.22:08:43.28#ibcon#first serial, iclass 30, count 0 2006.201.22:08:43.28#ibcon#enter sib2, iclass 30, count 0 2006.201.22:08:43.28#ibcon#flushed, iclass 30, count 0 2006.201.22:08:43.28#ibcon#about to write, iclass 30, count 0 2006.201.22:08:43.28#ibcon#wrote, iclass 30, count 0 2006.201.22:08:43.28#ibcon#about to read 3, iclass 30, count 0 2006.201.22:08:43.30#ibcon#read 3, iclass 30, count 0 2006.201.22:08:43.30#ibcon#about to read 4, iclass 30, count 0 2006.201.22:08:43.30#ibcon#read 4, iclass 30, count 0 2006.201.22:08:43.30#ibcon#about to read 5, iclass 30, count 0 2006.201.22:08:43.30#ibcon#read 5, iclass 30, count 0 2006.201.22:08:43.30#ibcon#about to read 6, iclass 30, count 0 2006.201.22:08:43.30#ibcon#read 6, iclass 30, count 0 2006.201.22:08:43.30#ibcon#end of sib2, iclass 30, count 0 2006.201.22:08:43.30#ibcon#*mode == 0, iclass 30, count 0 2006.201.22:08:43.30#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.22:08:43.30#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.22:08:43.30#ibcon#*before write, iclass 30, count 0 2006.201.22:08:43.30#ibcon#enter sib2, iclass 30, count 0 2006.201.22:08:43.30#ibcon#flushed, iclass 30, count 0 2006.201.22:08:43.30#ibcon#about to write, iclass 30, count 0 2006.201.22:08:43.30#ibcon#wrote, iclass 30, count 0 2006.201.22:08:43.30#ibcon#about to read 3, iclass 30, count 0 2006.201.22:08:43.34#ibcon#read 3, iclass 30, count 0 2006.201.22:08:43.34#ibcon#about to read 4, iclass 30, count 0 2006.201.22:08:43.34#ibcon#read 4, iclass 30, count 0 2006.201.22:08:43.34#ibcon#about to read 5, iclass 30, count 0 2006.201.22:08:43.34#ibcon#read 5, iclass 30, count 0 2006.201.22:08:43.34#ibcon#about to read 6, iclass 30, count 0 2006.201.22:08:43.34#ibcon#read 6, iclass 30, count 0 2006.201.22:08:43.34#ibcon#end of sib2, iclass 30, count 0 2006.201.22:08:43.34#ibcon#*after write, iclass 30, count 0 2006.201.22:08:43.34#ibcon#*before return 0, iclass 30, count 0 2006.201.22:08:43.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:43.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:43.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.22:08:43.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.22:08:43.34$vck44/va=5,4 2006.201.22:08:43.34#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.22:08:43.34#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.22:08:43.34#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:43.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:08:43.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:08:43.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:08:43.40#ibcon#enter wrdev, iclass 32, count 2 2006.201.22:08:43.40#ibcon#first serial, iclass 32, count 2 2006.201.22:08:43.40#ibcon#enter sib2, iclass 32, count 2 2006.201.22:08:43.40#ibcon#flushed, iclass 32, count 2 2006.201.22:08:43.40#ibcon#about to write, iclass 32, count 2 2006.201.22:08:43.40#ibcon#wrote, iclass 32, count 2 2006.201.22:08:43.40#ibcon#about to read 3, iclass 32, count 2 2006.201.22:08:43.42#ibcon#read 3, iclass 32, count 2 2006.201.22:08:43.42#ibcon#about to read 4, iclass 32, count 2 2006.201.22:08:43.42#ibcon#read 4, iclass 32, count 2 2006.201.22:08:43.42#ibcon#about to read 5, iclass 32, count 2 2006.201.22:08:43.42#ibcon#read 5, iclass 32, count 2 2006.201.22:08:43.42#ibcon#about to read 6, iclass 32, count 2 2006.201.22:08:43.42#ibcon#read 6, iclass 32, count 2 2006.201.22:08:43.42#ibcon#end of sib2, iclass 32, count 2 2006.201.22:08:43.42#ibcon#*mode == 0, iclass 32, count 2 2006.201.22:08:43.42#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.22:08:43.42#ibcon#[25=AT05-04\r\n] 2006.201.22:08:43.42#ibcon#*before write, iclass 32, count 2 2006.201.22:08:43.42#ibcon#enter sib2, iclass 32, count 2 2006.201.22:08:43.42#ibcon#flushed, iclass 32, count 2 2006.201.22:08:43.42#ibcon#about to write, iclass 32, count 2 2006.201.22:08:43.42#ibcon#wrote, iclass 32, count 2 2006.201.22:08:43.42#ibcon#about to read 3, iclass 32, count 2 2006.201.22:08:43.45#ibcon#read 3, iclass 32, count 2 2006.201.22:08:43.45#ibcon#about to read 4, iclass 32, count 2 2006.201.22:08:43.45#ibcon#read 4, iclass 32, count 2 2006.201.22:08:43.45#ibcon#about to read 5, iclass 32, count 2 2006.201.22:08:43.45#ibcon#read 5, iclass 32, count 2 2006.201.22:08:43.45#ibcon#about to read 6, iclass 32, count 2 2006.201.22:08:43.45#ibcon#read 6, iclass 32, count 2 2006.201.22:08:43.45#ibcon#end of sib2, iclass 32, count 2 2006.201.22:08:43.45#ibcon#*after write, iclass 32, count 2 2006.201.22:08:43.45#ibcon#*before return 0, iclass 32, count 2 2006.201.22:08:43.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:08:43.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:08:43.45#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.22:08:43.45#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:43.45#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:08:43.57#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:08:43.57#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:08:43.57#ibcon#enter wrdev, iclass 32, count 0 2006.201.22:08:43.57#ibcon#first serial, iclass 32, count 0 2006.201.22:08:43.57#ibcon#enter sib2, iclass 32, count 0 2006.201.22:08:43.57#ibcon#flushed, iclass 32, count 0 2006.201.22:08:43.57#ibcon#about to write, iclass 32, count 0 2006.201.22:08:43.57#ibcon#wrote, iclass 32, count 0 2006.201.22:08:43.57#ibcon#about to read 3, iclass 32, count 0 2006.201.22:08:43.59#ibcon#read 3, iclass 32, count 0 2006.201.22:08:43.59#ibcon#about to read 4, iclass 32, count 0 2006.201.22:08:43.59#ibcon#read 4, iclass 32, count 0 2006.201.22:08:43.59#ibcon#about to read 5, iclass 32, count 0 2006.201.22:08:43.59#ibcon#read 5, iclass 32, count 0 2006.201.22:08:43.59#ibcon#about to read 6, iclass 32, count 0 2006.201.22:08:43.59#ibcon#read 6, iclass 32, count 0 2006.201.22:08:43.59#ibcon#end of sib2, iclass 32, count 0 2006.201.22:08:43.59#ibcon#*mode == 0, iclass 32, count 0 2006.201.22:08:43.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.22:08:43.59#ibcon#[25=USB\r\n] 2006.201.22:08:43.59#ibcon#*before write, iclass 32, count 0 2006.201.22:08:43.59#ibcon#enter sib2, iclass 32, count 0 2006.201.22:08:43.59#ibcon#flushed, iclass 32, count 0 2006.201.22:08:43.59#ibcon#about to write, iclass 32, count 0 2006.201.22:08:43.59#ibcon#wrote, iclass 32, count 0 2006.201.22:08:43.59#ibcon#about to read 3, iclass 32, count 0 2006.201.22:08:43.62#ibcon#read 3, iclass 32, count 0 2006.201.22:08:43.62#ibcon#about to read 4, iclass 32, count 0 2006.201.22:08:43.62#ibcon#read 4, iclass 32, count 0 2006.201.22:08:43.62#ibcon#about to read 5, iclass 32, count 0 2006.201.22:08:43.62#ibcon#read 5, iclass 32, count 0 2006.201.22:08:43.62#ibcon#about to read 6, iclass 32, count 0 2006.201.22:08:43.62#ibcon#read 6, iclass 32, count 0 2006.201.22:08:43.62#ibcon#end of sib2, iclass 32, count 0 2006.201.22:08:43.62#ibcon#*after write, iclass 32, count 0 2006.201.22:08:43.62#ibcon#*before return 0, iclass 32, count 0 2006.201.22:08:43.62#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:08:43.62#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:08:43.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.22:08:43.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.22:08:43.62$vck44/valo=6,814.99 2006.201.22:08:43.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.22:08:43.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.22:08:43.62#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:43.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:08:43.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:08:43.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:08:43.62#ibcon#enter wrdev, iclass 34, count 0 2006.201.22:08:43.62#ibcon#first serial, iclass 34, count 0 2006.201.22:08:43.62#ibcon#enter sib2, iclass 34, count 0 2006.201.22:08:43.62#ibcon#flushed, iclass 34, count 0 2006.201.22:08:43.62#ibcon#about to write, iclass 34, count 0 2006.201.22:08:43.62#ibcon#wrote, iclass 34, count 0 2006.201.22:08:43.62#ibcon#about to read 3, iclass 34, count 0 2006.201.22:08:43.64#ibcon#read 3, iclass 34, count 0 2006.201.22:08:43.64#ibcon#about to read 4, iclass 34, count 0 2006.201.22:08:43.64#ibcon#read 4, iclass 34, count 0 2006.201.22:08:43.64#ibcon#about to read 5, iclass 34, count 0 2006.201.22:08:43.64#ibcon#read 5, iclass 34, count 0 2006.201.22:08:43.64#ibcon#about to read 6, iclass 34, count 0 2006.201.22:08:43.64#ibcon#read 6, iclass 34, count 0 2006.201.22:08:43.64#ibcon#end of sib2, iclass 34, count 0 2006.201.22:08:43.64#ibcon#*mode == 0, iclass 34, count 0 2006.201.22:08:43.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.22:08:43.64#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.22:08:43.64#ibcon#*before write, iclass 34, count 0 2006.201.22:08:43.64#ibcon#enter sib2, iclass 34, count 0 2006.201.22:08:43.64#ibcon#flushed, iclass 34, count 0 2006.201.22:08:43.64#ibcon#about to write, iclass 34, count 0 2006.201.22:08:43.64#ibcon#wrote, iclass 34, count 0 2006.201.22:08:43.64#ibcon#about to read 3, iclass 34, count 0 2006.201.22:08:43.69#ibcon#read 3, iclass 34, count 0 2006.201.22:08:43.69#ibcon#about to read 4, iclass 34, count 0 2006.201.22:08:43.69#ibcon#read 4, iclass 34, count 0 2006.201.22:08:43.69#ibcon#about to read 5, iclass 34, count 0 2006.201.22:08:43.69#ibcon#read 5, iclass 34, count 0 2006.201.22:08:43.69#ibcon#about to read 6, iclass 34, count 0 2006.201.22:08:43.69#ibcon#read 6, iclass 34, count 0 2006.201.22:08:43.69#ibcon#end of sib2, iclass 34, count 0 2006.201.22:08:43.69#ibcon#*after write, iclass 34, count 0 2006.201.22:08:43.69#ibcon#*before return 0, iclass 34, count 0 2006.201.22:08:43.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:08:43.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:08:43.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.22:08:43.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.22:08:43.69$vck44/va=6,5 2006.201.22:08:43.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.22:08:43.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.22:08:43.69#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:43.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:08:43.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:08:43.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:08:43.74#ibcon#enter wrdev, iclass 36, count 2 2006.201.22:08:43.74#ibcon#first serial, iclass 36, count 2 2006.201.22:08:43.74#ibcon#enter sib2, iclass 36, count 2 2006.201.22:08:43.74#ibcon#flushed, iclass 36, count 2 2006.201.22:08:43.74#ibcon#about to write, iclass 36, count 2 2006.201.22:08:43.74#ibcon#wrote, iclass 36, count 2 2006.201.22:08:43.74#ibcon#about to read 3, iclass 36, count 2 2006.201.22:08:43.76#ibcon#read 3, iclass 36, count 2 2006.201.22:08:43.76#ibcon#about to read 4, iclass 36, count 2 2006.201.22:08:43.76#ibcon#read 4, iclass 36, count 2 2006.201.22:08:43.76#ibcon#about to read 5, iclass 36, count 2 2006.201.22:08:43.76#ibcon#read 5, iclass 36, count 2 2006.201.22:08:43.76#ibcon#about to read 6, iclass 36, count 2 2006.201.22:08:43.76#ibcon#read 6, iclass 36, count 2 2006.201.22:08:43.76#ibcon#end of sib2, iclass 36, count 2 2006.201.22:08:43.76#ibcon#*mode == 0, iclass 36, count 2 2006.201.22:08:43.76#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.22:08:43.76#ibcon#[25=AT06-05\r\n] 2006.201.22:08:43.76#ibcon#*before write, iclass 36, count 2 2006.201.22:08:43.76#ibcon#enter sib2, iclass 36, count 2 2006.201.22:08:43.76#ibcon#flushed, iclass 36, count 2 2006.201.22:08:43.76#ibcon#about to write, iclass 36, count 2 2006.201.22:08:43.76#ibcon#wrote, iclass 36, count 2 2006.201.22:08:43.76#ibcon#about to read 3, iclass 36, count 2 2006.201.22:08:43.79#ibcon#read 3, iclass 36, count 2 2006.201.22:08:43.79#ibcon#about to read 4, iclass 36, count 2 2006.201.22:08:43.79#ibcon#read 4, iclass 36, count 2 2006.201.22:08:43.79#ibcon#about to read 5, iclass 36, count 2 2006.201.22:08:43.79#ibcon#read 5, iclass 36, count 2 2006.201.22:08:43.79#ibcon#about to read 6, iclass 36, count 2 2006.201.22:08:43.79#ibcon#read 6, iclass 36, count 2 2006.201.22:08:43.79#ibcon#end of sib2, iclass 36, count 2 2006.201.22:08:43.79#ibcon#*after write, iclass 36, count 2 2006.201.22:08:43.79#ibcon#*before return 0, iclass 36, count 2 2006.201.22:08:43.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:08:43.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:08:43.79#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.22:08:43.79#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:43.79#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:08:43.91#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:08:43.91#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:08:43.91#ibcon#enter wrdev, iclass 36, count 0 2006.201.22:08:43.91#ibcon#first serial, iclass 36, count 0 2006.201.22:08:43.91#ibcon#enter sib2, iclass 36, count 0 2006.201.22:08:43.91#ibcon#flushed, iclass 36, count 0 2006.201.22:08:43.91#ibcon#about to write, iclass 36, count 0 2006.201.22:08:43.91#ibcon#wrote, iclass 36, count 0 2006.201.22:08:43.91#ibcon#about to read 3, iclass 36, count 0 2006.201.22:08:43.93#ibcon#read 3, iclass 36, count 0 2006.201.22:08:43.93#ibcon#about to read 4, iclass 36, count 0 2006.201.22:08:43.93#ibcon#read 4, iclass 36, count 0 2006.201.22:08:43.93#ibcon#about to read 5, iclass 36, count 0 2006.201.22:08:43.93#ibcon#read 5, iclass 36, count 0 2006.201.22:08:43.93#ibcon#about to read 6, iclass 36, count 0 2006.201.22:08:43.93#ibcon#read 6, iclass 36, count 0 2006.201.22:08:43.93#ibcon#end of sib2, iclass 36, count 0 2006.201.22:08:43.93#ibcon#*mode == 0, iclass 36, count 0 2006.201.22:08:43.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.22:08:43.93#ibcon#[25=USB\r\n] 2006.201.22:08:43.93#ibcon#*before write, iclass 36, count 0 2006.201.22:08:43.93#ibcon#enter sib2, iclass 36, count 0 2006.201.22:08:43.93#ibcon#flushed, iclass 36, count 0 2006.201.22:08:43.93#ibcon#about to write, iclass 36, count 0 2006.201.22:08:43.93#ibcon#wrote, iclass 36, count 0 2006.201.22:08:43.93#ibcon#about to read 3, iclass 36, count 0 2006.201.22:08:43.96#ibcon#read 3, iclass 36, count 0 2006.201.22:08:43.96#ibcon#about to read 4, iclass 36, count 0 2006.201.22:08:43.96#ibcon#read 4, iclass 36, count 0 2006.201.22:08:43.96#ibcon#about to read 5, iclass 36, count 0 2006.201.22:08:43.96#ibcon#read 5, iclass 36, count 0 2006.201.22:08:43.96#ibcon#about to read 6, iclass 36, count 0 2006.201.22:08:43.96#ibcon#read 6, iclass 36, count 0 2006.201.22:08:43.96#ibcon#end of sib2, iclass 36, count 0 2006.201.22:08:43.96#ibcon#*after write, iclass 36, count 0 2006.201.22:08:43.96#ibcon#*before return 0, iclass 36, count 0 2006.201.22:08:43.96#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:08:43.96#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:08:43.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.22:08:43.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.22:08:43.96$vck44/valo=7,864.99 2006.201.22:08:43.96#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.22:08:43.96#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.22:08:43.96#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:43.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:43.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:43.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:43.96#ibcon#enter wrdev, iclass 38, count 0 2006.201.22:08:43.96#ibcon#first serial, iclass 38, count 0 2006.201.22:08:43.96#ibcon#enter sib2, iclass 38, count 0 2006.201.22:08:43.96#ibcon#flushed, iclass 38, count 0 2006.201.22:08:43.96#ibcon#about to write, iclass 38, count 0 2006.201.22:08:43.96#ibcon#wrote, iclass 38, count 0 2006.201.22:08:43.96#ibcon#about to read 3, iclass 38, count 0 2006.201.22:08:43.98#ibcon#read 3, iclass 38, count 0 2006.201.22:08:43.98#ibcon#about to read 4, iclass 38, count 0 2006.201.22:08:43.98#ibcon#read 4, iclass 38, count 0 2006.201.22:08:43.98#ibcon#about to read 5, iclass 38, count 0 2006.201.22:08:43.98#ibcon#read 5, iclass 38, count 0 2006.201.22:08:43.98#ibcon#about to read 6, iclass 38, count 0 2006.201.22:08:43.98#ibcon#read 6, iclass 38, count 0 2006.201.22:08:43.98#ibcon#end of sib2, iclass 38, count 0 2006.201.22:08:43.98#ibcon#*mode == 0, iclass 38, count 0 2006.201.22:08:43.98#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.22:08:43.98#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.22:08:43.98#ibcon#*before write, iclass 38, count 0 2006.201.22:08:43.98#ibcon#enter sib2, iclass 38, count 0 2006.201.22:08:43.98#ibcon#flushed, iclass 38, count 0 2006.201.22:08:43.98#ibcon#about to write, iclass 38, count 0 2006.201.22:08:43.98#ibcon#wrote, iclass 38, count 0 2006.201.22:08:43.98#ibcon#about to read 3, iclass 38, count 0 2006.201.22:08:44.02#ibcon#read 3, iclass 38, count 0 2006.201.22:08:44.02#ibcon#about to read 4, iclass 38, count 0 2006.201.22:08:44.02#ibcon#read 4, iclass 38, count 0 2006.201.22:08:44.02#ibcon#about to read 5, iclass 38, count 0 2006.201.22:08:44.02#ibcon#read 5, iclass 38, count 0 2006.201.22:08:44.02#ibcon#about to read 6, iclass 38, count 0 2006.201.22:08:44.02#ibcon#read 6, iclass 38, count 0 2006.201.22:08:44.02#ibcon#end of sib2, iclass 38, count 0 2006.201.22:08:44.02#ibcon#*after write, iclass 38, count 0 2006.201.22:08:44.02#ibcon#*before return 0, iclass 38, count 0 2006.201.22:08:44.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:44.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:44.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.22:08:44.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.22:08:44.02$vck44/va=7,5 2006.201.22:08:44.02#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.22:08:44.02#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.22:08:44.02#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:44.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:44.08#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:44.08#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:44.08#ibcon#enter wrdev, iclass 40, count 2 2006.201.22:08:44.08#ibcon#first serial, iclass 40, count 2 2006.201.22:08:44.08#ibcon#enter sib2, iclass 40, count 2 2006.201.22:08:44.08#ibcon#flushed, iclass 40, count 2 2006.201.22:08:44.08#ibcon#about to write, iclass 40, count 2 2006.201.22:08:44.08#ibcon#wrote, iclass 40, count 2 2006.201.22:08:44.08#ibcon#about to read 3, iclass 40, count 2 2006.201.22:08:44.10#ibcon#read 3, iclass 40, count 2 2006.201.22:08:44.10#ibcon#about to read 4, iclass 40, count 2 2006.201.22:08:44.10#ibcon#read 4, iclass 40, count 2 2006.201.22:08:44.10#ibcon#about to read 5, iclass 40, count 2 2006.201.22:08:44.10#ibcon#read 5, iclass 40, count 2 2006.201.22:08:44.10#ibcon#about to read 6, iclass 40, count 2 2006.201.22:08:44.10#ibcon#read 6, iclass 40, count 2 2006.201.22:08:44.10#ibcon#end of sib2, iclass 40, count 2 2006.201.22:08:44.10#ibcon#*mode == 0, iclass 40, count 2 2006.201.22:08:44.10#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.22:08:44.10#ibcon#[25=AT07-05\r\n] 2006.201.22:08:44.10#ibcon#*before write, iclass 40, count 2 2006.201.22:08:44.10#ibcon#enter sib2, iclass 40, count 2 2006.201.22:08:44.10#ibcon#flushed, iclass 40, count 2 2006.201.22:08:44.10#ibcon#about to write, iclass 40, count 2 2006.201.22:08:44.10#ibcon#wrote, iclass 40, count 2 2006.201.22:08:44.10#ibcon#about to read 3, iclass 40, count 2 2006.201.22:08:44.13#ibcon#read 3, iclass 40, count 2 2006.201.22:08:44.13#ibcon#about to read 4, iclass 40, count 2 2006.201.22:08:44.13#ibcon#read 4, iclass 40, count 2 2006.201.22:08:44.13#ibcon#about to read 5, iclass 40, count 2 2006.201.22:08:44.13#ibcon#read 5, iclass 40, count 2 2006.201.22:08:44.13#ibcon#about to read 6, iclass 40, count 2 2006.201.22:08:44.13#ibcon#read 6, iclass 40, count 2 2006.201.22:08:44.13#ibcon#end of sib2, iclass 40, count 2 2006.201.22:08:44.13#ibcon#*after write, iclass 40, count 2 2006.201.22:08:44.13#ibcon#*before return 0, iclass 40, count 2 2006.201.22:08:44.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:44.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:44.13#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.22:08:44.13#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:44.13#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:44.25#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:44.25#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:44.25#ibcon#enter wrdev, iclass 40, count 0 2006.201.22:08:44.25#ibcon#first serial, iclass 40, count 0 2006.201.22:08:44.25#ibcon#enter sib2, iclass 40, count 0 2006.201.22:08:44.25#ibcon#flushed, iclass 40, count 0 2006.201.22:08:44.25#ibcon#about to write, iclass 40, count 0 2006.201.22:08:44.25#ibcon#wrote, iclass 40, count 0 2006.201.22:08:44.25#ibcon#about to read 3, iclass 40, count 0 2006.201.22:08:44.27#ibcon#read 3, iclass 40, count 0 2006.201.22:08:44.27#ibcon#about to read 4, iclass 40, count 0 2006.201.22:08:44.27#ibcon#read 4, iclass 40, count 0 2006.201.22:08:44.27#ibcon#about to read 5, iclass 40, count 0 2006.201.22:08:44.27#ibcon#read 5, iclass 40, count 0 2006.201.22:08:44.27#ibcon#about to read 6, iclass 40, count 0 2006.201.22:08:44.27#ibcon#read 6, iclass 40, count 0 2006.201.22:08:44.27#ibcon#end of sib2, iclass 40, count 0 2006.201.22:08:44.27#ibcon#*mode == 0, iclass 40, count 0 2006.201.22:08:44.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.22:08:44.27#ibcon#[25=USB\r\n] 2006.201.22:08:44.27#ibcon#*before write, iclass 40, count 0 2006.201.22:08:44.27#ibcon#enter sib2, iclass 40, count 0 2006.201.22:08:44.27#ibcon#flushed, iclass 40, count 0 2006.201.22:08:44.27#ibcon#about to write, iclass 40, count 0 2006.201.22:08:44.27#ibcon#wrote, iclass 40, count 0 2006.201.22:08:44.27#ibcon#about to read 3, iclass 40, count 0 2006.201.22:08:44.30#ibcon#read 3, iclass 40, count 0 2006.201.22:08:44.30#ibcon#about to read 4, iclass 40, count 0 2006.201.22:08:44.30#ibcon#read 4, iclass 40, count 0 2006.201.22:08:44.30#ibcon#about to read 5, iclass 40, count 0 2006.201.22:08:44.30#ibcon#read 5, iclass 40, count 0 2006.201.22:08:44.30#ibcon#about to read 6, iclass 40, count 0 2006.201.22:08:44.30#ibcon#read 6, iclass 40, count 0 2006.201.22:08:44.30#ibcon#end of sib2, iclass 40, count 0 2006.201.22:08:44.30#ibcon#*after write, iclass 40, count 0 2006.201.22:08:44.30#ibcon#*before return 0, iclass 40, count 0 2006.201.22:08:44.30#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:44.30#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:44.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.22:08:44.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.22:08:44.30$vck44/valo=8,884.99 2006.201.22:08:44.30#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.22:08:44.30#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.22:08:44.30#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:44.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:44.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:44.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:44.30#ibcon#enter wrdev, iclass 4, count 0 2006.201.22:08:44.30#ibcon#first serial, iclass 4, count 0 2006.201.22:08:44.30#ibcon#enter sib2, iclass 4, count 0 2006.201.22:08:44.30#ibcon#flushed, iclass 4, count 0 2006.201.22:08:44.30#ibcon#about to write, iclass 4, count 0 2006.201.22:08:44.30#ibcon#wrote, iclass 4, count 0 2006.201.22:08:44.30#ibcon#about to read 3, iclass 4, count 0 2006.201.22:08:44.32#ibcon#read 3, iclass 4, count 0 2006.201.22:08:44.32#ibcon#about to read 4, iclass 4, count 0 2006.201.22:08:44.32#ibcon#read 4, iclass 4, count 0 2006.201.22:08:44.32#ibcon#about to read 5, iclass 4, count 0 2006.201.22:08:44.32#ibcon#read 5, iclass 4, count 0 2006.201.22:08:44.32#ibcon#about to read 6, iclass 4, count 0 2006.201.22:08:44.32#ibcon#read 6, iclass 4, count 0 2006.201.22:08:44.32#ibcon#end of sib2, iclass 4, count 0 2006.201.22:08:44.32#ibcon#*mode == 0, iclass 4, count 0 2006.201.22:08:44.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.22:08:44.32#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.22:08:44.32#ibcon#*before write, iclass 4, count 0 2006.201.22:08:44.32#ibcon#enter sib2, iclass 4, count 0 2006.201.22:08:44.32#ibcon#flushed, iclass 4, count 0 2006.201.22:08:44.32#ibcon#about to write, iclass 4, count 0 2006.201.22:08:44.32#ibcon#wrote, iclass 4, count 0 2006.201.22:08:44.32#ibcon#about to read 3, iclass 4, count 0 2006.201.22:08:44.37#ibcon#read 3, iclass 4, count 0 2006.201.22:08:44.37#ibcon#about to read 4, iclass 4, count 0 2006.201.22:08:44.37#ibcon#read 4, iclass 4, count 0 2006.201.22:08:44.37#ibcon#about to read 5, iclass 4, count 0 2006.201.22:08:44.37#ibcon#read 5, iclass 4, count 0 2006.201.22:08:44.37#ibcon#about to read 6, iclass 4, count 0 2006.201.22:08:44.37#ibcon#read 6, iclass 4, count 0 2006.201.22:08:44.37#ibcon#end of sib2, iclass 4, count 0 2006.201.22:08:44.37#ibcon#*after write, iclass 4, count 0 2006.201.22:08:44.37#ibcon#*before return 0, iclass 4, count 0 2006.201.22:08:44.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:44.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:44.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.22:08:44.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.22:08:44.37$vck44/va=8,4 2006.201.22:08:44.37#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.22:08:44.37#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.22:08:44.37#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:44.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:44.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:44.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:44.42#ibcon#enter wrdev, iclass 6, count 2 2006.201.22:08:44.42#ibcon#first serial, iclass 6, count 2 2006.201.22:08:44.42#ibcon#enter sib2, iclass 6, count 2 2006.201.22:08:44.42#ibcon#flushed, iclass 6, count 2 2006.201.22:08:44.42#ibcon#about to write, iclass 6, count 2 2006.201.22:08:44.42#ibcon#wrote, iclass 6, count 2 2006.201.22:08:44.42#ibcon#about to read 3, iclass 6, count 2 2006.201.22:08:44.44#ibcon#read 3, iclass 6, count 2 2006.201.22:08:44.44#ibcon#about to read 4, iclass 6, count 2 2006.201.22:08:44.44#ibcon#read 4, iclass 6, count 2 2006.201.22:08:44.44#ibcon#about to read 5, iclass 6, count 2 2006.201.22:08:44.44#ibcon#read 5, iclass 6, count 2 2006.201.22:08:44.44#ibcon#about to read 6, iclass 6, count 2 2006.201.22:08:44.44#ibcon#read 6, iclass 6, count 2 2006.201.22:08:44.44#ibcon#end of sib2, iclass 6, count 2 2006.201.22:08:44.44#ibcon#*mode == 0, iclass 6, count 2 2006.201.22:08:44.44#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.22:08:44.44#ibcon#[25=AT08-04\r\n] 2006.201.22:08:44.44#ibcon#*before write, iclass 6, count 2 2006.201.22:08:44.44#ibcon#enter sib2, iclass 6, count 2 2006.201.22:08:44.44#ibcon#flushed, iclass 6, count 2 2006.201.22:08:44.44#ibcon#about to write, iclass 6, count 2 2006.201.22:08:44.44#ibcon#wrote, iclass 6, count 2 2006.201.22:08:44.44#ibcon#about to read 3, iclass 6, count 2 2006.201.22:08:44.47#ibcon#read 3, iclass 6, count 2 2006.201.22:08:44.47#ibcon#about to read 4, iclass 6, count 2 2006.201.22:08:44.47#ibcon#read 4, iclass 6, count 2 2006.201.22:08:44.47#ibcon#about to read 5, iclass 6, count 2 2006.201.22:08:44.47#ibcon#read 5, iclass 6, count 2 2006.201.22:08:44.47#ibcon#about to read 6, iclass 6, count 2 2006.201.22:08:44.47#ibcon#read 6, iclass 6, count 2 2006.201.22:08:44.47#ibcon#end of sib2, iclass 6, count 2 2006.201.22:08:44.47#ibcon#*after write, iclass 6, count 2 2006.201.22:08:44.47#ibcon#*before return 0, iclass 6, count 2 2006.201.22:08:44.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:44.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:44.47#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.22:08:44.47#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:44.47#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:44.59#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:44.59#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:44.59#ibcon#enter wrdev, iclass 6, count 0 2006.201.22:08:44.59#ibcon#first serial, iclass 6, count 0 2006.201.22:08:44.59#ibcon#enter sib2, iclass 6, count 0 2006.201.22:08:44.59#ibcon#flushed, iclass 6, count 0 2006.201.22:08:44.59#ibcon#about to write, iclass 6, count 0 2006.201.22:08:44.59#ibcon#wrote, iclass 6, count 0 2006.201.22:08:44.59#ibcon#about to read 3, iclass 6, count 0 2006.201.22:08:44.61#ibcon#read 3, iclass 6, count 0 2006.201.22:08:44.61#ibcon#about to read 4, iclass 6, count 0 2006.201.22:08:44.61#ibcon#read 4, iclass 6, count 0 2006.201.22:08:44.61#ibcon#about to read 5, iclass 6, count 0 2006.201.22:08:44.61#ibcon#read 5, iclass 6, count 0 2006.201.22:08:44.61#ibcon#about to read 6, iclass 6, count 0 2006.201.22:08:44.61#ibcon#read 6, iclass 6, count 0 2006.201.22:08:44.61#ibcon#end of sib2, iclass 6, count 0 2006.201.22:08:44.61#ibcon#*mode == 0, iclass 6, count 0 2006.201.22:08:44.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.22:08:44.61#ibcon#[25=USB\r\n] 2006.201.22:08:44.61#ibcon#*before write, iclass 6, count 0 2006.201.22:08:44.61#ibcon#enter sib2, iclass 6, count 0 2006.201.22:08:44.61#ibcon#flushed, iclass 6, count 0 2006.201.22:08:44.61#ibcon#about to write, iclass 6, count 0 2006.201.22:08:44.61#ibcon#wrote, iclass 6, count 0 2006.201.22:08:44.61#ibcon#about to read 3, iclass 6, count 0 2006.201.22:08:44.64#ibcon#read 3, iclass 6, count 0 2006.201.22:08:44.64#ibcon#about to read 4, iclass 6, count 0 2006.201.22:08:44.64#ibcon#read 4, iclass 6, count 0 2006.201.22:08:44.64#ibcon#about to read 5, iclass 6, count 0 2006.201.22:08:44.64#ibcon#read 5, iclass 6, count 0 2006.201.22:08:44.64#ibcon#about to read 6, iclass 6, count 0 2006.201.22:08:44.64#ibcon#read 6, iclass 6, count 0 2006.201.22:08:44.64#ibcon#end of sib2, iclass 6, count 0 2006.201.22:08:44.64#ibcon#*after write, iclass 6, count 0 2006.201.22:08:44.64#ibcon#*before return 0, iclass 6, count 0 2006.201.22:08:44.64#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:44.64#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:44.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.22:08:44.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.22:08:44.64$vck44/vblo=1,629.99 2006.201.22:08:44.64#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.22:08:44.64#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.22:08:44.64#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:44.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:44.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:44.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:44.64#ibcon#enter wrdev, iclass 10, count 0 2006.201.22:08:44.64#ibcon#first serial, iclass 10, count 0 2006.201.22:08:44.64#ibcon#enter sib2, iclass 10, count 0 2006.201.22:08:44.64#ibcon#flushed, iclass 10, count 0 2006.201.22:08:44.64#ibcon#about to write, iclass 10, count 0 2006.201.22:08:44.64#ibcon#wrote, iclass 10, count 0 2006.201.22:08:44.64#ibcon#about to read 3, iclass 10, count 0 2006.201.22:08:44.66#ibcon#read 3, iclass 10, count 0 2006.201.22:08:44.66#ibcon#about to read 4, iclass 10, count 0 2006.201.22:08:44.66#ibcon#read 4, iclass 10, count 0 2006.201.22:08:44.66#ibcon#about to read 5, iclass 10, count 0 2006.201.22:08:44.66#ibcon#read 5, iclass 10, count 0 2006.201.22:08:44.66#ibcon#about to read 6, iclass 10, count 0 2006.201.22:08:44.66#ibcon#read 6, iclass 10, count 0 2006.201.22:08:44.66#ibcon#end of sib2, iclass 10, count 0 2006.201.22:08:44.66#ibcon#*mode == 0, iclass 10, count 0 2006.201.22:08:44.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.22:08:44.66#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.22:08:44.66#ibcon#*before write, iclass 10, count 0 2006.201.22:08:44.66#ibcon#enter sib2, iclass 10, count 0 2006.201.22:08:44.66#ibcon#flushed, iclass 10, count 0 2006.201.22:08:44.66#ibcon#about to write, iclass 10, count 0 2006.201.22:08:44.66#ibcon#wrote, iclass 10, count 0 2006.201.22:08:44.66#ibcon#about to read 3, iclass 10, count 0 2006.201.22:08:44.71#ibcon#read 3, iclass 10, count 0 2006.201.22:08:44.71#ibcon#about to read 4, iclass 10, count 0 2006.201.22:08:44.71#ibcon#read 4, iclass 10, count 0 2006.201.22:08:44.71#ibcon#about to read 5, iclass 10, count 0 2006.201.22:08:44.71#ibcon#read 5, iclass 10, count 0 2006.201.22:08:44.71#ibcon#about to read 6, iclass 10, count 0 2006.201.22:08:44.71#ibcon#read 6, iclass 10, count 0 2006.201.22:08:44.71#ibcon#end of sib2, iclass 10, count 0 2006.201.22:08:44.71#ibcon#*after write, iclass 10, count 0 2006.201.22:08:44.71#ibcon#*before return 0, iclass 10, count 0 2006.201.22:08:44.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:44.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:44.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.22:08:44.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.22:08:44.71$vck44/vb=1,4 2006.201.22:08:44.71#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.22:08:44.71#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.22:08:44.71#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:44.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:08:44.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:08:44.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:08:44.71#ibcon#enter wrdev, iclass 12, count 2 2006.201.22:08:44.71#ibcon#first serial, iclass 12, count 2 2006.201.22:08:44.71#ibcon#enter sib2, iclass 12, count 2 2006.201.22:08:44.71#ibcon#flushed, iclass 12, count 2 2006.201.22:08:44.71#ibcon#about to write, iclass 12, count 2 2006.201.22:08:44.71#ibcon#wrote, iclass 12, count 2 2006.201.22:08:44.71#ibcon#about to read 3, iclass 12, count 2 2006.201.22:08:44.73#ibcon#read 3, iclass 12, count 2 2006.201.22:08:44.73#ibcon#about to read 4, iclass 12, count 2 2006.201.22:08:44.73#ibcon#read 4, iclass 12, count 2 2006.201.22:08:44.73#ibcon#about to read 5, iclass 12, count 2 2006.201.22:08:44.73#ibcon#read 5, iclass 12, count 2 2006.201.22:08:44.73#ibcon#about to read 6, iclass 12, count 2 2006.201.22:08:44.73#ibcon#read 6, iclass 12, count 2 2006.201.22:08:44.73#ibcon#end of sib2, iclass 12, count 2 2006.201.22:08:44.73#ibcon#*mode == 0, iclass 12, count 2 2006.201.22:08:44.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.22:08:44.73#ibcon#[27=AT01-04\r\n] 2006.201.22:08:44.73#ibcon#*before write, iclass 12, count 2 2006.201.22:08:44.73#ibcon#enter sib2, iclass 12, count 2 2006.201.22:08:44.73#ibcon#flushed, iclass 12, count 2 2006.201.22:08:44.73#ibcon#about to write, iclass 12, count 2 2006.201.22:08:44.73#ibcon#wrote, iclass 12, count 2 2006.201.22:08:44.73#ibcon#about to read 3, iclass 12, count 2 2006.201.22:08:44.76#ibcon#read 3, iclass 12, count 2 2006.201.22:08:44.76#ibcon#about to read 4, iclass 12, count 2 2006.201.22:08:44.76#ibcon#read 4, iclass 12, count 2 2006.201.22:08:44.76#ibcon#about to read 5, iclass 12, count 2 2006.201.22:08:44.76#ibcon#read 5, iclass 12, count 2 2006.201.22:08:44.76#ibcon#about to read 6, iclass 12, count 2 2006.201.22:08:44.76#ibcon#read 6, iclass 12, count 2 2006.201.22:08:44.76#ibcon#end of sib2, iclass 12, count 2 2006.201.22:08:44.76#ibcon#*after write, iclass 12, count 2 2006.201.22:08:44.76#ibcon#*before return 0, iclass 12, count 2 2006.201.22:08:44.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:08:44.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:08:44.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.22:08:44.76#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:44.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:08:44.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:08:44.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:08:44.88#ibcon#enter wrdev, iclass 12, count 0 2006.201.22:08:44.88#ibcon#first serial, iclass 12, count 0 2006.201.22:08:44.88#ibcon#enter sib2, iclass 12, count 0 2006.201.22:08:44.88#ibcon#flushed, iclass 12, count 0 2006.201.22:08:44.88#ibcon#about to write, iclass 12, count 0 2006.201.22:08:44.88#ibcon#wrote, iclass 12, count 0 2006.201.22:08:44.88#ibcon#about to read 3, iclass 12, count 0 2006.201.22:08:44.90#ibcon#read 3, iclass 12, count 0 2006.201.22:08:44.90#ibcon#about to read 4, iclass 12, count 0 2006.201.22:08:44.90#ibcon#read 4, iclass 12, count 0 2006.201.22:08:44.90#ibcon#about to read 5, iclass 12, count 0 2006.201.22:08:44.90#ibcon#read 5, iclass 12, count 0 2006.201.22:08:44.90#ibcon#about to read 6, iclass 12, count 0 2006.201.22:08:44.90#ibcon#read 6, iclass 12, count 0 2006.201.22:08:44.90#ibcon#end of sib2, iclass 12, count 0 2006.201.22:08:44.90#ibcon#*mode == 0, iclass 12, count 0 2006.201.22:08:44.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.22:08:44.90#ibcon#[27=USB\r\n] 2006.201.22:08:44.90#ibcon#*before write, iclass 12, count 0 2006.201.22:08:44.90#ibcon#enter sib2, iclass 12, count 0 2006.201.22:08:44.90#ibcon#flushed, iclass 12, count 0 2006.201.22:08:44.90#ibcon#about to write, iclass 12, count 0 2006.201.22:08:44.90#ibcon#wrote, iclass 12, count 0 2006.201.22:08:44.90#ibcon#about to read 3, iclass 12, count 0 2006.201.22:08:44.93#ibcon#read 3, iclass 12, count 0 2006.201.22:08:44.93#ibcon#about to read 4, iclass 12, count 0 2006.201.22:08:44.93#ibcon#read 4, iclass 12, count 0 2006.201.22:08:44.93#ibcon#about to read 5, iclass 12, count 0 2006.201.22:08:44.93#ibcon#read 5, iclass 12, count 0 2006.201.22:08:44.93#ibcon#about to read 6, iclass 12, count 0 2006.201.22:08:44.93#ibcon#read 6, iclass 12, count 0 2006.201.22:08:44.93#ibcon#end of sib2, iclass 12, count 0 2006.201.22:08:44.93#ibcon#*after write, iclass 12, count 0 2006.201.22:08:44.93#ibcon#*before return 0, iclass 12, count 0 2006.201.22:08:44.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:08:44.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:08:44.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.22:08:44.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.22:08:44.93$vck44/vblo=2,634.99 2006.201.22:08:44.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.22:08:44.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.22:08:44.93#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:44.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:44.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:44.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:44.93#ibcon#enter wrdev, iclass 14, count 0 2006.201.22:08:44.93#ibcon#first serial, iclass 14, count 0 2006.201.22:08:44.93#ibcon#enter sib2, iclass 14, count 0 2006.201.22:08:44.93#ibcon#flushed, iclass 14, count 0 2006.201.22:08:44.93#ibcon#about to write, iclass 14, count 0 2006.201.22:08:44.93#ibcon#wrote, iclass 14, count 0 2006.201.22:08:44.93#ibcon#about to read 3, iclass 14, count 0 2006.201.22:08:44.95#ibcon#read 3, iclass 14, count 0 2006.201.22:08:44.95#ibcon#about to read 4, iclass 14, count 0 2006.201.22:08:44.95#ibcon#read 4, iclass 14, count 0 2006.201.22:08:44.95#ibcon#about to read 5, iclass 14, count 0 2006.201.22:08:44.95#ibcon#read 5, iclass 14, count 0 2006.201.22:08:44.95#ibcon#about to read 6, iclass 14, count 0 2006.201.22:08:44.95#ibcon#read 6, iclass 14, count 0 2006.201.22:08:44.95#ibcon#end of sib2, iclass 14, count 0 2006.201.22:08:44.95#ibcon#*mode == 0, iclass 14, count 0 2006.201.22:08:44.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.22:08:44.95#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.22:08:44.95#ibcon#*before write, iclass 14, count 0 2006.201.22:08:44.95#ibcon#enter sib2, iclass 14, count 0 2006.201.22:08:44.95#ibcon#flushed, iclass 14, count 0 2006.201.22:08:44.95#ibcon#about to write, iclass 14, count 0 2006.201.22:08:44.95#ibcon#wrote, iclass 14, count 0 2006.201.22:08:44.95#ibcon#about to read 3, iclass 14, count 0 2006.201.22:08:44.99#ibcon#read 3, iclass 14, count 0 2006.201.22:08:44.99#ibcon#about to read 4, iclass 14, count 0 2006.201.22:08:44.99#ibcon#read 4, iclass 14, count 0 2006.201.22:08:44.99#ibcon#about to read 5, iclass 14, count 0 2006.201.22:08:44.99#ibcon#read 5, iclass 14, count 0 2006.201.22:08:44.99#ibcon#about to read 6, iclass 14, count 0 2006.201.22:08:44.99#ibcon#read 6, iclass 14, count 0 2006.201.22:08:44.99#ibcon#end of sib2, iclass 14, count 0 2006.201.22:08:44.99#ibcon#*after write, iclass 14, count 0 2006.201.22:08:44.99#ibcon#*before return 0, iclass 14, count 0 2006.201.22:08:44.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:44.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:08:44.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.22:08:44.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.22:08:44.99$vck44/vb=2,5 2006.201.22:08:44.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.22:08:44.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.22:08:44.99#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:44.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:45.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:45.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:45.05#ibcon#enter wrdev, iclass 16, count 2 2006.201.22:08:45.05#ibcon#first serial, iclass 16, count 2 2006.201.22:08:45.05#ibcon#enter sib2, iclass 16, count 2 2006.201.22:08:45.05#ibcon#flushed, iclass 16, count 2 2006.201.22:08:45.05#ibcon#about to write, iclass 16, count 2 2006.201.22:08:45.05#ibcon#wrote, iclass 16, count 2 2006.201.22:08:45.05#ibcon#about to read 3, iclass 16, count 2 2006.201.22:08:45.07#ibcon#read 3, iclass 16, count 2 2006.201.22:08:45.07#ibcon#about to read 4, iclass 16, count 2 2006.201.22:08:45.07#ibcon#read 4, iclass 16, count 2 2006.201.22:08:45.07#ibcon#about to read 5, iclass 16, count 2 2006.201.22:08:45.07#ibcon#read 5, iclass 16, count 2 2006.201.22:08:45.07#ibcon#about to read 6, iclass 16, count 2 2006.201.22:08:45.07#ibcon#read 6, iclass 16, count 2 2006.201.22:08:45.07#ibcon#end of sib2, iclass 16, count 2 2006.201.22:08:45.07#ibcon#*mode == 0, iclass 16, count 2 2006.201.22:08:45.07#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.22:08:45.07#ibcon#[27=AT02-05\r\n] 2006.201.22:08:45.07#ibcon#*before write, iclass 16, count 2 2006.201.22:08:45.07#ibcon#enter sib2, iclass 16, count 2 2006.201.22:08:45.07#ibcon#flushed, iclass 16, count 2 2006.201.22:08:45.07#ibcon#about to write, iclass 16, count 2 2006.201.22:08:45.07#ibcon#wrote, iclass 16, count 2 2006.201.22:08:45.07#ibcon#about to read 3, iclass 16, count 2 2006.201.22:08:45.10#ibcon#read 3, iclass 16, count 2 2006.201.22:08:45.10#ibcon#about to read 4, iclass 16, count 2 2006.201.22:08:45.10#ibcon#read 4, iclass 16, count 2 2006.201.22:08:45.10#ibcon#about to read 5, iclass 16, count 2 2006.201.22:08:45.10#ibcon#read 5, iclass 16, count 2 2006.201.22:08:45.10#ibcon#about to read 6, iclass 16, count 2 2006.201.22:08:45.10#ibcon#read 6, iclass 16, count 2 2006.201.22:08:45.10#ibcon#end of sib2, iclass 16, count 2 2006.201.22:08:45.10#ibcon#*after write, iclass 16, count 2 2006.201.22:08:45.10#ibcon#*before return 0, iclass 16, count 2 2006.201.22:08:45.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:45.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:08:45.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.22:08:45.10#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:45.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:45.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:45.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:45.22#ibcon#enter wrdev, iclass 16, count 0 2006.201.22:08:45.22#ibcon#first serial, iclass 16, count 0 2006.201.22:08:45.22#ibcon#enter sib2, iclass 16, count 0 2006.201.22:08:45.22#ibcon#flushed, iclass 16, count 0 2006.201.22:08:45.22#ibcon#about to write, iclass 16, count 0 2006.201.22:08:45.22#ibcon#wrote, iclass 16, count 0 2006.201.22:08:45.22#ibcon#about to read 3, iclass 16, count 0 2006.201.22:08:45.24#ibcon#read 3, iclass 16, count 0 2006.201.22:08:45.24#ibcon#about to read 4, iclass 16, count 0 2006.201.22:08:45.24#ibcon#read 4, iclass 16, count 0 2006.201.22:08:45.24#ibcon#about to read 5, iclass 16, count 0 2006.201.22:08:45.24#ibcon#read 5, iclass 16, count 0 2006.201.22:08:45.24#ibcon#about to read 6, iclass 16, count 0 2006.201.22:08:45.24#ibcon#read 6, iclass 16, count 0 2006.201.22:08:45.24#ibcon#end of sib2, iclass 16, count 0 2006.201.22:08:45.24#ibcon#*mode == 0, iclass 16, count 0 2006.201.22:08:45.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.22:08:45.24#ibcon#[27=USB\r\n] 2006.201.22:08:45.24#ibcon#*before write, iclass 16, count 0 2006.201.22:08:45.24#ibcon#enter sib2, iclass 16, count 0 2006.201.22:08:45.24#ibcon#flushed, iclass 16, count 0 2006.201.22:08:45.24#ibcon#about to write, iclass 16, count 0 2006.201.22:08:45.24#ibcon#wrote, iclass 16, count 0 2006.201.22:08:45.24#ibcon#about to read 3, iclass 16, count 0 2006.201.22:08:45.27#ibcon#read 3, iclass 16, count 0 2006.201.22:08:45.27#ibcon#about to read 4, iclass 16, count 0 2006.201.22:08:45.27#ibcon#read 4, iclass 16, count 0 2006.201.22:08:45.27#ibcon#about to read 5, iclass 16, count 0 2006.201.22:08:45.27#ibcon#read 5, iclass 16, count 0 2006.201.22:08:45.27#ibcon#about to read 6, iclass 16, count 0 2006.201.22:08:45.27#ibcon#read 6, iclass 16, count 0 2006.201.22:08:45.27#ibcon#end of sib2, iclass 16, count 0 2006.201.22:08:45.27#ibcon#*after write, iclass 16, count 0 2006.201.22:08:45.27#ibcon#*before return 0, iclass 16, count 0 2006.201.22:08:45.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:45.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:08:45.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.22:08:45.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.22:08:45.27$vck44/vblo=3,649.99 2006.201.22:08:45.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.22:08:45.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.22:08:45.27#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:45.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:45.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:45.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:45.27#ibcon#enter wrdev, iclass 18, count 0 2006.201.22:08:45.27#ibcon#first serial, iclass 18, count 0 2006.201.22:08:45.27#ibcon#enter sib2, iclass 18, count 0 2006.201.22:08:45.27#ibcon#flushed, iclass 18, count 0 2006.201.22:08:45.27#ibcon#about to write, iclass 18, count 0 2006.201.22:08:45.27#ibcon#wrote, iclass 18, count 0 2006.201.22:08:45.27#ibcon#about to read 3, iclass 18, count 0 2006.201.22:08:45.29#ibcon#read 3, iclass 18, count 0 2006.201.22:08:45.29#ibcon#about to read 4, iclass 18, count 0 2006.201.22:08:45.29#ibcon#read 4, iclass 18, count 0 2006.201.22:08:45.29#ibcon#about to read 5, iclass 18, count 0 2006.201.22:08:45.29#ibcon#read 5, iclass 18, count 0 2006.201.22:08:45.29#ibcon#about to read 6, iclass 18, count 0 2006.201.22:08:45.29#ibcon#read 6, iclass 18, count 0 2006.201.22:08:45.29#ibcon#end of sib2, iclass 18, count 0 2006.201.22:08:45.29#ibcon#*mode == 0, iclass 18, count 0 2006.201.22:08:45.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.22:08:45.29#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.22:08:45.29#ibcon#*before write, iclass 18, count 0 2006.201.22:08:45.29#ibcon#enter sib2, iclass 18, count 0 2006.201.22:08:45.29#ibcon#flushed, iclass 18, count 0 2006.201.22:08:45.29#ibcon#about to write, iclass 18, count 0 2006.201.22:08:45.29#ibcon#wrote, iclass 18, count 0 2006.201.22:08:45.29#ibcon#about to read 3, iclass 18, count 0 2006.201.22:08:45.34#ibcon#read 3, iclass 18, count 0 2006.201.22:08:45.34#ibcon#about to read 4, iclass 18, count 0 2006.201.22:08:45.34#ibcon#read 4, iclass 18, count 0 2006.201.22:08:45.34#ibcon#about to read 5, iclass 18, count 0 2006.201.22:08:45.34#ibcon#read 5, iclass 18, count 0 2006.201.22:08:45.34#ibcon#about to read 6, iclass 18, count 0 2006.201.22:08:45.34#ibcon#read 6, iclass 18, count 0 2006.201.22:08:45.34#ibcon#end of sib2, iclass 18, count 0 2006.201.22:08:45.34#ibcon#*after write, iclass 18, count 0 2006.201.22:08:45.34#ibcon#*before return 0, iclass 18, count 0 2006.201.22:08:45.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:45.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:08:45.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.22:08:45.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.22:08:45.34$vck44/vb=3,4 2006.201.22:08:45.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.22:08:45.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.22:08:45.34#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:45.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:45.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:45.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:45.39#ibcon#enter wrdev, iclass 20, count 2 2006.201.22:08:45.39#ibcon#first serial, iclass 20, count 2 2006.201.22:08:45.39#ibcon#enter sib2, iclass 20, count 2 2006.201.22:08:45.39#ibcon#flushed, iclass 20, count 2 2006.201.22:08:45.39#ibcon#about to write, iclass 20, count 2 2006.201.22:08:45.39#ibcon#wrote, iclass 20, count 2 2006.201.22:08:45.39#ibcon#about to read 3, iclass 20, count 2 2006.201.22:08:45.41#ibcon#read 3, iclass 20, count 2 2006.201.22:08:45.41#ibcon#about to read 4, iclass 20, count 2 2006.201.22:08:45.41#ibcon#read 4, iclass 20, count 2 2006.201.22:08:45.41#ibcon#about to read 5, iclass 20, count 2 2006.201.22:08:45.41#ibcon#read 5, iclass 20, count 2 2006.201.22:08:45.41#ibcon#about to read 6, iclass 20, count 2 2006.201.22:08:45.41#ibcon#read 6, iclass 20, count 2 2006.201.22:08:45.41#ibcon#end of sib2, iclass 20, count 2 2006.201.22:08:45.41#ibcon#*mode == 0, iclass 20, count 2 2006.201.22:08:45.41#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.22:08:45.41#ibcon#[27=AT03-04\r\n] 2006.201.22:08:45.41#ibcon#*before write, iclass 20, count 2 2006.201.22:08:45.41#ibcon#enter sib2, iclass 20, count 2 2006.201.22:08:45.41#ibcon#flushed, iclass 20, count 2 2006.201.22:08:45.41#ibcon#about to write, iclass 20, count 2 2006.201.22:08:45.41#ibcon#wrote, iclass 20, count 2 2006.201.22:08:45.41#ibcon#about to read 3, iclass 20, count 2 2006.201.22:08:45.44#ibcon#read 3, iclass 20, count 2 2006.201.22:08:45.44#ibcon#about to read 4, iclass 20, count 2 2006.201.22:08:45.44#ibcon#read 4, iclass 20, count 2 2006.201.22:08:45.44#ibcon#about to read 5, iclass 20, count 2 2006.201.22:08:45.44#ibcon#read 5, iclass 20, count 2 2006.201.22:08:45.44#ibcon#about to read 6, iclass 20, count 2 2006.201.22:08:45.44#ibcon#read 6, iclass 20, count 2 2006.201.22:08:45.44#ibcon#end of sib2, iclass 20, count 2 2006.201.22:08:45.44#ibcon#*after write, iclass 20, count 2 2006.201.22:08:45.44#ibcon#*before return 0, iclass 20, count 2 2006.201.22:08:45.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:45.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:08:45.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.22:08:45.44#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:45.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:45.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:45.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:45.56#ibcon#enter wrdev, iclass 20, count 0 2006.201.22:08:45.56#ibcon#first serial, iclass 20, count 0 2006.201.22:08:45.56#ibcon#enter sib2, iclass 20, count 0 2006.201.22:08:45.56#ibcon#flushed, iclass 20, count 0 2006.201.22:08:45.56#ibcon#about to write, iclass 20, count 0 2006.201.22:08:45.56#ibcon#wrote, iclass 20, count 0 2006.201.22:08:45.56#ibcon#about to read 3, iclass 20, count 0 2006.201.22:08:45.58#ibcon#read 3, iclass 20, count 0 2006.201.22:08:45.58#ibcon#about to read 4, iclass 20, count 0 2006.201.22:08:45.58#ibcon#read 4, iclass 20, count 0 2006.201.22:08:45.58#ibcon#about to read 5, iclass 20, count 0 2006.201.22:08:45.58#ibcon#read 5, iclass 20, count 0 2006.201.22:08:45.58#ibcon#about to read 6, iclass 20, count 0 2006.201.22:08:45.58#ibcon#read 6, iclass 20, count 0 2006.201.22:08:45.58#ibcon#end of sib2, iclass 20, count 0 2006.201.22:08:45.58#ibcon#*mode == 0, iclass 20, count 0 2006.201.22:08:45.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.22:08:45.58#ibcon#[27=USB\r\n] 2006.201.22:08:45.58#ibcon#*before write, iclass 20, count 0 2006.201.22:08:45.58#ibcon#enter sib2, iclass 20, count 0 2006.201.22:08:45.58#ibcon#flushed, iclass 20, count 0 2006.201.22:08:45.58#ibcon#about to write, iclass 20, count 0 2006.201.22:08:45.58#ibcon#wrote, iclass 20, count 0 2006.201.22:08:45.58#ibcon#about to read 3, iclass 20, count 0 2006.201.22:08:45.61#ibcon#read 3, iclass 20, count 0 2006.201.22:08:45.61#ibcon#about to read 4, iclass 20, count 0 2006.201.22:08:45.61#ibcon#read 4, iclass 20, count 0 2006.201.22:08:45.61#ibcon#about to read 5, iclass 20, count 0 2006.201.22:08:45.61#ibcon#read 5, iclass 20, count 0 2006.201.22:08:45.61#ibcon#about to read 6, iclass 20, count 0 2006.201.22:08:45.61#ibcon#read 6, iclass 20, count 0 2006.201.22:08:45.61#ibcon#end of sib2, iclass 20, count 0 2006.201.22:08:45.61#ibcon#*after write, iclass 20, count 0 2006.201.22:08:45.61#ibcon#*before return 0, iclass 20, count 0 2006.201.22:08:45.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:45.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:08:45.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.22:08:45.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.22:08:45.61$vck44/vblo=4,679.99 2006.201.22:08:45.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.22:08:45.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.22:08:45.61#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:45.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:45.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:45.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:45.61#ibcon#enter wrdev, iclass 22, count 0 2006.201.22:08:45.61#ibcon#first serial, iclass 22, count 0 2006.201.22:08:45.61#ibcon#enter sib2, iclass 22, count 0 2006.201.22:08:45.61#ibcon#flushed, iclass 22, count 0 2006.201.22:08:45.61#ibcon#about to write, iclass 22, count 0 2006.201.22:08:45.61#ibcon#wrote, iclass 22, count 0 2006.201.22:08:45.61#ibcon#about to read 3, iclass 22, count 0 2006.201.22:08:45.63#ibcon#read 3, iclass 22, count 0 2006.201.22:08:45.63#ibcon#about to read 4, iclass 22, count 0 2006.201.22:08:45.63#ibcon#read 4, iclass 22, count 0 2006.201.22:08:45.63#ibcon#about to read 5, iclass 22, count 0 2006.201.22:08:45.63#ibcon#read 5, iclass 22, count 0 2006.201.22:08:45.63#ibcon#about to read 6, iclass 22, count 0 2006.201.22:08:45.63#ibcon#read 6, iclass 22, count 0 2006.201.22:08:45.63#ibcon#end of sib2, iclass 22, count 0 2006.201.22:08:45.63#ibcon#*mode == 0, iclass 22, count 0 2006.201.22:08:45.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.22:08:45.63#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.22:08:45.63#ibcon#*before write, iclass 22, count 0 2006.201.22:08:45.63#ibcon#enter sib2, iclass 22, count 0 2006.201.22:08:45.63#ibcon#flushed, iclass 22, count 0 2006.201.22:08:45.63#ibcon#about to write, iclass 22, count 0 2006.201.22:08:45.63#ibcon#wrote, iclass 22, count 0 2006.201.22:08:45.63#ibcon#about to read 3, iclass 22, count 0 2006.201.22:08:45.67#ibcon#read 3, iclass 22, count 0 2006.201.22:08:45.67#ibcon#about to read 4, iclass 22, count 0 2006.201.22:08:45.67#ibcon#read 4, iclass 22, count 0 2006.201.22:08:45.67#ibcon#about to read 5, iclass 22, count 0 2006.201.22:08:45.67#ibcon#read 5, iclass 22, count 0 2006.201.22:08:45.67#ibcon#about to read 6, iclass 22, count 0 2006.201.22:08:45.67#ibcon#read 6, iclass 22, count 0 2006.201.22:08:45.67#ibcon#end of sib2, iclass 22, count 0 2006.201.22:08:45.67#ibcon#*after write, iclass 22, count 0 2006.201.22:08:45.67#ibcon#*before return 0, iclass 22, count 0 2006.201.22:08:45.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:45.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:08:45.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.22:08:45.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.22:08:45.67$vck44/vb=4,5 2006.201.22:08:45.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.22:08:45.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.22:08:45.67#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:45.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:45.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:45.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:45.73#ibcon#enter wrdev, iclass 24, count 2 2006.201.22:08:45.73#ibcon#first serial, iclass 24, count 2 2006.201.22:08:45.73#ibcon#enter sib2, iclass 24, count 2 2006.201.22:08:45.73#ibcon#flushed, iclass 24, count 2 2006.201.22:08:45.73#ibcon#about to write, iclass 24, count 2 2006.201.22:08:45.73#ibcon#wrote, iclass 24, count 2 2006.201.22:08:45.73#ibcon#about to read 3, iclass 24, count 2 2006.201.22:08:45.75#ibcon#read 3, iclass 24, count 2 2006.201.22:08:45.75#ibcon#about to read 4, iclass 24, count 2 2006.201.22:08:45.75#ibcon#read 4, iclass 24, count 2 2006.201.22:08:45.75#ibcon#about to read 5, iclass 24, count 2 2006.201.22:08:45.75#ibcon#read 5, iclass 24, count 2 2006.201.22:08:45.75#ibcon#about to read 6, iclass 24, count 2 2006.201.22:08:45.75#ibcon#read 6, iclass 24, count 2 2006.201.22:08:45.75#ibcon#end of sib2, iclass 24, count 2 2006.201.22:08:45.75#ibcon#*mode == 0, iclass 24, count 2 2006.201.22:08:45.75#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.22:08:45.75#ibcon#[27=AT04-05\r\n] 2006.201.22:08:45.75#ibcon#*before write, iclass 24, count 2 2006.201.22:08:45.75#ibcon#enter sib2, iclass 24, count 2 2006.201.22:08:45.75#ibcon#flushed, iclass 24, count 2 2006.201.22:08:45.75#ibcon#about to write, iclass 24, count 2 2006.201.22:08:45.75#ibcon#wrote, iclass 24, count 2 2006.201.22:08:45.75#ibcon#about to read 3, iclass 24, count 2 2006.201.22:08:45.78#ibcon#read 3, iclass 24, count 2 2006.201.22:08:45.78#ibcon#about to read 4, iclass 24, count 2 2006.201.22:08:45.78#ibcon#read 4, iclass 24, count 2 2006.201.22:08:45.78#ibcon#about to read 5, iclass 24, count 2 2006.201.22:08:45.78#ibcon#read 5, iclass 24, count 2 2006.201.22:08:45.78#ibcon#about to read 6, iclass 24, count 2 2006.201.22:08:45.78#ibcon#read 6, iclass 24, count 2 2006.201.22:08:45.78#ibcon#end of sib2, iclass 24, count 2 2006.201.22:08:45.78#ibcon#*after write, iclass 24, count 2 2006.201.22:08:45.78#ibcon#*before return 0, iclass 24, count 2 2006.201.22:08:45.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:45.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:08:45.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.22:08:45.78#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:45.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:45.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:45.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:45.90#ibcon#enter wrdev, iclass 24, count 0 2006.201.22:08:45.90#ibcon#first serial, iclass 24, count 0 2006.201.22:08:45.90#ibcon#enter sib2, iclass 24, count 0 2006.201.22:08:45.90#ibcon#flushed, iclass 24, count 0 2006.201.22:08:45.90#ibcon#about to write, iclass 24, count 0 2006.201.22:08:45.90#ibcon#wrote, iclass 24, count 0 2006.201.22:08:45.90#ibcon#about to read 3, iclass 24, count 0 2006.201.22:08:45.92#ibcon#read 3, iclass 24, count 0 2006.201.22:08:45.92#ibcon#about to read 4, iclass 24, count 0 2006.201.22:08:45.92#ibcon#read 4, iclass 24, count 0 2006.201.22:08:45.92#ibcon#about to read 5, iclass 24, count 0 2006.201.22:08:45.92#ibcon#read 5, iclass 24, count 0 2006.201.22:08:45.92#ibcon#about to read 6, iclass 24, count 0 2006.201.22:08:45.92#ibcon#read 6, iclass 24, count 0 2006.201.22:08:45.92#ibcon#end of sib2, iclass 24, count 0 2006.201.22:08:45.92#ibcon#*mode == 0, iclass 24, count 0 2006.201.22:08:45.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.22:08:45.92#ibcon#[27=USB\r\n] 2006.201.22:08:45.92#ibcon#*before write, iclass 24, count 0 2006.201.22:08:45.92#ibcon#enter sib2, iclass 24, count 0 2006.201.22:08:45.92#ibcon#flushed, iclass 24, count 0 2006.201.22:08:45.92#ibcon#about to write, iclass 24, count 0 2006.201.22:08:45.92#ibcon#wrote, iclass 24, count 0 2006.201.22:08:45.92#ibcon#about to read 3, iclass 24, count 0 2006.201.22:08:45.95#ibcon#read 3, iclass 24, count 0 2006.201.22:08:45.95#ibcon#about to read 4, iclass 24, count 0 2006.201.22:08:45.95#ibcon#read 4, iclass 24, count 0 2006.201.22:08:45.95#ibcon#about to read 5, iclass 24, count 0 2006.201.22:08:45.95#ibcon#read 5, iclass 24, count 0 2006.201.22:08:45.95#ibcon#about to read 6, iclass 24, count 0 2006.201.22:08:45.95#ibcon#read 6, iclass 24, count 0 2006.201.22:08:45.95#ibcon#end of sib2, iclass 24, count 0 2006.201.22:08:45.95#ibcon#*after write, iclass 24, count 0 2006.201.22:08:45.95#ibcon#*before return 0, iclass 24, count 0 2006.201.22:08:45.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:45.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:08:45.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.22:08:45.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.22:08:45.95$vck44/vblo=5,709.99 2006.201.22:08:45.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.22:08:45.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.22:08:45.95#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:45.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:45.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:45.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:45.95#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:08:45.95#ibcon#first serial, iclass 26, count 0 2006.201.22:08:45.95#ibcon#enter sib2, iclass 26, count 0 2006.201.22:08:45.95#ibcon#flushed, iclass 26, count 0 2006.201.22:08:45.95#ibcon#about to write, iclass 26, count 0 2006.201.22:08:45.95#ibcon#wrote, iclass 26, count 0 2006.201.22:08:45.95#ibcon#about to read 3, iclass 26, count 0 2006.201.22:08:45.97#ibcon#read 3, iclass 26, count 0 2006.201.22:08:45.97#ibcon#about to read 4, iclass 26, count 0 2006.201.22:08:45.97#ibcon#read 4, iclass 26, count 0 2006.201.22:08:45.97#ibcon#about to read 5, iclass 26, count 0 2006.201.22:08:45.97#ibcon#read 5, iclass 26, count 0 2006.201.22:08:45.97#ibcon#about to read 6, iclass 26, count 0 2006.201.22:08:45.97#ibcon#read 6, iclass 26, count 0 2006.201.22:08:45.97#ibcon#end of sib2, iclass 26, count 0 2006.201.22:08:45.97#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:08:45.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:08:45.97#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.22:08:45.97#ibcon#*before write, iclass 26, count 0 2006.201.22:08:45.97#ibcon#enter sib2, iclass 26, count 0 2006.201.22:08:45.97#ibcon#flushed, iclass 26, count 0 2006.201.22:08:45.97#ibcon#about to write, iclass 26, count 0 2006.201.22:08:45.97#ibcon#wrote, iclass 26, count 0 2006.201.22:08:45.97#ibcon#about to read 3, iclass 26, count 0 2006.201.22:08:46.01#ibcon#read 3, iclass 26, count 0 2006.201.22:08:46.01#ibcon#about to read 4, iclass 26, count 0 2006.201.22:08:46.01#ibcon#read 4, iclass 26, count 0 2006.201.22:08:46.01#ibcon#about to read 5, iclass 26, count 0 2006.201.22:08:46.01#ibcon#read 5, iclass 26, count 0 2006.201.22:08:46.01#ibcon#about to read 6, iclass 26, count 0 2006.201.22:08:46.01#ibcon#read 6, iclass 26, count 0 2006.201.22:08:46.01#ibcon#end of sib2, iclass 26, count 0 2006.201.22:08:46.01#ibcon#*after write, iclass 26, count 0 2006.201.22:08:46.01#ibcon#*before return 0, iclass 26, count 0 2006.201.22:08:46.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:46.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:08:46.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:08:46.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:08:46.01$vck44/vb=5,4 2006.201.22:08:46.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.22:08:46.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.22:08:46.01#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:46.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:46.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:46.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:46.07#ibcon#enter wrdev, iclass 28, count 2 2006.201.22:08:46.07#ibcon#first serial, iclass 28, count 2 2006.201.22:08:46.07#ibcon#enter sib2, iclass 28, count 2 2006.201.22:08:46.07#ibcon#flushed, iclass 28, count 2 2006.201.22:08:46.07#ibcon#about to write, iclass 28, count 2 2006.201.22:08:46.07#ibcon#wrote, iclass 28, count 2 2006.201.22:08:46.07#ibcon#about to read 3, iclass 28, count 2 2006.201.22:08:46.09#ibcon#read 3, iclass 28, count 2 2006.201.22:08:46.09#ibcon#about to read 4, iclass 28, count 2 2006.201.22:08:46.09#ibcon#read 4, iclass 28, count 2 2006.201.22:08:46.09#ibcon#about to read 5, iclass 28, count 2 2006.201.22:08:46.09#ibcon#read 5, iclass 28, count 2 2006.201.22:08:46.09#ibcon#about to read 6, iclass 28, count 2 2006.201.22:08:46.09#ibcon#read 6, iclass 28, count 2 2006.201.22:08:46.09#ibcon#end of sib2, iclass 28, count 2 2006.201.22:08:46.09#ibcon#*mode == 0, iclass 28, count 2 2006.201.22:08:46.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.22:08:46.09#ibcon#[27=AT05-04\r\n] 2006.201.22:08:46.09#ibcon#*before write, iclass 28, count 2 2006.201.22:08:46.09#ibcon#enter sib2, iclass 28, count 2 2006.201.22:08:46.09#ibcon#flushed, iclass 28, count 2 2006.201.22:08:46.09#ibcon#about to write, iclass 28, count 2 2006.201.22:08:46.09#ibcon#wrote, iclass 28, count 2 2006.201.22:08:46.09#ibcon#about to read 3, iclass 28, count 2 2006.201.22:08:46.12#ibcon#read 3, iclass 28, count 2 2006.201.22:08:46.12#ibcon#about to read 4, iclass 28, count 2 2006.201.22:08:46.12#ibcon#read 4, iclass 28, count 2 2006.201.22:08:46.12#ibcon#about to read 5, iclass 28, count 2 2006.201.22:08:46.12#ibcon#read 5, iclass 28, count 2 2006.201.22:08:46.12#ibcon#about to read 6, iclass 28, count 2 2006.201.22:08:46.12#ibcon#read 6, iclass 28, count 2 2006.201.22:08:46.12#ibcon#end of sib2, iclass 28, count 2 2006.201.22:08:46.12#ibcon#*after write, iclass 28, count 2 2006.201.22:08:46.12#ibcon#*before return 0, iclass 28, count 2 2006.201.22:08:46.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:46.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:08:46.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.22:08:46.12#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:46.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:46.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:46.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:46.24#ibcon#enter wrdev, iclass 28, count 0 2006.201.22:08:46.24#ibcon#first serial, iclass 28, count 0 2006.201.22:08:46.24#ibcon#enter sib2, iclass 28, count 0 2006.201.22:08:46.24#ibcon#flushed, iclass 28, count 0 2006.201.22:08:46.24#ibcon#about to write, iclass 28, count 0 2006.201.22:08:46.24#ibcon#wrote, iclass 28, count 0 2006.201.22:08:46.24#ibcon#about to read 3, iclass 28, count 0 2006.201.22:08:46.26#ibcon#read 3, iclass 28, count 0 2006.201.22:08:46.26#ibcon#about to read 4, iclass 28, count 0 2006.201.22:08:46.26#ibcon#read 4, iclass 28, count 0 2006.201.22:08:46.26#ibcon#about to read 5, iclass 28, count 0 2006.201.22:08:46.26#ibcon#read 5, iclass 28, count 0 2006.201.22:08:46.26#ibcon#about to read 6, iclass 28, count 0 2006.201.22:08:46.26#ibcon#read 6, iclass 28, count 0 2006.201.22:08:46.26#ibcon#end of sib2, iclass 28, count 0 2006.201.22:08:46.26#ibcon#*mode == 0, iclass 28, count 0 2006.201.22:08:46.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.22:08:46.26#ibcon#[27=USB\r\n] 2006.201.22:08:46.26#ibcon#*before write, iclass 28, count 0 2006.201.22:08:46.26#ibcon#enter sib2, iclass 28, count 0 2006.201.22:08:46.26#ibcon#flushed, iclass 28, count 0 2006.201.22:08:46.26#ibcon#about to write, iclass 28, count 0 2006.201.22:08:46.26#ibcon#wrote, iclass 28, count 0 2006.201.22:08:46.26#ibcon#about to read 3, iclass 28, count 0 2006.201.22:08:46.29#ibcon#read 3, iclass 28, count 0 2006.201.22:08:46.29#ibcon#about to read 4, iclass 28, count 0 2006.201.22:08:46.29#ibcon#read 4, iclass 28, count 0 2006.201.22:08:46.29#ibcon#about to read 5, iclass 28, count 0 2006.201.22:08:46.29#ibcon#read 5, iclass 28, count 0 2006.201.22:08:46.29#ibcon#about to read 6, iclass 28, count 0 2006.201.22:08:46.29#ibcon#read 6, iclass 28, count 0 2006.201.22:08:46.29#ibcon#end of sib2, iclass 28, count 0 2006.201.22:08:46.29#ibcon#*after write, iclass 28, count 0 2006.201.22:08:46.29#ibcon#*before return 0, iclass 28, count 0 2006.201.22:08:46.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:46.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:08:46.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.22:08:46.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.22:08:46.29$vck44/vblo=6,719.99 2006.201.22:08:46.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.22:08:46.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.22:08:46.29#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:46.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:46.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:46.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:46.29#ibcon#enter wrdev, iclass 30, count 0 2006.201.22:08:46.29#ibcon#first serial, iclass 30, count 0 2006.201.22:08:46.29#ibcon#enter sib2, iclass 30, count 0 2006.201.22:08:46.29#ibcon#flushed, iclass 30, count 0 2006.201.22:08:46.29#ibcon#about to write, iclass 30, count 0 2006.201.22:08:46.29#ibcon#wrote, iclass 30, count 0 2006.201.22:08:46.29#ibcon#about to read 3, iclass 30, count 0 2006.201.22:08:46.31#ibcon#read 3, iclass 30, count 0 2006.201.22:08:46.31#ibcon#about to read 4, iclass 30, count 0 2006.201.22:08:46.31#ibcon#read 4, iclass 30, count 0 2006.201.22:08:46.31#ibcon#about to read 5, iclass 30, count 0 2006.201.22:08:46.31#ibcon#read 5, iclass 30, count 0 2006.201.22:08:46.31#ibcon#about to read 6, iclass 30, count 0 2006.201.22:08:46.31#ibcon#read 6, iclass 30, count 0 2006.201.22:08:46.31#ibcon#end of sib2, iclass 30, count 0 2006.201.22:08:46.31#ibcon#*mode == 0, iclass 30, count 0 2006.201.22:08:46.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.22:08:46.31#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.22:08:46.31#ibcon#*before write, iclass 30, count 0 2006.201.22:08:46.31#ibcon#enter sib2, iclass 30, count 0 2006.201.22:08:46.31#ibcon#flushed, iclass 30, count 0 2006.201.22:08:46.31#ibcon#about to write, iclass 30, count 0 2006.201.22:08:46.31#ibcon#wrote, iclass 30, count 0 2006.201.22:08:46.31#ibcon#about to read 3, iclass 30, count 0 2006.201.22:08:46.35#abcon#<5=/05 2.3 3.6 19.981001001.6\r\n> 2006.201.22:08:46.36#ibcon#read 3, iclass 30, count 0 2006.201.22:08:46.36#ibcon#about to read 4, iclass 30, count 0 2006.201.22:08:46.36#ibcon#read 4, iclass 30, count 0 2006.201.22:08:46.36#ibcon#about to read 5, iclass 30, count 0 2006.201.22:08:46.36#ibcon#read 5, iclass 30, count 0 2006.201.22:08:46.36#ibcon#about to read 6, iclass 30, count 0 2006.201.22:08:46.36#ibcon#read 6, iclass 30, count 0 2006.201.22:08:46.36#ibcon#end of sib2, iclass 30, count 0 2006.201.22:08:46.36#ibcon#*after write, iclass 30, count 0 2006.201.22:08:46.36#ibcon#*before return 0, iclass 30, count 0 2006.201.22:08:46.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:46.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:08:46.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.22:08:46.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.22:08:46.36$vck44/vb=6,4 2006.201.22:08:46.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.22:08:46.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.22:08:46.36#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:46.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:08:46.37#abcon#{5=INTERFACE CLEAR} 2006.201.22:08:46.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:08:46.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:08:46.41#ibcon#enter wrdev, iclass 35, count 2 2006.201.22:08:46.41#ibcon#first serial, iclass 35, count 2 2006.201.22:08:46.41#ibcon#enter sib2, iclass 35, count 2 2006.201.22:08:46.41#ibcon#flushed, iclass 35, count 2 2006.201.22:08:46.41#ibcon#about to write, iclass 35, count 2 2006.201.22:08:46.41#ibcon#wrote, iclass 35, count 2 2006.201.22:08:46.41#ibcon#about to read 3, iclass 35, count 2 2006.201.22:08:46.43#ibcon#read 3, iclass 35, count 2 2006.201.22:08:46.43#ibcon#about to read 4, iclass 35, count 2 2006.201.22:08:46.43#ibcon#read 4, iclass 35, count 2 2006.201.22:08:46.43#ibcon#about to read 5, iclass 35, count 2 2006.201.22:08:46.43#ibcon#read 5, iclass 35, count 2 2006.201.22:08:46.43#ibcon#about to read 6, iclass 35, count 2 2006.201.22:08:46.43#ibcon#read 6, iclass 35, count 2 2006.201.22:08:46.43#ibcon#end of sib2, iclass 35, count 2 2006.201.22:08:46.43#ibcon#*mode == 0, iclass 35, count 2 2006.201.22:08:46.43#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.22:08:46.43#ibcon#[27=AT06-04\r\n] 2006.201.22:08:46.43#ibcon#*before write, iclass 35, count 2 2006.201.22:08:46.43#ibcon#enter sib2, iclass 35, count 2 2006.201.22:08:46.43#ibcon#flushed, iclass 35, count 2 2006.201.22:08:46.43#ibcon#about to write, iclass 35, count 2 2006.201.22:08:46.43#ibcon#wrote, iclass 35, count 2 2006.201.22:08:46.43#ibcon#about to read 3, iclass 35, count 2 2006.201.22:08:46.43#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:08:46.46#ibcon#read 3, iclass 35, count 2 2006.201.22:08:46.46#ibcon#about to read 4, iclass 35, count 2 2006.201.22:08:46.46#ibcon#read 4, iclass 35, count 2 2006.201.22:08:46.46#ibcon#about to read 5, iclass 35, count 2 2006.201.22:08:46.46#ibcon#read 5, iclass 35, count 2 2006.201.22:08:46.46#ibcon#about to read 6, iclass 35, count 2 2006.201.22:08:46.46#ibcon#read 6, iclass 35, count 2 2006.201.22:08:46.46#ibcon#end of sib2, iclass 35, count 2 2006.201.22:08:46.46#ibcon#*after write, iclass 35, count 2 2006.201.22:08:46.46#ibcon#*before return 0, iclass 35, count 2 2006.201.22:08:46.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:08:46.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:08:46.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.22:08:46.46#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:46.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:08:46.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:08:46.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:08:46.58#ibcon#enter wrdev, iclass 35, count 0 2006.201.22:08:46.58#ibcon#first serial, iclass 35, count 0 2006.201.22:08:46.58#ibcon#enter sib2, iclass 35, count 0 2006.201.22:08:46.58#ibcon#flushed, iclass 35, count 0 2006.201.22:08:46.58#ibcon#about to write, iclass 35, count 0 2006.201.22:08:46.58#ibcon#wrote, iclass 35, count 0 2006.201.22:08:46.58#ibcon#about to read 3, iclass 35, count 0 2006.201.22:08:46.60#ibcon#read 3, iclass 35, count 0 2006.201.22:08:46.60#ibcon#about to read 4, iclass 35, count 0 2006.201.22:08:46.60#ibcon#read 4, iclass 35, count 0 2006.201.22:08:46.60#ibcon#about to read 5, iclass 35, count 0 2006.201.22:08:46.60#ibcon#read 5, iclass 35, count 0 2006.201.22:08:46.60#ibcon#about to read 6, iclass 35, count 0 2006.201.22:08:46.60#ibcon#read 6, iclass 35, count 0 2006.201.22:08:46.60#ibcon#end of sib2, iclass 35, count 0 2006.201.22:08:46.60#ibcon#*mode == 0, iclass 35, count 0 2006.201.22:08:46.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.22:08:46.60#ibcon#[27=USB\r\n] 2006.201.22:08:46.60#ibcon#*before write, iclass 35, count 0 2006.201.22:08:46.60#ibcon#enter sib2, iclass 35, count 0 2006.201.22:08:46.60#ibcon#flushed, iclass 35, count 0 2006.201.22:08:46.60#ibcon#about to write, iclass 35, count 0 2006.201.22:08:46.60#ibcon#wrote, iclass 35, count 0 2006.201.22:08:46.60#ibcon#about to read 3, iclass 35, count 0 2006.201.22:08:46.63#ibcon#read 3, iclass 35, count 0 2006.201.22:08:46.63#ibcon#about to read 4, iclass 35, count 0 2006.201.22:08:46.63#ibcon#read 4, iclass 35, count 0 2006.201.22:08:46.63#ibcon#about to read 5, iclass 35, count 0 2006.201.22:08:46.63#ibcon#read 5, iclass 35, count 0 2006.201.22:08:46.63#ibcon#about to read 6, iclass 35, count 0 2006.201.22:08:46.63#ibcon#read 6, iclass 35, count 0 2006.201.22:08:46.63#ibcon#end of sib2, iclass 35, count 0 2006.201.22:08:46.63#ibcon#*after write, iclass 35, count 0 2006.201.22:08:46.63#ibcon#*before return 0, iclass 35, count 0 2006.201.22:08:46.63#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:08:46.63#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:08:46.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.22:08:46.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.22:08:46.63$vck44/vblo=7,734.99 2006.201.22:08:46.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.22:08:46.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.22:08:46.63#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:46.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:46.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:46.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:46.63#ibcon#enter wrdev, iclass 38, count 0 2006.201.22:08:46.63#ibcon#first serial, iclass 38, count 0 2006.201.22:08:46.63#ibcon#enter sib2, iclass 38, count 0 2006.201.22:08:46.63#ibcon#flushed, iclass 38, count 0 2006.201.22:08:46.63#ibcon#about to write, iclass 38, count 0 2006.201.22:08:46.63#ibcon#wrote, iclass 38, count 0 2006.201.22:08:46.63#ibcon#about to read 3, iclass 38, count 0 2006.201.22:08:46.65#ibcon#read 3, iclass 38, count 0 2006.201.22:08:46.65#ibcon#about to read 4, iclass 38, count 0 2006.201.22:08:46.65#ibcon#read 4, iclass 38, count 0 2006.201.22:08:46.65#ibcon#about to read 5, iclass 38, count 0 2006.201.22:08:46.65#ibcon#read 5, iclass 38, count 0 2006.201.22:08:46.65#ibcon#about to read 6, iclass 38, count 0 2006.201.22:08:46.65#ibcon#read 6, iclass 38, count 0 2006.201.22:08:46.65#ibcon#end of sib2, iclass 38, count 0 2006.201.22:08:46.65#ibcon#*mode == 0, iclass 38, count 0 2006.201.22:08:46.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.22:08:46.65#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.22:08:46.65#ibcon#*before write, iclass 38, count 0 2006.201.22:08:46.65#ibcon#enter sib2, iclass 38, count 0 2006.201.22:08:46.65#ibcon#flushed, iclass 38, count 0 2006.201.22:08:46.65#ibcon#about to write, iclass 38, count 0 2006.201.22:08:46.65#ibcon#wrote, iclass 38, count 0 2006.201.22:08:46.65#ibcon#about to read 3, iclass 38, count 0 2006.201.22:08:46.69#ibcon#read 3, iclass 38, count 0 2006.201.22:08:46.69#ibcon#about to read 4, iclass 38, count 0 2006.201.22:08:46.69#ibcon#read 4, iclass 38, count 0 2006.201.22:08:46.69#ibcon#about to read 5, iclass 38, count 0 2006.201.22:08:46.69#ibcon#read 5, iclass 38, count 0 2006.201.22:08:46.69#ibcon#about to read 6, iclass 38, count 0 2006.201.22:08:46.69#ibcon#read 6, iclass 38, count 0 2006.201.22:08:46.69#ibcon#end of sib2, iclass 38, count 0 2006.201.22:08:46.69#ibcon#*after write, iclass 38, count 0 2006.201.22:08:46.69#ibcon#*before return 0, iclass 38, count 0 2006.201.22:08:46.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:46.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:08:46.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.22:08:46.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.22:08:46.69$vck44/vb=7,4 2006.201.22:08:46.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.22:08:46.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.22:08:46.69#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:46.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:46.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:46.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:46.75#ibcon#enter wrdev, iclass 40, count 2 2006.201.22:08:46.75#ibcon#first serial, iclass 40, count 2 2006.201.22:08:46.75#ibcon#enter sib2, iclass 40, count 2 2006.201.22:08:46.75#ibcon#flushed, iclass 40, count 2 2006.201.22:08:46.75#ibcon#about to write, iclass 40, count 2 2006.201.22:08:46.75#ibcon#wrote, iclass 40, count 2 2006.201.22:08:46.75#ibcon#about to read 3, iclass 40, count 2 2006.201.22:08:46.77#ibcon#read 3, iclass 40, count 2 2006.201.22:08:46.77#ibcon#about to read 4, iclass 40, count 2 2006.201.22:08:46.77#ibcon#read 4, iclass 40, count 2 2006.201.22:08:46.77#ibcon#about to read 5, iclass 40, count 2 2006.201.22:08:46.77#ibcon#read 5, iclass 40, count 2 2006.201.22:08:46.77#ibcon#about to read 6, iclass 40, count 2 2006.201.22:08:46.77#ibcon#read 6, iclass 40, count 2 2006.201.22:08:46.77#ibcon#end of sib2, iclass 40, count 2 2006.201.22:08:46.77#ibcon#*mode == 0, iclass 40, count 2 2006.201.22:08:46.77#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.22:08:46.77#ibcon#[27=AT07-04\r\n] 2006.201.22:08:46.77#ibcon#*before write, iclass 40, count 2 2006.201.22:08:46.77#ibcon#enter sib2, iclass 40, count 2 2006.201.22:08:46.77#ibcon#flushed, iclass 40, count 2 2006.201.22:08:46.77#ibcon#about to write, iclass 40, count 2 2006.201.22:08:46.77#ibcon#wrote, iclass 40, count 2 2006.201.22:08:46.77#ibcon#about to read 3, iclass 40, count 2 2006.201.22:08:46.80#ibcon#read 3, iclass 40, count 2 2006.201.22:08:46.80#ibcon#about to read 4, iclass 40, count 2 2006.201.22:08:46.80#ibcon#read 4, iclass 40, count 2 2006.201.22:08:46.80#ibcon#about to read 5, iclass 40, count 2 2006.201.22:08:46.80#ibcon#read 5, iclass 40, count 2 2006.201.22:08:46.80#ibcon#about to read 6, iclass 40, count 2 2006.201.22:08:46.80#ibcon#read 6, iclass 40, count 2 2006.201.22:08:46.80#ibcon#end of sib2, iclass 40, count 2 2006.201.22:08:46.80#ibcon#*after write, iclass 40, count 2 2006.201.22:08:46.80#ibcon#*before return 0, iclass 40, count 2 2006.201.22:08:46.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:46.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:08:46.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.22:08:46.80#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:46.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:46.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:46.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:46.92#ibcon#enter wrdev, iclass 40, count 0 2006.201.22:08:46.92#ibcon#first serial, iclass 40, count 0 2006.201.22:08:46.92#ibcon#enter sib2, iclass 40, count 0 2006.201.22:08:46.92#ibcon#flushed, iclass 40, count 0 2006.201.22:08:46.92#ibcon#about to write, iclass 40, count 0 2006.201.22:08:46.92#ibcon#wrote, iclass 40, count 0 2006.201.22:08:46.92#ibcon#about to read 3, iclass 40, count 0 2006.201.22:08:46.94#ibcon#read 3, iclass 40, count 0 2006.201.22:08:46.94#ibcon#about to read 4, iclass 40, count 0 2006.201.22:08:46.94#ibcon#read 4, iclass 40, count 0 2006.201.22:08:46.94#ibcon#about to read 5, iclass 40, count 0 2006.201.22:08:46.94#ibcon#read 5, iclass 40, count 0 2006.201.22:08:46.94#ibcon#about to read 6, iclass 40, count 0 2006.201.22:08:46.94#ibcon#read 6, iclass 40, count 0 2006.201.22:08:46.94#ibcon#end of sib2, iclass 40, count 0 2006.201.22:08:46.94#ibcon#*mode == 0, iclass 40, count 0 2006.201.22:08:46.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.22:08:46.94#ibcon#[27=USB\r\n] 2006.201.22:08:46.94#ibcon#*before write, iclass 40, count 0 2006.201.22:08:46.94#ibcon#enter sib2, iclass 40, count 0 2006.201.22:08:46.94#ibcon#flushed, iclass 40, count 0 2006.201.22:08:46.94#ibcon#about to write, iclass 40, count 0 2006.201.22:08:46.94#ibcon#wrote, iclass 40, count 0 2006.201.22:08:46.94#ibcon#about to read 3, iclass 40, count 0 2006.201.22:08:46.97#ibcon#read 3, iclass 40, count 0 2006.201.22:08:46.97#ibcon#about to read 4, iclass 40, count 0 2006.201.22:08:46.97#ibcon#read 4, iclass 40, count 0 2006.201.22:08:46.97#ibcon#about to read 5, iclass 40, count 0 2006.201.22:08:46.97#ibcon#read 5, iclass 40, count 0 2006.201.22:08:46.97#ibcon#about to read 6, iclass 40, count 0 2006.201.22:08:46.97#ibcon#read 6, iclass 40, count 0 2006.201.22:08:46.97#ibcon#end of sib2, iclass 40, count 0 2006.201.22:08:46.97#ibcon#*after write, iclass 40, count 0 2006.201.22:08:46.97#ibcon#*before return 0, iclass 40, count 0 2006.201.22:08:46.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:46.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:08:46.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.22:08:46.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.22:08:46.97$vck44/vblo=8,744.99 2006.201.22:08:46.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.22:08:46.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.22:08:46.97#ibcon#ireg 17 cls_cnt 0 2006.201.22:08:46.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:46.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:46.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:46.97#ibcon#enter wrdev, iclass 4, count 0 2006.201.22:08:46.97#ibcon#first serial, iclass 4, count 0 2006.201.22:08:46.97#ibcon#enter sib2, iclass 4, count 0 2006.201.22:08:46.97#ibcon#flushed, iclass 4, count 0 2006.201.22:08:46.97#ibcon#about to write, iclass 4, count 0 2006.201.22:08:46.97#ibcon#wrote, iclass 4, count 0 2006.201.22:08:46.97#ibcon#about to read 3, iclass 4, count 0 2006.201.22:08:46.99#ibcon#read 3, iclass 4, count 0 2006.201.22:08:46.99#ibcon#about to read 4, iclass 4, count 0 2006.201.22:08:46.99#ibcon#read 4, iclass 4, count 0 2006.201.22:08:46.99#ibcon#about to read 5, iclass 4, count 0 2006.201.22:08:46.99#ibcon#read 5, iclass 4, count 0 2006.201.22:08:46.99#ibcon#about to read 6, iclass 4, count 0 2006.201.22:08:46.99#ibcon#read 6, iclass 4, count 0 2006.201.22:08:46.99#ibcon#end of sib2, iclass 4, count 0 2006.201.22:08:46.99#ibcon#*mode == 0, iclass 4, count 0 2006.201.22:08:46.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.22:08:46.99#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.22:08:46.99#ibcon#*before write, iclass 4, count 0 2006.201.22:08:46.99#ibcon#enter sib2, iclass 4, count 0 2006.201.22:08:46.99#ibcon#flushed, iclass 4, count 0 2006.201.22:08:46.99#ibcon#about to write, iclass 4, count 0 2006.201.22:08:46.99#ibcon#wrote, iclass 4, count 0 2006.201.22:08:46.99#ibcon#about to read 3, iclass 4, count 0 2006.201.22:08:47.04#ibcon#read 3, iclass 4, count 0 2006.201.22:08:47.04#ibcon#about to read 4, iclass 4, count 0 2006.201.22:08:47.04#ibcon#read 4, iclass 4, count 0 2006.201.22:08:47.04#ibcon#about to read 5, iclass 4, count 0 2006.201.22:08:47.04#ibcon#read 5, iclass 4, count 0 2006.201.22:08:47.04#ibcon#about to read 6, iclass 4, count 0 2006.201.22:08:47.04#ibcon#read 6, iclass 4, count 0 2006.201.22:08:47.04#ibcon#end of sib2, iclass 4, count 0 2006.201.22:08:47.04#ibcon#*after write, iclass 4, count 0 2006.201.22:08:47.04#ibcon#*before return 0, iclass 4, count 0 2006.201.22:08:47.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:47.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:08:47.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.22:08:47.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.22:08:47.04$vck44/vb=8,4 2006.201.22:08:47.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.22:08:47.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.22:08:47.04#ibcon#ireg 11 cls_cnt 2 2006.201.22:08:47.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:47.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:47.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:47.09#ibcon#enter wrdev, iclass 6, count 2 2006.201.22:08:47.09#ibcon#first serial, iclass 6, count 2 2006.201.22:08:47.09#ibcon#enter sib2, iclass 6, count 2 2006.201.22:08:47.09#ibcon#flushed, iclass 6, count 2 2006.201.22:08:47.09#ibcon#about to write, iclass 6, count 2 2006.201.22:08:47.09#ibcon#wrote, iclass 6, count 2 2006.201.22:08:47.09#ibcon#about to read 3, iclass 6, count 2 2006.201.22:08:47.11#ibcon#read 3, iclass 6, count 2 2006.201.22:08:47.11#ibcon#about to read 4, iclass 6, count 2 2006.201.22:08:47.11#ibcon#read 4, iclass 6, count 2 2006.201.22:08:47.11#ibcon#about to read 5, iclass 6, count 2 2006.201.22:08:47.11#ibcon#read 5, iclass 6, count 2 2006.201.22:08:47.11#ibcon#about to read 6, iclass 6, count 2 2006.201.22:08:47.11#ibcon#read 6, iclass 6, count 2 2006.201.22:08:47.11#ibcon#end of sib2, iclass 6, count 2 2006.201.22:08:47.11#ibcon#*mode == 0, iclass 6, count 2 2006.201.22:08:47.11#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.22:08:47.11#ibcon#[27=AT08-04\r\n] 2006.201.22:08:47.11#ibcon#*before write, iclass 6, count 2 2006.201.22:08:47.11#ibcon#enter sib2, iclass 6, count 2 2006.201.22:08:47.11#ibcon#flushed, iclass 6, count 2 2006.201.22:08:47.11#ibcon#about to write, iclass 6, count 2 2006.201.22:08:47.11#ibcon#wrote, iclass 6, count 2 2006.201.22:08:47.11#ibcon#about to read 3, iclass 6, count 2 2006.201.22:08:47.14#ibcon#read 3, iclass 6, count 2 2006.201.22:08:47.14#ibcon#about to read 4, iclass 6, count 2 2006.201.22:08:47.14#ibcon#read 4, iclass 6, count 2 2006.201.22:08:47.14#ibcon#about to read 5, iclass 6, count 2 2006.201.22:08:47.14#ibcon#read 5, iclass 6, count 2 2006.201.22:08:47.14#ibcon#about to read 6, iclass 6, count 2 2006.201.22:08:47.14#ibcon#read 6, iclass 6, count 2 2006.201.22:08:47.14#ibcon#end of sib2, iclass 6, count 2 2006.201.22:08:47.14#ibcon#*after write, iclass 6, count 2 2006.201.22:08:47.14#ibcon#*before return 0, iclass 6, count 2 2006.201.22:08:47.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:47.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:08:47.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.22:08:47.14#ibcon#ireg 7 cls_cnt 0 2006.201.22:08:47.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:47.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:47.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:47.26#ibcon#enter wrdev, iclass 6, count 0 2006.201.22:08:47.26#ibcon#first serial, iclass 6, count 0 2006.201.22:08:47.26#ibcon#enter sib2, iclass 6, count 0 2006.201.22:08:47.26#ibcon#flushed, iclass 6, count 0 2006.201.22:08:47.26#ibcon#about to write, iclass 6, count 0 2006.201.22:08:47.26#ibcon#wrote, iclass 6, count 0 2006.201.22:08:47.26#ibcon#about to read 3, iclass 6, count 0 2006.201.22:08:47.28#ibcon#read 3, iclass 6, count 0 2006.201.22:08:47.28#ibcon#about to read 4, iclass 6, count 0 2006.201.22:08:47.28#ibcon#read 4, iclass 6, count 0 2006.201.22:08:47.28#ibcon#about to read 5, iclass 6, count 0 2006.201.22:08:47.28#ibcon#read 5, iclass 6, count 0 2006.201.22:08:47.28#ibcon#about to read 6, iclass 6, count 0 2006.201.22:08:47.28#ibcon#read 6, iclass 6, count 0 2006.201.22:08:47.28#ibcon#end of sib2, iclass 6, count 0 2006.201.22:08:47.28#ibcon#*mode == 0, iclass 6, count 0 2006.201.22:08:47.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.22:08:47.28#ibcon#[27=USB\r\n] 2006.201.22:08:47.28#ibcon#*before write, iclass 6, count 0 2006.201.22:08:47.28#ibcon#enter sib2, iclass 6, count 0 2006.201.22:08:47.28#ibcon#flushed, iclass 6, count 0 2006.201.22:08:47.28#ibcon#about to write, iclass 6, count 0 2006.201.22:08:47.28#ibcon#wrote, iclass 6, count 0 2006.201.22:08:47.28#ibcon#about to read 3, iclass 6, count 0 2006.201.22:08:47.31#ibcon#read 3, iclass 6, count 0 2006.201.22:08:47.31#ibcon#about to read 4, iclass 6, count 0 2006.201.22:08:47.31#ibcon#read 4, iclass 6, count 0 2006.201.22:08:47.31#ibcon#about to read 5, iclass 6, count 0 2006.201.22:08:47.31#ibcon#read 5, iclass 6, count 0 2006.201.22:08:47.31#ibcon#about to read 6, iclass 6, count 0 2006.201.22:08:47.31#ibcon#read 6, iclass 6, count 0 2006.201.22:08:47.31#ibcon#end of sib2, iclass 6, count 0 2006.201.22:08:47.31#ibcon#*after write, iclass 6, count 0 2006.201.22:08:47.31#ibcon#*before return 0, iclass 6, count 0 2006.201.22:08:47.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:47.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:08:47.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.22:08:47.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.22:08:47.31$vck44/vabw=wide 2006.201.22:08:47.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.22:08:47.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.22:08:47.31#ibcon#ireg 8 cls_cnt 0 2006.201.22:08:47.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:47.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:47.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:47.31#ibcon#enter wrdev, iclass 10, count 0 2006.201.22:08:47.31#ibcon#first serial, iclass 10, count 0 2006.201.22:08:47.31#ibcon#enter sib2, iclass 10, count 0 2006.201.22:08:47.31#ibcon#flushed, iclass 10, count 0 2006.201.22:08:47.31#ibcon#about to write, iclass 10, count 0 2006.201.22:08:47.31#ibcon#wrote, iclass 10, count 0 2006.201.22:08:47.31#ibcon#about to read 3, iclass 10, count 0 2006.201.22:08:47.33#ibcon#read 3, iclass 10, count 0 2006.201.22:08:47.33#ibcon#about to read 4, iclass 10, count 0 2006.201.22:08:47.33#ibcon#read 4, iclass 10, count 0 2006.201.22:08:47.33#ibcon#about to read 5, iclass 10, count 0 2006.201.22:08:47.33#ibcon#read 5, iclass 10, count 0 2006.201.22:08:47.33#ibcon#about to read 6, iclass 10, count 0 2006.201.22:08:47.33#ibcon#read 6, iclass 10, count 0 2006.201.22:08:47.33#ibcon#end of sib2, iclass 10, count 0 2006.201.22:08:47.33#ibcon#*mode == 0, iclass 10, count 0 2006.201.22:08:47.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.22:08:47.33#ibcon#[25=BW32\r\n] 2006.201.22:08:47.33#ibcon#*before write, iclass 10, count 0 2006.201.22:08:47.33#ibcon#enter sib2, iclass 10, count 0 2006.201.22:08:47.33#ibcon#flushed, iclass 10, count 0 2006.201.22:08:47.33#ibcon#about to write, iclass 10, count 0 2006.201.22:08:47.33#ibcon#wrote, iclass 10, count 0 2006.201.22:08:47.33#ibcon#about to read 3, iclass 10, count 0 2006.201.22:08:47.36#ibcon#read 3, iclass 10, count 0 2006.201.22:08:47.36#ibcon#about to read 4, iclass 10, count 0 2006.201.22:08:47.36#ibcon#read 4, iclass 10, count 0 2006.201.22:08:47.36#ibcon#about to read 5, iclass 10, count 0 2006.201.22:08:47.36#ibcon#read 5, iclass 10, count 0 2006.201.22:08:47.36#ibcon#about to read 6, iclass 10, count 0 2006.201.22:08:47.36#ibcon#read 6, iclass 10, count 0 2006.201.22:08:47.36#ibcon#end of sib2, iclass 10, count 0 2006.201.22:08:47.36#ibcon#*after write, iclass 10, count 0 2006.201.22:08:47.36#ibcon#*before return 0, iclass 10, count 0 2006.201.22:08:47.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:47.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:08:47.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.22:08:47.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.22:08:47.36$vck44/vbbw=wide 2006.201.22:08:47.36#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.22:08:47.36#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.22:08:47.36#ibcon#ireg 8 cls_cnt 0 2006.201.22:08:47.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:08:47.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:08:47.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:08:47.43#ibcon#enter wrdev, iclass 12, count 0 2006.201.22:08:47.43#ibcon#first serial, iclass 12, count 0 2006.201.22:08:47.43#ibcon#enter sib2, iclass 12, count 0 2006.201.22:08:47.43#ibcon#flushed, iclass 12, count 0 2006.201.22:08:47.43#ibcon#about to write, iclass 12, count 0 2006.201.22:08:47.43#ibcon#wrote, iclass 12, count 0 2006.201.22:08:47.43#ibcon#about to read 3, iclass 12, count 0 2006.201.22:08:47.45#ibcon#read 3, iclass 12, count 0 2006.201.22:08:47.45#ibcon#about to read 4, iclass 12, count 0 2006.201.22:08:47.45#ibcon#read 4, iclass 12, count 0 2006.201.22:08:47.45#ibcon#about to read 5, iclass 12, count 0 2006.201.22:08:47.45#ibcon#read 5, iclass 12, count 0 2006.201.22:08:47.45#ibcon#about to read 6, iclass 12, count 0 2006.201.22:08:47.45#ibcon#read 6, iclass 12, count 0 2006.201.22:08:47.45#ibcon#end of sib2, iclass 12, count 0 2006.201.22:08:47.45#ibcon#*mode == 0, iclass 12, count 0 2006.201.22:08:47.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.22:08:47.45#ibcon#[27=BW32\r\n] 2006.201.22:08:47.45#ibcon#*before write, iclass 12, count 0 2006.201.22:08:47.45#ibcon#enter sib2, iclass 12, count 0 2006.201.22:08:47.45#ibcon#flushed, iclass 12, count 0 2006.201.22:08:47.45#ibcon#about to write, iclass 12, count 0 2006.201.22:08:47.45#ibcon#wrote, iclass 12, count 0 2006.201.22:08:47.45#ibcon#about to read 3, iclass 12, count 0 2006.201.22:08:47.48#ibcon#read 3, iclass 12, count 0 2006.201.22:08:47.48#ibcon#about to read 4, iclass 12, count 0 2006.201.22:08:47.48#ibcon#read 4, iclass 12, count 0 2006.201.22:08:47.48#ibcon#about to read 5, iclass 12, count 0 2006.201.22:08:47.48#ibcon#read 5, iclass 12, count 0 2006.201.22:08:47.48#ibcon#about to read 6, iclass 12, count 0 2006.201.22:08:47.48#ibcon#read 6, iclass 12, count 0 2006.201.22:08:47.48#ibcon#end of sib2, iclass 12, count 0 2006.201.22:08:47.48#ibcon#*after write, iclass 12, count 0 2006.201.22:08:47.48#ibcon#*before return 0, iclass 12, count 0 2006.201.22:08:47.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:08:47.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:08:47.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.22:08:47.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.22:08:47.48$setupk4/ifdk4 2006.201.22:08:47.48$ifdk4/lo= 2006.201.22:08:47.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.22:08:47.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.22:08:47.48$ifdk4/patch= 2006.201.22:08:47.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.22:08:47.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.22:08:47.48$setupk4/!*+20s 2006.201.22:08:56.52#abcon#<5=/05 2.3 3.6 19.981001001.6\r\n> 2006.201.22:08:56.54#abcon#{5=INTERFACE CLEAR} 2006.201.22:08:56.60#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:09:01.94$setupk4/"tpicd 2006.201.22:09:01.94$setupk4/echo=off 2006.201.22:09:01.94$setupk4/xlog=off 2006.201.22:09:01.94:!2006.201.22:25:26 2006.201.22:09:24.14#trakl#Source acquired 2006.201.22:09:25.14#flagr#flagr/antenna,acquired 2006.201.22:25:26.00:preob 2006.201.22:25:26.13/onsource/TRACKING 2006.201.22:25:26.13:!2006.201.22:25:36 2006.201.22:25:36.00:"tape 2006.201.22:25:36.00:"st=record 2006.201.22:25:36.00:data_valid=on 2006.201.22:25:36.00:midob 2006.201.22:25:37.13/onsource/TRACKING 2006.201.22:25:37.13/wx/20.07,1001.6,100 2006.201.22:25:37.32/cable/+6.4827E-03 2006.201.22:25:38.41/va/01,08,usb,yes,48,51 2006.201.22:25:38.41/va/02,07,usb,yes,52,53 2006.201.22:25:38.41/va/03,08,usb,yes,47,49 2006.201.22:25:38.41/va/04,07,usb,yes,54,56 2006.201.22:25:38.41/va/05,04,usb,yes,48,49 2006.201.22:25:38.41/va/06,05,usb,yes,48,48 2006.201.22:25:38.41/va/07,05,usb,yes,47,49 2006.201.22:25:38.41/va/08,04,usb,yes,47,55 2006.201.22:25:38.64/valo/01,524.99,yes,locked 2006.201.22:25:38.64/valo/02,534.99,yes,locked 2006.201.22:25:38.64/valo/03,564.99,yes,locked 2006.201.22:25:38.64/valo/04,624.99,yes,locked 2006.201.22:25:38.64/valo/05,734.99,yes,locked 2006.201.22:25:38.64/valo/06,814.99,yes,locked 2006.201.22:25:38.64/valo/07,864.99,yes,locked 2006.201.22:25:38.64/valo/08,884.99,yes,locked 2006.201.22:25:39.73/vb/01,04,usb,yes,31,29 2006.201.22:25:39.73/vb/02,05,usb,yes,29,29 2006.201.22:25:39.73/vb/03,04,usb,yes,30,33 2006.201.22:25:39.73/vb/04,05,usb,yes,31,30 2006.201.22:25:39.73/vb/05,04,usb,yes,27,30 2006.201.22:25:39.73/vb/06,04,usb,yes,32,28 2006.201.22:25:39.73/vb/07,04,usb,yes,32,31 2006.201.22:25:39.73/vb/08,04,usb,yes,29,32 2006.201.22:25:39.97/vblo/01,629.99,yes,locked 2006.201.22:25:39.97/vblo/02,634.99,yes,locked 2006.201.22:25:39.97/vblo/03,649.99,yes,locked 2006.201.22:25:39.97/vblo/04,679.99,yes,locked 2006.201.22:25:39.97/vblo/05,709.99,yes,locked 2006.201.22:25:39.97/vblo/06,719.99,yes,locked 2006.201.22:25:39.97/vblo/07,734.99,yes,locked 2006.201.22:25:39.97/vblo/08,744.99,yes,locked 2006.201.22:25:40.12/vabw/8 2006.201.22:25:40.27/vbbw/8 2006.201.22:25:40.36/xfe/off,on,15.5 2006.201.22:25:40.73/ifatt/23,28,28,28 2006.201.22:25:41.07/fmout-gps/S +4.56E-07 2006.201.22:25:41.11:!2006.201.22:28:06 2006.201.22:28:06.00:data_valid=off 2006.201.22:28:06.00:"et 2006.201.22:28:06.00:!+3s 2006.201.22:28:09.02:"tape 2006.201.22:28:09.02:postob 2006.201.22:28:09.14/cable/+6.4839E-03 2006.201.22:28:09.14/wx/20.07,1001.5,100 2006.201.22:28:09.22/fmout-gps/S +4.57E-07 2006.201.22:28:09.22:scan_name=201-2236,jd0607,40 2006.201.22:28:09.23:source=2136+141,213901.31,142336.0,2000.0,cw 2006.201.22:28:10.14#flagr#flagr/antenna,new-source 2006.201.22:28:10.14:checkk5 2006.201.22:28:10.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.22:28:10.91/chk_autoobs//k5ts2/ autoobs is running! 2006.201.22:28:11.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.22:28:11.68/chk_autoobs//k5ts4/ autoobs is running! 2006.201.22:28:12.04/chk_obsdata//k5ts1/T2012225??a.dat file size is correct (nominal:600MB, actual:596MB). 2006.201.22:28:12.41/chk_obsdata//k5ts2/T2012225??b.dat file size is correct (nominal:600MB, actual:596MB). 2006.201.22:28:12.77/chk_obsdata//k5ts3/T2012225??c.dat file size is correct (nominal:600MB, actual:596MB). 2006.201.22:28:13.15/chk_obsdata//k5ts4/T2012225??d.dat file size is correct (nominal:600MB, actual:596MB). 2006.201.22:28:13.85/k5log//k5ts1_log_newline 2006.201.22:28:14.56/k5log//k5ts2_log_newline 2006.201.22:28:15.26/k5log//k5ts3_log_newline 2006.201.22:28:15.95/k5log//k5ts4_log_newline 2006.201.22:28:15.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.22:28:15.97:setupk4=1 2006.201.22:28:15.97$setupk4/echo=on 2006.201.22:28:15.97$setupk4/pcalon 2006.201.22:28:15.97$pcalon/"no phase cal control is implemented here 2006.201.22:28:15.97$setupk4/"tpicd=stop 2006.201.22:28:15.97$setupk4/"rec=synch_on 2006.201.22:28:15.97$setupk4/"rec_mode=128 2006.201.22:28:15.97$setupk4/!* 2006.201.22:28:15.97$setupk4/recpk4 2006.201.22:28:15.97$recpk4/recpatch= 2006.201.22:28:15.98$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.22:28:15.98$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.22:28:15.98$setupk4/vck44 2006.201.22:28:15.98$vck44/valo=1,524.99 2006.201.22:28:15.98#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.22:28:15.98#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.22:28:15.98#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:15.98#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:15.98#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:15.98#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:15.98#ibcon#enter wrdev, iclass 2, count 0 2006.201.22:28:15.98#ibcon#first serial, iclass 2, count 0 2006.201.22:28:15.98#ibcon#enter sib2, iclass 2, count 0 2006.201.22:28:15.98#ibcon#flushed, iclass 2, count 0 2006.201.22:28:15.98#ibcon#about to write, iclass 2, count 0 2006.201.22:28:15.98#ibcon#wrote, iclass 2, count 0 2006.201.22:28:15.98#ibcon#about to read 3, iclass 2, count 0 2006.201.22:28:16.01#ibcon#read 3, iclass 2, count 0 2006.201.22:28:16.01#ibcon#about to read 4, iclass 2, count 0 2006.201.22:28:16.01#ibcon#read 4, iclass 2, count 0 2006.201.22:28:16.01#ibcon#about to read 5, iclass 2, count 0 2006.201.22:28:16.01#ibcon#read 5, iclass 2, count 0 2006.201.22:28:16.01#ibcon#about to read 6, iclass 2, count 0 2006.201.22:28:16.01#ibcon#read 6, iclass 2, count 0 2006.201.22:28:16.01#ibcon#end of sib2, iclass 2, count 0 2006.201.22:28:16.01#ibcon#*mode == 0, iclass 2, count 0 2006.201.22:28:16.01#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.22:28:16.01#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.22:28:16.01#ibcon#*before write, iclass 2, count 0 2006.201.22:28:16.01#ibcon#enter sib2, iclass 2, count 0 2006.201.22:28:16.01#ibcon#flushed, iclass 2, count 0 2006.201.22:28:16.01#ibcon#about to write, iclass 2, count 0 2006.201.22:28:16.01#ibcon#wrote, iclass 2, count 0 2006.201.22:28:16.01#ibcon#about to read 3, iclass 2, count 0 2006.201.22:28:16.07#ibcon#read 3, iclass 2, count 0 2006.201.22:28:16.07#ibcon#about to read 4, iclass 2, count 0 2006.201.22:28:16.07#ibcon#read 4, iclass 2, count 0 2006.201.22:28:16.07#ibcon#about to read 5, iclass 2, count 0 2006.201.22:28:16.07#ibcon#read 5, iclass 2, count 0 2006.201.22:28:16.07#ibcon#about to read 6, iclass 2, count 0 2006.201.22:28:16.07#ibcon#read 6, iclass 2, count 0 2006.201.22:28:16.07#ibcon#end of sib2, iclass 2, count 0 2006.201.22:28:16.07#ibcon#*after write, iclass 2, count 0 2006.201.22:28:16.07#ibcon#*before return 0, iclass 2, count 0 2006.201.22:28:16.07#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:16.07#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:16.07#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.22:28:16.07#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.22:28:16.07$vck44/va=1,8 2006.201.22:28:16.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.22:28:16.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.22:28:16.07#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:16.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:16.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:16.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:16.07#ibcon#enter wrdev, iclass 5, count 2 2006.201.22:28:16.07#ibcon#first serial, iclass 5, count 2 2006.201.22:28:16.07#ibcon#enter sib2, iclass 5, count 2 2006.201.22:28:16.07#ibcon#flushed, iclass 5, count 2 2006.201.22:28:16.07#ibcon#about to write, iclass 5, count 2 2006.201.22:28:16.07#ibcon#wrote, iclass 5, count 2 2006.201.22:28:16.07#ibcon#about to read 3, iclass 5, count 2 2006.201.22:28:16.09#ibcon#read 3, iclass 5, count 2 2006.201.22:28:16.09#ibcon#about to read 4, iclass 5, count 2 2006.201.22:28:16.09#ibcon#read 4, iclass 5, count 2 2006.201.22:28:16.09#ibcon#about to read 5, iclass 5, count 2 2006.201.22:28:16.09#ibcon#read 5, iclass 5, count 2 2006.201.22:28:16.09#ibcon#about to read 6, iclass 5, count 2 2006.201.22:28:16.09#ibcon#read 6, iclass 5, count 2 2006.201.22:28:16.09#ibcon#end of sib2, iclass 5, count 2 2006.201.22:28:16.09#ibcon#*mode == 0, iclass 5, count 2 2006.201.22:28:16.09#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.22:28:16.09#ibcon#[25=AT01-08\r\n] 2006.201.22:28:16.09#ibcon#*before write, iclass 5, count 2 2006.201.22:28:16.09#ibcon#enter sib2, iclass 5, count 2 2006.201.22:28:16.09#ibcon#flushed, iclass 5, count 2 2006.201.22:28:16.09#ibcon#about to write, iclass 5, count 2 2006.201.22:28:16.09#ibcon#wrote, iclass 5, count 2 2006.201.22:28:16.09#ibcon#about to read 3, iclass 5, count 2 2006.201.22:28:16.13#ibcon#read 3, iclass 5, count 2 2006.201.22:28:16.13#ibcon#about to read 4, iclass 5, count 2 2006.201.22:28:16.13#ibcon#read 4, iclass 5, count 2 2006.201.22:28:16.13#ibcon#about to read 5, iclass 5, count 2 2006.201.22:28:16.13#ibcon#read 5, iclass 5, count 2 2006.201.22:28:16.13#ibcon#about to read 6, iclass 5, count 2 2006.201.22:28:16.13#ibcon#read 6, iclass 5, count 2 2006.201.22:28:16.13#ibcon#end of sib2, iclass 5, count 2 2006.201.22:28:16.13#ibcon#*after write, iclass 5, count 2 2006.201.22:28:16.13#ibcon#*before return 0, iclass 5, count 2 2006.201.22:28:16.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:16.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:16.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.22:28:16.13#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:16.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:16.17#abcon#<5=/04 1.9 3.6 20.071001001.5\r\n> 2006.201.22:28:16.19#abcon#{5=INTERFACE CLEAR} 2006.201.22:28:16.25#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:28:16.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:16.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:16.25#ibcon#enter wrdev, iclass 5, count 0 2006.201.22:28:16.25#ibcon#first serial, iclass 5, count 0 2006.201.22:28:16.25#ibcon#enter sib2, iclass 5, count 0 2006.201.22:28:16.25#ibcon#flushed, iclass 5, count 0 2006.201.22:28:16.25#ibcon#about to write, iclass 5, count 0 2006.201.22:28:16.25#ibcon#wrote, iclass 5, count 0 2006.201.22:28:16.25#ibcon#about to read 3, iclass 5, count 0 2006.201.22:28:16.27#ibcon#read 3, iclass 5, count 0 2006.201.22:28:16.27#ibcon#about to read 4, iclass 5, count 0 2006.201.22:28:16.27#ibcon#read 4, iclass 5, count 0 2006.201.22:28:16.27#ibcon#about to read 5, iclass 5, count 0 2006.201.22:28:16.27#ibcon#read 5, iclass 5, count 0 2006.201.22:28:16.27#ibcon#about to read 6, iclass 5, count 0 2006.201.22:28:16.27#ibcon#read 6, iclass 5, count 0 2006.201.22:28:16.27#ibcon#end of sib2, iclass 5, count 0 2006.201.22:28:16.27#ibcon#*mode == 0, iclass 5, count 0 2006.201.22:28:16.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.22:28:16.27#ibcon#[25=USB\r\n] 2006.201.22:28:16.27#ibcon#*before write, iclass 5, count 0 2006.201.22:28:16.27#ibcon#enter sib2, iclass 5, count 0 2006.201.22:28:16.27#ibcon#flushed, iclass 5, count 0 2006.201.22:28:16.27#ibcon#about to write, iclass 5, count 0 2006.201.22:28:16.27#ibcon#wrote, iclass 5, count 0 2006.201.22:28:16.27#ibcon#about to read 3, iclass 5, count 0 2006.201.22:28:16.30#ibcon#read 3, iclass 5, count 0 2006.201.22:28:16.30#ibcon#about to read 4, iclass 5, count 0 2006.201.22:28:16.30#ibcon#read 4, iclass 5, count 0 2006.201.22:28:16.30#ibcon#about to read 5, iclass 5, count 0 2006.201.22:28:16.30#ibcon#read 5, iclass 5, count 0 2006.201.22:28:16.30#ibcon#about to read 6, iclass 5, count 0 2006.201.22:28:16.30#ibcon#read 6, iclass 5, count 0 2006.201.22:28:16.30#ibcon#end of sib2, iclass 5, count 0 2006.201.22:28:16.30#ibcon#*after write, iclass 5, count 0 2006.201.22:28:16.30#ibcon#*before return 0, iclass 5, count 0 2006.201.22:28:16.30#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:16.30#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:16.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.22:28:16.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.22:28:16.30$vck44/valo=2,534.99 2006.201.22:28:16.30#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.22:28:16.30#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.22:28:16.30#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:16.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:16.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:16.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:16.30#ibcon#enter wrdev, iclass 13, count 0 2006.201.22:28:16.30#ibcon#first serial, iclass 13, count 0 2006.201.22:28:16.30#ibcon#enter sib2, iclass 13, count 0 2006.201.22:28:16.30#ibcon#flushed, iclass 13, count 0 2006.201.22:28:16.30#ibcon#about to write, iclass 13, count 0 2006.201.22:28:16.30#ibcon#wrote, iclass 13, count 0 2006.201.22:28:16.30#ibcon#about to read 3, iclass 13, count 0 2006.201.22:28:16.32#ibcon#read 3, iclass 13, count 0 2006.201.22:28:16.32#ibcon#about to read 4, iclass 13, count 0 2006.201.22:28:16.32#ibcon#read 4, iclass 13, count 0 2006.201.22:28:16.32#ibcon#about to read 5, iclass 13, count 0 2006.201.22:28:16.32#ibcon#read 5, iclass 13, count 0 2006.201.22:28:16.32#ibcon#about to read 6, iclass 13, count 0 2006.201.22:28:16.32#ibcon#read 6, iclass 13, count 0 2006.201.22:28:16.32#ibcon#end of sib2, iclass 13, count 0 2006.201.22:28:16.32#ibcon#*mode == 0, iclass 13, count 0 2006.201.22:28:16.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.22:28:16.32#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.22:28:16.32#ibcon#*before write, iclass 13, count 0 2006.201.22:28:16.32#ibcon#enter sib2, iclass 13, count 0 2006.201.22:28:16.32#ibcon#flushed, iclass 13, count 0 2006.201.22:28:16.32#ibcon#about to write, iclass 13, count 0 2006.201.22:28:16.32#ibcon#wrote, iclass 13, count 0 2006.201.22:28:16.32#ibcon#about to read 3, iclass 13, count 0 2006.201.22:28:16.36#ibcon#read 3, iclass 13, count 0 2006.201.22:28:16.36#ibcon#about to read 4, iclass 13, count 0 2006.201.22:28:16.36#ibcon#read 4, iclass 13, count 0 2006.201.22:28:16.36#ibcon#about to read 5, iclass 13, count 0 2006.201.22:28:16.36#ibcon#read 5, iclass 13, count 0 2006.201.22:28:16.36#ibcon#about to read 6, iclass 13, count 0 2006.201.22:28:16.36#ibcon#read 6, iclass 13, count 0 2006.201.22:28:16.36#ibcon#end of sib2, iclass 13, count 0 2006.201.22:28:16.36#ibcon#*after write, iclass 13, count 0 2006.201.22:28:16.36#ibcon#*before return 0, iclass 13, count 0 2006.201.22:28:16.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:16.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:16.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.22:28:16.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.22:28:16.36$vck44/va=2,7 2006.201.22:28:16.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.22:28:16.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.22:28:16.36#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:16.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:16.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:16.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:16.42#ibcon#enter wrdev, iclass 15, count 2 2006.201.22:28:16.42#ibcon#first serial, iclass 15, count 2 2006.201.22:28:16.42#ibcon#enter sib2, iclass 15, count 2 2006.201.22:28:16.42#ibcon#flushed, iclass 15, count 2 2006.201.22:28:16.42#ibcon#about to write, iclass 15, count 2 2006.201.22:28:16.42#ibcon#wrote, iclass 15, count 2 2006.201.22:28:16.42#ibcon#about to read 3, iclass 15, count 2 2006.201.22:28:16.44#ibcon#read 3, iclass 15, count 2 2006.201.22:28:16.44#ibcon#about to read 4, iclass 15, count 2 2006.201.22:28:16.44#ibcon#read 4, iclass 15, count 2 2006.201.22:28:16.44#ibcon#about to read 5, iclass 15, count 2 2006.201.22:28:16.44#ibcon#read 5, iclass 15, count 2 2006.201.22:28:16.44#ibcon#about to read 6, iclass 15, count 2 2006.201.22:28:16.44#ibcon#read 6, iclass 15, count 2 2006.201.22:28:16.44#ibcon#end of sib2, iclass 15, count 2 2006.201.22:28:16.44#ibcon#*mode == 0, iclass 15, count 2 2006.201.22:28:16.44#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.22:28:16.44#ibcon#[25=AT02-07\r\n] 2006.201.22:28:16.44#ibcon#*before write, iclass 15, count 2 2006.201.22:28:16.44#ibcon#enter sib2, iclass 15, count 2 2006.201.22:28:16.44#ibcon#flushed, iclass 15, count 2 2006.201.22:28:16.44#ibcon#about to write, iclass 15, count 2 2006.201.22:28:16.44#ibcon#wrote, iclass 15, count 2 2006.201.22:28:16.44#ibcon#about to read 3, iclass 15, count 2 2006.201.22:28:16.47#ibcon#read 3, iclass 15, count 2 2006.201.22:28:16.47#ibcon#about to read 4, iclass 15, count 2 2006.201.22:28:16.47#ibcon#read 4, iclass 15, count 2 2006.201.22:28:16.47#ibcon#about to read 5, iclass 15, count 2 2006.201.22:28:16.47#ibcon#read 5, iclass 15, count 2 2006.201.22:28:16.47#ibcon#about to read 6, iclass 15, count 2 2006.201.22:28:16.47#ibcon#read 6, iclass 15, count 2 2006.201.22:28:16.47#ibcon#end of sib2, iclass 15, count 2 2006.201.22:28:16.47#ibcon#*after write, iclass 15, count 2 2006.201.22:28:16.47#ibcon#*before return 0, iclass 15, count 2 2006.201.22:28:16.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:16.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:16.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.22:28:16.47#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:16.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:16.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:16.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:16.59#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:28:16.59#ibcon#first serial, iclass 15, count 0 2006.201.22:28:16.59#ibcon#enter sib2, iclass 15, count 0 2006.201.22:28:16.59#ibcon#flushed, iclass 15, count 0 2006.201.22:28:16.59#ibcon#about to write, iclass 15, count 0 2006.201.22:28:16.59#ibcon#wrote, iclass 15, count 0 2006.201.22:28:16.59#ibcon#about to read 3, iclass 15, count 0 2006.201.22:28:16.61#ibcon#read 3, iclass 15, count 0 2006.201.22:28:16.61#ibcon#about to read 4, iclass 15, count 0 2006.201.22:28:16.61#ibcon#read 4, iclass 15, count 0 2006.201.22:28:16.61#ibcon#about to read 5, iclass 15, count 0 2006.201.22:28:16.61#ibcon#read 5, iclass 15, count 0 2006.201.22:28:16.61#ibcon#about to read 6, iclass 15, count 0 2006.201.22:28:16.61#ibcon#read 6, iclass 15, count 0 2006.201.22:28:16.61#ibcon#end of sib2, iclass 15, count 0 2006.201.22:28:16.61#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:28:16.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:28:16.61#ibcon#[25=USB\r\n] 2006.201.22:28:16.61#ibcon#*before write, iclass 15, count 0 2006.201.22:28:16.61#ibcon#enter sib2, iclass 15, count 0 2006.201.22:28:16.61#ibcon#flushed, iclass 15, count 0 2006.201.22:28:16.61#ibcon#about to write, iclass 15, count 0 2006.201.22:28:16.61#ibcon#wrote, iclass 15, count 0 2006.201.22:28:16.61#ibcon#about to read 3, iclass 15, count 0 2006.201.22:28:16.64#ibcon#read 3, iclass 15, count 0 2006.201.22:28:16.64#ibcon#about to read 4, iclass 15, count 0 2006.201.22:28:16.64#ibcon#read 4, iclass 15, count 0 2006.201.22:28:16.64#ibcon#about to read 5, iclass 15, count 0 2006.201.22:28:16.64#ibcon#read 5, iclass 15, count 0 2006.201.22:28:16.64#ibcon#about to read 6, iclass 15, count 0 2006.201.22:28:16.64#ibcon#read 6, iclass 15, count 0 2006.201.22:28:16.64#ibcon#end of sib2, iclass 15, count 0 2006.201.22:28:16.64#ibcon#*after write, iclass 15, count 0 2006.201.22:28:16.64#ibcon#*before return 0, iclass 15, count 0 2006.201.22:28:16.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:16.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:16.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:28:16.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:28:16.64$vck44/valo=3,564.99 2006.201.22:28:16.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.22:28:16.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.22:28:16.64#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:16.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:16.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:16.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:16.64#ibcon#enter wrdev, iclass 17, count 0 2006.201.22:28:16.64#ibcon#first serial, iclass 17, count 0 2006.201.22:28:16.64#ibcon#enter sib2, iclass 17, count 0 2006.201.22:28:16.64#ibcon#flushed, iclass 17, count 0 2006.201.22:28:16.64#ibcon#about to write, iclass 17, count 0 2006.201.22:28:16.64#ibcon#wrote, iclass 17, count 0 2006.201.22:28:16.64#ibcon#about to read 3, iclass 17, count 0 2006.201.22:28:16.66#ibcon#read 3, iclass 17, count 0 2006.201.22:28:16.66#ibcon#about to read 4, iclass 17, count 0 2006.201.22:28:16.66#ibcon#read 4, iclass 17, count 0 2006.201.22:28:16.66#ibcon#about to read 5, iclass 17, count 0 2006.201.22:28:16.66#ibcon#read 5, iclass 17, count 0 2006.201.22:28:16.66#ibcon#about to read 6, iclass 17, count 0 2006.201.22:28:16.66#ibcon#read 6, iclass 17, count 0 2006.201.22:28:16.66#ibcon#end of sib2, iclass 17, count 0 2006.201.22:28:16.66#ibcon#*mode == 0, iclass 17, count 0 2006.201.22:28:16.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.22:28:16.66#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.22:28:16.66#ibcon#*before write, iclass 17, count 0 2006.201.22:28:16.66#ibcon#enter sib2, iclass 17, count 0 2006.201.22:28:16.66#ibcon#flushed, iclass 17, count 0 2006.201.22:28:16.66#ibcon#about to write, iclass 17, count 0 2006.201.22:28:16.66#ibcon#wrote, iclass 17, count 0 2006.201.22:28:16.66#ibcon#about to read 3, iclass 17, count 0 2006.201.22:28:16.71#ibcon#read 3, iclass 17, count 0 2006.201.22:28:16.71#ibcon#about to read 4, iclass 17, count 0 2006.201.22:28:16.71#ibcon#read 4, iclass 17, count 0 2006.201.22:28:16.71#ibcon#about to read 5, iclass 17, count 0 2006.201.22:28:16.71#ibcon#read 5, iclass 17, count 0 2006.201.22:28:16.71#ibcon#about to read 6, iclass 17, count 0 2006.201.22:28:16.71#ibcon#read 6, iclass 17, count 0 2006.201.22:28:16.71#ibcon#end of sib2, iclass 17, count 0 2006.201.22:28:16.71#ibcon#*after write, iclass 17, count 0 2006.201.22:28:16.71#ibcon#*before return 0, iclass 17, count 0 2006.201.22:28:16.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:16.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:16.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.22:28:16.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.22:28:16.71$vck44/va=3,8 2006.201.22:28:16.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.22:28:16.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.22:28:16.71#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:16.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:16.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:16.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:16.76#ibcon#enter wrdev, iclass 19, count 2 2006.201.22:28:16.76#ibcon#first serial, iclass 19, count 2 2006.201.22:28:16.76#ibcon#enter sib2, iclass 19, count 2 2006.201.22:28:16.76#ibcon#flushed, iclass 19, count 2 2006.201.22:28:16.76#ibcon#about to write, iclass 19, count 2 2006.201.22:28:16.76#ibcon#wrote, iclass 19, count 2 2006.201.22:28:16.76#ibcon#about to read 3, iclass 19, count 2 2006.201.22:28:16.78#ibcon#read 3, iclass 19, count 2 2006.201.22:28:16.78#ibcon#about to read 4, iclass 19, count 2 2006.201.22:28:16.78#ibcon#read 4, iclass 19, count 2 2006.201.22:28:16.78#ibcon#about to read 5, iclass 19, count 2 2006.201.22:28:16.78#ibcon#read 5, iclass 19, count 2 2006.201.22:28:16.78#ibcon#about to read 6, iclass 19, count 2 2006.201.22:28:16.78#ibcon#read 6, iclass 19, count 2 2006.201.22:28:16.78#ibcon#end of sib2, iclass 19, count 2 2006.201.22:28:16.78#ibcon#*mode == 0, iclass 19, count 2 2006.201.22:28:16.78#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.22:28:16.78#ibcon#[25=AT03-08\r\n] 2006.201.22:28:16.78#ibcon#*before write, iclass 19, count 2 2006.201.22:28:16.78#ibcon#enter sib2, iclass 19, count 2 2006.201.22:28:16.78#ibcon#flushed, iclass 19, count 2 2006.201.22:28:16.78#ibcon#about to write, iclass 19, count 2 2006.201.22:28:16.78#ibcon#wrote, iclass 19, count 2 2006.201.22:28:16.78#ibcon#about to read 3, iclass 19, count 2 2006.201.22:28:16.81#ibcon#read 3, iclass 19, count 2 2006.201.22:28:16.81#ibcon#about to read 4, iclass 19, count 2 2006.201.22:28:16.81#ibcon#read 4, iclass 19, count 2 2006.201.22:28:16.81#ibcon#about to read 5, iclass 19, count 2 2006.201.22:28:16.81#ibcon#read 5, iclass 19, count 2 2006.201.22:28:16.81#ibcon#about to read 6, iclass 19, count 2 2006.201.22:28:16.81#ibcon#read 6, iclass 19, count 2 2006.201.22:28:16.81#ibcon#end of sib2, iclass 19, count 2 2006.201.22:28:16.81#ibcon#*after write, iclass 19, count 2 2006.201.22:28:16.81#ibcon#*before return 0, iclass 19, count 2 2006.201.22:28:16.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:16.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:16.81#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.22:28:16.81#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:16.81#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:16.93#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:16.93#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:16.93#ibcon#enter wrdev, iclass 19, count 0 2006.201.22:28:16.93#ibcon#first serial, iclass 19, count 0 2006.201.22:28:16.93#ibcon#enter sib2, iclass 19, count 0 2006.201.22:28:16.93#ibcon#flushed, iclass 19, count 0 2006.201.22:28:16.93#ibcon#about to write, iclass 19, count 0 2006.201.22:28:16.93#ibcon#wrote, iclass 19, count 0 2006.201.22:28:16.93#ibcon#about to read 3, iclass 19, count 0 2006.201.22:28:16.95#ibcon#read 3, iclass 19, count 0 2006.201.22:28:16.95#ibcon#about to read 4, iclass 19, count 0 2006.201.22:28:16.95#ibcon#read 4, iclass 19, count 0 2006.201.22:28:16.95#ibcon#about to read 5, iclass 19, count 0 2006.201.22:28:16.95#ibcon#read 5, iclass 19, count 0 2006.201.22:28:16.95#ibcon#about to read 6, iclass 19, count 0 2006.201.22:28:16.95#ibcon#read 6, iclass 19, count 0 2006.201.22:28:16.95#ibcon#end of sib2, iclass 19, count 0 2006.201.22:28:16.95#ibcon#*mode == 0, iclass 19, count 0 2006.201.22:28:16.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.22:28:16.95#ibcon#[25=USB\r\n] 2006.201.22:28:16.95#ibcon#*before write, iclass 19, count 0 2006.201.22:28:16.95#ibcon#enter sib2, iclass 19, count 0 2006.201.22:28:16.95#ibcon#flushed, iclass 19, count 0 2006.201.22:28:16.95#ibcon#about to write, iclass 19, count 0 2006.201.22:28:16.95#ibcon#wrote, iclass 19, count 0 2006.201.22:28:16.95#ibcon#about to read 3, iclass 19, count 0 2006.201.22:28:16.98#ibcon#read 3, iclass 19, count 0 2006.201.22:28:16.98#ibcon#about to read 4, iclass 19, count 0 2006.201.22:28:16.98#ibcon#read 4, iclass 19, count 0 2006.201.22:28:16.98#ibcon#about to read 5, iclass 19, count 0 2006.201.22:28:16.98#ibcon#read 5, iclass 19, count 0 2006.201.22:28:16.98#ibcon#about to read 6, iclass 19, count 0 2006.201.22:28:16.98#ibcon#read 6, iclass 19, count 0 2006.201.22:28:16.98#ibcon#end of sib2, iclass 19, count 0 2006.201.22:28:16.98#ibcon#*after write, iclass 19, count 0 2006.201.22:28:16.98#ibcon#*before return 0, iclass 19, count 0 2006.201.22:28:16.98#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:16.98#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:16.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.22:28:16.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.22:28:16.98$vck44/valo=4,624.99 2006.201.22:28:16.98#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.22:28:16.98#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.22:28:16.98#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:16.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:16.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:16.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:16.98#ibcon#enter wrdev, iclass 21, count 0 2006.201.22:28:16.98#ibcon#first serial, iclass 21, count 0 2006.201.22:28:16.98#ibcon#enter sib2, iclass 21, count 0 2006.201.22:28:16.98#ibcon#flushed, iclass 21, count 0 2006.201.22:28:16.98#ibcon#about to write, iclass 21, count 0 2006.201.22:28:16.98#ibcon#wrote, iclass 21, count 0 2006.201.22:28:16.98#ibcon#about to read 3, iclass 21, count 0 2006.201.22:28:17.00#ibcon#read 3, iclass 21, count 0 2006.201.22:28:17.00#ibcon#about to read 4, iclass 21, count 0 2006.201.22:28:17.00#ibcon#read 4, iclass 21, count 0 2006.201.22:28:17.00#ibcon#about to read 5, iclass 21, count 0 2006.201.22:28:17.00#ibcon#read 5, iclass 21, count 0 2006.201.22:28:17.00#ibcon#about to read 6, iclass 21, count 0 2006.201.22:28:17.00#ibcon#read 6, iclass 21, count 0 2006.201.22:28:17.00#ibcon#end of sib2, iclass 21, count 0 2006.201.22:28:17.00#ibcon#*mode == 0, iclass 21, count 0 2006.201.22:28:17.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.22:28:17.00#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.22:28:17.00#ibcon#*before write, iclass 21, count 0 2006.201.22:28:17.00#ibcon#enter sib2, iclass 21, count 0 2006.201.22:28:17.00#ibcon#flushed, iclass 21, count 0 2006.201.22:28:17.00#ibcon#about to write, iclass 21, count 0 2006.201.22:28:17.00#ibcon#wrote, iclass 21, count 0 2006.201.22:28:17.00#ibcon#about to read 3, iclass 21, count 0 2006.201.22:28:17.04#ibcon#read 3, iclass 21, count 0 2006.201.22:28:17.04#ibcon#about to read 4, iclass 21, count 0 2006.201.22:28:17.04#ibcon#read 4, iclass 21, count 0 2006.201.22:28:17.04#ibcon#about to read 5, iclass 21, count 0 2006.201.22:28:17.04#ibcon#read 5, iclass 21, count 0 2006.201.22:28:17.04#ibcon#about to read 6, iclass 21, count 0 2006.201.22:28:17.04#ibcon#read 6, iclass 21, count 0 2006.201.22:28:17.04#ibcon#end of sib2, iclass 21, count 0 2006.201.22:28:17.04#ibcon#*after write, iclass 21, count 0 2006.201.22:28:17.04#ibcon#*before return 0, iclass 21, count 0 2006.201.22:28:17.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:17.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:17.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.22:28:17.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.22:28:17.04$vck44/va=4,7 2006.201.22:28:17.04#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.22:28:17.04#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.22:28:17.04#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:17.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:17.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:17.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:17.10#ibcon#enter wrdev, iclass 23, count 2 2006.201.22:28:17.10#ibcon#first serial, iclass 23, count 2 2006.201.22:28:17.10#ibcon#enter sib2, iclass 23, count 2 2006.201.22:28:17.10#ibcon#flushed, iclass 23, count 2 2006.201.22:28:17.10#ibcon#about to write, iclass 23, count 2 2006.201.22:28:17.10#ibcon#wrote, iclass 23, count 2 2006.201.22:28:17.10#ibcon#about to read 3, iclass 23, count 2 2006.201.22:28:17.12#ibcon#read 3, iclass 23, count 2 2006.201.22:28:17.12#ibcon#about to read 4, iclass 23, count 2 2006.201.22:28:17.12#ibcon#read 4, iclass 23, count 2 2006.201.22:28:17.12#ibcon#about to read 5, iclass 23, count 2 2006.201.22:28:17.12#ibcon#read 5, iclass 23, count 2 2006.201.22:28:17.12#ibcon#about to read 6, iclass 23, count 2 2006.201.22:28:17.12#ibcon#read 6, iclass 23, count 2 2006.201.22:28:17.12#ibcon#end of sib2, iclass 23, count 2 2006.201.22:28:17.12#ibcon#*mode == 0, iclass 23, count 2 2006.201.22:28:17.12#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.22:28:17.12#ibcon#[25=AT04-07\r\n] 2006.201.22:28:17.12#ibcon#*before write, iclass 23, count 2 2006.201.22:28:17.12#ibcon#enter sib2, iclass 23, count 2 2006.201.22:28:17.12#ibcon#flushed, iclass 23, count 2 2006.201.22:28:17.12#ibcon#about to write, iclass 23, count 2 2006.201.22:28:17.12#ibcon#wrote, iclass 23, count 2 2006.201.22:28:17.12#ibcon#about to read 3, iclass 23, count 2 2006.201.22:28:17.15#ibcon#read 3, iclass 23, count 2 2006.201.22:28:17.15#ibcon#about to read 4, iclass 23, count 2 2006.201.22:28:17.15#ibcon#read 4, iclass 23, count 2 2006.201.22:28:17.15#ibcon#about to read 5, iclass 23, count 2 2006.201.22:28:17.15#ibcon#read 5, iclass 23, count 2 2006.201.22:28:17.15#ibcon#about to read 6, iclass 23, count 2 2006.201.22:28:17.15#ibcon#read 6, iclass 23, count 2 2006.201.22:28:17.15#ibcon#end of sib2, iclass 23, count 2 2006.201.22:28:17.15#ibcon#*after write, iclass 23, count 2 2006.201.22:28:17.15#ibcon#*before return 0, iclass 23, count 2 2006.201.22:28:17.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:17.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:17.15#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.22:28:17.15#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:17.15#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:17.27#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:17.27#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:17.27#ibcon#enter wrdev, iclass 23, count 0 2006.201.22:28:17.27#ibcon#first serial, iclass 23, count 0 2006.201.22:28:17.27#ibcon#enter sib2, iclass 23, count 0 2006.201.22:28:17.27#ibcon#flushed, iclass 23, count 0 2006.201.22:28:17.27#ibcon#about to write, iclass 23, count 0 2006.201.22:28:17.27#ibcon#wrote, iclass 23, count 0 2006.201.22:28:17.27#ibcon#about to read 3, iclass 23, count 0 2006.201.22:28:17.29#ibcon#read 3, iclass 23, count 0 2006.201.22:28:17.29#ibcon#about to read 4, iclass 23, count 0 2006.201.22:28:17.29#ibcon#read 4, iclass 23, count 0 2006.201.22:28:17.29#ibcon#about to read 5, iclass 23, count 0 2006.201.22:28:17.29#ibcon#read 5, iclass 23, count 0 2006.201.22:28:17.29#ibcon#about to read 6, iclass 23, count 0 2006.201.22:28:17.29#ibcon#read 6, iclass 23, count 0 2006.201.22:28:17.29#ibcon#end of sib2, iclass 23, count 0 2006.201.22:28:17.29#ibcon#*mode == 0, iclass 23, count 0 2006.201.22:28:17.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.22:28:17.29#ibcon#[25=USB\r\n] 2006.201.22:28:17.29#ibcon#*before write, iclass 23, count 0 2006.201.22:28:17.29#ibcon#enter sib2, iclass 23, count 0 2006.201.22:28:17.29#ibcon#flushed, iclass 23, count 0 2006.201.22:28:17.29#ibcon#about to write, iclass 23, count 0 2006.201.22:28:17.29#ibcon#wrote, iclass 23, count 0 2006.201.22:28:17.29#ibcon#about to read 3, iclass 23, count 0 2006.201.22:28:17.32#ibcon#read 3, iclass 23, count 0 2006.201.22:28:17.32#ibcon#about to read 4, iclass 23, count 0 2006.201.22:28:17.32#ibcon#read 4, iclass 23, count 0 2006.201.22:28:17.32#ibcon#about to read 5, iclass 23, count 0 2006.201.22:28:17.32#ibcon#read 5, iclass 23, count 0 2006.201.22:28:17.32#ibcon#about to read 6, iclass 23, count 0 2006.201.22:28:17.32#ibcon#read 6, iclass 23, count 0 2006.201.22:28:17.32#ibcon#end of sib2, iclass 23, count 0 2006.201.22:28:17.32#ibcon#*after write, iclass 23, count 0 2006.201.22:28:17.32#ibcon#*before return 0, iclass 23, count 0 2006.201.22:28:17.32#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:17.32#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:17.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.22:28:17.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.22:28:17.32$vck44/valo=5,734.99 2006.201.22:28:17.32#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.22:28:17.32#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.22:28:17.32#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:17.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:17.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:17.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:17.32#ibcon#enter wrdev, iclass 25, count 0 2006.201.22:28:17.32#ibcon#first serial, iclass 25, count 0 2006.201.22:28:17.32#ibcon#enter sib2, iclass 25, count 0 2006.201.22:28:17.32#ibcon#flushed, iclass 25, count 0 2006.201.22:28:17.32#ibcon#about to write, iclass 25, count 0 2006.201.22:28:17.32#ibcon#wrote, iclass 25, count 0 2006.201.22:28:17.32#ibcon#about to read 3, iclass 25, count 0 2006.201.22:28:17.34#ibcon#read 3, iclass 25, count 0 2006.201.22:28:17.34#ibcon#about to read 4, iclass 25, count 0 2006.201.22:28:17.34#ibcon#read 4, iclass 25, count 0 2006.201.22:28:17.34#ibcon#about to read 5, iclass 25, count 0 2006.201.22:28:17.34#ibcon#read 5, iclass 25, count 0 2006.201.22:28:17.34#ibcon#about to read 6, iclass 25, count 0 2006.201.22:28:17.34#ibcon#read 6, iclass 25, count 0 2006.201.22:28:17.34#ibcon#end of sib2, iclass 25, count 0 2006.201.22:28:17.34#ibcon#*mode == 0, iclass 25, count 0 2006.201.22:28:17.34#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.22:28:17.34#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.22:28:17.34#ibcon#*before write, iclass 25, count 0 2006.201.22:28:17.34#ibcon#enter sib2, iclass 25, count 0 2006.201.22:28:17.34#ibcon#flushed, iclass 25, count 0 2006.201.22:28:17.34#ibcon#about to write, iclass 25, count 0 2006.201.22:28:17.34#ibcon#wrote, iclass 25, count 0 2006.201.22:28:17.34#ibcon#about to read 3, iclass 25, count 0 2006.201.22:28:17.38#ibcon#read 3, iclass 25, count 0 2006.201.22:28:17.38#ibcon#about to read 4, iclass 25, count 0 2006.201.22:28:17.38#ibcon#read 4, iclass 25, count 0 2006.201.22:28:17.38#ibcon#about to read 5, iclass 25, count 0 2006.201.22:28:17.38#ibcon#read 5, iclass 25, count 0 2006.201.22:28:17.38#ibcon#about to read 6, iclass 25, count 0 2006.201.22:28:17.38#ibcon#read 6, iclass 25, count 0 2006.201.22:28:17.38#ibcon#end of sib2, iclass 25, count 0 2006.201.22:28:17.38#ibcon#*after write, iclass 25, count 0 2006.201.22:28:17.38#ibcon#*before return 0, iclass 25, count 0 2006.201.22:28:17.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:17.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:17.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.22:28:17.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.22:28:17.38$vck44/va=5,4 2006.201.22:28:17.38#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.22:28:17.38#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.22:28:17.38#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:17.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:17.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:17.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:17.44#ibcon#enter wrdev, iclass 27, count 2 2006.201.22:28:17.44#ibcon#first serial, iclass 27, count 2 2006.201.22:28:17.44#ibcon#enter sib2, iclass 27, count 2 2006.201.22:28:17.44#ibcon#flushed, iclass 27, count 2 2006.201.22:28:17.44#ibcon#about to write, iclass 27, count 2 2006.201.22:28:17.44#ibcon#wrote, iclass 27, count 2 2006.201.22:28:17.44#ibcon#about to read 3, iclass 27, count 2 2006.201.22:28:17.46#ibcon#read 3, iclass 27, count 2 2006.201.22:28:17.46#ibcon#about to read 4, iclass 27, count 2 2006.201.22:28:17.46#ibcon#read 4, iclass 27, count 2 2006.201.22:28:17.46#ibcon#about to read 5, iclass 27, count 2 2006.201.22:28:17.46#ibcon#read 5, iclass 27, count 2 2006.201.22:28:17.46#ibcon#about to read 6, iclass 27, count 2 2006.201.22:28:17.46#ibcon#read 6, iclass 27, count 2 2006.201.22:28:17.46#ibcon#end of sib2, iclass 27, count 2 2006.201.22:28:17.46#ibcon#*mode == 0, iclass 27, count 2 2006.201.22:28:17.46#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.22:28:17.46#ibcon#[25=AT05-04\r\n] 2006.201.22:28:17.46#ibcon#*before write, iclass 27, count 2 2006.201.22:28:17.46#ibcon#enter sib2, iclass 27, count 2 2006.201.22:28:17.46#ibcon#flushed, iclass 27, count 2 2006.201.22:28:17.46#ibcon#about to write, iclass 27, count 2 2006.201.22:28:17.46#ibcon#wrote, iclass 27, count 2 2006.201.22:28:17.46#ibcon#about to read 3, iclass 27, count 2 2006.201.22:28:17.49#ibcon#read 3, iclass 27, count 2 2006.201.22:28:17.49#ibcon#about to read 4, iclass 27, count 2 2006.201.22:28:17.49#ibcon#read 4, iclass 27, count 2 2006.201.22:28:17.49#ibcon#about to read 5, iclass 27, count 2 2006.201.22:28:17.49#ibcon#read 5, iclass 27, count 2 2006.201.22:28:17.49#ibcon#about to read 6, iclass 27, count 2 2006.201.22:28:17.49#ibcon#read 6, iclass 27, count 2 2006.201.22:28:17.49#ibcon#end of sib2, iclass 27, count 2 2006.201.22:28:17.49#ibcon#*after write, iclass 27, count 2 2006.201.22:28:17.49#ibcon#*before return 0, iclass 27, count 2 2006.201.22:28:17.49#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:17.49#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:17.49#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.22:28:17.49#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:17.49#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:17.61#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:17.61#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:17.61#ibcon#enter wrdev, iclass 27, count 0 2006.201.22:28:17.61#ibcon#first serial, iclass 27, count 0 2006.201.22:28:17.61#ibcon#enter sib2, iclass 27, count 0 2006.201.22:28:17.61#ibcon#flushed, iclass 27, count 0 2006.201.22:28:17.61#ibcon#about to write, iclass 27, count 0 2006.201.22:28:17.61#ibcon#wrote, iclass 27, count 0 2006.201.22:28:17.61#ibcon#about to read 3, iclass 27, count 0 2006.201.22:28:17.63#ibcon#read 3, iclass 27, count 0 2006.201.22:28:17.63#ibcon#about to read 4, iclass 27, count 0 2006.201.22:28:17.63#ibcon#read 4, iclass 27, count 0 2006.201.22:28:17.63#ibcon#about to read 5, iclass 27, count 0 2006.201.22:28:17.63#ibcon#read 5, iclass 27, count 0 2006.201.22:28:17.63#ibcon#about to read 6, iclass 27, count 0 2006.201.22:28:17.63#ibcon#read 6, iclass 27, count 0 2006.201.22:28:17.63#ibcon#end of sib2, iclass 27, count 0 2006.201.22:28:17.63#ibcon#*mode == 0, iclass 27, count 0 2006.201.22:28:17.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.22:28:17.63#ibcon#[25=USB\r\n] 2006.201.22:28:17.63#ibcon#*before write, iclass 27, count 0 2006.201.22:28:17.63#ibcon#enter sib2, iclass 27, count 0 2006.201.22:28:17.63#ibcon#flushed, iclass 27, count 0 2006.201.22:28:17.63#ibcon#about to write, iclass 27, count 0 2006.201.22:28:17.63#ibcon#wrote, iclass 27, count 0 2006.201.22:28:17.63#ibcon#about to read 3, iclass 27, count 0 2006.201.22:28:17.66#ibcon#read 3, iclass 27, count 0 2006.201.22:28:17.66#ibcon#about to read 4, iclass 27, count 0 2006.201.22:28:17.66#ibcon#read 4, iclass 27, count 0 2006.201.22:28:17.66#ibcon#about to read 5, iclass 27, count 0 2006.201.22:28:17.66#ibcon#read 5, iclass 27, count 0 2006.201.22:28:17.66#ibcon#about to read 6, iclass 27, count 0 2006.201.22:28:17.66#ibcon#read 6, iclass 27, count 0 2006.201.22:28:17.66#ibcon#end of sib2, iclass 27, count 0 2006.201.22:28:17.66#ibcon#*after write, iclass 27, count 0 2006.201.22:28:17.66#ibcon#*before return 0, iclass 27, count 0 2006.201.22:28:17.66#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:17.66#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:17.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.22:28:17.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.22:28:17.66$vck44/valo=6,814.99 2006.201.22:28:17.66#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.22:28:17.66#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.22:28:17.66#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:17.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:17.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:17.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:17.66#ibcon#enter wrdev, iclass 29, count 0 2006.201.22:28:17.66#ibcon#first serial, iclass 29, count 0 2006.201.22:28:17.66#ibcon#enter sib2, iclass 29, count 0 2006.201.22:28:17.66#ibcon#flushed, iclass 29, count 0 2006.201.22:28:17.66#ibcon#about to write, iclass 29, count 0 2006.201.22:28:17.66#ibcon#wrote, iclass 29, count 0 2006.201.22:28:17.66#ibcon#about to read 3, iclass 29, count 0 2006.201.22:28:17.68#ibcon#read 3, iclass 29, count 0 2006.201.22:28:17.68#ibcon#about to read 4, iclass 29, count 0 2006.201.22:28:17.68#ibcon#read 4, iclass 29, count 0 2006.201.22:28:17.68#ibcon#about to read 5, iclass 29, count 0 2006.201.22:28:17.68#ibcon#read 5, iclass 29, count 0 2006.201.22:28:17.68#ibcon#about to read 6, iclass 29, count 0 2006.201.22:28:17.68#ibcon#read 6, iclass 29, count 0 2006.201.22:28:17.68#ibcon#end of sib2, iclass 29, count 0 2006.201.22:28:17.68#ibcon#*mode == 0, iclass 29, count 0 2006.201.22:28:17.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.22:28:17.68#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.22:28:17.68#ibcon#*before write, iclass 29, count 0 2006.201.22:28:17.68#ibcon#enter sib2, iclass 29, count 0 2006.201.22:28:17.68#ibcon#flushed, iclass 29, count 0 2006.201.22:28:17.68#ibcon#about to write, iclass 29, count 0 2006.201.22:28:17.68#ibcon#wrote, iclass 29, count 0 2006.201.22:28:17.68#ibcon#about to read 3, iclass 29, count 0 2006.201.22:28:17.72#ibcon#read 3, iclass 29, count 0 2006.201.22:28:17.72#ibcon#about to read 4, iclass 29, count 0 2006.201.22:28:17.72#ibcon#read 4, iclass 29, count 0 2006.201.22:28:17.72#ibcon#about to read 5, iclass 29, count 0 2006.201.22:28:17.72#ibcon#read 5, iclass 29, count 0 2006.201.22:28:17.72#ibcon#about to read 6, iclass 29, count 0 2006.201.22:28:17.72#ibcon#read 6, iclass 29, count 0 2006.201.22:28:17.72#ibcon#end of sib2, iclass 29, count 0 2006.201.22:28:17.72#ibcon#*after write, iclass 29, count 0 2006.201.22:28:17.72#ibcon#*before return 0, iclass 29, count 0 2006.201.22:28:17.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:17.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:17.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.22:28:17.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.22:28:17.72$vck44/va=6,5 2006.201.22:28:17.72#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.22:28:17.72#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.22:28:17.72#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:17.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:17.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:17.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:17.78#ibcon#enter wrdev, iclass 31, count 2 2006.201.22:28:17.78#ibcon#first serial, iclass 31, count 2 2006.201.22:28:17.78#ibcon#enter sib2, iclass 31, count 2 2006.201.22:28:17.78#ibcon#flushed, iclass 31, count 2 2006.201.22:28:17.78#ibcon#about to write, iclass 31, count 2 2006.201.22:28:17.78#ibcon#wrote, iclass 31, count 2 2006.201.22:28:17.78#ibcon#about to read 3, iclass 31, count 2 2006.201.22:28:17.80#ibcon#read 3, iclass 31, count 2 2006.201.22:28:17.80#ibcon#about to read 4, iclass 31, count 2 2006.201.22:28:17.80#ibcon#read 4, iclass 31, count 2 2006.201.22:28:17.80#ibcon#about to read 5, iclass 31, count 2 2006.201.22:28:17.80#ibcon#read 5, iclass 31, count 2 2006.201.22:28:17.80#ibcon#about to read 6, iclass 31, count 2 2006.201.22:28:17.80#ibcon#read 6, iclass 31, count 2 2006.201.22:28:17.80#ibcon#end of sib2, iclass 31, count 2 2006.201.22:28:17.80#ibcon#*mode == 0, iclass 31, count 2 2006.201.22:28:17.80#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.22:28:17.80#ibcon#[25=AT06-05\r\n] 2006.201.22:28:17.80#ibcon#*before write, iclass 31, count 2 2006.201.22:28:17.80#ibcon#enter sib2, iclass 31, count 2 2006.201.22:28:17.80#ibcon#flushed, iclass 31, count 2 2006.201.22:28:17.80#ibcon#about to write, iclass 31, count 2 2006.201.22:28:17.80#ibcon#wrote, iclass 31, count 2 2006.201.22:28:17.80#ibcon#about to read 3, iclass 31, count 2 2006.201.22:28:17.83#ibcon#read 3, iclass 31, count 2 2006.201.22:28:17.83#ibcon#about to read 4, iclass 31, count 2 2006.201.22:28:17.83#ibcon#read 4, iclass 31, count 2 2006.201.22:28:17.83#ibcon#about to read 5, iclass 31, count 2 2006.201.22:28:17.83#ibcon#read 5, iclass 31, count 2 2006.201.22:28:17.83#ibcon#about to read 6, iclass 31, count 2 2006.201.22:28:17.83#ibcon#read 6, iclass 31, count 2 2006.201.22:28:17.83#ibcon#end of sib2, iclass 31, count 2 2006.201.22:28:17.83#ibcon#*after write, iclass 31, count 2 2006.201.22:28:17.83#ibcon#*before return 0, iclass 31, count 2 2006.201.22:28:17.83#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:17.83#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:17.83#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.22:28:17.83#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:17.83#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:17.95#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:17.95#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:17.95#ibcon#enter wrdev, iclass 31, count 0 2006.201.22:28:17.95#ibcon#first serial, iclass 31, count 0 2006.201.22:28:17.95#ibcon#enter sib2, iclass 31, count 0 2006.201.22:28:17.95#ibcon#flushed, iclass 31, count 0 2006.201.22:28:17.95#ibcon#about to write, iclass 31, count 0 2006.201.22:28:17.95#ibcon#wrote, iclass 31, count 0 2006.201.22:28:17.95#ibcon#about to read 3, iclass 31, count 0 2006.201.22:28:17.97#ibcon#read 3, iclass 31, count 0 2006.201.22:28:17.97#ibcon#about to read 4, iclass 31, count 0 2006.201.22:28:17.97#ibcon#read 4, iclass 31, count 0 2006.201.22:28:17.97#ibcon#about to read 5, iclass 31, count 0 2006.201.22:28:17.97#ibcon#read 5, iclass 31, count 0 2006.201.22:28:17.97#ibcon#about to read 6, iclass 31, count 0 2006.201.22:28:17.97#ibcon#read 6, iclass 31, count 0 2006.201.22:28:17.97#ibcon#end of sib2, iclass 31, count 0 2006.201.22:28:17.97#ibcon#*mode == 0, iclass 31, count 0 2006.201.22:28:17.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.22:28:17.97#ibcon#[25=USB\r\n] 2006.201.22:28:17.97#ibcon#*before write, iclass 31, count 0 2006.201.22:28:17.97#ibcon#enter sib2, iclass 31, count 0 2006.201.22:28:17.97#ibcon#flushed, iclass 31, count 0 2006.201.22:28:17.97#ibcon#about to write, iclass 31, count 0 2006.201.22:28:17.97#ibcon#wrote, iclass 31, count 0 2006.201.22:28:17.97#ibcon#about to read 3, iclass 31, count 0 2006.201.22:28:18.00#ibcon#read 3, iclass 31, count 0 2006.201.22:28:18.00#ibcon#about to read 4, iclass 31, count 0 2006.201.22:28:18.00#ibcon#read 4, iclass 31, count 0 2006.201.22:28:18.00#ibcon#about to read 5, iclass 31, count 0 2006.201.22:28:18.00#ibcon#read 5, iclass 31, count 0 2006.201.22:28:18.00#ibcon#about to read 6, iclass 31, count 0 2006.201.22:28:18.00#ibcon#read 6, iclass 31, count 0 2006.201.22:28:18.00#ibcon#end of sib2, iclass 31, count 0 2006.201.22:28:18.00#ibcon#*after write, iclass 31, count 0 2006.201.22:28:18.00#ibcon#*before return 0, iclass 31, count 0 2006.201.22:28:18.00#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:18.00#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:18.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.22:28:18.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.22:28:18.00$vck44/valo=7,864.99 2006.201.22:28:18.00#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.22:28:18.00#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.22:28:18.00#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:18.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:18.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:18.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:18.00#ibcon#enter wrdev, iclass 33, count 0 2006.201.22:28:18.00#ibcon#first serial, iclass 33, count 0 2006.201.22:28:18.00#ibcon#enter sib2, iclass 33, count 0 2006.201.22:28:18.00#ibcon#flushed, iclass 33, count 0 2006.201.22:28:18.00#ibcon#about to write, iclass 33, count 0 2006.201.22:28:18.00#ibcon#wrote, iclass 33, count 0 2006.201.22:28:18.00#ibcon#about to read 3, iclass 33, count 0 2006.201.22:28:18.02#ibcon#read 3, iclass 33, count 0 2006.201.22:28:18.02#ibcon#about to read 4, iclass 33, count 0 2006.201.22:28:18.02#ibcon#read 4, iclass 33, count 0 2006.201.22:28:18.02#ibcon#about to read 5, iclass 33, count 0 2006.201.22:28:18.02#ibcon#read 5, iclass 33, count 0 2006.201.22:28:18.02#ibcon#about to read 6, iclass 33, count 0 2006.201.22:28:18.02#ibcon#read 6, iclass 33, count 0 2006.201.22:28:18.02#ibcon#end of sib2, iclass 33, count 0 2006.201.22:28:18.02#ibcon#*mode == 0, iclass 33, count 0 2006.201.22:28:18.02#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.22:28:18.02#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.22:28:18.02#ibcon#*before write, iclass 33, count 0 2006.201.22:28:18.02#ibcon#enter sib2, iclass 33, count 0 2006.201.22:28:18.02#ibcon#flushed, iclass 33, count 0 2006.201.22:28:18.02#ibcon#about to write, iclass 33, count 0 2006.201.22:28:18.02#ibcon#wrote, iclass 33, count 0 2006.201.22:28:18.02#ibcon#about to read 3, iclass 33, count 0 2006.201.22:28:18.07#ibcon#read 3, iclass 33, count 0 2006.201.22:28:18.07#ibcon#about to read 4, iclass 33, count 0 2006.201.22:28:18.07#ibcon#read 4, iclass 33, count 0 2006.201.22:28:18.07#ibcon#about to read 5, iclass 33, count 0 2006.201.22:28:18.07#ibcon#read 5, iclass 33, count 0 2006.201.22:28:18.07#ibcon#about to read 6, iclass 33, count 0 2006.201.22:28:18.07#ibcon#read 6, iclass 33, count 0 2006.201.22:28:18.07#ibcon#end of sib2, iclass 33, count 0 2006.201.22:28:18.07#ibcon#*after write, iclass 33, count 0 2006.201.22:28:18.07#ibcon#*before return 0, iclass 33, count 0 2006.201.22:28:18.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:18.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:18.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.22:28:18.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.22:28:18.07$vck44/va=7,5 2006.201.22:28:18.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.22:28:18.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.22:28:18.07#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:18.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:18.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:18.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:18.12#ibcon#enter wrdev, iclass 35, count 2 2006.201.22:28:18.12#ibcon#first serial, iclass 35, count 2 2006.201.22:28:18.12#ibcon#enter sib2, iclass 35, count 2 2006.201.22:28:18.12#ibcon#flushed, iclass 35, count 2 2006.201.22:28:18.12#ibcon#about to write, iclass 35, count 2 2006.201.22:28:18.12#ibcon#wrote, iclass 35, count 2 2006.201.22:28:18.12#ibcon#about to read 3, iclass 35, count 2 2006.201.22:28:18.14#ibcon#read 3, iclass 35, count 2 2006.201.22:28:18.14#ibcon#about to read 4, iclass 35, count 2 2006.201.22:28:18.14#ibcon#read 4, iclass 35, count 2 2006.201.22:28:18.14#ibcon#about to read 5, iclass 35, count 2 2006.201.22:28:18.14#ibcon#read 5, iclass 35, count 2 2006.201.22:28:18.14#ibcon#about to read 6, iclass 35, count 2 2006.201.22:28:18.14#ibcon#read 6, iclass 35, count 2 2006.201.22:28:18.14#ibcon#end of sib2, iclass 35, count 2 2006.201.22:28:18.14#ibcon#*mode == 0, iclass 35, count 2 2006.201.22:28:18.14#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.22:28:18.14#ibcon#[25=AT07-05\r\n] 2006.201.22:28:18.14#ibcon#*before write, iclass 35, count 2 2006.201.22:28:18.14#ibcon#enter sib2, iclass 35, count 2 2006.201.22:28:18.14#ibcon#flushed, iclass 35, count 2 2006.201.22:28:18.14#ibcon#about to write, iclass 35, count 2 2006.201.22:28:18.14#ibcon#wrote, iclass 35, count 2 2006.201.22:28:18.14#ibcon#about to read 3, iclass 35, count 2 2006.201.22:28:18.17#ibcon#read 3, iclass 35, count 2 2006.201.22:28:18.17#ibcon#about to read 4, iclass 35, count 2 2006.201.22:28:18.17#ibcon#read 4, iclass 35, count 2 2006.201.22:28:18.17#ibcon#about to read 5, iclass 35, count 2 2006.201.22:28:18.17#ibcon#read 5, iclass 35, count 2 2006.201.22:28:18.17#ibcon#about to read 6, iclass 35, count 2 2006.201.22:28:18.17#ibcon#read 6, iclass 35, count 2 2006.201.22:28:18.17#ibcon#end of sib2, iclass 35, count 2 2006.201.22:28:18.17#ibcon#*after write, iclass 35, count 2 2006.201.22:28:18.17#ibcon#*before return 0, iclass 35, count 2 2006.201.22:28:18.17#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:18.17#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:18.17#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.22:28:18.17#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:18.17#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:18.29#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:18.29#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:18.29#ibcon#enter wrdev, iclass 35, count 0 2006.201.22:28:18.29#ibcon#first serial, iclass 35, count 0 2006.201.22:28:18.29#ibcon#enter sib2, iclass 35, count 0 2006.201.22:28:18.29#ibcon#flushed, iclass 35, count 0 2006.201.22:28:18.29#ibcon#about to write, iclass 35, count 0 2006.201.22:28:18.29#ibcon#wrote, iclass 35, count 0 2006.201.22:28:18.29#ibcon#about to read 3, iclass 35, count 0 2006.201.22:28:18.31#ibcon#read 3, iclass 35, count 0 2006.201.22:28:18.31#ibcon#about to read 4, iclass 35, count 0 2006.201.22:28:18.31#ibcon#read 4, iclass 35, count 0 2006.201.22:28:18.31#ibcon#about to read 5, iclass 35, count 0 2006.201.22:28:18.31#ibcon#read 5, iclass 35, count 0 2006.201.22:28:18.31#ibcon#about to read 6, iclass 35, count 0 2006.201.22:28:18.31#ibcon#read 6, iclass 35, count 0 2006.201.22:28:18.31#ibcon#end of sib2, iclass 35, count 0 2006.201.22:28:18.31#ibcon#*mode == 0, iclass 35, count 0 2006.201.22:28:18.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.22:28:18.31#ibcon#[25=USB\r\n] 2006.201.22:28:18.31#ibcon#*before write, iclass 35, count 0 2006.201.22:28:18.31#ibcon#enter sib2, iclass 35, count 0 2006.201.22:28:18.31#ibcon#flushed, iclass 35, count 0 2006.201.22:28:18.31#ibcon#about to write, iclass 35, count 0 2006.201.22:28:18.31#ibcon#wrote, iclass 35, count 0 2006.201.22:28:18.31#ibcon#about to read 3, iclass 35, count 0 2006.201.22:28:18.34#ibcon#read 3, iclass 35, count 0 2006.201.22:28:18.34#ibcon#about to read 4, iclass 35, count 0 2006.201.22:28:18.34#ibcon#read 4, iclass 35, count 0 2006.201.22:28:18.34#ibcon#about to read 5, iclass 35, count 0 2006.201.22:28:18.34#ibcon#read 5, iclass 35, count 0 2006.201.22:28:18.34#ibcon#about to read 6, iclass 35, count 0 2006.201.22:28:18.34#ibcon#read 6, iclass 35, count 0 2006.201.22:28:18.34#ibcon#end of sib2, iclass 35, count 0 2006.201.22:28:18.34#ibcon#*after write, iclass 35, count 0 2006.201.22:28:18.34#ibcon#*before return 0, iclass 35, count 0 2006.201.22:28:18.34#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:18.34#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:18.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.22:28:18.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.22:28:18.34$vck44/valo=8,884.99 2006.201.22:28:18.34#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.22:28:18.34#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.22:28:18.34#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:18.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:18.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:18.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:18.34#ibcon#enter wrdev, iclass 37, count 0 2006.201.22:28:18.34#ibcon#first serial, iclass 37, count 0 2006.201.22:28:18.34#ibcon#enter sib2, iclass 37, count 0 2006.201.22:28:18.34#ibcon#flushed, iclass 37, count 0 2006.201.22:28:18.34#ibcon#about to write, iclass 37, count 0 2006.201.22:28:18.34#ibcon#wrote, iclass 37, count 0 2006.201.22:28:18.34#ibcon#about to read 3, iclass 37, count 0 2006.201.22:28:18.36#ibcon#read 3, iclass 37, count 0 2006.201.22:28:18.36#ibcon#about to read 4, iclass 37, count 0 2006.201.22:28:18.36#ibcon#read 4, iclass 37, count 0 2006.201.22:28:18.36#ibcon#about to read 5, iclass 37, count 0 2006.201.22:28:18.36#ibcon#read 5, iclass 37, count 0 2006.201.22:28:18.36#ibcon#about to read 6, iclass 37, count 0 2006.201.22:28:18.36#ibcon#read 6, iclass 37, count 0 2006.201.22:28:18.36#ibcon#end of sib2, iclass 37, count 0 2006.201.22:28:18.36#ibcon#*mode == 0, iclass 37, count 0 2006.201.22:28:18.36#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.22:28:18.36#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.22:28:18.36#ibcon#*before write, iclass 37, count 0 2006.201.22:28:18.36#ibcon#enter sib2, iclass 37, count 0 2006.201.22:28:18.36#ibcon#flushed, iclass 37, count 0 2006.201.22:28:18.36#ibcon#about to write, iclass 37, count 0 2006.201.22:28:18.36#ibcon#wrote, iclass 37, count 0 2006.201.22:28:18.36#ibcon#about to read 3, iclass 37, count 0 2006.201.22:28:18.40#ibcon#read 3, iclass 37, count 0 2006.201.22:28:18.40#ibcon#about to read 4, iclass 37, count 0 2006.201.22:28:18.40#ibcon#read 4, iclass 37, count 0 2006.201.22:28:18.40#ibcon#about to read 5, iclass 37, count 0 2006.201.22:28:18.40#ibcon#read 5, iclass 37, count 0 2006.201.22:28:18.40#ibcon#about to read 6, iclass 37, count 0 2006.201.22:28:18.40#ibcon#read 6, iclass 37, count 0 2006.201.22:28:18.40#ibcon#end of sib2, iclass 37, count 0 2006.201.22:28:18.40#ibcon#*after write, iclass 37, count 0 2006.201.22:28:18.40#ibcon#*before return 0, iclass 37, count 0 2006.201.22:28:18.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:18.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:18.40#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.22:28:18.40#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.22:28:18.40$vck44/va=8,4 2006.201.22:28:18.40#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.22:28:18.40#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.22:28:18.40#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:18.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:28:18.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:28:18.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:28:18.46#ibcon#enter wrdev, iclass 39, count 2 2006.201.22:28:18.46#ibcon#first serial, iclass 39, count 2 2006.201.22:28:18.46#ibcon#enter sib2, iclass 39, count 2 2006.201.22:28:18.46#ibcon#flushed, iclass 39, count 2 2006.201.22:28:18.46#ibcon#about to write, iclass 39, count 2 2006.201.22:28:18.46#ibcon#wrote, iclass 39, count 2 2006.201.22:28:18.46#ibcon#about to read 3, iclass 39, count 2 2006.201.22:28:18.48#ibcon#read 3, iclass 39, count 2 2006.201.22:28:18.48#ibcon#about to read 4, iclass 39, count 2 2006.201.22:28:18.48#ibcon#read 4, iclass 39, count 2 2006.201.22:28:18.48#ibcon#about to read 5, iclass 39, count 2 2006.201.22:28:18.48#ibcon#read 5, iclass 39, count 2 2006.201.22:28:18.48#ibcon#about to read 6, iclass 39, count 2 2006.201.22:28:18.48#ibcon#read 6, iclass 39, count 2 2006.201.22:28:18.48#ibcon#end of sib2, iclass 39, count 2 2006.201.22:28:18.48#ibcon#*mode == 0, iclass 39, count 2 2006.201.22:28:18.48#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.22:28:18.48#ibcon#[25=AT08-04\r\n] 2006.201.22:28:18.48#ibcon#*before write, iclass 39, count 2 2006.201.22:28:18.48#ibcon#enter sib2, iclass 39, count 2 2006.201.22:28:18.48#ibcon#flushed, iclass 39, count 2 2006.201.22:28:18.48#ibcon#about to write, iclass 39, count 2 2006.201.22:28:18.48#ibcon#wrote, iclass 39, count 2 2006.201.22:28:18.48#ibcon#about to read 3, iclass 39, count 2 2006.201.22:28:18.51#ibcon#read 3, iclass 39, count 2 2006.201.22:28:18.51#ibcon#about to read 4, iclass 39, count 2 2006.201.22:28:18.51#ibcon#read 4, iclass 39, count 2 2006.201.22:28:18.51#ibcon#about to read 5, iclass 39, count 2 2006.201.22:28:18.51#ibcon#read 5, iclass 39, count 2 2006.201.22:28:18.51#ibcon#about to read 6, iclass 39, count 2 2006.201.22:28:18.51#ibcon#read 6, iclass 39, count 2 2006.201.22:28:18.51#ibcon#end of sib2, iclass 39, count 2 2006.201.22:28:18.51#ibcon#*after write, iclass 39, count 2 2006.201.22:28:18.51#ibcon#*before return 0, iclass 39, count 2 2006.201.22:28:18.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:28:18.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:28:18.51#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.22:28:18.51#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:18.51#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:28:18.63#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:28:18.63#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:28:18.63#ibcon#enter wrdev, iclass 39, count 0 2006.201.22:28:18.63#ibcon#first serial, iclass 39, count 0 2006.201.22:28:18.63#ibcon#enter sib2, iclass 39, count 0 2006.201.22:28:18.63#ibcon#flushed, iclass 39, count 0 2006.201.22:28:18.63#ibcon#about to write, iclass 39, count 0 2006.201.22:28:18.63#ibcon#wrote, iclass 39, count 0 2006.201.22:28:18.63#ibcon#about to read 3, iclass 39, count 0 2006.201.22:28:18.65#ibcon#read 3, iclass 39, count 0 2006.201.22:28:18.65#ibcon#about to read 4, iclass 39, count 0 2006.201.22:28:18.65#ibcon#read 4, iclass 39, count 0 2006.201.22:28:18.65#ibcon#about to read 5, iclass 39, count 0 2006.201.22:28:18.65#ibcon#read 5, iclass 39, count 0 2006.201.22:28:18.65#ibcon#about to read 6, iclass 39, count 0 2006.201.22:28:18.65#ibcon#read 6, iclass 39, count 0 2006.201.22:28:18.65#ibcon#end of sib2, iclass 39, count 0 2006.201.22:28:18.65#ibcon#*mode == 0, iclass 39, count 0 2006.201.22:28:18.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.22:28:18.65#ibcon#[25=USB\r\n] 2006.201.22:28:18.65#ibcon#*before write, iclass 39, count 0 2006.201.22:28:18.65#ibcon#enter sib2, iclass 39, count 0 2006.201.22:28:18.65#ibcon#flushed, iclass 39, count 0 2006.201.22:28:18.65#ibcon#about to write, iclass 39, count 0 2006.201.22:28:18.65#ibcon#wrote, iclass 39, count 0 2006.201.22:28:18.65#ibcon#about to read 3, iclass 39, count 0 2006.201.22:28:18.68#ibcon#read 3, iclass 39, count 0 2006.201.22:28:18.68#ibcon#about to read 4, iclass 39, count 0 2006.201.22:28:18.68#ibcon#read 4, iclass 39, count 0 2006.201.22:28:18.68#ibcon#about to read 5, iclass 39, count 0 2006.201.22:28:18.68#ibcon#read 5, iclass 39, count 0 2006.201.22:28:18.68#ibcon#about to read 6, iclass 39, count 0 2006.201.22:28:18.68#ibcon#read 6, iclass 39, count 0 2006.201.22:28:18.68#ibcon#end of sib2, iclass 39, count 0 2006.201.22:28:18.68#ibcon#*after write, iclass 39, count 0 2006.201.22:28:18.68#ibcon#*before return 0, iclass 39, count 0 2006.201.22:28:18.68#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:28:18.68#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:28:18.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.22:28:18.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.22:28:18.68$vck44/vblo=1,629.99 2006.201.22:28:18.68#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.22:28:18.68#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.22:28:18.68#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:18.68#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:18.68#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:18.68#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:18.68#ibcon#enter wrdev, iclass 2, count 0 2006.201.22:28:18.68#ibcon#first serial, iclass 2, count 0 2006.201.22:28:18.68#ibcon#enter sib2, iclass 2, count 0 2006.201.22:28:18.68#ibcon#flushed, iclass 2, count 0 2006.201.22:28:18.68#ibcon#about to write, iclass 2, count 0 2006.201.22:28:18.68#ibcon#wrote, iclass 2, count 0 2006.201.22:28:18.68#ibcon#about to read 3, iclass 2, count 0 2006.201.22:28:18.70#ibcon#read 3, iclass 2, count 0 2006.201.22:28:18.70#ibcon#about to read 4, iclass 2, count 0 2006.201.22:28:18.70#ibcon#read 4, iclass 2, count 0 2006.201.22:28:18.70#ibcon#about to read 5, iclass 2, count 0 2006.201.22:28:18.70#ibcon#read 5, iclass 2, count 0 2006.201.22:28:18.70#ibcon#about to read 6, iclass 2, count 0 2006.201.22:28:18.70#ibcon#read 6, iclass 2, count 0 2006.201.22:28:18.70#ibcon#end of sib2, iclass 2, count 0 2006.201.22:28:18.70#ibcon#*mode == 0, iclass 2, count 0 2006.201.22:28:18.70#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.22:28:18.70#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.22:28:18.70#ibcon#*before write, iclass 2, count 0 2006.201.22:28:18.70#ibcon#enter sib2, iclass 2, count 0 2006.201.22:28:18.70#ibcon#flushed, iclass 2, count 0 2006.201.22:28:18.70#ibcon#about to write, iclass 2, count 0 2006.201.22:28:18.70#ibcon#wrote, iclass 2, count 0 2006.201.22:28:18.70#ibcon#about to read 3, iclass 2, count 0 2006.201.22:28:18.75#ibcon#read 3, iclass 2, count 0 2006.201.22:28:18.75#ibcon#about to read 4, iclass 2, count 0 2006.201.22:28:18.75#ibcon#read 4, iclass 2, count 0 2006.201.22:28:18.75#ibcon#about to read 5, iclass 2, count 0 2006.201.22:28:18.75#ibcon#read 5, iclass 2, count 0 2006.201.22:28:18.75#ibcon#about to read 6, iclass 2, count 0 2006.201.22:28:18.75#ibcon#read 6, iclass 2, count 0 2006.201.22:28:18.75#ibcon#end of sib2, iclass 2, count 0 2006.201.22:28:18.75#ibcon#*after write, iclass 2, count 0 2006.201.22:28:18.75#ibcon#*before return 0, iclass 2, count 0 2006.201.22:28:18.75#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:18.75#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:28:18.75#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.22:28:18.75#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.22:28:18.75$vck44/vb=1,4 2006.201.22:28:18.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.22:28:18.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.22:28:18.75#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:18.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:18.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:18.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:18.75#ibcon#enter wrdev, iclass 5, count 2 2006.201.22:28:18.75#ibcon#first serial, iclass 5, count 2 2006.201.22:28:18.75#ibcon#enter sib2, iclass 5, count 2 2006.201.22:28:18.75#ibcon#flushed, iclass 5, count 2 2006.201.22:28:18.75#ibcon#about to write, iclass 5, count 2 2006.201.22:28:18.75#ibcon#wrote, iclass 5, count 2 2006.201.22:28:18.75#ibcon#about to read 3, iclass 5, count 2 2006.201.22:28:18.77#ibcon#read 3, iclass 5, count 2 2006.201.22:28:18.77#ibcon#about to read 4, iclass 5, count 2 2006.201.22:28:18.77#ibcon#read 4, iclass 5, count 2 2006.201.22:28:18.77#ibcon#about to read 5, iclass 5, count 2 2006.201.22:28:18.77#ibcon#read 5, iclass 5, count 2 2006.201.22:28:18.77#ibcon#about to read 6, iclass 5, count 2 2006.201.22:28:18.77#ibcon#read 6, iclass 5, count 2 2006.201.22:28:18.77#ibcon#end of sib2, iclass 5, count 2 2006.201.22:28:18.77#ibcon#*mode == 0, iclass 5, count 2 2006.201.22:28:18.77#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.22:28:18.77#ibcon#[27=AT01-04\r\n] 2006.201.22:28:18.77#ibcon#*before write, iclass 5, count 2 2006.201.22:28:18.77#ibcon#enter sib2, iclass 5, count 2 2006.201.22:28:18.77#ibcon#flushed, iclass 5, count 2 2006.201.22:28:18.77#ibcon#about to write, iclass 5, count 2 2006.201.22:28:18.77#ibcon#wrote, iclass 5, count 2 2006.201.22:28:18.77#ibcon#about to read 3, iclass 5, count 2 2006.201.22:28:18.80#ibcon#read 3, iclass 5, count 2 2006.201.22:28:18.80#ibcon#about to read 4, iclass 5, count 2 2006.201.22:28:18.80#ibcon#read 4, iclass 5, count 2 2006.201.22:28:18.80#ibcon#about to read 5, iclass 5, count 2 2006.201.22:28:18.80#ibcon#read 5, iclass 5, count 2 2006.201.22:28:18.80#ibcon#about to read 6, iclass 5, count 2 2006.201.22:28:18.80#ibcon#read 6, iclass 5, count 2 2006.201.22:28:18.80#ibcon#end of sib2, iclass 5, count 2 2006.201.22:28:18.80#ibcon#*after write, iclass 5, count 2 2006.201.22:28:18.80#ibcon#*before return 0, iclass 5, count 2 2006.201.22:28:18.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:18.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:28:18.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.22:28:18.80#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:18.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:18.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:18.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:18.92#ibcon#enter wrdev, iclass 5, count 0 2006.201.22:28:18.92#ibcon#first serial, iclass 5, count 0 2006.201.22:28:18.92#ibcon#enter sib2, iclass 5, count 0 2006.201.22:28:18.92#ibcon#flushed, iclass 5, count 0 2006.201.22:28:18.92#ibcon#about to write, iclass 5, count 0 2006.201.22:28:18.92#ibcon#wrote, iclass 5, count 0 2006.201.22:28:18.92#ibcon#about to read 3, iclass 5, count 0 2006.201.22:28:18.94#ibcon#read 3, iclass 5, count 0 2006.201.22:28:18.94#ibcon#about to read 4, iclass 5, count 0 2006.201.22:28:18.94#ibcon#read 4, iclass 5, count 0 2006.201.22:28:18.94#ibcon#about to read 5, iclass 5, count 0 2006.201.22:28:18.94#ibcon#read 5, iclass 5, count 0 2006.201.22:28:18.94#ibcon#about to read 6, iclass 5, count 0 2006.201.22:28:18.94#ibcon#read 6, iclass 5, count 0 2006.201.22:28:18.94#ibcon#end of sib2, iclass 5, count 0 2006.201.22:28:18.94#ibcon#*mode == 0, iclass 5, count 0 2006.201.22:28:18.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.22:28:18.94#ibcon#[27=USB\r\n] 2006.201.22:28:18.94#ibcon#*before write, iclass 5, count 0 2006.201.22:28:18.94#ibcon#enter sib2, iclass 5, count 0 2006.201.22:28:18.94#ibcon#flushed, iclass 5, count 0 2006.201.22:28:18.94#ibcon#about to write, iclass 5, count 0 2006.201.22:28:18.94#ibcon#wrote, iclass 5, count 0 2006.201.22:28:18.94#ibcon#about to read 3, iclass 5, count 0 2006.201.22:28:18.97#ibcon#read 3, iclass 5, count 0 2006.201.22:28:18.97#ibcon#about to read 4, iclass 5, count 0 2006.201.22:28:18.97#ibcon#read 4, iclass 5, count 0 2006.201.22:28:18.97#ibcon#about to read 5, iclass 5, count 0 2006.201.22:28:18.97#ibcon#read 5, iclass 5, count 0 2006.201.22:28:18.97#ibcon#about to read 6, iclass 5, count 0 2006.201.22:28:18.97#ibcon#read 6, iclass 5, count 0 2006.201.22:28:18.97#ibcon#end of sib2, iclass 5, count 0 2006.201.22:28:18.97#ibcon#*after write, iclass 5, count 0 2006.201.22:28:18.97#ibcon#*before return 0, iclass 5, count 0 2006.201.22:28:18.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:18.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:28:18.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.22:28:18.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.22:28:18.97$vck44/vblo=2,634.99 2006.201.22:28:18.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.22:28:18.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.22:28:18.97#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:18.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:28:18.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:28:18.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:28:18.97#ibcon#enter wrdev, iclass 7, count 0 2006.201.22:28:18.97#ibcon#first serial, iclass 7, count 0 2006.201.22:28:18.97#ibcon#enter sib2, iclass 7, count 0 2006.201.22:28:18.97#ibcon#flushed, iclass 7, count 0 2006.201.22:28:18.97#ibcon#about to write, iclass 7, count 0 2006.201.22:28:18.97#ibcon#wrote, iclass 7, count 0 2006.201.22:28:18.97#ibcon#about to read 3, iclass 7, count 0 2006.201.22:28:18.99#ibcon#read 3, iclass 7, count 0 2006.201.22:28:18.99#ibcon#about to read 4, iclass 7, count 0 2006.201.22:28:18.99#ibcon#read 4, iclass 7, count 0 2006.201.22:28:18.99#ibcon#about to read 5, iclass 7, count 0 2006.201.22:28:18.99#ibcon#read 5, iclass 7, count 0 2006.201.22:28:18.99#ibcon#about to read 6, iclass 7, count 0 2006.201.22:28:18.99#ibcon#read 6, iclass 7, count 0 2006.201.22:28:18.99#ibcon#end of sib2, iclass 7, count 0 2006.201.22:28:18.99#ibcon#*mode == 0, iclass 7, count 0 2006.201.22:28:18.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.22:28:18.99#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.22:28:18.99#ibcon#*before write, iclass 7, count 0 2006.201.22:28:18.99#ibcon#enter sib2, iclass 7, count 0 2006.201.22:28:18.99#ibcon#flushed, iclass 7, count 0 2006.201.22:28:18.99#ibcon#about to write, iclass 7, count 0 2006.201.22:28:18.99#ibcon#wrote, iclass 7, count 0 2006.201.22:28:18.99#ibcon#about to read 3, iclass 7, count 0 2006.201.22:28:19.03#ibcon#read 3, iclass 7, count 0 2006.201.22:28:19.03#ibcon#about to read 4, iclass 7, count 0 2006.201.22:28:19.03#ibcon#read 4, iclass 7, count 0 2006.201.22:28:19.03#ibcon#about to read 5, iclass 7, count 0 2006.201.22:28:19.03#ibcon#read 5, iclass 7, count 0 2006.201.22:28:19.03#ibcon#about to read 6, iclass 7, count 0 2006.201.22:28:19.03#ibcon#read 6, iclass 7, count 0 2006.201.22:28:19.03#ibcon#end of sib2, iclass 7, count 0 2006.201.22:28:19.03#ibcon#*after write, iclass 7, count 0 2006.201.22:28:19.03#ibcon#*before return 0, iclass 7, count 0 2006.201.22:28:19.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:28:19.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:28:19.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.22:28:19.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.22:28:19.03$vck44/vb=2,5 2006.201.22:28:19.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.22:28:19.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.22:28:19.03#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:19.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:28:19.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:28:19.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:28:19.09#ibcon#enter wrdev, iclass 11, count 2 2006.201.22:28:19.09#ibcon#first serial, iclass 11, count 2 2006.201.22:28:19.09#ibcon#enter sib2, iclass 11, count 2 2006.201.22:28:19.09#ibcon#flushed, iclass 11, count 2 2006.201.22:28:19.09#ibcon#about to write, iclass 11, count 2 2006.201.22:28:19.09#ibcon#wrote, iclass 11, count 2 2006.201.22:28:19.09#ibcon#about to read 3, iclass 11, count 2 2006.201.22:28:19.11#ibcon#read 3, iclass 11, count 2 2006.201.22:28:19.11#ibcon#about to read 4, iclass 11, count 2 2006.201.22:28:19.11#ibcon#read 4, iclass 11, count 2 2006.201.22:28:19.11#ibcon#about to read 5, iclass 11, count 2 2006.201.22:28:19.11#ibcon#read 5, iclass 11, count 2 2006.201.22:28:19.11#ibcon#about to read 6, iclass 11, count 2 2006.201.22:28:19.11#ibcon#read 6, iclass 11, count 2 2006.201.22:28:19.11#ibcon#end of sib2, iclass 11, count 2 2006.201.22:28:19.11#ibcon#*mode == 0, iclass 11, count 2 2006.201.22:28:19.11#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.22:28:19.11#ibcon#[27=AT02-05\r\n] 2006.201.22:28:19.11#ibcon#*before write, iclass 11, count 2 2006.201.22:28:19.11#ibcon#enter sib2, iclass 11, count 2 2006.201.22:28:19.11#ibcon#flushed, iclass 11, count 2 2006.201.22:28:19.11#ibcon#about to write, iclass 11, count 2 2006.201.22:28:19.11#ibcon#wrote, iclass 11, count 2 2006.201.22:28:19.11#ibcon#about to read 3, iclass 11, count 2 2006.201.22:28:19.14#ibcon#read 3, iclass 11, count 2 2006.201.22:28:19.14#ibcon#about to read 4, iclass 11, count 2 2006.201.22:28:19.14#ibcon#read 4, iclass 11, count 2 2006.201.22:28:19.14#ibcon#about to read 5, iclass 11, count 2 2006.201.22:28:19.14#ibcon#read 5, iclass 11, count 2 2006.201.22:28:19.14#ibcon#about to read 6, iclass 11, count 2 2006.201.22:28:19.14#ibcon#read 6, iclass 11, count 2 2006.201.22:28:19.14#ibcon#end of sib2, iclass 11, count 2 2006.201.22:28:19.14#ibcon#*after write, iclass 11, count 2 2006.201.22:28:19.14#ibcon#*before return 0, iclass 11, count 2 2006.201.22:28:19.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:28:19.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:28:19.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.22:28:19.14#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:19.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:28:19.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:28:19.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:28:19.26#ibcon#enter wrdev, iclass 11, count 0 2006.201.22:28:19.26#ibcon#first serial, iclass 11, count 0 2006.201.22:28:19.26#ibcon#enter sib2, iclass 11, count 0 2006.201.22:28:19.26#ibcon#flushed, iclass 11, count 0 2006.201.22:28:19.26#ibcon#about to write, iclass 11, count 0 2006.201.22:28:19.26#ibcon#wrote, iclass 11, count 0 2006.201.22:28:19.26#ibcon#about to read 3, iclass 11, count 0 2006.201.22:28:19.28#ibcon#read 3, iclass 11, count 0 2006.201.22:28:19.28#ibcon#about to read 4, iclass 11, count 0 2006.201.22:28:19.28#ibcon#read 4, iclass 11, count 0 2006.201.22:28:19.28#ibcon#about to read 5, iclass 11, count 0 2006.201.22:28:19.28#ibcon#read 5, iclass 11, count 0 2006.201.22:28:19.28#ibcon#about to read 6, iclass 11, count 0 2006.201.22:28:19.28#ibcon#read 6, iclass 11, count 0 2006.201.22:28:19.28#ibcon#end of sib2, iclass 11, count 0 2006.201.22:28:19.28#ibcon#*mode == 0, iclass 11, count 0 2006.201.22:28:19.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.22:28:19.28#ibcon#[27=USB\r\n] 2006.201.22:28:19.28#ibcon#*before write, iclass 11, count 0 2006.201.22:28:19.28#ibcon#enter sib2, iclass 11, count 0 2006.201.22:28:19.28#ibcon#flushed, iclass 11, count 0 2006.201.22:28:19.28#ibcon#about to write, iclass 11, count 0 2006.201.22:28:19.28#ibcon#wrote, iclass 11, count 0 2006.201.22:28:19.28#ibcon#about to read 3, iclass 11, count 0 2006.201.22:28:19.31#ibcon#read 3, iclass 11, count 0 2006.201.22:28:19.31#ibcon#about to read 4, iclass 11, count 0 2006.201.22:28:19.31#ibcon#read 4, iclass 11, count 0 2006.201.22:28:19.31#ibcon#about to read 5, iclass 11, count 0 2006.201.22:28:19.31#ibcon#read 5, iclass 11, count 0 2006.201.22:28:19.31#ibcon#about to read 6, iclass 11, count 0 2006.201.22:28:19.31#ibcon#read 6, iclass 11, count 0 2006.201.22:28:19.31#ibcon#end of sib2, iclass 11, count 0 2006.201.22:28:19.31#ibcon#*after write, iclass 11, count 0 2006.201.22:28:19.31#ibcon#*before return 0, iclass 11, count 0 2006.201.22:28:19.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:28:19.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:28:19.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.22:28:19.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.22:28:19.31$vck44/vblo=3,649.99 2006.201.22:28:19.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.22:28:19.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.22:28:19.31#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:19.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:19.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:19.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:19.31#ibcon#enter wrdev, iclass 13, count 0 2006.201.22:28:19.31#ibcon#first serial, iclass 13, count 0 2006.201.22:28:19.31#ibcon#enter sib2, iclass 13, count 0 2006.201.22:28:19.31#ibcon#flushed, iclass 13, count 0 2006.201.22:28:19.31#ibcon#about to write, iclass 13, count 0 2006.201.22:28:19.31#ibcon#wrote, iclass 13, count 0 2006.201.22:28:19.31#ibcon#about to read 3, iclass 13, count 0 2006.201.22:28:19.33#ibcon#read 3, iclass 13, count 0 2006.201.22:28:19.33#ibcon#about to read 4, iclass 13, count 0 2006.201.22:28:19.33#ibcon#read 4, iclass 13, count 0 2006.201.22:28:19.33#ibcon#about to read 5, iclass 13, count 0 2006.201.22:28:19.33#ibcon#read 5, iclass 13, count 0 2006.201.22:28:19.33#ibcon#about to read 6, iclass 13, count 0 2006.201.22:28:19.33#ibcon#read 6, iclass 13, count 0 2006.201.22:28:19.33#ibcon#end of sib2, iclass 13, count 0 2006.201.22:28:19.33#ibcon#*mode == 0, iclass 13, count 0 2006.201.22:28:19.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.22:28:19.33#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.22:28:19.33#ibcon#*before write, iclass 13, count 0 2006.201.22:28:19.33#ibcon#enter sib2, iclass 13, count 0 2006.201.22:28:19.33#ibcon#flushed, iclass 13, count 0 2006.201.22:28:19.33#ibcon#about to write, iclass 13, count 0 2006.201.22:28:19.33#ibcon#wrote, iclass 13, count 0 2006.201.22:28:19.33#ibcon#about to read 3, iclass 13, count 0 2006.201.22:28:19.37#ibcon#read 3, iclass 13, count 0 2006.201.22:28:19.37#ibcon#about to read 4, iclass 13, count 0 2006.201.22:28:19.37#ibcon#read 4, iclass 13, count 0 2006.201.22:28:19.37#ibcon#about to read 5, iclass 13, count 0 2006.201.22:28:19.37#ibcon#read 5, iclass 13, count 0 2006.201.22:28:19.37#ibcon#about to read 6, iclass 13, count 0 2006.201.22:28:19.37#ibcon#read 6, iclass 13, count 0 2006.201.22:28:19.37#ibcon#end of sib2, iclass 13, count 0 2006.201.22:28:19.37#ibcon#*after write, iclass 13, count 0 2006.201.22:28:19.37#ibcon#*before return 0, iclass 13, count 0 2006.201.22:28:19.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:19.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:28:19.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.22:28:19.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.22:28:19.37$vck44/vb=3,4 2006.201.22:28:19.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.22:28:19.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.22:28:19.37#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:19.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:19.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:19.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:19.43#ibcon#enter wrdev, iclass 15, count 2 2006.201.22:28:19.43#ibcon#first serial, iclass 15, count 2 2006.201.22:28:19.43#ibcon#enter sib2, iclass 15, count 2 2006.201.22:28:19.43#ibcon#flushed, iclass 15, count 2 2006.201.22:28:19.43#ibcon#about to write, iclass 15, count 2 2006.201.22:28:19.43#ibcon#wrote, iclass 15, count 2 2006.201.22:28:19.43#ibcon#about to read 3, iclass 15, count 2 2006.201.22:28:19.45#ibcon#read 3, iclass 15, count 2 2006.201.22:28:19.45#ibcon#about to read 4, iclass 15, count 2 2006.201.22:28:19.45#ibcon#read 4, iclass 15, count 2 2006.201.22:28:19.45#ibcon#about to read 5, iclass 15, count 2 2006.201.22:28:19.45#ibcon#read 5, iclass 15, count 2 2006.201.22:28:19.45#ibcon#about to read 6, iclass 15, count 2 2006.201.22:28:19.45#ibcon#read 6, iclass 15, count 2 2006.201.22:28:19.45#ibcon#end of sib2, iclass 15, count 2 2006.201.22:28:19.45#ibcon#*mode == 0, iclass 15, count 2 2006.201.22:28:19.45#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.22:28:19.45#ibcon#[27=AT03-04\r\n] 2006.201.22:28:19.45#ibcon#*before write, iclass 15, count 2 2006.201.22:28:19.45#ibcon#enter sib2, iclass 15, count 2 2006.201.22:28:19.45#ibcon#flushed, iclass 15, count 2 2006.201.22:28:19.45#ibcon#about to write, iclass 15, count 2 2006.201.22:28:19.45#ibcon#wrote, iclass 15, count 2 2006.201.22:28:19.45#ibcon#about to read 3, iclass 15, count 2 2006.201.22:28:19.48#ibcon#read 3, iclass 15, count 2 2006.201.22:28:19.48#ibcon#about to read 4, iclass 15, count 2 2006.201.22:28:19.48#ibcon#read 4, iclass 15, count 2 2006.201.22:28:19.48#ibcon#about to read 5, iclass 15, count 2 2006.201.22:28:19.48#ibcon#read 5, iclass 15, count 2 2006.201.22:28:19.48#ibcon#about to read 6, iclass 15, count 2 2006.201.22:28:19.48#ibcon#read 6, iclass 15, count 2 2006.201.22:28:19.48#ibcon#end of sib2, iclass 15, count 2 2006.201.22:28:19.48#ibcon#*after write, iclass 15, count 2 2006.201.22:28:19.48#ibcon#*before return 0, iclass 15, count 2 2006.201.22:28:19.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:19.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:28:19.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.22:28:19.48#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:19.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:19.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:19.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:19.60#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:28:19.60#ibcon#first serial, iclass 15, count 0 2006.201.22:28:19.60#ibcon#enter sib2, iclass 15, count 0 2006.201.22:28:19.60#ibcon#flushed, iclass 15, count 0 2006.201.22:28:19.60#ibcon#about to write, iclass 15, count 0 2006.201.22:28:19.60#ibcon#wrote, iclass 15, count 0 2006.201.22:28:19.60#ibcon#about to read 3, iclass 15, count 0 2006.201.22:28:19.62#ibcon#read 3, iclass 15, count 0 2006.201.22:28:19.62#ibcon#about to read 4, iclass 15, count 0 2006.201.22:28:19.62#ibcon#read 4, iclass 15, count 0 2006.201.22:28:19.62#ibcon#about to read 5, iclass 15, count 0 2006.201.22:28:19.62#ibcon#read 5, iclass 15, count 0 2006.201.22:28:19.62#ibcon#about to read 6, iclass 15, count 0 2006.201.22:28:19.62#ibcon#read 6, iclass 15, count 0 2006.201.22:28:19.62#ibcon#end of sib2, iclass 15, count 0 2006.201.22:28:19.62#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:28:19.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:28:19.62#ibcon#[27=USB\r\n] 2006.201.22:28:19.62#ibcon#*before write, iclass 15, count 0 2006.201.22:28:19.62#ibcon#enter sib2, iclass 15, count 0 2006.201.22:28:19.62#ibcon#flushed, iclass 15, count 0 2006.201.22:28:19.62#ibcon#about to write, iclass 15, count 0 2006.201.22:28:19.62#ibcon#wrote, iclass 15, count 0 2006.201.22:28:19.62#ibcon#about to read 3, iclass 15, count 0 2006.201.22:28:19.65#ibcon#read 3, iclass 15, count 0 2006.201.22:28:19.65#ibcon#about to read 4, iclass 15, count 0 2006.201.22:28:19.65#ibcon#read 4, iclass 15, count 0 2006.201.22:28:19.65#ibcon#about to read 5, iclass 15, count 0 2006.201.22:28:19.65#ibcon#read 5, iclass 15, count 0 2006.201.22:28:19.65#ibcon#about to read 6, iclass 15, count 0 2006.201.22:28:19.65#ibcon#read 6, iclass 15, count 0 2006.201.22:28:19.65#ibcon#end of sib2, iclass 15, count 0 2006.201.22:28:19.65#ibcon#*after write, iclass 15, count 0 2006.201.22:28:19.65#ibcon#*before return 0, iclass 15, count 0 2006.201.22:28:19.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:19.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:28:19.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:28:19.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:28:19.65$vck44/vblo=4,679.99 2006.201.22:28:19.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.22:28:19.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.22:28:19.65#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:19.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:19.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:19.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:19.65#ibcon#enter wrdev, iclass 17, count 0 2006.201.22:28:19.65#ibcon#first serial, iclass 17, count 0 2006.201.22:28:19.65#ibcon#enter sib2, iclass 17, count 0 2006.201.22:28:19.65#ibcon#flushed, iclass 17, count 0 2006.201.22:28:19.65#ibcon#about to write, iclass 17, count 0 2006.201.22:28:19.65#ibcon#wrote, iclass 17, count 0 2006.201.22:28:19.65#ibcon#about to read 3, iclass 17, count 0 2006.201.22:28:19.67#ibcon#read 3, iclass 17, count 0 2006.201.22:28:19.67#ibcon#about to read 4, iclass 17, count 0 2006.201.22:28:19.67#ibcon#read 4, iclass 17, count 0 2006.201.22:28:19.67#ibcon#about to read 5, iclass 17, count 0 2006.201.22:28:19.67#ibcon#read 5, iclass 17, count 0 2006.201.22:28:19.67#ibcon#about to read 6, iclass 17, count 0 2006.201.22:28:19.67#ibcon#read 6, iclass 17, count 0 2006.201.22:28:19.67#ibcon#end of sib2, iclass 17, count 0 2006.201.22:28:19.67#ibcon#*mode == 0, iclass 17, count 0 2006.201.22:28:19.67#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.22:28:19.67#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.22:28:19.67#ibcon#*before write, iclass 17, count 0 2006.201.22:28:19.67#ibcon#enter sib2, iclass 17, count 0 2006.201.22:28:19.67#ibcon#flushed, iclass 17, count 0 2006.201.22:28:19.67#ibcon#about to write, iclass 17, count 0 2006.201.22:28:19.67#ibcon#wrote, iclass 17, count 0 2006.201.22:28:19.67#ibcon#about to read 3, iclass 17, count 0 2006.201.22:28:19.72#ibcon#read 3, iclass 17, count 0 2006.201.22:28:19.72#ibcon#about to read 4, iclass 17, count 0 2006.201.22:28:19.72#ibcon#read 4, iclass 17, count 0 2006.201.22:28:19.72#ibcon#about to read 5, iclass 17, count 0 2006.201.22:28:19.72#ibcon#read 5, iclass 17, count 0 2006.201.22:28:19.72#ibcon#about to read 6, iclass 17, count 0 2006.201.22:28:19.72#ibcon#read 6, iclass 17, count 0 2006.201.22:28:19.72#ibcon#end of sib2, iclass 17, count 0 2006.201.22:28:19.72#ibcon#*after write, iclass 17, count 0 2006.201.22:28:19.72#ibcon#*before return 0, iclass 17, count 0 2006.201.22:28:19.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:19.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:28:19.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.22:28:19.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.22:28:19.72$vck44/vb=4,5 2006.201.22:28:19.72#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.22:28:19.72#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.22:28:19.72#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:19.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:19.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:19.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:19.77#ibcon#enter wrdev, iclass 19, count 2 2006.201.22:28:19.77#ibcon#first serial, iclass 19, count 2 2006.201.22:28:19.77#ibcon#enter sib2, iclass 19, count 2 2006.201.22:28:19.77#ibcon#flushed, iclass 19, count 2 2006.201.22:28:19.77#ibcon#about to write, iclass 19, count 2 2006.201.22:28:19.77#ibcon#wrote, iclass 19, count 2 2006.201.22:28:19.77#ibcon#about to read 3, iclass 19, count 2 2006.201.22:28:19.79#ibcon#read 3, iclass 19, count 2 2006.201.22:28:19.79#ibcon#about to read 4, iclass 19, count 2 2006.201.22:28:19.79#ibcon#read 4, iclass 19, count 2 2006.201.22:28:19.79#ibcon#about to read 5, iclass 19, count 2 2006.201.22:28:19.79#ibcon#read 5, iclass 19, count 2 2006.201.22:28:19.79#ibcon#about to read 6, iclass 19, count 2 2006.201.22:28:19.79#ibcon#read 6, iclass 19, count 2 2006.201.22:28:19.79#ibcon#end of sib2, iclass 19, count 2 2006.201.22:28:19.79#ibcon#*mode == 0, iclass 19, count 2 2006.201.22:28:19.79#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.22:28:19.79#ibcon#[27=AT04-05\r\n] 2006.201.22:28:19.79#ibcon#*before write, iclass 19, count 2 2006.201.22:28:19.79#ibcon#enter sib2, iclass 19, count 2 2006.201.22:28:19.79#ibcon#flushed, iclass 19, count 2 2006.201.22:28:19.79#ibcon#about to write, iclass 19, count 2 2006.201.22:28:19.79#ibcon#wrote, iclass 19, count 2 2006.201.22:28:19.79#ibcon#about to read 3, iclass 19, count 2 2006.201.22:28:19.82#ibcon#read 3, iclass 19, count 2 2006.201.22:28:19.82#ibcon#about to read 4, iclass 19, count 2 2006.201.22:28:19.82#ibcon#read 4, iclass 19, count 2 2006.201.22:28:19.82#ibcon#about to read 5, iclass 19, count 2 2006.201.22:28:19.82#ibcon#read 5, iclass 19, count 2 2006.201.22:28:19.82#ibcon#about to read 6, iclass 19, count 2 2006.201.22:28:19.82#ibcon#read 6, iclass 19, count 2 2006.201.22:28:19.82#ibcon#end of sib2, iclass 19, count 2 2006.201.22:28:19.82#ibcon#*after write, iclass 19, count 2 2006.201.22:28:19.82#ibcon#*before return 0, iclass 19, count 2 2006.201.22:28:19.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:19.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:28:19.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.22:28:19.82#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:19.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:19.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:19.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:19.94#ibcon#enter wrdev, iclass 19, count 0 2006.201.22:28:19.94#ibcon#first serial, iclass 19, count 0 2006.201.22:28:19.94#ibcon#enter sib2, iclass 19, count 0 2006.201.22:28:19.94#ibcon#flushed, iclass 19, count 0 2006.201.22:28:19.94#ibcon#about to write, iclass 19, count 0 2006.201.22:28:19.94#ibcon#wrote, iclass 19, count 0 2006.201.22:28:19.94#ibcon#about to read 3, iclass 19, count 0 2006.201.22:28:19.96#ibcon#read 3, iclass 19, count 0 2006.201.22:28:19.96#ibcon#about to read 4, iclass 19, count 0 2006.201.22:28:19.96#ibcon#read 4, iclass 19, count 0 2006.201.22:28:19.96#ibcon#about to read 5, iclass 19, count 0 2006.201.22:28:19.96#ibcon#read 5, iclass 19, count 0 2006.201.22:28:19.96#ibcon#about to read 6, iclass 19, count 0 2006.201.22:28:19.96#ibcon#read 6, iclass 19, count 0 2006.201.22:28:19.96#ibcon#end of sib2, iclass 19, count 0 2006.201.22:28:19.96#ibcon#*mode == 0, iclass 19, count 0 2006.201.22:28:19.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.22:28:19.96#ibcon#[27=USB\r\n] 2006.201.22:28:19.96#ibcon#*before write, iclass 19, count 0 2006.201.22:28:19.96#ibcon#enter sib2, iclass 19, count 0 2006.201.22:28:19.96#ibcon#flushed, iclass 19, count 0 2006.201.22:28:19.96#ibcon#about to write, iclass 19, count 0 2006.201.22:28:19.96#ibcon#wrote, iclass 19, count 0 2006.201.22:28:19.96#ibcon#about to read 3, iclass 19, count 0 2006.201.22:28:19.99#ibcon#read 3, iclass 19, count 0 2006.201.22:28:19.99#ibcon#about to read 4, iclass 19, count 0 2006.201.22:28:19.99#ibcon#read 4, iclass 19, count 0 2006.201.22:28:19.99#ibcon#about to read 5, iclass 19, count 0 2006.201.22:28:19.99#ibcon#read 5, iclass 19, count 0 2006.201.22:28:19.99#ibcon#about to read 6, iclass 19, count 0 2006.201.22:28:19.99#ibcon#read 6, iclass 19, count 0 2006.201.22:28:19.99#ibcon#end of sib2, iclass 19, count 0 2006.201.22:28:19.99#ibcon#*after write, iclass 19, count 0 2006.201.22:28:19.99#ibcon#*before return 0, iclass 19, count 0 2006.201.22:28:19.99#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:19.99#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:28:19.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.22:28:19.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.22:28:19.99$vck44/vblo=5,709.99 2006.201.22:28:19.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.22:28:19.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.22:28:19.99#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:19.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:19.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:19.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:19.99#ibcon#enter wrdev, iclass 21, count 0 2006.201.22:28:19.99#ibcon#first serial, iclass 21, count 0 2006.201.22:28:19.99#ibcon#enter sib2, iclass 21, count 0 2006.201.22:28:19.99#ibcon#flushed, iclass 21, count 0 2006.201.22:28:19.99#ibcon#about to write, iclass 21, count 0 2006.201.22:28:19.99#ibcon#wrote, iclass 21, count 0 2006.201.22:28:19.99#ibcon#about to read 3, iclass 21, count 0 2006.201.22:28:20.01#ibcon#read 3, iclass 21, count 0 2006.201.22:28:20.01#ibcon#about to read 4, iclass 21, count 0 2006.201.22:28:20.01#ibcon#read 4, iclass 21, count 0 2006.201.22:28:20.01#ibcon#about to read 5, iclass 21, count 0 2006.201.22:28:20.01#ibcon#read 5, iclass 21, count 0 2006.201.22:28:20.01#ibcon#about to read 6, iclass 21, count 0 2006.201.22:28:20.01#ibcon#read 6, iclass 21, count 0 2006.201.22:28:20.01#ibcon#end of sib2, iclass 21, count 0 2006.201.22:28:20.01#ibcon#*mode == 0, iclass 21, count 0 2006.201.22:28:20.01#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.22:28:20.01#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.22:28:20.01#ibcon#*before write, iclass 21, count 0 2006.201.22:28:20.01#ibcon#enter sib2, iclass 21, count 0 2006.201.22:28:20.01#ibcon#flushed, iclass 21, count 0 2006.201.22:28:20.01#ibcon#about to write, iclass 21, count 0 2006.201.22:28:20.01#ibcon#wrote, iclass 21, count 0 2006.201.22:28:20.01#ibcon#about to read 3, iclass 21, count 0 2006.201.22:28:20.05#ibcon#read 3, iclass 21, count 0 2006.201.22:28:20.05#ibcon#about to read 4, iclass 21, count 0 2006.201.22:28:20.05#ibcon#read 4, iclass 21, count 0 2006.201.22:28:20.05#ibcon#about to read 5, iclass 21, count 0 2006.201.22:28:20.05#ibcon#read 5, iclass 21, count 0 2006.201.22:28:20.05#ibcon#about to read 6, iclass 21, count 0 2006.201.22:28:20.05#ibcon#read 6, iclass 21, count 0 2006.201.22:28:20.05#ibcon#end of sib2, iclass 21, count 0 2006.201.22:28:20.05#ibcon#*after write, iclass 21, count 0 2006.201.22:28:20.05#ibcon#*before return 0, iclass 21, count 0 2006.201.22:28:20.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:20.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:28:20.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.22:28:20.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.22:28:20.05$vck44/vb=5,4 2006.201.22:28:20.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.22:28:20.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.22:28:20.05#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:20.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:20.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:20.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:20.11#ibcon#enter wrdev, iclass 23, count 2 2006.201.22:28:20.11#ibcon#first serial, iclass 23, count 2 2006.201.22:28:20.11#ibcon#enter sib2, iclass 23, count 2 2006.201.22:28:20.11#ibcon#flushed, iclass 23, count 2 2006.201.22:28:20.11#ibcon#about to write, iclass 23, count 2 2006.201.22:28:20.11#ibcon#wrote, iclass 23, count 2 2006.201.22:28:20.11#ibcon#about to read 3, iclass 23, count 2 2006.201.22:28:20.13#ibcon#read 3, iclass 23, count 2 2006.201.22:28:20.13#ibcon#about to read 4, iclass 23, count 2 2006.201.22:28:20.13#ibcon#read 4, iclass 23, count 2 2006.201.22:28:20.13#ibcon#about to read 5, iclass 23, count 2 2006.201.22:28:20.13#ibcon#read 5, iclass 23, count 2 2006.201.22:28:20.13#ibcon#about to read 6, iclass 23, count 2 2006.201.22:28:20.13#ibcon#read 6, iclass 23, count 2 2006.201.22:28:20.13#ibcon#end of sib2, iclass 23, count 2 2006.201.22:28:20.13#ibcon#*mode == 0, iclass 23, count 2 2006.201.22:28:20.13#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.22:28:20.13#ibcon#[27=AT05-04\r\n] 2006.201.22:28:20.13#ibcon#*before write, iclass 23, count 2 2006.201.22:28:20.13#ibcon#enter sib2, iclass 23, count 2 2006.201.22:28:20.13#ibcon#flushed, iclass 23, count 2 2006.201.22:28:20.13#ibcon#about to write, iclass 23, count 2 2006.201.22:28:20.13#ibcon#wrote, iclass 23, count 2 2006.201.22:28:20.13#ibcon#about to read 3, iclass 23, count 2 2006.201.22:28:20.16#ibcon#read 3, iclass 23, count 2 2006.201.22:28:20.16#ibcon#about to read 4, iclass 23, count 2 2006.201.22:28:20.16#ibcon#read 4, iclass 23, count 2 2006.201.22:28:20.16#ibcon#about to read 5, iclass 23, count 2 2006.201.22:28:20.16#ibcon#read 5, iclass 23, count 2 2006.201.22:28:20.16#ibcon#about to read 6, iclass 23, count 2 2006.201.22:28:20.16#ibcon#read 6, iclass 23, count 2 2006.201.22:28:20.16#ibcon#end of sib2, iclass 23, count 2 2006.201.22:28:20.16#ibcon#*after write, iclass 23, count 2 2006.201.22:28:20.16#ibcon#*before return 0, iclass 23, count 2 2006.201.22:28:20.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:20.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:28:20.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.22:28:20.16#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:20.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:20.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:20.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:20.28#ibcon#enter wrdev, iclass 23, count 0 2006.201.22:28:20.28#ibcon#first serial, iclass 23, count 0 2006.201.22:28:20.28#ibcon#enter sib2, iclass 23, count 0 2006.201.22:28:20.28#ibcon#flushed, iclass 23, count 0 2006.201.22:28:20.28#ibcon#about to write, iclass 23, count 0 2006.201.22:28:20.28#ibcon#wrote, iclass 23, count 0 2006.201.22:28:20.28#ibcon#about to read 3, iclass 23, count 0 2006.201.22:28:20.30#ibcon#read 3, iclass 23, count 0 2006.201.22:28:20.30#ibcon#about to read 4, iclass 23, count 0 2006.201.22:28:20.30#ibcon#read 4, iclass 23, count 0 2006.201.22:28:20.30#ibcon#about to read 5, iclass 23, count 0 2006.201.22:28:20.30#ibcon#read 5, iclass 23, count 0 2006.201.22:28:20.30#ibcon#about to read 6, iclass 23, count 0 2006.201.22:28:20.30#ibcon#read 6, iclass 23, count 0 2006.201.22:28:20.30#ibcon#end of sib2, iclass 23, count 0 2006.201.22:28:20.30#ibcon#*mode == 0, iclass 23, count 0 2006.201.22:28:20.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.22:28:20.30#ibcon#[27=USB\r\n] 2006.201.22:28:20.30#ibcon#*before write, iclass 23, count 0 2006.201.22:28:20.30#ibcon#enter sib2, iclass 23, count 0 2006.201.22:28:20.30#ibcon#flushed, iclass 23, count 0 2006.201.22:28:20.30#ibcon#about to write, iclass 23, count 0 2006.201.22:28:20.30#ibcon#wrote, iclass 23, count 0 2006.201.22:28:20.30#ibcon#about to read 3, iclass 23, count 0 2006.201.22:28:20.33#ibcon#read 3, iclass 23, count 0 2006.201.22:28:20.33#ibcon#about to read 4, iclass 23, count 0 2006.201.22:28:20.33#ibcon#read 4, iclass 23, count 0 2006.201.22:28:20.33#ibcon#about to read 5, iclass 23, count 0 2006.201.22:28:20.33#ibcon#read 5, iclass 23, count 0 2006.201.22:28:20.33#ibcon#about to read 6, iclass 23, count 0 2006.201.22:28:20.33#ibcon#read 6, iclass 23, count 0 2006.201.22:28:20.33#ibcon#end of sib2, iclass 23, count 0 2006.201.22:28:20.33#ibcon#*after write, iclass 23, count 0 2006.201.22:28:20.33#ibcon#*before return 0, iclass 23, count 0 2006.201.22:28:20.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:20.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:28:20.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.22:28:20.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.22:28:20.33$vck44/vblo=6,719.99 2006.201.22:28:20.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.22:28:20.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.22:28:20.33#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:20.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:20.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:20.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:20.33#ibcon#enter wrdev, iclass 25, count 0 2006.201.22:28:20.33#ibcon#first serial, iclass 25, count 0 2006.201.22:28:20.33#ibcon#enter sib2, iclass 25, count 0 2006.201.22:28:20.33#ibcon#flushed, iclass 25, count 0 2006.201.22:28:20.33#ibcon#about to write, iclass 25, count 0 2006.201.22:28:20.33#ibcon#wrote, iclass 25, count 0 2006.201.22:28:20.33#ibcon#about to read 3, iclass 25, count 0 2006.201.22:28:20.35#ibcon#read 3, iclass 25, count 0 2006.201.22:28:20.35#ibcon#about to read 4, iclass 25, count 0 2006.201.22:28:20.35#ibcon#read 4, iclass 25, count 0 2006.201.22:28:20.35#ibcon#about to read 5, iclass 25, count 0 2006.201.22:28:20.35#ibcon#read 5, iclass 25, count 0 2006.201.22:28:20.35#ibcon#about to read 6, iclass 25, count 0 2006.201.22:28:20.35#ibcon#read 6, iclass 25, count 0 2006.201.22:28:20.35#ibcon#end of sib2, iclass 25, count 0 2006.201.22:28:20.35#ibcon#*mode == 0, iclass 25, count 0 2006.201.22:28:20.35#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.22:28:20.35#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.22:28:20.35#ibcon#*before write, iclass 25, count 0 2006.201.22:28:20.35#ibcon#enter sib2, iclass 25, count 0 2006.201.22:28:20.35#ibcon#flushed, iclass 25, count 0 2006.201.22:28:20.35#ibcon#about to write, iclass 25, count 0 2006.201.22:28:20.35#ibcon#wrote, iclass 25, count 0 2006.201.22:28:20.35#ibcon#about to read 3, iclass 25, count 0 2006.201.22:28:20.39#ibcon#read 3, iclass 25, count 0 2006.201.22:28:20.39#ibcon#about to read 4, iclass 25, count 0 2006.201.22:28:20.39#ibcon#read 4, iclass 25, count 0 2006.201.22:28:20.39#ibcon#about to read 5, iclass 25, count 0 2006.201.22:28:20.39#ibcon#read 5, iclass 25, count 0 2006.201.22:28:20.39#ibcon#about to read 6, iclass 25, count 0 2006.201.22:28:20.39#ibcon#read 6, iclass 25, count 0 2006.201.22:28:20.39#ibcon#end of sib2, iclass 25, count 0 2006.201.22:28:20.39#ibcon#*after write, iclass 25, count 0 2006.201.22:28:20.39#ibcon#*before return 0, iclass 25, count 0 2006.201.22:28:20.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:20.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:28:20.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.22:28:20.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.22:28:20.39$vck44/vb=6,4 2006.201.22:28:20.39#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.22:28:20.39#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.22:28:20.39#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:20.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:20.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:20.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:20.45#ibcon#enter wrdev, iclass 27, count 2 2006.201.22:28:20.45#ibcon#first serial, iclass 27, count 2 2006.201.22:28:20.45#ibcon#enter sib2, iclass 27, count 2 2006.201.22:28:20.45#ibcon#flushed, iclass 27, count 2 2006.201.22:28:20.45#ibcon#about to write, iclass 27, count 2 2006.201.22:28:20.45#ibcon#wrote, iclass 27, count 2 2006.201.22:28:20.45#ibcon#about to read 3, iclass 27, count 2 2006.201.22:28:20.47#ibcon#read 3, iclass 27, count 2 2006.201.22:28:20.47#ibcon#about to read 4, iclass 27, count 2 2006.201.22:28:20.47#ibcon#read 4, iclass 27, count 2 2006.201.22:28:20.47#ibcon#about to read 5, iclass 27, count 2 2006.201.22:28:20.47#ibcon#read 5, iclass 27, count 2 2006.201.22:28:20.47#ibcon#about to read 6, iclass 27, count 2 2006.201.22:28:20.47#ibcon#read 6, iclass 27, count 2 2006.201.22:28:20.47#ibcon#end of sib2, iclass 27, count 2 2006.201.22:28:20.47#ibcon#*mode == 0, iclass 27, count 2 2006.201.22:28:20.47#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.22:28:20.47#ibcon#[27=AT06-04\r\n] 2006.201.22:28:20.47#ibcon#*before write, iclass 27, count 2 2006.201.22:28:20.47#ibcon#enter sib2, iclass 27, count 2 2006.201.22:28:20.47#ibcon#flushed, iclass 27, count 2 2006.201.22:28:20.47#ibcon#about to write, iclass 27, count 2 2006.201.22:28:20.47#ibcon#wrote, iclass 27, count 2 2006.201.22:28:20.47#ibcon#about to read 3, iclass 27, count 2 2006.201.22:28:20.50#ibcon#read 3, iclass 27, count 2 2006.201.22:28:20.50#ibcon#about to read 4, iclass 27, count 2 2006.201.22:28:20.50#ibcon#read 4, iclass 27, count 2 2006.201.22:28:20.50#ibcon#about to read 5, iclass 27, count 2 2006.201.22:28:20.50#ibcon#read 5, iclass 27, count 2 2006.201.22:28:20.50#ibcon#about to read 6, iclass 27, count 2 2006.201.22:28:20.50#ibcon#read 6, iclass 27, count 2 2006.201.22:28:20.50#ibcon#end of sib2, iclass 27, count 2 2006.201.22:28:20.50#ibcon#*after write, iclass 27, count 2 2006.201.22:28:20.50#ibcon#*before return 0, iclass 27, count 2 2006.201.22:28:20.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:20.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:28:20.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.22:28:20.50#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:20.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:20.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:20.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:20.62#ibcon#enter wrdev, iclass 27, count 0 2006.201.22:28:20.62#ibcon#first serial, iclass 27, count 0 2006.201.22:28:20.62#ibcon#enter sib2, iclass 27, count 0 2006.201.22:28:20.62#ibcon#flushed, iclass 27, count 0 2006.201.22:28:20.62#ibcon#about to write, iclass 27, count 0 2006.201.22:28:20.62#ibcon#wrote, iclass 27, count 0 2006.201.22:28:20.62#ibcon#about to read 3, iclass 27, count 0 2006.201.22:28:20.64#ibcon#read 3, iclass 27, count 0 2006.201.22:28:20.64#ibcon#about to read 4, iclass 27, count 0 2006.201.22:28:20.64#ibcon#read 4, iclass 27, count 0 2006.201.22:28:20.64#ibcon#about to read 5, iclass 27, count 0 2006.201.22:28:20.64#ibcon#read 5, iclass 27, count 0 2006.201.22:28:20.64#ibcon#about to read 6, iclass 27, count 0 2006.201.22:28:20.64#ibcon#read 6, iclass 27, count 0 2006.201.22:28:20.64#ibcon#end of sib2, iclass 27, count 0 2006.201.22:28:20.64#ibcon#*mode == 0, iclass 27, count 0 2006.201.22:28:20.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.22:28:20.64#ibcon#[27=USB\r\n] 2006.201.22:28:20.64#ibcon#*before write, iclass 27, count 0 2006.201.22:28:20.64#ibcon#enter sib2, iclass 27, count 0 2006.201.22:28:20.64#ibcon#flushed, iclass 27, count 0 2006.201.22:28:20.64#ibcon#about to write, iclass 27, count 0 2006.201.22:28:20.64#ibcon#wrote, iclass 27, count 0 2006.201.22:28:20.64#ibcon#about to read 3, iclass 27, count 0 2006.201.22:28:20.67#ibcon#read 3, iclass 27, count 0 2006.201.22:28:20.67#ibcon#about to read 4, iclass 27, count 0 2006.201.22:28:20.67#ibcon#read 4, iclass 27, count 0 2006.201.22:28:20.67#ibcon#about to read 5, iclass 27, count 0 2006.201.22:28:20.67#ibcon#read 5, iclass 27, count 0 2006.201.22:28:20.67#ibcon#about to read 6, iclass 27, count 0 2006.201.22:28:20.67#ibcon#read 6, iclass 27, count 0 2006.201.22:28:20.67#ibcon#end of sib2, iclass 27, count 0 2006.201.22:28:20.67#ibcon#*after write, iclass 27, count 0 2006.201.22:28:20.67#ibcon#*before return 0, iclass 27, count 0 2006.201.22:28:20.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:20.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:28:20.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.22:28:20.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.22:28:20.67$vck44/vblo=7,734.99 2006.201.22:28:20.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.22:28:20.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.22:28:20.67#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:20.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:20.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:20.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:20.67#ibcon#enter wrdev, iclass 29, count 0 2006.201.22:28:20.67#ibcon#first serial, iclass 29, count 0 2006.201.22:28:20.67#ibcon#enter sib2, iclass 29, count 0 2006.201.22:28:20.67#ibcon#flushed, iclass 29, count 0 2006.201.22:28:20.67#ibcon#about to write, iclass 29, count 0 2006.201.22:28:20.67#ibcon#wrote, iclass 29, count 0 2006.201.22:28:20.67#ibcon#about to read 3, iclass 29, count 0 2006.201.22:28:20.69#ibcon#read 3, iclass 29, count 0 2006.201.22:28:20.69#ibcon#about to read 4, iclass 29, count 0 2006.201.22:28:20.69#ibcon#read 4, iclass 29, count 0 2006.201.22:28:20.69#ibcon#about to read 5, iclass 29, count 0 2006.201.22:28:20.69#ibcon#read 5, iclass 29, count 0 2006.201.22:28:20.69#ibcon#about to read 6, iclass 29, count 0 2006.201.22:28:20.69#ibcon#read 6, iclass 29, count 0 2006.201.22:28:20.69#ibcon#end of sib2, iclass 29, count 0 2006.201.22:28:20.69#ibcon#*mode == 0, iclass 29, count 0 2006.201.22:28:20.69#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.22:28:20.69#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.22:28:20.69#ibcon#*before write, iclass 29, count 0 2006.201.22:28:20.69#ibcon#enter sib2, iclass 29, count 0 2006.201.22:28:20.69#ibcon#flushed, iclass 29, count 0 2006.201.22:28:20.69#ibcon#about to write, iclass 29, count 0 2006.201.22:28:20.69#ibcon#wrote, iclass 29, count 0 2006.201.22:28:20.69#ibcon#about to read 3, iclass 29, count 0 2006.201.22:28:20.74#ibcon#read 3, iclass 29, count 0 2006.201.22:28:20.74#ibcon#about to read 4, iclass 29, count 0 2006.201.22:28:20.74#ibcon#read 4, iclass 29, count 0 2006.201.22:28:20.74#ibcon#about to read 5, iclass 29, count 0 2006.201.22:28:20.74#ibcon#read 5, iclass 29, count 0 2006.201.22:28:20.74#ibcon#about to read 6, iclass 29, count 0 2006.201.22:28:20.74#ibcon#read 6, iclass 29, count 0 2006.201.22:28:20.74#ibcon#end of sib2, iclass 29, count 0 2006.201.22:28:20.74#ibcon#*after write, iclass 29, count 0 2006.201.22:28:20.74#ibcon#*before return 0, iclass 29, count 0 2006.201.22:28:20.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:20.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:28:20.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.22:28:20.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.22:28:20.74$vck44/vb=7,4 2006.201.22:28:20.74#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.22:28:20.74#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.22:28:20.74#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:20.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:20.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:20.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:20.79#ibcon#enter wrdev, iclass 31, count 2 2006.201.22:28:20.79#ibcon#first serial, iclass 31, count 2 2006.201.22:28:20.79#ibcon#enter sib2, iclass 31, count 2 2006.201.22:28:20.79#ibcon#flushed, iclass 31, count 2 2006.201.22:28:20.79#ibcon#about to write, iclass 31, count 2 2006.201.22:28:20.79#ibcon#wrote, iclass 31, count 2 2006.201.22:28:20.79#ibcon#about to read 3, iclass 31, count 2 2006.201.22:28:20.81#ibcon#read 3, iclass 31, count 2 2006.201.22:28:20.81#ibcon#about to read 4, iclass 31, count 2 2006.201.22:28:20.81#ibcon#read 4, iclass 31, count 2 2006.201.22:28:20.81#ibcon#about to read 5, iclass 31, count 2 2006.201.22:28:20.81#ibcon#read 5, iclass 31, count 2 2006.201.22:28:20.81#ibcon#about to read 6, iclass 31, count 2 2006.201.22:28:20.81#ibcon#read 6, iclass 31, count 2 2006.201.22:28:20.81#ibcon#end of sib2, iclass 31, count 2 2006.201.22:28:20.81#ibcon#*mode == 0, iclass 31, count 2 2006.201.22:28:20.81#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.22:28:20.81#ibcon#[27=AT07-04\r\n] 2006.201.22:28:20.81#ibcon#*before write, iclass 31, count 2 2006.201.22:28:20.81#ibcon#enter sib2, iclass 31, count 2 2006.201.22:28:20.81#ibcon#flushed, iclass 31, count 2 2006.201.22:28:20.81#ibcon#about to write, iclass 31, count 2 2006.201.22:28:20.81#ibcon#wrote, iclass 31, count 2 2006.201.22:28:20.81#ibcon#about to read 3, iclass 31, count 2 2006.201.22:28:20.84#ibcon#read 3, iclass 31, count 2 2006.201.22:28:20.84#ibcon#about to read 4, iclass 31, count 2 2006.201.22:28:20.84#ibcon#read 4, iclass 31, count 2 2006.201.22:28:20.84#ibcon#about to read 5, iclass 31, count 2 2006.201.22:28:20.84#ibcon#read 5, iclass 31, count 2 2006.201.22:28:20.84#ibcon#about to read 6, iclass 31, count 2 2006.201.22:28:20.84#ibcon#read 6, iclass 31, count 2 2006.201.22:28:20.84#ibcon#end of sib2, iclass 31, count 2 2006.201.22:28:20.84#ibcon#*after write, iclass 31, count 2 2006.201.22:28:20.84#ibcon#*before return 0, iclass 31, count 2 2006.201.22:28:20.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:20.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:28:20.84#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.22:28:20.84#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:20.84#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:20.96#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:20.96#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:20.96#ibcon#enter wrdev, iclass 31, count 0 2006.201.22:28:20.96#ibcon#first serial, iclass 31, count 0 2006.201.22:28:20.96#ibcon#enter sib2, iclass 31, count 0 2006.201.22:28:20.96#ibcon#flushed, iclass 31, count 0 2006.201.22:28:20.96#ibcon#about to write, iclass 31, count 0 2006.201.22:28:20.96#ibcon#wrote, iclass 31, count 0 2006.201.22:28:20.96#ibcon#about to read 3, iclass 31, count 0 2006.201.22:28:20.98#ibcon#read 3, iclass 31, count 0 2006.201.22:28:20.98#ibcon#about to read 4, iclass 31, count 0 2006.201.22:28:20.98#ibcon#read 4, iclass 31, count 0 2006.201.22:28:20.98#ibcon#about to read 5, iclass 31, count 0 2006.201.22:28:20.98#ibcon#read 5, iclass 31, count 0 2006.201.22:28:20.98#ibcon#about to read 6, iclass 31, count 0 2006.201.22:28:20.98#ibcon#read 6, iclass 31, count 0 2006.201.22:28:20.98#ibcon#end of sib2, iclass 31, count 0 2006.201.22:28:20.98#ibcon#*mode == 0, iclass 31, count 0 2006.201.22:28:20.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.22:28:20.98#ibcon#[27=USB\r\n] 2006.201.22:28:20.98#ibcon#*before write, iclass 31, count 0 2006.201.22:28:20.98#ibcon#enter sib2, iclass 31, count 0 2006.201.22:28:20.98#ibcon#flushed, iclass 31, count 0 2006.201.22:28:20.98#ibcon#about to write, iclass 31, count 0 2006.201.22:28:20.98#ibcon#wrote, iclass 31, count 0 2006.201.22:28:20.98#ibcon#about to read 3, iclass 31, count 0 2006.201.22:28:21.01#ibcon#read 3, iclass 31, count 0 2006.201.22:28:21.01#ibcon#about to read 4, iclass 31, count 0 2006.201.22:28:21.01#ibcon#read 4, iclass 31, count 0 2006.201.22:28:21.01#ibcon#about to read 5, iclass 31, count 0 2006.201.22:28:21.01#ibcon#read 5, iclass 31, count 0 2006.201.22:28:21.01#ibcon#about to read 6, iclass 31, count 0 2006.201.22:28:21.01#ibcon#read 6, iclass 31, count 0 2006.201.22:28:21.01#ibcon#end of sib2, iclass 31, count 0 2006.201.22:28:21.01#ibcon#*after write, iclass 31, count 0 2006.201.22:28:21.01#ibcon#*before return 0, iclass 31, count 0 2006.201.22:28:21.01#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:21.01#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:28:21.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.22:28:21.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.22:28:21.01$vck44/vblo=8,744.99 2006.201.22:28:21.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.22:28:21.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.22:28:21.01#ibcon#ireg 17 cls_cnt 0 2006.201.22:28:21.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:21.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:21.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:21.01#ibcon#enter wrdev, iclass 33, count 0 2006.201.22:28:21.01#ibcon#first serial, iclass 33, count 0 2006.201.22:28:21.01#ibcon#enter sib2, iclass 33, count 0 2006.201.22:28:21.01#ibcon#flushed, iclass 33, count 0 2006.201.22:28:21.01#ibcon#about to write, iclass 33, count 0 2006.201.22:28:21.01#ibcon#wrote, iclass 33, count 0 2006.201.22:28:21.01#ibcon#about to read 3, iclass 33, count 0 2006.201.22:28:21.03#ibcon#read 3, iclass 33, count 0 2006.201.22:28:21.03#ibcon#about to read 4, iclass 33, count 0 2006.201.22:28:21.03#ibcon#read 4, iclass 33, count 0 2006.201.22:28:21.03#ibcon#about to read 5, iclass 33, count 0 2006.201.22:28:21.03#ibcon#read 5, iclass 33, count 0 2006.201.22:28:21.03#ibcon#about to read 6, iclass 33, count 0 2006.201.22:28:21.03#ibcon#read 6, iclass 33, count 0 2006.201.22:28:21.03#ibcon#end of sib2, iclass 33, count 0 2006.201.22:28:21.03#ibcon#*mode == 0, iclass 33, count 0 2006.201.22:28:21.03#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.22:28:21.03#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.22:28:21.03#ibcon#*before write, iclass 33, count 0 2006.201.22:28:21.03#ibcon#enter sib2, iclass 33, count 0 2006.201.22:28:21.03#ibcon#flushed, iclass 33, count 0 2006.201.22:28:21.03#ibcon#about to write, iclass 33, count 0 2006.201.22:28:21.03#ibcon#wrote, iclass 33, count 0 2006.201.22:28:21.03#ibcon#about to read 3, iclass 33, count 0 2006.201.22:28:21.07#ibcon#read 3, iclass 33, count 0 2006.201.22:28:21.07#ibcon#about to read 4, iclass 33, count 0 2006.201.22:28:21.07#ibcon#read 4, iclass 33, count 0 2006.201.22:28:21.07#ibcon#about to read 5, iclass 33, count 0 2006.201.22:28:21.07#ibcon#read 5, iclass 33, count 0 2006.201.22:28:21.07#ibcon#about to read 6, iclass 33, count 0 2006.201.22:28:21.07#ibcon#read 6, iclass 33, count 0 2006.201.22:28:21.07#ibcon#end of sib2, iclass 33, count 0 2006.201.22:28:21.07#ibcon#*after write, iclass 33, count 0 2006.201.22:28:21.07#ibcon#*before return 0, iclass 33, count 0 2006.201.22:28:21.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:21.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:28:21.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.22:28:21.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.22:28:21.07$vck44/vb=8,4 2006.201.22:28:21.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.22:28:21.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.22:28:21.07#ibcon#ireg 11 cls_cnt 2 2006.201.22:28:21.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:21.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:21.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:21.13#ibcon#enter wrdev, iclass 35, count 2 2006.201.22:28:21.13#ibcon#first serial, iclass 35, count 2 2006.201.22:28:21.13#ibcon#enter sib2, iclass 35, count 2 2006.201.22:28:21.13#ibcon#flushed, iclass 35, count 2 2006.201.22:28:21.13#ibcon#about to write, iclass 35, count 2 2006.201.22:28:21.13#ibcon#wrote, iclass 35, count 2 2006.201.22:28:21.13#ibcon#about to read 3, iclass 35, count 2 2006.201.22:28:21.15#ibcon#read 3, iclass 35, count 2 2006.201.22:28:21.15#ibcon#about to read 4, iclass 35, count 2 2006.201.22:28:21.15#ibcon#read 4, iclass 35, count 2 2006.201.22:28:21.15#ibcon#about to read 5, iclass 35, count 2 2006.201.22:28:21.15#ibcon#read 5, iclass 35, count 2 2006.201.22:28:21.15#ibcon#about to read 6, iclass 35, count 2 2006.201.22:28:21.15#ibcon#read 6, iclass 35, count 2 2006.201.22:28:21.15#ibcon#end of sib2, iclass 35, count 2 2006.201.22:28:21.15#ibcon#*mode == 0, iclass 35, count 2 2006.201.22:28:21.15#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.22:28:21.15#ibcon#[27=AT08-04\r\n] 2006.201.22:28:21.15#ibcon#*before write, iclass 35, count 2 2006.201.22:28:21.15#ibcon#enter sib2, iclass 35, count 2 2006.201.22:28:21.15#ibcon#flushed, iclass 35, count 2 2006.201.22:28:21.15#ibcon#about to write, iclass 35, count 2 2006.201.22:28:21.15#ibcon#wrote, iclass 35, count 2 2006.201.22:28:21.15#ibcon#about to read 3, iclass 35, count 2 2006.201.22:28:21.18#ibcon#read 3, iclass 35, count 2 2006.201.22:28:21.18#ibcon#about to read 4, iclass 35, count 2 2006.201.22:28:21.18#ibcon#read 4, iclass 35, count 2 2006.201.22:28:21.18#ibcon#about to read 5, iclass 35, count 2 2006.201.22:28:21.18#ibcon#read 5, iclass 35, count 2 2006.201.22:28:21.18#ibcon#about to read 6, iclass 35, count 2 2006.201.22:28:21.18#ibcon#read 6, iclass 35, count 2 2006.201.22:28:21.18#ibcon#end of sib2, iclass 35, count 2 2006.201.22:28:21.18#ibcon#*after write, iclass 35, count 2 2006.201.22:28:21.18#ibcon#*before return 0, iclass 35, count 2 2006.201.22:28:21.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:21.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:28:21.18#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.22:28:21.18#ibcon#ireg 7 cls_cnt 0 2006.201.22:28:21.18#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:21.30#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:21.30#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:21.30#ibcon#enter wrdev, iclass 35, count 0 2006.201.22:28:21.30#ibcon#first serial, iclass 35, count 0 2006.201.22:28:21.30#ibcon#enter sib2, iclass 35, count 0 2006.201.22:28:21.30#ibcon#flushed, iclass 35, count 0 2006.201.22:28:21.30#ibcon#about to write, iclass 35, count 0 2006.201.22:28:21.30#ibcon#wrote, iclass 35, count 0 2006.201.22:28:21.30#ibcon#about to read 3, iclass 35, count 0 2006.201.22:28:21.32#ibcon#read 3, iclass 35, count 0 2006.201.22:28:21.32#ibcon#about to read 4, iclass 35, count 0 2006.201.22:28:21.32#ibcon#read 4, iclass 35, count 0 2006.201.22:28:21.32#ibcon#about to read 5, iclass 35, count 0 2006.201.22:28:21.32#ibcon#read 5, iclass 35, count 0 2006.201.22:28:21.32#ibcon#about to read 6, iclass 35, count 0 2006.201.22:28:21.32#ibcon#read 6, iclass 35, count 0 2006.201.22:28:21.32#ibcon#end of sib2, iclass 35, count 0 2006.201.22:28:21.32#ibcon#*mode == 0, iclass 35, count 0 2006.201.22:28:21.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.22:28:21.32#ibcon#[27=USB\r\n] 2006.201.22:28:21.32#ibcon#*before write, iclass 35, count 0 2006.201.22:28:21.32#ibcon#enter sib2, iclass 35, count 0 2006.201.22:28:21.32#ibcon#flushed, iclass 35, count 0 2006.201.22:28:21.32#ibcon#about to write, iclass 35, count 0 2006.201.22:28:21.32#ibcon#wrote, iclass 35, count 0 2006.201.22:28:21.32#ibcon#about to read 3, iclass 35, count 0 2006.201.22:28:21.35#ibcon#read 3, iclass 35, count 0 2006.201.22:28:21.35#ibcon#about to read 4, iclass 35, count 0 2006.201.22:28:21.35#ibcon#read 4, iclass 35, count 0 2006.201.22:28:21.35#ibcon#about to read 5, iclass 35, count 0 2006.201.22:28:21.35#ibcon#read 5, iclass 35, count 0 2006.201.22:28:21.35#ibcon#about to read 6, iclass 35, count 0 2006.201.22:28:21.35#ibcon#read 6, iclass 35, count 0 2006.201.22:28:21.35#ibcon#end of sib2, iclass 35, count 0 2006.201.22:28:21.35#ibcon#*after write, iclass 35, count 0 2006.201.22:28:21.35#ibcon#*before return 0, iclass 35, count 0 2006.201.22:28:21.35#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:21.35#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:28:21.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.22:28:21.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.22:28:21.35$vck44/vabw=wide 2006.201.22:28:21.35#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.22:28:21.35#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.22:28:21.35#ibcon#ireg 8 cls_cnt 0 2006.201.22:28:21.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:21.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:21.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:21.35#ibcon#enter wrdev, iclass 37, count 0 2006.201.22:28:21.35#ibcon#first serial, iclass 37, count 0 2006.201.22:28:21.35#ibcon#enter sib2, iclass 37, count 0 2006.201.22:28:21.35#ibcon#flushed, iclass 37, count 0 2006.201.22:28:21.35#ibcon#about to write, iclass 37, count 0 2006.201.22:28:21.35#ibcon#wrote, iclass 37, count 0 2006.201.22:28:21.35#ibcon#about to read 3, iclass 37, count 0 2006.201.22:28:21.37#ibcon#read 3, iclass 37, count 0 2006.201.22:28:21.37#ibcon#about to read 4, iclass 37, count 0 2006.201.22:28:21.37#ibcon#read 4, iclass 37, count 0 2006.201.22:28:21.37#ibcon#about to read 5, iclass 37, count 0 2006.201.22:28:21.37#ibcon#read 5, iclass 37, count 0 2006.201.22:28:21.37#ibcon#about to read 6, iclass 37, count 0 2006.201.22:28:21.37#ibcon#read 6, iclass 37, count 0 2006.201.22:28:21.37#ibcon#end of sib2, iclass 37, count 0 2006.201.22:28:21.37#ibcon#*mode == 0, iclass 37, count 0 2006.201.22:28:21.37#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.22:28:21.37#ibcon#[25=BW32\r\n] 2006.201.22:28:21.37#ibcon#*before write, iclass 37, count 0 2006.201.22:28:21.37#ibcon#enter sib2, iclass 37, count 0 2006.201.22:28:21.37#ibcon#flushed, iclass 37, count 0 2006.201.22:28:21.37#ibcon#about to write, iclass 37, count 0 2006.201.22:28:21.37#ibcon#wrote, iclass 37, count 0 2006.201.22:28:21.37#ibcon#about to read 3, iclass 37, count 0 2006.201.22:28:21.40#ibcon#read 3, iclass 37, count 0 2006.201.22:28:21.40#ibcon#about to read 4, iclass 37, count 0 2006.201.22:28:21.40#ibcon#read 4, iclass 37, count 0 2006.201.22:28:21.40#ibcon#about to read 5, iclass 37, count 0 2006.201.22:28:21.40#ibcon#read 5, iclass 37, count 0 2006.201.22:28:21.40#ibcon#about to read 6, iclass 37, count 0 2006.201.22:28:21.40#ibcon#read 6, iclass 37, count 0 2006.201.22:28:21.40#ibcon#end of sib2, iclass 37, count 0 2006.201.22:28:21.40#ibcon#*after write, iclass 37, count 0 2006.201.22:28:21.40#ibcon#*before return 0, iclass 37, count 0 2006.201.22:28:21.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:21.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:28:21.40#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.22:28:21.40#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.22:28:21.40$vck44/vbbw=wide 2006.201.22:28:21.40#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.22:28:21.40#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.22:28:21.40#ibcon#ireg 8 cls_cnt 0 2006.201.22:28:21.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:28:21.47#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:28:21.47#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:28:21.47#ibcon#enter wrdev, iclass 39, count 0 2006.201.22:28:21.47#ibcon#first serial, iclass 39, count 0 2006.201.22:28:21.47#ibcon#enter sib2, iclass 39, count 0 2006.201.22:28:21.47#ibcon#flushed, iclass 39, count 0 2006.201.22:28:21.47#ibcon#about to write, iclass 39, count 0 2006.201.22:28:21.47#ibcon#wrote, iclass 39, count 0 2006.201.22:28:21.47#ibcon#about to read 3, iclass 39, count 0 2006.201.22:28:21.49#ibcon#read 3, iclass 39, count 0 2006.201.22:28:21.49#ibcon#about to read 4, iclass 39, count 0 2006.201.22:28:21.49#ibcon#read 4, iclass 39, count 0 2006.201.22:28:21.49#ibcon#about to read 5, iclass 39, count 0 2006.201.22:28:21.49#ibcon#read 5, iclass 39, count 0 2006.201.22:28:21.49#ibcon#about to read 6, iclass 39, count 0 2006.201.22:28:21.49#ibcon#read 6, iclass 39, count 0 2006.201.22:28:21.49#ibcon#end of sib2, iclass 39, count 0 2006.201.22:28:21.49#ibcon#*mode == 0, iclass 39, count 0 2006.201.22:28:21.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.22:28:21.49#ibcon#[27=BW32\r\n] 2006.201.22:28:21.49#ibcon#*before write, iclass 39, count 0 2006.201.22:28:21.49#ibcon#enter sib2, iclass 39, count 0 2006.201.22:28:21.49#ibcon#flushed, iclass 39, count 0 2006.201.22:28:21.49#ibcon#about to write, iclass 39, count 0 2006.201.22:28:21.49#ibcon#wrote, iclass 39, count 0 2006.201.22:28:21.49#ibcon#about to read 3, iclass 39, count 0 2006.201.22:28:21.52#ibcon#read 3, iclass 39, count 0 2006.201.22:28:21.52#ibcon#about to read 4, iclass 39, count 0 2006.201.22:28:21.52#ibcon#read 4, iclass 39, count 0 2006.201.22:28:21.52#ibcon#about to read 5, iclass 39, count 0 2006.201.22:28:21.52#ibcon#read 5, iclass 39, count 0 2006.201.22:28:21.52#ibcon#about to read 6, iclass 39, count 0 2006.201.22:28:21.52#ibcon#read 6, iclass 39, count 0 2006.201.22:28:21.52#ibcon#end of sib2, iclass 39, count 0 2006.201.22:28:21.52#ibcon#*after write, iclass 39, count 0 2006.201.22:28:21.52#ibcon#*before return 0, iclass 39, count 0 2006.201.22:28:21.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:28:21.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:28:21.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.22:28:21.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.22:28:21.52$setupk4/ifdk4 2006.201.22:28:21.52$ifdk4/lo= 2006.201.22:28:21.52$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.22:28:21.52$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.22:28:21.52$ifdk4/patch= 2006.201.22:28:21.52$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.22:28:21.52$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.22:28:21.52$setupk4/!*+20s 2006.201.22:28:26.34#abcon#<5=/04 1.9 3.6 20.071001001.5\r\n> 2006.201.22:28:26.36#abcon#{5=INTERFACE CLEAR} 2006.201.22:28:26.42#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:28:27.14#trakl#Source acquired 2006.201.22:28:27.14#flagr#flagr/antenna,acquired 2006.201.22:28:35.98$setupk4/"tpicd 2006.201.22:28:35.98$setupk4/echo=off 2006.201.22:28:35.98$setupk4/xlog=off 2006.201.22:28:35.98:!2006.201.22:36:03 2006.201.22:36:03.00:preob 2006.201.22:36:04.14/onsource/TRACKING 2006.201.22:36:04.14:!2006.201.22:36:13 2006.201.22:36:13.00:"tape 2006.201.22:36:13.00:"st=record 2006.201.22:36:13.00:data_valid=on 2006.201.22:36:13.00:midob 2006.201.22:36:13.14/onsource/TRACKING 2006.201.22:36:13.14/wx/20.07,1001.5,100 2006.201.22:36:13.34/cable/+6.4822E-03 2006.201.22:36:14.43/va/01,08,usb,yes,53,57 2006.201.22:36:14.43/va/02,07,usb,yes,57,59 2006.201.22:36:14.43/va/03,08,usb,yes,52,54 2006.201.22:36:14.43/va/04,07,usb,yes,59,62 2006.201.22:36:14.43/va/05,04,usb,yes,53,54 2006.201.22:36:14.43/va/06,05,usb,yes,53,53 2006.201.22:36:14.43/va/07,05,usb,yes,52,54 2006.201.22:36:14.43/va/08,04,usb,yes,52,61 2006.201.22:36:14.66/valo/01,524.99,yes,locked 2006.201.22:36:14.66/valo/02,534.99,yes,locked 2006.201.22:36:14.66/valo/03,564.99,yes,locked 2006.201.22:36:14.66/valo/04,624.99,yes,locked 2006.201.22:36:14.66/valo/05,734.99,yes,locked 2006.201.22:36:14.66/valo/06,814.99,yes,locked 2006.201.22:36:14.66/valo/07,864.99,yes,locked 2006.201.22:36:14.66/valo/08,884.99,yes,locked 2006.201.22:36:15.75/vb/01,04,usb,yes,33,30 2006.201.22:36:15.75/vb/02,05,usb,yes,31,30 2006.201.22:36:15.75/vb/03,04,usb,yes,32,35 2006.201.22:36:15.75/vb/04,05,usb,yes,32,31 2006.201.22:36:15.75/vb/05,04,usb,yes,29,31 2006.201.22:36:15.75/vb/06,04,usb,yes,33,29 2006.201.22:36:15.75/vb/07,04,usb,yes,33,33 2006.201.22:36:15.75/vb/08,04,usb,yes,31,34 2006.201.22:36:15.98/vblo/01,629.99,yes,locked 2006.201.22:36:15.98/vblo/02,634.99,yes,locked 2006.201.22:36:15.98/vblo/03,649.99,yes,locked 2006.201.22:36:15.98/vblo/04,679.99,yes,locked 2006.201.22:36:15.98/vblo/05,709.99,yes,locked 2006.201.22:36:15.98/vblo/06,719.99,yes,locked 2006.201.22:36:15.98/vblo/07,734.99,yes,locked 2006.201.22:36:15.98/vblo/08,744.99,yes,locked 2006.201.22:36:16.13/vabw/8 2006.201.22:36:16.28/vbbw/8 2006.201.22:36:16.37/xfe/off,on,16.2 2006.201.22:36:16.76/ifatt/23,28,28,28 2006.201.22:36:17.07/fmout-gps/S +4.55E-07 2006.201.22:36:17.11:!2006.201.22:36:53 2006.201.22:36:53.00:data_valid=off 2006.201.22:36:53.00:"et 2006.201.22:36:53.00:!+3s 2006.201.22:36:56.02:"tape 2006.201.22:36:56.02:postob 2006.201.22:36:56.22/cable/+6.4823E-03 2006.201.22:36:56.22/wx/20.07,1001.5,100 2006.201.22:36:56.28/fmout-gps/S +4.54E-07 2006.201.22:36:56.28:scan_name=201-2238,jd0607,70 2006.201.22:36:56.28:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.201.22:36:58.14#flagr#flagr/antenna,new-source 2006.201.22:36:58.14:checkk5 2006.201.22:36:58.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.22:36:58.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.22:36:59.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.22:36:59.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.22:37:00.01/chk_obsdata//k5ts1/T2012236??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.22:37:00.38/chk_obsdata//k5ts2/T2012236??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.22:37:00.74/chk_obsdata//k5ts3/T2012236??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.22:37:01.11/chk_obsdata//k5ts4/T2012236??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.22:37:01.79/k5log//k5ts1_log_newline 2006.201.22:37:02.47/k5log//k5ts2_log_newline 2006.201.22:37:03.16/k5log//k5ts3_log_newline 2006.201.22:37:03.85/k5log//k5ts4_log_newline 2006.201.22:37:03.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.22:37:03.87:setupk4=1 2006.201.22:37:03.87$setupk4/echo=on 2006.201.22:37:03.87$setupk4/pcalon 2006.201.22:37:03.87$pcalon/"no phase cal control is implemented here 2006.201.22:37:03.87$setupk4/"tpicd=stop 2006.201.22:37:03.87$setupk4/"rec=synch_on 2006.201.22:37:03.87$setupk4/"rec_mode=128 2006.201.22:37:03.87$setupk4/!* 2006.201.22:37:03.87$setupk4/recpk4 2006.201.22:37:03.87$recpk4/recpatch= 2006.201.22:37:03.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.22:37:03.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.22:37:03.88$setupk4/vck44 2006.201.22:37:03.88$vck44/valo=1,524.99 2006.201.22:37:03.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.22:37:03.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.22:37:03.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:03.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:03.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:03.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:03.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.22:37:03.88#ibcon#first serial, iclass 32, count 0 2006.201.22:37:03.88#ibcon#enter sib2, iclass 32, count 0 2006.201.22:37:03.88#ibcon#flushed, iclass 32, count 0 2006.201.22:37:03.88#ibcon#about to write, iclass 32, count 0 2006.201.22:37:03.88#ibcon#wrote, iclass 32, count 0 2006.201.22:37:03.88#ibcon#about to read 3, iclass 32, count 0 2006.201.22:37:03.91#ibcon#read 3, iclass 32, count 0 2006.201.22:37:03.91#ibcon#about to read 4, iclass 32, count 0 2006.201.22:37:03.91#ibcon#read 4, iclass 32, count 0 2006.201.22:37:03.91#ibcon#about to read 5, iclass 32, count 0 2006.201.22:37:03.91#ibcon#read 5, iclass 32, count 0 2006.201.22:37:03.91#ibcon#about to read 6, iclass 32, count 0 2006.201.22:37:03.91#ibcon#read 6, iclass 32, count 0 2006.201.22:37:03.91#ibcon#end of sib2, iclass 32, count 0 2006.201.22:37:03.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.22:37:03.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.22:37:03.91#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.22:37:03.91#ibcon#*before write, iclass 32, count 0 2006.201.22:37:03.91#ibcon#enter sib2, iclass 32, count 0 2006.201.22:37:03.91#ibcon#flushed, iclass 32, count 0 2006.201.22:37:03.91#ibcon#about to write, iclass 32, count 0 2006.201.22:37:03.91#ibcon#wrote, iclass 32, count 0 2006.201.22:37:03.91#ibcon#about to read 3, iclass 32, count 0 2006.201.22:37:03.96#ibcon#read 3, iclass 32, count 0 2006.201.22:37:03.96#ibcon#about to read 4, iclass 32, count 0 2006.201.22:37:03.96#ibcon#read 4, iclass 32, count 0 2006.201.22:37:03.96#ibcon#about to read 5, iclass 32, count 0 2006.201.22:37:03.96#ibcon#read 5, iclass 32, count 0 2006.201.22:37:03.96#ibcon#about to read 6, iclass 32, count 0 2006.201.22:37:03.96#ibcon#read 6, iclass 32, count 0 2006.201.22:37:03.96#ibcon#end of sib2, iclass 32, count 0 2006.201.22:37:03.96#ibcon#*after write, iclass 32, count 0 2006.201.22:37:03.96#ibcon#*before return 0, iclass 32, count 0 2006.201.22:37:03.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:03.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:03.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.22:37:03.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.22:37:03.96$vck44/va=1,8 2006.201.22:37:03.96#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.22:37:03.96#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.22:37:03.96#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:03.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:03.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:03.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:03.96#ibcon#enter wrdev, iclass 34, count 2 2006.201.22:37:03.96#ibcon#first serial, iclass 34, count 2 2006.201.22:37:03.96#ibcon#enter sib2, iclass 34, count 2 2006.201.22:37:03.96#ibcon#flushed, iclass 34, count 2 2006.201.22:37:03.96#ibcon#about to write, iclass 34, count 2 2006.201.22:37:03.96#ibcon#wrote, iclass 34, count 2 2006.201.22:37:03.96#ibcon#about to read 3, iclass 34, count 2 2006.201.22:37:03.98#ibcon#read 3, iclass 34, count 2 2006.201.22:37:03.98#ibcon#about to read 4, iclass 34, count 2 2006.201.22:37:03.98#ibcon#read 4, iclass 34, count 2 2006.201.22:37:03.98#ibcon#about to read 5, iclass 34, count 2 2006.201.22:37:03.98#ibcon#read 5, iclass 34, count 2 2006.201.22:37:03.98#ibcon#about to read 6, iclass 34, count 2 2006.201.22:37:03.98#ibcon#read 6, iclass 34, count 2 2006.201.22:37:03.98#ibcon#end of sib2, iclass 34, count 2 2006.201.22:37:03.98#ibcon#*mode == 0, iclass 34, count 2 2006.201.22:37:03.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.22:37:03.98#ibcon#[25=AT01-08\r\n] 2006.201.22:37:03.98#ibcon#*before write, iclass 34, count 2 2006.201.22:37:03.98#ibcon#enter sib2, iclass 34, count 2 2006.201.22:37:03.98#ibcon#flushed, iclass 34, count 2 2006.201.22:37:03.98#ibcon#about to write, iclass 34, count 2 2006.201.22:37:03.98#ibcon#wrote, iclass 34, count 2 2006.201.22:37:03.98#ibcon#about to read 3, iclass 34, count 2 2006.201.22:37:04.01#ibcon#read 3, iclass 34, count 2 2006.201.22:37:04.01#ibcon#about to read 4, iclass 34, count 2 2006.201.22:37:04.01#ibcon#read 4, iclass 34, count 2 2006.201.22:37:04.01#ibcon#about to read 5, iclass 34, count 2 2006.201.22:37:04.01#ibcon#read 5, iclass 34, count 2 2006.201.22:37:04.01#ibcon#about to read 6, iclass 34, count 2 2006.201.22:37:04.01#ibcon#read 6, iclass 34, count 2 2006.201.22:37:04.01#ibcon#end of sib2, iclass 34, count 2 2006.201.22:37:04.01#ibcon#*after write, iclass 34, count 2 2006.201.22:37:04.01#ibcon#*before return 0, iclass 34, count 2 2006.201.22:37:04.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:04.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:04.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.22:37:04.01#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:04.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:04.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:04.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:04.13#ibcon#enter wrdev, iclass 34, count 0 2006.201.22:37:04.13#ibcon#first serial, iclass 34, count 0 2006.201.22:37:04.13#ibcon#enter sib2, iclass 34, count 0 2006.201.22:37:04.13#ibcon#flushed, iclass 34, count 0 2006.201.22:37:04.13#ibcon#about to write, iclass 34, count 0 2006.201.22:37:04.13#ibcon#wrote, iclass 34, count 0 2006.201.22:37:04.13#ibcon#about to read 3, iclass 34, count 0 2006.201.22:37:04.15#ibcon#read 3, iclass 34, count 0 2006.201.22:37:04.15#ibcon#about to read 4, iclass 34, count 0 2006.201.22:37:04.15#ibcon#read 4, iclass 34, count 0 2006.201.22:37:04.15#ibcon#about to read 5, iclass 34, count 0 2006.201.22:37:04.15#ibcon#read 5, iclass 34, count 0 2006.201.22:37:04.15#ibcon#about to read 6, iclass 34, count 0 2006.201.22:37:04.15#ibcon#read 6, iclass 34, count 0 2006.201.22:37:04.15#ibcon#end of sib2, iclass 34, count 0 2006.201.22:37:04.15#ibcon#*mode == 0, iclass 34, count 0 2006.201.22:37:04.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.22:37:04.15#ibcon#[25=USB\r\n] 2006.201.22:37:04.15#ibcon#*before write, iclass 34, count 0 2006.201.22:37:04.15#ibcon#enter sib2, iclass 34, count 0 2006.201.22:37:04.15#ibcon#flushed, iclass 34, count 0 2006.201.22:37:04.15#ibcon#about to write, iclass 34, count 0 2006.201.22:37:04.15#ibcon#wrote, iclass 34, count 0 2006.201.22:37:04.15#ibcon#about to read 3, iclass 34, count 0 2006.201.22:37:04.18#ibcon#read 3, iclass 34, count 0 2006.201.22:37:04.18#ibcon#about to read 4, iclass 34, count 0 2006.201.22:37:04.18#ibcon#read 4, iclass 34, count 0 2006.201.22:37:04.18#ibcon#about to read 5, iclass 34, count 0 2006.201.22:37:04.18#ibcon#read 5, iclass 34, count 0 2006.201.22:37:04.18#ibcon#about to read 6, iclass 34, count 0 2006.201.22:37:04.18#ibcon#read 6, iclass 34, count 0 2006.201.22:37:04.18#ibcon#end of sib2, iclass 34, count 0 2006.201.22:37:04.18#ibcon#*after write, iclass 34, count 0 2006.201.22:37:04.18#ibcon#*before return 0, iclass 34, count 0 2006.201.22:37:04.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:04.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:04.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.22:37:04.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.22:37:04.18$vck44/valo=2,534.99 2006.201.22:37:04.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.22:37:04.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.22:37:04.18#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:04.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:04.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:04.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:04.18#ibcon#enter wrdev, iclass 36, count 0 2006.201.22:37:04.18#ibcon#first serial, iclass 36, count 0 2006.201.22:37:04.18#ibcon#enter sib2, iclass 36, count 0 2006.201.22:37:04.18#ibcon#flushed, iclass 36, count 0 2006.201.22:37:04.18#ibcon#about to write, iclass 36, count 0 2006.201.22:37:04.18#ibcon#wrote, iclass 36, count 0 2006.201.22:37:04.18#ibcon#about to read 3, iclass 36, count 0 2006.201.22:37:04.20#ibcon#read 3, iclass 36, count 0 2006.201.22:37:04.20#ibcon#about to read 4, iclass 36, count 0 2006.201.22:37:04.20#ibcon#read 4, iclass 36, count 0 2006.201.22:37:04.20#ibcon#about to read 5, iclass 36, count 0 2006.201.22:37:04.20#ibcon#read 5, iclass 36, count 0 2006.201.22:37:04.20#ibcon#about to read 6, iclass 36, count 0 2006.201.22:37:04.20#ibcon#read 6, iclass 36, count 0 2006.201.22:37:04.20#ibcon#end of sib2, iclass 36, count 0 2006.201.22:37:04.20#ibcon#*mode == 0, iclass 36, count 0 2006.201.22:37:04.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.22:37:04.20#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.22:37:04.20#ibcon#*before write, iclass 36, count 0 2006.201.22:37:04.20#ibcon#enter sib2, iclass 36, count 0 2006.201.22:37:04.20#ibcon#flushed, iclass 36, count 0 2006.201.22:37:04.20#ibcon#about to write, iclass 36, count 0 2006.201.22:37:04.20#ibcon#wrote, iclass 36, count 0 2006.201.22:37:04.20#ibcon#about to read 3, iclass 36, count 0 2006.201.22:37:04.24#ibcon#read 3, iclass 36, count 0 2006.201.22:37:04.24#ibcon#about to read 4, iclass 36, count 0 2006.201.22:37:04.24#ibcon#read 4, iclass 36, count 0 2006.201.22:37:04.24#ibcon#about to read 5, iclass 36, count 0 2006.201.22:37:04.24#ibcon#read 5, iclass 36, count 0 2006.201.22:37:04.24#ibcon#about to read 6, iclass 36, count 0 2006.201.22:37:04.24#ibcon#read 6, iclass 36, count 0 2006.201.22:37:04.24#ibcon#end of sib2, iclass 36, count 0 2006.201.22:37:04.24#ibcon#*after write, iclass 36, count 0 2006.201.22:37:04.24#ibcon#*before return 0, iclass 36, count 0 2006.201.22:37:04.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:04.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:04.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.22:37:04.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.22:37:04.24$vck44/va=2,7 2006.201.22:37:04.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.22:37:04.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.22:37:04.24#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:04.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:04.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:04.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:04.30#ibcon#enter wrdev, iclass 38, count 2 2006.201.22:37:04.30#ibcon#first serial, iclass 38, count 2 2006.201.22:37:04.30#ibcon#enter sib2, iclass 38, count 2 2006.201.22:37:04.30#ibcon#flushed, iclass 38, count 2 2006.201.22:37:04.30#ibcon#about to write, iclass 38, count 2 2006.201.22:37:04.30#ibcon#wrote, iclass 38, count 2 2006.201.22:37:04.30#ibcon#about to read 3, iclass 38, count 2 2006.201.22:37:04.32#ibcon#read 3, iclass 38, count 2 2006.201.22:37:04.32#ibcon#about to read 4, iclass 38, count 2 2006.201.22:37:04.32#ibcon#read 4, iclass 38, count 2 2006.201.22:37:04.32#ibcon#about to read 5, iclass 38, count 2 2006.201.22:37:04.32#ibcon#read 5, iclass 38, count 2 2006.201.22:37:04.32#ibcon#about to read 6, iclass 38, count 2 2006.201.22:37:04.32#ibcon#read 6, iclass 38, count 2 2006.201.22:37:04.32#ibcon#end of sib2, iclass 38, count 2 2006.201.22:37:04.32#ibcon#*mode == 0, iclass 38, count 2 2006.201.22:37:04.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.22:37:04.32#ibcon#[25=AT02-07\r\n] 2006.201.22:37:04.32#ibcon#*before write, iclass 38, count 2 2006.201.22:37:04.32#ibcon#enter sib2, iclass 38, count 2 2006.201.22:37:04.32#ibcon#flushed, iclass 38, count 2 2006.201.22:37:04.32#ibcon#about to write, iclass 38, count 2 2006.201.22:37:04.32#ibcon#wrote, iclass 38, count 2 2006.201.22:37:04.32#ibcon#about to read 3, iclass 38, count 2 2006.201.22:37:04.35#ibcon#read 3, iclass 38, count 2 2006.201.22:37:04.35#ibcon#about to read 4, iclass 38, count 2 2006.201.22:37:04.35#ibcon#read 4, iclass 38, count 2 2006.201.22:37:04.35#ibcon#about to read 5, iclass 38, count 2 2006.201.22:37:04.35#ibcon#read 5, iclass 38, count 2 2006.201.22:37:04.35#ibcon#about to read 6, iclass 38, count 2 2006.201.22:37:04.35#ibcon#read 6, iclass 38, count 2 2006.201.22:37:04.35#ibcon#end of sib2, iclass 38, count 2 2006.201.22:37:04.35#ibcon#*after write, iclass 38, count 2 2006.201.22:37:04.35#ibcon#*before return 0, iclass 38, count 2 2006.201.22:37:04.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:04.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:04.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.22:37:04.35#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:04.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:04.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:04.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:04.47#ibcon#enter wrdev, iclass 38, count 0 2006.201.22:37:04.47#ibcon#first serial, iclass 38, count 0 2006.201.22:37:04.47#ibcon#enter sib2, iclass 38, count 0 2006.201.22:37:04.47#ibcon#flushed, iclass 38, count 0 2006.201.22:37:04.47#ibcon#about to write, iclass 38, count 0 2006.201.22:37:04.47#ibcon#wrote, iclass 38, count 0 2006.201.22:37:04.47#ibcon#about to read 3, iclass 38, count 0 2006.201.22:37:04.49#ibcon#read 3, iclass 38, count 0 2006.201.22:37:04.49#ibcon#about to read 4, iclass 38, count 0 2006.201.22:37:04.49#ibcon#read 4, iclass 38, count 0 2006.201.22:37:04.49#ibcon#about to read 5, iclass 38, count 0 2006.201.22:37:04.49#ibcon#read 5, iclass 38, count 0 2006.201.22:37:04.49#ibcon#about to read 6, iclass 38, count 0 2006.201.22:37:04.49#ibcon#read 6, iclass 38, count 0 2006.201.22:37:04.49#ibcon#end of sib2, iclass 38, count 0 2006.201.22:37:04.49#ibcon#*mode == 0, iclass 38, count 0 2006.201.22:37:04.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.22:37:04.49#ibcon#[25=USB\r\n] 2006.201.22:37:04.49#ibcon#*before write, iclass 38, count 0 2006.201.22:37:04.49#ibcon#enter sib2, iclass 38, count 0 2006.201.22:37:04.49#ibcon#flushed, iclass 38, count 0 2006.201.22:37:04.49#ibcon#about to write, iclass 38, count 0 2006.201.22:37:04.49#ibcon#wrote, iclass 38, count 0 2006.201.22:37:04.49#ibcon#about to read 3, iclass 38, count 0 2006.201.22:37:04.52#ibcon#read 3, iclass 38, count 0 2006.201.22:37:04.52#ibcon#about to read 4, iclass 38, count 0 2006.201.22:37:04.52#ibcon#read 4, iclass 38, count 0 2006.201.22:37:04.52#ibcon#about to read 5, iclass 38, count 0 2006.201.22:37:04.52#ibcon#read 5, iclass 38, count 0 2006.201.22:37:04.52#ibcon#about to read 6, iclass 38, count 0 2006.201.22:37:04.52#ibcon#read 6, iclass 38, count 0 2006.201.22:37:04.52#ibcon#end of sib2, iclass 38, count 0 2006.201.22:37:04.52#ibcon#*after write, iclass 38, count 0 2006.201.22:37:04.52#ibcon#*before return 0, iclass 38, count 0 2006.201.22:37:04.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:04.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:04.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.22:37:04.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.22:37:04.52$vck44/valo=3,564.99 2006.201.22:37:04.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.22:37:04.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.22:37:04.52#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:04.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:04.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:04.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:04.52#ibcon#enter wrdev, iclass 40, count 0 2006.201.22:37:04.52#ibcon#first serial, iclass 40, count 0 2006.201.22:37:04.52#ibcon#enter sib2, iclass 40, count 0 2006.201.22:37:04.52#ibcon#flushed, iclass 40, count 0 2006.201.22:37:04.52#ibcon#about to write, iclass 40, count 0 2006.201.22:37:04.52#ibcon#wrote, iclass 40, count 0 2006.201.22:37:04.52#ibcon#about to read 3, iclass 40, count 0 2006.201.22:37:04.54#ibcon#read 3, iclass 40, count 0 2006.201.22:37:04.54#ibcon#about to read 4, iclass 40, count 0 2006.201.22:37:04.54#ibcon#read 4, iclass 40, count 0 2006.201.22:37:04.54#ibcon#about to read 5, iclass 40, count 0 2006.201.22:37:04.54#ibcon#read 5, iclass 40, count 0 2006.201.22:37:04.54#ibcon#about to read 6, iclass 40, count 0 2006.201.22:37:04.54#ibcon#read 6, iclass 40, count 0 2006.201.22:37:04.54#ibcon#end of sib2, iclass 40, count 0 2006.201.22:37:04.54#ibcon#*mode == 0, iclass 40, count 0 2006.201.22:37:04.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.22:37:04.54#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.22:37:04.54#ibcon#*before write, iclass 40, count 0 2006.201.22:37:04.54#ibcon#enter sib2, iclass 40, count 0 2006.201.22:37:04.54#ibcon#flushed, iclass 40, count 0 2006.201.22:37:04.54#ibcon#about to write, iclass 40, count 0 2006.201.22:37:04.54#ibcon#wrote, iclass 40, count 0 2006.201.22:37:04.54#ibcon#about to read 3, iclass 40, count 0 2006.201.22:37:04.58#ibcon#read 3, iclass 40, count 0 2006.201.22:37:04.58#ibcon#about to read 4, iclass 40, count 0 2006.201.22:37:04.58#ibcon#read 4, iclass 40, count 0 2006.201.22:37:04.58#ibcon#about to read 5, iclass 40, count 0 2006.201.22:37:04.58#ibcon#read 5, iclass 40, count 0 2006.201.22:37:04.58#ibcon#about to read 6, iclass 40, count 0 2006.201.22:37:04.58#ibcon#read 6, iclass 40, count 0 2006.201.22:37:04.58#ibcon#end of sib2, iclass 40, count 0 2006.201.22:37:04.58#ibcon#*after write, iclass 40, count 0 2006.201.22:37:04.58#ibcon#*before return 0, iclass 40, count 0 2006.201.22:37:04.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:04.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:04.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.22:37:04.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.22:37:04.58$vck44/va=3,8 2006.201.22:37:04.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.22:37:04.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.22:37:04.58#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:04.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:04.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:04.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:04.64#ibcon#enter wrdev, iclass 4, count 2 2006.201.22:37:04.64#ibcon#first serial, iclass 4, count 2 2006.201.22:37:04.64#ibcon#enter sib2, iclass 4, count 2 2006.201.22:37:04.64#ibcon#flushed, iclass 4, count 2 2006.201.22:37:04.64#ibcon#about to write, iclass 4, count 2 2006.201.22:37:04.64#ibcon#wrote, iclass 4, count 2 2006.201.22:37:04.64#ibcon#about to read 3, iclass 4, count 2 2006.201.22:37:04.66#ibcon#read 3, iclass 4, count 2 2006.201.22:37:04.66#ibcon#about to read 4, iclass 4, count 2 2006.201.22:37:04.66#ibcon#read 4, iclass 4, count 2 2006.201.22:37:04.66#ibcon#about to read 5, iclass 4, count 2 2006.201.22:37:04.66#ibcon#read 5, iclass 4, count 2 2006.201.22:37:04.66#ibcon#about to read 6, iclass 4, count 2 2006.201.22:37:04.66#ibcon#read 6, iclass 4, count 2 2006.201.22:37:04.66#ibcon#end of sib2, iclass 4, count 2 2006.201.22:37:04.66#ibcon#*mode == 0, iclass 4, count 2 2006.201.22:37:04.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.22:37:04.66#ibcon#[25=AT03-08\r\n] 2006.201.22:37:04.66#ibcon#*before write, iclass 4, count 2 2006.201.22:37:04.66#ibcon#enter sib2, iclass 4, count 2 2006.201.22:37:04.66#ibcon#flushed, iclass 4, count 2 2006.201.22:37:04.66#ibcon#about to write, iclass 4, count 2 2006.201.22:37:04.66#ibcon#wrote, iclass 4, count 2 2006.201.22:37:04.66#ibcon#about to read 3, iclass 4, count 2 2006.201.22:37:04.69#ibcon#read 3, iclass 4, count 2 2006.201.22:37:04.69#ibcon#about to read 4, iclass 4, count 2 2006.201.22:37:04.69#ibcon#read 4, iclass 4, count 2 2006.201.22:37:04.69#ibcon#about to read 5, iclass 4, count 2 2006.201.22:37:04.69#ibcon#read 5, iclass 4, count 2 2006.201.22:37:04.69#ibcon#about to read 6, iclass 4, count 2 2006.201.22:37:04.69#ibcon#read 6, iclass 4, count 2 2006.201.22:37:04.69#ibcon#end of sib2, iclass 4, count 2 2006.201.22:37:04.69#ibcon#*after write, iclass 4, count 2 2006.201.22:37:04.69#ibcon#*before return 0, iclass 4, count 2 2006.201.22:37:04.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:04.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:04.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.22:37:04.69#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:04.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:04.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:04.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:04.81#ibcon#enter wrdev, iclass 4, count 0 2006.201.22:37:04.81#ibcon#first serial, iclass 4, count 0 2006.201.22:37:04.81#ibcon#enter sib2, iclass 4, count 0 2006.201.22:37:04.81#ibcon#flushed, iclass 4, count 0 2006.201.22:37:04.81#ibcon#about to write, iclass 4, count 0 2006.201.22:37:04.81#ibcon#wrote, iclass 4, count 0 2006.201.22:37:04.81#ibcon#about to read 3, iclass 4, count 0 2006.201.22:37:04.83#ibcon#read 3, iclass 4, count 0 2006.201.22:37:04.83#ibcon#about to read 4, iclass 4, count 0 2006.201.22:37:04.83#ibcon#read 4, iclass 4, count 0 2006.201.22:37:04.83#ibcon#about to read 5, iclass 4, count 0 2006.201.22:37:04.83#ibcon#read 5, iclass 4, count 0 2006.201.22:37:04.83#ibcon#about to read 6, iclass 4, count 0 2006.201.22:37:04.83#ibcon#read 6, iclass 4, count 0 2006.201.22:37:04.83#ibcon#end of sib2, iclass 4, count 0 2006.201.22:37:04.83#ibcon#*mode == 0, iclass 4, count 0 2006.201.22:37:04.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.22:37:04.83#ibcon#[25=USB\r\n] 2006.201.22:37:04.83#ibcon#*before write, iclass 4, count 0 2006.201.22:37:04.83#ibcon#enter sib2, iclass 4, count 0 2006.201.22:37:04.83#ibcon#flushed, iclass 4, count 0 2006.201.22:37:04.83#ibcon#about to write, iclass 4, count 0 2006.201.22:37:04.83#ibcon#wrote, iclass 4, count 0 2006.201.22:37:04.83#ibcon#about to read 3, iclass 4, count 0 2006.201.22:37:04.86#ibcon#read 3, iclass 4, count 0 2006.201.22:37:04.86#ibcon#about to read 4, iclass 4, count 0 2006.201.22:37:04.86#ibcon#read 4, iclass 4, count 0 2006.201.22:37:04.86#ibcon#about to read 5, iclass 4, count 0 2006.201.22:37:04.86#ibcon#read 5, iclass 4, count 0 2006.201.22:37:04.86#ibcon#about to read 6, iclass 4, count 0 2006.201.22:37:04.86#ibcon#read 6, iclass 4, count 0 2006.201.22:37:04.86#ibcon#end of sib2, iclass 4, count 0 2006.201.22:37:04.86#ibcon#*after write, iclass 4, count 0 2006.201.22:37:04.86#ibcon#*before return 0, iclass 4, count 0 2006.201.22:37:04.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:04.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:04.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.22:37:04.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.22:37:04.86$vck44/valo=4,624.99 2006.201.22:37:04.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.22:37:04.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.22:37:04.86#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:04.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:04.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:04.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:04.86#ibcon#enter wrdev, iclass 6, count 0 2006.201.22:37:04.86#ibcon#first serial, iclass 6, count 0 2006.201.22:37:04.86#ibcon#enter sib2, iclass 6, count 0 2006.201.22:37:04.86#ibcon#flushed, iclass 6, count 0 2006.201.22:37:04.86#ibcon#about to write, iclass 6, count 0 2006.201.22:37:04.86#ibcon#wrote, iclass 6, count 0 2006.201.22:37:04.86#ibcon#about to read 3, iclass 6, count 0 2006.201.22:37:04.88#ibcon#read 3, iclass 6, count 0 2006.201.22:37:04.88#ibcon#about to read 4, iclass 6, count 0 2006.201.22:37:04.88#ibcon#read 4, iclass 6, count 0 2006.201.22:37:04.88#ibcon#about to read 5, iclass 6, count 0 2006.201.22:37:04.88#ibcon#read 5, iclass 6, count 0 2006.201.22:37:04.88#ibcon#about to read 6, iclass 6, count 0 2006.201.22:37:04.88#ibcon#read 6, iclass 6, count 0 2006.201.22:37:04.88#ibcon#end of sib2, iclass 6, count 0 2006.201.22:37:04.88#ibcon#*mode == 0, iclass 6, count 0 2006.201.22:37:04.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.22:37:04.88#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.22:37:04.88#ibcon#*before write, iclass 6, count 0 2006.201.22:37:04.88#ibcon#enter sib2, iclass 6, count 0 2006.201.22:37:04.88#ibcon#flushed, iclass 6, count 0 2006.201.22:37:04.88#ibcon#about to write, iclass 6, count 0 2006.201.22:37:04.88#ibcon#wrote, iclass 6, count 0 2006.201.22:37:04.88#ibcon#about to read 3, iclass 6, count 0 2006.201.22:37:04.93#ibcon#read 3, iclass 6, count 0 2006.201.22:37:04.93#ibcon#about to read 4, iclass 6, count 0 2006.201.22:37:04.93#ibcon#read 4, iclass 6, count 0 2006.201.22:37:04.93#ibcon#about to read 5, iclass 6, count 0 2006.201.22:37:04.93#ibcon#read 5, iclass 6, count 0 2006.201.22:37:04.93#ibcon#about to read 6, iclass 6, count 0 2006.201.22:37:04.93#ibcon#read 6, iclass 6, count 0 2006.201.22:37:04.93#ibcon#end of sib2, iclass 6, count 0 2006.201.22:37:04.93#ibcon#*after write, iclass 6, count 0 2006.201.22:37:04.93#ibcon#*before return 0, iclass 6, count 0 2006.201.22:37:04.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:04.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:04.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.22:37:04.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.22:37:04.93$vck44/va=4,7 2006.201.22:37:04.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.22:37:04.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.22:37:04.93#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:04.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:04.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:04.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:04.98#ibcon#enter wrdev, iclass 10, count 2 2006.201.22:37:04.98#ibcon#first serial, iclass 10, count 2 2006.201.22:37:04.98#ibcon#enter sib2, iclass 10, count 2 2006.201.22:37:04.98#ibcon#flushed, iclass 10, count 2 2006.201.22:37:04.98#ibcon#about to write, iclass 10, count 2 2006.201.22:37:04.98#ibcon#wrote, iclass 10, count 2 2006.201.22:37:04.98#ibcon#about to read 3, iclass 10, count 2 2006.201.22:37:05.00#ibcon#read 3, iclass 10, count 2 2006.201.22:37:05.00#ibcon#about to read 4, iclass 10, count 2 2006.201.22:37:05.00#ibcon#read 4, iclass 10, count 2 2006.201.22:37:05.00#ibcon#about to read 5, iclass 10, count 2 2006.201.22:37:05.00#ibcon#read 5, iclass 10, count 2 2006.201.22:37:05.00#ibcon#about to read 6, iclass 10, count 2 2006.201.22:37:05.00#ibcon#read 6, iclass 10, count 2 2006.201.22:37:05.00#ibcon#end of sib2, iclass 10, count 2 2006.201.22:37:05.00#ibcon#*mode == 0, iclass 10, count 2 2006.201.22:37:05.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.22:37:05.00#ibcon#[25=AT04-07\r\n] 2006.201.22:37:05.00#ibcon#*before write, iclass 10, count 2 2006.201.22:37:05.00#ibcon#enter sib2, iclass 10, count 2 2006.201.22:37:05.00#ibcon#flushed, iclass 10, count 2 2006.201.22:37:05.00#ibcon#about to write, iclass 10, count 2 2006.201.22:37:05.00#ibcon#wrote, iclass 10, count 2 2006.201.22:37:05.00#ibcon#about to read 3, iclass 10, count 2 2006.201.22:37:05.03#ibcon#read 3, iclass 10, count 2 2006.201.22:37:05.03#ibcon#about to read 4, iclass 10, count 2 2006.201.22:37:05.03#ibcon#read 4, iclass 10, count 2 2006.201.22:37:05.03#ibcon#about to read 5, iclass 10, count 2 2006.201.22:37:05.03#ibcon#read 5, iclass 10, count 2 2006.201.22:37:05.03#ibcon#about to read 6, iclass 10, count 2 2006.201.22:37:05.03#ibcon#read 6, iclass 10, count 2 2006.201.22:37:05.03#ibcon#end of sib2, iclass 10, count 2 2006.201.22:37:05.03#ibcon#*after write, iclass 10, count 2 2006.201.22:37:05.03#ibcon#*before return 0, iclass 10, count 2 2006.201.22:37:05.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:05.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:05.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.22:37:05.03#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:05.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:05.15#abcon#<5=/04 1.7 2.9 20.071001001.5\r\n> 2006.201.22:37:05.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:05.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:05.15#ibcon#enter wrdev, iclass 10, count 0 2006.201.22:37:05.15#ibcon#first serial, iclass 10, count 0 2006.201.22:37:05.15#ibcon#enter sib2, iclass 10, count 0 2006.201.22:37:05.15#ibcon#flushed, iclass 10, count 0 2006.201.22:37:05.15#ibcon#about to write, iclass 10, count 0 2006.201.22:37:05.15#ibcon#wrote, iclass 10, count 0 2006.201.22:37:05.15#ibcon#about to read 3, iclass 10, count 0 2006.201.22:37:05.17#ibcon#read 3, iclass 10, count 0 2006.201.22:37:05.17#ibcon#about to read 4, iclass 10, count 0 2006.201.22:37:05.17#ibcon#read 4, iclass 10, count 0 2006.201.22:37:05.17#ibcon#about to read 5, iclass 10, count 0 2006.201.22:37:05.17#ibcon#read 5, iclass 10, count 0 2006.201.22:37:05.17#ibcon#about to read 6, iclass 10, count 0 2006.201.22:37:05.17#ibcon#read 6, iclass 10, count 0 2006.201.22:37:05.17#ibcon#end of sib2, iclass 10, count 0 2006.201.22:37:05.17#ibcon#*mode == 0, iclass 10, count 0 2006.201.22:37:05.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.22:37:05.17#ibcon#[25=USB\r\n] 2006.201.22:37:05.17#ibcon#*before write, iclass 10, count 0 2006.201.22:37:05.17#ibcon#enter sib2, iclass 10, count 0 2006.201.22:37:05.17#ibcon#flushed, iclass 10, count 0 2006.201.22:37:05.17#ibcon#about to write, iclass 10, count 0 2006.201.22:37:05.17#ibcon#wrote, iclass 10, count 0 2006.201.22:37:05.17#ibcon#about to read 3, iclass 10, count 0 2006.201.22:37:05.17#abcon#{5=INTERFACE CLEAR} 2006.201.22:37:05.20#ibcon#read 3, iclass 10, count 0 2006.201.22:37:05.20#ibcon#about to read 4, iclass 10, count 0 2006.201.22:37:05.20#ibcon#read 4, iclass 10, count 0 2006.201.22:37:05.20#ibcon#about to read 5, iclass 10, count 0 2006.201.22:37:05.20#ibcon#read 5, iclass 10, count 0 2006.201.22:37:05.20#ibcon#about to read 6, iclass 10, count 0 2006.201.22:37:05.20#ibcon#read 6, iclass 10, count 0 2006.201.22:37:05.20#ibcon#end of sib2, iclass 10, count 0 2006.201.22:37:05.20#ibcon#*after write, iclass 10, count 0 2006.201.22:37:05.20#ibcon#*before return 0, iclass 10, count 0 2006.201.22:37:05.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:05.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:05.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.22:37:05.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.22:37:05.20$vck44/valo=5,734.99 2006.201.22:37:05.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.22:37:05.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.22:37:05.20#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:05.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:37:05.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:37:05.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:37:05.20#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:37:05.20#ibcon#first serial, iclass 15, count 0 2006.201.22:37:05.20#ibcon#enter sib2, iclass 15, count 0 2006.201.22:37:05.20#ibcon#flushed, iclass 15, count 0 2006.201.22:37:05.20#ibcon#about to write, iclass 15, count 0 2006.201.22:37:05.20#ibcon#wrote, iclass 15, count 0 2006.201.22:37:05.20#ibcon#about to read 3, iclass 15, count 0 2006.201.22:37:05.22#ibcon#read 3, iclass 15, count 0 2006.201.22:37:05.22#ibcon#about to read 4, iclass 15, count 0 2006.201.22:37:05.22#ibcon#read 4, iclass 15, count 0 2006.201.22:37:05.22#ibcon#about to read 5, iclass 15, count 0 2006.201.22:37:05.22#ibcon#read 5, iclass 15, count 0 2006.201.22:37:05.22#ibcon#about to read 6, iclass 15, count 0 2006.201.22:37:05.22#ibcon#read 6, iclass 15, count 0 2006.201.22:37:05.22#ibcon#end of sib2, iclass 15, count 0 2006.201.22:37:05.22#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:37:05.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:37:05.22#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.22:37:05.22#ibcon#*before write, iclass 15, count 0 2006.201.22:37:05.22#ibcon#enter sib2, iclass 15, count 0 2006.201.22:37:05.22#ibcon#flushed, iclass 15, count 0 2006.201.22:37:05.22#ibcon#about to write, iclass 15, count 0 2006.201.22:37:05.22#ibcon#wrote, iclass 15, count 0 2006.201.22:37:05.22#ibcon#about to read 3, iclass 15, count 0 2006.201.22:37:05.23#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:37:05.26#ibcon#read 3, iclass 15, count 0 2006.201.22:37:05.26#ibcon#about to read 4, iclass 15, count 0 2006.201.22:37:05.26#ibcon#read 4, iclass 15, count 0 2006.201.22:37:05.26#ibcon#about to read 5, iclass 15, count 0 2006.201.22:37:05.26#ibcon#read 5, iclass 15, count 0 2006.201.22:37:05.26#ibcon#about to read 6, iclass 15, count 0 2006.201.22:37:05.26#ibcon#read 6, iclass 15, count 0 2006.201.22:37:05.26#ibcon#end of sib2, iclass 15, count 0 2006.201.22:37:05.26#ibcon#*after write, iclass 15, count 0 2006.201.22:37:05.26#ibcon#*before return 0, iclass 15, count 0 2006.201.22:37:05.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:37:05.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:37:05.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:37:05.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:37:05.26$vck44/va=5,4 2006.201.22:37:05.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.22:37:05.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.22:37:05.26#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:05.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:05.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:05.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:05.32#ibcon#enter wrdev, iclass 18, count 2 2006.201.22:37:05.32#ibcon#first serial, iclass 18, count 2 2006.201.22:37:05.32#ibcon#enter sib2, iclass 18, count 2 2006.201.22:37:05.32#ibcon#flushed, iclass 18, count 2 2006.201.22:37:05.32#ibcon#about to write, iclass 18, count 2 2006.201.22:37:05.32#ibcon#wrote, iclass 18, count 2 2006.201.22:37:05.32#ibcon#about to read 3, iclass 18, count 2 2006.201.22:37:05.34#ibcon#read 3, iclass 18, count 2 2006.201.22:37:05.34#ibcon#about to read 4, iclass 18, count 2 2006.201.22:37:05.34#ibcon#read 4, iclass 18, count 2 2006.201.22:37:05.34#ibcon#about to read 5, iclass 18, count 2 2006.201.22:37:05.34#ibcon#read 5, iclass 18, count 2 2006.201.22:37:05.34#ibcon#about to read 6, iclass 18, count 2 2006.201.22:37:05.34#ibcon#read 6, iclass 18, count 2 2006.201.22:37:05.34#ibcon#end of sib2, iclass 18, count 2 2006.201.22:37:05.34#ibcon#*mode == 0, iclass 18, count 2 2006.201.22:37:05.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.22:37:05.34#ibcon#[25=AT05-04\r\n] 2006.201.22:37:05.34#ibcon#*before write, iclass 18, count 2 2006.201.22:37:05.34#ibcon#enter sib2, iclass 18, count 2 2006.201.22:37:05.34#ibcon#flushed, iclass 18, count 2 2006.201.22:37:05.34#ibcon#about to write, iclass 18, count 2 2006.201.22:37:05.34#ibcon#wrote, iclass 18, count 2 2006.201.22:37:05.34#ibcon#about to read 3, iclass 18, count 2 2006.201.22:37:05.37#ibcon#read 3, iclass 18, count 2 2006.201.22:37:05.37#ibcon#about to read 4, iclass 18, count 2 2006.201.22:37:05.37#ibcon#read 4, iclass 18, count 2 2006.201.22:37:05.37#ibcon#about to read 5, iclass 18, count 2 2006.201.22:37:05.37#ibcon#read 5, iclass 18, count 2 2006.201.22:37:05.37#ibcon#about to read 6, iclass 18, count 2 2006.201.22:37:05.37#ibcon#read 6, iclass 18, count 2 2006.201.22:37:05.37#ibcon#end of sib2, iclass 18, count 2 2006.201.22:37:05.37#ibcon#*after write, iclass 18, count 2 2006.201.22:37:05.37#ibcon#*before return 0, iclass 18, count 2 2006.201.22:37:05.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:05.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:05.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.22:37:05.37#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:05.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:05.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:05.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:05.49#ibcon#enter wrdev, iclass 18, count 0 2006.201.22:37:05.49#ibcon#first serial, iclass 18, count 0 2006.201.22:37:05.49#ibcon#enter sib2, iclass 18, count 0 2006.201.22:37:05.49#ibcon#flushed, iclass 18, count 0 2006.201.22:37:05.49#ibcon#about to write, iclass 18, count 0 2006.201.22:37:05.49#ibcon#wrote, iclass 18, count 0 2006.201.22:37:05.49#ibcon#about to read 3, iclass 18, count 0 2006.201.22:37:05.51#ibcon#read 3, iclass 18, count 0 2006.201.22:37:05.51#ibcon#about to read 4, iclass 18, count 0 2006.201.22:37:05.51#ibcon#read 4, iclass 18, count 0 2006.201.22:37:05.51#ibcon#about to read 5, iclass 18, count 0 2006.201.22:37:05.51#ibcon#read 5, iclass 18, count 0 2006.201.22:37:05.51#ibcon#about to read 6, iclass 18, count 0 2006.201.22:37:05.51#ibcon#read 6, iclass 18, count 0 2006.201.22:37:05.51#ibcon#end of sib2, iclass 18, count 0 2006.201.22:37:05.51#ibcon#*mode == 0, iclass 18, count 0 2006.201.22:37:05.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.22:37:05.51#ibcon#[25=USB\r\n] 2006.201.22:37:05.51#ibcon#*before write, iclass 18, count 0 2006.201.22:37:05.51#ibcon#enter sib2, iclass 18, count 0 2006.201.22:37:05.51#ibcon#flushed, iclass 18, count 0 2006.201.22:37:05.51#ibcon#about to write, iclass 18, count 0 2006.201.22:37:05.51#ibcon#wrote, iclass 18, count 0 2006.201.22:37:05.51#ibcon#about to read 3, iclass 18, count 0 2006.201.22:37:05.54#ibcon#read 3, iclass 18, count 0 2006.201.22:37:05.54#ibcon#about to read 4, iclass 18, count 0 2006.201.22:37:05.54#ibcon#read 4, iclass 18, count 0 2006.201.22:37:05.54#ibcon#about to read 5, iclass 18, count 0 2006.201.22:37:05.54#ibcon#read 5, iclass 18, count 0 2006.201.22:37:05.54#ibcon#about to read 6, iclass 18, count 0 2006.201.22:37:05.54#ibcon#read 6, iclass 18, count 0 2006.201.22:37:05.54#ibcon#end of sib2, iclass 18, count 0 2006.201.22:37:05.54#ibcon#*after write, iclass 18, count 0 2006.201.22:37:05.54#ibcon#*before return 0, iclass 18, count 0 2006.201.22:37:05.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:05.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:05.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.22:37:05.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.22:37:05.54$vck44/valo=6,814.99 2006.201.22:37:05.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.22:37:05.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.22:37:05.54#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:05.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:05.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:05.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:05.54#ibcon#enter wrdev, iclass 20, count 0 2006.201.22:37:05.54#ibcon#first serial, iclass 20, count 0 2006.201.22:37:05.54#ibcon#enter sib2, iclass 20, count 0 2006.201.22:37:05.54#ibcon#flushed, iclass 20, count 0 2006.201.22:37:05.54#ibcon#about to write, iclass 20, count 0 2006.201.22:37:05.54#ibcon#wrote, iclass 20, count 0 2006.201.22:37:05.54#ibcon#about to read 3, iclass 20, count 0 2006.201.22:37:05.56#ibcon#read 3, iclass 20, count 0 2006.201.22:37:05.56#ibcon#about to read 4, iclass 20, count 0 2006.201.22:37:05.56#ibcon#read 4, iclass 20, count 0 2006.201.22:37:05.56#ibcon#about to read 5, iclass 20, count 0 2006.201.22:37:05.56#ibcon#read 5, iclass 20, count 0 2006.201.22:37:05.56#ibcon#about to read 6, iclass 20, count 0 2006.201.22:37:05.56#ibcon#read 6, iclass 20, count 0 2006.201.22:37:05.56#ibcon#end of sib2, iclass 20, count 0 2006.201.22:37:05.56#ibcon#*mode == 0, iclass 20, count 0 2006.201.22:37:05.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.22:37:05.56#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.22:37:05.56#ibcon#*before write, iclass 20, count 0 2006.201.22:37:05.56#ibcon#enter sib2, iclass 20, count 0 2006.201.22:37:05.56#ibcon#flushed, iclass 20, count 0 2006.201.22:37:05.56#ibcon#about to write, iclass 20, count 0 2006.201.22:37:05.56#ibcon#wrote, iclass 20, count 0 2006.201.22:37:05.56#ibcon#about to read 3, iclass 20, count 0 2006.201.22:37:05.61#ibcon#read 3, iclass 20, count 0 2006.201.22:37:05.61#ibcon#about to read 4, iclass 20, count 0 2006.201.22:37:05.61#ibcon#read 4, iclass 20, count 0 2006.201.22:37:05.61#ibcon#about to read 5, iclass 20, count 0 2006.201.22:37:05.61#ibcon#read 5, iclass 20, count 0 2006.201.22:37:05.61#ibcon#about to read 6, iclass 20, count 0 2006.201.22:37:05.61#ibcon#read 6, iclass 20, count 0 2006.201.22:37:05.61#ibcon#end of sib2, iclass 20, count 0 2006.201.22:37:05.61#ibcon#*after write, iclass 20, count 0 2006.201.22:37:05.61#ibcon#*before return 0, iclass 20, count 0 2006.201.22:37:05.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:05.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:05.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.22:37:05.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.22:37:05.61$vck44/va=6,5 2006.201.22:37:05.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.22:37:05.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.22:37:05.61#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:05.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:05.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:05.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:05.66#ibcon#enter wrdev, iclass 22, count 2 2006.201.22:37:05.66#ibcon#first serial, iclass 22, count 2 2006.201.22:37:05.66#ibcon#enter sib2, iclass 22, count 2 2006.201.22:37:05.66#ibcon#flushed, iclass 22, count 2 2006.201.22:37:05.66#ibcon#about to write, iclass 22, count 2 2006.201.22:37:05.66#ibcon#wrote, iclass 22, count 2 2006.201.22:37:05.66#ibcon#about to read 3, iclass 22, count 2 2006.201.22:37:05.68#ibcon#read 3, iclass 22, count 2 2006.201.22:37:05.68#ibcon#about to read 4, iclass 22, count 2 2006.201.22:37:05.68#ibcon#read 4, iclass 22, count 2 2006.201.22:37:05.68#ibcon#about to read 5, iclass 22, count 2 2006.201.22:37:05.68#ibcon#read 5, iclass 22, count 2 2006.201.22:37:05.68#ibcon#about to read 6, iclass 22, count 2 2006.201.22:37:05.68#ibcon#read 6, iclass 22, count 2 2006.201.22:37:05.68#ibcon#end of sib2, iclass 22, count 2 2006.201.22:37:05.68#ibcon#*mode == 0, iclass 22, count 2 2006.201.22:37:05.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.22:37:05.68#ibcon#[25=AT06-05\r\n] 2006.201.22:37:05.68#ibcon#*before write, iclass 22, count 2 2006.201.22:37:05.68#ibcon#enter sib2, iclass 22, count 2 2006.201.22:37:05.68#ibcon#flushed, iclass 22, count 2 2006.201.22:37:05.68#ibcon#about to write, iclass 22, count 2 2006.201.22:37:05.68#ibcon#wrote, iclass 22, count 2 2006.201.22:37:05.68#ibcon#about to read 3, iclass 22, count 2 2006.201.22:37:05.71#ibcon#read 3, iclass 22, count 2 2006.201.22:37:05.71#ibcon#about to read 4, iclass 22, count 2 2006.201.22:37:05.71#ibcon#read 4, iclass 22, count 2 2006.201.22:37:05.71#ibcon#about to read 5, iclass 22, count 2 2006.201.22:37:05.71#ibcon#read 5, iclass 22, count 2 2006.201.22:37:05.71#ibcon#about to read 6, iclass 22, count 2 2006.201.22:37:05.71#ibcon#read 6, iclass 22, count 2 2006.201.22:37:05.71#ibcon#end of sib2, iclass 22, count 2 2006.201.22:37:05.71#ibcon#*after write, iclass 22, count 2 2006.201.22:37:05.71#ibcon#*before return 0, iclass 22, count 2 2006.201.22:37:05.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:05.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:05.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.22:37:05.71#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:05.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:05.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:05.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:05.83#ibcon#enter wrdev, iclass 22, count 0 2006.201.22:37:05.83#ibcon#first serial, iclass 22, count 0 2006.201.22:37:05.83#ibcon#enter sib2, iclass 22, count 0 2006.201.22:37:05.83#ibcon#flushed, iclass 22, count 0 2006.201.22:37:05.83#ibcon#about to write, iclass 22, count 0 2006.201.22:37:05.83#ibcon#wrote, iclass 22, count 0 2006.201.22:37:05.83#ibcon#about to read 3, iclass 22, count 0 2006.201.22:37:05.85#ibcon#read 3, iclass 22, count 0 2006.201.22:37:05.85#ibcon#about to read 4, iclass 22, count 0 2006.201.22:37:05.85#ibcon#read 4, iclass 22, count 0 2006.201.22:37:05.85#ibcon#about to read 5, iclass 22, count 0 2006.201.22:37:05.85#ibcon#read 5, iclass 22, count 0 2006.201.22:37:05.85#ibcon#about to read 6, iclass 22, count 0 2006.201.22:37:05.85#ibcon#read 6, iclass 22, count 0 2006.201.22:37:05.85#ibcon#end of sib2, iclass 22, count 0 2006.201.22:37:05.85#ibcon#*mode == 0, iclass 22, count 0 2006.201.22:37:05.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.22:37:05.85#ibcon#[25=USB\r\n] 2006.201.22:37:05.85#ibcon#*before write, iclass 22, count 0 2006.201.22:37:05.85#ibcon#enter sib2, iclass 22, count 0 2006.201.22:37:05.85#ibcon#flushed, iclass 22, count 0 2006.201.22:37:05.85#ibcon#about to write, iclass 22, count 0 2006.201.22:37:05.85#ibcon#wrote, iclass 22, count 0 2006.201.22:37:05.85#ibcon#about to read 3, iclass 22, count 0 2006.201.22:37:05.88#ibcon#read 3, iclass 22, count 0 2006.201.22:37:05.88#ibcon#about to read 4, iclass 22, count 0 2006.201.22:37:05.88#ibcon#read 4, iclass 22, count 0 2006.201.22:37:05.88#ibcon#about to read 5, iclass 22, count 0 2006.201.22:37:05.88#ibcon#read 5, iclass 22, count 0 2006.201.22:37:05.88#ibcon#about to read 6, iclass 22, count 0 2006.201.22:37:05.88#ibcon#read 6, iclass 22, count 0 2006.201.22:37:05.88#ibcon#end of sib2, iclass 22, count 0 2006.201.22:37:05.88#ibcon#*after write, iclass 22, count 0 2006.201.22:37:05.88#ibcon#*before return 0, iclass 22, count 0 2006.201.22:37:05.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:05.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:05.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.22:37:05.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.22:37:05.88$vck44/valo=7,864.99 2006.201.22:37:05.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.22:37:05.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.22:37:05.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:05.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:05.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:05.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:05.88#ibcon#enter wrdev, iclass 24, count 0 2006.201.22:37:05.88#ibcon#first serial, iclass 24, count 0 2006.201.22:37:05.88#ibcon#enter sib2, iclass 24, count 0 2006.201.22:37:05.88#ibcon#flushed, iclass 24, count 0 2006.201.22:37:05.88#ibcon#about to write, iclass 24, count 0 2006.201.22:37:05.88#ibcon#wrote, iclass 24, count 0 2006.201.22:37:05.88#ibcon#about to read 3, iclass 24, count 0 2006.201.22:37:05.90#ibcon#read 3, iclass 24, count 0 2006.201.22:37:05.90#ibcon#about to read 4, iclass 24, count 0 2006.201.22:37:05.90#ibcon#read 4, iclass 24, count 0 2006.201.22:37:05.90#ibcon#about to read 5, iclass 24, count 0 2006.201.22:37:05.90#ibcon#read 5, iclass 24, count 0 2006.201.22:37:05.90#ibcon#about to read 6, iclass 24, count 0 2006.201.22:37:05.90#ibcon#read 6, iclass 24, count 0 2006.201.22:37:05.90#ibcon#end of sib2, iclass 24, count 0 2006.201.22:37:05.90#ibcon#*mode == 0, iclass 24, count 0 2006.201.22:37:05.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.22:37:05.90#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.22:37:05.90#ibcon#*before write, iclass 24, count 0 2006.201.22:37:05.90#ibcon#enter sib2, iclass 24, count 0 2006.201.22:37:05.90#ibcon#flushed, iclass 24, count 0 2006.201.22:37:05.90#ibcon#about to write, iclass 24, count 0 2006.201.22:37:05.90#ibcon#wrote, iclass 24, count 0 2006.201.22:37:05.90#ibcon#about to read 3, iclass 24, count 0 2006.201.22:37:05.94#ibcon#read 3, iclass 24, count 0 2006.201.22:37:05.94#ibcon#about to read 4, iclass 24, count 0 2006.201.22:37:05.94#ibcon#read 4, iclass 24, count 0 2006.201.22:37:05.94#ibcon#about to read 5, iclass 24, count 0 2006.201.22:37:05.94#ibcon#read 5, iclass 24, count 0 2006.201.22:37:05.94#ibcon#about to read 6, iclass 24, count 0 2006.201.22:37:05.94#ibcon#read 6, iclass 24, count 0 2006.201.22:37:05.94#ibcon#end of sib2, iclass 24, count 0 2006.201.22:37:05.94#ibcon#*after write, iclass 24, count 0 2006.201.22:37:05.94#ibcon#*before return 0, iclass 24, count 0 2006.201.22:37:05.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:05.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:05.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.22:37:05.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.22:37:05.94$vck44/va=7,5 2006.201.22:37:05.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.22:37:05.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.22:37:05.94#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:05.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:06.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:06.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:06.00#ibcon#enter wrdev, iclass 26, count 2 2006.201.22:37:06.00#ibcon#first serial, iclass 26, count 2 2006.201.22:37:06.00#ibcon#enter sib2, iclass 26, count 2 2006.201.22:37:06.00#ibcon#flushed, iclass 26, count 2 2006.201.22:37:06.00#ibcon#about to write, iclass 26, count 2 2006.201.22:37:06.00#ibcon#wrote, iclass 26, count 2 2006.201.22:37:06.00#ibcon#about to read 3, iclass 26, count 2 2006.201.22:37:06.02#ibcon#read 3, iclass 26, count 2 2006.201.22:37:06.02#ibcon#about to read 4, iclass 26, count 2 2006.201.22:37:06.02#ibcon#read 4, iclass 26, count 2 2006.201.22:37:06.02#ibcon#about to read 5, iclass 26, count 2 2006.201.22:37:06.02#ibcon#read 5, iclass 26, count 2 2006.201.22:37:06.02#ibcon#about to read 6, iclass 26, count 2 2006.201.22:37:06.02#ibcon#read 6, iclass 26, count 2 2006.201.22:37:06.02#ibcon#end of sib2, iclass 26, count 2 2006.201.22:37:06.02#ibcon#*mode == 0, iclass 26, count 2 2006.201.22:37:06.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.22:37:06.02#ibcon#[25=AT07-05\r\n] 2006.201.22:37:06.02#ibcon#*before write, iclass 26, count 2 2006.201.22:37:06.02#ibcon#enter sib2, iclass 26, count 2 2006.201.22:37:06.02#ibcon#flushed, iclass 26, count 2 2006.201.22:37:06.02#ibcon#about to write, iclass 26, count 2 2006.201.22:37:06.02#ibcon#wrote, iclass 26, count 2 2006.201.22:37:06.02#ibcon#about to read 3, iclass 26, count 2 2006.201.22:37:06.05#ibcon#read 3, iclass 26, count 2 2006.201.22:37:06.05#ibcon#about to read 4, iclass 26, count 2 2006.201.22:37:06.05#ibcon#read 4, iclass 26, count 2 2006.201.22:37:06.05#ibcon#about to read 5, iclass 26, count 2 2006.201.22:37:06.05#ibcon#read 5, iclass 26, count 2 2006.201.22:37:06.05#ibcon#about to read 6, iclass 26, count 2 2006.201.22:37:06.05#ibcon#read 6, iclass 26, count 2 2006.201.22:37:06.05#ibcon#end of sib2, iclass 26, count 2 2006.201.22:37:06.05#ibcon#*after write, iclass 26, count 2 2006.201.22:37:06.05#ibcon#*before return 0, iclass 26, count 2 2006.201.22:37:06.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:06.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:06.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.22:37:06.05#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:06.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:06.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:06.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:06.17#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:37:06.17#ibcon#first serial, iclass 26, count 0 2006.201.22:37:06.17#ibcon#enter sib2, iclass 26, count 0 2006.201.22:37:06.17#ibcon#flushed, iclass 26, count 0 2006.201.22:37:06.17#ibcon#about to write, iclass 26, count 0 2006.201.22:37:06.17#ibcon#wrote, iclass 26, count 0 2006.201.22:37:06.17#ibcon#about to read 3, iclass 26, count 0 2006.201.22:37:06.19#ibcon#read 3, iclass 26, count 0 2006.201.22:37:06.19#ibcon#about to read 4, iclass 26, count 0 2006.201.22:37:06.19#ibcon#read 4, iclass 26, count 0 2006.201.22:37:06.19#ibcon#about to read 5, iclass 26, count 0 2006.201.22:37:06.19#ibcon#read 5, iclass 26, count 0 2006.201.22:37:06.19#ibcon#about to read 6, iclass 26, count 0 2006.201.22:37:06.19#ibcon#read 6, iclass 26, count 0 2006.201.22:37:06.19#ibcon#end of sib2, iclass 26, count 0 2006.201.22:37:06.19#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:37:06.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:37:06.19#ibcon#[25=USB\r\n] 2006.201.22:37:06.19#ibcon#*before write, iclass 26, count 0 2006.201.22:37:06.19#ibcon#enter sib2, iclass 26, count 0 2006.201.22:37:06.19#ibcon#flushed, iclass 26, count 0 2006.201.22:37:06.19#ibcon#about to write, iclass 26, count 0 2006.201.22:37:06.19#ibcon#wrote, iclass 26, count 0 2006.201.22:37:06.19#ibcon#about to read 3, iclass 26, count 0 2006.201.22:37:06.22#ibcon#read 3, iclass 26, count 0 2006.201.22:37:06.22#ibcon#about to read 4, iclass 26, count 0 2006.201.22:37:06.22#ibcon#read 4, iclass 26, count 0 2006.201.22:37:06.22#ibcon#about to read 5, iclass 26, count 0 2006.201.22:37:06.22#ibcon#read 5, iclass 26, count 0 2006.201.22:37:06.22#ibcon#about to read 6, iclass 26, count 0 2006.201.22:37:06.22#ibcon#read 6, iclass 26, count 0 2006.201.22:37:06.22#ibcon#end of sib2, iclass 26, count 0 2006.201.22:37:06.22#ibcon#*after write, iclass 26, count 0 2006.201.22:37:06.22#ibcon#*before return 0, iclass 26, count 0 2006.201.22:37:06.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:06.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:06.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:37:06.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:37:06.22$vck44/valo=8,884.99 2006.201.22:37:06.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.22:37:06.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.22:37:06.22#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:06.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:06.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:06.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:06.22#ibcon#enter wrdev, iclass 28, count 0 2006.201.22:37:06.22#ibcon#first serial, iclass 28, count 0 2006.201.22:37:06.22#ibcon#enter sib2, iclass 28, count 0 2006.201.22:37:06.22#ibcon#flushed, iclass 28, count 0 2006.201.22:37:06.22#ibcon#about to write, iclass 28, count 0 2006.201.22:37:06.22#ibcon#wrote, iclass 28, count 0 2006.201.22:37:06.22#ibcon#about to read 3, iclass 28, count 0 2006.201.22:37:06.24#ibcon#read 3, iclass 28, count 0 2006.201.22:37:06.24#ibcon#about to read 4, iclass 28, count 0 2006.201.22:37:06.24#ibcon#read 4, iclass 28, count 0 2006.201.22:37:06.24#ibcon#about to read 5, iclass 28, count 0 2006.201.22:37:06.24#ibcon#read 5, iclass 28, count 0 2006.201.22:37:06.24#ibcon#about to read 6, iclass 28, count 0 2006.201.22:37:06.24#ibcon#read 6, iclass 28, count 0 2006.201.22:37:06.24#ibcon#end of sib2, iclass 28, count 0 2006.201.22:37:06.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.22:37:06.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.22:37:06.24#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.22:37:06.24#ibcon#*before write, iclass 28, count 0 2006.201.22:37:06.24#ibcon#enter sib2, iclass 28, count 0 2006.201.22:37:06.24#ibcon#flushed, iclass 28, count 0 2006.201.22:37:06.24#ibcon#about to write, iclass 28, count 0 2006.201.22:37:06.24#ibcon#wrote, iclass 28, count 0 2006.201.22:37:06.24#ibcon#about to read 3, iclass 28, count 0 2006.201.22:37:06.29#ibcon#read 3, iclass 28, count 0 2006.201.22:37:06.29#ibcon#about to read 4, iclass 28, count 0 2006.201.22:37:06.29#ibcon#read 4, iclass 28, count 0 2006.201.22:37:06.29#ibcon#about to read 5, iclass 28, count 0 2006.201.22:37:06.29#ibcon#read 5, iclass 28, count 0 2006.201.22:37:06.29#ibcon#about to read 6, iclass 28, count 0 2006.201.22:37:06.29#ibcon#read 6, iclass 28, count 0 2006.201.22:37:06.29#ibcon#end of sib2, iclass 28, count 0 2006.201.22:37:06.29#ibcon#*after write, iclass 28, count 0 2006.201.22:37:06.29#ibcon#*before return 0, iclass 28, count 0 2006.201.22:37:06.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:06.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:06.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.22:37:06.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.22:37:06.29$vck44/va=8,4 2006.201.22:37:06.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.22:37:06.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.22:37:06.29#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:06.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:37:06.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:37:06.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:37:06.34#ibcon#enter wrdev, iclass 30, count 2 2006.201.22:37:06.34#ibcon#first serial, iclass 30, count 2 2006.201.22:37:06.34#ibcon#enter sib2, iclass 30, count 2 2006.201.22:37:06.34#ibcon#flushed, iclass 30, count 2 2006.201.22:37:06.34#ibcon#about to write, iclass 30, count 2 2006.201.22:37:06.34#ibcon#wrote, iclass 30, count 2 2006.201.22:37:06.34#ibcon#about to read 3, iclass 30, count 2 2006.201.22:37:06.36#ibcon#read 3, iclass 30, count 2 2006.201.22:37:06.36#ibcon#about to read 4, iclass 30, count 2 2006.201.22:37:06.36#ibcon#read 4, iclass 30, count 2 2006.201.22:37:06.36#ibcon#about to read 5, iclass 30, count 2 2006.201.22:37:06.36#ibcon#read 5, iclass 30, count 2 2006.201.22:37:06.36#ibcon#about to read 6, iclass 30, count 2 2006.201.22:37:06.36#ibcon#read 6, iclass 30, count 2 2006.201.22:37:06.36#ibcon#end of sib2, iclass 30, count 2 2006.201.22:37:06.36#ibcon#*mode == 0, iclass 30, count 2 2006.201.22:37:06.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.22:37:06.36#ibcon#[25=AT08-04\r\n] 2006.201.22:37:06.36#ibcon#*before write, iclass 30, count 2 2006.201.22:37:06.36#ibcon#enter sib2, iclass 30, count 2 2006.201.22:37:06.36#ibcon#flushed, iclass 30, count 2 2006.201.22:37:06.36#ibcon#about to write, iclass 30, count 2 2006.201.22:37:06.36#ibcon#wrote, iclass 30, count 2 2006.201.22:37:06.36#ibcon#about to read 3, iclass 30, count 2 2006.201.22:37:06.39#ibcon#read 3, iclass 30, count 2 2006.201.22:37:06.39#ibcon#about to read 4, iclass 30, count 2 2006.201.22:37:06.39#ibcon#read 4, iclass 30, count 2 2006.201.22:37:06.39#ibcon#about to read 5, iclass 30, count 2 2006.201.22:37:06.39#ibcon#read 5, iclass 30, count 2 2006.201.22:37:06.39#ibcon#about to read 6, iclass 30, count 2 2006.201.22:37:06.39#ibcon#read 6, iclass 30, count 2 2006.201.22:37:06.39#ibcon#end of sib2, iclass 30, count 2 2006.201.22:37:06.39#ibcon#*after write, iclass 30, count 2 2006.201.22:37:06.39#ibcon#*before return 0, iclass 30, count 2 2006.201.22:37:06.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:37:06.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:37:06.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.22:37:06.39#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:06.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:37:06.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:37:06.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:37:06.51#ibcon#enter wrdev, iclass 30, count 0 2006.201.22:37:06.51#ibcon#first serial, iclass 30, count 0 2006.201.22:37:06.51#ibcon#enter sib2, iclass 30, count 0 2006.201.22:37:06.51#ibcon#flushed, iclass 30, count 0 2006.201.22:37:06.51#ibcon#about to write, iclass 30, count 0 2006.201.22:37:06.51#ibcon#wrote, iclass 30, count 0 2006.201.22:37:06.51#ibcon#about to read 3, iclass 30, count 0 2006.201.22:37:06.53#ibcon#read 3, iclass 30, count 0 2006.201.22:37:06.53#ibcon#about to read 4, iclass 30, count 0 2006.201.22:37:06.53#ibcon#read 4, iclass 30, count 0 2006.201.22:37:06.53#ibcon#about to read 5, iclass 30, count 0 2006.201.22:37:06.53#ibcon#read 5, iclass 30, count 0 2006.201.22:37:06.53#ibcon#about to read 6, iclass 30, count 0 2006.201.22:37:06.53#ibcon#read 6, iclass 30, count 0 2006.201.22:37:06.53#ibcon#end of sib2, iclass 30, count 0 2006.201.22:37:06.53#ibcon#*mode == 0, iclass 30, count 0 2006.201.22:37:06.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.22:37:06.53#ibcon#[25=USB\r\n] 2006.201.22:37:06.53#ibcon#*before write, iclass 30, count 0 2006.201.22:37:06.53#ibcon#enter sib2, iclass 30, count 0 2006.201.22:37:06.53#ibcon#flushed, iclass 30, count 0 2006.201.22:37:06.53#ibcon#about to write, iclass 30, count 0 2006.201.22:37:06.53#ibcon#wrote, iclass 30, count 0 2006.201.22:37:06.53#ibcon#about to read 3, iclass 30, count 0 2006.201.22:37:06.56#ibcon#read 3, iclass 30, count 0 2006.201.22:37:06.56#ibcon#about to read 4, iclass 30, count 0 2006.201.22:37:06.56#ibcon#read 4, iclass 30, count 0 2006.201.22:37:06.56#ibcon#about to read 5, iclass 30, count 0 2006.201.22:37:06.56#ibcon#read 5, iclass 30, count 0 2006.201.22:37:06.56#ibcon#about to read 6, iclass 30, count 0 2006.201.22:37:06.56#ibcon#read 6, iclass 30, count 0 2006.201.22:37:06.56#ibcon#end of sib2, iclass 30, count 0 2006.201.22:37:06.56#ibcon#*after write, iclass 30, count 0 2006.201.22:37:06.56#ibcon#*before return 0, iclass 30, count 0 2006.201.22:37:06.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:37:06.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:37:06.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.22:37:06.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.22:37:06.56$vck44/vblo=1,629.99 2006.201.22:37:06.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.22:37:06.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.22:37:06.56#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:06.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:06.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:06.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:06.56#ibcon#enter wrdev, iclass 32, count 0 2006.201.22:37:06.56#ibcon#first serial, iclass 32, count 0 2006.201.22:37:06.56#ibcon#enter sib2, iclass 32, count 0 2006.201.22:37:06.56#ibcon#flushed, iclass 32, count 0 2006.201.22:37:06.56#ibcon#about to write, iclass 32, count 0 2006.201.22:37:06.56#ibcon#wrote, iclass 32, count 0 2006.201.22:37:06.56#ibcon#about to read 3, iclass 32, count 0 2006.201.22:37:06.58#ibcon#read 3, iclass 32, count 0 2006.201.22:37:06.58#ibcon#about to read 4, iclass 32, count 0 2006.201.22:37:06.58#ibcon#read 4, iclass 32, count 0 2006.201.22:37:06.58#ibcon#about to read 5, iclass 32, count 0 2006.201.22:37:06.58#ibcon#read 5, iclass 32, count 0 2006.201.22:37:06.58#ibcon#about to read 6, iclass 32, count 0 2006.201.22:37:06.58#ibcon#read 6, iclass 32, count 0 2006.201.22:37:06.58#ibcon#end of sib2, iclass 32, count 0 2006.201.22:37:06.58#ibcon#*mode == 0, iclass 32, count 0 2006.201.22:37:06.58#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.22:37:06.58#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.22:37:06.58#ibcon#*before write, iclass 32, count 0 2006.201.22:37:06.58#ibcon#enter sib2, iclass 32, count 0 2006.201.22:37:06.58#ibcon#flushed, iclass 32, count 0 2006.201.22:37:06.58#ibcon#about to write, iclass 32, count 0 2006.201.22:37:06.58#ibcon#wrote, iclass 32, count 0 2006.201.22:37:06.58#ibcon#about to read 3, iclass 32, count 0 2006.201.22:37:06.62#ibcon#read 3, iclass 32, count 0 2006.201.22:37:06.62#ibcon#about to read 4, iclass 32, count 0 2006.201.22:37:06.62#ibcon#read 4, iclass 32, count 0 2006.201.22:37:06.62#ibcon#about to read 5, iclass 32, count 0 2006.201.22:37:06.62#ibcon#read 5, iclass 32, count 0 2006.201.22:37:06.62#ibcon#about to read 6, iclass 32, count 0 2006.201.22:37:06.62#ibcon#read 6, iclass 32, count 0 2006.201.22:37:06.62#ibcon#end of sib2, iclass 32, count 0 2006.201.22:37:06.62#ibcon#*after write, iclass 32, count 0 2006.201.22:37:06.62#ibcon#*before return 0, iclass 32, count 0 2006.201.22:37:06.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:06.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:37:06.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.22:37:06.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.22:37:06.62$vck44/vb=1,4 2006.201.22:37:06.62#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.22:37:06.62#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.22:37:06.62#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:06.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:06.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:06.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:06.62#ibcon#enter wrdev, iclass 34, count 2 2006.201.22:37:06.62#ibcon#first serial, iclass 34, count 2 2006.201.22:37:06.62#ibcon#enter sib2, iclass 34, count 2 2006.201.22:37:06.62#ibcon#flushed, iclass 34, count 2 2006.201.22:37:06.62#ibcon#about to write, iclass 34, count 2 2006.201.22:37:06.62#ibcon#wrote, iclass 34, count 2 2006.201.22:37:06.62#ibcon#about to read 3, iclass 34, count 2 2006.201.22:37:06.64#ibcon#read 3, iclass 34, count 2 2006.201.22:37:06.64#ibcon#about to read 4, iclass 34, count 2 2006.201.22:37:06.64#ibcon#read 4, iclass 34, count 2 2006.201.22:37:06.64#ibcon#about to read 5, iclass 34, count 2 2006.201.22:37:06.64#ibcon#read 5, iclass 34, count 2 2006.201.22:37:06.64#ibcon#about to read 6, iclass 34, count 2 2006.201.22:37:06.64#ibcon#read 6, iclass 34, count 2 2006.201.22:37:06.64#ibcon#end of sib2, iclass 34, count 2 2006.201.22:37:06.64#ibcon#*mode == 0, iclass 34, count 2 2006.201.22:37:06.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.22:37:06.64#ibcon#[27=AT01-04\r\n] 2006.201.22:37:06.64#ibcon#*before write, iclass 34, count 2 2006.201.22:37:06.64#ibcon#enter sib2, iclass 34, count 2 2006.201.22:37:06.64#ibcon#flushed, iclass 34, count 2 2006.201.22:37:06.64#ibcon#about to write, iclass 34, count 2 2006.201.22:37:06.64#ibcon#wrote, iclass 34, count 2 2006.201.22:37:06.64#ibcon#about to read 3, iclass 34, count 2 2006.201.22:37:06.67#ibcon#read 3, iclass 34, count 2 2006.201.22:37:06.67#ibcon#about to read 4, iclass 34, count 2 2006.201.22:37:06.67#ibcon#read 4, iclass 34, count 2 2006.201.22:37:06.67#ibcon#about to read 5, iclass 34, count 2 2006.201.22:37:06.67#ibcon#read 5, iclass 34, count 2 2006.201.22:37:06.67#ibcon#about to read 6, iclass 34, count 2 2006.201.22:37:06.67#ibcon#read 6, iclass 34, count 2 2006.201.22:37:06.67#ibcon#end of sib2, iclass 34, count 2 2006.201.22:37:06.67#ibcon#*after write, iclass 34, count 2 2006.201.22:37:06.67#ibcon#*before return 0, iclass 34, count 2 2006.201.22:37:06.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:06.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:37:06.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.22:37:06.67#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:06.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:06.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:06.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:06.79#ibcon#enter wrdev, iclass 34, count 0 2006.201.22:37:06.79#ibcon#first serial, iclass 34, count 0 2006.201.22:37:06.79#ibcon#enter sib2, iclass 34, count 0 2006.201.22:37:06.79#ibcon#flushed, iclass 34, count 0 2006.201.22:37:06.79#ibcon#about to write, iclass 34, count 0 2006.201.22:37:06.79#ibcon#wrote, iclass 34, count 0 2006.201.22:37:06.79#ibcon#about to read 3, iclass 34, count 0 2006.201.22:37:06.81#ibcon#read 3, iclass 34, count 0 2006.201.22:37:06.81#ibcon#about to read 4, iclass 34, count 0 2006.201.22:37:06.81#ibcon#read 4, iclass 34, count 0 2006.201.22:37:06.81#ibcon#about to read 5, iclass 34, count 0 2006.201.22:37:06.81#ibcon#read 5, iclass 34, count 0 2006.201.22:37:06.81#ibcon#about to read 6, iclass 34, count 0 2006.201.22:37:06.81#ibcon#read 6, iclass 34, count 0 2006.201.22:37:06.81#ibcon#end of sib2, iclass 34, count 0 2006.201.22:37:06.81#ibcon#*mode == 0, iclass 34, count 0 2006.201.22:37:06.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.22:37:06.81#ibcon#[27=USB\r\n] 2006.201.22:37:06.81#ibcon#*before write, iclass 34, count 0 2006.201.22:37:06.81#ibcon#enter sib2, iclass 34, count 0 2006.201.22:37:06.81#ibcon#flushed, iclass 34, count 0 2006.201.22:37:06.81#ibcon#about to write, iclass 34, count 0 2006.201.22:37:06.81#ibcon#wrote, iclass 34, count 0 2006.201.22:37:06.81#ibcon#about to read 3, iclass 34, count 0 2006.201.22:37:06.84#ibcon#read 3, iclass 34, count 0 2006.201.22:37:06.84#ibcon#about to read 4, iclass 34, count 0 2006.201.22:37:06.84#ibcon#read 4, iclass 34, count 0 2006.201.22:37:06.84#ibcon#about to read 5, iclass 34, count 0 2006.201.22:37:06.84#ibcon#read 5, iclass 34, count 0 2006.201.22:37:06.84#ibcon#about to read 6, iclass 34, count 0 2006.201.22:37:06.84#ibcon#read 6, iclass 34, count 0 2006.201.22:37:06.84#ibcon#end of sib2, iclass 34, count 0 2006.201.22:37:06.84#ibcon#*after write, iclass 34, count 0 2006.201.22:37:06.84#ibcon#*before return 0, iclass 34, count 0 2006.201.22:37:06.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:06.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:37:06.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.22:37:06.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.22:37:06.84$vck44/vblo=2,634.99 2006.201.22:37:06.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.22:37:06.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.22:37:06.84#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:06.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:06.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:06.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:06.84#ibcon#enter wrdev, iclass 36, count 0 2006.201.22:37:06.84#ibcon#first serial, iclass 36, count 0 2006.201.22:37:06.84#ibcon#enter sib2, iclass 36, count 0 2006.201.22:37:06.84#ibcon#flushed, iclass 36, count 0 2006.201.22:37:06.84#ibcon#about to write, iclass 36, count 0 2006.201.22:37:06.84#ibcon#wrote, iclass 36, count 0 2006.201.22:37:06.84#ibcon#about to read 3, iclass 36, count 0 2006.201.22:37:06.86#ibcon#read 3, iclass 36, count 0 2006.201.22:37:06.86#ibcon#about to read 4, iclass 36, count 0 2006.201.22:37:06.86#ibcon#read 4, iclass 36, count 0 2006.201.22:37:06.86#ibcon#about to read 5, iclass 36, count 0 2006.201.22:37:06.86#ibcon#read 5, iclass 36, count 0 2006.201.22:37:06.86#ibcon#about to read 6, iclass 36, count 0 2006.201.22:37:06.86#ibcon#read 6, iclass 36, count 0 2006.201.22:37:06.86#ibcon#end of sib2, iclass 36, count 0 2006.201.22:37:06.86#ibcon#*mode == 0, iclass 36, count 0 2006.201.22:37:06.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.22:37:06.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.22:37:06.86#ibcon#*before write, iclass 36, count 0 2006.201.22:37:06.86#ibcon#enter sib2, iclass 36, count 0 2006.201.22:37:06.86#ibcon#flushed, iclass 36, count 0 2006.201.22:37:06.86#ibcon#about to write, iclass 36, count 0 2006.201.22:37:06.86#ibcon#wrote, iclass 36, count 0 2006.201.22:37:06.86#ibcon#about to read 3, iclass 36, count 0 2006.201.22:37:06.90#ibcon#read 3, iclass 36, count 0 2006.201.22:37:06.90#ibcon#about to read 4, iclass 36, count 0 2006.201.22:37:06.90#ibcon#read 4, iclass 36, count 0 2006.201.22:37:06.90#ibcon#about to read 5, iclass 36, count 0 2006.201.22:37:06.90#ibcon#read 5, iclass 36, count 0 2006.201.22:37:06.90#ibcon#about to read 6, iclass 36, count 0 2006.201.22:37:06.90#ibcon#read 6, iclass 36, count 0 2006.201.22:37:06.90#ibcon#end of sib2, iclass 36, count 0 2006.201.22:37:06.90#ibcon#*after write, iclass 36, count 0 2006.201.22:37:06.90#ibcon#*before return 0, iclass 36, count 0 2006.201.22:37:06.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:06.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:37:06.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.22:37:06.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.22:37:06.90$vck44/vb=2,5 2006.201.22:37:06.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.22:37:06.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.22:37:06.90#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:06.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:06.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:06.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:06.96#ibcon#enter wrdev, iclass 38, count 2 2006.201.22:37:06.96#ibcon#first serial, iclass 38, count 2 2006.201.22:37:06.96#ibcon#enter sib2, iclass 38, count 2 2006.201.22:37:06.96#ibcon#flushed, iclass 38, count 2 2006.201.22:37:06.96#ibcon#about to write, iclass 38, count 2 2006.201.22:37:06.96#ibcon#wrote, iclass 38, count 2 2006.201.22:37:06.96#ibcon#about to read 3, iclass 38, count 2 2006.201.22:37:06.98#ibcon#read 3, iclass 38, count 2 2006.201.22:37:06.98#ibcon#about to read 4, iclass 38, count 2 2006.201.22:37:06.98#ibcon#read 4, iclass 38, count 2 2006.201.22:37:06.98#ibcon#about to read 5, iclass 38, count 2 2006.201.22:37:06.98#ibcon#read 5, iclass 38, count 2 2006.201.22:37:06.98#ibcon#about to read 6, iclass 38, count 2 2006.201.22:37:06.98#ibcon#read 6, iclass 38, count 2 2006.201.22:37:06.98#ibcon#end of sib2, iclass 38, count 2 2006.201.22:37:06.98#ibcon#*mode == 0, iclass 38, count 2 2006.201.22:37:06.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.22:37:06.98#ibcon#[27=AT02-05\r\n] 2006.201.22:37:06.98#ibcon#*before write, iclass 38, count 2 2006.201.22:37:06.98#ibcon#enter sib2, iclass 38, count 2 2006.201.22:37:06.98#ibcon#flushed, iclass 38, count 2 2006.201.22:37:06.98#ibcon#about to write, iclass 38, count 2 2006.201.22:37:06.98#ibcon#wrote, iclass 38, count 2 2006.201.22:37:06.98#ibcon#about to read 3, iclass 38, count 2 2006.201.22:37:07.01#ibcon#read 3, iclass 38, count 2 2006.201.22:37:07.01#ibcon#about to read 4, iclass 38, count 2 2006.201.22:37:07.01#ibcon#read 4, iclass 38, count 2 2006.201.22:37:07.01#ibcon#about to read 5, iclass 38, count 2 2006.201.22:37:07.01#ibcon#read 5, iclass 38, count 2 2006.201.22:37:07.01#ibcon#about to read 6, iclass 38, count 2 2006.201.22:37:07.01#ibcon#read 6, iclass 38, count 2 2006.201.22:37:07.01#ibcon#end of sib2, iclass 38, count 2 2006.201.22:37:07.01#ibcon#*after write, iclass 38, count 2 2006.201.22:37:07.01#ibcon#*before return 0, iclass 38, count 2 2006.201.22:37:07.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:07.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:37:07.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.22:37:07.01#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:07.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:07.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:07.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:07.13#ibcon#enter wrdev, iclass 38, count 0 2006.201.22:37:07.13#ibcon#first serial, iclass 38, count 0 2006.201.22:37:07.13#ibcon#enter sib2, iclass 38, count 0 2006.201.22:37:07.13#ibcon#flushed, iclass 38, count 0 2006.201.22:37:07.13#ibcon#about to write, iclass 38, count 0 2006.201.22:37:07.13#ibcon#wrote, iclass 38, count 0 2006.201.22:37:07.13#ibcon#about to read 3, iclass 38, count 0 2006.201.22:37:07.15#ibcon#read 3, iclass 38, count 0 2006.201.22:37:07.15#ibcon#about to read 4, iclass 38, count 0 2006.201.22:37:07.15#ibcon#read 4, iclass 38, count 0 2006.201.22:37:07.15#ibcon#about to read 5, iclass 38, count 0 2006.201.22:37:07.15#ibcon#read 5, iclass 38, count 0 2006.201.22:37:07.15#ibcon#about to read 6, iclass 38, count 0 2006.201.22:37:07.15#ibcon#read 6, iclass 38, count 0 2006.201.22:37:07.15#ibcon#end of sib2, iclass 38, count 0 2006.201.22:37:07.15#ibcon#*mode == 0, iclass 38, count 0 2006.201.22:37:07.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.22:37:07.15#ibcon#[27=USB\r\n] 2006.201.22:37:07.15#ibcon#*before write, iclass 38, count 0 2006.201.22:37:07.15#ibcon#enter sib2, iclass 38, count 0 2006.201.22:37:07.15#ibcon#flushed, iclass 38, count 0 2006.201.22:37:07.15#ibcon#about to write, iclass 38, count 0 2006.201.22:37:07.15#ibcon#wrote, iclass 38, count 0 2006.201.22:37:07.15#ibcon#about to read 3, iclass 38, count 0 2006.201.22:37:07.18#ibcon#read 3, iclass 38, count 0 2006.201.22:37:07.18#ibcon#about to read 4, iclass 38, count 0 2006.201.22:37:07.18#ibcon#read 4, iclass 38, count 0 2006.201.22:37:07.18#ibcon#about to read 5, iclass 38, count 0 2006.201.22:37:07.18#ibcon#read 5, iclass 38, count 0 2006.201.22:37:07.18#ibcon#about to read 6, iclass 38, count 0 2006.201.22:37:07.18#ibcon#read 6, iclass 38, count 0 2006.201.22:37:07.18#ibcon#end of sib2, iclass 38, count 0 2006.201.22:37:07.18#ibcon#*after write, iclass 38, count 0 2006.201.22:37:07.18#ibcon#*before return 0, iclass 38, count 0 2006.201.22:37:07.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:07.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:37:07.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.22:37:07.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.22:37:07.18$vck44/vblo=3,649.99 2006.201.22:37:07.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.22:37:07.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.22:37:07.18#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:07.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:07.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:07.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:07.18#ibcon#enter wrdev, iclass 40, count 0 2006.201.22:37:07.18#ibcon#first serial, iclass 40, count 0 2006.201.22:37:07.18#ibcon#enter sib2, iclass 40, count 0 2006.201.22:37:07.18#ibcon#flushed, iclass 40, count 0 2006.201.22:37:07.18#ibcon#about to write, iclass 40, count 0 2006.201.22:37:07.18#ibcon#wrote, iclass 40, count 0 2006.201.22:37:07.18#ibcon#about to read 3, iclass 40, count 0 2006.201.22:37:07.20#ibcon#read 3, iclass 40, count 0 2006.201.22:37:07.20#ibcon#about to read 4, iclass 40, count 0 2006.201.22:37:07.20#ibcon#read 4, iclass 40, count 0 2006.201.22:37:07.20#ibcon#about to read 5, iclass 40, count 0 2006.201.22:37:07.20#ibcon#read 5, iclass 40, count 0 2006.201.22:37:07.20#ibcon#about to read 6, iclass 40, count 0 2006.201.22:37:07.20#ibcon#read 6, iclass 40, count 0 2006.201.22:37:07.20#ibcon#end of sib2, iclass 40, count 0 2006.201.22:37:07.20#ibcon#*mode == 0, iclass 40, count 0 2006.201.22:37:07.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.22:37:07.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.22:37:07.20#ibcon#*before write, iclass 40, count 0 2006.201.22:37:07.20#ibcon#enter sib2, iclass 40, count 0 2006.201.22:37:07.20#ibcon#flushed, iclass 40, count 0 2006.201.22:37:07.20#ibcon#about to write, iclass 40, count 0 2006.201.22:37:07.20#ibcon#wrote, iclass 40, count 0 2006.201.22:37:07.20#ibcon#about to read 3, iclass 40, count 0 2006.201.22:37:07.25#ibcon#read 3, iclass 40, count 0 2006.201.22:37:07.25#ibcon#about to read 4, iclass 40, count 0 2006.201.22:37:07.25#ibcon#read 4, iclass 40, count 0 2006.201.22:37:07.25#ibcon#about to read 5, iclass 40, count 0 2006.201.22:37:07.25#ibcon#read 5, iclass 40, count 0 2006.201.22:37:07.25#ibcon#about to read 6, iclass 40, count 0 2006.201.22:37:07.25#ibcon#read 6, iclass 40, count 0 2006.201.22:37:07.25#ibcon#end of sib2, iclass 40, count 0 2006.201.22:37:07.25#ibcon#*after write, iclass 40, count 0 2006.201.22:37:07.25#ibcon#*before return 0, iclass 40, count 0 2006.201.22:37:07.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:07.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:37:07.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.22:37:07.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.22:37:07.25$vck44/vb=3,4 2006.201.22:37:07.25#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.22:37:07.25#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.22:37:07.25#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:07.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:07.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:07.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:07.30#ibcon#enter wrdev, iclass 4, count 2 2006.201.22:37:07.30#ibcon#first serial, iclass 4, count 2 2006.201.22:37:07.30#ibcon#enter sib2, iclass 4, count 2 2006.201.22:37:07.30#ibcon#flushed, iclass 4, count 2 2006.201.22:37:07.30#ibcon#about to write, iclass 4, count 2 2006.201.22:37:07.30#ibcon#wrote, iclass 4, count 2 2006.201.22:37:07.30#ibcon#about to read 3, iclass 4, count 2 2006.201.22:37:07.32#ibcon#read 3, iclass 4, count 2 2006.201.22:37:07.32#ibcon#about to read 4, iclass 4, count 2 2006.201.22:37:07.32#ibcon#read 4, iclass 4, count 2 2006.201.22:37:07.32#ibcon#about to read 5, iclass 4, count 2 2006.201.22:37:07.32#ibcon#read 5, iclass 4, count 2 2006.201.22:37:07.32#ibcon#about to read 6, iclass 4, count 2 2006.201.22:37:07.32#ibcon#read 6, iclass 4, count 2 2006.201.22:37:07.32#ibcon#end of sib2, iclass 4, count 2 2006.201.22:37:07.32#ibcon#*mode == 0, iclass 4, count 2 2006.201.22:37:07.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.22:37:07.32#ibcon#[27=AT03-04\r\n] 2006.201.22:37:07.32#ibcon#*before write, iclass 4, count 2 2006.201.22:37:07.32#ibcon#enter sib2, iclass 4, count 2 2006.201.22:37:07.32#ibcon#flushed, iclass 4, count 2 2006.201.22:37:07.32#ibcon#about to write, iclass 4, count 2 2006.201.22:37:07.32#ibcon#wrote, iclass 4, count 2 2006.201.22:37:07.32#ibcon#about to read 3, iclass 4, count 2 2006.201.22:37:07.35#ibcon#read 3, iclass 4, count 2 2006.201.22:37:07.35#ibcon#about to read 4, iclass 4, count 2 2006.201.22:37:07.35#ibcon#read 4, iclass 4, count 2 2006.201.22:37:07.35#ibcon#about to read 5, iclass 4, count 2 2006.201.22:37:07.35#ibcon#read 5, iclass 4, count 2 2006.201.22:37:07.35#ibcon#about to read 6, iclass 4, count 2 2006.201.22:37:07.35#ibcon#read 6, iclass 4, count 2 2006.201.22:37:07.35#ibcon#end of sib2, iclass 4, count 2 2006.201.22:37:07.35#ibcon#*after write, iclass 4, count 2 2006.201.22:37:07.35#ibcon#*before return 0, iclass 4, count 2 2006.201.22:37:07.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:07.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:37:07.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.22:37:07.35#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:07.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:07.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:07.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:07.47#ibcon#enter wrdev, iclass 4, count 0 2006.201.22:37:07.47#ibcon#first serial, iclass 4, count 0 2006.201.22:37:07.47#ibcon#enter sib2, iclass 4, count 0 2006.201.22:37:07.47#ibcon#flushed, iclass 4, count 0 2006.201.22:37:07.47#ibcon#about to write, iclass 4, count 0 2006.201.22:37:07.47#ibcon#wrote, iclass 4, count 0 2006.201.22:37:07.47#ibcon#about to read 3, iclass 4, count 0 2006.201.22:37:07.49#ibcon#read 3, iclass 4, count 0 2006.201.22:37:07.49#ibcon#about to read 4, iclass 4, count 0 2006.201.22:37:07.49#ibcon#read 4, iclass 4, count 0 2006.201.22:37:07.49#ibcon#about to read 5, iclass 4, count 0 2006.201.22:37:07.49#ibcon#read 5, iclass 4, count 0 2006.201.22:37:07.49#ibcon#about to read 6, iclass 4, count 0 2006.201.22:37:07.49#ibcon#read 6, iclass 4, count 0 2006.201.22:37:07.49#ibcon#end of sib2, iclass 4, count 0 2006.201.22:37:07.49#ibcon#*mode == 0, iclass 4, count 0 2006.201.22:37:07.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.22:37:07.49#ibcon#[27=USB\r\n] 2006.201.22:37:07.49#ibcon#*before write, iclass 4, count 0 2006.201.22:37:07.49#ibcon#enter sib2, iclass 4, count 0 2006.201.22:37:07.49#ibcon#flushed, iclass 4, count 0 2006.201.22:37:07.49#ibcon#about to write, iclass 4, count 0 2006.201.22:37:07.49#ibcon#wrote, iclass 4, count 0 2006.201.22:37:07.49#ibcon#about to read 3, iclass 4, count 0 2006.201.22:37:07.52#ibcon#read 3, iclass 4, count 0 2006.201.22:37:07.52#ibcon#about to read 4, iclass 4, count 0 2006.201.22:37:07.52#ibcon#read 4, iclass 4, count 0 2006.201.22:37:07.52#ibcon#about to read 5, iclass 4, count 0 2006.201.22:37:07.52#ibcon#read 5, iclass 4, count 0 2006.201.22:37:07.52#ibcon#about to read 6, iclass 4, count 0 2006.201.22:37:07.52#ibcon#read 6, iclass 4, count 0 2006.201.22:37:07.52#ibcon#end of sib2, iclass 4, count 0 2006.201.22:37:07.52#ibcon#*after write, iclass 4, count 0 2006.201.22:37:07.52#ibcon#*before return 0, iclass 4, count 0 2006.201.22:37:07.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:07.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:37:07.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.22:37:07.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.22:37:07.52$vck44/vblo=4,679.99 2006.201.22:37:07.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.22:37:07.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.22:37:07.52#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:07.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:07.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:07.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:07.52#ibcon#enter wrdev, iclass 6, count 0 2006.201.22:37:07.52#ibcon#first serial, iclass 6, count 0 2006.201.22:37:07.52#ibcon#enter sib2, iclass 6, count 0 2006.201.22:37:07.52#ibcon#flushed, iclass 6, count 0 2006.201.22:37:07.52#ibcon#about to write, iclass 6, count 0 2006.201.22:37:07.52#ibcon#wrote, iclass 6, count 0 2006.201.22:37:07.52#ibcon#about to read 3, iclass 6, count 0 2006.201.22:37:07.54#ibcon#read 3, iclass 6, count 0 2006.201.22:37:07.54#ibcon#about to read 4, iclass 6, count 0 2006.201.22:37:07.54#ibcon#read 4, iclass 6, count 0 2006.201.22:37:07.54#ibcon#about to read 5, iclass 6, count 0 2006.201.22:37:07.54#ibcon#read 5, iclass 6, count 0 2006.201.22:37:07.54#ibcon#about to read 6, iclass 6, count 0 2006.201.22:37:07.54#ibcon#read 6, iclass 6, count 0 2006.201.22:37:07.54#ibcon#end of sib2, iclass 6, count 0 2006.201.22:37:07.54#ibcon#*mode == 0, iclass 6, count 0 2006.201.22:37:07.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.22:37:07.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.22:37:07.54#ibcon#*before write, iclass 6, count 0 2006.201.22:37:07.54#ibcon#enter sib2, iclass 6, count 0 2006.201.22:37:07.54#ibcon#flushed, iclass 6, count 0 2006.201.22:37:07.54#ibcon#about to write, iclass 6, count 0 2006.201.22:37:07.54#ibcon#wrote, iclass 6, count 0 2006.201.22:37:07.54#ibcon#about to read 3, iclass 6, count 0 2006.201.22:37:07.58#ibcon#read 3, iclass 6, count 0 2006.201.22:37:07.58#ibcon#about to read 4, iclass 6, count 0 2006.201.22:37:07.58#ibcon#read 4, iclass 6, count 0 2006.201.22:37:07.58#ibcon#about to read 5, iclass 6, count 0 2006.201.22:37:07.58#ibcon#read 5, iclass 6, count 0 2006.201.22:37:07.58#ibcon#about to read 6, iclass 6, count 0 2006.201.22:37:07.58#ibcon#read 6, iclass 6, count 0 2006.201.22:37:07.58#ibcon#end of sib2, iclass 6, count 0 2006.201.22:37:07.58#ibcon#*after write, iclass 6, count 0 2006.201.22:37:07.58#ibcon#*before return 0, iclass 6, count 0 2006.201.22:37:07.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:07.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:37:07.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.22:37:07.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.22:37:07.58$vck44/vb=4,5 2006.201.22:37:07.58#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.22:37:07.58#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.22:37:07.58#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:07.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:07.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:07.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:07.64#ibcon#enter wrdev, iclass 10, count 2 2006.201.22:37:07.64#ibcon#first serial, iclass 10, count 2 2006.201.22:37:07.64#ibcon#enter sib2, iclass 10, count 2 2006.201.22:37:07.64#ibcon#flushed, iclass 10, count 2 2006.201.22:37:07.64#ibcon#about to write, iclass 10, count 2 2006.201.22:37:07.64#ibcon#wrote, iclass 10, count 2 2006.201.22:37:07.64#ibcon#about to read 3, iclass 10, count 2 2006.201.22:37:07.66#ibcon#read 3, iclass 10, count 2 2006.201.22:37:07.66#ibcon#about to read 4, iclass 10, count 2 2006.201.22:37:07.66#ibcon#read 4, iclass 10, count 2 2006.201.22:37:07.66#ibcon#about to read 5, iclass 10, count 2 2006.201.22:37:07.66#ibcon#read 5, iclass 10, count 2 2006.201.22:37:07.66#ibcon#about to read 6, iclass 10, count 2 2006.201.22:37:07.66#ibcon#read 6, iclass 10, count 2 2006.201.22:37:07.66#ibcon#end of sib2, iclass 10, count 2 2006.201.22:37:07.66#ibcon#*mode == 0, iclass 10, count 2 2006.201.22:37:07.66#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.22:37:07.66#ibcon#[27=AT04-05\r\n] 2006.201.22:37:07.66#ibcon#*before write, iclass 10, count 2 2006.201.22:37:07.66#ibcon#enter sib2, iclass 10, count 2 2006.201.22:37:07.66#ibcon#flushed, iclass 10, count 2 2006.201.22:37:07.66#ibcon#about to write, iclass 10, count 2 2006.201.22:37:07.66#ibcon#wrote, iclass 10, count 2 2006.201.22:37:07.66#ibcon#about to read 3, iclass 10, count 2 2006.201.22:37:07.69#ibcon#read 3, iclass 10, count 2 2006.201.22:37:07.69#ibcon#about to read 4, iclass 10, count 2 2006.201.22:37:07.69#ibcon#read 4, iclass 10, count 2 2006.201.22:37:07.69#ibcon#about to read 5, iclass 10, count 2 2006.201.22:37:07.69#ibcon#read 5, iclass 10, count 2 2006.201.22:37:07.69#ibcon#about to read 6, iclass 10, count 2 2006.201.22:37:07.69#ibcon#read 6, iclass 10, count 2 2006.201.22:37:07.69#ibcon#end of sib2, iclass 10, count 2 2006.201.22:37:07.69#ibcon#*after write, iclass 10, count 2 2006.201.22:37:07.69#ibcon#*before return 0, iclass 10, count 2 2006.201.22:37:07.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:07.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:37:07.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.22:37:07.69#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:07.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:07.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:07.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:07.81#ibcon#enter wrdev, iclass 10, count 0 2006.201.22:37:07.81#ibcon#first serial, iclass 10, count 0 2006.201.22:37:07.81#ibcon#enter sib2, iclass 10, count 0 2006.201.22:37:07.81#ibcon#flushed, iclass 10, count 0 2006.201.22:37:07.81#ibcon#about to write, iclass 10, count 0 2006.201.22:37:07.81#ibcon#wrote, iclass 10, count 0 2006.201.22:37:07.81#ibcon#about to read 3, iclass 10, count 0 2006.201.22:37:07.83#ibcon#read 3, iclass 10, count 0 2006.201.22:37:07.83#ibcon#about to read 4, iclass 10, count 0 2006.201.22:37:07.83#ibcon#read 4, iclass 10, count 0 2006.201.22:37:07.83#ibcon#about to read 5, iclass 10, count 0 2006.201.22:37:07.83#ibcon#read 5, iclass 10, count 0 2006.201.22:37:07.83#ibcon#about to read 6, iclass 10, count 0 2006.201.22:37:07.83#ibcon#read 6, iclass 10, count 0 2006.201.22:37:07.83#ibcon#end of sib2, iclass 10, count 0 2006.201.22:37:07.83#ibcon#*mode == 0, iclass 10, count 0 2006.201.22:37:07.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.22:37:07.83#ibcon#[27=USB\r\n] 2006.201.22:37:07.83#ibcon#*before write, iclass 10, count 0 2006.201.22:37:07.83#ibcon#enter sib2, iclass 10, count 0 2006.201.22:37:07.83#ibcon#flushed, iclass 10, count 0 2006.201.22:37:07.83#ibcon#about to write, iclass 10, count 0 2006.201.22:37:07.83#ibcon#wrote, iclass 10, count 0 2006.201.22:37:07.83#ibcon#about to read 3, iclass 10, count 0 2006.201.22:37:07.86#ibcon#read 3, iclass 10, count 0 2006.201.22:37:07.86#ibcon#about to read 4, iclass 10, count 0 2006.201.22:37:07.86#ibcon#read 4, iclass 10, count 0 2006.201.22:37:07.86#ibcon#about to read 5, iclass 10, count 0 2006.201.22:37:07.86#ibcon#read 5, iclass 10, count 0 2006.201.22:37:07.86#ibcon#about to read 6, iclass 10, count 0 2006.201.22:37:07.86#ibcon#read 6, iclass 10, count 0 2006.201.22:37:07.86#ibcon#end of sib2, iclass 10, count 0 2006.201.22:37:07.86#ibcon#*after write, iclass 10, count 0 2006.201.22:37:07.86#ibcon#*before return 0, iclass 10, count 0 2006.201.22:37:07.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:07.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:37:07.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.22:37:07.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.22:37:07.86$vck44/vblo=5,709.99 2006.201.22:37:07.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.22:37:07.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.22:37:07.86#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:07.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:37:07.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:37:07.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:37:07.86#ibcon#enter wrdev, iclass 12, count 0 2006.201.22:37:07.86#ibcon#first serial, iclass 12, count 0 2006.201.22:37:07.86#ibcon#enter sib2, iclass 12, count 0 2006.201.22:37:07.86#ibcon#flushed, iclass 12, count 0 2006.201.22:37:07.86#ibcon#about to write, iclass 12, count 0 2006.201.22:37:07.86#ibcon#wrote, iclass 12, count 0 2006.201.22:37:07.86#ibcon#about to read 3, iclass 12, count 0 2006.201.22:37:07.88#ibcon#read 3, iclass 12, count 0 2006.201.22:37:07.88#ibcon#about to read 4, iclass 12, count 0 2006.201.22:37:07.88#ibcon#read 4, iclass 12, count 0 2006.201.22:37:07.88#ibcon#about to read 5, iclass 12, count 0 2006.201.22:37:07.88#ibcon#read 5, iclass 12, count 0 2006.201.22:37:07.88#ibcon#about to read 6, iclass 12, count 0 2006.201.22:37:07.88#ibcon#read 6, iclass 12, count 0 2006.201.22:37:07.88#ibcon#end of sib2, iclass 12, count 0 2006.201.22:37:07.88#ibcon#*mode == 0, iclass 12, count 0 2006.201.22:37:07.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.22:37:07.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.22:37:07.88#ibcon#*before write, iclass 12, count 0 2006.201.22:37:07.88#ibcon#enter sib2, iclass 12, count 0 2006.201.22:37:07.88#ibcon#flushed, iclass 12, count 0 2006.201.22:37:07.88#ibcon#about to write, iclass 12, count 0 2006.201.22:37:07.88#ibcon#wrote, iclass 12, count 0 2006.201.22:37:07.88#ibcon#about to read 3, iclass 12, count 0 2006.201.22:37:07.93#ibcon#read 3, iclass 12, count 0 2006.201.22:37:07.93#ibcon#about to read 4, iclass 12, count 0 2006.201.22:37:07.93#ibcon#read 4, iclass 12, count 0 2006.201.22:37:07.93#ibcon#about to read 5, iclass 12, count 0 2006.201.22:37:07.93#ibcon#read 5, iclass 12, count 0 2006.201.22:37:07.93#ibcon#about to read 6, iclass 12, count 0 2006.201.22:37:07.93#ibcon#read 6, iclass 12, count 0 2006.201.22:37:07.93#ibcon#end of sib2, iclass 12, count 0 2006.201.22:37:07.93#ibcon#*after write, iclass 12, count 0 2006.201.22:37:07.93#ibcon#*before return 0, iclass 12, count 0 2006.201.22:37:07.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:37:07.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:37:07.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.22:37:07.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.22:37:07.93$vck44/vb=5,4 2006.201.22:37:07.93#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.22:37:07.93#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.22:37:07.93#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:07.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:37:07.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:37:07.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:37:07.98#ibcon#enter wrdev, iclass 14, count 2 2006.201.22:37:07.98#ibcon#first serial, iclass 14, count 2 2006.201.22:37:07.98#ibcon#enter sib2, iclass 14, count 2 2006.201.22:37:07.98#ibcon#flushed, iclass 14, count 2 2006.201.22:37:07.98#ibcon#about to write, iclass 14, count 2 2006.201.22:37:07.98#ibcon#wrote, iclass 14, count 2 2006.201.22:37:07.98#ibcon#about to read 3, iclass 14, count 2 2006.201.22:37:08.00#ibcon#read 3, iclass 14, count 2 2006.201.22:37:08.00#ibcon#about to read 4, iclass 14, count 2 2006.201.22:37:08.00#ibcon#read 4, iclass 14, count 2 2006.201.22:37:08.00#ibcon#about to read 5, iclass 14, count 2 2006.201.22:37:08.00#ibcon#read 5, iclass 14, count 2 2006.201.22:37:08.00#ibcon#about to read 6, iclass 14, count 2 2006.201.22:37:08.00#ibcon#read 6, iclass 14, count 2 2006.201.22:37:08.00#ibcon#end of sib2, iclass 14, count 2 2006.201.22:37:08.00#ibcon#*mode == 0, iclass 14, count 2 2006.201.22:37:08.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.22:37:08.00#ibcon#[27=AT05-04\r\n] 2006.201.22:37:08.00#ibcon#*before write, iclass 14, count 2 2006.201.22:37:08.00#ibcon#enter sib2, iclass 14, count 2 2006.201.22:37:08.00#ibcon#flushed, iclass 14, count 2 2006.201.22:37:08.00#ibcon#about to write, iclass 14, count 2 2006.201.22:37:08.00#ibcon#wrote, iclass 14, count 2 2006.201.22:37:08.00#ibcon#about to read 3, iclass 14, count 2 2006.201.22:37:08.03#ibcon#read 3, iclass 14, count 2 2006.201.22:37:08.03#ibcon#about to read 4, iclass 14, count 2 2006.201.22:37:08.03#ibcon#read 4, iclass 14, count 2 2006.201.22:37:08.03#ibcon#about to read 5, iclass 14, count 2 2006.201.22:37:08.03#ibcon#read 5, iclass 14, count 2 2006.201.22:37:08.03#ibcon#about to read 6, iclass 14, count 2 2006.201.22:37:08.03#ibcon#read 6, iclass 14, count 2 2006.201.22:37:08.03#ibcon#end of sib2, iclass 14, count 2 2006.201.22:37:08.03#ibcon#*after write, iclass 14, count 2 2006.201.22:37:08.03#ibcon#*before return 0, iclass 14, count 2 2006.201.22:37:08.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:37:08.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:37:08.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.22:37:08.03#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:08.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:37:08.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:37:08.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:37:08.15#ibcon#enter wrdev, iclass 14, count 0 2006.201.22:37:08.15#ibcon#first serial, iclass 14, count 0 2006.201.22:37:08.15#ibcon#enter sib2, iclass 14, count 0 2006.201.22:37:08.15#ibcon#flushed, iclass 14, count 0 2006.201.22:37:08.15#ibcon#about to write, iclass 14, count 0 2006.201.22:37:08.15#ibcon#wrote, iclass 14, count 0 2006.201.22:37:08.15#ibcon#about to read 3, iclass 14, count 0 2006.201.22:37:08.17#ibcon#read 3, iclass 14, count 0 2006.201.22:37:08.17#ibcon#about to read 4, iclass 14, count 0 2006.201.22:37:08.17#ibcon#read 4, iclass 14, count 0 2006.201.22:37:08.17#ibcon#about to read 5, iclass 14, count 0 2006.201.22:37:08.17#ibcon#read 5, iclass 14, count 0 2006.201.22:37:08.17#ibcon#about to read 6, iclass 14, count 0 2006.201.22:37:08.17#ibcon#read 6, iclass 14, count 0 2006.201.22:37:08.17#ibcon#end of sib2, iclass 14, count 0 2006.201.22:37:08.17#ibcon#*mode == 0, iclass 14, count 0 2006.201.22:37:08.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.22:37:08.17#ibcon#[27=USB\r\n] 2006.201.22:37:08.17#ibcon#*before write, iclass 14, count 0 2006.201.22:37:08.17#ibcon#enter sib2, iclass 14, count 0 2006.201.22:37:08.17#ibcon#flushed, iclass 14, count 0 2006.201.22:37:08.17#ibcon#about to write, iclass 14, count 0 2006.201.22:37:08.17#ibcon#wrote, iclass 14, count 0 2006.201.22:37:08.17#ibcon#about to read 3, iclass 14, count 0 2006.201.22:37:08.20#ibcon#read 3, iclass 14, count 0 2006.201.22:37:08.20#ibcon#about to read 4, iclass 14, count 0 2006.201.22:37:08.20#ibcon#read 4, iclass 14, count 0 2006.201.22:37:08.20#ibcon#about to read 5, iclass 14, count 0 2006.201.22:37:08.20#ibcon#read 5, iclass 14, count 0 2006.201.22:37:08.20#ibcon#about to read 6, iclass 14, count 0 2006.201.22:37:08.20#ibcon#read 6, iclass 14, count 0 2006.201.22:37:08.20#ibcon#end of sib2, iclass 14, count 0 2006.201.22:37:08.20#ibcon#*after write, iclass 14, count 0 2006.201.22:37:08.20#ibcon#*before return 0, iclass 14, count 0 2006.201.22:37:08.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:37:08.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:37:08.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.22:37:08.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.22:37:08.20$vck44/vblo=6,719.99 2006.201.22:37:08.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.22:37:08.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.22:37:08.20#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:08.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:37:08.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:37:08.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:37:08.20#ibcon#enter wrdev, iclass 16, count 0 2006.201.22:37:08.20#ibcon#first serial, iclass 16, count 0 2006.201.22:37:08.20#ibcon#enter sib2, iclass 16, count 0 2006.201.22:37:08.20#ibcon#flushed, iclass 16, count 0 2006.201.22:37:08.20#ibcon#about to write, iclass 16, count 0 2006.201.22:37:08.20#ibcon#wrote, iclass 16, count 0 2006.201.22:37:08.20#ibcon#about to read 3, iclass 16, count 0 2006.201.22:37:08.22#ibcon#read 3, iclass 16, count 0 2006.201.22:37:08.22#ibcon#about to read 4, iclass 16, count 0 2006.201.22:37:08.22#ibcon#read 4, iclass 16, count 0 2006.201.22:37:08.22#ibcon#about to read 5, iclass 16, count 0 2006.201.22:37:08.22#ibcon#read 5, iclass 16, count 0 2006.201.22:37:08.22#ibcon#about to read 6, iclass 16, count 0 2006.201.22:37:08.22#ibcon#read 6, iclass 16, count 0 2006.201.22:37:08.22#ibcon#end of sib2, iclass 16, count 0 2006.201.22:37:08.22#ibcon#*mode == 0, iclass 16, count 0 2006.201.22:37:08.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.22:37:08.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.22:37:08.22#ibcon#*before write, iclass 16, count 0 2006.201.22:37:08.22#ibcon#enter sib2, iclass 16, count 0 2006.201.22:37:08.22#ibcon#flushed, iclass 16, count 0 2006.201.22:37:08.22#ibcon#about to write, iclass 16, count 0 2006.201.22:37:08.22#ibcon#wrote, iclass 16, count 0 2006.201.22:37:08.22#ibcon#about to read 3, iclass 16, count 0 2006.201.22:37:08.26#ibcon#read 3, iclass 16, count 0 2006.201.22:37:08.26#ibcon#about to read 4, iclass 16, count 0 2006.201.22:37:08.26#ibcon#read 4, iclass 16, count 0 2006.201.22:37:08.26#ibcon#about to read 5, iclass 16, count 0 2006.201.22:37:08.26#ibcon#read 5, iclass 16, count 0 2006.201.22:37:08.26#ibcon#about to read 6, iclass 16, count 0 2006.201.22:37:08.26#ibcon#read 6, iclass 16, count 0 2006.201.22:37:08.26#ibcon#end of sib2, iclass 16, count 0 2006.201.22:37:08.26#ibcon#*after write, iclass 16, count 0 2006.201.22:37:08.26#ibcon#*before return 0, iclass 16, count 0 2006.201.22:37:08.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:37:08.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:37:08.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.22:37:08.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.22:37:08.26$vck44/vb=6,4 2006.201.22:37:08.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.22:37:08.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.22:37:08.26#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:08.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:08.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:08.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:08.32#ibcon#enter wrdev, iclass 18, count 2 2006.201.22:37:08.32#ibcon#first serial, iclass 18, count 2 2006.201.22:37:08.32#ibcon#enter sib2, iclass 18, count 2 2006.201.22:37:08.32#ibcon#flushed, iclass 18, count 2 2006.201.22:37:08.32#ibcon#about to write, iclass 18, count 2 2006.201.22:37:08.32#ibcon#wrote, iclass 18, count 2 2006.201.22:37:08.32#ibcon#about to read 3, iclass 18, count 2 2006.201.22:37:08.34#ibcon#read 3, iclass 18, count 2 2006.201.22:37:08.34#ibcon#about to read 4, iclass 18, count 2 2006.201.22:37:08.34#ibcon#read 4, iclass 18, count 2 2006.201.22:37:08.34#ibcon#about to read 5, iclass 18, count 2 2006.201.22:37:08.34#ibcon#read 5, iclass 18, count 2 2006.201.22:37:08.34#ibcon#about to read 6, iclass 18, count 2 2006.201.22:37:08.34#ibcon#read 6, iclass 18, count 2 2006.201.22:37:08.34#ibcon#end of sib2, iclass 18, count 2 2006.201.22:37:08.34#ibcon#*mode == 0, iclass 18, count 2 2006.201.22:37:08.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.22:37:08.34#ibcon#[27=AT06-04\r\n] 2006.201.22:37:08.34#ibcon#*before write, iclass 18, count 2 2006.201.22:37:08.34#ibcon#enter sib2, iclass 18, count 2 2006.201.22:37:08.34#ibcon#flushed, iclass 18, count 2 2006.201.22:37:08.34#ibcon#about to write, iclass 18, count 2 2006.201.22:37:08.34#ibcon#wrote, iclass 18, count 2 2006.201.22:37:08.34#ibcon#about to read 3, iclass 18, count 2 2006.201.22:37:08.37#ibcon#read 3, iclass 18, count 2 2006.201.22:37:08.37#ibcon#about to read 4, iclass 18, count 2 2006.201.22:37:08.37#ibcon#read 4, iclass 18, count 2 2006.201.22:37:08.37#ibcon#about to read 5, iclass 18, count 2 2006.201.22:37:08.37#ibcon#read 5, iclass 18, count 2 2006.201.22:37:08.37#ibcon#about to read 6, iclass 18, count 2 2006.201.22:37:08.37#ibcon#read 6, iclass 18, count 2 2006.201.22:37:08.37#ibcon#end of sib2, iclass 18, count 2 2006.201.22:37:08.37#ibcon#*after write, iclass 18, count 2 2006.201.22:37:08.37#ibcon#*before return 0, iclass 18, count 2 2006.201.22:37:08.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:08.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:37:08.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.22:37:08.37#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:08.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:08.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:08.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:08.49#ibcon#enter wrdev, iclass 18, count 0 2006.201.22:37:08.49#ibcon#first serial, iclass 18, count 0 2006.201.22:37:08.49#ibcon#enter sib2, iclass 18, count 0 2006.201.22:37:08.49#ibcon#flushed, iclass 18, count 0 2006.201.22:37:08.49#ibcon#about to write, iclass 18, count 0 2006.201.22:37:08.49#ibcon#wrote, iclass 18, count 0 2006.201.22:37:08.49#ibcon#about to read 3, iclass 18, count 0 2006.201.22:37:08.51#ibcon#read 3, iclass 18, count 0 2006.201.22:37:08.51#ibcon#about to read 4, iclass 18, count 0 2006.201.22:37:08.51#ibcon#read 4, iclass 18, count 0 2006.201.22:37:08.51#ibcon#about to read 5, iclass 18, count 0 2006.201.22:37:08.51#ibcon#read 5, iclass 18, count 0 2006.201.22:37:08.51#ibcon#about to read 6, iclass 18, count 0 2006.201.22:37:08.51#ibcon#read 6, iclass 18, count 0 2006.201.22:37:08.51#ibcon#end of sib2, iclass 18, count 0 2006.201.22:37:08.51#ibcon#*mode == 0, iclass 18, count 0 2006.201.22:37:08.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.22:37:08.51#ibcon#[27=USB\r\n] 2006.201.22:37:08.51#ibcon#*before write, iclass 18, count 0 2006.201.22:37:08.51#ibcon#enter sib2, iclass 18, count 0 2006.201.22:37:08.51#ibcon#flushed, iclass 18, count 0 2006.201.22:37:08.51#ibcon#about to write, iclass 18, count 0 2006.201.22:37:08.51#ibcon#wrote, iclass 18, count 0 2006.201.22:37:08.51#ibcon#about to read 3, iclass 18, count 0 2006.201.22:37:08.54#ibcon#read 3, iclass 18, count 0 2006.201.22:37:08.54#ibcon#about to read 4, iclass 18, count 0 2006.201.22:37:08.54#ibcon#read 4, iclass 18, count 0 2006.201.22:37:08.54#ibcon#about to read 5, iclass 18, count 0 2006.201.22:37:08.54#ibcon#read 5, iclass 18, count 0 2006.201.22:37:08.54#ibcon#about to read 6, iclass 18, count 0 2006.201.22:37:08.54#ibcon#read 6, iclass 18, count 0 2006.201.22:37:08.54#ibcon#end of sib2, iclass 18, count 0 2006.201.22:37:08.54#ibcon#*after write, iclass 18, count 0 2006.201.22:37:08.54#ibcon#*before return 0, iclass 18, count 0 2006.201.22:37:08.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:08.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:37:08.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.22:37:08.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.22:37:08.54$vck44/vblo=7,734.99 2006.201.22:37:08.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.22:37:08.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.22:37:08.54#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:08.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:08.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:08.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:08.54#ibcon#enter wrdev, iclass 20, count 0 2006.201.22:37:08.54#ibcon#first serial, iclass 20, count 0 2006.201.22:37:08.54#ibcon#enter sib2, iclass 20, count 0 2006.201.22:37:08.54#ibcon#flushed, iclass 20, count 0 2006.201.22:37:08.54#ibcon#about to write, iclass 20, count 0 2006.201.22:37:08.54#ibcon#wrote, iclass 20, count 0 2006.201.22:37:08.54#ibcon#about to read 3, iclass 20, count 0 2006.201.22:37:08.56#ibcon#read 3, iclass 20, count 0 2006.201.22:37:08.56#ibcon#about to read 4, iclass 20, count 0 2006.201.22:37:08.56#ibcon#read 4, iclass 20, count 0 2006.201.22:37:08.56#ibcon#about to read 5, iclass 20, count 0 2006.201.22:37:08.56#ibcon#read 5, iclass 20, count 0 2006.201.22:37:08.56#ibcon#about to read 6, iclass 20, count 0 2006.201.22:37:08.56#ibcon#read 6, iclass 20, count 0 2006.201.22:37:08.56#ibcon#end of sib2, iclass 20, count 0 2006.201.22:37:08.56#ibcon#*mode == 0, iclass 20, count 0 2006.201.22:37:08.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.22:37:08.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.22:37:08.56#ibcon#*before write, iclass 20, count 0 2006.201.22:37:08.56#ibcon#enter sib2, iclass 20, count 0 2006.201.22:37:08.56#ibcon#flushed, iclass 20, count 0 2006.201.22:37:08.56#ibcon#about to write, iclass 20, count 0 2006.201.22:37:08.56#ibcon#wrote, iclass 20, count 0 2006.201.22:37:08.56#ibcon#about to read 3, iclass 20, count 0 2006.201.22:37:08.60#ibcon#read 3, iclass 20, count 0 2006.201.22:37:08.60#ibcon#about to read 4, iclass 20, count 0 2006.201.22:37:08.60#ibcon#read 4, iclass 20, count 0 2006.201.22:37:08.60#ibcon#about to read 5, iclass 20, count 0 2006.201.22:37:08.60#ibcon#read 5, iclass 20, count 0 2006.201.22:37:08.60#ibcon#about to read 6, iclass 20, count 0 2006.201.22:37:08.60#ibcon#read 6, iclass 20, count 0 2006.201.22:37:08.60#ibcon#end of sib2, iclass 20, count 0 2006.201.22:37:08.60#ibcon#*after write, iclass 20, count 0 2006.201.22:37:08.60#ibcon#*before return 0, iclass 20, count 0 2006.201.22:37:08.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:08.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:37:08.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.22:37:08.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.22:37:08.60$vck44/vb=7,4 2006.201.22:37:08.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.22:37:08.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.22:37:08.60#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:08.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:08.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:08.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:08.66#ibcon#enter wrdev, iclass 22, count 2 2006.201.22:37:08.66#ibcon#first serial, iclass 22, count 2 2006.201.22:37:08.66#ibcon#enter sib2, iclass 22, count 2 2006.201.22:37:08.66#ibcon#flushed, iclass 22, count 2 2006.201.22:37:08.66#ibcon#about to write, iclass 22, count 2 2006.201.22:37:08.66#ibcon#wrote, iclass 22, count 2 2006.201.22:37:08.66#ibcon#about to read 3, iclass 22, count 2 2006.201.22:37:08.68#ibcon#read 3, iclass 22, count 2 2006.201.22:37:08.68#ibcon#about to read 4, iclass 22, count 2 2006.201.22:37:08.68#ibcon#read 4, iclass 22, count 2 2006.201.22:37:08.68#ibcon#about to read 5, iclass 22, count 2 2006.201.22:37:08.68#ibcon#read 5, iclass 22, count 2 2006.201.22:37:08.68#ibcon#about to read 6, iclass 22, count 2 2006.201.22:37:08.68#ibcon#read 6, iclass 22, count 2 2006.201.22:37:08.68#ibcon#end of sib2, iclass 22, count 2 2006.201.22:37:08.68#ibcon#*mode == 0, iclass 22, count 2 2006.201.22:37:08.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.22:37:08.68#ibcon#[27=AT07-04\r\n] 2006.201.22:37:08.68#ibcon#*before write, iclass 22, count 2 2006.201.22:37:08.68#ibcon#enter sib2, iclass 22, count 2 2006.201.22:37:08.68#ibcon#flushed, iclass 22, count 2 2006.201.22:37:08.68#ibcon#about to write, iclass 22, count 2 2006.201.22:37:08.68#ibcon#wrote, iclass 22, count 2 2006.201.22:37:08.68#ibcon#about to read 3, iclass 22, count 2 2006.201.22:37:08.71#ibcon#read 3, iclass 22, count 2 2006.201.22:37:08.71#ibcon#about to read 4, iclass 22, count 2 2006.201.22:37:08.71#ibcon#read 4, iclass 22, count 2 2006.201.22:37:08.71#ibcon#about to read 5, iclass 22, count 2 2006.201.22:37:08.71#ibcon#read 5, iclass 22, count 2 2006.201.22:37:08.71#ibcon#about to read 6, iclass 22, count 2 2006.201.22:37:08.71#ibcon#read 6, iclass 22, count 2 2006.201.22:37:08.71#ibcon#end of sib2, iclass 22, count 2 2006.201.22:37:08.71#ibcon#*after write, iclass 22, count 2 2006.201.22:37:08.71#ibcon#*before return 0, iclass 22, count 2 2006.201.22:37:08.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:08.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:37:08.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.22:37:08.71#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:08.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:08.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:08.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:08.83#ibcon#enter wrdev, iclass 22, count 0 2006.201.22:37:08.83#ibcon#first serial, iclass 22, count 0 2006.201.22:37:08.83#ibcon#enter sib2, iclass 22, count 0 2006.201.22:37:08.83#ibcon#flushed, iclass 22, count 0 2006.201.22:37:08.83#ibcon#about to write, iclass 22, count 0 2006.201.22:37:08.83#ibcon#wrote, iclass 22, count 0 2006.201.22:37:08.83#ibcon#about to read 3, iclass 22, count 0 2006.201.22:37:08.85#ibcon#read 3, iclass 22, count 0 2006.201.22:37:08.85#ibcon#about to read 4, iclass 22, count 0 2006.201.22:37:08.85#ibcon#read 4, iclass 22, count 0 2006.201.22:37:08.85#ibcon#about to read 5, iclass 22, count 0 2006.201.22:37:08.85#ibcon#read 5, iclass 22, count 0 2006.201.22:37:08.85#ibcon#about to read 6, iclass 22, count 0 2006.201.22:37:08.85#ibcon#read 6, iclass 22, count 0 2006.201.22:37:08.85#ibcon#end of sib2, iclass 22, count 0 2006.201.22:37:08.85#ibcon#*mode == 0, iclass 22, count 0 2006.201.22:37:08.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.22:37:08.85#ibcon#[27=USB\r\n] 2006.201.22:37:08.85#ibcon#*before write, iclass 22, count 0 2006.201.22:37:08.85#ibcon#enter sib2, iclass 22, count 0 2006.201.22:37:08.85#ibcon#flushed, iclass 22, count 0 2006.201.22:37:08.85#ibcon#about to write, iclass 22, count 0 2006.201.22:37:08.85#ibcon#wrote, iclass 22, count 0 2006.201.22:37:08.85#ibcon#about to read 3, iclass 22, count 0 2006.201.22:37:08.88#ibcon#read 3, iclass 22, count 0 2006.201.22:37:08.88#ibcon#about to read 4, iclass 22, count 0 2006.201.22:37:08.88#ibcon#read 4, iclass 22, count 0 2006.201.22:37:08.88#ibcon#about to read 5, iclass 22, count 0 2006.201.22:37:08.88#ibcon#read 5, iclass 22, count 0 2006.201.22:37:08.88#ibcon#about to read 6, iclass 22, count 0 2006.201.22:37:08.88#ibcon#read 6, iclass 22, count 0 2006.201.22:37:08.88#ibcon#end of sib2, iclass 22, count 0 2006.201.22:37:08.88#ibcon#*after write, iclass 22, count 0 2006.201.22:37:08.88#ibcon#*before return 0, iclass 22, count 0 2006.201.22:37:08.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:08.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:37:08.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.22:37:08.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.22:37:08.88$vck44/vblo=8,744.99 2006.201.22:37:08.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.22:37:08.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.22:37:08.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:37:08.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:08.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:08.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:08.88#ibcon#enter wrdev, iclass 24, count 0 2006.201.22:37:08.88#ibcon#first serial, iclass 24, count 0 2006.201.22:37:08.88#ibcon#enter sib2, iclass 24, count 0 2006.201.22:37:08.88#ibcon#flushed, iclass 24, count 0 2006.201.22:37:08.88#ibcon#about to write, iclass 24, count 0 2006.201.22:37:08.88#ibcon#wrote, iclass 24, count 0 2006.201.22:37:08.88#ibcon#about to read 3, iclass 24, count 0 2006.201.22:37:08.90#ibcon#read 3, iclass 24, count 0 2006.201.22:37:08.90#ibcon#about to read 4, iclass 24, count 0 2006.201.22:37:08.90#ibcon#read 4, iclass 24, count 0 2006.201.22:37:08.90#ibcon#about to read 5, iclass 24, count 0 2006.201.22:37:08.90#ibcon#read 5, iclass 24, count 0 2006.201.22:37:08.90#ibcon#about to read 6, iclass 24, count 0 2006.201.22:37:08.90#ibcon#read 6, iclass 24, count 0 2006.201.22:37:08.90#ibcon#end of sib2, iclass 24, count 0 2006.201.22:37:08.90#ibcon#*mode == 0, iclass 24, count 0 2006.201.22:37:08.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.22:37:08.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.22:37:08.90#ibcon#*before write, iclass 24, count 0 2006.201.22:37:08.90#ibcon#enter sib2, iclass 24, count 0 2006.201.22:37:08.90#ibcon#flushed, iclass 24, count 0 2006.201.22:37:08.90#ibcon#about to write, iclass 24, count 0 2006.201.22:37:08.90#ibcon#wrote, iclass 24, count 0 2006.201.22:37:08.90#ibcon#about to read 3, iclass 24, count 0 2006.201.22:37:08.94#ibcon#read 3, iclass 24, count 0 2006.201.22:37:08.94#ibcon#about to read 4, iclass 24, count 0 2006.201.22:37:08.94#ibcon#read 4, iclass 24, count 0 2006.201.22:37:08.94#ibcon#about to read 5, iclass 24, count 0 2006.201.22:37:08.94#ibcon#read 5, iclass 24, count 0 2006.201.22:37:08.94#ibcon#about to read 6, iclass 24, count 0 2006.201.22:37:08.94#ibcon#read 6, iclass 24, count 0 2006.201.22:37:08.94#ibcon#end of sib2, iclass 24, count 0 2006.201.22:37:08.94#ibcon#*after write, iclass 24, count 0 2006.201.22:37:08.94#ibcon#*before return 0, iclass 24, count 0 2006.201.22:37:08.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:08.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:37:08.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.22:37:08.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.22:37:08.94$vck44/vb=8,4 2006.201.22:37:08.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.22:37:08.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.22:37:08.94#ibcon#ireg 11 cls_cnt 2 2006.201.22:37:08.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:09.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:09.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:09.00#ibcon#enter wrdev, iclass 26, count 2 2006.201.22:37:09.00#ibcon#first serial, iclass 26, count 2 2006.201.22:37:09.00#ibcon#enter sib2, iclass 26, count 2 2006.201.22:37:09.00#ibcon#flushed, iclass 26, count 2 2006.201.22:37:09.00#ibcon#about to write, iclass 26, count 2 2006.201.22:37:09.00#ibcon#wrote, iclass 26, count 2 2006.201.22:37:09.00#ibcon#about to read 3, iclass 26, count 2 2006.201.22:37:09.02#ibcon#read 3, iclass 26, count 2 2006.201.22:37:09.02#ibcon#about to read 4, iclass 26, count 2 2006.201.22:37:09.02#ibcon#read 4, iclass 26, count 2 2006.201.22:37:09.02#ibcon#about to read 5, iclass 26, count 2 2006.201.22:37:09.02#ibcon#read 5, iclass 26, count 2 2006.201.22:37:09.02#ibcon#about to read 6, iclass 26, count 2 2006.201.22:37:09.02#ibcon#read 6, iclass 26, count 2 2006.201.22:37:09.02#ibcon#end of sib2, iclass 26, count 2 2006.201.22:37:09.02#ibcon#*mode == 0, iclass 26, count 2 2006.201.22:37:09.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.22:37:09.02#ibcon#[27=AT08-04\r\n] 2006.201.22:37:09.02#ibcon#*before write, iclass 26, count 2 2006.201.22:37:09.02#ibcon#enter sib2, iclass 26, count 2 2006.201.22:37:09.02#ibcon#flushed, iclass 26, count 2 2006.201.22:37:09.02#ibcon#about to write, iclass 26, count 2 2006.201.22:37:09.02#ibcon#wrote, iclass 26, count 2 2006.201.22:37:09.02#ibcon#about to read 3, iclass 26, count 2 2006.201.22:37:09.05#ibcon#read 3, iclass 26, count 2 2006.201.22:37:09.05#ibcon#about to read 4, iclass 26, count 2 2006.201.22:37:09.05#ibcon#read 4, iclass 26, count 2 2006.201.22:37:09.05#ibcon#about to read 5, iclass 26, count 2 2006.201.22:37:09.05#ibcon#read 5, iclass 26, count 2 2006.201.22:37:09.05#ibcon#about to read 6, iclass 26, count 2 2006.201.22:37:09.05#ibcon#read 6, iclass 26, count 2 2006.201.22:37:09.05#ibcon#end of sib2, iclass 26, count 2 2006.201.22:37:09.05#ibcon#*after write, iclass 26, count 2 2006.201.22:37:09.05#ibcon#*before return 0, iclass 26, count 2 2006.201.22:37:09.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:09.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:37:09.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.22:37:09.05#ibcon#ireg 7 cls_cnt 0 2006.201.22:37:09.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:09.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:09.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:09.17#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:37:09.17#ibcon#first serial, iclass 26, count 0 2006.201.22:37:09.17#ibcon#enter sib2, iclass 26, count 0 2006.201.22:37:09.17#ibcon#flushed, iclass 26, count 0 2006.201.22:37:09.17#ibcon#about to write, iclass 26, count 0 2006.201.22:37:09.17#ibcon#wrote, iclass 26, count 0 2006.201.22:37:09.17#ibcon#about to read 3, iclass 26, count 0 2006.201.22:37:09.19#ibcon#read 3, iclass 26, count 0 2006.201.22:37:09.19#ibcon#about to read 4, iclass 26, count 0 2006.201.22:37:09.19#ibcon#read 4, iclass 26, count 0 2006.201.22:37:09.19#ibcon#about to read 5, iclass 26, count 0 2006.201.22:37:09.19#ibcon#read 5, iclass 26, count 0 2006.201.22:37:09.19#ibcon#about to read 6, iclass 26, count 0 2006.201.22:37:09.19#ibcon#read 6, iclass 26, count 0 2006.201.22:37:09.19#ibcon#end of sib2, iclass 26, count 0 2006.201.22:37:09.19#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:37:09.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:37:09.19#ibcon#[27=USB\r\n] 2006.201.22:37:09.19#ibcon#*before write, iclass 26, count 0 2006.201.22:37:09.19#ibcon#enter sib2, iclass 26, count 0 2006.201.22:37:09.19#ibcon#flushed, iclass 26, count 0 2006.201.22:37:09.19#ibcon#about to write, iclass 26, count 0 2006.201.22:37:09.19#ibcon#wrote, iclass 26, count 0 2006.201.22:37:09.19#ibcon#about to read 3, iclass 26, count 0 2006.201.22:37:09.22#ibcon#read 3, iclass 26, count 0 2006.201.22:37:09.22#ibcon#about to read 4, iclass 26, count 0 2006.201.22:37:09.22#ibcon#read 4, iclass 26, count 0 2006.201.22:37:09.22#ibcon#about to read 5, iclass 26, count 0 2006.201.22:37:09.22#ibcon#read 5, iclass 26, count 0 2006.201.22:37:09.22#ibcon#about to read 6, iclass 26, count 0 2006.201.22:37:09.22#ibcon#read 6, iclass 26, count 0 2006.201.22:37:09.22#ibcon#end of sib2, iclass 26, count 0 2006.201.22:37:09.22#ibcon#*after write, iclass 26, count 0 2006.201.22:37:09.22#ibcon#*before return 0, iclass 26, count 0 2006.201.22:37:09.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:09.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:37:09.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:37:09.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:37:09.22$vck44/vabw=wide 2006.201.22:37:09.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.22:37:09.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.22:37:09.22#ibcon#ireg 8 cls_cnt 0 2006.201.22:37:09.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:09.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:09.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:09.22#ibcon#enter wrdev, iclass 28, count 0 2006.201.22:37:09.22#ibcon#first serial, iclass 28, count 0 2006.201.22:37:09.22#ibcon#enter sib2, iclass 28, count 0 2006.201.22:37:09.22#ibcon#flushed, iclass 28, count 0 2006.201.22:37:09.22#ibcon#about to write, iclass 28, count 0 2006.201.22:37:09.22#ibcon#wrote, iclass 28, count 0 2006.201.22:37:09.22#ibcon#about to read 3, iclass 28, count 0 2006.201.22:37:09.24#ibcon#read 3, iclass 28, count 0 2006.201.22:37:09.24#ibcon#about to read 4, iclass 28, count 0 2006.201.22:37:09.24#ibcon#read 4, iclass 28, count 0 2006.201.22:37:09.24#ibcon#about to read 5, iclass 28, count 0 2006.201.22:37:09.24#ibcon#read 5, iclass 28, count 0 2006.201.22:37:09.24#ibcon#about to read 6, iclass 28, count 0 2006.201.22:37:09.24#ibcon#read 6, iclass 28, count 0 2006.201.22:37:09.24#ibcon#end of sib2, iclass 28, count 0 2006.201.22:37:09.24#ibcon#*mode == 0, iclass 28, count 0 2006.201.22:37:09.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.22:37:09.24#ibcon#[25=BW32\r\n] 2006.201.22:37:09.24#ibcon#*before write, iclass 28, count 0 2006.201.22:37:09.24#ibcon#enter sib2, iclass 28, count 0 2006.201.22:37:09.24#ibcon#flushed, iclass 28, count 0 2006.201.22:37:09.24#ibcon#about to write, iclass 28, count 0 2006.201.22:37:09.24#ibcon#wrote, iclass 28, count 0 2006.201.22:37:09.24#ibcon#about to read 3, iclass 28, count 0 2006.201.22:37:09.27#ibcon#read 3, iclass 28, count 0 2006.201.22:37:09.27#ibcon#about to read 4, iclass 28, count 0 2006.201.22:37:09.27#ibcon#read 4, iclass 28, count 0 2006.201.22:37:09.27#ibcon#about to read 5, iclass 28, count 0 2006.201.22:37:09.27#ibcon#read 5, iclass 28, count 0 2006.201.22:37:09.27#ibcon#about to read 6, iclass 28, count 0 2006.201.22:37:09.27#ibcon#read 6, iclass 28, count 0 2006.201.22:37:09.27#ibcon#end of sib2, iclass 28, count 0 2006.201.22:37:09.27#ibcon#*after write, iclass 28, count 0 2006.201.22:37:09.27#ibcon#*before return 0, iclass 28, count 0 2006.201.22:37:09.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:09.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:37:09.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.22:37:09.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.22:37:09.27$vck44/vbbw=wide 2006.201.22:37:09.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.22:37:09.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.22:37:09.27#ibcon#ireg 8 cls_cnt 0 2006.201.22:37:09.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:37:09.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:37:09.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:37:09.34#ibcon#enter wrdev, iclass 30, count 0 2006.201.22:37:09.34#ibcon#first serial, iclass 30, count 0 2006.201.22:37:09.34#ibcon#enter sib2, iclass 30, count 0 2006.201.22:37:09.34#ibcon#flushed, iclass 30, count 0 2006.201.22:37:09.34#ibcon#about to write, iclass 30, count 0 2006.201.22:37:09.34#ibcon#wrote, iclass 30, count 0 2006.201.22:37:09.34#ibcon#about to read 3, iclass 30, count 0 2006.201.22:37:09.36#ibcon#read 3, iclass 30, count 0 2006.201.22:37:09.36#ibcon#about to read 4, iclass 30, count 0 2006.201.22:37:09.36#ibcon#read 4, iclass 30, count 0 2006.201.22:37:09.36#ibcon#about to read 5, iclass 30, count 0 2006.201.22:37:09.36#ibcon#read 5, iclass 30, count 0 2006.201.22:37:09.36#ibcon#about to read 6, iclass 30, count 0 2006.201.22:37:09.36#ibcon#read 6, iclass 30, count 0 2006.201.22:37:09.36#ibcon#end of sib2, iclass 30, count 0 2006.201.22:37:09.36#ibcon#*mode == 0, iclass 30, count 0 2006.201.22:37:09.36#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.22:37:09.36#ibcon#[27=BW32\r\n] 2006.201.22:37:09.36#ibcon#*before write, iclass 30, count 0 2006.201.22:37:09.36#ibcon#enter sib2, iclass 30, count 0 2006.201.22:37:09.36#ibcon#flushed, iclass 30, count 0 2006.201.22:37:09.36#ibcon#about to write, iclass 30, count 0 2006.201.22:37:09.36#ibcon#wrote, iclass 30, count 0 2006.201.22:37:09.36#ibcon#about to read 3, iclass 30, count 0 2006.201.22:37:09.39#ibcon#read 3, iclass 30, count 0 2006.201.22:37:09.39#ibcon#about to read 4, iclass 30, count 0 2006.201.22:37:09.39#ibcon#read 4, iclass 30, count 0 2006.201.22:37:09.39#ibcon#about to read 5, iclass 30, count 0 2006.201.22:37:09.39#ibcon#read 5, iclass 30, count 0 2006.201.22:37:09.39#ibcon#about to read 6, iclass 30, count 0 2006.201.22:37:09.39#ibcon#read 6, iclass 30, count 0 2006.201.22:37:09.39#ibcon#end of sib2, iclass 30, count 0 2006.201.22:37:09.39#ibcon#*after write, iclass 30, count 0 2006.201.22:37:09.39#ibcon#*before return 0, iclass 30, count 0 2006.201.22:37:09.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:37:09.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:37:09.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.22:37:09.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.22:37:09.39$setupk4/ifdk4 2006.201.22:37:09.39$ifdk4/lo= 2006.201.22:37:09.39$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.22:37:09.39$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.22:37:09.39$ifdk4/patch= 2006.201.22:37:09.39$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.22:37:09.39$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.22:37:09.39$setupk4/!*+20s 2006.201.22:37:15.32#abcon#<5=/04 1.7 2.9 20.071001001.5\r\n> 2006.201.22:37:15.34#abcon#{5=INTERFACE CLEAR} 2006.201.22:37:15.41#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:37:23.88$setupk4/"tpicd 2006.201.22:37:23.88$setupk4/echo=off 2006.201.22:37:23.88$setupk4/xlog=off 2006.201.22:37:23.88:!2006.201.22:38:17 2006.201.22:38:02.14#trakl#Source acquired 2006.201.22:38:02.14#flagr#flagr/antenna,acquired 2006.201.22:38:17.00:preob 2006.201.22:38:18.14/onsource/TRACKING 2006.201.22:38:18.14:!2006.201.22:38:27 2006.201.22:38:27.00:"tape 2006.201.22:38:27.00:"st=record 2006.201.22:38:27.00:data_valid=on 2006.201.22:38:27.00:midob 2006.201.22:38:27.14/onsource/TRACKING 2006.201.22:38:27.14/wx/20.06,1001.5,100 2006.201.22:38:27.26/cable/+6.4832E-03 2006.201.22:38:28.35/va/01,08,usb,yes,46,50 2006.201.22:38:28.35/va/02,07,usb,yes,50,51 2006.201.22:38:28.35/va/03,08,usb,yes,45,47 2006.201.22:38:28.35/va/04,07,usb,yes,52,54 2006.201.22:38:28.35/va/05,04,usb,yes,46,47 2006.201.22:38:28.35/va/06,05,usb,yes,46,46 2006.201.22:38:28.35/va/07,05,usb,yes,45,47 2006.201.22:38:28.35/va/08,04,usb,yes,45,53 2006.201.22:38:28.58/valo/01,524.99,yes,locked 2006.201.22:38:28.58/valo/02,534.99,yes,locked 2006.201.22:38:28.58/valo/03,564.99,yes,locked 2006.201.22:38:28.58/valo/04,624.99,yes,locked 2006.201.22:38:28.58/valo/05,734.99,yes,locked 2006.201.22:38:28.58/valo/06,814.99,yes,locked 2006.201.22:38:28.58/valo/07,864.99,yes,locked 2006.201.22:38:28.58/valo/08,884.99,yes,locked 2006.201.22:38:29.67/vb/01,04,usb,yes,31,28 2006.201.22:38:29.67/vb/02,05,usb,yes,29,29 2006.201.22:38:29.67/vb/03,04,usb,yes,30,33 2006.201.22:38:29.67/vb/04,05,usb,yes,30,29 2006.201.22:38:29.67/vb/05,04,usb,yes,27,29 2006.201.22:38:29.67/vb/06,04,usb,yes,31,28 2006.201.22:38:29.67/vb/07,04,usb,yes,31,31 2006.201.22:38:29.67/vb/08,04,usb,yes,29,32 2006.201.22:38:29.90/vblo/01,629.99,yes,locked 2006.201.22:38:29.90/vblo/02,634.99,yes,locked 2006.201.22:38:29.90/vblo/03,649.99,yes,locked 2006.201.22:38:29.90/vblo/04,679.99,yes,locked 2006.201.22:38:29.90/vblo/05,709.99,yes,locked 2006.201.22:38:29.90/vblo/06,719.99,yes,locked 2006.201.22:38:29.90/vblo/07,734.99,yes,locked 2006.201.22:38:29.90/vblo/08,744.99,yes,locked 2006.201.22:38:30.05/vabw/8 2006.201.22:38:30.20/vbbw/8 2006.201.22:38:30.29/xfe/off,on,16.0 2006.201.22:38:30.66/ifatt/23,28,28,28 2006.201.22:38:31.07/fmout-gps/S +4.53E-07 2006.201.22:38:31.11:!2006.201.22:39:37 2006.201.22:39:37.00:data_valid=off 2006.201.22:39:37.00:"et 2006.201.22:39:37.00:!+3s 2006.201.22:39:40.02:"tape 2006.201.22:39:40.02:postob 2006.201.22:39:40.22/cable/+6.4826E-03 2006.201.22:39:40.22/wx/20.05,1001.5,100 2006.201.22:39:40.29/fmout-gps/S +4.52E-07 2006.201.22:39:40.29:scan_name=201-2242,jd0607,230 2006.201.22:39:40.29:source=1044+719,104827.62,714335.9,2000.0,cw 2006.201.22:39:42.14#flagr#flagr/antenna,new-source 2006.201.22:39:42.14:checkk5 2006.201.22:39:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.22:39:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.201.22:39:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.201.22:39:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.22:39:44.00/chk_obsdata//k5ts1/T2012238??a.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.22:39:44.38/chk_obsdata//k5ts2/T2012238??b.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.22:39:44.74/chk_obsdata//k5ts3/T2012238??c.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.22:39:45.11/chk_obsdata//k5ts4/T2012238??d.dat file size is correct (nominal:280MB, actual:276MB). 2006.201.22:39:45.79/k5log//k5ts1_log_newline 2006.201.22:39:46.47/k5log//k5ts2_log_newline 2006.201.22:39:47.16/k5log//k5ts3_log_newline 2006.201.22:39:47.85/k5log//k5ts4_log_newline 2006.201.22:39:47.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.22:39:47.87:setupk4=1 2006.201.22:39:47.87$setupk4/echo=on 2006.201.22:39:47.87$setupk4/pcalon 2006.201.22:39:47.87$pcalon/"no phase cal control is implemented here 2006.201.22:39:47.87$setupk4/"tpicd=stop 2006.201.22:39:47.87$setupk4/"rec=synch_on 2006.201.22:39:47.87$setupk4/"rec_mode=128 2006.201.22:39:47.87$setupk4/!* 2006.201.22:39:47.87$setupk4/recpk4 2006.201.22:39:47.87$recpk4/recpatch= 2006.201.22:39:47.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.22:39:47.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.22:39:47.88$setupk4/vck44 2006.201.22:39:47.88$vck44/valo=1,524.99 2006.201.22:39:47.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.22:39:47.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.22:39:47.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:47.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:39:47.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:39:47.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:39:47.88#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:39:47.88#ibcon#first serial, iclass 26, count 0 2006.201.22:39:47.88#ibcon#enter sib2, iclass 26, count 0 2006.201.22:39:47.88#ibcon#flushed, iclass 26, count 0 2006.201.22:39:47.88#ibcon#about to write, iclass 26, count 0 2006.201.22:39:47.88#ibcon#wrote, iclass 26, count 0 2006.201.22:39:47.88#ibcon#about to read 3, iclass 26, count 0 2006.201.22:39:47.92#abcon#{5=INTERFACE CLEAR} 2006.201.22:39:47.92#ibcon#read 3, iclass 26, count 0 2006.201.22:39:47.92#ibcon#about to read 4, iclass 26, count 0 2006.201.22:39:47.92#ibcon#read 4, iclass 26, count 0 2006.201.22:39:47.92#ibcon#about to read 5, iclass 26, count 0 2006.201.22:39:47.92#ibcon#read 5, iclass 26, count 0 2006.201.22:39:47.92#ibcon#about to read 6, iclass 26, count 0 2006.201.22:39:47.92#ibcon#read 6, iclass 26, count 0 2006.201.22:39:47.92#ibcon#end of sib2, iclass 26, count 0 2006.201.22:39:47.92#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:39:47.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:39:47.92#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.22:39:47.92#ibcon#*before write, iclass 26, count 0 2006.201.22:39:47.92#ibcon#enter sib2, iclass 26, count 0 2006.201.22:39:47.92#ibcon#flushed, iclass 26, count 0 2006.201.22:39:47.92#ibcon#about to write, iclass 26, count 0 2006.201.22:39:47.92#ibcon#wrote, iclass 26, count 0 2006.201.22:39:47.92#ibcon#about to read 3, iclass 26, count 0 2006.201.22:39:47.97#ibcon#read 3, iclass 26, count 0 2006.201.22:39:47.97#ibcon#about to read 4, iclass 26, count 0 2006.201.22:39:47.97#ibcon#read 4, iclass 26, count 0 2006.201.22:39:47.97#ibcon#about to read 5, iclass 26, count 0 2006.201.22:39:47.97#ibcon#read 5, iclass 26, count 0 2006.201.22:39:47.97#ibcon#about to read 6, iclass 26, count 0 2006.201.22:39:47.97#ibcon#read 6, iclass 26, count 0 2006.201.22:39:47.97#ibcon#end of sib2, iclass 26, count 0 2006.201.22:39:47.97#ibcon#*after write, iclass 26, count 0 2006.201.22:39:47.97#ibcon#*before return 0, iclass 26, count 0 2006.201.22:39:47.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:39:47.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:39:47.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:39:47.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:39:47.97$vck44/va=1,8 2006.201.22:39:47.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.22:39:47.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.22:39:47.97#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:47.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:47.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:47.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:47.97#ibcon#enter wrdev, iclass 29, count 2 2006.201.22:39:47.97#ibcon#first serial, iclass 29, count 2 2006.201.22:39:47.97#ibcon#enter sib2, iclass 29, count 2 2006.201.22:39:47.97#ibcon#flushed, iclass 29, count 2 2006.201.22:39:47.97#ibcon#about to write, iclass 29, count 2 2006.201.22:39:47.97#ibcon#wrote, iclass 29, count 2 2006.201.22:39:47.97#ibcon#about to read 3, iclass 29, count 2 2006.201.22:39:47.98#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:39:47.99#ibcon#read 3, iclass 29, count 2 2006.201.22:39:47.99#ibcon#about to read 4, iclass 29, count 2 2006.201.22:39:47.99#ibcon#read 4, iclass 29, count 2 2006.201.22:39:47.99#ibcon#about to read 5, iclass 29, count 2 2006.201.22:39:47.99#ibcon#read 5, iclass 29, count 2 2006.201.22:39:47.99#ibcon#about to read 6, iclass 29, count 2 2006.201.22:39:47.99#ibcon#read 6, iclass 29, count 2 2006.201.22:39:47.99#ibcon#end of sib2, iclass 29, count 2 2006.201.22:39:47.99#ibcon#*mode == 0, iclass 29, count 2 2006.201.22:39:47.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.22:39:47.99#ibcon#[25=AT01-08\r\n] 2006.201.22:39:47.99#ibcon#*before write, iclass 29, count 2 2006.201.22:39:47.99#ibcon#enter sib2, iclass 29, count 2 2006.201.22:39:47.99#ibcon#flushed, iclass 29, count 2 2006.201.22:39:47.99#ibcon#about to write, iclass 29, count 2 2006.201.22:39:47.99#ibcon#wrote, iclass 29, count 2 2006.201.22:39:47.99#ibcon#about to read 3, iclass 29, count 2 2006.201.22:39:48.02#ibcon#read 3, iclass 29, count 2 2006.201.22:39:48.02#ibcon#about to read 4, iclass 29, count 2 2006.201.22:39:48.02#ibcon#read 4, iclass 29, count 2 2006.201.22:39:48.02#ibcon#about to read 5, iclass 29, count 2 2006.201.22:39:48.02#ibcon#read 5, iclass 29, count 2 2006.201.22:39:48.02#ibcon#about to read 6, iclass 29, count 2 2006.201.22:39:48.02#ibcon#read 6, iclass 29, count 2 2006.201.22:39:48.02#ibcon#end of sib2, iclass 29, count 2 2006.201.22:39:48.02#ibcon#*after write, iclass 29, count 2 2006.201.22:39:48.02#ibcon#*before return 0, iclass 29, count 2 2006.201.22:39:48.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:48.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:48.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.22:39:48.02#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:48.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:48.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:48.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:48.14#ibcon#enter wrdev, iclass 29, count 0 2006.201.22:39:48.14#ibcon#first serial, iclass 29, count 0 2006.201.22:39:48.14#ibcon#enter sib2, iclass 29, count 0 2006.201.22:39:48.14#ibcon#flushed, iclass 29, count 0 2006.201.22:39:48.14#ibcon#about to write, iclass 29, count 0 2006.201.22:39:48.14#ibcon#wrote, iclass 29, count 0 2006.201.22:39:48.14#ibcon#about to read 3, iclass 29, count 0 2006.201.22:39:48.16#ibcon#read 3, iclass 29, count 0 2006.201.22:39:48.16#ibcon#about to read 4, iclass 29, count 0 2006.201.22:39:48.16#ibcon#read 4, iclass 29, count 0 2006.201.22:39:48.16#ibcon#about to read 5, iclass 29, count 0 2006.201.22:39:48.16#ibcon#read 5, iclass 29, count 0 2006.201.22:39:48.16#ibcon#about to read 6, iclass 29, count 0 2006.201.22:39:48.16#ibcon#read 6, iclass 29, count 0 2006.201.22:39:48.16#ibcon#end of sib2, iclass 29, count 0 2006.201.22:39:48.16#ibcon#*mode == 0, iclass 29, count 0 2006.201.22:39:48.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.22:39:48.16#ibcon#[25=USB\r\n] 2006.201.22:39:48.16#ibcon#*before write, iclass 29, count 0 2006.201.22:39:48.16#ibcon#enter sib2, iclass 29, count 0 2006.201.22:39:48.16#ibcon#flushed, iclass 29, count 0 2006.201.22:39:48.16#ibcon#about to write, iclass 29, count 0 2006.201.22:39:48.16#ibcon#wrote, iclass 29, count 0 2006.201.22:39:48.16#ibcon#about to read 3, iclass 29, count 0 2006.201.22:39:48.19#ibcon#read 3, iclass 29, count 0 2006.201.22:39:48.19#ibcon#about to read 4, iclass 29, count 0 2006.201.22:39:48.19#ibcon#read 4, iclass 29, count 0 2006.201.22:39:48.19#ibcon#about to read 5, iclass 29, count 0 2006.201.22:39:48.19#ibcon#read 5, iclass 29, count 0 2006.201.22:39:48.19#ibcon#about to read 6, iclass 29, count 0 2006.201.22:39:48.19#ibcon#read 6, iclass 29, count 0 2006.201.22:39:48.19#ibcon#end of sib2, iclass 29, count 0 2006.201.22:39:48.19#ibcon#*after write, iclass 29, count 0 2006.201.22:39:48.19#ibcon#*before return 0, iclass 29, count 0 2006.201.22:39:48.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:48.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:48.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.22:39:48.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.22:39:48.19$vck44/valo=2,534.99 2006.201.22:39:48.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.22:39:48.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.22:39:48.19#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:48.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:48.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:48.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:48.19#ibcon#enter wrdev, iclass 31, count 0 2006.201.22:39:48.19#ibcon#first serial, iclass 31, count 0 2006.201.22:39:48.19#ibcon#enter sib2, iclass 31, count 0 2006.201.22:39:48.19#ibcon#flushed, iclass 31, count 0 2006.201.22:39:48.19#ibcon#about to write, iclass 31, count 0 2006.201.22:39:48.19#ibcon#wrote, iclass 31, count 0 2006.201.22:39:48.19#ibcon#about to read 3, iclass 31, count 0 2006.201.22:39:48.21#ibcon#read 3, iclass 31, count 0 2006.201.22:39:48.21#ibcon#about to read 4, iclass 31, count 0 2006.201.22:39:48.21#ibcon#read 4, iclass 31, count 0 2006.201.22:39:48.21#ibcon#about to read 5, iclass 31, count 0 2006.201.22:39:48.21#ibcon#read 5, iclass 31, count 0 2006.201.22:39:48.21#ibcon#about to read 6, iclass 31, count 0 2006.201.22:39:48.21#ibcon#read 6, iclass 31, count 0 2006.201.22:39:48.21#ibcon#end of sib2, iclass 31, count 0 2006.201.22:39:48.21#ibcon#*mode == 0, iclass 31, count 0 2006.201.22:39:48.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.22:39:48.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.22:39:48.21#ibcon#*before write, iclass 31, count 0 2006.201.22:39:48.21#ibcon#enter sib2, iclass 31, count 0 2006.201.22:39:48.21#ibcon#flushed, iclass 31, count 0 2006.201.22:39:48.21#ibcon#about to write, iclass 31, count 0 2006.201.22:39:48.21#ibcon#wrote, iclass 31, count 0 2006.201.22:39:48.21#ibcon#about to read 3, iclass 31, count 0 2006.201.22:39:48.26#ibcon#read 3, iclass 31, count 0 2006.201.22:39:48.26#ibcon#about to read 4, iclass 31, count 0 2006.201.22:39:48.26#ibcon#read 4, iclass 31, count 0 2006.201.22:39:48.26#ibcon#about to read 5, iclass 31, count 0 2006.201.22:39:48.26#ibcon#read 5, iclass 31, count 0 2006.201.22:39:48.26#ibcon#about to read 6, iclass 31, count 0 2006.201.22:39:48.26#ibcon#read 6, iclass 31, count 0 2006.201.22:39:48.26#ibcon#end of sib2, iclass 31, count 0 2006.201.22:39:48.26#ibcon#*after write, iclass 31, count 0 2006.201.22:39:48.26#ibcon#*before return 0, iclass 31, count 0 2006.201.22:39:48.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:48.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:48.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.22:39:48.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.22:39:48.26$vck44/va=2,7 2006.201.22:39:48.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.22:39:48.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.22:39:48.26#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:48.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:48.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:48.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:48.31#ibcon#enter wrdev, iclass 33, count 2 2006.201.22:39:48.31#ibcon#first serial, iclass 33, count 2 2006.201.22:39:48.31#ibcon#enter sib2, iclass 33, count 2 2006.201.22:39:48.31#ibcon#flushed, iclass 33, count 2 2006.201.22:39:48.31#ibcon#about to write, iclass 33, count 2 2006.201.22:39:48.31#ibcon#wrote, iclass 33, count 2 2006.201.22:39:48.31#ibcon#about to read 3, iclass 33, count 2 2006.201.22:39:48.33#ibcon#read 3, iclass 33, count 2 2006.201.22:39:48.33#ibcon#about to read 4, iclass 33, count 2 2006.201.22:39:48.33#ibcon#read 4, iclass 33, count 2 2006.201.22:39:48.33#ibcon#about to read 5, iclass 33, count 2 2006.201.22:39:48.33#ibcon#read 5, iclass 33, count 2 2006.201.22:39:48.33#ibcon#about to read 6, iclass 33, count 2 2006.201.22:39:48.33#ibcon#read 6, iclass 33, count 2 2006.201.22:39:48.33#ibcon#end of sib2, iclass 33, count 2 2006.201.22:39:48.33#ibcon#*mode == 0, iclass 33, count 2 2006.201.22:39:48.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.22:39:48.33#ibcon#[25=AT02-07\r\n] 2006.201.22:39:48.33#ibcon#*before write, iclass 33, count 2 2006.201.22:39:48.33#ibcon#enter sib2, iclass 33, count 2 2006.201.22:39:48.33#ibcon#flushed, iclass 33, count 2 2006.201.22:39:48.33#ibcon#about to write, iclass 33, count 2 2006.201.22:39:48.33#ibcon#wrote, iclass 33, count 2 2006.201.22:39:48.33#ibcon#about to read 3, iclass 33, count 2 2006.201.22:39:48.36#ibcon#read 3, iclass 33, count 2 2006.201.22:39:48.36#ibcon#about to read 4, iclass 33, count 2 2006.201.22:39:48.36#ibcon#read 4, iclass 33, count 2 2006.201.22:39:48.36#ibcon#about to read 5, iclass 33, count 2 2006.201.22:39:48.36#ibcon#read 5, iclass 33, count 2 2006.201.22:39:48.36#ibcon#about to read 6, iclass 33, count 2 2006.201.22:39:48.36#ibcon#read 6, iclass 33, count 2 2006.201.22:39:48.36#ibcon#end of sib2, iclass 33, count 2 2006.201.22:39:48.36#ibcon#*after write, iclass 33, count 2 2006.201.22:39:48.36#ibcon#*before return 0, iclass 33, count 2 2006.201.22:39:48.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:48.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:48.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.22:39:48.36#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:48.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:48.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:48.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:48.48#ibcon#enter wrdev, iclass 33, count 0 2006.201.22:39:48.48#ibcon#first serial, iclass 33, count 0 2006.201.22:39:48.48#ibcon#enter sib2, iclass 33, count 0 2006.201.22:39:48.48#ibcon#flushed, iclass 33, count 0 2006.201.22:39:48.48#ibcon#about to write, iclass 33, count 0 2006.201.22:39:48.48#ibcon#wrote, iclass 33, count 0 2006.201.22:39:48.48#ibcon#about to read 3, iclass 33, count 0 2006.201.22:39:48.50#ibcon#read 3, iclass 33, count 0 2006.201.22:39:48.50#ibcon#about to read 4, iclass 33, count 0 2006.201.22:39:48.50#ibcon#read 4, iclass 33, count 0 2006.201.22:39:48.50#ibcon#about to read 5, iclass 33, count 0 2006.201.22:39:48.50#ibcon#read 5, iclass 33, count 0 2006.201.22:39:48.50#ibcon#about to read 6, iclass 33, count 0 2006.201.22:39:48.50#ibcon#read 6, iclass 33, count 0 2006.201.22:39:48.50#ibcon#end of sib2, iclass 33, count 0 2006.201.22:39:48.50#ibcon#*mode == 0, iclass 33, count 0 2006.201.22:39:48.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.22:39:48.50#ibcon#[25=USB\r\n] 2006.201.22:39:48.50#ibcon#*before write, iclass 33, count 0 2006.201.22:39:48.50#ibcon#enter sib2, iclass 33, count 0 2006.201.22:39:48.50#ibcon#flushed, iclass 33, count 0 2006.201.22:39:48.50#ibcon#about to write, iclass 33, count 0 2006.201.22:39:48.50#ibcon#wrote, iclass 33, count 0 2006.201.22:39:48.50#ibcon#about to read 3, iclass 33, count 0 2006.201.22:39:48.53#ibcon#read 3, iclass 33, count 0 2006.201.22:39:48.53#ibcon#about to read 4, iclass 33, count 0 2006.201.22:39:48.53#ibcon#read 4, iclass 33, count 0 2006.201.22:39:48.53#ibcon#about to read 5, iclass 33, count 0 2006.201.22:39:48.53#ibcon#read 5, iclass 33, count 0 2006.201.22:39:48.53#ibcon#about to read 6, iclass 33, count 0 2006.201.22:39:48.53#ibcon#read 6, iclass 33, count 0 2006.201.22:39:48.53#ibcon#end of sib2, iclass 33, count 0 2006.201.22:39:48.53#ibcon#*after write, iclass 33, count 0 2006.201.22:39:48.53#ibcon#*before return 0, iclass 33, count 0 2006.201.22:39:48.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:48.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:48.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.22:39:48.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.22:39:48.53$vck44/valo=3,564.99 2006.201.22:39:48.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.22:39:48.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.22:39:48.53#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:48.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:48.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:48.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:48.53#ibcon#enter wrdev, iclass 35, count 0 2006.201.22:39:48.53#ibcon#first serial, iclass 35, count 0 2006.201.22:39:48.53#ibcon#enter sib2, iclass 35, count 0 2006.201.22:39:48.53#ibcon#flushed, iclass 35, count 0 2006.201.22:39:48.53#ibcon#about to write, iclass 35, count 0 2006.201.22:39:48.53#ibcon#wrote, iclass 35, count 0 2006.201.22:39:48.53#ibcon#about to read 3, iclass 35, count 0 2006.201.22:39:48.55#ibcon#read 3, iclass 35, count 0 2006.201.22:39:48.55#ibcon#about to read 4, iclass 35, count 0 2006.201.22:39:48.55#ibcon#read 4, iclass 35, count 0 2006.201.22:39:48.55#ibcon#about to read 5, iclass 35, count 0 2006.201.22:39:48.55#ibcon#read 5, iclass 35, count 0 2006.201.22:39:48.55#ibcon#about to read 6, iclass 35, count 0 2006.201.22:39:48.55#ibcon#read 6, iclass 35, count 0 2006.201.22:39:48.55#ibcon#end of sib2, iclass 35, count 0 2006.201.22:39:48.55#ibcon#*mode == 0, iclass 35, count 0 2006.201.22:39:48.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.22:39:48.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.22:39:48.55#ibcon#*before write, iclass 35, count 0 2006.201.22:39:48.55#ibcon#enter sib2, iclass 35, count 0 2006.201.22:39:48.55#ibcon#flushed, iclass 35, count 0 2006.201.22:39:48.55#ibcon#about to write, iclass 35, count 0 2006.201.22:39:48.55#ibcon#wrote, iclass 35, count 0 2006.201.22:39:48.55#ibcon#about to read 3, iclass 35, count 0 2006.201.22:39:48.59#ibcon#read 3, iclass 35, count 0 2006.201.22:39:48.59#ibcon#about to read 4, iclass 35, count 0 2006.201.22:39:48.59#ibcon#read 4, iclass 35, count 0 2006.201.22:39:48.59#ibcon#about to read 5, iclass 35, count 0 2006.201.22:39:48.59#ibcon#read 5, iclass 35, count 0 2006.201.22:39:48.59#ibcon#about to read 6, iclass 35, count 0 2006.201.22:39:48.59#ibcon#read 6, iclass 35, count 0 2006.201.22:39:48.59#ibcon#end of sib2, iclass 35, count 0 2006.201.22:39:48.59#ibcon#*after write, iclass 35, count 0 2006.201.22:39:48.59#ibcon#*before return 0, iclass 35, count 0 2006.201.22:39:48.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:48.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:48.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.22:39:48.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.22:39:48.59$vck44/va=3,8 2006.201.22:39:48.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.22:39:48.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.22:39:48.59#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:48.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:48.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:48.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:48.65#ibcon#enter wrdev, iclass 37, count 2 2006.201.22:39:48.65#ibcon#first serial, iclass 37, count 2 2006.201.22:39:48.65#ibcon#enter sib2, iclass 37, count 2 2006.201.22:39:48.65#ibcon#flushed, iclass 37, count 2 2006.201.22:39:48.65#ibcon#about to write, iclass 37, count 2 2006.201.22:39:48.65#ibcon#wrote, iclass 37, count 2 2006.201.22:39:48.65#ibcon#about to read 3, iclass 37, count 2 2006.201.22:39:48.67#ibcon#read 3, iclass 37, count 2 2006.201.22:39:48.67#ibcon#about to read 4, iclass 37, count 2 2006.201.22:39:48.67#ibcon#read 4, iclass 37, count 2 2006.201.22:39:48.67#ibcon#about to read 5, iclass 37, count 2 2006.201.22:39:48.67#ibcon#read 5, iclass 37, count 2 2006.201.22:39:48.67#ibcon#about to read 6, iclass 37, count 2 2006.201.22:39:48.67#ibcon#read 6, iclass 37, count 2 2006.201.22:39:48.67#ibcon#end of sib2, iclass 37, count 2 2006.201.22:39:48.67#ibcon#*mode == 0, iclass 37, count 2 2006.201.22:39:48.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.22:39:48.67#ibcon#[25=AT03-08\r\n] 2006.201.22:39:48.67#ibcon#*before write, iclass 37, count 2 2006.201.22:39:48.67#ibcon#enter sib2, iclass 37, count 2 2006.201.22:39:48.67#ibcon#flushed, iclass 37, count 2 2006.201.22:39:48.67#ibcon#about to write, iclass 37, count 2 2006.201.22:39:48.67#ibcon#wrote, iclass 37, count 2 2006.201.22:39:48.67#ibcon#about to read 3, iclass 37, count 2 2006.201.22:39:48.70#ibcon#read 3, iclass 37, count 2 2006.201.22:39:48.70#ibcon#about to read 4, iclass 37, count 2 2006.201.22:39:48.70#ibcon#read 4, iclass 37, count 2 2006.201.22:39:48.70#ibcon#about to read 5, iclass 37, count 2 2006.201.22:39:48.70#ibcon#read 5, iclass 37, count 2 2006.201.22:39:48.70#ibcon#about to read 6, iclass 37, count 2 2006.201.22:39:48.70#ibcon#read 6, iclass 37, count 2 2006.201.22:39:48.70#ibcon#end of sib2, iclass 37, count 2 2006.201.22:39:48.70#ibcon#*after write, iclass 37, count 2 2006.201.22:39:48.70#ibcon#*before return 0, iclass 37, count 2 2006.201.22:39:48.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:48.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:48.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.22:39:48.70#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:48.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:48.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:48.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:48.82#ibcon#enter wrdev, iclass 37, count 0 2006.201.22:39:48.82#ibcon#first serial, iclass 37, count 0 2006.201.22:39:48.82#ibcon#enter sib2, iclass 37, count 0 2006.201.22:39:48.82#ibcon#flushed, iclass 37, count 0 2006.201.22:39:48.82#ibcon#about to write, iclass 37, count 0 2006.201.22:39:48.82#ibcon#wrote, iclass 37, count 0 2006.201.22:39:48.82#ibcon#about to read 3, iclass 37, count 0 2006.201.22:39:48.84#ibcon#read 3, iclass 37, count 0 2006.201.22:39:48.84#ibcon#about to read 4, iclass 37, count 0 2006.201.22:39:48.84#ibcon#read 4, iclass 37, count 0 2006.201.22:39:48.84#ibcon#about to read 5, iclass 37, count 0 2006.201.22:39:48.84#ibcon#read 5, iclass 37, count 0 2006.201.22:39:48.84#ibcon#about to read 6, iclass 37, count 0 2006.201.22:39:48.84#ibcon#read 6, iclass 37, count 0 2006.201.22:39:48.84#ibcon#end of sib2, iclass 37, count 0 2006.201.22:39:48.84#ibcon#*mode == 0, iclass 37, count 0 2006.201.22:39:48.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.22:39:48.84#ibcon#[25=USB\r\n] 2006.201.22:39:48.84#ibcon#*before write, iclass 37, count 0 2006.201.22:39:48.84#ibcon#enter sib2, iclass 37, count 0 2006.201.22:39:48.84#ibcon#flushed, iclass 37, count 0 2006.201.22:39:48.84#ibcon#about to write, iclass 37, count 0 2006.201.22:39:48.84#ibcon#wrote, iclass 37, count 0 2006.201.22:39:48.84#ibcon#about to read 3, iclass 37, count 0 2006.201.22:39:48.87#ibcon#read 3, iclass 37, count 0 2006.201.22:39:48.87#ibcon#about to read 4, iclass 37, count 0 2006.201.22:39:48.87#ibcon#read 4, iclass 37, count 0 2006.201.22:39:48.87#ibcon#about to read 5, iclass 37, count 0 2006.201.22:39:48.87#ibcon#read 5, iclass 37, count 0 2006.201.22:39:48.87#ibcon#about to read 6, iclass 37, count 0 2006.201.22:39:48.87#ibcon#read 6, iclass 37, count 0 2006.201.22:39:48.87#ibcon#end of sib2, iclass 37, count 0 2006.201.22:39:48.87#ibcon#*after write, iclass 37, count 0 2006.201.22:39:48.87#ibcon#*before return 0, iclass 37, count 0 2006.201.22:39:48.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:48.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:48.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.22:39:48.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.22:39:48.87$vck44/valo=4,624.99 2006.201.22:39:48.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.22:39:48.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.22:39:48.87#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:48.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:48.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:48.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:48.87#ibcon#enter wrdev, iclass 39, count 0 2006.201.22:39:48.87#ibcon#first serial, iclass 39, count 0 2006.201.22:39:48.87#ibcon#enter sib2, iclass 39, count 0 2006.201.22:39:48.87#ibcon#flushed, iclass 39, count 0 2006.201.22:39:48.87#ibcon#about to write, iclass 39, count 0 2006.201.22:39:48.87#ibcon#wrote, iclass 39, count 0 2006.201.22:39:48.87#ibcon#about to read 3, iclass 39, count 0 2006.201.22:39:48.89#ibcon#read 3, iclass 39, count 0 2006.201.22:39:48.89#ibcon#about to read 4, iclass 39, count 0 2006.201.22:39:48.89#ibcon#read 4, iclass 39, count 0 2006.201.22:39:48.89#ibcon#about to read 5, iclass 39, count 0 2006.201.22:39:48.89#ibcon#read 5, iclass 39, count 0 2006.201.22:39:48.89#ibcon#about to read 6, iclass 39, count 0 2006.201.22:39:48.89#ibcon#read 6, iclass 39, count 0 2006.201.22:39:48.89#ibcon#end of sib2, iclass 39, count 0 2006.201.22:39:48.89#ibcon#*mode == 0, iclass 39, count 0 2006.201.22:39:48.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.22:39:48.89#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.22:39:48.89#ibcon#*before write, iclass 39, count 0 2006.201.22:39:48.89#ibcon#enter sib2, iclass 39, count 0 2006.201.22:39:48.89#ibcon#flushed, iclass 39, count 0 2006.201.22:39:48.89#ibcon#about to write, iclass 39, count 0 2006.201.22:39:48.89#ibcon#wrote, iclass 39, count 0 2006.201.22:39:48.89#ibcon#about to read 3, iclass 39, count 0 2006.201.22:39:48.94#ibcon#read 3, iclass 39, count 0 2006.201.22:39:48.94#ibcon#about to read 4, iclass 39, count 0 2006.201.22:39:48.94#ibcon#read 4, iclass 39, count 0 2006.201.22:39:48.94#ibcon#about to read 5, iclass 39, count 0 2006.201.22:39:48.94#ibcon#read 5, iclass 39, count 0 2006.201.22:39:48.94#ibcon#about to read 6, iclass 39, count 0 2006.201.22:39:48.94#ibcon#read 6, iclass 39, count 0 2006.201.22:39:48.94#ibcon#end of sib2, iclass 39, count 0 2006.201.22:39:48.94#ibcon#*after write, iclass 39, count 0 2006.201.22:39:48.94#ibcon#*before return 0, iclass 39, count 0 2006.201.22:39:48.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:48.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:48.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.22:39:48.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.22:39:48.94$vck44/va=4,7 2006.201.22:39:48.94#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.22:39:48.94#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.22:39:48.94#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:48.94#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:48.99#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:48.99#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:48.99#ibcon#enter wrdev, iclass 2, count 2 2006.201.22:39:48.99#ibcon#first serial, iclass 2, count 2 2006.201.22:39:48.99#ibcon#enter sib2, iclass 2, count 2 2006.201.22:39:48.99#ibcon#flushed, iclass 2, count 2 2006.201.22:39:48.99#ibcon#about to write, iclass 2, count 2 2006.201.22:39:48.99#ibcon#wrote, iclass 2, count 2 2006.201.22:39:48.99#ibcon#about to read 3, iclass 2, count 2 2006.201.22:39:49.01#ibcon#read 3, iclass 2, count 2 2006.201.22:39:49.01#ibcon#about to read 4, iclass 2, count 2 2006.201.22:39:49.01#ibcon#read 4, iclass 2, count 2 2006.201.22:39:49.01#ibcon#about to read 5, iclass 2, count 2 2006.201.22:39:49.01#ibcon#read 5, iclass 2, count 2 2006.201.22:39:49.01#ibcon#about to read 6, iclass 2, count 2 2006.201.22:39:49.01#ibcon#read 6, iclass 2, count 2 2006.201.22:39:49.01#ibcon#end of sib2, iclass 2, count 2 2006.201.22:39:49.01#ibcon#*mode == 0, iclass 2, count 2 2006.201.22:39:49.01#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.22:39:49.01#ibcon#[25=AT04-07\r\n] 2006.201.22:39:49.01#ibcon#*before write, iclass 2, count 2 2006.201.22:39:49.01#ibcon#enter sib2, iclass 2, count 2 2006.201.22:39:49.01#ibcon#flushed, iclass 2, count 2 2006.201.22:39:49.01#ibcon#about to write, iclass 2, count 2 2006.201.22:39:49.01#ibcon#wrote, iclass 2, count 2 2006.201.22:39:49.01#ibcon#about to read 3, iclass 2, count 2 2006.201.22:39:49.04#ibcon#read 3, iclass 2, count 2 2006.201.22:39:49.04#ibcon#about to read 4, iclass 2, count 2 2006.201.22:39:49.04#ibcon#read 4, iclass 2, count 2 2006.201.22:39:49.04#ibcon#about to read 5, iclass 2, count 2 2006.201.22:39:49.04#ibcon#read 5, iclass 2, count 2 2006.201.22:39:49.04#ibcon#about to read 6, iclass 2, count 2 2006.201.22:39:49.04#ibcon#read 6, iclass 2, count 2 2006.201.22:39:49.04#ibcon#end of sib2, iclass 2, count 2 2006.201.22:39:49.04#ibcon#*after write, iclass 2, count 2 2006.201.22:39:49.04#ibcon#*before return 0, iclass 2, count 2 2006.201.22:39:49.04#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:49.04#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:49.04#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.22:39:49.04#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:49.04#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:49.16#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:49.16#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:49.16#ibcon#enter wrdev, iclass 2, count 0 2006.201.22:39:49.16#ibcon#first serial, iclass 2, count 0 2006.201.22:39:49.16#ibcon#enter sib2, iclass 2, count 0 2006.201.22:39:49.16#ibcon#flushed, iclass 2, count 0 2006.201.22:39:49.16#ibcon#about to write, iclass 2, count 0 2006.201.22:39:49.16#ibcon#wrote, iclass 2, count 0 2006.201.22:39:49.16#ibcon#about to read 3, iclass 2, count 0 2006.201.22:39:49.18#ibcon#read 3, iclass 2, count 0 2006.201.22:39:49.18#ibcon#about to read 4, iclass 2, count 0 2006.201.22:39:49.18#ibcon#read 4, iclass 2, count 0 2006.201.22:39:49.18#ibcon#about to read 5, iclass 2, count 0 2006.201.22:39:49.18#ibcon#read 5, iclass 2, count 0 2006.201.22:39:49.18#ibcon#about to read 6, iclass 2, count 0 2006.201.22:39:49.18#ibcon#read 6, iclass 2, count 0 2006.201.22:39:49.18#ibcon#end of sib2, iclass 2, count 0 2006.201.22:39:49.18#ibcon#*mode == 0, iclass 2, count 0 2006.201.22:39:49.18#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.22:39:49.18#ibcon#[25=USB\r\n] 2006.201.22:39:49.18#ibcon#*before write, iclass 2, count 0 2006.201.22:39:49.18#ibcon#enter sib2, iclass 2, count 0 2006.201.22:39:49.18#ibcon#flushed, iclass 2, count 0 2006.201.22:39:49.18#ibcon#about to write, iclass 2, count 0 2006.201.22:39:49.18#ibcon#wrote, iclass 2, count 0 2006.201.22:39:49.18#ibcon#about to read 3, iclass 2, count 0 2006.201.22:39:49.21#ibcon#read 3, iclass 2, count 0 2006.201.22:39:49.21#ibcon#about to read 4, iclass 2, count 0 2006.201.22:39:49.21#ibcon#read 4, iclass 2, count 0 2006.201.22:39:49.21#ibcon#about to read 5, iclass 2, count 0 2006.201.22:39:49.21#ibcon#read 5, iclass 2, count 0 2006.201.22:39:49.21#ibcon#about to read 6, iclass 2, count 0 2006.201.22:39:49.21#ibcon#read 6, iclass 2, count 0 2006.201.22:39:49.21#ibcon#end of sib2, iclass 2, count 0 2006.201.22:39:49.21#ibcon#*after write, iclass 2, count 0 2006.201.22:39:49.21#ibcon#*before return 0, iclass 2, count 0 2006.201.22:39:49.21#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:49.21#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:49.21#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.22:39:49.21#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.22:39:49.21$vck44/valo=5,734.99 2006.201.22:39:49.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.22:39:49.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.22:39:49.21#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:49.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:49.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:49.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:49.21#ibcon#enter wrdev, iclass 5, count 0 2006.201.22:39:49.21#ibcon#first serial, iclass 5, count 0 2006.201.22:39:49.21#ibcon#enter sib2, iclass 5, count 0 2006.201.22:39:49.21#ibcon#flushed, iclass 5, count 0 2006.201.22:39:49.21#ibcon#about to write, iclass 5, count 0 2006.201.22:39:49.21#ibcon#wrote, iclass 5, count 0 2006.201.22:39:49.21#ibcon#about to read 3, iclass 5, count 0 2006.201.22:39:49.23#ibcon#read 3, iclass 5, count 0 2006.201.22:39:49.23#ibcon#about to read 4, iclass 5, count 0 2006.201.22:39:49.23#ibcon#read 4, iclass 5, count 0 2006.201.22:39:49.23#ibcon#about to read 5, iclass 5, count 0 2006.201.22:39:49.23#ibcon#read 5, iclass 5, count 0 2006.201.22:39:49.23#ibcon#about to read 6, iclass 5, count 0 2006.201.22:39:49.23#ibcon#read 6, iclass 5, count 0 2006.201.22:39:49.23#ibcon#end of sib2, iclass 5, count 0 2006.201.22:39:49.23#ibcon#*mode == 0, iclass 5, count 0 2006.201.22:39:49.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.22:39:49.23#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.22:39:49.23#ibcon#*before write, iclass 5, count 0 2006.201.22:39:49.23#ibcon#enter sib2, iclass 5, count 0 2006.201.22:39:49.23#ibcon#flushed, iclass 5, count 0 2006.201.22:39:49.23#ibcon#about to write, iclass 5, count 0 2006.201.22:39:49.23#ibcon#wrote, iclass 5, count 0 2006.201.22:39:49.23#ibcon#about to read 3, iclass 5, count 0 2006.201.22:39:49.27#ibcon#read 3, iclass 5, count 0 2006.201.22:39:49.27#ibcon#about to read 4, iclass 5, count 0 2006.201.22:39:49.27#ibcon#read 4, iclass 5, count 0 2006.201.22:39:49.27#ibcon#about to read 5, iclass 5, count 0 2006.201.22:39:49.27#ibcon#read 5, iclass 5, count 0 2006.201.22:39:49.27#ibcon#about to read 6, iclass 5, count 0 2006.201.22:39:49.27#ibcon#read 6, iclass 5, count 0 2006.201.22:39:49.27#ibcon#end of sib2, iclass 5, count 0 2006.201.22:39:49.27#ibcon#*after write, iclass 5, count 0 2006.201.22:39:49.27#ibcon#*before return 0, iclass 5, count 0 2006.201.22:39:49.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:49.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:49.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.22:39:49.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.22:39:49.27$vck44/va=5,4 2006.201.22:39:49.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.22:39:49.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.22:39:49.27#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:49.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:49.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:49.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:49.33#ibcon#enter wrdev, iclass 7, count 2 2006.201.22:39:49.33#ibcon#first serial, iclass 7, count 2 2006.201.22:39:49.33#ibcon#enter sib2, iclass 7, count 2 2006.201.22:39:49.33#ibcon#flushed, iclass 7, count 2 2006.201.22:39:49.33#ibcon#about to write, iclass 7, count 2 2006.201.22:39:49.33#ibcon#wrote, iclass 7, count 2 2006.201.22:39:49.33#ibcon#about to read 3, iclass 7, count 2 2006.201.22:39:49.35#ibcon#read 3, iclass 7, count 2 2006.201.22:39:49.35#ibcon#about to read 4, iclass 7, count 2 2006.201.22:39:49.35#ibcon#read 4, iclass 7, count 2 2006.201.22:39:49.35#ibcon#about to read 5, iclass 7, count 2 2006.201.22:39:49.35#ibcon#read 5, iclass 7, count 2 2006.201.22:39:49.35#ibcon#about to read 6, iclass 7, count 2 2006.201.22:39:49.35#ibcon#read 6, iclass 7, count 2 2006.201.22:39:49.35#ibcon#end of sib2, iclass 7, count 2 2006.201.22:39:49.35#ibcon#*mode == 0, iclass 7, count 2 2006.201.22:39:49.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.22:39:49.35#ibcon#[25=AT05-04\r\n] 2006.201.22:39:49.35#ibcon#*before write, iclass 7, count 2 2006.201.22:39:49.35#ibcon#enter sib2, iclass 7, count 2 2006.201.22:39:49.35#ibcon#flushed, iclass 7, count 2 2006.201.22:39:49.35#ibcon#about to write, iclass 7, count 2 2006.201.22:39:49.35#ibcon#wrote, iclass 7, count 2 2006.201.22:39:49.35#ibcon#about to read 3, iclass 7, count 2 2006.201.22:39:49.38#ibcon#read 3, iclass 7, count 2 2006.201.22:39:49.38#ibcon#about to read 4, iclass 7, count 2 2006.201.22:39:49.38#ibcon#read 4, iclass 7, count 2 2006.201.22:39:49.38#ibcon#about to read 5, iclass 7, count 2 2006.201.22:39:49.38#ibcon#read 5, iclass 7, count 2 2006.201.22:39:49.38#ibcon#about to read 6, iclass 7, count 2 2006.201.22:39:49.38#ibcon#read 6, iclass 7, count 2 2006.201.22:39:49.38#ibcon#end of sib2, iclass 7, count 2 2006.201.22:39:49.38#ibcon#*after write, iclass 7, count 2 2006.201.22:39:49.38#ibcon#*before return 0, iclass 7, count 2 2006.201.22:39:49.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:49.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:49.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.22:39:49.38#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:49.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:49.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:49.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:49.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.22:39:49.50#ibcon#first serial, iclass 7, count 0 2006.201.22:39:49.50#ibcon#enter sib2, iclass 7, count 0 2006.201.22:39:49.50#ibcon#flushed, iclass 7, count 0 2006.201.22:39:49.50#ibcon#about to write, iclass 7, count 0 2006.201.22:39:49.50#ibcon#wrote, iclass 7, count 0 2006.201.22:39:49.50#ibcon#about to read 3, iclass 7, count 0 2006.201.22:39:49.52#ibcon#read 3, iclass 7, count 0 2006.201.22:39:49.52#ibcon#about to read 4, iclass 7, count 0 2006.201.22:39:49.52#ibcon#read 4, iclass 7, count 0 2006.201.22:39:49.52#ibcon#about to read 5, iclass 7, count 0 2006.201.22:39:49.52#ibcon#read 5, iclass 7, count 0 2006.201.22:39:49.52#ibcon#about to read 6, iclass 7, count 0 2006.201.22:39:49.52#ibcon#read 6, iclass 7, count 0 2006.201.22:39:49.52#ibcon#end of sib2, iclass 7, count 0 2006.201.22:39:49.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.22:39:49.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.22:39:49.52#ibcon#[25=USB\r\n] 2006.201.22:39:49.52#ibcon#*before write, iclass 7, count 0 2006.201.22:39:49.52#ibcon#enter sib2, iclass 7, count 0 2006.201.22:39:49.52#ibcon#flushed, iclass 7, count 0 2006.201.22:39:49.52#ibcon#about to write, iclass 7, count 0 2006.201.22:39:49.52#ibcon#wrote, iclass 7, count 0 2006.201.22:39:49.52#ibcon#about to read 3, iclass 7, count 0 2006.201.22:39:49.55#ibcon#read 3, iclass 7, count 0 2006.201.22:39:49.55#ibcon#about to read 4, iclass 7, count 0 2006.201.22:39:49.55#ibcon#read 4, iclass 7, count 0 2006.201.22:39:49.55#ibcon#about to read 5, iclass 7, count 0 2006.201.22:39:49.55#ibcon#read 5, iclass 7, count 0 2006.201.22:39:49.55#ibcon#about to read 6, iclass 7, count 0 2006.201.22:39:49.55#ibcon#read 6, iclass 7, count 0 2006.201.22:39:49.55#ibcon#end of sib2, iclass 7, count 0 2006.201.22:39:49.55#ibcon#*after write, iclass 7, count 0 2006.201.22:39:49.55#ibcon#*before return 0, iclass 7, count 0 2006.201.22:39:49.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:49.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:49.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.22:39:49.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.22:39:49.55$vck44/valo=6,814.99 2006.201.22:39:49.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.22:39:49.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.22:39:49.55#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:49.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:49.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:49.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:49.55#ibcon#enter wrdev, iclass 11, count 0 2006.201.22:39:49.55#ibcon#first serial, iclass 11, count 0 2006.201.22:39:49.55#ibcon#enter sib2, iclass 11, count 0 2006.201.22:39:49.55#ibcon#flushed, iclass 11, count 0 2006.201.22:39:49.55#ibcon#about to write, iclass 11, count 0 2006.201.22:39:49.55#ibcon#wrote, iclass 11, count 0 2006.201.22:39:49.55#ibcon#about to read 3, iclass 11, count 0 2006.201.22:39:49.57#ibcon#read 3, iclass 11, count 0 2006.201.22:39:49.57#ibcon#about to read 4, iclass 11, count 0 2006.201.22:39:49.57#ibcon#read 4, iclass 11, count 0 2006.201.22:39:49.57#ibcon#about to read 5, iclass 11, count 0 2006.201.22:39:49.57#ibcon#read 5, iclass 11, count 0 2006.201.22:39:49.57#ibcon#about to read 6, iclass 11, count 0 2006.201.22:39:49.57#ibcon#read 6, iclass 11, count 0 2006.201.22:39:49.57#ibcon#end of sib2, iclass 11, count 0 2006.201.22:39:49.57#ibcon#*mode == 0, iclass 11, count 0 2006.201.22:39:49.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.22:39:49.57#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.22:39:49.57#ibcon#*before write, iclass 11, count 0 2006.201.22:39:49.57#ibcon#enter sib2, iclass 11, count 0 2006.201.22:39:49.57#ibcon#flushed, iclass 11, count 0 2006.201.22:39:49.57#ibcon#about to write, iclass 11, count 0 2006.201.22:39:49.57#ibcon#wrote, iclass 11, count 0 2006.201.22:39:49.57#ibcon#about to read 3, iclass 11, count 0 2006.201.22:39:49.62#ibcon#read 3, iclass 11, count 0 2006.201.22:39:49.62#ibcon#about to read 4, iclass 11, count 0 2006.201.22:39:49.62#ibcon#read 4, iclass 11, count 0 2006.201.22:39:49.62#ibcon#about to read 5, iclass 11, count 0 2006.201.22:39:49.62#ibcon#read 5, iclass 11, count 0 2006.201.22:39:49.62#ibcon#about to read 6, iclass 11, count 0 2006.201.22:39:49.62#ibcon#read 6, iclass 11, count 0 2006.201.22:39:49.62#ibcon#end of sib2, iclass 11, count 0 2006.201.22:39:49.62#ibcon#*after write, iclass 11, count 0 2006.201.22:39:49.62#ibcon#*before return 0, iclass 11, count 0 2006.201.22:39:49.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:49.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:49.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.22:39:49.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.22:39:49.62$vck44/va=6,5 2006.201.22:39:49.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.22:39:49.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.22:39:49.62#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:49.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:49.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:49.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:49.67#ibcon#enter wrdev, iclass 13, count 2 2006.201.22:39:49.67#ibcon#first serial, iclass 13, count 2 2006.201.22:39:49.67#ibcon#enter sib2, iclass 13, count 2 2006.201.22:39:49.67#ibcon#flushed, iclass 13, count 2 2006.201.22:39:49.67#ibcon#about to write, iclass 13, count 2 2006.201.22:39:49.67#ibcon#wrote, iclass 13, count 2 2006.201.22:39:49.67#ibcon#about to read 3, iclass 13, count 2 2006.201.22:39:49.69#ibcon#read 3, iclass 13, count 2 2006.201.22:39:49.69#ibcon#about to read 4, iclass 13, count 2 2006.201.22:39:49.69#ibcon#read 4, iclass 13, count 2 2006.201.22:39:49.69#ibcon#about to read 5, iclass 13, count 2 2006.201.22:39:49.69#ibcon#read 5, iclass 13, count 2 2006.201.22:39:49.69#ibcon#about to read 6, iclass 13, count 2 2006.201.22:39:49.69#ibcon#read 6, iclass 13, count 2 2006.201.22:39:49.69#ibcon#end of sib2, iclass 13, count 2 2006.201.22:39:49.69#ibcon#*mode == 0, iclass 13, count 2 2006.201.22:39:49.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.22:39:49.69#ibcon#[25=AT06-05\r\n] 2006.201.22:39:49.69#ibcon#*before write, iclass 13, count 2 2006.201.22:39:49.69#ibcon#enter sib2, iclass 13, count 2 2006.201.22:39:49.69#ibcon#flushed, iclass 13, count 2 2006.201.22:39:49.69#ibcon#about to write, iclass 13, count 2 2006.201.22:39:49.69#ibcon#wrote, iclass 13, count 2 2006.201.22:39:49.69#ibcon#about to read 3, iclass 13, count 2 2006.201.22:39:49.72#ibcon#read 3, iclass 13, count 2 2006.201.22:39:49.72#ibcon#about to read 4, iclass 13, count 2 2006.201.22:39:49.72#ibcon#read 4, iclass 13, count 2 2006.201.22:39:49.72#ibcon#about to read 5, iclass 13, count 2 2006.201.22:39:49.72#ibcon#read 5, iclass 13, count 2 2006.201.22:39:49.72#ibcon#about to read 6, iclass 13, count 2 2006.201.22:39:49.72#ibcon#read 6, iclass 13, count 2 2006.201.22:39:49.72#ibcon#end of sib2, iclass 13, count 2 2006.201.22:39:49.72#ibcon#*after write, iclass 13, count 2 2006.201.22:39:49.72#ibcon#*before return 0, iclass 13, count 2 2006.201.22:39:49.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:49.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:49.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.22:39:49.72#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:49.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:49.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:49.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:49.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.22:39:49.84#ibcon#first serial, iclass 13, count 0 2006.201.22:39:49.84#ibcon#enter sib2, iclass 13, count 0 2006.201.22:39:49.84#ibcon#flushed, iclass 13, count 0 2006.201.22:39:49.84#ibcon#about to write, iclass 13, count 0 2006.201.22:39:49.84#ibcon#wrote, iclass 13, count 0 2006.201.22:39:49.84#ibcon#about to read 3, iclass 13, count 0 2006.201.22:39:49.86#ibcon#read 3, iclass 13, count 0 2006.201.22:39:49.86#ibcon#about to read 4, iclass 13, count 0 2006.201.22:39:49.86#ibcon#read 4, iclass 13, count 0 2006.201.22:39:49.86#ibcon#about to read 5, iclass 13, count 0 2006.201.22:39:49.86#ibcon#read 5, iclass 13, count 0 2006.201.22:39:49.86#ibcon#about to read 6, iclass 13, count 0 2006.201.22:39:49.86#ibcon#read 6, iclass 13, count 0 2006.201.22:39:49.86#ibcon#end of sib2, iclass 13, count 0 2006.201.22:39:49.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.22:39:49.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.22:39:49.86#ibcon#[25=USB\r\n] 2006.201.22:39:49.86#ibcon#*before write, iclass 13, count 0 2006.201.22:39:49.86#ibcon#enter sib2, iclass 13, count 0 2006.201.22:39:49.86#ibcon#flushed, iclass 13, count 0 2006.201.22:39:49.86#ibcon#about to write, iclass 13, count 0 2006.201.22:39:49.86#ibcon#wrote, iclass 13, count 0 2006.201.22:39:49.86#ibcon#about to read 3, iclass 13, count 0 2006.201.22:39:49.89#ibcon#read 3, iclass 13, count 0 2006.201.22:39:49.89#ibcon#about to read 4, iclass 13, count 0 2006.201.22:39:49.89#ibcon#read 4, iclass 13, count 0 2006.201.22:39:49.89#ibcon#about to read 5, iclass 13, count 0 2006.201.22:39:49.89#ibcon#read 5, iclass 13, count 0 2006.201.22:39:49.89#ibcon#about to read 6, iclass 13, count 0 2006.201.22:39:49.89#ibcon#read 6, iclass 13, count 0 2006.201.22:39:49.89#ibcon#end of sib2, iclass 13, count 0 2006.201.22:39:49.89#ibcon#*after write, iclass 13, count 0 2006.201.22:39:49.89#ibcon#*before return 0, iclass 13, count 0 2006.201.22:39:49.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:49.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:49.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.22:39:49.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.22:39:49.89$vck44/valo=7,864.99 2006.201.22:39:49.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.22:39:49.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.22:39:49.89#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:49.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:49.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:49.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:49.89#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:39:49.89#ibcon#first serial, iclass 15, count 0 2006.201.22:39:49.89#ibcon#enter sib2, iclass 15, count 0 2006.201.22:39:49.89#ibcon#flushed, iclass 15, count 0 2006.201.22:39:49.89#ibcon#about to write, iclass 15, count 0 2006.201.22:39:49.89#ibcon#wrote, iclass 15, count 0 2006.201.22:39:49.89#ibcon#about to read 3, iclass 15, count 0 2006.201.22:39:49.91#ibcon#read 3, iclass 15, count 0 2006.201.22:39:49.91#ibcon#about to read 4, iclass 15, count 0 2006.201.22:39:49.91#ibcon#read 4, iclass 15, count 0 2006.201.22:39:49.91#ibcon#about to read 5, iclass 15, count 0 2006.201.22:39:49.91#ibcon#read 5, iclass 15, count 0 2006.201.22:39:49.91#ibcon#about to read 6, iclass 15, count 0 2006.201.22:39:49.91#ibcon#read 6, iclass 15, count 0 2006.201.22:39:49.91#ibcon#end of sib2, iclass 15, count 0 2006.201.22:39:49.91#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:39:49.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:39:49.91#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.22:39:49.91#ibcon#*before write, iclass 15, count 0 2006.201.22:39:49.91#ibcon#enter sib2, iclass 15, count 0 2006.201.22:39:49.91#ibcon#flushed, iclass 15, count 0 2006.201.22:39:49.91#ibcon#about to write, iclass 15, count 0 2006.201.22:39:49.91#ibcon#wrote, iclass 15, count 0 2006.201.22:39:49.91#ibcon#about to read 3, iclass 15, count 0 2006.201.22:39:49.95#ibcon#read 3, iclass 15, count 0 2006.201.22:39:49.95#ibcon#about to read 4, iclass 15, count 0 2006.201.22:39:49.95#ibcon#read 4, iclass 15, count 0 2006.201.22:39:49.95#ibcon#about to read 5, iclass 15, count 0 2006.201.22:39:49.95#ibcon#read 5, iclass 15, count 0 2006.201.22:39:49.95#ibcon#about to read 6, iclass 15, count 0 2006.201.22:39:49.95#ibcon#read 6, iclass 15, count 0 2006.201.22:39:49.95#ibcon#end of sib2, iclass 15, count 0 2006.201.22:39:49.95#ibcon#*after write, iclass 15, count 0 2006.201.22:39:49.95#ibcon#*before return 0, iclass 15, count 0 2006.201.22:39:49.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:49.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:49.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:39:49.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:39:49.95$vck44/va=7,5 2006.201.22:39:49.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.22:39:49.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.22:39:49.95#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:49.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:50.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:50.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:50.01#ibcon#enter wrdev, iclass 17, count 2 2006.201.22:39:50.01#ibcon#first serial, iclass 17, count 2 2006.201.22:39:50.01#ibcon#enter sib2, iclass 17, count 2 2006.201.22:39:50.01#ibcon#flushed, iclass 17, count 2 2006.201.22:39:50.01#ibcon#about to write, iclass 17, count 2 2006.201.22:39:50.01#ibcon#wrote, iclass 17, count 2 2006.201.22:39:50.01#ibcon#about to read 3, iclass 17, count 2 2006.201.22:39:50.03#ibcon#read 3, iclass 17, count 2 2006.201.22:39:50.03#ibcon#about to read 4, iclass 17, count 2 2006.201.22:39:50.03#ibcon#read 4, iclass 17, count 2 2006.201.22:39:50.03#ibcon#about to read 5, iclass 17, count 2 2006.201.22:39:50.03#ibcon#read 5, iclass 17, count 2 2006.201.22:39:50.03#ibcon#about to read 6, iclass 17, count 2 2006.201.22:39:50.03#ibcon#read 6, iclass 17, count 2 2006.201.22:39:50.03#ibcon#end of sib2, iclass 17, count 2 2006.201.22:39:50.03#ibcon#*mode == 0, iclass 17, count 2 2006.201.22:39:50.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.22:39:50.03#ibcon#[25=AT07-05\r\n] 2006.201.22:39:50.03#ibcon#*before write, iclass 17, count 2 2006.201.22:39:50.03#ibcon#enter sib2, iclass 17, count 2 2006.201.22:39:50.03#ibcon#flushed, iclass 17, count 2 2006.201.22:39:50.03#ibcon#about to write, iclass 17, count 2 2006.201.22:39:50.03#ibcon#wrote, iclass 17, count 2 2006.201.22:39:50.03#ibcon#about to read 3, iclass 17, count 2 2006.201.22:39:50.06#ibcon#read 3, iclass 17, count 2 2006.201.22:39:50.06#ibcon#about to read 4, iclass 17, count 2 2006.201.22:39:50.06#ibcon#read 4, iclass 17, count 2 2006.201.22:39:50.06#ibcon#about to read 5, iclass 17, count 2 2006.201.22:39:50.06#ibcon#read 5, iclass 17, count 2 2006.201.22:39:50.06#ibcon#about to read 6, iclass 17, count 2 2006.201.22:39:50.06#ibcon#read 6, iclass 17, count 2 2006.201.22:39:50.06#ibcon#end of sib2, iclass 17, count 2 2006.201.22:39:50.06#ibcon#*after write, iclass 17, count 2 2006.201.22:39:50.06#ibcon#*before return 0, iclass 17, count 2 2006.201.22:39:50.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:50.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:50.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.22:39:50.06#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:50.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:50.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:50.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:50.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.22:39:50.18#ibcon#first serial, iclass 17, count 0 2006.201.22:39:50.18#ibcon#enter sib2, iclass 17, count 0 2006.201.22:39:50.18#ibcon#flushed, iclass 17, count 0 2006.201.22:39:50.18#ibcon#about to write, iclass 17, count 0 2006.201.22:39:50.18#ibcon#wrote, iclass 17, count 0 2006.201.22:39:50.18#ibcon#about to read 3, iclass 17, count 0 2006.201.22:39:50.20#ibcon#read 3, iclass 17, count 0 2006.201.22:39:50.20#ibcon#about to read 4, iclass 17, count 0 2006.201.22:39:50.20#ibcon#read 4, iclass 17, count 0 2006.201.22:39:50.20#ibcon#about to read 5, iclass 17, count 0 2006.201.22:39:50.20#ibcon#read 5, iclass 17, count 0 2006.201.22:39:50.20#ibcon#about to read 6, iclass 17, count 0 2006.201.22:39:50.20#ibcon#read 6, iclass 17, count 0 2006.201.22:39:50.20#ibcon#end of sib2, iclass 17, count 0 2006.201.22:39:50.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.22:39:50.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.22:39:50.20#ibcon#[25=USB\r\n] 2006.201.22:39:50.20#ibcon#*before write, iclass 17, count 0 2006.201.22:39:50.20#ibcon#enter sib2, iclass 17, count 0 2006.201.22:39:50.20#ibcon#flushed, iclass 17, count 0 2006.201.22:39:50.20#ibcon#about to write, iclass 17, count 0 2006.201.22:39:50.20#ibcon#wrote, iclass 17, count 0 2006.201.22:39:50.20#ibcon#about to read 3, iclass 17, count 0 2006.201.22:39:50.23#ibcon#read 3, iclass 17, count 0 2006.201.22:39:50.23#ibcon#about to read 4, iclass 17, count 0 2006.201.22:39:50.23#ibcon#read 4, iclass 17, count 0 2006.201.22:39:50.23#ibcon#about to read 5, iclass 17, count 0 2006.201.22:39:50.23#ibcon#read 5, iclass 17, count 0 2006.201.22:39:50.23#ibcon#about to read 6, iclass 17, count 0 2006.201.22:39:50.23#ibcon#read 6, iclass 17, count 0 2006.201.22:39:50.23#ibcon#end of sib2, iclass 17, count 0 2006.201.22:39:50.23#ibcon#*after write, iclass 17, count 0 2006.201.22:39:50.23#ibcon#*before return 0, iclass 17, count 0 2006.201.22:39:50.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:50.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:50.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.22:39:50.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.22:39:50.23$vck44/valo=8,884.99 2006.201.22:39:50.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.22:39:50.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.22:39:50.23#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:50.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:50.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:50.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:50.23#ibcon#enter wrdev, iclass 19, count 0 2006.201.22:39:50.23#ibcon#first serial, iclass 19, count 0 2006.201.22:39:50.23#ibcon#enter sib2, iclass 19, count 0 2006.201.22:39:50.23#ibcon#flushed, iclass 19, count 0 2006.201.22:39:50.23#ibcon#about to write, iclass 19, count 0 2006.201.22:39:50.23#ibcon#wrote, iclass 19, count 0 2006.201.22:39:50.23#ibcon#about to read 3, iclass 19, count 0 2006.201.22:39:50.25#ibcon#read 3, iclass 19, count 0 2006.201.22:39:50.25#ibcon#about to read 4, iclass 19, count 0 2006.201.22:39:50.25#ibcon#read 4, iclass 19, count 0 2006.201.22:39:50.25#ibcon#about to read 5, iclass 19, count 0 2006.201.22:39:50.25#ibcon#read 5, iclass 19, count 0 2006.201.22:39:50.25#ibcon#about to read 6, iclass 19, count 0 2006.201.22:39:50.25#ibcon#read 6, iclass 19, count 0 2006.201.22:39:50.25#ibcon#end of sib2, iclass 19, count 0 2006.201.22:39:50.25#ibcon#*mode == 0, iclass 19, count 0 2006.201.22:39:50.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.22:39:50.25#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.22:39:50.25#ibcon#*before write, iclass 19, count 0 2006.201.22:39:50.25#ibcon#enter sib2, iclass 19, count 0 2006.201.22:39:50.25#ibcon#flushed, iclass 19, count 0 2006.201.22:39:50.25#ibcon#about to write, iclass 19, count 0 2006.201.22:39:50.25#ibcon#wrote, iclass 19, count 0 2006.201.22:39:50.25#ibcon#about to read 3, iclass 19, count 0 2006.201.22:39:50.29#ibcon#read 3, iclass 19, count 0 2006.201.22:39:50.29#ibcon#about to read 4, iclass 19, count 0 2006.201.22:39:50.29#ibcon#read 4, iclass 19, count 0 2006.201.22:39:50.29#ibcon#about to read 5, iclass 19, count 0 2006.201.22:39:50.29#ibcon#read 5, iclass 19, count 0 2006.201.22:39:50.29#ibcon#about to read 6, iclass 19, count 0 2006.201.22:39:50.29#ibcon#read 6, iclass 19, count 0 2006.201.22:39:50.29#ibcon#end of sib2, iclass 19, count 0 2006.201.22:39:50.29#ibcon#*after write, iclass 19, count 0 2006.201.22:39:50.29#ibcon#*before return 0, iclass 19, count 0 2006.201.22:39:50.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:50.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:50.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.22:39:50.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.22:39:50.29$vck44/va=8,4 2006.201.22:39:50.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.22:39:50.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.22:39:50.29#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:50.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:39:50.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:39:50.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:39:50.35#ibcon#enter wrdev, iclass 21, count 2 2006.201.22:39:50.35#ibcon#first serial, iclass 21, count 2 2006.201.22:39:50.35#ibcon#enter sib2, iclass 21, count 2 2006.201.22:39:50.35#ibcon#flushed, iclass 21, count 2 2006.201.22:39:50.35#ibcon#about to write, iclass 21, count 2 2006.201.22:39:50.35#ibcon#wrote, iclass 21, count 2 2006.201.22:39:50.35#ibcon#about to read 3, iclass 21, count 2 2006.201.22:39:50.37#ibcon#read 3, iclass 21, count 2 2006.201.22:39:50.37#ibcon#about to read 4, iclass 21, count 2 2006.201.22:39:50.37#ibcon#read 4, iclass 21, count 2 2006.201.22:39:50.37#ibcon#about to read 5, iclass 21, count 2 2006.201.22:39:50.37#ibcon#read 5, iclass 21, count 2 2006.201.22:39:50.37#ibcon#about to read 6, iclass 21, count 2 2006.201.22:39:50.37#ibcon#read 6, iclass 21, count 2 2006.201.22:39:50.37#ibcon#end of sib2, iclass 21, count 2 2006.201.22:39:50.37#ibcon#*mode == 0, iclass 21, count 2 2006.201.22:39:50.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.22:39:50.37#ibcon#[25=AT08-04\r\n] 2006.201.22:39:50.37#ibcon#*before write, iclass 21, count 2 2006.201.22:39:50.37#ibcon#enter sib2, iclass 21, count 2 2006.201.22:39:50.37#ibcon#flushed, iclass 21, count 2 2006.201.22:39:50.37#ibcon#about to write, iclass 21, count 2 2006.201.22:39:50.37#ibcon#wrote, iclass 21, count 2 2006.201.22:39:50.37#ibcon#about to read 3, iclass 21, count 2 2006.201.22:39:50.40#ibcon#read 3, iclass 21, count 2 2006.201.22:39:50.40#ibcon#about to read 4, iclass 21, count 2 2006.201.22:39:50.40#ibcon#read 4, iclass 21, count 2 2006.201.22:39:50.40#ibcon#about to read 5, iclass 21, count 2 2006.201.22:39:50.40#ibcon#read 5, iclass 21, count 2 2006.201.22:39:50.40#ibcon#about to read 6, iclass 21, count 2 2006.201.22:39:50.40#ibcon#read 6, iclass 21, count 2 2006.201.22:39:50.40#ibcon#end of sib2, iclass 21, count 2 2006.201.22:39:50.40#ibcon#*after write, iclass 21, count 2 2006.201.22:39:50.40#ibcon#*before return 0, iclass 21, count 2 2006.201.22:39:50.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:39:50.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.22:39:50.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.22:39:50.40#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:50.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:39:50.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:39:50.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:39:50.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.22:39:50.52#ibcon#first serial, iclass 21, count 0 2006.201.22:39:50.52#ibcon#enter sib2, iclass 21, count 0 2006.201.22:39:50.52#ibcon#flushed, iclass 21, count 0 2006.201.22:39:50.52#ibcon#about to write, iclass 21, count 0 2006.201.22:39:50.52#ibcon#wrote, iclass 21, count 0 2006.201.22:39:50.52#ibcon#about to read 3, iclass 21, count 0 2006.201.22:39:50.54#ibcon#read 3, iclass 21, count 0 2006.201.22:39:50.54#ibcon#about to read 4, iclass 21, count 0 2006.201.22:39:50.54#ibcon#read 4, iclass 21, count 0 2006.201.22:39:50.54#ibcon#about to read 5, iclass 21, count 0 2006.201.22:39:50.54#ibcon#read 5, iclass 21, count 0 2006.201.22:39:50.54#ibcon#about to read 6, iclass 21, count 0 2006.201.22:39:50.54#ibcon#read 6, iclass 21, count 0 2006.201.22:39:50.54#ibcon#end of sib2, iclass 21, count 0 2006.201.22:39:50.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.22:39:50.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.22:39:50.54#ibcon#[25=USB\r\n] 2006.201.22:39:50.54#ibcon#*before write, iclass 21, count 0 2006.201.22:39:50.54#ibcon#enter sib2, iclass 21, count 0 2006.201.22:39:50.54#ibcon#flushed, iclass 21, count 0 2006.201.22:39:50.54#ibcon#about to write, iclass 21, count 0 2006.201.22:39:50.54#ibcon#wrote, iclass 21, count 0 2006.201.22:39:50.54#ibcon#about to read 3, iclass 21, count 0 2006.201.22:39:50.57#ibcon#read 3, iclass 21, count 0 2006.201.22:39:50.57#ibcon#about to read 4, iclass 21, count 0 2006.201.22:39:50.57#ibcon#read 4, iclass 21, count 0 2006.201.22:39:50.57#ibcon#about to read 5, iclass 21, count 0 2006.201.22:39:50.57#ibcon#read 5, iclass 21, count 0 2006.201.22:39:50.57#ibcon#about to read 6, iclass 21, count 0 2006.201.22:39:50.57#ibcon#read 6, iclass 21, count 0 2006.201.22:39:50.57#ibcon#end of sib2, iclass 21, count 0 2006.201.22:39:50.57#ibcon#*after write, iclass 21, count 0 2006.201.22:39:50.57#ibcon#*before return 0, iclass 21, count 0 2006.201.22:39:50.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:39:50.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.22:39:50.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.22:39:50.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.22:39:50.57$vck44/vblo=1,629.99 2006.201.22:39:50.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.22:39:50.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.22:39:50.57#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:50.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:39:50.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:39:50.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:39:50.57#ibcon#enter wrdev, iclass 23, count 0 2006.201.22:39:50.57#ibcon#first serial, iclass 23, count 0 2006.201.22:39:50.57#ibcon#enter sib2, iclass 23, count 0 2006.201.22:39:50.57#ibcon#flushed, iclass 23, count 0 2006.201.22:39:50.57#ibcon#about to write, iclass 23, count 0 2006.201.22:39:50.57#ibcon#wrote, iclass 23, count 0 2006.201.22:39:50.57#ibcon#about to read 3, iclass 23, count 0 2006.201.22:39:50.59#ibcon#read 3, iclass 23, count 0 2006.201.22:39:50.59#ibcon#about to read 4, iclass 23, count 0 2006.201.22:39:50.59#ibcon#read 4, iclass 23, count 0 2006.201.22:39:50.59#ibcon#about to read 5, iclass 23, count 0 2006.201.22:39:50.59#ibcon#read 5, iclass 23, count 0 2006.201.22:39:50.59#ibcon#about to read 6, iclass 23, count 0 2006.201.22:39:50.59#ibcon#read 6, iclass 23, count 0 2006.201.22:39:50.59#ibcon#end of sib2, iclass 23, count 0 2006.201.22:39:50.59#ibcon#*mode == 0, iclass 23, count 0 2006.201.22:39:50.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.22:39:50.59#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.22:39:50.59#ibcon#*before write, iclass 23, count 0 2006.201.22:39:50.59#ibcon#enter sib2, iclass 23, count 0 2006.201.22:39:50.59#ibcon#flushed, iclass 23, count 0 2006.201.22:39:50.59#ibcon#about to write, iclass 23, count 0 2006.201.22:39:50.59#ibcon#wrote, iclass 23, count 0 2006.201.22:39:50.59#ibcon#about to read 3, iclass 23, count 0 2006.201.22:39:50.63#ibcon#read 3, iclass 23, count 0 2006.201.22:39:50.63#ibcon#about to read 4, iclass 23, count 0 2006.201.22:39:50.63#ibcon#read 4, iclass 23, count 0 2006.201.22:39:50.63#ibcon#about to read 5, iclass 23, count 0 2006.201.22:39:50.63#ibcon#read 5, iclass 23, count 0 2006.201.22:39:50.63#ibcon#about to read 6, iclass 23, count 0 2006.201.22:39:50.63#ibcon#read 6, iclass 23, count 0 2006.201.22:39:50.63#ibcon#end of sib2, iclass 23, count 0 2006.201.22:39:50.63#ibcon#*after write, iclass 23, count 0 2006.201.22:39:50.63#ibcon#*before return 0, iclass 23, count 0 2006.201.22:39:50.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:39:50.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.22:39:50.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.22:39:50.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.22:39:50.63$vck44/vb=1,4 2006.201.22:39:50.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.22:39:50.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.22:39:50.63#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:50.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:39:50.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:39:50.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:39:50.63#ibcon#enter wrdev, iclass 25, count 2 2006.201.22:39:50.63#ibcon#first serial, iclass 25, count 2 2006.201.22:39:50.63#ibcon#enter sib2, iclass 25, count 2 2006.201.22:39:50.63#ibcon#flushed, iclass 25, count 2 2006.201.22:39:50.63#ibcon#about to write, iclass 25, count 2 2006.201.22:39:50.63#ibcon#wrote, iclass 25, count 2 2006.201.22:39:50.63#ibcon#about to read 3, iclass 25, count 2 2006.201.22:39:50.65#ibcon#read 3, iclass 25, count 2 2006.201.22:39:50.65#ibcon#about to read 4, iclass 25, count 2 2006.201.22:39:50.65#ibcon#read 4, iclass 25, count 2 2006.201.22:39:50.65#ibcon#about to read 5, iclass 25, count 2 2006.201.22:39:50.65#ibcon#read 5, iclass 25, count 2 2006.201.22:39:50.65#ibcon#about to read 6, iclass 25, count 2 2006.201.22:39:50.65#ibcon#read 6, iclass 25, count 2 2006.201.22:39:50.65#ibcon#end of sib2, iclass 25, count 2 2006.201.22:39:50.65#ibcon#*mode == 0, iclass 25, count 2 2006.201.22:39:50.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.22:39:50.65#ibcon#[27=AT01-04\r\n] 2006.201.22:39:50.65#ibcon#*before write, iclass 25, count 2 2006.201.22:39:50.65#ibcon#enter sib2, iclass 25, count 2 2006.201.22:39:50.65#ibcon#flushed, iclass 25, count 2 2006.201.22:39:50.65#ibcon#about to write, iclass 25, count 2 2006.201.22:39:50.65#ibcon#wrote, iclass 25, count 2 2006.201.22:39:50.65#ibcon#about to read 3, iclass 25, count 2 2006.201.22:39:50.68#ibcon#read 3, iclass 25, count 2 2006.201.22:39:50.68#ibcon#about to read 4, iclass 25, count 2 2006.201.22:39:50.68#ibcon#read 4, iclass 25, count 2 2006.201.22:39:50.68#ibcon#about to read 5, iclass 25, count 2 2006.201.22:39:50.68#ibcon#read 5, iclass 25, count 2 2006.201.22:39:50.68#ibcon#about to read 6, iclass 25, count 2 2006.201.22:39:50.68#ibcon#read 6, iclass 25, count 2 2006.201.22:39:50.68#ibcon#end of sib2, iclass 25, count 2 2006.201.22:39:50.68#ibcon#*after write, iclass 25, count 2 2006.201.22:39:50.68#ibcon#*before return 0, iclass 25, count 2 2006.201.22:39:50.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:39:50.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.22:39:50.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.22:39:50.68#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:50.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:39:50.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:39:50.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:39:50.80#ibcon#enter wrdev, iclass 25, count 0 2006.201.22:39:50.80#ibcon#first serial, iclass 25, count 0 2006.201.22:39:50.80#ibcon#enter sib2, iclass 25, count 0 2006.201.22:39:50.80#ibcon#flushed, iclass 25, count 0 2006.201.22:39:50.80#ibcon#about to write, iclass 25, count 0 2006.201.22:39:50.80#ibcon#wrote, iclass 25, count 0 2006.201.22:39:50.80#ibcon#about to read 3, iclass 25, count 0 2006.201.22:39:50.82#ibcon#read 3, iclass 25, count 0 2006.201.22:39:50.82#ibcon#about to read 4, iclass 25, count 0 2006.201.22:39:50.82#ibcon#read 4, iclass 25, count 0 2006.201.22:39:50.82#ibcon#about to read 5, iclass 25, count 0 2006.201.22:39:50.82#ibcon#read 5, iclass 25, count 0 2006.201.22:39:50.82#ibcon#about to read 6, iclass 25, count 0 2006.201.22:39:50.82#ibcon#read 6, iclass 25, count 0 2006.201.22:39:50.82#ibcon#end of sib2, iclass 25, count 0 2006.201.22:39:50.82#ibcon#*mode == 0, iclass 25, count 0 2006.201.22:39:50.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.22:39:50.82#ibcon#[27=USB\r\n] 2006.201.22:39:50.82#ibcon#*before write, iclass 25, count 0 2006.201.22:39:50.82#ibcon#enter sib2, iclass 25, count 0 2006.201.22:39:50.82#ibcon#flushed, iclass 25, count 0 2006.201.22:39:50.82#ibcon#about to write, iclass 25, count 0 2006.201.22:39:50.82#ibcon#wrote, iclass 25, count 0 2006.201.22:39:50.82#ibcon#about to read 3, iclass 25, count 0 2006.201.22:39:50.85#ibcon#read 3, iclass 25, count 0 2006.201.22:39:50.85#ibcon#about to read 4, iclass 25, count 0 2006.201.22:39:50.85#ibcon#read 4, iclass 25, count 0 2006.201.22:39:50.85#ibcon#about to read 5, iclass 25, count 0 2006.201.22:39:50.85#ibcon#read 5, iclass 25, count 0 2006.201.22:39:50.85#ibcon#about to read 6, iclass 25, count 0 2006.201.22:39:50.85#ibcon#read 6, iclass 25, count 0 2006.201.22:39:50.85#ibcon#end of sib2, iclass 25, count 0 2006.201.22:39:50.85#ibcon#*after write, iclass 25, count 0 2006.201.22:39:50.85#ibcon#*before return 0, iclass 25, count 0 2006.201.22:39:50.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:39:50.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.22:39:50.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.22:39:50.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.22:39:50.85$vck44/vblo=2,634.99 2006.201.22:39:50.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.22:39:50.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.22:39:50.85#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:50.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:39:50.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:39:50.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:39:50.85#ibcon#enter wrdev, iclass 27, count 0 2006.201.22:39:50.85#ibcon#first serial, iclass 27, count 0 2006.201.22:39:50.85#ibcon#enter sib2, iclass 27, count 0 2006.201.22:39:50.85#ibcon#flushed, iclass 27, count 0 2006.201.22:39:50.85#ibcon#about to write, iclass 27, count 0 2006.201.22:39:50.85#ibcon#wrote, iclass 27, count 0 2006.201.22:39:50.85#ibcon#about to read 3, iclass 27, count 0 2006.201.22:39:50.87#ibcon#read 3, iclass 27, count 0 2006.201.22:39:50.87#ibcon#about to read 4, iclass 27, count 0 2006.201.22:39:50.87#ibcon#read 4, iclass 27, count 0 2006.201.22:39:50.87#ibcon#about to read 5, iclass 27, count 0 2006.201.22:39:50.87#ibcon#read 5, iclass 27, count 0 2006.201.22:39:50.87#ibcon#about to read 6, iclass 27, count 0 2006.201.22:39:50.87#ibcon#read 6, iclass 27, count 0 2006.201.22:39:50.87#ibcon#end of sib2, iclass 27, count 0 2006.201.22:39:50.87#ibcon#*mode == 0, iclass 27, count 0 2006.201.22:39:50.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.22:39:50.87#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.22:39:50.87#ibcon#*before write, iclass 27, count 0 2006.201.22:39:50.87#ibcon#enter sib2, iclass 27, count 0 2006.201.22:39:50.87#ibcon#flushed, iclass 27, count 0 2006.201.22:39:50.87#ibcon#about to write, iclass 27, count 0 2006.201.22:39:50.87#ibcon#wrote, iclass 27, count 0 2006.201.22:39:50.87#ibcon#about to read 3, iclass 27, count 0 2006.201.22:39:50.91#ibcon#read 3, iclass 27, count 0 2006.201.22:39:50.91#ibcon#about to read 4, iclass 27, count 0 2006.201.22:39:50.91#ibcon#read 4, iclass 27, count 0 2006.201.22:39:50.91#ibcon#about to read 5, iclass 27, count 0 2006.201.22:39:50.91#ibcon#read 5, iclass 27, count 0 2006.201.22:39:50.91#ibcon#about to read 6, iclass 27, count 0 2006.201.22:39:50.91#ibcon#read 6, iclass 27, count 0 2006.201.22:39:50.91#ibcon#end of sib2, iclass 27, count 0 2006.201.22:39:50.91#ibcon#*after write, iclass 27, count 0 2006.201.22:39:50.91#ibcon#*before return 0, iclass 27, count 0 2006.201.22:39:50.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:39:50.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.22:39:50.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.22:39:50.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.22:39:50.91$vck44/vb=2,5 2006.201.22:39:50.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.22:39:50.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.22:39:50.91#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:50.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:50.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:50.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:50.97#ibcon#enter wrdev, iclass 29, count 2 2006.201.22:39:50.97#ibcon#first serial, iclass 29, count 2 2006.201.22:39:50.97#ibcon#enter sib2, iclass 29, count 2 2006.201.22:39:50.97#ibcon#flushed, iclass 29, count 2 2006.201.22:39:50.97#ibcon#about to write, iclass 29, count 2 2006.201.22:39:50.97#ibcon#wrote, iclass 29, count 2 2006.201.22:39:50.97#ibcon#about to read 3, iclass 29, count 2 2006.201.22:39:50.99#ibcon#read 3, iclass 29, count 2 2006.201.22:39:50.99#ibcon#about to read 4, iclass 29, count 2 2006.201.22:39:50.99#ibcon#read 4, iclass 29, count 2 2006.201.22:39:50.99#ibcon#about to read 5, iclass 29, count 2 2006.201.22:39:50.99#ibcon#read 5, iclass 29, count 2 2006.201.22:39:50.99#ibcon#about to read 6, iclass 29, count 2 2006.201.22:39:50.99#ibcon#read 6, iclass 29, count 2 2006.201.22:39:50.99#ibcon#end of sib2, iclass 29, count 2 2006.201.22:39:50.99#ibcon#*mode == 0, iclass 29, count 2 2006.201.22:39:50.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.22:39:50.99#ibcon#[27=AT02-05\r\n] 2006.201.22:39:50.99#ibcon#*before write, iclass 29, count 2 2006.201.22:39:50.99#ibcon#enter sib2, iclass 29, count 2 2006.201.22:39:50.99#ibcon#flushed, iclass 29, count 2 2006.201.22:39:50.99#ibcon#about to write, iclass 29, count 2 2006.201.22:39:50.99#ibcon#wrote, iclass 29, count 2 2006.201.22:39:50.99#ibcon#about to read 3, iclass 29, count 2 2006.201.22:39:51.02#ibcon#read 3, iclass 29, count 2 2006.201.22:39:51.02#ibcon#about to read 4, iclass 29, count 2 2006.201.22:39:51.02#ibcon#read 4, iclass 29, count 2 2006.201.22:39:51.02#ibcon#about to read 5, iclass 29, count 2 2006.201.22:39:51.02#ibcon#read 5, iclass 29, count 2 2006.201.22:39:51.02#ibcon#about to read 6, iclass 29, count 2 2006.201.22:39:51.02#ibcon#read 6, iclass 29, count 2 2006.201.22:39:51.02#ibcon#end of sib2, iclass 29, count 2 2006.201.22:39:51.02#ibcon#*after write, iclass 29, count 2 2006.201.22:39:51.02#ibcon#*before return 0, iclass 29, count 2 2006.201.22:39:51.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:51.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.22:39:51.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.22:39:51.02#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:51.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:51.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:51.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:51.14#ibcon#enter wrdev, iclass 29, count 0 2006.201.22:39:51.14#ibcon#first serial, iclass 29, count 0 2006.201.22:39:51.14#ibcon#enter sib2, iclass 29, count 0 2006.201.22:39:51.14#ibcon#flushed, iclass 29, count 0 2006.201.22:39:51.14#ibcon#about to write, iclass 29, count 0 2006.201.22:39:51.14#ibcon#wrote, iclass 29, count 0 2006.201.22:39:51.14#ibcon#about to read 3, iclass 29, count 0 2006.201.22:39:51.16#ibcon#read 3, iclass 29, count 0 2006.201.22:39:51.16#ibcon#about to read 4, iclass 29, count 0 2006.201.22:39:51.16#ibcon#read 4, iclass 29, count 0 2006.201.22:39:51.16#ibcon#about to read 5, iclass 29, count 0 2006.201.22:39:51.16#ibcon#read 5, iclass 29, count 0 2006.201.22:39:51.16#ibcon#about to read 6, iclass 29, count 0 2006.201.22:39:51.16#ibcon#read 6, iclass 29, count 0 2006.201.22:39:51.16#ibcon#end of sib2, iclass 29, count 0 2006.201.22:39:51.16#ibcon#*mode == 0, iclass 29, count 0 2006.201.22:39:51.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.22:39:51.16#ibcon#[27=USB\r\n] 2006.201.22:39:51.16#ibcon#*before write, iclass 29, count 0 2006.201.22:39:51.16#ibcon#enter sib2, iclass 29, count 0 2006.201.22:39:51.16#ibcon#flushed, iclass 29, count 0 2006.201.22:39:51.16#ibcon#about to write, iclass 29, count 0 2006.201.22:39:51.16#ibcon#wrote, iclass 29, count 0 2006.201.22:39:51.16#ibcon#about to read 3, iclass 29, count 0 2006.201.22:39:51.19#ibcon#read 3, iclass 29, count 0 2006.201.22:39:51.19#ibcon#about to read 4, iclass 29, count 0 2006.201.22:39:51.19#ibcon#read 4, iclass 29, count 0 2006.201.22:39:51.19#ibcon#about to read 5, iclass 29, count 0 2006.201.22:39:51.19#ibcon#read 5, iclass 29, count 0 2006.201.22:39:51.19#ibcon#about to read 6, iclass 29, count 0 2006.201.22:39:51.19#ibcon#read 6, iclass 29, count 0 2006.201.22:39:51.19#ibcon#end of sib2, iclass 29, count 0 2006.201.22:39:51.19#ibcon#*after write, iclass 29, count 0 2006.201.22:39:51.19#ibcon#*before return 0, iclass 29, count 0 2006.201.22:39:51.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:51.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.22:39:51.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.22:39:51.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.22:39:51.19$vck44/vblo=3,649.99 2006.201.22:39:51.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.22:39:51.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.22:39:51.19#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:51.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:51.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:51.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:51.19#ibcon#enter wrdev, iclass 31, count 0 2006.201.22:39:51.19#ibcon#first serial, iclass 31, count 0 2006.201.22:39:51.19#ibcon#enter sib2, iclass 31, count 0 2006.201.22:39:51.19#ibcon#flushed, iclass 31, count 0 2006.201.22:39:51.19#ibcon#about to write, iclass 31, count 0 2006.201.22:39:51.19#ibcon#wrote, iclass 31, count 0 2006.201.22:39:51.19#ibcon#about to read 3, iclass 31, count 0 2006.201.22:39:51.21#ibcon#read 3, iclass 31, count 0 2006.201.22:39:51.21#ibcon#about to read 4, iclass 31, count 0 2006.201.22:39:51.21#ibcon#read 4, iclass 31, count 0 2006.201.22:39:51.21#ibcon#about to read 5, iclass 31, count 0 2006.201.22:39:51.21#ibcon#read 5, iclass 31, count 0 2006.201.22:39:51.21#ibcon#about to read 6, iclass 31, count 0 2006.201.22:39:51.21#ibcon#read 6, iclass 31, count 0 2006.201.22:39:51.21#ibcon#end of sib2, iclass 31, count 0 2006.201.22:39:51.21#ibcon#*mode == 0, iclass 31, count 0 2006.201.22:39:51.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.22:39:51.21#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.22:39:51.21#ibcon#*before write, iclass 31, count 0 2006.201.22:39:51.21#ibcon#enter sib2, iclass 31, count 0 2006.201.22:39:51.21#ibcon#flushed, iclass 31, count 0 2006.201.22:39:51.21#ibcon#about to write, iclass 31, count 0 2006.201.22:39:51.21#ibcon#wrote, iclass 31, count 0 2006.201.22:39:51.21#ibcon#about to read 3, iclass 31, count 0 2006.201.22:39:51.26#ibcon#read 3, iclass 31, count 0 2006.201.22:39:51.26#ibcon#about to read 4, iclass 31, count 0 2006.201.22:39:51.26#ibcon#read 4, iclass 31, count 0 2006.201.22:39:51.26#ibcon#about to read 5, iclass 31, count 0 2006.201.22:39:51.26#ibcon#read 5, iclass 31, count 0 2006.201.22:39:51.26#ibcon#about to read 6, iclass 31, count 0 2006.201.22:39:51.26#ibcon#read 6, iclass 31, count 0 2006.201.22:39:51.26#ibcon#end of sib2, iclass 31, count 0 2006.201.22:39:51.26#ibcon#*after write, iclass 31, count 0 2006.201.22:39:51.26#ibcon#*before return 0, iclass 31, count 0 2006.201.22:39:51.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:51.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:39:51.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.22:39:51.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.22:39:51.26$vck44/vb=3,4 2006.201.22:39:51.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.22:39:51.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.22:39:51.26#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:51.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:51.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:51.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:51.31#ibcon#enter wrdev, iclass 33, count 2 2006.201.22:39:51.31#ibcon#first serial, iclass 33, count 2 2006.201.22:39:51.31#ibcon#enter sib2, iclass 33, count 2 2006.201.22:39:51.31#ibcon#flushed, iclass 33, count 2 2006.201.22:39:51.31#ibcon#about to write, iclass 33, count 2 2006.201.22:39:51.31#ibcon#wrote, iclass 33, count 2 2006.201.22:39:51.31#ibcon#about to read 3, iclass 33, count 2 2006.201.22:39:51.33#ibcon#read 3, iclass 33, count 2 2006.201.22:39:51.33#ibcon#about to read 4, iclass 33, count 2 2006.201.22:39:51.33#ibcon#read 4, iclass 33, count 2 2006.201.22:39:51.33#ibcon#about to read 5, iclass 33, count 2 2006.201.22:39:51.33#ibcon#read 5, iclass 33, count 2 2006.201.22:39:51.33#ibcon#about to read 6, iclass 33, count 2 2006.201.22:39:51.33#ibcon#read 6, iclass 33, count 2 2006.201.22:39:51.33#ibcon#end of sib2, iclass 33, count 2 2006.201.22:39:51.33#ibcon#*mode == 0, iclass 33, count 2 2006.201.22:39:51.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.22:39:51.33#ibcon#[27=AT03-04\r\n] 2006.201.22:39:51.33#ibcon#*before write, iclass 33, count 2 2006.201.22:39:51.33#ibcon#enter sib2, iclass 33, count 2 2006.201.22:39:51.33#ibcon#flushed, iclass 33, count 2 2006.201.22:39:51.33#ibcon#about to write, iclass 33, count 2 2006.201.22:39:51.33#ibcon#wrote, iclass 33, count 2 2006.201.22:39:51.33#ibcon#about to read 3, iclass 33, count 2 2006.201.22:39:51.36#ibcon#read 3, iclass 33, count 2 2006.201.22:39:51.36#ibcon#about to read 4, iclass 33, count 2 2006.201.22:39:51.36#ibcon#read 4, iclass 33, count 2 2006.201.22:39:51.36#ibcon#about to read 5, iclass 33, count 2 2006.201.22:39:51.36#ibcon#read 5, iclass 33, count 2 2006.201.22:39:51.36#ibcon#about to read 6, iclass 33, count 2 2006.201.22:39:51.36#ibcon#read 6, iclass 33, count 2 2006.201.22:39:51.36#ibcon#end of sib2, iclass 33, count 2 2006.201.22:39:51.36#ibcon#*after write, iclass 33, count 2 2006.201.22:39:51.36#ibcon#*before return 0, iclass 33, count 2 2006.201.22:39:51.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:51.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.22:39:51.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.22:39:51.36#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:51.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:51.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:51.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:51.48#ibcon#enter wrdev, iclass 33, count 0 2006.201.22:39:51.48#ibcon#first serial, iclass 33, count 0 2006.201.22:39:51.48#ibcon#enter sib2, iclass 33, count 0 2006.201.22:39:51.48#ibcon#flushed, iclass 33, count 0 2006.201.22:39:51.48#ibcon#about to write, iclass 33, count 0 2006.201.22:39:51.48#ibcon#wrote, iclass 33, count 0 2006.201.22:39:51.48#ibcon#about to read 3, iclass 33, count 0 2006.201.22:39:51.50#ibcon#read 3, iclass 33, count 0 2006.201.22:39:51.50#ibcon#about to read 4, iclass 33, count 0 2006.201.22:39:51.50#ibcon#read 4, iclass 33, count 0 2006.201.22:39:51.50#ibcon#about to read 5, iclass 33, count 0 2006.201.22:39:51.50#ibcon#read 5, iclass 33, count 0 2006.201.22:39:51.50#ibcon#about to read 6, iclass 33, count 0 2006.201.22:39:51.50#ibcon#read 6, iclass 33, count 0 2006.201.22:39:51.50#ibcon#end of sib2, iclass 33, count 0 2006.201.22:39:51.50#ibcon#*mode == 0, iclass 33, count 0 2006.201.22:39:51.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.22:39:51.50#ibcon#[27=USB\r\n] 2006.201.22:39:51.50#ibcon#*before write, iclass 33, count 0 2006.201.22:39:51.50#ibcon#enter sib2, iclass 33, count 0 2006.201.22:39:51.50#ibcon#flushed, iclass 33, count 0 2006.201.22:39:51.50#ibcon#about to write, iclass 33, count 0 2006.201.22:39:51.50#ibcon#wrote, iclass 33, count 0 2006.201.22:39:51.50#ibcon#about to read 3, iclass 33, count 0 2006.201.22:39:51.53#ibcon#read 3, iclass 33, count 0 2006.201.22:39:51.53#ibcon#about to read 4, iclass 33, count 0 2006.201.22:39:51.53#ibcon#read 4, iclass 33, count 0 2006.201.22:39:51.53#ibcon#about to read 5, iclass 33, count 0 2006.201.22:39:51.53#ibcon#read 5, iclass 33, count 0 2006.201.22:39:51.53#ibcon#about to read 6, iclass 33, count 0 2006.201.22:39:51.53#ibcon#read 6, iclass 33, count 0 2006.201.22:39:51.53#ibcon#end of sib2, iclass 33, count 0 2006.201.22:39:51.53#ibcon#*after write, iclass 33, count 0 2006.201.22:39:51.53#ibcon#*before return 0, iclass 33, count 0 2006.201.22:39:51.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:51.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.22:39:51.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.22:39:51.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.22:39:51.53$vck44/vblo=4,679.99 2006.201.22:39:51.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.22:39:51.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.22:39:51.53#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:51.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:51.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:51.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:51.53#ibcon#enter wrdev, iclass 35, count 0 2006.201.22:39:51.53#ibcon#first serial, iclass 35, count 0 2006.201.22:39:51.53#ibcon#enter sib2, iclass 35, count 0 2006.201.22:39:51.53#ibcon#flushed, iclass 35, count 0 2006.201.22:39:51.53#ibcon#about to write, iclass 35, count 0 2006.201.22:39:51.53#ibcon#wrote, iclass 35, count 0 2006.201.22:39:51.53#ibcon#about to read 3, iclass 35, count 0 2006.201.22:39:51.55#ibcon#read 3, iclass 35, count 0 2006.201.22:39:51.55#ibcon#about to read 4, iclass 35, count 0 2006.201.22:39:51.55#ibcon#read 4, iclass 35, count 0 2006.201.22:39:51.55#ibcon#about to read 5, iclass 35, count 0 2006.201.22:39:51.55#ibcon#read 5, iclass 35, count 0 2006.201.22:39:51.55#ibcon#about to read 6, iclass 35, count 0 2006.201.22:39:51.55#ibcon#read 6, iclass 35, count 0 2006.201.22:39:51.55#ibcon#end of sib2, iclass 35, count 0 2006.201.22:39:51.55#ibcon#*mode == 0, iclass 35, count 0 2006.201.22:39:51.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.22:39:51.55#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.22:39:51.55#ibcon#*before write, iclass 35, count 0 2006.201.22:39:51.55#ibcon#enter sib2, iclass 35, count 0 2006.201.22:39:51.55#ibcon#flushed, iclass 35, count 0 2006.201.22:39:51.55#ibcon#about to write, iclass 35, count 0 2006.201.22:39:51.55#ibcon#wrote, iclass 35, count 0 2006.201.22:39:51.55#ibcon#about to read 3, iclass 35, count 0 2006.201.22:39:51.59#ibcon#read 3, iclass 35, count 0 2006.201.22:39:51.59#ibcon#about to read 4, iclass 35, count 0 2006.201.22:39:51.59#ibcon#read 4, iclass 35, count 0 2006.201.22:39:51.59#ibcon#about to read 5, iclass 35, count 0 2006.201.22:39:51.59#ibcon#read 5, iclass 35, count 0 2006.201.22:39:51.59#ibcon#about to read 6, iclass 35, count 0 2006.201.22:39:51.59#ibcon#read 6, iclass 35, count 0 2006.201.22:39:51.59#ibcon#end of sib2, iclass 35, count 0 2006.201.22:39:51.59#ibcon#*after write, iclass 35, count 0 2006.201.22:39:51.59#ibcon#*before return 0, iclass 35, count 0 2006.201.22:39:51.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:51.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.22:39:51.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.22:39:51.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.22:39:51.59$vck44/vb=4,5 2006.201.22:39:51.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.22:39:51.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.22:39:51.59#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:51.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:51.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:51.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:51.65#ibcon#enter wrdev, iclass 37, count 2 2006.201.22:39:51.65#ibcon#first serial, iclass 37, count 2 2006.201.22:39:51.65#ibcon#enter sib2, iclass 37, count 2 2006.201.22:39:51.65#ibcon#flushed, iclass 37, count 2 2006.201.22:39:51.65#ibcon#about to write, iclass 37, count 2 2006.201.22:39:51.65#ibcon#wrote, iclass 37, count 2 2006.201.22:39:51.65#ibcon#about to read 3, iclass 37, count 2 2006.201.22:39:51.67#ibcon#read 3, iclass 37, count 2 2006.201.22:39:51.67#ibcon#about to read 4, iclass 37, count 2 2006.201.22:39:51.67#ibcon#read 4, iclass 37, count 2 2006.201.22:39:51.67#ibcon#about to read 5, iclass 37, count 2 2006.201.22:39:51.67#ibcon#read 5, iclass 37, count 2 2006.201.22:39:51.67#ibcon#about to read 6, iclass 37, count 2 2006.201.22:39:51.67#ibcon#read 6, iclass 37, count 2 2006.201.22:39:51.67#ibcon#end of sib2, iclass 37, count 2 2006.201.22:39:51.67#ibcon#*mode == 0, iclass 37, count 2 2006.201.22:39:51.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.22:39:51.67#ibcon#[27=AT04-05\r\n] 2006.201.22:39:51.67#ibcon#*before write, iclass 37, count 2 2006.201.22:39:51.67#ibcon#enter sib2, iclass 37, count 2 2006.201.22:39:51.67#ibcon#flushed, iclass 37, count 2 2006.201.22:39:51.67#ibcon#about to write, iclass 37, count 2 2006.201.22:39:51.67#ibcon#wrote, iclass 37, count 2 2006.201.22:39:51.67#ibcon#about to read 3, iclass 37, count 2 2006.201.22:39:51.70#ibcon#read 3, iclass 37, count 2 2006.201.22:39:51.70#ibcon#about to read 4, iclass 37, count 2 2006.201.22:39:51.70#ibcon#read 4, iclass 37, count 2 2006.201.22:39:51.70#ibcon#about to read 5, iclass 37, count 2 2006.201.22:39:51.70#ibcon#read 5, iclass 37, count 2 2006.201.22:39:51.70#ibcon#about to read 6, iclass 37, count 2 2006.201.22:39:51.70#ibcon#read 6, iclass 37, count 2 2006.201.22:39:51.70#ibcon#end of sib2, iclass 37, count 2 2006.201.22:39:51.70#ibcon#*after write, iclass 37, count 2 2006.201.22:39:51.70#ibcon#*before return 0, iclass 37, count 2 2006.201.22:39:51.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:51.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.22:39:51.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.22:39:51.70#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:51.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:51.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:51.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:51.82#ibcon#enter wrdev, iclass 37, count 0 2006.201.22:39:51.82#ibcon#first serial, iclass 37, count 0 2006.201.22:39:51.82#ibcon#enter sib2, iclass 37, count 0 2006.201.22:39:51.82#ibcon#flushed, iclass 37, count 0 2006.201.22:39:51.82#ibcon#about to write, iclass 37, count 0 2006.201.22:39:51.82#ibcon#wrote, iclass 37, count 0 2006.201.22:39:51.82#ibcon#about to read 3, iclass 37, count 0 2006.201.22:39:51.84#ibcon#read 3, iclass 37, count 0 2006.201.22:39:51.84#ibcon#about to read 4, iclass 37, count 0 2006.201.22:39:51.84#ibcon#read 4, iclass 37, count 0 2006.201.22:39:51.84#ibcon#about to read 5, iclass 37, count 0 2006.201.22:39:51.84#ibcon#read 5, iclass 37, count 0 2006.201.22:39:51.84#ibcon#about to read 6, iclass 37, count 0 2006.201.22:39:51.84#ibcon#read 6, iclass 37, count 0 2006.201.22:39:51.84#ibcon#end of sib2, iclass 37, count 0 2006.201.22:39:51.84#ibcon#*mode == 0, iclass 37, count 0 2006.201.22:39:51.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.22:39:51.84#ibcon#[27=USB\r\n] 2006.201.22:39:51.84#ibcon#*before write, iclass 37, count 0 2006.201.22:39:51.84#ibcon#enter sib2, iclass 37, count 0 2006.201.22:39:51.84#ibcon#flushed, iclass 37, count 0 2006.201.22:39:51.84#ibcon#about to write, iclass 37, count 0 2006.201.22:39:51.84#ibcon#wrote, iclass 37, count 0 2006.201.22:39:51.84#ibcon#about to read 3, iclass 37, count 0 2006.201.22:39:51.87#ibcon#read 3, iclass 37, count 0 2006.201.22:39:51.87#ibcon#about to read 4, iclass 37, count 0 2006.201.22:39:51.87#ibcon#read 4, iclass 37, count 0 2006.201.22:39:51.87#ibcon#about to read 5, iclass 37, count 0 2006.201.22:39:51.87#ibcon#read 5, iclass 37, count 0 2006.201.22:39:51.87#ibcon#about to read 6, iclass 37, count 0 2006.201.22:39:51.87#ibcon#read 6, iclass 37, count 0 2006.201.22:39:51.87#ibcon#end of sib2, iclass 37, count 0 2006.201.22:39:51.87#ibcon#*after write, iclass 37, count 0 2006.201.22:39:51.87#ibcon#*before return 0, iclass 37, count 0 2006.201.22:39:51.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:51.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.22:39:51.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.22:39:51.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.22:39:51.87$vck44/vblo=5,709.99 2006.201.22:39:51.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.22:39:51.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.22:39:51.87#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:51.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:51.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:51.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:51.87#ibcon#enter wrdev, iclass 39, count 0 2006.201.22:39:51.87#ibcon#first serial, iclass 39, count 0 2006.201.22:39:51.87#ibcon#enter sib2, iclass 39, count 0 2006.201.22:39:51.87#ibcon#flushed, iclass 39, count 0 2006.201.22:39:51.87#ibcon#about to write, iclass 39, count 0 2006.201.22:39:51.87#ibcon#wrote, iclass 39, count 0 2006.201.22:39:51.87#ibcon#about to read 3, iclass 39, count 0 2006.201.22:39:51.89#ibcon#read 3, iclass 39, count 0 2006.201.22:39:51.89#ibcon#about to read 4, iclass 39, count 0 2006.201.22:39:51.89#ibcon#read 4, iclass 39, count 0 2006.201.22:39:51.89#ibcon#about to read 5, iclass 39, count 0 2006.201.22:39:51.89#ibcon#read 5, iclass 39, count 0 2006.201.22:39:51.89#ibcon#about to read 6, iclass 39, count 0 2006.201.22:39:51.89#ibcon#read 6, iclass 39, count 0 2006.201.22:39:51.89#ibcon#end of sib2, iclass 39, count 0 2006.201.22:39:51.89#ibcon#*mode == 0, iclass 39, count 0 2006.201.22:39:51.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.22:39:51.89#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.22:39:51.89#ibcon#*before write, iclass 39, count 0 2006.201.22:39:51.89#ibcon#enter sib2, iclass 39, count 0 2006.201.22:39:51.89#ibcon#flushed, iclass 39, count 0 2006.201.22:39:51.89#ibcon#about to write, iclass 39, count 0 2006.201.22:39:51.89#ibcon#wrote, iclass 39, count 0 2006.201.22:39:51.89#ibcon#about to read 3, iclass 39, count 0 2006.201.22:39:51.93#ibcon#read 3, iclass 39, count 0 2006.201.22:39:51.93#ibcon#about to read 4, iclass 39, count 0 2006.201.22:39:51.93#ibcon#read 4, iclass 39, count 0 2006.201.22:39:51.93#ibcon#about to read 5, iclass 39, count 0 2006.201.22:39:51.93#ibcon#read 5, iclass 39, count 0 2006.201.22:39:51.93#ibcon#about to read 6, iclass 39, count 0 2006.201.22:39:51.93#ibcon#read 6, iclass 39, count 0 2006.201.22:39:51.93#ibcon#end of sib2, iclass 39, count 0 2006.201.22:39:51.93#ibcon#*after write, iclass 39, count 0 2006.201.22:39:51.93#ibcon#*before return 0, iclass 39, count 0 2006.201.22:39:51.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:51.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.22:39:51.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.22:39:51.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.22:39:51.93$vck44/vb=5,4 2006.201.22:39:51.93#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.22:39:51.93#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.22:39:51.93#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:51.93#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:51.99#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:51.99#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:51.99#ibcon#enter wrdev, iclass 2, count 2 2006.201.22:39:51.99#ibcon#first serial, iclass 2, count 2 2006.201.22:39:51.99#ibcon#enter sib2, iclass 2, count 2 2006.201.22:39:51.99#ibcon#flushed, iclass 2, count 2 2006.201.22:39:51.99#ibcon#about to write, iclass 2, count 2 2006.201.22:39:51.99#ibcon#wrote, iclass 2, count 2 2006.201.22:39:51.99#ibcon#about to read 3, iclass 2, count 2 2006.201.22:39:52.01#ibcon#read 3, iclass 2, count 2 2006.201.22:39:52.01#ibcon#about to read 4, iclass 2, count 2 2006.201.22:39:52.01#ibcon#read 4, iclass 2, count 2 2006.201.22:39:52.01#ibcon#about to read 5, iclass 2, count 2 2006.201.22:39:52.01#ibcon#read 5, iclass 2, count 2 2006.201.22:39:52.01#ibcon#about to read 6, iclass 2, count 2 2006.201.22:39:52.01#ibcon#read 6, iclass 2, count 2 2006.201.22:39:52.01#ibcon#end of sib2, iclass 2, count 2 2006.201.22:39:52.01#ibcon#*mode == 0, iclass 2, count 2 2006.201.22:39:52.01#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.22:39:52.01#ibcon#[27=AT05-04\r\n] 2006.201.22:39:52.01#ibcon#*before write, iclass 2, count 2 2006.201.22:39:52.01#ibcon#enter sib2, iclass 2, count 2 2006.201.22:39:52.01#ibcon#flushed, iclass 2, count 2 2006.201.22:39:52.01#ibcon#about to write, iclass 2, count 2 2006.201.22:39:52.01#ibcon#wrote, iclass 2, count 2 2006.201.22:39:52.01#ibcon#about to read 3, iclass 2, count 2 2006.201.22:39:52.04#ibcon#read 3, iclass 2, count 2 2006.201.22:39:52.04#ibcon#about to read 4, iclass 2, count 2 2006.201.22:39:52.04#ibcon#read 4, iclass 2, count 2 2006.201.22:39:52.04#ibcon#about to read 5, iclass 2, count 2 2006.201.22:39:52.04#ibcon#read 5, iclass 2, count 2 2006.201.22:39:52.04#ibcon#about to read 6, iclass 2, count 2 2006.201.22:39:52.04#ibcon#read 6, iclass 2, count 2 2006.201.22:39:52.04#ibcon#end of sib2, iclass 2, count 2 2006.201.22:39:52.04#ibcon#*after write, iclass 2, count 2 2006.201.22:39:52.04#ibcon#*before return 0, iclass 2, count 2 2006.201.22:39:52.04#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:52.04#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.22:39:52.04#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.22:39:52.04#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:52.04#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:52.16#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:52.16#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:52.16#ibcon#enter wrdev, iclass 2, count 0 2006.201.22:39:52.16#ibcon#first serial, iclass 2, count 0 2006.201.22:39:52.16#ibcon#enter sib2, iclass 2, count 0 2006.201.22:39:52.16#ibcon#flushed, iclass 2, count 0 2006.201.22:39:52.16#ibcon#about to write, iclass 2, count 0 2006.201.22:39:52.16#ibcon#wrote, iclass 2, count 0 2006.201.22:39:52.16#ibcon#about to read 3, iclass 2, count 0 2006.201.22:39:52.18#ibcon#read 3, iclass 2, count 0 2006.201.22:39:52.18#ibcon#about to read 4, iclass 2, count 0 2006.201.22:39:52.18#ibcon#read 4, iclass 2, count 0 2006.201.22:39:52.18#ibcon#about to read 5, iclass 2, count 0 2006.201.22:39:52.18#ibcon#read 5, iclass 2, count 0 2006.201.22:39:52.18#ibcon#about to read 6, iclass 2, count 0 2006.201.22:39:52.18#ibcon#read 6, iclass 2, count 0 2006.201.22:39:52.18#ibcon#end of sib2, iclass 2, count 0 2006.201.22:39:52.18#ibcon#*mode == 0, iclass 2, count 0 2006.201.22:39:52.18#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.22:39:52.18#ibcon#[27=USB\r\n] 2006.201.22:39:52.18#ibcon#*before write, iclass 2, count 0 2006.201.22:39:52.18#ibcon#enter sib2, iclass 2, count 0 2006.201.22:39:52.18#ibcon#flushed, iclass 2, count 0 2006.201.22:39:52.18#ibcon#about to write, iclass 2, count 0 2006.201.22:39:52.18#ibcon#wrote, iclass 2, count 0 2006.201.22:39:52.18#ibcon#about to read 3, iclass 2, count 0 2006.201.22:39:52.21#ibcon#read 3, iclass 2, count 0 2006.201.22:39:52.21#ibcon#about to read 4, iclass 2, count 0 2006.201.22:39:52.21#ibcon#read 4, iclass 2, count 0 2006.201.22:39:52.21#ibcon#about to read 5, iclass 2, count 0 2006.201.22:39:52.21#ibcon#read 5, iclass 2, count 0 2006.201.22:39:52.21#ibcon#about to read 6, iclass 2, count 0 2006.201.22:39:52.21#ibcon#read 6, iclass 2, count 0 2006.201.22:39:52.21#ibcon#end of sib2, iclass 2, count 0 2006.201.22:39:52.21#ibcon#*after write, iclass 2, count 0 2006.201.22:39:52.21#ibcon#*before return 0, iclass 2, count 0 2006.201.22:39:52.21#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:52.21#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.22:39:52.21#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.22:39:52.21#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.22:39:52.21$vck44/vblo=6,719.99 2006.201.22:39:52.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.22:39:52.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.22:39:52.21#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:52.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:52.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:52.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:52.21#ibcon#enter wrdev, iclass 5, count 0 2006.201.22:39:52.21#ibcon#first serial, iclass 5, count 0 2006.201.22:39:52.21#ibcon#enter sib2, iclass 5, count 0 2006.201.22:39:52.21#ibcon#flushed, iclass 5, count 0 2006.201.22:39:52.21#ibcon#about to write, iclass 5, count 0 2006.201.22:39:52.21#ibcon#wrote, iclass 5, count 0 2006.201.22:39:52.21#ibcon#about to read 3, iclass 5, count 0 2006.201.22:39:52.23#ibcon#read 3, iclass 5, count 0 2006.201.22:39:52.23#ibcon#about to read 4, iclass 5, count 0 2006.201.22:39:52.23#ibcon#read 4, iclass 5, count 0 2006.201.22:39:52.23#ibcon#about to read 5, iclass 5, count 0 2006.201.22:39:52.23#ibcon#read 5, iclass 5, count 0 2006.201.22:39:52.23#ibcon#about to read 6, iclass 5, count 0 2006.201.22:39:52.23#ibcon#read 6, iclass 5, count 0 2006.201.22:39:52.23#ibcon#end of sib2, iclass 5, count 0 2006.201.22:39:52.23#ibcon#*mode == 0, iclass 5, count 0 2006.201.22:39:52.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.22:39:52.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.22:39:52.23#ibcon#*before write, iclass 5, count 0 2006.201.22:39:52.23#ibcon#enter sib2, iclass 5, count 0 2006.201.22:39:52.23#ibcon#flushed, iclass 5, count 0 2006.201.22:39:52.23#ibcon#about to write, iclass 5, count 0 2006.201.22:39:52.23#ibcon#wrote, iclass 5, count 0 2006.201.22:39:52.23#ibcon#about to read 3, iclass 5, count 0 2006.201.22:39:52.27#ibcon#read 3, iclass 5, count 0 2006.201.22:39:52.27#ibcon#about to read 4, iclass 5, count 0 2006.201.22:39:52.27#ibcon#read 4, iclass 5, count 0 2006.201.22:39:52.27#ibcon#about to read 5, iclass 5, count 0 2006.201.22:39:52.27#ibcon#read 5, iclass 5, count 0 2006.201.22:39:52.27#ibcon#about to read 6, iclass 5, count 0 2006.201.22:39:52.27#ibcon#read 6, iclass 5, count 0 2006.201.22:39:52.27#ibcon#end of sib2, iclass 5, count 0 2006.201.22:39:52.27#ibcon#*after write, iclass 5, count 0 2006.201.22:39:52.27#ibcon#*before return 0, iclass 5, count 0 2006.201.22:39:52.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:52.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.22:39:52.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.22:39:52.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.22:39:52.27$vck44/vb=6,4 2006.201.22:39:52.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.22:39:52.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.22:39:52.27#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:52.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:52.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:52.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:52.33#ibcon#enter wrdev, iclass 7, count 2 2006.201.22:39:52.33#ibcon#first serial, iclass 7, count 2 2006.201.22:39:52.33#ibcon#enter sib2, iclass 7, count 2 2006.201.22:39:52.33#ibcon#flushed, iclass 7, count 2 2006.201.22:39:52.33#ibcon#about to write, iclass 7, count 2 2006.201.22:39:52.33#ibcon#wrote, iclass 7, count 2 2006.201.22:39:52.33#ibcon#about to read 3, iclass 7, count 2 2006.201.22:39:52.35#ibcon#read 3, iclass 7, count 2 2006.201.22:39:52.35#ibcon#about to read 4, iclass 7, count 2 2006.201.22:39:52.35#ibcon#read 4, iclass 7, count 2 2006.201.22:39:52.35#ibcon#about to read 5, iclass 7, count 2 2006.201.22:39:52.35#ibcon#read 5, iclass 7, count 2 2006.201.22:39:52.35#ibcon#about to read 6, iclass 7, count 2 2006.201.22:39:52.35#ibcon#read 6, iclass 7, count 2 2006.201.22:39:52.35#ibcon#end of sib2, iclass 7, count 2 2006.201.22:39:52.35#ibcon#*mode == 0, iclass 7, count 2 2006.201.22:39:52.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.22:39:52.35#ibcon#[27=AT06-04\r\n] 2006.201.22:39:52.35#ibcon#*before write, iclass 7, count 2 2006.201.22:39:52.35#ibcon#enter sib2, iclass 7, count 2 2006.201.22:39:52.35#ibcon#flushed, iclass 7, count 2 2006.201.22:39:52.35#ibcon#about to write, iclass 7, count 2 2006.201.22:39:52.35#ibcon#wrote, iclass 7, count 2 2006.201.22:39:52.35#ibcon#about to read 3, iclass 7, count 2 2006.201.22:39:52.38#ibcon#read 3, iclass 7, count 2 2006.201.22:39:52.38#ibcon#about to read 4, iclass 7, count 2 2006.201.22:39:52.38#ibcon#read 4, iclass 7, count 2 2006.201.22:39:52.38#ibcon#about to read 5, iclass 7, count 2 2006.201.22:39:52.38#ibcon#read 5, iclass 7, count 2 2006.201.22:39:52.38#ibcon#about to read 6, iclass 7, count 2 2006.201.22:39:52.38#ibcon#read 6, iclass 7, count 2 2006.201.22:39:52.38#ibcon#end of sib2, iclass 7, count 2 2006.201.22:39:52.38#ibcon#*after write, iclass 7, count 2 2006.201.22:39:52.38#ibcon#*before return 0, iclass 7, count 2 2006.201.22:39:52.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:52.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.22:39:52.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.22:39:52.38#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:52.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:52.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:52.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:52.50#ibcon#enter wrdev, iclass 7, count 0 2006.201.22:39:52.50#ibcon#first serial, iclass 7, count 0 2006.201.22:39:52.50#ibcon#enter sib2, iclass 7, count 0 2006.201.22:39:52.50#ibcon#flushed, iclass 7, count 0 2006.201.22:39:52.50#ibcon#about to write, iclass 7, count 0 2006.201.22:39:52.50#ibcon#wrote, iclass 7, count 0 2006.201.22:39:52.50#ibcon#about to read 3, iclass 7, count 0 2006.201.22:39:52.52#ibcon#read 3, iclass 7, count 0 2006.201.22:39:52.52#ibcon#about to read 4, iclass 7, count 0 2006.201.22:39:52.52#ibcon#read 4, iclass 7, count 0 2006.201.22:39:52.52#ibcon#about to read 5, iclass 7, count 0 2006.201.22:39:52.52#ibcon#read 5, iclass 7, count 0 2006.201.22:39:52.52#ibcon#about to read 6, iclass 7, count 0 2006.201.22:39:52.52#ibcon#read 6, iclass 7, count 0 2006.201.22:39:52.52#ibcon#end of sib2, iclass 7, count 0 2006.201.22:39:52.52#ibcon#*mode == 0, iclass 7, count 0 2006.201.22:39:52.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.22:39:52.52#ibcon#[27=USB\r\n] 2006.201.22:39:52.52#ibcon#*before write, iclass 7, count 0 2006.201.22:39:52.52#ibcon#enter sib2, iclass 7, count 0 2006.201.22:39:52.52#ibcon#flushed, iclass 7, count 0 2006.201.22:39:52.52#ibcon#about to write, iclass 7, count 0 2006.201.22:39:52.52#ibcon#wrote, iclass 7, count 0 2006.201.22:39:52.52#ibcon#about to read 3, iclass 7, count 0 2006.201.22:39:52.55#ibcon#read 3, iclass 7, count 0 2006.201.22:39:52.55#ibcon#about to read 4, iclass 7, count 0 2006.201.22:39:52.55#ibcon#read 4, iclass 7, count 0 2006.201.22:39:52.55#ibcon#about to read 5, iclass 7, count 0 2006.201.22:39:52.55#ibcon#read 5, iclass 7, count 0 2006.201.22:39:52.55#ibcon#about to read 6, iclass 7, count 0 2006.201.22:39:52.55#ibcon#read 6, iclass 7, count 0 2006.201.22:39:52.55#ibcon#end of sib2, iclass 7, count 0 2006.201.22:39:52.55#ibcon#*after write, iclass 7, count 0 2006.201.22:39:52.55#ibcon#*before return 0, iclass 7, count 0 2006.201.22:39:52.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:52.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.22:39:52.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.22:39:52.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.22:39:52.55$vck44/vblo=7,734.99 2006.201.22:39:52.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.22:39:52.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.22:39:52.55#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:52.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:52.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:52.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:52.55#ibcon#enter wrdev, iclass 11, count 0 2006.201.22:39:52.55#ibcon#first serial, iclass 11, count 0 2006.201.22:39:52.55#ibcon#enter sib2, iclass 11, count 0 2006.201.22:39:52.55#ibcon#flushed, iclass 11, count 0 2006.201.22:39:52.55#ibcon#about to write, iclass 11, count 0 2006.201.22:39:52.55#ibcon#wrote, iclass 11, count 0 2006.201.22:39:52.55#ibcon#about to read 3, iclass 11, count 0 2006.201.22:39:52.57#ibcon#read 3, iclass 11, count 0 2006.201.22:39:52.57#ibcon#about to read 4, iclass 11, count 0 2006.201.22:39:52.57#ibcon#read 4, iclass 11, count 0 2006.201.22:39:52.57#ibcon#about to read 5, iclass 11, count 0 2006.201.22:39:52.57#ibcon#read 5, iclass 11, count 0 2006.201.22:39:52.57#ibcon#about to read 6, iclass 11, count 0 2006.201.22:39:52.57#ibcon#read 6, iclass 11, count 0 2006.201.22:39:52.57#ibcon#end of sib2, iclass 11, count 0 2006.201.22:39:52.57#ibcon#*mode == 0, iclass 11, count 0 2006.201.22:39:52.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.22:39:52.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.22:39:52.57#ibcon#*before write, iclass 11, count 0 2006.201.22:39:52.57#ibcon#enter sib2, iclass 11, count 0 2006.201.22:39:52.57#ibcon#flushed, iclass 11, count 0 2006.201.22:39:52.57#ibcon#about to write, iclass 11, count 0 2006.201.22:39:52.57#ibcon#wrote, iclass 11, count 0 2006.201.22:39:52.57#ibcon#about to read 3, iclass 11, count 0 2006.201.22:39:52.61#ibcon#read 3, iclass 11, count 0 2006.201.22:39:52.61#ibcon#about to read 4, iclass 11, count 0 2006.201.22:39:52.61#ibcon#read 4, iclass 11, count 0 2006.201.22:39:52.61#ibcon#about to read 5, iclass 11, count 0 2006.201.22:39:52.61#ibcon#read 5, iclass 11, count 0 2006.201.22:39:52.61#ibcon#about to read 6, iclass 11, count 0 2006.201.22:39:52.61#ibcon#read 6, iclass 11, count 0 2006.201.22:39:52.61#ibcon#end of sib2, iclass 11, count 0 2006.201.22:39:52.61#ibcon#*after write, iclass 11, count 0 2006.201.22:39:52.61#ibcon#*before return 0, iclass 11, count 0 2006.201.22:39:52.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:52.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.22:39:52.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.22:39:52.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.22:39:52.61$vck44/vb=7,4 2006.201.22:39:52.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.22:39:52.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.22:39:52.61#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:52.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:52.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:52.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:52.67#ibcon#enter wrdev, iclass 13, count 2 2006.201.22:39:52.67#ibcon#first serial, iclass 13, count 2 2006.201.22:39:52.67#ibcon#enter sib2, iclass 13, count 2 2006.201.22:39:52.67#ibcon#flushed, iclass 13, count 2 2006.201.22:39:52.67#ibcon#about to write, iclass 13, count 2 2006.201.22:39:52.67#ibcon#wrote, iclass 13, count 2 2006.201.22:39:52.67#ibcon#about to read 3, iclass 13, count 2 2006.201.22:39:52.69#ibcon#read 3, iclass 13, count 2 2006.201.22:39:52.69#ibcon#about to read 4, iclass 13, count 2 2006.201.22:39:52.69#ibcon#read 4, iclass 13, count 2 2006.201.22:39:52.69#ibcon#about to read 5, iclass 13, count 2 2006.201.22:39:52.69#ibcon#read 5, iclass 13, count 2 2006.201.22:39:52.69#ibcon#about to read 6, iclass 13, count 2 2006.201.22:39:52.69#ibcon#read 6, iclass 13, count 2 2006.201.22:39:52.69#ibcon#end of sib2, iclass 13, count 2 2006.201.22:39:52.69#ibcon#*mode == 0, iclass 13, count 2 2006.201.22:39:52.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.22:39:52.69#ibcon#[27=AT07-04\r\n] 2006.201.22:39:52.69#ibcon#*before write, iclass 13, count 2 2006.201.22:39:52.69#ibcon#enter sib2, iclass 13, count 2 2006.201.22:39:52.69#ibcon#flushed, iclass 13, count 2 2006.201.22:39:52.69#ibcon#about to write, iclass 13, count 2 2006.201.22:39:52.69#ibcon#wrote, iclass 13, count 2 2006.201.22:39:52.69#ibcon#about to read 3, iclass 13, count 2 2006.201.22:39:52.72#ibcon#read 3, iclass 13, count 2 2006.201.22:39:52.72#ibcon#about to read 4, iclass 13, count 2 2006.201.22:39:52.72#ibcon#read 4, iclass 13, count 2 2006.201.22:39:52.72#ibcon#about to read 5, iclass 13, count 2 2006.201.22:39:52.72#ibcon#read 5, iclass 13, count 2 2006.201.22:39:52.72#ibcon#about to read 6, iclass 13, count 2 2006.201.22:39:52.72#ibcon#read 6, iclass 13, count 2 2006.201.22:39:52.72#ibcon#end of sib2, iclass 13, count 2 2006.201.22:39:52.72#ibcon#*after write, iclass 13, count 2 2006.201.22:39:52.72#ibcon#*before return 0, iclass 13, count 2 2006.201.22:39:52.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:52.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.22:39:52.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.22:39:52.72#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:52.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:52.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:52.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:52.84#ibcon#enter wrdev, iclass 13, count 0 2006.201.22:39:52.84#ibcon#first serial, iclass 13, count 0 2006.201.22:39:52.84#ibcon#enter sib2, iclass 13, count 0 2006.201.22:39:52.84#ibcon#flushed, iclass 13, count 0 2006.201.22:39:52.84#ibcon#about to write, iclass 13, count 0 2006.201.22:39:52.84#ibcon#wrote, iclass 13, count 0 2006.201.22:39:52.84#ibcon#about to read 3, iclass 13, count 0 2006.201.22:39:52.86#ibcon#read 3, iclass 13, count 0 2006.201.22:39:52.86#ibcon#about to read 4, iclass 13, count 0 2006.201.22:39:52.86#ibcon#read 4, iclass 13, count 0 2006.201.22:39:52.86#ibcon#about to read 5, iclass 13, count 0 2006.201.22:39:52.86#ibcon#read 5, iclass 13, count 0 2006.201.22:39:52.86#ibcon#about to read 6, iclass 13, count 0 2006.201.22:39:52.86#ibcon#read 6, iclass 13, count 0 2006.201.22:39:52.86#ibcon#end of sib2, iclass 13, count 0 2006.201.22:39:52.86#ibcon#*mode == 0, iclass 13, count 0 2006.201.22:39:52.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.22:39:52.86#ibcon#[27=USB\r\n] 2006.201.22:39:52.86#ibcon#*before write, iclass 13, count 0 2006.201.22:39:52.86#ibcon#enter sib2, iclass 13, count 0 2006.201.22:39:52.86#ibcon#flushed, iclass 13, count 0 2006.201.22:39:52.86#ibcon#about to write, iclass 13, count 0 2006.201.22:39:52.86#ibcon#wrote, iclass 13, count 0 2006.201.22:39:52.86#ibcon#about to read 3, iclass 13, count 0 2006.201.22:39:52.89#ibcon#read 3, iclass 13, count 0 2006.201.22:39:52.89#ibcon#about to read 4, iclass 13, count 0 2006.201.22:39:52.89#ibcon#read 4, iclass 13, count 0 2006.201.22:39:52.89#ibcon#about to read 5, iclass 13, count 0 2006.201.22:39:52.89#ibcon#read 5, iclass 13, count 0 2006.201.22:39:52.89#ibcon#about to read 6, iclass 13, count 0 2006.201.22:39:52.89#ibcon#read 6, iclass 13, count 0 2006.201.22:39:52.89#ibcon#end of sib2, iclass 13, count 0 2006.201.22:39:52.89#ibcon#*after write, iclass 13, count 0 2006.201.22:39:52.89#ibcon#*before return 0, iclass 13, count 0 2006.201.22:39:52.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:52.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.22:39:52.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.22:39:52.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.22:39:52.89$vck44/vblo=8,744.99 2006.201.22:39:52.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.22:39:52.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.22:39:52.89#ibcon#ireg 17 cls_cnt 0 2006.201.22:39:52.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:52.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:52.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:52.89#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:39:52.89#ibcon#first serial, iclass 15, count 0 2006.201.22:39:52.89#ibcon#enter sib2, iclass 15, count 0 2006.201.22:39:52.89#ibcon#flushed, iclass 15, count 0 2006.201.22:39:52.89#ibcon#about to write, iclass 15, count 0 2006.201.22:39:52.89#ibcon#wrote, iclass 15, count 0 2006.201.22:39:52.89#ibcon#about to read 3, iclass 15, count 0 2006.201.22:39:52.91#ibcon#read 3, iclass 15, count 0 2006.201.22:39:52.91#ibcon#about to read 4, iclass 15, count 0 2006.201.22:39:52.91#ibcon#read 4, iclass 15, count 0 2006.201.22:39:52.91#ibcon#about to read 5, iclass 15, count 0 2006.201.22:39:52.91#ibcon#read 5, iclass 15, count 0 2006.201.22:39:52.91#ibcon#about to read 6, iclass 15, count 0 2006.201.22:39:52.91#ibcon#read 6, iclass 15, count 0 2006.201.22:39:52.91#ibcon#end of sib2, iclass 15, count 0 2006.201.22:39:52.91#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:39:52.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:39:52.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.22:39:52.91#ibcon#*before write, iclass 15, count 0 2006.201.22:39:52.91#ibcon#enter sib2, iclass 15, count 0 2006.201.22:39:52.91#ibcon#flushed, iclass 15, count 0 2006.201.22:39:52.91#ibcon#about to write, iclass 15, count 0 2006.201.22:39:52.91#ibcon#wrote, iclass 15, count 0 2006.201.22:39:52.91#ibcon#about to read 3, iclass 15, count 0 2006.201.22:39:52.96#ibcon#read 3, iclass 15, count 0 2006.201.22:39:52.96#ibcon#about to read 4, iclass 15, count 0 2006.201.22:39:52.96#ibcon#read 4, iclass 15, count 0 2006.201.22:39:52.96#ibcon#about to read 5, iclass 15, count 0 2006.201.22:39:52.96#ibcon#read 5, iclass 15, count 0 2006.201.22:39:52.96#ibcon#about to read 6, iclass 15, count 0 2006.201.22:39:52.96#ibcon#read 6, iclass 15, count 0 2006.201.22:39:52.96#ibcon#end of sib2, iclass 15, count 0 2006.201.22:39:52.96#ibcon#*after write, iclass 15, count 0 2006.201.22:39:52.96#ibcon#*before return 0, iclass 15, count 0 2006.201.22:39:52.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:52.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.22:39:52.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:39:52.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:39:52.96$vck44/vb=8,4 2006.201.22:39:52.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.22:39:52.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.22:39:52.96#ibcon#ireg 11 cls_cnt 2 2006.201.22:39:52.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:53.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:53.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:53.01#ibcon#enter wrdev, iclass 17, count 2 2006.201.22:39:53.01#ibcon#first serial, iclass 17, count 2 2006.201.22:39:53.01#ibcon#enter sib2, iclass 17, count 2 2006.201.22:39:53.01#ibcon#flushed, iclass 17, count 2 2006.201.22:39:53.01#ibcon#about to write, iclass 17, count 2 2006.201.22:39:53.01#ibcon#wrote, iclass 17, count 2 2006.201.22:39:53.01#ibcon#about to read 3, iclass 17, count 2 2006.201.22:39:53.03#ibcon#read 3, iclass 17, count 2 2006.201.22:39:53.03#ibcon#about to read 4, iclass 17, count 2 2006.201.22:39:53.03#ibcon#read 4, iclass 17, count 2 2006.201.22:39:53.03#ibcon#about to read 5, iclass 17, count 2 2006.201.22:39:53.03#ibcon#read 5, iclass 17, count 2 2006.201.22:39:53.03#ibcon#about to read 6, iclass 17, count 2 2006.201.22:39:53.03#ibcon#read 6, iclass 17, count 2 2006.201.22:39:53.03#ibcon#end of sib2, iclass 17, count 2 2006.201.22:39:53.03#ibcon#*mode == 0, iclass 17, count 2 2006.201.22:39:53.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.22:39:53.03#ibcon#[27=AT08-04\r\n] 2006.201.22:39:53.03#ibcon#*before write, iclass 17, count 2 2006.201.22:39:53.03#ibcon#enter sib2, iclass 17, count 2 2006.201.22:39:53.03#ibcon#flushed, iclass 17, count 2 2006.201.22:39:53.03#ibcon#about to write, iclass 17, count 2 2006.201.22:39:53.03#ibcon#wrote, iclass 17, count 2 2006.201.22:39:53.03#ibcon#about to read 3, iclass 17, count 2 2006.201.22:39:53.06#ibcon#read 3, iclass 17, count 2 2006.201.22:39:53.06#ibcon#about to read 4, iclass 17, count 2 2006.201.22:39:53.06#ibcon#read 4, iclass 17, count 2 2006.201.22:39:53.06#ibcon#about to read 5, iclass 17, count 2 2006.201.22:39:53.06#ibcon#read 5, iclass 17, count 2 2006.201.22:39:53.06#ibcon#about to read 6, iclass 17, count 2 2006.201.22:39:53.06#ibcon#read 6, iclass 17, count 2 2006.201.22:39:53.06#ibcon#end of sib2, iclass 17, count 2 2006.201.22:39:53.06#ibcon#*after write, iclass 17, count 2 2006.201.22:39:53.06#ibcon#*before return 0, iclass 17, count 2 2006.201.22:39:53.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:53.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.22:39:53.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.22:39:53.06#ibcon#ireg 7 cls_cnt 0 2006.201.22:39:53.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:53.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:53.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:53.18#ibcon#enter wrdev, iclass 17, count 0 2006.201.22:39:53.18#ibcon#first serial, iclass 17, count 0 2006.201.22:39:53.18#ibcon#enter sib2, iclass 17, count 0 2006.201.22:39:53.18#ibcon#flushed, iclass 17, count 0 2006.201.22:39:53.18#ibcon#about to write, iclass 17, count 0 2006.201.22:39:53.18#ibcon#wrote, iclass 17, count 0 2006.201.22:39:53.18#ibcon#about to read 3, iclass 17, count 0 2006.201.22:39:53.20#ibcon#read 3, iclass 17, count 0 2006.201.22:39:53.20#ibcon#about to read 4, iclass 17, count 0 2006.201.22:39:53.20#ibcon#read 4, iclass 17, count 0 2006.201.22:39:53.20#ibcon#about to read 5, iclass 17, count 0 2006.201.22:39:53.20#ibcon#read 5, iclass 17, count 0 2006.201.22:39:53.20#ibcon#about to read 6, iclass 17, count 0 2006.201.22:39:53.20#ibcon#read 6, iclass 17, count 0 2006.201.22:39:53.20#ibcon#end of sib2, iclass 17, count 0 2006.201.22:39:53.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.22:39:53.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.22:39:53.20#ibcon#[27=USB\r\n] 2006.201.22:39:53.20#ibcon#*before write, iclass 17, count 0 2006.201.22:39:53.20#ibcon#enter sib2, iclass 17, count 0 2006.201.22:39:53.20#ibcon#flushed, iclass 17, count 0 2006.201.22:39:53.20#ibcon#about to write, iclass 17, count 0 2006.201.22:39:53.20#ibcon#wrote, iclass 17, count 0 2006.201.22:39:53.20#ibcon#about to read 3, iclass 17, count 0 2006.201.22:39:53.23#ibcon#read 3, iclass 17, count 0 2006.201.22:39:53.23#ibcon#about to read 4, iclass 17, count 0 2006.201.22:39:53.23#ibcon#read 4, iclass 17, count 0 2006.201.22:39:53.23#ibcon#about to read 5, iclass 17, count 0 2006.201.22:39:53.23#ibcon#read 5, iclass 17, count 0 2006.201.22:39:53.23#ibcon#about to read 6, iclass 17, count 0 2006.201.22:39:53.23#ibcon#read 6, iclass 17, count 0 2006.201.22:39:53.23#ibcon#end of sib2, iclass 17, count 0 2006.201.22:39:53.23#ibcon#*after write, iclass 17, count 0 2006.201.22:39:53.23#ibcon#*before return 0, iclass 17, count 0 2006.201.22:39:53.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:53.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.22:39:53.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.22:39:53.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.22:39:53.23$vck44/vabw=wide 2006.201.22:39:53.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.22:39:53.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.22:39:53.23#ibcon#ireg 8 cls_cnt 0 2006.201.22:39:53.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:53.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:53.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:53.23#ibcon#enter wrdev, iclass 19, count 0 2006.201.22:39:53.23#ibcon#first serial, iclass 19, count 0 2006.201.22:39:53.23#ibcon#enter sib2, iclass 19, count 0 2006.201.22:39:53.23#ibcon#flushed, iclass 19, count 0 2006.201.22:39:53.23#ibcon#about to write, iclass 19, count 0 2006.201.22:39:53.23#ibcon#wrote, iclass 19, count 0 2006.201.22:39:53.23#ibcon#about to read 3, iclass 19, count 0 2006.201.22:39:53.25#ibcon#read 3, iclass 19, count 0 2006.201.22:39:53.25#ibcon#about to read 4, iclass 19, count 0 2006.201.22:39:53.25#ibcon#read 4, iclass 19, count 0 2006.201.22:39:53.25#ibcon#about to read 5, iclass 19, count 0 2006.201.22:39:53.25#ibcon#read 5, iclass 19, count 0 2006.201.22:39:53.25#ibcon#about to read 6, iclass 19, count 0 2006.201.22:39:53.25#ibcon#read 6, iclass 19, count 0 2006.201.22:39:53.25#ibcon#end of sib2, iclass 19, count 0 2006.201.22:39:53.25#ibcon#*mode == 0, iclass 19, count 0 2006.201.22:39:53.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.22:39:53.25#ibcon#[25=BW32\r\n] 2006.201.22:39:53.25#ibcon#*before write, iclass 19, count 0 2006.201.22:39:53.25#ibcon#enter sib2, iclass 19, count 0 2006.201.22:39:53.25#ibcon#flushed, iclass 19, count 0 2006.201.22:39:53.25#ibcon#about to write, iclass 19, count 0 2006.201.22:39:53.25#ibcon#wrote, iclass 19, count 0 2006.201.22:39:53.25#ibcon#about to read 3, iclass 19, count 0 2006.201.22:39:53.28#ibcon#read 3, iclass 19, count 0 2006.201.22:39:53.28#ibcon#about to read 4, iclass 19, count 0 2006.201.22:39:53.28#ibcon#read 4, iclass 19, count 0 2006.201.22:39:53.28#ibcon#about to read 5, iclass 19, count 0 2006.201.22:39:53.28#ibcon#read 5, iclass 19, count 0 2006.201.22:39:53.28#ibcon#about to read 6, iclass 19, count 0 2006.201.22:39:53.28#ibcon#read 6, iclass 19, count 0 2006.201.22:39:53.28#ibcon#end of sib2, iclass 19, count 0 2006.201.22:39:53.28#ibcon#*after write, iclass 19, count 0 2006.201.22:39:53.28#ibcon#*before return 0, iclass 19, count 0 2006.201.22:39:53.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:53.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.22:39:53.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.22:39:53.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.22:39:53.28$vck44/vbbw=wide 2006.201.22:39:53.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.22:39:53.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.22:39:53.28#ibcon#ireg 8 cls_cnt 0 2006.201.22:39:53.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:39:53.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:39:53.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:39:53.35#ibcon#enter wrdev, iclass 21, count 0 2006.201.22:39:53.35#ibcon#first serial, iclass 21, count 0 2006.201.22:39:53.35#ibcon#enter sib2, iclass 21, count 0 2006.201.22:39:53.35#ibcon#flushed, iclass 21, count 0 2006.201.22:39:53.35#ibcon#about to write, iclass 21, count 0 2006.201.22:39:53.35#ibcon#wrote, iclass 21, count 0 2006.201.22:39:53.35#ibcon#about to read 3, iclass 21, count 0 2006.201.22:39:53.37#ibcon#read 3, iclass 21, count 0 2006.201.22:39:53.37#ibcon#about to read 4, iclass 21, count 0 2006.201.22:39:53.37#ibcon#read 4, iclass 21, count 0 2006.201.22:39:53.37#ibcon#about to read 5, iclass 21, count 0 2006.201.22:39:53.37#ibcon#read 5, iclass 21, count 0 2006.201.22:39:53.37#ibcon#about to read 6, iclass 21, count 0 2006.201.22:39:53.37#ibcon#read 6, iclass 21, count 0 2006.201.22:39:53.37#ibcon#end of sib2, iclass 21, count 0 2006.201.22:39:53.37#ibcon#*mode == 0, iclass 21, count 0 2006.201.22:39:53.37#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.22:39:53.37#ibcon#[27=BW32\r\n] 2006.201.22:39:53.37#ibcon#*before write, iclass 21, count 0 2006.201.22:39:53.37#ibcon#enter sib2, iclass 21, count 0 2006.201.22:39:53.37#ibcon#flushed, iclass 21, count 0 2006.201.22:39:53.37#ibcon#about to write, iclass 21, count 0 2006.201.22:39:53.37#ibcon#wrote, iclass 21, count 0 2006.201.22:39:53.37#ibcon#about to read 3, iclass 21, count 0 2006.201.22:39:53.40#ibcon#read 3, iclass 21, count 0 2006.201.22:39:53.40#ibcon#about to read 4, iclass 21, count 0 2006.201.22:39:53.40#ibcon#read 4, iclass 21, count 0 2006.201.22:39:53.40#ibcon#about to read 5, iclass 21, count 0 2006.201.22:39:53.40#ibcon#read 5, iclass 21, count 0 2006.201.22:39:53.40#ibcon#about to read 6, iclass 21, count 0 2006.201.22:39:53.40#ibcon#read 6, iclass 21, count 0 2006.201.22:39:53.40#ibcon#end of sib2, iclass 21, count 0 2006.201.22:39:53.40#ibcon#*after write, iclass 21, count 0 2006.201.22:39:53.40#ibcon#*before return 0, iclass 21, count 0 2006.201.22:39:53.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:39:53.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:39:53.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.22:39:53.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.22:39:53.40$setupk4/ifdk4 2006.201.22:39:53.40$ifdk4/lo= 2006.201.22:39:53.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.22:39:53.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.22:39:53.40$ifdk4/patch= 2006.201.22:39:53.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.22:39:53.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.22:39:53.40$setupk4/!*+20s 2006.201.22:39:58.07#abcon#<5=/04 1.9 4.4 20.051001001.5\r\n> 2006.201.22:39:58.09#abcon#{5=INTERFACE CLEAR} 2006.201.22:39:58.15#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:40:07.88$setupk4/"tpicd 2006.201.22:40:07.88$setupk4/echo=off 2006.201.22:40:07.88$setupk4/xlog=off 2006.201.22:40:07.88:!2006.201.22:42:37 2006.201.22:40:26.14#trakl#Source acquired 2006.201.22:40:28.14#flagr#flagr/antenna,acquired 2006.201.22:42:37.00:preob 2006.201.22:42:38.13/onsource/TRACKING 2006.201.22:42:38.13:!2006.201.22:42:47 2006.201.22:42:47.00:"tape 2006.201.22:42:47.00:"st=record 2006.201.22:42:47.00:data_valid=on 2006.201.22:42:47.00:midob 2006.201.22:42:47.13/onsource/TRACKING 2006.201.22:42:47.13/wx/20.02,1001.5,100 2006.201.22:42:47.34/cable/+6.4833E-03 2006.201.22:42:48.43/va/01,08,usb,yes,48,51 2006.201.22:42:48.43/va/02,07,usb,yes,52,53 2006.201.22:42:48.43/va/03,08,usb,yes,47,49 2006.201.22:42:48.43/va/04,07,usb,yes,53,56 2006.201.22:42:48.43/va/05,04,usb,yes,48,49 2006.201.22:42:48.43/va/06,05,usb,yes,48,48 2006.201.22:42:48.43/va/07,05,usb,yes,47,48 2006.201.22:42:48.43/va/08,04,usb,yes,46,55 2006.201.22:42:48.66/valo/01,524.99,yes,locked 2006.201.22:42:48.66/valo/02,534.99,yes,locked 2006.201.22:42:48.66/valo/03,564.99,yes,locked 2006.201.22:42:48.66/valo/04,624.99,yes,locked 2006.201.22:42:48.66/valo/05,734.99,yes,locked 2006.201.22:42:48.66/valo/06,814.99,yes,locked 2006.201.22:42:48.66/valo/07,864.99,yes,locked 2006.201.22:42:48.66/valo/08,884.99,yes,locked 2006.201.22:42:49.75/vb/01,04,usb,yes,31,29 2006.201.22:42:49.75/vb/02,05,usb,yes,29,29 2006.201.22:42:49.75/vb/03,04,usb,yes,30,33 2006.201.22:42:49.75/vb/04,05,usb,yes,31,29 2006.201.22:42:49.75/vb/05,04,usb,yes,27,30 2006.201.22:42:49.75/vb/06,04,usb,yes,32,28 2006.201.22:42:49.75/vb/07,04,usb,yes,31,31 2006.201.22:42:49.75/vb/08,04,usb,yes,29,32 2006.201.22:42:49.99/vblo/01,629.99,yes,locked 2006.201.22:42:49.99/vblo/02,634.99,yes,locked 2006.201.22:42:49.99/vblo/03,649.99,yes,locked 2006.201.22:42:49.99/vblo/04,679.99,yes,locked 2006.201.22:42:49.99/vblo/05,709.99,yes,locked 2006.201.22:42:49.99/vblo/06,719.99,yes,locked 2006.201.22:42:49.99/vblo/07,734.99,yes,locked 2006.201.22:42:49.99/vblo/08,744.99,yes,locked 2006.201.22:42:50.14/vabw/8 2006.201.22:42:50.29/vbbw/8 2006.201.22:42:50.38/xfe/off,on,15.5 2006.201.22:42:50.77/ifatt/23,28,28,28 2006.201.22:42:51.07/fmout-gps/S +4.54E-07 2006.201.22:42:51.14:!2006.201.22:46:37 2006.201.22:46:37.00:data_valid=off 2006.201.22:46:37.00:"et 2006.201.22:46:37.00:!+3s 2006.201.22:46:40.02:"tape 2006.201.22:46:40.02:postob 2006.201.22:46:40.14/cable/+6.4834E-03 2006.201.22:46:40.14/wx/20.03,1001.3,100 2006.201.22:46:40.20/fmout-gps/S +4.54E-07 2006.201.22:46:40.20:scan_name=201-2250,jd0607,90 2006.201.22:46:40.20:source=0528+134,053056.42,133155.1,2000.0,cw 2006.201.22:46:41.14#flagr#flagr/antenna,new-source 2006.201.22:46:41.14:checkk5 2006.201.22:46:41.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.22:46:41.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.22:46:42.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.22:46:42.64/chk_autoobs//k5ts4/ autoobs is running! 2006.201.22:46:43.01/chk_obsdata//k5ts1/T2012242??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.22:46:43.37/chk_obsdata//k5ts2/T2012242??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.22:46:43.74/chk_obsdata//k5ts3/T2012242??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.22:46:44.10/chk_obsdata//k5ts4/T2012242??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.22:46:44.81/k5log//k5ts1_log_newline 2006.201.22:46:45.50/k5log//k5ts2_log_newline 2006.201.22:46:46.19/k5log//k5ts3_log_newline 2006.201.22:46:46.87/k5log//k5ts4_log_newline 2006.201.22:46:46.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.22:46:46.90:setupk4=1 2006.201.22:46:46.90$setupk4/echo=on 2006.201.22:46:46.90$setupk4/pcalon 2006.201.22:46:46.90$pcalon/"no phase cal control is implemented here 2006.201.22:46:46.90$setupk4/"tpicd=stop 2006.201.22:46:46.90$setupk4/"rec=synch_on 2006.201.22:46:46.90$setupk4/"rec_mode=128 2006.201.22:46:46.90$setupk4/!* 2006.201.22:46:46.90$setupk4/recpk4 2006.201.22:46:46.90$recpk4/recpatch= 2006.201.22:46:46.90$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.22:46:46.90$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.22:46:46.90$setupk4/vck44 2006.201.22:46:46.90$vck44/valo=1,524.99 2006.201.22:46:46.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.22:46:46.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.22:46:46.90#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:46.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:46.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:46.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:46.90#ibcon#enter wrdev, iclass 10, count 0 2006.201.22:46:46.90#ibcon#first serial, iclass 10, count 0 2006.201.22:46:46.90#ibcon#enter sib2, iclass 10, count 0 2006.201.22:46:46.90#ibcon#flushed, iclass 10, count 0 2006.201.22:46:46.90#ibcon#about to write, iclass 10, count 0 2006.201.22:46:46.90#ibcon#wrote, iclass 10, count 0 2006.201.22:46:46.90#ibcon#about to read 3, iclass 10, count 0 2006.201.22:46:46.94#ibcon#read 3, iclass 10, count 0 2006.201.22:46:46.94#ibcon#about to read 4, iclass 10, count 0 2006.201.22:46:46.94#ibcon#read 4, iclass 10, count 0 2006.201.22:46:46.94#ibcon#about to read 5, iclass 10, count 0 2006.201.22:46:46.94#ibcon#read 5, iclass 10, count 0 2006.201.22:46:46.94#ibcon#about to read 6, iclass 10, count 0 2006.201.22:46:46.94#ibcon#read 6, iclass 10, count 0 2006.201.22:46:46.94#ibcon#end of sib2, iclass 10, count 0 2006.201.22:46:46.94#ibcon#*mode == 0, iclass 10, count 0 2006.201.22:46:46.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.22:46:46.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.22:46:46.94#ibcon#*before write, iclass 10, count 0 2006.201.22:46:46.94#ibcon#enter sib2, iclass 10, count 0 2006.201.22:46:46.94#ibcon#flushed, iclass 10, count 0 2006.201.22:46:46.94#ibcon#about to write, iclass 10, count 0 2006.201.22:46:46.94#ibcon#wrote, iclass 10, count 0 2006.201.22:46:46.94#ibcon#about to read 3, iclass 10, count 0 2006.201.22:46:46.99#ibcon#read 3, iclass 10, count 0 2006.201.22:46:46.99#ibcon#about to read 4, iclass 10, count 0 2006.201.22:46:46.99#ibcon#read 4, iclass 10, count 0 2006.201.22:46:46.99#ibcon#about to read 5, iclass 10, count 0 2006.201.22:46:46.99#ibcon#read 5, iclass 10, count 0 2006.201.22:46:46.99#ibcon#about to read 6, iclass 10, count 0 2006.201.22:46:46.99#ibcon#read 6, iclass 10, count 0 2006.201.22:46:46.99#ibcon#end of sib2, iclass 10, count 0 2006.201.22:46:46.99#ibcon#*after write, iclass 10, count 0 2006.201.22:46:46.99#ibcon#*before return 0, iclass 10, count 0 2006.201.22:46:46.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:46.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:46.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.22:46:46.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.22:46:46.99$vck44/va=1,8 2006.201.22:46:46.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.22:46:46.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.22:46:46.99#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:46.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:46.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:46.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:46.99#ibcon#enter wrdev, iclass 12, count 2 2006.201.22:46:46.99#ibcon#first serial, iclass 12, count 2 2006.201.22:46:46.99#ibcon#enter sib2, iclass 12, count 2 2006.201.22:46:46.99#ibcon#flushed, iclass 12, count 2 2006.201.22:46:46.99#ibcon#about to write, iclass 12, count 2 2006.201.22:46:46.99#ibcon#wrote, iclass 12, count 2 2006.201.22:46:46.99#ibcon#about to read 3, iclass 12, count 2 2006.201.22:46:47.01#ibcon#read 3, iclass 12, count 2 2006.201.22:46:47.01#ibcon#about to read 4, iclass 12, count 2 2006.201.22:46:47.01#ibcon#read 4, iclass 12, count 2 2006.201.22:46:47.01#ibcon#about to read 5, iclass 12, count 2 2006.201.22:46:47.01#ibcon#read 5, iclass 12, count 2 2006.201.22:46:47.01#ibcon#about to read 6, iclass 12, count 2 2006.201.22:46:47.01#ibcon#read 6, iclass 12, count 2 2006.201.22:46:47.01#ibcon#end of sib2, iclass 12, count 2 2006.201.22:46:47.01#ibcon#*mode == 0, iclass 12, count 2 2006.201.22:46:47.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.22:46:47.01#ibcon#[25=AT01-08\r\n] 2006.201.22:46:47.01#ibcon#*before write, iclass 12, count 2 2006.201.22:46:47.01#ibcon#enter sib2, iclass 12, count 2 2006.201.22:46:47.01#ibcon#flushed, iclass 12, count 2 2006.201.22:46:47.01#ibcon#about to write, iclass 12, count 2 2006.201.22:46:47.01#ibcon#wrote, iclass 12, count 2 2006.201.22:46:47.01#ibcon#about to read 3, iclass 12, count 2 2006.201.22:46:47.04#ibcon#read 3, iclass 12, count 2 2006.201.22:46:47.04#ibcon#about to read 4, iclass 12, count 2 2006.201.22:46:47.04#ibcon#read 4, iclass 12, count 2 2006.201.22:46:47.04#ibcon#about to read 5, iclass 12, count 2 2006.201.22:46:47.04#ibcon#read 5, iclass 12, count 2 2006.201.22:46:47.04#ibcon#about to read 6, iclass 12, count 2 2006.201.22:46:47.04#ibcon#read 6, iclass 12, count 2 2006.201.22:46:47.04#ibcon#end of sib2, iclass 12, count 2 2006.201.22:46:47.04#ibcon#*after write, iclass 12, count 2 2006.201.22:46:47.04#ibcon#*before return 0, iclass 12, count 2 2006.201.22:46:47.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:47.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:47.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.22:46:47.04#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:47.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:47.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:47.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:47.16#ibcon#enter wrdev, iclass 12, count 0 2006.201.22:46:47.16#ibcon#first serial, iclass 12, count 0 2006.201.22:46:47.16#ibcon#enter sib2, iclass 12, count 0 2006.201.22:46:47.16#ibcon#flushed, iclass 12, count 0 2006.201.22:46:47.16#ibcon#about to write, iclass 12, count 0 2006.201.22:46:47.16#ibcon#wrote, iclass 12, count 0 2006.201.22:46:47.16#ibcon#about to read 3, iclass 12, count 0 2006.201.22:46:47.18#ibcon#read 3, iclass 12, count 0 2006.201.22:46:47.18#ibcon#about to read 4, iclass 12, count 0 2006.201.22:46:47.18#ibcon#read 4, iclass 12, count 0 2006.201.22:46:47.18#ibcon#about to read 5, iclass 12, count 0 2006.201.22:46:47.18#ibcon#read 5, iclass 12, count 0 2006.201.22:46:47.18#ibcon#about to read 6, iclass 12, count 0 2006.201.22:46:47.18#ibcon#read 6, iclass 12, count 0 2006.201.22:46:47.18#ibcon#end of sib2, iclass 12, count 0 2006.201.22:46:47.18#ibcon#*mode == 0, iclass 12, count 0 2006.201.22:46:47.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.22:46:47.18#ibcon#[25=USB\r\n] 2006.201.22:46:47.18#ibcon#*before write, iclass 12, count 0 2006.201.22:46:47.18#ibcon#enter sib2, iclass 12, count 0 2006.201.22:46:47.18#ibcon#flushed, iclass 12, count 0 2006.201.22:46:47.18#ibcon#about to write, iclass 12, count 0 2006.201.22:46:47.18#ibcon#wrote, iclass 12, count 0 2006.201.22:46:47.18#ibcon#about to read 3, iclass 12, count 0 2006.201.22:46:47.21#ibcon#read 3, iclass 12, count 0 2006.201.22:46:47.21#ibcon#about to read 4, iclass 12, count 0 2006.201.22:46:47.21#ibcon#read 4, iclass 12, count 0 2006.201.22:46:47.21#ibcon#about to read 5, iclass 12, count 0 2006.201.22:46:47.21#ibcon#read 5, iclass 12, count 0 2006.201.22:46:47.21#ibcon#about to read 6, iclass 12, count 0 2006.201.22:46:47.21#ibcon#read 6, iclass 12, count 0 2006.201.22:46:47.21#ibcon#end of sib2, iclass 12, count 0 2006.201.22:46:47.21#ibcon#*after write, iclass 12, count 0 2006.201.22:46:47.21#ibcon#*before return 0, iclass 12, count 0 2006.201.22:46:47.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:47.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:47.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.22:46:47.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.22:46:47.21$vck44/valo=2,534.99 2006.201.22:46:47.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.22:46:47.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.22:46:47.21#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:47.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:47.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:47.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:47.21#ibcon#enter wrdev, iclass 14, count 0 2006.201.22:46:47.21#ibcon#first serial, iclass 14, count 0 2006.201.22:46:47.21#ibcon#enter sib2, iclass 14, count 0 2006.201.22:46:47.21#ibcon#flushed, iclass 14, count 0 2006.201.22:46:47.21#ibcon#about to write, iclass 14, count 0 2006.201.22:46:47.21#ibcon#wrote, iclass 14, count 0 2006.201.22:46:47.21#ibcon#about to read 3, iclass 14, count 0 2006.201.22:46:47.23#ibcon#read 3, iclass 14, count 0 2006.201.22:46:47.23#ibcon#about to read 4, iclass 14, count 0 2006.201.22:46:47.23#ibcon#read 4, iclass 14, count 0 2006.201.22:46:47.23#ibcon#about to read 5, iclass 14, count 0 2006.201.22:46:47.23#ibcon#read 5, iclass 14, count 0 2006.201.22:46:47.23#ibcon#about to read 6, iclass 14, count 0 2006.201.22:46:47.23#ibcon#read 6, iclass 14, count 0 2006.201.22:46:47.23#ibcon#end of sib2, iclass 14, count 0 2006.201.22:46:47.23#ibcon#*mode == 0, iclass 14, count 0 2006.201.22:46:47.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.22:46:47.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.22:46:47.23#ibcon#*before write, iclass 14, count 0 2006.201.22:46:47.23#ibcon#enter sib2, iclass 14, count 0 2006.201.22:46:47.23#ibcon#flushed, iclass 14, count 0 2006.201.22:46:47.23#ibcon#about to write, iclass 14, count 0 2006.201.22:46:47.23#ibcon#wrote, iclass 14, count 0 2006.201.22:46:47.23#ibcon#about to read 3, iclass 14, count 0 2006.201.22:46:47.27#ibcon#read 3, iclass 14, count 0 2006.201.22:46:47.27#ibcon#about to read 4, iclass 14, count 0 2006.201.22:46:47.27#ibcon#read 4, iclass 14, count 0 2006.201.22:46:47.27#ibcon#about to read 5, iclass 14, count 0 2006.201.22:46:47.27#ibcon#read 5, iclass 14, count 0 2006.201.22:46:47.27#ibcon#about to read 6, iclass 14, count 0 2006.201.22:46:47.27#ibcon#read 6, iclass 14, count 0 2006.201.22:46:47.27#ibcon#end of sib2, iclass 14, count 0 2006.201.22:46:47.27#ibcon#*after write, iclass 14, count 0 2006.201.22:46:47.27#ibcon#*before return 0, iclass 14, count 0 2006.201.22:46:47.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:47.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:47.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.22:46:47.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.22:46:47.27$vck44/va=2,7 2006.201.22:46:47.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.22:46:47.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.22:46:47.27#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:47.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:47.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:47.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:47.33#ibcon#enter wrdev, iclass 16, count 2 2006.201.22:46:47.33#ibcon#first serial, iclass 16, count 2 2006.201.22:46:47.33#ibcon#enter sib2, iclass 16, count 2 2006.201.22:46:47.33#ibcon#flushed, iclass 16, count 2 2006.201.22:46:47.33#ibcon#about to write, iclass 16, count 2 2006.201.22:46:47.33#ibcon#wrote, iclass 16, count 2 2006.201.22:46:47.33#ibcon#about to read 3, iclass 16, count 2 2006.201.22:46:47.35#ibcon#read 3, iclass 16, count 2 2006.201.22:46:47.35#ibcon#about to read 4, iclass 16, count 2 2006.201.22:46:47.35#ibcon#read 4, iclass 16, count 2 2006.201.22:46:47.35#ibcon#about to read 5, iclass 16, count 2 2006.201.22:46:47.35#ibcon#read 5, iclass 16, count 2 2006.201.22:46:47.35#ibcon#about to read 6, iclass 16, count 2 2006.201.22:46:47.35#ibcon#read 6, iclass 16, count 2 2006.201.22:46:47.35#ibcon#end of sib2, iclass 16, count 2 2006.201.22:46:47.35#ibcon#*mode == 0, iclass 16, count 2 2006.201.22:46:47.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.22:46:47.35#ibcon#[25=AT02-07\r\n] 2006.201.22:46:47.35#ibcon#*before write, iclass 16, count 2 2006.201.22:46:47.35#ibcon#enter sib2, iclass 16, count 2 2006.201.22:46:47.35#ibcon#flushed, iclass 16, count 2 2006.201.22:46:47.35#ibcon#about to write, iclass 16, count 2 2006.201.22:46:47.35#ibcon#wrote, iclass 16, count 2 2006.201.22:46:47.35#ibcon#about to read 3, iclass 16, count 2 2006.201.22:46:47.38#ibcon#read 3, iclass 16, count 2 2006.201.22:46:47.38#ibcon#about to read 4, iclass 16, count 2 2006.201.22:46:47.38#ibcon#read 4, iclass 16, count 2 2006.201.22:46:47.38#ibcon#about to read 5, iclass 16, count 2 2006.201.22:46:47.38#ibcon#read 5, iclass 16, count 2 2006.201.22:46:47.38#ibcon#about to read 6, iclass 16, count 2 2006.201.22:46:47.38#ibcon#read 6, iclass 16, count 2 2006.201.22:46:47.38#ibcon#end of sib2, iclass 16, count 2 2006.201.22:46:47.38#ibcon#*after write, iclass 16, count 2 2006.201.22:46:47.38#ibcon#*before return 0, iclass 16, count 2 2006.201.22:46:47.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:47.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:47.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.22:46:47.38#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:47.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:47.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:47.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:47.50#ibcon#enter wrdev, iclass 16, count 0 2006.201.22:46:47.50#ibcon#first serial, iclass 16, count 0 2006.201.22:46:47.50#ibcon#enter sib2, iclass 16, count 0 2006.201.22:46:47.50#ibcon#flushed, iclass 16, count 0 2006.201.22:46:47.50#ibcon#about to write, iclass 16, count 0 2006.201.22:46:47.50#ibcon#wrote, iclass 16, count 0 2006.201.22:46:47.50#ibcon#about to read 3, iclass 16, count 0 2006.201.22:46:47.52#ibcon#read 3, iclass 16, count 0 2006.201.22:46:47.52#ibcon#about to read 4, iclass 16, count 0 2006.201.22:46:47.52#ibcon#read 4, iclass 16, count 0 2006.201.22:46:47.52#ibcon#about to read 5, iclass 16, count 0 2006.201.22:46:47.52#ibcon#read 5, iclass 16, count 0 2006.201.22:46:47.52#ibcon#about to read 6, iclass 16, count 0 2006.201.22:46:47.52#ibcon#read 6, iclass 16, count 0 2006.201.22:46:47.52#ibcon#end of sib2, iclass 16, count 0 2006.201.22:46:47.52#ibcon#*mode == 0, iclass 16, count 0 2006.201.22:46:47.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.22:46:47.52#ibcon#[25=USB\r\n] 2006.201.22:46:47.52#ibcon#*before write, iclass 16, count 0 2006.201.22:46:47.52#ibcon#enter sib2, iclass 16, count 0 2006.201.22:46:47.52#ibcon#flushed, iclass 16, count 0 2006.201.22:46:47.52#ibcon#about to write, iclass 16, count 0 2006.201.22:46:47.52#ibcon#wrote, iclass 16, count 0 2006.201.22:46:47.52#ibcon#about to read 3, iclass 16, count 0 2006.201.22:46:47.55#ibcon#read 3, iclass 16, count 0 2006.201.22:46:47.55#ibcon#about to read 4, iclass 16, count 0 2006.201.22:46:47.55#ibcon#read 4, iclass 16, count 0 2006.201.22:46:47.55#ibcon#about to read 5, iclass 16, count 0 2006.201.22:46:47.55#ibcon#read 5, iclass 16, count 0 2006.201.22:46:47.55#ibcon#about to read 6, iclass 16, count 0 2006.201.22:46:47.55#ibcon#read 6, iclass 16, count 0 2006.201.22:46:47.55#ibcon#end of sib2, iclass 16, count 0 2006.201.22:46:47.55#ibcon#*after write, iclass 16, count 0 2006.201.22:46:47.55#ibcon#*before return 0, iclass 16, count 0 2006.201.22:46:47.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:47.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:47.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.22:46:47.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.22:46:47.55$vck44/valo=3,564.99 2006.201.22:46:47.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.22:46:47.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.22:46:47.55#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:47.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:47.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:47.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:47.55#ibcon#enter wrdev, iclass 18, count 0 2006.201.22:46:47.55#ibcon#first serial, iclass 18, count 0 2006.201.22:46:47.55#ibcon#enter sib2, iclass 18, count 0 2006.201.22:46:47.55#ibcon#flushed, iclass 18, count 0 2006.201.22:46:47.55#ibcon#about to write, iclass 18, count 0 2006.201.22:46:47.55#ibcon#wrote, iclass 18, count 0 2006.201.22:46:47.55#ibcon#about to read 3, iclass 18, count 0 2006.201.22:46:47.57#ibcon#read 3, iclass 18, count 0 2006.201.22:46:47.57#ibcon#about to read 4, iclass 18, count 0 2006.201.22:46:47.57#ibcon#read 4, iclass 18, count 0 2006.201.22:46:47.57#ibcon#about to read 5, iclass 18, count 0 2006.201.22:46:47.57#ibcon#read 5, iclass 18, count 0 2006.201.22:46:47.57#ibcon#about to read 6, iclass 18, count 0 2006.201.22:46:47.57#ibcon#read 6, iclass 18, count 0 2006.201.22:46:47.57#ibcon#end of sib2, iclass 18, count 0 2006.201.22:46:47.57#ibcon#*mode == 0, iclass 18, count 0 2006.201.22:46:47.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.22:46:47.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.22:46:47.57#ibcon#*before write, iclass 18, count 0 2006.201.22:46:47.57#ibcon#enter sib2, iclass 18, count 0 2006.201.22:46:47.57#ibcon#flushed, iclass 18, count 0 2006.201.22:46:47.57#ibcon#about to write, iclass 18, count 0 2006.201.22:46:47.57#ibcon#wrote, iclass 18, count 0 2006.201.22:46:47.57#ibcon#about to read 3, iclass 18, count 0 2006.201.22:46:47.62#ibcon#read 3, iclass 18, count 0 2006.201.22:46:47.62#ibcon#about to read 4, iclass 18, count 0 2006.201.22:46:47.62#ibcon#read 4, iclass 18, count 0 2006.201.22:46:47.62#ibcon#about to read 5, iclass 18, count 0 2006.201.22:46:47.62#ibcon#read 5, iclass 18, count 0 2006.201.22:46:47.62#ibcon#about to read 6, iclass 18, count 0 2006.201.22:46:47.62#ibcon#read 6, iclass 18, count 0 2006.201.22:46:47.62#ibcon#end of sib2, iclass 18, count 0 2006.201.22:46:47.62#ibcon#*after write, iclass 18, count 0 2006.201.22:46:47.62#ibcon#*before return 0, iclass 18, count 0 2006.201.22:46:47.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:47.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:47.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.22:46:47.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.22:46:47.62$vck44/va=3,8 2006.201.22:46:47.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.22:46:47.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.22:46:47.62#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:47.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:47.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:47.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:47.67#ibcon#enter wrdev, iclass 20, count 2 2006.201.22:46:47.67#ibcon#first serial, iclass 20, count 2 2006.201.22:46:47.67#ibcon#enter sib2, iclass 20, count 2 2006.201.22:46:47.67#ibcon#flushed, iclass 20, count 2 2006.201.22:46:47.67#ibcon#about to write, iclass 20, count 2 2006.201.22:46:47.67#ibcon#wrote, iclass 20, count 2 2006.201.22:46:47.67#ibcon#about to read 3, iclass 20, count 2 2006.201.22:46:47.69#ibcon#read 3, iclass 20, count 2 2006.201.22:46:47.69#ibcon#about to read 4, iclass 20, count 2 2006.201.22:46:47.69#ibcon#read 4, iclass 20, count 2 2006.201.22:46:47.69#ibcon#about to read 5, iclass 20, count 2 2006.201.22:46:47.69#ibcon#read 5, iclass 20, count 2 2006.201.22:46:47.69#ibcon#about to read 6, iclass 20, count 2 2006.201.22:46:47.69#ibcon#read 6, iclass 20, count 2 2006.201.22:46:47.69#ibcon#end of sib2, iclass 20, count 2 2006.201.22:46:47.69#ibcon#*mode == 0, iclass 20, count 2 2006.201.22:46:47.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.22:46:47.69#ibcon#[25=AT03-08\r\n] 2006.201.22:46:47.69#ibcon#*before write, iclass 20, count 2 2006.201.22:46:47.69#ibcon#enter sib2, iclass 20, count 2 2006.201.22:46:47.69#ibcon#flushed, iclass 20, count 2 2006.201.22:46:47.69#ibcon#about to write, iclass 20, count 2 2006.201.22:46:47.69#ibcon#wrote, iclass 20, count 2 2006.201.22:46:47.69#ibcon#about to read 3, iclass 20, count 2 2006.201.22:46:47.72#ibcon#read 3, iclass 20, count 2 2006.201.22:46:47.72#ibcon#about to read 4, iclass 20, count 2 2006.201.22:46:47.72#ibcon#read 4, iclass 20, count 2 2006.201.22:46:47.72#ibcon#about to read 5, iclass 20, count 2 2006.201.22:46:47.72#ibcon#read 5, iclass 20, count 2 2006.201.22:46:47.72#ibcon#about to read 6, iclass 20, count 2 2006.201.22:46:47.72#ibcon#read 6, iclass 20, count 2 2006.201.22:46:47.72#ibcon#end of sib2, iclass 20, count 2 2006.201.22:46:47.72#ibcon#*after write, iclass 20, count 2 2006.201.22:46:47.72#ibcon#*before return 0, iclass 20, count 2 2006.201.22:46:47.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:47.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:47.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.22:46:47.72#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:47.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:47.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:47.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:47.84#ibcon#enter wrdev, iclass 20, count 0 2006.201.22:46:47.84#ibcon#first serial, iclass 20, count 0 2006.201.22:46:47.84#ibcon#enter sib2, iclass 20, count 0 2006.201.22:46:47.84#ibcon#flushed, iclass 20, count 0 2006.201.22:46:47.84#ibcon#about to write, iclass 20, count 0 2006.201.22:46:47.84#ibcon#wrote, iclass 20, count 0 2006.201.22:46:47.84#ibcon#about to read 3, iclass 20, count 0 2006.201.22:46:47.86#ibcon#read 3, iclass 20, count 0 2006.201.22:46:47.86#ibcon#about to read 4, iclass 20, count 0 2006.201.22:46:47.86#ibcon#read 4, iclass 20, count 0 2006.201.22:46:47.86#ibcon#about to read 5, iclass 20, count 0 2006.201.22:46:47.86#ibcon#read 5, iclass 20, count 0 2006.201.22:46:47.86#ibcon#about to read 6, iclass 20, count 0 2006.201.22:46:47.86#ibcon#read 6, iclass 20, count 0 2006.201.22:46:47.86#ibcon#end of sib2, iclass 20, count 0 2006.201.22:46:47.86#ibcon#*mode == 0, iclass 20, count 0 2006.201.22:46:47.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.22:46:47.86#ibcon#[25=USB\r\n] 2006.201.22:46:47.86#ibcon#*before write, iclass 20, count 0 2006.201.22:46:47.86#ibcon#enter sib2, iclass 20, count 0 2006.201.22:46:47.86#ibcon#flushed, iclass 20, count 0 2006.201.22:46:47.86#ibcon#about to write, iclass 20, count 0 2006.201.22:46:47.86#ibcon#wrote, iclass 20, count 0 2006.201.22:46:47.86#ibcon#about to read 3, iclass 20, count 0 2006.201.22:46:47.89#ibcon#read 3, iclass 20, count 0 2006.201.22:46:47.89#ibcon#about to read 4, iclass 20, count 0 2006.201.22:46:47.89#ibcon#read 4, iclass 20, count 0 2006.201.22:46:47.89#ibcon#about to read 5, iclass 20, count 0 2006.201.22:46:47.89#ibcon#read 5, iclass 20, count 0 2006.201.22:46:47.89#ibcon#about to read 6, iclass 20, count 0 2006.201.22:46:47.89#ibcon#read 6, iclass 20, count 0 2006.201.22:46:47.89#ibcon#end of sib2, iclass 20, count 0 2006.201.22:46:47.89#ibcon#*after write, iclass 20, count 0 2006.201.22:46:47.89#ibcon#*before return 0, iclass 20, count 0 2006.201.22:46:47.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:47.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:47.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.22:46:47.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.22:46:47.89$vck44/valo=4,624.99 2006.201.22:46:47.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.22:46:47.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.22:46:47.89#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:47.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:47.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:47.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:47.89#ibcon#enter wrdev, iclass 22, count 0 2006.201.22:46:47.89#ibcon#first serial, iclass 22, count 0 2006.201.22:46:47.89#ibcon#enter sib2, iclass 22, count 0 2006.201.22:46:47.89#ibcon#flushed, iclass 22, count 0 2006.201.22:46:47.89#ibcon#about to write, iclass 22, count 0 2006.201.22:46:47.89#ibcon#wrote, iclass 22, count 0 2006.201.22:46:47.89#ibcon#about to read 3, iclass 22, count 0 2006.201.22:46:47.91#ibcon#read 3, iclass 22, count 0 2006.201.22:46:47.91#ibcon#about to read 4, iclass 22, count 0 2006.201.22:46:47.91#ibcon#read 4, iclass 22, count 0 2006.201.22:46:47.91#ibcon#about to read 5, iclass 22, count 0 2006.201.22:46:47.91#ibcon#read 5, iclass 22, count 0 2006.201.22:46:47.91#ibcon#about to read 6, iclass 22, count 0 2006.201.22:46:47.91#ibcon#read 6, iclass 22, count 0 2006.201.22:46:47.91#ibcon#end of sib2, iclass 22, count 0 2006.201.22:46:47.91#ibcon#*mode == 0, iclass 22, count 0 2006.201.22:46:47.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.22:46:47.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.22:46:47.91#ibcon#*before write, iclass 22, count 0 2006.201.22:46:47.91#ibcon#enter sib2, iclass 22, count 0 2006.201.22:46:47.91#ibcon#flushed, iclass 22, count 0 2006.201.22:46:47.91#ibcon#about to write, iclass 22, count 0 2006.201.22:46:47.91#ibcon#wrote, iclass 22, count 0 2006.201.22:46:47.91#ibcon#about to read 3, iclass 22, count 0 2006.201.22:46:47.96#ibcon#read 3, iclass 22, count 0 2006.201.22:46:47.96#ibcon#about to read 4, iclass 22, count 0 2006.201.22:46:47.96#ibcon#read 4, iclass 22, count 0 2006.201.22:46:47.96#ibcon#about to read 5, iclass 22, count 0 2006.201.22:46:47.96#ibcon#read 5, iclass 22, count 0 2006.201.22:46:47.96#ibcon#about to read 6, iclass 22, count 0 2006.201.22:46:47.96#ibcon#read 6, iclass 22, count 0 2006.201.22:46:47.96#ibcon#end of sib2, iclass 22, count 0 2006.201.22:46:47.96#ibcon#*after write, iclass 22, count 0 2006.201.22:46:47.96#ibcon#*before return 0, iclass 22, count 0 2006.201.22:46:47.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:47.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:47.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.22:46:47.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.22:46:47.96$vck44/va=4,7 2006.201.22:46:47.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.22:46:47.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.22:46:47.96#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:47.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:48.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:48.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:48.01#ibcon#enter wrdev, iclass 24, count 2 2006.201.22:46:48.01#ibcon#first serial, iclass 24, count 2 2006.201.22:46:48.01#ibcon#enter sib2, iclass 24, count 2 2006.201.22:46:48.01#ibcon#flushed, iclass 24, count 2 2006.201.22:46:48.01#ibcon#about to write, iclass 24, count 2 2006.201.22:46:48.01#ibcon#wrote, iclass 24, count 2 2006.201.22:46:48.01#ibcon#about to read 3, iclass 24, count 2 2006.201.22:46:48.03#ibcon#read 3, iclass 24, count 2 2006.201.22:46:48.03#ibcon#about to read 4, iclass 24, count 2 2006.201.22:46:48.03#ibcon#read 4, iclass 24, count 2 2006.201.22:46:48.03#ibcon#about to read 5, iclass 24, count 2 2006.201.22:46:48.03#ibcon#read 5, iclass 24, count 2 2006.201.22:46:48.03#ibcon#about to read 6, iclass 24, count 2 2006.201.22:46:48.03#ibcon#read 6, iclass 24, count 2 2006.201.22:46:48.03#ibcon#end of sib2, iclass 24, count 2 2006.201.22:46:48.03#ibcon#*mode == 0, iclass 24, count 2 2006.201.22:46:48.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.22:46:48.03#ibcon#[25=AT04-07\r\n] 2006.201.22:46:48.03#ibcon#*before write, iclass 24, count 2 2006.201.22:46:48.03#ibcon#enter sib2, iclass 24, count 2 2006.201.22:46:48.03#ibcon#flushed, iclass 24, count 2 2006.201.22:46:48.03#ibcon#about to write, iclass 24, count 2 2006.201.22:46:48.03#ibcon#wrote, iclass 24, count 2 2006.201.22:46:48.03#ibcon#about to read 3, iclass 24, count 2 2006.201.22:46:48.06#ibcon#read 3, iclass 24, count 2 2006.201.22:46:48.06#ibcon#about to read 4, iclass 24, count 2 2006.201.22:46:48.06#ibcon#read 4, iclass 24, count 2 2006.201.22:46:48.06#ibcon#about to read 5, iclass 24, count 2 2006.201.22:46:48.06#ibcon#read 5, iclass 24, count 2 2006.201.22:46:48.06#ibcon#about to read 6, iclass 24, count 2 2006.201.22:46:48.06#ibcon#read 6, iclass 24, count 2 2006.201.22:46:48.06#ibcon#end of sib2, iclass 24, count 2 2006.201.22:46:48.06#ibcon#*after write, iclass 24, count 2 2006.201.22:46:48.06#ibcon#*before return 0, iclass 24, count 2 2006.201.22:46:48.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:48.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:48.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.22:46:48.06#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:48.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:48.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:48.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:48.18#ibcon#enter wrdev, iclass 24, count 0 2006.201.22:46:48.18#ibcon#first serial, iclass 24, count 0 2006.201.22:46:48.18#ibcon#enter sib2, iclass 24, count 0 2006.201.22:46:48.18#ibcon#flushed, iclass 24, count 0 2006.201.22:46:48.18#ibcon#about to write, iclass 24, count 0 2006.201.22:46:48.18#ibcon#wrote, iclass 24, count 0 2006.201.22:46:48.18#ibcon#about to read 3, iclass 24, count 0 2006.201.22:46:48.20#ibcon#read 3, iclass 24, count 0 2006.201.22:46:48.20#ibcon#about to read 4, iclass 24, count 0 2006.201.22:46:48.20#ibcon#read 4, iclass 24, count 0 2006.201.22:46:48.20#ibcon#about to read 5, iclass 24, count 0 2006.201.22:46:48.20#ibcon#read 5, iclass 24, count 0 2006.201.22:46:48.20#ibcon#about to read 6, iclass 24, count 0 2006.201.22:46:48.20#ibcon#read 6, iclass 24, count 0 2006.201.22:46:48.20#ibcon#end of sib2, iclass 24, count 0 2006.201.22:46:48.20#ibcon#*mode == 0, iclass 24, count 0 2006.201.22:46:48.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.22:46:48.20#ibcon#[25=USB\r\n] 2006.201.22:46:48.20#ibcon#*before write, iclass 24, count 0 2006.201.22:46:48.20#ibcon#enter sib2, iclass 24, count 0 2006.201.22:46:48.20#ibcon#flushed, iclass 24, count 0 2006.201.22:46:48.20#ibcon#about to write, iclass 24, count 0 2006.201.22:46:48.20#ibcon#wrote, iclass 24, count 0 2006.201.22:46:48.20#ibcon#about to read 3, iclass 24, count 0 2006.201.22:46:48.23#ibcon#read 3, iclass 24, count 0 2006.201.22:46:48.23#ibcon#about to read 4, iclass 24, count 0 2006.201.22:46:48.23#ibcon#read 4, iclass 24, count 0 2006.201.22:46:48.23#ibcon#about to read 5, iclass 24, count 0 2006.201.22:46:48.23#ibcon#read 5, iclass 24, count 0 2006.201.22:46:48.23#ibcon#about to read 6, iclass 24, count 0 2006.201.22:46:48.23#ibcon#read 6, iclass 24, count 0 2006.201.22:46:48.23#ibcon#end of sib2, iclass 24, count 0 2006.201.22:46:48.23#ibcon#*after write, iclass 24, count 0 2006.201.22:46:48.23#ibcon#*before return 0, iclass 24, count 0 2006.201.22:46:48.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:48.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:48.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.22:46:48.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.22:46:48.23$vck44/valo=5,734.99 2006.201.22:46:48.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.22:46:48.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.22:46:48.23#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:48.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:48.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:48.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:48.23#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:46:48.23#ibcon#first serial, iclass 26, count 0 2006.201.22:46:48.23#ibcon#enter sib2, iclass 26, count 0 2006.201.22:46:48.23#ibcon#flushed, iclass 26, count 0 2006.201.22:46:48.23#ibcon#about to write, iclass 26, count 0 2006.201.22:46:48.23#ibcon#wrote, iclass 26, count 0 2006.201.22:46:48.23#ibcon#about to read 3, iclass 26, count 0 2006.201.22:46:48.25#ibcon#read 3, iclass 26, count 0 2006.201.22:46:48.25#ibcon#about to read 4, iclass 26, count 0 2006.201.22:46:48.25#ibcon#read 4, iclass 26, count 0 2006.201.22:46:48.25#ibcon#about to read 5, iclass 26, count 0 2006.201.22:46:48.25#ibcon#read 5, iclass 26, count 0 2006.201.22:46:48.25#ibcon#about to read 6, iclass 26, count 0 2006.201.22:46:48.25#ibcon#read 6, iclass 26, count 0 2006.201.22:46:48.25#ibcon#end of sib2, iclass 26, count 0 2006.201.22:46:48.25#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:46:48.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:46:48.25#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.22:46:48.25#ibcon#*before write, iclass 26, count 0 2006.201.22:46:48.25#ibcon#enter sib2, iclass 26, count 0 2006.201.22:46:48.25#ibcon#flushed, iclass 26, count 0 2006.201.22:46:48.25#ibcon#about to write, iclass 26, count 0 2006.201.22:46:48.25#ibcon#wrote, iclass 26, count 0 2006.201.22:46:48.25#ibcon#about to read 3, iclass 26, count 0 2006.201.22:46:48.29#ibcon#read 3, iclass 26, count 0 2006.201.22:46:48.29#ibcon#about to read 4, iclass 26, count 0 2006.201.22:46:48.29#ibcon#read 4, iclass 26, count 0 2006.201.22:46:48.29#ibcon#about to read 5, iclass 26, count 0 2006.201.22:46:48.29#ibcon#read 5, iclass 26, count 0 2006.201.22:46:48.29#ibcon#about to read 6, iclass 26, count 0 2006.201.22:46:48.29#ibcon#read 6, iclass 26, count 0 2006.201.22:46:48.29#ibcon#end of sib2, iclass 26, count 0 2006.201.22:46:48.29#ibcon#*after write, iclass 26, count 0 2006.201.22:46:48.29#ibcon#*before return 0, iclass 26, count 0 2006.201.22:46:48.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:48.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:48.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:46:48.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:46:48.29$vck44/va=5,4 2006.201.22:46:48.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.22:46:48.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.22:46:48.29#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:48.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:48.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:48.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:48.35#ibcon#enter wrdev, iclass 28, count 2 2006.201.22:46:48.35#ibcon#first serial, iclass 28, count 2 2006.201.22:46:48.35#ibcon#enter sib2, iclass 28, count 2 2006.201.22:46:48.35#ibcon#flushed, iclass 28, count 2 2006.201.22:46:48.35#ibcon#about to write, iclass 28, count 2 2006.201.22:46:48.35#ibcon#wrote, iclass 28, count 2 2006.201.22:46:48.35#ibcon#about to read 3, iclass 28, count 2 2006.201.22:46:48.37#ibcon#read 3, iclass 28, count 2 2006.201.22:46:48.37#ibcon#about to read 4, iclass 28, count 2 2006.201.22:46:48.37#ibcon#read 4, iclass 28, count 2 2006.201.22:46:48.37#ibcon#about to read 5, iclass 28, count 2 2006.201.22:46:48.37#ibcon#read 5, iclass 28, count 2 2006.201.22:46:48.37#ibcon#about to read 6, iclass 28, count 2 2006.201.22:46:48.37#ibcon#read 6, iclass 28, count 2 2006.201.22:46:48.37#ibcon#end of sib2, iclass 28, count 2 2006.201.22:46:48.37#ibcon#*mode == 0, iclass 28, count 2 2006.201.22:46:48.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.22:46:48.37#ibcon#[25=AT05-04\r\n] 2006.201.22:46:48.37#ibcon#*before write, iclass 28, count 2 2006.201.22:46:48.37#ibcon#enter sib2, iclass 28, count 2 2006.201.22:46:48.37#ibcon#flushed, iclass 28, count 2 2006.201.22:46:48.37#ibcon#about to write, iclass 28, count 2 2006.201.22:46:48.37#ibcon#wrote, iclass 28, count 2 2006.201.22:46:48.37#ibcon#about to read 3, iclass 28, count 2 2006.201.22:46:48.40#ibcon#read 3, iclass 28, count 2 2006.201.22:46:48.40#ibcon#about to read 4, iclass 28, count 2 2006.201.22:46:48.40#ibcon#read 4, iclass 28, count 2 2006.201.22:46:48.40#ibcon#about to read 5, iclass 28, count 2 2006.201.22:46:48.40#ibcon#read 5, iclass 28, count 2 2006.201.22:46:48.40#ibcon#about to read 6, iclass 28, count 2 2006.201.22:46:48.40#ibcon#read 6, iclass 28, count 2 2006.201.22:46:48.40#ibcon#end of sib2, iclass 28, count 2 2006.201.22:46:48.40#ibcon#*after write, iclass 28, count 2 2006.201.22:46:48.40#ibcon#*before return 0, iclass 28, count 2 2006.201.22:46:48.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:48.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:48.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.22:46:48.40#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:48.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:48.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:48.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:48.52#ibcon#enter wrdev, iclass 28, count 0 2006.201.22:46:48.52#ibcon#first serial, iclass 28, count 0 2006.201.22:46:48.52#ibcon#enter sib2, iclass 28, count 0 2006.201.22:46:48.52#ibcon#flushed, iclass 28, count 0 2006.201.22:46:48.52#ibcon#about to write, iclass 28, count 0 2006.201.22:46:48.52#ibcon#wrote, iclass 28, count 0 2006.201.22:46:48.52#ibcon#about to read 3, iclass 28, count 0 2006.201.22:46:48.54#ibcon#read 3, iclass 28, count 0 2006.201.22:46:48.54#ibcon#about to read 4, iclass 28, count 0 2006.201.22:46:48.54#ibcon#read 4, iclass 28, count 0 2006.201.22:46:48.54#ibcon#about to read 5, iclass 28, count 0 2006.201.22:46:48.54#ibcon#read 5, iclass 28, count 0 2006.201.22:46:48.54#ibcon#about to read 6, iclass 28, count 0 2006.201.22:46:48.54#ibcon#read 6, iclass 28, count 0 2006.201.22:46:48.54#ibcon#end of sib2, iclass 28, count 0 2006.201.22:46:48.54#ibcon#*mode == 0, iclass 28, count 0 2006.201.22:46:48.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.22:46:48.54#ibcon#[25=USB\r\n] 2006.201.22:46:48.54#ibcon#*before write, iclass 28, count 0 2006.201.22:46:48.54#ibcon#enter sib2, iclass 28, count 0 2006.201.22:46:48.54#ibcon#flushed, iclass 28, count 0 2006.201.22:46:48.54#ibcon#about to write, iclass 28, count 0 2006.201.22:46:48.54#ibcon#wrote, iclass 28, count 0 2006.201.22:46:48.54#ibcon#about to read 3, iclass 28, count 0 2006.201.22:46:48.57#ibcon#read 3, iclass 28, count 0 2006.201.22:46:48.57#ibcon#about to read 4, iclass 28, count 0 2006.201.22:46:48.57#ibcon#read 4, iclass 28, count 0 2006.201.22:46:48.57#ibcon#about to read 5, iclass 28, count 0 2006.201.22:46:48.57#ibcon#read 5, iclass 28, count 0 2006.201.22:46:48.57#ibcon#about to read 6, iclass 28, count 0 2006.201.22:46:48.57#ibcon#read 6, iclass 28, count 0 2006.201.22:46:48.57#ibcon#end of sib2, iclass 28, count 0 2006.201.22:46:48.57#ibcon#*after write, iclass 28, count 0 2006.201.22:46:48.57#ibcon#*before return 0, iclass 28, count 0 2006.201.22:46:48.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:48.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:48.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.22:46:48.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.22:46:48.57$vck44/valo=6,814.99 2006.201.22:46:48.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.22:46:48.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.22:46:48.57#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:48.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:48.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:48.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:48.57#ibcon#enter wrdev, iclass 30, count 0 2006.201.22:46:48.57#ibcon#first serial, iclass 30, count 0 2006.201.22:46:48.57#ibcon#enter sib2, iclass 30, count 0 2006.201.22:46:48.57#ibcon#flushed, iclass 30, count 0 2006.201.22:46:48.57#ibcon#about to write, iclass 30, count 0 2006.201.22:46:48.57#ibcon#wrote, iclass 30, count 0 2006.201.22:46:48.57#ibcon#about to read 3, iclass 30, count 0 2006.201.22:46:48.59#ibcon#read 3, iclass 30, count 0 2006.201.22:46:48.59#ibcon#about to read 4, iclass 30, count 0 2006.201.22:46:48.59#ibcon#read 4, iclass 30, count 0 2006.201.22:46:48.59#ibcon#about to read 5, iclass 30, count 0 2006.201.22:46:48.59#ibcon#read 5, iclass 30, count 0 2006.201.22:46:48.59#ibcon#about to read 6, iclass 30, count 0 2006.201.22:46:48.59#ibcon#read 6, iclass 30, count 0 2006.201.22:46:48.59#ibcon#end of sib2, iclass 30, count 0 2006.201.22:46:48.59#ibcon#*mode == 0, iclass 30, count 0 2006.201.22:46:48.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.22:46:48.59#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.22:46:48.59#ibcon#*before write, iclass 30, count 0 2006.201.22:46:48.59#ibcon#enter sib2, iclass 30, count 0 2006.201.22:46:48.59#ibcon#flushed, iclass 30, count 0 2006.201.22:46:48.59#ibcon#about to write, iclass 30, count 0 2006.201.22:46:48.59#ibcon#wrote, iclass 30, count 0 2006.201.22:46:48.59#ibcon#about to read 3, iclass 30, count 0 2006.201.22:46:48.63#ibcon#read 3, iclass 30, count 0 2006.201.22:46:48.63#ibcon#about to read 4, iclass 30, count 0 2006.201.22:46:48.63#ibcon#read 4, iclass 30, count 0 2006.201.22:46:48.63#ibcon#about to read 5, iclass 30, count 0 2006.201.22:46:48.63#ibcon#read 5, iclass 30, count 0 2006.201.22:46:48.63#ibcon#about to read 6, iclass 30, count 0 2006.201.22:46:48.63#ibcon#read 6, iclass 30, count 0 2006.201.22:46:48.63#ibcon#end of sib2, iclass 30, count 0 2006.201.22:46:48.63#ibcon#*after write, iclass 30, count 0 2006.201.22:46:48.63#ibcon#*before return 0, iclass 30, count 0 2006.201.22:46:48.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:48.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:48.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.22:46:48.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.22:46:48.63$vck44/va=6,5 2006.201.22:46:48.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.22:46:48.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.22:46:48.63#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:48.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:48.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:48.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:48.69#ibcon#enter wrdev, iclass 32, count 2 2006.201.22:46:48.69#ibcon#first serial, iclass 32, count 2 2006.201.22:46:48.69#ibcon#enter sib2, iclass 32, count 2 2006.201.22:46:48.69#ibcon#flushed, iclass 32, count 2 2006.201.22:46:48.69#ibcon#about to write, iclass 32, count 2 2006.201.22:46:48.69#ibcon#wrote, iclass 32, count 2 2006.201.22:46:48.69#ibcon#about to read 3, iclass 32, count 2 2006.201.22:46:48.71#ibcon#read 3, iclass 32, count 2 2006.201.22:46:48.71#ibcon#about to read 4, iclass 32, count 2 2006.201.22:46:48.71#ibcon#read 4, iclass 32, count 2 2006.201.22:46:48.71#ibcon#about to read 5, iclass 32, count 2 2006.201.22:46:48.71#ibcon#read 5, iclass 32, count 2 2006.201.22:46:48.71#ibcon#about to read 6, iclass 32, count 2 2006.201.22:46:48.71#ibcon#read 6, iclass 32, count 2 2006.201.22:46:48.71#ibcon#end of sib2, iclass 32, count 2 2006.201.22:46:48.71#ibcon#*mode == 0, iclass 32, count 2 2006.201.22:46:48.71#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.22:46:48.71#ibcon#[25=AT06-05\r\n] 2006.201.22:46:48.71#ibcon#*before write, iclass 32, count 2 2006.201.22:46:48.71#ibcon#enter sib2, iclass 32, count 2 2006.201.22:46:48.71#ibcon#flushed, iclass 32, count 2 2006.201.22:46:48.71#ibcon#about to write, iclass 32, count 2 2006.201.22:46:48.71#ibcon#wrote, iclass 32, count 2 2006.201.22:46:48.71#ibcon#about to read 3, iclass 32, count 2 2006.201.22:46:48.74#ibcon#read 3, iclass 32, count 2 2006.201.22:46:48.74#ibcon#about to read 4, iclass 32, count 2 2006.201.22:46:48.74#ibcon#read 4, iclass 32, count 2 2006.201.22:46:48.74#ibcon#about to read 5, iclass 32, count 2 2006.201.22:46:48.74#ibcon#read 5, iclass 32, count 2 2006.201.22:46:48.74#ibcon#about to read 6, iclass 32, count 2 2006.201.22:46:48.74#ibcon#read 6, iclass 32, count 2 2006.201.22:46:48.74#ibcon#end of sib2, iclass 32, count 2 2006.201.22:46:48.74#ibcon#*after write, iclass 32, count 2 2006.201.22:46:48.74#ibcon#*before return 0, iclass 32, count 2 2006.201.22:46:48.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:48.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:48.74#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.22:46:48.74#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:48.74#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:48.86#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:48.86#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:48.86#ibcon#enter wrdev, iclass 32, count 0 2006.201.22:46:48.86#ibcon#first serial, iclass 32, count 0 2006.201.22:46:48.86#ibcon#enter sib2, iclass 32, count 0 2006.201.22:46:48.86#ibcon#flushed, iclass 32, count 0 2006.201.22:46:48.86#ibcon#about to write, iclass 32, count 0 2006.201.22:46:48.86#ibcon#wrote, iclass 32, count 0 2006.201.22:46:48.86#ibcon#about to read 3, iclass 32, count 0 2006.201.22:46:48.88#ibcon#read 3, iclass 32, count 0 2006.201.22:46:48.88#ibcon#about to read 4, iclass 32, count 0 2006.201.22:46:48.88#ibcon#read 4, iclass 32, count 0 2006.201.22:46:48.88#ibcon#about to read 5, iclass 32, count 0 2006.201.22:46:48.88#ibcon#read 5, iclass 32, count 0 2006.201.22:46:48.88#ibcon#about to read 6, iclass 32, count 0 2006.201.22:46:48.88#ibcon#read 6, iclass 32, count 0 2006.201.22:46:48.88#ibcon#end of sib2, iclass 32, count 0 2006.201.22:46:48.88#ibcon#*mode == 0, iclass 32, count 0 2006.201.22:46:48.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.22:46:48.88#ibcon#[25=USB\r\n] 2006.201.22:46:48.88#ibcon#*before write, iclass 32, count 0 2006.201.22:46:48.88#ibcon#enter sib2, iclass 32, count 0 2006.201.22:46:48.88#ibcon#flushed, iclass 32, count 0 2006.201.22:46:48.88#ibcon#about to write, iclass 32, count 0 2006.201.22:46:48.88#ibcon#wrote, iclass 32, count 0 2006.201.22:46:48.88#ibcon#about to read 3, iclass 32, count 0 2006.201.22:46:48.91#ibcon#read 3, iclass 32, count 0 2006.201.22:46:48.91#ibcon#about to read 4, iclass 32, count 0 2006.201.22:46:48.91#ibcon#read 4, iclass 32, count 0 2006.201.22:46:48.91#ibcon#about to read 5, iclass 32, count 0 2006.201.22:46:48.91#ibcon#read 5, iclass 32, count 0 2006.201.22:46:48.91#ibcon#about to read 6, iclass 32, count 0 2006.201.22:46:48.91#ibcon#read 6, iclass 32, count 0 2006.201.22:46:48.91#ibcon#end of sib2, iclass 32, count 0 2006.201.22:46:48.91#ibcon#*after write, iclass 32, count 0 2006.201.22:46:48.91#ibcon#*before return 0, iclass 32, count 0 2006.201.22:46:48.91#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:48.91#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:48.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.22:46:48.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.22:46:48.91$vck44/valo=7,864.99 2006.201.22:46:48.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.22:46:48.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.22:46:48.91#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:48.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:48.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:48.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:48.91#ibcon#enter wrdev, iclass 34, count 0 2006.201.22:46:48.91#ibcon#first serial, iclass 34, count 0 2006.201.22:46:48.91#ibcon#enter sib2, iclass 34, count 0 2006.201.22:46:48.91#ibcon#flushed, iclass 34, count 0 2006.201.22:46:48.91#ibcon#about to write, iclass 34, count 0 2006.201.22:46:48.91#ibcon#wrote, iclass 34, count 0 2006.201.22:46:48.91#ibcon#about to read 3, iclass 34, count 0 2006.201.22:46:48.93#ibcon#read 3, iclass 34, count 0 2006.201.22:46:48.93#ibcon#about to read 4, iclass 34, count 0 2006.201.22:46:48.93#ibcon#read 4, iclass 34, count 0 2006.201.22:46:48.93#ibcon#about to read 5, iclass 34, count 0 2006.201.22:46:48.93#ibcon#read 5, iclass 34, count 0 2006.201.22:46:48.93#ibcon#about to read 6, iclass 34, count 0 2006.201.22:46:48.93#ibcon#read 6, iclass 34, count 0 2006.201.22:46:48.93#ibcon#end of sib2, iclass 34, count 0 2006.201.22:46:48.93#ibcon#*mode == 0, iclass 34, count 0 2006.201.22:46:48.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.22:46:48.93#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.22:46:48.93#ibcon#*before write, iclass 34, count 0 2006.201.22:46:48.93#ibcon#enter sib2, iclass 34, count 0 2006.201.22:46:48.93#ibcon#flushed, iclass 34, count 0 2006.201.22:46:48.93#ibcon#about to write, iclass 34, count 0 2006.201.22:46:48.93#ibcon#wrote, iclass 34, count 0 2006.201.22:46:48.93#ibcon#about to read 3, iclass 34, count 0 2006.201.22:46:48.97#ibcon#read 3, iclass 34, count 0 2006.201.22:46:48.97#ibcon#about to read 4, iclass 34, count 0 2006.201.22:46:48.97#ibcon#read 4, iclass 34, count 0 2006.201.22:46:48.97#ibcon#about to read 5, iclass 34, count 0 2006.201.22:46:48.97#ibcon#read 5, iclass 34, count 0 2006.201.22:46:48.97#ibcon#about to read 6, iclass 34, count 0 2006.201.22:46:48.97#ibcon#read 6, iclass 34, count 0 2006.201.22:46:48.97#ibcon#end of sib2, iclass 34, count 0 2006.201.22:46:48.97#ibcon#*after write, iclass 34, count 0 2006.201.22:46:48.97#ibcon#*before return 0, iclass 34, count 0 2006.201.22:46:48.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:48.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:48.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.22:46:48.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.22:46:48.97$vck44/va=7,5 2006.201.22:46:48.97#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.22:46:48.97#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.22:46:48.97#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:48.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:49.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:49.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:49.03#ibcon#enter wrdev, iclass 36, count 2 2006.201.22:46:49.03#ibcon#first serial, iclass 36, count 2 2006.201.22:46:49.03#ibcon#enter sib2, iclass 36, count 2 2006.201.22:46:49.03#ibcon#flushed, iclass 36, count 2 2006.201.22:46:49.03#ibcon#about to write, iclass 36, count 2 2006.201.22:46:49.03#ibcon#wrote, iclass 36, count 2 2006.201.22:46:49.03#ibcon#about to read 3, iclass 36, count 2 2006.201.22:46:49.05#ibcon#read 3, iclass 36, count 2 2006.201.22:46:49.05#ibcon#about to read 4, iclass 36, count 2 2006.201.22:46:49.05#ibcon#read 4, iclass 36, count 2 2006.201.22:46:49.05#ibcon#about to read 5, iclass 36, count 2 2006.201.22:46:49.05#ibcon#read 5, iclass 36, count 2 2006.201.22:46:49.05#ibcon#about to read 6, iclass 36, count 2 2006.201.22:46:49.05#ibcon#read 6, iclass 36, count 2 2006.201.22:46:49.05#ibcon#end of sib2, iclass 36, count 2 2006.201.22:46:49.05#ibcon#*mode == 0, iclass 36, count 2 2006.201.22:46:49.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.22:46:49.05#ibcon#[25=AT07-05\r\n] 2006.201.22:46:49.05#ibcon#*before write, iclass 36, count 2 2006.201.22:46:49.05#ibcon#enter sib2, iclass 36, count 2 2006.201.22:46:49.05#ibcon#flushed, iclass 36, count 2 2006.201.22:46:49.05#ibcon#about to write, iclass 36, count 2 2006.201.22:46:49.05#ibcon#wrote, iclass 36, count 2 2006.201.22:46:49.05#ibcon#about to read 3, iclass 36, count 2 2006.201.22:46:49.08#ibcon#read 3, iclass 36, count 2 2006.201.22:46:49.08#ibcon#about to read 4, iclass 36, count 2 2006.201.22:46:49.08#ibcon#read 4, iclass 36, count 2 2006.201.22:46:49.08#ibcon#about to read 5, iclass 36, count 2 2006.201.22:46:49.08#ibcon#read 5, iclass 36, count 2 2006.201.22:46:49.08#ibcon#about to read 6, iclass 36, count 2 2006.201.22:46:49.08#ibcon#read 6, iclass 36, count 2 2006.201.22:46:49.08#ibcon#end of sib2, iclass 36, count 2 2006.201.22:46:49.08#ibcon#*after write, iclass 36, count 2 2006.201.22:46:49.08#ibcon#*before return 0, iclass 36, count 2 2006.201.22:46:49.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:49.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:49.08#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.22:46:49.08#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:49.08#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:49.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:49.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:49.20#ibcon#enter wrdev, iclass 36, count 0 2006.201.22:46:49.20#ibcon#first serial, iclass 36, count 0 2006.201.22:46:49.20#ibcon#enter sib2, iclass 36, count 0 2006.201.22:46:49.20#ibcon#flushed, iclass 36, count 0 2006.201.22:46:49.20#ibcon#about to write, iclass 36, count 0 2006.201.22:46:49.20#ibcon#wrote, iclass 36, count 0 2006.201.22:46:49.20#ibcon#about to read 3, iclass 36, count 0 2006.201.22:46:49.22#ibcon#read 3, iclass 36, count 0 2006.201.22:46:49.22#ibcon#about to read 4, iclass 36, count 0 2006.201.22:46:49.22#ibcon#read 4, iclass 36, count 0 2006.201.22:46:49.22#ibcon#about to read 5, iclass 36, count 0 2006.201.22:46:49.22#ibcon#read 5, iclass 36, count 0 2006.201.22:46:49.22#ibcon#about to read 6, iclass 36, count 0 2006.201.22:46:49.22#ibcon#read 6, iclass 36, count 0 2006.201.22:46:49.22#ibcon#end of sib2, iclass 36, count 0 2006.201.22:46:49.22#ibcon#*mode == 0, iclass 36, count 0 2006.201.22:46:49.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.22:46:49.22#ibcon#[25=USB\r\n] 2006.201.22:46:49.22#ibcon#*before write, iclass 36, count 0 2006.201.22:46:49.22#ibcon#enter sib2, iclass 36, count 0 2006.201.22:46:49.22#ibcon#flushed, iclass 36, count 0 2006.201.22:46:49.22#ibcon#about to write, iclass 36, count 0 2006.201.22:46:49.22#ibcon#wrote, iclass 36, count 0 2006.201.22:46:49.22#ibcon#about to read 3, iclass 36, count 0 2006.201.22:46:49.25#ibcon#read 3, iclass 36, count 0 2006.201.22:46:49.25#ibcon#about to read 4, iclass 36, count 0 2006.201.22:46:49.25#ibcon#read 4, iclass 36, count 0 2006.201.22:46:49.25#ibcon#about to read 5, iclass 36, count 0 2006.201.22:46:49.25#ibcon#read 5, iclass 36, count 0 2006.201.22:46:49.25#ibcon#about to read 6, iclass 36, count 0 2006.201.22:46:49.25#ibcon#read 6, iclass 36, count 0 2006.201.22:46:49.25#ibcon#end of sib2, iclass 36, count 0 2006.201.22:46:49.25#ibcon#*after write, iclass 36, count 0 2006.201.22:46:49.25#ibcon#*before return 0, iclass 36, count 0 2006.201.22:46:49.25#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:49.25#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:49.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.22:46:49.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.22:46:49.25$vck44/valo=8,884.99 2006.201.22:46:49.25#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.22:46:49.25#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.22:46:49.25#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:49.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:49.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:49.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:49.25#ibcon#enter wrdev, iclass 38, count 0 2006.201.22:46:49.25#ibcon#first serial, iclass 38, count 0 2006.201.22:46:49.25#ibcon#enter sib2, iclass 38, count 0 2006.201.22:46:49.25#ibcon#flushed, iclass 38, count 0 2006.201.22:46:49.25#ibcon#about to write, iclass 38, count 0 2006.201.22:46:49.25#ibcon#wrote, iclass 38, count 0 2006.201.22:46:49.25#ibcon#about to read 3, iclass 38, count 0 2006.201.22:46:49.27#ibcon#read 3, iclass 38, count 0 2006.201.22:46:49.27#ibcon#about to read 4, iclass 38, count 0 2006.201.22:46:49.27#ibcon#read 4, iclass 38, count 0 2006.201.22:46:49.27#ibcon#about to read 5, iclass 38, count 0 2006.201.22:46:49.27#ibcon#read 5, iclass 38, count 0 2006.201.22:46:49.27#ibcon#about to read 6, iclass 38, count 0 2006.201.22:46:49.27#ibcon#read 6, iclass 38, count 0 2006.201.22:46:49.27#ibcon#end of sib2, iclass 38, count 0 2006.201.22:46:49.27#ibcon#*mode == 0, iclass 38, count 0 2006.201.22:46:49.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.22:46:49.27#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.22:46:49.27#ibcon#*before write, iclass 38, count 0 2006.201.22:46:49.27#ibcon#enter sib2, iclass 38, count 0 2006.201.22:46:49.27#ibcon#flushed, iclass 38, count 0 2006.201.22:46:49.27#ibcon#about to write, iclass 38, count 0 2006.201.22:46:49.27#ibcon#wrote, iclass 38, count 0 2006.201.22:46:49.27#ibcon#about to read 3, iclass 38, count 0 2006.201.22:46:49.31#ibcon#read 3, iclass 38, count 0 2006.201.22:46:49.31#ibcon#about to read 4, iclass 38, count 0 2006.201.22:46:49.31#ibcon#read 4, iclass 38, count 0 2006.201.22:46:49.31#ibcon#about to read 5, iclass 38, count 0 2006.201.22:46:49.31#ibcon#read 5, iclass 38, count 0 2006.201.22:46:49.31#ibcon#about to read 6, iclass 38, count 0 2006.201.22:46:49.31#ibcon#read 6, iclass 38, count 0 2006.201.22:46:49.31#ibcon#end of sib2, iclass 38, count 0 2006.201.22:46:49.31#ibcon#*after write, iclass 38, count 0 2006.201.22:46:49.31#ibcon#*before return 0, iclass 38, count 0 2006.201.22:46:49.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:49.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:49.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.22:46:49.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.22:46:49.31$vck44/va=8,4 2006.201.22:46:49.31#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.22:46:49.31#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.22:46:49.31#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:49.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:46:49.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:46:49.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:46:49.37#ibcon#enter wrdev, iclass 40, count 2 2006.201.22:46:49.37#ibcon#first serial, iclass 40, count 2 2006.201.22:46:49.37#ibcon#enter sib2, iclass 40, count 2 2006.201.22:46:49.37#ibcon#flushed, iclass 40, count 2 2006.201.22:46:49.37#ibcon#about to write, iclass 40, count 2 2006.201.22:46:49.37#ibcon#wrote, iclass 40, count 2 2006.201.22:46:49.37#ibcon#about to read 3, iclass 40, count 2 2006.201.22:46:49.39#ibcon#read 3, iclass 40, count 2 2006.201.22:46:49.39#ibcon#about to read 4, iclass 40, count 2 2006.201.22:46:49.39#ibcon#read 4, iclass 40, count 2 2006.201.22:46:49.39#ibcon#about to read 5, iclass 40, count 2 2006.201.22:46:49.39#ibcon#read 5, iclass 40, count 2 2006.201.22:46:49.39#ibcon#about to read 6, iclass 40, count 2 2006.201.22:46:49.39#ibcon#read 6, iclass 40, count 2 2006.201.22:46:49.39#ibcon#end of sib2, iclass 40, count 2 2006.201.22:46:49.39#ibcon#*mode == 0, iclass 40, count 2 2006.201.22:46:49.39#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.22:46:49.39#ibcon#[25=AT08-04\r\n] 2006.201.22:46:49.39#ibcon#*before write, iclass 40, count 2 2006.201.22:46:49.39#ibcon#enter sib2, iclass 40, count 2 2006.201.22:46:49.39#ibcon#flushed, iclass 40, count 2 2006.201.22:46:49.39#ibcon#about to write, iclass 40, count 2 2006.201.22:46:49.39#ibcon#wrote, iclass 40, count 2 2006.201.22:46:49.39#ibcon#about to read 3, iclass 40, count 2 2006.201.22:46:49.42#ibcon#read 3, iclass 40, count 2 2006.201.22:46:49.42#ibcon#about to read 4, iclass 40, count 2 2006.201.22:46:49.42#ibcon#read 4, iclass 40, count 2 2006.201.22:46:49.42#ibcon#about to read 5, iclass 40, count 2 2006.201.22:46:49.42#ibcon#read 5, iclass 40, count 2 2006.201.22:46:49.42#ibcon#about to read 6, iclass 40, count 2 2006.201.22:46:49.42#ibcon#read 6, iclass 40, count 2 2006.201.22:46:49.42#ibcon#end of sib2, iclass 40, count 2 2006.201.22:46:49.42#ibcon#*after write, iclass 40, count 2 2006.201.22:46:49.42#ibcon#*before return 0, iclass 40, count 2 2006.201.22:46:49.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:46:49.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.22:46:49.42#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.22:46:49.42#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:49.42#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:46:49.54#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:46:49.54#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:46:49.54#ibcon#enter wrdev, iclass 40, count 0 2006.201.22:46:49.54#ibcon#first serial, iclass 40, count 0 2006.201.22:46:49.54#ibcon#enter sib2, iclass 40, count 0 2006.201.22:46:49.54#ibcon#flushed, iclass 40, count 0 2006.201.22:46:49.54#ibcon#about to write, iclass 40, count 0 2006.201.22:46:49.54#ibcon#wrote, iclass 40, count 0 2006.201.22:46:49.54#ibcon#about to read 3, iclass 40, count 0 2006.201.22:46:49.56#ibcon#read 3, iclass 40, count 0 2006.201.22:46:49.56#ibcon#about to read 4, iclass 40, count 0 2006.201.22:46:49.56#ibcon#read 4, iclass 40, count 0 2006.201.22:46:49.56#ibcon#about to read 5, iclass 40, count 0 2006.201.22:46:49.56#ibcon#read 5, iclass 40, count 0 2006.201.22:46:49.56#ibcon#about to read 6, iclass 40, count 0 2006.201.22:46:49.56#ibcon#read 6, iclass 40, count 0 2006.201.22:46:49.56#ibcon#end of sib2, iclass 40, count 0 2006.201.22:46:49.56#ibcon#*mode == 0, iclass 40, count 0 2006.201.22:46:49.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.22:46:49.56#ibcon#[25=USB\r\n] 2006.201.22:46:49.56#ibcon#*before write, iclass 40, count 0 2006.201.22:46:49.56#ibcon#enter sib2, iclass 40, count 0 2006.201.22:46:49.56#ibcon#flushed, iclass 40, count 0 2006.201.22:46:49.56#ibcon#about to write, iclass 40, count 0 2006.201.22:46:49.56#ibcon#wrote, iclass 40, count 0 2006.201.22:46:49.56#ibcon#about to read 3, iclass 40, count 0 2006.201.22:46:49.59#ibcon#read 3, iclass 40, count 0 2006.201.22:46:49.59#ibcon#about to read 4, iclass 40, count 0 2006.201.22:46:49.59#ibcon#read 4, iclass 40, count 0 2006.201.22:46:49.59#ibcon#about to read 5, iclass 40, count 0 2006.201.22:46:49.59#ibcon#read 5, iclass 40, count 0 2006.201.22:46:49.59#ibcon#about to read 6, iclass 40, count 0 2006.201.22:46:49.59#ibcon#read 6, iclass 40, count 0 2006.201.22:46:49.59#ibcon#end of sib2, iclass 40, count 0 2006.201.22:46:49.59#ibcon#*after write, iclass 40, count 0 2006.201.22:46:49.59#ibcon#*before return 0, iclass 40, count 0 2006.201.22:46:49.59#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:46:49.59#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.22:46:49.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.22:46:49.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.22:46:49.59$vck44/vblo=1,629.99 2006.201.22:46:49.59#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.22:46:49.59#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.22:46:49.59#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:49.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:46:49.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:46:49.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:46:49.59#ibcon#enter wrdev, iclass 4, count 0 2006.201.22:46:49.59#ibcon#first serial, iclass 4, count 0 2006.201.22:46:49.59#ibcon#enter sib2, iclass 4, count 0 2006.201.22:46:49.59#ibcon#flushed, iclass 4, count 0 2006.201.22:46:49.59#ibcon#about to write, iclass 4, count 0 2006.201.22:46:49.59#ibcon#wrote, iclass 4, count 0 2006.201.22:46:49.59#ibcon#about to read 3, iclass 4, count 0 2006.201.22:46:49.61#ibcon#read 3, iclass 4, count 0 2006.201.22:46:49.61#ibcon#about to read 4, iclass 4, count 0 2006.201.22:46:49.61#ibcon#read 4, iclass 4, count 0 2006.201.22:46:49.61#ibcon#about to read 5, iclass 4, count 0 2006.201.22:46:49.61#ibcon#read 5, iclass 4, count 0 2006.201.22:46:49.61#ibcon#about to read 6, iclass 4, count 0 2006.201.22:46:49.61#ibcon#read 6, iclass 4, count 0 2006.201.22:46:49.61#ibcon#end of sib2, iclass 4, count 0 2006.201.22:46:49.61#ibcon#*mode == 0, iclass 4, count 0 2006.201.22:46:49.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.22:46:49.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.22:46:49.61#ibcon#*before write, iclass 4, count 0 2006.201.22:46:49.61#ibcon#enter sib2, iclass 4, count 0 2006.201.22:46:49.61#ibcon#flushed, iclass 4, count 0 2006.201.22:46:49.61#ibcon#about to write, iclass 4, count 0 2006.201.22:46:49.61#ibcon#wrote, iclass 4, count 0 2006.201.22:46:49.61#ibcon#about to read 3, iclass 4, count 0 2006.201.22:46:49.66#ibcon#read 3, iclass 4, count 0 2006.201.22:46:49.66#ibcon#about to read 4, iclass 4, count 0 2006.201.22:46:49.66#ibcon#read 4, iclass 4, count 0 2006.201.22:46:49.66#ibcon#about to read 5, iclass 4, count 0 2006.201.22:46:49.66#ibcon#read 5, iclass 4, count 0 2006.201.22:46:49.66#ibcon#about to read 6, iclass 4, count 0 2006.201.22:46:49.66#ibcon#read 6, iclass 4, count 0 2006.201.22:46:49.66#ibcon#end of sib2, iclass 4, count 0 2006.201.22:46:49.66#ibcon#*after write, iclass 4, count 0 2006.201.22:46:49.66#ibcon#*before return 0, iclass 4, count 0 2006.201.22:46:49.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:46:49.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.22:46:49.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.22:46:49.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.22:46:49.66$vck44/vb=1,4 2006.201.22:46:49.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.22:46:49.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.22:46:49.66#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:49.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:46:49.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:46:49.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:46:49.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.22:46:49.66#ibcon#first serial, iclass 6, count 2 2006.201.22:46:49.66#ibcon#enter sib2, iclass 6, count 2 2006.201.22:46:49.66#ibcon#flushed, iclass 6, count 2 2006.201.22:46:49.66#ibcon#about to write, iclass 6, count 2 2006.201.22:46:49.66#ibcon#wrote, iclass 6, count 2 2006.201.22:46:49.66#ibcon#about to read 3, iclass 6, count 2 2006.201.22:46:49.68#ibcon#read 3, iclass 6, count 2 2006.201.22:46:49.68#ibcon#about to read 4, iclass 6, count 2 2006.201.22:46:49.68#ibcon#read 4, iclass 6, count 2 2006.201.22:46:49.68#ibcon#about to read 5, iclass 6, count 2 2006.201.22:46:49.68#ibcon#read 5, iclass 6, count 2 2006.201.22:46:49.68#ibcon#about to read 6, iclass 6, count 2 2006.201.22:46:49.68#ibcon#read 6, iclass 6, count 2 2006.201.22:46:49.68#ibcon#end of sib2, iclass 6, count 2 2006.201.22:46:49.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.22:46:49.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.22:46:49.68#ibcon#[27=AT01-04\r\n] 2006.201.22:46:49.68#ibcon#*before write, iclass 6, count 2 2006.201.22:46:49.68#ibcon#enter sib2, iclass 6, count 2 2006.201.22:46:49.68#ibcon#flushed, iclass 6, count 2 2006.201.22:46:49.68#ibcon#about to write, iclass 6, count 2 2006.201.22:46:49.68#ibcon#wrote, iclass 6, count 2 2006.201.22:46:49.68#ibcon#about to read 3, iclass 6, count 2 2006.201.22:46:49.71#ibcon#read 3, iclass 6, count 2 2006.201.22:46:49.71#ibcon#about to read 4, iclass 6, count 2 2006.201.22:46:49.71#ibcon#read 4, iclass 6, count 2 2006.201.22:46:49.71#ibcon#about to read 5, iclass 6, count 2 2006.201.22:46:49.71#ibcon#read 5, iclass 6, count 2 2006.201.22:46:49.71#ibcon#about to read 6, iclass 6, count 2 2006.201.22:46:49.71#ibcon#read 6, iclass 6, count 2 2006.201.22:46:49.71#ibcon#end of sib2, iclass 6, count 2 2006.201.22:46:49.71#ibcon#*after write, iclass 6, count 2 2006.201.22:46:49.71#ibcon#*before return 0, iclass 6, count 2 2006.201.22:46:49.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:46:49.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.22:46:49.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.22:46:49.71#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:49.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:46:49.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:46:49.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:46:49.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.22:46:49.83#ibcon#first serial, iclass 6, count 0 2006.201.22:46:49.83#ibcon#enter sib2, iclass 6, count 0 2006.201.22:46:49.83#ibcon#flushed, iclass 6, count 0 2006.201.22:46:49.83#ibcon#about to write, iclass 6, count 0 2006.201.22:46:49.83#ibcon#wrote, iclass 6, count 0 2006.201.22:46:49.83#ibcon#about to read 3, iclass 6, count 0 2006.201.22:46:49.85#ibcon#read 3, iclass 6, count 0 2006.201.22:46:49.85#ibcon#about to read 4, iclass 6, count 0 2006.201.22:46:49.85#ibcon#read 4, iclass 6, count 0 2006.201.22:46:49.85#ibcon#about to read 5, iclass 6, count 0 2006.201.22:46:49.85#ibcon#read 5, iclass 6, count 0 2006.201.22:46:49.85#ibcon#about to read 6, iclass 6, count 0 2006.201.22:46:49.85#ibcon#read 6, iclass 6, count 0 2006.201.22:46:49.85#ibcon#end of sib2, iclass 6, count 0 2006.201.22:46:49.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.22:46:49.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.22:46:49.85#ibcon#[27=USB\r\n] 2006.201.22:46:49.85#ibcon#*before write, iclass 6, count 0 2006.201.22:46:49.85#ibcon#enter sib2, iclass 6, count 0 2006.201.22:46:49.85#ibcon#flushed, iclass 6, count 0 2006.201.22:46:49.85#ibcon#about to write, iclass 6, count 0 2006.201.22:46:49.85#ibcon#wrote, iclass 6, count 0 2006.201.22:46:49.85#ibcon#about to read 3, iclass 6, count 0 2006.201.22:46:49.88#ibcon#read 3, iclass 6, count 0 2006.201.22:46:49.88#ibcon#about to read 4, iclass 6, count 0 2006.201.22:46:49.88#ibcon#read 4, iclass 6, count 0 2006.201.22:46:49.88#ibcon#about to read 5, iclass 6, count 0 2006.201.22:46:49.88#ibcon#read 5, iclass 6, count 0 2006.201.22:46:49.88#ibcon#about to read 6, iclass 6, count 0 2006.201.22:46:49.88#ibcon#read 6, iclass 6, count 0 2006.201.22:46:49.88#ibcon#end of sib2, iclass 6, count 0 2006.201.22:46:49.88#ibcon#*after write, iclass 6, count 0 2006.201.22:46:49.88#ibcon#*before return 0, iclass 6, count 0 2006.201.22:46:49.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:46:49.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.22:46:49.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.22:46:49.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.22:46:49.88$vck44/vblo=2,634.99 2006.201.22:46:49.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.22:46:49.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.22:46:49.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:49.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:49.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:49.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:49.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.22:46:49.88#ibcon#first serial, iclass 10, count 0 2006.201.22:46:49.88#ibcon#enter sib2, iclass 10, count 0 2006.201.22:46:49.88#ibcon#flushed, iclass 10, count 0 2006.201.22:46:49.88#ibcon#about to write, iclass 10, count 0 2006.201.22:46:49.88#ibcon#wrote, iclass 10, count 0 2006.201.22:46:49.88#ibcon#about to read 3, iclass 10, count 0 2006.201.22:46:49.90#ibcon#read 3, iclass 10, count 0 2006.201.22:46:49.90#ibcon#about to read 4, iclass 10, count 0 2006.201.22:46:49.90#ibcon#read 4, iclass 10, count 0 2006.201.22:46:49.90#ibcon#about to read 5, iclass 10, count 0 2006.201.22:46:49.90#ibcon#read 5, iclass 10, count 0 2006.201.22:46:49.90#ibcon#about to read 6, iclass 10, count 0 2006.201.22:46:49.90#ibcon#read 6, iclass 10, count 0 2006.201.22:46:49.90#ibcon#end of sib2, iclass 10, count 0 2006.201.22:46:49.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.22:46:49.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.22:46:49.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.22:46:49.90#ibcon#*before write, iclass 10, count 0 2006.201.22:46:49.90#ibcon#enter sib2, iclass 10, count 0 2006.201.22:46:49.90#ibcon#flushed, iclass 10, count 0 2006.201.22:46:49.90#ibcon#about to write, iclass 10, count 0 2006.201.22:46:49.90#ibcon#wrote, iclass 10, count 0 2006.201.22:46:49.90#ibcon#about to read 3, iclass 10, count 0 2006.201.22:46:49.94#ibcon#read 3, iclass 10, count 0 2006.201.22:46:49.94#ibcon#about to read 4, iclass 10, count 0 2006.201.22:46:49.94#ibcon#read 4, iclass 10, count 0 2006.201.22:46:49.94#ibcon#about to read 5, iclass 10, count 0 2006.201.22:46:49.94#ibcon#read 5, iclass 10, count 0 2006.201.22:46:49.94#ibcon#about to read 6, iclass 10, count 0 2006.201.22:46:49.94#ibcon#read 6, iclass 10, count 0 2006.201.22:46:49.94#ibcon#end of sib2, iclass 10, count 0 2006.201.22:46:49.94#ibcon#*after write, iclass 10, count 0 2006.201.22:46:49.94#ibcon#*before return 0, iclass 10, count 0 2006.201.22:46:49.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:49.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.22:46:49.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.22:46:49.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.22:46:49.94$vck44/vb=2,5 2006.201.22:46:49.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.22:46:49.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.22:46:49.94#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:49.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:50.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:50.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:50.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.22:46:50.00#ibcon#first serial, iclass 12, count 2 2006.201.22:46:50.00#ibcon#enter sib2, iclass 12, count 2 2006.201.22:46:50.00#ibcon#flushed, iclass 12, count 2 2006.201.22:46:50.00#ibcon#about to write, iclass 12, count 2 2006.201.22:46:50.00#ibcon#wrote, iclass 12, count 2 2006.201.22:46:50.00#ibcon#about to read 3, iclass 12, count 2 2006.201.22:46:50.02#ibcon#read 3, iclass 12, count 2 2006.201.22:46:50.02#ibcon#about to read 4, iclass 12, count 2 2006.201.22:46:50.02#ibcon#read 4, iclass 12, count 2 2006.201.22:46:50.02#ibcon#about to read 5, iclass 12, count 2 2006.201.22:46:50.02#ibcon#read 5, iclass 12, count 2 2006.201.22:46:50.02#ibcon#about to read 6, iclass 12, count 2 2006.201.22:46:50.02#ibcon#read 6, iclass 12, count 2 2006.201.22:46:50.02#ibcon#end of sib2, iclass 12, count 2 2006.201.22:46:50.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.22:46:50.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.22:46:50.02#ibcon#[27=AT02-05\r\n] 2006.201.22:46:50.02#ibcon#*before write, iclass 12, count 2 2006.201.22:46:50.02#ibcon#enter sib2, iclass 12, count 2 2006.201.22:46:50.02#ibcon#flushed, iclass 12, count 2 2006.201.22:46:50.02#ibcon#about to write, iclass 12, count 2 2006.201.22:46:50.02#ibcon#wrote, iclass 12, count 2 2006.201.22:46:50.02#ibcon#about to read 3, iclass 12, count 2 2006.201.22:46:50.05#ibcon#read 3, iclass 12, count 2 2006.201.22:46:50.05#ibcon#about to read 4, iclass 12, count 2 2006.201.22:46:50.05#ibcon#read 4, iclass 12, count 2 2006.201.22:46:50.05#ibcon#about to read 5, iclass 12, count 2 2006.201.22:46:50.05#ibcon#read 5, iclass 12, count 2 2006.201.22:46:50.05#ibcon#about to read 6, iclass 12, count 2 2006.201.22:46:50.05#ibcon#read 6, iclass 12, count 2 2006.201.22:46:50.05#ibcon#end of sib2, iclass 12, count 2 2006.201.22:46:50.05#ibcon#*after write, iclass 12, count 2 2006.201.22:46:50.05#ibcon#*before return 0, iclass 12, count 2 2006.201.22:46:50.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:50.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.22:46:50.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.22:46:50.05#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:50.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:50.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:50.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:50.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.22:46:50.17#ibcon#first serial, iclass 12, count 0 2006.201.22:46:50.17#ibcon#enter sib2, iclass 12, count 0 2006.201.22:46:50.17#ibcon#flushed, iclass 12, count 0 2006.201.22:46:50.17#ibcon#about to write, iclass 12, count 0 2006.201.22:46:50.17#ibcon#wrote, iclass 12, count 0 2006.201.22:46:50.17#ibcon#about to read 3, iclass 12, count 0 2006.201.22:46:50.19#ibcon#read 3, iclass 12, count 0 2006.201.22:46:50.19#ibcon#about to read 4, iclass 12, count 0 2006.201.22:46:50.19#ibcon#read 4, iclass 12, count 0 2006.201.22:46:50.19#ibcon#about to read 5, iclass 12, count 0 2006.201.22:46:50.19#ibcon#read 5, iclass 12, count 0 2006.201.22:46:50.19#ibcon#about to read 6, iclass 12, count 0 2006.201.22:46:50.19#ibcon#read 6, iclass 12, count 0 2006.201.22:46:50.19#ibcon#end of sib2, iclass 12, count 0 2006.201.22:46:50.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.22:46:50.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.22:46:50.19#ibcon#[27=USB\r\n] 2006.201.22:46:50.19#ibcon#*before write, iclass 12, count 0 2006.201.22:46:50.19#ibcon#enter sib2, iclass 12, count 0 2006.201.22:46:50.19#ibcon#flushed, iclass 12, count 0 2006.201.22:46:50.19#ibcon#about to write, iclass 12, count 0 2006.201.22:46:50.19#ibcon#wrote, iclass 12, count 0 2006.201.22:46:50.19#ibcon#about to read 3, iclass 12, count 0 2006.201.22:46:50.22#ibcon#read 3, iclass 12, count 0 2006.201.22:46:50.22#ibcon#about to read 4, iclass 12, count 0 2006.201.22:46:50.22#ibcon#read 4, iclass 12, count 0 2006.201.22:46:50.22#ibcon#about to read 5, iclass 12, count 0 2006.201.22:46:50.22#ibcon#read 5, iclass 12, count 0 2006.201.22:46:50.22#ibcon#about to read 6, iclass 12, count 0 2006.201.22:46:50.22#ibcon#read 6, iclass 12, count 0 2006.201.22:46:50.22#ibcon#end of sib2, iclass 12, count 0 2006.201.22:46:50.22#ibcon#*after write, iclass 12, count 0 2006.201.22:46:50.22#ibcon#*before return 0, iclass 12, count 0 2006.201.22:46:50.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:50.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.22:46:50.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.22:46:50.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.22:46:50.22$vck44/vblo=3,649.99 2006.201.22:46:50.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.22:46:50.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.22:46:50.22#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:50.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:50.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:50.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:50.22#ibcon#enter wrdev, iclass 14, count 0 2006.201.22:46:50.22#ibcon#first serial, iclass 14, count 0 2006.201.22:46:50.22#ibcon#enter sib2, iclass 14, count 0 2006.201.22:46:50.22#ibcon#flushed, iclass 14, count 0 2006.201.22:46:50.22#ibcon#about to write, iclass 14, count 0 2006.201.22:46:50.22#ibcon#wrote, iclass 14, count 0 2006.201.22:46:50.22#ibcon#about to read 3, iclass 14, count 0 2006.201.22:46:50.24#ibcon#read 3, iclass 14, count 0 2006.201.22:46:50.24#ibcon#about to read 4, iclass 14, count 0 2006.201.22:46:50.24#ibcon#read 4, iclass 14, count 0 2006.201.22:46:50.24#ibcon#about to read 5, iclass 14, count 0 2006.201.22:46:50.24#ibcon#read 5, iclass 14, count 0 2006.201.22:46:50.24#ibcon#about to read 6, iclass 14, count 0 2006.201.22:46:50.24#ibcon#read 6, iclass 14, count 0 2006.201.22:46:50.24#ibcon#end of sib2, iclass 14, count 0 2006.201.22:46:50.24#ibcon#*mode == 0, iclass 14, count 0 2006.201.22:46:50.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.22:46:50.24#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.22:46:50.24#ibcon#*before write, iclass 14, count 0 2006.201.22:46:50.24#ibcon#enter sib2, iclass 14, count 0 2006.201.22:46:50.24#ibcon#flushed, iclass 14, count 0 2006.201.22:46:50.24#ibcon#about to write, iclass 14, count 0 2006.201.22:46:50.24#ibcon#wrote, iclass 14, count 0 2006.201.22:46:50.24#ibcon#about to read 3, iclass 14, count 0 2006.201.22:46:50.28#ibcon#read 3, iclass 14, count 0 2006.201.22:46:50.28#ibcon#about to read 4, iclass 14, count 0 2006.201.22:46:50.28#ibcon#read 4, iclass 14, count 0 2006.201.22:46:50.28#ibcon#about to read 5, iclass 14, count 0 2006.201.22:46:50.28#ibcon#read 5, iclass 14, count 0 2006.201.22:46:50.28#ibcon#about to read 6, iclass 14, count 0 2006.201.22:46:50.28#ibcon#read 6, iclass 14, count 0 2006.201.22:46:50.28#ibcon#end of sib2, iclass 14, count 0 2006.201.22:46:50.28#ibcon#*after write, iclass 14, count 0 2006.201.22:46:50.28#ibcon#*before return 0, iclass 14, count 0 2006.201.22:46:50.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:50.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.22:46:50.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.22:46:50.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.22:46:50.28$vck44/vb=3,4 2006.201.22:46:50.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.22:46:50.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.22:46:50.28#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:50.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:50.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:50.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:50.34#ibcon#enter wrdev, iclass 16, count 2 2006.201.22:46:50.34#ibcon#first serial, iclass 16, count 2 2006.201.22:46:50.34#ibcon#enter sib2, iclass 16, count 2 2006.201.22:46:50.34#ibcon#flushed, iclass 16, count 2 2006.201.22:46:50.34#ibcon#about to write, iclass 16, count 2 2006.201.22:46:50.34#ibcon#wrote, iclass 16, count 2 2006.201.22:46:50.34#ibcon#about to read 3, iclass 16, count 2 2006.201.22:46:50.36#ibcon#read 3, iclass 16, count 2 2006.201.22:46:50.36#ibcon#about to read 4, iclass 16, count 2 2006.201.22:46:50.36#ibcon#read 4, iclass 16, count 2 2006.201.22:46:50.36#ibcon#about to read 5, iclass 16, count 2 2006.201.22:46:50.36#ibcon#read 5, iclass 16, count 2 2006.201.22:46:50.36#ibcon#about to read 6, iclass 16, count 2 2006.201.22:46:50.36#ibcon#read 6, iclass 16, count 2 2006.201.22:46:50.36#ibcon#end of sib2, iclass 16, count 2 2006.201.22:46:50.36#ibcon#*mode == 0, iclass 16, count 2 2006.201.22:46:50.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.22:46:50.36#ibcon#[27=AT03-04\r\n] 2006.201.22:46:50.36#ibcon#*before write, iclass 16, count 2 2006.201.22:46:50.36#ibcon#enter sib2, iclass 16, count 2 2006.201.22:46:50.36#ibcon#flushed, iclass 16, count 2 2006.201.22:46:50.36#ibcon#about to write, iclass 16, count 2 2006.201.22:46:50.36#ibcon#wrote, iclass 16, count 2 2006.201.22:46:50.36#ibcon#about to read 3, iclass 16, count 2 2006.201.22:46:50.39#ibcon#read 3, iclass 16, count 2 2006.201.22:46:50.39#ibcon#about to read 4, iclass 16, count 2 2006.201.22:46:50.39#ibcon#read 4, iclass 16, count 2 2006.201.22:46:50.39#ibcon#about to read 5, iclass 16, count 2 2006.201.22:46:50.39#ibcon#read 5, iclass 16, count 2 2006.201.22:46:50.39#ibcon#about to read 6, iclass 16, count 2 2006.201.22:46:50.39#ibcon#read 6, iclass 16, count 2 2006.201.22:46:50.39#ibcon#end of sib2, iclass 16, count 2 2006.201.22:46:50.39#ibcon#*after write, iclass 16, count 2 2006.201.22:46:50.39#ibcon#*before return 0, iclass 16, count 2 2006.201.22:46:50.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:50.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.22:46:50.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.22:46:50.39#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:50.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:50.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:50.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:50.51#ibcon#enter wrdev, iclass 16, count 0 2006.201.22:46:50.51#ibcon#first serial, iclass 16, count 0 2006.201.22:46:50.51#ibcon#enter sib2, iclass 16, count 0 2006.201.22:46:50.51#ibcon#flushed, iclass 16, count 0 2006.201.22:46:50.51#ibcon#about to write, iclass 16, count 0 2006.201.22:46:50.51#ibcon#wrote, iclass 16, count 0 2006.201.22:46:50.51#ibcon#about to read 3, iclass 16, count 0 2006.201.22:46:50.53#ibcon#read 3, iclass 16, count 0 2006.201.22:46:50.53#ibcon#about to read 4, iclass 16, count 0 2006.201.22:46:50.53#ibcon#read 4, iclass 16, count 0 2006.201.22:46:50.53#ibcon#about to read 5, iclass 16, count 0 2006.201.22:46:50.53#ibcon#read 5, iclass 16, count 0 2006.201.22:46:50.53#ibcon#about to read 6, iclass 16, count 0 2006.201.22:46:50.53#ibcon#read 6, iclass 16, count 0 2006.201.22:46:50.53#ibcon#end of sib2, iclass 16, count 0 2006.201.22:46:50.53#ibcon#*mode == 0, iclass 16, count 0 2006.201.22:46:50.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.22:46:50.53#ibcon#[27=USB\r\n] 2006.201.22:46:50.53#ibcon#*before write, iclass 16, count 0 2006.201.22:46:50.53#ibcon#enter sib2, iclass 16, count 0 2006.201.22:46:50.53#ibcon#flushed, iclass 16, count 0 2006.201.22:46:50.53#ibcon#about to write, iclass 16, count 0 2006.201.22:46:50.53#ibcon#wrote, iclass 16, count 0 2006.201.22:46:50.53#ibcon#about to read 3, iclass 16, count 0 2006.201.22:46:50.56#ibcon#read 3, iclass 16, count 0 2006.201.22:46:50.56#ibcon#about to read 4, iclass 16, count 0 2006.201.22:46:50.56#ibcon#read 4, iclass 16, count 0 2006.201.22:46:50.56#ibcon#about to read 5, iclass 16, count 0 2006.201.22:46:50.56#ibcon#read 5, iclass 16, count 0 2006.201.22:46:50.56#ibcon#about to read 6, iclass 16, count 0 2006.201.22:46:50.56#ibcon#read 6, iclass 16, count 0 2006.201.22:46:50.56#ibcon#end of sib2, iclass 16, count 0 2006.201.22:46:50.56#ibcon#*after write, iclass 16, count 0 2006.201.22:46:50.56#ibcon#*before return 0, iclass 16, count 0 2006.201.22:46:50.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:50.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.22:46:50.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.22:46:50.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.22:46:50.56$vck44/vblo=4,679.99 2006.201.22:46:50.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.22:46:50.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.22:46:50.56#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:50.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:50.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:50.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:50.56#ibcon#enter wrdev, iclass 18, count 0 2006.201.22:46:50.56#ibcon#first serial, iclass 18, count 0 2006.201.22:46:50.56#ibcon#enter sib2, iclass 18, count 0 2006.201.22:46:50.56#ibcon#flushed, iclass 18, count 0 2006.201.22:46:50.56#ibcon#about to write, iclass 18, count 0 2006.201.22:46:50.56#ibcon#wrote, iclass 18, count 0 2006.201.22:46:50.56#ibcon#about to read 3, iclass 18, count 0 2006.201.22:46:50.58#ibcon#read 3, iclass 18, count 0 2006.201.22:46:50.58#ibcon#about to read 4, iclass 18, count 0 2006.201.22:46:50.58#ibcon#read 4, iclass 18, count 0 2006.201.22:46:50.58#ibcon#about to read 5, iclass 18, count 0 2006.201.22:46:50.58#ibcon#read 5, iclass 18, count 0 2006.201.22:46:50.58#ibcon#about to read 6, iclass 18, count 0 2006.201.22:46:50.58#ibcon#read 6, iclass 18, count 0 2006.201.22:46:50.58#ibcon#end of sib2, iclass 18, count 0 2006.201.22:46:50.58#ibcon#*mode == 0, iclass 18, count 0 2006.201.22:46:50.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.22:46:50.58#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.22:46:50.58#ibcon#*before write, iclass 18, count 0 2006.201.22:46:50.58#ibcon#enter sib2, iclass 18, count 0 2006.201.22:46:50.58#ibcon#flushed, iclass 18, count 0 2006.201.22:46:50.58#ibcon#about to write, iclass 18, count 0 2006.201.22:46:50.58#ibcon#wrote, iclass 18, count 0 2006.201.22:46:50.58#ibcon#about to read 3, iclass 18, count 0 2006.201.22:46:50.62#ibcon#read 3, iclass 18, count 0 2006.201.22:46:50.62#ibcon#about to read 4, iclass 18, count 0 2006.201.22:46:50.62#ibcon#read 4, iclass 18, count 0 2006.201.22:46:50.62#ibcon#about to read 5, iclass 18, count 0 2006.201.22:46:50.62#ibcon#read 5, iclass 18, count 0 2006.201.22:46:50.62#ibcon#about to read 6, iclass 18, count 0 2006.201.22:46:50.62#ibcon#read 6, iclass 18, count 0 2006.201.22:46:50.62#ibcon#end of sib2, iclass 18, count 0 2006.201.22:46:50.62#ibcon#*after write, iclass 18, count 0 2006.201.22:46:50.62#ibcon#*before return 0, iclass 18, count 0 2006.201.22:46:50.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:50.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.22:46:50.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.22:46:50.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.22:46:50.62$vck44/vb=4,5 2006.201.22:46:50.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.22:46:50.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.22:46:50.62#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:50.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:50.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:50.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:50.68#ibcon#enter wrdev, iclass 20, count 2 2006.201.22:46:50.68#ibcon#first serial, iclass 20, count 2 2006.201.22:46:50.68#ibcon#enter sib2, iclass 20, count 2 2006.201.22:46:50.68#ibcon#flushed, iclass 20, count 2 2006.201.22:46:50.68#ibcon#about to write, iclass 20, count 2 2006.201.22:46:50.68#ibcon#wrote, iclass 20, count 2 2006.201.22:46:50.68#ibcon#about to read 3, iclass 20, count 2 2006.201.22:46:50.70#ibcon#read 3, iclass 20, count 2 2006.201.22:46:50.70#ibcon#about to read 4, iclass 20, count 2 2006.201.22:46:50.70#ibcon#read 4, iclass 20, count 2 2006.201.22:46:50.70#ibcon#about to read 5, iclass 20, count 2 2006.201.22:46:50.70#ibcon#read 5, iclass 20, count 2 2006.201.22:46:50.70#ibcon#about to read 6, iclass 20, count 2 2006.201.22:46:50.70#ibcon#read 6, iclass 20, count 2 2006.201.22:46:50.70#ibcon#end of sib2, iclass 20, count 2 2006.201.22:46:50.70#ibcon#*mode == 0, iclass 20, count 2 2006.201.22:46:50.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.22:46:50.70#ibcon#[27=AT04-05\r\n] 2006.201.22:46:50.70#ibcon#*before write, iclass 20, count 2 2006.201.22:46:50.70#ibcon#enter sib2, iclass 20, count 2 2006.201.22:46:50.70#ibcon#flushed, iclass 20, count 2 2006.201.22:46:50.70#ibcon#about to write, iclass 20, count 2 2006.201.22:46:50.70#ibcon#wrote, iclass 20, count 2 2006.201.22:46:50.70#ibcon#about to read 3, iclass 20, count 2 2006.201.22:46:50.73#ibcon#read 3, iclass 20, count 2 2006.201.22:46:50.73#ibcon#about to read 4, iclass 20, count 2 2006.201.22:46:50.73#ibcon#read 4, iclass 20, count 2 2006.201.22:46:50.73#ibcon#about to read 5, iclass 20, count 2 2006.201.22:46:50.73#ibcon#read 5, iclass 20, count 2 2006.201.22:46:50.73#ibcon#about to read 6, iclass 20, count 2 2006.201.22:46:50.73#ibcon#read 6, iclass 20, count 2 2006.201.22:46:50.73#ibcon#end of sib2, iclass 20, count 2 2006.201.22:46:50.73#ibcon#*after write, iclass 20, count 2 2006.201.22:46:50.73#ibcon#*before return 0, iclass 20, count 2 2006.201.22:46:50.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:50.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.22:46:50.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.22:46:50.73#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:50.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:50.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:50.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:50.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.22:46:50.85#ibcon#first serial, iclass 20, count 0 2006.201.22:46:50.85#ibcon#enter sib2, iclass 20, count 0 2006.201.22:46:50.85#ibcon#flushed, iclass 20, count 0 2006.201.22:46:50.85#ibcon#about to write, iclass 20, count 0 2006.201.22:46:50.85#ibcon#wrote, iclass 20, count 0 2006.201.22:46:50.85#ibcon#about to read 3, iclass 20, count 0 2006.201.22:46:50.87#ibcon#read 3, iclass 20, count 0 2006.201.22:46:50.87#ibcon#about to read 4, iclass 20, count 0 2006.201.22:46:50.87#ibcon#read 4, iclass 20, count 0 2006.201.22:46:50.87#ibcon#about to read 5, iclass 20, count 0 2006.201.22:46:50.87#ibcon#read 5, iclass 20, count 0 2006.201.22:46:50.87#ibcon#about to read 6, iclass 20, count 0 2006.201.22:46:50.87#ibcon#read 6, iclass 20, count 0 2006.201.22:46:50.87#ibcon#end of sib2, iclass 20, count 0 2006.201.22:46:50.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.22:46:50.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.22:46:50.87#ibcon#[27=USB\r\n] 2006.201.22:46:50.87#ibcon#*before write, iclass 20, count 0 2006.201.22:46:50.87#ibcon#enter sib2, iclass 20, count 0 2006.201.22:46:50.87#ibcon#flushed, iclass 20, count 0 2006.201.22:46:50.87#ibcon#about to write, iclass 20, count 0 2006.201.22:46:50.87#ibcon#wrote, iclass 20, count 0 2006.201.22:46:50.87#ibcon#about to read 3, iclass 20, count 0 2006.201.22:46:50.90#ibcon#read 3, iclass 20, count 0 2006.201.22:46:50.90#ibcon#about to read 4, iclass 20, count 0 2006.201.22:46:50.90#ibcon#read 4, iclass 20, count 0 2006.201.22:46:50.90#ibcon#about to read 5, iclass 20, count 0 2006.201.22:46:50.90#ibcon#read 5, iclass 20, count 0 2006.201.22:46:50.90#ibcon#about to read 6, iclass 20, count 0 2006.201.22:46:50.90#ibcon#read 6, iclass 20, count 0 2006.201.22:46:50.90#ibcon#end of sib2, iclass 20, count 0 2006.201.22:46:50.90#ibcon#*after write, iclass 20, count 0 2006.201.22:46:50.90#ibcon#*before return 0, iclass 20, count 0 2006.201.22:46:50.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:50.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.22:46:50.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.22:46:50.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.22:46:50.90$vck44/vblo=5,709.99 2006.201.22:46:50.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.22:46:50.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.22:46:50.90#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:50.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:50.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:50.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:50.90#ibcon#enter wrdev, iclass 22, count 0 2006.201.22:46:50.90#ibcon#first serial, iclass 22, count 0 2006.201.22:46:50.90#ibcon#enter sib2, iclass 22, count 0 2006.201.22:46:50.90#ibcon#flushed, iclass 22, count 0 2006.201.22:46:50.90#ibcon#about to write, iclass 22, count 0 2006.201.22:46:50.90#ibcon#wrote, iclass 22, count 0 2006.201.22:46:50.90#ibcon#about to read 3, iclass 22, count 0 2006.201.22:46:50.92#ibcon#read 3, iclass 22, count 0 2006.201.22:46:50.92#ibcon#about to read 4, iclass 22, count 0 2006.201.22:46:50.92#ibcon#read 4, iclass 22, count 0 2006.201.22:46:50.92#ibcon#about to read 5, iclass 22, count 0 2006.201.22:46:50.92#ibcon#read 5, iclass 22, count 0 2006.201.22:46:50.92#ibcon#about to read 6, iclass 22, count 0 2006.201.22:46:50.92#ibcon#read 6, iclass 22, count 0 2006.201.22:46:50.92#ibcon#end of sib2, iclass 22, count 0 2006.201.22:46:50.92#ibcon#*mode == 0, iclass 22, count 0 2006.201.22:46:50.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.22:46:50.92#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.22:46:50.92#ibcon#*before write, iclass 22, count 0 2006.201.22:46:50.92#ibcon#enter sib2, iclass 22, count 0 2006.201.22:46:50.92#ibcon#flushed, iclass 22, count 0 2006.201.22:46:50.92#ibcon#about to write, iclass 22, count 0 2006.201.22:46:50.92#ibcon#wrote, iclass 22, count 0 2006.201.22:46:50.92#ibcon#about to read 3, iclass 22, count 0 2006.201.22:46:50.96#ibcon#read 3, iclass 22, count 0 2006.201.22:46:50.96#ibcon#about to read 4, iclass 22, count 0 2006.201.22:46:50.96#ibcon#read 4, iclass 22, count 0 2006.201.22:46:50.96#ibcon#about to read 5, iclass 22, count 0 2006.201.22:46:50.96#ibcon#read 5, iclass 22, count 0 2006.201.22:46:50.96#ibcon#about to read 6, iclass 22, count 0 2006.201.22:46:50.96#ibcon#read 6, iclass 22, count 0 2006.201.22:46:50.96#ibcon#end of sib2, iclass 22, count 0 2006.201.22:46:50.96#ibcon#*after write, iclass 22, count 0 2006.201.22:46:50.96#ibcon#*before return 0, iclass 22, count 0 2006.201.22:46:50.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:50.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.22:46:50.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.22:46:50.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.22:46:50.96$vck44/vb=5,4 2006.201.22:46:50.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.22:46:50.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.22:46:50.96#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:50.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:51.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:51.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:51.02#ibcon#enter wrdev, iclass 24, count 2 2006.201.22:46:51.02#ibcon#first serial, iclass 24, count 2 2006.201.22:46:51.02#ibcon#enter sib2, iclass 24, count 2 2006.201.22:46:51.02#ibcon#flushed, iclass 24, count 2 2006.201.22:46:51.02#ibcon#about to write, iclass 24, count 2 2006.201.22:46:51.02#ibcon#wrote, iclass 24, count 2 2006.201.22:46:51.02#ibcon#about to read 3, iclass 24, count 2 2006.201.22:46:51.04#ibcon#read 3, iclass 24, count 2 2006.201.22:46:51.04#ibcon#about to read 4, iclass 24, count 2 2006.201.22:46:51.04#ibcon#read 4, iclass 24, count 2 2006.201.22:46:51.04#ibcon#about to read 5, iclass 24, count 2 2006.201.22:46:51.04#ibcon#read 5, iclass 24, count 2 2006.201.22:46:51.04#ibcon#about to read 6, iclass 24, count 2 2006.201.22:46:51.04#ibcon#read 6, iclass 24, count 2 2006.201.22:46:51.04#ibcon#end of sib2, iclass 24, count 2 2006.201.22:46:51.04#ibcon#*mode == 0, iclass 24, count 2 2006.201.22:46:51.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.22:46:51.04#ibcon#[27=AT05-04\r\n] 2006.201.22:46:51.04#ibcon#*before write, iclass 24, count 2 2006.201.22:46:51.04#ibcon#enter sib2, iclass 24, count 2 2006.201.22:46:51.04#ibcon#flushed, iclass 24, count 2 2006.201.22:46:51.04#ibcon#about to write, iclass 24, count 2 2006.201.22:46:51.04#ibcon#wrote, iclass 24, count 2 2006.201.22:46:51.04#ibcon#about to read 3, iclass 24, count 2 2006.201.22:46:51.07#ibcon#read 3, iclass 24, count 2 2006.201.22:46:51.07#ibcon#about to read 4, iclass 24, count 2 2006.201.22:46:51.07#ibcon#read 4, iclass 24, count 2 2006.201.22:46:51.07#ibcon#about to read 5, iclass 24, count 2 2006.201.22:46:51.07#ibcon#read 5, iclass 24, count 2 2006.201.22:46:51.07#ibcon#about to read 6, iclass 24, count 2 2006.201.22:46:51.07#ibcon#read 6, iclass 24, count 2 2006.201.22:46:51.07#ibcon#end of sib2, iclass 24, count 2 2006.201.22:46:51.07#ibcon#*after write, iclass 24, count 2 2006.201.22:46:51.07#ibcon#*before return 0, iclass 24, count 2 2006.201.22:46:51.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:51.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.22:46:51.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.22:46:51.07#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:51.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:51.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:51.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:51.19#ibcon#enter wrdev, iclass 24, count 0 2006.201.22:46:51.19#ibcon#first serial, iclass 24, count 0 2006.201.22:46:51.19#ibcon#enter sib2, iclass 24, count 0 2006.201.22:46:51.19#ibcon#flushed, iclass 24, count 0 2006.201.22:46:51.19#ibcon#about to write, iclass 24, count 0 2006.201.22:46:51.19#ibcon#wrote, iclass 24, count 0 2006.201.22:46:51.19#ibcon#about to read 3, iclass 24, count 0 2006.201.22:46:51.22#ibcon#read 3, iclass 24, count 0 2006.201.22:46:51.22#ibcon#about to read 4, iclass 24, count 0 2006.201.22:46:51.22#ibcon#read 4, iclass 24, count 0 2006.201.22:46:51.22#ibcon#about to read 5, iclass 24, count 0 2006.201.22:46:51.22#ibcon#read 5, iclass 24, count 0 2006.201.22:46:51.22#ibcon#about to read 6, iclass 24, count 0 2006.201.22:46:51.22#ibcon#read 6, iclass 24, count 0 2006.201.22:46:51.22#ibcon#end of sib2, iclass 24, count 0 2006.201.22:46:51.22#ibcon#*mode == 0, iclass 24, count 0 2006.201.22:46:51.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.22:46:51.22#ibcon#[27=USB\r\n] 2006.201.22:46:51.22#ibcon#*before write, iclass 24, count 0 2006.201.22:46:51.22#ibcon#enter sib2, iclass 24, count 0 2006.201.22:46:51.22#ibcon#flushed, iclass 24, count 0 2006.201.22:46:51.22#ibcon#about to write, iclass 24, count 0 2006.201.22:46:51.22#ibcon#wrote, iclass 24, count 0 2006.201.22:46:51.22#ibcon#about to read 3, iclass 24, count 0 2006.201.22:46:51.25#ibcon#read 3, iclass 24, count 0 2006.201.22:46:51.25#ibcon#about to read 4, iclass 24, count 0 2006.201.22:46:51.25#ibcon#read 4, iclass 24, count 0 2006.201.22:46:51.25#ibcon#about to read 5, iclass 24, count 0 2006.201.22:46:51.25#ibcon#read 5, iclass 24, count 0 2006.201.22:46:51.25#ibcon#about to read 6, iclass 24, count 0 2006.201.22:46:51.25#ibcon#read 6, iclass 24, count 0 2006.201.22:46:51.25#ibcon#end of sib2, iclass 24, count 0 2006.201.22:46:51.25#ibcon#*after write, iclass 24, count 0 2006.201.22:46:51.25#ibcon#*before return 0, iclass 24, count 0 2006.201.22:46:51.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:51.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.22:46:51.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.22:46:51.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.22:46:51.25$vck44/vblo=6,719.99 2006.201.22:46:51.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.22:46:51.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.22:46:51.25#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:51.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:51.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:51.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:51.25#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:46:51.25#ibcon#first serial, iclass 26, count 0 2006.201.22:46:51.25#ibcon#enter sib2, iclass 26, count 0 2006.201.22:46:51.25#ibcon#flushed, iclass 26, count 0 2006.201.22:46:51.25#ibcon#about to write, iclass 26, count 0 2006.201.22:46:51.25#ibcon#wrote, iclass 26, count 0 2006.201.22:46:51.25#ibcon#about to read 3, iclass 26, count 0 2006.201.22:46:51.27#ibcon#read 3, iclass 26, count 0 2006.201.22:46:51.27#ibcon#about to read 4, iclass 26, count 0 2006.201.22:46:51.27#ibcon#read 4, iclass 26, count 0 2006.201.22:46:51.27#ibcon#about to read 5, iclass 26, count 0 2006.201.22:46:51.27#ibcon#read 5, iclass 26, count 0 2006.201.22:46:51.27#ibcon#about to read 6, iclass 26, count 0 2006.201.22:46:51.27#ibcon#read 6, iclass 26, count 0 2006.201.22:46:51.27#ibcon#end of sib2, iclass 26, count 0 2006.201.22:46:51.27#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:46:51.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:46:51.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.22:46:51.27#ibcon#*before write, iclass 26, count 0 2006.201.22:46:51.27#ibcon#enter sib2, iclass 26, count 0 2006.201.22:46:51.27#ibcon#flushed, iclass 26, count 0 2006.201.22:46:51.27#ibcon#about to write, iclass 26, count 0 2006.201.22:46:51.27#ibcon#wrote, iclass 26, count 0 2006.201.22:46:51.27#ibcon#about to read 3, iclass 26, count 0 2006.201.22:46:51.31#ibcon#read 3, iclass 26, count 0 2006.201.22:46:51.31#ibcon#about to read 4, iclass 26, count 0 2006.201.22:46:51.31#ibcon#read 4, iclass 26, count 0 2006.201.22:46:51.31#ibcon#about to read 5, iclass 26, count 0 2006.201.22:46:51.31#ibcon#read 5, iclass 26, count 0 2006.201.22:46:51.31#ibcon#about to read 6, iclass 26, count 0 2006.201.22:46:51.31#ibcon#read 6, iclass 26, count 0 2006.201.22:46:51.31#ibcon#end of sib2, iclass 26, count 0 2006.201.22:46:51.31#ibcon#*after write, iclass 26, count 0 2006.201.22:46:51.31#ibcon#*before return 0, iclass 26, count 0 2006.201.22:46:51.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:51.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.22:46:51.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:46:51.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:46:51.31$vck44/vb=6,4 2006.201.22:46:51.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.22:46:51.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.22:46:51.31#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:51.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:51.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:51.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:51.37#ibcon#enter wrdev, iclass 28, count 2 2006.201.22:46:51.37#ibcon#first serial, iclass 28, count 2 2006.201.22:46:51.37#ibcon#enter sib2, iclass 28, count 2 2006.201.22:46:51.37#ibcon#flushed, iclass 28, count 2 2006.201.22:46:51.37#ibcon#about to write, iclass 28, count 2 2006.201.22:46:51.37#ibcon#wrote, iclass 28, count 2 2006.201.22:46:51.37#ibcon#about to read 3, iclass 28, count 2 2006.201.22:46:51.39#ibcon#read 3, iclass 28, count 2 2006.201.22:46:51.39#ibcon#about to read 4, iclass 28, count 2 2006.201.22:46:51.39#ibcon#read 4, iclass 28, count 2 2006.201.22:46:51.39#ibcon#about to read 5, iclass 28, count 2 2006.201.22:46:51.39#ibcon#read 5, iclass 28, count 2 2006.201.22:46:51.39#ibcon#about to read 6, iclass 28, count 2 2006.201.22:46:51.39#ibcon#read 6, iclass 28, count 2 2006.201.22:46:51.39#ibcon#end of sib2, iclass 28, count 2 2006.201.22:46:51.39#ibcon#*mode == 0, iclass 28, count 2 2006.201.22:46:51.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.22:46:51.39#ibcon#[27=AT06-04\r\n] 2006.201.22:46:51.39#ibcon#*before write, iclass 28, count 2 2006.201.22:46:51.39#ibcon#enter sib2, iclass 28, count 2 2006.201.22:46:51.39#ibcon#flushed, iclass 28, count 2 2006.201.22:46:51.39#ibcon#about to write, iclass 28, count 2 2006.201.22:46:51.39#ibcon#wrote, iclass 28, count 2 2006.201.22:46:51.39#ibcon#about to read 3, iclass 28, count 2 2006.201.22:46:51.42#ibcon#read 3, iclass 28, count 2 2006.201.22:46:51.42#ibcon#about to read 4, iclass 28, count 2 2006.201.22:46:51.42#ibcon#read 4, iclass 28, count 2 2006.201.22:46:51.42#ibcon#about to read 5, iclass 28, count 2 2006.201.22:46:51.42#ibcon#read 5, iclass 28, count 2 2006.201.22:46:51.42#ibcon#about to read 6, iclass 28, count 2 2006.201.22:46:51.42#ibcon#read 6, iclass 28, count 2 2006.201.22:46:51.42#ibcon#end of sib2, iclass 28, count 2 2006.201.22:46:51.42#ibcon#*after write, iclass 28, count 2 2006.201.22:46:51.42#ibcon#*before return 0, iclass 28, count 2 2006.201.22:46:51.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:51.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.22:46:51.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.22:46:51.42#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:51.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:51.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:51.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:51.54#ibcon#enter wrdev, iclass 28, count 0 2006.201.22:46:51.54#ibcon#first serial, iclass 28, count 0 2006.201.22:46:51.54#ibcon#enter sib2, iclass 28, count 0 2006.201.22:46:51.54#ibcon#flushed, iclass 28, count 0 2006.201.22:46:51.54#ibcon#about to write, iclass 28, count 0 2006.201.22:46:51.54#ibcon#wrote, iclass 28, count 0 2006.201.22:46:51.54#ibcon#about to read 3, iclass 28, count 0 2006.201.22:46:51.56#ibcon#read 3, iclass 28, count 0 2006.201.22:46:51.56#ibcon#about to read 4, iclass 28, count 0 2006.201.22:46:51.56#ibcon#read 4, iclass 28, count 0 2006.201.22:46:51.56#ibcon#about to read 5, iclass 28, count 0 2006.201.22:46:51.56#ibcon#read 5, iclass 28, count 0 2006.201.22:46:51.56#ibcon#about to read 6, iclass 28, count 0 2006.201.22:46:51.56#ibcon#read 6, iclass 28, count 0 2006.201.22:46:51.56#ibcon#end of sib2, iclass 28, count 0 2006.201.22:46:51.56#ibcon#*mode == 0, iclass 28, count 0 2006.201.22:46:51.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.22:46:51.56#ibcon#[27=USB\r\n] 2006.201.22:46:51.56#ibcon#*before write, iclass 28, count 0 2006.201.22:46:51.56#ibcon#enter sib2, iclass 28, count 0 2006.201.22:46:51.56#ibcon#flushed, iclass 28, count 0 2006.201.22:46:51.56#ibcon#about to write, iclass 28, count 0 2006.201.22:46:51.56#ibcon#wrote, iclass 28, count 0 2006.201.22:46:51.56#ibcon#about to read 3, iclass 28, count 0 2006.201.22:46:51.59#ibcon#read 3, iclass 28, count 0 2006.201.22:46:51.59#ibcon#about to read 4, iclass 28, count 0 2006.201.22:46:51.59#ibcon#read 4, iclass 28, count 0 2006.201.22:46:51.59#ibcon#about to read 5, iclass 28, count 0 2006.201.22:46:51.59#ibcon#read 5, iclass 28, count 0 2006.201.22:46:51.59#ibcon#about to read 6, iclass 28, count 0 2006.201.22:46:51.59#ibcon#read 6, iclass 28, count 0 2006.201.22:46:51.59#ibcon#end of sib2, iclass 28, count 0 2006.201.22:46:51.59#ibcon#*after write, iclass 28, count 0 2006.201.22:46:51.59#ibcon#*before return 0, iclass 28, count 0 2006.201.22:46:51.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:51.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.22:46:51.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.22:46:51.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.22:46:51.59$vck44/vblo=7,734.99 2006.201.22:46:51.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.22:46:51.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.22:46:51.59#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:51.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:51.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:51.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:51.59#ibcon#enter wrdev, iclass 30, count 0 2006.201.22:46:51.59#ibcon#first serial, iclass 30, count 0 2006.201.22:46:51.59#ibcon#enter sib2, iclass 30, count 0 2006.201.22:46:51.59#ibcon#flushed, iclass 30, count 0 2006.201.22:46:51.59#ibcon#about to write, iclass 30, count 0 2006.201.22:46:51.59#ibcon#wrote, iclass 30, count 0 2006.201.22:46:51.59#ibcon#about to read 3, iclass 30, count 0 2006.201.22:46:51.61#ibcon#read 3, iclass 30, count 0 2006.201.22:46:51.61#ibcon#about to read 4, iclass 30, count 0 2006.201.22:46:51.61#ibcon#read 4, iclass 30, count 0 2006.201.22:46:51.61#ibcon#about to read 5, iclass 30, count 0 2006.201.22:46:51.61#ibcon#read 5, iclass 30, count 0 2006.201.22:46:51.61#ibcon#about to read 6, iclass 30, count 0 2006.201.22:46:51.61#ibcon#read 6, iclass 30, count 0 2006.201.22:46:51.61#ibcon#end of sib2, iclass 30, count 0 2006.201.22:46:51.61#ibcon#*mode == 0, iclass 30, count 0 2006.201.22:46:51.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.22:46:51.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.22:46:51.61#ibcon#*before write, iclass 30, count 0 2006.201.22:46:51.61#ibcon#enter sib2, iclass 30, count 0 2006.201.22:46:51.61#ibcon#flushed, iclass 30, count 0 2006.201.22:46:51.61#ibcon#about to write, iclass 30, count 0 2006.201.22:46:51.61#ibcon#wrote, iclass 30, count 0 2006.201.22:46:51.61#ibcon#about to read 3, iclass 30, count 0 2006.201.22:46:51.65#ibcon#read 3, iclass 30, count 0 2006.201.22:46:51.65#ibcon#about to read 4, iclass 30, count 0 2006.201.22:46:51.65#ibcon#read 4, iclass 30, count 0 2006.201.22:46:51.65#ibcon#about to read 5, iclass 30, count 0 2006.201.22:46:51.65#ibcon#read 5, iclass 30, count 0 2006.201.22:46:51.65#ibcon#about to read 6, iclass 30, count 0 2006.201.22:46:51.65#ibcon#read 6, iclass 30, count 0 2006.201.22:46:51.65#ibcon#end of sib2, iclass 30, count 0 2006.201.22:46:51.65#ibcon#*after write, iclass 30, count 0 2006.201.22:46:51.65#ibcon#*before return 0, iclass 30, count 0 2006.201.22:46:51.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:51.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.22:46:51.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.22:46:51.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.22:46:51.65$vck44/vb=7,4 2006.201.22:46:51.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.22:46:51.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.22:46:51.65#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:51.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:51.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:51.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:51.71#ibcon#enter wrdev, iclass 32, count 2 2006.201.22:46:51.71#ibcon#first serial, iclass 32, count 2 2006.201.22:46:51.71#ibcon#enter sib2, iclass 32, count 2 2006.201.22:46:51.71#ibcon#flushed, iclass 32, count 2 2006.201.22:46:51.71#ibcon#about to write, iclass 32, count 2 2006.201.22:46:51.71#ibcon#wrote, iclass 32, count 2 2006.201.22:46:51.71#ibcon#about to read 3, iclass 32, count 2 2006.201.22:46:51.73#ibcon#read 3, iclass 32, count 2 2006.201.22:46:51.73#ibcon#about to read 4, iclass 32, count 2 2006.201.22:46:51.73#ibcon#read 4, iclass 32, count 2 2006.201.22:46:51.73#ibcon#about to read 5, iclass 32, count 2 2006.201.22:46:51.73#ibcon#read 5, iclass 32, count 2 2006.201.22:46:51.73#ibcon#about to read 6, iclass 32, count 2 2006.201.22:46:51.73#ibcon#read 6, iclass 32, count 2 2006.201.22:46:51.73#ibcon#end of sib2, iclass 32, count 2 2006.201.22:46:51.73#ibcon#*mode == 0, iclass 32, count 2 2006.201.22:46:51.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.22:46:51.73#ibcon#[27=AT07-04\r\n] 2006.201.22:46:51.73#ibcon#*before write, iclass 32, count 2 2006.201.22:46:51.73#ibcon#enter sib2, iclass 32, count 2 2006.201.22:46:51.73#ibcon#flushed, iclass 32, count 2 2006.201.22:46:51.73#ibcon#about to write, iclass 32, count 2 2006.201.22:46:51.73#ibcon#wrote, iclass 32, count 2 2006.201.22:46:51.73#ibcon#about to read 3, iclass 32, count 2 2006.201.22:46:51.76#ibcon#read 3, iclass 32, count 2 2006.201.22:46:51.76#ibcon#about to read 4, iclass 32, count 2 2006.201.22:46:51.76#ibcon#read 4, iclass 32, count 2 2006.201.22:46:51.76#ibcon#about to read 5, iclass 32, count 2 2006.201.22:46:51.76#ibcon#read 5, iclass 32, count 2 2006.201.22:46:51.76#ibcon#about to read 6, iclass 32, count 2 2006.201.22:46:51.76#ibcon#read 6, iclass 32, count 2 2006.201.22:46:51.76#ibcon#end of sib2, iclass 32, count 2 2006.201.22:46:51.76#ibcon#*after write, iclass 32, count 2 2006.201.22:46:51.76#ibcon#*before return 0, iclass 32, count 2 2006.201.22:46:51.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:51.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.22:46:51.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.22:46:51.76#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:51.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:51.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:51.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:51.88#ibcon#enter wrdev, iclass 32, count 0 2006.201.22:46:51.88#ibcon#first serial, iclass 32, count 0 2006.201.22:46:51.88#ibcon#enter sib2, iclass 32, count 0 2006.201.22:46:51.88#ibcon#flushed, iclass 32, count 0 2006.201.22:46:51.88#ibcon#about to write, iclass 32, count 0 2006.201.22:46:51.88#ibcon#wrote, iclass 32, count 0 2006.201.22:46:51.88#ibcon#about to read 3, iclass 32, count 0 2006.201.22:46:51.90#ibcon#read 3, iclass 32, count 0 2006.201.22:46:51.90#ibcon#about to read 4, iclass 32, count 0 2006.201.22:46:51.90#ibcon#read 4, iclass 32, count 0 2006.201.22:46:51.90#ibcon#about to read 5, iclass 32, count 0 2006.201.22:46:51.90#ibcon#read 5, iclass 32, count 0 2006.201.22:46:51.90#ibcon#about to read 6, iclass 32, count 0 2006.201.22:46:51.90#ibcon#read 6, iclass 32, count 0 2006.201.22:46:51.90#ibcon#end of sib2, iclass 32, count 0 2006.201.22:46:51.90#ibcon#*mode == 0, iclass 32, count 0 2006.201.22:46:51.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.22:46:51.90#ibcon#[27=USB\r\n] 2006.201.22:46:51.90#ibcon#*before write, iclass 32, count 0 2006.201.22:46:51.90#ibcon#enter sib2, iclass 32, count 0 2006.201.22:46:51.90#ibcon#flushed, iclass 32, count 0 2006.201.22:46:51.90#ibcon#about to write, iclass 32, count 0 2006.201.22:46:51.90#ibcon#wrote, iclass 32, count 0 2006.201.22:46:51.90#ibcon#about to read 3, iclass 32, count 0 2006.201.22:46:51.93#ibcon#read 3, iclass 32, count 0 2006.201.22:46:51.93#ibcon#about to read 4, iclass 32, count 0 2006.201.22:46:51.93#ibcon#read 4, iclass 32, count 0 2006.201.22:46:51.93#ibcon#about to read 5, iclass 32, count 0 2006.201.22:46:51.93#ibcon#read 5, iclass 32, count 0 2006.201.22:46:51.93#ibcon#about to read 6, iclass 32, count 0 2006.201.22:46:51.93#ibcon#read 6, iclass 32, count 0 2006.201.22:46:51.93#ibcon#end of sib2, iclass 32, count 0 2006.201.22:46:51.93#ibcon#*after write, iclass 32, count 0 2006.201.22:46:51.93#ibcon#*before return 0, iclass 32, count 0 2006.201.22:46:51.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:51.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.22:46:51.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.22:46:51.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.22:46:51.93$vck44/vblo=8,744.99 2006.201.22:46:51.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.22:46:51.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.22:46:51.93#ibcon#ireg 17 cls_cnt 0 2006.201.22:46:51.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:51.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:51.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:51.93#ibcon#enter wrdev, iclass 34, count 0 2006.201.22:46:51.93#ibcon#first serial, iclass 34, count 0 2006.201.22:46:51.93#ibcon#enter sib2, iclass 34, count 0 2006.201.22:46:51.93#ibcon#flushed, iclass 34, count 0 2006.201.22:46:51.93#ibcon#about to write, iclass 34, count 0 2006.201.22:46:51.93#ibcon#wrote, iclass 34, count 0 2006.201.22:46:51.93#ibcon#about to read 3, iclass 34, count 0 2006.201.22:46:51.95#ibcon#read 3, iclass 34, count 0 2006.201.22:46:51.95#ibcon#about to read 4, iclass 34, count 0 2006.201.22:46:51.95#ibcon#read 4, iclass 34, count 0 2006.201.22:46:51.95#ibcon#about to read 5, iclass 34, count 0 2006.201.22:46:51.95#ibcon#read 5, iclass 34, count 0 2006.201.22:46:51.95#ibcon#about to read 6, iclass 34, count 0 2006.201.22:46:51.95#ibcon#read 6, iclass 34, count 0 2006.201.22:46:51.95#ibcon#end of sib2, iclass 34, count 0 2006.201.22:46:51.95#ibcon#*mode == 0, iclass 34, count 0 2006.201.22:46:51.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.22:46:51.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.22:46:51.95#ibcon#*before write, iclass 34, count 0 2006.201.22:46:51.95#ibcon#enter sib2, iclass 34, count 0 2006.201.22:46:51.95#ibcon#flushed, iclass 34, count 0 2006.201.22:46:51.95#ibcon#about to write, iclass 34, count 0 2006.201.22:46:51.95#ibcon#wrote, iclass 34, count 0 2006.201.22:46:51.95#ibcon#about to read 3, iclass 34, count 0 2006.201.22:46:52.00#ibcon#read 3, iclass 34, count 0 2006.201.22:46:52.00#ibcon#about to read 4, iclass 34, count 0 2006.201.22:46:52.00#ibcon#read 4, iclass 34, count 0 2006.201.22:46:52.00#ibcon#about to read 5, iclass 34, count 0 2006.201.22:46:52.00#ibcon#read 5, iclass 34, count 0 2006.201.22:46:52.00#ibcon#about to read 6, iclass 34, count 0 2006.201.22:46:52.00#ibcon#read 6, iclass 34, count 0 2006.201.22:46:52.00#ibcon#end of sib2, iclass 34, count 0 2006.201.22:46:52.00#ibcon#*after write, iclass 34, count 0 2006.201.22:46:52.00#ibcon#*before return 0, iclass 34, count 0 2006.201.22:46:52.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:52.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:46:52.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.22:46:52.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.22:46:52.00$vck44/vb=8,4 2006.201.22:46:52.00#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.22:46:52.00#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.22:46:52.00#ibcon#ireg 11 cls_cnt 2 2006.201.22:46:52.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:52.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:52.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:52.05#ibcon#enter wrdev, iclass 36, count 2 2006.201.22:46:52.05#ibcon#first serial, iclass 36, count 2 2006.201.22:46:52.05#ibcon#enter sib2, iclass 36, count 2 2006.201.22:46:52.05#ibcon#flushed, iclass 36, count 2 2006.201.22:46:52.05#ibcon#about to write, iclass 36, count 2 2006.201.22:46:52.05#ibcon#wrote, iclass 36, count 2 2006.201.22:46:52.05#ibcon#about to read 3, iclass 36, count 2 2006.201.22:46:52.07#ibcon#read 3, iclass 36, count 2 2006.201.22:46:52.07#ibcon#about to read 4, iclass 36, count 2 2006.201.22:46:52.07#ibcon#read 4, iclass 36, count 2 2006.201.22:46:52.07#ibcon#about to read 5, iclass 36, count 2 2006.201.22:46:52.07#ibcon#read 5, iclass 36, count 2 2006.201.22:46:52.07#ibcon#about to read 6, iclass 36, count 2 2006.201.22:46:52.07#ibcon#read 6, iclass 36, count 2 2006.201.22:46:52.07#ibcon#end of sib2, iclass 36, count 2 2006.201.22:46:52.07#ibcon#*mode == 0, iclass 36, count 2 2006.201.22:46:52.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.22:46:52.07#ibcon#[27=AT08-04\r\n] 2006.201.22:46:52.07#ibcon#*before write, iclass 36, count 2 2006.201.22:46:52.07#ibcon#enter sib2, iclass 36, count 2 2006.201.22:46:52.07#ibcon#flushed, iclass 36, count 2 2006.201.22:46:52.07#ibcon#about to write, iclass 36, count 2 2006.201.22:46:52.07#ibcon#wrote, iclass 36, count 2 2006.201.22:46:52.07#ibcon#about to read 3, iclass 36, count 2 2006.201.22:46:52.10#ibcon#read 3, iclass 36, count 2 2006.201.22:46:52.10#ibcon#about to read 4, iclass 36, count 2 2006.201.22:46:52.10#ibcon#read 4, iclass 36, count 2 2006.201.22:46:52.10#ibcon#about to read 5, iclass 36, count 2 2006.201.22:46:52.10#ibcon#read 5, iclass 36, count 2 2006.201.22:46:52.10#ibcon#about to read 6, iclass 36, count 2 2006.201.22:46:52.10#ibcon#read 6, iclass 36, count 2 2006.201.22:46:52.10#ibcon#end of sib2, iclass 36, count 2 2006.201.22:46:52.10#ibcon#*after write, iclass 36, count 2 2006.201.22:46:52.10#ibcon#*before return 0, iclass 36, count 2 2006.201.22:46:52.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:52.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.22:46:52.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.22:46:52.10#ibcon#ireg 7 cls_cnt 0 2006.201.22:46:52.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:52.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:52.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:52.22#ibcon#enter wrdev, iclass 36, count 0 2006.201.22:46:52.22#ibcon#first serial, iclass 36, count 0 2006.201.22:46:52.22#ibcon#enter sib2, iclass 36, count 0 2006.201.22:46:52.22#ibcon#flushed, iclass 36, count 0 2006.201.22:46:52.22#ibcon#about to write, iclass 36, count 0 2006.201.22:46:52.22#ibcon#wrote, iclass 36, count 0 2006.201.22:46:52.22#ibcon#about to read 3, iclass 36, count 0 2006.201.22:46:52.24#ibcon#read 3, iclass 36, count 0 2006.201.22:46:52.24#ibcon#about to read 4, iclass 36, count 0 2006.201.22:46:52.24#ibcon#read 4, iclass 36, count 0 2006.201.22:46:52.24#ibcon#about to read 5, iclass 36, count 0 2006.201.22:46:52.24#ibcon#read 5, iclass 36, count 0 2006.201.22:46:52.24#ibcon#about to read 6, iclass 36, count 0 2006.201.22:46:52.24#ibcon#read 6, iclass 36, count 0 2006.201.22:46:52.24#ibcon#end of sib2, iclass 36, count 0 2006.201.22:46:52.24#ibcon#*mode == 0, iclass 36, count 0 2006.201.22:46:52.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.22:46:52.24#ibcon#[27=USB\r\n] 2006.201.22:46:52.24#ibcon#*before write, iclass 36, count 0 2006.201.22:46:52.24#ibcon#enter sib2, iclass 36, count 0 2006.201.22:46:52.24#ibcon#flushed, iclass 36, count 0 2006.201.22:46:52.24#ibcon#about to write, iclass 36, count 0 2006.201.22:46:52.24#ibcon#wrote, iclass 36, count 0 2006.201.22:46:52.24#ibcon#about to read 3, iclass 36, count 0 2006.201.22:46:52.27#ibcon#read 3, iclass 36, count 0 2006.201.22:46:52.27#ibcon#about to read 4, iclass 36, count 0 2006.201.22:46:52.27#ibcon#read 4, iclass 36, count 0 2006.201.22:46:52.27#ibcon#about to read 5, iclass 36, count 0 2006.201.22:46:52.27#ibcon#read 5, iclass 36, count 0 2006.201.22:46:52.27#ibcon#about to read 6, iclass 36, count 0 2006.201.22:46:52.27#ibcon#read 6, iclass 36, count 0 2006.201.22:46:52.27#ibcon#end of sib2, iclass 36, count 0 2006.201.22:46:52.27#ibcon#*after write, iclass 36, count 0 2006.201.22:46:52.27#ibcon#*before return 0, iclass 36, count 0 2006.201.22:46:52.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:52.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.22:46:52.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.22:46:52.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.22:46:52.27$vck44/vabw=wide 2006.201.22:46:52.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.22:46:52.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.22:46:52.27#ibcon#ireg 8 cls_cnt 0 2006.201.22:46:52.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:52.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:52.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:52.27#ibcon#enter wrdev, iclass 38, count 0 2006.201.22:46:52.27#ibcon#first serial, iclass 38, count 0 2006.201.22:46:52.27#ibcon#enter sib2, iclass 38, count 0 2006.201.22:46:52.27#ibcon#flushed, iclass 38, count 0 2006.201.22:46:52.27#ibcon#about to write, iclass 38, count 0 2006.201.22:46:52.27#ibcon#wrote, iclass 38, count 0 2006.201.22:46:52.27#ibcon#about to read 3, iclass 38, count 0 2006.201.22:46:52.29#ibcon#read 3, iclass 38, count 0 2006.201.22:46:52.29#ibcon#about to read 4, iclass 38, count 0 2006.201.22:46:52.29#ibcon#read 4, iclass 38, count 0 2006.201.22:46:52.29#ibcon#about to read 5, iclass 38, count 0 2006.201.22:46:52.29#ibcon#read 5, iclass 38, count 0 2006.201.22:46:52.29#ibcon#about to read 6, iclass 38, count 0 2006.201.22:46:52.29#ibcon#read 6, iclass 38, count 0 2006.201.22:46:52.29#ibcon#end of sib2, iclass 38, count 0 2006.201.22:46:52.29#ibcon#*mode == 0, iclass 38, count 0 2006.201.22:46:52.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.22:46:52.29#ibcon#[25=BW32\r\n] 2006.201.22:46:52.29#ibcon#*before write, iclass 38, count 0 2006.201.22:46:52.29#ibcon#enter sib2, iclass 38, count 0 2006.201.22:46:52.29#ibcon#flushed, iclass 38, count 0 2006.201.22:46:52.29#ibcon#about to write, iclass 38, count 0 2006.201.22:46:52.29#ibcon#wrote, iclass 38, count 0 2006.201.22:46:52.29#ibcon#about to read 3, iclass 38, count 0 2006.201.22:46:52.33#ibcon#read 3, iclass 38, count 0 2006.201.22:46:52.33#ibcon#about to read 4, iclass 38, count 0 2006.201.22:46:52.33#ibcon#read 4, iclass 38, count 0 2006.201.22:46:52.33#ibcon#about to read 5, iclass 38, count 0 2006.201.22:46:52.33#ibcon#read 5, iclass 38, count 0 2006.201.22:46:52.33#ibcon#about to read 6, iclass 38, count 0 2006.201.22:46:52.33#ibcon#read 6, iclass 38, count 0 2006.201.22:46:52.33#ibcon#end of sib2, iclass 38, count 0 2006.201.22:46:52.33#ibcon#*after write, iclass 38, count 0 2006.201.22:46:52.33#ibcon#*before return 0, iclass 38, count 0 2006.201.22:46:52.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:52.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.22:46:52.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.22:46:52.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.22:46:52.33$vck44/vbbw=wide 2006.201.22:46:52.33#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.22:46:52.33#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.22:46:52.33#ibcon#ireg 8 cls_cnt 0 2006.201.22:46:52.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:46:52.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:46:52.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:46:52.39#ibcon#enter wrdev, iclass 40, count 0 2006.201.22:46:52.39#ibcon#first serial, iclass 40, count 0 2006.201.22:46:52.39#ibcon#enter sib2, iclass 40, count 0 2006.201.22:46:52.39#ibcon#flushed, iclass 40, count 0 2006.201.22:46:52.39#ibcon#about to write, iclass 40, count 0 2006.201.22:46:52.39#ibcon#wrote, iclass 40, count 0 2006.201.22:46:52.39#ibcon#about to read 3, iclass 40, count 0 2006.201.22:46:52.41#ibcon#read 3, iclass 40, count 0 2006.201.22:46:52.41#ibcon#about to read 4, iclass 40, count 0 2006.201.22:46:52.41#ibcon#read 4, iclass 40, count 0 2006.201.22:46:52.41#ibcon#about to read 5, iclass 40, count 0 2006.201.22:46:52.41#ibcon#read 5, iclass 40, count 0 2006.201.22:46:52.41#ibcon#about to read 6, iclass 40, count 0 2006.201.22:46:52.41#ibcon#read 6, iclass 40, count 0 2006.201.22:46:52.41#ibcon#end of sib2, iclass 40, count 0 2006.201.22:46:52.41#ibcon#*mode == 0, iclass 40, count 0 2006.201.22:46:52.41#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.22:46:52.41#ibcon#[27=BW32\r\n] 2006.201.22:46:52.41#ibcon#*before write, iclass 40, count 0 2006.201.22:46:52.41#ibcon#enter sib2, iclass 40, count 0 2006.201.22:46:52.41#ibcon#flushed, iclass 40, count 0 2006.201.22:46:52.41#ibcon#about to write, iclass 40, count 0 2006.201.22:46:52.41#ibcon#wrote, iclass 40, count 0 2006.201.22:46:52.41#ibcon#about to read 3, iclass 40, count 0 2006.201.22:46:52.44#ibcon#read 3, iclass 40, count 0 2006.201.22:46:52.44#ibcon#about to read 4, iclass 40, count 0 2006.201.22:46:52.44#ibcon#read 4, iclass 40, count 0 2006.201.22:46:52.44#ibcon#about to read 5, iclass 40, count 0 2006.201.22:46:52.44#ibcon#read 5, iclass 40, count 0 2006.201.22:46:52.44#ibcon#about to read 6, iclass 40, count 0 2006.201.22:46:52.44#ibcon#read 6, iclass 40, count 0 2006.201.22:46:52.44#ibcon#end of sib2, iclass 40, count 0 2006.201.22:46:52.44#ibcon#*after write, iclass 40, count 0 2006.201.22:46:52.44#ibcon#*before return 0, iclass 40, count 0 2006.201.22:46:52.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:46:52.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:46:52.44#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.22:46:52.44#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.22:46:52.44$setupk4/ifdk4 2006.201.22:46:52.44$ifdk4/lo= 2006.201.22:46:52.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.22:46:52.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.22:46:52.44$ifdk4/patch= 2006.201.22:46:52.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.22:46:52.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.22:46:52.44$setupk4/!*+20s 2006.201.22:46:55.32#abcon#<5=/04 2.0 4.4 20.031001001.3\r\n> 2006.201.22:46:55.34#abcon#{5=INTERFACE CLEAR} 2006.201.22:46:55.40#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:47:05.49#abcon#<5=/04 2.0 4.4 20.031001001.3\r\n> 2006.201.22:47:05.51#abcon#{5=INTERFACE CLEAR} 2006.201.22:47:05.57#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:47:06.91$setupk4/"tpicd 2006.201.22:47:06.91$setupk4/echo=off 2006.201.22:47:06.91$setupk4/xlog=off 2006.201.22:47:06.91:!2006.201.22:50:38 2006.201.22:47:27.14#trakl#Source acquired 2006.201.22:47:27.14#flagr#flagr/antenna,acquired 2006.201.22:50:38.00:preob 2006.201.22:50:38.13/onsource/TRACKING 2006.201.22:50:38.13:!2006.201.22:50:48 2006.201.22:50:48.00:"tape 2006.201.22:50:48.00:"st=record 2006.201.22:50:48.00:data_valid=on 2006.201.22:50:48.00:midob 2006.201.22:50:48.13/onsource/TRACKING 2006.201.22:50:48.13/wx/20.04,1001.3,100 2006.201.22:50:48.34/cable/+6.4814E-03 2006.201.22:50:49.43/va/01,08,usb,yes,57,61 2006.201.22:50:49.43/va/02,07,usb,yes,62,63 2006.201.22:50:49.43/va/03,08,usb,yes,56,59 2006.201.22:50:49.43/va/04,07,usb,yes,64,67 2006.201.22:50:49.43/va/05,04,usb,yes,57,58 2006.201.22:50:49.43/va/06,05,usb,yes,57,57 2006.201.22:50:49.43/va/07,05,usb,yes,56,58 2006.201.22:50:49.43/va/08,04,usb,yes,56,65 2006.201.22:50:49.66/valo/01,524.99,yes,locked 2006.201.22:50:49.66/valo/02,534.99,yes,locked 2006.201.22:50:49.66/valo/03,564.99,yes,locked 2006.201.22:50:49.66/valo/04,624.99,yes,locked 2006.201.22:50:49.66/valo/05,734.99,yes,locked 2006.201.22:50:49.66/valo/06,814.99,yes,locked 2006.201.22:50:49.66/valo/07,864.99,yes,locked 2006.201.22:50:49.66/valo/08,884.99,yes,locked 2006.201.22:50:50.75/vb/01,04,usb,yes,32,30 2006.201.22:50:50.75/vb/02,05,usb,yes,30,30 2006.201.22:50:50.75/vb/03,04,usb,yes,31,34 2006.201.22:50:50.75/vb/04,05,usb,yes,32,30 2006.201.22:50:50.75/vb/05,04,usb,yes,28,31 2006.201.22:50:50.75/vb/06,04,usb,yes,33,29 2006.201.22:50:50.75/vb/07,04,usb,yes,33,33 2006.201.22:50:50.75/vb/08,04,usb,yes,30,33 2006.201.22:50:50.99/vblo/01,629.99,yes,locked 2006.201.22:50:50.99/vblo/02,634.99,yes,locked 2006.201.22:50:50.99/vblo/03,649.99,yes,locked 2006.201.22:50:50.99/vblo/04,679.99,yes,locked 2006.201.22:50:50.99/vblo/05,709.99,yes,locked 2006.201.22:50:50.99/vblo/06,719.99,yes,locked 2006.201.22:50:50.99/vblo/07,734.99,yes,locked 2006.201.22:50:50.99/vblo/08,744.99,yes,locked 2006.201.22:50:51.14/vabw/8 2006.201.22:50:51.29/vbbw/8 2006.201.22:50:51.38/xfe/off,on,15.2 2006.201.22:50:51.77/ifatt/23,28,28,28 2006.201.22:50:52.07/fmout-gps/S +4.53E-07 2006.201.22:50:52.11:!2006.201.22:52:18 2006.201.22:52:18.00:data_valid=off 2006.201.22:52:18.00:"et 2006.201.22:52:18.00:!+3s 2006.201.22:52:21.02:"tape 2006.201.22:52:21.02:postob 2006.201.22:52:21.14/cable/+6.4847E-03 2006.201.22:52:21.14/wx/20.04,1001.4,100 2006.201.22:52:21.22/fmout-gps/S +4.51E-07 2006.201.22:52:21.22:scan_name=201-2254,jd0607,40 2006.201.22:52:21.22:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.201.22:52:22.14#flagr#flagr/antenna,new-source 2006.201.22:52:22.14:checkk5 2006.201.22:52:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.201.22:52:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.201.22:52:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.22:52:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.201.22:52:24.02/chk_obsdata//k5ts1/T2012250??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.22:52:24.38/chk_obsdata//k5ts2/T2012250??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.22:52:24.76/chk_obsdata//k5ts3/T2012250??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.22:52:25.12/chk_obsdata//k5ts4/T2012250??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.22:52:25.81/k5log//k5ts1_log_newline 2006.201.22:52:26.51/k5log//k5ts2_log_newline 2006.201.22:52:27.21/k5log//k5ts3_log_newline 2006.201.22:52:27.89/k5log//k5ts4_log_newline 2006.201.22:52:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.22:52:27.92:setupk4=1 2006.201.22:52:27.92$setupk4/echo=on 2006.201.22:52:27.92$setupk4/pcalon 2006.201.22:52:27.92$pcalon/"no phase cal control is implemented here 2006.201.22:52:27.92$setupk4/"tpicd=stop 2006.201.22:52:27.92$setupk4/"rec=synch_on 2006.201.22:52:27.92$setupk4/"rec_mode=128 2006.201.22:52:27.92$setupk4/!* 2006.201.22:52:27.92$setupk4/recpk4 2006.201.22:52:27.92$recpk4/recpatch= 2006.201.22:52:27.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.22:52:27.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.22:52:27.92$setupk4/vck44 2006.201.22:52:27.92$vck44/valo=1,524.99 2006.201.22:52:27.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.22:52:27.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.22:52:27.92#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:27.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:27.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:27.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:27.92#ibcon#enter wrdev, iclass 33, count 0 2006.201.22:52:27.92#ibcon#first serial, iclass 33, count 0 2006.201.22:52:27.92#ibcon#enter sib2, iclass 33, count 0 2006.201.22:52:27.92#ibcon#flushed, iclass 33, count 0 2006.201.22:52:27.92#ibcon#about to write, iclass 33, count 0 2006.201.22:52:27.92#ibcon#wrote, iclass 33, count 0 2006.201.22:52:27.92#ibcon#about to read 3, iclass 33, count 0 2006.201.22:52:27.94#ibcon#read 3, iclass 33, count 0 2006.201.22:52:27.94#ibcon#about to read 4, iclass 33, count 0 2006.201.22:52:27.94#ibcon#read 4, iclass 33, count 0 2006.201.22:52:27.94#ibcon#about to read 5, iclass 33, count 0 2006.201.22:52:27.94#ibcon#read 5, iclass 33, count 0 2006.201.22:52:27.94#ibcon#about to read 6, iclass 33, count 0 2006.201.22:52:27.94#ibcon#read 6, iclass 33, count 0 2006.201.22:52:27.94#ibcon#end of sib2, iclass 33, count 0 2006.201.22:52:27.94#ibcon#*mode == 0, iclass 33, count 0 2006.201.22:52:27.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.22:52:27.94#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.22:52:27.94#ibcon#*before write, iclass 33, count 0 2006.201.22:52:27.94#ibcon#enter sib2, iclass 33, count 0 2006.201.22:52:27.94#ibcon#flushed, iclass 33, count 0 2006.201.22:52:27.94#ibcon#about to write, iclass 33, count 0 2006.201.22:52:27.94#ibcon#wrote, iclass 33, count 0 2006.201.22:52:27.94#ibcon#about to read 3, iclass 33, count 0 2006.201.22:52:27.99#ibcon#read 3, iclass 33, count 0 2006.201.22:52:27.99#ibcon#about to read 4, iclass 33, count 0 2006.201.22:52:27.99#ibcon#read 4, iclass 33, count 0 2006.201.22:52:27.99#ibcon#about to read 5, iclass 33, count 0 2006.201.22:52:27.99#ibcon#read 5, iclass 33, count 0 2006.201.22:52:27.99#ibcon#about to read 6, iclass 33, count 0 2006.201.22:52:27.99#ibcon#read 6, iclass 33, count 0 2006.201.22:52:27.99#ibcon#end of sib2, iclass 33, count 0 2006.201.22:52:27.99#ibcon#*after write, iclass 33, count 0 2006.201.22:52:27.99#ibcon#*before return 0, iclass 33, count 0 2006.201.22:52:27.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:27.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:27.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.22:52:27.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.22:52:27.99$vck44/va=1,8 2006.201.22:52:27.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.22:52:27.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.22:52:27.99#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:27.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:27.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:27.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:27.99#ibcon#enter wrdev, iclass 35, count 2 2006.201.22:52:27.99#ibcon#first serial, iclass 35, count 2 2006.201.22:52:27.99#ibcon#enter sib2, iclass 35, count 2 2006.201.22:52:27.99#ibcon#flushed, iclass 35, count 2 2006.201.22:52:27.99#ibcon#about to write, iclass 35, count 2 2006.201.22:52:27.99#ibcon#wrote, iclass 35, count 2 2006.201.22:52:27.99#ibcon#about to read 3, iclass 35, count 2 2006.201.22:52:28.01#ibcon#read 3, iclass 35, count 2 2006.201.22:52:28.01#ibcon#about to read 4, iclass 35, count 2 2006.201.22:52:28.01#ibcon#read 4, iclass 35, count 2 2006.201.22:52:28.01#ibcon#about to read 5, iclass 35, count 2 2006.201.22:52:28.01#ibcon#read 5, iclass 35, count 2 2006.201.22:52:28.01#ibcon#about to read 6, iclass 35, count 2 2006.201.22:52:28.01#ibcon#read 6, iclass 35, count 2 2006.201.22:52:28.01#ibcon#end of sib2, iclass 35, count 2 2006.201.22:52:28.01#ibcon#*mode == 0, iclass 35, count 2 2006.201.22:52:28.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.22:52:28.01#ibcon#[25=AT01-08\r\n] 2006.201.22:52:28.01#ibcon#*before write, iclass 35, count 2 2006.201.22:52:28.01#ibcon#enter sib2, iclass 35, count 2 2006.201.22:52:28.01#ibcon#flushed, iclass 35, count 2 2006.201.22:52:28.01#ibcon#about to write, iclass 35, count 2 2006.201.22:52:28.01#ibcon#wrote, iclass 35, count 2 2006.201.22:52:28.01#ibcon#about to read 3, iclass 35, count 2 2006.201.22:52:28.04#ibcon#read 3, iclass 35, count 2 2006.201.22:52:28.04#ibcon#about to read 4, iclass 35, count 2 2006.201.22:52:28.04#ibcon#read 4, iclass 35, count 2 2006.201.22:52:28.04#ibcon#about to read 5, iclass 35, count 2 2006.201.22:52:28.04#ibcon#read 5, iclass 35, count 2 2006.201.22:52:28.04#ibcon#about to read 6, iclass 35, count 2 2006.201.22:52:28.04#ibcon#read 6, iclass 35, count 2 2006.201.22:52:28.04#ibcon#end of sib2, iclass 35, count 2 2006.201.22:52:28.04#ibcon#*after write, iclass 35, count 2 2006.201.22:52:28.04#ibcon#*before return 0, iclass 35, count 2 2006.201.22:52:28.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:28.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:28.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.22:52:28.04#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:28.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:28.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:28.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:28.16#ibcon#enter wrdev, iclass 35, count 0 2006.201.22:52:28.16#ibcon#first serial, iclass 35, count 0 2006.201.22:52:28.16#ibcon#enter sib2, iclass 35, count 0 2006.201.22:52:28.16#ibcon#flushed, iclass 35, count 0 2006.201.22:52:28.16#ibcon#about to write, iclass 35, count 0 2006.201.22:52:28.16#ibcon#wrote, iclass 35, count 0 2006.201.22:52:28.16#ibcon#about to read 3, iclass 35, count 0 2006.201.22:52:28.18#ibcon#read 3, iclass 35, count 0 2006.201.22:52:28.18#ibcon#about to read 4, iclass 35, count 0 2006.201.22:52:28.18#ibcon#read 4, iclass 35, count 0 2006.201.22:52:28.18#ibcon#about to read 5, iclass 35, count 0 2006.201.22:52:28.18#ibcon#read 5, iclass 35, count 0 2006.201.22:52:28.18#ibcon#about to read 6, iclass 35, count 0 2006.201.22:52:28.18#ibcon#read 6, iclass 35, count 0 2006.201.22:52:28.18#ibcon#end of sib2, iclass 35, count 0 2006.201.22:52:28.18#ibcon#*mode == 0, iclass 35, count 0 2006.201.22:52:28.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.22:52:28.18#ibcon#[25=USB\r\n] 2006.201.22:52:28.18#ibcon#*before write, iclass 35, count 0 2006.201.22:52:28.18#ibcon#enter sib2, iclass 35, count 0 2006.201.22:52:28.18#ibcon#flushed, iclass 35, count 0 2006.201.22:52:28.18#ibcon#about to write, iclass 35, count 0 2006.201.22:52:28.18#ibcon#wrote, iclass 35, count 0 2006.201.22:52:28.18#ibcon#about to read 3, iclass 35, count 0 2006.201.22:52:28.21#ibcon#read 3, iclass 35, count 0 2006.201.22:52:28.21#ibcon#about to read 4, iclass 35, count 0 2006.201.22:52:28.21#ibcon#read 4, iclass 35, count 0 2006.201.22:52:28.21#ibcon#about to read 5, iclass 35, count 0 2006.201.22:52:28.21#ibcon#read 5, iclass 35, count 0 2006.201.22:52:28.21#ibcon#about to read 6, iclass 35, count 0 2006.201.22:52:28.21#ibcon#read 6, iclass 35, count 0 2006.201.22:52:28.21#ibcon#end of sib2, iclass 35, count 0 2006.201.22:52:28.21#ibcon#*after write, iclass 35, count 0 2006.201.22:52:28.21#ibcon#*before return 0, iclass 35, count 0 2006.201.22:52:28.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:28.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:28.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.22:52:28.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.22:52:28.21$vck44/valo=2,534.99 2006.201.22:52:28.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.22:52:28.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.22:52:28.21#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:28.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:52:28.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:52:28.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:52:28.21#ibcon#enter wrdev, iclass 37, count 0 2006.201.22:52:28.21#ibcon#first serial, iclass 37, count 0 2006.201.22:52:28.21#ibcon#enter sib2, iclass 37, count 0 2006.201.22:52:28.21#ibcon#flushed, iclass 37, count 0 2006.201.22:52:28.21#ibcon#about to write, iclass 37, count 0 2006.201.22:52:28.21#ibcon#wrote, iclass 37, count 0 2006.201.22:52:28.21#ibcon#about to read 3, iclass 37, count 0 2006.201.22:52:28.23#ibcon#read 3, iclass 37, count 0 2006.201.22:52:28.23#ibcon#about to read 4, iclass 37, count 0 2006.201.22:52:28.23#ibcon#read 4, iclass 37, count 0 2006.201.22:52:28.23#ibcon#about to read 5, iclass 37, count 0 2006.201.22:52:28.23#ibcon#read 5, iclass 37, count 0 2006.201.22:52:28.23#ibcon#about to read 6, iclass 37, count 0 2006.201.22:52:28.23#ibcon#read 6, iclass 37, count 0 2006.201.22:52:28.23#ibcon#end of sib2, iclass 37, count 0 2006.201.22:52:28.23#ibcon#*mode == 0, iclass 37, count 0 2006.201.22:52:28.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.22:52:28.23#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.22:52:28.23#ibcon#*before write, iclass 37, count 0 2006.201.22:52:28.23#ibcon#enter sib2, iclass 37, count 0 2006.201.22:52:28.23#ibcon#flushed, iclass 37, count 0 2006.201.22:52:28.23#ibcon#about to write, iclass 37, count 0 2006.201.22:52:28.23#ibcon#wrote, iclass 37, count 0 2006.201.22:52:28.23#ibcon#about to read 3, iclass 37, count 0 2006.201.22:52:28.27#ibcon#read 3, iclass 37, count 0 2006.201.22:52:28.27#ibcon#about to read 4, iclass 37, count 0 2006.201.22:52:28.27#ibcon#read 4, iclass 37, count 0 2006.201.22:52:28.27#ibcon#about to read 5, iclass 37, count 0 2006.201.22:52:28.27#ibcon#read 5, iclass 37, count 0 2006.201.22:52:28.27#ibcon#about to read 6, iclass 37, count 0 2006.201.22:52:28.27#ibcon#read 6, iclass 37, count 0 2006.201.22:52:28.27#ibcon#end of sib2, iclass 37, count 0 2006.201.22:52:28.27#ibcon#*after write, iclass 37, count 0 2006.201.22:52:28.27#ibcon#*before return 0, iclass 37, count 0 2006.201.22:52:28.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:52:28.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.22:52:28.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.22:52:28.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.22:52:28.27$vck44/va=2,7 2006.201.22:52:28.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.22:52:28.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.22:52:28.27#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:28.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:52:28.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:52:28.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:52:28.33#ibcon#enter wrdev, iclass 39, count 2 2006.201.22:52:28.33#ibcon#first serial, iclass 39, count 2 2006.201.22:52:28.33#ibcon#enter sib2, iclass 39, count 2 2006.201.22:52:28.33#ibcon#flushed, iclass 39, count 2 2006.201.22:52:28.33#ibcon#about to write, iclass 39, count 2 2006.201.22:52:28.33#ibcon#wrote, iclass 39, count 2 2006.201.22:52:28.33#ibcon#about to read 3, iclass 39, count 2 2006.201.22:52:28.35#ibcon#read 3, iclass 39, count 2 2006.201.22:52:28.35#ibcon#about to read 4, iclass 39, count 2 2006.201.22:52:28.35#ibcon#read 4, iclass 39, count 2 2006.201.22:52:28.35#ibcon#about to read 5, iclass 39, count 2 2006.201.22:52:28.35#ibcon#read 5, iclass 39, count 2 2006.201.22:52:28.35#ibcon#about to read 6, iclass 39, count 2 2006.201.22:52:28.35#ibcon#read 6, iclass 39, count 2 2006.201.22:52:28.35#ibcon#end of sib2, iclass 39, count 2 2006.201.22:52:28.35#ibcon#*mode == 0, iclass 39, count 2 2006.201.22:52:28.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.22:52:28.35#ibcon#[25=AT02-07\r\n] 2006.201.22:52:28.35#ibcon#*before write, iclass 39, count 2 2006.201.22:52:28.35#ibcon#enter sib2, iclass 39, count 2 2006.201.22:52:28.35#ibcon#flushed, iclass 39, count 2 2006.201.22:52:28.35#ibcon#about to write, iclass 39, count 2 2006.201.22:52:28.35#ibcon#wrote, iclass 39, count 2 2006.201.22:52:28.35#ibcon#about to read 3, iclass 39, count 2 2006.201.22:52:28.38#ibcon#read 3, iclass 39, count 2 2006.201.22:52:28.38#ibcon#about to read 4, iclass 39, count 2 2006.201.22:52:28.38#ibcon#read 4, iclass 39, count 2 2006.201.22:52:28.38#ibcon#about to read 5, iclass 39, count 2 2006.201.22:52:28.38#ibcon#read 5, iclass 39, count 2 2006.201.22:52:28.38#ibcon#about to read 6, iclass 39, count 2 2006.201.22:52:28.38#ibcon#read 6, iclass 39, count 2 2006.201.22:52:28.38#ibcon#end of sib2, iclass 39, count 2 2006.201.22:52:28.38#ibcon#*after write, iclass 39, count 2 2006.201.22:52:28.38#ibcon#*before return 0, iclass 39, count 2 2006.201.22:52:28.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:52:28.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.22:52:28.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.22:52:28.38#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:28.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:52:28.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:52:28.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:52:28.50#ibcon#enter wrdev, iclass 39, count 0 2006.201.22:52:28.50#ibcon#first serial, iclass 39, count 0 2006.201.22:52:28.50#ibcon#enter sib2, iclass 39, count 0 2006.201.22:52:28.50#ibcon#flushed, iclass 39, count 0 2006.201.22:52:28.50#ibcon#about to write, iclass 39, count 0 2006.201.22:52:28.50#ibcon#wrote, iclass 39, count 0 2006.201.22:52:28.50#ibcon#about to read 3, iclass 39, count 0 2006.201.22:52:28.52#ibcon#read 3, iclass 39, count 0 2006.201.22:52:28.52#ibcon#about to read 4, iclass 39, count 0 2006.201.22:52:28.52#ibcon#read 4, iclass 39, count 0 2006.201.22:52:28.52#ibcon#about to read 5, iclass 39, count 0 2006.201.22:52:28.52#ibcon#read 5, iclass 39, count 0 2006.201.22:52:28.52#ibcon#about to read 6, iclass 39, count 0 2006.201.22:52:28.52#ibcon#read 6, iclass 39, count 0 2006.201.22:52:28.52#ibcon#end of sib2, iclass 39, count 0 2006.201.22:52:28.52#ibcon#*mode == 0, iclass 39, count 0 2006.201.22:52:28.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.22:52:28.52#ibcon#[25=USB\r\n] 2006.201.22:52:28.52#ibcon#*before write, iclass 39, count 0 2006.201.22:52:28.52#ibcon#enter sib2, iclass 39, count 0 2006.201.22:52:28.52#ibcon#flushed, iclass 39, count 0 2006.201.22:52:28.52#ibcon#about to write, iclass 39, count 0 2006.201.22:52:28.52#ibcon#wrote, iclass 39, count 0 2006.201.22:52:28.52#ibcon#about to read 3, iclass 39, count 0 2006.201.22:52:28.55#ibcon#read 3, iclass 39, count 0 2006.201.22:52:28.55#ibcon#about to read 4, iclass 39, count 0 2006.201.22:52:28.55#ibcon#read 4, iclass 39, count 0 2006.201.22:52:28.55#ibcon#about to read 5, iclass 39, count 0 2006.201.22:52:28.55#ibcon#read 5, iclass 39, count 0 2006.201.22:52:28.55#ibcon#about to read 6, iclass 39, count 0 2006.201.22:52:28.55#ibcon#read 6, iclass 39, count 0 2006.201.22:52:28.55#ibcon#end of sib2, iclass 39, count 0 2006.201.22:52:28.55#ibcon#*after write, iclass 39, count 0 2006.201.22:52:28.55#ibcon#*before return 0, iclass 39, count 0 2006.201.22:52:28.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:52:28.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.22:52:28.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.22:52:28.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.22:52:28.55$vck44/valo=3,564.99 2006.201.22:52:28.55#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.22:52:28.55#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.22:52:28.55#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:28.55#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:28.55#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:28.55#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:28.55#ibcon#enter wrdev, iclass 2, count 0 2006.201.22:52:28.55#ibcon#first serial, iclass 2, count 0 2006.201.22:52:28.55#ibcon#enter sib2, iclass 2, count 0 2006.201.22:52:28.55#ibcon#flushed, iclass 2, count 0 2006.201.22:52:28.55#ibcon#about to write, iclass 2, count 0 2006.201.22:52:28.55#ibcon#wrote, iclass 2, count 0 2006.201.22:52:28.55#ibcon#about to read 3, iclass 2, count 0 2006.201.22:52:28.57#ibcon#read 3, iclass 2, count 0 2006.201.22:52:28.57#ibcon#about to read 4, iclass 2, count 0 2006.201.22:52:28.57#ibcon#read 4, iclass 2, count 0 2006.201.22:52:28.57#ibcon#about to read 5, iclass 2, count 0 2006.201.22:52:28.57#ibcon#read 5, iclass 2, count 0 2006.201.22:52:28.57#ibcon#about to read 6, iclass 2, count 0 2006.201.22:52:28.57#ibcon#read 6, iclass 2, count 0 2006.201.22:52:28.57#ibcon#end of sib2, iclass 2, count 0 2006.201.22:52:28.57#ibcon#*mode == 0, iclass 2, count 0 2006.201.22:52:28.57#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.22:52:28.57#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.22:52:28.57#ibcon#*before write, iclass 2, count 0 2006.201.22:52:28.57#ibcon#enter sib2, iclass 2, count 0 2006.201.22:52:28.57#ibcon#flushed, iclass 2, count 0 2006.201.22:52:28.57#ibcon#about to write, iclass 2, count 0 2006.201.22:52:28.57#ibcon#wrote, iclass 2, count 0 2006.201.22:52:28.57#ibcon#about to read 3, iclass 2, count 0 2006.201.22:52:28.62#ibcon#read 3, iclass 2, count 0 2006.201.22:52:28.62#ibcon#about to read 4, iclass 2, count 0 2006.201.22:52:28.62#ibcon#read 4, iclass 2, count 0 2006.201.22:52:28.62#ibcon#about to read 5, iclass 2, count 0 2006.201.22:52:28.62#ibcon#read 5, iclass 2, count 0 2006.201.22:52:28.62#ibcon#about to read 6, iclass 2, count 0 2006.201.22:52:28.62#ibcon#read 6, iclass 2, count 0 2006.201.22:52:28.62#ibcon#end of sib2, iclass 2, count 0 2006.201.22:52:28.62#ibcon#*after write, iclass 2, count 0 2006.201.22:52:28.62#ibcon#*before return 0, iclass 2, count 0 2006.201.22:52:28.62#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:28.62#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:28.62#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.22:52:28.62#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.22:52:28.62$vck44/va=3,8 2006.201.22:52:28.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.22:52:28.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.22:52:28.62#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:28.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:28.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:28.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:28.67#ibcon#enter wrdev, iclass 5, count 2 2006.201.22:52:28.67#ibcon#first serial, iclass 5, count 2 2006.201.22:52:28.67#ibcon#enter sib2, iclass 5, count 2 2006.201.22:52:28.67#ibcon#flushed, iclass 5, count 2 2006.201.22:52:28.67#ibcon#about to write, iclass 5, count 2 2006.201.22:52:28.67#ibcon#wrote, iclass 5, count 2 2006.201.22:52:28.67#ibcon#about to read 3, iclass 5, count 2 2006.201.22:52:28.69#ibcon#read 3, iclass 5, count 2 2006.201.22:52:28.69#ibcon#about to read 4, iclass 5, count 2 2006.201.22:52:28.69#ibcon#read 4, iclass 5, count 2 2006.201.22:52:28.69#ibcon#about to read 5, iclass 5, count 2 2006.201.22:52:28.69#ibcon#read 5, iclass 5, count 2 2006.201.22:52:28.69#ibcon#about to read 6, iclass 5, count 2 2006.201.22:52:28.69#ibcon#read 6, iclass 5, count 2 2006.201.22:52:28.69#ibcon#end of sib2, iclass 5, count 2 2006.201.22:52:28.69#ibcon#*mode == 0, iclass 5, count 2 2006.201.22:52:28.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.22:52:28.69#ibcon#[25=AT03-08\r\n] 2006.201.22:52:28.69#ibcon#*before write, iclass 5, count 2 2006.201.22:52:28.69#ibcon#enter sib2, iclass 5, count 2 2006.201.22:52:28.69#ibcon#flushed, iclass 5, count 2 2006.201.22:52:28.69#ibcon#about to write, iclass 5, count 2 2006.201.22:52:28.69#ibcon#wrote, iclass 5, count 2 2006.201.22:52:28.69#ibcon#about to read 3, iclass 5, count 2 2006.201.22:52:28.72#ibcon#read 3, iclass 5, count 2 2006.201.22:52:28.72#ibcon#about to read 4, iclass 5, count 2 2006.201.22:52:28.72#ibcon#read 4, iclass 5, count 2 2006.201.22:52:28.72#ibcon#about to read 5, iclass 5, count 2 2006.201.22:52:28.72#ibcon#read 5, iclass 5, count 2 2006.201.22:52:28.72#ibcon#about to read 6, iclass 5, count 2 2006.201.22:52:28.72#ibcon#read 6, iclass 5, count 2 2006.201.22:52:28.72#ibcon#end of sib2, iclass 5, count 2 2006.201.22:52:28.72#ibcon#*after write, iclass 5, count 2 2006.201.22:52:28.72#ibcon#*before return 0, iclass 5, count 2 2006.201.22:52:28.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:28.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:28.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.22:52:28.72#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:28.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:28.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:28.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:28.84#ibcon#enter wrdev, iclass 5, count 0 2006.201.22:52:28.84#ibcon#first serial, iclass 5, count 0 2006.201.22:52:28.84#ibcon#enter sib2, iclass 5, count 0 2006.201.22:52:28.84#ibcon#flushed, iclass 5, count 0 2006.201.22:52:28.84#ibcon#about to write, iclass 5, count 0 2006.201.22:52:28.84#ibcon#wrote, iclass 5, count 0 2006.201.22:52:28.84#ibcon#about to read 3, iclass 5, count 0 2006.201.22:52:28.86#ibcon#read 3, iclass 5, count 0 2006.201.22:52:28.86#ibcon#about to read 4, iclass 5, count 0 2006.201.22:52:28.86#ibcon#read 4, iclass 5, count 0 2006.201.22:52:28.86#ibcon#about to read 5, iclass 5, count 0 2006.201.22:52:28.86#ibcon#read 5, iclass 5, count 0 2006.201.22:52:28.86#ibcon#about to read 6, iclass 5, count 0 2006.201.22:52:28.86#ibcon#read 6, iclass 5, count 0 2006.201.22:52:28.86#ibcon#end of sib2, iclass 5, count 0 2006.201.22:52:28.86#ibcon#*mode == 0, iclass 5, count 0 2006.201.22:52:28.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.22:52:28.86#ibcon#[25=USB\r\n] 2006.201.22:52:28.86#ibcon#*before write, iclass 5, count 0 2006.201.22:52:28.86#ibcon#enter sib2, iclass 5, count 0 2006.201.22:52:28.86#ibcon#flushed, iclass 5, count 0 2006.201.22:52:28.86#ibcon#about to write, iclass 5, count 0 2006.201.22:52:28.86#ibcon#wrote, iclass 5, count 0 2006.201.22:52:28.86#ibcon#about to read 3, iclass 5, count 0 2006.201.22:52:28.89#ibcon#read 3, iclass 5, count 0 2006.201.22:52:28.89#ibcon#about to read 4, iclass 5, count 0 2006.201.22:52:28.89#ibcon#read 4, iclass 5, count 0 2006.201.22:52:28.89#ibcon#about to read 5, iclass 5, count 0 2006.201.22:52:28.89#ibcon#read 5, iclass 5, count 0 2006.201.22:52:28.89#ibcon#about to read 6, iclass 5, count 0 2006.201.22:52:28.89#ibcon#read 6, iclass 5, count 0 2006.201.22:52:28.89#ibcon#end of sib2, iclass 5, count 0 2006.201.22:52:28.89#ibcon#*after write, iclass 5, count 0 2006.201.22:52:28.89#ibcon#*before return 0, iclass 5, count 0 2006.201.22:52:28.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:28.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:28.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.22:52:28.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.22:52:28.89$vck44/valo=4,624.99 2006.201.22:52:28.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.22:52:28.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.22:52:28.89#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:28.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:28.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:28.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:28.89#ibcon#enter wrdev, iclass 7, count 0 2006.201.22:52:28.89#ibcon#first serial, iclass 7, count 0 2006.201.22:52:28.89#ibcon#enter sib2, iclass 7, count 0 2006.201.22:52:28.89#ibcon#flushed, iclass 7, count 0 2006.201.22:52:28.89#ibcon#about to write, iclass 7, count 0 2006.201.22:52:28.89#ibcon#wrote, iclass 7, count 0 2006.201.22:52:28.89#ibcon#about to read 3, iclass 7, count 0 2006.201.22:52:28.91#ibcon#read 3, iclass 7, count 0 2006.201.22:52:28.91#ibcon#about to read 4, iclass 7, count 0 2006.201.22:52:28.91#ibcon#read 4, iclass 7, count 0 2006.201.22:52:28.91#ibcon#about to read 5, iclass 7, count 0 2006.201.22:52:28.91#ibcon#read 5, iclass 7, count 0 2006.201.22:52:28.91#ibcon#about to read 6, iclass 7, count 0 2006.201.22:52:28.91#ibcon#read 6, iclass 7, count 0 2006.201.22:52:28.91#ibcon#end of sib2, iclass 7, count 0 2006.201.22:52:28.91#ibcon#*mode == 0, iclass 7, count 0 2006.201.22:52:28.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.22:52:28.91#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.22:52:28.91#ibcon#*before write, iclass 7, count 0 2006.201.22:52:28.91#ibcon#enter sib2, iclass 7, count 0 2006.201.22:52:28.91#ibcon#flushed, iclass 7, count 0 2006.201.22:52:28.91#ibcon#about to write, iclass 7, count 0 2006.201.22:52:28.91#ibcon#wrote, iclass 7, count 0 2006.201.22:52:28.91#ibcon#about to read 3, iclass 7, count 0 2006.201.22:52:28.96#ibcon#read 3, iclass 7, count 0 2006.201.22:52:28.96#ibcon#about to read 4, iclass 7, count 0 2006.201.22:52:28.96#ibcon#read 4, iclass 7, count 0 2006.201.22:52:28.96#ibcon#about to read 5, iclass 7, count 0 2006.201.22:52:28.96#ibcon#read 5, iclass 7, count 0 2006.201.22:52:28.96#ibcon#about to read 6, iclass 7, count 0 2006.201.22:52:28.96#ibcon#read 6, iclass 7, count 0 2006.201.22:52:28.96#ibcon#end of sib2, iclass 7, count 0 2006.201.22:52:28.96#ibcon#*after write, iclass 7, count 0 2006.201.22:52:28.96#ibcon#*before return 0, iclass 7, count 0 2006.201.22:52:28.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:28.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:28.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.22:52:28.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.22:52:28.96$vck44/va=4,7 2006.201.22:52:28.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.22:52:28.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.22:52:28.96#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:28.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:29.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:29.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:29.01#ibcon#enter wrdev, iclass 11, count 2 2006.201.22:52:29.01#ibcon#first serial, iclass 11, count 2 2006.201.22:52:29.01#ibcon#enter sib2, iclass 11, count 2 2006.201.22:52:29.01#ibcon#flushed, iclass 11, count 2 2006.201.22:52:29.01#ibcon#about to write, iclass 11, count 2 2006.201.22:52:29.01#ibcon#wrote, iclass 11, count 2 2006.201.22:52:29.01#ibcon#about to read 3, iclass 11, count 2 2006.201.22:52:29.03#ibcon#read 3, iclass 11, count 2 2006.201.22:52:29.03#ibcon#about to read 4, iclass 11, count 2 2006.201.22:52:29.03#ibcon#read 4, iclass 11, count 2 2006.201.22:52:29.03#ibcon#about to read 5, iclass 11, count 2 2006.201.22:52:29.03#ibcon#read 5, iclass 11, count 2 2006.201.22:52:29.03#ibcon#about to read 6, iclass 11, count 2 2006.201.22:52:29.03#ibcon#read 6, iclass 11, count 2 2006.201.22:52:29.03#ibcon#end of sib2, iclass 11, count 2 2006.201.22:52:29.03#ibcon#*mode == 0, iclass 11, count 2 2006.201.22:52:29.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.22:52:29.03#ibcon#[25=AT04-07\r\n] 2006.201.22:52:29.03#ibcon#*before write, iclass 11, count 2 2006.201.22:52:29.03#ibcon#enter sib2, iclass 11, count 2 2006.201.22:52:29.03#ibcon#flushed, iclass 11, count 2 2006.201.22:52:29.03#ibcon#about to write, iclass 11, count 2 2006.201.22:52:29.03#ibcon#wrote, iclass 11, count 2 2006.201.22:52:29.03#ibcon#about to read 3, iclass 11, count 2 2006.201.22:52:29.06#ibcon#read 3, iclass 11, count 2 2006.201.22:52:29.06#ibcon#about to read 4, iclass 11, count 2 2006.201.22:52:29.06#ibcon#read 4, iclass 11, count 2 2006.201.22:52:29.06#ibcon#about to read 5, iclass 11, count 2 2006.201.22:52:29.06#ibcon#read 5, iclass 11, count 2 2006.201.22:52:29.06#ibcon#about to read 6, iclass 11, count 2 2006.201.22:52:29.06#ibcon#read 6, iclass 11, count 2 2006.201.22:52:29.06#ibcon#end of sib2, iclass 11, count 2 2006.201.22:52:29.06#ibcon#*after write, iclass 11, count 2 2006.201.22:52:29.06#ibcon#*before return 0, iclass 11, count 2 2006.201.22:52:29.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:29.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:29.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.22:52:29.06#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:29.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:29.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:29.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:29.18#ibcon#enter wrdev, iclass 11, count 0 2006.201.22:52:29.18#ibcon#first serial, iclass 11, count 0 2006.201.22:52:29.18#ibcon#enter sib2, iclass 11, count 0 2006.201.22:52:29.18#ibcon#flushed, iclass 11, count 0 2006.201.22:52:29.18#ibcon#about to write, iclass 11, count 0 2006.201.22:52:29.18#ibcon#wrote, iclass 11, count 0 2006.201.22:52:29.18#ibcon#about to read 3, iclass 11, count 0 2006.201.22:52:29.21#ibcon#read 3, iclass 11, count 0 2006.201.22:52:29.21#ibcon#about to read 4, iclass 11, count 0 2006.201.22:52:29.21#ibcon#read 4, iclass 11, count 0 2006.201.22:52:29.21#ibcon#about to read 5, iclass 11, count 0 2006.201.22:52:29.21#ibcon#read 5, iclass 11, count 0 2006.201.22:52:29.21#ibcon#about to read 6, iclass 11, count 0 2006.201.22:52:29.21#ibcon#read 6, iclass 11, count 0 2006.201.22:52:29.21#ibcon#end of sib2, iclass 11, count 0 2006.201.22:52:29.21#ibcon#*mode == 0, iclass 11, count 0 2006.201.22:52:29.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.22:52:29.21#ibcon#[25=USB\r\n] 2006.201.22:52:29.21#ibcon#*before write, iclass 11, count 0 2006.201.22:52:29.21#ibcon#enter sib2, iclass 11, count 0 2006.201.22:52:29.21#ibcon#flushed, iclass 11, count 0 2006.201.22:52:29.21#ibcon#about to write, iclass 11, count 0 2006.201.22:52:29.21#ibcon#wrote, iclass 11, count 0 2006.201.22:52:29.21#ibcon#about to read 3, iclass 11, count 0 2006.201.22:52:29.24#ibcon#read 3, iclass 11, count 0 2006.201.22:52:29.24#ibcon#about to read 4, iclass 11, count 0 2006.201.22:52:29.24#ibcon#read 4, iclass 11, count 0 2006.201.22:52:29.24#ibcon#about to read 5, iclass 11, count 0 2006.201.22:52:29.24#ibcon#read 5, iclass 11, count 0 2006.201.22:52:29.24#ibcon#about to read 6, iclass 11, count 0 2006.201.22:52:29.24#ibcon#read 6, iclass 11, count 0 2006.201.22:52:29.24#ibcon#end of sib2, iclass 11, count 0 2006.201.22:52:29.24#ibcon#*after write, iclass 11, count 0 2006.201.22:52:29.24#ibcon#*before return 0, iclass 11, count 0 2006.201.22:52:29.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:29.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:29.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.22:52:29.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.22:52:29.24$vck44/valo=5,734.99 2006.201.22:52:29.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.22:52:29.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.22:52:29.24#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:29.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:29.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:29.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:29.24#ibcon#enter wrdev, iclass 13, count 0 2006.201.22:52:29.24#ibcon#first serial, iclass 13, count 0 2006.201.22:52:29.24#ibcon#enter sib2, iclass 13, count 0 2006.201.22:52:29.24#ibcon#flushed, iclass 13, count 0 2006.201.22:52:29.24#ibcon#about to write, iclass 13, count 0 2006.201.22:52:29.24#ibcon#wrote, iclass 13, count 0 2006.201.22:52:29.24#ibcon#about to read 3, iclass 13, count 0 2006.201.22:52:29.26#ibcon#read 3, iclass 13, count 0 2006.201.22:52:29.26#ibcon#about to read 4, iclass 13, count 0 2006.201.22:52:29.26#ibcon#read 4, iclass 13, count 0 2006.201.22:52:29.26#ibcon#about to read 5, iclass 13, count 0 2006.201.22:52:29.26#ibcon#read 5, iclass 13, count 0 2006.201.22:52:29.26#ibcon#about to read 6, iclass 13, count 0 2006.201.22:52:29.26#ibcon#read 6, iclass 13, count 0 2006.201.22:52:29.26#ibcon#end of sib2, iclass 13, count 0 2006.201.22:52:29.26#ibcon#*mode == 0, iclass 13, count 0 2006.201.22:52:29.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.22:52:29.26#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.22:52:29.26#ibcon#*before write, iclass 13, count 0 2006.201.22:52:29.26#ibcon#enter sib2, iclass 13, count 0 2006.201.22:52:29.26#ibcon#flushed, iclass 13, count 0 2006.201.22:52:29.26#ibcon#about to write, iclass 13, count 0 2006.201.22:52:29.26#ibcon#wrote, iclass 13, count 0 2006.201.22:52:29.26#ibcon#about to read 3, iclass 13, count 0 2006.201.22:52:29.30#ibcon#read 3, iclass 13, count 0 2006.201.22:52:29.30#ibcon#about to read 4, iclass 13, count 0 2006.201.22:52:29.30#ibcon#read 4, iclass 13, count 0 2006.201.22:52:29.30#ibcon#about to read 5, iclass 13, count 0 2006.201.22:52:29.30#ibcon#read 5, iclass 13, count 0 2006.201.22:52:29.30#ibcon#about to read 6, iclass 13, count 0 2006.201.22:52:29.30#ibcon#read 6, iclass 13, count 0 2006.201.22:52:29.30#ibcon#end of sib2, iclass 13, count 0 2006.201.22:52:29.30#ibcon#*after write, iclass 13, count 0 2006.201.22:52:29.30#ibcon#*before return 0, iclass 13, count 0 2006.201.22:52:29.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:29.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:29.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.22:52:29.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.22:52:29.30$vck44/va=5,4 2006.201.22:52:29.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.22:52:29.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.22:52:29.30#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:29.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:29.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:29.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:29.36#ibcon#enter wrdev, iclass 15, count 2 2006.201.22:52:29.36#ibcon#first serial, iclass 15, count 2 2006.201.22:52:29.36#ibcon#enter sib2, iclass 15, count 2 2006.201.22:52:29.36#ibcon#flushed, iclass 15, count 2 2006.201.22:52:29.36#ibcon#about to write, iclass 15, count 2 2006.201.22:52:29.36#ibcon#wrote, iclass 15, count 2 2006.201.22:52:29.36#ibcon#about to read 3, iclass 15, count 2 2006.201.22:52:29.38#ibcon#read 3, iclass 15, count 2 2006.201.22:52:29.38#ibcon#about to read 4, iclass 15, count 2 2006.201.22:52:29.38#ibcon#read 4, iclass 15, count 2 2006.201.22:52:29.38#ibcon#about to read 5, iclass 15, count 2 2006.201.22:52:29.38#ibcon#read 5, iclass 15, count 2 2006.201.22:52:29.38#ibcon#about to read 6, iclass 15, count 2 2006.201.22:52:29.38#ibcon#read 6, iclass 15, count 2 2006.201.22:52:29.38#ibcon#end of sib2, iclass 15, count 2 2006.201.22:52:29.38#ibcon#*mode == 0, iclass 15, count 2 2006.201.22:52:29.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.22:52:29.38#ibcon#[25=AT05-04\r\n] 2006.201.22:52:29.38#ibcon#*before write, iclass 15, count 2 2006.201.22:52:29.38#ibcon#enter sib2, iclass 15, count 2 2006.201.22:52:29.38#ibcon#flushed, iclass 15, count 2 2006.201.22:52:29.38#ibcon#about to write, iclass 15, count 2 2006.201.22:52:29.38#ibcon#wrote, iclass 15, count 2 2006.201.22:52:29.38#ibcon#about to read 3, iclass 15, count 2 2006.201.22:52:29.41#ibcon#read 3, iclass 15, count 2 2006.201.22:52:29.41#ibcon#about to read 4, iclass 15, count 2 2006.201.22:52:29.41#ibcon#read 4, iclass 15, count 2 2006.201.22:52:29.41#ibcon#about to read 5, iclass 15, count 2 2006.201.22:52:29.41#ibcon#read 5, iclass 15, count 2 2006.201.22:52:29.41#ibcon#about to read 6, iclass 15, count 2 2006.201.22:52:29.41#ibcon#read 6, iclass 15, count 2 2006.201.22:52:29.41#ibcon#end of sib2, iclass 15, count 2 2006.201.22:52:29.41#ibcon#*after write, iclass 15, count 2 2006.201.22:52:29.41#ibcon#*before return 0, iclass 15, count 2 2006.201.22:52:29.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:29.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:29.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.22:52:29.41#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:29.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:29.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:29.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:29.53#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:52:29.53#ibcon#first serial, iclass 15, count 0 2006.201.22:52:29.53#ibcon#enter sib2, iclass 15, count 0 2006.201.22:52:29.53#ibcon#flushed, iclass 15, count 0 2006.201.22:52:29.53#ibcon#about to write, iclass 15, count 0 2006.201.22:52:29.53#ibcon#wrote, iclass 15, count 0 2006.201.22:52:29.53#ibcon#about to read 3, iclass 15, count 0 2006.201.22:52:29.55#ibcon#read 3, iclass 15, count 0 2006.201.22:52:29.55#ibcon#about to read 4, iclass 15, count 0 2006.201.22:52:29.55#ibcon#read 4, iclass 15, count 0 2006.201.22:52:29.55#ibcon#about to read 5, iclass 15, count 0 2006.201.22:52:29.55#ibcon#read 5, iclass 15, count 0 2006.201.22:52:29.55#ibcon#about to read 6, iclass 15, count 0 2006.201.22:52:29.55#ibcon#read 6, iclass 15, count 0 2006.201.22:52:29.55#ibcon#end of sib2, iclass 15, count 0 2006.201.22:52:29.55#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:52:29.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:52:29.55#ibcon#[25=USB\r\n] 2006.201.22:52:29.55#ibcon#*before write, iclass 15, count 0 2006.201.22:52:29.55#ibcon#enter sib2, iclass 15, count 0 2006.201.22:52:29.55#ibcon#flushed, iclass 15, count 0 2006.201.22:52:29.55#ibcon#about to write, iclass 15, count 0 2006.201.22:52:29.55#ibcon#wrote, iclass 15, count 0 2006.201.22:52:29.55#ibcon#about to read 3, iclass 15, count 0 2006.201.22:52:29.58#ibcon#read 3, iclass 15, count 0 2006.201.22:52:29.58#ibcon#about to read 4, iclass 15, count 0 2006.201.22:52:29.58#ibcon#read 4, iclass 15, count 0 2006.201.22:52:29.58#ibcon#about to read 5, iclass 15, count 0 2006.201.22:52:29.58#ibcon#read 5, iclass 15, count 0 2006.201.22:52:29.58#ibcon#about to read 6, iclass 15, count 0 2006.201.22:52:29.58#ibcon#read 6, iclass 15, count 0 2006.201.22:52:29.58#ibcon#end of sib2, iclass 15, count 0 2006.201.22:52:29.58#ibcon#*after write, iclass 15, count 0 2006.201.22:52:29.58#ibcon#*before return 0, iclass 15, count 0 2006.201.22:52:29.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:29.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:29.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:52:29.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:52:29.58$vck44/valo=6,814.99 2006.201.22:52:29.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.22:52:29.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.22:52:29.58#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:29.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:29.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:29.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:29.58#ibcon#enter wrdev, iclass 17, count 0 2006.201.22:52:29.58#ibcon#first serial, iclass 17, count 0 2006.201.22:52:29.58#ibcon#enter sib2, iclass 17, count 0 2006.201.22:52:29.58#ibcon#flushed, iclass 17, count 0 2006.201.22:52:29.58#ibcon#about to write, iclass 17, count 0 2006.201.22:52:29.58#ibcon#wrote, iclass 17, count 0 2006.201.22:52:29.58#ibcon#about to read 3, iclass 17, count 0 2006.201.22:52:29.60#ibcon#read 3, iclass 17, count 0 2006.201.22:52:29.60#ibcon#about to read 4, iclass 17, count 0 2006.201.22:52:29.60#ibcon#read 4, iclass 17, count 0 2006.201.22:52:29.60#ibcon#about to read 5, iclass 17, count 0 2006.201.22:52:29.60#ibcon#read 5, iclass 17, count 0 2006.201.22:52:29.60#ibcon#about to read 6, iclass 17, count 0 2006.201.22:52:29.60#ibcon#read 6, iclass 17, count 0 2006.201.22:52:29.60#ibcon#end of sib2, iclass 17, count 0 2006.201.22:52:29.60#ibcon#*mode == 0, iclass 17, count 0 2006.201.22:52:29.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.22:52:29.60#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.22:52:29.60#ibcon#*before write, iclass 17, count 0 2006.201.22:52:29.60#ibcon#enter sib2, iclass 17, count 0 2006.201.22:52:29.60#ibcon#flushed, iclass 17, count 0 2006.201.22:52:29.60#ibcon#about to write, iclass 17, count 0 2006.201.22:52:29.60#ibcon#wrote, iclass 17, count 0 2006.201.22:52:29.60#ibcon#about to read 3, iclass 17, count 0 2006.201.22:52:29.65#ibcon#read 3, iclass 17, count 0 2006.201.22:52:29.65#ibcon#about to read 4, iclass 17, count 0 2006.201.22:52:29.65#ibcon#read 4, iclass 17, count 0 2006.201.22:52:29.65#ibcon#about to read 5, iclass 17, count 0 2006.201.22:52:29.65#ibcon#read 5, iclass 17, count 0 2006.201.22:52:29.65#ibcon#about to read 6, iclass 17, count 0 2006.201.22:52:29.65#ibcon#read 6, iclass 17, count 0 2006.201.22:52:29.65#ibcon#end of sib2, iclass 17, count 0 2006.201.22:52:29.65#ibcon#*after write, iclass 17, count 0 2006.201.22:52:29.65#ibcon#*before return 0, iclass 17, count 0 2006.201.22:52:29.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:29.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:29.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.22:52:29.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.22:52:29.65$vck44/va=6,5 2006.201.22:52:29.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.22:52:29.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.22:52:29.65#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:29.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:29.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:29.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:29.70#ibcon#enter wrdev, iclass 19, count 2 2006.201.22:52:29.70#ibcon#first serial, iclass 19, count 2 2006.201.22:52:29.70#ibcon#enter sib2, iclass 19, count 2 2006.201.22:52:29.70#ibcon#flushed, iclass 19, count 2 2006.201.22:52:29.70#ibcon#about to write, iclass 19, count 2 2006.201.22:52:29.70#ibcon#wrote, iclass 19, count 2 2006.201.22:52:29.70#ibcon#about to read 3, iclass 19, count 2 2006.201.22:52:29.72#ibcon#read 3, iclass 19, count 2 2006.201.22:52:29.72#ibcon#about to read 4, iclass 19, count 2 2006.201.22:52:29.72#ibcon#read 4, iclass 19, count 2 2006.201.22:52:29.72#ibcon#about to read 5, iclass 19, count 2 2006.201.22:52:29.72#ibcon#read 5, iclass 19, count 2 2006.201.22:52:29.72#ibcon#about to read 6, iclass 19, count 2 2006.201.22:52:29.72#ibcon#read 6, iclass 19, count 2 2006.201.22:52:29.72#ibcon#end of sib2, iclass 19, count 2 2006.201.22:52:29.72#ibcon#*mode == 0, iclass 19, count 2 2006.201.22:52:29.72#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.22:52:29.72#ibcon#[25=AT06-05\r\n] 2006.201.22:52:29.72#ibcon#*before write, iclass 19, count 2 2006.201.22:52:29.72#ibcon#enter sib2, iclass 19, count 2 2006.201.22:52:29.72#ibcon#flushed, iclass 19, count 2 2006.201.22:52:29.72#ibcon#about to write, iclass 19, count 2 2006.201.22:52:29.72#ibcon#wrote, iclass 19, count 2 2006.201.22:52:29.72#ibcon#about to read 3, iclass 19, count 2 2006.201.22:52:29.75#ibcon#read 3, iclass 19, count 2 2006.201.22:52:29.75#ibcon#about to read 4, iclass 19, count 2 2006.201.22:52:29.75#ibcon#read 4, iclass 19, count 2 2006.201.22:52:29.75#ibcon#about to read 5, iclass 19, count 2 2006.201.22:52:29.75#ibcon#read 5, iclass 19, count 2 2006.201.22:52:29.75#ibcon#about to read 6, iclass 19, count 2 2006.201.22:52:29.75#ibcon#read 6, iclass 19, count 2 2006.201.22:52:29.75#ibcon#end of sib2, iclass 19, count 2 2006.201.22:52:29.75#ibcon#*after write, iclass 19, count 2 2006.201.22:52:29.75#ibcon#*before return 0, iclass 19, count 2 2006.201.22:52:29.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:29.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:29.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.22:52:29.75#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:29.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:29.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:29.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:29.87#ibcon#enter wrdev, iclass 19, count 0 2006.201.22:52:29.87#ibcon#first serial, iclass 19, count 0 2006.201.22:52:29.87#ibcon#enter sib2, iclass 19, count 0 2006.201.22:52:29.87#ibcon#flushed, iclass 19, count 0 2006.201.22:52:29.87#ibcon#about to write, iclass 19, count 0 2006.201.22:52:29.87#ibcon#wrote, iclass 19, count 0 2006.201.22:52:29.87#ibcon#about to read 3, iclass 19, count 0 2006.201.22:52:29.89#ibcon#read 3, iclass 19, count 0 2006.201.22:52:29.89#ibcon#about to read 4, iclass 19, count 0 2006.201.22:52:29.89#ibcon#read 4, iclass 19, count 0 2006.201.22:52:29.89#ibcon#about to read 5, iclass 19, count 0 2006.201.22:52:29.89#ibcon#read 5, iclass 19, count 0 2006.201.22:52:29.89#ibcon#about to read 6, iclass 19, count 0 2006.201.22:52:29.89#ibcon#read 6, iclass 19, count 0 2006.201.22:52:29.89#ibcon#end of sib2, iclass 19, count 0 2006.201.22:52:29.89#ibcon#*mode == 0, iclass 19, count 0 2006.201.22:52:29.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.22:52:29.89#ibcon#[25=USB\r\n] 2006.201.22:52:29.89#ibcon#*before write, iclass 19, count 0 2006.201.22:52:29.89#ibcon#enter sib2, iclass 19, count 0 2006.201.22:52:29.89#ibcon#flushed, iclass 19, count 0 2006.201.22:52:29.89#ibcon#about to write, iclass 19, count 0 2006.201.22:52:29.89#ibcon#wrote, iclass 19, count 0 2006.201.22:52:29.89#ibcon#about to read 3, iclass 19, count 0 2006.201.22:52:29.92#ibcon#read 3, iclass 19, count 0 2006.201.22:52:29.92#ibcon#about to read 4, iclass 19, count 0 2006.201.22:52:29.92#ibcon#read 4, iclass 19, count 0 2006.201.22:52:29.92#ibcon#about to read 5, iclass 19, count 0 2006.201.22:52:29.92#ibcon#read 5, iclass 19, count 0 2006.201.22:52:29.92#ibcon#about to read 6, iclass 19, count 0 2006.201.22:52:29.92#ibcon#read 6, iclass 19, count 0 2006.201.22:52:29.92#ibcon#end of sib2, iclass 19, count 0 2006.201.22:52:29.92#ibcon#*after write, iclass 19, count 0 2006.201.22:52:29.92#ibcon#*before return 0, iclass 19, count 0 2006.201.22:52:29.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:29.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:29.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.22:52:29.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.22:52:29.92$vck44/valo=7,864.99 2006.201.22:52:29.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.22:52:29.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.22:52:29.92#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:29.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:29.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:29.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:29.92#ibcon#enter wrdev, iclass 21, count 0 2006.201.22:52:29.92#ibcon#first serial, iclass 21, count 0 2006.201.22:52:29.92#ibcon#enter sib2, iclass 21, count 0 2006.201.22:52:29.92#ibcon#flushed, iclass 21, count 0 2006.201.22:52:29.92#ibcon#about to write, iclass 21, count 0 2006.201.22:52:29.92#ibcon#wrote, iclass 21, count 0 2006.201.22:52:29.92#ibcon#about to read 3, iclass 21, count 0 2006.201.22:52:29.94#ibcon#read 3, iclass 21, count 0 2006.201.22:52:29.94#ibcon#about to read 4, iclass 21, count 0 2006.201.22:52:29.94#ibcon#read 4, iclass 21, count 0 2006.201.22:52:29.94#ibcon#about to read 5, iclass 21, count 0 2006.201.22:52:29.94#ibcon#read 5, iclass 21, count 0 2006.201.22:52:29.94#ibcon#about to read 6, iclass 21, count 0 2006.201.22:52:29.94#ibcon#read 6, iclass 21, count 0 2006.201.22:52:29.94#ibcon#end of sib2, iclass 21, count 0 2006.201.22:52:29.94#ibcon#*mode == 0, iclass 21, count 0 2006.201.22:52:29.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.22:52:29.94#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.22:52:29.94#ibcon#*before write, iclass 21, count 0 2006.201.22:52:29.94#ibcon#enter sib2, iclass 21, count 0 2006.201.22:52:29.94#ibcon#flushed, iclass 21, count 0 2006.201.22:52:29.94#ibcon#about to write, iclass 21, count 0 2006.201.22:52:29.94#ibcon#wrote, iclass 21, count 0 2006.201.22:52:29.94#ibcon#about to read 3, iclass 21, count 0 2006.201.22:52:29.99#ibcon#read 3, iclass 21, count 0 2006.201.22:52:29.99#ibcon#about to read 4, iclass 21, count 0 2006.201.22:52:29.99#ibcon#read 4, iclass 21, count 0 2006.201.22:52:29.99#ibcon#about to read 5, iclass 21, count 0 2006.201.22:52:29.99#ibcon#read 5, iclass 21, count 0 2006.201.22:52:29.99#ibcon#about to read 6, iclass 21, count 0 2006.201.22:52:29.99#ibcon#read 6, iclass 21, count 0 2006.201.22:52:29.99#ibcon#end of sib2, iclass 21, count 0 2006.201.22:52:29.99#ibcon#*after write, iclass 21, count 0 2006.201.22:52:29.99#ibcon#*before return 0, iclass 21, count 0 2006.201.22:52:29.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:29.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:29.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.22:52:29.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.22:52:29.99$vck44/va=7,5 2006.201.22:52:29.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.22:52:29.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.22:52:29.99#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:29.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:30.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:30.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:30.04#ibcon#enter wrdev, iclass 23, count 2 2006.201.22:52:30.04#ibcon#first serial, iclass 23, count 2 2006.201.22:52:30.04#ibcon#enter sib2, iclass 23, count 2 2006.201.22:52:30.04#ibcon#flushed, iclass 23, count 2 2006.201.22:52:30.04#ibcon#about to write, iclass 23, count 2 2006.201.22:52:30.04#ibcon#wrote, iclass 23, count 2 2006.201.22:52:30.04#ibcon#about to read 3, iclass 23, count 2 2006.201.22:52:30.06#ibcon#read 3, iclass 23, count 2 2006.201.22:52:30.06#ibcon#about to read 4, iclass 23, count 2 2006.201.22:52:30.06#ibcon#read 4, iclass 23, count 2 2006.201.22:52:30.06#ibcon#about to read 5, iclass 23, count 2 2006.201.22:52:30.06#ibcon#read 5, iclass 23, count 2 2006.201.22:52:30.06#ibcon#about to read 6, iclass 23, count 2 2006.201.22:52:30.06#ibcon#read 6, iclass 23, count 2 2006.201.22:52:30.06#ibcon#end of sib2, iclass 23, count 2 2006.201.22:52:30.06#ibcon#*mode == 0, iclass 23, count 2 2006.201.22:52:30.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.22:52:30.06#ibcon#[25=AT07-05\r\n] 2006.201.22:52:30.06#ibcon#*before write, iclass 23, count 2 2006.201.22:52:30.06#ibcon#enter sib2, iclass 23, count 2 2006.201.22:52:30.06#ibcon#flushed, iclass 23, count 2 2006.201.22:52:30.06#ibcon#about to write, iclass 23, count 2 2006.201.22:52:30.06#ibcon#wrote, iclass 23, count 2 2006.201.22:52:30.06#ibcon#about to read 3, iclass 23, count 2 2006.201.22:52:30.09#ibcon#read 3, iclass 23, count 2 2006.201.22:52:30.09#ibcon#about to read 4, iclass 23, count 2 2006.201.22:52:30.09#ibcon#read 4, iclass 23, count 2 2006.201.22:52:30.09#ibcon#about to read 5, iclass 23, count 2 2006.201.22:52:30.09#ibcon#read 5, iclass 23, count 2 2006.201.22:52:30.09#ibcon#about to read 6, iclass 23, count 2 2006.201.22:52:30.09#ibcon#read 6, iclass 23, count 2 2006.201.22:52:30.09#ibcon#end of sib2, iclass 23, count 2 2006.201.22:52:30.09#ibcon#*after write, iclass 23, count 2 2006.201.22:52:30.09#ibcon#*before return 0, iclass 23, count 2 2006.201.22:52:30.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:30.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:30.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.22:52:30.09#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:30.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:30.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:30.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:30.21#ibcon#enter wrdev, iclass 23, count 0 2006.201.22:52:30.21#ibcon#first serial, iclass 23, count 0 2006.201.22:52:30.21#ibcon#enter sib2, iclass 23, count 0 2006.201.22:52:30.21#ibcon#flushed, iclass 23, count 0 2006.201.22:52:30.21#ibcon#about to write, iclass 23, count 0 2006.201.22:52:30.21#ibcon#wrote, iclass 23, count 0 2006.201.22:52:30.21#ibcon#about to read 3, iclass 23, count 0 2006.201.22:52:30.23#ibcon#read 3, iclass 23, count 0 2006.201.22:52:30.23#ibcon#about to read 4, iclass 23, count 0 2006.201.22:52:30.23#ibcon#read 4, iclass 23, count 0 2006.201.22:52:30.23#ibcon#about to read 5, iclass 23, count 0 2006.201.22:52:30.23#ibcon#read 5, iclass 23, count 0 2006.201.22:52:30.23#ibcon#about to read 6, iclass 23, count 0 2006.201.22:52:30.23#ibcon#read 6, iclass 23, count 0 2006.201.22:52:30.23#ibcon#end of sib2, iclass 23, count 0 2006.201.22:52:30.23#ibcon#*mode == 0, iclass 23, count 0 2006.201.22:52:30.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.22:52:30.23#ibcon#[25=USB\r\n] 2006.201.22:52:30.23#ibcon#*before write, iclass 23, count 0 2006.201.22:52:30.23#ibcon#enter sib2, iclass 23, count 0 2006.201.22:52:30.23#ibcon#flushed, iclass 23, count 0 2006.201.22:52:30.23#ibcon#about to write, iclass 23, count 0 2006.201.22:52:30.23#ibcon#wrote, iclass 23, count 0 2006.201.22:52:30.23#ibcon#about to read 3, iclass 23, count 0 2006.201.22:52:30.26#ibcon#read 3, iclass 23, count 0 2006.201.22:52:30.26#ibcon#about to read 4, iclass 23, count 0 2006.201.22:52:30.26#ibcon#read 4, iclass 23, count 0 2006.201.22:52:30.26#ibcon#about to read 5, iclass 23, count 0 2006.201.22:52:30.26#ibcon#read 5, iclass 23, count 0 2006.201.22:52:30.26#ibcon#about to read 6, iclass 23, count 0 2006.201.22:52:30.26#ibcon#read 6, iclass 23, count 0 2006.201.22:52:30.26#ibcon#end of sib2, iclass 23, count 0 2006.201.22:52:30.26#ibcon#*after write, iclass 23, count 0 2006.201.22:52:30.26#ibcon#*before return 0, iclass 23, count 0 2006.201.22:52:30.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:30.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:30.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.22:52:30.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.22:52:30.26$vck44/valo=8,884.99 2006.201.22:52:30.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.22:52:30.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.22:52:30.26#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:30.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:30.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:30.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:30.26#ibcon#enter wrdev, iclass 25, count 0 2006.201.22:52:30.26#ibcon#first serial, iclass 25, count 0 2006.201.22:52:30.26#ibcon#enter sib2, iclass 25, count 0 2006.201.22:52:30.26#ibcon#flushed, iclass 25, count 0 2006.201.22:52:30.26#ibcon#about to write, iclass 25, count 0 2006.201.22:52:30.26#ibcon#wrote, iclass 25, count 0 2006.201.22:52:30.26#ibcon#about to read 3, iclass 25, count 0 2006.201.22:52:30.28#ibcon#read 3, iclass 25, count 0 2006.201.22:52:30.28#ibcon#about to read 4, iclass 25, count 0 2006.201.22:52:30.28#ibcon#read 4, iclass 25, count 0 2006.201.22:52:30.28#ibcon#about to read 5, iclass 25, count 0 2006.201.22:52:30.28#ibcon#read 5, iclass 25, count 0 2006.201.22:52:30.28#ibcon#about to read 6, iclass 25, count 0 2006.201.22:52:30.28#ibcon#read 6, iclass 25, count 0 2006.201.22:52:30.28#ibcon#end of sib2, iclass 25, count 0 2006.201.22:52:30.28#ibcon#*mode == 0, iclass 25, count 0 2006.201.22:52:30.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.22:52:30.28#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.22:52:30.28#ibcon#*before write, iclass 25, count 0 2006.201.22:52:30.28#ibcon#enter sib2, iclass 25, count 0 2006.201.22:52:30.28#ibcon#flushed, iclass 25, count 0 2006.201.22:52:30.28#ibcon#about to write, iclass 25, count 0 2006.201.22:52:30.28#ibcon#wrote, iclass 25, count 0 2006.201.22:52:30.28#ibcon#about to read 3, iclass 25, count 0 2006.201.22:52:30.32#ibcon#read 3, iclass 25, count 0 2006.201.22:52:30.32#ibcon#about to read 4, iclass 25, count 0 2006.201.22:52:30.32#ibcon#read 4, iclass 25, count 0 2006.201.22:52:30.32#ibcon#about to read 5, iclass 25, count 0 2006.201.22:52:30.32#ibcon#read 5, iclass 25, count 0 2006.201.22:52:30.32#ibcon#about to read 6, iclass 25, count 0 2006.201.22:52:30.32#ibcon#read 6, iclass 25, count 0 2006.201.22:52:30.32#ibcon#end of sib2, iclass 25, count 0 2006.201.22:52:30.32#ibcon#*after write, iclass 25, count 0 2006.201.22:52:30.32#ibcon#*before return 0, iclass 25, count 0 2006.201.22:52:30.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:30.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:30.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.22:52:30.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.22:52:30.32$vck44/va=8,4 2006.201.22:52:30.32#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.22:52:30.32#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.22:52:30.32#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:30.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:30.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:30.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:30.38#ibcon#enter wrdev, iclass 27, count 2 2006.201.22:52:30.38#ibcon#first serial, iclass 27, count 2 2006.201.22:52:30.38#ibcon#enter sib2, iclass 27, count 2 2006.201.22:52:30.38#ibcon#flushed, iclass 27, count 2 2006.201.22:52:30.38#ibcon#about to write, iclass 27, count 2 2006.201.22:52:30.38#ibcon#wrote, iclass 27, count 2 2006.201.22:52:30.38#ibcon#about to read 3, iclass 27, count 2 2006.201.22:52:30.40#ibcon#read 3, iclass 27, count 2 2006.201.22:52:30.40#ibcon#about to read 4, iclass 27, count 2 2006.201.22:52:30.40#ibcon#read 4, iclass 27, count 2 2006.201.22:52:30.40#ibcon#about to read 5, iclass 27, count 2 2006.201.22:52:30.40#ibcon#read 5, iclass 27, count 2 2006.201.22:52:30.40#ibcon#about to read 6, iclass 27, count 2 2006.201.22:52:30.40#ibcon#read 6, iclass 27, count 2 2006.201.22:52:30.40#ibcon#end of sib2, iclass 27, count 2 2006.201.22:52:30.40#ibcon#*mode == 0, iclass 27, count 2 2006.201.22:52:30.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.22:52:30.40#ibcon#[25=AT08-04\r\n] 2006.201.22:52:30.40#ibcon#*before write, iclass 27, count 2 2006.201.22:52:30.40#ibcon#enter sib2, iclass 27, count 2 2006.201.22:52:30.40#ibcon#flushed, iclass 27, count 2 2006.201.22:52:30.40#ibcon#about to write, iclass 27, count 2 2006.201.22:52:30.40#ibcon#wrote, iclass 27, count 2 2006.201.22:52:30.40#ibcon#about to read 3, iclass 27, count 2 2006.201.22:52:30.43#ibcon#read 3, iclass 27, count 2 2006.201.22:52:30.43#ibcon#about to read 4, iclass 27, count 2 2006.201.22:52:30.43#ibcon#read 4, iclass 27, count 2 2006.201.22:52:30.43#ibcon#about to read 5, iclass 27, count 2 2006.201.22:52:30.43#ibcon#read 5, iclass 27, count 2 2006.201.22:52:30.43#ibcon#about to read 6, iclass 27, count 2 2006.201.22:52:30.43#ibcon#read 6, iclass 27, count 2 2006.201.22:52:30.43#ibcon#end of sib2, iclass 27, count 2 2006.201.22:52:30.43#ibcon#*after write, iclass 27, count 2 2006.201.22:52:30.43#ibcon#*before return 0, iclass 27, count 2 2006.201.22:52:30.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:30.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:30.43#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.22:52:30.43#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:30.43#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:30.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:30.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:30.55#ibcon#enter wrdev, iclass 27, count 0 2006.201.22:52:30.55#ibcon#first serial, iclass 27, count 0 2006.201.22:52:30.55#ibcon#enter sib2, iclass 27, count 0 2006.201.22:52:30.55#ibcon#flushed, iclass 27, count 0 2006.201.22:52:30.55#ibcon#about to write, iclass 27, count 0 2006.201.22:52:30.55#ibcon#wrote, iclass 27, count 0 2006.201.22:52:30.55#ibcon#about to read 3, iclass 27, count 0 2006.201.22:52:30.57#ibcon#read 3, iclass 27, count 0 2006.201.22:52:30.57#ibcon#about to read 4, iclass 27, count 0 2006.201.22:52:30.57#ibcon#read 4, iclass 27, count 0 2006.201.22:52:30.57#ibcon#about to read 5, iclass 27, count 0 2006.201.22:52:30.57#ibcon#read 5, iclass 27, count 0 2006.201.22:52:30.57#ibcon#about to read 6, iclass 27, count 0 2006.201.22:52:30.57#ibcon#read 6, iclass 27, count 0 2006.201.22:52:30.57#ibcon#end of sib2, iclass 27, count 0 2006.201.22:52:30.57#ibcon#*mode == 0, iclass 27, count 0 2006.201.22:52:30.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.22:52:30.57#ibcon#[25=USB\r\n] 2006.201.22:52:30.57#ibcon#*before write, iclass 27, count 0 2006.201.22:52:30.57#ibcon#enter sib2, iclass 27, count 0 2006.201.22:52:30.57#ibcon#flushed, iclass 27, count 0 2006.201.22:52:30.57#ibcon#about to write, iclass 27, count 0 2006.201.22:52:30.57#ibcon#wrote, iclass 27, count 0 2006.201.22:52:30.57#ibcon#about to read 3, iclass 27, count 0 2006.201.22:52:30.60#ibcon#read 3, iclass 27, count 0 2006.201.22:52:30.60#ibcon#about to read 4, iclass 27, count 0 2006.201.22:52:30.60#ibcon#read 4, iclass 27, count 0 2006.201.22:52:30.60#ibcon#about to read 5, iclass 27, count 0 2006.201.22:52:30.60#ibcon#read 5, iclass 27, count 0 2006.201.22:52:30.60#ibcon#about to read 6, iclass 27, count 0 2006.201.22:52:30.60#ibcon#read 6, iclass 27, count 0 2006.201.22:52:30.60#ibcon#end of sib2, iclass 27, count 0 2006.201.22:52:30.60#ibcon#*after write, iclass 27, count 0 2006.201.22:52:30.60#ibcon#*before return 0, iclass 27, count 0 2006.201.22:52:30.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:30.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:30.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.22:52:30.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.22:52:30.60$vck44/vblo=1,629.99 2006.201.22:52:30.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.22:52:30.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.22:52:30.60#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:30.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:30.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:30.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:30.60#ibcon#enter wrdev, iclass 29, count 0 2006.201.22:52:30.60#ibcon#first serial, iclass 29, count 0 2006.201.22:52:30.60#ibcon#enter sib2, iclass 29, count 0 2006.201.22:52:30.60#ibcon#flushed, iclass 29, count 0 2006.201.22:52:30.60#ibcon#about to write, iclass 29, count 0 2006.201.22:52:30.60#ibcon#wrote, iclass 29, count 0 2006.201.22:52:30.60#ibcon#about to read 3, iclass 29, count 0 2006.201.22:52:30.62#ibcon#read 3, iclass 29, count 0 2006.201.22:52:30.62#ibcon#about to read 4, iclass 29, count 0 2006.201.22:52:30.62#ibcon#read 4, iclass 29, count 0 2006.201.22:52:30.62#ibcon#about to read 5, iclass 29, count 0 2006.201.22:52:30.62#ibcon#read 5, iclass 29, count 0 2006.201.22:52:30.62#ibcon#about to read 6, iclass 29, count 0 2006.201.22:52:30.62#ibcon#read 6, iclass 29, count 0 2006.201.22:52:30.62#ibcon#end of sib2, iclass 29, count 0 2006.201.22:52:30.62#ibcon#*mode == 0, iclass 29, count 0 2006.201.22:52:30.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.22:52:30.62#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.22:52:30.62#ibcon#*before write, iclass 29, count 0 2006.201.22:52:30.62#ibcon#enter sib2, iclass 29, count 0 2006.201.22:52:30.62#ibcon#flushed, iclass 29, count 0 2006.201.22:52:30.62#ibcon#about to write, iclass 29, count 0 2006.201.22:52:30.62#ibcon#wrote, iclass 29, count 0 2006.201.22:52:30.62#ibcon#about to read 3, iclass 29, count 0 2006.201.22:52:30.67#ibcon#read 3, iclass 29, count 0 2006.201.22:52:30.67#ibcon#about to read 4, iclass 29, count 0 2006.201.22:52:30.67#ibcon#read 4, iclass 29, count 0 2006.201.22:52:30.67#ibcon#about to read 5, iclass 29, count 0 2006.201.22:52:30.67#ibcon#read 5, iclass 29, count 0 2006.201.22:52:30.67#ibcon#about to read 6, iclass 29, count 0 2006.201.22:52:30.67#ibcon#read 6, iclass 29, count 0 2006.201.22:52:30.67#ibcon#end of sib2, iclass 29, count 0 2006.201.22:52:30.67#ibcon#*after write, iclass 29, count 0 2006.201.22:52:30.67#ibcon#*before return 0, iclass 29, count 0 2006.201.22:52:30.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:30.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:30.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.22:52:30.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.22:52:30.67$vck44/vb=1,4 2006.201.22:52:30.67#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.22:52:30.67#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.22:52:30.67#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:30.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:52:30.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:52:30.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:52:30.67#ibcon#enter wrdev, iclass 31, count 2 2006.201.22:52:30.67#ibcon#first serial, iclass 31, count 2 2006.201.22:52:30.67#ibcon#enter sib2, iclass 31, count 2 2006.201.22:52:30.67#ibcon#flushed, iclass 31, count 2 2006.201.22:52:30.67#ibcon#about to write, iclass 31, count 2 2006.201.22:52:30.67#ibcon#wrote, iclass 31, count 2 2006.201.22:52:30.67#ibcon#about to read 3, iclass 31, count 2 2006.201.22:52:30.69#ibcon#read 3, iclass 31, count 2 2006.201.22:52:30.69#ibcon#about to read 4, iclass 31, count 2 2006.201.22:52:30.69#ibcon#read 4, iclass 31, count 2 2006.201.22:52:30.69#ibcon#about to read 5, iclass 31, count 2 2006.201.22:52:30.69#ibcon#read 5, iclass 31, count 2 2006.201.22:52:30.69#ibcon#about to read 6, iclass 31, count 2 2006.201.22:52:30.69#ibcon#read 6, iclass 31, count 2 2006.201.22:52:30.69#ibcon#end of sib2, iclass 31, count 2 2006.201.22:52:30.69#ibcon#*mode == 0, iclass 31, count 2 2006.201.22:52:30.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.22:52:30.69#ibcon#[27=AT01-04\r\n] 2006.201.22:52:30.69#ibcon#*before write, iclass 31, count 2 2006.201.22:52:30.69#ibcon#enter sib2, iclass 31, count 2 2006.201.22:52:30.69#ibcon#flushed, iclass 31, count 2 2006.201.22:52:30.69#ibcon#about to write, iclass 31, count 2 2006.201.22:52:30.69#ibcon#wrote, iclass 31, count 2 2006.201.22:52:30.69#ibcon#about to read 3, iclass 31, count 2 2006.201.22:52:30.72#ibcon#read 3, iclass 31, count 2 2006.201.22:52:30.72#ibcon#about to read 4, iclass 31, count 2 2006.201.22:52:30.72#ibcon#read 4, iclass 31, count 2 2006.201.22:52:30.72#ibcon#about to read 5, iclass 31, count 2 2006.201.22:52:30.72#ibcon#read 5, iclass 31, count 2 2006.201.22:52:30.72#ibcon#about to read 6, iclass 31, count 2 2006.201.22:52:30.72#ibcon#read 6, iclass 31, count 2 2006.201.22:52:30.72#ibcon#end of sib2, iclass 31, count 2 2006.201.22:52:30.72#ibcon#*after write, iclass 31, count 2 2006.201.22:52:30.72#ibcon#*before return 0, iclass 31, count 2 2006.201.22:52:30.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:52:30.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.22:52:30.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.22:52:30.72#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:30.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:52:30.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:52:30.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:52:30.84#ibcon#enter wrdev, iclass 31, count 0 2006.201.22:52:30.84#ibcon#first serial, iclass 31, count 0 2006.201.22:52:30.84#ibcon#enter sib2, iclass 31, count 0 2006.201.22:52:30.84#ibcon#flushed, iclass 31, count 0 2006.201.22:52:30.84#ibcon#about to write, iclass 31, count 0 2006.201.22:52:30.84#ibcon#wrote, iclass 31, count 0 2006.201.22:52:30.84#ibcon#about to read 3, iclass 31, count 0 2006.201.22:52:30.86#ibcon#read 3, iclass 31, count 0 2006.201.22:52:30.86#ibcon#about to read 4, iclass 31, count 0 2006.201.22:52:30.86#ibcon#read 4, iclass 31, count 0 2006.201.22:52:30.86#ibcon#about to read 5, iclass 31, count 0 2006.201.22:52:30.86#ibcon#read 5, iclass 31, count 0 2006.201.22:52:30.86#ibcon#about to read 6, iclass 31, count 0 2006.201.22:52:30.86#ibcon#read 6, iclass 31, count 0 2006.201.22:52:30.86#ibcon#end of sib2, iclass 31, count 0 2006.201.22:52:30.86#ibcon#*mode == 0, iclass 31, count 0 2006.201.22:52:30.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.22:52:30.86#ibcon#[27=USB\r\n] 2006.201.22:52:30.86#ibcon#*before write, iclass 31, count 0 2006.201.22:52:30.86#ibcon#enter sib2, iclass 31, count 0 2006.201.22:52:30.86#ibcon#flushed, iclass 31, count 0 2006.201.22:52:30.86#ibcon#about to write, iclass 31, count 0 2006.201.22:52:30.86#ibcon#wrote, iclass 31, count 0 2006.201.22:52:30.86#ibcon#about to read 3, iclass 31, count 0 2006.201.22:52:30.89#ibcon#read 3, iclass 31, count 0 2006.201.22:52:30.89#ibcon#about to read 4, iclass 31, count 0 2006.201.22:52:30.89#ibcon#read 4, iclass 31, count 0 2006.201.22:52:30.89#ibcon#about to read 5, iclass 31, count 0 2006.201.22:52:30.89#ibcon#read 5, iclass 31, count 0 2006.201.22:52:30.89#ibcon#about to read 6, iclass 31, count 0 2006.201.22:52:30.89#ibcon#read 6, iclass 31, count 0 2006.201.22:52:30.89#ibcon#end of sib2, iclass 31, count 0 2006.201.22:52:30.89#ibcon#*after write, iclass 31, count 0 2006.201.22:52:30.89#ibcon#*before return 0, iclass 31, count 0 2006.201.22:52:30.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:52:30.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.22:52:30.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.22:52:30.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.22:52:30.89$vck44/vblo=2,634.99 2006.201.22:52:30.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.22:52:30.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.22:52:30.89#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:30.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:30.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:30.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:30.89#ibcon#enter wrdev, iclass 33, count 0 2006.201.22:52:30.89#ibcon#first serial, iclass 33, count 0 2006.201.22:52:30.89#ibcon#enter sib2, iclass 33, count 0 2006.201.22:52:30.89#ibcon#flushed, iclass 33, count 0 2006.201.22:52:30.89#ibcon#about to write, iclass 33, count 0 2006.201.22:52:30.89#ibcon#wrote, iclass 33, count 0 2006.201.22:52:30.89#ibcon#about to read 3, iclass 33, count 0 2006.201.22:52:30.91#ibcon#read 3, iclass 33, count 0 2006.201.22:52:30.91#ibcon#about to read 4, iclass 33, count 0 2006.201.22:52:30.91#ibcon#read 4, iclass 33, count 0 2006.201.22:52:30.91#ibcon#about to read 5, iclass 33, count 0 2006.201.22:52:30.91#ibcon#read 5, iclass 33, count 0 2006.201.22:52:30.91#ibcon#about to read 6, iclass 33, count 0 2006.201.22:52:30.91#ibcon#read 6, iclass 33, count 0 2006.201.22:52:30.91#ibcon#end of sib2, iclass 33, count 0 2006.201.22:52:30.91#ibcon#*mode == 0, iclass 33, count 0 2006.201.22:52:30.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.22:52:30.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.22:52:30.91#ibcon#*before write, iclass 33, count 0 2006.201.22:52:30.91#ibcon#enter sib2, iclass 33, count 0 2006.201.22:52:30.91#ibcon#flushed, iclass 33, count 0 2006.201.22:52:30.91#ibcon#about to write, iclass 33, count 0 2006.201.22:52:30.91#ibcon#wrote, iclass 33, count 0 2006.201.22:52:30.91#ibcon#about to read 3, iclass 33, count 0 2006.201.22:52:30.95#ibcon#read 3, iclass 33, count 0 2006.201.22:52:30.95#ibcon#about to read 4, iclass 33, count 0 2006.201.22:52:30.95#ibcon#read 4, iclass 33, count 0 2006.201.22:52:30.95#ibcon#about to read 5, iclass 33, count 0 2006.201.22:52:30.95#ibcon#read 5, iclass 33, count 0 2006.201.22:52:30.95#ibcon#about to read 6, iclass 33, count 0 2006.201.22:52:30.95#ibcon#read 6, iclass 33, count 0 2006.201.22:52:30.95#ibcon#end of sib2, iclass 33, count 0 2006.201.22:52:30.95#ibcon#*after write, iclass 33, count 0 2006.201.22:52:30.95#ibcon#*before return 0, iclass 33, count 0 2006.201.22:52:30.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:30.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.22:52:30.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.22:52:30.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.22:52:30.95$vck44/vb=2,5 2006.201.22:52:30.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.22:52:30.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.22:52:30.95#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:30.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:31.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:31.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:31.01#ibcon#enter wrdev, iclass 35, count 2 2006.201.22:52:31.01#ibcon#first serial, iclass 35, count 2 2006.201.22:52:31.01#ibcon#enter sib2, iclass 35, count 2 2006.201.22:52:31.01#ibcon#flushed, iclass 35, count 2 2006.201.22:52:31.01#ibcon#about to write, iclass 35, count 2 2006.201.22:52:31.01#ibcon#wrote, iclass 35, count 2 2006.201.22:52:31.01#ibcon#about to read 3, iclass 35, count 2 2006.201.22:52:31.02#abcon#<5=/04 1.8 3.3 20.041001001.4\r\n> 2006.201.22:52:31.03#ibcon#read 3, iclass 35, count 2 2006.201.22:52:31.03#ibcon#about to read 4, iclass 35, count 2 2006.201.22:52:31.03#ibcon#read 4, iclass 35, count 2 2006.201.22:52:31.03#ibcon#about to read 5, iclass 35, count 2 2006.201.22:52:31.03#ibcon#read 5, iclass 35, count 2 2006.201.22:52:31.03#ibcon#about to read 6, iclass 35, count 2 2006.201.22:52:31.03#ibcon#read 6, iclass 35, count 2 2006.201.22:52:31.03#ibcon#end of sib2, iclass 35, count 2 2006.201.22:52:31.03#ibcon#*mode == 0, iclass 35, count 2 2006.201.22:52:31.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.22:52:31.03#ibcon#[27=AT02-05\r\n] 2006.201.22:52:31.03#ibcon#*before write, iclass 35, count 2 2006.201.22:52:31.03#ibcon#enter sib2, iclass 35, count 2 2006.201.22:52:31.03#ibcon#flushed, iclass 35, count 2 2006.201.22:52:31.03#ibcon#about to write, iclass 35, count 2 2006.201.22:52:31.03#ibcon#wrote, iclass 35, count 2 2006.201.22:52:31.03#ibcon#about to read 3, iclass 35, count 2 2006.201.22:52:31.04#abcon#{5=INTERFACE CLEAR} 2006.201.22:52:31.06#ibcon#read 3, iclass 35, count 2 2006.201.22:52:31.06#ibcon#about to read 4, iclass 35, count 2 2006.201.22:52:31.06#ibcon#read 4, iclass 35, count 2 2006.201.22:52:31.06#ibcon#about to read 5, iclass 35, count 2 2006.201.22:52:31.06#ibcon#read 5, iclass 35, count 2 2006.201.22:52:31.06#ibcon#about to read 6, iclass 35, count 2 2006.201.22:52:31.06#ibcon#read 6, iclass 35, count 2 2006.201.22:52:31.06#ibcon#end of sib2, iclass 35, count 2 2006.201.22:52:31.06#ibcon#*after write, iclass 35, count 2 2006.201.22:52:31.06#ibcon#*before return 0, iclass 35, count 2 2006.201.22:52:31.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:31.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.22:52:31.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.22:52:31.06#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:31.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:31.10#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:52:31.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:31.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:31.18#ibcon#enter wrdev, iclass 35, count 0 2006.201.22:52:31.18#ibcon#first serial, iclass 35, count 0 2006.201.22:52:31.18#ibcon#enter sib2, iclass 35, count 0 2006.201.22:52:31.18#ibcon#flushed, iclass 35, count 0 2006.201.22:52:31.18#ibcon#about to write, iclass 35, count 0 2006.201.22:52:31.18#ibcon#wrote, iclass 35, count 0 2006.201.22:52:31.18#ibcon#about to read 3, iclass 35, count 0 2006.201.22:52:31.20#ibcon#read 3, iclass 35, count 0 2006.201.22:52:31.20#ibcon#about to read 4, iclass 35, count 0 2006.201.22:52:31.20#ibcon#read 4, iclass 35, count 0 2006.201.22:52:31.20#ibcon#about to read 5, iclass 35, count 0 2006.201.22:52:31.20#ibcon#read 5, iclass 35, count 0 2006.201.22:52:31.20#ibcon#about to read 6, iclass 35, count 0 2006.201.22:52:31.20#ibcon#read 6, iclass 35, count 0 2006.201.22:52:31.20#ibcon#end of sib2, iclass 35, count 0 2006.201.22:52:31.20#ibcon#*mode == 0, iclass 35, count 0 2006.201.22:52:31.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.22:52:31.20#ibcon#[27=USB\r\n] 2006.201.22:52:31.20#ibcon#*before write, iclass 35, count 0 2006.201.22:52:31.20#ibcon#enter sib2, iclass 35, count 0 2006.201.22:52:31.20#ibcon#flushed, iclass 35, count 0 2006.201.22:52:31.20#ibcon#about to write, iclass 35, count 0 2006.201.22:52:31.20#ibcon#wrote, iclass 35, count 0 2006.201.22:52:31.20#ibcon#about to read 3, iclass 35, count 0 2006.201.22:52:31.23#ibcon#read 3, iclass 35, count 0 2006.201.22:52:31.23#ibcon#about to read 4, iclass 35, count 0 2006.201.22:52:31.23#ibcon#read 4, iclass 35, count 0 2006.201.22:52:31.23#ibcon#about to read 5, iclass 35, count 0 2006.201.22:52:31.23#ibcon#read 5, iclass 35, count 0 2006.201.22:52:31.23#ibcon#about to read 6, iclass 35, count 0 2006.201.22:52:31.23#ibcon#read 6, iclass 35, count 0 2006.201.22:52:31.23#ibcon#end of sib2, iclass 35, count 0 2006.201.22:52:31.23#ibcon#*after write, iclass 35, count 0 2006.201.22:52:31.23#ibcon#*before return 0, iclass 35, count 0 2006.201.22:52:31.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:31.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.22:52:31.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.22:52:31.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.22:52:31.23$vck44/vblo=3,649.99 2006.201.22:52:31.23#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.22:52:31.23#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.22:52:31.23#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:31.23#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:31.23#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:31.23#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:31.23#ibcon#enter wrdev, iclass 2, count 0 2006.201.22:52:31.23#ibcon#first serial, iclass 2, count 0 2006.201.22:52:31.23#ibcon#enter sib2, iclass 2, count 0 2006.201.22:52:31.23#ibcon#flushed, iclass 2, count 0 2006.201.22:52:31.23#ibcon#about to write, iclass 2, count 0 2006.201.22:52:31.23#ibcon#wrote, iclass 2, count 0 2006.201.22:52:31.23#ibcon#about to read 3, iclass 2, count 0 2006.201.22:52:31.25#ibcon#read 3, iclass 2, count 0 2006.201.22:52:31.25#ibcon#about to read 4, iclass 2, count 0 2006.201.22:52:31.25#ibcon#read 4, iclass 2, count 0 2006.201.22:52:31.25#ibcon#about to read 5, iclass 2, count 0 2006.201.22:52:31.25#ibcon#read 5, iclass 2, count 0 2006.201.22:52:31.25#ibcon#about to read 6, iclass 2, count 0 2006.201.22:52:31.25#ibcon#read 6, iclass 2, count 0 2006.201.22:52:31.25#ibcon#end of sib2, iclass 2, count 0 2006.201.22:52:31.25#ibcon#*mode == 0, iclass 2, count 0 2006.201.22:52:31.25#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.22:52:31.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.22:52:31.25#ibcon#*before write, iclass 2, count 0 2006.201.22:52:31.25#ibcon#enter sib2, iclass 2, count 0 2006.201.22:52:31.25#ibcon#flushed, iclass 2, count 0 2006.201.22:52:31.25#ibcon#about to write, iclass 2, count 0 2006.201.22:52:31.25#ibcon#wrote, iclass 2, count 0 2006.201.22:52:31.25#ibcon#about to read 3, iclass 2, count 0 2006.201.22:52:31.29#ibcon#read 3, iclass 2, count 0 2006.201.22:52:31.29#ibcon#about to read 4, iclass 2, count 0 2006.201.22:52:31.29#ibcon#read 4, iclass 2, count 0 2006.201.22:52:31.29#ibcon#about to read 5, iclass 2, count 0 2006.201.22:52:31.29#ibcon#read 5, iclass 2, count 0 2006.201.22:52:31.29#ibcon#about to read 6, iclass 2, count 0 2006.201.22:52:31.29#ibcon#read 6, iclass 2, count 0 2006.201.22:52:31.29#ibcon#end of sib2, iclass 2, count 0 2006.201.22:52:31.29#ibcon#*after write, iclass 2, count 0 2006.201.22:52:31.29#ibcon#*before return 0, iclass 2, count 0 2006.201.22:52:31.29#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:31.29#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.22:52:31.29#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.22:52:31.29#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.22:52:31.29$vck44/vb=3,4 2006.201.22:52:31.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.22:52:31.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.22:52:31.29#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:31.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:31.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:31.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:31.35#ibcon#enter wrdev, iclass 5, count 2 2006.201.22:52:31.35#ibcon#first serial, iclass 5, count 2 2006.201.22:52:31.35#ibcon#enter sib2, iclass 5, count 2 2006.201.22:52:31.35#ibcon#flushed, iclass 5, count 2 2006.201.22:52:31.35#ibcon#about to write, iclass 5, count 2 2006.201.22:52:31.35#ibcon#wrote, iclass 5, count 2 2006.201.22:52:31.35#ibcon#about to read 3, iclass 5, count 2 2006.201.22:52:31.37#ibcon#read 3, iclass 5, count 2 2006.201.22:52:31.37#ibcon#about to read 4, iclass 5, count 2 2006.201.22:52:31.37#ibcon#read 4, iclass 5, count 2 2006.201.22:52:31.37#ibcon#about to read 5, iclass 5, count 2 2006.201.22:52:31.37#ibcon#read 5, iclass 5, count 2 2006.201.22:52:31.37#ibcon#about to read 6, iclass 5, count 2 2006.201.22:52:31.37#ibcon#read 6, iclass 5, count 2 2006.201.22:52:31.37#ibcon#end of sib2, iclass 5, count 2 2006.201.22:52:31.37#ibcon#*mode == 0, iclass 5, count 2 2006.201.22:52:31.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.22:52:31.37#ibcon#[27=AT03-04\r\n] 2006.201.22:52:31.37#ibcon#*before write, iclass 5, count 2 2006.201.22:52:31.37#ibcon#enter sib2, iclass 5, count 2 2006.201.22:52:31.37#ibcon#flushed, iclass 5, count 2 2006.201.22:52:31.37#ibcon#about to write, iclass 5, count 2 2006.201.22:52:31.37#ibcon#wrote, iclass 5, count 2 2006.201.22:52:31.37#ibcon#about to read 3, iclass 5, count 2 2006.201.22:52:31.40#ibcon#read 3, iclass 5, count 2 2006.201.22:52:31.40#ibcon#about to read 4, iclass 5, count 2 2006.201.22:52:31.40#ibcon#read 4, iclass 5, count 2 2006.201.22:52:31.40#ibcon#about to read 5, iclass 5, count 2 2006.201.22:52:31.40#ibcon#read 5, iclass 5, count 2 2006.201.22:52:31.40#ibcon#about to read 6, iclass 5, count 2 2006.201.22:52:31.40#ibcon#read 6, iclass 5, count 2 2006.201.22:52:31.40#ibcon#end of sib2, iclass 5, count 2 2006.201.22:52:31.40#ibcon#*after write, iclass 5, count 2 2006.201.22:52:31.40#ibcon#*before return 0, iclass 5, count 2 2006.201.22:52:31.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:31.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.22:52:31.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.22:52:31.40#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:31.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:31.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:31.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:31.52#ibcon#enter wrdev, iclass 5, count 0 2006.201.22:52:31.52#ibcon#first serial, iclass 5, count 0 2006.201.22:52:31.52#ibcon#enter sib2, iclass 5, count 0 2006.201.22:52:31.52#ibcon#flushed, iclass 5, count 0 2006.201.22:52:31.52#ibcon#about to write, iclass 5, count 0 2006.201.22:52:31.52#ibcon#wrote, iclass 5, count 0 2006.201.22:52:31.52#ibcon#about to read 3, iclass 5, count 0 2006.201.22:52:31.54#ibcon#read 3, iclass 5, count 0 2006.201.22:52:31.54#ibcon#about to read 4, iclass 5, count 0 2006.201.22:52:31.54#ibcon#read 4, iclass 5, count 0 2006.201.22:52:31.54#ibcon#about to read 5, iclass 5, count 0 2006.201.22:52:31.54#ibcon#read 5, iclass 5, count 0 2006.201.22:52:31.54#ibcon#about to read 6, iclass 5, count 0 2006.201.22:52:31.54#ibcon#read 6, iclass 5, count 0 2006.201.22:52:31.54#ibcon#end of sib2, iclass 5, count 0 2006.201.22:52:31.54#ibcon#*mode == 0, iclass 5, count 0 2006.201.22:52:31.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.22:52:31.54#ibcon#[27=USB\r\n] 2006.201.22:52:31.54#ibcon#*before write, iclass 5, count 0 2006.201.22:52:31.54#ibcon#enter sib2, iclass 5, count 0 2006.201.22:52:31.54#ibcon#flushed, iclass 5, count 0 2006.201.22:52:31.54#ibcon#about to write, iclass 5, count 0 2006.201.22:52:31.54#ibcon#wrote, iclass 5, count 0 2006.201.22:52:31.54#ibcon#about to read 3, iclass 5, count 0 2006.201.22:52:31.57#ibcon#read 3, iclass 5, count 0 2006.201.22:52:31.57#ibcon#about to read 4, iclass 5, count 0 2006.201.22:52:31.57#ibcon#read 4, iclass 5, count 0 2006.201.22:52:31.57#ibcon#about to read 5, iclass 5, count 0 2006.201.22:52:31.57#ibcon#read 5, iclass 5, count 0 2006.201.22:52:31.57#ibcon#about to read 6, iclass 5, count 0 2006.201.22:52:31.57#ibcon#read 6, iclass 5, count 0 2006.201.22:52:31.57#ibcon#end of sib2, iclass 5, count 0 2006.201.22:52:31.57#ibcon#*after write, iclass 5, count 0 2006.201.22:52:31.57#ibcon#*before return 0, iclass 5, count 0 2006.201.22:52:31.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:31.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.22:52:31.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.22:52:31.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.22:52:31.57$vck44/vblo=4,679.99 2006.201.22:52:31.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.22:52:31.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.22:52:31.57#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:31.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:31.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:31.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:31.57#ibcon#enter wrdev, iclass 7, count 0 2006.201.22:52:31.57#ibcon#first serial, iclass 7, count 0 2006.201.22:52:31.57#ibcon#enter sib2, iclass 7, count 0 2006.201.22:52:31.57#ibcon#flushed, iclass 7, count 0 2006.201.22:52:31.57#ibcon#about to write, iclass 7, count 0 2006.201.22:52:31.57#ibcon#wrote, iclass 7, count 0 2006.201.22:52:31.57#ibcon#about to read 3, iclass 7, count 0 2006.201.22:52:31.59#ibcon#read 3, iclass 7, count 0 2006.201.22:52:31.59#ibcon#about to read 4, iclass 7, count 0 2006.201.22:52:31.59#ibcon#read 4, iclass 7, count 0 2006.201.22:52:31.59#ibcon#about to read 5, iclass 7, count 0 2006.201.22:52:31.59#ibcon#read 5, iclass 7, count 0 2006.201.22:52:31.59#ibcon#about to read 6, iclass 7, count 0 2006.201.22:52:31.59#ibcon#read 6, iclass 7, count 0 2006.201.22:52:31.59#ibcon#end of sib2, iclass 7, count 0 2006.201.22:52:31.59#ibcon#*mode == 0, iclass 7, count 0 2006.201.22:52:31.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.22:52:31.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.22:52:31.59#ibcon#*before write, iclass 7, count 0 2006.201.22:52:31.59#ibcon#enter sib2, iclass 7, count 0 2006.201.22:52:31.59#ibcon#flushed, iclass 7, count 0 2006.201.22:52:31.59#ibcon#about to write, iclass 7, count 0 2006.201.22:52:31.59#ibcon#wrote, iclass 7, count 0 2006.201.22:52:31.59#ibcon#about to read 3, iclass 7, count 0 2006.201.22:52:31.64#ibcon#read 3, iclass 7, count 0 2006.201.22:52:31.64#ibcon#about to read 4, iclass 7, count 0 2006.201.22:52:31.64#ibcon#read 4, iclass 7, count 0 2006.201.22:52:31.64#ibcon#about to read 5, iclass 7, count 0 2006.201.22:52:31.64#ibcon#read 5, iclass 7, count 0 2006.201.22:52:31.64#ibcon#about to read 6, iclass 7, count 0 2006.201.22:52:31.64#ibcon#read 6, iclass 7, count 0 2006.201.22:52:31.64#ibcon#end of sib2, iclass 7, count 0 2006.201.22:52:31.64#ibcon#*after write, iclass 7, count 0 2006.201.22:52:31.64#ibcon#*before return 0, iclass 7, count 0 2006.201.22:52:31.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:31.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.22:52:31.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.22:52:31.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.22:52:31.64$vck44/vb=4,5 2006.201.22:52:31.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.22:52:31.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.22:52:31.64#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:31.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:31.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:31.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:31.69#ibcon#enter wrdev, iclass 11, count 2 2006.201.22:52:31.69#ibcon#first serial, iclass 11, count 2 2006.201.22:52:31.69#ibcon#enter sib2, iclass 11, count 2 2006.201.22:52:31.69#ibcon#flushed, iclass 11, count 2 2006.201.22:52:31.69#ibcon#about to write, iclass 11, count 2 2006.201.22:52:31.69#ibcon#wrote, iclass 11, count 2 2006.201.22:52:31.69#ibcon#about to read 3, iclass 11, count 2 2006.201.22:52:31.71#ibcon#read 3, iclass 11, count 2 2006.201.22:52:31.71#ibcon#about to read 4, iclass 11, count 2 2006.201.22:52:31.71#ibcon#read 4, iclass 11, count 2 2006.201.22:52:31.71#ibcon#about to read 5, iclass 11, count 2 2006.201.22:52:31.71#ibcon#read 5, iclass 11, count 2 2006.201.22:52:31.71#ibcon#about to read 6, iclass 11, count 2 2006.201.22:52:31.71#ibcon#read 6, iclass 11, count 2 2006.201.22:52:31.71#ibcon#end of sib2, iclass 11, count 2 2006.201.22:52:31.71#ibcon#*mode == 0, iclass 11, count 2 2006.201.22:52:31.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.22:52:31.71#ibcon#[27=AT04-05\r\n] 2006.201.22:52:31.71#ibcon#*before write, iclass 11, count 2 2006.201.22:52:31.71#ibcon#enter sib2, iclass 11, count 2 2006.201.22:52:31.71#ibcon#flushed, iclass 11, count 2 2006.201.22:52:31.71#ibcon#about to write, iclass 11, count 2 2006.201.22:52:31.71#ibcon#wrote, iclass 11, count 2 2006.201.22:52:31.71#ibcon#about to read 3, iclass 11, count 2 2006.201.22:52:31.74#ibcon#read 3, iclass 11, count 2 2006.201.22:52:31.74#ibcon#about to read 4, iclass 11, count 2 2006.201.22:52:31.74#ibcon#read 4, iclass 11, count 2 2006.201.22:52:31.74#ibcon#about to read 5, iclass 11, count 2 2006.201.22:52:31.74#ibcon#read 5, iclass 11, count 2 2006.201.22:52:31.74#ibcon#about to read 6, iclass 11, count 2 2006.201.22:52:31.74#ibcon#read 6, iclass 11, count 2 2006.201.22:52:31.74#ibcon#end of sib2, iclass 11, count 2 2006.201.22:52:31.74#ibcon#*after write, iclass 11, count 2 2006.201.22:52:31.74#ibcon#*before return 0, iclass 11, count 2 2006.201.22:52:31.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:31.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.22:52:31.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.22:52:31.74#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:31.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:31.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:31.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:31.86#ibcon#enter wrdev, iclass 11, count 0 2006.201.22:52:31.86#ibcon#first serial, iclass 11, count 0 2006.201.22:52:31.86#ibcon#enter sib2, iclass 11, count 0 2006.201.22:52:31.86#ibcon#flushed, iclass 11, count 0 2006.201.22:52:31.86#ibcon#about to write, iclass 11, count 0 2006.201.22:52:31.86#ibcon#wrote, iclass 11, count 0 2006.201.22:52:31.86#ibcon#about to read 3, iclass 11, count 0 2006.201.22:52:31.88#ibcon#read 3, iclass 11, count 0 2006.201.22:52:31.88#ibcon#about to read 4, iclass 11, count 0 2006.201.22:52:31.88#ibcon#read 4, iclass 11, count 0 2006.201.22:52:31.88#ibcon#about to read 5, iclass 11, count 0 2006.201.22:52:31.88#ibcon#read 5, iclass 11, count 0 2006.201.22:52:31.88#ibcon#about to read 6, iclass 11, count 0 2006.201.22:52:31.88#ibcon#read 6, iclass 11, count 0 2006.201.22:52:31.88#ibcon#end of sib2, iclass 11, count 0 2006.201.22:52:31.88#ibcon#*mode == 0, iclass 11, count 0 2006.201.22:52:31.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.22:52:31.88#ibcon#[27=USB\r\n] 2006.201.22:52:31.88#ibcon#*before write, iclass 11, count 0 2006.201.22:52:31.88#ibcon#enter sib2, iclass 11, count 0 2006.201.22:52:31.88#ibcon#flushed, iclass 11, count 0 2006.201.22:52:31.88#ibcon#about to write, iclass 11, count 0 2006.201.22:52:31.88#ibcon#wrote, iclass 11, count 0 2006.201.22:52:31.88#ibcon#about to read 3, iclass 11, count 0 2006.201.22:52:31.91#ibcon#read 3, iclass 11, count 0 2006.201.22:52:31.91#ibcon#about to read 4, iclass 11, count 0 2006.201.22:52:31.91#ibcon#read 4, iclass 11, count 0 2006.201.22:52:31.91#ibcon#about to read 5, iclass 11, count 0 2006.201.22:52:31.91#ibcon#read 5, iclass 11, count 0 2006.201.22:52:31.91#ibcon#about to read 6, iclass 11, count 0 2006.201.22:52:31.91#ibcon#read 6, iclass 11, count 0 2006.201.22:52:31.91#ibcon#end of sib2, iclass 11, count 0 2006.201.22:52:31.91#ibcon#*after write, iclass 11, count 0 2006.201.22:52:31.91#ibcon#*before return 0, iclass 11, count 0 2006.201.22:52:31.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:31.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.22:52:31.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.22:52:31.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.22:52:31.91$vck44/vblo=5,709.99 2006.201.22:52:31.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.22:52:31.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.22:52:31.91#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:31.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:31.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:31.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:31.91#ibcon#enter wrdev, iclass 13, count 0 2006.201.22:52:31.91#ibcon#first serial, iclass 13, count 0 2006.201.22:52:31.91#ibcon#enter sib2, iclass 13, count 0 2006.201.22:52:31.91#ibcon#flushed, iclass 13, count 0 2006.201.22:52:31.91#ibcon#about to write, iclass 13, count 0 2006.201.22:52:31.91#ibcon#wrote, iclass 13, count 0 2006.201.22:52:31.91#ibcon#about to read 3, iclass 13, count 0 2006.201.22:52:31.93#ibcon#read 3, iclass 13, count 0 2006.201.22:52:31.93#ibcon#about to read 4, iclass 13, count 0 2006.201.22:52:31.93#ibcon#read 4, iclass 13, count 0 2006.201.22:52:31.93#ibcon#about to read 5, iclass 13, count 0 2006.201.22:52:31.93#ibcon#read 5, iclass 13, count 0 2006.201.22:52:31.93#ibcon#about to read 6, iclass 13, count 0 2006.201.22:52:31.93#ibcon#read 6, iclass 13, count 0 2006.201.22:52:31.93#ibcon#end of sib2, iclass 13, count 0 2006.201.22:52:31.93#ibcon#*mode == 0, iclass 13, count 0 2006.201.22:52:31.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.22:52:31.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.22:52:31.93#ibcon#*before write, iclass 13, count 0 2006.201.22:52:31.93#ibcon#enter sib2, iclass 13, count 0 2006.201.22:52:31.93#ibcon#flushed, iclass 13, count 0 2006.201.22:52:31.93#ibcon#about to write, iclass 13, count 0 2006.201.22:52:31.93#ibcon#wrote, iclass 13, count 0 2006.201.22:52:31.93#ibcon#about to read 3, iclass 13, count 0 2006.201.22:52:31.97#ibcon#read 3, iclass 13, count 0 2006.201.22:52:31.97#ibcon#about to read 4, iclass 13, count 0 2006.201.22:52:31.97#ibcon#read 4, iclass 13, count 0 2006.201.22:52:31.97#ibcon#about to read 5, iclass 13, count 0 2006.201.22:52:31.97#ibcon#read 5, iclass 13, count 0 2006.201.22:52:31.97#ibcon#about to read 6, iclass 13, count 0 2006.201.22:52:31.97#ibcon#read 6, iclass 13, count 0 2006.201.22:52:31.97#ibcon#end of sib2, iclass 13, count 0 2006.201.22:52:31.97#ibcon#*after write, iclass 13, count 0 2006.201.22:52:31.97#ibcon#*before return 0, iclass 13, count 0 2006.201.22:52:31.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:31.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.22:52:31.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.22:52:31.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.22:52:31.97$vck44/vb=5,4 2006.201.22:52:31.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.22:52:31.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.22:52:31.97#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:31.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:32.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:32.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:32.03#ibcon#enter wrdev, iclass 15, count 2 2006.201.22:52:32.03#ibcon#first serial, iclass 15, count 2 2006.201.22:52:32.03#ibcon#enter sib2, iclass 15, count 2 2006.201.22:52:32.03#ibcon#flushed, iclass 15, count 2 2006.201.22:52:32.03#ibcon#about to write, iclass 15, count 2 2006.201.22:52:32.03#ibcon#wrote, iclass 15, count 2 2006.201.22:52:32.03#ibcon#about to read 3, iclass 15, count 2 2006.201.22:52:32.05#ibcon#read 3, iclass 15, count 2 2006.201.22:52:32.05#ibcon#about to read 4, iclass 15, count 2 2006.201.22:52:32.05#ibcon#read 4, iclass 15, count 2 2006.201.22:52:32.05#ibcon#about to read 5, iclass 15, count 2 2006.201.22:52:32.05#ibcon#read 5, iclass 15, count 2 2006.201.22:52:32.05#ibcon#about to read 6, iclass 15, count 2 2006.201.22:52:32.05#ibcon#read 6, iclass 15, count 2 2006.201.22:52:32.05#ibcon#end of sib2, iclass 15, count 2 2006.201.22:52:32.05#ibcon#*mode == 0, iclass 15, count 2 2006.201.22:52:32.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.22:52:32.05#ibcon#[27=AT05-04\r\n] 2006.201.22:52:32.05#ibcon#*before write, iclass 15, count 2 2006.201.22:52:32.05#ibcon#enter sib2, iclass 15, count 2 2006.201.22:52:32.05#ibcon#flushed, iclass 15, count 2 2006.201.22:52:32.05#ibcon#about to write, iclass 15, count 2 2006.201.22:52:32.05#ibcon#wrote, iclass 15, count 2 2006.201.22:52:32.05#ibcon#about to read 3, iclass 15, count 2 2006.201.22:52:32.08#ibcon#read 3, iclass 15, count 2 2006.201.22:52:32.08#ibcon#about to read 4, iclass 15, count 2 2006.201.22:52:32.08#ibcon#read 4, iclass 15, count 2 2006.201.22:52:32.08#ibcon#about to read 5, iclass 15, count 2 2006.201.22:52:32.08#ibcon#read 5, iclass 15, count 2 2006.201.22:52:32.08#ibcon#about to read 6, iclass 15, count 2 2006.201.22:52:32.08#ibcon#read 6, iclass 15, count 2 2006.201.22:52:32.08#ibcon#end of sib2, iclass 15, count 2 2006.201.22:52:32.08#ibcon#*after write, iclass 15, count 2 2006.201.22:52:32.08#ibcon#*before return 0, iclass 15, count 2 2006.201.22:52:32.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:32.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.22:52:32.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.22:52:32.08#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:32.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:32.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:32.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:32.20#ibcon#enter wrdev, iclass 15, count 0 2006.201.22:52:32.20#ibcon#first serial, iclass 15, count 0 2006.201.22:52:32.20#ibcon#enter sib2, iclass 15, count 0 2006.201.22:52:32.20#ibcon#flushed, iclass 15, count 0 2006.201.22:52:32.20#ibcon#about to write, iclass 15, count 0 2006.201.22:52:32.20#ibcon#wrote, iclass 15, count 0 2006.201.22:52:32.20#ibcon#about to read 3, iclass 15, count 0 2006.201.22:52:32.22#ibcon#read 3, iclass 15, count 0 2006.201.22:52:32.22#ibcon#about to read 4, iclass 15, count 0 2006.201.22:52:32.22#ibcon#read 4, iclass 15, count 0 2006.201.22:52:32.22#ibcon#about to read 5, iclass 15, count 0 2006.201.22:52:32.22#ibcon#read 5, iclass 15, count 0 2006.201.22:52:32.22#ibcon#about to read 6, iclass 15, count 0 2006.201.22:52:32.22#ibcon#read 6, iclass 15, count 0 2006.201.22:52:32.22#ibcon#end of sib2, iclass 15, count 0 2006.201.22:52:32.22#ibcon#*mode == 0, iclass 15, count 0 2006.201.22:52:32.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.22:52:32.22#ibcon#[27=USB\r\n] 2006.201.22:52:32.22#ibcon#*before write, iclass 15, count 0 2006.201.22:52:32.22#ibcon#enter sib2, iclass 15, count 0 2006.201.22:52:32.22#ibcon#flushed, iclass 15, count 0 2006.201.22:52:32.22#ibcon#about to write, iclass 15, count 0 2006.201.22:52:32.22#ibcon#wrote, iclass 15, count 0 2006.201.22:52:32.22#ibcon#about to read 3, iclass 15, count 0 2006.201.22:52:32.25#ibcon#read 3, iclass 15, count 0 2006.201.22:52:32.25#ibcon#about to read 4, iclass 15, count 0 2006.201.22:52:32.25#ibcon#read 4, iclass 15, count 0 2006.201.22:52:32.25#ibcon#about to read 5, iclass 15, count 0 2006.201.22:52:32.25#ibcon#read 5, iclass 15, count 0 2006.201.22:52:32.25#ibcon#about to read 6, iclass 15, count 0 2006.201.22:52:32.25#ibcon#read 6, iclass 15, count 0 2006.201.22:52:32.25#ibcon#end of sib2, iclass 15, count 0 2006.201.22:52:32.25#ibcon#*after write, iclass 15, count 0 2006.201.22:52:32.25#ibcon#*before return 0, iclass 15, count 0 2006.201.22:52:32.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:32.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.22:52:32.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.22:52:32.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.22:52:32.25$vck44/vblo=6,719.99 2006.201.22:52:32.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.22:52:32.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.22:52:32.25#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:32.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:32.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:32.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:32.25#ibcon#enter wrdev, iclass 17, count 0 2006.201.22:52:32.25#ibcon#first serial, iclass 17, count 0 2006.201.22:52:32.25#ibcon#enter sib2, iclass 17, count 0 2006.201.22:52:32.25#ibcon#flushed, iclass 17, count 0 2006.201.22:52:32.25#ibcon#about to write, iclass 17, count 0 2006.201.22:52:32.25#ibcon#wrote, iclass 17, count 0 2006.201.22:52:32.25#ibcon#about to read 3, iclass 17, count 0 2006.201.22:52:32.27#ibcon#read 3, iclass 17, count 0 2006.201.22:52:32.27#ibcon#about to read 4, iclass 17, count 0 2006.201.22:52:32.27#ibcon#read 4, iclass 17, count 0 2006.201.22:52:32.27#ibcon#about to read 5, iclass 17, count 0 2006.201.22:52:32.27#ibcon#read 5, iclass 17, count 0 2006.201.22:52:32.27#ibcon#about to read 6, iclass 17, count 0 2006.201.22:52:32.27#ibcon#read 6, iclass 17, count 0 2006.201.22:52:32.27#ibcon#end of sib2, iclass 17, count 0 2006.201.22:52:32.27#ibcon#*mode == 0, iclass 17, count 0 2006.201.22:52:32.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.22:52:32.27#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.22:52:32.27#ibcon#*before write, iclass 17, count 0 2006.201.22:52:32.27#ibcon#enter sib2, iclass 17, count 0 2006.201.22:52:32.27#ibcon#flushed, iclass 17, count 0 2006.201.22:52:32.27#ibcon#about to write, iclass 17, count 0 2006.201.22:52:32.27#ibcon#wrote, iclass 17, count 0 2006.201.22:52:32.27#ibcon#about to read 3, iclass 17, count 0 2006.201.22:52:32.31#ibcon#read 3, iclass 17, count 0 2006.201.22:52:32.31#ibcon#about to read 4, iclass 17, count 0 2006.201.22:52:32.31#ibcon#read 4, iclass 17, count 0 2006.201.22:52:32.31#ibcon#about to read 5, iclass 17, count 0 2006.201.22:52:32.31#ibcon#read 5, iclass 17, count 0 2006.201.22:52:32.31#ibcon#about to read 6, iclass 17, count 0 2006.201.22:52:32.31#ibcon#read 6, iclass 17, count 0 2006.201.22:52:32.31#ibcon#end of sib2, iclass 17, count 0 2006.201.22:52:32.31#ibcon#*after write, iclass 17, count 0 2006.201.22:52:32.31#ibcon#*before return 0, iclass 17, count 0 2006.201.22:52:32.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:32.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.22:52:32.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.22:52:32.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.22:52:32.31$vck44/vb=6,4 2006.201.22:52:32.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.22:52:32.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.22:52:32.31#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:32.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:32.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:32.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:32.37#ibcon#enter wrdev, iclass 19, count 2 2006.201.22:52:32.37#ibcon#first serial, iclass 19, count 2 2006.201.22:52:32.37#ibcon#enter sib2, iclass 19, count 2 2006.201.22:52:32.37#ibcon#flushed, iclass 19, count 2 2006.201.22:52:32.37#ibcon#about to write, iclass 19, count 2 2006.201.22:52:32.37#ibcon#wrote, iclass 19, count 2 2006.201.22:52:32.37#ibcon#about to read 3, iclass 19, count 2 2006.201.22:52:32.39#ibcon#read 3, iclass 19, count 2 2006.201.22:52:32.39#ibcon#about to read 4, iclass 19, count 2 2006.201.22:52:32.39#ibcon#read 4, iclass 19, count 2 2006.201.22:52:32.39#ibcon#about to read 5, iclass 19, count 2 2006.201.22:52:32.39#ibcon#read 5, iclass 19, count 2 2006.201.22:52:32.39#ibcon#about to read 6, iclass 19, count 2 2006.201.22:52:32.39#ibcon#read 6, iclass 19, count 2 2006.201.22:52:32.39#ibcon#end of sib2, iclass 19, count 2 2006.201.22:52:32.39#ibcon#*mode == 0, iclass 19, count 2 2006.201.22:52:32.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.22:52:32.39#ibcon#[27=AT06-04\r\n] 2006.201.22:52:32.39#ibcon#*before write, iclass 19, count 2 2006.201.22:52:32.39#ibcon#enter sib2, iclass 19, count 2 2006.201.22:52:32.39#ibcon#flushed, iclass 19, count 2 2006.201.22:52:32.39#ibcon#about to write, iclass 19, count 2 2006.201.22:52:32.39#ibcon#wrote, iclass 19, count 2 2006.201.22:52:32.39#ibcon#about to read 3, iclass 19, count 2 2006.201.22:52:32.42#ibcon#read 3, iclass 19, count 2 2006.201.22:52:32.42#ibcon#about to read 4, iclass 19, count 2 2006.201.22:52:32.42#ibcon#read 4, iclass 19, count 2 2006.201.22:52:32.42#ibcon#about to read 5, iclass 19, count 2 2006.201.22:52:32.42#ibcon#read 5, iclass 19, count 2 2006.201.22:52:32.42#ibcon#about to read 6, iclass 19, count 2 2006.201.22:52:32.42#ibcon#read 6, iclass 19, count 2 2006.201.22:52:32.42#ibcon#end of sib2, iclass 19, count 2 2006.201.22:52:32.42#ibcon#*after write, iclass 19, count 2 2006.201.22:52:32.42#ibcon#*before return 0, iclass 19, count 2 2006.201.22:52:32.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:32.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.22:52:32.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.22:52:32.42#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:32.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:32.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:32.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:32.54#ibcon#enter wrdev, iclass 19, count 0 2006.201.22:52:32.54#ibcon#first serial, iclass 19, count 0 2006.201.22:52:32.54#ibcon#enter sib2, iclass 19, count 0 2006.201.22:52:32.54#ibcon#flushed, iclass 19, count 0 2006.201.22:52:32.54#ibcon#about to write, iclass 19, count 0 2006.201.22:52:32.54#ibcon#wrote, iclass 19, count 0 2006.201.22:52:32.54#ibcon#about to read 3, iclass 19, count 0 2006.201.22:52:32.56#ibcon#read 3, iclass 19, count 0 2006.201.22:52:32.56#ibcon#about to read 4, iclass 19, count 0 2006.201.22:52:32.56#ibcon#read 4, iclass 19, count 0 2006.201.22:52:32.56#ibcon#about to read 5, iclass 19, count 0 2006.201.22:52:32.56#ibcon#read 5, iclass 19, count 0 2006.201.22:52:32.56#ibcon#about to read 6, iclass 19, count 0 2006.201.22:52:32.56#ibcon#read 6, iclass 19, count 0 2006.201.22:52:32.56#ibcon#end of sib2, iclass 19, count 0 2006.201.22:52:32.56#ibcon#*mode == 0, iclass 19, count 0 2006.201.22:52:32.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.22:52:32.56#ibcon#[27=USB\r\n] 2006.201.22:52:32.56#ibcon#*before write, iclass 19, count 0 2006.201.22:52:32.56#ibcon#enter sib2, iclass 19, count 0 2006.201.22:52:32.56#ibcon#flushed, iclass 19, count 0 2006.201.22:52:32.56#ibcon#about to write, iclass 19, count 0 2006.201.22:52:32.56#ibcon#wrote, iclass 19, count 0 2006.201.22:52:32.56#ibcon#about to read 3, iclass 19, count 0 2006.201.22:52:32.59#ibcon#read 3, iclass 19, count 0 2006.201.22:52:32.59#ibcon#about to read 4, iclass 19, count 0 2006.201.22:52:32.59#ibcon#read 4, iclass 19, count 0 2006.201.22:52:32.59#ibcon#about to read 5, iclass 19, count 0 2006.201.22:52:32.59#ibcon#read 5, iclass 19, count 0 2006.201.22:52:32.59#ibcon#about to read 6, iclass 19, count 0 2006.201.22:52:32.59#ibcon#read 6, iclass 19, count 0 2006.201.22:52:32.59#ibcon#end of sib2, iclass 19, count 0 2006.201.22:52:32.59#ibcon#*after write, iclass 19, count 0 2006.201.22:52:32.59#ibcon#*before return 0, iclass 19, count 0 2006.201.22:52:32.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:32.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.22:52:32.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.22:52:32.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.22:52:32.59$vck44/vblo=7,734.99 2006.201.22:52:32.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.22:52:32.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.22:52:32.59#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:32.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:32.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:32.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:32.59#ibcon#enter wrdev, iclass 21, count 0 2006.201.22:52:32.59#ibcon#first serial, iclass 21, count 0 2006.201.22:52:32.59#ibcon#enter sib2, iclass 21, count 0 2006.201.22:52:32.59#ibcon#flushed, iclass 21, count 0 2006.201.22:52:32.59#ibcon#about to write, iclass 21, count 0 2006.201.22:52:32.59#ibcon#wrote, iclass 21, count 0 2006.201.22:52:32.59#ibcon#about to read 3, iclass 21, count 0 2006.201.22:52:32.61#ibcon#read 3, iclass 21, count 0 2006.201.22:52:32.61#ibcon#about to read 4, iclass 21, count 0 2006.201.22:52:32.61#ibcon#read 4, iclass 21, count 0 2006.201.22:52:32.61#ibcon#about to read 5, iclass 21, count 0 2006.201.22:52:32.61#ibcon#read 5, iclass 21, count 0 2006.201.22:52:32.61#ibcon#about to read 6, iclass 21, count 0 2006.201.22:52:32.61#ibcon#read 6, iclass 21, count 0 2006.201.22:52:32.61#ibcon#end of sib2, iclass 21, count 0 2006.201.22:52:32.61#ibcon#*mode == 0, iclass 21, count 0 2006.201.22:52:32.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.22:52:32.61#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.22:52:32.61#ibcon#*before write, iclass 21, count 0 2006.201.22:52:32.61#ibcon#enter sib2, iclass 21, count 0 2006.201.22:52:32.61#ibcon#flushed, iclass 21, count 0 2006.201.22:52:32.61#ibcon#about to write, iclass 21, count 0 2006.201.22:52:32.61#ibcon#wrote, iclass 21, count 0 2006.201.22:52:32.61#ibcon#about to read 3, iclass 21, count 0 2006.201.22:52:32.65#ibcon#read 3, iclass 21, count 0 2006.201.22:52:32.65#ibcon#about to read 4, iclass 21, count 0 2006.201.22:52:32.65#ibcon#read 4, iclass 21, count 0 2006.201.22:52:32.65#ibcon#about to read 5, iclass 21, count 0 2006.201.22:52:32.65#ibcon#read 5, iclass 21, count 0 2006.201.22:52:32.65#ibcon#about to read 6, iclass 21, count 0 2006.201.22:52:32.65#ibcon#read 6, iclass 21, count 0 2006.201.22:52:32.65#ibcon#end of sib2, iclass 21, count 0 2006.201.22:52:32.65#ibcon#*after write, iclass 21, count 0 2006.201.22:52:32.65#ibcon#*before return 0, iclass 21, count 0 2006.201.22:52:32.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:32.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.22:52:32.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.22:52:32.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.22:52:32.65$vck44/vb=7,4 2006.201.22:52:32.65#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.22:52:32.65#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.22:52:32.65#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:32.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:32.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:32.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:32.71#ibcon#enter wrdev, iclass 23, count 2 2006.201.22:52:32.71#ibcon#first serial, iclass 23, count 2 2006.201.22:52:32.71#ibcon#enter sib2, iclass 23, count 2 2006.201.22:52:32.71#ibcon#flushed, iclass 23, count 2 2006.201.22:52:32.71#ibcon#about to write, iclass 23, count 2 2006.201.22:52:32.71#ibcon#wrote, iclass 23, count 2 2006.201.22:52:32.71#ibcon#about to read 3, iclass 23, count 2 2006.201.22:52:32.73#ibcon#read 3, iclass 23, count 2 2006.201.22:52:32.73#ibcon#about to read 4, iclass 23, count 2 2006.201.22:52:32.73#ibcon#read 4, iclass 23, count 2 2006.201.22:52:32.73#ibcon#about to read 5, iclass 23, count 2 2006.201.22:52:32.73#ibcon#read 5, iclass 23, count 2 2006.201.22:52:32.73#ibcon#about to read 6, iclass 23, count 2 2006.201.22:52:32.73#ibcon#read 6, iclass 23, count 2 2006.201.22:52:32.73#ibcon#end of sib2, iclass 23, count 2 2006.201.22:52:32.73#ibcon#*mode == 0, iclass 23, count 2 2006.201.22:52:32.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.22:52:32.73#ibcon#[27=AT07-04\r\n] 2006.201.22:52:32.73#ibcon#*before write, iclass 23, count 2 2006.201.22:52:32.73#ibcon#enter sib2, iclass 23, count 2 2006.201.22:52:32.73#ibcon#flushed, iclass 23, count 2 2006.201.22:52:32.73#ibcon#about to write, iclass 23, count 2 2006.201.22:52:32.73#ibcon#wrote, iclass 23, count 2 2006.201.22:52:32.73#ibcon#about to read 3, iclass 23, count 2 2006.201.22:52:32.76#ibcon#read 3, iclass 23, count 2 2006.201.22:52:32.76#ibcon#about to read 4, iclass 23, count 2 2006.201.22:52:32.76#ibcon#read 4, iclass 23, count 2 2006.201.22:52:32.76#ibcon#about to read 5, iclass 23, count 2 2006.201.22:52:32.76#ibcon#read 5, iclass 23, count 2 2006.201.22:52:32.76#ibcon#about to read 6, iclass 23, count 2 2006.201.22:52:32.76#ibcon#read 6, iclass 23, count 2 2006.201.22:52:32.76#ibcon#end of sib2, iclass 23, count 2 2006.201.22:52:32.76#ibcon#*after write, iclass 23, count 2 2006.201.22:52:32.76#ibcon#*before return 0, iclass 23, count 2 2006.201.22:52:32.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:32.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.22:52:32.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.22:52:32.76#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:32.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:32.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:32.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:32.88#ibcon#enter wrdev, iclass 23, count 0 2006.201.22:52:32.88#ibcon#first serial, iclass 23, count 0 2006.201.22:52:32.88#ibcon#enter sib2, iclass 23, count 0 2006.201.22:52:32.88#ibcon#flushed, iclass 23, count 0 2006.201.22:52:32.88#ibcon#about to write, iclass 23, count 0 2006.201.22:52:32.88#ibcon#wrote, iclass 23, count 0 2006.201.22:52:32.88#ibcon#about to read 3, iclass 23, count 0 2006.201.22:52:32.90#ibcon#read 3, iclass 23, count 0 2006.201.22:52:32.90#ibcon#about to read 4, iclass 23, count 0 2006.201.22:52:32.90#ibcon#read 4, iclass 23, count 0 2006.201.22:52:32.90#ibcon#about to read 5, iclass 23, count 0 2006.201.22:52:32.90#ibcon#read 5, iclass 23, count 0 2006.201.22:52:32.90#ibcon#about to read 6, iclass 23, count 0 2006.201.22:52:32.90#ibcon#read 6, iclass 23, count 0 2006.201.22:52:32.90#ibcon#end of sib2, iclass 23, count 0 2006.201.22:52:32.90#ibcon#*mode == 0, iclass 23, count 0 2006.201.22:52:32.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.22:52:32.90#ibcon#[27=USB\r\n] 2006.201.22:52:32.90#ibcon#*before write, iclass 23, count 0 2006.201.22:52:32.90#ibcon#enter sib2, iclass 23, count 0 2006.201.22:52:32.90#ibcon#flushed, iclass 23, count 0 2006.201.22:52:32.90#ibcon#about to write, iclass 23, count 0 2006.201.22:52:32.90#ibcon#wrote, iclass 23, count 0 2006.201.22:52:32.90#ibcon#about to read 3, iclass 23, count 0 2006.201.22:52:32.93#ibcon#read 3, iclass 23, count 0 2006.201.22:52:32.93#ibcon#about to read 4, iclass 23, count 0 2006.201.22:52:32.93#ibcon#read 4, iclass 23, count 0 2006.201.22:52:32.93#ibcon#about to read 5, iclass 23, count 0 2006.201.22:52:32.93#ibcon#read 5, iclass 23, count 0 2006.201.22:52:32.93#ibcon#about to read 6, iclass 23, count 0 2006.201.22:52:32.93#ibcon#read 6, iclass 23, count 0 2006.201.22:52:32.93#ibcon#end of sib2, iclass 23, count 0 2006.201.22:52:32.93#ibcon#*after write, iclass 23, count 0 2006.201.22:52:32.93#ibcon#*before return 0, iclass 23, count 0 2006.201.22:52:32.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:32.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.22:52:32.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.22:52:32.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.22:52:32.93$vck44/vblo=8,744.99 2006.201.22:52:32.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.22:52:32.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.22:52:32.93#ibcon#ireg 17 cls_cnt 0 2006.201.22:52:32.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:32.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:32.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:32.93#ibcon#enter wrdev, iclass 25, count 0 2006.201.22:52:32.93#ibcon#first serial, iclass 25, count 0 2006.201.22:52:32.93#ibcon#enter sib2, iclass 25, count 0 2006.201.22:52:32.93#ibcon#flushed, iclass 25, count 0 2006.201.22:52:32.93#ibcon#about to write, iclass 25, count 0 2006.201.22:52:32.93#ibcon#wrote, iclass 25, count 0 2006.201.22:52:32.93#ibcon#about to read 3, iclass 25, count 0 2006.201.22:52:32.95#ibcon#read 3, iclass 25, count 0 2006.201.22:52:32.95#ibcon#about to read 4, iclass 25, count 0 2006.201.22:52:32.95#ibcon#read 4, iclass 25, count 0 2006.201.22:52:32.95#ibcon#about to read 5, iclass 25, count 0 2006.201.22:52:32.95#ibcon#read 5, iclass 25, count 0 2006.201.22:52:32.95#ibcon#about to read 6, iclass 25, count 0 2006.201.22:52:32.95#ibcon#read 6, iclass 25, count 0 2006.201.22:52:32.95#ibcon#end of sib2, iclass 25, count 0 2006.201.22:52:32.95#ibcon#*mode == 0, iclass 25, count 0 2006.201.22:52:32.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.22:52:32.95#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.22:52:32.95#ibcon#*before write, iclass 25, count 0 2006.201.22:52:32.95#ibcon#enter sib2, iclass 25, count 0 2006.201.22:52:32.95#ibcon#flushed, iclass 25, count 0 2006.201.22:52:32.95#ibcon#about to write, iclass 25, count 0 2006.201.22:52:32.95#ibcon#wrote, iclass 25, count 0 2006.201.22:52:32.95#ibcon#about to read 3, iclass 25, count 0 2006.201.22:52:32.99#ibcon#read 3, iclass 25, count 0 2006.201.22:52:32.99#ibcon#about to read 4, iclass 25, count 0 2006.201.22:52:32.99#ibcon#read 4, iclass 25, count 0 2006.201.22:52:32.99#ibcon#about to read 5, iclass 25, count 0 2006.201.22:52:32.99#ibcon#read 5, iclass 25, count 0 2006.201.22:52:32.99#ibcon#about to read 6, iclass 25, count 0 2006.201.22:52:32.99#ibcon#read 6, iclass 25, count 0 2006.201.22:52:32.99#ibcon#end of sib2, iclass 25, count 0 2006.201.22:52:32.99#ibcon#*after write, iclass 25, count 0 2006.201.22:52:32.99#ibcon#*before return 0, iclass 25, count 0 2006.201.22:52:32.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:32.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.22:52:32.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.22:52:32.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.22:52:32.99$vck44/vb=8,4 2006.201.22:52:32.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.22:52:32.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.22:52:32.99#ibcon#ireg 11 cls_cnt 2 2006.201.22:52:32.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:33.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:33.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:33.05#ibcon#enter wrdev, iclass 27, count 2 2006.201.22:52:33.05#ibcon#first serial, iclass 27, count 2 2006.201.22:52:33.05#ibcon#enter sib2, iclass 27, count 2 2006.201.22:52:33.05#ibcon#flushed, iclass 27, count 2 2006.201.22:52:33.05#ibcon#about to write, iclass 27, count 2 2006.201.22:52:33.05#ibcon#wrote, iclass 27, count 2 2006.201.22:52:33.05#ibcon#about to read 3, iclass 27, count 2 2006.201.22:52:33.07#ibcon#read 3, iclass 27, count 2 2006.201.22:52:33.07#ibcon#about to read 4, iclass 27, count 2 2006.201.22:52:33.07#ibcon#read 4, iclass 27, count 2 2006.201.22:52:33.07#ibcon#about to read 5, iclass 27, count 2 2006.201.22:52:33.07#ibcon#read 5, iclass 27, count 2 2006.201.22:52:33.07#ibcon#about to read 6, iclass 27, count 2 2006.201.22:52:33.07#ibcon#read 6, iclass 27, count 2 2006.201.22:52:33.07#ibcon#end of sib2, iclass 27, count 2 2006.201.22:52:33.07#ibcon#*mode == 0, iclass 27, count 2 2006.201.22:52:33.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.22:52:33.07#ibcon#[27=AT08-04\r\n] 2006.201.22:52:33.07#ibcon#*before write, iclass 27, count 2 2006.201.22:52:33.07#ibcon#enter sib2, iclass 27, count 2 2006.201.22:52:33.07#ibcon#flushed, iclass 27, count 2 2006.201.22:52:33.07#ibcon#about to write, iclass 27, count 2 2006.201.22:52:33.07#ibcon#wrote, iclass 27, count 2 2006.201.22:52:33.07#ibcon#about to read 3, iclass 27, count 2 2006.201.22:52:33.10#ibcon#read 3, iclass 27, count 2 2006.201.22:52:33.10#ibcon#about to read 4, iclass 27, count 2 2006.201.22:52:33.10#ibcon#read 4, iclass 27, count 2 2006.201.22:52:33.10#ibcon#about to read 5, iclass 27, count 2 2006.201.22:52:33.10#ibcon#read 5, iclass 27, count 2 2006.201.22:52:33.10#ibcon#about to read 6, iclass 27, count 2 2006.201.22:52:33.10#ibcon#read 6, iclass 27, count 2 2006.201.22:52:33.10#ibcon#end of sib2, iclass 27, count 2 2006.201.22:52:33.10#ibcon#*after write, iclass 27, count 2 2006.201.22:52:33.10#ibcon#*before return 0, iclass 27, count 2 2006.201.22:52:33.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:33.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.22:52:33.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.22:52:33.10#ibcon#ireg 7 cls_cnt 0 2006.201.22:52:33.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:33.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:33.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:33.22#ibcon#enter wrdev, iclass 27, count 0 2006.201.22:52:33.22#ibcon#first serial, iclass 27, count 0 2006.201.22:52:33.22#ibcon#enter sib2, iclass 27, count 0 2006.201.22:52:33.22#ibcon#flushed, iclass 27, count 0 2006.201.22:52:33.22#ibcon#about to write, iclass 27, count 0 2006.201.22:52:33.22#ibcon#wrote, iclass 27, count 0 2006.201.22:52:33.22#ibcon#about to read 3, iclass 27, count 0 2006.201.22:52:33.24#ibcon#read 3, iclass 27, count 0 2006.201.22:52:33.24#ibcon#about to read 4, iclass 27, count 0 2006.201.22:52:33.24#ibcon#read 4, iclass 27, count 0 2006.201.22:52:33.24#ibcon#about to read 5, iclass 27, count 0 2006.201.22:52:33.24#ibcon#read 5, iclass 27, count 0 2006.201.22:52:33.24#ibcon#about to read 6, iclass 27, count 0 2006.201.22:52:33.24#ibcon#read 6, iclass 27, count 0 2006.201.22:52:33.24#ibcon#end of sib2, iclass 27, count 0 2006.201.22:52:33.24#ibcon#*mode == 0, iclass 27, count 0 2006.201.22:52:33.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.22:52:33.24#ibcon#[27=USB\r\n] 2006.201.22:52:33.24#ibcon#*before write, iclass 27, count 0 2006.201.22:52:33.24#ibcon#enter sib2, iclass 27, count 0 2006.201.22:52:33.24#ibcon#flushed, iclass 27, count 0 2006.201.22:52:33.24#ibcon#about to write, iclass 27, count 0 2006.201.22:52:33.24#ibcon#wrote, iclass 27, count 0 2006.201.22:52:33.24#ibcon#about to read 3, iclass 27, count 0 2006.201.22:52:33.27#ibcon#read 3, iclass 27, count 0 2006.201.22:52:33.27#ibcon#about to read 4, iclass 27, count 0 2006.201.22:52:33.27#ibcon#read 4, iclass 27, count 0 2006.201.22:52:33.27#ibcon#about to read 5, iclass 27, count 0 2006.201.22:52:33.27#ibcon#read 5, iclass 27, count 0 2006.201.22:52:33.27#ibcon#about to read 6, iclass 27, count 0 2006.201.22:52:33.27#ibcon#read 6, iclass 27, count 0 2006.201.22:52:33.27#ibcon#end of sib2, iclass 27, count 0 2006.201.22:52:33.27#ibcon#*after write, iclass 27, count 0 2006.201.22:52:33.27#ibcon#*before return 0, iclass 27, count 0 2006.201.22:52:33.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:33.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.22:52:33.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.22:52:33.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.22:52:33.27$vck44/vabw=wide 2006.201.22:52:33.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.22:52:33.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.22:52:33.27#ibcon#ireg 8 cls_cnt 0 2006.201.22:52:33.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:33.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:33.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:33.27#ibcon#enter wrdev, iclass 29, count 0 2006.201.22:52:33.27#ibcon#first serial, iclass 29, count 0 2006.201.22:52:33.27#ibcon#enter sib2, iclass 29, count 0 2006.201.22:52:33.27#ibcon#flushed, iclass 29, count 0 2006.201.22:52:33.27#ibcon#about to write, iclass 29, count 0 2006.201.22:52:33.27#ibcon#wrote, iclass 29, count 0 2006.201.22:52:33.27#ibcon#about to read 3, iclass 29, count 0 2006.201.22:52:33.29#ibcon#read 3, iclass 29, count 0 2006.201.22:52:33.29#ibcon#about to read 4, iclass 29, count 0 2006.201.22:52:33.29#ibcon#read 4, iclass 29, count 0 2006.201.22:52:33.29#ibcon#about to read 5, iclass 29, count 0 2006.201.22:52:33.29#ibcon#read 5, iclass 29, count 0 2006.201.22:52:33.29#ibcon#about to read 6, iclass 29, count 0 2006.201.22:52:33.29#ibcon#read 6, iclass 29, count 0 2006.201.22:52:33.29#ibcon#end of sib2, iclass 29, count 0 2006.201.22:52:33.29#ibcon#*mode == 0, iclass 29, count 0 2006.201.22:52:33.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.22:52:33.29#ibcon#[25=BW32\r\n] 2006.201.22:52:33.29#ibcon#*before write, iclass 29, count 0 2006.201.22:52:33.29#ibcon#enter sib2, iclass 29, count 0 2006.201.22:52:33.29#ibcon#flushed, iclass 29, count 0 2006.201.22:52:33.29#ibcon#about to write, iclass 29, count 0 2006.201.22:52:33.29#ibcon#wrote, iclass 29, count 0 2006.201.22:52:33.29#ibcon#about to read 3, iclass 29, count 0 2006.201.22:52:33.32#ibcon#read 3, iclass 29, count 0 2006.201.22:52:33.32#ibcon#about to read 4, iclass 29, count 0 2006.201.22:52:33.32#ibcon#read 4, iclass 29, count 0 2006.201.22:52:33.32#ibcon#about to read 5, iclass 29, count 0 2006.201.22:52:33.32#ibcon#read 5, iclass 29, count 0 2006.201.22:52:33.32#ibcon#about to read 6, iclass 29, count 0 2006.201.22:52:33.32#ibcon#read 6, iclass 29, count 0 2006.201.22:52:33.32#ibcon#end of sib2, iclass 29, count 0 2006.201.22:52:33.32#ibcon#*after write, iclass 29, count 0 2006.201.22:52:33.32#ibcon#*before return 0, iclass 29, count 0 2006.201.22:52:33.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:33.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.22:52:33.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.22:52:33.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.22:52:33.32$vck44/vbbw=wide 2006.201.22:52:33.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.22:52:33.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.22:52:33.32#ibcon#ireg 8 cls_cnt 0 2006.201.22:52:33.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:52:33.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:52:33.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:52:33.39#ibcon#enter wrdev, iclass 31, count 0 2006.201.22:52:33.39#ibcon#first serial, iclass 31, count 0 2006.201.22:52:33.39#ibcon#enter sib2, iclass 31, count 0 2006.201.22:52:33.39#ibcon#flushed, iclass 31, count 0 2006.201.22:52:33.39#ibcon#about to write, iclass 31, count 0 2006.201.22:52:33.39#ibcon#wrote, iclass 31, count 0 2006.201.22:52:33.39#ibcon#about to read 3, iclass 31, count 0 2006.201.22:52:33.41#ibcon#read 3, iclass 31, count 0 2006.201.22:52:33.41#ibcon#about to read 4, iclass 31, count 0 2006.201.22:52:33.41#ibcon#read 4, iclass 31, count 0 2006.201.22:52:33.41#ibcon#about to read 5, iclass 31, count 0 2006.201.22:52:33.41#ibcon#read 5, iclass 31, count 0 2006.201.22:52:33.41#ibcon#about to read 6, iclass 31, count 0 2006.201.22:52:33.41#ibcon#read 6, iclass 31, count 0 2006.201.22:52:33.41#ibcon#end of sib2, iclass 31, count 0 2006.201.22:52:33.41#ibcon#*mode == 0, iclass 31, count 0 2006.201.22:52:33.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.22:52:33.41#ibcon#[27=BW32\r\n] 2006.201.22:52:33.41#ibcon#*before write, iclass 31, count 0 2006.201.22:52:33.41#ibcon#enter sib2, iclass 31, count 0 2006.201.22:52:33.41#ibcon#flushed, iclass 31, count 0 2006.201.22:52:33.41#ibcon#about to write, iclass 31, count 0 2006.201.22:52:33.41#ibcon#wrote, iclass 31, count 0 2006.201.22:52:33.41#ibcon#about to read 3, iclass 31, count 0 2006.201.22:52:33.44#ibcon#read 3, iclass 31, count 0 2006.201.22:52:33.44#ibcon#about to read 4, iclass 31, count 0 2006.201.22:52:33.44#ibcon#read 4, iclass 31, count 0 2006.201.22:52:33.44#ibcon#about to read 5, iclass 31, count 0 2006.201.22:52:33.44#ibcon#read 5, iclass 31, count 0 2006.201.22:52:33.44#ibcon#about to read 6, iclass 31, count 0 2006.201.22:52:33.44#ibcon#read 6, iclass 31, count 0 2006.201.22:52:33.44#ibcon#end of sib2, iclass 31, count 0 2006.201.22:52:33.44#ibcon#*after write, iclass 31, count 0 2006.201.22:52:33.44#ibcon#*before return 0, iclass 31, count 0 2006.201.22:52:33.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:52:33.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.22:52:33.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.22:52:33.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.22:52:33.44$setupk4/ifdk4 2006.201.22:52:33.44$ifdk4/lo= 2006.201.22:52:33.44$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.22:52:33.44$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.22:52:33.44$ifdk4/patch= 2006.201.22:52:33.44$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.22:52:33.44$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.22:52:33.44$setupk4/!*+20s 2006.201.22:52:41.19#abcon#<5=/04 1.8 3.3 20.041001001.4\r\n> 2006.201.22:52:41.22#abcon#{5=INTERFACE CLEAR} 2006.201.22:52:41.29#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:52:47.93$setupk4/"tpicd 2006.201.22:52:47.93$setupk4/echo=off 2006.201.22:52:47.93$setupk4/xlog=off 2006.201.22:52:47.93:!2006.201.22:54:45 2006.201.22:52:52.14#trakl#Source acquired 2006.201.22:52:54.14#flagr#flagr/antenna,acquired 2006.201.22:54:45.00:preob 2006.201.22:54:46.14/onsource/TRACKING 2006.201.22:54:46.14:!2006.201.22:54:55 2006.201.22:54:55.00:"tape 2006.201.22:54:55.00:"st=record 2006.201.22:54:55.00:data_valid=on 2006.201.22:54:55.00:midob 2006.201.22:54:55.14/onsource/TRACKING 2006.201.22:54:55.14/wx/20.05,1001.5,100 2006.201.22:54:55.31/cable/+6.4836E-03 2006.201.22:54:56.40/va/01,08,usb,yes,60,64 2006.201.22:54:56.40/va/02,07,usb,yes,64,65 2006.201.22:54:56.40/va/03,08,usb,yes,59,61 2006.201.22:54:56.40/va/04,07,usb,yes,66,70 2006.201.22:54:56.40/va/05,04,usb,yes,59,61 2006.201.22:54:56.40/va/06,05,usb,yes,60,60 2006.201.22:54:56.40/va/07,05,usb,yes,59,60 2006.201.22:54:56.40/va/08,04,usb,yes,58,68 2006.201.22:54:56.63/valo/01,524.99,yes,locked 2006.201.22:54:56.63/valo/02,534.99,yes,locked 2006.201.22:54:56.63/valo/03,564.99,yes,locked 2006.201.22:54:56.63/valo/04,624.99,yes,locked 2006.201.22:54:56.63/valo/05,734.99,yes,locked 2006.201.22:54:56.63/valo/06,814.99,yes,locked 2006.201.22:54:56.63/valo/07,864.99,yes,locked 2006.201.22:54:56.63/valo/08,884.99,yes,locked 2006.201.22:54:57.72/vb/01,04,usb,yes,33,31 2006.201.22:54:57.72/vb/02,05,usb,yes,31,31 2006.201.22:54:57.72/vb/03,04,usb,yes,32,35 2006.201.22:54:57.72/vb/04,05,usb,yes,32,31 2006.201.22:54:57.72/vb/05,04,usb,yes,29,32 2006.201.22:54:57.72/vb/06,04,usb,yes,34,30 2006.201.22:54:57.72/vb/07,04,usb,yes,34,34 2006.201.22:54:57.72/vb/08,04,usb,yes,31,35 2006.201.22:54:57.96/vblo/01,629.99,yes,locked 2006.201.22:54:57.96/vblo/02,634.99,yes,locked 2006.201.22:54:57.96/vblo/03,649.99,yes,locked 2006.201.22:54:57.96/vblo/04,679.99,yes,locked 2006.201.22:54:57.96/vblo/05,709.99,yes,locked 2006.201.22:54:57.96/vblo/06,719.99,yes,locked 2006.201.22:54:57.96/vblo/07,734.99,yes,locked 2006.201.22:54:57.96/vblo/08,744.99,yes,locked 2006.201.22:54:58.11/vabw/8 2006.201.22:54:58.26/vbbw/8 2006.201.22:54:58.35/xfe/off,on,14.0 2006.201.22:54:58.72/ifatt/23,28,28,28 2006.201.22:54:59.07/fmout-gps/S +4.51E-07 2006.201.22:54:59.11:!2006.201.22:55:35 2006.201.22:55:35.00:data_valid=off 2006.201.22:55:35.00:"et 2006.201.22:55:35.00:!+3s 2006.201.22:55:38.02:"tape 2006.201.22:55:38.02:postob 2006.201.22:55:38.21/cable/+6.4835E-03 2006.201.22:55:38.21/wx/20.06,1001.5,100 2006.201.22:55:38.29/fmout-gps/S +4.52E-07 2006.201.22:55:38.29:scan_name=201-2259,jd0607,230 2006.201.22:55:38.29:source=cta26,033930.94,-014635.8,2000.0,cw 2006.201.22:55:40.14#flagr#flagr/antenna,new-source 2006.201.22:55:40.14:checkk5 2006.201.22:55:40.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.22:55:40.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.22:55:41.29/chk_autoobs//k5ts3/ autoobs is running! 2006.201.22:55:41.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.22:55:42.02/chk_obsdata//k5ts1/T2012254??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.22:55:42.39/chk_obsdata//k5ts2/T2012254??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.22:55:42.75/chk_obsdata//k5ts3/T2012254??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.22:55:43.12/chk_obsdata//k5ts4/T2012254??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.201.22:55:43.80/k5log//k5ts1_log_newline 2006.201.22:55:44.49/k5log//k5ts2_log_newline 2006.201.22:55:45.17/k5log//k5ts3_log_newline 2006.201.22:55:45.85/k5log//k5ts4_log_newline 2006.201.22:55:45.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.22:55:45.88:setupk4=1 2006.201.22:55:45.88$setupk4/echo=on 2006.201.22:55:45.88$setupk4/pcalon 2006.201.22:55:45.88$pcalon/"no phase cal control is implemented here 2006.201.22:55:45.88$setupk4/"tpicd=stop 2006.201.22:55:45.88$setupk4/"rec=synch_on 2006.201.22:55:45.88$setupk4/"rec_mode=128 2006.201.22:55:45.88$setupk4/!* 2006.201.22:55:45.88$setupk4/recpk4 2006.201.22:55:45.88$recpk4/recpatch= 2006.201.22:55:45.88$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.22:55:45.88$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.22:55:45.88$setupk4/vck44 2006.201.22:55:45.88$vck44/valo=1,524.99 2006.201.22:55:45.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.22:55:45.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.22:55:45.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:45.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:45.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:45.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:45.88#ibcon#enter wrdev, iclass 40, count 0 2006.201.22:55:45.88#ibcon#first serial, iclass 40, count 0 2006.201.22:55:45.88#ibcon#enter sib2, iclass 40, count 0 2006.201.22:55:45.88#ibcon#flushed, iclass 40, count 0 2006.201.22:55:45.88#ibcon#about to write, iclass 40, count 0 2006.201.22:55:45.88#ibcon#wrote, iclass 40, count 0 2006.201.22:55:45.88#ibcon#about to read 3, iclass 40, count 0 2006.201.22:55:45.90#ibcon#read 3, iclass 40, count 0 2006.201.22:55:45.90#ibcon#about to read 4, iclass 40, count 0 2006.201.22:55:45.90#ibcon#read 4, iclass 40, count 0 2006.201.22:55:45.90#ibcon#about to read 5, iclass 40, count 0 2006.201.22:55:45.90#ibcon#read 5, iclass 40, count 0 2006.201.22:55:45.90#ibcon#about to read 6, iclass 40, count 0 2006.201.22:55:45.90#ibcon#read 6, iclass 40, count 0 2006.201.22:55:45.90#ibcon#end of sib2, iclass 40, count 0 2006.201.22:55:45.90#ibcon#*mode == 0, iclass 40, count 0 2006.201.22:55:45.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.22:55:45.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.22:55:45.90#ibcon#*before write, iclass 40, count 0 2006.201.22:55:45.90#ibcon#enter sib2, iclass 40, count 0 2006.201.22:55:45.90#ibcon#flushed, iclass 40, count 0 2006.201.22:55:45.90#ibcon#about to write, iclass 40, count 0 2006.201.22:55:45.90#ibcon#wrote, iclass 40, count 0 2006.201.22:55:45.90#ibcon#about to read 3, iclass 40, count 0 2006.201.22:55:45.95#ibcon#read 3, iclass 40, count 0 2006.201.22:55:45.95#ibcon#about to read 4, iclass 40, count 0 2006.201.22:55:45.95#ibcon#read 4, iclass 40, count 0 2006.201.22:55:45.95#ibcon#about to read 5, iclass 40, count 0 2006.201.22:55:45.95#ibcon#read 5, iclass 40, count 0 2006.201.22:55:45.95#ibcon#about to read 6, iclass 40, count 0 2006.201.22:55:45.95#ibcon#read 6, iclass 40, count 0 2006.201.22:55:45.95#ibcon#end of sib2, iclass 40, count 0 2006.201.22:55:45.95#ibcon#*after write, iclass 40, count 0 2006.201.22:55:45.95#ibcon#*before return 0, iclass 40, count 0 2006.201.22:55:45.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:45.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:45.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.22:55:45.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.22:55:45.95$vck44/va=1,8 2006.201.22:55:45.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.22:55:45.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.22:55:45.95#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:45.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:45.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:45.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:45.95#ibcon#enter wrdev, iclass 4, count 2 2006.201.22:55:45.95#ibcon#first serial, iclass 4, count 2 2006.201.22:55:45.95#ibcon#enter sib2, iclass 4, count 2 2006.201.22:55:45.95#ibcon#flushed, iclass 4, count 2 2006.201.22:55:45.95#ibcon#about to write, iclass 4, count 2 2006.201.22:55:45.95#ibcon#wrote, iclass 4, count 2 2006.201.22:55:45.95#ibcon#about to read 3, iclass 4, count 2 2006.201.22:55:45.97#ibcon#read 3, iclass 4, count 2 2006.201.22:55:45.97#ibcon#about to read 4, iclass 4, count 2 2006.201.22:55:45.97#ibcon#read 4, iclass 4, count 2 2006.201.22:55:45.97#ibcon#about to read 5, iclass 4, count 2 2006.201.22:55:45.97#ibcon#read 5, iclass 4, count 2 2006.201.22:55:45.97#ibcon#about to read 6, iclass 4, count 2 2006.201.22:55:45.97#ibcon#read 6, iclass 4, count 2 2006.201.22:55:45.97#ibcon#end of sib2, iclass 4, count 2 2006.201.22:55:45.97#ibcon#*mode == 0, iclass 4, count 2 2006.201.22:55:45.97#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.22:55:45.97#ibcon#[25=AT01-08\r\n] 2006.201.22:55:45.97#ibcon#*before write, iclass 4, count 2 2006.201.22:55:45.97#ibcon#enter sib2, iclass 4, count 2 2006.201.22:55:45.97#ibcon#flushed, iclass 4, count 2 2006.201.22:55:45.97#ibcon#about to write, iclass 4, count 2 2006.201.22:55:45.97#ibcon#wrote, iclass 4, count 2 2006.201.22:55:45.97#ibcon#about to read 3, iclass 4, count 2 2006.201.22:55:46.00#ibcon#read 3, iclass 4, count 2 2006.201.22:55:46.00#ibcon#about to read 4, iclass 4, count 2 2006.201.22:55:46.00#ibcon#read 4, iclass 4, count 2 2006.201.22:55:46.00#ibcon#about to read 5, iclass 4, count 2 2006.201.22:55:46.00#ibcon#read 5, iclass 4, count 2 2006.201.22:55:46.00#ibcon#about to read 6, iclass 4, count 2 2006.201.22:55:46.00#ibcon#read 6, iclass 4, count 2 2006.201.22:55:46.00#ibcon#end of sib2, iclass 4, count 2 2006.201.22:55:46.00#ibcon#*after write, iclass 4, count 2 2006.201.22:55:46.00#ibcon#*before return 0, iclass 4, count 2 2006.201.22:55:46.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:46.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:46.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.22:55:46.00#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:46.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:46.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:46.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:46.12#ibcon#enter wrdev, iclass 4, count 0 2006.201.22:55:46.12#ibcon#first serial, iclass 4, count 0 2006.201.22:55:46.12#ibcon#enter sib2, iclass 4, count 0 2006.201.22:55:46.12#ibcon#flushed, iclass 4, count 0 2006.201.22:55:46.12#ibcon#about to write, iclass 4, count 0 2006.201.22:55:46.12#ibcon#wrote, iclass 4, count 0 2006.201.22:55:46.12#ibcon#about to read 3, iclass 4, count 0 2006.201.22:55:46.14#ibcon#read 3, iclass 4, count 0 2006.201.22:55:46.14#ibcon#about to read 4, iclass 4, count 0 2006.201.22:55:46.14#ibcon#read 4, iclass 4, count 0 2006.201.22:55:46.14#ibcon#about to read 5, iclass 4, count 0 2006.201.22:55:46.14#ibcon#read 5, iclass 4, count 0 2006.201.22:55:46.14#ibcon#about to read 6, iclass 4, count 0 2006.201.22:55:46.14#ibcon#read 6, iclass 4, count 0 2006.201.22:55:46.14#ibcon#end of sib2, iclass 4, count 0 2006.201.22:55:46.14#ibcon#*mode == 0, iclass 4, count 0 2006.201.22:55:46.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.22:55:46.14#ibcon#[25=USB\r\n] 2006.201.22:55:46.14#ibcon#*before write, iclass 4, count 0 2006.201.22:55:46.14#ibcon#enter sib2, iclass 4, count 0 2006.201.22:55:46.14#ibcon#flushed, iclass 4, count 0 2006.201.22:55:46.14#ibcon#about to write, iclass 4, count 0 2006.201.22:55:46.14#ibcon#wrote, iclass 4, count 0 2006.201.22:55:46.14#ibcon#about to read 3, iclass 4, count 0 2006.201.22:55:46.17#ibcon#read 3, iclass 4, count 0 2006.201.22:55:46.17#ibcon#about to read 4, iclass 4, count 0 2006.201.22:55:46.17#ibcon#read 4, iclass 4, count 0 2006.201.22:55:46.17#ibcon#about to read 5, iclass 4, count 0 2006.201.22:55:46.17#ibcon#read 5, iclass 4, count 0 2006.201.22:55:46.17#ibcon#about to read 6, iclass 4, count 0 2006.201.22:55:46.17#ibcon#read 6, iclass 4, count 0 2006.201.22:55:46.17#ibcon#end of sib2, iclass 4, count 0 2006.201.22:55:46.17#ibcon#*after write, iclass 4, count 0 2006.201.22:55:46.17#ibcon#*before return 0, iclass 4, count 0 2006.201.22:55:46.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:46.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:46.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.22:55:46.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.22:55:46.17$vck44/valo=2,534.99 2006.201.22:55:46.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.22:55:46.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.22:55:46.17#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:46.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:46.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:46.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:46.17#ibcon#enter wrdev, iclass 6, count 0 2006.201.22:55:46.17#ibcon#first serial, iclass 6, count 0 2006.201.22:55:46.17#ibcon#enter sib2, iclass 6, count 0 2006.201.22:55:46.17#ibcon#flushed, iclass 6, count 0 2006.201.22:55:46.17#ibcon#about to write, iclass 6, count 0 2006.201.22:55:46.17#ibcon#wrote, iclass 6, count 0 2006.201.22:55:46.17#ibcon#about to read 3, iclass 6, count 0 2006.201.22:55:46.19#ibcon#read 3, iclass 6, count 0 2006.201.22:55:46.19#ibcon#about to read 4, iclass 6, count 0 2006.201.22:55:46.19#ibcon#read 4, iclass 6, count 0 2006.201.22:55:46.19#ibcon#about to read 5, iclass 6, count 0 2006.201.22:55:46.19#ibcon#read 5, iclass 6, count 0 2006.201.22:55:46.19#ibcon#about to read 6, iclass 6, count 0 2006.201.22:55:46.19#ibcon#read 6, iclass 6, count 0 2006.201.22:55:46.19#ibcon#end of sib2, iclass 6, count 0 2006.201.22:55:46.19#ibcon#*mode == 0, iclass 6, count 0 2006.201.22:55:46.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.22:55:46.19#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.22:55:46.19#ibcon#*before write, iclass 6, count 0 2006.201.22:55:46.19#ibcon#enter sib2, iclass 6, count 0 2006.201.22:55:46.19#ibcon#flushed, iclass 6, count 0 2006.201.22:55:46.19#ibcon#about to write, iclass 6, count 0 2006.201.22:55:46.19#ibcon#wrote, iclass 6, count 0 2006.201.22:55:46.19#ibcon#about to read 3, iclass 6, count 0 2006.201.22:55:46.24#ibcon#read 3, iclass 6, count 0 2006.201.22:55:46.24#ibcon#about to read 4, iclass 6, count 0 2006.201.22:55:46.24#ibcon#read 4, iclass 6, count 0 2006.201.22:55:46.24#ibcon#about to read 5, iclass 6, count 0 2006.201.22:55:46.24#ibcon#read 5, iclass 6, count 0 2006.201.22:55:46.24#ibcon#about to read 6, iclass 6, count 0 2006.201.22:55:46.24#ibcon#read 6, iclass 6, count 0 2006.201.22:55:46.24#ibcon#end of sib2, iclass 6, count 0 2006.201.22:55:46.24#ibcon#*after write, iclass 6, count 0 2006.201.22:55:46.24#ibcon#*before return 0, iclass 6, count 0 2006.201.22:55:46.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:46.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:46.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.22:55:46.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.22:55:46.24$vck44/va=2,7 2006.201.22:55:46.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.22:55:46.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.22:55:46.24#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:46.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:46.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:46.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:46.29#ibcon#enter wrdev, iclass 10, count 2 2006.201.22:55:46.29#ibcon#first serial, iclass 10, count 2 2006.201.22:55:46.29#ibcon#enter sib2, iclass 10, count 2 2006.201.22:55:46.29#ibcon#flushed, iclass 10, count 2 2006.201.22:55:46.29#ibcon#about to write, iclass 10, count 2 2006.201.22:55:46.29#ibcon#wrote, iclass 10, count 2 2006.201.22:55:46.29#ibcon#about to read 3, iclass 10, count 2 2006.201.22:55:46.31#ibcon#read 3, iclass 10, count 2 2006.201.22:55:46.31#ibcon#about to read 4, iclass 10, count 2 2006.201.22:55:46.31#ibcon#read 4, iclass 10, count 2 2006.201.22:55:46.31#ibcon#about to read 5, iclass 10, count 2 2006.201.22:55:46.31#ibcon#read 5, iclass 10, count 2 2006.201.22:55:46.31#ibcon#about to read 6, iclass 10, count 2 2006.201.22:55:46.31#ibcon#read 6, iclass 10, count 2 2006.201.22:55:46.31#ibcon#end of sib2, iclass 10, count 2 2006.201.22:55:46.31#ibcon#*mode == 0, iclass 10, count 2 2006.201.22:55:46.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.22:55:46.31#ibcon#[25=AT02-07\r\n] 2006.201.22:55:46.31#ibcon#*before write, iclass 10, count 2 2006.201.22:55:46.31#ibcon#enter sib2, iclass 10, count 2 2006.201.22:55:46.31#ibcon#flushed, iclass 10, count 2 2006.201.22:55:46.31#ibcon#about to write, iclass 10, count 2 2006.201.22:55:46.31#ibcon#wrote, iclass 10, count 2 2006.201.22:55:46.31#ibcon#about to read 3, iclass 10, count 2 2006.201.22:55:46.34#ibcon#read 3, iclass 10, count 2 2006.201.22:55:46.34#ibcon#about to read 4, iclass 10, count 2 2006.201.22:55:46.34#ibcon#read 4, iclass 10, count 2 2006.201.22:55:46.34#ibcon#about to read 5, iclass 10, count 2 2006.201.22:55:46.34#ibcon#read 5, iclass 10, count 2 2006.201.22:55:46.34#ibcon#about to read 6, iclass 10, count 2 2006.201.22:55:46.34#ibcon#read 6, iclass 10, count 2 2006.201.22:55:46.34#ibcon#end of sib2, iclass 10, count 2 2006.201.22:55:46.34#ibcon#*after write, iclass 10, count 2 2006.201.22:55:46.34#ibcon#*before return 0, iclass 10, count 2 2006.201.22:55:46.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:46.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:46.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.22:55:46.34#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:46.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:46.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:46.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:46.46#ibcon#enter wrdev, iclass 10, count 0 2006.201.22:55:46.46#ibcon#first serial, iclass 10, count 0 2006.201.22:55:46.46#ibcon#enter sib2, iclass 10, count 0 2006.201.22:55:46.46#ibcon#flushed, iclass 10, count 0 2006.201.22:55:46.46#ibcon#about to write, iclass 10, count 0 2006.201.22:55:46.46#ibcon#wrote, iclass 10, count 0 2006.201.22:55:46.46#ibcon#about to read 3, iclass 10, count 0 2006.201.22:55:46.48#ibcon#read 3, iclass 10, count 0 2006.201.22:55:46.48#ibcon#about to read 4, iclass 10, count 0 2006.201.22:55:46.48#ibcon#read 4, iclass 10, count 0 2006.201.22:55:46.48#ibcon#about to read 5, iclass 10, count 0 2006.201.22:55:46.48#ibcon#read 5, iclass 10, count 0 2006.201.22:55:46.48#ibcon#about to read 6, iclass 10, count 0 2006.201.22:55:46.48#ibcon#read 6, iclass 10, count 0 2006.201.22:55:46.48#ibcon#end of sib2, iclass 10, count 0 2006.201.22:55:46.48#ibcon#*mode == 0, iclass 10, count 0 2006.201.22:55:46.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.22:55:46.48#ibcon#[25=USB\r\n] 2006.201.22:55:46.48#ibcon#*before write, iclass 10, count 0 2006.201.22:55:46.48#ibcon#enter sib2, iclass 10, count 0 2006.201.22:55:46.48#ibcon#flushed, iclass 10, count 0 2006.201.22:55:46.48#ibcon#about to write, iclass 10, count 0 2006.201.22:55:46.48#ibcon#wrote, iclass 10, count 0 2006.201.22:55:46.48#ibcon#about to read 3, iclass 10, count 0 2006.201.22:55:46.51#ibcon#read 3, iclass 10, count 0 2006.201.22:55:46.51#ibcon#about to read 4, iclass 10, count 0 2006.201.22:55:46.51#ibcon#read 4, iclass 10, count 0 2006.201.22:55:46.51#ibcon#about to read 5, iclass 10, count 0 2006.201.22:55:46.51#ibcon#read 5, iclass 10, count 0 2006.201.22:55:46.51#ibcon#about to read 6, iclass 10, count 0 2006.201.22:55:46.51#ibcon#read 6, iclass 10, count 0 2006.201.22:55:46.51#ibcon#end of sib2, iclass 10, count 0 2006.201.22:55:46.51#ibcon#*after write, iclass 10, count 0 2006.201.22:55:46.51#ibcon#*before return 0, iclass 10, count 0 2006.201.22:55:46.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:46.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:46.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.22:55:46.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.22:55:46.51$vck44/valo=3,564.99 2006.201.22:55:46.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.22:55:46.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.22:55:46.51#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:46.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:46.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:46.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:46.51#ibcon#enter wrdev, iclass 12, count 0 2006.201.22:55:46.51#ibcon#first serial, iclass 12, count 0 2006.201.22:55:46.51#ibcon#enter sib2, iclass 12, count 0 2006.201.22:55:46.51#ibcon#flushed, iclass 12, count 0 2006.201.22:55:46.51#ibcon#about to write, iclass 12, count 0 2006.201.22:55:46.51#ibcon#wrote, iclass 12, count 0 2006.201.22:55:46.51#ibcon#about to read 3, iclass 12, count 0 2006.201.22:55:46.53#ibcon#read 3, iclass 12, count 0 2006.201.22:55:46.53#ibcon#about to read 4, iclass 12, count 0 2006.201.22:55:46.53#ibcon#read 4, iclass 12, count 0 2006.201.22:55:46.53#ibcon#about to read 5, iclass 12, count 0 2006.201.22:55:46.53#ibcon#read 5, iclass 12, count 0 2006.201.22:55:46.53#ibcon#about to read 6, iclass 12, count 0 2006.201.22:55:46.53#ibcon#read 6, iclass 12, count 0 2006.201.22:55:46.53#ibcon#end of sib2, iclass 12, count 0 2006.201.22:55:46.53#ibcon#*mode == 0, iclass 12, count 0 2006.201.22:55:46.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.22:55:46.53#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.22:55:46.53#ibcon#*before write, iclass 12, count 0 2006.201.22:55:46.53#ibcon#enter sib2, iclass 12, count 0 2006.201.22:55:46.53#ibcon#flushed, iclass 12, count 0 2006.201.22:55:46.53#ibcon#about to write, iclass 12, count 0 2006.201.22:55:46.53#ibcon#wrote, iclass 12, count 0 2006.201.22:55:46.53#ibcon#about to read 3, iclass 12, count 0 2006.201.22:55:46.58#ibcon#read 3, iclass 12, count 0 2006.201.22:55:46.58#ibcon#about to read 4, iclass 12, count 0 2006.201.22:55:46.58#ibcon#read 4, iclass 12, count 0 2006.201.22:55:46.58#ibcon#about to read 5, iclass 12, count 0 2006.201.22:55:46.58#ibcon#read 5, iclass 12, count 0 2006.201.22:55:46.58#ibcon#about to read 6, iclass 12, count 0 2006.201.22:55:46.58#ibcon#read 6, iclass 12, count 0 2006.201.22:55:46.58#ibcon#end of sib2, iclass 12, count 0 2006.201.22:55:46.58#ibcon#*after write, iclass 12, count 0 2006.201.22:55:46.58#ibcon#*before return 0, iclass 12, count 0 2006.201.22:55:46.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:46.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:46.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.22:55:46.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.22:55:46.58$vck44/va=3,8 2006.201.22:55:46.58#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.22:55:46.58#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.22:55:46.58#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:46.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:46.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:46.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:46.63#ibcon#enter wrdev, iclass 14, count 2 2006.201.22:55:46.63#ibcon#first serial, iclass 14, count 2 2006.201.22:55:46.63#ibcon#enter sib2, iclass 14, count 2 2006.201.22:55:46.63#ibcon#flushed, iclass 14, count 2 2006.201.22:55:46.63#ibcon#about to write, iclass 14, count 2 2006.201.22:55:46.63#ibcon#wrote, iclass 14, count 2 2006.201.22:55:46.63#ibcon#about to read 3, iclass 14, count 2 2006.201.22:55:46.65#ibcon#read 3, iclass 14, count 2 2006.201.22:55:46.65#ibcon#about to read 4, iclass 14, count 2 2006.201.22:55:46.65#ibcon#read 4, iclass 14, count 2 2006.201.22:55:46.65#ibcon#about to read 5, iclass 14, count 2 2006.201.22:55:46.65#ibcon#read 5, iclass 14, count 2 2006.201.22:55:46.65#ibcon#about to read 6, iclass 14, count 2 2006.201.22:55:46.65#ibcon#read 6, iclass 14, count 2 2006.201.22:55:46.65#ibcon#end of sib2, iclass 14, count 2 2006.201.22:55:46.65#ibcon#*mode == 0, iclass 14, count 2 2006.201.22:55:46.65#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.22:55:46.65#ibcon#[25=AT03-08\r\n] 2006.201.22:55:46.65#ibcon#*before write, iclass 14, count 2 2006.201.22:55:46.65#ibcon#enter sib2, iclass 14, count 2 2006.201.22:55:46.65#ibcon#flushed, iclass 14, count 2 2006.201.22:55:46.65#ibcon#about to write, iclass 14, count 2 2006.201.22:55:46.65#ibcon#wrote, iclass 14, count 2 2006.201.22:55:46.65#ibcon#about to read 3, iclass 14, count 2 2006.201.22:55:46.68#ibcon#read 3, iclass 14, count 2 2006.201.22:55:46.68#ibcon#about to read 4, iclass 14, count 2 2006.201.22:55:46.68#ibcon#read 4, iclass 14, count 2 2006.201.22:55:46.68#ibcon#about to read 5, iclass 14, count 2 2006.201.22:55:46.68#ibcon#read 5, iclass 14, count 2 2006.201.22:55:46.68#ibcon#about to read 6, iclass 14, count 2 2006.201.22:55:46.68#ibcon#read 6, iclass 14, count 2 2006.201.22:55:46.68#ibcon#end of sib2, iclass 14, count 2 2006.201.22:55:46.68#ibcon#*after write, iclass 14, count 2 2006.201.22:55:46.68#ibcon#*before return 0, iclass 14, count 2 2006.201.22:55:46.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:46.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:46.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.22:55:46.68#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:46.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:46.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:46.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:46.80#ibcon#enter wrdev, iclass 14, count 0 2006.201.22:55:46.80#ibcon#first serial, iclass 14, count 0 2006.201.22:55:46.80#ibcon#enter sib2, iclass 14, count 0 2006.201.22:55:46.80#ibcon#flushed, iclass 14, count 0 2006.201.22:55:46.80#ibcon#about to write, iclass 14, count 0 2006.201.22:55:46.80#ibcon#wrote, iclass 14, count 0 2006.201.22:55:46.80#ibcon#about to read 3, iclass 14, count 0 2006.201.22:55:46.82#ibcon#read 3, iclass 14, count 0 2006.201.22:55:46.82#ibcon#about to read 4, iclass 14, count 0 2006.201.22:55:46.82#ibcon#read 4, iclass 14, count 0 2006.201.22:55:46.82#ibcon#about to read 5, iclass 14, count 0 2006.201.22:55:46.82#ibcon#read 5, iclass 14, count 0 2006.201.22:55:46.82#ibcon#about to read 6, iclass 14, count 0 2006.201.22:55:46.82#ibcon#read 6, iclass 14, count 0 2006.201.22:55:46.82#ibcon#end of sib2, iclass 14, count 0 2006.201.22:55:46.82#ibcon#*mode == 0, iclass 14, count 0 2006.201.22:55:46.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.22:55:46.82#ibcon#[25=USB\r\n] 2006.201.22:55:46.82#ibcon#*before write, iclass 14, count 0 2006.201.22:55:46.82#ibcon#enter sib2, iclass 14, count 0 2006.201.22:55:46.82#ibcon#flushed, iclass 14, count 0 2006.201.22:55:46.82#ibcon#about to write, iclass 14, count 0 2006.201.22:55:46.82#ibcon#wrote, iclass 14, count 0 2006.201.22:55:46.82#ibcon#about to read 3, iclass 14, count 0 2006.201.22:55:46.85#ibcon#read 3, iclass 14, count 0 2006.201.22:55:46.85#ibcon#about to read 4, iclass 14, count 0 2006.201.22:55:46.85#ibcon#read 4, iclass 14, count 0 2006.201.22:55:46.85#ibcon#about to read 5, iclass 14, count 0 2006.201.22:55:46.85#ibcon#read 5, iclass 14, count 0 2006.201.22:55:46.85#ibcon#about to read 6, iclass 14, count 0 2006.201.22:55:46.85#ibcon#read 6, iclass 14, count 0 2006.201.22:55:46.85#ibcon#end of sib2, iclass 14, count 0 2006.201.22:55:46.85#ibcon#*after write, iclass 14, count 0 2006.201.22:55:46.85#ibcon#*before return 0, iclass 14, count 0 2006.201.22:55:46.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:46.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:46.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.22:55:46.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.22:55:46.85$vck44/valo=4,624.99 2006.201.22:55:46.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.22:55:46.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.22:55:46.85#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:46.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:46.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:46.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:46.85#ibcon#enter wrdev, iclass 16, count 0 2006.201.22:55:46.85#ibcon#first serial, iclass 16, count 0 2006.201.22:55:46.85#ibcon#enter sib2, iclass 16, count 0 2006.201.22:55:46.85#ibcon#flushed, iclass 16, count 0 2006.201.22:55:46.85#ibcon#about to write, iclass 16, count 0 2006.201.22:55:46.85#ibcon#wrote, iclass 16, count 0 2006.201.22:55:46.85#ibcon#about to read 3, iclass 16, count 0 2006.201.22:55:46.87#ibcon#read 3, iclass 16, count 0 2006.201.22:55:46.87#ibcon#about to read 4, iclass 16, count 0 2006.201.22:55:46.87#ibcon#read 4, iclass 16, count 0 2006.201.22:55:46.87#ibcon#about to read 5, iclass 16, count 0 2006.201.22:55:46.87#ibcon#read 5, iclass 16, count 0 2006.201.22:55:46.87#ibcon#about to read 6, iclass 16, count 0 2006.201.22:55:46.87#ibcon#read 6, iclass 16, count 0 2006.201.22:55:46.87#ibcon#end of sib2, iclass 16, count 0 2006.201.22:55:46.87#ibcon#*mode == 0, iclass 16, count 0 2006.201.22:55:46.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.22:55:46.87#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.22:55:46.87#ibcon#*before write, iclass 16, count 0 2006.201.22:55:46.87#ibcon#enter sib2, iclass 16, count 0 2006.201.22:55:46.87#ibcon#flushed, iclass 16, count 0 2006.201.22:55:46.87#ibcon#about to write, iclass 16, count 0 2006.201.22:55:46.87#ibcon#wrote, iclass 16, count 0 2006.201.22:55:46.87#ibcon#about to read 3, iclass 16, count 0 2006.201.22:55:46.92#ibcon#read 3, iclass 16, count 0 2006.201.22:55:46.92#ibcon#about to read 4, iclass 16, count 0 2006.201.22:55:46.92#ibcon#read 4, iclass 16, count 0 2006.201.22:55:46.92#ibcon#about to read 5, iclass 16, count 0 2006.201.22:55:46.92#ibcon#read 5, iclass 16, count 0 2006.201.22:55:46.92#ibcon#about to read 6, iclass 16, count 0 2006.201.22:55:46.92#ibcon#read 6, iclass 16, count 0 2006.201.22:55:46.92#ibcon#end of sib2, iclass 16, count 0 2006.201.22:55:46.92#ibcon#*after write, iclass 16, count 0 2006.201.22:55:46.92#ibcon#*before return 0, iclass 16, count 0 2006.201.22:55:46.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:46.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:46.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.22:55:46.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.22:55:46.92$vck44/va=4,7 2006.201.22:55:46.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.22:55:46.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.22:55:46.92#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:46.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:46.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:46.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:46.97#ibcon#enter wrdev, iclass 18, count 2 2006.201.22:55:46.97#ibcon#first serial, iclass 18, count 2 2006.201.22:55:46.97#ibcon#enter sib2, iclass 18, count 2 2006.201.22:55:46.97#ibcon#flushed, iclass 18, count 2 2006.201.22:55:46.97#ibcon#about to write, iclass 18, count 2 2006.201.22:55:46.97#ibcon#wrote, iclass 18, count 2 2006.201.22:55:46.97#ibcon#about to read 3, iclass 18, count 2 2006.201.22:55:46.99#ibcon#read 3, iclass 18, count 2 2006.201.22:55:46.99#ibcon#about to read 4, iclass 18, count 2 2006.201.22:55:46.99#ibcon#read 4, iclass 18, count 2 2006.201.22:55:46.99#ibcon#about to read 5, iclass 18, count 2 2006.201.22:55:46.99#ibcon#read 5, iclass 18, count 2 2006.201.22:55:46.99#ibcon#about to read 6, iclass 18, count 2 2006.201.22:55:46.99#ibcon#read 6, iclass 18, count 2 2006.201.22:55:46.99#ibcon#end of sib2, iclass 18, count 2 2006.201.22:55:46.99#ibcon#*mode == 0, iclass 18, count 2 2006.201.22:55:46.99#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.22:55:46.99#ibcon#[25=AT04-07\r\n] 2006.201.22:55:46.99#ibcon#*before write, iclass 18, count 2 2006.201.22:55:46.99#ibcon#enter sib2, iclass 18, count 2 2006.201.22:55:46.99#ibcon#flushed, iclass 18, count 2 2006.201.22:55:46.99#ibcon#about to write, iclass 18, count 2 2006.201.22:55:46.99#ibcon#wrote, iclass 18, count 2 2006.201.22:55:46.99#ibcon#about to read 3, iclass 18, count 2 2006.201.22:55:47.02#ibcon#read 3, iclass 18, count 2 2006.201.22:55:47.02#ibcon#about to read 4, iclass 18, count 2 2006.201.22:55:47.02#ibcon#read 4, iclass 18, count 2 2006.201.22:55:47.02#ibcon#about to read 5, iclass 18, count 2 2006.201.22:55:47.02#ibcon#read 5, iclass 18, count 2 2006.201.22:55:47.02#ibcon#about to read 6, iclass 18, count 2 2006.201.22:55:47.02#ibcon#read 6, iclass 18, count 2 2006.201.22:55:47.02#ibcon#end of sib2, iclass 18, count 2 2006.201.22:55:47.02#ibcon#*after write, iclass 18, count 2 2006.201.22:55:47.02#ibcon#*before return 0, iclass 18, count 2 2006.201.22:55:47.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:47.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:47.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.22:55:47.02#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:47.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:47.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:47.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:47.14#ibcon#enter wrdev, iclass 18, count 0 2006.201.22:55:47.14#ibcon#first serial, iclass 18, count 0 2006.201.22:55:47.14#ibcon#enter sib2, iclass 18, count 0 2006.201.22:55:47.14#ibcon#flushed, iclass 18, count 0 2006.201.22:55:47.14#ibcon#about to write, iclass 18, count 0 2006.201.22:55:47.14#ibcon#wrote, iclass 18, count 0 2006.201.22:55:47.14#ibcon#about to read 3, iclass 18, count 0 2006.201.22:55:47.16#ibcon#read 3, iclass 18, count 0 2006.201.22:55:47.16#ibcon#about to read 4, iclass 18, count 0 2006.201.22:55:47.16#ibcon#read 4, iclass 18, count 0 2006.201.22:55:47.16#ibcon#about to read 5, iclass 18, count 0 2006.201.22:55:47.16#ibcon#read 5, iclass 18, count 0 2006.201.22:55:47.16#ibcon#about to read 6, iclass 18, count 0 2006.201.22:55:47.16#ibcon#read 6, iclass 18, count 0 2006.201.22:55:47.16#ibcon#end of sib2, iclass 18, count 0 2006.201.22:55:47.16#ibcon#*mode == 0, iclass 18, count 0 2006.201.22:55:47.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.22:55:47.16#ibcon#[25=USB\r\n] 2006.201.22:55:47.16#ibcon#*before write, iclass 18, count 0 2006.201.22:55:47.16#ibcon#enter sib2, iclass 18, count 0 2006.201.22:55:47.16#ibcon#flushed, iclass 18, count 0 2006.201.22:55:47.16#ibcon#about to write, iclass 18, count 0 2006.201.22:55:47.16#ibcon#wrote, iclass 18, count 0 2006.201.22:55:47.16#ibcon#about to read 3, iclass 18, count 0 2006.201.22:55:47.19#ibcon#read 3, iclass 18, count 0 2006.201.22:55:47.19#ibcon#about to read 4, iclass 18, count 0 2006.201.22:55:47.19#ibcon#read 4, iclass 18, count 0 2006.201.22:55:47.19#ibcon#about to read 5, iclass 18, count 0 2006.201.22:55:47.19#ibcon#read 5, iclass 18, count 0 2006.201.22:55:47.19#ibcon#about to read 6, iclass 18, count 0 2006.201.22:55:47.19#ibcon#read 6, iclass 18, count 0 2006.201.22:55:47.19#ibcon#end of sib2, iclass 18, count 0 2006.201.22:55:47.19#ibcon#*after write, iclass 18, count 0 2006.201.22:55:47.19#ibcon#*before return 0, iclass 18, count 0 2006.201.22:55:47.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:47.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:47.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.22:55:47.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.22:55:47.19$vck44/valo=5,734.99 2006.201.22:55:47.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.22:55:47.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.22:55:47.19#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:47.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:47.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:47.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:47.19#ibcon#enter wrdev, iclass 20, count 0 2006.201.22:55:47.19#ibcon#first serial, iclass 20, count 0 2006.201.22:55:47.19#ibcon#enter sib2, iclass 20, count 0 2006.201.22:55:47.19#ibcon#flushed, iclass 20, count 0 2006.201.22:55:47.19#ibcon#about to write, iclass 20, count 0 2006.201.22:55:47.19#ibcon#wrote, iclass 20, count 0 2006.201.22:55:47.19#ibcon#about to read 3, iclass 20, count 0 2006.201.22:55:47.21#ibcon#read 3, iclass 20, count 0 2006.201.22:55:47.21#ibcon#about to read 4, iclass 20, count 0 2006.201.22:55:47.21#ibcon#read 4, iclass 20, count 0 2006.201.22:55:47.21#ibcon#about to read 5, iclass 20, count 0 2006.201.22:55:47.21#ibcon#read 5, iclass 20, count 0 2006.201.22:55:47.21#ibcon#about to read 6, iclass 20, count 0 2006.201.22:55:47.21#ibcon#read 6, iclass 20, count 0 2006.201.22:55:47.21#ibcon#end of sib2, iclass 20, count 0 2006.201.22:55:47.21#ibcon#*mode == 0, iclass 20, count 0 2006.201.22:55:47.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.22:55:47.21#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.22:55:47.21#ibcon#*before write, iclass 20, count 0 2006.201.22:55:47.21#ibcon#enter sib2, iclass 20, count 0 2006.201.22:55:47.21#ibcon#flushed, iclass 20, count 0 2006.201.22:55:47.21#ibcon#about to write, iclass 20, count 0 2006.201.22:55:47.21#ibcon#wrote, iclass 20, count 0 2006.201.22:55:47.21#ibcon#about to read 3, iclass 20, count 0 2006.201.22:55:47.25#ibcon#read 3, iclass 20, count 0 2006.201.22:55:47.25#ibcon#about to read 4, iclass 20, count 0 2006.201.22:55:47.25#ibcon#read 4, iclass 20, count 0 2006.201.22:55:47.25#ibcon#about to read 5, iclass 20, count 0 2006.201.22:55:47.25#ibcon#read 5, iclass 20, count 0 2006.201.22:55:47.25#ibcon#about to read 6, iclass 20, count 0 2006.201.22:55:47.25#ibcon#read 6, iclass 20, count 0 2006.201.22:55:47.25#ibcon#end of sib2, iclass 20, count 0 2006.201.22:55:47.25#ibcon#*after write, iclass 20, count 0 2006.201.22:55:47.25#ibcon#*before return 0, iclass 20, count 0 2006.201.22:55:47.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:47.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:47.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.22:55:47.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.22:55:47.25$vck44/va=5,4 2006.201.22:55:47.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.22:55:47.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.22:55:47.25#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:47.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:47.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:47.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:47.31#ibcon#enter wrdev, iclass 22, count 2 2006.201.22:55:47.31#ibcon#first serial, iclass 22, count 2 2006.201.22:55:47.31#ibcon#enter sib2, iclass 22, count 2 2006.201.22:55:47.31#ibcon#flushed, iclass 22, count 2 2006.201.22:55:47.31#ibcon#about to write, iclass 22, count 2 2006.201.22:55:47.31#ibcon#wrote, iclass 22, count 2 2006.201.22:55:47.31#ibcon#about to read 3, iclass 22, count 2 2006.201.22:55:47.33#ibcon#read 3, iclass 22, count 2 2006.201.22:55:47.33#ibcon#about to read 4, iclass 22, count 2 2006.201.22:55:47.33#ibcon#read 4, iclass 22, count 2 2006.201.22:55:47.33#ibcon#about to read 5, iclass 22, count 2 2006.201.22:55:47.33#ibcon#read 5, iclass 22, count 2 2006.201.22:55:47.33#ibcon#about to read 6, iclass 22, count 2 2006.201.22:55:47.33#ibcon#read 6, iclass 22, count 2 2006.201.22:55:47.33#ibcon#end of sib2, iclass 22, count 2 2006.201.22:55:47.33#ibcon#*mode == 0, iclass 22, count 2 2006.201.22:55:47.33#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.22:55:47.33#ibcon#[25=AT05-04\r\n] 2006.201.22:55:47.33#ibcon#*before write, iclass 22, count 2 2006.201.22:55:47.33#ibcon#enter sib2, iclass 22, count 2 2006.201.22:55:47.33#ibcon#flushed, iclass 22, count 2 2006.201.22:55:47.33#ibcon#about to write, iclass 22, count 2 2006.201.22:55:47.33#ibcon#wrote, iclass 22, count 2 2006.201.22:55:47.33#ibcon#about to read 3, iclass 22, count 2 2006.201.22:55:47.36#ibcon#read 3, iclass 22, count 2 2006.201.22:55:47.36#ibcon#about to read 4, iclass 22, count 2 2006.201.22:55:47.36#ibcon#read 4, iclass 22, count 2 2006.201.22:55:47.36#ibcon#about to read 5, iclass 22, count 2 2006.201.22:55:47.36#ibcon#read 5, iclass 22, count 2 2006.201.22:55:47.36#ibcon#about to read 6, iclass 22, count 2 2006.201.22:55:47.36#ibcon#read 6, iclass 22, count 2 2006.201.22:55:47.36#ibcon#end of sib2, iclass 22, count 2 2006.201.22:55:47.36#ibcon#*after write, iclass 22, count 2 2006.201.22:55:47.36#ibcon#*before return 0, iclass 22, count 2 2006.201.22:55:47.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:47.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:47.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.22:55:47.36#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:47.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:47.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:47.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:47.48#ibcon#enter wrdev, iclass 22, count 0 2006.201.22:55:47.48#ibcon#first serial, iclass 22, count 0 2006.201.22:55:47.48#ibcon#enter sib2, iclass 22, count 0 2006.201.22:55:47.48#ibcon#flushed, iclass 22, count 0 2006.201.22:55:47.48#ibcon#about to write, iclass 22, count 0 2006.201.22:55:47.48#ibcon#wrote, iclass 22, count 0 2006.201.22:55:47.48#ibcon#about to read 3, iclass 22, count 0 2006.201.22:55:47.50#ibcon#read 3, iclass 22, count 0 2006.201.22:55:47.50#ibcon#about to read 4, iclass 22, count 0 2006.201.22:55:47.50#ibcon#read 4, iclass 22, count 0 2006.201.22:55:47.50#ibcon#about to read 5, iclass 22, count 0 2006.201.22:55:47.50#ibcon#read 5, iclass 22, count 0 2006.201.22:55:47.50#ibcon#about to read 6, iclass 22, count 0 2006.201.22:55:47.50#ibcon#read 6, iclass 22, count 0 2006.201.22:55:47.50#ibcon#end of sib2, iclass 22, count 0 2006.201.22:55:47.50#ibcon#*mode == 0, iclass 22, count 0 2006.201.22:55:47.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.22:55:47.50#ibcon#[25=USB\r\n] 2006.201.22:55:47.50#ibcon#*before write, iclass 22, count 0 2006.201.22:55:47.50#ibcon#enter sib2, iclass 22, count 0 2006.201.22:55:47.50#ibcon#flushed, iclass 22, count 0 2006.201.22:55:47.50#ibcon#about to write, iclass 22, count 0 2006.201.22:55:47.50#ibcon#wrote, iclass 22, count 0 2006.201.22:55:47.50#ibcon#about to read 3, iclass 22, count 0 2006.201.22:55:47.53#ibcon#read 3, iclass 22, count 0 2006.201.22:55:47.53#ibcon#about to read 4, iclass 22, count 0 2006.201.22:55:47.53#ibcon#read 4, iclass 22, count 0 2006.201.22:55:47.53#ibcon#about to read 5, iclass 22, count 0 2006.201.22:55:47.53#ibcon#read 5, iclass 22, count 0 2006.201.22:55:47.53#ibcon#about to read 6, iclass 22, count 0 2006.201.22:55:47.53#ibcon#read 6, iclass 22, count 0 2006.201.22:55:47.53#ibcon#end of sib2, iclass 22, count 0 2006.201.22:55:47.53#ibcon#*after write, iclass 22, count 0 2006.201.22:55:47.53#ibcon#*before return 0, iclass 22, count 0 2006.201.22:55:47.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:47.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:47.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.22:55:47.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.22:55:47.53$vck44/valo=6,814.99 2006.201.22:55:47.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.22:55:47.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.22:55:47.53#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:47.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:47.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:47.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:47.53#ibcon#enter wrdev, iclass 24, count 0 2006.201.22:55:47.53#ibcon#first serial, iclass 24, count 0 2006.201.22:55:47.53#ibcon#enter sib2, iclass 24, count 0 2006.201.22:55:47.53#ibcon#flushed, iclass 24, count 0 2006.201.22:55:47.53#ibcon#about to write, iclass 24, count 0 2006.201.22:55:47.53#ibcon#wrote, iclass 24, count 0 2006.201.22:55:47.53#ibcon#about to read 3, iclass 24, count 0 2006.201.22:55:47.55#ibcon#read 3, iclass 24, count 0 2006.201.22:55:47.55#ibcon#about to read 4, iclass 24, count 0 2006.201.22:55:47.55#ibcon#read 4, iclass 24, count 0 2006.201.22:55:47.55#ibcon#about to read 5, iclass 24, count 0 2006.201.22:55:47.55#ibcon#read 5, iclass 24, count 0 2006.201.22:55:47.55#ibcon#about to read 6, iclass 24, count 0 2006.201.22:55:47.55#ibcon#read 6, iclass 24, count 0 2006.201.22:55:47.55#ibcon#end of sib2, iclass 24, count 0 2006.201.22:55:47.55#ibcon#*mode == 0, iclass 24, count 0 2006.201.22:55:47.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.22:55:47.55#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.22:55:47.55#ibcon#*before write, iclass 24, count 0 2006.201.22:55:47.55#ibcon#enter sib2, iclass 24, count 0 2006.201.22:55:47.55#ibcon#flushed, iclass 24, count 0 2006.201.22:55:47.55#ibcon#about to write, iclass 24, count 0 2006.201.22:55:47.55#ibcon#wrote, iclass 24, count 0 2006.201.22:55:47.55#ibcon#about to read 3, iclass 24, count 0 2006.201.22:55:47.60#ibcon#read 3, iclass 24, count 0 2006.201.22:55:47.60#ibcon#about to read 4, iclass 24, count 0 2006.201.22:55:47.60#ibcon#read 4, iclass 24, count 0 2006.201.22:55:47.60#ibcon#about to read 5, iclass 24, count 0 2006.201.22:55:47.60#ibcon#read 5, iclass 24, count 0 2006.201.22:55:47.60#ibcon#about to read 6, iclass 24, count 0 2006.201.22:55:47.60#ibcon#read 6, iclass 24, count 0 2006.201.22:55:47.60#ibcon#end of sib2, iclass 24, count 0 2006.201.22:55:47.60#ibcon#*after write, iclass 24, count 0 2006.201.22:55:47.60#ibcon#*before return 0, iclass 24, count 0 2006.201.22:55:47.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:47.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:47.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.22:55:47.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.22:55:47.60$vck44/va=6,5 2006.201.22:55:47.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.22:55:47.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.22:55:47.60#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:47.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:47.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:47.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:47.65#ibcon#enter wrdev, iclass 26, count 2 2006.201.22:55:47.65#ibcon#first serial, iclass 26, count 2 2006.201.22:55:47.65#ibcon#enter sib2, iclass 26, count 2 2006.201.22:55:47.65#ibcon#flushed, iclass 26, count 2 2006.201.22:55:47.65#ibcon#about to write, iclass 26, count 2 2006.201.22:55:47.65#ibcon#wrote, iclass 26, count 2 2006.201.22:55:47.65#ibcon#about to read 3, iclass 26, count 2 2006.201.22:55:47.67#ibcon#read 3, iclass 26, count 2 2006.201.22:55:47.67#ibcon#about to read 4, iclass 26, count 2 2006.201.22:55:47.67#ibcon#read 4, iclass 26, count 2 2006.201.22:55:47.67#ibcon#about to read 5, iclass 26, count 2 2006.201.22:55:47.67#ibcon#read 5, iclass 26, count 2 2006.201.22:55:47.67#ibcon#about to read 6, iclass 26, count 2 2006.201.22:55:47.67#ibcon#read 6, iclass 26, count 2 2006.201.22:55:47.67#ibcon#end of sib2, iclass 26, count 2 2006.201.22:55:47.67#ibcon#*mode == 0, iclass 26, count 2 2006.201.22:55:47.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.22:55:47.67#ibcon#[25=AT06-05\r\n] 2006.201.22:55:47.67#ibcon#*before write, iclass 26, count 2 2006.201.22:55:47.67#ibcon#enter sib2, iclass 26, count 2 2006.201.22:55:47.67#ibcon#flushed, iclass 26, count 2 2006.201.22:55:47.67#ibcon#about to write, iclass 26, count 2 2006.201.22:55:47.67#ibcon#wrote, iclass 26, count 2 2006.201.22:55:47.67#ibcon#about to read 3, iclass 26, count 2 2006.201.22:55:47.70#ibcon#read 3, iclass 26, count 2 2006.201.22:55:47.70#ibcon#about to read 4, iclass 26, count 2 2006.201.22:55:47.70#ibcon#read 4, iclass 26, count 2 2006.201.22:55:47.70#ibcon#about to read 5, iclass 26, count 2 2006.201.22:55:47.70#ibcon#read 5, iclass 26, count 2 2006.201.22:55:47.70#ibcon#about to read 6, iclass 26, count 2 2006.201.22:55:47.70#ibcon#read 6, iclass 26, count 2 2006.201.22:55:47.70#ibcon#end of sib2, iclass 26, count 2 2006.201.22:55:47.70#ibcon#*after write, iclass 26, count 2 2006.201.22:55:47.70#ibcon#*before return 0, iclass 26, count 2 2006.201.22:55:47.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:47.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:47.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.22:55:47.70#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:47.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:47.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:47.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:47.82#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:55:47.82#ibcon#first serial, iclass 26, count 0 2006.201.22:55:47.82#ibcon#enter sib2, iclass 26, count 0 2006.201.22:55:47.82#ibcon#flushed, iclass 26, count 0 2006.201.22:55:47.82#ibcon#about to write, iclass 26, count 0 2006.201.22:55:47.82#ibcon#wrote, iclass 26, count 0 2006.201.22:55:47.82#ibcon#about to read 3, iclass 26, count 0 2006.201.22:55:47.84#ibcon#read 3, iclass 26, count 0 2006.201.22:55:47.84#ibcon#about to read 4, iclass 26, count 0 2006.201.22:55:47.84#ibcon#read 4, iclass 26, count 0 2006.201.22:55:47.84#ibcon#about to read 5, iclass 26, count 0 2006.201.22:55:47.84#ibcon#read 5, iclass 26, count 0 2006.201.22:55:47.84#ibcon#about to read 6, iclass 26, count 0 2006.201.22:55:47.84#ibcon#read 6, iclass 26, count 0 2006.201.22:55:47.84#ibcon#end of sib2, iclass 26, count 0 2006.201.22:55:47.84#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:55:47.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:55:47.84#ibcon#[25=USB\r\n] 2006.201.22:55:47.84#ibcon#*before write, iclass 26, count 0 2006.201.22:55:47.84#ibcon#enter sib2, iclass 26, count 0 2006.201.22:55:47.84#ibcon#flushed, iclass 26, count 0 2006.201.22:55:47.84#ibcon#about to write, iclass 26, count 0 2006.201.22:55:47.84#ibcon#wrote, iclass 26, count 0 2006.201.22:55:47.84#ibcon#about to read 3, iclass 26, count 0 2006.201.22:55:47.87#ibcon#read 3, iclass 26, count 0 2006.201.22:55:47.87#ibcon#about to read 4, iclass 26, count 0 2006.201.22:55:47.87#ibcon#read 4, iclass 26, count 0 2006.201.22:55:47.87#ibcon#about to read 5, iclass 26, count 0 2006.201.22:55:47.87#ibcon#read 5, iclass 26, count 0 2006.201.22:55:47.87#ibcon#about to read 6, iclass 26, count 0 2006.201.22:55:47.87#ibcon#read 6, iclass 26, count 0 2006.201.22:55:47.87#ibcon#end of sib2, iclass 26, count 0 2006.201.22:55:47.87#ibcon#*after write, iclass 26, count 0 2006.201.22:55:47.87#ibcon#*before return 0, iclass 26, count 0 2006.201.22:55:47.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:47.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:47.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:55:47.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:55:47.87$vck44/valo=7,864.99 2006.201.22:55:47.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.22:55:47.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.22:55:47.87#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:47.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:47.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:47.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:47.87#ibcon#enter wrdev, iclass 28, count 0 2006.201.22:55:47.87#ibcon#first serial, iclass 28, count 0 2006.201.22:55:47.87#ibcon#enter sib2, iclass 28, count 0 2006.201.22:55:47.87#ibcon#flushed, iclass 28, count 0 2006.201.22:55:47.87#ibcon#about to write, iclass 28, count 0 2006.201.22:55:47.87#ibcon#wrote, iclass 28, count 0 2006.201.22:55:47.87#ibcon#about to read 3, iclass 28, count 0 2006.201.22:55:47.89#ibcon#read 3, iclass 28, count 0 2006.201.22:55:47.89#ibcon#about to read 4, iclass 28, count 0 2006.201.22:55:47.89#ibcon#read 4, iclass 28, count 0 2006.201.22:55:47.89#ibcon#about to read 5, iclass 28, count 0 2006.201.22:55:47.89#ibcon#read 5, iclass 28, count 0 2006.201.22:55:47.89#ibcon#about to read 6, iclass 28, count 0 2006.201.22:55:47.89#ibcon#read 6, iclass 28, count 0 2006.201.22:55:47.89#ibcon#end of sib2, iclass 28, count 0 2006.201.22:55:47.89#ibcon#*mode == 0, iclass 28, count 0 2006.201.22:55:47.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.22:55:47.89#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.22:55:47.89#ibcon#*before write, iclass 28, count 0 2006.201.22:55:47.89#ibcon#enter sib2, iclass 28, count 0 2006.201.22:55:47.89#ibcon#flushed, iclass 28, count 0 2006.201.22:55:47.89#ibcon#about to write, iclass 28, count 0 2006.201.22:55:47.89#ibcon#wrote, iclass 28, count 0 2006.201.22:55:47.89#ibcon#about to read 3, iclass 28, count 0 2006.201.22:55:47.94#ibcon#read 3, iclass 28, count 0 2006.201.22:55:47.94#ibcon#about to read 4, iclass 28, count 0 2006.201.22:55:47.94#ibcon#read 4, iclass 28, count 0 2006.201.22:55:47.94#ibcon#about to read 5, iclass 28, count 0 2006.201.22:55:47.94#ibcon#read 5, iclass 28, count 0 2006.201.22:55:47.94#ibcon#about to read 6, iclass 28, count 0 2006.201.22:55:47.94#ibcon#read 6, iclass 28, count 0 2006.201.22:55:47.94#ibcon#end of sib2, iclass 28, count 0 2006.201.22:55:47.94#ibcon#*after write, iclass 28, count 0 2006.201.22:55:47.94#ibcon#*before return 0, iclass 28, count 0 2006.201.22:55:47.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:47.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:47.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.22:55:47.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.22:55:47.94$vck44/va=7,5 2006.201.22:55:47.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.22:55:47.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.22:55:47.94#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:47.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:47.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:47.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:47.99#ibcon#enter wrdev, iclass 30, count 2 2006.201.22:55:47.99#ibcon#first serial, iclass 30, count 2 2006.201.22:55:47.99#ibcon#enter sib2, iclass 30, count 2 2006.201.22:55:47.99#ibcon#flushed, iclass 30, count 2 2006.201.22:55:47.99#ibcon#about to write, iclass 30, count 2 2006.201.22:55:47.99#ibcon#wrote, iclass 30, count 2 2006.201.22:55:47.99#ibcon#about to read 3, iclass 30, count 2 2006.201.22:55:48.01#ibcon#read 3, iclass 30, count 2 2006.201.22:55:48.01#ibcon#about to read 4, iclass 30, count 2 2006.201.22:55:48.01#ibcon#read 4, iclass 30, count 2 2006.201.22:55:48.01#ibcon#about to read 5, iclass 30, count 2 2006.201.22:55:48.01#ibcon#read 5, iclass 30, count 2 2006.201.22:55:48.01#ibcon#about to read 6, iclass 30, count 2 2006.201.22:55:48.01#ibcon#read 6, iclass 30, count 2 2006.201.22:55:48.01#ibcon#end of sib2, iclass 30, count 2 2006.201.22:55:48.01#ibcon#*mode == 0, iclass 30, count 2 2006.201.22:55:48.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.22:55:48.01#ibcon#[25=AT07-05\r\n] 2006.201.22:55:48.01#ibcon#*before write, iclass 30, count 2 2006.201.22:55:48.01#ibcon#enter sib2, iclass 30, count 2 2006.201.22:55:48.01#ibcon#flushed, iclass 30, count 2 2006.201.22:55:48.01#ibcon#about to write, iclass 30, count 2 2006.201.22:55:48.01#ibcon#wrote, iclass 30, count 2 2006.201.22:55:48.01#ibcon#about to read 3, iclass 30, count 2 2006.201.22:55:48.04#ibcon#read 3, iclass 30, count 2 2006.201.22:55:48.04#ibcon#about to read 4, iclass 30, count 2 2006.201.22:55:48.04#ibcon#read 4, iclass 30, count 2 2006.201.22:55:48.04#ibcon#about to read 5, iclass 30, count 2 2006.201.22:55:48.04#ibcon#read 5, iclass 30, count 2 2006.201.22:55:48.04#ibcon#about to read 6, iclass 30, count 2 2006.201.22:55:48.04#ibcon#read 6, iclass 30, count 2 2006.201.22:55:48.04#ibcon#end of sib2, iclass 30, count 2 2006.201.22:55:48.04#ibcon#*after write, iclass 30, count 2 2006.201.22:55:48.04#ibcon#*before return 0, iclass 30, count 2 2006.201.22:55:48.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:48.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:48.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.22:55:48.04#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:48.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:48.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:48.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:48.16#ibcon#enter wrdev, iclass 30, count 0 2006.201.22:55:48.16#ibcon#first serial, iclass 30, count 0 2006.201.22:55:48.16#ibcon#enter sib2, iclass 30, count 0 2006.201.22:55:48.16#ibcon#flushed, iclass 30, count 0 2006.201.22:55:48.16#ibcon#about to write, iclass 30, count 0 2006.201.22:55:48.16#ibcon#wrote, iclass 30, count 0 2006.201.22:55:48.16#ibcon#about to read 3, iclass 30, count 0 2006.201.22:55:48.18#ibcon#read 3, iclass 30, count 0 2006.201.22:55:48.18#ibcon#about to read 4, iclass 30, count 0 2006.201.22:55:48.18#ibcon#read 4, iclass 30, count 0 2006.201.22:55:48.18#ibcon#about to read 5, iclass 30, count 0 2006.201.22:55:48.18#ibcon#read 5, iclass 30, count 0 2006.201.22:55:48.18#ibcon#about to read 6, iclass 30, count 0 2006.201.22:55:48.18#ibcon#read 6, iclass 30, count 0 2006.201.22:55:48.18#ibcon#end of sib2, iclass 30, count 0 2006.201.22:55:48.18#ibcon#*mode == 0, iclass 30, count 0 2006.201.22:55:48.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.22:55:48.18#ibcon#[25=USB\r\n] 2006.201.22:55:48.18#ibcon#*before write, iclass 30, count 0 2006.201.22:55:48.18#ibcon#enter sib2, iclass 30, count 0 2006.201.22:55:48.18#ibcon#flushed, iclass 30, count 0 2006.201.22:55:48.18#ibcon#about to write, iclass 30, count 0 2006.201.22:55:48.18#ibcon#wrote, iclass 30, count 0 2006.201.22:55:48.18#ibcon#about to read 3, iclass 30, count 0 2006.201.22:55:48.21#ibcon#read 3, iclass 30, count 0 2006.201.22:55:48.21#ibcon#about to read 4, iclass 30, count 0 2006.201.22:55:48.21#ibcon#read 4, iclass 30, count 0 2006.201.22:55:48.21#ibcon#about to read 5, iclass 30, count 0 2006.201.22:55:48.21#ibcon#read 5, iclass 30, count 0 2006.201.22:55:48.21#ibcon#about to read 6, iclass 30, count 0 2006.201.22:55:48.21#ibcon#read 6, iclass 30, count 0 2006.201.22:55:48.21#ibcon#end of sib2, iclass 30, count 0 2006.201.22:55:48.21#ibcon#*after write, iclass 30, count 0 2006.201.22:55:48.21#ibcon#*before return 0, iclass 30, count 0 2006.201.22:55:48.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:48.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:48.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.22:55:48.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.22:55:48.21$vck44/valo=8,884.99 2006.201.22:55:48.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.22:55:48.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.22:55:48.21#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:48.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:48.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:48.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:48.21#ibcon#enter wrdev, iclass 32, count 0 2006.201.22:55:48.21#ibcon#first serial, iclass 32, count 0 2006.201.22:55:48.21#ibcon#enter sib2, iclass 32, count 0 2006.201.22:55:48.21#ibcon#flushed, iclass 32, count 0 2006.201.22:55:48.21#ibcon#about to write, iclass 32, count 0 2006.201.22:55:48.21#ibcon#wrote, iclass 32, count 0 2006.201.22:55:48.21#ibcon#about to read 3, iclass 32, count 0 2006.201.22:55:48.23#ibcon#read 3, iclass 32, count 0 2006.201.22:55:48.23#ibcon#about to read 4, iclass 32, count 0 2006.201.22:55:48.23#ibcon#read 4, iclass 32, count 0 2006.201.22:55:48.23#ibcon#about to read 5, iclass 32, count 0 2006.201.22:55:48.23#ibcon#read 5, iclass 32, count 0 2006.201.22:55:48.23#ibcon#about to read 6, iclass 32, count 0 2006.201.22:55:48.23#ibcon#read 6, iclass 32, count 0 2006.201.22:55:48.23#ibcon#end of sib2, iclass 32, count 0 2006.201.22:55:48.23#ibcon#*mode == 0, iclass 32, count 0 2006.201.22:55:48.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.22:55:48.23#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.22:55:48.23#ibcon#*before write, iclass 32, count 0 2006.201.22:55:48.23#ibcon#enter sib2, iclass 32, count 0 2006.201.22:55:48.23#ibcon#flushed, iclass 32, count 0 2006.201.22:55:48.23#ibcon#about to write, iclass 32, count 0 2006.201.22:55:48.23#ibcon#wrote, iclass 32, count 0 2006.201.22:55:48.23#ibcon#about to read 3, iclass 32, count 0 2006.201.22:55:48.27#ibcon#read 3, iclass 32, count 0 2006.201.22:55:48.27#ibcon#about to read 4, iclass 32, count 0 2006.201.22:55:48.27#ibcon#read 4, iclass 32, count 0 2006.201.22:55:48.27#ibcon#about to read 5, iclass 32, count 0 2006.201.22:55:48.27#ibcon#read 5, iclass 32, count 0 2006.201.22:55:48.27#ibcon#about to read 6, iclass 32, count 0 2006.201.22:55:48.27#ibcon#read 6, iclass 32, count 0 2006.201.22:55:48.27#ibcon#end of sib2, iclass 32, count 0 2006.201.22:55:48.27#ibcon#*after write, iclass 32, count 0 2006.201.22:55:48.27#ibcon#*before return 0, iclass 32, count 0 2006.201.22:55:48.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:48.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:48.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.22:55:48.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.22:55:48.27$vck44/va=8,4 2006.201.22:55:48.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.22:55:48.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.22:55:48.27#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:48.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:55:48.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:55:48.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:55:48.33#ibcon#enter wrdev, iclass 34, count 2 2006.201.22:55:48.33#ibcon#first serial, iclass 34, count 2 2006.201.22:55:48.33#ibcon#enter sib2, iclass 34, count 2 2006.201.22:55:48.33#ibcon#flushed, iclass 34, count 2 2006.201.22:55:48.33#ibcon#about to write, iclass 34, count 2 2006.201.22:55:48.33#ibcon#wrote, iclass 34, count 2 2006.201.22:55:48.33#ibcon#about to read 3, iclass 34, count 2 2006.201.22:55:48.35#ibcon#read 3, iclass 34, count 2 2006.201.22:55:48.35#ibcon#about to read 4, iclass 34, count 2 2006.201.22:55:48.35#ibcon#read 4, iclass 34, count 2 2006.201.22:55:48.35#ibcon#about to read 5, iclass 34, count 2 2006.201.22:55:48.35#ibcon#read 5, iclass 34, count 2 2006.201.22:55:48.35#ibcon#about to read 6, iclass 34, count 2 2006.201.22:55:48.35#ibcon#read 6, iclass 34, count 2 2006.201.22:55:48.35#ibcon#end of sib2, iclass 34, count 2 2006.201.22:55:48.35#ibcon#*mode == 0, iclass 34, count 2 2006.201.22:55:48.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.22:55:48.35#ibcon#[25=AT08-04\r\n] 2006.201.22:55:48.35#ibcon#*before write, iclass 34, count 2 2006.201.22:55:48.35#ibcon#enter sib2, iclass 34, count 2 2006.201.22:55:48.35#ibcon#flushed, iclass 34, count 2 2006.201.22:55:48.35#ibcon#about to write, iclass 34, count 2 2006.201.22:55:48.35#ibcon#wrote, iclass 34, count 2 2006.201.22:55:48.35#ibcon#about to read 3, iclass 34, count 2 2006.201.22:55:48.38#ibcon#read 3, iclass 34, count 2 2006.201.22:55:48.38#ibcon#about to read 4, iclass 34, count 2 2006.201.22:55:48.38#ibcon#read 4, iclass 34, count 2 2006.201.22:55:48.38#ibcon#about to read 5, iclass 34, count 2 2006.201.22:55:48.38#ibcon#read 5, iclass 34, count 2 2006.201.22:55:48.38#ibcon#about to read 6, iclass 34, count 2 2006.201.22:55:48.38#ibcon#read 6, iclass 34, count 2 2006.201.22:55:48.38#ibcon#end of sib2, iclass 34, count 2 2006.201.22:55:48.38#ibcon#*after write, iclass 34, count 2 2006.201.22:55:48.38#ibcon#*before return 0, iclass 34, count 2 2006.201.22:55:48.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:55:48.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.22:55:48.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.22:55:48.38#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:48.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:55:48.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:55:48.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:55:48.50#ibcon#enter wrdev, iclass 34, count 0 2006.201.22:55:48.50#ibcon#first serial, iclass 34, count 0 2006.201.22:55:48.50#ibcon#enter sib2, iclass 34, count 0 2006.201.22:55:48.50#ibcon#flushed, iclass 34, count 0 2006.201.22:55:48.50#ibcon#about to write, iclass 34, count 0 2006.201.22:55:48.50#ibcon#wrote, iclass 34, count 0 2006.201.22:55:48.50#ibcon#about to read 3, iclass 34, count 0 2006.201.22:55:48.52#ibcon#read 3, iclass 34, count 0 2006.201.22:55:48.52#ibcon#about to read 4, iclass 34, count 0 2006.201.22:55:48.52#ibcon#read 4, iclass 34, count 0 2006.201.22:55:48.52#ibcon#about to read 5, iclass 34, count 0 2006.201.22:55:48.52#ibcon#read 5, iclass 34, count 0 2006.201.22:55:48.52#ibcon#about to read 6, iclass 34, count 0 2006.201.22:55:48.52#ibcon#read 6, iclass 34, count 0 2006.201.22:55:48.52#ibcon#end of sib2, iclass 34, count 0 2006.201.22:55:48.52#ibcon#*mode == 0, iclass 34, count 0 2006.201.22:55:48.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.22:55:48.52#ibcon#[25=USB\r\n] 2006.201.22:55:48.52#ibcon#*before write, iclass 34, count 0 2006.201.22:55:48.52#ibcon#enter sib2, iclass 34, count 0 2006.201.22:55:48.52#ibcon#flushed, iclass 34, count 0 2006.201.22:55:48.52#ibcon#about to write, iclass 34, count 0 2006.201.22:55:48.52#ibcon#wrote, iclass 34, count 0 2006.201.22:55:48.52#ibcon#about to read 3, iclass 34, count 0 2006.201.22:55:48.55#ibcon#read 3, iclass 34, count 0 2006.201.22:55:48.55#ibcon#about to read 4, iclass 34, count 0 2006.201.22:55:48.55#ibcon#read 4, iclass 34, count 0 2006.201.22:55:48.55#ibcon#about to read 5, iclass 34, count 0 2006.201.22:55:48.55#ibcon#read 5, iclass 34, count 0 2006.201.22:55:48.55#ibcon#about to read 6, iclass 34, count 0 2006.201.22:55:48.55#ibcon#read 6, iclass 34, count 0 2006.201.22:55:48.55#ibcon#end of sib2, iclass 34, count 0 2006.201.22:55:48.55#ibcon#*after write, iclass 34, count 0 2006.201.22:55:48.55#ibcon#*before return 0, iclass 34, count 0 2006.201.22:55:48.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:55:48.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.22:55:48.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.22:55:48.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.22:55:48.55$vck44/vblo=1,629.99 2006.201.22:55:48.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.22:55:48.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.22:55:48.55#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:48.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:55:48.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:55:48.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:55:48.55#ibcon#enter wrdev, iclass 36, count 0 2006.201.22:55:48.55#ibcon#first serial, iclass 36, count 0 2006.201.22:55:48.55#ibcon#enter sib2, iclass 36, count 0 2006.201.22:55:48.55#ibcon#flushed, iclass 36, count 0 2006.201.22:55:48.55#ibcon#about to write, iclass 36, count 0 2006.201.22:55:48.55#ibcon#wrote, iclass 36, count 0 2006.201.22:55:48.55#ibcon#about to read 3, iclass 36, count 0 2006.201.22:55:48.57#ibcon#read 3, iclass 36, count 0 2006.201.22:55:48.57#ibcon#about to read 4, iclass 36, count 0 2006.201.22:55:48.57#ibcon#read 4, iclass 36, count 0 2006.201.22:55:48.57#ibcon#about to read 5, iclass 36, count 0 2006.201.22:55:48.57#ibcon#read 5, iclass 36, count 0 2006.201.22:55:48.57#ibcon#about to read 6, iclass 36, count 0 2006.201.22:55:48.57#ibcon#read 6, iclass 36, count 0 2006.201.22:55:48.57#ibcon#end of sib2, iclass 36, count 0 2006.201.22:55:48.57#ibcon#*mode == 0, iclass 36, count 0 2006.201.22:55:48.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.22:55:48.57#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.22:55:48.57#ibcon#*before write, iclass 36, count 0 2006.201.22:55:48.57#ibcon#enter sib2, iclass 36, count 0 2006.201.22:55:48.57#ibcon#flushed, iclass 36, count 0 2006.201.22:55:48.57#ibcon#about to write, iclass 36, count 0 2006.201.22:55:48.57#ibcon#wrote, iclass 36, count 0 2006.201.22:55:48.57#ibcon#about to read 3, iclass 36, count 0 2006.201.22:55:48.62#ibcon#read 3, iclass 36, count 0 2006.201.22:55:48.62#ibcon#about to read 4, iclass 36, count 0 2006.201.22:55:48.62#ibcon#read 4, iclass 36, count 0 2006.201.22:55:48.62#ibcon#about to read 5, iclass 36, count 0 2006.201.22:55:48.62#ibcon#read 5, iclass 36, count 0 2006.201.22:55:48.62#ibcon#about to read 6, iclass 36, count 0 2006.201.22:55:48.62#ibcon#read 6, iclass 36, count 0 2006.201.22:55:48.62#ibcon#end of sib2, iclass 36, count 0 2006.201.22:55:48.62#ibcon#*after write, iclass 36, count 0 2006.201.22:55:48.62#ibcon#*before return 0, iclass 36, count 0 2006.201.22:55:48.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:55:48.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.22:55:48.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.22:55:48.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.22:55:48.62$vck44/vb=1,4 2006.201.22:55:48.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.22:55:48.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.22:55:48.62#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:48.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:55:48.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:55:48.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:55:48.62#ibcon#enter wrdev, iclass 38, count 2 2006.201.22:55:48.62#ibcon#first serial, iclass 38, count 2 2006.201.22:55:48.62#ibcon#enter sib2, iclass 38, count 2 2006.201.22:55:48.62#ibcon#flushed, iclass 38, count 2 2006.201.22:55:48.62#ibcon#about to write, iclass 38, count 2 2006.201.22:55:48.62#ibcon#wrote, iclass 38, count 2 2006.201.22:55:48.62#ibcon#about to read 3, iclass 38, count 2 2006.201.22:55:48.64#ibcon#read 3, iclass 38, count 2 2006.201.22:55:48.64#ibcon#about to read 4, iclass 38, count 2 2006.201.22:55:48.64#ibcon#read 4, iclass 38, count 2 2006.201.22:55:48.64#ibcon#about to read 5, iclass 38, count 2 2006.201.22:55:48.64#ibcon#read 5, iclass 38, count 2 2006.201.22:55:48.64#ibcon#about to read 6, iclass 38, count 2 2006.201.22:55:48.64#ibcon#read 6, iclass 38, count 2 2006.201.22:55:48.64#ibcon#end of sib2, iclass 38, count 2 2006.201.22:55:48.64#ibcon#*mode == 0, iclass 38, count 2 2006.201.22:55:48.64#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.22:55:48.64#ibcon#[27=AT01-04\r\n] 2006.201.22:55:48.64#ibcon#*before write, iclass 38, count 2 2006.201.22:55:48.64#ibcon#enter sib2, iclass 38, count 2 2006.201.22:55:48.64#ibcon#flushed, iclass 38, count 2 2006.201.22:55:48.64#ibcon#about to write, iclass 38, count 2 2006.201.22:55:48.64#ibcon#wrote, iclass 38, count 2 2006.201.22:55:48.64#ibcon#about to read 3, iclass 38, count 2 2006.201.22:55:48.67#ibcon#read 3, iclass 38, count 2 2006.201.22:55:48.67#ibcon#about to read 4, iclass 38, count 2 2006.201.22:55:48.67#ibcon#read 4, iclass 38, count 2 2006.201.22:55:48.67#ibcon#about to read 5, iclass 38, count 2 2006.201.22:55:48.67#ibcon#read 5, iclass 38, count 2 2006.201.22:55:48.67#ibcon#about to read 6, iclass 38, count 2 2006.201.22:55:48.67#ibcon#read 6, iclass 38, count 2 2006.201.22:55:48.67#ibcon#end of sib2, iclass 38, count 2 2006.201.22:55:48.67#ibcon#*after write, iclass 38, count 2 2006.201.22:55:48.67#ibcon#*before return 0, iclass 38, count 2 2006.201.22:55:48.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:55:48.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.22:55:48.67#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.22:55:48.67#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:48.67#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:55:48.79#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:55:48.79#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:55:48.79#ibcon#enter wrdev, iclass 38, count 0 2006.201.22:55:48.79#ibcon#first serial, iclass 38, count 0 2006.201.22:55:48.79#ibcon#enter sib2, iclass 38, count 0 2006.201.22:55:48.79#ibcon#flushed, iclass 38, count 0 2006.201.22:55:48.79#ibcon#about to write, iclass 38, count 0 2006.201.22:55:48.79#ibcon#wrote, iclass 38, count 0 2006.201.22:55:48.79#ibcon#about to read 3, iclass 38, count 0 2006.201.22:55:48.81#ibcon#read 3, iclass 38, count 0 2006.201.22:55:48.81#ibcon#about to read 4, iclass 38, count 0 2006.201.22:55:48.81#ibcon#read 4, iclass 38, count 0 2006.201.22:55:48.81#ibcon#about to read 5, iclass 38, count 0 2006.201.22:55:48.81#ibcon#read 5, iclass 38, count 0 2006.201.22:55:48.81#ibcon#about to read 6, iclass 38, count 0 2006.201.22:55:48.81#ibcon#read 6, iclass 38, count 0 2006.201.22:55:48.81#ibcon#end of sib2, iclass 38, count 0 2006.201.22:55:48.81#ibcon#*mode == 0, iclass 38, count 0 2006.201.22:55:48.81#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.22:55:48.81#ibcon#[27=USB\r\n] 2006.201.22:55:48.81#ibcon#*before write, iclass 38, count 0 2006.201.22:55:48.81#ibcon#enter sib2, iclass 38, count 0 2006.201.22:55:48.81#ibcon#flushed, iclass 38, count 0 2006.201.22:55:48.81#ibcon#about to write, iclass 38, count 0 2006.201.22:55:48.81#ibcon#wrote, iclass 38, count 0 2006.201.22:55:48.81#ibcon#about to read 3, iclass 38, count 0 2006.201.22:55:48.84#ibcon#read 3, iclass 38, count 0 2006.201.22:55:48.84#ibcon#about to read 4, iclass 38, count 0 2006.201.22:55:48.84#ibcon#read 4, iclass 38, count 0 2006.201.22:55:48.84#ibcon#about to read 5, iclass 38, count 0 2006.201.22:55:48.84#ibcon#read 5, iclass 38, count 0 2006.201.22:55:48.84#ibcon#about to read 6, iclass 38, count 0 2006.201.22:55:48.84#ibcon#read 6, iclass 38, count 0 2006.201.22:55:48.84#ibcon#end of sib2, iclass 38, count 0 2006.201.22:55:48.84#ibcon#*after write, iclass 38, count 0 2006.201.22:55:48.84#ibcon#*before return 0, iclass 38, count 0 2006.201.22:55:48.84#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:55:48.84#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.22:55:48.84#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.22:55:48.84#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.22:55:48.84$vck44/vblo=2,634.99 2006.201.22:55:48.84#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.22:55:48.84#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.22:55:48.84#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:48.84#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:48.84#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:48.84#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:48.84#ibcon#enter wrdev, iclass 40, count 0 2006.201.22:55:48.84#ibcon#first serial, iclass 40, count 0 2006.201.22:55:48.84#ibcon#enter sib2, iclass 40, count 0 2006.201.22:55:48.84#ibcon#flushed, iclass 40, count 0 2006.201.22:55:48.84#ibcon#about to write, iclass 40, count 0 2006.201.22:55:48.84#ibcon#wrote, iclass 40, count 0 2006.201.22:55:48.84#ibcon#about to read 3, iclass 40, count 0 2006.201.22:55:48.86#ibcon#read 3, iclass 40, count 0 2006.201.22:55:48.86#ibcon#about to read 4, iclass 40, count 0 2006.201.22:55:48.86#ibcon#read 4, iclass 40, count 0 2006.201.22:55:48.86#ibcon#about to read 5, iclass 40, count 0 2006.201.22:55:48.86#ibcon#read 5, iclass 40, count 0 2006.201.22:55:48.86#ibcon#about to read 6, iclass 40, count 0 2006.201.22:55:48.86#ibcon#read 6, iclass 40, count 0 2006.201.22:55:48.86#ibcon#end of sib2, iclass 40, count 0 2006.201.22:55:48.86#ibcon#*mode == 0, iclass 40, count 0 2006.201.22:55:48.86#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.22:55:48.86#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.22:55:48.86#ibcon#*before write, iclass 40, count 0 2006.201.22:55:48.86#ibcon#enter sib2, iclass 40, count 0 2006.201.22:55:48.86#ibcon#flushed, iclass 40, count 0 2006.201.22:55:48.86#ibcon#about to write, iclass 40, count 0 2006.201.22:55:48.86#ibcon#wrote, iclass 40, count 0 2006.201.22:55:48.86#ibcon#about to read 3, iclass 40, count 0 2006.201.22:55:48.90#ibcon#read 3, iclass 40, count 0 2006.201.22:55:48.90#ibcon#about to read 4, iclass 40, count 0 2006.201.22:55:48.90#ibcon#read 4, iclass 40, count 0 2006.201.22:55:48.90#ibcon#about to read 5, iclass 40, count 0 2006.201.22:55:48.90#ibcon#read 5, iclass 40, count 0 2006.201.22:55:48.90#ibcon#about to read 6, iclass 40, count 0 2006.201.22:55:48.90#ibcon#read 6, iclass 40, count 0 2006.201.22:55:48.90#ibcon#end of sib2, iclass 40, count 0 2006.201.22:55:48.90#ibcon#*after write, iclass 40, count 0 2006.201.22:55:48.90#ibcon#*before return 0, iclass 40, count 0 2006.201.22:55:48.90#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:48.90#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.22:55:48.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.22:55:48.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.22:55:48.90$vck44/vb=2,5 2006.201.22:55:48.90#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.22:55:48.90#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.22:55:48.90#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:48.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:48.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:48.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:48.96#ibcon#enter wrdev, iclass 4, count 2 2006.201.22:55:48.96#ibcon#first serial, iclass 4, count 2 2006.201.22:55:48.96#ibcon#enter sib2, iclass 4, count 2 2006.201.22:55:48.96#ibcon#flushed, iclass 4, count 2 2006.201.22:55:48.96#ibcon#about to write, iclass 4, count 2 2006.201.22:55:48.96#ibcon#wrote, iclass 4, count 2 2006.201.22:55:48.96#ibcon#about to read 3, iclass 4, count 2 2006.201.22:55:48.98#ibcon#read 3, iclass 4, count 2 2006.201.22:55:48.98#ibcon#about to read 4, iclass 4, count 2 2006.201.22:55:48.98#ibcon#read 4, iclass 4, count 2 2006.201.22:55:48.98#ibcon#about to read 5, iclass 4, count 2 2006.201.22:55:48.98#ibcon#read 5, iclass 4, count 2 2006.201.22:55:48.98#ibcon#about to read 6, iclass 4, count 2 2006.201.22:55:48.98#ibcon#read 6, iclass 4, count 2 2006.201.22:55:48.98#ibcon#end of sib2, iclass 4, count 2 2006.201.22:55:48.98#ibcon#*mode == 0, iclass 4, count 2 2006.201.22:55:48.98#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.22:55:48.98#ibcon#[27=AT02-05\r\n] 2006.201.22:55:48.98#ibcon#*before write, iclass 4, count 2 2006.201.22:55:48.98#ibcon#enter sib2, iclass 4, count 2 2006.201.22:55:48.98#ibcon#flushed, iclass 4, count 2 2006.201.22:55:48.98#ibcon#about to write, iclass 4, count 2 2006.201.22:55:48.98#ibcon#wrote, iclass 4, count 2 2006.201.22:55:48.98#ibcon#about to read 3, iclass 4, count 2 2006.201.22:55:49.01#ibcon#read 3, iclass 4, count 2 2006.201.22:55:49.01#ibcon#about to read 4, iclass 4, count 2 2006.201.22:55:49.01#ibcon#read 4, iclass 4, count 2 2006.201.22:55:49.01#ibcon#about to read 5, iclass 4, count 2 2006.201.22:55:49.01#ibcon#read 5, iclass 4, count 2 2006.201.22:55:49.01#ibcon#about to read 6, iclass 4, count 2 2006.201.22:55:49.01#ibcon#read 6, iclass 4, count 2 2006.201.22:55:49.01#ibcon#end of sib2, iclass 4, count 2 2006.201.22:55:49.01#ibcon#*after write, iclass 4, count 2 2006.201.22:55:49.01#ibcon#*before return 0, iclass 4, count 2 2006.201.22:55:49.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:49.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.22:55:49.01#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.22:55:49.01#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:49.01#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:49.13#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:49.13#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:49.13#ibcon#enter wrdev, iclass 4, count 0 2006.201.22:55:49.13#ibcon#first serial, iclass 4, count 0 2006.201.22:55:49.13#ibcon#enter sib2, iclass 4, count 0 2006.201.22:55:49.13#ibcon#flushed, iclass 4, count 0 2006.201.22:55:49.13#ibcon#about to write, iclass 4, count 0 2006.201.22:55:49.13#ibcon#wrote, iclass 4, count 0 2006.201.22:55:49.13#ibcon#about to read 3, iclass 4, count 0 2006.201.22:55:49.15#ibcon#read 3, iclass 4, count 0 2006.201.22:55:49.15#ibcon#about to read 4, iclass 4, count 0 2006.201.22:55:49.15#ibcon#read 4, iclass 4, count 0 2006.201.22:55:49.15#ibcon#about to read 5, iclass 4, count 0 2006.201.22:55:49.15#ibcon#read 5, iclass 4, count 0 2006.201.22:55:49.15#ibcon#about to read 6, iclass 4, count 0 2006.201.22:55:49.15#ibcon#read 6, iclass 4, count 0 2006.201.22:55:49.15#ibcon#end of sib2, iclass 4, count 0 2006.201.22:55:49.15#ibcon#*mode == 0, iclass 4, count 0 2006.201.22:55:49.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.22:55:49.15#ibcon#[27=USB\r\n] 2006.201.22:55:49.15#ibcon#*before write, iclass 4, count 0 2006.201.22:55:49.15#ibcon#enter sib2, iclass 4, count 0 2006.201.22:55:49.15#ibcon#flushed, iclass 4, count 0 2006.201.22:55:49.15#ibcon#about to write, iclass 4, count 0 2006.201.22:55:49.15#ibcon#wrote, iclass 4, count 0 2006.201.22:55:49.15#ibcon#about to read 3, iclass 4, count 0 2006.201.22:55:49.18#ibcon#read 3, iclass 4, count 0 2006.201.22:55:49.18#ibcon#about to read 4, iclass 4, count 0 2006.201.22:55:49.18#ibcon#read 4, iclass 4, count 0 2006.201.22:55:49.18#ibcon#about to read 5, iclass 4, count 0 2006.201.22:55:49.18#ibcon#read 5, iclass 4, count 0 2006.201.22:55:49.18#ibcon#about to read 6, iclass 4, count 0 2006.201.22:55:49.18#ibcon#read 6, iclass 4, count 0 2006.201.22:55:49.18#ibcon#end of sib2, iclass 4, count 0 2006.201.22:55:49.18#ibcon#*after write, iclass 4, count 0 2006.201.22:55:49.18#ibcon#*before return 0, iclass 4, count 0 2006.201.22:55:49.18#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:49.18#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.22:55:49.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.22:55:49.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.22:55:49.18$vck44/vblo=3,649.99 2006.201.22:55:49.18#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.22:55:49.18#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.22:55:49.18#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:49.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:49.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:49.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:49.18#ibcon#enter wrdev, iclass 6, count 0 2006.201.22:55:49.18#ibcon#first serial, iclass 6, count 0 2006.201.22:55:49.18#ibcon#enter sib2, iclass 6, count 0 2006.201.22:55:49.18#ibcon#flushed, iclass 6, count 0 2006.201.22:55:49.18#ibcon#about to write, iclass 6, count 0 2006.201.22:55:49.18#ibcon#wrote, iclass 6, count 0 2006.201.22:55:49.18#ibcon#about to read 3, iclass 6, count 0 2006.201.22:55:49.20#ibcon#read 3, iclass 6, count 0 2006.201.22:55:49.20#ibcon#about to read 4, iclass 6, count 0 2006.201.22:55:49.20#ibcon#read 4, iclass 6, count 0 2006.201.22:55:49.20#ibcon#about to read 5, iclass 6, count 0 2006.201.22:55:49.20#ibcon#read 5, iclass 6, count 0 2006.201.22:55:49.20#ibcon#about to read 6, iclass 6, count 0 2006.201.22:55:49.20#ibcon#read 6, iclass 6, count 0 2006.201.22:55:49.20#ibcon#end of sib2, iclass 6, count 0 2006.201.22:55:49.20#ibcon#*mode == 0, iclass 6, count 0 2006.201.22:55:49.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.22:55:49.20#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.22:55:49.20#ibcon#*before write, iclass 6, count 0 2006.201.22:55:49.20#ibcon#enter sib2, iclass 6, count 0 2006.201.22:55:49.20#ibcon#flushed, iclass 6, count 0 2006.201.22:55:49.20#ibcon#about to write, iclass 6, count 0 2006.201.22:55:49.20#ibcon#wrote, iclass 6, count 0 2006.201.22:55:49.20#ibcon#about to read 3, iclass 6, count 0 2006.201.22:55:49.24#ibcon#read 3, iclass 6, count 0 2006.201.22:55:49.24#ibcon#about to read 4, iclass 6, count 0 2006.201.22:55:49.24#ibcon#read 4, iclass 6, count 0 2006.201.22:55:49.24#ibcon#about to read 5, iclass 6, count 0 2006.201.22:55:49.24#ibcon#read 5, iclass 6, count 0 2006.201.22:55:49.24#ibcon#about to read 6, iclass 6, count 0 2006.201.22:55:49.24#ibcon#read 6, iclass 6, count 0 2006.201.22:55:49.24#ibcon#end of sib2, iclass 6, count 0 2006.201.22:55:49.24#ibcon#*after write, iclass 6, count 0 2006.201.22:55:49.24#ibcon#*before return 0, iclass 6, count 0 2006.201.22:55:49.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:49.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.22:55:49.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.22:55:49.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.22:55:49.24$vck44/vb=3,4 2006.201.22:55:49.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.22:55:49.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.22:55:49.24#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:49.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:49.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:49.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:49.30#ibcon#enter wrdev, iclass 10, count 2 2006.201.22:55:49.30#ibcon#first serial, iclass 10, count 2 2006.201.22:55:49.30#ibcon#enter sib2, iclass 10, count 2 2006.201.22:55:49.30#ibcon#flushed, iclass 10, count 2 2006.201.22:55:49.30#ibcon#about to write, iclass 10, count 2 2006.201.22:55:49.30#ibcon#wrote, iclass 10, count 2 2006.201.22:55:49.30#ibcon#about to read 3, iclass 10, count 2 2006.201.22:55:49.32#ibcon#read 3, iclass 10, count 2 2006.201.22:55:49.32#ibcon#about to read 4, iclass 10, count 2 2006.201.22:55:49.32#ibcon#read 4, iclass 10, count 2 2006.201.22:55:49.32#ibcon#about to read 5, iclass 10, count 2 2006.201.22:55:49.32#ibcon#read 5, iclass 10, count 2 2006.201.22:55:49.32#ibcon#about to read 6, iclass 10, count 2 2006.201.22:55:49.32#ibcon#read 6, iclass 10, count 2 2006.201.22:55:49.32#ibcon#end of sib2, iclass 10, count 2 2006.201.22:55:49.32#ibcon#*mode == 0, iclass 10, count 2 2006.201.22:55:49.32#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.22:55:49.32#ibcon#[27=AT03-04\r\n] 2006.201.22:55:49.32#ibcon#*before write, iclass 10, count 2 2006.201.22:55:49.32#ibcon#enter sib2, iclass 10, count 2 2006.201.22:55:49.32#ibcon#flushed, iclass 10, count 2 2006.201.22:55:49.32#ibcon#about to write, iclass 10, count 2 2006.201.22:55:49.32#ibcon#wrote, iclass 10, count 2 2006.201.22:55:49.32#ibcon#about to read 3, iclass 10, count 2 2006.201.22:55:49.35#ibcon#read 3, iclass 10, count 2 2006.201.22:55:49.35#ibcon#about to read 4, iclass 10, count 2 2006.201.22:55:49.35#ibcon#read 4, iclass 10, count 2 2006.201.22:55:49.35#ibcon#about to read 5, iclass 10, count 2 2006.201.22:55:49.35#ibcon#read 5, iclass 10, count 2 2006.201.22:55:49.35#ibcon#about to read 6, iclass 10, count 2 2006.201.22:55:49.35#ibcon#read 6, iclass 10, count 2 2006.201.22:55:49.35#ibcon#end of sib2, iclass 10, count 2 2006.201.22:55:49.35#ibcon#*after write, iclass 10, count 2 2006.201.22:55:49.35#ibcon#*before return 0, iclass 10, count 2 2006.201.22:55:49.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:49.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.22:55:49.35#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.22:55:49.35#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:49.35#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:49.47#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:49.47#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:49.47#ibcon#enter wrdev, iclass 10, count 0 2006.201.22:55:49.47#ibcon#first serial, iclass 10, count 0 2006.201.22:55:49.47#ibcon#enter sib2, iclass 10, count 0 2006.201.22:55:49.47#ibcon#flushed, iclass 10, count 0 2006.201.22:55:49.47#ibcon#about to write, iclass 10, count 0 2006.201.22:55:49.47#ibcon#wrote, iclass 10, count 0 2006.201.22:55:49.47#ibcon#about to read 3, iclass 10, count 0 2006.201.22:55:49.49#ibcon#read 3, iclass 10, count 0 2006.201.22:55:49.49#ibcon#about to read 4, iclass 10, count 0 2006.201.22:55:49.49#ibcon#read 4, iclass 10, count 0 2006.201.22:55:49.49#ibcon#about to read 5, iclass 10, count 0 2006.201.22:55:49.49#ibcon#read 5, iclass 10, count 0 2006.201.22:55:49.49#ibcon#about to read 6, iclass 10, count 0 2006.201.22:55:49.49#ibcon#read 6, iclass 10, count 0 2006.201.22:55:49.49#ibcon#end of sib2, iclass 10, count 0 2006.201.22:55:49.49#ibcon#*mode == 0, iclass 10, count 0 2006.201.22:55:49.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.22:55:49.49#ibcon#[27=USB\r\n] 2006.201.22:55:49.49#ibcon#*before write, iclass 10, count 0 2006.201.22:55:49.49#ibcon#enter sib2, iclass 10, count 0 2006.201.22:55:49.49#ibcon#flushed, iclass 10, count 0 2006.201.22:55:49.49#ibcon#about to write, iclass 10, count 0 2006.201.22:55:49.49#ibcon#wrote, iclass 10, count 0 2006.201.22:55:49.49#ibcon#about to read 3, iclass 10, count 0 2006.201.22:55:49.52#ibcon#read 3, iclass 10, count 0 2006.201.22:55:49.52#ibcon#about to read 4, iclass 10, count 0 2006.201.22:55:49.52#ibcon#read 4, iclass 10, count 0 2006.201.22:55:49.52#ibcon#about to read 5, iclass 10, count 0 2006.201.22:55:49.52#ibcon#read 5, iclass 10, count 0 2006.201.22:55:49.52#ibcon#about to read 6, iclass 10, count 0 2006.201.22:55:49.52#ibcon#read 6, iclass 10, count 0 2006.201.22:55:49.52#ibcon#end of sib2, iclass 10, count 0 2006.201.22:55:49.52#ibcon#*after write, iclass 10, count 0 2006.201.22:55:49.52#ibcon#*before return 0, iclass 10, count 0 2006.201.22:55:49.52#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:49.52#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.22:55:49.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.22:55:49.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.22:55:49.52$vck44/vblo=4,679.99 2006.201.22:55:49.52#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.22:55:49.52#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.22:55:49.52#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:49.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:49.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:49.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:49.52#ibcon#enter wrdev, iclass 12, count 0 2006.201.22:55:49.52#ibcon#first serial, iclass 12, count 0 2006.201.22:55:49.52#ibcon#enter sib2, iclass 12, count 0 2006.201.22:55:49.52#ibcon#flushed, iclass 12, count 0 2006.201.22:55:49.52#ibcon#about to write, iclass 12, count 0 2006.201.22:55:49.52#ibcon#wrote, iclass 12, count 0 2006.201.22:55:49.52#ibcon#about to read 3, iclass 12, count 0 2006.201.22:55:49.54#ibcon#read 3, iclass 12, count 0 2006.201.22:55:49.54#ibcon#about to read 4, iclass 12, count 0 2006.201.22:55:49.54#ibcon#read 4, iclass 12, count 0 2006.201.22:55:49.54#ibcon#about to read 5, iclass 12, count 0 2006.201.22:55:49.54#ibcon#read 5, iclass 12, count 0 2006.201.22:55:49.54#ibcon#about to read 6, iclass 12, count 0 2006.201.22:55:49.54#ibcon#read 6, iclass 12, count 0 2006.201.22:55:49.54#ibcon#end of sib2, iclass 12, count 0 2006.201.22:55:49.54#ibcon#*mode == 0, iclass 12, count 0 2006.201.22:55:49.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.22:55:49.54#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.22:55:49.54#ibcon#*before write, iclass 12, count 0 2006.201.22:55:49.54#ibcon#enter sib2, iclass 12, count 0 2006.201.22:55:49.54#ibcon#flushed, iclass 12, count 0 2006.201.22:55:49.54#ibcon#about to write, iclass 12, count 0 2006.201.22:55:49.54#ibcon#wrote, iclass 12, count 0 2006.201.22:55:49.54#ibcon#about to read 3, iclass 12, count 0 2006.201.22:55:49.59#ibcon#read 3, iclass 12, count 0 2006.201.22:55:49.59#ibcon#about to read 4, iclass 12, count 0 2006.201.22:55:49.59#ibcon#read 4, iclass 12, count 0 2006.201.22:55:49.59#ibcon#about to read 5, iclass 12, count 0 2006.201.22:55:49.59#ibcon#read 5, iclass 12, count 0 2006.201.22:55:49.59#ibcon#about to read 6, iclass 12, count 0 2006.201.22:55:49.59#ibcon#read 6, iclass 12, count 0 2006.201.22:55:49.59#ibcon#end of sib2, iclass 12, count 0 2006.201.22:55:49.59#ibcon#*after write, iclass 12, count 0 2006.201.22:55:49.59#ibcon#*before return 0, iclass 12, count 0 2006.201.22:55:49.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:49.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.22:55:49.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.22:55:49.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.22:55:49.59$vck44/vb=4,5 2006.201.22:55:49.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.22:55:49.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.22:55:49.59#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:49.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:49.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:49.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:49.64#ibcon#enter wrdev, iclass 14, count 2 2006.201.22:55:49.64#ibcon#first serial, iclass 14, count 2 2006.201.22:55:49.64#ibcon#enter sib2, iclass 14, count 2 2006.201.22:55:49.64#ibcon#flushed, iclass 14, count 2 2006.201.22:55:49.64#ibcon#about to write, iclass 14, count 2 2006.201.22:55:49.64#ibcon#wrote, iclass 14, count 2 2006.201.22:55:49.64#ibcon#about to read 3, iclass 14, count 2 2006.201.22:55:49.66#ibcon#read 3, iclass 14, count 2 2006.201.22:55:49.66#ibcon#about to read 4, iclass 14, count 2 2006.201.22:55:49.66#ibcon#read 4, iclass 14, count 2 2006.201.22:55:49.66#ibcon#about to read 5, iclass 14, count 2 2006.201.22:55:49.66#ibcon#read 5, iclass 14, count 2 2006.201.22:55:49.66#ibcon#about to read 6, iclass 14, count 2 2006.201.22:55:49.66#ibcon#read 6, iclass 14, count 2 2006.201.22:55:49.66#ibcon#end of sib2, iclass 14, count 2 2006.201.22:55:49.66#ibcon#*mode == 0, iclass 14, count 2 2006.201.22:55:49.66#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.22:55:49.66#ibcon#[27=AT04-05\r\n] 2006.201.22:55:49.66#ibcon#*before write, iclass 14, count 2 2006.201.22:55:49.66#ibcon#enter sib2, iclass 14, count 2 2006.201.22:55:49.66#ibcon#flushed, iclass 14, count 2 2006.201.22:55:49.66#ibcon#about to write, iclass 14, count 2 2006.201.22:55:49.66#ibcon#wrote, iclass 14, count 2 2006.201.22:55:49.66#ibcon#about to read 3, iclass 14, count 2 2006.201.22:55:49.69#ibcon#read 3, iclass 14, count 2 2006.201.22:55:49.69#ibcon#about to read 4, iclass 14, count 2 2006.201.22:55:49.69#ibcon#read 4, iclass 14, count 2 2006.201.22:55:49.69#ibcon#about to read 5, iclass 14, count 2 2006.201.22:55:49.69#ibcon#read 5, iclass 14, count 2 2006.201.22:55:49.69#ibcon#about to read 6, iclass 14, count 2 2006.201.22:55:49.69#ibcon#read 6, iclass 14, count 2 2006.201.22:55:49.69#ibcon#end of sib2, iclass 14, count 2 2006.201.22:55:49.69#ibcon#*after write, iclass 14, count 2 2006.201.22:55:49.69#ibcon#*before return 0, iclass 14, count 2 2006.201.22:55:49.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:49.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.22:55:49.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.22:55:49.69#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:49.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:49.81#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:49.81#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:49.81#ibcon#enter wrdev, iclass 14, count 0 2006.201.22:55:49.81#ibcon#first serial, iclass 14, count 0 2006.201.22:55:49.81#ibcon#enter sib2, iclass 14, count 0 2006.201.22:55:49.81#ibcon#flushed, iclass 14, count 0 2006.201.22:55:49.81#ibcon#about to write, iclass 14, count 0 2006.201.22:55:49.81#ibcon#wrote, iclass 14, count 0 2006.201.22:55:49.81#ibcon#about to read 3, iclass 14, count 0 2006.201.22:55:49.83#ibcon#read 3, iclass 14, count 0 2006.201.22:55:49.83#ibcon#about to read 4, iclass 14, count 0 2006.201.22:55:49.83#ibcon#read 4, iclass 14, count 0 2006.201.22:55:49.83#ibcon#about to read 5, iclass 14, count 0 2006.201.22:55:49.83#ibcon#read 5, iclass 14, count 0 2006.201.22:55:49.83#ibcon#about to read 6, iclass 14, count 0 2006.201.22:55:49.83#ibcon#read 6, iclass 14, count 0 2006.201.22:55:49.83#ibcon#end of sib2, iclass 14, count 0 2006.201.22:55:49.83#ibcon#*mode == 0, iclass 14, count 0 2006.201.22:55:49.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.22:55:49.83#ibcon#[27=USB\r\n] 2006.201.22:55:49.83#ibcon#*before write, iclass 14, count 0 2006.201.22:55:49.83#ibcon#enter sib2, iclass 14, count 0 2006.201.22:55:49.83#ibcon#flushed, iclass 14, count 0 2006.201.22:55:49.83#ibcon#about to write, iclass 14, count 0 2006.201.22:55:49.83#ibcon#wrote, iclass 14, count 0 2006.201.22:55:49.83#ibcon#about to read 3, iclass 14, count 0 2006.201.22:55:49.86#ibcon#read 3, iclass 14, count 0 2006.201.22:55:49.86#ibcon#about to read 4, iclass 14, count 0 2006.201.22:55:49.86#ibcon#read 4, iclass 14, count 0 2006.201.22:55:49.86#ibcon#about to read 5, iclass 14, count 0 2006.201.22:55:49.86#ibcon#read 5, iclass 14, count 0 2006.201.22:55:49.86#ibcon#about to read 6, iclass 14, count 0 2006.201.22:55:49.86#ibcon#read 6, iclass 14, count 0 2006.201.22:55:49.86#ibcon#end of sib2, iclass 14, count 0 2006.201.22:55:49.86#ibcon#*after write, iclass 14, count 0 2006.201.22:55:49.86#ibcon#*before return 0, iclass 14, count 0 2006.201.22:55:49.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:49.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.22:55:49.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.22:55:49.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.22:55:49.86$vck44/vblo=5,709.99 2006.201.22:55:49.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.22:55:49.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.22:55:49.86#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:49.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:49.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:49.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:49.86#ibcon#enter wrdev, iclass 16, count 0 2006.201.22:55:49.86#ibcon#first serial, iclass 16, count 0 2006.201.22:55:49.86#ibcon#enter sib2, iclass 16, count 0 2006.201.22:55:49.86#ibcon#flushed, iclass 16, count 0 2006.201.22:55:49.86#ibcon#about to write, iclass 16, count 0 2006.201.22:55:49.86#ibcon#wrote, iclass 16, count 0 2006.201.22:55:49.86#ibcon#about to read 3, iclass 16, count 0 2006.201.22:55:49.88#ibcon#read 3, iclass 16, count 0 2006.201.22:55:49.88#ibcon#about to read 4, iclass 16, count 0 2006.201.22:55:49.88#ibcon#read 4, iclass 16, count 0 2006.201.22:55:49.88#ibcon#about to read 5, iclass 16, count 0 2006.201.22:55:49.88#ibcon#read 5, iclass 16, count 0 2006.201.22:55:49.88#ibcon#about to read 6, iclass 16, count 0 2006.201.22:55:49.88#ibcon#read 6, iclass 16, count 0 2006.201.22:55:49.88#ibcon#end of sib2, iclass 16, count 0 2006.201.22:55:49.88#ibcon#*mode == 0, iclass 16, count 0 2006.201.22:55:49.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.22:55:49.88#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.22:55:49.88#ibcon#*before write, iclass 16, count 0 2006.201.22:55:49.88#ibcon#enter sib2, iclass 16, count 0 2006.201.22:55:49.88#ibcon#flushed, iclass 16, count 0 2006.201.22:55:49.88#ibcon#about to write, iclass 16, count 0 2006.201.22:55:49.88#ibcon#wrote, iclass 16, count 0 2006.201.22:55:49.88#ibcon#about to read 3, iclass 16, count 0 2006.201.22:55:49.92#ibcon#read 3, iclass 16, count 0 2006.201.22:55:49.92#ibcon#about to read 4, iclass 16, count 0 2006.201.22:55:49.92#ibcon#read 4, iclass 16, count 0 2006.201.22:55:49.92#ibcon#about to read 5, iclass 16, count 0 2006.201.22:55:49.92#ibcon#read 5, iclass 16, count 0 2006.201.22:55:49.92#ibcon#about to read 6, iclass 16, count 0 2006.201.22:55:49.92#ibcon#read 6, iclass 16, count 0 2006.201.22:55:49.92#ibcon#end of sib2, iclass 16, count 0 2006.201.22:55:49.92#ibcon#*after write, iclass 16, count 0 2006.201.22:55:49.92#ibcon#*before return 0, iclass 16, count 0 2006.201.22:55:49.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:49.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.22:55:49.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.22:55:49.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.22:55:49.92$vck44/vb=5,4 2006.201.22:55:49.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.22:55:49.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.22:55:49.92#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:49.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:49.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:49.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:49.98#ibcon#enter wrdev, iclass 18, count 2 2006.201.22:55:49.98#ibcon#first serial, iclass 18, count 2 2006.201.22:55:49.98#ibcon#enter sib2, iclass 18, count 2 2006.201.22:55:49.98#ibcon#flushed, iclass 18, count 2 2006.201.22:55:49.98#ibcon#about to write, iclass 18, count 2 2006.201.22:55:49.98#ibcon#wrote, iclass 18, count 2 2006.201.22:55:49.98#ibcon#about to read 3, iclass 18, count 2 2006.201.22:55:50.00#ibcon#read 3, iclass 18, count 2 2006.201.22:55:50.00#ibcon#about to read 4, iclass 18, count 2 2006.201.22:55:50.00#ibcon#read 4, iclass 18, count 2 2006.201.22:55:50.00#ibcon#about to read 5, iclass 18, count 2 2006.201.22:55:50.00#ibcon#read 5, iclass 18, count 2 2006.201.22:55:50.00#ibcon#about to read 6, iclass 18, count 2 2006.201.22:55:50.00#ibcon#read 6, iclass 18, count 2 2006.201.22:55:50.00#ibcon#end of sib2, iclass 18, count 2 2006.201.22:55:50.00#ibcon#*mode == 0, iclass 18, count 2 2006.201.22:55:50.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.22:55:50.00#ibcon#[27=AT05-04\r\n] 2006.201.22:55:50.00#ibcon#*before write, iclass 18, count 2 2006.201.22:55:50.00#ibcon#enter sib2, iclass 18, count 2 2006.201.22:55:50.00#ibcon#flushed, iclass 18, count 2 2006.201.22:55:50.00#ibcon#about to write, iclass 18, count 2 2006.201.22:55:50.00#ibcon#wrote, iclass 18, count 2 2006.201.22:55:50.00#ibcon#about to read 3, iclass 18, count 2 2006.201.22:55:50.03#ibcon#read 3, iclass 18, count 2 2006.201.22:55:50.03#ibcon#about to read 4, iclass 18, count 2 2006.201.22:55:50.03#ibcon#read 4, iclass 18, count 2 2006.201.22:55:50.03#ibcon#about to read 5, iclass 18, count 2 2006.201.22:55:50.03#ibcon#read 5, iclass 18, count 2 2006.201.22:55:50.03#ibcon#about to read 6, iclass 18, count 2 2006.201.22:55:50.03#ibcon#read 6, iclass 18, count 2 2006.201.22:55:50.03#ibcon#end of sib2, iclass 18, count 2 2006.201.22:55:50.03#ibcon#*after write, iclass 18, count 2 2006.201.22:55:50.03#ibcon#*before return 0, iclass 18, count 2 2006.201.22:55:50.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:50.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.22:55:50.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.22:55:50.03#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:50.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:50.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:50.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:50.15#ibcon#enter wrdev, iclass 18, count 0 2006.201.22:55:50.15#ibcon#first serial, iclass 18, count 0 2006.201.22:55:50.15#ibcon#enter sib2, iclass 18, count 0 2006.201.22:55:50.15#ibcon#flushed, iclass 18, count 0 2006.201.22:55:50.15#ibcon#about to write, iclass 18, count 0 2006.201.22:55:50.15#ibcon#wrote, iclass 18, count 0 2006.201.22:55:50.15#ibcon#about to read 3, iclass 18, count 0 2006.201.22:55:50.17#ibcon#read 3, iclass 18, count 0 2006.201.22:55:50.17#ibcon#about to read 4, iclass 18, count 0 2006.201.22:55:50.17#ibcon#read 4, iclass 18, count 0 2006.201.22:55:50.17#ibcon#about to read 5, iclass 18, count 0 2006.201.22:55:50.17#ibcon#read 5, iclass 18, count 0 2006.201.22:55:50.17#ibcon#about to read 6, iclass 18, count 0 2006.201.22:55:50.17#ibcon#read 6, iclass 18, count 0 2006.201.22:55:50.17#ibcon#end of sib2, iclass 18, count 0 2006.201.22:55:50.17#ibcon#*mode == 0, iclass 18, count 0 2006.201.22:55:50.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.22:55:50.17#ibcon#[27=USB\r\n] 2006.201.22:55:50.17#ibcon#*before write, iclass 18, count 0 2006.201.22:55:50.17#ibcon#enter sib2, iclass 18, count 0 2006.201.22:55:50.17#ibcon#flushed, iclass 18, count 0 2006.201.22:55:50.17#ibcon#about to write, iclass 18, count 0 2006.201.22:55:50.17#ibcon#wrote, iclass 18, count 0 2006.201.22:55:50.17#ibcon#about to read 3, iclass 18, count 0 2006.201.22:55:50.20#ibcon#read 3, iclass 18, count 0 2006.201.22:55:50.20#ibcon#about to read 4, iclass 18, count 0 2006.201.22:55:50.20#ibcon#read 4, iclass 18, count 0 2006.201.22:55:50.20#ibcon#about to read 5, iclass 18, count 0 2006.201.22:55:50.20#ibcon#read 5, iclass 18, count 0 2006.201.22:55:50.20#ibcon#about to read 6, iclass 18, count 0 2006.201.22:55:50.20#ibcon#read 6, iclass 18, count 0 2006.201.22:55:50.20#ibcon#end of sib2, iclass 18, count 0 2006.201.22:55:50.20#ibcon#*after write, iclass 18, count 0 2006.201.22:55:50.20#ibcon#*before return 0, iclass 18, count 0 2006.201.22:55:50.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:50.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.22:55:50.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.22:55:50.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.22:55:50.20$vck44/vblo=6,719.99 2006.201.22:55:50.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.22:55:50.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.22:55:50.20#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:50.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:50.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:50.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:50.20#ibcon#enter wrdev, iclass 20, count 0 2006.201.22:55:50.20#ibcon#first serial, iclass 20, count 0 2006.201.22:55:50.20#ibcon#enter sib2, iclass 20, count 0 2006.201.22:55:50.20#ibcon#flushed, iclass 20, count 0 2006.201.22:55:50.20#ibcon#about to write, iclass 20, count 0 2006.201.22:55:50.20#ibcon#wrote, iclass 20, count 0 2006.201.22:55:50.20#ibcon#about to read 3, iclass 20, count 0 2006.201.22:55:50.22#ibcon#read 3, iclass 20, count 0 2006.201.22:55:50.22#ibcon#about to read 4, iclass 20, count 0 2006.201.22:55:50.22#ibcon#read 4, iclass 20, count 0 2006.201.22:55:50.22#ibcon#about to read 5, iclass 20, count 0 2006.201.22:55:50.22#ibcon#read 5, iclass 20, count 0 2006.201.22:55:50.22#ibcon#about to read 6, iclass 20, count 0 2006.201.22:55:50.22#ibcon#read 6, iclass 20, count 0 2006.201.22:55:50.22#ibcon#end of sib2, iclass 20, count 0 2006.201.22:55:50.22#ibcon#*mode == 0, iclass 20, count 0 2006.201.22:55:50.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.22:55:50.22#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.22:55:50.22#ibcon#*before write, iclass 20, count 0 2006.201.22:55:50.22#ibcon#enter sib2, iclass 20, count 0 2006.201.22:55:50.22#ibcon#flushed, iclass 20, count 0 2006.201.22:55:50.22#ibcon#about to write, iclass 20, count 0 2006.201.22:55:50.22#ibcon#wrote, iclass 20, count 0 2006.201.22:55:50.22#ibcon#about to read 3, iclass 20, count 0 2006.201.22:55:50.26#ibcon#read 3, iclass 20, count 0 2006.201.22:55:50.26#ibcon#about to read 4, iclass 20, count 0 2006.201.22:55:50.26#ibcon#read 4, iclass 20, count 0 2006.201.22:55:50.26#ibcon#about to read 5, iclass 20, count 0 2006.201.22:55:50.26#ibcon#read 5, iclass 20, count 0 2006.201.22:55:50.26#ibcon#about to read 6, iclass 20, count 0 2006.201.22:55:50.26#ibcon#read 6, iclass 20, count 0 2006.201.22:55:50.26#ibcon#end of sib2, iclass 20, count 0 2006.201.22:55:50.26#ibcon#*after write, iclass 20, count 0 2006.201.22:55:50.26#ibcon#*before return 0, iclass 20, count 0 2006.201.22:55:50.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:50.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.22:55:50.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.22:55:50.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.22:55:50.26$vck44/vb=6,4 2006.201.22:55:50.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.22:55:50.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.22:55:50.26#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:50.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:50.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:50.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:50.32#ibcon#enter wrdev, iclass 22, count 2 2006.201.22:55:50.32#ibcon#first serial, iclass 22, count 2 2006.201.22:55:50.32#ibcon#enter sib2, iclass 22, count 2 2006.201.22:55:50.32#ibcon#flushed, iclass 22, count 2 2006.201.22:55:50.32#ibcon#about to write, iclass 22, count 2 2006.201.22:55:50.32#ibcon#wrote, iclass 22, count 2 2006.201.22:55:50.32#ibcon#about to read 3, iclass 22, count 2 2006.201.22:55:50.34#ibcon#read 3, iclass 22, count 2 2006.201.22:55:50.34#ibcon#about to read 4, iclass 22, count 2 2006.201.22:55:50.34#ibcon#read 4, iclass 22, count 2 2006.201.22:55:50.34#ibcon#about to read 5, iclass 22, count 2 2006.201.22:55:50.34#ibcon#read 5, iclass 22, count 2 2006.201.22:55:50.34#ibcon#about to read 6, iclass 22, count 2 2006.201.22:55:50.34#ibcon#read 6, iclass 22, count 2 2006.201.22:55:50.34#ibcon#end of sib2, iclass 22, count 2 2006.201.22:55:50.34#ibcon#*mode == 0, iclass 22, count 2 2006.201.22:55:50.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.22:55:50.34#ibcon#[27=AT06-04\r\n] 2006.201.22:55:50.34#ibcon#*before write, iclass 22, count 2 2006.201.22:55:50.34#ibcon#enter sib2, iclass 22, count 2 2006.201.22:55:50.34#ibcon#flushed, iclass 22, count 2 2006.201.22:55:50.34#ibcon#about to write, iclass 22, count 2 2006.201.22:55:50.34#ibcon#wrote, iclass 22, count 2 2006.201.22:55:50.34#ibcon#about to read 3, iclass 22, count 2 2006.201.22:55:50.37#ibcon#read 3, iclass 22, count 2 2006.201.22:55:50.37#ibcon#about to read 4, iclass 22, count 2 2006.201.22:55:50.37#ibcon#read 4, iclass 22, count 2 2006.201.22:55:50.37#ibcon#about to read 5, iclass 22, count 2 2006.201.22:55:50.37#ibcon#read 5, iclass 22, count 2 2006.201.22:55:50.37#ibcon#about to read 6, iclass 22, count 2 2006.201.22:55:50.37#ibcon#read 6, iclass 22, count 2 2006.201.22:55:50.37#ibcon#end of sib2, iclass 22, count 2 2006.201.22:55:50.37#ibcon#*after write, iclass 22, count 2 2006.201.22:55:50.37#ibcon#*before return 0, iclass 22, count 2 2006.201.22:55:50.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:50.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.22:55:50.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.22:55:50.37#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:50.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:50.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:50.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:50.49#ibcon#enter wrdev, iclass 22, count 0 2006.201.22:55:50.49#ibcon#first serial, iclass 22, count 0 2006.201.22:55:50.49#ibcon#enter sib2, iclass 22, count 0 2006.201.22:55:50.49#ibcon#flushed, iclass 22, count 0 2006.201.22:55:50.49#ibcon#about to write, iclass 22, count 0 2006.201.22:55:50.49#ibcon#wrote, iclass 22, count 0 2006.201.22:55:50.49#ibcon#about to read 3, iclass 22, count 0 2006.201.22:55:50.51#ibcon#read 3, iclass 22, count 0 2006.201.22:55:50.51#ibcon#about to read 4, iclass 22, count 0 2006.201.22:55:50.51#ibcon#read 4, iclass 22, count 0 2006.201.22:55:50.51#ibcon#about to read 5, iclass 22, count 0 2006.201.22:55:50.51#ibcon#read 5, iclass 22, count 0 2006.201.22:55:50.51#ibcon#about to read 6, iclass 22, count 0 2006.201.22:55:50.51#ibcon#read 6, iclass 22, count 0 2006.201.22:55:50.51#ibcon#end of sib2, iclass 22, count 0 2006.201.22:55:50.51#ibcon#*mode == 0, iclass 22, count 0 2006.201.22:55:50.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.22:55:50.51#ibcon#[27=USB\r\n] 2006.201.22:55:50.51#ibcon#*before write, iclass 22, count 0 2006.201.22:55:50.51#ibcon#enter sib2, iclass 22, count 0 2006.201.22:55:50.51#ibcon#flushed, iclass 22, count 0 2006.201.22:55:50.51#ibcon#about to write, iclass 22, count 0 2006.201.22:55:50.51#ibcon#wrote, iclass 22, count 0 2006.201.22:55:50.51#ibcon#about to read 3, iclass 22, count 0 2006.201.22:55:50.54#ibcon#read 3, iclass 22, count 0 2006.201.22:55:50.54#ibcon#about to read 4, iclass 22, count 0 2006.201.22:55:50.54#ibcon#read 4, iclass 22, count 0 2006.201.22:55:50.54#ibcon#about to read 5, iclass 22, count 0 2006.201.22:55:50.54#ibcon#read 5, iclass 22, count 0 2006.201.22:55:50.54#ibcon#about to read 6, iclass 22, count 0 2006.201.22:55:50.54#ibcon#read 6, iclass 22, count 0 2006.201.22:55:50.54#ibcon#end of sib2, iclass 22, count 0 2006.201.22:55:50.54#ibcon#*after write, iclass 22, count 0 2006.201.22:55:50.54#ibcon#*before return 0, iclass 22, count 0 2006.201.22:55:50.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:50.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.22:55:50.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.22:55:50.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.22:55:50.54$vck44/vblo=7,734.99 2006.201.22:55:50.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.22:55:50.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.22:55:50.54#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:50.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:50.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:50.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:50.54#ibcon#enter wrdev, iclass 24, count 0 2006.201.22:55:50.54#ibcon#first serial, iclass 24, count 0 2006.201.22:55:50.54#ibcon#enter sib2, iclass 24, count 0 2006.201.22:55:50.54#ibcon#flushed, iclass 24, count 0 2006.201.22:55:50.54#ibcon#about to write, iclass 24, count 0 2006.201.22:55:50.54#ibcon#wrote, iclass 24, count 0 2006.201.22:55:50.54#ibcon#about to read 3, iclass 24, count 0 2006.201.22:55:50.56#ibcon#read 3, iclass 24, count 0 2006.201.22:55:50.56#ibcon#about to read 4, iclass 24, count 0 2006.201.22:55:50.56#ibcon#read 4, iclass 24, count 0 2006.201.22:55:50.56#ibcon#about to read 5, iclass 24, count 0 2006.201.22:55:50.56#ibcon#read 5, iclass 24, count 0 2006.201.22:55:50.56#ibcon#about to read 6, iclass 24, count 0 2006.201.22:55:50.56#ibcon#read 6, iclass 24, count 0 2006.201.22:55:50.56#ibcon#end of sib2, iclass 24, count 0 2006.201.22:55:50.56#ibcon#*mode == 0, iclass 24, count 0 2006.201.22:55:50.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.22:55:50.56#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.22:55:50.56#ibcon#*before write, iclass 24, count 0 2006.201.22:55:50.56#ibcon#enter sib2, iclass 24, count 0 2006.201.22:55:50.56#ibcon#flushed, iclass 24, count 0 2006.201.22:55:50.56#ibcon#about to write, iclass 24, count 0 2006.201.22:55:50.56#ibcon#wrote, iclass 24, count 0 2006.201.22:55:50.56#ibcon#about to read 3, iclass 24, count 0 2006.201.22:55:50.60#ibcon#read 3, iclass 24, count 0 2006.201.22:55:50.60#ibcon#about to read 4, iclass 24, count 0 2006.201.22:55:50.60#ibcon#read 4, iclass 24, count 0 2006.201.22:55:50.60#ibcon#about to read 5, iclass 24, count 0 2006.201.22:55:50.60#ibcon#read 5, iclass 24, count 0 2006.201.22:55:50.60#ibcon#about to read 6, iclass 24, count 0 2006.201.22:55:50.60#ibcon#read 6, iclass 24, count 0 2006.201.22:55:50.60#ibcon#end of sib2, iclass 24, count 0 2006.201.22:55:50.60#ibcon#*after write, iclass 24, count 0 2006.201.22:55:50.60#ibcon#*before return 0, iclass 24, count 0 2006.201.22:55:50.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:50.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.22:55:50.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.22:55:50.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.22:55:50.60$vck44/vb=7,4 2006.201.22:55:50.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.22:55:50.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.22:55:50.60#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:50.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:50.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:50.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:50.66#ibcon#enter wrdev, iclass 26, count 2 2006.201.22:55:50.66#ibcon#first serial, iclass 26, count 2 2006.201.22:55:50.66#ibcon#enter sib2, iclass 26, count 2 2006.201.22:55:50.66#ibcon#flushed, iclass 26, count 2 2006.201.22:55:50.66#ibcon#about to write, iclass 26, count 2 2006.201.22:55:50.66#ibcon#wrote, iclass 26, count 2 2006.201.22:55:50.66#ibcon#about to read 3, iclass 26, count 2 2006.201.22:55:50.68#ibcon#read 3, iclass 26, count 2 2006.201.22:55:50.68#ibcon#about to read 4, iclass 26, count 2 2006.201.22:55:50.68#ibcon#read 4, iclass 26, count 2 2006.201.22:55:50.68#ibcon#about to read 5, iclass 26, count 2 2006.201.22:55:50.68#ibcon#read 5, iclass 26, count 2 2006.201.22:55:50.68#ibcon#about to read 6, iclass 26, count 2 2006.201.22:55:50.68#ibcon#read 6, iclass 26, count 2 2006.201.22:55:50.68#ibcon#end of sib2, iclass 26, count 2 2006.201.22:55:50.68#ibcon#*mode == 0, iclass 26, count 2 2006.201.22:55:50.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.22:55:50.68#ibcon#[27=AT07-04\r\n] 2006.201.22:55:50.68#ibcon#*before write, iclass 26, count 2 2006.201.22:55:50.68#ibcon#enter sib2, iclass 26, count 2 2006.201.22:55:50.68#ibcon#flushed, iclass 26, count 2 2006.201.22:55:50.68#ibcon#about to write, iclass 26, count 2 2006.201.22:55:50.68#ibcon#wrote, iclass 26, count 2 2006.201.22:55:50.68#ibcon#about to read 3, iclass 26, count 2 2006.201.22:55:50.71#ibcon#read 3, iclass 26, count 2 2006.201.22:55:50.71#ibcon#about to read 4, iclass 26, count 2 2006.201.22:55:50.71#ibcon#read 4, iclass 26, count 2 2006.201.22:55:50.71#ibcon#about to read 5, iclass 26, count 2 2006.201.22:55:50.71#ibcon#read 5, iclass 26, count 2 2006.201.22:55:50.71#ibcon#about to read 6, iclass 26, count 2 2006.201.22:55:50.71#ibcon#read 6, iclass 26, count 2 2006.201.22:55:50.71#ibcon#end of sib2, iclass 26, count 2 2006.201.22:55:50.71#ibcon#*after write, iclass 26, count 2 2006.201.22:55:50.71#ibcon#*before return 0, iclass 26, count 2 2006.201.22:55:50.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:50.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.22:55:50.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.22:55:50.71#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:50.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:50.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:50.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:50.83#ibcon#enter wrdev, iclass 26, count 0 2006.201.22:55:50.83#ibcon#first serial, iclass 26, count 0 2006.201.22:55:50.83#ibcon#enter sib2, iclass 26, count 0 2006.201.22:55:50.83#ibcon#flushed, iclass 26, count 0 2006.201.22:55:50.83#ibcon#about to write, iclass 26, count 0 2006.201.22:55:50.83#ibcon#wrote, iclass 26, count 0 2006.201.22:55:50.83#ibcon#about to read 3, iclass 26, count 0 2006.201.22:55:50.85#ibcon#read 3, iclass 26, count 0 2006.201.22:55:50.85#ibcon#about to read 4, iclass 26, count 0 2006.201.22:55:50.85#ibcon#read 4, iclass 26, count 0 2006.201.22:55:50.85#ibcon#about to read 5, iclass 26, count 0 2006.201.22:55:50.85#ibcon#read 5, iclass 26, count 0 2006.201.22:55:50.85#ibcon#about to read 6, iclass 26, count 0 2006.201.22:55:50.85#ibcon#read 6, iclass 26, count 0 2006.201.22:55:50.85#ibcon#end of sib2, iclass 26, count 0 2006.201.22:55:50.85#ibcon#*mode == 0, iclass 26, count 0 2006.201.22:55:50.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.22:55:50.85#ibcon#[27=USB\r\n] 2006.201.22:55:50.85#ibcon#*before write, iclass 26, count 0 2006.201.22:55:50.85#ibcon#enter sib2, iclass 26, count 0 2006.201.22:55:50.85#ibcon#flushed, iclass 26, count 0 2006.201.22:55:50.85#ibcon#about to write, iclass 26, count 0 2006.201.22:55:50.85#ibcon#wrote, iclass 26, count 0 2006.201.22:55:50.85#ibcon#about to read 3, iclass 26, count 0 2006.201.22:55:50.88#ibcon#read 3, iclass 26, count 0 2006.201.22:55:50.88#ibcon#about to read 4, iclass 26, count 0 2006.201.22:55:50.88#ibcon#read 4, iclass 26, count 0 2006.201.22:55:50.88#ibcon#about to read 5, iclass 26, count 0 2006.201.22:55:50.88#ibcon#read 5, iclass 26, count 0 2006.201.22:55:50.88#ibcon#about to read 6, iclass 26, count 0 2006.201.22:55:50.88#ibcon#read 6, iclass 26, count 0 2006.201.22:55:50.88#ibcon#end of sib2, iclass 26, count 0 2006.201.22:55:50.88#ibcon#*after write, iclass 26, count 0 2006.201.22:55:50.88#ibcon#*before return 0, iclass 26, count 0 2006.201.22:55:50.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:50.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.22:55:50.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.22:55:50.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.22:55:50.88$vck44/vblo=8,744.99 2006.201.22:55:50.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.22:55:50.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.22:55:50.88#ibcon#ireg 17 cls_cnt 0 2006.201.22:55:50.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:50.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:50.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:50.88#ibcon#enter wrdev, iclass 28, count 0 2006.201.22:55:50.88#ibcon#first serial, iclass 28, count 0 2006.201.22:55:50.88#ibcon#enter sib2, iclass 28, count 0 2006.201.22:55:50.88#ibcon#flushed, iclass 28, count 0 2006.201.22:55:50.88#ibcon#about to write, iclass 28, count 0 2006.201.22:55:50.88#ibcon#wrote, iclass 28, count 0 2006.201.22:55:50.88#ibcon#about to read 3, iclass 28, count 0 2006.201.22:55:50.90#ibcon#read 3, iclass 28, count 0 2006.201.22:55:50.90#ibcon#about to read 4, iclass 28, count 0 2006.201.22:55:50.90#ibcon#read 4, iclass 28, count 0 2006.201.22:55:50.90#ibcon#about to read 5, iclass 28, count 0 2006.201.22:55:50.90#ibcon#read 5, iclass 28, count 0 2006.201.22:55:50.90#ibcon#about to read 6, iclass 28, count 0 2006.201.22:55:50.90#ibcon#read 6, iclass 28, count 0 2006.201.22:55:50.90#ibcon#end of sib2, iclass 28, count 0 2006.201.22:55:50.90#ibcon#*mode == 0, iclass 28, count 0 2006.201.22:55:50.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.22:55:50.90#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.22:55:50.90#ibcon#*before write, iclass 28, count 0 2006.201.22:55:50.90#ibcon#enter sib2, iclass 28, count 0 2006.201.22:55:50.90#ibcon#flushed, iclass 28, count 0 2006.201.22:55:50.90#ibcon#about to write, iclass 28, count 0 2006.201.22:55:50.90#ibcon#wrote, iclass 28, count 0 2006.201.22:55:50.90#ibcon#about to read 3, iclass 28, count 0 2006.201.22:55:50.95#ibcon#read 3, iclass 28, count 0 2006.201.22:55:50.95#ibcon#about to read 4, iclass 28, count 0 2006.201.22:55:50.95#ibcon#read 4, iclass 28, count 0 2006.201.22:55:50.95#ibcon#about to read 5, iclass 28, count 0 2006.201.22:55:50.95#ibcon#read 5, iclass 28, count 0 2006.201.22:55:50.95#ibcon#about to read 6, iclass 28, count 0 2006.201.22:55:50.95#ibcon#read 6, iclass 28, count 0 2006.201.22:55:50.95#ibcon#end of sib2, iclass 28, count 0 2006.201.22:55:50.95#ibcon#*after write, iclass 28, count 0 2006.201.22:55:50.95#ibcon#*before return 0, iclass 28, count 0 2006.201.22:55:50.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:50.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.22:55:50.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.22:55:50.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.22:55:50.95$vck44/vb=8,4 2006.201.22:55:50.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.22:55:50.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.22:55:50.95#ibcon#ireg 11 cls_cnt 2 2006.201.22:55:50.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:51.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:51.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:51.00#ibcon#enter wrdev, iclass 30, count 2 2006.201.22:55:51.00#ibcon#first serial, iclass 30, count 2 2006.201.22:55:51.00#ibcon#enter sib2, iclass 30, count 2 2006.201.22:55:51.00#ibcon#flushed, iclass 30, count 2 2006.201.22:55:51.00#ibcon#about to write, iclass 30, count 2 2006.201.22:55:51.00#ibcon#wrote, iclass 30, count 2 2006.201.22:55:51.00#ibcon#about to read 3, iclass 30, count 2 2006.201.22:55:51.02#ibcon#read 3, iclass 30, count 2 2006.201.22:55:51.02#ibcon#about to read 4, iclass 30, count 2 2006.201.22:55:51.02#ibcon#read 4, iclass 30, count 2 2006.201.22:55:51.02#ibcon#about to read 5, iclass 30, count 2 2006.201.22:55:51.02#ibcon#read 5, iclass 30, count 2 2006.201.22:55:51.02#ibcon#about to read 6, iclass 30, count 2 2006.201.22:55:51.02#ibcon#read 6, iclass 30, count 2 2006.201.22:55:51.02#ibcon#end of sib2, iclass 30, count 2 2006.201.22:55:51.02#ibcon#*mode == 0, iclass 30, count 2 2006.201.22:55:51.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.22:55:51.02#ibcon#[27=AT08-04\r\n] 2006.201.22:55:51.02#ibcon#*before write, iclass 30, count 2 2006.201.22:55:51.02#ibcon#enter sib2, iclass 30, count 2 2006.201.22:55:51.02#ibcon#flushed, iclass 30, count 2 2006.201.22:55:51.02#ibcon#about to write, iclass 30, count 2 2006.201.22:55:51.02#ibcon#wrote, iclass 30, count 2 2006.201.22:55:51.02#ibcon#about to read 3, iclass 30, count 2 2006.201.22:55:51.05#ibcon#read 3, iclass 30, count 2 2006.201.22:55:51.05#ibcon#about to read 4, iclass 30, count 2 2006.201.22:55:51.05#ibcon#read 4, iclass 30, count 2 2006.201.22:55:51.05#ibcon#about to read 5, iclass 30, count 2 2006.201.22:55:51.05#ibcon#read 5, iclass 30, count 2 2006.201.22:55:51.05#ibcon#about to read 6, iclass 30, count 2 2006.201.22:55:51.05#ibcon#read 6, iclass 30, count 2 2006.201.22:55:51.05#ibcon#end of sib2, iclass 30, count 2 2006.201.22:55:51.05#ibcon#*after write, iclass 30, count 2 2006.201.22:55:51.05#ibcon#*before return 0, iclass 30, count 2 2006.201.22:55:51.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:51.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.22:55:51.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.22:55:51.05#ibcon#ireg 7 cls_cnt 0 2006.201.22:55:51.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:51.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:51.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:51.17#ibcon#enter wrdev, iclass 30, count 0 2006.201.22:55:51.17#ibcon#first serial, iclass 30, count 0 2006.201.22:55:51.17#ibcon#enter sib2, iclass 30, count 0 2006.201.22:55:51.17#ibcon#flushed, iclass 30, count 0 2006.201.22:55:51.17#ibcon#about to write, iclass 30, count 0 2006.201.22:55:51.17#ibcon#wrote, iclass 30, count 0 2006.201.22:55:51.17#ibcon#about to read 3, iclass 30, count 0 2006.201.22:55:51.20#ibcon#read 3, iclass 30, count 0 2006.201.22:55:51.20#ibcon#about to read 4, iclass 30, count 0 2006.201.22:55:51.20#ibcon#read 4, iclass 30, count 0 2006.201.22:55:51.20#ibcon#about to read 5, iclass 30, count 0 2006.201.22:55:51.20#ibcon#read 5, iclass 30, count 0 2006.201.22:55:51.20#ibcon#about to read 6, iclass 30, count 0 2006.201.22:55:51.20#ibcon#read 6, iclass 30, count 0 2006.201.22:55:51.20#ibcon#end of sib2, iclass 30, count 0 2006.201.22:55:51.20#ibcon#*mode == 0, iclass 30, count 0 2006.201.22:55:51.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.22:55:51.20#ibcon#[27=USB\r\n] 2006.201.22:55:51.20#ibcon#*before write, iclass 30, count 0 2006.201.22:55:51.20#ibcon#enter sib2, iclass 30, count 0 2006.201.22:55:51.20#ibcon#flushed, iclass 30, count 0 2006.201.22:55:51.20#ibcon#about to write, iclass 30, count 0 2006.201.22:55:51.20#ibcon#wrote, iclass 30, count 0 2006.201.22:55:51.20#ibcon#about to read 3, iclass 30, count 0 2006.201.22:55:51.23#ibcon#read 3, iclass 30, count 0 2006.201.22:55:51.23#ibcon#about to read 4, iclass 30, count 0 2006.201.22:55:51.23#ibcon#read 4, iclass 30, count 0 2006.201.22:55:51.23#ibcon#about to read 5, iclass 30, count 0 2006.201.22:55:51.23#ibcon#read 5, iclass 30, count 0 2006.201.22:55:51.23#ibcon#about to read 6, iclass 30, count 0 2006.201.22:55:51.23#ibcon#read 6, iclass 30, count 0 2006.201.22:55:51.23#ibcon#end of sib2, iclass 30, count 0 2006.201.22:55:51.23#ibcon#*after write, iclass 30, count 0 2006.201.22:55:51.23#ibcon#*before return 0, iclass 30, count 0 2006.201.22:55:51.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:51.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.22:55:51.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.22:55:51.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.22:55:51.23$vck44/vabw=wide 2006.201.22:55:51.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.22:55:51.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.22:55:51.23#ibcon#ireg 8 cls_cnt 0 2006.201.22:55:51.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:51.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:51.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:51.23#ibcon#enter wrdev, iclass 32, count 0 2006.201.22:55:51.23#ibcon#first serial, iclass 32, count 0 2006.201.22:55:51.23#ibcon#enter sib2, iclass 32, count 0 2006.201.22:55:51.23#ibcon#flushed, iclass 32, count 0 2006.201.22:55:51.23#ibcon#about to write, iclass 32, count 0 2006.201.22:55:51.23#ibcon#wrote, iclass 32, count 0 2006.201.22:55:51.23#ibcon#about to read 3, iclass 32, count 0 2006.201.22:55:51.25#ibcon#read 3, iclass 32, count 0 2006.201.22:55:51.25#ibcon#about to read 4, iclass 32, count 0 2006.201.22:55:51.25#ibcon#read 4, iclass 32, count 0 2006.201.22:55:51.25#ibcon#about to read 5, iclass 32, count 0 2006.201.22:55:51.25#ibcon#read 5, iclass 32, count 0 2006.201.22:55:51.25#ibcon#about to read 6, iclass 32, count 0 2006.201.22:55:51.25#ibcon#read 6, iclass 32, count 0 2006.201.22:55:51.25#ibcon#end of sib2, iclass 32, count 0 2006.201.22:55:51.25#ibcon#*mode == 0, iclass 32, count 0 2006.201.22:55:51.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.22:55:51.25#ibcon#[25=BW32\r\n] 2006.201.22:55:51.25#ibcon#*before write, iclass 32, count 0 2006.201.22:55:51.25#ibcon#enter sib2, iclass 32, count 0 2006.201.22:55:51.25#ibcon#flushed, iclass 32, count 0 2006.201.22:55:51.25#ibcon#about to write, iclass 32, count 0 2006.201.22:55:51.25#ibcon#wrote, iclass 32, count 0 2006.201.22:55:51.25#ibcon#about to read 3, iclass 32, count 0 2006.201.22:55:51.28#ibcon#read 3, iclass 32, count 0 2006.201.22:55:51.28#ibcon#about to read 4, iclass 32, count 0 2006.201.22:55:51.28#ibcon#read 4, iclass 32, count 0 2006.201.22:55:51.28#ibcon#about to read 5, iclass 32, count 0 2006.201.22:55:51.28#ibcon#read 5, iclass 32, count 0 2006.201.22:55:51.28#ibcon#about to read 6, iclass 32, count 0 2006.201.22:55:51.28#ibcon#read 6, iclass 32, count 0 2006.201.22:55:51.28#ibcon#end of sib2, iclass 32, count 0 2006.201.22:55:51.28#ibcon#*after write, iclass 32, count 0 2006.201.22:55:51.28#ibcon#*before return 0, iclass 32, count 0 2006.201.22:55:51.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:51.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.22:55:51.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.22:55:51.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.22:55:51.28$vck44/vbbw=wide 2006.201.22:55:51.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.22:55:51.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.22:55:51.28#ibcon#ireg 8 cls_cnt 0 2006.201.22:55:51.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:55:51.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:55:51.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:55:51.35#ibcon#enter wrdev, iclass 34, count 0 2006.201.22:55:51.35#ibcon#first serial, iclass 34, count 0 2006.201.22:55:51.35#ibcon#enter sib2, iclass 34, count 0 2006.201.22:55:51.35#ibcon#flushed, iclass 34, count 0 2006.201.22:55:51.35#ibcon#about to write, iclass 34, count 0 2006.201.22:55:51.35#ibcon#wrote, iclass 34, count 0 2006.201.22:55:51.35#ibcon#about to read 3, iclass 34, count 0 2006.201.22:55:51.37#ibcon#read 3, iclass 34, count 0 2006.201.22:55:51.37#ibcon#about to read 4, iclass 34, count 0 2006.201.22:55:51.37#ibcon#read 4, iclass 34, count 0 2006.201.22:55:51.37#ibcon#about to read 5, iclass 34, count 0 2006.201.22:55:51.37#ibcon#read 5, iclass 34, count 0 2006.201.22:55:51.37#ibcon#about to read 6, iclass 34, count 0 2006.201.22:55:51.37#ibcon#read 6, iclass 34, count 0 2006.201.22:55:51.37#ibcon#end of sib2, iclass 34, count 0 2006.201.22:55:51.37#ibcon#*mode == 0, iclass 34, count 0 2006.201.22:55:51.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.22:55:51.37#ibcon#[27=BW32\r\n] 2006.201.22:55:51.37#ibcon#*before write, iclass 34, count 0 2006.201.22:55:51.37#ibcon#enter sib2, iclass 34, count 0 2006.201.22:55:51.37#ibcon#flushed, iclass 34, count 0 2006.201.22:55:51.37#ibcon#about to write, iclass 34, count 0 2006.201.22:55:51.37#ibcon#wrote, iclass 34, count 0 2006.201.22:55:51.37#ibcon#about to read 3, iclass 34, count 0 2006.201.22:55:51.40#ibcon#read 3, iclass 34, count 0 2006.201.22:55:51.40#ibcon#about to read 4, iclass 34, count 0 2006.201.22:55:51.40#ibcon#read 4, iclass 34, count 0 2006.201.22:55:51.40#ibcon#about to read 5, iclass 34, count 0 2006.201.22:55:51.40#ibcon#read 5, iclass 34, count 0 2006.201.22:55:51.40#ibcon#about to read 6, iclass 34, count 0 2006.201.22:55:51.40#ibcon#read 6, iclass 34, count 0 2006.201.22:55:51.40#ibcon#end of sib2, iclass 34, count 0 2006.201.22:55:51.40#ibcon#*after write, iclass 34, count 0 2006.201.22:55:51.40#ibcon#*before return 0, iclass 34, count 0 2006.201.22:55:51.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:55:51.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.22:55:51.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.22:55:51.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.22:55:51.40$setupk4/ifdk4 2006.201.22:55:51.40$ifdk4/lo= 2006.201.22:55:51.40$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.22:55:51.40$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.22:55:51.40$ifdk4/patch= 2006.201.22:55:51.40$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.22:55:51.40$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.22:55:51.40$setupk4/!*+20s 2006.201.22:55:54.54#abcon#<5=/04 1.6 3.1 20.061001001.5\r\n> 2006.201.22:55:54.56#abcon#{5=INTERFACE CLEAR} 2006.201.22:55:54.62#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:56:04.71#abcon#<5=/04 1.6 3.0 20.061001001.5\r\n> 2006.201.22:56:04.73#abcon#{5=INTERFACE CLEAR} 2006.201.22:56:04.79#abcon#[5=S1D000X0/0*\r\n] 2006.201.22:56:05.14#trakl#Source acquired 2006.201.22:56:05.14#flagr#flagr/antenna,acquired 2006.201.22:56:05.89$setupk4/"tpicd 2006.201.22:56:05.89$setupk4/echo=off 2006.201.22:56:05.89$setupk4/xlog=off 2006.201.22:56:05.89:!2006.201.22:59:42 2006.201.22:59:42.00:preob 2006.201.22:59:42.13/onsource/TRACKING 2006.201.22:59:42.13:!2006.201.22:59:52 2006.201.22:59:52.00:"tape 2006.201.22:59:52.00:"st=record 2006.201.22:59:52.00:data_valid=on 2006.201.22:59:52.00:midob 2006.201.22:59:53.13/onsource/TRACKING 2006.201.22:59:53.13/wx/20.09,1001.5,100 2006.201.22:59:53.34/cable/+6.4854E-03 2006.201.22:59:54.43/va/01,08,usb,yes,57,61 2006.201.22:59:54.43/va/02,07,usb,yes,61,62 2006.201.22:59:54.43/va/03,08,usb,yes,56,58 2006.201.22:59:54.43/va/04,07,usb,yes,63,66 2006.201.22:59:54.43/va/05,04,usb,yes,56,58 2006.201.22:59:54.43/va/06,05,usb,yes,57,57 2006.201.22:59:54.43/va/07,05,usb,yes,56,57 2006.201.22:59:54.43/va/08,04,usb,yes,55,65 2006.201.22:59:54.66/valo/01,524.99,yes,locked 2006.201.22:59:54.66/valo/02,534.99,yes,locked 2006.201.22:59:54.66/valo/03,564.99,yes,locked 2006.201.22:59:54.66/valo/04,624.99,yes,locked 2006.201.22:59:54.66/valo/05,734.99,yes,locked 2006.201.22:59:54.66/valo/06,814.99,yes,locked 2006.201.22:59:54.66/valo/07,864.99,yes,locked 2006.201.22:59:54.66/valo/08,884.99,yes,locked 2006.201.22:59:55.75/vb/01,04,usb,yes,32,30 2006.201.22:59:55.75/vb/02,05,usb,yes,30,30 2006.201.22:59:55.75/vb/03,04,usb,yes,31,35 2006.201.22:59:55.75/vb/04,05,usb,yes,32,31 2006.201.22:59:55.75/vb/05,04,usb,yes,28,31 2006.201.22:59:55.75/vb/06,04,usb,yes,33,29 2006.201.22:59:55.75/vb/07,04,usb,yes,33,33 2006.201.22:59:55.75/vb/08,04,usb,yes,30,34 2006.201.22:59:55.99/vblo/01,629.99,yes,locked 2006.201.22:59:55.99/vblo/02,634.99,yes,locked 2006.201.22:59:55.99/vblo/03,649.99,yes,locked 2006.201.22:59:55.99/vblo/04,679.99,yes,locked 2006.201.22:59:55.99/vblo/05,709.99,yes,locked 2006.201.22:59:55.99/vblo/06,719.99,yes,locked 2006.201.22:59:55.99/vblo/07,734.99,yes,locked 2006.201.22:59:55.99/vblo/08,744.99,yes,locked 2006.201.22:59:56.14/vabw/8 2006.201.22:59:56.29/vbbw/8 2006.201.22:59:56.38/xfe/off,on,14.5 2006.201.22:59:56.76/ifatt/23,28,28,28 2006.201.22:59:57.06/fmout-gps/S +4.53E-07 2006.201.22:59:57.13:!2006.201.23:03:42 2006.201.23:03:42.00:data_valid=off 2006.201.23:03:42.00:"et 2006.201.23:03:42.00:!+3s 2006.201.23:03:45.02:"tape 2006.201.23:03:45.02:postob 2006.201.23:03:45.10/cable/+6.4834E-03 2006.201.23:03:45.10/wx/20.12,1001.7,100 2006.201.23:03:45.17/fmout-gps/S +4.52E-07 2006.201.23:03:45.17:scan_name=201-2314,jd0607,580 2006.201.23:03:45.18:source=0133+476,013658.59,475129.1,2000.0,cw 2006.201.23:03:46.14#flagr#flagr/antenna,new-source 2006.201.23:03:46.14:checkk5 2006.201.23:03:46.52/chk_autoobs//k5ts1/ autoobs is running! 2006.201.23:03:46.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.23:03:47.27/chk_autoobs//k5ts3/ autoobs is running! 2006.201.23:03:47.63/chk_autoobs//k5ts4/ autoobs is running! 2006.201.23:03:48.00/chk_obsdata//k5ts1/T2012259??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.23:03:48.36/chk_obsdata//k5ts2/T2012259??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.23:03:48.73/chk_obsdata//k5ts3/T2012259??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.23:03:49.09/chk_obsdata//k5ts4/T2012259??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.201.23:03:49.78/k5log//k5ts1_log_newline 2006.201.23:03:50.47/k5log//k5ts2_log_newline 2006.201.23:03:51.16/k5log//k5ts3_log_newline 2006.201.23:03:51.84/k5log//k5ts4_log_newline 2006.201.23:03:51.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.23:03:51.86:setupk4=1 2006.201.23:03:51.86$setupk4/echo=on 2006.201.23:03:51.86$setupk4/pcalon 2006.201.23:03:51.86$pcalon/"no phase cal control is implemented here 2006.201.23:03:51.86$setupk4/"tpicd=stop 2006.201.23:03:51.86$setupk4/"rec=synch_on 2006.201.23:03:51.86$setupk4/"rec_mode=128 2006.201.23:03:51.86$setupk4/!* 2006.201.23:03:51.86$setupk4/recpk4 2006.201.23:03:51.86$recpk4/recpatch= 2006.201.23:03:51.87$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.23:03:51.87$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.23:03:51.87$setupk4/vck44 2006.201.23:03:51.87$vck44/valo=1,524.99 2006.201.23:03:51.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.23:03:51.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.23:03:51.87#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:51.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:51.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:51.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:51.87#ibcon#enter wrdev, iclass 11, count 0 2006.201.23:03:51.87#ibcon#first serial, iclass 11, count 0 2006.201.23:03:51.87#ibcon#enter sib2, iclass 11, count 0 2006.201.23:03:51.87#ibcon#flushed, iclass 11, count 0 2006.201.23:03:51.87#ibcon#about to write, iclass 11, count 0 2006.201.23:03:51.87#ibcon#wrote, iclass 11, count 0 2006.201.23:03:51.87#ibcon#about to read 3, iclass 11, count 0 2006.201.23:03:51.90#ibcon#read 3, iclass 11, count 0 2006.201.23:03:51.90#ibcon#about to read 4, iclass 11, count 0 2006.201.23:03:51.90#ibcon#read 4, iclass 11, count 0 2006.201.23:03:51.90#ibcon#about to read 5, iclass 11, count 0 2006.201.23:03:51.90#ibcon#read 5, iclass 11, count 0 2006.201.23:03:51.90#ibcon#about to read 6, iclass 11, count 0 2006.201.23:03:51.90#ibcon#read 6, iclass 11, count 0 2006.201.23:03:51.90#ibcon#end of sib2, iclass 11, count 0 2006.201.23:03:51.90#ibcon#*mode == 0, iclass 11, count 0 2006.201.23:03:51.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.23:03:51.90#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.23:03:51.90#ibcon#*before write, iclass 11, count 0 2006.201.23:03:51.90#ibcon#enter sib2, iclass 11, count 0 2006.201.23:03:51.90#ibcon#flushed, iclass 11, count 0 2006.201.23:03:51.90#ibcon#about to write, iclass 11, count 0 2006.201.23:03:51.90#ibcon#wrote, iclass 11, count 0 2006.201.23:03:51.90#ibcon#about to read 3, iclass 11, count 0 2006.201.23:03:51.96#ibcon#read 3, iclass 11, count 0 2006.201.23:03:51.96#ibcon#about to read 4, iclass 11, count 0 2006.201.23:03:51.96#ibcon#read 4, iclass 11, count 0 2006.201.23:03:51.96#ibcon#about to read 5, iclass 11, count 0 2006.201.23:03:51.96#ibcon#read 5, iclass 11, count 0 2006.201.23:03:51.96#ibcon#about to read 6, iclass 11, count 0 2006.201.23:03:51.96#ibcon#read 6, iclass 11, count 0 2006.201.23:03:51.96#ibcon#end of sib2, iclass 11, count 0 2006.201.23:03:51.96#ibcon#*after write, iclass 11, count 0 2006.201.23:03:51.96#ibcon#*before return 0, iclass 11, count 0 2006.201.23:03:51.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:51.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:51.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.23:03:51.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.23:03:51.96$vck44/va=1,8 2006.201.23:03:51.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.23:03:51.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.23:03:51.96#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:51.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:51.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:51.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:51.96#ibcon#enter wrdev, iclass 13, count 2 2006.201.23:03:51.96#ibcon#first serial, iclass 13, count 2 2006.201.23:03:51.96#ibcon#enter sib2, iclass 13, count 2 2006.201.23:03:51.96#ibcon#flushed, iclass 13, count 2 2006.201.23:03:51.96#ibcon#about to write, iclass 13, count 2 2006.201.23:03:51.96#ibcon#wrote, iclass 13, count 2 2006.201.23:03:51.96#ibcon#about to read 3, iclass 13, count 2 2006.201.23:03:51.98#ibcon#read 3, iclass 13, count 2 2006.201.23:03:51.98#ibcon#about to read 4, iclass 13, count 2 2006.201.23:03:51.98#ibcon#read 4, iclass 13, count 2 2006.201.23:03:51.98#ibcon#about to read 5, iclass 13, count 2 2006.201.23:03:51.98#ibcon#read 5, iclass 13, count 2 2006.201.23:03:51.98#ibcon#about to read 6, iclass 13, count 2 2006.201.23:03:51.98#ibcon#read 6, iclass 13, count 2 2006.201.23:03:51.98#ibcon#end of sib2, iclass 13, count 2 2006.201.23:03:51.98#ibcon#*mode == 0, iclass 13, count 2 2006.201.23:03:51.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.23:03:51.98#ibcon#[25=AT01-08\r\n] 2006.201.23:03:51.98#ibcon#*before write, iclass 13, count 2 2006.201.23:03:51.98#ibcon#enter sib2, iclass 13, count 2 2006.201.23:03:51.98#ibcon#flushed, iclass 13, count 2 2006.201.23:03:51.98#ibcon#about to write, iclass 13, count 2 2006.201.23:03:51.98#ibcon#wrote, iclass 13, count 2 2006.201.23:03:51.98#ibcon#about to read 3, iclass 13, count 2 2006.201.23:03:52.02#ibcon#read 3, iclass 13, count 2 2006.201.23:03:52.02#ibcon#about to read 4, iclass 13, count 2 2006.201.23:03:52.02#ibcon#read 4, iclass 13, count 2 2006.201.23:03:52.02#ibcon#about to read 5, iclass 13, count 2 2006.201.23:03:52.02#ibcon#read 5, iclass 13, count 2 2006.201.23:03:52.02#ibcon#about to read 6, iclass 13, count 2 2006.201.23:03:52.02#ibcon#read 6, iclass 13, count 2 2006.201.23:03:52.02#ibcon#end of sib2, iclass 13, count 2 2006.201.23:03:52.02#ibcon#*after write, iclass 13, count 2 2006.201.23:03:52.02#ibcon#*before return 0, iclass 13, count 2 2006.201.23:03:52.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:52.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:52.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.23:03:52.02#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:52.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:52.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:52.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:52.14#ibcon#enter wrdev, iclass 13, count 0 2006.201.23:03:52.14#ibcon#first serial, iclass 13, count 0 2006.201.23:03:52.14#ibcon#enter sib2, iclass 13, count 0 2006.201.23:03:52.14#ibcon#flushed, iclass 13, count 0 2006.201.23:03:52.14#ibcon#about to write, iclass 13, count 0 2006.201.23:03:52.14#ibcon#wrote, iclass 13, count 0 2006.201.23:03:52.14#ibcon#about to read 3, iclass 13, count 0 2006.201.23:03:52.16#ibcon#read 3, iclass 13, count 0 2006.201.23:03:52.16#ibcon#about to read 4, iclass 13, count 0 2006.201.23:03:52.16#ibcon#read 4, iclass 13, count 0 2006.201.23:03:52.16#ibcon#about to read 5, iclass 13, count 0 2006.201.23:03:52.16#ibcon#read 5, iclass 13, count 0 2006.201.23:03:52.16#ibcon#about to read 6, iclass 13, count 0 2006.201.23:03:52.16#ibcon#read 6, iclass 13, count 0 2006.201.23:03:52.16#ibcon#end of sib2, iclass 13, count 0 2006.201.23:03:52.16#ibcon#*mode == 0, iclass 13, count 0 2006.201.23:03:52.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.23:03:52.16#ibcon#[25=USB\r\n] 2006.201.23:03:52.16#ibcon#*before write, iclass 13, count 0 2006.201.23:03:52.16#ibcon#enter sib2, iclass 13, count 0 2006.201.23:03:52.16#ibcon#flushed, iclass 13, count 0 2006.201.23:03:52.16#ibcon#about to write, iclass 13, count 0 2006.201.23:03:52.16#ibcon#wrote, iclass 13, count 0 2006.201.23:03:52.16#ibcon#about to read 3, iclass 13, count 0 2006.201.23:03:52.19#ibcon#read 3, iclass 13, count 0 2006.201.23:03:52.19#ibcon#about to read 4, iclass 13, count 0 2006.201.23:03:52.19#ibcon#read 4, iclass 13, count 0 2006.201.23:03:52.19#ibcon#about to read 5, iclass 13, count 0 2006.201.23:03:52.19#ibcon#read 5, iclass 13, count 0 2006.201.23:03:52.19#ibcon#about to read 6, iclass 13, count 0 2006.201.23:03:52.19#ibcon#read 6, iclass 13, count 0 2006.201.23:03:52.19#ibcon#end of sib2, iclass 13, count 0 2006.201.23:03:52.19#ibcon#*after write, iclass 13, count 0 2006.201.23:03:52.19#ibcon#*before return 0, iclass 13, count 0 2006.201.23:03:52.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:52.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:52.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.23:03:52.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.23:03:52.19$vck44/valo=2,534.99 2006.201.23:03:52.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.23:03:52.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.23:03:52.19#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:52.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:52.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:52.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:52.19#ibcon#enter wrdev, iclass 15, count 0 2006.201.23:03:52.19#ibcon#first serial, iclass 15, count 0 2006.201.23:03:52.19#ibcon#enter sib2, iclass 15, count 0 2006.201.23:03:52.19#ibcon#flushed, iclass 15, count 0 2006.201.23:03:52.19#ibcon#about to write, iclass 15, count 0 2006.201.23:03:52.19#ibcon#wrote, iclass 15, count 0 2006.201.23:03:52.19#ibcon#about to read 3, iclass 15, count 0 2006.201.23:03:52.21#ibcon#read 3, iclass 15, count 0 2006.201.23:03:52.21#ibcon#about to read 4, iclass 15, count 0 2006.201.23:03:52.21#ibcon#read 4, iclass 15, count 0 2006.201.23:03:52.21#ibcon#about to read 5, iclass 15, count 0 2006.201.23:03:52.21#ibcon#read 5, iclass 15, count 0 2006.201.23:03:52.21#ibcon#about to read 6, iclass 15, count 0 2006.201.23:03:52.21#ibcon#read 6, iclass 15, count 0 2006.201.23:03:52.21#ibcon#end of sib2, iclass 15, count 0 2006.201.23:03:52.21#ibcon#*mode == 0, iclass 15, count 0 2006.201.23:03:52.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.23:03:52.21#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.23:03:52.21#ibcon#*before write, iclass 15, count 0 2006.201.23:03:52.21#ibcon#enter sib2, iclass 15, count 0 2006.201.23:03:52.21#ibcon#flushed, iclass 15, count 0 2006.201.23:03:52.21#ibcon#about to write, iclass 15, count 0 2006.201.23:03:52.21#ibcon#wrote, iclass 15, count 0 2006.201.23:03:52.21#ibcon#about to read 3, iclass 15, count 0 2006.201.23:03:52.26#ibcon#read 3, iclass 15, count 0 2006.201.23:03:52.26#ibcon#about to read 4, iclass 15, count 0 2006.201.23:03:52.26#ibcon#read 4, iclass 15, count 0 2006.201.23:03:52.26#ibcon#about to read 5, iclass 15, count 0 2006.201.23:03:52.26#ibcon#read 5, iclass 15, count 0 2006.201.23:03:52.26#ibcon#about to read 6, iclass 15, count 0 2006.201.23:03:52.26#ibcon#read 6, iclass 15, count 0 2006.201.23:03:52.26#ibcon#end of sib2, iclass 15, count 0 2006.201.23:03:52.26#ibcon#*after write, iclass 15, count 0 2006.201.23:03:52.26#ibcon#*before return 0, iclass 15, count 0 2006.201.23:03:52.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:52.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:52.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.23:03:52.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.23:03:52.26$vck44/va=2,7 2006.201.23:03:52.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.23:03:52.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.23:03:52.26#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:52.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:52.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:52.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:52.31#ibcon#enter wrdev, iclass 17, count 2 2006.201.23:03:52.31#ibcon#first serial, iclass 17, count 2 2006.201.23:03:52.31#ibcon#enter sib2, iclass 17, count 2 2006.201.23:03:52.31#ibcon#flushed, iclass 17, count 2 2006.201.23:03:52.31#ibcon#about to write, iclass 17, count 2 2006.201.23:03:52.31#ibcon#wrote, iclass 17, count 2 2006.201.23:03:52.31#ibcon#about to read 3, iclass 17, count 2 2006.201.23:03:52.33#ibcon#read 3, iclass 17, count 2 2006.201.23:03:52.33#ibcon#about to read 4, iclass 17, count 2 2006.201.23:03:52.33#ibcon#read 4, iclass 17, count 2 2006.201.23:03:52.33#ibcon#about to read 5, iclass 17, count 2 2006.201.23:03:52.33#ibcon#read 5, iclass 17, count 2 2006.201.23:03:52.33#ibcon#about to read 6, iclass 17, count 2 2006.201.23:03:52.33#ibcon#read 6, iclass 17, count 2 2006.201.23:03:52.33#ibcon#end of sib2, iclass 17, count 2 2006.201.23:03:52.33#ibcon#*mode == 0, iclass 17, count 2 2006.201.23:03:52.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.23:03:52.33#ibcon#[25=AT02-07\r\n] 2006.201.23:03:52.33#ibcon#*before write, iclass 17, count 2 2006.201.23:03:52.33#ibcon#enter sib2, iclass 17, count 2 2006.201.23:03:52.33#ibcon#flushed, iclass 17, count 2 2006.201.23:03:52.33#ibcon#about to write, iclass 17, count 2 2006.201.23:03:52.33#ibcon#wrote, iclass 17, count 2 2006.201.23:03:52.33#ibcon#about to read 3, iclass 17, count 2 2006.201.23:03:52.36#ibcon#read 3, iclass 17, count 2 2006.201.23:03:52.36#ibcon#about to read 4, iclass 17, count 2 2006.201.23:03:52.36#ibcon#read 4, iclass 17, count 2 2006.201.23:03:52.36#ibcon#about to read 5, iclass 17, count 2 2006.201.23:03:52.36#ibcon#read 5, iclass 17, count 2 2006.201.23:03:52.36#ibcon#about to read 6, iclass 17, count 2 2006.201.23:03:52.36#ibcon#read 6, iclass 17, count 2 2006.201.23:03:52.36#ibcon#end of sib2, iclass 17, count 2 2006.201.23:03:52.36#ibcon#*after write, iclass 17, count 2 2006.201.23:03:52.36#ibcon#*before return 0, iclass 17, count 2 2006.201.23:03:52.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:52.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:52.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.23:03:52.36#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:52.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:52.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:52.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:52.48#ibcon#enter wrdev, iclass 17, count 0 2006.201.23:03:52.48#ibcon#first serial, iclass 17, count 0 2006.201.23:03:52.48#ibcon#enter sib2, iclass 17, count 0 2006.201.23:03:52.48#ibcon#flushed, iclass 17, count 0 2006.201.23:03:52.48#ibcon#about to write, iclass 17, count 0 2006.201.23:03:52.48#ibcon#wrote, iclass 17, count 0 2006.201.23:03:52.48#ibcon#about to read 3, iclass 17, count 0 2006.201.23:03:52.50#ibcon#read 3, iclass 17, count 0 2006.201.23:03:52.50#ibcon#about to read 4, iclass 17, count 0 2006.201.23:03:52.50#ibcon#read 4, iclass 17, count 0 2006.201.23:03:52.50#ibcon#about to read 5, iclass 17, count 0 2006.201.23:03:52.50#ibcon#read 5, iclass 17, count 0 2006.201.23:03:52.50#ibcon#about to read 6, iclass 17, count 0 2006.201.23:03:52.50#ibcon#read 6, iclass 17, count 0 2006.201.23:03:52.50#ibcon#end of sib2, iclass 17, count 0 2006.201.23:03:52.50#ibcon#*mode == 0, iclass 17, count 0 2006.201.23:03:52.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.23:03:52.50#ibcon#[25=USB\r\n] 2006.201.23:03:52.50#ibcon#*before write, iclass 17, count 0 2006.201.23:03:52.50#ibcon#enter sib2, iclass 17, count 0 2006.201.23:03:52.50#ibcon#flushed, iclass 17, count 0 2006.201.23:03:52.50#ibcon#about to write, iclass 17, count 0 2006.201.23:03:52.50#ibcon#wrote, iclass 17, count 0 2006.201.23:03:52.50#ibcon#about to read 3, iclass 17, count 0 2006.201.23:03:52.53#ibcon#read 3, iclass 17, count 0 2006.201.23:03:52.53#ibcon#about to read 4, iclass 17, count 0 2006.201.23:03:52.53#ibcon#read 4, iclass 17, count 0 2006.201.23:03:52.53#ibcon#about to read 5, iclass 17, count 0 2006.201.23:03:52.53#ibcon#read 5, iclass 17, count 0 2006.201.23:03:52.53#ibcon#about to read 6, iclass 17, count 0 2006.201.23:03:52.53#ibcon#read 6, iclass 17, count 0 2006.201.23:03:52.53#ibcon#end of sib2, iclass 17, count 0 2006.201.23:03:52.53#ibcon#*after write, iclass 17, count 0 2006.201.23:03:52.53#ibcon#*before return 0, iclass 17, count 0 2006.201.23:03:52.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:52.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:52.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.23:03:52.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.23:03:52.53$vck44/valo=3,564.99 2006.201.23:03:52.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.23:03:52.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.23:03:52.53#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:52.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:52.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:52.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:52.53#ibcon#enter wrdev, iclass 19, count 0 2006.201.23:03:52.53#ibcon#first serial, iclass 19, count 0 2006.201.23:03:52.53#ibcon#enter sib2, iclass 19, count 0 2006.201.23:03:52.53#ibcon#flushed, iclass 19, count 0 2006.201.23:03:52.53#ibcon#about to write, iclass 19, count 0 2006.201.23:03:52.53#ibcon#wrote, iclass 19, count 0 2006.201.23:03:52.53#ibcon#about to read 3, iclass 19, count 0 2006.201.23:03:52.55#ibcon#read 3, iclass 19, count 0 2006.201.23:03:52.55#ibcon#about to read 4, iclass 19, count 0 2006.201.23:03:52.55#ibcon#read 4, iclass 19, count 0 2006.201.23:03:52.55#ibcon#about to read 5, iclass 19, count 0 2006.201.23:03:52.55#ibcon#read 5, iclass 19, count 0 2006.201.23:03:52.55#ibcon#about to read 6, iclass 19, count 0 2006.201.23:03:52.55#ibcon#read 6, iclass 19, count 0 2006.201.23:03:52.55#ibcon#end of sib2, iclass 19, count 0 2006.201.23:03:52.55#ibcon#*mode == 0, iclass 19, count 0 2006.201.23:03:52.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.23:03:52.55#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.23:03:52.55#ibcon#*before write, iclass 19, count 0 2006.201.23:03:52.55#ibcon#enter sib2, iclass 19, count 0 2006.201.23:03:52.55#ibcon#flushed, iclass 19, count 0 2006.201.23:03:52.55#ibcon#about to write, iclass 19, count 0 2006.201.23:03:52.55#ibcon#wrote, iclass 19, count 0 2006.201.23:03:52.55#ibcon#about to read 3, iclass 19, count 0 2006.201.23:03:52.60#ibcon#read 3, iclass 19, count 0 2006.201.23:03:52.60#ibcon#about to read 4, iclass 19, count 0 2006.201.23:03:52.60#ibcon#read 4, iclass 19, count 0 2006.201.23:03:52.60#ibcon#about to read 5, iclass 19, count 0 2006.201.23:03:52.60#ibcon#read 5, iclass 19, count 0 2006.201.23:03:52.60#ibcon#about to read 6, iclass 19, count 0 2006.201.23:03:52.60#ibcon#read 6, iclass 19, count 0 2006.201.23:03:52.60#ibcon#end of sib2, iclass 19, count 0 2006.201.23:03:52.60#ibcon#*after write, iclass 19, count 0 2006.201.23:03:52.60#ibcon#*before return 0, iclass 19, count 0 2006.201.23:03:52.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:52.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:52.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.23:03:52.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.23:03:52.60$vck44/va=3,8 2006.201.23:03:52.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.23:03:52.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.23:03:52.60#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:52.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:52.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:52.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:52.65#ibcon#enter wrdev, iclass 21, count 2 2006.201.23:03:52.65#ibcon#first serial, iclass 21, count 2 2006.201.23:03:52.65#ibcon#enter sib2, iclass 21, count 2 2006.201.23:03:52.65#ibcon#flushed, iclass 21, count 2 2006.201.23:03:52.65#ibcon#about to write, iclass 21, count 2 2006.201.23:03:52.65#ibcon#wrote, iclass 21, count 2 2006.201.23:03:52.65#ibcon#about to read 3, iclass 21, count 2 2006.201.23:03:52.67#ibcon#read 3, iclass 21, count 2 2006.201.23:03:52.67#ibcon#about to read 4, iclass 21, count 2 2006.201.23:03:52.67#ibcon#read 4, iclass 21, count 2 2006.201.23:03:52.67#ibcon#about to read 5, iclass 21, count 2 2006.201.23:03:52.67#ibcon#read 5, iclass 21, count 2 2006.201.23:03:52.67#ibcon#about to read 6, iclass 21, count 2 2006.201.23:03:52.67#ibcon#read 6, iclass 21, count 2 2006.201.23:03:52.67#ibcon#end of sib2, iclass 21, count 2 2006.201.23:03:52.67#ibcon#*mode == 0, iclass 21, count 2 2006.201.23:03:52.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.23:03:52.67#ibcon#[25=AT03-08\r\n] 2006.201.23:03:52.67#ibcon#*before write, iclass 21, count 2 2006.201.23:03:52.67#ibcon#enter sib2, iclass 21, count 2 2006.201.23:03:52.67#ibcon#flushed, iclass 21, count 2 2006.201.23:03:52.67#ibcon#about to write, iclass 21, count 2 2006.201.23:03:52.67#ibcon#wrote, iclass 21, count 2 2006.201.23:03:52.67#ibcon#about to read 3, iclass 21, count 2 2006.201.23:03:52.70#ibcon#read 3, iclass 21, count 2 2006.201.23:03:52.70#ibcon#about to read 4, iclass 21, count 2 2006.201.23:03:52.70#ibcon#read 4, iclass 21, count 2 2006.201.23:03:52.70#ibcon#about to read 5, iclass 21, count 2 2006.201.23:03:52.70#ibcon#read 5, iclass 21, count 2 2006.201.23:03:52.70#ibcon#about to read 6, iclass 21, count 2 2006.201.23:03:52.70#ibcon#read 6, iclass 21, count 2 2006.201.23:03:52.70#ibcon#end of sib2, iclass 21, count 2 2006.201.23:03:52.70#ibcon#*after write, iclass 21, count 2 2006.201.23:03:52.70#ibcon#*before return 0, iclass 21, count 2 2006.201.23:03:52.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:52.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:52.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.23:03:52.70#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:52.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:52.71#abcon#<5=/03 0.6 2.0 20.121001001.7\r\n> 2006.201.23:03:52.73#abcon#{5=INTERFACE CLEAR} 2006.201.23:03:52.79#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:03:52.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:52.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:52.82#ibcon#enter wrdev, iclass 21, count 0 2006.201.23:03:52.82#ibcon#first serial, iclass 21, count 0 2006.201.23:03:52.82#ibcon#enter sib2, iclass 21, count 0 2006.201.23:03:52.82#ibcon#flushed, iclass 21, count 0 2006.201.23:03:52.82#ibcon#about to write, iclass 21, count 0 2006.201.23:03:52.82#ibcon#wrote, iclass 21, count 0 2006.201.23:03:52.82#ibcon#about to read 3, iclass 21, count 0 2006.201.23:03:52.85#ibcon#read 3, iclass 21, count 0 2006.201.23:03:52.85#ibcon#about to read 4, iclass 21, count 0 2006.201.23:03:52.85#ibcon#read 4, iclass 21, count 0 2006.201.23:03:52.85#ibcon#about to read 5, iclass 21, count 0 2006.201.23:03:52.85#ibcon#read 5, iclass 21, count 0 2006.201.23:03:52.85#ibcon#about to read 6, iclass 21, count 0 2006.201.23:03:52.85#ibcon#read 6, iclass 21, count 0 2006.201.23:03:52.85#ibcon#end of sib2, iclass 21, count 0 2006.201.23:03:52.85#ibcon#*mode == 0, iclass 21, count 0 2006.201.23:03:52.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.23:03:52.85#ibcon#[25=USB\r\n] 2006.201.23:03:52.85#ibcon#*before write, iclass 21, count 0 2006.201.23:03:52.85#ibcon#enter sib2, iclass 21, count 0 2006.201.23:03:52.85#ibcon#flushed, iclass 21, count 0 2006.201.23:03:52.85#ibcon#about to write, iclass 21, count 0 2006.201.23:03:52.85#ibcon#wrote, iclass 21, count 0 2006.201.23:03:52.85#ibcon#about to read 3, iclass 21, count 0 2006.201.23:03:52.88#ibcon#read 3, iclass 21, count 0 2006.201.23:03:52.88#ibcon#about to read 4, iclass 21, count 0 2006.201.23:03:52.88#ibcon#read 4, iclass 21, count 0 2006.201.23:03:52.88#ibcon#about to read 5, iclass 21, count 0 2006.201.23:03:52.88#ibcon#read 5, iclass 21, count 0 2006.201.23:03:52.88#ibcon#about to read 6, iclass 21, count 0 2006.201.23:03:52.88#ibcon#read 6, iclass 21, count 0 2006.201.23:03:52.88#ibcon#end of sib2, iclass 21, count 0 2006.201.23:03:52.88#ibcon#*after write, iclass 21, count 0 2006.201.23:03:52.88#ibcon#*before return 0, iclass 21, count 0 2006.201.23:03:52.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:52.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:52.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.23:03:52.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.23:03:52.88$vck44/valo=4,624.99 2006.201.23:03:52.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.23:03:52.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.23:03:52.88#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:52.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:52.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:52.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:52.88#ibcon#enter wrdev, iclass 27, count 0 2006.201.23:03:52.88#ibcon#first serial, iclass 27, count 0 2006.201.23:03:52.88#ibcon#enter sib2, iclass 27, count 0 2006.201.23:03:52.88#ibcon#flushed, iclass 27, count 0 2006.201.23:03:52.88#ibcon#about to write, iclass 27, count 0 2006.201.23:03:52.88#ibcon#wrote, iclass 27, count 0 2006.201.23:03:52.88#ibcon#about to read 3, iclass 27, count 0 2006.201.23:03:52.90#ibcon#read 3, iclass 27, count 0 2006.201.23:03:52.90#ibcon#about to read 4, iclass 27, count 0 2006.201.23:03:52.90#ibcon#read 4, iclass 27, count 0 2006.201.23:03:52.90#ibcon#about to read 5, iclass 27, count 0 2006.201.23:03:52.90#ibcon#read 5, iclass 27, count 0 2006.201.23:03:52.90#ibcon#about to read 6, iclass 27, count 0 2006.201.23:03:52.90#ibcon#read 6, iclass 27, count 0 2006.201.23:03:52.90#ibcon#end of sib2, iclass 27, count 0 2006.201.23:03:52.90#ibcon#*mode == 0, iclass 27, count 0 2006.201.23:03:52.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.23:03:52.90#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.23:03:52.90#ibcon#*before write, iclass 27, count 0 2006.201.23:03:52.90#ibcon#enter sib2, iclass 27, count 0 2006.201.23:03:52.90#ibcon#flushed, iclass 27, count 0 2006.201.23:03:52.90#ibcon#about to write, iclass 27, count 0 2006.201.23:03:52.90#ibcon#wrote, iclass 27, count 0 2006.201.23:03:52.90#ibcon#about to read 3, iclass 27, count 0 2006.201.23:03:52.94#ibcon#read 3, iclass 27, count 0 2006.201.23:03:52.94#ibcon#about to read 4, iclass 27, count 0 2006.201.23:03:52.94#ibcon#read 4, iclass 27, count 0 2006.201.23:03:52.94#ibcon#about to read 5, iclass 27, count 0 2006.201.23:03:52.94#ibcon#read 5, iclass 27, count 0 2006.201.23:03:52.94#ibcon#about to read 6, iclass 27, count 0 2006.201.23:03:52.94#ibcon#read 6, iclass 27, count 0 2006.201.23:03:52.94#ibcon#end of sib2, iclass 27, count 0 2006.201.23:03:52.94#ibcon#*after write, iclass 27, count 0 2006.201.23:03:52.94#ibcon#*before return 0, iclass 27, count 0 2006.201.23:03:52.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:52.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:52.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.23:03:52.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.23:03:52.94$vck44/va=4,7 2006.201.23:03:52.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.23:03:52.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.23:03:52.94#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:52.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:53.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:53.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:53.00#ibcon#enter wrdev, iclass 29, count 2 2006.201.23:03:53.00#ibcon#first serial, iclass 29, count 2 2006.201.23:03:53.00#ibcon#enter sib2, iclass 29, count 2 2006.201.23:03:53.00#ibcon#flushed, iclass 29, count 2 2006.201.23:03:53.00#ibcon#about to write, iclass 29, count 2 2006.201.23:03:53.00#ibcon#wrote, iclass 29, count 2 2006.201.23:03:53.00#ibcon#about to read 3, iclass 29, count 2 2006.201.23:03:53.02#ibcon#read 3, iclass 29, count 2 2006.201.23:03:53.02#ibcon#about to read 4, iclass 29, count 2 2006.201.23:03:53.02#ibcon#read 4, iclass 29, count 2 2006.201.23:03:53.02#ibcon#about to read 5, iclass 29, count 2 2006.201.23:03:53.02#ibcon#read 5, iclass 29, count 2 2006.201.23:03:53.02#ibcon#about to read 6, iclass 29, count 2 2006.201.23:03:53.02#ibcon#read 6, iclass 29, count 2 2006.201.23:03:53.02#ibcon#end of sib2, iclass 29, count 2 2006.201.23:03:53.02#ibcon#*mode == 0, iclass 29, count 2 2006.201.23:03:53.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.23:03:53.02#ibcon#[25=AT04-07\r\n] 2006.201.23:03:53.02#ibcon#*before write, iclass 29, count 2 2006.201.23:03:53.02#ibcon#enter sib2, iclass 29, count 2 2006.201.23:03:53.02#ibcon#flushed, iclass 29, count 2 2006.201.23:03:53.02#ibcon#about to write, iclass 29, count 2 2006.201.23:03:53.02#ibcon#wrote, iclass 29, count 2 2006.201.23:03:53.02#ibcon#about to read 3, iclass 29, count 2 2006.201.23:03:53.05#ibcon#read 3, iclass 29, count 2 2006.201.23:03:53.05#ibcon#about to read 4, iclass 29, count 2 2006.201.23:03:53.05#ibcon#read 4, iclass 29, count 2 2006.201.23:03:53.05#ibcon#about to read 5, iclass 29, count 2 2006.201.23:03:53.05#ibcon#read 5, iclass 29, count 2 2006.201.23:03:53.05#ibcon#about to read 6, iclass 29, count 2 2006.201.23:03:53.05#ibcon#read 6, iclass 29, count 2 2006.201.23:03:53.05#ibcon#end of sib2, iclass 29, count 2 2006.201.23:03:53.05#ibcon#*after write, iclass 29, count 2 2006.201.23:03:53.05#ibcon#*before return 0, iclass 29, count 2 2006.201.23:03:53.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:53.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:53.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.23:03:53.05#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:53.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:53.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:53.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:53.17#ibcon#enter wrdev, iclass 29, count 0 2006.201.23:03:53.17#ibcon#first serial, iclass 29, count 0 2006.201.23:03:53.17#ibcon#enter sib2, iclass 29, count 0 2006.201.23:03:53.17#ibcon#flushed, iclass 29, count 0 2006.201.23:03:53.17#ibcon#about to write, iclass 29, count 0 2006.201.23:03:53.17#ibcon#wrote, iclass 29, count 0 2006.201.23:03:53.17#ibcon#about to read 3, iclass 29, count 0 2006.201.23:03:53.19#ibcon#read 3, iclass 29, count 0 2006.201.23:03:53.19#ibcon#about to read 4, iclass 29, count 0 2006.201.23:03:53.19#ibcon#read 4, iclass 29, count 0 2006.201.23:03:53.19#ibcon#about to read 5, iclass 29, count 0 2006.201.23:03:53.19#ibcon#read 5, iclass 29, count 0 2006.201.23:03:53.19#ibcon#about to read 6, iclass 29, count 0 2006.201.23:03:53.19#ibcon#read 6, iclass 29, count 0 2006.201.23:03:53.19#ibcon#end of sib2, iclass 29, count 0 2006.201.23:03:53.19#ibcon#*mode == 0, iclass 29, count 0 2006.201.23:03:53.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.23:03:53.19#ibcon#[25=USB\r\n] 2006.201.23:03:53.19#ibcon#*before write, iclass 29, count 0 2006.201.23:03:53.19#ibcon#enter sib2, iclass 29, count 0 2006.201.23:03:53.19#ibcon#flushed, iclass 29, count 0 2006.201.23:03:53.19#ibcon#about to write, iclass 29, count 0 2006.201.23:03:53.19#ibcon#wrote, iclass 29, count 0 2006.201.23:03:53.19#ibcon#about to read 3, iclass 29, count 0 2006.201.23:03:53.22#ibcon#read 3, iclass 29, count 0 2006.201.23:03:53.22#ibcon#about to read 4, iclass 29, count 0 2006.201.23:03:53.22#ibcon#read 4, iclass 29, count 0 2006.201.23:03:53.22#ibcon#about to read 5, iclass 29, count 0 2006.201.23:03:53.22#ibcon#read 5, iclass 29, count 0 2006.201.23:03:53.22#ibcon#about to read 6, iclass 29, count 0 2006.201.23:03:53.22#ibcon#read 6, iclass 29, count 0 2006.201.23:03:53.22#ibcon#end of sib2, iclass 29, count 0 2006.201.23:03:53.22#ibcon#*after write, iclass 29, count 0 2006.201.23:03:53.22#ibcon#*before return 0, iclass 29, count 0 2006.201.23:03:53.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:53.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:53.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.23:03:53.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.23:03:53.22$vck44/valo=5,734.99 2006.201.23:03:53.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.23:03:53.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.23:03:53.22#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:53.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:53.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:53.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:53.22#ibcon#enter wrdev, iclass 31, count 0 2006.201.23:03:53.22#ibcon#first serial, iclass 31, count 0 2006.201.23:03:53.22#ibcon#enter sib2, iclass 31, count 0 2006.201.23:03:53.22#ibcon#flushed, iclass 31, count 0 2006.201.23:03:53.22#ibcon#about to write, iclass 31, count 0 2006.201.23:03:53.22#ibcon#wrote, iclass 31, count 0 2006.201.23:03:53.22#ibcon#about to read 3, iclass 31, count 0 2006.201.23:03:53.24#ibcon#read 3, iclass 31, count 0 2006.201.23:03:53.24#ibcon#about to read 4, iclass 31, count 0 2006.201.23:03:53.24#ibcon#read 4, iclass 31, count 0 2006.201.23:03:53.24#ibcon#about to read 5, iclass 31, count 0 2006.201.23:03:53.24#ibcon#read 5, iclass 31, count 0 2006.201.23:03:53.24#ibcon#about to read 6, iclass 31, count 0 2006.201.23:03:53.24#ibcon#read 6, iclass 31, count 0 2006.201.23:03:53.24#ibcon#end of sib2, iclass 31, count 0 2006.201.23:03:53.24#ibcon#*mode == 0, iclass 31, count 0 2006.201.23:03:53.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.23:03:53.24#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.23:03:53.24#ibcon#*before write, iclass 31, count 0 2006.201.23:03:53.24#ibcon#enter sib2, iclass 31, count 0 2006.201.23:03:53.24#ibcon#flushed, iclass 31, count 0 2006.201.23:03:53.24#ibcon#about to write, iclass 31, count 0 2006.201.23:03:53.24#ibcon#wrote, iclass 31, count 0 2006.201.23:03:53.24#ibcon#about to read 3, iclass 31, count 0 2006.201.23:03:53.28#ibcon#read 3, iclass 31, count 0 2006.201.23:03:53.28#ibcon#about to read 4, iclass 31, count 0 2006.201.23:03:53.28#ibcon#read 4, iclass 31, count 0 2006.201.23:03:53.28#ibcon#about to read 5, iclass 31, count 0 2006.201.23:03:53.28#ibcon#read 5, iclass 31, count 0 2006.201.23:03:53.28#ibcon#about to read 6, iclass 31, count 0 2006.201.23:03:53.28#ibcon#read 6, iclass 31, count 0 2006.201.23:03:53.28#ibcon#end of sib2, iclass 31, count 0 2006.201.23:03:53.28#ibcon#*after write, iclass 31, count 0 2006.201.23:03:53.28#ibcon#*before return 0, iclass 31, count 0 2006.201.23:03:53.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:53.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:53.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.23:03:53.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.23:03:53.28$vck44/va=5,4 2006.201.23:03:53.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.23:03:53.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.23:03:53.28#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:53.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:53.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:53.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:53.34#ibcon#enter wrdev, iclass 33, count 2 2006.201.23:03:53.34#ibcon#first serial, iclass 33, count 2 2006.201.23:03:53.34#ibcon#enter sib2, iclass 33, count 2 2006.201.23:03:53.34#ibcon#flushed, iclass 33, count 2 2006.201.23:03:53.34#ibcon#about to write, iclass 33, count 2 2006.201.23:03:53.34#ibcon#wrote, iclass 33, count 2 2006.201.23:03:53.34#ibcon#about to read 3, iclass 33, count 2 2006.201.23:03:53.36#ibcon#read 3, iclass 33, count 2 2006.201.23:03:53.36#ibcon#about to read 4, iclass 33, count 2 2006.201.23:03:53.36#ibcon#read 4, iclass 33, count 2 2006.201.23:03:53.36#ibcon#about to read 5, iclass 33, count 2 2006.201.23:03:53.36#ibcon#read 5, iclass 33, count 2 2006.201.23:03:53.36#ibcon#about to read 6, iclass 33, count 2 2006.201.23:03:53.36#ibcon#read 6, iclass 33, count 2 2006.201.23:03:53.36#ibcon#end of sib2, iclass 33, count 2 2006.201.23:03:53.36#ibcon#*mode == 0, iclass 33, count 2 2006.201.23:03:53.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.23:03:53.36#ibcon#[25=AT05-04\r\n] 2006.201.23:03:53.36#ibcon#*before write, iclass 33, count 2 2006.201.23:03:53.36#ibcon#enter sib2, iclass 33, count 2 2006.201.23:03:53.36#ibcon#flushed, iclass 33, count 2 2006.201.23:03:53.36#ibcon#about to write, iclass 33, count 2 2006.201.23:03:53.36#ibcon#wrote, iclass 33, count 2 2006.201.23:03:53.36#ibcon#about to read 3, iclass 33, count 2 2006.201.23:03:53.39#ibcon#read 3, iclass 33, count 2 2006.201.23:03:53.39#ibcon#about to read 4, iclass 33, count 2 2006.201.23:03:53.39#ibcon#read 4, iclass 33, count 2 2006.201.23:03:53.39#ibcon#about to read 5, iclass 33, count 2 2006.201.23:03:53.39#ibcon#read 5, iclass 33, count 2 2006.201.23:03:53.39#ibcon#about to read 6, iclass 33, count 2 2006.201.23:03:53.39#ibcon#read 6, iclass 33, count 2 2006.201.23:03:53.39#ibcon#end of sib2, iclass 33, count 2 2006.201.23:03:53.39#ibcon#*after write, iclass 33, count 2 2006.201.23:03:53.39#ibcon#*before return 0, iclass 33, count 2 2006.201.23:03:53.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:53.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:53.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.23:03:53.39#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:53.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:53.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:53.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:53.51#ibcon#enter wrdev, iclass 33, count 0 2006.201.23:03:53.51#ibcon#first serial, iclass 33, count 0 2006.201.23:03:53.51#ibcon#enter sib2, iclass 33, count 0 2006.201.23:03:53.51#ibcon#flushed, iclass 33, count 0 2006.201.23:03:53.51#ibcon#about to write, iclass 33, count 0 2006.201.23:03:53.51#ibcon#wrote, iclass 33, count 0 2006.201.23:03:53.51#ibcon#about to read 3, iclass 33, count 0 2006.201.23:03:53.53#ibcon#read 3, iclass 33, count 0 2006.201.23:03:53.53#ibcon#about to read 4, iclass 33, count 0 2006.201.23:03:53.53#ibcon#read 4, iclass 33, count 0 2006.201.23:03:53.53#ibcon#about to read 5, iclass 33, count 0 2006.201.23:03:53.53#ibcon#read 5, iclass 33, count 0 2006.201.23:03:53.53#ibcon#about to read 6, iclass 33, count 0 2006.201.23:03:53.53#ibcon#read 6, iclass 33, count 0 2006.201.23:03:53.53#ibcon#end of sib2, iclass 33, count 0 2006.201.23:03:53.53#ibcon#*mode == 0, iclass 33, count 0 2006.201.23:03:53.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.23:03:53.53#ibcon#[25=USB\r\n] 2006.201.23:03:53.53#ibcon#*before write, iclass 33, count 0 2006.201.23:03:53.53#ibcon#enter sib2, iclass 33, count 0 2006.201.23:03:53.53#ibcon#flushed, iclass 33, count 0 2006.201.23:03:53.53#ibcon#about to write, iclass 33, count 0 2006.201.23:03:53.53#ibcon#wrote, iclass 33, count 0 2006.201.23:03:53.53#ibcon#about to read 3, iclass 33, count 0 2006.201.23:03:53.56#ibcon#read 3, iclass 33, count 0 2006.201.23:03:53.56#ibcon#about to read 4, iclass 33, count 0 2006.201.23:03:53.56#ibcon#read 4, iclass 33, count 0 2006.201.23:03:53.56#ibcon#about to read 5, iclass 33, count 0 2006.201.23:03:53.56#ibcon#read 5, iclass 33, count 0 2006.201.23:03:53.56#ibcon#about to read 6, iclass 33, count 0 2006.201.23:03:53.56#ibcon#read 6, iclass 33, count 0 2006.201.23:03:53.56#ibcon#end of sib2, iclass 33, count 0 2006.201.23:03:53.56#ibcon#*after write, iclass 33, count 0 2006.201.23:03:53.56#ibcon#*before return 0, iclass 33, count 0 2006.201.23:03:53.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:53.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:53.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.23:03:53.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.23:03:53.56$vck44/valo=6,814.99 2006.201.23:03:53.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.23:03:53.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.23:03:53.56#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:53.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:53.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:53.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:53.56#ibcon#enter wrdev, iclass 35, count 0 2006.201.23:03:53.56#ibcon#first serial, iclass 35, count 0 2006.201.23:03:53.56#ibcon#enter sib2, iclass 35, count 0 2006.201.23:03:53.56#ibcon#flushed, iclass 35, count 0 2006.201.23:03:53.56#ibcon#about to write, iclass 35, count 0 2006.201.23:03:53.56#ibcon#wrote, iclass 35, count 0 2006.201.23:03:53.56#ibcon#about to read 3, iclass 35, count 0 2006.201.23:03:53.58#ibcon#read 3, iclass 35, count 0 2006.201.23:03:53.58#ibcon#about to read 4, iclass 35, count 0 2006.201.23:03:53.58#ibcon#read 4, iclass 35, count 0 2006.201.23:03:53.58#ibcon#about to read 5, iclass 35, count 0 2006.201.23:03:53.58#ibcon#read 5, iclass 35, count 0 2006.201.23:03:53.58#ibcon#about to read 6, iclass 35, count 0 2006.201.23:03:53.58#ibcon#read 6, iclass 35, count 0 2006.201.23:03:53.58#ibcon#end of sib2, iclass 35, count 0 2006.201.23:03:53.58#ibcon#*mode == 0, iclass 35, count 0 2006.201.23:03:53.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.23:03:53.58#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.23:03:53.58#ibcon#*before write, iclass 35, count 0 2006.201.23:03:53.58#ibcon#enter sib2, iclass 35, count 0 2006.201.23:03:53.58#ibcon#flushed, iclass 35, count 0 2006.201.23:03:53.58#ibcon#about to write, iclass 35, count 0 2006.201.23:03:53.58#ibcon#wrote, iclass 35, count 0 2006.201.23:03:53.58#ibcon#about to read 3, iclass 35, count 0 2006.201.23:03:53.63#ibcon#read 3, iclass 35, count 0 2006.201.23:03:53.63#ibcon#about to read 4, iclass 35, count 0 2006.201.23:03:53.63#ibcon#read 4, iclass 35, count 0 2006.201.23:03:53.63#ibcon#about to read 5, iclass 35, count 0 2006.201.23:03:53.63#ibcon#read 5, iclass 35, count 0 2006.201.23:03:53.63#ibcon#about to read 6, iclass 35, count 0 2006.201.23:03:53.63#ibcon#read 6, iclass 35, count 0 2006.201.23:03:53.63#ibcon#end of sib2, iclass 35, count 0 2006.201.23:03:53.63#ibcon#*after write, iclass 35, count 0 2006.201.23:03:53.63#ibcon#*before return 0, iclass 35, count 0 2006.201.23:03:53.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:53.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:53.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.23:03:53.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.23:03:53.63$vck44/va=6,5 2006.201.23:03:53.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.23:03:53.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.23:03:53.63#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:53.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:53.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:53.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:53.68#ibcon#enter wrdev, iclass 37, count 2 2006.201.23:03:53.68#ibcon#first serial, iclass 37, count 2 2006.201.23:03:53.68#ibcon#enter sib2, iclass 37, count 2 2006.201.23:03:53.68#ibcon#flushed, iclass 37, count 2 2006.201.23:03:53.68#ibcon#about to write, iclass 37, count 2 2006.201.23:03:53.68#ibcon#wrote, iclass 37, count 2 2006.201.23:03:53.68#ibcon#about to read 3, iclass 37, count 2 2006.201.23:03:53.70#ibcon#read 3, iclass 37, count 2 2006.201.23:03:53.70#ibcon#about to read 4, iclass 37, count 2 2006.201.23:03:53.70#ibcon#read 4, iclass 37, count 2 2006.201.23:03:53.70#ibcon#about to read 5, iclass 37, count 2 2006.201.23:03:53.70#ibcon#read 5, iclass 37, count 2 2006.201.23:03:53.70#ibcon#about to read 6, iclass 37, count 2 2006.201.23:03:53.70#ibcon#read 6, iclass 37, count 2 2006.201.23:03:53.70#ibcon#end of sib2, iclass 37, count 2 2006.201.23:03:53.70#ibcon#*mode == 0, iclass 37, count 2 2006.201.23:03:53.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.23:03:53.70#ibcon#[25=AT06-05\r\n] 2006.201.23:03:53.70#ibcon#*before write, iclass 37, count 2 2006.201.23:03:53.70#ibcon#enter sib2, iclass 37, count 2 2006.201.23:03:53.70#ibcon#flushed, iclass 37, count 2 2006.201.23:03:53.70#ibcon#about to write, iclass 37, count 2 2006.201.23:03:53.70#ibcon#wrote, iclass 37, count 2 2006.201.23:03:53.70#ibcon#about to read 3, iclass 37, count 2 2006.201.23:03:53.73#ibcon#read 3, iclass 37, count 2 2006.201.23:03:53.73#ibcon#about to read 4, iclass 37, count 2 2006.201.23:03:53.73#ibcon#read 4, iclass 37, count 2 2006.201.23:03:53.73#ibcon#about to read 5, iclass 37, count 2 2006.201.23:03:53.73#ibcon#read 5, iclass 37, count 2 2006.201.23:03:53.73#ibcon#about to read 6, iclass 37, count 2 2006.201.23:03:53.73#ibcon#read 6, iclass 37, count 2 2006.201.23:03:53.73#ibcon#end of sib2, iclass 37, count 2 2006.201.23:03:53.73#ibcon#*after write, iclass 37, count 2 2006.201.23:03:53.73#ibcon#*before return 0, iclass 37, count 2 2006.201.23:03:53.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:53.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:53.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.23:03:53.73#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:53.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:53.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:53.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:53.85#ibcon#enter wrdev, iclass 37, count 0 2006.201.23:03:53.85#ibcon#first serial, iclass 37, count 0 2006.201.23:03:53.85#ibcon#enter sib2, iclass 37, count 0 2006.201.23:03:53.85#ibcon#flushed, iclass 37, count 0 2006.201.23:03:53.85#ibcon#about to write, iclass 37, count 0 2006.201.23:03:53.85#ibcon#wrote, iclass 37, count 0 2006.201.23:03:53.85#ibcon#about to read 3, iclass 37, count 0 2006.201.23:03:53.87#ibcon#read 3, iclass 37, count 0 2006.201.23:03:53.87#ibcon#about to read 4, iclass 37, count 0 2006.201.23:03:53.87#ibcon#read 4, iclass 37, count 0 2006.201.23:03:53.87#ibcon#about to read 5, iclass 37, count 0 2006.201.23:03:53.87#ibcon#read 5, iclass 37, count 0 2006.201.23:03:53.87#ibcon#about to read 6, iclass 37, count 0 2006.201.23:03:53.87#ibcon#read 6, iclass 37, count 0 2006.201.23:03:53.87#ibcon#end of sib2, iclass 37, count 0 2006.201.23:03:53.87#ibcon#*mode == 0, iclass 37, count 0 2006.201.23:03:53.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.23:03:53.87#ibcon#[25=USB\r\n] 2006.201.23:03:53.87#ibcon#*before write, iclass 37, count 0 2006.201.23:03:53.87#ibcon#enter sib2, iclass 37, count 0 2006.201.23:03:53.87#ibcon#flushed, iclass 37, count 0 2006.201.23:03:53.87#ibcon#about to write, iclass 37, count 0 2006.201.23:03:53.87#ibcon#wrote, iclass 37, count 0 2006.201.23:03:53.87#ibcon#about to read 3, iclass 37, count 0 2006.201.23:03:53.90#ibcon#read 3, iclass 37, count 0 2006.201.23:03:53.90#ibcon#about to read 4, iclass 37, count 0 2006.201.23:03:53.90#ibcon#read 4, iclass 37, count 0 2006.201.23:03:53.90#ibcon#about to read 5, iclass 37, count 0 2006.201.23:03:53.90#ibcon#read 5, iclass 37, count 0 2006.201.23:03:53.90#ibcon#about to read 6, iclass 37, count 0 2006.201.23:03:53.90#ibcon#read 6, iclass 37, count 0 2006.201.23:03:53.90#ibcon#end of sib2, iclass 37, count 0 2006.201.23:03:53.90#ibcon#*after write, iclass 37, count 0 2006.201.23:03:53.90#ibcon#*before return 0, iclass 37, count 0 2006.201.23:03:53.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:53.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:53.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.23:03:53.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.23:03:53.90$vck44/valo=7,864.99 2006.201.23:03:53.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.23:03:53.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.23:03:53.90#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:53.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:53.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:53.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:53.90#ibcon#enter wrdev, iclass 39, count 0 2006.201.23:03:53.90#ibcon#first serial, iclass 39, count 0 2006.201.23:03:53.90#ibcon#enter sib2, iclass 39, count 0 2006.201.23:03:53.90#ibcon#flushed, iclass 39, count 0 2006.201.23:03:53.90#ibcon#about to write, iclass 39, count 0 2006.201.23:03:53.90#ibcon#wrote, iclass 39, count 0 2006.201.23:03:53.90#ibcon#about to read 3, iclass 39, count 0 2006.201.23:03:53.92#ibcon#read 3, iclass 39, count 0 2006.201.23:03:53.92#ibcon#about to read 4, iclass 39, count 0 2006.201.23:03:53.92#ibcon#read 4, iclass 39, count 0 2006.201.23:03:53.92#ibcon#about to read 5, iclass 39, count 0 2006.201.23:03:53.92#ibcon#read 5, iclass 39, count 0 2006.201.23:03:53.92#ibcon#about to read 6, iclass 39, count 0 2006.201.23:03:53.92#ibcon#read 6, iclass 39, count 0 2006.201.23:03:53.92#ibcon#end of sib2, iclass 39, count 0 2006.201.23:03:53.92#ibcon#*mode == 0, iclass 39, count 0 2006.201.23:03:53.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.23:03:53.92#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.23:03:53.92#ibcon#*before write, iclass 39, count 0 2006.201.23:03:53.92#ibcon#enter sib2, iclass 39, count 0 2006.201.23:03:53.92#ibcon#flushed, iclass 39, count 0 2006.201.23:03:53.92#ibcon#about to write, iclass 39, count 0 2006.201.23:03:53.92#ibcon#wrote, iclass 39, count 0 2006.201.23:03:53.92#ibcon#about to read 3, iclass 39, count 0 2006.201.23:03:53.96#ibcon#read 3, iclass 39, count 0 2006.201.23:03:53.96#ibcon#about to read 4, iclass 39, count 0 2006.201.23:03:53.96#ibcon#read 4, iclass 39, count 0 2006.201.23:03:53.96#ibcon#about to read 5, iclass 39, count 0 2006.201.23:03:53.96#ibcon#read 5, iclass 39, count 0 2006.201.23:03:53.96#ibcon#about to read 6, iclass 39, count 0 2006.201.23:03:53.96#ibcon#read 6, iclass 39, count 0 2006.201.23:03:53.96#ibcon#end of sib2, iclass 39, count 0 2006.201.23:03:53.96#ibcon#*after write, iclass 39, count 0 2006.201.23:03:53.96#ibcon#*before return 0, iclass 39, count 0 2006.201.23:03:53.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:53.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:53.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.23:03:53.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.23:03:53.96$vck44/va=7,5 2006.201.23:03:53.96#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.23:03:53.96#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.23:03:53.96#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:53.96#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:54.02#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:54.02#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:54.02#ibcon#enter wrdev, iclass 2, count 2 2006.201.23:03:54.02#ibcon#first serial, iclass 2, count 2 2006.201.23:03:54.02#ibcon#enter sib2, iclass 2, count 2 2006.201.23:03:54.02#ibcon#flushed, iclass 2, count 2 2006.201.23:03:54.02#ibcon#about to write, iclass 2, count 2 2006.201.23:03:54.02#ibcon#wrote, iclass 2, count 2 2006.201.23:03:54.02#ibcon#about to read 3, iclass 2, count 2 2006.201.23:03:54.04#ibcon#read 3, iclass 2, count 2 2006.201.23:03:54.04#ibcon#about to read 4, iclass 2, count 2 2006.201.23:03:54.04#ibcon#read 4, iclass 2, count 2 2006.201.23:03:54.04#ibcon#about to read 5, iclass 2, count 2 2006.201.23:03:54.04#ibcon#read 5, iclass 2, count 2 2006.201.23:03:54.04#ibcon#about to read 6, iclass 2, count 2 2006.201.23:03:54.04#ibcon#read 6, iclass 2, count 2 2006.201.23:03:54.04#ibcon#end of sib2, iclass 2, count 2 2006.201.23:03:54.04#ibcon#*mode == 0, iclass 2, count 2 2006.201.23:03:54.04#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.23:03:54.04#ibcon#[25=AT07-05\r\n] 2006.201.23:03:54.04#ibcon#*before write, iclass 2, count 2 2006.201.23:03:54.04#ibcon#enter sib2, iclass 2, count 2 2006.201.23:03:54.04#ibcon#flushed, iclass 2, count 2 2006.201.23:03:54.04#ibcon#about to write, iclass 2, count 2 2006.201.23:03:54.04#ibcon#wrote, iclass 2, count 2 2006.201.23:03:54.04#ibcon#about to read 3, iclass 2, count 2 2006.201.23:03:54.07#ibcon#read 3, iclass 2, count 2 2006.201.23:03:54.07#ibcon#about to read 4, iclass 2, count 2 2006.201.23:03:54.07#ibcon#read 4, iclass 2, count 2 2006.201.23:03:54.07#ibcon#about to read 5, iclass 2, count 2 2006.201.23:03:54.07#ibcon#read 5, iclass 2, count 2 2006.201.23:03:54.07#ibcon#about to read 6, iclass 2, count 2 2006.201.23:03:54.07#ibcon#read 6, iclass 2, count 2 2006.201.23:03:54.07#ibcon#end of sib2, iclass 2, count 2 2006.201.23:03:54.07#ibcon#*after write, iclass 2, count 2 2006.201.23:03:54.07#ibcon#*before return 0, iclass 2, count 2 2006.201.23:03:54.07#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:54.07#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:54.07#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.23:03:54.07#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:54.07#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:54.19#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:54.19#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:54.19#ibcon#enter wrdev, iclass 2, count 0 2006.201.23:03:54.19#ibcon#first serial, iclass 2, count 0 2006.201.23:03:54.19#ibcon#enter sib2, iclass 2, count 0 2006.201.23:03:54.19#ibcon#flushed, iclass 2, count 0 2006.201.23:03:54.19#ibcon#about to write, iclass 2, count 0 2006.201.23:03:54.19#ibcon#wrote, iclass 2, count 0 2006.201.23:03:54.19#ibcon#about to read 3, iclass 2, count 0 2006.201.23:03:54.21#ibcon#read 3, iclass 2, count 0 2006.201.23:03:54.21#ibcon#about to read 4, iclass 2, count 0 2006.201.23:03:54.21#ibcon#read 4, iclass 2, count 0 2006.201.23:03:54.21#ibcon#about to read 5, iclass 2, count 0 2006.201.23:03:54.21#ibcon#read 5, iclass 2, count 0 2006.201.23:03:54.21#ibcon#about to read 6, iclass 2, count 0 2006.201.23:03:54.21#ibcon#read 6, iclass 2, count 0 2006.201.23:03:54.21#ibcon#end of sib2, iclass 2, count 0 2006.201.23:03:54.21#ibcon#*mode == 0, iclass 2, count 0 2006.201.23:03:54.21#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.23:03:54.21#ibcon#[25=USB\r\n] 2006.201.23:03:54.21#ibcon#*before write, iclass 2, count 0 2006.201.23:03:54.21#ibcon#enter sib2, iclass 2, count 0 2006.201.23:03:54.21#ibcon#flushed, iclass 2, count 0 2006.201.23:03:54.21#ibcon#about to write, iclass 2, count 0 2006.201.23:03:54.21#ibcon#wrote, iclass 2, count 0 2006.201.23:03:54.21#ibcon#about to read 3, iclass 2, count 0 2006.201.23:03:54.24#ibcon#read 3, iclass 2, count 0 2006.201.23:03:54.24#ibcon#about to read 4, iclass 2, count 0 2006.201.23:03:54.24#ibcon#read 4, iclass 2, count 0 2006.201.23:03:54.24#ibcon#about to read 5, iclass 2, count 0 2006.201.23:03:54.24#ibcon#read 5, iclass 2, count 0 2006.201.23:03:54.24#ibcon#about to read 6, iclass 2, count 0 2006.201.23:03:54.24#ibcon#read 6, iclass 2, count 0 2006.201.23:03:54.24#ibcon#end of sib2, iclass 2, count 0 2006.201.23:03:54.24#ibcon#*after write, iclass 2, count 0 2006.201.23:03:54.24#ibcon#*before return 0, iclass 2, count 0 2006.201.23:03:54.24#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:54.24#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:54.24#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.23:03:54.24#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.23:03:54.24$vck44/valo=8,884.99 2006.201.23:03:54.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.23:03:54.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.23:03:54.24#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:54.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:54.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:54.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:54.24#ibcon#enter wrdev, iclass 5, count 0 2006.201.23:03:54.24#ibcon#first serial, iclass 5, count 0 2006.201.23:03:54.24#ibcon#enter sib2, iclass 5, count 0 2006.201.23:03:54.24#ibcon#flushed, iclass 5, count 0 2006.201.23:03:54.24#ibcon#about to write, iclass 5, count 0 2006.201.23:03:54.24#ibcon#wrote, iclass 5, count 0 2006.201.23:03:54.24#ibcon#about to read 3, iclass 5, count 0 2006.201.23:03:54.26#ibcon#read 3, iclass 5, count 0 2006.201.23:03:54.26#ibcon#about to read 4, iclass 5, count 0 2006.201.23:03:54.26#ibcon#read 4, iclass 5, count 0 2006.201.23:03:54.26#ibcon#about to read 5, iclass 5, count 0 2006.201.23:03:54.26#ibcon#read 5, iclass 5, count 0 2006.201.23:03:54.26#ibcon#about to read 6, iclass 5, count 0 2006.201.23:03:54.26#ibcon#read 6, iclass 5, count 0 2006.201.23:03:54.26#ibcon#end of sib2, iclass 5, count 0 2006.201.23:03:54.26#ibcon#*mode == 0, iclass 5, count 0 2006.201.23:03:54.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.23:03:54.26#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.23:03:54.26#ibcon#*before write, iclass 5, count 0 2006.201.23:03:54.26#ibcon#enter sib2, iclass 5, count 0 2006.201.23:03:54.26#ibcon#flushed, iclass 5, count 0 2006.201.23:03:54.26#ibcon#about to write, iclass 5, count 0 2006.201.23:03:54.26#ibcon#wrote, iclass 5, count 0 2006.201.23:03:54.26#ibcon#about to read 3, iclass 5, count 0 2006.201.23:03:54.30#ibcon#read 3, iclass 5, count 0 2006.201.23:03:54.30#ibcon#about to read 4, iclass 5, count 0 2006.201.23:03:54.30#ibcon#read 4, iclass 5, count 0 2006.201.23:03:54.30#ibcon#about to read 5, iclass 5, count 0 2006.201.23:03:54.30#ibcon#read 5, iclass 5, count 0 2006.201.23:03:54.30#ibcon#about to read 6, iclass 5, count 0 2006.201.23:03:54.30#ibcon#read 6, iclass 5, count 0 2006.201.23:03:54.30#ibcon#end of sib2, iclass 5, count 0 2006.201.23:03:54.30#ibcon#*after write, iclass 5, count 0 2006.201.23:03:54.30#ibcon#*before return 0, iclass 5, count 0 2006.201.23:03:54.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:54.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:54.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.23:03:54.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.23:03:54.30$vck44/va=8,4 2006.201.23:03:54.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.23:03:54.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.23:03:54.30#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:54.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:03:54.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:03:54.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:03:54.36#ibcon#enter wrdev, iclass 7, count 2 2006.201.23:03:54.36#ibcon#first serial, iclass 7, count 2 2006.201.23:03:54.36#ibcon#enter sib2, iclass 7, count 2 2006.201.23:03:54.36#ibcon#flushed, iclass 7, count 2 2006.201.23:03:54.36#ibcon#about to write, iclass 7, count 2 2006.201.23:03:54.36#ibcon#wrote, iclass 7, count 2 2006.201.23:03:54.36#ibcon#about to read 3, iclass 7, count 2 2006.201.23:03:54.38#ibcon#read 3, iclass 7, count 2 2006.201.23:03:54.38#ibcon#about to read 4, iclass 7, count 2 2006.201.23:03:54.38#ibcon#read 4, iclass 7, count 2 2006.201.23:03:54.38#ibcon#about to read 5, iclass 7, count 2 2006.201.23:03:54.38#ibcon#read 5, iclass 7, count 2 2006.201.23:03:54.38#ibcon#about to read 6, iclass 7, count 2 2006.201.23:03:54.38#ibcon#read 6, iclass 7, count 2 2006.201.23:03:54.38#ibcon#end of sib2, iclass 7, count 2 2006.201.23:03:54.38#ibcon#*mode == 0, iclass 7, count 2 2006.201.23:03:54.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.23:03:54.38#ibcon#[25=AT08-04\r\n] 2006.201.23:03:54.38#ibcon#*before write, iclass 7, count 2 2006.201.23:03:54.38#ibcon#enter sib2, iclass 7, count 2 2006.201.23:03:54.38#ibcon#flushed, iclass 7, count 2 2006.201.23:03:54.38#ibcon#about to write, iclass 7, count 2 2006.201.23:03:54.38#ibcon#wrote, iclass 7, count 2 2006.201.23:03:54.38#ibcon#about to read 3, iclass 7, count 2 2006.201.23:03:54.42#ibcon#read 3, iclass 7, count 2 2006.201.23:03:54.42#ibcon#about to read 4, iclass 7, count 2 2006.201.23:03:54.42#ibcon#read 4, iclass 7, count 2 2006.201.23:03:54.42#ibcon#about to read 5, iclass 7, count 2 2006.201.23:03:54.42#ibcon#read 5, iclass 7, count 2 2006.201.23:03:54.42#ibcon#about to read 6, iclass 7, count 2 2006.201.23:03:54.42#ibcon#read 6, iclass 7, count 2 2006.201.23:03:54.42#ibcon#end of sib2, iclass 7, count 2 2006.201.23:03:54.42#ibcon#*after write, iclass 7, count 2 2006.201.23:03:54.42#ibcon#*before return 0, iclass 7, count 2 2006.201.23:03:54.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:03:54.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:03:54.42#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.23:03:54.42#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:54.42#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:03:54.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:03:54.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:03:54.54#ibcon#enter wrdev, iclass 7, count 0 2006.201.23:03:54.54#ibcon#first serial, iclass 7, count 0 2006.201.23:03:54.54#ibcon#enter sib2, iclass 7, count 0 2006.201.23:03:54.54#ibcon#flushed, iclass 7, count 0 2006.201.23:03:54.54#ibcon#about to write, iclass 7, count 0 2006.201.23:03:54.54#ibcon#wrote, iclass 7, count 0 2006.201.23:03:54.54#ibcon#about to read 3, iclass 7, count 0 2006.201.23:03:54.56#ibcon#read 3, iclass 7, count 0 2006.201.23:03:54.56#ibcon#about to read 4, iclass 7, count 0 2006.201.23:03:54.56#ibcon#read 4, iclass 7, count 0 2006.201.23:03:54.56#ibcon#about to read 5, iclass 7, count 0 2006.201.23:03:54.56#ibcon#read 5, iclass 7, count 0 2006.201.23:03:54.56#ibcon#about to read 6, iclass 7, count 0 2006.201.23:03:54.56#ibcon#read 6, iclass 7, count 0 2006.201.23:03:54.56#ibcon#end of sib2, iclass 7, count 0 2006.201.23:03:54.56#ibcon#*mode == 0, iclass 7, count 0 2006.201.23:03:54.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.23:03:54.56#ibcon#[25=USB\r\n] 2006.201.23:03:54.56#ibcon#*before write, iclass 7, count 0 2006.201.23:03:54.56#ibcon#enter sib2, iclass 7, count 0 2006.201.23:03:54.56#ibcon#flushed, iclass 7, count 0 2006.201.23:03:54.56#ibcon#about to write, iclass 7, count 0 2006.201.23:03:54.56#ibcon#wrote, iclass 7, count 0 2006.201.23:03:54.56#ibcon#about to read 3, iclass 7, count 0 2006.201.23:03:54.59#ibcon#read 3, iclass 7, count 0 2006.201.23:03:54.59#ibcon#about to read 4, iclass 7, count 0 2006.201.23:03:54.59#ibcon#read 4, iclass 7, count 0 2006.201.23:03:54.59#ibcon#about to read 5, iclass 7, count 0 2006.201.23:03:54.59#ibcon#read 5, iclass 7, count 0 2006.201.23:03:54.59#ibcon#about to read 6, iclass 7, count 0 2006.201.23:03:54.59#ibcon#read 6, iclass 7, count 0 2006.201.23:03:54.59#ibcon#end of sib2, iclass 7, count 0 2006.201.23:03:54.59#ibcon#*after write, iclass 7, count 0 2006.201.23:03:54.59#ibcon#*before return 0, iclass 7, count 0 2006.201.23:03:54.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:03:54.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:03:54.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.23:03:54.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.23:03:54.59$vck44/vblo=1,629.99 2006.201.23:03:54.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.23:03:54.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.23:03:54.59#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:54.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:54.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:54.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:54.59#ibcon#enter wrdev, iclass 11, count 0 2006.201.23:03:54.59#ibcon#first serial, iclass 11, count 0 2006.201.23:03:54.59#ibcon#enter sib2, iclass 11, count 0 2006.201.23:03:54.59#ibcon#flushed, iclass 11, count 0 2006.201.23:03:54.59#ibcon#about to write, iclass 11, count 0 2006.201.23:03:54.59#ibcon#wrote, iclass 11, count 0 2006.201.23:03:54.59#ibcon#about to read 3, iclass 11, count 0 2006.201.23:03:54.61#ibcon#read 3, iclass 11, count 0 2006.201.23:03:54.61#ibcon#about to read 4, iclass 11, count 0 2006.201.23:03:54.61#ibcon#read 4, iclass 11, count 0 2006.201.23:03:54.61#ibcon#about to read 5, iclass 11, count 0 2006.201.23:03:54.61#ibcon#read 5, iclass 11, count 0 2006.201.23:03:54.61#ibcon#about to read 6, iclass 11, count 0 2006.201.23:03:54.61#ibcon#read 6, iclass 11, count 0 2006.201.23:03:54.61#ibcon#end of sib2, iclass 11, count 0 2006.201.23:03:54.61#ibcon#*mode == 0, iclass 11, count 0 2006.201.23:03:54.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.23:03:54.61#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.23:03:54.61#ibcon#*before write, iclass 11, count 0 2006.201.23:03:54.61#ibcon#enter sib2, iclass 11, count 0 2006.201.23:03:54.61#ibcon#flushed, iclass 11, count 0 2006.201.23:03:54.61#ibcon#about to write, iclass 11, count 0 2006.201.23:03:54.61#ibcon#wrote, iclass 11, count 0 2006.201.23:03:54.61#ibcon#about to read 3, iclass 11, count 0 2006.201.23:03:54.66#ibcon#read 3, iclass 11, count 0 2006.201.23:03:54.66#ibcon#about to read 4, iclass 11, count 0 2006.201.23:03:54.66#ibcon#read 4, iclass 11, count 0 2006.201.23:03:54.66#ibcon#about to read 5, iclass 11, count 0 2006.201.23:03:54.66#ibcon#read 5, iclass 11, count 0 2006.201.23:03:54.66#ibcon#about to read 6, iclass 11, count 0 2006.201.23:03:54.66#ibcon#read 6, iclass 11, count 0 2006.201.23:03:54.66#ibcon#end of sib2, iclass 11, count 0 2006.201.23:03:54.66#ibcon#*after write, iclass 11, count 0 2006.201.23:03:54.66#ibcon#*before return 0, iclass 11, count 0 2006.201.23:03:54.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:54.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:03:54.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.23:03:54.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.23:03:54.66$vck44/vb=1,4 2006.201.23:03:54.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.23:03:54.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.23:03:54.66#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:54.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:54.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:54.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:54.66#ibcon#enter wrdev, iclass 13, count 2 2006.201.23:03:54.66#ibcon#first serial, iclass 13, count 2 2006.201.23:03:54.66#ibcon#enter sib2, iclass 13, count 2 2006.201.23:03:54.66#ibcon#flushed, iclass 13, count 2 2006.201.23:03:54.66#ibcon#about to write, iclass 13, count 2 2006.201.23:03:54.66#ibcon#wrote, iclass 13, count 2 2006.201.23:03:54.66#ibcon#about to read 3, iclass 13, count 2 2006.201.23:03:54.68#ibcon#read 3, iclass 13, count 2 2006.201.23:03:54.68#ibcon#about to read 4, iclass 13, count 2 2006.201.23:03:54.68#ibcon#read 4, iclass 13, count 2 2006.201.23:03:54.68#ibcon#about to read 5, iclass 13, count 2 2006.201.23:03:54.68#ibcon#read 5, iclass 13, count 2 2006.201.23:03:54.68#ibcon#about to read 6, iclass 13, count 2 2006.201.23:03:54.68#ibcon#read 6, iclass 13, count 2 2006.201.23:03:54.68#ibcon#end of sib2, iclass 13, count 2 2006.201.23:03:54.68#ibcon#*mode == 0, iclass 13, count 2 2006.201.23:03:54.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.23:03:54.68#ibcon#[27=AT01-04\r\n] 2006.201.23:03:54.68#ibcon#*before write, iclass 13, count 2 2006.201.23:03:54.68#ibcon#enter sib2, iclass 13, count 2 2006.201.23:03:54.68#ibcon#flushed, iclass 13, count 2 2006.201.23:03:54.68#ibcon#about to write, iclass 13, count 2 2006.201.23:03:54.68#ibcon#wrote, iclass 13, count 2 2006.201.23:03:54.68#ibcon#about to read 3, iclass 13, count 2 2006.201.23:03:54.71#ibcon#read 3, iclass 13, count 2 2006.201.23:03:54.71#ibcon#about to read 4, iclass 13, count 2 2006.201.23:03:54.71#ibcon#read 4, iclass 13, count 2 2006.201.23:03:54.71#ibcon#about to read 5, iclass 13, count 2 2006.201.23:03:54.71#ibcon#read 5, iclass 13, count 2 2006.201.23:03:54.71#ibcon#about to read 6, iclass 13, count 2 2006.201.23:03:54.71#ibcon#read 6, iclass 13, count 2 2006.201.23:03:54.71#ibcon#end of sib2, iclass 13, count 2 2006.201.23:03:54.71#ibcon#*after write, iclass 13, count 2 2006.201.23:03:54.71#ibcon#*before return 0, iclass 13, count 2 2006.201.23:03:54.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:54.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:03:54.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.23:03:54.71#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:54.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:54.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:54.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:54.83#ibcon#enter wrdev, iclass 13, count 0 2006.201.23:03:54.83#ibcon#first serial, iclass 13, count 0 2006.201.23:03:54.83#ibcon#enter sib2, iclass 13, count 0 2006.201.23:03:54.83#ibcon#flushed, iclass 13, count 0 2006.201.23:03:54.83#ibcon#about to write, iclass 13, count 0 2006.201.23:03:54.83#ibcon#wrote, iclass 13, count 0 2006.201.23:03:54.83#ibcon#about to read 3, iclass 13, count 0 2006.201.23:03:54.85#ibcon#read 3, iclass 13, count 0 2006.201.23:03:54.85#ibcon#about to read 4, iclass 13, count 0 2006.201.23:03:54.85#ibcon#read 4, iclass 13, count 0 2006.201.23:03:54.85#ibcon#about to read 5, iclass 13, count 0 2006.201.23:03:54.85#ibcon#read 5, iclass 13, count 0 2006.201.23:03:54.85#ibcon#about to read 6, iclass 13, count 0 2006.201.23:03:54.85#ibcon#read 6, iclass 13, count 0 2006.201.23:03:54.85#ibcon#end of sib2, iclass 13, count 0 2006.201.23:03:54.85#ibcon#*mode == 0, iclass 13, count 0 2006.201.23:03:54.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.23:03:54.85#ibcon#[27=USB\r\n] 2006.201.23:03:54.85#ibcon#*before write, iclass 13, count 0 2006.201.23:03:54.85#ibcon#enter sib2, iclass 13, count 0 2006.201.23:03:54.85#ibcon#flushed, iclass 13, count 0 2006.201.23:03:54.85#ibcon#about to write, iclass 13, count 0 2006.201.23:03:54.85#ibcon#wrote, iclass 13, count 0 2006.201.23:03:54.85#ibcon#about to read 3, iclass 13, count 0 2006.201.23:03:54.88#ibcon#read 3, iclass 13, count 0 2006.201.23:03:54.88#ibcon#about to read 4, iclass 13, count 0 2006.201.23:03:54.88#ibcon#read 4, iclass 13, count 0 2006.201.23:03:54.88#ibcon#about to read 5, iclass 13, count 0 2006.201.23:03:54.88#ibcon#read 5, iclass 13, count 0 2006.201.23:03:54.88#ibcon#about to read 6, iclass 13, count 0 2006.201.23:03:54.88#ibcon#read 6, iclass 13, count 0 2006.201.23:03:54.88#ibcon#end of sib2, iclass 13, count 0 2006.201.23:03:54.88#ibcon#*after write, iclass 13, count 0 2006.201.23:03:54.88#ibcon#*before return 0, iclass 13, count 0 2006.201.23:03:54.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:54.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:03:54.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.23:03:54.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.23:03:54.88$vck44/vblo=2,634.99 2006.201.23:03:54.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.23:03:54.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.23:03:54.88#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:54.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:54.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:54.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:54.88#ibcon#enter wrdev, iclass 15, count 0 2006.201.23:03:54.88#ibcon#first serial, iclass 15, count 0 2006.201.23:03:54.88#ibcon#enter sib2, iclass 15, count 0 2006.201.23:03:54.88#ibcon#flushed, iclass 15, count 0 2006.201.23:03:54.88#ibcon#about to write, iclass 15, count 0 2006.201.23:03:54.88#ibcon#wrote, iclass 15, count 0 2006.201.23:03:54.88#ibcon#about to read 3, iclass 15, count 0 2006.201.23:03:54.90#ibcon#read 3, iclass 15, count 0 2006.201.23:03:54.90#ibcon#about to read 4, iclass 15, count 0 2006.201.23:03:54.90#ibcon#read 4, iclass 15, count 0 2006.201.23:03:54.90#ibcon#about to read 5, iclass 15, count 0 2006.201.23:03:54.90#ibcon#read 5, iclass 15, count 0 2006.201.23:03:54.90#ibcon#about to read 6, iclass 15, count 0 2006.201.23:03:54.90#ibcon#read 6, iclass 15, count 0 2006.201.23:03:54.90#ibcon#end of sib2, iclass 15, count 0 2006.201.23:03:54.90#ibcon#*mode == 0, iclass 15, count 0 2006.201.23:03:54.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.23:03:54.90#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.23:03:54.90#ibcon#*before write, iclass 15, count 0 2006.201.23:03:54.90#ibcon#enter sib2, iclass 15, count 0 2006.201.23:03:54.90#ibcon#flushed, iclass 15, count 0 2006.201.23:03:54.90#ibcon#about to write, iclass 15, count 0 2006.201.23:03:54.90#ibcon#wrote, iclass 15, count 0 2006.201.23:03:54.90#ibcon#about to read 3, iclass 15, count 0 2006.201.23:03:54.94#ibcon#read 3, iclass 15, count 0 2006.201.23:03:54.94#ibcon#about to read 4, iclass 15, count 0 2006.201.23:03:54.94#ibcon#read 4, iclass 15, count 0 2006.201.23:03:54.94#ibcon#about to read 5, iclass 15, count 0 2006.201.23:03:54.94#ibcon#read 5, iclass 15, count 0 2006.201.23:03:54.94#ibcon#about to read 6, iclass 15, count 0 2006.201.23:03:54.94#ibcon#read 6, iclass 15, count 0 2006.201.23:03:54.94#ibcon#end of sib2, iclass 15, count 0 2006.201.23:03:54.94#ibcon#*after write, iclass 15, count 0 2006.201.23:03:54.94#ibcon#*before return 0, iclass 15, count 0 2006.201.23:03:54.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:54.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:03:54.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.23:03:54.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.23:03:54.94$vck44/vb=2,5 2006.201.23:03:54.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.23:03:54.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.23:03:54.94#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:54.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:55.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:55.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:55.00#ibcon#enter wrdev, iclass 17, count 2 2006.201.23:03:55.00#ibcon#first serial, iclass 17, count 2 2006.201.23:03:55.00#ibcon#enter sib2, iclass 17, count 2 2006.201.23:03:55.00#ibcon#flushed, iclass 17, count 2 2006.201.23:03:55.00#ibcon#about to write, iclass 17, count 2 2006.201.23:03:55.00#ibcon#wrote, iclass 17, count 2 2006.201.23:03:55.00#ibcon#about to read 3, iclass 17, count 2 2006.201.23:03:55.02#ibcon#read 3, iclass 17, count 2 2006.201.23:03:55.02#ibcon#about to read 4, iclass 17, count 2 2006.201.23:03:55.02#ibcon#read 4, iclass 17, count 2 2006.201.23:03:55.02#ibcon#about to read 5, iclass 17, count 2 2006.201.23:03:55.02#ibcon#read 5, iclass 17, count 2 2006.201.23:03:55.02#ibcon#about to read 6, iclass 17, count 2 2006.201.23:03:55.02#ibcon#read 6, iclass 17, count 2 2006.201.23:03:55.02#ibcon#end of sib2, iclass 17, count 2 2006.201.23:03:55.02#ibcon#*mode == 0, iclass 17, count 2 2006.201.23:03:55.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.23:03:55.02#ibcon#[27=AT02-05\r\n] 2006.201.23:03:55.02#ibcon#*before write, iclass 17, count 2 2006.201.23:03:55.02#ibcon#enter sib2, iclass 17, count 2 2006.201.23:03:55.02#ibcon#flushed, iclass 17, count 2 2006.201.23:03:55.02#ibcon#about to write, iclass 17, count 2 2006.201.23:03:55.02#ibcon#wrote, iclass 17, count 2 2006.201.23:03:55.02#ibcon#about to read 3, iclass 17, count 2 2006.201.23:03:55.05#ibcon#read 3, iclass 17, count 2 2006.201.23:03:55.05#ibcon#about to read 4, iclass 17, count 2 2006.201.23:03:55.05#ibcon#read 4, iclass 17, count 2 2006.201.23:03:55.05#ibcon#about to read 5, iclass 17, count 2 2006.201.23:03:55.05#ibcon#read 5, iclass 17, count 2 2006.201.23:03:55.05#ibcon#about to read 6, iclass 17, count 2 2006.201.23:03:55.05#ibcon#read 6, iclass 17, count 2 2006.201.23:03:55.05#ibcon#end of sib2, iclass 17, count 2 2006.201.23:03:55.05#ibcon#*after write, iclass 17, count 2 2006.201.23:03:55.05#ibcon#*before return 0, iclass 17, count 2 2006.201.23:03:55.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:55.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:03:55.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.23:03:55.05#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:55.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:55.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:55.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:55.17#ibcon#enter wrdev, iclass 17, count 0 2006.201.23:03:55.17#ibcon#first serial, iclass 17, count 0 2006.201.23:03:55.17#ibcon#enter sib2, iclass 17, count 0 2006.201.23:03:55.17#ibcon#flushed, iclass 17, count 0 2006.201.23:03:55.17#ibcon#about to write, iclass 17, count 0 2006.201.23:03:55.17#ibcon#wrote, iclass 17, count 0 2006.201.23:03:55.17#ibcon#about to read 3, iclass 17, count 0 2006.201.23:03:55.20#ibcon#read 3, iclass 17, count 0 2006.201.23:03:55.20#ibcon#about to read 4, iclass 17, count 0 2006.201.23:03:55.20#ibcon#read 4, iclass 17, count 0 2006.201.23:03:55.20#ibcon#about to read 5, iclass 17, count 0 2006.201.23:03:55.20#ibcon#read 5, iclass 17, count 0 2006.201.23:03:55.20#ibcon#about to read 6, iclass 17, count 0 2006.201.23:03:55.20#ibcon#read 6, iclass 17, count 0 2006.201.23:03:55.20#ibcon#end of sib2, iclass 17, count 0 2006.201.23:03:55.20#ibcon#*mode == 0, iclass 17, count 0 2006.201.23:03:55.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.23:03:55.20#ibcon#[27=USB\r\n] 2006.201.23:03:55.20#ibcon#*before write, iclass 17, count 0 2006.201.23:03:55.20#ibcon#enter sib2, iclass 17, count 0 2006.201.23:03:55.20#ibcon#flushed, iclass 17, count 0 2006.201.23:03:55.20#ibcon#about to write, iclass 17, count 0 2006.201.23:03:55.20#ibcon#wrote, iclass 17, count 0 2006.201.23:03:55.20#ibcon#about to read 3, iclass 17, count 0 2006.201.23:03:55.23#ibcon#read 3, iclass 17, count 0 2006.201.23:03:55.23#ibcon#about to read 4, iclass 17, count 0 2006.201.23:03:55.23#ibcon#read 4, iclass 17, count 0 2006.201.23:03:55.23#ibcon#about to read 5, iclass 17, count 0 2006.201.23:03:55.23#ibcon#read 5, iclass 17, count 0 2006.201.23:03:55.23#ibcon#about to read 6, iclass 17, count 0 2006.201.23:03:55.23#ibcon#read 6, iclass 17, count 0 2006.201.23:03:55.23#ibcon#end of sib2, iclass 17, count 0 2006.201.23:03:55.23#ibcon#*after write, iclass 17, count 0 2006.201.23:03:55.23#ibcon#*before return 0, iclass 17, count 0 2006.201.23:03:55.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:55.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:03:55.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.23:03:55.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.23:03:55.23$vck44/vblo=3,649.99 2006.201.23:03:55.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.23:03:55.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.23:03:55.23#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:55.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:55.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:55.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:55.23#ibcon#enter wrdev, iclass 19, count 0 2006.201.23:03:55.23#ibcon#first serial, iclass 19, count 0 2006.201.23:03:55.23#ibcon#enter sib2, iclass 19, count 0 2006.201.23:03:55.23#ibcon#flushed, iclass 19, count 0 2006.201.23:03:55.23#ibcon#about to write, iclass 19, count 0 2006.201.23:03:55.23#ibcon#wrote, iclass 19, count 0 2006.201.23:03:55.23#ibcon#about to read 3, iclass 19, count 0 2006.201.23:03:55.25#ibcon#read 3, iclass 19, count 0 2006.201.23:03:55.25#ibcon#about to read 4, iclass 19, count 0 2006.201.23:03:55.25#ibcon#read 4, iclass 19, count 0 2006.201.23:03:55.25#ibcon#about to read 5, iclass 19, count 0 2006.201.23:03:55.25#ibcon#read 5, iclass 19, count 0 2006.201.23:03:55.25#ibcon#about to read 6, iclass 19, count 0 2006.201.23:03:55.25#ibcon#read 6, iclass 19, count 0 2006.201.23:03:55.25#ibcon#end of sib2, iclass 19, count 0 2006.201.23:03:55.25#ibcon#*mode == 0, iclass 19, count 0 2006.201.23:03:55.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.23:03:55.25#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.23:03:55.25#ibcon#*before write, iclass 19, count 0 2006.201.23:03:55.25#ibcon#enter sib2, iclass 19, count 0 2006.201.23:03:55.25#ibcon#flushed, iclass 19, count 0 2006.201.23:03:55.25#ibcon#about to write, iclass 19, count 0 2006.201.23:03:55.25#ibcon#wrote, iclass 19, count 0 2006.201.23:03:55.25#ibcon#about to read 3, iclass 19, count 0 2006.201.23:03:55.29#ibcon#read 3, iclass 19, count 0 2006.201.23:03:55.29#ibcon#about to read 4, iclass 19, count 0 2006.201.23:03:55.29#ibcon#read 4, iclass 19, count 0 2006.201.23:03:55.29#ibcon#about to read 5, iclass 19, count 0 2006.201.23:03:55.29#ibcon#read 5, iclass 19, count 0 2006.201.23:03:55.29#ibcon#about to read 6, iclass 19, count 0 2006.201.23:03:55.29#ibcon#read 6, iclass 19, count 0 2006.201.23:03:55.29#ibcon#end of sib2, iclass 19, count 0 2006.201.23:03:55.29#ibcon#*after write, iclass 19, count 0 2006.201.23:03:55.29#ibcon#*before return 0, iclass 19, count 0 2006.201.23:03:55.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:55.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:03:55.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.23:03:55.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.23:03:55.29$vck44/vb=3,4 2006.201.23:03:55.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.23:03:55.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.23:03:55.29#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:55.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:55.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:55.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:55.35#ibcon#enter wrdev, iclass 21, count 2 2006.201.23:03:55.35#ibcon#first serial, iclass 21, count 2 2006.201.23:03:55.35#ibcon#enter sib2, iclass 21, count 2 2006.201.23:03:55.35#ibcon#flushed, iclass 21, count 2 2006.201.23:03:55.35#ibcon#about to write, iclass 21, count 2 2006.201.23:03:55.35#ibcon#wrote, iclass 21, count 2 2006.201.23:03:55.35#ibcon#about to read 3, iclass 21, count 2 2006.201.23:03:55.37#ibcon#read 3, iclass 21, count 2 2006.201.23:03:55.37#ibcon#about to read 4, iclass 21, count 2 2006.201.23:03:55.37#ibcon#read 4, iclass 21, count 2 2006.201.23:03:55.37#ibcon#about to read 5, iclass 21, count 2 2006.201.23:03:55.37#ibcon#read 5, iclass 21, count 2 2006.201.23:03:55.37#ibcon#about to read 6, iclass 21, count 2 2006.201.23:03:55.37#ibcon#read 6, iclass 21, count 2 2006.201.23:03:55.37#ibcon#end of sib2, iclass 21, count 2 2006.201.23:03:55.37#ibcon#*mode == 0, iclass 21, count 2 2006.201.23:03:55.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.23:03:55.37#ibcon#[27=AT03-04\r\n] 2006.201.23:03:55.37#ibcon#*before write, iclass 21, count 2 2006.201.23:03:55.37#ibcon#enter sib2, iclass 21, count 2 2006.201.23:03:55.37#ibcon#flushed, iclass 21, count 2 2006.201.23:03:55.37#ibcon#about to write, iclass 21, count 2 2006.201.23:03:55.37#ibcon#wrote, iclass 21, count 2 2006.201.23:03:55.37#ibcon#about to read 3, iclass 21, count 2 2006.201.23:03:55.40#ibcon#read 3, iclass 21, count 2 2006.201.23:03:55.40#ibcon#about to read 4, iclass 21, count 2 2006.201.23:03:55.40#ibcon#read 4, iclass 21, count 2 2006.201.23:03:55.40#ibcon#about to read 5, iclass 21, count 2 2006.201.23:03:55.40#ibcon#read 5, iclass 21, count 2 2006.201.23:03:55.40#ibcon#about to read 6, iclass 21, count 2 2006.201.23:03:55.40#ibcon#read 6, iclass 21, count 2 2006.201.23:03:55.40#ibcon#end of sib2, iclass 21, count 2 2006.201.23:03:55.40#ibcon#*after write, iclass 21, count 2 2006.201.23:03:55.40#ibcon#*before return 0, iclass 21, count 2 2006.201.23:03:55.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:55.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:03:55.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.23:03:55.40#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:55.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:55.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:55.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:55.52#ibcon#enter wrdev, iclass 21, count 0 2006.201.23:03:55.52#ibcon#first serial, iclass 21, count 0 2006.201.23:03:55.52#ibcon#enter sib2, iclass 21, count 0 2006.201.23:03:55.52#ibcon#flushed, iclass 21, count 0 2006.201.23:03:55.52#ibcon#about to write, iclass 21, count 0 2006.201.23:03:55.52#ibcon#wrote, iclass 21, count 0 2006.201.23:03:55.52#ibcon#about to read 3, iclass 21, count 0 2006.201.23:03:55.54#ibcon#read 3, iclass 21, count 0 2006.201.23:03:55.54#ibcon#about to read 4, iclass 21, count 0 2006.201.23:03:55.54#ibcon#read 4, iclass 21, count 0 2006.201.23:03:55.54#ibcon#about to read 5, iclass 21, count 0 2006.201.23:03:55.54#ibcon#read 5, iclass 21, count 0 2006.201.23:03:55.54#ibcon#about to read 6, iclass 21, count 0 2006.201.23:03:55.54#ibcon#read 6, iclass 21, count 0 2006.201.23:03:55.54#ibcon#end of sib2, iclass 21, count 0 2006.201.23:03:55.54#ibcon#*mode == 0, iclass 21, count 0 2006.201.23:03:55.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.23:03:55.54#ibcon#[27=USB\r\n] 2006.201.23:03:55.54#ibcon#*before write, iclass 21, count 0 2006.201.23:03:55.54#ibcon#enter sib2, iclass 21, count 0 2006.201.23:03:55.54#ibcon#flushed, iclass 21, count 0 2006.201.23:03:55.54#ibcon#about to write, iclass 21, count 0 2006.201.23:03:55.54#ibcon#wrote, iclass 21, count 0 2006.201.23:03:55.54#ibcon#about to read 3, iclass 21, count 0 2006.201.23:03:55.57#ibcon#read 3, iclass 21, count 0 2006.201.23:03:55.57#ibcon#about to read 4, iclass 21, count 0 2006.201.23:03:55.57#ibcon#read 4, iclass 21, count 0 2006.201.23:03:55.57#ibcon#about to read 5, iclass 21, count 0 2006.201.23:03:55.57#ibcon#read 5, iclass 21, count 0 2006.201.23:03:55.57#ibcon#about to read 6, iclass 21, count 0 2006.201.23:03:55.57#ibcon#read 6, iclass 21, count 0 2006.201.23:03:55.57#ibcon#end of sib2, iclass 21, count 0 2006.201.23:03:55.57#ibcon#*after write, iclass 21, count 0 2006.201.23:03:55.57#ibcon#*before return 0, iclass 21, count 0 2006.201.23:03:55.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:55.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:03:55.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.23:03:55.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.23:03:55.57$vck44/vblo=4,679.99 2006.201.23:03:55.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.23:03:55.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.23:03:55.57#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:55.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:03:55.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:03:55.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:03:55.57#ibcon#enter wrdev, iclass 23, count 0 2006.201.23:03:55.57#ibcon#first serial, iclass 23, count 0 2006.201.23:03:55.57#ibcon#enter sib2, iclass 23, count 0 2006.201.23:03:55.57#ibcon#flushed, iclass 23, count 0 2006.201.23:03:55.57#ibcon#about to write, iclass 23, count 0 2006.201.23:03:55.57#ibcon#wrote, iclass 23, count 0 2006.201.23:03:55.57#ibcon#about to read 3, iclass 23, count 0 2006.201.23:03:55.59#ibcon#read 3, iclass 23, count 0 2006.201.23:03:55.59#ibcon#about to read 4, iclass 23, count 0 2006.201.23:03:55.59#ibcon#read 4, iclass 23, count 0 2006.201.23:03:55.59#ibcon#about to read 5, iclass 23, count 0 2006.201.23:03:55.59#ibcon#read 5, iclass 23, count 0 2006.201.23:03:55.59#ibcon#about to read 6, iclass 23, count 0 2006.201.23:03:55.59#ibcon#read 6, iclass 23, count 0 2006.201.23:03:55.59#ibcon#end of sib2, iclass 23, count 0 2006.201.23:03:55.59#ibcon#*mode == 0, iclass 23, count 0 2006.201.23:03:55.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.23:03:55.59#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.23:03:55.59#ibcon#*before write, iclass 23, count 0 2006.201.23:03:55.59#ibcon#enter sib2, iclass 23, count 0 2006.201.23:03:55.59#ibcon#flushed, iclass 23, count 0 2006.201.23:03:55.59#ibcon#about to write, iclass 23, count 0 2006.201.23:03:55.59#ibcon#wrote, iclass 23, count 0 2006.201.23:03:55.59#ibcon#about to read 3, iclass 23, count 0 2006.201.23:03:55.63#ibcon#read 3, iclass 23, count 0 2006.201.23:03:55.63#ibcon#about to read 4, iclass 23, count 0 2006.201.23:03:55.63#ibcon#read 4, iclass 23, count 0 2006.201.23:03:55.63#ibcon#about to read 5, iclass 23, count 0 2006.201.23:03:55.63#ibcon#read 5, iclass 23, count 0 2006.201.23:03:55.63#ibcon#about to read 6, iclass 23, count 0 2006.201.23:03:55.63#ibcon#read 6, iclass 23, count 0 2006.201.23:03:55.63#ibcon#end of sib2, iclass 23, count 0 2006.201.23:03:55.63#ibcon#*after write, iclass 23, count 0 2006.201.23:03:55.63#ibcon#*before return 0, iclass 23, count 0 2006.201.23:03:55.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:03:55.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:03:55.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.23:03:55.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.23:03:55.63$vck44/vb=4,5 2006.201.23:03:55.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.23:03:55.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.23:03:55.63#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:55.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:03:55.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:03:55.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:03:55.69#ibcon#enter wrdev, iclass 25, count 2 2006.201.23:03:55.69#ibcon#first serial, iclass 25, count 2 2006.201.23:03:55.69#ibcon#enter sib2, iclass 25, count 2 2006.201.23:03:55.69#ibcon#flushed, iclass 25, count 2 2006.201.23:03:55.69#ibcon#about to write, iclass 25, count 2 2006.201.23:03:55.69#ibcon#wrote, iclass 25, count 2 2006.201.23:03:55.69#ibcon#about to read 3, iclass 25, count 2 2006.201.23:03:55.71#ibcon#read 3, iclass 25, count 2 2006.201.23:03:55.71#ibcon#about to read 4, iclass 25, count 2 2006.201.23:03:55.71#ibcon#read 4, iclass 25, count 2 2006.201.23:03:55.71#ibcon#about to read 5, iclass 25, count 2 2006.201.23:03:55.71#ibcon#read 5, iclass 25, count 2 2006.201.23:03:55.71#ibcon#about to read 6, iclass 25, count 2 2006.201.23:03:55.71#ibcon#read 6, iclass 25, count 2 2006.201.23:03:55.71#ibcon#end of sib2, iclass 25, count 2 2006.201.23:03:55.71#ibcon#*mode == 0, iclass 25, count 2 2006.201.23:03:55.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.23:03:55.71#ibcon#[27=AT04-05\r\n] 2006.201.23:03:55.71#ibcon#*before write, iclass 25, count 2 2006.201.23:03:55.71#ibcon#enter sib2, iclass 25, count 2 2006.201.23:03:55.71#ibcon#flushed, iclass 25, count 2 2006.201.23:03:55.71#ibcon#about to write, iclass 25, count 2 2006.201.23:03:55.71#ibcon#wrote, iclass 25, count 2 2006.201.23:03:55.71#ibcon#about to read 3, iclass 25, count 2 2006.201.23:03:55.74#ibcon#read 3, iclass 25, count 2 2006.201.23:03:55.74#ibcon#about to read 4, iclass 25, count 2 2006.201.23:03:55.74#ibcon#read 4, iclass 25, count 2 2006.201.23:03:55.74#ibcon#about to read 5, iclass 25, count 2 2006.201.23:03:55.74#ibcon#read 5, iclass 25, count 2 2006.201.23:03:55.74#ibcon#about to read 6, iclass 25, count 2 2006.201.23:03:55.74#ibcon#read 6, iclass 25, count 2 2006.201.23:03:55.74#ibcon#end of sib2, iclass 25, count 2 2006.201.23:03:55.74#ibcon#*after write, iclass 25, count 2 2006.201.23:03:55.74#ibcon#*before return 0, iclass 25, count 2 2006.201.23:03:55.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:03:55.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:03:55.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.23:03:55.74#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:55.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:03:55.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:03:55.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:03:55.86#ibcon#enter wrdev, iclass 25, count 0 2006.201.23:03:55.86#ibcon#first serial, iclass 25, count 0 2006.201.23:03:55.86#ibcon#enter sib2, iclass 25, count 0 2006.201.23:03:55.86#ibcon#flushed, iclass 25, count 0 2006.201.23:03:55.86#ibcon#about to write, iclass 25, count 0 2006.201.23:03:55.86#ibcon#wrote, iclass 25, count 0 2006.201.23:03:55.86#ibcon#about to read 3, iclass 25, count 0 2006.201.23:03:55.88#ibcon#read 3, iclass 25, count 0 2006.201.23:03:55.88#ibcon#about to read 4, iclass 25, count 0 2006.201.23:03:55.88#ibcon#read 4, iclass 25, count 0 2006.201.23:03:55.88#ibcon#about to read 5, iclass 25, count 0 2006.201.23:03:55.88#ibcon#read 5, iclass 25, count 0 2006.201.23:03:55.88#ibcon#about to read 6, iclass 25, count 0 2006.201.23:03:55.88#ibcon#read 6, iclass 25, count 0 2006.201.23:03:55.88#ibcon#end of sib2, iclass 25, count 0 2006.201.23:03:55.88#ibcon#*mode == 0, iclass 25, count 0 2006.201.23:03:55.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.23:03:55.88#ibcon#[27=USB\r\n] 2006.201.23:03:55.88#ibcon#*before write, iclass 25, count 0 2006.201.23:03:55.88#ibcon#enter sib2, iclass 25, count 0 2006.201.23:03:55.88#ibcon#flushed, iclass 25, count 0 2006.201.23:03:55.88#ibcon#about to write, iclass 25, count 0 2006.201.23:03:55.88#ibcon#wrote, iclass 25, count 0 2006.201.23:03:55.88#ibcon#about to read 3, iclass 25, count 0 2006.201.23:03:55.91#ibcon#read 3, iclass 25, count 0 2006.201.23:03:55.91#ibcon#about to read 4, iclass 25, count 0 2006.201.23:03:55.91#ibcon#read 4, iclass 25, count 0 2006.201.23:03:55.91#ibcon#about to read 5, iclass 25, count 0 2006.201.23:03:55.91#ibcon#read 5, iclass 25, count 0 2006.201.23:03:55.91#ibcon#about to read 6, iclass 25, count 0 2006.201.23:03:55.91#ibcon#read 6, iclass 25, count 0 2006.201.23:03:55.91#ibcon#end of sib2, iclass 25, count 0 2006.201.23:03:55.91#ibcon#*after write, iclass 25, count 0 2006.201.23:03:55.91#ibcon#*before return 0, iclass 25, count 0 2006.201.23:03:55.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:03:55.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:03:55.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.23:03:55.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.23:03:55.91$vck44/vblo=5,709.99 2006.201.23:03:55.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.23:03:55.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.23:03:55.91#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:55.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:55.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:55.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:55.91#ibcon#enter wrdev, iclass 27, count 0 2006.201.23:03:55.91#ibcon#first serial, iclass 27, count 0 2006.201.23:03:55.91#ibcon#enter sib2, iclass 27, count 0 2006.201.23:03:55.91#ibcon#flushed, iclass 27, count 0 2006.201.23:03:55.91#ibcon#about to write, iclass 27, count 0 2006.201.23:03:55.91#ibcon#wrote, iclass 27, count 0 2006.201.23:03:55.91#ibcon#about to read 3, iclass 27, count 0 2006.201.23:03:55.93#ibcon#read 3, iclass 27, count 0 2006.201.23:03:55.93#ibcon#about to read 4, iclass 27, count 0 2006.201.23:03:55.93#ibcon#read 4, iclass 27, count 0 2006.201.23:03:55.93#ibcon#about to read 5, iclass 27, count 0 2006.201.23:03:55.93#ibcon#read 5, iclass 27, count 0 2006.201.23:03:55.93#ibcon#about to read 6, iclass 27, count 0 2006.201.23:03:55.93#ibcon#read 6, iclass 27, count 0 2006.201.23:03:55.93#ibcon#end of sib2, iclass 27, count 0 2006.201.23:03:55.93#ibcon#*mode == 0, iclass 27, count 0 2006.201.23:03:55.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.23:03:55.93#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.23:03:55.93#ibcon#*before write, iclass 27, count 0 2006.201.23:03:55.93#ibcon#enter sib2, iclass 27, count 0 2006.201.23:03:55.93#ibcon#flushed, iclass 27, count 0 2006.201.23:03:55.93#ibcon#about to write, iclass 27, count 0 2006.201.23:03:55.93#ibcon#wrote, iclass 27, count 0 2006.201.23:03:55.93#ibcon#about to read 3, iclass 27, count 0 2006.201.23:03:55.97#ibcon#read 3, iclass 27, count 0 2006.201.23:03:55.97#ibcon#about to read 4, iclass 27, count 0 2006.201.23:03:55.97#ibcon#read 4, iclass 27, count 0 2006.201.23:03:55.97#ibcon#about to read 5, iclass 27, count 0 2006.201.23:03:55.97#ibcon#read 5, iclass 27, count 0 2006.201.23:03:55.97#ibcon#about to read 6, iclass 27, count 0 2006.201.23:03:55.97#ibcon#read 6, iclass 27, count 0 2006.201.23:03:55.97#ibcon#end of sib2, iclass 27, count 0 2006.201.23:03:55.97#ibcon#*after write, iclass 27, count 0 2006.201.23:03:55.97#ibcon#*before return 0, iclass 27, count 0 2006.201.23:03:55.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:55.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:03:55.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.23:03:55.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.23:03:55.97$vck44/vb=5,4 2006.201.23:03:55.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.23:03:55.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.23:03:55.97#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:55.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:56.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:56.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:56.03#ibcon#enter wrdev, iclass 29, count 2 2006.201.23:03:56.03#ibcon#first serial, iclass 29, count 2 2006.201.23:03:56.03#ibcon#enter sib2, iclass 29, count 2 2006.201.23:03:56.03#ibcon#flushed, iclass 29, count 2 2006.201.23:03:56.03#ibcon#about to write, iclass 29, count 2 2006.201.23:03:56.03#ibcon#wrote, iclass 29, count 2 2006.201.23:03:56.03#ibcon#about to read 3, iclass 29, count 2 2006.201.23:03:56.05#ibcon#read 3, iclass 29, count 2 2006.201.23:03:56.05#ibcon#about to read 4, iclass 29, count 2 2006.201.23:03:56.05#ibcon#read 4, iclass 29, count 2 2006.201.23:03:56.05#ibcon#about to read 5, iclass 29, count 2 2006.201.23:03:56.05#ibcon#read 5, iclass 29, count 2 2006.201.23:03:56.05#ibcon#about to read 6, iclass 29, count 2 2006.201.23:03:56.05#ibcon#read 6, iclass 29, count 2 2006.201.23:03:56.05#ibcon#end of sib2, iclass 29, count 2 2006.201.23:03:56.05#ibcon#*mode == 0, iclass 29, count 2 2006.201.23:03:56.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.23:03:56.05#ibcon#[27=AT05-04\r\n] 2006.201.23:03:56.05#ibcon#*before write, iclass 29, count 2 2006.201.23:03:56.05#ibcon#enter sib2, iclass 29, count 2 2006.201.23:03:56.05#ibcon#flushed, iclass 29, count 2 2006.201.23:03:56.05#ibcon#about to write, iclass 29, count 2 2006.201.23:03:56.05#ibcon#wrote, iclass 29, count 2 2006.201.23:03:56.05#ibcon#about to read 3, iclass 29, count 2 2006.201.23:03:56.08#ibcon#read 3, iclass 29, count 2 2006.201.23:03:56.08#ibcon#about to read 4, iclass 29, count 2 2006.201.23:03:56.08#ibcon#read 4, iclass 29, count 2 2006.201.23:03:56.08#ibcon#about to read 5, iclass 29, count 2 2006.201.23:03:56.08#ibcon#read 5, iclass 29, count 2 2006.201.23:03:56.08#ibcon#about to read 6, iclass 29, count 2 2006.201.23:03:56.08#ibcon#read 6, iclass 29, count 2 2006.201.23:03:56.08#ibcon#end of sib2, iclass 29, count 2 2006.201.23:03:56.08#ibcon#*after write, iclass 29, count 2 2006.201.23:03:56.08#ibcon#*before return 0, iclass 29, count 2 2006.201.23:03:56.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:56.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:03:56.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.23:03:56.08#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:56.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:56.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:56.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:56.20#ibcon#enter wrdev, iclass 29, count 0 2006.201.23:03:56.20#ibcon#first serial, iclass 29, count 0 2006.201.23:03:56.20#ibcon#enter sib2, iclass 29, count 0 2006.201.23:03:56.20#ibcon#flushed, iclass 29, count 0 2006.201.23:03:56.20#ibcon#about to write, iclass 29, count 0 2006.201.23:03:56.20#ibcon#wrote, iclass 29, count 0 2006.201.23:03:56.20#ibcon#about to read 3, iclass 29, count 0 2006.201.23:03:56.23#ibcon#read 3, iclass 29, count 0 2006.201.23:03:56.23#ibcon#about to read 4, iclass 29, count 0 2006.201.23:03:56.23#ibcon#read 4, iclass 29, count 0 2006.201.23:03:56.23#ibcon#about to read 5, iclass 29, count 0 2006.201.23:03:56.23#ibcon#read 5, iclass 29, count 0 2006.201.23:03:56.23#ibcon#about to read 6, iclass 29, count 0 2006.201.23:03:56.23#ibcon#read 6, iclass 29, count 0 2006.201.23:03:56.23#ibcon#end of sib2, iclass 29, count 0 2006.201.23:03:56.23#ibcon#*mode == 0, iclass 29, count 0 2006.201.23:03:56.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.23:03:56.23#ibcon#[27=USB\r\n] 2006.201.23:03:56.23#ibcon#*before write, iclass 29, count 0 2006.201.23:03:56.23#ibcon#enter sib2, iclass 29, count 0 2006.201.23:03:56.23#ibcon#flushed, iclass 29, count 0 2006.201.23:03:56.23#ibcon#about to write, iclass 29, count 0 2006.201.23:03:56.23#ibcon#wrote, iclass 29, count 0 2006.201.23:03:56.23#ibcon#about to read 3, iclass 29, count 0 2006.201.23:03:56.26#ibcon#read 3, iclass 29, count 0 2006.201.23:03:56.26#ibcon#about to read 4, iclass 29, count 0 2006.201.23:03:56.26#ibcon#read 4, iclass 29, count 0 2006.201.23:03:56.26#ibcon#about to read 5, iclass 29, count 0 2006.201.23:03:56.26#ibcon#read 5, iclass 29, count 0 2006.201.23:03:56.26#ibcon#about to read 6, iclass 29, count 0 2006.201.23:03:56.26#ibcon#read 6, iclass 29, count 0 2006.201.23:03:56.26#ibcon#end of sib2, iclass 29, count 0 2006.201.23:03:56.26#ibcon#*after write, iclass 29, count 0 2006.201.23:03:56.26#ibcon#*before return 0, iclass 29, count 0 2006.201.23:03:56.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:56.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:03:56.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.23:03:56.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.23:03:56.26$vck44/vblo=6,719.99 2006.201.23:03:56.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.23:03:56.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.23:03:56.26#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:56.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:56.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:56.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:56.26#ibcon#enter wrdev, iclass 31, count 0 2006.201.23:03:56.26#ibcon#first serial, iclass 31, count 0 2006.201.23:03:56.26#ibcon#enter sib2, iclass 31, count 0 2006.201.23:03:56.26#ibcon#flushed, iclass 31, count 0 2006.201.23:03:56.26#ibcon#about to write, iclass 31, count 0 2006.201.23:03:56.26#ibcon#wrote, iclass 31, count 0 2006.201.23:03:56.26#ibcon#about to read 3, iclass 31, count 0 2006.201.23:03:56.28#ibcon#read 3, iclass 31, count 0 2006.201.23:03:56.28#ibcon#about to read 4, iclass 31, count 0 2006.201.23:03:56.28#ibcon#read 4, iclass 31, count 0 2006.201.23:03:56.28#ibcon#about to read 5, iclass 31, count 0 2006.201.23:03:56.28#ibcon#read 5, iclass 31, count 0 2006.201.23:03:56.28#ibcon#about to read 6, iclass 31, count 0 2006.201.23:03:56.28#ibcon#read 6, iclass 31, count 0 2006.201.23:03:56.28#ibcon#end of sib2, iclass 31, count 0 2006.201.23:03:56.28#ibcon#*mode == 0, iclass 31, count 0 2006.201.23:03:56.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.23:03:56.28#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.23:03:56.28#ibcon#*before write, iclass 31, count 0 2006.201.23:03:56.28#ibcon#enter sib2, iclass 31, count 0 2006.201.23:03:56.28#ibcon#flushed, iclass 31, count 0 2006.201.23:03:56.28#ibcon#about to write, iclass 31, count 0 2006.201.23:03:56.28#ibcon#wrote, iclass 31, count 0 2006.201.23:03:56.28#ibcon#about to read 3, iclass 31, count 0 2006.201.23:03:56.32#ibcon#read 3, iclass 31, count 0 2006.201.23:03:56.32#ibcon#about to read 4, iclass 31, count 0 2006.201.23:03:56.32#ibcon#read 4, iclass 31, count 0 2006.201.23:03:56.32#ibcon#about to read 5, iclass 31, count 0 2006.201.23:03:56.32#ibcon#read 5, iclass 31, count 0 2006.201.23:03:56.32#ibcon#about to read 6, iclass 31, count 0 2006.201.23:03:56.32#ibcon#read 6, iclass 31, count 0 2006.201.23:03:56.32#ibcon#end of sib2, iclass 31, count 0 2006.201.23:03:56.32#ibcon#*after write, iclass 31, count 0 2006.201.23:03:56.32#ibcon#*before return 0, iclass 31, count 0 2006.201.23:03:56.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:56.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:03:56.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.23:03:56.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.23:03:56.32$vck44/vb=6,4 2006.201.23:03:56.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.23:03:56.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.23:03:56.32#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:56.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:56.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:56.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:56.38#ibcon#enter wrdev, iclass 33, count 2 2006.201.23:03:56.38#ibcon#first serial, iclass 33, count 2 2006.201.23:03:56.38#ibcon#enter sib2, iclass 33, count 2 2006.201.23:03:56.38#ibcon#flushed, iclass 33, count 2 2006.201.23:03:56.38#ibcon#about to write, iclass 33, count 2 2006.201.23:03:56.38#ibcon#wrote, iclass 33, count 2 2006.201.23:03:56.38#ibcon#about to read 3, iclass 33, count 2 2006.201.23:03:56.40#ibcon#read 3, iclass 33, count 2 2006.201.23:03:56.40#ibcon#about to read 4, iclass 33, count 2 2006.201.23:03:56.40#ibcon#read 4, iclass 33, count 2 2006.201.23:03:56.40#ibcon#about to read 5, iclass 33, count 2 2006.201.23:03:56.40#ibcon#read 5, iclass 33, count 2 2006.201.23:03:56.40#ibcon#about to read 6, iclass 33, count 2 2006.201.23:03:56.40#ibcon#read 6, iclass 33, count 2 2006.201.23:03:56.40#ibcon#end of sib2, iclass 33, count 2 2006.201.23:03:56.40#ibcon#*mode == 0, iclass 33, count 2 2006.201.23:03:56.40#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.23:03:56.40#ibcon#[27=AT06-04\r\n] 2006.201.23:03:56.40#ibcon#*before write, iclass 33, count 2 2006.201.23:03:56.40#ibcon#enter sib2, iclass 33, count 2 2006.201.23:03:56.40#ibcon#flushed, iclass 33, count 2 2006.201.23:03:56.40#ibcon#about to write, iclass 33, count 2 2006.201.23:03:56.40#ibcon#wrote, iclass 33, count 2 2006.201.23:03:56.40#ibcon#about to read 3, iclass 33, count 2 2006.201.23:03:56.43#ibcon#read 3, iclass 33, count 2 2006.201.23:03:56.43#ibcon#about to read 4, iclass 33, count 2 2006.201.23:03:56.43#ibcon#read 4, iclass 33, count 2 2006.201.23:03:56.43#ibcon#about to read 5, iclass 33, count 2 2006.201.23:03:56.43#ibcon#read 5, iclass 33, count 2 2006.201.23:03:56.43#ibcon#about to read 6, iclass 33, count 2 2006.201.23:03:56.43#ibcon#read 6, iclass 33, count 2 2006.201.23:03:56.43#ibcon#end of sib2, iclass 33, count 2 2006.201.23:03:56.43#ibcon#*after write, iclass 33, count 2 2006.201.23:03:56.43#ibcon#*before return 0, iclass 33, count 2 2006.201.23:03:56.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:56.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:03:56.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.23:03:56.43#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:56.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:56.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:56.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:56.55#ibcon#enter wrdev, iclass 33, count 0 2006.201.23:03:56.55#ibcon#first serial, iclass 33, count 0 2006.201.23:03:56.55#ibcon#enter sib2, iclass 33, count 0 2006.201.23:03:56.55#ibcon#flushed, iclass 33, count 0 2006.201.23:03:56.55#ibcon#about to write, iclass 33, count 0 2006.201.23:03:56.55#ibcon#wrote, iclass 33, count 0 2006.201.23:03:56.55#ibcon#about to read 3, iclass 33, count 0 2006.201.23:03:56.57#ibcon#read 3, iclass 33, count 0 2006.201.23:03:56.57#ibcon#about to read 4, iclass 33, count 0 2006.201.23:03:56.57#ibcon#read 4, iclass 33, count 0 2006.201.23:03:56.57#ibcon#about to read 5, iclass 33, count 0 2006.201.23:03:56.57#ibcon#read 5, iclass 33, count 0 2006.201.23:03:56.57#ibcon#about to read 6, iclass 33, count 0 2006.201.23:03:56.57#ibcon#read 6, iclass 33, count 0 2006.201.23:03:56.57#ibcon#end of sib2, iclass 33, count 0 2006.201.23:03:56.57#ibcon#*mode == 0, iclass 33, count 0 2006.201.23:03:56.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.23:03:56.57#ibcon#[27=USB\r\n] 2006.201.23:03:56.57#ibcon#*before write, iclass 33, count 0 2006.201.23:03:56.57#ibcon#enter sib2, iclass 33, count 0 2006.201.23:03:56.57#ibcon#flushed, iclass 33, count 0 2006.201.23:03:56.57#ibcon#about to write, iclass 33, count 0 2006.201.23:03:56.57#ibcon#wrote, iclass 33, count 0 2006.201.23:03:56.57#ibcon#about to read 3, iclass 33, count 0 2006.201.23:03:56.60#ibcon#read 3, iclass 33, count 0 2006.201.23:03:56.60#ibcon#about to read 4, iclass 33, count 0 2006.201.23:03:56.60#ibcon#read 4, iclass 33, count 0 2006.201.23:03:56.60#ibcon#about to read 5, iclass 33, count 0 2006.201.23:03:56.60#ibcon#read 5, iclass 33, count 0 2006.201.23:03:56.60#ibcon#about to read 6, iclass 33, count 0 2006.201.23:03:56.60#ibcon#read 6, iclass 33, count 0 2006.201.23:03:56.60#ibcon#end of sib2, iclass 33, count 0 2006.201.23:03:56.60#ibcon#*after write, iclass 33, count 0 2006.201.23:03:56.60#ibcon#*before return 0, iclass 33, count 0 2006.201.23:03:56.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:56.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:03:56.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.23:03:56.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.23:03:56.60$vck44/vblo=7,734.99 2006.201.23:03:56.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.23:03:56.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.23:03:56.60#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:56.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:56.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:56.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:56.60#ibcon#enter wrdev, iclass 35, count 0 2006.201.23:03:56.60#ibcon#first serial, iclass 35, count 0 2006.201.23:03:56.60#ibcon#enter sib2, iclass 35, count 0 2006.201.23:03:56.60#ibcon#flushed, iclass 35, count 0 2006.201.23:03:56.60#ibcon#about to write, iclass 35, count 0 2006.201.23:03:56.60#ibcon#wrote, iclass 35, count 0 2006.201.23:03:56.60#ibcon#about to read 3, iclass 35, count 0 2006.201.23:03:56.62#ibcon#read 3, iclass 35, count 0 2006.201.23:03:56.62#ibcon#about to read 4, iclass 35, count 0 2006.201.23:03:56.62#ibcon#read 4, iclass 35, count 0 2006.201.23:03:56.62#ibcon#about to read 5, iclass 35, count 0 2006.201.23:03:56.62#ibcon#read 5, iclass 35, count 0 2006.201.23:03:56.62#ibcon#about to read 6, iclass 35, count 0 2006.201.23:03:56.62#ibcon#read 6, iclass 35, count 0 2006.201.23:03:56.62#ibcon#end of sib2, iclass 35, count 0 2006.201.23:03:56.62#ibcon#*mode == 0, iclass 35, count 0 2006.201.23:03:56.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.23:03:56.62#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.23:03:56.62#ibcon#*before write, iclass 35, count 0 2006.201.23:03:56.62#ibcon#enter sib2, iclass 35, count 0 2006.201.23:03:56.62#ibcon#flushed, iclass 35, count 0 2006.201.23:03:56.62#ibcon#about to write, iclass 35, count 0 2006.201.23:03:56.62#ibcon#wrote, iclass 35, count 0 2006.201.23:03:56.62#ibcon#about to read 3, iclass 35, count 0 2006.201.23:03:56.66#ibcon#read 3, iclass 35, count 0 2006.201.23:03:56.66#ibcon#about to read 4, iclass 35, count 0 2006.201.23:03:56.66#ibcon#read 4, iclass 35, count 0 2006.201.23:03:56.66#ibcon#about to read 5, iclass 35, count 0 2006.201.23:03:56.66#ibcon#read 5, iclass 35, count 0 2006.201.23:03:56.66#ibcon#about to read 6, iclass 35, count 0 2006.201.23:03:56.66#ibcon#read 6, iclass 35, count 0 2006.201.23:03:56.66#ibcon#end of sib2, iclass 35, count 0 2006.201.23:03:56.66#ibcon#*after write, iclass 35, count 0 2006.201.23:03:56.66#ibcon#*before return 0, iclass 35, count 0 2006.201.23:03:56.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:56.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:03:56.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.23:03:56.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.23:03:56.66$vck44/vb=7,4 2006.201.23:03:56.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.23:03:56.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.23:03:56.66#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:56.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:56.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:56.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:56.72#ibcon#enter wrdev, iclass 37, count 2 2006.201.23:03:56.72#ibcon#first serial, iclass 37, count 2 2006.201.23:03:56.72#ibcon#enter sib2, iclass 37, count 2 2006.201.23:03:56.72#ibcon#flushed, iclass 37, count 2 2006.201.23:03:56.72#ibcon#about to write, iclass 37, count 2 2006.201.23:03:56.72#ibcon#wrote, iclass 37, count 2 2006.201.23:03:56.72#ibcon#about to read 3, iclass 37, count 2 2006.201.23:03:56.74#ibcon#read 3, iclass 37, count 2 2006.201.23:03:56.74#ibcon#about to read 4, iclass 37, count 2 2006.201.23:03:56.74#ibcon#read 4, iclass 37, count 2 2006.201.23:03:56.74#ibcon#about to read 5, iclass 37, count 2 2006.201.23:03:56.74#ibcon#read 5, iclass 37, count 2 2006.201.23:03:56.74#ibcon#about to read 6, iclass 37, count 2 2006.201.23:03:56.74#ibcon#read 6, iclass 37, count 2 2006.201.23:03:56.74#ibcon#end of sib2, iclass 37, count 2 2006.201.23:03:56.74#ibcon#*mode == 0, iclass 37, count 2 2006.201.23:03:56.74#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.23:03:56.74#ibcon#[27=AT07-04\r\n] 2006.201.23:03:56.74#ibcon#*before write, iclass 37, count 2 2006.201.23:03:56.74#ibcon#enter sib2, iclass 37, count 2 2006.201.23:03:56.74#ibcon#flushed, iclass 37, count 2 2006.201.23:03:56.74#ibcon#about to write, iclass 37, count 2 2006.201.23:03:56.74#ibcon#wrote, iclass 37, count 2 2006.201.23:03:56.74#ibcon#about to read 3, iclass 37, count 2 2006.201.23:03:56.77#ibcon#read 3, iclass 37, count 2 2006.201.23:03:56.77#ibcon#about to read 4, iclass 37, count 2 2006.201.23:03:56.77#ibcon#read 4, iclass 37, count 2 2006.201.23:03:56.77#ibcon#about to read 5, iclass 37, count 2 2006.201.23:03:56.77#ibcon#read 5, iclass 37, count 2 2006.201.23:03:56.77#ibcon#about to read 6, iclass 37, count 2 2006.201.23:03:56.77#ibcon#read 6, iclass 37, count 2 2006.201.23:03:56.77#ibcon#end of sib2, iclass 37, count 2 2006.201.23:03:56.77#ibcon#*after write, iclass 37, count 2 2006.201.23:03:56.77#ibcon#*before return 0, iclass 37, count 2 2006.201.23:03:56.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:56.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:03:56.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.23:03:56.77#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:56.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:56.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:56.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:56.89#ibcon#enter wrdev, iclass 37, count 0 2006.201.23:03:56.89#ibcon#first serial, iclass 37, count 0 2006.201.23:03:56.89#ibcon#enter sib2, iclass 37, count 0 2006.201.23:03:56.89#ibcon#flushed, iclass 37, count 0 2006.201.23:03:56.89#ibcon#about to write, iclass 37, count 0 2006.201.23:03:56.89#ibcon#wrote, iclass 37, count 0 2006.201.23:03:56.89#ibcon#about to read 3, iclass 37, count 0 2006.201.23:03:56.91#ibcon#read 3, iclass 37, count 0 2006.201.23:03:56.91#ibcon#about to read 4, iclass 37, count 0 2006.201.23:03:56.91#ibcon#read 4, iclass 37, count 0 2006.201.23:03:56.91#ibcon#about to read 5, iclass 37, count 0 2006.201.23:03:56.91#ibcon#read 5, iclass 37, count 0 2006.201.23:03:56.91#ibcon#about to read 6, iclass 37, count 0 2006.201.23:03:56.91#ibcon#read 6, iclass 37, count 0 2006.201.23:03:56.91#ibcon#end of sib2, iclass 37, count 0 2006.201.23:03:56.91#ibcon#*mode == 0, iclass 37, count 0 2006.201.23:03:56.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.23:03:56.91#ibcon#[27=USB\r\n] 2006.201.23:03:56.91#ibcon#*before write, iclass 37, count 0 2006.201.23:03:56.91#ibcon#enter sib2, iclass 37, count 0 2006.201.23:03:56.91#ibcon#flushed, iclass 37, count 0 2006.201.23:03:56.91#ibcon#about to write, iclass 37, count 0 2006.201.23:03:56.91#ibcon#wrote, iclass 37, count 0 2006.201.23:03:56.91#ibcon#about to read 3, iclass 37, count 0 2006.201.23:03:56.94#ibcon#read 3, iclass 37, count 0 2006.201.23:03:56.94#ibcon#about to read 4, iclass 37, count 0 2006.201.23:03:56.94#ibcon#read 4, iclass 37, count 0 2006.201.23:03:56.94#ibcon#about to read 5, iclass 37, count 0 2006.201.23:03:56.94#ibcon#read 5, iclass 37, count 0 2006.201.23:03:56.94#ibcon#about to read 6, iclass 37, count 0 2006.201.23:03:56.94#ibcon#read 6, iclass 37, count 0 2006.201.23:03:56.94#ibcon#end of sib2, iclass 37, count 0 2006.201.23:03:56.94#ibcon#*after write, iclass 37, count 0 2006.201.23:03:56.94#ibcon#*before return 0, iclass 37, count 0 2006.201.23:03:56.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:56.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:03:56.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.23:03:56.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.23:03:56.94$vck44/vblo=8,744.99 2006.201.23:03:56.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.23:03:56.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.23:03:56.94#ibcon#ireg 17 cls_cnt 0 2006.201.23:03:56.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:56.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:56.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:56.94#ibcon#enter wrdev, iclass 39, count 0 2006.201.23:03:56.94#ibcon#first serial, iclass 39, count 0 2006.201.23:03:56.94#ibcon#enter sib2, iclass 39, count 0 2006.201.23:03:56.94#ibcon#flushed, iclass 39, count 0 2006.201.23:03:56.94#ibcon#about to write, iclass 39, count 0 2006.201.23:03:56.94#ibcon#wrote, iclass 39, count 0 2006.201.23:03:56.94#ibcon#about to read 3, iclass 39, count 0 2006.201.23:03:56.96#ibcon#read 3, iclass 39, count 0 2006.201.23:03:56.96#ibcon#about to read 4, iclass 39, count 0 2006.201.23:03:56.96#ibcon#read 4, iclass 39, count 0 2006.201.23:03:56.96#ibcon#about to read 5, iclass 39, count 0 2006.201.23:03:56.96#ibcon#read 5, iclass 39, count 0 2006.201.23:03:56.96#ibcon#about to read 6, iclass 39, count 0 2006.201.23:03:56.96#ibcon#read 6, iclass 39, count 0 2006.201.23:03:56.96#ibcon#end of sib2, iclass 39, count 0 2006.201.23:03:56.96#ibcon#*mode == 0, iclass 39, count 0 2006.201.23:03:56.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.23:03:56.96#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.23:03:56.96#ibcon#*before write, iclass 39, count 0 2006.201.23:03:56.96#ibcon#enter sib2, iclass 39, count 0 2006.201.23:03:56.96#ibcon#flushed, iclass 39, count 0 2006.201.23:03:56.96#ibcon#about to write, iclass 39, count 0 2006.201.23:03:56.96#ibcon#wrote, iclass 39, count 0 2006.201.23:03:56.96#ibcon#about to read 3, iclass 39, count 0 2006.201.23:03:57.01#ibcon#read 3, iclass 39, count 0 2006.201.23:03:57.01#ibcon#about to read 4, iclass 39, count 0 2006.201.23:03:57.01#ibcon#read 4, iclass 39, count 0 2006.201.23:03:57.01#ibcon#about to read 5, iclass 39, count 0 2006.201.23:03:57.01#ibcon#read 5, iclass 39, count 0 2006.201.23:03:57.01#ibcon#about to read 6, iclass 39, count 0 2006.201.23:03:57.01#ibcon#read 6, iclass 39, count 0 2006.201.23:03:57.01#ibcon#end of sib2, iclass 39, count 0 2006.201.23:03:57.01#ibcon#*after write, iclass 39, count 0 2006.201.23:03:57.01#ibcon#*before return 0, iclass 39, count 0 2006.201.23:03:57.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:57.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:03:57.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.23:03:57.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.23:03:57.01$vck44/vb=8,4 2006.201.23:03:57.01#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.23:03:57.01#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.23:03:57.01#ibcon#ireg 11 cls_cnt 2 2006.201.23:03:57.01#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:57.06#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:57.06#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:57.06#ibcon#enter wrdev, iclass 2, count 2 2006.201.23:03:57.06#ibcon#first serial, iclass 2, count 2 2006.201.23:03:57.06#ibcon#enter sib2, iclass 2, count 2 2006.201.23:03:57.06#ibcon#flushed, iclass 2, count 2 2006.201.23:03:57.06#ibcon#about to write, iclass 2, count 2 2006.201.23:03:57.06#ibcon#wrote, iclass 2, count 2 2006.201.23:03:57.06#ibcon#about to read 3, iclass 2, count 2 2006.201.23:03:57.08#ibcon#read 3, iclass 2, count 2 2006.201.23:03:57.08#ibcon#about to read 4, iclass 2, count 2 2006.201.23:03:57.08#ibcon#read 4, iclass 2, count 2 2006.201.23:03:57.08#ibcon#about to read 5, iclass 2, count 2 2006.201.23:03:57.08#ibcon#read 5, iclass 2, count 2 2006.201.23:03:57.08#ibcon#about to read 6, iclass 2, count 2 2006.201.23:03:57.08#ibcon#read 6, iclass 2, count 2 2006.201.23:03:57.08#ibcon#end of sib2, iclass 2, count 2 2006.201.23:03:57.08#ibcon#*mode == 0, iclass 2, count 2 2006.201.23:03:57.08#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.23:03:57.08#ibcon#[27=AT08-04\r\n] 2006.201.23:03:57.08#ibcon#*before write, iclass 2, count 2 2006.201.23:03:57.08#ibcon#enter sib2, iclass 2, count 2 2006.201.23:03:57.08#ibcon#flushed, iclass 2, count 2 2006.201.23:03:57.08#ibcon#about to write, iclass 2, count 2 2006.201.23:03:57.08#ibcon#wrote, iclass 2, count 2 2006.201.23:03:57.08#ibcon#about to read 3, iclass 2, count 2 2006.201.23:03:57.11#ibcon#read 3, iclass 2, count 2 2006.201.23:03:57.11#ibcon#about to read 4, iclass 2, count 2 2006.201.23:03:57.11#ibcon#read 4, iclass 2, count 2 2006.201.23:03:57.11#ibcon#about to read 5, iclass 2, count 2 2006.201.23:03:57.11#ibcon#read 5, iclass 2, count 2 2006.201.23:03:57.11#ibcon#about to read 6, iclass 2, count 2 2006.201.23:03:57.11#ibcon#read 6, iclass 2, count 2 2006.201.23:03:57.11#ibcon#end of sib2, iclass 2, count 2 2006.201.23:03:57.11#ibcon#*after write, iclass 2, count 2 2006.201.23:03:57.11#ibcon#*before return 0, iclass 2, count 2 2006.201.23:03:57.11#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:57.11#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:03:57.11#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.23:03:57.11#ibcon#ireg 7 cls_cnt 0 2006.201.23:03:57.11#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:57.23#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:57.23#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:57.23#ibcon#enter wrdev, iclass 2, count 0 2006.201.23:03:57.23#ibcon#first serial, iclass 2, count 0 2006.201.23:03:57.23#ibcon#enter sib2, iclass 2, count 0 2006.201.23:03:57.23#ibcon#flushed, iclass 2, count 0 2006.201.23:03:57.23#ibcon#about to write, iclass 2, count 0 2006.201.23:03:57.23#ibcon#wrote, iclass 2, count 0 2006.201.23:03:57.23#ibcon#about to read 3, iclass 2, count 0 2006.201.23:03:57.25#ibcon#read 3, iclass 2, count 0 2006.201.23:03:57.25#ibcon#about to read 4, iclass 2, count 0 2006.201.23:03:57.25#ibcon#read 4, iclass 2, count 0 2006.201.23:03:57.25#ibcon#about to read 5, iclass 2, count 0 2006.201.23:03:57.25#ibcon#read 5, iclass 2, count 0 2006.201.23:03:57.25#ibcon#about to read 6, iclass 2, count 0 2006.201.23:03:57.25#ibcon#read 6, iclass 2, count 0 2006.201.23:03:57.25#ibcon#end of sib2, iclass 2, count 0 2006.201.23:03:57.25#ibcon#*mode == 0, iclass 2, count 0 2006.201.23:03:57.25#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.23:03:57.25#ibcon#[27=USB\r\n] 2006.201.23:03:57.25#ibcon#*before write, iclass 2, count 0 2006.201.23:03:57.25#ibcon#enter sib2, iclass 2, count 0 2006.201.23:03:57.25#ibcon#flushed, iclass 2, count 0 2006.201.23:03:57.25#ibcon#about to write, iclass 2, count 0 2006.201.23:03:57.25#ibcon#wrote, iclass 2, count 0 2006.201.23:03:57.25#ibcon#about to read 3, iclass 2, count 0 2006.201.23:03:57.28#ibcon#read 3, iclass 2, count 0 2006.201.23:03:57.28#ibcon#about to read 4, iclass 2, count 0 2006.201.23:03:57.28#ibcon#read 4, iclass 2, count 0 2006.201.23:03:57.28#ibcon#about to read 5, iclass 2, count 0 2006.201.23:03:57.28#ibcon#read 5, iclass 2, count 0 2006.201.23:03:57.28#ibcon#about to read 6, iclass 2, count 0 2006.201.23:03:57.28#ibcon#read 6, iclass 2, count 0 2006.201.23:03:57.28#ibcon#end of sib2, iclass 2, count 0 2006.201.23:03:57.28#ibcon#*after write, iclass 2, count 0 2006.201.23:03:57.28#ibcon#*before return 0, iclass 2, count 0 2006.201.23:03:57.28#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:57.28#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:03:57.28#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.23:03:57.28#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.23:03:57.28$vck44/vabw=wide 2006.201.23:03:57.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.23:03:57.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.23:03:57.28#ibcon#ireg 8 cls_cnt 0 2006.201.23:03:57.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:57.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:57.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:57.28#ibcon#enter wrdev, iclass 5, count 0 2006.201.23:03:57.28#ibcon#first serial, iclass 5, count 0 2006.201.23:03:57.28#ibcon#enter sib2, iclass 5, count 0 2006.201.23:03:57.28#ibcon#flushed, iclass 5, count 0 2006.201.23:03:57.28#ibcon#about to write, iclass 5, count 0 2006.201.23:03:57.28#ibcon#wrote, iclass 5, count 0 2006.201.23:03:57.28#ibcon#about to read 3, iclass 5, count 0 2006.201.23:03:57.30#ibcon#read 3, iclass 5, count 0 2006.201.23:03:57.30#ibcon#about to read 4, iclass 5, count 0 2006.201.23:03:57.30#ibcon#read 4, iclass 5, count 0 2006.201.23:03:57.30#ibcon#about to read 5, iclass 5, count 0 2006.201.23:03:57.30#ibcon#read 5, iclass 5, count 0 2006.201.23:03:57.30#ibcon#about to read 6, iclass 5, count 0 2006.201.23:03:57.30#ibcon#read 6, iclass 5, count 0 2006.201.23:03:57.30#ibcon#end of sib2, iclass 5, count 0 2006.201.23:03:57.30#ibcon#*mode == 0, iclass 5, count 0 2006.201.23:03:57.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.23:03:57.30#ibcon#[25=BW32\r\n] 2006.201.23:03:57.30#ibcon#*before write, iclass 5, count 0 2006.201.23:03:57.30#ibcon#enter sib2, iclass 5, count 0 2006.201.23:03:57.30#ibcon#flushed, iclass 5, count 0 2006.201.23:03:57.30#ibcon#about to write, iclass 5, count 0 2006.201.23:03:57.30#ibcon#wrote, iclass 5, count 0 2006.201.23:03:57.30#ibcon#about to read 3, iclass 5, count 0 2006.201.23:03:57.33#ibcon#read 3, iclass 5, count 0 2006.201.23:03:57.33#ibcon#about to read 4, iclass 5, count 0 2006.201.23:03:57.33#ibcon#read 4, iclass 5, count 0 2006.201.23:03:57.33#ibcon#about to read 5, iclass 5, count 0 2006.201.23:03:57.33#ibcon#read 5, iclass 5, count 0 2006.201.23:03:57.33#ibcon#about to read 6, iclass 5, count 0 2006.201.23:03:57.33#ibcon#read 6, iclass 5, count 0 2006.201.23:03:57.33#ibcon#end of sib2, iclass 5, count 0 2006.201.23:03:57.33#ibcon#*after write, iclass 5, count 0 2006.201.23:03:57.33#ibcon#*before return 0, iclass 5, count 0 2006.201.23:03:57.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:57.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:03:57.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.23:03:57.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.23:03:57.33$vck44/vbbw=wide 2006.201.23:03:57.33#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.23:03:57.33#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.23:03:57.33#ibcon#ireg 8 cls_cnt 0 2006.201.23:03:57.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:03:57.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:03:57.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:03:57.40#ibcon#enter wrdev, iclass 7, count 0 2006.201.23:03:57.40#ibcon#first serial, iclass 7, count 0 2006.201.23:03:57.40#ibcon#enter sib2, iclass 7, count 0 2006.201.23:03:57.40#ibcon#flushed, iclass 7, count 0 2006.201.23:03:57.40#ibcon#about to write, iclass 7, count 0 2006.201.23:03:57.40#ibcon#wrote, iclass 7, count 0 2006.201.23:03:57.40#ibcon#about to read 3, iclass 7, count 0 2006.201.23:03:57.42#ibcon#read 3, iclass 7, count 0 2006.201.23:03:57.42#ibcon#about to read 4, iclass 7, count 0 2006.201.23:03:57.42#ibcon#read 4, iclass 7, count 0 2006.201.23:03:57.42#ibcon#about to read 5, iclass 7, count 0 2006.201.23:03:57.42#ibcon#read 5, iclass 7, count 0 2006.201.23:03:57.42#ibcon#about to read 6, iclass 7, count 0 2006.201.23:03:57.42#ibcon#read 6, iclass 7, count 0 2006.201.23:03:57.42#ibcon#end of sib2, iclass 7, count 0 2006.201.23:03:57.42#ibcon#*mode == 0, iclass 7, count 0 2006.201.23:03:57.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.23:03:57.42#ibcon#[27=BW32\r\n] 2006.201.23:03:57.42#ibcon#*before write, iclass 7, count 0 2006.201.23:03:57.42#ibcon#enter sib2, iclass 7, count 0 2006.201.23:03:57.42#ibcon#flushed, iclass 7, count 0 2006.201.23:03:57.42#ibcon#about to write, iclass 7, count 0 2006.201.23:03:57.42#ibcon#wrote, iclass 7, count 0 2006.201.23:03:57.42#ibcon#about to read 3, iclass 7, count 0 2006.201.23:03:57.45#ibcon#read 3, iclass 7, count 0 2006.201.23:03:57.45#ibcon#about to read 4, iclass 7, count 0 2006.201.23:03:57.45#ibcon#read 4, iclass 7, count 0 2006.201.23:03:57.45#ibcon#about to read 5, iclass 7, count 0 2006.201.23:03:57.45#ibcon#read 5, iclass 7, count 0 2006.201.23:03:57.45#ibcon#about to read 6, iclass 7, count 0 2006.201.23:03:57.45#ibcon#read 6, iclass 7, count 0 2006.201.23:03:57.45#ibcon#end of sib2, iclass 7, count 0 2006.201.23:03:57.45#ibcon#*after write, iclass 7, count 0 2006.201.23:03:57.45#ibcon#*before return 0, iclass 7, count 0 2006.201.23:03:57.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:03:57.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:03:57.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.23:03:57.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.23:03:57.45$setupk4/ifdk4 2006.201.23:03:57.45$ifdk4/lo= 2006.201.23:03:57.45$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.23:03:57.45$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.23:03:57.45$ifdk4/patch= 2006.201.23:03:57.45$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.23:03:57.45$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.23:03:57.45$setupk4/!*+20s 2006.201.23:04:02.88#abcon#<5=/03 0.6 2.0 20.121001001.7\r\n> 2006.201.23:04:02.90#abcon#{5=INTERFACE CLEAR} 2006.201.23:04:02.96#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:04:11.87$setupk4/"tpicd 2006.201.23:04:11.87$setupk4/echo=off 2006.201.23:04:11.87$setupk4/xlog=off 2006.201.23:04:11.87:!2006.201.23:13:55 2006.201.23:04:31.14#trakl#Source acquired 2006.201.23:04:32.14#flagr#flagr/antenna,acquired 2006.201.23:13:55.00:preob 2006.201.23:13:55.14/onsource/TRACKING 2006.201.23:13:55.14:!2006.201.23:14:05 2006.201.23:14:05.00:"tape 2006.201.23:14:05.00:"st=record 2006.201.23:14:05.00:data_valid=on 2006.201.23:14:05.00:midob 2006.201.23:14:05.14/onsource/TRACKING 2006.201.23:14:05.14/wx/20.20,1001.6,100 2006.201.23:14:05.37/cable/+6.4844E-03 2006.201.23:14:06.46/va/01,08,usb,yes,52,55 2006.201.23:14:06.46/va/02,07,usb,yes,55,57 2006.201.23:14:06.46/va/03,08,usb,yes,50,53 2006.201.23:14:06.46/va/04,07,usb,yes,57,60 2006.201.23:14:06.46/va/05,04,usb,yes,51,52 2006.201.23:14:06.46/va/06,05,usb,yes,51,51 2006.201.23:14:06.46/va/07,05,usb,yes,50,52 2006.201.23:14:06.46/va/08,04,usb,yes,50,59 2006.201.23:14:06.69/valo/01,524.99,yes,locked 2006.201.23:14:06.69/valo/02,534.99,yes,locked 2006.201.23:14:06.69/valo/03,564.99,yes,locked 2006.201.23:14:06.69/valo/04,624.99,yes,locked 2006.201.23:14:06.69/valo/05,734.99,yes,locked 2006.201.23:14:06.69/valo/06,814.99,yes,locked 2006.201.23:14:06.69/valo/07,864.99,yes,locked 2006.201.23:14:06.69/valo/08,884.99,yes,locked 2006.201.23:14:07.78/vb/01,04,usb,yes,31,29 2006.201.23:14:07.78/vb/02,05,usb,yes,30,29 2006.201.23:14:07.78/vb/03,04,usb,yes,31,34 2006.201.23:14:07.78/vb/04,05,usb,yes,31,30 2006.201.23:14:07.78/vb/05,04,usb,yes,27,30 2006.201.23:14:07.78/vb/06,04,usb,yes,32,28 2006.201.23:14:07.78/vb/07,04,usb,yes,32,32 2006.201.23:14:07.78/vb/08,04,usb,yes,29,33 2006.201.23:14:08.01/vblo/01,629.99,yes,locked 2006.201.23:14:08.01/vblo/02,634.99,yes,locked 2006.201.23:14:08.01/vblo/03,649.99,yes,locked 2006.201.23:14:08.01/vblo/04,679.99,yes,locked 2006.201.23:14:08.01/vblo/05,709.99,yes,locked 2006.201.23:14:08.01/vblo/06,719.99,yes,locked 2006.201.23:14:08.01/vblo/07,734.99,yes,locked 2006.201.23:14:08.01/vblo/08,744.99,yes,locked 2006.201.23:14:08.16/vabw/8 2006.201.23:14:08.31/vbbw/8 2006.201.23:14:08.40/xfe/off,on,14.5 2006.201.23:14:08.80/ifatt/23,28,28,28 2006.201.23:14:09.07/fmout-gps/S +4.52E-07 2006.201.23:14:09.14:!2006.201.23:23:45 2006.201.23:23:45.00:data_valid=off 2006.201.23:23:45.00:"et 2006.201.23:23:45.00:!+3s 2006.201.23:23:48.02:"tape 2006.201.23:23:48.02:postob 2006.201.23:23:48.22/cable/+6.4854E-03 2006.201.23:23:48.22/wx/20.34,1001.7,100 2006.201.23:23:48.29/fmout-gps/S +4.51E-07 2006.201.23:23:48.29:scan_name=201-2327,jd0607,220 2006.201.23:23:48.29:source=2201+315,220314.98,314538.3,2000.0,cw 2006.201.23:23:50.13#flagr#flagr/antenna,new-source 2006.201.23:23:50.13:checkk5 2006.201.23:23:50.51/chk_autoobs//k5ts1/ autoobs is running! 2006.201.23:23:50.89/chk_autoobs//k5ts2/ autoobs is running! 2006.201.23:23:51.28/chk_autoobs//k5ts3/ autoobs is running! 2006.201.23:23:51.66/chk_autoobs//k5ts4/ autoobs is running! 2006.201.23:23:52.34/chk_obsdata//k5ts1/T2012314??a.dat file size is correct (nominal:2320MB, actual:2316MB). 2006.201.23:23:53.01/chk_obsdata//k5ts2/T2012314??b.dat file size is correct (nominal:2320MB, actual:2316MB). 2006.201.23:23:53.69/chk_obsdata//k5ts3/T2012314??c.dat file size is correct (nominal:2320MB, actual:2316MB). 2006.201.23:23:54.36/chk_obsdata//k5ts4/T2012314??d.dat file size is correct (nominal:2320MB, actual:2316MB). 2006.201.23:23:55.06/k5log//k5ts1_log_newline 2006.201.23:23:55.75/k5log//k5ts2_log_newline 2006.201.23:23:56.44/k5log//k5ts3_log_newline 2006.201.23:23:57.13/k5log//k5ts4_log_newline 2006.201.23:23:57.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.23:23:57.15:setupk4=1 2006.201.23:23:57.15$setupk4/echo=on 2006.201.23:23:57.15$setupk4/pcalon 2006.201.23:23:57.15$pcalon/"no phase cal control is implemented here 2006.201.23:23:57.15$setupk4/"tpicd=stop 2006.201.23:23:57.15$setupk4/"rec=synch_on 2006.201.23:23:57.15$setupk4/"rec_mode=128 2006.201.23:23:57.15$setupk4/!* 2006.201.23:23:57.15$setupk4/recpk4 2006.201.23:23:57.15$recpk4/recpatch= 2006.201.23:23:57.16$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.23:23:57.16$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.23:23:57.16$setupk4/vck44 2006.201.23:23:57.16$vck44/valo=1,524.99 2006.201.23:23:57.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.23:23:57.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.23:23:57.16#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:57.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:23:57.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:23:57.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:23:57.16#ibcon#enter wrdev, iclass 18, count 0 2006.201.23:23:57.16#ibcon#first serial, iclass 18, count 0 2006.201.23:23:57.16#ibcon#enter sib2, iclass 18, count 0 2006.201.23:23:57.16#ibcon#flushed, iclass 18, count 0 2006.201.23:23:57.16#ibcon#about to write, iclass 18, count 0 2006.201.23:23:57.16#ibcon#wrote, iclass 18, count 0 2006.201.23:23:57.16#ibcon#about to read 3, iclass 18, count 0 2006.201.23:23:57.19#ibcon#read 3, iclass 18, count 0 2006.201.23:23:57.19#ibcon#about to read 4, iclass 18, count 0 2006.201.23:23:57.19#ibcon#read 4, iclass 18, count 0 2006.201.23:23:57.19#ibcon#about to read 5, iclass 18, count 0 2006.201.23:23:57.19#ibcon#read 5, iclass 18, count 0 2006.201.23:23:57.19#ibcon#about to read 6, iclass 18, count 0 2006.201.23:23:57.19#ibcon#read 6, iclass 18, count 0 2006.201.23:23:57.19#ibcon#end of sib2, iclass 18, count 0 2006.201.23:23:57.19#ibcon#*mode == 0, iclass 18, count 0 2006.201.23:23:57.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.23:23:57.19#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.23:23:57.19#ibcon#*before write, iclass 18, count 0 2006.201.23:23:57.19#ibcon#enter sib2, iclass 18, count 0 2006.201.23:23:57.19#ibcon#flushed, iclass 18, count 0 2006.201.23:23:57.19#ibcon#about to write, iclass 18, count 0 2006.201.23:23:57.19#ibcon#wrote, iclass 18, count 0 2006.201.23:23:57.19#ibcon#about to read 3, iclass 18, count 0 2006.201.23:23:57.24#ibcon#read 3, iclass 18, count 0 2006.201.23:23:57.24#ibcon#about to read 4, iclass 18, count 0 2006.201.23:23:57.24#ibcon#read 4, iclass 18, count 0 2006.201.23:23:57.24#ibcon#about to read 5, iclass 18, count 0 2006.201.23:23:57.24#ibcon#read 5, iclass 18, count 0 2006.201.23:23:57.24#ibcon#about to read 6, iclass 18, count 0 2006.201.23:23:57.24#ibcon#read 6, iclass 18, count 0 2006.201.23:23:57.24#ibcon#end of sib2, iclass 18, count 0 2006.201.23:23:57.24#ibcon#*after write, iclass 18, count 0 2006.201.23:23:57.24#ibcon#*before return 0, iclass 18, count 0 2006.201.23:23:57.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:23:57.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:23:57.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.23:23:57.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.23:23:57.24$vck44/va=1,8 2006.201.23:23:57.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.23:23:57.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.23:23:57.24#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:57.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:23:57.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:23:57.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:23:57.24#ibcon#enter wrdev, iclass 20, count 2 2006.201.23:23:57.24#ibcon#first serial, iclass 20, count 2 2006.201.23:23:57.24#ibcon#enter sib2, iclass 20, count 2 2006.201.23:23:57.24#ibcon#flushed, iclass 20, count 2 2006.201.23:23:57.24#ibcon#about to write, iclass 20, count 2 2006.201.23:23:57.24#ibcon#wrote, iclass 20, count 2 2006.201.23:23:57.24#ibcon#about to read 3, iclass 20, count 2 2006.201.23:23:57.26#ibcon#read 3, iclass 20, count 2 2006.201.23:23:57.26#ibcon#about to read 4, iclass 20, count 2 2006.201.23:23:57.26#ibcon#read 4, iclass 20, count 2 2006.201.23:23:57.26#ibcon#about to read 5, iclass 20, count 2 2006.201.23:23:57.26#ibcon#read 5, iclass 20, count 2 2006.201.23:23:57.26#ibcon#about to read 6, iclass 20, count 2 2006.201.23:23:57.26#ibcon#read 6, iclass 20, count 2 2006.201.23:23:57.26#ibcon#end of sib2, iclass 20, count 2 2006.201.23:23:57.26#ibcon#*mode == 0, iclass 20, count 2 2006.201.23:23:57.26#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.23:23:57.26#ibcon#[25=AT01-08\r\n] 2006.201.23:23:57.26#ibcon#*before write, iclass 20, count 2 2006.201.23:23:57.26#ibcon#enter sib2, iclass 20, count 2 2006.201.23:23:57.26#ibcon#flushed, iclass 20, count 2 2006.201.23:23:57.26#ibcon#about to write, iclass 20, count 2 2006.201.23:23:57.26#ibcon#wrote, iclass 20, count 2 2006.201.23:23:57.26#ibcon#about to read 3, iclass 20, count 2 2006.201.23:23:57.29#ibcon#read 3, iclass 20, count 2 2006.201.23:23:57.29#ibcon#about to read 4, iclass 20, count 2 2006.201.23:23:57.29#ibcon#read 4, iclass 20, count 2 2006.201.23:23:57.29#ibcon#about to read 5, iclass 20, count 2 2006.201.23:23:57.29#ibcon#read 5, iclass 20, count 2 2006.201.23:23:57.29#ibcon#about to read 6, iclass 20, count 2 2006.201.23:23:57.29#ibcon#read 6, iclass 20, count 2 2006.201.23:23:57.29#ibcon#end of sib2, iclass 20, count 2 2006.201.23:23:57.29#ibcon#*after write, iclass 20, count 2 2006.201.23:23:57.29#ibcon#*before return 0, iclass 20, count 2 2006.201.23:23:57.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:23:57.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:23:57.29#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.23:23:57.29#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:57.29#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:23:57.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:23:57.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:23:57.41#ibcon#enter wrdev, iclass 20, count 0 2006.201.23:23:57.41#ibcon#first serial, iclass 20, count 0 2006.201.23:23:57.41#ibcon#enter sib2, iclass 20, count 0 2006.201.23:23:57.41#ibcon#flushed, iclass 20, count 0 2006.201.23:23:57.41#ibcon#about to write, iclass 20, count 0 2006.201.23:23:57.41#ibcon#wrote, iclass 20, count 0 2006.201.23:23:57.41#ibcon#about to read 3, iclass 20, count 0 2006.201.23:23:57.43#ibcon#read 3, iclass 20, count 0 2006.201.23:23:57.43#ibcon#about to read 4, iclass 20, count 0 2006.201.23:23:57.43#ibcon#read 4, iclass 20, count 0 2006.201.23:23:57.43#ibcon#about to read 5, iclass 20, count 0 2006.201.23:23:57.43#ibcon#read 5, iclass 20, count 0 2006.201.23:23:57.43#ibcon#about to read 6, iclass 20, count 0 2006.201.23:23:57.43#ibcon#read 6, iclass 20, count 0 2006.201.23:23:57.43#ibcon#end of sib2, iclass 20, count 0 2006.201.23:23:57.43#ibcon#*mode == 0, iclass 20, count 0 2006.201.23:23:57.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.23:23:57.43#ibcon#[25=USB\r\n] 2006.201.23:23:57.43#ibcon#*before write, iclass 20, count 0 2006.201.23:23:57.43#ibcon#enter sib2, iclass 20, count 0 2006.201.23:23:57.43#ibcon#flushed, iclass 20, count 0 2006.201.23:23:57.43#ibcon#about to write, iclass 20, count 0 2006.201.23:23:57.43#ibcon#wrote, iclass 20, count 0 2006.201.23:23:57.43#ibcon#about to read 3, iclass 20, count 0 2006.201.23:23:57.46#ibcon#read 3, iclass 20, count 0 2006.201.23:23:57.46#ibcon#about to read 4, iclass 20, count 0 2006.201.23:23:57.46#ibcon#read 4, iclass 20, count 0 2006.201.23:23:57.46#ibcon#about to read 5, iclass 20, count 0 2006.201.23:23:57.46#ibcon#read 5, iclass 20, count 0 2006.201.23:23:57.46#ibcon#about to read 6, iclass 20, count 0 2006.201.23:23:57.46#ibcon#read 6, iclass 20, count 0 2006.201.23:23:57.46#ibcon#end of sib2, iclass 20, count 0 2006.201.23:23:57.46#ibcon#*after write, iclass 20, count 0 2006.201.23:23:57.46#ibcon#*before return 0, iclass 20, count 0 2006.201.23:23:57.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:23:57.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:23:57.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.23:23:57.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.23:23:57.46$vck44/valo=2,534.99 2006.201.23:23:57.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.23:23:57.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.23:23:57.46#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:57.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:23:57.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:23:57.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:23:57.46#ibcon#enter wrdev, iclass 22, count 0 2006.201.23:23:57.46#ibcon#first serial, iclass 22, count 0 2006.201.23:23:57.46#ibcon#enter sib2, iclass 22, count 0 2006.201.23:23:57.46#ibcon#flushed, iclass 22, count 0 2006.201.23:23:57.46#ibcon#about to write, iclass 22, count 0 2006.201.23:23:57.46#ibcon#wrote, iclass 22, count 0 2006.201.23:23:57.46#ibcon#about to read 3, iclass 22, count 0 2006.201.23:23:57.48#ibcon#read 3, iclass 22, count 0 2006.201.23:23:57.48#ibcon#about to read 4, iclass 22, count 0 2006.201.23:23:57.48#ibcon#read 4, iclass 22, count 0 2006.201.23:23:57.48#ibcon#about to read 5, iclass 22, count 0 2006.201.23:23:57.48#ibcon#read 5, iclass 22, count 0 2006.201.23:23:57.48#ibcon#about to read 6, iclass 22, count 0 2006.201.23:23:57.48#ibcon#read 6, iclass 22, count 0 2006.201.23:23:57.48#ibcon#end of sib2, iclass 22, count 0 2006.201.23:23:57.48#ibcon#*mode == 0, iclass 22, count 0 2006.201.23:23:57.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.23:23:57.48#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.23:23:57.48#ibcon#*before write, iclass 22, count 0 2006.201.23:23:57.48#ibcon#enter sib2, iclass 22, count 0 2006.201.23:23:57.48#ibcon#flushed, iclass 22, count 0 2006.201.23:23:57.48#ibcon#about to write, iclass 22, count 0 2006.201.23:23:57.48#ibcon#wrote, iclass 22, count 0 2006.201.23:23:57.48#ibcon#about to read 3, iclass 22, count 0 2006.201.23:23:57.52#ibcon#read 3, iclass 22, count 0 2006.201.23:23:57.52#ibcon#about to read 4, iclass 22, count 0 2006.201.23:23:57.52#ibcon#read 4, iclass 22, count 0 2006.201.23:23:57.52#ibcon#about to read 5, iclass 22, count 0 2006.201.23:23:57.52#ibcon#read 5, iclass 22, count 0 2006.201.23:23:57.52#ibcon#about to read 6, iclass 22, count 0 2006.201.23:23:57.52#ibcon#read 6, iclass 22, count 0 2006.201.23:23:57.52#ibcon#end of sib2, iclass 22, count 0 2006.201.23:23:57.52#ibcon#*after write, iclass 22, count 0 2006.201.23:23:57.52#ibcon#*before return 0, iclass 22, count 0 2006.201.23:23:57.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:23:57.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:23:57.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.23:23:57.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.23:23:57.52$vck44/va=2,7 2006.201.23:23:57.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.23:23:57.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.23:23:57.52#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:57.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:23:57.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:23:57.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:23:57.58#ibcon#enter wrdev, iclass 24, count 2 2006.201.23:23:57.58#ibcon#first serial, iclass 24, count 2 2006.201.23:23:57.58#ibcon#enter sib2, iclass 24, count 2 2006.201.23:23:57.58#ibcon#flushed, iclass 24, count 2 2006.201.23:23:57.58#ibcon#about to write, iclass 24, count 2 2006.201.23:23:57.58#ibcon#wrote, iclass 24, count 2 2006.201.23:23:57.58#ibcon#about to read 3, iclass 24, count 2 2006.201.23:23:57.60#ibcon#read 3, iclass 24, count 2 2006.201.23:23:57.60#ibcon#about to read 4, iclass 24, count 2 2006.201.23:23:57.60#ibcon#read 4, iclass 24, count 2 2006.201.23:23:57.60#ibcon#about to read 5, iclass 24, count 2 2006.201.23:23:57.60#ibcon#read 5, iclass 24, count 2 2006.201.23:23:57.60#ibcon#about to read 6, iclass 24, count 2 2006.201.23:23:57.60#ibcon#read 6, iclass 24, count 2 2006.201.23:23:57.60#ibcon#end of sib2, iclass 24, count 2 2006.201.23:23:57.60#ibcon#*mode == 0, iclass 24, count 2 2006.201.23:23:57.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.23:23:57.60#ibcon#[25=AT02-07\r\n] 2006.201.23:23:57.60#ibcon#*before write, iclass 24, count 2 2006.201.23:23:57.60#ibcon#enter sib2, iclass 24, count 2 2006.201.23:23:57.60#ibcon#flushed, iclass 24, count 2 2006.201.23:23:57.60#ibcon#about to write, iclass 24, count 2 2006.201.23:23:57.60#ibcon#wrote, iclass 24, count 2 2006.201.23:23:57.60#ibcon#about to read 3, iclass 24, count 2 2006.201.23:23:57.63#ibcon#read 3, iclass 24, count 2 2006.201.23:23:57.63#ibcon#about to read 4, iclass 24, count 2 2006.201.23:23:57.63#ibcon#read 4, iclass 24, count 2 2006.201.23:23:57.63#ibcon#about to read 5, iclass 24, count 2 2006.201.23:23:57.63#ibcon#read 5, iclass 24, count 2 2006.201.23:23:57.63#ibcon#about to read 6, iclass 24, count 2 2006.201.23:23:57.63#ibcon#read 6, iclass 24, count 2 2006.201.23:23:57.63#ibcon#end of sib2, iclass 24, count 2 2006.201.23:23:57.63#ibcon#*after write, iclass 24, count 2 2006.201.23:23:57.63#ibcon#*before return 0, iclass 24, count 2 2006.201.23:23:57.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:23:57.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:23:57.63#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.23:23:57.63#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:57.63#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:23:57.75#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:23:57.75#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:23:57.75#ibcon#enter wrdev, iclass 24, count 0 2006.201.23:23:57.75#ibcon#first serial, iclass 24, count 0 2006.201.23:23:57.75#ibcon#enter sib2, iclass 24, count 0 2006.201.23:23:57.75#ibcon#flushed, iclass 24, count 0 2006.201.23:23:57.75#ibcon#about to write, iclass 24, count 0 2006.201.23:23:57.75#ibcon#wrote, iclass 24, count 0 2006.201.23:23:57.75#ibcon#about to read 3, iclass 24, count 0 2006.201.23:23:57.77#ibcon#read 3, iclass 24, count 0 2006.201.23:23:57.77#ibcon#about to read 4, iclass 24, count 0 2006.201.23:23:57.77#ibcon#read 4, iclass 24, count 0 2006.201.23:23:57.77#ibcon#about to read 5, iclass 24, count 0 2006.201.23:23:57.77#ibcon#read 5, iclass 24, count 0 2006.201.23:23:57.77#ibcon#about to read 6, iclass 24, count 0 2006.201.23:23:57.77#ibcon#read 6, iclass 24, count 0 2006.201.23:23:57.77#ibcon#end of sib2, iclass 24, count 0 2006.201.23:23:57.77#ibcon#*mode == 0, iclass 24, count 0 2006.201.23:23:57.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.23:23:57.77#ibcon#[25=USB\r\n] 2006.201.23:23:57.77#ibcon#*before write, iclass 24, count 0 2006.201.23:23:57.77#ibcon#enter sib2, iclass 24, count 0 2006.201.23:23:57.77#ibcon#flushed, iclass 24, count 0 2006.201.23:23:57.77#ibcon#about to write, iclass 24, count 0 2006.201.23:23:57.77#ibcon#wrote, iclass 24, count 0 2006.201.23:23:57.77#ibcon#about to read 3, iclass 24, count 0 2006.201.23:23:57.80#ibcon#read 3, iclass 24, count 0 2006.201.23:23:57.80#ibcon#about to read 4, iclass 24, count 0 2006.201.23:23:57.80#ibcon#read 4, iclass 24, count 0 2006.201.23:23:57.80#ibcon#about to read 5, iclass 24, count 0 2006.201.23:23:57.80#ibcon#read 5, iclass 24, count 0 2006.201.23:23:57.80#ibcon#about to read 6, iclass 24, count 0 2006.201.23:23:57.80#ibcon#read 6, iclass 24, count 0 2006.201.23:23:57.80#ibcon#end of sib2, iclass 24, count 0 2006.201.23:23:57.80#ibcon#*after write, iclass 24, count 0 2006.201.23:23:57.80#ibcon#*before return 0, iclass 24, count 0 2006.201.23:23:57.80#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:23:57.80#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:23:57.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.23:23:57.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.23:23:57.80$vck44/valo=3,564.99 2006.201.23:23:57.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.23:23:57.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.23:23:57.80#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:57.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:23:57.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:23:57.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:23:57.80#ibcon#enter wrdev, iclass 26, count 0 2006.201.23:23:57.80#ibcon#first serial, iclass 26, count 0 2006.201.23:23:57.80#ibcon#enter sib2, iclass 26, count 0 2006.201.23:23:57.80#ibcon#flushed, iclass 26, count 0 2006.201.23:23:57.80#ibcon#about to write, iclass 26, count 0 2006.201.23:23:57.80#ibcon#wrote, iclass 26, count 0 2006.201.23:23:57.80#ibcon#about to read 3, iclass 26, count 0 2006.201.23:23:57.82#ibcon#read 3, iclass 26, count 0 2006.201.23:23:57.82#ibcon#about to read 4, iclass 26, count 0 2006.201.23:23:57.82#ibcon#read 4, iclass 26, count 0 2006.201.23:23:57.82#ibcon#about to read 5, iclass 26, count 0 2006.201.23:23:57.82#ibcon#read 5, iclass 26, count 0 2006.201.23:23:57.82#ibcon#about to read 6, iclass 26, count 0 2006.201.23:23:57.82#ibcon#read 6, iclass 26, count 0 2006.201.23:23:57.82#ibcon#end of sib2, iclass 26, count 0 2006.201.23:23:57.82#ibcon#*mode == 0, iclass 26, count 0 2006.201.23:23:57.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.23:23:57.82#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.23:23:57.82#ibcon#*before write, iclass 26, count 0 2006.201.23:23:57.82#ibcon#enter sib2, iclass 26, count 0 2006.201.23:23:57.82#ibcon#flushed, iclass 26, count 0 2006.201.23:23:57.82#ibcon#about to write, iclass 26, count 0 2006.201.23:23:57.82#ibcon#wrote, iclass 26, count 0 2006.201.23:23:57.82#ibcon#about to read 3, iclass 26, count 0 2006.201.23:23:57.87#ibcon#read 3, iclass 26, count 0 2006.201.23:23:57.87#ibcon#about to read 4, iclass 26, count 0 2006.201.23:23:57.87#ibcon#read 4, iclass 26, count 0 2006.201.23:23:57.87#ibcon#about to read 5, iclass 26, count 0 2006.201.23:23:57.87#ibcon#read 5, iclass 26, count 0 2006.201.23:23:57.87#ibcon#about to read 6, iclass 26, count 0 2006.201.23:23:57.87#ibcon#read 6, iclass 26, count 0 2006.201.23:23:57.87#ibcon#end of sib2, iclass 26, count 0 2006.201.23:23:57.87#ibcon#*after write, iclass 26, count 0 2006.201.23:23:57.87#ibcon#*before return 0, iclass 26, count 0 2006.201.23:23:57.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:23:57.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:23:57.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.23:23:57.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.23:23:57.87$vck44/va=3,8 2006.201.23:23:57.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.23:23:57.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.23:23:57.87#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:57.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:23:57.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:23:57.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:23:57.92#ibcon#enter wrdev, iclass 28, count 2 2006.201.23:23:57.92#ibcon#first serial, iclass 28, count 2 2006.201.23:23:57.92#ibcon#enter sib2, iclass 28, count 2 2006.201.23:23:57.92#ibcon#flushed, iclass 28, count 2 2006.201.23:23:57.92#ibcon#about to write, iclass 28, count 2 2006.201.23:23:57.92#ibcon#wrote, iclass 28, count 2 2006.201.23:23:57.92#ibcon#about to read 3, iclass 28, count 2 2006.201.23:23:57.94#ibcon#read 3, iclass 28, count 2 2006.201.23:23:57.94#ibcon#about to read 4, iclass 28, count 2 2006.201.23:23:57.94#ibcon#read 4, iclass 28, count 2 2006.201.23:23:57.94#ibcon#about to read 5, iclass 28, count 2 2006.201.23:23:57.94#ibcon#read 5, iclass 28, count 2 2006.201.23:23:57.94#ibcon#about to read 6, iclass 28, count 2 2006.201.23:23:57.94#ibcon#read 6, iclass 28, count 2 2006.201.23:23:57.94#ibcon#end of sib2, iclass 28, count 2 2006.201.23:23:57.94#ibcon#*mode == 0, iclass 28, count 2 2006.201.23:23:57.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.23:23:57.94#ibcon#[25=AT03-08\r\n] 2006.201.23:23:57.94#ibcon#*before write, iclass 28, count 2 2006.201.23:23:57.94#ibcon#enter sib2, iclass 28, count 2 2006.201.23:23:57.94#ibcon#flushed, iclass 28, count 2 2006.201.23:23:57.94#ibcon#about to write, iclass 28, count 2 2006.201.23:23:57.94#ibcon#wrote, iclass 28, count 2 2006.201.23:23:57.94#ibcon#about to read 3, iclass 28, count 2 2006.201.23:23:57.97#ibcon#read 3, iclass 28, count 2 2006.201.23:23:57.97#ibcon#about to read 4, iclass 28, count 2 2006.201.23:23:57.97#ibcon#read 4, iclass 28, count 2 2006.201.23:23:57.97#ibcon#about to read 5, iclass 28, count 2 2006.201.23:23:57.97#ibcon#read 5, iclass 28, count 2 2006.201.23:23:57.97#ibcon#about to read 6, iclass 28, count 2 2006.201.23:23:57.97#ibcon#read 6, iclass 28, count 2 2006.201.23:23:57.97#ibcon#end of sib2, iclass 28, count 2 2006.201.23:23:57.97#ibcon#*after write, iclass 28, count 2 2006.201.23:23:57.97#ibcon#*before return 0, iclass 28, count 2 2006.201.23:23:57.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:23:57.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:23:57.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.23:23:57.97#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:57.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:23:58.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:23:58.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:23:58.09#ibcon#enter wrdev, iclass 28, count 0 2006.201.23:23:58.09#ibcon#first serial, iclass 28, count 0 2006.201.23:23:58.09#ibcon#enter sib2, iclass 28, count 0 2006.201.23:23:58.09#ibcon#flushed, iclass 28, count 0 2006.201.23:23:58.09#ibcon#about to write, iclass 28, count 0 2006.201.23:23:58.09#ibcon#wrote, iclass 28, count 0 2006.201.23:23:58.09#ibcon#about to read 3, iclass 28, count 0 2006.201.23:23:58.11#ibcon#read 3, iclass 28, count 0 2006.201.23:23:58.11#ibcon#about to read 4, iclass 28, count 0 2006.201.23:23:58.11#ibcon#read 4, iclass 28, count 0 2006.201.23:23:58.11#ibcon#about to read 5, iclass 28, count 0 2006.201.23:23:58.11#ibcon#read 5, iclass 28, count 0 2006.201.23:23:58.11#ibcon#about to read 6, iclass 28, count 0 2006.201.23:23:58.11#ibcon#read 6, iclass 28, count 0 2006.201.23:23:58.11#ibcon#end of sib2, iclass 28, count 0 2006.201.23:23:58.11#ibcon#*mode == 0, iclass 28, count 0 2006.201.23:23:58.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.23:23:58.11#ibcon#[25=USB\r\n] 2006.201.23:23:58.11#ibcon#*before write, iclass 28, count 0 2006.201.23:23:58.11#ibcon#enter sib2, iclass 28, count 0 2006.201.23:23:58.11#ibcon#flushed, iclass 28, count 0 2006.201.23:23:58.11#ibcon#about to write, iclass 28, count 0 2006.201.23:23:58.11#ibcon#wrote, iclass 28, count 0 2006.201.23:23:58.11#ibcon#about to read 3, iclass 28, count 0 2006.201.23:23:58.14#ibcon#read 3, iclass 28, count 0 2006.201.23:23:58.14#ibcon#about to read 4, iclass 28, count 0 2006.201.23:23:58.14#ibcon#read 4, iclass 28, count 0 2006.201.23:23:58.14#ibcon#about to read 5, iclass 28, count 0 2006.201.23:23:58.14#ibcon#read 5, iclass 28, count 0 2006.201.23:23:58.14#ibcon#about to read 6, iclass 28, count 0 2006.201.23:23:58.14#ibcon#read 6, iclass 28, count 0 2006.201.23:23:58.14#ibcon#end of sib2, iclass 28, count 0 2006.201.23:23:58.14#ibcon#*after write, iclass 28, count 0 2006.201.23:23:58.14#ibcon#*before return 0, iclass 28, count 0 2006.201.23:23:58.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:23:58.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:23:58.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.23:23:58.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.23:23:58.14$vck44/valo=4,624.99 2006.201.23:23:58.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.23:23:58.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.23:23:58.14#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:58.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:23:58.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:23:58.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:23:58.14#ibcon#enter wrdev, iclass 30, count 0 2006.201.23:23:58.14#ibcon#first serial, iclass 30, count 0 2006.201.23:23:58.14#ibcon#enter sib2, iclass 30, count 0 2006.201.23:23:58.14#ibcon#flushed, iclass 30, count 0 2006.201.23:23:58.14#ibcon#about to write, iclass 30, count 0 2006.201.23:23:58.14#ibcon#wrote, iclass 30, count 0 2006.201.23:23:58.14#ibcon#about to read 3, iclass 30, count 0 2006.201.23:23:58.16#ibcon#read 3, iclass 30, count 0 2006.201.23:23:58.16#ibcon#about to read 4, iclass 30, count 0 2006.201.23:23:58.16#ibcon#read 4, iclass 30, count 0 2006.201.23:23:58.16#ibcon#about to read 5, iclass 30, count 0 2006.201.23:23:58.16#ibcon#read 5, iclass 30, count 0 2006.201.23:23:58.16#ibcon#about to read 6, iclass 30, count 0 2006.201.23:23:58.16#ibcon#read 6, iclass 30, count 0 2006.201.23:23:58.16#ibcon#end of sib2, iclass 30, count 0 2006.201.23:23:58.16#ibcon#*mode == 0, iclass 30, count 0 2006.201.23:23:58.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.23:23:58.16#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.23:23:58.16#ibcon#*before write, iclass 30, count 0 2006.201.23:23:58.16#ibcon#enter sib2, iclass 30, count 0 2006.201.23:23:58.16#ibcon#flushed, iclass 30, count 0 2006.201.23:23:58.16#ibcon#about to write, iclass 30, count 0 2006.201.23:23:58.16#ibcon#wrote, iclass 30, count 0 2006.201.23:23:58.16#ibcon#about to read 3, iclass 30, count 0 2006.201.23:23:58.20#ibcon#read 3, iclass 30, count 0 2006.201.23:23:58.20#ibcon#about to read 4, iclass 30, count 0 2006.201.23:23:58.20#ibcon#read 4, iclass 30, count 0 2006.201.23:23:58.20#ibcon#about to read 5, iclass 30, count 0 2006.201.23:23:58.20#ibcon#read 5, iclass 30, count 0 2006.201.23:23:58.20#ibcon#about to read 6, iclass 30, count 0 2006.201.23:23:58.20#ibcon#read 6, iclass 30, count 0 2006.201.23:23:58.20#ibcon#end of sib2, iclass 30, count 0 2006.201.23:23:58.20#ibcon#*after write, iclass 30, count 0 2006.201.23:23:58.20#ibcon#*before return 0, iclass 30, count 0 2006.201.23:23:58.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:23:58.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:23:58.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.23:23:58.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.23:23:58.20$vck44/va=4,7 2006.201.23:23:58.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.23:23:58.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.23:23:58.20#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:58.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:23:58.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:23:58.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:23:58.26#ibcon#enter wrdev, iclass 32, count 2 2006.201.23:23:58.26#ibcon#first serial, iclass 32, count 2 2006.201.23:23:58.26#ibcon#enter sib2, iclass 32, count 2 2006.201.23:23:58.26#ibcon#flushed, iclass 32, count 2 2006.201.23:23:58.26#ibcon#about to write, iclass 32, count 2 2006.201.23:23:58.26#ibcon#wrote, iclass 32, count 2 2006.201.23:23:58.26#ibcon#about to read 3, iclass 32, count 2 2006.201.23:23:58.28#ibcon#read 3, iclass 32, count 2 2006.201.23:23:58.28#ibcon#about to read 4, iclass 32, count 2 2006.201.23:23:58.28#ibcon#read 4, iclass 32, count 2 2006.201.23:23:58.28#ibcon#about to read 5, iclass 32, count 2 2006.201.23:23:58.28#ibcon#read 5, iclass 32, count 2 2006.201.23:23:58.28#ibcon#about to read 6, iclass 32, count 2 2006.201.23:23:58.28#ibcon#read 6, iclass 32, count 2 2006.201.23:23:58.28#ibcon#end of sib2, iclass 32, count 2 2006.201.23:23:58.28#ibcon#*mode == 0, iclass 32, count 2 2006.201.23:23:58.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.23:23:58.28#ibcon#[25=AT04-07\r\n] 2006.201.23:23:58.28#ibcon#*before write, iclass 32, count 2 2006.201.23:23:58.28#ibcon#enter sib2, iclass 32, count 2 2006.201.23:23:58.28#ibcon#flushed, iclass 32, count 2 2006.201.23:23:58.28#ibcon#about to write, iclass 32, count 2 2006.201.23:23:58.28#ibcon#wrote, iclass 32, count 2 2006.201.23:23:58.28#ibcon#about to read 3, iclass 32, count 2 2006.201.23:23:58.31#ibcon#read 3, iclass 32, count 2 2006.201.23:23:58.31#ibcon#about to read 4, iclass 32, count 2 2006.201.23:23:58.31#ibcon#read 4, iclass 32, count 2 2006.201.23:23:58.31#ibcon#about to read 5, iclass 32, count 2 2006.201.23:23:58.31#ibcon#read 5, iclass 32, count 2 2006.201.23:23:58.31#ibcon#about to read 6, iclass 32, count 2 2006.201.23:23:58.31#ibcon#read 6, iclass 32, count 2 2006.201.23:23:58.31#ibcon#end of sib2, iclass 32, count 2 2006.201.23:23:58.31#ibcon#*after write, iclass 32, count 2 2006.201.23:23:58.31#ibcon#*before return 0, iclass 32, count 2 2006.201.23:23:58.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:23:58.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:23:58.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.23:23:58.31#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:58.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:23:58.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:23:58.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:23:58.43#ibcon#enter wrdev, iclass 32, count 0 2006.201.23:23:58.43#ibcon#first serial, iclass 32, count 0 2006.201.23:23:58.43#ibcon#enter sib2, iclass 32, count 0 2006.201.23:23:58.43#ibcon#flushed, iclass 32, count 0 2006.201.23:23:58.43#ibcon#about to write, iclass 32, count 0 2006.201.23:23:58.43#ibcon#wrote, iclass 32, count 0 2006.201.23:23:58.43#ibcon#about to read 3, iclass 32, count 0 2006.201.23:23:58.45#ibcon#read 3, iclass 32, count 0 2006.201.23:23:58.45#ibcon#about to read 4, iclass 32, count 0 2006.201.23:23:58.45#ibcon#read 4, iclass 32, count 0 2006.201.23:23:58.45#ibcon#about to read 5, iclass 32, count 0 2006.201.23:23:58.45#ibcon#read 5, iclass 32, count 0 2006.201.23:23:58.45#ibcon#about to read 6, iclass 32, count 0 2006.201.23:23:58.45#ibcon#read 6, iclass 32, count 0 2006.201.23:23:58.45#ibcon#end of sib2, iclass 32, count 0 2006.201.23:23:58.45#ibcon#*mode == 0, iclass 32, count 0 2006.201.23:23:58.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.23:23:58.45#ibcon#[25=USB\r\n] 2006.201.23:23:58.45#ibcon#*before write, iclass 32, count 0 2006.201.23:23:58.45#ibcon#enter sib2, iclass 32, count 0 2006.201.23:23:58.45#ibcon#flushed, iclass 32, count 0 2006.201.23:23:58.45#ibcon#about to write, iclass 32, count 0 2006.201.23:23:58.45#ibcon#wrote, iclass 32, count 0 2006.201.23:23:58.45#ibcon#about to read 3, iclass 32, count 0 2006.201.23:23:58.48#ibcon#read 3, iclass 32, count 0 2006.201.23:23:58.48#ibcon#about to read 4, iclass 32, count 0 2006.201.23:23:58.48#ibcon#read 4, iclass 32, count 0 2006.201.23:23:58.48#ibcon#about to read 5, iclass 32, count 0 2006.201.23:23:58.48#ibcon#read 5, iclass 32, count 0 2006.201.23:23:58.48#ibcon#about to read 6, iclass 32, count 0 2006.201.23:23:58.48#ibcon#read 6, iclass 32, count 0 2006.201.23:23:58.48#ibcon#end of sib2, iclass 32, count 0 2006.201.23:23:58.48#ibcon#*after write, iclass 32, count 0 2006.201.23:23:58.48#ibcon#*before return 0, iclass 32, count 0 2006.201.23:23:58.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:23:58.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:23:58.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.23:23:58.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.23:23:58.48$vck44/valo=5,734.99 2006.201.23:23:58.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.23:23:58.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.23:23:58.48#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:58.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:23:58.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:23:58.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:23:58.48#ibcon#enter wrdev, iclass 34, count 0 2006.201.23:23:58.48#ibcon#first serial, iclass 34, count 0 2006.201.23:23:58.48#ibcon#enter sib2, iclass 34, count 0 2006.201.23:23:58.48#ibcon#flushed, iclass 34, count 0 2006.201.23:23:58.48#ibcon#about to write, iclass 34, count 0 2006.201.23:23:58.48#ibcon#wrote, iclass 34, count 0 2006.201.23:23:58.48#ibcon#about to read 3, iclass 34, count 0 2006.201.23:23:58.50#ibcon#read 3, iclass 34, count 0 2006.201.23:23:58.50#ibcon#about to read 4, iclass 34, count 0 2006.201.23:23:58.50#ibcon#read 4, iclass 34, count 0 2006.201.23:23:58.50#ibcon#about to read 5, iclass 34, count 0 2006.201.23:23:58.50#ibcon#read 5, iclass 34, count 0 2006.201.23:23:58.50#ibcon#about to read 6, iclass 34, count 0 2006.201.23:23:58.50#ibcon#read 6, iclass 34, count 0 2006.201.23:23:58.50#ibcon#end of sib2, iclass 34, count 0 2006.201.23:23:58.50#ibcon#*mode == 0, iclass 34, count 0 2006.201.23:23:58.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.23:23:58.50#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.23:23:58.50#ibcon#*before write, iclass 34, count 0 2006.201.23:23:58.50#ibcon#enter sib2, iclass 34, count 0 2006.201.23:23:58.50#ibcon#flushed, iclass 34, count 0 2006.201.23:23:58.50#ibcon#about to write, iclass 34, count 0 2006.201.23:23:58.50#ibcon#wrote, iclass 34, count 0 2006.201.23:23:58.50#ibcon#about to read 3, iclass 34, count 0 2006.201.23:23:58.54#ibcon#read 3, iclass 34, count 0 2006.201.23:23:58.54#ibcon#about to read 4, iclass 34, count 0 2006.201.23:23:58.54#ibcon#read 4, iclass 34, count 0 2006.201.23:23:58.54#ibcon#about to read 5, iclass 34, count 0 2006.201.23:23:58.54#ibcon#read 5, iclass 34, count 0 2006.201.23:23:58.54#ibcon#about to read 6, iclass 34, count 0 2006.201.23:23:58.54#ibcon#read 6, iclass 34, count 0 2006.201.23:23:58.54#ibcon#end of sib2, iclass 34, count 0 2006.201.23:23:58.54#ibcon#*after write, iclass 34, count 0 2006.201.23:23:58.54#ibcon#*before return 0, iclass 34, count 0 2006.201.23:23:58.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:23:58.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:23:58.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.23:23:58.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.23:23:58.54$vck44/va=5,4 2006.201.23:23:58.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.23:23:58.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.23:23:58.54#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:58.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:23:58.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:23:58.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:23:58.60#ibcon#enter wrdev, iclass 36, count 2 2006.201.23:23:58.60#ibcon#first serial, iclass 36, count 2 2006.201.23:23:58.60#ibcon#enter sib2, iclass 36, count 2 2006.201.23:23:58.60#ibcon#flushed, iclass 36, count 2 2006.201.23:23:58.60#ibcon#about to write, iclass 36, count 2 2006.201.23:23:58.60#ibcon#wrote, iclass 36, count 2 2006.201.23:23:58.60#ibcon#about to read 3, iclass 36, count 2 2006.201.23:23:58.62#ibcon#read 3, iclass 36, count 2 2006.201.23:23:58.62#ibcon#about to read 4, iclass 36, count 2 2006.201.23:23:58.62#ibcon#read 4, iclass 36, count 2 2006.201.23:23:58.62#ibcon#about to read 5, iclass 36, count 2 2006.201.23:23:58.62#ibcon#read 5, iclass 36, count 2 2006.201.23:23:58.62#ibcon#about to read 6, iclass 36, count 2 2006.201.23:23:58.62#ibcon#read 6, iclass 36, count 2 2006.201.23:23:58.62#ibcon#end of sib2, iclass 36, count 2 2006.201.23:23:58.62#ibcon#*mode == 0, iclass 36, count 2 2006.201.23:23:58.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.23:23:58.62#ibcon#[25=AT05-04\r\n] 2006.201.23:23:58.62#ibcon#*before write, iclass 36, count 2 2006.201.23:23:58.62#ibcon#enter sib2, iclass 36, count 2 2006.201.23:23:58.62#ibcon#flushed, iclass 36, count 2 2006.201.23:23:58.62#ibcon#about to write, iclass 36, count 2 2006.201.23:23:58.62#ibcon#wrote, iclass 36, count 2 2006.201.23:23:58.62#ibcon#about to read 3, iclass 36, count 2 2006.201.23:23:58.65#ibcon#read 3, iclass 36, count 2 2006.201.23:23:58.65#ibcon#about to read 4, iclass 36, count 2 2006.201.23:23:58.65#ibcon#read 4, iclass 36, count 2 2006.201.23:23:58.65#ibcon#about to read 5, iclass 36, count 2 2006.201.23:23:58.65#ibcon#read 5, iclass 36, count 2 2006.201.23:23:58.65#ibcon#about to read 6, iclass 36, count 2 2006.201.23:23:58.65#ibcon#read 6, iclass 36, count 2 2006.201.23:23:58.65#ibcon#end of sib2, iclass 36, count 2 2006.201.23:23:58.65#ibcon#*after write, iclass 36, count 2 2006.201.23:23:58.65#ibcon#*before return 0, iclass 36, count 2 2006.201.23:23:58.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:23:58.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:23:58.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.23:23:58.65#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:58.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:23:58.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:23:58.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:23:58.77#ibcon#enter wrdev, iclass 36, count 0 2006.201.23:23:58.77#ibcon#first serial, iclass 36, count 0 2006.201.23:23:58.77#ibcon#enter sib2, iclass 36, count 0 2006.201.23:23:58.77#ibcon#flushed, iclass 36, count 0 2006.201.23:23:58.77#ibcon#about to write, iclass 36, count 0 2006.201.23:23:58.77#ibcon#wrote, iclass 36, count 0 2006.201.23:23:58.77#ibcon#about to read 3, iclass 36, count 0 2006.201.23:23:58.79#ibcon#read 3, iclass 36, count 0 2006.201.23:23:58.79#ibcon#about to read 4, iclass 36, count 0 2006.201.23:23:58.79#ibcon#read 4, iclass 36, count 0 2006.201.23:23:58.79#ibcon#about to read 5, iclass 36, count 0 2006.201.23:23:58.79#ibcon#read 5, iclass 36, count 0 2006.201.23:23:58.79#ibcon#about to read 6, iclass 36, count 0 2006.201.23:23:58.79#ibcon#read 6, iclass 36, count 0 2006.201.23:23:58.79#ibcon#end of sib2, iclass 36, count 0 2006.201.23:23:58.79#ibcon#*mode == 0, iclass 36, count 0 2006.201.23:23:58.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.23:23:58.79#ibcon#[25=USB\r\n] 2006.201.23:23:58.79#ibcon#*before write, iclass 36, count 0 2006.201.23:23:58.79#ibcon#enter sib2, iclass 36, count 0 2006.201.23:23:58.79#ibcon#flushed, iclass 36, count 0 2006.201.23:23:58.79#ibcon#about to write, iclass 36, count 0 2006.201.23:23:58.79#ibcon#wrote, iclass 36, count 0 2006.201.23:23:58.79#ibcon#about to read 3, iclass 36, count 0 2006.201.23:23:58.82#ibcon#read 3, iclass 36, count 0 2006.201.23:23:58.82#ibcon#about to read 4, iclass 36, count 0 2006.201.23:23:58.82#ibcon#read 4, iclass 36, count 0 2006.201.23:23:58.82#ibcon#about to read 5, iclass 36, count 0 2006.201.23:23:58.82#ibcon#read 5, iclass 36, count 0 2006.201.23:23:58.82#ibcon#about to read 6, iclass 36, count 0 2006.201.23:23:58.82#ibcon#read 6, iclass 36, count 0 2006.201.23:23:58.82#ibcon#end of sib2, iclass 36, count 0 2006.201.23:23:58.82#ibcon#*after write, iclass 36, count 0 2006.201.23:23:58.82#ibcon#*before return 0, iclass 36, count 0 2006.201.23:23:58.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:23:58.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:23:58.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.23:23:58.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.23:23:58.82$vck44/valo=6,814.99 2006.201.23:23:58.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.23:23:58.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.23:23:58.82#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:58.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:23:58.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:23:58.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:23:58.82#ibcon#enter wrdev, iclass 38, count 0 2006.201.23:23:58.82#ibcon#first serial, iclass 38, count 0 2006.201.23:23:58.82#ibcon#enter sib2, iclass 38, count 0 2006.201.23:23:58.82#ibcon#flushed, iclass 38, count 0 2006.201.23:23:58.82#ibcon#about to write, iclass 38, count 0 2006.201.23:23:58.82#ibcon#wrote, iclass 38, count 0 2006.201.23:23:58.82#ibcon#about to read 3, iclass 38, count 0 2006.201.23:23:58.84#ibcon#read 3, iclass 38, count 0 2006.201.23:23:58.84#ibcon#about to read 4, iclass 38, count 0 2006.201.23:23:58.84#ibcon#read 4, iclass 38, count 0 2006.201.23:23:58.84#ibcon#about to read 5, iclass 38, count 0 2006.201.23:23:58.84#ibcon#read 5, iclass 38, count 0 2006.201.23:23:58.84#ibcon#about to read 6, iclass 38, count 0 2006.201.23:23:58.84#ibcon#read 6, iclass 38, count 0 2006.201.23:23:58.84#ibcon#end of sib2, iclass 38, count 0 2006.201.23:23:58.84#ibcon#*mode == 0, iclass 38, count 0 2006.201.23:23:58.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.23:23:58.84#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.23:23:58.84#ibcon#*before write, iclass 38, count 0 2006.201.23:23:58.84#ibcon#enter sib2, iclass 38, count 0 2006.201.23:23:58.84#ibcon#flushed, iclass 38, count 0 2006.201.23:23:58.84#ibcon#about to write, iclass 38, count 0 2006.201.23:23:58.84#ibcon#wrote, iclass 38, count 0 2006.201.23:23:58.84#ibcon#about to read 3, iclass 38, count 0 2006.201.23:23:58.88#ibcon#read 3, iclass 38, count 0 2006.201.23:23:58.88#ibcon#about to read 4, iclass 38, count 0 2006.201.23:23:58.88#ibcon#read 4, iclass 38, count 0 2006.201.23:23:58.88#ibcon#about to read 5, iclass 38, count 0 2006.201.23:23:58.88#ibcon#read 5, iclass 38, count 0 2006.201.23:23:58.88#ibcon#about to read 6, iclass 38, count 0 2006.201.23:23:58.88#ibcon#read 6, iclass 38, count 0 2006.201.23:23:58.88#ibcon#end of sib2, iclass 38, count 0 2006.201.23:23:58.88#ibcon#*after write, iclass 38, count 0 2006.201.23:23:58.88#ibcon#*before return 0, iclass 38, count 0 2006.201.23:23:58.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:23:58.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:23:58.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.23:23:58.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.23:23:58.88$vck44/va=6,5 2006.201.23:23:58.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.23:23:58.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.23:23:58.88#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:58.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:23:58.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:23:58.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:23:58.94#ibcon#enter wrdev, iclass 40, count 2 2006.201.23:23:58.94#ibcon#first serial, iclass 40, count 2 2006.201.23:23:58.94#ibcon#enter sib2, iclass 40, count 2 2006.201.23:23:58.94#ibcon#flushed, iclass 40, count 2 2006.201.23:23:58.94#ibcon#about to write, iclass 40, count 2 2006.201.23:23:58.94#ibcon#wrote, iclass 40, count 2 2006.201.23:23:58.94#ibcon#about to read 3, iclass 40, count 2 2006.201.23:23:58.96#ibcon#read 3, iclass 40, count 2 2006.201.23:23:58.96#ibcon#about to read 4, iclass 40, count 2 2006.201.23:23:58.96#ibcon#read 4, iclass 40, count 2 2006.201.23:23:58.96#ibcon#about to read 5, iclass 40, count 2 2006.201.23:23:58.96#ibcon#read 5, iclass 40, count 2 2006.201.23:23:58.96#ibcon#about to read 6, iclass 40, count 2 2006.201.23:23:58.96#ibcon#read 6, iclass 40, count 2 2006.201.23:23:58.96#ibcon#end of sib2, iclass 40, count 2 2006.201.23:23:58.96#ibcon#*mode == 0, iclass 40, count 2 2006.201.23:23:58.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.23:23:58.96#ibcon#[25=AT06-05\r\n] 2006.201.23:23:58.96#ibcon#*before write, iclass 40, count 2 2006.201.23:23:58.96#ibcon#enter sib2, iclass 40, count 2 2006.201.23:23:58.96#ibcon#flushed, iclass 40, count 2 2006.201.23:23:58.96#ibcon#about to write, iclass 40, count 2 2006.201.23:23:58.96#ibcon#wrote, iclass 40, count 2 2006.201.23:23:58.96#ibcon#about to read 3, iclass 40, count 2 2006.201.23:23:58.99#ibcon#read 3, iclass 40, count 2 2006.201.23:23:58.99#ibcon#about to read 4, iclass 40, count 2 2006.201.23:23:58.99#ibcon#read 4, iclass 40, count 2 2006.201.23:23:58.99#ibcon#about to read 5, iclass 40, count 2 2006.201.23:23:58.99#ibcon#read 5, iclass 40, count 2 2006.201.23:23:58.99#ibcon#about to read 6, iclass 40, count 2 2006.201.23:23:58.99#ibcon#read 6, iclass 40, count 2 2006.201.23:23:58.99#ibcon#end of sib2, iclass 40, count 2 2006.201.23:23:58.99#ibcon#*after write, iclass 40, count 2 2006.201.23:23:58.99#ibcon#*before return 0, iclass 40, count 2 2006.201.23:23:58.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:23:58.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:23:58.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.23:23:58.99#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:58.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:23:59.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:23:59.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:23:59.11#ibcon#enter wrdev, iclass 40, count 0 2006.201.23:23:59.11#ibcon#first serial, iclass 40, count 0 2006.201.23:23:59.11#ibcon#enter sib2, iclass 40, count 0 2006.201.23:23:59.11#ibcon#flushed, iclass 40, count 0 2006.201.23:23:59.11#ibcon#about to write, iclass 40, count 0 2006.201.23:23:59.11#ibcon#wrote, iclass 40, count 0 2006.201.23:23:59.11#ibcon#about to read 3, iclass 40, count 0 2006.201.23:23:59.13#ibcon#read 3, iclass 40, count 0 2006.201.23:23:59.13#ibcon#about to read 4, iclass 40, count 0 2006.201.23:23:59.13#ibcon#read 4, iclass 40, count 0 2006.201.23:23:59.13#ibcon#about to read 5, iclass 40, count 0 2006.201.23:23:59.13#ibcon#read 5, iclass 40, count 0 2006.201.23:23:59.13#ibcon#about to read 6, iclass 40, count 0 2006.201.23:23:59.13#ibcon#read 6, iclass 40, count 0 2006.201.23:23:59.13#ibcon#end of sib2, iclass 40, count 0 2006.201.23:23:59.13#ibcon#*mode == 0, iclass 40, count 0 2006.201.23:23:59.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.23:23:59.13#ibcon#[25=USB\r\n] 2006.201.23:23:59.13#ibcon#*before write, iclass 40, count 0 2006.201.23:23:59.13#ibcon#enter sib2, iclass 40, count 0 2006.201.23:23:59.13#ibcon#flushed, iclass 40, count 0 2006.201.23:23:59.13#ibcon#about to write, iclass 40, count 0 2006.201.23:23:59.13#ibcon#wrote, iclass 40, count 0 2006.201.23:23:59.13#ibcon#about to read 3, iclass 40, count 0 2006.201.23:23:59.16#ibcon#read 3, iclass 40, count 0 2006.201.23:23:59.16#ibcon#about to read 4, iclass 40, count 0 2006.201.23:23:59.16#ibcon#read 4, iclass 40, count 0 2006.201.23:23:59.16#ibcon#about to read 5, iclass 40, count 0 2006.201.23:23:59.16#ibcon#read 5, iclass 40, count 0 2006.201.23:23:59.16#ibcon#about to read 6, iclass 40, count 0 2006.201.23:23:59.16#ibcon#read 6, iclass 40, count 0 2006.201.23:23:59.16#ibcon#end of sib2, iclass 40, count 0 2006.201.23:23:59.16#ibcon#*after write, iclass 40, count 0 2006.201.23:23:59.16#ibcon#*before return 0, iclass 40, count 0 2006.201.23:23:59.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:23:59.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:23:59.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.23:23:59.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.23:23:59.16$vck44/valo=7,864.99 2006.201.23:23:59.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.23:23:59.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.23:23:59.16#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:59.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:23:59.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:23:59.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:23:59.16#ibcon#enter wrdev, iclass 4, count 0 2006.201.23:23:59.16#ibcon#first serial, iclass 4, count 0 2006.201.23:23:59.16#ibcon#enter sib2, iclass 4, count 0 2006.201.23:23:59.16#ibcon#flushed, iclass 4, count 0 2006.201.23:23:59.16#ibcon#about to write, iclass 4, count 0 2006.201.23:23:59.16#ibcon#wrote, iclass 4, count 0 2006.201.23:23:59.16#ibcon#about to read 3, iclass 4, count 0 2006.201.23:23:59.18#ibcon#read 3, iclass 4, count 0 2006.201.23:23:59.18#ibcon#about to read 4, iclass 4, count 0 2006.201.23:23:59.18#ibcon#read 4, iclass 4, count 0 2006.201.23:23:59.18#ibcon#about to read 5, iclass 4, count 0 2006.201.23:23:59.18#ibcon#read 5, iclass 4, count 0 2006.201.23:23:59.18#ibcon#about to read 6, iclass 4, count 0 2006.201.23:23:59.18#ibcon#read 6, iclass 4, count 0 2006.201.23:23:59.18#ibcon#end of sib2, iclass 4, count 0 2006.201.23:23:59.18#ibcon#*mode == 0, iclass 4, count 0 2006.201.23:23:59.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.23:23:59.18#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.23:23:59.18#ibcon#*before write, iclass 4, count 0 2006.201.23:23:59.18#ibcon#enter sib2, iclass 4, count 0 2006.201.23:23:59.18#ibcon#flushed, iclass 4, count 0 2006.201.23:23:59.18#ibcon#about to write, iclass 4, count 0 2006.201.23:23:59.18#ibcon#wrote, iclass 4, count 0 2006.201.23:23:59.18#ibcon#about to read 3, iclass 4, count 0 2006.201.23:23:59.22#ibcon#read 3, iclass 4, count 0 2006.201.23:23:59.22#ibcon#about to read 4, iclass 4, count 0 2006.201.23:23:59.22#ibcon#read 4, iclass 4, count 0 2006.201.23:23:59.22#ibcon#about to read 5, iclass 4, count 0 2006.201.23:23:59.22#ibcon#read 5, iclass 4, count 0 2006.201.23:23:59.22#ibcon#about to read 6, iclass 4, count 0 2006.201.23:23:59.22#ibcon#read 6, iclass 4, count 0 2006.201.23:23:59.22#ibcon#end of sib2, iclass 4, count 0 2006.201.23:23:59.22#ibcon#*after write, iclass 4, count 0 2006.201.23:23:59.22#ibcon#*before return 0, iclass 4, count 0 2006.201.23:23:59.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:23:59.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:23:59.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.23:23:59.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.23:23:59.22$vck44/va=7,5 2006.201.23:23:59.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.23:23:59.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.23:23:59.22#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:59.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:23:59.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:23:59.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:23:59.28#ibcon#enter wrdev, iclass 6, count 2 2006.201.23:23:59.28#ibcon#first serial, iclass 6, count 2 2006.201.23:23:59.28#ibcon#enter sib2, iclass 6, count 2 2006.201.23:23:59.28#ibcon#flushed, iclass 6, count 2 2006.201.23:23:59.28#ibcon#about to write, iclass 6, count 2 2006.201.23:23:59.28#ibcon#wrote, iclass 6, count 2 2006.201.23:23:59.28#ibcon#about to read 3, iclass 6, count 2 2006.201.23:23:59.30#ibcon#read 3, iclass 6, count 2 2006.201.23:23:59.30#ibcon#about to read 4, iclass 6, count 2 2006.201.23:23:59.30#ibcon#read 4, iclass 6, count 2 2006.201.23:23:59.30#ibcon#about to read 5, iclass 6, count 2 2006.201.23:23:59.30#ibcon#read 5, iclass 6, count 2 2006.201.23:23:59.30#ibcon#about to read 6, iclass 6, count 2 2006.201.23:23:59.30#ibcon#read 6, iclass 6, count 2 2006.201.23:23:59.30#ibcon#end of sib2, iclass 6, count 2 2006.201.23:23:59.30#ibcon#*mode == 0, iclass 6, count 2 2006.201.23:23:59.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.23:23:59.30#ibcon#[25=AT07-05\r\n] 2006.201.23:23:59.30#ibcon#*before write, iclass 6, count 2 2006.201.23:23:59.30#ibcon#enter sib2, iclass 6, count 2 2006.201.23:23:59.30#ibcon#flushed, iclass 6, count 2 2006.201.23:23:59.30#ibcon#about to write, iclass 6, count 2 2006.201.23:23:59.30#ibcon#wrote, iclass 6, count 2 2006.201.23:23:59.30#ibcon#about to read 3, iclass 6, count 2 2006.201.23:23:59.33#ibcon#read 3, iclass 6, count 2 2006.201.23:23:59.33#ibcon#about to read 4, iclass 6, count 2 2006.201.23:23:59.33#ibcon#read 4, iclass 6, count 2 2006.201.23:23:59.33#ibcon#about to read 5, iclass 6, count 2 2006.201.23:23:59.33#ibcon#read 5, iclass 6, count 2 2006.201.23:23:59.33#ibcon#about to read 6, iclass 6, count 2 2006.201.23:23:59.33#ibcon#read 6, iclass 6, count 2 2006.201.23:23:59.33#ibcon#end of sib2, iclass 6, count 2 2006.201.23:23:59.33#ibcon#*after write, iclass 6, count 2 2006.201.23:23:59.33#ibcon#*before return 0, iclass 6, count 2 2006.201.23:23:59.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:23:59.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:23:59.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.23:23:59.33#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:59.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:23:59.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:23:59.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:23:59.45#ibcon#enter wrdev, iclass 6, count 0 2006.201.23:23:59.45#ibcon#first serial, iclass 6, count 0 2006.201.23:23:59.45#ibcon#enter sib2, iclass 6, count 0 2006.201.23:23:59.45#ibcon#flushed, iclass 6, count 0 2006.201.23:23:59.45#ibcon#about to write, iclass 6, count 0 2006.201.23:23:59.45#ibcon#wrote, iclass 6, count 0 2006.201.23:23:59.45#ibcon#about to read 3, iclass 6, count 0 2006.201.23:23:59.47#ibcon#read 3, iclass 6, count 0 2006.201.23:23:59.47#ibcon#about to read 4, iclass 6, count 0 2006.201.23:23:59.47#ibcon#read 4, iclass 6, count 0 2006.201.23:23:59.47#ibcon#about to read 5, iclass 6, count 0 2006.201.23:23:59.47#ibcon#read 5, iclass 6, count 0 2006.201.23:23:59.47#ibcon#about to read 6, iclass 6, count 0 2006.201.23:23:59.47#ibcon#read 6, iclass 6, count 0 2006.201.23:23:59.47#ibcon#end of sib2, iclass 6, count 0 2006.201.23:23:59.47#ibcon#*mode == 0, iclass 6, count 0 2006.201.23:23:59.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.23:23:59.47#ibcon#[25=USB\r\n] 2006.201.23:23:59.47#ibcon#*before write, iclass 6, count 0 2006.201.23:23:59.47#ibcon#enter sib2, iclass 6, count 0 2006.201.23:23:59.47#ibcon#flushed, iclass 6, count 0 2006.201.23:23:59.47#ibcon#about to write, iclass 6, count 0 2006.201.23:23:59.47#ibcon#wrote, iclass 6, count 0 2006.201.23:23:59.47#ibcon#about to read 3, iclass 6, count 0 2006.201.23:23:59.50#ibcon#read 3, iclass 6, count 0 2006.201.23:23:59.50#ibcon#about to read 4, iclass 6, count 0 2006.201.23:23:59.50#ibcon#read 4, iclass 6, count 0 2006.201.23:23:59.50#ibcon#about to read 5, iclass 6, count 0 2006.201.23:23:59.50#ibcon#read 5, iclass 6, count 0 2006.201.23:23:59.50#ibcon#about to read 6, iclass 6, count 0 2006.201.23:23:59.50#ibcon#read 6, iclass 6, count 0 2006.201.23:23:59.50#ibcon#end of sib2, iclass 6, count 0 2006.201.23:23:59.50#ibcon#*after write, iclass 6, count 0 2006.201.23:23:59.50#ibcon#*before return 0, iclass 6, count 0 2006.201.23:23:59.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:23:59.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:23:59.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.23:23:59.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.23:23:59.50$vck44/valo=8,884.99 2006.201.23:23:59.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.23:23:59.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.23:23:59.50#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:59.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:23:59.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:23:59.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:23:59.50#ibcon#enter wrdev, iclass 10, count 0 2006.201.23:23:59.50#ibcon#first serial, iclass 10, count 0 2006.201.23:23:59.50#ibcon#enter sib2, iclass 10, count 0 2006.201.23:23:59.50#ibcon#flushed, iclass 10, count 0 2006.201.23:23:59.50#ibcon#about to write, iclass 10, count 0 2006.201.23:23:59.50#ibcon#wrote, iclass 10, count 0 2006.201.23:23:59.50#ibcon#about to read 3, iclass 10, count 0 2006.201.23:23:59.52#ibcon#read 3, iclass 10, count 0 2006.201.23:23:59.52#ibcon#about to read 4, iclass 10, count 0 2006.201.23:23:59.52#ibcon#read 4, iclass 10, count 0 2006.201.23:23:59.52#ibcon#about to read 5, iclass 10, count 0 2006.201.23:23:59.52#ibcon#read 5, iclass 10, count 0 2006.201.23:23:59.52#ibcon#about to read 6, iclass 10, count 0 2006.201.23:23:59.52#ibcon#read 6, iclass 10, count 0 2006.201.23:23:59.52#ibcon#end of sib2, iclass 10, count 0 2006.201.23:23:59.52#ibcon#*mode == 0, iclass 10, count 0 2006.201.23:23:59.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.23:23:59.52#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.23:23:59.52#ibcon#*before write, iclass 10, count 0 2006.201.23:23:59.52#ibcon#enter sib2, iclass 10, count 0 2006.201.23:23:59.52#ibcon#flushed, iclass 10, count 0 2006.201.23:23:59.52#ibcon#about to write, iclass 10, count 0 2006.201.23:23:59.52#ibcon#wrote, iclass 10, count 0 2006.201.23:23:59.52#ibcon#about to read 3, iclass 10, count 0 2006.201.23:23:59.56#ibcon#read 3, iclass 10, count 0 2006.201.23:23:59.56#ibcon#about to read 4, iclass 10, count 0 2006.201.23:23:59.56#ibcon#read 4, iclass 10, count 0 2006.201.23:23:59.56#ibcon#about to read 5, iclass 10, count 0 2006.201.23:23:59.56#ibcon#read 5, iclass 10, count 0 2006.201.23:23:59.56#ibcon#about to read 6, iclass 10, count 0 2006.201.23:23:59.56#ibcon#read 6, iclass 10, count 0 2006.201.23:23:59.56#ibcon#end of sib2, iclass 10, count 0 2006.201.23:23:59.56#ibcon#*after write, iclass 10, count 0 2006.201.23:23:59.56#ibcon#*before return 0, iclass 10, count 0 2006.201.23:23:59.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:23:59.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:23:59.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.23:23:59.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.23:23:59.56$vck44/va=8,4 2006.201.23:23:59.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.23:23:59.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.23:23:59.56#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:59.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:23:59.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:23:59.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:23:59.62#ibcon#enter wrdev, iclass 12, count 2 2006.201.23:23:59.62#ibcon#first serial, iclass 12, count 2 2006.201.23:23:59.62#ibcon#enter sib2, iclass 12, count 2 2006.201.23:23:59.62#ibcon#flushed, iclass 12, count 2 2006.201.23:23:59.62#ibcon#about to write, iclass 12, count 2 2006.201.23:23:59.62#ibcon#wrote, iclass 12, count 2 2006.201.23:23:59.62#ibcon#about to read 3, iclass 12, count 2 2006.201.23:23:59.64#ibcon#read 3, iclass 12, count 2 2006.201.23:23:59.64#ibcon#about to read 4, iclass 12, count 2 2006.201.23:23:59.64#ibcon#read 4, iclass 12, count 2 2006.201.23:23:59.64#ibcon#about to read 5, iclass 12, count 2 2006.201.23:23:59.64#ibcon#read 5, iclass 12, count 2 2006.201.23:23:59.64#ibcon#about to read 6, iclass 12, count 2 2006.201.23:23:59.64#ibcon#read 6, iclass 12, count 2 2006.201.23:23:59.64#ibcon#end of sib2, iclass 12, count 2 2006.201.23:23:59.64#ibcon#*mode == 0, iclass 12, count 2 2006.201.23:23:59.64#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.23:23:59.64#ibcon#[25=AT08-04\r\n] 2006.201.23:23:59.64#ibcon#*before write, iclass 12, count 2 2006.201.23:23:59.64#ibcon#enter sib2, iclass 12, count 2 2006.201.23:23:59.64#ibcon#flushed, iclass 12, count 2 2006.201.23:23:59.64#ibcon#about to write, iclass 12, count 2 2006.201.23:23:59.64#ibcon#wrote, iclass 12, count 2 2006.201.23:23:59.64#ibcon#about to read 3, iclass 12, count 2 2006.201.23:23:59.67#ibcon#read 3, iclass 12, count 2 2006.201.23:23:59.67#ibcon#about to read 4, iclass 12, count 2 2006.201.23:23:59.67#ibcon#read 4, iclass 12, count 2 2006.201.23:23:59.67#ibcon#about to read 5, iclass 12, count 2 2006.201.23:23:59.67#ibcon#read 5, iclass 12, count 2 2006.201.23:23:59.67#ibcon#about to read 6, iclass 12, count 2 2006.201.23:23:59.67#ibcon#read 6, iclass 12, count 2 2006.201.23:23:59.67#ibcon#end of sib2, iclass 12, count 2 2006.201.23:23:59.67#ibcon#*after write, iclass 12, count 2 2006.201.23:23:59.67#ibcon#*before return 0, iclass 12, count 2 2006.201.23:23:59.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:23:59.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:23:59.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.23:23:59.67#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:59.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:23:59.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:23:59.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:23:59.79#ibcon#enter wrdev, iclass 12, count 0 2006.201.23:23:59.79#ibcon#first serial, iclass 12, count 0 2006.201.23:23:59.79#ibcon#enter sib2, iclass 12, count 0 2006.201.23:23:59.79#ibcon#flushed, iclass 12, count 0 2006.201.23:23:59.79#ibcon#about to write, iclass 12, count 0 2006.201.23:23:59.79#ibcon#wrote, iclass 12, count 0 2006.201.23:23:59.79#ibcon#about to read 3, iclass 12, count 0 2006.201.23:23:59.81#ibcon#read 3, iclass 12, count 0 2006.201.23:23:59.81#ibcon#about to read 4, iclass 12, count 0 2006.201.23:23:59.81#ibcon#read 4, iclass 12, count 0 2006.201.23:23:59.81#ibcon#about to read 5, iclass 12, count 0 2006.201.23:23:59.81#ibcon#read 5, iclass 12, count 0 2006.201.23:23:59.81#ibcon#about to read 6, iclass 12, count 0 2006.201.23:23:59.81#ibcon#read 6, iclass 12, count 0 2006.201.23:23:59.81#ibcon#end of sib2, iclass 12, count 0 2006.201.23:23:59.81#ibcon#*mode == 0, iclass 12, count 0 2006.201.23:23:59.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.23:23:59.81#ibcon#[25=USB\r\n] 2006.201.23:23:59.81#ibcon#*before write, iclass 12, count 0 2006.201.23:23:59.81#ibcon#enter sib2, iclass 12, count 0 2006.201.23:23:59.81#ibcon#flushed, iclass 12, count 0 2006.201.23:23:59.81#ibcon#about to write, iclass 12, count 0 2006.201.23:23:59.81#ibcon#wrote, iclass 12, count 0 2006.201.23:23:59.81#ibcon#about to read 3, iclass 12, count 0 2006.201.23:23:59.84#ibcon#read 3, iclass 12, count 0 2006.201.23:23:59.84#ibcon#about to read 4, iclass 12, count 0 2006.201.23:23:59.84#ibcon#read 4, iclass 12, count 0 2006.201.23:23:59.84#ibcon#about to read 5, iclass 12, count 0 2006.201.23:23:59.84#ibcon#read 5, iclass 12, count 0 2006.201.23:23:59.84#ibcon#about to read 6, iclass 12, count 0 2006.201.23:23:59.84#ibcon#read 6, iclass 12, count 0 2006.201.23:23:59.84#ibcon#end of sib2, iclass 12, count 0 2006.201.23:23:59.84#ibcon#*after write, iclass 12, count 0 2006.201.23:23:59.84#ibcon#*before return 0, iclass 12, count 0 2006.201.23:23:59.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:23:59.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:23:59.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.23:23:59.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.23:23:59.84$vck44/vblo=1,629.99 2006.201.23:23:59.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.23:23:59.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.23:23:59.84#ibcon#ireg 17 cls_cnt 0 2006.201.23:23:59.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:23:59.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:23:59.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:23:59.84#ibcon#enter wrdev, iclass 14, count 0 2006.201.23:23:59.84#ibcon#first serial, iclass 14, count 0 2006.201.23:23:59.84#ibcon#enter sib2, iclass 14, count 0 2006.201.23:23:59.84#ibcon#flushed, iclass 14, count 0 2006.201.23:23:59.84#ibcon#about to write, iclass 14, count 0 2006.201.23:23:59.84#ibcon#wrote, iclass 14, count 0 2006.201.23:23:59.84#ibcon#about to read 3, iclass 14, count 0 2006.201.23:23:59.86#ibcon#read 3, iclass 14, count 0 2006.201.23:23:59.86#ibcon#about to read 4, iclass 14, count 0 2006.201.23:23:59.86#ibcon#read 4, iclass 14, count 0 2006.201.23:23:59.86#ibcon#about to read 5, iclass 14, count 0 2006.201.23:23:59.86#ibcon#read 5, iclass 14, count 0 2006.201.23:23:59.86#ibcon#about to read 6, iclass 14, count 0 2006.201.23:23:59.86#ibcon#read 6, iclass 14, count 0 2006.201.23:23:59.86#ibcon#end of sib2, iclass 14, count 0 2006.201.23:23:59.86#ibcon#*mode == 0, iclass 14, count 0 2006.201.23:23:59.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.23:23:59.86#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.23:23:59.86#ibcon#*before write, iclass 14, count 0 2006.201.23:23:59.86#ibcon#enter sib2, iclass 14, count 0 2006.201.23:23:59.86#ibcon#flushed, iclass 14, count 0 2006.201.23:23:59.86#ibcon#about to write, iclass 14, count 0 2006.201.23:23:59.86#ibcon#wrote, iclass 14, count 0 2006.201.23:23:59.86#ibcon#about to read 3, iclass 14, count 0 2006.201.23:23:59.90#ibcon#read 3, iclass 14, count 0 2006.201.23:23:59.90#ibcon#about to read 4, iclass 14, count 0 2006.201.23:23:59.90#ibcon#read 4, iclass 14, count 0 2006.201.23:23:59.90#ibcon#about to read 5, iclass 14, count 0 2006.201.23:23:59.90#ibcon#read 5, iclass 14, count 0 2006.201.23:23:59.90#ibcon#about to read 6, iclass 14, count 0 2006.201.23:23:59.90#ibcon#read 6, iclass 14, count 0 2006.201.23:23:59.90#ibcon#end of sib2, iclass 14, count 0 2006.201.23:23:59.90#ibcon#*after write, iclass 14, count 0 2006.201.23:23:59.90#ibcon#*before return 0, iclass 14, count 0 2006.201.23:23:59.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:23:59.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:23:59.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.23:23:59.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.23:23:59.90$vck44/vb=1,4 2006.201.23:23:59.90#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.23:23:59.90#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.23:23:59.90#ibcon#ireg 11 cls_cnt 2 2006.201.23:23:59.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:23:59.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:23:59.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:23:59.90#ibcon#enter wrdev, iclass 16, count 2 2006.201.23:23:59.90#ibcon#first serial, iclass 16, count 2 2006.201.23:23:59.90#ibcon#enter sib2, iclass 16, count 2 2006.201.23:23:59.90#ibcon#flushed, iclass 16, count 2 2006.201.23:23:59.90#ibcon#about to write, iclass 16, count 2 2006.201.23:23:59.90#ibcon#wrote, iclass 16, count 2 2006.201.23:23:59.90#ibcon#about to read 3, iclass 16, count 2 2006.201.23:23:59.92#ibcon#read 3, iclass 16, count 2 2006.201.23:23:59.92#ibcon#about to read 4, iclass 16, count 2 2006.201.23:23:59.92#ibcon#read 4, iclass 16, count 2 2006.201.23:23:59.92#ibcon#about to read 5, iclass 16, count 2 2006.201.23:23:59.92#ibcon#read 5, iclass 16, count 2 2006.201.23:23:59.92#ibcon#about to read 6, iclass 16, count 2 2006.201.23:23:59.92#ibcon#read 6, iclass 16, count 2 2006.201.23:23:59.92#ibcon#end of sib2, iclass 16, count 2 2006.201.23:23:59.92#ibcon#*mode == 0, iclass 16, count 2 2006.201.23:23:59.92#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.23:23:59.92#ibcon#[27=AT01-04\r\n] 2006.201.23:23:59.92#ibcon#*before write, iclass 16, count 2 2006.201.23:23:59.92#ibcon#enter sib2, iclass 16, count 2 2006.201.23:23:59.92#ibcon#flushed, iclass 16, count 2 2006.201.23:23:59.92#ibcon#about to write, iclass 16, count 2 2006.201.23:23:59.92#ibcon#wrote, iclass 16, count 2 2006.201.23:23:59.92#ibcon#about to read 3, iclass 16, count 2 2006.201.23:23:59.95#ibcon#read 3, iclass 16, count 2 2006.201.23:23:59.95#ibcon#about to read 4, iclass 16, count 2 2006.201.23:23:59.95#ibcon#read 4, iclass 16, count 2 2006.201.23:23:59.95#ibcon#about to read 5, iclass 16, count 2 2006.201.23:23:59.95#ibcon#read 5, iclass 16, count 2 2006.201.23:23:59.95#ibcon#about to read 6, iclass 16, count 2 2006.201.23:23:59.95#ibcon#read 6, iclass 16, count 2 2006.201.23:23:59.95#ibcon#end of sib2, iclass 16, count 2 2006.201.23:23:59.95#ibcon#*after write, iclass 16, count 2 2006.201.23:23:59.95#ibcon#*before return 0, iclass 16, count 2 2006.201.23:23:59.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:23:59.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:23:59.95#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.23:23:59.95#ibcon#ireg 7 cls_cnt 0 2006.201.23:23:59.95#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:24:00.07#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:24:00.07#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:24:00.07#ibcon#enter wrdev, iclass 16, count 0 2006.201.23:24:00.07#ibcon#first serial, iclass 16, count 0 2006.201.23:24:00.07#ibcon#enter sib2, iclass 16, count 0 2006.201.23:24:00.07#ibcon#flushed, iclass 16, count 0 2006.201.23:24:00.07#ibcon#about to write, iclass 16, count 0 2006.201.23:24:00.07#ibcon#wrote, iclass 16, count 0 2006.201.23:24:00.07#ibcon#about to read 3, iclass 16, count 0 2006.201.23:24:00.09#ibcon#read 3, iclass 16, count 0 2006.201.23:24:00.09#ibcon#about to read 4, iclass 16, count 0 2006.201.23:24:00.09#ibcon#read 4, iclass 16, count 0 2006.201.23:24:00.09#ibcon#about to read 5, iclass 16, count 0 2006.201.23:24:00.09#ibcon#read 5, iclass 16, count 0 2006.201.23:24:00.09#ibcon#about to read 6, iclass 16, count 0 2006.201.23:24:00.09#ibcon#read 6, iclass 16, count 0 2006.201.23:24:00.09#ibcon#end of sib2, iclass 16, count 0 2006.201.23:24:00.09#ibcon#*mode == 0, iclass 16, count 0 2006.201.23:24:00.09#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.23:24:00.09#ibcon#[27=USB\r\n] 2006.201.23:24:00.09#ibcon#*before write, iclass 16, count 0 2006.201.23:24:00.09#ibcon#enter sib2, iclass 16, count 0 2006.201.23:24:00.09#ibcon#flushed, iclass 16, count 0 2006.201.23:24:00.09#ibcon#about to write, iclass 16, count 0 2006.201.23:24:00.09#ibcon#wrote, iclass 16, count 0 2006.201.23:24:00.09#ibcon#about to read 3, iclass 16, count 0 2006.201.23:24:00.12#ibcon#read 3, iclass 16, count 0 2006.201.23:24:00.12#ibcon#about to read 4, iclass 16, count 0 2006.201.23:24:00.12#ibcon#read 4, iclass 16, count 0 2006.201.23:24:00.12#ibcon#about to read 5, iclass 16, count 0 2006.201.23:24:00.12#ibcon#read 5, iclass 16, count 0 2006.201.23:24:00.12#ibcon#about to read 6, iclass 16, count 0 2006.201.23:24:00.12#ibcon#read 6, iclass 16, count 0 2006.201.23:24:00.12#ibcon#end of sib2, iclass 16, count 0 2006.201.23:24:00.12#ibcon#*after write, iclass 16, count 0 2006.201.23:24:00.12#ibcon#*before return 0, iclass 16, count 0 2006.201.23:24:00.12#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:24:00.12#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:24:00.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.23:24:00.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.23:24:00.12$vck44/vblo=2,634.99 2006.201.23:24:00.12#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.23:24:00.12#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.23:24:00.12#ibcon#ireg 17 cls_cnt 0 2006.201.23:24:00.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:24:00.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:24:00.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:24:00.12#ibcon#enter wrdev, iclass 18, count 0 2006.201.23:24:00.12#ibcon#first serial, iclass 18, count 0 2006.201.23:24:00.12#ibcon#enter sib2, iclass 18, count 0 2006.201.23:24:00.12#ibcon#flushed, iclass 18, count 0 2006.201.23:24:00.12#ibcon#about to write, iclass 18, count 0 2006.201.23:24:00.12#ibcon#wrote, iclass 18, count 0 2006.201.23:24:00.12#ibcon#about to read 3, iclass 18, count 0 2006.201.23:24:00.14#ibcon#read 3, iclass 18, count 0 2006.201.23:24:00.14#ibcon#about to read 4, iclass 18, count 0 2006.201.23:24:00.14#ibcon#read 4, iclass 18, count 0 2006.201.23:24:00.14#ibcon#about to read 5, iclass 18, count 0 2006.201.23:24:00.14#ibcon#read 5, iclass 18, count 0 2006.201.23:24:00.14#ibcon#about to read 6, iclass 18, count 0 2006.201.23:24:00.14#ibcon#read 6, iclass 18, count 0 2006.201.23:24:00.14#ibcon#end of sib2, iclass 18, count 0 2006.201.23:24:00.14#ibcon#*mode == 0, iclass 18, count 0 2006.201.23:24:00.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.23:24:00.14#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.23:24:00.14#ibcon#*before write, iclass 18, count 0 2006.201.23:24:00.14#ibcon#enter sib2, iclass 18, count 0 2006.201.23:24:00.14#ibcon#flushed, iclass 18, count 0 2006.201.23:24:00.14#ibcon#about to write, iclass 18, count 0 2006.201.23:24:00.14#ibcon#wrote, iclass 18, count 0 2006.201.23:24:00.14#ibcon#about to read 3, iclass 18, count 0 2006.201.23:24:00.18#ibcon#read 3, iclass 18, count 0 2006.201.23:24:00.18#ibcon#about to read 4, iclass 18, count 0 2006.201.23:24:00.18#ibcon#read 4, iclass 18, count 0 2006.201.23:24:00.18#ibcon#about to read 5, iclass 18, count 0 2006.201.23:24:00.18#ibcon#read 5, iclass 18, count 0 2006.201.23:24:00.18#ibcon#about to read 6, iclass 18, count 0 2006.201.23:24:00.18#ibcon#read 6, iclass 18, count 0 2006.201.23:24:00.18#ibcon#end of sib2, iclass 18, count 0 2006.201.23:24:00.18#ibcon#*after write, iclass 18, count 0 2006.201.23:24:00.18#ibcon#*before return 0, iclass 18, count 0 2006.201.23:24:00.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:24:00.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:24:00.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.23:24:00.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.23:24:00.18$vck44/vb=2,5 2006.201.23:24:00.18#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.23:24:00.18#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.23:24:00.18#ibcon#ireg 11 cls_cnt 2 2006.201.23:24:00.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:24:00.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:24:00.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:24:00.24#ibcon#enter wrdev, iclass 20, count 2 2006.201.23:24:00.24#ibcon#first serial, iclass 20, count 2 2006.201.23:24:00.24#ibcon#enter sib2, iclass 20, count 2 2006.201.23:24:00.24#ibcon#flushed, iclass 20, count 2 2006.201.23:24:00.24#ibcon#about to write, iclass 20, count 2 2006.201.23:24:00.24#ibcon#wrote, iclass 20, count 2 2006.201.23:24:00.24#ibcon#about to read 3, iclass 20, count 2 2006.201.23:24:00.26#ibcon#read 3, iclass 20, count 2 2006.201.23:24:00.26#ibcon#about to read 4, iclass 20, count 2 2006.201.23:24:00.26#ibcon#read 4, iclass 20, count 2 2006.201.23:24:00.26#ibcon#about to read 5, iclass 20, count 2 2006.201.23:24:00.26#ibcon#read 5, iclass 20, count 2 2006.201.23:24:00.26#ibcon#about to read 6, iclass 20, count 2 2006.201.23:24:00.26#ibcon#read 6, iclass 20, count 2 2006.201.23:24:00.26#ibcon#end of sib2, iclass 20, count 2 2006.201.23:24:00.26#ibcon#*mode == 0, iclass 20, count 2 2006.201.23:24:00.26#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.23:24:00.26#ibcon#[27=AT02-05\r\n] 2006.201.23:24:00.26#ibcon#*before write, iclass 20, count 2 2006.201.23:24:00.26#ibcon#enter sib2, iclass 20, count 2 2006.201.23:24:00.26#ibcon#flushed, iclass 20, count 2 2006.201.23:24:00.26#ibcon#about to write, iclass 20, count 2 2006.201.23:24:00.26#ibcon#wrote, iclass 20, count 2 2006.201.23:24:00.26#ibcon#about to read 3, iclass 20, count 2 2006.201.23:24:00.29#ibcon#read 3, iclass 20, count 2 2006.201.23:24:00.29#ibcon#about to read 4, iclass 20, count 2 2006.201.23:24:00.29#ibcon#read 4, iclass 20, count 2 2006.201.23:24:00.29#ibcon#about to read 5, iclass 20, count 2 2006.201.23:24:00.29#ibcon#read 5, iclass 20, count 2 2006.201.23:24:00.29#ibcon#about to read 6, iclass 20, count 2 2006.201.23:24:00.29#ibcon#read 6, iclass 20, count 2 2006.201.23:24:00.29#ibcon#end of sib2, iclass 20, count 2 2006.201.23:24:00.29#ibcon#*after write, iclass 20, count 2 2006.201.23:24:00.29#ibcon#*before return 0, iclass 20, count 2 2006.201.23:24:00.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:24:00.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:24:00.29#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.23:24:00.29#ibcon#ireg 7 cls_cnt 0 2006.201.23:24:00.29#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:24:00.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:24:00.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:24:00.41#ibcon#enter wrdev, iclass 20, count 0 2006.201.23:24:00.41#ibcon#first serial, iclass 20, count 0 2006.201.23:24:00.41#ibcon#enter sib2, iclass 20, count 0 2006.201.23:24:00.41#ibcon#flushed, iclass 20, count 0 2006.201.23:24:00.41#ibcon#about to write, iclass 20, count 0 2006.201.23:24:00.41#ibcon#wrote, iclass 20, count 0 2006.201.23:24:00.41#ibcon#about to read 3, iclass 20, count 0 2006.201.23:24:00.43#ibcon#read 3, iclass 20, count 0 2006.201.23:24:00.43#ibcon#about to read 4, iclass 20, count 0 2006.201.23:24:00.43#ibcon#read 4, iclass 20, count 0 2006.201.23:24:00.43#ibcon#about to read 5, iclass 20, count 0 2006.201.23:24:00.43#ibcon#read 5, iclass 20, count 0 2006.201.23:24:00.43#ibcon#about to read 6, iclass 20, count 0 2006.201.23:24:00.43#ibcon#read 6, iclass 20, count 0 2006.201.23:24:00.43#ibcon#end of sib2, iclass 20, count 0 2006.201.23:24:00.43#ibcon#*mode == 0, iclass 20, count 0 2006.201.23:24:00.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.23:24:00.43#ibcon#[27=USB\r\n] 2006.201.23:24:00.43#ibcon#*before write, iclass 20, count 0 2006.201.23:24:00.43#ibcon#enter sib2, iclass 20, count 0 2006.201.23:24:00.43#ibcon#flushed, iclass 20, count 0 2006.201.23:24:00.43#ibcon#about to write, iclass 20, count 0 2006.201.23:24:00.43#ibcon#wrote, iclass 20, count 0 2006.201.23:24:00.43#ibcon#about to read 3, iclass 20, count 0 2006.201.23:24:00.46#ibcon#read 3, iclass 20, count 0 2006.201.23:24:00.46#ibcon#about to read 4, iclass 20, count 0 2006.201.23:24:00.46#ibcon#read 4, iclass 20, count 0 2006.201.23:24:00.46#ibcon#about to read 5, iclass 20, count 0 2006.201.23:24:00.46#ibcon#read 5, iclass 20, count 0 2006.201.23:24:00.46#ibcon#about to read 6, iclass 20, count 0 2006.201.23:24:00.46#ibcon#read 6, iclass 20, count 0 2006.201.23:24:00.46#ibcon#end of sib2, iclass 20, count 0 2006.201.23:24:00.46#ibcon#*after write, iclass 20, count 0 2006.201.23:24:00.46#ibcon#*before return 0, iclass 20, count 0 2006.201.23:24:00.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:24:00.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:24:00.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.23:24:00.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.23:24:00.46$vck44/vblo=3,649.99 2006.201.23:24:00.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.23:24:00.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.23:24:00.46#ibcon#ireg 17 cls_cnt 0 2006.201.23:24:00.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:24:00.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:24:00.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:24:00.46#ibcon#enter wrdev, iclass 22, count 0 2006.201.23:24:00.46#ibcon#first serial, iclass 22, count 0 2006.201.23:24:00.46#ibcon#enter sib2, iclass 22, count 0 2006.201.23:24:00.46#ibcon#flushed, iclass 22, count 0 2006.201.23:24:00.46#ibcon#about to write, iclass 22, count 0 2006.201.23:24:00.46#ibcon#wrote, iclass 22, count 0 2006.201.23:24:00.46#ibcon#about to read 3, iclass 22, count 0 2006.201.23:24:00.48#ibcon#read 3, iclass 22, count 0 2006.201.23:24:00.48#ibcon#about to read 4, iclass 22, count 0 2006.201.23:24:00.48#ibcon#read 4, iclass 22, count 0 2006.201.23:24:00.48#ibcon#about to read 5, iclass 22, count 0 2006.201.23:24:00.48#ibcon#read 5, iclass 22, count 0 2006.201.23:24:00.48#ibcon#about to read 6, iclass 22, count 0 2006.201.23:24:00.48#ibcon#read 6, iclass 22, count 0 2006.201.23:24:00.48#ibcon#end of sib2, iclass 22, count 0 2006.201.23:24:00.48#ibcon#*mode == 0, iclass 22, count 0 2006.201.23:24:00.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.23:24:00.48#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.23:24:00.48#ibcon#*before write, iclass 22, count 0 2006.201.23:24:00.48#ibcon#enter sib2, iclass 22, count 0 2006.201.23:24:00.48#ibcon#flushed, iclass 22, count 0 2006.201.23:24:00.48#ibcon#about to write, iclass 22, count 0 2006.201.23:24:00.48#ibcon#wrote, iclass 22, count 0 2006.201.23:24:00.48#ibcon#about to read 3, iclass 22, count 0 2006.201.23:24:00.52#ibcon#read 3, iclass 22, count 0 2006.201.23:24:00.52#ibcon#about to read 4, iclass 22, count 0 2006.201.23:24:00.52#ibcon#read 4, iclass 22, count 0 2006.201.23:24:00.52#ibcon#about to read 5, iclass 22, count 0 2006.201.23:24:00.52#ibcon#read 5, iclass 22, count 0 2006.201.23:24:00.52#ibcon#about to read 6, iclass 22, count 0 2006.201.23:24:00.52#ibcon#read 6, iclass 22, count 0 2006.201.23:24:00.52#ibcon#end of sib2, iclass 22, count 0 2006.201.23:24:00.52#ibcon#*after write, iclass 22, count 0 2006.201.23:24:00.52#ibcon#*before return 0, iclass 22, count 0 2006.201.23:24:00.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:24:00.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:24:00.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.23:24:00.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.23:24:00.52$vck44/vb=3,4 2006.201.23:24:00.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.23:24:00.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.23:24:00.52#ibcon#ireg 11 cls_cnt 2 2006.201.23:24:00.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:24:00.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:24:00.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:24:00.58#ibcon#enter wrdev, iclass 24, count 2 2006.201.23:24:00.58#ibcon#first serial, iclass 24, count 2 2006.201.23:24:00.58#ibcon#enter sib2, iclass 24, count 2 2006.201.23:24:00.58#ibcon#flushed, iclass 24, count 2 2006.201.23:24:00.58#ibcon#about to write, iclass 24, count 2 2006.201.23:24:00.58#ibcon#wrote, iclass 24, count 2 2006.201.23:24:00.58#ibcon#about to read 3, iclass 24, count 2 2006.201.23:24:00.60#ibcon#read 3, iclass 24, count 2 2006.201.23:24:00.60#ibcon#about to read 4, iclass 24, count 2 2006.201.23:24:00.60#ibcon#read 4, iclass 24, count 2 2006.201.23:24:00.60#ibcon#about to read 5, iclass 24, count 2 2006.201.23:24:00.60#ibcon#read 5, iclass 24, count 2 2006.201.23:24:00.60#ibcon#about to read 6, iclass 24, count 2 2006.201.23:24:00.60#ibcon#read 6, iclass 24, count 2 2006.201.23:24:00.60#ibcon#end of sib2, iclass 24, count 2 2006.201.23:24:00.60#ibcon#*mode == 0, iclass 24, count 2 2006.201.23:24:00.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.23:24:00.60#ibcon#[27=AT03-04\r\n] 2006.201.23:24:00.60#ibcon#*before write, iclass 24, count 2 2006.201.23:24:00.60#ibcon#enter sib2, iclass 24, count 2 2006.201.23:24:00.60#ibcon#flushed, iclass 24, count 2 2006.201.23:24:00.60#ibcon#about to write, iclass 24, count 2 2006.201.23:24:00.60#ibcon#wrote, iclass 24, count 2 2006.201.23:24:00.60#ibcon#about to read 3, iclass 24, count 2 2006.201.23:24:00.63#ibcon#read 3, iclass 24, count 2 2006.201.23:24:00.63#ibcon#about to read 4, iclass 24, count 2 2006.201.23:24:00.63#ibcon#read 4, iclass 24, count 2 2006.201.23:24:00.63#ibcon#about to read 5, iclass 24, count 2 2006.201.23:24:00.63#ibcon#read 5, iclass 24, count 2 2006.201.23:24:00.63#ibcon#about to read 6, iclass 24, count 2 2006.201.23:24:00.63#ibcon#read 6, iclass 24, count 2 2006.201.23:24:00.63#ibcon#end of sib2, iclass 24, count 2 2006.201.23:24:00.63#ibcon#*after write, iclass 24, count 2 2006.201.23:24:00.63#ibcon#*before return 0, iclass 24, count 2 2006.201.23:24:00.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:24:00.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:24:00.63#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.23:24:00.63#ibcon#ireg 7 cls_cnt 0 2006.201.23:24:00.63#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:24:00.75#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:24:00.75#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:24:00.75#ibcon#enter wrdev, iclass 24, count 0 2006.201.23:24:00.75#ibcon#first serial, iclass 24, count 0 2006.201.23:24:00.75#ibcon#enter sib2, iclass 24, count 0 2006.201.23:24:00.75#ibcon#flushed, iclass 24, count 0 2006.201.23:24:00.75#ibcon#about to write, iclass 24, count 0 2006.201.23:24:00.75#ibcon#wrote, iclass 24, count 0 2006.201.23:24:00.75#ibcon#about to read 3, iclass 24, count 0 2006.201.23:24:00.77#ibcon#read 3, iclass 24, count 0 2006.201.23:24:00.77#ibcon#about to read 4, iclass 24, count 0 2006.201.23:24:00.77#ibcon#read 4, iclass 24, count 0 2006.201.23:24:00.77#ibcon#about to read 5, iclass 24, count 0 2006.201.23:24:00.77#ibcon#read 5, iclass 24, count 0 2006.201.23:24:00.77#ibcon#about to read 6, iclass 24, count 0 2006.201.23:24:00.77#ibcon#read 6, iclass 24, count 0 2006.201.23:24:00.77#ibcon#end of sib2, iclass 24, count 0 2006.201.23:24:00.77#ibcon#*mode == 0, iclass 24, count 0 2006.201.23:24:00.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.23:24:00.77#ibcon#[27=USB\r\n] 2006.201.23:24:00.77#ibcon#*before write, iclass 24, count 0 2006.201.23:24:00.77#ibcon#enter sib2, iclass 24, count 0 2006.201.23:24:00.77#ibcon#flushed, iclass 24, count 0 2006.201.23:24:00.77#ibcon#about to write, iclass 24, count 0 2006.201.23:24:00.77#ibcon#wrote, iclass 24, count 0 2006.201.23:24:00.77#ibcon#about to read 3, iclass 24, count 0 2006.201.23:24:00.80#ibcon#read 3, iclass 24, count 0 2006.201.23:24:00.80#ibcon#about to read 4, iclass 24, count 0 2006.201.23:24:00.80#ibcon#read 4, iclass 24, count 0 2006.201.23:24:00.80#ibcon#about to read 5, iclass 24, count 0 2006.201.23:24:00.80#ibcon#read 5, iclass 24, count 0 2006.201.23:24:00.80#ibcon#about to read 6, iclass 24, count 0 2006.201.23:24:00.80#ibcon#read 6, iclass 24, count 0 2006.201.23:24:00.80#ibcon#end of sib2, iclass 24, count 0 2006.201.23:24:00.80#ibcon#*after write, iclass 24, count 0 2006.201.23:24:00.80#ibcon#*before return 0, iclass 24, count 0 2006.201.23:24:00.80#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:24:00.80#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:24:00.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.23:24:00.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.23:24:00.80$vck44/vblo=4,679.99 2006.201.23:24:00.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.23:24:00.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.23:24:00.80#ibcon#ireg 17 cls_cnt 0 2006.201.23:24:00.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:24:00.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:24:00.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:24:00.80#ibcon#enter wrdev, iclass 26, count 0 2006.201.23:24:00.80#ibcon#first serial, iclass 26, count 0 2006.201.23:24:00.80#ibcon#enter sib2, iclass 26, count 0 2006.201.23:24:00.80#ibcon#flushed, iclass 26, count 0 2006.201.23:24:00.80#ibcon#about to write, iclass 26, count 0 2006.201.23:24:00.80#ibcon#wrote, iclass 26, count 0 2006.201.23:24:00.80#ibcon#about to read 3, iclass 26, count 0 2006.201.23:24:00.82#ibcon#read 3, iclass 26, count 0 2006.201.23:24:00.82#ibcon#about to read 4, iclass 26, count 0 2006.201.23:24:00.82#ibcon#read 4, iclass 26, count 0 2006.201.23:24:00.82#ibcon#about to read 5, iclass 26, count 0 2006.201.23:24:00.82#ibcon#read 5, iclass 26, count 0 2006.201.23:24:00.82#ibcon#about to read 6, iclass 26, count 0 2006.201.23:24:00.82#ibcon#read 6, iclass 26, count 0 2006.201.23:24:00.82#ibcon#end of sib2, iclass 26, count 0 2006.201.23:24:00.82#ibcon#*mode == 0, iclass 26, count 0 2006.201.23:24:00.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.23:24:00.82#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.23:24:00.82#ibcon#*before write, iclass 26, count 0 2006.201.23:24:00.82#ibcon#enter sib2, iclass 26, count 0 2006.201.23:24:00.82#ibcon#flushed, iclass 26, count 0 2006.201.23:24:00.82#ibcon#about to write, iclass 26, count 0 2006.201.23:24:00.82#ibcon#wrote, iclass 26, count 0 2006.201.23:24:00.82#ibcon#about to read 3, iclass 26, count 0 2006.201.23:24:00.86#ibcon#read 3, iclass 26, count 0 2006.201.23:24:00.86#ibcon#about to read 4, iclass 26, count 0 2006.201.23:24:00.86#ibcon#read 4, iclass 26, count 0 2006.201.23:24:00.86#ibcon#about to read 5, iclass 26, count 0 2006.201.23:24:00.86#ibcon#read 5, iclass 26, count 0 2006.201.23:24:00.86#ibcon#about to read 6, iclass 26, count 0 2006.201.23:24:00.86#ibcon#read 6, iclass 26, count 0 2006.201.23:24:00.86#ibcon#end of sib2, iclass 26, count 0 2006.201.23:24:00.86#ibcon#*after write, iclass 26, count 0 2006.201.23:24:00.86#ibcon#*before return 0, iclass 26, count 0 2006.201.23:24:00.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:24:00.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:24:00.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.23:24:00.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.23:24:00.86$vck44/vb=4,5 2006.201.23:24:00.86#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.23:24:00.86#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.23:24:00.86#ibcon#ireg 11 cls_cnt 2 2006.201.23:24:00.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:24:00.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:24:00.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:24:00.92#ibcon#enter wrdev, iclass 28, count 2 2006.201.23:24:00.92#ibcon#first serial, iclass 28, count 2 2006.201.23:24:00.92#ibcon#enter sib2, iclass 28, count 2 2006.201.23:24:00.92#ibcon#flushed, iclass 28, count 2 2006.201.23:24:00.92#ibcon#about to write, iclass 28, count 2 2006.201.23:24:00.92#ibcon#wrote, iclass 28, count 2 2006.201.23:24:00.92#ibcon#about to read 3, iclass 28, count 2 2006.201.23:24:00.94#ibcon#read 3, iclass 28, count 2 2006.201.23:24:00.94#ibcon#about to read 4, iclass 28, count 2 2006.201.23:24:00.94#ibcon#read 4, iclass 28, count 2 2006.201.23:24:00.94#ibcon#about to read 5, iclass 28, count 2 2006.201.23:24:00.94#ibcon#read 5, iclass 28, count 2 2006.201.23:24:00.94#ibcon#about to read 6, iclass 28, count 2 2006.201.23:24:00.94#ibcon#read 6, iclass 28, count 2 2006.201.23:24:00.94#ibcon#end of sib2, iclass 28, count 2 2006.201.23:24:00.94#ibcon#*mode == 0, iclass 28, count 2 2006.201.23:24:00.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.23:24:00.94#ibcon#[27=AT04-05\r\n] 2006.201.23:24:00.94#ibcon#*before write, iclass 28, count 2 2006.201.23:24:00.94#ibcon#enter sib2, iclass 28, count 2 2006.201.23:24:00.94#ibcon#flushed, iclass 28, count 2 2006.201.23:24:00.94#ibcon#about to write, iclass 28, count 2 2006.201.23:24:00.94#ibcon#wrote, iclass 28, count 2 2006.201.23:24:00.94#ibcon#about to read 3, iclass 28, count 2 2006.201.23:24:00.97#ibcon#read 3, iclass 28, count 2 2006.201.23:24:00.97#ibcon#about to read 4, iclass 28, count 2 2006.201.23:24:00.97#ibcon#read 4, iclass 28, count 2 2006.201.23:24:00.97#ibcon#about to read 5, iclass 28, count 2 2006.201.23:24:00.97#ibcon#read 5, iclass 28, count 2 2006.201.23:24:00.97#ibcon#about to read 6, iclass 28, count 2 2006.201.23:24:00.97#ibcon#read 6, iclass 28, count 2 2006.201.23:24:00.97#ibcon#end of sib2, iclass 28, count 2 2006.201.23:24:00.97#ibcon#*after write, iclass 28, count 2 2006.201.23:24:00.97#ibcon#*before return 0, iclass 28, count 2 2006.201.23:24:00.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:24:00.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:24:00.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.23:24:00.97#ibcon#ireg 7 cls_cnt 0 2006.201.23:24:00.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:24:01.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:24:01.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:24:01.09#ibcon#enter wrdev, iclass 28, count 0 2006.201.23:24:01.09#ibcon#first serial, iclass 28, count 0 2006.201.23:24:01.09#ibcon#enter sib2, iclass 28, count 0 2006.201.23:24:01.09#ibcon#flushed, iclass 28, count 0 2006.201.23:24:01.09#ibcon#about to write, iclass 28, count 0 2006.201.23:24:01.09#ibcon#wrote, iclass 28, count 0 2006.201.23:24:01.09#ibcon#about to read 3, iclass 28, count 0 2006.201.23:24:01.11#ibcon#read 3, iclass 28, count 0 2006.201.23:24:01.11#ibcon#about to read 4, iclass 28, count 0 2006.201.23:24:01.11#ibcon#read 4, iclass 28, count 0 2006.201.23:24:01.11#ibcon#about to read 5, iclass 28, count 0 2006.201.23:24:01.11#ibcon#read 5, iclass 28, count 0 2006.201.23:24:01.11#ibcon#about to read 6, iclass 28, count 0 2006.201.23:24:01.11#ibcon#read 6, iclass 28, count 0 2006.201.23:24:01.11#ibcon#end of sib2, iclass 28, count 0 2006.201.23:24:01.11#ibcon#*mode == 0, iclass 28, count 0 2006.201.23:24:01.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.23:24:01.11#ibcon#[27=USB\r\n] 2006.201.23:24:01.11#ibcon#*before write, iclass 28, count 0 2006.201.23:24:01.11#ibcon#enter sib2, iclass 28, count 0 2006.201.23:24:01.11#ibcon#flushed, iclass 28, count 0 2006.201.23:24:01.11#ibcon#about to write, iclass 28, count 0 2006.201.23:24:01.11#ibcon#wrote, iclass 28, count 0 2006.201.23:24:01.11#ibcon#about to read 3, iclass 28, count 0 2006.201.23:24:01.14#ibcon#read 3, iclass 28, count 0 2006.201.23:24:01.14#ibcon#about to read 4, iclass 28, count 0 2006.201.23:24:01.14#ibcon#read 4, iclass 28, count 0 2006.201.23:24:01.14#ibcon#about to read 5, iclass 28, count 0 2006.201.23:24:01.14#ibcon#read 5, iclass 28, count 0 2006.201.23:24:01.14#ibcon#about to read 6, iclass 28, count 0 2006.201.23:24:01.14#ibcon#read 6, iclass 28, count 0 2006.201.23:24:01.14#ibcon#end of sib2, iclass 28, count 0 2006.201.23:24:01.14#ibcon#*after write, iclass 28, count 0 2006.201.23:24:01.14#ibcon#*before return 0, iclass 28, count 0 2006.201.23:24:01.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:24:01.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:24:01.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.23:24:01.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.23:24:01.14$vck44/vblo=5,709.99 2006.201.23:24:01.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.23:24:01.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.23:24:01.14#ibcon#ireg 17 cls_cnt 0 2006.201.23:24:01.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:24:01.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:24:01.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:24:01.14#ibcon#enter wrdev, iclass 30, count 0 2006.201.23:24:01.14#ibcon#first serial, iclass 30, count 0 2006.201.23:24:01.14#ibcon#enter sib2, iclass 30, count 0 2006.201.23:24:01.14#ibcon#flushed, iclass 30, count 0 2006.201.23:24:01.14#ibcon#about to write, iclass 30, count 0 2006.201.23:24:01.14#ibcon#wrote, iclass 30, count 0 2006.201.23:24:01.14#ibcon#about to read 3, iclass 30, count 0 2006.201.23:24:01.16#ibcon#read 3, iclass 30, count 0 2006.201.23:24:01.16#ibcon#about to read 4, iclass 30, count 0 2006.201.23:24:01.16#ibcon#read 4, iclass 30, count 0 2006.201.23:24:01.16#ibcon#about to read 5, iclass 30, count 0 2006.201.23:24:01.16#ibcon#read 5, iclass 30, count 0 2006.201.23:24:01.16#ibcon#about to read 6, iclass 30, count 0 2006.201.23:24:01.16#ibcon#read 6, iclass 30, count 0 2006.201.23:24:01.16#ibcon#end of sib2, iclass 30, count 0 2006.201.23:24:01.16#ibcon#*mode == 0, iclass 30, count 0 2006.201.23:24:01.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.23:24:01.16#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.23:24:01.16#ibcon#*before write, iclass 30, count 0 2006.201.23:24:01.16#ibcon#enter sib2, iclass 30, count 0 2006.201.23:24:01.16#ibcon#flushed, iclass 30, count 0 2006.201.23:24:01.16#ibcon#about to write, iclass 30, count 0 2006.201.23:24:01.16#ibcon#wrote, iclass 30, count 0 2006.201.23:24:01.16#ibcon#about to read 3, iclass 30, count 0 2006.201.23:24:01.20#ibcon#read 3, iclass 30, count 0 2006.201.23:24:01.20#ibcon#about to read 4, iclass 30, count 0 2006.201.23:24:01.20#ibcon#read 4, iclass 30, count 0 2006.201.23:24:01.20#ibcon#about to read 5, iclass 30, count 0 2006.201.23:24:01.20#ibcon#read 5, iclass 30, count 0 2006.201.23:24:01.20#ibcon#about to read 6, iclass 30, count 0 2006.201.23:24:01.20#ibcon#read 6, iclass 30, count 0 2006.201.23:24:01.20#ibcon#end of sib2, iclass 30, count 0 2006.201.23:24:01.20#ibcon#*after write, iclass 30, count 0 2006.201.23:24:01.20#ibcon#*before return 0, iclass 30, count 0 2006.201.23:24:01.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:24:01.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:24:01.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.23:24:01.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.23:24:01.20$vck44/vb=5,4 2006.201.23:24:01.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.23:24:01.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.23:24:01.20#ibcon#ireg 11 cls_cnt 2 2006.201.23:24:01.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:24:01.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:24:01.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:24:01.26#ibcon#enter wrdev, iclass 32, count 2 2006.201.23:24:01.26#ibcon#first serial, iclass 32, count 2 2006.201.23:24:01.26#ibcon#enter sib2, iclass 32, count 2 2006.201.23:24:01.26#ibcon#flushed, iclass 32, count 2 2006.201.23:24:01.26#ibcon#about to write, iclass 32, count 2 2006.201.23:24:01.26#ibcon#wrote, iclass 32, count 2 2006.201.23:24:01.26#ibcon#about to read 3, iclass 32, count 2 2006.201.23:24:01.28#ibcon#read 3, iclass 32, count 2 2006.201.23:24:01.28#ibcon#about to read 4, iclass 32, count 2 2006.201.23:24:01.28#ibcon#read 4, iclass 32, count 2 2006.201.23:24:01.28#ibcon#about to read 5, iclass 32, count 2 2006.201.23:24:01.28#ibcon#read 5, iclass 32, count 2 2006.201.23:24:01.28#ibcon#about to read 6, iclass 32, count 2 2006.201.23:24:01.28#ibcon#read 6, iclass 32, count 2 2006.201.23:24:01.28#ibcon#end of sib2, iclass 32, count 2 2006.201.23:24:01.28#ibcon#*mode == 0, iclass 32, count 2 2006.201.23:24:01.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.23:24:01.28#ibcon#[27=AT05-04\r\n] 2006.201.23:24:01.28#ibcon#*before write, iclass 32, count 2 2006.201.23:24:01.28#ibcon#enter sib2, iclass 32, count 2 2006.201.23:24:01.28#ibcon#flushed, iclass 32, count 2 2006.201.23:24:01.28#ibcon#about to write, iclass 32, count 2 2006.201.23:24:01.28#ibcon#wrote, iclass 32, count 2 2006.201.23:24:01.28#ibcon#about to read 3, iclass 32, count 2 2006.201.23:24:01.31#ibcon#read 3, iclass 32, count 2 2006.201.23:24:01.31#ibcon#about to read 4, iclass 32, count 2 2006.201.23:24:01.31#ibcon#read 4, iclass 32, count 2 2006.201.23:24:01.31#ibcon#about to read 5, iclass 32, count 2 2006.201.23:24:01.31#ibcon#read 5, iclass 32, count 2 2006.201.23:24:01.31#ibcon#about to read 6, iclass 32, count 2 2006.201.23:24:01.31#ibcon#read 6, iclass 32, count 2 2006.201.23:24:01.31#ibcon#end of sib2, iclass 32, count 2 2006.201.23:24:01.31#ibcon#*after write, iclass 32, count 2 2006.201.23:24:01.31#ibcon#*before return 0, iclass 32, count 2 2006.201.23:24:01.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:24:01.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:24:01.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.23:24:01.31#ibcon#ireg 7 cls_cnt 0 2006.201.23:24:01.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:24:01.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:24:01.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:24:01.43#ibcon#enter wrdev, iclass 32, count 0 2006.201.23:24:01.43#ibcon#first serial, iclass 32, count 0 2006.201.23:24:01.43#ibcon#enter sib2, iclass 32, count 0 2006.201.23:24:01.43#ibcon#flushed, iclass 32, count 0 2006.201.23:24:01.43#ibcon#about to write, iclass 32, count 0 2006.201.23:24:01.43#ibcon#wrote, iclass 32, count 0 2006.201.23:24:01.43#ibcon#about to read 3, iclass 32, count 0 2006.201.23:24:01.45#ibcon#read 3, iclass 32, count 0 2006.201.23:24:01.45#ibcon#about to read 4, iclass 32, count 0 2006.201.23:24:01.45#ibcon#read 4, iclass 32, count 0 2006.201.23:24:01.45#ibcon#about to read 5, iclass 32, count 0 2006.201.23:24:01.45#ibcon#read 5, iclass 32, count 0 2006.201.23:24:01.45#ibcon#about to read 6, iclass 32, count 0 2006.201.23:24:01.45#ibcon#read 6, iclass 32, count 0 2006.201.23:24:01.45#ibcon#end of sib2, iclass 32, count 0 2006.201.23:24:01.45#ibcon#*mode == 0, iclass 32, count 0 2006.201.23:24:01.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.23:24:01.45#ibcon#[27=USB\r\n] 2006.201.23:24:01.45#ibcon#*before write, iclass 32, count 0 2006.201.23:24:01.45#ibcon#enter sib2, iclass 32, count 0 2006.201.23:24:01.45#ibcon#flushed, iclass 32, count 0 2006.201.23:24:01.45#ibcon#about to write, iclass 32, count 0 2006.201.23:24:01.45#ibcon#wrote, iclass 32, count 0 2006.201.23:24:01.45#ibcon#about to read 3, iclass 32, count 0 2006.201.23:24:01.48#ibcon#read 3, iclass 32, count 0 2006.201.23:24:01.48#ibcon#about to read 4, iclass 32, count 0 2006.201.23:24:01.48#ibcon#read 4, iclass 32, count 0 2006.201.23:24:01.48#ibcon#about to read 5, iclass 32, count 0 2006.201.23:24:01.48#ibcon#read 5, iclass 32, count 0 2006.201.23:24:01.48#ibcon#about to read 6, iclass 32, count 0 2006.201.23:24:01.48#ibcon#read 6, iclass 32, count 0 2006.201.23:24:01.48#ibcon#end of sib2, iclass 32, count 0 2006.201.23:24:01.48#ibcon#*after write, iclass 32, count 0 2006.201.23:24:01.48#ibcon#*before return 0, iclass 32, count 0 2006.201.23:24:01.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:24:01.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:24:01.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.23:24:01.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.23:24:01.48$vck44/vblo=6,719.99 2006.201.23:24:01.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.23:24:01.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.23:24:01.48#ibcon#ireg 17 cls_cnt 0 2006.201.23:24:01.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:24:01.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:24:01.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:24:01.48#ibcon#enter wrdev, iclass 34, count 0 2006.201.23:24:01.48#ibcon#first serial, iclass 34, count 0 2006.201.23:24:01.48#ibcon#enter sib2, iclass 34, count 0 2006.201.23:24:01.48#ibcon#flushed, iclass 34, count 0 2006.201.23:24:01.48#ibcon#about to write, iclass 34, count 0 2006.201.23:24:01.48#ibcon#wrote, iclass 34, count 0 2006.201.23:24:01.48#ibcon#about to read 3, iclass 34, count 0 2006.201.23:24:01.50#ibcon#read 3, iclass 34, count 0 2006.201.23:24:01.50#ibcon#about to read 4, iclass 34, count 0 2006.201.23:24:01.50#ibcon#read 4, iclass 34, count 0 2006.201.23:24:01.50#ibcon#about to read 5, iclass 34, count 0 2006.201.23:24:01.50#ibcon#read 5, iclass 34, count 0 2006.201.23:24:01.50#ibcon#about to read 6, iclass 34, count 0 2006.201.23:24:01.50#ibcon#read 6, iclass 34, count 0 2006.201.23:24:01.50#ibcon#end of sib2, iclass 34, count 0 2006.201.23:24:01.50#ibcon#*mode == 0, iclass 34, count 0 2006.201.23:24:01.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.23:24:01.50#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.23:24:01.50#ibcon#*before write, iclass 34, count 0 2006.201.23:24:01.50#ibcon#enter sib2, iclass 34, count 0 2006.201.23:24:01.50#ibcon#flushed, iclass 34, count 0 2006.201.23:24:01.50#ibcon#about to write, iclass 34, count 0 2006.201.23:24:01.50#ibcon#wrote, iclass 34, count 0 2006.201.23:24:01.50#ibcon#about to read 3, iclass 34, count 0 2006.201.23:24:01.55#ibcon#read 3, iclass 34, count 0 2006.201.23:24:01.55#ibcon#about to read 4, iclass 34, count 0 2006.201.23:24:01.55#ibcon#read 4, iclass 34, count 0 2006.201.23:24:01.55#ibcon#about to read 5, iclass 34, count 0 2006.201.23:24:01.55#ibcon#read 5, iclass 34, count 0 2006.201.23:24:01.55#ibcon#about to read 6, iclass 34, count 0 2006.201.23:24:01.55#ibcon#read 6, iclass 34, count 0 2006.201.23:24:01.55#ibcon#end of sib2, iclass 34, count 0 2006.201.23:24:01.55#ibcon#*after write, iclass 34, count 0 2006.201.23:24:01.55#ibcon#*before return 0, iclass 34, count 0 2006.201.23:24:01.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:24:01.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:24:01.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.23:24:01.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.23:24:01.55$vck44/vb=6,4 2006.201.23:24:01.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.23:24:01.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.23:24:01.55#ibcon#ireg 11 cls_cnt 2 2006.201.23:24:01.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:24:01.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:24:01.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:24:01.60#ibcon#enter wrdev, iclass 36, count 2 2006.201.23:24:01.60#ibcon#first serial, iclass 36, count 2 2006.201.23:24:01.60#ibcon#enter sib2, iclass 36, count 2 2006.201.23:24:01.60#ibcon#flushed, iclass 36, count 2 2006.201.23:24:01.60#ibcon#about to write, iclass 36, count 2 2006.201.23:24:01.60#ibcon#wrote, iclass 36, count 2 2006.201.23:24:01.60#ibcon#about to read 3, iclass 36, count 2 2006.201.23:24:01.62#ibcon#read 3, iclass 36, count 2 2006.201.23:24:01.62#ibcon#about to read 4, iclass 36, count 2 2006.201.23:24:01.62#ibcon#read 4, iclass 36, count 2 2006.201.23:24:01.62#ibcon#about to read 5, iclass 36, count 2 2006.201.23:24:01.62#ibcon#read 5, iclass 36, count 2 2006.201.23:24:01.62#ibcon#about to read 6, iclass 36, count 2 2006.201.23:24:01.62#ibcon#read 6, iclass 36, count 2 2006.201.23:24:01.62#ibcon#end of sib2, iclass 36, count 2 2006.201.23:24:01.62#ibcon#*mode == 0, iclass 36, count 2 2006.201.23:24:01.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.23:24:01.62#ibcon#[27=AT06-04\r\n] 2006.201.23:24:01.62#ibcon#*before write, iclass 36, count 2 2006.201.23:24:01.62#ibcon#enter sib2, iclass 36, count 2 2006.201.23:24:01.62#ibcon#flushed, iclass 36, count 2 2006.201.23:24:01.62#ibcon#about to write, iclass 36, count 2 2006.201.23:24:01.62#ibcon#wrote, iclass 36, count 2 2006.201.23:24:01.62#ibcon#about to read 3, iclass 36, count 2 2006.201.23:24:01.65#ibcon#read 3, iclass 36, count 2 2006.201.23:24:01.65#ibcon#about to read 4, iclass 36, count 2 2006.201.23:24:01.65#ibcon#read 4, iclass 36, count 2 2006.201.23:24:01.65#ibcon#about to read 5, iclass 36, count 2 2006.201.23:24:01.65#ibcon#read 5, iclass 36, count 2 2006.201.23:24:01.65#ibcon#about to read 6, iclass 36, count 2 2006.201.23:24:01.65#ibcon#read 6, iclass 36, count 2 2006.201.23:24:01.65#ibcon#end of sib2, iclass 36, count 2 2006.201.23:24:01.65#ibcon#*after write, iclass 36, count 2 2006.201.23:24:01.65#ibcon#*before return 0, iclass 36, count 2 2006.201.23:24:01.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:24:01.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:24:01.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.23:24:01.65#ibcon#ireg 7 cls_cnt 0 2006.201.23:24:01.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:24:01.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:24:01.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:24:01.77#ibcon#enter wrdev, iclass 36, count 0 2006.201.23:24:01.77#ibcon#first serial, iclass 36, count 0 2006.201.23:24:01.77#ibcon#enter sib2, iclass 36, count 0 2006.201.23:24:01.77#ibcon#flushed, iclass 36, count 0 2006.201.23:24:01.77#ibcon#about to write, iclass 36, count 0 2006.201.23:24:01.77#ibcon#wrote, iclass 36, count 0 2006.201.23:24:01.77#ibcon#about to read 3, iclass 36, count 0 2006.201.23:24:01.79#ibcon#read 3, iclass 36, count 0 2006.201.23:24:01.79#ibcon#about to read 4, iclass 36, count 0 2006.201.23:24:01.79#ibcon#read 4, iclass 36, count 0 2006.201.23:24:01.79#ibcon#about to read 5, iclass 36, count 0 2006.201.23:24:01.79#ibcon#read 5, iclass 36, count 0 2006.201.23:24:01.79#ibcon#about to read 6, iclass 36, count 0 2006.201.23:24:01.79#ibcon#read 6, iclass 36, count 0 2006.201.23:24:01.79#ibcon#end of sib2, iclass 36, count 0 2006.201.23:24:01.79#ibcon#*mode == 0, iclass 36, count 0 2006.201.23:24:01.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.23:24:01.79#ibcon#[27=USB\r\n] 2006.201.23:24:01.79#ibcon#*before write, iclass 36, count 0 2006.201.23:24:01.79#ibcon#enter sib2, iclass 36, count 0 2006.201.23:24:01.79#ibcon#flushed, iclass 36, count 0 2006.201.23:24:01.79#ibcon#about to write, iclass 36, count 0 2006.201.23:24:01.79#ibcon#wrote, iclass 36, count 0 2006.201.23:24:01.79#ibcon#about to read 3, iclass 36, count 0 2006.201.23:24:01.82#ibcon#read 3, iclass 36, count 0 2006.201.23:24:01.82#ibcon#about to read 4, iclass 36, count 0 2006.201.23:24:01.82#ibcon#read 4, iclass 36, count 0 2006.201.23:24:01.82#ibcon#about to read 5, iclass 36, count 0 2006.201.23:24:01.82#ibcon#read 5, iclass 36, count 0 2006.201.23:24:01.82#ibcon#about to read 6, iclass 36, count 0 2006.201.23:24:01.82#ibcon#read 6, iclass 36, count 0 2006.201.23:24:01.82#ibcon#end of sib2, iclass 36, count 0 2006.201.23:24:01.82#ibcon#*after write, iclass 36, count 0 2006.201.23:24:01.82#ibcon#*before return 0, iclass 36, count 0 2006.201.23:24:01.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:24:01.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:24:01.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.23:24:01.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.23:24:01.82$vck44/vblo=7,734.99 2006.201.23:24:01.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.23:24:01.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.23:24:01.82#ibcon#ireg 17 cls_cnt 0 2006.201.23:24:01.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:24:01.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:24:01.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:24:01.82#ibcon#enter wrdev, iclass 38, count 0 2006.201.23:24:01.82#ibcon#first serial, iclass 38, count 0 2006.201.23:24:01.82#ibcon#enter sib2, iclass 38, count 0 2006.201.23:24:01.82#ibcon#flushed, iclass 38, count 0 2006.201.23:24:01.82#ibcon#about to write, iclass 38, count 0 2006.201.23:24:01.82#ibcon#wrote, iclass 38, count 0 2006.201.23:24:01.82#ibcon#about to read 3, iclass 38, count 0 2006.201.23:24:01.84#ibcon#read 3, iclass 38, count 0 2006.201.23:24:01.84#ibcon#about to read 4, iclass 38, count 0 2006.201.23:24:01.84#ibcon#read 4, iclass 38, count 0 2006.201.23:24:01.84#ibcon#about to read 5, iclass 38, count 0 2006.201.23:24:01.84#ibcon#read 5, iclass 38, count 0 2006.201.23:24:01.84#ibcon#about to read 6, iclass 38, count 0 2006.201.23:24:01.84#ibcon#read 6, iclass 38, count 0 2006.201.23:24:01.84#ibcon#end of sib2, iclass 38, count 0 2006.201.23:24:01.84#ibcon#*mode == 0, iclass 38, count 0 2006.201.23:24:01.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.23:24:01.84#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.23:24:01.84#ibcon#*before write, iclass 38, count 0 2006.201.23:24:01.84#ibcon#enter sib2, iclass 38, count 0 2006.201.23:24:01.84#ibcon#flushed, iclass 38, count 0 2006.201.23:24:01.84#ibcon#about to write, iclass 38, count 0 2006.201.23:24:01.84#ibcon#wrote, iclass 38, count 0 2006.201.23:24:01.84#ibcon#about to read 3, iclass 38, count 0 2006.201.23:24:01.88#ibcon#read 3, iclass 38, count 0 2006.201.23:24:01.88#ibcon#about to read 4, iclass 38, count 0 2006.201.23:24:01.88#ibcon#read 4, iclass 38, count 0 2006.201.23:24:01.88#ibcon#about to read 5, iclass 38, count 0 2006.201.23:24:01.88#ibcon#read 5, iclass 38, count 0 2006.201.23:24:01.88#ibcon#about to read 6, iclass 38, count 0 2006.201.23:24:01.88#ibcon#read 6, iclass 38, count 0 2006.201.23:24:01.88#ibcon#end of sib2, iclass 38, count 0 2006.201.23:24:01.88#ibcon#*after write, iclass 38, count 0 2006.201.23:24:01.88#ibcon#*before return 0, iclass 38, count 0 2006.201.23:24:01.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:24:01.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:24:01.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.23:24:01.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.23:24:01.88$vck44/vb=7,4 2006.201.23:24:01.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.23:24:01.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.23:24:01.88#ibcon#ireg 11 cls_cnt 2 2006.201.23:24:01.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:24:01.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:24:01.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:24:01.94#ibcon#enter wrdev, iclass 40, count 2 2006.201.23:24:01.94#ibcon#first serial, iclass 40, count 2 2006.201.23:24:01.94#ibcon#enter sib2, iclass 40, count 2 2006.201.23:24:01.94#ibcon#flushed, iclass 40, count 2 2006.201.23:24:01.94#ibcon#about to write, iclass 40, count 2 2006.201.23:24:01.94#ibcon#wrote, iclass 40, count 2 2006.201.23:24:01.94#ibcon#about to read 3, iclass 40, count 2 2006.201.23:24:01.96#ibcon#read 3, iclass 40, count 2 2006.201.23:24:01.96#ibcon#about to read 4, iclass 40, count 2 2006.201.23:24:01.96#ibcon#read 4, iclass 40, count 2 2006.201.23:24:01.96#ibcon#about to read 5, iclass 40, count 2 2006.201.23:24:01.96#ibcon#read 5, iclass 40, count 2 2006.201.23:24:01.96#ibcon#about to read 6, iclass 40, count 2 2006.201.23:24:01.96#ibcon#read 6, iclass 40, count 2 2006.201.23:24:01.96#ibcon#end of sib2, iclass 40, count 2 2006.201.23:24:01.96#ibcon#*mode == 0, iclass 40, count 2 2006.201.23:24:01.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.23:24:01.96#ibcon#[27=AT07-04\r\n] 2006.201.23:24:01.96#ibcon#*before write, iclass 40, count 2 2006.201.23:24:01.96#ibcon#enter sib2, iclass 40, count 2 2006.201.23:24:01.96#ibcon#flushed, iclass 40, count 2 2006.201.23:24:01.96#ibcon#about to write, iclass 40, count 2 2006.201.23:24:01.96#ibcon#wrote, iclass 40, count 2 2006.201.23:24:01.96#ibcon#about to read 3, iclass 40, count 2 2006.201.23:24:01.99#ibcon#read 3, iclass 40, count 2 2006.201.23:24:01.99#ibcon#about to read 4, iclass 40, count 2 2006.201.23:24:01.99#ibcon#read 4, iclass 40, count 2 2006.201.23:24:01.99#ibcon#about to read 5, iclass 40, count 2 2006.201.23:24:01.99#ibcon#read 5, iclass 40, count 2 2006.201.23:24:01.99#ibcon#about to read 6, iclass 40, count 2 2006.201.23:24:01.99#ibcon#read 6, iclass 40, count 2 2006.201.23:24:01.99#ibcon#end of sib2, iclass 40, count 2 2006.201.23:24:01.99#ibcon#*after write, iclass 40, count 2 2006.201.23:24:01.99#ibcon#*before return 0, iclass 40, count 2 2006.201.23:24:01.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:24:01.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:24:01.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.23:24:01.99#ibcon#ireg 7 cls_cnt 0 2006.201.23:24:01.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:24:02.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:24:02.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:24:02.11#ibcon#enter wrdev, iclass 40, count 0 2006.201.23:24:02.11#ibcon#first serial, iclass 40, count 0 2006.201.23:24:02.11#ibcon#enter sib2, iclass 40, count 0 2006.201.23:24:02.11#ibcon#flushed, iclass 40, count 0 2006.201.23:24:02.11#ibcon#about to write, iclass 40, count 0 2006.201.23:24:02.11#ibcon#wrote, iclass 40, count 0 2006.201.23:24:02.11#ibcon#about to read 3, iclass 40, count 0 2006.201.23:24:02.13#ibcon#read 3, iclass 40, count 0 2006.201.23:24:02.13#ibcon#about to read 4, iclass 40, count 0 2006.201.23:24:02.13#ibcon#read 4, iclass 40, count 0 2006.201.23:24:02.13#ibcon#about to read 5, iclass 40, count 0 2006.201.23:24:02.13#ibcon#read 5, iclass 40, count 0 2006.201.23:24:02.13#ibcon#about to read 6, iclass 40, count 0 2006.201.23:24:02.13#ibcon#read 6, iclass 40, count 0 2006.201.23:24:02.13#ibcon#end of sib2, iclass 40, count 0 2006.201.23:24:02.13#ibcon#*mode == 0, iclass 40, count 0 2006.201.23:24:02.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.23:24:02.13#ibcon#[27=USB\r\n] 2006.201.23:24:02.13#ibcon#*before write, iclass 40, count 0 2006.201.23:24:02.13#ibcon#enter sib2, iclass 40, count 0 2006.201.23:24:02.13#ibcon#flushed, iclass 40, count 0 2006.201.23:24:02.13#ibcon#about to write, iclass 40, count 0 2006.201.23:24:02.13#ibcon#wrote, iclass 40, count 0 2006.201.23:24:02.13#ibcon#about to read 3, iclass 40, count 0 2006.201.23:24:02.16#ibcon#read 3, iclass 40, count 0 2006.201.23:24:02.16#ibcon#about to read 4, iclass 40, count 0 2006.201.23:24:02.16#ibcon#read 4, iclass 40, count 0 2006.201.23:24:02.16#ibcon#about to read 5, iclass 40, count 0 2006.201.23:24:02.16#ibcon#read 5, iclass 40, count 0 2006.201.23:24:02.16#ibcon#about to read 6, iclass 40, count 0 2006.201.23:24:02.16#ibcon#read 6, iclass 40, count 0 2006.201.23:24:02.16#ibcon#end of sib2, iclass 40, count 0 2006.201.23:24:02.16#ibcon#*after write, iclass 40, count 0 2006.201.23:24:02.16#ibcon#*before return 0, iclass 40, count 0 2006.201.23:24:02.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:24:02.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:24:02.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.23:24:02.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.23:24:02.16$vck44/vblo=8,744.99 2006.201.23:24:02.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.23:24:02.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.23:24:02.16#ibcon#ireg 17 cls_cnt 0 2006.201.23:24:02.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:24:02.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:24:02.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:24:02.16#ibcon#enter wrdev, iclass 4, count 0 2006.201.23:24:02.16#ibcon#first serial, iclass 4, count 0 2006.201.23:24:02.16#ibcon#enter sib2, iclass 4, count 0 2006.201.23:24:02.16#ibcon#flushed, iclass 4, count 0 2006.201.23:24:02.16#ibcon#about to write, iclass 4, count 0 2006.201.23:24:02.16#ibcon#wrote, iclass 4, count 0 2006.201.23:24:02.16#ibcon#about to read 3, iclass 4, count 0 2006.201.23:24:02.18#ibcon#read 3, iclass 4, count 0 2006.201.23:24:02.18#ibcon#about to read 4, iclass 4, count 0 2006.201.23:24:02.18#ibcon#read 4, iclass 4, count 0 2006.201.23:24:02.18#ibcon#about to read 5, iclass 4, count 0 2006.201.23:24:02.18#ibcon#read 5, iclass 4, count 0 2006.201.23:24:02.18#ibcon#about to read 6, iclass 4, count 0 2006.201.23:24:02.18#ibcon#read 6, iclass 4, count 0 2006.201.23:24:02.18#ibcon#end of sib2, iclass 4, count 0 2006.201.23:24:02.18#ibcon#*mode == 0, iclass 4, count 0 2006.201.23:24:02.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.23:24:02.18#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.23:24:02.18#ibcon#*before write, iclass 4, count 0 2006.201.23:24:02.18#ibcon#enter sib2, iclass 4, count 0 2006.201.23:24:02.18#ibcon#flushed, iclass 4, count 0 2006.201.23:24:02.18#ibcon#about to write, iclass 4, count 0 2006.201.23:24:02.18#ibcon#wrote, iclass 4, count 0 2006.201.23:24:02.18#ibcon#about to read 3, iclass 4, count 0 2006.201.23:24:02.22#ibcon#read 3, iclass 4, count 0 2006.201.23:24:02.22#ibcon#about to read 4, iclass 4, count 0 2006.201.23:24:02.22#ibcon#read 4, iclass 4, count 0 2006.201.23:24:02.22#ibcon#about to read 5, iclass 4, count 0 2006.201.23:24:02.22#ibcon#read 5, iclass 4, count 0 2006.201.23:24:02.22#ibcon#about to read 6, iclass 4, count 0 2006.201.23:24:02.22#ibcon#read 6, iclass 4, count 0 2006.201.23:24:02.22#ibcon#end of sib2, iclass 4, count 0 2006.201.23:24:02.22#ibcon#*after write, iclass 4, count 0 2006.201.23:24:02.22#ibcon#*before return 0, iclass 4, count 0 2006.201.23:24:02.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:24:02.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:24:02.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.23:24:02.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.23:24:02.22$vck44/vb=8,4 2006.201.23:24:02.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.23:24:02.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.23:24:02.22#ibcon#ireg 11 cls_cnt 2 2006.201.23:24:02.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:24:02.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:24:02.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:24:02.28#ibcon#enter wrdev, iclass 6, count 2 2006.201.23:24:02.28#ibcon#first serial, iclass 6, count 2 2006.201.23:24:02.28#ibcon#enter sib2, iclass 6, count 2 2006.201.23:24:02.28#ibcon#flushed, iclass 6, count 2 2006.201.23:24:02.28#ibcon#about to write, iclass 6, count 2 2006.201.23:24:02.28#ibcon#wrote, iclass 6, count 2 2006.201.23:24:02.28#ibcon#about to read 3, iclass 6, count 2 2006.201.23:24:02.30#ibcon#read 3, iclass 6, count 2 2006.201.23:24:02.30#ibcon#about to read 4, iclass 6, count 2 2006.201.23:24:02.30#ibcon#read 4, iclass 6, count 2 2006.201.23:24:02.30#ibcon#about to read 5, iclass 6, count 2 2006.201.23:24:02.30#ibcon#read 5, iclass 6, count 2 2006.201.23:24:02.30#ibcon#about to read 6, iclass 6, count 2 2006.201.23:24:02.30#ibcon#read 6, iclass 6, count 2 2006.201.23:24:02.30#ibcon#end of sib2, iclass 6, count 2 2006.201.23:24:02.30#ibcon#*mode == 0, iclass 6, count 2 2006.201.23:24:02.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.23:24:02.30#ibcon#[27=AT08-04\r\n] 2006.201.23:24:02.30#ibcon#*before write, iclass 6, count 2 2006.201.23:24:02.30#ibcon#enter sib2, iclass 6, count 2 2006.201.23:24:02.30#ibcon#flushed, iclass 6, count 2 2006.201.23:24:02.30#ibcon#about to write, iclass 6, count 2 2006.201.23:24:02.30#ibcon#wrote, iclass 6, count 2 2006.201.23:24:02.30#ibcon#about to read 3, iclass 6, count 2 2006.201.23:24:02.33#ibcon#read 3, iclass 6, count 2 2006.201.23:24:02.33#ibcon#about to read 4, iclass 6, count 2 2006.201.23:24:02.33#ibcon#read 4, iclass 6, count 2 2006.201.23:24:02.33#ibcon#about to read 5, iclass 6, count 2 2006.201.23:24:02.33#ibcon#read 5, iclass 6, count 2 2006.201.23:24:02.33#ibcon#about to read 6, iclass 6, count 2 2006.201.23:24:02.33#ibcon#read 6, iclass 6, count 2 2006.201.23:24:02.33#ibcon#end of sib2, iclass 6, count 2 2006.201.23:24:02.33#ibcon#*after write, iclass 6, count 2 2006.201.23:24:02.33#ibcon#*before return 0, iclass 6, count 2 2006.201.23:24:02.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:24:02.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:24:02.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.23:24:02.33#ibcon#ireg 7 cls_cnt 0 2006.201.23:24:02.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:24:02.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:24:02.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:24:02.45#ibcon#enter wrdev, iclass 6, count 0 2006.201.23:24:02.45#ibcon#first serial, iclass 6, count 0 2006.201.23:24:02.45#ibcon#enter sib2, iclass 6, count 0 2006.201.23:24:02.45#ibcon#flushed, iclass 6, count 0 2006.201.23:24:02.45#ibcon#about to write, iclass 6, count 0 2006.201.23:24:02.45#ibcon#wrote, iclass 6, count 0 2006.201.23:24:02.45#ibcon#about to read 3, iclass 6, count 0 2006.201.23:24:02.47#ibcon#read 3, iclass 6, count 0 2006.201.23:24:02.47#ibcon#about to read 4, iclass 6, count 0 2006.201.23:24:02.47#ibcon#read 4, iclass 6, count 0 2006.201.23:24:02.47#ibcon#about to read 5, iclass 6, count 0 2006.201.23:24:02.47#ibcon#read 5, iclass 6, count 0 2006.201.23:24:02.47#ibcon#about to read 6, iclass 6, count 0 2006.201.23:24:02.47#ibcon#read 6, iclass 6, count 0 2006.201.23:24:02.47#ibcon#end of sib2, iclass 6, count 0 2006.201.23:24:02.47#ibcon#*mode == 0, iclass 6, count 0 2006.201.23:24:02.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.23:24:02.47#ibcon#[27=USB\r\n] 2006.201.23:24:02.47#ibcon#*before write, iclass 6, count 0 2006.201.23:24:02.47#ibcon#enter sib2, iclass 6, count 0 2006.201.23:24:02.47#ibcon#flushed, iclass 6, count 0 2006.201.23:24:02.47#ibcon#about to write, iclass 6, count 0 2006.201.23:24:02.47#ibcon#wrote, iclass 6, count 0 2006.201.23:24:02.47#ibcon#about to read 3, iclass 6, count 0 2006.201.23:24:02.50#ibcon#read 3, iclass 6, count 0 2006.201.23:24:02.50#ibcon#about to read 4, iclass 6, count 0 2006.201.23:24:02.50#ibcon#read 4, iclass 6, count 0 2006.201.23:24:02.50#ibcon#about to read 5, iclass 6, count 0 2006.201.23:24:02.50#ibcon#read 5, iclass 6, count 0 2006.201.23:24:02.50#ibcon#about to read 6, iclass 6, count 0 2006.201.23:24:02.50#ibcon#read 6, iclass 6, count 0 2006.201.23:24:02.50#ibcon#end of sib2, iclass 6, count 0 2006.201.23:24:02.50#ibcon#*after write, iclass 6, count 0 2006.201.23:24:02.50#ibcon#*before return 0, iclass 6, count 0 2006.201.23:24:02.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:24:02.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:24:02.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.23:24:02.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.23:24:02.50$vck44/vabw=wide 2006.201.23:24:02.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.23:24:02.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.23:24:02.50#ibcon#ireg 8 cls_cnt 0 2006.201.23:24:02.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:24:02.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:24:02.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:24:02.50#ibcon#enter wrdev, iclass 10, count 0 2006.201.23:24:02.50#ibcon#first serial, iclass 10, count 0 2006.201.23:24:02.50#ibcon#enter sib2, iclass 10, count 0 2006.201.23:24:02.50#ibcon#flushed, iclass 10, count 0 2006.201.23:24:02.50#ibcon#about to write, iclass 10, count 0 2006.201.23:24:02.50#ibcon#wrote, iclass 10, count 0 2006.201.23:24:02.50#ibcon#about to read 3, iclass 10, count 0 2006.201.23:24:02.52#ibcon#read 3, iclass 10, count 0 2006.201.23:24:02.52#ibcon#about to read 4, iclass 10, count 0 2006.201.23:24:02.52#ibcon#read 4, iclass 10, count 0 2006.201.23:24:02.52#ibcon#about to read 5, iclass 10, count 0 2006.201.23:24:02.52#ibcon#read 5, iclass 10, count 0 2006.201.23:24:02.52#ibcon#about to read 6, iclass 10, count 0 2006.201.23:24:02.52#ibcon#read 6, iclass 10, count 0 2006.201.23:24:02.52#ibcon#end of sib2, iclass 10, count 0 2006.201.23:24:02.52#ibcon#*mode == 0, iclass 10, count 0 2006.201.23:24:02.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.23:24:02.52#ibcon#[25=BW32\r\n] 2006.201.23:24:02.52#ibcon#*before write, iclass 10, count 0 2006.201.23:24:02.52#ibcon#enter sib2, iclass 10, count 0 2006.201.23:24:02.52#ibcon#flushed, iclass 10, count 0 2006.201.23:24:02.52#ibcon#about to write, iclass 10, count 0 2006.201.23:24:02.52#ibcon#wrote, iclass 10, count 0 2006.201.23:24:02.52#ibcon#about to read 3, iclass 10, count 0 2006.201.23:24:02.55#ibcon#read 3, iclass 10, count 0 2006.201.23:24:02.55#ibcon#about to read 4, iclass 10, count 0 2006.201.23:24:02.55#ibcon#read 4, iclass 10, count 0 2006.201.23:24:02.55#ibcon#about to read 5, iclass 10, count 0 2006.201.23:24:02.55#ibcon#read 5, iclass 10, count 0 2006.201.23:24:02.55#ibcon#about to read 6, iclass 10, count 0 2006.201.23:24:02.55#ibcon#read 6, iclass 10, count 0 2006.201.23:24:02.55#ibcon#end of sib2, iclass 10, count 0 2006.201.23:24:02.55#ibcon#*after write, iclass 10, count 0 2006.201.23:24:02.55#ibcon#*before return 0, iclass 10, count 0 2006.201.23:24:02.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:24:02.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:24:02.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.23:24:02.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.23:24:02.55$vck44/vbbw=wide 2006.201.23:24:02.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.23:24:02.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.23:24:02.55#ibcon#ireg 8 cls_cnt 0 2006.201.23:24:02.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:24:02.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:24:02.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:24:02.62#ibcon#enter wrdev, iclass 12, count 0 2006.201.23:24:02.62#ibcon#first serial, iclass 12, count 0 2006.201.23:24:02.62#ibcon#enter sib2, iclass 12, count 0 2006.201.23:24:02.62#ibcon#flushed, iclass 12, count 0 2006.201.23:24:02.62#ibcon#about to write, iclass 12, count 0 2006.201.23:24:02.62#ibcon#wrote, iclass 12, count 0 2006.201.23:24:02.62#ibcon#about to read 3, iclass 12, count 0 2006.201.23:24:02.64#ibcon#read 3, iclass 12, count 0 2006.201.23:24:02.64#ibcon#about to read 4, iclass 12, count 0 2006.201.23:24:02.64#ibcon#read 4, iclass 12, count 0 2006.201.23:24:02.64#ibcon#about to read 5, iclass 12, count 0 2006.201.23:24:02.64#ibcon#read 5, iclass 12, count 0 2006.201.23:24:02.64#ibcon#about to read 6, iclass 12, count 0 2006.201.23:24:02.64#ibcon#read 6, iclass 12, count 0 2006.201.23:24:02.64#ibcon#end of sib2, iclass 12, count 0 2006.201.23:24:02.64#ibcon#*mode == 0, iclass 12, count 0 2006.201.23:24:02.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.23:24:02.64#ibcon#[27=BW32\r\n] 2006.201.23:24:02.64#ibcon#*before write, iclass 12, count 0 2006.201.23:24:02.64#ibcon#enter sib2, iclass 12, count 0 2006.201.23:24:02.64#ibcon#flushed, iclass 12, count 0 2006.201.23:24:02.64#ibcon#about to write, iclass 12, count 0 2006.201.23:24:02.64#ibcon#wrote, iclass 12, count 0 2006.201.23:24:02.64#ibcon#about to read 3, iclass 12, count 0 2006.201.23:24:02.67#ibcon#read 3, iclass 12, count 0 2006.201.23:24:02.67#ibcon#about to read 4, iclass 12, count 0 2006.201.23:24:02.67#ibcon#read 4, iclass 12, count 0 2006.201.23:24:02.67#ibcon#about to read 5, iclass 12, count 0 2006.201.23:24:02.67#ibcon#read 5, iclass 12, count 0 2006.201.23:24:02.67#ibcon#about to read 6, iclass 12, count 0 2006.201.23:24:02.67#ibcon#read 6, iclass 12, count 0 2006.201.23:24:02.67#ibcon#end of sib2, iclass 12, count 0 2006.201.23:24:02.67#ibcon#*after write, iclass 12, count 0 2006.201.23:24:02.67#ibcon#*before return 0, iclass 12, count 0 2006.201.23:24:02.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:24:02.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:24:02.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.23:24:02.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.23:24:02.67$setupk4/ifdk4 2006.201.23:24:02.67$ifdk4/lo= 2006.201.23:24:02.67$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.23:24:02.67$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.23:24:02.67$ifdk4/patch= 2006.201.23:24:02.67$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.23:24:02.67$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.23:24:02.67$setupk4/!*+20s 2006.201.23:24:03.15#abcon#<5=/00 0.2 0.9 20.341001001.7\r\n> 2006.201.23:24:03.17#abcon#{5=INTERFACE CLEAR} 2006.201.23:24:03.23#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:24:13.32#abcon#<5=/00 0.2 0.9 20.341001001.6\r\n> 2006.201.23:24:13.34#abcon#{5=INTERFACE CLEAR} 2006.201.23:24:13.40#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:24:16.13#trakl#Source acquired 2006.201.23:24:17.16$setupk4/"tpicd 2006.201.23:24:17.16$setupk4/echo=off 2006.201.23:24:17.16$setupk4/xlog=off 2006.201.23:24:17.16:!2006.201.23:27:46 2006.201.23:24:18.13#flagr#flagr/antenna,acquired 2006.201.23:27:46.00:preob 2006.201.23:27:46.14/onsource/TRACKING 2006.201.23:27:46.14:!2006.201.23:27:56 2006.201.23:27:56.00:"tape 2006.201.23:27:56.00:"st=record 2006.201.23:27:56.00:data_valid=on 2006.201.23:27:56.00:midob 2006.201.23:27:57.14/onsource/TRACKING 2006.201.23:27:57.14/wx/20.37,1001.5,100 2006.201.23:27:57.27/cable/+6.4843E-03 2006.201.23:27:58.36/va/01,08,usb,yes,52,55 2006.201.23:27:58.36/va/02,07,usb,yes,56,57 2006.201.23:27:58.36/va/03,08,usb,yes,51,53 2006.201.23:27:58.36/va/04,07,usb,yes,57,61 2006.201.23:27:58.36/va/05,04,usb,yes,51,53 2006.201.23:27:58.36/va/06,05,usb,yes,52,52 2006.201.23:27:58.36/va/07,05,usb,yes,51,52 2006.201.23:27:58.36/va/08,04,usb,yes,50,59 2006.201.23:27:58.59/valo/01,524.99,yes,locked 2006.201.23:27:58.59/valo/02,534.99,yes,locked 2006.201.23:27:58.59/valo/03,564.99,yes,locked 2006.201.23:27:58.59/valo/04,624.99,yes,locked 2006.201.23:27:58.59/valo/05,734.99,yes,locked 2006.201.23:27:58.59/valo/06,814.99,yes,locked 2006.201.23:27:58.59/valo/07,864.99,yes,locked 2006.201.23:27:58.59/valo/08,884.99,yes,locked 2006.201.23:27:59.68/vb/01,04,usb,yes,33,31 2006.201.23:27:59.68/vb/02,05,usb,yes,32,31 2006.201.23:27:59.68/vb/03,04,usb,yes,33,36 2006.201.23:27:59.68/vb/04,05,usb,yes,33,32 2006.201.23:27:59.68/vb/05,04,usb,yes,29,32 2006.201.23:27:59.68/vb/06,04,usb,yes,34,30 2006.201.23:27:59.68/vb/07,04,usb,yes,34,34 2006.201.23:27:59.68/vb/08,04,usb,yes,31,35 2006.201.23:27:59.92/vblo/01,629.99,yes,locked 2006.201.23:27:59.92/vblo/02,634.99,yes,locked 2006.201.23:27:59.92/vblo/03,649.99,yes,locked 2006.201.23:27:59.92/vblo/04,679.99,yes,locked 2006.201.23:27:59.92/vblo/05,709.99,yes,locked 2006.201.23:27:59.92/vblo/06,719.99,yes,locked 2006.201.23:27:59.92/vblo/07,734.99,yes,locked 2006.201.23:27:59.92/vblo/08,744.99,yes,locked 2006.201.23:28:00.07/vabw/8 2006.201.23:28:00.22/vbbw/8 2006.201.23:28:00.31/xfe/off,on,14.5 2006.201.23:28:00.68/ifatt/23,28,28,28 2006.201.23:28:01.07/fmout-gps/S +4.51E-07 2006.201.23:28:01.11:!2006.201.23:31:36 2006.201.23:31:36.00:data_valid=off 2006.201.23:31:36.00:"et 2006.201.23:31:36.00:!+3s 2006.201.23:31:39.01:"tape 2006.201.23:31:39.01:postob 2006.201.23:31:39.19/cable/+6.4859E-03 2006.201.23:31:39.19/wx/20.32,1001.5,100 2006.201.23:31:40.07/fmout-gps/S +4.52E-07 2006.201.23:31:40.07:scan_name=201-2332,jd0607,220 2006.201.23:31:40.07:source=0059+581,010245.76,582411.1,2000.0,cw 2006.201.23:31:41.14#flagr#flagr/antenna,new-source 2006.201.23:31:41.14:checkk5 2006.201.23:31:41.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.23:31:41.85/chk_autoobs//k5ts2/ autoobs is running! 2006.201.23:31:42.21/chk_autoobs//k5ts3/ autoobs is running! 2006.201.23:31:42.55/chk_autoobs//k5ts4/ autoobs is running! 2006.201.23:31:42.90/chk_obsdata//k5ts1/T2012327??a.dat file size is correct (nominal:880MB, actual:880MB). 2006.201.23:31:43.24/chk_obsdata//k5ts2/T2012327??b.dat file size is correct (nominal:880MB, actual:880MB). 2006.201.23:31:43.59/chk_obsdata//k5ts3/T2012327??c.dat file size is correct (nominal:880MB, actual:880MB). 2006.201.23:31:43.93/chk_obsdata//k5ts4/T2012327??d.dat file size is correct (nominal:880MB, actual:880MB). 2006.201.23:31:44.60/k5log//k5ts1_log_newline 2006.201.23:31:45.27/k5log//k5ts2_log_newline 2006.201.23:31:45.92/k5log//k5ts3_log_newline 2006.201.23:31:46.58/k5log//k5ts4_log_newline 2006.201.23:31:46.60/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.23:31:46.60:setupk4=1 2006.201.23:31:46.60$setupk4/echo=on 2006.201.23:31:46.60$setupk4/pcalon 2006.201.23:31:46.60$pcalon/"no phase cal control is implemented here 2006.201.23:31:46.60$setupk4/"tpicd=stop 2006.201.23:31:46.60$setupk4/"rec=synch_on 2006.201.23:31:46.60$setupk4/"rec_mode=128 2006.201.23:31:46.60$setupk4/!* 2006.201.23:31:46.60$setupk4/recpk4 2006.201.23:31:46.60$recpk4/recpatch= 2006.201.23:31:46.61$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.23:31:46.61$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.23:31:46.61$setupk4/vck44 2006.201.23:31:46.61$vck44/valo=1,524.99 2006.201.23:31:46.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.23:31:46.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.23:31:46.61#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:46.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:46.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:46.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:46.61#ibcon#enter wrdev, iclass 16, count 0 2006.201.23:31:46.61#ibcon#first serial, iclass 16, count 0 2006.201.23:31:46.61#ibcon#enter sib2, iclass 16, count 0 2006.201.23:31:46.61#ibcon#flushed, iclass 16, count 0 2006.201.23:31:46.61#ibcon#about to write, iclass 16, count 0 2006.201.23:31:46.61#ibcon#wrote, iclass 16, count 0 2006.201.23:31:46.61#ibcon#about to read 3, iclass 16, count 0 2006.201.23:31:46.63#ibcon#read 3, iclass 16, count 0 2006.201.23:31:46.63#ibcon#about to read 4, iclass 16, count 0 2006.201.23:31:46.63#ibcon#read 4, iclass 16, count 0 2006.201.23:31:46.63#ibcon#about to read 5, iclass 16, count 0 2006.201.23:31:46.63#ibcon#read 5, iclass 16, count 0 2006.201.23:31:46.63#ibcon#about to read 6, iclass 16, count 0 2006.201.23:31:46.63#ibcon#read 6, iclass 16, count 0 2006.201.23:31:46.63#ibcon#end of sib2, iclass 16, count 0 2006.201.23:31:46.63#ibcon#*mode == 0, iclass 16, count 0 2006.201.23:31:46.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.23:31:46.63#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.23:31:46.63#ibcon#*before write, iclass 16, count 0 2006.201.23:31:46.63#ibcon#enter sib2, iclass 16, count 0 2006.201.23:31:46.63#ibcon#flushed, iclass 16, count 0 2006.201.23:31:46.63#ibcon#about to write, iclass 16, count 0 2006.201.23:31:46.63#ibcon#wrote, iclass 16, count 0 2006.201.23:31:46.63#ibcon#about to read 3, iclass 16, count 0 2006.201.23:31:46.68#ibcon#read 3, iclass 16, count 0 2006.201.23:31:46.68#ibcon#about to read 4, iclass 16, count 0 2006.201.23:31:46.68#ibcon#read 4, iclass 16, count 0 2006.201.23:31:46.68#ibcon#about to read 5, iclass 16, count 0 2006.201.23:31:46.68#ibcon#read 5, iclass 16, count 0 2006.201.23:31:46.68#ibcon#about to read 6, iclass 16, count 0 2006.201.23:31:46.68#ibcon#read 6, iclass 16, count 0 2006.201.23:31:46.68#ibcon#end of sib2, iclass 16, count 0 2006.201.23:31:46.68#ibcon#*after write, iclass 16, count 0 2006.201.23:31:46.68#ibcon#*before return 0, iclass 16, count 0 2006.201.23:31:46.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:46.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:46.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.23:31:46.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.23:31:46.68$vck44/va=1,8 2006.201.23:31:46.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.23:31:46.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.23:31:46.68#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:46.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:46.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:46.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:46.68#ibcon#enter wrdev, iclass 18, count 2 2006.201.23:31:46.68#ibcon#first serial, iclass 18, count 2 2006.201.23:31:46.68#ibcon#enter sib2, iclass 18, count 2 2006.201.23:31:46.68#ibcon#flushed, iclass 18, count 2 2006.201.23:31:46.68#ibcon#about to write, iclass 18, count 2 2006.201.23:31:46.68#ibcon#wrote, iclass 18, count 2 2006.201.23:31:46.68#ibcon#about to read 3, iclass 18, count 2 2006.201.23:31:46.70#ibcon#read 3, iclass 18, count 2 2006.201.23:31:46.70#ibcon#about to read 4, iclass 18, count 2 2006.201.23:31:46.70#ibcon#read 4, iclass 18, count 2 2006.201.23:31:46.70#ibcon#about to read 5, iclass 18, count 2 2006.201.23:31:46.70#ibcon#read 5, iclass 18, count 2 2006.201.23:31:46.70#ibcon#about to read 6, iclass 18, count 2 2006.201.23:31:46.70#ibcon#read 6, iclass 18, count 2 2006.201.23:31:46.70#ibcon#end of sib2, iclass 18, count 2 2006.201.23:31:46.70#ibcon#*mode == 0, iclass 18, count 2 2006.201.23:31:46.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.23:31:46.70#ibcon#[25=AT01-08\r\n] 2006.201.23:31:46.70#ibcon#*before write, iclass 18, count 2 2006.201.23:31:46.70#ibcon#enter sib2, iclass 18, count 2 2006.201.23:31:46.70#ibcon#flushed, iclass 18, count 2 2006.201.23:31:46.70#ibcon#about to write, iclass 18, count 2 2006.201.23:31:46.70#ibcon#wrote, iclass 18, count 2 2006.201.23:31:46.70#ibcon#about to read 3, iclass 18, count 2 2006.201.23:31:46.73#ibcon#read 3, iclass 18, count 2 2006.201.23:31:46.73#ibcon#about to read 4, iclass 18, count 2 2006.201.23:31:46.73#ibcon#read 4, iclass 18, count 2 2006.201.23:31:46.73#ibcon#about to read 5, iclass 18, count 2 2006.201.23:31:46.73#ibcon#read 5, iclass 18, count 2 2006.201.23:31:46.73#ibcon#about to read 6, iclass 18, count 2 2006.201.23:31:46.73#ibcon#read 6, iclass 18, count 2 2006.201.23:31:46.73#ibcon#end of sib2, iclass 18, count 2 2006.201.23:31:46.73#ibcon#*after write, iclass 18, count 2 2006.201.23:31:46.73#ibcon#*before return 0, iclass 18, count 2 2006.201.23:31:46.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:46.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:46.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.23:31:46.73#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:46.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:46.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:46.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:46.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.23:31:46.85#ibcon#first serial, iclass 18, count 0 2006.201.23:31:46.85#ibcon#enter sib2, iclass 18, count 0 2006.201.23:31:46.85#ibcon#flushed, iclass 18, count 0 2006.201.23:31:46.85#ibcon#about to write, iclass 18, count 0 2006.201.23:31:46.85#ibcon#wrote, iclass 18, count 0 2006.201.23:31:46.85#ibcon#about to read 3, iclass 18, count 0 2006.201.23:31:46.87#ibcon#read 3, iclass 18, count 0 2006.201.23:31:46.87#ibcon#about to read 4, iclass 18, count 0 2006.201.23:31:46.87#ibcon#read 4, iclass 18, count 0 2006.201.23:31:46.87#ibcon#about to read 5, iclass 18, count 0 2006.201.23:31:46.87#ibcon#read 5, iclass 18, count 0 2006.201.23:31:46.87#ibcon#about to read 6, iclass 18, count 0 2006.201.23:31:46.87#ibcon#read 6, iclass 18, count 0 2006.201.23:31:46.87#ibcon#end of sib2, iclass 18, count 0 2006.201.23:31:46.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.23:31:46.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.23:31:46.87#ibcon#[25=USB\r\n] 2006.201.23:31:46.87#ibcon#*before write, iclass 18, count 0 2006.201.23:31:46.87#ibcon#enter sib2, iclass 18, count 0 2006.201.23:31:46.87#ibcon#flushed, iclass 18, count 0 2006.201.23:31:46.87#ibcon#about to write, iclass 18, count 0 2006.201.23:31:46.87#ibcon#wrote, iclass 18, count 0 2006.201.23:31:46.87#ibcon#about to read 3, iclass 18, count 0 2006.201.23:31:46.90#ibcon#read 3, iclass 18, count 0 2006.201.23:31:46.90#ibcon#about to read 4, iclass 18, count 0 2006.201.23:31:46.90#ibcon#read 4, iclass 18, count 0 2006.201.23:31:46.90#ibcon#about to read 5, iclass 18, count 0 2006.201.23:31:46.90#ibcon#read 5, iclass 18, count 0 2006.201.23:31:46.90#ibcon#about to read 6, iclass 18, count 0 2006.201.23:31:46.90#ibcon#read 6, iclass 18, count 0 2006.201.23:31:46.90#ibcon#end of sib2, iclass 18, count 0 2006.201.23:31:46.90#ibcon#*after write, iclass 18, count 0 2006.201.23:31:46.90#ibcon#*before return 0, iclass 18, count 0 2006.201.23:31:46.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:46.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:46.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.23:31:46.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.23:31:46.90$vck44/valo=2,534.99 2006.201.23:31:46.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.23:31:46.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.23:31:46.90#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:46.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:46.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:46.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:46.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.23:31:46.90#ibcon#first serial, iclass 20, count 0 2006.201.23:31:46.90#ibcon#enter sib2, iclass 20, count 0 2006.201.23:31:46.90#ibcon#flushed, iclass 20, count 0 2006.201.23:31:46.90#ibcon#about to write, iclass 20, count 0 2006.201.23:31:46.90#ibcon#wrote, iclass 20, count 0 2006.201.23:31:46.90#ibcon#about to read 3, iclass 20, count 0 2006.201.23:31:46.92#ibcon#read 3, iclass 20, count 0 2006.201.23:31:46.92#ibcon#about to read 4, iclass 20, count 0 2006.201.23:31:46.92#ibcon#read 4, iclass 20, count 0 2006.201.23:31:46.92#ibcon#about to read 5, iclass 20, count 0 2006.201.23:31:46.92#ibcon#read 5, iclass 20, count 0 2006.201.23:31:46.92#ibcon#about to read 6, iclass 20, count 0 2006.201.23:31:46.92#ibcon#read 6, iclass 20, count 0 2006.201.23:31:46.92#ibcon#end of sib2, iclass 20, count 0 2006.201.23:31:46.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.23:31:46.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.23:31:46.92#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.23:31:46.92#ibcon#*before write, iclass 20, count 0 2006.201.23:31:46.92#ibcon#enter sib2, iclass 20, count 0 2006.201.23:31:46.92#ibcon#flushed, iclass 20, count 0 2006.201.23:31:46.92#ibcon#about to write, iclass 20, count 0 2006.201.23:31:46.92#ibcon#wrote, iclass 20, count 0 2006.201.23:31:46.92#ibcon#about to read 3, iclass 20, count 0 2006.201.23:31:46.96#ibcon#read 3, iclass 20, count 0 2006.201.23:31:46.96#ibcon#about to read 4, iclass 20, count 0 2006.201.23:31:46.96#ibcon#read 4, iclass 20, count 0 2006.201.23:31:46.96#ibcon#about to read 5, iclass 20, count 0 2006.201.23:31:46.96#ibcon#read 5, iclass 20, count 0 2006.201.23:31:46.96#ibcon#about to read 6, iclass 20, count 0 2006.201.23:31:46.96#ibcon#read 6, iclass 20, count 0 2006.201.23:31:46.96#ibcon#end of sib2, iclass 20, count 0 2006.201.23:31:46.96#ibcon#*after write, iclass 20, count 0 2006.201.23:31:46.96#ibcon#*before return 0, iclass 20, count 0 2006.201.23:31:46.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:46.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:46.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.23:31:46.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.23:31:46.96$vck44/va=2,7 2006.201.23:31:46.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.23:31:46.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.23:31:46.96#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:46.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:47.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:47.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:47.02#ibcon#enter wrdev, iclass 22, count 2 2006.201.23:31:47.02#ibcon#first serial, iclass 22, count 2 2006.201.23:31:47.02#ibcon#enter sib2, iclass 22, count 2 2006.201.23:31:47.02#ibcon#flushed, iclass 22, count 2 2006.201.23:31:47.02#ibcon#about to write, iclass 22, count 2 2006.201.23:31:47.02#ibcon#wrote, iclass 22, count 2 2006.201.23:31:47.02#ibcon#about to read 3, iclass 22, count 2 2006.201.23:31:47.04#ibcon#read 3, iclass 22, count 2 2006.201.23:31:47.04#ibcon#about to read 4, iclass 22, count 2 2006.201.23:31:47.04#ibcon#read 4, iclass 22, count 2 2006.201.23:31:47.04#ibcon#about to read 5, iclass 22, count 2 2006.201.23:31:47.04#ibcon#read 5, iclass 22, count 2 2006.201.23:31:47.04#ibcon#about to read 6, iclass 22, count 2 2006.201.23:31:47.04#ibcon#read 6, iclass 22, count 2 2006.201.23:31:47.04#ibcon#end of sib2, iclass 22, count 2 2006.201.23:31:47.04#ibcon#*mode == 0, iclass 22, count 2 2006.201.23:31:47.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.23:31:47.04#ibcon#[25=AT02-07\r\n] 2006.201.23:31:47.04#ibcon#*before write, iclass 22, count 2 2006.201.23:31:47.04#ibcon#enter sib2, iclass 22, count 2 2006.201.23:31:47.04#ibcon#flushed, iclass 22, count 2 2006.201.23:31:47.04#ibcon#about to write, iclass 22, count 2 2006.201.23:31:47.04#ibcon#wrote, iclass 22, count 2 2006.201.23:31:47.04#ibcon#about to read 3, iclass 22, count 2 2006.201.23:31:47.07#ibcon#read 3, iclass 22, count 2 2006.201.23:31:47.07#ibcon#about to read 4, iclass 22, count 2 2006.201.23:31:47.07#ibcon#read 4, iclass 22, count 2 2006.201.23:31:47.07#ibcon#about to read 5, iclass 22, count 2 2006.201.23:31:47.07#ibcon#read 5, iclass 22, count 2 2006.201.23:31:47.07#ibcon#about to read 6, iclass 22, count 2 2006.201.23:31:47.07#ibcon#read 6, iclass 22, count 2 2006.201.23:31:47.07#ibcon#end of sib2, iclass 22, count 2 2006.201.23:31:47.07#ibcon#*after write, iclass 22, count 2 2006.201.23:31:47.07#ibcon#*before return 0, iclass 22, count 2 2006.201.23:31:47.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:47.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:47.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.23:31:47.07#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:47.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:47.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:47.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:47.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.23:31:47.19#ibcon#first serial, iclass 22, count 0 2006.201.23:31:47.19#ibcon#enter sib2, iclass 22, count 0 2006.201.23:31:47.19#ibcon#flushed, iclass 22, count 0 2006.201.23:31:47.19#ibcon#about to write, iclass 22, count 0 2006.201.23:31:47.19#ibcon#wrote, iclass 22, count 0 2006.201.23:31:47.19#ibcon#about to read 3, iclass 22, count 0 2006.201.23:31:47.21#ibcon#read 3, iclass 22, count 0 2006.201.23:31:47.21#ibcon#about to read 4, iclass 22, count 0 2006.201.23:31:47.21#ibcon#read 4, iclass 22, count 0 2006.201.23:31:47.21#ibcon#about to read 5, iclass 22, count 0 2006.201.23:31:47.21#ibcon#read 5, iclass 22, count 0 2006.201.23:31:47.21#ibcon#about to read 6, iclass 22, count 0 2006.201.23:31:47.21#ibcon#read 6, iclass 22, count 0 2006.201.23:31:47.21#ibcon#end of sib2, iclass 22, count 0 2006.201.23:31:47.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.23:31:47.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.23:31:47.21#ibcon#[25=USB\r\n] 2006.201.23:31:47.21#ibcon#*before write, iclass 22, count 0 2006.201.23:31:47.21#ibcon#enter sib2, iclass 22, count 0 2006.201.23:31:47.21#ibcon#flushed, iclass 22, count 0 2006.201.23:31:47.21#ibcon#about to write, iclass 22, count 0 2006.201.23:31:47.21#ibcon#wrote, iclass 22, count 0 2006.201.23:31:47.21#ibcon#about to read 3, iclass 22, count 0 2006.201.23:31:47.24#ibcon#read 3, iclass 22, count 0 2006.201.23:31:47.24#ibcon#about to read 4, iclass 22, count 0 2006.201.23:31:47.24#ibcon#read 4, iclass 22, count 0 2006.201.23:31:47.24#ibcon#about to read 5, iclass 22, count 0 2006.201.23:31:47.24#ibcon#read 5, iclass 22, count 0 2006.201.23:31:47.24#ibcon#about to read 6, iclass 22, count 0 2006.201.23:31:47.24#ibcon#read 6, iclass 22, count 0 2006.201.23:31:47.24#ibcon#end of sib2, iclass 22, count 0 2006.201.23:31:47.24#ibcon#*after write, iclass 22, count 0 2006.201.23:31:47.24#ibcon#*before return 0, iclass 22, count 0 2006.201.23:31:47.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:47.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:47.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.23:31:47.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.23:31:47.24$vck44/valo=3,564.99 2006.201.23:31:47.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.23:31:47.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.23:31:47.24#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:47.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:47.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:47.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:47.24#ibcon#enter wrdev, iclass 24, count 0 2006.201.23:31:47.24#ibcon#first serial, iclass 24, count 0 2006.201.23:31:47.24#ibcon#enter sib2, iclass 24, count 0 2006.201.23:31:47.24#ibcon#flushed, iclass 24, count 0 2006.201.23:31:47.24#ibcon#about to write, iclass 24, count 0 2006.201.23:31:47.24#ibcon#wrote, iclass 24, count 0 2006.201.23:31:47.24#ibcon#about to read 3, iclass 24, count 0 2006.201.23:31:47.26#ibcon#read 3, iclass 24, count 0 2006.201.23:31:47.26#ibcon#about to read 4, iclass 24, count 0 2006.201.23:31:47.26#ibcon#read 4, iclass 24, count 0 2006.201.23:31:47.26#ibcon#about to read 5, iclass 24, count 0 2006.201.23:31:47.26#ibcon#read 5, iclass 24, count 0 2006.201.23:31:47.26#ibcon#about to read 6, iclass 24, count 0 2006.201.23:31:47.26#ibcon#read 6, iclass 24, count 0 2006.201.23:31:47.26#ibcon#end of sib2, iclass 24, count 0 2006.201.23:31:47.26#ibcon#*mode == 0, iclass 24, count 0 2006.201.23:31:47.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.23:31:47.26#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.23:31:47.26#ibcon#*before write, iclass 24, count 0 2006.201.23:31:47.26#ibcon#enter sib2, iclass 24, count 0 2006.201.23:31:47.26#ibcon#flushed, iclass 24, count 0 2006.201.23:31:47.26#ibcon#about to write, iclass 24, count 0 2006.201.23:31:47.26#ibcon#wrote, iclass 24, count 0 2006.201.23:31:47.26#ibcon#about to read 3, iclass 24, count 0 2006.201.23:31:47.30#ibcon#read 3, iclass 24, count 0 2006.201.23:31:47.30#ibcon#about to read 4, iclass 24, count 0 2006.201.23:31:47.30#ibcon#read 4, iclass 24, count 0 2006.201.23:31:47.30#ibcon#about to read 5, iclass 24, count 0 2006.201.23:31:47.30#ibcon#read 5, iclass 24, count 0 2006.201.23:31:47.30#ibcon#about to read 6, iclass 24, count 0 2006.201.23:31:47.30#ibcon#read 6, iclass 24, count 0 2006.201.23:31:47.30#ibcon#end of sib2, iclass 24, count 0 2006.201.23:31:47.30#ibcon#*after write, iclass 24, count 0 2006.201.23:31:47.30#ibcon#*before return 0, iclass 24, count 0 2006.201.23:31:47.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:47.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:47.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.23:31:47.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.23:31:47.30$vck44/va=3,8 2006.201.23:31:47.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.23:31:47.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.23:31:47.30#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:47.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:47.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:47.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:47.36#ibcon#enter wrdev, iclass 26, count 2 2006.201.23:31:47.36#ibcon#first serial, iclass 26, count 2 2006.201.23:31:47.36#ibcon#enter sib2, iclass 26, count 2 2006.201.23:31:47.36#ibcon#flushed, iclass 26, count 2 2006.201.23:31:47.36#ibcon#about to write, iclass 26, count 2 2006.201.23:31:47.36#ibcon#wrote, iclass 26, count 2 2006.201.23:31:47.36#ibcon#about to read 3, iclass 26, count 2 2006.201.23:31:47.38#ibcon#read 3, iclass 26, count 2 2006.201.23:31:47.38#ibcon#about to read 4, iclass 26, count 2 2006.201.23:31:47.38#ibcon#read 4, iclass 26, count 2 2006.201.23:31:47.38#ibcon#about to read 5, iclass 26, count 2 2006.201.23:31:47.38#ibcon#read 5, iclass 26, count 2 2006.201.23:31:47.38#ibcon#about to read 6, iclass 26, count 2 2006.201.23:31:47.38#ibcon#read 6, iclass 26, count 2 2006.201.23:31:47.38#ibcon#end of sib2, iclass 26, count 2 2006.201.23:31:47.38#ibcon#*mode == 0, iclass 26, count 2 2006.201.23:31:47.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.23:31:47.38#ibcon#[25=AT03-08\r\n] 2006.201.23:31:47.38#ibcon#*before write, iclass 26, count 2 2006.201.23:31:47.38#ibcon#enter sib2, iclass 26, count 2 2006.201.23:31:47.38#ibcon#flushed, iclass 26, count 2 2006.201.23:31:47.38#ibcon#about to write, iclass 26, count 2 2006.201.23:31:47.38#ibcon#wrote, iclass 26, count 2 2006.201.23:31:47.38#ibcon#about to read 3, iclass 26, count 2 2006.201.23:31:47.41#ibcon#read 3, iclass 26, count 2 2006.201.23:31:47.41#ibcon#about to read 4, iclass 26, count 2 2006.201.23:31:47.41#ibcon#read 4, iclass 26, count 2 2006.201.23:31:47.41#ibcon#about to read 5, iclass 26, count 2 2006.201.23:31:47.41#ibcon#read 5, iclass 26, count 2 2006.201.23:31:47.41#ibcon#about to read 6, iclass 26, count 2 2006.201.23:31:47.41#ibcon#read 6, iclass 26, count 2 2006.201.23:31:47.41#ibcon#end of sib2, iclass 26, count 2 2006.201.23:31:47.41#ibcon#*after write, iclass 26, count 2 2006.201.23:31:47.41#ibcon#*before return 0, iclass 26, count 2 2006.201.23:31:47.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:47.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:47.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.23:31:47.41#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:47.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:47.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:47.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:47.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.23:31:47.53#ibcon#first serial, iclass 26, count 0 2006.201.23:31:47.53#ibcon#enter sib2, iclass 26, count 0 2006.201.23:31:47.53#ibcon#flushed, iclass 26, count 0 2006.201.23:31:47.53#ibcon#about to write, iclass 26, count 0 2006.201.23:31:47.53#ibcon#wrote, iclass 26, count 0 2006.201.23:31:47.53#ibcon#about to read 3, iclass 26, count 0 2006.201.23:31:47.55#ibcon#read 3, iclass 26, count 0 2006.201.23:31:47.55#ibcon#about to read 4, iclass 26, count 0 2006.201.23:31:47.55#ibcon#read 4, iclass 26, count 0 2006.201.23:31:47.55#ibcon#about to read 5, iclass 26, count 0 2006.201.23:31:47.55#ibcon#read 5, iclass 26, count 0 2006.201.23:31:47.55#ibcon#about to read 6, iclass 26, count 0 2006.201.23:31:47.55#ibcon#read 6, iclass 26, count 0 2006.201.23:31:47.55#ibcon#end of sib2, iclass 26, count 0 2006.201.23:31:47.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.23:31:47.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.23:31:47.55#ibcon#[25=USB\r\n] 2006.201.23:31:47.55#ibcon#*before write, iclass 26, count 0 2006.201.23:31:47.55#ibcon#enter sib2, iclass 26, count 0 2006.201.23:31:47.55#ibcon#flushed, iclass 26, count 0 2006.201.23:31:47.55#ibcon#about to write, iclass 26, count 0 2006.201.23:31:47.55#ibcon#wrote, iclass 26, count 0 2006.201.23:31:47.55#ibcon#about to read 3, iclass 26, count 0 2006.201.23:31:47.58#ibcon#read 3, iclass 26, count 0 2006.201.23:31:47.58#ibcon#about to read 4, iclass 26, count 0 2006.201.23:31:47.58#ibcon#read 4, iclass 26, count 0 2006.201.23:31:47.58#ibcon#about to read 5, iclass 26, count 0 2006.201.23:31:47.58#ibcon#read 5, iclass 26, count 0 2006.201.23:31:47.58#ibcon#about to read 6, iclass 26, count 0 2006.201.23:31:47.58#ibcon#read 6, iclass 26, count 0 2006.201.23:31:47.58#ibcon#end of sib2, iclass 26, count 0 2006.201.23:31:47.58#ibcon#*after write, iclass 26, count 0 2006.201.23:31:47.58#ibcon#*before return 0, iclass 26, count 0 2006.201.23:31:47.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:47.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:47.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.23:31:47.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.23:31:47.58$vck44/valo=4,624.99 2006.201.23:31:47.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.23:31:47.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.23:31:47.58#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:47.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:47.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:47.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:47.58#ibcon#enter wrdev, iclass 28, count 0 2006.201.23:31:47.58#ibcon#first serial, iclass 28, count 0 2006.201.23:31:47.58#ibcon#enter sib2, iclass 28, count 0 2006.201.23:31:47.58#ibcon#flushed, iclass 28, count 0 2006.201.23:31:47.58#ibcon#about to write, iclass 28, count 0 2006.201.23:31:47.58#ibcon#wrote, iclass 28, count 0 2006.201.23:31:47.58#ibcon#about to read 3, iclass 28, count 0 2006.201.23:31:47.60#ibcon#read 3, iclass 28, count 0 2006.201.23:31:47.60#ibcon#about to read 4, iclass 28, count 0 2006.201.23:31:47.60#ibcon#read 4, iclass 28, count 0 2006.201.23:31:47.60#ibcon#about to read 5, iclass 28, count 0 2006.201.23:31:47.60#ibcon#read 5, iclass 28, count 0 2006.201.23:31:47.60#ibcon#about to read 6, iclass 28, count 0 2006.201.23:31:47.60#ibcon#read 6, iclass 28, count 0 2006.201.23:31:47.60#ibcon#end of sib2, iclass 28, count 0 2006.201.23:31:47.60#ibcon#*mode == 0, iclass 28, count 0 2006.201.23:31:47.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.23:31:47.60#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.23:31:47.60#ibcon#*before write, iclass 28, count 0 2006.201.23:31:47.60#ibcon#enter sib2, iclass 28, count 0 2006.201.23:31:47.60#ibcon#flushed, iclass 28, count 0 2006.201.23:31:47.60#ibcon#about to write, iclass 28, count 0 2006.201.23:31:47.60#ibcon#wrote, iclass 28, count 0 2006.201.23:31:47.60#ibcon#about to read 3, iclass 28, count 0 2006.201.23:31:47.64#ibcon#read 3, iclass 28, count 0 2006.201.23:31:47.64#ibcon#about to read 4, iclass 28, count 0 2006.201.23:31:47.64#ibcon#read 4, iclass 28, count 0 2006.201.23:31:47.64#ibcon#about to read 5, iclass 28, count 0 2006.201.23:31:47.64#ibcon#read 5, iclass 28, count 0 2006.201.23:31:47.64#ibcon#about to read 6, iclass 28, count 0 2006.201.23:31:47.64#ibcon#read 6, iclass 28, count 0 2006.201.23:31:47.64#ibcon#end of sib2, iclass 28, count 0 2006.201.23:31:47.64#ibcon#*after write, iclass 28, count 0 2006.201.23:31:47.64#ibcon#*before return 0, iclass 28, count 0 2006.201.23:31:47.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:47.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:47.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.23:31:47.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.23:31:47.64$vck44/va=4,7 2006.201.23:31:47.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.23:31:47.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.23:31:47.64#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:47.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:47.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:47.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:47.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.23:31:47.70#ibcon#first serial, iclass 30, count 2 2006.201.23:31:47.70#ibcon#enter sib2, iclass 30, count 2 2006.201.23:31:47.70#ibcon#flushed, iclass 30, count 2 2006.201.23:31:47.70#ibcon#about to write, iclass 30, count 2 2006.201.23:31:47.70#ibcon#wrote, iclass 30, count 2 2006.201.23:31:47.70#ibcon#about to read 3, iclass 30, count 2 2006.201.23:31:47.72#ibcon#read 3, iclass 30, count 2 2006.201.23:31:47.72#ibcon#about to read 4, iclass 30, count 2 2006.201.23:31:47.72#ibcon#read 4, iclass 30, count 2 2006.201.23:31:47.72#ibcon#about to read 5, iclass 30, count 2 2006.201.23:31:47.72#ibcon#read 5, iclass 30, count 2 2006.201.23:31:47.72#ibcon#about to read 6, iclass 30, count 2 2006.201.23:31:47.72#ibcon#read 6, iclass 30, count 2 2006.201.23:31:47.72#ibcon#end of sib2, iclass 30, count 2 2006.201.23:31:47.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.23:31:47.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.23:31:47.72#ibcon#[25=AT04-07\r\n] 2006.201.23:31:47.72#ibcon#*before write, iclass 30, count 2 2006.201.23:31:47.72#ibcon#enter sib2, iclass 30, count 2 2006.201.23:31:47.72#ibcon#flushed, iclass 30, count 2 2006.201.23:31:47.72#ibcon#about to write, iclass 30, count 2 2006.201.23:31:47.72#ibcon#wrote, iclass 30, count 2 2006.201.23:31:47.72#ibcon#about to read 3, iclass 30, count 2 2006.201.23:31:47.75#ibcon#read 3, iclass 30, count 2 2006.201.23:31:47.75#ibcon#about to read 4, iclass 30, count 2 2006.201.23:31:47.75#ibcon#read 4, iclass 30, count 2 2006.201.23:31:47.75#ibcon#about to read 5, iclass 30, count 2 2006.201.23:31:47.75#ibcon#read 5, iclass 30, count 2 2006.201.23:31:47.75#ibcon#about to read 6, iclass 30, count 2 2006.201.23:31:47.75#ibcon#read 6, iclass 30, count 2 2006.201.23:31:47.75#ibcon#end of sib2, iclass 30, count 2 2006.201.23:31:47.75#ibcon#*after write, iclass 30, count 2 2006.201.23:31:47.75#ibcon#*before return 0, iclass 30, count 2 2006.201.23:31:47.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:47.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:47.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.23:31:47.75#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:47.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:47.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:47.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:47.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.23:31:47.87#ibcon#first serial, iclass 30, count 0 2006.201.23:31:47.87#ibcon#enter sib2, iclass 30, count 0 2006.201.23:31:47.87#ibcon#flushed, iclass 30, count 0 2006.201.23:31:47.87#ibcon#about to write, iclass 30, count 0 2006.201.23:31:47.87#ibcon#wrote, iclass 30, count 0 2006.201.23:31:47.87#ibcon#about to read 3, iclass 30, count 0 2006.201.23:31:47.89#ibcon#read 3, iclass 30, count 0 2006.201.23:31:47.89#ibcon#about to read 4, iclass 30, count 0 2006.201.23:31:47.89#ibcon#read 4, iclass 30, count 0 2006.201.23:31:47.89#ibcon#about to read 5, iclass 30, count 0 2006.201.23:31:47.89#ibcon#read 5, iclass 30, count 0 2006.201.23:31:47.89#ibcon#about to read 6, iclass 30, count 0 2006.201.23:31:47.89#ibcon#read 6, iclass 30, count 0 2006.201.23:31:47.89#ibcon#end of sib2, iclass 30, count 0 2006.201.23:31:47.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.23:31:47.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.23:31:47.89#ibcon#[25=USB\r\n] 2006.201.23:31:47.89#ibcon#*before write, iclass 30, count 0 2006.201.23:31:47.89#ibcon#enter sib2, iclass 30, count 0 2006.201.23:31:47.89#ibcon#flushed, iclass 30, count 0 2006.201.23:31:47.89#ibcon#about to write, iclass 30, count 0 2006.201.23:31:47.89#ibcon#wrote, iclass 30, count 0 2006.201.23:31:47.89#ibcon#about to read 3, iclass 30, count 0 2006.201.23:31:47.92#ibcon#read 3, iclass 30, count 0 2006.201.23:31:47.92#ibcon#about to read 4, iclass 30, count 0 2006.201.23:31:47.92#ibcon#read 4, iclass 30, count 0 2006.201.23:31:47.92#ibcon#about to read 5, iclass 30, count 0 2006.201.23:31:47.92#ibcon#read 5, iclass 30, count 0 2006.201.23:31:47.92#ibcon#about to read 6, iclass 30, count 0 2006.201.23:31:47.92#ibcon#read 6, iclass 30, count 0 2006.201.23:31:47.92#ibcon#end of sib2, iclass 30, count 0 2006.201.23:31:47.92#ibcon#*after write, iclass 30, count 0 2006.201.23:31:47.92#ibcon#*before return 0, iclass 30, count 0 2006.201.23:31:47.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:47.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:47.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.23:31:47.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.23:31:47.92$vck44/valo=5,734.99 2006.201.23:31:47.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.23:31:47.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.23:31:47.92#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:47.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:47.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:47.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:47.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.23:31:47.92#ibcon#first serial, iclass 32, count 0 2006.201.23:31:47.92#ibcon#enter sib2, iclass 32, count 0 2006.201.23:31:47.92#ibcon#flushed, iclass 32, count 0 2006.201.23:31:47.92#ibcon#about to write, iclass 32, count 0 2006.201.23:31:47.92#ibcon#wrote, iclass 32, count 0 2006.201.23:31:47.92#ibcon#about to read 3, iclass 32, count 0 2006.201.23:31:47.94#ibcon#read 3, iclass 32, count 0 2006.201.23:31:47.94#ibcon#about to read 4, iclass 32, count 0 2006.201.23:31:47.94#ibcon#read 4, iclass 32, count 0 2006.201.23:31:47.94#ibcon#about to read 5, iclass 32, count 0 2006.201.23:31:47.94#ibcon#read 5, iclass 32, count 0 2006.201.23:31:47.94#ibcon#about to read 6, iclass 32, count 0 2006.201.23:31:47.94#ibcon#read 6, iclass 32, count 0 2006.201.23:31:47.94#ibcon#end of sib2, iclass 32, count 0 2006.201.23:31:47.94#ibcon#*mode == 0, iclass 32, count 0 2006.201.23:31:47.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.23:31:47.94#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.23:31:47.94#ibcon#*before write, iclass 32, count 0 2006.201.23:31:47.94#ibcon#enter sib2, iclass 32, count 0 2006.201.23:31:47.94#ibcon#flushed, iclass 32, count 0 2006.201.23:31:47.94#ibcon#about to write, iclass 32, count 0 2006.201.23:31:47.94#ibcon#wrote, iclass 32, count 0 2006.201.23:31:47.94#ibcon#about to read 3, iclass 32, count 0 2006.201.23:31:47.98#ibcon#read 3, iclass 32, count 0 2006.201.23:31:47.98#ibcon#about to read 4, iclass 32, count 0 2006.201.23:31:47.98#ibcon#read 4, iclass 32, count 0 2006.201.23:31:47.98#ibcon#about to read 5, iclass 32, count 0 2006.201.23:31:47.98#ibcon#read 5, iclass 32, count 0 2006.201.23:31:47.98#ibcon#about to read 6, iclass 32, count 0 2006.201.23:31:47.98#ibcon#read 6, iclass 32, count 0 2006.201.23:31:47.98#ibcon#end of sib2, iclass 32, count 0 2006.201.23:31:47.98#ibcon#*after write, iclass 32, count 0 2006.201.23:31:47.98#ibcon#*before return 0, iclass 32, count 0 2006.201.23:31:47.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:47.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:47.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.23:31:47.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.23:31:47.98$vck44/va=5,4 2006.201.23:31:47.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.23:31:47.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.23:31:47.98#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:47.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:48.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:48.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:48.04#ibcon#enter wrdev, iclass 34, count 2 2006.201.23:31:48.04#ibcon#first serial, iclass 34, count 2 2006.201.23:31:48.04#ibcon#enter sib2, iclass 34, count 2 2006.201.23:31:48.04#ibcon#flushed, iclass 34, count 2 2006.201.23:31:48.04#ibcon#about to write, iclass 34, count 2 2006.201.23:31:48.04#ibcon#wrote, iclass 34, count 2 2006.201.23:31:48.04#ibcon#about to read 3, iclass 34, count 2 2006.201.23:31:48.06#ibcon#read 3, iclass 34, count 2 2006.201.23:31:48.06#ibcon#about to read 4, iclass 34, count 2 2006.201.23:31:48.06#ibcon#read 4, iclass 34, count 2 2006.201.23:31:48.06#ibcon#about to read 5, iclass 34, count 2 2006.201.23:31:48.06#ibcon#read 5, iclass 34, count 2 2006.201.23:31:48.06#ibcon#about to read 6, iclass 34, count 2 2006.201.23:31:48.06#ibcon#read 6, iclass 34, count 2 2006.201.23:31:48.06#ibcon#end of sib2, iclass 34, count 2 2006.201.23:31:48.06#ibcon#*mode == 0, iclass 34, count 2 2006.201.23:31:48.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.23:31:48.06#ibcon#[25=AT05-04\r\n] 2006.201.23:31:48.06#ibcon#*before write, iclass 34, count 2 2006.201.23:31:48.06#ibcon#enter sib2, iclass 34, count 2 2006.201.23:31:48.06#ibcon#flushed, iclass 34, count 2 2006.201.23:31:48.06#ibcon#about to write, iclass 34, count 2 2006.201.23:31:48.06#ibcon#wrote, iclass 34, count 2 2006.201.23:31:48.06#ibcon#about to read 3, iclass 34, count 2 2006.201.23:31:48.09#ibcon#read 3, iclass 34, count 2 2006.201.23:31:48.09#ibcon#about to read 4, iclass 34, count 2 2006.201.23:31:48.09#ibcon#read 4, iclass 34, count 2 2006.201.23:31:48.09#ibcon#about to read 5, iclass 34, count 2 2006.201.23:31:48.09#ibcon#read 5, iclass 34, count 2 2006.201.23:31:48.09#ibcon#about to read 6, iclass 34, count 2 2006.201.23:31:48.09#ibcon#read 6, iclass 34, count 2 2006.201.23:31:48.09#ibcon#end of sib2, iclass 34, count 2 2006.201.23:31:48.09#ibcon#*after write, iclass 34, count 2 2006.201.23:31:48.09#ibcon#*before return 0, iclass 34, count 2 2006.201.23:31:48.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:48.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:48.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.23:31:48.09#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:48.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:48.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:48.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:48.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.23:31:48.21#ibcon#first serial, iclass 34, count 0 2006.201.23:31:48.21#ibcon#enter sib2, iclass 34, count 0 2006.201.23:31:48.21#ibcon#flushed, iclass 34, count 0 2006.201.23:31:48.21#ibcon#about to write, iclass 34, count 0 2006.201.23:31:48.21#ibcon#wrote, iclass 34, count 0 2006.201.23:31:48.21#ibcon#about to read 3, iclass 34, count 0 2006.201.23:31:48.23#ibcon#read 3, iclass 34, count 0 2006.201.23:31:48.23#ibcon#about to read 4, iclass 34, count 0 2006.201.23:31:48.23#ibcon#read 4, iclass 34, count 0 2006.201.23:31:48.23#ibcon#about to read 5, iclass 34, count 0 2006.201.23:31:48.23#ibcon#read 5, iclass 34, count 0 2006.201.23:31:48.23#ibcon#about to read 6, iclass 34, count 0 2006.201.23:31:48.23#ibcon#read 6, iclass 34, count 0 2006.201.23:31:48.23#ibcon#end of sib2, iclass 34, count 0 2006.201.23:31:48.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.23:31:48.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.23:31:48.23#ibcon#[25=USB\r\n] 2006.201.23:31:48.23#ibcon#*before write, iclass 34, count 0 2006.201.23:31:48.23#ibcon#enter sib2, iclass 34, count 0 2006.201.23:31:48.23#ibcon#flushed, iclass 34, count 0 2006.201.23:31:48.23#ibcon#about to write, iclass 34, count 0 2006.201.23:31:48.23#ibcon#wrote, iclass 34, count 0 2006.201.23:31:48.23#ibcon#about to read 3, iclass 34, count 0 2006.201.23:31:48.26#ibcon#read 3, iclass 34, count 0 2006.201.23:31:48.26#ibcon#about to read 4, iclass 34, count 0 2006.201.23:31:48.26#ibcon#read 4, iclass 34, count 0 2006.201.23:31:48.26#ibcon#about to read 5, iclass 34, count 0 2006.201.23:31:48.26#ibcon#read 5, iclass 34, count 0 2006.201.23:31:48.26#ibcon#about to read 6, iclass 34, count 0 2006.201.23:31:48.26#ibcon#read 6, iclass 34, count 0 2006.201.23:31:48.26#ibcon#end of sib2, iclass 34, count 0 2006.201.23:31:48.26#ibcon#*after write, iclass 34, count 0 2006.201.23:31:48.26#ibcon#*before return 0, iclass 34, count 0 2006.201.23:31:48.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:48.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:48.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.23:31:48.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.23:31:48.26$vck44/valo=6,814.99 2006.201.23:31:48.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.23:31:48.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.23:31:48.26#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:48.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:48.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:48.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:48.26#ibcon#enter wrdev, iclass 36, count 0 2006.201.23:31:48.26#ibcon#first serial, iclass 36, count 0 2006.201.23:31:48.26#ibcon#enter sib2, iclass 36, count 0 2006.201.23:31:48.26#ibcon#flushed, iclass 36, count 0 2006.201.23:31:48.26#ibcon#about to write, iclass 36, count 0 2006.201.23:31:48.26#ibcon#wrote, iclass 36, count 0 2006.201.23:31:48.26#ibcon#about to read 3, iclass 36, count 0 2006.201.23:31:48.28#ibcon#read 3, iclass 36, count 0 2006.201.23:31:48.28#ibcon#about to read 4, iclass 36, count 0 2006.201.23:31:48.28#ibcon#read 4, iclass 36, count 0 2006.201.23:31:48.28#ibcon#about to read 5, iclass 36, count 0 2006.201.23:31:48.28#ibcon#read 5, iclass 36, count 0 2006.201.23:31:48.28#ibcon#about to read 6, iclass 36, count 0 2006.201.23:31:48.28#ibcon#read 6, iclass 36, count 0 2006.201.23:31:48.28#ibcon#end of sib2, iclass 36, count 0 2006.201.23:31:48.28#ibcon#*mode == 0, iclass 36, count 0 2006.201.23:31:48.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.23:31:48.28#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.23:31:48.28#ibcon#*before write, iclass 36, count 0 2006.201.23:31:48.28#ibcon#enter sib2, iclass 36, count 0 2006.201.23:31:48.28#ibcon#flushed, iclass 36, count 0 2006.201.23:31:48.28#ibcon#about to write, iclass 36, count 0 2006.201.23:31:48.28#ibcon#wrote, iclass 36, count 0 2006.201.23:31:48.28#ibcon#about to read 3, iclass 36, count 0 2006.201.23:31:48.32#ibcon#read 3, iclass 36, count 0 2006.201.23:31:48.32#ibcon#about to read 4, iclass 36, count 0 2006.201.23:31:48.32#ibcon#read 4, iclass 36, count 0 2006.201.23:31:48.32#ibcon#about to read 5, iclass 36, count 0 2006.201.23:31:48.32#ibcon#read 5, iclass 36, count 0 2006.201.23:31:48.32#ibcon#about to read 6, iclass 36, count 0 2006.201.23:31:48.32#ibcon#read 6, iclass 36, count 0 2006.201.23:31:48.32#ibcon#end of sib2, iclass 36, count 0 2006.201.23:31:48.32#ibcon#*after write, iclass 36, count 0 2006.201.23:31:48.32#ibcon#*before return 0, iclass 36, count 0 2006.201.23:31:48.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:48.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:48.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.23:31:48.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.23:31:48.32$vck44/va=6,5 2006.201.23:31:48.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.23:31:48.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.23:31:48.32#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:48.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:48.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:48.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:48.38#ibcon#enter wrdev, iclass 38, count 2 2006.201.23:31:48.38#ibcon#first serial, iclass 38, count 2 2006.201.23:31:48.38#ibcon#enter sib2, iclass 38, count 2 2006.201.23:31:48.38#ibcon#flushed, iclass 38, count 2 2006.201.23:31:48.38#ibcon#about to write, iclass 38, count 2 2006.201.23:31:48.38#ibcon#wrote, iclass 38, count 2 2006.201.23:31:48.38#ibcon#about to read 3, iclass 38, count 2 2006.201.23:31:48.40#ibcon#read 3, iclass 38, count 2 2006.201.23:31:48.40#ibcon#about to read 4, iclass 38, count 2 2006.201.23:31:48.40#ibcon#read 4, iclass 38, count 2 2006.201.23:31:48.40#ibcon#about to read 5, iclass 38, count 2 2006.201.23:31:48.40#ibcon#read 5, iclass 38, count 2 2006.201.23:31:48.40#ibcon#about to read 6, iclass 38, count 2 2006.201.23:31:48.40#ibcon#read 6, iclass 38, count 2 2006.201.23:31:48.40#ibcon#end of sib2, iclass 38, count 2 2006.201.23:31:48.40#ibcon#*mode == 0, iclass 38, count 2 2006.201.23:31:48.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.23:31:48.40#ibcon#[25=AT06-05\r\n] 2006.201.23:31:48.40#ibcon#*before write, iclass 38, count 2 2006.201.23:31:48.40#ibcon#enter sib2, iclass 38, count 2 2006.201.23:31:48.40#ibcon#flushed, iclass 38, count 2 2006.201.23:31:48.40#ibcon#about to write, iclass 38, count 2 2006.201.23:31:48.40#ibcon#wrote, iclass 38, count 2 2006.201.23:31:48.40#ibcon#about to read 3, iclass 38, count 2 2006.201.23:31:48.43#ibcon#read 3, iclass 38, count 2 2006.201.23:31:48.43#ibcon#about to read 4, iclass 38, count 2 2006.201.23:31:48.43#ibcon#read 4, iclass 38, count 2 2006.201.23:31:48.43#ibcon#about to read 5, iclass 38, count 2 2006.201.23:31:48.43#ibcon#read 5, iclass 38, count 2 2006.201.23:31:48.43#ibcon#about to read 6, iclass 38, count 2 2006.201.23:31:48.43#ibcon#read 6, iclass 38, count 2 2006.201.23:31:48.43#ibcon#end of sib2, iclass 38, count 2 2006.201.23:31:48.43#ibcon#*after write, iclass 38, count 2 2006.201.23:31:48.43#ibcon#*before return 0, iclass 38, count 2 2006.201.23:31:48.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:48.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:48.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.23:31:48.43#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:48.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:48.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:48.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:48.55#ibcon#enter wrdev, iclass 38, count 0 2006.201.23:31:48.55#ibcon#first serial, iclass 38, count 0 2006.201.23:31:48.55#ibcon#enter sib2, iclass 38, count 0 2006.201.23:31:48.55#ibcon#flushed, iclass 38, count 0 2006.201.23:31:48.55#ibcon#about to write, iclass 38, count 0 2006.201.23:31:48.55#ibcon#wrote, iclass 38, count 0 2006.201.23:31:48.55#ibcon#about to read 3, iclass 38, count 0 2006.201.23:31:48.57#ibcon#read 3, iclass 38, count 0 2006.201.23:31:48.57#ibcon#about to read 4, iclass 38, count 0 2006.201.23:31:48.57#ibcon#read 4, iclass 38, count 0 2006.201.23:31:48.57#ibcon#about to read 5, iclass 38, count 0 2006.201.23:31:48.57#ibcon#read 5, iclass 38, count 0 2006.201.23:31:48.57#ibcon#about to read 6, iclass 38, count 0 2006.201.23:31:48.57#ibcon#read 6, iclass 38, count 0 2006.201.23:31:48.57#ibcon#end of sib2, iclass 38, count 0 2006.201.23:31:48.57#ibcon#*mode == 0, iclass 38, count 0 2006.201.23:31:48.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.23:31:48.57#ibcon#[25=USB\r\n] 2006.201.23:31:48.57#ibcon#*before write, iclass 38, count 0 2006.201.23:31:48.57#ibcon#enter sib2, iclass 38, count 0 2006.201.23:31:48.57#ibcon#flushed, iclass 38, count 0 2006.201.23:31:48.57#ibcon#about to write, iclass 38, count 0 2006.201.23:31:48.57#ibcon#wrote, iclass 38, count 0 2006.201.23:31:48.57#ibcon#about to read 3, iclass 38, count 0 2006.201.23:31:48.60#ibcon#read 3, iclass 38, count 0 2006.201.23:31:48.60#ibcon#about to read 4, iclass 38, count 0 2006.201.23:31:48.60#ibcon#read 4, iclass 38, count 0 2006.201.23:31:48.60#ibcon#about to read 5, iclass 38, count 0 2006.201.23:31:48.60#ibcon#read 5, iclass 38, count 0 2006.201.23:31:48.60#ibcon#about to read 6, iclass 38, count 0 2006.201.23:31:48.60#ibcon#read 6, iclass 38, count 0 2006.201.23:31:48.60#ibcon#end of sib2, iclass 38, count 0 2006.201.23:31:48.60#ibcon#*after write, iclass 38, count 0 2006.201.23:31:48.60#ibcon#*before return 0, iclass 38, count 0 2006.201.23:31:48.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:48.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:48.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.23:31:48.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.23:31:48.60$vck44/valo=7,864.99 2006.201.23:31:48.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.23:31:48.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.23:31:48.60#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:48.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:48.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:48.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:48.60#ibcon#enter wrdev, iclass 40, count 0 2006.201.23:31:48.60#ibcon#first serial, iclass 40, count 0 2006.201.23:31:48.60#ibcon#enter sib2, iclass 40, count 0 2006.201.23:31:48.60#ibcon#flushed, iclass 40, count 0 2006.201.23:31:48.60#ibcon#about to write, iclass 40, count 0 2006.201.23:31:48.60#ibcon#wrote, iclass 40, count 0 2006.201.23:31:48.60#ibcon#about to read 3, iclass 40, count 0 2006.201.23:31:48.62#ibcon#read 3, iclass 40, count 0 2006.201.23:31:48.62#ibcon#about to read 4, iclass 40, count 0 2006.201.23:31:48.62#ibcon#read 4, iclass 40, count 0 2006.201.23:31:48.62#ibcon#about to read 5, iclass 40, count 0 2006.201.23:31:48.62#ibcon#read 5, iclass 40, count 0 2006.201.23:31:48.62#ibcon#about to read 6, iclass 40, count 0 2006.201.23:31:48.62#ibcon#read 6, iclass 40, count 0 2006.201.23:31:48.62#ibcon#end of sib2, iclass 40, count 0 2006.201.23:31:48.62#ibcon#*mode == 0, iclass 40, count 0 2006.201.23:31:48.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.23:31:48.62#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.23:31:48.62#ibcon#*before write, iclass 40, count 0 2006.201.23:31:48.62#ibcon#enter sib2, iclass 40, count 0 2006.201.23:31:48.62#ibcon#flushed, iclass 40, count 0 2006.201.23:31:48.62#ibcon#about to write, iclass 40, count 0 2006.201.23:31:48.62#ibcon#wrote, iclass 40, count 0 2006.201.23:31:48.62#ibcon#about to read 3, iclass 40, count 0 2006.201.23:31:48.66#ibcon#read 3, iclass 40, count 0 2006.201.23:31:48.66#ibcon#about to read 4, iclass 40, count 0 2006.201.23:31:48.66#ibcon#read 4, iclass 40, count 0 2006.201.23:31:48.66#ibcon#about to read 5, iclass 40, count 0 2006.201.23:31:48.66#ibcon#read 5, iclass 40, count 0 2006.201.23:31:48.66#ibcon#about to read 6, iclass 40, count 0 2006.201.23:31:48.66#ibcon#read 6, iclass 40, count 0 2006.201.23:31:48.66#ibcon#end of sib2, iclass 40, count 0 2006.201.23:31:48.66#ibcon#*after write, iclass 40, count 0 2006.201.23:31:48.66#ibcon#*before return 0, iclass 40, count 0 2006.201.23:31:48.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:48.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:48.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.23:31:48.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.23:31:48.66$vck44/va=7,5 2006.201.23:31:48.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.23:31:48.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.23:31:48.66#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:48.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:48.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:48.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:48.72#ibcon#enter wrdev, iclass 4, count 2 2006.201.23:31:48.72#ibcon#first serial, iclass 4, count 2 2006.201.23:31:48.72#ibcon#enter sib2, iclass 4, count 2 2006.201.23:31:48.72#ibcon#flushed, iclass 4, count 2 2006.201.23:31:48.72#ibcon#about to write, iclass 4, count 2 2006.201.23:31:48.72#ibcon#wrote, iclass 4, count 2 2006.201.23:31:48.72#ibcon#about to read 3, iclass 4, count 2 2006.201.23:31:48.74#ibcon#read 3, iclass 4, count 2 2006.201.23:31:48.74#ibcon#about to read 4, iclass 4, count 2 2006.201.23:31:48.74#ibcon#read 4, iclass 4, count 2 2006.201.23:31:48.74#ibcon#about to read 5, iclass 4, count 2 2006.201.23:31:48.74#ibcon#read 5, iclass 4, count 2 2006.201.23:31:48.74#ibcon#about to read 6, iclass 4, count 2 2006.201.23:31:48.74#ibcon#read 6, iclass 4, count 2 2006.201.23:31:48.74#ibcon#end of sib2, iclass 4, count 2 2006.201.23:31:48.74#ibcon#*mode == 0, iclass 4, count 2 2006.201.23:31:48.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.23:31:48.74#ibcon#[25=AT07-05\r\n] 2006.201.23:31:48.74#ibcon#*before write, iclass 4, count 2 2006.201.23:31:48.74#ibcon#enter sib2, iclass 4, count 2 2006.201.23:31:48.74#ibcon#flushed, iclass 4, count 2 2006.201.23:31:48.74#ibcon#about to write, iclass 4, count 2 2006.201.23:31:48.74#ibcon#wrote, iclass 4, count 2 2006.201.23:31:48.74#ibcon#about to read 3, iclass 4, count 2 2006.201.23:31:48.77#ibcon#read 3, iclass 4, count 2 2006.201.23:31:48.77#ibcon#about to read 4, iclass 4, count 2 2006.201.23:31:48.77#ibcon#read 4, iclass 4, count 2 2006.201.23:31:48.77#ibcon#about to read 5, iclass 4, count 2 2006.201.23:31:48.77#ibcon#read 5, iclass 4, count 2 2006.201.23:31:48.77#ibcon#about to read 6, iclass 4, count 2 2006.201.23:31:48.77#ibcon#read 6, iclass 4, count 2 2006.201.23:31:48.77#ibcon#end of sib2, iclass 4, count 2 2006.201.23:31:48.77#ibcon#*after write, iclass 4, count 2 2006.201.23:31:48.77#ibcon#*before return 0, iclass 4, count 2 2006.201.23:31:48.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:48.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:48.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.23:31:48.77#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:48.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:48.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:48.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:48.89#ibcon#enter wrdev, iclass 4, count 0 2006.201.23:31:48.89#ibcon#first serial, iclass 4, count 0 2006.201.23:31:48.89#ibcon#enter sib2, iclass 4, count 0 2006.201.23:31:48.89#ibcon#flushed, iclass 4, count 0 2006.201.23:31:48.89#ibcon#about to write, iclass 4, count 0 2006.201.23:31:48.89#ibcon#wrote, iclass 4, count 0 2006.201.23:31:48.89#ibcon#about to read 3, iclass 4, count 0 2006.201.23:31:48.91#ibcon#read 3, iclass 4, count 0 2006.201.23:31:48.91#ibcon#about to read 4, iclass 4, count 0 2006.201.23:31:48.91#ibcon#read 4, iclass 4, count 0 2006.201.23:31:48.91#ibcon#about to read 5, iclass 4, count 0 2006.201.23:31:48.91#ibcon#read 5, iclass 4, count 0 2006.201.23:31:48.91#ibcon#about to read 6, iclass 4, count 0 2006.201.23:31:48.91#ibcon#read 6, iclass 4, count 0 2006.201.23:31:48.91#ibcon#end of sib2, iclass 4, count 0 2006.201.23:31:48.91#ibcon#*mode == 0, iclass 4, count 0 2006.201.23:31:48.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.23:31:48.91#ibcon#[25=USB\r\n] 2006.201.23:31:48.91#ibcon#*before write, iclass 4, count 0 2006.201.23:31:48.91#ibcon#enter sib2, iclass 4, count 0 2006.201.23:31:48.91#ibcon#flushed, iclass 4, count 0 2006.201.23:31:48.91#ibcon#about to write, iclass 4, count 0 2006.201.23:31:48.91#ibcon#wrote, iclass 4, count 0 2006.201.23:31:48.91#ibcon#about to read 3, iclass 4, count 0 2006.201.23:31:48.94#ibcon#read 3, iclass 4, count 0 2006.201.23:31:48.94#ibcon#about to read 4, iclass 4, count 0 2006.201.23:31:48.94#ibcon#read 4, iclass 4, count 0 2006.201.23:31:48.94#ibcon#about to read 5, iclass 4, count 0 2006.201.23:31:48.94#ibcon#read 5, iclass 4, count 0 2006.201.23:31:48.94#ibcon#about to read 6, iclass 4, count 0 2006.201.23:31:48.94#ibcon#read 6, iclass 4, count 0 2006.201.23:31:48.94#ibcon#end of sib2, iclass 4, count 0 2006.201.23:31:48.94#ibcon#*after write, iclass 4, count 0 2006.201.23:31:48.94#ibcon#*before return 0, iclass 4, count 0 2006.201.23:31:48.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:48.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:48.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.23:31:48.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.23:31:48.94$vck44/valo=8,884.99 2006.201.23:31:48.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.23:31:48.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.23:31:48.94#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:48.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:48.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:48.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:48.94#ibcon#enter wrdev, iclass 6, count 0 2006.201.23:31:48.94#ibcon#first serial, iclass 6, count 0 2006.201.23:31:48.94#ibcon#enter sib2, iclass 6, count 0 2006.201.23:31:48.94#ibcon#flushed, iclass 6, count 0 2006.201.23:31:48.94#ibcon#about to write, iclass 6, count 0 2006.201.23:31:48.94#ibcon#wrote, iclass 6, count 0 2006.201.23:31:48.94#ibcon#about to read 3, iclass 6, count 0 2006.201.23:31:48.96#ibcon#read 3, iclass 6, count 0 2006.201.23:31:48.96#ibcon#about to read 4, iclass 6, count 0 2006.201.23:31:48.96#ibcon#read 4, iclass 6, count 0 2006.201.23:31:48.96#ibcon#about to read 5, iclass 6, count 0 2006.201.23:31:48.96#ibcon#read 5, iclass 6, count 0 2006.201.23:31:48.96#ibcon#about to read 6, iclass 6, count 0 2006.201.23:31:48.96#ibcon#read 6, iclass 6, count 0 2006.201.23:31:48.96#ibcon#end of sib2, iclass 6, count 0 2006.201.23:31:48.96#ibcon#*mode == 0, iclass 6, count 0 2006.201.23:31:48.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.23:31:48.96#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.23:31:48.96#ibcon#*before write, iclass 6, count 0 2006.201.23:31:48.96#ibcon#enter sib2, iclass 6, count 0 2006.201.23:31:48.96#ibcon#flushed, iclass 6, count 0 2006.201.23:31:48.96#ibcon#about to write, iclass 6, count 0 2006.201.23:31:48.96#ibcon#wrote, iclass 6, count 0 2006.201.23:31:48.96#ibcon#about to read 3, iclass 6, count 0 2006.201.23:31:49.00#ibcon#read 3, iclass 6, count 0 2006.201.23:31:49.00#ibcon#about to read 4, iclass 6, count 0 2006.201.23:31:49.00#ibcon#read 4, iclass 6, count 0 2006.201.23:31:49.00#ibcon#about to read 5, iclass 6, count 0 2006.201.23:31:49.00#ibcon#read 5, iclass 6, count 0 2006.201.23:31:49.00#ibcon#about to read 6, iclass 6, count 0 2006.201.23:31:49.00#ibcon#read 6, iclass 6, count 0 2006.201.23:31:49.00#ibcon#end of sib2, iclass 6, count 0 2006.201.23:31:49.00#ibcon#*after write, iclass 6, count 0 2006.201.23:31:49.00#ibcon#*before return 0, iclass 6, count 0 2006.201.23:31:49.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:49.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:49.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.23:31:49.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.23:31:49.00$vck44/va=8,4 2006.201.23:31:49.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.23:31:49.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.23:31:49.00#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:49.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:31:49.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:31:49.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:31:49.06#ibcon#enter wrdev, iclass 10, count 2 2006.201.23:31:49.06#ibcon#first serial, iclass 10, count 2 2006.201.23:31:49.06#ibcon#enter sib2, iclass 10, count 2 2006.201.23:31:49.06#ibcon#flushed, iclass 10, count 2 2006.201.23:31:49.06#ibcon#about to write, iclass 10, count 2 2006.201.23:31:49.06#ibcon#wrote, iclass 10, count 2 2006.201.23:31:49.06#ibcon#about to read 3, iclass 10, count 2 2006.201.23:31:49.08#ibcon#read 3, iclass 10, count 2 2006.201.23:31:49.08#ibcon#about to read 4, iclass 10, count 2 2006.201.23:31:49.08#ibcon#read 4, iclass 10, count 2 2006.201.23:31:49.08#ibcon#about to read 5, iclass 10, count 2 2006.201.23:31:49.08#ibcon#read 5, iclass 10, count 2 2006.201.23:31:49.08#ibcon#about to read 6, iclass 10, count 2 2006.201.23:31:49.08#ibcon#read 6, iclass 10, count 2 2006.201.23:31:49.08#ibcon#end of sib2, iclass 10, count 2 2006.201.23:31:49.08#ibcon#*mode == 0, iclass 10, count 2 2006.201.23:31:49.08#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.23:31:49.08#ibcon#[25=AT08-04\r\n] 2006.201.23:31:49.08#ibcon#*before write, iclass 10, count 2 2006.201.23:31:49.08#ibcon#enter sib2, iclass 10, count 2 2006.201.23:31:49.08#ibcon#flushed, iclass 10, count 2 2006.201.23:31:49.08#ibcon#about to write, iclass 10, count 2 2006.201.23:31:49.08#ibcon#wrote, iclass 10, count 2 2006.201.23:31:49.08#ibcon#about to read 3, iclass 10, count 2 2006.201.23:31:49.11#ibcon#read 3, iclass 10, count 2 2006.201.23:31:49.11#ibcon#about to read 4, iclass 10, count 2 2006.201.23:31:49.11#ibcon#read 4, iclass 10, count 2 2006.201.23:31:49.11#ibcon#about to read 5, iclass 10, count 2 2006.201.23:31:49.11#ibcon#read 5, iclass 10, count 2 2006.201.23:31:49.11#ibcon#about to read 6, iclass 10, count 2 2006.201.23:31:49.11#ibcon#read 6, iclass 10, count 2 2006.201.23:31:49.11#ibcon#end of sib2, iclass 10, count 2 2006.201.23:31:49.11#ibcon#*after write, iclass 10, count 2 2006.201.23:31:49.11#ibcon#*before return 0, iclass 10, count 2 2006.201.23:31:49.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:31:49.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:31:49.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.23:31:49.11#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:49.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:31:49.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:31:49.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:31:49.23#ibcon#enter wrdev, iclass 10, count 0 2006.201.23:31:49.23#ibcon#first serial, iclass 10, count 0 2006.201.23:31:49.23#ibcon#enter sib2, iclass 10, count 0 2006.201.23:31:49.23#ibcon#flushed, iclass 10, count 0 2006.201.23:31:49.23#ibcon#about to write, iclass 10, count 0 2006.201.23:31:49.23#ibcon#wrote, iclass 10, count 0 2006.201.23:31:49.23#ibcon#about to read 3, iclass 10, count 0 2006.201.23:31:49.25#ibcon#read 3, iclass 10, count 0 2006.201.23:31:49.25#ibcon#about to read 4, iclass 10, count 0 2006.201.23:31:49.25#ibcon#read 4, iclass 10, count 0 2006.201.23:31:49.25#ibcon#about to read 5, iclass 10, count 0 2006.201.23:31:49.25#ibcon#read 5, iclass 10, count 0 2006.201.23:31:49.25#ibcon#about to read 6, iclass 10, count 0 2006.201.23:31:49.25#ibcon#read 6, iclass 10, count 0 2006.201.23:31:49.25#ibcon#end of sib2, iclass 10, count 0 2006.201.23:31:49.25#ibcon#*mode == 0, iclass 10, count 0 2006.201.23:31:49.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.23:31:49.25#ibcon#[25=USB\r\n] 2006.201.23:31:49.25#ibcon#*before write, iclass 10, count 0 2006.201.23:31:49.25#ibcon#enter sib2, iclass 10, count 0 2006.201.23:31:49.25#ibcon#flushed, iclass 10, count 0 2006.201.23:31:49.25#ibcon#about to write, iclass 10, count 0 2006.201.23:31:49.25#ibcon#wrote, iclass 10, count 0 2006.201.23:31:49.25#ibcon#about to read 3, iclass 10, count 0 2006.201.23:31:49.28#ibcon#read 3, iclass 10, count 0 2006.201.23:31:49.28#ibcon#about to read 4, iclass 10, count 0 2006.201.23:31:49.28#ibcon#read 4, iclass 10, count 0 2006.201.23:31:49.28#ibcon#about to read 5, iclass 10, count 0 2006.201.23:31:49.28#ibcon#read 5, iclass 10, count 0 2006.201.23:31:49.28#ibcon#about to read 6, iclass 10, count 0 2006.201.23:31:49.28#ibcon#read 6, iclass 10, count 0 2006.201.23:31:49.28#ibcon#end of sib2, iclass 10, count 0 2006.201.23:31:49.28#ibcon#*after write, iclass 10, count 0 2006.201.23:31:49.28#ibcon#*before return 0, iclass 10, count 0 2006.201.23:31:49.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:31:49.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:31:49.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.23:31:49.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.23:31:49.28$vck44/vblo=1,629.99 2006.201.23:31:49.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.23:31:49.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.23:31:49.28#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:49.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:31:49.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:31:49.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:31:49.28#ibcon#enter wrdev, iclass 12, count 0 2006.201.23:31:49.28#ibcon#first serial, iclass 12, count 0 2006.201.23:31:49.28#ibcon#enter sib2, iclass 12, count 0 2006.201.23:31:49.28#ibcon#flushed, iclass 12, count 0 2006.201.23:31:49.28#ibcon#about to write, iclass 12, count 0 2006.201.23:31:49.28#ibcon#wrote, iclass 12, count 0 2006.201.23:31:49.28#ibcon#about to read 3, iclass 12, count 0 2006.201.23:31:49.30#ibcon#read 3, iclass 12, count 0 2006.201.23:31:49.30#ibcon#about to read 4, iclass 12, count 0 2006.201.23:31:49.30#ibcon#read 4, iclass 12, count 0 2006.201.23:31:49.30#ibcon#about to read 5, iclass 12, count 0 2006.201.23:31:49.30#ibcon#read 5, iclass 12, count 0 2006.201.23:31:49.30#ibcon#about to read 6, iclass 12, count 0 2006.201.23:31:49.30#ibcon#read 6, iclass 12, count 0 2006.201.23:31:49.30#ibcon#end of sib2, iclass 12, count 0 2006.201.23:31:49.30#ibcon#*mode == 0, iclass 12, count 0 2006.201.23:31:49.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.23:31:49.30#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.23:31:49.30#ibcon#*before write, iclass 12, count 0 2006.201.23:31:49.30#ibcon#enter sib2, iclass 12, count 0 2006.201.23:31:49.30#ibcon#flushed, iclass 12, count 0 2006.201.23:31:49.30#ibcon#about to write, iclass 12, count 0 2006.201.23:31:49.30#ibcon#wrote, iclass 12, count 0 2006.201.23:31:49.30#ibcon#about to read 3, iclass 12, count 0 2006.201.23:31:49.34#ibcon#read 3, iclass 12, count 0 2006.201.23:31:49.34#ibcon#about to read 4, iclass 12, count 0 2006.201.23:31:49.34#ibcon#read 4, iclass 12, count 0 2006.201.23:31:49.34#ibcon#about to read 5, iclass 12, count 0 2006.201.23:31:49.34#ibcon#read 5, iclass 12, count 0 2006.201.23:31:49.34#ibcon#about to read 6, iclass 12, count 0 2006.201.23:31:49.34#ibcon#read 6, iclass 12, count 0 2006.201.23:31:49.34#ibcon#end of sib2, iclass 12, count 0 2006.201.23:31:49.34#ibcon#*after write, iclass 12, count 0 2006.201.23:31:49.34#ibcon#*before return 0, iclass 12, count 0 2006.201.23:31:49.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:31:49.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:31:49.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.23:31:49.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.23:31:49.34$vck44/vb=1,4 2006.201.23:31:49.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.23:31:49.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.23:31:49.34#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:49.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:31:49.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:31:49.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:31:49.34#ibcon#enter wrdev, iclass 14, count 2 2006.201.23:31:49.34#ibcon#first serial, iclass 14, count 2 2006.201.23:31:49.34#ibcon#enter sib2, iclass 14, count 2 2006.201.23:31:49.34#ibcon#flushed, iclass 14, count 2 2006.201.23:31:49.34#ibcon#about to write, iclass 14, count 2 2006.201.23:31:49.34#ibcon#wrote, iclass 14, count 2 2006.201.23:31:49.34#ibcon#about to read 3, iclass 14, count 2 2006.201.23:31:49.36#ibcon#read 3, iclass 14, count 2 2006.201.23:31:49.36#ibcon#about to read 4, iclass 14, count 2 2006.201.23:31:49.36#ibcon#read 4, iclass 14, count 2 2006.201.23:31:49.36#ibcon#about to read 5, iclass 14, count 2 2006.201.23:31:49.36#ibcon#read 5, iclass 14, count 2 2006.201.23:31:49.36#ibcon#about to read 6, iclass 14, count 2 2006.201.23:31:49.36#ibcon#read 6, iclass 14, count 2 2006.201.23:31:49.36#ibcon#end of sib2, iclass 14, count 2 2006.201.23:31:49.36#ibcon#*mode == 0, iclass 14, count 2 2006.201.23:31:49.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.23:31:49.36#ibcon#[27=AT01-04\r\n] 2006.201.23:31:49.36#ibcon#*before write, iclass 14, count 2 2006.201.23:31:49.36#ibcon#enter sib2, iclass 14, count 2 2006.201.23:31:49.36#ibcon#flushed, iclass 14, count 2 2006.201.23:31:49.36#ibcon#about to write, iclass 14, count 2 2006.201.23:31:49.36#ibcon#wrote, iclass 14, count 2 2006.201.23:31:49.36#ibcon#about to read 3, iclass 14, count 2 2006.201.23:31:49.39#ibcon#read 3, iclass 14, count 2 2006.201.23:31:49.39#ibcon#about to read 4, iclass 14, count 2 2006.201.23:31:49.39#ibcon#read 4, iclass 14, count 2 2006.201.23:31:49.39#ibcon#about to read 5, iclass 14, count 2 2006.201.23:31:49.39#ibcon#read 5, iclass 14, count 2 2006.201.23:31:49.39#ibcon#about to read 6, iclass 14, count 2 2006.201.23:31:49.39#ibcon#read 6, iclass 14, count 2 2006.201.23:31:49.39#ibcon#end of sib2, iclass 14, count 2 2006.201.23:31:49.39#ibcon#*after write, iclass 14, count 2 2006.201.23:31:49.39#ibcon#*before return 0, iclass 14, count 2 2006.201.23:31:49.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:31:49.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:31:49.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.23:31:49.39#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:49.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:31:49.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:31:49.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:31:49.51#ibcon#enter wrdev, iclass 14, count 0 2006.201.23:31:49.51#ibcon#first serial, iclass 14, count 0 2006.201.23:31:49.51#ibcon#enter sib2, iclass 14, count 0 2006.201.23:31:49.51#ibcon#flushed, iclass 14, count 0 2006.201.23:31:49.51#ibcon#about to write, iclass 14, count 0 2006.201.23:31:49.51#ibcon#wrote, iclass 14, count 0 2006.201.23:31:49.51#ibcon#about to read 3, iclass 14, count 0 2006.201.23:31:49.53#ibcon#read 3, iclass 14, count 0 2006.201.23:31:49.53#ibcon#about to read 4, iclass 14, count 0 2006.201.23:31:49.53#ibcon#read 4, iclass 14, count 0 2006.201.23:31:49.53#ibcon#about to read 5, iclass 14, count 0 2006.201.23:31:49.53#ibcon#read 5, iclass 14, count 0 2006.201.23:31:49.53#ibcon#about to read 6, iclass 14, count 0 2006.201.23:31:49.53#ibcon#read 6, iclass 14, count 0 2006.201.23:31:49.53#ibcon#end of sib2, iclass 14, count 0 2006.201.23:31:49.53#ibcon#*mode == 0, iclass 14, count 0 2006.201.23:31:49.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.23:31:49.53#ibcon#[27=USB\r\n] 2006.201.23:31:49.53#ibcon#*before write, iclass 14, count 0 2006.201.23:31:49.53#ibcon#enter sib2, iclass 14, count 0 2006.201.23:31:49.53#ibcon#flushed, iclass 14, count 0 2006.201.23:31:49.53#ibcon#about to write, iclass 14, count 0 2006.201.23:31:49.53#ibcon#wrote, iclass 14, count 0 2006.201.23:31:49.53#ibcon#about to read 3, iclass 14, count 0 2006.201.23:31:49.56#ibcon#read 3, iclass 14, count 0 2006.201.23:31:49.56#ibcon#about to read 4, iclass 14, count 0 2006.201.23:31:49.56#ibcon#read 4, iclass 14, count 0 2006.201.23:31:49.56#ibcon#about to read 5, iclass 14, count 0 2006.201.23:31:49.56#ibcon#read 5, iclass 14, count 0 2006.201.23:31:49.56#ibcon#about to read 6, iclass 14, count 0 2006.201.23:31:49.56#ibcon#read 6, iclass 14, count 0 2006.201.23:31:49.56#ibcon#end of sib2, iclass 14, count 0 2006.201.23:31:49.56#ibcon#*after write, iclass 14, count 0 2006.201.23:31:49.56#ibcon#*before return 0, iclass 14, count 0 2006.201.23:31:49.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:31:49.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:31:49.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.23:31:49.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.23:31:49.56$vck44/vblo=2,634.99 2006.201.23:31:49.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.23:31:49.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.23:31:49.56#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:49.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:49.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:49.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:49.56#ibcon#enter wrdev, iclass 16, count 0 2006.201.23:31:49.56#ibcon#first serial, iclass 16, count 0 2006.201.23:31:49.56#ibcon#enter sib2, iclass 16, count 0 2006.201.23:31:49.56#ibcon#flushed, iclass 16, count 0 2006.201.23:31:49.56#ibcon#about to write, iclass 16, count 0 2006.201.23:31:49.56#ibcon#wrote, iclass 16, count 0 2006.201.23:31:49.56#ibcon#about to read 3, iclass 16, count 0 2006.201.23:31:49.58#ibcon#read 3, iclass 16, count 0 2006.201.23:31:49.58#ibcon#about to read 4, iclass 16, count 0 2006.201.23:31:49.58#ibcon#read 4, iclass 16, count 0 2006.201.23:31:49.58#ibcon#about to read 5, iclass 16, count 0 2006.201.23:31:49.58#ibcon#read 5, iclass 16, count 0 2006.201.23:31:49.58#ibcon#about to read 6, iclass 16, count 0 2006.201.23:31:49.58#ibcon#read 6, iclass 16, count 0 2006.201.23:31:49.58#ibcon#end of sib2, iclass 16, count 0 2006.201.23:31:49.58#ibcon#*mode == 0, iclass 16, count 0 2006.201.23:31:49.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.23:31:49.58#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.23:31:49.58#ibcon#*before write, iclass 16, count 0 2006.201.23:31:49.58#ibcon#enter sib2, iclass 16, count 0 2006.201.23:31:49.58#ibcon#flushed, iclass 16, count 0 2006.201.23:31:49.58#ibcon#about to write, iclass 16, count 0 2006.201.23:31:49.58#ibcon#wrote, iclass 16, count 0 2006.201.23:31:49.58#ibcon#about to read 3, iclass 16, count 0 2006.201.23:31:49.62#ibcon#read 3, iclass 16, count 0 2006.201.23:31:49.62#ibcon#about to read 4, iclass 16, count 0 2006.201.23:31:49.62#ibcon#read 4, iclass 16, count 0 2006.201.23:31:49.62#ibcon#about to read 5, iclass 16, count 0 2006.201.23:31:49.62#ibcon#read 5, iclass 16, count 0 2006.201.23:31:49.62#ibcon#about to read 6, iclass 16, count 0 2006.201.23:31:49.62#ibcon#read 6, iclass 16, count 0 2006.201.23:31:49.62#ibcon#end of sib2, iclass 16, count 0 2006.201.23:31:49.62#ibcon#*after write, iclass 16, count 0 2006.201.23:31:49.62#ibcon#*before return 0, iclass 16, count 0 2006.201.23:31:49.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:49.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:31:49.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.23:31:49.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.23:31:49.62$vck44/vb=2,5 2006.201.23:31:49.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.23:31:49.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.23:31:49.62#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:49.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:49.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:49.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:49.68#ibcon#enter wrdev, iclass 18, count 2 2006.201.23:31:49.68#ibcon#first serial, iclass 18, count 2 2006.201.23:31:49.68#ibcon#enter sib2, iclass 18, count 2 2006.201.23:31:49.68#ibcon#flushed, iclass 18, count 2 2006.201.23:31:49.68#ibcon#about to write, iclass 18, count 2 2006.201.23:31:49.68#ibcon#wrote, iclass 18, count 2 2006.201.23:31:49.68#ibcon#about to read 3, iclass 18, count 2 2006.201.23:31:49.70#ibcon#read 3, iclass 18, count 2 2006.201.23:31:49.70#ibcon#about to read 4, iclass 18, count 2 2006.201.23:31:49.70#ibcon#read 4, iclass 18, count 2 2006.201.23:31:49.70#ibcon#about to read 5, iclass 18, count 2 2006.201.23:31:49.70#ibcon#read 5, iclass 18, count 2 2006.201.23:31:49.70#ibcon#about to read 6, iclass 18, count 2 2006.201.23:31:49.70#ibcon#read 6, iclass 18, count 2 2006.201.23:31:49.70#ibcon#end of sib2, iclass 18, count 2 2006.201.23:31:49.70#ibcon#*mode == 0, iclass 18, count 2 2006.201.23:31:49.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.23:31:49.70#ibcon#[27=AT02-05\r\n] 2006.201.23:31:49.70#ibcon#*before write, iclass 18, count 2 2006.201.23:31:49.70#ibcon#enter sib2, iclass 18, count 2 2006.201.23:31:49.70#ibcon#flushed, iclass 18, count 2 2006.201.23:31:49.70#ibcon#about to write, iclass 18, count 2 2006.201.23:31:49.70#ibcon#wrote, iclass 18, count 2 2006.201.23:31:49.70#ibcon#about to read 3, iclass 18, count 2 2006.201.23:31:49.73#ibcon#read 3, iclass 18, count 2 2006.201.23:31:49.73#ibcon#about to read 4, iclass 18, count 2 2006.201.23:31:49.73#ibcon#read 4, iclass 18, count 2 2006.201.23:31:49.73#ibcon#about to read 5, iclass 18, count 2 2006.201.23:31:49.73#ibcon#read 5, iclass 18, count 2 2006.201.23:31:49.73#ibcon#about to read 6, iclass 18, count 2 2006.201.23:31:49.73#ibcon#read 6, iclass 18, count 2 2006.201.23:31:49.73#ibcon#end of sib2, iclass 18, count 2 2006.201.23:31:49.73#ibcon#*after write, iclass 18, count 2 2006.201.23:31:49.73#ibcon#*before return 0, iclass 18, count 2 2006.201.23:31:49.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:49.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:31:49.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.23:31:49.73#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:49.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:49.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:49.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:49.85#ibcon#enter wrdev, iclass 18, count 0 2006.201.23:31:49.85#ibcon#first serial, iclass 18, count 0 2006.201.23:31:49.85#ibcon#enter sib2, iclass 18, count 0 2006.201.23:31:49.85#ibcon#flushed, iclass 18, count 0 2006.201.23:31:49.85#ibcon#about to write, iclass 18, count 0 2006.201.23:31:49.85#ibcon#wrote, iclass 18, count 0 2006.201.23:31:49.85#ibcon#about to read 3, iclass 18, count 0 2006.201.23:31:49.87#ibcon#read 3, iclass 18, count 0 2006.201.23:31:49.87#ibcon#about to read 4, iclass 18, count 0 2006.201.23:31:49.87#ibcon#read 4, iclass 18, count 0 2006.201.23:31:49.87#ibcon#about to read 5, iclass 18, count 0 2006.201.23:31:49.87#ibcon#read 5, iclass 18, count 0 2006.201.23:31:49.87#ibcon#about to read 6, iclass 18, count 0 2006.201.23:31:49.87#ibcon#read 6, iclass 18, count 0 2006.201.23:31:49.87#ibcon#end of sib2, iclass 18, count 0 2006.201.23:31:49.87#ibcon#*mode == 0, iclass 18, count 0 2006.201.23:31:49.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.23:31:49.87#ibcon#[27=USB\r\n] 2006.201.23:31:49.87#ibcon#*before write, iclass 18, count 0 2006.201.23:31:49.87#ibcon#enter sib2, iclass 18, count 0 2006.201.23:31:49.87#ibcon#flushed, iclass 18, count 0 2006.201.23:31:49.87#ibcon#about to write, iclass 18, count 0 2006.201.23:31:49.87#ibcon#wrote, iclass 18, count 0 2006.201.23:31:49.87#ibcon#about to read 3, iclass 18, count 0 2006.201.23:31:49.90#ibcon#read 3, iclass 18, count 0 2006.201.23:31:49.90#ibcon#about to read 4, iclass 18, count 0 2006.201.23:31:49.90#ibcon#read 4, iclass 18, count 0 2006.201.23:31:49.90#ibcon#about to read 5, iclass 18, count 0 2006.201.23:31:49.90#ibcon#read 5, iclass 18, count 0 2006.201.23:31:49.90#ibcon#about to read 6, iclass 18, count 0 2006.201.23:31:49.90#ibcon#read 6, iclass 18, count 0 2006.201.23:31:49.90#ibcon#end of sib2, iclass 18, count 0 2006.201.23:31:49.90#ibcon#*after write, iclass 18, count 0 2006.201.23:31:49.90#ibcon#*before return 0, iclass 18, count 0 2006.201.23:31:49.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:49.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:31:49.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.23:31:49.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.23:31:49.90$vck44/vblo=3,649.99 2006.201.23:31:49.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.23:31:49.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.23:31:49.90#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:49.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:49.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:49.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:49.90#ibcon#enter wrdev, iclass 20, count 0 2006.201.23:31:49.90#ibcon#first serial, iclass 20, count 0 2006.201.23:31:49.90#ibcon#enter sib2, iclass 20, count 0 2006.201.23:31:49.90#ibcon#flushed, iclass 20, count 0 2006.201.23:31:49.90#ibcon#about to write, iclass 20, count 0 2006.201.23:31:49.90#ibcon#wrote, iclass 20, count 0 2006.201.23:31:49.90#ibcon#about to read 3, iclass 20, count 0 2006.201.23:31:49.92#ibcon#read 3, iclass 20, count 0 2006.201.23:31:49.92#ibcon#about to read 4, iclass 20, count 0 2006.201.23:31:49.92#ibcon#read 4, iclass 20, count 0 2006.201.23:31:49.92#ibcon#about to read 5, iclass 20, count 0 2006.201.23:31:49.92#ibcon#read 5, iclass 20, count 0 2006.201.23:31:49.92#ibcon#about to read 6, iclass 20, count 0 2006.201.23:31:49.92#ibcon#read 6, iclass 20, count 0 2006.201.23:31:49.92#ibcon#end of sib2, iclass 20, count 0 2006.201.23:31:49.92#ibcon#*mode == 0, iclass 20, count 0 2006.201.23:31:49.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.23:31:49.92#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.23:31:49.92#ibcon#*before write, iclass 20, count 0 2006.201.23:31:49.92#ibcon#enter sib2, iclass 20, count 0 2006.201.23:31:49.92#ibcon#flushed, iclass 20, count 0 2006.201.23:31:49.92#ibcon#about to write, iclass 20, count 0 2006.201.23:31:49.92#ibcon#wrote, iclass 20, count 0 2006.201.23:31:49.92#ibcon#about to read 3, iclass 20, count 0 2006.201.23:31:49.96#ibcon#read 3, iclass 20, count 0 2006.201.23:31:49.96#ibcon#about to read 4, iclass 20, count 0 2006.201.23:31:49.96#ibcon#read 4, iclass 20, count 0 2006.201.23:31:49.96#ibcon#about to read 5, iclass 20, count 0 2006.201.23:31:49.96#ibcon#read 5, iclass 20, count 0 2006.201.23:31:49.96#ibcon#about to read 6, iclass 20, count 0 2006.201.23:31:49.96#ibcon#read 6, iclass 20, count 0 2006.201.23:31:49.96#ibcon#end of sib2, iclass 20, count 0 2006.201.23:31:49.96#ibcon#*after write, iclass 20, count 0 2006.201.23:31:49.96#ibcon#*before return 0, iclass 20, count 0 2006.201.23:31:49.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:49.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:31:49.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.23:31:49.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.23:31:49.96$vck44/vb=3,4 2006.201.23:31:49.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.23:31:49.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.23:31:49.96#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:49.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:50.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:50.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:50.02#ibcon#enter wrdev, iclass 22, count 2 2006.201.23:31:50.02#ibcon#first serial, iclass 22, count 2 2006.201.23:31:50.02#ibcon#enter sib2, iclass 22, count 2 2006.201.23:31:50.02#ibcon#flushed, iclass 22, count 2 2006.201.23:31:50.02#ibcon#about to write, iclass 22, count 2 2006.201.23:31:50.02#ibcon#wrote, iclass 22, count 2 2006.201.23:31:50.02#ibcon#about to read 3, iclass 22, count 2 2006.201.23:31:50.04#ibcon#read 3, iclass 22, count 2 2006.201.23:31:50.04#ibcon#about to read 4, iclass 22, count 2 2006.201.23:31:50.04#ibcon#read 4, iclass 22, count 2 2006.201.23:31:50.04#ibcon#about to read 5, iclass 22, count 2 2006.201.23:31:50.04#ibcon#read 5, iclass 22, count 2 2006.201.23:31:50.04#ibcon#about to read 6, iclass 22, count 2 2006.201.23:31:50.04#ibcon#read 6, iclass 22, count 2 2006.201.23:31:50.04#ibcon#end of sib2, iclass 22, count 2 2006.201.23:31:50.04#ibcon#*mode == 0, iclass 22, count 2 2006.201.23:31:50.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.23:31:50.04#ibcon#[27=AT03-04\r\n] 2006.201.23:31:50.04#ibcon#*before write, iclass 22, count 2 2006.201.23:31:50.04#ibcon#enter sib2, iclass 22, count 2 2006.201.23:31:50.04#ibcon#flushed, iclass 22, count 2 2006.201.23:31:50.04#ibcon#about to write, iclass 22, count 2 2006.201.23:31:50.04#ibcon#wrote, iclass 22, count 2 2006.201.23:31:50.04#ibcon#about to read 3, iclass 22, count 2 2006.201.23:31:50.07#ibcon#read 3, iclass 22, count 2 2006.201.23:31:50.07#ibcon#about to read 4, iclass 22, count 2 2006.201.23:31:50.07#ibcon#read 4, iclass 22, count 2 2006.201.23:31:50.07#ibcon#about to read 5, iclass 22, count 2 2006.201.23:31:50.07#ibcon#read 5, iclass 22, count 2 2006.201.23:31:50.07#ibcon#about to read 6, iclass 22, count 2 2006.201.23:31:50.07#ibcon#read 6, iclass 22, count 2 2006.201.23:31:50.07#ibcon#end of sib2, iclass 22, count 2 2006.201.23:31:50.07#ibcon#*after write, iclass 22, count 2 2006.201.23:31:50.07#ibcon#*before return 0, iclass 22, count 2 2006.201.23:31:50.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:50.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:31:50.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.23:31:50.07#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:50.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:50.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:50.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:50.19#ibcon#enter wrdev, iclass 22, count 0 2006.201.23:31:50.19#ibcon#first serial, iclass 22, count 0 2006.201.23:31:50.19#ibcon#enter sib2, iclass 22, count 0 2006.201.23:31:50.19#ibcon#flushed, iclass 22, count 0 2006.201.23:31:50.19#ibcon#about to write, iclass 22, count 0 2006.201.23:31:50.19#ibcon#wrote, iclass 22, count 0 2006.201.23:31:50.19#ibcon#about to read 3, iclass 22, count 0 2006.201.23:31:50.21#ibcon#read 3, iclass 22, count 0 2006.201.23:31:50.21#ibcon#about to read 4, iclass 22, count 0 2006.201.23:31:50.21#ibcon#read 4, iclass 22, count 0 2006.201.23:31:50.21#ibcon#about to read 5, iclass 22, count 0 2006.201.23:31:50.21#ibcon#read 5, iclass 22, count 0 2006.201.23:31:50.21#ibcon#about to read 6, iclass 22, count 0 2006.201.23:31:50.21#ibcon#read 6, iclass 22, count 0 2006.201.23:31:50.21#ibcon#end of sib2, iclass 22, count 0 2006.201.23:31:50.21#ibcon#*mode == 0, iclass 22, count 0 2006.201.23:31:50.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.23:31:50.21#ibcon#[27=USB\r\n] 2006.201.23:31:50.21#ibcon#*before write, iclass 22, count 0 2006.201.23:31:50.21#ibcon#enter sib2, iclass 22, count 0 2006.201.23:31:50.21#ibcon#flushed, iclass 22, count 0 2006.201.23:31:50.21#ibcon#about to write, iclass 22, count 0 2006.201.23:31:50.21#ibcon#wrote, iclass 22, count 0 2006.201.23:31:50.21#ibcon#about to read 3, iclass 22, count 0 2006.201.23:31:50.24#ibcon#read 3, iclass 22, count 0 2006.201.23:31:50.24#ibcon#about to read 4, iclass 22, count 0 2006.201.23:31:50.24#ibcon#read 4, iclass 22, count 0 2006.201.23:31:50.24#ibcon#about to read 5, iclass 22, count 0 2006.201.23:31:50.24#ibcon#read 5, iclass 22, count 0 2006.201.23:31:50.24#ibcon#about to read 6, iclass 22, count 0 2006.201.23:31:50.24#ibcon#read 6, iclass 22, count 0 2006.201.23:31:50.24#ibcon#end of sib2, iclass 22, count 0 2006.201.23:31:50.24#ibcon#*after write, iclass 22, count 0 2006.201.23:31:50.24#ibcon#*before return 0, iclass 22, count 0 2006.201.23:31:50.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:50.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:31:50.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.23:31:50.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.23:31:50.24$vck44/vblo=4,679.99 2006.201.23:31:50.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.23:31:50.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.23:31:50.24#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:50.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:50.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:50.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:50.24#ibcon#enter wrdev, iclass 24, count 0 2006.201.23:31:50.24#ibcon#first serial, iclass 24, count 0 2006.201.23:31:50.24#ibcon#enter sib2, iclass 24, count 0 2006.201.23:31:50.24#ibcon#flushed, iclass 24, count 0 2006.201.23:31:50.24#ibcon#about to write, iclass 24, count 0 2006.201.23:31:50.24#ibcon#wrote, iclass 24, count 0 2006.201.23:31:50.24#ibcon#about to read 3, iclass 24, count 0 2006.201.23:31:50.26#ibcon#read 3, iclass 24, count 0 2006.201.23:31:50.26#ibcon#about to read 4, iclass 24, count 0 2006.201.23:31:50.26#ibcon#read 4, iclass 24, count 0 2006.201.23:31:50.26#ibcon#about to read 5, iclass 24, count 0 2006.201.23:31:50.26#ibcon#read 5, iclass 24, count 0 2006.201.23:31:50.26#ibcon#about to read 6, iclass 24, count 0 2006.201.23:31:50.26#ibcon#read 6, iclass 24, count 0 2006.201.23:31:50.26#ibcon#end of sib2, iclass 24, count 0 2006.201.23:31:50.26#ibcon#*mode == 0, iclass 24, count 0 2006.201.23:31:50.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.23:31:50.26#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.23:31:50.26#ibcon#*before write, iclass 24, count 0 2006.201.23:31:50.26#ibcon#enter sib2, iclass 24, count 0 2006.201.23:31:50.26#ibcon#flushed, iclass 24, count 0 2006.201.23:31:50.26#ibcon#about to write, iclass 24, count 0 2006.201.23:31:50.26#ibcon#wrote, iclass 24, count 0 2006.201.23:31:50.26#ibcon#about to read 3, iclass 24, count 0 2006.201.23:31:50.30#ibcon#read 3, iclass 24, count 0 2006.201.23:31:50.30#ibcon#about to read 4, iclass 24, count 0 2006.201.23:31:50.30#ibcon#read 4, iclass 24, count 0 2006.201.23:31:50.30#ibcon#about to read 5, iclass 24, count 0 2006.201.23:31:50.30#ibcon#read 5, iclass 24, count 0 2006.201.23:31:50.30#ibcon#about to read 6, iclass 24, count 0 2006.201.23:31:50.30#ibcon#read 6, iclass 24, count 0 2006.201.23:31:50.30#ibcon#end of sib2, iclass 24, count 0 2006.201.23:31:50.30#ibcon#*after write, iclass 24, count 0 2006.201.23:31:50.30#ibcon#*before return 0, iclass 24, count 0 2006.201.23:31:50.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:50.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:31:50.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.23:31:50.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.23:31:50.30$vck44/vb=4,5 2006.201.23:31:50.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.23:31:50.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.23:31:50.30#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:50.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:50.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:50.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:50.36#ibcon#enter wrdev, iclass 26, count 2 2006.201.23:31:50.36#ibcon#first serial, iclass 26, count 2 2006.201.23:31:50.36#ibcon#enter sib2, iclass 26, count 2 2006.201.23:31:50.36#ibcon#flushed, iclass 26, count 2 2006.201.23:31:50.36#ibcon#about to write, iclass 26, count 2 2006.201.23:31:50.36#ibcon#wrote, iclass 26, count 2 2006.201.23:31:50.36#ibcon#about to read 3, iclass 26, count 2 2006.201.23:31:50.38#ibcon#read 3, iclass 26, count 2 2006.201.23:31:50.38#ibcon#about to read 4, iclass 26, count 2 2006.201.23:31:50.38#ibcon#read 4, iclass 26, count 2 2006.201.23:31:50.38#ibcon#about to read 5, iclass 26, count 2 2006.201.23:31:50.38#ibcon#read 5, iclass 26, count 2 2006.201.23:31:50.38#ibcon#about to read 6, iclass 26, count 2 2006.201.23:31:50.38#ibcon#read 6, iclass 26, count 2 2006.201.23:31:50.38#ibcon#end of sib2, iclass 26, count 2 2006.201.23:31:50.38#ibcon#*mode == 0, iclass 26, count 2 2006.201.23:31:50.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.23:31:50.38#ibcon#[27=AT04-05\r\n] 2006.201.23:31:50.38#ibcon#*before write, iclass 26, count 2 2006.201.23:31:50.38#ibcon#enter sib2, iclass 26, count 2 2006.201.23:31:50.38#ibcon#flushed, iclass 26, count 2 2006.201.23:31:50.38#ibcon#about to write, iclass 26, count 2 2006.201.23:31:50.38#ibcon#wrote, iclass 26, count 2 2006.201.23:31:50.38#ibcon#about to read 3, iclass 26, count 2 2006.201.23:31:50.41#ibcon#read 3, iclass 26, count 2 2006.201.23:31:50.41#ibcon#about to read 4, iclass 26, count 2 2006.201.23:31:50.41#ibcon#read 4, iclass 26, count 2 2006.201.23:31:50.41#ibcon#about to read 5, iclass 26, count 2 2006.201.23:31:50.41#ibcon#read 5, iclass 26, count 2 2006.201.23:31:50.41#ibcon#about to read 6, iclass 26, count 2 2006.201.23:31:50.41#ibcon#read 6, iclass 26, count 2 2006.201.23:31:50.41#ibcon#end of sib2, iclass 26, count 2 2006.201.23:31:50.41#ibcon#*after write, iclass 26, count 2 2006.201.23:31:50.41#ibcon#*before return 0, iclass 26, count 2 2006.201.23:31:50.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:50.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:31:50.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.23:31:50.41#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:50.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:50.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:50.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:50.53#ibcon#enter wrdev, iclass 26, count 0 2006.201.23:31:50.53#ibcon#first serial, iclass 26, count 0 2006.201.23:31:50.53#ibcon#enter sib2, iclass 26, count 0 2006.201.23:31:50.53#ibcon#flushed, iclass 26, count 0 2006.201.23:31:50.53#ibcon#about to write, iclass 26, count 0 2006.201.23:31:50.53#ibcon#wrote, iclass 26, count 0 2006.201.23:31:50.53#ibcon#about to read 3, iclass 26, count 0 2006.201.23:31:50.55#ibcon#read 3, iclass 26, count 0 2006.201.23:31:50.55#ibcon#about to read 4, iclass 26, count 0 2006.201.23:31:50.55#ibcon#read 4, iclass 26, count 0 2006.201.23:31:50.55#ibcon#about to read 5, iclass 26, count 0 2006.201.23:31:50.55#ibcon#read 5, iclass 26, count 0 2006.201.23:31:50.55#ibcon#about to read 6, iclass 26, count 0 2006.201.23:31:50.55#ibcon#read 6, iclass 26, count 0 2006.201.23:31:50.55#ibcon#end of sib2, iclass 26, count 0 2006.201.23:31:50.55#ibcon#*mode == 0, iclass 26, count 0 2006.201.23:31:50.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.23:31:50.55#ibcon#[27=USB\r\n] 2006.201.23:31:50.55#ibcon#*before write, iclass 26, count 0 2006.201.23:31:50.55#ibcon#enter sib2, iclass 26, count 0 2006.201.23:31:50.55#ibcon#flushed, iclass 26, count 0 2006.201.23:31:50.55#ibcon#about to write, iclass 26, count 0 2006.201.23:31:50.55#ibcon#wrote, iclass 26, count 0 2006.201.23:31:50.55#ibcon#about to read 3, iclass 26, count 0 2006.201.23:31:50.58#ibcon#read 3, iclass 26, count 0 2006.201.23:31:50.58#ibcon#about to read 4, iclass 26, count 0 2006.201.23:31:50.58#ibcon#read 4, iclass 26, count 0 2006.201.23:31:50.58#ibcon#about to read 5, iclass 26, count 0 2006.201.23:31:50.58#ibcon#read 5, iclass 26, count 0 2006.201.23:31:50.58#ibcon#about to read 6, iclass 26, count 0 2006.201.23:31:50.58#ibcon#read 6, iclass 26, count 0 2006.201.23:31:50.58#ibcon#end of sib2, iclass 26, count 0 2006.201.23:31:50.58#ibcon#*after write, iclass 26, count 0 2006.201.23:31:50.58#ibcon#*before return 0, iclass 26, count 0 2006.201.23:31:50.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:50.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:31:50.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.23:31:50.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.23:31:50.58$vck44/vblo=5,709.99 2006.201.23:31:50.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.23:31:50.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.23:31:50.58#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:50.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:50.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:50.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:50.58#ibcon#enter wrdev, iclass 28, count 0 2006.201.23:31:50.58#ibcon#first serial, iclass 28, count 0 2006.201.23:31:50.58#ibcon#enter sib2, iclass 28, count 0 2006.201.23:31:50.58#ibcon#flushed, iclass 28, count 0 2006.201.23:31:50.58#ibcon#about to write, iclass 28, count 0 2006.201.23:31:50.58#ibcon#wrote, iclass 28, count 0 2006.201.23:31:50.58#ibcon#about to read 3, iclass 28, count 0 2006.201.23:31:50.60#ibcon#read 3, iclass 28, count 0 2006.201.23:31:50.60#ibcon#about to read 4, iclass 28, count 0 2006.201.23:31:50.60#ibcon#read 4, iclass 28, count 0 2006.201.23:31:50.60#ibcon#about to read 5, iclass 28, count 0 2006.201.23:31:50.60#ibcon#read 5, iclass 28, count 0 2006.201.23:31:50.60#ibcon#about to read 6, iclass 28, count 0 2006.201.23:31:50.60#ibcon#read 6, iclass 28, count 0 2006.201.23:31:50.60#ibcon#end of sib2, iclass 28, count 0 2006.201.23:31:50.60#ibcon#*mode == 0, iclass 28, count 0 2006.201.23:31:50.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.23:31:50.60#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.23:31:50.60#ibcon#*before write, iclass 28, count 0 2006.201.23:31:50.60#ibcon#enter sib2, iclass 28, count 0 2006.201.23:31:50.60#ibcon#flushed, iclass 28, count 0 2006.201.23:31:50.60#ibcon#about to write, iclass 28, count 0 2006.201.23:31:50.60#ibcon#wrote, iclass 28, count 0 2006.201.23:31:50.60#ibcon#about to read 3, iclass 28, count 0 2006.201.23:31:50.64#ibcon#read 3, iclass 28, count 0 2006.201.23:31:50.64#ibcon#about to read 4, iclass 28, count 0 2006.201.23:31:50.64#ibcon#read 4, iclass 28, count 0 2006.201.23:31:50.64#ibcon#about to read 5, iclass 28, count 0 2006.201.23:31:50.64#ibcon#read 5, iclass 28, count 0 2006.201.23:31:50.64#ibcon#about to read 6, iclass 28, count 0 2006.201.23:31:50.64#ibcon#read 6, iclass 28, count 0 2006.201.23:31:50.64#ibcon#end of sib2, iclass 28, count 0 2006.201.23:31:50.64#ibcon#*after write, iclass 28, count 0 2006.201.23:31:50.64#ibcon#*before return 0, iclass 28, count 0 2006.201.23:31:50.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:50.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:31:50.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.23:31:50.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.23:31:50.64$vck44/vb=5,4 2006.201.23:31:50.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.23:31:50.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.23:31:50.64#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:50.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:50.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:50.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:50.70#ibcon#enter wrdev, iclass 30, count 2 2006.201.23:31:50.70#ibcon#first serial, iclass 30, count 2 2006.201.23:31:50.70#ibcon#enter sib2, iclass 30, count 2 2006.201.23:31:50.70#ibcon#flushed, iclass 30, count 2 2006.201.23:31:50.70#ibcon#about to write, iclass 30, count 2 2006.201.23:31:50.70#ibcon#wrote, iclass 30, count 2 2006.201.23:31:50.70#ibcon#about to read 3, iclass 30, count 2 2006.201.23:31:50.72#ibcon#read 3, iclass 30, count 2 2006.201.23:31:50.72#ibcon#about to read 4, iclass 30, count 2 2006.201.23:31:50.72#ibcon#read 4, iclass 30, count 2 2006.201.23:31:50.72#ibcon#about to read 5, iclass 30, count 2 2006.201.23:31:50.72#ibcon#read 5, iclass 30, count 2 2006.201.23:31:50.72#ibcon#about to read 6, iclass 30, count 2 2006.201.23:31:50.72#ibcon#read 6, iclass 30, count 2 2006.201.23:31:50.72#ibcon#end of sib2, iclass 30, count 2 2006.201.23:31:50.72#ibcon#*mode == 0, iclass 30, count 2 2006.201.23:31:50.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.23:31:50.72#ibcon#[27=AT05-04\r\n] 2006.201.23:31:50.72#ibcon#*before write, iclass 30, count 2 2006.201.23:31:50.72#ibcon#enter sib2, iclass 30, count 2 2006.201.23:31:50.72#ibcon#flushed, iclass 30, count 2 2006.201.23:31:50.72#ibcon#about to write, iclass 30, count 2 2006.201.23:31:50.72#ibcon#wrote, iclass 30, count 2 2006.201.23:31:50.72#ibcon#about to read 3, iclass 30, count 2 2006.201.23:31:50.75#ibcon#read 3, iclass 30, count 2 2006.201.23:31:50.75#ibcon#about to read 4, iclass 30, count 2 2006.201.23:31:50.75#ibcon#read 4, iclass 30, count 2 2006.201.23:31:50.75#ibcon#about to read 5, iclass 30, count 2 2006.201.23:31:50.75#ibcon#read 5, iclass 30, count 2 2006.201.23:31:50.75#ibcon#about to read 6, iclass 30, count 2 2006.201.23:31:50.75#ibcon#read 6, iclass 30, count 2 2006.201.23:31:50.75#ibcon#end of sib2, iclass 30, count 2 2006.201.23:31:50.75#ibcon#*after write, iclass 30, count 2 2006.201.23:31:50.75#ibcon#*before return 0, iclass 30, count 2 2006.201.23:31:50.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:50.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:31:50.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.23:31:50.75#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:50.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:50.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:50.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:50.87#ibcon#enter wrdev, iclass 30, count 0 2006.201.23:31:50.87#ibcon#first serial, iclass 30, count 0 2006.201.23:31:50.87#ibcon#enter sib2, iclass 30, count 0 2006.201.23:31:50.87#ibcon#flushed, iclass 30, count 0 2006.201.23:31:50.87#ibcon#about to write, iclass 30, count 0 2006.201.23:31:50.87#ibcon#wrote, iclass 30, count 0 2006.201.23:31:50.87#ibcon#about to read 3, iclass 30, count 0 2006.201.23:31:50.89#ibcon#read 3, iclass 30, count 0 2006.201.23:31:50.89#ibcon#about to read 4, iclass 30, count 0 2006.201.23:31:50.89#ibcon#read 4, iclass 30, count 0 2006.201.23:31:50.89#ibcon#about to read 5, iclass 30, count 0 2006.201.23:31:50.89#ibcon#read 5, iclass 30, count 0 2006.201.23:31:50.89#ibcon#about to read 6, iclass 30, count 0 2006.201.23:31:50.89#ibcon#read 6, iclass 30, count 0 2006.201.23:31:50.89#ibcon#end of sib2, iclass 30, count 0 2006.201.23:31:50.89#ibcon#*mode == 0, iclass 30, count 0 2006.201.23:31:50.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.23:31:50.89#ibcon#[27=USB\r\n] 2006.201.23:31:50.89#ibcon#*before write, iclass 30, count 0 2006.201.23:31:50.89#ibcon#enter sib2, iclass 30, count 0 2006.201.23:31:50.89#ibcon#flushed, iclass 30, count 0 2006.201.23:31:50.89#ibcon#about to write, iclass 30, count 0 2006.201.23:31:50.89#ibcon#wrote, iclass 30, count 0 2006.201.23:31:50.89#ibcon#about to read 3, iclass 30, count 0 2006.201.23:31:50.92#ibcon#read 3, iclass 30, count 0 2006.201.23:31:50.92#ibcon#about to read 4, iclass 30, count 0 2006.201.23:31:50.92#ibcon#read 4, iclass 30, count 0 2006.201.23:31:50.92#ibcon#about to read 5, iclass 30, count 0 2006.201.23:31:50.92#ibcon#read 5, iclass 30, count 0 2006.201.23:31:50.92#ibcon#about to read 6, iclass 30, count 0 2006.201.23:31:50.92#ibcon#read 6, iclass 30, count 0 2006.201.23:31:50.92#ibcon#end of sib2, iclass 30, count 0 2006.201.23:31:50.92#ibcon#*after write, iclass 30, count 0 2006.201.23:31:50.92#ibcon#*before return 0, iclass 30, count 0 2006.201.23:31:50.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:50.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:31:50.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.23:31:50.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.23:31:50.92$vck44/vblo=6,719.99 2006.201.23:31:50.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.23:31:50.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.23:31:50.92#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:50.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:50.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:50.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:50.92#ibcon#enter wrdev, iclass 32, count 0 2006.201.23:31:50.92#ibcon#first serial, iclass 32, count 0 2006.201.23:31:50.92#ibcon#enter sib2, iclass 32, count 0 2006.201.23:31:50.92#ibcon#flushed, iclass 32, count 0 2006.201.23:31:50.92#ibcon#about to write, iclass 32, count 0 2006.201.23:31:50.92#ibcon#wrote, iclass 32, count 0 2006.201.23:31:50.92#ibcon#about to read 3, iclass 32, count 0 2006.201.23:31:50.94#ibcon#read 3, iclass 32, count 0 2006.201.23:31:50.94#ibcon#about to read 4, iclass 32, count 0 2006.201.23:31:50.94#ibcon#read 4, iclass 32, count 0 2006.201.23:31:50.94#ibcon#about to read 5, iclass 32, count 0 2006.201.23:31:50.94#ibcon#read 5, iclass 32, count 0 2006.201.23:31:50.94#ibcon#about to read 6, iclass 32, count 0 2006.201.23:31:50.94#ibcon#read 6, iclass 32, count 0 2006.201.23:31:50.94#ibcon#end of sib2, iclass 32, count 0 2006.201.23:31:50.94#ibcon#*mode == 0, iclass 32, count 0 2006.201.23:31:50.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.23:31:50.94#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.23:31:50.94#ibcon#*before write, iclass 32, count 0 2006.201.23:31:50.94#ibcon#enter sib2, iclass 32, count 0 2006.201.23:31:50.94#ibcon#flushed, iclass 32, count 0 2006.201.23:31:50.94#ibcon#about to write, iclass 32, count 0 2006.201.23:31:50.94#ibcon#wrote, iclass 32, count 0 2006.201.23:31:50.94#ibcon#about to read 3, iclass 32, count 0 2006.201.23:31:50.98#ibcon#read 3, iclass 32, count 0 2006.201.23:31:50.98#ibcon#about to read 4, iclass 32, count 0 2006.201.23:31:50.98#ibcon#read 4, iclass 32, count 0 2006.201.23:31:50.98#ibcon#about to read 5, iclass 32, count 0 2006.201.23:31:50.98#ibcon#read 5, iclass 32, count 0 2006.201.23:31:50.98#ibcon#about to read 6, iclass 32, count 0 2006.201.23:31:50.98#ibcon#read 6, iclass 32, count 0 2006.201.23:31:50.98#ibcon#end of sib2, iclass 32, count 0 2006.201.23:31:50.98#ibcon#*after write, iclass 32, count 0 2006.201.23:31:50.98#ibcon#*before return 0, iclass 32, count 0 2006.201.23:31:50.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:50.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:31:50.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.23:31:50.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.23:31:50.98$vck44/vb=6,4 2006.201.23:31:50.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.23:31:50.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.23:31:50.98#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:50.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:51.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:51.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:51.04#ibcon#enter wrdev, iclass 34, count 2 2006.201.23:31:51.04#ibcon#first serial, iclass 34, count 2 2006.201.23:31:51.04#ibcon#enter sib2, iclass 34, count 2 2006.201.23:31:51.04#ibcon#flushed, iclass 34, count 2 2006.201.23:31:51.04#ibcon#about to write, iclass 34, count 2 2006.201.23:31:51.04#ibcon#wrote, iclass 34, count 2 2006.201.23:31:51.04#ibcon#about to read 3, iclass 34, count 2 2006.201.23:31:51.06#ibcon#read 3, iclass 34, count 2 2006.201.23:31:51.06#ibcon#about to read 4, iclass 34, count 2 2006.201.23:31:51.06#ibcon#read 4, iclass 34, count 2 2006.201.23:31:51.06#ibcon#about to read 5, iclass 34, count 2 2006.201.23:31:51.06#ibcon#read 5, iclass 34, count 2 2006.201.23:31:51.06#ibcon#about to read 6, iclass 34, count 2 2006.201.23:31:51.06#ibcon#read 6, iclass 34, count 2 2006.201.23:31:51.06#ibcon#end of sib2, iclass 34, count 2 2006.201.23:31:51.06#ibcon#*mode == 0, iclass 34, count 2 2006.201.23:31:51.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.23:31:51.06#ibcon#[27=AT06-04\r\n] 2006.201.23:31:51.06#ibcon#*before write, iclass 34, count 2 2006.201.23:31:51.06#ibcon#enter sib2, iclass 34, count 2 2006.201.23:31:51.06#ibcon#flushed, iclass 34, count 2 2006.201.23:31:51.06#ibcon#about to write, iclass 34, count 2 2006.201.23:31:51.06#ibcon#wrote, iclass 34, count 2 2006.201.23:31:51.06#ibcon#about to read 3, iclass 34, count 2 2006.201.23:31:51.09#ibcon#read 3, iclass 34, count 2 2006.201.23:31:51.09#ibcon#about to read 4, iclass 34, count 2 2006.201.23:31:51.09#ibcon#read 4, iclass 34, count 2 2006.201.23:31:51.09#ibcon#about to read 5, iclass 34, count 2 2006.201.23:31:51.09#ibcon#read 5, iclass 34, count 2 2006.201.23:31:51.09#ibcon#about to read 6, iclass 34, count 2 2006.201.23:31:51.09#ibcon#read 6, iclass 34, count 2 2006.201.23:31:51.09#ibcon#end of sib2, iclass 34, count 2 2006.201.23:31:51.09#ibcon#*after write, iclass 34, count 2 2006.201.23:31:51.09#ibcon#*before return 0, iclass 34, count 2 2006.201.23:31:51.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:51.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:31:51.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.23:31:51.09#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:51.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:51.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:51.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:51.21#ibcon#enter wrdev, iclass 34, count 0 2006.201.23:31:51.21#ibcon#first serial, iclass 34, count 0 2006.201.23:31:51.21#ibcon#enter sib2, iclass 34, count 0 2006.201.23:31:51.21#ibcon#flushed, iclass 34, count 0 2006.201.23:31:51.21#ibcon#about to write, iclass 34, count 0 2006.201.23:31:51.21#ibcon#wrote, iclass 34, count 0 2006.201.23:31:51.21#ibcon#about to read 3, iclass 34, count 0 2006.201.23:31:51.23#ibcon#read 3, iclass 34, count 0 2006.201.23:31:51.23#ibcon#about to read 4, iclass 34, count 0 2006.201.23:31:51.23#ibcon#read 4, iclass 34, count 0 2006.201.23:31:51.23#ibcon#about to read 5, iclass 34, count 0 2006.201.23:31:51.23#ibcon#read 5, iclass 34, count 0 2006.201.23:31:51.23#ibcon#about to read 6, iclass 34, count 0 2006.201.23:31:51.23#ibcon#read 6, iclass 34, count 0 2006.201.23:31:51.23#ibcon#end of sib2, iclass 34, count 0 2006.201.23:31:51.23#ibcon#*mode == 0, iclass 34, count 0 2006.201.23:31:51.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.23:31:51.23#ibcon#[27=USB\r\n] 2006.201.23:31:51.23#ibcon#*before write, iclass 34, count 0 2006.201.23:31:51.23#ibcon#enter sib2, iclass 34, count 0 2006.201.23:31:51.23#ibcon#flushed, iclass 34, count 0 2006.201.23:31:51.23#ibcon#about to write, iclass 34, count 0 2006.201.23:31:51.23#ibcon#wrote, iclass 34, count 0 2006.201.23:31:51.23#ibcon#about to read 3, iclass 34, count 0 2006.201.23:31:51.26#ibcon#read 3, iclass 34, count 0 2006.201.23:31:51.26#ibcon#about to read 4, iclass 34, count 0 2006.201.23:31:51.26#ibcon#read 4, iclass 34, count 0 2006.201.23:31:51.26#ibcon#about to read 5, iclass 34, count 0 2006.201.23:31:51.26#ibcon#read 5, iclass 34, count 0 2006.201.23:31:51.26#ibcon#about to read 6, iclass 34, count 0 2006.201.23:31:51.26#ibcon#read 6, iclass 34, count 0 2006.201.23:31:51.26#ibcon#end of sib2, iclass 34, count 0 2006.201.23:31:51.26#ibcon#*after write, iclass 34, count 0 2006.201.23:31:51.26#ibcon#*before return 0, iclass 34, count 0 2006.201.23:31:51.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:51.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:31:51.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.23:31:51.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.23:31:51.26$vck44/vblo=7,734.99 2006.201.23:31:51.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.23:31:51.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.23:31:51.26#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:51.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:51.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:51.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:51.26#ibcon#enter wrdev, iclass 36, count 0 2006.201.23:31:51.26#ibcon#first serial, iclass 36, count 0 2006.201.23:31:51.26#ibcon#enter sib2, iclass 36, count 0 2006.201.23:31:51.26#ibcon#flushed, iclass 36, count 0 2006.201.23:31:51.26#ibcon#about to write, iclass 36, count 0 2006.201.23:31:51.26#ibcon#wrote, iclass 36, count 0 2006.201.23:31:51.26#ibcon#about to read 3, iclass 36, count 0 2006.201.23:31:51.28#ibcon#read 3, iclass 36, count 0 2006.201.23:31:51.28#ibcon#about to read 4, iclass 36, count 0 2006.201.23:31:51.28#ibcon#read 4, iclass 36, count 0 2006.201.23:31:51.28#ibcon#about to read 5, iclass 36, count 0 2006.201.23:31:51.28#ibcon#read 5, iclass 36, count 0 2006.201.23:31:51.28#ibcon#about to read 6, iclass 36, count 0 2006.201.23:31:51.28#ibcon#read 6, iclass 36, count 0 2006.201.23:31:51.28#ibcon#end of sib2, iclass 36, count 0 2006.201.23:31:51.28#ibcon#*mode == 0, iclass 36, count 0 2006.201.23:31:51.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.23:31:51.28#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.23:31:51.28#ibcon#*before write, iclass 36, count 0 2006.201.23:31:51.28#ibcon#enter sib2, iclass 36, count 0 2006.201.23:31:51.28#ibcon#flushed, iclass 36, count 0 2006.201.23:31:51.28#ibcon#about to write, iclass 36, count 0 2006.201.23:31:51.28#ibcon#wrote, iclass 36, count 0 2006.201.23:31:51.28#ibcon#about to read 3, iclass 36, count 0 2006.201.23:31:51.32#ibcon#read 3, iclass 36, count 0 2006.201.23:31:51.32#ibcon#about to read 4, iclass 36, count 0 2006.201.23:31:51.32#ibcon#read 4, iclass 36, count 0 2006.201.23:31:51.32#ibcon#about to read 5, iclass 36, count 0 2006.201.23:31:51.32#ibcon#read 5, iclass 36, count 0 2006.201.23:31:51.32#ibcon#about to read 6, iclass 36, count 0 2006.201.23:31:51.32#ibcon#read 6, iclass 36, count 0 2006.201.23:31:51.32#ibcon#end of sib2, iclass 36, count 0 2006.201.23:31:51.32#ibcon#*after write, iclass 36, count 0 2006.201.23:31:51.32#ibcon#*before return 0, iclass 36, count 0 2006.201.23:31:51.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:51.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:31:51.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.23:31:51.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.23:31:51.32$vck44/vb=7,4 2006.201.23:31:51.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.23:31:51.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.23:31:51.32#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:51.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:51.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:51.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:51.38#ibcon#enter wrdev, iclass 38, count 2 2006.201.23:31:51.38#ibcon#first serial, iclass 38, count 2 2006.201.23:31:51.38#ibcon#enter sib2, iclass 38, count 2 2006.201.23:31:51.38#ibcon#flushed, iclass 38, count 2 2006.201.23:31:51.38#ibcon#about to write, iclass 38, count 2 2006.201.23:31:51.38#ibcon#wrote, iclass 38, count 2 2006.201.23:31:51.38#ibcon#about to read 3, iclass 38, count 2 2006.201.23:31:51.40#ibcon#read 3, iclass 38, count 2 2006.201.23:31:51.40#ibcon#about to read 4, iclass 38, count 2 2006.201.23:31:51.40#ibcon#read 4, iclass 38, count 2 2006.201.23:31:51.40#ibcon#about to read 5, iclass 38, count 2 2006.201.23:31:51.40#ibcon#read 5, iclass 38, count 2 2006.201.23:31:51.40#ibcon#about to read 6, iclass 38, count 2 2006.201.23:31:51.40#ibcon#read 6, iclass 38, count 2 2006.201.23:31:51.40#ibcon#end of sib2, iclass 38, count 2 2006.201.23:31:51.40#ibcon#*mode == 0, iclass 38, count 2 2006.201.23:31:51.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.23:31:51.40#ibcon#[27=AT07-04\r\n] 2006.201.23:31:51.40#ibcon#*before write, iclass 38, count 2 2006.201.23:31:51.40#ibcon#enter sib2, iclass 38, count 2 2006.201.23:31:51.40#ibcon#flushed, iclass 38, count 2 2006.201.23:31:51.40#ibcon#about to write, iclass 38, count 2 2006.201.23:31:51.40#ibcon#wrote, iclass 38, count 2 2006.201.23:31:51.40#ibcon#about to read 3, iclass 38, count 2 2006.201.23:31:51.43#ibcon#read 3, iclass 38, count 2 2006.201.23:31:51.43#ibcon#about to read 4, iclass 38, count 2 2006.201.23:31:51.43#ibcon#read 4, iclass 38, count 2 2006.201.23:31:51.43#ibcon#about to read 5, iclass 38, count 2 2006.201.23:31:51.43#ibcon#read 5, iclass 38, count 2 2006.201.23:31:51.43#ibcon#about to read 6, iclass 38, count 2 2006.201.23:31:51.43#ibcon#read 6, iclass 38, count 2 2006.201.23:31:51.43#ibcon#end of sib2, iclass 38, count 2 2006.201.23:31:51.43#ibcon#*after write, iclass 38, count 2 2006.201.23:31:51.43#ibcon#*before return 0, iclass 38, count 2 2006.201.23:31:51.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:51.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:31:51.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.23:31:51.43#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:51.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:51.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:51.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:51.55#ibcon#enter wrdev, iclass 38, count 0 2006.201.23:31:51.55#ibcon#first serial, iclass 38, count 0 2006.201.23:31:51.55#ibcon#enter sib2, iclass 38, count 0 2006.201.23:31:51.55#ibcon#flushed, iclass 38, count 0 2006.201.23:31:51.55#ibcon#about to write, iclass 38, count 0 2006.201.23:31:51.55#ibcon#wrote, iclass 38, count 0 2006.201.23:31:51.55#ibcon#about to read 3, iclass 38, count 0 2006.201.23:31:51.57#ibcon#read 3, iclass 38, count 0 2006.201.23:31:51.57#ibcon#about to read 4, iclass 38, count 0 2006.201.23:31:51.57#ibcon#read 4, iclass 38, count 0 2006.201.23:31:51.57#ibcon#about to read 5, iclass 38, count 0 2006.201.23:31:51.57#ibcon#read 5, iclass 38, count 0 2006.201.23:31:51.57#ibcon#about to read 6, iclass 38, count 0 2006.201.23:31:51.57#ibcon#read 6, iclass 38, count 0 2006.201.23:31:51.57#ibcon#end of sib2, iclass 38, count 0 2006.201.23:31:51.57#ibcon#*mode == 0, iclass 38, count 0 2006.201.23:31:51.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.23:31:51.57#ibcon#[27=USB\r\n] 2006.201.23:31:51.57#ibcon#*before write, iclass 38, count 0 2006.201.23:31:51.57#ibcon#enter sib2, iclass 38, count 0 2006.201.23:31:51.57#ibcon#flushed, iclass 38, count 0 2006.201.23:31:51.57#ibcon#about to write, iclass 38, count 0 2006.201.23:31:51.57#ibcon#wrote, iclass 38, count 0 2006.201.23:31:51.57#ibcon#about to read 3, iclass 38, count 0 2006.201.23:31:51.60#ibcon#read 3, iclass 38, count 0 2006.201.23:31:51.60#ibcon#about to read 4, iclass 38, count 0 2006.201.23:31:51.60#ibcon#read 4, iclass 38, count 0 2006.201.23:31:51.60#ibcon#about to read 5, iclass 38, count 0 2006.201.23:31:51.60#ibcon#read 5, iclass 38, count 0 2006.201.23:31:51.60#ibcon#about to read 6, iclass 38, count 0 2006.201.23:31:51.60#ibcon#read 6, iclass 38, count 0 2006.201.23:31:51.60#ibcon#end of sib2, iclass 38, count 0 2006.201.23:31:51.60#ibcon#*after write, iclass 38, count 0 2006.201.23:31:51.60#ibcon#*before return 0, iclass 38, count 0 2006.201.23:31:51.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:51.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:31:51.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.23:31:51.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.23:31:51.60$vck44/vblo=8,744.99 2006.201.23:31:51.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.23:31:51.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.23:31:51.60#ibcon#ireg 17 cls_cnt 0 2006.201.23:31:51.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:51.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:51.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:51.60#ibcon#enter wrdev, iclass 40, count 0 2006.201.23:31:51.60#ibcon#first serial, iclass 40, count 0 2006.201.23:31:51.60#ibcon#enter sib2, iclass 40, count 0 2006.201.23:31:51.60#ibcon#flushed, iclass 40, count 0 2006.201.23:31:51.60#ibcon#about to write, iclass 40, count 0 2006.201.23:31:51.60#ibcon#wrote, iclass 40, count 0 2006.201.23:31:51.60#ibcon#about to read 3, iclass 40, count 0 2006.201.23:31:51.62#ibcon#read 3, iclass 40, count 0 2006.201.23:31:51.62#ibcon#about to read 4, iclass 40, count 0 2006.201.23:31:51.62#ibcon#read 4, iclass 40, count 0 2006.201.23:31:51.62#ibcon#about to read 5, iclass 40, count 0 2006.201.23:31:51.62#ibcon#read 5, iclass 40, count 0 2006.201.23:31:51.62#ibcon#about to read 6, iclass 40, count 0 2006.201.23:31:51.62#ibcon#read 6, iclass 40, count 0 2006.201.23:31:51.62#ibcon#end of sib2, iclass 40, count 0 2006.201.23:31:51.62#ibcon#*mode == 0, iclass 40, count 0 2006.201.23:31:51.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.23:31:51.62#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.23:31:51.62#ibcon#*before write, iclass 40, count 0 2006.201.23:31:51.62#ibcon#enter sib2, iclass 40, count 0 2006.201.23:31:51.62#ibcon#flushed, iclass 40, count 0 2006.201.23:31:51.62#ibcon#about to write, iclass 40, count 0 2006.201.23:31:51.62#ibcon#wrote, iclass 40, count 0 2006.201.23:31:51.62#ibcon#about to read 3, iclass 40, count 0 2006.201.23:31:51.66#ibcon#read 3, iclass 40, count 0 2006.201.23:31:51.66#ibcon#about to read 4, iclass 40, count 0 2006.201.23:31:51.66#ibcon#read 4, iclass 40, count 0 2006.201.23:31:51.66#ibcon#about to read 5, iclass 40, count 0 2006.201.23:31:51.66#ibcon#read 5, iclass 40, count 0 2006.201.23:31:51.66#ibcon#about to read 6, iclass 40, count 0 2006.201.23:31:51.66#ibcon#read 6, iclass 40, count 0 2006.201.23:31:51.66#ibcon#end of sib2, iclass 40, count 0 2006.201.23:31:51.66#ibcon#*after write, iclass 40, count 0 2006.201.23:31:51.66#ibcon#*before return 0, iclass 40, count 0 2006.201.23:31:51.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:51.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:31:51.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.23:31:51.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.23:31:51.66$vck44/vb=8,4 2006.201.23:31:51.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.23:31:51.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.23:31:51.66#ibcon#ireg 11 cls_cnt 2 2006.201.23:31:51.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:51.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:51.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:51.72#ibcon#enter wrdev, iclass 4, count 2 2006.201.23:31:51.72#ibcon#first serial, iclass 4, count 2 2006.201.23:31:51.72#ibcon#enter sib2, iclass 4, count 2 2006.201.23:31:51.72#ibcon#flushed, iclass 4, count 2 2006.201.23:31:51.72#ibcon#about to write, iclass 4, count 2 2006.201.23:31:51.72#ibcon#wrote, iclass 4, count 2 2006.201.23:31:51.72#ibcon#about to read 3, iclass 4, count 2 2006.201.23:31:51.74#ibcon#read 3, iclass 4, count 2 2006.201.23:31:51.74#ibcon#about to read 4, iclass 4, count 2 2006.201.23:31:51.74#ibcon#read 4, iclass 4, count 2 2006.201.23:31:51.74#ibcon#about to read 5, iclass 4, count 2 2006.201.23:31:51.74#ibcon#read 5, iclass 4, count 2 2006.201.23:31:51.74#ibcon#about to read 6, iclass 4, count 2 2006.201.23:31:51.74#ibcon#read 6, iclass 4, count 2 2006.201.23:31:51.74#ibcon#end of sib2, iclass 4, count 2 2006.201.23:31:51.74#ibcon#*mode == 0, iclass 4, count 2 2006.201.23:31:51.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.23:31:51.74#ibcon#[27=AT08-04\r\n] 2006.201.23:31:51.74#ibcon#*before write, iclass 4, count 2 2006.201.23:31:51.74#ibcon#enter sib2, iclass 4, count 2 2006.201.23:31:51.74#ibcon#flushed, iclass 4, count 2 2006.201.23:31:51.74#ibcon#about to write, iclass 4, count 2 2006.201.23:31:51.74#ibcon#wrote, iclass 4, count 2 2006.201.23:31:51.74#ibcon#about to read 3, iclass 4, count 2 2006.201.23:31:51.77#ibcon#read 3, iclass 4, count 2 2006.201.23:31:51.77#ibcon#about to read 4, iclass 4, count 2 2006.201.23:31:51.77#ibcon#read 4, iclass 4, count 2 2006.201.23:31:51.77#ibcon#about to read 5, iclass 4, count 2 2006.201.23:31:51.77#ibcon#read 5, iclass 4, count 2 2006.201.23:31:51.77#ibcon#about to read 6, iclass 4, count 2 2006.201.23:31:51.77#ibcon#read 6, iclass 4, count 2 2006.201.23:31:51.77#ibcon#end of sib2, iclass 4, count 2 2006.201.23:31:51.77#ibcon#*after write, iclass 4, count 2 2006.201.23:31:51.77#ibcon#*before return 0, iclass 4, count 2 2006.201.23:31:51.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:51.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:31:51.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.23:31:51.77#ibcon#ireg 7 cls_cnt 0 2006.201.23:31:51.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:51.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:51.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:51.89#ibcon#enter wrdev, iclass 4, count 0 2006.201.23:31:51.89#ibcon#first serial, iclass 4, count 0 2006.201.23:31:51.89#ibcon#enter sib2, iclass 4, count 0 2006.201.23:31:51.89#ibcon#flushed, iclass 4, count 0 2006.201.23:31:51.89#ibcon#about to write, iclass 4, count 0 2006.201.23:31:51.89#ibcon#wrote, iclass 4, count 0 2006.201.23:31:51.89#ibcon#about to read 3, iclass 4, count 0 2006.201.23:31:51.91#ibcon#read 3, iclass 4, count 0 2006.201.23:31:51.91#ibcon#about to read 4, iclass 4, count 0 2006.201.23:31:51.91#ibcon#read 4, iclass 4, count 0 2006.201.23:31:51.91#ibcon#about to read 5, iclass 4, count 0 2006.201.23:31:51.91#ibcon#read 5, iclass 4, count 0 2006.201.23:31:51.91#ibcon#about to read 6, iclass 4, count 0 2006.201.23:31:51.91#ibcon#read 6, iclass 4, count 0 2006.201.23:31:51.91#ibcon#end of sib2, iclass 4, count 0 2006.201.23:31:51.91#ibcon#*mode == 0, iclass 4, count 0 2006.201.23:31:51.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.23:31:51.91#ibcon#[27=USB\r\n] 2006.201.23:31:51.91#ibcon#*before write, iclass 4, count 0 2006.201.23:31:51.91#ibcon#enter sib2, iclass 4, count 0 2006.201.23:31:51.91#ibcon#flushed, iclass 4, count 0 2006.201.23:31:51.91#ibcon#about to write, iclass 4, count 0 2006.201.23:31:51.91#ibcon#wrote, iclass 4, count 0 2006.201.23:31:51.91#ibcon#about to read 3, iclass 4, count 0 2006.201.23:31:51.94#ibcon#read 3, iclass 4, count 0 2006.201.23:31:51.94#ibcon#about to read 4, iclass 4, count 0 2006.201.23:31:51.94#ibcon#read 4, iclass 4, count 0 2006.201.23:31:51.94#ibcon#about to read 5, iclass 4, count 0 2006.201.23:31:51.94#ibcon#read 5, iclass 4, count 0 2006.201.23:31:51.94#ibcon#about to read 6, iclass 4, count 0 2006.201.23:31:51.94#ibcon#read 6, iclass 4, count 0 2006.201.23:31:51.94#ibcon#end of sib2, iclass 4, count 0 2006.201.23:31:51.94#ibcon#*after write, iclass 4, count 0 2006.201.23:31:51.94#ibcon#*before return 0, iclass 4, count 0 2006.201.23:31:51.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:51.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:31:51.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.23:31:51.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.23:31:51.94$vck44/vabw=wide 2006.201.23:31:51.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.23:31:51.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.23:31:51.94#ibcon#ireg 8 cls_cnt 0 2006.201.23:31:51.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:51.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:51.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:51.94#ibcon#enter wrdev, iclass 6, count 0 2006.201.23:31:51.94#ibcon#first serial, iclass 6, count 0 2006.201.23:31:51.94#ibcon#enter sib2, iclass 6, count 0 2006.201.23:31:51.94#ibcon#flushed, iclass 6, count 0 2006.201.23:31:51.94#ibcon#about to write, iclass 6, count 0 2006.201.23:31:51.94#ibcon#wrote, iclass 6, count 0 2006.201.23:31:51.94#ibcon#about to read 3, iclass 6, count 0 2006.201.23:31:51.96#ibcon#read 3, iclass 6, count 0 2006.201.23:31:51.96#ibcon#about to read 4, iclass 6, count 0 2006.201.23:31:51.96#ibcon#read 4, iclass 6, count 0 2006.201.23:31:51.96#ibcon#about to read 5, iclass 6, count 0 2006.201.23:31:51.96#ibcon#read 5, iclass 6, count 0 2006.201.23:31:51.96#ibcon#about to read 6, iclass 6, count 0 2006.201.23:31:51.96#ibcon#read 6, iclass 6, count 0 2006.201.23:31:51.96#ibcon#end of sib2, iclass 6, count 0 2006.201.23:31:51.96#ibcon#*mode == 0, iclass 6, count 0 2006.201.23:31:51.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.23:31:51.96#ibcon#[25=BW32\r\n] 2006.201.23:31:51.96#ibcon#*before write, iclass 6, count 0 2006.201.23:31:51.96#ibcon#enter sib2, iclass 6, count 0 2006.201.23:31:51.96#ibcon#flushed, iclass 6, count 0 2006.201.23:31:51.96#ibcon#about to write, iclass 6, count 0 2006.201.23:31:51.96#ibcon#wrote, iclass 6, count 0 2006.201.23:31:51.96#ibcon#about to read 3, iclass 6, count 0 2006.201.23:31:51.99#ibcon#read 3, iclass 6, count 0 2006.201.23:31:51.99#ibcon#about to read 4, iclass 6, count 0 2006.201.23:31:51.99#ibcon#read 4, iclass 6, count 0 2006.201.23:31:51.99#ibcon#about to read 5, iclass 6, count 0 2006.201.23:31:51.99#ibcon#read 5, iclass 6, count 0 2006.201.23:31:51.99#ibcon#about to read 6, iclass 6, count 0 2006.201.23:31:51.99#ibcon#read 6, iclass 6, count 0 2006.201.23:31:51.99#ibcon#end of sib2, iclass 6, count 0 2006.201.23:31:51.99#ibcon#*after write, iclass 6, count 0 2006.201.23:31:51.99#ibcon#*before return 0, iclass 6, count 0 2006.201.23:31:51.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:51.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:31:51.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.23:31:51.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.23:31:51.99$vck44/vbbw=wide 2006.201.23:31:51.99#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.23:31:51.99#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.23:31:51.99#ibcon#ireg 8 cls_cnt 0 2006.201.23:31:51.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:31:52.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:31:52.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:31:52.06#ibcon#enter wrdev, iclass 10, count 0 2006.201.23:31:52.06#ibcon#first serial, iclass 10, count 0 2006.201.23:31:52.06#ibcon#enter sib2, iclass 10, count 0 2006.201.23:31:52.06#ibcon#flushed, iclass 10, count 0 2006.201.23:31:52.06#ibcon#about to write, iclass 10, count 0 2006.201.23:31:52.06#ibcon#wrote, iclass 10, count 0 2006.201.23:31:52.06#ibcon#about to read 3, iclass 10, count 0 2006.201.23:31:52.08#ibcon#read 3, iclass 10, count 0 2006.201.23:31:52.08#ibcon#about to read 4, iclass 10, count 0 2006.201.23:31:52.08#ibcon#read 4, iclass 10, count 0 2006.201.23:31:52.08#ibcon#about to read 5, iclass 10, count 0 2006.201.23:31:52.08#ibcon#read 5, iclass 10, count 0 2006.201.23:31:52.08#ibcon#about to read 6, iclass 10, count 0 2006.201.23:31:52.08#ibcon#read 6, iclass 10, count 0 2006.201.23:31:52.08#ibcon#end of sib2, iclass 10, count 0 2006.201.23:31:52.08#ibcon#*mode == 0, iclass 10, count 0 2006.201.23:31:52.08#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.23:31:52.08#ibcon#[27=BW32\r\n] 2006.201.23:31:52.08#ibcon#*before write, iclass 10, count 0 2006.201.23:31:52.08#ibcon#enter sib2, iclass 10, count 0 2006.201.23:31:52.08#ibcon#flushed, iclass 10, count 0 2006.201.23:31:52.08#ibcon#about to write, iclass 10, count 0 2006.201.23:31:52.08#ibcon#wrote, iclass 10, count 0 2006.201.23:31:52.08#ibcon#about to read 3, iclass 10, count 0 2006.201.23:31:52.11#ibcon#read 3, iclass 10, count 0 2006.201.23:31:52.11#ibcon#about to read 4, iclass 10, count 0 2006.201.23:31:52.11#ibcon#read 4, iclass 10, count 0 2006.201.23:31:52.11#ibcon#about to read 5, iclass 10, count 0 2006.201.23:31:52.11#ibcon#read 5, iclass 10, count 0 2006.201.23:31:52.11#ibcon#about to read 6, iclass 10, count 0 2006.201.23:31:52.11#ibcon#read 6, iclass 10, count 0 2006.201.23:31:52.11#ibcon#end of sib2, iclass 10, count 0 2006.201.23:31:52.11#ibcon#*after write, iclass 10, count 0 2006.201.23:31:52.11#ibcon#*before return 0, iclass 10, count 0 2006.201.23:31:52.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:31:52.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:31:52.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.23:31:52.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.23:31:52.11$setupk4/ifdk4 2006.201.23:31:52.11$ifdk4/lo= 2006.201.23:31:52.11$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.23:31:52.11$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.23:31:52.11$ifdk4/patch= 2006.201.23:31:52.11$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.23:31:52.11$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.23:31:52.11$setupk4/!*+20s 2006.201.23:31:53.89#abcon#<5=/04 0.6 1.4 20.321001001.5\r\n> 2006.201.23:31:53.91#abcon#{5=INTERFACE CLEAR} 2006.201.23:31:53.97#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:32:04.06#abcon#<5=/04 0.6 1.4 20.321001001.5\r\n> 2006.201.23:32:04.08#abcon#{5=INTERFACE CLEAR} 2006.201.23:32:04.13#trakl#Source acquired 2006.201.23:32:04.14#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:32:06.13#flagr#flagr/antenna,acquired 2006.201.23:32:06.61$setupk4/"tpicd 2006.201.23:32:06.61$setupk4/echo=off 2006.201.23:32:06.61$setupk4/xlog=off 2006.201.23:32:06.61:!2006.201.23:32:31 2006.201.23:32:31.00:preob 2006.201.23:32:31.13/onsource/TRACKING 2006.201.23:32:31.13:!2006.201.23:32:41 2006.201.23:32:41.00:"tape 2006.201.23:32:41.00:"st=record 2006.201.23:32:41.00:data_valid=on 2006.201.23:32:41.00:midob 2006.201.23:32:42.13/onsource/TRACKING 2006.201.23:32:42.13/wx/20.32,1001.5,100 2006.201.23:32:42.31/cable/+6.4834E-03 2006.201.23:32:43.40/va/01,08,usb,yes,38,41 2006.201.23:32:43.40/va/02,07,usb,yes,41,42 2006.201.23:32:43.40/va/03,08,usb,yes,37,39 2006.201.23:32:43.40/va/04,07,usb,yes,42,45 2006.201.23:32:43.40/va/05,04,usb,yes,38,38 2006.201.23:32:43.40/va/06,05,usb,yes,38,38 2006.201.23:32:43.40/va/07,05,usb,yes,37,38 2006.201.23:32:43.40/va/08,04,usb,yes,37,44 2006.201.23:32:43.63/valo/01,524.99,yes,locked 2006.201.23:32:43.63/valo/02,534.99,yes,locked 2006.201.23:32:43.63/valo/03,564.99,yes,locked 2006.201.23:32:43.63/valo/04,624.99,yes,locked 2006.201.23:32:43.63/valo/05,734.99,yes,locked 2006.201.23:32:43.63/valo/06,814.99,yes,locked 2006.201.23:32:43.63/valo/07,864.99,yes,locked 2006.201.23:32:43.63/valo/08,884.99,yes,locked 2006.201.23:32:44.72/vb/01,04,usb,yes,29,27 2006.201.23:32:44.72/vb/02,05,usb,yes,28,28 2006.201.23:32:44.72/vb/03,04,usb,yes,29,32 2006.201.23:32:44.72/vb/04,05,usb,yes,29,28 2006.201.23:32:44.72/vb/05,04,usb,yes,26,28 2006.201.23:32:44.72/vb/06,04,usb,yes,30,26 2006.201.23:32:44.72/vb/07,04,usb,yes,30,30 2006.201.23:32:44.72/vb/08,04,usb,yes,27,31 2006.201.23:32:44.95/vblo/01,629.99,yes,locked 2006.201.23:32:44.95/vblo/02,634.99,yes,locked 2006.201.23:32:44.95/vblo/03,649.99,yes,locked 2006.201.23:32:44.95/vblo/04,679.99,yes,locked 2006.201.23:32:44.95/vblo/05,709.99,yes,locked 2006.201.23:32:44.95/vblo/06,719.99,yes,locked 2006.201.23:32:44.95/vblo/07,734.99,yes,locked 2006.201.23:32:44.95/vblo/08,744.99,yes,locked 2006.201.23:32:45.10/vabw/8 2006.201.23:32:45.25/vbbw/8 2006.201.23:32:45.34/xfe/off,on,14.2 2006.201.23:32:45.71/ifatt/23,28,28,28 2006.201.23:32:46.07/fmout-gps/S +4.52E-07 2006.201.23:32:46.11:!2006.201.23:36:21 2006.201.23:36:21.00:data_valid=off 2006.201.23:36:21.00:"et 2006.201.23:36:21.00:!+3s 2006.201.23:36:24.01:"tape 2006.201.23:36:24.01:postob 2006.201.23:36:24.18/cable/+6.4825E-03 2006.201.23:36:24.18/wx/20.28,1001.5,100 2006.201.23:36:25.08/fmout-gps/S +4.55E-07 2006.201.23:36:25.08:scan_name=201-2340,jd0607,90 2006.201.23:36:25.08:source=0528+134,053056.42,133155.1,2000.0,cw 2006.201.23:36:26.14#flagr#flagr/antenna,new-source 2006.201.23:36:26.14:checkk5 2006.201.23:36:26.49/chk_autoobs//k5ts1/ autoobs is running! 2006.201.23:36:26.84/chk_autoobs//k5ts2/ autoobs is running! 2006.201.23:36:27.18/chk_autoobs//k5ts3/ autoobs is running! 2006.201.23:36:27.53/chk_autoobs//k5ts4/ autoobs is running! 2006.201.23:36:27.87/chk_obsdata//k5ts1/T2012332??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.23:36:28.21/chk_obsdata//k5ts2/T2012332??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.23:36:28.55/chk_obsdata//k5ts3/T2012332??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.23:36:28.90/chk_obsdata//k5ts4/T2012332??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.201.23:36:29.56/k5log//k5ts1_log_newline 2006.201.23:36:30.21/k5log//k5ts2_log_newline 2006.201.23:36:30.87/k5log//k5ts3_log_newline 2006.201.23:36:31.53/k5log//k5ts4_log_newline 2006.201.23:36:31.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.23:36:31.55:setupk4=1 2006.201.23:36:31.56$setupk4/echo=on 2006.201.23:36:31.56$setupk4/pcalon 2006.201.23:36:31.56$pcalon/"no phase cal control is implemented here 2006.201.23:36:31.56$setupk4/"tpicd=stop 2006.201.23:36:31.56$setupk4/"rec=synch_on 2006.201.23:36:31.56$setupk4/"rec_mode=128 2006.201.23:36:31.56$setupk4/!* 2006.201.23:36:31.56$setupk4/recpk4 2006.201.23:36:31.56$recpk4/recpatch= 2006.201.23:36:31.56$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.23:36:31.56$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.23:36:31.56$setupk4/vck44 2006.201.23:36:31.56$vck44/valo=1,524.99 2006.201.23:36:31.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.23:36:31.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.23:36:31.56#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:31.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:31.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:31.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:31.56#ibcon#enter wrdev, iclass 19, count 0 2006.201.23:36:31.56#ibcon#first serial, iclass 19, count 0 2006.201.23:36:31.56#ibcon#enter sib2, iclass 19, count 0 2006.201.23:36:31.56#ibcon#flushed, iclass 19, count 0 2006.201.23:36:31.56#ibcon#about to write, iclass 19, count 0 2006.201.23:36:31.56#ibcon#wrote, iclass 19, count 0 2006.201.23:36:31.56#ibcon#about to read 3, iclass 19, count 0 2006.201.23:36:31.58#ibcon#read 3, iclass 19, count 0 2006.201.23:36:31.58#ibcon#about to read 4, iclass 19, count 0 2006.201.23:36:31.58#ibcon#read 4, iclass 19, count 0 2006.201.23:36:31.58#ibcon#about to read 5, iclass 19, count 0 2006.201.23:36:31.58#ibcon#read 5, iclass 19, count 0 2006.201.23:36:31.58#ibcon#about to read 6, iclass 19, count 0 2006.201.23:36:31.58#ibcon#read 6, iclass 19, count 0 2006.201.23:36:31.58#ibcon#end of sib2, iclass 19, count 0 2006.201.23:36:31.58#ibcon#*mode == 0, iclass 19, count 0 2006.201.23:36:31.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.23:36:31.58#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.23:36:31.58#ibcon#*before write, iclass 19, count 0 2006.201.23:36:31.58#ibcon#enter sib2, iclass 19, count 0 2006.201.23:36:31.58#ibcon#flushed, iclass 19, count 0 2006.201.23:36:31.58#ibcon#about to write, iclass 19, count 0 2006.201.23:36:31.58#ibcon#wrote, iclass 19, count 0 2006.201.23:36:31.58#ibcon#about to read 3, iclass 19, count 0 2006.201.23:36:31.63#ibcon#read 3, iclass 19, count 0 2006.201.23:36:31.63#ibcon#about to read 4, iclass 19, count 0 2006.201.23:36:31.63#ibcon#read 4, iclass 19, count 0 2006.201.23:36:31.63#ibcon#about to read 5, iclass 19, count 0 2006.201.23:36:31.63#ibcon#read 5, iclass 19, count 0 2006.201.23:36:31.63#ibcon#about to read 6, iclass 19, count 0 2006.201.23:36:31.63#ibcon#read 6, iclass 19, count 0 2006.201.23:36:31.63#ibcon#end of sib2, iclass 19, count 0 2006.201.23:36:31.63#ibcon#*after write, iclass 19, count 0 2006.201.23:36:31.63#ibcon#*before return 0, iclass 19, count 0 2006.201.23:36:31.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:31.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:31.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.23:36:31.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.23:36:31.63$vck44/va=1,8 2006.201.23:36:31.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.23:36:31.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.23:36:31.63#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:31.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:31.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:31.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:31.63#ibcon#enter wrdev, iclass 21, count 2 2006.201.23:36:31.63#ibcon#first serial, iclass 21, count 2 2006.201.23:36:31.63#ibcon#enter sib2, iclass 21, count 2 2006.201.23:36:31.63#ibcon#flushed, iclass 21, count 2 2006.201.23:36:31.63#ibcon#about to write, iclass 21, count 2 2006.201.23:36:31.63#ibcon#wrote, iclass 21, count 2 2006.201.23:36:31.63#ibcon#about to read 3, iclass 21, count 2 2006.201.23:36:31.65#ibcon#read 3, iclass 21, count 2 2006.201.23:36:31.65#ibcon#about to read 4, iclass 21, count 2 2006.201.23:36:31.65#ibcon#read 4, iclass 21, count 2 2006.201.23:36:31.65#ibcon#about to read 5, iclass 21, count 2 2006.201.23:36:31.65#ibcon#read 5, iclass 21, count 2 2006.201.23:36:31.65#ibcon#about to read 6, iclass 21, count 2 2006.201.23:36:31.65#ibcon#read 6, iclass 21, count 2 2006.201.23:36:31.65#ibcon#end of sib2, iclass 21, count 2 2006.201.23:36:31.65#ibcon#*mode == 0, iclass 21, count 2 2006.201.23:36:31.65#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.23:36:31.65#ibcon#[25=AT01-08\r\n] 2006.201.23:36:31.65#ibcon#*before write, iclass 21, count 2 2006.201.23:36:31.65#ibcon#enter sib2, iclass 21, count 2 2006.201.23:36:31.65#ibcon#flushed, iclass 21, count 2 2006.201.23:36:31.65#ibcon#about to write, iclass 21, count 2 2006.201.23:36:31.65#ibcon#wrote, iclass 21, count 2 2006.201.23:36:31.65#ibcon#about to read 3, iclass 21, count 2 2006.201.23:36:31.68#ibcon#read 3, iclass 21, count 2 2006.201.23:36:31.68#ibcon#about to read 4, iclass 21, count 2 2006.201.23:36:31.68#ibcon#read 4, iclass 21, count 2 2006.201.23:36:31.68#ibcon#about to read 5, iclass 21, count 2 2006.201.23:36:31.68#ibcon#read 5, iclass 21, count 2 2006.201.23:36:31.68#ibcon#about to read 6, iclass 21, count 2 2006.201.23:36:31.68#ibcon#read 6, iclass 21, count 2 2006.201.23:36:31.68#ibcon#end of sib2, iclass 21, count 2 2006.201.23:36:31.68#ibcon#*after write, iclass 21, count 2 2006.201.23:36:31.68#ibcon#*before return 0, iclass 21, count 2 2006.201.23:36:31.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:31.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:31.68#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.23:36:31.68#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:31.68#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:31.80#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:31.80#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:31.80#ibcon#enter wrdev, iclass 21, count 0 2006.201.23:36:31.80#ibcon#first serial, iclass 21, count 0 2006.201.23:36:31.80#ibcon#enter sib2, iclass 21, count 0 2006.201.23:36:31.80#ibcon#flushed, iclass 21, count 0 2006.201.23:36:31.80#ibcon#about to write, iclass 21, count 0 2006.201.23:36:31.80#ibcon#wrote, iclass 21, count 0 2006.201.23:36:31.80#ibcon#about to read 3, iclass 21, count 0 2006.201.23:36:31.82#ibcon#read 3, iclass 21, count 0 2006.201.23:36:31.82#ibcon#about to read 4, iclass 21, count 0 2006.201.23:36:31.82#ibcon#read 4, iclass 21, count 0 2006.201.23:36:31.82#ibcon#about to read 5, iclass 21, count 0 2006.201.23:36:31.82#ibcon#read 5, iclass 21, count 0 2006.201.23:36:31.82#ibcon#about to read 6, iclass 21, count 0 2006.201.23:36:31.82#ibcon#read 6, iclass 21, count 0 2006.201.23:36:31.82#ibcon#end of sib2, iclass 21, count 0 2006.201.23:36:31.82#ibcon#*mode == 0, iclass 21, count 0 2006.201.23:36:31.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.23:36:31.82#ibcon#[25=USB\r\n] 2006.201.23:36:31.82#ibcon#*before write, iclass 21, count 0 2006.201.23:36:31.82#ibcon#enter sib2, iclass 21, count 0 2006.201.23:36:31.82#ibcon#flushed, iclass 21, count 0 2006.201.23:36:31.82#ibcon#about to write, iclass 21, count 0 2006.201.23:36:31.82#ibcon#wrote, iclass 21, count 0 2006.201.23:36:31.82#ibcon#about to read 3, iclass 21, count 0 2006.201.23:36:31.85#ibcon#read 3, iclass 21, count 0 2006.201.23:36:31.85#ibcon#about to read 4, iclass 21, count 0 2006.201.23:36:31.85#ibcon#read 4, iclass 21, count 0 2006.201.23:36:31.85#ibcon#about to read 5, iclass 21, count 0 2006.201.23:36:31.85#ibcon#read 5, iclass 21, count 0 2006.201.23:36:31.85#ibcon#about to read 6, iclass 21, count 0 2006.201.23:36:31.85#ibcon#read 6, iclass 21, count 0 2006.201.23:36:31.85#ibcon#end of sib2, iclass 21, count 0 2006.201.23:36:31.85#ibcon#*after write, iclass 21, count 0 2006.201.23:36:31.85#ibcon#*before return 0, iclass 21, count 0 2006.201.23:36:31.85#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:31.85#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:31.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.23:36:31.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.23:36:31.85$vck44/valo=2,534.99 2006.201.23:36:31.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.23:36:31.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.23:36:31.85#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:31.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:31.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:31.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:31.85#ibcon#enter wrdev, iclass 23, count 0 2006.201.23:36:31.85#ibcon#first serial, iclass 23, count 0 2006.201.23:36:31.85#ibcon#enter sib2, iclass 23, count 0 2006.201.23:36:31.85#ibcon#flushed, iclass 23, count 0 2006.201.23:36:31.85#ibcon#about to write, iclass 23, count 0 2006.201.23:36:31.85#ibcon#wrote, iclass 23, count 0 2006.201.23:36:31.85#ibcon#about to read 3, iclass 23, count 0 2006.201.23:36:31.87#ibcon#read 3, iclass 23, count 0 2006.201.23:36:31.87#ibcon#about to read 4, iclass 23, count 0 2006.201.23:36:31.87#ibcon#read 4, iclass 23, count 0 2006.201.23:36:31.87#ibcon#about to read 5, iclass 23, count 0 2006.201.23:36:31.87#ibcon#read 5, iclass 23, count 0 2006.201.23:36:31.87#ibcon#about to read 6, iclass 23, count 0 2006.201.23:36:31.87#ibcon#read 6, iclass 23, count 0 2006.201.23:36:31.87#ibcon#end of sib2, iclass 23, count 0 2006.201.23:36:31.87#ibcon#*mode == 0, iclass 23, count 0 2006.201.23:36:31.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.23:36:31.87#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.23:36:31.87#ibcon#*before write, iclass 23, count 0 2006.201.23:36:31.87#ibcon#enter sib2, iclass 23, count 0 2006.201.23:36:31.87#ibcon#flushed, iclass 23, count 0 2006.201.23:36:31.87#ibcon#about to write, iclass 23, count 0 2006.201.23:36:31.87#ibcon#wrote, iclass 23, count 0 2006.201.23:36:31.87#ibcon#about to read 3, iclass 23, count 0 2006.201.23:36:31.91#ibcon#read 3, iclass 23, count 0 2006.201.23:36:31.91#ibcon#about to read 4, iclass 23, count 0 2006.201.23:36:31.91#ibcon#read 4, iclass 23, count 0 2006.201.23:36:31.91#ibcon#about to read 5, iclass 23, count 0 2006.201.23:36:31.91#ibcon#read 5, iclass 23, count 0 2006.201.23:36:31.91#ibcon#about to read 6, iclass 23, count 0 2006.201.23:36:31.91#ibcon#read 6, iclass 23, count 0 2006.201.23:36:31.91#ibcon#end of sib2, iclass 23, count 0 2006.201.23:36:31.91#ibcon#*after write, iclass 23, count 0 2006.201.23:36:31.91#ibcon#*before return 0, iclass 23, count 0 2006.201.23:36:31.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:31.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:31.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.23:36:31.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.23:36:31.91$vck44/va=2,7 2006.201.23:36:31.91#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.23:36:31.91#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.23:36:31.91#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:31.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:31.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:31.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:31.97#ibcon#enter wrdev, iclass 25, count 2 2006.201.23:36:31.97#ibcon#first serial, iclass 25, count 2 2006.201.23:36:31.97#ibcon#enter sib2, iclass 25, count 2 2006.201.23:36:31.97#ibcon#flushed, iclass 25, count 2 2006.201.23:36:31.97#ibcon#about to write, iclass 25, count 2 2006.201.23:36:31.97#ibcon#wrote, iclass 25, count 2 2006.201.23:36:31.97#ibcon#about to read 3, iclass 25, count 2 2006.201.23:36:31.99#ibcon#read 3, iclass 25, count 2 2006.201.23:36:31.99#ibcon#about to read 4, iclass 25, count 2 2006.201.23:36:31.99#ibcon#read 4, iclass 25, count 2 2006.201.23:36:31.99#ibcon#about to read 5, iclass 25, count 2 2006.201.23:36:31.99#ibcon#read 5, iclass 25, count 2 2006.201.23:36:31.99#ibcon#about to read 6, iclass 25, count 2 2006.201.23:36:31.99#ibcon#read 6, iclass 25, count 2 2006.201.23:36:31.99#ibcon#end of sib2, iclass 25, count 2 2006.201.23:36:31.99#ibcon#*mode == 0, iclass 25, count 2 2006.201.23:36:31.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.23:36:31.99#ibcon#[25=AT02-07\r\n] 2006.201.23:36:31.99#ibcon#*before write, iclass 25, count 2 2006.201.23:36:31.99#ibcon#enter sib2, iclass 25, count 2 2006.201.23:36:31.99#ibcon#flushed, iclass 25, count 2 2006.201.23:36:31.99#ibcon#about to write, iclass 25, count 2 2006.201.23:36:31.99#ibcon#wrote, iclass 25, count 2 2006.201.23:36:31.99#ibcon#about to read 3, iclass 25, count 2 2006.201.23:36:32.02#ibcon#read 3, iclass 25, count 2 2006.201.23:36:32.02#ibcon#about to read 4, iclass 25, count 2 2006.201.23:36:32.02#ibcon#read 4, iclass 25, count 2 2006.201.23:36:32.02#ibcon#about to read 5, iclass 25, count 2 2006.201.23:36:32.02#ibcon#read 5, iclass 25, count 2 2006.201.23:36:32.02#ibcon#about to read 6, iclass 25, count 2 2006.201.23:36:32.02#ibcon#read 6, iclass 25, count 2 2006.201.23:36:32.02#ibcon#end of sib2, iclass 25, count 2 2006.201.23:36:32.02#ibcon#*after write, iclass 25, count 2 2006.201.23:36:32.02#ibcon#*before return 0, iclass 25, count 2 2006.201.23:36:32.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:32.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:32.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.23:36:32.02#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:32.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:32.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:32.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:32.14#ibcon#enter wrdev, iclass 25, count 0 2006.201.23:36:32.14#ibcon#first serial, iclass 25, count 0 2006.201.23:36:32.14#ibcon#enter sib2, iclass 25, count 0 2006.201.23:36:32.14#ibcon#flushed, iclass 25, count 0 2006.201.23:36:32.14#ibcon#about to write, iclass 25, count 0 2006.201.23:36:32.14#ibcon#wrote, iclass 25, count 0 2006.201.23:36:32.14#ibcon#about to read 3, iclass 25, count 0 2006.201.23:36:32.16#ibcon#read 3, iclass 25, count 0 2006.201.23:36:32.16#ibcon#about to read 4, iclass 25, count 0 2006.201.23:36:32.16#ibcon#read 4, iclass 25, count 0 2006.201.23:36:32.16#ibcon#about to read 5, iclass 25, count 0 2006.201.23:36:32.16#ibcon#read 5, iclass 25, count 0 2006.201.23:36:32.16#ibcon#about to read 6, iclass 25, count 0 2006.201.23:36:32.16#ibcon#read 6, iclass 25, count 0 2006.201.23:36:32.16#ibcon#end of sib2, iclass 25, count 0 2006.201.23:36:32.16#ibcon#*mode == 0, iclass 25, count 0 2006.201.23:36:32.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.23:36:32.16#ibcon#[25=USB\r\n] 2006.201.23:36:32.16#ibcon#*before write, iclass 25, count 0 2006.201.23:36:32.16#ibcon#enter sib2, iclass 25, count 0 2006.201.23:36:32.16#ibcon#flushed, iclass 25, count 0 2006.201.23:36:32.16#ibcon#about to write, iclass 25, count 0 2006.201.23:36:32.16#ibcon#wrote, iclass 25, count 0 2006.201.23:36:32.16#ibcon#about to read 3, iclass 25, count 0 2006.201.23:36:32.19#ibcon#read 3, iclass 25, count 0 2006.201.23:36:32.19#ibcon#about to read 4, iclass 25, count 0 2006.201.23:36:32.19#ibcon#read 4, iclass 25, count 0 2006.201.23:36:32.19#ibcon#about to read 5, iclass 25, count 0 2006.201.23:36:32.19#ibcon#read 5, iclass 25, count 0 2006.201.23:36:32.19#ibcon#about to read 6, iclass 25, count 0 2006.201.23:36:32.19#ibcon#read 6, iclass 25, count 0 2006.201.23:36:32.19#ibcon#end of sib2, iclass 25, count 0 2006.201.23:36:32.19#ibcon#*after write, iclass 25, count 0 2006.201.23:36:32.19#ibcon#*before return 0, iclass 25, count 0 2006.201.23:36:32.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:32.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:32.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.23:36:32.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.23:36:32.19$vck44/valo=3,564.99 2006.201.23:36:32.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.23:36:32.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.23:36:32.19#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:32.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:32.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:32.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:32.19#ibcon#enter wrdev, iclass 27, count 0 2006.201.23:36:32.19#ibcon#first serial, iclass 27, count 0 2006.201.23:36:32.19#ibcon#enter sib2, iclass 27, count 0 2006.201.23:36:32.19#ibcon#flushed, iclass 27, count 0 2006.201.23:36:32.19#ibcon#about to write, iclass 27, count 0 2006.201.23:36:32.19#ibcon#wrote, iclass 27, count 0 2006.201.23:36:32.19#ibcon#about to read 3, iclass 27, count 0 2006.201.23:36:32.21#ibcon#read 3, iclass 27, count 0 2006.201.23:36:32.21#ibcon#about to read 4, iclass 27, count 0 2006.201.23:36:32.21#ibcon#read 4, iclass 27, count 0 2006.201.23:36:32.21#ibcon#about to read 5, iclass 27, count 0 2006.201.23:36:32.21#ibcon#read 5, iclass 27, count 0 2006.201.23:36:32.21#ibcon#about to read 6, iclass 27, count 0 2006.201.23:36:32.21#ibcon#read 6, iclass 27, count 0 2006.201.23:36:32.21#ibcon#end of sib2, iclass 27, count 0 2006.201.23:36:32.21#ibcon#*mode == 0, iclass 27, count 0 2006.201.23:36:32.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.23:36:32.21#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.23:36:32.21#ibcon#*before write, iclass 27, count 0 2006.201.23:36:32.21#ibcon#enter sib2, iclass 27, count 0 2006.201.23:36:32.21#ibcon#flushed, iclass 27, count 0 2006.201.23:36:32.21#ibcon#about to write, iclass 27, count 0 2006.201.23:36:32.21#ibcon#wrote, iclass 27, count 0 2006.201.23:36:32.21#ibcon#about to read 3, iclass 27, count 0 2006.201.23:36:32.25#ibcon#read 3, iclass 27, count 0 2006.201.23:36:32.25#ibcon#about to read 4, iclass 27, count 0 2006.201.23:36:32.25#ibcon#read 4, iclass 27, count 0 2006.201.23:36:32.25#ibcon#about to read 5, iclass 27, count 0 2006.201.23:36:32.25#ibcon#read 5, iclass 27, count 0 2006.201.23:36:32.25#ibcon#about to read 6, iclass 27, count 0 2006.201.23:36:32.25#ibcon#read 6, iclass 27, count 0 2006.201.23:36:32.25#ibcon#end of sib2, iclass 27, count 0 2006.201.23:36:32.25#ibcon#*after write, iclass 27, count 0 2006.201.23:36:32.25#ibcon#*before return 0, iclass 27, count 0 2006.201.23:36:32.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:32.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:32.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.23:36:32.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.23:36:32.25$vck44/va=3,8 2006.201.23:36:32.25#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.23:36:32.25#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.23:36:32.25#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:32.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:32.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:32.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:32.31#ibcon#enter wrdev, iclass 29, count 2 2006.201.23:36:32.31#ibcon#first serial, iclass 29, count 2 2006.201.23:36:32.31#ibcon#enter sib2, iclass 29, count 2 2006.201.23:36:32.31#ibcon#flushed, iclass 29, count 2 2006.201.23:36:32.31#ibcon#about to write, iclass 29, count 2 2006.201.23:36:32.31#ibcon#wrote, iclass 29, count 2 2006.201.23:36:32.31#ibcon#about to read 3, iclass 29, count 2 2006.201.23:36:32.33#ibcon#read 3, iclass 29, count 2 2006.201.23:36:32.33#ibcon#about to read 4, iclass 29, count 2 2006.201.23:36:32.33#ibcon#read 4, iclass 29, count 2 2006.201.23:36:32.33#ibcon#about to read 5, iclass 29, count 2 2006.201.23:36:32.33#ibcon#read 5, iclass 29, count 2 2006.201.23:36:32.33#ibcon#about to read 6, iclass 29, count 2 2006.201.23:36:32.33#ibcon#read 6, iclass 29, count 2 2006.201.23:36:32.33#ibcon#end of sib2, iclass 29, count 2 2006.201.23:36:32.33#ibcon#*mode == 0, iclass 29, count 2 2006.201.23:36:32.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.23:36:32.33#ibcon#[25=AT03-08\r\n] 2006.201.23:36:32.33#ibcon#*before write, iclass 29, count 2 2006.201.23:36:32.33#ibcon#enter sib2, iclass 29, count 2 2006.201.23:36:32.33#ibcon#flushed, iclass 29, count 2 2006.201.23:36:32.33#ibcon#about to write, iclass 29, count 2 2006.201.23:36:32.33#ibcon#wrote, iclass 29, count 2 2006.201.23:36:32.33#ibcon#about to read 3, iclass 29, count 2 2006.201.23:36:32.36#ibcon#read 3, iclass 29, count 2 2006.201.23:36:32.36#ibcon#about to read 4, iclass 29, count 2 2006.201.23:36:32.36#ibcon#read 4, iclass 29, count 2 2006.201.23:36:32.36#ibcon#about to read 5, iclass 29, count 2 2006.201.23:36:32.36#ibcon#read 5, iclass 29, count 2 2006.201.23:36:32.36#ibcon#about to read 6, iclass 29, count 2 2006.201.23:36:32.36#ibcon#read 6, iclass 29, count 2 2006.201.23:36:32.36#ibcon#end of sib2, iclass 29, count 2 2006.201.23:36:32.36#ibcon#*after write, iclass 29, count 2 2006.201.23:36:32.36#ibcon#*before return 0, iclass 29, count 2 2006.201.23:36:32.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:32.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:32.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.23:36:32.36#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:32.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:32.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:32.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:32.48#ibcon#enter wrdev, iclass 29, count 0 2006.201.23:36:32.48#ibcon#first serial, iclass 29, count 0 2006.201.23:36:32.48#ibcon#enter sib2, iclass 29, count 0 2006.201.23:36:32.48#ibcon#flushed, iclass 29, count 0 2006.201.23:36:32.48#ibcon#about to write, iclass 29, count 0 2006.201.23:36:32.48#ibcon#wrote, iclass 29, count 0 2006.201.23:36:32.48#ibcon#about to read 3, iclass 29, count 0 2006.201.23:36:32.50#ibcon#read 3, iclass 29, count 0 2006.201.23:36:32.50#ibcon#about to read 4, iclass 29, count 0 2006.201.23:36:32.50#ibcon#read 4, iclass 29, count 0 2006.201.23:36:32.50#ibcon#about to read 5, iclass 29, count 0 2006.201.23:36:32.50#ibcon#read 5, iclass 29, count 0 2006.201.23:36:32.50#ibcon#about to read 6, iclass 29, count 0 2006.201.23:36:32.50#ibcon#read 6, iclass 29, count 0 2006.201.23:36:32.50#ibcon#end of sib2, iclass 29, count 0 2006.201.23:36:32.50#ibcon#*mode == 0, iclass 29, count 0 2006.201.23:36:32.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.23:36:32.50#ibcon#[25=USB\r\n] 2006.201.23:36:32.50#ibcon#*before write, iclass 29, count 0 2006.201.23:36:32.50#ibcon#enter sib2, iclass 29, count 0 2006.201.23:36:32.50#ibcon#flushed, iclass 29, count 0 2006.201.23:36:32.50#ibcon#about to write, iclass 29, count 0 2006.201.23:36:32.50#ibcon#wrote, iclass 29, count 0 2006.201.23:36:32.50#ibcon#about to read 3, iclass 29, count 0 2006.201.23:36:32.53#ibcon#read 3, iclass 29, count 0 2006.201.23:36:32.53#ibcon#about to read 4, iclass 29, count 0 2006.201.23:36:32.53#ibcon#read 4, iclass 29, count 0 2006.201.23:36:32.53#ibcon#about to read 5, iclass 29, count 0 2006.201.23:36:32.53#ibcon#read 5, iclass 29, count 0 2006.201.23:36:32.53#ibcon#about to read 6, iclass 29, count 0 2006.201.23:36:32.53#ibcon#read 6, iclass 29, count 0 2006.201.23:36:32.53#ibcon#end of sib2, iclass 29, count 0 2006.201.23:36:32.53#ibcon#*after write, iclass 29, count 0 2006.201.23:36:32.53#ibcon#*before return 0, iclass 29, count 0 2006.201.23:36:32.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:32.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:32.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.23:36:32.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.23:36:32.53$vck44/valo=4,624.99 2006.201.23:36:32.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.23:36:32.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.23:36:32.53#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:32.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:32.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:32.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:32.53#ibcon#enter wrdev, iclass 31, count 0 2006.201.23:36:32.53#ibcon#first serial, iclass 31, count 0 2006.201.23:36:32.53#ibcon#enter sib2, iclass 31, count 0 2006.201.23:36:32.53#ibcon#flushed, iclass 31, count 0 2006.201.23:36:32.53#ibcon#about to write, iclass 31, count 0 2006.201.23:36:32.53#ibcon#wrote, iclass 31, count 0 2006.201.23:36:32.53#ibcon#about to read 3, iclass 31, count 0 2006.201.23:36:32.55#ibcon#read 3, iclass 31, count 0 2006.201.23:36:32.55#ibcon#about to read 4, iclass 31, count 0 2006.201.23:36:32.55#ibcon#read 4, iclass 31, count 0 2006.201.23:36:32.55#ibcon#about to read 5, iclass 31, count 0 2006.201.23:36:32.55#ibcon#read 5, iclass 31, count 0 2006.201.23:36:32.55#ibcon#about to read 6, iclass 31, count 0 2006.201.23:36:32.55#ibcon#read 6, iclass 31, count 0 2006.201.23:36:32.55#ibcon#end of sib2, iclass 31, count 0 2006.201.23:36:32.55#ibcon#*mode == 0, iclass 31, count 0 2006.201.23:36:32.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.23:36:32.55#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.23:36:32.55#ibcon#*before write, iclass 31, count 0 2006.201.23:36:32.55#ibcon#enter sib2, iclass 31, count 0 2006.201.23:36:32.55#ibcon#flushed, iclass 31, count 0 2006.201.23:36:32.55#ibcon#about to write, iclass 31, count 0 2006.201.23:36:32.55#ibcon#wrote, iclass 31, count 0 2006.201.23:36:32.55#ibcon#about to read 3, iclass 31, count 0 2006.201.23:36:32.59#ibcon#read 3, iclass 31, count 0 2006.201.23:36:32.59#ibcon#about to read 4, iclass 31, count 0 2006.201.23:36:32.59#ibcon#read 4, iclass 31, count 0 2006.201.23:36:32.59#ibcon#about to read 5, iclass 31, count 0 2006.201.23:36:32.59#ibcon#read 5, iclass 31, count 0 2006.201.23:36:32.59#ibcon#about to read 6, iclass 31, count 0 2006.201.23:36:32.59#ibcon#read 6, iclass 31, count 0 2006.201.23:36:32.59#ibcon#end of sib2, iclass 31, count 0 2006.201.23:36:32.59#ibcon#*after write, iclass 31, count 0 2006.201.23:36:32.59#ibcon#*before return 0, iclass 31, count 0 2006.201.23:36:32.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:32.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:32.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.23:36:32.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.23:36:32.59$vck44/va=4,7 2006.201.23:36:32.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.23:36:32.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.23:36:32.59#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:32.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:32.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:32.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:32.65#ibcon#enter wrdev, iclass 33, count 2 2006.201.23:36:32.65#ibcon#first serial, iclass 33, count 2 2006.201.23:36:32.65#ibcon#enter sib2, iclass 33, count 2 2006.201.23:36:32.65#ibcon#flushed, iclass 33, count 2 2006.201.23:36:32.65#ibcon#about to write, iclass 33, count 2 2006.201.23:36:32.65#ibcon#wrote, iclass 33, count 2 2006.201.23:36:32.65#ibcon#about to read 3, iclass 33, count 2 2006.201.23:36:32.67#ibcon#read 3, iclass 33, count 2 2006.201.23:36:32.67#ibcon#about to read 4, iclass 33, count 2 2006.201.23:36:32.67#ibcon#read 4, iclass 33, count 2 2006.201.23:36:32.67#ibcon#about to read 5, iclass 33, count 2 2006.201.23:36:32.67#ibcon#read 5, iclass 33, count 2 2006.201.23:36:32.67#ibcon#about to read 6, iclass 33, count 2 2006.201.23:36:32.67#ibcon#read 6, iclass 33, count 2 2006.201.23:36:32.67#ibcon#end of sib2, iclass 33, count 2 2006.201.23:36:32.67#ibcon#*mode == 0, iclass 33, count 2 2006.201.23:36:32.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.23:36:32.67#ibcon#[25=AT04-07\r\n] 2006.201.23:36:32.67#ibcon#*before write, iclass 33, count 2 2006.201.23:36:32.67#ibcon#enter sib2, iclass 33, count 2 2006.201.23:36:32.67#ibcon#flushed, iclass 33, count 2 2006.201.23:36:32.67#ibcon#about to write, iclass 33, count 2 2006.201.23:36:32.67#ibcon#wrote, iclass 33, count 2 2006.201.23:36:32.67#ibcon#about to read 3, iclass 33, count 2 2006.201.23:36:32.70#ibcon#read 3, iclass 33, count 2 2006.201.23:36:32.70#ibcon#about to read 4, iclass 33, count 2 2006.201.23:36:32.70#ibcon#read 4, iclass 33, count 2 2006.201.23:36:32.70#ibcon#about to read 5, iclass 33, count 2 2006.201.23:36:32.70#ibcon#read 5, iclass 33, count 2 2006.201.23:36:32.70#ibcon#about to read 6, iclass 33, count 2 2006.201.23:36:32.70#ibcon#read 6, iclass 33, count 2 2006.201.23:36:32.70#ibcon#end of sib2, iclass 33, count 2 2006.201.23:36:32.70#ibcon#*after write, iclass 33, count 2 2006.201.23:36:32.70#ibcon#*before return 0, iclass 33, count 2 2006.201.23:36:32.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:32.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:32.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.23:36:32.70#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:32.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:32.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:32.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:32.82#ibcon#enter wrdev, iclass 33, count 0 2006.201.23:36:32.82#ibcon#first serial, iclass 33, count 0 2006.201.23:36:32.82#ibcon#enter sib2, iclass 33, count 0 2006.201.23:36:32.82#ibcon#flushed, iclass 33, count 0 2006.201.23:36:32.82#ibcon#about to write, iclass 33, count 0 2006.201.23:36:32.82#ibcon#wrote, iclass 33, count 0 2006.201.23:36:32.82#ibcon#about to read 3, iclass 33, count 0 2006.201.23:36:32.84#ibcon#read 3, iclass 33, count 0 2006.201.23:36:32.84#ibcon#about to read 4, iclass 33, count 0 2006.201.23:36:32.84#ibcon#read 4, iclass 33, count 0 2006.201.23:36:32.84#ibcon#about to read 5, iclass 33, count 0 2006.201.23:36:32.84#ibcon#read 5, iclass 33, count 0 2006.201.23:36:32.84#ibcon#about to read 6, iclass 33, count 0 2006.201.23:36:32.84#ibcon#read 6, iclass 33, count 0 2006.201.23:36:32.84#ibcon#end of sib2, iclass 33, count 0 2006.201.23:36:32.84#ibcon#*mode == 0, iclass 33, count 0 2006.201.23:36:32.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.23:36:32.84#ibcon#[25=USB\r\n] 2006.201.23:36:32.84#ibcon#*before write, iclass 33, count 0 2006.201.23:36:32.84#ibcon#enter sib2, iclass 33, count 0 2006.201.23:36:32.84#ibcon#flushed, iclass 33, count 0 2006.201.23:36:32.84#ibcon#about to write, iclass 33, count 0 2006.201.23:36:32.84#ibcon#wrote, iclass 33, count 0 2006.201.23:36:32.84#ibcon#about to read 3, iclass 33, count 0 2006.201.23:36:32.87#ibcon#read 3, iclass 33, count 0 2006.201.23:36:32.87#ibcon#about to read 4, iclass 33, count 0 2006.201.23:36:32.87#ibcon#read 4, iclass 33, count 0 2006.201.23:36:32.87#ibcon#about to read 5, iclass 33, count 0 2006.201.23:36:32.87#ibcon#read 5, iclass 33, count 0 2006.201.23:36:32.87#ibcon#about to read 6, iclass 33, count 0 2006.201.23:36:32.87#ibcon#read 6, iclass 33, count 0 2006.201.23:36:32.87#ibcon#end of sib2, iclass 33, count 0 2006.201.23:36:32.87#ibcon#*after write, iclass 33, count 0 2006.201.23:36:32.87#ibcon#*before return 0, iclass 33, count 0 2006.201.23:36:32.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:32.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:32.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.23:36:32.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.23:36:32.87$vck44/valo=5,734.99 2006.201.23:36:32.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.23:36:32.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.23:36:32.87#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:32.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:32.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:32.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:32.87#ibcon#enter wrdev, iclass 35, count 0 2006.201.23:36:32.87#ibcon#first serial, iclass 35, count 0 2006.201.23:36:32.87#ibcon#enter sib2, iclass 35, count 0 2006.201.23:36:32.87#ibcon#flushed, iclass 35, count 0 2006.201.23:36:32.87#ibcon#about to write, iclass 35, count 0 2006.201.23:36:32.87#ibcon#wrote, iclass 35, count 0 2006.201.23:36:32.87#ibcon#about to read 3, iclass 35, count 0 2006.201.23:36:32.89#ibcon#read 3, iclass 35, count 0 2006.201.23:36:32.89#ibcon#about to read 4, iclass 35, count 0 2006.201.23:36:32.89#ibcon#read 4, iclass 35, count 0 2006.201.23:36:32.89#ibcon#about to read 5, iclass 35, count 0 2006.201.23:36:32.89#ibcon#read 5, iclass 35, count 0 2006.201.23:36:32.89#ibcon#about to read 6, iclass 35, count 0 2006.201.23:36:32.89#ibcon#read 6, iclass 35, count 0 2006.201.23:36:32.89#ibcon#end of sib2, iclass 35, count 0 2006.201.23:36:32.89#ibcon#*mode == 0, iclass 35, count 0 2006.201.23:36:32.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.23:36:32.89#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.23:36:32.89#ibcon#*before write, iclass 35, count 0 2006.201.23:36:32.89#ibcon#enter sib2, iclass 35, count 0 2006.201.23:36:32.89#ibcon#flushed, iclass 35, count 0 2006.201.23:36:32.89#ibcon#about to write, iclass 35, count 0 2006.201.23:36:32.89#ibcon#wrote, iclass 35, count 0 2006.201.23:36:32.89#ibcon#about to read 3, iclass 35, count 0 2006.201.23:36:32.93#ibcon#read 3, iclass 35, count 0 2006.201.23:36:32.93#ibcon#about to read 4, iclass 35, count 0 2006.201.23:36:32.93#ibcon#read 4, iclass 35, count 0 2006.201.23:36:32.93#ibcon#about to read 5, iclass 35, count 0 2006.201.23:36:32.93#ibcon#read 5, iclass 35, count 0 2006.201.23:36:32.93#ibcon#about to read 6, iclass 35, count 0 2006.201.23:36:32.93#ibcon#read 6, iclass 35, count 0 2006.201.23:36:32.93#ibcon#end of sib2, iclass 35, count 0 2006.201.23:36:32.93#ibcon#*after write, iclass 35, count 0 2006.201.23:36:32.93#ibcon#*before return 0, iclass 35, count 0 2006.201.23:36:32.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:32.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:32.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.23:36:32.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.23:36:32.93$vck44/va=5,4 2006.201.23:36:32.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.23:36:32.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.23:36:32.93#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:32.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:32.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:32.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:32.99#ibcon#enter wrdev, iclass 37, count 2 2006.201.23:36:32.99#ibcon#first serial, iclass 37, count 2 2006.201.23:36:32.99#ibcon#enter sib2, iclass 37, count 2 2006.201.23:36:32.99#ibcon#flushed, iclass 37, count 2 2006.201.23:36:32.99#ibcon#about to write, iclass 37, count 2 2006.201.23:36:32.99#ibcon#wrote, iclass 37, count 2 2006.201.23:36:32.99#ibcon#about to read 3, iclass 37, count 2 2006.201.23:36:33.01#ibcon#read 3, iclass 37, count 2 2006.201.23:36:33.01#ibcon#about to read 4, iclass 37, count 2 2006.201.23:36:33.01#ibcon#read 4, iclass 37, count 2 2006.201.23:36:33.01#ibcon#about to read 5, iclass 37, count 2 2006.201.23:36:33.01#ibcon#read 5, iclass 37, count 2 2006.201.23:36:33.01#ibcon#about to read 6, iclass 37, count 2 2006.201.23:36:33.01#ibcon#read 6, iclass 37, count 2 2006.201.23:36:33.01#ibcon#end of sib2, iclass 37, count 2 2006.201.23:36:33.01#ibcon#*mode == 0, iclass 37, count 2 2006.201.23:36:33.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.23:36:33.01#ibcon#[25=AT05-04\r\n] 2006.201.23:36:33.01#ibcon#*before write, iclass 37, count 2 2006.201.23:36:33.01#ibcon#enter sib2, iclass 37, count 2 2006.201.23:36:33.01#ibcon#flushed, iclass 37, count 2 2006.201.23:36:33.01#ibcon#about to write, iclass 37, count 2 2006.201.23:36:33.01#ibcon#wrote, iclass 37, count 2 2006.201.23:36:33.01#ibcon#about to read 3, iclass 37, count 2 2006.201.23:36:33.04#ibcon#read 3, iclass 37, count 2 2006.201.23:36:33.04#ibcon#about to read 4, iclass 37, count 2 2006.201.23:36:33.04#ibcon#read 4, iclass 37, count 2 2006.201.23:36:33.04#ibcon#about to read 5, iclass 37, count 2 2006.201.23:36:33.04#ibcon#read 5, iclass 37, count 2 2006.201.23:36:33.04#ibcon#about to read 6, iclass 37, count 2 2006.201.23:36:33.04#ibcon#read 6, iclass 37, count 2 2006.201.23:36:33.04#ibcon#end of sib2, iclass 37, count 2 2006.201.23:36:33.04#ibcon#*after write, iclass 37, count 2 2006.201.23:36:33.04#ibcon#*before return 0, iclass 37, count 2 2006.201.23:36:33.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:33.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:33.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.23:36:33.04#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:33.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:33.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:33.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:33.16#ibcon#enter wrdev, iclass 37, count 0 2006.201.23:36:33.16#ibcon#first serial, iclass 37, count 0 2006.201.23:36:33.16#ibcon#enter sib2, iclass 37, count 0 2006.201.23:36:33.16#ibcon#flushed, iclass 37, count 0 2006.201.23:36:33.16#ibcon#about to write, iclass 37, count 0 2006.201.23:36:33.16#ibcon#wrote, iclass 37, count 0 2006.201.23:36:33.16#ibcon#about to read 3, iclass 37, count 0 2006.201.23:36:33.18#ibcon#read 3, iclass 37, count 0 2006.201.23:36:33.18#ibcon#about to read 4, iclass 37, count 0 2006.201.23:36:33.18#ibcon#read 4, iclass 37, count 0 2006.201.23:36:33.18#ibcon#about to read 5, iclass 37, count 0 2006.201.23:36:33.18#ibcon#read 5, iclass 37, count 0 2006.201.23:36:33.18#ibcon#about to read 6, iclass 37, count 0 2006.201.23:36:33.18#ibcon#read 6, iclass 37, count 0 2006.201.23:36:33.18#ibcon#end of sib2, iclass 37, count 0 2006.201.23:36:33.18#ibcon#*mode == 0, iclass 37, count 0 2006.201.23:36:33.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.23:36:33.18#ibcon#[25=USB\r\n] 2006.201.23:36:33.18#ibcon#*before write, iclass 37, count 0 2006.201.23:36:33.18#ibcon#enter sib2, iclass 37, count 0 2006.201.23:36:33.18#ibcon#flushed, iclass 37, count 0 2006.201.23:36:33.18#ibcon#about to write, iclass 37, count 0 2006.201.23:36:33.18#ibcon#wrote, iclass 37, count 0 2006.201.23:36:33.18#ibcon#about to read 3, iclass 37, count 0 2006.201.23:36:33.21#ibcon#read 3, iclass 37, count 0 2006.201.23:36:33.21#ibcon#about to read 4, iclass 37, count 0 2006.201.23:36:33.21#ibcon#read 4, iclass 37, count 0 2006.201.23:36:33.21#ibcon#about to read 5, iclass 37, count 0 2006.201.23:36:33.21#ibcon#read 5, iclass 37, count 0 2006.201.23:36:33.21#ibcon#about to read 6, iclass 37, count 0 2006.201.23:36:33.21#ibcon#read 6, iclass 37, count 0 2006.201.23:36:33.21#ibcon#end of sib2, iclass 37, count 0 2006.201.23:36:33.21#ibcon#*after write, iclass 37, count 0 2006.201.23:36:33.21#ibcon#*before return 0, iclass 37, count 0 2006.201.23:36:33.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:33.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:33.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.23:36:33.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.23:36:33.21$vck44/valo=6,814.99 2006.201.23:36:33.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.23:36:33.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.23:36:33.21#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:33.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:33.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:33.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:33.21#ibcon#enter wrdev, iclass 39, count 0 2006.201.23:36:33.21#ibcon#first serial, iclass 39, count 0 2006.201.23:36:33.21#ibcon#enter sib2, iclass 39, count 0 2006.201.23:36:33.21#ibcon#flushed, iclass 39, count 0 2006.201.23:36:33.21#ibcon#about to write, iclass 39, count 0 2006.201.23:36:33.21#ibcon#wrote, iclass 39, count 0 2006.201.23:36:33.21#ibcon#about to read 3, iclass 39, count 0 2006.201.23:36:33.23#ibcon#read 3, iclass 39, count 0 2006.201.23:36:33.23#ibcon#about to read 4, iclass 39, count 0 2006.201.23:36:33.23#ibcon#read 4, iclass 39, count 0 2006.201.23:36:33.23#ibcon#about to read 5, iclass 39, count 0 2006.201.23:36:33.23#ibcon#read 5, iclass 39, count 0 2006.201.23:36:33.23#ibcon#about to read 6, iclass 39, count 0 2006.201.23:36:33.23#ibcon#read 6, iclass 39, count 0 2006.201.23:36:33.23#ibcon#end of sib2, iclass 39, count 0 2006.201.23:36:33.23#ibcon#*mode == 0, iclass 39, count 0 2006.201.23:36:33.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.23:36:33.23#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.23:36:33.23#ibcon#*before write, iclass 39, count 0 2006.201.23:36:33.23#ibcon#enter sib2, iclass 39, count 0 2006.201.23:36:33.23#ibcon#flushed, iclass 39, count 0 2006.201.23:36:33.23#ibcon#about to write, iclass 39, count 0 2006.201.23:36:33.23#ibcon#wrote, iclass 39, count 0 2006.201.23:36:33.23#ibcon#about to read 3, iclass 39, count 0 2006.201.23:36:33.27#ibcon#read 3, iclass 39, count 0 2006.201.23:36:33.27#ibcon#about to read 4, iclass 39, count 0 2006.201.23:36:33.27#ibcon#read 4, iclass 39, count 0 2006.201.23:36:33.27#ibcon#about to read 5, iclass 39, count 0 2006.201.23:36:33.27#ibcon#read 5, iclass 39, count 0 2006.201.23:36:33.27#ibcon#about to read 6, iclass 39, count 0 2006.201.23:36:33.27#ibcon#read 6, iclass 39, count 0 2006.201.23:36:33.27#ibcon#end of sib2, iclass 39, count 0 2006.201.23:36:33.27#ibcon#*after write, iclass 39, count 0 2006.201.23:36:33.27#ibcon#*before return 0, iclass 39, count 0 2006.201.23:36:33.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:33.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:33.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.23:36:33.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.23:36:33.27$vck44/va=6,5 2006.201.23:36:33.27#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.23:36:33.27#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.23:36:33.27#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:33.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:33.33#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:33.33#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:33.33#ibcon#enter wrdev, iclass 2, count 2 2006.201.23:36:33.33#ibcon#first serial, iclass 2, count 2 2006.201.23:36:33.33#ibcon#enter sib2, iclass 2, count 2 2006.201.23:36:33.33#ibcon#flushed, iclass 2, count 2 2006.201.23:36:33.33#ibcon#about to write, iclass 2, count 2 2006.201.23:36:33.33#ibcon#wrote, iclass 2, count 2 2006.201.23:36:33.33#ibcon#about to read 3, iclass 2, count 2 2006.201.23:36:33.35#ibcon#read 3, iclass 2, count 2 2006.201.23:36:33.35#ibcon#about to read 4, iclass 2, count 2 2006.201.23:36:33.35#ibcon#read 4, iclass 2, count 2 2006.201.23:36:33.35#ibcon#about to read 5, iclass 2, count 2 2006.201.23:36:33.35#ibcon#read 5, iclass 2, count 2 2006.201.23:36:33.35#ibcon#about to read 6, iclass 2, count 2 2006.201.23:36:33.35#ibcon#read 6, iclass 2, count 2 2006.201.23:36:33.35#ibcon#end of sib2, iclass 2, count 2 2006.201.23:36:33.35#ibcon#*mode == 0, iclass 2, count 2 2006.201.23:36:33.35#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.23:36:33.35#ibcon#[25=AT06-05\r\n] 2006.201.23:36:33.35#ibcon#*before write, iclass 2, count 2 2006.201.23:36:33.35#ibcon#enter sib2, iclass 2, count 2 2006.201.23:36:33.35#ibcon#flushed, iclass 2, count 2 2006.201.23:36:33.35#ibcon#about to write, iclass 2, count 2 2006.201.23:36:33.35#ibcon#wrote, iclass 2, count 2 2006.201.23:36:33.35#ibcon#about to read 3, iclass 2, count 2 2006.201.23:36:33.38#ibcon#read 3, iclass 2, count 2 2006.201.23:36:33.38#ibcon#about to read 4, iclass 2, count 2 2006.201.23:36:33.38#ibcon#read 4, iclass 2, count 2 2006.201.23:36:33.38#ibcon#about to read 5, iclass 2, count 2 2006.201.23:36:33.38#ibcon#read 5, iclass 2, count 2 2006.201.23:36:33.38#ibcon#about to read 6, iclass 2, count 2 2006.201.23:36:33.38#ibcon#read 6, iclass 2, count 2 2006.201.23:36:33.38#ibcon#end of sib2, iclass 2, count 2 2006.201.23:36:33.38#ibcon#*after write, iclass 2, count 2 2006.201.23:36:33.38#ibcon#*before return 0, iclass 2, count 2 2006.201.23:36:33.38#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:33.38#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:33.38#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.23:36:33.38#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:33.38#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:33.50#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:33.50#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:33.50#ibcon#enter wrdev, iclass 2, count 0 2006.201.23:36:33.50#ibcon#first serial, iclass 2, count 0 2006.201.23:36:33.50#ibcon#enter sib2, iclass 2, count 0 2006.201.23:36:33.50#ibcon#flushed, iclass 2, count 0 2006.201.23:36:33.50#ibcon#about to write, iclass 2, count 0 2006.201.23:36:33.50#ibcon#wrote, iclass 2, count 0 2006.201.23:36:33.50#ibcon#about to read 3, iclass 2, count 0 2006.201.23:36:33.52#ibcon#read 3, iclass 2, count 0 2006.201.23:36:33.52#ibcon#about to read 4, iclass 2, count 0 2006.201.23:36:33.52#ibcon#read 4, iclass 2, count 0 2006.201.23:36:33.52#ibcon#about to read 5, iclass 2, count 0 2006.201.23:36:33.52#ibcon#read 5, iclass 2, count 0 2006.201.23:36:33.52#ibcon#about to read 6, iclass 2, count 0 2006.201.23:36:33.52#ibcon#read 6, iclass 2, count 0 2006.201.23:36:33.52#ibcon#end of sib2, iclass 2, count 0 2006.201.23:36:33.52#ibcon#*mode == 0, iclass 2, count 0 2006.201.23:36:33.52#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.23:36:33.52#ibcon#[25=USB\r\n] 2006.201.23:36:33.52#ibcon#*before write, iclass 2, count 0 2006.201.23:36:33.52#ibcon#enter sib2, iclass 2, count 0 2006.201.23:36:33.52#ibcon#flushed, iclass 2, count 0 2006.201.23:36:33.52#ibcon#about to write, iclass 2, count 0 2006.201.23:36:33.52#ibcon#wrote, iclass 2, count 0 2006.201.23:36:33.52#ibcon#about to read 3, iclass 2, count 0 2006.201.23:36:33.55#ibcon#read 3, iclass 2, count 0 2006.201.23:36:33.55#ibcon#about to read 4, iclass 2, count 0 2006.201.23:36:33.55#ibcon#read 4, iclass 2, count 0 2006.201.23:36:33.55#ibcon#about to read 5, iclass 2, count 0 2006.201.23:36:33.55#ibcon#read 5, iclass 2, count 0 2006.201.23:36:33.55#ibcon#about to read 6, iclass 2, count 0 2006.201.23:36:33.55#ibcon#read 6, iclass 2, count 0 2006.201.23:36:33.55#ibcon#end of sib2, iclass 2, count 0 2006.201.23:36:33.55#ibcon#*after write, iclass 2, count 0 2006.201.23:36:33.55#ibcon#*before return 0, iclass 2, count 0 2006.201.23:36:33.55#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:33.55#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:33.55#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.23:36:33.55#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.23:36:33.55$vck44/valo=7,864.99 2006.201.23:36:33.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.23:36:33.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.23:36:33.55#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:33.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:33.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:33.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:33.55#ibcon#enter wrdev, iclass 5, count 0 2006.201.23:36:33.55#ibcon#first serial, iclass 5, count 0 2006.201.23:36:33.55#ibcon#enter sib2, iclass 5, count 0 2006.201.23:36:33.55#ibcon#flushed, iclass 5, count 0 2006.201.23:36:33.55#ibcon#about to write, iclass 5, count 0 2006.201.23:36:33.55#ibcon#wrote, iclass 5, count 0 2006.201.23:36:33.55#ibcon#about to read 3, iclass 5, count 0 2006.201.23:36:33.57#ibcon#read 3, iclass 5, count 0 2006.201.23:36:33.57#ibcon#about to read 4, iclass 5, count 0 2006.201.23:36:33.57#ibcon#read 4, iclass 5, count 0 2006.201.23:36:33.57#ibcon#about to read 5, iclass 5, count 0 2006.201.23:36:33.57#ibcon#read 5, iclass 5, count 0 2006.201.23:36:33.57#ibcon#about to read 6, iclass 5, count 0 2006.201.23:36:33.57#ibcon#read 6, iclass 5, count 0 2006.201.23:36:33.57#ibcon#end of sib2, iclass 5, count 0 2006.201.23:36:33.57#ibcon#*mode == 0, iclass 5, count 0 2006.201.23:36:33.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.23:36:33.57#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.23:36:33.57#ibcon#*before write, iclass 5, count 0 2006.201.23:36:33.57#ibcon#enter sib2, iclass 5, count 0 2006.201.23:36:33.57#ibcon#flushed, iclass 5, count 0 2006.201.23:36:33.57#ibcon#about to write, iclass 5, count 0 2006.201.23:36:33.57#ibcon#wrote, iclass 5, count 0 2006.201.23:36:33.57#ibcon#about to read 3, iclass 5, count 0 2006.201.23:36:33.61#ibcon#read 3, iclass 5, count 0 2006.201.23:36:33.61#ibcon#about to read 4, iclass 5, count 0 2006.201.23:36:33.61#ibcon#read 4, iclass 5, count 0 2006.201.23:36:33.61#ibcon#about to read 5, iclass 5, count 0 2006.201.23:36:33.61#ibcon#read 5, iclass 5, count 0 2006.201.23:36:33.61#ibcon#about to read 6, iclass 5, count 0 2006.201.23:36:33.61#ibcon#read 6, iclass 5, count 0 2006.201.23:36:33.61#ibcon#end of sib2, iclass 5, count 0 2006.201.23:36:33.61#ibcon#*after write, iclass 5, count 0 2006.201.23:36:33.61#ibcon#*before return 0, iclass 5, count 0 2006.201.23:36:33.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:33.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:33.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.23:36:33.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.23:36:33.61$vck44/va=7,5 2006.201.23:36:33.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.23:36:33.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.23:36:33.61#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:33.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:33.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:33.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:33.67#ibcon#enter wrdev, iclass 7, count 2 2006.201.23:36:33.67#ibcon#first serial, iclass 7, count 2 2006.201.23:36:33.67#ibcon#enter sib2, iclass 7, count 2 2006.201.23:36:33.67#ibcon#flushed, iclass 7, count 2 2006.201.23:36:33.67#ibcon#about to write, iclass 7, count 2 2006.201.23:36:33.67#ibcon#wrote, iclass 7, count 2 2006.201.23:36:33.67#ibcon#about to read 3, iclass 7, count 2 2006.201.23:36:33.69#ibcon#read 3, iclass 7, count 2 2006.201.23:36:33.69#ibcon#about to read 4, iclass 7, count 2 2006.201.23:36:33.69#ibcon#read 4, iclass 7, count 2 2006.201.23:36:33.69#ibcon#about to read 5, iclass 7, count 2 2006.201.23:36:33.69#ibcon#read 5, iclass 7, count 2 2006.201.23:36:33.69#ibcon#about to read 6, iclass 7, count 2 2006.201.23:36:33.69#ibcon#read 6, iclass 7, count 2 2006.201.23:36:33.69#ibcon#end of sib2, iclass 7, count 2 2006.201.23:36:33.69#ibcon#*mode == 0, iclass 7, count 2 2006.201.23:36:33.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.23:36:33.69#ibcon#[25=AT07-05\r\n] 2006.201.23:36:33.69#ibcon#*before write, iclass 7, count 2 2006.201.23:36:33.69#ibcon#enter sib2, iclass 7, count 2 2006.201.23:36:33.69#ibcon#flushed, iclass 7, count 2 2006.201.23:36:33.69#ibcon#about to write, iclass 7, count 2 2006.201.23:36:33.69#ibcon#wrote, iclass 7, count 2 2006.201.23:36:33.69#ibcon#about to read 3, iclass 7, count 2 2006.201.23:36:33.72#ibcon#read 3, iclass 7, count 2 2006.201.23:36:33.72#ibcon#about to read 4, iclass 7, count 2 2006.201.23:36:33.72#ibcon#read 4, iclass 7, count 2 2006.201.23:36:33.72#ibcon#about to read 5, iclass 7, count 2 2006.201.23:36:33.72#ibcon#read 5, iclass 7, count 2 2006.201.23:36:33.72#ibcon#about to read 6, iclass 7, count 2 2006.201.23:36:33.72#ibcon#read 6, iclass 7, count 2 2006.201.23:36:33.72#ibcon#end of sib2, iclass 7, count 2 2006.201.23:36:33.72#ibcon#*after write, iclass 7, count 2 2006.201.23:36:33.72#ibcon#*before return 0, iclass 7, count 2 2006.201.23:36:33.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:33.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:33.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.23:36:33.72#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:33.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:33.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:33.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:33.84#ibcon#enter wrdev, iclass 7, count 0 2006.201.23:36:33.84#ibcon#first serial, iclass 7, count 0 2006.201.23:36:33.84#ibcon#enter sib2, iclass 7, count 0 2006.201.23:36:33.84#ibcon#flushed, iclass 7, count 0 2006.201.23:36:33.84#ibcon#about to write, iclass 7, count 0 2006.201.23:36:33.84#ibcon#wrote, iclass 7, count 0 2006.201.23:36:33.84#ibcon#about to read 3, iclass 7, count 0 2006.201.23:36:33.86#ibcon#read 3, iclass 7, count 0 2006.201.23:36:33.86#ibcon#about to read 4, iclass 7, count 0 2006.201.23:36:33.86#ibcon#read 4, iclass 7, count 0 2006.201.23:36:33.86#ibcon#about to read 5, iclass 7, count 0 2006.201.23:36:33.86#ibcon#read 5, iclass 7, count 0 2006.201.23:36:33.86#ibcon#about to read 6, iclass 7, count 0 2006.201.23:36:33.86#ibcon#read 6, iclass 7, count 0 2006.201.23:36:33.86#ibcon#end of sib2, iclass 7, count 0 2006.201.23:36:33.86#ibcon#*mode == 0, iclass 7, count 0 2006.201.23:36:33.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.23:36:33.86#ibcon#[25=USB\r\n] 2006.201.23:36:33.86#ibcon#*before write, iclass 7, count 0 2006.201.23:36:33.86#ibcon#enter sib2, iclass 7, count 0 2006.201.23:36:33.86#ibcon#flushed, iclass 7, count 0 2006.201.23:36:33.86#ibcon#about to write, iclass 7, count 0 2006.201.23:36:33.86#ibcon#wrote, iclass 7, count 0 2006.201.23:36:33.86#ibcon#about to read 3, iclass 7, count 0 2006.201.23:36:33.89#ibcon#read 3, iclass 7, count 0 2006.201.23:36:33.89#ibcon#about to read 4, iclass 7, count 0 2006.201.23:36:33.89#ibcon#read 4, iclass 7, count 0 2006.201.23:36:33.89#ibcon#about to read 5, iclass 7, count 0 2006.201.23:36:33.89#ibcon#read 5, iclass 7, count 0 2006.201.23:36:33.89#ibcon#about to read 6, iclass 7, count 0 2006.201.23:36:33.89#ibcon#read 6, iclass 7, count 0 2006.201.23:36:33.89#ibcon#end of sib2, iclass 7, count 0 2006.201.23:36:33.89#ibcon#*after write, iclass 7, count 0 2006.201.23:36:33.89#ibcon#*before return 0, iclass 7, count 0 2006.201.23:36:33.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:33.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:33.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.23:36:33.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.23:36:33.89$vck44/valo=8,884.99 2006.201.23:36:33.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.23:36:33.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.23:36:33.89#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:33.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:33.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:33.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:33.89#ibcon#enter wrdev, iclass 11, count 0 2006.201.23:36:33.89#ibcon#first serial, iclass 11, count 0 2006.201.23:36:33.89#ibcon#enter sib2, iclass 11, count 0 2006.201.23:36:33.89#ibcon#flushed, iclass 11, count 0 2006.201.23:36:33.89#ibcon#about to write, iclass 11, count 0 2006.201.23:36:33.89#ibcon#wrote, iclass 11, count 0 2006.201.23:36:33.89#ibcon#about to read 3, iclass 11, count 0 2006.201.23:36:33.91#ibcon#read 3, iclass 11, count 0 2006.201.23:36:33.91#ibcon#about to read 4, iclass 11, count 0 2006.201.23:36:33.91#ibcon#read 4, iclass 11, count 0 2006.201.23:36:33.91#ibcon#about to read 5, iclass 11, count 0 2006.201.23:36:33.91#ibcon#read 5, iclass 11, count 0 2006.201.23:36:33.91#ibcon#about to read 6, iclass 11, count 0 2006.201.23:36:33.91#ibcon#read 6, iclass 11, count 0 2006.201.23:36:33.91#ibcon#end of sib2, iclass 11, count 0 2006.201.23:36:33.91#ibcon#*mode == 0, iclass 11, count 0 2006.201.23:36:33.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.23:36:33.91#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.23:36:33.91#ibcon#*before write, iclass 11, count 0 2006.201.23:36:33.91#ibcon#enter sib2, iclass 11, count 0 2006.201.23:36:33.91#ibcon#flushed, iclass 11, count 0 2006.201.23:36:33.91#ibcon#about to write, iclass 11, count 0 2006.201.23:36:33.91#ibcon#wrote, iclass 11, count 0 2006.201.23:36:33.91#ibcon#about to read 3, iclass 11, count 0 2006.201.23:36:33.95#ibcon#read 3, iclass 11, count 0 2006.201.23:36:33.95#ibcon#about to read 4, iclass 11, count 0 2006.201.23:36:33.95#ibcon#read 4, iclass 11, count 0 2006.201.23:36:33.95#ibcon#about to read 5, iclass 11, count 0 2006.201.23:36:33.95#ibcon#read 5, iclass 11, count 0 2006.201.23:36:33.95#ibcon#about to read 6, iclass 11, count 0 2006.201.23:36:33.95#ibcon#read 6, iclass 11, count 0 2006.201.23:36:33.95#ibcon#end of sib2, iclass 11, count 0 2006.201.23:36:33.95#ibcon#*after write, iclass 11, count 0 2006.201.23:36:33.95#ibcon#*before return 0, iclass 11, count 0 2006.201.23:36:33.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:33.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:33.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.23:36:33.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.23:36:33.95$vck44/va=8,4 2006.201.23:36:33.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.201.23:36:33.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.201.23:36:33.95#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:33.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:36:34.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:36:34.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:36:34.01#ibcon#enter wrdev, iclass 13, count 2 2006.201.23:36:34.01#ibcon#first serial, iclass 13, count 2 2006.201.23:36:34.01#ibcon#enter sib2, iclass 13, count 2 2006.201.23:36:34.01#ibcon#flushed, iclass 13, count 2 2006.201.23:36:34.01#ibcon#about to write, iclass 13, count 2 2006.201.23:36:34.01#ibcon#wrote, iclass 13, count 2 2006.201.23:36:34.01#ibcon#about to read 3, iclass 13, count 2 2006.201.23:36:34.03#ibcon#read 3, iclass 13, count 2 2006.201.23:36:34.03#ibcon#about to read 4, iclass 13, count 2 2006.201.23:36:34.03#ibcon#read 4, iclass 13, count 2 2006.201.23:36:34.03#ibcon#about to read 5, iclass 13, count 2 2006.201.23:36:34.03#ibcon#read 5, iclass 13, count 2 2006.201.23:36:34.03#ibcon#about to read 6, iclass 13, count 2 2006.201.23:36:34.03#ibcon#read 6, iclass 13, count 2 2006.201.23:36:34.03#ibcon#end of sib2, iclass 13, count 2 2006.201.23:36:34.03#ibcon#*mode == 0, iclass 13, count 2 2006.201.23:36:34.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.201.23:36:34.03#ibcon#[25=AT08-04\r\n] 2006.201.23:36:34.03#ibcon#*before write, iclass 13, count 2 2006.201.23:36:34.03#ibcon#enter sib2, iclass 13, count 2 2006.201.23:36:34.03#ibcon#flushed, iclass 13, count 2 2006.201.23:36:34.03#ibcon#about to write, iclass 13, count 2 2006.201.23:36:34.03#ibcon#wrote, iclass 13, count 2 2006.201.23:36:34.03#ibcon#about to read 3, iclass 13, count 2 2006.201.23:36:34.06#ibcon#read 3, iclass 13, count 2 2006.201.23:36:34.06#ibcon#about to read 4, iclass 13, count 2 2006.201.23:36:34.06#ibcon#read 4, iclass 13, count 2 2006.201.23:36:34.06#ibcon#about to read 5, iclass 13, count 2 2006.201.23:36:34.06#ibcon#read 5, iclass 13, count 2 2006.201.23:36:34.06#ibcon#about to read 6, iclass 13, count 2 2006.201.23:36:34.06#ibcon#read 6, iclass 13, count 2 2006.201.23:36:34.06#ibcon#end of sib2, iclass 13, count 2 2006.201.23:36:34.06#ibcon#*after write, iclass 13, count 2 2006.201.23:36:34.06#ibcon#*before return 0, iclass 13, count 2 2006.201.23:36:34.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:36:34.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.201.23:36:34.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.201.23:36:34.06#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:34.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:36:34.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:36:34.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:36:34.18#ibcon#enter wrdev, iclass 13, count 0 2006.201.23:36:34.18#ibcon#first serial, iclass 13, count 0 2006.201.23:36:34.18#ibcon#enter sib2, iclass 13, count 0 2006.201.23:36:34.18#ibcon#flushed, iclass 13, count 0 2006.201.23:36:34.18#ibcon#about to write, iclass 13, count 0 2006.201.23:36:34.18#ibcon#wrote, iclass 13, count 0 2006.201.23:36:34.18#ibcon#about to read 3, iclass 13, count 0 2006.201.23:36:34.20#ibcon#read 3, iclass 13, count 0 2006.201.23:36:34.20#ibcon#about to read 4, iclass 13, count 0 2006.201.23:36:34.20#ibcon#read 4, iclass 13, count 0 2006.201.23:36:34.20#ibcon#about to read 5, iclass 13, count 0 2006.201.23:36:34.20#ibcon#read 5, iclass 13, count 0 2006.201.23:36:34.20#ibcon#about to read 6, iclass 13, count 0 2006.201.23:36:34.20#ibcon#read 6, iclass 13, count 0 2006.201.23:36:34.20#ibcon#end of sib2, iclass 13, count 0 2006.201.23:36:34.20#ibcon#*mode == 0, iclass 13, count 0 2006.201.23:36:34.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.23:36:34.20#ibcon#[25=USB\r\n] 2006.201.23:36:34.20#ibcon#*before write, iclass 13, count 0 2006.201.23:36:34.20#ibcon#enter sib2, iclass 13, count 0 2006.201.23:36:34.20#ibcon#flushed, iclass 13, count 0 2006.201.23:36:34.20#ibcon#about to write, iclass 13, count 0 2006.201.23:36:34.20#ibcon#wrote, iclass 13, count 0 2006.201.23:36:34.20#ibcon#about to read 3, iclass 13, count 0 2006.201.23:36:34.23#ibcon#read 3, iclass 13, count 0 2006.201.23:36:34.23#ibcon#about to read 4, iclass 13, count 0 2006.201.23:36:34.23#ibcon#read 4, iclass 13, count 0 2006.201.23:36:34.23#ibcon#about to read 5, iclass 13, count 0 2006.201.23:36:34.23#ibcon#read 5, iclass 13, count 0 2006.201.23:36:34.23#ibcon#about to read 6, iclass 13, count 0 2006.201.23:36:34.23#ibcon#read 6, iclass 13, count 0 2006.201.23:36:34.23#ibcon#end of sib2, iclass 13, count 0 2006.201.23:36:34.23#ibcon#*after write, iclass 13, count 0 2006.201.23:36:34.23#ibcon#*before return 0, iclass 13, count 0 2006.201.23:36:34.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:36:34.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.201.23:36:34.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.23:36:34.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.23:36:34.23$vck44/vblo=1,629.99 2006.201.23:36:34.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.23:36:34.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.23:36:34.23#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:34.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:36:34.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:36:34.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:36:34.23#ibcon#enter wrdev, iclass 15, count 0 2006.201.23:36:34.23#ibcon#first serial, iclass 15, count 0 2006.201.23:36:34.23#ibcon#enter sib2, iclass 15, count 0 2006.201.23:36:34.23#ibcon#flushed, iclass 15, count 0 2006.201.23:36:34.23#ibcon#about to write, iclass 15, count 0 2006.201.23:36:34.23#ibcon#wrote, iclass 15, count 0 2006.201.23:36:34.23#ibcon#about to read 3, iclass 15, count 0 2006.201.23:36:34.25#ibcon#read 3, iclass 15, count 0 2006.201.23:36:34.25#ibcon#about to read 4, iclass 15, count 0 2006.201.23:36:34.25#ibcon#read 4, iclass 15, count 0 2006.201.23:36:34.25#ibcon#about to read 5, iclass 15, count 0 2006.201.23:36:34.25#ibcon#read 5, iclass 15, count 0 2006.201.23:36:34.25#ibcon#about to read 6, iclass 15, count 0 2006.201.23:36:34.25#ibcon#read 6, iclass 15, count 0 2006.201.23:36:34.25#ibcon#end of sib2, iclass 15, count 0 2006.201.23:36:34.25#ibcon#*mode == 0, iclass 15, count 0 2006.201.23:36:34.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.23:36:34.25#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.23:36:34.25#ibcon#*before write, iclass 15, count 0 2006.201.23:36:34.25#ibcon#enter sib2, iclass 15, count 0 2006.201.23:36:34.25#ibcon#flushed, iclass 15, count 0 2006.201.23:36:34.25#ibcon#about to write, iclass 15, count 0 2006.201.23:36:34.25#ibcon#wrote, iclass 15, count 0 2006.201.23:36:34.25#ibcon#about to read 3, iclass 15, count 0 2006.201.23:36:34.29#ibcon#read 3, iclass 15, count 0 2006.201.23:36:34.29#ibcon#about to read 4, iclass 15, count 0 2006.201.23:36:34.29#ibcon#read 4, iclass 15, count 0 2006.201.23:36:34.29#ibcon#about to read 5, iclass 15, count 0 2006.201.23:36:34.29#ibcon#read 5, iclass 15, count 0 2006.201.23:36:34.29#ibcon#about to read 6, iclass 15, count 0 2006.201.23:36:34.29#ibcon#read 6, iclass 15, count 0 2006.201.23:36:34.29#ibcon#end of sib2, iclass 15, count 0 2006.201.23:36:34.29#ibcon#*after write, iclass 15, count 0 2006.201.23:36:34.29#ibcon#*before return 0, iclass 15, count 0 2006.201.23:36:34.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:36:34.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:36:34.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.23:36:34.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.23:36:34.29$vck44/vb=1,4 2006.201.23:36:34.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.23:36:34.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.23:36:34.29#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:34.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:36:34.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:36:34.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:36:34.29#ibcon#enter wrdev, iclass 17, count 2 2006.201.23:36:34.29#ibcon#first serial, iclass 17, count 2 2006.201.23:36:34.29#ibcon#enter sib2, iclass 17, count 2 2006.201.23:36:34.29#ibcon#flushed, iclass 17, count 2 2006.201.23:36:34.29#ibcon#about to write, iclass 17, count 2 2006.201.23:36:34.29#ibcon#wrote, iclass 17, count 2 2006.201.23:36:34.29#ibcon#about to read 3, iclass 17, count 2 2006.201.23:36:34.31#ibcon#read 3, iclass 17, count 2 2006.201.23:36:34.31#ibcon#about to read 4, iclass 17, count 2 2006.201.23:36:34.31#ibcon#read 4, iclass 17, count 2 2006.201.23:36:34.31#ibcon#about to read 5, iclass 17, count 2 2006.201.23:36:34.31#ibcon#read 5, iclass 17, count 2 2006.201.23:36:34.31#ibcon#about to read 6, iclass 17, count 2 2006.201.23:36:34.31#ibcon#read 6, iclass 17, count 2 2006.201.23:36:34.31#ibcon#end of sib2, iclass 17, count 2 2006.201.23:36:34.31#ibcon#*mode == 0, iclass 17, count 2 2006.201.23:36:34.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.23:36:34.31#ibcon#[27=AT01-04\r\n] 2006.201.23:36:34.31#ibcon#*before write, iclass 17, count 2 2006.201.23:36:34.31#ibcon#enter sib2, iclass 17, count 2 2006.201.23:36:34.31#ibcon#flushed, iclass 17, count 2 2006.201.23:36:34.31#ibcon#about to write, iclass 17, count 2 2006.201.23:36:34.31#ibcon#wrote, iclass 17, count 2 2006.201.23:36:34.31#ibcon#about to read 3, iclass 17, count 2 2006.201.23:36:34.34#ibcon#read 3, iclass 17, count 2 2006.201.23:36:34.34#ibcon#about to read 4, iclass 17, count 2 2006.201.23:36:34.34#ibcon#read 4, iclass 17, count 2 2006.201.23:36:34.34#ibcon#about to read 5, iclass 17, count 2 2006.201.23:36:34.34#ibcon#read 5, iclass 17, count 2 2006.201.23:36:34.34#ibcon#about to read 6, iclass 17, count 2 2006.201.23:36:34.34#ibcon#read 6, iclass 17, count 2 2006.201.23:36:34.34#ibcon#end of sib2, iclass 17, count 2 2006.201.23:36:34.34#ibcon#*after write, iclass 17, count 2 2006.201.23:36:34.34#ibcon#*before return 0, iclass 17, count 2 2006.201.23:36:34.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:36:34.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:36:34.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.23:36:34.34#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:34.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:36:34.46#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:36:34.46#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:36:34.46#ibcon#enter wrdev, iclass 17, count 0 2006.201.23:36:34.46#ibcon#first serial, iclass 17, count 0 2006.201.23:36:34.46#ibcon#enter sib2, iclass 17, count 0 2006.201.23:36:34.46#ibcon#flushed, iclass 17, count 0 2006.201.23:36:34.46#ibcon#about to write, iclass 17, count 0 2006.201.23:36:34.46#ibcon#wrote, iclass 17, count 0 2006.201.23:36:34.46#ibcon#about to read 3, iclass 17, count 0 2006.201.23:36:34.48#ibcon#read 3, iclass 17, count 0 2006.201.23:36:34.48#ibcon#about to read 4, iclass 17, count 0 2006.201.23:36:34.48#ibcon#read 4, iclass 17, count 0 2006.201.23:36:34.48#ibcon#about to read 5, iclass 17, count 0 2006.201.23:36:34.48#ibcon#read 5, iclass 17, count 0 2006.201.23:36:34.48#ibcon#about to read 6, iclass 17, count 0 2006.201.23:36:34.48#ibcon#read 6, iclass 17, count 0 2006.201.23:36:34.48#ibcon#end of sib2, iclass 17, count 0 2006.201.23:36:34.48#ibcon#*mode == 0, iclass 17, count 0 2006.201.23:36:34.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.23:36:34.48#ibcon#[27=USB\r\n] 2006.201.23:36:34.48#ibcon#*before write, iclass 17, count 0 2006.201.23:36:34.48#ibcon#enter sib2, iclass 17, count 0 2006.201.23:36:34.48#ibcon#flushed, iclass 17, count 0 2006.201.23:36:34.48#ibcon#about to write, iclass 17, count 0 2006.201.23:36:34.48#ibcon#wrote, iclass 17, count 0 2006.201.23:36:34.48#ibcon#about to read 3, iclass 17, count 0 2006.201.23:36:34.51#ibcon#read 3, iclass 17, count 0 2006.201.23:36:34.51#ibcon#about to read 4, iclass 17, count 0 2006.201.23:36:34.51#ibcon#read 4, iclass 17, count 0 2006.201.23:36:34.51#ibcon#about to read 5, iclass 17, count 0 2006.201.23:36:34.51#ibcon#read 5, iclass 17, count 0 2006.201.23:36:34.51#ibcon#about to read 6, iclass 17, count 0 2006.201.23:36:34.51#ibcon#read 6, iclass 17, count 0 2006.201.23:36:34.51#ibcon#end of sib2, iclass 17, count 0 2006.201.23:36:34.51#ibcon#*after write, iclass 17, count 0 2006.201.23:36:34.51#ibcon#*before return 0, iclass 17, count 0 2006.201.23:36:34.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:36:34.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:36:34.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.23:36:34.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.23:36:34.51$vck44/vblo=2,634.99 2006.201.23:36:34.51#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.201.23:36:34.51#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.201.23:36:34.51#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:34.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:34.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:34.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:34.51#ibcon#enter wrdev, iclass 19, count 0 2006.201.23:36:34.51#ibcon#first serial, iclass 19, count 0 2006.201.23:36:34.51#ibcon#enter sib2, iclass 19, count 0 2006.201.23:36:34.51#ibcon#flushed, iclass 19, count 0 2006.201.23:36:34.51#ibcon#about to write, iclass 19, count 0 2006.201.23:36:34.51#ibcon#wrote, iclass 19, count 0 2006.201.23:36:34.51#ibcon#about to read 3, iclass 19, count 0 2006.201.23:36:34.53#ibcon#read 3, iclass 19, count 0 2006.201.23:36:34.53#ibcon#about to read 4, iclass 19, count 0 2006.201.23:36:34.53#ibcon#read 4, iclass 19, count 0 2006.201.23:36:34.53#ibcon#about to read 5, iclass 19, count 0 2006.201.23:36:34.53#ibcon#read 5, iclass 19, count 0 2006.201.23:36:34.53#ibcon#about to read 6, iclass 19, count 0 2006.201.23:36:34.53#ibcon#read 6, iclass 19, count 0 2006.201.23:36:34.53#ibcon#end of sib2, iclass 19, count 0 2006.201.23:36:34.53#ibcon#*mode == 0, iclass 19, count 0 2006.201.23:36:34.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.23:36:34.53#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.23:36:34.53#ibcon#*before write, iclass 19, count 0 2006.201.23:36:34.53#ibcon#enter sib2, iclass 19, count 0 2006.201.23:36:34.53#ibcon#flushed, iclass 19, count 0 2006.201.23:36:34.53#ibcon#about to write, iclass 19, count 0 2006.201.23:36:34.53#ibcon#wrote, iclass 19, count 0 2006.201.23:36:34.53#ibcon#about to read 3, iclass 19, count 0 2006.201.23:36:34.57#ibcon#read 3, iclass 19, count 0 2006.201.23:36:34.57#ibcon#about to read 4, iclass 19, count 0 2006.201.23:36:34.57#ibcon#read 4, iclass 19, count 0 2006.201.23:36:34.57#ibcon#about to read 5, iclass 19, count 0 2006.201.23:36:34.57#ibcon#read 5, iclass 19, count 0 2006.201.23:36:34.57#ibcon#about to read 6, iclass 19, count 0 2006.201.23:36:34.57#ibcon#read 6, iclass 19, count 0 2006.201.23:36:34.57#ibcon#end of sib2, iclass 19, count 0 2006.201.23:36:34.57#ibcon#*after write, iclass 19, count 0 2006.201.23:36:34.57#ibcon#*before return 0, iclass 19, count 0 2006.201.23:36:34.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:34.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.201.23:36:34.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.23:36:34.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.23:36:34.57$vck44/vb=2,5 2006.201.23:36:34.57#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.201.23:36:34.57#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.201.23:36:34.57#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:34.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:34.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:34.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:34.63#ibcon#enter wrdev, iclass 21, count 2 2006.201.23:36:34.63#ibcon#first serial, iclass 21, count 2 2006.201.23:36:34.63#ibcon#enter sib2, iclass 21, count 2 2006.201.23:36:34.63#ibcon#flushed, iclass 21, count 2 2006.201.23:36:34.63#ibcon#about to write, iclass 21, count 2 2006.201.23:36:34.63#ibcon#wrote, iclass 21, count 2 2006.201.23:36:34.63#ibcon#about to read 3, iclass 21, count 2 2006.201.23:36:34.65#ibcon#read 3, iclass 21, count 2 2006.201.23:36:34.65#ibcon#about to read 4, iclass 21, count 2 2006.201.23:36:34.65#ibcon#read 4, iclass 21, count 2 2006.201.23:36:34.65#ibcon#about to read 5, iclass 21, count 2 2006.201.23:36:34.65#ibcon#read 5, iclass 21, count 2 2006.201.23:36:34.65#ibcon#about to read 6, iclass 21, count 2 2006.201.23:36:34.65#ibcon#read 6, iclass 21, count 2 2006.201.23:36:34.65#ibcon#end of sib2, iclass 21, count 2 2006.201.23:36:34.65#ibcon#*mode == 0, iclass 21, count 2 2006.201.23:36:34.65#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.201.23:36:34.65#ibcon#[27=AT02-05\r\n] 2006.201.23:36:34.65#ibcon#*before write, iclass 21, count 2 2006.201.23:36:34.65#ibcon#enter sib2, iclass 21, count 2 2006.201.23:36:34.65#ibcon#flushed, iclass 21, count 2 2006.201.23:36:34.65#ibcon#about to write, iclass 21, count 2 2006.201.23:36:34.65#ibcon#wrote, iclass 21, count 2 2006.201.23:36:34.65#ibcon#about to read 3, iclass 21, count 2 2006.201.23:36:34.68#ibcon#read 3, iclass 21, count 2 2006.201.23:36:34.68#ibcon#about to read 4, iclass 21, count 2 2006.201.23:36:34.68#ibcon#read 4, iclass 21, count 2 2006.201.23:36:34.68#ibcon#about to read 5, iclass 21, count 2 2006.201.23:36:34.68#ibcon#read 5, iclass 21, count 2 2006.201.23:36:34.68#ibcon#about to read 6, iclass 21, count 2 2006.201.23:36:34.68#ibcon#read 6, iclass 21, count 2 2006.201.23:36:34.68#ibcon#end of sib2, iclass 21, count 2 2006.201.23:36:34.68#ibcon#*after write, iclass 21, count 2 2006.201.23:36:34.68#ibcon#*before return 0, iclass 21, count 2 2006.201.23:36:34.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:34.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.201.23:36:34.68#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.201.23:36:34.68#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:34.68#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:34.80#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:34.80#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:34.80#ibcon#enter wrdev, iclass 21, count 0 2006.201.23:36:34.80#ibcon#first serial, iclass 21, count 0 2006.201.23:36:34.80#ibcon#enter sib2, iclass 21, count 0 2006.201.23:36:34.80#ibcon#flushed, iclass 21, count 0 2006.201.23:36:34.80#ibcon#about to write, iclass 21, count 0 2006.201.23:36:34.80#ibcon#wrote, iclass 21, count 0 2006.201.23:36:34.80#ibcon#about to read 3, iclass 21, count 0 2006.201.23:36:34.82#ibcon#read 3, iclass 21, count 0 2006.201.23:36:34.82#ibcon#about to read 4, iclass 21, count 0 2006.201.23:36:34.82#ibcon#read 4, iclass 21, count 0 2006.201.23:36:34.82#ibcon#about to read 5, iclass 21, count 0 2006.201.23:36:34.82#ibcon#read 5, iclass 21, count 0 2006.201.23:36:34.82#ibcon#about to read 6, iclass 21, count 0 2006.201.23:36:34.82#ibcon#read 6, iclass 21, count 0 2006.201.23:36:34.82#ibcon#end of sib2, iclass 21, count 0 2006.201.23:36:34.82#ibcon#*mode == 0, iclass 21, count 0 2006.201.23:36:34.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.23:36:34.82#ibcon#[27=USB\r\n] 2006.201.23:36:34.82#ibcon#*before write, iclass 21, count 0 2006.201.23:36:34.82#ibcon#enter sib2, iclass 21, count 0 2006.201.23:36:34.82#ibcon#flushed, iclass 21, count 0 2006.201.23:36:34.82#ibcon#about to write, iclass 21, count 0 2006.201.23:36:34.82#ibcon#wrote, iclass 21, count 0 2006.201.23:36:34.82#ibcon#about to read 3, iclass 21, count 0 2006.201.23:36:34.85#ibcon#read 3, iclass 21, count 0 2006.201.23:36:34.85#ibcon#about to read 4, iclass 21, count 0 2006.201.23:36:34.85#ibcon#read 4, iclass 21, count 0 2006.201.23:36:34.85#ibcon#about to read 5, iclass 21, count 0 2006.201.23:36:34.85#ibcon#read 5, iclass 21, count 0 2006.201.23:36:34.85#ibcon#about to read 6, iclass 21, count 0 2006.201.23:36:34.85#ibcon#read 6, iclass 21, count 0 2006.201.23:36:34.85#ibcon#end of sib2, iclass 21, count 0 2006.201.23:36:34.85#ibcon#*after write, iclass 21, count 0 2006.201.23:36:34.85#ibcon#*before return 0, iclass 21, count 0 2006.201.23:36:34.85#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:34.85#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.201.23:36:34.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.23:36:34.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.23:36:34.85$vck44/vblo=3,649.99 2006.201.23:36:34.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.201.23:36:34.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.201.23:36:34.85#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:34.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:34.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:34.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:34.85#ibcon#enter wrdev, iclass 23, count 0 2006.201.23:36:34.85#ibcon#first serial, iclass 23, count 0 2006.201.23:36:34.85#ibcon#enter sib2, iclass 23, count 0 2006.201.23:36:34.85#ibcon#flushed, iclass 23, count 0 2006.201.23:36:34.85#ibcon#about to write, iclass 23, count 0 2006.201.23:36:34.85#ibcon#wrote, iclass 23, count 0 2006.201.23:36:34.85#ibcon#about to read 3, iclass 23, count 0 2006.201.23:36:34.87#ibcon#read 3, iclass 23, count 0 2006.201.23:36:34.87#ibcon#about to read 4, iclass 23, count 0 2006.201.23:36:34.87#ibcon#read 4, iclass 23, count 0 2006.201.23:36:34.87#ibcon#about to read 5, iclass 23, count 0 2006.201.23:36:34.87#ibcon#read 5, iclass 23, count 0 2006.201.23:36:34.87#ibcon#about to read 6, iclass 23, count 0 2006.201.23:36:34.87#ibcon#read 6, iclass 23, count 0 2006.201.23:36:34.87#ibcon#end of sib2, iclass 23, count 0 2006.201.23:36:34.87#ibcon#*mode == 0, iclass 23, count 0 2006.201.23:36:34.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.23:36:34.87#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.23:36:34.87#ibcon#*before write, iclass 23, count 0 2006.201.23:36:34.87#ibcon#enter sib2, iclass 23, count 0 2006.201.23:36:34.87#ibcon#flushed, iclass 23, count 0 2006.201.23:36:34.87#ibcon#about to write, iclass 23, count 0 2006.201.23:36:34.87#ibcon#wrote, iclass 23, count 0 2006.201.23:36:34.87#ibcon#about to read 3, iclass 23, count 0 2006.201.23:36:34.91#ibcon#read 3, iclass 23, count 0 2006.201.23:36:34.91#ibcon#about to read 4, iclass 23, count 0 2006.201.23:36:34.91#ibcon#read 4, iclass 23, count 0 2006.201.23:36:34.91#ibcon#about to read 5, iclass 23, count 0 2006.201.23:36:34.91#ibcon#read 5, iclass 23, count 0 2006.201.23:36:34.91#ibcon#about to read 6, iclass 23, count 0 2006.201.23:36:34.91#ibcon#read 6, iclass 23, count 0 2006.201.23:36:34.91#ibcon#end of sib2, iclass 23, count 0 2006.201.23:36:34.91#ibcon#*after write, iclass 23, count 0 2006.201.23:36:34.91#ibcon#*before return 0, iclass 23, count 0 2006.201.23:36:34.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:34.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.201.23:36:34.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.23:36:34.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.23:36:34.91$vck44/vb=3,4 2006.201.23:36:34.91#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.201.23:36:34.91#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.201.23:36:34.91#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:34.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:34.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:34.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:34.97#ibcon#enter wrdev, iclass 25, count 2 2006.201.23:36:34.97#ibcon#first serial, iclass 25, count 2 2006.201.23:36:34.97#ibcon#enter sib2, iclass 25, count 2 2006.201.23:36:34.97#ibcon#flushed, iclass 25, count 2 2006.201.23:36:34.97#ibcon#about to write, iclass 25, count 2 2006.201.23:36:34.97#ibcon#wrote, iclass 25, count 2 2006.201.23:36:34.97#ibcon#about to read 3, iclass 25, count 2 2006.201.23:36:34.99#ibcon#read 3, iclass 25, count 2 2006.201.23:36:34.99#ibcon#about to read 4, iclass 25, count 2 2006.201.23:36:34.99#ibcon#read 4, iclass 25, count 2 2006.201.23:36:34.99#ibcon#about to read 5, iclass 25, count 2 2006.201.23:36:34.99#ibcon#read 5, iclass 25, count 2 2006.201.23:36:34.99#ibcon#about to read 6, iclass 25, count 2 2006.201.23:36:34.99#ibcon#read 6, iclass 25, count 2 2006.201.23:36:34.99#ibcon#end of sib2, iclass 25, count 2 2006.201.23:36:34.99#ibcon#*mode == 0, iclass 25, count 2 2006.201.23:36:34.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.201.23:36:34.99#ibcon#[27=AT03-04\r\n] 2006.201.23:36:34.99#ibcon#*before write, iclass 25, count 2 2006.201.23:36:34.99#ibcon#enter sib2, iclass 25, count 2 2006.201.23:36:34.99#ibcon#flushed, iclass 25, count 2 2006.201.23:36:34.99#ibcon#about to write, iclass 25, count 2 2006.201.23:36:34.99#ibcon#wrote, iclass 25, count 2 2006.201.23:36:34.99#ibcon#about to read 3, iclass 25, count 2 2006.201.23:36:35.02#ibcon#read 3, iclass 25, count 2 2006.201.23:36:35.02#ibcon#about to read 4, iclass 25, count 2 2006.201.23:36:35.02#ibcon#read 4, iclass 25, count 2 2006.201.23:36:35.02#ibcon#about to read 5, iclass 25, count 2 2006.201.23:36:35.02#ibcon#read 5, iclass 25, count 2 2006.201.23:36:35.02#ibcon#about to read 6, iclass 25, count 2 2006.201.23:36:35.02#ibcon#read 6, iclass 25, count 2 2006.201.23:36:35.02#ibcon#end of sib2, iclass 25, count 2 2006.201.23:36:35.02#ibcon#*after write, iclass 25, count 2 2006.201.23:36:35.02#ibcon#*before return 0, iclass 25, count 2 2006.201.23:36:35.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:35.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.201.23:36:35.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.201.23:36:35.02#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:35.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:35.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:35.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:35.14#ibcon#enter wrdev, iclass 25, count 0 2006.201.23:36:35.14#ibcon#first serial, iclass 25, count 0 2006.201.23:36:35.14#ibcon#enter sib2, iclass 25, count 0 2006.201.23:36:35.14#ibcon#flushed, iclass 25, count 0 2006.201.23:36:35.14#ibcon#about to write, iclass 25, count 0 2006.201.23:36:35.14#ibcon#wrote, iclass 25, count 0 2006.201.23:36:35.14#ibcon#about to read 3, iclass 25, count 0 2006.201.23:36:35.16#ibcon#read 3, iclass 25, count 0 2006.201.23:36:35.16#ibcon#about to read 4, iclass 25, count 0 2006.201.23:36:35.16#ibcon#read 4, iclass 25, count 0 2006.201.23:36:35.16#ibcon#about to read 5, iclass 25, count 0 2006.201.23:36:35.16#ibcon#read 5, iclass 25, count 0 2006.201.23:36:35.16#ibcon#about to read 6, iclass 25, count 0 2006.201.23:36:35.16#ibcon#read 6, iclass 25, count 0 2006.201.23:36:35.16#ibcon#end of sib2, iclass 25, count 0 2006.201.23:36:35.16#ibcon#*mode == 0, iclass 25, count 0 2006.201.23:36:35.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.23:36:35.16#ibcon#[27=USB\r\n] 2006.201.23:36:35.16#ibcon#*before write, iclass 25, count 0 2006.201.23:36:35.16#ibcon#enter sib2, iclass 25, count 0 2006.201.23:36:35.16#ibcon#flushed, iclass 25, count 0 2006.201.23:36:35.16#ibcon#about to write, iclass 25, count 0 2006.201.23:36:35.16#ibcon#wrote, iclass 25, count 0 2006.201.23:36:35.16#ibcon#about to read 3, iclass 25, count 0 2006.201.23:36:35.19#ibcon#read 3, iclass 25, count 0 2006.201.23:36:35.19#ibcon#about to read 4, iclass 25, count 0 2006.201.23:36:35.19#ibcon#read 4, iclass 25, count 0 2006.201.23:36:35.19#ibcon#about to read 5, iclass 25, count 0 2006.201.23:36:35.19#ibcon#read 5, iclass 25, count 0 2006.201.23:36:35.19#ibcon#about to read 6, iclass 25, count 0 2006.201.23:36:35.19#ibcon#read 6, iclass 25, count 0 2006.201.23:36:35.19#ibcon#end of sib2, iclass 25, count 0 2006.201.23:36:35.19#ibcon#*after write, iclass 25, count 0 2006.201.23:36:35.19#ibcon#*before return 0, iclass 25, count 0 2006.201.23:36:35.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:35.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.201.23:36:35.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.23:36:35.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.23:36:35.19$vck44/vblo=4,679.99 2006.201.23:36:35.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.201.23:36:35.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.201.23:36:35.19#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:35.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:35.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:35.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:35.19#ibcon#enter wrdev, iclass 27, count 0 2006.201.23:36:35.19#ibcon#first serial, iclass 27, count 0 2006.201.23:36:35.19#ibcon#enter sib2, iclass 27, count 0 2006.201.23:36:35.19#ibcon#flushed, iclass 27, count 0 2006.201.23:36:35.19#ibcon#about to write, iclass 27, count 0 2006.201.23:36:35.19#ibcon#wrote, iclass 27, count 0 2006.201.23:36:35.19#ibcon#about to read 3, iclass 27, count 0 2006.201.23:36:35.21#ibcon#read 3, iclass 27, count 0 2006.201.23:36:35.21#ibcon#about to read 4, iclass 27, count 0 2006.201.23:36:35.21#ibcon#read 4, iclass 27, count 0 2006.201.23:36:35.21#ibcon#about to read 5, iclass 27, count 0 2006.201.23:36:35.21#ibcon#read 5, iclass 27, count 0 2006.201.23:36:35.21#ibcon#about to read 6, iclass 27, count 0 2006.201.23:36:35.21#ibcon#read 6, iclass 27, count 0 2006.201.23:36:35.21#ibcon#end of sib2, iclass 27, count 0 2006.201.23:36:35.21#ibcon#*mode == 0, iclass 27, count 0 2006.201.23:36:35.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.23:36:35.21#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.23:36:35.21#ibcon#*before write, iclass 27, count 0 2006.201.23:36:35.21#ibcon#enter sib2, iclass 27, count 0 2006.201.23:36:35.21#ibcon#flushed, iclass 27, count 0 2006.201.23:36:35.21#ibcon#about to write, iclass 27, count 0 2006.201.23:36:35.21#ibcon#wrote, iclass 27, count 0 2006.201.23:36:35.21#ibcon#about to read 3, iclass 27, count 0 2006.201.23:36:35.25#ibcon#read 3, iclass 27, count 0 2006.201.23:36:35.25#ibcon#about to read 4, iclass 27, count 0 2006.201.23:36:35.25#ibcon#read 4, iclass 27, count 0 2006.201.23:36:35.25#ibcon#about to read 5, iclass 27, count 0 2006.201.23:36:35.25#ibcon#read 5, iclass 27, count 0 2006.201.23:36:35.25#ibcon#about to read 6, iclass 27, count 0 2006.201.23:36:35.25#ibcon#read 6, iclass 27, count 0 2006.201.23:36:35.25#ibcon#end of sib2, iclass 27, count 0 2006.201.23:36:35.25#ibcon#*after write, iclass 27, count 0 2006.201.23:36:35.25#ibcon#*before return 0, iclass 27, count 0 2006.201.23:36:35.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:35.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.201.23:36:35.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.23:36:35.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.23:36:35.25$vck44/vb=4,5 2006.201.23:36:35.25#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.201.23:36:35.25#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.201.23:36:35.25#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:35.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:35.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:35.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:35.31#ibcon#enter wrdev, iclass 29, count 2 2006.201.23:36:35.31#ibcon#first serial, iclass 29, count 2 2006.201.23:36:35.31#ibcon#enter sib2, iclass 29, count 2 2006.201.23:36:35.31#ibcon#flushed, iclass 29, count 2 2006.201.23:36:35.31#ibcon#about to write, iclass 29, count 2 2006.201.23:36:35.31#ibcon#wrote, iclass 29, count 2 2006.201.23:36:35.31#ibcon#about to read 3, iclass 29, count 2 2006.201.23:36:35.33#ibcon#read 3, iclass 29, count 2 2006.201.23:36:35.33#ibcon#about to read 4, iclass 29, count 2 2006.201.23:36:35.33#ibcon#read 4, iclass 29, count 2 2006.201.23:36:35.33#ibcon#about to read 5, iclass 29, count 2 2006.201.23:36:35.33#ibcon#read 5, iclass 29, count 2 2006.201.23:36:35.33#ibcon#about to read 6, iclass 29, count 2 2006.201.23:36:35.33#ibcon#read 6, iclass 29, count 2 2006.201.23:36:35.33#ibcon#end of sib2, iclass 29, count 2 2006.201.23:36:35.33#ibcon#*mode == 0, iclass 29, count 2 2006.201.23:36:35.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.201.23:36:35.33#ibcon#[27=AT04-05\r\n] 2006.201.23:36:35.33#ibcon#*before write, iclass 29, count 2 2006.201.23:36:35.33#ibcon#enter sib2, iclass 29, count 2 2006.201.23:36:35.33#ibcon#flushed, iclass 29, count 2 2006.201.23:36:35.33#ibcon#about to write, iclass 29, count 2 2006.201.23:36:35.33#ibcon#wrote, iclass 29, count 2 2006.201.23:36:35.33#ibcon#about to read 3, iclass 29, count 2 2006.201.23:36:35.36#ibcon#read 3, iclass 29, count 2 2006.201.23:36:35.36#ibcon#about to read 4, iclass 29, count 2 2006.201.23:36:35.36#ibcon#read 4, iclass 29, count 2 2006.201.23:36:35.36#ibcon#about to read 5, iclass 29, count 2 2006.201.23:36:35.36#ibcon#read 5, iclass 29, count 2 2006.201.23:36:35.36#ibcon#about to read 6, iclass 29, count 2 2006.201.23:36:35.36#ibcon#read 6, iclass 29, count 2 2006.201.23:36:35.36#ibcon#end of sib2, iclass 29, count 2 2006.201.23:36:35.36#ibcon#*after write, iclass 29, count 2 2006.201.23:36:35.36#ibcon#*before return 0, iclass 29, count 2 2006.201.23:36:35.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:35.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.201.23:36:35.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.201.23:36:35.36#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:35.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:35.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:35.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:35.48#ibcon#enter wrdev, iclass 29, count 0 2006.201.23:36:35.48#ibcon#first serial, iclass 29, count 0 2006.201.23:36:35.48#ibcon#enter sib2, iclass 29, count 0 2006.201.23:36:35.48#ibcon#flushed, iclass 29, count 0 2006.201.23:36:35.48#ibcon#about to write, iclass 29, count 0 2006.201.23:36:35.48#ibcon#wrote, iclass 29, count 0 2006.201.23:36:35.48#ibcon#about to read 3, iclass 29, count 0 2006.201.23:36:35.50#ibcon#read 3, iclass 29, count 0 2006.201.23:36:35.50#ibcon#about to read 4, iclass 29, count 0 2006.201.23:36:35.50#ibcon#read 4, iclass 29, count 0 2006.201.23:36:35.50#ibcon#about to read 5, iclass 29, count 0 2006.201.23:36:35.50#ibcon#read 5, iclass 29, count 0 2006.201.23:36:35.50#ibcon#about to read 6, iclass 29, count 0 2006.201.23:36:35.50#ibcon#read 6, iclass 29, count 0 2006.201.23:36:35.50#ibcon#end of sib2, iclass 29, count 0 2006.201.23:36:35.50#ibcon#*mode == 0, iclass 29, count 0 2006.201.23:36:35.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.23:36:35.50#ibcon#[27=USB\r\n] 2006.201.23:36:35.50#ibcon#*before write, iclass 29, count 0 2006.201.23:36:35.50#ibcon#enter sib2, iclass 29, count 0 2006.201.23:36:35.50#ibcon#flushed, iclass 29, count 0 2006.201.23:36:35.50#ibcon#about to write, iclass 29, count 0 2006.201.23:36:35.50#ibcon#wrote, iclass 29, count 0 2006.201.23:36:35.50#ibcon#about to read 3, iclass 29, count 0 2006.201.23:36:35.53#ibcon#read 3, iclass 29, count 0 2006.201.23:36:35.53#ibcon#about to read 4, iclass 29, count 0 2006.201.23:36:35.53#ibcon#read 4, iclass 29, count 0 2006.201.23:36:35.53#ibcon#about to read 5, iclass 29, count 0 2006.201.23:36:35.53#ibcon#read 5, iclass 29, count 0 2006.201.23:36:35.53#ibcon#about to read 6, iclass 29, count 0 2006.201.23:36:35.53#ibcon#read 6, iclass 29, count 0 2006.201.23:36:35.53#ibcon#end of sib2, iclass 29, count 0 2006.201.23:36:35.53#ibcon#*after write, iclass 29, count 0 2006.201.23:36:35.53#ibcon#*before return 0, iclass 29, count 0 2006.201.23:36:35.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:35.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.201.23:36:35.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.23:36:35.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.23:36:35.53$vck44/vblo=5,709.99 2006.201.23:36:35.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.201.23:36:35.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.201.23:36:35.53#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:35.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:35.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:35.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:35.53#ibcon#enter wrdev, iclass 31, count 0 2006.201.23:36:35.53#ibcon#first serial, iclass 31, count 0 2006.201.23:36:35.53#ibcon#enter sib2, iclass 31, count 0 2006.201.23:36:35.53#ibcon#flushed, iclass 31, count 0 2006.201.23:36:35.53#ibcon#about to write, iclass 31, count 0 2006.201.23:36:35.53#ibcon#wrote, iclass 31, count 0 2006.201.23:36:35.53#ibcon#about to read 3, iclass 31, count 0 2006.201.23:36:35.55#ibcon#read 3, iclass 31, count 0 2006.201.23:36:35.55#ibcon#about to read 4, iclass 31, count 0 2006.201.23:36:35.55#ibcon#read 4, iclass 31, count 0 2006.201.23:36:35.55#ibcon#about to read 5, iclass 31, count 0 2006.201.23:36:35.55#ibcon#read 5, iclass 31, count 0 2006.201.23:36:35.55#ibcon#about to read 6, iclass 31, count 0 2006.201.23:36:35.55#ibcon#read 6, iclass 31, count 0 2006.201.23:36:35.55#ibcon#end of sib2, iclass 31, count 0 2006.201.23:36:35.55#ibcon#*mode == 0, iclass 31, count 0 2006.201.23:36:35.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.23:36:35.55#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.23:36:35.55#ibcon#*before write, iclass 31, count 0 2006.201.23:36:35.55#ibcon#enter sib2, iclass 31, count 0 2006.201.23:36:35.55#ibcon#flushed, iclass 31, count 0 2006.201.23:36:35.55#ibcon#about to write, iclass 31, count 0 2006.201.23:36:35.55#ibcon#wrote, iclass 31, count 0 2006.201.23:36:35.55#ibcon#about to read 3, iclass 31, count 0 2006.201.23:36:35.59#ibcon#read 3, iclass 31, count 0 2006.201.23:36:35.59#ibcon#about to read 4, iclass 31, count 0 2006.201.23:36:35.59#ibcon#read 4, iclass 31, count 0 2006.201.23:36:35.59#ibcon#about to read 5, iclass 31, count 0 2006.201.23:36:35.59#ibcon#read 5, iclass 31, count 0 2006.201.23:36:35.59#ibcon#about to read 6, iclass 31, count 0 2006.201.23:36:35.59#ibcon#read 6, iclass 31, count 0 2006.201.23:36:35.59#ibcon#end of sib2, iclass 31, count 0 2006.201.23:36:35.59#ibcon#*after write, iclass 31, count 0 2006.201.23:36:35.59#ibcon#*before return 0, iclass 31, count 0 2006.201.23:36:35.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:35.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.201.23:36:35.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.23:36:35.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.23:36:35.59$vck44/vb=5,4 2006.201.23:36:35.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.201.23:36:35.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.201.23:36:35.59#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:35.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:35.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:35.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:35.65#ibcon#enter wrdev, iclass 33, count 2 2006.201.23:36:35.65#ibcon#first serial, iclass 33, count 2 2006.201.23:36:35.65#ibcon#enter sib2, iclass 33, count 2 2006.201.23:36:35.65#ibcon#flushed, iclass 33, count 2 2006.201.23:36:35.65#ibcon#about to write, iclass 33, count 2 2006.201.23:36:35.65#ibcon#wrote, iclass 33, count 2 2006.201.23:36:35.65#ibcon#about to read 3, iclass 33, count 2 2006.201.23:36:35.67#ibcon#read 3, iclass 33, count 2 2006.201.23:36:35.67#ibcon#about to read 4, iclass 33, count 2 2006.201.23:36:35.67#ibcon#read 4, iclass 33, count 2 2006.201.23:36:35.67#ibcon#about to read 5, iclass 33, count 2 2006.201.23:36:35.67#ibcon#read 5, iclass 33, count 2 2006.201.23:36:35.67#ibcon#about to read 6, iclass 33, count 2 2006.201.23:36:35.67#ibcon#read 6, iclass 33, count 2 2006.201.23:36:35.67#ibcon#end of sib2, iclass 33, count 2 2006.201.23:36:35.67#ibcon#*mode == 0, iclass 33, count 2 2006.201.23:36:35.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.201.23:36:35.67#ibcon#[27=AT05-04\r\n] 2006.201.23:36:35.67#ibcon#*before write, iclass 33, count 2 2006.201.23:36:35.67#ibcon#enter sib2, iclass 33, count 2 2006.201.23:36:35.67#ibcon#flushed, iclass 33, count 2 2006.201.23:36:35.67#ibcon#about to write, iclass 33, count 2 2006.201.23:36:35.67#ibcon#wrote, iclass 33, count 2 2006.201.23:36:35.67#ibcon#about to read 3, iclass 33, count 2 2006.201.23:36:35.70#ibcon#read 3, iclass 33, count 2 2006.201.23:36:35.70#ibcon#about to read 4, iclass 33, count 2 2006.201.23:36:35.70#ibcon#read 4, iclass 33, count 2 2006.201.23:36:35.70#ibcon#about to read 5, iclass 33, count 2 2006.201.23:36:35.70#ibcon#read 5, iclass 33, count 2 2006.201.23:36:35.70#ibcon#about to read 6, iclass 33, count 2 2006.201.23:36:35.70#ibcon#read 6, iclass 33, count 2 2006.201.23:36:35.70#ibcon#end of sib2, iclass 33, count 2 2006.201.23:36:35.70#ibcon#*after write, iclass 33, count 2 2006.201.23:36:35.70#ibcon#*before return 0, iclass 33, count 2 2006.201.23:36:35.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:35.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.201.23:36:35.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.201.23:36:35.70#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:35.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:35.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:35.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:35.82#ibcon#enter wrdev, iclass 33, count 0 2006.201.23:36:35.82#ibcon#first serial, iclass 33, count 0 2006.201.23:36:35.82#ibcon#enter sib2, iclass 33, count 0 2006.201.23:36:35.82#ibcon#flushed, iclass 33, count 0 2006.201.23:36:35.82#ibcon#about to write, iclass 33, count 0 2006.201.23:36:35.82#ibcon#wrote, iclass 33, count 0 2006.201.23:36:35.82#ibcon#about to read 3, iclass 33, count 0 2006.201.23:36:35.84#ibcon#read 3, iclass 33, count 0 2006.201.23:36:35.84#ibcon#about to read 4, iclass 33, count 0 2006.201.23:36:35.84#ibcon#read 4, iclass 33, count 0 2006.201.23:36:35.84#ibcon#about to read 5, iclass 33, count 0 2006.201.23:36:35.84#ibcon#read 5, iclass 33, count 0 2006.201.23:36:35.84#ibcon#about to read 6, iclass 33, count 0 2006.201.23:36:35.84#ibcon#read 6, iclass 33, count 0 2006.201.23:36:35.84#ibcon#end of sib2, iclass 33, count 0 2006.201.23:36:35.84#ibcon#*mode == 0, iclass 33, count 0 2006.201.23:36:35.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.23:36:35.84#ibcon#[27=USB\r\n] 2006.201.23:36:35.84#ibcon#*before write, iclass 33, count 0 2006.201.23:36:35.84#ibcon#enter sib2, iclass 33, count 0 2006.201.23:36:35.84#ibcon#flushed, iclass 33, count 0 2006.201.23:36:35.84#ibcon#about to write, iclass 33, count 0 2006.201.23:36:35.84#ibcon#wrote, iclass 33, count 0 2006.201.23:36:35.84#ibcon#about to read 3, iclass 33, count 0 2006.201.23:36:35.87#ibcon#read 3, iclass 33, count 0 2006.201.23:36:35.87#ibcon#about to read 4, iclass 33, count 0 2006.201.23:36:35.87#ibcon#read 4, iclass 33, count 0 2006.201.23:36:35.87#ibcon#about to read 5, iclass 33, count 0 2006.201.23:36:35.87#ibcon#read 5, iclass 33, count 0 2006.201.23:36:35.87#ibcon#about to read 6, iclass 33, count 0 2006.201.23:36:35.87#ibcon#read 6, iclass 33, count 0 2006.201.23:36:35.87#ibcon#end of sib2, iclass 33, count 0 2006.201.23:36:35.87#ibcon#*after write, iclass 33, count 0 2006.201.23:36:35.87#ibcon#*before return 0, iclass 33, count 0 2006.201.23:36:35.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:35.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.201.23:36:35.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.23:36:35.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.23:36:35.87$vck44/vblo=6,719.99 2006.201.23:36:35.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.201.23:36:35.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.201.23:36:35.87#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:35.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:35.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:35.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:35.87#ibcon#enter wrdev, iclass 35, count 0 2006.201.23:36:35.87#ibcon#first serial, iclass 35, count 0 2006.201.23:36:35.87#ibcon#enter sib2, iclass 35, count 0 2006.201.23:36:35.87#ibcon#flushed, iclass 35, count 0 2006.201.23:36:35.87#ibcon#about to write, iclass 35, count 0 2006.201.23:36:35.87#ibcon#wrote, iclass 35, count 0 2006.201.23:36:35.87#ibcon#about to read 3, iclass 35, count 0 2006.201.23:36:35.89#ibcon#read 3, iclass 35, count 0 2006.201.23:36:35.89#ibcon#about to read 4, iclass 35, count 0 2006.201.23:36:35.89#ibcon#read 4, iclass 35, count 0 2006.201.23:36:35.89#ibcon#about to read 5, iclass 35, count 0 2006.201.23:36:35.89#ibcon#read 5, iclass 35, count 0 2006.201.23:36:35.89#ibcon#about to read 6, iclass 35, count 0 2006.201.23:36:35.89#ibcon#read 6, iclass 35, count 0 2006.201.23:36:35.89#ibcon#end of sib2, iclass 35, count 0 2006.201.23:36:35.89#ibcon#*mode == 0, iclass 35, count 0 2006.201.23:36:35.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.23:36:35.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.23:36:35.89#ibcon#*before write, iclass 35, count 0 2006.201.23:36:35.89#ibcon#enter sib2, iclass 35, count 0 2006.201.23:36:35.89#ibcon#flushed, iclass 35, count 0 2006.201.23:36:35.89#ibcon#about to write, iclass 35, count 0 2006.201.23:36:35.89#ibcon#wrote, iclass 35, count 0 2006.201.23:36:35.89#ibcon#about to read 3, iclass 35, count 0 2006.201.23:36:35.93#ibcon#read 3, iclass 35, count 0 2006.201.23:36:35.93#ibcon#about to read 4, iclass 35, count 0 2006.201.23:36:35.93#ibcon#read 4, iclass 35, count 0 2006.201.23:36:35.93#ibcon#about to read 5, iclass 35, count 0 2006.201.23:36:35.93#ibcon#read 5, iclass 35, count 0 2006.201.23:36:35.93#ibcon#about to read 6, iclass 35, count 0 2006.201.23:36:35.93#ibcon#read 6, iclass 35, count 0 2006.201.23:36:35.93#ibcon#end of sib2, iclass 35, count 0 2006.201.23:36:35.93#ibcon#*after write, iclass 35, count 0 2006.201.23:36:35.93#ibcon#*before return 0, iclass 35, count 0 2006.201.23:36:35.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:35.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.201.23:36:35.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.23:36:35.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.23:36:35.93$vck44/vb=6,4 2006.201.23:36:35.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.201.23:36:35.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.201.23:36:35.93#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:35.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:35.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:35.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:35.99#ibcon#enter wrdev, iclass 37, count 2 2006.201.23:36:35.99#ibcon#first serial, iclass 37, count 2 2006.201.23:36:35.99#ibcon#enter sib2, iclass 37, count 2 2006.201.23:36:35.99#ibcon#flushed, iclass 37, count 2 2006.201.23:36:35.99#ibcon#about to write, iclass 37, count 2 2006.201.23:36:35.99#ibcon#wrote, iclass 37, count 2 2006.201.23:36:35.99#ibcon#about to read 3, iclass 37, count 2 2006.201.23:36:36.01#ibcon#read 3, iclass 37, count 2 2006.201.23:36:36.01#ibcon#about to read 4, iclass 37, count 2 2006.201.23:36:36.01#ibcon#read 4, iclass 37, count 2 2006.201.23:36:36.01#ibcon#about to read 5, iclass 37, count 2 2006.201.23:36:36.01#ibcon#read 5, iclass 37, count 2 2006.201.23:36:36.01#ibcon#about to read 6, iclass 37, count 2 2006.201.23:36:36.01#ibcon#read 6, iclass 37, count 2 2006.201.23:36:36.01#ibcon#end of sib2, iclass 37, count 2 2006.201.23:36:36.01#ibcon#*mode == 0, iclass 37, count 2 2006.201.23:36:36.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.201.23:36:36.01#ibcon#[27=AT06-04\r\n] 2006.201.23:36:36.01#ibcon#*before write, iclass 37, count 2 2006.201.23:36:36.01#ibcon#enter sib2, iclass 37, count 2 2006.201.23:36:36.01#ibcon#flushed, iclass 37, count 2 2006.201.23:36:36.01#ibcon#about to write, iclass 37, count 2 2006.201.23:36:36.01#ibcon#wrote, iclass 37, count 2 2006.201.23:36:36.01#ibcon#about to read 3, iclass 37, count 2 2006.201.23:36:36.04#ibcon#read 3, iclass 37, count 2 2006.201.23:36:36.04#ibcon#about to read 4, iclass 37, count 2 2006.201.23:36:36.04#ibcon#read 4, iclass 37, count 2 2006.201.23:36:36.04#ibcon#about to read 5, iclass 37, count 2 2006.201.23:36:36.04#ibcon#read 5, iclass 37, count 2 2006.201.23:36:36.04#ibcon#about to read 6, iclass 37, count 2 2006.201.23:36:36.04#ibcon#read 6, iclass 37, count 2 2006.201.23:36:36.04#ibcon#end of sib2, iclass 37, count 2 2006.201.23:36:36.04#ibcon#*after write, iclass 37, count 2 2006.201.23:36:36.04#ibcon#*before return 0, iclass 37, count 2 2006.201.23:36:36.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:36.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.201.23:36:36.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.201.23:36:36.04#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:36.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:36.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:36.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:36.16#ibcon#enter wrdev, iclass 37, count 0 2006.201.23:36:36.16#ibcon#first serial, iclass 37, count 0 2006.201.23:36:36.16#ibcon#enter sib2, iclass 37, count 0 2006.201.23:36:36.16#ibcon#flushed, iclass 37, count 0 2006.201.23:36:36.16#ibcon#about to write, iclass 37, count 0 2006.201.23:36:36.16#ibcon#wrote, iclass 37, count 0 2006.201.23:36:36.16#ibcon#about to read 3, iclass 37, count 0 2006.201.23:36:36.18#ibcon#read 3, iclass 37, count 0 2006.201.23:36:36.18#ibcon#about to read 4, iclass 37, count 0 2006.201.23:36:36.18#ibcon#read 4, iclass 37, count 0 2006.201.23:36:36.18#ibcon#about to read 5, iclass 37, count 0 2006.201.23:36:36.18#ibcon#read 5, iclass 37, count 0 2006.201.23:36:36.18#ibcon#about to read 6, iclass 37, count 0 2006.201.23:36:36.18#ibcon#read 6, iclass 37, count 0 2006.201.23:36:36.18#ibcon#end of sib2, iclass 37, count 0 2006.201.23:36:36.18#ibcon#*mode == 0, iclass 37, count 0 2006.201.23:36:36.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.23:36:36.18#ibcon#[27=USB\r\n] 2006.201.23:36:36.18#ibcon#*before write, iclass 37, count 0 2006.201.23:36:36.18#ibcon#enter sib2, iclass 37, count 0 2006.201.23:36:36.18#ibcon#flushed, iclass 37, count 0 2006.201.23:36:36.18#ibcon#about to write, iclass 37, count 0 2006.201.23:36:36.18#ibcon#wrote, iclass 37, count 0 2006.201.23:36:36.18#ibcon#about to read 3, iclass 37, count 0 2006.201.23:36:36.21#ibcon#read 3, iclass 37, count 0 2006.201.23:36:36.21#ibcon#about to read 4, iclass 37, count 0 2006.201.23:36:36.21#ibcon#read 4, iclass 37, count 0 2006.201.23:36:36.21#ibcon#about to read 5, iclass 37, count 0 2006.201.23:36:36.21#ibcon#read 5, iclass 37, count 0 2006.201.23:36:36.21#ibcon#about to read 6, iclass 37, count 0 2006.201.23:36:36.21#ibcon#read 6, iclass 37, count 0 2006.201.23:36:36.21#ibcon#end of sib2, iclass 37, count 0 2006.201.23:36:36.21#ibcon#*after write, iclass 37, count 0 2006.201.23:36:36.21#ibcon#*before return 0, iclass 37, count 0 2006.201.23:36:36.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:36.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.201.23:36:36.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.23:36:36.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.23:36:36.21$vck44/vblo=7,734.99 2006.201.23:36:36.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.201.23:36:36.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.201.23:36:36.21#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:36.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:36.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:36.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:36.21#ibcon#enter wrdev, iclass 39, count 0 2006.201.23:36:36.21#ibcon#first serial, iclass 39, count 0 2006.201.23:36:36.21#ibcon#enter sib2, iclass 39, count 0 2006.201.23:36:36.21#ibcon#flushed, iclass 39, count 0 2006.201.23:36:36.21#ibcon#about to write, iclass 39, count 0 2006.201.23:36:36.21#ibcon#wrote, iclass 39, count 0 2006.201.23:36:36.21#ibcon#about to read 3, iclass 39, count 0 2006.201.23:36:36.23#ibcon#read 3, iclass 39, count 0 2006.201.23:36:36.23#ibcon#about to read 4, iclass 39, count 0 2006.201.23:36:36.23#ibcon#read 4, iclass 39, count 0 2006.201.23:36:36.23#ibcon#about to read 5, iclass 39, count 0 2006.201.23:36:36.23#ibcon#read 5, iclass 39, count 0 2006.201.23:36:36.23#ibcon#about to read 6, iclass 39, count 0 2006.201.23:36:36.23#ibcon#read 6, iclass 39, count 0 2006.201.23:36:36.23#ibcon#end of sib2, iclass 39, count 0 2006.201.23:36:36.23#ibcon#*mode == 0, iclass 39, count 0 2006.201.23:36:36.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.23:36:36.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.23:36:36.23#ibcon#*before write, iclass 39, count 0 2006.201.23:36:36.23#ibcon#enter sib2, iclass 39, count 0 2006.201.23:36:36.23#ibcon#flushed, iclass 39, count 0 2006.201.23:36:36.23#ibcon#about to write, iclass 39, count 0 2006.201.23:36:36.23#ibcon#wrote, iclass 39, count 0 2006.201.23:36:36.23#ibcon#about to read 3, iclass 39, count 0 2006.201.23:36:36.27#ibcon#read 3, iclass 39, count 0 2006.201.23:36:36.27#ibcon#about to read 4, iclass 39, count 0 2006.201.23:36:36.27#ibcon#read 4, iclass 39, count 0 2006.201.23:36:36.27#ibcon#about to read 5, iclass 39, count 0 2006.201.23:36:36.27#ibcon#read 5, iclass 39, count 0 2006.201.23:36:36.27#ibcon#about to read 6, iclass 39, count 0 2006.201.23:36:36.27#ibcon#read 6, iclass 39, count 0 2006.201.23:36:36.27#ibcon#end of sib2, iclass 39, count 0 2006.201.23:36:36.27#ibcon#*after write, iclass 39, count 0 2006.201.23:36:36.27#ibcon#*before return 0, iclass 39, count 0 2006.201.23:36:36.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:36.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.201.23:36:36.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.23:36:36.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.23:36:36.27$vck44/vb=7,4 2006.201.23:36:36.27#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.201.23:36:36.27#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.201.23:36:36.27#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:36.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:36.33#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:36.33#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:36.33#ibcon#enter wrdev, iclass 2, count 2 2006.201.23:36:36.33#ibcon#first serial, iclass 2, count 2 2006.201.23:36:36.33#ibcon#enter sib2, iclass 2, count 2 2006.201.23:36:36.33#ibcon#flushed, iclass 2, count 2 2006.201.23:36:36.33#ibcon#about to write, iclass 2, count 2 2006.201.23:36:36.33#ibcon#wrote, iclass 2, count 2 2006.201.23:36:36.33#ibcon#about to read 3, iclass 2, count 2 2006.201.23:36:36.35#ibcon#read 3, iclass 2, count 2 2006.201.23:36:36.35#ibcon#about to read 4, iclass 2, count 2 2006.201.23:36:36.35#ibcon#read 4, iclass 2, count 2 2006.201.23:36:36.35#ibcon#about to read 5, iclass 2, count 2 2006.201.23:36:36.35#ibcon#read 5, iclass 2, count 2 2006.201.23:36:36.35#ibcon#about to read 6, iclass 2, count 2 2006.201.23:36:36.35#ibcon#read 6, iclass 2, count 2 2006.201.23:36:36.35#ibcon#end of sib2, iclass 2, count 2 2006.201.23:36:36.35#ibcon#*mode == 0, iclass 2, count 2 2006.201.23:36:36.35#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.201.23:36:36.35#ibcon#[27=AT07-04\r\n] 2006.201.23:36:36.35#ibcon#*before write, iclass 2, count 2 2006.201.23:36:36.35#ibcon#enter sib2, iclass 2, count 2 2006.201.23:36:36.35#ibcon#flushed, iclass 2, count 2 2006.201.23:36:36.35#ibcon#about to write, iclass 2, count 2 2006.201.23:36:36.35#ibcon#wrote, iclass 2, count 2 2006.201.23:36:36.35#ibcon#about to read 3, iclass 2, count 2 2006.201.23:36:36.38#ibcon#read 3, iclass 2, count 2 2006.201.23:36:36.38#ibcon#about to read 4, iclass 2, count 2 2006.201.23:36:36.38#ibcon#read 4, iclass 2, count 2 2006.201.23:36:36.38#ibcon#about to read 5, iclass 2, count 2 2006.201.23:36:36.38#ibcon#read 5, iclass 2, count 2 2006.201.23:36:36.38#ibcon#about to read 6, iclass 2, count 2 2006.201.23:36:36.38#ibcon#read 6, iclass 2, count 2 2006.201.23:36:36.38#ibcon#end of sib2, iclass 2, count 2 2006.201.23:36:36.38#ibcon#*after write, iclass 2, count 2 2006.201.23:36:36.38#ibcon#*before return 0, iclass 2, count 2 2006.201.23:36:36.38#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:36.38#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.201.23:36:36.38#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.201.23:36:36.38#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:36.38#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:36.50#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:36.50#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:36.50#ibcon#enter wrdev, iclass 2, count 0 2006.201.23:36:36.50#ibcon#first serial, iclass 2, count 0 2006.201.23:36:36.50#ibcon#enter sib2, iclass 2, count 0 2006.201.23:36:36.50#ibcon#flushed, iclass 2, count 0 2006.201.23:36:36.50#ibcon#about to write, iclass 2, count 0 2006.201.23:36:36.50#ibcon#wrote, iclass 2, count 0 2006.201.23:36:36.50#ibcon#about to read 3, iclass 2, count 0 2006.201.23:36:36.52#ibcon#read 3, iclass 2, count 0 2006.201.23:36:36.52#ibcon#about to read 4, iclass 2, count 0 2006.201.23:36:36.52#ibcon#read 4, iclass 2, count 0 2006.201.23:36:36.52#ibcon#about to read 5, iclass 2, count 0 2006.201.23:36:36.52#ibcon#read 5, iclass 2, count 0 2006.201.23:36:36.52#ibcon#about to read 6, iclass 2, count 0 2006.201.23:36:36.52#ibcon#read 6, iclass 2, count 0 2006.201.23:36:36.52#ibcon#end of sib2, iclass 2, count 0 2006.201.23:36:36.52#ibcon#*mode == 0, iclass 2, count 0 2006.201.23:36:36.52#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.23:36:36.52#ibcon#[27=USB\r\n] 2006.201.23:36:36.52#ibcon#*before write, iclass 2, count 0 2006.201.23:36:36.52#ibcon#enter sib2, iclass 2, count 0 2006.201.23:36:36.52#ibcon#flushed, iclass 2, count 0 2006.201.23:36:36.52#ibcon#about to write, iclass 2, count 0 2006.201.23:36:36.52#ibcon#wrote, iclass 2, count 0 2006.201.23:36:36.52#ibcon#about to read 3, iclass 2, count 0 2006.201.23:36:36.55#ibcon#read 3, iclass 2, count 0 2006.201.23:36:36.55#ibcon#about to read 4, iclass 2, count 0 2006.201.23:36:36.55#ibcon#read 4, iclass 2, count 0 2006.201.23:36:36.55#ibcon#about to read 5, iclass 2, count 0 2006.201.23:36:36.55#ibcon#read 5, iclass 2, count 0 2006.201.23:36:36.55#ibcon#about to read 6, iclass 2, count 0 2006.201.23:36:36.55#ibcon#read 6, iclass 2, count 0 2006.201.23:36:36.55#ibcon#end of sib2, iclass 2, count 0 2006.201.23:36:36.55#ibcon#*after write, iclass 2, count 0 2006.201.23:36:36.55#ibcon#*before return 0, iclass 2, count 0 2006.201.23:36:36.55#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:36.55#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.201.23:36:36.55#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.23:36:36.55#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.23:36:36.55$vck44/vblo=8,744.99 2006.201.23:36:36.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.201.23:36:36.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.201.23:36:36.55#ibcon#ireg 17 cls_cnt 0 2006.201.23:36:36.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:36.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:36.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:36.55#ibcon#enter wrdev, iclass 5, count 0 2006.201.23:36:36.55#ibcon#first serial, iclass 5, count 0 2006.201.23:36:36.55#ibcon#enter sib2, iclass 5, count 0 2006.201.23:36:36.55#ibcon#flushed, iclass 5, count 0 2006.201.23:36:36.55#ibcon#about to write, iclass 5, count 0 2006.201.23:36:36.55#ibcon#wrote, iclass 5, count 0 2006.201.23:36:36.55#ibcon#about to read 3, iclass 5, count 0 2006.201.23:36:36.57#ibcon#read 3, iclass 5, count 0 2006.201.23:36:36.57#ibcon#about to read 4, iclass 5, count 0 2006.201.23:36:36.57#ibcon#read 4, iclass 5, count 0 2006.201.23:36:36.57#ibcon#about to read 5, iclass 5, count 0 2006.201.23:36:36.57#ibcon#read 5, iclass 5, count 0 2006.201.23:36:36.57#ibcon#about to read 6, iclass 5, count 0 2006.201.23:36:36.57#ibcon#read 6, iclass 5, count 0 2006.201.23:36:36.57#ibcon#end of sib2, iclass 5, count 0 2006.201.23:36:36.57#ibcon#*mode == 0, iclass 5, count 0 2006.201.23:36:36.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.23:36:36.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.23:36:36.57#ibcon#*before write, iclass 5, count 0 2006.201.23:36:36.57#ibcon#enter sib2, iclass 5, count 0 2006.201.23:36:36.57#ibcon#flushed, iclass 5, count 0 2006.201.23:36:36.57#ibcon#about to write, iclass 5, count 0 2006.201.23:36:36.57#ibcon#wrote, iclass 5, count 0 2006.201.23:36:36.57#ibcon#about to read 3, iclass 5, count 0 2006.201.23:36:36.61#ibcon#read 3, iclass 5, count 0 2006.201.23:36:36.61#ibcon#about to read 4, iclass 5, count 0 2006.201.23:36:36.61#ibcon#read 4, iclass 5, count 0 2006.201.23:36:36.61#ibcon#about to read 5, iclass 5, count 0 2006.201.23:36:36.61#ibcon#read 5, iclass 5, count 0 2006.201.23:36:36.61#ibcon#about to read 6, iclass 5, count 0 2006.201.23:36:36.61#ibcon#read 6, iclass 5, count 0 2006.201.23:36:36.61#ibcon#end of sib2, iclass 5, count 0 2006.201.23:36:36.61#ibcon#*after write, iclass 5, count 0 2006.201.23:36:36.61#ibcon#*before return 0, iclass 5, count 0 2006.201.23:36:36.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:36.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.201.23:36:36.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.23:36:36.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.23:36:36.61$vck44/vb=8,4 2006.201.23:36:36.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.201.23:36:36.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.201.23:36:36.61#ibcon#ireg 11 cls_cnt 2 2006.201.23:36:36.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:36.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:36.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:36.67#ibcon#enter wrdev, iclass 7, count 2 2006.201.23:36:36.67#ibcon#first serial, iclass 7, count 2 2006.201.23:36:36.67#ibcon#enter sib2, iclass 7, count 2 2006.201.23:36:36.67#ibcon#flushed, iclass 7, count 2 2006.201.23:36:36.67#ibcon#about to write, iclass 7, count 2 2006.201.23:36:36.67#ibcon#wrote, iclass 7, count 2 2006.201.23:36:36.67#ibcon#about to read 3, iclass 7, count 2 2006.201.23:36:36.69#ibcon#read 3, iclass 7, count 2 2006.201.23:36:36.69#ibcon#about to read 4, iclass 7, count 2 2006.201.23:36:36.69#ibcon#read 4, iclass 7, count 2 2006.201.23:36:36.69#ibcon#about to read 5, iclass 7, count 2 2006.201.23:36:36.69#ibcon#read 5, iclass 7, count 2 2006.201.23:36:36.69#ibcon#about to read 6, iclass 7, count 2 2006.201.23:36:36.69#ibcon#read 6, iclass 7, count 2 2006.201.23:36:36.69#ibcon#end of sib2, iclass 7, count 2 2006.201.23:36:36.69#ibcon#*mode == 0, iclass 7, count 2 2006.201.23:36:36.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.201.23:36:36.69#ibcon#[27=AT08-04\r\n] 2006.201.23:36:36.69#ibcon#*before write, iclass 7, count 2 2006.201.23:36:36.69#ibcon#enter sib2, iclass 7, count 2 2006.201.23:36:36.69#ibcon#flushed, iclass 7, count 2 2006.201.23:36:36.69#ibcon#about to write, iclass 7, count 2 2006.201.23:36:36.69#ibcon#wrote, iclass 7, count 2 2006.201.23:36:36.69#ibcon#about to read 3, iclass 7, count 2 2006.201.23:36:36.72#ibcon#read 3, iclass 7, count 2 2006.201.23:36:36.72#ibcon#about to read 4, iclass 7, count 2 2006.201.23:36:36.72#ibcon#read 4, iclass 7, count 2 2006.201.23:36:36.72#ibcon#about to read 5, iclass 7, count 2 2006.201.23:36:36.72#ibcon#read 5, iclass 7, count 2 2006.201.23:36:36.72#ibcon#about to read 6, iclass 7, count 2 2006.201.23:36:36.72#ibcon#read 6, iclass 7, count 2 2006.201.23:36:36.72#ibcon#end of sib2, iclass 7, count 2 2006.201.23:36:36.72#ibcon#*after write, iclass 7, count 2 2006.201.23:36:36.72#ibcon#*before return 0, iclass 7, count 2 2006.201.23:36:36.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:36.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.201.23:36:36.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.201.23:36:36.72#ibcon#ireg 7 cls_cnt 0 2006.201.23:36:36.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:36.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:36.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:36.84#ibcon#enter wrdev, iclass 7, count 0 2006.201.23:36:36.84#ibcon#first serial, iclass 7, count 0 2006.201.23:36:36.84#ibcon#enter sib2, iclass 7, count 0 2006.201.23:36:36.84#ibcon#flushed, iclass 7, count 0 2006.201.23:36:36.84#ibcon#about to write, iclass 7, count 0 2006.201.23:36:36.84#ibcon#wrote, iclass 7, count 0 2006.201.23:36:36.84#ibcon#about to read 3, iclass 7, count 0 2006.201.23:36:36.86#ibcon#read 3, iclass 7, count 0 2006.201.23:36:36.86#ibcon#about to read 4, iclass 7, count 0 2006.201.23:36:36.86#ibcon#read 4, iclass 7, count 0 2006.201.23:36:36.86#ibcon#about to read 5, iclass 7, count 0 2006.201.23:36:36.86#ibcon#read 5, iclass 7, count 0 2006.201.23:36:36.86#ibcon#about to read 6, iclass 7, count 0 2006.201.23:36:36.86#ibcon#read 6, iclass 7, count 0 2006.201.23:36:36.86#ibcon#end of sib2, iclass 7, count 0 2006.201.23:36:36.86#ibcon#*mode == 0, iclass 7, count 0 2006.201.23:36:36.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.23:36:36.86#ibcon#[27=USB\r\n] 2006.201.23:36:36.86#ibcon#*before write, iclass 7, count 0 2006.201.23:36:36.86#ibcon#enter sib2, iclass 7, count 0 2006.201.23:36:36.86#ibcon#flushed, iclass 7, count 0 2006.201.23:36:36.86#ibcon#about to write, iclass 7, count 0 2006.201.23:36:36.86#ibcon#wrote, iclass 7, count 0 2006.201.23:36:36.86#ibcon#about to read 3, iclass 7, count 0 2006.201.23:36:36.89#ibcon#read 3, iclass 7, count 0 2006.201.23:36:36.89#ibcon#about to read 4, iclass 7, count 0 2006.201.23:36:36.89#ibcon#read 4, iclass 7, count 0 2006.201.23:36:36.89#ibcon#about to read 5, iclass 7, count 0 2006.201.23:36:36.89#ibcon#read 5, iclass 7, count 0 2006.201.23:36:36.89#ibcon#about to read 6, iclass 7, count 0 2006.201.23:36:36.89#ibcon#read 6, iclass 7, count 0 2006.201.23:36:36.89#ibcon#end of sib2, iclass 7, count 0 2006.201.23:36:36.89#ibcon#*after write, iclass 7, count 0 2006.201.23:36:36.89#ibcon#*before return 0, iclass 7, count 0 2006.201.23:36:36.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:36.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.201.23:36:36.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.23:36:36.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.23:36:36.89$vck44/vabw=wide 2006.201.23:36:36.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.201.23:36:36.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.201.23:36:36.89#ibcon#ireg 8 cls_cnt 0 2006.201.23:36:36.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:36.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:36.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:36.89#ibcon#enter wrdev, iclass 11, count 0 2006.201.23:36:36.89#ibcon#first serial, iclass 11, count 0 2006.201.23:36:36.89#ibcon#enter sib2, iclass 11, count 0 2006.201.23:36:36.89#ibcon#flushed, iclass 11, count 0 2006.201.23:36:36.89#ibcon#about to write, iclass 11, count 0 2006.201.23:36:36.89#ibcon#wrote, iclass 11, count 0 2006.201.23:36:36.89#ibcon#about to read 3, iclass 11, count 0 2006.201.23:36:36.91#ibcon#read 3, iclass 11, count 0 2006.201.23:36:36.91#ibcon#about to read 4, iclass 11, count 0 2006.201.23:36:36.91#ibcon#read 4, iclass 11, count 0 2006.201.23:36:36.91#ibcon#about to read 5, iclass 11, count 0 2006.201.23:36:36.91#ibcon#read 5, iclass 11, count 0 2006.201.23:36:36.91#ibcon#about to read 6, iclass 11, count 0 2006.201.23:36:36.91#ibcon#read 6, iclass 11, count 0 2006.201.23:36:36.91#ibcon#end of sib2, iclass 11, count 0 2006.201.23:36:36.91#ibcon#*mode == 0, iclass 11, count 0 2006.201.23:36:36.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.23:36:36.91#ibcon#[25=BW32\r\n] 2006.201.23:36:36.91#ibcon#*before write, iclass 11, count 0 2006.201.23:36:36.91#ibcon#enter sib2, iclass 11, count 0 2006.201.23:36:36.91#ibcon#flushed, iclass 11, count 0 2006.201.23:36:36.91#ibcon#about to write, iclass 11, count 0 2006.201.23:36:36.91#ibcon#wrote, iclass 11, count 0 2006.201.23:36:36.91#ibcon#about to read 3, iclass 11, count 0 2006.201.23:36:36.94#ibcon#read 3, iclass 11, count 0 2006.201.23:36:36.94#ibcon#about to read 4, iclass 11, count 0 2006.201.23:36:36.94#ibcon#read 4, iclass 11, count 0 2006.201.23:36:36.94#ibcon#about to read 5, iclass 11, count 0 2006.201.23:36:36.94#ibcon#read 5, iclass 11, count 0 2006.201.23:36:36.94#ibcon#about to read 6, iclass 11, count 0 2006.201.23:36:36.94#ibcon#read 6, iclass 11, count 0 2006.201.23:36:36.94#ibcon#end of sib2, iclass 11, count 0 2006.201.23:36:36.94#ibcon#*after write, iclass 11, count 0 2006.201.23:36:36.94#ibcon#*before return 0, iclass 11, count 0 2006.201.23:36:36.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:36.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.201.23:36:36.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.23:36:36.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.23:36:36.94$vck44/vbbw=wide 2006.201.23:36:36.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.23:36:36.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.23:36:36.94#ibcon#ireg 8 cls_cnt 0 2006.201.23:36:36.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:36:37.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:36:37.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:36:37.01#ibcon#enter wrdev, iclass 13, count 0 2006.201.23:36:37.01#ibcon#first serial, iclass 13, count 0 2006.201.23:36:37.01#ibcon#enter sib2, iclass 13, count 0 2006.201.23:36:37.01#ibcon#flushed, iclass 13, count 0 2006.201.23:36:37.01#ibcon#about to write, iclass 13, count 0 2006.201.23:36:37.01#ibcon#wrote, iclass 13, count 0 2006.201.23:36:37.01#ibcon#about to read 3, iclass 13, count 0 2006.201.23:36:37.03#ibcon#read 3, iclass 13, count 0 2006.201.23:36:37.03#ibcon#about to read 4, iclass 13, count 0 2006.201.23:36:37.03#ibcon#read 4, iclass 13, count 0 2006.201.23:36:37.03#ibcon#about to read 5, iclass 13, count 0 2006.201.23:36:37.03#ibcon#read 5, iclass 13, count 0 2006.201.23:36:37.03#ibcon#about to read 6, iclass 13, count 0 2006.201.23:36:37.03#ibcon#read 6, iclass 13, count 0 2006.201.23:36:37.03#ibcon#end of sib2, iclass 13, count 0 2006.201.23:36:37.03#ibcon#*mode == 0, iclass 13, count 0 2006.201.23:36:37.03#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.23:36:37.03#ibcon#[27=BW32\r\n] 2006.201.23:36:37.03#ibcon#*before write, iclass 13, count 0 2006.201.23:36:37.03#ibcon#enter sib2, iclass 13, count 0 2006.201.23:36:37.03#ibcon#flushed, iclass 13, count 0 2006.201.23:36:37.03#ibcon#about to write, iclass 13, count 0 2006.201.23:36:37.03#ibcon#wrote, iclass 13, count 0 2006.201.23:36:37.03#ibcon#about to read 3, iclass 13, count 0 2006.201.23:36:37.06#ibcon#read 3, iclass 13, count 0 2006.201.23:36:37.06#ibcon#about to read 4, iclass 13, count 0 2006.201.23:36:37.06#ibcon#read 4, iclass 13, count 0 2006.201.23:36:37.06#ibcon#about to read 5, iclass 13, count 0 2006.201.23:36:37.06#ibcon#read 5, iclass 13, count 0 2006.201.23:36:37.06#ibcon#about to read 6, iclass 13, count 0 2006.201.23:36:37.06#ibcon#read 6, iclass 13, count 0 2006.201.23:36:37.06#ibcon#end of sib2, iclass 13, count 0 2006.201.23:36:37.06#ibcon#*after write, iclass 13, count 0 2006.201.23:36:37.06#ibcon#*before return 0, iclass 13, count 0 2006.201.23:36:37.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:36:37.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:36:37.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.23:36:37.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.23:36:37.06$setupk4/ifdk4 2006.201.23:36:37.06$ifdk4/lo= 2006.201.23:36:37.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.23:36:37.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.23:36:37.06$ifdk4/patch= 2006.201.23:36:37.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.23:36:37.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.23:36:37.06$setupk4/!*+20s 2006.201.23:36:38.72#abcon#<5=/04 0.9 2.0 20.281001001.5\r\n> 2006.201.23:36:38.74#abcon#{5=INTERFACE CLEAR} 2006.201.23:36:38.80#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:36:48.89#abcon#<5=/04 0.9 2.0 20.281001001.5\r\n> 2006.201.23:36:48.91#abcon#{5=INTERFACE CLEAR} 2006.201.23:36:48.97#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:36:51.57$setupk4/"tpicd 2006.201.23:36:51.57$setupk4/echo=off 2006.201.23:36:51.57$setupk4/xlog=off 2006.201.23:36:51.57:!2006.201.23:40:21 2006.201.23:37:30.14#trakl#Source acquired 2006.201.23:37:30.14#flagr#flagr/antenna,acquired 2006.201.23:40:21.00:preob 2006.201.23:40:22.13/onsource/TRACKING 2006.201.23:40:22.13:!2006.201.23:40:31 2006.201.23:40:31.00:"tape 2006.201.23:40:31.00:"st=record 2006.201.23:40:31.00:data_valid=on 2006.201.23:40:31.00:midob 2006.201.23:40:31.13/onsource/TRACKING 2006.201.23:40:31.13/wx/20.31,1001.6,100 2006.201.23:40:31.24/cable/+6.4843E-03 2006.201.23:40:32.33/va/01,08,usb,yes,47,50 2006.201.23:40:32.33/va/02,07,usb,yes,50,51 2006.201.23:40:32.33/va/03,08,usb,yes,46,48 2006.201.23:40:32.33/va/04,07,usb,yes,52,55 2006.201.23:40:32.33/va/05,04,usb,yes,46,47 2006.201.23:40:32.33/va/06,05,usb,yes,47,47 2006.201.23:40:32.33/va/07,05,usb,yes,46,47 2006.201.23:40:32.33/va/08,04,usb,yes,45,53 2006.201.23:40:32.56/valo/01,524.99,yes,locked 2006.201.23:40:32.56/valo/02,534.99,yes,locked 2006.201.23:40:32.56/valo/03,564.99,yes,locked 2006.201.23:40:32.56/valo/04,624.99,yes,locked 2006.201.23:40:32.56/valo/05,734.99,yes,locked 2006.201.23:40:32.56/valo/06,814.99,yes,locked 2006.201.23:40:32.56/valo/07,864.99,yes,locked 2006.201.23:40:32.56/valo/08,884.99,yes,locked 2006.201.23:40:33.65/vb/01,04,usb,yes,30,28 2006.201.23:40:33.65/vb/02,05,usb,yes,28,28 2006.201.23:40:33.65/vb/03,04,usb,yes,29,32 2006.201.23:40:33.65/vb/04,05,usb,yes,30,29 2006.201.23:40:33.65/vb/05,04,usb,yes,26,29 2006.201.23:40:33.65/vb/06,04,usb,yes,31,27 2006.201.23:40:33.65/vb/07,04,usb,yes,30,30 2006.201.23:40:33.65/vb/08,04,usb,yes,28,31 2006.201.23:40:33.89/vblo/01,629.99,yes,locked 2006.201.23:40:33.89/vblo/02,634.99,yes,locked 2006.201.23:40:33.89/vblo/03,649.99,yes,locked 2006.201.23:40:33.89/vblo/04,679.99,yes,locked 2006.201.23:40:33.89/vblo/05,709.99,yes,locked 2006.201.23:40:33.89/vblo/06,719.99,yes,locked 2006.201.23:40:33.89/vblo/07,734.99,yes,locked 2006.201.23:40:33.89/vblo/08,744.99,yes,locked 2006.201.23:40:34.04/vabw/8 2006.201.23:40:34.19/vbbw/8 2006.201.23:40:34.28/xfe/off,on,15.2 2006.201.23:40:34.66/ifatt/23,28,28,28 2006.201.23:40:35.07/fmout-gps/S +4.56E-07 2006.201.23:40:35.11:!2006.201.23:42:01 2006.201.23:42:01.00:data_valid=off 2006.201.23:42:01.00:"et 2006.201.23:42:01.00:!+3s 2006.201.23:42:04.02:"tape 2006.201.23:42:04.02:postob 2006.201.23:42:04.22/cable/+6.4846E-03 2006.201.23:42:04.22/wx/20.33,1001.7,100 2006.201.23:42:04.28/fmout-gps/S +4.57E-07 2006.201.23:42:04.28:scan_name=201-2344,jd0607,60 2006.201.23:42:04.28:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.201.23:42:05.13#flagr#flagr/antenna,new-source 2006.201.23:42:05.13:checkk5 2006.201.23:42:05.49/chk_autoobs//k5ts1/ autoobs is running! 2006.201.23:42:05.85/chk_autoobs//k5ts2/ autoobs is running! 2006.201.23:42:06.21/chk_autoobs//k5ts3/ autoobs is running! 2006.201.23:42:06.55/chk_autoobs//k5ts4/ autoobs is running! 2006.201.23:42:06.89/chk_obsdata//k5ts1/T2012340??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.23:42:07.23/chk_obsdata//k5ts2/T2012340??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.23:42:07.57/chk_obsdata//k5ts3/T2012340??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.23:42:07.92/chk_obsdata//k5ts4/T2012340??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.201.23:42:08.58/k5log//k5ts1_log_newline 2006.201.23:42:09.24/k5log//k5ts2_log_newline 2006.201.23:42:09.90/k5log//k5ts3_log_newline 2006.201.23:42:10.56/k5log//k5ts4_log_newline 2006.201.23:42:10.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.23:42:10.59:setupk4=1 2006.201.23:42:10.59$setupk4/echo=on 2006.201.23:42:10.59$setupk4/pcalon 2006.201.23:42:10.59$pcalon/"no phase cal control is implemented here 2006.201.23:42:10.59$setupk4/"tpicd=stop 2006.201.23:42:10.59$setupk4/"rec=synch_on 2006.201.23:42:10.59$setupk4/"rec_mode=128 2006.201.23:42:10.59$setupk4/!* 2006.201.23:42:10.59$setupk4/recpk4 2006.201.23:42:10.59$recpk4/recpatch= 2006.201.23:42:10.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.23:42:10.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.23:42:10.59$setupk4/vck44 2006.201.23:42:10.59$vck44/valo=1,524.99 2006.201.23:42:10.59#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.23:42:10.59#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.23:42:10.59#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:10.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:10.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:10.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:10.59#ibcon#enter wrdev, iclass 4, count 0 2006.201.23:42:10.59#ibcon#first serial, iclass 4, count 0 2006.201.23:42:10.59#ibcon#enter sib2, iclass 4, count 0 2006.201.23:42:10.59#ibcon#flushed, iclass 4, count 0 2006.201.23:42:10.59#ibcon#about to write, iclass 4, count 0 2006.201.23:42:10.59#ibcon#wrote, iclass 4, count 0 2006.201.23:42:10.59#ibcon#about to read 3, iclass 4, count 0 2006.201.23:42:10.61#ibcon#read 3, iclass 4, count 0 2006.201.23:42:10.61#ibcon#about to read 4, iclass 4, count 0 2006.201.23:42:10.61#ibcon#read 4, iclass 4, count 0 2006.201.23:42:10.61#ibcon#about to read 5, iclass 4, count 0 2006.201.23:42:10.61#ibcon#read 5, iclass 4, count 0 2006.201.23:42:10.61#ibcon#about to read 6, iclass 4, count 0 2006.201.23:42:10.61#ibcon#read 6, iclass 4, count 0 2006.201.23:42:10.61#ibcon#end of sib2, iclass 4, count 0 2006.201.23:42:10.61#ibcon#*mode == 0, iclass 4, count 0 2006.201.23:42:10.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.23:42:10.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.23:42:10.61#ibcon#*before write, iclass 4, count 0 2006.201.23:42:10.61#ibcon#enter sib2, iclass 4, count 0 2006.201.23:42:10.61#ibcon#flushed, iclass 4, count 0 2006.201.23:42:10.61#ibcon#about to write, iclass 4, count 0 2006.201.23:42:10.61#ibcon#wrote, iclass 4, count 0 2006.201.23:42:10.61#ibcon#about to read 3, iclass 4, count 0 2006.201.23:42:10.66#ibcon#read 3, iclass 4, count 0 2006.201.23:42:10.66#ibcon#about to read 4, iclass 4, count 0 2006.201.23:42:10.66#ibcon#read 4, iclass 4, count 0 2006.201.23:42:10.66#ibcon#about to read 5, iclass 4, count 0 2006.201.23:42:10.66#ibcon#read 5, iclass 4, count 0 2006.201.23:42:10.66#ibcon#about to read 6, iclass 4, count 0 2006.201.23:42:10.66#ibcon#read 6, iclass 4, count 0 2006.201.23:42:10.66#ibcon#end of sib2, iclass 4, count 0 2006.201.23:42:10.66#ibcon#*after write, iclass 4, count 0 2006.201.23:42:10.66#ibcon#*before return 0, iclass 4, count 0 2006.201.23:42:10.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:10.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:10.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.23:42:10.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.23:42:10.66$vck44/va=1,8 2006.201.23:42:10.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.23:42:10.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.23:42:10.66#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:10.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:10.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:10.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:10.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.23:42:10.66#ibcon#first serial, iclass 6, count 2 2006.201.23:42:10.66#ibcon#enter sib2, iclass 6, count 2 2006.201.23:42:10.66#ibcon#flushed, iclass 6, count 2 2006.201.23:42:10.66#ibcon#about to write, iclass 6, count 2 2006.201.23:42:10.66#ibcon#wrote, iclass 6, count 2 2006.201.23:42:10.66#ibcon#about to read 3, iclass 6, count 2 2006.201.23:42:10.68#ibcon#read 3, iclass 6, count 2 2006.201.23:42:10.68#ibcon#about to read 4, iclass 6, count 2 2006.201.23:42:10.68#ibcon#read 4, iclass 6, count 2 2006.201.23:42:10.68#ibcon#about to read 5, iclass 6, count 2 2006.201.23:42:10.68#ibcon#read 5, iclass 6, count 2 2006.201.23:42:10.68#ibcon#about to read 6, iclass 6, count 2 2006.201.23:42:10.68#ibcon#read 6, iclass 6, count 2 2006.201.23:42:10.68#ibcon#end of sib2, iclass 6, count 2 2006.201.23:42:10.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.23:42:10.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.23:42:10.68#ibcon#[25=AT01-08\r\n] 2006.201.23:42:10.68#ibcon#*before write, iclass 6, count 2 2006.201.23:42:10.68#ibcon#enter sib2, iclass 6, count 2 2006.201.23:42:10.68#ibcon#flushed, iclass 6, count 2 2006.201.23:42:10.68#ibcon#about to write, iclass 6, count 2 2006.201.23:42:10.68#ibcon#wrote, iclass 6, count 2 2006.201.23:42:10.68#ibcon#about to read 3, iclass 6, count 2 2006.201.23:42:10.71#ibcon#read 3, iclass 6, count 2 2006.201.23:42:10.71#ibcon#about to read 4, iclass 6, count 2 2006.201.23:42:10.71#ibcon#read 4, iclass 6, count 2 2006.201.23:42:10.71#ibcon#about to read 5, iclass 6, count 2 2006.201.23:42:10.71#ibcon#read 5, iclass 6, count 2 2006.201.23:42:10.71#ibcon#about to read 6, iclass 6, count 2 2006.201.23:42:10.71#ibcon#read 6, iclass 6, count 2 2006.201.23:42:10.71#ibcon#end of sib2, iclass 6, count 2 2006.201.23:42:10.71#ibcon#*after write, iclass 6, count 2 2006.201.23:42:10.71#ibcon#*before return 0, iclass 6, count 2 2006.201.23:42:10.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:10.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:10.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.23:42:10.71#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:10.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:10.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:10.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:10.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.23:42:10.83#ibcon#first serial, iclass 6, count 0 2006.201.23:42:10.83#ibcon#enter sib2, iclass 6, count 0 2006.201.23:42:10.83#ibcon#flushed, iclass 6, count 0 2006.201.23:42:10.83#ibcon#about to write, iclass 6, count 0 2006.201.23:42:10.83#ibcon#wrote, iclass 6, count 0 2006.201.23:42:10.83#ibcon#about to read 3, iclass 6, count 0 2006.201.23:42:10.85#ibcon#read 3, iclass 6, count 0 2006.201.23:42:10.85#ibcon#about to read 4, iclass 6, count 0 2006.201.23:42:10.85#ibcon#read 4, iclass 6, count 0 2006.201.23:42:10.85#ibcon#about to read 5, iclass 6, count 0 2006.201.23:42:10.85#ibcon#read 5, iclass 6, count 0 2006.201.23:42:10.85#ibcon#about to read 6, iclass 6, count 0 2006.201.23:42:10.85#ibcon#read 6, iclass 6, count 0 2006.201.23:42:10.85#ibcon#end of sib2, iclass 6, count 0 2006.201.23:42:10.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.23:42:10.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.23:42:10.85#ibcon#[25=USB\r\n] 2006.201.23:42:10.85#ibcon#*before write, iclass 6, count 0 2006.201.23:42:10.85#ibcon#enter sib2, iclass 6, count 0 2006.201.23:42:10.85#ibcon#flushed, iclass 6, count 0 2006.201.23:42:10.85#ibcon#about to write, iclass 6, count 0 2006.201.23:42:10.85#ibcon#wrote, iclass 6, count 0 2006.201.23:42:10.85#ibcon#about to read 3, iclass 6, count 0 2006.201.23:42:10.88#ibcon#read 3, iclass 6, count 0 2006.201.23:42:10.88#ibcon#about to read 4, iclass 6, count 0 2006.201.23:42:10.88#ibcon#read 4, iclass 6, count 0 2006.201.23:42:10.88#ibcon#about to read 5, iclass 6, count 0 2006.201.23:42:10.88#ibcon#read 5, iclass 6, count 0 2006.201.23:42:10.88#ibcon#about to read 6, iclass 6, count 0 2006.201.23:42:10.88#ibcon#read 6, iclass 6, count 0 2006.201.23:42:10.88#ibcon#end of sib2, iclass 6, count 0 2006.201.23:42:10.88#ibcon#*after write, iclass 6, count 0 2006.201.23:42:10.88#ibcon#*before return 0, iclass 6, count 0 2006.201.23:42:10.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:10.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:10.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.23:42:10.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.23:42:10.88$vck44/valo=2,534.99 2006.201.23:42:10.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.23:42:10.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.23:42:10.88#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:10.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:10.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:10.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:10.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.23:42:10.88#ibcon#first serial, iclass 10, count 0 2006.201.23:42:10.88#ibcon#enter sib2, iclass 10, count 0 2006.201.23:42:10.88#ibcon#flushed, iclass 10, count 0 2006.201.23:42:10.88#ibcon#about to write, iclass 10, count 0 2006.201.23:42:10.88#ibcon#wrote, iclass 10, count 0 2006.201.23:42:10.88#ibcon#about to read 3, iclass 10, count 0 2006.201.23:42:10.90#ibcon#read 3, iclass 10, count 0 2006.201.23:42:10.90#ibcon#about to read 4, iclass 10, count 0 2006.201.23:42:10.90#ibcon#read 4, iclass 10, count 0 2006.201.23:42:10.90#ibcon#about to read 5, iclass 10, count 0 2006.201.23:42:10.90#ibcon#read 5, iclass 10, count 0 2006.201.23:42:10.90#ibcon#about to read 6, iclass 10, count 0 2006.201.23:42:10.90#ibcon#read 6, iclass 10, count 0 2006.201.23:42:10.90#ibcon#end of sib2, iclass 10, count 0 2006.201.23:42:10.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.23:42:10.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.23:42:10.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.23:42:10.90#ibcon#*before write, iclass 10, count 0 2006.201.23:42:10.90#ibcon#enter sib2, iclass 10, count 0 2006.201.23:42:10.90#ibcon#flushed, iclass 10, count 0 2006.201.23:42:10.90#ibcon#about to write, iclass 10, count 0 2006.201.23:42:10.90#ibcon#wrote, iclass 10, count 0 2006.201.23:42:10.90#ibcon#about to read 3, iclass 10, count 0 2006.201.23:42:10.94#ibcon#read 3, iclass 10, count 0 2006.201.23:42:10.94#ibcon#about to read 4, iclass 10, count 0 2006.201.23:42:10.94#ibcon#read 4, iclass 10, count 0 2006.201.23:42:10.94#ibcon#about to read 5, iclass 10, count 0 2006.201.23:42:10.94#ibcon#read 5, iclass 10, count 0 2006.201.23:42:10.94#ibcon#about to read 6, iclass 10, count 0 2006.201.23:42:10.94#ibcon#read 6, iclass 10, count 0 2006.201.23:42:10.94#ibcon#end of sib2, iclass 10, count 0 2006.201.23:42:10.94#ibcon#*after write, iclass 10, count 0 2006.201.23:42:10.94#ibcon#*before return 0, iclass 10, count 0 2006.201.23:42:10.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:10.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:10.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.23:42:10.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.23:42:10.94$vck44/va=2,7 2006.201.23:42:10.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.23:42:10.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.23:42:10.94#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:10.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:11.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:11.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:11.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.23:42:11.00#ibcon#first serial, iclass 12, count 2 2006.201.23:42:11.00#ibcon#enter sib2, iclass 12, count 2 2006.201.23:42:11.00#ibcon#flushed, iclass 12, count 2 2006.201.23:42:11.00#ibcon#about to write, iclass 12, count 2 2006.201.23:42:11.00#ibcon#wrote, iclass 12, count 2 2006.201.23:42:11.00#ibcon#about to read 3, iclass 12, count 2 2006.201.23:42:11.02#ibcon#read 3, iclass 12, count 2 2006.201.23:42:11.02#ibcon#about to read 4, iclass 12, count 2 2006.201.23:42:11.02#ibcon#read 4, iclass 12, count 2 2006.201.23:42:11.02#ibcon#about to read 5, iclass 12, count 2 2006.201.23:42:11.02#ibcon#read 5, iclass 12, count 2 2006.201.23:42:11.02#ibcon#about to read 6, iclass 12, count 2 2006.201.23:42:11.02#ibcon#read 6, iclass 12, count 2 2006.201.23:42:11.02#ibcon#end of sib2, iclass 12, count 2 2006.201.23:42:11.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.23:42:11.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.23:42:11.02#ibcon#[25=AT02-07\r\n] 2006.201.23:42:11.02#ibcon#*before write, iclass 12, count 2 2006.201.23:42:11.02#ibcon#enter sib2, iclass 12, count 2 2006.201.23:42:11.02#ibcon#flushed, iclass 12, count 2 2006.201.23:42:11.02#ibcon#about to write, iclass 12, count 2 2006.201.23:42:11.02#ibcon#wrote, iclass 12, count 2 2006.201.23:42:11.02#ibcon#about to read 3, iclass 12, count 2 2006.201.23:42:11.05#ibcon#read 3, iclass 12, count 2 2006.201.23:42:11.05#ibcon#about to read 4, iclass 12, count 2 2006.201.23:42:11.05#ibcon#read 4, iclass 12, count 2 2006.201.23:42:11.05#ibcon#about to read 5, iclass 12, count 2 2006.201.23:42:11.05#ibcon#read 5, iclass 12, count 2 2006.201.23:42:11.05#ibcon#about to read 6, iclass 12, count 2 2006.201.23:42:11.05#ibcon#read 6, iclass 12, count 2 2006.201.23:42:11.05#ibcon#end of sib2, iclass 12, count 2 2006.201.23:42:11.05#ibcon#*after write, iclass 12, count 2 2006.201.23:42:11.05#ibcon#*before return 0, iclass 12, count 2 2006.201.23:42:11.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:11.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:11.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.23:42:11.05#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:11.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:11.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:11.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:11.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.23:42:11.17#ibcon#first serial, iclass 12, count 0 2006.201.23:42:11.17#ibcon#enter sib2, iclass 12, count 0 2006.201.23:42:11.17#ibcon#flushed, iclass 12, count 0 2006.201.23:42:11.17#ibcon#about to write, iclass 12, count 0 2006.201.23:42:11.17#ibcon#wrote, iclass 12, count 0 2006.201.23:42:11.17#ibcon#about to read 3, iclass 12, count 0 2006.201.23:42:11.19#ibcon#read 3, iclass 12, count 0 2006.201.23:42:11.19#ibcon#about to read 4, iclass 12, count 0 2006.201.23:42:11.19#ibcon#read 4, iclass 12, count 0 2006.201.23:42:11.19#ibcon#about to read 5, iclass 12, count 0 2006.201.23:42:11.19#ibcon#read 5, iclass 12, count 0 2006.201.23:42:11.19#ibcon#about to read 6, iclass 12, count 0 2006.201.23:42:11.19#ibcon#read 6, iclass 12, count 0 2006.201.23:42:11.19#ibcon#end of sib2, iclass 12, count 0 2006.201.23:42:11.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.23:42:11.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.23:42:11.19#ibcon#[25=USB\r\n] 2006.201.23:42:11.19#ibcon#*before write, iclass 12, count 0 2006.201.23:42:11.19#ibcon#enter sib2, iclass 12, count 0 2006.201.23:42:11.19#ibcon#flushed, iclass 12, count 0 2006.201.23:42:11.19#ibcon#about to write, iclass 12, count 0 2006.201.23:42:11.19#ibcon#wrote, iclass 12, count 0 2006.201.23:42:11.19#ibcon#about to read 3, iclass 12, count 0 2006.201.23:42:11.22#ibcon#read 3, iclass 12, count 0 2006.201.23:42:11.22#ibcon#about to read 4, iclass 12, count 0 2006.201.23:42:11.22#ibcon#read 4, iclass 12, count 0 2006.201.23:42:11.22#ibcon#about to read 5, iclass 12, count 0 2006.201.23:42:11.22#ibcon#read 5, iclass 12, count 0 2006.201.23:42:11.22#ibcon#about to read 6, iclass 12, count 0 2006.201.23:42:11.22#ibcon#read 6, iclass 12, count 0 2006.201.23:42:11.22#ibcon#end of sib2, iclass 12, count 0 2006.201.23:42:11.22#ibcon#*after write, iclass 12, count 0 2006.201.23:42:11.22#ibcon#*before return 0, iclass 12, count 0 2006.201.23:42:11.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:11.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:11.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.23:42:11.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.23:42:11.22$vck44/valo=3,564.99 2006.201.23:42:11.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.23:42:11.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.23:42:11.22#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:11.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:11.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:11.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:11.22#ibcon#enter wrdev, iclass 14, count 0 2006.201.23:42:11.22#ibcon#first serial, iclass 14, count 0 2006.201.23:42:11.22#ibcon#enter sib2, iclass 14, count 0 2006.201.23:42:11.22#ibcon#flushed, iclass 14, count 0 2006.201.23:42:11.22#ibcon#about to write, iclass 14, count 0 2006.201.23:42:11.22#ibcon#wrote, iclass 14, count 0 2006.201.23:42:11.22#ibcon#about to read 3, iclass 14, count 0 2006.201.23:42:11.24#ibcon#read 3, iclass 14, count 0 2006.201.23:42:11.24#ibcon#about to read 4, iclass 14, count 0 2006.201.23:42:11.24#ibcon#read 4, iclass 14, count 0 2006.201.23:42:11.24#ibcon#about to read 5, iclass 14, count 0 2006.201.23:42:11.24#ibcon#read 5, iclass 14, count 0 2006.201.23:42:11.24#ibcon#about to read 6, iclass 14, count 0 2006.201.23:42:11.24#ibcon#read 6, iclass 14, count 0 2006.201.23:42:11.24#ibcon#end of sib2, iclass 14, count 0 2006.201.23:42:11.24#ibcon#*mode == 0, iclass 14, count 0 2006.201.23:42:11.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.23:42:11.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.23:42:11.24#ibcon#*before write, iclass 14, count 0 2006.201.23:42:11.24#ibcon#enter sib2, iclass 14, count 0 2006.201.23:42:11.24#ibcon#flushed, iclass 14, count 0 2006.201.23:42:11.24#ibcon#about to write, iclass 14, count 0 2006.201.23:42:11.24#ibcon#wrote, iclass 14, count 0 2006.201.23:42:11.24#ibcon#about to read 3, iclass 14, count 0 2006.201.23:42:11.28#ibcon#read 3, iclass 14, count 0 2006.201.23:42:11.28#ibcon#about to read 4, iclass 14, count 0 2006.201.23:42:11.28#ibcon#read 4, iclass 14, count 0 2006.201.23:42:11.28#ibcon#about to read 5, iclass 14, count 0 2006.201.23:42:11.28#ibcon#read 5, iclass 14, count 0 2006.201.23:42:11.28#ibcon#about to read 6, iclass 14, count 0 2006.201.23:42:11.28#ibcon#read 6, iclass 14, count 0 2006.201.23:42:11.28#ibcon#end of sib2, iclass 14, count 0 2006.201.23:42:11.28#ibcon#*after write, iclass 14, count 0 2006.201.23:42:11.28#ibcon#*before return 0, iclass 14, count 0 2006.201.23:42:11.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:11.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:11.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.23:42:11.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.23:42:11.28$vck44/va=3,8 2006.201.23:42:11.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.201.23:42:11.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.201.23:42:11.28#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:11.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:42:11.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:42:11.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:42:11.34#ibcon#enter wrdev, iclass 16, count 2 2006.201.23:42:11.34#ibcon#first serial, iclass 16, count 2 2006.201.23:42:11.34#ibcon#enter sib2, iclass 16, count 2 2006.201.23:42:11.34#ibcon#flushed, iclass 16, count 2 2006.201.23:42:11.34#ibcon#about to write, iclass 16, count 2 2006.201.23:42:11.34#ibcon#wrote, iclass 16, count 2 2006.201.23:42:11.34#ibcon#about to read 3, iclass 16, count 2 2006.201.23:42:11.36#ibcon#read 3, iclass 16, count 2 2006.201.23:42:11.36#ibcon#about to read 4, iclass 16, count 2 2006.201.23:42:11.36#ibcon#read 4, iclass 16, count 2 2006.201.23:42:11.36#ibcon#about to read 5, iclass 16, count 2 2006.201.23:42:11.36#ibcon#read 5, iclass 16, count 2 2006.201.23:42:11.36#ibcon#about to read 6, iclass 16, count 2 2006.201.23:42:11.36#ibcon#read 6, iclass 16, count 2 2006.201.23:42:11.36#ibcon#end of sib2, iclass 16, count 2 2006.201.23:42:11.36#ibcon#*mode == 0, iclass 16, count 2 2006.201.23:42:11.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.201.23:42:11.36#ibcon#[25=AT03-08\r\n] 2006.201.23:42:11.36#ibcon#*before write, iclass 16, count 2 2006.201.23:42:11.36#ibcon#enter sib2, iclass 16, count 2 2006.201.23:42:11.36#ibcon#flushed, iclass 16, count 2 2006.201.23:42:11.36#ibcon#about to write, iclass 16, count 2 2006.201.23:42:11.36#ibcon#wrote, iclass 16, count 2 2006.201.23:42:11.36#ibcon#about to read 3, iclass 16, count 2 2006.201.23:42:11.39#ibcon#read 3, iclass 16, count 2 2006.201.23:42:11.39#ibcon#about to read 4, iclass 16, count 2 2006.201.23:42:11.39#ibcon#read 4, iclass 16, count 2 2006.201.23:42:11.39#ibcon#about to read 5, iclass 16, count 2 2006.201.23:42:11.39#ibcon#read 5, iclass 16, count 2 2006.201.23:42:11.39#ibcon#about to read 6, iclass 16, count 2 2006.201.23:42:11.39#ibcon#read 6, iclass 16, count 2 2006.201.23:42:11.39#ibcon#end of sib2, iclass 16, count 2 2006.201.23:42:11.39#ibcon#*after write, iclass 16, count 2 2006.201.23:42:11.39#ibcon#*before return 0, iclass 16, count 2 2006.201.23:42:11.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:42:11.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.201.23:42:11.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.201.23:42:11.39#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:11.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:42:11.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:42:11.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:42:11.51#ibcon#enter wrdev, iclass 16, count 0 2006.201.23:42:11.51#ibcon#first serial, iclass 16, count 0 2006.201.23:42:11.51#ibcon#enter sib2, iclass 16, count 0 2006.201.23:42:11.51#ibcon#flushed, iclass 16, count 0 2006.201.23:42:11.51#ibcon#about to write, iclass 16, count 0 2006.201.23:42:11.51#ibcon#wrote, iclass 16, count 0 2006.201.23:42:11.51#ibcon#about to read 3, iclass 16, count 0 2006.201.23:42:11.53#ibcon#read 3, iclass 16, count 0 2006.201.23:42:11.53#ibcon#about to read 4, iclass 16, count 0 2006.201.23:42:11.53#ibcon#read 4, iclass 16, count 0 2006.201.23:42:11.53#ibcon#about to read 5, iclass 16, count 0 2006.201.23:42:11.53#ibcon#read 5, iclass 16, count 0 2006.201.23:42:11.53#ibcon#about to read 6, iclass 16, count 0 2006.201.23:42:11.53#ibcon#read 6, iclass 16, count 0 2006.201.23:42:11.53#ibcon#end of sib2, iclass 16, count 0 2006.201.23:42:11.53#ibcon#*mode == 0, iclass 16, count 0 2006.201.23:42:11.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.23:42:11.53#ibcon#[25=USB\r\n] 2006.201.23:42:11.53#ibcon#*before write, iclass 16, count 0 2006.201.23:42:11.53#ibcon#enter sib2, iclass 16, count 0 2006.201.23:42:11.53#ibcon#flushed, iclass 16, count 0 2006.201.23:42:11.53#ibcon#about to write, iclass 16, count 0 2006.201.23:42:11.53#ibcon#wrote, iclass 16, count 0 2006.201.23:42:11.53#ibcon#about to read 3, iclass 16, count 0 2006.201.23:42:11.56#ibcon#read 3, iclass 16, count 0 2006.201.23:42:11.56#ibcon#about to read 4, iclass 16, count 0 2006.201.23:42:11.56#ibcon#read 4, iclass 16, count 0 2006.201.23:42:11.56#ibcon#about to read 5, iclass 16, count 0 2006.201.23:42:11.56#ibcon#read 5, iclass 16, count 0 2006.201.23:42:11.56#ibcon#about to read 6, iclass 16, count 0 2006.201.23:42:11.56#ibcon#read 6, iclass 16, count 0 2006.201.23:42:11.56#ibcon#end of sib2, iclass 16, count 0 2006.201.23:42:11.56#ibcon#*after write, iclass 16, count 0 2006.201.23:42:11.56#ibcon#*before return 0, iclass 16, count 0 2006.201.23:42:11.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:42:11.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.201.23:42:11.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.23:42:11.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.23:42:11.56$vck44/valo=4,624.99 2006.201.23:42:11.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.201.23:42:11.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.201.23:42:11.56#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:11.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:42:11.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:42:11.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:42:11.56#ibcon#enter wrdev, iclass 18, count 0 2006.201.23:42:11.56#ibcon#first serial, iclass 18, count 0 2006.201.23:42:11.56#ibcon#enter sib2, iclass 18, count 0 2006.201.23:42:11.56#ibcon#flushed, iclass 18, count 0 2006.201.23:42:11.56#ibcon#about to write, iclass 18, count 0 2006.201.23:42:11.56#ibcon#wrote, iclass 18, count 0 2006.201.23:42:11.56#ibcon#about to read 3, iclass 18, count 0 2006.201.23:42:11.58#ibcon#read 3, iclass 18, count 0 2006.201.23:42:11.58#ibcon#about to read 4, iclass 18, count 0 2006.201.23:42:11.58#ibcon#read 4, iclass 18, count 0 2006.201.23:42:11.58#ibcon#about to read 5, iclass 18, count 0 2006.201.23:42:11.58#ibcon#read 5, iclass 18, count 0 2006.201.23:42:11.58#ibcon#about to read 6, iclass 18, count 0 2006.201.23:42:11.58#ibcon#read 6, iclass 18, count 0 2006.201.23:42:11.58#ibcon#end of sib2, iclass 18, count 0 2006.201.23:42:11.58#ibcon#*mode == 0, iclass 18, count 0 2006.201.23:42:11.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.23:42:11.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.23:42:11.58#ibcon#*before write, iclass 18, count 0 2006.201.23:42:11.58#ibcon#enter sib2, iclass 18, count 0 2006.201.23:42:11.58#ibcon#flushed, iclass 18, count 0 2006.201.23:42:11.58#ibcon#about to write, iclass 18, count 0 2006.201.23:42:11.58#ibcon#wrote, iclass 18, count 0 2006.201.23:42:11.58#ibcon#about to read 3, iclass 18, count 0 2006.201.23:42:11.62#ibcon#read 3, iclass 18, count 0 2006.201.23:42:11.62#ibcon#about to read 4, iclass 18, count 0 2006.201.23:42:11.62#ibcon#read 4, iclass 18, count 0 2006.201.23:42:11.62#ibcon#about to read 5, iclass 18, count 0 2006.201.23:42:11.62#ibcon#read 5, iclass 18, count 0 2006.201.23:42:11.62#ibcon#about to read 6, iclass 18, count 0 2006.201.23:42:11.62#ibcon#read 6, iclass 18, count 0 2006.201.23:42:11.62#ibcon#end of sib2, iclass 18, count 0 2006.201.23:42:11.62#ibcon#*after write, iclass 18, count 0 2006.201.23:42:11.62#ibcon#*before return 0, iclass 18, count 0 2006.201.23:42:11.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:42:11.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.201.23:42:11.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.23:42:11.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.23:42:11.62$vck44/va=4,7 2006.201.23:42:11.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.201.23:42:11.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.201.23:42:11.62#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:11.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:42:11.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:42:11.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:42:11.68#ibcon#enter wrdev, iclass 20, count 2 2006.201.23:42:11.68#ibcon#first serial, iclass 20, count 2 2006.201.23:42:11.68#ibcon#enter sib2, iclass 20, count 2 2006.201.23:42:11.68#ibcon#flushed, iclass 20, count 2 2006.201.23:42:11.68#ibcon#about to write, iclass 20, count 2 2006.201.23:42:11.68#ibcon#wrote, iclass 20, count 2 2006.201.23:42:11.68#ibcon#about to read 3, iclass 20, count 2 2006.201.23:42:11.70#ibcon#read 3, iclass 20, count 2 2006.201.23:42:11.70#ibcon#about to read 4, iclass 20, count 2 2006.201.23:42:11.70#ibcon#read 4, iclass 20, count 2 2006.201.23:42:11.70#ibcon#about to read 5, iclass 20, count 2 2006.201.23:42:11.70#ibcon#read 5, iclass 20, count 2 2006.201.23:42:11.70#ibcon#about to read 6, iclass 20, count 2 2006.201.23:42:11.70#ibcon#read 6, iclass 20, count 2 2006.201.23:42:11.70#ibcon#end of sib2, iclass 20, count 2 2006.201.23:42:11.70#ibcon#*mode == 0, iclass 20, count 2 2006.201.23:42:11.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.201.23:42:11.70#ibcon#[25=AT04-07\r\n] 2006.201.23:42:11.70#ibcon#*before write, iclass 20, count 2 2006.201.23:42:11.70#ibcon#enter sib2, iclass 20, count 2 2006.201.23:42:11.70#ibcon#flushed, iclass 20, count 2 2006.201.23:42:11.70#ibcon#about to write, iclass 20, count 2 2006.201.23:42:11.70#ibcon#wrote, iclass 20, count 2 2006.201.23:42:11.70#ibcon#about to read 3, iclass 20, count 2 2006.201.23:42:11.73#ibcon#read 3, iclass 20, count 2 2006.201.23:42:11.73#ibcon#about to read 4, iclass 20, count 2 2006.201.23:42:11.73#ibcon#read 4, iclass 20, count 2 2006.201.23:42:11.73#ibcon#about to read 5, iclass 20, count 2 2006.201.23:42:11.73#ibcon#read 5, iclass 20, count 2 2006.201.23:42:11.73#ibcon#about to read 6, iclass 20, count 2 2006.201.23:42:11.73#ibcon#read 6, iclass 20, count 2 2006.201.23:42:11.73#ibcon#end of sib2, iclass 20, count 2 2006.201.23:42:11.73#ibcon#*after write, iclass 20, count 2 2006.201.23:42:11.73#ibcon#*before return 0, iclass 20, count 2 2006.201.23:42:11.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:42:11.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.201.23:42:11.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.201.23:42:11.73#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:11.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:42:11.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:42:11.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:42:11.85#ibcon#enter wrdev, iclass 20, count 0 2006.201.23:42:11.85#ibcon#first serial, iclass 20, count 0 2006.201.23:42:11.85#ibcon#enter sib2, iclass 20, count 0 2006.201.23:42:11.85#ibcon#flushed, iclass 20, count 0 2006.201.23:42:11.85#ibcon#about to write, iclass 20, count 0 2006.201.23:42:11.85#ibcon#wrote, iclass 20, count 0 2006.201.23:42:11.85#ibcon#about to read 3, iclass 20, count 0 2006.201.23:42:11.87#ibcon#read 3, iclass 20, count 0 2006.201.23:42:11.87#ibcon#about to read 4, iclass 20, count 0 2006.201.23:42:11.87#ibcon#read 4, iclass 20, count 0 2006.201.23:42:11.87#ibcon#about to read 5, iclass 20, count 0 2006.201.23:42:11.87#ibcon#read 5, iclass 20, count 0 2006.201.23:42:11.87#ibcon#about to read 6, iclass 20, count 0 2006.201.23:42:11.87#ibcon#read 6, iclass 20, count 0 2006.201.23:42:11.87#ibcon#end of sib2, iclass 20, count 0 2006.201.23:42:11.87#ibcon#*mode == 0, iclass 20, count 0 2006.201.23:42:11.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.23:42:11.87#ibcon#[25=USB\r\n] 2006.201.23:42:11.87#ibcon#*before write, iclass 20, count 0 2006.201.23:42:11.87#ibcon#enter sib2, iclass 20, count 0 2006.201.23:42:11.87#ibcon#flushed, iclass 20, count 0 2006.201.23:42:11.87#ibcon#about to write, iclass 20, count 0 2006.201.23:42:11.87#ibcon#wrote, iclass 20, count 0 2006.201.23:42:11.87#ibcon#about to read 3, iclass 20, count 0 2006.201.23:42:11.90#ibcon#read 3, iclass 20, count 0 2006.201.23:42:11.90#ibcon#about to read 4, iclass 20, count 0 2006.201.23:42:11.90#ibcon#read 4, iclass 20, count 0 2006.201.23:42:11.90#ibcon#about to read 5, iclass 20, count 0 2006.201.23:42:11.90#ibcon#read 5, iclass 20, count 0 2006.201.23:42:11.90#ibcon#about to read 6, iclass 20, count 0 2006.201.23:42:11.90#ibcon#read 6, iclass 20, count 0 2006.201.23:42:11.90#ibcon#end of sib2, iclass 20, count 0 2006.201.23:42:11.90#ibcon#*after write, iclass 20, count 0 2006.201.23:42:11.90#ibcon#*before return 0, iclass 20, count 0 2006.201.23:42:11.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:42:11.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.201.23:42:11.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.23:42:11.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.23:42:11.90$vck44/valo=5,734.99 2006.201.23:42:11.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.23:42:11.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.23:42:11.90#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:11.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:11.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:11.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:11.90#ibcon#enter wrdev, iclass 22, count 0 2006.201.23:42:11.90#ibcon#first serial, iclass 22, count 0 2006.201.23:42:11.90#ibcon#enter sib2, iclass 22, count 0 2006.201.23:42:11.90#ibcon#flushed, iclass 22, count 0 2006.201.23:42:11.90#ibcon#about to write, iclass 22, count 0 2006.201.23:42:11.90#ibcon#wrote, iclass 22, count 0 2006.201.23:42:11.90#ibcon#about to read 3, iclass 22, count 0 2006.201.23:42:11.92#ibcon#read 3, iclass 22, count 0 2006.201.23:42:11.92#ibcon#about to read 4, iclass 22, count 0 2006.201.23:42:11.92#ibcon#read 4, iclass 22, count 0 2006.201.23:42:11.92#ibcon#about to read 5, iclass 22, count 0 2006.201.23:42:11.92#ibcon#read 5, iclass 22, count 0 2006.201.23:42:11.92#ibcon#about to read 6, iclass 22, count 0 2006.201.23:42:11.92#ibcon#read 6, iclass 22, count 0 2006.201.23:42:11.92#ibcon#end of sib2, iclass 22, count 0 2006.201.23:42:11.92#ibcon#*mode == 0, iclass 22, count 0 2006.201.23:42:11.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.23:42:11.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.23:42:11.92#ibcon#*before write, iclass 22, count 0 2006.201.23:42:11.92#ibcon#enter sib2, iclass 22, count 0 2006.201.23:42:11.92#ibcon#flushed, iclass 22, count 0 2006.201.23:42:11.92#ibcon#about to write, iclass 22, count 0 2006.201.23:42:11.92#ibcon#wrote, iclass 22, count 0 2006.201.23:42:11.92#ibcon#about to read 3, iclass 22, count 0 2006.201.23:42:11.96#ibcon#read 3, iclass 22, count 0 2006.201.23:42:11.96#ibcon#about to read 4, iclass 22, count 0 2006.201.23:42:11.96#ibcon#read 4, iclass 22, count 0 2006.201.23:42:11.96#ibcon#about to read 5, iclass 22, count 0 2006.201.23:42:11.96#ibcon#read 5, iclass 22, count 0 2006.201.23:42:11.96#ibcon#about to read 6, iclass 22, count 0 2006.201.23:42:11.96#ibcon#read 6, iclass 22, count 0 2006.201.23:42:11.96#ibcon#end of sib2, iclass 22, count 0 2006.201.23:42:11.96#ibcon#*after write, iclass 22, count 0 2006.201.23:42:11.96#ibcon#*before return 0, iclass 22, count 0 2006.201.23:42:11.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:11.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:11.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.23:42:11.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.23:42:11.96$vck44/va=5,4 2006.201.23:42:11.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.23:42:11.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.23:42:11.96#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:11.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:12.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:12.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:12.02#ibcon#enter wrdev, iclass 24, count 2 2006.201.23:42:12.02#ibcon#first serial, iclass 24, count 2 2006.201.23:42:12.02#ibcon#enter sib2, iclass 24, count 2 2006.201.23:42:12.02#ibcon#flushed, iclass 24, count 2 2006.201.23:42:12.02#ibcon#about to write, iclass 24, count 2 2006.201.23:42:12.02#ibcon#wrote, iclass 24, count 2 2006.201.23:42:12.02#ibcon#about to read 3, iclass 24, count 2 2006.201.23:42:12.04#ibcon#read 3, iclass 24, count 2 2006.201.23:42:12.04#ibcon#about to read 4, iclass 24, count 2 2006.201.23:42:12.04#ibcon#read 4, iclass 24, count 2 2006.201.23:42:12.04#ibcon#about to read 5, iclass 24, count 2 2006.201.23:42:12.04#ibcon#read 5, iclass 24, count 2 2006.201.23:42:12.04#ibcon#about to read 6, iclass 24, count 2 2006.201.23:42:12.04#ibcon#read 6, iclass 24, count 2 2006.201.23:42:12.04#ibcon#end of sib2, iclass 24, count 2 2006.201.23:42:12.04#ibcon#*mode == 0, iclass 24, count 2 2006.201.23:42:12.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.23:42:12.04#ibcon#[25=AT05-04\r\n] 2006.201.23:42:12.04#ibcon#*before write, iclass 24, count 2 2006.201.23:42:12.04#ibcon#enter sib2, iclass 24, count 2 2006.201.23:42:12.04#ibcon#flushed, iclass 24, count 2 2006.201.23:42:12.04#ibcon#about to write, iclass 24, count 2 2006.201.23:42:12.04#ibcon#wrote, iclass 24, count 2 2006.201.23:42:12.04#ibcon#about to read 3, iclass 24, count 2 2006.201.23:42:12.07#ibcon#read 3, iclass 24, count 2 2006.201.23:42:12.07#ibcon#about to read 4, iclass 24, count 2 2006.201.23:42:12.07#ibcon#read 4, iclass 24, count 2 2006.201.23:42:12.07#ibcon#about to read 5, iclass 24, count 2 2006.201.23:42:12.07#ibcon#read 5, iclass 24, count 2 2006.201.23:42:12.07#ibcon#about to read 6, iclass 24, count 2 2006.201.23:42:12.07#ibcon#read 6, iclass 24, count 2 2006.201.23:42:12.07#ibcon#end of sib2, iclass 24, count 2 2006.201.23:42:12.07#ibcon#*after write, iclass 24, count 2 2006.201.23:42:12.07#ibcon#*before return 0, iclass 24, count 2 2006.201.23:42:12.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:12.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:12.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.23:42:12.07#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:12.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:12.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:12.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:12.19#ibcon#enter wrdev, iclass 24, count 0 2006.201.23:42:12.19#ibcon#first serial, iclass 24, count 0 2006.201.23:42:12.19#ibcon#enter sib2, iclass 24, count 0 2006.201.23:42:12.19#ibcon#flushed, iclass 24, count 0 2006.201.23:42:12.19#ibcon#about to write, iclass 24, count 0 2006.201.23:42:12.19#ibcon#wrote, iclass 24, count 0 2006.201.23:42:12.19#ibcon#about to read 3, iclass 24, count 0 2006.201.23:42:12.21#ibcon#read 3, iclass 24, count 0 2006.201.23:42:12.21#ibcon#about to read 4, iclass 24, count 0 2006.201.23:42:12.21#ibcon#read 4, iclass 24, count 0 2006.201.23:42:12.21#ibcon#about to read 5, iclass 24, count 0 2006.201.23:42:12.21#ibcon#read 5, iclass 24, count 0 2006.201.23:42:12.21#ibcon#about to read 6, iclass 24, count 0 2006.201.23:42:12.21#ibcon#read 6, iclass 24, count 0 2006.201.23:42:12.21#ibcon#end of sib2, iclass 24, count 0 2006.201.23:42:12.21#ibcon#*mode == 0, iclass 24, count 0 2006.201.23:42:12.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.23:42:12.21#ibcon#[25=USB\r\n] 2006.201.23:42:12.21#ibcon#*before write, iclass 24, count 0 2006.201.23:42:12.21#ibcon#enter sib2, iclass 24, count 0 2006.201.23:42:12.21#ibcon#flushed, iclass 24, count 0 2006.201.23:42:12.21#ibcon#about to write, iclass 24, count 0 2006.201.23:42:12.21#ibcon#wrote, iclass 24, count 0 2006.201.23:42:12.21#ibcon#about to read 3, iclass 24, count 0 2006.201.23:42:12.24#ibcon#read 3, iclass 24, count 0 2006.201.23:42:12.24#ibcon#about to read 4, iclass 24, count 0 2006.201.23:42:12.24#ibcon#read 4, iclass 24, count 0 2006.201.23:42:12.24#ibcon#about to read 5, iclass 24, count 0 2006.201.23:42:12.24#ibcon#read 5, iclass 24, count 0 2006.201.23:42:12.24#ibcon#about to read 6, iclass 24, count 0 2006.201.23:42:12.24#ibcon#read 6, iclass 24, count 0 2006.201.23:42:12.24#ibcon#end of sib2, iclass 24, count 0 2006.201.23:42:12.24#ibcon#*after write, iclass 24, count 0 2006.201.23:42:12.24#ibcon#*before return 0, iclass 24, count 0 2006.201.23:42:12.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:12.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:12.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.23:42:12.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.23:42:12.24$vck44/valo=6,814.99 2006.201.23:42:12.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.23:42:12.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.23:42:12.24#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:12.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:12.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:12.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:12.24#ibcon#enter wrdev, iclass 26, count 0 2006.201.23:42:12.24#ibcon#first serial, iclass 26, count 0 2006.201.23:42:12.24#ibcon#enter sib2, iclass 26, count 0 2006.201.23:42:12.24#ibcon#flushed, iclass 26, count 0 2006.201.23:42:12.24#ibcon#about to write, iclass 26, count 0 2006.201.23:42:12.24#ibcon#wrote, iclass 26, count 0 2006.201.23:42:12.24#ibcon#about to read 3, iclass 26, count 0 2006.201.23:42:12.26#ibcon#read 3, iclass 26, count 0 2006.201.23:42:12.26#ibcon#about to read 4, iclass 26, count 0 2006.201.23:42:12.26#ibcon#read 4, iclass 26, count 0 2006.201.23:42:12.26#ibcon#about to read 5, iclass 26, count 0 2006.201.23:42:12.26#ibcon#read 5, iclass 26, count 0 2006.201.23:42:12.26#ibcon#about to read 6, iclass 26, count 0 2006.201.23:42:12.26#ibcon#read 6, iclass 26, count 0 2006.201.23:42:12.26#ibcon#end of sib2, iclass 26, count 0 2006.201.23:42:12.26#ibcon#*mode == 0, iclass 26, count 0 2006.201.23:42:12.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.23:42:12.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.23:42:12.26#ibcon#*before write, iclass 26, count 0 2006.201.23:42:12.26#ibcon#enter sib2, iclass 26, count 0 2006.201.23:42:12.26#ibcon#flushed, iclass 26, count 0 2006.201.23:42:12.26#ibcon#about to write, iclass 26, count 0 2006.201.23:42:12.26#ibcon#wrote, iclass 26, count 0 2006.201.23:42:12.26#ibcon#about to read 3, iclass 26, count 0 2006.201.23:42:12.30#ibcon#read 3, iclass 26, count 0 2006.201.23:42:12.30#ibcon#about to read 4, iclass 26, count 0 2006.201.23:42:12.30#ibcon#read 4, iclass 26, count 0 2006.201.23:42:12.30#ibcon#about to read 5, iclass 26, count 0 2006.201.23:42:12.30#ibcon#read 5, iclass 26, count 0 2006.201.23:42:12.30#ibcon#about to read 6, iclass 26, count 0 2006.201.23:42:12.30#ibcon#read 6, iclass 26, count 0 2006.201.23:42:12.30#ibcon#end of sib2, iclass 26, count 0 2006.201.23:42:12.30#ibcon#*after write, iclass 26, count 0 2006.201.23:42:12.30#ibcon#*before return 0, iclass 26, count 0 2006.201.23:42:12.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:12.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:12.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.23:42:12.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.23:42:12.30$vck44/va=6,5 2006.201.23:42:12.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.23:42:12.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.23:42:12.30#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:12.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:12.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:12.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:12.36#ibcon#enter wrdev, iclass 28, count 2 2006.201.23:42:12.36#ibcon#first serial, iclass 28, count 2 2006.201.23:42:12.36#ibcon#enter sib2, iclass 28, count 2 2006.201.23:42:12.36#ibcon#flushed, iclass 28, count 2 2006.201.23:42:12.36#ibcon#about to write, iclass 28, count 2 2006.201.23:42:12.36#ibcon#wrote, iclass 28, count 2 2006.201.23:42:12.36#ibcon#about to read 3, iclass 28, count 2 2006.201.23:42:12.38#ibcon#read 3, iclass 28, count 2 2006.201.23:42:12.38#ibcon#about to read 4, iclass 28, count 2 2006.201.23:42:12.38#ibcon#read 4, iclass 28, count 2 2006.201.23:42:12.38#ibcon#about to read 5, iclass 28, count 2 2006.201.23:42:12.38#ibcon#read 5, iclass 28, count 2 2006.201.23:42:12.38#ibcon#about to read 6, iclass 28, count 2 2006.201.23:42:12.38#ibcon#read 6, iclass 28, count 2 2006.201.23:42:12.38#ibcon#end of sib2, iclass 28, count 2 2006.201.23:42:12.38#ibcon#*mode == 0, iclass 28, count 2 2006.201.23:42:12.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.23:42:12.38#ibcon#[25=AT06-05\r\n] 2006.201.23:42:12.38#ibcon#*before write, iclass 28, count 2 2006.201.23:42:12.38#ibcon#enter sib2, iclass 28, count 2 2006.201.23:42:12.38#ibcon#flushed, iclass 28, count 2 2006.201.23:42:12.38#ibcon#about to write, iclass 28, count 2 2006.201.23:42:12.38#ibcon#wrote, iclass 28, count 2 2006.201.23:42:12.38#ibcon#about to read 3, iclass 28, count 2 2006.201.23:42:12.41#ibcon#read 3, iclass 28, count 2 2006.201.23:42:12.41#ibcon#about to read 4, iclass 28, count 2 2006.201.23:42:12.41#ibcon#read 4, iclass 28, count 2 2006.201.23:42:12.41#ibcon#about to read 5, iclass 28, count 2 2006.201.23:42:12.41#ibcon#read 5, iclass 28, count 2 2006.201.23:42:12.41#ibcon#about to read 6, iclass 28, count 2 2006.201.23:42:12.41#ibcon#read 6, iclass 28, count 2 2006.201.23:42:12.41#ibcon#end of sib2, iclass 28, count 2 2006.201.23:42:12.41#ibcon#*after write, iclass 28, count 2 2006.201.23:42:12.41#ibcon#*before return 0, iclass 28, count 2 2006.201.23:42:12.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:12.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:12.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.23:42:12.41#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:12.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:12.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:12.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:12.53#ibcon#enter wrdev, iclass 28, count 0 2006.201.23:42:12.53#ibcon#first serial, iclass 28, count 0 2006.201.23:42:12.53#ibcon#enter sib2, iclass 28, count 0 2006.201.23:42:12.53#ibcon#flushed, iclass 28, count 0 2006.201.23:42:12.53#ibcon#about to write, iclass 28, count 0 2006.201.23:42:12.53#ibcon#wrote, iclass 28, count 0 2006.201.23:42:12.53#ibcon#about to read 3, iclass 28, count 0 2006.201.23:42:12.55#ibcon#read 3, iclass 28, count 0 2006.201.23:42:12.55#ibcon#about to read 4, iclass 28, count 0 2006.201.23:42:12.55#ibcon#read 4, iclass 28, count 0 2006.201.23:42:12.55#ibcon#about to read 5, iclass 28, count 0 2006.201.23:42:12.55#ibcon#read 5, iclass 28, count 0 2006.201.23:42:12.55#ibcon#about to read 6, iclass 28, count 0 2006.201.23:42:12.55#ibcon#read 6, iclass 28, count 0 2006.201.23:42:12.55#ibcon#end of sib2, iclass 28, count 0 2006.201.23:42:12.55#ibcon#*mode == 0, iclass 28, count 0 2006.201.23:42:12.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.23:42:12.55#ibcon#[25=USB\r\n] 2006.201.23:42:12.55#ibcon#*before write, iclass 28, count 0 2006.201.23:42:12.55#ibcon#enter sib2, iclass 28, count 0 2006.201.23:42:12.55#ibcon#flushed, iclass 28, count 0 2006.201.23:42:12.55#ibcon#about to write, iclass 28, count 0 2006.201.23:42:12.55#ibcon#wrote, iclass 28, count 0 2006.201.23:42:12.55#ibcon#about to read 3, iclass 28, count 0 2006.201.23:42:12.58#ibcon#read 3, iclass 28, count 0 2006.201.23:42:12.58#ibcon#about to read 4, iclass 28, count 0 2006.201.23:42:12.58#ibcon#read 4, iclass 28, count 0 2006.201.23:42:12.58#ibcon#about to read 5, iclass 28, count 0 2006.201.23:42:12.58#ibcon#read 5, iclass 28, count 0 2006.201.23:42:12.58#ibcon#about to read 6, iclass 28, count 0 2006.201.23:42:12.58#ibcon#read 6, iclass 28, count 0 2006.201.23:42:12.58#ibcon#end of sib2, iclass 28, count 0 2006.201.23:42:12.58#ibcon#*after write, iclass 28, count 0 2006.201.23:42:12.58#ibcon#*before return 0, iclass 28, count 0 2006.201.23:42:12.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:12.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:12.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.23:42:12.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.23:42:12.58$vck44/valo=7,864.99 2006.201.23:42:12.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.23:42:12.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.23:42:12.58#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:12.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:12.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:12.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:12.58#ibcon#enter wrdev, iclass 30, count 0 2006.201.23:42:12.58#ibcon#first serial, iclass 30, count 0 2006.201.23:42:12.58#ibcon#enter sib2, iclass 30, count 0 2006.201.23:42:12.58#ibcon#flushed, iclass 30, count 0 2006.201.23:42:12.58#ibcon#about to write, iclass 30, count 0 2006.201.23:42:12.58#ibcon#wrote, iclass 30, count 0 2006.201.23:42:12.58#ibcon#about to read 3, iclass 30, count 0 2006.201.23:42:12.60#ibcon#read 3, iclass 30, count 0 2006.201.23:42:12.60#ibcon#about to read 4, iclass 30, count 0 2006.201.23:42:12.60#ibcon#read 4, iclass 30, count 0 2006.201.23:42:12.60#ibcon#about to read 5, iclass 30, count 0 2006.201.23:42:12.60#ibcon#read 5, iclass 30, count 0 2006.201.23:42:12.60#ibcon#about to read 6, iclass 30, count 0 2006.201.23:42:12.60#ibcon#read 6, iclass 30, count 0 2006.201.23:42:12.60#ibcon#end of sib2, iclass 30, count 0 2006.201.23:42:12.60#ibcon#*mode == 0, iclass 30, count 0 2006.201.23:42:12.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.23:42:12.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.23:42:12.60#ibcon#*before write, iclass 30, count 0 2006.201.23:42:12.60#ibcon#enter sib2, iclass 30, count 0 2006.201.23:42:12.60#ibcon#flushed, iclass 30, count 0 2006.201.23:42:12.60#ibcon#about to write, iclass 30, count 0 2006.201.23:42:12.60#ibcon#wrote, iclass 30, count 0 2006.201.23:42:12.60#ibcon#about to read 3, iclass 30, count 0 2006.201.23:42:12.64#ibcon#read 3, iclass 30, count 0 2006.201.23:42:12.64#ibcon#about to read 4, iclass 30, count 0 2006.201.23:42:12.64#ibcon#read 4, iclass 30, count 0 2006.201.23:42:12.64#ibcon#about to read 5, iclass 30, count 0 2006.201.23:42:12.64#ibcon#read 5, iclass 30, count 0 2006.201.23:42:12.64#ibcon#about to read 6, iclass 30, count 0 2006.201.23:42:12.64#ibcon#read 6, iclass 30, count 0 2006.201.23:42:12.64#ibcon#end of sib2, iclass 30, count 0 2006.201.23:42:12.64#ibcon#*after write, iclass 30, count 0 2006.201.23:42:12.64#ibcon#*before return 0, iclass 30, count 0 2006.201.23:42:12.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:12.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:12.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.23:42:12.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.23:42:12.64$vck44/va=7,5 2006.201.23:42:12.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.23:42:12.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.23:42:12.64#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:12.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:12.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:12.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:12.70#ibcon#enter wrdev, iclass 32, count 2 2006.201.23:42:12.70#ibcon#first serial, iclass 32, count 2 2006.201.23:42:12.70#ibcon#enter sib2, iclass 32, count 2 2006.201.23:42:12.70#ibcon#flushed, iclass 32, count 2 2006.201.23:42:12.70#ibcon#about to write, iclass 32, count 2 2006.201.23:42:12.70#ibcon#wrote, iclass 32, count 2 2006.201.23:42:12.70#ibcon#about to read 3, iclass 32, count 2 2006.201.23:42:12.72#ibcon#read 3, iclass 32, count 2 2006.201.23:42:12.72#ibcon#about to read 4, iclass 32, count 2 2006.201.23:42:12.72#ibcon#read 4, iclass 32, count 2 2006.201.23:42:12.72#ibcon#about to read 5, iclass 32, count 2 2006.201.23:42:12.72#ibcon#read 5, iclass 32, count 2 2006.201.23:42:12.72#ibcon#about to read 6, iclass 32, count 2 2006.201.23:42:12.72#ibcon#read 6, iclass 32, count 2 2006.201.23:42:12.72#ibcon#end of sib2, iclass 32, count 2 2006.201.23:42:12.72#ibcon#*mode == 0, iclass 32, count 2 2006.201.23:42:12.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.23:42:12.72#ibcon#[25=AT07-05\r\n] 2006.201.23:42:12.72#ibcon#*before write, iclass 32, count 2 2006.201.23:42:12.72#ibcon#enter sib2, iclass 32, count 2 2006.201.23:42:12.72#ibcon#flushed, iclass 32, count 2 2006.201.23:42:12.72#ibcon#about to write, iclass 32, count 2 2006.201.23:42:12.72#ibcon#wrote, iclass 32, count 2 2006.201.23:42:12.72#ibcon#about to read 3, iclass 32, count 2 2006.201.23:42:12.75#ibcon#read 3, iclass 32, count 2 2006.201.23:42:12.75#ibcon#about to read 4, iclass 32, count 2 2006.201.23:42:12.75#ibcon#read 4, iclass 32, count 2 2006.201.23:42:12.75#ibcon#about to read 5, iclass 32, count 2 2006.201.23:42:12.75#ibcon#read 5, iclass 32, count 2 2006.201.23:42:12.75#ibcon#about to read 6, iclass 32, count 2 2006.201.23:42:12.75#ibcon#read 6, iclass 32, count 2 2006.201.23:42:12.75#ibcon#end of sib2, iclass 32, count 2 2006.201.23:42:12.75#ibcon#*after write, iclass 32, count 2 2006.201.23:42:12.75#ibcon#*before return 0, iclass 32, count 2 2006.201.23:42:12.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:12.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:12.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.23:42:12.75#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:12.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:12.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:12.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:12.87#ibcon#enter wrdev, iclass 32, count 0 2006.201.23:42:12.87#ibcon#first serial, iclass 32, count 0 2006.201.23:42:12.87#ibcon#enter sib2, iclass 32, count 0 2006.201.23:42:12.87#ibcon#flushed, iclass 32, count 0 2006.201.23:42:12.87#ibcon#about to write, iclass 32, count 0 2006.201.23:42:12.87#ibcon#wrote, iclass 32, count 0 2006.201.23:42:12.87#ibcon#about to read 3, iclass 32, count 0 2006.201.23:42:12.89#ibcon#read 3, iclass 32, count 0 2006.201.23:42:12.89#ibcon#about to read 4, iclass 32, count 0 2006.201.23:42:12.89#ibcon#read 4, iclass 32, count 0 2006.201.23:42:12.89#ibcon#about to read 5, iclass 32, count 0 2006.201.23:42:12.89#ibcon#read 5, iclass 32, count 0 2006.201.23:42:12.89#ibcon#about to read 6, iclass 32, count 0 2006.201.23:42:12.89#ibcon#read 6, iclass 32, count 0 2006.201.23:42:12.89#ibcon#end of sib2, iclass 32, count 0 2006.201.23:42:12.89#ibcon#*mode == 0, iclass 32, count 0 2006.201.23:42:12.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.23:42:12.89#ibcon#[25=USB\r\n] 2006.201.23:42:12.89#ibcon#*before write, iclass 32, count 0 2006.201.23:42:12.89#ibcon#enter sib2, iclass 32, count 0 2006.201.23:42:12.89#ibcon#flushed, iclass 32, count 0 2006.201.23:42:12.89#ibcon#about to write, iclass 32, count 0 2006.201.23:42:12.89#ibcon#wrote, iclass 32, count 0 2006.201.23:42:12.89#ibcon#about to read 3, iclass 32, count 0 2006.201.23:42:12.92#ibcon#read 3, iclass 32, count 0 2006.201.23:42:12.92#ibcon#about to read 4, iclass 32, count 0 2006.201.23:42:12.92#ibcon#read 4, iclass 32, count 0 2006.201.23:42:12.92#ibcon#about to read 5, iclass 32, count 0 2006.201.23:42:12.92#ibcon#read 5, iclass 32, count 0 2006.201.23:42:12.92#ibcon#about to read 6, iclass 32, count 0 2006.201.23:42:12.92#ibcon#read 6, iclass 32, count 0 2006.201.23:42:12.92#ibcon#end of sib2, iclass 32, count 0 2006.201.23:42:12.92#ibcon#*after write, iclass 32, count 0 2006.201.23:42:12.92#ibcon#*before return 0, iclass 32, count 0 2006.201.23:42:12.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:12.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:12.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.23:42:12.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.23:42:12.92$vck44/valo=8,884.99 2006.201.23:42:12.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.23:42:12.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.23:42:12.92#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:12.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:12.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:12.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:12.92#ibcon#enter wrdev, iclass 34, count 0 2006.201.23:42:12.92#ibcon#first serial, iclass 34, count 0 2006.201.23:42:12.92#ibcon#enter sib2, iclass 34, count 0 2006.201.23:42:12.92#ibcon#flushed, iclass 34, count 0 2006.201.23:42:12.92#ibcon#about to write, iclass 34, count 0 2006.201.23:42:12.92#ibcon#wrote, iclass 34, count 0 2006.201.23:42:12.92#ibcon#about to read 3, iclass 34, count 0 2006.201.23:42:12.94#ibcon#read 3, iclass 34, count 0 2006.201.23:42:12.94#ibcon#about to read 4, iclass 34, count 0 2006.201.23:42:12.94#ibcon#read 4, iclass 34, count 0 2006.201.23:42:12.94#ibcon#about to read 5, iclass 34, count 0 2006.201.23:42:12.94#ibcon#read 5, iclass 34, count 0 2006.201.23:42:12.94#ibcon#about to read 6, iclass 34, count 0 2006.201.23:42:12.94#ibcon#read 6, iclass 34, count 0 2006.201.23:42:12.94#ibcon#end of sib2, iclass 34, count 0 2006.201.23:42:12.94#ibcon#*mode == 0, iclass 34, count 0 2006.201.23:42:12.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.23:42:12.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.23:42:12.94#ibcon#*before write, iclass 34, count 0 2006.201.23:42:12.94#ibcon#enter sib2, iclass 34, count 0 2006.201.23:42:12.94#ibcon#flushed, iclass 34, count 0 2006.201.23:42:12.94#ibcon#about to write, iclass 34, count 0 2006.201.23:42:12.94#ibcon#wrote, iclass 34, count 0 2006.201.23:42:12.94#ibcon#about to read 3, iclass 34, count 0 2006.201.23:42:12.98#ibcon#read 3, iclass 34, count 0 2006.201.23:42:12.98#ibcon#about to read 4, iclass 34, count 0 2006.201.23:42:12.98#ibcon#read 4, iclass 34, count 0 2006.201.23:42:12.98#ibcon#about to read 5, iclass 34, count 0 2006.201.23:42:12.98#ibcon#read 5, iclass 34, count 0 2006.201.23:42:12.98#ibcon#about to read 6, iclass 34, count 0 2006.201.23:42:12.98#ibcon#read 6, iclass 34, count 0 2006.201.23:42:12.98#ibcon#end of sib2, iclass 34, count 0 2006.201.23:42:12.98#ibcon#*after write, iclass 34, count 0 2006.201.23:42:12.98#ibcon#*before return 0, iclass 34, count 0 2006.201.23:42:12.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:12.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:12.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.23:42:12.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.23:42:12.98$vck44/va=8,4 2006.201.23:42:12.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.23:42:12.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.23:42:12.98#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:12.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:13.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:13.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:13.04#ibcon#enter wrdev, iclass 36, count 2 2006.201.23:42:13.04#ibcon#first serial, iclass 36, count 2 2006.201.23:42:13.04#ibcon#enter sib2, iclass 36, count 2 2006.201.23:42:13.04#ibcon#flushed, iclass 36, count 2 2006.201.23:42:13.04#ibcon#about to write, iclass 36, count 2 2006.201.23:42:13.04#ibcon#wrote, iclass 36, count 2 2006.201.23:42:13.04#ibcon#about to read 3, iclass 36, count 2 2006.201.23:42:13.06#ibcon#read 3, iclass 36, count 2 2006.201.23:42:13.06#ibcon#about to read 4, iclass 36, count 2 2006.201.23:42:13.06#ibcon#read 4, iclass 36, count 2 2006.201.23:42:13.06#ibcon#about to read 5, iclass 36, count 2 2006.201.23:42:13.06#ibcon#read 5, iclass 36, count 2 2006.201.23:42:13.06#ibcon#about to read 6, iclass 36, count 2 2006.201.23:42:13.06#ibcon#read 6, iclass 36, count 2 2006.201.23:42:13.06#ibcon#end of sib2, iclass 36, count 2 2006.201.23:42:13.06#ibcon#*mode == 0, iclass 36, count 2 2006.201.23:42:13.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.23:42:13.06#ibcon#[25=AT08-04\r\n] 2006.201.23:42:13.06#ibcon#*before write, iclass 36, count 2 2006.201.23:42:13.06#ibcon#enter sib2, iclass 36, count 2 2006.201.23:42:13.06#ibcon#flushed, iclass 36, count 2 2006.201.23:42:13.06#ibcon#about to write, iclass 36, count 2 2006.201.23:42:13.06#ibcon#wrote, iclass 36, count 2 2006.201.23:42:13.06#ibcon#about to read 3, iclass 36, count 2 2006.201.23:42:13.09#ibcon#read 3, iclass 36, count 2 2006.201.23:42:13.09#ibcon#about to read 4, iclass 36, count 2 2006.201.23:42:13.09#ibcon#read 4, iclass 36, count 2 2006.201.23:42:13.09#ibcon#about to read 5, iclass 36, count 2 2006.201.23:42:13.09#ibcon#read 5, iclass 36, count 2 2006.201.23:42:13.09#ibcon#about to read 6, iclass 36, count 2 2006.201.23:42:13.09#ibcon#read 6, iclass 36, count 2 2006.201.23:42:13.09#ibcon#end of sib2, iclass 36, count 2 2006.201.23:42:13.09#ibcon#*after write, iclass 36, count 2 2006.201.23:42:13.09#ibcon#*before return 0, iclass 36, count 2 2006.201.23:42:13.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:13.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:13.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.23:42:13.09#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:13.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:13.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:13.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:13.21#ibcon#enter wrdev, iclass 36, count 0 2006.201.23:42:13.21#ibcon#first serial, iclass 36, count 0 2006.201.23:42:13.21#ibcon#enter sib2, iclass 36, count 0 2006.201.23:42:13.21#ibcon#flushed, iclass 36, count 0 2006.201.23:42:13.21#ibcon#about to write, iclass 36, count 0 2006.201.23:42:13.21#ibcon#wrote, iclass 36, count 0 2006.201.23:42:13.21#ibcon#about to read 3, iclass 36, count 0 2006.201.23:42:13.23#ibcon#read 3, iclass 36, count 0 2006.201.23:42:13.23#ibcon#about to read 4, iclass 36, count 0 2006.201.23:42:13.23#ibcon#read 4, iclass 36, count 0 2006.201.23:42:13.23#ibcon#about to read 5, iclass 36, count 0 2006.201.23:42:13.23#ibcon#read 5, iclass 36, count 0 2006.201.23:42:13.23#ibcon#about to read 6, iclass 36, count 0 2006.201.23:42:13.23#ibcon#read 6, iclass 36, count 0 2006.201.23:42:13.23#ibcon#end of sib2, iclass 36, count 0 2006.201.23:42:13.23#ibcon#*mode == 0, iclass 36, count 0 2006.201.23:42:13.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.23:42:13.23#ibcon#[25=USB\r\n] 2006.201.23:42:13.23#ibcon#*before write, iclass 36, count 0 2006.201.23:42:13.23#ibcon#enter sib2, iclass 36, count 0 2006.201.23:42:13.23#ibcon#flushed, iclass 36, count 0 2006.201.23:42:13.23#ibcon#about to write, iclass 36, count 0 2006.201.23:42:13.23#ibcon#wrote, iclass 36, count 0 2006.201.23:42:13.23#ibcon#about to read 3, iclass 36, count 0 2006.201.23:42:13.26#ibcon#read 3, iclass 36, count 0 2006.201.23:42:13.26#ibcon#about to read 4, iclass 36, count 0 2006.201.23:42:13.26#ibcon#read 4, iclass 36, count 0 2006.201.23:42:13.26#ibcon#about to read 5, iclass 36, count 0 2006.201.23:42:13.26#ibcon#read 5, iclass 36, count 0 2006.201.23:42:13.26#ibcon#about to read 6, iclass 36, count 0 2006.201.23:42:13.26#ibcon#read 6, iclass 36, count 0 2006.201.23:42:13.26#ibcon#end of sib2, iclass 36, count 0 2006.201.23:42:13.26#ibcon#*after write, iclass 36, count 0 2006.201.23:42:13.26#ibcon#*before return 0, iclass 36, count 0 2006.201.23:42:13.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:13.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:13.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.23:42:13.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.23:42:13.26$vck44/vblo=1,629.99 2006.201.23:42:13.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.23:42:13.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.23:42:13.26#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:13.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:13.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:13.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:13.26#ibcon#enter wrdev, iclass 38, count 0 2006.201.23:42:13.26#ibcon#first serial, iclass 38, count 0 2006.201.23:42:13.26#ibcon#enter sib2, iclass 38, count 0 2006.201.23:42:13.26#ibcon#flushed, iclass 38, count 0 2006.201.23:42:13.26#ibcon#about to write, iclass 38, count 0 2006.201.23:42:13.26#ibcon#wrote, iclass 38, count 0 2006.201.23:42:13.26#ibcon#about to read 3, iclass 38, count 0 2006.201.23:42:13.28#ibcon#read 3, iclass 38, count 0 2006.201.23:42:13.28#ibcon#about to read 4, iclass 38, count 0 2006.201.23:42:13.28#ibcon#read 4, iclass 38, count 0 2006.201.23:42:13.28#ibcon#about to read 5, iclass 38, count 0 2006.201.23:42:13.28#ibcon#read 5, iclass 38, count 0 2006.201.23:42:13.28#ibcon#about to read 6, iclass 38, count 0 2006.201.23:42:13.28#ibcon#read 6, iclass 38, count 0 2006.201.23:42:13.28#ibcon#end of sib2, iclass 38, count 0 2006.201.23:42:13.28#ibcon#*mode == 0, iclass 38, count 0 2006.201.23:42:13.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.23:42:13.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.23:42:13.28#ibcon#*before write, iclass 38, count 0 2006.201.23:42:13.28#ibcon#enter sib2, iclass 38, count 0 2006.201.23:42:13.28#ibcon#flushed, iclass 38, count 0 2006.201.23:42:13.28#ibcon#about to write, iclass 38, count 0 2006.201.23:42:13.28#ibcon#wrote, iclass 38, count 0 2006.201.23:42:13.28#ibcon#about to read 3, iclass 38, count 0 2006.201.23:42:13.32#ibcon#read 3, iclass 38, count 0 2006.201.23:42:13.32#ibcon#about to read 4, iclass 38, count 0 2006.201.23:42:13.32#ibcon#read 4, iclass 38, count 0 2006.201.23:42:13.32#ibcon#about to read 5, iclass 38, count 0 2006.201.23:42:13.32#ibcon#read 5, iclass 38, count 0 2006.201.23:42:13.32#ibcon#about to read 6, iclass 38, count 0 2006.201.23:42:13.32#ibcon#read 6, iclass 38, count 0 2006.201.23:42:13.32#ibcon#end of sib2, iclass 38, count 0 2006.201.23:42:13.32#ibcon#*after write, iclass 38, count 0 2006.201.23:42:13.32#ibcon#*before return 0, iclass 38, count 0 2006.201.23:42:13.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:13.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:13.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.23:42:13.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.23:42:13.32$vck44/vb=1,4 2006.201.23:42:13.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.201.23:42:13.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.201.23:42:13.32#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:13.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:42:13.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:42:13.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:42:13.32#ibcon#enter wrdev, iclass 40, count 2 2006.201.23:42:13.32#ibcon#first serial, iclass 40, count 2 2006.201.23:42:13.32#ibcon#enter sib2, iclass 40, count 2 2006.201.23:42:13.32#ibcon#flushed, iclass 40, count 2 2006.201.23:42:13.32#ibcon#about to write, iclass 40, count 2 2006.201.23:42:13.32#ibcon#wrote, iclass 40, count 2 2006.201.23:42:13.32#ibcon#about to read 3, iclass 40, count 2 2006.201.23:42:13.34#ibcon#read 3, iclass 40, count 2 2006.201.23:42:13.34#ibcon#about to read 4, iclass 40, count 2 2006.201.23:42:13.34#ibcon#read 4, iclass 40, count 2 2006.201.23:42:13.34#ibcon#about to read 5, iclass 40, count 2 2006.201.23:42:13.34#ibcon#read 5, iclass 40, count 2 2006.201.23:42:13.34#ibcon#about to read 6, iclass 40, count 2 2006.201.23:42:13.34#ibcon#read 6, iclass 40, count 2 2006.201.23:42:13.34#ibcon#end of sib2, iclass 40, count 2 2006.201.23:42:13.34#ibcon#*mode == 0, iclass 40, count 2 2006.201.23:42:13.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.201.23:42:13.34#ibcon#[27=AT01-04\r\n] 2006.201.23:42:13.34#ibcon#*before write, iclass 40, count 2 2006.201.23:42:13.34#ibcon#enter sib2, iclass 40, count 2 2006.201.23:42:13.34#ibcon#flushed, iclass 40, count 2 2006.201.23:42:13.34#ibcon#about to write, iclass 40, count 2 2006.201.23:42:13.34#ibcon#wrote, iclass 40, count 2 2006.201.23:42:13.34#ibcon#about to read 3, iclass 40, count 2 2006.201.23:42:13.37#ibcon#read 3, iclass 40, count 2 2006.201.23:42:13.37#ibcon#about to read 4, iclass 40, count 2 2006.201.23:42:13.37#ibcon#read 4, iclass 40, count 2 2006.201.23:42:13.37#ibcon#about to read 5, iclass 40, count 2 2006.201.23:42:13.37#ibcon#read 5, iclass 40, count 2 2006.201.23:42:13.37#ibcon#about to read 6, iclass 40, count 2 2006.201.23:42:13.37#ibcon#read 6, iclass 40, count 2 2006.201.23:42:13.37#ibcon#end of sib2, iclass 40, count 2 2006.201.23:42:13.37#ibcon#*after write, iclass 40, count 2 2006.201.23:42:13.37#ibcon#*before return 0, iclass 40, count 2 2006.201.23:42:13.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:42:13.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.201.23:42:13.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.201.23:42:13.37#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:13.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:42:13.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:42:13.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:42:13.49#ibcon#enter wrdev, iclass 40, count 0 2006.201.23:42:13.49#ibcon#first serial, iclass 40, count 0 2006.201.23:42:13.49#ibcon#enter sib2, iclass 40, count 0 2006.201.23:42:13.49#ibcon#flushed, iclass 40, count 0 2006.201.23:42:13.49#ibcon#about to write, iclass 40, count 0 2006.201.23:42:13.49#ibcon#wrote, iclass 40, count 0 2006.201.23:42:13.49#ibcon#about to read 3, iclass 40, count 0 2006.201.23:42:13.51#ibcon#read 3, iclass 40, count 0 2006.201.23:42:13.51#ibcon#about to read 4, iclass 40, count 0 2006.201.23:42:13.51#ibcon#read 4, iclass 40, count 0 2006.201.23:42:13.51#ibcon#about to read 5, iclass 40, count 0 2006.201.23:42:13.51#ibcon#read 5, iclass 40, count 0 2006.201.23:42:13.51#ibcon#about to read 6, iclass 40, count 0 2006.201.23:42:13.51#ibcon#read 6, iclass 40, count 0 2006.201.23:42:13.51#ibcon#end of sib2, iclass 40, count 0 2006.201.23:42:13.51#ibcon#*mode == 0, iclass 40, count 0 2006.201.23:42:13.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.23:42:13.51#ibcon#[27=USB\r\n] 2006.201.23:42:13.51#ibcon#*before write, iclass 40, count 0 2006.201.23:42:13.51#ibcon#enter sib2, iclass 40, count 0 2006.201.23:42:13.51#ibcon#flushed, iclass 40, count 0 2006.201.23:42:13.51#ibcon#about to write, iclass 40, count 0 2006.201.23:42:13.51#ibcon#wrote, iclass 40, count 0 2006.201.23:42:13.51#ibcon#about to read 3, iclass 40, count 0 2006.201.23:42:13.54#ibcon#read 3, iclass 40, count 0 2006.201.23:42:13.54#ibcon#about to read 4, iclass 40, count 0 2006.201.23:42:13.54#ibcon#read 4, iclass 40, count 0 2006.201.23:42:13.54#ibcon#about to read 5, iclass 40, count 0 2006.201.23:42:13.54#ibcon#read 5, iclass 40, count 0 2006.201.23:42:13.54#ibcon#about to read 6, iclass 40, count 0 2006.201.23:42:13.54#ibcon#read 6, iclass 40, count 0 2006.201.23:42:13.54#ibcon#end of sib2, iclass 40, count 0 2006.201.23:42:13.54#ibcon#*after write, iclass 40, count 0 2006.201.23:42:13.54#ibcon#*before return 0, iclass 40, count 0 2006.201.23:42:13.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:42:13.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.201.23:42:13.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.23:42:13.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.23:42:13.54$vck44/vblo=2,634.99 2006.201.23:42:13.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.201.23:42:13.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.201.23:42:13.54#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:13.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:13.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:13.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:13.54#ibcon#enter wrdev, iclass 4, count 0 2006.201.23:42:13.54#ibcon#first serial, iclass 4, count 0 2006.201.23:42:13.54#ibcon#enter sib2, iclass 4, count 0 2006.201.23:42:13.54#ibcon#flushed, iclass 4, count 0 2006.201.23:42:13.54#ibcon#about to write, iclass 4, count 0 2006.201.23:42:13.54#ibcon#wrote, iclass 4, count 0 2006.201.23:42:13.54#ibcon#about to read 3, iclass 4, count 0 2006.201.23:42:13.56#ibcon#read 3, iclass 4, count 0 2006.201.23:42:13.56#ibcon#about to read 4, iclass 4, count 0 2006.201.23:42:13.56#ibcon#read 4, iclass 4, count 0 2006.201.23:42:13.56#ibcon#about to read 5, iclass 4, count 0 2006.201.23:42:13.56#ibcon#read 5, iclass 4, count 0 2006.201.23:42:13.56#ibcon#about to read 6, iclass 4, count 0 2006.201.23:42:13.56#ibcon#read 6, iclass 4, count 0 2006.201.23:42:13.56#ibcon#end of sib2, iclass 4, count 0 2006.201.23:42:13.56#ibcon#*mode == 0, iclass 4, count 0 2006.201.23:42:13.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.23:42:13.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.23:42:13.56#ibcon#*before write, iclass 4, count 0 2006.201.23:42:13.56#ibcon#enter sib2, iclass 4, count 0 2006.201.23:42:13.56#ibcon#flushed, iclass 4, count 0 2006.201.23:42:13.56#ibcon#about to write, iclass 4, count 0 2006.201.23:42:13.56#ibcon#wrote, iclass 4, count 0 2006.201.23:42:13.56#ibcon#about to read 3, iclass 4, count 0 2006.201.23:42:13.60#ibcon#read 3, iclass 4, count 0 2006.201.23:42:13.60#ibcon#about to read 4, iclass 4, count 0 2006.201.23:42:13.60#ibcon#read 4, iclass 4, count 0 2006.201.23:42:13.60#ibcon#about to read 5, iclass 4, count 0 2006.201.23:42:13.60#ibcon#read 5, iclass 4, count 0 2006.201.23:42:13.60#ibcon#about to read 6, iclass 4, count 0 2006.201.23:42:13.60#ibcon#read 6, iclass 4, count 0 2006.201.23:42:13.60#ibcon#end of sib2, iclass 4, count 0 2006.201.23:42:13.60#ibcon#*after write, iclass 4, count 0 2006.201.23:42:13.60#ibcon#*before return 0, iclass 4, count 0 2006.201.23:42:13.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:13.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.201.23:42:13.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.23:42:13.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.23:42:13.60$vck44/vb=2,5 2006.201.23:42:13.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.201.23:42:13.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.201.23:42:13.60#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:13.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:13.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:13.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:13.66#ibcon#enter wrdev, iclass 6, count 2 2006.201.23:42:13.66#ibcon#first serial, iclass 6, count 2 2006.201.23:42:13.66#ibcon#enter sib2, iclass 6, count 2 2006.201.23:42:13.66#ibcon#flushed, iclass 6, count 2 2006.201.23:42:13.66#ibcon#about to write, iclass 6, count 2 2006.201.23:42:13.66#ibcon#wrote, iclass 6, count 2 2006.201.23:42:13.66#ibcon#about to read 3, iclass 6, count 2 2006.201.23:42:13.68#ibcon#read 3, iclass 6, count 2 2006.201.23:42:13.68#ibcon#about to read 4, iclass 6, count 2 2006.201.23:42:13.68#ibcon#read 4, iclass 6, count 2 2006.201.23:42:13.68#ibcon#about to read 5, iclass 6, count 2 2006.201.23:42:13.68#ibcon#read 5, iclass 6, count 2 2006.201.23:42:13.68#ibcon#about to read 6, iclass 6, count 2 2006.201.23:42:13.68#ibcon#read 6, iclass 6, count 2 2006.201.23:42:13.68#ibcon#end of sib2, iclass 6, count 2 2006.201.23:42:13.68#ibcon#*mode == 0, iclass 6, count 2 2006.201.23:42:13.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.201.23:42:13.68#ibcon#[27=AT02-05\r\n] 2006.201.23:42:13.68#ibcon#*before write, iclass 6, count 2 2006.201.23:42:13.68#ibcon#enter sib2, iclass 6, count 2 2006.201.23:42:13.68#ibcon#flushed, iclass 6, count 2 2006.201.23:42:13.68#ibcon#about to write, iclass 6, count 2 2006.201.23:42:13.68#ibcon#wrote, iclass 6, count 2 2006.201.23:42:13.68#ibcon#about to read 3, iclass 6, count 2 2006.201.23:42:13.71#ibcon#read 3, iclass 6, count 2 2006.201.23:42:13.71#ibcon#about to read 4, iclass 6, count 2 2006.201.23:42:13.71#ibcon#read 4, iclass 6, count 2 2006.201.23:42:13.71#ibcon#about to read 5, iclass 6, count 2 2006.201.23:42:13.71#ibcon#read 5, iclass 6, count 2 2006.201.23:42:13.71#ibcon#about to read 6, iclass 6, count 2 2006.201.23:42:13.71#ibcon#read 6, iclass 6, count 2 2006.201.23:42:13.71#ibcon#end of sib2, iclass 6, count 2 2006.201.23:42:13.71#ibcon#*after write, iclass 6, count 2 2006.201.23:42:13.71#ibcon#*before return 0, iclass 6, count 2 2006.201.23:42:13.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:13.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.201.23:42:13.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.201.23:42:13.71#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:13.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:13.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:13.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:13.83#ibcon#enter wrdev, iclass 6, count 0 2006.201.23:42:13.83#ibcon#first serial, iclass 6, count 0 2006.201.23:42:13.83#ibcon#enter sib2, iclass 6, count 0 2006.201.23:42:13.83#ibcon#flushed, iclass 6, count 0 2006.201.23:42:13.83#ibcon#about to write, iclass 6, count 0 2006.201.23:42:13.83#ibcon#wrote, iclass 6, count 0 2006.201.23:42:13.83#ibcon#about to read 3, iclass 6, count 0 2006.201.23:42:13.85#ibcon#read 3, iclass 6, count 0 2006.201.23:42:13.85#ibcon#about to read 4, iclass 6, count 0 2006.201.23:42:13.85#ibcon#read 4, iclass 6, count 0 2006.201.23:42:13.85#ibcon#about to read 5, iclass 6, count 0 2006.201.23:42:13.85#ibcon#read 5, iclass 6, count 0 2006.201.23:42:13.85#ibcon#about to read 6, iclass 6, count 0 2006.201.23:42:13.85#ibcon#read 6, iclass 6, count 0 2006.201.23:42:13.85#ibcon#end of sib2, iclass 6, count 0 2006.201.23:42:13.85#ibcon#*mode == 0, iclass 6, count 0 2006.201.23:42:13.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.23:42:13.85#ibcon#[27=USB\r\n] 2006.201.23:42:13.85#ibcon#*before write, iclass 6, count 0 2006.201.23:42:13.85#ibcon#enter sib2, iclass 6, count 0 2006.201.23:42:13.85#ibcon#flushed, iclass 6, count 0 2006.201.23:42:13.85#ibcon#about to write, iclass 6, count 0 2006.201.23:42:13.85#ibcon#wrote, iclass 6, count 0 2006.201.23:42:13.85#ibcon#about to read 3, iclass 6, count 0 2006.201.23:42:13.88#ibcon#read 3, iclass 6, count 0 2006.201.23:42:13.88#ibcon#about to read 4, iclass 6, count 0 2006.201.23:42:13.88#ibcon#read 4, iclass 6, count 0 2006.201.23:42:13.88#ibcon#about to read 5, iclass 6, count 0 2006.201.23:42:13.88#ibcon#read 5, iclass 6, count 0 2006.201.23:42:13.88#ibcon#about to read 6, iclass 6, count 0 2006.201.23:42:13.88#ibcon#read 6, iclass 6, count 0 2006.201.23:42:13.88#ibcon#end of sib2, iclass 6, count 0 2006.201.23:42:13.88#ibcon#*after write, iclass 6, count 0 2006.201.23:42:13.88#ibcon#*before return 0, iclass 6, count 0 2006.201.23:42:13.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:13.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.201.23:42:13.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.23:42:13.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.23:42:13.88$vck44/vblo=3,649.99 2006.201.23:42:13.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.201.23:42:13.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.201.23:42:13.88#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:13.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:13.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:13.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:13.88#ibcon#enter wrdev, iclass 10, count 0 2006.201.23:42:13.88#ibcon#first serial, iclass 10, count 0 2006.201.23:42:13.88#ibcon#enter sib2, iclass 10, count 0 2006.201.23:42:13.88#ibcon#flushed, iclass 10, count 0 2006.201.23:42:13.88#ibcon#about to write, iclass 10, count 0 2006.201.23:42:13.88#ibcon#wrote, iclass 10, count 0 2006.201.23:42:13.88#ibcon#about to read 3, iclass 10, count 0 2006.201.23:42:13.90#ibcon#read 3, iclass 10, count 0 2006.201.23:42:13.90#ibcon#about to read 4, iclass 10, count 0 2006.201.23:42:13.90#ibcon#read 4, iclass 10, count 0 2006.201.23:42:13.90#ibcon#about to read 5, iclass 10, count 0 2006.201.23:42:13.90#ibcon#read 5, iclass 10, count 0 2006.201.23:42:13.90#ibcon#about to read 6, iclass 10, count 0 2006.201.23:42:13.90#ibcon#read 6, iclass 10, count 0 2006.201.23:42:13.90#ibcon#end of sib2, iclass 10, count 0 2006.201.23:42:13.90#ibcon#*mode == 0, iclass 10, count 0 2006.201.23:42:13.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.23:42:13.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.23:42:13.90#ibcon#*before write, iclass 10, count 0 2006.201.23:42:13.90#ibcon#enter sib2, iclass 10, count 0 2006.201.23:42:13.90#ibcon#flushed, iclass 10, count 0 2006.201.23:42:13.90#ibcon#about to write, iclass 10, count 0 2006.201.23:42:13.90#ibcon#wrote, iclass 10, count 0 2006.201.23:42:13.90#ibcon#about to read 3, iclass 10, count 0 2006.201.23:42:13.94#ibcon#read 3, iclass 10, count 0 2006.201.23:42:13.94#ibcon#about to read 4, iclass 10, count 0 2006.201.23:42:13.94#ibcon#read 4, iclass 10, count 0 2006.201.23:42:13.94#ibcon#about to read 5, iclass 10, count 0 2006.201.23:42:13.94#ibcon#read 5, iclass 10, count 0 2006.201.23:42:13.94#ibcon#about to read 6, iclass 10, count 0 2006.201.23:42:13.94#ibcon#read 6, iclass 10, count 0 2006.201.23:42:13.94#ibcon#end of sib2, iclass 10, count 0 2006.201.23:42:13.94#ibcon#*after write, iclass 10, count 0 2006.201.23:42:13.94#ibcon#*before return 0, iclass 10, count 0 2006.201.23:42:13.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:13.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.201.23:42:13.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.23:42:13.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.23:42:13.94$vck44/vb=3,4 2006.201.23:42:13.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.201.23:42:13.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.201.23:42:13.94#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:13.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:14.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:14.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:14.00#ibcon#enter wrdev, iclass 12, count 2 2006.201.23:42:14.00#ibcon#first serial, iclass 12, count 2 2006.201.23:42:14.00#ibcon#enter sib2, iclass 12, count 2 2006.201.23:42:14.00#ibcon#flushed, iclass 12, count 2 2006.201.23:42:14.00#ibcon#about to write, iclass 12, count 2 2006.201.23:42:14.00#ibcon#wrote, iclass 12, count 2 2006.201.23:42:14.00#ibcon#about to read 3, iclass 12, count 2 2006.201.23:42:14.02#ibcon#read 3, iclass 12, count 2 2006.201.23:42:14.02#ibcon#about to read 4, iclass 12, count 2 2006.201.23:42:14.02#ibcon#read 4, iclass 12, count 2 2006.201.23:42:14.02#ibcon#about to read 5, iclass 12, count 2 2006.201.23:42:14.02#ibcon#read 5, iclass 12, count 2 2006.201.23:42:14.02#ibcon#about to read 6, iclass 12, count 2 2006.201.23:42:14.02#ibcon#read 6, iclass 12, count 2 2006.201.23:42:14.02#ibcon#end of sib2, iclass 12, count 2 2006.201.23:42:14.02#ibcon#*mode == 0, iclass 12, count 2 2006.201.23:42:14.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.201.23:42:14.02#ibcon#[27=AT03-04\r\n] 2006.201.23:42:14.02#ibcon#*before write, iclass 12, count 2 2006.201.23:42:14.02#ibcon#enter sib2, iclass 12, count 2 2006.201.23:42:14.02#ibcon#flushed, iclass 12, count 2 2006.201.23:42:14.02#ibcon#about to write, iclass 12, count 2 2006.201.23:42:14.02#ibcon#wrote, iclass 12, count 2 2006.201.23:42:14.02#ibcon#about to read 3, iclass 12, count 2 2006.201.23:42:14.05#ibcon#read 3, iclass 12, count 2 2006.201.23:42:14.05#ibcon#about to read 4, iclass 12, count 2 2006.201.23:42:14.05#ibcon#read 4, iclass 12, count 2 2006.201.23:42:14.05#ibcon#about to read 5, iclass 12, count 2 2006.201.23:42:14.05#ibcon#read 5, iclass 12, count 2 2006.201.23:42:14.05#ibcon#about to read 6, iclass 12, count 2 2006.201.23:42:14.05#ibcon#read 6, iclass 12, count 2 2006.201.23:42:14.05#ibcon#end of sib2, iclass 12, count 2 2006.201.23:42:14.05#ibcon#*after write, iclass 12, count 2 2006.201.23:42:14.05#ibcon#*before return 0, iclass 12, count 2 2006.201.23:42:14.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:14.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.201.23:42:14.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.201.23:42:14.05#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:14.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:14.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:14.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:14.17#ibcon#enter wrdev, iclass 12, count 0 2006.201.23:42:14.17#ibcon#first serial, iclass 12, count 0 2006.201.23:42:14.17#ibcon#enter sib2, iclass 12, count 0 2006.201.23:42:14.17#ibcon#flushed, iclass 12, count 0 2006.201.23:42:14.17#ibcon#about to write, iclass 12, count 0 2006.201.23:42:14.17#ibcon#wrote, iclass 12, count 0 2006.201.23:42:14.17#ibcon#about to read 3, iclass 12, count 0 2006.201.23:42:14.19#ibcon#read 3, iclass 12, count 0 2006.201.23:42:14.19#ibcon#about to read 4, iclass 12, count 0 2006.201.23:42:14.19#ibcon#read 4, iclass 12, count 0 2006.201.23:42:14.19#ibcon#about to read 5, iclass 12, count 0 2006.201.23:42:14.19#ibcon#read 5, iclass 12, count 0 2006.201.23:42:14.19#ibcon#about to read 6, iclass 12, count 0 2006.201.23:42:14.19#ibcon#read 6, iclass 12, count 0 2006.201.23:42:14.19#ibcon#end of sib2, iclass 12, count 0 2006.201.23:42:14.19#ibcon#*mode == 0, iclass 12, count 0 2006.201.23:42:14.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.23:42:14.19#ibcon#[27=USB\r\n] 2006.201.23:42:14.19#ibcon#*before write, iclass 12, count 0 2006.201.23:42:14.19#ibcon#enter sib2, iclass 12, count 0 2006.201.23:42:14.19#ibcon#flushed, iclass 12, count 0 2006.201.23:42:14.19#ibcon#about to write, iclass 12, count 0 2006.201.23:42:14.19#ibcon#wrote, iclass 12, count 0 2006.201.23:42:14.19#ibcon#about to read 3, iclass 12, count 0 2006.201.23:42:14.22#ibcon#read 3, iclass 12, count 0 2006.201.23:42:14.22#ibcon#about to read 4, iclass 12, count 0 2006.201.23:42:14.22#ibcon#read 4, iclass 12, count 0 2006.201.23:42:14.22#ibcon#about to read 5, iclass 12, count 0 2006.201.23:42:14.22#ibcon#read 5, iclass 12, count 0 2006.201.23:42:14.22#ibcon#about to read 6, iclass 12, count 0 2006.201.23:42:14.22#ibcon#read 6, iclass 12, count 0 2006.201.23:42:14.22#ibcon#end of sib2, iclass 12, count 0 2006.201.23:42:14.22#ibcon#*after write, iclass 12, count 0 2006.201.23:42:14.22#ibcon#*before return 0, iclass 12, count 0 2006.201.23:42:14.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:14.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.201.23:42:14.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.23:42:14.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.23:42:14.22$vck44/vblo=4,679.99 2006.201.23:42:14.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.201.23:42:14.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.201.23:42:14.22#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:14.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:14.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:14.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:14.22#ibcon#enter wrdev, iclass 14, count 0 2006.201.23:42:14.22#ibcon#first serial, iclass 14, count 0 2006.201.23:42:14.22#ibcon#enter sib2, iclass 14, count 0 2006.201.23:42:14.22#ibcon#flushed, iclass 14, count 0 2006.201.23:42:14.22#ibcon#about to write, iclass 14, count 0 2006.201.23:42:14.22#ibcon#wrote, iclass 14, count 0 2006.201.23:42:14.22#ibcon#about to read 3, iclass 14, count 0 2006.201.23:42:14.24#ibcon#read 3, iclass 14, count 0 2006.201.23:42:14.24#ibcon#about to read 4, iclass 14, count 0 2006.201.23:42:14.24#ibcon#read 4, iclass 14, count 0 2006.201.23:42:14.24#ibcon#about to read 5, iclass 14, count 0 2006.201.23:42:14.24#ibcon#read 5, iclass 14, count 0 2006.201.23:42:14.24#ibcon#about to read 6, iclass 14, count 0 2006.201.23:42:14.24#ibcon#read 6, iclass 14, count 0 2006.201.23:42:14.24#ibcon#end of sib2, iclass 14, count 0 2006.201.23:42:14.24#ibcon#*mode == 0, iclass 14, count 0 2006.201.23:42:14.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.23:42:14.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.23:42:14.24#ibcon#*before write, iclass 14, count 0 2006.201.23:42:14.24#ibcon#enter sib2, iclass 14, count 0 2006.201.23:42:14.24#ibcon#flushed, iclass 14, count 0 2006.201.23:42:14.24#ibcon#about to write, iclass 14, count 0 2006.201.23:42:14.24#ibcon#wrote, iclass 14, count 0 2006.201.23:42:14.24#ibcon#about to read 3, iclass 14, count 0 2006.201.23:42:14.28#ibcon#read 3, iclass 14, count 0 2006.201.23:42:14.28#ibcon#about to read 4, iclass 14, count 0 2006.201.23:42:14.28#ibcon#read 4, iclass 14, count 0 2006.201.23:42:14.28#ibcon#about to read 5, iclass 14, count 0 2006.201.23:42:14.28#ibcon#read 5, iclass 14, count 0 2006.201.23:42:14.28#ibcon#about to read 6, iclass 14, count 0 2006.201.23:42:14.28#ibcon#read 6, iclass 14, count 0 2006.201.23:42:14.28#ibcon#end of sib2, iclass 14, count 0 2006.201.23:42:14.28#ibcon#*after write, iclass 14, count 0 2006.201.23:42:14.28#ibcon#*before return 0, iclass 14, count 0 2006.201.23:42:14.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:14.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.201.23:42:14.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.23:42:14.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.23:42:14.28$vck44/vb=4,5 2006.201.23:42:14.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.201.23:42:14.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.201.23:42:14.28#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:14.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:42:14.32#abcon#<5=/03 0.8 2.1 20.321001001.6\r\n> 2006.201.23:42:14.34#abcon#{5=INTERFACE CLEAR} 2006.201.23:42:14.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:42:14.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:42:14.34#ibcon#enter wrdev, iclass 17, count 2 2006.201.23:42:14.34#ibcon#first serial, iclass 17, count 2 2006.201.23:42:14.34#ibcon#enter sib2, iclass 17, count 2 2006.201.23:42:14.34#ibcon#flushed, iclass 17, count 2 2006.201.23:42:14.34#ibcon#about to write, iclass 17, count 2 2006.201.23:42:14.34#ibcon#wrote, iclass 17, count 2 2006.201.23:42:14.34#ibcon#about to read 3, iclass 17, count 2 2006.201.23:42:14.36#ibcon#read 3, iclass 17, count 2 2006.201.23:42:14.36#ibcon#about to read 4, iclass 17, count 2 2006.201.23:42:14.36#ibcon#read 4, iclass 17, count 2 2006.201.23:42:14.36#ibcon#about to read 5, iclass 17, count 2 2006.201.23:42:14.36#ibcon#read 5, iclass 17, count 2 2006.201.23:42:14.36#ibcon#about to read 6, iclass 17, count 2 2006.201.23:42:14.36#ibcon#read 6, iclass 17, count 2 2006.201.23:42:14.36#ibcon#end of sib2, iclass 17, count 2 2006.201.23:42:14.36#ibcon#*mode == 0, iclass 17, count 2 2006.201.23:42:14.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.201.23:42:14.36#ibcon#[27=AT04-05\r\n] 2006.201.23:42:14.36#ibcon#*before write, iclass 17, count 2 2006.201.23:42:14.36#ibcon#enter sib2, iclass 17, count 2 2006.201.23:42:14.36#ibcon#flushed, iclass 17, count 2 2006.201.23:42:14.36#ibcon#about to write, iclass 17, count 2 2006.201.23:42:14.36#ibcon#wrote, iclass 17, count 2 2006.201.23:42:14.36#ibcon#about to read 3, iclass 17, count 2 2006.201.23:42:14.39#ibcon#read 3, iclass 17, count 2 2006.201.23:42:14.39#ibcon#about to read 4, iclass 17, count 2 2006.201.23:42:14.39#ibcon#read 4, iclass 17, count 2 2006.201.23:42:14.39#ibcon#about to read 5, iclass 17, count 2 2006.201.23:42:14.39#ibcon#read 5, iclass 17, count 2 2006.201.23:42:14.39#ibcon#about to read 6, iclass 17, count 2 2006.201.23:42:14.39#ibcon#read 6, iclass 17, count 2 2006.201.23:42:14.39#ibcon#end of sib2, iclass 17, count 2 2006.201.23:42:14.39#ibcon#*after write, iclass 17, count 2 2006.201.23:42:14.39#ibcon#*before return 0, iclass 17, count 2 2006.201.23:42:14.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:42:14.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.201.23:42:14.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.201.23:42:14.39#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:14.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:42:14.40#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:42:14.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:42:14.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:42:14.51#ibcon#enter wrdev, iclass 17, count 0 2006.201.23:42:14.51#ibcon#first serial, iclass 17, count 0 2006.201.23:42:14.51#ibcon#enter sib2, iclass 17, count 0 2006.201.23:42:14.51#ibcon#flushed, iclass 17, count 0 2006.201.23:42:14.51#ibcon#about to write, iclass 17, count 0 2006.201.23:42:14.51#ibcon#wrote, iclass 17, count 0 2006.201.23:42:14.51#ibcon#about to read 3, iclass 17, count 0 2006.201.23:42:14.53#ibcon#read 3, iclass 17, count 0 2006.201.23:42:14.53#ibcon#about to read 4, iclass 17, count 0 2006.201.23:42:14.53#ibcon#read 4, iclass 17, count 0 2006.201.23:42:14.53#ibcon#about to read 5, iclass 17, count 0 2006.201.23:42:14.53#ibcon#read 5, iclass 17, count 0 2006.201.23:42:14.53#ibcon#about to read 6, iclass 17, count 0 2006.201.23:42:14.53#ibcon#read 6, iclass 17, count 0 2006.201.23:42:14.53#ibcon#end of sib2, iclass 17, count 0 2006.201.23:42:14.53#ibcon#*mode == 0, iclass 17, count 0 2006.201.23:42:14.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.23:42:14.53#ibcon#[27=USB\r\n] 2006.201.23:42:14.53#ibcon#*before write, iclass 17, count 0 2006.201.23:42:14.53#ibcon#enter sib2, iclass 17, count 0 2006.201.23:42:14.53#ibcon#flushed, iclass 17, count 0 2006.201.23:42:14.53#ibcon#about to write, iclass 17, count 0 2006.201.23:42:14.53#ibcon#wrote, iclass 17, count 0 2006.201.23:42:14.53#ibcon#about to read 3, iclass 17, count 0 2006.201.23:42:14.56#ibcon#read 3, iclass 17, count 0 2006.201.23:42:14.56#ibcon#about to read 4, iclass 17, count 0 2006.201.23:42:14.56#ibcon#read 4, iclass 17, count 0 2006.201.23:42:14.56#ibcon#about to read 5, iclass 17, count 0 2006.201.23:42:14.56#ibcon#read 5, iclass 17, count 0 2006.201.23:42:14.56#ibcon#about to read 6, iclass 17, count 0 2006.201.23:42:14.56#ibcon#read 6, iclass 17, count 0 2006.201.23:42:14.56#ibcon#end of sib2, iclass 17, count 0 2006.201.23:42:14.56#ibcon#*after write, iclass 17, count 0 2006.201.23:42:14.56#ibcon#*before return 0, iclass 17, count 0 2006.201.23:42:14.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:42:14.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.201.23:42:14.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.23:42:14.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.23:42:14.56$vck44/vblo=5,709.99 2006.201.23:42:14.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.201.23:42:14.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.201.23:42:14.56#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:14.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:14.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:14.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:14.56#ibcon#enter wrdev, iclass 22, count 0 2006.201.23:42:14.56#ibcon#first serial, iclass 22, count 0 2006.201.23:42:14.56#ibcon#enter sib2, iclass 22, count 0 2006.201.23:42:14.56#ibcon#flushed, iclass 22, count 0 2006.201.23:42:14.56#ibcon#about to write, iclass 22, count 0 2006.201.23:42:14.56#ibcon#wrote, iclass 22, count 0 2006.201.23:42:14.56#ibcon#about to read 3, iclass 22, count 0 2006.201.23:42:14.58#ibcon#read 3, iclass 22, count 0 2006.201.23:42:14.58#ibcon#about to read 4, iclass 22, count 0 2006.201.23:42:14.58#ibcon#read 4, iclass 22, count 0 2006.201.23:42:14.58#ibcon#about to read 5, iclass 22, count 0 2006.201.23:42:14.58#ibcon#read 5, iclass 22, count 0 2006.201.23:42:14.58#ibcon#about to read 6, iclass 22, count 0 2006.201.23:42:14.58#ibcon#read 6, iclass 22, count 0 2006.201.23:42:14.58#ibcon#end of sib2, iclass 22, count 0 2006.201.23:42:14.58#ibcon#*mode == 0, iclass 22, count 0 2006.201.23:42:14.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.23:42:14.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.23:42:14.58#ibcon#*before write, iclass 22, count 0 2006.201.23:42:14.58#ibcon#enter sib2, iclass 22, count 0 2006.201.23:42:14.58#ibcon#flushed, iclass 22, count 0 2006.201.23:42:14.58#ibcon#about to write, iclass 22, count 0 2006.201.23:42:14.58#ibcon#wrote, iclass 22, count 0 2006.201.23:42:14.58#ibcon#about to read 3, iclass 22, count 0 2006.201.23:42:14.62#ibcon#read 3, iclass 22, count 0 2006.201.23:42:14.62#ibcon#about to read 4, iclass 22, count 0 2006.201.23:42:14.62#ibcon#read 4, iclass 22, count 0 2006.201.23:42:14.62#ibcon#about to read 5, iclass 22, count 0 2006.201.23:42:14.62#ibcon#read 5, iclass 22, count 0 2006.201.23:42:14.62#ibcon#about to read 6, iclass 22, count 0 2006.201.23:42:14.62#ibcon#read 6, iclass 22, count 0 2006.201.23:42:14.62#ibcon#end of sib2, iclass 22, count 0 2006.201.23:42:14.62#ibcon#*after write, iclass 22, count 0 2006.201.23:42:14.62#ibcon#*before return 0, iclass 22, count 0 2006.201.23:42:14.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:14.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.201.23:42:14.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.23:42:14.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.23:42:14.62$vck44/vb=5,4 2006.201.23:42:14.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.201.23:42:14.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.201.23:42:14.62#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:14.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:14.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:14.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:14.68#ibcon#enter wrdev, iclass 24, count 2 2006.201.23:42:14.68#ibcon#first serial, iclass 24, count 2 2006.201.23:42:14.68#ibcon#enter sib2, iclass 24, count 2 2006.201.23:42:14.68#ibcon#flushed, iclass 24, count 2 2006.201.23:42:14.68#ibcon#about to write, iclass 24, count 2 2006.201.23:42:14.68#ibcon#wrote, iclass 24, count 2 2006.201.23:42:14.68#ibcon#about to read 3, iclass 24, count 2 2006.201.23:42:14.70#ibcon#read 3, iclass 24, count 2 2006.201.23:42:14.70#ibcon#about to read 4, iclass 24, count 2 2006.201.23:42:14.70#ibcon#read 4, iclass 24, count 2 2006.201.23:42:14.70#ibcon#about to read 5, iclass 24, count 2 2006.201.23:42:14.70#ibcon#read 5, iclass 24, count 2 2006.201.23:42:14.70#ibcon#about to read 6, iclass 24, count 2 2006.201.23:42:14.70#ibcon#read 6, iclass 24, count 2 2006.201.23:42:14.70#ibcon#end of sib2, iclass 24, count 2 2006.201.23:42:14.70#ibcon#*mode == 0, iclass 24, count 2 2006.201.23:42:14.70#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.201.23:42:14.70#ibcon#[27=AT05-04\r\n] 2006.201.23:42:14.70#ibcon#*before write, iclass 24, count 2 2006.201.23:42:14.70#ibcon#enter sib2, iclass 24, count 2 2006.201.23:42:14.70#ibcon#flushed, iclass 24, count 2 2006.201.23:42:14.70#ibcon#about to write, iclass 24, count 2 2006.201.23:42:14.70#ibcon#wrote, iclass 24, count 2 2006.201.23:42:14.70#ibcon#about to read 3, iclass 24, count 2 2006.201.23:42:14.73#ibcon#read 3, iclass 24, count 2 2006.201.23:42:14.73#ibcon#about to read 4, iclass 24, count 2 2006.201.23:42:14.73#ibcon#read 4, iclass 24, count 2 2006.201.23:42:14.73#ibcon#about to read 5, iclass 24, count 2 2006.201.23:42:14.73#ibcon#read 5, iclass 24, count 2 2006.201.23:42:14.73#ibcon#about to read 6, iclass 24, count 2 2006.201.23:42:14.73#ibcon#read 6, iclass 24, count 2 2006.201.23:42:14.73#ibcon#end of sib2, iclass 24, count 2 2006.201.23:42:14.73#ibcon#*after write, iclass 24, count 2 2006.201.23:42:14.73#ibcon#*before return 0, iclass 24, count 2 2006.201.23:42:14.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:14.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.201.23:42:14.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.201.23:42:14.73#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:14.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:14.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:14.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:14.85#ibcon#enter wrdev, iclass 24, count 0 2006.201.23:42:14.85#ibcon#first serial, iclass 24, count 0 2006.201.23:42:14.85#ibcon#enter sib2, iclass 24, count 0 2006.201.23:42:14.85#ibcon#flushed, iclass 24, count 0 2006.201.23:42:14.85#ibcon#about to write, iclass 24, count 0 2006.201.23:42:14.85#ibcon#wrote, iclass 24, count 0 2006.201.23:42:14.85#ibcon#about to read 3, iclass 24, count 0 2006.201.23:42:14.87#ibcon#read 3, iclass 24, count 0 2006.201.23:42:14.87#ibcon#about to read 4, iclass 24, count 0 2006.201.23:42:14.87#ibcon#read 4, iclass 24, count 0 2006.201.23:42:14.87#ibcon#about to read 5, iclass 24, count 0 2006.201.23:42:14.87#ibcon#read 5, iclass 24, count 0 2006.201.23:42:14.87#ibcon#about to read 6, iclass 24, count 0 2006.201.23:42:14.87#ibcon#read 6, iclass 24, count 0 2006.201.23:42:14.87#ibcon#end of sib2, iclass 24, count 0 2006.201.23:42:14.87#ibcon#*mode == 0, iclass 24, count 0 2006.201.23:42:14.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.23:42:14.87#ibcon#[27=USB\r\n] 2006.201.23:42:14.87#ibcon#*before write, iclass 24, count 0 2006.201.23:42:14.87#ibcon#enter sib2, iclass 24, count 0 2006.201.23:42:14.87#ibcon#flushed, iclass 24, count 0 2006.201.23:42:14.87#ibcon#about to write, iclass 24, count 0 2006.201.23:42:14.87#ibcon#wrote, iclass 24, count 0 2006.201.23:42:14.87#ibcon#about to read 3, iclass 24, count 0 2006.201.23:42:14.90#ibcon#read 3, iclass 24, count 0 2006.201.23:42:14.90#ibcon#about to read 4, iclass 24, count 0 2006.201.23:42:14.90#ibcon#read 4, iclass 24, count 0 2006.201.23:42:14.90#ibcon#about to read 5, iclass 24, count 0 2006.201.23:42:14.90#ibcon#read 5, iclass 24, count 0 2006.201.23:42:14.90#ibcon#about to read 6, iclass 24, count 0 2006.201.23:42:14.90#ibcon#read 6, iclass 24, count 0 2006.201.23:42:14.90#ibcon#end of sib2, iclass 24, count 0 2006.201.23:42:14.90#ibcon#*after write, iclass 24, count 0 2006.201.23:42:14.90#ibcon#*before return 0, iclass 24, count 0 2006.201.23:42:14.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:14.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.201.23:42:14.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.23:42:14.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.23:42:14.90$vck44/vblo=6,719.99 2006.201.23:42:14.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.23:42:14.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.23:42:14.90#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:14.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:14.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:14.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:14.90#ibcon#enter wrdev, iclass 26, count 0 2006.201.23:42:14.90#ibcon#first serial, iclass 26, count 0 2006.201.23:42:14.90#ibcon#enter sib2, iclass 26, count 0 2006.201.23:42:14.90#ibcon#flushed, iclass 26, count 0 2006.201.23:42:14.90#ibcon#about to write, iclass 26, count 0 2006.201.23:42:14.90#ibcon#wrote, iclass 26, count 0 2006.201.23:42:14.90#ibcon#about to read 3, iclass 26, count 0 2006.201.23:42:14.92#ibcon#read 3, iclass 26, count 0 2006.201.23:42:14.92#ibcon#about to read 4, iclass 26, count 0 2006.201.23:42:14.92#ibcon#read 4, iclass 26, count 0 2006.201.23:42:14.92#ibcon#about to read 5, iclass 26, count 0 2006.201.23:42:14.92#ibcon#read 5, iclass 26, count 0 2006.201.23:42:14.92#ibcon#about to read 6, iclass 26, count 0 2006.201.23:42:14.92#ibcon#read 6, iclass 26, count 0 2006.201.23:42:14.92#ibcon#end of sib2, iclass 26, count 0 2006.201.23:42:14.92#ibcon#*mode == 0, iclass 26, count 0 2006.201.23:42:14.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.23:42:14.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.23:42:14.92#ibcon#*before write, iclass 26, count 0 2006.201.23:42:14.92#ibcon#enter sib2, iclass 26, count 0 2006.201.23:42:14.92#ibcon#flushed, iclass 26, count 0 2006.201.23:42:14.92#ibcon#about to write, iclass 26, count 0 2006.201.23:42:14.92#ibcon#wrote, iclass 26, count 0 2006.201.23:42:14.92#ibcon#about to read 3, iclass 26, count 0 2006.201.23:42:14.96#ibcon#read 3, iclass 26, count 0 2006.201.23:42:14.96#ibcon#about to read 4, iclass 26, count 0 2006.201.23:42:14.96#ibcon#read 4, iclass 26, count 0 2006.201.23:42:14.96#ibcon#about to read 5, iclass 26, count 0 2006.201.23:42:14.96#ibcon#read 5, iclass 26, count 0 2006.201.23:42:14.96#ibcon#about to read 6, iclass 26, count 0 2006.201.23:42:14.96#ibcon#read 6, iclass 26, count 0 2006.201.23:42:14.96#ibcon#end of sib2, iclass 26, count 0 2006.201.23:42:14.96#ibcon#*after write, iclass 26, count 0 2006.201.23:42:14.96#ibcon#*before return 0, iclass 26, count 0 2006.201.23:42:14.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:14.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:42:14.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.23:42:14.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.23:42:14.96$vck44/vb=6,4 2006.201.23:42:14.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.201.23:42:14.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.201.23:42:14.96#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:14.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:15.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:15.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:15.02#ibcon#enter wrdev, iclass 28, count 2 2006.201.23:42:15.02#ibcon#first serial, iclass 28, count 2 2006.201.23:42:15.02#ibcon#enter sib2, iclass 28, count 2 2006.201.23:42:15.02#ibcon#flushed, iclass 28, count 2 2006.201.23:42:15.02#ibcon#about to write, iclass 28, count 2 2006.201.23:42:15.02#ibcon#wrote, iclass 28, count 2 2006.201.23:42:15.02#ibcon#about to read 3, iclass 28, count 2 2006.201.23:42:15.04#ibcon#read 3, iclass 28, count 2 2006.201.23:42:15.04#ibcon#about to read 4, iclass 28, count 2 2006.201.23:42:15.04#ibcon#read 4, iclass 28, count 2 2006.201.23:42:15.04#ibcon#about to read 5, iclass 28, count 2 2006.201.23:42:15.04#ibcon#read 5, iclass 28, count 2 2006.201.23:42:15.04#ibcon#about to read 6, iclass 28, count 2 2006.201.23:42:15.04#ibcon#read 6, iclass 28, count 2 2006.201.23:42:15.04#ibcon#end of sib2, iclass 28, count 2 2006.201.23:42:15.04#ibcon#*mode == 0, iclass 28, count 2 2006.201.23:42:15.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.201.23:42:15.04#ibcon#[27=AT06-04\r\n] 2006.201.23:42:15.04#ibcon#*before write, iclass 28, count 2 2006.201.23:42:15.04#ibcon#enter sib2, iclass 28, count 2 2006.201.23:42:15.04#ibcon#flushed, iclass 28, count 2 2006.201.23:42:15.04#ibcon#about to write, iclass 28, count 2 2006.201.23:42:15.04#ibcon#wrote, iclass 28, count 2 2006.201.23:42:15.04#ibcon#about to read 3, iclass 28, count 2 2006.201.23:42:15.07#ibcon#read 3, iclass 28, count 2 2006.201.23:42:15.07#ibcon#about to read 4, iclass 28, count 2 2006.201.23:42:15.07#ibcon#read 4, iclass 28, count 2 2006.201.23:42:15.07#ibcon#about to read 5, iclass 28, count 2 2006.201.23:42:15.07#ibcon#read 5, iclass 28, count 2 2006.201.23:42:15.07#ibcon#about to read 6, iclass 28, count 2 2006.201.23:42:15.07#ibcon#read 6, iclass 28, count 2 2006.201.23:42:15.07#ibcon#end of sib2, iclass 28, count 2 2006.201.23:42:15.07#ibcon#*after write, iclass 28, count 2 2006.201.23:42:15.07#ibcon#*before return 0, iclass 28, count 2 2006.201.23:42:15.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:15.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.201.23:42:15.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.201.23:42:15.07#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:15.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:15.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:15.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:15.19#ibcon#enter wrdev, iclass 28, count 0 2006.201.23:42:15.19#ibcon#first serial, iclass 28, count 0 2006.201.23:42:15.19#ibcon#enter sib2, iclass 28, count 0 2006.201.23:42:15.19#ibcon#flushed, iclass 28, count 0 2006.201.23:42:15.19#ibcon#about to write, iclass 28, count 0 2006.201.23:42:15.19#ibcon#wrote, iclass 28, count 0 2006.201.23:42:15.19#ibcon#about to read 3, iclass 28, count 0 2006.201.23:42:15.21#ibcon#read 3, iclass 28, count 0 2006.201.23:42:15.21#ibcon#about to read 4, iclass 28, count 0 2006.201.23:42:15.21#ibcon#read 4, iclass 28, count 0 2006.201.23:42:15.21#ibcon#about to read 5, iclass 28, count 0 2006.201.23:42:15.21#ibcon#read 5, iclass 28, count 0 2006.201.23:42:15.21#ibcon#about to read 6, iclass 28, count 0 2006.201.23:42:15.21#ibcon#read 6, iclass 28, count 0 2006.201.23:42:15.21#ibcon#end of sib2, iclass 28, count 0 2006.201.23:42:15.21#ibcon#*mode == 0, iclass 28, count 0 2006.201.23:42:15.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.23:42:15.21#ibcon#[27=USB\r\n] 2006.201.23:42:15.21#ibcon#*before write, iclass 28, count 0 2006.201.23:42:15.21#ibcon#enter sib2, iclass 28, count 0 2006.201.23:42:15.21#ibcon#flushed, iclass 28, count 0 2006.201.23:42:15.21#ibcon#about to write, iclass 28, count 0 2006.201.23:42:15.21#ibcon#wrote, iclass 28, count 0 2006.201.23:42:15.21#ibcon#about to read 3, iclass 28, count 0 2006.201.23:42:15.24#ibcon#read 3, iclass 28, count 0 2006.201.23:42:15.24#ibcon#about to read 4, iclass 28, count 0 2006.201.23:42:15.24#ibcon#read 4, iclass 28, count 0 2006.201.23:42:15.24#ibcon#about to read 5, iclass 28, count 0 2006.201.23:42:15.24#ibcon#read 5, iclass 28, count 0 2006.201.23:42:15.24#ibcon#about to read 6, iclass 28, count 0 2006.201.23:42:15.24#ibcon#read 6, iclass 28, count 0 2006.201.23:42:15.24#ibcon#end of sib2, iclass 28, count 0 2006.201.23:42:15.24#ibcon#*after write, iclass 28, count 0 2006.201.23:42:15.24#ibcon#*before return 0, iclass 28, count 0 2006.201.23:42:15.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:15.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.201.23:42:15.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.23:42:15.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.23:42:15.24$vck44/vblo=7,734.99 2006.201.23:42:15.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.201.23:42:15.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.201.23:42:15.24#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:15.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:15.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:15.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:15.24#ibcon#enter wrdev, iclass 30, count 0 2006.201.23:42:15.24#ibcon#first serial, iclass 30, count 0 2006.201.23:42:15.24#ibcon#enter sib2, iclass 30, count 0 2006.201.23:42:15.24#ibcon#flushed, iclass 30, count 0 2006.201.23:42:15.24#ibcon#about to write, iclass 30, count 0 2006.201.23:42:15.24#ibcon#wrote, iclass 30, count 0 2006.201.23:42:15.24#ibcon#about to read 3, iclass 30, count 0 2006.201.23:42:15.26#ibcon#read 3, iclass 30, count 0 2006.201.23:42:15.26#ibcon#about to read 4, iclass 30, count 0 2006.201.23:42:15.26#ibcon#read 4, iclass 30, count 0 2006.201.23:42:15.26#ibcon#about to read 5, iclass 30, count 0 2006.201.23:42:15.26#ibcon#read 5, iclass 30, count 0 2006.201.23:42:15.26#ibcon#about to read 6, iclass 30, count 0 2006.201.23:42:15.26#ibcon#read 6, iclass 30, count 0 2006.201.23:42:15.26#ibcon#end of sib2, iclass 30, count 0 2006.201.23:42:15.26#ibcon#*mode == 0, iclass 30, count 0 2006.201.23:42:15.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.23:42:15.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.23:42:15.26#ibcon#*before write, iclass 30, count 0 2006.201.23:42:15.26#ibcon#enter sib2, iclass 30, count 0 2006.201.23:42:15.26#ibcon#flushed, iclass 30, count 0 2006.201.23:42:15.26#ibcon#about to write, iclass 30, count 0 2006.201.23:42:15.26#ibcon#wrote, iclass 30, count 0 2006.201.23:42:15.26#ibcon#about to read 3, iclass 30, count 0 2006.201.23:42:15.30#ibcon#read 3, iclass 30, count 0 2006.201.23:42:15.30#ibcon#about to read 4, iclass 30, count 0 2006.201.23:42:15.30#ibcon#read 4, iclass 30, count 0 2006.201.23:42:15.30#ibcon#about to read 5, iclass 30, count 0 2006.201.23:42:15.30#ibcon#read 5, iclass 30, count 0 2006.201.23:42:15.30#ibcon#about to read 6, iclass 30, count 0 2006.201.23:42:15.30#ibcon#read 6, iclass 30, count 0 2006.201.23:42:15.30#ibcon#end of sib2, iclass 30, count 0 2006.201.23:42:15.30#ibcon#*after write, iclass 30, count 0 2006.201.23:42:15.30#ibcon#*before return 0, iclass 30, count 0 2006.201.23:42:15.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:15.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.201.23:42:15.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.23:42:15.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.23:42:15.30$vck44/vb=7,4 2006.201.23:42:15.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.201.23:42:15.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.201.23:42:15.30#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:15.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:15.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:15.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:15.36#ibcon#enter wrdev, iclass 32, count 2 2006.201.23:42:15.36#ibcon#first serial, iclass 32, count 2 2006.201.23:42:15.36#ibcon#enter sib2, iclass 32, count 2 2006.201.23:42:15.36#ibcon#flushed, iclass 32, count 2 2006.201.23:42:15.36#ibcon#about to write, iclass 32, count 2 2006.201.23:42:15.36#ibcon#wrote, iclass 32, count 2 2006.201.23:42:15.36#ibcon#about to read 3, iclass 32, count 2 2006.201.23:42:15.38#ibcon#read 3, iclass 32, count 2 2006.201.23:42:15.38#ibcon#about to read 4, iclass 32, count 2 2006.201.23:42:15.38#ibcon#read 4, iclass 32, count 2 2006.201.23:42:15.38#ibcon#about to read 5, iclass 32, count 2 2006.201.23:42:15.38#ibcon#read 5, iclass 32, count 2 2006.201.23:42:15.38#ibcon#about to read 6, iclass 32, count 2 2006.201.23:42:15.38#ibcon#read 6, iclass 32, count 2 2006.201.23:42:15.38#ibcon#end of sib2, iclass 32, count 2 2006.201.23:42:15.38#ibcon#*mode == 0, iclass 32, count 2 2006.201.23:42:15.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.201.23:42:15.38#ibcon#[27=AT07-04\r\n] 2006.201.23:42:15.38#ibcon#*before write, iclass 32, count 2 2006.201.23:42:15.38#ibcon#enter sib2, iclass 32, count 2 2006.201.23:42:15.38#ibcon#flushed, iclass 32, count 2 2006.201.23:42:15.38#ibcon#about to write, iclass 32, count 2 2006.201.23:42:15.38#ibcon#wrote, iclass 32, count 2 2006.201.23:42:15.38#ibcon#about to read 3, iclass 32, count 2 2006.201.23:42:15.41#ibcon#read 3, iclass 32, count 2 2006.201.23:42:15.41#ibcon#about to read 4, iclass 32, count 2 2006.201.23:42:15.41#ibcon#read 4, iclass 32, count 2 2006.201.23:42:15.41#ibcon#about to read 5, iclass 32, count 2 2006.201.23:42:15.41#ibcon#read 5, iclass 32, count 2 2006.201.23:42:15.41#ibcon#about to read 6, iclass 32, count 2 2006.201.23:42:15.41#ibcon#read 6, iclass 32, count 2 2006.201.23:42:15.41#ibcon#end of sib2, iclass 32, count 2 2006.201.23:42:15.41#ibcon#*after write, iclass 32, count 2 2006.201.23:42:15.41#ibcon#*before return 0, iclass 32, count 2 2006.201.23:42:15.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:15.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.201.23:42:15.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.201.23:42:15.41#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:15.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:15.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:15.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:15.53#ibcon#enter wrdev, iclass 32, count 0 2006.201.23:42:15.53#ibcon#first serial, iclass 32, count 0 2006.201.23:42:15.53#ibcon#enter sib2, iclass 32, count 0 2006.201.23:42:15.53#ibcon#flushed, iclass 32, count 0 2006.201.23:42:15.53#ibcon#about to write, iclass 32, count 0 2006.201.23:42:15.53#ibcon#wrote, iclass 32, count 0 2006.201.23:42:15.53#ibcon#about to read 3, iclass 32, count 0 2006.201.23:42:15.55#ibcon#read 3, iclass 32, count 0 2006.201.23:42:15.55#ibcon#about to read 4, iclass 32, count 0 2006.201.23:42:15.55#ibcon#read 4, iclass 32, count 0 2006.201.23:42:15.55#ibcon#about to read 5, iclass 32, count 0 2006.201.23:42:15.55#ibcon#read 5, iclass 32, count 0 2006.201.23:42:15.55#ibcon#about to read 6, iclass 32, count 0 2006.201.23:42:15.55#ibcon#read 6, iclass 32, count 0 2006.201.23:42:15.55#ibcon#end of sib2, iclass 32, count 0 2006.201.23:42:15.55#ibcon#*mode == 0, iclass 32, count 0 2006.201.23:42:15.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.23:42:15.55#ibcon#[27=USB\r\n] 2006.201.23:42:15.55#ibcon#*before write, iclass 32, count 0 2006.201.23:42:15.55#ibcon#enter sib2, iclass 32, count 0 2006.201.23:42:15.55#ibcon#flushed, iclass 32, count 0 2006.201.23:42:15.55#ibcon#about to write, iclass 32, count 0 2006.201.23:42:15.55#ibcon#wrote, iclass 32, count 0 2006.201.23:42:15.55#ibcon#about to read 3, iclass 32, count 0 2006.201.23:42:15.58#ibcon#read 3, iclass 32, count 0 2006.201.23:42:15.58#ibcon#about to read 4, iclass 32, count 0 2006.201.23:42:15.58#ibcon#read 4, iclass 32, count 0 2006.201.23:42:15.58#ibcon#about to read 5, iclass 32, count 0 2006.201.23:42:15.58#ibcon#read 5, iclass 32, count 0 2006.201.23:42:15.58#ibcon#about to read 6, iclass 32, count 0 2006.201.23:42:15.58#ibcon#read 6, iclass 32, count 0 2006.201.23:42:15.58#ibcon#end of sib2, iclass 32, count 0 2006.201.23:42:15.58#ibcon#*after write, iclass 32, count 0 2006.201.23:42:15.58#ibcon#*before return 0, iclass 32, count 0 2006.201.23:42:15.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:15.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.201.23:42:15.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.23:42:15.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.23:42:15.58$vck44/vblo=8,744.99 2006.201.23:42:15.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.201.23:42:15.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.201.23:42:15.58#ibcon#ireg 17 cls_cnt 0 2006.201.23:42:15.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:15.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:15.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:15.58#ibcon#enter wrdev, iclass 34, count 0 2006.201.23:42:15.58#ibcon#first serial, iclass 34, count 0 2006.201.23:42:15.58#ibcon#enter sib2, iclass 34, count 0 2006.201.23:42:15.58#ibcon#flushed, iclass 34, count 0 2006.201.23:42:15.58#ibcon#about to write, iclass 34, count 0 2006.201.23:42:15.58#ibcon#wrote, iclass 34, count 0 2006.201.23:42:15.58#ibcon#about to read 3, iclass 34, count 0 2006.201.23:42:15.60#ibcon#read 3, iclass 34, count 0 2006.201.23:42:15.60#ibcon#about to read 4, iclass 34, count 0 2006.201.23:42:15.60#ibcon#read 4, iclass 34, count 0 2006.201.23:42:15.60#ibcon#about to read 5, iclass 34, count 0 2006.201.23:42:15.60#ibcon#read 5, iclass 34, count 0 2006.201.23:42:15.60#ibcon#about to read 6, iclass 34, count 0 2006.201.23:42:15.60#ibcon#read 6, iclass 34, count 0 2006.201.23:42:15.60#ibcon#end of sib2, iclass 34, count 0 2006.201.23:42:15.60#ibcon#*mode == 0, iclass 34, count 0 2006.201.23:42:15.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.23:42:15.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.23:42:15.60#ibcon#*before write, iclass 34, count 0 2006.201.23:42:15.60#ibcon#enter sib2, iclass 34, count 0 2006.201.23:42:15.60#ibcon#flushed, iclass 34, count 0 2006.201.23:42:15.60#ibcon#about to write, iclass 34, count 0 2006.201.23:42:15.60#ibcon#wrote, iclass 34, count 0 2006.201.23:42:15.60#ibcon#about to read 3, iclass 34, count 0 2006.201.23:42:15.64#ibcon#read 3, iclass 34, count 0 2006.201.23:42:15.64#ibcon#about to read 4, iclass 34, count 0 2006.201.23:42:15.64#ibcon#read 4, iclass 34, count 0 2006.201.23:42:15.64#ibcon#about to read 5, iclass 34, count 0 2006.201.23:42:15.64#ibcon#read 5, iclass 34, count 0 2006.201.23:42:15.64#ibcon#about to read 6, iclass 34, count 0 2006.201.23:42:15.64#ibcon#read 6, iclass 34, count 0 2006.201.23:42:15.64#ibcon#end of sib2, iclass 34, count 0 2006.201.23:42:15.64#ibcon#*after write, iclass 34, count 0 2006.201.23:42:15.64#ibcon#*before return 0, iclass 34, count 0 2006.201.23:42:15.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:15.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.201.23:42:15.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.23:42:15.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.23:42:15.64$vck44/vb=8,4 2006.201.23:42:15.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.201.23:42:15.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.201.23:42:15.64#ibcon#ireg 11 cls_cnt 2 2006.201.23:42:15.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:15.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:15.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:15.70#ibcon#enter wrdev, iclass 36, count 2 2006.201.23:42:15.70#ibcon#first serial, iclass 36, count 2 2006.201.23:42:15.70#ibcon#enter sib2, iclass 36, count 2 2006.201.23:42:15.70#ibcon#flushed, iclass 36, count 2 2006.201.23:42:15.70#ibcon#about to write, iclass 36, count 2 2006.201.23:42:15.70#ibcon#wrote, iclass 36, count 2 2006.201.23:42:15.70#ibcon#about to read 3, iclass 36, count 2 2006.201.23:42:15.72#ibcon#read 3, iclass 36, count 2 2006.201.23:42:15.72#ibcon#about to read 4, iclass 36, count 2 2006.201.23:42:15.72#ibcon#read 4, iclass 36, count 2 2006.201.23:42:15.72#ibcon#about to read 5, iclass 36, count 2 2006.201.23:42:15.72#ibcon#read 5, iclass 36, count 2 2006.201.23:42:15.72#ibcon#about to read 6, iclass 36, count 2 2006.201.23:42:15.72#ibcon#read 6, iclass 36, count 2 2006.201.23:42:15.72#ibcon#end of sib2, iclass 36, count 2 2006.201.23:42:15.72#ibcon#*mode == 0, iclass 36, count 2 2006.201.23:42:15.72#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.201.23:42:15.72#ibcon#[27=AT08-04\r\n] 2006.201.23:42:15.72#ibcon#*before write, iclass 36, count 2 2006.201.23:42:15.72#ibcon#enter sib2, iclass 36, count 2 2006.201.23:42:15.72#ibcon#flushed, iclass 36, count 2 2006.201.23:42:15.72#ibcon#about to write, iclass 36, count 2 2006.201.23:42:15.72#ibcon#wrote, iclass 36, count 2 2006.201.23:42:15.72#ibcon#about to read 3, iclass 36, count 2 2006.201.23:42:15.75#ibcon#read 3, iclass 36, count 2 2006.201.23:42:15.75#ibcon#about to read 4, iclass 36, count 2 2006.201.23:42:15.75#ibcon#read 4, iclass 36, count 2 2006.201.23:42:15.75#ibcon#about to read 5, iclass 36, count 2 2006.201.23:42:15.75#ibcon#read 5, iclass 36, count 2 2006.201.23:42:15.75#ibcon#about to read 6, iclass 36, count 2 2006.201.23:42:15.75#ibcon#read 6, iclass 36, count 2 2006.201.23:42:15.75#ibcon#end of sib2, iclass 36, count 2 2006.201.23:42:15.75#ibcon#*after write, iclass 36, count 2 2006.201.23:42:15.75#ibcon#*before return 0, iclass 36, count 2 2006.201.23:42:15.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:15.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.201.23:42:15.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.201.23:42:15.75#ibcon#ireg 7 cls_cnt 0 2006.201.23:42:15.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:15.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:15.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:15.87#ibcon#enter wrdev, iclass 36, count 0 2006.201.23:42:15.87#ibcon#first serial, iclass 36, count 0 2006.201.23:42:15.87#ibcon#enter sib2, iclass 36, count 0 2006.201.23:42:15.87#ibcon#flushed, iclass 36, count 0 2006.201.23:42:15.87#ibcon#about to write, iclass 36, count 0 2006.201.23:42:15.87#ibcon#wrote, iclass 36, count 0 2006.201.23:42:15.87#ibcon#about to read 3, iclass 36, count 0 2006.201.23:42:15.89#ibcon#read 3, iclass 36, count 0 2006.201.23:42:15.89#ibcon#about to read 4, iclass 36, count 0 2006.201.23:42:15.89#ibcon#read 4, iclass 36, count 0 2006.201.23:42:15.89#ibcon#about to read 5, iclass 36, count 0 2006.201.23:42:15.89#ibcon#read 5, iclass 36, count 0 2006.201.23:42:15.89#ibcon#about to read 6, iclass 36, count 0 2006.201.23:42:15.89#ibcon#read 6, iclass 36, count 0 2006.201.23:42:15.89#ibcon#end of sib2, iclass 36, count 0 2006.201.23:42:15.89#ibcon#*mode == 0, iclass 36, count 0 2006.201.23:42:15.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.23:42:15.89#ibcon#[27=USB\r\n] 2006.201.23:42:15.89#ibcon#*before write, iclass 36, count 0 2006.201.23:42:15.89#ibcon#enter sib2, iclass 36, count 0 2006.201.23:42:15.89#ibcon#flushed, iclass 36, count 0 2006.201.23:42:15.89#ibcon#about to write, iclass 36, count 0 2006.201.23:42:15.89#ibcon#wrote, iclass 36, count 0 2006.201.23:42:15.89#ibcon#about to read 3, iclass 36, count 0 2006.201.23:42:15.92#ibcon#read 3, iclass 36, count 0 2006.201.23:42:15.92#ibcon#about to read 4, iclass 36, count 0 2006.201.23:42:15.92#ibcon#read 4, iclass 36, count 0 2006.201.23:42:15.92#ibcon#about to read 5, iclass 36, count 0 2006.201.23:42:15.92#ibcon#read 5, iclass 36, count 0 2006.201.23:42:15.92#ibcon#about to read 6, iclass 36, count 0 2006.201.23:42:15.92#ibcon#read 6, iclass 36, count 0 2006.201.23:42:15.92#ibcon#end of sib2, iclass 36, count 0 2006.201.23:42:15.92#ibcon#*after write, iclass 36, count 0 2006.201.23:42:15.92#ibcon#*before return 0, iclass 36, count 0 2006.201.23:42:15.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:15.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.201.23:42:15.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.23:42:15.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.23:42:15.92$vck44/vabw=wide 2006.201.23:42:15.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.201.23:42:15.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.201.23:42:15.92#ibcon#ireg 8 cls_cnt 0 2006.201.23:42:15.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:15.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:15.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:15.92#ibcon#enter wrdev, iclass 38, count 0 2006.201.23:42:15.92#ibcon#first serial, iclass 38, count 0 2006.201.23:42:15.92#ibcon#enter sib2, iclass 38, count 0 2006.201.23:42:15.92#ibcon#flushed, iclass 38, count 0 2006.201.23:42:15.92#ibcon#about to write, iclass 38, count 0 2006.201.23:42:15.92#ibcon#wrote, iclass 38, count 0 2006.201.23:42:15.92#ibcon#about to read 3, iclass 38, count 0 2006.201.23:42:15.94#ibcon#read 3, iclass 38, count 0 2006.201.23:42:15.94#ibcon#about to read 4, iclass 38, count 0 2006.201.23:42:15.94#ibcon#read 4, iclass 38, count 0 2006.201.23:42:15.94#ibcon#about to read 5, iclass 38, count 0 2006.201.23:42:15.94#ibcon#read 5, iclass 38, count 0 2006.201.23:42:15.94#ibcon#about to read 6, iclass 38, count 0 2006.201.23:42:15.94#ibcon#read 6, iclass 38, count 0 2006.201.23:42:15.94#ibcon#end of sib2, iclass 38, count 0 2006.201.23:42:15.94#ibcon#*mode == 0, iclass 38, count 0 2006.201.23:42:15.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.23:42:15.94#ibcon#[25=BW32\r\n] 2006.201.23:42:15.94#ibcon#*before write, iclass 38, count 0 2006.201.23:42:15.94#ibcon#enter sib2, iclass 38, count 0 2006.201.23:42:15.94#ibcon#flushed, iclass 38, count 0 2006.201.23:42:15.94#ibcon#about to write, iclass 38, count 0 2006.201.23:42:15.94#ibcon#wrote, iclass 38, count 0 2006.201.23:42:15.94#ibcon#about to read 3, iclass 38, count 0 2006.201.23:42:15.97#ibcon#read 3, iclass 38, count 0 2006.201.23:42:15.97#ibcon#about to read 4, iclass 38, count 0 2006.201.23:42:15.97#ibcon#read 4, iclass 38, count 0 2006.201.23:42:15.97#ibcon#about to read 5, iclass 38, count 0 2006.201.23:42:15.97#ibcon#read 5, iclass 38, count 0 2006.201.23:42:15.97#ibcon#about to read 6, iclass 38, count 0 2006.201.23:42:15.97#ibcon#read 6, iclass 38, count 0 2006.201.23:42:15.97#ibcon#end of sib2, iclass 38, count 0 2006.201.23:42:15.97#ibcon#*after write, iclass 38, count 0 2006.201.23:42:15.97#ibcon#*before return 0, iclass 38, count 0 2006.201.23:42:15.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:15.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.201.23:42:15.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.23:42:15.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.23:42:15.97$vck44/vbbw=wide 2006.201.23:42:15.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.23:42:15.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.23:42:15.97#ibcon#ireg 8 cls_cnt 0 2006.201.23:42:15.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:42:16.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:42:16.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:42:16.04#ibcon#enter wrdev, iclass 40, count 0 2006.201.23:42:16.04#ibcon#first serial, iclass 40, count 0 2006.201.23:42:16.04#ibcon#enter sib2, iclass 40, count 0 2006.201.23:42:16.04#ibcon#flushed, iclass 40, count 0 2006.201.23:42:16.04#ibcon#about to write, iclass 40, count 0 2006.201.23:42:16.04#ibcon#wrote, iclass 40, count 0 2006.201.23:42:16.04#ibcon#about to read 3, iclass 40, count 0 2006.201.23:42:16.06#ibcon#read 3, iclass 40, count 0 2006.201.23:42:16.06#ibcon#about to read 4, iclass 40, count 0 2006.201.23:42:16.06#ibcon#read 4, iclass 40, count 0 2006.201.23:42:16.06#ibcon#about to read 5, iclass 40, count 0 2006.201.23:42:16.06#ibcon#read 5, iclass 40, count 0 2006.201.23:42:16.06#ibcon#about to read 6, iclass 40, count 0 2006.201.23:42:16.06#ibcon#read 6, iclass 40, count 0 2006.201.23:42:16.06#ibcon#end of sib2, iclass 40, count 0 2006.201.23:42:16.06#ibcon#*mode == 0, iclass 40, count 0 2006.201.23:42:16.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.23:42:16.06#ibcon#[27=BW32\r\n] 2006.201.23:42:16.06#ibcon#*before write, iclass 40, count 0 2006.201.23:42:16.06#ibcon#enter sib2, iclass 40, count 0 2006.201.23:42:16.06#ibcon#flushed, iclass 40, count 0 2006.201.23:42:16.06#ibcon#about to write, iclass 40, count 0 2006.201.23:42:16.06#ibcon#wrote, iclass 40, count 0 2006.201.23:42:16.06#ibcon#about to read 3, iclass 40, count 0 2006.201.23:42:16.09#ibcon#read 3, iclass 40, count 0 2006.201.23:42:16.09#ibcon#about to read 4, iclass 40, count 0 2006.201.23:42:16.09#ibcon#read 4, iclass 40, count 0 2006.201.23:42:16.09#ibcon#about to read 5, iclass 40, count 0 2006.201.23:42:16.09#ibcon#read 5, iclass 40, count 0 2006.201.23:42:16.09#ibcon#about to read 6, iclass 40, count 0 2006.201.23:42:16.09#ibcon#read 6, iclass 40, count 0 2006.201.23:42:16.09#ibcon#end of sib2, iclass 40, count 0 2006.201.23:42:16.09#ibcon#*after write, iclass 40, count 0 2006.201.23:42:16.09#ibcon#*before return 0, iclass 40, count 0 2006.201.23:42:16.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:42:16.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:42:16.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.23:42:16.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.23:42:16.09$setupk4/ifdk4 2006.201.23:42:16.09$ifdk4/lo= 2006.201.23:42:16.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.23:42:16.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.23:42:16.09$ifdk4/patch= 2006.201.23:42:16.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.23:42:16.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.23:42:16.09$setupk4/!*+20s 2006.201.23:42:24.49#abcon#<5=/03 0.8 2.1 20.331001001.7\r\n> 2006.201.23:42:24.51#abcon#{5=INTERFACE CLEAR} 2006.201.23:42:24.57#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:42:29.14#trakl#Source acquired 2006.201.23:42:30.60$setupk4/"tpicd 2006.201.23:42:30.60$setupk4/echo=off 2006.201.23:42:30.60$setupk4/xlog=off 2006.201.23:42:30.60:!2006.201.23:44:28 2006.201.23:42:31.14#flagr#flagr/antenna,acquired 2006.201.23:44:28.00:preob 2006.201.23:44:29.14/onsource/TRACKING 2006.201.23:44:29.14:!2006.201.23:44:38 2006.201.23:44:38.00:"tape 2006.201.23:44:38.00:"st=record 2006.201.23:44:38.00:data_valid=on 2006.201.23:44:38.00:midob 2006.201.23:44:38.14/onsource/TRACKING 2006.201.23:44:38.14/wx/20.32,1001.6,100 2006.201.23:44:38.26/cable/+6.4851E-03 2006.201.23:44:39.35/va/01,08,usb,yes,45,48 2006.201.23:44:39.35/va/02,07,usb,yes,48,50 2006.201.23:44:39.35/va/03,08,usb,yes,44,46 2006.201.23:44:39.35/va/04,07,usb,yes,50,53 2006.201.23:44:39.35/va/05,04,usb,yes,45,46 2006.201.23:44:39.35/va/06,05,usb,yes,45,45 2006.201.23:44:39.35/va/07,05,usb,yes,44,45 2006.201.23:44:39.35/va/08,04,usb,yes,44,52 2006.201.23:44:39.58/valo/01,524.99,yes,locked 2006.201.23:44:39.58/valo/02,534.99,yes,locked 2006.201.23:44:39.58/valo/03,564.99,yes,locked 2006.201.23:44:39.58/valo/04,624.99,yes,locked 2006.201.23:44:39.58/valo/05,734.99,yes,locked 2006.201.23:44:39.58/valo/06,814.99,yes,locked 2006.201.23:44:39.58/valo/07,864.99,yes,locked 2006.201.23:44:39.58/valo/08,884.99,yes,locked 2006.201.23:44:40.67/vb/01,04,usb,yes,30,28 2006.201.23:44:40.67/vb/02,05,usb,yes,29,28 2006.201.23:44:40.67/vb/03,04,usb,yes,30,33 2006.201.23:44:40.67/vb/04,05,usb,yes,30,29 2006.201.23:44:40.67/vb/05,04,usb,yes,26,29 2006.201.23:44:40.67/vb/06,04,usb,yes,31,27 2006.201.23:44:40.67/vb/07,04,usb,yes,31,31 2006.201.23:44:40.67/vb/08,04,usb,yes,28,32 2006.201.23:44:40.90/vblo/01,629.99,yes,locked 2006.201.23:44:40.90/vblo/02,634.99,yes,locked 2006.201.23:44:40.90/vblo/03,649.99,yes,locked 2006.201.23:44:40.90/vblo/04,679.99,yes,locked 2006.201.23:44:40.90/vblo/05,709.99,yes,locked 2006.201.23:44:40.90/vblo/06,719.99,yes,locked 2006.201.23:44:40.90/vblo/07,734.99,yes,locked 2006.201.23:44:40.90/vblo/08,744.99,yes,locked 2006.201.23:44:41.05/vabw/8 2006.201.23:44:41.20/vbbw/8 2006.201.23:44:41.29/xfe/off,on,15.2 2006.201.23:44:41.66/ifatt/23,28,28,28 2006.201.23:44:42.07/fmout-gps/S +4.58E-07 2006.201.23:44:42.10:!2006.201.23:45:38 2006.201.23:45:38.00:data_valid=off 2006.201.23:45:38.00:"et 2006.201.23:45:38.00:!+3s 2006.201.23:45:41.01:"tape 2006.201.23:45:41.01:postob 2006.201.23:45:41.21/cable/+6.4834E-03 2006.201.23:45:41.21/wx/20.33,1001.6,100 2006.201.23:45:42.06/fmout-gps/S +4.56E-07 2006.201.23:45:42.06:scan_name=201-2348,jd0607,50 2006.201.23:45:42.06:source=0552+398,055530.81,394849.2,2000.0,cw 2006.201.23:45:42.14#flagr#flagr/antenna,new-source 2006.201.23:45:43.14:checkk5 2006.201.23:45:43.49/chk_autoobs//k5ts1/ autoobs is running! 2006.201.23:45:43.84/chk_autoobs//k5ts2/ autoobs is running! 2006.201.23:45:44.18/chk_autoobs//k5ts3/ autoobs is running! 2006.201.23:45:44.54/chk_autoobs//k5ts4/ autoobs is running! 2006.201.23:45:44.87/chk_obsdata//k5ts1/T2012344??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.23:45:45.22/chk_obsdata//k5ts2/T2012344??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.23:45:45.56/chk_obsdata//k5ts3/T2012344??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.23:45:45.91/chk_obsdata//k5ts4/T2012344??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.201.23:45:46.57/k5log//k5ts1_log_newline 2006.201.23:45:47.23/k5log//k5ts2_log_newline 2006.201.23:45:47.89/k5log//k5ts3_log_newline 2006.201.23:45:48.56/k5log//k5ts4_log_newline 2006.201.23:45:48.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.23:45:48.58:setupk4=1 2006.201.23:45:48.58$setupk4/echo=on 2006.201.23:45:48.58$setupk4/pcalon 2006.201.23:45:48.58$pcalon/"no phase cal control is implemented here 2006.201.23:45:48.58$setupk4/"tpicd=stop 2006.201.23:45:48.58$setupk4/"rec=synch_on 2006.201.23:45:48.58$setupk4/"rec_mode=128 2006.201.23:45:48.58$setupk4/!* 2006.201.23:45:48.58$setupk4/recpk4 2006.201.23:45:48.58$recpk4/recpatch= 2006.201.23:45:48.59$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.23:45:48.59$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.23:45:48.59$setupk4/vck44 2006.201.23:45:48.59$vck44/valo=1,524.99 2006.201.23:45:48.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.23:45:48.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.23:45:48.59#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:48.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:48.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:48.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:48.59#ibcon#enter wrdev, iclass 21, count 0 2006.201.23:45:48.59#ibcon#first serial, iclass 21, count 0 2006.201.23:45:48.59#ibcon#enter sib2, iclass 21, count 0 2006.201.23:45:48.59#ibcon#flushed, iclass 21, count 0 2006.201.23:45:48.59#ibcon#about to write, iclass 21, count 0 2006.201.23:45:48.59#ibcon#wrote, iclass 21, count 0 2006.201.23:45:48.59#ibcon#about to read 3, iclass 21, count 0 2006.201.23:45:48.61#ibcon#read 3, iclass 21, count 0 2006.201.23:45:48.61#ibcon#about to read 4, iclass 21, count 0 2006.201.23:45:48.61#ibcon#read 4, iclass 21, count 0 2006.201.23:45:48.61#ibcon#about to read 5, iclass 21, count 0 2006.201.23:45:48.61#ibcon#read 5, iclass 21, count 0 2006.201.23:45:48.61#ibcon#about to read 6, iclass 21, count 0 2006.201.23:45:48.61#ibcon#read 6, iclass 21, count 0 2006.201.23:45:48.61#ibcon#end of sib2, iclass 21, count 0 2006.201.23:45:48.61#ibcon#*mode == 0, iclass 21, count 0 2006.201.23:45:48.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.23:45:48.61#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.23:45:48.61#ibcon#*before write, iclass 21, count 0 2006.201.23:45:48.61#ibcon#enter sib2, iclass 21, count 0 2006.201.23:45:48.61#ibcon#flushed, iclass 21, count 0 2006.201.23:45:48.61#ibcon#about to write, iclass 21, count 0 2006.201.23:45:48.61#ibcon#wrote, iclass 21, count 0 2006.201.23:45:48.61#ibcon#about to read 3, iclass 21, count 0 2006.201.23:45:48.66#ibcon#read 3, iclass 21, count 0 2006.201.23:45:48.66#ibcon#about to read 4, iclass 21, count 0 2006.201.23:45:48.66#ibcon#read 4, iclass 21, count 0 2006.201.23:45:48.66#ibcon#about to read 5, iclass 21, count 0 2006.201.23:45:48.66#ibcon#read 5, iclass 21, count 0 2006.201.23:45:48.66#ibcon#about to read 6, iclass 21, count 0 2006.201.23:45:48.66#ibcon#read 6, iclass 21, count 0 2006.201.23:45:48.66#ibcon#end of sib2, iclass 21, count 0 2006.201.23:45:48.66#ibcon#*after write, iclass 21, count 0 2006.201.23:45:48.66#ibcon#*before return 0, iclass 21, count 0 2006.201.23:45:48.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:48.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:48.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.23:45:48.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.23:45:48.66$vck44/va=1,8 2006.201.23:45:48.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.23:45:48.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.23:45:48.66#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:48.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:48.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:48.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:48.66#ibcon#enter wrdev, iclass 23, count 2 2006.201.23:45:48.66#ibcon#first serial, iclass 23, count 2 2006.201.23:45:48.66#ibcon#enter sib2, iclass 23, count 2 2006.201.23:45:48.66#ibcon#flushed, iclass 23, count 2 2006.201.23:45:48.66#ibcon#about to write, iclass 23, count 2 2006.201.23:45:48.66#ibcon#wrote, iclass 23, count 2 2006.201.23:45:48.66#ibcon#about to read 3, iclass 23, count 2 2006.201.23:45:48.68#ibcon#read 3, iclass 23, count 2 2006.201.23:45:48.68#ibcon#about to read 4, iclass 23, count 2 2006.201.23:45:48.68#ibcon#read 4, iclass 23, count 2 2006.201.23:45:48.68#ibcon#about to read 5, iclass 23, count 2 2006.201.23:45:48.68#ibcon#read 5, iclass 23, count 2 2006.201.23:45:48.68#ibcon#about to read 6, iclass 23, count 2 2006.201.23:45:48.68#ibcon#read 6, iclass 23, count 2 2006.201.23:45:48.68#ibcon#end of sib2, iclass 23, count 2 2006.201.23:45:48.68#ibcon#*mode == 0, iclass 23, count 2 2006.201.23:45:48.68#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.23:45:48.68#ibcon#[25=AT01-08\r\n] 2006.201.23:45:48.68#ibcon#*before write, iclass 23, count 2 2006.201.23:45:48.68#ibcon#enter sib2, iclass 23, count 2 2006.201.23:45:48.68#ibcon#flushed, iclass 23, count 2 2006.201.23:45:48.68#ibcon#about to write, iclass 23, count 2 2006.201.23:45:48.68#ibcon#wrote, iclass 23, count 2 2006.201.23:45:48.68#ibcon#about to read 3, iclass 23, count 2 2006.201.23:45:48.71#ibcon#read 3, iclass 23, count 2 2006.201.23:45:48.71#ibcon#about to read 4, iclass 23, count 2 2006.201.23:45:48.71#ibcon#read 4, iclass 23, count 2 2006.201.23:45:48.71#ibcon#about to read 5, iclass 23, count 2 2006.201.23:45:48.71#ibcon#read 5, iclass 23, count 2 2006.201.23:45:48.71#ibcon#about to read 6, iclass 23, count 2 2006.201.23:45:48.71#ibcon#read 6, iclass 23, count 2 2006.201.23:45:48.71#ibcon#end of sib2, iclass 23, count 2 2006.201.23:45:48.71#ibcon#*after write, iclass 23, count 2 2006.201.23:45:48.71#ibcon#*before return 0, iclass 23, count 2 2006.201.23:45:48.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:48.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:48.71#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.23:45:48.71#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:48.71#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:48.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:48.83#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:48.83#ibcon#enter wrdev, iclass 23, count 0 2006.201.23:45:48.83#ibcon#first serial, iclass 23, count 0 2006.201.23:45:48.83#ibcon#enter sib2, iclass 23, count 0 2006.201.23:45:48.83#ibcon#flushed, iclass 23, count 0 2006.201.23:45:48.83#ibcon#about to write, iclass 23, count 0 2006.201.23:45:48.83#ibcon#wrote, iclass 23, count 0 2006.201.23:45:48.83#ibcon#about to read 3, iclass 23, count 0 2006.201.23:45:48.85#ibcon#read 3, iclass 23, count 0 2006.201.23:45:48.85#ibcon#about to read 4, iclass 23, count 0 2006.201.23:45:48.85#ibcon#read 4, iclass 23, count 0 2006.201.23:45:48.85#ibcon#about to read 5, iclass 23, count 0 2006.201.23:45:48.85#ibcon#read 5, iclass 23, count 0 2006.201.23:45:48.85#ibcon#about to read 6, iclass 23, count 0 2006.201.23:45:48.85#ibcon#read 6, iclass 23, count 0 2006.201.23:45:48.85#ibcon#end of sib2, iclass 23, count 0 2006.201.23:45:48.85#ibcon#*mode == 0, iclass 23, count 0 2006.201.23:45:48.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.23:45:48.85#ibcon#[25=USB\r\n] 2006.201.23:45:48.85#ibcon#*before write, iclass 23, count 0 2006.201.23:45:48.85#ibcon#enter sib2, iclass 23, count 0 2006.201.23:45:48.85#ibcon#flushed, iclass 23, count 0 2006.201.23:45:48.85#ibcon#about to write, iclass 23, count 0 2006.201.23:45:48.85#ibcon#wrote, iclass 23, count 0 2006.201.23:45:48.85#ibcon#about to read 3, iclass 23, count 0 2006.201.23:45:48.88#ibcon#read 3, iclass 23, count 0 2006.201.23:45:48.88#ibcon#about to read 4, iclass 23, count 0 2006.201.23:45:48.88#ibcon#read 4, iclass 23, count 0 2006.201.23:45:48.88#ibcon#about to read 5, iclass 23, count 0 2006.201.23:45:48.88#ibcon#read 5, iclass 23, count 0 2006.201.23:45:48.88#ibcon#about to read 6, iclass 23, count 0 2006.201.23:45:48.88#ibcon#read 6, iclass 23, count 0 2006.201.23:45:48.88#ibcon#end of sib2, iclass 23, count 0 2006.201.23:45:48.88#ibcon#*after write, iclass 23, count 0 2006.201.23:45:48.88#ibcon#*before return 0, iclass 23, count 0 2006.201.23:45:48.88#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:48.88#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:48.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.23:45:48.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.23:45:48.88$vck44/valo=2,534.99 2006.201.23:45:48.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.23:45:48.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.23:45:48.88#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:48.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:48.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:48.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:48.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.23:45:48.88#ibcon#first serial, iclass 25, count 0 2006.201.23:45:48.88#ibcon#enter sib2, iclass 25, count 0 2006.201.23:45:48.88#ibcon#flushed, iclass 25, count 0 2006.201.23:45:48.88#ibcon#about to write, iclass 25, count 0 2006.201.23:45:48.88#ibcon#wrote, iclass 25, count 0 2006.201.23:45:48.88#ibcon#about to read 3, iclass 25, count 0 2006.201.23:45:48.90#ibcon#read 3, iclass 25, count 0 2006.201.23:45:48.90#ibcon#about to read 4, iclass 25, count 0 2006.201.23:45:48.90#ibcon#read 4, iclass 25, count 0 2006.201.23:45:48.90#ibcon#about to read 5, iclass 25, count 0 2006.201.23:45:48.90#ibcon#read 5, iclass 25, count 0 2006.201.23:45:48.90#ibcon#about to read 6, iclass 25, count 0 2006.201.23:45:48.90#ibcon#read 6, iclass 25, count 0 2006.201.23:45:48.90#ibcon#end of sib2, iclass 25, count 0 2006.201.23:45:48.90#ibcon#*mode == 0, iclass 25, count 0 2006.201.23:45:48.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.23:45:48.90#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.23:45:48.90#ibcon#*before write, iclass 25, count 0 2006.201.23:45:48.90#ibcon#enter sib2, iclass 25, count 0 2006.201.23:45:48.90#ibcon#flushed, iclass 25, count 0 2006.201.23:45:48.90#ibcon#about to write, iclass 25, count 0 2006.201.23:45:48.90#ibcon#wrote, iclass 25, count 0 2006.201.23:45:48.90#ibcon#about to read 3, iclass 25, count 0 2006.201.23:45:48.94#ibcon#read 3, iclass 25, count 0 2006.201.23:45:48.94#ibcon#about to read 4, iclass 25, count 0 2006.201.23:45:48.94#ibcon#read 4, iclass 25, count 0 2006.201.23:45:48.94#ibcon#about to read 5, iclass 25, count 0 2006.201.23:45:48.94#ibcon#read 5, iclass 25, count 0 2006.201.23:45:48.94#ibcon#about to read 6, iclass 25, count 0 2006.201.23:45:48.94#ibcon#read 6, iclass 25, count 0 2006.201.23:45:48.94#ibcon#end of sib2, iclass 25, count 0 2006.201.23:45:48.94#ibcon#*after write, iclass 25, count 0 2006.201.23:45:48.94#ibcon#*before return 0, iclass 25, count 0 2006.201.23:45:48.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:48.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:48.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.23:45:48.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.23:45:48.94$vck44/va=2,7 2006.201.23:45:48.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.23:45:48.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.23:45:48.94#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:48.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:49.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:49.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:49.00#ibcon#enter wrdev, iclass 27, count 2 2006.201.23:45:49.00#ibcon#first serial, iclass 27, count 2 2006.201.23:45:49.00#ibcon#enter sib2, iclass 27, count 2 2006.201.23:45:49.00#ibcon#flushed, iclass 27, count 2 2006.201.23:45:49.00#ibcon#about to write, iclass 27, count 2 2006.201.23:45:49.00#ibcon#wrote, iclass 27, count 2 2006.201.23:45:49.00#ibcon#about to read 3, iclass 27, count 2 2006.201.23:45:49.02#ibcon#read 3, iclass 27, count 2 2006.201.23:45:49.02#ibcon#about to read 4, iclass 27, count 2 2006.201.23:45:49.02#ibcon#read 4, iclass 27, count 2 2006.201.23:45:49.02#ibcon#about to read 5, iclass 27, count 2 2006.201.23:45:49.02#ibcon#read 5, iclass 27, count 2 2006.201.23:45:49.02#ibcon#about to read 6, iclass 27, count 2 2006.201.23:45:49.02#ibcon#read 6, iclass 27, count 2 2006.201.23:45:49.02#ibcon#end of sib2, iclass 27, count 2 2006.201.23:45:49.02#ibcon#*mode == 0, iclass 27, count 2 2006.201.23:45:49.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.23:45:49.02#ibcon#[25=AT02-07\r\n] 2006.201.23:45:49.02#ibcon#*before write, iclass 27, count 2 2006.201.23:45:49.02#ibcon#enter sib2, iclass 27, count 2 2006.201.23:45:49.02#ibcon#flushed, iclass 27, count 2 2006.201.23:45:49.02#ibcon#about to write, iclass 27, count 2 2006.201.23:45:49.02#ibcon#wrote, iclass 27, count 2 2006.201.23:45:49.02#ibcon#about to read 3, iclass 27, count 2 2006.201.23:45:49.05#ibcon#read 3, iclass 27, count 2 2006.201.23:45:49.05#ibcon#about to read 4, iclass 27, count 2 2006.201.23:45:49.05#ibcon#read 4, iclass 27, count 2 2006.201.23:45:49.05#ibcon#about to read 5, iclass 27, count 2 2006.201.23:45:49.05#ibcon#read 5, iclass 27, count 2 2006.201.23:45:49.05#ibcon#about to read 6, iclass 27, count 2 2006.201.23:45:49.05#ibcon#read 6, iclass 27, count 2 2006.201.23:45:49.05#ibcon#end of sib2, iclass 27, count 2 2006.201.23:45:49.05#ibcon#*after write, iclass 27, count 2 2006.201.23:45:49.05#ibcon#*before return 0, iclass 27, count 2 2006.201.23:45:49.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:49.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:49.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.23:45:49.05#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:49.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:49.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:49.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:49.17#ibcon#enter wrdev, iclass 27, count 0 2006.201.23:45:49.17#ibcon#first serial, iclass 27, count 0 2006.201.23:45:49.17#ibcon#enter sib2, iclass 27, count 0 2006.201.23:45:49.17#ibcon#flushed, iclass 27, count 0 2006.201.23:45:49.17#ibcon#about to write, iclass 27, count 0 2006.201.23:45:49.17#ibcon#wrote, iclass 27, count 0 2006.201.23:45:49.17#ibcon#about to read 3, iclass 27, count 0 2006.201.23:45:49.19#ibcon#read 3, iclass 27, count 0 2006.201.23:45:49.19#ibcon#about to read 4, iclass 27, count 0 2006.201.23:45:49.19#ibcon#read 4, iclass 27, count 0 2006.201.23:45:49.19#ibcon#about to read 5, iclass 27, count 0 2006.201.23:45:49.19#ibcon#read 5, iclass 27, count 0 2006.201.23:45:49.19#ibcon#about to read 6, iclass 27, count 0 2006.201.23:45:49.19#ibcon#read 6, iclass 27, count 0 2006.201.23:45:49.19#ibcon#end of sib2, iclass 27, count 0 2006.201.23:45:49.19#ibcon#*mode == 0, iclass 27, count 0 2006.201.23:45:49.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.23:45:49.19#ibcon#[25=USB\r\n] 2006.201.23:45:49.19#ibcon#*before write, iclass 27, count 0 2006.201.23:45:49.19#ibcon#enter sib2, iclass 27, count 0 2006.201.23:45:49.19#ibcon#flushed, iclass 27, count 0 2006.201.23:45:49.19#ibcon#about to write, iclass 27, count 0 2006.201.23:45:49.19#ibcon#wrote, iclass 27, count 0 2006.201.23:45:49.19#ibcon#about to read 3, iclass 27, count 0 2006.201.23:45:49.22#ibcon#read 3, iclass 27, count 0 2006.201.23:45:49.22#ibcon#about to read 4, iclass 27, count 0 2006.201.23:45:49.22#ibcon#read 4, iclass 27, count 0 2006.201.23:45:49.22#ibcon#about to read 5, iclass 27, count 0 2006.201.23:45:49.22#ibcon#read 5, iclass 27, count 0 2006.201.23:45:49.22#ibcon#about to read 6, iclass 27, count 0 2006.201.23:45:49.22#ibcon#read 6, iclass 27, count 0 2006.201.23:45:49.22#ibcon#end of sib2, iclass 27, count 0 2006.201.23:45:49.22#ibcon#*after write, iclass 27, count 0 2006.201.23:45:49.22#ibcon#*before return 0, iclass 27, count 0 2006.201.23:45:49.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:49.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:49.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.23:45:49.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.23:45:49.22$vck44/valo=3,564.99 2006.201.23:45:49.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.23:45:49.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.23:45:49.22#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:49.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:49.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:49.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:49.22#ibcon#enter wrdev, iclass 29, count 0 2006.201.23:45:49.22#ibcon#first serial, iclass 29, count 0 2006.201.23:45:49.22#ibcon#enter sib2, iclass 29, count 0 2006.201.23:45:49.22#ibcon#flushed, iclass 29, count 0 2006.201.23:45:49.22#ibcon#about to write, iclass 29, count 0 2006.201.23:45:49.22#ibcon#wrote, iclass 29, count 0 2006.201.23:45:49.22#ibcon#about to read 3, iclass 29, count 0 2006.201.23:45:49.24#ibcon#read 3, iclass 29, count 0 2006.201.23:45:49.24#ibcon#about to read 4, iclass 29, count 0 2006.201.23:45:49.24#ibcon#read 4, iclass 29, count 0 2006.201.23:45:49.24#ibcon#about to read 5, iclass 29, count 0 2006.201.23:45:49.24#ibcon#read 5, iclass 29, count 0 2006.201.23:45:49.24#ibcon#about to read 6, iclass 29, count 0 2006.201.23:45:49.24#ibcon#read 6, iclass 29, count 0 2006.201.23:45:49.24#ibcon#end of sib2, iclass 29, count 0 2006.201.23:45:49.24#ibcon#*mode == 0, iclass 29, count 0 2006.201.23:45:49.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.23:45:49.24#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.23:45:49.24#ibcon#*before write, iclass 29, count 0 2006.201.23:45:49.24#ibcon#enter sib2, iclass 29, count 0 2006.201.23:45:49.24#ibcon#flushed, iclass 29, count 0 2006.201.23:45:49.24#ibcon#about to write, iclass 29, count 0 2006.201.23:45:49.24#ibcon#wrote, iclass 29, count 0 2006.201.23:45:49.24#ibcon#about to read 3, iclass 29, count 0 2006.201.23:45:49.28#ibcon#read 3, iclass 29, count 0 2006.201.23:45:49.28#ibcon#about to read 4, iclass 29, count 0 2006.201.23:45:49.28#ibcon#read 4, iclass 29, count 0 2006.201.23:45:49.28#ibcon#about to read 5, iclass 29, count 0 2006.201.23:45:49.28#ibcon#read 5, iclass 29, count 0 2006.201.23:45:49.28#ibcon#about to read 6, iclass 29, count 0 2006.201.23:45:49.28#ibcon#read 6, iclass 29, count 0 2006.201.23:45:49.28#ibcon#end of sib2, iclass 29, count 0 2006.201.23:45:49.28#ibcon#*after write, iclass 29, count 0 2006.201.23:45:49.28#ibcon#*before return 0, iclass 29, count 0 2006.201.23:45:49.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:49.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:49.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.23:45:49.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.23:45:49.28$vck44/va=3,8 2006.201.23:45:49.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.23:45:49.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.23:45:49.28#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:49.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:49.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:49.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:49.34#ibcon#enter wrdev, iclass 31, count 2 2006.201.23:45:49.34#ibcon#first serial, iclass 31, count 2 2006.201.23:45:49.34#ibcon#enter sib2, iclass 31, count 2 2006.201.23:45:49.34#ibcon#flushed, iclass 31, count 2 2006.201.23:45:49.34#ibcon#about to write, iclass 31, count 2 2006.201.23:45:49.34#ibcon#wrote, iclass 31, count 2 2006.201.23:45:49.34#ibcon#about to read 3, iclass 31, count 2 2006.201.23:45:49.36#ibcon#read 3, iclass 31, count 2 2006.201.23:45:49.36#ibcon#about to read 4, iclass 31, count 2 2006.201.23:45:49.36#ibcon#read 4, iclass 31, count 2 2006.201.23:45:49.36#ibcon#about to read 5, iclass 31, count 2 2006.201.23:45:49.36#ibcon#read 5, iclass 31, count 2 2006.201.23:45:49.36#ibcon#about to read 6, iclass 31, count 2 2006.201.23:45:49.36#ibcon#read 6, iclass 31, count 2 2006.201.23:45:49.36#ibcon#end of sib2, iclass 31, count 2 2006.201.23:45:49.36#ibcon#*mode == 0, iclass 31, count 2 2006.201.23:45:49.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.23:45:49.36#ibcon#[25=AT03-08\r\n] 2006.201.23:45:49.36#ibcon#*before write, iclass 31, count 2 2006.201.23:45:49.36#ibcon#enter sib2, iclass 31, count 2 2006.201.23:45:49.36#ibcon#flushed, iclass 31, count 2 2006.201.23:45:49.36#ibcon#about to write, iclass 31, count 2 2006.201.23:45:49.36#ibcon#wrote, iclass 31, count 2 2006.201.23:45:49.36#ibcon#about to read 3, iclass 31, count 2 2006.201.23:45:49.39#ibcon#read 3, iclass 31, count 2 2006.201.23:45:49.39#ibcon#about to read 4, iclass 31, count 2 2006.201.23:45:49.39#ibcon#read 4, iclass 31, count 2 2006.201.23:45:49.39#ibcon#about to read 5, iclass 31, count 2 2006.201.23:45:49.39#ibcon#read 5, iclass 31, count 2 2006.201.23:45:49.39#ibcon#about to read 6, iclass 31, count 2 2006.201.23:45:49.39#ibcon#read 6, iclass 31, count 2 2006.201.23:45:49.39#ibcon#end of sib2, iclass 31, count 2 2006.201.23:45:49.39#ibcon#*after write, iclass 31, count 2 2006.201.23:45:49.39#ibcon#*before return 0, iclass 31, count 2 2006.201.23:45:49.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:49.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:49.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.23:45:49.39#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:49.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:49.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:49.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:49.51#ibcon#enter wrdev, iclass 31, count 0 2006.201.23:45:49.51#ibcon#first serial, iclass 31, count 0 2006.201.23:45:49.51#ibcon#enter sib2, iclass 31, count 0 2006.201.23:45:49.51#ibcon#flushed, iclass 31, count 0 2006.201.23:45:49.51#ibcon#about to write, iclass 31, count 0 2006.201.23:45:49.51#ibcon#wrote, iclass 31, count 0 2006.201.23:45:49.51#ibcon#about to read 3, iclass 31, count 0 2006.201.23:45:49.53#ibcon#read 3, iclass 31, count 0 2006.201.23:45:49.53#ibcon#about to read 4, iclass 31, count 0 2006.201.23:45:49.53#ibcon#read 4, iclass 31, count 0 2006.201.23:45:49.53#ibcon#about to read 5, iclass 31, count 0 2006.201.23:45:49.53#ibcon#read 5, iclass 31, count 0 2006.201.23:45:49.53#ibcon#about to read 6, iclass 31, count 0 2006.201.23:45:49.53#ibcon#read 6, iclass 31, count 0 2006.201.23:45:49.53#ibcon#end of sib2, iclass 31, count 0 2006.201.23:45:49.53#ibcon#*mode == 0, iclass 31, count 0 2006.201.23:45:49.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.23:45:49.53#ibcon#[25=USB\r\n] 2006.201.23:45:49.53#ibcon#*before write, iclass 31, count 0 2006.201.23:45:49.53#ibcon#enter sib2, iclass 31, count 0 2006.201.23:45:49.53#ibcon#flushed, iclass 31, count 0 2006.201.23:45:49.53#ibcon#about to write, iclass 31, count 0 2006.201.23:45:49.53#ibcon#wrote, iclass 31, count 0 2006.201.23:45:49.53#ibcon#about to read 3, iclass 31, count 0 2006.201.23:45:49.56#ibcon#read 3, iclass 31, count 0 2006.201.23:45:49.56#ibcon#about to read 4, iclass 31, count 0 2006.201.23:45:49.56#ibcon#read 4, iclass 31, count 0 2006.201.23:45:49.56#ibcon#about to read 5, iclass 31, count 0 2006.201.23:45:49.56#ibcon#read 5, iclass 31, count 0 2006.201.23:45:49.56#ibcon#about to read 6, iclass 31, count 0 2006.201.23:45:49.56#ibcon#read 6, iclass 31, count 0 2006.201.23:45:49.56#ibcon#end of sib2, iclass 31, count 0 2006.201.23:45:49.56#ibcon#*after write, iclass 31, count 0 2006.201.23:45:49.56#ibcon#*before return 0, iclass 31, count 0 2006.201.23:45:49.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:49.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:49.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.23:45:49.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.23:45:49.56$vck44/valo=4,624.99 2006.201.23:45:49.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.23:45:49.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.23:45:49.56#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:49.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:49.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:49.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:49.56#ibcon#enter wrdev, iclass 33, count 0 2006.201.23:45:49.56#ibcon#first serial, iclass 33, count 0 2006.201.23:45:49.56#ibcon#enter sib2, iclass 33, count 0 2006.201.23:45:49.56#ibcon#flushed, iclass 33, count 0 2006.201.23:45:49.56#ibcon#about to write, iclass 33, count 0 2006.201.23:45:49.56#ibcon#wrote, iclass 33, count 0 2006.201.23:45:49.56#ibcon#about to read 3, iclass 33, count 0 2006.201.23:45:49.58#ibcon#read 3, iclass 33, count 0 2006.201.23:45:49.58#ibcon#about to read 4, iclass 33, count 0 2006.201.23:45:49.58#ibcon#read 4, iclass 33, count 0 2006.201.23:45:49.58#ibcon#about to read 5, iclass 33, count 0 2006.201.23:45:49.58#ibcon#read 5, iclass 33, count 0 2006.201.23:45:49.58#ibcon#about to read 6, iclass 33, count 0 2006.201.23:45:49.58#ibcon#read 6, iclass 33, count 0 2006.201.23:45:49.58#ibcon#end of sib2, iclass 33, count 0 2006.201.23:45:49.58#ibcon#*mode == 0, iclass 33, count 0 2006.201.23:45:49.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.23:45:49.58#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.23:45:49.58#ibcon#*before write, iclass 33, count 0 2006.201.23:45:49.58#ibcon#enter sib2, iclass 33, count 0 2006.201.23:45:49.58#ibcon#flushed, iclass 33, count 0 2006.201.23:45:49.58#ibcon#about to write, iclass 33, count 0 2006.201.23:45:49.58#ibcon#wrote, iclass 33, count 0 2006.201.23:45:49.58#ibcon#about to read 3, iclass 33, count 0 2006.201.23:45:49.62#ibcon#read 3, iclass 33, count 0 2006.201.23:45:49.62#ibcon#about to read 4, iclass 33, count 0 2006.201.23:45:49.62#ibcon#read 4, iclass 33, count 0 2006.201.23:45:49.62#ibcon#about to read 5, iclass 33, count 0 2006.201.23:45:49.62#ibcon#read 5, iclass 33, count 0 2006.201.23:45:49.62#ibcon#about to read 6, iclass 33, count 0 2006.201.23:45:49.62#ibcon#read 6, iclass 33, count 0 2006.201.23:45:49.62#ibcon#end of sib2, iclass 33, count 0 2006.201.23:45:49.62#ibcon#*after write, iclass 33, count 0 2006.201.23:45:49.62#ibcon#*before return 0, iclass 33, count 0 2006.201.23:45:49.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:49.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:49.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.23:45:49.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.23:45:49.62$vck44/va=4,7 2006.201.23:45:49.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.23:45:49.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.23:45:49.62#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:49.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:49.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:49.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:49.68#ibcon#enter wrdev, iclass 35, count 2 2006.201.23:45:49.68#ibcon#first serial, iclass 35, count 2 2006.201.23:45:49.68#ibcon#enter sib2, iclass 35, count 2 2006.201.23:45:49.68#ibcon#flushed, iclass 35, count 2 2006.201.23:45:49.68#ibcon#about to write, iclass 35, count 2 2006.201.23:45:49.68#ibcon#wrote, iclass 35, count 2 2006.201.23:45:49.68#ibcon#about to read 3, iclass 35, count 2 2006.201.23:45:49.70#ibcon#read 3, iclass 35, count 2 2006.201.23:45:49.70#ibcon#about to read 4, iclass 35, count 2 2006.201.23:45:49.70#ibcon#read 4, iclass 35, count 2 2006.201.23:45:49.70#ibcon#about to read 5, iclass 35, count 2 2006.201.23:45:49.70#ibcon#read 5, iclass 35, count 2 2006.201.23:45:49.70#ibcon#about to read 6, iclass 35, count 2 2006.201.23:45:49.70#ibcon#read 6, iclass 35, count 2 2006.201.23:45:49.70#ibcon#end of sib2, iclass 35, count 2 2006.201.23:45:49.70#ibcon#*mode == 0, iclass 35, count 2 2006.201.23:45:49.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.23:45:49.70#ibcon#[25=AT04-07\r\n] 2006.201.23:45:49.70#ibcon#*before write, iclass 35, count 2 2006.201.23:45:49.70#ibcon#enter sib2, iclass 35, count 2 2006.201.23:45:49.70#ibcon#flushed, iclass 35, count 2 2006.201.23:45:49.70#ibcon#about to write, iclass 35, count 2 2006.201.23:45:49.70#ibcon#wrote, iclass 35, count 2 2006.201.23:45:49.70#ibcon#about to read 3, iclass 35, count 2 2006.201.23:45:49.73#ibcon#read 3, iclass 35, count 2 2006.201.23:45:49.73#ibcon#about to read 4, iclass 35, count 2 2006.201.23:45:49.73#ibcon#read 4, iclass 35, count 2 2006.201.23:45:49.73#ibcon#about to read 5, iclass 35, count 2 2006.201.23:45:49.73#ibcon#read 5, iclass 35, count 2 2006.201.23:45:49.73#ibcon#about to read 6, iclass 35, count 2 2006.201.23:45:49.73#ibcon#read 6, iclass 35, count 2 2006.201.23:45:49.73#ibcon#end of sib2, iclass 35, count 2 2006.201.23:45:49.73#ibcon#*after write, iclass 35, count 2 2006.201.23:45:49.73#ibcon#*before return 0, iclass 35, count 2 2006.201.23:45:49.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:49.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:49.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.23:45:49.73#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:49.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:49.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:49.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:49.85#ibcon#enter wrdev, iclass 35, count 0 2006.201.23:45:49.85#ibcon#first serial, iclass 35, count 0 2006.201.23:45:49.85#ibcon#enter sib2, iclass 35, count 0 2006.201.23:45:49.85#ibcon#flushed, iclass 35, count 0 2006.201.23:45:49.85#ibcon#about to write, iclass 35, count 0 2006.201.23:45:49.85#ibcon#wrote, iclass 35, count 0 2006.201.23:45:49.85#ibcon#about to read 3, iclass 35, count 0 2006.201.23:45:49.87#ibcon#read 3, iclass 35, count 0 2006.201.23:45:49.87#ibcon#about to read 4, iclass 35, count 0 2006.201.23:45:49.87#ibcon#read 4, iclass 35, count 0 2006.201.23:45:49.87#ibcon#about to read 5, iclass 35, count 0 2006.201.23:45:49.87#ibcon#read 5, iclass 35, count 0 2006.201.23:45:49.87#ibcon#about to read 6, iclass 35, count 0 2006.201.23:45:49.87#ibcon#read 6, iclass 35, count 0 2006.201.23:45:49.87#ibcon#end of sib2, iclass 35, count 0 2006.201.23:45:49.87#ibcon#*mode == 0, iclass 35, count 0 2006.201.23:45:49.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.23:45:49.87#ibcon#[25=USB\r\n] 2006.201.23:45:49.87#ibcon#*before write, iclass 35, count 0 2006.201.23:45:49.87#ibcon#enter sib2, iclass 35, count 0 2006.201.23:45:49.87#ibcon#flushed, iclass 35, count 0 2006.201.23:45:49.87#ibcon#about to write, iclass 35, count 0 2006.201.23:45:49.87#ibcon#wrote, iclass 35, count 0 2006.201.23:45:49.87#ibcon#about to read 3, iclass 35, count 0 2006.201.23:45:49.90#ibcon#read 3, iclass 35, count 0 2006.201.23:45:49.90#ibcon#about to read 4, iclass 35, count 0 2006.201.23:45:49.90#ibcon#read 4, iclass 35, count 0 2006.201.23:45:49.90#ibcon#about to read 5, iclass 35, count 0 2006.201.23:45:49.90#ibcon#read 5, iclass 35, count 0 2006.201.23:45:49.90#ibcon#about to read 6, iclass 35, count 0 2006.201.23:45:49.90#ibcon#read 6, iclass 35, count 0 2006.201.23:45:49.90#ibcon#end of sib2, iclass 35, count 0 2006.201.23:45:49.90#ibcon#*after write, iclass 35, count 0 2006.201.23:45:49.90#ibcon#*before return 0, iclass 35, count 0 2006.201.23:45:49.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:49.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:49.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.23:45:49.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.23:45:49.90$vck44/valo=5,734.99 2006.201.23:45:49.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.23:45:49.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.23:45:49.90#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:49.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:49.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:49.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:49.90#ibcon#enter wrdev, iclass 37, count 0 2006.201.23:45:49.90#ibcon#first serial, iclass 37, count 0 2006.201.23:45:49.90#ibcon#enter sib2, iclass 37, count 0 2006.201.23:45:49.90#ibcon#flushed, iclass 37, count 0 2006.201.23:45:49.90#ibcon#about to write, iclass 37, count 0 2006.201.23:45:49.90#ibcon#wrote, iclass 37, count 0 2006.201.23:45:49.90#ibcon#about to read 3, iclass 37, count 0 2006.201.23:45:49.92#ibcon#read 3, iclass 37, count 0 2006.201.23:45:49.92#ibcon#about to read 4, iclass 37, count 0 2006.201.23:45:49.92#ibcon#read 4, iclass 37, count 0 2006.201.23:45:49.92#ibcon#about to read 5, iclass 37, count 0 2006.201.23:45:49.92#ibcon#read 5, iclass 37, count 0 2006.201.23:45:49.92#ibcon#about to read 6, iclass 37, count 0 2006.201.23:45:49.92#ibcon#read 6, iclass 37, count 0 2006.201.23:45:49.92#ibcon#end of sib2, iclass 37, count 0 2006.201.23:45:49.92#ibcon#*mode == 0, iclass 37, count 0 2006.201.23:45:49.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.23:45:49.92#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.23:45:49.92#ibcon#*before write, iclass 37, count 0 2006.201.23:45:49.92#ibcon#enter sib2, iclass 37, count 0 2006.201.23:45:49.92#ibcon#flushed, iclass 37, count 0 2006.201.23:45:49.92#ibcon#about to write, iclass 37, count 0 2006.201.23:45:49.92#ibcon#wrote, iclass 37, count 0 2006.201.23:45:49.92#ibcon#about to read 3, iclass 37, count 0 2006.201.23:45:49.96#ibcon#read 3, iclass 37, count 0 2006.201.23:45:49.96#ibcon#about to read 4, iclass 37, count 0 2006.201.23:45:49.96#ibcon#read 4, iclass 37, count 0 2006.201.23:45:49.96#ibcon#about to read 5, iclass 37, count 0 2006.201.23:45:49.96#ibcon#read 5, iclass 37, count 0 2006.201.23:45:49.96#ibcon#about to read 6, iclass 37, count 0 2006.201.23:45:49.96#ibcon#read 6, iclass 37, count 0 2006.201.23:45:49.96#ibcon#end of sib2, iclass 37, count 0 2006.201.23:45:49.96#ibcon#*after write, iclass 37, count 0 2006.201.23:45:49.96#ibcon#*before return 0, iclass 37, count 0 2006.201.23:45:49.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:49.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:49.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.23:45:49.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.23:45:49.96$vck44/va=5,4 2006.201.23:45:49.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.23:45:49.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.23:45:49.96#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:49.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:50.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:50.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:50.02#ibcon#enter wrdev, iclass 39, count 2 2006.201.23:45:50.02#ibcon#first serial, iclass 39, count 2 2006.201.23:45:50.02#ibcon#enter sib2, iclass 39, count 2 2006.201.23:45:50.02#ibcon#flushed, iclass 39, count 2 2006.201.23:45:50.02#ibcon#about to write, iclass 39, count 2 2006.201.23:45:50.02#ibcon#wrote, iclass 39, count 2 2006.201.23:45:50.02#ibcon#about to read 3, iclass 39, count 2 2006.201.23:45:50.04#ibcon#read 3, iclass 39, count 2 2006.201.23:45:50.04#ibcon#about to read 4, iclass 39, count 2 2006.201.23:45:50.04#ibcon#read 4, iclass 39, count 2 2006.201.23:45:50.04#ibcon#about to read 5, iclass 39, count 2 2006.201.23:45:50.04#ibcon#read 5, iclass 39, count 2 2006.201.23:45:50.04#ibcon#about to read 6, iclass 39, count 2 2006.201.23:45:50.04#ibcon#read 6, iclass 39, count 2 2006.201.23:45:50.04#ibcon#end of sib2, iclass 39, count 2 2006.201.23:45:50.04#ibcon#*mode == 0, iclass 39, count 2 2006.201.23:45:50.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.23:45:50.04#ibcon#[25=AT05-04\r\n] 2006.201.23:45:50.04#ibcon#*before write, iclass 39, count 2 2006.201.23:45:50.04#ibcon#enter sib2, iclass 39, count 2 2006.201.23:45:50.04#ibcon#flushed, iclass 39, count 2 2006.201.23:45:50.04#ibcon#about to write, iclass 39, count 2 2006.201.23:45:50.04#ibcon#wrote, iclass 39, count 2 2006.201.23:45:50.04#ibcon#about to read 3, iclass 39, count 2 2006.201.23:45:50.07#ibcon#read 3, iclass 39, count 2 2006.201.23:45:50.07#ibcon#about to read 4, iclass 39, count 2 2006.201.23:45:50.07#ibcon#read 4, iclass 39, count 2 2006.201.23:45:50.07#ibcon#about to read 5, iclass 39, count 2 2006.201.23:45:50.07#ibcon#read 5, iclass 39, count 2 2006.201.23:45:50.07#ibcon#about to read 6, iclass 39, count 2 2006.201.23:45:50.07#ibcon#read 6, iclass 39, count 2 2006.201.23:45:50.07#ibcon#end of sib2, iclass 39, count 2 2006.201.23:45:50.07#ibcon#*after write, iclass 39, count 2 2006.201.23:45:50.07#ibcon#*before return 0, iclass 39, count 2 2006.201.23:45:50.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:50.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:50.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.23:45:50.07#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:50.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:50.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:50.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:50.19#ibcon#enter wrdev, iclass 39, count 0 2006.201.23:45:50.19#ibcon#first serial, iclass 39, count 0 2006.201.23:45:50.19#ibcon#enter sib2, iclass 39, count 0 2006.201.23:45:50.19#ibcon#flushed, iclass 39, count 0 2006.201.23:45:50.19#ibcon#about to write, iclass 39, count 0 2006.201.23:45:50.19#ibcon#wrote, iclass 39, count 0 2006.201.23:45:50.19#ibcon#about to read 3, iclass 39, count 0 2006.201.23:45:50.21#ibcon#read 3, iclass 39, count 0 2006.201.23:45:50.21#ibcon#about to read 4, iclass 39, count 0 2006.201.23:45:50.21#ibcon#read 4, iclass 39, count 0 2006.201.23:45:50.21#ibcon#about to read 5, iclass 39, count 0 2006.201.23:45:50.21#ibcon#read 5, iclass 39, count 0 2006.201.23:45:50.21#ibcon#about to read 6, iclass 39, count 0 2006.201.23:45:50.21#ibcon#read 6, iclass 39, count 0 2006.201.23:45:50.21#ibcon#end of sib2, iclass 39, count 0 2006.201.23:45:50.21#ibcon#*mode == 0, iclass 39, count 0 2006.201.23:45:50.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.23:45:50.21#ibcon#[25=USB\r\n] 2006.201.23:45:50.21#ibcon#*before write, iclass 39, count 0 2006.201.23:45:50.21#ibcon#enter sib2, iclass 39, count 0 2006.201.23:45:50.21#ibcon#flushed, iclass 39, count 0 2006.201.23:45:50.21#ibcon#about to write, iclass 39, count 0 2006.201.23:45:50.21#ibcon#wrote, iclass 39, count 0 2006.201.23:45:50.21#ibcon#about to read 3, iclass 39, count 0 2006.201.23:45:50.24#ibcon#read 3, iclass 39, count 0 2006.201.23:45:50.24#ibcon#about to read 4, iclass 39, count 0 2006.201.23:45:50.24#ibcon#read 4, iclass 39, count 0 2006.201.23:45:50.24#ibcon#about to read 5, iclass 39, count 0 2006.201.23:45:50.24#ibcon#read 5, iclass 39, count 0 2006.201.23:45:50.24#ibcon#about to read 6, iclass 39, count 0 2006.201.23:45:50.24#ibcon#read 6, iclass 39, count 0 2006.201.23:45:50.24#ibcon#end of sib2, iclass 39, count 0 2006.201.23:45:50.24#ibcon#*after write, iclass 39, count 0 2006.201.23:45:50.24#ibcon#*before return 0, iclass 39, count 0 2006.201.23:45:50.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:50.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:50.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.23:45:50.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.23:45:50.24$vck44/valo=6,814.99 2006.201.23:45:50.24#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.23:45:50.24#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.23:45:50.24#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:50.24#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:50.24#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:50.24#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:50.24#ibcon#enter wrdev, iclass 2, count 0 2006.201.23:45:50.24#ibcon#first serial, iclass 2, count 0 2006.201.23:45:50.24#ibcon#enter sib2, iclass 2, count 0 2006.201.23:45:50.24#ibcon#flushed, iclass 2, count 0 2006.201.23:45:50.24#ibcon#about to write, iclass 2, count 0 2006.201.23:45:50.24#ibcon#wrote, iclass 2, count 0 2006.201.23:45:50.24#ibcon#about to read 3, iclass 2, count 0 2006.201.23:45:50.26#ibcon#read 3, iclass 2, count 0 2006.201.23:45:50.26#ibcon#about to read 4, iclass 2, count 0 2006.201.23:45:50.26#ibcon#read 4, iclass 2, count 0 2006.201.23:45:50.26#ibcon#about to read 5, iclass 2, count 0 2006.201.23:45:50.26#ibcon#read 5, iclass 2, count 0 2006.201.23:45:50.26#ibcon#about to read 6, iclass 2, count 0 2006.201.23:45:50.26#ibcon#read 6, iclass 2, count 0 2006.201.23:45:50.26#ibcon#end of sib2, iclass 2, count 0 2006.201.23:45:50.26#ibcon#*mode == 0, iclass 2, count 0 2006.201.23:45:50.26#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.23:45:50.26#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.23:45:50.26#ibcon#*before write, iclass 2, count 0 2006.201.23:45:50.26#ibcon#enter sib2, iclass 2, count 0 2006.201.23:45:50.26#ibcon#flushed, iclass 2, count 0 2006.201.23:45:50.26#ibcon#about to write, iclass 2, count 0 2006.201.23:45:50.26#ibcon#wrote, iclass 2, count 0 2006.201.23:45:50.26#ibcon#about to read 3, iclass 2, count 0 2006.201.23:45:50.30#ibcon#read 3, iclass 2, count 0 2006.201.23:45:50.30#ibcon#about to read 4, iclass 2, count 0 2006.201.23:45:50.30#ibcon#read 4, iclass 2, count 0 2006.201.23:45:50.30#ibcon#about to read 5, iclass 2, count 0 2006.201.23:45:50.30#ibcon#read 5, iclass 2, count 0 2006.201.23:45:50.30#ibcon#about to read 6, iclass 2, count 0 2006.201.23:45:50.30#ibcon#read 6, iclass 2, count 0 2006.201.23:45:50.30#ibcon#end of sib2, iclass 2, count 0 2006.201.23:45:50.30#ibcon#*after write, iclass 2, count 0 2006.201.23:45:50.30#ibcon#*before return 0, iclass 2, count 0 2006.201.23:45:50.30#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:50.30#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:50.30#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.23:45:50.30#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.23:45:50.30$vck44/va=6,5 2006.201.23:45:50.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.23:45:50.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.23:45:50.30#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:50.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:50.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:50.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:50.36#ibcon#enter wrdev, iclass 5, count 2 2006.201.23:45:50.36#ibcon#first serial, iclass 5, count 2 2006.201.23:45:50.36#ibcon#enter sib2, iclass 5, count 2 2006.201.23:45:50.36#ibcon#flushed, iclass 5, count 2 2006.201.23:45:50.36#ibcon#about to write, iclass 5, count 2 2006.201.23:45:50.36#ibcon#wrote, iclass 5, count 2 2006.201.23:45:50.36#ibcon#about to read 3, iclass 5, count 2 2006.201.23:45:50.38#ibcon#read 3, iclass 5, count 2 2006.201.23:45:50.38#ibcon#about to read 4, iclass 5, count 2 2006.201.23:45:50.38#ibcon#read 4, iclass 5, count 2 2006.201.23:45:50.38#ibcon#about to read 5, iclass 5, count 2 2006.201.23:45:50.38#ibcon#read 5, iclass 5, count 2 2006.201.23:45:50.38#ibcon#about to read 6, iclass 5, count 2 2006.201.23:45:50.38#ibcon#read 6, iclass 5, count 2 2006.201.23:45:50.38#ibcon#end of sib2, iclass 5, count 2 2006.201.23:45:50.38#ibcon#*mode == 0, iclass 5, count 2 2006.201.23:45:50.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.23:45:50.38#ibcon#[25=AT06-05\r\n] 2006.201.23:45:50.38#ibcon#*before write, iclass 5, count 2 2006.201.23:45:50.38#ibcon#enter sib2, iclass 5, count 2 2006.201.23:45:50.38#ibcon#flushed, iclass 5, count 2 2006.201.23:45:50.38#ibcon#about to write, iclass 5, count 2 2006.201.23:45:50.38#ibcon#wrote, iclass 5, count 2 2006.201.23:45:50.38#ibcon#about to read 3, iclass 5, count 2 2006.201.23:45:50.41#ibcon#read 3, iclass 5, count 2 2006.201.23:45:50.41#ibcon#about to read 4, iclass 5, count 2 2006.201.23:45:50.41#ibcon#read 4, iclass 5, count 2 2006.201.23:45:50.41#ibcon#about to read 5, iclass 5, count 2 2006.201.23:45:50.41#ibcon#read 5, iclass 5, count 2 2006.201.23:45:50.41#ibcon#about to read 6, iclass 5, count 2 2006.201.23:45:50.41#ibcon#read 6, iclass 5, count 2 2006.201.23:45:50.41#ibcon#end of sib2, iclass 5, count 2 2006.201.23:45:50.41#ibcon#*after write, iclass 5, count 2 2006.201.23:45:50.41#ibcon#*before return 0, iclass 5, count 2 2006.201.23:45:50.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:50.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:50.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.23:45:50.41#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:50.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:50.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:50.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:50.53#ibcon#enter wrdev, iclass 5, count 0 2006.201.23:45:50.53#ibcon#first serial, iclass 5, count 0 2006.201.23:45:50.53#ibcon#enter sib2, iclass 5, count 0 2006.201.23:45:50.53#ibcon#flushed, iclass 5, count 0 2006.201.23:45:50.53#ibcon#about to write, iclass 5, count 0 2006.201.23:45:50.53#ibcon#wrote, iclass 5, count 0 2006.201.23:45:50.53#ibcon#about to read 3, iclass 5, count 0 2006.201.23:45:50.55#ibcon#read 3, iclass 5, count 0 2006.201.23:45:50.55#ibcon#about to read 4, iclass 5, count 0 2006.201.23:45:50.55#ibcon#read 4, iclass 5, count 0 2006.201.23:45:50.55#ibcon#about to read 5, iclass 5, count 0 2006.201.23:45:50.55#ibcon#read 5, iclass 5, count 0 2006.201.23:45:50.55#ibcon#about to read 6, iclass 5, count 0 2006.201.23:45:50.55#ibcon#read 6, iclass 5, count 0 2006.201.23:45:50.55#ibcon#end of sib2, iclass 5, count 0 2006.201.23:45:50.55#ibcon#*mode == 0, iclass 5, count 0 2006.201.23:45:50.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.23:45:50.55#ibcon#[25=USB\r\n] 2006.201.23:45:50.55#ibcon#*before write, iclass 5, count 0 2006.201.23:45:50.55#ibcon#enter sib2, iclass 5, count 0 2006.201.23:45:50.55#ibcon#flushed, iclass 5, count 0 2006.201.23:45:50.55#ibcon#about to write, iclass 5, count 0 2006.201.23:45:50.55#ibcon#wrote, iclass 5, count 0 2006.201.23:45:50.55#ibcon#about to read 3, iclass 5, count 0 2006.201.23:45:50.58#ibcon#read 3, iclass 5, count 0 2006.201.23:45:50.58#ibcon#about to read 4, iclass 5, count 0 2006.201.23:45:50.58#ibcon#read 4, iclass 5, count 0 2006.201.23:45:50.58#ibcon#about to read 5, iclass 5, count 0 2006.201.23:45:50.58#ibcon#read 5, iclass 5, count 0 2006.201.23:45:50.58#ibcon#about to read 6, iclass 5, count 0 2006.201.23:45:50.58#ibcon#read 6, iclass 5, count 0 2006.201.23:45:50.58#ibcon#end of sib2, iclass 5, count 0 2006.201.23:45:50.58#ibcon#*after write, iclass 5, count 0 2006.201.23:45:50.58#ibcon#*before return 0, iclass 5, count 0 2006.201.23:45:50.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:50.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:50.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.23:45:50.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.23:45:50.58$vck44/valo=7,864.99 2006.201.23:45:50.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.23:45:50.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.23:45:50.58#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:50.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:50.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:50.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:50.58#ibcon#enter wrdev, iclass 7, count 0 2006.201.23:45:50.58#ibcon#first serial, iclass 7, count 0 2006.201.23:45:50.58#ibcon#enter sib2, iclass 7, count 0 2006.201.23:45:50.58#ibcon#flushed, iclass 7, count 0 2006.201.23:45:50.58#ibcon#about to write, iclass 7, count 0 2006.201.23:45:50.58#ibcon#wrote, iclass 7, count 0 2006.201.23:45:50.58#ibcon#about to read 3, iclass 7, count 0 2006.201.23:45:50.60#ibcon#read 3, iclass 7, count 0 2006.201.23:45:50.60#ibcon#about to read 4, iclass 7, count 0 2006.201.23:45:50.60#ibcon#read 4, iclass 7, count 0 2006.201.23:45:50.60#ibcon#about to read 5, iclass 7, count 0 2006.201.23:45:50.60#ibcon#read 5, iclass 7, count 0 2006.201.23:45:50.60#ibcon#about to read 6, iclass 7, count 0 2006.201.23:45:50.60#ibcon#read 6, iclass 7, count 0 2006.201.23:45:50.60#ibcon#end of sib2, iclass 7, count 0 2006.201.23:45:50.60#ibcon#*mode == 0, iclass 7, count 0 2006.201.23:45:50.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.23:45:50.60#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.23:45:50.60#ibcon#*before write, iclass 7, count 0 2006.201.23:45:50.60#ibcon#enter sib2, iclass 7, count 0 2006.201.23:45:50.60#ibcon#flushed, iclass 7, count 0 2006.201.23:45:50.60#ibcon#about to write, iclass 7, count 0 2006.201.23:45:50.60#ibcon#wrote, iclass 7, count 0 2006.201.23:45:50.60#ibcon#about to read 3, iclass 7, count 0 2006.201.23:45:50.64#ibcon#read 3, iclass 7, count 0 2006.201.23:45:50.64#ibcon#about to read 4, iclass 7, count 0 2006.201.23:45:50.64#ibcon#read 4, iclass 7, count 0 2006.201.23:45:50.64#ibcon#about to read 5, iclass 7, count 0 2006.201.23:45:50.64#ibcon#read 5, iclass 7, count 0 2006.201.23:45:50.64#ibcon#about to read 6, iclass 7, count 0 2006.201.23:45:50.64#ibcon#read 6, iclass 7, count 0 2006.201.23:45:50.64#ibcon#end of sib2, iclass 7, count 0 2006.201.23:45:50.64#ibcon#*after write, iclass 7, count 0 2006.201.23:45:50.64#ibcon#*before return 0, iclass 7, count 0 2006.201.23:45:50.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:50.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:50.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.23:45:50.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.23:45:50.64$vck44/va=7,5 2006.201.23:45:50.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.23:45:50.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.23:45:50.64#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:50.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:50.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:50.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:50.70#ibcon#enter wrdev, iclass 11, count 2 2006.201.23:45:50.70#ibcon#first serial, iclass 11, count 2 2006.201.23:45:50.70#ibcon#enter sib2, iclass 11, count 2 2006.201.23:45:50.70#ibcon#flushed, iclass 11, count 2 2006.201.23:45:50.70#ibcon#about to write, iclass 11, count 2 2006.201.23:45:50.70#ibcon#wrote, iclass 11, count 2 2006.201.23:45:50.70#ibcon#about to read 3, iclass 11, count 2 2006.201.23:45:50.72#ibcon#read 3, iclass 11, count 2 2006.201.23:45:50.72#ibcon#about to read 4, iclass 11, count 2 2006.201.23:45:50.72#ibcon#read 4, iclass 11, count 2 2006.201.23:45:50.72#ibcon#about to read 5, iclass 11, count 2 2006.201.23:45:50.72#ibcon#read 5, iclass 11, count 2 2006.201.23:45:50.72#ibcon#about to read 6, iclass 11, count 2 2006.201.23:45:50.72#ibcon#read 6, iclass 11, count 2 2006.201.23:45:50.72#ibcon#end of sib2, iclass 11, count 2 2006.201.23:45:50.72#ibcon#*mode == 0, iclass 11, count 2 2006.201.23:45:50.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.23:45:50.72#ibcon#[25=AT07-05\r\n] 2006.201.23:45:50.72#ibcon#*before write, iclass 11, count 2 2006.201.23:45:50.72#ibcon#enter sib2, iclass 11, count 2 2006.201.23:45:50.72#ibcon#flushed, iclass 11, count 2 2006.201.23:45:50.72#ibcon#about to write, iclass 11, count 2 2006.201.23:45:50.72#ibcon#wrote, iclass 11, count 2 2006.201.23:45:50.72#ibcon#about to read 3, iclass 11, count 2 2006.201.23:45:50.75#ibcon#read 3, iclass 11, count 2 2006.201.23:45:50.75#ibcon#about to read 4, iclass 11, count 2 2006.201.23:45:50.75#ibcon#read 4, iclass 11, count 2 2006.201.23:45:50.75#ibcon#about to read 5, iclass 11, count 2 2006.201.23:45:50.75#ibcon#read 5, iclass 11, count 2 2006.201.23:45:50.75#ibcon#about to read 6, iclass 11, count 2 2006.201.23:45:50.75#ibcon#read 6, iclass 11, count 2 2006.201.23:45:50.75#ibcon#end of sib2, iclass 11, count 2 2006.201.23:45:50.75#ibcon#*after write, iclass 11, count 2 2006.201.23:45:50.75#ibcon#*before return 0, iclass 11, count 2 2006.201.23:45:50.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:50.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:50.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.23:45:50.75#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:50.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:50.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:50.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:50.87#ibcon#enter wrdev, iclass 11, count 0 2006.201.23:45:50.87#ibcon#first serial, iclass 11, count 0 2006.201.23:45:50.87#ibcon#enter sib2, iclass 11, count 0 2006.201.23:45:50.87#ibcon#flushed, iclass 11, count 0 2006.201.23:45:50.87#ibcon#about to write, iclass 11, count 0 2006.201.23:45:50.87#ibcon#wrote, iclass 11, count 0 2006.201.23:45:50.87#ibcon#about to read 3, iclass 11, count 0 2006.201.23:45:50.89#ibcon#read 3, iclass 11, count 0 2006.201.23:45:50.89#ibcon#about to read 4, iclass 11, count 0 2006.201.23:45:50.89#ibcon#read 4, iclass 11, count 0 2006.201.23:45:50.89#ibcon#about to read 5, iclass 11, count 0 2006.201.23:45:50.89#ibcon#read 5, iclass 11, count 0 2006.201.23:45:50.89#ibcon#about to read 6, iclass 11, count 0 2006.201.23:45:50.89#ibcon#read 6, iclass 11, count 0 2006.201.23:45:50.89#ibcon#end of sib2, iclass 11, count 0 2006.201.23:45:50.89#ibcon#*mode == 0, iclass 11, count 0 2006.201.23:45:50.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.23:45:50.89#ibcon#[25=USB\r\n] 2006.201.23:45:50.89#ibcon#*before write, iclass 11, count 0 2006.201.23:45:50.89#ibcon#enter sib2, iclass 11, count 0 2006.201.23:45:50.89#ibcon#flushed, iclass 11, count 0 2006.201.23:45:50.89#ibcon#about to write, iclass 11, count 0 2006.201.23:45:50.89#ibcon#wrote, iclass 11, count 0 2006.201.23:45:50.89#ibcon#about to read 3, iclass 11, count 0 2006.201.23:45:50.92#ibcon#read 3, iclass 11, count 0 2006.201.23:45:50.92#ibcon#about to read 4, iclass 11, count 0 2006.201.23:45:50.92#ibcon#read 4, iclass 11, count 0 2006.201.23:45:50.92#ibcon#about to read 5, iclass 11, count 0 2006.201.23:45:50.92#ibcon#read 5, iclass 11, count 0 2006.201.23:45:50.92#ibcon#about to read 6, iclass 11, count 0 2006.201.23:45:50.92#ibcon#read 6, iclass 11, count 0 2006.201.23:45:50.92#ibcon#end of sib2, iclass 11, count 0 2006.201.23:45:50.92#ibcon#*after write, iclass 11, count 0 2006.201.23:45:50.92#ibcon#*before return 0, iclass 11, count 0 2006.201.23:45:50.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:50.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:50.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.23:45:50.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.23:45:50.92$vck44/valo=8,884.99 2006.201.23:45:50.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.23:45:50.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.23:45:50.92#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:50.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:50.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:50.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:50.92#ibcon#enter wrdev, iclass 13, count 0 2006.201.23:45:50.92#ibcon#first serial, iclass 13, count 0 2006.201.23:45:50.92#ibcon#enter sib2, iclass 13, count 0 2006.201.23:45:50.92#ibcon#flushed, iclass 13, count 0 2006.201.23:45:50.92#ibcon#about to write, iclass 13, count 0 2006.201.23:45:50.92#ibcon#wrote, iclass 13, count 0 2006.201.23:45:50.92#ibcon#about to read 3, iclass 13, count 0 2006.201.23:45:50.94#ibcon#read 3, iclass 13, count 0 2006.201.23:45:50.94#ibcon#about to read 4, iclass 13, count 0 2006.201.23:45:50.94#ibcon#read 4, iclass 13, count 0 2006.201.23:45:50.94#ibcon#about to read 5, iclass 13, count 0 2006.201.23:45:50.94#ibcon#read 5, iclass 13, count 0 2006.201.23:45:50.94#ibcon#about to read 6, iclass 13, count 0 2006.201.23:45:50.94#ibcon#read 6, iclass 13, count 0 2006.201.23:45:50.94#ibcon#end of sib2, iclass 13, count 0 2006.201.23:45:50.94#ibcon#*mode == 0, iclass 13, count 0 2006.201.23:45:50.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.23:45:50.94#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.23:45:50.94#ibcon#*before write, iclass 13, count 0 2006.201.23:45:50.94#ibcon#enter sib2, iclass 13, count 0 2006.201.23:45:50.94#ibcon#flushed, iclass 13, count 0 2006.201.23:45:50.94#ibcon#about to write, iclass 13, count 0 2006.201.23:45:50.94#ibcon#wrote, iclass 13, count 0 2006.201.23:45:50.94#ibcon#about to read 3, iclass 13, count 0 2006.201.23:45:50.98#ibcon#read 3, iclass 13, count 0 2006.201.23:45:50.98#ibcon#about to read 4, iclass 13, count 0 2006.201.23:45:50.98#ibcon#read 4, iclass 13, count 0 2006.201.23:45:50.98#ibcon#about to read 5, iclass 13, count 0 2006.201.23:45:50.98#ibcon#read 5, iclass 13, count 0 2006.201.23:45:50.98#ibcon#about to read 6, iclass 13, count 0 2006.201.23:45:50.98#ibcon#read 6, iclass 13, count 0 2006.201.23:45:50.98#ibcon#end of sib2, iclass 13, count 0 2006.201.23:45:50.98#ibcon#*after write, iclass 13, count 0 2006.201.23:45:50.98#ibcon#*before return 0, iclass 13, count 0 2006.201.23:45:50.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:50.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:50.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.23:45:50.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.23:45:50.98$vck44/va=8,4 2006.201.23:45:50.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.201.23:45:50.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.201.23:45:50.98#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:50.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.23:45:51.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.201.23:45:51.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.23:45:51.04#ibcon#enter wrdev, iclass 15, count 2 2006.201.23:45:51.04#ibcon#first serial, iclass 15, count 2 2006.201.23:45:51.04#ibcon#enter sib2, iclass 15, count 2 2006.201.23:45:51.04#ibcon#flushed, iclass 15, count 2 2006.201.23:45:51.04#ibcon#about to write, iclass 15, count 2 2006.201.23:45:51.04#ibcon#wrote, iclass 15, count 2 2006.201.23:45:51.04#ibcon#about to read 3, iclass 15, count 2 2006.201.23:45:51.06#ibcon#read 3, iclass 15, count 2 2006.201.23:45:51.06#ibcon#about to read 4, iclass 15, count 2 2006.201.23:45:51.06#ibcon#read 4, iclass 15, count 2 2006.201.23:45:51.06#ibcon#about to read 5, iclass 15, count 2 2006.201.23:45:51.06#ibcon#read 5, iclass 15, count 2 2006.201.23:45:51.06#ibcon#about to read 6, iclass 15, count 2 2006.201.23:45:51.06#ibcon#read 6, iclass 15, count 2 2006.201.23:45:51.06#ibcon#end of sib2, iclass 15, count 2 2006.201.23:45:51.06#ibcon#*mode == 0, iclass 15, count 2 2006.201.23:45:51.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.201.23:45:51.06#ibcon#[25=AT08-04\r\n] 2006.201.23:45:51.06#ibcon#*before write, iclass 15, count 2 2006.201.23:45:51.06#ibcon#enter sib2, iclass 15, count 2 2006.201.23:45:51.06#ibcon#flushed, iclass 15, count 2 2006.201.23:45:51.06#ibcon#about to write, iclass 15, count 2 2006.201.23:45:51.06#ibcon#wrote, iclass 15, count 2 2006.201.23:45:51.06#ibcon#about to read 3, iclass 15, count 2 2006.201.23:45:51.09#ibcon#read 3, iclass 15, count 2 2006.201.23:45:51.09#ibcon#about to read 4, iclass 15, count 2 2006.201.23:45:51.09#ibcon#read 4, iclass 15, count 2 2006.201.23:45:51.09#ibcon#about to read 5, iclass 15, count 2 2006.201.23:45:51.09#ibcon#read 5, iclass 15, count 2 2006.201.23:45:51.09#ibcon#about to read 6, iclass 15, count 2 2006.201.23:45:51.09#ibcon#read 6, iclass 15, count 2 2006.201.23:45:51.09#ibcon#end of sib2, iclass 15, count 2 2006.201.23:45:51.09#ibcon#*after write, iclass 15, count 2 2006.201.23:45:51.09#ibcon#*before return 0, iclass 15, count 2 2006.201.23:45:51.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.201.23:45:51.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.201.23:45:51.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.201.23:45:51.09#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:51.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.23:45:51.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.201.23:45:51.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.23:45:51.21#ibcon#enter wrdev, iclass 15, count 0 2006.201.23:45:51.21#ibcon#first serial, iclass 15, count 0 2006.201.23:45:51.21#ibcon#enter sib2, iclass 15, count 0 2006.201.23:45:51.21#ibcon#flushed, iclass 15, count 0 2006.201.23:45:51.21#ibcon#about to write, iclass 15, count 0 2006.201.23:45:51.21#ibcon#wrote, iclass 15, count 0 2006.201.23:45:51.21#ibcon#about to read 3, iclass 15, count 0 2006.201.23:45:51.23#ibcon#read 3, iclass 15, count 0 2006.201.23:45:51.23#ibcon#about to read 4, iclass 15, count 0 2006.201.23:45:51.23#ibcon#read 4, iclass 15, count 0 2006.201.23:45:51.23#ibcon#about to read 5, iclass 15, count 0 2006.201.23:45:51.23#ibcon#read 5, iclass 15, count 0 2006.201.23:45:51.23#ibcon#about to read 6, iclass 15, count 0 2006.201.23:45:51.23#ibcon#read 6, iclass 15, count 0 2006.201.23:45:51.23#ibcon#end of sib2, iclass 15, count 0 2006.201.23:45:51.23#ibcon#*mode == 0, iclass 15, count 0 2006.201.23:45:51.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.23:45:51.23#ibcon#[25=USB\r\n] 2006.201.23:45:51.23#ibcon#*before write, iclass 15, count 0 2006.201.23:45:51.23#ibcon#enter sib2, iclass 15, count 0 2006.201.23:45:51.23#ibcon#flushed, iclass 15, count 0 2006.201.23:45:51.23#ibcon#about to write, iclass 15, count 0 2006.201.23:45:51.23#ibcon#wrote, iclass 15, count 0 2006.201.23:45:51.23#ibcon#about to read 3, iclass 15, count 0 2006.201.23:45:51.26#ibcon#read 3, iclass 15, count 0 2006.201.23:45:51.26#ibcon#about to read 4, iclass 15, count 0 2006.201.23:45:51.26#ibcon#read 4, iclass 15, count 0 2006.201.23:45:51.26#ibcon#about to read 5, iclass 15, count 0 2006.201.23:45:51.26#ibcon#read 5, iclass 15, count 0 2006.201.23:45:51.26#ibcon#about to read 6, iclass 15, count 0 2006.201.23:45:51.26#ibcon#read 6, iclass 15, count 0 2006.201.23:45:51.26#ibcon#end of sib2, iclass 15, count 0 2006.201.23:45:51.26#ibcon#*after write, iclass 15, count 0 2006.201.23:45:51.26#ibcon#*before return 0, iclass 15, count 0 2006.201.23:45:51.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.201.23:45:51.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.201.23:45:51.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.23:45:51.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.23:45:51.26$vck44/vblo=1,629.99 2006.201.23:45:51.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.201.23:45:51.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.201.23:45:51.26#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:51.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.23:45:51.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.201.23:45:51.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.23:45:51.26#ibcon#enter wrdev, iclass 17, count 0 2006.201.23:45:51.26#ibcon#first serial, iclass 17, count 0 2006.201.23:45:51.26#ibcon#enter sib2, iclass 17, count 0 2006.201.23:45:51.26#ibcon#flushed, iclass 17, count 0 2006.201.23:45:51.26#ibcon#about to write, iclass 17, count 0 2006.201.23:45:51.26#ibcon#wrote, iclass 17, count 0 2006.201.23:45:51.26#ibcon#about to read 3, iclass 17, count 0 2006.201.23:45:51.28#ibcon#read 3, iclass 17, count 0 2006.201.23:45:51.28#ibcon#about to read 4, iclass 17, count 0 2006.201.23:45:51.28#ibcon#read 4, iclass 17, count 0 2006.201.23:45:51.28#ibcon#about to read 5, iclass 17, count 0 2006.201.23:45:51.28#ibcon#read 5, iclass 17, count 0 2006.201.23:45:51.28#ibcon#about to read 6, iclass 17, count 0 2006.201.23:45:51.28#ibcon#read 6, iclass 17, count 0 2006.201.23:45:51.28#ibcon#end of sib2, iclass 17, count 0 2006.201.23:45:51.28#ibcon#*mode == 0, iclass 17, count 0 2006.201.23:45:51.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.201.23:45:51.28#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.23:45:51.28#ibcon#*before write, iclass 17, count 0 2006.201.23:45:51.28#ibcon#enter sib2, iclass 17, count 0 2006.201.23:45:51.28#ibcon#flushed, iclass 17, count 0 2006.201.23:45:51.28#ibcon#about to write, iclass 17, count 0 2006.201.23:45:51.28#ibcon#wrote, iclass 17, count 0 2006.201.23:45:51.28#ibcon#about to read 3, iclass 17, count 0 2006.201.23:45:51.32#ibcon#read 3, iclass 17, count 0 2006.201.23:45:51.32#ibcon#about to read 4, iclass 17, count 0 2006.201.23:45:51.32#ibcon#read 4, iclass 17, count 0 2006.201.23:45:51.32#ibcon#about to read 5, iclass 17, count 0 2006.201.23:45:51.32#ibcon#read 5, iclass 17, count 0 2006.201.23:45:51.32#ibcon#about to read 6, iclass 17, count 0 2006.201.23:45:51.32#ibcon#read 6, iclass 17, count 0 2006.201.23:45:51.32#ibcon#end of sib2, iclass 17, count 0 2006.201.23:45:51.32#ibcon#*after write, iclass 17, count 0 2006.201.23:45:51.32#ibcon#*before return 0, iclass 17, count 0 2006.201.23:45:51.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.201.23:45:51.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.201.23:45:51.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.201.23:45:51.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.201.23:45:51.32$vck44/vb=1,4 2006.201.23:45:51.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.201.23:45:51.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.201.23:45:51.32#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:51.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.23:45:51.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.201.23:45:51.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.23:45:51.32#ibcon#enter wrdev, iclass 19, count 2 2006.201.23:45:51.32#ibcon#first serial, iclass 19, count 2 2006.201.23:45:51.32#ibcon#enter sib2, iclass 19, count 2 2006.201.23:45:51.32#ibcon#flushed, iclass 19, count 2 2006.201.23:45:51.32#ibcon#about to write, iclass 19, count 2 2006.201.23:45:51.32#ibcon#wrote, iclass 19, count 2 2006.201.23:45:51.32#ibcon#about to read 3, iclass 19, count 2 2006.201.23:45:51.34#ibcon#read 3, iclass 19, count 2 2006.201.23:45:51.34#ibcon#about to read 4, iclass 19, count 2 2006.201.23:45:51.34#ibcon#read 4, iclass 19, count 2 2006.201.23:45:51.34#ibcon#about to read 5, iclass 19, count 2 2006.201.23:45:51.34#ibcon#read 5, iclass 19, count 2 2006.201.23:45:51.34#ibcon#about to read 6, iclass 19, count 2 2006.201.23:45:51.34#ibcon#read 6, iclass 19, count 2 2006.201.23:45:51.34#ibcon#end of sib2, iclass 19, count 2 2006.201.23:45:51.34#ibcon#*mode == 0, iclass 19, count 2 2006.201.23:45:51.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.201.23:45:51.34#ibcon#[27=AT01-04\r\n] 2006.201.23:45:51.34#ibcon#*before write, iclass 19, count 2 2006.201.23:45:51.34#ibcon#enter sib2, iclass 19, count 2 2006.201.23:45:51.34#ibcon#flushed, iclass 19, count 2 2006.201.23:45:51.34#ibcon#about to write, iclass 19, count 2 2006.201.23:45:51.34#ibcon#wrote, iclass 19, count 2 2006.201.23:45:51.34#ibcon#about to read 3, iclass 19, count 2 2006.201.23:45:51.37#ibcon#read 3, iclass 19, count 2 2006.201.23:45:51.37#ibcon#about to read 4, iclass 19, count 2 2006.201.23:45:51.37#ibcon#read 4, iclass 19, count 2 2006.201.23:45:51.37#ibcon#about to read 5, iclass 19, count 2 2006.201.23:45:51.37#ibcon#read 5, iclass 19, count 2 2006.201.23:45:51.37#ibcon#about to read 6, iclass 19, count 2 2006.201.23:45:51.37#ibcon#read 6, iclass 19, count 2 2006.201.23:45:51.37#ibcon#end of sib2, iclass 19, count 2 2006.201.23:45:51.37#ibcon#*after write, iclass 19, count 2 2006.201.23:45:51.37#ibcon#*before return 0, iclass 19, count 2 2006.201.23:45:51.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.201.23:45:51.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.201.23:45:51.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.201.23:45:51.37#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:51.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.23:45:51.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.201.23:45:51.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.23:45:51.49#ibcon#enter wrdev, iclass 19, count 0 2006.201.23:45:51.49#ibcon#first serial, iclass 19, count 0 2006.201.23:45:51.49#ibcon#enter sib2, iclass 19, count 0 2006.201.23:45:51.49#ibcon#flushed, iclass 19, count 0 2006.201.23:45:51.49#ibcon#about to write, iclass 19, count 0 2006.201.23:45:51.49#ibcon#wrote, iclass 19, count 0 2006.201.23:45:51.49#ibcon#about to read 3, iclass 19, count 0 2006.201.23:45:51.51#ibcon#read 3, iclass 19, count 0 2006.201.23:45:51.51#ibcon#about to read 4, iclass 19, count 0 2006.201.23:45:51.51#ibcon#read 4, iclass 19, count 0 2006.201.23:45:51.51#ibcon#about to read 5, iclass 19, count 0 2006.201.23:45:51.51#ibcon#read 5, iclass 19, count 0 2006.201.23:45:51.51#ibcon#about to read 6, iclass 19, count 0 2006.201.23:45:51.51#ibcon#read 6, iclass 19, count 0 2006.201.23:45:51.51#ibcon#end of sib2, iclass 19, count 0 2006.201.23:45:51.51#ibcon#*mode == 0, iclass 19, count 0 2006.201.23:45:51.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.201.23:45:51.51#ibcon#[27=USB\r\n] 2006.201.23:45:51.51#ibcon#*before write, iclass 19, count 0 2006.201.23:45:51.51#ibcon#enter sib2, iclass 19, count 0 2006.201.23:45:51.51#ibcon#flushed, iclass 19, count 0 2006.201.23:45:51.51#ibcon#about to write, iclass 19, count 0 2006.201.23:45:51.51#ibcon#wrote, iclass 19, count 0 2006.201.23:45:51.51#ibcon#about to read 3, iclass 19, count 0 2006.201.23:45:51.54#ibcon#read 3, iclass 19, count 0 2006.201.23:45:51.54#ibcon#about to read 4, iclass 19, count 0 2006.201.23:45:51.54#ibcon#read 4, iclass 19, count 0 2006.201.23:45:51.54#ibcon#about to read 5, iclass 19, count 0 2006.201.23:45:51.54#ibcon#read 5, iclass 19, count 0 2006.201.23:45:51.54#ibcon#about to read 6, iclass 19, count 0 2006.201.23:45:51.54#ibcon#read 6, iclass 19, count 0 2006.201.23:45:51.54#ibcon#end of sib2, iclass 19, count 0 2006.201.23:45:51.54#ibcon#*after write, iclass 19, count 0 2006.201.23:45:51.54#ibcon#*before return 0, iclass 19, count 0 2006.201.23:45:51.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.201.23:45:51.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.201.23:45:51.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.201.23:45:51.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.201.23:45:51.54$vck44/vblo=2,634.99 2006.201.23:45:51.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.201.23:45:51.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.201.23:45:51.54#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:51.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:51.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:51.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:51.54#ibcon#enter wrdev, iclass 21, count 0 2006.201.23:45:51.54#ibcon#first serial, iclass 21, count 0 2006.201.23:45:51.54#ibcon#enter sib2, iclass 21, count 0 2006.201.23:45:51.54#ibcon#flushed, iclass 21, count 0 2006.201.23:45:51.54#ibcon#about to write, iclass 21, count 0 2006.201.23:45:51.54#ibcon#wrote, iclass 21, count 0 2006.201.23:45:51.54#ibcon#about to read 3, iclass 21, count 0 2006.201.23:45:51.56#ibcon#read 3, iclass 21, count 0 2006.201.23:45:51.56#ibcon#about to read 4, iclass 21, count 0 2006.201.23:45:51.56#ibcon#read 4, iclass 21, count 0 2006.201.23:45:51.56#ibcon#about to read 5, iclass 21, count 0 2006.201.23:45:51.56#ibcon#read 5, iclass 21, count 0 2006.201.23:45:51.56#ibcon#about to read 6, iclass 21, count 0 2006.201.23:45:51.56#ibcon#read 6, iclass 21, count 0 2006.201.23:45:51.56#ibcon#end of sib2, iclass 21, count 0 2006.201.23:45:51.56#ibcon#*mode == 0, iclass 21, count 0 2006.201.23:45:51.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.201.23:45:51.56#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.23:45:51.56#ibcon#*before write, iclass 21, count 0 2006.201.23:45:51.56#ibcon#enter sib2, iclass 21, count 0 2006.201.23:45:51.56#ibcon#flushed, iclass 21, count 0 2006.201.23:45:51.56#ibcon#about to write, iclass 21, count 0 2006.201.23:45:51.56#ibcon#wrote, iclass 21, count 0 2006.201.23:45:51.56#ibcon#about to read 3, iclass 21, count 0 2006.201.23:45:51.60#ibcon#read 3, iclass 21, count 0 2006.201.23:45:51.60#ibcon#about to read 4, iclass 21, count 0 2006.201.23:45:51.60#ibcon#read 4, iclass 21, count 0 2006.201.23:45:51.60#ibcon#about to read 5, iclass 21, count 0 2006.201.23:45:51.60#ibcon#read 5, iclass 21, count 0 2006.201.23:45:51.60#ibcon#about to read 6, iclass 21, count 0 2006.201.23:45:51.60#ibcon#read 6, iclass 21, count 0 2006.201.23:45:51.60#ibcon#end of sib2, iclass 21, count 0 2006.201.23:45:51.60#ibcon#*after write, iclass 21, count 0 2006.201.23:45:51.60#ibcon#*before return 0, iclass 21, count 0 2006.201.23:45:51.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:51.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.201.23:45:51.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.201.23:45:51.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.201.23:45:51.60$vck44/vb=2,5 2006.201.23:45:51.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.201.23:45:51.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.201.23:45:51.60#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:51.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:51.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:51.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:51.66#ibcon#enter wrdev, iclass 23, count 2 2006.201.23:45:51.66#ibcon#first serial, iclass 23, count 2 2006.201.23:45:51.66#ibcon#enter sib2, iclass 23, count 2 2006.201.23:45:51.66#ibcon#flushed, iclass 23, count 2 2006.201.23:45:51.66#ibcon#about to write, iclass 23, count 2 2006.201.23:45:51.66#ibcon#wrote, iclass 23, count 2 2006.201.23:45:51.66#ibcon#about to read 3, iclass 23, count 2 2006.201.23:45:51.68#ibcon#read 3, iclass 23, count 2 2006.201.23:45:51.68#ibcon#about to read 4, iclass 23, count 2 2006.201.23:45:51.68#ibcon#read 4, iclass 23, count 2 2006.201.23:45:51.68#ibcon#about to read 5, iclass 23, count 2 2006.201.23:45:51.68#ibcon#read 5, iclass 23, count 2 2006.201.23:45:51.68#ibcon#about to read 6, iclass 23, count 2 2006.201.23:45:51.68#ibcon#read 6, iclass 23, count 2 2006.201.23:45:51.68#ibcon#end of sib2, iclass 23, count 2 2006.201.23:45:51.68#ibcon#*mode == 0, iclass 23, count 2 2006.201.23:45:51.68#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.201.23:45:51.68#ibcon#[27=AT02-05\r\n] 2006.201.23:45:51.68#ibcon#*before write, iclass 23, count 2 2006.201.23:45:51.68#ibcon#enter sib2, iclass 23, count 2 2006.201.23:45:51.68#ibcon#flushed, iclass 23, count 2 2006.201.23:45:51.68#ibcon#about to write, iclass 23, count 2 2006.201.23:45:51.68#ibcon#wrote, iclass 23, count 2 2006.201.23:45:51.68#ibcon#about to read 3, iclass 23, count 2 2006.201.23:45:51.71#ibcon#read 3, iclass 23, count 2 2006.201.23:45:51.71#ibcon#about to read 4, iclass 23, count 2 2006.201.23:45:51.71#ibcon#read 4, iclass 23, count 2 2006.201.23:45:51.71#ibcon#about to read 5, iclass 23, count 2 2006.201.23:45:51.71#ibcon#read 5, iclass 23, count 2 2006.201.23:45:51.71#ibcon#about to read 6, iclass 23, count 2 2006.201.23:45:51.71#ibcon#read 6, iclass 23, count 2 2006.201.23:45:51.71#ibcon#end of sib2, iclass 23, count 2 2006.201.23:45:51.71#ibcon#*after write, iclass 23, count 2 2006.201.23:45:51.71#ibcon#*before return 0, iclass 23, count 2 2006.201.23:45:51.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:51.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.201.23:45:51.71#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.201.23:45:51.71#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:51.71#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:51.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:51.83#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:51.83#ibcon#enter wrdev, iclass 23, count 0 2006.201.23:45:51.83#ibcon#first serial, iclass 23, count 0 2006.201.23:45:51.83#ibcon#enter sib2, iclass 23, count 0 2006.201.23:45:51.83#ibcon#flushed, iclass 23, count 0 2006.201.23:45:51.83#ibcon#about to write, iclass 23, count 0 2006.201.23:45:51.83#ibcon#wrote, iclass 23, count 0 2006.201.23:45:51.83#ibcon#about to read 3, iclass 23, count 0 2006.201.23:45:51.85#ibcon#read 3, iclass 23, count 0 2006.201.23:45:51.85#ibcon#about to read 4, iclass 23, count 0 2006.201.23:45:51.85#ibcon#read 4, iclass 23, count 0 2006.201.23:45:51.85#ibcon#about to read 5, iclass 23, count 0 2006.201.23:45:51.85#ibcon#read 5, iclass 23, count 0 2006.201.23:45:51.85#ibcon#about to read 6, iclass 23, count 0 2006.201.23:45:51.85#ibcon#read 6, iclass 23, count 0 2006.201.23:45:51.85#ibcon#end of sib2, iclass 23, count 0 2006.201.23:45:51.85#ibcon#*mode == 0, iclass 23, count 0 2006.201.23:45:51.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.201.23:45:51.85#ibcon#[27=USB\r\n] 2006.201.23:45:51.85#ibcon#*before write, iclass 23, count 0 2006.201.23:45:51.85#ibcon#enter sib2, iclass 23, count 0 2006.201.23:45:51.85#ibcon#flushed, iclass 23, count 0 2006.201.23:45:51.85#ibcon#about to write, iclass 23, count 0 2006.201.23:45:51.85#ibcon#wrote, iclass 23, count 0 2006.201.23:45:51.85#ibcon#about to read 3, iclass 23, count 0 2006.201.23:45:51.88#ibcon#read 3, iclass 23, count 0 2006.201.23:45:51.88#ibcon#about to read 4, iclass 23, count 0 2006.201.23:45:51.88#ibcon#read 4, iclass 23, count 0 2006.201.23:45:51.88#ibcon#about to read 5, iclass 23, count 0 2006.201.23:45:51.88#ibcon#read 5, iclass 23, count 0 2006.201.23:45:51.88#ibcon#about to read 6, iclass 23, count 0 2006.201.23:45:51.88#ibcon#read 6, iclass 23, count 0 2006.201.23:45:51.88#ibcon#end of sib2, iclass 23, count 0 2006.201.23:45:51.88#ibcon#*after write, iclass 23, count 0 2006.201.23:45:51.88#ibcon#*before return 0, iclass 23, count 0 2006.201.23:45:51.88#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:51.88#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.201.23:45:51.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.201.23:45:51.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.201.23:45:51.88$vck44/vblo=3,649.99 2006.201.23:45:51.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.201.23:45:51.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.201.23:45:51.88#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:51.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:51.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:51.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:51.88#ibcon#enter wrdev, iclass 25, count 0 2006.201.23:45:51.88#ibcon#first serial, iclass 25, count 0 2006.201.23:45:51.88#ibcon#enter sib2, iclass 25, count 0 2006.201.23:45:51.88#ibcon#flushed, iclass 25, count 0 2006.201.23:45:51.88#ibcon#about to write, iclass 25, count 0 2006.201.23:45:51.88#ibcon#wrote, iclass 25, count 0 2006.201.23:45:51.88#ibcon#about to read 3, iclass 25, count 0 2006.201.23:45:51.90#ibcon#read 3, iclass 25, count 0 2006.201.23:45:51.90#ibcon#about to read 4, iclass 25, count 0 2006.201.23:45:51.90#ibcon#read 4, iclass 25, count 0 2006.201.23:45:51.90#ibcon#about to read 5, iclass 25, count 0 2006.201.23:45:51.90#ibcon#read 5, iclass 25, count 0 2006.201.23:45:51.90#ibcon#about to read 6, iclass 25, count 0 2006.201.23:45:51.90#ibcon#read 6, iclass 25, count 0 2006.201.23:45:51.90#ibcon#end of sib2, iclass 25, count 0 2006.201.23:45:51.90#ibcon#*mode == 0, iclass 25, count 0 2006.201.23:45:51.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.201.23:45:51.90#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.23:45:51.90#ibcon#*before write, iclass 25, count 0 2006.201.23:45:51.90#ibcon#enter sib2, iclass 25, count 0 2006.201.23:45:51.90#ibcon#flushed, iclass 25, count 0 2006.201.23:45:51.90#ibcon#about to write, iclass 25, count 0 2006.201.23:45:51.90#ibcon#wrote, iclass 25, count 0 2006.201.23:45:51.90#ibcon#about to read 3, iclass 25, count 0 2006.201.23:45:51.94#ibcon#read 3, iclass 25, count 0 2006.201.23:45:51.94#ibcon#about to read 4, iclass 25, count 0 2006.201.23:45:51.94#ibcon#read 4, iclass 25, count 0 2006.201.23:45:51.94#ibcon#about to read 5, iclass 25, count 0 2006.201.23:45:51.94#ibcon#read 5, iclass 25, count 0 2006.201.23:45:51.94#ibcon#about to read 6, iclass 25, count 0 2006.201.23:45:51.94#ibcon#read 6, iclass 25, count 0 2006.201.23:45:51.94#ibcon#end of sib2, iclass 25, count 0 2006.201.23:45:51.94#ibcon#*after write, iclass 25, count 0 2006.201.23:45:51.94#ibcon#*before return 0, iclass 25, count 0 2006.201.23:45:51.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:51.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.201.23:45:51.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.201.23:45:51.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.201.23:45:51.94$vck44/vb=3,4 2006.201.23:45:51.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.201.23:45:51.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.201.23:45:51.94#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:51.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:52.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:52.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:52.00#ibcon#enter wrdev, iclass 27, count 2 2006.201.23:45:52.00#ibcon#first serial, iclass 27, count 2 2006.201.23:45:52.00#ibcon#enter sib2, iclass 27, count 2 2006.201.23:45:52.00#ibcon#flushed, iclass 27, count 2 2006.201.23:45:52.00#ibcon#about to write, iclass 27, count 2 2006.201.23:45:52.00#ibcon#wrote, iclass 27, count 2 2006.201.23:45:52.00#ibcon#about to read 3, iclass 27, count 2 2006.201.23:45:52.02#ibcon#read 3, iclass 27, count 2 2006.201.23:45:52.02#ibcon#about to read 4, iclass 27, count 2 2006.201.23:45:52.02#ibcon#read 4, iclass 27, count 2 2006.201.23:45:52.02#ibcon#about to read 5, iclass 27, count 2 2006.201.23:45:52.02#ibcon#read 5, iclass 27, count 2 2006.201.23:45:52.02#ibcon#about to read 6, iclass 27, count 2 2006.201.23:45:52.02#ibcon#read 6, iclass 27, count 2 2006.201.23:45:52.02#ibcon#end of sib2, iclass 27, count 2 2006.201.23:45:52.02#ibcon#*mode == 0, iclass 27, count 2 2006.201.23:45:52.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.201.23:45:52.02#ibcon#[27=AT03-04\r\n] 2006.201.23:45:52.02#ibcon#*before write, iclass 27, count 2 2006.201.23:45:52.02#ibcon#enter sib2, iclass 27, count 2 2006.201.23:45:52.02#ibcon#flushed, iclass 27, count 2 2006.201.23:45:52.02#ibcon#about to write, iclass 27, count 2 2006.201.23:45:52.02#ibcon#wrote, iclass 27, count 2 2006.201.23:45:52.02#ibcon#about to read 3, iclass 27, count 2 2006.201.23:45:52.05#ibcon#read 3, iclass 27, count 2 2006.201.23:45:52.05#ibcon#about to read 4, iclass 27, count 2 2006.201.23:45:52.05#ibcon#read 4, iclass 27, count 2 2006.201.23:45:52.05#ibcon#about to read 5, iclass 27, count 2 2006.201.23:45:52.05#ibcon#read 5, iclass 27, count 2 2006.201.23:45:52.05#ibcon#about to read 6, iclass 27, count 2 2006.201.23:45:52.05#ibcon#read 6, iclass 27, count 2 2006.201.23:45:52.05#ibcon#end of sib2, iclass 27, count 2 2006.201.23:45:52.05#ibcon#*after write, iclass 27, count 2 2006.201.23:45:52.05#ibcon#*before return 0, iclass 27, count 2 2006.201.23:45:52.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:52.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.201.23:45:52.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.201.23:45:52.05#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:52.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:52.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:52.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:52.17#ibcon#enter wrdev, iclass 27, count 0 2006.201.23:45:52.17#ibcon#first serial, iclass 27, count 0 2006.201.23:45:52.17#ibcon#enter sib2, iclass 27, count 0 2006.201.23:45:52.17#ibcon#flushed, iclass 27, count 0 2006.201.23:45:52.17#ibcon#about to write, iclass 27, count 0 2006.201.23:45:52.17#ibcon#wrote, iclass 27, count 0 2006.201.23:45:52.17#ibcon#about to read 3, iclass 27, count 0 2006.201.23:45:52.19#ibcon#read 3, iclass 27, count 0 2006.201.23:45:52.19#ibcon#about to read 4, iclass 27, count 0 2006.201.23:45:52.19#ibcon#read 4, iclass 27, count 0 2006.201.23:45:52.19#ibcon#about to read 5, iclass 27, count 0 2006.201.23:45:52.19#ibcon#read 5, iclass 27, count 0 2006.201.23:45:52.19#ibcon#about to read 6, iclass 27, count 0 2006.201.23:45:52.19#ibcon#read 6, iclass 27, count 0 2006.201.23:45:52.19#ibcon#end of sib2, iclass 27, count 0 2006.201.23:45:52.19#ibcon#*mode == 0, iclass 27, count 0 2006.201.23:45:52.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.201.23:45:52.19#ibcon#[27=USB\r\n] 2006.201.23:45:52.19#ibcon#*before write, iclass 27, count 0 2006.201.23:45:52.19#ibcon#enter sib2, iclass 27, count 0 2006.201.23:45:52.19#ibcon#flushed, iclass 27, count 0 2006.201.23:45:52.19#ibcon#about to write, iclass 27, count 0 2006.201.23:45:52.19#ibcon#wrote, iclass 27, count 0 2006.201.23:45:52.19#ibcon#about to read 3, iclass 27, count 0 2006.201.23:45:52.22#ibcon#read 3, iclass 27, count 0 2006.201.23:45:52.22#ibcon#about to read 4, iclass 27, count 0 2006.201.23:45:52.22#ibcon#read 4, iclass 27, count 0 2006.201.23:45:52.22#ibcon#about to read 5, iclass 27, count 0 2006.201.23:45:52.22#ibcon#read 5, iclass 27, count 0 2006.201.23:45:52.22#ibcon#about to read 6, iclass 27, count 0 2006.201.23:45:52.22#ibcon#read 6, iclass 27, count 0 2006.201.23:45:52.22#ibcon#end of sib2, iclass 27, count 0 2006.201.23:45:52.22#ibcon#*after write, iclass 27, count 0 2006.201.23:45:52.22#ibcon#*before return 0, iclass 27, count 0 2006.201.23:45:52.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:52.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.201.23:45:52.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.201.23:45:52.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.201.23:45:52.22$vck44/vblo=4,679.99 2006.201.23:45:52.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.201.23:45:52.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.201.23:45:52.22#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:52.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:52.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:52.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:52.22#ibcon#enter wrdev, iclass 29, count 0 2006.201.23:45:52.22#ibcon#first serial, iclass 29, count 0 2006.201.23:45:52.22#ibcon#enter sib2, iclass 29, count 0 2006.201.23:45:52.22#ibcon#flushed, iclass 29, count 0 2006.201.23:45:52.22#ibcon#about to write, iclass 29, count 0 2006.201.23:45:52.22#ibcon#wrote, iclass 29, count 0 2006.201.23:45:52.22#ibcon#about to read 3, iclass 29, count 0 2006.201.23:45:52.24#ibcon#read 3, iclass 29, count 0 2006.201.23:45:52.24#ibcon#about to read 4, iclass 29, count 0 2006.201.23:45:52.24#ibcon#read 4, iclass 29, count 0 2006.201.23:45:52.24#ibcon#about to read 5, iclass 29, count 0 2006.201.23:45:52.24#ibcon#read 5, iclass 29, count 0 2006.201.23:45:52.24#ibcon#about to read 6, iclass 29, count 0 2006.201.23:45:52.24#ibcon#read 6, iclass 29, count 0 2006.201.23:45:52.24#ibcon#end of sib2, iclass 29, count 0 2006.201.23:45:52.24#ibcon#*mode == 0, iclass 29, count 0 2006.201.23:45:52.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.201.23:45:52.24#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.23:45:52.24#ibcon#*before write, iclass 29, count 0 2006.201.23:45:52.24#ibcon#enter sib2, iclass 29, count 0 2006.201.23:45:52.24#ibcon#flushed, iclass 29, count 0 2006.201.23:45:52.24#ibcon#about to write, iclass 29, count 0 2006.201.23:45:52.24#ibcon#wrote, iclass 29, count 0 2006.201.23:45:52.24#ibcon#about to read 3, iclass 29, count 0 2006.201.23:45:52.28#ibcon#read 3, iclass 29, count 0 2006.201.23:45:52.28#ibcon#about to read 4, iclass 29, count 0 2006.201.23:45:52.28#ibcon#read 4, iclass 29, count 0 2006.201.23:45:52.28#ibcon#about to read 5, iclass 29, count 0 2006.201.23:45:52.28#ibcon#read 5, iclass 29, count 0 2006.201.23:45:52.28#ibcon#about to read 6, iclass 29, count 0 2006.201.23:45:52.28#ibcon#read 6, iclass 29, count 0 2006.201.23:45:52.28#ibcon#end of sib2, iclass 29, count 0 2006.201.23:45:52.28#ibcon#*after write, iclass 29, count 0 2006.201.23:45:52.28#ibcon#*before return 0, iclass 29, count 0 2006.201.23:45:52.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:52.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.201.23:45:52.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.201.23:45:52.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.201.23:45:52.28$vck44/vb=4,5 2006.201.23:45:52.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.201.23:45:52.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.201.23:45:52.28#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:52.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:52.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:52.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:52.34#ibcon#enter wrdev, iclass 31, count 2 2006.201.23:45:52.34#ibcon#first serial, iclass 31, count 2 2006.201.23:45:52.34#ibcon#enter sib2, iclass 31, count 2 2006.201.23:45:52.34#ibcon#flushed, iclass 31, count 2 2006.201.23:45:52.34#ibcon#about to write, iclass 31, count 2 2006.201.23:45:52.34#ibcon#wrote, iclass 31, count 2 2006.201.23:45:52.34#ibcon#about to read 3, iclass 31, count 2 2006.201.23:45:52.36#ibcon#read 3, iclass 31, count 2 2006.201.23:45:52.36#ibcon#about to read 4, iclass 31, count 2 2006.201.23:45:52.36#ibcon#read 4, iclass 31, count 2 2006.201.23:45:52.36#ibcon#about to read 5, iclass 31, count 2 2006.201.23:45:52.36#ibcon#read 5, iclass 31, count 2 2006.201.23:45:52.36#ibcon#about to read 6, iclass 31, count 2 2006.201.23:45:52.36#ibcon#read 6, iclass 31, count 2 2006.201.23:45:52.36#ibcon#end of sib2, iclass 31, count 2 2006.201.23:45:52.36#ibcon#*mode == 0, iclass 31, count 2 2006.201.23:45:52.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.201.23:45:52.36#ibcon#[27=AT04-05\r\n] 2006.201.23:45:52.36#ibcon#*before write, iclass 31, count 2 2006.201.23:45:52.36#ibcon#enter sib2, iclass 31, count 2 2006.201.23:45:52.36#ibcon#flushed, iclass 31, count 2 2006.201.23:45:52.36#ibcon#about to write, iclass 31, count 2 2006.201.23:45:52.36#ibcon#wrote, iclass 31, count 2 2006.201.23:45:52.36#ibcon#about to read 3, iclass 31, count 2 2006.201.23:45:52.39#ibcon#read 3, iclass 31, count 2 2006.201.23:45:52.39#ibcon#about to read 4, iclass 31, count 2 2006.201.23:45:52.39#ibcon#read 4, iclass 31, count 2 2006.201.23:45:52.39#ibcon#about to read 5, iclass 31, count 2 2006.201.23:45:52.39#ibcon#read 5, iclass 31, count 2 2006.201.23:45:52.39#ibcon#about to read 6, iclass 31, count 2 2006.201.23:45:52.39#ibcon#read 6, iclass 31, count 2 2006.201.23:45:52.39#ibcon#end of sib2, iclass 31, count 2 2006.201.23:45:52.39#ibcon#*after write, iclass 31, count 2 2006.201.23:45:52.39#ibcon#*before return 0, iclass 31, count 2 2006.201.23:45:52.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:52.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.201.23:45:52.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.201.23:45:52.39#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:52.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:52.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:52.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:52.51#ibcon#enter wrdev, iclass 31, count 0 2006.201.23:45:52.51#ibcon#first serial, iclass 31, count 0 2006.201.23:45:52.51#ibcon#enter sib2, iclass 31, count 0 2006.201.23:45:52.51#ibcon#flushed, iclass 31, count 0 2006.201.23:45:52.51#ibcon#about to write, iclass 31, count 0 2006.201.23:45:52.51#ibcon#wrote, iclass 31, count 0 2006.201.23:45:52.51#ibcon#about to read 3, iclass 31, count 0 2006.201.23:45:52.53#ibcon#read 3, iclass 31, count 0 2006.201.23:45:52.53#ibcon#about to read 4, iclass 31, count 0 2006.201.23:45:52.53#ibcon#read 4, iclass 31, count 0 2006.201.23:45:52.53#ibcon#about to read 5, iclass 31, count 0 2006.201.23:45:52.53#ibcon#read 5, iclass 31, count 0 2006.201.23:45:52.53#ibcon#about to read 6, iclass 31, count 0 2006.201.23:45:52.53#ibcon#read 6, iclass 31, count 0 2006.201.23:45:52.53#ibcon#end of sib2, iclass 31, count 0 2006.201.23:45:52.53#ibcon#*mode == 0, iclass 31, count 0 2006.201.23:45:52.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.201.23:45:52.53#ibcon#[27=USB\r\n] 2006.201.23:45:52.53#ibcon#*before write, iclass 31, count 0 2006.201.23:45:52.53#ibcon#enter sib2, iclass 31, count 0 2006.201.23:45:52.53#ibcon#flushed, iclass 31, count 0 2006.201.23:45:52.53#ibcon#about to write, iclass 31, count 0 2006.201.23:45:52.53#ibcon#wrote, iclass 31, count 0 2006.201.23:45:52.53#ibcon#about to read 3, iclass 31, count 0 2006.201.23:45:52.56#ibcon#read 3, iclass 31, count 0 2006.201.23:45:52.56#ibcon#about to read 4, iclass 31, count 0 2006.201.23:45:52.56#ibcon#read 4, iclass 31, count 0 2006.201.23:45:52.56#ibcon#about to read 5, iclass 31, count 0 2006.201.23:45:52.56#ibcon#read 5, iclass 31, count 0 2006.201.23:45:52.56#ibcon#about to read 6, iclass 31, count 0 2006.201.23:45:52.56#ibcon#read 6, iclass 31, count 0 2006.201.23:45:52.56#ibcon#end of sib2, iclass 31, count 0 2006.201.23:45:52.56#ibcon#*after write, iclass 31, count 0 2006.201.23:45:52.56#ibcon#*before return 0, iclass 31, count 0 2006.201.23:45:52.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:52.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.201.23:45:52.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.201.23:45:52.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.201.23:45:52.56$vck44/vblo=5,709.99 2006.201.23:45:52.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.201.23:45:52.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.201.23:45:52.56#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:52.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:52.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:52.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:52.56#ibcon#enter wrdev, iclass 33, count 0 2006.201.23:45:52.56#ibcon#first serial, iclass 33, count 0 2006.201.23:45:52.56#ibcon#enter sib2, iclass 33, count 0 2006.201.23:45:52.56#ibcon#flushed, iclass 33, count 0 2006.201.23:45:52.56#ibcon#about to write, iclass 33, count 0 2006.201.23:45:52.56#ibcon#wrote, iclass 33, count 0 2006.201.23:45:52.56#ibcon#about to read 3, iclass 33, count 0 2006.201.23:45:52.58#ibcon#read 3, iclass 33, count 0 2006.201.23:45:52.58#ibcon#about to read 4, iclass 33, count 0 2006.201.23:45:52.58#ibcon#read 4, iclass 33, count 0 2006.201.23:45:52.58#ibcon#about to read 5, iclass 33, count 0 2006.201.23:45:52.58#ibcon#read 5, iclass 33, count 0 2006.201.23:45:52.58#ibcon#about to read 6, iclass 33, count 0 2006.201.23:45:52.58#ibcon#read 6, iclass 33, count 0 2006.201.23:45:52.58#ibcon#end of sib2, iclass 33, count 0 2006.201.23:45:52.58#ibcon#*mode == 0, iclass 33, count 0 2006.201.23:45:52.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.201.23:45:52.58#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.23:45:52.58#ibcon#*before write, iclass 33, count 0 2006.201.23:45:52.58#ibcon#enter sib2, iclass 33, count 0 2006.201.23:45:52.58#ibcon#flushed, iclass 33, count 0 2006.201.23:45:52.58#ibcon#about to write, iclass 33, count 0 2006.201.23:45:52.58#ibcon#wrote, iclass 33, count 0 2006.201.23:45:52.58#ibcon#about to read 3, iclass 33, count 0 2006.201.23:45:52.62#ibcon#read 3, iclass 33, count 0 2006.201.23:45:52.62#ibcon#about to read 4, iclass 33, count 0 2006.201.23:45:52.62#ibcon#read 4, iclass 33, count 0 2006.201.23:45:52.62#ibcon#about to read 5, iclass 33, count 0 2006.201.23:45:52.62#ibcon#read 5, iclass 33, count 0 2006.201.23:45:52.62#ibcon#about to read 6, iclass 33, count 0 2006.201.23:45:52.62#ibcon#read 6, iclass 33, count 0 2006.201.23:45:52.62#ibcon#end of sib2, iclass 33, count 0 2006.201.23:45:52.62#ibcon#*after write, iclass 33, count 0 2006.201.23:45:52.62#ibcon#*before return 0, iclass 33, count 0 2006.201.23:45:52.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:52.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.201.23:45:52.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.201.23:45:52.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.201.23:45:52.62$vck44/vb=5,4 2006.201.23:45:52.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.201.23:45:52.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.201.23:45:52.62#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:52.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:52.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:52.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:52.68#ibcon#enter wrdev, iclass 35, count 2 2006.201.23:45:52.68#ibcon#first serial, iclass 35, count 2 2006.201.23:45:52.68#ibcon#enter sib2, iclass 35, count 2 2006.201.23:45:52.68#ibcon#flushed, iclass 35, count 2 2006.201.23:45:52.68#ibcon#about to write, iclass 35, count 2 2006.201.23:45:52.68#ibcon#wrote, iclass 35, count 2 2006.201.23:45:52.68#ibcon#about to read 3, iclass 35, count 2 2006.201.23:45:52.70#ibcon#read 3, iclass 35, count 2 2006.201.23:45:52.70#ibcon#about to read 4, iclass 35, count 2 2006.201.23:45:52.70#ibcon#read 4, iclass 35, count 2 2006.201.23:45:52.70#ibcon#about to read 5, iclass 35, count 2 2006.201.23:45:52.70#ibcon#read 5, iclass 35, count 2 2006.201.23:45:52.70#ibcon#about to read 6, iclass 35, count 2 2006.201.23:45:52.70#ibcon#read 6, iclass 35, count 2 2006.201.23:45:52.70#ibcon#end of sib2, iclass 35, count 2 2006.201.23:45:52.70#ibcon#*mode == 0, iclass 35, count 2 2006.201.23:45:52.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.201.23:45:52.70#ibcon#[27=AT05-04\r\n] 2006.201.23:45:52.70#ibcon#*before write, iclass 35, count 2 2006.201.23:45:52.70#ibcon#enter sib2, iclass 35, count 2 2006.201.23:45:52.70#ibcon#flushed, iclass 35, count 2 2006.201.23:45:52.70#ibcon#about to write, iclass 35, count 2 2006.201.23:45:52.70#ibcon#wrote, iclass 35, count 2 2006.201.23:45:52.70#ibcon#about to read 3, iclass 35, count 2 2006.201.23:45:52.73#ibcon#read 3, iclass 35, count 2 2006.201.23:45:52.73#ibcon#about to read 4, iclass 35, count 2 2006.201.23:45:52.73#ibcon#read 4, iclass 35, count 2 2006.201.23:45:52.73#ibcon#about to read 5, iclass 35, count 2 2006.201.23:45:52.73#ibcon#read 5, iclass 35, count 2 2006.201.23:45:52.73#ibcon#about to read 6, iclass 35, count 2 2006.201.23:45:52.73#ibcon#read 6, iclass 35, count 2 2006.201.23:45:52.73#ibcon#end of sib2, iclass 35, count 2 2006.201.23:45:52.73#ibcon#*after write, iclass 35, count 2 2006.201.23:45:52.73#ibcon#*before return 0, iclass 35, count 2 2006.201.23:45:52.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:52.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.201.23:45:52.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.201.23:45:52.73#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:52.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:52.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:52.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:52.85#ibcon#enter wrdev, iclass 35, count 0 2006.201.23:45:52.85#ibcon#first serial, iclass 35, count 0 2006.201.23:45:52.85#ibcon#enter sib2, iclass 35, count 0 2006.201.23:45:52.85#ibcon#flushed, iclass 35, count 0 2006.201.23:45:52.85#ibcon#about to write, iclass 35, count 0 2006.201.23:45:52.85#ibcon#wrote, iclass 35, count 0 2006.201.23:45:52.85#ibcon#about to read 3, iclass 35, count 0 2006.201.23:45:52.87#ibcon#read 3, iclass 35, count 0 2006.201.23:45:52.87#ibcon#about to read 4, iclass 35, count 0 2006.201.23:45:52.87#ibcon#read 4, iclass 35, count 0 2006.201.23:45:52.87#ibcon#about to read 5, iclass 35, count 0 2006.201.23:45:52.87#ibcon#read 5, iclass 35, count 0 2006.201.23:45:52.87#ibcon#about to read 6, iclass 35, count 0 2006.201.23:45:52.87#ibcon#read 6, iclass 35, count 0 2006.201.23:45:52.87#ibcon#end of sib2, iclass 35, count 0 2006.201.23:45:52.87#ibcon#*mode == 0, iclass 35, count 0 2006.201.23:45:52.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.201.23:45:52.87#ibcon#[27=USB\r\n] 2006.201.23:45:52.87#ibcon#*before write, iclass 35, count 0 2006.201.23:45:52.87#ibcon#enter sib2, iclass 35, count 0 2006.201.23:45:52.87#ibcon#flushed, iclass 35, count 0 2006.201.23:45:52.87#ibcon#about to write, iclass 35, count 0 2006.201.23:45:52.87#ibcon#wrote, iclass 35, count 0 2006.201.23:45:52.87#ibcon#about to read 3, iclass 35, count 0 2006.201.23:45:52.90#ibcon#read 3, iclass 35, count 0 2006.201.23:45:52.90#ibcon#about to read 4, iclass 35, count 0 2006.201.23:45:52.90#ibcon#read 4, iclass 35, count 0 2006.201.23:45:52.90#ibcon#about to read 5, iclass 35, count 0 2006.201.23:45:52.90#ibcon#read 5, iclass 35, count 0 2006.201.23:45:52.90#ibcon#about to read 6, iclass 35, count 0 2006.201.23:45:52.90#ibcon#read 6, iclass 35, count 0 2006.201.23:45:52.90#ibcon#end of sib2, iclass 35, count 0 2006.201.23:45:52.90#ibcon#*after write, iclass 35, count 0 2006.201.23:45:52.90#ibcon#*before return 0, iclass 35, count 0 2006.201.23:45:52.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:52.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.201.23:45:52.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.201.23:45:52.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.201.23:45:52.90$vck44/vblo=6,719.99 2006.201.23:45:52.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.201.23:45:52.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.201.23:45:52.90#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:52.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:52.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:52.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:52.90#ibcon#enter wrdev, iclass 37, count 0 2006.201.23:45:52.90#ibcon#first serial, iclass 37, count 0 2006.201.23:45:52.90#ibcon#enter sib2, iclass 37, count 0 2006.201.23:45:52.90#ibcon#flushed, iclass 37, count 0 2006.201.23:45:52.90#ibcon#about to write, iclass 37, count 0 2006.201.23:45:52.90#ibcon#wrote, iclass 37, count 0 2006.201.23:45:52.90#ibcon#about to read 3, iclass 37, count 0 2006.201.23:45:52.92#ibcon#read 3, iclass 37, count 0 2006.201.23:45:52.92#ibcon#about to read 4, iclass 37, count 0 2006.201.23:45:52.92#ibcon#read 4, iclass 37, count 0 2006.201.23:45:52.92#ibcon#about to read 5, iclass 37, count 0 2006.201.23:45:52.92#ibcon#read 5, iclass 37, count 0 2006.201.23:45:52.92#ibcon#about to read 6, iclass 37, count 0 2006.201.23:45:52.92#ibcon#read 6, iclass 37, count 0 2006.201.23:45:52.92#ibcon#end of sib2, iclass 37, count 0 2006.201.23:45:52.92#ibcon#*mode == 0, iclass 37, count 0 2006.201.23:45:52.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.201.23:45:52.92#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.23:45:52.92#ibcon#*before write, iclass 37, count 0 2006.201.23:45:52.92#ibcon#enter sib2, iclass 37, count 0 2006.201.23:45:52.92#ibcon#flushed, iclass 37, count 0 2006.201.23:45:52.92#ibcon#about to write, iclass 37, count 0 2006.201.23:45:52.92#ibcon#wrote, iclass 37, count 0 2006.201.23:45:52.92#ibcon#about to read 3, iclass 37, count 0 2006.201.23:45:52.96#ibcon#read 3, iclass 37, count 0 2006.201.23:45:52.96#ibcon#about to read 4, iclass 37, count 0 2006.201.23:45:52.96#ibcon#read 4, iclass 37, count 0 2006.201.23:45:52.96#ibcon#about to read 5, iclass 37, count 0 2006.201.23:45:52.96#ibcon#read 5, iclass 37, count 0 2006.201.23:45:52.96#ibcon#about to read 6, iclass 37, count 0 2006.201.23:45:52.96#ibcon#read 6, iclass 37, count 0 2006.201.23:45:52.96#ibcon#end of sib2, iclass 37, count 0 2006.201.23:45:52.96#ibcon#*after write, iclass 37, count 0 2006.201.23:45:52.96#ibcon#*before return 0, iclass 37, count 0 2006.201.23:45:52.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:52.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.201.23:45:52.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.201.23:45:52.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.201.23:45:52.96$vck44/vb=6,4 2006.201.23:45:52.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.201.23:45:52.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.201.23:45:52.96#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:52.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:53.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:53.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:53.02#ibcon#enter wrdev, iclass 39, count 2 2006.201.23:45:53.02#ibcon#first serial, iclass 39, count 2 2006.201.23:45:53.02#ibcon#enter sib2, iclass 39, count 2 2006.201.23:45:53.02#ibcon#flushed, iclass 39, count 2 2006.201.23:45:53.02#ibcon#about to write, iclass 39, count 2 2006.201.23:45:53.02#ibcon#wrote, iclass 39, count 2 2006.201.23:45:53.02#ibcon#about to read 3, iclass 39, count 2 2006.201.23:45:53.04#ibcon#read 3, iclass 39, count 2 2006.201.23:45:53.04#ibcon#about to read 4, iclass 39, count 2 2006.201.23:45:53.04#ibcon#read 4, iclass 39, count 2 2006.201.23:45:53.04#ibcon#about to read 5, iclass 39, count 2 2006.201.23:45:53.04#ibcon#read 5, iclass 39, count 2 2006.201.23:45:53.04#ibcon#about to read 6, iclass 39, count 2 2006.201.23:45:53.04#ibcon#read 6, iclass 39, count 2 2006.201.23:45:53.04#ibcon#end of sib2, iclass 39, count 2 2006.201.23:45:53.04#ibcon#*mode == 0, iclass 39, count 2 2006.201.23:45:53.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.201.23:45:53.04#ibcon#[27=AT06-04\r\n] 2006.201.23:45:53.04#ibcon#*before write, iclass 39, count 2 2006.201.23:45:53.04#ibcon#enter sib2, iclass 39, count 2 2006.201.23:45:53.04#ibcon#flushed, iclass 39, count 2 2006.201.23:45:53.04#ibcon#about to write, iclass 39, count 2 2006.201.23:45:53.04#ibcon#wrote, iclass 39, count 2 2006.201.23:45:53.04#ibcon#about to read 3, iclass 39, count 2 2006.201.23:45:53.07#ibcon#read 3, iclass 39, count 2 2006.201.23:45:53.07#ibcon#about to read 4, iclass 39, count 2 2006.201.23:45:53.07#ibcon#read 4, iclass 39, count 2 2006.201.23:45:53.07#ibcon#about to read 5, iclass 39, count 2 2006.201.23:45:53.07#ibcon#read 5, iclass 39, count 2 2006.201.23:45:53.07#ibcon#about to read 6, iclass 39, count 2 2006.201.23:45:53.07#ibcon#read 6, iclass 39, count 2 2006.201.23:45:53.07#ibcon#end of sib2, iclass 39, count 2 2006.201.23:45:53.07#ibcon#*after write, iclass 39, count 2 2006.201.23:45:53.07#ibcon#*before return 0, iclass 39, count 2 2006.201.23:45:53.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:53.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.201.23:45:53.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.201.23:45:53.07#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:53.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:53.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:53.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:53.19#ibcon#enter wrdev, iclass 39, count 0 2006.201.23:45:53.19#ibcon#first serial, iclass 39, count 0 2006.201.23:45:53.19#ibcon#enter sib2, iclass 39, count 0 2006.201.23:45:53.19#ibcon#flushed, iclass 39, count 0 2006.201.23:45:53.19#ibcon#about to write, iclass 39, count 0 2006.201.23:45:53.19#ibcon#wrote, iclass 39, count 0 2006.201.23:45:53.19#ibcon#about to read 3, iclass 39, count 0 2006.201.23:45:53.21#ibcon#read 3, iclass 39, count 0 2006.201.23:45:53.21#ibcon#about to read 4, iclass 39, count 0 2006.201.23:45:53.21#ibcon#read 4, iclass 39, count 0 2006.201.23:45:53.21#ibcon#about to read 5, iclass 39, count 0 2006.201.23:45:53.21#ibcon#read 5, iclass 39, count 0 2006.201.23:45:53.21#ibcon#about to read 6, iclass 39, count 0 2006.201.23:45:53.21#ibcon#read 6, iclass 39, count 0 2006.201.23:45:53.21#ibcon#end of sib2, iclass 39, count 0 2006.201.23:45:53.21#ibcon#*mode == 0, iclass 39, count 0 2006.201.23:45:53.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.201.23:45:53.21#ibcon#[27=USB\r\n] 2006.201.23:45:53.21#ibcon#*before write, iclass 39, count 0 2006.201.23:45:53.21#ibcon#enter sib2, iclass 39, count 0 2006.201.23:45:53.21#ibcon#flushed, iclass 39, count 0 2006.201.23:45:53.21#ibcon#about to write, iclass 39, count 0 2006.201.23:45:53.21#ibcon#wrote, iclass 39, count 0 2006.201.23:45:53.21#ibcon#about to read 3, iclass 39, count 0 2006.201.23:45:53.24#ibcon#read 3, iclass 39, count 0 2006.201.23:45:53.24#ibcon#about to read 4, iclass 39, count 0 2006.201.23:45:53.24#ibcon#read 4, iclass 39, count 0 2006.201.23:45:53.24#ibcon#about to read 5, iclass 39, count 0 2006.201.23:45:53.24#ibcon#read 5, iclass 39, count 0 2006.201.23:45:53.24#ibcon#about to read 6, iclass 39, count 0 2006.201.23:45:53.24#ibcon#read 6, iclass 39, count 0 2006.201.23:45:53.24#ibcon#end of sib2, iclass 39, count 0 2006.201.23:45:53.24#ibcon#*after write, iclass 39, count 0 2006.201.23:45:53.24#ibcon#*before return 0, iclass 39, count 0 2006.201.23:45:53.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:53.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.201.23:45:53.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.201.23:45:53.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.201.23:45:53.24$vck44/vblo=7,734.99 2006.201.23:45:53.24#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.201.23:45:53.24#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.201.23:45:53.24#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:53.24#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:53.24#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:53.24#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:53.24#ibcon#enter wrdev, iclass 2, count 0 2006.201.23:45:53.24#ibcon#first serial, iclass 2, count 0 2006.201.23:45:53.24#ibcon#enter sib2, iclass 2, count 0 2006.201.23:45:53.24#ibcon#flushed, iclass 2, count 0 2006.201.23:45:53.24#ibcon#about to write, iclass 2, count 0 2006.201.23:45:53.24#ibcon#wrote, iclass 2, count 0 2006.201.23:45:53.24#ibcon#about to read 3, iclass 2, count 0 2006.201.23:45:53.26#ibcon#read 3, iclass 2, count 0 2006.201.23:45:53.26#ibcon#about to read 4, iclass 2, count 0 2006.201.23:45:53.26#ibcon#read 4, iclass 2, count 0 2006.201.23:45:53.26#ibcon#about to read 5, iclass 2, count 0 2006.201.23:45:53.26#ibcon#read 5, iclass 2, count 0 2006.201.23:45:53.26#ibcon#about to read 6, iclass 2, count 0 2006.201.23:45:53.26#ibcon#read 6, iclass 2, count 0 2006.201.23:45:53.26#ibcon#end of sib2, iclass 2, count 0 2006.201.23:45:53.26#ibcon#*mode == 0, iclass 2, count 0 2006.201.23:45:53.26#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.201.23:45:53.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.23:45:53.26#ibcon#*before write, iclass 2, count 0 2006.201.23:45:53.26#ibcon#enter sib2, iclass 2, count 0 2006.201.23:45:53.26#ibcon#flushed, iclass 2, count 0 2006.201.23:45:53.26#ibcon#about to write, iclass 2, count 0 2006.201.23:45:53.26#ibcon#wrote, iclass 2, count 0 2006.201.23:45:53.26#ibcon#about to read 3, iclass 2, count 0 2006.201.23:45:53.30#ibcon#read 3, iclass 2, count 0 2006.201.23:45:53.30#ibcon#about to read 4, iclass 2, count 0 2006.201.23:45:53.30#ibcon#read 4, iclass 2, count 0 2006.201.23:45:53.30#ibcon#about to read 5, iclass 2, count 0 2006.201.23:45:53.30#ibcon#read 5, iclass 2, count 0 2006.201.23:45:53.30#ibcon#about to read 6, iclass 2, count 0 2006.201.23:45:53.30#ibcon#read 6, iclass 2, count 0 2006.201.23:45:53.30#ibcon#end of sib2, iclass 2, count 0 2006.201.23:45:53.30#ibcon#*after write, iclass 2, count 0 2006.201.23:45:53.30#ibcon#*before return 0, iclass 2, count 0 2006.201.23:45:53.30#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:53.30#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.201.23:45:53.30#ibcon#about to clear, iclass 2 cls_cnt 0 2006.201.23:45:53.30#ibcon#cleared, iclass 2 cls_cnt 0 2006.201.23:45:53.30$vck44/vb=7,4 2006.201.23:45:53.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.201.23:45:53.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.201.23:45:53.30#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:53.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:53.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:53.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:53.36#ibcon#enter wrdev, iclass 5, count 2 2006.201.23:45:53.36#ibcon#first serial, iclass 5, count 2 2006.201.23:45:53.36#ibcon#enter sib2, iclass 5, count 2 2006.201.23:45:53.36#ibcon#flushed, iclass 5, count 2 2006.201.23:45:53.36#ibcon#about to write, iclass 5, count 2 2006.201.23:45:53.36#ibcon#wrote, iclass 5, count 2 2006.201.23:45:53.36#ibcon#about to read 3, iclass 5, count 2 2006.201.23:45:53.38#ibcon#read 3, iclass 5, count 2 2006.201.23:45:53.38#ibcon#about to read 4, iclass 5, count 2 2006.201.23:45:53.38#ibcon#read 4, iclass 5, count 2 2006.201.23:45:53.38#ibcon#about to read 5, iclass 5, count 2 2006.201.23:45:53.38#ibcon#read 5, iclass 5, count 2 2006.201.23:45:53.38#ibcon#about to read 6, iclass 5, count 2 2006.201.23:45:53.38#ibcon#read 6, iclass 5, count 2 2006.201.23:45:53.38#ibcon#end of sib2, iclass 5, count 2 2006.201.23:45:53.38#ibcon#*mode == 0, iclass 5, count 2 2006.201.23:45:53.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.201.23:45:53.38#ibcon#[27=AT07-04\r\n] 2006.201.23:45:53.38#ibcon#*before write, iclass 5, count 2 2006.201.23:45:53.38#ibcon#enter sib2, iclass 5, count 2 2006.201.23:45:53.38#ibcon#flushed, iclass 5, count 2 2006.201.23:45:53.38#ibcon#about to write, iclass 5, count 2 2006.201.23:45:53.38#ibcon#wrote, iclass 5, count 2 2006.201.23:45:53.38#ibcon#about to read 3, iclass 5, count 2 2006.201.23:45:53.41#ibcon#read 3, iclass 5, count 2 2006.201.23:45:53.41#ibcon#about to read 4, iclass 5, count 2 2006.201.23:45:53.41#ibcon#read 4, iclass 5, count 2 2006.201.23:45:53.41#ibcon#about to read 5, iclass 5, count 2 2006.201.23:45:53.41#ibcon#read 5, iclass 5, count 2 2006.201.23:45:53.41#ibcon#about to read 6, iclass 5, count 2 2006.201.23:45:53.41#ibcon#read 6, iclass 5, count 2 2006.201.23:45:53.41#ibcon#end of sib2, iclass 5, count 2 2006.201.23:45:53.41#ibcon#*after write, iclass 5, count 2 2006.201.23:45:53.41#ibcon#*before return 0, iclass 5, count 2 2006.201.23:45:53.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:53.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.201.23:45:53.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.201.23:45:53.41#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:53.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:53.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:53.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:53.53#ibcon#enter wrdev, iclass 5, count 0 2006.201.23:45:53.53#ibcon#first serial, iclass 5, count 0 2006.201.23:45:53.53#ibcon#enter sib2, iclass 5, count 0 2006.201.23:45:53.53#ibcon#flushed, iclass 5, count 0 2006.201.23:45:53.53#ibcon#about to write, iclass 5, count 0 2006.201.23:45:53.53#ibcon#wrote, iclass 5, count 0 2006.201.23:45:53.53#ibcon#about to read 3, iclass 5, count 0 2006.201.23:45:53.55#ibcon#read 3, iclass 5, count 0 2006.201.23:45:53.55#ibcon#about to read 4, iclass 5, count 0 2006.201.23:45:53.55#ibcon#read 4, iclass 5, count 0 2006.201.23:45:53.55#ibcon#about to read 5, iclass 5, count 0 2006.201.23:45:53.55#ibcon#read 5, iclass 5, count 0 2006.201.23:45:53.55#ibcon#about to read 6, iclass 5, count 0 2006.201.23:45:53.55#ibcon#read 6, iclass 5, count 0 2006.201.23:45:53.55#ibcon#end of sib2, iclass 5, count 0 2006.201.23:45:53.55#ibcon#*mode == 0, iclass 5, count 0 2006.201.23:45:53.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.201.23:45:53.55#ibcon#[27=USB\r\n] 2006.201.23:45:53.55#ibcon#*before write, iclass 5, count 0 2006.201.23:45:53.55#ibcon#enter sib2, iclass 5, count 0 2006.201.23:45:53.55#ibcon#flushed, iclass 5, count 0 2006.201.23:45:53.55#ibcon#about to write, iclass 5, count 0 2006.201.23:45:53.55#ibcon#wrote, iclass 5, count 0 2006.201.23:45:53.55#ibcon#about to read 3, iclass 5, count 0 2006.201.23:45:53.58#ibcon#read 3, iclass 5, count 0 2006.201.23:45:53.58#ibcon#about to read 4, iclass 5, count 0 2006.201.23:45:53.58#ibcon#read 4, iclass 5, count 0 2006.201.23:45:53.58#ibcon#about to read 5, iclass 5, count 0 2006.201.23:45:53.58#ibcon#read 5, iclass 5, count 0 2006.201.23:45:53.58#ibcon#about to read 6, iclass 5, count 0 2006.201.23:45:53.58#ibcon#read 6, iclass 5, count 0 2006.201.23:45:53.58#ibcon#end of sib2, iclass 5, count 0 2006.201.23:45:53.58#ibcon#*after write, iclass 5, count 0 2006.201.23:45:53.58#ibcon#*before return 0, iclass 5, count 0 2006.201.23:45:53.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:53.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.201.23:45:53.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.201.23:45:53.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.201.23:45:53.58$vck44/vblo=8,744.99 2006.201.23:45:53.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.201.23:45:53.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.201.23:45:53.58#ibcon#ireg 17 cls_cnt 0 2006.201.23:45:53.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:53.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:53.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:53.58#ibcon#enter wrdev, iclass 7, count 0 2006.201.23:45:53.58#ibcon#first serial, iclass 7, count 0 2006.201.23:45:53.58#ibcon#enter sib2, iclass 7, count 0 2006.201.23:45:53.58#ibcon#flushed, iclass 7, count 0 2006.201.23:45:53.58#ibcon#about to write, iclass 7, count 0 2006.201.23:45:53.58#ibcon#wrote, iclass 7, count 0 2006.201.23:45:53.58#ibcon#about to read 3, iclass 7, count 0 2006.201.23:45:53.60#ibcon#read 3, iclass 7, count 0 2006.201.23:45:53.60#ibcon#about to read 4, iclass 7, count 0 2006.201.23:45:53.60#ibcon#read 4, iclass 7, count 0 2006.201.23:45:53.60#ibcon#about to read 5, iclass 7, count 0 2006.201.23:45:53.60#ibcon#read 5, iclass 7, count 0 2006.201.23:45:53.60#ibcon#about to read 6, iclass 7, count 0 2006.201.23:45:53.60#ibcon#read 6, iclass 7, count 0 2006.201.23:45:53.60#ibcon#end of sib2, iclass 7, count 0 2006.201.23:45:53.60#ibcon#*mode == 0, iclass 7, count 0 2006.201.23:45:53.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.201.23:45:53.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.23:45:53.60#ibcon#*before write, iclass 7, count 0 2006.201.23:45:53.60#ibcon#enter sib2, iclass 7, count 0 2006.201.23:45:53.60#ibcon#flushed, iclass 7, count 0 2006.201.23:45:53.60#ibcon#about to write, iclass 7, count 0 2006.201.23:45:53.60#ibcon#wrote, iclass 7, count 0 2006.201.23:45:53.60#ibcon#about to read 3, iclass 7, count 0 2006.201.23:45:53.64#ibcon#read 3, iclass 7, count 0 2006.201.23:45:53.64#ibcon#about to read 4, iclass 7, count 0 2006.201.23:45:53.64#ibcon#read 4, iclass 7, count 0 2006.201.23:45:53.64#ibcon#about to read 5, iclass 7, count 0 2006.201.23:45:53.64#ibcon#read 5, iclass 7, count 0 2006.201.23:45:53.64#ibcon#about to read 6, iclass 7, count 0 2006.201.23:45:53.64#ibcon#read 6, iclass 7, count 0 2006.201.23:45:53.64#ibcon#end of sib2, iclass 7, count 0 2006.201.23:45:53.64#ibcon#*after write, iclass 7, count 0 2006.201.23:45:53.64#ibcon#*before return 0, iclass 7, count 0 2006.201.23:45:53.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:53.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.201.23:45:53.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.201.23:45:53.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.201.23:45:53.64$vck44/vb=8,4 2006.201.23:45:53.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.201.23:45:53.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.201.23:45:53.64#ibcon#ireg 11 cls_cnt 2 2006.201.23:45:53.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:53.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:53.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:53.70#ibcon#enter wrdev, iclass 11, count 2 2006.201.23:45:53.70#ibcon#first serial, iclass 11, count 2 2006.201.23:45:53.70#ibcon#enter sib2, iclass 11, count 2 2006.201.23:45:53.70#ibcon#flushed, iclass 11, count 2 2006.201.23:45:53.70#ibcon#about to write, iclass 11, count 2 2006.201.23:45:53.70#ibcon#wrote, iclass 11, count 2 2006.201.23:45:53.70#ibcon#about to read 3, iclass 11, count 2 2006.201.23:45:53.72#ibcon#read 3, iclass 11, count 2 2006.201.23:45:53.72#ibcon#about to read 4, iclass 11, count 2 2006.201.23:45:53.72#ibcon#read 4, iclass 11, count 2 2006.201.23:45:53.72#ibcon#about to read 5, iclass 11, count 2 2006.201.23:45:53.72#ibcon#read 5, iclass 11, count 2 2006.201.23:45:53.72#ibcon#about to read 6, iclass 11, count 2 2006.201.23:45:53.72#ibcon#read 6, iclass 11, count 2 2006.201.23:45:53.72#ibcon#end of sib2, iclass 11, count 2 2006.201.23:45:53.72#ibcon#*mode == 0, iclass 11, count 2 2006.201.23:45:53.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.201.23:45:53.72#ibcon#[27=AT08-04\r\n] 2006.201.23:45:53.72#ibcon#*before write, iclass 11, count 2 2006.201.23:45:53.72#ibcon#enter sib2, iclass 11, count 2 2006.201.23:45:53.72#ibcon#flushed, iclass 11, count 2 2006.201.23:45:53.72#ibcon#about to write, iclass 11, count 2 2006.201.23:45:53.72#ibcon#wrote, iclass 11, count 2 2006.201.23:45:53.72#ibcon#about to read 3, iclass 11, count 2 2006.201.23:45:53.75#ibcon#read 3, iclass 11, count 2 2006.201.23:45:53.75#ibcon#about to read 4, iclass 11, count 2 2006.201.23:45:53.75#ibcon#read 4, iclass 11, count 2 2006.201.23:45:53.75#ibcon#about to read 5, iclass 11, count 2 2006.201.23:45:53.75#ibcon#read 5, iclass 11, count 2 2006.201.23:45:53.75#ibcon#about to read 6, iclass 11, count 2 2006.201.23:45:53.75#ibcon#read 6, iclass 11, count 2 2006.201.23:45:53.75#ibcon#end of sib2, iclass 11, count 2 2006.201.23:45:53.75#ibcon#*after write, iclass 11, count 2 2006.201.23:45:53.75#ibcon#*before return 0, iclass 11, count 2 2006.201.23:45:53.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:53.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.201.23:45:53.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.201.23:45:53.75#ibcon#ireg 7 cls_cnt 0 2006.201.23:45:53.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:53.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:53.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:53.87#ibcon#enter wrdev, iclass 11, count 0 2006.201.23:45:53.87#ibcon#first serial, iclass 11, count 0 2006.201.23:45:53.87#ibcon#enter sib2, iclass 11, count 0 2006.201.23:45:53.87#ibcon#flushed, iclass 11, count 0 2006.201.23:45:53.87#ibcon#about to write, iclass 11, count 0 2006.201.23:45:53.87#ibcon#wrote, iclass 11, count 0 2006.201.23:45:53.87#ibcon#about to read 3, iclass 11, count 0 2006.201.23:45:53.89#ibcon#read 3, iclass 11, count 0 2006.201.23:45:53.89#ibcon#about to read 4, iclass 11, count 0 2006.201.23:45:53.89#ibcon#read 4, iclass 11, count 0 2006.201.23:45:53.89#ibcon#about to read 5, iclass 11, count 0 2006.201.23:45:53.89#ibcon#read 5, iclass 11, count 0 2006.201.23:45:53.89#ibcon#about to read 6, iclass 11, count 0 2006.201.23:45:53.89#ibcon#read 6, iclass 11, count 0 2006.201.23:45:53.89#ibcon#end of sib2, iclass 11, count 0 2006.201.23:45:53.89#ibcon#*mode == 0, iclass 11, count 0 2006.201.23:45:53.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.201.23:45:53.89#ibcon#[27=USB\r\n] 2006.201.23:45:53.89#ibcon#*before write, iclass 11, count 0 2006.201.23:45:53.89#ibcon#enter sib2, iclass 11, count 0 2006.201.23:45:53.89#ibcon#flushed, iclass 11, count 0 2006.201.23:45:53.89#ibcon#about to write, iclass 11, count 0 2006.201.23:45:53.89#ibcon#wrote, iclass 11, count 0 2006.201.23:45:53.89#ibcon#about to read 3, iclass 11, count 0 2006.201.23:45:53.92#ibcon#read 3, iclass 11, count 0 2006.201.23:45:53.92#ibcon#about to read 4, iclass 11, count 0 2006.201.23:45:53.92#ibcon#read 4, iclass 11, count 0 2006.201.23:45:53.92#ibcon#about to read 5, iclass 11, count 0 2006.201.23:45:53.92#ibcon#read 5, iclass 11, count 0 2006.201.23:45:53.92#ibcon#about to read 6, iclass 11, count 0 2006.201.23:45:53.92#ibcon#read 6, iclass 11, count 0 2006.201.23:45:53.92#ibcon#end of sib2, iclass 11, count 0 2006.201.23:45:53.92#ibcon#*after write, iclass 11, count 0 2006.201.23:45:53.92#ibcon#*before return 0, iclass 11, count 0 2006.201.23:45:53.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:53.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.201.23:45:53.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.201.23:45:53.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.201.23:45:53.92$vck44/vabw=wide 2006.201.23:45:53.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.201.23:45:53.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.201.23:45:53.92#ibcon#ireg 8 cls_cnt 0 2006.201.23:45:53.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:53.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:53.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:53.92#ibcon#enter wrdev, iclass 13, count 0 2006.201.23:45:53.92#ibcon#first serial, iclass 13, count 0 2006.201.23:45:53.92#ibcon#enter sib2, iclass 13, count 0 2006.201.23:45:53.92#ibcon#flushed, iclass 13, count 0 2006.201.23:45:53.92#ibcon#about to write, iclass 13, count 0 2006.201.23:45:53.92#ibcon#wrote, iclass 13, count 0 2006.201.23:45:53.92#ibcon#about to read 3, iclass 13, count 0 2006.201.23:45:53.94#ibcon#read 3, iclass 13, count 0 2006.201.23:45:53.94#ibcon#about to read 4, iclass 13, count 0 2006.201.23:45:53.94#ibcon#read 4, iclass 13, count 0 2006.201.23:45:53.94#ibcon#about to read 5, iclass 13, count 0 2006.201.23:45:53.94#ibcon#read 5, iclass 13, count 0 2006.201.23:45:53.94#ibcon#about to read 6, iclass 13, count 0 2006.201.23:45:53.94#ibcon#read 6, iclass 13, count 0 2006.201.23:45:53.94#ibcon#end of sib2, iclass 13, count 0 2006.201.23:45:53.94#ibcon#*mode == 0, iclass 13, count 0 2006.201.23:45:53.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.201.23:45:53.94#ibcon#[25=BW32\r\n] 2006.201.23:45:53.94#ibcon#*before write, iclass 13, count 0 2006.201.23:45:53.94#ibcon#enter sib2, iclass 13, count 0 2006.201.23:45:53.94#ibcon#flushed, iclass 13, count 0 2006.201.23:45:53.94#ibcon#about to write, iclass 13, count 0 2006.201.23:45:53.94#ibcon#wrote, iclass 13, count 0 2006.201.23:45:53.94#ibcon#about to read 3, iclass 13, count 0 2006.201.23:45:53.97#ibcon#read 3, iclass 13, count 0 2006.201.23:45:53.97#ibcon#about to read 4, iclass 13, count 0 2006.201.23:45:53.97#ibcon#read 4, iclass 13, count 0 2006.201.23:45:53.97#ibcon#about to read 5, iclass 13, count 0 2006.201.23:45:53.97#ibcon#read 5, iclass 13, count 0 2006.201.23:45:53.97#ibcon#about to read 6, iclass 13, count 0 2006.201.23:45:53.97#ibcon#read 6, iclass 13, count 0 2006.201.23:45:53.97#ibcon#end of sib2, iclass 13, count 0 2006.201.23:45:53.97#ibcon#*after write, iclass 13, count 0 2006.201.23:45:53.97#ibcon#*before return 0, iclass 13, count 0 2006.201.23:45:53.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:53.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.201.23:45:53.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.201.23:45:53.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.201.23:45:53.97$vck44/vbbw=wide 2006.201.23:45:53.97#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.201.23:45:53.97#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.201.23:45:53.97#ibcon#ireg 8 cls_cnt 0 2006.201.23:45:53.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:45:54.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:45:54.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:45:54.04#ibcon#enter wrdev, iclass 15, count 0 2006.201.23:45:54.04#ibcon#first serial, iclass 15, count 0 2006.201.23:45:54.04#ibcon#enter sib2, iclass 15, count 0 2006.201.23:45:54.04#ibcon#flushed, iclass 15, count 0 2006.201.23:45:54.04#ibcon#about to write, iclass 15, count 0 2006.201.23:45:54.04#ibcon#wrote, iclass 15, count 0 2006.201.23:45:54.04#ibcon#about to read 3, iclass 15, count 0 2006.201.23:45:54.06#ibcon#read 3, iclass 15, count 0 2006.201.23:45:54.06#ibcon#about to read 4, iclass 15, count 0 2006.201.23:45:54.06#ibcon#read 4, iclass 15, count 0 2006.201.23:45:54.06#ibcon#about to read 5, iclass 15, count 0 2006.201.23:45:54.06#ibcon#read 5, iclass 15, count 0 2006.201.23:45:54.06#ibcon#about to read 6, iclass 15, count 0 2006.201.23:45:54.06#ibcon#read 6, iclass 15, count 0 2006.201.23:45:54.06#ibcon#end of sib2, iclass 15, count 0 2006.201.23:45:54.06#ibcon#*mode == 0, iclass 15, count 0 2006.201.23:45:54.06#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.201.23:45:54.06#ibcon#[27=BW32\r\n] 2006.201.23:45:54.06#ibcon#*before write, iclass 15, count 0 2006.201.23:45:54.06#ibcon#enter sib2, iclass 15, count 0 2006.201.23:45:54.06#ibcon#flushed, iclass 15, count 0 2006.201.23:45:54.06#ibcon#about to write, iclass 15, count 0 2006.201.23:45:54.06#ibcon#wrote, iclass 15, count 0 2006.201.23:45:54.06#ibcon#about to read 3, iclass 15, count 0 2006.201.23:45:54.09#ibcon#read 3, iclass 15, count 0 2006.201.23:45:54.09#ibcon#about to read 4, iclass 15, count 0 2006.201.23:45:54.09#ibcon#read 4, iclass 15, count 0 2006.201.23:45:54.09#ibcon#about to read 5, iclass 15, count 0 2006.201.23:45:54.09#ibcon#read 5, iclass 15, count 0 2006.201.23:45:54.09#ibcon#about to read 6, iclass 15, count 0 2006.201.23:45:54.09#ibcon#read 6, iclass 15, count 0 2006.201.23:45:54.09#ibcon#end of sib2, iclass 15, count 0 2006.201.23:45:54.09#ibcon#*after write, iclass 15, count 0 2006.201.23:45:54.09#ibcon#*before return 0, iclass 15, count 0 2006.201.23:45:54.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:45:54.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.201.23:45:54.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.201.23:45:54.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.201.23:45:54.09$setupk4/ifdk4 2006.201.23:45:54.09$ifdk4/lo= 2006.201.23:45:54.09$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.23:45:54.09$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.23:45:54.09$ifdk4/patch= 2006.201.23:45:54.09$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.23:45:54.09$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.23:45:54.09$setupk4/!*+20s 2006.201.23:45:58.20#abcon#<5=/02 0.7 2.1 20.331001001.6\r\n> 2006.201.23:45:58.22#abcon#{5=INTERFACE CLEAR} 2006.201.23:45:58.28#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:46:08.37#abcon#<5=/02 0.7 2.1 20.341001001.6\r\n> 2006.201.23:46:08.39#abcon#{5=INTERFACE CLEAR} 2006.201.23:46:08.45#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:46:08.59$setupk4/"tpicd 2006.201.23:46:08.59$setupk4/echo=off 2006.201.23:46:08.59$setupk4/xlog=off 2006.201.23:46:08.59:!2006.201.23:48:08 2006.201.23:46:15.14#trakl#Source acquired 2006.201.23:46:15.14#flagr#flagr/antenna,acquired 2006.201.23:48:08.00:preob 2006.201.23:48:08.14/onsource/TRACKING 2006.201.23:48:08.14:!2006.201.23:48:18 2006.201.23:48:18.00:"tape 2006.201.23:48:18.00:"st=record 2006.201.23:48:18.00:data_valid=on 2006.201.23:48:18.00:midob 2006.201.23:48:18.14/onsource/TRACKING 2006.201.23:48:18.14/wx/20.35,1001.4,100 2006.201.23:48:18.33/cable/+6.4835E-03 2006.201.23:48:19.42/va/01,08,usb,yes,54,57 2006.201.23:48:19.42/va/02,07,usb,yes,58,59 2006.201.23:48:19.42/va/03,08,usb,yes,53,55 2006.201.23:48:19.42/va/04,07,usb,yes,60,63 2006.201.23:48:19.42/va/05,04,usb,yes,53,55 2006.201.23:48:19.42/va/06,05,usb,yes,54,54 2006.201.23:48:19.42/va/07,05,usb,yes,53,54 2006.201.23:48:19.42/va/08,04,usb,yes,52,61 2006.201.23:48:19.65/valo/01,524.99,yes,locked 2006.201.23:48:19.65/valo/02,534.99,yes,locked 2006.201.23:48:19.65/valo/03,564.99,yes,locked 2006.201.23:48:19.65/valo/04,624.99,yes,locked 2006.201.23:48:19.65/valo/05,734.99,yes,locked 2006.201.23:48:19.65/valo/06,814.99,yes,locked 2006.201.23:48:19.65/valo/07,864.99,yes,locked 2006.201.23:48:19.65/valo/08,884.99,yes,locked 2006.201.23:48:20.74/vb/01,04,usb,yes,31,29 2006.201.23:48:20.74/vb/02,05,usb,yes,30,30 2006.201.23:48:20.74/vb/03,04,usb,yes,31,34 2006.201.23:48:20.74/vb/04,05,usb,yes,31,30 2006.201.23:48:20.74/vb/05,04,usb,yes,28,30 2006.201.23:48:20.74/vb/06,04,usb,yes,32,28 2006.201.23:48:20.74/vb/07,04,usb,yes,32,32 2006.201.23:48:20.74/vb/08,04,usb,yes,29,33 2006.201.23:48:20.98/vblo/01,629.99,yes,locked 2006.201.23:48:20.98/vblo/02,634.99,yes,locked 2006.201.23:48:20.98/vblo/03,649.99,yes,locked 2006.201.23:48:20.98/vblo/04,679.99,yes,locked 2006.201.23:48:20.98/vblo/05,709.99,yes,locked 2006.201.23:48:20.98/vblo/06,719.99,yes,locked 2006.201.23:48:20.98/vblo/07,734.99,yes,locked 2006.201.23:48:20.98/vblo/08,744.99,yes,locked 2006.201.23:48:21.13/vabw/8 2006.201.23:48:21.28/vbbw/8 2006.201.23:48:21.37/xfe/off,on,15.2 2006.201.23:48:21.75/ifatt/23,28,28,28 2006.201.23:48:22.07/fmout-gps/S +4.58E-07 2006.201.23:48:22.10:!2006.201.23:49:08 2006.201.23:49:08.00:data_valid=off 2006.201.23:49:08.00:"et 2006.201.23:49:08.00:!+3s 2006.201.23:49:11.01:"tape 2006.201.23:49:11.01:postob 2006.201.23:49:11.13/cable/+6.4831E-03 2006.201.23:49:11.13/wx/20.36,1001.4,100 2006.201.23:49:12.07/fmout-gps/S +4.56E-07 2006.201.23:49:12.07:scan_name=201-2351,jd0607,784 2006.201.23:49:12.07:source=1418+546,141946.60,542314.8,2000.0,cw 2006.201.23:49:13.13#flagr#flagr/antenna,new-source 2006.201.23:49:13.13:checkk5 2006.201.23:49:13.50/chk_autoobs//k5ts1/ autoobs is running! 2006.201.23:49:13.85/chk_autoobs//k5ts2/ autoobs is running! 2006.201.23:49:14.20/chk_autoobs//k5ts3/ autoobs is running! 2006.201.23:49:14.55/chk_autoobs//k5ts4/ autoobs is running! 2006.201.23:49:14.89/chk_obsdata//k5ts1/T2012348??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.23:49:15.23/chk_obsdata//k5ts2/T2012348??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.23:49:15.58/chk_obsdata//k5ts3/T2012348??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.23:49:15.92/chk_obsdata//k5ts4/T2012348??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.201.23:49:16.58/k5log//k5ts1_log_newline 2006.201.23:49:17.25/k5log//k5ts2_log_newline 2006.201.23:49:17.90/k5log//k5ts3_log_newline 2006.201.23:49:18.57/k5log//k5ts4_log_newline 2006.201.23:49:18.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.201.23:49:18.59:setupk4=1 2006.201.23:49:18.59$setupk4/echo=on 2006.201.23:49:18.59$setupk4/pcalon 2006.201.23:49:18.59$pcalon/"no phase cal control is implemented here 2006.201.23:49:18.59$setupk4/"tpicd=stop 2006.201.23:49:18.59$setupk4/"rec=synch_on 2006.201.23:49:18.59$setupk4/"rec_mode=128 2006.201.23:49:18.59$setupk4/!* 2006.201.23:49:18.59$setupk4/recpk4 2006.201.23:49:18.59$recpk4/recpatch= 2006.201.23:49:18.60$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.201.23:49:18.60$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.201.23:49:18.60$setupk4/vck44 2006.201.23:49:18.60$vck44/valo=1,524.99 2006.201.23:49:18.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.23:49:18.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.23:49:18.60#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:18.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:18.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:18.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:18.60#ibcon#enter wrdev, iclass 28, count 0 2006.201.23:49:18.60#ibcon#first serial, iclass 28, count 0 2006.201.23:49:18.60#ibcon#enter sib2, iclass 28, count 0 2006.201.23:49:18.60#ibcon#flushed, iclass 28, count 0 2006.201.23:49:18.60#ibcon#about to write, iclass 28, count 0 2006.201.23:49:18.60#ibcon#wrote, iclass 28, count 0 2006.201.23:49:18.60#ibcon#about to read 3, iclass 28, count 0 2006.201.23:49:18.62#ibcon#read 3, iclass 28, count 0 2006.201.23:49:18.62#ibcon#about to read 4, iclass 28, count 0 2006.201.23:49:18.62#ibcon#read 4, iclass 28, count 0 2006.201.23:49:18.62#ibcon#about to read 5, iclass 28, count 0 2006.201.23:49:18.62#ibcon#read 5, iclass 28, count 0 2006.201.23:49:18.62#ibcon#about to read 6, iclass 28, count 0 2006.201.23:49:18.62#ibcon#read 6, iclass 28, count 0 2006.201.23:49:18.62#ibcon#end of sib2, iclass 28, count 0 2006.201.23:49:18.62#ibcon#*mode == 0, iclass 28, count 0 2006.201.23:49:18.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.23:49:18.62#ibcon#[26=FRQ=01,524.99\r\n] 2006.201.23:49:18.62#ibcon#*before write, iclass 28, count 0 2006.201.23:49:18.62#ibcon#enter sib2, iclass 28, count 0 2006.201.23:49:18.62#ibcon#flushed, iclass 28, count 0 2006.201.23:49:18.62#ibcon#about to write, iclass 28, count 0 2006.201.23:49:18.62#ibcon#wrote, iclass 28, count 0 2006.201.23:49:18.62#ibcon#about to read 3, iclass 28, count 0 2006.201.23:49:18.67#ibcon#read 3, iclass 28, count 0 2006.201.23:49:18.67#ibcon#about to read 4, iclass 28, count 0 2006.201.23:49:18.67#ibcon#read 4, iclass 28, count 0 2006.201.23:49:18.67#ibcon#about to read 5, iclass 28, count 0 2006.201.23:49:18.67#ibcon#read 5, iclass 28, count 0 2006.201.23:49:18.67#ibcon#about to read 6, iclass 28, count 0 2006.201.23:49:18.67#ibcon#read 6, iclass 28, count 0 2006.201.23:49:18.67#ibcon#end of sib2, iclass 28, count 0 2006.201.23:49:18.67#ibcon#*after write, iclass 28, count 0 2006.201.23:49:18.67#ibcon#*before return 0, iclass 28, count 0 2006.201.23:49:18.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:18.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:18.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.23:49:18.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.23:49:18.67$vck44/va=1,8 2006.201.23:49:18.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.23:49:18.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.23:49:18.67#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:18.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:18.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:18.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:18.67#ibcon#enter wrdev, iclass 30, count 2 2006.201.23:49:18.67#ibcon#first serial, iclass 30, count 2 2006.201.23:49:18.67#ibcon#enter sib2, iclass 30, count 2 2006.201.23:49:18.67#ibcon#flushed, iclass 30, count 2 2006.201.23:49:18.67#ibcon#about to write, iclass 30, count 2 2006.201.23:49:18.67#ibcon#wrote, iclass 30, count 2 2006.201.23:49:18.67#ibcon#about to read 3, iclass 30, count 2 2006.201.23:49:18.69#ibcon#read 3, iclass 30, count 2 2006.201.23:49:18.69#ibcon#about to read 4, iclass 30, count 2 2006.201.23:49:18.69#ibcon#read 4, iclass 30, count 2 2006.201.23:49:18.69#ibcon#about to read 5, iclass 30, count 2 2006.201.23:49:18.69#ibcon#read 5, iclass 30, count 2 2006.201.23:49:18.69#ibcon#about to read 6, iclass 30, count 2 2006.201.23:49:18.69#ibcon#read 6, iclass 30, count 2 2006.201.23:49:18.69#ibcon#end of sib2, iclass 30, count 2 2006.201.23:49:18.69#ibcon#*mode == 0, iclass 30, count 2 2006.201.23:49:18.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.23:49:18.69#ibcon#[25=AT01-08\r\n] 2006.201.23:49:18.69#ibcon#*before write, iclass 30, count 2 2006.201.23:49:18.69#ibcon#enter sib2, iclass 30, count 2 2006.201.23:49:18.69#ibcon#flushed, iclass 30, count 2 2006.201.23:49:18.69#ibcon#about to write, iclass 30, count 2 2006.201.23:49:18.69#ibcon#wrote, iclass 30, count 2 2006.201.23:49:18.69#ibcon#about to read 3, iclass 30, count 2 2006.201.23:49:18.72#ibcon#read 3, iclass 30, count 2 2006.201.23:49:18.72#ibcon#about to read 4, iclass 30, count 2 2006.201.23:49:18.72#ibcon#read 4, iclass 30, count 2 2006.201.23:49:18.72#ibcon#about to read 5, iclass 30, count 2 2006.201.23:49:18.72#ibcon#read 5, iclass 30, count 2 2006.201.23:49:18.72#ibcon#about to read 6, iclass 30, count 2 2006.201.23:49:18.72#ibcon#read 6, iclass 30, count 2 2006.201.23:49:18.72#ibcon#end of sib2, iclass 30, count 2 2006.201.23:49:18.72#ibcon#*after write, iclass 30, count 2 2006.201.23:49:18.72#ibcon#*before return 0, iclass 30, count 2 2006.201.23:49:18.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:18.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:18.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.23:49:18.72#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:18.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:18.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:18.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:18.84#ibcon#enter wrdev, iclass 30, count 0 2006.201.23:49:18.84#ibcon#first serial, iclass 30, count 0 2006.201.23:49:18.84#ibcon#enter sib2, iclass 30, count 0 2006.201.23:49:18.84#ibcon#flushed, iclass 30, count 0 2006.201.23:49:18.84#ibcon#about to write, iclass 30, count 0 2006.201.23:49:18.84#ibcon#wrote, iclass 30, count 0 2006.201.23:49:18.84#ibcon#about to read 3, iclass 30, count 0 2006.201.23:49:18.86#ibcon#read 3, iclass 30, count 0 2006.201.23:49:18.86#ibcon#about to read 4, iclass 30, count 0 2006.201.23:49:18.86#ibcon#read 4, iclass 30, count 0 2006.201.23:49:18.86#ibcon#about to read 5, iclass 30, count 0 2006.201.23:49:18.86#ibcon#read 5, iclass 30, count 0 2006.201.23:49:18.86#ibcon#about to read 6, iclass 30, count 0 2006.201.23:49:18.86#ibcon#read 6, iclass 30, count 0 2006.201.23:49:18.86#ibcon#end of sib2, iclass 30, count 0 2006.201.23:49:18.86#ibcon#*mode == 0, iclass 30, count 0 2006.201.23:49:18.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.23:49:18.86#ibcon#[25=USB\r\n] 2006.201.23:49:18.86#ibcon#*before write, iclass 30, count 0 2006.201.23:49:18.86#ibcon#enter sib2, iclass 30, count 0 2006.201.23:49:18.86#ibcon#flushed, iclass 30, count 0 2006.201.23:49:18.86#ibcon#about to write, iclass 30, count 0 2006.201.23:49:18.86#ibcon#wrote, iclass 30, count 0 2006.201.23:49:18.86#ibcon#about to read 3, iclass 30, count 0 2006.201.23:49:18.89#ibcon#read 3, iclass 30, count 0 2006.201.23:49:18.89#ibcon#about to read 4, iclass 30, count 0 2006.201.23:49:18.89#ibcon#read 4, iclass 30, count 0 2006.201.23:49:18.89#ibcon#about to read 5, iclass 30, count 0 2006.201.23:49:18.89#ibcon#read 5, iclass 30, count 0 2006.201.23:49:18.89#ibcon#about to read 6, iclass 30, count 0 2006.201.23:49:18.89#ibcon#read 6, iclass 30, count 0 2006.201.23:49:18.89#ibcon#end of sib2, iclass 30, count 0 2006.201.23:49:18.89#ibcon#*after write, iclass 30, count 0 2006.201.23:49:18.89#ibcon#*before return 0, iclass 30, count 0 2006.201.23:49:18.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:18.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:18.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.23:49:18.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.23:49:18.89$vck44/valo=2,534.99 2006.201.23:49:18.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.201.23:49:18.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.201.23:49:18.89#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:18.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:49:18.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:49:18.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:49:18.89#ibcon#enter wrdev, iclass 32, count 0 2006.201.23:49:18.89#ibcon#first serial, iclass 32, count 0 2006.201.23:49:18.89#ibcon#enter sib2, iclass 32, count 0 2006.201.23:49:18.89#ibcon#flushed, iclass 32, count 0 2006.201.23:49:18.89#ibcon#about to write, iclass 32, count 0 2006.201.23:49:18.89#ibcon#wrote, iclass 32, count 0 2006.201.23:49:18.89#ibcon#about to read 3, iclass 32, count 0 2006.201.23:49:18.91#ibcon#read 3, iclass 32, count 0 2006.201.23:49:18.91#ibcon#about to read 4, iclass 32, count 0 2006.201.23:49:18.91#ibcon#read 4, iclass 32, count 0 2006.201.23:49:18.91#ibcon#about to read 5, iclass 32, count 0 2006.201.23:49:18.91#ibcon#read 5, iclass 32, count 0 2006.201.23:49:18.91#ibcon#about to read 6, iclass 32, count 0 2006.201.23:49:18.91#ibcon#read 6, iclass 32, count 0 2006.201.23:49:18.91#ibcon#end of sib2, iclass 32, count 0 2006.201.23:49:18.91#ibcon#*mode == 0, iclass 32, count 0 2006.201.23:49:18.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.201.23:49:18.91#ibcon#[26=FRQ=02,534.99\r\n] 2006.201.23:49:18.91#ibcon#*before write, iclass 32, count 0 2006.201.23:49:18.91#ibcon#enter sib2, iclass 32, count 0 2006.201.23:49:18.91#ibcon#flushed, iclass 32, count 0 2006.201.23:49:18.91#ibcon#about to write, iclass 32, count 0 2006.201.23:49:18.91#ibcon#wrote, iclass 32, count 0 2006.201.23:49:18.91#ibcon#about to read 3, iclass 32, count 0 2006.201.23:49:18.95#ibcon#read 3, iclass 32, count 0 2006.201.23:49:18.95#ibcon#about to read 4, iclass 32, count 0 2006.201.23:49:18.95#ibcon#read 4, iclass 32, count 0 2006.201.23:49:18.95#ibcon#about to read 5, iclass 32, count 0 2006.201.23:49:18.95#ibcon#read 5, iclass 32, count 0 2006.201.23:49:18.95#ibcon#about to read 6, iclass 32, count 0 2006.201.23:49:18.95#ibcon#read 6, iclass 32, count 0 2006.201.23:49:18.95#ibcon#end of sib2, iclass 32, count 0 2006.201.23:49:18.95#ibcon#*after write, iclass 32, count 0 2006.201.23:49:18.95#ibcon#*before return 0, iclass 32, count 0 2006.201.23:49:18.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:49:18.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.201.23:49:18.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.201.23:49:18.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.201.23:49:18.95$vck44/va=2,7 2006.201.23:49:18.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.201.23:49:18.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.201.23:49:18.95#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:18.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:49:19.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:49:19.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:49:19.01#ibcon#enter wrdev, iclass 34, count 2 2006.201.23:49:19.01#ibcon#first serial, iclass 34, count 2 2006.201.23:49:19.01#ibcon#enter sib2, iclass 34, count 2 2006.201.23:49:19.01#ibcon#flushed, iclass 34, count 2 2006.201.23:49:19.01#ibcon#about to write, iclass 34, count 2 2006.201.23:49:19.01#ibcon#wrote, iclass 34, count 2 2006.201.23:49:19.01#ibcon#about to read 3, iclass 34, count 2 2006.201.23:49:19.03#ibcon#read 3, iclass 34, count 2 2006.201.23:49:19.03#ibcon#about to read 4, iclass 34, count 2 2006.201.23:49:19.03#ibcon#read 4, iclass 34, count 2 2006.201.23:49:19.03#ibcon#about to read 5, iclass 34, count 2 2006.201.23:49:19.03#ibcon#read 5, iclass 34, count 2 2006.201.23:49:19.03#ibcon#about to read 6, iclass 34, count 2 2006.201.23:49:19.03#ibcon#read 6, iclass 34, count 2 2006.201.23:49:19.03#ibcon#end of sib2, iclass 34, count 2 2006.201.23:49:19.03#ibcon#*mode == 0, iclass 34, count 2 2006.201.23:49:19.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.201.23:49:19.03#ibcon#[25=AT02-07\r\n] 2006.201.23:49:19.03#ibcon#*before write, iclass 34, count 2 2006.201.23:49:19.03#ibcon#enter sib2, iclass 34, count 2 2006.201.23:49:19.03#ibcon#flushed, iclass 34, count 2 2006.201.23:49:19.03#ibcon#about to write, iclass 34, count 2 2006.201.23:49:19.03#ibcon#wrote, iclass 34, count 2 2006.201.23:49:19.03#ibcon#about to read 3, iclass 34, count 2 2006.201.23:49:19.06#ibcon#read 3, iclass 34, count 2 2006.201.23:49:19.06#ibcon#about to read 4, iclass 34, count 2 2006.201.23:49:19.06#ibcon#read 4, iclass 34, count 2 2006.201.23:49:19.06#ibcon#about to read 5, iclass 34, count 2 2006.201.23:49:19.06#ibcon#read 5, iclass 34, count 2 2006.201.23:49:19.06#ibcon#about to read 6, iclass 34, count 2 2006.201.23:49:19.06#ibcon#read 6, iclass 34, count 2 2006.201.23:49:19.06#ibcon#end of sib2, iclass 34, count 2 2006.201.23:49:19.06#ibcon#*after write, iclass 34, count 2 2006.201.23:49:19.06#ibcon#*before return 0, iclass 34, count 2 2006.201.23:49:19.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:49:19.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.201.23:49:19.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.201.23:49:19.06#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:19.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:49:19.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:49:19.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:49:19.18#ibcon#enter wrdev, iclass 34, count 0 2006.201.23:49:19.18#ibcon#first serial, iclass 34, count 0 2006.201.23:49:19.18#ibcon#enter sib2, iclass 34, count 0 2006.201.23:49:19.18#ibcon#flushed, iclass 34, count 0 2006.201.23:49:19.18#ibcon#about to write, iclass 34, count 0 2006.201.23:49:19.18#ibcon#wrote, iclass 34, count 0 2006.201.23:49:19.18#ibcon#about to read 3, iclass 34, count 0 2006.201.23:49:19.20#ibcon#read 3, iclass 34, count 0 2006.201.23:49:19.20#ibcon#about to read 4, iclass 34, count 0 2006.201.23:49:19.20#ibcon#read 4, iclass 34, count 0 2006.201.23:49:19.20#ibcon#about to read 5, iclass 34, count 0 2006.201.23:49:19.20#ibcon#read 5, iclass 34, count 0 2006.201.23:49:19.20#ibcon#about to read 6, iclass 34, count 0 2006.201.23:49:19.20#ibcon#read 6, iclass 34, count 0 2006.201.23:49:19.20#ibcon#end of sib2, iclass 34, count 0 2006.201.23:49:19.20#ibcon#*mode == 0, iclass 34, count 0 2006.201.23:49:19.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.201.23:49:19.20#ibcon#[25=USB\r\n] 2006.201.23:49:19.20#ibcon#*before write, iclass 34, count 0 2006.201.23:49:19.20#ibcon#enter sib2, iclass 34, count 0 2006.201.23:49:19.20#ibcon#flushed, iclass 34, count 0 2006.201.23:49:19.20#ibcon#about to write, iclass 34, count 0 2006.201.23:49:19.20#ibcon#wrote, iclass 34, count 0 2006.201.23:49:19.20#ibcon#about to read 3, iclass 34, count 0 2006.201.23:49:19.23#ibcon#read 3, iclass 34, count 0 2006.201.23:49:19.23#ibcon#about to read 4, iclass 34, count 0 2006.201.23:49:19.23#ibcon#read 4, iclass 34, count 0 2006.201.23:49:19.23#ibcon#about to read 5, iclass 34, count 0 2006.201.23:49:19.23#ibcon#read 5, iclass 34, count 0 2006.201.23:49:19.23#ibcon#about to read 6, iclass 34, count 0 2006.201.23:49:19.23#ibcon#read 6, iclass 34, count 0 2006.201.23:49:19.23#ibcon#end of sib2, iclass 34, count 0 2006.201.23:49:19.23#ibcon#*after write, iclass 34, count 0 2006.201.23:49:19.23#ibcon#*before return 0, iclass 34, count 0 2006.201.23:49:19.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:49:19.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.201.23:49:19.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.201.23:49:19.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.201.23:49:19.23$vck44/valo=3,564.99 2006.201.23:49:19.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.23:49:19.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.23:49:19.23#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:19.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:19.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:19.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:19.23#ibcon#enter wrdev, iclass 36, count 0 2006.201.23:49:19.23#ibcon#first serial, iclass 36, count 0 2006.201.23:49:19.23#ibcon#enter sib2, iclass 36, count 0 2006.201.23:49:19.23#ibcon#flushed, iclass 36, count 0 2006.201.23:49:19.23#ibcon#about to write, iclass 36, count 0 2006.201.23:49:19.23#ibcon#wrote, iclass 36, count 0 2006.201.23:49:19.23#ibcon#about to read 3, iclass 36, count 0 2006.201.23:49:19.25#ibcon#read 3, iclass 36, count 0 2006.201.23:49:19.25#ibcon#about to read 4, iclass 36, count 0 2006.201.23:49:19.25#ibcon#read 4, iclass 36, count 0 2006.201.23:49:19.25#ibcon#about to read 5, iclass 36, count 0 2006.201.23:49:19.25#ibcon#read 5, iclass 36, count 0 2006.201.23:49:19.25#ibcon#about to read 6, iclass 36, count 0 2006.201.23:49:19.25#ibcon#read 6, iclass 36, count 0 2006.201.23:49:19.25#ibcon#end of sib2, iclass 36, count 0 2006.201.23:49:19.25#ibcon#*mode == 0, iclass 36, count 0 2006.201.23:49:19.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.23:49:19.25#ibcon#[26=FRQ=03,564.99\r\n] 2006.201.23:49:19.25#ibcon#*before write, iclass 36, count 0 2006.201.23:49:19.25#ibcon#enter sib2, iclass 36, count 0 2006.201.23:49:19.25#ibcon#flushed, iclass 36, count 0 2006.201.23:49:19.25#ibcon#about to write, iclass 36, count 0 2006.201.23:49:19.25#ibcon#wrote, iclass 36, count 0 2006.201.23:49:19.25#ibcon#about to read 3, iclass 36, count 0 2006.201.23:49:19.29#ibcon#read 3, iclass 36, count 0 2006.201.23:49:19.29#ibcon#about to read 4, iclass 36, count 0 2006.201.23:49:19.29#ibcon#read 4, iclass 36, count 0 2006.201.23:49:19.29#ibcon#about to read 5, iclass 36, count 0 2006.201.23:49:19.29#ibcon#read 5, iclass 36, count 0 2006.201.23:49:19.29#ibcon#about to read 6, iclass 36, count 0 2006.201.23:49:19.29#ibcon#read 6, iclass 36, count 0 2006.201.23:49:19.29#ibcon#end of sib2, iclass 36, count 0 2006.201.23:49:19.29#ibcon#*after write, iclass 36, count 0 2006.201.23:49:19.29#ibcon#*before return 0, iclass 36, count 0 2006.201.23:49:19.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:19.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:19.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.23:49:19.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.23:49:19.29$vck44/va=3,8 2006.201.23:49:19.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.23:49:19.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.23:49:19.29#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:19.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:19.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:19.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:19.35#ibcon#enter wrdev, iclass 38, count 2 2006.201.23:49:19.35#ibcon#first serial, iclass 38, count 2 2006.201.23:49:19.35#ibcon#enter sib2, iclass 38, count 2 2006.201.23:49:19.35#ibcon#flushed, iclass 38, count 2 2006.201.23:49:19.35#ibcon#about to write, iclass 38, count 2 2006.201.23:49:19.35#ibcon#wrote, iclass 38, count 2 2006.201.23:49:19.35#ibcon#about to read 3, iclass 38, count 2 2006.201.23:49:19.37#ibcon#read 3, iclass 38, count 2 2006.201.23:49:19.37#ibcon#about to read 4, iclass 38, count 2 2006.201.23:49:19.37#ibcon#read 4, iclass 38, count 2 2006.201.23:49:19.37#ibcon#about to read 5, iclass 38, count 2 2006.201.23:49:19.37#ibcon#read 5, iclass 38, count 2 2006.201.23:49:19.37#ibcon#about to read 6, iclass 38, count 2 2006.201.23:49:19.37#ibcon#read 6, iclass 38, count 2 2006.201.23:49:19.37#ibcon#end of sib2, iclass 38, count 2 2006.201.23:49:19.37#ibcon#*mode == 0, iclass 38, count 2 2006.201.23:49:19.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.23:49:19.37#ibcon#[25=AT03-08\r\n] 2006.201.23:49:19.37#ibcon#*before write, iclass 38, count 2 2006.201.23:49:19.37#ibcon#enter sib2, iclass 38, count 2 2006.201.23:49:19.37#ibcon#flushed, iclass 38, count 2 2006.201.23:49:19.37#ibcon#about to write, iclass 38, count 2 2006.201.23:49:19.37#ibcon#wrote, iclass 38, count 2 2006.201.23:49:19.37#ibcon#about to read 3, iclass 38, count 2 2006.201.23:49:19.40#ibcon#read 3, iclass 38, count 2 2006.201.23:49:19.40#ibcon#about to read 4, iclass 38, count 2 2006.201.23:49:19.40#ibcon#read 4, iclass 38, count 2 2006.201.23:49:19.40#ibcon#about to read 5, iclass 38, count 2 2006.201.23:49:19.40#ibcon#read 5, iclass 38, count 2 2006.201.23:49:19.40#ibcon#about to read 6, iclass 38, count 2 2006.201.23:49:19.40#ibcon#read 6, iclass 38, count 2 2006.201.23:49:19.40#ibcon#end of sib2, iclass 38, count 2 2006.201.23:49:19.40#ibcon#*after write, iclass 38, count 2 2006.201.23:49:19.40#ibcon#*before return 0, iclass 38, count 2 2006.201.23:49:19.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:19.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:19.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.23:49:19.40#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:19.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:19.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:19.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:19.52#ibcon#enter wrdev, iclass 38, count 0 2006.201.23:49:19.52#ibcon#first serial, iclass 38, count 0 2006.201.23:49:19.52#ibcon#enter sib2, iclass 38, count 0 2006.201.23:49:19.52#ibcon#flushed, iclass 38, count 0 2006.201.23:49:19.52#ibcon#about to write, iclass 38, count 0 2006.201.23:49:19.52#ibcon#wrote, iclass 38, count 0 2006.201.23:49:19.52#ibcon#about to read 3, iclass 38, count 0 2006.201.23:49:19.54#ibcon#read 3, iclass 38, count 0 2006.201.23:49:19.54#ibcon#about to read 4, iclass 38, count 0 2006.201.23:49:19.54#ibcon#read 4, iclass 38, count 0 2006.201.23:49:19.54#ibcon#about to read 5, iclass 38, count 0 2006.201.23:49:19.54#ibcon#read 5, iclass 38, count 0 2006.201.23:49:19.54#ibcon#about to read 6, iclass 38, count 0 2006.201.23:49:19.54#ibcon#read 6, iclass 38, count 0 2006.201.23:49:19.54#ibcon#end of sib2, iclass 38, count 0 2006.201.23:49:19.54#ibcon#*mode == 0, iclass 38, count 0 2006.201.23:49:19.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.23:49:19.54#ibcon#[25=USB\r\n] 2006.201.23:49:19.54#ibcon#*before write, iclass 38, count 0 2006.201.23:49:19.54#ibcon#enter sib2, iclass 38, count 0 2006.201.23:49:19.54#ibcon#flushed, iclass 38, count 0 2006.201.23:49:19.54#ibcon#about to write, iclass 38, count 0 2006.201.23:49:19.54#ibcon#wrote, iclass 38, count 0 2006.201.23:49:19.54#ibcon#about to read 3, iclass 38, count 0 2006.201.23:49:19.57#ibcon#read 3, iclass 38, count 0 2006.201.23:49:19.57#ibcon#about to read 4, iclass 38, count 0 2006.201.23:49:19.57#ibcon#read 4, iclass 38, count 0 2006.201.23:49:19.57#ibcon#about to read 5, iclass 38, count 0 2006.201.23:49:19.57#ibcon#read 5, iclass 38, count 0 2006.201.23:49:19.57#ibcon#about to read 6, iclass 38, count 0 2006.201.23:49:19.57#ibcon#read 6, iclass 38, count 0 2006.201.23:49:19.57#ibcon#end of sib2, iclass 38, count 0 2006.201.23:49:19.57#ibcon#*after write, iclass 38, count 0 2006.201.23:49:19.57#ibcon#*before return 0, iclass 38, count 0 2006.201.23:49:19.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:19.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:19.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.23:49:19.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.23:49:19.57$vck44/valo=4,624.99 2006.201.23:49:19.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.23:49:19.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.23:49:19.57#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:19.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:19.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:19.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:19.57#ibcon#enter wrdev, iclass 40, count 0 2006.201.23:49:19.57#ibcon#first serial, iclass 40, count 0 2006.201.23:49:19.57#ibcon#enter sib2, iclass 40, count 0 2006.201.23:49:19.57#ibcon#flushed, iclass 40, count 0 2006.201.23:49:19.57#ibcon#about to write, iclass 40, count 0 2006.201.23:49:19.57#ibcon#wrote, iclass 40, count 0 2006.201.23:49:19.57#ibcon#about to read 3, iclass 40, count 0 2006.201.23:49:19.59#ibcon#read 3, iclass 40, count 0 2006.201.23:49:19.59#ibcon#about to read 4, iclass 40, count 0 2006.201.23:49:19.59#ibcon#read 4, iclass 40, count 0 2006.201.23:49:19.59#ibcon#about to read 5, iclass 40, count 0 2006.201.23:49:19.59#ibcon#read 5, iclass 40, count 0 2006.201.23:49:19.59#ibcon#about to read 6, iclass 40, count 0 2006.201.23:49:19.59#ibcon#read 6, iclass 40, count 0 2006.201.23:49:19.59#ibcon#end of sib2, iclass 40, count 0 2006.201.23:49:19.59#ibcon#*mode == 0, iclass 40, count 0 2006.201.23:49:19.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.23:49:19.59#ibcon#[26=FRQ=04,624.99\r\n] 2006.201.23:49:19.59#ibcon#*before write, iclass 40, count 0 2006.201.23:49:19.59#ibcon#enter sib2, iclass 40, count 0 2006.201.23:49:19.59#ibcon#flushed, iclass 40, count 0 2006.201.23:49:19.59#ibcon#about to write, iclass 40, count 0 2006.201.23:49:19.59#ibcon#wrote, iclass 40, count 0 2006.201.23:49:19.59#ibcon#about to read 3, iclass 40, count 0 2006.201.23:49:19.63#ibcon#read 3, iclass 40, count 0 2006.201.23:49:19.63#ibcon#about to read 4, iclass 40, count 0 2006.201.23:49:19.63#ibcon#read 4, iclass 40, count 0 2006.201.23:49:19.63#ibcon#about to read 5, iclass 40, count 0 2006.201.23:49:19.63#ibcon#read 5, iclass 40, count 0 2006.201.23:49:19.63#ibcon#about to read 6, iclass 40, count 0 2006.201.23:49:19.63#ibcon#read 6, iclass 40, count 0 2006.201.23:49:19.63#ibcon#end of sib2, iclass 40, count 0 2006.201.23:49:19.63#ibcon#*after write, iclass 40, count 0 2006.201.23:49:19.63#ibcon#*before return 0, iclass 40, count 0 2006.201.23:49:19.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:19.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:19.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.23:49:19.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.23:49:19.63$vck44/va=4,7 2006.201.23:49:19.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.23:49:19.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.23:49:19.63#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:19.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:19.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:19.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:19.69#ibcon#enter wrdev, iclass 4, count 2 2006.201.23:49:19.69#ibcon#first serial, iclass 4, count 2 2006.201.23:49:19.69#ibcon#enter sib2, iclass 4, count 2 2006.201.23:49:19.69#ibcon#flushed, iclass 4, count 2 2006.201.23:49:19.69#ibcon#about to write, iclass 4, count 2 2006.201.23:49:19.69#ibcon#wrote, iclass 4, count 2 2006.201.23:49:19.69#ibcon#about to read 3, iclass 4, count 2 2006.201.23:49:19.71#ibcon#read 3, iclass 4, count 2 2006.201.23:49:19.71#ibcon#about to read 4, iclass 4, count 2 2006.201.23:49:19.71#ibcon#read 4, iclass 4, count 2 2006.201.23:49:19.71#ibcon#about to read 5, iclass 4, count 2 2006.201.23:49:19.71#ibcon#read 5, iclass 4, count 2 2006.201.23:49:19.71#ibcon#about to read 6, iclass 4, count 2 2006.201.23:49:19.71#ibcon#read 6, iclass 4, count 2 2006.201.23:49:19.71#ibcon#end of sib2, iclass 4, count 2 2006.201.23:49:19.71#ibcon#*mode == 0, iclass 4, count 2 2006.201.23:49:19.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.23:49:19.71#ibcon#[25=AT04-07\r\n] 2006.201.23:49:19.71#ibcon#*before write, iclass 4, count 2 2006.201.23:49:19.71#ibcon#enter sib2, iclass 4, count 2 2006.201.23:49:19.71#ibcon#flushed, iclass 4, count 2 2006.201.23:49:19.71#ibcon#about to write, iclass 4, count 2 2006.201.23:49:19.71#ibcon#wrote, iclass 4, count 2 2006.201.23:49:19.71#ibcon#about to read 3, iclass 4, count 2 2006.201.23:49:19.74#ibcon#read 3, iclass 4, count 2 2006.201.23:49:19.74#ibcon#about to read 4, iclass 4, count 2 2006.201.23:49:19.74#ibcon#read 4, iclass 4, count 2 2006.201.23:49:19.74#ibcon#about to read 5, iclass 4, count 2 2006.201.23:49:19.74#ibcon#read 5, iclass 4, count 2 2006.201.23:49:19.74#ibcon#about to read 6, iclass 4, count 2 2006.201.23:49:19.74#ibcon#read 6, iclass 4, count 2 2006.201.23:49:19.74#ibcon#end of sib2, iclass 4, count 2 2006.201.23:49:19.74#ibcon#*after write, iclass 4, count 2 2006.201.23:49:19.74#ibcon#*before return 0, iclass 4, count 2 2006.201.23:49:19.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:19.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:19.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.23:49:19.74#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:19.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:19.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:19.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:19.86#ibcon#enter wrdev, iclass 4, count 0 2006.201.23:49:19.86#ibcon#first serial, iclass 4, count 0 2006.201.23:49:19.86#ibcon#enter sib2, iclass 4, count 0 2006.201.23:49:19.86#ibcon#flushed, iclass 4, count 0 2006.201.23:49:19.86#ibcon#about to write, iclass 4, count 0 2006.201.23:49:19.86#ibcon#wrote, iclass 4, count 0 2006.201.23:49:19.86#ibcon#about to read 3, iclass 4, count 0 2006.201.23:49:19.88#ibcon#read 3, iclass 4, count 0 2006.201.23:49:19.88#ibcon#about to read 4, iclass 4, count 0 2006.201.23:49:19.88#ibcon#read 4, iclass 4, count 0 2006.201.23:49:19.88#ibcon#about to read 5, iclass 4, count 0 2006.201.23:49:19.88#ibcon#read 5, iclass 4, count 0 2006.201.23:49:19.88#ibcon#about to read 6, iclass 4, count 0 2006.201.23:49:19.88#ibcon#read 6, iclass 4, count 0 2006.201.23:49:19.88#ibcon#end of sib2, iclass 4, count 0 2006.201.23:49:19.88#ibcon#*mode == 0, iclass 4, count 0 2006.201.23:49:19.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.23:49:19.88#ibcon#[25=USB\r\n] 2006.201.23:49:19.88#ibcon#*before write, iclass 4, count 0 2006.201.23:49:19.88#ibcon#enter sib2, iclass 4, count 0 2006.201.23:49:19.88#ibcon#flushed, iclass 4, count 0 2006.201.23:49:19.88#ibcon#about to write, iclass 4, count 0 2006.201.23:49:19.88#ibcon#wrote, iclass 4, count 0 2006.201.23:49:19.88#ibcon#about to read 3, iclass 4, count 0 2006.201.23:49:19.91#ibcon#read 3, iclass 4, count 0 2006.201.23:49:19.91#ibcon#about to read 4, iclass 4, count 0 2006.201.23:49:19.91#ibcon#read 4, iclass 4, count 0 2006.201.23:49:19.91#ibcon#about to read 5, iclass 4, count 0 2006.201.23:49:19.91#ibcon#read 5, iclass 4, count 0 2006.201.23:49:19.91#ibcon#about to read 6, iclass 4, count 0 2006.201.23:49:19.91#ibcon#read 6, iclass 4, count 0 2006.201.23:49:19.91#ibcon#end of sib2, iclass 4, count 0 2006.201.23:49:19.91#ibcon#*after write, iclass 4, count 0 2006.201.23:49:19.91#ibcon#*before return 0, iclass 4, count 0 2006.201.23:49:19.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:19.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:19.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.23:49:19.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.23:49:19.91$vck44/valo=5,734.99 2006.201.23:49:19.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.23:49:19.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.23:49:19.91#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:19.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:19.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:19.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:19.91#ibcon#enter wrdev, iclass 6, count 0 2006.201.23:49:19.91#ibcon#first serial, iclass 6, count 0 2006.201.23:49:19.91#ibcon#enter sib2, iclass 6, count 0 2006.201.23:49:19.91#ibcon#flushed, iclass 6, count 0 2006.201.23:49:19.91#ibcon#about to write, iclass 6, count 0 2006.201.23:49:19.91#ibcon#wrote, iclass 6, count 0 2006.201.23:49:19.91#ibcon#about to read 3, iclass 6, count 0 2006.201.23:49:19.93#ibcon#read 3, iclass 6, count 0 2006.201.23:49:19.93#ibcon#about to read 4, iclass 6, count 0 2006.201.23:49:19.93#ibcon#read 4, iclass 6, count 0 2006.201.23:49:19.93#ibcon#about to read 5, iclass 6, count 0 2006.201.23:49:19.93#ibcon#read 5, iclass 6, count 0 2006.201.23:49:19.93#ibcon#about to read 6, iclass 6, count 0 2006.201.23:49:19.93#ibcon#read 6, iclass 6, count 0 2006.201.23:49:19.93#ibcon#end of sib2, iclass 6, count 0 2006.201.23:49:19.93#ibcon#*mode == 0, iclass 6, count 0 2006.201.23:49:19.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.23:49:19.93#ibcon#[26=FRQ=05,734.99\r\n] 2006.201.23:49:19.93#ibcon#*before write, iclass 6, count 0 2006.201.23:49:19.93#ibcon#enter sib2, iclass 6, count 0 2006.201.23:49:19.93#ibcon#flushed, iclass 6, count 0 2006.201.23:49:19.93#ibcon#about to write, iclass 6, count 0 2006.201.23:49:19.93#ibcon#wrote, iclass 6, count 0 2006.201.23:49:19.93#ibcon#about to read 3, iclass 6, count 0 2006.201.23:49:19.97#ibcon#read 3, iclass 6, count 0 2006.201.23:49:19.97#ibcon#about to read 4, iclass 6, count 0 2006.201.23:49:19.97#ibcon#read 4, iclass 6, count 0 2006.201.23:49:19.97#ibcon#about to read 5, iclass 6, count 0 2006.201.23:49:19.97#ibcon#read 5, iclass 6, count 0 2006.201.23:49:19.97#ibcon#about to read 6, iclass 6, count 0 2006.201.23:49:19.97#ibcon#read 6, iclass 6, count 0 2006.201.23:49:19.97#ibcon#end of sib2, iclass 6, count 0 2006.201.23:49:19.97#ibcon#*after write, iclass 6, count 0 2006.201.23:49:19.97#ibcon#*before return 0, iclass 6, count 0 2006.201.23:49:19.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:19.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:19.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.23:49:19.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.23:49:19.97$vck44/va=5,4 2006.201.23:49:19.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.23:49:19.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.23:49:19.97#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:19.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:20.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:20.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:20.03#ibcon#enter wrdev, iclass 10, count 2 2006.201.23:49:20.03#ibcon#first serial, iclass 10, count 2 2006.201.23:49:20.03#ibcon#enter sib2, iclass 10, count 2 2006.201.23:49:20.03#ibcon#flushed, iclass 10, count 2 2006.201.23:49:20.03#ibcon#about to write, iclass 10, count 2 2006.201.23:49:20.03#ibcon#wrote, iclass 10, count 2 2006.201.23:49:20.03#ibcon#about to read 3, iclass 10, count 2 2006.201.23:49:20.05#ibcon#read 3, iclass 10, count 2 2006.201.23:49:20.05#ibcon#about to read 4, iclass 10, count 2 2006.201.23:49:20.05#ibcon#read 4, iclass 10, count 2 2006.201.23:49:20.05#ibcon#about to read 5, iclass 10, count 2 2006.201.23:49:20.05#ibcon#read 5, iclass 10, count 2 2006.201.23:49:20.05#ibcon#about to read 6, iclass 10, count 2 2006.201.23:49:20.05#ibcon#read 6, iclass 10, count 2 2006.201.23:49:20.05#ibcon#end of sib2, iclass 10, count 2 2006.201.23:49:20.05#ibcon#*mode == 0, iclass 10, count 2 2006.201.23:49:20.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.23:49:20.05#ibcon#[25=AT05-04\r\n] 2006.201.23:49:20.05#ibcon#*before write, iclass 10, count 2 2006.201.23:49:20.05#ibcon#enter sib2, iclass 10, count 2 2006.201.23:49:20.05#ibcon#flushed, iclass 10, count 2 2006.201.23:49:20.05#ibcon#about to write, iclass 10, count 2 2006.201.23:49:20.05#ibcon#wrote, iclass 10, count 2 2006.201.23:49:20.05#ibcon#about to read 3, iclass 10, count 2 2006.201.23:49:20.08#ibcon#read 3, iclass 10, count 2 2006.201.23:49:20.08#ibcon#about to read 4, iclass 10, count 2 2006.201.23:49:20.08#ibcon#read 4, iclass 10, count 2 2006.201.23:49:20.08#ibcon#about to read 5, iclass 10, count 2 2006.201.23:49:20.08#ibcon#read 5, iclass 10, count 2 2006.201.23:49:20.08#ibcon#about to read 6, iclass 10, count 2 2006.201.23:49:20.08#ibcon#read 6, iclass 10, count 2 2006.201.23:49:20.08#ibcon#end of sib2, iclass 10, count 2 2006.201.23:49:20.08#ibcon#*after write, iclass 10, count 2 2006.201.23:49:20.08#ibcon#*before return 0, iclass 10, count 2 2006.201.23:49:20.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:20.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:20.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.23:49:20.08#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:20.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:20.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:20.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:20.20#ibcon#enter wrdev, iclass 10, count 0 2006.201.23:49:20.20#ibcon#first serial, iclass 10, count 0 2006.201.23:49:20.20#ibcon#enter sib2, iclass 10, count 0 2006.201.23:49:20.20#ibcon#flushed, iclass 10, count 0 2006.201.23:49:20.20#ibcon#about to write, iclass 10, count 0 2006.201.23:49:20.20#ibcon#wrote, iclass 10, count 0 2006.201.23:49:20.20#ibcon#about to read 3, iclass 10, count 0 2006.201.23:49:20.22#ibcon#read 3, iclass 10, count 0 2006.201.23:49:20.22#ibcon#about to read 4, iclass 10, count 0 2006.201.23:49:20.22#ibcon#read 4, iclass 10, count 0 2006.201.23:49:20.22#ibcon#about to read 5, iclass 10, count 0 2006.201.23:49:20.22#ibcon#read 5, iclass 10, count 0 2006.201.23:49:20.22#ibcon#about to read 6, iclass 10, count 0 2006.201.23:49:20.22#ibcon#read 6, iclass 10, count 0 2006.201.23:49:20.22#ibcon#end of sib2, iclass 10, count 0 2006.201.23:49:20.22#ibcon#*mode == 0, iclass 10, count 0 2006.201.23:49:20.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.23:49:20.22#ibcon#[25=USB\r\n] 2006.201.23:49:20.22#ibcon#*before write, iclass 10, count 0 2006.201.23:49:20.22#ibcon#enter sib2, iclass 10, count 0 2006.201.23:49:20.22#ibcon#flushed, iclass 10, count 0 2006.201.23:49:20.22#ibcon#about to write, iclass 10, count 0 2006.201.23:49:20.22#ibcon#wrote, iclass 10, count 0 2006.201.23:49:20.22#ibcon#about to read 3, iclass 10, count 0 2006.201.23:49:20.25#ibcon#read 3, iclass 10, count 0 2006.201.23:49:20.25#ibcon#about to read 4, iclass 10, count 0 2006.201.23:49:20.25#ibcon#read 4, iclass 10, count 0 2006.201.23:49:20.25#ibcon#about to read 5, iclass 10, count 0 2006.201.23:49:20.25#ibcon#read 5, iclass 10, count 0 2006.201.23:49:20.25#ibcon#about to read 6, iclass 10, count 0 2006.201.23:49:20.25#ibcon#read 6, iclass 10, count 0 2006.201.23:49:20.25#ibcon#end of sib2, iclass 10, count 0 2006.201.23:49:20.25#ibcon#*after write, iclass 10, count 0 2006.201.23:49:20.25#ibcon#*before return 0, iclass 10, count 0 2006.201.23:49:20.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:20.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:20.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.23:49:20.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.23:49:20.25$vck44/valo=6,814.99 2006.201.23:49:20.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.23:49:20.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.23:49:20.25#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:20.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:20.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:20.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:20.25#ibcon#enter wrdev, iclass 12, count 0 2006.201.23:49:20.25#ibcon#first serial, iclass 12, count 0 2006.201.23:49:20.25#ibcon#enter sib2, iclass 12, count 0 2006.201.23:49:20.25#ibcon#flushed, iclass 12, count 0 2006.201.23:49:20.25#ibcon#about to write, iclass 12, count 0 2006.201.23:49:20.25#ibcon#wrote, iclass 12, count 0 2006.201.23:49:20.25#ibcon#about to read 3, iclass 12, count 0 2006.201.23:49:20.27#ibcon#read 3, iclass 12, count 0 2006.201.23:49:20.27#ibcon#about to read 4, iclass 12, count 0 2006.201.23:49:20.27#ibcon#read 4, iclass 12, count 0 2006.201.23:49:20.27#ibcon#about to read 5, iclass 12, count 0 2006.201.23:49:20.27#ibcon#read 5, iclass 12, count 0 2006.201.23:49:20.27#ibcon#about to read 6, iclass 12, count 0 2006.201.23:49:20.27#ibcon#read 6, iclass 12, count 0 2006.201.23:49:20.27#ibcon#end of sib2, iclass 12, count 0 2006.201.23:49:20.27#ibcon#*mode == 0, iclass 12, count 0 2006.201.23:49:20.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.23:49:20.27#ibcon#[26=FRQ=06,814.99\r\n] 2006.201.23:49:20.27#ibcon#*before write, iclass 12, count 0 2006.201.23:49:20.27#ibcon#enter sib2, iclass 12, count 0 2006.201.23:49:20.27#ibcon#flushed, iclass 12, count 0 2006.201.23:49:20.27#ibcon#about to write, iclass 12, count 0 2006.201.23:49:20.27#ibcon#wrote, iclass 12, count 0 2006.201.23:49:20.27#ibcon#about to read 3, iclass 12, count 0 2006.201.23:49:20.31#ibcon#read 3, iclass 12, count 0 2006.201.23:49:20.31#ibcon#about to read 4, iclass 12, count 0 2006.201.23:49:20.31#ibcon#read 4, iclass 12, count 0 2006.201.23:49:20.31#ibcon#about to read 5, iclass 12, count 0 2006.201.23:49:20.31#ibcon#read 5, iclass 12, count 0 2006.201.23:49:20.31#ibcon#about to read 6, iclass 12, count 0 2006.201.23:49:20.31#ibcon#read 6, iclass 12, count 0 2006.201.23:49:20.31#ibcon#end of sib2, iclass 12, count 0 2006.201.23:49:20.31#ibcon#*after write, iclass 12, count 0 2006.201.23:49:20.31#ibcon#*before return 0, iclass 12, count 0 2006.201.23:49:20.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:20.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:20.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.23:49:20.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.23:49:20.31$vck44/va=6,5 2006.201.23:49:20.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.23:49:20.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.23:49:20.31#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:20.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:20.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:20.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:20.37#ibcon#enter wrdev, iclass 14, count 2 2006.201.23:49:20.37#ibcon#first serial, iclass 14, count 2 2006.201.23:49:20.37#ibcon#enter sib2, iclass 14, count 2 2006.201.23:49:20.37#ibcon#flushed, iclass 14, count 2 2006.201.23:49:20.37#ibcon#about to write, iclass 14, count 2 2006.201.23:49:20.37#ibcon#wrote, iclass 14, count 2 2006.201.23:49:20.37#ibcon#about to read 3, iclass 14, count 2 2006.201.23:49:20.39#ibcon#read 3, iclass 14, count 2 2006.201.23:49:20.39#ibcon#about to read 4, iclass 14, count 2 2006.201.23:49:20.39#ibcon#read 4, iclass 14, count 2 2006.201.23:49:20.39#ibcon#about to read 5, iclass 14, count 2 2006.201.23:49:20.39#ibcon#read 5, iclass 14, count 2 2006.201.23:49:20.39#ibcon#about to read 6, iclass 14, count 2 2006.201.23:49:20.39#ibcon#read 6, iclass 14, count 2 2006.201.23:49:20.39#ibcon#end of sib2, iclass 14, count 2 2006.201.23:49:20.39#ibcon#*mode == 0, iclass 14, count 2 2006.201.23:49:20.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.23:49:20.39#ibcon#[25=AT06-05\r\n] 2006.201.23:49:20.39#ibcon#*before write, iclass 14, count 2 2006.201.23:49:20.39#ibcon#enter sib2, iclass 14, count 2 2006.201.23:49:20.39#ibcon#flushed, iclass 14, count 2 2006.201.23:49:20.39#ibcon#about to write, iclass 14, count 2 2006.201.23:49:20.39#ibcon#wrote, iclass 14, count 2 2006.201.23:49:20.39#ibcon#about to read 3, iclass 14, count 2 2006.201.23:49:20.42#ibcon#read 3, iclass 14, count 2 2006.201.23:49:20.42#ibcon#about to read 4, iclass 14, count 2 2006.201.23:49:20.42#ibcon#read 4, iclass 14, count 2 2006.201.23:49:20.42#ibcon#about to read 5, iclass 14, count 2 2006.201.23:49:20.42#ibcon#read 5, iclass 14, count 2 2006.201.23:49:20.42#ibcon#about to read 6, iclass 14, count 2 2006.201.23:49:20.42#ibcon#read 6, iclass 14, count 2 2006.201.23:49:20.42#ibcon#end of sib2, iclass 14, count 2 2006.201.23:49:20.42#ibcon#*after write, iclass 14, count 2 2006.201.23:49:20.42#ibcon#*before return 0, iclass 14, count 2 2006.201.23:49:20.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:20.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:20.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.23:49:20.42#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:20.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:20.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:20.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:20.54#ibcon#enter wrdev, iclass 14, count 0 2006.201.23:49:20.54#ibcon#first serial, iclass 14, count 0 2006.201.23:49:20.54#ibcon#enter sib2, iclass 14, count 0 2006.201.23:49:20.54#ibcon#flushed, iclass 14, count 0 2006.201.23:49:20.54#ibcon#about to write, iclass 14, count 0 2006.201.23:49:20.54#ibcon#wrote, iclass 14, count 0 2006.201.23:49:20.54#ibcon#about to read 3, iclass 14, count 0 2006.201.23:49:20.56#ibcon#read 3, iclass 14, count 0 2006.201.23:49:20.56#ibcon#about to read 4, iclass 14, count 0 2006.201.23:49:20.56#ibcon#read 4, iclass 14, count 0 2006.201.23:49:20.56#ibcon#about to read 5, iclass 14, count 0 2006.201.23:49:20.56#ibcon#read 5, iclass 14, count 0 2006.201.23:49:20.56#ibcon#about to read 6, iclass 14, count 0 2006.201.23:49:20.56#ibcon#read 6, iclass 14, count 0 2006.201.23:49:20.56#ibcon#end of sib2, iclass 14, count 0 2006.201.23:49:20.56#ibcon#*mode == 0, iclass 14, count 0 2006.201.23:49:20.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.23:49:20.56#ibcon#[25=USB\r\n] 2006.201.23:49:20.56#ibcon#*before write, iclass 14, count 0 2006.201.23:49:20.56#ibcon#enter sib2, iclass 14, count 0 2006.201.23:49:20.56#ibcon#flushed, iclass 14, count 0 2006.201.23:49:20.56#ibcon#about to write, iclass 14, count 0 2006.201.23:49:20.56#ibcon#wrote, iclass 14, count 0 2006.201.23:49:20.56#ibcon#about to read 3, iclass 14, count 0 2006.201.23:49:20.59#ibcon#read 3, iclass 14, count 0 2006.201.23:49:20.59#ibcon#about to read 4, iclass 14, count 0 2006.201.23:49:20.59#ibcon#read 4, iclass 14, count 0 2006.201.23:49:20.59#ibcon#about to read 5, iclass 14, count 0 2006.201.23:49:20.59#ibcon#read 5, iclass 14, count 0 2006.201.23:49:20.59#ibcon#about to read 6, iclass 14, count 0 2006.201.23:49:20.59#ibcon#read 6, iclass 14, count 0 2006.201.23:49:20.59#ibcon#end of sib2, iclass 14, count 0 2006.201.23:49:20.59#ibcon#*after write, iclass 14, count 0 2006.201.23:49:20.59#ibcon#*before return 0, iclass 14, count 0 2006.201.23:49:20.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:20.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:20.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.23:49:20.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.23:49:20.59$vck44/valo=7,864.99 2006.201.23:49:20.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.23:49:20.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.23:49:20.59#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:20.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:20.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:20.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:20.59#ibcon#enter wrdev, iclass 16, count 0 2006.201.23:49:20.59#ibcon#first serial, iclass 16, count 0 2006.201.23:49:20.59#ibcon#enter sib2, iclass 16, count 0 2006.201.23:49:20.59#ibcon#flushed, iclass 16, count 0 2006.201.23:49:20.59#ibcon#about to write, iclass 16, count 0 2006.201.23:49:20.59#ibcon#wrote, iclass 16, count 0 2006.201.23:49:20.59#ibcon#about to read 3, iclass 16, count 0 2006.201.23:49:20.61#ibcon#read 3, iclass 16, count 0 2006.201.23:49:20.61#ibcon#about to read 4, iclass 16, count 0 2006.201.23:49:20.61#ibcon#read 4, iclass 16, count 0 2006.201.23:49:20.61#ibcon#about to read 5, iclass 16, count 0 2006.201.23:49:20.61#ibcon#read 5, iclass 16, count 0 2006.201.23:49:20.61#ibcon#about to read 6, iclass 16, count 0 2006.201.23:49:20.61#ibcon#read 6, iclass 16, count 0 2006.201.23:49:20.61#ibcon#end of sib2, iclass 16, count 0 2006.201.23:49:20.61#ibcon#*mode == 0, iclass 16, count 0 2006.201.23:49:20.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.23:49:20.61#ibcon#[26=FRQ=07,864.99\r\n] 2006.201.23:49:20.61#ibcon#*before write, iclass 16, count 0 2006.201.23:49:20.61#ibcon#enter sib2, iclass 16, count 0 2006.201.23:49:20.61#ibcon#flushed, iclass 16, count 0 2006.201.23:49:20.61#ibcon#about to write, iclass 16, count 0 2006.201.23:49:20.61#ibcon#wrote, iclass 16, count 0 2006.201.23:49:20.61#ibcon#about to read 3, iclass 16, count 0 2006.201.23:49:20.65#ibcon#read 3, iclass 16, count 0 2006.201.23:49:20.65#ibcon#about to read 4, iclass 16, count 0 2006.201.23:49:20.65#ibcon#read 4, iclass 16, count 0 2006.201.23:49:20.65#ibcon#about to read 5, iclass 16, count 0 2006.201.23:49:20.65#ibcon#read 5, iclass 16, count 0 2006.201.23:49:20.65#ibcon#about to read 6, iclass 16, count 0 2006.201.23:49:20.65#ibcon#read 6, iclass 16, count 0 2006.201.23:49:20.65#ibcon#end of sib2, iclass 16, count 0 2006.201.23:49:20.65#ibcon#*after write, iclass 16, count 0 2006.201.23:49:20.65#ibcon#*before return 0, iclass 16, count 0 2006.201.23:49:20.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:20.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:20.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.23:49:20.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.23:49:20.65$vck44/va=7,5 2006.201.23:49:20.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.23:49:20.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.23:49:20.65#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:20.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:20.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:20.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:20.71#ibcon#enter wrdev, iclass 18, count 2 2006.201.23:49:20.71#ibcon#first serial, iclass 18, count 2 2006.201.23:49:20.71#ibcon#enter sib2, iclass 18, count 2 2006.201.23:49:20.71#ibcon#flushed, iclass 18, count 2 2006.201.23:49:20.71#ibcon#about to write, iclass 18, count 2 2006.201.23:49:20.71#ibcon#wrote, iclass 18, count 2 2006.201.23:49:20.71#ibcon#about to read 3, iclass 18, count 2 2006.201.23:49:20.73#ibcon#read 3, iclass 18, count 2 2006.201.23:49:20.73#ibcon#about to read 4, iclass 18, count 2 2006.201.23:49:20.73#ibcon#read 4, iclass 18, count 2 2006.201.23:49:20.73#ibcon#about to read 5, iclass 18, count 2 2006.201.23:49:20.73#ibcon#read 5, iclass 18, count 2 2006.201.23:49:20.73#ibcon#about to read 6, iclass 18, count 2 2006.201.23:49:20.73#ibcon#read 6, iclass 18, count 2 2006.201.23:49:20.73#ibcon#end of sib2, iclass 18, count 2 2006.201.23:49:20.73#ibcon#*mode == 0, iclass 18, count 2 2006.201.23:49:20.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.23:49:20.73#ibcon#[25=AT07-05\r\n] 2006.201.23:49:20.73#ibcon#*before write, iclass 18, count 2 2006.201.23:49:20.73#ibcon#enter sib2, iclass 18, count 2 2006.201.23:49:20.73#ibcon#flushed, iclass 18, count 2 2006.201.23:49:20.73#ibcon#about to write, iclass 18, count 2 2006.201.23:49:20.73#ibcon#wrote, iclass 18, count 2 2006.201.23:49:20.73#ibcon#about to read 3, iclass 18, count 2 2006.201.23:49:20.76#ibcon#read 3, iclass 18, count 2 2006.201.23:49:20.76#ibcon#about to read 4, iclass 18, count 2 2006.201.23:49:20.76#ibcon#read 4, iclass 18, count 2 2006.201.23:49:20.76#ibcon#about to read 5, iclass 18, count 2 2006.201.23:49:20.76#ibcon#read 5, iclass 18, count 2 2006.201.23:49:20.76#ibcon#about to read 6, iclass 18, count 2 2006.201.23:49:20.76#ibcon#read 6, iclass 18, count 2 2006.201.23:49:20.76#ibcon#end of sib2, iclass 18, count 2 2006.201.23:49:20.76#ibcon#*after write, iclass 18, count 2 2006.201.23:49:20.76#ibcon#*before return 0, iclass 18, count 2 2006.201.23:49:20.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:20.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:20.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.23:49:20.76#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:20.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:20.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:20.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:20.88#ibcon#enter wrdev, iclass 18, count 0 2006.201.23:49:20.88#ibcon#first serial, iclass 18, count 0 2006.201.23:49:20.88#ibcon#enter sib2, iclass 18, count 0 2006.201.23:49:20.88#ibcon#flushed, iclass 18, count 0 2006.201.23:49:20.88#ibcon#about to write, iclass 18, count 0 2006.201.23:49:20.88#ibcon#wrote, iclass 18, count 0 2006.201.23:49:20.88#ibcon#about to read 3, iclass 18, count 0 2006.201.23:49:20.90#ibcon#read 3, iclass 18, count 0 2006.201.23:49:20.90#ibcon#about to read 4, iclass 18, count 0 2006.201.23:49:20.90#ibcon#read 4, iclass 18, count 0 2006.201.23:49:20.90#ibcon#about to read 5, iclass 18, count 0 2006.201.23:49:20.90#ibcon#read 5, iclass 18, count 0 2006.201.23:49:20.90#ibcon#about to read 6, iclass 18, count 0 2006.201.23:49:20.90#ibcon#read 6, iclass 18, count 0 2006.201.23:49:20.90#ibcon#end of sib2, iclass 18, count 0 2006.201.23:49:20.90#ibcon#*mode == 0, iclass 18, count 0 2006.201.23:49:20.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.23:49:20.90#ibcon#[25=USB\r\n] 2006.201.23:49:20.90#ibcon#*before write, iclass 18, count 0 2006.201.23:49:20.90#ibcon#enter sib2, iclass 18, count 0 2006.201.23:49:20.90#ibcon#flushed, iclass 18, count 0 2006.201.23:49:20.90#ibcon#about to write, iclass 18, count 0 2006.201.23:49:20.90#ibcon#wrote, iclass 18, count 0 2006.201.23:49:20.90#ibcon#about to read 3, iclass 18, count 0 2006.201.23:49:20.93#ibcon#read 3, iclass 18, count 0 2006.201.23:49:20.93#ibcon#about to read 4, iclass 18, count 0 2006.201.23:49:20.93#ibcon#read 4, iclass 18, count 0 2006.201.23:49:20.93#ibcon#about to read 5, iclass 18, count 0 2006.201.23:49:20.93#ibcon#read 5, iclass 18, count 0 2006.201.23:49:20.93#ibcon#about to read 6, iclass 18, count 0 2006.201.23:49:20.93#ibcon#read 6, iclass 18, count 0 2006.201.23:49:20.93#ibcon#end of sib2, iclass 18, count 0 2006.201.23:49:20.93#ibcon#*after write, iclass 18, count 0 2006.201.23:49:20.93#ibcon#*before return 0, iclass 18, count 0 2006.201.23:49:20.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:20.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:20.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.23:49:20.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.23:49:20.93$vck44/valo=8,884.99 2006.201.23:49:20.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.23:49:20.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.23:49:20.93#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:20.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:20.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:20.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:20.93#ibcon#enter wrdev, iclass 20, count 0 2006.201.23:49:20.93#ibcon#first serial, iclass 20, count 0 2006.201.23:49:20.93#ibcon#enter sib2, iclass 20, count 0 2006.201.23:49:20.93#ibcon#flushed, iclass 20, count 0 2006.201.23:49:20.93#ibcon#about to write, iclass 20, count 0 2006.201.23:49:20.93#ibcon#wrote, iclass 20, count 0 2006.201.23:49:20.93#ibcon#about to read 3, iclass 20, count 0 2006.201.23:49:20.95#ibcon#read 3, iclass 20, count 0 2006.201.23:49:20.95#ibcon#about to read 4, iclass 20, count 0 2006.201.23:49:20.95#ibcon#read 4, iclass 20, count 0 2006.201.23:49:20.95#ibcon#about to read 5, iclass 20, count 0 2006.201.23:49:20.95#ibcon#read 5, iclass 20, count 0 2006.201.23:49:20.95#ibcon#about to read 6, iclass 20, count 0 2006.201.23:49:20.95#ibcon#read 6, iclass 20, count 0 2006.201.23:49:20.95#ibcon#end of sib2, iclass 20, count 0 2006.201.23:49:20.95#ibcon#*mode == 0, iclass 20, count 0 2006.201.23:49:20.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.23:49:20.95#ibcon#[26=FRQ=08,884.99\r\n] 2006.201.23:49:20.95#ibcon#*before write, iclass 20, count 0 2006.201.23:49:20.95#ibcon#enter sib2, iclass 20, count 0 2006.201.23:49:20.95#ibcon#flushed, iclass 20, count 0 2006.201.23:49:20.95#ibcon#about to write, iclass 20, count 0 2006.201.23:49:20.95#ibcon#wrote, iclass 20, count 0 2006.201.23:49:20.95#ibcon#about to read 3, iclass 20, count 0 2006.201.23:49:20.99#ibcon#read 3, iclass 20, count 0 2006.201.23:49:20.99#ibcon#about to read 4, iclass 20, count 0 2006.201.23:49:20.99#ibcon#read 4, iclass 20, count 0 2006.201.23:49:20.99#ibcon#about to read 5, iclass 20, count 0 2006.201.23:49:20.99#ibcon#read 5, iclass 20, count 0 2006.201.23:49:20.99#ibcon#about to read 6, iclass 20, count 0 2006.201.23:49:20.99#ibcon#read 6, iclass 20, count 0 2006.201.23:49:20.99#ibcon#end of sib2, iclass 20, count 0 2006.201.23:49:20.99#ibcon#*after write, iclass 20, count 0 2006.201.23:49:20.99#ibcon#*before return 0, iclass 20, count 0 2006.201.23:49:20.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:20.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:20.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.23:49:20.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.23:49:20.99$vck44/va=8,4 2006.201.23:49:20.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.23:49:20.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.23:49:20.99#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:20.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:21.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:21.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:21.05#ibcon#enter wrdev, iclass 22, count 2 2006.201.23:49:21.05#ibcon#first serial, iclass 22, count 2 2006.201.23:49:21.05#ibcon#enter sib2, iclass 22, count 2 2006.201.23:49:21.05#ibcon#flushed, iclass 22, count 2 2006.201.23:49:21.05#ibcon#about to write, iclass 22, count 2 2006.201.23:49:21.05#ibcon#wrote, iclass 22, count 2 2006.201.23:49:21.05#ibcon#about to read 3, iclass 22, count 2 2006.201.23:49:21.07#ibcon#read 3, iclass 22, count 2 2006.201.23:49:21.07#ibcon#about to read 4, iclass 22, count 2 2006.201.23:49:21.07#ibcon#read 4, iclass 22, count 2 2006.201.23:49:21.07#ibcon#about to read 5, iclass 22, count 2 2006.201.23:49:21.07#ibcon#read 5, iclass 22, count 2 2006.201.23:49:21.07#ibcon#about to read 6, iclass 22, count 2 2006.201.23:49:21.07#ibcon#read 6, iclass 22, count 2 2006.201.23:49:21.07#ibcon#end of sib2, iclass 22, count 2 2006.201.23:49:21.07#ibcon#*mode == 0, iclass 22, count 2 2006.201.23:49:21.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.23:49:21.07#ibcon#[25=AT08-04\r\n] 2006.201.23:49:21.07#ibcon#*before write, iclass 22, count 2 2006.201.23:49:21.07#ibcon#enter sib2, iclass 22, count 2 2006.201.23:49:21.07#ibcon#flushed, iclass 22, count 2 2006.201.23:49:21.07#ibcon#about to write, iclass 22, count 2 2006.201.23:49:21.07#ibcon#wrote, iclass 22, count 2 2006.201.23:49:21.07#ibcon#about to read 3, iclass 22, count 2 2006.201.23:49:21.10#ibcon#read 3, iclass 22, count 2 2006.201.23:49:21.10#ibcon#about to read 4, iclass 22, count 2 2006.201.23:49:21.10#ibcon#read 4, iclass 22, count 2 2006.201.23:49:21.10#ibcon#about to read 5, iclass 22, count 2 2006.201.23:49:21.10#ibcon#read 5, iclass 22, count 2 2006.201.23:49:21.10#ibcon#about to read 6, iclass 22, count 2 2006.201.23:49:21.10#ibcon#read 6, iclass 22, count 2 2006.201.23:49:21.10#ibcon#end of sib2, iclass 22, count 2 2006.201.23:49:21.10#ibcon#*after write, iclass 22, count 2 2006.201.23:49:21.10#ibcon#*before return 0, iclass 22, count 2 2006.201.23:49:21.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:21.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:21.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.23:49:21.10#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:21.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:21.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:21.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:21.22#ibcon#enter wrdev, iclass 22, count 0 2006.201.23:49:21.22#ibcon#first serial, iclass 22, count 0 2006.201.23:49:21.22#ibcon#enter sib2, iclass 22, count 0 2006.201.23:49:21.22#ibcon#flushed, iclass 22, count 0 2006.201.23:49:21.22#ibcon#about to write, iclass 22, count 0 2006.201.23:49:21.22#ibcon#wrote, iclass 22, count 0 2006.201.23:49:21.22#ibcon#about to read 3, iclass 22, count 0 2006.201.23:49:21.24#ibcon#read 3, iclass 22, count 0 2006.201.23:49:21.24#ibcon#about to read 4, iclass 22, count 0 2006.201.23:49:21.24#ibcon#read 4, iclass 22, count 0 2006.201.23:49:21.24#ibcon#about to read 5, iclass 22, count 0 2006.201.23:49:21.24#ibcon#read 5, iclass 22, count 0 2006.201.23:49:21.24#ibcon#about to read 6, iclass 22, count 0 2006.201.23:49:21.24#ibcon#read 6, iclass 22, count 0 2006.201.23:49:21.24#ibcon#end of sib2, iclass 22, count 0 2006.201.23:49:21.24#ibcon#*mode == 0, iclass 22, count 0 2006.201.23:49:21.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.23:49:21.24#ibcon#[25=USB\r\n] 2006.201.23:49:21.24#ibcon#*before write, iclass 22, count 0 2006.201.23:49:21.24#ibcon#enter sib2, iclass 22, count 0 2006.201.23:49:21.24#ibcon#flushed, iclass 22, count 0 2006.201.23:49:21.24#ibcon#about to write, iclass 22, count 0 2006.201.23:49:21.24#ibcon#wrote, iclass 22, count 0 2006.201.23:49:21.24#ibcon#about to read 3, iclass 22, count 0 2006.201.23:49:21.27#ibcon#read 3, iclass 22, count 0 2006.201.23:49:21.27#ibcon#about to read 4, iclass 22, count 0 2006.201.23:49:21.27#ibcon#read 4, iclass 22, count 0 2006.201.23:49:21.27#ibcon#about to read 5, iclass 22, count 0 2006.201.23:49:21.27#ibcon#read 5, iclass 22, count 0 2006.201.23:49:21.27#ibcon#about to read 6, iclass 22, count 0 2006.201.23:49:21.27#ibcon#read 6, iclass 22, count 0 2006.201.23:49:21.27#ibcon#end of sib2, iclass 22, count 0 2006.201.23:49:21.27#ibcon#*after write, iclass 22, count 0 2006.201.23:49:21.27#ibcon#*before return 0, iclass 22, count 0 2006.201.23:49:21.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:21.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:21.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.23:49:21.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.23:49:21.27$vck44/vblo=1,629.99 2006.201.23:49:21.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.23:49:21.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.23:49:21.27#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:21.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:21.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:21.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:21.27#ibcon#enter wrdev, iclass 24, count 0 2006.201.23:49:21.27#ibcon#first serial, iclass 24, count 0 2006.201.23:49:21.27#ibcon#enter sib2, iclass 24, count 0 2006.201.23:49:21.27#ibcon#flushed, iclass 24, count 0 2006.201.23:49:21.27#ibcon#about to write, iclass 24, count 0 2006.201.23:49:21.27#ibcon#wrote, iclass 24, count 0 2006.201.23:49:21.27#ibcon#about to read 3, iclass 24, count 0 2006.201.23:49:21.29#ibcon#read 3, iclass 24, count 0 2006.201.23:49:21.29#ibcon#about to read 4, iclass 24, count 0 2006.201.23:49:21.29#ibcon#read 4, iclass 24, count 0 2006.201.23:49:21.29#ibcon#about to read 5, iclass 24, count 0 2006.201.23:49:21.29#ibcon#read 5, iclass 24, count 0 2006.201.23:49:21.29#ibcon#about to read 6, iclass 24, count 0 2006.201.23:49:21.29#ibcon#read 6, iclass 24, count 0 2006.201.23:49:21.29#ibcon#end of sib2, iclass 24, count 0 2006.201.23:49:21.29#ibcon#*mode == 0, iclass 24, count 0 2006.201.23:49:21.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.23:49:21.29#ibcon#[28=FRQ=01,629.99\r\n] 2006.201.23:49:21.29#ibcon#*before write, iclass 24, count 0 2006.201.23:49:21.29#ibcon#enter sib2, iclass 24, count 0 2006.201.23:49:21.29#ibcon#flushed, iclass 24, count 0 2006.201.23:49:21.29#ibcon#about to write, iclass 24, count 0 2006.201.23:49:21.29#ibcon#wrote, iclass 24, count 0 2006.201.23:49:21.29#ibcon#about to read 3, iclass 24, count 0 2006.201.23:49:21.33#ibcon#read 3, iclass 24, count 0 2006.201.23:49:21.33#ibcon#about to read 4, iclass 24, count 0 2006.201.23:49:21.33#ibcon#read 4, iclass 24, count 0 2006.201.23:49:21.33#ibcon#about to read 5, iclass 24, count 0 2006.201.23:49:21.33#ibcon#read 5, iclass 24, count 0 2006.201.23:49:21.33#ibcon#about to read 6, iclass 24, count 0 2006.201.23:49:21.33#ibcon#read 6, iclass 24, count 0 2006.201.23:49:21.33#ibcon#end of sib2, iclass 24, count 0 2006.201.23:49:21.33#ibcon#*after write, iclass 24, count 0 2006.201.23:49:21.33#ibcon#*before return 0, iclass 24, count 0 2006.201.23:49:21.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:21.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:21.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.23:49:21.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.23:49:21.33$vck44/vb=1,4 2006.201.23:49:21.33#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.201.23:49:21.33#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.201.23:49:21.33#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:21.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:49:21.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:49:21.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:49:21.33#ibcon#enter wrdev, iclass 26, count 2 2006.201.23:49:21.33#ibcon#first serial, iclass 26, count 2 2006.201.23:49:21.33#ibcon#enter sib2, iclass 26, count 2 2006.201.23:49:21.33#ibcon#flushed, iclass 26, count 2 2006.201.23:49:21.33#ibcon#about to write, iclass 26, count 2 2006.201.23:49:21.33#ibcon#wrote, iclass 26, count 2 2006.201.23:49:21.33#ibcon#about to read 3, iclass 26, count 2 2006.201.23:49:21.35#ibcon#read 3, iclass 26, count 2 2006.201.23:49:21.35#ibcon#about to read 4, iclass 26, count 2 2006.201.23:49:21.35#ibcon#read 4, iclass 26, count 2 2006.201.23:49:21.35#ibcon#about to read 5, iclass 26, count 2 2006.201.23:49:21.35#ibcon#read 5, iclass 26, count 2 2006.201.23:49:21.35#ibcon#about to read 6, iclass 26, count 2 2006.201.23:49:21.35#ibcon#read 6, iclass 26, count 2 2006.201.23:49:21.35#ibcon#end of sib2, iclass 26, count 2 2006.201.23:49:21.35#ibcon#*mode == 0, iclass 26, count 2 2006.201.23:49:21.35#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.201.23:49:21.35#ibcon#[27=AT01-04\r\n] 2006.201.23:49:21.35#ibcon#*before write, iclass 26, count 2 2006.201.23:49:21.35#ibcon#enter sib2, iclass 26, count 2 2006.201.23:49:21.35#ibcon#flushed, iclass 26, count 2 2006.201.23:49:21.35#ibcon#about to write, iclass 26, count 2 2006.201.23:49:21.35#ibcon#wrote, iclass 26, count 2 2006.201.23:49:21.35#ibcon#about to read 3, iclass 26, count 2 2006.201.23:49:21.38#ibcon#read 3, iclass 26, count 2 2006.201.23:49:21.38#ibcon#about to read 4, iclass 26, count 2 2006.201.23:49:21.38#ibcon#read 4, iclass 26, count 2 2006.201.23:49:21.38#ibcon#about to read 5, iclass 26, count 2 2006.201.23:49:21.38#ibcon#read 5, iclass 26, count 2 2006.201.23:49:21.38#ibcon#about to read 6, iclass 26, count 2 2006.201.23:49:21.38#ibcon#read 6, iclass 26, count 2 2006.201.23:49:21.38#ibcon#end of sib2, iclass 26, count 2 2006.201.23:49:21.38#ibcon#*after write, iclass 26, count 2 2006.201.23:49:21.38#ibcon#*before return 0, iclass 26, count 2 2006.201.23:49:21.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:49:21.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.201.23:49:21.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.201.23:49:21.38#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:21.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:49:21.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:49:21.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:49:21.50#ibcon#enter wrdev, iclass 26, count 0 2006.201.23:49:21.50#ibcon#first serial, iclass 26, count 0 2006.201.23:49:21.50#ibcon#enter sib2, iclass 26, count 0 2006.201.23:49:21.50#ibcon#flushed, iclass 26, count 0 2006.201.23:49:21.50#ibcon#about to write, iclass 26, count 0 2006.201.23:49:21.50#ibcon#wrote, iclass 26, count 0 2006.201.23:49:21.50#ibcon#about to read 3, iclass 26, count 0 2006.201.23:49:21.52#ibcon#read 3, iclass 26, count 0 2006.201.23:49:21.52#ibcon#about to read 4, iclass 26, count 0 2006.201.23:49:21.52#ibcon#read 4, iclass 26, count 0 2006.201.23:49:21.52#ibcon#about to read 5, iclass 26, count 0 2006.201.23:49:21.52#ibcon#read 5, iclass 26, count 0 2006.201.23:49:21.52#ibcon#about to read 6, iclass 26, count 0 2006.201.23:49:21.52#ibcon#read 6, iclass 26, count 0 2006.201.23:49:21.52#ibcon#end of sib2, iclass 26, count 0 2006.201.23:49:21.52#ibcon#*mode == 0, iclass 26, count 0 2006.201.23:49:21.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.23:49:21.52#ibcon#[27=USB\r\n] 2006.201.23:49:21.52#ibcon#*before write, iclass 26, count 0 2006.201.23:49:21.52#ibcon#enter sib2, iclass 26, count 0 2006.201.23:49:21.52#ibcon#flushed, iclass 26, count 0 2006.201.23:49:21.52#ibcon#about to write, iclass 26, count 0 2006.201.23:49:21.52#ibcon#wrote, iclass 26, count 0 2006.201.23:49:21.52#ibcon#about to read 3, iclass 26, count 0 2006.201.23:49:21.55#ibcon#read 3, iclass 26, count 0 2006.201.23:49:21.55#ibcon#about to read 4, iclass 26, count 0 2006.201.23:49:21.55#ibcon#read 4, iclass 26, count 0 2006.201.23:49:21.55#ibcon#about to read 5, iclass 26, count 0 2006.201.23:49:21.55#ibcon#read 5, iclass 26, count 0 2006.201.23:49:21.55#ibcon#about to read 6, iclass 26, count 0 2006.201.23:49:21.55#ibcon#read 6, iclass 26, count 0 2006.201.23:49:21.55#ibcon#end of sib2, iclass 26, count 0 2006.201.23:49:21.55#ibcon#*after write, iclass 26, count 0 2006.201.23:49:21.55#ibcon#*before return 0, iclass 26, count 0 2006.201.23:49:21.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:49:21.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.201.23:49:21.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.23:49:21.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.23:49:21.55$vck44/vblo=2,634.99 2006.201.23:49:21.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.201.23:49:21.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.201.23:49:21.55#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:21.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:21.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:21.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:21.55#ibcon#enter wrdev, iclass 28, count 0 2006.201.23:49:21.55#ibcon#first serial, iclass 28, count 0 2006.201.23:49:21.55#ibcon#enter sib2, iclass 28, count 0 2006.201.23:49:21.55#ibcon#flushed, iclass 28, count 0 2006.201.23:49:21.55#ibcon#about to write, iclass 28, count 0 2006.201.23:49:21.55#ibcon#wrote, iclass 28, count 0 2006.201.23:49:21.55#ibcon#about to read 3, iclass 28, count 0 2006.201.23:49:21.57#ibcon#read 3, iclass 28, count 0 2006.201.23:49:21.57#ibcon#about to read 4, iclass 28, count 0 2006.201.23:49:21.57#ibcon#read 4, iclass 28, count 0 2006.201.23:49:21.57#ibcon#about to read 5, iclass 28, count 0 2006.201.23:49:21.57#ibcon#read 5, iclass 28, count 0 2006.201.23:49:21.57#ibcon#about to read 6, iclass 28, count 0 2006.201.23:49:21.57#ibcon#read 6, iclass 28, count 0 2006.201.23:49:21.57#ibcon#end of sib2, iclass 28, count 0 2006.201.23:49:21.57#ibcon#*mode == 0, iclass 28, count 0 2006.201.23:49:21.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.201.23:49:21.57#ibcon#[28=FRQ=02,634.99\r\n] 2006.201.23:49:21.57#ibcon#*before write, iclass 28, count 0 2006.201.23:49:21.57#ibcon#enter sib2, iclass 28, count 0 2006.201.23:49:21.57#ibcon#flushed, iclass 28, count 0 2006.201.23:49:21.57#ibcon#about to write, iclass 28, count 0 2006.201.23:49:21.57#ibcon#wrote, iclass 28, count 0 2006.201.23:49:21.57#ibcon#about to read 3, iclass 28, count 0 2006.201.23:49:21.61#ibcon#read 3, iclass 28, count 0 2006.201.23:49:21.61#ibcon#about to read 4, iclass 28, count 0 2006.201.23:49:21.61#ibcon#read 4, iclass 28, count 0 2006.201.23:49:21.61#ibcon#about to read 5, iclass 28, count 0 2006.201.23:49:21.61#ibcon#read 5, iclass 28, count 0 2006.201.23:49:21.61#ibcon#about to read 6, iclass 28, count 0 2006.201.23:49:21.61#ibcon#read 6, iclass 28, count 0 2006.201.23:49:21.61#ibcon#end of sib2, iclass 28, count 0 2006.201.23:49:21.61#ibcon#*after write, iclass 28, count 0 2006.201.23:49:21.61#ibcon#*before return 0, iclass 28, count 0 2006.201.23:49:21.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:21.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.201.23:49:21.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.201.23:49:21.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.201.23:49:21.61$vck44/vb=2,5 2006.201.23:49:21.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.201.23:49:21.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.201.23:49:21.61#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:21.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:21.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:21.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:21.67#ibcon#enter wrdev, iclass 30, count 2 2006.201.23:49:21.67#ibcon#first serial, iclass 30, count 2 2006.201.23:49:21.67#ibcon#enter sib2, iclass 30, count 2 2006.201.23:49:21.67#ibcon#flushed, iclass 30, count 2 2006.201.23:49:21.67#ibcon#about to write, iclass 30, count 2 2006.201.23:49:21.67#ibcon#wrote, iclass 30, count 2 2006.201.23:49:21.67#ibcon#about to read 3, iclass 30, count 2 2006.201.23:49:21.69#ibcon#read 3, iclass 30, count 2 2006.201.23:49:21.69#ibcon#about to read 4, iclass 30, count 2 2006.201.23:49:21.69#ibcon#read 4, iclass 30, count 2 2006.201.23:49:21.69#ibcon#about to read 5, iclass 30, count 2 2006.201.23:49:21.69#ibcon#read 5, iclass 30, count 2 2006.201.23:49:21.69#ibcon#about to read 6, iclass 30, count 2 2006.201.23:49:21.69#ibcon#read 6, iclass 30, count 2 2006.201.23:49:21.69#ibcon#end of sib2, iclass 30, count 2 2006.201.23:49:21.69#ibcon#*mode == 0, iclass 30, count 2 2006.201.23:49:21.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.201.23:49:21.69#ibcon#[27=AT02-05\r\n] 2006.201.23:49:21.69#ibcon#*before write, iclass 30, count 2 2006.201.23:49:21.69#ibcon#enter sib2, iclass 30, count 2 2006.201.23:49:21.69#ibcon#flushed, iclass 30, count 2 2006.201.23:49:21.69#ibcon#about to write, iclass 30, count 2 2006.201.23:49:21.69#ibcon#wrote, iclass 30, count 2 2006.201.23:49:21.69#ibcon#about to read 3, iclass 30, count 2 2006.201.23:49:21.69#abcon#<5=/01 0.8 2.1 20.361001001.4\r\n> 2006.201.23:49:21.71#abcon#{5=INTERFACE CLEAR} 2006.201.23:49:21.72#ibcon#read 3, iclass 30, count 2 2006.201.23:49:21.72#ibcon#about to read 4, iclass 30, count 2 2006.201.23:49:21.72#ibcon#read 4, iclass 30, count 2 2006.201.23:49:21.72#ibcon#about to read 5, iclass 30, count 2 2006.201.23:49:21.72#ibcon#read 5, iclass 30, count 2 2006.201.23:49:21.72#ibcon#about to read 6, iclass 30, count 2 2006.201.23:49:21.72#ibcon#read 6, iclass 30, count 2 2006.201.23:49:21.72#ibcon#end of sib2, iclass 30, count 2 2006.201.23:49:21.72#ibcon#*after write, iclass 30, count 2 2006.201.23:49:21.72#ibcon#*before return 0, iclass 30, count 2 2006.201.23:49:21.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:21.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.201.23:49:21.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.201.23:49:21.72#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:21.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:21.77#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:49:21.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:21.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:21.84#ibcon#enter wrdev, iclass 30, count 0 2006.201.23:49:21.84#ibcon#first serial, iclass 30, count 0 2006.201.23:49:21.84#ibcon#enter sib2, iclass 30, count 0 2006.201.23:49:21.84#ibcon#flushed, iclass 30, count 0 2006.201.23:49:21.84#ibcon#about to write, iclass 30, count 0 2006.201.23:49:21.84#ibcon#wrote, iclass 30, count 0 2006.201.23:49:21.84#ibcon#about to read 3, iclass 30, count 0 2006.201.23:49:21.86#ibcon#read 3, iclass 30, count 0 2006.201.23:49:21.86#ibcon#about to read 4, iclass 30, count 0 2006.201.23:49:21.86#ibcon#read 4, iclass 30, count 0 2006.201.23:49:21.86#ibcon#about to read 5, iclass 30, count 0 2006.201.23:49:21.86#ibcon#read 5, iclass 30, count 0 2006.201.23:49:21.86#ibcon#about to read 6, iclass 30, count 0 2006.201.23:49:21.86#ibcon#read 6, iclass 30, count 0 2006.201.23:49:21.86#ibcon#end of sib2, iclass 30, count 0 2006.201.23:49:21.86#ibcon#*mode == 0, iclass 30, count 0 2006.201.23:49:21.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.201.23:49:21.86#ibcon#[27=USB\r\n] 2006.201.23:49:21.86#ibcon#*before write, iclass 30, count 0 2006.201.23:49:21.86#ibcon#enter sib2, iclass 30, count 0 2006.201.23:49:21.86#ibcon#flushed, iclass 30, count 0 2006.201.23:49:21.86#ibcon#about to write, iclass 30, count 0 2006.201.23:49:21.86#ibcon#wrote, iclass 30, count 0 2006.201.23:49:21.86#ibcon#about to read 3, iclass 30, count 0 2006.201.23:49:21.89#ibcon#read 3, iclass 30, count 0 2006.201.23:49:21.89#ibcon#about to read 4, iclass 30, count 0 2006.201.23:49:21.89#ibcon#read 4, iclass 30, count 0 2006.201.23:49:21.89#ibcon#about to read 5, iclass 30, count 0 2006.201.23:49:21.89#ibcon#read 5, iclass 30, count 0 2006.201.23:49:21.89#ibcon#about to read 6, iclass 30, count 0 2006.201.23:49:21.89#ibcon#read 6, iclass 30, count 0 2006.201.23:49:21.89#ibcon#end of sib2, iclass 30, count 0 2006.201.23:49:21.89#ibcon#*after write, iclass 30, count 0 2006.201.23:49:21.89#ibcon#*before return 0, iclass 30, count 0 2006.201.23:49:21.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:21.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.201.23:49:21.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.201.23:49:21.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.201.23:49:21.89$vck44/vblo=3,649.99 2006.201.23:49:21.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.201.23:49:21.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.201.23:49:21.89#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:21.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:21.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:21.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:21.89#ibcon#enter wrdev, iclass 36, count 0 2006.201.23:49:21.89#ibcon#first serial, iclass 36, count 0 2006.201.23:49:21.89#ibcon#enter sib2, iclass 36, count 0 2006.201.23:49:21.89#ibcon#flushed, iclass 36, count 0 2006.201.23:49:21.89#ibcon#about to write, iclass 36, count 0 2006.201.23:49:21.89#ibcon#wrote, iclass 36, count 0 2006.201.23:49:21.89#ibcon#about to read 3, iclass 36, count 0 2006.201.23:49:21.91#ibcon#read 3, iclass 36, count 0 2006.201.23:49:21.91#ibcon#about to read 4, iclass 36, count 0 2006.201.23:49:21.91#ibcon#read 4, iclass 36, count 0 2006.201.23:49:21.91#ibcon#about to read 5, iclass 36, count 0 2006.201.23:49:21.91#ibcon#read 5, iclass 36, count 0 2006.201.23:49:21.91#ibcon#about to read 6, iclass 36, count 0 2006.201.23:49:21.91#ibcon#read 6, iclass 36, count 0 2006.201.23:49:21.91#ibcon#end of sib2, iclass 36, count 0 2006.201.23:49:21.91#ibcon#*mode == 0, iclass 36, count 0 2006.201.23:49:21.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.201.23:49:21.91#ibcon#[28=FRQ=03,649.99\r\n] 2006.201.23:49:21.91#ibcon#*before write, iclass 36, count 0 2006.201.23:49:21.91#ibcon#enter sib2, iclass 36, count 0 2006.201.23:49:21.91#ibcon#flushed, iclass 36, count 0 2006.201.23:49:21.91#ibcon#about to write, iclass 36, count 0 2006.201.23:49:21.91#ibcon#wrote, iclass 36, count 0 2006.201.23:49:21.91#ibcon#about to read 3, iclass 36, count 0 2006.201.23:49:21.95#ibcon#read 3, iclass 36, count 0 2006.201.23:49:21.95#ibcon#about to read 4, iclass 36, count 0 2006.201.23:49:21.95#ibcon#read 4, iclass 36, count 0 2006.201.23:49:21.95#ibcon#about to read 5, iclass 36, count 0 2006.201.23:49:21.95#ibcon#read 5, iclass 36, count 0 2006.201.23:49:21.95#ibcon#about to read 6, iclass 36, count 0 2006.201.23:49:21.95#ibcon#read 6, iclass 36, count 0 2006.201.23:49:21.95#ibcon#end of sib2, iclass 36, count 0 2006.201.23:49:21.95#ibcon#*after write, iclass 36, count 0 2006.201.23:49:21.95#ibcon#*before return 0, iclass 36, count 0 2006.201.23:49:21.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:21.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.201.23:49:21.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.201.23:49:21.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.201.23:49:21.95$vck44/vb=3,4 2006.201.23:49:21.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.201.23:49:21.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.201.23:49:21.95#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:21.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:22.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:22.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:22.01#ibcon#enter wrdev, iclass 38, count 2 2006.201.23:49:22.01#ibcon#first serial, iclass 38, count 2 2006.201.23:49:22.01#ibcon#enter sib2, iclass 38, count 2 2006.201.23:49:22.01#ibcon#flushed, iclass 38, count 2 2006.201.23:49:22.01#ibcon#about to write, iclass 38, count 2 2006.201.23:49:22.01#ibcon#wrote, iclass 38, count 2 2006.201.23:49:22.01#ibcon#about to read 3, iclass 38, count 2 2006.201.23:49:22.03#ibcon#read 3, iclass 38, count 2 2006.201.23:49:22.03#ibcon#about to read 4, iclass 38, count 2 2006.201.23:49:22.03#ibcon#read 4, iclass 38, count 2 2006.201.23:49:22.03#ibcon#about to read 5, iclass 38, count 2 2006.201.23:49:22.03#ibcon#read 5, iclass 38, count 2 2006.201.23:49:22.03#ibcon#about to read 6, iclass 38, count 2 2006.201.23:49:22.03#ibcon#read 6, iclass 38, count 2 2006.201.23:49:22.03#ibcon#end of sib2, iclass 38, count 2 2006.201.23:49:22.03#ibcon#*mode == 0, iclass 38, count 2 2006.201.23:49:22.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.201.23:49:22.03#ibcon#[27=AT03-04\r\n] 2006.201.23:49:22.03#ibcon#*before write, iclass 38, count 2 2006.201.23:49:22.03#ibcon#enter sib2, iclass 38, count 2 2006.201.23:49:22.03#ibcon#flushed, iclass 38, count 2 2006.201.23:49:22.03#ibcon#about to write, iclass 38, count 2 2006.201.23:49:22.03#ibcon#wrote, iclass 38, count 2 2006.201.23:49:22.03#ibcon#about to read 3, iclass 38, count 2 2006.201.23:49:22.06#ibcon#read 3, iclass 38, count 2 2006.201.23:49:22.06#ibcon#about to read 4, iclass 38, count 2 2006.201.23:49:22.06#ibcon#read 4, iclass 38, count 2 2006.201.23:49:22.06#ibcon#about to read 5, iclass 38, count 2 2006.201.23:49:22.06#ibcon#read 5, iclass 38, count 2 2006.201.23:49:22.06#ibcon#about to read 6, iclass 38, count 2 2006.201.23:49:22.06#ibcon#read 6, iclass 38, count 2 2006.201.23:49:22.06#ibcon#end of sib2, iclass 38, count 2 2006.201.23:49:22.06#ibcon#*after write, iclass 38, count 2 2006.201.23:49:22.06#ibcon#*before return 0, iclass 38, count 2 2006.201.23:49:22.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:22.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.201.23:49:22.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.201.23:49:22.06#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:22.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:22.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:22.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:22.18#ibcon#enter wrdev, iclass 38, count 0 2006.201.23:49:22.18#ibcon#first serial, iclass 38, count 0 2006.201.23:49:22.18#ibcon#enter sib2, iclass 38, count 0 2006.201.23:49:22.18#ibcon#flushed, iclass 38, count 0 2006.201.23:49:22.18#ibcon#about to write, iclass 38, count 0 2006.201.23:49:22.18#ibcon#wrote, iclass 38, count 0 2006.201.23:49:22.18#ibcon#about to read 3, iclass 38, count 0 2006.201.23:49:22.20#ibcon#read 3, iclass 38, count 0 2006.201.23:49:22.20#ibcon#about to read 4, iclass 38, count 0 2006.201.23:49:22.20#ibcon#read 4, iclass 38, count 0 2006.201.23:49:22.20#ibcon#about to read 5, iclass 38, count 0 2006.201.23:49:22.20#ibcon#read 5, iclass 38, count 0 2006.201.23:49:22.20#ibcon#about to read 6, iclass 38, count 0 2006.201.23:49:22.20#ibcon#read 6, iclass 38, count 0 2006.201.23:49:22.20#ibcon#end of sib2, iclass 38, count 0 2006.201.23:49:22.20#ibcon#*mode == 0, iclass 38, count 0 2006.201.23:49:22.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.201.23:49:22.20#ibcon#[27=USB\r\n] 2006.201.23:49:22.20#ibcon#*before write, iclass 38, count 0 2006.201.23:49:22.20#ibcon#enter sib2, iclass 38, count 0 2006.201.23:49:22.20#ibcon#flushed, iclass 38, count 0 2006.201.23:49:22.20#ibcon#about to write, iclass 38, count 0 2006.201.23:49:22.20#ibcon#wrote, iclass 38, count 0 2006.201.23:49:22.20#ibcon#about to read 3, iclass 38, count 0 2006.201.23:49:22.23#ibcon#read 3, iclass 38, count 0 2006.201.23:49:22.23#ibcon#about to read 4, iclass 38, count 0 2006.201.23:49:22.23#ibcon#read 4, iclass 38, count 0 2006.201.23:49:22.23#ibcon#about to read 5, iclass 38, count 0 2006.201.23:49:22.23#ibcon#read 5, iclass 38, count 0 2006.201.23:49:22.23#ibcon#about to read 6, iclass 38, count 0 2006.201.23:49:22.23#ibcon#read 6, iclass 38, count 0 2006.201.23:49:22.23#ibcon#end of sib2, iclass 38, count 0 2006.201.23:49:22.23#ibcon#*after write, iclass 38, count 0 2006.201.23:49:22.23#ibcon#*before return 0, iclass 38, count 0 2006.201.23:49:22.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:22.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.201.23:49:22.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.201.23:49:22.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.201.23:49:22.23$vck44/vblo=4,679.99 2006.201.23:49:22.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.201.23:49:22.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.201.23:49:22.23#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:22.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:22.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:22.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:22.23#ibcon#enter wrdev, iclass 40, count 0 2006.201.23:49:22.23#ibcon#first serial, iclass 40, count 0 2006.201.23:49:22.23#ibcon#enter sib2, iclass 40, count 0 2006.201.23:49:22.23#ibcon#flushed, iclass 40, count 0 2006.201.23:49:22.23#ibcon#about to write, iclass 40, count 0 2006.201.23:49:22.23#ibcon#wrote, iclass 40, count 0 2006.201.23:49:22.23#ibcon#about to read 3, iclass 40, count 0 2006.201.23:49:22.25#ibcon#read 3, iclass 40, count 0 2006.201.23:49:22.25#ibcon#about to read 4, iclass 40, count 0 2006.201.23:49:22.25#ibcon#read 4, iclass 40, count 0 2006.201.23:49:22.25#ibcon#about to read 5, iclass 40, count 0 2006.201.23:49:22.25#ibcon#read 5, iclass 40, count 0 2006.201.23:49:22.25#ibcon#about to read 6, iclass 40, count 0 2006.201.23:49:22.25#ibcon#read 6, iclass 40, count 0 2006.201.23:49:22.25#ibcon#end of sib2, iclass 40, count 0 2006.201.23:49:22.25#ibcon#*mode == 0, iclass 40, count 0 2006.201.23:49:22.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.201.23:49:22.25#ibcon#[28=FRQ=04,679.99\r\n] 2006.201.23:49:22.25#ibcon#*before write, iclass 40, count 0 2006.201.23:49:22.25#ibcon#enter sib2, iclass 40, count 0 2006.201.23:49:22.25#ibcon#flushed, iclass 40, count 0 2006.201.23:49:22.25#ibcon#about to write, iclass 40, count 0 2006.201.23:49:22.25#ibcon#wrote, iclass 40, count 0 2006.201.23:49:22.25#ibcon#about to read 3, iclass 40, count 0 2006.201.23:49:22.29#ibcon#read 3, iclass 40, count 0 2006.201.23:49:22.29#ibcon#about to read 4, iclass 40, count 0 2006.201.23:49:22.29#ibcon#read 4, iclass 40, count 0 2006.201.23:49:22.29#ibcon#about to read 5, iclass 40, count 0 2006.201.23:49:22.29#ibcon#read 5, iclass 40, count 0 2006.201.23:49:22.29#ibcon#about to read 6, iclass 40, count 0 2006.201.23:49:22.29#ibcon#read 6, iclass 40, count 0 2006.201.23:49:22.29#ibcon#end of sib2, iclass 40, count 0 2006.201.23:49:22.29#ibcon#*after write, iclass 40, count 0 2006.201.23:49:22.29#ibcon#*before return 0, iclass 40, count 0 2006.201.23:49:22.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:22.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.201.23:49:22.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.201.23:49:22.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.201.23:49:22.29$vck44/vb=4,5 2006.201.23:49:22.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.201.23:49:22.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.201.23:49:22.29#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:22.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:22.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:22.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:22.35#ibcon#enter wrdev, iclass 4, count 2 2006.201.23:49:22.35#ibcon#first serial, iclass 4, count 2 2006.201.23:49:22.35#ibcon#enter sib2, iclass 4, count 2 2006.201.23:49:22.35#ibcon#flushed, iclass 4, count 2 2006.201.23:49:22.35#ibcon#about to write, iclass 4, count 2 2006.201.23:49:22.35#ibcon#wrote, iclass 4, count 2 2006.201.23:49:22.35#ibcon#about to read 3, iclass 4, count 2 2006.201.23:49:22.37#ibcon#read 3, iclass 4, count 2 2006.201.23:49:22.37#ibcon#about to read 4, iclass 4, count 2 2006.201.23:49:22.37#ibcon#read 4, iclass 4, count 2 2006.201.23:49:22.37#ibcon#about to read 5, iclass 4, count 2 2006.201.23:49:22.37#ibcon#read 5, iclass 4, count 2 2006.201.23:49:22.37#ibcon#about to read 6, iclass 4, count 2 2006.201.23:49:22.37#ibcon#read 6, iclass 4, count 2 2006.201.23:49:22.37#ibcon#end of sib2, iclass 4, count 2 2006.201.23:49:22.37#ibcon#*mode == 0, iclass 4, count 2 2006.201.23:49:22.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.201.23:49:22.37#ibcon#[27=AT04-05\r\n] 2006.201.23:49:22.37#ibcon#*before write, iclass 4, count 2 2006.201.23:49:22.37#ibcon#enter sib2, iclass 4, count 2 2006.201.23:49:22.37#ibcon#flushed, iclass 4, count 2 2006.201.23:49:22.37#ibcon#about to write, iclass 4, count 2 2006.201.23:49:22.37#ibcon#wrote, iclass 4, count 2 2006.201.23:49:22.37#ibcon#about to read 3, iclass 4, count 2 2006.201.23:49:22.40#ibcon#read 3, iclass 4, count 2 2006.201.23:49:22.40#ibcon#about to read 4, iclass 4, count 2 2006.201.23:49:22.40#ibcon#read 4, iclass 4, count 2 2006.201.23:49:22.40#ibcon#about to read 5, iclass 4, count 2 2006.201.23:49:22.40#ibcon#read 5, iclass 4, count 2 2006.201.23:49:22.40#ibcon#about to read 6, iclass 4, count 2 2006.201.23:49:22.40#ibcon#read 6, iclass 4, count 2 2006.201.23:49:22.40#ibcon#end of sib2, iclass 4, count 2 2006.201.23:49:22.40#ibcon#*after write, iclass 4, count 2 2006.201.23:49:22.40#ibcon#*before return 0, iclass 4, count 2 2006.201.23:49:22.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:22.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.201.23:49:22.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.201.23:49:22.40#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:22.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:22.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:22.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:22.52#ibcon#enter wrdev, iclass 4, count 0 2006.201.23:49:22.52#ibcon#first serial, iclass 4, count 0 2006.201.23:49:22.52#ibcon#enter sib2, iclass 4, count 0 2006.201.23:49:22.52#ibcon#flushed, iclass 4, count 0 2006.201.23:49:22.52#ibcon#about to write, iclass 4, count 0 2006.201.23:49:22.52#ibcon#wrote, iclass 4, count 0 2006.201.23:49:22.52#ibcon#about to read 3, iclass 4, count 0 2006.201.23:49:22.54#ibcon#read 3, iclass 4, count 0 2006.201.23:49:22.54#ibcon#about to read 4, iclass 4, count 0 2006.201.23:49:22.54#ibcon#read 4, iclass 4, count 0 2006.201.23:49:22.54#ibcon#about to read 5, iclass 4, count 0 2006.201.23:49:22.54#ibcon#read 5, iclass 4, count 0 2006.201.23:49:22.54#ibcon#about to read 6, iclass 4, count 0 2006.201.23:49:22.54#ibcon#read 6, iclass 4, count 0 2006.201.23:49:22.54#ibcon#end of sib2, iclass 4, count 0 2006.201.23:49:22.54#ibcon#*mode == 0, iclass 4, count 0 2006.201.23:49:22.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.201.23:49:22.54#ibcon#[27=USB\r\n] 2006.201.23:49:22.54#ibcon#*before write, iclass 4, count 0 2006.201.23:49:22.54#ibcon#enter sib2, iclass 4, count 0 2006.201.23:49:22.54#ibcon#flushed, iclass 4, count 0 2006.201.23:49:22.54#ibcon#about to write, iclass 4, count 0 2006.201.23:49:22.54#ibcon#wrote, iclass 4, count 0 2006.201.23:49:22.54#ibcon#about to read 3, iclass 4, count 0 2006.201.23:49:22.57#ibcon#read 3, iclass 4, count 0 2006.201.23:49:22.57#ibcon#about to read 4, iclass 4, count 0 2006.201.23:49:22.57#ibcon#read 4, iclass 4, count 0 2006.201.23:49:22.57#ibcon#about to read 5, iclass 4, count 0 2006.201.23:49:22.57#ibcon#read 5, iclass 4, count 0 2006.201.23:49:22.57#ibcon#about to read 6, iclass 4, count 0 2006.201.23:49:22.57#ibcon#read 6, iclass 4, count 0 2006.201.23:49:22.57#ibcon#end of sib2, iclass 4, count 0 2006.201.23:49:22.57#ibcon#*after write, iclass 4, count 0 2006.201.23:49:22.57#ibcon#*before return 0, iclass 4, count 0 2006.201.23:49:22.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:22.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.201.23:49:22.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.201.23:49:22.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.201.23:49:22.57$vck44/vblo=5,709.99 2006.201.23:49:22.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.201.23:49:22.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.201.23:49:22.57#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:22.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:22.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:22.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:22.57#ibcon#enter wrdev, iclass 6, count 0 2006.201.23:49:22.57#ibcon#first serial, iclass 6, count 0 2006.201.23:49:22.57#ibcon#enter sib2, iclass 6, count 0 2006.201.23:49:22.57#ibcon#flushed, iclass 6, count 0 2006.201.23:49:22.57#ibcon#about to write, iclass 6, count 0 2006.201.23:49:22.57#ibcon#wrote, iclass 6, count 0 2006.201.23:49:22.57#ibcon#about to read 3, iclass 6, count 0 2006.201.23:49:22.59#ibcon#read 3, iclass 6, count 0 2006.201.23:49:22.59#ibcon#about to read 4, iclass 6, count 0 2006.201.23:49:22.59#ibcon#read 4, iclass 6, count 0 2006.201.23:49:22.59#ibcon#about to read 5, iclass 6, count 0 2006.201.23:49:22.59#ibcon#read 5, iclass 6, count 0 2006.201.23:49:22.59#ibcon#about to read 6, iclass 6, count 0 2006.201.23:49:22.59#ibcon#read 6, iclass 6, count 0 2006.201.23:49:22.59#ibcon#end of sib2, iclass 6, count 0 2006.201.23:49:22.59#ibcon#*mode == 0, iclass 6, count 0 2006.201.23:49:22.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.201.23:49:22.59#ibcon#[28=FRQ=05,709.99\r\n] 2006.201.23:49:22.59#ibcon#*before write, iclass 6, count 0 2006.201.23:49:22.59#ibcon#enter sib2, iclass 6, count 0 2006.201.23:49:22.59#ibcon#flushed, iclass 6, count 0 2006.201.23:49:22.59#ibcon#about to write, iclass 6, count 0 2006.201.23:49:22.59#ibcon#wrote, iclass 6, count 0 2006.201.23:49:22.59#ibcon#about to read 3, iclass 6, count 0 2006.201.23:49:22.63#ibcon#read 3, iclass 6, count 0 2006.201.23:49:22.63#ibcon#about to read 4, iclass 6, count 0 2006.201.23:49:22.63#ibcon#read 4, iclass 6, count 0 2006.201.23:49:22.63#ibcon#about to read 5, iclass 6, count 0 2006.201.23:49:22.63#ibcon#read 5, iclass 6, count 0 2006.201.23:49:22.63#ibcon#about to read 6, iclass 6, count 0 2006.201.23:49:22.63#ibcon#read 6, iclass 6, count 0 2006.201.23:49:22.63#ibcon#end of sib2, iclass 6, count 0 2006.201.23:49:22.63#ibcon#*after write, iclass 6, count 0 2006.201.23:49:22.63#ibcon#*before return 0, iclass 6, count 0 2006.201.23:49:22.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:22.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.201.23:49:22.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.201.23:49:22.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.201.23:49:22.63$vck44/vb=5,4 2006.201.23:49:22.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.201.23:49:22.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.201.23:49:22.63#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:22.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:22.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:22.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:22.69#ibcon#enter wrdev, iclass 10, count 2 2006.201.23:49:22.69#ibcon#first serial, iclass 10, count 2 2006.201.23:49:22.69#ibcon#enter sib2, iclass 10, count 2 2006.201.23:49:22.69#ibcon#flushed, iclass 10, count 2 2006.201.23:49:22.69#ibcon#about to write, iclass 10, count 2 2006.201.23:49:22.69#ibcon#wrote, iclass 10, count 2 2006.201.23:49:22.69#ibcon#about to read 3, iclass 10, count 2 2006.201.23:49:22.71#ibcon#read 3, iclass 10, count 2 2006.201.23:49:22.71#ibcon#about to read 4, iclass 10, count 2 2006.201.23:49:22.71#ibcon#read 4, iclass 10, count 2 2006.201.23:49:22.71#ibcon#about to read 5, iclass 10, count 2 2006.201.23:49:22.71#ibcon#read 5, iclass 10, count 2 2006.201.23:49:22.71#ibcon#about to read 6, iclass 10, count 2 2006.201.23:49:22.71#ibcon#read 6, iclass 10, count 2 2006.201.23:49:22.71#ibcon#end of sib2, iclass 10, count 2 2006.201.23:49:22.71#ibcon#*mode == 0, iclass 10, count 2 2006.201.23:49:22.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.201.23:49:22.71#ibcon#[27=AT05-04\r\n] 2006.201.23:49:22.71#ibcon#*before write, iclass 10, count 2 2006.201.23:49:22.71#ibcon#enter sib2, iclass 10, count 2 2006.201.23:49:22.71#ibcon#flushed, iclass 10, count 2 2006.201.23:49:22.71#ibcon#about to write, iclass 10, count 2 2006.201.23:49:22.71#ibcon#wrote, iclass 10, count 2 2006.201.23:49:22.71#ibcon#about to read 3, iclass 10, count 2 2006.201.23:49:22.74#ibcon#read 3, iclass 10, count 2 2006.201.23:49:22.74#ibcon#about to read 4, iclass 10, count 2 2006.201.23:49:22.74#ibcon#read 4, iclass 10, count 2 2006.201.23:49:22.74#ibcon#about to read 5, iclass 10, count 2 2006.201.23:49:22.74#ibcon#read 5, iclass 10, count 2 2006.201.23:49:22.74#ibcon#about to read 6, iclass 10, count 2 2006.201.23:49:22.74#ibcon#read 6, iclass 10, count 2 2006.201.23:49:22.74#ibcon#end of sib2, iclass 10, count 2 2006.201.23:49:22.74#ibcon#*after write, iclass 10, count 2 2006.201.23:49:22.74#ibcon#*before return 0, iclass 10, count 2 2006.201.23:49:22.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:22.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.201.23:49:22.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.201.23:49:22.74#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:22.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:22.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:22.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:22.86#ibcon#enter wrdev, iclass 10, count 0 2006.201.23:49:22.86#ibcon#first serial, iclass 10, count 0 2006.201.23:49:22.86#ibcon#enter sib2, iclass 10, count 0 2006.201.23:49:22.86#ibcon#flushed, iclass 10, count 0 2006.201.23:49:22.86#ibcon#about to write, iclass 10, count 0 2006.201.23:49:22.86#ibcon#wrote, iclass 10, count 0 2006.201.23:49:22.86#ibcon#about to read 3, iclass 10, count 0 2006.201.23:49:22.88#ibcon#read 3, iclass 10, count 0 2006.201.23:49:22.88#ibcon#about to read 4, iclass 10, count 0 2006.201.23:49:22.88#ibcon#read 4, iclass 10, count 0 2006.201.23:49:22.88#ibcon#about to read 5, iclass 10, count 0 2006.201.23:49:22.88#ibcon#read 5, iclass 10, count 0 2006.201.23:49:22.88#ibcon#about to read 6, iclass 10, count 0 2006.201.23:49:22.88#ibcon#read 6, iclass 10, count 0 2006.201.23:49:22.88#ibcon#end of sib2, iclass 10, count 0 2006.201.23:49:22.88#ibcon#*mode == 0, iclass 10, count 0 2006.201.23:49:22.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.201.23:49:22.88#ibcon#[27=USB\r\n] 2006.201.23:49:22.88#ibcon#*before write, iclass 10, count 0 2006.201.23:49:22.88#ibcon#enter sib2, iclass 10, count 0 2006.201.23:49:22.88#ibcon#flushed, iclass 10, count 0 2006.201.23:49:22.88#ibcon#about to write, iclass 10, count 0 2006.201.23:49:22.88#ibcon#wrote, iclass 10, count 0 2006.201.23:49:22.88#ibcon#about to read 3, iclass 10, count 0 2006.201.23:49:22.91#ibcon#read 3, iclass 10, count 0 2006.201.23:49:22.91#ibcon#about to read 4, iclass 10, count 0 2006.201.23:49:22.91#ibcon#read 4, iclass 10, count 0 2006.201.23:49:22.91#ibcon#about to read 5, iclass 10, count 0 2006.201.23:49:22.91#ibcon#read 5, iclass 10, count 0 2006.201.23:49:22.91#ibcon#about to read 6, iclass 10, count 0 2006.201.23:49:22.91#ibcon#read 6, iclass 10, count 0 2006.201.23:49:22.91#ibcon#end of sib2, iclass 10, count 0 2006.201.23:49:22.91#ibcon#*after write, iclass 10, count 0 2006.201.23:49:22.91#ibcon#*before return 0, iclass 10, count 0 2006.201.23:49:22.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:22.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.201.23:49:22.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.201.23:49:22.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.201.23:49:22.91$vck44/vblo=6,719.99 2006.201.23:49:22.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.201.23:49:22.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.201.23:49:22.91#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:22.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:22.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:22.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:22.91#ibcon#enter wrdev, iclass 12, count 0 2006.201.23:49:22.91#ibcon#first serial, iclass 12, count 0 2006.201.23:49:22.91#ibcon#enter sib2, iclass 12, count 0 2006.201.23:49:22.91#ibcon#flushed, iclass 12, count 0 2006.201.23:49:22.91#ibcon#about to write, iclass 12, count 0 2006.201.23:49:22.91#ibcon#wrote, iclass 12, count 0 2006.201.23:49:22.91#ibcon#about to read 3, iclass 12, count 0 2006.201.23:49:22.93#ibcon#read 3, iclass 12, count 0 2006.201.23:49:22.93#ibcon#about to read 4, iclass 12, count 0 2006.201.23:49:22.93#ibcon#read 4, iclass 12, count 0 2006.201.23:49:22.93#ibcon#about to read 5, iclass 12, count 0 2006.201.23:49:22.93#ibcon#read 5, iclass 12, count 0 2006.201.23:49:22.93#ibcon#about to read 6, iclass 12, count 0 2006.201.23:49:22.93#ibcon#read 6, iclass 12, count 0 2006.201.23:49:22.93#ibcon#end of sib2, iclass 12, count 0 2006.201.23:49:22.93#ibcon#*mode == 0, iclass 12, count 0 2006.201.23:49:22.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.201.23:49:22.93#ibcon#[28=FRQ=06,719.99\r\n] 2006.201.23:49:22.93#ibcon#*before write, iclass 12, count 0 2006.201.23:49:22.93#ibcon#enter sib2, iclass 12, count 0 2006.201.23:49:22.93#ibcon#flushed, iclass 12, count 0 2006.201.23:49:22.93#ibcon#about to write, iclass 12, count 0 2006.201.23:49:22.93#ibcon#wrote, iclass 12, count 0 2006.201.23:49:22.93#ibcon#about to read 3, iclass 12, count 0 2006.201.23:49:22.97#ibcon#read 3, iclass 12, count 0 2006.201.23:49:22.97#ibcon#about to read 4, iclass 12, count 0 2006.201.23:49:22.97#ibcon#read 4, iclass 12, count 0 2006.201.23:49:22.97#ibcon#about to read 5, iclass 12, count 0 2006.201.23:49:22.97#ibcon#read 5, iclass 12, count 0 2006.201.23:49:22.97#ibcon#about to read 6, iclass 12, count 0 2006.201.23:49:22.97#ibcon#read 6, iclass 12, count 0 2006.201.23:49:22.97#ibcon#end of sib2, iclass 12, count 0 2006.201.23:49:22.97#ibcon#*after write, iclass 12, count 0 2006.201.23:49:22.97#ibcon#*before return 0, iclass 12, count 0 2006.201.23:49:22.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:22.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.201.23:49:22.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.201.23:49:22.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.201.23:49:22.97$vck44/vb=6,4 2006.201.23:49:22.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.201.23:49:22.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.201.23:49:22.97#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:22.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:23.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:23.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:23.03#ibcon#enter wrdev, iclass 14, count 2 2006.201.23:49:23.03#ibcon#first serial, iclass 14, count 2 2006.201.23:49:23.03#ibcon#enter sib2, iclass 14, count 2 2006.201.23:49:23.03#ibcon#flushed, iclass 14, count 2 2006.201.23:49:23.03#ibcon#about to write, iclass 14, count 2 2006.201.23:49:23.03#ibcon#wrote, iclass 14, count 2 2006.201.23:49:23.03#ibcon#about to read 3, iclass 14, count 2 2006.201.23:49:23.05#ibcon#read 3, iclass 14, count 2 2006.201.23:49:23.05#ibcon#about to read 4, iclass 14, count 2 2006.201.23:49:23.05#ibcon#read 4, iclass 14, count 2 2006.201.23:49:23.05#ibcon#about to read 5, iclass 14, count 2 2006.201.23:49:23.05#ibcon#read 5, iclass 14, count 2 2006.201.23:49:23.05#ibcon#about to read 6, iclass 14, count 2 2006.201.23:49:23.05#ibcon#read 6, iclass 14, count 2 2006.201.23:49:23.05#ibcon#end of sib2, iclass 14, count 2 2006.201.23:49:23.05#ibcon#*mode == 0, iclass 14, count 2 2006.201.23:49:23.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.201.23:49:23.05#ibcon#[27=AT06-04\r\n] 2006.201.23:49:23.05#ibcon#*before write, iclass 14, count 2 2006.201.23:49:23.05#ibcon#enter sib2, iclass 14, count 2 2006.201.23:49:23.05#ibcon#flushed, iclass 14, count 2 2006.201.23:49:23.05#ibcon#about to write, iclass 14, count 2 2006.201.23:49:23.05#ibcon#wrote, iclass 14, count 2 2006.201.23:49:23.05#ibcon#about to read 3, iclass 14, count 2 2006.201.23:49:23.08#ibcon#read 3, iclass 14, count 2 2006.201.23:49:23.08#ibcon#about to read 4, iclass 14, count 2 2006.201.23:49:23.08#ibcon#read 4, iclass 14, count 2 2006.201.23:49:23.08#ibcon#about to read 5, iclass 14, count 2 2006.201.23:49:23.08#ibcon#read 5, iclass 14, count 2 2006.201.23:49:23.08#ibcon#about to read 6, iclass 14, count 2 2006.201.23:49:23.08#ibcon#read 6, iclass 14, count 2 2006.201.23:49:23.08#ibcon#end of sib2, iclass 14, count 2 2006.201.23:49:23.08#ibcon#*after write, iclass 14, count 2 2006.201.23:49:23.08#ibcon#*before return 0, iclass 14, count 2 2006.201.23:49:23.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:23.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.201.23:49:23.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.201.23:49:23.08#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:23.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:23.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:23.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:23.20#ibcon#enter wrdev, iclass 14, count 0 2006.201.23:49:23.20#ibcon#first serial, iclass 14, count 0 2006.201.23:49:23.20#ibcon#enter sib2, iclass 14, count 0 2006.201.23:49:23.20#ibcon#flushed, iclass 14, count 0 2006.201.23:49:23.20#ibcon#about to write, iclass 14, count 0 2006.201.23:49:23.20#ibcon#wrote, iclass 14, count 0 2006.201.23:49:23.20#ibcon#about to read 3, iclass 14, count 0 2006.201.23:49:23.22#ibcon#read 3, iclass 14, count 0 2006.201.23:49:23.22#ibcon#about to read 4, iclass 14, count 0 2006.201.23:49:23.22#ibcon#read 4, iclass 14, count 0 2006.201.23:49:23.22#ibcon#about to read 5, iclass 14, count 0 2006.201.23:49:23.22#ibcon#read 5, iclass 14, count 0 2006.201.23:49:23.22#ibcon#about to read 6, iclass 14, count 0 2006.201.23:49:23.22#ibcon#read 6, iclass 14, count 0 2006.201.23:49:23.22#ibcon#end of sib2, iclass 14, count 0 2006.201.23:49:23.22#ibcon#*mode == 0, iclass 14, count 0 2006.201.23:49:23.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.201.23:49:23.22#ibcon#[27=USB\r\n] 2006.201.23:49:23.22#ibcon#*before write, iclass 14, count 0 2006.201.23:49:23.22#ibcon#enter sib2, iclass 14, count 0 2006.201.23:49:23.22#ibcon#flushed, iclass 14, count 0 2006.201.23:49:23.22#ibcon#about to write, iclass 14, count 0 2006.201.23:49:23.22#ibcon#wrote, iclass 14, count 0 2006.201.23:49:23.22#ibcon#about to read 3, iclass 14, count 0 2006.201.23:49:23.25#ibcon#read 3, iclass 14, count 0 2006.201.23:49:23.25#ibcon#about to read 4, iclass 14, count 0 2006.201.23:49:23.25#ibcon#read 4, iclass 14, count 0 2006.201.23:49:23.25#ibcon#about to read 5, iclass 14, count 0 2006.201.23:49:23.25#ibcon#read 5, iclass 14, count 0 2006.201.23:49:23.25#ibcon#about to read 6, iclass 14, count 0 2006.201.23:49:23.25#ibcon#read 6, iclass 14, count 0 2006.201.23:49:23.25#ibcon#end of sib2, iclass 14, count 0 2006.201.23:49:23.25#ibcon#*after write, iclass 14, count 0 2006.201.23:49:23.25#ibcon#*before return 0, iclass 14, count 0 2006.201.23:49:23.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:23.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.201.23:49:23.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.201.23:49:23.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.201.23:49:23.25$vck44/vblo=7,734.99 2006.201.23:49:23.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.201.23:49:23.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.201.23:49:23.25#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:23.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:23.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:23.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:23.25#ibcon#enter wrdev, iclass 16, count 0 2006.201.23:49:23.25#ibcon#first serial, iclass 16, count 0 2006.201.23:49:23.25#ibcon#enter sib2, iclass 16, count 0 2006.201.23:49:23.25#ibcon#flushed, iclass 16, count 0 2006.201.23:49:23.25#ibcon#about to write, iclass 16, count 0 2006.201.23:49:23.25#ibcon#wrote, iclass 16, count 0 2006.201.23:49:23.25#ibcon#about to read 3, iclass 16, count 0 2006.201.23:49:23.27#ibcon#read 3, iclass 16, count 0 2006.201.23:49:23.27#ibcon#about to read 4, iclass 16, count 0 2006.201.23:49:23.27#ibcon#read 4, iclass 16, count 0 2006.201.23:49:23.27#ibcon#about to read 5, iclass 16, count 0 2006.201.23:49:23.27#ibcon#read 5, iclass 16, count 0 2006.201.23:49:23.27#ibcon#about to read 6, iclass 16, count 0 2006.201.23:49:23.27#ibcon#read 6, iclass 16, count 0 2006.201.23:49:23.27#ibcon#end of sib2, iclass 16, count 0 2006.201.23:49:23.27#ibcon#*mode == 0, iclass 16, count 0 2006.201.23:49:23.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.201.23:49:23.27#ibcon#[28=FRQ=07,734.99\r\n] 2006.201.23:49:23.27#ibcon#*before write, iclass 16, count 0 2006.201.23:49:23.27#ibcon#enter sib2, iclass 16, count 0 2006.201.23:49:23.27#ibcon#flushed, iclass 16, count 0 2006.201.23:49:23.27#ibcon#about to write, iclass 16, count 0 2006.201.23:49:23.27#ibcon#wrote, iclass 16, count 0 2006.201.23:49:23.27#ibcon#about to read 3, iclass 16, count 0 2006.201.23:49:23.31#ibcon#read 3, iclass 16, count 0 2006.201.23:49:23.31#ibcon#about to read 4, iclass 16, count 0 2006.201.23:49:23.31#ibcon#read 4, iclass 16, count 0 2006.201.23:49:23.31#ibcon#about to read 5, iclass 16, count 0 2006.201.23:49:23.31#ibcon#read 5, iclass 16, count 0 2006.201.23:49:23.31#ibcon#about to read 6, iclass 16, count 0 2006.201.23:49:23.31#ibcon#read 6, iclass 16, count 0 2006.201.23:49:23.31#ibcon#end of sib2, iclass 16, count 0 2006.201.23:49:23.31#ibcon#*after write, iclass 16, count 0 2006.201.23:49:23.31#ibcon#*before return 0, iclass 16, count 0 2006.201.23:49:23.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:23.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.201.23:49:23.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.201.23:49:23.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.201.23:49:23.31$vck44/vb=7,4 2006.201.23:49:23.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.201.23:49:23.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.201.23:49:23.31#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:23.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:23.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:23.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:23.37#ibcon#enter wrdev, iclass 18, count 2 2006.201.23:49:23.37#ibcon#first serial, iclass 18, count 2 2006.201.23:49:23.37#ibcon#enter sib2, iclass 18, count 2 2006.201.23:49:23.37#ibcon#flushed, iclass 18, count 2 2006.201.23:49:23.37#ibcon#about to write, iclass 18, count 2 2006.201.23:49:23.37#ibcon#wrote, iclass 18, count 2 2006.201.23:49:23.37#ibcon#about to read 3, iclass 18, count 2 2006.201.23:49:23.39#ibcon#read 3, iclass 18, count 2 2006.201.23:49:23.39#ibcon#about to read 4, iclass 18, count 2 2006.201.23:49:23.39#ibcon#read 4, iclass 18, count 2 2006.201.23:49:23.39#ibcon#about to read 5, iclass 18, count 2 2006.201.23:49:23.39#ibcon#read 5, iclass 18, count 2 2006.201.23:49:23.39#ibcon#about to read 6, iclass 18, count 2 2006.201.23:49:23.39#ibcon#read 6, iclass 18, count 2 2006.201.23:49:23.39#ibcon#end of sib2, iclass 18, count 2 2006.201.23:49:23.39#ibcon#*mode == 0, iclass 18, count 2 2006.201.23:49:23.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.201.23:49:23.39#ibcon#[27=AT07-04\r\n] 2006.201.23:49:23.39#ibcon#*before write, iclass 18, count 2 2006.201.23:49:23.39#ibcon#enter sib2, iclass 18, count 2 2006.201.23:49:23.39#ibcon#flushed, iclass 18, count 2 2006.201.23:49:23.39#ibcon#about to write, iclass 18, count 2 2006.201.23:49:23.39#ibcon#wrote, iclass 18, count 2 2006.201.23:49:23.39#ibcon#about to read 3, iclass 18, count 2 2006.201.23:49:23.42#ibcon#read 3, iclass 18, count 2 2006.201.23:49:23.42#ibcon#about to read 4, iclass 18, count 2 2006.201.23:49:23.42#ibcon#read 4, iclass 18, count 2 2006.201.23:49:23.42#ibcon#about to read 5, iclass 18, count 2 2006.201.23:49:23.42#ibcon#read 5, iclass 18, count 2 2006.201.23:49:23.42#ibcon#about to read 6, iclass 18, count 2 2006.201.23:49:23.42#ibcon#read 6, iclass 18, count 2 2006.201.23:49:23.42#ibcon#end of sib2, iclass 18, count 2 2006.201.23:49:23.42#ibcon#*after write, iclass 18, count 2 2006.201.23:49:23.42#ibcon#*before return 0, iclass 18, count 2 2006.201.23:49:23.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:23.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.201.23:49:23.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.201.23:49:23.42#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:23.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:23.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:23.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:23.54#ibcon#enter wrdev, iclass 18, count 0 2006.201.23:49:23.54#ibcon#first serial, iclass 18, count 0 2006.201.23:49:23.54#ibcon#enter sib2, iclass 18, count 0 2006.201.23:49:23.54#ibcon#flushed, iclass 18, count 0 2006.201.23:49:23.54#ibcon#about to write, iclass 18, count 0 2006.201.23:49:23.54#ibcon#wrote, iclass 18, count 0 2006.201.23:49:23.54#ibcon#about to read 3, iclass 18, count 0 2006.201.23:49:23.56#ibcon#read 3, iclass 18, count 0 2006.201.23:49:23.56#ibcon#about to read 4, iclass 18, count 0 2006.201.23:49:23.56#ibcon#read 4, iclass 18, count 0 2006.201.23:49:23.56#ibcon#about to read 5, iclass 18, count 0 2006.201.23:49:23.56#ibcon#read 5, iclass 18, count 0 2006.201.23:49:23.56#ibcon#about to read 6, iclass 18, count 0 2006.201.23:49:23.56#ibcon#read 6, iclass 18, count 0 2006.201.23:49:23.56#ibcon#end of sib2, iclass 18, count 0 2006.201.23:49:23.56#ibcon#*mode == 0, iclass 18, count 0 2006.201.23:49:23.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.201.23:49:23.56#ibcon#[27=USB\r\n] 2006.201.23:49:23.56#ibcon#*before write, iclass 18, count 0 2006.201.23:49:23.56#ibcon#enter sib2, iclass 18, count 0 2006.201.23:49:23.56#ibcon#flushed, iclass 18, count 0 2006.201.23:49:23.56#ibcon#about to write, iclass 18, count 0 2006.201.23:49:23.56#ibcon#wrote, iclass 18, count 0 2006.201.23:49:23.56#ibcon#about to read 3, iclass 18, count 0 2006.201.23:49:23.59#ibcon#read 3, iclass 18, count 0 2006.201.23:49:23.59#ibcon#about to read 4, iclass 18, count 0 2006.201.23:49:23.59#ibcon#read 4, iclass 18, count 0 2006.201.23:49:23.59#ibcon#about to read 5, iclass 18, count 0 2006.201.23:49:23.59#ibcon#read 5, iclass 18, count 0 2006.201.23:49:23.59#ibcon#about to read 6, iclass 18, count 0 2006.201.23:49:23.59#ibcon#read 6, iclass 18, count 0 2006.201.23:49:23.59#ibcon#end of sib2, iclass 18, count 0 2006.201.23:49:23.59#ibcon#*after write, iclass 18, count 0 2006.201.23:49:23.59#ibcon#*before return 0, iclass 18, count 0 2006.201.23:49:23.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:23.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.201.23:49:23.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.201.23:49:23.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.201.23:49:23.59$vck44/vblo=8,744.99 2006.201.23:49:23.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.201.23:49:23.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.201.23:49:23.59#ibcon#ireg 17 cls_cnt 0 2006.201.23:49:23.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:23.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:23.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:23.59#ibcon#enter wrdev, iclass 20, count 0 2006.201.23:49:23.59#ibcon#first serial, iclass 20, count 0 2006.201.23:49:23.59#ibcon#enter sib2, iclass 20, count 0 2006.201.23:49:23.59#ibcon#flushed, iclass 20, count 0 2006.201.23:49:23.59#ibcon#about to write, iclass 20, count 0 2006.201.23:49:23.59#ibcon#wrote, iclass 20, count 0 2006.201.23:49:23.59#ibcon#about to read 3, iclass 20, count 0 2006.201.23:49:23.61#ibcon#read 3, iclass 20, count 0 2006.201.23:49:23.61#ibcon#about to read 4, iclass 20, count 0 2006.201.23:49:23.61#ibcon#read 4, iclass 20, count 0 2006.201.23:49:23.61#ibcon#about to read 5, iclass 20, count 0 2006.201.23:49:23.61#ibcon#read 5, iclass 20, count 0 2006.201.23:49:23.61#ibcon#about to read 6, iclass 20, count 0 2006.201.23:49:23.61#ibcon#read 6, iclass 20, count 0 2006.201.23:49:23.61#ibcon#end of sib2, iclass 20, count 0 2006.201.23:49:23.61#ibcon#*mode == 0, iclass 20, count 0 2006.201.23:49:23.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.201.23:49:23.61#ibcon#[28=FRQ=08,744.99\r\n] 2006.201.23:49:23.61#ibcon#*before write, iclass 20, count 0 2006.201.23:49:23.61#ibcon#enter sib2, iclass 20, count 0 2006.201.23:49:23.61#ibcon#flushed, iclass 20, count 0 2006.201.23:49:23.61#ibcon#about to write, iclass 20, count 0 2006.201.23:49:23.61#ibcon#wrote, iclass 20, count 0 2006.201.23:49:23.61#ibcon#about to read 3, iclass 20, count 0 2006.201.23:49:23.65#ibcon#read 3, iclass 20, count 0 2006.201.23:49:23.65#ibcon#about to read 4, iclass 20, count 0 2006.201.23:49:23.65#ibcon#read 4, iclass 20, count 0 2006.201.23:49:23.65#ibcon#about to read 5, iclass 20, count 0 2006.201.23:49:23.65#ibcon#read 5, iclass 20, count 0 2006.201.23:49:23.65#ibcon#about to read 6, iclass 20, count 0 2006.201.23:49:23.65#ibcon#read 6, iclass 20, count 0 2006.201.23:49:23.65#ibcon#end of sib2, iclass 20, count 0 2006.201.23:49:23.65#ibcon#*after write, iclass 20, count 0 2006.201.23:49:23.65#ibcon#*before return 0, iclass 20, count 0 2006.201.23:49:23.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:23.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.201.23:49:23.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.201.23:49:23.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.201.23:49:23.65$vck44/vb=8,4 2006.201.23:49:23.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.201.23:49:23.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.201.23:49:23.65#ibcon#ireg 11 cls_cnt 2 2006.201.23:49:23.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:23.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:23.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:23.71#ibcon#enter wrdev, iclass 22, count 2 2006.201.23:49:23.71#ibcon#first serial, iclass 22, count 2 2006.201.23:49:23.71#ibcon#enter sib2, iclass 22, count 2 2006.201.23:49:23.71#ibcon#flushed, iclass 22, count 2 2006.201.23:49:23.71#ibcon#about to write, iclass 22, count 2 2006.201.23:49:23.71#ibcon#wrote, iclass 22, count 2 2006.201.23:49:23.71#ibcon#about to read 3, iclass 22, count 2 2006.201.23:49:23.73#ibcon#read 3, iclass 22, count 2 2006.201.23:49:23.73#ibcon#about to read 4, iclass 22, count 2 2006.201.23:49:23.73#ibcon#read 4, iclass 22, count 2 2006.201.23:49:23.73#ibcon#about to read 5, iclass 22, count 2 2006.201.23:49:23.73#ibcon#read 5, iclass 22, count 2 2006.201.23:49:23.73#ibcon#about to read 6, iclass 22, count 2 2006.201.23:49:23.73#ibcon#read 6, iclass 22, count 2 2006.201.23:49:23.73#ibcon#end of sib2, iclass 22, count 2 2006.201.23:49:23.73#ibcon#*mode == 0, iclass 22, count 2 2006.201.23:49:23.73#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.201.23:49:23.73#ibcon#[27=AT08-04\r\n] 2006.201.23:49:23.73#ibcon#*before write, iclass 22, count 2 2006.201.23:49:23.73#ibcon#enter sib2, iclass 22, count 2 2006.201.23:49:23.73#ibcon#flushed, iclass 22, count 2 2006.201.23:49:23.73#ibcon#about to write, iclass 22, count 2 2006.201.23:49:23.73#ibcon#wrote, iclass 22, count 2 2006.201.23:49:23.73#ibcon#about to read 3, iclass 22, count 2 2006.201.23:49:23.76#ibcon#read 3, iclass 22, count 2 2006.201.23:49:23.76#ibcon#about to read 4, iclass 22, count 2 2006.201.23:49:23.76#ibcon#read 4, iclass 22, count 2 2006.201.23:49:23.76#ibcon#about to read 5, iclass 22, count 2 2006.201.23:49:23.76#ibcon#read 5, iclass 22, count 2 2006.201.23:49:23.76#ibcon#about to read 6, iclass 22, count 2 2006.201.23:49:23.76#ibcon#read 6, iclass 22, count 2 2006.201.23:49:23.76#ibcon#end of sib2, iclass 22, count 2 2006.201.23:49:23.76#ibcon#*after write, iclass 22, count 2 2006.201.23:49:23.76#ibcon#*before return 0, iclass 22, count 2 2006.201.23:49:23.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:23.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.201.23:49:23.76#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.201.23:49:23.76#ibcon#ireg 7 cls_cnt 0 2006.201.23:49:23.76#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:23.88#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:23.88#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:23.88#ibcon#enter wrdev, iclass 22, count 0 2006.201.23:49:23.88#ibcon#first serial, iclass 22, count 0 2006.201.23:49:23.88#ibcon#enter sib2, iclass 22, count 0 2006.201.23:49:23.88#ibcon#flushed, iclass 22, count 0 2006.201.23:49:23.88#ibcon#about to write, iclass 22, count 0 2006.201.23:49:23.88#ibcon#wrote, iclass 22, count 0 2006.201.23:49:23.88#ibcon#about to read 3, iclass 22, count 0 2006.201.23:49:23.90#ibcon#read 3, iclass 22, count 0 2006.201.23:49:23.90#ibcon#about to read 4, iclass 22, count 0 2006.201.23:49:23.90#ibcon#read 4, iclass 22, count 0 2006.201.23:49:23.90#ibcon#about to read 5, iclass 22, count 0 2006.201.23:49:23.90#ibcon#read 5, iclass 22, count 0 2006.201.23:49:23.90#ibcon#about to read 6, iclass 22, count 0 2006.201.23:49:23.90#ibcon#read 6, iclass 22, count 0 2006.201.23:49:23.90#ibcon#end of sib2, iclass 22, count 0 2006.201.23:49:23.90#ibcon#*mode == 0, iclass 22, count 0 2006.201.23:49:23.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.201.23:49:23.90#ibcon#[27=USB\r\n] 2006.201.23:49:23.90#ibcon#*before write, iclass 22, count 0 2006.201.23:49:23.90#ibcon#enter sib2, iclass 22, count 0 2006.201.23:49:23.90#ibcon#flushed, iclass 22, count 0 2006.201.23:49:23.90#ibcon#about to write, iclass 22, count 0 2006.201.23:49:23.90#ibcon#wrote, iclass 22, count 0 2006.201.23:49:23.90#ibcon#about to read 3, iclass 22, count 0 2006.201.23:49:23.93#ibcon#read 3, iclass 22, count 0 2006.201.23:49:23.93#ibcon#about to read 4, iclass 22, count 0 2006.201.23:49:23.93#ibcon#read 4, iclass 22, count 0 2006.201.23:49:23.93#ibcon#about to read 5, iclass 22, count 0 2006.201.23:49:23.93#ibcon#read 5, iclass 22, count 0 2006.201.23:49:23.93#ibcon#about to read 6, iclass 22, count 0 2006.201.23:49:23.93#ibcon#read 6, iclass 22, count 0 2006.201.23:49:23.93#ibcon#end of sib2, iclass 22, count 0 2006.201.23:49:23.93#ibcon#*after write, iclass 22, count 0 2006.201.23:49:23.93#ibcon#*before return 0, iclass 22, count 0 2006.201.23:49:23.93#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:23.93#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.201.23:49:23.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.201.23:49:23.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.201.23:49:23.93$vck44/vabw=wide 2006.201.23:49:23.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.201.23:49:23.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.201.23:49:23.93#ibcon#ireg 8 cls_cnt 0 2006.201.23:49:23.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:23.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:23.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:23.93#ibcon#enter wrdev, iclass 24, count 0 2006.201.23:49:23.93#ibcon#first serial, iclass 24, count 0 2006.201.23:49:23.93#ibcon#enter sib2, iclass 24, count 0 2006.201.23:49:23.93#ibcon#flushed, iclass 24, count 0 2006.201.23:49:23.93#ibcon#about to write, iclass 24, count 0 2006.201.23:49:23.93#ibcon#wrote, iclass 24, count 0 2006.201.23:49:23.93#ibcon#about to read 3, iclass 24, count 0 2006.201.23:49:23.95#ibcon#read 3, iclass 24, count 0 2006.201.23:49:23.95#ibcon#about to read 4, iclass 24, count 0 2006.201.23:49:23.95#ibcon#read 4, iclass 24, count 0 2006.201.23:49:23.95#ibcon#about to read 5, iclass 24, count 0 2006.201.23:49:23.95#ibcon#read 5, iclass 24, count 0 2006.201.23:49:23.95#ibcon#about to read 6, iclass 24, count 0 2006.201.23:49:23.95#ibcon#read 6, iclass 24, count 0 2006.201.23:49:23.95#ibcon#end of sib2, iclass 24, count 0 2006.201.23:49:23.95#ibcon#*mode == 0, iclass 24, count 0 2006.201.23:49:23.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.201.23:49:23.95#ibcon#[25=BW32\r\n] 2006.201.23:49:23.95#ibcon#*before write, iclass 24, count 0 2006.201.23:49:23.95#ibcon#enter sib2, iclass 24, count 0 2006.201.23:49:23.95#ibcon#flushed, iclass 24, count 0 2006.201.23:49:23.95#ibcon#about to write, iclass 24, count 0 2006.201.23:49:23.95#ibcon#wrote, iclass 24, count 0 2006.201.23:49:23.95#ibcon#about to read 3, iclass 24, count 0 2006.201.23:49:23.98#ibcon#read 3, iclass 24, count 0 2006.201.23:49:23.98#ibcon#about to read 4, iclass 24, count 0 2006.201.23:49:23.98#ibcon#read 4, iclass 24, count 0 2006.201.23:49:23.98#ibcon#about to read 5, iclass 24, count 0 2006.201.23:49:23.98#ibcon#read 5, iclass 24, count 0 2006.201.23:49:23.98#ibcon#about to read 6, iclass 24, count 0 2006.201.23:49:23.98#ibcon#read 6, iclass 24, count 0 2006.201.23:49:23.98#ibcon#end of sib2, iclass 24, count 0 2006.201.23:49:23.98#ibcon#*after write, iclass 24, count 0 2006.201.23:49:23.98#ibcon#*before return 0, iclass 24, count 0 2006.201.23:49:23.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:23.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.201.23:49:23.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.201.23:49:23.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.201.23:49:23.98$vck44/vbbw=wide 2006.201.23:49:23.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.201.23:49:23.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.201.23:49:23.98#ibcon#ireg 8 cls_cnt 0 2006.201.23:49:23.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:49:24.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:49:24.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:49:24.05#ibcon#enter wrdev, iclass 26, count 0 2006.201.23:49:24.05#ibcon#first serial, iclass 26, count 0 2006.201.23:49:24.05#ibcon#enter sib2, iclass 26, count 0 2006.201.23:49:24.05#ibcon#flushed, iclass 26, count 0 2006.201.23:49:24.05#ibcon#about to write, iclass 26, count 0 2006.201.23:49:24.05#ibcon#wrote, iclass 26, count 0 2006.201.23:49:24.05#ibcon#about to read 3, iclass 26, count 0 2006.201.23:49:24.07#ibcon#read 3, iclass 26, count 0 2006.201.23:49:24.07#ibcon#about to read 4, iclass 26, count 0 2006.201.23:49:24.07#ibcon#read 4, iclass 26, count 0 2006.201.23:49:24.07#ibcon#about to read 5, iclass 26, count 0 2006.201.23:49:24.07#ibcon#read 5, iclass 26, count 0 2006.201.23:49:24.07#ibcon#about to read 6, iclass 26, count 0 2006.201.23:49:24.07#ibcon#read 6, iclass 26, count 0 2006.201.23:49:24.07#ibcon#end of sib2, iclass 26, count 0 2006.201.23:49:24.07#ibcon#*mode == 0, iclass 26, count 0 2006.201.23:49:24.07#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.201.23:49:24.07#ibcon#[27=BW32\r\n] 2006.201.23:49:24.07#ibcon#*before write, iclass 26, count 0 2006.201.23:49:24.07#ibcon#enter sib2, iclass 26, count 0 2006.201.23:49:24.07#ibcon#flushed, iclass 26, count 0 2006.201.23:49:24.07#ibcon#about to write, iclass 26, count 0 2006.201.23:49:24.07#ibcon#wrote, iclass 26, count 0 2006.201.23:49:24.07#ibcon#about to read 3, iclass 26, count 0 2006.201.23:49:24.10#ibcon#read 3, iclass 26, count 0 2006.201.23:49:24.10#ibcon#about to read 4, iclass 26, count 0 2006.201.23:49:24.10#ibcon#read 4, iclass 26, count 0 2006.201.23:49:24.10#ibcon#about to read 5, iclass 26, count 0 2006.201.23:49:24.10#ibcon#read 5, iclass 26, count 0 2006.201.23:49:24.10#ibcon#about to read 6, iclass 26, count 0 2006.201.23:49:24.10#ibcon#read 6, iclass 26, count 0 2006.201.23:49:24.10#ibcon#end of sib2, iclass 26, count 0 2006.201.23:49:24.10#ibcon#*after write, iclass 26, count 0 2006.201.23:49:24.10#ibcon#*before return 0, iclass 26, count 0 2006.201.23:49:24.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:49:24.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.201.23:49:24.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.201.23:49:24.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.201.23:49:24.10$setupk4/ifdk4 2006.201.23:49:24.10$ifdk4/lo= 2006.201.23:49:24.10$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.201.23:49:24.10$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.201.23:49:24.10$ifdk4/patch= 2006.201.23:49:24.10$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.201.23:49:24.10$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.201.23:49:24.10$setupk4/!*+20s 2006.201.23:49:31.86#abcon#<5=/02 0.8 2.0 20.371001001.4\r\n> 2006.201.23:49:31.88#abcon#{5=INTERFACE CLEAR} 2006.201.23:49:31.94#abcon#[5=S1D000X0/0*\r\n] 2006.201.23:49:38.60$setupk4/"tpicd 2006.201.23:49:38.60$setupk4/echo=off 2006.201.23:49:38.60$setupk4/xlog=off 2006.201.23:49:38.60:!2006.201.23:50:50 2006.201.23:49:48.13#trakl#Source acquired 2006.201.23:49:48.13#flagr#flagr/antenna,acquired 2006.201.23:50:50.00:preob 2006.201.23:50:50.13/onsource/TRACKING 2006.201.23:50:50.13:!2006.201.23:51:00 2006.201.23:51:00.00:"tape 2006.201.23:51:00.00:"st=record 2006.201.23:51:00.00:data_valid=on 2006.201.23:51:00.00:midob 2006.201.23:51:00.14/onsource/TRACKING 2006.201.23:51:00.14/wx/20.38,1001.3,100 2006.201.23:51:00.26/cable/+6.4829E-03 2006.201.23:51:01.35/va/01,08,usb,yes,68,72 2006.201.23:51:01.35/va/02,07,usb,yes,73,74 2006.201.23:51:01.35/va/03,08,usb,yes,67,69 2006.201.23:51:01.35/va/04,07,usb,yes,75,79 2006.201.23:51:01.35/va/05,04,usb,yes,68,70 2006.201.23:51:01.35/va/06,05,usb,yes,68,68 2006.201.23:51:01.35/va/07,05,usb,yes,67,69 2006.201.23:51:01.35/va/08,04,usb,yes,66,77 2006.201.23:51:01.58/valo/01,524.99,yes,locked 2006.201.23:51:01.58/valo/02,534.99,yes,locked 2006.201.23:51:01.58/valo/03,564.99,yes,locked 2006.201.23:51:01.58/valo/04,624.99,yes,locked 2006.201.23:51:01.58/valo/05,734.99,yes,locked 2006.201.23:51:01.58/valo/06,814.99,yes,locked 2006.201.23:51:01.58/valo/07,864.99,yes,locked 2006.201.23:51:01.58/valo/08,884.99,yes,locked 2006.201.23:51:02.67/vb/01,04,usb,yes,35,61 2006.201.23:51:02.67/vb/02,05,usb,yes,33,55 2006.201.23:51:02.67/vb/03,04,usb,yes,35,41 2006.201.23:51:02.67/vb/04,05,usb,yes,34,33 2006.201.23:51:02.67/vb/05,04,usb,yes,32,34 2006.201.23:51:02.67/vb/06,04,usb,yes,37,33 2006.201.23:51:02.67/vb/07,04,usb,yes,36,36 2006.201.23:51:02.67/vb/08,04,usb,yes,33,37 2006.201.23:51:02.90/vblo/01,629.99,yes,locked 2006.201.23:51:02.90/vblo/02,634.99,yes,locked 2006.201.23:51:02.90/vblo/03,649.99,yes,locked 2006.201.23:51:02.90/vblo/04,679.99,yes,locked 2006.201.23:51:02.90/vblo/05,709.99,yes,locked 2006.201.23:51:02.90/vblo/06,719.99,yes,locked 2006.201.23:51:02.90/vblo/07,734.99,yes,locked 2006.201.23:51:02.90/vblo/08,744.99,yes,locked 2006.201.23:51:03.05/vabw/8 2006.201.23:51:03.20/vbbw/8 2006.201.23:51:03.29/xfe/off,on,16.0 2006.201.23:51:03.66/ifatt/23,28,28,28 2006.201.23:51:04.07/fmout-gps/S +4.56E-07 2006.201.23:51:04.11:!2006.202.00:04:04 2006.202.00:04:04.00:data_valid=off 2006.202.00:04:04.00:"et 2006.202.00:04:04.00:!+3s 2006.202.00:04:07.01:"tape 2006.202.00:04:07.01:postob 2006.202.00:04:07.17/cable/+6.4830E-03 2006.202.00:04:07.17/wx/20.41,1001.4,100 2006.202.00:04:08.07/fmout-gps/S +4.57E-07 2006.202.00:04:08.07:scan_name=202-0004,jd0607,300 2006.202.00:04:08.07:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.202.00:04:09.14#flagr#flagr/antenna,new-source 2006.202.00:04:09.14:checkk5 2006.202.00:04:09.56/chk_autoobs//k5ts1/ autoobs is running! 2006.202.00:04:09.98/chk_autoobs//k5ts2/ autoobs is running! 2006.202.00:04:10.40/chk_autoobs//k5ts3/ autoobs is running! 2006.202.00:04:10.80/chk_autoobs//k5ts4/ autoobs is running! 2006.202.00:04:11.48/chk_obsdata//k5ts1/T2012351??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.202.00:04:12.20/chk_obsdata//k5ts2/T2012351??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.202.00:04:12.91/chk_obsdata//k5ts3/T2012351??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.202.00:04:13.61/chk_obsdata//k5ts4/T2012351??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.202.00:04:14.34/k5log//k5ts1_log_newline 2006.202.00:04:15.07/k5log//k5ts2_log_newline 2006.202.00:04:15.81/k5log//k5ts3_log_newline 2006.202.00:04:16.52/k5log//k5ts4_log_newline 2006.202.00:04:16.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.00:04:16.55:setupk4=1 2006.202.00:04:16.55$setupk4/echo=on 2006.202.00:04:16.55$setupk4/pcalon 2006.202.00:04:16.55$pcalon/"no phase cal control is implemented here 2006.202.00:04:16.55$setupk4/"tpicd=stop 2006.202.00:04:16.55$setupk4/"rec=synch_on 2006.202.00:04:16.55$setupk4/"rec_mode=128 2006.202.00:04:16.55$setupk4/!* 2006.202.00:04:16.55$setupk4/recpk4 2006.202.00:04:16.55$recpk4/recpatch= 2006.202.00:04:16.55$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.00:04:16.55$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.00:04:16.55$setupk4/vck44 2006.202.00:04:16.55$vck44/valo=1,524.99 2006.202.00:04:16.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.202.00:04:16.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.202.00:04:16.55#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:16.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:16.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:16.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:16.55#ibcon#enter wrdev, iclass 19, count 0 2006.202.00:04:16.55#ibcon#first serial, iclass 19, count 0 2006.202.00:04:16.55#ibcon#enter sib2, iclass 19, count 0 2006.202.00:04:16.55#ibcon#flushed, iclass 19, count 0 2006.202.00:04:16.55#ibcon#about to write, iclass 19, count 0 2006.202.00:04:16.55#ibcon#wrote, iclass 19, count 0 2006.202.00:04:16.55#ibcon#about to read 3, iclass 19, count 0 2006.202.00:04:16.57#ibcon#read 3, iclass 19, count 0 2006.202.00:04:16.57#ibcon#about to read 4, iclass 19, count 0 2006.202.00:04:16.57#ibcon#read 4, iclass 19, count 0 2006.202.00:04:16.57#ibcon#about to read 5, iclass 19, count 0 2006.202.00:04:16.57#ibcon#read 5, iclass 19, count 0 2006.202.00:04:16.57#ibcon#about to read 6, iclass 19, count 0 2006.202.00:04:16.57#ibcon#read 6, iclass 19, count 0 2006.202.00:04:16.57#ibcon#end of sib2, iclass 19, count 0 2006.202.00:04:16.57#ibcon#*mode == 0, iclass 19, count 0 2006.202.00:04:16.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.00:04:16.57#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.00:04:16.57#ibcon#*before write, iclass 19, count 0 2006.202.00:04:16.57#ibcon#enter sib2, iclass 19, count 0 2006.202.00:04:16.57#ibcon#flushed, iclass 19, count 0 2006.202.00:04:16.57#ibcon#about to write, iclass 19, count 0 2006.202.00:04:16.57#ibcon#wrote, iclass 19, count 0 2006.202.00:04:16.57#ibcon#about to read 3, iclass 19, count 0 2006.202.00:04:16.62#ibcon#read 3, iclass 19, count 0 2006.202.00:04:16.62#ibcon#about to read 4, iclass 19, count 0 2006.202.00:04:16.62#ibcon#read 4, iclass 19, count 0 2006.202.00:04:16.62#ibcon#about to read 5, iclass 19, count 0 2006.202.00:04:16.62#ibcon#read 5, iclass 19, count 0 2006.202.00:04:16.62#ibcon#about to read 6, iclass 19, count 0 2006.202.00:04:16.62#ibcon#read 6, iclass 19, count 0 2006.202.00:04:16.62#ibcon#end of sib2, iclass 19, count 0 2006.202.00:04:16.62#ibcon#*after write, iclass 19, count 0 2006.202.00:04:16.62#ibcon#*before return 0, iclass 19, count 0 2006.202.00:04:16.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:16.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:16.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.00:04:16.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.00:04:16.62$vck44/va=1,8 2006.202.00:04:16.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.202.00:04:16.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.202.00:04:16.62#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:16.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:16.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:16.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:16.62#ibcon#enter wrdev, iclass 21, count 2 2006.202.00:04:16.62#ibcon#first serial, iclass 21, count 2 2006.202.00:04:16.62#ibcon#enter sib2, iclass 21, count 2 2006.202.00:04:16.62#ibcon#flushed, iclass 21, count 2 2006.202.00:04:16.62#ibcon#about to write, iclass 21, count 2 2006.202.00:04:16.62#ibcon#wrote, iclass 21, count 2 2006.202.00:04:16.62#ibcon#about to read 3, iclass 21, count 2 2006.202.00:04:16.64#ibcon#read 3, iclass 21, count 2 2006.202.00:04:16.64#ibcon#about to read 4, iclass 21, count 2 2006.202.00:04:16.64#ibcon#read 4, iclass 21, count 2 2006.202.00:04:16.64#ibcon#about to read 5, iclass 21, count 2 2006.202.00:04:16.64#ibcon#read 5, iclass 21, count 2 2006.202.00:04:16.64#ibcon#about to read 6, iclass 21, count 2 2006.202.00:04:16.64#ibcon#read 6, iclass 21, count 2 2006.202.00:04:16.64#ibcon#end of sib2, iclass 21, count 2 2006.202.00:04:16.64#ibcon#*mode == 0, iclass 21, count 2 2006.202.00:04:16.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.202.00:04:16.64#ibcon#[25=AT01-08\r\n] 2006.202.00:04:16.64#ibcon#*before write, iclass 21, count 2 2006.202.00:04:16.64#ibcon#enter sib2, iclass 21, count 2 2006.202.00:04:16.64#ibcon#flushed, iclass 21, count 2 2006.202.00:04:16.64#ibcon#about to write, iclass 21, count 2 2006.202.00:04:16.64#ibcon#wrote, iclass 21, count 2 2006.202.00:04:16.64#ibcon#about to read 3, iclass 21, count 2 2006.202.00:04:16.67#ibcon#read 3, iclass 21, count 2 2006.202.00:04:16.67#ibcon#about to read 4, iclass 21, count 2 2006.202.00:04:16.67#ibcon#read 4, iclass 21, count 2 2006.202.00:04:16.67#ibcon#about to read 5, iclass 21, count 2 2006.202.00:04:16.67#ibcon#read 5, iclass 21, count 2 2006.202.00:04:16.67#ibcon#about to read 6, iclass 21, count 2 2006.202.00:04:16.67#ibcon#read 6, iclass 21, count 2 2006.202.00:04:16.67#ibcon#end of sib2, iclass 21, count 2 2006.202.00:04:16.67#ibcon#*after write, iclass 21, count 2 2006.202.00:04:16.67#ibcon#*before return 0, iclass 21, count 2 2006.202.00:04:16.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:16.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:16.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.202.00:04:16.67#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:16.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:16.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:16.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:16.79#ibcon#enter wrdev, iclass 21, count 0 2006.202.00:04:16.79#ibcon#first serial, iclass 21, count 0 2006.202.00:04:16.79#ibcon#enter sib2, iclass 21, count 0 2006.202.00:04:16.79#ibcon#flushed, iclass 21, count 0 2006.202.00:04:16.79#ibcon#about to write, iclass 21, count 0 2006.202.00:04:16.79#ibcon#wrote, iclass 21, count 0 2006.202.00:04:16.79#ibcon#about to read 3, iclass 21, count 0 2006.202.00:04:16.81#ibcon#read 3, iclass 21, count 0 2006.202.00:04:16.81#ibcon#about to read 4, iclass 21, count 0 2006.202.00:04:16.81#ibcon#read 4, iclass 21, count 0 2006.202.00:04:16.81#ibcon#about to read 5, iclass 21, count 0 2006.202.00:04:16.81#ibcon#read 5, iclass 21, count 0 2006.202.00:04:16.81#ibcon#about to read 6, iclass 21, count 0 2006.202.00:04:16.81#ibcon#read 6, iclass 21, count 0 2006.202.00:04:16.81#ibcon#end of sib2, iclass 21, count 0 2006.202.00:04:16.81#ibcon#*mode == 0, iclass 21, count 0 2006.202.00:04:16.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.00:04:16.81#ibcon#[25=USB\r\n] 2006.202.00:04:16.81#ibcon#*before write, iclass 21, count 0 2006.202.00:04:16.81#ibcon#enter sib2, iclass 21, count 0 2006.202.00:04:16.81#ibcon#flushed, iclass 21, count 0 2006.202.00:04:16.81#ibcon#about to write, iclass 21, count 0 2006.202.00:04:16.81#ibcon#wrote, iclass 21, count 0 2006.202.00:04:16.81#ibcon#about to read 3, iclass 21, count 0 2006.202.00:04:16.84#ibcon#read 3, iclass 21, count 0 2006.202.00:04:16.84#ibcon#about to read 4, iclass 21, count 0 2006.202.00:04:16.84#ibcon#read 4, iclass 21, count 0 2006.202.00:04:16.84#ibcon#about to read 5, iclass 21, count 0 2006.202.00:04:16.84#ibcon#read 5, iclass 21, count 0 2006.202.00:04:16.84#ibcon#about to read 6, iclass 21, count 0 2006.202.00:04:16.84#ibcon#read 6, iclass 21, count 0 2006.202.00:04:16.84#ibcon#end of sib2, iclass 21, count 0 2006.202.00:04:16.84#ibcon#*after write, iclass 21, count 0 2006.202.00:04:16.84#ibcon#*before return 0, iclass 21, count 0 2006.202.00:04:16.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:16.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:16.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.00:04:16.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.00:04:16.84$vck44/valo=2,534.99 2006.202.00:04:16.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.00:04:16.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.00:04:16.84#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:16.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:16.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:16.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:16.84#ibcon#enter wrdev, iclass 23, count 0 2006.202.00:04:16.84#ibcon#first serial, iclass 23, count 0 2006.202.00:04:16.84#ibcon#enter sib2, iclass 23, count 0 2006.202.00:04:16.84#ibcon#flushed, iclass 23, count 0 2006.202.00:04:16.84#ibcon#about to write, iclass 23, count 0 2006.202.00:04:16.84#ibcon#wrote, iclass 23, count 0 2006.202.00:04:16.84#ibcon#about to read 3, iclass 23, count 0 2006.202.00:04:16.86#ibcon#read 3, iclass 23, count 0 2006.202.00:04:16.86#ibcon#about to read 4, iclass 23, count 0 2006.202.00:04:16.86#ibcon#read 4, iclass 23, count 0 2006.202.00:04:16.86#ibcon#about to read 5, iclass 23, count 0 2006.202.00:04:16.86#ibcon#read 5, iclass 23, count 0 2006.202.00:04:16.86#ibcon#about to read 6, iclass 23, count 0 2006.202.00:04:16.86#ibcon#read 6, iclass 23, count 0 2006.202.00:04:16.86#ibcon#end of sib2, iclass 23, count 0 2006.202.00:04:16.86#ibcon#*mode == 0, iclass 23, count 0 2006.202.00:04:16.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.00:04:16.86#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.00:04:16.86#ibcon#*before write, iclass 23, count 0 2006.202.00:04:16.86#ibcon#enter sib2, iclass 23, count 0 2006.202.00:04:16.86#ibcon#flushed, iclass 23, count 0 2006.202.00:04:16.86#ibcon#about to write, iclass 23, count 0 2006.202.00:04:16.86#ibcon#wrote, iclass 23, count 0 2006.202.00:04:16.86#ibcon#about to read 3, iclass 23, count 0 2006.202.00:04:16.90#ibcon#read 3, iclass 23, count 0 2006.202.00:04:16.90#ibcon#about to read 4, iclass 23, count 0 2006.202.00:04:16.90#ibcon#read 4, iclass 23, count 0 2006.202.00:04:16.90#ibcon#about to read 5, iclass 23, count 0 2006.202.00:04:16.90#ibcon#read 5, iclass 23, count 0 2006.202.00:04:16.90#ibcon#about to read 6, iclass 23, count 0 2006.202.00:04:16.90#ibcon#read 6, iclass 23, count 0 2006.202.00:04:16.90#ibcon#end of sib2, iclass 23, count 0 2006.202.00:04:16.90#ibcon#*after write, iclass 23, count 0 2006.202.00:04:16.90#ibcon#*before return 0, iclass 23, count 0 2006.202.00:04:16.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:16.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:16.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.00:04:16.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.00:04:16.90$vck44/va=2,7 2006.202.00:04:16.90#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.202.00:04:16.90#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.202.00:04:16.90#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:16.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:16.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:16.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:16.96#ibcon#enter wrdev, iclass 25, count 2 2006.202.00:04:16.96#ibcon#first serial, iclass 25, count 2 2006.202.00:04:16.96#ibcon#enter sib2, iclass 25, count 2 2006.202.00:04:16.96#ibcon#flushed, iclass 25, count 2 2006.202.00:04:16.96#ibcon#about to write, iclass 25, count 2 2006.202.00:04:16.96#ibcon#wrote, iclass 25, count 2 2006.202.00:04:16.96#ibcon#about to read 3, iclass 25, count 2 2006.202.00:04:16.98#ibcon#read 3, iclass 25, count 2 2006.202.00:04:16.98#ibcon#about to read 4, iclass 25, count 2 2006.202.00:04:16.98#ibcon#read 4, iclass 25, count 2 2006.202.00:04:16.98#ibcon#about to read 5, iclass 25, count 2 2006.202.00:04:16.98#ibcon#read 5, iclass 25, count 2 2006.202.00:04:16.98#ibcon#about to read 6, iclass 25, count 2 2006.202.00:04:16.98#ibcon#read 6, iclass 25, count 2 2006.202.00:04:16.98#ibcon#end of sib2, iclass 25, count 2 2006.202.00:04:16.98#ibcon#*mode == 0, iclass 25, count 2 2006.202.00:04:16.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.202.00:04:16.98#ibcon#[25=AT02-07\r\n] 2006.202.00:04:16.98#ibcon#*before write, iclass 25, count 2 2006.202.00:04:16.98#ibcon#enter sib2, iclass 25, count 2 2006.202.00:04:16.98#ibcon#flushed, iclass 25, count 2 2006.202.00:04:16.98#ibcon#about to write, iclass 25, count 2 2006.202.00:04:16.98#ibcon#wrote, iclass 25, count 2 2006.202.00:04:16.98#ibcon#about to read 3, iclass 25, count 2 2006.202.00:04:17.01#ibcon#read 3, iclass 25, count 2 2006.202.00:04:17.01#ibcon#about to read 4, iclass 25, count 2 2006.202.00:04:17.01#ibcon#read 4, iclass 25, count 2 2006.202.00:04:17.01#ibcon#about to read 5, iclass 25, count 2 2006.202.00:04:17.01#ibcon#read 5, iclass 25, count 2 2006.202.00:04:17.01#ibcon#about to read 6, iclass 25, count 2 2006.202.00:04:17.01#ibcon#read 6, iclass 25, count 2 2006.202.00:04:17.01#ibcon#end of sib2, iclass 25, count 2 2006.202.00:04:17.01#ibcon#*after write, iclass 25, count 2 2006.202.00:04:17.01#ibcon#*before return 0, iclass 25, count 2 2006.202.00:04:17.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:17.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:17.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.202.00:04:17.01#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:17.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:17.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:17.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:17.13#ibcon#enter wrdev, iclass 25, count 0 2006.202.00:04:17.13#ibcon#first serial, iclass 25, count 0 2006.202.00:04:17.13#ibcon#enter sib2, iclass 25, count 0 2006.202.00:04:17.13#ibcon#flushed, iclass 25, count 0 2006.202.00:04:17.13#ibcon#about to write, iclass 25, count 0 2006.202.00:04:17.13#ibcon#wrote, iclass 25, count 0 2006.202.00:04:17.13#ibcon#about to read 3, iclass 25, count 0 2006.202.00:04:17.15#ibcon#read 3, iclass 25, count 0 2006.202.00:04:17.15#ibcon#about to read 4, iclass 25, count 0 2006.202.00:04:17.15#ibcon#read 4, iclass 25, count 0 2006.202.00:04:17.15#ibcon#about to read 5, iclass 25, count 0 2006.202.00:04:17.15#ibcon#read 5, iclass 25, count 0 2006.202.00:04:17.15#ibcon#about to read 6, iclass 25, count 0 2006.202.00:04:17.15#ibcon#read 6, iclass 25, count 0 2006.202.00:04:17.15#ibcon#end of sib2, iclass 25, count 0 2006.202.00:04:17.15#ibcon#*mode == 0, iclass 25, count 0 2006.202.00:04:17.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.00:04:17.15#ibcon#[25=USB\r\n] 2006.202.00:04:17.15#ibcon#*before write, iclass 25, count 0 2006.202.00:04:17.15#ibcon#enter sib2, iclass 25, count 0 2006.202.00:04:17.15#ibcon#flushed, iclass 25, count 0 2006.202.00:04:17.15#ibcon#about to write, iclass 25, count 0 2006.202.00:04:17.15#ibcon#wrote, iclass 25, count 0 2006.202.00:04:17.15#ibcon#about to read 3, iclass 25, count 0 2006.202.00:04:17.18#ibcon#read 3, iclass 25, count 0 2006.202.00:04:17.18#ibcon#about to read 4, iclass 25, count 0 2006.202.00:04:17.18#ibcon#read 4, iclass 25, count 0 2006.202.00:04:17.18#ibcon#about to read 5, iclass 25, count 0 2006.202.00:04:17.18#ibcon#read 5, iclass 25, count 0 2006.202.00:04:17.18#ibcon#about to read 6, iclass 25, count 0 2006.202.00:04:17.18#ibcon#read 6, iclass 25, count 0 2006.202.00:04:17.18#ibcon#end of sib2, iclass 25, count 0 2006.202.00:04:17.18#ibcon#*after write, iclass 25, count 0 2006.202.00:04:17.18#ibcon#*before return 0, iclass 25, count 0 2006.202.00:04:17.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:17.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:17.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.00:04:17.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.00:04:17.18$vck44/valo=3,564.99 2006.202.00:04:17.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.202.00:04:17.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.202.00:04:17.18#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:17.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:17.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:17.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:17.18#ibcon#enter wrdev, iclass 27, count 0 2006.202.00:04:17.18#ibcon#first serial, iclass 27, count 0 2006.202.00:04:17.18#ibcon#enter sib2, iclass 27, count 0 2006.202.00:04:17.18#ibcon#flushed, iclass 27, count 0 2006.202.00:04:17.18#ibcon#about to write, iclass 27, count 0 2006.202.00:04:17.18#ibcon#wrote, iclass 27, count 0 2006.202.00:04:17.18#ibcon#about to read 3, iclass 27, count 0 2006.202.00:04:17.20#ibcon#read 3, iclass 27, count 0 2006.202.00:04:17.20#ibcon#about to read 4, iclass 27, count 0 2006.202.00:04:17.20#ibcon#read 4, iclass 27, count 0 2006.202.00:04:17.20#ibcon#about to read 5, iclass 27, count 0 2006.202.00:04:17.20#ibcon#read 5, iclass 27, count 0 2006.202.00:04:17.20#ibcon#about to read 6, iclass 27, count 0 2006.202.00:04:17.20#ibcon#read 6, iclass 27, count 0 2006.202.00:04:17.20#ibcon#end of sib2, iclass 27, count 0 2006.202.00:04:17.20#ibcon#*mode == 0, iclass 27, count 0 2006.202.00:04:17.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.00:04:17.20#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.00:04:17.20#ibcon#*before write, iclass 27, count 0 2006.202.00:04:17.20#ibcon#enter sib2, iclass 27, count 0 2006.202.00:04:17.20#ibcon#flushed, iclass 27, count 0 2006.202.00:04:17.20#ibcon#about to write, iclass 27, count 0 2006.202.00:04:17.20#ibcon#wrote, iclass 27, count 0 2006.202.00:04:17.20#ibcon#about to read 3, iclass 27, count 0 2006.202.00:04:17.24#ibcon#read 3, iclass 27, count 0 2006.202.00:04:17.24#ibcon#about to read 4, iclass 27, count 0 2006.202.00:04:17.24#ibcon#read 4, iclass 27, count 0 2006.202.00:04:17.24#ibcon#about to read 5, iclass 27, count 0 2006.202.00:04:17.24#ibcon#read 5, iclass 27, count 0 2006.202.00:04:17.24#ibcon#about to read 6, iclass 27, count 0 2006.202.00:04:17.24#ibcon#read 6, iclass 27, count 0 2006.202.00:04:17.24#ibcon#end of sib2, iclass 27, count 0 2006.202.00:04:17.24#ibcon#*after write, iclass 27, count 0 2006.202.00:04:17.24#ibcon#*before return 0, iclass 27, count 0 2006.202.00:04:17.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:17.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:17.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.00:04:17.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.00:04:17.24$vck44/va=3,8 2006.202.00:04:17.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.00:04:17.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.00:04:17.24#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:17.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:17.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:17.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:17.30#ibcon#enter wrdev, iclass 29, count 2 2006.202.00:04:17.30#ibcon#first serial, iclass 29, count 2 2006.202.00:04:17.30#ibcon#enter sib2, iclass 29, count 2 2006.202.00:04:17.30#ibcon#flushed, iclass 29, count 2 2006.202.00:04:17.30#ibcon#about to write, iclass 29, count 2 2006.202.00:04:17.30#ibcon#wrote, iclass 29, count 2 2006.202.00:04:17.30#ibcon#about to read 3, iclass 29, count 2 2006.202.00:04:17.32#ibcon#read 3, iclass 29, count 2 2006.202.00:04:17.32#ibcon#about to read 4, iclass 29, count 2 2006.202.00:04:17.32#ibcon#read 4, iclass 29, count 2 2006.202.00:04:17.32#ibcon#about to read 5, iclass 29, count 2 2006.202.00:04:17.32#ibcon#read 5, iclass 29, count 2 2006.202.00:04:17.32#ibcon#about to read 6, iclass 29, count 2 2006.202.00:04:17.32#ibcon#read 6, iclass 29, count 2 2006.202.00:04:17.32#ibcon#end of sib2, iclass 29, count 2 2006.202.00:04:17.32#ibcon#*mode == 0, iclass 29, count 2 2006.202.00:04:17.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.00:04:17.32#ibcon#[25=AT03-08\r\n] 2006.202.00:04:17.32#ibcon#*before write, iclass 29, count 2 2006.202.00:04:17.32#ibcon#enter sib2, iclass 29, count 2 2006.202.00:04:17.32#ibcon#flushed, iclass 29, count 2 2006.202.00:04:17.32#ibcon#about to write, iclass 29, count 2 2006.202.00:04:17.32#ibcon#wrote, iclass 29, count 2 2006.202.00:04:17.32#ibcon#about to read 3, iclass 29, count 2 2006.202.00:04:17.35#ibcon#read 3, iclass 29, count 2 2006.202.00:04:17.35#ibcon#about to read 4, iclass 29, count 2 2006.202.00:04:17.35#ibcon#read 4, iclass 29, count 2 2006.202.00:04:17.35#ibcon#about to read 5, iclass 29, count 2 2006.202.00:04:17.35#ibcon#read 5, iclass 29, count 2 2006.202.00:04:17.35#ibcon#about to read 6, iclass 29, count 2 2006.202.00:04:17.35#ibcon#read 6, iclass 29, count 2 2006.202.00:04:17.35#ibcon#end of sib2, iclass 29, count 2 2006.202.00:04:17.35#ibcon#*after write, iclass 29, count 2 2006.202.00:04:17.35#ibcon#*before return 0, iclass 29, count 2 2006.202.00:04:17.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:17.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:17.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.00:04:17.35#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:17.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:17.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:17.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:17.47#ibcon#enter wrdev, iclass 29, count 0 2006.202.00:04:17.47#ibcon#first serial, iclass 29, count 0 2006.202.00:04:17.47#ibcon#enter sib2, iclass 29, count 0 2006.202.00:04:17.47#ibcon#flushed, iclass 29, count 0 2006.202.00:04:17.47#ibcon#about to write, iclass 29, count 0 2006.202.00:04:17.47#ibcon#wrote, iclass 29, count 0 2006.202.00:04:17.47#ibcon#about to read 3, iclass 29, count 0 2006.202.00:04:17.49#ibcon#read 3, iclass 29, count 0 2006.202.00:04:17.49#ibcon#about to read 4, iclass 29, count 0 2006.202.00:04:17.49#ibcon#read 4, iclass 29, count 0 2006.202.00:04:17.49#ibcon#about to read 5, iclass 29, count 0 2006.202.00:04:17.49#ibcon#read 5, iclass 29, count 0 2006.202.00:04:17.49#ibcon#about to read 6, iclass 29, count 0 2006.202.00:04:17.49#ibcon#read 6, iclass 29, count 0 2006.202.00:04:17.49#ibcon#end of sib2, iclass 29, count 0 2006.202.00:04:17.49#ibcon#*mode == 0, iclass 29, count 0 2006.202.00:04:17.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.00:04:17.49#ibcon#[25=USB\r\n] 2006.202.00:04:17.49#ibcon#*before write, iclass 29, count 0 2006.202.00:04:17.49#ibcon#enter sib2, iclass 29, count 0 2006.202.00:04:17.49#ibcon#flushed, iclass 29, count 0 2006.202.00:04:17.49#ibcon#about to write, iclass 29, count 0 2006.202.00:04:17.49#ibcon#wrote, iclass 29, count 0 2006.202.00:04:17.49#ibcon#about to read 3, iclass 29, count 0 2006.202.00:04:17.52#abcon#<5=/03 1.2 3.0 20.411001001.4\r\n> 2006.202.00:04:17.52#ibcon#read 3, iclass 29, count 0 2006.202.00:04:17.52#ibcon#about to read 4, iclass 29, count 0 2006.202.00:04:17.52#ibcon#read 4, iclass 29, count 0 2006.202.00:04:17.52#ibcon#about to read 5, iclass 29, count 0 2006.202.00:04:17.52#ibcon#read 5, iclass 29, count 0 2006.202.00:04:17.52#ibcon#about to read 6, iclass 29, count 0 2006.202.00:04:17.52#ibcon#read 6, iclass 29, count 0 2006.202.00:04:17.52#ibcon#end of sib2, iclass 29, count 0 2006.202.00:04:17.52#ibcon#*after write, iclass 29, count 0 2006.202.00:04:17.52#ibcon#*before return 0, iclass 29, count 0 2006.202.00:04:17.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:17.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:17.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.00:04:17.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.00:04:17.52$vck44/valo=4,624.99 2006.202.00:04:17.52#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.00:04:17.52#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.00:04:17.52#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:17.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:04:17.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:04:17.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:04:17.52#ibcon#enter wrdev, iclass 34, count 0 2006.202.00:04:17.52#ibcon#first serial, iclass 34, count 0 2006.202.00:04:17.52#ibcon#enter sib2, iclass 34, count 0 2006.202.00:04:17.52#ibcon#flushed, iclass 34, count 0 2006.202.00:04:17.52#ibcon#about to write, iclass 34, count 0 2006.202.00:04:17.52#ibcon#wrote, iclass 34, count 0 2006.202.00:04:17.52#ibcon#about to read 3, iclass 34, count 0 2006.202.00:04:17.54#abcon#{5=INTERFACE CLEAR} 2006.202.00:04:17.54#ibcon#read 3, iclass 34, count 0 2006.202.00:04:17.54#ibcon#about to read 4, iclass 34, count 0 2006.202.00:04:17.54#ibcon#read 4, iclass 34, count 0 2006.202.00:04:17.54#ibcon#about to read 5, iclass 34, count 0 2006.202.00:04:17.54#ibcon#read 5, iclass 34, count 0 2006.202.00:04:17.54#ibcon#about to read 6, iclass 34, count 0 2006.202.00:04:17.54#ibcon#read 6, iclass 34, count 0 2006.202.00:04:17.54#ibcon#end of sib2, iclass 34, count 0 2006.202.00:04:17.54#ibcon#*mode == 0, iclass 34, count 0 2006.202.00:04:17.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.00:04:17.54#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.00:04:17.54#ibcon#*before write, iclass 34, count 0 2006.202.00:04:17.54#ibcon#enter sib2, iclass 34, count 0 2006.202.00:04:17.54#ibcon#flushed, iclass 34, count 0 2006.202.00:04:17.54#ibcon#about to write, iclass 34, count 0 2006.202.00:04:17.54#ibcon#wrote, iclass 34, count 0 2006.202.00:04:17.54#ibcon#about to read 3, iclass 34, count 0 2006.202.00:04:17.58#ibcon#read 3, iclass 34, count 0 2006.202.00:04:17.58#ibcon#about to read 4, iclass 34, count 0 2006.202.00:04:17.58#ibcon#read 4, iclass 34, count 0 2006.202.00:04:17.58#ibcon#about to read 5, iclass 34, count 0 2006.202.00:04:17.58#ibcon#read 5, iclass 34, count 0 2006.202.00:04:17.58#ibcon#about to read 6, iclass 34, count 0 2006.202.00:04:17.58#ibcon#read 6, iclass 34, count 0 2006.202.00:04:17.58#ibcon#end of sib2, iclass 34, count 0 2006.202.00:04:17.58#ibcon#*after write, iclass 34, count 0 2006.202.00:04:17.58#ibcon#*before return 0, iclass 34, count 0 2006.202.00:04:17.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:04:17.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:04:17.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.00:04:17.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.00:04:17.58$vck44/va=4,7 2006.202.00:04:17.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.00:04:17.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.00:04:17.58#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:17.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:04:17.60#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:04:17.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:04:17.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:04:17.64#ibcon#enter wrdev, iclass 36, count 2 2006.202.00:04:17.64#ibcon#first serial, iclass 36, count 2 2006.202.00:04:17.64#ibcon#enter sib2, iclass 36, count 2 2006.202.00:04:17.64#ibcon#flushed, iclass 36, count 2 2006.202.00:04:17.64#ibcon#about to write, iclass 36, count 2 2006.202.00:04:17.64#ibcon#wrote, iclass 36, count 2 2006.202.00:04:17.64#ibcon#about to read 3, iclass 36, count 2 2006.202.00:04:17.66#ibcon#read 3, iclass 36, count 2 2006.202.00:04:17.66#ibcon#about to read 4, iclass 36, count 2 2006.202.00:04:17.66#ibcon#read 4, iclass 36, count 2 2006.202.00:04:17.66#ibcon#about to read 5, iclass 36, count 2 2006.202.00:04:17.66#ibcon#read 5, iclass 36, count 2 2006.202.00:04:17.66#ibcon#about to read 6, iclass 36, count 2 2006.202.00:04:17.66#ibcon#read 6, iclass 36, count 2 2006.202.00:04:17.66#ibcon#end of sib2, iclass 36, count 2 2006.202.00:04:17.66#ibcon#*mode == 0, iclass 36, count 2 2006.202.00:04:17.66#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.00:04:17.66#ibcon#[25=AT04-07\r\n] 2006.202.00:04:17.66#ibcon#*before write, iclass 36, count 2 2006.202.00:04:17.66#ibcon#enter sib2, iclass 36, count 2 2006.202.00:04:17.66#ibcon#flushed, iclass 36, count 2 2006.202.00:04:17.66#ibcon#about to write, iclass 36, count 2 2006.202.00:04:17.77#ibcon#wrote, iclass 36, count 2 2006.202.00:04:17.77#ibcon#about to read 3, iclass 36, count 2 2006.202.00:04:17.81#ibcon#read 3, iclass 36, count 2 2006.202.00:04:17.81#ibcon#about to read 4, iclass 36, count 2 2006.202.00:04:17.81#ibcon#read 4, iclass 36, count 2 2006.202.00:04:17.81#ibcon#about to read 5, iclass 36, count 2 2006.202.00:04:17.81#ibcon#read 5, iclass 36, count 2 2006.202.00:04:17.81#ibcon#about to read 6, iclass 36, count 2 2006.202.00:04:17.81#ibcon#read 6, iclass 36, count 2 2006.202.00:04:17.81#ibcon#end of sib2, iclass 36, count 2 2006.202.00:04:17.81#ibcon#*after write, iclass 36, count 2 2006.202.00:04:17.81#ibcon#*before return 0, iclass 36, count 2 2006.202.00:04:17.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:04:17.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:04:17.81#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.00:04:17.81#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:17.81#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:04:17.93#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:04:17.93#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:04:17.93#ibcon#enter wrdev, iclass 36, count 0 2006.202.00:04:17.93#ibcon#first serial, iclass 36, count 0 2006.202.00:04:17.93#ibcon#enter sib2, iclass 36, count 0 2006.202.00:04:17.93#ibcon#flushed, iclass 36, count 0 2006.202.00:04:17.93#ibcon#about to write, iclass 36, count 0 2006.202.00:04:17.93#ibcon#wrote, iclass 36, count 0 2006.202.00:04:17.93#ibcon#about to read 3, iclass 36, count 0 2006.202.00:04:17.95#ibcon#read 3, iclass 36, count 0 2006.202.00:04:17.95#ibcon#about to read 4, iclass 36, count 0 2006.202.00:04:17.95#ibcon#read 4, iclass 36, count 0 2006.202.00:04:17.95#ibcon#about to read 5, iclass 36, count 0 2006.202.00:04:17.95#ibcon#read 5, iclass 36, count 0 2006.202.00:04:17.95#ibcon#about to read 6, iclass 36, count 0 2006.202.00:04:17.95#ibcon#read 6, iclass 36, count 0 2006.202.00:04:17.95#ibcon#end of sib2, iclass 36, count 0 2006.202.00:04:17.95#ibcon#*mode == 0, iclass 36, count 0 2006.202.00:04:17.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.00:04:17.95#ibcon#[25=USB\r\n] 2006.202.00:04:17.95#ibcon#*before write, iclass 36, count 0 2006.202.00:04:17.95#ibcon#enter sib2, iclass 36, count 0 2006.202.00:04:17.95#ibcon#flushed, iclass 36, count 0 2006.202.00:04:17.95#ibcon#about to write, iclass 36, count 0 2006.202.00:04:17.95#ibcon#wrote, iclass 36, count 0 2006.202.00:04:17.95#ibcon#about to read 3, iclass 36, count 0 2006.202.00:04:17.98#ibcon#read 3, iclass 36, count 0 2006.202.00:04:17.98#ibcon#about to read 4, iclass 36, count 0 2006.202.00:04:17.98#ibcon#read 4, iclass 36, count 0 2006.202.00:04:17.98#ibcon#about to read 5, iclass 36, count 0 2006.202.00:04:17.98#ibcon#read 5, iclass 36, count 0 2006.202.00:04:17.98#ibcon#about to read 6, iclass 36, count 0 2006.202.00:04:17.98#ibcon#read 6, iclass 36, count 0 2006.202.00:04:17.98#ibcon#end of sib2, iclass 36, count 0 2006.202.00:04:17.98#ibcon#*after write, iclass 36, count 0 2006.202.00:04:17.98#ibcon#*before return 0, iclass 36, count 0 2006.202.00:04:17.98#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:04:17.98#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:04:17.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.00:04:17.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.00:04:17.98$vck44/valo=5,734.99 2006.202.00:04:17.98#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.202.00:04:17.98#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.202.00:04:17.98#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:17.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:17.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:17.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:17.98#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:04:17.98#ibcon#first serial, iclass 39, count 0 2006.202.00:04:17.98#ibcon#enter sib2, iclass 39, count 0 2006.202.00:04:17.98#ibcon#flushed, iclass 39, count 0 2006.202.00:04:17.98#ibcon#about to write, iclass 39, count 0 2006.202.00:04:17.98#ibcon#wrote, iclass 39, count 0 2006.202.00:04:17.98#ibcon#about to read 3, iclass 39, count 0 2006.202.00:04:18.00#ibcon#read 3, iclass 39, count 0 2006.202.00:04:18.00#ibcon#about to read 4, iclass 39, count 0 2006.202.00:04:18.00#ibcon#read 4, iclass 39, count 0 2006.202.00:04:18.00#ibcon#about to read 5, iclass 39, count 0 2006.202.00:04:18.00#ibcon#read 5, iclass 39, count 0 2006.202.00:04:18.00#ibcon#about to read 6, iclass 39, count 0 2006.202.00:04:18.00#ibcon#read 6, iclass 39, count 0 2006.202.00:04:18.00#ibcon#end of sib2, iclass 39, count 0 2006.202.00:04:18.00#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:04:18.00#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:04:18.00#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.00:04:18.00#ibcon#*before write, iclass 39, count 0 2006.202.00:04:18.00#ibcon#enter sib2, iclass 39, count 0 2006.202.00:04:18.00#ibcon#flushed, iclass 39, count 0 2006.202.00:04:18.00#ibcon#about to write, iclass 39, count 0 2006.202.00:04:18.00#ibcon#wrote, iclass 39, count 0 2006.202.00:04:18.00#ibcon#about to read 3, iclass 39, count 0 2006.202.00:04:18.04#ibcon#read 3, iclass 39, count 0 2006.202.00:04:18.04#ibcon#about to read 4, iclass 39, count 0 2006.202.00:04:18.04#ibcon#read 4, iclass 39, count 0 2006.202.00:04:18.04#ibcon#about to read 5, iclass 39, count 0 2006.202.00:04:18.04#ibcon#read 5, iclass 39, count 0 2006.202.00:04:18.04#ibcon#about to read 6, iclass 39, count 0 2006.202.00:04:18.04#ibcon#read 6, iclass 39, count 0 2006.202.00:04:18.04#ibcon#end of sib2, iclass 39, count 0 2006.202.00:04:18.04#ibcon#*after write, iclass 39, count 0 2006.202.00:04:18.04#ibcon#*before return 0, iclass 39, count 0 2006.202.00:04:18.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:18.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:18.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:04:18.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:04:18.04$vck44/va=5,4 2006.202.00:04:18.04#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.202.00:04:18.04#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.202.00:04:18.04#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:18.04#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:18.10#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:18.10#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:18.10#ibcon#enter wrdev, iclass 2, count 2 2006.202.00:04:18.10#ibcon#first serial, iclass 2, count 2 2006.202.00:04:18.10#ibcon#enter sib2, iclass 2, count 2 2006.202.00:04:18.10#ibcon#flushed, iclass 2, count 2 2006.202.00:04:18.10#ibcon#about to write, iclass 2, count 2 2006.202.00:04:18.10#ibcon#wrote, iclass 2, count 2 2006.202.00:04:18.10#ibcon#about to read 3, iclass 2, count 2 2006.202.00:04:18.12#ibcon#read 3, iclass 2, count 2 2006.202.00:04:18.12#ibcon#about to read 4, iclass 2, count 2 2006.202.00:04:18.12#ibcon#read 4, iclass 2, count 2 2006.202.00:04:18.12#ibcon#about to read 5, iclass 2, count 2 2006.202.00:04:18.12#ibcon#read 5, iclass 2, count 2 2006.202.00:04:18.12#ibcon#about to read 6, iclass 2, count 2 2006.202.00:04:18.12#ibcon#read 6, iclass 2, count 2 2006.202.00:04:18.12#ibcon#end of sib2, iclass 2, count 2 2006.202.00:04:18.12#ibcon#*mode == 0, iclass 2, count 2 2006.202.00:04:18.12#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.202.00:04:18.12#ibcon#[25=AT05-04\r\n] 2006.202.00:04:18.12#ibcon#*before write, iclass 2, count 2 2006.202.00:04:18.12#ibcon#enter sib2, iclass 2, count 2 2006.202.00:04:18.12#ibcon#flushed, iclass 2, count 2 2006.202.00:04:18.12#ibcon#about to write, iclass 2, count 2 2006.202.00:04:18.12#ibcon#wrote, iclass 2, count 2 2006.202.00:04:18.12#ibcon#about to read 3, iclass 2, count 2 2006.202.00:04:18.15#ibcon#read 3, iclass 2, count 2 2006.202.00:04:18.15#ibcon#about to read 4, iclass 2, count 2 2006.202.00:04:18.15#ibcon#read 4, iclass 2, count 2 2006.202.00:04:18.15#ibcon#about to read 5, iclass 2, count 2 2006.202.00:04:18.15#ibcon#read 5, iclass 2, count 2 2006.202.00:04:18.15#ibcon#about to read 6, iclass 2, count 2 2006.202.00:04:18.15#ibcon#read 6, iclass 2, count 2 2006.202.00:04:18.15#ibcon#end of sib2, iclass 2, count 2 2006.202.00:04:18.15#ibcon#*after write, iclass 2, count 2 2006.202.00:04:18.15#ibcon#*before return 0, iclass 2, count 2 2006.202.00:04:18.15#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:18.15#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:18.15#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.202.00:04:18.15#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:18.15#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:18.27#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:18.27#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:18.27#ibcon#enter wrdev, iclass 2, count 0 2006.202.00:04:18.27#ibcon#first serial, iclass 2, count 0 2006.202.00:04:18.27#ibcon#enter sib2, iclass 2, count 0 2006.202.00:04:18.27#ibcon#flushed, iclass 2, count 0 2006.202.00:04:18.27#ibcon#about to write, iclass 2, count 0 2006.202.00:04:18.27#ibcon#wrote, iclass 2, count 0 2006.202.00:04:18.27#ibcon#about to read 3, iclass 2, count 0 2006.202.00:04:18.29#ibcon#read 3, iclass 2, count 0 2006.202.00:04:18.29#ibcon#about to read 4, iclass 2, count 0 2006.202.00:04:18.29#ibcon#read 4, iclass 2, count 0 2006.202.00:04:18.29#ibcon#about to read 5, iclass 2, count 0 2006.202.00:04:18.29#ibcon#read 5, iclass 2, count 0 2006.202.00:04:18.29#ibcon#about to read 6, iclass 2, count 0 2006.202.00:04:18.29#ibcon#read 6, iclass 2, count 0 2006.202.00:04:18.29#ibcon#end of sib2, iclass 2, count 0 2006.202.00:04:18.29#ibcon#*mode == 0, iclass 2, count 0 2006.202.00:04:18.29#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.00:04:18.29#ibcon#[25=USB\r\n] 2006.202.00:04:18.29#ibcon#*before write, iclass 2, count 0 2006.202.00:04:18.29#ibcon#enter sib2, iclass 2, count 0 2006.202.00:04:18.29#ibcon#flushed, iclass 2, count 0 2006.202.00:04:18.29#ibcon#about to write, iclass 2, count 0 2006.202.00:04:18.29#ibcon#wrote, iclass 2, count 0 2006.202.00:04:18.29#ibcon#about to read 3, iclass 2, count 0 2006.202.00:04:18.32#ibcon#read 3, iclass 2, count 0 2006.202.00:04:18.32#ibcon#about to read 4, iclass 2, count 0 2006.202.00:04:18.32#ibcon#read 4, iclass 2, count 0 2006.202.00:04:18.32#ibcon#about to read 5, iclass 2, count 0 2006.202.00:04:18.32#ibcon#read 5, iclass 2, count 0 2006.202.00:04:18.32#ibcon#about to read 6, iclass 2, count 0 2006.202.00:04:18.32#ibcon#read 6, iclass 2, count 0 2006.202.00:04:18.32#ibcon#end of sib2, iclass 2, count 0 2006.202.00:04:18.32#ibcon#*after write, iclass 2, count 0 2006.202.00:04:18.32#ibcon#*before return 0, iclass 2, count 0 2006.202.00:04:18.32#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:18.32#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:18.32#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.00:04:18.32#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.00:04:18.32$vck44/valo=6,814.99 2006.202.00:04:18.32#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.202.00:04:18.32#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.202.00:04:18.32#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:18.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:18.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:18.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:18.32#ibcon#enter wrdev, iclass 5, count 0 2006.202.00:04:18.32#ibcon#first serial, iclass 5, count 0 2006.202.00:04:18.32#ibcon#enter sib2, iclass 5, count 0 2006.202.00:04:18.32#ibcon#flushed, iclass 5, count 0 2006.202.00:04:18.32#ibcon#about to write, iclass 5, count 0 2006.202.00:04:18.32#ibcon#wrote, iclass 5, count 0 2006.202.00:04:18.32#ibcon#about to read 3, iclass 5, count 0 2006.202.00:04:18.34#ibcon#read 3, iclass 5, count 0 2006.202.00:04:18.34#ibcon#about to read 4, iclass 5, count 0 2006.202.00:04:18.34#ibcon#read 4, iclass 5, count 0 2006.202.00:04:18.34#ibcon#about to read 5, iclass 5, count 0 2006.202.00:04:18.34#ibcon#read 5, iclass 5, count 0 2006.202.00:04:18.34#ibcon#about to read 6, iclass 5, count 0 2006.202.00:04:18.34#ibcon#read 6, iclass 5, count 0 2006.202.00:04:18.34#ibcon#end of sib2, iclass 5, count 0 2006.202.00:04:18.34#ibcon#*mode == 0, iclass 5, count 0 2006.202.00:04:18.34#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.00:04:18.34#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.00:04:18.34#ibcon#*before write, iclass 5, count 0 2006.202.00:04:18.34#ibcon#enter sib2, iclass 5, count 0 2006.202.00:04:18.34#ibcon#flushed, iclass 5, count 0 2006.202.00:04:18.34#ibcon#about to write, iclass 5, count 0 2006.202.00:04:18.34#ibcon#wrote, iclass 5, count 0 2006.202.00:04:18.34#ibcon#about to read 3, iclass 5, count 0 2006.202.00:04:18.38#ibcon#read 3, iclass 5, count 0 2006.202.00:04:18.38#ibcon#about to read 4, iclass 5, count 0 2006.202.00:04:18.38#ibcon#read 4, iclass 5, count 0 2006.202.00:04:18.38#ibcon#about to read 5, iclass 5, count 0 2006.202.00:04:18.38#ibcon#read 5, iclass 5, count 0 2006.202.00:04:18.38#ibcon#about to read 6, iclass 5, count 0 2006.202.00:04:18.38#ibcon#read 6, iclass 5, count 0 2006.202.00:04:18.38#ibcon#end of sib2, iclass 5, count 0 2006.202.00:04:18.38#ibcon#*after write, iclass 5, count 0 2006.202.00:04:18.38#ibcon#*before return 0, iclass 5, count 0 2006.202.00:04:18.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:18.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:18.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.00:04:18.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.00:04:18.38$vck44/va=6,5 2006.202.00:04:18.38#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.202.00:04:18.38#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.202.00:04:18.38#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:18.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:18.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:18.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:18.44#ibcon#enter wrdev, iclass 7, count 2 2006.202.00:04:18.44#ibcon#first serial, iclass 7, count 2 2006.202.00:04:18.44#ibcon#enter sib2, iclass 7, count 2 2006.202.00:04:18.44#ibcon#flushed, iclass 7, count 2 2006.202.00:04:18.44#ibcon#about to write, iclass 7, count 2 2006.202.00:04:18.44#ibcon#wrote, iclass 7, count 2 2006.202.00:04:18.44#ibcon#about to read 3, iclass 7, count 2 2006.202.00:04:18.46#ibcon#read 3, iclass 7, count 2 2006.202.00:04:18.46#ibcon#about to read 4, iclass 7, count 2 2006.202.00:04:18.46#ibcon#read 4, iclass 7, count 2 2006.202.00:04:18.46#ibcon#about to read 5, iclass 7, count 2 2006.202.00:04:18.46#ibcon#read 5, iclass 7, count 2 2006.202.00:04:18.46#ibcon#about to read 6, iclass 7, count 2 2006.202.00:04:18.46#ibcon#read 6, iclass 7, count 2 2006.202.00:04:18.46#ibcon#end of sib2, iclass 7, count 2 2006.202.00:04:18.46#ibcon#*mode == 0, iclass 7, count 2 2006.202.00:04:18.46#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.202.00:04:18.46#ibcon#[25=AT06-05\r\n] 2006.202.00:04:18.46#ibcon#*before write, iclass 7, count 2 2006.202.00:04:18.46#ibcon#enter sib2, iclass 7, count 2 2006.202.00:04:18.46#ibcon#flushed, iclass 7, count 2 2006.202.00:04:18.46#ibcon#about to write, iclass 7, count 2 2006.202.00:04:18.46#ibcon#wrote, iclass 7, count 2 2006.202.00:04:18.46#ibcon#about to read 3, iclass 7, count 2 2006.202.00:04:18.49#ibcon#read 3, iclass 7, count 2 2006.202.00:04:18.49#ibcon#about to read 4, iclass 7, count 2 2006.202.00:04:18.49#ibcon#read 4, iclass 7, count 2 2006.202.00:04:18.49#ibcon#about to read 5, iclass 7, count 2 2006.202.00:04:18.49#ibcon#read 5, iclass 7, count 2 2006.202.00:04:18.49#ibcon#about to read 6, iclass 7, count 2 2006.202.00:04:18.49#ibcon#read 6, iclass 7, count 2 2006.202.00:04:18.49#ibcon#end of sib2, iclass 7, count 2 2006.202.00:04:18.49#ibcon#*after write, iclass 7, count 2 2006.202.00:04:18.49#ibcon#*before return 0, iclass 7, count 2 2006.202.00:04:18.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:18.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:18.49#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.202.00:04:18.49#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:18.49#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:18.61#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:18.61#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:18.61#ibcon#enter wrdev, iclass 7, count 0 2006.202.00:04:18.61#ibcon#first serial, iclass 7, count 0 2006.202.00:04:18.61#ibcon#enter sib2, iclass 7, count 0 2006.202.00:04:18.61#ibcon#flushed, iclass 7, count 0 2006.202.00:04:18.61#ibcon#about to write, iclass 7, count 0 2006.202.00:04:18.61#ibcon#wrote, iclass 7, count 0 2006.202.00:04:18.61#ibcon#about to read 3, iclass 7, count 0 2006.202.00:04:18.63#ibcon#read 3, iclass 7, count 0 2006.202.00:04:18.63#ibcon#about to read 4, iclass 7, count 0 2006.202.00:04:18.63#ibcon#read 4, iclass 7, count 0 2006.202.00:04:18.63#ibcon#about to read 5, iclass 7, count 0 2006.202.00:04:18.63#ibcon#read 5, iclass 7, count 0 2006.202.00:04:18.63#ibcon#about to read 6, iclass 7, count 0 2006.202.00:04:18.63#ibcon#read 6, iclass 7, count 0 2006.202.00:04:18.63#ibcon#end of sib2, iclass 7, count 0 2006.202.00:04:18.63#ibcon#*mode == 0, iclass 7, count 0 2006.202.00:04:18.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.00:04:18.63#ibcon#[25=USB\r\n] 2006.202.00:04:18.63#ibcon#*before write, iclass 7, count 0 2006.202.00:04:18.63#ibcon#enter sib2, iclass 7, count 0 2006.202.00:04:18.63#ibcon#flushed, iclass 7, count 0 2006.202.00:04:18.63#ibcon#about to write, iclass 7, count 0 2006.202.00:04:18.63#ibcon#wrote, iclass 7, count 0 2006.202.00:04:18.63#ibcon#about to read 3, iclass 7, count 0 2006.202.00:04:18.66#ibcon#read 3, iclass 7, count 0 2006.202.00:04:18.66#ibcon#about to read 4, iclass 7, count 0 2006.202.00:04:18.66#ibcon#read 4, iclass 7, count 0 2006.202.00:04:18.66#ibcon#about to read 5, iclass 7, count 0 2006.202.00:04:18.66#ibcon#read 5, iclass 7, count 0 2006.202.00:04:18.66#ibcon#about to read 6, iclass 7, count 0 2006.202.00:04:18.66#ibcon#read 6, iclass 7, count 0 2006.202.00:04:18.66#ibcon#end of sib2, iclass 7, count 0 2006.202.00:04:18.66#ibcon#*after write, iclass 7, count 0 2006.202.00:04:18.66#ibcon#*before return 0, iclass 7, count 0 2006.202.00:04:18.66#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:18.66#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:18.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.00:04:18.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.00:04:18.66$vck44/valo=7,864.99 2006.202.00:04:18.66#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.202.00:04:18.66#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.202.00:04:18.66#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:18.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:18.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:18.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:18.66#ibcon#enter wrdev, iclass 11, count 0 2006.202.00:04:18.66#ibcon#first serial, iclass 11, count 0 2006.202.00:04:18.66#ibcon#enter sib2, iclass 11, count 0 2006.202.00:04:18.66#ibcon#flushed, iclass 11, count 0 2006.202.00:04:18.66#ibcon#about to write, iclass 11, count 0 2006.202.00:04:18.66#ibcon#wrote, iclass 11, count 0 2006.202.00:04:18.66#ibcon#about to read 3, iclass 11, count 0 2006.202.00:04:18.68#ibcon#read 3, iclass 11, count 0 2006.202.00:04:18.68#ibcon#about to read 4, iclass 11, count 0 2006.202.00:04:18.68#ibcon#read 4, iclass 11, count 0 2006.202.00:04:18.68#ibcon#about to read 5, iclass 11, count 0 2006.202.00:04:18.68#ibcon#read 5, iclass 11, count 0 2006.202.00:04:18.68#ibcon#about to read 6, iclass 11, count 0 2006.202.00:04:18.68#ibcon#read 6, iclass 11, count 0 2006.202.00:04:18.68#ibcon#end of sib2, iclass 11, count 0 2006.202.00:04:18.68#ibcon#*mode == 0, iclass 11, count 0 2006.202.00:04:18.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.00:04:18.68#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.00:04:18.68#ibcon#*before write, iclass 11, count 0 2006.202.00:04:18.68#ibcon#enter sib2, iclass 11, count 0 2006.202.00:04:18.68#ibcon#flushed, iclass 11, count 0 2006.202.00:04:18.68#ibcon#about to write, iclass 11, count 0 2006.202.00:04:18.68#ibcon#wrote, iclass 11, count 0 2006.202.00:04:18.68#ibcon#about to read 3, iclass 11, count 0 2006.202.00:04:18.72#ibcon#read 3, iclass 11, count 0 2006.202.00:04:18.72#ibcon#about to read 4, iclass 11, count 0 2006.202.00:04:18.72#ibcon#read 4, iclass 11, count 0 2006.202.00:04:18.72#ibcon#about to read 5, iclass 11, count 0 2006.202.00:04:18.72#ibcon#read 5, iclass 11, count 0 2006.202.00:04:18.72#ibcon#about to read 6, iclass 11, count 0 2006.202.00:04:18.72#ibcon#read 6, iclass 11, count 0 2006.202.00:04:18.72#ibcon#end of sib2, iclass 11, count 0 2006.202.00:04:18.72#ibcon#*after write, iclass 11, count 0 2006.202.00:04:18.72#ibcon#*before return 0, iclass 11, count 0 2006.202.00:04:18.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:18.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:18.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.00:04:18.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.00:04:18.72$vck44/va=7,5 2006.202.00:04:18.72#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.202.00:04:18.72#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.202.00:04:18.72#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:18.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:18.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:18.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:18.78#ibcon#enter wrdev, iclass 13, count 2 2006.202.00:04:18.78#ibcon#first serial, iclass 13, count 2 2006.202.00:04:18.78#ibcon#enter sib2, iclass 13, count 2 2006.202.00:04:18.78#ibcon#flushed, iclass 13, count 2 2006.202.00:04:18.78#ibcon#about to write, iclass 13, count 2 2006.202.00:04:18.78#ibcon#wrote, iclass 13, count 2 2006.202.00:04:18.78#ibcon#about to read 3, iclass 13, count 2 2006.202.00:04:18.80#ibcon#read 3, iclass 13, count 2 2006.202.00:04:18.80#ibcon#about to read 4, iclass 13, count 2 2006.202.00:04:18.80#ibcon#read 4, iclass 13, count 2 2006.202.00:04:18.80#ibcon#about to read 5, iclass 13, count 2 2006.202.00:04:18.80#ibcon#read 5, iclass 13, count 2 2006.202.00:04:18.80#ibcon#about to read 6, iclass 13, count 2 2006.202.00:04:18.80#ibcon#read 6, iclass 13, count 2 2006.202.00:04:18.80#ibcon#end of sib2, iclass 13, count 2 2006.202.00:04:18.80#ibcon#*mode == 0, iclass 13, count 2 2006.202.00:04:18.80#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.202.00:04:18.80#ibcon#[25=AT07-05\r\n] 2006.202.00:04:18.80#ibcon#*before write, iclass 13, count 2 2006.202.00:04:18.80#ibcon#enter sib2, iclass 13, count 2 2006.202.00:04:18.80#ibcon#flushed, iclass 13, count 2 2006.202.00:04:18.80#ibcon#about to write, iclass 13, count 2 2006.202.00:04:18.80#ibcon#wrote, iclass 13, count 2 2006.202.00:04:18.80#ibcon#about to read 3, iclass 13, count 2 2006.202.00:04:18.83#ibcon#read 3, iclass 13, count 2 2006.202.00:04:18.83#ibcon#about to read 4, iclass 13, count 2 2006.202.00:04:18.83#ibcon#read 4, iclass 13, count 2 2006.202.00:04:18.83#ibcon#about to read 5, iclass 13, count 2 2006.202.00:04:18.83#ibcon#read 5, iclass 13, count 2 2006.202.00:04:18.83#ibcon#about to read 6, iclass 13, count 2 2006.202.00:04:18.83#ibcon#read 6, iclass 13, count 2 2006.202.00:04:18.83#ibcon#end of sib2, iclass 13, count 2 2006.202.00:04:18.83#ibcon#*after write, iclass 13, count 2 2006.202.00:04:18.83#ibcon#*before return 0, iclass 13, count 2 2006.202.00:04:18.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:18.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:18.88#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.202.00:04:18.88#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:18.88#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:19.00#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:19.00#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:19.00#ibcon#enter wrdev, iclass 13, count 0 2006.202.00:04:19.00#ibcon#first serial, iclass 13, count 0 2006.202.00:04:19.00#ibcon#enter sib2, iclass 13, count 0 2006.202.00:04:19.00#ibcon#flushed, iclass 13, count 0 2006.202.00:04:19.00#ibcon#about to write, iclass 13, count 0 2006.202.00:04:19.00#ibcon#wrote, iclass 13, count 0 2006.202.00:04:19.00#ibcon#about to read 3, iclass 13, count 0 2006.202.00:04:19.02#ibcon#read 3, iclass 13, count 0 2006.202.00:04:19.02#ibcon#about to read 4, iclass 13, count 0 2006.202.00:04:19.02#ibcon#read 4, iclass 13, count 0 2006.202.00:04:19.02#ibcon#about to read 5, iclass 13, count 0 2006.202.00:04:19.02#ibcon#read 5, iclass 13, count 0 2006.202.00:04:19.02#ibcon#about to read 6, iclass 13, count 0 2006.202.00:04:19.02#ibcon#read 6, iclass 13, count 0 2006.202.00:04:19.02#ibcon#end of sib2, iclass 13, count 0 2006.202.00:04:19.02#ibcon#*mode == 0, iclass 13, count 0 2006.202.00:04:19.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.00:04:19.02#ibcon#[25=USB\r\n] 2006.202.00:04:19.02#ibcon#*before write, iclass 13, count 0 2006.202.00:04:19.02#ibcon#enter sib2, iclass 13, count 0 2006.202.00:04:19.02#ibcon#flushed, iclass 13, count 0 2006.202.00:04:19.02#ibcon#about to write, iclass 13, count 0 2006.202.00:04:19.02#ibcon#wrote, iclass 13, count 0 2006.202.00:04:19.02#ibcon#about to read 3, iclass 13, count 0 2006.202.00:04:19.05#ibcon#read 3, iclass 13, count 0 2006.202.00:04:19.05#ibcon#about to read 4, iclass 13, count 0 2006.202.00:04:19.05#ibcon#read 4, iclass 13, count 0 2006.202.00:04:19.05#ibcon#about to read 5, iclass 13, count 0 2006.202.00:04:19.05#ibcon#read 5, iclass 13, count 0 2006.202.00:04:19.05#ibcon#about to read 6, iclass 13, count 0 2006.202.00:04:19.05#ibcon#read 6, iclass 13, count 0 2006.202.00:04:19.05#ibcon#end of sib2, iclass 13, count 0 2006.202.00:04:19.05#ibcon#*after write, iclass 13, count 0 2006.202.00:04:19.05#ibcon#*before return 0, iclass 13, count 0 2006.202.00:04:19.05#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:19.05#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:19.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.00:04:19.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.00:04:19.05$vck44/valo=8,884.99 2006.202.00:04:19.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.00:04:19.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.00:04:19.05#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:19.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:19.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:19.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:19.05#ibcon#enter wrdev, iclass 15, count 0 2006.202.00:04:19.05#ibcon#first serial, iclass 15, count 0 2006.202.00:04:19.05#ibcon#enter sib2, iclass 15, count 0 2006.202.00:04:19.05#ibcon#flushed, iclass 15, count 0 2006.202.00:04:19.05#ibcon#about to write, iclass 15, count 0 2006.202.00:04:19.05#ibcon#wrote, iclass 15, count 0 2006.202.00:04:19.05#ibcon#about to read 3, iclass 15, count 0 2006.202.00:04:19.07#ibcon#read 3, iclass 15, count 0 2006.202.00:04:19.07#ibcon#about to read 4, iclass 15, count 0 2006.202.00:04:19.07#ibcon#read 4, iclass 15, count 0 2006.202.00:04:19.07#ibcon#about to read 5, iclass 15, count 0 2006.202.00:04:19.07#ibcon#read 5, iclass 15, count 0 2006.202.00:04:19.07#ibcon#about to read 6, iclass 15, count 0 2006.202.00:04:19.07#ibcon#read 6, iclass 15, count 0 2006.202.00:04:19.07#ibcon#end of sib2, iclass 15, count 0 2006.202.00:04:19.07#ibcon#*mode == 0, iclass 15, count 0 2006.202.00:04:19.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.00:04:19.07#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.00:04:19.07#ibcon#*before write, iclass 15, count 0 2006.202.00:04:19.07#ibcon#enter sib2, iclass 15, count 0 2006.202.00:04:19.07#ibcon#flushed, iclass 15, count 0 2006.202.00:04:19.07#ibcon#about to write, iclass 15, count 0 2006.202.00:04:19.07#ibcon#wrote, iclass 15, count 0 2006.202.00:04:19.07#ibcon#about to read 3, iclass 15, count 0 2006.202.00:04:19.11#ibcon#read 3, iclass 15, count 0 2006.202.00:04:19.11#ibcon#about to read 4, iclass 15, count 0 2006.202.00:04:19.11#ibcon#read 4, iclass 15, count 0 2006.202.00:04:19.11#ibcon#about to read 5, iclass 15, count 0 2006.202.00:04:19.11#ibcon#read 5, iclass 15, count 0 2006.202.00:04:19.11#ibcon#about to read 6, iclass 15, count 0 2006.202.00:04:19.11#ibcon#read 6, iclass 15, count 0 2006.202.00:04:19.11#ibcon#end of sib2, iclass 15, count 0 2006.202.00:04:19.11#ibcon#*after write, iclass 15, count 0 2006.202.00:04:19.11#ibcon#*before return 0, iclass 15, count 0 2006.202.00:04:19.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:19.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:19.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.00:04:19.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.00:04:19.11$vck44/va=8,4 2006.202.00:04:19.11#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.202.00:04:19.11#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.202.00:04:19.11#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:19.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:04:19.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:04:19.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:04:19.17#ibcon#enter wrdev, iclass 17, count 2 2006.202.00:04:19.17#ibcon#first serial, iclass 17, count 2 2006.202.00:04:19.17#ibcon#enter sib2, iclass 17, count 2 2006.202.00:04:19.17#ibcon#flushed, iclass 17, count 2 2006.202.00:04:19.17#ibcon#about to write, iclass 17, count 2 2006.202.00:04:19.17#ibcon#wrote, iclass 17, count 2 2006.202.00:04:19.17#ibcon#about to read 3, iclass 17, count 2 2006.202.00:04:19.19#ibcon#read 3, iclass 17, count 2 2006.202.00:04:19.19#ibcon#about to read 4, iclass 17, count 2 2006.202.00:04:19.19#ibcon#read 4, iclass 17, count 2 2006.202.00:04:19.19#ibcon#about to read 5, iclass 17, count 2 2006.202.00:04:19.19#ibcon#read 5, iclass 17, count 2 2006.202.00:04:19.19#ibcon#about to read 6, iclass 17, count 2 2006.202.00:04:19.19#ibcon#read 6, iclass 17, count 2 2006.202.00:04:19.19#ibcon#end of sib2, iclass 17, count 2 2006.202.00:04:19.19#ibcon#*mode == 0, iclass 17, count 2 2006.202.00:04:19.19#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.202.00:04:19.19#ibcon#[25=AT08-04\r\n] 2006.202.00:04:19.19#ibcon#*before write, iclass 17, count 2 2006.202.00:04:19.19#ibcon#enter sib2, iclass 17, count 2 2006.202.00:04:19.19#ibcon#flushed, iclass 17, count 2 2006.202.00:04:19.19#ibcon#about to write, iclass 17, count 2 2006.202.00:04:19.19#ibcon#wrote, iclass 17, count 2 2006.202.00:04:19.19#ibcon#about to read 3, iclass 17, count 2 2006.202.00:04:19.22#ibcon#read 3, iclass 17, count 2 2006.202.00:04:19.22#ibcon#about to read 4, iclass 17, count 2 2006.202.00:04:19.22#ibcon#read 4, iclass 17, count 2 2006.202.00:04:19.22#ibcon#about to read 5, iclass 17, count 2 2006.202.00:04:19.22#ibcon#read 5, iclass 17, count 2 2006.202.00:04:19.22#ibcon#about to read 6, iclass 17, count 2 2006.202.00:04:19.22#ibcon#read 6, iclass 17, count 2 2006.202.00:04:19.22#ibcon#end of sib2, iclass 17, count 2 2006.202.00:04:19.22#ibcon#*after write, iclass 17, count 2 2006.202.00:04:19.22#ibcon#*before return 0, iclass 17, count 2 2006.202.00:04:19.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:04:19.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:04:19.22#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.202.00:04:19.22#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:19.22#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:04:19.34#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:04:19.34#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:04:19.34#ibcon#enter wrdev, iclass 17, count 0 2006.202.00:04:19.34#ibcon#first serial, iclass 17, count 0 2006.202.00:04:19.34#ibcon#enter sib2, iclass 17, count 0 2006.202.00:04:19.34#ibcon#flushed, iclass 17, count 0 2006.202.00:04:19.34#ibcon#about to write, iclass 17, count 0 2006.202.00:04:19.34#ibcon#wrote, iclass 17, count 0 2006.202.00:04:19.34#ibcon#about to read 3, iclass 17, count 0 2006.202.00:04:19.36#ibcon#read 3, iclass 17, count 0 2006.202.00:04:19.36#ibcon#about to read 4, iclass 17, count 0 2006.202.00:04:19.36#ibcon#read 4, iclass 17, count 0 2006.202.00:04:19.36#ibcon#about to read 5, iclass 17, count 0 2006.202.00:04:19.36#ibcon#read 5, iclass 17, count 0 2006.202.00:04:19.36#ibcon#about to read 6, iclass 17, count 0 2006.202.00:04:19.36#ibcon#read 6, iclass 17, count 0 2006.202.00:04:19.36#ibcon#end of sib2, iclass 17, count 0 2006.202.00:04:19.36#ibcon#*mode == 0, iclass 17, count 0 2006.202.00:04:19.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.00:04:19.36#ibcon#[25=USB\r\n] 2006.202.00:04:19.36#ibcon#*before write, iclass 17, count 0 2006.202.00:04:19.36#ibcon#enter sib2, iclass 17, count 0 2006.202.00:04:19.36#ibcon#flushed, iclass 17, count 0 2006.202.00:04:19.36#ibcon#about to write, iclass 17, count 0 2006.202.00:04:19.36#ibcon#wrote, iclass 17, count 0 2006.202.00:04:19.36#ibcon#about to read 3, iclass 17, count 0 2006.202.00:04:19.39#ibcon#read 3, iclass 17, count 0 2006.202.00:04:19.39#ibcon#about to read 4, iclass 17, count 0 2006.202.00:04:19.39#ibcon#read 4, iclass 17, count 0 2006.202.00:04:19.39#ibcon#about to read 5, iclass 17, count 0 2006.202.00:04:19.39#ibcon#read 5, iclass 17, count 0 2006.202.00:04:19.39#ibcon#about to read 6, iclass 17, count 0 2006.202.00:04:19.39#ibcon#read 6, iclass 17, count 0 2006.202.00:04:19.39#ibcon#end of sib2, iclass 17, count 0 2006.202.00:04:19.39#ibcon#*after write, iclass 17, count 0 2006.202.00:04:19.39#ibcon#*before return 0, iclass 17, count 0 2006.202.00:04:19.39#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:04:19.39#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:04:19.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.00:04:19.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.00:04:19.39$vck44/vblo=1,629.99 2006.202.00:04:19.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.202.00:04:19.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.202.00:04:19.39#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:19.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:19.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:19.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:19.39#ibcon#enter wrdev, iclass 19, count 0 2006.202.00:04:19.39#ibcon#first serial, iclass 19, count 0 2006.202.00:04:19.39#ibcon#enter sib2, iclass 19, count 0 2006.202.00:04:19.39#ibcon#flushed, iclass 19, count 0 2006.202.00:04:19.39#ibcon#about to write, iclass 19, count 0 2006.202.00:04:19.39#ibcon#wrote, iclass 19, count 0 2006.202.00:04:19.39#ibcon#about to read 3, iclass 19, count 0 2006.202.00:04:19.41#ibcon#read 3, iclass 19, count 0 2006.202.00:04:19.41#ibcon#about to read 4, iclass 19, count 0 2006.202.00:04:19.41#ibcon#read 4, iclass 19, count 0 2006.202.00:04:19.41#ibcon#about to read 5, iclass 19, count 0 2006.202.00:04:19.41#ibcon#read 5, iclass 19, count 0 2006.202.00:04:19.41#ibcon#about to read 6, iclass 19, count 0 2006.202.00:04:19.41#ibcon#read 6, iclass 19, count 0 2006.202.00:04:19.41#ibcon#end of sib2, iclass 19, count 0 2006.202.00:04:19.41#ibcon#*mode == 0, iclass 19, count 0 2006.202.00:04:19.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.00:04:19.41#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.00:04:19.41#ibcon#*before write, iclass 19, count 0 2006.202.00:04:19.41#ibcon#enter sib2, iclass 19, count 0 2006.202.00:04:19.41#ibcon#flushed, iclass 19, count 0 2006.202.00:04:19.41#ibcon#about to write, iclass 19, count 0 2006.202.00:04:19.41#ibcon#wrote, iclass 19, count 0 2006.202.00:04:19.41#ibcon#about to read 3, iclass 19, count 0 2006.202.00:04:19.45#ibcon#read 3, iclass 19, count 0 2006.202.00:04:19.45#ibcon#about to read 4, iclass 19, count 0 2006.202.00:04:19.45#ibcon#read 4, iclass 19, count 0 2006.202.00:04:19.45#ibcon#about to read 5, iclass 19, count 0 2006.202.00:04:19.45#ibcon#read 5, iclass 19, count 0 2006.202.00:04:19.45#ibcon#about to read 6, iclass 19, count 0 2006.202.00:04:19.45#ibcon#read 6, iclass 19, count 0 2006.202.00:04:19.45#ibcon#end of sib2, iclass 19, count 0 2006.202.00:04:19.45#ibcon#*after write, iclass 19, count 0 2006.202.00:04:19.45#ibcon#*before return 0, iclass 19, count 0 2006.202.00:04:19.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:19.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:04:19.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.00:04:19.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.00:04:19.45$vck44/vb=1,4 2006.202.00:04:19.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.202.00:04:19.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.202.00:04:19.45#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:19.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:19.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:19.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:19.45#ibcon#enter wrdev, iclass 21, count 2 2006.202.00:04:19.45#ibcon#first serial, iclass 21, count 2 2006.202.00:04:19.45#ibcon#enter sib2, iclass 21, count 2 2006.202.00:04:19.45#ibcon#flushed, iclass 21, count 2 2006.202.00:04:19.45#ibcon#about to write, iclass 21, count 2 2006.202.00:04:19.45#ibcon#wrote, iclass 21, count 2 2006.202.00:04:19.45#ibcon#about to read 3, iclass 21, count 2 2006.202.00:04:19.47#ibcon#read 3, iclass 21, count 2 2006.202.00:04:19.47#ibcon#about to read 4, iclass 21, count 2 2006.202.00:04:19.47#ibcon#read 4, iclass 21, count 2 2006.202.00:04:19.47#ibcon#about to read 5, iclass 21, count 2 2006.202.00:04:19.47#ibcon#read 5, iclass 21, count 2 2006.202.00:04:19.47#ibcon#about to read 6, iclass 21, count 2 2006.202.00:04:19.47#ibcon#read 6, iclass 21, count 2 2006.202.00:04:19.47#ibcon#end of sib2, iclass 21, count 2 2006.202.00:04:19.47#ibcon#*mode == 0, iclass 21, count 2 2006.202.00:04:19.47#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.202.00:04:19.47#ibcon#[27=AT01-04\r\n] 2006.202.00:04:19.47#ibcon#*before write, iclass 21, count 2 2006.202.00:04:19.47#ibcon#enter sib2, iclass 21, count 2 2006.202.00:04:19.47#ibcon#flushed, iclass 21, count 2 2006.202.00:04:19.47#ibcon#about to write, iclass 21, count 2 2006.202.00:04:19.47#ibcon#wrote, iclass 21, count 2 2006.202.00:04:19.47#ibcon#about to read 3, iclass 21, count 2 2006.202.00:04:19.50#ibcon#read 3, iclass 21, count 2 2006.202.00:04:19.50#ibcon#about to read 4, iclass 21, count 2 2006.202.00:04:19.50#ibcon#read 4, iclass 21, count 2 2006.202.00:04:19.50#ibcon#about to read 5, iclass 21, count 2 2006.202.00:04:19.50#ibcon#read 5, iclass 21, count 2 2006.202.00:04:19.50#ibcon#about to read 6, iclass 21, count 2 2006.202.00:04:19.50#ibcon#read 6, iclass 21, count 2 2006.202.00:04:19.50#ibcon#end of sib2, iclass 21, count 2 2006.202.00:04:19.50#ibcon#*after write, iclass 21, count 2 2006.202.00:04:19.50#ibcon#*before return 0, iclass 21, count 2 2006.202.00:04:19.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:19.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:04:19.50#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.202.00:04:19.50#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:19.50#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:19.62#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:19.62#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:19.62#ibcon#enter wrdev, iclass 21, count 0 2006.202.00:04:19.62#ibcon#first serial, iclass 21, count 0 2006.202.00:04:19.62#ibcon#enter sib2, iclass 21, count 0 2006.202.00:04:19.62#ibcon#flushed, iclass 21, count 0 2006.202.00:04:19.62#ibcon#about to write, iclass 21, count 0 2006.202.00:04:19.62#ibcon#wrote, iclass 21, count 0 2006.202.00:04:19.62#ibcon#about to read 3, iclass 21, count 0 2006.202.00:04:19.64#ibcon#read 3, iclass 21, count 0 2006.202.00:04:19.64#ibcon#about to read 4, iclass 21, count 0 2006.202.00:04:19.64#ibcon#read 4, iclass 21, count 0 2006.202.00:04:19.64#ibcon#about to read 5, iclass 21, count 0 2006.202.00:04:19.64#ibcon#read 5, iclass 21, count 0 2006.202.00:04:19.64#ibcon#about to read 6, iclass 21, count 0 2006.202.00:04:19.64#ibcon#read 6, iclass 21, count 0 2006.202.00:04:19.64#ibcon#end of sib2, iclass 21, count 0 2006.202.00:04:19.64#ibcon#*mode == 0, iclass 21, count 0 2006.202.00:04:19.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.00:04:19.64#ibcon#[27=USB\r\n] 2006.202.00:04:19.64#ibcon#*before write, iclass 21, count 0 2006.202.00:04:19.64#ibcon#enter sib2, iclass 21, count 0 2006.202.00:04:19.64#ibcon#flushed, iclass 21, count 0 2006.202.00:04:19.64#ibcon#about to write, iclass 21, count 0 2006.202.00:04:19.64#ibcon#wrote, iclass 21, count 0 2006.202.00:04:19.64#ibcon#about to read 3, iclass 21, count 0 2006.202.00:04:19.67#ibcon#read 3, iclass 21, count 0 2006.202.00:04:19.67#ibcon#about to read 4, iclass 21, count 0 2006.202.00:04:19.67#ibcon#read 4, iclass 21, count 0 2006.202.00:04:19.67#ibcon#about to read 5, iclass 21, count 0 2006.202.00:04:19.67#ibcon#read 5, iclass 21, count 0 2006.202.00:04:19.67#ibcon#about to read 6, iclass 21, count 0 2006.202.00:04:19.67#ibcon#read 6, iclass 21, count 0 2006.202.00:04:19.67#ibcon#end of sib2, iclass 21, count 0 2006.202.00:04:19.67#ibcon#*after write, iclass 21, count 0 2006.202.00:04:19.67#ibcon#*before return 0, iclass 21, count 0 2006.202.00:04:19.67#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:19.67#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:04:19.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.00:04:19.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.00:04:19.67$vck44/vblo=2,634.99 2006.202.00:04:19.67#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.00:04:19.67#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.00:04:19.67#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:19.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:19.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:19.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:19.67#ibcon#enter wrdev, iclass 23, count 0 2006.202.00:04:19.67#ibcon#first serial, iclass 23, count 0 2006.202.00:04:19.67#ibcon#enter sib2, iclass 23, count 0 2006.202.00:04:19.67#ibcon#flushed, iclass 23, count 0 2006.202.00:04:19.67#ibcon#about to write, iclass 23, count 0 2006.202.00:04:19.67#ibcon#wrote, iclass 23, count 0 2006.202.00:04:19.67#ibcon#about to read 3, iclass 23, count 0 2006.202.00:04:19.69#ibcon#read 3, iclass 23, count 0 2006.202.00:04:19.69#ibcon#about to read 4, iclass 23, count 0 2006.202.00:04:19.69#ibcon#read 4, iclass 23, count 0 2006.202.00:04:19.69#ibcon#about to read 5, iclass 23, count 0 2006.202.00:04:19.69#ibcon#read 5, iclass 23, count 0 2006.202.00:04:19.69#ibcon#about to read 6, iclass 23, count 0 2006.202.00:04:19.69#ibcon#read 6, iclass 23, count 0 2006.202.00:04:19.69#ibcon#end of sib2, iclass 23, count 0 2006.202.00:04:19.69#ibcon#*mode == 0, iclass 23, count 0 2006.202.00:04:19.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.00:04:19.69#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.00:04:19.69#ibcon#*before write, iclass 23, count 0 2006.202.00:04:19.69#ibcon#enter sib2, iclass 23, count 0 2006.202.00:04:19.69#ibcon#flushed, iclass 23, count 0 2006.202.00:04:19.69#ibcon#about to write, iclass 23, count 0 2006.202.00:04:19.69#ibcon#wrote, iclass 23, count 0 2006.202.00:04:19.69#ibcon#about to read 3, iclass 23, count 0 2006.202.00:04:19.73#ibcon#read 3, iclass 23, count 0 2006.202.00:04:19.73#ibcon#about to read 4, iclass 23, count 0 2006.202.00:04:19.73#ibcon#read 4, iclass 23, count 0 2006.202.00:04:19.73#ibcon#about to read 5, iclass 23, count 0 2006.202.00:04:19.73#ibcon#read 5, iclass 23, count 0 2006.202.00:04:19.73#ibcon#about to read 6, iclass 23, count 0 2006.202.00:04:19.73#ibcon#read 6, iclass 23, count 0 2006.202.00:04:19.73#ibcon#end of sib2, iclass 23, count 0 2006.202.00:04:19.73#ibcon#*after write, iclass 23, count 0 2006.202.00:04:19.73#ibcon#*before return 0, iclass 23, count 0 2006.202.00:04:19.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:19.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:04:19.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.00:04:19.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.00:04:19.73$vck44/vb=2,5 2006.202.00:04:19.73#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.202.00:04:19.73#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.202.00:04:19.73#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:19.73#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:19.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:19.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:19.79#ibcon#enter wrdev, iclass 25, count 2 2006.202.00:04:19.79#ibcon#first serial, iclass 25, count 2 2006.202.00:04:19.79#ibcon#enter sib2, iclass 25, count 2 2006.202.00:04:19.79#ibcon#flushed, iclass 25, count 2 2006.202.00:04:19.79#ibcon#about to write, iclass 25, count 2 2006.202.00:04:19.79#ibcon#wrote, iclass 25, count 2 2006.202.00:04:19.79#ibcon#about to read 3, iclass 25, count 2 2006.202.00:04:19.81#ibcon#read 3, iclass 25, count 2 2006.202.00:04:19.81#ibcon#about to read 4, iclass 25, count 2 2006.202.00:04:19.81#ibcon#read 4, iclass 25, count 2 2006.202.00:04:19.81#ibcon#about to read 5, iclass 25, count 2 2006.202.00:04:19.81#ibcon#read 5, iclass 25, count 2 2006.202.00:04:19.81#ibcon#about to read 6, iclass 25, count 2 2006.202.00:04:19.81#ibcon#read 6, iclass 25, count 2 2006.202.00:04:19.81#ibcon#end of sib2, iclass 25, count 2 2006.202.00:04:19.81#ibcon#*mode == 0, iclass 25, count 2 2006.202.00:04:19.81#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.202.00:04:19.81#ibcon#[27=AT02-05\r\n] 2006.202.00:04:19.81#ibcon#*before write, iclass 25, count 2 2006.202.00:04:19.81#ibcon#enter sib2, iclass 25, count 2 2006.202.00:04:19.81#ibcon#flushed, iclass 25, count 2 2006.202.00:04:19.81#ibcon#about to write, iclass 25, count 2 2006.202.00:04:19.81#ibcon#wrote, iclass 25, count 2 2006.202.00:04:19.81#ibcon#about to read 3, iclass 25, count 2 2006.202.00:04:19.84#ibcon#read 3, iclass 25, count 2 2006.202.00:04:19.84#ibcon#about to read 4, iclass 25, count 2 2006.202.00:04:19.84#ibcon#read 4, iclass 25, count 2 2006.202.00:04:19.84#ibcon#about to read 5, iclass 25, count 2 2006.202.00:04:19.84#ibcon#read 5, iclass 25, count 2 2006.202.00:04:19.84#ibcon#about to read 6, iclass 25, count 2 2006.202.00:04:19.84#ibcon#read 6, iclass 25, count 2 2006.202.00:04:19.84#ibcon#end of sib2, iclass 25, count 2 2006.202.00:04:19.84#ibcon#*after write, iclass 25, count 2 2006.202.00:04:19.84#ibcon#*before return 0, iclass 25, count 2 2006.202.00:04:19.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:19.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:04:19.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.202.00:04:19.95#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:19.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:20.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:20.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:20.07#ibcon#enter wrdev, iclass 25, count 0 2006.202.00:04:20.07#ibcon#first serial, iclass 25, count 0 2006.202.00:04:20.07#ibcon#enter sib2, iclass 25, count 0 2006.202.00:04:20.07#ibcon#flushed, iclass 25, count 0 2006.202.00:04:20.07#ibcon#about to write, iclass 25, count 0 2006.202.00:04:20.07#ibcon#wrote, iclass 25, count 0 2006.202.00:04:20.07#ibcon#about to read 3, iclass 25, count 0 2006.202.00:04:20.09#ibcon#read 3, iclass 25, count 0 2006.202.00:04:20.09#ibcon#about to read 4, iclass 25, count 0 2006.202.00:04:20.09#ibcon#read 4, iclass 25, count 0 2006.202.00:04:20.09#ibcon#about to read 5, iclass 25, count 0 2006.202.00:04:20.09#ibcon#read 5, iclass 25, count 0 2006.202.00:04:20.09#ibcon#about to read 6, iclass 25, count 0 2006.202.00:04:20.09#ibcon#read 6, iclass 25, count 0 2006.202.00:04:20.09#ibcon#end of sib2, iclass 25, count 0 2006.202.00:04:20.09#ibcon#*mode == 0, iclass 25, count 0 2006.202.00:04:20.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.00:04:20.09#ibcon#[27=USB\r\n] 2006.202.00:04:20.09#ibcon#*before write, iclass 25, count 0 2006.202.00:04:20.09#ibcon#enter sib2, iclass 25, count 0 2006.202.00:04:20.09#ibcon#flushed, iclass 25, count 0 2006.202.00:04:20.09#ibcon#about to write, iclass 25, count 0 2006.202.00:04:20.09#ibcon#wrote, iclass 25, count 0 2006.202.00:04:20.09#ibcon#about to read 3, iclass 25, count 0 2006.202.00:04:20.12#ibcon#read 3, iclass 25, count 0 2006.202.00:04:20.12#ibcon#about to read 4, iclass 25, count 0 2006.202.00:04:20.12#ibcon#read 4, iclass 25, count 0 2006.202.00:04:20.12#ibcon#about to read 5, iclass 25, count 0 2006.202.00:04:20.12#ibcon#read 5, iclass 25, count 0 2006.202.00:04:20.12#ibcon#about to read 6, iclass 25, count 0 2006.202.00:04:20.12#ibcon#read 6, iclass 25, count 0 2006.202.00:04:20.12#ibcon#end of sib2, iclass 25, count 0 2006.202.00:04:20.12#ibcon#*after write, iclass 25, count 0 2006.202.00:04:20.12#ibcon#*before return 0, iclass 25, count 0 2006.202.00:04:20.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:20.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:04:20.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.00:04:20.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.00:04:20.12$vck44/vblo=3,649.99 2006.202.00:04:20.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.202.00:04:20.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.202.00:04:20.12#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:20.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:20.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:20.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:20.12#ibcon#enter wrdev, iclass 27, count 0 2006.202.00:04:20.12#ibcon#first serial, iclass 27, count 0 2006.202.00:04:20.12#ibcon#enter sib2, iclass 27, count 0 2006.202.00:04:20.12#ibcon#flushed, iclass 27, count 0 2006.202.00:04:20.12#ibcon#about to write, iclass 27, count 0 2006.202.00:04:20.12#ibcon#wrote, iclass 27, count 0 2006.202.00:04:20.12#ibcon#about to read 3, iclass 27, count 0 2006.202.00:04:20.14#ibcon#read 3, iclass 27, count 0 2006.202.00:04:20.14#ibcon#about to read 4, iclass 27, count 0 2006.202.00:04:20.14#ibcon#read 4, iclass 27, count 0 2006.202.00:04:20.14#ibcon#about to read 5, iclass 27, count 0 2006.202.00:04:20.14#ibcon#read 5, iclass 27, count 0 2006.202.00:04:20.14#ibcon#about to read 6, iclass 27, count 0 2006.202.00:04:20.14#ibcon#read 6, iclass 27, count 0 2006.202.00:04:20.14#ibcon#end of sib2, iclass 27, count 0 2006.202.00:04:20.14#ibcon#*mode == 0, iclass 27, count 0 2006.202.00:04:20.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.00:04:20.14#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.00:04:20.14#ibcon#*before write, iclass 27, count 0 2006.202.00:04:20.14#ibcon#enter sib2, iclass 27, count 0 2006.202.00:04:20.14#ibcon#flushed, iclass 27, count 0 2006.202.00:04:20.14#ibcon#about to write, iclass 27, count 0 2006.202.00:04:20.14#ibcon#wrote, iclass 27, count 0 2006.202.00:04:20.14#ibcon#about to read 3, iclass 27, count 0 2006.202.00:04:20.18#ibcon#read 3, iclass 27, count 0 2006.202.00:04:20.18#ibcon#about to read 4, iclass 27, count 0 2006.202.00:04:20.18#ibcon#read 4, iclass 27, count 0 2006.202.00:04:20.18#ibcon#about to read 5, iclass 27, count 0 2006.202.00:04:20.18#ibcon#read 5, iclass 27, count 0 2006.202.00:04:20.18#ibcon#about to read 6, iclass 27, count 0 2006.202.00:04:20.18#ibcon#read 6, iclass 27, count 0 2006.202.00:04:20.18#ibcon#end of sib2, iclass 27, count 0 2006.202.00:04:20.18#ibcon#*after write, iclass 27, count 0 2006.202.00:04:20.18#ibcon#*before return 0, iclass 27, count 0 2006.202.00:04:20.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:20.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:04:20.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.00:04:20.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.00:04:20.18$vck44/vb=3,4 2006.202.00:04:20.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.00:04:20.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.00:04:20.18#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:20.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:20.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:20.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:20.24#ibcon#enter wrdev, iclass 29, count 2 2006.202.00:04:20.24#ibcon#first serial, iclass 29, count 2 2006.202.00:04:20.24#ibcon#enter sib2, iclass 29, count 2 2006.202.00:04:20.24#ibcon#flushed, iclass 29, count 2 2006.202.00:04:20.24#ibcon#about to write, iclass 29, count 2 2006.202.00:04:20.24#ibcon#wrote, iclass 29, count 2 2006.202.00:04:20.24#ibcon#about to read 3, iclass 29, count 2 2006.202.00:04:20.26#ibcon#read 3, iclass 29, count 2 2006.202.00:04:20.26#ibcon#about to read 4, iclass 29, count 2 2006.202.00:04:20.26#ibcon#read 4, iclass 29, count 2 2006.202.00:04:20.26#ibcon#about to read 5, iclass 29, count 2 2006.202.00:04:20.26#ibcon#read 5, iclass 29, count 2 2006.202.00:04:20.26#ibcon#about to read 6, iclass 29, count 2 2006.202.00:04:20.26#ibcon#read 6, iclass 29, count 2 2006.202.00:04:20.26#ibcon#end of sib2, iclass 29, count 2 2006.202.00:04:20.26#ibcon#*mode == 0, iclass 29, count 2 2006.202.00:04:20.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.00:04:20.26#ibcon#[27=AT03-04\r\n] 2006.202.00:04:20.26#ibcon#*before write, iclass 29, count 2 2006.202.00:04:20.26#ibcon#enter sib2, iclass 29, count 2 2006.202.00:04:20.26#ibcon#flushed, iclass 29, count 2 2006.202.00:04:20.26#ibcon#about to write, iclass 29, count 2 2006.202.00:04:20.26#ibcon#wrote, iclass 29, count 2 2006.202.00:04:20.26#ibcon#about to read 3, iclass 29, count 2 2006.202.00:04:20.29#ibcon#read 3, iclass 29, count 2 2006.202.00:04:20.29#ibcon#about to read 4, iclass 29, count 2 2006.202.00:04:20.29#ibcon#read 4, iclass 29, count 2 2006.202.00:04:20.29#ibcon#about to read 5, iclass 29, count 2 2006.202.00:04:20.29#ibcon#read 5, iclass 29, count 2 2006.202.00:04:20.29#ibcon#about to read 6, iclass 29, count 2 2006.202.00:04:20.29#ibcon#read 6, iclass 29, count 2 2006.202.00:04:20.29#ibcon#end of sib2, iclass 29, count 2 2006.202.00:04:20.29#ibcon#*after write, iclass 29, count 2 2006.202.00:04:20.29#ibcon#*before return 0, iclass 29, count 2 2006.202.00:04:20.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:20.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:04:20.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.00:04:20.29#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:20.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:20.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:20.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:20.41#ibcon#enter wrdev, iclass 29, count 0 2006.202.00:04:20.41#ibcon#first serial, iclass 29, count 0 2006.202.00:04:20.41#ibcon#enter sib2, iclass 29, count 0 2006.202.00:04:20.41#ibcon#flushed, iclass 29, count 0 2006.202.00:04:20.41#ibcon#about to write, iclass 29, count 0 2006.202.00:04:20.41#ibcon#wrote, iclass 29, count 0 2006.202.00:04:20.41#ibcon#about to read 3, iclass 29, count 0 2006.202.00:04:20.43#ibcon#read 3, iclass 29, count 0 2006.202.00:04:20.43#ibcon#about to read 4, iclass 29, count 0 2006.202.00:04:20.43#ibcon#read 4, iclass 29, count 0 2006.202.00:04:20.43#ibcon#about to read 5, iclass 29, count 0 2006.202.00:04:20.43#ibcon#read 5, iclass 29, count 0 2006.202.00:04:20.43#ibcon#about to read 6, iclass 29, count 0 2006.202.00:04:20.43#ibcon#read 6, iclass 29, count 0 2006.202.00:04:20.43#ibcon#end of sib2, iclass 29, count 0 2006.202.00:04:20.43#ibcon#*mode == 0, iclass 29, count 0 2006.202.00:04:20.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.00:04:20.43#ibcon#[27=USB\r\n] 2006.202.00:04:20.43#ibcon#*before write, iclass 29, count 0 2006.202.00:04:20.43#ibcon#enter sib2, iclass 29, count 0 2006.202.00:04:20.43#ibcon#flushed, iclass 29, count 0 2006.202.00:04:20.43#ibcon#about to write, iclass 29, count 0 2006.202.00:04:20.43#ibcon#wrote, iclass 29, count 0 2006.202.00:04:20.43#ibcon#about to read 3, iclass 29, count 0 2006.202.00:04:20.46#ibcon#read 3, iclass 29, count 0 2006.202.00:04:20.46#ibcon#about to read 4, iclass 29, count 0 2006.202.00:04:20.46#ibcon#read 4, iclass 29, count 0 2006.202.00:04:20.46#ibcon#about to read 5, iclass 29, count 0 2006.202.00:04:20.46#ibcon#read 5, iclass 29, count 0 2006.202.00:04:20.46#ibcon#about to read 6, iclass 29, count 0 2006.202.00:04:20.46#ibcon#read 6, iclass 29, count 0 2006.202.00:04:20.46#ibcon#end of sib2, iclass 29, count 0 2006.202.00:04:20.46#ibcon#*after write, iclass 29, count 0 2006.202.00:04:20.46#ibcon#*before return 0, iclass 29, count 0 2006.202.00:04:20.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:20.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:04:20.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.00:04:20.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.00:04:20.46$vck44/vblo=4,679.99 2006.202.00:04:20.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.202.00:04:20.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.202.00:04:20.46#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:20.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:04:20.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:04:20.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:04:20.46#ibcon#enter wrdev, iclass 31, count 0 2006.202.00:04:20.46#ibcon#first serial, iclass 31, count 0 2006.202.00:04:20.46#ibcon#enter sib2, iclass 31, count 0 2006.202.00:04:20.46#ibcon#flushed, iclass 31, count 0 2006.202.00:04:20.46#ibcon#about to write, iclass 31, count 0 2006.202.00:04:20.46#ibcon#wrote, iclass 31, count 0 2006.202.00:04:20.46#ibcon#about to read 3, iclass 31, count 0 2006.202.00:04:20.48#ibcon#read 3, iclass 31, count 0 2006.202.00:04:20.48#ibcon#about to read 4, iclass 31, count 0 2006.202.00:04:20.48#ibcon#read 4, iclass 31, count 0 2006.202.00:04:20.48#ibcon#about to read 5, iclass 31, count 0 2006.202.00:04:20.48#ibcon#read 5, iclass 31, count 0 2006.202.00:04:20.48#ibcon#about to read 6, iclass 31, count 0 2006.202.00:04:20.48#ibcon#read 6, iclass 31, count 0 2006.202.00:04:20.48#ibcon#end of sib2, iclass 31, count 0 2006.202.00:04:20.48#ibcon#*mode == 0, iclass 31, count 0 2006.202.00:04:20.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.00:04:20.48#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.00:04:20.48#ibcon#*before write, iclass 31, count 0 2006.202.00:04:20.48#ibcon#enter sib2, iclass 31, count 0 2006.202.00:04:20.48#ibcon#flushed, iclass 31, count 0 2006.202.00:04:20.48#ibcon#about to write, iclass 31, count 0 2006.202.00:04:20.48#ibcon#wrote, iclass 31, count 0 2006.202.00:04:20.48#ibcon#about to read 3, iclass 31, count 0 2006.202.00:04:20.52#ibcon#read 3, iclass 31, count 0 2006.202.00:04:20.52#ibcon#about to read 4, iclass 31, count 0 2006.202.00:04:20.52#ibcon#read 4, iclass 31, count 0 2006.202.00:04:20.52#ibcon#about to read 5, iclass 31, count 0 2006.202.00:04:20.52#ibcon#read 5, iclass 31, count 0 2006.202.00:04:20.52#ibcon#about to read 6, iclass 31, count 0 2006.202.00:04:20.52#ibcon#read 6, iclass 31, count 0 2006.202.00:04:20.52#ibcon#end of sib2, iclass 31, count 0 2006.202.00:04:20.52#ibcon#*after write, iclass 31, count 0 2006.202.00:04:20.52#ibcon#*before return 0, iclass 31, count 0 2006.202.00:04:20.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:04:20.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:04:20.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.00:04:20.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.00:04:20.52$vck44/vb=4,5 2006.202.00:04:20.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.202.00:04:20.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.202.00:04:20.52#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:20.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:04:20.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:04:20.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:04:20.58#ibcon#enter wrdev, iclass 33, count 2 2006.202.00:04:20.58#ibcon#first serial, iclass 33, count 2 2006.202.00:04:20.58#ibcon#enter sib2, iclass 33, count 2 2006.202.00:04:20.58#ibcon#flushed, iclass 33, count 2 2006.202.00:04:20.58#ibcon#about to write, iclass 33, count 2 2006.202.00:04:20.58#ibcon#wrote, iclass 33, count 2 2006.202.00:04:20.58#ibcon#about to read 3, iclass 33, count 2 2006.202.00:04:20.60#ibcon#read 3, iclass 33, count 2 2006.202.00:04:20.60#ibcon#about to read 4, iclass 33, count 2 2006.202.00:04:20.60#ibcon#read 4, iclass 33, count 2 2006.202.00:04:20.60#ibcon#about to read 5, iclass 33, count 2 2006.202.00:04:20.60#ibcon#read 5, iclass 33, count 2 2006.202.00:04:20.60#ibcon#about to read 6, iclass 33, count 2 2006.202.00:04:20.60#ibcon#read 6, iclass 33, count 2 2006.202.00:04:20.60#ibcon#end of sib2, iclass 33, count 2 2006.202.00:04:20.60#ibcon#*mode == 0, iclass 33, count 2 2006.202.00:04:20.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.202.00:04:20.60#ibcon#[27=AT04-05\r\n] 2006.202.00:04:20.60#ibcon#*before write, iclass 33, count 2 2006.202.00:04:20.60#ibcon#enter sib2, iclass 33, count 2 2006.202.00:04:20.60#ibcon#flushed, iclass 33, count 2 2006.202.00:04:20.60#ibcon#about to write, iclass 33, count 2 2006.202.00:04:20.60#ibcon#wrote, iclass 33, count 2 2006.202.00:04:20.60#ibcon#about to read 3, iclass 33, count 2 2006.202.00:04:20.63#ibcon#read 3, iclass 33, count 2 2006.202.00:04:20.63#ibcon#about to read 4, iclass 33, count 2 2006.202.00:04:20.63#ibcon#read 4, iclass 33, count 2 2006.202.00:04:20.63#ibcon#about to read 5, iclass 33, count 2 2006.202.00:04:20.63#ibcon#read 5, iclass 33, count 2 2006.202.00:04:20.63#ibcon#about to read 6, iclass 33, count 2 2006.202.00:04:20.63#ibcon#read 6, iclass 33, count 2 2006.202.00:04:20.63#ibcon#end of sib2, iclass 33, count 2 2006.202.00:04:20.63#ibcon#*after write, iclass 33, count 2 2006.202.00:04:20.63#ibcon#*before return 0, iclass 33, count 2 2006.202.00:04:20.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:04:20.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:04:20.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.202.00:04:20.63#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:20.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:04:20.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:04:20.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:04:20.75#ibcon#enter wrdev, iclass 33, count 0 2006.202.00:04:20.75#ibcon#first serial, iclass 33, count 0 2006.202.00:04:20.75#ibcon#enter sib2, iclass 33, count 0 2006.202.00:04:20.75#ibcon#flushed, iclass 33, count 0 2006.202.00:04:20.75#ibcon#about to write, iclass 33, count 0 2006.202.00:04:20.75#ibcon#wrote, iclass 33, count 0 2006.202.00:04:20.75#ibcon#about to read 3, iclass 33, count 0 2006.202.00:04:20.77#ibcon#read 3, iclass 33, count 0 2006.202.00:04:20.77#ibcon#about to read 4, iclass 33, count 0 2006.202.00:04:20.77#ibcon#read 4, iclass 33, count 0 2006.202.00:04:20.77#ibcon#about to read 5, iclass 33, count 0 2006.202.00:04:20.77#ibcon#read 5, iclass 33, count 0 2006.202.00:04:20.77#ibcon#about to read 6, iclass 33, count 0 2006.202.00:04:20.77#ibcon#read 6, iclass 33, count 0 2006.202.00:04:20.77#ibcon#end of sib2, iclass 33, count 0 2006.202.00:04:20.77#ibcon#*mode == 0, iclass 33, count 0 2006.202.00:04:20.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.00:04:20.77#ibcon#[27=USB\r\n] 2006.202.00:04:20.77#ibcon#*before write, iclass 33, count 0 2006.202.00:04:20.77#ibcon#enter sib2, iclass 33, count 0 2006.202.00:04:20.77#ibcon#flushed, iclass 33, count 0 2006.202.00:04:20.77#ibcon#about to write, iclass 33, count 0 2006.202.00:04:20.77#ibcon#wrote, iclass 33, count 0 2006.202.00:04:20.77#ibcon#about to read 3, iclass 33, count 0 2006.202.00:04:20.80#ibcon#read 3, iclass 33, count 0 2006.202.00:04:20.80#ibcon#about to read 4, iclass 33, count 0 2006.202.00:04:20.80#ibcon#read 4, iclass 33, count 0 2006.202.00:04:20.80#ibcon#about to read 5, iclass 33, count 0 2006.202.00:04:20.80#ibcon#read 5, iclass 33, count 0 2006.202.00:04:20.80#ibcon#about to read 6, iclass 33, count 0 2006.202.00:04:20.80#ibcon#read 6, iclass 33, count 0 2006.202.00:04:20.80#ibcon#end of sib2, iclass 33, count 0 2006.202.00:04:20.80#ibcon#*after write, iclass 33, count 0 2006.202.00:04:20.80#ibcon#*before return 0, iclass 33, count 0 2006.202.00:04:20.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:04:20.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:04:20.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.00:04:20.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.00:04:20.80$vck44/vblo=5,709.99 2006.202.00:04:20.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.202.00:04:20.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.202.00:04:20.80#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:20.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:04:20.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:04:20.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:04:20.80#ibcon#enter wrdev, iclass 35, count 0 2006.202.00:04:20.80#ibcon#first serial, iclass 35, count 0 2006.202.00:04:20.80#ibcon#enter sib2, iclass 35, count 0 2006.202.00:04:20.80#ibcon#flushed, iclass 35, count 0 2006.202.00:04:20.80#ibcon#about to write, iclass 35, count 0 2006.202.00:04:20.80#ibcon#wrote, iclass 35, count 0 2006.202.00:04:20.80#ibcon#about to read 3, iclass 35, count 0 2006.202.00:04:20.82#ibcon#read 3, iclass 35, count 0 2006.202.00:04:20.82#ibcon#about to read 4, iclass 35, count 0 2006.202.00:04:20.82#ibcon#read 4, iclass 35, count 0 2006.202.00:04:20.82#ibcon#about to read 5, iclass 35, count 0 2006.202.00:04:20.82#ibcon#read 5, iclass 35, count 0 2006.202.00:04:20.82#ibcon#about to read 6, iclass 35, count 0 2006.202.00:04:20.82#ibcon#read 6, iclass 35, count 0 2006.202.00:04:20.82#ibcon#end of sib2, iclass 35, count 0 2006.202.00:04:20.82#ibcon#*mode == 0, iclass 35, count 0 2006.202.00:04:20.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.00:04:20.82#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.00:04:20.82#ibcon#*before write, iclass 35, count 0 2006.202.00:04:20.82#ibcon#enter sib2, iclass 35, count 0 2006.202.00:04:20.82#ibcon#flushed, iclass 35, count 0 2006.202.00:04:20.82#ibcon#about to write, iclass 35, count 0 2006.202.00:04:20.82#ibcon#wrote, iclass 35, count 0 2006.202.00:04:20.82#ibcon#about to read 3, iclass 35, count 0 2006.202.00:04:20.86#ibcon#read 3, iclass 35, count 0 2006.202.00:04:20.86#ibcon#about to read 4, iclass 35, count 0 2006.202.00:04:20.86#ibcon#read 4, iclass 35, count 0 2006.202.00:04:20.86#ibcon#about to read 5, iclass 35, count 0 2006.202.00:04:20.86#ibcon#read 5, iclass 35, count 0 2006.202.00:04:20.86#ibcon#about to read 6, iclass 35, count 0 2006.202.00:04:20.86#ibcon#read 6, iclass 35, count 0 2006.202.00:04:20.86#ibcon#end of sib2, iclass 35, count 0 2006.202.00:04:20.86#ibcon#*after write, iclass 35, count 0 2006.202.00:04:20.86#ibcon#*before return 0, iclass 35, count 0 2006.202.00:04:20.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:04:20.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:04:20.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.00:04:20.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.00:04:20.86$vck44/vb=5,4 2006.202.00:04:20.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.202.00:04:20.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.202.00:04:20.86#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:20.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:04:20.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:04:20.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:04:20.92#ibcon#enter wrdev, iclass 37, count 2 2006.202.00:04:20.92#ibcon#first serial, iclass 37, count 2 2006.202.00:04:20.92#ibcon#enter sib2, iclass 37, count 2 2006.202.00:04:20.92#ibcon#flushed, iclass 37, count 2 2006.202.00:04:20.92#ibcon#about to write, iclass 37, count 2 2006.202.00:04:20.92#ibcon#wrote, iclass 37, count 2 2006.202.00:04:20.92#ibcon#about to read 3, iclass 37, count 2 2006.202.00:04:20.94#ibcon#read 3, iclass 37, count 2 2006.202.00:04:20.94#ibcon#about to read 4, iclass 37, count 2 2006.202.00:04:20.94#ibcon#read 4, iclass 37, count 2 2006.202.00:04:20.94#ibcon#about to read 5, iclass 37, count 2 2006.202.00:04:20.94#ibcon#read 5, iclass 37, count 2 2006.202.00:04:20.94#ibcon#about to read 6, iclass 37, count 2 2006.202.00:04:20.94#ibcon#read 6, iclass 37, count 2 2006.202.00:04:20.94#ibcon#end of sib2, iclass 37, count 2 2006.202.00:04:20.94#ibcon#*mode == 0, iclass 37, count 2 2006.202.00:04:20.94#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.202.00:04:20.94#ibcon#[27=AT05-04\r\n] 2006.202.00:04:20.94#ibcon#*before write, iclass 37, count 2 2006.202.00:04:20.94#ibcon#enter sib2, iclass 37, count 2 2006.202.00:04:20.94#ibcon#flushed, iclass 37, count 2 2006.202.00:04:20.94#ibcon#about to write, iclass 37, count 2 2006.202.00:04:20.94#ibcon#wrote, iclass 37, count 2 2006.202.00:04:20.94#ibcon#about to read 3, iclass 37, count 2 2006.202.00:04:20.97#ibcon#read 3, iclass 37, count 2 2006.202.00:04:20.97#ibcon#about to read 4, iclass 37, count 2 2006.202.00:04:20.97#ibcon#read 4, iclass 37, count 2 2006.202.00:04:20.97#ibcon#about to read 5, iclass 37, count 2 2006.202.00:04:20.97#ibcon#read 5, iclass 37, count 2 2006.202.00:04:20.97#ibcon#about to read 6, iclass 37, count 2 2006.202.00:04:20.97#ibcon#read 6, iclass 37, count 2 2006.202.00:04:20.97#ibcon#end of sib2, iclass 37, count 2 2006.202.00:04:20.97#ibcon#*after write, iclass 37, count 2 2006.202.00:04:21.03#ibcon#*before return 0, iclass 37, count 2 2006.202.00:04:21.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:04:21.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:04:21.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.202.00:04:21.03#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:21.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:04:21.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:04:21.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:04:21.16#ibcon#enter wrdev, iclass 37, count 0 2006.202.00:04:21.16#ibcon#first serial, iclass 37, count 0 2006.202.00:04:21.16#ibcon#enter sib2, iclass 37, count 0 2006.202.00:04:21.16#ibcon#flushed, iclass 37, count 0 2006.202.00:04:21.16#ibcon#about to write, iclass 37, count 0 2006.202.00:04:21.16#ibcon#wrote, iclass 37, count 0 2006.202.00:04:21.16#ibcon#about to read 3, iclass 37, count 0 2006.202.00:04:21.18#ibcon#read 3, iclass 37, count 0 2006.202.00:04:21.18#ibcon#about to read 4, iclass 37, count 0 2006.202.00:04:21.18#ibcon#read 4, iclass 37, count 0 2006.202.00:04:21.18#ibcon#about to read 5, iclass 37, count 0 2006.202.00:04:21.18#ibcon#read 5, iclass 37, count 0 2006.202.00:04:21.18#ibcon#about to read 6, iclass 37, count 0 2006.202.00:04:21.18#ibcon#read 6, iclass 37, count 0 2006.202.00:04:21.18#ibcon#end of sib2, iclass 37, count 0 2006.202.00:04:21.18#ibcon#*mode == 0, iclass 37, count 0 2006.202.00:04:21.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.00:04:21.18#ibcon#[27=USB\r\n] 2006.202.00:04:21.18#ibcon#*before write, iclass 37, count 0 2006.202.00:04:21.18#ibcon#enter sib2, iclass 37, count 0 2006.202.00:04:21.18#ibcon#flushed, iclass 37, count 0 2006.202.00:04:21.18#ibcon#about to write, iclass 37, count 0 2006.202.00:04:21.18#ibcon#wrote, iclass 37, count 0 2006.202.00:04:21.18#ibcon#about to read 3, iclass 37, count 0 2006.202.00:04:21.21#ibcon#read 3, iclass 37, count 0 2006.202.00:04:21.21#ibcon#about to read 4, iclass 37, count 0 2006.202.00:04:21.21#ibcon#read 4, iclass 37, count 0 2006.202.00:04:21.21#ibcon#about to read 5, iclass 37, count 0 2006.202.00:04:21.21#ibcon#read 5, iclass 37, count 0 2006.202.00:04:21.21#ibcon#about to read 6, iclass 37, count 0 2006.202.00:04:21.21#ibcon#read 6, iclass 37, count 0 2006.202.00:04:21.21#ibcon#end of sib2, iclass 37, count 0 2006.202.00:04:21.21#ibcon#*after write, iclass 37, count 0 2006.202.00:04:21.21#ibcon#*before return 0, iclass 37, count 0 2006.202.00:04:21.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:04:21.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:04:21.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.00:04:21.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.00:04:21.21$vck44/vblo=6,719.99 2006.202.00:04:21.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.202.00:04:21.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.202.00:04:21.21#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:21.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:21.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:21.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:21.21#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:04:21.21#ibcon#first serial, iclass 39, count 0 2006.202.00:04:21.21#ibcon#enter sib2, iclass 39, count 0 2006.202.00:04:21.21#ibcon#flushed, iclass 39, count 0 2006.202.00:04:21.21#ibcon#about to write, iclass 39, count 0 2006.202.00:04:21.21#ibcon#wrote, iclass 39, count 0 2006.202.00:04:21.21#ibcon#about to read 3, iclass 39, count 0 2006.202.00:04:21.23#ibcon#read 3, iclass 39, count 0 2006.202.00:04:21.23#ibcon#about to read 4, iclass 39, count 0 2006.202.00:04:21.23#ibcon#read 4, iclass 39, count 0 2006.202.00:04:21.23#ibcon#about to read 5, iclass 39, count 0 2006.202.00:04:21.23#ibcon#read 5, iclass 39, count 0 2006.202.00:04:21.23#ibcon#about to read 6, iclass 39, count 0 2006.202.00:04:21.23#ibcon#read 6, iclass 39, count 0 2006.202.00:04:21.23#ibcon#end of sib2, iclass 39, count 0 2006.202.00:04:21.23#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:04:21.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:04:21.23#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.00:04:21.23#ibcon#*before write, iclass 39, count 0 2006.202.00:04:21.23#ibcon#enter sib2, iclass 39, count 0 2006.202.00:04:21.23#ibcon#flushed, iclass 39, count 0 2006.202.00:04:21.23#ibcon#about to write, iclass 39, count 0 2006.202.00:04:21.23#ibcon#wrote, iclass 39, count 0 2006.202.00:04:21.23#ibcon#about to read 3, iclass 39, count 0 2006.202.00:04:21.27#ibcon#read 3, iclass 39, count 0 2006.202.00:04:21.27#ibcon#about to read 4, iclass 39, count 0 2006.202.00:04:21.27#ibcon#read 4, iclass 39, count 0 2006.202.00:04:21.27#ibcon#about to read 5, iclass 39, count 0 2006.202.00:04:21.27#ibcon#read 5, iclass 39, count 0 2006.202.00:04:21.27#ibcon#about to read 6, iclass 39, count 0 2006.202.00:04:21.27#ibcon#read 6, iclass 39, count 0 2006.202.00:04:21.27#ibcon#end of sib2, iclass 39, count 0 2006.202.00:04:21.27#ibcon#*after write, iclass 39, count 0 2006.202.00:04:21.27#ibcon#*before return 0, iclass 39, count 0 2006.202.00:04:21.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:21.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:04:21.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:04:21.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:04:21.27$vck44/vb=6,4 2006.202.00:04:21.27#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.202.00:04:21.27#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.202.00:04:21.27#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:21.27#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:21.33#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:21.33#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:21.33#ibcon#enter wrdev, iclass 2, count 2 2006.202.00:04:21.33#ibcon#first serial, iclass 2, count 2 2006.202.00:04:21.33#ibcon#enter sib2, iclass 2, count 2 2006.202.00:04:21.33#ibcon#flushed, iclass 2, count 2 2006.202.00:04:21.33#ibcon#about to write, iclass 2, count 2 2006.202.00:04:21.33#ibcon#wrote, iclass 2, count 2 2006.202.00:04:21.33#ibcon#about to read 3, iclass 2, count 2 2006.202.00:04:21.35#ibcon#read 3, iclass 2, count 2 2006.202.00:04:21.35#ibcon#about to read 4, iclass 2, count 2 2006.202.00:04:21.35#ibcon#read 4, iclass 2, count 2 2006.202.00:04:21.35#ibcon#about to read 5, iclass 2, count 2 2006.202.00:04:21.35#ibcon#read 5, iclass 2, count 2 2006.202.00:04:21.35#ibcon#about to read 6, iclass 2, count 2 2006.202.00:04:21.35#ibcon#read 6, iclass 2, count 2 2006.202.00:04:21.35#ibcon#end of sib2, iclass 2, count 2 2006.202.00:04:21.35#ibcon#*mode == 0, iclass 2, count 2 2006.202.00:04:21.35#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.202.00:04:21.35#ibcon#[27=AT06-04\r\n] 2006.202.00:04:21.35#ibcon#*before write, iclass 2, count 2 2006.202.00:04:21.35#ibcon#enter sib2, iclass 2, count 2 2006.202.00:04:21.35#ibcon#flushed, iclass 2, count 2 2006.202.00:04:21.35#ibcon#about to write, iclass 2, count 2 2006.202.00:04:21.35#ibcon#wrote, iclass 2, count 2 2006.202.00:04:21.35#ibcon#about to read 3, iclass 2, count 2 2006.202.00:04:21.38#ibcon#read 3, iclass 2, count 2 2006.202.00:04:21.38#ibcon#about to read 4, iclass 2, count 2 2006.202.00:04:21.38#ibcon#read 4, iclass 2, count 2 2006.202.00:04:21.38#ibcon#about to read 5, iclass 2, count 2 2006.202.00:04:21.38#ibcon#read 5, iclass 2, count 2 2006.202.00:04:21.38#ibcon#about to read 6, iclass 2, count 2 2006.202.00:04:21.38#ibcon#read 6, iclass 2, count 2 2006.202.00:04:21.38#ibcon#end of sib2, iclass 2, count 2 2006.202.00:04:21.38#ibcon#*after write, iclass 2, count 2 2006.202.00:04:21.38#ibcon#*before return 0, iclass 2, count 2 2006.202.00:04:21.38#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:21.38#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:04:21.38#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.202.00:04:21.38#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:21.38#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:21.50#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:21.50#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:21.50#ibcon#enter wrdev, iclass 2, count 0 2006.202.00:04:21.50#ibcon#first serial, iclass 2, count 0 2006.202.00:04:21.50#ibcon#enter sib2, iclass 2, count 0 2006.202.00:04:21.50#ibcon#flushed, iclass 2, count 0 2006.202.00:04:21.50#ibcon#about to write, iclass 2, count 0 2006.202.00:04:21.50#ibcon#wrote, iclass 2, count 0 2006.202.00:04:21.50#ibcon#about to read 3, iclass 2, count 0 2006.202.00:04:21.52#ibcon#read 3, iclass 2, count 0 2006.202.00:04:21.52#ibcon#about to read 4, iclass 2, count 0 2006.202.00:04:21.52#ibcon#read 4, iclass 2, count 0 2006.202.00:04:21.52#ibcon#about to read 5, iclass 2, count 0 2006.202.00:04:21.52#ibcon#read 5, iclass 2, count 0 2006.202.00:04:21.52#ibcon#about to read 6, iclass 2, count 0 2006.202.00:04:21.52#ibcon#read 6, iclass 2, count 0 2006.202.00:04:21.52#ibcon#end of sib2, iclass 2, count 0 2006.202.00:04:21.52#ibcon#*mode == 0, iclass 2, count 0 2006.202.00:04:21.52#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.00:04:21.52#ibcon#[27=USB\r\n] 2006.202.00:04:21.52#ibcon#*before write, iclass 2, count 0 2006.202.00:04:21.52#ibcon#enter sib2, iclass 2, count 0 2006.202.00:04:21.52#ibcon#flushed, iclass 2, count 0 2006.202.00:04:21.52#ibcon#about to write, iclass 2, count 0 2006.202.00:04:21.52#ibcon#wrote, iclass 2, count 0 2006.202.00:04:21.52#ibcon#about to read 3, iclass 2, count 0 2006.202.00:04:21.55#ibcon#read 3, iclass 2, count 0 2006.202.00:04:21.55#ibcon#about to read 4, iclass 2, count 0 2006.202.00:04:21.55#ibcon#read 4, iclass 2, count 0 2006.202.00:04:21.55#ibcon#about to read 5, iclass 2, count 0 2006.202.00:04:21.55#ibcon#read 5, iclass 2, count 0 2006.202.00:04:21.55#ibcon#about to read 6, iclass 2, count 0 2006.202.00:04:21.55#ibcon#read 6, iclass 2, count 0 2006.202.00:04:21.55#ibcon#end of sib2, iclass 2, count 0 2006.202.00:04:21.55#ibcon#*after write, iclass 2, count 0 2006.202.00:04:21.55#ibcon#*before return 0, iclass 2, count 0 2006.202.00:04:21.55#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:21.55#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:04:21.55#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.00:04:21.55#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.00:04:21.55$vck44/vblo=7,734.99 2006.202.00:04:21.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.202.00:04:21.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.202.00:04:21.55#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:21.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:21.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:21.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:21.55#ibcon#enter wrdev, iclass 5, count 0 2006.202.00:04:21.55#ibcon#first serial, iclass 5, count 0 2006.202.00:04:21.55#ibcon#enter sib2, iclass 5, count 0 2006.202.00:04:21.55#ibcon#flushed, iclass 5, count 0 2006.202.00:04:21.55#ibcon#about to write, iclass 5, count 0 2006.202.00:04:21.55#ibcon#wrote, iclass 5, count 0 2006.202.00:04:21.55#ibcon#about to read 3, iclass 5, count 0 2006.202.00:04:21.57#ibcon#read 3, iclass 5, count 0 2006.202.00:04:21.57#ibcon#about to read 4, iclass 5, count 0 2006.202.00:04:21.57#ibcon#read 4, iclass 5, count 0 2006.202.00:04:21.57#ibcon#about to read 5, iclass 5, count 0 2006.202.00:04:21.57#ibcon#read 5, iclass 5, count 0 2006.202.00:04:21.57#ibcon#about to read 6, iclass 5, count 0 2006.202.00:04:21.57#ibcon#read 6, iclass 5, count 0 2006.202.00:04:21.57#ibcon#end of sib2, iclass 5, count 0 2006.202.00:04:21.57#ibcon#*mode == 0, iclass 5, count 0 2006.202.00:04:21.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.00:04:21.57#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.00:04:21.57#ibcon#*before write, iclass 5, count 0 2006.202.00:04:21.57#ibcon#enter sib2, iclass 5, count 0 2006.202.00:04:21.57#ibcon#flushed, iclass 5, count 0 2006.202.00:04:21.57#ibcon#about to write, iclass 5, count 0 2006.202.00:04:21.57#ibcon#wrote, iclass 5, count 0 2006.202.00:04:21.57#ibcon#about to read 3, iclass 5, count 0 2006.202.00:04:21.61#ibcon#read 3, iclass 5, count 0 2006.202.00:04:21.61#ibcon#about to read 4, iclass 5, count 0 2006.202.00:04:21.61#ibcon#read 4, iclass 5, count 0 2006.202.00:04:21.61#ibcon#about to read 5, iclass 5, count 0 2006.202.00:04:21.61#ibcon#read 5, iclass 5, count 0 2006.202.00:04:21.61#ibcon#about to read 6, iclass 5, count 0 2006.202.00:04:21.61#ibcon#read 6, iclass 5, count 0 2006.202.00:04:21.61#ibcon#end of sib2, iclass 5, count 0 2006.202.00:04:21.61#ibcon#*after write, iclass 5, count 0 2006.202.00:04:21.61#ibcon#*before return 0, iclass 5, count 0 2006.202.00:04:21.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:21.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:04:21.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.00:04:21.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.00:04:21.61$vck44/vb=7,4 2006.202.00:04:21.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.202.00:04:21.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.202.00:04:21.61#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:21.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:21.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:21.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:21.67#ibcon#enter wrdev, iclass 7, count 2 2006.202.00:04:21.67#ibcon#first serial, iclass 7, count 2 2006.202.00:04:21.67#ibcon#enter sib2, iclass 7, count 2 2006.202.00:04:21.67#ibcon#flushed, iclass 7, count 2 2006.202.00:04:21.67#ibcon#about to write, iclass 7, count 2 2006.202.00:04:21.67#ibcon#wrote, iclass 7, count 2 2006.202.00:04:21.67#ibcon#about to read 3, iclass 7, count 2 2006.202.00:04:21.69#ibcon#read 3, iclass 7, count 2 2006.202.00:04:21.69#ibcon#about to read 4, iclass 7, count 2 2006.202.00:04:21.69#ibcon#read 4, iclass 7, count 2 2006.202.00:04:21.69#ibcon#about to read 5, iclass 7, count 2 2006.202.00:04:21.69#ibcon#read 5, iclass 7, count 2 2006.202.00:04:21.69#ibcon#about to read 6, iclass 7, count 2 2006.202.00:04:21.69#ibcon#read 6, iclass 7, count 2 2006.202.00:04:21.69#ibcon#end of sib2, iclass 7, count 2 2006.202.00:04:21.69#ibcon#*mode == 0, iclass 7, count 2 2006.202.00:04:21.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.202.00:04:21.69#ibcon#[27=AT07-04\r\n] 2006.202.00:04:21.69#ibcon#*before write, iclass 7, count 2 2006.202.00:04:21.69#ibcon#enter sib2, iclass 7, count 2 2006.202.00:04:21.69#ibcon#flushed, iclass 7, count 2 2006.202.00:04:21.69#ibcon#about to write, iclass 7, count 2 2006.202.00:04:21.69#ibcon#wrote, iclass 7, count 2 2006.202.00:04:21.69#ibcon#about to read 3, iclass 7, count 2 2006.202.00:04:21.72#ibcon#read 3, iclass 7, count 2 2006.202.00:04:21.72#ibcon#about to read 4, iclass 7, count 2 2006.202.00:04:21.72#ibcon#read 4, iclass 7, count 2 2006.202.00:04:21.72#ibcon#about to read 5, iclass 7, count 2 2006.202.00:04:21.72#ibcon#read 5, iclass 7, count 2 2006.202.00:04:21.72#ibcon#about to read 6, iclass 7, count 2 2006.202.00:04:21.72#ibcon#read 6, iclass 7, count 2 2006.202.00:04:21.72#ibcon#end of sib2, iclass 7, count 2 2006.202.00:04:21.72#ibcon#*after write, iclass 7, count 2 2006.202.00:04:21.72#ibcon#*before return 0, iclass 7, count 2 2006.202.00:04:21.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:21.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:04:21.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.202.00:04:21.72#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:21.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:21.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:21.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:21.84#ibcon#enter wrdev, iclass 7, count 0 2006.202.00:04:21.84#ibcon#first serial, iclass 7, count 0 2006.202.00:04:21.84#ibcon#enter sib2, iclass 7, count 0 2006.202.00:04:21.84#ibcon#flushed, iclass 7, count 0 2006.202.00:04:21.84#ibcon#about to write, iclass 7, count 0 2006.202.00:04:21.84#ibcon#wrote, iclass 7, count 0 2006.202.00:04:21.84#ibcon#about to read 3, iclass 7, count 0 2006.202.00:04:21.86#ibcon#read 3, iclass 7, count 0 2006.202.00:04:21.86#ibcon#about to read 4, iclass 7, count 0 2006.202.00:04:21.86#ibcon#read 4, iclass 7, count 0 2006.202.00:04:21.86#ibcon#about to read 5, iclass 7, count 0 2006.202.00:04:21.86#ibcon#read 5, iclass 7, count 0 2006.202.00:04:21.86#ibcon#about to read 6, iclass 7, count 0 2006.202.00:04:21.86#ibcon#read 6, iclass 7, count 0 2006.202.00:04:21.86#ibcon#end of sib2, iclass 7, count 0 2006.202.00:04:21.86#ibcon#*mode == 0, iclass 7, count 0 2006.202.00:04:21.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.00:04:21.86#ibcon#[27=USB\r\n] 2006.202.00:04:21.86#ibcon#*before write, iclass 7, count 0 2006.202.00:04:21.86#ibcon#enter sib2, iclass 7, count 0 2006.202.00:04:21.86#ibcon#flushed, iclass 7, count 0 2006.202.00:04:21.86#ibcon#about to write, iclass 7, count 0 2006.202.00:04:21.86#ibcon#wrote, iclass 7, count 0 2006.202.00:04:21.86#ibcon#about to read 3, iclass 7, count 0 2006.202.00:04:21.89#ibcon#read 3, iclass 7, count 0 2006.202.00:04:21.89#ibcon#about to read 4, iclass 7, count 0 2006.202.00:04:21.89#ibcon#read 4, iclass 7, count 0 2006.202.00:04:21.89#ibcon#about to read 5, iclass 7, count 0 2006.202.00:04:21.89#ibcon#read 5, iclass 7, count 0 2006.202.00:04:21.89#ibcon#about to read 6, iclass 7, count 0 2006.202.00:04:21.89#ibcon#read 6, iclass 7, count 0 2006.202.00:04:21.89#ibcon#end of sib2, iclass 7, count 0 2006.202.00:04:21.89#ibcon#*after write, iclass 7, count 0 2006.202.00:04:21.89#ibcon#*before return 0, iclass 7, count 0 2006.202.00:04:21.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:21.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:04:21.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.00:04:21.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.00:04:21.89$vck44/vblo=8,744.99 2006.202.00:04:21.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.202.00:04:21.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.202.00:04:21.89#ibcon#ireg 17 cls_cnt 0 2006.202.00:04:21.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:21.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:21.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:21.89#ibcon#enter wrdev, iclass 11, count 0 2006.202.00:04:21.89#ibcon#first serial, iclass 11, count 0 2006.202.00:04:21.89#ibcon#enter sib2, iclass 11, count 0 2006.202.00:04:21.89#ibcon#flushed, iclass 11, count 0 2006.202.00:04:21.89#ibcon#about to write, iclass 11, count 0 2006.202.00:04:21.89#ibcon#wrote, iclass 11, count 0 2006.202.00:04:21.89#ibcon#about to read 3, iclass 11, count 0 2006.202.00:04:21.91#ibcon#read 3, iclass 11, count 0 2006.202.00:04:21.91#ibcon#about to read 4, iclass 11, count 0 2006.202.00:04:21.91#ibcon#read 4, iclass 11, count 0 2006.202.00:04:21.91#ibcon#about to read 5, iclass 11, count 0 2006.202.00:04:21.91#ibcon#read 5, iclass 11, count 0 2006.202.00:04:21.91#ibcon#about to read 6, iclass 11, count 0 2006.202.00:04:21.91#ibcon#read 6, iclass 11, count 0 2006.202.00:04:21.91#ibcon#end of sib2, iclass 11, count 0 2006.202.00:04:21.91#ibcon#*mode == 0, iclass 11, count 0 2006.202.00:04:21.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.00:04:21.91#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.00:04:21.91#ibcon#*before write, iclass 11, count 0 2006.202.00:04:21.91#ibcon#enter sib2, iclass 11, count 0 2006.202.00:04:21.91#ibcon#flushed, iclass 11, count 0 2006.202.00:04:21.91#ibcon#about to write, iclass 11, count 0 2006.202.00:04:21.91#ibcon#wrote, iclass 11, count 0 2006.202.00:04:21.91#ibcon#about to read 3, iclass 11, count 0 2006.202.00:04:21.95#ibcon#read 3, iclass 11, count 0 2006.202.00:04:21.95#ibcon#about to read 4, iclass 11, count 0 2006.202.00:04:21.95#ibcon#read 4, iclass 11, count 0 2006.202.00:04:21.95#ibcon#about to read 5, iclass 11, count 0 2006.202.00:04:21.95#ibcon#read 5, iclass 11, count 0 2006.202.00:04:21.95#ibcon#about to read 6, iclass 11, count 0 2006.202.00:04:21.95#ibcon#read 6, iclass 11, count 0 2006.202.00:04:21.95#ibcon#end of sib2, iclass 11, count 0 2006.202.00:04:21.95#ibcon#*after write, iclass 11, count 0 2006.202.00:04:21.95#ibcon#*before return 0, iclass 11, count 0 2006.202.00:04:21.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:21.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:04:21.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.00:04:21.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.00:04:21.95$vck44/vb=8,4 2006.202.00:04:21.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.202.00:04:21.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.202.00:04:21.95#ibcon#ireg 11 cls_cnt 2 2006.202.00:04:21.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:22.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:22.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:22.01#ibcon#enter wrdev, iclass 13, count 2 2006.202.00:04:22.01#ibcon#first serial, iclass 13, count 2 2006.202.00:04:22.01#ibcon#enter sib2, iclass 13, count 2 2006.202.00:04:22.01#ibcon#flushed, iclass 13, count 2 2006.202.00:04:22.01#ibcon#about to write, iclass 13, count 2 2006.202.00:04:22.01#ibcon#wrote, iclass 13, count 2 2006.202.00:04:22.01#ibcon#about to read 3, iclass 13, count 2 2006.202.00:04:22.03#ibcon#read 3, iclass 13, count 2 2006.202.00:04:22.03#ibcon#about to read 4, iclass 13, count 2 2006.202.00:04:22.03#ibcon#read 4, iclass 13, count 2 2006.202.00:04:22.03#ibcon#about to read 5, iclass 13, count 2 2006.202.00:04:22.03#ibcon#read 5, iclass 13, count 2 2006.202.00:04:22.03#ibcon#about to read 6, iclass 13, count 2 2006.202.00:04:22.03#ibcon#read 6, iclass 13, count 2 2006.202.00:04:22.03#ibcon#end of sib2, iclass 13, count 2 2006.202.00:04:22.03#ibcon#*mode == 0, iclass 13, count 2 2006.202.00:04:22.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.202.00:04:22.03#ibcon#[27=AT08-04\r\n] 2006.202.00:04:22.03#ibcon#*before write, iclass 13, count 2 2006.202.00:04:22.03#ibcon#enter sib2, iclass 13, count 2 2006.202.00:04:22.03#ibcon#flushed, iclass 13, count 2 2006.202.00:04:22.03#ibcon#about to write, iclass 13, count 2 2006.202.00:04:22.03#ibcon#wrote, iclass 13, count 2 2006.202.00:04:22.03#ibcon#about to read 3, iclass 13, count 2 2006.202.00:04:22.06#ibcon#read 3, iclass 13, count 2 2006.202.00:04:22.13#ibcon#about to read 4, iclass 13, count 2 2006.202.00:04:22.13#ibcon#read 4, iclass 13, count 2 2006.202.00:04:22.13#ibcon#about to read 5, iclass 13, count 2 2006.202.00:04:22.14#ibcon#read 5, iclass 13, count 2 2006.202.00:04:22.14#ibcon#about to read 6, iclass 13, count 2 2006.202.00:04:22.14#ibcon#read 6, iclass 13, count 2 2006.202.00:04:22.14#ibcon#end of sib2, iclass 13, count 2 2006.202.00:04:22.14#ibcon#*after write, iclass 13, count 2 2006.202.00:04:22.14#ibcon#*before return 0, iclass 13, count 2 2006.202.00:04:22.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:22.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:04:22.14#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.202.00:04:22.14#ibcon#ireg 7 cls_cnt 0 2006.202.00:04:22.14#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:22.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:22.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:22.26#ibcon#enter wrdev, iclass 13, count 0 2006.202.00:04:22.26#ibcon#first serial, iclass 13, count 0 2006.202.00:04:22.26#ibcon#enter sib2, iclass 13, count 0 2006.202.00:04:22.26#ibcon#flushed, iclass 13, count 0 2006.202.00:04:22.26#ibcon#about to write, iclass 13, count 0 2006.202.00:04:22.26#ibcon#wrote, iclass 13, count 0 2006.202.00:04:22.26#ibcon#about to read 3, iclass 13, count 0 2006.202.00:04:22.28#ibcon#read 3, iclass 13, count 0 2006.202.00:04:22.28#ibcon#about to read 4, iclass 13, count 0 2006.202.00:04:22.28#ibcon#read 4, iclass 13, count 0 2006.202.00:04:22.28#ibcon#about to read 5, iclass 13, count 0 2006.202.00:04:22.28#ibcon#read 5, iclass 13, count 0 2006.202.00:04:22.28#ibcon#about to read 6, iclass 13, count 0 2006.202.00:04:22.28#ibcon#read 6, iclass 13, count 0 2006.202.00:04:22.28#ibcon#end of sib2, iclass 13, count 0 2006.202.00:04:22.28#ibcon#*mode == 0, iclass 13, count 0 2006.202.00:04:22.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.00:04:22.28#ibcon#[27=USB\r\n] 2006.202.00:04:22.28#ibcon#*before write, iclass 13, count 0 2006.202.00:04:22.28#ibcon#enter sib2, iclass 13, count 0 2006.202.00:04:22.28#ibcon#flushed, iclass 13, count 0 2006.202.00:04:22.28#ibcon#about to write, iclass 13, count 0 2006.202.00:04:22.28#ibcon#wrote, iclass 13, count 0 2006.202.00:04:22.28#ibcon#about to read 3, iclass 13, count 0 2006.202.00:04:22.31#ibcon#read 3, iclass 13, count 0 2006.202.00:04:22.31#ibcon#about to read 4, iclass 13, count 0 2006.202.00:04:22.31#ibcon#read 4, iclass 13, count 0 2006.202.00:04:22.31#ibcon#about to read 5, iclass 13, count 0 2006.202.00:04:22.31#ibcon#read 5, iclass 13, count 0 2006.202.00:04:22.31#ibcon#about to read 6, iclass 13, count 0 2006.202.00:04:22.31#ibcon#read 6, iclass 13, count 0 2006.202.00:04:22.31#ibcon#end of sib2, iclass 13, count 0 2006.202.00:04:22.31#ibcon#*after write, iclass 13, count 0 2006.202.00:04:22.31#ibcon#*before return 0, iclass 13, count 0 2006.202.00:04:22.31#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:22.31#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:04:22.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.00:04:22.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.00:04:22.31$vck44/vabw=wide 2006.202.00:04:22.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.00:04:22.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.00:04:22.31#ibcon#ireg 8 cls_cnt 0 2006.202.00:04:22.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:22.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:22.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:22.31#ibcon#enter wrdev, iclass 15, count 0 2006.202.00:04:22.31#ibcon#first serial, iclass 15, count 0 2006.202.00:04:22.31#ibcon#enter sib2, iclass 15, count 0 2006.202.00:04:22.31#ibcon#flushed, iclass 15, count 0 2006.202.00:04:22.31#ibcon#about to write, iclass 15, count 0 2006.202.00:04:22.31#ibcon#wrote, iclass 15, count 0 2006.202.00:04:22.31#ibcon#about to read 3, iclass 15, count 0 2006.202.00:04:22.33#ibcon#read 3, iclass 15, count 0 2006.202.00:04:22.33#ibcon#about to read 4, iclass 15, count 0 2006.202.00:04:22.33#ibcon#read 4, iclass 15, count 0 2006.202.00:04:22.33#ibcon#about to read 5, iclass 15, count 0 2006.202.00:04:22.33#ibcon#read 5, iclass 15, count 0 2006.202.00:04:22.33#ibcon#about to read 6, iclass 15, count 0 2006.202.00:04:22.33#ibcon#read 6, iclass 15, count 0 2006.202.00:04:22.33#ibcon#end of sib2, iclass 15, count 0 2006.202.00:04:22.33#ibcon#*mode == 0, iclass 15, count 0 2006.202.00:04:22.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.00:04:22.33#ibcon#[25=BW32\r\n] 2006.202.00:04:22.33#ibcon#*before write, iclass 15, count 0 2006.202.00:04:22.33#ibcon#enter sib2, iclass 15, count 0 2006.202.00:04:22.33#ibcon#flushed, iclass 15, count 0 2006.202.00:04:22.33#ibcon#about to write, iclass 15, count 0 2006.202.00:04:22.33#ibcon#wrote, iclass 15, count 0 2006.202.00:04:22.33#ibcon#about to read 3, iclass 15, count 0 2006.202.00:04:22.36#ibcon#read 3, iclass 15, count 0 2006.202.00:04:22.36#ibcon#about to read 4, iclass 15, count 0 2006.202.00:04:22.36#ibcon#read 4, iclass 15, count 0 2006.202.00:04:22.36#ibcon#about to read 5, iclass 15, count 0 2006.202.00:04:22.36#ibcon#read 5, iclass 15, count 0 2006.202.00:04:22.36#ibcon#about to read 6, iclass 15, count 0 2006.202.00:04:22.36#ibcon#read 6, iclass 15, count 0 2006.202.00:04:22.36#ibcon#end of sib2, iclass 15, count 0 2006.202.00:04:22.36#ibcon#*after write, iclass 15, count 0 2006.202.00:04:22.36#ibcon#*before return 0, iclass 15, count 0 2006.202.00:04:22.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:22.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:04:22.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.00:04:22.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.00:04:22.36$vck44/vbbw=wide 2006.202.00:04:22.36#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.00:04:22.36#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.00:04:22.36#ibcon#ireg 8 cls_cnt 0 2006.202.00:04:22.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:04:22.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:04:22.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:04:22.43#ibcon#enter wrdev, iclass 17, count 0 2006.202.00:04:22.43#ibcon#first serial, iclass 17, count 0 2006.202.00:04:22.43#ibcon#enter sib2, iclass 17, count 0 2006.202.00:04:22.43#ibcon#flushed, iclass 17, count 0 2006.202.00:04:22.43#ibcon#about to write, iclass 17, count 0 2006.202.00:04:22.43#ibcon#wrote, iclass 17, count 0 2006.202.00:04:22.43#ibcon#about to read 3, iclass 17, count 0 2006.202.00:04:22.45#ibcon#read 3, iclass 17, count 0 2006.202.00:04:22.45#ibcon#about to read 4, iclass 17, count 0 2006.202.00:04:22.45#ibcon#read 4, iclass 17, count 0 2006.202.00:04:22.45#ibcon#about to read 5, iclass 17, count 0 2006.202.00:04:22.45#ibcon#read 5, iclass 17, count 0 2006.202.00:04:22.45#ibcon#about to read 6, iclass 17, count 0 2006.202.00:04:22.45#ibcon#read 6, iclass 17, count 0 2006.202.00:04:22.45#ibcon#end of sib2, iclass 17, count 0 2006.202.00:04:22.45#ibcon#*mode == 0, iclass 17, count 0 2006.202.00:04:22.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.00:04:22.45#ibcon#[27=BW32\r\n] 2006.202.00:04:22.45#ibcon#*before write, iclass 17, count 0 2006.202.00:04:22.45#ibcon#enter sib2, iclass 17, count 0 2006.202.00:04:22.45#ibcon#flushed, iclass 17, count 0 2006.202.00:04:22.45#ibcon#about to write, iclass 17, count 0 2006.202.00:04:22.45#ibcon#wrote, iclass 17, count 0 2006.202.00:04:22.45#ibcon#about to read 3, iclass 17, count 0 2006.202.00:04:22.48#ibcon#read 3, iclass 17, count 0 2006.202.00:04:22.48#ibcon#about to read 4, iclass 17, count 0 2006.202.00:04:22.48#ibcon#read 4, iclass 17, count 0 2006.202.00:04:22.48#ibcon#about to read 5, iclass 17, count 0 2006.202.00:04:22.48#ibcon#read 5, iclass 17, count 0 2006.202.00:04:22.48#ibcon#about to read 6, iclass 17, count 0 2006.202.00:04:22.48#ibcon#read 6, iclass 17, count 0 2006.202.00:04:22.48#ibcon#end of sib2, iclass 17, count 0 2006.202.00:04:22.48#ibcon#*after write, iclass 17, count 0 2006.202.00:04:22.48#ibcon#*before return 0, iclass 17, count 0 2006.202.00:04:22.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:04:22.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:04:22.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.00:04:22.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.00:04:22.48$setupk4/ifdk4 2006.202.00:04:22.48$ifdk4/lo= 2006.202.00:04:22.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.00:04:22.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.00:04:22.48$ifdk4/patch= 2006.202.00:04:22.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.00:04:22.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.00:04:22.48$setupk4/!*+20s 2006.202.00:04:27.69#abcon#<5=/03 1.2 3.0 20.411001001.4\r\n> 2006.202.00:04:27.71#abcon#{5=INTERFACE CLEAR} 2006.202.00:04:27.77#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:04:29.14#trakl#Source acquired 2006.202.00:04:31.14#flagr#flagr/antenna,acquired 2006.202.00:04:36.56$setupk4/"tpicd 2006.202.00:04:36.56$setupk4/echo=off 2006.202.00:04:36.56$setupk4/xlog=off 2006.202.00:04:36.56:!2006.202.00:04:49 2006.202.00:04:49.00:preob 2006.202.00:04:50.14/onsource/TRACKING 2006.202.00:04:50.14:!2006.202.00:04:59 2006.202.00:04:59.00:"tape 2006.202.00:04:59.00:"st=record 2006.202.00:04:59.00:data_valid=on 2006.202.00:04:59.00:midob 2006.202.00:04:59.14/onsource/TRACKING 2006.202.00:04:59.14/wx/20.42,1001.4,100 2006.202.00:04:59.23/cable/+6.4825E-03 2006.202.00:05:00.32/va/01,08,usb,yes,37,39 2006.202.00:05:00.32/va/02,07,usb,yes,40,41 2006.202.00:05:00.32/va/03,08,usb,yes,36,38 2006.202.00:05:00.32/va/04,07,usb,yes,41,43 2006.202.00:05:00.32/va/05,04,usb,yes,36,37 2006.202.00:05:00.32/va/06,05,usb,yes,37,37 2006.202.00:05:00.32/va/07,05,usb,yes,36,37 2006.202.00:05:00.32/va/08,04,usb,yes,36,42 2006.202.00:05:00.55/valo/01,524.99,yes,locked 2006.202.00:05:00.55/valo/02,534.99,yes,locked 2006.202.00:05:00.55/valo/03,564.99,yes,locked 2006.202.00:05:00.55/valo/04,624.99,yes,locked 2006.202.00:05:00.55/valo/05,734.99,yes,locked 2006.202.00:05:00.55/valo/06,814.99,yes,locked 2006.202.00:05:00.55/valo/07,864.99,yes,locked 2006.202.00:05:00.55/valo/08,884.99,yes,locked 2006.202.00:05:01.64/vb/01,04,usb,yes,30,27 2006.202.00:05:01.64/vb/02,05,usb,yes,28,28 2006.202.00:05:01.64/vb/03,04,usb,yes,29,32 2006.202.00:05:01.64/vb/04,05,usb,yes,29,28 2006.202.00:05:01.64/vb/05,04,usb,yes,25,28 2006.202.00:05:01.64/vb/06,04,usb,yes,30,26 2006.202.00:05:01.64/vb/07,04,usb,yes,30,30 2006.202.00:05:01.64/vb/08,04,usb,yes,27,31 2006.202.00:05:01.88/vblo/01,629.99,yes,locked 2006.202.00:05:01.88/vblo/02,634.99,yes,locked 2006.202.00:05:01.88/vblo/03,649.99,yes,locked 2006.202.00:05:01.88/vblo/04,679.99,yes,locked 2006.202.00:05:01.88/vblo/05,709.99,yes,locked 2006.202.00:05:01.88/vblo/06,719.99,yes,locked 2006.202.00:05:01.88/vblo/07,734.99,yes,locked 2006.202.00:05:01.88/vblo/08,744.99,yes,locked 2006.202.00:05:02.03/vabw/8 2006.202.00:05:02.18/vbbw/8 2006.202.00:05:02.29/xfe/off,on,14.2 2006.202.00:05:02.66/ifatt/23,28,28,28 2006.202.00:05:03.07/fmout-gps/S +4.58E-07 2006.202.00:05:03.11:!2006.202.00:09:59 2006.202.00:09:59.00:data_valid=off 2006.202.00:09:59.00:"et 2006.202.00:09:59.00:!+3s 2006.202.00:10:02.02:"tape 2006.202.00:10:02.02:postob 2006.202.00:10:02.26/cable/+6.4835E-03 2006.202.00:10:02.26/wx/20.44,1001.4,100 2006.202.00:10:02.32/fmout-gps/S +4.59E-07 2006.202.00:10:02.32:scan_name=202-0018,jd0607,220 2006.202.00:10:02.32:source=0014+813,001708.47,813508.1,2000.0,ccw 2006.202.00:10:03.14#flagr#flagr/antenna,new-source 2006.202.00:10:03.14:checkk5 2006.202.00:10:03.55/chk_autoobs//k5ts1/ autoobs is running! 2006.202.00:10:03.95/chk_autoobs//k5ts2/ autoobs is running! 2006.202.00:10:04.36/chk_autoobs//k5ts3/ autoobs is running! 2006.202.00:10:04.76/chk_autoobs//k5ts4/ autoobs is running! 2006.202.00:10:05.14/chk_obsdata//k5ts1/T2020004??a.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.202.00:10:05.54/chk_obsdata//k5ts2/T2020004??b.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.202.00:10:05.94/chk_obsdata//k5ts3/T2020004??c.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.202.00:10:06.34/chk_obsdata//k5ts4/T2020004??d.dat file size is correct (nominal:1200MB, actual:1196MB). 2006.202.00:10:07.06/k5log//k5ts1_log_newline 2006.202.00:10:07.77/k5log//k5ts2_log_newline 2006.202.00:10:08.49/k5log//k5ts3_log_newline 2006.202.00:10:09.21/k5log//k5ts4_log_newline 2006.202.00:10:09.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.00:10:09.23:setupk4=1 2006.202.00:10:09.23$setupk4/echo=on 2006.202.00:10:09.23$setupk4/pcalon 2006.202.00:10:09.23$pcalon/"no phase cal control is implemented here 2006.202.00:10:09.23$setupk4/"tpicd=stop 2006.202.00:10:09.24$setupk4/"rec=synch_on 2006.202.00:10:09.24$setupk4/"rec_mode=128 2006.202.00:10:09.24$setupk4/!* 2006.202.00:10:09.24$setupk4/recpk4 2006.202.00:10:09.24$recpk4/recpatch= 2006.202.00:10:09.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.00:10:09.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.00:10:09.24$setupk4/vck44 2006.202.00:10:09.24$vck44/valo=1,524.99 2006.202.00:10:09.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.00:10:09.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.00:10:09.24#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:09.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:09.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:09.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:09.24#ibcon#enter wrdev, iclass 14, count 0 2006.202.00:10:09.24#ibcon#first serial, iclass 14, count 0 2006.202.00:10:09.24#ibcon#enter sib2, iclass 14, count 0 2006.202.00:10:09.24#ibcon#flushed, iclass 14, count 0 2006.202.00:10:09.24#ibcon#about to write, iclass 14, count 0 2006.202.00:10:09.24#ibcon#wrote, iclass 14, count 0 2006.202.00:10:09.24#ibcon#about to read 3, iclass 14, count 0 2006.202.00:10:09.26#ibcon#read 3, iclass 14, count 0 2006.202.00:10:09.26#ibcon#about to read 4, iclass 14, count 0 2006.202.00:10:09.26#ibcon#read 4, iclass 14, count 0 2006.202.00:10:09.26#ibcon#about to read 5, iclass 14, count 0 2006.202.00:10:09.26#ibcon#read 5, iclass 14, count 0 2006.202.00:10:09.26#ibcon#about to read 6, iclass 14, count 0 2006.202.00:10:09.26#ibcon#read 6, iclass 14, count 0 2006.202.00:10:09.26#ibcon#end of sib2, iclass 14, count 0 2006.202.00:10:09.26#ibcon#*mode == 0, iclass 14, count 0 2006.202.00:10:09.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.00:10:09.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.00:10:09.26#ibcon#*before write, iclass 14, count 0 2006.202.00:10:09.26#ibcon#enter sib2, iclass 14, count 0 2006.202.00:10:09.26#ibcon#flushed, iclass 14, count 0 2006.202.00:10:09.26#ibcon#about to write, iclass 14, count 0 2006.202.00:10:09.26#ibcon#wrote, iclass 14, count 0 2006.202.00:10:09.26#ibcon#about to read 3, iclass 14, count 0 2006.202.00:10:09.31#ibcon#read 3, iclass 14, count 0 2006.202.00:10:09.31#ibcon#about to read 4, iclass 14, count 0 2006.202.00:10:09.31#ibcon#read 4, iclass 14, count 0 2006.202.00:10:09.31#ibcon#about to read 5, iclass 14, count 0 2006.202.00:10:09.31#ibcon#read 5, iclass 14, count 0 2006.202.00:10:09.31#ibcon#about to read 6, iclass 14, count 0 2006.202.00:10:09.31#ibcon#read 6, iclass 14, count 0 2006.202.00:10:09.31#ibcon#end of sib2, iclass 14, count 0 2006.202.00:10:09.31#ibcon#*after write, iclass 14, count 0 2006.202.00:10:09.31#ibcon#*before return 0, iclass 14, count 0 2006.202.00:10:09.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:09.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:09.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.00:10:09.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.00:10:09.31$vck44/va=1,8 2006.202.00:10:09.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.00:10:09.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.00:10:09.31#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:09.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:09.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:09.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:09.31#ibcon#enter wrdev, iclass 16, count 2 2006.202.00:10:09.31#ibcon#first serial, iclass 16, count 2 2006.202.00:10:09.31#ibcon#enter sib2, iclass 16, count 2 2006.202.00:10:09.31#ibcon#flushed, iclass 16, count 2 2006.202.00:10:09.31#ibcon#about to write, iclass 16, count 2 2006.202.00:10:09.31#ibcon#wrote, iclass 16, count 2 2006.202.00:10:09.31#ibcon#about to read 3, iclass 16, count 2 2006.202.00:10:09.33#ibcon#read 3, iclass 16, count 2 2006.202.00:10:09.33#ibcon#about to read 4, iclass 16, count 2 2006.202.00:10:09.33#ibcon#read 4, iclass 16, count 2 2006.202.00:10:09.33#ibcon#about to read 5, iclass 16, count 2 2006.202.00:10:09.33#ibcon#read 5, iclass 16, count 2 2006.202.00:10:09.33#ibcon#about to read 6, iclass 16, count 2 2006.202.00:10:09.33#ibcon#read 6, iclass 16, count 2 2006.202.00:10:09.33#ibcon#end of sib2, iclass 16, count 2 2006.202.00:10:09.33#ibcon#*mode == 0, iclass 16, count 2 2006.202.00:10:09.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.00:10:09.33#ibcon#[25=AT01-08\r\n] 2006.202.00:10:09.33#ibcon#*before write, iclass 16, count 2 2006.202.00:10:09.33#ibcon#enter sib2, iclass 16, count 2 2006.202.00:10:09.33#ibcon#flushed, iclass 16, count 2 2006.202.00:10:09.33#ibcon#about to write, iclass 16, count 2 2006.202.00:10:09.33#ibcon#wrote, iclass 16, count 2 2006.202.00:10:09.33#ibcon#about to read 3, iclass 16, count 2 2006.202.00:10:09.36#ibcon#read 3, iclass 16, count 2 2006.202.00:10:09.36#ibcon#about to read 4, iclass 16, count 2 2006.202.00:10:09.36#ibcon#read 4, iclass 16, count 2 2006.202.00:10:09.36#ibcon#about to read 5, iclass 16, count 2 2006.202.00:10:09.36#ibcon#read 5, iclass 16, count 2 2006.202.00:10:09.36#ibcon#about to read 6, iclass 16, count 2 2006.202.00:10:09.36#ibcon#read 6, iclass 16, count 2 2006.202.00:10:09.36#ibcon#end of sib2, iclass 16, count 2 2006.202.00:10:09.36#ibcon#*after write, iclass 16, count 2 2006.202.00:10:09.36#ibcon#*before return 0, iclass 16, count 2 2006.202.00:10:09.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:09.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:09.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.00:10:09.36#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:09.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:09.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:09.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:09.48#ibcon#enter wrdev, iclass 16, count 0 2006.202.00:10:09.48#ibcon#first serial, iclass 16, count 0 2006.202.00:10:09.48#ibcon#enter sib2, iclass 16, count 0 2006.202.00:10:09.48#ibcon#flushed, iclass 16, count 0 2006.202.00:10:09.48#ibcon#about to write, iclass 16, count 0 2006.202.00:10:09.48#ibcon#wrote, iclass 16, count 0 2006.202.00:10:09.48#ibcon#about to read 3, iclass 16, count 0 2006.202.00:10:09.50#ibcon#read 3, iclass 16, count 0 2006.202.00:10:09.50#ibcon#about to read 4, iclass 16, count 0 2006.202.00:10:09.50#ibcon#read 4, iclass 16, count 0 2006.202.00:10:09.50#ibcon#about to read 5, iclass 16, count 0 2006.202.00:10:09.50#ibcon#read 5, iclass 16, count 0 2006.202.00:10:09.50#ibcon#about to read 6, iclass 16, count 0 2006.202.00:10:09.50#ibcon#read 6, iclass 16, count 0 2006.202.00:10:09.50#ibcon#end of sib2, iclass 16, count 0 2006.202.00:10:09.50#ibcon#*mode == 0, iclass 16, count 0 2006.202.00:10:09.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.00:10:09.50#ibcon#[25=USB\r\n] 2006.202.00:10:09.50#ibcon#*before write, iclass 16, count 0 2006.202.00:10:09.50#ibcon#enter sib2, iclass 16, count 0 2006.202.00:10:09.50#ibcon#flushed, iclass 16, count 0 2006.202.00:10:09.50#ibcon#about to write, iclass 16, count 0 2006.202.00:10:09.50#ibcon#wrote, iclass 16, count 0 2006.202.00:10:09.50#ibcon#about to read 3, iclass 16, count 0 2006.202.00:10:09.53#ibcon#read 3, iclass 16, count 0 2006.202.00:10:09.53#ibcon#about to read 4, iclass 16, count 0 2006.202.00:10:09.53#ibcon#read 4, iclass 16, count 0 2006.202.00:10:09.53#ibcon#about to read 5, iclass 16, count 0 2006.202.00:10:09.53#ibcon#read 5, iclass 16, count 0 2006.202.00:10:09.53#ibcon#about to read 6, iclass 16, count 0 2006.202.00:10:09.53#ibcon#read 6, iclass 16, count 0 2006.202.00:10:09.53#ibcon#end of sib2, iclass 16, count 0 2006.202.00:10:09.53#ibcon#*after write, iclass 16, count 0 2006.202.00:10:09.53#ibcon#*before return 0, iclass 16, count 0 2006.202.00:10:09.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:09.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:09.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.00:10:09.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.00:10:09.53$vck44/valo=2,534.99 2006.202.00:10:09.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.00:10:09.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.00:10:09.53#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:09.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:09.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:09.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:09.53#ibcon#enter wrdev, iclass 18, count 0 2006.202.00:10:09.53#ibcon#first serial, iclass 18, count 0 2006.202.00:10:09.53#ibcon#enter sib2, iclass 18, count 0 2006.202.00:10:09.53#ibcon#flushed, iclass 18, count 0 2006.202.00:10:09.53#ibcon#about to write, iclass 18, count 0 2006.202.00:10:09.53#ibcon#wrote, iclass 18, count 0 2006.202.00:10:09.53#ibcon#about to read 3, iclass 18, count 0 2006.202.00:10:09.55#ibcon#read 3, iclass 18, count 0 2006.202.00:10:09.55#ibcon#about to read 4, iclass 18, count 0 2006.202.00:10:09.55#ibcon#read 4, iclass 18, count 0 2006.202.00:10:09.55#ibcon#about to read 5, iclass 18, count 0 2006.202.00:10:09.55#ibcon#read 5, iclass 18, count 0 2006.202.00:10:09.55#ibcon#about to read 6, iclass 18, count 0 2006.202.00:10:09.55#ibcon#read 6, iclass 18, count 0 2006.202.00:10:09.55#ibcon#end of sib2, iclass 18, count 0 2006.202.00:10:09.55#ibcon#*mode == 0, iclass 18, count 0 2006.202.00:10:09.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.00:10:09.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.00:10:09.55#ibcon#*before write, iclass 18, count 0 2006.202.00:10:09.55#ibcon#enter sib2, iclass 18, count 0 2006.202.00:10:09.55#ibcon#flushed, iclass 18, count 0 2006.202.00:10:09.55#ibcon#about to write, iclass 18, count 0 2006.202.00:10:09.55#ibcon#wrote, iclass 18, count 0 2006.202.00:10:09.55#ibcon#about to read 3, iclass 18, count 0 2006.202.00:10:09.59#ibcon#read 3, iclass 18, count 0 2006.202.00:10:09.59#ibcon#about to read 4, iclass 18, count 0 2006.202.00:10:09.59#ibcon#read 4, iclass 18, count 0 2006.202.00:10:09.59#ibcon#about to read 5, iclass 18, count 0 2006.202.00:10:09.59#ibcon#read 5, iclass 18, count 0 2006.202.00:10:09.59#ibcon#about to read 6, iclass 18, count 0 2006.202.00:10:09.59#ibcon#read 6, iclass 18, count 0 2006.202.00:10:09.59#ibcon#end of sib2, iclass 18, count 0 2006.202.00:10:09.59#ibcon#*after write, iclass 18, count 0 2006.202.00:10:09.59#ibcon#*before return 0, iclass 18, count 0 2006.202.00:10:09.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:09.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:09.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.00:10:09.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.00:10:09.59$vck44/va=2,7 2006.202.00:10:09.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.00:10:09.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.00:10:09.59#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:09.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:09.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:09.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:09.65#ibcon#enter wrdev, iclass 20, count 2 2006.202.00:10:09.65#ibcon#first serial, iclass 20, count 2 2006.202.00:10:09.65#ibcon#enter sib2, iclass 20, count 2 2006.202.00:10:09.65#ibcon#flushed, iclass 20, count 2 2006.202.00:10:09.65#ibcon#about to write, iclass 20, count 2 2006.202.00:10:09.65#ibcon#wrote, iclass 20, count 2 2006.202.00:10:09.65#ibcon#about to read 3, iclass 20, count 2 2006.202.00:10:09.67#ibcon#read 3, iclass 20, count 2 2006.202.00:10:09.67#ibcon#about to read 4, iclass 20, count 2 2006.202.00:10:09.67#ibcon#read 4, iclass 20, count 2 2006.202.00:10:09.67#ibcon#about to read 5, iclass 20, count 2 2006.202.00:10:09.67#ibcon#read 5, iclass 20, count 2 2006.202.00:10:09.67#ibcon#about to read 6, iclass 20, count 2 2006.202.00:10:09.67#ibcon#read 6, iclass 20, count 2 2006.202.00:10:09.67#ibcon#end of sib2, iclass 20, count 2 2006.202.00:10:09.67#ibcon#*mode == 0, iclass 20, count 2 2006.202.00:10:09.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.00:10:09.67#ibcon#[25=AT02-07\r\n] 2006.202.00:10:09.67#ibcon#*before write, iclass 20, count 2 2006.202.00:10:09.67#ibcon#enter sib2, iclass 20, count 2 2006.202.00:10:09.67#ibcon#flushed, iclass 20, count 2 2006.202.00:10:09.67#ibcon#about to write, iclass 20, count 2 2006.202.00:10:09.67#ibcon#wrote, iclass 20, count 2 2006.202.00:10:09.67#ibcon#about to read 3, iclass 20, count 2 2006.202.00:10:09.70#ibcon#read 3, iclass 20, count 2 2006.202.00:10:09.70#ibcon#about to read 4, iclass 20, count 2 2006.202.00:10:09.70#ibcon#read 4, iclass 20, count 2 2006.202.00:10:09.70#ibcon#about to read 5, iclass 20, count 2 2006.202.00:10:09.70#ibcon#read 5, iclass 20, count 2 2006.202.00:10:09.70#ibcon#about to read 6, iclass 20, count 2 2006.202.00:10:09.70#ibcon#read 6, iclass 20, count 2 2006.202.00:10:09.70#ibcon#end of sib2, iclass 20, count 2 2006.202.00:10:09.70#ibcon#*after write, iclass 20, count 2 2006.202.00:10:09.70#ibcon#*before return 0, iclass 20, count 2 2006.202.00:10:09.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:09.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:09.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.00:10:09.70#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:09.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:09.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:09.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:09.82#ibcon#enter wrdev, iclass 20, count 0 2006.202.00:10:09.82#ibcon#first serial, iclass 20, count 0 2006.202.00:10:09.82#ibcon#enter sib2, iclass 20, count 0 2006.202.00:10:09.82#ibcon#flushed, iclass 20, count 0 2006.202.00:10:09.82#ibcon#about to write, iclass 20, count 0 2006.202.00:10:09.82#ibcon#wrote, iclass 20, count 0 2006.202.00:10:09.82#ibcon#about to read 3, iclass 20, count 0 2006.202.00:10:09.84#ibcon#read 3, iclass 20, count 0 2006.202.00:10:09.84#ibcon#about to read 4, iclass 20, count 0 2006.202.00:10:09.84#ibcon#read 4, iclass 20, count 0 2006.202.00:10:09.84#ibcon#about to read 5, iclass 20, count 0 2006.202.00:10:09.84#ibcon#read 5, iclass 20, count 0 2006.202.00:10:09.84#ibcon#about to read 6, iclass 20, count 0 2006.202.00:10:09.84#ibcon#read 6, iclass 20, count 0 2006.202.00:10:09.84#ibcon#end of sib2, iclass 20, count 0 2006.202.00:10:09.84#ibcon#*mode == 0, iclass 20, count 0 2006.202.00:10:09.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.00:10:09.84#ibcon#[25=USB\r\n] 2006.202.00:10:09.84#ibcon#*before write, iclass 20, count 0 2006.202.00:10:09.84#ibcon#enter sib2, iclass 20, count 0 2006.202.00:10:09.84#ibcon#flushed, iclass 20, count 0 2006.202.00:10:09.84#ibcon#about to write, iclass 20, count 0 2006.202.00:10:09.84#ibcon#wrote, iclass 20, count 0 2006.202.00:10:09.84#ibcon#about to read 3, iclass 20, count 0 2006.202.00:10:09.87#ibcon#read 3, iclass 20, count 0 2006.202.00:10:09.87#ibcon#about to read 4, iclass 20, count 0 2006.202.00:10:09.87#ibcon#read 4, iclass 20, count 0 2006.202.00:10:09.87#ibcon#about to read 5, iclass 20, count 0 2006.202.00:10:09.87#ibcon#read 5, iclass 20, count 0 2006.202.00:10:09.87#ibcon#about to read 6, iclass 20, count 0 2006.202.00:10:09.87#ibcon#read 6, iclass 20, count 0 2006.202.00:10:09.87#ibcon#end of sib2, iclass 20, count 0 2006.202.00:10:09.87#ibcon#*after write, iclass 20, count 0 2006.202.00:10:09.87#ibcon#*before return 0, iclass 20, count 0 2006.202.00:10:09.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:09.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:09.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.00:10:09.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.00:10:09.87$vck44/valo=3,564.99 2006.202.00:10:09.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.00:10:09.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.00:10:09.87#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:09.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:09.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:09.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:09.87#ibcon#enter wrdev, iclass 22, count 0 2006.202.00:10:09.87#ibcon#first serial, iclass 22, count 0 2006.202.00:10:09.87#ibcon#enter sib2, iclass 22, count 0 2006.202.00:10:09.87#ibcon#flushed, iclass 22, count 0 2006.202.00:10:09.87#ibcon#about to write, iclass 22, count 0 2006.202.00:10:09.87#ibcon#wrote, iclass 22, count 0 2006.202.00:10:09.87#ibcon#about to read 3, iclass 22, count 0 2006.202.00:10:09.89#ibcon#read 3, iclass 22, count 0 2006.202.00:10:09.89#ibcon#about to read 4, iclass 22, count 0 2006.202.00:10:09.89#ibcon#read 4, iclass 22, count 0 2006.202.00:10:09.89#ibcon#about to read 5, iclass 22, count 0 2006.202.00:10:09.89#ibcon#read 5, iclass 22, count 0 2006.202.00:10:09.89#ibcon#about to read 6, iclass 22, count 0 2006.202.00:10:09.89#ibcon#read 6, iclass 22, count 0 2006.202.00:10:09.89#ibcon#end of sib2, iclass 22, count 0 2006.202.00:10:09.89#ibcon#*mode == 0, iclass 22, count 0 2006.202.00:10:09.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.00:10:09.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.00:10:09.89#ibcon#*before write, iclass 22, count 0 2006.202.00:10:09.89#ibcon#enter sib2, iclass 22, count 0 2006.202.00:10:09.89#ibcon#flushed, iclass 22, count 0 2006.202.00:10:09.89#ibcon#about to write, iclass 22, count 0 2006.202.00:10:09.89#ibcon#wrote, iclass 22, count 0 2006.202.00:10:09.89#ibcon#about to read 3, iclass 22, count 0 2006.202.00:10:09.93#ibcon#read 3, iclass 22, count 0 2006.202.00:10:09.93#ibcon#about to read 4, iclass 22, count 0 2006.202.00:10:09.93#ibcon#read 4, iclass 22, count 0 2006.202.00:10:09.93#ibcon#about to read 5, iclass 22, count 0 2006.202.00:10:09.93#ibcon#read 5, iclass 22, count 0 2006.202.00:10:09.93#ibcon#about to read 6, iclass 22, count 0 2006.202.00:10:09.93#ibcon#read 6, iclass 22, count 0 2006.202.00:10:09.93#ibcon#end of sib2, iclass 22, count 0 2006.202.00:10:09.93#ibcon#*after write, iclass 22, count 0 2006.202.00:10:09.93#ibcon#*before return 0, iclass 22, count 0 2006.202.00:10:09.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:09.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:09.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.00:10:09.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.00:10:09.93$vck44/va=3,8 2006.202.00:10:09.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.00:10:09.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.00:10:09.93#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:09.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:09.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:09.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:09.99#ibcon#enter wrdev, iclass 24, count 2 2006.202.00:10:09.99#ibcon#first serial, iclass 24, count 2 2006.202.00:10:09.99#ibcon#enter sib2, iclass 24, count 2 2006.202.00:10:09.99#ibcon#flushed, iclass 24, count 2 2006.202.00:10:09.99#ibcon#about to write, iclass 24, count 2 2006.202.00:10:09.99#ibcon#wrote, iclass 24, count 2 2006.202.00:10:09.99#ibcon#about to read 3, iclass 24, count 2 2006.202.00:10:10.01#ibcon#read 3, iclass 24, count 2 2006.202.00:10:10.01#ibcon#about to read 4, iclass 24, count 2 2006.202.00:10:10.01#ibcon#read 4, iclass 24, count 2 2006.202.00:10:10.01#ibcon#about to read 5, iclass 24, count 2 2006.202.00:10:10.01#ibcon#read 5, iclass 24, count 2 2006.202.00:10:10.01#ibcon#about to read 6, iclass 24, count 2 2006.202.00:10:10.01#ibcon#read 6, iclass 24, count 2 2006.202.00:10:10.01#ibcon#end of sib2, iclass 24, count 2 2006.202.00:10:10.01#ibcon#*mode == 0, iclass 24, count 2 2006.202.00:10:10.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.00:10:10.01#ibcon#[25=AT03-08\r\n] 2006.202.00:10:10.01#ibcon#*before write, iclass 24, count 2 2006.202.00:10:10.01#ibcon#enter sib2, iclass 24, count 2 2006.202.00:10:10.01#ibcon#flushed, iclass 24, count 2 2006.202.00:10:10.01#ibcon#about to write, iclass 24, count 2 2006.202.00:10:10.01#ibcon#wrote, iclass 24, count 2 2006.202.00:10:10.01#ibcon#about to read 3, iclass 24, count 2 2006.202.00:10:10.04#ibcon#read 3, iclass 24, count 2 2006.202.00:10:10.04#ibcon#about to read 4, iclass 24, count 2 2006.202.00:10:10.04#ibcon#read 4, iclass 24, count 2 2006.202.00:10:10.04#ibcon#about to read 5, iclass 24, count 2 2006.202.00:10:10.04#ibcon#read 5, iclass 24, count 2 2006.202.00:10:10.04#ibcon#about to read 6, iclass 24, count 2 2006.202.00:10:10.04#ibcon#read 6, iclass 24, count 2 2006.202.00:10:10.04#ibcon#end of sib2, iclass 24, count 2 2006.202.00:10:10.04#ibcon#*after write, iclass 24, count 2 2006.202.00:10:10.04#ibcon#*before return 0, iclass 24, count 2 2006.202.00:10:10.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:10.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:10.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.00:10:10.04#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:10.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:10.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:10.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:10.16#ibcon#enter wrdev, iclass 24, count 0 2006.202.00:10:10.16#ibcon#first serial, iclass 24, count 0 2006.202.00:10:10.16#ibcon#enter sib2, iclass 24, count 0 2006.202.00:10:10.16#ibcon#flushed, iclass 24, count 0 2006.202.00:10:10.16#ibcon#about to write, iclass 24, count 0 2006.202.00:10:10.16#ibcon#wrote, iclass 24, count 0 2006.202.00:10:10.16#ibcon#about to read 3, iclass 24, count 0 2006.202.00:10:10.18#ibcon#read 3, iclass 24, count 0 2006.202.00:10:10.18#ibcon#about to read 4, iclass 24, count 0 2006.202.00:10:10.18#ibcon#read 4, iclass 24, count 0 2006.202.00:10:10.18#ibcon#about to read 5, iclass 24, count 0 2006.202.00:10:10.18#ibcon#read 5, iclass 24, count 0 2006.202.00:10:10.18#ibcon#about to read 6, iclass 24, count 0 2006.202.00:10:10.18#ibcon#read 6, iclass 24, count 0 2006.202.00:10:10.18#ibcon#end of sib2, iclass 24, count 0 2006.202.00:10:10.18#ibcon#*mode == 0, iclass 24, count 0 2006.202.00:10:10.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.00:10:10.18#ibcon#[25=USB\r\n] 2006.202.00:10:10.18#ibcon#*before write, iclass 24, count 0 2006.202.00:10:10.18#ibcon#enter sib2, iclass 24, count 0 2006.202.00:10:10.18#ibcon#flushed, iclass 24, count 0 2006.202.00:10:10.18#ibcon#about to write, iclass 24, count 0 2006.202.00:10:10.18#ibcon#wrote, iclass 24, count 0 2006.202.00:10:10.18#ibcon#about to read 3, iclass 24, count 0 2006.202.00:10:10.21#ibcon#read 3, iclass 24, count 0 2006.202.00:10:10.21#ibcon#about to read 4, iclass 24, count 0 2006.202.00:10:10.21#ibcon#read 4, iclass 24, count 0 2006.202.00:10:10.21#ibcon#about to read 5, iclass 24, count 0 2006.202.00:10:10.21#ibcon#read 5, iclass 24, count 0 2006.202.00:10:10.21#ibcon#about to read 6, iclass 24, count 0 2006.202.00:10:10.21#ibcon#read 6, iclass 24, count 0 2006.202.00:10:10.21#ibcon#end of sib2, iclass 24, count 0 2006.202.00:10:10.21#ibcon#*after write, iclass 24, count 0 2006.202.00:10:10.21#ibcon#*before return 0, iclass 24, count 0 2006.202.00:10:10.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:10.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:10.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.00:10:10.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.00:10:10.21$vck44/valo=4,624.99 2006.202.00:10:10.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.00:10:10.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.00:10:10.21#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:10.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:10.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:10.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:10.21#ibcon#enter wrdev, iclass 26, count 0 2006.202.00:10:10.21#ibcon#first serial, iclass 26, count 0 2006.202.00:10:10.21#ibcon#enter sib2, iclass 26, count 0 2006.202.00:10:10.21#ibcon#flushed, iclass 26, count 0 2006.202.00:10:10.21#ibcon#about to write, iclass 26, count 0 2006.202.00:10:10.21#ibcon#wrote, iclass 26, count 0 2006.202.00:10:10.21#ibcon#about to read 3, iclass 26, count 0 2006.202.00:10:10.23#ibcon#read 3, iclass 26, count 0 2006.202.00:10:10.23#ibcon#about to read 4, iclass 26, count 0 2006.202.00:10:10.23#ibcon#read 4, iclass 26, count 0 2006.202.00:10:10.23#ibcon#about to read 5, iclass 26, count 0 2006.202.00:10:10.23#ibcon#read 5, iclass 26, count 0 2006.202.00:10:10.23#ibcon#about to read 6, iclass 26, count 0 2006.202.00:10:10.23#ibcon#read 6, iclass 26, count 0 2006.202.00:10:10.23#ibcon#end of sib2, iclass 26, count 0 2006.202.00:10:10.23#ibcon#*mode == 0, iclass 26, count 0 2006.202.00:10:10.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.00:10:10.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.00:10:10.23#ibcon#*before write, iclass 26, count 0 2006.202.00:10:10.23#ibcon#enter sib2, iclass 26, count 0 2006.202.00:10:10.23#ibcon#flushed, iclass 26, count 0 2006.202.00:10:10.23#ibcon#about to write, iclass 26, count 0 2006.202.00:10:10.23#ibcon#wrote, iclass 26, count 0 2006.202.00:10:10.23#ibcon#about to read 3, iclass 26, count 0 2006.202.00:10:10.27#ibcon#read 3, iclass 26, count 0 2006.202.00:10:10.27#ibcon#about to read 4, iclass 26, count 0 2006.202.00:10:10.27#ibcon#read 4, iclass 26, count 0 2006.202.00:10:10.27#ibcon#about to read 5, iclass 26, count 0 2006.202.00:10:10.27#ibcon#read 5, iclass 26, count 0 2006.202.00:10:10.27#ibcon#about to read 6, iclass 26, count 0 2006.202.00:10:10.27#ibcon#read 6, iclass 26, count 0 2006.202.00:10:10.27#ibcon#end of sib2, iclass 26, count 0 2006.202.00:10:10.27#ibcon#*after write, iclass 26, count 0 2006.202.00:10:10.27#ibcon#*before return 0, iclass 26, count 0 2006.202.00:10:10.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:10.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:10.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.00:10:10.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.00:10:10.27$vck44/va=4,7 2006.202.00:10:10.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.00:10:10.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.00:10:10.27#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:10.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:10.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:10.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:10.33#ibcon#enter wrdev, iclass 28, count 2 2006.202.00:10:10.33#ibcon#first serial, iclass 28, count 2 2006.202.00:10:10.33#ibcon#enter sib2, iclass 28, count 2 2006.202.00:10:10.33#ibcon#flushed, iclass 28, count 2 2006.202.00:10:10.33#ibcon#about to write, iclass 28, count 2 2006.202.00:10:10.33#ibcon#wrote, iclass 28, count 2 2006.202.00:10:10.33#ibcon#about to read 3, iclass 28, count 2 2006.202.00:10:10.35#ibcon#read 3, iclass 28, count 2 2006.202.00:10:10.35#ibcon#about to read 4, iclass 28, count 2 2006.202.00:10:10.35#ibcon#read 4, iclass 28, count 2 2006.202.00:10:10.35#ibcon#about to read 5, iclass 28, count 2 2006.202.00:10:10.35#ibcon#read 5, iclass 28, count 2 2006.202.00:10:10.35#ibcon#about to read 6, iclass 28, count 2 2006.202.00:10:10.35#ibcon#read 6, iclass 28, count 2 2006.202.00:10:10.35#ibcon#end of sib2, iclass 28, count 2 2006.202.00:10:10.35#ibcon#*mode == 0, iclass 28, count 2 2006.202.00:10:10.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.00:10:10.35#ibcon#[25=AT04-07\r\n] 2006.202.00:10:10.35#ibcon#*before write, iclass 28, count 2 2006.202.00:10:10.35#ibcon#enter sib2, iclass 28, count 2 2006.202.00:10:10.35#ibcon#flushed, iclass 28, count 2 2006.202.00:10:10.35#ibcon#about to write, iclass 28, count 2 2006.202.00:10:10.35#ibcon#wrote, iclass 28, count 2 2006.202.00:10:10.35#ibcon#about to read 3, iclass 28, count 2 2006.202.00:10:10.38#ibcon#read 3, iclass 28, count 2 2006.202.00:10:10.39#ibcon#about to read 4, iclass 28, count 2 2006.202.00:10:10.39#ibcon#read 4, iclass 28, count 2 2006.202.00:10:10.39#ibcon#about to read 5, iclass 28, count 2 2006.202.00:10:10.40#ibcon#read 5, iclass 28, count 2 2006.202.00:10:10.40#ibcon#about to read 6, iclass 28, count 2 2006.202.00:10:10.40#ibcon#read 6, iclass 28, count 2 2006.202.00:10:10.40#ibcon#end of sib2, iclass 28, count 2 2006.202.00:10:10.40#ibcon#*after write, iclass 28, count 2 2006.202.00:10:10.40#ibcon#*before return 0, iclass 28, count 2 2006.202.00:10:10.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:10.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:10.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.00:10:10.40#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:10.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:10.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:10.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:10.52#ibcon#enter wrdev, iclass 28, count 0 2006.202.00:10:10.52#ibcon#first serial, iclass 28, count 0 2006.202.00:10:10.52#ibcon#enter sib2, iclass 28, count 0 2006.202.00:10:10.52#ibcon#flushed, iclass 28, count 0 2006.202.00:10:10.52#ibcon#about to write, iclass 28, count 0 2006.202.00:10:10.52#ibcon#wrote, iclass 28, count 0 2006.202.00:10:10.52#ibcon#about to read 3, iclass 28, count 0 2006.202.00:10:10.54#ibcon#read 3, iclass 28, count 0 2006.202.00:10:10.54#ibcon#about to read 4, iclass 28, count 0 2006.202.00:10:10.54#ibcon#read 4, iclass 28, count 0 2006.202.00:10:10.54#ibcon#about to read 5, iclass 28, count 0 2006.202.00:10:10.54#ibcon#read 5, iclass 28, count 0 2006.202.00:10:10.54#ibcon#about to read 6, iclass 28, count 0 2006.202.00:10:10.54#ibcon#read 6, iclass 28, count 0 2006.202.00:10:10.54#ibcon#end of sib2, iclass 28, count 0 2006.202.00:10:10.54#ibcon#*mode == 0, iclass 28, count 0 2006.202.00:10:10.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.00:10:10.54#ibcon#[25=USB\r\n] 2006.202.00:10:10.54#ibcon#*before write, iclass 28, count 0 2006.202.00:10:10.54#ibcon#enter sib2, iclass 28, count 0 2006.202.00:10:10.54#ibcon#flushed, iclass 28, count 0 2006.202.00:10:10.54#ibcon#about to write, iclass 28, count 0 2006.202.00:10:10.54#ibcon#wrote, iclass 28, count 0 2006.202.00:10:10.54#ibcon#about to read 3, iclass 28, count 0 2006.202.00:10:10.57#ibcon#read 3, iclass 28, count 0 2006.202.00:10:10.57#ibcon#about to read 4, iclass 28, count 0 2006.202.00:10:10.57#ibcon#read 4, iclass 28, count 0 2006.202.00:10:10.57#ibcon#about to read 5, iclass 28, count 0 2006.202.00:10:10.57#ibcon#read 5, iclass 28, count 0 2006.202.00:10:10.57#ibcon#about to read 6, iclass 28, count 0 2006.202.00:10:10.57#ibcon#read 6, iclass 28, count 0 2006.202.00:10:10.57#ibcon#end of sib2, iclass 28, count 0 2006.202.00:10:10.57#ibcon#*after write, iclass 28, count 0 2006.202.00:10:10.57#ibcon#*before return 0, iclass 28, count 0 2006.202.00:10:10.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:10.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:10.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.00:10:10.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.00:10:10.57$vck44/valo=5,734.99 2006.202.00:10:10.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.00:10:10.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.00:10:10.57#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:10.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:10:10.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:10:10.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:10:10.57#ibcon#enter wrdev, iclass 30, count 0 2006.202.00:10:10.57#ibcon#first serial, iclass 30, count 0 2006.202.00:10:10.57#ibcon#enter sib2, iclass 30, count 0 2006.202.00:10:10.57#ibcon#flushed, iclass 30, count 0 2006.202.00:10:10.57#ibcon#about to write, iclass 30, count 0 2006.202.00:10:10.57#ibcon#wrote, iclass 30, count 0 2006.202.00:10:10.57#ibcon#about to read 3, iclass 30, count 0 2006.202.00:10:10.59#ibcon#read 3, iclass 30, count 0 2006.202.00:10:10.59#ibcon#about to read 4, iclass 30, count 0 2006.202.00:10:10.59#ibcon#read 4, iclass 30, count 0 2006.202.00:10:10.59#ibcon#about to read 5, iclass 30, count 0 2006.202.00:10:10.59#ibcon#read 5, iclass 30, count 0 2006.202.00:10:10.59#ibcon#about to read 6, iclass 30, count 0 2006.202.00:10:10.59#ibcon#read 6, iclass 30, count 0 2006.202.00:10:10.59#ibcon#end of sib2, iclass 30, count 0 2006.202.00:10:10.59#ibcon#*mode == 0, iclass 30, count 0 2006.202.00:10:10.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.00:10:10.59#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.00:10:10.59#ibcon#*before write, iclass 30, count 0 2006.202.00:10:10.59#ibcon#enter sib2, iclass 30, count 0 2006.202.00:10:10.59#ibcon#flushed, iclass 30, count 0 2006.202.00:10:10.59#ibcon#about to write, iclass 30, count 0 2006.202.00:10:10.59#ibcon#wrote, iclass 30, count 0 2006.202.00:10:10.59#ibcon#about to read 3, iclass 30, count 0 2006.202.00:10:10.63#ibcon#read 3, iclass 30, count 0 2006.202.00:10:10.63#ibcon#about to read 4, iclass 30, count 0 2006.202.00:10:10.63#ibcon#read 4, iclass 30, count 0 2006.202.00:10:10.63#ibcon#about to read 5, iclass 30, count 0 2006.202.00:10:10.63#ibcon#read 5, iclass 30, count 0 2006.202.00:10:10.63#ibcon#about to read 6, iclass 30, count 0 2006.202.00:10:10.63#ibcon#read 6, iclass 30, count 0 2006.202.00:10:10.63#ibcon#end of sib2, iclass 30, count 0 2006.202.00:10:10.63#ibcon#*after write, iclass 30, count 0 2006.202.00:10:10.63#ibcon#*before return 0, iclass 30, count 0 2006.202.00:10:10.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:10:10.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:10:10.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.00:10:10.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.00:10:10.63$vck44/va=5,4 2006.202.00:10:10.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.00:10:10.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.00:10:10.63#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:10.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:10:10.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:10:10.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:10:10.69#ibcon#enter wrdev, iclass 32, count 2 2006.202.00:10:10.69#ibcon#first serial, iclass 32, count 2 2006.202.00:10:10.69#ibcon#enter sib2, iclass 32, count 2 2006.202.00:10:10.69#ibcon#flushed, iclass 32, count 2 2006.202.00:10:10.69#ibcon#about to write, iclass 32, count 2 2006.202.00:10:10.69#ibcon#wrote, iclass 32, count 2 2006.202.00:10:10.69#ibcon#about to read 3, iclass 32, count 2 2006.202.00:10:10.71#ibcon#read 3, iclass 32, count 2 2006.202.00:10:10.71#ibcon#about to read 4, iclass 32, count 2 2006.202.00:10:10.71#ibcon#read 4, iclass 32, count 2 2006.202.00:10:10.71#ibcon#about to read 5, iclass 32, count 2 2006.202.00:10:10.71#ibcon#read 5, iclass 32, count 2 2006.202.00:10:10.71#ibcon#about to read 6, iclass 32, count 2 2006.202.00:10:10.71#ibcon#read 6, iclass 32, count 2 2006.202.00:10:10.71#ibcon#end of sib2, iclass 32, count 2 2006.202.00:10:10.71#ibcon#*mode == 0, iclass 32, count 2 2006.202.00:10:10.71#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.00:10:10.71#ibcon#[25=AT05-04\r\n] 2006.202.00:10:10.71#ibcon#*before write, iclass 32, count 2 2006.202.00:10:10.71#ibcon#enter sib2, iclass 32, count 2 2006.202.00:10:10.71#ibcon#flushed, iclass 32, count 2 2006.202.00:10:10.71#ibcon#about to write, iclass 32, count 2 2006.202.00:10:10.71#ibcon#wrote, iclass 32, count 2 2006.202.00:10:10.71#ibcon#about to read 3, iclass 32, count 2 2006.202.00:10:10.74#ibcon#read 3, iclass 32, count 2 2006.202.00:10:10.74#ibcon#about to read 4, iclass 32, count 2 2006.202.00:10:10.74#ibcon#read 4, iclass 32, count 2 2006.202.00:10:10.74#ibcon#about to read 5, iclass 32, count 2 2006.202.00:10:10.74#ibcon#read 5, iclass 32, count 2 2006.202.00:10:10.74#ibcon#about to read 6, iclass 32, count 2 2006.202.00:10:10.74#ibcon#read 6, iclass 32, count 2 2006.202.00:10:10.74#ibcon#end of sib2, iclass 32, count 2 2006.202.00:10:10.74#ibcon#*after write, iclass 32, count 2 2006.202.00:10:10.74#ibcon#*before return 0, iclass 32, count 2 2006.202.00:10:10.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:10:10.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:10:10.74#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.00:10:10.74#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:10.74#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:10:10.86#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:10:10.86#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:10:10.86#ibcon#enter wrdev, iclass 32, count 0 2006.202.00:10:10.86#ibcon#first serial, iclass 32, count 0 2006.202.00:10:10.86#ibcon#enter sib2, iclass 32, count 0 2006.202.00:10:10.86#ibcon#flushed, iclass 32, count 0 2006.202.00:10:10.86#ibcon#about to write, iclass 32, count 0 2006.202.00:10:10.86#ibcon#wrote, iclass 32, count 0 2006.202.00:10:10.86#ibcon#about to read 3, iclass 32, count 0 2006.202.00:10:10.88#ibcon#read 3, iclass 32, count 0 2006.202.00:10:10.88#ibcon#about to read 4, iclass 32, count 0 2006.202.00:10:10.88#ibcon#read 4, iclass 32, count 0 2006.202.00:10:10.88#ibcon#about to read 5, iclass 32, count 0 2006.202.00:10:10.88#ibcon#read 5, iclass 32, count 0 2006.202.00:10:10.88#ibcon#about to read 6, iclass 32, count 0 2006.202.00:10:10.88#ibcon#read 6, iclass 32, count 0 2006.202.00:10:10.88#ibcon#end of sib2, iclass 32, count 0 2006.202.00:10:10.88#ibcon#*mode == 0, iclass 32, count 0 2006.202.00:10:10.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.00:10:10.88#ibcon#[25=USB\r\n] 2006.202.00:10:10.88#ibcon#*before write, iclass 32, count 0 2006.202.00:10:10.88#ibcon#enter sib2, iclass 32, count 0 2006.202.00:10:10.88#ibcon#flushed, iclass 32, count 0 2006.202.00:10:10.88#ibcon#about to write, iclass 32, count 0 2006.202.00:10:10.88#ibcon#wrote, iclass 32, count 0 2006.202.00:10:10.88#ibcon#about to read 3, iclass 32, count 0 2006.202.00:10:10.91#ibcon#read 3, iclass 32, count 0 2006.202.00:10:10.91#ibcon#about to read 4, iclass 32, count 0 2006.202.00:10:10.91#ibcon#read 4, iclass 32, count 0 2006.202.00:10:10.91#ibcon#about to read 5, iclass 32, count 0 2006.202.00:10:10.91#ibcon#read 5, iclass 32, count 0 2006.202.00:10:10.91#ibcon#about to read 6, iclass 32, count 0 2006.202.00:10:10.91#ibcon#read 6, iclass 32, count 0 2006.202.00:10:10.91#ibcon#end of sib2, iclass 32, count 0 2006.202.00:10:10.91#ibcon#*after write, iclass 32, count 0 2006.202.00:10:10.91#ibcon#*before return 0, iclass 32, count 0 2006.202.00:10:10.91#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:10:10.91#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:10:10.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.00:10:10.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.00:10:10.91$vck44/valo=6,814.99 2006.202.00:10:10.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.00:10:10.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.00:10:10.91#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:10.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:10.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:10.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:10.91#ibcon#enter wrdev, iclass 34, count 0 2006.202.00:10:10.91#ibcon#first serial, iclass 34, count 0 2006.202.00:10:10.91#ibcon#enter sib2, iclass 34, count 0 2006.202.00:10:10.91#ibcon#flushed, iclass 34, count 0 2006.202.00:10:10.91#ibcon#about to write, iclass 34, count 0 2006.202.00:10:10.91#ibcon#wrote, iclass 34, count 0 2006.202.00:10:10.91#ibcon#about to read 3, iclass 34, count 0 2006.202.00:10:10.93#ibcon#read 3, iclass 34, count 0 2006.202.00:10:10.93#ibcon#about to read 4, iclass 34, count 0 2006.202.00:10:10.93#ibcon#read 4, iclass 34, count 0 2006.202.00:10:10.93#ibcon#about to read 5, iclass 34, count 0 2006.202.00:10:10.93#ibcon#read 5, iclass 34, count 0 2006.202.00:10:10.93#ibcon#about to read 6, iclass 34, count 0 2006.202.00:10:10.93#ibcon#read 6, iclass 34, count 0 2006.202.00:10:10.93#ibcon#end of sib2, iclass 34, count 0 2006.202.00:10:10.93#ibcon#*mode == 0, iclass 34, count 0 2006.202.00:10:10.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.00:10:10.93#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.00:10:10.93#ibcon#*before write, iclass 34, count 0 2006.202.00:10:10.93#ibcon#enter sib2, iclass 34, count 0 2006.202.00:10:10.93#ibcon#flushed, iclass 34, count 0 2006.202.00:10:10.93#ibcon#about to write, iclass 34, count 0 2006.202.00:10:10.93#ibcon#wrote, iclass 34, count 0 2006.202.00:10:10.93#ibcon#about to read 3, iclass 34, count 0 2006.202.00:10:10.97#ibcon#read 3, iclass 34, count 0 2006.202.00:10:10.97#ibcon#about to read 4, iclass 34, count 0 2006.202.00:10:10.97#ibcon#read 4, iclass 34, count 0 2006.202.00:10:10.97#ibcon#about to read 5, iclass 34, count 0 2006.202.00:10:10.97#ibcon#read 5, iclass 34, count 0 2006.202.00:10:10.97#ibcon#about to read 6, iclass 34, count 0 2006.202.00:10:10.97#ibcon#read 6, iclass 34, count 0 2006.202.00:10:10.97#ibcon#end of sib2, iclass 34, count 0 2006.202.00:10:10.97#ibcon#*after write, iclass 34, count 0 2006.202.00:10:10.97#ibcon#*before return 0, iclass 34, count 0 2006.202.00:10:10.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:10.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:10.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.00:10:10.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.00:10:10.97$vck44/va=6,5 2006.202.00:10:10.97#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.00:10:10.97#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.00:10:10.97#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:10.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:11.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:11.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:11.03#ibcon#enter wrdev, iclass 36, count 2 2006.202.00:10:11.03#ibcon#first serial, iclass 36, count 2 2006.202.00:10:11.03#ibcon#enter sib2, iclass 36, count 2 2006.202.00:10:11.03#ibcon#flushed, iclass 36, count 2 2006.202.00:10:11.03#ibcon#about to write, iclass 36, count 2 2006.202.00:10:11.03#ibcon#wrote, iclass 36, count 2 2006.202.00:10:11.03#ibcon#about to read 3, iclass 36, count 2 2006.202.00:10:11.05#ibcon#read 3, iclass 36, count 2 2006.202.00:10:11.05#ibcon#about to read 4, iclass 36, count 2 2006.202.00:10:11.05#ibcon#read 4, iclass 36, count 2 2006.202.00:10:11.05#ibcon#about to read 5, iclass 36, count 2 2006.202.00:10:11.05#ibcon#read 5, iclass 36, count 2 2006.202.00:10:11.05#ibcon#about to read 6, iclass 36, count 2 2006.202.00:10:11.05#ibcon#read 6, iclass 36, count 2 2006.202.00:10:11.05#ibcon#end of sib2, iclass 36, count 2 2006.202.00:10:11.05#ibcon#*mode == 0, iclass 36, count 2 2006.202.00:10:11.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.00:10:11.05#ibcon#[25=AT06-05\r\n] 2006.202.00:10:11.05#ibcon#*before write, iclass 36, count 2 2006.202.00:10:11.05#ibcon#enter sib2, iclass 36, count 2 2006.202.00:10:11.05#ibcon#flushed, iclass 36, count 2 2006.202.00:10:11.05#ibcon#about to write, iclass 36, count 2 2006.202.00:10:11.05#ibcon#wrote, iclass 36, count 2 2006.202.00:10:11.05#ibcon#about to read 3, iclass 36, count 2 2006.202.00:10:11.08#ibcon#read 3, iclass 36, count 2 2006.202.00:10:11.08#ibcon#about to read 4, iclass 36, count 2 2006.202.00:10:11.08#ibcon#read 4, iclass 36, count 2 2006.202.00:10:11.08#ibcon#about to read 5, iclass 36, count 2 2006.202.00:10:11.08#ibcon#read 5, iclass 36, count 2 2006.202.00:10:11.08#ibcon#about to read 6, iclass 36, count 2 2006.202.00:10:11.08#ibcon#read 6, iclass 36, count 2 2006.202.00:10:11.08#ibcon#end of sib2, iclass 36, count 2 2006.202.00:10:11.08#ibcon#*after write, iclass 36, count 2 2006.202.00:10:11.08#ibcon#*before return 0, iclass 36, count 2 2006.202.00:10:11.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:11.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:11.08#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.00:10:11.08#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:11.08#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:11.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:11.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:11.20#ibcon#enter wrdev, iclass 36, count 0 2006.202.00:10:11.20#ibcon#first serial, iclass 36, count 0 2006.202.00:10:11.20#ibcon#enter sib2, iclass 36, count 0 2006.202.00:10:11.20#ibcon#flushed, iclass 36, count 0 2006.202.00:10:11.20#ibcon#about to write, iclass 36, count 0 2006.202.00:10:11.20#ibcon#wrote, iclass 36, count 0 2006.202.00:10:11.20#ibcon#about to read 3, iclass 36, count 0 2006.202.00:10:11.22#ibcon#read 3, iclass 36, count 0 2006.202.00:10:11.22#ibcon#about to read 4, iclass 36, count 0 2006.202.00:10:11.22#ibcon#read 4, iclass 36, count 0 2006.202.00:10:11.22#ibcon#about to read 5, iclass 36, count 0 2006.202.00:10:11.22#ibcon#read 5, iclass 36, count 0 2006.202.00:10:11.22#ibcon#about to read 6, iclass 36, count 0 2006.202.00:10:11.22#ibcon#read 6, iclass 36, count 0 2006.202.00:10:11.22#ibcon#end of sib2, iclass 36, count 0 2006.202.00:10:11.22#ibcon#*mode == 0, iclass 36, count 0 2006.202.00:10:11.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.00:10:11.22#ibcon#[25=USB\r\n] 2006.202.00:10:11.22#ibcon#*before write, iclass 36, count 0 2006.202.00:10:11.22#ibcon#enter sib2, iclass 36, count 0 2006.202.00:10:11.22#ibcon#flushed, iclass 36, count 0 2006.202.00:10:11.22#ibcon#about to write, iclass 36, count 0 2006.202.00:10:11.22#ibcon#wrote, iclass 36, count 0 2006.202.00:10:11.22#ibcon#about to read 3, iclass 36, count 0 2006.202.00:10:11.25#ibcon#read 3, iclass 36, count 0 2006.202.00:10:11.25#ibcon#about to read 4, iclass 36, count 0 2006.202.00:10:11.25#ibcon#read 4, iclass 36, count 0 2006.202.00:10:11.25#ibcon#about to read 5, iclass 36, count 0 2006.202.00:10:11.25#ibcon#read 5, iclass 36, count 0 2006.202.00:10:11.25#ibcon#about to read 6, iclass 36, count 0 2006.202.00:10:11.25#ibcon#read 6, iclass 36, count 0 2006.202.00:10:11.25#ibcon#end of sib2, iclass 36, count 0 2006.202.00:10:11.25#ibcon#*after write, iclass 36, count 0 2006.202.00:10:11.25#ibcon#*before return 0, iclass 36, count 0 2006.202.00:10:11.25#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:11.25#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:11.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.00:10:11.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.00:10:11.25$vck44/valo=7,864.99 2006.202.00:10:11.25#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.00:10:11.25#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.00:10:11.25#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:11.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:11.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:11.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:11.25#ibcon#enter wrdev, iclass 38, count 0 2006.202.00:10:11.25#ibcon#first serial, iclass 38, count 0 2006.202.00:10:11.25#ibcon#enter sib2, iclass 38, count 0 2006.202.00:10:11.25#ibcon#flushed, iclass 38, count 0 2006.202.00:10:11.25#ibcon#about to write, iclass 38, count 0 2006.202.00:10:11.25#ibcon#wrote, iclass 38, count 0 2006.202.00:10:11.25#ibcon#about to read 3, iclass 38, count 0 2006.202.00:10:11.27#ibcon#read 3, iclass 38, count 0 2006.202.00:10:11.27#ibcon#about to read 4, iclass 38, count 0 2006.202.00:10:11.27#ibcon#read 4, iclass 38, count 0 2006.202.00:10:11.27#ibcon#about to read 5, iclass 38, count 0 2006.202.00:10:11.27#ibcon#read 5, iclass 38, count 0 2006.202.00:10:11.27#ibcon#about to read 6, iclass 38, count 0 2006.202.00:10:11.27#ibcon#read 6, iclass 38, count 0 2006.202.00:10:11.27#ibcon#end of sib2, iclass 38, count 0 2006.202.00:10:11.27#ibcon#*mode == 0, iclass 38, count 0 2006.202.00:10:11.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.00:10:11.27#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.00:10:11.27#ibcon#*before write, iclass 38, count 0 2006.202.00:10:11.27#ibcon#enter sib2, iclass 38, count 0 2006.202.00:10:11.27#ibcon#flushed, iclass 38, count 0 2006.202.00:10:11.27#ibcon#about to write, iclass 38, count 0 2006.202.00:10:11.27#ibcon#wrote, iclass 38, count 0 2006.202.00:10:11.27#ibcon#about to read 3, iclass 38, count 0 2006.202.00:10:11.31#ibcon#read 3, iclass 38, count 0 2006.202.00:10:11.31#ibcon#about to read 4, iclass 38, count 0 2006.202.00:10:11.31#ibcon#read 4, iclass 38, count 0 2006.202.00:10:11.31#ibcon#about to read 5, iclass 38, count 0 2006.202.00:10:11.31#ibcon#read 5, iclass 38, count 0 2006.202.00:10:11.31#ibcon#about to read 6, iclass 38, count 0 2006.202.00:10:11.31#ibcon#read 6, iclass 38, count 0 2006.202.00:10:11.31#ibcon#end of sib2, iclass 38, count 0 2006.202.00:10:11.31#ibcon#*after write, iclass 38, count 0 2006.202.00:10:11.31#ibcon#*before return 0, iclass 38, count 0 2006.202.00:10:11.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:11.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:11.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.00:10:11.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.00:10:11.31$vck44/va=7,5 2006.202.00:10:11.31#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.202.00:10:11.31#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.202.00:10:11.31#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:11.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:11.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:11.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:11.37#ibcon#enter wrdev, iclass 40, count 2 2006.202.00:10:11.37#ibcon#first serial, iclass 40, count 2 2006.202.00:10:11.37#ibcon#enter sib2, iclass 40, count 2 2006.202.00:10:11.37#ibcon#flushed, iclass 40, count 2 2006.202.00:10:11.37#ibcon#about to write, iclass 40, count 2 2006.202.00:10:11.37#ibcon#wrote, iclass 40, count 2 2006.202.00:10:11.37#ibcon#about to read 3, iclass 40, count 2 2006.202.00:10:11.39#ibcon#read 3, iclass 40, count 2 2006.202.00:10:11.39#ibcon#about to read 4, iclass 40, count 2 2006.202.00:10:11.39#ibcon#read 4, iclass 40, count 2 2006.202.00:10:11.39#ibcon#about to read 5, iclass 40, count 2 2006.202.00:10:11.39#ibcon#read 5, iclass 40, count 2 2006.202.00:10:11.39#ibcon#about to read 6, iclass 40, count 2 2006.202.00:10:11.39#ibcon#read 6, iclass 40, count 2 2006.202.00:10:11.39#ibcon#end of sib2, iclass 40, count 2 2006.202.00:10:11.39#ibcon#*mode == 0, iclass 40, count 2 2006.202.00:10:11.39#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.202.00:10:11.39#ibcon#[25=AT07-05\r\n] 2006.202.00:10:11.39#ibcon#*before write, iclass 40, count 2 2006.202.00:10:11.39#ibcon#enter sib2, iclass 40, count 2 2006.202.00:10:11.39#ibcon#flushed, iclass 40, count 2 2006.202.00:10:11.39#ibcon#about to write, iclass 40, count 2 2006.202.00:10:11.39#ibcon#wrote, iclass 40, count 2 2006.202.00:10:11.39#ibcon#about to read 3, iclass 40, count 2 2006.202.00:10:11.47#ibcon#read 3, iclass 40, count 2 2006.202.00:10:11.47#ibcon#about to read 4, iclass 40, count 2 2006.202.00:10:11.47#ibcon#read 4, iclass 40, count 2 2006.202.00:10:11.47#ibcon#about to read 5, iclass 40, count 2 2006.202.00:10:11.47#ibcon#read 5, iclass 40, count 2 2006.202.00:10:11.47#ibcon#about to read 6, iclass 40, count 2 2006.202.00:10:11.47#ibcon#read 6, iclass 40, count 2 2006.202.00:10:11.47#ibcon#end of sib2, iclass 40, count 2 2006.202.00:10:11.47#ibcon#*after write, iclass 40, count 2 2006.202.00:10:11.47#ibcon#*before return 0, iclass 40, count 2 2006.202.00:10:11.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:11.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:11.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.202.00:10:11.47#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:11.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:11.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:11.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:11.59#ibcon#enter wrdev, iclass 40, count 0 2006.202.00:10:11.59#ibcon#first serial, iclass 40, count 0 2006.202.00:10:11.59#ibcon#enter sib2, iclass 40, count 0 2006.202.00:10:11.59#ibcon#flushed, iclass 40, count 0 2006.202.00:10:11.59#ibcon#about to write, iclass 40, count 0 2006.202.00:10:11.59#ibcon#wrote, iclass 40, count 0 2006.202.00:10:11.59#ibcon#about to read 3, iclass 40, count 0 2006.202.00:10:11.61#ibcon#read 3, iclass 40, count 0 2006.202.00:10:11.61#ibcon#about to read 4, iclass 40, count 0 2006.202.00:10:11.61#ibcon#read 4, iclass 40, count 0 2006.202.00:10:11.61#ibcon#about to read 5, iclass 40, count 0 2006.202.00:10:11.61#ibcon#read 5, iclass 40, count 0 2006.202.00:10:11.61#ibcon#about to read 6, iclass 40, count 0 2006.202.00:10:11.61#ibcon#read 6, iclass 40, count 0 2006.202.00:10:11.61#ibcon#end of sib2, iclass 40, count 0 2006.202.00:10:11.61#ibcon#*mode == 0, iclass 40, count 0 2006.202.00:10:11.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.00:10:11.61#ibcon#[25=USB\r\n] 2006.202.00:10:11.61#ibcon#*before write, iclass 40, count 0 2006.202.00:10:11.61#ibcon#enter sib2, iclass 40, count 0 2006.202.00:10:11.61#ibcon#flushed, iclass 40, count 0 2006.202.00:10:11.61#ibcon#about to write, iclass 40, count 0 2006.202.00:10:11.61#ibcon#wrote, iclass 40, count 0 2006.202.00:10:11.61#ibcon#about to read 3, iclass 40, count 0 2006.202.00:10:11.64#ibcon#read 3, iclass 40, count 0 2006.202.00:10:11.64#ibcon#about to read 4, iclass 40, count 0 2006.202.00:10:11.64#ibcon#read 4, iclass 40, count 0 2006.202.00:10:11.64#ibcon#about to read 5, iclass 40, count 0 2006.202.00:10:11.64#ibcon#read 5, iclass 40, count 0 2006.202.00:10:11.64#ibcon#about to read 6, iclass 40, count 0 2006.202.00:10:11.64#ibcon#read 6, iclass 40, count 0 2006.202.00:10:11.64#ibcon#end of sib2, iclass 40, count 0 2006.202.00:10:11.64#ibcon#*after write, iclass 40, count 0 2006.202.00:10:11.64#ibcon#*before return 0, iclass 40, count 0 2006.202.00:10:11.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:11.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:11.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.00:10:11.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.00:10:11.64$vck44/valo=8,884.99 2006.202.00:10:11.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.00:10:11.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.00:10:11.64#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:11.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:11.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:11.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:11.64#ibcon#enter wrdev, iclass 4, count 0 2006.202.00:10:11.64#ibcon#first serial, iclass 4, count 0 2006.202.00:10:11.64#ibcon#enter sib2, iclass 4, count 0 2006.202.00:10:11.64#ibcon#flushed, iclass 4, count 0 2006.202.00:10:11.64#ibcon#about to write, iclass 4, count 0 2006.202.00:10:11.64#ibcon#wrote, iclass 4, count 0 2006.202.00:10:11.64#ibcon#about to read 3, iclass 4, count 0 2006.202.00:10:11.66#ibcon#read 3, iclass 4, count 0 2006.202.00:10:11.66#ibcon#about to read 4, iclass 4, count 0 2006.202.00:10:11.66#ibcon#read 4, iclass 4, count 0 2006.202.00:10:11.66#ibcon#about to read 5, iclass 4, count 0 2006.202.00:10:11.66#ibcon#read 5, iclass 4, count 0 2006.202.00:10:11.66#ibcon#about to read 6, iclass 4, count 0 2006.202.00:10:11.66#ibcon#read 6, iclass 4, count 0 2006.202.00:10:11.66#ibcon#end of sib2, iclass 4, count 0 2006.202.00:10:11.66#ibcon#*mode == 0, iclass 4, count 0 2006.202.00:10:11.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.00:10:11.66#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.00:10:11.66#ibcon#*before write, iclass 4, count 0 2006.202.00:10:11.66#ibcon#enter sib2, iclass 4, count 0 2006.202.00:10:11.66#ibcon#flushed, iclass 4, count 0 2006.202.00:10:11.66#ibcon#about to write, iclass 4, count 0 2006.202.00:10:11.66#ibcon#wrote, iclass 4, count 0 2006.202.00:10:11.66#ibcon#about to read 3, iclass 4, count 0 2006.202.00:10:11.70#ibcon#read 3, iclass 4, count 0 2006.202.00:10:11.70#ibcon#about to read 4, iclass 4, count 0 2006.202.00:10:11.70#ibcon#read 4, iclass 4, count 0 2006.202.00:10:11.70#ibcon#about to read 5, iclass 4, count 0 2006.202.00:10:11.70#ibcon#read 5, iclass 4, count 0 2006.202.00:10:11.70#ibcon#about to read 6, iclass 4, count 0 2006.202.00:10:11.70#ibcon#read 6, iclass 4, count 0 2006.202.00:10:11.70#ibcon#end of sib2, iclass 4, count 0 2006.202.00:10:11.70#ibcon#*after write, iclass 4, count 0 2006.202.00:10:11.70#ibcon#*before return 0, iclass 4, count 0 2006.202.00:10:11.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:11.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:11.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.00:10:11.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.00:10:11.70$vck44/va=8,4 2006.202.00:10:11.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.202.00:10:11.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.202.00:10:11.70#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:11.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:11.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:11.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:11.76#ibcon#enter wrdev, iclass 6, count 2 2006.202.00:10:11.76#ibcon#first serial, iclass 6, count 2 2006.202.00:10:11.76#ibcon#enter sib2, iclass 6, count 2 2006.202.00:10:11.76#ibcon#flushed, iclass 6, count 2 2006.202.00:10:11.76#ibcon#about to write, iclass 6, count 2 2006.202.00:10:11.76#ibcon#wrote, iclass 6, count 2 2006.202.00:10:11.76#ibcon#about to read 3, iclass 6, count 2 2006.202.00:10:11.78#ibcon#read 3, iclass 6, count 2 2006.202.00:10:11.78#ibcon#about to read 4, iclass 6, count 2 2006.202.00:10:11.78#ibcon#read 4, iclass 6, count 2 2006.202.00:10:11.78#ibcon#about to read 5, iclass 6, count 2 2006.202.00:10:11.78#ibcon#read 5, iclass 6, count 2 2006.202.00:10:11.78#ibcon#about to read 6, iclass 6, count 2 2006.202.00:10:11.78#ibcon#read 6, iclass 6, count 2 2006.202.00:10:11.78#ibcon#end of sib2, iclass 6, count 2 2006.202.00:10:11.78#ibcon#*mode == 0, iclass 6, count 2 2006.202.00:10:11.78#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.202.00:10:11.78#ibcon#[25=AT08-04\r\n] 2006.202.00:10:11.78#ibcon#*before write, iclass 6, count 2 2006.202.00:10:11.78#ibcon#enter sib2, iclass 6, count 2 2006.202.00:10:11.78#ibcon#flushed, iclass 6, count 2 2006.202.00:10:11.78#ibcon#about to write, iclass 6, count 2 2006.202.00:10:11.78#ibcon#wrote, iclass 6, count 2 2006.202.00:10:11.78#ibcon#about to read 3, iclass 6, count 2 2006.202.00:10:11.81#ibcon#read 3, iclass 6, count 2 2006.202.00:10:11.81#ibcon#about to read 4, iclass 6, count 2 2006.202.00:10:11.81#ibcon#read 4, iclass 6, count 2 2006.202.00:10:11.81#ibcon#about to read 5, iclass 6, count 2 2006.202.00:10:11.81#ibcon#read 5, iclass 6, count 2 2006.202.00:10:11.81#ibcon#about to read 6, iclass 6, count 2 2006.202.00:10:11.81#ibcon#read 6, iclass 6, count 2 2006.202.00:10:11.81#ibcon#end of sib2, iclass 6, count 2 2006.202.00:10:11.81#ibcon#*after write, iclass 6, count 2 2006.202.00:10:11.81#ibcon#*before return 0, iclass 6, count 2 2006.202.00:10:11.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:11.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:11.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.202.00:10:11.81#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:11.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:11.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:11.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:11.93#ibcon#enter wrdev, iclass 6, count 0 2006.202.00:10:11.93#ibcon#first serial, iclass 6, count 0 2006.202.00:10:11.93#ibcon#enter sib2, iclass 6, count 0 2006.202.00:10:11.93#ibcon#flushed, iclass 6, count 0 2006.202.00:10:11.93#ibcon#about to write, iclass 6, count 0 2006.202.00:10:11.93#ibcon#wrote, iclass 6, count 0 2006.202.00:10:11.93#ibcon#about to read 3, iclass 6, count 0 2006.202.00:10:11.95#ibcon#read 3, iclass 6, count 0 2006.202.00:10:11.95#ibcon#about to read 4, iclass 6, count 0 2006.202.00:10:11.95#ibcon#read 4, iclass 6, count 0 2006.202.00:10:11.95#ibcon#about to read 5, iclass 6, count 0 2006.202.00:10:11.95#ibcon#read 5, iclass 6, count 0 2006.202.00:10:11.95#ibcon#about to read 6, iclass 6, count 0 2006.202.00:10:11.95#ibcon#read 6, iclass 6, count 0 2006.202.00:10:11.95#ibcon#end of sib2, iclass 6, count 0 2006.202.00:10:11.95#ibcon#*mode == 0, iclass 6, count 0 2006.202.00:10:11.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.00:10:11.95#ibcon#[25=USB\r\n] 2006.202.00:10:11.95#ibcon#*before write, iclass 6, count 0 2006.202.00:10:11.95#ibcon#enter sib2, iclass 6, count 0 2006.202.00:10:11.95#ibcon#flushed, iclass 6, count 0 2006.202.00:10:11.95#ibcon#about to write, iclass 6, count 0 2006.202.00:10:11.95#ibcon#wrote, iclass 6, count 0 2006.202.00:10:11.95#ibcon#about to read 3, iclass 6, count 0 2006.202.00:10:11.98#ibcon#read 3, iclass 6, count 0 2006.202.00:10:11.98#ibcon#about to read 4, iclass 6, count 0 2006.202.00:10:11.98#ibcon#read 4, iclass 6, count 0 2006.202.00:10:11.98#ibcon#about to read 5, iclass 6, count 0 2006.202.00:10:11.98#ibcon#read 5, iclass 6, count 0 2006.202.00:10:11.98#ibcon#about to read 6, iclass 6, count 0 2006.202.00:10:11.98#ibcon#read 6, iclass 6, count 0 2006.202.00:10:11.98#ibcon#end of sib2, iclass 6, count 0 2006.202.00:10:11.98#ibcon#*after write, iclass 6, count 0 2006.202.00:10:11.98#ibcon#*before return 0, iclass 6, count 0 2006.202.00:10:11.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:11.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:11.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.00:10:11.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.00:10:11.98$vck44/vblo=1,629.99 2006.202.00:10:11.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.00:10:11.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.00:10:11.98#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:11.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:11.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:11.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:11.98#ibcon#enter wrdev, iclass 10, count 0 2006.202.00:10:11.98#ibcon#first serial, iclass 10, count 0 2006.202.00:10:11.98#ibcon#enter sib2, iclass 10, count 0 2006.202.00:10:11.98#ibcon#flushed, iclass 10, count 0 2006.202.00:10:11.98#ibcon#about to write, iclass 10, count 0 2006.202.00:10:11.98#ibcon#wrote, iclass 10, count 0 2006.202.00:10:11.98#ibcon#about to read 3, iclass 10, count 0 2006.202.00:10:12.00#ibcon#read 3, iclass 10, count 0 2006.202.00:10:12.00#ibcon#about to read 4, iclass 10, count 0 2006.202.00:10:12.00#ibcon#read 4, iclass 10, count 0 2006.202.00:10:12.00#ibcon#about to read 5, iclass 10, count 0 2006.202.00:10:12.00#ibcon#read 5, iclass 10, count 0 2006.202.00:10:12.00#ibcon#about to read 6, iclass 10, count 0 2006.202.00:10:12.00#ibcon#read 6, iclass 10, count 0 2006.202.00:10:12.00#ibcon#end of sib2, iclass 10, count 0 2006.202.00:10:12.00#ibcon#*mode == 0, iclass 10, count 0 2006.202.00:10:12.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.00:10:12.00#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.00:10:12.00#ibcon#*before write, iclass 10, count 0 2006.202.00:10:12.00#ibcon#enter sib2, iclass 10, count 0 2006.202.00:10:12.00#ibcon#flushed, iclass 10, count 0 2006.202.00:10:12.00#ibcon#about to write, iclass 10, count 0 2006.202.00:10:12.00#ibcon#wrote, iclass 10, count 0 2006.202.00:10:12.00#ibcon#about to read 3, iclass 10, count 0 2006.202.00:10:12.04#ibcon#read 3, iclass 10, count 0 2006.202.00:10:12.04#ibcon#about to read 4, iclass 10, count 0 2006.202.00:10:12.04#ibcon#read 4, iclass 10, count 0 2006.202.00:10:12.04#ibcon#about to read 5, iclass 10, count 0 2006.202.00:10:12.04#ibcon#read 5, iclass 10, count 0 2006.202.00:10:12.04#ibcon#about to read 6, iclass 10, count 0 2006.202.00:10:12.04#ibcon#read 6, iclass 10, count 0 2006.202.00:10:12.04#ibcon#end of sib2, iclass 10, count 0 2006.202.00:10:12.04#ibcon#*after write, iclass 10, count 0 2006.202.00:10:12.04#ibcon#*before return 0, iclass 10, count 0 2006.202.00:10:12.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:12.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:12.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.00:10:12.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.00:10:12.04$vck44/vb=1,4 2006.202.00:10:12.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.202.00:10:12.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.202.00:10:12.04#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:12.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:10:12.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:10:12.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:10:12.04#ibcon#enter wrdev, iclass 12, count 2 2006.202.00:10:12.04#ibcon#first serial, iclass 12, count 2 2006.202.00:10:12.04#ibcon#enter sib2, iclass 12, count 2 2006.202.00:10:12.04#ibcon#flushed, iclass 12, count 2 2006.202.00:10:12.04#ibcon#about to write, iclass 12, count 2 2006.202.00:10:12.04#ibcon#wrote, iclass 12, count 2 2006.202.00:10:12.04#ibcon#about to read 3, iclass 12, count 2 2006.202.00:10:12.06#ibcon#read 3, iclass 12, count 2 2006.202.00:10:12.06#ibcon#about to read 4, iclass 12, count 2 2006.202.00:10:12.06#ibcon#read 4, iclass 12, count 2 2006.202.00:10:12.06#ibcon#about to read 5, iclass 12, count 2 2006.202.00:10:12.06#ibcon#read 5, iclass 12, count 2 2006.202.00:10:12.06#ibcon#about to read 6, iclass 12, count 2 2006.202.00:10:12.06#ibcon#read 6, iclass 12, count 2 2006.202.00:10:12.06#ibcon#end of sib2, iclass 12, count 2 2006.202.00:10:12.06#ibcon#*mode == 0, iclass 12, count 2 2006.202.00:10:12.06#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.202.00:10:12.06#ibcon#[27=AT01-04\r\n] 2006.202.00:10:12.06#ibcon#*before write, iclass 12, count 2 2006.202.00:10:12.06#ibcon#enter sib2, iclass 12, count 2 2006.202.00:10:12.06#ibcon#flushed, iclass 12, count 2 2006.202.00:10:12.06#ibcon#about to write, iclass 12, count 2 2006.202.00:10:12.06#ibcon#wrote, iclass 12, count 2 2006.202.00:10:12.06#ibcon#about to read 3, iclass 12, count 2 2006.202.00:10:12.09#ibcon#read 3, iclass 12, count 2 2006.202.00:10:12.09#ibcon#about to read 4, iclass 12, count 2 2006.202.00:10:12.09#ibcon#read 4, iclass 12, count 2 2006.202.00:10:12.09#ibcon#about to read 5, iclass 12, count 2 2006.202.00:10:12.09#ibcon#read 5, iclass 12, count 2 2006.202.00:10:12.09#ibcon#about to read 6, iclass 12, count 2 2006.202.00:10:12.09#ibcon#read 6, iclass 12, count 2 2006.202.00:10:12.09#ibcon#end of sib2, iclass 12, count 2 2006.202.00:10:12.09#ibcon#*after write, iclass 12, count 2 2006.202.00:10:12.09#ibcon#*before return 0, iclass 12, count 2 2006.202.00:10:12.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:10:12.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:10:12.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.202.00:10:12.09#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:12.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:10:12.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:10:12.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:10:12.21#ibcon#enter wrdev, iclass 12, count 0 2006.202.00:10:12.21#ibcon#first serial, iclass 12, count 0 2006.202.00:10:12.21#ibcon#enter sib2, iclass 12, count 0 2006.202.00:10:12.21#ibcon#flushed, iclass 12, count 0 2006.202.00:10:12.21#ibcon#about to write, iclass 12, count 0 2006.202.00:10:12.21#ibcon#wrote, iclass 12, count 0 2006.202.00:10:12.21#ibcon#about to read 3, iclass 12, count 0 2006.202.00:10:12.23#ibcon#read 3, iclass 12, count 0 2006.202.00:10:12.23#ibcon#about to read 4, iclass 12, count 0 2006.202.00:10:12.23#ibcon#read 4, iclass 12, count 0 2006.202.00:10:12.23#ibcon#about to read 5, iclass 12, count 0 2006.202.00:10:12.23#ibcon#read 5, iclass 12, count 0 2006.202.00:10:12.23#ibcon#about to read 6, iclass 12, count 0 2006.202.00:10:12.23#ibcon#read 6, iclass 12, count 0 2006.202.00:10:12.23#ibcon#end of sib2, iclass 12, count 0 2006.202.00:10:12.23#ibcon#*mode == 0, iclass 12, count 0 2006.202.00:10:12.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.00:10:12.23#ibcon#[27=USB\r\n] 2006.202.00:10:12.23#ibcon#*before write, iclass 12, count 0 2006.202.00:10:12.23#ibcon#enter sib2, iclass 12, count 0 2006.202.00:10:12.23#ibcon#flushed, iclass 12, count 0 2006.202.00:10:12.23#ibcon#about to write, iclass 12, count 0 2006.202.00:10:12.23#ibcon#wrote, iclass 12, count 0 2006.202.00:10:12.23#ibcon#about to read 3, iclass 12, count 0 2006.202.00:10:12.26#ibcon#read 3, iclass 12, count 0 2006.202.00:10:12.26#ibcon#about to read 4, iclass 12, count 0 2006.202.00:10:12.26#ibcon#read 4, iclass 12, count 0 2006.202.00:10:12.26#ibcon#about to read 5, iclass 12, count 0 2006.202.00:10:12.26#ibcon#read 5, iclass 12, count 0 2006.202.00:10:12.26#ibcon#about to read 6, iclass 12, count 0 2006.202.00:10:12.26#ibcon#read 6, iclass 12, count 0 2006.202.00:10:12.26#ibcon#end of sib2, iclass 12, count 0 2006.202.00:10:12.26#ibcon#*after write, iclass 12, count 0 2006.202.00:10:12.26#ibcon#*before return 0, iclass 12, count 0 2006.202.00:10:12.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:10:12.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:10:12.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.00:10:12.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.00:10:12.26$vck44/vblo=2,634.99 2006.202.00:10:12.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.00:10:12.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.00:10:12.26#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:12.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:12.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:12.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:12.26#ibcon#enter wrdev, iclass 14, count 0 2006.202.00:10:12.26#ibcon#first serial, iclass 14, count 0 2006.202.00:10:12.26#ibcon#enter sib2, iclass 14, count 0 2006.202.00:10:12.26#ibcon#flushed, iclass 14, count 0 2006.202.00:10:12.26#ibcon#about to write, iclass 14, count 0 2006.202.00:10:12.26#ibcon#wrote, iclass 14, count 0 2006.202.00:10:12.26#ibcon#about to read 3, iclass 14, count 0 2006.202.00:10:12.28#ibcon#read 3, iclass 14, count 0 2006.202.00:10:12.28#ibcon#about to read 4, iclass 14, count 0 2006.202.00:10:12.28#ibcon#read 4, iclass 14, count 0 2006.202.00:10:12.28#ibcon#about to read 5, iclass 14, count 0 2006.202.00:10:12.28#ibcon#read 5, iclass 14, count 0 2006.202.00:10:12.28#ibcon#about to read 6, iclass 14, count 0 2006.202.00:10:12.28#ibcon#read 6, iclass 14, count 0 2006.202.00:10:12.28#ibcon#end of sib2, iclass 14, count 0 2006.202.00:10:12.28#ibcon#*mode == 0, iclass 14, count 0 2006.202.00:10:12.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.00:10:12.28#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.00:10:12.28#ibcon#*before write, iclass 14, count 0 2006.202.00:10:12.28#ibcon#enter sib2, iclass 14, count 0 2006.202.00:10:12.28#ibcon#flushed, iclass 14, count 0 2006.202.00:10:12.28#ibcon#about to write, iclass 14, count 0 2006.202.00:10:12.28#ibcon#wrote, iclass 14, count 0 2006.202.00:10:12.28#ibcon#about to read 3, iclass 14, count 0 2006.202.00:10:12.32#ibcon#read 3, iclass 14, count 0 2006.202.00:10:12.32#ibcon#about to read 4, iclass 14, count 0 2006.202.00:10:12.32#ibcon#read 4, iclass 14, count 0 2006.202.00:10:12.32#ibcon#about to read 5, iclass 14, count 0 2006.202.00:10:12.32#ibcon#read 5, iclass 14, count 0 2006.202.00:10:12.32#ibcon#about to read 6, iclass 14, count 0 2006.202.00:10:12.32#ibcon#read 6, iclass 14, count 0 2006.202.00:10:12.32#ibcon#end of sib2, iclass 14, count 0 2006.202.00:10:12.32#ibcon#*after write, iclass 14, count 0 2006.202.00:10:12.32#ibcon#*before return 0, iclass 14, count 0 2006.202.00:10:12.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:12.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:10:12.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.00:10:12.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.00:10:12.32$vck44/vb=2,5 2006.202.00:10:12.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.00:10:12.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.00:10:12.32#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:12.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:12.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:12.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:12.38#ibcon#enter wrdev, iclass 16, count 2 2006.202.00:10:12.38#ibcon#first serial, iclass 16, count 2 2006.202.00:10:12.38#ibcon#enter sib2, iclass 16, count 2 2006.202.00:10:12.38#ibcon#flushed, iclass 16, count 2 2006.202.00:10:12.38#ibcon#about to write, iclass 16, count 2 2006.202.00:10:12.38#ibcon#wrote, iclass 16, count 2 2006.202.00:10:12.38#ibcon#about to read 3, iclass 16, count 2 2006.202.00:10:12.40#ibcon#read 3, iclass 16, count 2 2006.202.00:10:12.40#ibcon#about to read 4, iclass 16, count 2 2006.202.00:10:12.40#ibcon#read 4, iclass 16, count 2 2006.202.00:10:12.40#ibcon#about to read 5, iclass 16, count 2 2006.202.00:10:12.40#ibcon#read 5, iclass 16, count 2 2006.202.00:10:12.40#ibcon#about to read 6, iclass 16, count 2 2006.202.00:10:12.40#ibcon#read 6, iclass 16, count 2 2006.202.00:10:12.40#ibcon#end of sib2, iclass 16, count 2 2006.202.00:10:12.40#ibcon#*mode == 0, iclass 16, count 2 2006.202.00:10:12.40#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.00:10:12.40#ibcon#[27=AT02-05\r\n] 2006.202.00:10:12.40#ibcon#*before write, iclass 16, count 2 2006.202.00:10:12.40#ibcon#enter sib2, iclass 16, count 2 2006.202.00:10:12.40#ibcon#flushed, iclass 16, count 2 2006.202.00:10:12.40#ibcon#about to write, iclass 16, count 2 2006.202.00:10:12.40#ibcon#wrote, iclass 16, count 2 2006.202.00:10:12.40#ibcon#about to read 3, iclass 16, count 2 2006.202.00:10:12.43#ibcon#read 3, iclass 16, count 2 2006.202.00:10:12.43#ibcon#about to read 4, iclass 16, count 2 2006.202.00:10:12.43#ibcon#read 4, iclass 16, count 2 2006.202.00:10:12.43#ibcon#about to read 5, iclass 16, count 2 2006.202.00:10:12.43#ibcon#read 5, iclass 16, count 2 2006.202.00:10:12.43#ibcon#about to read 6, iclass 16, count 2 2006.202.00:10:12.43#ibcon#read 6, iclass 16, count 2 2006.202.00:10:12.43#ibcon#end of sib2, iclass 16, count 2 2006.202.00:10:12.43#ibcon#*after write, iclass 16, count 2 2006.202.00:10:12.43#ibcon#*before return 0, iclass 16, count 2 2006.202.00:10:12.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:12.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:10:12.57#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.00:10:12.57#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:12.57#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:12.69#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:12.69#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:12.69#ibcon#enter wrdev, iclass 16, count 0 2006.202.00:10:12.69#ibcon#first serial, iclass 16, count 0 2006.202.00:10:12.69#ibcon#enter sib2, iclass 16, count 0 2006.202.00:10:12.69#ibcon#flushed, iclass 16, count 0 2006.202.00:10:12.69#ibcon#about to write, iclass 16, count 0 2006.202.00:10:12.69#ibcon#wrote, iclass 16, count 0 2006.202.00:10:12.69#ibcon#about to read 3, iclass 16, count 0 2006.202.00:10:12.71#ibcon#read 3, iclass 16, count 0 2006.202.00:10:12.71#ibcon#about to read 4, iclass 16, count 0 2006.202.00:10:12.71#ibcon#read 4, iclass 16, count 0 2006.202.00:10:12.71#ibcon#about to read 5, iclass 16, count 0 2006.202.00:10:12.71#ibcon#read 5, iclass 16, count 0 2006.202.00:10:12.71#ibcon#about to read 6, iclass 16, count 0 2006.202.00:10:12.71#ibcon#read 6, iclass 16, count 0 2006.202.00:10:12.71#ibcon#end of sib2, iclass 16, count 0 2006.202.00:10:12.71#ibcon#*mode == 0, iclass 16, count 0 2006.202.00:10:12.71#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.00:10:12.71#ibcon#[27=USB\r\n] 2006.202.00:10:12.71#ibcon#*before write, iclass 16, count 0 2006.202.00:10:12.71#ibcon#enter sib2, iclass 16, count 0 2006.202.00:10:12.71#ibcon#flushed, iclass 16, count 0 2006.202.00:10:12.71#ibcon#about to write, iclass 16, count 0 2006.202.00:10:12.71#ibcon#wrote, iclass 16, count 0 2006.202.00:10:12.71#ibcon#about to read 3, iclass 16, count 0 2006.202.00:10:12.74#ibcon#read 3, iclass 16, count 0 2006.202.00:10:12.74#ibcon#about to read 4, iclass 16, count 0 2006.202.00:10:12.74#ibcon#read 4, iclass 16, count 0 2006.202.00:10:12.74#ibcon#about to read 5, iclass 16, count 0 2006.202.00:10:12.74#ibcon#read 5, iclass 16, count 0 2006.202.00:10:12.74#ibcon#about to read 6, iclass 16, count 0 2006.202.00:10:12.74#ibcon#read 6, iclass 16, count 0 2006.202.00:10:12.74#ibcon#end of sib2, iclass 16, count 0 2006.202.00:10:12.74#ibcon#*after write, iclass 16, count 0 2006.202.00:10:12.74#ibcon#*before return 0, iclass 16, count 0 2006.202.00:10:12.74#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:12.74#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:10:12.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.00:10:12.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.00:10:12.74$vck44/vblo=3,649.99 2006.202.00:10:12.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.00:10:12.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.00:10:12.74#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:12.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:12.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:12.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:12.74#ibcon#enter wrdev, iclass 18, count 0 2006.202.00:10:12.74#ibcon#first serial, iclass 18, count 0 2006.202.00:10:12.74#ibcon#enter sib2, iclass 18, count 0 2006.202.00:10:12.74#ibcon#flushed, iclass 18, count 0 2006.202.00:10:12.74#ibcon#about to write, iclass 18, count 0 2006.202.00:10:12.74#ibcon#wrote, iclass 18, count 0 2006.202.00:10:12.74#ibcon#about to read 3, iclass 18, count 0 2006.202.00:10:12.76#ibcon#read 3, iclass 18, count 0 2006.202.00:10:12.76#ibcon#about to read 4, iclass 18, count 0 2006.202.00:10:12.76#ibcon#read 4, iclass 18, count 0 2006.202.00:10:12.76#ibcon#about to read 5, iclass 18, count 0 2006.202.00:10:12.76#ibcon#read 5, iclass 18, count 0 2006.202.00:10:12.76#ibcon#about to read 6, iclass 18, count 0 2006.202.00:10:12.76#ibcon#read 6, iclass 18, count 0 2006.202.00:10:12.76#ibcon#end of sib2, iclass 18, count 0 2006.202.00:10:12.76#ibcon#*mode == 0, iclass 18, count 0 2006.202.00:10:12.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.00:10:12.76#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.00:10:12.76#ibcon#*before write, iclass 18, count 0 2006.202.00:10:12.76#ibcon#enter sib2, iclass 18, count 0 2006.202.00:10:12.76#ibcon#flushed, iclass 18, count 0 2006.202.00:10:12.76#ibcon#about to write, iclass 18, count 0 2006.202.00:10:12.76#ibcon#wrote, iclass 18, count 0 2006.202.00:10:12.76#ibcon#about to read 3, iclass 18, count 0 2006.202.00:10:12.80#ibcon#read 3, iclass 18, count 0 2006.202.00:10:12.80#ibcon#about to read 4, iclass 18, count 0 2006.202.00:10:12.80#ibcon#read 4, iclass 18, count 0 2006.202.00:10:12.80#ibcon#about to read 5, iclass 18, count 0 2006.202.00:10:12.80#ibcon#read 5, iclass 18, count 0 2006.202.00:10:12.80#ibcon#about to read 6, iclass 18, count 0 2006.202.00:10:12.80#ibcon#read 6, iclass 18, count 0 2006.202.00:10:12.80#ibcon#end of sib2, iclass 18, count 0 2006.202.00:10:12.80#ibcon#*after write, iclass 18, count 0 2006.202.00:10:12.80#ibcon#*before return 0, iclass 18, count 0 2006.202.00:10:12.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:12.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:10:12.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.00:10:12.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.00:10:12.80$vck44/vb=3,4 2006.202.00:10:12.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.00:10:12.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.00:10:12.80#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:12.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:12.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:12.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:12.86#ibcon#enter wrdev, iclass 20, count 2 2006.202.00:10:12.86#ibcon#first serial, iclass 20, count 2 2006.202.00:10:12.86#ibcon#enter sib2, iclass 20, count 2 2006.202.00:10:12.86#ibcon#flushed, iclass 20, count 2 2006.202.00:10:12.86#ibcon#about to write, iclass 20, count 2 2006.202.00:10:12.86#ibcon#wrote, iclass 20, count 2 2006.202.00:10:12.86#ibcon#about to read 3, iclass 20, count 2 2006.202.00:10:12.88#ibcon#read 3, iclass 20, count 2 2006.202.00:10:12.88#ibcon#about to read 4, iclass 20, count 2 2006.202.00:10:12.88#ibcon#read 4, iclass 20, count 2 2006.202.00:10:12.88#ibcon#about to read 5, iclass 20, count 2 2006.202.00:10:12.88#ibcon#read 5, iclass 20, count 2 2006.202.00:10:12.88#ibcon#about to read 6, iclass 20, count 2 2006.202.00:10:12.88#ibcon#read 6, iclass 20, count 2 2006.202.00:10:12.88#ibcon#end of sib2, iclass 20, count 2 2006.202.00:10:12.88#ibcon#*mode == 0, iclass 20, count 2 2006.202.00:10:12.88#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.00:10:12.88#ibcon#[27=AT03-04\r\n] 2006.202.00:10:12.88#ibcon#*before write, iclass 20, count 2 2006.202.00:10:12.88#ibcon#enter sib2, iclass 20, count 2 2006.202.00:10:12.88#ibcon#flushed, iclass 20, count 2 2006.202.00:10:12.88#ibcon#about to write, iclass 20, count 2 2006.202.00:10:12.88#ibcon#wrote, iclass 20, count 2 2006.202.00:10:12.88#ibcon#about to read 3, iclass 20, count 2 2006.202.00:10:12.91#ibcon#read 3, iclass 20, count 2 2006.202.00:10:12.91#ibcon#about to read 4, iclass 20, count 2 2006.202.00:10:12.91#ibcon#read 4, iclass 20, count 2 2006.202.00:10:12.91#ibcon#about to read 5, iclass 20, count 2 2006.202.00:10:12.91#ibcon#read 5, iclass 20, count 2 2006.202.00:10:12.91#ibcon#about to read 6, iclass 20, count 2 2006.202.00:10:12.91#ibcon#read 6, iclass 20, count 2 2006.202.00:10:12.91#ibcon#end of sib2, iclass 20, count 2 2006.202.00:10:12.91#ibcon#*after write, iclass 20, count 2 2006.202.00:10:12.91#ibcon#*before return 0, iclass 20, count 2 2006.202.00:10:12.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:12.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:10:12.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.00:10:12.91#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:12.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:13.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:13.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:13.03#ibcon#enter wrdev, iclass 20, count 0 2006.202.00:10:13.03#ibcon#first serial, iclass 20, count 0 2006.202.00:10:13.03#ibcon#enter sib2, iclass 20, count 0 2006.202.00:10:13.03#ibcon#flushed, iclass 20, count 0 2006.202.00:10:13.03#ibcon#about to write, iclass 20, count 0 2006.202.00:10:13.03#ibcon#wrote, iclass 20, count 0 2006.202.00:10:13.03#ibcon#about to read 3, iclass 20, count 0 2006.202.00:10:13.05#ibcon#read 3, iclass 20, count 0 2006.202.00:10:13.05#ibcon#about to read 4, iclass 20, count 0 2006.202.00:10:13.05#ibcon#read 4, iclass 20, count 0 2006.202.00:10:13.05#ibcon#about to read 5, iclass 20, count 0 2006.202.00:10:13.05#ibcon#read 5, iclass 20, count 0 2006.202.00:10:13.05#ibcon#about to read 6, iclass 20, count 0 2006.202.00:10:13.05#ibcon#read 6, iclass 20, count 0 2006.202.00:10:13.05#ibcon#end of sib2, iclass 20, count 0 2006.202.00:10:13.05#ibcon#*mode == 0, iclass 20, count 0 2006.202.00:10:13.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.00:10:13.05#ibcon#[27=USB\r\n] 2006.202.00:10:13.05#ibcon#*before write, iclass 20, count 0 2006.202.00:10:13.05#ibcon#enter sib2, iclass 20, count 0 2006.202.00:10:13.05#ibcon#flushed, iclass 20, count 0 2006.202.00:10:13.05#ibcon#about to write, iclass 20, count 0 2006.202.00:10:13.05#ibcon#wrote, iclass 20, count 0 2006.202.00:10:13.05#ibcon#about to read 3, iclass 20, count 0 2006.202.00:10:13.08#ibcon#read 3, iclass 20, count 0 2006.202.00:10:13.08#ibcon#about to read 4, iclass 20, count 0 2006.202.00:10:13.08#ibcon#read 4, iclass 20, count 0 2006.202.00:10:13.08#ibcon#about to read 5, iclass 20, count 0 2006.202.00:10:13.08#ibcon#read 5, iclass 20, count 0 2006.202.00:10:13.08#ibcon#about to read 6, iclass 20, count 0 2006.202.00:10:13.08#ibcon#read 6, iclass 20, count 0 2006.202.00:10:13.08#ibcon#end of sib2, iclass 20, count 0 2006.202.00:10:13.08#ibcon#*after write, iclass 20, count 0 2006.202.00:10:13.08#ibcon#*before return 0, iclass 20, count 0 2006.202.00:10:13.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:13.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:10:13.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.00:10:13.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.00:10:13.08$vck44/vblo=4,679.99 2006.202.00:10:13.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.00:10:13.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.00:10:13.08#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:13.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:13.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:13.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:13.08#ibcon#enter wrdev, iclass 22, count 0 2006.202.00:10:13.08#ibcon#first serial, iclass 22, count 0 2006.202.00:10:13.08#ibcon#enter sib2, iclass 22, count 0 2006.202.00:10:13.08#ibcon#flushed, iclass 22, count 0 2006.202.00:10:13.08#ibcon#about to write, iclass 22, count 0 2006.202.00:10:13.08#ibcon#wrote, iclass 22, count 0 2006.202.00:10:13.08#ibcon#about to read 3, iclass 22, count 0 2006.202.00:10:13.10#ibcon#read 3, iclass 22, count 0 2006.202.00:10:13.10#ibcon#about to read 4, iclass 22, count 0 2006.202.00:10:13.10#ibcon#read 4, iclass 22, count 0 2006.202.00:10:13.10#ibcon#about to read 5, iclass 22, count 0 2006.202.00:10:13.10#ibcon#read 5, iclass 22, count 0 2006.202.00:10:13.10#ibcon#about to read 6, iclass 22, count 0 2006.202.00:10:13.10#ibcon#read 6, iclass 22, count 0 2006.202.00:10:13.10#ibcon#end of sib2, iclass 22, count 0 2006.202.00:10:13.10#ibcon#*mode == 0, iclass 22, count 0 2006.202.00:10:13.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.00:10:13.10#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.00:10:13.10#ibcon#*before write, iclass 22, count 0 2006.202.00:10:13.10#ibcon#enter sib2, iclass 22, count 0 2006.202.00:10:13.10#ibcon#flushed, iclass 22, count 0 2006.202.00:10:13.10#ibcon#about to write, iclass 22, count 0 2006.202.00:10:13.10#ibcon#wrote, iclass 22, count 0 2006.202.00:10:13.10#ibcon#about to read 3, iclass 22, count 0 2006.202.00:10:13.14#ibcon#read 3, iclass 22, count 0 2006.202.00:10:13.14#ibcon#about to read 4, iclass 22, count 0 2006.202.00:10:13.14#ibcon#read 4, iclass 22, count 0 2006.202.00:10:13.14#ibcon#about to read 5, iclass 22, count 0 2006.202.00:10:13.14#ibcon#read 5, iclass 22, count 0 2006.202.00:10:13.14#ibcon#about to read 6, iclass 22, count 0 2006.202.00:10:13.14#ibcon#read 6, iclass 22, count 0 2006.202.00:10:13.14#ibcon#end of sib2, iclass 22, count 0 2006.202.00:10:13.14#ibcon#*after write, iclass 22, count 0 2006.202.00:10:13.14#ibcon#*before return 0, iclass 22, count 0 2006.202.00:10:13.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:13.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:10:13.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.00:10:13.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.00:10:13.14$vck44/vb=4,5 2006.202.00:10:13.14#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.00:10:13.14#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.00:10:13.14#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:13.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:13.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:13.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:13.20#ibcon#enter wrdev, iclass 24, count 2 2006.202.00:10:13.20#ibcon#first serial, iclass 24, count 2 2006.202.00:10:13.20#ibcon#enter sib2, iclass 24, count 2 2006.202.00:10:13.20#ibcon#flushed, iclass 24, count 2 2006.202.00:10:13.20#ibcon#about to write, iclass 24, count 2 2006.202.00:10:13.20#ibcon#wrote, iclass 24, count 2 2006.202.00:10:13.20#ibcon#about to read 3, iclass 24, count 2 2006.202.00:10:13.22#ibcon#read 3, iclass 24, count 2 2006.202.00:10:13.22#ibcon#about to read 4, iclass 24, count 2 2006.202.00:10:13.22#ibcon#read 4, iclass 24, count 2 2006.202.00:10:13.22#ibcon#about to read 5, iclass 24, count 2 2006.202.00:10:13.22#ibcon#read 5, iclass 24, count 2 2006.202.00:10:13.22#ibcon#about to read 6, iclass 24, count 2 2006.202.00:10:13.22#ibcon#read 6, iclass 24, count 2 2006.202.00:10:13.22#ibcon#end of sib2, iclass 24, count 2 2006.202.00:10:13.22#ibcon#*mode == 0, iclass 24, count 2 2006.202.00:10:13.22#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.00:10:13.22#ibcon#[27=AT04-05\r\n] 2006.202.00:10:13.22#ibcon#*before write, iclass 24, count 2 2006.202.00:10:13.22#ibcon#enter sib2, iclass 24, count 2 2006.202.00:10:13.22#ibcon#flushed, iclass 24, count 2 2006.202.00:10:13.22#ibcon#about to write, iclass 24, count 2 2006.202.00:10:13.22#ibcon#wrote, iclass 24, count 2 2006.202.00:10:13.22#ibcon#about to read 3, iclass 24, count 2 2006.202.00:10:13.25#ibcon#read 3, iclass 24, count 2 2006.202.00:10:13.25#ibcon#about to read 4, iclass 24, count 2 2006.202.00:10:13.25#ibcon#read 4, iclass 24, count 2 2006.202.00:10:13.25#ibcon#about to read 5, iclass 24, count 2 2006.202.00:10:13.25#ibcon#read 5, iclass 24, count 2 2006.202.00:10:13.25#ibcon#about to read 6, iclass 24, count 2 2006.202.00:10:13.25#ibcon#read 6, iclass 24, count 2 2006.202.00:10:13.25#ibcon#end of sib2, iclass 24, count 2 2006.202.00:10:13.25#ibcon#*after write, iclass 24, count 2 2006.202.00:10:13.25#ibcon#*before return 0, iclass 24, count 2 2006.202.00:10:13.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:13.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:10:13.25#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.00:10:13.25#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:13.25#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:13.37#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:13.37#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:13.37#ibcon#enter wrdev, iclass 24, count 0 2006.202.00:10:13.37#ibcon#first serial, iclass 24, count 0 2006.202.00:10:13.37#ibcon#enter sib2, iclass 24, count 0 2006.202.00:10:13.37#ibcon#flushed, iclass 24, count 0 2006.202.00:10:13.37#ibcon#about to write, iclass 24, count 0 2006.202.00:10:13.37#ibcon#wrote, iclass 24, count 0 2006.202.00:10:13.37#ibcon#about to read 3, iclass 24, count 0 2006.202.00:10:13.39#ibcon#read 3, iclass 24, count 0 2006.202.00:10:13.39#ibcon#about to read 4, iclass 24, count 0 2006.202.00:10:13.39#ibcon#read 4, iclass 24, count 0 2006.202.00:10:13.39#ibcon#about to read 5, iclass 24, count 0 2006.202.00:10:13.39#ibcon#read 5, iclass 24, count 0 2006.202.00:10:13.39#ibcon#about to read 6, iclass 24, count 0 2006.202.00:10:13.39#ibcon#read 6, iclass 24, count 0 2006.202.00:10:13.39#ibcon#end of sib2, iclass 24, count 0 2006.202.00:10:13.39#ibcon#*mode == 0, iclass 24, count 0 2006.202.00:10:13.39#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.00:10:13.39#ibcon#[27=USB\r\n] 2006.202.00:10:13.39#ibcon#*before write, iclass 24, count 0 2006.202.00:10:13.39#ibcon#enter sib2, iclass 24, count 0 2006.202.00:10:13.39#ibcon#flushed, iclass 24, count 0 2006.202.00:10:13.39#ibcon#about to write, iclass 24, count 0 2006.202.00:10:13.39#ibcon#wrote, iclass 24, count 0 2006.202.00:10:13.39#ibcon#about to read 3, iclass 24, count 0 2006.202.00:10:13.42#ibcon#read 3, iclass 24, count 0 2006.202.00:10:13.42#ibcon#about to read 4, iclass 24, count 0 2006.202.00:10:13.42#ibcon#read 4, iclass 24, count 0 2006.202.00:10:13.42#ibcon#about to read 5, iclass 24, count 0 2006.202.00:10:13.42#ibcon#read 5, iclass 24, count 0 2006.202.00:10:13.42#ibcon#about to read 6, iclass 24, count 0 2006.202.00:10:13.42#ibcon#read 6, iclass 24, count 0 2006.202.00:10:13.42#ibcon#end of sib2, iclass 24, count 0 2006.202.00:10:13.42#ibcon#*after write, iclass 24, count 0 2006.202.00:10:13.42#ibcon#*before return 0, iclass 24, count 0 2006.202.00:10:13.42#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:13.42#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:10:13.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.00:10:13.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.00:10:13.42$vck44/vblo=5,709.99 2006.202.00:10:13.42#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.00:10:13.42#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.00:10:13.42#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:13.42#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:13.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:13.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:13.42#ibcon#enter wrdev, iclass 26, count 0 2006.202.00:10:13.42#ibcon#first serial, iclass 26, count 0 2006.202.00:10:13.42#ibcon#enter sib2, iclass 26, count 0 2006.202.00:10:13.42#ibcon#flushed, iclass 26, count 0 2006.202.00:10:13.42#ibcon#about to write, iclass 26, count 0 2006.202.00:10:13.42#ibcon#wrote, iclass 26, count 0 2006.202.00:10:13.42#ibcon#about to read 3, iclass 26, count 0 2006.202.00:10:13.44#ibcon#read 3, iclass 26, count 0 2006.202.00:10:13.44#ibcon#about to read 4, iclass 26, count 0 2006.202.00:10:13.44#ibcon#read 4, iclass 26, count 0 2006.202.00:10:13.44#ibcon#about to read 5, iclass 26, count 0 2006.202.00:10:13.44#ibcon#read 5, iclass 26, count 0 2006.202.00:10:13.44#ibcon#about to read 6, iclass 26, count 0 2006.202.00:10:13.44#ibcon#read 6, iclass 26, count 0 2006.202.00:10:13.44#ibcon#end of sib2, iclass 26, count 0 2006.202.00:10:13.44#ibcon#*mode == 0, iclass 26, count 0 2006.202.00:10:13.44#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.00:10:13.44#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.00:10:13.44#ibcon#*before write, iclass 26, count 0 2006.202.00:10:13.44#ibcon#enter sib2, iclass 26, count 0 2006.202.00:10:13.44#ibcon#flushed, iclass 26, count 0 2006.202.00:10:13.44#ibcon#about to write, iclass 26, count 0 2006.202.00:10:13.44#ibcon#wrote, iclass 26, count 0 2006.202.00:10:13.44#ibcon#about to read 3, iclass 26, count 0 2006.202.00:10:13.48#ibcon#read 3, iclass 26, count 0 2006.202.00:10:13.48#ibcon#about to read 4, iclass 26, count 0 2006.202.00:10:13.48#ibcon#read 4, iclass 26, count 0 2006.202.00:10:13.48#ibcon#about to read 5, iclass 26, count 0 2006.202.00:10:13.48#ibcon#read 5, iclass 26, count 0 2006.202.00:10:13.48#ibcon#about to read 6, iclass 26, count 0 2006.202.00:10:13.48#ibcon#read 6, iclass 26, count 0 2006.202.00:10:13.48#ibcon#end of sib2, iclass 26, count 0 2006.202.00:10:13.48#ibcon#*after write, iclass 26, count 0 2006.202.00:10:13.48#ibcon#*before return 0, iclass 26, count 0 2006.202.00:10:13.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:13.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:10:13.48#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.00:10:13.48#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.00:10:13.48$vck44/vb=5,4 2006.202.00:10:13.48#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.00:10:13.48#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.00:10:13.48#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:13.48#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:13.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:13.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:13.54#ibcon#enter wrdev, iclass 28, count 2 2006.202.00:10:13.54#ibcon#first serial, iclass 28, count 2 2006.202.00:10:13.54#ibcon#enter sib2, iclass 28, count 2 2006.202.00:10:13.54#ibcon#flushed, iclass 28, count 2 2006.202.00:10:13.54#ibcon#about to write, iclass 28, count 2 2006.202.00:10:13.54#ibcon#wrote, iclass 28, count 2 2006.202.00:10:13.54#ibcon#about to read 3, iclass 28, count 2 2006.202.00:10:13.56#ibcon#read 3, iclass 28, count 2 2006.202.00:10:13.56#ibcon#about to read 4, iclass 28, count 2 2006.202.00:10:13.56#ibcon#read 4, iclass 28, count 2 2006.202.00:10:13.56#ibcon#about to read 5, iclass 28, count 2 2006.202.00:10:13.56#ibcon#read 5, iclass 28, count 2 2006.202.00:10:13.56#ibcon#about to read 6, iclass 28, count 2 2006.202.00:10:13.56#ibcon#read 6, iclass 28, count 2 2006.202.00:10:13.56#ibcon#end of sib2, iclass 28, count 2 2006.202.00:10:13.56#ibcon#*mode == 0, iclass 28, count 2 2006.202.00:10:13.56#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.00:10:13.56#ibcon#[27=AT05-04\r\n] 2006.202.00:10:13.56#ibcon#*before write, iclass 28, count 2 2006.202.00:10:13.56#ibcon#enter sib2, iclass 28, count 2 2006.202.00:10:13.56#ibcon#flushed, iclass 28, count 2 2006.202.00:10:13.56#ibcon#about to write, iclass 28, count 2 2006.202.00:10:13.56#ibcon#wrote, iclass 28, count 2 2006.202.00:10:13.56#ibcon#about to read 3, iclass 28, count 2 2006.202.00:10:13.64#ibcon#read 3, iclass 28, count 2 2006.202.00:10:13.57#abcon#<5=/03 1.1 2.1 20.441001001.4\r\n> 2006.202.00:10:13.64#ibcon#about to read 4, iclass 28, count 2 2006.202.00:10:13.64#ibcon#read 4, iclass 28, count 2 2006.202.00:10:13.64#ibcon#about to read 5, iclass 28, count 2 2006.202.00:10:13.64#ibcon#read 5, iclass 28, count 2 2006.202.00:10:13.64#ibcon#about to read 6, iclass 28, count 2 2006.202.00:10:13.64#ibcon#read 6, iclass 28, count 2 2006.202.00:10:13.64#ibcon#end of sib2, iclass 28, count 2 2006.202.00:10:13.64#ibcon#*after write, iclass 28, count 2 2006.202.00:10:13.65#ibcon#*before return 0, iclass 28, count 2 2006.202.00:10:13.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:13.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:10:13.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.00:10:13.65#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:13.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:13.67#abcon#{5=INTERFACE CLEAR} 2006.202.00:10:13.73#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:10:13.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:13.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:13.77#ibcon#enter wrdev, iclass 28, count 0 2006.202.00:10:13.77#ibcon#first serial, iclass 28, count 0 2006.202.00:10:13.77#ibcon#enter sib2, iclass 28, count 0 2006.202.00:10:13.77#ibcon#flushed, iclass 28, count 0 2006.202.00:10:13.77#ibcon#about to write, iclass 28, count 0 2006.202.00:10:13.77#ibcon#wrote, iclass 28, count 0 2006.202.00:10:13.77#ibcon#about to read 3, iclass 28, count 0 2006.202.00:10:13.79#ibcon#read 3, iclass 28, count 0 2006.202.00:10:13.79#ibcon#about to read 4, iclass 28, count 0 2006.202.00:10:13.79#ibcon#read 4, iclass 28, count 0 2006.202.00:10:13.79#ibcon#about to read 5, iclass 28, count 0 2006.202.00:10:13.79#ibcon#read 5, iclass 28, count 0 2006.202.00:10:13.79#ibcon#about to read 6, iclass 28, count 0 2006.202.00:10:13.79#ibcon#read 6, iclass 28, count 0 2006.202.00:10:13.79#ibcon#end of sib2, iclass 28, count 0 2006.202.00:10:13.79#ibcon#*mode == 0, iclass 28, count 0 2006.202.00:10:13.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.00:10:13.79#ibcon#[27=USB\r\n] 2006.202.00:10:13.79#ibcon#*before write, iclass 28, count 0 2006.202.00:10:13.79#ibcon#enter sib2, iclass 28, count 0 2006.202.00:10:13.79#ibcon#flushed, iclass 28, count 0 2006.202.00:10:13.79#ibcon#about to write, iclass 28, count 0 2006.202.00:10:13.79#ibcon#wrote, iclass 28, count 0 2006.202.00:10:13.79#ibcon#about to read 3, iclass 28, count 0 2006.202.00:10:13.82#ibcon#read 3, iclass 28, count 0 2006.202.00:10:13.82#ibcon#about to read 4, iclass 28, count 0 2006.202.00:10:13.82#ibcon#read 4, iclass 28, count 0 2006.202.00:10:13.82#ibcon#about to read 5, iclass 28, count 0 2006.202.00:10:13.82#ibcon#read 5, iclass 28, count 0 2006.202.00:10:13.82#ibcon#about to read 6, iclass 28, count 0 2006.202.00:10:13.82#ibcon#read 6, iclass 28, count 0 2006.202.00:10:13.82#ibcon#end of sib2, iclass 28, count 0 2006.202.00:10:13.82#ibcon#*after write, iclass 28, count 0 2006.202.00:10:13.82#ibcon#*before return 0, iclass 28, count 0 2006.202.00:10:13.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:13.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:10:13.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.00:10:13.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.00:10:13.82$vck44/vblo=6,719.99 2006.202.00:10:13.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.00:10:13.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.00:10:13.82#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:13.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:13.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:13.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:13.82#ibcon#enter wrdev, iclass 34, count 0 2006.202.00:10:13.82#ibcon#first serial, iclass 34, count 0 2006.202.00:10:13.82#ibcon#enter sib2, iclass 34, count 0 2006.202.00:10:13.82#ibcon#flushed, iclass 34, count 0 2006.202.00:10:13.82#ibcon#about to write, iclass 34, count 0 2006.202.00:10:13.82#ibcon#wrote, iclass 34, count 0 2006.202.00:10:13.82#ibcon#about to read 3, iclass 34, count 0 2006.202.00:10:13.84#ibcon#read 3, iclass 34, count 0 2006.202.00:10:13.84#ibcon#about to read 4, iclass 34, count 0 2006.202.00:10:13.84#ibcon#read 4, iclass 34, count 0 2006.202.00:10:13.84#ibcon#about to read 5, iclass 34, count 0 2006.202.00:10:13.84#ibcon#read 5, iclass 34, count 0 2006.202.00:10:13.84#ibcon#about to read 6, iclass 34, count 0 2006.202.00:10:13.84#ibcon#read 6, iclass 34, count 0 2006.202.00:10:13.84#ibcon#end of sib2, iclass 34, count 0 2006.202.00:10:13.84#ibcon#*mode == 0, iclass 34, count 0 2006.202.00:10:13.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.00:10:13.84#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.00:10:13.84#ibcon#*before write, iclass 34, count 0 2006.202.00:10:13.84#ibcon#enter sib2, iclass 34, count 0 2006.202.00:10:13.84#ibcon#flushed, iclass 34, count 0 2006.202.00:10:13.84#ibcon#about to write, iclass 34, count 0 2006.202.00:10:13.84#ibcon#wrote, iclass 34, count 0 2006.202.00:10:13.84#ibcon#about to read 3, iclass 34, count 0 2006.202.00:10:13.88#ibcon#read 3, iclass 34, count 0 2006.202.00:10:13.88#ibcon#about to read 4, iclass 34, count 0 2006.202.00:10:13.88#ibcon#read 4, iclass 34, count 0 2006.202.00:10:13.88#ibcon#about to read 5, iclass 34, count 0 2006.202.00:10:13.88#ibcon#read 5, iclass 34, count 0 2006.202.00:10:13.88#ibcon#about to read 6, iclass 34, count 0 2006.202.00:10:13.88#ibcon#read 6, iclass 34, count 0 2006.202.00:10:13.88#ibcon#end of sib2, iclass 34, count 0 2006.202.00:10:13.88#ibcon#*after write, iclass 34, count 0 2006.202.00:10:13.88#ibcon#*before return 0, iclass 34, count 0 2006.202.00:10:13.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:13.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:10:13.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.00:10:13.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.00:10:13.88$vck44/vb=6,4 2006.202.00:10:13.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.00:10:13.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.00:10:13.88#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:13.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:13.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:13.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:13.94#ibcon#enter wrdev, iclass 36, count 2 2006.202.00:10:13.94#ibcon#first serial, iclass 36, count 2 2006.202.00:10:13.94#ibcon#enter sib2, iclass 36, count 2 2006.202.00:10:13.94#ibcon#flushed, iclass 36, count 2 2006.202.00:10:13.94#ibcon#about to write, iclass 36, count 2 2006.202.00:10:13.94#ibcon#wrote, iclass 36, count 2 2006.202.00:10:13.94#ibcon#about to read 3, iclass 36, count 2 2006.202.00:10:13.96#ibcon#read 3, iclass 36, count 2 2006.202.00:10:13.96#ibcon#about to read 4, iclass 36, count 2 2006.202.00:10:13.96#ibcon#read 4, iclass 36, count 2 2006.202.00:10:13.96#ibcon#about to read 5, iclass 36, count 2 2006.202.00:10:13.96#ibcon#read 5, iclass 36, count 2 2006.202.00:10:13.96#ibcon#about to read 6, iclass 36, count 2 2006.202.00:10:13.96#ibcon#read 6, iclass 36, count 2 2006.202.00:10:13.96#ibcon#end of sib2, iclass 36, count 2 2006.202.00:10:13.96#ibcon#*mode == 0, iclass 36, count 2 2006.202.00:10:13.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.00:10:13.96#ibcon#[27=AT06-04\r\n] 2006.202.00:10:13.96#ibcon#*before write, iclass 36, count 2 2006.202.00:10:13.96#ibcon#enter sib2, iclass 36, count 2 2006.202.00:10:13.96#ibcon#flushed, iclass 36, count 2 2006.202.00:10:13.96#ibcon#about to write, iclass 36, count 2 2006.202.00:10:13.96#ibcon#wrote, iclass 36, count 2 2006.202.00:10:13.96#ibcon#about to read 3, iclass 36, count 2 2006.202.00:10:13.99#ibcon#read 3, iclass 36, count 2 2006.202.00:10:13.99#ibcon#about to read 4, iclass 36, count 2 2006.202.00:10:13.99#ibcon#read 4, iclass 36, count 2 2006.202.00:10:13.99#ibcon#about to read 5, iclass 36, count 2 2006.202.00:10:13.99#ibcon#read 5, iclass 36, count 2 2006.202.00:10:13.99#ibcon#about to read 6, iclass 36, count 2 2006.202.00:10:13.99#ibcon#read 6, iclass 36, count 2 2006.202.00:10:13.99#ibcon#end of sib2, iclass 36, count 2 2006.202.00:10:13.99#ibcon#*after write, iclass 36, count 2 2006.202.00:10:13.99#ibcon#*before return 0, iclass 36, count 2 2006.202.00:10:13.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:13.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:10:13.99#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.00:10:13.99#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:13.99#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:14.11#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:14.11#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:14.11#ibcon#enter wrdev, iclass 36, count 0 2006.202.00:10:14.11#ibcon#first serial, iclass 36, count 0 2006.202.00:10:14.11#ibcon#enter sib2, iclass 36, count 0 2006.202.00:10:14.11#ibcon#flushed, iclass 36, count 0 2006.202.00:10:14.11#ibcon#about to write, iclass 36, count 0 2006.202.00:10:14.11#ibcon#wrote, iclass 36, count 0 2006.202.00:10:14.11#ibcon#about to read 3, iclass 36, count 0 2006.202.00:10:14.13#ibcon#read 3, iclass 36, count 0 2006.202.00:10:14.13#ibcon#about to read 4, iclass 36, count 0 2006.202.00:10:14.13#ibcon#read 4, iclass 36, count 0 2006.202.00:10:14.13#ibcon#about to read 5, iclass 36, count 0 2006.202.00:10:14.13#ibcon#read 5, iclass 36, count 0 2006.202.00:10:14.13#ibcon#about to read 6, iclass 36, count 0 2006.202.00:10:14.13#ibcon#read 6, iclass 36, count 0 2006.202.00:10:14.13#ibcon#end of sib2, iclass 36, count 0 2006.202.00:10:14.13#ibcon#*mode == 0, iclass 36, count 0 2006.202.00:10:14.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.00:10:14.13#ibcon#[27=USB\r\n] 2006.202.00:10:14.13#ibcon#*before write, iclass 36, count 0 2006.202.00:10:14.13#ibcon#enter sib2, iclass 36, count 0 2006.202.00:10:14.13#ibcon#flushed, iclass 36, count 0 2006.202.00:10:14.13#ibcon#about to write, iclass 36, count 0 2006.202.00:10:14.13#ibcon#wrote, iclass 36, count 0 2006.202.00:10:14.13#ibcon#about to read 3, iclass 36, count 0 2006.202.00:10:14.16#ibcon#read 3, iclass 36, count 0 2006.202.00:10:14.16#ibcon#about to read 4, iclass 36, count 0 2006.202.00:10:14.16#ibcon#read 4, iclass 36, count 0 2006.202.00:10:14.16#ibcon#about to read 5, iclass 36, count 0 2006.202.00:10:14.16#ibcon#read 5, iclass 36, count 0 2006.202.00:10:14.16#ibcon#about to read 6, iclass 36, count 0 2006.202.00:10:14.16#ibcon#read 6, iclass 36, count 0 2006.202.00:10:14.16#ibcon#end of sib2, iclass 36, count 0 2006.202.00:10:14.16#ibcon#*after write, iclass 36, count 0 2006.202.00:10:14.16#ibcon#*before return 0, iclass 36, count 0 2006.202.00:10:14.16#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:14.16#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:10:14.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.00:10:14.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.00:10:14.16$vck44/vblo=7,734.99 2006.202.00:10:14.16#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.00:10:14.16#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.00:10:14.16#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:14.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:14.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:14.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:14.16#ibcon#enter wrdev, iclass 38, count 0 2006.202.00:10:14.16#ibcon#first serial, iclass 38, count 0 2006.202.00:10:14.16#ibcon#enter sib2, iclass 38, count 0 2006.202.00:10:14.16#ibcon#flushed, iclass 38, count 0 2006.202.00:10:14.16#ibcon#about to write, iclass 38, count 0 2006.202.00:10:14.16#ibcon#wrote, iclass 38, count 0 2006.202.00:10:14.16#ibcon#about to read 3, iclass 38, count 0 2006.202.00:10:14.18#ibcon#read 3, iclass 38, count 0 2006.202.00:10:14.18#ibcon#about to read 4, iclass 38, count 0 2006.202.00:10:14.18#ibcon#read 4, iclass 38, count 0 2006.202.00:10:14.18#ibcon#about to read 5, iclass 38, count 0 2006.202.00:10:14.18#ibcon#read 5, iclass 38, count 0 2006.202.00:10:14.18#ibcon#about to read 6, iclass 38, count 0 2006.202.00:10:14.18#ibcon#read 6, iclass 38, count 0 2006.202.00:10:14.18#ibcon#end of sib2, iclass 38, count 0 2006.202.00:10:14.18#ibcon#*mode == 0, iclass 38, count 0 2006.202.00:10:14.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.00:10:14.18#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.00:10:14.18#ibcon#*before write, iclass 38, count 0 2006.202.00:10:14.18#ibcon#enter sib2, iclass 38, count 0 2006.202.00:10:14.18#ibcon#flushed, iclass 38, count 0 2006.202.00:10:14.18#ibcon#about to write, iclass 38, count 0 2006.202.00:10:14.18#ibcon#wrote, iclass 38, count 0 2006.202.00:10:14.18#ibcon#about to read 3, iclass 38, count 0 2006.202.00:10:14.22#ibcon#read 3, iclass 38, count 0 2006.202.00:10:14.22#ibcon#about to read 4, iclass 38, count 0 2006.202.00:10:14.22#ibcon#read 4, iclass 38, count 0 2006.202.00:10:14.22#ibcon#about to read 5, iclass 38, count 0 2006.202.00:10:14.22#ibcon#read 5, iclass 38, count 0 2006.202.00:10:14.22#ibcon#about to read 6, iclass 38, count 0 2006.202.00:10:14.22#ibcon#read 6, iclass 38, count 0 2006.202.00:10:14.22#ibcon#end of sib2, iclass 38, count 0 2006.202.00:10:14.22#ibcon#*after write, iclass 38, count 0 2006.202.00:10:14.22#ibcon#*before return 0, iclass 38, count 0 2006.202.00:10:14.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:14.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:10:14.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.00:10:14.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.00:10:14.22$vck44/vb=7,4 2006.202.00:10:14.22#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.202.00:10:14.22#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.202.00:10:14.22#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:14.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:14.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:14.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:14.28#ibcon#enter wrdev, iclass 40, count 2 2006.202.00:10:14.28#ibcon#first serial, iclass 40, count 2 2006.202.00:10:14.28#ibcon#enter sib2, iclass 40, count 2 2006.202.00:10:14.28#ibcon#flushed, iclass 40, count 2 2006.202.00:10:14.28#ibcon#about to write, iclass 40, count 2 2006.202.00:10:14.28#ibcon#wrote, iclass 40, count 2 2006.202.00:10:14.28#ibcon#about to read 3, iclass 40, count 2 2006.202.00:10:14.30#ibcon#read 3, iclass 40, count 2 2006.202.00:10:14.30#ibcon#about to read 4, iclass 40, count 2 2006.202.00:10:14.30#ibcon#read 4, iclass 40, count 2 2006.202.00:10:14.30#ibcon#about to read 5, iclass 40, count 2 2006.202.00:10:14.30#ibcon#read 5, iclass 40, count 2 2006.202.00:10:14.30#ibcon#about to read 6, iclass 40, count 2 2006.202.00:10:14.30#ibcon#read 6, iclass 40, count 2 2006.202.00:10:14.30#ibcon#end of sib2, iclass 40, count 2 2006.202.00:10:14.30#ibcon#*mode == 0, iclass 40, count 2 2006.202.00:10:14.30#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.202.00:10:14.30#ibcon#[27=AT07-04\r\n] 2006.202.00:10:14.30#ibcon#*before write, iclass 40, count 2 2006.202.00:10:14.30#ibcon#enter sib2, iclass 40, count 2 2006.202.00:10:14.30#ibcon#flushed, iclass 40, count 2 2006.202.00:10:14.30#ibcon#about to write, iclass 40, count 2 2006.202.00:10:14.30#ibcon#wrote, iclass 40, count 2 2006.202.00:10:14.30#ibcon#about to read 3, iclass 40, count 2 2006.202.00:10:14.33#ibcon#read 3, iclass 40, count 2 2006.202.00:10:14.33#ibcon#about to read 4, iclass 40, count 2 2006.202.00:10:14.33#ibcon#read 4, iclass 40, count 2 2006.202.00:10:14.33#ibcon#about to read 5, iclass 40, count 2 2006.202.00:10:14.33#ibcon#read 5, iclass 40, count 2 2006.202.00:10:14.33#ibcon#about to read 6, iclass 40, count 2 2006.202.00:10:14.33#ibcon#read 6, iclass 40, count 2 2006.202.00:10:14.33#ibcon#end of sib2, iclass 40, count 2 2006.202.00:10:14.33#ibcon#*after write, iclass 40, count 2 2006.202.00:10:14.33#ibcon#*before return 0, iclass 40, count 2 2006.202.00:10:14.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:14.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:10:14.33#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.202.00:10:14.33#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:14.33#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:14.45#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:14.45#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:14.45#ibcon#enter wrdev, iclass 40, count 0 2006.202.00:10:14.45#ibcon#first serial, iclass 40, count 0 2006.202.00:10:14.45#ibcon#enter sib2, iclass 40, count 0 2006.202.00:10:14.45#ibcon#flushed, iclass 40, count 0 2006.202.00:10:14.45#ibcon#about to write, iclass 40, count 0 2006.202.00:10:14.45#ibcon#wrote, iclass 40, count 0 2006.202.00:10:14.45#ibcon#about to read 3, iclass 40, count 0 2006.202.00:10:14.47#ibcon#read 3, iclass 40, count 0 2006.202.00:10:14.47#ibcon#about to read 4, iclass 40, count 0 2006.202.00:10:14.47#ibcon#read 4, iclass 40, count 0 2006.202.00:10:14.47#ibcon#about to read 5, iclass 40, count 0 2006.202.00:10:14.47#ibcon#read 5, iclass 40, count 0 2006.202.00:10:14.47#ibcon#about to read 6, iclass 40, count 0 2006.202.00:10:14.47#ibcon#read 6, iclass 40, count 0 2006.202.00:10:14.47#ibcon#end of sib2, iclass 40, count 0 2006.202.00:10:14.47#ibcon#*mode == 0, iclass 40, count 0 2006.202.00:10:14.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.00:10:14.47#ibcon#[27=USB\r\n] 2006.202.00:10:14.47#ibcon#*before write, iclass 40, count 0 2006.202.00:10:14.47#ibcon#enter sib2, iclass 40, count 0 2006.202.00:10:14.47#ibcon#flushed, iclass 40, count 0 2006.202.00:10:14.47#ibcon#about to write, iclass 40, count 0 2006.202.00:10:14.47#ibcon#wrote, iclass 40, count 0 2006.202.00:10:14.47#ibcon#about to read 3, iclass 40, count 0 2006.202.00:10:14.50#ibcon#read 3, iclass 40, count 0 2006.202.00:10:14.50#ibcon#about to read 4, iclass 40, count 0 2006.202.00:10:14.50#ibcon#read 4, iclass 40, count 0 2006.202.00:10:14.50#ibcon#about to read 5, iclass 40, count 0 2006.202.00:10:14.50#ibcon#read 5, iclass 40, count 0 2006.202.00:10:14.50#ibcon#about to read 6, iclass 40, count 0 2006.202.00:10:14.50#ibcon#read 6, iclass 40, count 0 2006.202.00:10:14.50#ibcon#end of sib2, iclass 40, count 0 2006.202.00:10:14.50#ibcon#*after write, iclass 40, count 0 2006.202.00:10:14.50#ibcon#*before return 0, iclass 40, count 0 2006.202.00:10:14.50#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:14.50#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:10:14.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.00:10:14.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.00:10:14.50$vck44/vblo=8,744.99 2006.202.00:10:14.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.00:10:14.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.00:10:14.50#ibcon#ireg 17 cls_cnt 0 2006.202.00:10:14.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:14.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:14.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:14.50#ibcon#enter wrdev, iclass 4, count 0 2006.202.00:10:14.50#ibcon#first serial, iclass 4, count 0 2006.202.00:10:14.50#ibcon#enter sib2, iclass 4, count 0 2006.202.00:10:14.50#ibcon#flushed, iclass 4, count 0 2006.202.00:10:14.50#ibcon#about to write, iclass 4, count 0 2006.202.00:10:14.50#ibcon#wrote, iclass 4, count 0 2006.202.00:10:14.50#ibcon#about to read 3, iclass 4, count 0 2006.202.00:10:14.52#ibcon#read 3, iclass 4, count 0 2006.202.00:10:14.52#ibcon#about to read 4, iclass 4, count 0 2006.202.00:10:14.52#ibcon#read 4, iclass 4, count 0 2006.202.00:10:14.52#ibcon#about to read 5, iclass 4, count 0 2006.202.00:10:14.52#ibcon#read 5, iclass 4, count 0 2006.202.00:10:14.52#ibcon#about to read 6, iclass 4, count 0 2006.202.00:10:14.52#ibcon#read 6, iclass 4, count 0 2006.202.00:10:14.52#ibcon#end of sib2, iclass 4, count 0 2006.202.00:10:14.52#ibcon#*mode == 0, iclass 4, count 0 2006.202.00:10:14.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.00:10:14.52#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.00:10:14.52#ibcon#*before write, iclass 4, count 0 2006.202.00:10:14.52#ibcon#enter sib2, iclass 4, count 0 2006.202.00:10:14.52#ibcon#flushed, iclass 4, count 0 2006.202.00:10:14.52#ibcon#about to write, iclass 4, count 0 2006.202.00:10:14.52#ibcon#wrote, iclass 4, count 0 2006.202.00:10:14.52#ibcon#about to read 3, iclass 4, count 0 2006.202.00:10:14.56#ibcon#read 3, iclass 4, count 0 2006.202.00:10:14.56#ibcon#about to read 4, iclass 4, count 0 2006.202.00:10:14.56#ibcon#read 4, iclass 4, count 0 2006.202.00:10:14.56#ibcon#about to read 5, iclass 4, count 0 2006.202.00:10:14.56#ibcon#read 5, iclass 4, count 0 2006.202.00:10:14.56#ibcon#about to read 6, iclass 4, count 0 2006.202.00:10:14.56#ibcon#read 6, iclass 4, count 0 2006.202.00:10:14.56#ibcon#end of sib2, iclass 4, count 0 2006.202.00:10:14.56#ibcon#*after write, iclass 4, count 0 2006.202.00:10:14.56#ibcon#*before return 0, iclass 4, count 0 2006.202.00:10:14.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:14.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:10:14.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.00:10:14.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.00:10:14.56$vck44/vb=8,4 2006.202.00:10:14.56#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.202.00:10:14.56#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.202.00:10:14.56#ibcon#ireg 11 cls_cnt 2 2006.202.00:10:14.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:14.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:14.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:14.62#ibcon#enter wrdev, iclass 6, count 2 2006.202.00:10:14.62#ibcon#first serial, iclass 6, count 2 2006.202.00:10:14.62#ibcon#enter sib2, iclass 6, count 2 2006.202.00:10:14.62#ibcon#flushed, iclass 6, count 2 2006.202.00:10:14.62#ibcon#about to write, iclass 6, count 2 2006.202.00:10:14.62#ibcon#wrote, iclass 6, count 2 2006.202.00:10:14.62#ibcon#about to read 3, iclass 6, count 2 2006.202.00:10:14.64#ibcon#read 3, iclass 6, count 2 2006.202.00:10:14.64#ibcon#about to read 4, iclass 6, count 2 2006.202.00:10:14.64#ibcon#read 4, iclass 6, count 2 2006.202.00:10:14.64#ibcon#about to read 5, iclass 6, count 2 2006.202.00:10:14.64#ibcon#read 5, iclass 6, count 2 2006.202.00:10:14.64#ibcon#about to read 6, iclass 6, count 2 2006.202.00:10:14.64#ibcon#read 6, iclass 6, count 2 2006.202.00:10:14.64#ibcon#end of sib2, iclass 6, count 2 2006.202.00:10:14.64#ibcon#*mode == 0, iclass 6, count 2 2006.202.00:10:14.64#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.202.00:10:14.64#ibcon#[27=AT08-04\r\n] 2006.202.00:10:14.64#ibcon#*before write, iclass 6, count 2 2006.202.00:10:14.64#ibcon#enter sib2, iclass 6, count 2 2006.202.00:10:14.64#ibcon#flushed, iclass 6, count 2 2006.202.00:10:14.64#ibcon#about to write, iclass 6, count 2 2006.202.00:10:14.64#ibcon#wrote, iclass 6, count 2 2006.202.00:10:14.64#ibcon#about to read 3, iclass 6, count 2 2006.202.00:10:14.67#ibcon#read 3, iclass 6, count 2 2006.202.00:10:14.67#ibcon#about to read 4, iclass 6, count 2 2006.202.00:10:14.67#ibcon#read 4, iclass 6, count 2 2006.202.00:10:14.67#ibcon#about to read 5, iclass 6, count 2 2006.202.00:10:14.67#ibcon#read 5, iclass 6, count 2 2006.202.00:10:14.67#ibcon#about to read 6, iclass 6, count 2 2006.202.00:10:14.67#ibcon#read 6, iclass 6, count 2 2006.202.00:10:14.67#ibcon#end of sib2, iclass 6, count 2 2006.202.00:10:14.67#ibcon#*after write, iclass 6, count 2 2006.202.00:10:14.67#ibcon#*before return 0, iclass 6, count 2 2006.202.00:10:14.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:14.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:10:14.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.202.00:10:14.72#ibcon#ireg 7 cls_cnt 0 2006.202.00:10:14.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:14.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:14.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:14.84#ibcon#enter wrdev, iclass 6, count 0 2006.202.00:10:14.84#ibcon#first serial, iclass 6, count 0 2006.202.00:10:14.84#ibcon#enter sib2, iclass 6, count 0 2006.202.00:10:14.84#ibcon#flushed, iclass 6, count 0 2006.202.00:10:14.84#ibcon#about to write, iclass 6, count 0 2006.202.00:10:14.84#ibcon#wrote, iclass 6, count 0 2006.202.00:10:14.84#ibcon#about to read 3, iclass 6, count 0 2006.202.00:10:14.86#ibcon#read 3, iclass 6, count 0 2006.202.00:10:14.86#ibcon#about to read 4, iclass 6, count 0 2006.202.00:10:14.86#ibcon#read 4, iclass 6, count 0 2006.202.00:10:14.86#ibcon#about to read 5, iclass 6, count 0 2006.202.00:10:14.86#ibcon#read 5, iclass 6, count 0 2006.202.00:10:14.86#ibcon#about to read 6, iclass 6, count 0 2006.202.00:10:14.86#ibcon#read 6, iclass 6, count 0 2006.202.00:10:14.86#ibcon#end of sib2, iclass 6, count 0 2006.202.00:10:14.86#ibcon#*mode == 0, iclass 6, count 0 2006.202.00:10:14.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.00:10:14.86#ibcon#[27=USB\r\n] 2006.202.00:10:14.86#ibcon#*before write, iclass 6, count 0 2006.202.00:10:14.86#ibcon#enter sib2, iclass 6, count 0 2006.202.00:10:14.86#ibcon#flushed, iclass 6, count 0 2006.202.00:10:14.86#ibcon#about to write, iclass 6, count 0 2006.202.00:10:14.86#ibcon#wrote, iclass 6, count 0 2006.202.00:10:14.86#ibcon#about to read 3, iclass 6, count 0 2006.202.00:10:14.89#ibcon#read 3, iclass 6, count 0 2006.202.00:10:14.89#ibcon#about to read 4, iclass 6, count 0 2006.202.00:10:14.89#ibcon#read 4, iclass 6, count 0 2006.202.00:10:14.89#ibcon#about to read 5, iclass 6, count 0 2006.202.00:10:14.89#ibcon#read 5, iclass 6, count 0 2006.202.00:10:14.89#ibcon#about to read 6, iclass 6, count 0 2006.202.00:10:14.89#ibcon#read 6, iclass 6, count 0 2006.202.00:10:14.89#ibcon#end of sib2, iclass 6, count 0 2006.202.00:10:14.89#ibcon#*after write, iclass 6, count 0 2006.202.00:10:14.89#ibcon#*before return 0, iclass 6, count 0 2006.202.00:10:14.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:14.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:10:14.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.00:10:14.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.00:10:14.89$vck44/vabw=wide 2006.202.00:10:14.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.00:10:14.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.00:10:14.89#ibcon#ireg 8 cls_cnt 0 2006.202.00:10:14.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:14.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:14.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:14.89#ibcon#enter wrdev, iclass 10, count 0 2006.202.00:10:14.89#ibcon#first serial, iclass 10, count 0 2006.202.00:10:14.89#ibcon#enter sib2, iclass 10, count 0 2006.202.00:10:14.89#ibcon#flushed, iclass 10, count 0 2006.202.00:10:14.89#ibcon#about to write, iclass 10, count 0 2006.202.00:10:14.89#ibcon#wrote, iclass 10, count 0 2006.202.00:10:14.89#ibcon#about to read 3, iclass 10, count 0 2006.202.00:10:14.91#ibcon#read 3, iclass 10, count 0 2006.202.00:10:14.91#ibcon#about to read 4, iclass 10, count 0 2006.202.00:10:14.91#ibcon#read 4, iclass 10, count 0 2006.202.00:10:14.91#ibcon#about to read 5, iclass 10, count 0 2006.202.00:10:14.91#ibcon#read 5, iclass 10, count 0 2006.202.00:10:14.91#ibcon#about to read 6, iclass 10, count 0 2006.202.00:10:14.91#ibcon#read 6, iclass 10, count 0 2006.202.00:10:14.91#ibcon#end of sib2, iclass 10, count 0 2006.202.00:10:14.91#ibcon#*mode == 0, iclass 10, count 0 2006.202.00:10:14.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.00:10:14.91#ibcon#[25=BW32\r\n] 2006.202.00:10:14.91#ibcon#*before write, iclass 10, count 0 2006.202.00:10:14.91#ibcon#enter sib2, iclass 10, count 0 2006.202.00:10:14.91#ibcon#flushed, iclass 10, count 0 2006.202.00:10:14.91#ibcon#about to write, iclass 10, count 0 2006.202.00:10:14.91#ibcon#wrote, iclass 10, count 0 2006.202.00:10:14.91#ibcon#about to read 3, iclass 10, count 0 2006.202.00:10:14.94#ibcon#read 3, iclass 10, count 0 2006.202.00:10:14.94#ibcon#about to read 4, iclass 10, count 0 2006.202.00:10:14.94#ibcon#read 4, iclass 10, count 0 2006.202.00:10:14.94#ibcon#about to read 5, iclass 10, count 0 2006.202.00:10:14.94#ibcon#read 5, iclass 10, count 0 2006.202.00:10:14.94#ibcon#about to read 6, iclass 10, count 0 2006.202.00:10:14.94#ibcon#read 6, iclass 10, count 0 2006.202.00:10:14.94#ibcon#end of sib2, iclass 10, count 0 2006.202.00:10:14.94#ibcon#*after write, iclass 10, count 0 2006.202.00:10:14.94#ibcon#*before return 0, iclass 10, count 0 2006.202.00:10:14.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:14.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:10:14.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.00:10:14.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.00:10:14.94$vck44/vbbw=wide 2006.202.00:10:14.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.202.00:10:14.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.202.00:10:14.94#ibcon#ireg 8 cls_cnt 0 2006.202.00:10:14.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:10:15.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:10:15.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:10:15.01#ibcon#enter wrdev, iclass 12, count 0 2006.202.00:10:15.01#ibcon#first serial, iclass 12, count 0 2006.202.00:10:15.01#ibcon#enter sib2, iclass 12, count 0 2006.202.00:10:15.01#ibcon#flushed, iclass 12, count 0 2006.202.00:10:15.01#ibcon#about to write, iclass 12, count 0 2006.202.00:10:15.01#ibcon#wrote, iclass 12, count 0 2006.202.00:10:15.01#ibcon#about to read 3, iclass 12, count 0 2006.202.00:10:15.03#ibcon#read 3, iclass 12, count 0 2006.202.00:10:15.03#ibcon#about to read 4, iclass 12, count 0 2006.202.00:10:15.03#ibcon#read 4, iclass 12, count 0 2006.202.00:10:15.03#ibcon#about to read 5, iclass 12, count 0 2006.202.00:10:15.03#ibcon#read 5, iclass 12, count 0 2006.202.00:10:15.03#ibcon#about to read 6, iclass 12, count 0 2006.202.00:10:15.03#ibcon#read 6, iclass 12, count 0 2006.202.00:10:15.03#ibcon#end of sib2, iclass 12, count 0 2006.202.00:10:15.03#ibcon#*mode == 0, iclass 12, count 0 2006.202.00:10:15.03#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.00:10:15.03#ibcon#[27=BW32\r\n] 2006.202.00:10:15.03#ibcon#*before write, iclass 12, count 0 2006.202.00:10:15.03#ibcon#enter sib2, iclass 12, count 0 2006.202.00:10:15.03#ibcon#flushed, iclass 12, count 0 2006.202.00:10:15.03#ibcon#about to write, iclass 12, count 0 2006.202.00:10:15.03#ibcon#wrote, iclass 12, count 0 2006.202.00:10:15.03#ibcon#about to read 3, iclass 12, count 0 2006.202.00:10:15.06#ibcon#read 3, iclass 12, count 0 2006.202.00:10:15.06#ibcon#about to read 4, iclass 12, count 0 2006.202.00:10:15.06#ibcon#read 4, iclass 12, count 0 2006.202.00:10:15.06#ibcon#about to read 5, iclass 12, count 0 2006.202.00:10:15.06#ibcon#read 5, iclass 12, count 0 2006.202.00:10:15.06#ibcon#about to read 6, iclass 12, count 0 2006.202.00:10:15.06#ibcon#read 6, iclass 12, count 0 2006.202.00:10:15.06#ibcon#end of sib2, iclass 12, count 0 2006.202.00:10:15.06#ibcon#*after write, iclass 12, count 0 2006.202.00:10:15.06#ibcon#*before return 0, iclass 12, count 0 2006.202.00:10:15.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:10:15.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:10:15.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.00:10:15.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.00:10:15.06$setupk4/ifdk4 2006.202.00:10:15.06$ifdk4/lo= 2006.202.00:10:15.06$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.00:10:15.06$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.00:10:15.06$ifdk4/patch= 2006.202.00:10:15.06$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.00:10:15.06$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.00:10:15.06$setupk4/!*+20s 2006.202.00:10:18.14#trakl#Source acquired 2006.202.00:10:20.14#flagr#flagr/antenna,acquired 2006.202.00:10:23.82#abcon#<5=/03 1.1 2.1 20.441001001.4\r\n> 2006.202.00:10:23.84#abcon#{5=INTERFACE CLEAR} 2006.202.00:10:23.90#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:10:29.25$setupk4/"tpicd 2006.202.00:10:29.25$setupk4/echo=off 2006.202.00:10:29.25$setupk4/xlog=off 2006.202.00:10:29.25:!2006.202.00:18:40 2006.202.00:18:40.00:preob 2006.202.00:18:40.14/onsource/TRACKING 2006.202.00:18:40.14:!2006.202.00:18:50 2006.202.00:18:50.00:"tape 2006.202.00:18:50.00:"st=record 2006.202.00:18:50.00:data_valid=on 2006.202.00:18:50.01:midob 2006.202.00:18:51.14/onsource/TRACKING 2006.202.00:18:51.14/wx/20.41,1001.5,100 2006.202.00:18:51.30/cable/+6.4850E-03 2006.202.00:18:52.39/va/01,08,usb,yes,42,45 2006.202.00:18:52.39/va/02,07,usb,yes,46,47 2006.202.00:18:52.39/va/03,08,usb,yes,41,43 2006.202.00:18:52.39/va/04,07,usb,yes,47,50 2006.202.00:18:52.40/va/05,04,usb,yes,42,43 2006.202.00:18:52.40/va/06,05,usb,yes,42,42 2006.202.00:18:52.40/va/07,05,usb,yes,41,43 2006.202.00:18:52.41/va/08,04,usb,yes,41,49 2006.202.00:18:52.64/valo/01,524.99,yes,locked 2006.202.00:18:52.64/valo/02,534.99,yes,locked 2006.202.00:18:52.64/valo/03,564.99,yes,locked 2006.202.00:18:52.64/valo/04,624.99,yes,locked 2006.202.00:18:52.64/valo/05,734.99,yes,locked 2006.202.00:18:52.64/valo/06,814.99,yes,locked 2006.202.00:18:52.64/valo/07,864.99,yes,locked 2006.202.00:18:52.64/valo/08,884.99,yes,locked 2006.202.00:18:53.73/vb/01,04,usb,yes,30,28 2006.202.00:18:53.73/vb/02,05,usb,yes,28,28 2006.202.00:18:53.73/vb/03,04,usb,yes,29,32 2006.202.00:18:53.73/vb/04,05,usb,yes,29,28 2006.202.00:18:53.73/vb/05,04,usb,yes,26,28 2006.202.00:18:53.73/vb/06,04,usb,yes,30,27 2006.202.00:18:53.73/vb/07,04,usb,yes,30,30 2006.202.00:18:53.73/vb/08,04,usb,yes,28,31 2006.202.00:18:53.96/vblo/01,629.99,yes,locked 2006.202.00:18:53.96/vblo/02,634.99,yes,locked 2006.202.00:18:53.96/vblo/03,649.99,yes,locked 2006.202.00:18:53.96/vblo/04,679.99,yes,locked 2006.202.00:18:53.96/vblo/05,709.99,yes,locked 2006.202.00:18:53.96/vblo/06,719.99,yes,locked 2006.202.00:18:53.96/vblo/07,734.99,yes,locked 2006.202.00:18:53.96/vblo/08,744.99,yes,locked 2006.202.00:18:54.11/vabw/8 2006.202.00:18:54.26/vbbw/8 2006.202.00:18:54.35/xfe/off,on,14.0 2006.202.00:18:54.73/ifatt/23,28,28,28 2006.202.00:18:55.07/fmout-gps/S +4.55E-07 2006.202.00:18:55.11:!2006.202.00:22:30 2006.202.00:22:30.00:data_valid=off 2006.202.00:22:30.00:"et 2006.202.00:22:30.00:!+3s 2006.202.00:22:33.02:"tape 2006.202.00:22:33.02:postob 2006.202.00:22:33.22/cable/+6.4825E-03 2006.202.00:22:33.22/wx/20.42,1001.4,100 2006.202.00:22:33.28/fmout-gps/S +4.53E-07 2006.202.00:22:33.28:scan_name=202-0033,jd0607,60 2006.202.00:22:33.28:source=0727-115,073019.11,-114112.6,2000.0,cw 2006.202.00:22:34.14#flagr#flagr/antenna,new-source 2006.202.00:22:34.14:checkk5 2006.202.00:22:34.56/chk_autoobs//k5ts1/ autoobs is running! 2006.202.00:22:34.97/chk_autoobs//k5ts2/ autoobs is running! 2006.202.00:22:35.36/chk_autoobs//k5ts3/ autoobs is running! 2006.202.00:22:35.77/chk_autoobs//k5ts4/ autoobs is running! 2006.202.00:22:36.19/chk_obsdata//k5ts1/T2020018??a.dat file size is correct (nominal:880MB, actual:876MB). 2006.202.00:22:36.59/chk_obsdata//k5ts2/T2020018??b.dat file size is correct (nominal:880MB, actual:876MB). 2006.202.00:22:36.99/chk_obsdata//k5ts3/T2020018??c.dat file size is correct (nominal:880MB, actual:876MB). 2006.202.00:22:37.40/chk_obsdata//k5ts4/T2020018??d.dat file size is correct (nominal:880MB, actual:876MB). 2006.202.00:22:38.12/k5log//k5ts1_log_newline 2006.202.00:22:38.83/k5log//k5ts2_log_newline 2006.202.00:22:39.56/k5log//k5ts3_log_newline 2006.202.00:22:40.27/k5log//k5ts4_log_newline 2006.202.00:22:40.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.00:22:40.29:setupk4=1 2006.202.00:22:40.29$setupk4/echo=on 2006.202.00:22:40.29$setupk4/pcalon 2006.202.00:22:40.29$pcalon/"no phase cal control is implemented here 2006.202.00:22:40.29$setupk4/"tpicd=stop 2006.202.00:22:40.29$setupk4/"rec=synch_on 2006.202.00:22:40.29$setupk4/"rec_mode=128 2006.202.00:22:40.29$setupk4/!* 2006.202.00:22:40.29$setupk4/recpk4 2006.202.00:22:40.30$recpk4/recpatch= 2006.202.00:22:40.30$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.00:22:40.30$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.00:22:40.30$setupk4/vck44 2006.202.00:22:40.30$vck44/valo=1,524.99 2006.202.00:22:40.30#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.202.00:22:40.30#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.202.00:22:40.30#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:40.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:40.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:40.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:40.30#ibcon#enter wrdev, iclass 21, count 0 2006.202.00:22:40.30#ibcon#first serial, iclass 21, count 0 2006.202.00:22:40.30#ibcon#enter sib2, iclass 21, count 0 2006.202.00:22:40.30#ibcon#flushed, iclass 21, count 0 2006.202.00:22:40.30#ibcon#about to write, iclass 21, count 0 2006.202.00:22:40.30#ibcon#wrote, iclass 21, count 0 2006.202.00:22:40.30#ibcon#about to read 3, iclass 21, count 0 2006.202.00:22:40.32#ibcon#read 3, iclass 21, count 0 2006.202.00:22:40.32#ibcon#about to read 4, iclass 21, count 0 2006.202.00:22:40.32#ibcon#read 4, iclass 21, count 0 2006.202.00:22:40.32#ibcon#about to read 5, iclass 21, count 0 2006.202.00:22:40.32#ibcon#read 5, iclass 21, count 0 2006.202.00:22:40.32#ibcon#about to read 6, iclass 21, count 0 2006.202.00:22:40.32#ibcon#read 6, iclass 21, count 0 2006.202.00:22:40.32#ibcon#end of sib2, iclass 21, count 0 2006.202.00:22:40.32#ibcon#*mode == 0, iclass 21, count 0 2006.202.00:22:40.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.00:22:40.32#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.00:22:40.32#ibcon#*before write, iclass 21, count 0 2006.202.00:22:40.32#ibcon#enter sib2, iclass 21, count 0 2006.202.00:22:40.32#ibcon#flushed, iclass 21, count 0 2006.202.00:22:40.32#ibcon#about to write, iclass 21, count 0 2006.202.00:22:40.32#ibcon#wrote, iclass 21, count 0 2006.202.00:22:40.32#ibcon#about to read 3, iclass 21, count 0 2006.202.00:22:40.37#ibcon#read 3, iclass 21, count 0 2006.202.00:22:40.37#ibcon#about to read 4, iclass 21, count 0 2006.202.00:22:40.37#ibcon#read 4, iclass 21, count 0 2006.202.00:22:40.37#ibcon#about to read 5, iclass 21, count 0 2006.202.00:22:40.37#ibcon#read 5, iclass 21, count 0 2006.202.00:22:40.37#ibcon#about to read 6, iclass 21, count 0 2006.202.00:22:40.37#ibcon#read 6, iclass 21, count 0 2006.202.00:22:40.37#ibcon#end of sib2, iclass 21, count 0 2006.202.00:22:40.37#ibcon#*after write, iclass 21, count 0 2006.202.00:22:40.37#ibcon#*before return 0, iclass 21, count 0 2006.202.00:22:40.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:40.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:40.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.00:22:40.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.00:22:40.37$vck44/va=1,8 2006.202.00:22:40.37#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.202.00:22:40.37#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.202.00:22:40.37#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:40.37#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:40.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:40.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:40.37#ibcon#enter wrdev, iclass 23, count 2 2006.202.00:22:40.37#ibcon#first serial, iclass 23, count 2 2006.202.00:22:40.37#ibcon#enter sib2, iclass 23, count 2 2006.202.00:22:40.37#ibcon#flushed, iclass 23, count 2 2006.202.00:22:40.37#ibcon#about to write, iclass 23, count 2 2006.202.00:22:40.37#ibcon#wrote, iclass 23, count 2 2006.202.00:22:40.37#ibcon#about to read 3, iclass 23, count 2 2006.202.00:22:40.39#ibcon#read 3, iclass 23, count 2 2006.202.00:22:40.39#ibcon#about to read 4, iclass 23, count 2 2006.202.00:22:40.39#ibcon#read 4, iclass 23, count 2 2006.202.00:22:40.39#ibcon#about to read 5, iclass 23, count 2 2006.202.00:22:40.39#ibcon#read 5, iclass 23, count 2 2006.202.00:22:40.39#ibcon#about to read 6, iclass 23, count 2 2006.202.00:22:40.39#ibcon#read 6, iclass 23, count 2 2006.202.00:22:40.39#ibcon#end of sib2, iclass 23, count 2 2006.202.00:22:40.39#ibcon#*mode == 0, iclass 23, count 2 2006.202.00:22:40.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.202.00:22:40.39#ibcon#[25=AT01-08\r\n] 2006.202.00:22:40.39#ibcon#*before write, iclass 23, count 2 2006.202.00:22:40.39#ibcon#enter sib2, iclass 23, count 2 2006.202.00:22:40.39#ibcon#flushed, iclass 23, count 2 2006.202.00:22:40.39#ibcon#about to write, iclass 23, count 2 2006.202.00:22:40.39#ibcon#wrote, iclass 23, count 2 2006.202.00:22:40.39#ibcon#about to read 3, iclass 23, count 2 2006.202.00:22:40.42#ibcon#read 3, iclass 23, count 2 2006.202.00:22:40.42#ibcon#about to read 4, iclass 23, count 2 2006.202.00:22:40.42#ibcon#read 4, iclass 23, count 2 2006.202.00:22:40.42#ibcon#about to read 5, iclass 23, count 2 2006.202.00:22:40.42#ibcon#read 5, iclass 23, count 2 2006.202.00:22:40.42#ibcon#about to read 6, iclass 23, count 2 2006.202.00:22:40.42#ibcon#read 6, iclass 23, count 2 2006.202.00:22:40.42#ibcon#end of sib2, iclass 23, count 2 2006.202.00:22:40.42#ibcon#*after write, iclass 23, count 2 2006.202.00:22:40.42#ibcon#*before return 0, iclass 23, count 2 2006.202.00:22:40.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:40.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:40.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.202.00:22:40.42#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:40.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:40.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:40.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:40.54#ibcon#enter wrdev, iclass 23, count 0 2006.202.00:22:40.54#ibcon#first serial, iclass 23, count 0 2006.202.00:22:40.54#ibcon#enter sib2, iclass 23, count 0 2006.202.00:22:40.54#ibcon#flushed, iclass 23, count 0 2006.202.00:22:40.54#ibcon#about to write, iclass 23, count 0 2006.202.00:22:40.54#ibcon#wrote, iclass 23, count 0 2006.202.00:22:40.54#ibcon#about to read 3, iclass 23, count 0 2006.202.00:22:40.56#ibcon#read 3, iclass 23, count 0 2006.202.00:22:40.56#ibcon#about to read 4, iclass 23, count 0 2006.202.00:22:40.56#ibcon#read 4, iclass 23, count 0 2006.202.00:22:40.56#ibcon#about to read 5, iclass 23, count 0 2006.202.00:22:40.56#ibcon#read 5, iclass 23, count 0 2006.202.00:22:40.56#ibcon#about to read 6, iclass 23, count 0 2006.202.00:22:40.56#ibcon#read 6, iclass 23, count 0 2006.202.00:22:40.56#ibcon#end of sib2, iclass 23, count 0 2006.202.00:22:40.56#ibcon#*mode == 0, iclass 23, count 0 2006.202.00:22:40.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.00:22:40.56#ibcon#[25=USB\r\n] 2006.202.00:22:40.56#ibcon#*before write, iclass 23, count 0 2006.202.00:22:40.56#ibcon#enter sib2, iclass 23, count 0 2006.202.00:22:40.56#ibcon#flushed, iclass 23, count 0 2006.202.00:22:40.56#ibcon#about to write, iclass 23, count 0 2006.202.00:22:40.56#ibcon#wrote, iclass 23, count 0 2006.202.00:22:40.56#ibcon#about to read 3, iclass 23, count 0 2006.202.00:22:40.59#ibcon#read 3, iclass 23, count 0 2006.202.00:22:40.59#ibcon#about to read 4, iclass 23, count 0 2006.202.00:22:40.59#ibcon#read 4, iclass 23, count 0 2006.202.00:22:40.59#ibcon#about to read 5, iclass 23, count 0 2006.202.00:22:40.59#ibcon#read 5, iclass 23, count 0 2006.202.00:22:40.59#ibcon#about to read 6, iclass 23, count 0 2006.202.00:22:40.59#ibcon#read 6, iclass 23, count 0 2006.202.00:22:40.59#ibcon#end of sib2, iclass 23, count 0 2006.202.00:22:40.59#ibcon#*after write, iclass 23, count 0 2006.202.00:22:40.59#ibcon#*before return 0, iclass 23, count 0 2006.202.00:22:40.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:40.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:40.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.00:22:40.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.00:22:40.59$vck44/valo=2,534.99 2006.202.00:22:40.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.202.00:22:40.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.202.00:22:40.59#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:40.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:40.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:40.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:40.59#ibcon#enter wrdev, iclass 25, count 0 2006.202.00:22:40.59#ibcon#first serial, iclass 25, count 0 2006.202.00:22:40.59#ibcon#enter sib2, iclass 25, count 0 2006.202.00:22:40.59#ibcon#flushed, iclass 25, count 0 2006.202.00:22:40.59#ibcon#about to write, iclass 25, count 0 2006.202.00:22:40.59#ibcon#wrote, iclass 25, count 0 2006.202.00:22:40.59#ibcon#about to read 3, iclass 25, count 0 2006.202.00:22:40.61#ibcon#read 3, iclass 25, count 0 2006.202.00:22:40.61#ibcon#about to read 4, iclass 25, count 0 2006.202.00:22:40.61#ibcon#read 4, iclass 25, count 0 2006.202.00:22:40.61#ibcon#about to read 5, iclass 25, count 0 2006.202.00:22:40.61#ibcon#read 5, iclass 25, count 0 2006.202.00:22:40.61#ibcon#about to read 6, iclass 25, count 0 2006.202.00:22:40.61#ibcon#read 6, iclass 25, count 0 2006.202.00:22:40.61#ibcon#end of sib2, iclass 25, count 0 2006.202.00:22:40.61#ibcon#*mode == 0, iclass 25, count 0 2006.202.00:22:40.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.00:22:40.61#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.00:22:40.61#ibcon#*before write, iclass 25, count 0 2006.202.00:22:40.61#ibcon#enter sib2, iclass 25, count 0 2006.202.00:22:40.61#ibcon#flushed, iclass 25, count 0 2006.202.00:22:40.61#ibcon#about to write, iclass 25, count 0 2006.202.00:22:40.61#ibcon#wrote, iclass 25, count 0 2006.202.00:22:40.61#ibcon#about to read 3, iclass 25, count 0 2006.202.00:22:40.65#ibcon#read 3, iclass 25, count 0 2006.202.00:22:40.65#ibcon#about to read 4, iclass 25, count 0 2006.202.00:22:40.65#ibcon#read 4, iclass 25, count 0 2006.202.00:22:40.65#ibcon#about to read 5, iclass 25, count 0 2006.202.00:22:40.65#ibcon#read 5, iclass 25, count 0 2006.202.00:22:40.65#ibcon#about to read 6, iclass 25, count 0 2006.202.00:22:40.65#ibcon#read 6, iclass 25, count 0 2006.202.00:22:40.65#ibcon#end of sib2, iclass 25, count 0 2006.202.00:22:40.65#ibcon#*after write, iclass 25, count 0 2006.202.00:22:40.65#ibcon#*before return 0, iclass 25, count 0 2006.202.00:22:40.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:40.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:40.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.00:22:40.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.00:22:40.65$vck44/va=2,7 2006.202.00:22:40.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.202.00:22:40.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.202.00:22:40.65#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:40.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:40.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:40.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:40.71#ibcon#enter wrdev, iclass 27, count 2 2006.202.00:22:40.71#ibcon#first serial, iclass 27, count 2 2006.202.00:22:40.71#ibcon#enter sib2, iclass 27, count 2 2006.202.00:22:40.71#ibcon#flushed, iclass 27, count 2 2006.202.00:22:40.71#ibcon#about to write, iclass 27, count 2 2006.202.00:22:40.71#ibcon#wrote, iclass 27, count 2 2006.202.00:22:40.71#ibcon#about to read 3, iclass 27, count 2 2006.202.00:22:40.73#ibcon#read 3, iclass 27, count 2 2006.202.00:22:40.73#ibcon#about to read 4, iclass 27, count 2 2006.202.00:22:40.73#ibcon#read 4, iclass 27, count 2 2006.202.00:22:40.73#ibcon#about to read 5, iclass 27, count 2 2006.202.00:22:40.73#ibcon#read 5, iclass 27, count 2 2006.202.00:22:40.73#ibcon#about to read 6, iclass 27, count 2 2006.202.00:22:40.73#ibcon#read 6, iclass 27, count 2 2006.202.00:22:40.73#ibcon#end of sib2, iclass 27, count 2 2006.202.00:22:40.73#ibcon#*mode == 0, iclass 27, count 2 2006.202.00:22:40.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.202.00:22:40.73#ibcon#[25=AT02-07\r\n] 2006.202.00:22:40.73#ibcon#*before write, iclass 27, count 2 2006.202.00:22:40.73#ibcon#enter sib2, iclass 27, count 2 2006.202.00:22:40.73#ibcon#flushed, iclass 27, count 2 2006.202.00:22:40.73#ibcon#about to write, iclass 27, count 2 2006.202.00:22:40.73#ibcon#wrote, iclass 27, count 2 2006.202.00:22:40.73#ibcon#about to read 3, iclass 27, count 2 2006.202.00:22:40.76#ibcon#read 3, iclass 27, count 2 2006.202.00:22:40.76#ibcon#about to read 4, iclass 27, count 2 2006.202.00:22:40.76#ibcon#read 4, iclass 27, count 2 2006.202.00:22:40.76#ibcon#about to read 5, iclass 27, count 2 2006.202.00:22:40.76#ibcon#read 5, iclass 27, count 2 2006.202.00:22:40.76#ibcon#about to read 6, iclass 27, count 2 2006.202.00:22:40.76#ibcon#read 6, iclass 27, count 2 2006.202.00:22:40.76#ibcon#end of sib2, iclass 27, count 2 2006.202.00:22:40.76#ibcon#*after write, iclass 27, count 2 2006.202.00:22:40.76#ibcon#*before return 0, iclass 27, count 2 2006.202.00:22:40.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:40.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:40.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.202.00:22:40.76#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:40.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:40.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:40.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:40.88#ibcon#enter wrdev, iclass 27, count 0 2006.202.00:22:40.88#ibcon#first serial, iclass 27, count 0 2006.202.00:22:40.88#ibcon#enter sib2, iclass 27, count 0 2006.202.00:22:40.88#ibcon#flushed, iclass 27, count 0 2006.202.00:22:40.88#ibcon#about to write, iclass 27, count 0 2006.202.00:22:40.88#ibcon#wrote, iclass 27, count 0 2006.202.00:22:40.88#ibcon#about to read 3, iclass 27, count 0 2006.202.00:22:40.90#ibcon#read 3, iclass 27, count 0 2006.202.00:22:40.90#ibcon#about to read 4, iclass 27, count 0 2006.202.00:22:40.90#ibcon#read 4, iclass 27, count 0 2006.202.00:22:40.90#ibcon#about to read 5, iclass 27, count 0 2006.202.00:22:40.90#ibcon#read 5, iclass 27, count 0 2006.202.00:22:40.90#ibcon#about to read 6, iclass 27, count 0 2006.202.00:22:40.90#ibcon#read 6, iclass 27, count 0 2006.202.00:22:40.90#ibcon#end of sib2, iclass 27, count 0 2006.202.00:22:40.90#ibcon#*mode == 0, iclass 27, count 0 2006.202.00:22:40.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.00:22:40.90#ibcon#[25=USB\r\n] 2006.202.00:22:40.90#ibcon#*before write, iclass 27, count 0 2006.202.00:22:40.90#ibcon#enter sib2, iclass 27, count 0 2006.202.00:22:40.90#ibcon#flushed, iclass 27, count 0 2006.202.00:22:40.90#ibcon#about to write, iclass 27, count 0 2006.202.00:22:40.90#ibcon#wrote, iclass 27, count 0 2006.202.00:22:40.90#ibcon#about to read 3, iclass 27, count 0 2006.202.00:22:40.93#ibcon#read 3, iclass 27, count 0 2006.202.00:22:40.93#ibcon#about to read 4, iclass 27, count 0 2006.202.00:22:40.93#ibcon#read 4, iclass 27, count 0 2006.202.00:22:40.93#ibcon#about to read 5, iclass 27, count 0 2006.202.00:22:40.93#ibcon#read 5, iclass 27, count 0 2006.202.00:22:40.93#ibcon#about to read 6, iclass 27, count 0 2006.202.00:22:40.93#ibcon#read 6, iclass 27, count 0 2006.202.00:22:40.93#ibcon#end of sib2, iclass 27, count 0 2006.202.00:22:40.93#ibcon#*after write, iclass 27, count 0 2006.202.00:22:40.93#ibcon#*before return 0, iclass 27, count 0 2006.202.00:22:40.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:40.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:40.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.00:22:40.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.00:22:40.93$vck44/valo=3,564.99 2006.202.00:22:40.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.202.00:22:40.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.202.00:22:40.93#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:40.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:40.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:40.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:40.93#ibcon#enter wrdev, iclass 29, count 0 2006.202.00:22:40.93#ibcon#first serial, iclass 29, count 0 2006.202.00:22:40.93#ibcon#enter sib2, iclass 29, count 0 2006.202.00:22:40.93#ibcon#flushed, iclass 29, count 0 2006.202.00:22:40.93#ibcon#about to write, iclass 29, count 0 2006.202.00:22:40.93#ibcon#wrote, iclass 29, count 0 2006.202.00:22:40.93#ibcon#about to read 3, iclass 29, count 0 2006.202.00:22:40.95#ibcon#read 3, iclass 29, count 0 2006.202.00:22:40.95#ibcon#about to read 4, iclass 29, count 0 2006.202.00:22:40.95#ibcon#read 4, iclass 29, count 0 2006.202.00:22:40.95#ibcon#about to read 5, iclass 29, count 0 2006.202.00:22:40.95#ibcon#read 5, iclass 29, count 0 2006.202.00:22:40.95#ibcon#about to read 6, iclass 29, count 0 2006.202.00:22:40.95#ibcon#read 6, iclass 29, count 0 2006.202.00:22:40.95#ibcon#end of sib2, iclass 29, count 0 2006.202.00:22:40.95#ibcon#*mode == 0, iclass 29, count 0 2006.202.00:22:40.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.00:22:40.95#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.00:22:40.95#ibcon#*before write, iclass 29, count 0 2006.202.00:22:40.95#ibcon#enter sib2, iclass 29, count 0 2006.202.00:22:40.95#ibcon#flushed, iclass 29, count 0 2006.202.00:22:40.95#ibcon#about to write, iclass 29, count 0 2006.202.00:22:40.95#ibcon#wrote, iclass 29, count 0 2006.202.00:22:40.95#ibcon#about to read 3, iclass 29, count 0 2006.202.00:22:40.99#ibcon#read 3, iclass 29, count 0 2006.202.00:22:40.99#ibcon#about to read 4, iclass 29, count 0 2006.202.00:22:40.99#ibcon#read 4, iclass 29, count 0 2006.202.00:22:40.99#ibcon#about to read 5, iclass 29, count 0 2006.202.00:22:40.99#ibcon#read 5, iclass 29, count 0 2006.202.00:22:40.99#ibcon#about to read 6, iclass 29, count 0 2006.202.00:22:40.99#ibcon#read 6, iclass 29, count 0 2006.202.00:22:40.99#ibcon#end of sib2, iclass 29, count 0 2006.202.00:22:40.99#ibcon#*after write, iclass 29, count 0 2006.202.00:22:40.99#ibcon#*before return 0, iclass 29, count 0 2006.202.00:22:40.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:40.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:40.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.00:22:40.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.00:22:40.99$vck44/va=3,8 2006.202.00:22:40.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.202.00:22:40.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.202.00:22:40.99#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:40.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:41.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:41.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:41.05#ibcon#enter wrdev, iclass 31, count 2 2006.202.00:22:41.05#ibcon#first serial, iclass 31, count 2 2006.202.00:22:41.05#ibcon#enter sib2, iclass 31, count 2 2006.202.00:22:41.05#ibcon#flushed, iclass 31, count 2 2006.202.00:22:41.05#ibcon#about to write, iclass 31, count 2 2006.202.00:22:41.05#ibcon#wrote, iclass 31, count 2 2006.202.00:22:41.05#ibcon#about to read 3, iclass 31, count 2 2006.202.00:22:41.07#ibcon#read 3, iclass 31, count 2 2006.202.00:22:41.07#ibcon#about to read 4, iclass 31, count 2 2006.202.00:22:41.07#ibcon#read 4, iclass 31, count 2 2006.202.00:22:41.07#ibcon#about to read 5, iclass 31, count 2 2006.202.00:22:41.07#ibcon#read 5, iclass 31, count 2 2006.202.00:22:41.07#ibcon#about to read 6, iclass 31, count 2 2006.202.00:22:41.07#ibcon#read 6, iclass 31, count 2 2006.202.00:22:41.07#ibcon#end of sib2, iclass 31, count 2 2006.202.00:22:41.07#ibcon#*mode == 0, iclass 31, count 2 2006.202.00:22:41.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.202.00:22:41.07#ibcon#[25=AT03-08\r\n] 2006.202.00:22:41.07#ibcon#*before write, iclass 31, count 2 2006.202.00:22:41.07#ibcon#enter sib2, iclass 31, count 2 2006.202.00:22:41.07#ibcon#flushed, iclass 31, count 2 2006.202.00:22:41.07#ibcon#about to write, iclass 31, count 2 2006.202.00:22:41.07#ibcon#wrote, iclass 31, count 2 2006.202.00:22:41.07#ibcon#about to read 3, iclass 31, count 2 2006.202.00:22:41.10#ibcon#read 3, iclass 31, count 2 2006.202.00:22:41.10#ibcon#about to read 4, iclass 31, count 2 2006.202.00:22:41.10#ibcon#read 4, iclass 31, count 2 2006.202.00:22:41.10#ibcon#about to read 5, iclass 31, count 2 2006.202.00:22:41.10#ibcon#read 5, iclass 31, count 2 2006.202.00:22:41.10#ibcon#about to read 6, iclass 31, count 2 2006.202.00:22:41.10#ibcon#read 6, iclass 31, count 2 2006.202.00:22:41.10#ibcon#end of sib2, iclass 31, count 2 2006.202.00:22:41.10#ibcon#*after write, iclass 31, count 2 2006.202.00:22:41.10#ibcon#*before return 0, iclass 31, count 2 2006.202.00:22:41.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:41.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:41.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.202.00:22:41.10#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:41.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:41.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:41.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:41.22#ibcon#enter wrdev, iclass 31, count 0 2006.202.00:22:41.22#ibcon#first serial, iclass 31, count 0 2006.202.00:22:41.22#ibcon#enter sib2, iclass 31, count 0 2006.202.00:22:41.22#ibcon#flushed, iclass 31, count 0 2006.202.00:22:41.22#ibcon#about to write, iclass 31, count 0 2006.202.00:22:41.22#ibcon#wrote, iclass 31, count 0 2006.202.00:22:41.22#ibcon#about to read 3, iclass 31, count 0 2006.202.00:22:41.24#ibcon#read 3, iclass 31, count 0 2006.202.00:22:41.24#ibcon#about to read 4, iclass 31, count 0 2006.202.00:22:41.24#ibcon#read 4, iclass 31, count 0 2006.202.00:22:41.24#ibcon#about to read 5, iclass 31, count 0 2006.202.00:22:41.24#ibcon#read 5, iclass 31, count 0 2006.202.00:22:41.24#ibcon#about to read 6, iclass 31, count 0 2006.202.00:22:41.24#ibcon#read 6, iclass 31, count 0 2006.202.00:22:41.24#ibcon#end of sib2, iclass 31, count 0 2006.202.00:22:41.24#ibcon#*mode == 0, iclass 31, count 0 2006.202.00:22:41.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.00:22:41.24#ibcon#[25=USB\r\n] 2006.202.00:22:41.24#ibcon#*before write, iclass 31, count 0 2006.202.00:22:41.24#ibcon#enter sib2, iclass 31, count 0 2006.202.00:22:41.24#ibcon#flushed, iclass 31, count 0 2006.202.00:22:41.24#ibcon#about to write, iclass 31, count 0 2006.202.00:22:41.24#ibcon#wrote, iclass 31, count 0 2006.202.00:22:41.24#ibcon#about to read 3, iclass 31, count 0 2006.202.00:22:41.27#ibcon#read 3, iclass 31, count 0 2006.202.00:22:41.27#ibcon#about to read 4, iclass 31, count 0 2006.202.00:22:41.27#ibcon#read 4, iclass 31, count 0 2006.202.00:22:41.27#ibcon#about to read 5, iclass 31, count 0 2006.202.00:22:41.27#ibcon#read 5, iclass 31, count 0 2006.202.00:22:41.27#ibcon#about to read 6, iclass 31, count 0 2006.202.00:22:41.27#ibcon#read 6, iclass 31, count 0 2006.202.00:22:41.27#ibcon#end of sib2, iclass 31, count 0 2006.202.00:22:41.27#ibcon#*after write, iclass 31, count 0 2006.202.00:22:41.27#ibcon#*before return 0, iclass 31, count 0 2006.202.00:22:41.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:41.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:41.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.00:22:41.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.00:22:41.27$vck44/valo=4,624.99 2006.202.00:22:41.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.00:22:41.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.00:22:41.27#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:41.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:41.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:41.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:41.27#ibcon#enter wrdev, iclass 33, count 0 2006.202.00:22:41.27#ibcon#first serial, iclass 33, count 0 2006.202.00:22:41.27#ibcon#enter sib2, iclass 33, count 0 2006.202.00:22:41.27#ibcon#flushed, iclass 33, count 0 2006.202.00:22:41.27#ibcon#about to write, iclass 33, count 0 2006.202.00:22:41.27#ibcon#wrote, iclass 33, count 0 2006.202.00:22:41.27#ibcon#about to read 3, iclass 33, count 0 2006.202.00:22:41.29#ibcon#read 3, iclass 33, count 0 2006.202.00:22:41.29#ibcon#about to read 4, iclass 33, count 0 2006.202.00:22:41.29#ibcon#read 4, iclass 33, count 0 2006.202.00:22:41.29#ibcon#about to read 5, iclass 33, count 0 2006.202.00:22:41.29#ibcon#read 5, iclass 33, count 0 2006.202.00:22:41.29#ibcon#about to read 6, iclass 33, count 0 2006.202.00:22:41.29#ibcon#read 6, iclass 33, count 0 2006.202.00:22:41.29#ibcon#end of sib2, iclass 33, count 0 2006.202.00:22:41.29#ibcon#*mode == 0, iclass 33, count 0 2006.202.00:22:41.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.00:22:41.29#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.00:22:41.29#ibcon#*before write, iclass 33, count 0 2006.202.00:22:41.29#ibcon#enter sib2, iclass 33, count 0 2006.202.00:22:41.29#ibcon#flushed, iclass 33, count 0 2006.202.00:22:41.29#ibcon#about to write, iclass 33, count 0 2006.202.00:22:41.29#ibcon#wrote, iclass 33, count 0 2006.202.00:22:41.29#ibcon#about to read 3, iclass 33, count 0 2006.202.00:22:41.33#ibcon#read 3, iclass 33, count 0 2006.202.00:22:41.33#ibcon#about to read 4, iclass 33, count 0 2006.202.00:22:41.33#ibcon#read 4, iclass 33, count 0 2006.202.00:22:41.33#ibcon#about to read 5, iclass 33, count 0 2006.202.00:22:41.33#ibcon#read 5, iclass 33, count 0 2006.202.00:22:41.33#ibcon#about to read 6, iclass 33, count 0 2006.202.00:22:41.33#ibcon#read 6, iclass 33, count 0 2006.202.00:22:41.33#ibcon#end of sib2, iclass 33, count 0 2006.202.00:22:41.33#ibcon#*after write, iclass 33, count 0 2006.202.00:22:41.33#ibcon#*before return 0, iclass 33, count 0 2006.202.00:22:41.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:41.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:41.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.00:22:41.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.00:22:41.33$vck44/va=4,7 2006.202.00:22:41.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.202.00:22:41.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.202.00:22:41.33#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:41.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:41.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:41.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:41.39#ibcon#enter wrdev, iclass 35, count 2 2006.202.00:22:41.39#ibcon#first serial, iclass 35, count 2 2006.202.00:22:41.39#ibcon#enter sib2, iclass 35, count 2 2006.202.00:22:41.39#ibcon#flushed, iclass 35, count 2 2006.202.00:22:41.39#ibcon#about to write, iclass 35, count 2 2006.202.00:22:41.39#ibcon#wrote, iclass 35, count 2 2006.202.00:22:41.39#ibcon#about to read 3, iclass 35, count 2 2006.202.00:22:41.41#ibcon#read 3, iclass 35, count 2 2006.202.00:22:41.41#ibcon#about to read 4, iclass 35, count 2 2006.202.00:22:41.41#ibcon#read 4, iclass 35, count 2 2006.202.00:22:41.41#ibcon#about to read 5, iclass 35, count 2 2006.202.00:22:41.41#ibcon#read 5, iclass 35, count 2 2006.202.00:22:41.41#ibcon#about to read 6, iclass 35, count 2 2006.202.00:22:41.41#ibcon#read 6, iclass 35, count 2 2006.202.00:22:41.41#ibcon#end of sib2, iclass 35, count 2 2006.202.00:22:41.41#ibcon#*mode == 0, iclass 35, count 2 2006.202.00:22:41.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.202.00:22:41.41#ibcon#[25=AT04-07\r\n] 2006.202.00:22:41.41#ibcon#*before write, iclass 35, count 2 2006.202.00:22:41.41#ibcon#enter sib2, iclass 35, count 2 2006.202.00:22:41.41#ibcon#flushed, iclass 35, count 2 2006.202.00:22:41.41#ibcon#about to write, iclass 35, count 2 2006.202.00:22:41.41#ibcon#wrote, iclass 35, count 2 2006.202.00:22:41.41#ibcon#about to read 3, iclass 35, count 2 2006.202.00:22:41.44#ibcon#read 3, iclass 35, count 2 2006.202.00:22:41.44#ibcon#about to read 4, iclass 35, count 2 2006.202.00:22:41.44#ibcon#read 4, iclass 35, count 2 2006.202.00:22:41.44#ibcon#about to read 5, iclass 35, count 2 2006.202.00:22:41.44#ibcon#read 5, iclass 35, count 2 2006.202.00:22:41.44#ibcon#about to read 6, iclass 35, count 2 2006.202.00:22:41.44#ibcon#read 6, iclass 35, count 2 2006.202.00:22:41.44#ibcon#end of sib2, iclass 35, count 2 2006.202.00:22:41.44#ibcon#*after write, iclass 35, count 2 2006.202.00:22:41.44#ibcon#*before return 0, iclass 35, count 2 2006.202.00:22:41.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:41.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:41.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.202.00:22:41.44#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:41.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:41.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:41.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:41.56#ibcon#enter wrdev, iclass 35, count 0 2006.202.00:22:41.56#ibcon#first serial, iclass 35, count 0 2006.202.00:22:41.56#ibcon#enter sib2, iclass 35, count 0 2006.202.00:22:41.56#ibcon#flushed, iclass 35, count 0 2006.202.00:22:41.56#ibcon#about to write, iclass 35, count 0 2006.202.00:22:41.56#ibcon#wrote, iclass 35, count 0 2006.202.00:22:41.56#ibcon#about to read 3, iclass 35, count 0 2006.202.00:22:41.58#ibcon#read 3, iclass 35, count 0 2006.202.00:22:41.58#ibcon#about to read 4, iclass 35, count 0 2006.202.00:22:41.58#ibcon#read 4, iclass 35, count 0 2006.202.00:22:41.58#ibcon#about to read 5, iclass 35, count 0 2006.202.00:22:41.58#ibcon#read 5, iclass 35, count 0 2006.202.00:22:41.58#ibcon#about to read 6, iclass 35, count 0 2006.202.00:22:41.58#ibcon#read 6, iclass 35, count 0 2006.202.00:22:41.58#ibcon#end of sib2, iclass 35, count 0 2006.202.00:22:41.58#ibcon#*mode == 0, iclass 35, count 0 2006.202.00:22:41.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.00:22:41.58#ibcon#[25=USB\r\n] 2006.202.00:22:41.58#ibcon#*before write, iclass 35, count 0 2006.202.00:22:41.58#ibcon#enter sib2, iclass 35, count 0 2006.202.00:22:41.58#ibcon#flushed, iclass 35, count 0 2006.202.00:22:41.58#ibcon#about to write, iclass 35, count 0 2006.202.00:22:41.58#ibcon#wrote, iclass 35, count 0 2006.202.00:22:41.58#ibcon#about to read 3, iclass 35, count 0 2006.202.00:22:41.61#ibcon#read 3, iclass 35, count 0 2006.202.00:22:41.61#ibcon#about to read 4, iclass 35, count 0 2006.202.00:22:41.61#ibcon#read 4, iclass 35, count 0 2006.202.00:22:41.61#ibcon#about to read 5, iclass 35, count 0 2006.202.00:22:41.61#ibcon#read 5, iclass 35, count 0 2006.202.00:22:41.61#ibcon#about to read 6, iclass 35, count 0 2006.202.00:22:41.61#ibcon#read 6, iclass 35, count 0 2006.202.00:22:41.61#ibcon#end of sib2, iclass 35, count 0 2006.202.00:22:41.61#ibcon#*after write, iclass 35, count 0 2006.202.00:22:41.61#ibcon#*before return 0, iclass 35, count 0 2006.202.00:22:41.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:41.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:41.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.00:22:41.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.00:22:41.61$vck44/valo=5,734.99 2006.202.00:22:41.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.202.00:22:41.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.202.00:22:41.61#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:41.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:41.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:41.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:41.61#ibcon#enter wrdev, iclass 37, count 0 2006.202.00:22:41.61#ibcon#first serial, iclass 37, count 0 2006.202.00:22:41.61#ibcon#enter sib2, iclass 37, count 0 2006.202.00:22:41.61#ibcon#flushed, iclass 37, count 0 2006.202.00:22:41.61#ibcon#about to write, iclass 37, count 0 2006.202.00:22:41.61#ibcon#wrote, iclass 37, count 0 2006.202.00:22:41.61#ibcon#about to read 3, iclass 37, count 0 2006.202.00:22:41.63#ibcon#read 3, iclass 37, count 0 2006.202.00:22:41.63#ibcon#about to read 4, iclass 37, count 0 2006.202.00:22:41.63#ibcon#read 4, iclass 37, count 0 2006.202.00:22:41.63#ibcon#about to read 5, iclass 37, count 0 2006.202.00:22:41.63#ibcon#read 5, iclass 37, count 0 2006.202.00:22:41.63#ibcon#about to read 6, iclass 37, count 0 2006.202.00:22:41.63#ibcon#read 6, iclass 37, count 0 2006.202.00:22:41.63#ibcon#end of sib2, iclass 37, count 0 2006.202.00:22:41.63#ibcon#*mode == 0, iclass 37, count 0 2006.202.00:22:41.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.00:22:41.63#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.00:22:41.63#ibcon#*before write, iclass 37, count 0 2006.202.00:22:41.63#ibcon#enter sib2, iclass 37, count 0 2006.202.00:22:41.63#ibcon#flushed, iclass 37, count 0 2006.202.00:22:41.63#ibcon#about to write, iclass 37, count 0 2006.202.00:22:41.63#ibcon#wrote, iclass 37, count 0 2006.202.00:22:41.63#ibcon#about to read 3, iclass 37, count 0 2006.202.00:22:41.67#ibcon#read 3, iclass 37, count 0 2006.202.00:22:41.67#ibcon#about to read 4, iclass 37, count 0 2006.202.00:22:41.67#ibcon#read 4, iclass 37, count 0 2006.202.00:22:41.67#ibcon#about to read 5, iclass 37, count 0 2006.202.00:22:41.67#ibcon#read 5, iclass 37, count 0 2006.202.00:22:41.67#ibcon#about to read 6, iclass 37, count 0 2006.202.00:22:41.67#ibcon#read 6, iclass 37, count 0 2006.202.00:22:41.67#ibcon#end of sib2, iclass 37, count 0 2006.202.00:22:41.67#ibcon#*after write, iclass 37, count 0 2006.202.00:22:41.67#ibcon#*before return 0, iclass 37, count 0 2006.202.00:22:41.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:41.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:41.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.00:22:41.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.00:22:41.67$vck44/va=5,4 2006.202.00:22:41.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.202.00:22:41.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.202.00:22:41.67#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:41.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:41.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:41.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:41.73#ibcon#enter wrdev, iclass 39, count 2 2006.202.00:22:41.73#ibcon#first serial, iclass 39, count 2 2006.202.00:22:41.73#ibcon#enter sib2, iclass 39, count 2 2006.202.00:22:41.73#ibcon#flushed, iclass 39, count 2 2006.202.00:22:41.73#ibcon#about to write, iclass 39, count 2 2006.202.00:22:41.73#ibcon#wrote, iclass 39, count 2 2006.202.00:22:41.73#ibcon#about to read 3, iclass 39, count 2 2006.202.00:22:41.75#ibcon#read 3, iclass 39, count 2 2006.202.00:22:41.75#ibcon#about to read 4, iclass 39, count 2 2006.202.00:22:41.75#ibcon#read 4, iclass 39, count 2 2006.202.00:22:41.75#ibcon#about to read 5, iclass 39, count 2 2006.202.00:22:41.75#ibcon#read 5, iclass 39, count 2 2006.202.00:22:41.75#ibcon#about to read 6, iclass 39, count 2 2006.202.00:22:41.75#ibcon#read 6, iclass 39, count 2 2006.202.00:22:41.75#ibcon#end of sib2, iclass 39, count 2 2006.202.00:22:41.75#ibcon#*mode == 0, iclass 39, count 2 2006.202.00:22:41.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.202.00:22:41.75#ibcon#[25=AT05-04\r\n] 2006.202.00:22:41.75#ibcon#*before write, iclass 39, count 2 2006.202.00:22:41.75#ibcon#enter sib2, iclass 39, count 2 2006.202.00:22:41.75#ibcon#flushed, iclass 39, count 2 2006.202.00:22:41.75#ibcon#about to write, iclass 39, count 2 2006.202.00:22:41.75#ibcon#wrote, iclass 39, count 2 2006.202.00:22:41.75#ibcon#about to read 3, iclass 39, count 2 2006.202.00:22:41.78#ibcon#read 3, iclass 39, count 2 2006.202.00:22:41.78#ibcon#about to read 4, iclass 39, count 2 2006.202.00:22:41.78#ibcon#read 4, iclass 39, count 2 2006.202.00:22:41.78#ibcon#about to read 5, iclass 39, count 2 2006.202.00:22:41.78#ibcon#read 5, iclass 39, count 2 2006.202.00:22:41.78#ibcon#about to read 6, iclass 39, count 2 2006.202.00:22:41.78#ibcon#read 6, iclass 39, count 2 2006.202.00:22:41.78#ibcon#end of sib2, iclass 39, count 2 2006.202.00:22:41.78#ibcon#*after write, iclass 39, count 2 2006.202.00:22:41.78#ibcon#*before return 0, iclass 39, count 2 2006.202.00:22:41.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:41.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:41.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.202.00:22:41.78#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:41.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:41.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:41.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:41.90#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:22:41.90#ibcon#first serial, iclass 39, count 0 2006.202.00:22:41.90#ibcon#enter sib2, iclass 39, count 0 2006.202.00:22:41.90#ibcon#flushed, iclass 39, count 0 2006.202.00:22:41.90#ibcon#about to write, iclass 39, count 0 2006.202.00:22:41.90#ibcon#wrote, iclass 39, count 0 2006.202.00:22:41.90#ibcon#about to read 3, iclass 39, count 0 2006.202.00:22:41.92#ibcon#read 3, iclass 39, count 0 2006.202.00:22:41.92#ibcon#about to read 4, iclass 39, count 0 2006.202.00:22:41.92#ibcon#read 4, iclass 39, count 0 2006.202.00:22:41.92#ibcon#about to read 5, iclass 39, count 0 2006.202.00:22:41.92#ibcon#read 5, iclass 39, count 0 2006.202.00:22:41.92#ibcon#about to read 6, iclass 39, count 0 2006.202.00:22:41.92#ibcon#read 6, iclass 39, count 0 2006.202.00:22:41.92#ibcon#end of sib2, iclass 39, count 0 2006.202.00:22:41.92#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:22:41.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:22:41.92#ibcon#[25=USB\r\n] 2006.202.00:22:41.92#ibcon#*before write, iclass 39, count 0 2006.202.00:22:41.92#ibcon#enter sib2, iclass 39, count 0 2006.202.00:22:41.92#ibcon#flushed, iclass 39, count 0 2006.202.00:22:41.92#ibcon#about to write, iclass 39, count 0 2006.202.00:22:41.92#ibcon#wrote, iclass 39, count 0 2006.202.00:22:41.92#ibcon#about to read 3, iclass 39, count 0 2006.202.00:22:41.95#ibcon#read 3, iclass 39, count 0 2006.202.00:22:41.95#ibcon#about to read 4, iclass 39, count 0 2006.202.00:22:41.95#ibcon#read 4, iclass 39, count 0 2006.202.00:22:41.95#ibcon#about to read 5, iclass 39, count 0 2006.202.00:22:41.95#ibcon#read 5, iclass 39, count 0 2006.202.00:22:41.95#ibcon#about to read 6, iclass 39, count 0 2006.202.00:22:41.95#ibcon#read 6, iclass 39, count 0 2006.202.00:22:41.95#ibcon#end of sib2, iclass 39, count 0 2006.202.00:22:41.95#ibcon#*after write, iclass 39, count 0 2006.202.00:22:41.95#ibcon#*before return 0, iclass 39, count 0 2006.202.00:22:41.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:41.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:41.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:22:41.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:22:41.95$vck44/valo=6,814.99 2006.202.00:22:41.95#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.202.00:22:41.95#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.202.00:22:41.95#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:41.95#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:41.95#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:41.95#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:41.95#ibcon#enter wrdev, iclass 2, count 0 2006.202.00:22:41.95#ibcon#first serial, iclass 2, count 0 2006.202.00:22:41.95#ibcon#enter sib2, iclass 2, count 0 2006.202.00:22:41.95#ibcon#flushed, iclass 2, count 0 2006.202.00:22:41.95#ibcon#about to write, iclass 2, count 0 2006.202.00:22:41.95#ibcon#wrote, iclass 2, count 0 2006.202.00:22:41.95#ibcon#about to read 3, iclass 2, count 0 2006.202.00:22:41.97#ibcon#read 3, iclass 2, count 0 2006.202.00:22:41.97#ibcon#about to read 4, iclass 2, count 0 2006.202.00:22:41.97#ibcon#read 4, iclass 2, count 0 2006.202.00:22:41.97#ibcon#about to read 5, iclass 2, count 0 2006.202.00:22:41.97#ibcon#read 5, iclass 2, count 0 2006.202.00:22:41.97#ibcon#about to read 6, iclass 2, count 0 2006.202.00:22:41.97#ibcon#read 6, iclass 2, count 0 2006.202.00:22:41.97#ibcon#end of sib2, iclass 2, count 0 2006.202.00:22:41.97#ibcon#*mode == 0, iclass 2, count 0 2006.202.00:22:41.97#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.00:22:41.97#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.00:22:41.97#ibcon#*before write, iclass 2, count 0 2006.202.00:22:41.97#ibcon#enter sib2, iclass 2, count 0 2006.202.00:22:41.97#ibcon#flushed, iclass 2, count 0 2006.202.00:22:41.97#ibcon#about to write, iclass 2, count 0 2006.202.00:22:41.97#ibcon#wrote, iclass 2, count 0 2006.202.00:22:41.97#ibcon#about to read 3, iclass 2, count 0 2006.202.00:22:42.01#ibcon#read 3, iclass 2, count 0 2006.202.00:22:42.01#ibcon#about to read 4, iclass 2, count 0 2006.202.00:22:42.01#ibcon#read 4, iclass 2, count 0 2006.202.00:22:42.01#ibcon#about to read 5, iclass 2, count 0 2006.202.00:22:42.01#ibcon#read 5, iclass 2, count 0 2006.202.00:22:42.01#ibcon#about to read 6, iclass 2, count 0 2006.202.00:22:42.01#ibcon#read 6, iclass 2, count 0 2006.202.00:22:42.01#ibcon#end of sib2, iclass 2, count 0 2006.202.00:22:42.01#ibcon#*after write, iclass 2, count 0 2006.202.00:22:42.01#ibcon#*before return 0, iclass 2, count 0 2006.202.00:22:42.01#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:42.01#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:42.01#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.00:22:42.01#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.00:22:42.01$vck44/va=6,5 2006.202.00:22:42.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.202.00:22:42.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.202.00:22:42.01#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:42.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:42.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:42.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:42.07#ibcon#enter wrdev, iclass 5, count 2 2006.202.00:22:42.07#ibcon#first serial, iclass 5, count 2 2006.202.00:22:42.07#ibcon#enter sib2, iclass 5, count 2 2006.202.00:22:42.07#ibcon#flushed, iclass 5, count 2 2006.202.00:22:42.07#ibcon#about to write, iclass 5, count 2 2006.202.00:22:42.07#ibcon#wrote, iclass 5, count 2 2006.202.00:22:42.07#ibcon#about to read 3, iclass 5, count 2 2006.202.00:22:42.09#ibcon#read 3, iclass 5, count 2 2006.202.00:22:42.09#ibcon#about to read 4, iclass 5, count 2 2006.202.00:22:42.09#ibcon#read 4, iclass 5, count 2 2006.202.00:22:42.09#ibcon#about to read 5, iclass 5, count 2 2006.202.00:22:42.09#ibcon#read 5, iclass 5, count 2 2006.202.00:22:42.09#ibcon#about to read 6, iclass 5, count 2 2006.202.00:22:42.09#ibcon#read 6, iclass 5, count 2 2006.202.00:22:42.09#ibcon#end of sib2, iclass 5, count 2 2006.202.00:22:42.09#ibcon#*mode == 0, iclass 5, count 2 2006.202.00:22:42.09#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.202.00:22:42.09#ibcon#[25=AT06-05\r\n] 2006.202.00:22:42.09#ibcon#*before write, iclass 5, count 2 2006.202.00:22:42.09#ibcon#enter sib2, iclass 5, count 2 2006.202.00:22:42.09#ibcon#flushed, iclass 5, count 2 2006.202.00:22:42.09#ibcon#about to write, iclass 5, count 2 2006.202.00:22:42.09#ibcon#wrote, iclass 5, count 2 2006.202.00:22:42.09#ibcon#about to read 3, iclass 5, count 2 2006.202.00:22:42.12#ibcon#read 3, iclass 5, count 2 2006.202.00:22:42.12#ibcon#about to read 4, iclass 5, count 2 2006.202.00:22:42.12#ibcon#read 4, iclass 5, count 2 2006.202.00:22:42.12#ibcon#about to read 5, iclass 5, count 2 2006.202.00:22:42.12#ibcon#read 5, iclass 5, count 2 2006.202.00:22:42.12#ibcon#about to read 6, iclass 5, count 2 2006.202.00:22:42.12#ibcon#read 6, iclass 5, count 2 2006.202.00:22:42.12#ibcon#end of sib2, iclass 5, count 2 2006.202.00:22:42.12#ibcon#*after write, iclass 5, count 2 2006.202.00:22:42.12#ibcon#*before return 0, iclass 5, count 2 2006.202.00:22:42.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:42.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:42.12#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.202.00:22:42.12#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:42.12#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:42.24#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:42.24#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:42.24#ibcon#enter wrdev, iclass 5, count 0 2006.202.00:22:42.24#ibcon#first serial, iclass 5, count 0 2006.202.00:22:42.24#ibcon#enter sib2, iclass 5, count 0 2006.202.00:22:42.24#ibcon#flushed, iclass 5, count 0 2006.202.00:22:42.24#ibcon#about to write, iclass 5, count 0 2006.202.00:22:42.24#ibcon#wrote, iclass 5, count 0 2006.202.00:22:42.24#ibcon#about to read 3, iclass 5, count 0 2006.202.00:22:42.26#ibcon#read 3, iclass 5, count 0 2006.202.00:22:42.26#ibcon#about to read 4, iclass 5, count 0 2006.202.00:22:42.26#ibcon#read 4, iclass 5, count 0 2006.202.00:22:42.26#ibcon#about to read 5, iclass 5, count 0 2006.202.00:22:42.26#ibcon#read 5, iclass 5, count 0 2006.202.00:22:42.26#ibcon#about to read 6, iclass 5, count 0 2006.202.00:22:42.26#ibcon#read 6, iclass 5, count 0 2006.202.00:22:42.26#ibcon#end of sib2, iclass 5, count 0 2006.202.00:22:42.26#ibcon#*mode == 0, iclass 5, count 0 2006.202.00:22:42.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.00:22:42.26#ibcon#[25=USB\r\n] 2006.202.00:22:42.26#ibcon#*before write, iclass 5, count 0 2006.202.00:22:42.26#ibcon#enter sib2, iclass 5, count 0 2006.202.00:22:42.26#ibcon#flushed, iclass 5, count 0 2006.202.00:22:42.26#ibcon#about to write, iclass 5, count 0 2006.202.00:22:42.26#ibcon#wrote, iclass 5, count 0 2006.202.00:22:42.26#ibcon#about to read 3, iclass 5, count 0 2006.202.00:22:42.29#ibcon#read 3, iclass 5, count 0 2006.202.00:22:42.29#ibcon#about to read 4, iclass 5, count 0 2006.202.00:22:42.29#ibcon#read 4, iclass 5, count 0 2006.202.00:22:42.29#ibcon#about to read 5, iclass 5, count 0 2006.202.00:22:42.29#ibcon#read 5, iclass 5, count 0 2006.202.00:22:42.29#ibcon#about to read 6, iclass 5, count 0 2006.202.00:22:42.29#ibcon#read 6, iclass 5, count 0 2006.202.00:22:42.29#ibcon#end of sib2, iclass 5, count 0 2006.202.00:22:42.29#ibcon#*after write, iclass 5, count 0 2006.202.00:22:42.29#ibcon#*before return 0, iclass 5, count 0 2006.202.00:22:42.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:42.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:42.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.00:22:42.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.00:22:42.29$vck44/valo=7,864.99 2006.202.00:22:42.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.00:22:42.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.00:22:42.29#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:42.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:42.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:42.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:42.29#ibcon#enter wrdev, iclass 7, count 0 2006.202.00:22:42.29#ibcon#first serial, iclass 7, count 0 2006.202.00:22:42.29#ibcon#enter sib2, iclass 7, count 0 2006.202.00:22:42.29#ibcon#flushed, iclass 7, count 0 2006.202.00:22:42.29#ibcon#about to write, iclass 7, count 0 2006.202.00:22:42.29#ibcon#wrote, iclass 7, count 0 2006.202.00:22:42.29#ibcon#about to read 3, iclass 7, count 0 2006.202.00:22:42.31#ibcon#read 3, iclass 7, count 0 2006.202.00:22:42.31#ibcon#about to read 4, iclass 7, count 0 2006.202.00:22:42.31#ibcon#read 4, iclass 7, count 0 2006.202.00:22:42.31#ibcon#about to read 5, iclass 7, count 0 2006.202.00:22:42.31#ibcon#read 5, iclass 7, count 0 2006.202.00:22:42.31#ibcon#about to read 6, iclass 7, count 0 2006.202.00:22:42.31#ibcon#read 6, iclass 7, count 0 2006.202.00:22:42.31#ibcon#end of sib2, iclass 7, count 0 2006.202.00:22:42.31#ibcon#*mode == 0, iclass 7, count 0 2006.202.00:22:42.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.00:22:42.31#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.00:22:42.31#ibcon#*before write, iclass 7, count 0 2006.202.00:22:42.31#ibcon#enter sib2, iclass 7, count 0 2006.202.00:22:42.31#ibcon#flushed, iclass 7, count 0 2006.202.00:22:42.31#ibcon#about to write, iclass 7, count 0 2006.202.00:22:42.31#ibcon#wrote, iclass 7, count 0 2006.202.00:22:42.31#ibcon#about to read 3, iclass 7, count 0 2006.202.00:22:42.35#ibcon#read 3, iclass 7, count 0 2006.202.00:22:42.35#ibcon#about to read 4, iclass 7, count 0 2006.202.00:22:42.35#ibcon#read 4, iclass 7, count 0 2006.202.00:22:42.35#ibcon#about to read 5, iclass 7, count 0 2006.202.00:22:42.35#ibcon#read 5, iclass 7, count 0 2006.202.00:22:42.35#ibcon#about to read 6, iclass 7, count 0 2006.202.00:22:42.35#ibcon#read 6, iclass 7, count 0 2006.202.00:22:42.35#ibcon#end of sib2, iclass 7, count 0 2006.202.00:22:42.35#ibcon#*after write, iclass 7, count 0 2006.202.00:22:42.35#ibcon#*before return 0, iclass 7, count 0 2006.202.00:22:42.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:42.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:42.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.00:22:42.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.00:22:42.35$vck44/va=7,5 2006.202.00:22:42.35#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.202.00:22:42.35#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.202.00:22:42.35#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:42.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:42.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:42.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:42.41#ibcon#enter wrdev, iclass 11, count 2 2006.202.00:22:42.41#ibcon#first serial, iclass 11, count 2 2006.202.00:22:42.41#ibcon#enter sib2, iclass 11, count 2 2006.202.00:22:42.41#ibcon#flushed, iclass 11, count 2 2006.202.00:22:42.41#ibcon#about to write, iclass 11, count 2 2006.202.00:22:42.41#ibcon#wrote, iclass 11, count 2 2006.202.00:22:42.41#ibcon#about to read 3, iclass 11, count 2 2006.202.00:22:42.43#ibcon#read 3, iclass 11, count 2 2006.202.00:22:42.43#ibcon#about to read 4, iclass 11, count 2 2006.202.00:22:42.43#ibcon#read 4, iclass 11, count 2 2006.202.00:22:42.43#ibcon#about to read 5, iclass 11, count 2 2006.202.00:22:42.43#ibcon#read 5, iclass 11, count 2 2006.202.00:22:42.43#ibcon#about to read 6, iclass 11, count 2 2006.202.00:22:42.43#ibcon#read 6, iclass 11, count 2 2006.202.00:22:42.43#ibcon#end of sib2, iclass 11, count 2 2006.202.00:22:42.43#ibcon#*mode == 0, iclass 11, count 2 2006.202.00:22:42.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.202.00:22:42.43#ibcon#[25=AT07-05\r\n] 2006.202.00:22:42.43#ibcon#*before write, iclass 11, count 2 2006.202.00:22:42.43#ibcon#enter sib2, iclass 11, count 2 2006.202.00:22:42.43#ibcon#flushed, iclass 11, count 2 2006.202.00:22:42.43#ibcon#about to write, iclass 11, count 2 2006.202.00:22:42.43#ibcon#wrote, iclass 11, count 2 2006.202.00:22:42.43#ibcon#about to read 3, iclass 11, count 2 2006.202.00:22:42.46#ibcon#read 3, iclass 11, count 2 2006.202.00:22:42.46#ibcon#about to read 4, iclass 11, count 2 2006.202.00:22:42.46#ibcon#read 4, iclass 11, count 2 2006.202.00:22:42.46#ibcon#about to read 5, iclass 11, count 2 2006.202.00:22:42.46#ibcon#read 5, iclass 11, count 2 2006.202.00:22:42.46#ibcon#about to read 6, iclass 11, count 2 2006.202.00:22:42.46#ibcon#read 6, iclass 11, count 2 2006.202.00:22:42.46#ibcon#end of sib2, iclass 11, count 2 2006.202.00:22:42.46#ibcon#*after write, iclass 11, count 2 2006.202.00:22:42.46#ibcon#*before return 0, iclass 11, count 2 2006.202.00:22:42.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:42.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:42.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.202.00:22:42.46#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:42.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:42.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:42.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:42.58#ibcon#enter wrdev, iclass 11, count 0 2006.202.00:22:42.58#ibcon#first serial, iclass 11, count 0 2006.202.00:22:42.58#ibcon#enter sib2, iclass 11, count 0 2006.202.00:22:42.58#ibcon#flushed, iclass 11, count 0 2006.202.00:22:42.58#ibcon#about to write, iclass 11, count 0 2006.202.00:22:42.58#ibcon#wrote, iclass 11, count 0 2006.202.00:22:42.58#ibcon#about to read 3, iclass 11, count 0 2006.202.00:22:42.60#ibcon#read 3, iclass 11, count 0 2006.202.00:22:42.60#ibcon#about to read 4, iclass 11, count 0 2006.202.00:22:42.60#ibcon#read 4, iclass 11, count 0 2006.202.00:22:42.60#ibcon#about to read 5, iclass 11, count 0 2006.202.00:22:42.60#ibcon#read 5, iclass 11, count 0 2006.202.00:22:42.60#ibcon#about to read 6, iclass 11, count 0 2006.202.00:22:42.60#ibcon#read 6, iclass 11, count 0 2006.202.00:22:42.60#ibcon#end of sib2, iclass 11, count 0 2006.202.00:22:42.60#ibcon#*mode == 0, iclass 11, count 0 2006.202.00:22:42.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.00:22:42.60#ibcon#[25=USB\r\n] 2006.202.00:22:42.60#ibcon#*before write, iclass 11, count 0 2006.202.00:22:42.60#ibcon#enter sib2, iclass 11, count 0 2006.202.00:22:42.60#ibcon#flushed, iclass 11, count 0 2006.202.00:22:42.60#ibcon#about to write, iclass 11, count 0 2006.202.00:22:42.60#ibcon#wrote, iclass 11, count 0 2006.202.00:22:42.60#ibcon#about to read 3, iclass 11, count 0 2006.202.00:22:42.63#ibcon#read 3, iclass 11, count 0 2006.202.00:22:42.63#ibcon#about to read 4, iclass 11, count 0 2006.202.00:22:42.63#ibcon#read 4, iclass 11, count 0 2006.202.00:22:42.63#ibcon#about to read 5, iclass 11, count 0 2006.202.00:22:42.63#ibcon#read 5, iclass 11, count 0 2006.202.00:22:42.63#ibcon#about to read 6, iclass 11, count 0 2006.202.00:22:42.63#ibcon#read 6, iclass 11, count 0 2006.202.00:22:42.63#ibcon#end of sib2, iclass 11, count 0 2006.202.00:22:42.63#ibcon#*after write, iclass 11, count 0 2006.202.00:22:42.63#ibcon#*before return 0, iclass 11, count 0 2006.202.00:22:42.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:42.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:42.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.00:22:42.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.00:22:42.63$vck44/valo=8,884.99 2006.202.00:22:42.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.202.00:22:42.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.202.00:22:42.63#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:42.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:42.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:42.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:42.63#ibcon#enter wrdev, iclass 13, count 0 2006.202.00:22:42.63#ibcon#first serial, iclass 13, count 0 2006.202.00:22:42.63#ibcon#enter sib2, iclass 13, count 0 2006.202.00:22:42.63#ibcon#flushed, iclass 13, count 0 2006.202.00:22:42.63#ibcon#about to write, iclass 13, count 0 2006.202.00:22:42.63#ibcon#wrote, iclass 13, count 0 2006.202.00:22:42.63#ibcon#about to read 3, iclass 13, count 0 2006.202.00:22:42.65#ibcon#read 3, iclass 13, count 0 2006.202.00:22:42.65#ibcon#about to read 4, iclass 13, count 0 2006.202.00:22:42.65#ibcon#read 4, iclass 13, count 0 2006.202.00:22:42.65#ibcon#about to read 5, iclass 13, count 0 2006.202.00:22:42.65#ibcon#read 5, iclass 13, count 0 2006.202.00:22:42.65#ibcon#about to read 6, iclass 13, count 0 2006.202.00:22:42.65#ibcon#read 6, iclass 13, count 0 2006.202.00:22:42.65#ibcon#end of sib2, iclass 13, count 0 2006.202.00:22:42.65#ibcon#*mode == 0, iclass 13, count 0 2006.202.00:22:42.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.00:22:42.65#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.00:22:42.65#ibcon#*before write, iclass 13, count 0 2006.202.00:22:42.65#ibcon#enter sib2, iclass 13, count 0 2006.202.00:22:42.65#ibcon#flushed, iclass 13, count 0 2006.202.00:22:42.65#ibcon#about to write, iclass 13, count 0 2006.202.00:22:42.65#ibcon#wrote, iclass 13, count 0 2006.202.00:22:42.65#ibcon#about to read 3, iclass 13, count 0 2006.202.00:22:42.69#ibcon#read 3, iclass 13, count 0 2006.202.00:22:42.69#ibcon#about to read 4, iclass 13, count 0 2006.202.00:22:42.69#ibcon#read 4, iclass 13, count 0 2006.202.00:22:42.69#ibcon#about to read 5, iclass 13, count 0 2006.202.00:22:42.69#ibcon#read 5, iclass 13, count 0 2006.202.00:22:42.69#ibcon#about to read 6, iclass 13, count 0 2006.202.00:22:42.69#ibcon#read 6, iclass 13, count 0 2006.202.00:22:42.69#ibcon#end of sib2, iclass 13, count 0 2006.202.00:22:42.69#ibcon#*after write, iclass 13, count 0 2006.202.00:22:42.69#ibcon#*before return 0, iclass 13, count 0 2006.202.00:22:42.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:42.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:42.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.00:22:42.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.00:22:42.69$vck44/va=8,4 2006.202.00:22:42.69#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.202.00:22:42.69#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.202.00:22:42.69#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:42.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.00:22:42.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.00:22:42.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.00:22:42.75#ibcon#enter wrdev, iclass 15, count 2 2006.202.00:22:42.75#ibcon#first serial, iclass 15, count 2 2006.202.00:22:42.75#ibcon#enter sib2, iclass 15, count 2 2006.202.00:22:42.75#ibcon#flushed, iclass 15, count 2 2006.202.00:22:42.75#ibcon#about to write, iclass 15, count 2 2006.202.00:22:42.75#ibcon#wrote, iclass 15, count 2 2006.202.00:22:42.75#ibcon#about to read 3, iclass 15, count 2 2006.202.00:22:42.77#ibcon#read 3, iclass 15, count 2 2006.202.00:22:42.77#ibcon#about to read 4, iclass 15, count 2 2006.202.00:22:42.77#ibcon#read 4, iclass 15, count 2 2006.202.00:22:42.77#ibcon#about to read 5, iclass 15, count 2 2006.202.00:22:42.77#ibcon#read 5, iclass 15, count 2 2006.202.00:22:42.77#ibcon#about to read 6, iclass 15, count 2 2006.202.00:22:42.77#ibcon#read 6, iclass 15, count 2 2006.202.00:22:42.77#ibcon#end of sib2, iclass 15, count 2 2006.202.00:22:42.77#ibcon#*mode == 0, iclass 15, count 2 2006.202.00:22:42.77#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.202.00:22:42.77#ibcon#[25=AT08-04\r\n] 2006.202.00:22:42.77#ibcon#*before write, iclass 15, count 2 2006.202.00:22:42.77#ibcon#enter sib2, iclass 15, count 2 2006.202.00:22:42.77#ibcon#flushed, iclass 15, count 2 2006.202.00:22:42.77#ibcon#about to write, iclass 15, count 2 2006.202.00:22:42.77#ibcon#wrote, iclass 15, count 2 2006.202.00:22:42.77#ibcon#about to read 3, iclass 15, count 2 2006.202.00:22:42.80#ibcon#read 3, iclass 15, count 2 2006.202.00:22:42.80#ibcon#about to read 4, iclass 15, count 2 2006.202.00:22:42.80#ibcon#read 4, iclass 15, count 2 2006.202.00:22:42.80#ibcon#about to read 5, iclass 15, count 2 2006.202.00:22:42.80#ibcon#read 5, iclass 15, count 2 2006.202.00:22:42.80#ibcon#about to read 6, iclass 15, count 2 2006.202.00:22:42.80#ibcon#read 6, iclass 15, count 2 2006.202.00:22:42.80#ibcon#end of sib2, iclass 15, count 2 2006.202.00:22:42.80#ibcon#*after write, iclass 15, count 2 2006.202.00:22:42.80#ibcon#*before return 0, iclass 15, count 2 2006.202.00:22:42.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.00:22:42.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.202.00:22:42.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.202.00:22:42.80#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:42.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.00:22:42.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.00:22:42.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.00:22:42.92#ibcon#enter wrdev, iclass 15, count 0 2006.202.00:22:42.92#ibcon#first serial, iclass 15, count 0 2006.202.00:22:42.92#ibcon#enter sib2, iclass 15, count 0 2006.202.00:22:42.92#ibcon#flushed, iclass 15, count 0 2006.202.00:22:42.92#ibcon#about to write, iclass 15, count 0 2006.202.00:22:42.92#ibcon#wrote, iclass 15, count 0 2006.202.00:22:42.92#ibcon#about to read 3, iclass 15, count 0 2006.202.00:22:42.94#ibcon#read 3, iclass 15, count 0 2006.202.00:22:42.94#ibcon#about to read 4, iclass 15, count 0 2006.202.00:22:42.94#ibcon#read 4, iclass 15, count 0 2006.202.00:22:42.94#ibcon#about to read 5, iclass 15, count 0 2006.202.00:22:42.94#ibcon#read 5, iclass 15, count 0 2006.202.00:22:42.94#ibcon#about to read 6, iclass 15, count 0 2006.202.00:22:42.94#ibcon#read 6, iclass 15, count 0 2006.202.00:22:42.94#ibcon#end of sib2, iclass 15, count 0 2006.202.00:22:42.94#ibcon#*mode == 0, iclass 15, count 0 2006.202.00:22:42.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.00:22:42.94#ibcon#[25=USB\r\n] 2006.202.00:22:42.94#ibcon#*before write, iclass 15, count 0 2006.202.00:22:42.94#ibcon#enter sib2, iclass 15, count 0 2006.202.00:22:42.94#ibcon#flushed, iclass 15, count 0 2006.202.00:22:42.94#ibcon#about to write, iclass 15, count 0 2006.202.00:22:42.94#ibcon#wrote, iclass 15, count 0 2006.202.00:22:42.94#ibcon#about to read 3, iclass 15, count 0 2006.202.00:22:42.97#ibcon#read 3, iclass 15, count 0 2006.202.00:22:42.97#ibcon#about to read 4, iclass 15, count 0 2006.202.00:22:42.97#ibcon#read 4, iclass 15, count 0 2006.202.00:22:42.97#ibcon#about to read 5, iclass 15, count 0 2006.202.00:22:42.97#ibcon#read 5, iclass 15, count 0 2006.202.00:22:42.97#ibcon#about to read 6, iclass 15, count 0 2006.202.00:22:42.97#ibcon#read 6, iclass 15, count 0 2006.202.00:22:42.97#ibcon#end of sib2, iclass 15, count 0 2006.202.00:22:42.97#ibcon#*after write, iclass 15, count 0 2006.202.00:22:42.97#ibcon#*before return 0, iclass 15, count 0 2006.202.00:22:42.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.00:22:42.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.202.00:22:42.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.00:22:42.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.00:22:42.97$vck44/vblo=1,629.99 2006.202.00:22:42.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.00:22:42.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.00:22:42.97#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:42.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:22:42.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:22:42.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:22:42.97#ibcon#enter wrdev, iclass 17, count 0 2006.202.00:22:42.97#ibcon#first serial, iclass 17, count 0 2006.202.00:22:42.97#ibcon#enter sib2, iclass 17, count 0 2006.202.00:22:42.97#ibcon#flushed, iclass 17, count 0 2006.202.00:22:42.97#ibcon#about to write, iclass 17, count 0 2006.202.00:22:42.97#ibcon#wrote, iclass 17, count 0 2006.202.00:22:42.97#ibcon#about to read 3, iclass 17, count 0 2006.202.00:22:42.99#ibcon#read 3, iclass 17, count 0 2006.202.00:22:42.99#ibcon#about to read 4, iclass 17, count 0 2006.202.00:22:42.99#ibcon#read 4, iclass 17, count 0 2006.202.00:22:42.99#ibcon#about to read 5, iclass 17, count 0 2006.202.00:22:42.99#ibcon#read 5, iclass 17, count 0 2006.202.00:22:42.99#ibcon#about to read 6, iclass 17, count 0 2006.202.00:22:42.99#ibcon#read 6, iclass 17, count 0 2006.202.00:22:42.99#ibcon#end of sib2, iclass 17, count 0 2006.202.00:22:42.99#ibcon#*mode == 0, iclass 17, count 0 2006.202.00:22:42.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.00:22:42.99#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.00:22:42.99#ibcon#*before write, iclass 17, count 0 2006.202.00:22:42.99#ibcon#enter sib2, iclass 17, count 0 2006.202.00:22:42.99#ibcon#flushed, iclass 17, count 0 2006.202.00:22:42.99#ibcon#about to write, iclass 17, count 0 2006.202.00:22:42.99#ibcon#wrote, iclass 17, count 0 2006.202.00:22:42.99#ibcon#about to read 3, iclass 17, count 0 2006.202.00:22:43.03#ibcon#read 3, iclass 17, count 0 2006.202.00:22:43.03#ibcon#about to read 4, iclass 17, count 0 2006.202.00:22:43.03#ibcon#read 4, iclass 17, count 0 2006.202.00:22:43.03#ibcon#about to read 5, iclass 17, count 0 2006.202.00:22:43.03#ibcon#read 5, iclass 17, count 0 2006.202.00:22:43.03#ibcon#about to read 6, iclass 17, count 0 2006.202.00:22:43.03#ibcon#read 6, iclass 17, count 0 2006.202.00:22:43.03#ibcon#end of sib2, iclass 17, count 0 2006.202.00:22:43.03#ibcon#*after write, iclass 17, count 0 2006.202.00:22:43.03#ibcon#*before return 0, iclass 17, count 0 2006.202.00:22:43.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:22:43.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:22:43.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.00:22:43.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.00:22:43.03$vck44/vb=1,4 2006.202.00:22:43.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.202.00:22:43.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.202.00:22:43.03#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:43.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.00:22:43.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.00:22:43.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.00:22:43.03#ibcon#enter wrdev, iclass 19, count 2 2006.202.00:22:43.03#ibcon#first serial, iclass 19, count 2 2006.202.00:22:43.03#ibcon#enter sib2, iclass 19, count 2 2006.202.00:22:43.03#ibcon#flushed, iclass 19, count 2 2006.202.00:22:43.03#ibcon#about to write, iclass 19, count 2 2006.202.00:22:43.03#ibcon#wrote, iclass 19, count 2 2006.202.00:22:43.03#ibcon#about to read 3, iclass 19, count 2 2006.202.00:22:43.05#ibcon#read 3, iclass 19, count 2 2006.202.00:22:43.05#ibcon#about to read 4, iclass 19, count 2 2006.202.00:22:43.05#ibcon#read 4, iclass 19, count 2 2006.202.00:22:43.05#ibcon#about to read 5, iclass 19, count 2 2006.202.00:22:43.05#ibcon#read 5, iclass 19, count 2 2006.202.00:22:43.05#ibcon#about to read 6, iclass 19, count 2 2006.202.00:22:43.05#ibcon#read 6, iclass 19, count 2 2006.202.00:22:43.05#ibcon#end of sib2, iclass 19, count 2 2006.202.00:22:43.05#ibcon#*mode == 0, iclass 19, count 2 2006.202.00:22:43.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.202.00:22:43.05#ibcon#[27=AT01-04\r\n] 2006.202.00:22:43.05#ibcon#*before write, iclass 19, count 2 2006.202.00:22:43.05#ibcon#enter sib2, iclass 19, count 2 2006.202.00:22:43.05#ibcon#flushed, iclass 19, count 2 2006.202.00:22:43.05#ibcon#about to write, iclass 19, count 2 2006.202.00:22:43.05#ibcon#wrote, iclass 19, count 2 2006.202.00:22:43.05#ibcon#about to read 3, iclass 19, count 2 2006.202.00:22:43.08#ibcon#read 3, iclass 19, count 2 2006.202.00:22:43.08#ibcon#about to read 4, iclass 19, count 2 2006.202.00:22:43.08#ibcon#read 4, iclass 19, count 2 2006.202.00:22:43.08#ibcon#about to read 5, iclass 19, count 2 2006.202.00:22:43.08#ibcon#read 5, iclass 19, count 2 2006.202.00:22:43.08#ibcon#about to read 6, iclass 19, count 2 2006.202.00:22:43.08#ibcon#read 6, iclass 19, count 2 2006.202.00:22:43.08#ibcon#end of sib2, iclass 19, count 2 2006.202.00:22:43.08#ibcon#*after write, iclass 19, count 2 2006.202.00:22:43.08#ibcon#*before return 0, iclass 19, count 2 2006.202.00:22:43.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.00:22:43.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.202.00:22:43.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.202.00:22:43.08#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:43.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.00:22:43.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.00:22:43.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.00:22:43.20#ibcon#enter wrdev, iclass 19, count 0 2006.202.00:22:43.20#ibcon#first serial, iclass 19, count 0 2006.202.00:22:43.20#ibcon#enter sib2, iclass 19, count 0 2006.202.00:22:43.20#ibcon#flushed, iclass 19, count 0 2006.202.00:22:43.20#ibcon#about to write, iclass 19, count 0 2006.202.00:22:43.20#ibcon#wrote, iclass 19, count 0 2006.202.00:22:43.20#ibcon#about to read 3, iclass 19, count 0 2006.202.00:22:43.22#ibcon#read 3, iclass 19, count 0 2006.202.00:22:43.22#ibcon#about to read 4, iclass 19, count 0 2006.202.00:22:43.22#ibcon#read 4, iclass 19, count 0 2006.202.00:22:43.22#ibcon#about to read 5, iclass 19, count 0 2006.202.00:22:43.22#ibcon#read 5, iclass 19, count 0 2006.202.00:22:43.22#ibcon#about to read 6, iclass 19, count 0 2006.202.00:22:43.22#ibcon#read 6, iclass 19, count 0 2006.202.00:22:43.22#ibcon#end of sib2, iclass 19, count 0 2006.202.00:22:43.22#ibcon#*mode == 0, iclass 19, count 0 2006.202.00:22:43.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.00:22:43.22#ibcon#[27=USB\r\n] 2006.202.00:22:43.22#ibcon#*before write, iclass 19, count 0 2006.202.00:22:43.22#ibcon#enter sib2, iclass 19, count 0 2006.202.00:22:43.22#ibcon#flushed, iclass 19, count 0 2006.202.00:22:43.22#ibcon#about to write, iclass 19, count 0 2006.202.00:22:43.22#ibcon#wrote, iclass 19, count 0 2006.202.00:22:43.22#ibcon#about to read 3, iclass 19, count 0 2006.202.00:22:43.25#ibcon#read 3, iclass 19, count 0 2006.202.00:22:43.25#ibcon#about to read 4, iclass 19, count 0 2006.202.00:22:43.25#ibcon#read 4, iclass 19, count 0 2006.202.00:22:43.25#ibcon#about to read 5, iclass 19, count 0 2006.202.00:22:43.25#ibcon#read 5, iclass 19, count 0 2006.202.00:22:43.25#ibcon#about to read 6, iclass 19, count 0 2006.202.00:22:43.25#ibcon#read 6, iclass 19, count 0 2006.202.00:22:43.25#ibcon#end of sib2, iclass 19, count 0 2006.202.00:22:43.25#ibcon#*after write, iclass 19, count 0 2006.202.00:22:43.25#ibcon#*before return 0, iclass 19, count 0 2006.202.00:22:43.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.00:22:43.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.202.00:22:43.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.00:22:43.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.00:22:43.25$vck44/vblo=2,634.99 2006.202.00:22:43.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.202.00:22:43.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.202.00:22:43.25#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:43.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:43.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:43.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:43.25#ibcon#enter wrdev, iclass 21, count 0 2006.202.00:22:43.25#ibcon#first serial, iclass 21, count 0 2006.202.00:22:43.25#ibcon#enter sib2, iclass 21, count 0 2006.202.00:22:43.25#ibcon#flushed, iclass 21, count 0 2006.202.00:22:43.25#ibcon#about to write, iclass 21, count 0 2006.202.00:22:43.25#ibcon#wrote, iclass 21, count 0 2006.202.00:22:43.25#ibcon#about to read 3, iclass 21, count 0 2006.202.00:22:43.27#ibcon#read 3, iclass 21, count 0 2006.202.00:22:43.27#ibcon#about to read 4, iclass 21, count 0 2006.202.00:22:43.27#ibcon#read 4, iclass 21, count 0 2006.202.00:22:43.27#ibcon#about to read 5, iclass 21, count 0 2006.202.00:22:43.27#ibcon#read 5, iclass 21, count 0 2006.202.00:22:43.27#ibcon#about to read 6, iclass 21, count 0 2006.202.00:22:43.27#ibcon#read 6, iclass 21, count 0 2006.202.00:22:43.27#ibcon#end of sib2, iclass 21, count 0 2006.202.00:22:43.27#ibcon#*mode == 0, iclass 21, count 0 2006.202.00:22:43.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.00:22:43.27#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.00:22:43.27#ibcon#*before write, iclass 21, count 0 2006.202.00:22:43.27#ibcon#enter sib2, iclass 21, count 0 2006.202.00:22:43.27#ibcon#flushed, iclass 21, count 0 2006.202.00:22:43.27#ibcon#about to write, iclass 21, count 0 2006.202.00:22:43.27#ibcon#wrote, iclass 21, count 0 2006.202.00:22:43.27#ibcon#about to read 3, iclass 21, count 0 2006.202.00:22:43.31#ibcon#read 3, iclass 21, count 0 2006.202.00:22:43.31#ibcon#about to read 4, iclass 21, count 0 2006.202.00:22:43.31#ibcon#read 4, iclass 21, count 0 2006.202.00:22:43.31#ibcon#about to read 5, iclass 21, count 0 2006.202.00:22:43.31#ibcon#read 5, iclass 21, count 0 2006.202.00:22:43.31#ibcon#about to read 6, iclass 21, count 0 2006.202.00:22:43.31#ibcon#read 6, iclass 21, count 0 2006.202.00:22:43.31#ibcon#end of sib2, iclass 21, count 0 2006.202.00:22:43.31#ibcon#*after write, iclass 21, count 0 2006.202.00:22:43.31#ibcon#*before return 0, iclass 21, count 0 2006.202.00:22:43.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:43.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.202.00:22:43.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.00:22:43.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.00:22:43.31$vck44/vb=2,5 2006.202.00:22:43.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.202.00:22:43.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.202.00:22:43.31#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:43.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:43.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:43.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:43.37#ibcon#enter wrdev, iclass 23, count 2 2006.202.00:22:43.37#ibcon#first serial, iclass 23, count 2 2006.202.00:22:43.37#ibcon#enter sib2, iclass 23, count 2 2006.202.00:22:43.37#ibcon#flushed, iclass 23, count 2 2006.202.00:22:43.37#ibcon#about to write, iclass 23, count 2 2006.202.00:22:43.37#ibcon#wrote, iclass 23, count 2 2006.202.00:22:43.37#ibcon#about to read 3, iclass 23, count 2 2006.202.00:22:43.39#ibcon#read 3, iclass 23, count 2 2006.202.00:22:43.39#ibcon#about to read 4, iclass 23, count 2 2006.202.00:22:43.39#ibcon#read 4, iclass 23, count 2 2006.202.00:22:43.39#ibcon#about to read 5, iclass 23, count 2 2006.202.00:22:43.39#ibcon#read 5, iclass 23, count 2 2006.202.00:22:43.39#ibcon#about to read 6, iclass 23, count 2 2006.202.00:22:43.39#ibcon#read 6, iclass 23, count 2 2006.202.00:22:43.39#ibcon#end of sib2, iclass 23, count 2 2006.202.00:22:43.39#ibcon#*mode == 0, iclass 23, count 2 2006.202.00:22:43.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.202.00:22:43.39#ibcon#[27=AT02-05\r\n] 2006.202.00:22:43.39#ibcon#*before write, iclass 23, count 2 2006.202.00:22:43.39#ibcon#enter sib2, iclass 23, count 2 2006.202.00:22:43.39#ibcon#flushed, iclass 23, count 2 2006.202.00:22:43.39#ibcon#about to write, iclass 23, count 2 2006.202.00:22:43.39#ibcon#wrote, iclass 23, count 2 2006.202.00:22:43.39#ibcon#about to read 3, iclass 23, count 2 2006.202.00:22:43.42#ibcon#read 3, iclass 23, count 2 2006.202.00:22:43.42#ibcon#about to read 4, iclass 23, count 2 2006.202.00:22:43.42#ibcon#read 4, iclass 23, count 2 2006.202.00:22:43.42#ibcon#about to read 5, iclass 23, count 2 2006.202.00:22:43.42#ibcon#read 5, iclass 23, count 2 2006.202.00:22:43.42#ibcon#about to read 6, iclass 23, count 2 2006.202.00:22:43.42#ibcon#read 6, iclass 23, count 2 2006.202.00:22:43.42#ibcon#end of sib2, iclass 23, count 2 2006.202.00:22:43.42#ibcon#*after write, iclass 23, count 2 2006.202.00:22:43.42#ibcon#*before return 0, iclass 23, count 2 2006.202.00:22:43.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:43.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.202.00:22:43.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.202.00:22:43.42#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:43.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:43.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:43.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:43.54#ibcon#enter wrdev, iclass 23, count 0 2006.202.00:22:43.54#ibcon#first serial, iclass 23, count 0 2006.202.00:22:43.54#ibcon#enter sib2, iclass 23, count 0 2006.202.00:22:43.54#ibcon#flushed, iclass 23, count 0 2006.202.00:22:43.54#ibcon#about to write, iclass 23, count 0 2006.202.00:22:43.54#ibcon#wrote, iclass 23, count 0 2006.202.00:22:43.54#ibcon#about to read 3, iclass 23, count 0 2006.202.00:22:43.56#ibcon#read 3, iclass 23, count 0 2006.202.00:22:43.56#ibcon#about to read 4, iclass 23, count 0 2006.202.00:22:43.56#ibcon#read 4, iclass 23, count 0 2006.202.00:22:43.56#ibcon#about to read 5, iclass 23, count 0 2006.202.00:22:43.56#ibcon#read 5, iclass 23, count 0 2006.202.00:22:43.56#ibcon#about to read 6, iclass 23, count 0 2006.202.00:22:43.56#ibcon#read 6, iclass 23, count 0 2006.202.00:22:43.56#ibcon#end of sib2, iclass 23, count 0 2006.202.00:22:43.56#ibcon#*mode == 0, iclass 23, count 0 2006.202.00:22:43.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.00:22:43.56#ibcon#[27=USB\r\n] 2006.202.00:22:43.56#ibcon#*before write, iclass 23, count 0 2006.202.00:22:43.56#ibcon#enter sib2, iclass 23, count 0 2006.202.00:22:43.56#ibcon#flushed, iclass 23, count 0 2006.202.00:22:43.56#ibcon#about to write, iclass 23, count 0 2006.202.00:22:43.56#ibcon#wrote, iclass 23, count 0 2006.202.00:22:43.56#ibcon#about to read 3, iclass 23, count 0 2006.202.00:22:43.59#ibcon#read 3, iclass 23, count 0 2006.202.00:22:43.59#ibcon#about to read 4, iclass 23, count 0 2006.202.00:22:43.59#ibcon#read 4, iclass 23, count 0 2006.202.00:22:43.59#ibcon#about to read 5, iclass 23, count 0 2006.202.00:22:43.59#ibcon#read 5, iclass 23, count 0 2006.202.00:22:43.59#ibcon#about to read 6, iclass 23, count 0 2006.202.00:22:43.59#ibcon#read 6, iclass 23, count 0 2006.202.00:22:43.59#ibcon#end of sib2, iclass 23, count 0 2006.202.00:22:43.59#ibcon#*after write, iclass 23, count 0 2006.202.00:22:43.59#ibcon#*before return 0, iclass 23, count 0 2006.202.00:22:43.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:43.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.202.00:22:43.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.00:22:43.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.00:22:43.59$vck44/vblo=3,649.99 2006.202.00:22:43.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.202.00:22:43.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.202.00:22:43.59#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:43.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:43.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:43.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:43.59#ibcon#enter wrdev, iclass 25, count 0 2006.202.00:22:43.59#ibcon#first serial, iclass 25, count 0 2006.202.00:22:43.59#ibcon#enter sib2, iclass 25, count 0 2006.202.00:22:43.59#ibcon#flushed, iclass 25, count 0 2006.202.00:22:43.59#ibcon#about to write, iclass 25, count 0 2006.202.00:22:43.59#ibcon#wrote, iclass 25, count 0 2006.202.00:22:43.59#ibcon#about to read 3, iclass 25, count 0 2006.202.00:22:43.61#ibcon#read 3, iclass 25, count 0 2006.202.00:22:43.61#ibcon#about to read 4, iclass 25, count 0 2006.202.00:22:43.61#ibcon#read 4, iclass 25, count 0 2006.202.00:22:43.61#ibcon#about to read 5, iclass 25, count 0 2006.202.00:22:43.61#ibcon#read 5, iclass 25, count 0 2006.202.00:22:43.61#ibcon#about to read 6, iclass 25, count 0 2006.202.00:22:43.61#ibcon#read 6, iclass 25, count 0 2006.202.00:22:43.61#ibcon#end of sib2, iclass 25, count 0 2006.202.00:22:43.61#ibcon#*mode == 0, iclass 25, count 0 2006.202.00:22:43.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.00:22:43.61#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.00:22:43.61#ibcon#*before write, iclass 25, count 0 2006.202.00:22:43.61#ibcon#enter sib2, iclass 25, count 0 2006.202.00:22:43.61#ibcon#flushed, iclass 25, count 0 2006.202.00:22:43.61#ibcon#about to write, iclass 25, count 0 2006.202.00:22:43.61#ibcon#wrote, iclass 25, count 0 2006.202.00:22:43.61#ibcon#about to read 3, iclass 25, count 0 2006.202.00:22:43.65#ibcon#read 3, iclass 25, count 0 2006.202.00:22:43.65#ibcon#about to read 4, iclass 25, count 0 2006.202.00:22:43.65#ibcon#read 4, iclass 25, count 0 2006.202.00:22:43.65#ibcon#about to read 5, iclass 25, count 0 2006.202.00:22:43.65#ibcon#read 5, iclass 25, count 0 2006.202.00:22:43.65#ibcon#about to read 6, iclass 25, count 0 2006.202.00:22:43.65#ibcon#read 6, iclass 25, count 0 2006.202.00:22:43.65#ibcon#end of sib2, iclass 25, count 0 2006.202.00:22:43.65#ibcon#*after write, iclass 25, count 0 2006.202.00:22:43.65#ibcon#*before return 0, iclass 25, count 0 2006.202.00:22:43.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:43.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.202.00:22:43.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.00:22:43.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.00:22:43.74$vck44/vb=3,4 2006.202.00:22:43.75#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.202.00:22:43.75#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.202.00:22:43.75#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:43.75#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:43.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:43.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:43.75#ibcon#enter wrdev, iclass 27, count 2 2006.202.00:22:43.75#ibcon#first serial, iclass 27, count 2 2006.202.00:22:43.75#ibcon#enter sib2, iclass 27, count 2 2006.202.00:22:43.75#ibcon#flushed, iclass 27, count 2 2006.202.00:22:43.75#ibcon#about to write, iclass 27, count 2 2006.202.00:22:43.75#ibcon#wrote, iclass 27, count 2 2006.202.00:22:43.75#ibcon#about to read 3, iclass 27, count 2 2006.202.00:22:43.77#ibcon#read 3, iclass 27, count 2 2006.202.00:22:43.77#ibcon#about to read 4, iclass 27, count 2 2006.202.00:22:43.77#ibcon#read 4, iclass 27, count 2 2006.202.00:22:43.77#ibcon#about to read 5, iclass 27, count 2 2006.202.00:22:43.77#ibcon#read 5, iclass 27, count 2 2006.202.00:22:43.77#ibcon#about to read 6, iclass 27, count 2 2006.202.00:22:43.77#ibcon#read 6, iclass 27, count 2 2006.202.00:22:43.77#ibcon#end of sib2, iclass 27, count 2 2006.202.00:22:43.77#ibcon#*mode == 0, iclass 27, count 2 2006.202.00:22:43.77#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.202.00:22:43.77#ibcon#[27=AT03-04\r\n] 2006.202.00:22:43.77#ibcon#*before write, iclass 27, count 2 2006.202.00:22:43.77#ibcon#enter sib2, iclass 27, count 2 2006.202.00:22:43.77#ibcon#flushed, iclass 27, count 2 2006.202.00:22:43.77#ibcon#about to write, iclass 27, count 2 2006.202.00:22:43.77#ibcon#wrote, iclass 27, count 2 2006.202.00:22:43.77#ibcon#about to read 3, iclass 27, count 2 2006.202.00:22:43.80#ibcon#read 3, iclass 27, count 2 2006.202.00:22:43.80#ibcon#about to read 4, iclass 27, count 2 2006.202.00:22:43.80#ibcon#read 4, iclass 27, count 2 2006.202.00:22:43.80#ibcon#about to read 5, iclass 27, count 2 2006.202.00:22:43.80#ibcon#read 5, iclass 27, count 2 2006.202.00:22:43.80#ibcon#about to read 6, iclass 27, count 2 2006.202.00:22:43.80#ibcon#read 6, iclass 27, count 2 2006.202.00:22:43.80#ibcon#end of sib2, iclass 27, count 2 2006.202.00:22:43.80#ibcon#*after write, iclass 27, count 2 2006.202.00:22:43.80#ibcon#*before return 0, iclass 27, count 2 2006.202.00:22:43.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:43.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.202.00:22:43.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.202.00:22:43.80#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:43.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:43.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:43.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:43.92#ibcon#enter wrdev, iclass 27, count 0 2006.202.00:22:43.92#ibcon#first serial, iclass 27, count 0 2006.202.00:22:43.92#ibcon#enter sib2, iclass 27, count 0 2006.202.00:22:43.92#ibcon#flushed, iclass 27, count 0 2006.202.00:22:43.92#ibcon#about to write, iclass 27, count 0 2006.202.00:22:43.92#ibcon#wrote, iclass 27, count 0 2006.202.00:22:43.92#ibcon#about to read 3, iclass 27, count 0 2006.202.00:22:43.94#ibcon#read 3, iclass 27, count 0 2006.202.00:22:43.94#ibcon#about to read 4, iclass 27, count 0 2006.202.00:22:43.94#ibcon#read 4, iclass 27, count 0 2006.202.00:22:43.94#ibcon#about to read 5, iclass 27, count 0 2006.202.00:22:43.94#ibcon#read 5, iclass 27, count 0 2006.202.00:22:43.94#ibcon#about to read 6, iclass 27, count 0 2006.202.00:22:43.94#ibcon#read 6, iclass 27, count 0 2006.202.00:22:43.94#ibcon#end of sib2, iclass 27, count 0 2006.202.00:22:43.94#ibcon#*mode == 0, iclass 27, count 0 2006.202.00:22:43.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.00:22:43.94#ibcon#[27=USB\r\n] 2006.202.00:22:43.94#ibcon#*before write, iclass 27, count 0 2006.202.00:22:43.94#ibcon#enter sib2, iclass 27, count 0 2006.202.00:22:43.94#ibcon#flushed, iclass 27, count 0 2006.202.00:22:43.94#ibcon#about to write, iclass 27, count 0 2006.202.00:22:43.94#ibcon#wrote, iclass 27, count 0 2006.202.00:22:43.94#ibcon#about to read 3, iclass 27, count 0 2006.202.00:22:43.97#ibcon#read 3, iclass 27, count 0 2006.202.00:22:43.97#ibcon#about to read 4, iclass 27, count 0 2006.202.00:22:43.97#ibcon#read 4, iclass 27, count 0 2006.202.00:22:43.97#ibcon#about to read 5, iclass 27, count 0 2006.202.00:22:43.97#ibcon#read 5, iclass 27, count 0 2006.202.00:22:43.97#ibcon#about to read 6, iclass 27, count 0 2006.202.00:22:43.97#ibcon#read 6, iclass 27, count 0 2006.202.00:22:43.97#ibcon#end of sib2, iclass 27, count 0 2006.202.00:22:43.97#ibcon#*after write, iclass 27, count 0 2006.202.00:22:43.97#ibcon#*before return 0, iclass 27, count 0 2006.202.00:22:43.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:43.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.202.00:22:43.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.00:22:43.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.00:22:43.97$vck44/vblo=4,679.99 2006.202.00:22:43.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.202.00:22:43.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.202.00:22:43.97#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:43.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:43.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:43.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:43.97#ibcon#enter wrdev, iclass 29, count 0 2006.202.00:22:43.97#ibcon#first serial, iclass 29, count 0 2006.202.00:22:43.97#ibcon#enter sib2, iclass 29, count 0 2006.202.00:22:43.97#ibcon#flushed, iclass 29, count 0 2006.202.00:22:43.97#ibcon#about to write, iclass 29, count 0 2006.202.00:22:43.97#ibcon#wrote, iclass 29, count 0 2006.202.00:22:43.97#ibcon#about to read 3, iclass 29, count 0 2006.202.00:22:43.99#ibcon#read 3, iclass 29, count 0 2006.202.00:22:43.99#ibcon#about to read 4, iclass 29, count 0 2006.202.00:22:43.99#ibcon#read 4, iclass 29, count 0 2006.202.00:22:43.99#ibcon#about to read 5, iclass 29, count 0 2006.202.00:22:43.99#ibcon#read 5, iclass 29, count 0 2006.202.00:22:43.99#ibcon#about to read 6, iclass 29, count 0 2006.202.00:22:43.99#ibcon#read 6, iclass 29, count 0 2006.202.00:22:43.99#ibcon#end of sib2, iclass 29, count 0 2006.202.00:22:43.99#ibcon#*mode == 0, iclass 29, count 0 2006.202.00:22:43.99#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.00:22:43.99#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.00:22:43.99#ibcon#*before write, iclass 29, count 0 2006.202.00:22:43.99#ibcon#enter sib2, iclass 29, count 0 2006.202.00:22:43.99#ibcon#flushed, iclass 29, count 0 2006.202.00:22:43.99#ibcon#about to write, iclass 29, count 0 2006.202.00:22:43.99#ibcon#wrote, iclass 29, count 0 2006.202.00:22:43.99#ibcon#about to read 3, iclass 29, count 0 2006.202.00:22:44.03#ibcon#read 3, iclass 29, count 0 2006.202.00:22:44.03#ibcon#about to read 4, iclass 29, count 0 2006.202.00:22:44.03#ibcon#read 4, iclass 29, count 0 2006.202.00:22:44.03#ibcon#about to read 5, iclass 29, count 0 2006.202.00:22:44.03#ibcon#read 5, iclass 29, count 0 2006.202.00:22:44.03#ibcon#about to read 6, iclass 29, count 0 2006.202.00:22:44.03#ibcon#read 6, iclass 29, count 0 2006.202.00:22:44.03#ibcon#end of sib2, iclass 29, count 0 2006.202.00:22:44.03#ibcon#*after write, iclass 29, count 0 2006.202.00:22:44.03#ibcon#*before return 0, iclass 29, count 0 2006.202.00:22:44.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:44.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.202.00:22:44.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.00:22:44.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.00:22:44.03$vck44/vb=4,5 2006.202.00:22:44.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.202.00:22:44.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.202.00:22:44.03#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:44.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:44.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:44.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:44.09#ibcon#enter wrdev, iclass 31, count 2 2006.202.00:22:44.09#ibcon#first serial, iclass 31, count 2 2006.202.00:22:44.09#ibcon#enter sib2, iclass 31, count 2 2006.202.00:22:44.09#ibcon#flushed, iclass 31, count 2 2006.202.00:22:44.09#ibcon#about to write, iclass 31, count 2 2006.202.00:22:44.09#ibcon#wrote, iclass 31, count 2 2006.202.00:22:44.09#ibcon#about to read 3, iclass 31, count 2 2006.202.00:22:44.11#ibcon#read 3, iclass 31, count 2 2006.202.00:22:44.11#ibcon#about to read 4, iclass 31, count 2 2006.202.00:22:44.11#ibcon#read 4, iclass 31, count 2 2006.202.00:22:44.11#ibcon#about to read 5, iclass 31, count 2 2006.202.00:22:44.11#ibcon#read 5, iclass 31, count 2 2006.202.00:22:44.11#ibcon#about to read 6, iclass 31, count 2 2006.202.00:22:44.11#ibcon#read 6, iclass 31, count 2 2006.202.00:22:44.11#ibcon#end of sib2, iclass 31, count 2 2006.202.00:22:44.11#ibcon#*mode == 0, iclass 31, count 2 2006.202.00:22:44.11#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.202.00:22:44.11#ibcon#[27=AT04-05\r\n] 2006.202.00:22:44.11#ibcon#*before write, iclass 31, count 2 2006.202.00:22:44.11#ibcon#enter sib2, iclass 31, count 2 2006.202.00:22:44.11#ibcon#flushed, iclass 31, count 2 2006.202.00:22:44.11#ibcon#about to write, iclass 31, count 2 2006.202.00:22:44.11#ibcon#wrote, iclass 31, count 2 2006.202.00:22:44.11#ibcon#about to read 3, iclass 31, count 2 2006.202.00:22:44.14#ibcon#read 3, iclass 31, count 2 2006.202.00:22:44.14#ibcon#about to read 4, iclass 31, count 2 2006.202.00:22:44.14#ibcon#read 4, iclass 31, count 2 2006.202.00:22:44.14#ibcon#about to read 5, iclass 31, count 2 2006.202.00:22:44.14#ibcon#read 5, iclass 31, count 2 2006.202.00:22:44.14#ibcon#about to read 6, iclass 31, count 2 2006.202.00:22:44.14#ibcon#read 6, iclass 31, count 2 2006.202.00:22:44.14#ibcon#end of sib2, iclass 31, count 2 2006.202.00:22:44.14#ibcon#*after write, iclass 31, count 2 2006.202.00:22:44.14#ibcon#*before return 0, iclass 31, count 2 2006.202.00:22:44.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:44.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.202.00:22:44.14#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.202.00:22:44.14#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:44.14#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:44.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:44.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:44.26#ibcon#enter wrdev, iclass 31, count 0 2006.202.00:22:44.26#ibcon#first serial, iclass 31, count 0 2006.202.00:22:44.26#ibcon#enter sib2, iclass 31, count 0 2006.202.00:22:44.26#ibcon#flushed, iclass 31, count 0 2006.202.00:22:44.26#ibcon#about to write, iclass 31, count 0 2006.202.00:22:44.26#ibcon#wrote, iclass 31, count 0 2006.202.00:22:44.26#ibcon#about to read 3, iclass 31, count 0 2006.202.00:22:44.28#ibcon#read 3, iclass 31, count 0 2006.202.00:22:44.28#ibcon#about to read 4, iclass 31, count 0 2006.202.00:22:44.28#ibcon#read 4, iclass 31, count 0 2006.202.00:22:44.28#ibcon#about to read 5, iclass 31, count 0 2006.202.00:22:44.28#ibcon#read 5, iclass 31, count 0 2006.202.00:22:44.28#ibcon#about to read 6, iclass 31, count 0 2006.202.00:22:44.28#ibcon#read 6, iclass 31, count 0 2006.202.00:22:44.28#ibcon#end of sib2, iclass 31, count 0 2006.202.00:22:44.28#ibcon#*mode == 0, iclass 31, count 0 2006.202.00:22:44.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.00:22:44.28#ibcon#[27=USB\r\n] 2006.202.00:22:44.28#ibcon#*before write, iclass 31, count 0 2006.202.00:22:44.28#ibcon#enter sib2, iclass 31, count 0 2006.202.00:22:44.28#ibcon#flushed, iclass 31, count 0 2006.202.00:22:44.28#ibcon#about to write, iclass 31, count 0 2006.202.00:22:44.28#ibcon#wrote, iclass 31, count 0 2006.202.00:22:44.28#ibcon#about to read 3, iclass 31, count 0 2006.202.00:22:44.31#ibcon#read 3, iclass 31, count 0 2006.202.00:22:44.31#ibcon#about to read 4, iclass 31, count 0 2006.202.00:22:44.31#ibcon#read 4, iclass 31, count 0 2006.202.00:22:44.31#ibcon#about to read 5, iclass 31, count 0 2006.202.00:22:44.31#ibcon#read 5, iclass 31, count 0 2006.202.00:22:44.31#ibcon#about to read 6, iclass 31, count 0 2006.202.00:22:44.31#ibcon#read 6, iclass 31, count 0 2006.202.00:22:44.31#ibcon#end of sib2, iclass 31, count 0 2006.202.00:22:44.31#ibcon#*after write, iclass 31, count 0 2006.202.00:22:44.31#ibcon#*before return 0, iclass 31, count 0 2006.202.00:22:44.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:44.31#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.202.00:22:44.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.00:22:44.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.00:22:44.31$vck44/vblo=5,709.99 2006.202.00:22:44.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.00:22:44.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.00:22:44.31#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:44.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:44.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:44.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:44.31#ibcon#enter wrdev, iclass 33, count 0 2006.202.00:22:44.31#ibcon#first serial, iclass 33, count 0 2006.202.00:22:44.31#ibcon#enter sib2, iclass 33, count 0 2006.202.00:22:44.31#ibcon#flushed, iclass 33, count 0 2006.202.00:22:44.31#ibcon#about to write, iclass 33, count 0 2006.202.00:22:44.31#ibcon#wrote, iclass 33, count 0 2006.202.00:22:44.31#ibcon#about to read 3, iclass 33, count 0 2006.202.00:22:44.33#ibcon#read 3, iclass 33, count 0 2006.202.00:22:44.33#ibcon#about to read 4, iclass 33, count 0 2006.202.00:22:44.33#ibcon#read 4, iclass 33, count 0 2006.202.00:22:44.33#ibcon#about to read 5, iclass 33, count 0 2006.202.00:22:44.33#ibcon#read 5, iclass 33, count 0 2006.202.00:22:44.33#ibcon#about to read 6, iclass 33, count 0 2006.202.00:22:44.33#ibcon#read 6, iclass 33, count 0 2006.202.00:22:44.33#ibcon#end of sib2, iclass 33, count 0 2006.202.00:22:44.33#ibcon#*mode == 0, iclass 33, count 0 2006.202.00:22:44.33#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.00:22:44.33#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.00:22:44.33#ibcon#*before write, iclass 33, count 0 2006.202.00:22:44.33#ibcon#enter sib2, iclass 33, count 0 2006.202.00:22:44.33#ibcon#flushed, iclass 33, count 0 2006.202.00:22:44.33#ibcon#about to write, iclass 33, count 0 2006.202.00:22:44.33#ibcon#wrote, iclass 33, count 0 2006.202.00:22:44.33#ibcon#about to read 3, iclass 33, count 0 2006.202.00:22:44.37#ibcon#read 3, iclass 33, count 0 2006.202.00:22:44.37#ibcon#about to read 4, iclass 33, count 0 2006.202.00:22:44.37#ibcon#read 4, iclass 33, count 0 2006.202.00:22:44.37#ibcon#about to read 5, iclass 33, count 0 2006.202.00:22:44.37#ibcon#read 5, iclass 33, count 0 2006.202.00:22:44.37#ibcon#about to read 6, iclass 33, count 0 2006.202.00:22:44.37#ibcon#read 6, iclass 33, count 0 2006.202.00:22:44.37#ibcon#end of sib2, iclass 33, count 0 2006.202.00:22:44.37#ibcon#*after write, iclass 33, count 0 2006.202.00:22:44.37#ibcon#*before return 0, iclass 33, count 0 2006.202.00:22:44.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:44.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:22:44.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.00:22:44.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.00:22:44.37$vck44/vb=5,4 2006.202.00:22:44.37#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.202.00:22:44.37#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.202.00:22:44.37#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:44.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:44.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:44.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:44.43#ibcon#enter wrdev, iclass 35, count 2 2006.202.00:22:44.43#ibcon#first serial, iclass 35, count 2 2006.202.00:22:44.43#ibcon#enter sib2, iclass 35, count 2 2006.202.00:22:44.43#ibcon#flushed, iclass 35, count 2 2006.202.00:22:44.43#ibcon#about to write, iclass 35, count 2 2006.202.00:22:44.43#ibcon#wrote, iclass 35, count 2 2006.202.00:22:44.43#ibcon#about to read 3, iclass 35, count 2 2006.202.00:22:44.45#ibcon#read 3, iclass 35, count 2 2006.202.00:22:44.45#ibcon#about to read 4, iclass 35, count 2 2006.202.00:22:44.45#ibcon#read 4, iclass 35, count 2 2006.202.00:22:44.45#ibcon#about to read 5, iclass 35, count 2 2006.202.00:22:44.45#ibcon#read 5, iclass 35, count 2 2006.202.00:22:44.45#ibcon#about to read 6, iclass 35, count 2 2006.202.00:22:44.45#ibcon#read 6, iclass 35, count 2 2006.202.00:22:44.45#ibcon#end of sib2, iclass 35, count 2 2006.202.00:22:44.45#ibcon#*mode == 0, iclass 35, count 2 2006.202.00:22:44.45#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.202.00:22:44.45#ibcon#[27=AT05-04\r\n] 2006.202.00:22:44.45#ibcon#*before write, iclass 35, count 2 2006.202.00:22:44.45#ibcon#enter sib2, iclass 35, count 2 2006.202.00:22:44.45#ibcon#flushed, iclass 35, count 2 2006.202.00:22:44.45#ibcon#about to write, iclass 35, count 2 2006.202.00:22:44.45#ibcon#wrote, iclass 35, count 2 2006.202.00:22:44.45#ibcon#about to read 3, iclass 35, count 2 2006.202.00:22:44.48#ibcon#read 3, iclass 35, count 2 2006.202.00:22:44.48#ibcon#about to read 4, iclass 35, count 2 2006.202.00:22:44.48#ibcon#read 4, iclass 35, count 2 2006.202.00:22:44.48#ibcon#about to read 5, iclass 35, count 2 2006.202.00:22:44.48#ibcon#read 5, iclass 35, count 2 2006.202.00:22:44.48#ibcon#about to read 6, iclass 35, count 2 2006.202.00:22:44.48#ibcon#read 6, iclass 35, count 2 2006.202.00:22:44.48#ibcon#end of sib2, iclass 35, count 2 2006.202.00:22:44.48#ibcon#*after write, iclass 35, count 2 2006.202.00:22:44.48#ibcon#*before return 0, iclass 35, count 2 2006.202.00:22:44.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:44.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.202.00:22:44.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.202.00:22:44.48#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:44.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:44.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:44.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:44.60#ibcon#enter wrdev, iclass 35, count 0 2006.202.00:22:44.60#ibcon#first serial, iclass 35, count 0 2006.202.00:22:44.60#ibcon#enter sib2, iclass 35, count 0 2006.202.00:22:44.60#ibcon#flushed, iclass 35, count 0 2006.202.00:22:44.60#ibcon#about to write, iclass 35, count 0 2006.202.00:22:44.60#ibcon#wrote, iclass 35, count 0 2006.202.00:22:44.60#ibcon#about to read 3, iclass 35, count 0 2006.202.00:22:44.62#ibcon#read 3, iclass 35, count 0 2006.202.00:22:44.62#ibcon#about to read 4, iclass 35, count 0 2006.202.00:22:44.62#ibcon#read 4, iclass 35, count 0 2006.202.00:22:44.62#ibcon#about to read 5, iclass 35, count 0 2006.202.00:22:44.62#ibcon#read 5, iclass 35, count 0 2006.202.00:22:44.62#ibcon#about to read 6, iclass 35, count 0 2006.202.00:22:44.62#ibcon#read 6, iclass 35, count 0 2006.202.00:22:44.62#ibcon#end of sib2, iclass 35, count 0 2006.202.00:22:44.62#ibcon#*mode == 0, iclass 35, count 0 2006.202.00:22:44.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.00:22:44.62#ibcon#[27=USB\r\n] 2006.202.00:22:44.62#ibcon#*before write, iclass 35, count 0 2006.202.00:22:44.62#ibcon#enter sib2, iclass 35, count 0 2006.202.00:22:44.62#ibcon#flushed, iclass 35, count 0 2006.202.00:22:44.62#ibcon#about to write, iclass 35, count 0 2006.202.00:22:44.62#ibcon#wrote, iclass 35, count 0 2006.202.00:22:44.62#ibcon#about to read 3, iclass 35, count 0 2006.202.00:22:44.65#ibcon#read 3, iclass 35, count 0 2006.202.00:22:44.65#ibcon#about to read 4, iclass 35, count 0 2006.202.00:22:44.65#ibcon#read 4, iclass 35, count 0 2006.202.00:22:44.65#ibcon#about to read 5, iclass 35, count 0 2006.202.00:22:44.65#ibcon#read 5, iclass 35, count 0 2006.202.00:22:44.65#ibcon#about to read 6, iclass 35, count 0 2006.202.00:22:44.65#ibcon#read 6, iclass 35, count 0 2006.202.00:22:44.65#ibcon#end of sib2, iclass 35, count 0 2006.202.00:22:44.65#ibcon#*after write, iclass 35, count 0 2006.202.00:22:44.65#ibcon#*before return 0, iclass 35, count 0 2006.202.00:22:44.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:44.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.202.00:22:44.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.00:22:44.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.00:22:44.65$vck44/vblo=6,719.99 2006.202.00:22:44.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.202.00:22:44.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.202.00:22:44.65#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:44.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:44.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:44.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:44.65#ibcon#enter wrdev, iclass 37, count 0 2006.202.00:22:44.65#ibcon#first serial, iclass 37, count 0 2006.202.00:22:44.65#ibcon#enter sib2, iclass 37, count 0 2006.202.00:22:44.65#ibcon#flushed, iclass 37, count 0 2006.202.00:22:44.65#ibcon#about to write, iclass 37, count 0 2006.202.00:22:44.65#ibcon#wrote, iclass 37, count 0 2006.202.00:22:44.65#ibcon#about to read 3, iclass 37, count 0 2006.202.00:22:44.67#ibcon#read 3, iclass 37, count 0 2006.202.00:22:44.67#ibcon#about to read 4, iclass 37, count 0 2006.202.00:22:44.67#ibcon#read 4, iclass 37, count 0 2006.202.00:22:44.67#ibcon#about to read 5, iclass 37, count 0 2006.202.00:22:44.67#ibcon#read 5, iclass 37, count 0 2006.202.00:22:44.67#ibcon#about to read 6, iclass 37, count 0 2006.202.00:22:44.67#ibcon#read 6, iclass 37, count 0 2006.202.00:22:44.67#ibcon#end of sib2, iclass 37, count 0 2006.202.00:22:44.67#ibcon#*mode == 0, iclass 37, count 0 2006.202.00:22:44.67#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.00:22:44.67#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.00:22:44.67#ibcon#*before write, iclass 37, count 0 2006.202.00:22:44.67#ibcon#enter sib2, iclass 37, count 0 2006.202.00:22:44.67#ibcon#flushed, iclass 37, count 0 2006.202.00:22:44.67#ibcon#about to write, iclass 37, count 0 2006.202.00:22:44.67#ibcon#wrote, iclass 37, count 0 2006.202.00:22:44.67#ibcon#about to read 3, iclass 37, count 0 2006.202.00:22:44.71#ibcon#read 3, iclass 37, count 0 2006.202.00:22:44.71#ibcon#about to read 4, iclass 37, count 0 2006.202.00:22:44.71#ibcon#read 4, iclass 37, count 0 2006.202.00:22:44.71#ibcon#about to read 5, iclass 37, count 0 2006.202.00:22:44.71#ibcon#read 5, iclass 37, count 0 2006.202.00:22:44.71#ibcon#about to read 6, iclass 37, count 0 2006.202.00:22:44.71#ibcon#read 6, iclass 37, count 0 2006.202.00:22:44.71#ibcon#end of sib2, iclass 37, count 0 2006.202.00:22:44.71#ibcon#*after write, iclass 37, count 0 2006.202.00:22:44.71#ibcon#*before return 0, iclass 37, count 0 2006.202.00:22:44.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:44.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.202.00:22:44.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.00:22:44.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.00:22:44.71$vck44/vb=6,4 2006.202.00:22:44.71#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.202.00:22:44.71#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.202.00:22:44.71#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:44.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:44.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:44.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:44.77#ibcon#enter wrdev, iclass 39, count 2 2006.202.00:22:44.77#ibcon#first serial, iclass 39, count 2 2006.202.00:22:44.77#ibcon#enter sib2, iclass 39, count 2 2006.202.00:22:44.77#ibcon#flushed, iclass 39, count 2 2006.202.00:22:44.77#ibcon#about to write, iclass 39, count 2 2006.202.00:22:44.77#ibcon#wrote, iclass 39, count 2 2006.202.00:22:44.77#ibcon#about to read 3, iclass 39, count 2 2006.202.00:22:44.79#ibcon#read 3, iclass 39, count 2 2006.202.00:22:44.79#ibcon#about to read 4, iclass 39, count 2 2006.202.00:22:44.79#ibcon#read 4, iclass 39, count 2 2006.202.00:22:44.79#ibcon#about to read 5, iclass 39, count 2 2006.202.00:22:44.79#ibcon#read 5, iclass 39, count 2 2006.202.00:22:44.79#ibcon#about to read 6, iclass 39, count 2 2006.202.00:22:44.79#ibcon#read 6, iclass 39, count 2 2006.202.00:22:44.79#ibcon#end of sib2, iclass 39, count 2 2006.202.00:22:44.79#ibcon#*mode == 0, iclass 39, count 2 2006.202.00:22:44.79#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.202.00:22:44.79#ibcon#[27=AT06-04\r\n] 2006.202.00:22:44.79#ibcon#*before write, iclass 39, count 2 2006.202.00:22:44.79#ibcon#enter sib2, iclass 39, count 2 2006.202.00:22:44.79#ibcon#flushed, iclass 39, count 2 2006.202.00:22:44.79#ibcon#about to write, iclass 39, count 2 2006.202.00:22:44.79#ibcon#wrote, iclass 39, count 2 2006.202.00:22:44.79#ibcon#about to read 3, iclass 39, count 2 2006.202.00:22:44.82#ibcon#read 3, iclass 39, count 2 2006.202.00:22:44.85#ibcon#about to read 4, iclass 39, count 2 2006.202.00:22:44.85#ibcon#read 4, iclass 39, count 2 2006.202.00:22:44.85#ibcon#about to read 5, iclass 39, count 2 2006.202.00:22:44.85#ibcon#read 5, iclass 39, count 2 2006.202.00:22:44.86#ibcon#about to read 6, iclass 39, count 2 2006.202.00:22:44.86#ibcon#read 6, iclass 39, count 2 2006.202.00:22:44.86#ibcon#end of sib2, iclass 39, count 2 2006.202.00:22:44.86#ibcon#*after write, iclass 39, count 2 2006.202.00:22:44.86#ibcon#*before return 0, iclass 39, count 2 2006.202.00:22:44.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:44.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:22:44.86#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.202.00:22:44.86#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:44.86#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:44.98#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:44.98#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:44.98#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:22:44.98#ibcon#first serial, iclass 39, count 0 2006.202.00:22:44.98#ibcon#enter sib2, iclass 39, count 0 2006.202.00:22:44.98#ibcon#flushed, iclass 39, count 0 2006.202.00:22:44.98#ibcon#about to write, iclass 39, count 0 2006.202.00:22:44.98#ibcon#wrote, iclass 39, count 0 2006.202.00:22:44.98#ibcon#about to read 3, iclass 39, count 0 2006.202.00:22:45.00#ibcon#read 3, iclass 39, count 0 2006.202.00:22:45.00#ibcon#about to read 4, iclass 39, count 0 2006.202.00:22:45.00#ibcon#read 4, iclass 39, count 0 2006.202.00:22:45.00#ibcon#about to read 5, iclass 39, count 0 2006.202.00:22:45.00#ibcon#read 5, iclass 39, count 0 2006.202.00:22:45.00#ibcon#about to read 6, iclass 39, count 0 2006.202.00:22:45.00#ibcon#read 6, iclass 39, count 0 2006.202.00:22:45.00#ibcon#end of sib2, iclass 39, count 0 2006.202.00:22:45.00#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:22:45.00#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:22:45.00#ibcon#[27=USB\r\n] 2006.202.00:22:45.00#ibcon#*before write, iclass 39, count 0 2006.202.00:22:45.00#ibcon#enter sib2, iclass 39, count 0 2006.202.00:22:45.00#ibcon#flushed, iclass 39, count 0 2006.202.00:22:45.00#ibcon#about to write, iclass 39, count 0 2006.202.00:22:45.00#ibcon#wrote, iclass 39, count 0 2006.202.00:22:45.00#ibcon#about to read 3, iclass 39, count 0 2006.202.00:22:45.03#ibcon#read 3, iclass 39, count 0 2006.202.00:22:45.03#ibcon#about to read 4, iclass 39, count 0 2006.202.00:22:45.03#ibcon#read 4, iclass 39, count 0 2006.202.00:22:45.03#ibcon#about to read 5, iclass 39, count 0 2006.202.00:22:45.03#ibcon#read 5, iclass 39, count 0 2006.202.00:22:45.03#ibcon#about to read 6, iclass 39, count 0 2006.202.00:22:45.03#ibcon#read 6, iclass 39, count 0 2006.202.00:22:45.03#ibcon#end of sib2, iclass 39, count 0 2006.202.00:22:45.03#ibcon#*after write, iclass 39, count 0 2006.202.00:22:45.03#ibcon#*before return 0, iclass 39, count 0 2006.202.00:22:45.03#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:45.03#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:22:45.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:22:45.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:22:45.03$vck44/vblo=7,734.99 2006.202.00:22:45.03#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.202.00:22:45.03#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.202.00:22:45.03#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:45.03#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:45.03#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:45.03#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:45.03#ibcon#enter wrdev, iclass 2, count 0 2006.202.00:22:45.03#ibcon#first serial, iclass 2, count 0 2006.202.00:22:45.03#ibcon#enter sib2, iclass 2, count 0 2006.202.00:22:45.03#ibcon#flushed, iclass 2, count 0 2006.202.00:22:45.03#ibcon#about to write, iclass 2, count 0 2006.202.00:22:45.03#ibcon#wrote, iclass 2, count 0 2006.202.00:22:45.03#ibcon#about to read 3, iclass 2, count 0 2006.202.00:22:45.05#ibcon#read 3, iclass 2, count 0 2006.202.00:22:45.05#ibcon#about to read 4, iclass 2, count 0 2006.202.00:22:45.05#ibcon#read 4, iclass 2, count 0 2006.202.00:22:45.05#ibcon#about to read 5, iclass 2, count 0 2006.202.00:22:45.05#ibcon#read 5, iclass 2, count 0 2006.202.00:22:45.05#ibcon#about to read 6, iclass 2, count 0 2006.202.00:22:45.05#ibcon#read 6, iclass 2, count 0 2006.202.00:22:45.05#ibcon#end of sib2, iclass 2, count 0 2006.202.00:22:45.05#ibcon#*mode == 0, iclass 2, count 0 2006.202.00:22:45.05#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.00:22:45.05#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.00:22:45.05#ibcon#*before write, iclass 2, count 0 2006.202.00:22:45.05#ibcon#enter sib2, iclass 2, count 0 2006.202.00:22:45.05#ibcon#flushed, iclass 2, count 0 2006.202.00:22:45.05#ibcon#about to write, iclass 2, count 0 2006.202.00:22:45.05#ibcon#wrote, iclass 2, count 0 2006.202.00:22:45.05#ibcon#about to read 3, iclass 2, count 0 2006.202.00:22:45.09#ibcon#read 3, iclass 2, count 0 2006.202.00:22:45.09#ibcon#about to read 4, iclass 2, count 0 2006.202.00:22:45.09#ibcon#read 4, iclass 2, count 0 2006.202.00:22:45.09#ibcon#about to read 5, iclass 2, count 0 2006.202.00:22:45.09#ibcon#read 5, iclass 2, count 0 2006.202.00:22:45.09#ibcon#about to read 6, iclass 2, count 0 2006.202.00:22:45.09#ibcon#read 6, iclass 2, count 0 2006.202.00:22:45.09#ibcon#end of sib2, iclass 2, count 0 2006.202.00:22:45.09#ibcon#*after write, iclass 2, count 0 2006.202.00:22:45.09#ibcon#*before return 0, iclass 2, count 0 2006.202.00:22:45.09#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:45.09#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.202.00:22:45.09#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.00:22:45.09#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.00:22:45.09$vck44/vb=7,4 2006.202.00:22:45.09#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.202.00:22:45.09#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.202.00:22:45.09#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:45.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:45.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:45.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:45.15#ibcon#enter wrdev, iclass 5, count 2 2006.202.00:22:45.15#ibcon#first serial, iclass 5, count 2 2006.202.00:22:45.15#ibcon#enter sib2, iclass 5, count 2 2006.202.00:22:45.15#ibcon#flushed, iclass 5, count 2 2006.202.00:22:45.15#ibcon#about to write, iclass 5, count 2 2006.202.00:22:45.15#ibcon#wrote, iclass 5, count 2 2006.202.00:22:45.15#ibcon#about to read 3, iclass 5, count 2 2006.202.00:22:45.17#ibcon#read 3, iclass 5, count 2 2006.202.00:22:45.17#ibcon#about to read 4, iclass 5, count 2 2006.202.00:22:45.17#ibcon#read 4, iclass 5, count 2 2006.202.00:22:45.17#ibcon#about to read 5, iclass 5, count 2 2006.202.00:22:45.17#ibcon#read 5, iclass 5, count 2 2006.202.00:22:45.17#ibcon#about to read 6, iclass 5, count 2 2006.202.00:22:45.17#ibcon#read 6, iclass 5, count 2 2006.202.00:22:45.17#ibcon#end of sib2, iclass 5, count 2 2006.202.00:22:45.17#ibcon#*mode == 0, iclass 5, count 2 2006.202.00:22:45.17#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.202.00:22:45.17#ibcon#[27=AT07-04\r\n] 2006.202.00:22:45.17#ibcon#*before write, iclass 5, count 2 2006.202.00:22:45.17#ibcon#enter sib2, iclass 5, count 2 2006.202.00:22:45.17#ibcon#flushed, iclass 5, count 2 2006.202.00:22:45.17#ibcon#about to write, iclass 5, count 2 2006.202.00:22:45.17#ibcon#wrote, iclass 5, count 2 2006.202.00:22:45.17#ibcon#about to read 3, iclass 5, count 2 2006.202.00:22:45.20#ibcon#read 3, iclass 5, count 2 2006.202.00:22:45.20#ibcon#about to read 4, iclass 5, count 2 2006.202.00:22:45.20#ibcon#read 4, iclass 5, count 2 2006.202.00:22:45.20#ibcon#about to read 5, iclass 5, count 2 2006.202.00:22:45.20#ibcon#read 5, iclass 5, count 2 2006.202.00:22:45.20#ibcon#about to read 6, iclass 5, count 2 2006.202.00:22:45.20#ibcon#read 6, iclass 5, count 2 2006.202.00:22:45.20#ibcon#end of sib2, iclass 5, count 2 2006.202.00:22:45.20#ibcon#*after write, iclass 5, count 2 2006.202.00:22:45.20#ibcon#*before return 0, iclass 5, count 2 2006.202.00:22:45.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:45.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.202.00:22:45.20#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.202.00:22:45.20#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:45.20#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:45.32#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:45.32#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:45.32#ibcon#enter wrdev, iclass 5, count 0 2006.202.00:22:45.32#ibcon#first serial, iclass 5, count 0 2006.202.00:22:45.32#ibcon#enter sib2, iclass 5, count 0 2006.202.00:22:45.32#ibcon#flushed, iclass 5, count 0 2006.202.00:22:45.32#ibcon#about to write, iclass 5, count 0 2006.202.00:22:45.32#ibcon#wrote, iclass 5, count 0 2006.202.00:22:45.32#ibcon#about to read 3, iclass 5, count 0 2006.202.00:22:45.34#ibcon#read 3, iclass 5, count 0 2006.202.00:22:45.34#ibcon#about to read 4, iclass 5, count 0 2006.202.00:22:45.34#ibcon#read 4, iclass 5, count 0 2006.202.00:22:45.34#ibcon#about to read 5, iclass 5, count 0 2006.202.00:22:45.34#ibcon#read 5, iclass 5, count 0 2006.202.00:22:45.34#ibcon#about to read 6, iclass 5, count 0 2006.202.00:22:45.34#ibcon#read 6, iclass 5, count 0 2006.202.00:22:45.34#ibcon#end of sib2, iclass 5, count 0 2006.202.00:22:45.34#ibcon#*mode == 0, iclass 5, count 0 2006.202.00:22:45.34#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.00:22:45.34#ibcon#[27=USB\r\n] 2006.202.00:22:45.34#ibcon#*before write, iclass 5, count 0 2006.202.00:22:45.34#ibcon#enter sib2, iclass 5, count 0 2006.202.00:22:45.34#ibcon#flushed, iclass 5, count 0 2006.202.00:22:45.34#ibcon#about to write, iclass 5, count 0 2006.202.00:22:45.34#ibcon#wrote, iclass 5, count 0 2006.202.00:22:45.34#ibcon#about to read 3, iclass 5, count 0 2006.202.00:22:45.37#ibcon#read 3, iclass 5, count 0 2006.202.00:22:45.37#ibcon#about to read 4, iclass 5, count 0 2006.202.00:22:45.37#ibcon#read 4, iclass 5, count 0 2006.202.00:22:45.37#ibcon#about to read 5, iclass 5, count 0 2006.202.00:22:45.37#ibcon#read 5, iclass 5, count 0 2006.202.00:22:45.37#ibcon#about to read 6, iclass 5, count 0 2006.202.00:22:45.37#ibcon#read 6, iclass 5, count 0 2006.202.00:22:45.37#ibcon#end of sib2, iclass 5, count 0 2006.202.00:22:45.37#ibcon#*after write, iclass 5, count 0 2006.202.00:22:45.37#ibcon#*before return 0, iclass 5, count 0 2006.202.00:22:45.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:45.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.202.00:22:45.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.00:22:45.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.00:22:45.37$vck44/vblo=8,744.99 2006.202.00:22:45.37#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.00:22:45.37#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.00:22:45.37#ibcon#ireg 17 cls_cnt 0 2006.202.00:22:45.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:45.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:45.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:45.37#ibcon#enter wrdev, iclass 7, count 0 2006.202.00:22:45.37#ibcon#first serial, iclass 7, count 0 2006.202.00:22:45.37#ibcon#enter sib2, iclass 7, count 0 2006.202.00:22:45.37#ibcon#flushed, iclass 7, count 0 2006.202.00:22:45.37#ibcon#about to write, iclass 7, count 0 2006.202.00:22:45.37#ibcon#wrote, iclass 7, count 0 2006.202.00:22:45.37#ibcon#about to read 3, iclass 7, count 0 2006.202.00:22:45.39#ibcon#read 3, iclass 7, count 0 2006.202.00:22:45.39#ibcon#about to read 4, iclass 7, count 0 2006.202.00:22:45.39#ibcon#read 4, iclass 7, count 0 2006.202.00:22:45.39#ibcon#about to read 5, iclass 7, count 0 2006.202.00:22:45.39#ibcon#read 5, iclass 7, count 0 2006.202.00:22:45.39#ibcon#about to read 6, iclass 7, count 0 2006.202.00:22:45.39#ibcon#read 6, iclass 7, count 0 2006.202.00:22:45.39#ibcon#end of sib2, iclass 7, count 0 2006.202.00:22:45.39#ibcon#*mode == 0, iclass 7, count 0 2006.202.00:22:45.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.00:22:45.39#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.00:22:45.39#ibcon#*before write, iclass 7, count 0 2006.202.00:22:45.39#ibcon#enter sib2, iclass 7, count 0 2006.202.00:22:45.39#ibcon#flushed, iclass 7, count 0 2006.202.00:22:45.39#ibcon#about to write, iclass 7, count 0 2006.202.00:22:45.39#ibcon#wrote, iclass 7, count 0 2006.202.00:22:45.39#ibcon#about to read 3, iclass 7, count 0 2006.202.00:22:45.43#ibcon#read 3, iclass 7, count 0 2006.202.00:22:45.43#ibcon#about to read 4, iclass 7, count 0 2006.202.00:22:45.43#ibcon#read 4, iclass 7, count 0 2006.202.00:22:45.43#ibcon#about to read 5, iclass 7, count 0 2006.202.00:22:45.43#ibcon#read 5, iclass 7, count 0 2006.202.00:22:45.43#ibcon#about to read 6, iclass 7, count 0 2006.202.00:22:45.43#ibcon#read 6, iclass 7, count 0 2006.202.00:22:45.43#ibcon#end of sib2, iclass 7, count 0 2006.202.00:22:45.43#ibcon#*after write, iclass 7, count 0 2006.202.00:22:45.43#ibcon#*before return 0, iclass 7, count 0 2006.202.00:22:45.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:45.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.00:22:45.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.00:22:45.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.00:22:45.43$vck44/vb=8,4 2006.202.00:22:45.43#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.202.00:22:45.43#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.202.00:22:45.43#ibcon#ireg 11 cls_cnt 2 2006.202.00:22:45.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:45.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:45.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:45.49#ibcon#enter wrdev, iclass 11, count 2 2006.202.00:22:45.49#ibcon#first serial, iclass 11, count 2 2006.202.00:22:45.49#ibcon#enter sib2, iclass 11, count 2 2006.202.00:22:45.49#ibcon#flushed, iclass 11, count 2 2006.202.00:22:45.49#ibcon#about to write, iclass 11, count 2 2006.202.00:22:45.49#ibcon#wrote, iclass 11, count 2 2006.202.00:22:45.49#ibcon#about to read 3, iclass 11, count 2 2006.202.00:22:45.51#ibcon#read 3, iclass 11, count 2 2006.202.00:22:45.51#ibcon#about to read 4, iclass 11, count 2 2006.202.00:22:45.51#ibcon#read 4, iclass 11, count 2 2006.202.00:22:45.51#ibcon#about to read 5, iclass 11, count 2 2006.202.00:22:45.51#ibcon#read 5, iclass 11, count 2 2006.202.00:22:45.51#ibcon#about to read 6, iclass 11, count 2 2006.202.00:22:45.51#ibcon#read 6, iclass 11, count 2 2006.202.00:22:45.51#ibcon#end of sib2, iclass 11, count 2 2006.202.00:22:45.51#ibcon#*mode == 0, iclass 11, count 2 2006.202.00:22:45.51#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.202.00:22:45.51#ibcon#[27=AT08-04\r\n] 2006.202.00:22:45.51#ibcon#*before write, iclass 11, count 2 2006.202.00:22:45.51#ibcon#enter sib2, iclass 11, count 2 2006.202.00:22:45.51#ibcon#flushed, iclass 11, count 2 2006.202.00:22:45.51#ibcon#about to write, iclass 11, count 2 2006.202.00:22:45.51#ibcon#wrote, iclass 11, count 2 2006.202.00:22:45.51#ibcon#about to read 3, iclass 11, count 2 2006.202.00:22:45.54#ibcon#read 3, iclass 11, count 2 2006.202.00:22:45.54#ibcon#about to read 4, iclass 11, count 2 2006.202.00:22:45.54#ibcon#read 4, iclass 11, count 2 2006.202.00:22:45.54#ibcon#about to read 5, iclass 11, count 2 2006.202.00:22:45.54#ibcon#read 5, iclass 11, count 2 2006.202.00:22:45.54#ibcon#about to read 6, iclass 11, count 2 2006.202.00:22:45.54#ibcon#read 6, iclass 11, count 2 2006.202.00:22:45.54#ibcon#end of sib2, iclass 11, count 2 2006.202.00:22:45.54#ibcon#*after write, iclass 11, count 2 2006.202.00:22:45.54#ibcon#*before return 0, iclass 11, count 2 2006.202.00:22:45.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:45.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.202.00:22:45.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.202.00:22:45.54#ibcon#ireg 7 cls_cnt 0 2006.202.00:22:45.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:45.66#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:45.66#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:45.66#ibcon#enter wrdev, iclass 11, count 0 2006.202.00:22:45.66#ibcon#first serial, iclass 11, count 0 2006.202.00:22:45.66#ibcon#enter sib2, iclass 11, count 0 2006.202.00:22:45.66#ibcon#flushed, iclass 11, count 0 2006.202.00:22:45.66#ibcon#about to write, iclass 11, count 0 2006.202.00:22:45.66#ibcon#wrote, iclass 11, count 0 2006.202.00:22:45.66#ibcon#about to read 3, iclass 11, count 0 2006.202.00:22:45.68#ibcon#read 3, iclass 11, count 0 2006.202.00:22:45.68#ibcon#about to read 4, iclass 11, count 0 2006.202.00:22:45.68#ibcon#read 4, iclass 11, count 0 2006.202.00:22:45.68#ibcon#about to read 5, iclass 11, count 0 2006.202.00:22:45.68#ibcon#read 5, iclass 11, count 0 2006.202.00:22:45.68#ibcon#about to read 6, iclass 11, count 0 2006.202.00:22:45.68#ibcon#read 6, iclass 11, count 0 2006.202.00:22:45.68#ibcon#end of sib2, iclass 11, count 0 2006.202.00:22:45.68#ibcon#*mode == 0, iclass 11, count 0 2006.202.00:22:45.68#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.00:22:45.68#ibcon#[27=USB\r\n] 2006.202.00:22:45.68#ibcon#*before write, iclass 11, count 0 2006.202.00:22:45.68#ibcon#enter sib2, iclass 11, count 0 2006.202.00:22:45.68#ibcon#flushed, iclass 11, count 0 2006.202.00:22:45.68#ibcon#about to write, iclass 11, count 0 2006.202.00:22:45.68#ibcon#wrote, iclass 11, count 0 2006.202.00:22:45.68#ibcon#about to read 3, iclass 11, count 0 2006.202.00:22:45.71#ibcon#read 3, iclass 11, count 0 2006.202.00:22:45.71#ibcon#about to read 4, iclass 11, count 0 2006.202.00:22:45.71#ibcon#read 4, iclass 11, count 0 2006.202.00:22:45.71#ibcon#about to read 5, iclass 11, count 0 2006.202.00:22:45.71#ibcon#read 5, iclass 11, count 0 2006.202.00:22:45.71#ibcon#about to read 6, iclass 11, count 0 2006.202.00:22:45.71#ibcon#read 6, iclass 11, count 0 2006.202.00:22:45.71#ibcon#end of sib2, iclass 11, count 0 2006.202.00:22:45.71#ibcon#*after write, iclass 11, count 0 2006.202.00:22:45.71#ibcon#*before return 0, iclass 11, count 0 2006.202.00:22:45.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:45.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.202.00:22:45.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.00:22:45.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.00:22:45.71$vck44/vabw=wide 2006.202.00:22:45.71#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.202.00:22:45.71#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.202.00:22:45.71#ibcon#ireg 8 cls_cnt 0 2006.202.00:22:45.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:45.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:45.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:45.71#ibcon#enter wrdev, iclass 13, count 0 2006.202.00:22:45.71#ibcon#first serial, iclass 13, count 0 2006.202.00:22:45.71#ibcon#enter sib2, iclass 13, count 0 2006.202.00:22:45.71#ibcon#flushed, iclass 13, count 0 2006.202.00:22:45.71#ibcon#about to write, iclass 13, count 0 2006.202.00:22:45.71#ibcon#wrote, iclass 13, count 0 2006.202.00:22:45.71#ibcon#about to read 3, iclass 13, count 0 2006.202.00:22:45.73#ibcon#read 3, iclass 13, count 0 2006.202.00:22:45.73#ibcon#about to read 4, iclass 13, count 0 2006.202.00:22:45.73#ibcon#read 4, iclass 13, count 0 2006.202.00:22:45.73#ibcon#about to read 5, iclass 13, count 0 2006.202.00:22:45.73#ibcon#read 5, iclass 13, count 0 2006.202.00:22:45.73#ibcon#about to read 6, iclass 13, count 0 2006.202.00:22:45.73#ibcon#read 6, iclass 13, count 0 2006.202.00:22:45.73#ibcon#end of sib2, iclass 13, count 0 2006.202.00:22:45.73#ibcon#*mode == 0, iclass 13, count 0 2006.202.00:22:45.73#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.00:22:45.73#ibcon#[25=BW32\r\n] 2006.202.00:22:45.73#ibcon#*before write, iclass 13, count 0 2006.202.00:22:45.73#ibcon#enter sib2, iclass 13, count 0 2006.202.00:22:45.73#ibcon#flushed, iclass 13, count 0 2006.202.00:22:45.73#ibcon#about to write, iclass 13, count 0 2006.202.00:22:45.73#ibcon#wrote, iclass 13, count 0 2006.202.00:22:45.73#ibcon#about to read 3, iclass 13, count 0 2006.202.00:22:45.76#ibcon#read 3, iclass 13, count 0 2006.202.00:22:45.76#ibcon#about to read 4, iclass 13, count 0 2006.202.00:22:45.76#ibcon#read 4, iclass 13, count 0 2006.202.00:22:45.76#ibcon#about to read 5, iclass 13, count 0 2006.202.00:22:45.76#ibcon#read 5, iclass 13, count 0 2006.202.00:22:45.76#ibcon#about to read 6, iclass 13, count 0 2006.202.00:22:45.76#ibcon#read 6, iclass 13, count 0 2006.202.00:22:45.76#ibcon#end of sib2, iclass 13, count 0 2006.202.00:22:45.76#ibcon#*after write, iclass 13, count 0 2006.202.00:22:45.76#ibcon#*before return 0, iclass 13, count 0 2006.202.00:22:45.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:45.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.202.00:22:45.76#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.00:22:45.76#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.00:22:45.76$vck44/vbbw=wide 2006.202.00:22:45.76#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.00:22:45.76#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.00:22:45.76#ibcon#ireg 8 cls_cnt 0 2006.202.00:22:45.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:22:45.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:22:45.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:22:45.83#ibcon#enter wrdev, iclass 15, count 0 2006.202.00:22:45.83#ibcon#first serial, iclass 15, count 0 2006.202.00:22:45.83#ibcon#enter sib2, iclass 15, count 0 2006.202.00:22:45.83#ibcon#flushed, iclass 15, count 0 2006.202.00:22:45.83#ibcon#about to write, iclass 15, count 0 2006.202.00:22:45.83#ibcon#wrote, iclass 15, count 0 2006.202.00:22:45.83#ibcon#about to read 3, iclass 15, count 0 2006.202.00:22:45.85#ibcon#read 3, iclass 15, count 0 2006.202.00:22:45.85#ibcon#about to read 4, iclass 15, count 0 2006.202.00:22:45.85#ibcon#read 4, iclass 15, count 0 2006.202.00:22:45.85#ibcon#about to read 5, iclass 15, count 0 2006.202.00:22:45.85#ibcon#read 5, iclass 15, count 0 2006.202.00:22:45.85#ibcon#about to read 6, iclass 15, count 0 2006.202.00:22:45.85#ibcon#read 6, iclass 15, count 0 2006.202.00:22:45.85#ibcon#end of sib2, iclass 15, count 0 2006.202.00:22:45.85#ibcon#*mode == 0, iclass 15, count 0 2006.202.00:22:45.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.00:22:45.85#ibcon#[27=BW32\r\n] 2006.202.00:22:45.85#ibcon#*before write, iclass 15, count 0 2006.202.00:22:45.85#ibcon#enter sib2, iclass 15, count 0 2006.202.00:22:45.85#ibcon#flushed, iclass 15, count 0 2006.202.00:22:45.85#ibcon#about to write, iclass 15, count 0 2006.202.00:22:45.85#ibcon#wrote, iclass 15, count 0 2006.202.00:22:45.85#ibcon#about to read 3, iclass 15, count 0 2006.202.00:22:45.88#ibcon#read 3, iclass 15, count 0 2006.202.00:22:45.88#ibcon#about to read 4, iclass 15, count 0 2006.202.00:22:45.88#ibcon#read 4, iclass 15, count 0 2006.202.00:22:45.88#ibcon#about to read 5, iclass 15, count 0 2006.202.00:22:45.88#ibcon#read 5, iclass 15, count 0 2006.202.00:22:45.88#ibcon#about to read 6, iclass 15, count 0 2006.202.00:22:45.88#ibcon#read 6, iclass 15, count 0 2006.202.00:22:45.88#ibcon#end of sib2, iclass 15, count 0 2006.202.00:22:45.88#ibcon#*after write, iclass 15, count 0 2006.202.00:22:45.88#ibcon#*before return 0, iclass 15, count 0 2006.202.00:22:45.88#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:22:45.88#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:22:45.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.00:22:45.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.00:22:45.92$setupk4/ifdk4 2006.202.00:22:45.92$ifdk4/lo= 2006.202.00:22:45.92$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.00:22:45.92$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.00:22:45.92$ifdk4/patch= 2006.202.00:22:45.92$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.00:22:45.92$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.00:22:45.92$setupk4/!*+20s 2006.202.00:22:46.50#abcon#<5=/03 1.7 3.2 20.431001001.4\r\n> 2006.202.00:22:46.52#abcon#{5=INTERFACE CLEAR} 2006.202.00:22:46.58#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:22:56.67#abcon#<5=/03 1.7 3.1 20.431001001.4\r\n> 2006.202.00:22:56.69#abcon#{5=INTERFACE CLEAR} 2006.202.00:22:56.75#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:23:00.30$setupk4/"tpicd 2006.202.00:23:00.30$setupk4/echo=off 2006.202.00:23:00.30$setupk4/xlog=off 2006.202.00:23:00.30:!2006.202.00:33:02 2006.202.00:23:33.13#trakl#Source acquired 2006.202.00:23:33.13#flagr#flagr/antenna,acquired 2006.202.00:33:02.00:preob 2006.202.00:33:02.13/onsource/TRACKING 2006.202.00:33:02.13:!2006.202.00:33:12 2006.202.00:33:12.00:"tape 2006.202.00:33:12.00:"st=record 2006.202.00:33:12.00:data_valid=on 2006.202.00:33:12.00:midob 2006.202.00:33:12.14/onsource/TRACKING 2006.202.00:33:12.14/wx/20.38,1001.2,100 2006.202.00:33:12.30/cable/+6.4829E-03 2006.202.00:33:13.39/va/01,08,usb,yes,39,42 2006.202.00:33:13.39/va/02,07,usb,yes,42,43 2006.202.00:33:13.39/va/03,08,usb,yes,38,40 2006.202.00:33:13.39/va/04,07,usb,yes,43,46 2006.202.00:33:13.39/va/05,04,usb,yes,39,39 2006.202.00:33:13.39/va/06,05,usb,yes,39,39 2006.202.00:33:13.39/va/07,05,usb,yes,38,39 2006.202.00:33:13.39/va/08,04,usb,yes,38,45 2006.202.00:33:13.62/valo/01,524.99,yes,locked 2006.202.00:33:13.62/valo/02,534.99,yes,locked 2006.202.00:33:13.62/valo/03,564.99,yes,locked 2006.202.00:33:13.62/valo/04,624.99,yes,locked 2006.202.00:33:13.62/valo/05,734.99,yes,locked 2006.202.00:33:13.62/valo/06,814.99,yes,locked 2006.202.00:33:13.62/valo/07,864.99,yes,locked 2006.202.00:33:13.62/valo/08,884.99,yes,locked 2006.202.00:33:14.71/vb/01,04,usb,yes,29,27 2006.202.00:33:14.71/vb/02,05,usb,yes,28,28 2006.202.00:33:14.71/vb/03,04,usb,yes,29,32 2006.202.00:33:14.71/vb/04,05,usb,yes,29,28 2006.202.00:33:14.71/vb/05,04,usb,yes,26,28 2006.202.00:33:14.71/vb/06,04,usb,yes,30,26 2006.202.00:33:14.71/vb/07,04,usb,yes,30,30 2006.202.00:33:14.71/vb/08,04,usb,yes,27,31 2006.202.00:33:14.95/vblo/01,629.99,yes,locked 2006.202.00:33:14.95/vblo/02,634.99,yes,locked 2006.202.00:33:14.95/vblo/03,649.99,yes,locked 2006.202.00:33:14.95/vblo/04,679.99,yes,locked 2006.202.00:33:14.95/vblo/05,709.99,yes,locked 2006.202.00:33:14.95/vblo/06,719.99,yes,locked 2006.202.00:33:14.95/vblo/07,734.99,yes,locked 2006.202.00:33:14.95/vblo/08,744.99,yes,locked 2006.202.00:33:15.10/vabw/8 2006.202.00:33:15.25/vbbw/8 2006.202.00:33:15.36/xfe/off,on,15.5 2006.202.00:33:15.76/ifatt/23,28,28,28 2006.202.00:33:16.07/fmout-gps/S +4.50E-07 2006.202.00:33:16.11:!2006.202.00:34:12 2006.202.00:34:12.00:data_valid=off 2006.202.00:34:12.00:"et 2006.202.00:34:12.00:!+3s 2006.202.00:34:15.02:"tape 2006.202.00:34:15.02:postob 2006.202.00:34:15.13/cable/+6.4823E-03 2006.202.00:34:15.13/wx/20.38,1001.3,100 2006.202.00:34:15.19/fmout-gps/S +4.50E-07 2006.202.00:34:15.19:scan_name=202-0036,jd0607,80 2006.202.00:34:15.19:source=0528+134,053056.42,133155.1,2000.0,cw 2006.202.00:34:16.14#flagr#flagr/antenna,new-source 2006.202.00:34:16.14:checkk5 2006.202.00:34:16.54/chk_autoobs//k5ts1/ autoobs is running! 2006.202.00:34:16.96/chk_autoobs//k5ts2/ autoobs is running! 2006.202.00:34:17.37/chk_autoobs//k5ts3/ autoobs is running! 2006.202.00:34:17.77/chk_autoobs//k5ts4/ autoobs is running! 2006.202.00:34:18.16/chk_obsdata//k5ts1/T2020033??a.dat file size is correct (nominal:240MB, actual:240MB). 2006.202.00:34:18.55/chk_obsdata//k5ts2/T2020033??b.dat file size is correct (nominal:240MB, actual:240MB). 2006.202.00:34:18.97/chk_obsdata//k5ts3/T2020033??c.dat file size is correct (nominal:240MB, actual:240MB). 2006.202.00:34:19.40/chk_obsdata//k5ts4/T2020033??d.dat file size is correct (nominal:240MB, actual:240MB). 2006.202.00:34:20.13/k5log//k5ts1_log_newline 2006.202.00:34:20.85/k5log//k5ts2_log_newline 2006.202.00:34:21.57/k5log//k5ts3_log_newline 2006.202.00:34:22.26/k5log//k5ts4_log_newline 2006.202.00:34:22.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.00:34:22.28:setupk4=1 2006.202.00:34:22.28$setupk4/echo=on 2006.202.00:34:22.28$setupk4/pcalon 2006.202.00:34:22.28$pcalon/"no phase cal control is implemented here 2006.202.00:34:22.28$setupk4/"tpicd=stop 2006.202.00:34:22.28$setupk4/"rec=synch_on 2006.202.00:34:22.28$setupk4/"rec_mode=128 2006.202.00:34:22.28$setupk4/!* 2006.202.00:34:22.28$setupk4/recpk4 2006.202.00:34:22.28$recpk4/recpatch= 2006.202.00:34:22.29$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.00:34:22.29$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.00:34:22.29$setupk4/vck44 2006.202.00:34:22.29$vck44/valo=1,524.99 2006.202.00:34:22.29#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.202.00:34:22.29#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.202.00:34:22.29#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:22.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:22.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:22.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:22.29#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:34:22.29#ibcon#first serial, iclass 39, count 0 2006.202.00:34:22.29#ibcon#enter sib2, iclass 39, count 0 2006.202.00:34:22.29#ibcon#flushed, iclass 39, count 0 2006.202.00:34:22.29#ibcon#about to write, iclass 39, count 0 2006.202.00:34:22.29#ibcon#wrote, iclass 39, count 0 2006.202.00:34:22.29#ibcon#about to read 3, iclass 39, count 0 2006.202.00:34:22.31#ibcon#read 3, iclass 39, count 0 2006.202.00:34:22.31#ibcon#about to read 4, iclass 39, count 0 2006.202.00:34:22.31#ibcon#read 4, iclass 39, count 0 2006.202.00:34:22.31#ibcon#about to read 5, iclass 39, count 0 2006.202.00:34:22.31#ibcon#read 5, iclass 39, count 0 2006.202.00:34:22.31#ibcon#about to read 6, iclass 39, count 0 2006.202.00:34:22.31#ibcon#read 6, iclass 39, count 0 2006.202.00:34:22.31#ibcon#end of sib2, iclass 39, count 0 2006.202.00:34:22.31#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:34:22.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:34:22.31#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.00:34:22.31#ibcon#*before write, iclass 39, count 0 2006.202.00:34:22.31#ibcon#enter sib2, iclass 39, count 0 2006.202.00:34:22.31#ibcon#flushed, iclass 39, count 0 2006.202.00:34:22.31#ibcon#about to write, iclass 39, count 0 2006.202.00:34:22.31#ibcon#wrote, iclass 39, count 0 2006.202.00:34:22.31#ibcon#about to read 3, iclass 39, count 0 2006.202.00:34:22.36#ibcon#read 3, iclass 39, count 0 2006.202.00:34:22.36#ibcon#about to read 4, iclass 39, count 0 2006.202.00:34:22.36#ibcon#read 4, iclass 39, count 0 2006.202.00:34:22.36#ibcon#about to read 5, iclass 39, count 0 2006.202.00:34:22.36#ibcon#read 5, iclass 39, count 0 2006.202.00:34:22.36#ibcon#about to read 6, iclass 39, count 0 2006.202.00:34:22.36#ibcon#read 6, iclass 39, count 0 2006.202.00:34:22.36#ibcon#end of sib2, iclass 39, count 0 2006.202.00:34:22.36#ibcon#*after write, iclass 39, count 0 2006.202.00:34:22.36#ibcon#*before return 0, iclass 39, count 0 2006.202.00:34:22.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:22.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:22.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:34:22.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:34:22.36$vck44/va=1,8 2006.202.00:34:22.36#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.202.00:34:22.36#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.202.00:34:22.36#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:22.36#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:22.36#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:22.36#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:22.36#ibcon#enter wrdev, iclass 2, count 2 2006.202.00:34:22.36#ibcon#first serial, iclass 2, count 2 2006.202.00:34:22.36#ibcon#enter sib2, iclass 2, count 2 2006.202.00:34:22.36#ibcon#flushed, iclass 2, count 2 2006.202.00:34:22.36#ibcon#about to write, iclass 2, count 2 2006.202.00:34:22.36#ibcon#wrote, iclass 2, count 2 2006.202.00:34:22.36#ibcon#about to read 3, iclass 2, count 2 2006.202.00:34:22.38#ibcon#read 3, iclass 2, count 2 2006.202.00:34:22.38#ibcon#about to read 4, iclass 2, count 2 2006.202.00:34:22.38#ibcon#read 4, iclass 2, count 2 2006.202.00:34:22.38#ibcon#about to read 5, iclass 2, count 2 2006.202.00:34:22.38#ibcon#read 5, iclass 2, count 2 2006.202.00:34:22.38#ibcon#about to read 6, iclass 2, count 2 2006.202.00:34:22.38#ibcon#read 6, iclass 2, count 2 2006.202.00:34:22.38#ibcon#end of sib2, iclass 2, count 2 2006.202.00:34:22.38#ibcon#*mode == 0, iclass 2, count 2 2006.202.00:34:22.38#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.202.00:34:22.38#ibcon#[25=AT01-08\r\n] 2006.202.00:34:22.38#ibcon#*before write, iclass 2, count 2 2006.202.00:34:22.38#ibcon#enter sib2, iclass 2, count 2 2006.202.00:34:22.38#ibcon#flushed, iclass 2, count 2 2006.202.00:34:22.38#ibcon#about to write, iclass 2, count 2 2006.202.00:34:22.38#ibcon#wrote, iclass 2, count 2 2006.202.00:34:22.38#ibcon#about to read 3, iclass 2, count 2 2006.202.00:34:22.41#ibcon#read 3, iclass 2, count 2 2006.202.00:34:22.41#ibcon#about to read 4, iclass 2, count 2 2006.202.00:34:22.41#ibcon#read 4, iclass 2, count 2 2006.202.00:34:22.41#ibcon#about to read 5, iclass 2, count 2 2006.202.00:34:22.41#ibcon#read 5, iclass 2, count 2 2006.202.00:34:22.41#ibcon#about to read 6, iclass 2, count 2 2006.202.00:34:22.41#ibcon#read 6, iclass 2, count 2 2006.202.00:34:22.41#ibcon#end of sib2, iclass 2, count 2 2006.202.00:34:22.41#ibcon#*after write, iclass 2, count 2 2006.202.00:34:22.41#ibcon#*before return 0, iclass 2, count 2 2006.202.00:34:22.41#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:22.41#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:22.41#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.202.00:34:22.41#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:22.41#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:22.53#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:22.53#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:22.53#ibcon#enter wrdev, iclass 2, count 0 2006.202.00:34:22.53#ibcon#first serial, iclass 2, count 0 2006.202.00:34:22.53#ibcon#enter sib2, iclass 2, count 0 2006.202.00:34:22.53#ibcon#flushed, iclass 2, count 0 2006.202.00:34:22.53#ibcon#about to write, iclass 2, count 0 2006.202.00:34:22.53#ibcon#wrote, iclass 2, count 0 2006.202.00:34:22.53#ibcon#about to read 3, iclass 2, count 0 2006.202.00:34:22.55#ibcon#read 3, iclass 2, count 0 2006.202.00:34:22.55#ibcon#about to read 4, iclass 2, count 0 2006.202.00:34:22.55#ibcon#read 4, iclass 2, count 0 2006.202.00:34:22.55#ibcon#about to read 5, iclass 2, count 0 2006.202.00:34:22.55#ibcon#read 5, iclass 2, count 0 2006.202.00:34:22.55#ibcon#about to read 6, iclass 2, count 0 2006.202.00:34:22.55#ibcon#read 6, iclass 2, count 0 2006.202.00:34:22.55#ibcon#end of sib2, iclass 2, count 0 2006.202.00:34:22.55#ibcon#*mode == 0, iclass 2, count 0 2006.202.00:34:22.55#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.00:34:22.55#ibcon#[25=USB\r\n] 2006.202.00:34:22.55#ibcon#*before write, iclass 2, count 0 2006.202.00:34:22.55#ibcon#enter sib2, iclass 2, count 0 2006.202.00:34:22.55#ibcon#flushed, iclass 2, count 0 2006.202.00:34:22.55#ibcon#about to write, iclass 2, count 0 2006.202.00:34:22.55#ibcon#wrote, iclass 2, count 0 2006.202.00:34:22.55#ibcon#about to read 3, iclass 2, count 0 2006.202.00:34:22.58#ibcon#read 3, iclass 2, count 0 2006.202.00:34:22.58#ibcon#about to read 4, iclass 2, count 0 2006.202.00:34:22.58#ibcon#read 4, iclass 2, count 0 2006.202.00:34:22.58#ibcon#about to read 5, iclass 2, count 0 2006.202.00:34:22.58#ibcon#read 5, iclass 2, count 0 2006.202.00:34:22.58#ibcon#about to read 6, iclass 2, count 0 2006.202.00:34:22.58#ibcon#read 6, iclass 2, count 0 2006.202.00:34:22.58#ibcon#end of sib2, iclass 2, count 0 2006.202.00:34:22.58#ibcon#*after write, iclass 2, count 0 2006.202.00:34:22.58#ibcon#*before return 0, iclass 2, count 0 2006.202.00:34:22.58#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:22.58#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:22.58#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.00:34:22.58#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.00:34:22.58$vck44/valo=2,534.99 2006.202.00:34:22.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.202.00:34:22.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.202.00:34:22.58#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:22.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:22.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:22.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:22.58#ibcon#enter wrdev, iclass 5, count 0 2006.202.00:34:22.58#ibcon#first serial, iclass 5, count 0 2006.202.00:34:22.58#ibcon#enter sib2, iclass 5, count 0 2006.202.00:34:22.58#ibcon#flushed, iclass 5, count 0 2006.202.00:34:22.58#ibcon#about to write, iclass 5, count 0 2006.202.00:34:22.58#ibcon#wrote, iclass 5, count 0 2006.202.00:34:22.58#ibcon#about to read 3, iclass 5, count 0 2006.202.00:34:22.60#ibcon#read 3, iclass 5, count 0 2006.202.00:34:22.60#ibcon#about to read 4, iclass 5, count 0 2006.202.00:34:22.60#ibcon#read 4, iclass 5, count 0 2006.202.00:34:22.60#ibcon#about to read 5, iclass 5, count 0 2006.202.00:34:22.60#ibcon#read 5, iclass 5, count 0 2006.202.00:34:22.60#ibcon#about to read 6, iclass 5, count 0 2006.202.00:34:22.60#ibcon#read 6, iclass 5, count 0 2006.202.00:34:22.60#ibcon#end of sib2, iclass 5, count 0 2006.202.00:34:22.60#ibcon#*mode == 0, iclass 5, count 0 2006.202.00:34:22.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.00:34:22.60#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.00:34:22.60#ibcon#*before write, iclass 5, count 0 2006.202.00:34:22.60#ibcon#enter sib2, iclass 5, count 0 2006.202.00:34:22.60#ibcon#flushed, iclass 5, count 0 2006.202.00:34:22.60#ibcon#about to write, iclass 5, count 0 2006.202.00:34:22.60#ibcon#wrote, iclass 5, count 0 2006.202.00:34:22.60#ibcon#about to read 3, iclass 5, count 0 2006.202.00:34:22.64#ibcon#read 3, iclass 5, count 0 2006.202.00:34:22.64#ibcon#about to read 4, iclass 5, count 0 2006.202.00:34:22.64#ibcon#read 4, iclass 5, count 0 2006.202.00:34:22.64#ibcon#about to read 5, iclass 5, count 0 2006.202.00:34:22.64#ibcon#read 5, iclass 5, count 0 2006.202.00:34:22.64#ibcon#about to read 6, iclass 5, count 0 2006.202.00:34:22.64#ibcon#read 6, iclass 5, count 0 2006.202.00:34:22.64#ibcon#end of sib2, iclass 5, count 0 2006.202.00:34:22.64#ibcon#*after write, iclass 5, count 0 2006.202.00:34:22.64#ibcon#*before return 0, iclass 5, count 0 2006.202.00:34:22.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:22.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:22.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.00:34:22.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.00:34:22.64$vck44/va=2,7 2006.202.00:34:22.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.202.00:34:22.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.202.00:34:22.64#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:22.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:22.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:22.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:22.70#ibcon#enter wrdev, iclass 7, count 2 2006.202.00:34:22.70#ibcon#first serial, iclass 7, count 2 2006.202.00:34:22.70#ibcon#enter sib2, iclass 7, count 2 2006.202.00:34:22.70#ibcon#flushed, iclass 7, count 2 2006.202.00:34:22.70#ibcon#about to write, iclass 7, count 2 2006.202.00:34:22.70#ibcon#wrote, iclass 7, count 2 2006.202.00:34:22.70#ibcon#about to read 3, iclass 7, count 2 2006.202.00:34:22.72#ibcon#read 3, iclass 7, count 2 2006.202.00:34:22.72#ibcon#about to read 4, iclass 7, count 2 2006.202.00:34:22.72#ibcon#read 4, iclass 7, count 2 2006.202.00:34:22.72#ibcon#about to read 5, iclass 7, count 2 2006.202.00:34:22.72#ibcon#read 5, iclass 7, count 2 2006.202.00:34:22.72#ibcon#about to read 6, iclass 7, count 2 2006.202.00:34:22.72#ibcon#read 6, iclass 7, count 2 2006.202.00:34:22.72#ibcon#end of sib2, iclass 7, count 2 2006.202.00:34:22.72#ibcon#*mode == 0, iclass 7, count 2 2006.202.00:34:22.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.202.00:34:22.72#ibcon#[25=AT02-07\r\n] 2006.202.00:34:22.72#ibcon#*before write, iclass 7, count 2 2006.202.00:34:22.72#ibcon#enter sib2, iclass 7, count 2 2006.202.00:34:22.72#ibcon#flushed, iclass 7, count 2 2006.202.00:34:22.72#ibcon#about to write, iclass 7, count 2 2006.202.00:34:22.72#ibcon#wrote, iclass 7, count 2 2006.202.00:34:22.72#ibcon#about to read 3, iclass 7, count 2 2006.202.00:34:22.75#ibcon#read 3, iclass 7, count 2 2006.202.00:34:22.75#ibcon#about to read 4, iclass 7, count 2 2006.202.00:34:22.75#ibcon#read 4, iclass 7, count 2 2006.202.00:34:22.75#ibcon#about to read 5, iclass 7, count 2 2006.202.00:34:22.75#ibcon#read 5, iclass 7, count 2 2006.202.00:34:22.75#ibcon#about to read 6, iclass 7, count 2 2006.202.00:34:22.75#ibcon#read 6, iclass 7, count 2 2006.202.00:34:22.75#ibcon#end of sib2, iclass 7, count 2 2006.202.00:34:22.75#ibcon#*after write, iclass 7, count 2 2006.202.00:34:22.75#ibcon#*before return 0, iclass 7, count 2 2006.202.00:34:22.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:22.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:22.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.202.00:34:22.75#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:22.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:22.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:22.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:22.87#ibcon#enter wrdev, iclass 7, count 0 2006.202.00:34:22.87#ibcon#first serial, iclass 7, count 0 2006.202.00:34:22.87#ibcon#enter sib2, iclass 7, count 0 2006.202.00:34:22.87#ibcon#flushed, iclass 7, count 0 2006.202.00:34:22.87#ibcon#about to write, iclass 7, count 0 2006.202.00:34:22.87#ibcon#wrote, iclass 7, count 0 2006.202.00:34:22.87#ibcon#about to read 3, iclass 7, count 0 2006.202.00:34:22.89#ibcon#read 3, iclass 7, count 0 2006.202.00:34:22.89#ibcon#about to read 4, iclass 7, count 0 2006.202.00:34:22.89#ibcon#read 4, iclass 7, count 0 2006.202.00:34:22.89#ibcon#about to read 5, iclass 7, count 0 2006.202.00:34:22.89#ibcon#read 5, iclass 7, count 0 2006.202.00:34:22.89#ibcon#about to read 6, iclass 7, count 0 2006.202.00:34:22.89#ibcon#read 6, iclass 7, count 0 2006.202.00:34:22.89#ibcon#end of sib2, iclass 7, count 0 2006.202.00:34:22.89#ibcon#*mode == 0, iclass 7, count 0 2006.202.00:34:22.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.00:34:22.89#ibcon#[25=USB\r\n] 2006.202.00:34:22.89#ibcon#*before write, iclass 7, count 0 2006.202.00:34:22.89#ibcon#enter sib2, iclass 7, count 0 2006.202.00:34:22.89#ibcon#flushed, iclass 7, count 0 2006.202.00:34:22.89#ibcon#about to write, iclass 7, count 0 2006.202.00:34:22.89#ibcon#wrote, iclass 7, count 0 2006.202.00:34:22.89#ibcon#about to read 3, iclass 7, count 0 2006.202.00:34:22.92#ibcon#read 3, iclass 7, count 0 2006.202.00:34:22.92#ibcon#about to read 4, iclass 7, count 0 2006.202.00:34:22.92#ibcon#read 4, iclass 7, count 0 2006.202.00:34:22.92#ibcon#about to read 5, iclass 7, count 0 2006.202.00:34:22.92#ibcon#read 5, iclass 7, count 0 2006.202.00:34:22.92#ibcon#about to read 6, iclass 7, count 0 2006.202.00:34:22.92#ibcon#read 6, iclass 7, count 0 2006.202.00:34:22.92#ibcon#end of sib2, iclass 7, count 0 2006.202.00:34:22.92#ibcon#*after write, iclass 7, count 0 2006.202.00:34:22.92#ibcon#*before return 0, iclass 7, count 0 2006.202.00:34:22.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:22.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:22.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.00:34:22.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.00:34:22.92$vck44/valo=3,564.99 2006.202.00:34:22.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.202.00:34:22.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.202.00:34:22.92#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:22.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:22.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:22.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:22.92#ibcon#enter wrdev, iclass 11, count 0 2006.202.00:34:22.92#ibcon#first serial, iclass 11, count 0 2006.202.00:34:22.92#ibcon#enter sib2, iclass 11, count 0 2006.202.00:34:22.92#ibcon#flushed, iclass 11, count 0 2006.202.00:34:22.92#ibcon#about to write, iclass 11, count 0 2006.202.00:34:22.92#ibcon#wrote, iclass 11, count 0 2006.202.00:34:22.92#ibcon#about to read 3, iclass 11, count 0 2006.202.00:34:22.94#ibcon#read 3, iclass 11, count 0 2006.202.00:34:22.94#ibcon#about to read 4, iclass 11, count 0 2006.202.00:34:22.94#ibcon#read 4, iclass 11, count 0 2006.202.00:34:22.94#ibcon#about to read 5, iclass 11, count 0 2006.202.00:34:22.94#ibcon#read 5, iclass 11, count 0 2006.202.00:34:22.94#ibcon#about to read 6, iclass 11, count 0 2006.202.00:34:22.94#ibcon#read 6, iclass 11, count 0 2006.202.00:34:22.94#ibcon#end of sib2, iclass 11, count 0 2006.202.00:34:22.94#ibcon#*mode == 0, iclass 11, count 0 2006.202.00:34:22.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.00:34:22.94#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.00:34:22.94#ibcon#*before write, iclass 11, count 0 2006.202.00:34:22.94#ibcon#enter sib2, iclass 11, count 0 2006.202.00:34:22.94#ibcon#flushed, iclass 11, count 0 2006.202.00:34:22.94#ibcon#about to write, iclass 11, count 0 2006.202.00:34:22.94#ibcon#wrote, iclass 11, count 0 2006.202.00:34:22.94#ibcon#about to read 3, iclass 11, count 0 2006.202.00:34:22.98#ibcon#read 3, iclass 11, count 0 2006.202.00:34:22.98#ibcon#about to read 4, iclass 11, count 0 2006.202.00:34:22.98#ibcon#read 4, iclass 11, count 0 2006.202.00:34:22.98#ibcon#about to read 5, iclass 11, count 0 2006.202.00:34:22.98#ibcon#read 5, iclass 11, count 0 2006.202.00:34:22.98#ibcon#about to read 6, iclass 11, count 0 2006.202.00:34:22.98#ibcon#read 6, iclass 11, count 0 2006.202.00:34:22.98#ibcon#end of sib2, iclass 11, count 0 2006.202.00:34:22.98#ibcon#*after write, iclass 11, count 0 2006.202.00:34:22.98#ibcon#*before return 0, iclass 11, count 0 2006.202.00:34:22.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:22.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:22.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.00:34:22.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.00:34:22.98$vck44/va=3,8 2006.202.00:34:22.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.202.00:34:22.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.202.00:34:22.98#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:22.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:23.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:23.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:23.04#ibcon#enter wrdev, iclass 13, count 2 2006.202.00:34:23.04#ibcon#first serial, iclass 13, count 2 2006.202.00:34:23.04#ibcon#enter sib2, iclass 13, count 2 2006.202.00:34:23.04#ibcon#flushed, iclass 13, count 2 2006.202.00:34:23.04#ibcon#about to write, iclass 13, count 2 2006.202.00:34:23.04#ibcon#wrote, iclass 13, count 2 2006.202.00:34:23.04#ibcon#about to read 3, iclass 13, count 2 2006.202.00:34:23.06#ibcon#read 3, iclass 13, count 2 2006.202.00:34:23.06#ibcon#about to read 4, iclass 13, count 2 2006.202.00:34:23.06#ibcon#read 4, iclass 13, count 2 2006.202.00:34:23.06#ibcon#about to read 5, iclass 13, count 2 2006.202.00:34:23.06#ibcon#read 5, iclass 13, count 2 2006.202.00:34:23.06#ibcon#about to read 6, iclass 13, count 2 2006.202.00:34:23.06#ibcon#read 6, iclass 13, count 2 2006.202.00:34:23.06#ibcon#end of sib2, iclass 13, count 2 2006.202.00:34:23.06#ibcon#*mode == 0, iclass 13, count 2 2006.202.00:34:23.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.202.00:34:23.06#ibcon#[25=AT03-08\r\n] 2006.202.00:34:23.06#ibcon#*before write, iclass 13, count 2 2006.202.00:34:23.06#ibcon#enter sib2, iclass 13, count 2 2006.202.00:34:23.06#ibcon#flushed, iclass 13, count 2 2006.202.00:34:23.06#ibcon#about to write, iclass 13, count 2 2006.202.00:34:23.06#ibcon#wrote, iclass 13, count 2 2006.202.00:34:23.06#ibcon#about to read 3, iclass 13, count 2 2006.202.00:34:23.09#ibcon#read 3, iclass 13, count 2 2006.202.00:34:23.09#ibcon#about to read 4, iclass 13, count 2 2006.202.00:34:23.09#ibcon#read 4, iclass 13, count 2 2006.202.00:34:23.09#ibcon#about to read 5, iclass 13, count 2 2006.202.00:34:23.09#ibcon#read 5, iclass 13, count 2 2006.202.00:34:23.09#ibcon#about to read 6, iclass 13, count 2 2006.202.00:34:23.09#ibcon#read 6, iclass 13, count 2 2006.202.00:34:23.09#ibcon#end of sib2, iclass 13, count 2 2006.202.00:34:23.09#ibcon#*after write, iclass 13, count 2 2006.202.00:34:23.09#ibcon#*before return 0, iclass 13, count 2 2006.202.00:34:23.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:23.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:23.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.202.00:34:23.09#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:23.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:23.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:23.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:23.21#ibcon#enter wrdev, iclass 13, count 0 2006.202.00:34:23.21#ibcon#first serial, iclass 13, count 0 2006.202.00:34:23.21#ibcon#enter sib2, iclass 13, count 0 2006.202.00:34:23.21#ibcon#flushed, iclass 13, count 0 2006.202.00:34:23.21#ibcon#about to write, iclass 13, count 0 2006.202.00:34:23.21#ibcon#wrote, iclass 13, count 0 2006.202.00:34:23.21#ibcon#about to read 3, iclass 13, count 0 2006.202.00:34:23.23#ibcon#read 3, iclass 13, count 0 2006.202.00:34:23.23#ibcon#about to read 4, iclass 13, count 0 2006.202.00:34:23.23#ibcon#read 4, iclass 13, count 0 2006.202.00:34:23.23#ibcon#about to read 5, iclass 13, count 0 2006.202.00:34:23.23#ibcon#read 5, iclass 13, count 0 2006.202.00:34:23.23#ibcon#about to read 6, iclass 13, count 0 2006.202.00:34:23.23#ibcon#read 6, iclass 13, count 0 2006.202.00:34:23.23#ibcon#end of sib2, iclass 13, count 0 2006.202.00:34:23.23#ibcon#*mode == 0, iclass 13, count 0 2006.202.00:34:23.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.00:34:23.23#ibcon#[25=USB\r\n] 2006.202.00:34:23.23#ibcon#*before write, iclass 13, count 0 2006.202.00:34:23.23#ibcon#enter sib2, iclass 13, count 0 2006.202.00:34:23.23#ibcon#flushed, iclass 13, count 0 2006.202.00:34:23.23#ibcon#about to write, iclass 13, count 0 2006.202.00:34:23.23#ibcon#wrote, iclass 13, count 0 2006.202.00:34:23.23#ibcon#about to read 3, iclass 13, count 0 2006.202.00:34:23.26#ibcon#read 3, iclass 13, count 0 2006.202.00:34:23.26#ibcon#about to read 4, iclass 13, count 0 2006.202.00:34:23.26#ibcon#read 4, iclass 13, count 0 2006.202.00:34:23.26#ibcon#about to read 5, iclass 13, count 0 2006.202.00:34:23.26#ibcon#read 5, iclass 13, count 0 2006.202.00:34:23.26#ibcon#about to read 6, iclass 13, count 0 2006.202.00:34:23.26#ibcon#read 6, iclass 13, count 0 2006.202.00:34:23.26#ibcon#end of sib2, iclass 13, count 0 2006.202.00:34:23.26#ibcon#*after write, iclass 13, count 0 2006.202.00:34:23.26#ibcon#*before return 0, iclass 13, count 0 2006.202.00:34:23.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:23.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:23.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.00:34:23.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.00:34:23.31$vck44/valo=4,624.99 2006.202.00:34:23.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.00:34:23.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.00:34:23.31#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:23.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:23.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:23.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:23.31#ibcon#enter wrdev, iclass 15, count 0 2006.202.00:34:23.31#ibcon#first serial, iclass 15, count 0 2006.202.00:34:23.31#ibcon#enter sib2, iclass 15, count 0 2006.202.00:34:23.31#ibcon#flushed, iclass 15, count 0 2006.202.00:34:23.31#ibcon#about to write, iclass 15, count 0 2006.202.00:34:23.31#ibcon#wrote, iclass 15, count 0 2006.202.00:34:23.31#ibcon#about to read 3, iclass 15, count 0 2006.202.00:34:23.33#ibcon#read 3, iclass 15, count 0 2006.202.00:34:23.33#ibcon#about to read 4, iclass 15, count 0 2006.202.00:34:23.33#ibcon#read 4, iclass 15, count 0 2006.202.00:34:23.33#ibcon#about to read 5, iclass 15, count 0 2006.202.00:34:23.33#ibcon#read 5, iclass 15, count 0 2006.202.00:34:23.33#ibcon#about to read 6, iclass 15, count 0 2006.202.00:34:23.33#ibcon#read 6, iclass 15, count 0 2006.202.00:34:23.33#ibcon#end of sib2, iclass 15, count 0 2006.202.00:34:23.33#ibcon#*mode == 0, iclass 15, count 0 2006.202.00:34:23.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.00:34:23.33#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.00:34:23.33#ibcon#*before write, iclass 15, count 0 2006.202.00:34:23.33#ibcon#enter sib2, iclass 15, count 0 2006.202.00:34:23.33#ibcon#flushed, iclass 15, count 0 2006.202.00:34:23.33#ibcon#about to write, iclass 15, count 0 2006.202.00:34:23.33#ibcon#wrote, iclass 15, count 0 2006.202.00:34:23.33#ibcon#about to read 3, iclass 15, count 0 2006.202.00:34:23.37#ibcon#read 3, iclass 15, count 0 2006.202.00:34:23.37#ibcon#about to read 4, iclass 15, count 0 2006.202.00:34:23.37#ibcon#read 4, iclass 15, count 0 2006.202.00:34:23.37#ibcon#about to read 5, iclass 15, count 0 2006.202.00:34:23.37#ibcon#read 5, iclass 15, count 0 2006.202.00:34:23.37#ibcon#about to read 6, iclass 15, count 0 2006.202.00:34:23.37#ibcon#read 6, iclass 15, count 0 2006.202.00:34:23.37#ibcon#end of sib2, iclass 15, count 0 2006.202.00:34:23.37#ibcon#*after write, iclass 15, count 0 2006.202.00:34:23.37#ibcon#*before return 0, iclass 15, count 0 2006.202.00:34:23.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:23.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:23.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.00:34:23.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.00:34:23.37$vck44/va=4,7 2006.202.00:34:23.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.202.00:34:23.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.202.00:34:23.37#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:23.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:23.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:23.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:23.37#ibcon#enter wrdev, iclass 17, count 2 2006.202.00:34:23.37#ibcon#first serial, iclass 17, count 2 2006.202.00:34:23.37#ibcon#enter sib2, iclass 17, count 2 2006.202.00:34:23.37#ibcon#flushed, iclass 17, count 2 2006.202.00:34:23.37#ibcon#about to write, iclass 17, count 2 2006.202.00:34:23.37#ibcon#wrote, iclass 17, count 2 2006.202.00:34:23.37#ibcon#about to read 3, iclass 17, count 2 2006.202.00:34:23.39#ibcon#read 3, iclass 17, count 2 2006.202.00:34:23.39#ibcon#about to read 4, iclass 17, count 2 2006.202.00:34:23.39#ibcon#read 4, iclass 17, count 2 2006.202.00:34:23.39#ibcon#about to read 5, iclass 17, count 2 2006.202.00:34:23.39#ibcon#read 5, iclass 17, count 2 2006.202.00:34:23.39#ibcon#about to read 6, iclass 17, count 2 2006.202.00:34:23.39#ibcon#read 6, iclass 17, count 2 2006.202.00:34:23.39#ibcon#end of sib2, iclass 17, count 2 2006.202.00:34:23.39#ibcon#*mode == 0, iclass 17, count 2 2006.202.00:34:23.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.202.00:34:23.39#ibcon#[25=AT04-07\r\n] 2006.202.00:34:23.39#ibcon#*before write, iclass 17, count 2 2006.202.00:34:23.39#ibcon#enter sib2, iclass 17, count 2 2006.202.00:34:23.39#ibcon#flushed, iclass 17, count 2 2006.202.00:34:23.39#ibcon#about to write, iclass 17, count 2 2006.202.00:34:23.39#ibcon#wrote, iclass 17, count 2 2006.202.00:34:23.39#ibcon#about to read 3, iclass 17, count 2 2006.202.00:34:23.42#ibcon#read 3, iclass 17, count 2 2006.202.00:34:23.42#ibcon#about to read 4, iclass 17, count 2 2006.202.00:34:23.42#ibcon#read 4, iclass 17, count 2 2006.202.00:34:23.42#ibcon#about to read 5, iclass 17, count 2 2006.202.00:34:23.42#ibcon#read 5, iclass 17, count 2 2006.202.00:34:23.42#ibcon#about to read 6, iclass 17, count 2 2006.202.00:34:23.42#ibcon#read 6, iclass 17, count 2 2006.202.00:34:23.42#ibcon#end of sib2, iclass 17, count 2 2006.202.00:34:23.42#ibcon#*after write, iclass 17, count 2 2006.202.00:34:23.42#ibcon#*before return 0, iclass 17, count 2 2006.202.00:34:23.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:23.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:23.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.202.00:34:23.42#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:23.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:23.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:23.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:23.54#ibcon#enter wrdev, iclass 17, count 0 2006.202.00:34:23.54#ibcon#first serial, iclass 17, count 0 2006.202.00:34:23.54#ibcon#enter sib2, iclass 17, count 0 2006.202.00:34:23.54#ibcon#flushed, iclass 17, count 0 2006.202.00:34:23.54#ibcon#about to write, iclass 17, count 0 2006.202.00:34:23.54#ibcon#wrote, iclass 17, count 0 2006.202.00:34:23.54#ibcon#about to read 3, iclass 17, count 0 2006.202.00:34:23.56#ibcon#read 3, iclass 17, count 0 2006.202.00:34:23.56#ibcon#about to read 4, iclass 17, count 0 2006.202.00:34:23.56#ibcon#read 4, iclass 17, count 0 2006.202.00:34:23.56#ibcon#about to read 5, iclass 17, count 0 2006.202.00:34:23.56#ibcon#read 5, iclass 17, count 0 2006.202.00:34:23.56#ibcon#about to read 6, iclass 17, count 0 2006.202.00:34:23.56#ibcon#read 6, iclass 17, count 0 2006.202.00:34:23.56#ibcon#end of sib2, iclass 17, count 0 2006.202.00:34:23.56#ibcon#*mode == 0, iclass 17, count 0 2006.202.00:34:23.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.00:34:23.56#ibcon#[25=USB\r\n] 2006.202.00:34:23.56#ibcon#*before write, iclass 17, count 0 2006.202.00:34:23.56#ibcon#enter sib2, iclass 17, count 0 2006.202.00:34:23.56#ibcon#flushed, iclass 17, count 0 2006.202.00:34:23.56#ibcon#about to write, iclass 17, count 0 2006.202.00:34:23.56#ibcon#wrote, iclass 17, count 0 2006.202.00:34:23.56#ibcon#about to read 3, iclass 17, count 0 2006.202.00:34:23.59#ibcon#read 3, iclass 17, count 0 2006.202.00:34:23.59#ibcon#about to read 4, iclass 17, count 0 2006.202.00:34:23.59#ibcon#read 4, iclass 17, count 0 2006.202.00:34:23.59#ibcon#about to read 5, iclass 17, count 0 2006.202.00:34:23.59#ibcon#read 5, iclass 17, count 0 2006.202.00:34:23.59#ibcon#about to read 6, iclass 17, count 0 2006.202.00:34:23.59#ibcon#read 6, iclass 17, count 0 2006.202.00:34:23.59#ibcon#end of sib2, iclass 17, count 0 2006.202.00:34:23.59#ibcon#*after write, iclass 17, count 0 2006.202.00:34:23.59#ibcon#*before return 0, iclass 17, count 0 2006.202.00:34:23.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:23.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:23.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.00:34:23.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.00:34:23.59$vck44/valo=5,734.99 2006.202.00:34:23.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.202.00:34:23.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.202.00:34:23.59#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:23.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:23.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:23.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:23.59#ibcon#enter wrdev, iclass 19, count 0 2006.202.00:34:23.59#ibcon#first serial, iclass 19, count 0 2006.202.00:34:23.59#ibcon#enter sib2, iclass 19, count 0 2006.202.00:34:23.59#ibcon#flushed, iclass 19, count 0 2006.202.00:34:23.59#ibcon#about to write, iclass 19, count 0 2006.202.00:34:23.59#ibcon#wrote, iclass 19, count 0 2006.202.00:34:23.59#ibcon#about to read 3, iclass 19, count 0 2006.202.00:34:23.61#ibcon#read 3, iclass 19, count 0 2006.202.00:34:23.61#ibcon#about to read 4, iclass 19, count 0 2006.202.00:34:23.61#ibcon#read 4, iclass 19, count 0 2006.202.00:34:23.61#ibcon#about to read 5, iclass 19, count 0 2006.202.00:34:23.61#ibcon#read 5, iclass 19, count 0 2006.202.00:34:23.61#ibcon#about to read 6, iclass 19, count 0 2006.202.00:34:23.61#ibcon#read 6, iclass 19, count 0 2006.202.00:34:23.61#ibcon#end of sib2, iclass 19, count 0 2006.202.00:34:23.61#ibcon#*mode == 0, iclass 19, count 0 2006.202.00:34:23.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.00:34:23.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.00:34:23.61#ibcon#*before write, iclass 19, count 0 2006.202.00:34:23.61#ibcon#enter sib2, iclass 19, count 0 2006.202.00:34:23.61#ibcon#flushed, iclass 19, count 0 2006.202.00:34:23.61#ibcon#about to write, iclass 19, count 0 2006.202.00:34:23.61#ibcon#wrote, iclass 19, count 0 2006.202.00:34:23.61#ibcon#about to read 3, iclass 19, count 0 2006.202.00:34:23.65#ibcon#read 3, iclass 19, count 0 2006.202.00:34:23.65#ibcon#about to read 4, iclass 19, count 0 2006.202.00:34:23.65#ibcon#read 4, iclass 19, count 0 2006.202.00:34:23.65#ibcon#about to read 5, iclass 19, count 0 2006.202.00:34:23.65#ibcon#read 5, iclass 19, count 0 2006.202.00:34:23.65#ibcon#about to read 6, iclass 19, count 0 2006.202.00:34:23.65#ibcon#read 6, iclass 19, count 0 2006.202.00:34:23.65#ibcon#end of sib2, iclass 19, count 0 2006.202.00:34:23.65#ibcon#*after write, iclass 19, count 0 2006.202.00:34:23.65#ibcon#*before return 0, iclass 19, count 0 2006.202.00:34:23.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:23.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:23.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.00:34:23.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.00:34:23.65$vck44/va=5,4 2006.202.00:34:23.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.202.00:34:23.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.202.00:34:23.65#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:23.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:23.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:23.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:23.71#ibcon#enter wrdev, iclass 21, count 2 2006.202.00:34:23.71#ibcon#first serial, iclass 21, count 2 2006.202.00:34:23.71#ibcon#enter sib2, iclass 21, count 2 2006.202.00:34:23.71#ibcon#flushed, iclass 21, count 2 2006.202.00:34:23.71#ibcon#about to write, iclass 21, count 2 2006.202.00:34:23.71#ibcon#wrote, iclass 21, count 2 2006.202.00:34:23.71#ibcon#about to read 3, iclass 21, count 2 2006.202.00:34:23.73#ibcon#read 3, iclass 21, count 2 2006.202.00:34:23.73#ibcon#about to read 4, iclass 21, count 2 2006.202.00:34:23.73#ibcon#read 4, iclass 21, count 2 2006.202.00:34:23.73#ibcon#about to read 5, iclass 21, count 2 2006.202.00:34:23.73#ibcon#read 5, iclass 21, count 2 2006.202.00:34:23.73#ibcon#about to read 6, iclass 21, count 2 2006.202.00:34:23.73#ibcon#read 6, iclass 21, count 2 2006.202.00:34:23.73#ibcon#end of sib2, iclass 21, count 2 2006.202.00:34:23.73#ibcon#*mode == 0, iclass 21, count 2 2006.202.00:34:23.73#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.202.00:34:23.73#ibcon#[25=AT05-04\r\n] 2006.202.00:34:23.73#ibcon#*before write, iclass 21, count 2 2006.202.00:34:23.73#ibcon#enter sib2, iclass 21, count 2 2006.202.00:34:23.73#ibcon#flushed, iclass 21, count 2 2006.202.00:34:23.73#ibcon#about to write, iclass 21, count 2 2006.202.00:34:23.73#ibcon#wrote, iclass 21, count 2 2006.202.00:34:23.73#ibcon#about to read 3, iclass 21, count 2 2006.202.00:34:23.76#ibcon#read 3, iclass 21, count 2 2006.202.00:34:23.76#ibcon#about to read 4, iclass 21, count 2 2006.202.00:34:23.76#ibcon#read 4, iclass 21, count 2 2006.202.00:34:23.76#ibcon#about to read 5, iclass 21, count 2 2006.202.00:34:23.76#ibcon#read 5, iclass 21, count 2 2006.202.00:34:23.76#ibcon#about to read 6, iclass 21, count 2 2006.202.00:34:23.76#ibcon#read 6, iclass 21, count 2 2006.202.00:34:23.76#ibcon#end of sib2, iclass 21, count 2 2006.202.00:34:23.76#ibcon#*after write, iclass 21, count 2 2006.202.00:34:23.76#ibcon#*before return 0, iclass 21, count 2 2006.202.00:34:23.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:23.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:23.76#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.202.00:34:23.76#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:23.76#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:23.88#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:23.88#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:23.88#ibcon#enter wrdev, iclass 21, count 0 2006.202.00:34:23.88#ibcon#first serial, iclass 21, count 0 2006.202.00:34:23.88#ibcon#enter sib2, iclass 21, count 0 2006.202.00:34:23.88#ibcon#flushed, iclass 21, count 0 2006.202.00:34:23.88#ibcon#about to write, iclass 21, count 0 2006.202.00:34:23.88#ibcon#wrote, iclass 21, count 0 2006.202.00:34:23.88#ibcon#about to read 3, iclass 21, count 0 2006.202.00:34:23.90#ibcon#read 3, iclass 21, count 0 2006.202.00:34:23.90#ibcon#about to read 4, iclass 21, count 0 2006.202.00:34:23.90#ibcon#read 4, iclass 21, count 0 2006.202.00:34:23.90#ibcon#about to read 5, iclass 21, count 0 2006.202.00:34:23.90#ibcon#read 5, iclass 21, count 0 2006.202.00:34:23.90#ibcon#about to read 6, iclass 21, count 0 2006.202.00:34:23.90#ibcon#read 6, iclass 21, count 0 2006.202.00:34:23.90#ibcon#end of sib2, iclass 21, count 0 2006.202.00:34:23.90#ibcon#*mode == 0, iclass 21, count 0 2006.202.00:34:23.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.00:34:23.90#ibcon#[25=USB\r\n] 2006.202.00:34:23.90#ibcon#*before write, iclass 21, count 0 2006.202.00:34:23.90#ibcon#enter sib2, iclass 21, count 0 2006.202.00:34:23.90#ibcon#flushed, iclass 21, count 0 2006.202.00:34:23.90#ibcon#about to write, iclass 21, count 0 2006.202.00:34:23.90#ibcon#wrote, iclass 21, count 0 2006.202.00:34:23.90#ibcon#about to read 3, iclass 21, count 0 2006.202.00:34:23.93#ibcon#read 3, iclass 21, count 0 2006.202.00:34:23.93#ibcon#about to read 4, iclass 21, count 0 2006.202.00:34:23.93#ibcon#read 4, iclass 21, count 0 2006.202.00:34:23.93#ibcon#about to read 5, iclass 21, count 0 2006.202.00:34:23.93#ibcon#read 5, iclass 21, count 0 2006.202.00:34:23.93#ibcon#about to read 6, iclass 21, count 0 2006.202.00:34:23.93#ibcon#read 6, iclass 21, count 0 2006.202.00:34:23.93#ibcon#end of sib2, iclass 21, count 0 2006.202.00:34:23.93#ibcon#*after write, iclass 21, count 0 2006.202.00:34:23.93#ibcon#*before return 0, iclass 21, count 0 2006.202.00:34:23.93#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:23.93#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:23.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.00:34:23.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.00:34:23.93$vck44/valo=6,814.99 2006.202.00:34:23.93#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.00:34:23.93#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.00:34:23.93#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:23.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:23.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:23.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:23.93#ibcon#enter wrdev, iclass 23, count 0 2006.202.00:34:23.93#ibcon#first serial, iclass 23, count 0 2006.202.00:34:23.93#ibcon#enter sib2, iclass 23, count 0 2006.202.00:34:23.93#ibcon#flushed, iclass 23, count 0 2006.202.00:34:23.93#ibcon#about to write, iclass 23, count 0 2006.202.00:34:23.93#ibcon#wrote, iclass 23, count 0 2006.202.00:34:23.93#ibcon#about to read 3, iclass 23, count 0 2006.202.00:34:23.95#ibcon#read 3, iclass 23, count 0 2006.202.00:34:23.95#ibcon#about to read 4, iclass 23, count 0 2006.202.00:34:23.95#ibcon#read 4, iclass 23, count 0 2006.202.00:34:23.95#ibcon#about to read 5, iclass 23, count 0 2006.202.00:34:23.95#ibcon#read 5, iclass 23, count 0 2006.202.00:34:23.95#ibcon#about to read 6, iclass 23, count 0 2006.202.00:34:23.95#ibcon#read 6, iclass 23, count 0 2006.202.00:34:23.95#ibcon#end of sib2, iclass 23, count 0 2006.202.00:34:23.95#ibcon#*mode == 0, iclass 23, count 0 2006.202.00:34:23.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.00:34:23.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.00:34:23.95#ibcon#*before write, iclass 23, count 0 2006.202.00:34:23.95#ibcon#enter sib2, iclass 23, count 0 2006.202.00:34:23.95#ibcon#flushed, iclass 23, count 0 2006.202.00:34:23.95#ibcon#about to write, iclass 23, count 0 2006.202.00:34:23.95#ibcon#wrote, iclass 23, count 0 2006.202.00:34:23.95#ibcon#about to read 3, iclass 23, count 0 2006.202.00:34:23.99#ibcon#read 3, iclass 23, count 0 2006.202.00:34:23.99#ibcon#about to read 4, iclass 23, count 0 2006.202.00:34:23.99#ibcon#read 4, iclass 23, count 0 2006.202.00:34:23.99#ibcon#about to read 5, iclass 23, count 0 2006.202.00:34:23.99#ibcon#read 5, iclass 23, count 0 2006.202.00:34:23.99#ibcon#about to read 6, iclass 23, count 0 2006.202.00:34:23.99#ibcon#read 6, iclass 23, count 0 2006.202.00:34:23.99#ibcon#end of sib2, iclass 23, count 0 2006.202.00:34:23.99#ibcon#*after write, iclass 23, count 0 2006.202.00:34:23.99#ibcon#*before return 0, iclass 23, count 0 2006.202.00:34:23.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:23.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:23.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.00:34:23.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.00:34:23.99$vck44/va=6,5 2006.202.00:34:23.99#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.202.00:34:23.99#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.202.00:34:23.99#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:23.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:24.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:24.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:24.05#ibcon#enter wrdev, iclass 25, count 2 2006.202.00:34:24.05#ibcon#first serial, iclass 25, count 2 2006.202.00:34:24.05#ibcon#enter sib2, iclass 25, count 2 2006.202.00:34:24.05#ibcon#flushed, iclass 25, count 2 2006.202.00:34:24.05#ibcon#about to write, iclass 25, count 2 2006.202.00:34:24.05#ibcon#wrote, iclass 25, count 2 2006.202.00:34:24.05#ibcon#about to read 3, iclass 25, count 2 2006.202.00:34:24.07#ibcon#read 3, iclass 25, count 2 2006.202.00:34:24.07#ibcon#about to read 4, iclass 25, count 2 2006.202.00:34:24.07#ibcon#read 4, iclass 25, count 2 2006.202.00:34:24.07#ibcon#about to read 5, iclass 25, count 2 2006.202.00:34:24.07#ibcon#read 5, iclass 25, count 2 2006.202.00:34:24.07#ibcon#about to read 6, iclass 25, count 2 2006.202.00:34:24.07#ibcon#read 6, iclass 25, count 2 2006.202.00:34:24.07#ibcon#end of sib2, iclass 25, count 2 2006.202.00:34:24.07#ibcon#*mode == 0, iclass 25, count 2 2006.202.00:34:24.07#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.202.00:34:24.07#ibcon#[25=AT06-05\r\n] 2006.202.00:34:24.07#ibcon#*before write, iclass 25, count 2 2006.202.00:34:24.07#ibcon#enter sib2, iclass 25, count 2 2006.202.00:34:24.07#ibcon#flushed, iclass 25, count 2 2006.202.00:34:24.07#ibcon#about to write, iclass 25, count 2 2006.202.00:34:24.07#ibcon#wrote, iclass 25, count 2 2006.202.00:34:24.07#ibcon#about to read 3, iclass 25, count 2 2006.202.00:34:24.10#ibcon#read 3, iclass 25, count 2 2006.202.00:34:24.10#ibcon#about to read 4, iclass 25, count 2 2006.202.00:34:24.10#ibcon#read 4, iclass 25, count 2 2006.202.00:34:24.10#ibcon#about to read 5, iclass 25, count 2 2006.202.00:34:24.10#ibcon#read 5, iclass 25, count 2 2006.202.00:34:24.10#ibcon#about to read 6, iclass 25, count 2 2006.202.00:34:24.10#ibcon#read 6, iclass 25, count 2 2006.202.00:34:24.10#ibcon#end of sib2, iclass 25, count 2 2006.202.00:34:24.10#ibcon#*after write, iclass 25, count 2 2006.202.00:34:24.10#ibcon#*before return 0, iclass 25, count 2 2006.202.00:34:24.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:24.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:24.10#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.202.00:34:24.10#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:24.10#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:24.22#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:24.22#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:24.22#ibcon#enter wrdev, iclass 25, count 0 2006.202.00:34:24.22#ibcon#first serial, iclass 25, count 0 2006.202.00:34:24.22#ibcon#enter sib2, iclass 25, count 0 2006.202.00:34:24.22#ibcon#flushed, iclass 25, count 0 2006.202.00:34:24.22#ibcon#about to write, iclass 25, count 0 2006.202.00:34:24.22#ibcon#wrote, iclass 25, count 0 2006.202.00:34:24.22#ibcon#about to read 3, iclass 25, count 0 2006.202.00:34:24.24#ibcon#read 3, iclass 25, count 0 2006.202.00:34:24.24#ibcon#about to read 4, iclass 25, count 0 2006.202.00:34:24.24#ibcon#read 4, iclass 25, count 0 2006.202.00:34:24.24#ibcon#about to read 5, iclass 25, count 0 2006.202.00:34:24.24#ibcon#read 5, iclass 25, count 0 2006.202.00:34:24.24#ibcon#about to read 6, iclass 25, count 0 2006.202.00:34:24.24#ibcon#read 6, iclass 25, count 0 2006.202.00:34:24.24#ibcon#end of sib2, iclass 25, count 0 2006.202.00:34:24.24#ibcon#*mode == 0, iclass 25, count 0 2006.202.00:34:24.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.00:34:24.24#ibcon#[25=USB\r\n] 2006.202.00:34:24.24#ibcon#*before write, iclass 25, count 0 2006.202.00:34:24.24#ibcon#enter sib2, iclass 25, count 0 2006.202.00:34:24.24#ibcon#flushed, iclass 25, count 0 2006.202.00:34:24.24#ibcon#about to write, iclass 25, count 0 2006.202.00:34:24.24#ibcon#wrote, iclass 25, count 0 2006.202.00:34:24.24#ibcon#about to read 3, iclass 25, count 0 2006.202.00:34:24.27#ibcon#read 3, iclass 25, count 0 2006.202.00:34:24.27#ibcon#about to read 4, iclass 25, count 0 2006.202.00:34:24.27#ibcon#read 4, iclass 25, count 0 2006.202.00:34:24.27#ibcon#about to read 5, iclass 25, count 0 2006.202.00:34:24.27#ibcon#read 5, iclass 25, count 0 2006.202.00:34:24.27#ibcon#about to read 6, iclass 25, count 0 2006.202.00:34:24.27#ibcon#read 6, iclass 25, count 0 2006.202.00:34:24.27#ibcon#end of sib2, iclass 25, count 0 2006.202.00:34:24.27#ibcon#*after write, iclass 25, count 0 2006.202.00:34:24.27#ibcon#*before return 0, iclass 25, count 0 2006.202.00:34:24.27#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:24.27#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:24.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.00:34:24.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.00:34:24.27$vck44/valo=7,864.99 2006.202.00:34:24.27#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.202.00:34:24.27#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.202.00:34:24.27#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:24.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:24.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:24.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:24.27#ibcon#enter wrdev, iclass 27, count 0 2006.202.00:34:24.27#ibcon#first serial, iclass 27, count 0 2006.202.00:34:24.27#ibcon#enter sib2, iclass 27, count 0 2006.202.00:34:24.27#ibcon#flushed, iclass 27, count 0 2006.202.00:34:24.27#ibcon#about to write, iclass 27, count 0 2006.202.00:34:24.27#ibcon#wrote, iclass 27, count 0 2006.202.00:34:24.27#ibcon#about to read 3, iclass 27, count 0 2006.202.00:34:24.29#ibcon#read 3, iclass 27, count 0 2006.202.00:34:24.29#ibcon#about to read 4, iclass 27, count 0 2006.202.00:34:24.29#ibcon#read 4, iclass 27, count 0 2006.202.00:34:24.29#ibcon#about to read 5, iclass 27, count 0 2006.202.00:34:24.29#ibcon#read 5, iclass 27, count 0 2006.202.00:34:24.29#ibcon#about to read 6, iclass 27, count 0 2006.202.00:34:24.29#ibcon#read 6, iclass 27, count 0 2006.202.00:34:24.29#ibcon#end of sib2, iclass 27, count 0 2006.202.00:34:24.29#ibcon#*mode == 0, iclass 27, count 0 2006.202.00:34:24.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.00:34:24.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.00:34:24.29#ibcon#*before write, iclass 27, count 0 2006.202.00:34:24.29#ibcon#enter sib2, iclass 27, count 0 2006.202.00:34:24.29#ibcon#flushed, iclass 27, count 0 2006.202.00:34:24.29#ibcon#about to write, iclass 27, count 0 2006.202.00:34:24.29#ibcon#wrote, iclass 27, count 0 2006.202.00:34:24.29#ibcon#about to read 3, iclass 27, count 0 2006.202.00:34:24.33#ibcon#read 3, iclass 27, count 0 2006.202.00:34:24.33#ibcon#about to read 4, iclass 27, count 0 2006.202.00:34:24.33#ibcon#read 4, iclass 27, count 0 2006.202.00:34:24.33#ibcon#about to read 5, iclass 27, count 0 2006.202.00:34:24.33#ibcon#read 5, iclass 27, count 0 2006.202.00:34:24.33#ibcon#about to read 6, iclass 27, count 0 2006.202.00:34:24.33#ibcon#read 6, iclass 27, count 0 2006.202.00:34:24.33#ibcon#end of sib2, iclass 27, count 0 2006.202.00:34:24.33#ibcon#*after write, iclass 27, count 0 2006.202.00:34:24.33#ibcon#*before return 0, iclass 27, count 0 2006.202.00:34:24.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:24.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:24.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.00:34:24.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.00:34:24.33$vck44/va=7,5 2006.202.00:34:24.33#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.00:34:24.33#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.00:34:24.33#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:24.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:24.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:24.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:24.39#ibcon#enter wrdev, iclass 29, count 2 2006.202.00:34:24.39#ibcon#first serial, iclass 29, count 2 2006.202.00:34:24.39#ibcon#enter sib2, iclass 29, count 2 2006.202.00:34:24.39#ibcon#flushed, iclass 29, count 2 2006.202.00:34:24.39#ibcon#about to write, iclass 29, count 2 2006.202.00:34:24.39#ibcon#wrote, iclass 29, count 2 2006.202.00:34:24.39#ibcon#about to read 3, iclass 29, count 2 2006.202.00:34:24.41#ibcon#read 3, iclass 29, count 2 2006.202.00:34:24.41#ibcon#about to read 4, iclass 29, count 2 2006.202.00:34:24.41#ibcon#read 4, iclass 29, count 2 2006.202.00:34:24.41#ibcon#about to read 5, iclass 29, count 2 2006.202.00:34:24.41#ibcon#read 5, iclass 29, count 2 2006.202.00:34:24.41#ibcon#about to read 6, iclass 29, count 2 2006.202.00:34:24.41#ibcon#read 6, iclass 29, count 2 2006.202.00:34:24.41#ibcon#end of sib2, iclass 29, count 2 2006.202.00:34:24.41#ibcon#*mode == 0, iclass 29, count 2 2006.202.00:34:24.41#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.00:34:24.41#ibcon#[25=AT07-05\r\n] 2006.202.00:34:24.41#ibcon#*before write, iclass 29, count 2 2006.202.00:34:24.41#ibcon#enter sib2, iclass 29, count 2 2006.202.00:34:24.41#ibcon#flushed, iclass 29, count 2 2006.202.00:34:24.41#ibcon#about to write, iclass 29, count 2 2006.202.00:34:24.41#ibcon#wrote, iclass 29, count 2 2006.202.00:34:24.41#ibcon#about to read 3, iclass 29, count 2 2006.202.00:34:24.44#ibcon#read 3, iclass 29, count 2 2006.202.00:34:24.44#ibcon#about to read 4, iclass 29, count 2 2006.202.00:34:24.44#ibcon#read 4, iclass 29, count 2 2006.202.00:34:24.44#ibcon#about to read 5, iclass 29, count 2 2006.202.00:34:24.44#ibcon#read 5, iclass 29, count 2 2006.202.00:34:24.44#ibcon#about to read 6, iclass 29, count 2 2006.202.00:34:24.44#ibcon#read 6, iclass 29, count 2 2006.202.00:34:24.44#ibcon#end of sib2, iclass 29, count 2 2006.202.00:34:24.44#ibcon#*after write, iclass 29, count 2 2006.202.00:34:24.44#ibcon#*before return 0, iclass 29, count 2 2006.202.00:34:24.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:24.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:24.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.00:34:24.44#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:24.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:24.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:24.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:24.56#ibcon#enter wrdev, iclass 29, count 0 2006.202.00:34:24.56#ibcon#first serial, iclass 29, count 0 2006.202.00:34:24.56#ibcon#enter sib2, iclass 29, count 0 2006.202.00:34:24.56#ibcon#flushed, iclass 29, count 0 2006.202.00:34:24.56#ibcon#about to write, iclass 29, count 0 2006.202.00:34:24.56#ibcon#wrote, iclass 29, count 0 2006.202.00:34:24.56#ibcon#about to read 3, iclass 29, count 0 2006.202.00:34:24.58#ibcon#read 3, iclass 29, count 0 2006.202.00:34:24.58#ibcon#about to read 4, iclass 29, count 0 2006.202.00:34:24.58#ibcon#read 4, iclass 29, count 0 2006.202.00:34:24.58#ibcon#about to read 5, iclass 29, count 0 2006.202.00:34:24.58#ibcon#read 5, iclass 29, count 0 2006.202.00:34:24.58#ibcon#about to read 6, iclass 29, count 0 2006.202.00:34:24.58#ibcon#read 6, iclass 29, count 0 2006.202.00:34:24.58#ibcon#end of sib2, iclass 29, count 0 2006.202.00:34:24.58#ibcon#*mode == 0, iclass 29, count 0 2006.202.00:34:24.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.00:34:24.58#ibcon#[25=USB\r\n] 2006.202.00:34:24.58#ibcon#*before write, iclass 29, count 0 2006.202.00:34:24.58#ibcon#enter sib2, iclass 29, count 0 2006.202.00:34:24.58#ibcon#flushed, iclass 29, count 0 2006.202.00:34:24.58#ibcon#about to write, iclass 29, count 0 2006.202.00:34:24.58#ibcon#wrote, iclass 29, count 0 2006.202.00:34:24.58#ibcon#about to read 3, iclass 29, count 0 2006.202.00:34:24.61#ibcon#read 3, iclass 29, count 0 2006.202.00:34:24.61#ibcon#about to read 4, iclass 29, count 0 2006.202.00:34:24.61#ibcon#read 4, iclass 29, count 0 2006.202.00:34:24.61#ibcon#about to read 5, iclass 29, count 0 2006.202.00:34:24.61#ibcon#read 5, iclass 29, count 0 2006.202.00:34:24.61#ibcon#about to read 6, iclass 29, count 0 2006.202.00:34:24.61#ibcon#read 6, iclass 29, count 0 2006.202.00:34:24.61#ibcon#end of sib2, iclass 29, count 0 2006.202.00:34:24.61#ibcon#*after write, iclass 29, count 0 2006.202.00:34:24.61#ibcon#*before return 0, iclass 29, count 0 2006.202.00:34:24.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:24.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:24.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.00:34:24.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.00:34:24.61$vck44/valo=8,884.99 2006.202.00:34:24.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.202.00:34:24.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.202.00:34:24.61#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:24.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:24.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:24.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:24.61#ibcon#enter wrdev, iclass 31, count 0 2006.202.00:34:24.61#ibcon#first serial, iclass 31, count 0 2006.202.00:34:24.61#ibcon#enter sib2, iclass 31, count 0 2006.202.00:34:24.61#ibcon#flushed, iclass 31, count 0 2006.202.00:34:24.61#ibcon#about to write, iclass 31, count 0 2006.202.00:34:24.61#ibcon#wrote, iclass 31, count 0 2006.202.00:34:24.61#ibcon#about to read 3, iclass 31, count 0 2006.202.00:34:24.63#ibcon#read 3, iclass 31, count 0 2006.202.00:34:24.63#ibcon#about to read 4, iclass 31, count 0 2006.202.00:34:24.63#ibcon#read 4, iclass 31, count 0 2006.202.00:34:24.63#ibcon#about to read 5, iclass 31, count 0 2006.202.00:34:24.63#ibcon#read 5, iclass 31, count 0 2006.202.00:34:24.63#ibcon#about to read 6, iclass 31, count 0 2006.202.00:34:24.63#ibcon#read 6, iclass 31, count 0 2006.202.00:34:24.63#ibcon#end of sib2, iclass 31, count 0 2006.202.00:34:24.63#ibcon#*mode == 0, iclass 31, count 0 2006.202.00:34:24.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.00:34:24.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.00:34:24.63#ibcon#*before write, iclass 31, count 0 2006.202.00:34:24.63#ibcon#enter sib2, iclass 31, count 0 2006.202.00:34:24.63#ibcon#flushed, iclass 31, count 0 2006.202.00:34:24.63#ibcon#about to write, iclass 31, count 0 2006.202.00:34:24.63#ibcon#wrote, iclass 31, count 0 2006.202.00:34:24.63#ibcon#about to read 3, iclass 31, count 0 2006.202.00:34:24.67#ibcon#read 3, iclass 31, count 0 2006.202.00:34:24.67#ibcon#about to read 4, iclass 31, count 0 2006.202.00:34:24.67#ibcon#read 4, iclass 31, count 0 2006.202.00:34:24.67#ibcon#about to read 5, iclass 31, count 0 2006.202.00:34:24.67#ibcon#read 5, iclass 31, count 0 2006.202.00:34:24.67#ibcon#about to read 6, iclass 31, count 0 2006.202.00:34:24.67#ibcon#read 6, iclass 31, count 0 2006.202.00:34:24.67#ibcon#end of sib2, iclass 31, count 0 2006.202.00:34:24.67#ibcon#*after write, iclass 31, count 0 2006.202.00:34:24.67#ibcon#*before return 0, iclass 31, count 0 2006.202.00:34:24.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:24.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:24.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.00:34:24.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.00:34:24.67$vck44/va=8,4 2006.202.00:34:24.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.202.00:34:24.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.202.00:34:24.67#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:24.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:34:24.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:34:24.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:34:24.73#ibcon#enter wrdev, iclass 33, count 2 2006.202.00:34:24.73#ibcon#first serial, iclass 33, count 2 2006.202.00:34:24.73#ibcon#enter sib2, iclass 33, count 2 2006.202.00:34:24.73#ibcon#flushed, iclass 33, count 2 2006.202.00:34:24.73#ibcon#about to write, iclass 33, count 2 2006.202.00:34:24.73#ibcon#wrote, iclass 33, count 2 2006.202.00:34:24.73#ibcon#about to read 3, iclass 33, count 2 2006.202.00:34:24.75#ibcon#read 3, iclass 33, count 2 2006.202.00:34:24.75#ibcon#about to read 4, iclass 33, count 2 2006.202.00:34:24.75#ibcon#read 4, iclass 33, count 2 2006.202.00:34:24.75#ibcon#about to read 5, iclass 33, count 2 2006.202.00:34:24.75#ibcon#read 5, iclass 33, count 2 2006.202.00:34:24.75#ibcon#about to read 6, iclass 33, count 2 2006.202.00:34:24.75#ibcon#read 6, iclass 33, count 2 2006.202.00:34:24.75#ibcon#end of sib2, iclass 33, count 2 2006.202.00:34:24.75#ibcon#*mode == 0, iclass 33, count 2 2006.202.00:34:24.75#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.202.00:34:24.75#ibcon#[25=AT08-04\r\n] 2006.202.00:34:24.75#ibcon#*before write, iclass 33, count 2 2006.202.00:34:24.75#ibcon#enter sib2, iclass 33, count 2 2006.202.00:34:24.75#ibcon#flushed, iclass 33, count 2 2006.202.00:34:24.75#ibcon#about to write, iclass 33, count 2 2006.202.00:34:24.75#ibcon#wrote, iclass 33, count 2 2006.202.00:34:24.75#ibcon#about to read 3, iclass 33, count 2 2006.202.00:34:24.78#ibcon#read 3, iclass 33, count 2 2006.202.00:34:24.78#ibcon#about to read 4, iclass 33, count 2 2006.202.00:34:24.78#ibcon#read 4, iclass 33, count 2 2006.202.00:34:24.78#ibcon#about to read 5, iclass 33, count 2 2006.202.00:34:24.78#ibcon#read 5, iclass 33, count 2 2006.202.00:34:24.78#ibcon#about to read 6, iclass 33, count 2 2006.202.00:34:24.78#ibcon#read 6, iclass 33, count 2 2006.202.00:34:24.78#ibcon#end of sib2, iclass 33, count 2 2006.202.00:34:24.78#ibcon#*after write, iclass 33, count 2 2006.202.00:34:24.78#ibcon#*before return 0, iclass 33, count 2 2006.202.00:34:24.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:34:24.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:34:24.78#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.202.00:34:24.78#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:24.78#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:34:24.90#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:34:24.90#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:34:24.90#ibcon#enter wrdev, iclass 33, count 0 2006.202.00:34:24.90#ibcon#first serial, iclass 33, count 0 2006.202.00:34:24.90#ibcon#enter sib2, iclass 33, count 0 2006.202.00:34:24.90#ibcon#flushed, iclass 33, count 0 2006.202.00:34:24.90#ibcon#about to write, iclass 33, count 0 2006.202.00:34:24.90#ibcon#wrote, iclass 33, count 0 2006.202.00:34:24.90#ibcon#about to read 3, iclass 33, count 0 2006.202.00:34:24.92#ibcon#read 3, iclass 33, count 0 2006.202.00:34:24.92#ibcon#about to read 4, iclass 33, count 0 2006.202.00:34:24.92#ibcon#read 4, iclass 33, count 0 2006.202.00:34:24.92#ibcon#about to read 5, iclass 33, count 0 2006.202.00:34:24.92#ibcon#read 5, iclass 33, count 0 2006.202.00:34:24.92#ibcon#about to read 6, iclass 33, count 0 2006.202.00:34:24.92#ibcon#read 6, iclass 33, count 0 2006.202.00:34:24.92#ibcon#end of sib2, iclass 33, count 0 2006.202.00:34:24.92#ibcon#*mode == 0, iclass 33, count 0 2006.202.00:34:24.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.00:34:24.92#ibcon#[25=USB\r\n] 2006.202.00:34:24.92#ibcon#*before write, iclass 33, count 0 2006.202.00:34:24.92#ibcon#enter sib2, iclass 33, count 0 2006.202.00:34:24.92#ibcon#flushed, iclass 33, count 0 2006.202.00:34:24.92#ibcon#about to write, iclass 33, count 0 2006.202.00:34:24.92#ibcon#wrote, iclass 33, count 0 2006.202.00:34:24.92#ibcon#about to read 3, iclass 33, count 0 2006.202.00:34:24.95#ibcon#read 3, iclass 33, count 0 2006.202.00:34:24.95#ibcon#about to read 4, iclass 33, count 0 2006.202.00:34:24.95#ibcon#read 4, iclass 33, count 0 2006.202.00:34:24.95#ibcon#about to read 5, iclass 33, count 0 2006.202.00:34:24.95#ibcon#read 5, iclass 33, count 0 2006.202.00:34:24.95#ibcon#about to read 6, iclass 33, count 0 2006.202.00:34:24.95#ibcon#read 6, iclass 33, count 0 2006.202.00:34:24.95#ibcon#end of sib2, iclass 33, count 0 2006.202.00:34:24.95#ibcon#*after write, iclass 33, count 0 2006.202.00:34:24.95#ibcon#*before return 0, iclass 33, count 0 2006.202.00:34:24.95#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:34:24.95#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:34:24.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.00:34:24.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.00:34:24.95$vck44/vblo=1,629.99 2006.202.00:34:24.95#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.202.00:34:24.95#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.202.00:34:24.95#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:24.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:34:24.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:34:24.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:34:24.95#ibcon#enter wrdev, iclass 35, count 0 2006.202.00:34:24.95#ibcon#first serial, iclass 35, count 0 2006.202.00:34:24.95#ibcon#enter sib2, iclass 35, count 0 2006.202.00:34:24.95#ibcon#flushed, iclass 35, count 0 2006.202.00:34:24.95#ibcon#about to write, iclass 35, count 0 2006.202.00:34:24.95#ibcon#wrote, iclass 35, count 0 2006.202.00:34:24.95#ibcon#about to read 3, iclass 35, count 0 2006.202.00:34:24.97#ibcon#read 3, iclass 35, count 0 2006.202.00:34:24.97#ibcon#about to read 4, iclass 35, count 0 2006.202.00:34:24.97#ibcon#read 4, iclass 35, count 0 2006.202.00:34:24.97#ibcon#about to read 5, iclass 35, count 0 2006.202.00:34:24.97#ibcon#read 5, iclass 35, count 0 2006.202.00:34:24.97#ibcon#about to read 6, iclass 35, count 0 2006.202.00:34:24.97#ibcon#read 6, iclass 35, count 0 2006.202.00:34:24.97#ibcon#end of sib2, iclass 35, count 0 2006.202.00:34:24.97#ibcon#*mode == 0, iclass 35, count 0 2006.202.00:34:24.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.00:34:24.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.00:34:24.97#ibcon#*before write, iclass 35, count 0 2006.202.00:34:24.97#ibcon#enter sib2, iclass 35, count 0 2006.202.00:34:24.97#ibcon#flushed, iclass 35, count 0 2006.202.00:34:24.97#ibcon#about to write, iclass 35, count 0 2006.202.00:34:24.97#ibcon#wrote, iclass 35, count 0 2006.202.00:34:24.97#ibcon#about to read 3, iclass 35, count 0 2006.202.00:34:25.01#ibcon#read 3, iclass 35, count 0 2006.202.00:34:25.01#ibcon#about to read 4, iclass 35, count 0 2006.202.00:34:25.01#ibcon#read 4, iclass 35, count 0 2006.202.00:34:25.01#ibcon#about to read 5, iclass 35, count 0 2006.202.00:34:25.01#ibcon#read 5, iclass 35, count 0 2006.202.00:34:25.01#ibcon#about to read 6, iclass 35, count 0 2006.202.00:34:25.01#ibcon#read 6, iclass 35, count 0 2006.202.00:34:25.01#ibcon#end of sib2, iclass 35, count 0 2006.202.00:34:25.01#ibcon#*after write, iclass 35, count 0 2006.202.00:34:25.01#ibcon#*before return 0, iclass 35, count 0 2006.202.00:34:25.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:34:25.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:34:25.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.00:34:25.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.00:34:25.01$vck44/vb=1,4 2006.202.00:34:25.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.202.00:34:25.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.202.00:34:25.01#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:25.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:34:25.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:34:25.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:34:25.01#ibcon#enter wrdev, iclass 37, count 2 2006.202.00:34:25.01#ibcon#first serial, iclass 37, count 2 2006.202.00:34:25.01#ibcon#enter sib2, iclass 37, count 2 2006.202.00:34:25.01#ibcon#flushed, iclass 37, count 2 2006.202.00:34:25.01#ibcon#about to write, iclass 37, count 2 2006.202.00:34:25.01#ibcon#wrote, iclass 37, count 2 2006.202.00:34:25.01#ibcon#about to read 3, iclass 37, count 2 2006.202.00:34:25.03#ibcon#read 3, iclass 37, count 2 2006.202.00:34:25.03#ibcon#about to read 4, iclass 37, count 2 2006.202.00:34:25.03#ibcon#read 4, iclass 37, count 2 2006.202.00:34:25.03#ibcon#about to read 5, iclass 37, count 2 2006.202.00:34:25.03#ibcon#read 5, iclass 37, count 2 2006.202.00:34:25.03#ibcon#about to read 6, iclass 37, count 2 2006.202.00:34:25.03#ibcon#read 6, iclass 37, count 2 2006.202.00:34:25.03#ibcon#end of sib2, iclass 37, count 2 2006.202.00:34:25.03#ibcon#*mode == 0, iclass 37, count 2 2006.202.00:34:25.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.202.00:34:25.03#ibcon#[27=AT01-04\r\n] 2006.202.00:34:25.03#ibcon#*before write, iclass 37, count 2 2006.202.00:34:25.03#ibcon#enter sib2, iclass 37, count 2 2006.202.00:34:25.03#ibcon#flushed, iclass 37, count 2 2006.202.00:34:25.03#ibcon#about to write, iclass 37, count 2 2006.202.00:34:25.03#ibcon#wrote, iclass 37, count 2 2006.202.00:34:25.03#ibcon#about to read 3, iclass 37, count 2 2006.202.00:34:25.06#ibcon#read 3, iclass 37, count 2 2006.202.00:34:25.06#ibcon#about to read 4, iclass 37, count 2 2006.202.00:34:25.06#ibcon#read 4, iclass 37, count 2 2006.202.00:34:25.06#ibcon#about to read 5, iclass 37, count 2 2006.202.00:34:25.06#ibcon#read 5, iclass 37, count 2 2006.202.00:34:25.06#ibcon#about to read 6, iclass 37, count 2 2006.202.00:34:25.06#ibcon#read 6, iclass 37, count 2 2006.202.00:34:25.06#ibcon#end of sib2, iclass 37, count 2 2006.202.00:34:25.06#ibcon#*after write, iclass 37, count 2 2006.202.00:34:25.06#ibcon#*before return 0, iclass 37, count 2 2006.202.00:34:25.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:34:25.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:34:25.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.202.00:34:25.06#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:25.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:34:25.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:34:25.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:34:25.18#ibcon#enter wrdev, iclass 37, count 0 2006.202.00:34:25.18#ibcon#first serial, iclass 37, count 0 2006.202.00:34:25.18#ibcon#enter sib2, iclass 37, count 0 2006.202.00:34:25.18#ibcon#flushed, iclass 37, count 0 2006.202.00:34:25.18#ibcon#about to write, iclass 37, count 0 2006.202.00:34:25.18#ibcon#wrote, iclass 37, count 0 2006.202.00:34:25.18#ibcon#about to read 3, iclass 37, count 0 2006.202.00:34:25.20#ibcon#read 3, iclass 37, count 0 2006.202.00:34:25.20#ibcon#about to read 4, iclass 37, count 0 2006.202.00:34:25.20#ibcon#read 4, iclass 37, count 0 2006.202.00:34:25.20#ibcon#about to read 5, iclass 37, count 0 2006.202.00:34:25.20#ibcon#read 5, iclass 37, count 0 2006.202.00:34:25.20#ibcon#about to read 6, iclass 37, count 0 2006.202.00:34:25.20#ibcon#read 6, iclass 37, count 0 2006.202.00:34:25.20#ibcon#end of sib2, iclass 37, count 0 2006.202.00:34:25.20#ibcon#*mode == 0, iclass 37, count 0 2006.202.00:34:25.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.00:34:25.20#ibcon#[27=USB\r\n] 2006.202.00:34:25.20#ibcon#*before write, iclass 37, count 0 2006.202.00:34:25.20#ibcon#enter sib2, iclass 37, count 0 2006.202.00:34:25.20#ibcon#flushed, iclass 37, count 0 2006.202.00:34:25.20#ibcon#about to write, iclass 37, count 0 2006.202.00:34:25.20#ibcon#wrote, iclass 37, count 0 2006.202.00:34:25.20#ibcon#about to read 3, iclass 37, count 0 2006.202.00:34:25.23#ibcon#read 3, iclass 37, count 0 2006.202.00:34:25.23#ibcon#about to read 4, iclass 37, count 0 2006.202.00:34:25.23#ibcon#read 4, iclass 37, count 0 2006.202.00:34:25.23#ibcon#about to read 5, iclass 37, count 0 2006.202.00:34:25.23#ibcon#read 5, iclass 37, count 0 2006.202.00:34:25.23#ibcon#about to read 6, iclass 37, count 0 2006.202.00:34:25.23#ibcon#read 6, iclass 37, count 0 2006.202.00:34:25.23#ibcon#end of sib2, iclass 37, count 0 2006.202.00:34:25.23#ibcon#*after write, iclass 37, count 0 2006.202.00:34:25.23#ibcon#*before return 0, iclass 37, count 0 2006.202.00:34:25.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:34:25.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:34:25.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.00:34:25.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.00:34:25.23$vck44/vblo=2,634.99 2006.202.00:34:25.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.202.00:34:25.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.202.00:34:25.23#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:25.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:25.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:25.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:25.23#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:34:25.23#ibcon#first serial, iclass 39, count 0 2006.202.00:34:25.23#ibcon#enter sib2, iclass 39, count 0 2006.202.00:34:25.23#ibcon#flushed, iclass 39, count 0 2006.202.00:34:25.23#ibcon#about to write, iclass 39, count 0 2006.202.00:34:25.23#ibcon#wrote, iclass 39, count 0 2006.202.00:34:25.23#ibcon#about to read 3, iclass 39, count 0 2006.202.00:34:25.25#ibcon#read 3, iclass 39, count 0 2006.202.00:34:25.25#ibcon#about to read 4, iclass 39, count 0 2006.202.00:34:25.25#ibcon#read 4, iclass 39, count 0 2006.202.00:34:25.25#ibcon#about to read 5, iclass 39, count 0 2006.202.00:34:25.25#ibcon#read 5, iclass 39, count 0 2006.202.00:34:25.25#ibcon#about to read 6, iclass 39, count 0 2006.202.00:34:25.25#ibcon#read 6, iclass 39, count 0 2006.202.00:34:25.25#ibcon#end of sib2, iclass 39, count 0 2006.202.00:34:25.25#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:34:25.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:34:25.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.00:34:25.25#ibcon#*before write, iclass 39, count 0 2006.202.00:34:25.25#ibcon#enter sib2, iclass 39, count 0 2006.202.00:34:25.25#ibcon#flushed, iclass 39, count 0 2006.202.00:34:25.25#ibcon#about to write, iclass 39, count 0 2006.202.00:34:25.25#ibcon#wrote, iclass 39, count 0 2006.202.00:34:25.25#ibcon#about to read 3, iclass 39, count 0 2006.202.00:34:25.29#ibcon#read 3, iclass 39, count 0 2006.202.00:34:25.29#ibcon#about to read 4, iclass 39, count 0 2006.202.00:34:25.29#ibcon#read 4, iclass 39, count 0 2006.202.00:34:25.29#ibcon#about to read 5, iclass 39, count 0 2006.202.00:34:25.29#ibcon#read 5, iclass 39, count 0 2006.202.00:34:25.29#ibcon#about to read 6, iclass 39, count 0 2006.202.00:34:25.29#ibcon#read 6, iclass 39, count 0 2006.202.00:34:25.29#ibcon#end of sib2, iclass 39, count 0 2006.202.00:34:25.29#ibcon#*after write, iclass 39, count 0 2006.202.00:34:25.29#ibcon#*before return 0, iclass 39, count 0 2006.202.00:34:25.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:25.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:34:25.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:34:25.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:34:25.29$vck44/vb=2,5 2006.202.00:34:25.29#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.202.00:34:25.29#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.202.00:34:25.29#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:25.29#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:25.35#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:25.35#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:25.35#ibcon#enter wrdev, iclass 2, count 2 2006.202.00:34:25.35#ibcon#first serial, iclass 2, count 2 2006.202.00:34:25.35#ibcon#enter sib2, iclass 2, count 2 2006.202.00:34:25.35#ibcon#flushed, iclass 2, count 2 2006.202.00:34:25.35#ibcon#about to write, iclass 2, count 2 2006.202.00:34:25.35#ibcon#wrote, iclass 2, count 2 2006.202.00:34:25.35#ibcon#about to read 3, iclass 2, count 2 2006.202.00:34:25.37#ibcon#read 3, iclass 2, count 2 2006.202.00:34:25.37#ibcon#about to read 4, iclass 2, count 2 2006.202.00:34:25.37#ibcon#read 4, iclass 2, count 2 2006.202.00:34:25.37#ibcon#about to read 5, iclass 2, count 2 2006.202.00:34:25.37#ibcon#read 5, iclass 2, count 2 2006.202.00:34:25.37#ibcon#about to read 6, iclass 2, count 2 2006.202.00:34:25.37#ibcon#read 6, iclass 2, count 2 2006.202.00:34:25.37#ibcon#end of sib2, iclass 2, count 2 2006.202.00:34:25.37#ibcon#*mode == 0, iclass 2, count 2 2006.202.00:34:25.37#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.202.00:34:25.37#ibcon#[27=AT02-05\r\n] 2006.202.00:34:25.37#ibcon#*before write, iclass 2, count 2 2006.202.00:34:25.37#ibcon#enter sib2, iclass 2, count 2 2006.202.00:34:25.37#ibcon#flushed, iclass 2, count 2 2006.202.00:34:25.37#ibcon#about to write, iclass 2, count 2 2006.202.00:34:25.37#ibcon#wrote, iclass 2, count 2 2006.202.00:34:25.37#ibcon#about to read 3, iclass 2, count 2 2006.202.00:34:25.40#ibcon#read 3, iclass 2, count 2 2006.202.00:34:25.40#ibcon#about to read 4, iclass 2, count 2 2006.202.00:34:25.40#ibcon#read 4, iclass 2, count 2 2006.202.00:34:25.40#ibcon#about to read 5, iclass 2, count 2 2006.202.00:34:25.40#ibcon#read 5, iclass 2, count 2 2006.202.00:34:25.40#ibcon#about to read 6, iclass 2, count 2 2006.202.00:34:25.40#ibcon#read 6, iclass 2, count 2 2006.202.00:34:25.40#ibcon#end of sib2, iclass 2, count 2 2006.202.00:34:25.40#ibcon#*after write, iclass 2, count 2 2006.202.00:34:25.40#ibcon#*before return 0, iclass 2, count 2 2006.202.00:34:25.40#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:25.40#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:34:25.40#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.202.00:34:25.40#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:25.40#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:25.52#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:25.52#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:25.52#ibcon#enter wrdev, iclass 2, count 0 2006.202.00:34:25.52#ibcon#first serial, iclass 2, count 0 2006.202.00:34:25.52#ibcon#enter sib2, iclass 2, count 0 2006.202.00:34:25.52#ibcon#flushed, iclass 2, count 0 2006.202.00:34:25.52#ibcon#about to write, iclass 2, count 0 2006.202.00:34:25.52#ibcon#wrote, iclass 2, count 0 2006.202.00:34:25.52#ibcon#about to read 3, iclass 2, count 0 2006.202.00:34:25.54#ibcon#read 3, iclass 2, count 0 2006.202.00:34:25.54#ibcon#about to read 4, iclass 2, count 0 2006.202.00:34:25.54#ibcon#read 4, iclass 2, count 0 2006.202.00:34:25.54#ibcon#about to read 5, iclass 2, count 0 2006.202.00:34:25.54#ibcon#read 5, iclass 2, count 0 2006.202.00:34:25.54#ibcon#about to read 6, iclass 2, count 0 2006.202.00:34:25.54#ibcon#read 6, iclass 2, count 0 2006.202.00:34:25.54#ibcon#end of sib2, iclass 2, count 0 2006.202.00:34:25.54#ibcon#*mode == 0, iclass 2, count 0 2006.202.00:34:25.54#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.00:34:25.54#ibcon#[27=USB\r\n] 2006.202.00:34:25.54#ibcon#*before write, iclass 2, count 0 2006.202.00:34:25.54#ibcon#enter sib2, iclass 2, count 0 2006.202.00:34:25.54#ibcon#flushed, iclass 2, count 0 2006.202.00:34:25.54#ibcon#about to write, iclass 2, count 0 2006.202.00:34:25.54#ibcon#wrote, iclass 2, count 0 2006.202.00:34:25.54#ibcon#about to read 3, iclass 2, count 0 2006.202.00:34:25.57#ibcon#read 3, iclass 2, count 0 2006.202.00:34:25.57#ibcon#about to read 4, iclass 2, count 0 2006.202.00:34:25.57#ibcon#read 4, iclass 2, count 0 2006.202.00:34:25.57#ibcon#about to read 5, iclass 2, count 0 2006.202.00:34:25.57#ibcon#read 5, iclass 2, count 0 2006.202.00:34:25.57#ibcon#about to read 6, iclass 2, count 0 2006.202.00:34:25.57#ibcon#read 6, iclass 2, count 0 2006.202.00:34:25.57#ibcon#end of sib2, iclass 2, count 0 2006.202.00:34:25.57#ibcon#*after write, iclass 2, count 0 2006.202.00:34:25.57#ibcon#*before return 0, iclass 2, count 0 2006.202.00:34:25.57#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:25.57#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:34:25.57#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.00:34:25.57#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.00:34:25.57$vck44/vblo=3,649.99 2006.202.00:34:25.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.202.00:34:25.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.202.00:34:25.57#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:25.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:25.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:25.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:25.57#ibcon#enter wrdev, iclass 5, count 0 2006.202.00:34:25.57#ibcon#first serial, iclass 5, count 0 2006.202.00:34:25.57#ibcon#enter sib2, iclass 5, count 0 2006.202.00:34:25.57#ibcon#flushed, iclass 5, count 0 2006.202.00:34:25.57#ibcon#about to write, iclass 5, count 0 2006.202.00:34:25.57#ibcon#wrote, iclass 5, count 0 2006.202.00:34:25.57#ibcon#about to read 3, iclass 5, count 0 2006.202.00:34:25.59#ibcon#read 3, iclass 5, count 0 2006.202.00:34:25.59#ibcon#about to read 4, iclass 5, count 0 2006.202.00:34:25.59#ibcon#read 4, iclass 5, count 0 2006.202.00:34:25.59#ibcon#about to read 5, iclass 5, count 0 2006.202.00:34:25.59#ibcon#read 5, iclass 5, count 0 2006.202.00:34:25.59#ibcon#about to read 6, iclass 5, count 0 2006.202.00:34:25.59#ibcon#read 6, iclass 5, count 0 2006.202.00:34:25.59#ibcon#end of sib2, iclass 5, count 0 2006.202.00:34:25.59#ibcon#*mode == 0, iclass 5, count 0 2006.202.00:34:25.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.00:34:25.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.00:34:25.59#ibcon#*before write, iclass 5, count 0 2006.202.00:34:25.59#ibcon#enter sib2, iclass 5, count 0 2006.202.00:34:25.59#ibcon#flushed, iclass 5, count 0 2006.202.00:34:25.59#ibcon#about to write, iclass 5, count 0 2006.202.00:34:25.59#ibcon#wrote, iclass 5, count 0 2006.202.00:34:25.59#ibcon#about to read 3, iclass 5, count 0 2006.202.00:34:25.63#ibcon#read 3, iclass 5, count 0 2006.202.00:34:25.63#ibcon#about to read 4, iclass 5, count 0 2006.202.00:34:25.63#ibcon#read 4, iclass 5, count 0 2006.202.00:34:25.63#ibcon#about to read 5, iclass 5, count 0 2006.202.00:34:25.63#ibcon#read 5, iclass 5, count 0 2006.202.00:34:25.63#ibcon#about to read 6, iclass 5, count 0 2006.202.00:34:25.63#ibcon#read 6, iclass 5, count 0 2006.202.00:34:25.63#ibcon#end of sib2, iclass 5, count 0 2006.202.00:34:25.63#ibcon#*after write, iclass 5, count 0 2006.202.00:34:25.63#ibcon#*before return 0, iclass 5, count 0 2006.202.00:34:25.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:25.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:34:25.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.00:34:25.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.00:34:25.63$vck44/vb=3,4 2006.202.00:34:25.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.202.00:34:25.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.202.00:34:25.63#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:25.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:25.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:25.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:25.69#ibcon#enter wrdev, iclass 7, count 2 2006.202.00:34:25.69#ibcon#first serial, iclass 7, count 2 2006.202.00:34:25.69#ibcon#enter sib2, iclass 7, count 2 2006.202.00:34:25.69#ibcon#flushed, iclass 7, count 2 2006.202.00:34:25.69#ibcon#about to write, iclass 7, count 2 2006.202.00:34:25.69#ibcon#wrote, iclass 7, count 2 2006.202.00:34:25.69#ibcon#about to read 3, iclass 7, count 2 2006.202.00:34:25.71#ibcon#read 3, iclass 7, count 2 2006.202.00:34:25.71#ibcon#about to read 4, iclass 7, count 2 2006.202.00:34:25.71#ibcon#read 4, iclass 7, count 2 2006.202.00:34:25.71#ibcon#about to read 5, iclass 7, count 2 2006.202.00:34:25.71#ibcon#read 5, iclass 7, count 2 2006.202.00:34:25.71#ibcon#about to read 6, iclass 7, count 2 2006.202.00:34:25.71#ibcon#read 6, iclass 7, count 2 2006.202.00:34:25.71#ibcon#end of sib2, iclass 7, count 2 2006.202.00:34:25.71#ibcon#*mode == 0, iclass 7, count 2 2006.202.00:34:25.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.202.00:34:25.71#ibcon#[27=AT03-04\r\n] 2006.202.00:34:25.71#ibcon#*before write, iclass 7, count 2 2006.202.00:34:25.71#ibcon#enter sib2, iclass 7, count 2 2006.202.00:34:25.71#ibcon#flushed, iclass 7, count 2 2006.202.00:34:25.71#ibcon#about to write, iclass 7, count 2 2006.202.00:34:25.71#ibcon#wrote, iclass 7, count 2 2006.202.00:34:25.71#ibcon#about to read 3, iclass 7, count 2 2006.202.00:34:25.74#ibcon#read 3, iclass 7, count 2 2006.202.00:34:25.74#ibcon#about to read 4, iclass 7, count 2 2006.202.00:34:25.74#ibcon#read 4, iclass 7, count 2 2006.202.00:34:25.74#ibcon#about to read 5, iclass 7, count 2 2006.202.00:34:25.74#ibcon#read 5, iclass 7, count 2 2006.202.00:34:25.74#ibcon#about to read 6, iclass 7, count 2 2006.202.00:34:25.74#ibcon#read 6, iclass 7, count 2 2006.202.00:34:25.74#ibcon#end of sib2, iclass 7, count 2 2006.202.00:34:25.74#ibcon#*after write, iclass 7, count 2 2006.202.00:34:25.74#ibcon#*before return 0, iclass 7, count 2 2006.202.00:34:25.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:25.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:34:25.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.202.00:34:25.74#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:25.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:25.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:25.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:25.86#ibcon#enter wrdev, iclass 7, count 0 2006.202.00:34:25.86#ibcon#first serial, iclass 7, count 0 2006.202.00:34:25.86#ibcon#enter sib2, iclass 7, count 0 2006.202.00:34:25.86#ibcon#flushed, iclass 7, count 0 2006.202.00:34:25.86#ibcon#about to write, iclass 7, count 0 2006.202.00:34:25.86#ibcon#wrote, iclass 7, count 0 2006.202.00:34:25.86#ibcon#about to read 3, iclass 7, count 0 2006.202.00:34:25.88#ibcon#read 3, iclass 7, count 0 2006.202.00:34:25.88#ibcon#about to read 4, iclass 7, count 0 2006.202.00:34:25.88#ibcon#read 4, iclass 7, count 0 2006.202.00:34:25.88#ibcon#about to read 5, iclass 7, count 0 2006.202.00:34:25.88#ibcon#read 5, iclass 7, count 0 2006.202.00:34:25.88#ibcon#about to read 6, iclass 7, count 0 2006.202.00:34:25.88#ibcon#read 6, iclass 7, count 0 2006.202.00:34:25.88#ibcon#end of sib2, iclass 7, count 0 2006.202.00:34:25.88#ibcon#*mode == 0, iclass 7, count 0 2006.202.00:34:25.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.00:34:25.88#ibcon#[27=USB\r\n] 2006.202.00:34:25.88#ibcon#*before write, iclass 7, count 0 2006.202.00:34:25.88#ibcon#enter sib2, iclass 7, count 0 2006.202.00:34:25.88#ibcon#flushed, iclass 7, count 0 2006.202.00:34:25.88#ibcon#about to write, iclass 7, count 0 2006.202.00:34:25.88#ibcon#wrote, iclass 7, count 0 2006.202.00:34:25.88#ibcon#about to read 3, iclass 7, count 0 2006.202.00:34:25.91#ibcon#read 3, iclass 7, count 0 2006.202.00:34:25.91#ibcon#about to read 4, iclass 7, count 0 2006.202.00:34:25.91#ibcon#read 4, iclass 7, count 0 2006.202.00:34:25.91#ibcon#about to read 5, iclass 7, count 0 2006.202.00:34:25.91#ibcon#read 5, iclass 7, count 0 2006.202.00:34:25.91#ibcon#about to read 6, iclass 7, count 0 2006.202.00:34:25.91#ibcon#read 6, iclass 7, count 0 2006.202.00:34:25.91#ibcon#end of sib2, iclass 7, count 0 2006.202.00:34:25.91#ibcon#*after write, iclass 7, count 0 2006.202.00:34:25.91#ibcon#*before return 0, iclass 7, count 0 2006.202.00:34:25.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:25.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:34:25.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.00:34:25.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.00:34:25.91$vck44/vblo=4,679.99 2006.202.00:34:25.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.202.00:34:25.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.202.00:34:25.91#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:25.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:25.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:25.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:25.91#ibcon#enter wrdev, iclass 11, count 0 2006.202.00:34:25.91#ibcon#first serial, iclass 11, count 0 2006.202.00:34:25.91#ibcon#enter sib2, iclass 11, count 0 2006.202.00:34:25.91#ibcon#flushed, iclass 11, count 0 2006.202.00:34:25.91#ibcon#about to write, iclass 11, count 0 2006.202.00:34:25.91#ibcon#wrote, iclass 11, count 0 2006.202.00:34:25.91#ibcon#about to read 3, iclass 11, count 0 2006.202.00:34:25.93#ibcon#read 3, iclass 11, count 0 2006.202.00:34:25.93#ibcon#about to read 4, iclass 11, count 0 2006.202.00:34:25.93#ibcon#read 4, iclass 11, count 0 2006.202.00:34:25.93#ibcon#about to read 5, iclass 11, count 0 2006.202.00:34:25.93#ibcon#read 5, iclass 11, count 0 2006.202.00:34:25.93#ibcon#about to read 6, iclass 11, count 0 2006.202.00:34:25.93#ibcon#read 6, iclass 11, count 0 2006.202.00:34:25.93#ibcon#end of sib2, iclass 11, count 0 2006.202.00:34:25.93#ibcon#*mode == 0, iclass 11, count 0 2006.202.00:34:25.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.00:34:25.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.00:34:25.93#ibcon#*before write, iclass 11, count 0 2006.202.00:34:25.93#ibcon#enter sib2, iclass 11, count 0 2006.202.00:34:25.93#ibcon#flushed, iclass 11, count 0 2006.202.00:34:25.93#ibcon#about to write, iclass 11, count 0 2006.202.00:34:25.93#ibcon#wrote, iclass 11, count 0 2006.202.00:34:25.93#ibcon#about to read 3, iclass 11, count 0 2006.202.00:34:25.97#ibcon#read 3, iclass 11, count 0 2006.202.00:34:25.97#ibcon#about to read 4, iclass 11, count 0 2006.202.00:34:25.97#ibcon#read 4, iclass 11, count 0 2006.202.00:34:25.97#ibcon#about to read 5, iclass 11, count 0 2006.202.00:34:25.97#ibcon#read 5, iclass 11, count 0 2006.202.00:34:25.97#ibcon#about to read 6, iclass 11, count 0 2006.202.00:34:25.97#ibcon#read 6, iclass 11, count 0 2006.202.00:34:25.97#ibcon#end of sib2, iclass 11, count 0 2006.202.00:34:25.97#ibcon#*after write, iclass 11, count 0 2006.202.00:34:25.97#ibcon#*before return 0, iclass 11, count 0 2006.202.00:34:25.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:25.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:34:25.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.00:34:25.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.00:34:25.97$vck44/vb=4,5 2006.202.00:34:25.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.202.00:34:25.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.202.00:34:25.97#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:25.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:26.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:26.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:26.03#ibcon#enter wrdev, iclass 13, count 2 2006.202.00:34:26.03#ibcon#first serial, iclass 13, count 2 2006.202.00:34:26.03#ibcon#enter sib2, iclass 13, count 2 2006.202.00:34:26.03#ibcon#flushed, iclass 13, count 2 2006.202.00:34:26.03#ibcon#about to write, iclass 13, count 2 2006.202.00:34:26.03#ibcon#wrote, iclass 13, count 2 2006.202.00:34:26.03#ibcon#about to read 3, iclass 13, count 2 2006.202.00:34:26.05#ibcon#read 3, iclass 13, count 2 2006.202.00:34:26.05#ibcon#about to read 4, iclass 13, count 2 2006.202.00:34:26.05#ibcon#read 4, iclass 13, count 2 2006.202.00:34:26.05#ibcon#about to read 5, iclass 13, count 2 2006.202.00:34:26.05#ibcon#read 5, iclass 13, count 2 2006.202.00:34:26.05#ibcon#about to read 6, iclass 13, count 2 2006.202.00:34:26.05#ibcon#read 6, iclass 13, count 2 2006.202.00:34:26.05#ibcon#end of sib2, iclass 13, count 2 2006.202.00:34:26.05#ibcon#*mode == 0, iclass 13, count 2 2006.202.00:34:26.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.202.00:34:26.05#ibcon#[27=AT04-05\r\n] 2006.202.00:34:26.05#ibcon#*before write, iclass 13, count 2 2006.202.00:34:26.05#ibcon#enter sib2, iclass 13, count 2 2006.202.00:34:26.05#ibcon#flushed, iclass 13, count 2 2006.202.00:34:26.05#ibcon#about to write, iclass 13, count 2 2006.202.00:34:26.05#ibcon#wrote, iclass 13, count 2 2006.202.00:34:26.05#ibcon#about to read 3, iclass 13, count 2 2006.202.00:34:26.08#ibcon#read 3, iclass 13, count 2 2006.202.00:34:26.08#ibcon#about to read 4, iclass 13, count 2 2006.202.00:34:26.08#ibcon#read 4, iclass 13, count 2 2006.202.00:34:26.08#ibcon#about to read 5, iclass 13, count 2 2006.202.00:34:26.08#ibcon#read 5, iclass 13, count 2 2006.202.00:34:26.08#ibcon#about to read 6, iclass 13, count 2 2006.202.00:34:26.08#ibcon#read 6, iclass 13, count 2 2006.202.00:34:26.08#ibcon#end of sib2, iclass 13, count 2 2006.202.00:34:26.08#ibcon#*after write, iclass 13, count 2 2006.202.00:34:26.08#ibcon#*before return 0, iclass 13, count 2 2006.202.00:34:26.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:26.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:34:26.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.202.00:34:26.08#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:26.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:26.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:26.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:26.20#ibcon#enter wrdev, iclass 13, count 0 2006.202.00:34:26.20#ibcon#first serial, iclass 13, count 0 2006.202.00:34:26.20#ibcon#enter sib2, iclass 13, count 0 2006.202.00:34:26.20#ibcon#flushed, iclass 13, count 0 2006.202.00:34:26.20#ibcon#about to write, iclass 13, count 0 2006.202.00:34:26.20#ibcon#wrote, iclass 13, count 0 2006.202.00:34:26.20#ibcon#about to read 3, iclass 13, count 0 2006.202.00:34:26.22#ibcon#read 3, iclass 13, count 0 2006.202.00:34:26.22#ibcon#about to read 4, iclass 13, count 0 2006.202.00:34:26.22#ibcon#read 4, iclass 13, count 0 2006.202.00:34:26.22#ibcon#about to read 5, iclass 13, count 0 2006.202.00:34:26.22#ibcon#read 5, iclass 13, count 0 2006.202.00:34:26.22#ibcon#about to read 6, iclass 13, count 0 2006.202.00:34:26.22#ibcon#read 6, iclass 13, count 0 2006.202.00:34:26.22#ibcon#end of sib2, iclass 13, count 0 2006.202.00:34:26.22#ibcon#*mode == 0, iclass 13, count 0 2006.202.00:34:26.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.00:34:26.22#ibcon#[27=USB\r\n] 2006.202.00:34:26.22#ibcon#*before write, iclass 13, count 0 2006.202.00:34:26.22#ibcon#enter sib2, iclass 13, count 0 2006.202.00:34:26.22#ibcon#flushed, iclass 13, count 0 2006.202.00:34:26.22#ibcon#about to write, iclass 13, count 0 2006.202.00:34:26.22#ibcon#wrote, iclass 13, count 0 2006.202.00:34:26.22#ibcon#about to read 3, iclass 13, count 0 2006.202.00:34:26.25#ibcon#read 3, iclass 13, count 0 2006.202.00:34:26.25#ibcon#about to read 4, iclass 13, count 0 2006.202.00:34:26.25#ibcon#read 4, iclass 13, count 0 2006.202.00:34:26.25#ibcon#about to read 5, iclass 13, count 0 2006.202.00:34:26.25#ibcon#read 5, iclass 13, count 0 2006.202.00:34:26.25#ibcon#about to read 6, iclass 13, count 0 2006.202.00:34:26.25#ibcon#read 6, iclass 13, count 0 2006.202.00:34:26.25#ibcon#end of sib2, iclass 13, count 0 2006.202.00:34:26.25#ibcon#*after write, iclass 13, count 0 2006.202.00:34:26.25#ibcon#*before return 0, iclass 13, count 0 2006.202.00:34:26.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:26.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:34:26.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.00:34:26.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.00:34:26.25$vck44/vblo=5,709.99 2006.202.00:34:26.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.00:34:26.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.00:34:26.25#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:26.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:26.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:26.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:26.25#ibcon#enter wrdev, iclass 15, count 0 2006.202.00:34:26.25#ibcon#first serial, iclass 15, count 0 2006.202.00:34:26.25#ibcon#enter sib2, iclass 15, count 0 2006.202.00:34:26.25#ibcon#flushed, iclass 15, count 0 2006.202.00:34:26.25#ibcon#about to write, iclass 15, count 0 2006.202.00:34:26.25#ibcon#wrote, iclass 15, count 0 2006.202.00:34:26.25#ibcon#about to read 3, iclass 15, count 0 2006.202.00:34:26.27#ibcon#read 3, iclass 15, count 0 2006.202.00:34:26.27#ibcon#about to read 4, iclass 15, count 0 2006.202.00:34:26.27#ibcon#read 4, iclass 15, count 0 2006.202.00:34:26.27#ibcon#about to read 5, iclass 15, count 0 2006.202.00:34:26.27#ibcon#read 5, iclass 15, count 0 2006.202.00:34:26.27#ibcon#about to read 6, iclass 15, count 0 2006.202.00:34:26.27#ibcon#read 6, iclass 15, count 0 2006.202.00:34:26.27#ibcon#end of sib2, iclass 15, count 0 2006.202.00:34:26.27#ibcon#*mode == 0, iclass 15, count 0 2006.202.00:34:26.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.00:34:26.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.00:34:26.27#ibcon#*before write, iclass 15, count 0 2006.202.00:34:26.27#ibcon#enter sib2, iclass 15, count 0 2006.202.00:34:26.27#ibcon#flushed, iclass 15, count 0 2006.202.00:34:26.27#ibcon#about to write, iclass 15, count 0 2006.202.00:34:26.27#ibcon#wrote, iclass 15, count 0 2006.202.00:34:26.27#ibcon#about to read 3, iclass 15, count 0 2006.202.00:34:26.31#ibcon#read 3, iclass 15, count 0 2006.202.00:34:26.31#ibcon#about to read 4, iclass 15, count 0 2006.202.00:34:26.31#ibcon#read 4, iclass 15, count 0 2006.202.00:34:26.31#ibcon#about to read 5, iclass 15, count 0 2006.202.00:34:26.31#ibcon#read 5, iclass 15, count 0 2006.202.00:34:26.31#ibcon#about to read 6, iclass 15, count 0 2006.202.00:34:26.31#ibcon#read 6, iclass 15, count 0 2006.202.00:34:26.31#ibcon#end of sib2, iclass 15, count 0 2006.202.00:34:26.31#ibcon#*after write, iclass 15, count 0 2006.202.00:34:26.31#ibcon#*before return 0, iclass 15, count 0 2006.202.00:34:26.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:26.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:34:26.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.00:34:26.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.00:34:26.31$vck44/vb=5,4 2006.202.00:34:26.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.202.00:34:26.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.202.00:34:26.31#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:26.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:26.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:26.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:26.37#ibcon#enter wrdev, iclass 17, count 2 2006.202.00:34:26.37#ibcon#first serial, iclass 17, count 2 2006.202.00:34:26.37#ibcon#enter sib2, iclass 17, count 2 2006.202.00:34:26.37#ibcon#flushed, iclass 17, count 2 2006.202.00:34:26.37#ibcon#about to write, iclass 17, count 2 2006.202.00:34:26.37#ibcon#wrote, iclass 17, count 2 2006.202.00:34:26.37#ibcon#about to read 3, iclass 17, count 2 2006.202.00:34:26.39#ibcon#read 3, iclass 17, count 2 2006.202.00:34:26.39#ibcon#about to read 4, iclass 17, count 2 2006.202.00:34:26.39#ibcon#read 4, iclass 17, count 2 2006.202.00:34:26.39#ibcon#about to read 5, iclass 17, count 2 2006.202.00:34:26.39#ibcon#read 5, iclass 17, count 2 2006.202.00:34:26.39#ibcon#about to read 6, iclass 17, count 2 2006.202.00:34:26.39#ibcon#read 6, iclass 17, count 2 2006.202.00:34:26.39#ibcon#end of sib2, iclass 17, count 2 2006.202.00:34:26.39#ibcon#*mode == 0, iclass 17, count 2 2006.202.00:34:26.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.202.00:34:26.39#ibcon#[27=AT05-04\r\n] 2006.202.00:34:26.39#ibcon#*before write, iclass 17, count 2 2006.202.00:34:26.39#ibcon#enter sib2, iclass 17, count 2 2006.202.00:34:26.39#ibcon#flushed, iclass 17, count 2 2006.202.00:34:26.39#ibcon#about to write, iclass 17, count 2 2006.202.00:34:26.39#ibcon#wrote, iclass 17, count 2 2006.202.00:34:26.39#ibcon#about to read 3, iclass 17, count 2 2006.202.00:34:26.42#ibcon#read 3, iclass 17, count 2 2006.202.00:34:26.42#ibcon#about to read 4, iclass 17, count 2 2006.202.00:34:26.42#ibcon#read 4, iclass 17, count 2 2006.202.00:34:26.42#ibcon#about to read 5, iclass 17, count 2 2006.202.00:34:26.42#ibcon#read 5, iclass 17, count 2 2006.202.00:34:26.42#ibcon#about to read 6, iclass 17, count 2 2006.202.00:34:26.42#ibcon#read 6, iclass 17, count 2 2006.202.00:34:26.42#ibcon#end of sib2, iclass 17, count 2 2006.202.00:34:26.42#ibcon#*after write, iclass 17, count 2 2006.202.00:34:26.42#ibcon#*before return 0, iclass 17, count 2 2006.202.00:34:26.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:26.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:34:26.47#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.202.00:34:26.47#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:26.47#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:26.59#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:26.59#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:26.59#ibcon#enter wrdev, iclass 17, count 0 2006.202.00:34:26.59#ibcon#first serial, iclass 17, count 0 2006.202.00:34:26.59#ibcon#enter sib2, iclass 17, count 0 2006.202.00:34:26.59#ibcon#flushed, iclass 17, count 0 2006.202.00:34:26.59#ibcon#about to write, iclass 17, count 0 2006.202.00:34:26.59#ibcon#wrote, iclass 17, count 0 2006.202.00:34:26.59#ibcon#about to read 3, iclass 17, count 0 2006.202.00:34:26.61#ibcon#read 3, iclass 17, count 0 2006.202.00:34:26.61#ibcon#about to read 4, iclass 17, count 0 2006.202.00:34:26.61#ibcon#read 4, iclass 17, count 0 2006.202.00:34:26.61#ibcon#about to read 5, iclass 17, count 0 2006.202.00:34:26.61#ibcon#read 5, iclass 17, count 0 2006.202.00:34:26.61#ibcon#about to read 6, iclass 17, count 0 2006.202.00:34:26.61#ibcon#read 6, iclass 17, count 0 2006.202.00:34:26.61#ibcon#end of sib2, iclass 17, count 0 2006.202.00:34:26.61#ibcon#*mode == 0, iclass 17, count 0 2006.202.00:34:26.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.00:34:26.61#ibcon#[27=USB\r\n] 2006.202.00:34:26.61#ibcon#*before write, iclass 17, count 0 2006.202.00:34:26.61#ibcon#enter sib2, iclass 17, count 0 2006.202.00:34:26.61#ibcon#flushed, iclass 17, count 0 2006.202.00:34:26.61#ibcon#about to write, iclass 17, count 0 2006.202.00:34:26.61#ibcon#wrote, iclass 17, count 0 2006.202.00:34:26.61#ibcon#about to read 3, iclass 17, count 0 2006.202.00:34:26.64#ibcon#read 3, iclass 17, count 0 2006.202.00:34:26.64#ibcon#about to read 4, iclass 17, count 0 2006.202.00:34:26.64#ibcon#read 4, iclass 17, count 0 2006.202.00:34:26.64#ibcon#about to read 5, iclass 17, count 0 2006.202.00:34:26.64#ibcon#read 5, iclass 17, count 0 2006.202.00:34:26.64#ibcon#about to read 6, iclass 17, count 0 2006.202.00:34:26.64#ibcon#read 6, iclass 17, count 0 2006.202.00:34:26.64#ibcon#end of sib2, iclass 17, count 0 2006.202.00:34:26.64#ibcon#*after write, iclass 17, count 0 2006.202.00:34:26.64#ibcon#*before return 0, iclass 17, count 0 2006.202.00:34:26.64#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:26.64#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:34:26.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.00:34:26.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.00:34:26.64$vck44/vblo=6,719.99 2006.202.00:34:26.64#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.202.00:34:26.64#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.202.00:34:26.64#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:26.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:26.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:26.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:26.64#ibcon#enter wrdev, iclass 19, count 0 2006.202.00:34:26.64#ibcon#first serial, iclass 19, count 0 2006.202.00:34:26.64#ibcon#enter sib2, iclass 19, count 0 2006.202.00:34:26.64#ibcon#flushed, iclass 19, count 0 2006.202.00:34:26.64#ibcon#about to write, iclass 19, count 0 2006.202.00:34:26.64#ibcon#wrote, iclass 19, count 0 2006.202.00:34:26.64#ibcon#about to read 3, iclass 19, count 0 2006.202.00:34:26.66#ibcon#read 3, iclass 19, count 0 2006.202.00:34:26.66#ibcon#about to read 4, iclass 19, count 0 2006.202.00:34:26.66#ibcon#read 4, iclass 19, count 0 2006.202.00:34:26.66#ibcon#about to read 5, iclass 19, count 0 2006.202.00:34:26.66#ibcon#read 5, iclass 19, count 0 2006.202.00:34:26.66#ibcon#about to read 6, iclass 19, count 0 2006.202.00:34:26.66#ibcon#read 6, iclass 19, count 0 2006.202.00:34:26.66#ibcon#end of sib2, iclass 19, count 0 2006.202.00:34:26.66#ibcon#*mode == 0, iclass 19, count 0 2006.202.00:34:26.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.00:34:26.66#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.00:34:26.66#ibcon#*before write, iclass 19, count 0 2006.202.00:34:26.66#ibcon#enter sib2, iclass 19, count 0 2006.202.00:34:26.66#ibcon#flushed, iclass 19, count 0 2006.202.00:34:26.66#ibcon#about to write, iclass 19, count 0 2006.202.00:34:26.66#ibcon#wrote, iclass 19, count 0 2006.202.00:34:26.66#ibcon#about to read 3, iclass 19, count 0 2006.202.00:34:26.70#ibcon#read 3, iclass 19, count 0 2006.202.00:34:26.70#ibcon#about to read 4, iclass 19, count 0 2006.202.00:34:26.70#ibcon#read 4, iclass 19, count 0 2006.202.00:34:26.70#ibcon#about to read 5, iclass 19, count 0 2006.202.00:34:26.70#ibcon#read 5, iclass 19, count 0 2006.202.00:34:26.70#ibcon#about to read 6, iclass 19, count 0 2006.202.00:34:26.70#ibcon#read 6, iclass 19, count 0 2006.202.00:34:26.70#ibcon#end of sib2, iclass 19, count 0 2006.202.00:34:26.70#ibcon#*after write, iclass 19, count 0 2006.202.00:34:26.70#ibcon#*before return 0, iclass 19, count 0 2006.202.00:34:26.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:26.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:34:26.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.00:34:26.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.00:34:26.70$vck44/vb=6,4 2006.202.00:34:26.70#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.202.00:34:26.70#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.202.00:34:26.70#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:26.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:26.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:26.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:26.76#ibcon#enter wrdev, iclass 21, count 2 2006.202.00:34:26.76#ibcon#first serial, iclass 21, count 2 2006.202.00:34:26.76#ibcon#enter sib2, iclass 21, count 2 2006.202.00:34:26.76#ibcon#flushed, iclass 21, count 2 2006.202.00:34:26.76#ibcon#about to write, iclass 21, count 2 2006.202.00:34:26.76#ibcon#wrote, iclass 21, count 2 2006.202.00:34:26.76#ibcon#about to read 3, iclass 21, count 2 2006.202.00:34:26.78#ibcon#read 3, iclass 21, count 2 2006.202.00:34:26.78#ibcon#about to read 4, iclass 21, count 2 2006.202.00:34:26.78#ibcon#read 4, iclass 21, count 2 2006.202.00:34:26.78#ibcon#about to read 5, iclass 21, count 2 2006.202.00:34:26.78#ibcon#read 5, iclass 21, count 2 2006.202.00:34:26.78#ibcon#about to read 6, iclass 21, count 2 2006.202.00:34:26.78#ibcon#read 6, iclass 21, count 2 2006.202.00:34:26.78#ibcon#end of sib2, iclass 21, count 2 2006.202.00:34:26.78#ibcon#*mode == 0, iclass 21, count 2 2006.202.00:34:26.78#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.202.00:34:26.78#ibcon#[27=AT06-04\r\n] 2006.202.00:34:26.78#ibcon#*before write, iclass 21, count 2 2006.202.00:34:26.78#ibcon#enter sib2, iclass 21, count 2 2006.202.00:34:26.78#ibcon#flushed, iclass 21, count 2 2006.202.00:34:26.78#ibcon#about to write, iclass 21, count 2 2006.202.00:34:26.78#ibcon#wrote, iclass 21, count 2 2006.202.00:34:26.78#ibcon#about to read 3, iclass 21, count 2 2006.202.00:34:26.81#ibcon#read 3, iclass 21, count 2 2006.202.00:34:26.81#ibcon#about to read 4, iclass 21, count 2 2006.202.00:34:26.81#ibcon#read 4, iclass 21, count 2 2006.202.00:34:26.81#ibcon#about to read 5, iclass 21, count 2 2006.202.00:34:26.81#ibcon#read 5, iclass 21, count 2 2006.202.00:34:26.81#ibcon#about to read 6, iclass 21, count 2 2006.202.00:34:26.81#ibcon#read 6, iclass 21, count 2 2006.202.00:34:26.81#ibcon#end of sib2, iclass 21, count 2 2006.202.00:34:26.81#ibcon#*after write, iclass 21, count 2 2006.202.00:34:26.81#ibcon#*before return 0, iclass 21, count 2 2006.202.00:34:26.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:26.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:34:26.81#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.202.00:34:26.81#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:26.81#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:26.93#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:26.93#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:26.93#ibcon#enter wrdev, iclass 21, count 0 2006.202.00:34:26.93#ibcon#first serial, iclass 21, count 0 2006.202.00:34:26.93#ibcon#enter sib2, iclass 21, count 0 2006.202.00:34:26.93#ibcon#flushed, iclass 21, count 0 2006.202.00:34:26.93#ibcon#about to write, iclass 21, count 0 2006.202.00:34:26.93#ibcon#wrote, iclass 21, count 0 2006.202.00:34:26.93#ibcon#about to read 3, iclass 21, count 0 2006.202.00:34:26.95#ibcon#read 3, iclass 21, count 0 2006.202.00:34:26.95#ibcon#about to read 4, iclass 21, count 0 2006.202.00:34:26.95#ibcon#read 4, iclass 21, count 0 2006.202.00:34:26.95#ibcon#about to read 5, iclass 21, count 0 2006.202.00:34:26.95#ibcon#read 5, iclass 21, count 0 2006.202.00:34:26.95#ibcon#about to read 6, iclass 21, count 0 2006.202.00:34:26.95#ibcon#read 6, iclass 21, count 0 2006.202.00:34:26.95#ibcon#end of sib2, iclass 21, count 0 2006.202.00:34:26.95#ibcon#*mode == 0, iclass 21, count 0 2006.202.00:34:26.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.00:34:26.95#ibcon#[27=USB\r\n] 2006.202.00:34:26.95#ibcon#*before write, iclass 21, count 0 2006.202.00:34:26.95#ibcon#enter sib2, iclass 21, count 0 2006.202.00:34:26.95#ibcon#flushed, iclass 21, count 0 2006.202.00:34:26.95#ibcon#about to write, iclass 21, count 0 2006.202.00:34:26.95#ibcon#wrote, iclass 21, count 0 2006.202.00:34:26.95#ibcon#about to read 3, iclass 21, count 0 2006.202.00:34:26.98#ibcon#read 3, iclass 21, count 0 2006.202.00:34:26.98#ibcon#about to read 4, iclass 21, count 0 2006.202.00:34:26.98#ibcon#read 4, iclass 21, count 0 2006.202.00:34:26.98#ibcon#about to read 5, iclass 21, count 0 2006.202.00:34:26.98#ibcon#read 5, iclass 21, count 0 2006.202.00:34:26.98#ibcon#about to read 6, iclass 21, count 0 2006.202.00:34:26.98#ibcon#read 6, iclass 21, count 0 2006.202.00:34:26.98#ibcon#end of sib2, iclass 21, count 0 2006.202.00:34:26.98#ibcon#*after write, iclass 21, count 0 2006.202.00:34:26.98#ibcon#*before return 0, iclass 21, count 0 2006.202.00:34:26.98#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:26.98#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:34:26.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.00:34:26.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.00:34:26.98$vck44/vblo=7,734.99 2006.202.00:34:26.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.00:34:26.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.00:34:26.98#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:26.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:26.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:26.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:26.98#ibcon#enter wrdev, iclass 23, count 0 2006.202.00:34:26.98#ibcon#first serial, iclass 23, count 0 2006.202.00:34:26.98#ibcon#enter sib2, iclass 23, count 0 2006.202.00:34:26.98#ibcon#flushed, iclass 23, count 0 2006.202.00:34:26.98#ibcon#about to write, iclass 23, count 0 2006.202.00:34:26.98#ibcon#wrote, iclass 23, count 0 2006.202.00:34:26.98#ibcon#about to read 3, iclass 23, count 0 2006.202.00:34:27.00#ibcon#read 3, iclass 23, count 0 2006.202.00:34:27.00#ibcon#about to read 4, iclass 23, count 0 2006.202.00:34:27.00#ibcon#read 4, iclass 23, count 0 2006.202.00:34:27.00#ibcon#about to read 5, iclass 23, count 0 2006.202.00:34:27.00#ibcon#read 5, iclass 23, count 0 2006.202.00:34:27.00#ibcon#about to read 6, iclass 23, count 0 2006.202.00:34:27.00#ibcon#read 6, iclass 23, count 0 2006.202.00:34:27.00#ibcon#end of sib2, iclass 23, count 0 2006.202.00:34:27.00#ibcon#*mode == 0, iclass 23, count 0 2006.202.00:34:27.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.00:34:27.00#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.00:34:27.00#ibcon#*before write, iclass 23, count 0 2006.202.00:34:27.00#ibcon#enter sib2, iclass 23, count 0 2006.202.00:34:27.00#ibcon#flushed, iclass 23, count 0 2006.202.00:34:27.00#ibcon#about to write, iclass 23, count 0 2006.202.00:34:27.00#ibcon#wrote, iclass 23, count 0 2006.202.00:34:27.00#ibcon#about to read 3, iclass 23, count 0 2006.202.00:34:27.04#ibcon#read 3, iclass 23, count 0 2006.202.00:34:27.04#ibcon#about to read 4, iclass 23, count 0 2006.202.00:34:27.04#ibcon#read 4, iclass 23, count 0 2006.202.00:34:27.04#ibcon#about to read 5, iclass 23, count 0 2006.202.00:34:27.04#ibcon#read 5, iclass 23, count 0 2006.202.00:34:27.04#ibcon#about to read 6, iclass 23, count 0 2006.202.00:34:27.04#ibcon#read 6, iclass 23, count 0 2006.202.00:34:27.04#ibcon#end of sib2, iclass 23, count 0 2006.202.00:34:27.04#ibcon#*after write, iclass 23, count 0 2006.202.00:34:27.04#ibcon#*before return 0, iclass 23, count 0 2006.202.00:34:27.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:27.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:34:27.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.00:34:27.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.00:34:27.04$vck44/vb=7,4 2006.202.00:34:27.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.202.00:34:27.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.202.00:34:27.04#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:27.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:27.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:27.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:27.10#ibcon#enter wrdev, iclass 25, count 2 2006.202.00:34:27.10#ibcon#first serial, iclass 25, count 2 2006.202.00:34:27.10#ibcon#enter sib2, iclass 25, count 2 2006.202.00:34:27.10#ibcon#flushed, iclass 25, count 2 2006.202.00:34:27.10#ibcon#about to write, iclass 25, count 2 2006.202.00:34:27.10#ibcon#wrote, iclass 25, count 2 2006.202.00:34:27.10#ibcon#about to read 3, iclass 25, count 2 2006.202.00:34:27.12#ibcon#read 3, iclass 25, count 2 2006.202.00:34:27.12#ibcon#about to read 4, iclass 25, count 2 2006.202.00:34:27.12#ibcon#read 4, iclass 25, count 2 2006.202.00:34:27.12#ibcon#about to read 5, iclass 25, count 2 2006.202.00:34:27.12#ibcon#read 5, iclass 25, count 2 2006.202.00:34:27.12#ibcon#about to read 6, iclass 25, count 2 2006.202.00:34:27.12#ibcon#read 6, iclass 25, count 2 2006.202.00:34:27.12#ibcon#end of sib2, iclass 25, count 2 2006.202.00:34:27.12#ibcon#*mode == 0, iclass 25, count 2 2006.202.00:34:27.12#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.202.00:34:27.12#ibcon#[27=AT07-04\r\n] 2006.202.00:34:27.12#ibcon#*before write, iclass 25, count 2 2006.202.00:34:27.12#ibcon#enter sib2, iclass 25, count 2 2006.202.00:34:27.12#ibcon#flushed, iclass 25, count 2 2006.202.00:34:27.12#ibcon#about to write, iclass 25, count 2 2006.202.00:34:27.12#ibcon#wrote, iclass 25, count 2 2006.202.00:34:27.12#ibcon#about to read 3, iclass 25, count 2 2006.202.00:34:27.15#ibcon#read 3, iclass 25, count 2 2006.202.00:34:27.15#ibcon#about to read 4, iclass 25, count 2 2006.202.00:34:27.15#ibcon#read 4, iclass 25, count 2 2006.202.00:34:27.15#ibcon#about to read 5, iclass 25, count 2 2006.202.00:34:27.15#ibcon#read 5, iclass 25, count 2 2006.202.00:34:27.15#ibcon#about to read 6, iclass 25, count 2 2006.202.00:34:27.15#ibcon#read 6, iclass 25, count 2 2006.202.00:34:27.15#ibcon#end of sib2, iclass 25, count 2 2006.202.00:34:27.15#ibcon#*after write, iclass 25, count 2 2006.202.00:34:27.15#ibcon#*before return 0, iclass 25, count 2 2006.202.00:34:27.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:27.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:34:27.15#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.202.00:34:27.15#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:27.15#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:27.27#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:27.27#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:27.27#ibcon#enter wrdev, iclass 25, count 0 2006.202.00:34:27.27#ibcon#first serial, iclass 25, count 0 2006.202.00:34:27.27#ibcon#enter sib2, iclass 25, count 0 2006.202.00:34:27.27#ibcon#flushed, iclass 25, count 0 2006.202.00:34:27.27#ibcon#about to write, iclass 25, count 0 2006.202.00:34:27.27#ibcon#wrote, iclass 25, count 0 2006.202.00:34:27.27#ibcon#about to read 3, iclass 25, count 0 2006.202.00:34:27.29#ibcon#read 3, iclass 25, count 0 2006.202.00:34:27.29#ibcon#about to read 4, iclass 25, count 0 2006.202.00:34:27.29#ibcon#read 4, iclass 25, count 0 2006.202.00:34:27.29#ibcon#about to read 5, iclass 25, count 0 2006.202.00:34:27.29#ibcon#read 5, iclass 25, count 0 2006.202.00:34:27.29#ibcon#about to read 6, iclass 25, count 0 2006.202.00:34:27.29#ibcon#read 6, iclass 25, count 0 2006.202.00:34:27.29#ibcon#end of sib2, iclass 25, count 0 2006.202.00:34:27.29#ibcon#*mode == 0, iclass 25, count 0 2006.202.00:34:27.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.00:34:27.29#ibcon#[27=USB\r\n] 2006.202.00:34:27.29#ibcon#*before write, iclass 25, count 0 2006.202.00:34:27.29#ibcon#enter sib2, iclass 25, count 0 2006.202.00:34:27.29#ibcon#flushed, iclass 25, count 0 2006.202.00:34:27.29#ibcon#about to write, iclass 25, count 0 2006.202.00:34:27.29#ibcon#wrote, iclass 25, count 0 2006.202.00:34:27.29#ibcon#about to read 3, iclass 25, count 0 2006.202.00:34:27.32#ibcon#read 3, iclass 25, count 0 2006.202.00:34:27.32#ibcon#about to read 4, iclass 25, count 0 2006.202.00:34:27.32#ibcon#read 4, iclass 25, count 0 2006.202.00:34:27.32#ibcon#about to read 5, iclass 25, count 0 2006.202.00:34:27.32#ibcon#read 5, iclass 25, count 0 2006.202.00:34:27.32#ibcon#about to read 6, iclass 25, count 0 2006.202.00:34:27.32#ibcon#read 6, iclass 25, count 0 2006.202.00:34:27.32#ibcon#end of sib2, iclass 25, count 0 2006.202.00:34:27.32#ibcon#*after write, iclass 25, count 0 2006.202.00:34:27.32#ibcon#*before return 0, iclass 25, count 0 2006.202.00:34:27.32#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:27.32#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:34:27.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.00:34:27.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.00:34:27.32$vck44/vblo=8,744.99 2006.202.00:34:27.32#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.202.00:34:27.32#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.202.00:34:27.32#ibcon#ireg 17 cls_cnt 0 2006.202.00:34:27.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:27.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:27.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:27.32#ibcon#enter wrdev, iclass 27, count 0 2006.202.00:34:27.32#ibcon#first serial, iclass 27, count 0 2006.202.00:34:27.32#ibcon#enter sib2, iclass 27, count 0 2006.202.00:34:27.32#ibcon#flushed, iclass 27, count 0 2006.202.00:34:27.32#ibcon#about to write, iclass 27, count 0 2006.202.00:34:27.32#ibcon#wrote, iclass 27, count 0 2006.202.00:34:27.32#ibcon#about to read 3, iclass 27, count 0 2006.202.00:34:27.34#ibcon#read 3, iclass 27, count 0 2006.202.00:34:27.34#ibcon#about to read 4, iclass 27, count 0 2006.202.00:34:27.34#ibcon#read 4, iclass 27, count 0 2006.202.00:34:27.34#ibcon#about to read 5, iclass 27, count 0 2006.202.00:34:27.34#ibcon#read 5, iclass 27, count 0 2006.202.00:34:27.34#ibcon#about to read 6, iclass 27, count 0 2006.202.00:34:27.34#ibcon#read 6, iclass 27, count 0 2006.202.00:34:27.34#ibcon#end of sib2, iclass 27, count 0 2006.202.00:34:27.34#ibcon#*mode == 0, iclass 27, count 0 2006.202.00:34:27.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.00:34:27.34#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.00:34:27.34#ibcon#*before write, iclass 27, count 0 2006.202.00:34:27.34#ibcon#enter sib2, iclass 27, count 0 2006.202.00:34:27.34#ibcon#flushed, iclass 27, count 0 2006.202.00:34:27.34#ibcon#about to write, iclass 27, count 0 2006.202.00:34:27.34#ibcon#wrote, iclass 27, count 0 2006.202.00:34:27.34#ibcon#about to read 3, iclass 27, count 0 2006.202.00:34:27.38#ibcon#read 3, iclass 27, count 0 2006.202.00:34:27.38#ibcon#about to read 4, iclass 27, count 0 2006.202.00:34:27.38#ibcon#read 4, iclass 27, count 0 2006.202.00:34:27.38#ibcon#about to read 5, iclass 27, count 0 2006.202.00:34:27.38#ibcon#read 5, iclass 27, count 0 2006.202.00:34:27.38#ibcon#about to read 6, iclass 27, count 0 2006.202.00:34:27.38#ibcon#read 6, iclass 27, count 0 2006.202.00:34:27.38#ibcon#end of sib2, iclass 27, count 0 2006.202.00:34:27.38#ibcon#*after write, iclass 27, count 0 2006.202.00:34:27.38#ibcon#*before return 0, iclass 27, count 0 2006.202.00:34:27.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:27.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:34:27.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.00:34:27.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.00:34:27.38$vck44/vb=8,4 2006.202.00:34:27.38#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.00:34:27.38#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.00:34:27.38#ibcon#ireg 11 cls_cnt 2 2006.202.00:34:27.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:27.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:27.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:27.44#ibcon#enter wrdev, iclass 29, count 2 2006.202.00:34:27.44#ibcon#first serial, iclass 29, count 2 2006.202.00:34:27.44#ibcon#enter sib2, iclass 29, count 2 2006.202.00:34:27.44#ibcon#flushed, iclass 29, count 2 2006.202.00:34:27.44#ibcon#about to write, iclass 29, count 2 2006.202.00:34:27.44#ibcon#wrote, iclass 29, count 2 2006.202.00:34:27.44#ibcon#about to read 3, iclass 29, count 2 2006.202.00:34:27.46#ibcon#read 3, iclass 29, count 2 2006.202.00:34:27.46#ibcon#about to read 4, iclass 29, count 2 2006.202.00:34:27.46#ibcon#read 4, iclass 29, count 2 2006.202.00:34:27.46#ibcon#about to read 5, iclass 29, count 2 2006.202.00:34:27.46#ibcon#read 5, iclass 29, count 2 2006.202.00:34:27.46#ibcon#about to read 6, iclass 29, count 2 2006.202.00:34:27.46#ibcon#read 6, iclass 29, count 2 2006.202.00:34:27.46#ibcon#end of sib2, iclass 29, count 2 2006.202.00:34:27.46#ibcon#*mode == 0, iclass 29, count 2 2006.202.00:34:27.46#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.00:34:27.46#ibcon#[27=AT08-04\r\n] 2006.202.00:34:27.46#ibcon#*before write, iclass 29, count 2 2006.202.00:34:27.46#ibcon#enter sib2, iclass 29, count 2 2006.202.00:34:27.46#ibcon#flushed, iclass 29, count 2 2006.202.00:34:27.46#ibcon#about to write, iclass 29, count 2 2006.202.00:34:27.53#ibcon#wrote, iclass 29, count 2 2006.202.00:34:27.53#ibcon#about to read 3, iclass 29, count 2 2006.202.00:34:27.57#ibcon#read 3, iclass 29, count 2 2006.202.00:34:27.57#ibcon#about to read 4, iclass 29, count 2 2006.202.00:34:27.57#ibcon#read 4, iclass 29, count 2 2006.202.00:34:27.57#ibcon#about to read 5, iclass 29, count 2 2006.202.00:34:27.57#ibcon#read 5, iclass 29, count 2 2006.202.00:34:27.57#ibcon#about to read 6, iclass 29, count 2 2006.202.00:34:27.57#ibcon#read 6, iclass 29, count 2 2006.202.00:34:27.57#ibcon#end of sib2, iclass 29, count 2 2006.202.00:34:27.57#ibcon#*after write, iclass 29, count 2 2006.202.00:34:27.57#ibcon#*before return 0, iclass 29, count 2 2006.202.00:34:27.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:27.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:34:27.57#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.00:34:27.57#ibcon#ireg 7 cls_cnt 0 2006.202.00:34:27.57#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:27.69#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:27.69#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:27.69#ibcon#enter wrdev, iclass 29, count 0 2006.202.00:34:27.69#ibcon#first serial, iclass 29, count 0 2006.202.00:34:27.69#ibcon#enter sib2, iclass 29, count 0 2006.202.00:34:27.69#ibcon#flushed, iclass 29, count 0 2006.202.00:34:27.69#ibcon#about to write, iclass 29, count 0 2006.202.00:34:27.69#ibcon#wrote, iclass 29, count 0 2006.202.00:34:27.69#ibcon#about to read 3, iclass 29, count 0 2006.202.00:34:27.71#ibcon#read 3, iclass 29, count 0 2006.202.00:34:27.71#ibcon#about to read 4, iclass 29, count 0 2006.202.00:34:27.71#ibcon#read 4, iclass 29, count 0 2006.202.00:34:27.71#ibcon#about to read 5, iclass 29, count 0 2006.202.00:34:27.71#ibcon#read 5, iclass 29, count 0 2006.202.00:34:27.71#ibcon#about to read 6, iclass 29, count 0 2006.202.00:34:27.71#ibcon#read 6, iclass 29, count 0 2006.202.00:34:27.71#ibcon#end of sib2, iclass 29, count 0 2006.202.00:34:27.71#ibcon#*mode == 0, iclass 29, count 0 2006.202.00:34:27.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.00:34:27.71#ibcon#[27=USB\r\n] 2006.202.00:34:27.71#ibcon#*before write, iclass 29, count 0 2006.202.00:34:27.71#ibcon#enter sib2, iclass 29, count 0 2006.202.00:34:27.71#ibcon#flushed, iclass 29, count 0 2006.202.00:34:27.71#ibcon#about to write, iclass 29, count 0 2006.202.00:34:27.71#ibcon#wrote, iclass 29, count 0 2006.202.00:34:27.71#ibcon#about to read 3, iclass 29, count 0 2006.202.00:34:27.74#ibcon#read 3, iclass 29, count 0 2006.202.00:34:27.74#ibcon#about to read 4, iclass 29, count 0 2006.202.00:34:27.74#ibcon#read 4, iclass 29, count 0 2006.202.00:34:27.74#ibcon#about to read 5, iclass 29, count 0 2006.202.00:34:27.74#ibcon#read 5, iclass 29, count 0 2006.202.00:34:27.74#ibcon#about to read 6, iclass 29, count 0 2006.202.00:34:27.74#ibcon#read 6, iclass 29, count 0 2006.202.00:34:27.74#ibcon#end of sib2, iclass 29, count 0 2006.202.00:34:27.74#ibcon#*after write, iclass 29, count 0 2006.202.00:34:27.74#ibcon#*before return 0, iclass 29, count 0 2006.202.00:34:27.74#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:27.74#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:34:27.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.00:34:27.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.00:34:27.74$vck44/vabw=wide 2006.202.00:34:27.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.202.00:34:27.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.202.00:34:27.74#ibcon#ireg 8 cls_cnt 0 2006.202.00:34:27.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:27.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:27.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:27.74#ibcon#enter wrdev, iclass 31, count 0 2006.202.00:34:27.74#ibcon#first serial, iclass 31, count 0 2006.202.00:34:27.74#ibcon#enter sib2, iclass 31, count 0 2006.202.00:34:27.74#ibcon#flushed, iclass 31, count 0 2006.202.00:34:27.74#ibcon#about to write, iclass 31, count 0 2006.202.00:34:27.74#ibcon#wrote, iclass 31, count 0 2006.202.00:34:27.74#ibcon#about to read 3, iclass 31, count 0 2006.202.00:34:27.76#ibcon#read 3, iclass 31, count 0 2006.202.00:34:27.76#ibcon#about to read 4, iclass 31, count 0 2006.202.00:34:27.76#ibcon#read 4, iclass 31, count 0 2006.202.00:34:27.76#ibcon#about to read 5, iclass 31, count 0 2006.202.00:34:27.76#ibcon#read 5, iclass 31, count 0 2006.202.00:34:27.76#ibcon#about to read 6, iclass 31, count 0 2006.202.00:34:27.76#ibcon#read 6, iclass 31, count 0 2006.202.00:34:27.76#ibcon#end of sib2, iclass 31, count 0 2006.202.00:34:27.76#ibcon#*mode == 0, iclass 31, count 0 2006.202.00:34:27.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.00:34:27.76#ibcon#[25=BW32\r\n] 2006.202.00:34:27.76#ibcon#*before write, iclass 31, count 0 2006.202.00:34:27.76#ibcon#enter sib2, iclass 31, count 0 2006.202.00:34:27.76#ibcon#flushed, iclass 31, count 0 2006.202.00:34:27.76#ibcon#about to write, iclass 31, count 0 2006.202.00:34:27.76#ibcon#wrote, iclass 31, count 0 2006.202.00:34:27.76#ibcon#about to read 3, iclass 31, count 0 2006.202.00:34:27.79#ibcon#read 3, iclass 31, count 0 2006.202.00:34:27.79#ibcon#about to read 4, iclass 31, count 0 2006.202.00:34:27.79#ibcon#read 4, iclass 31, count 0 2006.202.00:34:27.79#ibcon#about to read 5, iclass 31, count 0 2006.202.00:34:27.79#ibcon#read 5, iclass 31, count 0 2006.202.00:34:27.79#ibcon#about to read 6, iclass 31, count 0 2006.202.00:34:27.79#ibcon#read 6, iclass 31, count 0 2006.202.00:34:27.79#ibcon#end of sib2, iclass 31, count 0 2006.202.00:34:27.79#ibcon#*after write, iclass 31, count 0 2006.202.00:34:27.79#ibcon#*before return 0, iclass 31, count 0 2006.202.00:34:27.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:27.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:34:27.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.00:34:27.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.00:34:27.79$vck44/vbbw=wide 2006.202.00:34:27.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.00:34:27.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.00:34:27.79#ibcon#ireg 8 cls_cnt 0 2006.202.00:34:27.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:34:27.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:34:27.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:34:27.86#ibcon#enter wrdev, iclass 33, count 0 2006.202.00:34:27.86#ibcon#first serial, iclass 33, count 0 2006.202.00:34:27.86#ibcon#enter sib2, iclass 33, count 0 2006.202.00:34:27.86#ibcon#flushed, iclass 33, count 0 2006.202.00:34:27.86#ibcon#about to write, iclass 33, count 0 2006.202.00:34:27.86#ibcon#wrote, iclass 33, count 0 2006.202.00:34:27.86#ibcon#about to read 3, iclass 33, count 0 2006.202.00:34:27.88#ibcon#read 3, iclass 33, count 0 2006.202.00:34:27.88#ibcon#about to read 4, iclass 33, count 0 2006.202.00:34:27.88#ibcon#read 4, iclass 33, count 0 2006.202.00:34:27.88#ibcon#about to read 5, iclass 33, count 0 2006.202.00:34:27.88#ibcon#read 5, iclass 33, count 0 2006.202.00:34:27.88#ibcon#about to read 6, iclass 33, count 0 2006.202.00:34:27.88#ibcon#read 6, iclass 33, count 0 2006.202.00:34:27.88#ibcon#end of sib2, iclass 33, count 0 2006.202.00:34:27.88#ibcon#*mode == 0, iclass 33, count 0 2006.202.00:34:27.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.00:34:27.88#ibcon#[27=BW32\r\n] 2006.202.00:34:27.88#ibcon#*before write, iclass 33, count 0 2006.202.00:34:27.88#ibcon#enter sib2, iclass 33, count 0 2006.202.00:34:27.88#ibcon#flushed, iclass 33, count 0 2006.202.00:34:27.88#ibcon#about to write, iclass 33, count 0 2006.202.00:34:27.88#ibcon#wrote, iclass 33, count 0 2006.202.00:34:27.88#ibcon#about to read 3, iclass 33, count 0 2006.202.00:34:27.91#ibcon#read 3, iclass 33, count 0 2006.202.00:34:27.91#ibcon#about to read 4, iclass 33, count 0 2006.202.00:34:27.91#ibcon#read 4, iclass 33, count 0 2006.202.00:34:27.91#ibcon#about to read 5, iclass 33, count 0 2006.202.00:34:27.91#ibcon#read 5, iclass 33, count 0 2006.202.00:34:27.91#ibcon#about to read 6, iclass 33, count 0 2006.202.00:34:27.91#ibcon#read 6, iclass 33, count 0 2006.202.00:34:27.91#ibcon#end of sib2, iclass 33, count 0 2006.202.00:34:27.91#ibcon#*after write, iclass 33, count 0 2006.202.00:34:27.91#ibcon#*before return 0, iclass 33, count 0 2006.202.00:34:27.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:34:27.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.00:34:27.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.00:34:27.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.00:34:27.91$setupk4/ifdk4 2006.202.00:34:27.91$ifdk4/lo= 2006.202.00:34:27.91$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.00:34:27.91$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.00:34:27.91$ifdk4/patch= 2006.202.00:34:27.91$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.00:34:27.91$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.00:34:27.91$setupk4/!*+20s 2006.202.00:34:31.15#abcon#<5=/03 2.6 4.3 20.381001001.3\r\n> 2006.202.00:34:31.17#abcon#{5=INTERFACE CLEAR} 2006.202.00:34:31.23#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:34:40.14#trakl#Source acquired 2006.202.00:34:41.32#abcon#<5=/03 2.6 4.4 20.381001001.3\r\n> 2006.202.00:34:41.34#abcon#{5=INTERFACE CLEAR} 2006.202.00:34:41.40#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:34:42.14#flagr#flagr/antenna,acquired 2006.202.00:34:42.29$setupk4/"tpicd 2006.202.00:34:42.29$setupk4/echo=off 2006.202.00:34:42.29$setupk4/xlog=off 2006.202.00:34:42.29:!2006.202.00:36:09 2006.202.00:36:09.00:preob 2006.202.00:36:10.14/onsource/TRACKING 2006.202.00:36:10.14:!2006.202.00:36:19 2006.202.00:36:19.00:"tape 2006.202.00:36:19.00:"st=record 2006.202.00:36:19.00:data_valid=on 2006.202.00:36:19.00:midob 2006.202.00:36:19.14/onsource/TRACKING 2006.202.00:36:19.14/wx/20.40,1001.4,100 2006.202.00:36:19.22/cable/+6.4839E-03 2006.202.00:36:20.31/va/01,08,usb,yes,38,41 2006.202.00:36:20.31/va/02,07,usb,yes,41,42 2006.202.00:36:20.31/va/03,08,usb,yes,37,39 2006.202.00:36:20.31/va/04,07,usb,yes,42,45 2006.202.00:36:20.31/va/05,04,usb,yes,38,39 2006.202.00:36:20.31/va/06,05,usb,yes,38,38 2006.202.00:36:20.31/va/07,05,usb,yes,37,38 2006.202.00:36:20.31/va/08,04,usb,yes,37,44 2006.202.00:36:20.54/valo/01,524.99,yes,locked 2006.202.00:36:20.54/valo/02,534.99,yes,locked 2006.202.00:36:20.54/valo/03,564.99,yes,locked 2006.202.00:36:20.54/valo/04,624.99,yes,locked 2006.202.00:36:20.54/valo/05,734.99,yes,locked 2006.202.00:36:20.54/valo/06,814.99,yes,locked 2006.202.00:36:20.54/valo/07,864.99,yes,locked 2006.202.00:36:20.54/valo/08,884.99,yes,locked 2006.202.00:36:21.63/vb/01,04,usb,yes,29,27 2006.202.00:36:21.63/vb/02,05,usb,yes,27,27 2006.202.00:36:21.63/vb/03,04,usb,yes,28,31 2006.202.00:36:21.63/vb/04,05,usb,yes,29,28 2006.202.00:36:21.63/vb/05,04,usb,yes,25,28 2006.202.00:36:21.63/vb/06,04,usb,yes,30,26 2006.202.00:36:21.63/vb/07,04,usb,yes,29,29 2006.202.00:36:21.63/vb/08,04,usb,yes,27,30 2006.202.00:36:21.87/vblo/01,629.99,yes,locked 2006.202.00:36:21.87/vblo/02,634.99,yes,locked 2006.202.00:36:21.87/vblo/03,649.99,yes,locked 2006.202.00:36:21.87/vblo/04,679.99,yes,locked 2006.202.00:36:21.87/vblo/05,709.99,yes,locked 2006.202.00:36:21.87/vblo/06,719.99,yes,locked 2006.202.00:36:21.87/vblo/07,734.99,yes,locked 2006.202.00:36:21.87/vblo/08,744.99,yes,locked 2006.202.00:36:22.02/vabw/8 2006.202.00:36:22.17/vbbw/8 2006.202.00:36:22.26/xfe/off,on,16.2 2006.202.00:36:22.63/ifatt/23,28,28,28 2006.202.00:36:23.07/fmout-gps/S +4.50E-07 2006.202.00:36:23.11:!2006.202.00:37:39 2006.202.00:37:39.00:data_valid=off 2006.202.00:37:39.00:"et 2006.202.00:37:39.00:!+3s 2006.202.00:37:42.02:"tape 2006.202.00:37:42.02:postob 2006.202.00:37:42.18/cable/+6.4847E-03 2006.202.00:37:42.18/wx/20.42,1001.4,100 2006.202.00:37:42.24/fmout-gps/S +4.50E-07 2006.202.00:37:42.24:scan_name=202-0040,jd0607,40 2006.202.00:37:42.24:source=0537-441,053850.36,-440508.9,2000.0,cw 2006.202.00:37:43.14#flagr#flagr/antenna,new-source 2006.202.00:37:43.14:checkk5 2006.202.00:37:43.56/chk_autoobs//k5ts1/ autoobs is running! 2006.202.00:37:43.95/chk_autoobs//k5ts2/ autoobs is running! 2006.202.00:37:44.35/chk_autoobs//k5ts3/ autoobs is running! 2006.202.00:37:44.75/chk_autoobs//k5ts4/ autoobs is running! 2006.202.00:37:45.14/chk_obsdata//k5ts1/T2020036??a.dat file size is correct (nominal:320MB, actual:316MB). 2006.202.00:37:45.53/chk_obsdata//k5ts2/T2020036??b.dat file size is correct (nominal:320MB, actual:316MB). 2006.202.00:37:45.93/chk_obsdata//k5ts3/T2020036??c.dat file size is correct (nominal:320MB, actual:316MB). 2006.202.00:37:46.34/chk_obsdata//k5ts4/T2020036??d.dat file size is correct (nominal:320MB, actual:316MB). 2006.202.00:37:47.08/k5log//k5ts1_log_newline 2006.202.00:37:47.79/k5log//k5ts2_log_newline 2006.202.00:37:48.51/k5log//k5ts3_log_newline 2006.202.00:37:49.20/k5log//k5ts4_log_newline 2006.202.00:37:49.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.00:37:49.22:setupk4=1 2006.202.00:37:49.22$setupk4/echo=on 2006.202.00:37:49.22$setupk4/pcalon 2006.202.00:37:49.22$pcalon/"no phase cal control is implemented here 2006.202.00:37:49.22$setupk4/"tpicd=stop 2006.202.00:37:49.23$setupk4/"rec=synch_on 2006.202.00:37:49.23$setupk4/"rec_mode=128 2006.202.00:37:49.23$setupk4/!* 2006.202.00:37:49.23$setupk4/recpk4 2006.202.00:37:49.23$recpk4/recpatch= 2006.202.00:37:49.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.00:37:49.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.00:37:49.23$setupk4/vck44 2006.202.00:37:49.23$vck44/valo=1,524.99 2006.202.00:37:49.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.00:37:49.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.00:37:49.23#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:49.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:49.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:49.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:49.23#ibcon#enter wrdev, iclass 10, count 0 2006.202.00:37:49.23#ibcon#first serial, iclass 10, count 0 2006.202.00:37:49.23#ibcon#enter sib2, iclass 10, count 0 2006.202.00:37:49.23#ibcon#flushed, iclass 10, count 0 2006.202.00:37:49.23#ibcon#about to write, iclass 10, count 0 2006.202.00:37:49.23#ibcon#wrote, iclass 10, count 0 2006.202.00:37:49.23#ibcon#about to read 3, iclass 10, count 0 2006.202.00:37:49.25#ibcon#read 3, iclass 10, count 0 2006.202.00:37:49.25#ibcon#about to read 4, iclass 10, count 0 2006.202.00:37:49.25#ibcon#read 4, iclass 10, count 0 2006.202.00:37:49.25#ibcon#about to read 5, iclass 10, count 0 2006.202.00:37:49.25#ibcon#read 5, iclass 10, count 0 2006.202.00:37:49.25#ibcon#about to read 6, iclass 10, count 0 2006.202.00:37:49.25#ibcon#read 6, iclass 10, count 0 2006.202.00:37:49.25#ibcon#end of sib2, iclass 10, count 0 2006.202.00:37:49.25#ibcon#*mode == 0, iclass 10, count 0 2006.202.00:37:49.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.00:37:49.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.00:37:49.25#ibcon#*before write, iclass 10, count 0 2006.202.00:37:49.25#ibcon#enter sib2, iclass 10, count 0 2006.202.00:37:49.25#ibcon#flushed, iclass 10, count 0 2006.202.00:37:49.25#ibcon#about to write, iclass 10, count 0 2006.202.00:37:49.25#ibcon#wrote, iclass 10, count 0 2006.202.00:37:49.25#ibcon#about to read 3, iclass 10, count 0 2006.202.00:37:49.30#ibcon#read 3, iclass 10, count 0 2006.202.00:37:49.30#ibcon#about to read 4, iclass 10, count 0 2006.202.00:37:49.30#ibcon#read 4, iclass 10, count 0 2006.202.00:37:49.30#ibcon#about to read 5, iclass 10, count 0 2006.202.00:37:49.30#ibcon#read 5, iclass 10, count 0 2006.202.00:37:49.30#ibcon#about to read 6, iclass 10, count 0 2006.202.00:37:49.30#ibcon#read 6, iclass 10, count 0 2006.202.00:37:49.30#ibcon#end of sib2, iclass 10, count 0 2006.202.00:37:49.30#ibcon#*after write, iclass 10, count 0 2006.202.00:37:49.30#ibcon#*before return 0, iclass 10, count 0 2006.202.00:37:49.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:49.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:49.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.00:37:49.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.00:37:49.30$vck44/va=1,8 2006.202.00:37:49.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.202.00:37:49.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.202.00:37:49.30#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:49.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:49.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:49.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:49.30#ibcon#enter wrdev, iclass 12, count 2 2006.202.00:37:49.30#ibcon#first serial, iclass 12, count 2 2006.202.00:37:49.30#ibcon#enter sib2, iclass 12, count 2 2006.202.00:37:49.30#ibcon#flushed, iclass 12, count 2 2006.202.00:37:49.30#ibcon#about to write, iclass 12, count 2 2006.202.00:37:49.30#ibcon#wrote, iclass 12, count 2 2006.202.00:37:49.30#ibcon#about to read 3, iclass 12, count 2 2006.202.00:37:49.32#ibcon#read 3, iclass 12, count 2 2006.202.00:37:49.32#ibcon#about to read 4, iclass 12, count 2 2006.202.00:37:49.32#ibcon#read 4, iclass 12, count 2 2006.202.00:37:49.32#ibcon#about to read 5, iclass 12, count 2 2006.202.00:37:49.32#ibcon#read 5, iclass 12, count 2 2006.202.00:37:49.32#ibcon#about to read 6, iclass 12, count 2 2006.202.00:37:49.32#ibcon#read 6, iclass 12, count 2 2006.202.00:37:49.32#ibcon#end of sib2, iclass 12, count 2 2006.202.00:37:49.32#ibcon#*mode == 0, iclass 12, count 2 2006.202.00:37:49.32#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.202.00:37:49.32#ibcon#[25=AT01-08\r\n] 2006.202.00:37:49.32#ibcon#*before write, iclass 12, count 2 2006.202.00:37:49.32#ibcon#enter sib2, iclass 12, count 2 2006.202.00:37:49.32#ibcon#flushed, iclass 12, count 2 2006.202.00:37:49.32#ibcon#about to write, iclass 12, count 2 2006.202.00:37:49.32#ibcon#wrote, iclass 12, count 2 2006.202.00:37:49.32#ibcon#about to read 3, iclass 12, count 2 2006.202.00:37:49.35#ibcon#read 3, iclass 12, count 2 2006.202.00:37:49.35#ibcon#about to read 4, iclass 12, count 2 2006.202.00:37:49.35#ibcon#read 4, iclass 12, count 2 2006.202.00:37:49.35#ibcon#about to read 5, iclass 12, count 2 2006.202.00:37:49.35#ibcon#read 5, iclass 12, count 2 2006.202.00:37:49.35#ibcon#about to read 6, iclass 12, count 2 2006.202.00:37:49.35#ibcon#read 6, iclass 12, count 2 2006.202.00:37:49.35#ibcon#end of sib2, iclass 12, count 2 2006.202.00:37:49.35#ibcon#*after write, iclass 12, count 2 2006.202.00:37:49.35#ibcon#*before return 0, iclass 12, count 2 2006.202.00:37:49.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:49.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:49.35#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.202.00:37:49.35#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:49.35#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:49.47#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:49.47#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:49.47#ibcon#enter wrdev, iclass 12, count 0 2006.202.00:37:49.47#ibcon#first serial, iclass 12, count 0 2006.202.00:37:49.47#ibcon#enter sib2, iclass 12, count 0 2006.202.00:37:49.47#ibcon#flushed, iclass 12, count 0 2006.202.00:37:49.47#ibcon#about to write, iclass 12, count 0 2006.202.00:37:49.47#ibcon#wrote, iclass 12, count 0 2006.202.00:37:49.47#ibcon#about to read 3, iclass 12, count 0 2006.202.00:37:49.49#ibcon#read 3, iclass 12, count 0 2006.202.00:37:49.49#ibcon#about to read 4, iclass 12, count 0 2006.202.00:37:49.49#ibcon#read 4, iclass 12, count 0 2006.202.00:37:49.49#ibcon#about to read 5, iclass 12, count 0 2006.202.00:37:49.49#ibcon#read 5, iclass 12, count 0 2006.202.00:37:49.49#ibcon#about to read 6, iclass 12, count 0 2006.202.00:37:49.49#ibcon#read 6, iclass 12, count 0 2006.202.00:37:49.49#ibcon#end of sib2, iclass 12, count 0 2006.202.00:37:49.49#ibcon#*mode == 0, iclass 12, count 0 2006.202.00:37:49.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.00:37:49.49#ibcon#[25=USB\r\n] 2006.202.00:37:49.49#ibcon#*before write, iclass 12, count 0 2006.202.00:37:49.49#ibcon#enter sib2, iclass 12, count 0 2006.202.00:37:49.49#ibcon#flushed, iclass 12, count 0 2006.202.00:37:49.49#ibcon#about to write, iclass 12, count 0 2006.202.00:37:49.49#ibcon#wrote, iclass 12, count 0 2006.202.00:37:49.49#ibcon#about to read 3, iclass 12, count 0 2006.202.00:37:49.52#ibcon#read 3, iclass 12, count 0 2006.202.00:37:49.52#ibcon#about to read 4, iclass 12, count 0 2006.202.00:37:49.52#ibcon#read 4, iclass 12, count 0 2006.202.00:37:49.52#ibcon#about to read 5, iclass 12, count 0 2006.202.00:37:49.52#ibcon#read 5, iclass 12, count 0 2006.202.00:37:49.52#ibcon#about to read 6, iclass 12, count 0 2006.202.00:37:49.52#ibcon#read 6, iclass 12, count 0 2006.202.00:37:49.52#ibcon#end of sib2, iclass 12, count 0 2006.202.00:37:49.52#ibcon#*after write, iclass 12, count 0 2006.202.00:37:49.52#ibcon#*before return 0, iclass 12, count 0 2006.202.00:37:49.52#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:49.52#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:49.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.00:37:49.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.00:37:49.52$vck44/valo=2,534.99 2006.202.00:37:49.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.00:37:49.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.00:37:49.52#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:49.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:49.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:49.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:49.52#ibcon#enter wrdev, iclass 14, count 0 2006.202.00:37:49.52#ibcon#first serial, iclass 14, count 0 2006.202.00:37:49.52#ibcon#enter sib2, iclass 14, count 0 2006.202.00:37:49.52#ibcon#flushed, iclass 14, count 0 2006.202.00:37:49.52#ibcon#about to write, iclass 14, count 0 2006.202.00:37:49.52#ibcon#wrote, iclass 14, count 0 2006.202.00:37:49.52#ibcon#about to read 3, iclass 14, count 0 2006.202.00:37:49.54#ibcon#read 3, iclass 14, count 0 2006.202.00:37:49.54#ibcon#about to read 4, iclass 14, count 0 2006.202.00:37:49.54#ibcon#read 4, iclass 14, count 0 2006.202.00:37:49.54#ibcon#about to read 5, iclass 14, count 0 2006.202.00:37:49.54#ibcon#read 5, iclass 14, count 0 2006.202.00:37:49.54#ibcon#about to read 6, iclass 14, count 0 2006.202.00:37:49.54#ibcon#read 6, iclass 14, count 0 2006.202.00:37:49.54#ibcon#end of sib2, iclass 14, count 0 2006.202.00:37:49.54#ibcon#*mode == 0, iclass 14, count 0 2006.202.00:37:49.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.00:37:49.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.00:37:49.54#ibcon#*before write, iclass 14, count 0 2006.202.00:37:49.54#ibcon#enter sib2, iclass 14, count 0 2006.202.00:37:49.54#ibcon#flushed, iclass 14, count 0 2006.202.00:37:49.54#ibcon#about to write, iclass 14, count 0 2006.202.00:37:49.54#ibcon#wrote, iclass 14, count 0 2006.202.00:37:49.54#ibcon#about to read 3, iclass 14, count 0 2006.202.00:37:49.58#ibcon#read 3, iclass 14, count 0 2006.202.00:37:49.58#ibcon#about to read 4, iclass 14, count 0 2006.202.00:37:49.58#ibcon#read 4, iclass 14, count 0 2006.202.00:37:49.58#ibcon#about to read 5, iclass 14, count 0 2006.202.00:37:49.58#ibcon#read 5, iclass 14, count 0 2006.202.00:37:49.58#ibcon#about to read 6, iclass 14, count 0 2006.202.00:37:49.58#ibcon#read 6, iclass 14, count 0 2006.202.00:37:49.58#ibcon#end of sib2, iclass 14, count 0 2006.202.00:37:49.58#ibcon#*after write, iclass 14, count 0 2006.202.00:37:49.58#ibcon#*before return 0, iclass 14, count 0 2006.202.00:37:49.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:49.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:49.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.00:37:49.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.00:37:49.58$vck44/va=2,7 2006.202.00:37:49.58#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.00:37:49.58#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.00:37:49.58#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:49.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:49.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:49.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:49.64#ibcon#enter wrdev, iclass 16, count 2 2006.202.00:37:49.64#ibcon#first serial, iclass 16, count 2 2006.202.00:37:49.64#ibcon#enter sib2, iclass 16, count 2 2006.202.00:37:49.64#ibcon#flushed, iclass 16, count 2 2006.202.00:37:49.64#ibcon#about to write, iclass 16, count 2 2006.202.00:37:49.64#ibcon#wrote, iclass 16, count 2 2006.202.00:37:49.64#ibcon#about to read 3, iclass 16, count 2 2006.202.00:37:49.66#ibcon#read 3, iclass 16, count 2 2006.202.00:37:49.66#ibcon#about to read 4, iclass 16, count 2 2006.202.00:37:49.66#ibcon#read 4, iclass 16, count 2 2006.202.00:37:49.66#ibcon#about to read 5, iclass 16, count 2 2006.202.00:37:49.66#ibcon#read 5, iclass 16, count 2 2006.202.00:37:49.66#ibcon#about to read 6, iclass 16, count 2 2006.202.00:37:49.66#ibcon#read 6, iclass 16, count 2 2006.202.00:37:49.66#ibcon#end of sib2, iclass 16, count 2 2006.202.00:37:49.66#ibcon#*mode == 0, iclass 16, count 2 2006.202.00:37:49.66#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.00:37:49.66#ibcon#[25=AT02-07\r\n] 2006.202.00:37:49.66#ibcon#*before write, iclass 16, count 2 2006.202.00:37:49.66#ibcon#enter sib2, iclass 16, count 2 2006.202.00:37:49.66#ibcon#flushed, iclass 16, count 2 2006.202.00:37:49.66#ibcon#about to write, iclass 16, count 2 2006.202.00:37:49.66#ibcon#wrote, iclass 16, count 2 2006.202.00:37:49.66#ibcon#about to read 3, iclass 16, count 2 2006.202.00:37:49.69#ibcon#read 3, iclass 16, count 2 2006.202.00:37:49.69#ibcon#about to read 4, iclass 16, count 2 2006.202.00:37:49.69#ibcon#read 4, iclass 16, count 2 2006.202.00:37:49.69#ibcon#about to read 5, iclass 16, count 2 2006.202.00:37:49.69#ibcon#read 5, iclass 16, count 2 2006.202.00:37:49.69#ibcon#about to read 6, iclass 16, count 2 2006.202.00:37:49.69#ibcon#read 6, iclass 16, count 2 2006.202.00:37:49.69#ibcon#end of sib2, iclass 16, count 2 2006.202.00:37:49.69#ibcon#*after write, iclass 16, count 2 2006.202.00:37:49.69#ibcon#*before return 0, iclass 16, count 2 2006.202.00:37:49.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:49.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:49.69#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.00:37:49.69#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:49.69#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:49.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:49.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:49.81#ibcon#enter wrdev, iclass 16, count 0 2006.202.00:37:49.81#ibcon#first serial, iclass 16, count 0 2006.202.00:37:49.81#ibcon#enter sib2, iclass 16, count 0 2006.202.00:37:49.81#ibcon#flushed, iclass 16, count 0 2006.202.00:37:49.81#ibcon#about to write, iclass 16, count 0 2006.202.00:37:49.81#ibcon#wrote, iclass 16, count 0 2006.202.00:37:49.81#ibcon#about to read 3, iclass 16, count 0 2006.202.00:37:49.83#ibcon#read 3, iclass 16, count 0 2006.202.00:37:49.83#ibcon#about to read 4, iclass 16, count 0 2006.202.00:37:49.83#ibcon#read 4, iclass 16, count 0 2006.202.00:37:49.83#ibcon#about to read 5, iclass 16, count 0 2006.202.00:37:49.83#ibcon#read 5, iclass 16, count 0 2006.202.00:37:49.83#ibcon#about to read 6, iclass 16, count 0 2006.202.00:37:49.83#ibcon#read 6, iclass 16, count 0 2006.202.00:37:49.83#ibcon#end of sib2, iclass 16, count 0 2006.202.00:37:49.83#ibcon#*mode == 0, iclass 16, count 0 2006.202.00:37:49.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.00:37:49.83#ibcon#[25=USB\r\n] 2006.202.00:37:49.83#ibcon#*before write, iclass 16, count 0 2006.202.00:37:49.83#ibcon#enter sib2, iclass 16, count 0 2006.202.00:37:49.83#ibcon#flushed, iclass 16, count 0 2006.202.00:37:49.83#ibcon#about to write, iclass 16, count 0 2006.202.00:37:49.83#ibcon#wrote, iclass 16, count 0 2006.202.00:37:49.83#ibcon#about to read 3, iclass 16, count 0 2006.202.00:37:49.86#ibcon#read 3, iclass 16, count 0 2006.202.00:37:49.86#ibcon#about to read 4, iclass 16, count 0 2006.202.00:37:49.86#ibcon#read 4, iclass 16, count 0 2006.202.00:37:49.86#ibcon#about to read 5, iclass 16, count 0 2006.202.00:37:49.86#ibcon#read 5, iclass 16, count 0 2006.202.00:37:49.86#ibcon#about to read 6, iclass 16, count 0 2006.202.00:37:49.86#ibcon#read 6, iclass 16, count 0 2006.202.00:37:49.86#ibcon#end of sib2, iclass 16, count 0 2006.202.00:37:49.86#ibcon#*after write, iclass 16, count 0 2006.202.00:37:49.86#ibcon#*before return 0, iclass 16, count 0 2006.202.00:37:49.86#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:49.86#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:49.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.00:37:49.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.00:37:49.86$vck44/valo=3,564.99 2006.202.00:37:49.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.00:37:49.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.00:37:49.86#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:49.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:49.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:49.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:49.86#ibcon#enter wrdev, iclass 18, count 0 2006.202.00:37:49.86#ibcon#first serial, iclass 18, count 0 2006.202.00:37:49.86#ibcon#enter sib2, iclass 18, count 0 2006.202.00:37:49.86#ibcon#flushed, iclass 18, count 0 2006.202.00:37:49.86#ibcon#about to write, iclass 18, count 0 2006.202.00:37:49.86#ibcon#wrote, iclass 18, count 0 2006.202.00:37:49.86#ibcon#about to read 3, iclass 18, count 0 2006.202.00:37:49.88#ibcon#read 3, iclass 18, count 0 2006.202.00:37:49.88#ibcon#about to read 4, iclass 18, count 0 2006.202.00:37:49.88#ibcon#read 4, iclass 18, count 0 2006.202.00:37:49.88#ibcon#about to read 5, iclass 18, count 0 2006.202.00:37:49.88#ibcon#read 5, iclass 18, count 0 2006.202.00:37:49.88#ibcon#about to read 6, iclass 18, count 0 2006.202.00:37:49.88#ibcon#read 6, iclass 18, count 0 2006.202.00:37:49.88#ibcon#end of sib2, iclass 18, count 0 2006.202.00:37:49.88#ibcon#*mode == 0, iclass 18, count 0 2006.202.00:37:49.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.00:37:49.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.00:37:49.88#ibcon#*before write, iclass 18, count 0 2006.202.00:37:49.88#ibcon#enter sib2, iclass 18, count 0 2006.202.00:37:49.88#ibcon#flushed, iclass 18, count 0 2006.202.00:37:49.88#ibcon#about to write, iclass 18, count 0 2006.202.00:37:49.88#ibcon#wrote, iclass 18, count 0 2006.202.00:37:49.88#ibcon#about to read 3, iclass 18, count 0 2006.202.00:37:49.92#ibcon#read 3, iclass 18, count 0 2006.202.00:37:49.92#ibcon#about to read 4, iclass 18, count 0 2006.202.00:37:49.92#ibcon#read 4, iclass 18, count 0 2006.202.00:37:49.92#ibcon#about to read 5, iclass 18, count 0 2006.202.00:37:49.92#ibcon#read 5, iclass 18, count 0 2006.202.00:37:49.92#ibcon#about to read 6, iclass 18, count 0 2006.202.00:37:49.92#ibcon#read 6, iclass 18, count 0 2006.202.00:37:49.92#ibcon#end of sib2, iclass 18, count 0 2006.202.00:37:49.92#ibcon#*after write, iclass 18, count 0 2006.202.00:37:49.92#ibcon#*before return 0, iclass 18, count 0 2006.202.00:37:49.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:49.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:49.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.00:37:49.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.00:37:49.92$vck44/va=3,8 2006.202.00:37:49.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.00:37:49.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.00:37:49.92#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:49.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:49.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:49.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:49.98#ibcon#enter wrdev, iclass 20, count 2 2006.202.00:37:49.98#ibcon#first serial, iclass 20, count 2 2006.202.00:37:49.98#ibcon#enter sib2, iclass 20, count 2 2006.202.00:37:49.98#ibcon#flushed, iclass 20, count 2 2006.202.00:37:49.98#ibcon#about to write, iclass 20, count 2 2006.202.00:37:49.98#ibcon#wrote, iclass 20, count 2 2006.202.00:37:49.98#ibcon#about to read 3, iclass 20, count 2 2006.202.00:37:50.00#ibcon#read 3, iclass 20, count 2 2006.202.00:37:50.00#ibcon#about to read 4, iclass 20, count 2 2006.202.00:37:50.00#ibcon#read 4, iclass 20, count 2 2006.202.00:37:50.00#ibcon#about to read 5, iclass 20, count 2 2006.202.00:37:50.00#ibcon#read 5, iclass 20, count 2 2006.202.00:37:50.00#ibcon#about to read 6, iclass 20, count 2 2006.202.00:37:50.00#ibcon#read 6, iclass 20, count 2 2006.202.00:37:50.00#ibcon#end of sib2, iclass 20, count 2 2006.202.00:37:50.00#ibcon#*mode == 0, iclass 20, count 2 2006.202.00:37:50.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.00:37:50.00#ibcon#[25=AT03-08\r\n] 2006.202.00:37:50.00#ibcon#*before write, iclass 20, count 2 2006.202.00:37:50.00#ibcon#enter sib2, iclass 20, count 2 2006.202.00:37:50.00#ibcon#flushed, iclass 20, count 2 2006.202.00:37:50.00#ibcon#about to write, iclass 20, count 2 2006.202.00:37:50.00#ibcon#wrote, iclass 20, count 2 2006.202.00:37:50.00#ibcon#about to read 3, iclass 20, count 2 2006.202.00:37:50.03#ibcon#read 3, iclass 20, count 2 2006.202.00:37:50.03#ibcon#about to read 4, iclass 20, count 2 2006.202.00:37:50.03#ibcon#read 4, iclass 20, count 2 2006.202.00:37:50.03#ibcon#about to read 5, iclass 20, count 2 2006.202.00:37:50.03#ibcon#read 5, iclass 20, count 2 2006.202.00:37:50.03#ibcon#about to read 6, iclass 20, count 2 2006.202.00:37:50.03#ibcon#read 6, iclass 20, count 2 2006.202.00:37:50.03#ibcon#end of sib2, iclass 20, count 2 2006.202.00:37:50.03#ibcon#*after write, iclass 20, count 2 2006.202.00:37:50.03#ibcon#*before return 0, iclass 20, count 2 2006.202.00:37:50.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:50.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:50.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.00:37:50.03#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:50.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:50.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:50.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:50.15#ibcon#enter wrdev, iclass 20, count 0 2006.202.00:37:50.15#ibcon#first serial, iclass 20, count 0 2006.202.00:37:50.15#ibcon#enter sib2, iclass 20, count 0 2006.202.00:37:50.15#ibcon#flushed, iclass 20, count 0 2006.202.00:37:50.15#ibcon#about to write, iclass 20, count 0 2006.202.00:37:50.15#ibcon#wrote, iclass 20, count 0 2006.202.00:37:50.15#ibcon#about to read 3, iclass 20, count 0 2006.202.00:37:50.17#ibcon#read 3, iclass 20, count 0 2006.202.00:37:50.17#ibcon#about to read 4, iclass 20, count 0 2006.202.00:37:50.17#ibcon#read 4, iclass 20, count 0 2006.202.00:37:50.17#ibcon#about to read 5, iclass 20, count 0 2006.202.00:37:50.17#ibcon#read 5, iclass 20, count 0 2006.202.00:37:50.17#ibcon#about to read 6, iclass 20, count 0 2006.202.00:37:50.17#ibcon#read 6, iclass 20, count 0 2006.202.00:37:50.17#ibcon#end of sib2, iclass 20, count 0 2006.202.00:37:50.17#ibcon#*mode == 0, iclass 20, count 0 2006.202.00:37:50.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.00:37:50.17#ibcon#[25=USB\r\n] 2006.202.00:37:50.17#ibcon#*before write, iclass 20, count 0 2006.202.00:37:50.17#ibcon#enter sib2, iclass 20, count 0 2006.202.00:37:50.17#ibcon#flushed, iclass 20, count 0 2006.202.00:37:50.17#ibcon#about to write, iclass 20, count 0 2006.202.00:37:50.17#ibcon#wrote, iclass 20, count 0 2006.202.00:37:50.17#ibcon#about to read 3, iclass 20, count 0 2006.202.00:37:50.20#ibcon#read 3, iclass 20, count 0 2006.202.00:37:50.20#ibcon#about to read 4, iclass 20, count 0 2006.202.00:37:50.20#ibcon#read 4, iclass 20, count 0 2006.202.00:37:50.20#ibcon#about to read 5, iclass 20, count 0 2006.202.00:37:50.20#ibcon#read 5, iclass 20, count 0 2006.202.00:37:50.20#ibcon#about to read 6, iclass 20, count 0 2006.202.00:37:50.20#ibcon#read 6, iclass 20, count 0 2006.202.00:37:50.20#ibcon#end of sib2, iclass 20, count 0 2006.202.00:37:50.20#ibcon#*after write, iclass 20, count 0 2006.202.00:37:50.20#ibcon#*before return 0, iclass 20, count 0 2006.202.00:37:50.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:50.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:50.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.00:37:50.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.00:37:50.20$vck44/valo=4,624.99 2006.202.00:37:50.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.00:37:50.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.00:37:50.20#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:50.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:50.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:50.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:50.20#ibcon#enter wrdev, iclass 22, count 0 2006.202.00:37:50.20#ibcon#first serial, iclass 22, count 0 2006.202.00:37:50.20#ibcon#enter sib2, iclass 22, count 0 2006.202.00:37:50.20#ibcon#flushed, iclass 22, count 0 2006.202.00:37:50.20#ibcon#about to write, iclass 22, count 0 2006.202.00:37:50.20#ibcon#wrote, iclass 22, count 0 2006.202.00:37:50.20#ibcon#about to read 3, iclass 22, count 0 2006.202.00:37:50.22#ibcon#read 3, iclass 22, count 0 2006.202.00:37:50.22#ibcon#about to read 4, iclass 22, count 0 2006.202.00:37:50.22#ibcon#read 4, iclass 22, count 0 2006.202.00:37:50.22#ibcon#about to read 5, iclass 22, count 0 2006.202.00:37:50.22#ibcon#read 5, iclass 22, count 0 2006.202.00:37:50.22#ibcon#about to read 6, iclass 22, count 0 2006.202.00:37:50.22#ibcon#read 6, iclass 22, count 0 2006.202.00:37:50.22#ibcon#end of sib2, iclass 22, count 0 2006.202.00:37:50.22#ibcon#*mode == 0, iclass 22, count 0 2006.202.00:37:50.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.00:37:50.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.00:37:50.22#ibcon#*before write, iclass 22, count 0 2006.202.00:37:50.22#ibcon#enter sib2, iclass 22, count 0 2006.202.00:37:50.22#ibcon#flushed, iclass 22, count 0 2006.202.00:37:50.22#ibcon#about to write, iclass 22, count 0 2006.202.00:37:50.22#ibcon#wrote, iclass 22, count 0 2006.202.00:37:50.22#ibcon#about to read 3, iclass 22, count 0 2006.202.00:37:50.26#ibcon#read 3, iclass 22, count 0 2006.202.00:37:50.26#ibcon#about to read 4, iclass 22, count 0 2006.202.00:37:50.26#ibcon#read 4, iclass 22, count 0 2006.202.00:37:50.26#ibcon#about to read 5, iclass 22, count 0 2006.202.00:37:50.26#ibcon#read 5, iclass 22, count 0 2006.202.00:37:50.26#ibcon#about to read 6, iclass 22, count 0 2006.202.00:37:50.26#ibcon#read 6, iclass 22, count 0 2006.202.00:37:50.26#ibcon#end of sib2, iclass 22, count 0 2006.202.00:37:50.26#ibcon#*after write, iclass 22, count 0 2006.202.00:37:50.26#ibcon#*before return 0, iclass 22, count 0 2006.202.00:37:50.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:50.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:50.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.00:37:50.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.00:37:50.26$vck44/va=4,7 2006.202.00:37:50.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.00:37:50.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.00:37:50.26#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:50.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:50.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:50.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:50.32#ibcon#enter wrdev, iclass 24, count 2 2006.202.00:37:50.32#ibcon#first serial, iclass 24, count 2 2006.202.00:37:50.32#ibcon#enter sib2, iclass 24, count 2 2006.202.00:37:50.32#ibcon#flushed, iclass 24, count 2 2006.202.00:37:50.32#ibcon#about to write, iclass 24, count 2 2006.202.00:37:50.32#ibcon#wrote, iclass 24, count 2 2006.202.00:37:50.32#ibcon#about to read 3, iclass 24, count 2 2006.202.00:37:50.34#ibcon#read 3, iclass 24, count 2 2006.202.00:37:50.34#ibcon#about to read 4, iclass 24, count 2 2006.202.00:37:50.34#ibcon#read 4, iclass 24, count 2 2006.202.00:37:50.34#ibcon#about to read 5, iclass 24, count 2 2006.202.00:37:50.34#ibcon#read 5, iclass 24, count 2 2006.202.00:37:50.34#ibcon#about to read 6, iclass 24, count 2 2006.202.00:37:50.34#ibcon#read 6, iclass 24, count 2 2006.202.00:37:50.34#ibcon#end of sib2, iclass 24, count 2 2006.202.00:37:50.34#ibcon#*mode == 0, iclass 24, count 2 2006.202.00:37:50.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.00:37:50.34#ibcon#[25=AT04-07\r\n] 2006.202.00:37:50.34#ibcon#*before write, iclass 24, count 2 2006.202.00:37:50.34#ibcon#enter sib2, iclass 24, count 2 2006.202.00:37:50.34#ibcon#flushed, iclass 24, count 2 2006.202.00:37:50.34#ibcon#about to write, iclass 24, count 2 2006.202.00:37:50.34#ibcon#wrote, iclass 24, count 2 2006.202.00:37:50.34#ibcon#about to read 3, iclass 24, count 2 2006.202.00:37:50.37#ibcon#read 3, iclass 24, count 2 2006.202.00:37:50.41#ibcon#about to read 4, iclass 24, count 2 2006.202.00:37:50.41#ibcon#read 4, iclass 24, count 2 2006.202.00:37:50.41#ibcon#about to read 5, iclass 24, count 2 2006.202.00:37:50.41#ibcon#read 5, iclass 24, count 2 2006.202.00:37:50.41#ibcon#about to read 6, iclass 24, count 2 2006.202.00:37:50.41#ibcon#read 6, iclass 24, count 2 2006.202.00:37:50.41#ibcon#end of sib2, iclass 24, count 2 2006.202.00:37:50.41#ibcon#*after write, iclass 24, count 2 2006.202.00:37:50.41#ibcon#*before return 0, iclass 24, count 2 2006.202.00:37:50.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:50.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:50.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.00:37:50.41#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:50.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:50.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:50.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:50.53#ibcon#enter wrdev, iclass 24, count 0 2006.202.00:37:50.53#ibcon#first serial, iclass 24, count 0 2006.202.00:37:50.53#ibcon#enter sib2, iclass 24, count 0 2006.202.00:37:50.53#ibcon#flushed, iclass 24, count 0 2006.202.00:37:50.53#ibcon#about to write, iclass 24, count 0 2006.202.00:37:50.53#ibcon#wrote, iclass 24, count 0 2006.202.00:37:50.53#ibcon#about to read 3, iclass 24, count 0 2006.202.00:37:50.55#ibcon#read 3, iclass 24, count 0 2006.202.00:37:50.55#ibcon#about to read 4, iclass 24, count 0 2006.202.00:37:50.55#ibcon#read 4, iclass 24, count 0 2006.202.00:37:50.55#ibcon#about to read 5, iclass 24, count 0 2006.202.00:37:50.55#ibcon#read 5, iclass 24, count 0 2006.202.00:37:50.55#ibcon#about to read 6, iclass 24, count 0 2006.202.00:37:50.55#ibcon#read 6, iclass 24, count 0 2006.202.00:37:50.55#ibcon#end of sib2, iclass 24, count 0 2006.202.00:37:50.55#ibcon#*mode == 0, iclass 24, count 0 2006.202.00:37:50.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.00:37:50.55#ibcon#[25=USB\r\n] 2006.202.00:37:50.55#ibcon#*before write, iclass 24, count 0 2006.202.00:37:50.55#ibcon#enter sib2, iclass 24, count 0 2006.202.00:37:50.55#ibcon#flushed, iclass 24, count 0 2006.202.00:37:50.55#ibcon#about to write, iclass 24, count 0 2006.202.00:37:50.55#ibcon#wrote, iclass 24, count 0 2006.202.00:37:50.55#ibcon#about to read 3, iclass 24, count 0 2006.202.00:37:50.58#ibcon#read 3, iclass 24, count 0 2006.202.00:37:50.58#ibcon#about to read 4, iclass 24, count 0 2006.202.00:37:50.58#ibcon#read 4, iclass 24, count 0 2006.202.00:37:50.58#ibcon#about to read 5, iclass 24, count 0 2006.202.00:37:50.58#ibcon#read 5, iclass 24, count 0 2006.202.00:37:50.58#ibcon#about to read 6, iclass 24, count 0 2006.202.00:37:50.58#ibcon#read 6, iclass 24, count 0 2006.202.00:37:50.58#ibcon#end of sib2, iclass 24, count 0 2006.202.00:37:50.58#ibcon#*after write, iclass 24, count 0 2006.202.00:37:50.58#ibcon#*before return 0, iclass 24, count 0 2006.202.00:37:50.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:50.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:50.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.00:37:50.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.00:37:50.58$vck44/valo=5,734.99 2006.202.00:37:50.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.00:37:50.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.00:37:50.58#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:50.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:50.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:50.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:50.58#ibcon#enter wrdev, iclass 26, count 0 2006.202.00:37:50.58#ibcon#first serial, iclass 26, count 0 2006.202.00:37:50.58#ibcon#enter sib2, iclass 26, count 0 2006.202.00:37:50.58#ibcon#flushed, iclass 26, count 0 2006.202.00:37:50.58#ibcon#about to write, iclass 26, count 0 2006.202.00:37:50.58#ibcon#wrote, iclass 26, count 0 2006.202.00:37:50.58#ibcon#about to read 3, iclass 26, count 0 2006.202.00:37:50.60#ibcon#read 3, iclass 26, count 0 2006.202.00:37:50.60#ibcon#about to read 4, iclass 26, count 0 2006.202.00:37:50.60#ibcon#read 4, iclass 26, count 0 2006.202.00:37:50.60#ibcon#about to read 5, iclass 26, count 0 2006.202.00:37:50.60#ibcon#read 5, iclass 26, count 0 2006.202.00:37:50.60#ibcon#about to read 6, iclass 26, count 0 2006.202.00:37:50.60#ibcon#read 6, iclass 26, count 0 2006.202.00:37:50.60#ibcon#end of sib2, iclass 26, count 0 2006.202.00:37:50.60#ibcon#*mode == 0, iclass 26, count 0 2006.202.00:37:50.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.00:37:50.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.00:37:50.60#ibcon#*before write, iclass 26, count 0 2006.202.00:37:50.60#ibcon#enter sib2, iclass 26, count 0 2006.202.00:37:50.60#ibcon#flushed, iclass 26, count 0 2006.202.00:37:50.60#ibcon#about to write, iclass 26, count 0 2006.202.00:37:50.60#ibcon#wrote, iclass 26, count 0 2006.202.00:37:50.60#ibcon#about to read 3, iclass 26, count 0 2006.202.00:37:50.64#ibcon#read 3, iclass 26, count 0 2006.202.00:37:50.64#ibcon#about to read 4, iclass 26, count 0 2006.202.00:37:50.64#ibcon#read 4, iclass 26, count 0 2006.202.00:37:50.64#ibcon#about to read 5, iclass 26, count 0 2006.202.00:37:50.64#ibcon#read 5, iclass 26, count 0 2006.202.00:37:50.64#ibcon#about to read 6, iclass 26, count 0 2006.202.00:37:50.64#ibcon#read 6, iclass 26, count 0 2006.202.00:37:50.64#ibcon#end of sib2, iclass 26, count 0 2006.202.00:37:50.64#ibcon#*after write, iclass 26, count 0 2006.202.00:37:50.64#ibcon#*before return 0, iclass 26, count 0 2006.202.00:37:50.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:50.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:50.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.00:37:50.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.00:37:50.64$vck44/va=5,4 2006.202.00:37:50.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.00:37:50.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.00:37:50.64#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:50.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:50.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:50.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:50.70#ibcon#enter wrdev, iclass 28, count 2 2006.202.00:37:50.70#ibcon#first serial, iclass 28, count 2 2006.202.00:37:50.70#ibcon#enter sib2, iclass 28, count 2 2006.202.00:37:50.70#ibcon#flushed, iclass 28, count 2 2006.202.00:37:50.70#ibcon#about to write, iclass 28, count 2 2006.202.00:37:50.70#ibcon#wrote, iclass 28, count 2 2006.202.00:37:50.70#ibcon#about to read 3, iclass 28, count 2 2006.202.00:37:50.72#ibcon#read 3, iclass 28, count 2 2006.202.00:37:50.72#ibcon#about to read 4, iclass 28, count 2 2006.202.00:37:50.72#ibcon#read 4, iclass 28, count 2 2006.202.00:37:50.72#ibcon#about to read 5, iclass 28, count 2 2006.202.00:37:50.72#ibcon#read 5, iclass 28, count 2 2006.202.00:37:50.72#ibcon#about to read 6, iclass 28, count 2 2006.202.00:37:50.72#ibcon#read 6, iclass 28, count 2 2006.202.00:37:50.72#ibcon#end of sib2, iclass 28, count 2 2006.202.00:37:50.72#ibcon#*mode == 0, iclass 28, count 2 2006.202.00:37:50.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.00:37:50.72#ibcon#[25=AT05-04\r\n] 2006.202.00:37:50.72#ibcon#*before write, iclass 28, count 2 2006.202.00:37:50.72#ibcon#enter sib2, iclass 28, count 2 2006.202.00:37:50.72#ibcon#flushed, iclass 28, count 2 2006.202.00:37:50.72#ibcon#about to write, iclass 28, count 2 2006.202.00:37:50.72#ibcon#wrote, iclass 28, count 2 2006.202.00:37:50.72#ibcon#about to read 3, iclass 28, count 2 2006.202.00:37:50.75#ibcon#read 3, iclass 28, count 2 2006.202.00:37:50.75#ibcon#about to read 4, iclass 28, count 2 2006.202.00:37:50.75#ibcon#read 4, iclass 28, count 2 2006.202.00:37:50.75#ibcon#about to read 5, iclass 28, count 2 2006.202.00:37:50.75#ibcon#read 5, iclass 28, count 2 2006.202.00:37:50.75#ibcon#about to read 6, iclass 28, count 2 2006.202.00:37:50.75#ibcon#read 6, iclass 28, count 2 2006.202.00:37:50.75#ibcon#end of sib2, iclass 28, count 2 2006.202.00:37:50.75#ibcon#*after write, iclass 28, count 2 2006.202.00:37:50.75#ibcon#*before return 0, iclass 28, count 2 2006.202.00:37:50.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:50.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:50.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.00:37:50.75#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:50.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:50.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:50.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:50.87#ibcon#enter wrdev, iclass 28, count 0 2006.202.00:37:50.87#ibcon#first serial, iclass 28, count 0 2006.202.00:37:50.87#ibcon#enter sib2, iclass 28, count 0 2006.202.00:37:50.87#ibcon#flushed, iclass 28, count 0 2006.202.00:37:50.87#ibcon#about to write, iclass 28, count 0 2006.202.00:37:50.87#ibcon#wrote, iclass 28, count 0 2006.202.00:37:50.87#ibcon#about to read 3, iclass 28, count 0 2006.202.00:37:50.89#ibcon#read 3, iclass 28, count 0 2006.202.00:37:50.89#ibcon#about to read 4, iclass 28, count 0 2006.202.00:37:50.89#ibcon#read 4, iclass 28, count 0 2006.202.00:37:50.89#ibcon#about to read 5, iclass 28, count 0 2006.202.00:37:50.89#ibcon#read 5, iclass 28, count 0 2006.202.00:37:50.89#ibcon#about to read 6, iclass 28, count 0 2006.202.00:37:50.89#ibcon#read 6, iclass 28, count 0 2006.202.00:37:50.89#ibcon#end of sib2, iclass 28, count 0 2006.202.00:37:50.89#ibcon#*mode == 0, iclass 28, count 0 2006.202.00:37:50.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.00:37:50.89#ibcon#[25=USB\r\n] 2006.202.00:37:50.89#ibcon#*before write, iclass 28, count 0 2006.202.00:37:50.89#ibcon#enter sib2, iclass 28, count 0 2006.202.00:37:50.89#ibcon#flushed, iclass 28, count 0 2006.202.00:37:50.89#ibcon#about to write, iclass 28, count 0 2006.202.00:37:50.89#ibcon#wrote, iclass 28, count 0 2006.202.00:37:50.89#ibcon#about to read 3, iclass 28, count 0 2006.202.00:37:50.92#ibcon#read 3, iclass 28, count 0 2006.202.00:37:50.92#ibcon#about to read 4, iclass 28, count 0 2006.202.00:37:50.92#ibcon#read 4, iclass 28, count 0 2006.202.00:37:50.92#ibcon#about to read 5, iclass 28, count 0 2006.202.00:37:50.92#ibcon#read 5, iclass 28, count 0 2006.202.00:37:50.92#ibcon#about to read 6, iclass 28, count 0 2006.202.00:37:50.92#ibcon#read 6, iclass 28, count 0 2006.202.00:37:50.92#ibcon#end of sib2, iclass 28, count 0 2006.202.00:37:50.92#ibcon#*after write, iclass 28, count 0 2006.202.00:37:50.92#ibcon#*before return 0, iclass 28, count 0 2006.202.00:37:50.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:50.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:50.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.00:37:50.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.00:37:50.92$vck44/valo=6,814.99 2006.202.00:37:50.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.00:37:50.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.00:37:50.92#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:50.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:50.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:50.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:50.92#ibcon#enter wrdev, iclass 30, count 0 2006.202.00:37:50.92#ibcon#first serial, iclass 30, count 0 2006.202.00:37:50.92#ibcon#enter sib2, iclass 30, count 0 2006.202.00:37:50.92#ibcon#flushed, iclass 30, count 0 2006.202.00:37:50.92#ibcon#about to write, iclass 30, count 0 2006.202.00:37:50.92#ibcon#wrote, iclass 30, count 0 2006.202.00:37:50.92#ibcon#about to read 3, iclass 30, count 0 2006.202.00:37:50.94#ibcon#read 3, iclass 30, count 0 2006.202.00:37:50.94#ibcon#about to read 4, iclass 30, count 0 2006.202.00:37:50.94#ibcon#read 4, iclass 30, count 0 2006.202.00:37:50.94#ibcon#about to read 5, iclass 30, count 0 2006.202.00:37:50.94#ibcon#read 5, iclass 30, count 0 2006.202.00:37:50.94#ibcon#about to read 6, iclass 30, count 0 2006.202.00:37:50.94#ibcon#read 6, iclass 30, count 0 2006.202.00:37:50.94#ibcon#end of sib2, iclass 30, count 0 2006.202.00:37:50.94#ibcon#*mode == 0, iclass 30, count 0 2006.202.00:37:50.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.00:37:50.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.00:37:50.94#ibcon#*before write, iclass 30, count 0 2006.202.00:37:50.94#ibcon#enter sib2, iclass 30, count 0 2006.202.00:37:50.94#ibcon#flushed, iclass 30, count 0 2006.202.00:37:50.94#ibcon#about to write, iclass 30, count 0 2006.202.00:37:50.94#ibcon#wrote, iclass 30, count 0 2006.202.00:37:50.94#ibcon#about to read 3, iclass 30, count 0 2006.202.00:37:50.98#ibcon#read 3, iclass 30, count 0 2006.202.00:37:50.98#ibcon#about to read 4, iclass 30, count 0 2006.202.00:37:50.98#ibcon#read 4, iclass 30, count 0 2006.202.00:37:50.98#ibcon#about to read 5, iclass 30, count 0 2006.202.00:37:50.98#ibcon#read 5, iclass 30, count 0 2006.202.00:37:50.98#ibcon#about to read 6, iclass 30, count 0 2006.202.00:37:50.98#ibcon#read 6, iclass 30, count 0 2006.202.00:37:50.98#ibcon#end of sib2, iclass 30, count 0 2006.202.00:37:50.98#ibcon#*after write, iclass 30, count 0 2006.202.00:37:50.98#ibcon#*before return 0, iclass 30, count 0 2006.202.00:37:50.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:50.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:50.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.00:37:50.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.00:37:50.98$vck44/va=6,5 2006.202.00:37:50.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.00:37:50.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.00:37:50.98#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:50.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:51.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:51.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:51.04#ibcon#enter wrdev, iclass 32, count 2 2006.202.00:37:51.04#ibcon#first serial, iclass 32, count 2 2006.202.00:37:51.04#ibcon#enter sib2, iclass 32, count 2 2006.202.00:37:51.04#ibcon#flushed, iclass 32, count 2 2006.202.00:37:51.04#ibcon#about to write, iclass 32, count 2 2006.202.00:37:51.04#ibcon#wrote, iclass 32, count 2 2006.202.00:37:51.04#ibcon#about to read 3, iclass 32, count 2 2006.202.00:37:51.06#ibcon#read 3, iclass 32, count 2 2006.202.00:37:51.06#ibcon#about to read 4, iclass 32, count 2 2006.202.00:37:51.06#ibcon#read 4, iclass 32, count 2 2006.202.00:37:51.06#ibcon#about to read 5, iclass 32, count 2 2006.202.00:37:51.06#ibcon#read 5, iclass 32, count 2 2006.202.00:37:51.06#ibcon#about to read 6, iclass 32, count 2 2006.202.00:37:51.06#ibcon#read 6, iclass 32, count 2 2006.202.00:37:51.06#ibcon#end of sib2, iclass 32, count 2 2006.202.00:37:51.06#ibcon#*mode == 0, iclass 32, count 2 2006.202.00:37:51.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.00:37:51.06#ibcon#[25=AT06-05\r\n] 2006.202.00:37:51.06#ibcon#*before write, iclass 32, count 2 2006.202.00:37:51.06#ibcon#enter sib2, iclass 32, count 2 2006.202.00:37:51.06#ibcon#flushed, iclass 32, count 2 2006.202.00:37:51.06#ibcon#about to write, iclass 32, count 2 2006.202.00:37:51.06#ibcon#wrote, iclass 32, count 2 2006.202.00:37:51.06#ibcon#about to read 3, iclass 32, count 2 2006.202.00:37:51.09#ibcon#read 3, iclass 32, count 2 2006.202.00:37:51.09#ibcon#about to read 4, iclass 32, count 2 2006.202.00:37:51.09#ibcon#read 4, iclass 32, count 2 2006.202.00:37:51.09#ibcon#about to read 5, iclass 32, count 2 2006.202.00:37:51.09#ibcon#read 5, iclass 32, count 2 2006.202.00:37:51.09#ibcon#about to read 6, iclass 32, count 2 2006.202.00:37:51.09#ibcon#read 6, iclass 32, count 2 2006.202.00:37:51.09#ibcon#end of sib2, iclass 32, count 2 2006.202.00:37:51.09#ibcon#*after write, iclass 32, count 2 2006.202.00:37:51.09#ibcon#*before return 0, iclass 32, count 2 2006.202.00:37:51.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:51.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:51.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.00:37:51.09#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:51.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:51.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:51.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:51.21#ibcon#enter wrdev, iclass 32, count 0 2006.202.00:37:51.21#ibcon#first serial, iclass 32, count 0 2006.202.00:37:51.21#ibcon#enter sib2, iclass 32, count 0 2006.202.00:37:51.21#ibcon#flushed, iclass 32, count 0 2006.202.00:37:51.21#ibcon#about to write, iclass 32, count 0 2006.202.00:37:51.21#ibcon#wrote, iclass 32, count 0 2006.202.00:37:51.21#ibcon#about to read 3, iclass 32, count 0 2006.202.00:37:51.23#ibcon#read 3, iclass 32, count 0 2006.202.00:37:51.23#ibcon#about to read 4, iclass 32, count 0 2006.202.00:37:51.23#ibcon#read 4, iclass 32, count 0 2006.202.00:37:51.23#ibcon#about to read 5, iclass 32, count 0 2006.202.00:37:51.23#ibcon#read 5, iclass 32, count 0 2006.202.00:37:51.23#ibcon#about to read 6, iclass 32, count 0 2006.202.00:37:51.23#ibcon#read 6, iclass 32, count 0 2006.202.00:37:51.23#ibcon#end of sib2, iclass 32, count 0 2006.202.00:37:51.23#ibcon#*mode == 0, iclass 32, count 0 2006.202.00:37:51.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.00:37:51.23#ibcon#[25=USB\r\n] 2006.202.00:37:51.23#ibcon#*before write, iclass 32, count 0 2006.202.00:37:51.23#ibcon#enter sib2, iclass 32, count 0 2006.202.00:37:51.23#ibcon#flushed, iclass 32, count 0 2006.202.00:37:51.23#ibcon#about to write, iclass 32, count 0 2006.202.00:37:51.23#ibcon#wrote, iclass 32, count 0 2006.202.00:37:51.23#ibcon#about to read 3, iclass 32, count 0 2006.202.00:37:51.26#ibcon#read 3, iclass 32, count 0 2006.202.00:37:51.26#ibcon#about to read 4, iclass 32, count 0 2006.202.00:37:51.26#ibcon#read 4, iclass 32, count 0 2006.202.00:37:51.26#ibcon#about to read 5, iclass 32, count 0 2006.202.00:37:51.26#ibcon#read 5, iclass 32, count 0 2006.202.00:37:51.26#ibcon#about to read 6, iclass 32, count 0 2006.202.00:37:51.26#ibcon#read 6, iclass 32, count 0 2006.202.00:37:51.26#ibcon#end of sib2, iclass 32, count 0 2006.202.00:37:51.26#ibcon#*after write, iclass 32, count 0 2006.202.00:37:51.26#ibcon#*before return 0, iclass 32, count 0 2006.202.00:37:51.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:51.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:51.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.00:37:51.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.00:37:51.26$vck44/valo=7,864.99 2006.202.00:37:51.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.00:37:51.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.00:37:51.26#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:51.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:37:51.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:37:51.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:37:51.26#ibcon#enter wrdev, iclass 34, count 0 2006.202.00:37:51.26#ibcon#first serial, iclass 34, count 0 2006.202.00:37:51.26#ibcon#enter sib2, iclass 34, count 0 2006.202.00:37:51.26#ibcon#flushed, iclass 34, count 0 2006.202.00:37:51.26#ibcon#about to write, iclass 34, count 0 2006.202.00:37:51.26#ibcon#wrote, iclass 34, count 0 2006.202.00:37:51.26#ibcon#about to read 3, iclass 34, count 0 2006.202.00:37:51.28#ibcon#read 3, iclass 34, count 0 2006.202.00:37:51.28#ibcon#about to read 4, iclass 34, count 0 2006.202.00:37:51.28#ibcon#read 4, iclass 34, count 0 2006.202.00:37:51.28#ibcon#about to read 5, iclass 34, count 0 2006.202.00:37:51.28#ibcon#read 5, iclass 34, count 0 2006.202.00:37:51.28#ibcon#about to read 6, iclass 34, count 0 2006.202.00:37:51.28#ibcon#read 6, iclass 34, count 0 2006.202.00:37:51.28#ibcon#end of sib2, iclass 34, count 0 2006.202.00:37:51.28#ibcon#*mode == 0, iclass 34, count 0 2006.202.00:37:51.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.00:37:51.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.00:37:51.28#ibcon#*before write, iclass 34, count 0 2006.202.00:37:51.28#ibcon#enter sib2, iclass 34, count 0 2006.202.00:37:51.28#ibcon#flushed, iclass 34, count 0 2006.202.00:37:51.28#ibcon#about to write, iclass 34, count 0 2006.202.00:37:51.28#ibcon#wrote, iclass 34, count 0 2006.202.00:37:51.28#ibcon#about to read 3, iclass 34, count 0 2006.202.00:37:51.32#ibcon#read 3, iclass 34, count 0 2006.202.00:37:51.32#ibcon#about to read 4, iclass 34, count 0 2006.202.00:37:51.32#ibcon#read 4, iclass 34, count 0 2006.202.00:37:51.32#ibcon#about to read 5, iclass 34, count 0 2006.202.00:37:51.32#ibcon#read 5, iclass 34, count 0 2006.202.00:37:51.32#ibcon#about to read 6, iclass 34, count 0 2006.202.00:37:51.32#ibcon#read 6, iclass 34, count 0 2006.202.00:37:51.32#ibcon#end of sib2, iclass 34, count 0 2006.202.00:37:51.32#ibcon#*after write, iclass 34, count 0 2006.202.00:37:51.32#ibcon#*before return 0, iclass 34, count 0 2006.202.00:37:51.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:37:51.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:37:51.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.00:37:51.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.00:37:51.32$vck44/va=7,5 2006.202.00:37:51.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.00:37:51.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.00:37:51.32#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:51.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:37:51.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:37:51.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:37:51.38#ibcon#enter wrdev, iclass 36, count 2 2006.202.00:37:51.38#ibcon#first serial, iclass 36, count 2 2006.202.00:37:51.38#ibcon#enter sib2, iclass 36, count 2 2006.202.00:37:51.38#ibcon#flushed, iclass 36, count 2 2006.202.00:37:51.38#ibcon#about to write, iclass 36, count 2 2006.202.00:37:51.38#ibcon#wrote, iclass 36, count 2 2006.202.00:37:51.38#ibcon#about to read 3, iclass 36, count 2 2006.202.00:37:51.40#ibcon#read 3, iclass 36, count 2 2006.202.00:37:51.40#ibcon#about to read 4, iclass 36, count 2 2006.202.00:37:51.40#ibcon#read 4, iclass 36, count 2 2006.202.00:37:51.40#ibcon#about to read 5, iclass 36, count 2 2006.202.00:37:51.40#ibcon#read 5, iclass 36, count 2 2006.202.00:37:51.40#ibcon#about to read 6, iclass 36, count 2 2006.202.00:37:51.40#ibcon#read 6, iclass 36, count 2 2006.202.00:37:51.40#ibcon#end of sib2, iclass 36, count 2 2006.202.00:37:51.40#ibcon#*mode == 0, iclass 36, count 2 2006.202.00:37:51.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.00:37:51.40#ibcon#[25=AT07-05\r\n] 2006.202.00:37:51.40#ibcon#*before write, iclass 36, count 2 2006.202.00:37:51.40#ibcon#enter sib2, iclass 36, count 2 2006.202.00:37:51.40#ibcon#flushed, iclass 36, count 2 2006.202.00:37:51.40#ibcon#about to write, iclass 36, count 2 2006.202.00:37:51.40#ibcon#wrote, iclass 36, count 2 2006.202.00:37:51.40#ibcon#about to read 3, iclass 36, count 2 2006.202.00:37:51.43#ibcon#read 3, iclass 36, count 2 2006.202.00:37:51.49#ibcon#about to read 4, iclass 36, count 2 2006.202.00:37:51.49#ibcon#read 4, iclass 36, count 2 2006.202.00:37:51.49#ibcon#about to read 5, iclass 36, count 2 2006.202.00:37:51.49#ibcon#read 5, iclass 36, count 2 2006.202.00:37:51.49#ibcon#about to read 6, iclass 36, count 2 2006.202.00:37:51.49#ibcon#read 6, iclass 36, count 2 2006.202.00:37:51.49#ibcon#end of sib2, iclass 36, count 2 2006.202.00:37:51.49#ibcon#*after write, iclass 36, count 2 2006.202.00:37:51.49#ibcon#*before return 0, iclass 36, count 2 2006.202.00:37:51.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:37:51.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:37:51.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.00:37:51.49#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:51.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:37:51.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:37:51.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:37:51.61#ibcon#enter wrdev, iclass 36, count 0 2006.202.00:37:51.61#ibcon#first serial, iclass 36, count 0 2006.202.00:37:51.61#ibcon#enter sib2, iclass 36, count 0 2006.202.00:37:51.61#ibcon#flushed, iclass 36, count 0 2006.202.00:37:51.61#ibcon#about to write, iclass 36, count 0 2006.202.00:37:51.61#ibcon#wrote, iclass 36, count 0 2006.202.00:37:51.61#ibcon#about to read 3, iclass 36, count 0 2006.202.00:37:51.63#ibcon#read 3, iclass 36, count 0 2006.202.00:37:51.63#ibcon#about to read 4, iclass 36, count 0 2006.202.00:37:51.63#ibcon#read 4, iclass 36, count 0 2006.202.00:37:51.63#ibcon#about to read 5, iclass 36, count 0 2006.202.00:37:51.63#ibcon#read 5, iclass 36, count 0 2006.202.00:37:51.63#ibcon#about to read 6, iclass 36, count 0 2006.202.00:37:51.63#ibcon#read 6, iclass 36, count 0 2006.202.00:37:51.63#ibcon#end of sib2, iclass 36, count 0 2006.202.00:37:51.63#ibcon#*mode == 0, iclass 36, count 0 2006.202.00:37:51.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.00:37:51.63#ibcon#[25=USB\r\n] 2006.202.00:37:51.63#ibcon#*before write, iclass 36, count 0 2006.202.00:37:51.63#ibcon#enter sib2, iclass 36, count 0 2006.202.00:37:51.63#ibcon#flushed, iclass 36, count 0 2006.202.00:37:51.63#ibcon#about to write, iclass 36, count 0 2006.202.00:37:51.63#ibcon#wrote, iclass 36, count 0 2006.202.00:37:51.63#ibcon#about to read 3, iclass 36, count 0 2006.202.00:37:51.66#ibcon#read 3, iclass 36, count 0 2006.202.00:37:51.66#ibcon#about to read 4, iclass 36, count 0 2006.202.00:37:51.66#ibcon#read 4, iclass 36, count 0 2006.202.00:37:51.66#ibcon#about to read 5, iclass 36, count 0 2006.202.00:37:51.66#ibcon#read 5, iclass 36, count 0 2006.202.00:37:51.66#ibcon#about to read 6, iclass 36, count 0 2006.202.00:37:51.66#ibcon#read 6, iclass 36, count 0 2006.202.00:37:51.66#ibcon#end of sib2, iclass 36, count 0 2006.202.00:37:51.66#ibcon#*after write, iclass 36, count 0 2006.202.00:37:51.66#ibcon#*before return 0, iclass 36, count 0 2006.202.00:37:51.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:37:51.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:37:51.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.00:37:51.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.00:37:51.66$vck44/valo=8,884.99 2006.202.00:37:51.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.00:37:51.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.00:37:51.66#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:51.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:37:51.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:37:51.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:37:51.66#ibcon#enter wrdev, iclass 38, count 0 2006.202.00:37:51.66#ibcon#first serial, iclass 38, count 0 2006.202.00:37:51.66#ibcon#enter sib2, iclass 38, count 0 2006.202.00:37:51.66#ibcon#flushed, iclass 38, count 0 2006.202.00:37:51.66#ibcon#about to write, iclass 38, count 0 2006.202.00:37:51.66#ibcon#wrote, iclass 38, count 0 2006.202.00:37:51.66#ibcon#about to read 3, iclass 38, count 0 2006.202.00:37:51.68#ibcon#read 3, iclass 38, count 0 2006.202.00:37:51.68#ibcon#about to read 4, iclass 38, count 0 2006.202.00:37:51.68#ibcon#read 4, iclass 38, count 0 2006.202.00:37:51.68#ibcon#about to read 5, iclass 38, count 0 2006.202.00:37:51.68#ibcon#read 5, iclass 38, count 0 2006.202.00:37:51.68#ibcon#about to read 6, iclass 38, count 0 2006.202.00:37:51.68#ibcon#read 6, iclass 38, count 0 2006.202.00:37:51.68#ibcon#end of sib2, iclass 38, count 0 2006.202.00:37:51.68#ibcon#*mode == 0, iclass 38, count 0 2006.202.00:37:51.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.00:37:51.68#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.00:37:51.68#ibcon#*before write, iclass 38, count 0 2006.202.00:37:51.68#ibcon#enter sib2, iclass 38, count 0 2006.202.00:37:51.68#ibcon#flushed, iclass 38, count 0 2006.202.00:37:51.68#ibcon#about to write, iclass 38, count 0 2006.202.00:37:51.68#ibcon#wrote, iclass 38, count 0 2006.202.00:37:51.68#ibcon#about to read 3, iclass 38, count 0 2006.202.00:37:51.72#ibcon#read 3, iclass 38, count 0 2006.202.00:37:51.72#ibcon#about to read 4, iclass 38, count 0 2006.202.00:37:51.72#ibcon#read 4, iclass 38, count 0 2006.202.00:37:51.72#ibcon#about to read 5, iclass 38, count 0 2006.202.00:37:51.72#ibcon#read 5, iclass 38, count 0 2006.202.00:37:51.72#ibcon#about to read 6, iclass 38, count 0 2006.202.00:37:51.72#ibcon#read 6, iclass 38, count 0 2006.202.00:37:51.72#ibcon#end of sib2, iclass 38, count 0 2006.202.00:37:51.72#ibcon#*after write, iclass 38, count 0 2006.202.00:37:51.72#ibcon#*before return 0, iclass 38, count 0 2006.202.00:37:51.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:37:51.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:37:51.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.00:37:51.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.00:37:51.72$vck44/va=8,4 2006.202.00:37:51.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.202.00:37:51.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.202.00:37:51.72#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:51.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:37:51.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:37:51.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:37:51.78#ibcon#enter wrdev, iclass 40, count 2 2006.202.00:37:51.78#ibcon#first serial, iclass 40, count 2 2006.202.00:37:51.78#ibcon#enter sib2, iclass 40, count 2 2006.202.00:37:51.78#ibcon#flushed, iclass 40, count 2 2006.202.00:37:51.78#ibcon#about to write, iclass 40, count 2 2006.202.00:37:51.78#ibcon#wrote, iclass 40, count 2 2006.202.00:37:51.78#ibcon#about to read 3, iclass 40, count 2 2006.202.00:37:51.80#ibcon#read 3, iclass 40, count 2 2006.202.00:37:51.80#ibcon#about to read 4, iclass 40, count 2 2006.202.00:37:51.80#ibcon#read 4, iclass 40, count 2 2006.202.00:37:51.80#ibcon#about to read 5, iclass 40, count 2 2006.202.00:37:51.80#ibcon#read 5, iclass 40, count 2 2006.202.00:37:51.80#ibcon#about to read 6, iclass 40, count 2 2006.202.00:37:51.80#ibcon#read 6, iclass 40, count 2 2006.202.00:37:51.80#ibcon#end of sib2, iclass 40, count 2 2006.202.00:37:51.80#ibcon#*mode == 0, iclass 40, count 2 2006.202.00:37:51.80#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.202.00:37:51.80#ibcon#[25=AT08-04\r\n] 2006.202.00:37:51.80#ibcon#*before write, iclass 40, count 2 2006.202.00:37:51.80#ibcon#enter sib2, iclass 40, count 2 2006.202.00:37:51.80#ibcon#flushed, iclass 40, count 2 2006.202.00:37:51.80#ibcon#about to write, iclass 40, count 2 2006.202.00:37:51.80#ibcon#wrote, iclass 40, count 2 2006.202.00:37:51.80#ibcon#about to read 3, iclass 40, count 2 2006.202.00:37:51.83#ibcon#read 3, iclass 40, count 2 2006.202.00:37:51.83#ibcon#about to read 4, iclass 40, count 2 2006.202.00:37:51.83#ibcon#read 4, iclass 40, count 2 2006.202.00:37:51.83#ibcon#about to read 5, iclass 40, count 2 2006.202.00:37:51.83#ibcon#read 5, iclass 40, count 2 2006.202.00:37:51.83#ibcon#about to read 6, iclass 40, count 2 2006.202.00:37:51.83#ibcon#read 6, iclass 40, count 2 2006.202.00:37:51.83#ibcon#end of sib2, iclass 40, count 2 2006.202.00:37:51.83#ibcon#*after write, iclass 40, count 2 2006.202.00:37:51.83#ibcon#*before return 0, iclass 40, count 2 2006.202.00:37:51.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:37:51.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:37:51.83#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.202.00:37:51.83#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:51.83#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:37:51.95#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:37:51.95#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:37:51.95#ibcon#enter wrdev, iclass 40, count 0 2006.202.00:37:51.95#ibcon#first serial, iclass 40, count 0 2006.202.00:37:51.95#ibcon#enter sib2, iclass 40, count 0 2006.202.00:37:51.95#ibcon#flushed, iclass 40, count 0 2006.202.00:37:51.95#ibcon#about to write, iclass 40, count 0 2006.202.00:37:51.95#ibcon#wrote, iclass 40, count 0 2006.202.00:37:51.95#ibcon#about to read 3, iclass 40, count 0 2006.202.00:37:51.97#ibcon#read 3, iclass 40, count 0 2006.202.00:37:51.97#ibcon#about to read 4, iclass 40, count 0 2006.202.00:37:51.97#ibcon#read 4, iclass 40, count 0 2006.202.00:37:51.97#ibcon#about to read 5, iclass 40, count 0 2006.202.00:37:51.97#ibcon#read 5, iclass 40, count 0 2006.202.00:37:51.97#ibcon#about to read 6, iclass 40, count 0 2006.202.00:37:51.97#ibcon#read 6, iclass 40, count 0 2006.202.00:37:51.97#ibcon#end of sib2, iclass 40, count 0 2006.202.00:37:51.97#ibcon#*mode == 0, iclass 40, count 0 2006.202.00:37:51.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.00:37:51.97#ibcon#[25=USB\r\n] 2006.202.00:37:51.97#ibcon#*before write, iclass 40, count 0 2006.202.00:37:51.97#ibcon#enter sib2, iclass 40, count 0 2006.202.00:37:51.97#ibcon#flushed, iclass 40, count 0 2006.202.00:37:51.97#ibcon#about to write, iclass 40, count 0 2006.202.00:37:51.97#ibcon#wrote, iclass 40, count 0 2006.202.00:37:51.97#ibcon#about to read 3, iclass 40, count 0 2006.202.00:37:52.00#ibcon#read 3, iclass 40, count 0 2006.202.00:37:52.00#ibcon#about to read 4, iclass 40, count 0 2006.202.00:37:52.00#ibcon#read 4, iclass 40, count 0 2006.202.00:37:52.00#ibcon#about to read 5, iclass 40, count 0 2006.202.00:37:52.00#ibcon#read 5, iclass 40, count 0 2006.202.00:37:52.00#ibcon#about to read 6, iclass 40, count 0 2006.202.00:37:52.00#ibcon#read 6, iclass 40, count 0 2006.202.00:37:52.00#ibcon#end of sib2, iclass 40, count 0 2006.202.00:37:52.00#ibcon#*after write, iclass 40, count 0 2006.202.00:37:52.00#ibcon#*before return 0, iclass 40, count 0 2006.202.00:37:52.00#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:37:52.00#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:37:52.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.00:37:52.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.00:37:52.00$vck44/vblo=1,629.99 2006.202.00:37:52.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.00:37:52.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.00:37:52.00#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:52.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:52.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:52.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:52.00#ibcon#enter wrdev, iclass 4, count 0 2006.202.00:37:52.00#ibcon#first serial, iclass 4, count 0 2006.202.00:37:52.00#ibcon#enter sib2, iclass 4, count 0 2006.202.00:37:52.00#ibcon#flushed, iclass 4, count 0 2006.202.00:37:52.00#ibcon#about to write, iclass 4, count 0 2006.202.00:37:52.00#ibcon#wrote, iclass 4, count 0 2006.202.00:37:52.00#ibcon#about to read 3, iclass 4, count 0 2006.202.00:37:52.02#ibcon#read 3, iclass 4, count 0 2006.202.00:37:52.02#ibcon#about to read 4, iclass 4, count 0 2006.202.00:37:52.02#ibcon#read 4, iclass 4, count 0 2006.202.00:37:52.02#ibcon#about to read 5, iclass 4, count 0 2006.202.00:37:52.02#ibcon#read 5, iclass 4, count 0 2006.202.00:37:52.02#ibcon#about to read 6, iclass 4, count 0 2006.202.00:37:52.02#ibcon#read 6, iclass 4, count 0 2006.202.00:37:52.02#ibcon#end of sib2, iclass 4, count 0 2006.202.00:37:52.02#ibcon#*mode == 0, iclass 4, count 0 2006.202.00:37:52.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.00:37:52.02#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.00:37:52.02#ibcon#*before write, iclass 4, count 0 2006.202.00:37:52.02#ibcon#enter sib2, iclass 4, count 0 2006.202.00:37:52.02#ibcon#flushed, iclass 4, count 0 2006.202.00:37:52.02#ibcon#about to write, iclass 4, count 0 2006.202.00:37:52.02#ibcon#wrote, iclass 4, count 0 2006.202.00:37:52.02#ibcon#about to read 3, iclass 4, count 0 2006.202.00:37:52.06#ibcon#read 3, iclass 4, count 0 2006.202.00:37:52.06#ibcon#about to read 4, iclass 4, count 0 2006.202.00:37:52.06#ibcon#read 4, iclass 4, count 0 2006.202.00:37:52.06#ibcon#about to read 5, iclass 4, count 0 2006.202.00:37:52.06#ibcon#read 5, iclass 4, count 0 2006.202.00:37:52.06#ibcon#about to read 6, iclass 4, count 0 2006.202.00:37:52.06#ibcon#read 6, iclass 4, count 0 2006.202.00:37:52.06#ibcon#end of sib2, iclass 4, count 0 2006.202.00:37:52.06#ibcon#*after write, iclass 4, count 0 2006.202.00:37:52.06#ibcon#*before return 0, iclass 4, count 0 2006.202.00:37:52.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:52.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:52.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.00:37:52.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.00:37:52.06$vck44/vb=1,4 2006.202.00:37:52.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.202.00:37:52.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.202.00:37:52.06#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:52.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:37:52.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:37:52.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:37:52.06#ibcon#enter wrdev, iclass 6, count 2 2006.202.00:37:52.06#ibcon#first serial, iclass 6, count 2 2006.202.00:37:52.06#ibcon#enter sib2, iclass 6, count 2 2006.202.00:37:52.06#ibcon#flushed, iclass 6, count 2 2006.202.00:37:52.06#ibcon#about to write, iclass 6, count 2 2006.202.00:37:52.06#ibcon#wrote, iclass 6, count 2 2006.202.00:37:52.06#ibcon#about to read 3, iclass 6, count 2 2006.202.00:37:52.08#ibcon#read 3, iclass 6, count 2 2006.202.00:37:52.08#ibcon#about to read 4, iclass 6, count 2 2006.202.00:37:52.08#ibcon#read 4, iclass 6, count 2 2006.202.00:37:52.08#ibcon#about to read 5, iclass 6, count 2 2006.202.00:37:52.08#ibcon#read 5, iclass 6, count 2 2006.202.00:37:52.08#ibcon#about to read 6, iclass 6, count 2 2006.202.00:37:52.08#ibcon#read 6, iclass 6, count 2 2006.202.00:37:52.08#ibcon#end of sib2, iclass 6, count 2 2006.202.00:37:52.08#ibcon#*mode == 0, iclass 6, count 2 2006.202.00:37:52.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.202.00:37:52.08#ibcon#[27=AT01-04\r\n] 2006.202.00:37:52.08#ibcon#*before write, iclass 6, count 2 2006.202.00:37:52.08#ibcon#enter sib2, iclass 6, count 2 2006.202.00:37:52.08#ibcon#flushed, iclass 6, count 2 2006.202.00:37:52.08#ibcon#about to write, iclass 6, count 2 2006.202.00:37:52.08#ibcon#wrote, iclass 6, count 2 2006.202.00:37:52.08#ibcon#about to read 3, iclass 6, count 2 2006.202.00:37:52.11#ibcon#read 3, iclass 6, count 2 2006.202.00:37:52.11#ibcon#about to read 4, iclass 6, count 2 2006.202.00:37:52.11#ibcon#read 4, iclass 6, count 2 2006.202.00:37:52.11#ibcon#about to read 5, iclass 6, count 2 2006.202.00:37:52.11#ibcon#read 5, iclass 6, count 2 2006.202.00:37:52.11#ibcon#about to read 6, iclass 6, count 2 2006.202.00:37:52.11#ibcon#read 6, iclass 6, count 2 2006.202.00:37:52.11#ibcon#end of sib2, iclass 6, count 2 2006.202.00:37:52.11#ibcon#*after write, iclass 6, count 2 2006.202.00:37:52.11#ibcon#*before return 0, iclass 6, count 2 2006.202.00:37:52.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:37:52.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:37:52.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.202.00:37:52.11#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:52.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:37:52.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:37:52.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:37:52.23#ibcon#enter wrdev, iclass 6, count 0 2006.202.00:37:52.23#ibcon#first serial, iclass 6, count 0 2006.202.00:37:52.23#ibcon#enter sib2, iclass 6, count 0 2006.202.00:37:52.23#ibcon#flushed, iclass 6, count 0 2006.202.00:37:52.23#ibcon#about to write, iclass 6, count 0 2006.202.00:37:52.23#ibcon#wrote, iclass 6, count 0 2006.202.00:37:52.23#ibcon#about to read 3, iclass 6, count 0 2006.202.00:37:52.25#ibcon#read 3, iclass 6, count 0 2006.202.00:37:52.25#ibcon#about to read 4, iclass 6, count 0 2006.202.00:37:52.25#ibcon#read 4, iclass 6, count 0 2006.202.00:37:52.25#ibcon#about to read 5, iclass 6, count 0 2006.202.00:37:52.25#ibcon#read 5, iclass 6, count 0 2006.202.00:37:52.25#ibcon#about to read 6, iclass 6, count 0 2006.202.00:37:52.25#ibcon#read 6, iclass 6, count 0 2006.202.00:37:52.25#ibcon#end of sib2, iclass 6, count 0 2006.202.00:37:52.25#ibcon#*mode == 0, iclass 6, count 0 2006.202.00:37:52.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.00:37:52.25#ibcon#[27=USB\r\n] 2006.202.00:37:52.25#ibcon#*before write, iclass 6, count 0 2006.202.00:37:52.25#ibcon#enter sib2, iclass 6, count 0 2006.202.00:37:52.25#ibcon#flushed, iclass 6, count 0 2006.202.00:37:52.25#ibcon#about to write, iclass 6, count 0 2006.202.00:37:52.25#ibcon#wrote, iclass 6, count 0 2006.202.00:37:52.25#ibcon#about to read 3, iclass 6, count 0 2006.202.00:37:52.28#ibcon#read 3, iclass 6, count 0 2006.202.00:37:52.28#ibcon#about to read 4, iclass 6, count 0 2006.202.00:37:52.28#ibcon#read 4, iclass 6, count 0 2006.202.00:37:52.28#ibcon#about to read 5, iclass 6, count 0 2006.202.00:37:52.28#ibcon#read 5, iclass 6, count 0 2006.202.00:37:52.28#ibcon#about to read 6, iclass 6, count 0 2006.202.00:37:52.28#ibcon#read 6, iclass 6, count 0 2006.202.00:37:52.28#ibcon#end of sib2, iclass 6, count 0 2006.202.00:37:52.28#ibcon#*after write, iclass 6, count 0 2006.202.00:37:52.28#ibcon#*before return 0, iclass 6, count 0 2006.202.00:37:52.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:37:52.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:37:52.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.00:37:52.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.00:37:52.28$vck44/vblo=2,634.99 2006.202.00:37:52.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.00:37:52.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.00:37:52.28#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:52.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:52.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:52.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:52.28#ibcon#enter wrdev, iclass 10, count 0 2006.202.00:37:52.28#ibcon#first serial, iclass 10, count 0 2006.202.00:37:52.28#ibcon#enter sib2, iclass 10, count 0 2006.202.00:37:52.28#ibcon#flushed, iclass 10, count 0 2006.202.00:37:52.28#ibcon#about to write, iclass 10, count 0 2006.202.00:37:52.28#ibcon#wrote, iclass 10, count 0 2006.202.00:37:52.28#ibcon#about to read 3, iclass 10, count 0 2006.202.00:37:52.30#ibcon#read 3, iclass 10, count 0 2006.202.00:37:52.30#ibcon#about to read 4, iclass 10, count 0 2006.202.00:37:52.30#ibcon#read 4, iclass 10, count 0 2006.202.00:37:52.30#ibcon#about to read 5, iclass 10, count 0 2006.202.00:37:52.30#ibcon#read 5, iclass 10, count 0 2006.202.00:37:52.30#ibcon#about to read 6, iclass 10, count 0 2006.202.00:37:52.30#ibcon#read 6, iclass 10, count 0 2006.202.00:37:52.30#ibcon#end of sib2, iclass 10, count 0 2006.202.00:37:52.30#ibcon#*mode == 0, iclass 10, count 0 2006.202.00:37:52.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.00:37:52.30#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.00:37:52.30#ibcon#*before write, iclass 10, count 0 2006.202.00:37:52.30#ibcon#enter sib2, iclass 10, count 0 2006.202.00:37:52.30#ibcon#flushed, iclass 10, count 0 2006.202.00:37:52.30#ibcon#about to write, iclass 10, count 0 2006.202.00:37:52.30#ibcon#wrote, iclass 10, count 0 2006.202.00:37:52.30#ibcon#about to read 3, iclass 10, count 0 2006.202.00:37:52.34#ibcon#read 3, iclass 10, count 0 2006.202.00:37:52.34#ibcon#about to read 4, iclass 10, count 0 2006.202.00:37:52.34#ibcon#read 4, iclass 10, count 0 2006.202.00:37:52.34#ibcon#about to read 5, iclass 10, count 0 2006.202.00:37:52.34#ibcon#read 5, iclass 10, count 0 2006.202.00:37:52.34#ibcon#about to read 6, iclass 10, count 0 2006.202.00:37:52.34#ibcon#read 6, iclass 10, count 0 2006.202.00:37:52.34#ibcon#end of sib2, iclass 10, count 0 2006.202.00:37:52.34#ibcon#*after write, iclass 10, count 0 2006.202.00:37:52.34#ibcon#*before return 0, iclass 10, count 0 2006.202.00:37:52.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:52.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:37:52.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.00:37:52.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.00:37:52.34$vck44/vb=2,5 2006.202.00:37:52.34#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.202.00:37:52.34#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.202.00:37:52.34#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:52.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:52.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:52.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:52.40#ibcon#enter wrdev, iclass 12, count 2 2006.202.00:37:52.40#ibcon#first serial, iclass 12, count 2 2006.202.00:37:52.40#ibcon#enter sib2, iclass 12, count 2 2006.202.00:37:52.40#ibcon#flushed, iclass 12, count 2 2006.202.00:37:52.40#ibcon#about to write, iclass 12, count 2 2006.202.00:37:52.40#ibcon#wrote, iclass 12, count 2 2006.202.00:37:52.40#ibcon#about to read 3, iclass 12, count 2 2006.202.00:37:52.42#ibcon#read 3, iclass 12, count 2 2006.202.00:37:52.42#ibcon#about to read 4, iclass 12, count 2 2006.202.00:37:52.42#ibcon#read 4, iclass 12, count 2 2006.202.00:37:52.42#ibcon#about to read 5, iclass 12, count 2 2006.202.00:37:52.42#ibcon#read 5, iclass 12, count 2 2006.202.00:37:52.42#ibcon#about to read 6, iclass 12, count 2 2006.202.00:37:52.42#ibcon#read 6, iclass 12, count 2 2006.202.00:37:52.42#ibcon#end of sib2, iclass 12, count 2 2006.202.00:37:52.42#ibcon#*mode == 0, iclass 12, count 2 2006.202.00:37:52.42#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.202.00:37:52.42#ibcon#[27=AT02-05\r\n] 2006.202.00:37:52.42#ibcon#*before write, iclass 12, count 2 2006.202.00:37:52.42#ibcon#enter sib2, iclass 12, count 2 2006.202.00:37:52.42#ibcon#flushed, iclass 12, count 2 2006.202.00:37:52.42#ibcon#about to write, iclass 12, count 2 2006.202.00:37:52.42#ibcon#wrote, iclass 12, count 2 2006.202.00:37:52.42#ibcon#about to read 3, iclass 12, count 2 2006.202.00:37:52.45#ibcon#read 3, iclass 12, count 2 2006.202.00:37:52.45#ibcon#about to read 4, iclass 12, count 2 2006.202.00:37:52.59#ibcon#read 4, iclass 12, count 2 2006.202.00:37:52.59#ibcon#about to read 5, iclass 12, count 2 2006.202.00:37:52.59#ibcon#read 5, iclass 12, count 2 2006.202.00:37:52.59#ibcon#about to read 6, iclass 12, count 2 2006.202.00:37:52.59#ibcon#read 6, iclass 12, count 2 2006.202.00:37:52.59#ibcon#end of sib2, iclass 12, count 2 2006.202.00:37:52.59#ibcon#*after write, iclass 12, count 2 2006.202.00:37:52.59#ibcon#*before return 0, iclass 12, count 2 2006.202.00:37:52.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:52.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:37:52.59#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.202.00:37:52.59#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:52.59#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:52.71#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:52.71#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:52.71#ibcon#enter wrdev, iclass 12, count 0 2006.202.00:37:52.71#ibcon#first serial, iclass 12, count 0 2006.202.00:37:52.71#ibcon#enter sib2, iclass 12, count 0 2006.202.00:37:52.71#ibcon#flushed, iclass 12, count 0 2006.202.00:37:52.71#ibcon#about to write, iclass 12, count 0 2006.202.00:37:52.71#ibcon#wrote, iclass 12, count 0 2006.202.00:37:52.71#ibcon#about to read 3, iclass 12, count 0 2006.202.00:37:52.73#ibcon#read 3, iclass 12, count 0 2006.202.00:37:52.73#ibcon#about to read 4, iclass 12, count 0 2006.202.00:37:52.73#ibcon#read 4, iclass 12, count 0 2006.202.00:37:52.73#ibcon#about to read 5, iclass 12, count 0 2006.202.00:37:52.73#ibcon#read 5, iclass 12, count 0 2006.202.00:37:52.73#ibcon#about to read 6, iclass 12, count 0 2006.202.00:37:52.73#ibcon#read 6, iclass 12, count 0 2006.202.00:37:52.73#ibcon#end of sib2, iclass 12, count 0 2006.202.00:37:52.73#ibcon#*mode == 0, iclass 12, count 0 2006.202.00:37:52.73#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.00:37:52.73#ibcon#[27=USB\r\n] 2006.202.00:37:52.73#ibcon#*before write, iclass 12, count 0 2006.202.00:37:52.73#ibcon#enter sib2, iclass 12, count 0 2006.202.00:37:52.73#ibcon#flushed, iclass 12, count 0 2006.202.00:37:52.73#ibcon#about to write, iclass 12, count 0 2006.202.00:37:52.73#ibcon#wrote, iclass 12, count 0 2006.202.00:37:52.73#ibcon#about to read 3, iclass 12, count 0 2006.202.00:37:52.76#ibcon#read 3, iclass 12, count 0 2006.202.00:37:52.76#ibcon#about to read 4, iclass 12, count 0 2006.202.00:37:52.76#ibcon#read 4, iclass 12, count 0 2006.202.00:37:52.76#ibcon#about to read 5, iclass 12, count 0 2006.202.00:37:52.76#ibcon#read 5, iclass 12, count 0 2006.202.00:37:52.76#ibcon#about to read 6, iclass 12, count 0 2006.202.00:37:52.76#ibcon#read 6, iclass 12, count 0 2006.202.00:37:52.76#ibcon#end of sib2, iclass 12, count 0 2006.202.00:37:52.76#ibcon#*after write, iclass 12, count 0 2006.202.00:37:52.76#ibcon#*before return 0, iclass 12, count 0 2006.202.00:37:52.76#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:52.76#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:37:52.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.00:37:52.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.00:37:52.76$vck44/vblo=3,649.99 2006.202.00:37:52.76#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.00:37:52.76#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.00:37:52.76#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:52.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:52.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:52.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:52.76#ibcon#enter wrdev, iclass 14, count 0 2006.202.00:37:52.76#ibcon#first serial, iclass 14, count 0 2006.202.00:37:52.76#ibcon#enter sib2, iclass 14, count 0 2006.202.00:37:52.76#ibcon#flushed, iclass 14, count 0 2006.202.00:37:52.76#ibcon#about to write, iclass 14, count 0 2006.202.00:37:52.76#ibcon#wrote, iclass 14, count 0 2006.202.00:37:52.76#ibcon#about to read 3, iclass 14, count 0 2006.202.00:37:52.78#ibcon#read 3, iclass 14, count 0 2006.202.00:37:52.78#ibcon#about to read 4, iclass 14, count 0 2006.202.00:37:52.78#ibcon#read 4, iclass 14, count 0 2006.202.00:37:52.78#ibcon#about to read 5, iclass 14, count 0 2006.202.00:37:52.78#ibcon#read 5, iclass 14, count 0 2006.202.00:37:52.78#ibcon#about to read 6, iclass 14, count 0 2006.202.00:37:52.78#ibcon#read 6, iclass 14, count 0 2006.202.00:37:52.78#ibcon#end of sib2, iclass 14, count 0 2006.202.00:37:52.78#ibcon#*mode == 0, iclass 14, count 0 2006.202.00:37:52.78#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.00:37:52.78#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.00:37:52.78#ibcon#*before write, iclass 14, count 0 2006.202.00:37:52.78#ibcon#enter sib2, iclass 14, count 0 2006.202.00:37:52.78#ibcon#flushed, iclass 14, count 0 2006.202.00:37:52.78#ibcon#about to write, iclass 14, count 0 2006.202.00:37:52.78#ibcon#wrote, iclass 14, count 0 2006.202.00:37:52.78#ibcon#about to read 3, iclass 14, count 0 2006.202.00:37:52.82#ibcon#read 3, iclass 14, count 0 2006.202.00:37:52.82#ibcon#about to read 4, iclass 14, count 0 2006.202.00:37:52.82#ibcon#read 4, iclass 14, count 0 2006.202.00:37:52.82#ibcon#about to read 5, iclass 14, count 0 2006.202.00:37:52.82#ibcon#read 5, iclass 14, count 0 2006.202.00:37:52.82#ibcon#about to read 6, iclass 14, count 0 2006.202.00:37:52.82#ibcon#read 6, iclass 14, count 0 2006.202.00:37:52.82#ibcon#end of sib2, iclass 14, count 0 2006.202.00:37:52.82#ibcon#*after write, iclass 14, count 0 2006.202.00:37:52.82#ibcon#*before return 0, iclass 14, count 0 2006.202.00:37:52.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:52.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:37:52.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.00:37:52.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.00:37:52.82$vck44/vb=3,4 2006.202.00:37:52.82#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.00:37:52.82#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.00:37:52.82#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:52.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:52.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:52.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:52.88#ibcon#enter wrdev, iclass 16, count 2 2006.202.00:37:52.88#ibcon#first serial, iclass 16, count 2 2006.202.00:37:52.88#ibcon#enter sib2, iclass 16, count 2 2006.202.00:37:52.88#ibcon#flushed, iclass 16, count 2 2006.202.00:37:52.88#ibcon#about to write, iclass 16, count 2 2006.202.00:37:52.88#ibcon#wrote, iclass 16, count 2 2006.202.00:37:52.88#ibcon#about to read 3, iclass 16, count 2 2006.202.00:37:52.90#ibcon#read 3, iclass 16, count 2 2006.202.00:37:52.90#ibcon#about to read 4, iclass 16, count 2 2006.202.00:37:52.90#ibcon#read 4, iclass 16, count 2 2006.202.00:37:52.90#ibcon#about to read 5, iclass 16, count 2 2006.202.00:37:52.90#ibcon#read 5, iclass 16, count 2 2006.202.00:37:52.90#ibcon#about to read 6, iclass 16, count 2 2006.202.00:37:52.90#ibcon#read 6, iclass 16, count 2 2006.202.00:37:52.90#ibcon#end of sib2, iclass 16, count 2 2006.202.00:37:52.90#ibcon#*mode == 0, iclass 16, count 2 2006.202.00:37:52.90#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.00:37:52.90#ibcon#[27=AT03-04\r\n] 2006.202.00:37:52.90#ibcon#*before write, iclass 16, count 2 2006.202.00:37:52.90#ibcon#enter sib2, iclass 16, count 2 2006.202.00:37:52.90#ibcon#flushed, iclass 16, count 2 2006.202.00:37:52.90#ibcon#about to write, iclass 16, count 2 2006.202.00:37:52.90#ibcon#wrote, iclass 16, count 2 2006.202.00:37:52.90#ibcon#about to read 3, iclass 16, count 2 2006.202.00:37:52.93#ibcon#read 3, iclass 16, count 2 2006.202.00:37:52.93#ibcon#about to read 4, iclass 16, count 2 2006.202.00:37:52.93#ibcon#read 4, iclass 16, count 2 2006.202.00:37:52.93#ibcon#about to read 5, iclass 16, count 2 2006.202.00:37:52.93#ibcon#read 5, iclass 16, count 2 2006.202.00:37:52.93#ibcon#about to read 6, iclass 16, count 2 2006.202.00:37:52.93#ibcon#read 6, iclass 16, count 2 2006.202.00:37:52.93#ibcon#end of sib2, iclass 16, count 2 2006.202.00:37:52.93#ibcon#*after write, iclass 16, count 2 2006.202.00:37:52.93#ibcon#*before return 0, iclass 16, count 2 2006.202.00:37:52.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:52.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:37:52.93#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.00:37:52.93#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:52.93#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:53.05#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:53.05#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:53.05#ibcon#enter wrdev, iclass 16, count 0 2006.202.00:37:53.05#ibcon#first serial, iclass 16, count 0 2006.202.00:37:53.05#ibcon#enter sib2, iclass 16, count 0 2006.202.00:37:53.05#ibcon#flushed, iclass 16, count 0 2006.202.00:37:53.05#ibcon#about to write, iclass 16, count 0 2006.202.00:37:53.05#ibcon#wrote, iclass 16, count 0 2006.202.00:37:53.05#ibcon#about to read 3, iclass 16, count 0 2006.202.00:37:53.07#ibcon#read 3, iclass 16, count 0 2006.202.00:37:53.07#ibcon#about to read 4, iclass 16, count 0 2006.202.00:37:53.07#ibcon#read 4, iclass 16, count 0 2006.202.00:37:53.07#ibcon#about to read 5, iclass 16, count 0 2006.202.00:37:53.07#ibcon#read 5, iclass 16, count 0 2006.202.00:37:53.07#ibcon#about to read 6, iclass 16, count 0 2006.202.00:37:53.07#ibcon#read 6, iclass 16, count 0 2006.202.00:37:53.07#ibcon#end of sib2, iclass 16, count 0 2006.202.00:37:53.07#ibcon#*mode == 0, iclass 16, count 0 2006.202.00:37:53.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.00:37:53.07#ibcon#[27=USB\r\n] 2006.202.00:37:53.07#ibcon#*before write, iclass 16, count 0 2006.202.00:37:53.07#ibcon#enter sib2, iclass 16, count 0 2006.202.00:37:53.07#ibcon#flushed, iclass 16, count 0 2006.202.00:37:53.07#ibcon#about to write, iclass 16, count 0 2006.202.00:37:53.07#ibcon#wrote, iclass 16, count 0 2006.202.00:37:53.07#ibcon#about to read 3, iclass 16, count 0 2006.202.00:37:53.10#ibcon#read 3, iclass 16, count 0 2006.202.00:37:53.10#ibcon#about to read 4, iclass 16, count 0 2006.202.00:37:53.10#ibcon#read 4, iclass 16, count 0 2006.202.00:37:53.10#ibcon#about to read 5, iclass 16, count 0 2006.202.00:37:53.10#ibcon#read 5, iclass 16, count 0 2006.202.00:37:53.10#ibcon#about to read 6, iclass 16, count 0 2006.202.00:37:53.10#ibcon#read 6, iclass 16, count 0 2006.202.00:37:53.10#ibcon#end of sib2, iclass 16, count 0 2006.202.00:37:53.10#ibcon#*after write, iclass 16, count 0 2006.202.00:37:53.10#ibcon#*before return 0, iclass 16, count 0 2006.202.00:37:53.10#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:53.10#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:37:53.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.00:37:53.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.00:37:53.10$vck44/vblo=4,679.99 2006.202.00:37:53.10#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.00:37:53.10#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.00:37:53.10#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:53.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:53.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:53.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:53.10#ibcon#enter wrdev, iclass 18, count 0 2006.202.00:37:53.10#ibcon#first serial, iclass 18, count 0 2006.202.00:37:53.10#ibcon#enter sib2, iclass 18, count 0 2006.202.00:37:53.10#ibcon#flushed, iclass 18, count 0 2006.202.00:37:53.10#ibcon#about to write, iclass 18, count 0 2006.202.00:37:53.10#ibcon#wrote, iclass 18, count 0 2006.202.00:37:53.10#ibcon#about to read 3, iclass 18, count 0 2006.202.00:37:53.12#ibcon#read 3, iclass 18, count 0 2006.202.00:37:53.12#ibcon#about to read 4, iclass 18, count 0 2006.202.00:37:53.12#ibcon#read 4, iclass 18, count 0 2006.202.00:37:53.12#ibcon#about to read 5, iclass 18, count 0 2006.202.00:37:53.12#ibcon#read 5, iclass 18, count 0 2006.202.00:37:53.12#ibcon#about to read 6, iclass 18, count 0 2006.202.00:37:53.12#ibcon#read 6, iclass 18, count 0 2006.202.00:37:53.12#ibcon#end of sib2, iclass 18, count 0 2006.202.00:37:53.12#ibcon#*mode == 0, iclass 18, count 0 2006.202.00:37:53.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.00:37:53.12#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.00:37:53.12#ibcon#*before write, iclass 18, count 0 2006.202.00:37:53.12#ibcon#enter sib2, iclass 18, count 0 2006.202.00:37:53.12#ibcon#flushed, iclass 18, count 0 2006.202.00:37:53.12#ibcon#about to write, iclass 18, count 0 2006.202.00:37:53.12#ibcon#wrote, iclass 18, count 0 2006.202.00:37:53.12#ibcon#about to read 3, iclass 18, count 0 2006.202.00:37:53.16#ibcon#read 3, iclass 18, count 0 2006.202.00:37:53.16#ibcon#about to read 4, iclass 18, count 0 2006.202.00:37:53.16#ibcon#read 4, iclass 18, count 0 2006.202.00:37:53.16#ibcon#about to read 5, iclass 18, count 0 2006.202.00:37:53.16#ibcon#read 5, iclass 18, count 0 2006.202.00:37:53.16#ibcon#about to read 6, iclass 18, count 0 2006.202.00:37:53.16#ibcon#read 6, iclass 18, count 0 2006.202.00:37:53.16#ibcon#end of sib2, iclass 18, count 0 2006.202.00:37:53.16#ibcon#*after write, iclass 18, count 0 2006.202.00:37:53.16#ibcon#*before return 0, iclass 18, count 0 2006.202.00:37:53.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:53.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:37:53.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.00:37:53.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.00:37:53.16$vck44/vb=4,5 2006.202.00:37:53.16#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.00:37:53.16#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.00:37:53.16#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:53.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:53.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:53.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:53.22#ibcon#enter wrdev, iclass 20, count 2 2006.202.00:37:53.22#ibcon#first serial, iclass 20, count 2 2006.202.00:37:53.22#ibcon#enter sib2, iclass 20, count 2 2006.202.00:37:53.22#ibcon#flushed, iclass 20, count 2 2006.202.00:37:53.22#ibcon#about to write, iclass 20, count 2 2006.202.00:37:53.22#ibcon#wrote, iclass 20, count 2 2006.202.00:37:53.22#ibcon#about to read 3, iclass 20, count 2 2006.202.00:37:53.24#ibcon#read 3, iclass 20, count 2 2006.202.00:37:53.24#ibcon#about to read 4, iclass 20, count 2 2006.202.00:37:53.24#ibcon#read 4, iclass 20, count 2 2006.202.00:37:53.24#ibcon#about to read 5, iclass 20, count 2 2006.202.00:37:53.24#ibcon#read 5, iclass 20, count 2 2006.202.00:37:53.24#ibcon#about to read 6, iclass 20, count 2 2006.202.00:37:53.24#ibcon#read 6, iclass 20, count 2 2006.202.00:37:53.24#ibcon#end of sib2, iclass 20, count 2 2006.202.00:37:53.24#ibcon#*mode == 0, iclass 20, count 2 2006.202.00:37:53.24#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.00:37:53.24#ibcon#[27=AT04-05\r\n] 2006.202.00:37:53.24#ibcon#*before write, iclass 20, count 2 2006.202.00:37:53.24#ibcon#enter sib2, iclass 20, count 2 2006.202.00:37:53.24#ibcon#flushed, iclass 20, count 2 2006.202.00:37:53.24#ibcon#about to write, iclass 20, count 2 2006.202.00:37:53.24#ibcon#wrote, iclass 20, count 2 2006.202.00:37:53.24#ibcon#about to read 3, iclass 20, count 2 2006.202.00:37:53.27#ibcon#read 3, iclass 20, count 2 2006.202.00:37:53.27#ibcon#about to read 4, iclass 20, count 2 2006.202.00:37:53.27#ibcon#read 4, iclass 20, count 2 2006.202.00:37:53.27#ibcon#about to read 5, iclass 20, count 2 2006.202.00:37:53.27#ibcon#read 5, iclass 20, count 2 2006.202.00:37:53.27#ibcon#about to read 6, iclass 20, count 2 2006.202.00:37:53.27#ibcon#read 6, iclass 20, count 2 2006.202.00:37:53.27#ibcon#end of sib2, iclass 20, count 2 2006.202.00:37:53.27#ibcon#*after write, iclass 20, count 2 2006.202.00:37:53.27#ibcon#*before return 0, iclass 20, count 2 2006.202.00:37:53.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:53.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:37:53.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.00:37:53.27#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:53.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:53.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:53.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:53.39#ibcon#enter wrdev, iclass 20, count 0 2006.202.00:37:53.39#ibcon#first serial, iclass 20, count 0 2006.202.00:37:53.39#ibcon#enter sib2, iclass 20, count 0 2006.202.00:37:53.39#ibcon#flushed, iclass 20, count 0 2006.202.00:37:53.39#ibcon#about to write, iclass 20, count 0 2006.202.00:37:53.39#ibcon#wrote, iclass 20, count 0 2006.202.00:37:53.39#ibcon#about to read 3, iclass 20, count 0 2006.202.00:37:53.41#ibcon#read 3, iclass 20, count 0 2006.202.00:37:53.41#ibcon#about to read 4, iclass 20, count 0 2006.202.00:37:53.41#ibcon#read 4, iclass 20, count 0 2006.202.00:37:53.41#ibcon#about to read 5, iclass 20, count 0 2006.202.00:37:53.41#ibcon#read 5, iclass 20, count 0 2006.202.00:37:53.41#ibcon#about to read 6, iclass 20, count 0 2006.202.00:37:53.41#ibcon#read 6, iclass 20, count 0 2006.202.00:37:53.41#ibcon#end of sib2, iclass 20, count 0 2006.202.00:37:53.41#ibcon#*mode == 0, iclass 20, count 0 2006.202.00:37:53.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.00:37:53.41#ibcon#[27=USB\r\n] 2006.202.00:37:53.41#ibcon#*before write, iclass 20, count 0 2006.202.00:37:53.41#ibcon#enter sib2, iclass 20, count 0 2006.202.00:37:53.41#ibcon#flushed, iclass 20, count 0 2006.202.00:37:53.41#ibcon#about to write, iclass 20, count 0 2006.202.00:37:53.41#ibcon#wrote, iclass 20, count 0 2006.202.00:37:53.41#ibcon#about to read 3, iclass 20, count 0 2006.202.00:37:53.44#ibcon#read 3, iclass 20, count 0 2006.202.00:37:53.44#ibcon#about to read 4, iclass 20, count 0 2006.202.00:37:53.44#ibcon#read 4, iclass 20, count 0 2006.202.00:37:53.44#ibcon#about to read 5, iclass 20, count 0 2006.202.00:37:53.44#ibcon#read 5, iclass 20, count 0 2006.202.00:37:53.44#ibcon#about to read 6, iclass 20, count 0 2006.202.00:37:53.44#ibcon#read 6, iclass 20, count 0 2006.202.00:37:53.44#ibcon#end of sib2, iclass 20, count 0 2006.202.00:37:53.44#ibcon#*after write, iclass 20, count 0 2006.202.00:37:53.44#ibcon#*before return 0, iclass 20, count 0 2006.202.00:37:53.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:53.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:37:53.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.00:37:53.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.00:37:53.44$vck44/vblo=5,709.99 2006.202.00:37:53.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.00:37:53.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.00:37:53.44#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:53.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:53.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:53.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:53.44#ibcon#enter wrdev, iclass 22, count 0 2006.202.00:37:53.44#ibcon#first serial, iclass 22, count 0 2006.202.00:37:53.44#ibcon#enter sib2, iclass 22, count 0 2006.202.00:37:53.44#ibcon#flushed, iclass 22, count 0 2006.202.00:37:53.44#ibcon#about to write, iclass 22, count 0 2006.202.00:37:53.44#ibcon#wrote, iclass 22, count 0 2006.202.00:37:53.44#ibcon#about to read 3, iclass 22, count 0 2006.202.00:37:53.46#ibcon#read 3, iclass 22, count 0 2006.202.00:37:53.46#ibcon#about to read 4, iclass 22, count 0 2006.202.00:37:53.46#ibcon#read 4, iclass 22, count 0 2006.202.00:37:53.46#ibcon#about to read 5, iclass 22, count 0 2006.202.00:37:53.46#ibcon#read 5, iclass 22, count 0 2006.202.00:37:53.46#ibcon#about to read 6, iclass 22, count 0 2006.202.00:37:53.46#ibcon#read 6, iclass 22, count 0 2006.202.00:37:53.46#ibcon#end of sib2, iclass 22, count 0 2006.202.00:37:53.46#ibcon#*mode == 0, iclass 22, count 0 2006.202.00:37:53.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.00:37:53.46#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.00:37:53.46#ibcon#*before write, iclass 22, count 0 2006.202.00:37:53.46#ibcon#enter sib2, iclass 22, count 0 2006.202.00:37:53.46#ibcon#flushed, iclass 22, count 0 2006.202.00:37:53.46#ibcon#about to write, iclass 22, count 0 2006.202.00:37:53.46#ibcon#wrote, iclass 22, count 0 2006.202.00:37:53.46#ibcon#about to read 3, iclass 22, count 0 2006.202.00:37:53.50#ibcon#read 3, iclass 22, count 0 2006.202.00:37:53.50#ibcon#about to read 4, iclass 22, count 0 2006.202.00:37:53.50#ibcon#read 4, iclass 22, count 0 2006.202.00:37:53.50#ibcon#about to read 5, iclass 22, count 0 2006.202.00:37:53.50#ibcon#read 5, iclass 22, count 0 2006.202.00:37:53.50#ibcon#about to read 6, iclass 22, count 0 2006.202.00:37:53.50#ibcon#read 6, iclass 22, count 0 2006.202.00:37:53.50#ibcon#end of sib2, iclass 22, count 0 2006.202.00:37:53.50#ibcon#*after write, iclass 22, count 0 2006.202.00:37:53.50#ibcon#*before return 0, iclass 22, count 0 2006.202.00:37:53.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:53.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:37:53.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.00:37:53.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.00:37:53.50$vck44/vb=5,4 2006.202.00:37:53.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.00:37:53.50#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.00:37:53.50#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:53.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:53.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:53.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:53.56#ibcon#enter wrdev, iclass 24, count 2 2006.202.00:37:53.56#ibcon#first serial, iclass 24, count 2 2006.202.00:37:53.56#ibcon#enter sib2, iclass 24, count 2 2006.202.00:37:53.56#ibcon#flushed, iclass 24, count 2 2006.202.00:37:53.56#ibcon#about to write, iclass 24, count 2 2006.202.00:37:53.56#ibcon#wrote, iclass 24, count 2 2006.202.00:37:53.56#ibcon#about to read 3, iclass 24, count 2 2006.202.00:37:53.58#ibcon#read 3, iclass 24, count 2 2006.202.00:37:53.58#ibcon#about to read 4, iclass 24, count 2 2006.202.00:37:53.58#ibcon#read 4, iclass 24, count 2 2006.202.00:37:53.58#ibcon#about to read 5, iclass 24, count 2 2006.202.00:37:53.58#ibcon#read 5, iclass 24, count 2 2006.202.00:37:53.58#ibcon#about to read 6, iclass 24, count 2 2006.202.00:37:53.58#ibcon#read 6, iclass 24, count 2 2006.202.00:37:53.58#ibcon#end of sib2, iclass 24, count 2 2006.202.00:37:53.58#ibcon#*mode == 0, iclass 24, count 2 2006.202.00:37:53.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.00:37:53.58#ibcon#[27=AT05-04\r\n] 2006.202.00:37:53.58#ibcon#*before write, iclass 24, count 2 2006.202.00:37:53.58#ibcon#enter sib2, iclass 24, count 2 2006.202.00:37:53.58#ibcon#flushed, iclass 24, count 2 2006.202.00:37:53.58#ibcon#about to write, iclass 24, count 2 2006.202.00:37:53.58#ibcon#wrote, iclass 24, count 2 2006.202.00:37:53.58#ibcon#about to read 3, iclass 24, count 2 2006.202.00:37:53.61#ibcon#read 3, iclass 24, count 2 2006.202.00:37:53.69#ibcon#about to read 4, iclass 24, count 2 2006.202.00:37:53.69#ibcon#read 4, iclass 24, count 2 2006.202.00:37:53.69#ibcon#about to read 5, iclass 24, count 2 2006.202.00:37:53.70#ibcon#read 5, iclass 24, count 2 2006.202.00:37:53.70#ibcon#about to read 6, iclass 24, count 2 2006.202.00:37:53.70#ibcon#read 6, iclass 24, count 2 2006.202.00:37:53.70#ibcon#end of sib2, iclass 24, count 2 2006.202.00:37:53.70#ibcon#*after write, iclass 24, count 2 2006.202.00:37:53.70#ibcon#*before return 0, iclass 24, count 2 2006.202.00:37:53.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:53.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:37:53.70#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.00:37:53.70#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:53.70#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:53.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:53.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:53.82#ibcon#enter wrdev, iclass 24, count 0 2006.202.00:37:53.82#ibcon#first serial, iclass 24, count 0 2006.202.00:37:53.82#ibcon#enter sib2, iclass 24, count 0 2006.202.00:37:53.82#ibcon#flushed, iclass 24, count 0 2006.202.00:37:53.82#ibcon#about to write, iclass 24, count 0 2006.202.00:37:53.82#ibcon#wrote, iclass 24, count 0 2006.202.00:37:53.82#ibcon#about to read 3, iclass 24, count 0 2006.202.00:37:53.84#ibcon#read 3, iclass 24, count 0 2006.202.00:37:53.84#ibcon#about to read 4, iclass 24, count 0 2006.202.00:37:53.84#ibcon#read 4, iclass 24, count 0 2006.202.00:37:53.84#ibcon#about to read 5, iclass 24, count 0 2006.202.00:37:53.84#ibcon#read 5, iclass 24, count 0 2006.202.00:37:53.84#ibcon#about to read 6, iclass 24, count 0 2006.202.00:37:53.84#ibcon#read 6, iclass 24, count 0 2006.202.00:37:53.84#ibcon#end of sib2, iclass 24, count 0 2006.202.00:37:53.84#ibcon#*mode == 0, iclass 24, count 0 2006.202.00:37:53.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.00:37:53.84#ibcon#[27=USB\r\n] 2006.202.00:37:53.84#ibcon#*before write, iclass 24, count 0 2006.202.00:37:53.84#ibcon#enter sib2, iclass 24, count 0 2006.202.00:37:53.84#ibcon#flushed, iclass 24, count 0 2006.202.00:37:53.84#ibcon#about to write, iclass 24, count 0 2006.202.00:37:53.84#ibcon#wrote, iclass 24, count 0 2006.202.00:37:53.84#ibcon#about to read 3, iclass 24, count 0 2006.202.00:37:53.87#ibcon#read 3, iclass 24, count 0 2006.202.00:37:53.87#ibcon#about to read 4, iclass 24, count 0 2006.202.00:37:53.87#ibcon#read 4, iclass 24, count 0 2006.202.00:37:53.87#ibcon#about to read 5, iclass 24, count 0 2006.202.00:37:53.87#ibcon#read 5, iclass 24, count 0 2006.202.00:37:53.87#ibcon#about to read 6, iclass 24, count 0 2006.202.00:37:53.87#ibcon#read 6, iclass 24, count 0 2006.202.00:37:53.87#ibcon#end of sib2, iclass 24, count 0 2006.202.00:37:53.87#ibcon#*after write, iclass 24, count 0 2006.202.00:37:53.87#ibcon#*before return 0, iclass 24, count 0 2006.202.00:37:53.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:53.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:37:53.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.00:37:53.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.00:37:53.87$vck44/vblo=6,719.99 2006.202.00:37:53.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.00:37:53.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.00:37:53.87#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:53.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:53.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:53.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:53.87#ibcon#enter wrdev, iclass 26, count 0 2006.202.00:37:53.87#ibcon#first serial, iclass 26, count 0 2006.202.00:37:53.87#ibcon#enter sib2, iclass 26, count 0 2006.202.00:37:53.87#ibcon#flushed, iclass 26, count 0 2006.202.00:37:53.87#ibcon#about to write, iclass 26, count 0 2006.202.00:37:53.87#ibcon#wrote, iclass 26, count 0 2006.202.00:37:53.87#ibcon#about to read 3, iclass 26, count 0 2006.202.00:37:53.89#ibcon#read 3, iclass 26, count 0 2006.202.00:37:53.89#ibcon#about to read 4, iclass 26, count 0 2006.202.00:37:53.89#ibcon#read 4, iclass 26, count 0 2006.202.00:37:53.89#ibcon#about to read 5, iclass 26, count 0 2006.202.00:37:53.89#ibcon#read 5, iclass 26, count 0 2006.202.00:37:53.89#ibcon#about to read 6, iclass 26, count 0 2006.202.00:37:53.89#ibcon#read 6, iclass 26, count 0 2006.202.00:37:53.89#ibcon#end of sib2, iclass 26, count 0 2006.202.00:37:53.89#ibcon#*mode == 0, iclass 26, count 0 2006.202.00:37:53.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.00:37:53.89#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.00:37:53.89#ibcon#*before write, iclass 26, count 0 2006.202.00:37:53.89#ibcon#enter sib2, iclass 26, count 0 2006.202.00:37:53.89#ibcon#flushed, iclass 26, count 0 2006.202.00:37:53.89#ibcon#about to write, iclass 26, count 0 2006.202.00:37:53.89#ibcon#wrote, iclass 26, count 0 2006.202.00:37:53.89#ibcon#about to read 3, iclass 26, count 0 2006.202.00:37:53.93#ibcon#read 3, iclass 26, count 0 2006.202.00:37:53.93#ibcon#about to read 4, iclass 26, count 0 2006.202.00:37:53.93#ibcon#read 4, iclass 26, count 0 2006.202.00:37:53.93#ibcon#about to read 5, iclass 26, count 0 2006.202.00:37:53.93#ibcon#read 5, iclass 26, count 0 2006.202.00:37:53.93#ibcon#about to read 6, iclass 26, count 0 2006.202.00:37:53.93#ibcon#read 6, iclass 26, count 0 2006.202.00:37:53.93#ibcon#end of sib2, iclass 26, count 0 2006.202.00:37:53.93#ibcon#*after write, iclass 26, count 0 2006.202.00:37:53.93#ibcon#*before return 0, iclass 26, count 0 2006.202.00:37:53.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:53.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:37:53.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.00:37:53.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.00:37:53.93$vck44/vb=6,4 2006.202.00:37:53.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.00:37:53.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.00:37:53.93#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:53.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:53.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:53.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:53.99#ibcon#enter wrdev, iclass 28, count 2 2006.202.00:37:53.99#ibcon#first serial, iclass 28, count 2 2006.202.00:37:53.99#ibcon#enter sib2, iclass 28, count 2 2006.202.00:37:53.99#ibcon#flushed, iclass 28, count 2 2006.202.00:37:53.99#ibcon#about to write, iclass 28, count 2 2006.202.00:37:53.99#ibcon#wrote, iclass 28, count 2 2006.202.00:37:53.99#ibcon#about to read 3, iclass 28, count 2 2006.202.00:37:54.01#ibcon#read 3, iclass 28, count 2 2006.202.00:37:54.01#ibcon#about to read 4, iclass 28, count 2 2006.202.00:37:54.01#ibcon#read 4, iclass 28, count 2 2006.202.00:37:54.01#ibcon#about to read 5, iclass 28, count 2 2006.202.00:37:54.01#ibcon#read 5, iclass 28, count 2 2006.202.00:37:54.01#ibcon#about to read 6, iclass 28, count 2 2006.202.00:37:54.01#ibcon#read 6, iclass 28, count 2 2006.202.00:37:54.01#ibcon#end of sib2, iclass 28, count 2 2006.202.00:37:54.01#ibcon#*mode == 0, iclass 28, count 2 2006.202.00:37:54.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.00:37:54.01#ibcon#[27=AT06-04\r\n] 2006.202.00:37:54.01#ibcon#*before write, iclass 28, count 2 2006.202.00:37:54.01#ibcon#enter sib2, iclass 28, count 2 2006.202.00:37:54.01#ibcon#flushed, iclass 28, count 2 2006.202.00:37:54.01#ibcon#about to write, iclass 28, count 2 2006.202.00:37:54.01#ibcon#wrote, iclass 28, count 2 2006.202.00:37:54.01#ibcon#about to read 3, iclass 28, count 2 2006.202.00:37:54.04#ibcon#read 3, iclass 28, count 2 2006.202.00:37:54.04#ibcon#about to read 4, iclass 28, count 2 2006.202.00:37:54.04#ibcon#read 4, iclass 28, count 2 2006.202.00:37:54.04#ibcon#about to read 5, iclass 28, count 2 2006.202.00:37:54.04#ibcon#read 5, iclass 28, count 2 2006.202.00:37:54.04#ibcon#about to read 6, iclass 28, count 2 2006.202.00:37:54.04#ibcon#read 6, iclass 28, count 2 2006.202.00:37:54.04#ibcon#end of sib2, iclass 28, count 2 2006.202.00:37:54.04#ibcon#*after write, iclass 28, count 2 2006.202.00:37:54.04#ibcon#*before return 0, iclass 28, count 2 2006.202.00:37:54.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:54.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:37:54.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.00:37:54.04#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:54.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:54.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:54.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:54.16#ibcon#enter wrdev, iclass 28, count 0 2006.202.00:37:54.16#ibcon#first serial, iclass 28, count 0 2006.202.00:37:54.16#ibcon#enter sib2, iclass 28, count 0 2006.202.00:37:54.16#ibcon#flushed, iclass 28, count 0 2006.202.00:37:54.16#ibcon#about to write, iclass 28, count 0 2006.202.00:37:54.16#ibcon#wrote, iclass 28, count 0 2006.202.00:37:54.16#ibcon#about to read 3, iclass 28, count 0 2006.202.00:37:54.18#ibcon#read 3, iclass 28, count 0 2006.202.00:37:54.18#ibcon#about to read 4, iclass 28, count 0 2006.202.00:37:54.18#ibcon#read 4, iclass 28, count 0 2006.202.00:37:54.18#ibcon#about to read 5, iclass 28, count 0 2006.202.00:37:54.18#ibcon#read 5, iclass 28, count 0 2006.202.00:37:54.18#ibcon#about to read 6, iclass 28, count 0 2006.202.00:37:54.18#ibcon#read 6, iclass 28, count 0 2006.202.00:37:54.18#ibcon#end of sib2, iclass 28, count 0 2006.202.00:37:54.18#ibcon#*mode == 0, iclass 28, count 0 2006.202.00:37:54.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.00:37:54.18#ibcon#[27=USB\r\n] 2006.202.00:37:54.18#ibcon#*before write, iclass 28, count 0 2006.202.00:37:54.18#ibcon#enter sib2, iclass 28, count 0 2006.202.00:37:54.18#ibcon#flushed, iclass 28, count 0 2006.202.00:37:54.18#ibcon#about to write, iclass 28, count 0 2006.202.00:37:54.18#ibcon#wrote, iclass 28, count 0 2006.202.00:37:54.18#ibcon#about to read 3, iclass 28, count 0 2006.202.00:37:54.21#ibcon#read 3, iclass 28, count 0 2006.202.00:37:54.21#ibcon#about to read 4, iclass 28, count 0 2006.202.00:37:54.21#ibcon#read 4, iclass 28, count 0 2006.202.00:37:54.21#ibcon#about to read 5, iclass 28, count 0 2006.202.00:37:54.21#ibcon#read 5, iclass 28, count 0 2006.202.00:37:54.21#ibcon#about to read 6, iclass 28, count 0 2006.202.00:37:54.21#ibcon#read 6, iclass 28, count 0 2006.202.00:37:54.21#ibcon#end of sib2, iclass 28, count 0 2006.202.00:37:54.21#ibcon#*after write, iclass 28, count 0 2006.202.00:37:54.21#ibcon#*before return 0, iclass 28, count 0 2006.202.00:37:54.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:54.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:37:54.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.00:37:54.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.00:37:54.21$vck44/vblo=7,734.99 2006.202.00:37:54.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.00:37:54.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.00:37:54.21#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:54.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:54.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:54.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:54.21#ibcon#enter wrdev, iclass 30, count 0 2006.202.00:37:54.21#ibcon#first serial, iclass 30, count 0 2006.202.00:37:54.21#ibcon#enter sib2, iclass 30, count 0 2006.202.00:37:54.21#ibcon#flushed, iclass 30, count 0 2006.202.00:37:54.21#ibcon#about to write, iclass 30, count 0 2006.202.00:37:54.21#ibcon#wrote, iclass 30, count 0 2006.202.00:37:54.21#ibcon#about to read 3, iclass 30, count 0 2006.202.00:37:54.23#ibcon#read 3, iclass 30, count 0 2006.202.00:37:54.23#ibcon#about to read 4, iclass 30, count 0 2006.202.00:37:54.23#ibcon#read 4, iclass 30, count 0 2006.202.00:37:54.23#ibcon#about to read 5, iclass 30, count 0 2006.202.00:37:54.23#ibcon#read 5, iclass 30, count 0 2006.202.00:37:54.23#ibcon#about to read 6, iclass 30, count 0 2006.202.00:37:54.23#ibcon#read 6, iclass 30, count 0 2006.202.00:37:54.23#ibcon#end of sib2, iclass 30, count 0 2006.202.00:37:54.23#ibcon#*mode == 0, iclass 30, count 0 2006.202.00:37:54.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.00:37:54.23#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.00:37:54.23#ibcon#*before write, iclass 30, count 0 2006.202.00:37:54.23#ibcon#enter sib2, iclass 30, count 0 2006.202.00:37:54.23#ibcon#flushed, iclass 30, count 0 2006.202.00:37:54.23#ibcon#about to write, iclass 30, count 0 2006.202.00:37:54.23#ibcon#wrote, iclass 30, count 0 2006.202.00:37:54.23#ibcon#about to read 3, iclass 30, count 0 2006.202.00:37:54.27#ibcon#read 3, iclass 30, count 0 2006.202.00:37:54.27#ibcon#about to read 4, iclass 30, count 0 2006.202.00:37:54.27#ibcon#read 4, iclass 30, count 0 2006.202.00:37:54.27#ibcon#about to read 5, iclass 30, count 0 2006.202.00:37:54.27#ibcon#read 5, iclass 30, count 0 2006.202.00:37:54.27#ibcon#about to read 6, iclass 30, count 0 2006.202.00:37:54.27#ibcon#read 6, iclass 30, count 0 2006.202.00:37:54.27#ibcon#end of sib2, iclass 30, count 0 2006.202.00:37:54.27#ibcon#*after write, iclass 30, count 0 2006.202.00:37:54.27#ibcon#*before return 0, iclass 30, count 0 2006.202.00:37:54.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:54.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:37:54.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.00:37:54.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.00:37:54.27$vck44/vb=7,4 2006.202.00:37:54.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.00:37:54.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.00:37:54.27#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:54.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:54.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:54.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:54.33#ibcon#enter wrdev, iclass 32, count 2 2006.202.00:37:54.33#ibcon#first serial, iclass 32, count 2 2006.202.00:37:54.33#ibcon#enter sib2, iclass 32, count 2 2006.202.00:37:54.33#ibcon#flushed, iclass 32, count 2 2006.202.00:37:54.33#ibcon#about to write, iclass 32, count 2 2006.202.00:37:54.33#ibcon#wrote, iclass 32, count 2 2006.202.00:37:54.33#ibcon#about to read 3, iclass 32, count 2 2006.202.00:37:54.35#ibcon#read 3, iclass 32, count 2 2006.202.00:37:54.35#ibcon#about to read 4, iclass 32, count 2 2006.202.00:37:54.35#ibcon#read 4, iclass 32, count 2 2006.202.00:37:54.35#ibcon#about to read 5, iclass 32, count 2 2006.202.00:37:54.35#ibcon#read 5, iclass 32, count 2 2006.202.00:37:54.35#ibcon#about to read 6, iclass 32, count 2 2006.202.00:37:54.35#ibcon#read 6, iclass 32, count 2 2006.202.00:37:54.35#ibcon#end of sib2, iclass 32, count 2 2006.202.00:37:54.35#ibcon#*mode == 0, iclass 32, count 2 2006.202.00:37:54.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.00:37:54.35#ibcon#[27=AT07-04\r\n] 2006.202.00:37:54.35#ibcon#*before write, iclass 32, count 2 2006.202.00:37:54.35#ibcon#enter sib2, iclass 32, count 2 2006.202.00:37:54.35#ibcon#flushed, iclass 32, count 2 2006.202.00:37:54.35#ibcon#about to write, iclass 32, count 2 2006.202.00:37:54.35#ibcon#wrote, iclass 32, count 2 2006.202.00:37:54.35#ibcon#about to read 3, iclass 32, count 2 2006.202.00:37:54.38#ibcon#read 3, iclass 32, count 2 2006.202.00:37:54.38#ibcon#about to read 4, iclass 32, count 2 2006.202.00:37:54.38#ibcon#read 4, iclass 32, count 2 2006.202.00:37:54.38#ibcon#about to read 5, iclass 32, count 2 2006.202.00:37:54.38#ibcon#read 5, iclass 32, count 2 2006.202.00:37:54.38#ibcon#about to read 6, iclass 32, count 2 2006.202.00:37:54.38#ibcon#read 6, iclass 32, count 2 2006.202.00:37:54.38#ibcon#end of sib2, iclass 32, count 2 2006.202.00:37:54.38#ibcon#*after write, iclass 32, count 2 2006.202.00:37:54.38#ibcon#*before return 0, iclass 32, count 2 2006.202.00:37:54.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:54.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:37:54.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.00:37:54.38#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:54.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:54.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:54.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:54.50#ibcon#enter wrdev, iclass 32, count 0 2006.202.00:37:54.50#ibcon#first serial, iclass 32, count 0 2006.202.00:37:54.50#ibcon#enter sib2, iclass 32, count 0 2006.202.00:37:54.50#ibcon#flushed, iclass 32, count 0 2006.202.00:37:54.50#ibcon#about to write, iclass 32, count 0 2006.202.00:37:54.50#ibcon#wrote, iclass 32, count 0 2006.202.00:37:54.50#ibcon#about to read 3, iclass 32, count 0 2006.202.00:37:54.52#ibcon#read 3, iclass 32, count 0 2006.202.00:37:54.52#ibcon#about to read 4, iclass 32, count 0 2006.202.00:37:54.52#ibcon#read 4, iclass 32, count 0 2006.202.00:37:54.52#ibcon#about to read 5, iclass 32, count 0 2006.202.00:37:54.52#ibcon#read 5, iclass 32, count 0 2006.202.00:37:54.52#ibcon#about to read 6, iclass 32, count 0 2006.202.00:37:54.52#ibcon#read 6, iclass 32, count 0 2006.202.00:37:54.52#ibcon#end of sib2, iclass 32, count 0 2006.202.00:37:54.52#ibcon#*mode == 0, iclass 32, count 0 2006.202.00:37:54.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.00:37:54.52#ibcon#[27=USB\r\n] 2006.202.00:37:54.52#ibcon#*before write, iclass 32, count 0 2006.202.00:37:54.52#ibcon#enter sib2, iclass 32, count 0 2006.202.00:37:54.52#ibcon#flushed, iclass 32, count 0 2006.202.00:37:54.52#ibcon#about to write, iclass 32, count 0 2006.202.00:37:54.52#ibcon#wrote, iclass 32, count 0 2006.202.00:37:54.52#ibcon#about to read 3, iclass 32, count 0 2006.202.00:37:54.55#ibcon#read 3, iclass 32, count 0 2006.202.00:37:54.55#ibcon#about to read 4, iclass 32, count 0 2006.202.00:37:54.55#ibcon#read 4, iclass 32, count 0 2006.202.00:37:54.55#ibcon#about to read 5, iclass 32, count 0 2006.202.00:37:54.55#ibcon#read 5, iclass 32, count 0 2006.202.00:37:54.55#ibcon#about to read 6, iclass 32, count 0 2006.202.00:37:54.55#ibcon#read 6, iclass 32, count 0 2006.202.00:37:54.55#ibcon#end of sib2, iclass 32, count 0 2006.202.00:37:54.55#ibcon#*after write, iclass 32, count 0 2006.202.00:37:54.55#ibcon#*before return 0, iclass 32, count 0 2006.202.00:37:54.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:54.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:37:54.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.00:37:54.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.00:37:54.55$vck44/vblo=8,744.99 2006.202.00:37:54.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.202.00:37:54.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.202.00:37:54.55#ibcon#ireg 17 cls_cnt 0 2006.202.00:37:54.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:37:54.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:37:54.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:37:54.55#ibcon#enter wrdev, iclass 35, count 0 2006.202.00:37:54.55#ibcon#first serial, iclass 35, count 0 2006.202.00:37:54.55#ibcon#enter sib2, iclass 35, count 0 2006.202.00:37:54.55#ibcon#flushed, iclass 35, count 0 2006.202.00:37:54.55#ibcon#about to write, iclass 35, count 0 2006.202.00:37:54.55#ibcon#wrote, iclass 35, count 0 2006.202.00:37:54.55#ibcon#about to read 3, iclass 35, count 0 2006.202.00:37:54.57#abcon#<5=/03 2.3 4.4 20.421001001.4\r\n> 2006.202.00:37:54.57#ibcon#read 3, iclass 35, count 0 2006.202.00:37:54.57#ibcon#about to read 4, iclass 35, count 0 2006.202.00:37:54.57#ibcon#read 4, iclass 35, count 0 2006.202.00:37:54.57#ibcon#about to read 5, iclass 35, count 0 2006.202.00:37:54.57#ibcon#read 5, iclass 35, count 0 2006.202.00:37:54.57#ibcon#about to read 6, iclass 35, count 0 2006.202.00:37:54.57#ibcon#read 6, iclass 35, count 0 2006.202.00:37:54.57#ibcon#end of sib2, iclass 35, count 0 2006.202.00:37:54.57#ibcon#*mode == 0, iclass 35, count 0 2006.202.00:37:54.57#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.00:37:54.57#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.00:37:54.57#ibcon#*before write, iclass 35, count 0 2006.202.00:37:54.57#ibcon#enter sib2, iclass 35, count 0 2006.202.00:37:54.57#ibcon#flushed, iclass 35, count 0 2006.202.00:37:54.57#ibcon#about to write, iclass 35, count 0 2006.202.00:37:54.57#ibcon#wrote, iclass 35, count 0 2006.202.00:37:54.57#ibcon#about to read 3, iclass 35, count 0 2006.202.00:37:54.59#abcon#{5=INTERFACE CLEAR} 2006.202.00:37:54.61#ibcon#read 3, iclass 35, count 0 2006.202.00:37:54.61#ibcon#about to read 4, iclass 35, count 0 2006.202.00:37:54.61#ibcon#read 4, iclass 35, count 0 2006.202.00:37:54.61#ibcon#about to read 5, iclass 35, count 0 2006.202.00:37:54.61#ibcon#read 5, iclass 35, count 0 2006.202.00:37:54.61#ibcon#about to read 6, iclass 35, count 0 2006.202.00:37:54.61#ibcon#read 6, iclass 35, count 0 2006.202.00:37:54.61#ibcon#end of sib2, iclass 35, count 0 2006.202.00:37:54.61#ibcon#*after write, iclass 35, count 0 2006.202.00:37:54.61#ibcon#*before return 0, iclass 35, count 0 2006.202.00:37:54.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:37:54.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:37:54.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.00:37:54.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.00:37:54.61$vck44/vb=8,4 2006.202.00:37:54.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.202.00:37:54.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.202.00:37:54.61#ibcon#ireg 11 cls_cnt 2 2006.202.00:37:54.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:37:54.65#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:37:54.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:37:54.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:37:54.67#ibcon#enter wrdev, iclass 39, count 2 2006.202.00:37:54.67#ibcon#first serial, iclass 39, count 2 2006.202.00:37:54.67#ibcon#enter sib2, iclass 39, count 2 2006.202.00:37:54.67#ibcon#flushed, iclass 39, count 2 2006.202.00:37:54.67#ibcon#about to write, iclass 39, count 2 2006.202.00:37:54.67#ibcon#wrote, iclass 39, count 2 2006.202.00:37:54.67#ibcon#about to read 3, iclass 39, count 2 2006.202.00:37:54.69#ibcon#read 3, iclass 39, count 2 2006.202.00:37:54.69#ibcon#about to read 4, iclass 39, count 2 2006.202.00:37:54.69#ibcon#read 4, iclass 39, count 2 2006.202.00:37:54.69#ibcon#about to read 5, iclass 39, count 2 2006.202.00:37:54.69#ibcon#read 5, iclass 39, count 2 2006.202.00:37:54.69#ibcon#about to read 6, iclass 39, count 2 2006.202.00:37:54.69#ibcon#read 6, iclass 39, count 2 2006.202.00:37:54.69#ibcon#end of sib2, iclass 39, count 2 2006.202.00:37:54.69#ibcon#*mode == 0, iclass 39, count 2 2006.202.00:37:54.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.202.00:37:54.69#ibcon#[27=AT08-04\r\n] 2006.202.00:37:54.69#ibcon#*before write, iclass 39, count 2 2006.202.00:37:54.69#ibcon#enter sib2, iclass 39, count 2 2006.202.00:37:54.69#ibcon#flushed, iclass 39, count 2 2006.202.00:37:54.77#ibcon#about to write, iclass 39, count 2 2006.202.00:37:54.77#ibcon#wrote, iclass 39, count 2 2006.202.00:37:54.77#ibcon#about to read 3, iclass 39, count 2 2006.202.00:37:54.80#ibcon#read 3, iclass 39, count 2 2006.202.00:37:54.80#ibcon#about to read 4, iclass 39, count 2 2006.202.00:37:54.80#ibcon#read 4, iclass 39, count 2 2006.202.00:37:54.80#ibcon#about to read 5, iclass 39, count 2 2006.202.00:37:54.80#ibcon#read 5, iclass 39, count 2 2006.202.00:37:54.80#ibcon#about to read 6, iclass 39, count 2 2006.202.00:37:54.80#ibcon#read 6, iclass 39, count 2 2006.202.00:37:54.80#ibcon#end of sib2, iclass 39, count 2 2006.202.00:37:54.80#ibcon#*after write, iclass 39, count 2 2006.202.00:37:54.80#ibcon#*before return 0, iclass 39, count 2 2006.202.00:37:54.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:37:54.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.202.00:37:54.80#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.202.00:37:54.80#ibcon#ireg 7 cls_cnt 0 2006.202.00:37:54.80#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:37:54.92#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:37:54.92#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:37:54.92#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:37:54.92#ibcon#first serial, iclass 39, count 0 2006.202.00:37:54.92#ibcon#enter sib2, iclass 39, count 0 2006.202.00:37:54.92#ibcon#flushed, iclass 39, count 0 2006.202.00:37:54.92#ibcon#about to write, iclass 39, count 0 2006.202.00:37:54.92#ibcon#wrote, iclass 39, count 0 2006.202.00:37:54.92#ibcon#about to read 3, iclass 39, count 0 2006.202.00:37:54.94#ibcon#read 3, iclass 39, count 0 2006.202.00:37:54.94#ibcon#about to read 4, iclass 39, count 0 2006.202.00:37:54.94#ibcon#read 4, iclass 39, count 0 2006.202.00:37:54.94#ibcon#about to read 5, iclass 39, count 0 2006.202.00:37:54.94#ibcon#read 5, iclass 39, count 0 2006.202.00:37:54.94#ibcon#about to read 6, iclass 39, count 0 2006.202.00:37:54.94#ibcon#read 6, iclass 39, count 0 2006.202.00:37:54.94#ibcon#end of sib2, iclass 39, count 0 2006.202.00:37:54.94#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:37:54.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:37:54.94#ibcon#[27=USB\r\n] 2006.202.00:37:54.94#ibcon#*before write, iclass 39, count 0 2006.202.00:37:54.94#ibcon#enter sib2, iclass 39, count 0 2006.202.00:37:54.94#ibcon#flushed, iclass 39, count 0 2006.202.00:37:54.94#ibcon#about to write, iclass 39, count 0 2006.202.00:37:54.94#ibcon#wrote, iclass 39, count 0 2006.202.00:37:54.94#ibcon#about to read 3, iclass 39, count 0 2006.202.00:37:54.97#ibcon#read 3, iclass 39, count 0 2006.202.00:37:54.97#ibcon#about to read 4, iclass 39, count 0 2006.202.00:37:54.97#ibcon#read 4, iclass 39, count 0 2006.202.00:37:54.97#ibcon#about to read 5, iclass 39, count 0 2006.202.00:37:54.97#ibcon#read 5, iclass 39, count 0 2006.202.00:37:54.97#ibcon#about to read 6, iclass 39, count 0 2006.202.00:37:54.97#ibcon#read 6, iclass 39, count 0 2006.202.00:37:54.97#ibcon#end of sib2, iclass 39, count 0 2006.202.00:37:54.97#ibcon#*after write, iclass 39, count 0 2006.202.00:37:54.97#ibcon#*before return 0, iclass 39, count 0 2006.202.00:37:54.97#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:37:54.97#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.202.00:37:54.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:37:54.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:37:54.97$vck44/vabw=wide 2006.202.00:37:54.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.00:37:54.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.00:37:54.97#ibcon#ireg 8 cls_cnt 0 2006.202.00:37:54.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:54.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:54.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:54.97#ibcon#enter wrdev, iclass 4, count 0 2006.202.00:37:54.97#ibcon#first serial, iclass 4, count 0 2006.202.00:37:54.97#ibcon#enter sib2, iclass 4, count 0 2006.202.00:37:54.97#ibcon#flushed, iclass 4, count 0 2006.202.00:37:54.97#ibcon#about to write, iclass 4, count 0 2006.202.00:37:54.97#ibcon#wrote, iclass 4, count 0 2006.202.00:37:54.97#ibcon#about to read 3, iclass 4, count 0 2006.202.00:37:54.99#ibcon#read 3, iclass 4, count 0 2006.202.00:37:54.99#ibcon#about to read 4, iclass 4, count 0 2006.202.00:37:54.99#ibcon#read 4, iclass 4, count 0 2006.202.00:37:54.99#ibcon#about to read 5, iclass 4, count 0 2006.202.00:37:54.99#ibcon#read 5, iclass 4, count 0 2006.202.00:37:54.99#ibcon#about to read 6, iclass 4, count 0 2006.202.00:37:54.99#ibcon#read 6, iclass 4, count 0 2006.202.00:37:54.99#ibcon#end of sib2, iclass 4, count 0 2006.202.00:37:54.99#ibcon#*mode == 0, iclass 4, count 0 2006.202.00:37:54.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.00:37:54.99#ibcon#[25=BW32\r\n] 2006.202.00:37:54.99#ibcon#*before write, iclass 4, count 0 2006.202.00:37:54.99#ibcon#enter sib2, iclass 4, count 0 2006.202.00:37:54.99#ibcon#flushed, iclass 4, count 0 2006.202.00:37:54.99#ibcon#about to write, iclass 4, count 0 2006.202.00:37:54.99#ibcon#wrote, iclass 4, count 0 2006.202.00:37:54.99#ibcon#about to read 3, iclass 4, count 0 2006.202.00:37:55.02#ibcon#read 3, iclass 4, count 0 2006.202.00:37:55.02#ibcon#about to read 4, iclass 4, count 0 2006.202.00:37:55.02#ibcon#read 4, iclass 4, count 0 2006.202.00:37:55.02#ibcon#about to read 5, iclass 4, count 0 2006.202.00:37:55.02#ibcon#read 5, iclass 4, count 0 2006.202.00:37:55.02#ibcon#about to read 6, iclass 4, count 0 2006.202.00:37:55.02#ibcon#read 6, iclass 4, count 0 2006.202.00:37:55.02#ibcon#end of sib2, iclass 4, count 0 2006.202.00:37:55.02#ibcon#*after write, iclass 4, count 0 2006.202.00:37:55.02#ibcon#*before return 0, iclass 4, count 0 2006.202.00:37:55.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:55.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:37:55.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.00:37:55.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.00:37:55.02$vck44/vbbw=wide 2006.202.00:37:55.02#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.202.00:37:55.02#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.202.00:37:55.02#ibcon#ireg 8 cls_cnt 0 2006.202.00:37:55.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:37:55.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:37:55.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:37:55.09#ibcon#enter wrdev, iclass 6, count 0 2006.202.00:37:55.09#ibcon#first serial, iclass 6, count 0 2006.202.00:37:55.09#ibcon#enter sib2, iclass 6, count 0 2006.202.00:37:55.09#ibcon#flushed, iclass 6, count 0 2006.202.00:37:55.09#ibcon#about to write, iclass 6, count 0 2006.202.00:37:55.09#ibcon#wrote, iclass 6, count 0 2006.202.00:37:55.09#ibcon#about to read 3, iclass 6, count 0 2006.202.00:37:55.11#ibcon#read 3, iclass 6, count 0 2006.202.00:37:55.11#ibcon#about to read 4, iclass 6, count 0 2006.202.00:37:55.11#ibcon#read 4, iclass 6, count 0 2006.202.00:37:55.11#ibcon#about to read 5, iclass 6, count 0 2006.202.00:37:55.11#ibcon#read 5, iclass 6, count 0 2006.202.00:37:55.11#ibcon#about to read 6, iclass 6, count 0 2006.202.00:37:55.11#ibcon#read 6, iclass 6, count 0 2006.202.00:37:55.11#ibcon#end of sib2, iclass 6, count 0 2006.202.00:37:55.11#ibcon#*mode == 0, iclass 6, count 0 2006.202.00:37:55.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.00:37:55.11#ibcon#[27=BW32\r\n] 2006.202.00:37:55.11#ibcon#*before write, iclass 6, count 0 2006.202.00:37:55.11#ibcon#enter sib2, iclass 6, count 0 2006.202.00:37:55.11#ibcon#flushed, iclass 6, count 0 2006.202.00:37:55.11#ibcon#about to write, iclass 6, count 0 2006.202.00:37:55.11#ibcon#wrote, iclass 6, count 0 2006.202.00:37:55.11#ibcon#about to read 3, iclass 6, count 0 2006.202.00:37:55.14#ibcon#read 3, iclass 6, count 0 2006.202.00:37:55.14#ibcon#about to read 4, iclass 6, count 0 2006.202.00:37:55.14#ibcon#read 4, iclass 6, count 0 2006.202.00:37:55.14#ibcon#about to read 5, iclass 6, count 0 2006.202.00:37:55.14#ibcon#read 5, iclass 6, count 0 2006.202.00:37:55.14#ibcon#about to read 6, iclass 6, count 0 2006.202.00:37:55.14#ibcon#read 6, iclass 6, count 0 2006.202.00:37:55.14#ibcon#end of sib2, iclass 6, count 0 2006.202.00:37:55.14#ibcon#*after write, iclass 6, count 0 2006.202.00:37:55.14#ibcon#*before return 0, iclass 6, count 0 2006.202.00:37:55.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:37:55.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:37:55.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.00:37:55.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.00:37:55.14$setupk4/ifdk4 2006.202.00:37:55.14$ifdk4/lo= 2006.202.00:37:55.14$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.00:37:55.14$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.00:37:55.14$ifdk4/patch= 2006.202.00:37:55.14$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.00:37:55.14$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.00:37:55.14$setupk4/!*+20s 2006.202.00:38:04.74#abcon#<5=/03 2.3 4.4 20.421001001.4\r\n> 2006.202.00:38:04.76#abcon#{5=INTERFACE CLEAR} 2006.202.00:38:04.82#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:38:09.24$setupk4/"tpicd 2006.202.00:38:09.24$setupk4/echo=off 2006.202.00:38:09.24$setupk4/xlog=off 2006.202.00:38:09.24:!2006.202.00:40:16 2006.202.00:38:14.14#trakl#Source acquired 2006.202.00:38:14.14#flagr#flagr/antenna,acquired 2006.202.00:40:16.00:preob 2006.202.00:40:16.13/onsource/TRACKING 2006.202.00:40:16.13:!2006.202.00:40:26 2006.202.00:40:26.00:"tape 2006.202.00:40:26.00:"st=record 2006.202.00:40:26.00:data_valid=on 2006.202.00:40:26.00:midob 2006.202.00:40:26.13/onsource/TRACKING 2006.202.00:40:26.13/wx/20.41,1001.5,100 2006.202.00:40:26.19/cable/+6.4829E-03 2006.202.00:40:27.28/va/01,08,usb,yes,45,48 2006.202.00:40:27.28/va/02,07,usb,yes,48,49 2006.202.00:40:27.28/va/03,08,usb,yes,44,45 2006.202.00:40:27.28/va/04,07,usb,yes,50,52 2006.202.00:40:27.28/va/05,04,usb,yes,44,45 2006.202.00:40:27.28/va/06,05,usb,yes,44,44 2006.202.00:40:27.28/va/07,05,usb,yes,44,45 2006.202.00:40:27.28/va/08,04,usb,yes,43,51 2006.202.00:40:27.51/valo/01,524.99,yes,locked 2006.202.00:40:27.51/valo/02,534.99,yes,locked 2006.202.00:40:27.51/valo/03,564.99,yes,locked 2006.202.00:40:27.51/valo/04,624.99,yes,locked 2006.202.00:40:27.51/valo/05,734.99,yes,locked 2006.202.00:40:27.51/valo/06,814.99,yes,locked 2006.202.00:40:27.51/valo/07,864.99,yes,locked 2006.202.00:40:27.51/valo/08,884.99,yes,locked 2006.202.00:40:28.60/vb/01,04,usb,yes,33,30 2006.202.00:40:28.60/vb/02,05,usb,yes,31,31 2006.202.00:40:28.60/vb/03,04,usb,yes,32,35 2006.202.00:40:28.60/vb/04,05,usb,yes,32,31 2006.202.00:40:28.60/vb/05,04,usb,yes,29,31 2006.202.00:40:28.60/vb/06,04,usb,yes,33,30 2006.202.00:40:28.60/vb/07,04,usb,yes,33,33 2006.202.00:40:28.60/vb/08,04,usb,yes,30,34 2006.202.00:40:28.83/vblo/01,629.99,yes,locked 2006.202.00:40:28.83/vblo/02,634.99,yes,locked 2006.202.00:40:28.83/vblo/03,649.99,yes,locked 2006.202.00:40:28.83/vblo/04,679.99,yes,locked 2006.202.00:40:28.83/vblo/05,709.99,yes,locked 2006.202.00:40:28.83/vblo/06,719.99,yes,locked 2006.202.00:40:28.83/vblo/07,734.99,yes,locked 2006.202.00:40:28.83/vblo/08,744.99,yes,locked 2006.202.00:40:28.98/vabw/8 2006.202.00:40:29.13/vbbw/8 2006.202.00:40:29.22/xfe/off,on,14.5 2006.202.00:40:29.62/ifatt/23,28,28,28 2006.202.00:40:30.07/fmout-gps/S +4.49E-07 2006.202.00:40:30.11:!2006.202.00:41:06 2006.202.00:41:06.00:data_valid=off 2006.202.00:41:06.00:"et 2006.202.00:41:06.00:!+3s 2006.202.00:41:09.02:"tape 2006.202.00:41:09.02:postob 2006.202.00:41:09.09/cable/+6.4838E-03 2006.202.00:41:09.09/wx/20.40,1001.5,100 2006.202.00:41:09.15/fmout-gps/S +4.49E-07 2006.202.00:41:09.15:scan_name=202-0045,jd0607,50 2006.202.00:41:09.15:source=0552+398,055530.81,394849.2,2000.0,neutral 2006.202.00:41:11.13#flagr#flagr/antenna,new-source 2006.202.00:41:11.13:checkk5 2006.202.00:41:11.54/chk_autoobs//k5ts1/ autoobs is running! 2006.202.00:41:11.95/chk_autoobs//k5ts2/ autoobs is running! 2006.202.00:41:12.36/chk_autoobs//k5ts3/ autoobs is running! 2006.202.00:41:12.76/chk_autoobs//k5ts4/ autoobs is running! 2006.202.00:41:13.15/chk_obsdata//k5ts1/T2020040??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.202.00:41:13.55/chk_obsdata//k5ts2/T2020040??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.202.00:41:13.96/chk_obsdata//k5ts3/T2020040??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.202.00:41:14.37/chk_obsdata//k5ts4/T2020040??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.202.00:41:15.09/k5log//k5ts1_log_newline 2006.202.00:41:15.80/k5log//k5ts2_log_newline 2006.202.00:41:16.52/k5log//k5ts3_log_newline 2006.202.00:41:17.23/k5log//k5ts4_log_newline 2006.202.00:41:17.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.00:41:17.26:setupk4=1 2006.202.00:41:17.26$setupk4/echo=on 2006.202.00:41:17.26$setupk4/pcalon 2006.202.00:41:17.26$pcalon/"no phase cal control is implemented here 2006.202.00:41:17.26$setupk4/"tpicd=stop 2006.202.00:41:17.26$setupk4/"rec=synch_on 2006.202.00:41:17.26$setupk4/"rec_mode=128 2006.202.00:41:17.26$setupk4/!* 2006.202.00:41:17.26$setupk4/recpk4 2006.202.00:41:17.26$recpk4/recpatch= 2006.202.00:41:17.26$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.00:41:17.26$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.00:41:17.26$setupk4/vck44 2006.202.00:41:17.26$vck44/valo=1,524.99 2006.202.00:41:17.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.202.00:41:17.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.202.00:41:17.26#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:17.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:17.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:17.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:17.26#ibcon#enter wrdev, iclass 12, count 0 2006.202.00:41:17.26#ibcon#first serial, iclass 12, count 0 2006.202.00:41:17.26#ibcon#enter sib2, iclass 12, count 0 2006.202.00:41:17.26#ibcon#flushed, iclass 12, count 0 2006.202.00:41:17.26#ibcon#about to write, iclass 12, count 0 2006.202.00:41:17.26#ibcon#wrote, iclass 12, count 0 2006.202.00:41:17.26#ibcon#about to read 3, iclass 12, count 0 2006.202.00:41:17.29#ibcon#read 3, iclass 12, count 0 2006.202.00:41:17.29#ibcon#about to read 4, iclass 12, count 0 2006.202.00:41:17.29#ibcon#read 4, iclass 12, count 0 2006.202.00:41:17.29#ibcon#about to read 5, iclass 12, count 0 2006.202.00:41:17.29#ibcon#read 5, iclass 12, count 0 2006.202.00:41:17.29#ibcon#about to read 6, iclass 12, count 0 2006.202.00:41:17.29#ibcon#read 6, iclass 12, count 0 2006.202.00:41:17.29#ibcon#end of sib2, iclass 12, count 0 2006.202.00:41:17.29#ibcon#*mode == 0, iclass 12, count 0 2006.202.00:41:17.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.00:41:17.29#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.00:41:17.29#ibcon#*before write, iclass 12, count 0 2006.202.00:41:17.29#ibcon#enter sib2, iclass 12, count 0 2006.202.00:41:17.29#ibcon#flushed, iclass 12, count 0 2006.202.00:41:17.29#ibcon#about to write, iclass 12, count 0 2006.202.00:41:17.29#ibcon#wrote, iclass 12, count 0 2006.202.00:41:17.29#ibcon#about to read 3, iclass 12, count 0 2006.202.00:41:17.34#ibcon#read 3, iclass 12, count 0 2006.202.00:41:17.34#ibcon#about to read 4, iclass 12, count 0 2006.202.00:41:17.34#ibcon#read 4, iclass 12, count 0 2006.202.00:41:17.34#ibcon#about to read 5, iclass 12, count 0 2006.202.00:41:17.34#ibcon#read 5, iclass 12, count 0 2006.202.00:41:17.34#ibcon#about to read 6, iclass 12, count 0 2006.202.00:41:17.34#ibcon#read 6, iclass 12, count 0 2006.202.00:41:17.34#ibcon#end of sib2, iclass 12, count 0 2006.202.00:41:17.34#ibcon#*after write, iclass 12, count 0 2006.202.00:41:17.34#ibcon#*before return 0, iclass 12, count 0 2006.202.00:41:17.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:17.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:17.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.00:41:17.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.00:41:17.34$vck44/va=1,8 2006.202.00:41:17.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.202.00:41:17.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.202.00:41:17.34#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:17.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:17.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:17.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:17.34#ibcon#enter wrdev, iclass 14, count 2 2006.202.00:41:17.34#ibcon#first serial, iclass 14, count 2 2006.202.00:41:17.34#ibcon#enter sib2, iclass 14, count 2 2006.202.00:41:17.34#ibcon#flushed, iclass 14, count 2 2006.202.00:41:17.34#ibcon#about to write, iclass 14, count 2 2006.202.00:41:17.34#ibcon#wrote, iclass 14, count 2 2006.202.00:41:17.34#ibcon#about to read 3, iclass 14, count 2 2006.202.00:41:17.36#ibcon#read 3, iclass 14, count 2 2006.202.00:41:17.36#ibcon#about to read 4, iclass 14, count 2 2006.202.00:41:17.36#ibcon#read 4, iclass 14, count 2 2006.202.00:41:17.36#ibcon#about to read 5, iclass 14, count 2 2006.202.00:41:17.36#ibcon#read 5, iclass 14, count 2 2006.202.00:41:17.36#ibcon#about to read 6, iclass 14, count 2 2006.202.00:41:17.36#ibcon#read 6, iclass 14, count 2 2006.202.00:41:17.36#ibcon#end of sib2, iclass 14, count 2 2006.202.00:41:17.36#ibcon#*mode == 0, iclass 14, count 2 2006.202.00:41:17.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.202.00:41:17.36#ibcon#[25=AT01-08\r\n] 2006.202.00:41:17.36#ibcon#*before write, iclass 14, count 2 2006.202.00:41:17.36#ibcon#enter sib2, iclass 14, count 2 2006.202.00:41:17.36#ibcon#flushed, iclass 14, count 2 2006.202.00:41:17.36#ibcon#about to write, iclass 14, count 2 2006.202.00:41:17.36#ibcon#wrote, iclass 14, count 2 2006.202.00:41:17.36#ibcon#about to read 3, iclass 14, count 2 2006.202.00:41:17.39#ibcon#read 3, iclass 14, count 2 2006.202.00:41:17.39#ibcon#about to read 4, iclass 14, count 2 2006.202.00:41:17.39#ibcon#read 4, iclass 14, count 2 2006.202.00:41:17.39#ibcon#about to read 5, iclass 14, count 2 2006.202.00:41:17.39#ibcon#read 5, iclass 14, count 2 2006.202.00:41:17.39#ibcon#about to read 6, iclass 14, count 2 2006.202.00:41:17.39#ibcon#read 6, iclass 14, count 2 2006.202.00:41:17.39#ibcon#end of sib2, iclass 14, count 2 2006.202.00:41:17.39#ibcon#*after write, iclass 14, count 2 2006.202.00:41:17.39#ibcon#*before return 0, iclass 14, count 2 2006.202.00:41:17.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:17.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:17.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.202.00:41:17.39#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:17.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:17.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:17.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:17.51#ibcon#enter wrdev, iclass 14, count 0 2006.202.00:41:17.51#ibcon#first serial, iclass 14, count 0 2006.202.00:41:17.51#ibcon#enter sib2, iclass 14, count 0 2006.202.00:41:17.51#ibcon#flushed, iclass 14, count 0 2006.202.00:41:17.51#ibcon#about to write, iclass 14, count 0 2006.202.00:41:17.51#ibcon#wrote, iclass 14, count 0 2006.202.00:41:17.51#ibcon#about to read 3, iclass 14, count 0 2006.202.00:41:17.53#ibcon#read 3, iclass 14, count 0 2006.202.00:41:17.53#ibcon#about to read 4, iclass 14, count 0 2006.202.00:41:17.53#ibcon#read 4, iclass 14, count 0 2006.202.00:41:17.53#ibcon#about to read 5, iclass 14, count 0 2006.202.00:41:17.53#ibcon#read 5, iclass 14, count 0 2006.202.00:41:17.53#ibcon#about to read 6, iclass 14, count 0 2006.202.00:41:17.53#ibcon#read 6, iclass 14, count 0 2006.202.00:41:17.53#ibcon#end of sib2, iclass 14, count 0 2006.202.00:41:17.53#ibcon#*mode == 0, iclass 14, count 0 2006.202.00:41:17.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.00:41:17.53#ibcon#[25=USB\r\n] 2006.202.00:41:17.53#ibcon#*before write, iclass 14, count 0 2006.202.00:41:17.53#ibcon#enter sib2, iclass 14, count 0 2006.202.00:41:17.53#ibcon#flushed, iclass 14, count 0 2006.202.00:41:17.53#ibcon#about to write, iclass 14, count 0 2006.202.00:41:17.53#ibcon#wrote, iclass 14, count 0 2006.202.00:41:17.53#ibcon#about to read 3, iclass 14, count 0 2006.202.00:41:17.56#ibcon#read 3, iclass 14, count 0 2006.202.00:41:17.56#ibcon#about to read 4, iclass 14, count 0 2006.202.00:41:17.56#ibcon#read 4, iclass 14, count 0 2006.202.00:41:17.56#ibcon#about to read 5, iclass 14, count 0 2006.202.00:41:17.56#ibcon#read 5, iclass 14, count 0 2006.202.00:41:17.56#ibcon#about to read 6, iclass 14, count 0 2006.202.00:41:17.56#ibcon#read 6, iclass 14, count 0 2006.202.00:41:17.56#ibcon#end of sib2, iclass 14, count 0 2006.202.00:41:17.56#ibcon#*after write, iclass 14, count 0 2006.202.00:41:17.56#ibcon#*before return 0, iclass 14, count 0 2006.202.00:41:17.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:17.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:17.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.00:41:17.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.00:41:17.56$vck44/valo=2,534.99 2006.202.00:41:17.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.202.00:41:17.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.202.00:41:17.56#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:17.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:17.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:17.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:17.56#ibcon#enter wrdev, iclass 16, count 0 2006.202.00:41:17.56#ibcon#first serial, iclass 16, count 0 2006.202.00:41:17.56#ibcon#enter sib2, iclass 16, count 0 2006.202.00:41:17.56#ibcon#flushed, iclass 16, count 0 2006.202.00:41:17.56#ibcon#about to write, iclass 16, count 0 2006.202.00:41:17.56#ibcon#wrote, iclass 16, count 0 2006.202.00:41:17.56#ibcon#about to read 3, iclass 16, count 0 2006.202.00:41:17.58#ibcon#read 3, iclass 16, count 0 2006.202.00:41:17.58#ibcon#about to read 4, iclass 16, count 0 2006.202.00:41:17.58#ibcon#read 4, iclass 16, count 0 2006.202.00:41:17.58#ibcon#about to read 5, iclass 16, count 0 2006.202.00:41:17.58#ibcon#read 5, iclass 16, count 0 2006.202.00:41:17.58#ibcon#about to read 6, iclass 16, count 0 2006.202.00:41:17.58#ibcon#read 6, iclass 16, count 0 2006.202.00:41:17.58#ibcon#end of sib2, iclass 16, count 0 2006.202.00:41:17.58#ibcon#*mode == 0, iclass 16, count 0 2006.202.00:41:17.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.00:41:17.58#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.00:41:17.58#ibcon#*before write, iclass 16, count 0 2006.202.00:41:17.58#ibcon#enter sib2, iclass 16, count 0 2006.202.00:41:17.58#ibcon#flushed, iclass 16, count 0 2006.202.00:41:17.58#ibcon#about to write, iclass 16, count 0 2006.202.00:41:17.58#ibcon#wrote, iclass 16, count 0 2006.202.00:41:17.58#ibcon#about to read 3, iclass 16, count 0 2006.202.00:41:17.62#ibcon#read 3, iclass 16, count 0 2006.202.00:41:17.62#ibcon#about to read 4, iclass 16, count 0 2006.202.00:41:17.62#ibcon#read 4, iclass 16, count 0 2006.202.00:41:17.62#ibcon#about to read 5, iclass 16, count 0 2006.202.00:41:17.62#ibcon#read 5, iclass 16, count 0 2006.202.00:41:17.62#ibcon#about to read 6, iclass 16, count 0 2006.202.00:41:17.62#ibcon#read 6, iclass 16, count 0 2006.202.00:41:17.62#ibcon#end of sib2, iclass 16, count 0 2006.202.00:41:17.62#ibcon#*after write, iclass 16, count 0 2006.202.00:41:17.62#ibcon#*before return 0, iclass 16, count 0 2006.202.00:41:17.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:17.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:17.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.00:41:17.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.00:41:17.62$vck44/va=2,7 2006.202.00:41:17.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.202.00:41:17.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.202.00:41:17.62#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:17.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:17.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:17.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:17.68#ibcon#enter wrdev, iclass 18, count 2 2006.202.00:41:17.68#ibcon#first serial, iclass 18, count 2 2006.202.00:41:17.68#ibcon#enter sib2, iclass 18, count 2 2006.202.00:41:17.68#ibcon#flushed, iclass 18, count 2 2006.202.00:41:17.68#ibcon#about to write, iclass 18, count 2 2006.202.00:41:17.68#ibcon#wrote, iclass 18, count 2 2006.202.00:41:17.68#ibcon#about to read 3, iclass 18, count 2 2006.202.00:41:17.70#ibcon#read 3, iclass 18, count 2 2006.202.00:41:17.70#ibcon#about to read 4, iclass 18, count 2 2006.202.00:41:17.70#ibcon#read 4, iclass 18, count 2 2006.202.00:41:17.70#ibcon#about to read 5, iclass 18, count 2 2006.202.00:41:17.70#ibcon#read 5, iclass 18, count 2 2006.202.00:41:17.70#ibcon#about to read 6, iclass 18, count 2 2006.202.00:41:17.70#ibcon#read 6, iclass 18, count 2 2006.202.00:41:17.70#ibcon#end of sib2, iclass 18, count 2 2006.202.00:41:17.70#ibcon#*mode == 0, iclass 18, count 2 2006.202.00:41:17.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.202.00:41:17.70#ibcon#[25=AT02-07\r\n] 2006.202.00:41:17.70#ibcon#*before write, iclass 18, count 2 2006.202.00:41:17.70#ibcon#enter sib2, iclass 18, count 2 2006.202.00:41:17.70#ibcon#flushed, iclass 18, count 2 2006.202.00:41:17.70#ibcon#about to write, iclass 18, count 2 2006.202.00:41:17.70#ibcon#wrote, iclass 18, count 2 2006.202.00:41:17.70#ibcon#about to read 3, iclass 18, count 2 2006.202.00:41:17.73#ibcon#read 3, iclass 18, count 2 2006.202.00:41:17.73#ibcon#about to read 4, iclass 18, count 2 2006.202.00:41:17.73#ibcon#read 4, iclass 18, count 2 2006.202.00:41:17.73#ibcon#about to read 5, iclass 18, count 2 2006.202.00:41:17.73#ibcon#read 5, iclass 18, count 2 2006.202.00:41:17.73#ibcon#about to read 6, iclass 18, count 2 2006.202.00:41:17.73#ibcon#read 6, iclass 18, count 2 2006.202.00:41:17.73#ibcon#end of sib2, iclass 18, count 2 2006.202.00:41:17.73#ibcon#*after write, iclass 18, count 2 2006.202.00:41:17.73#ibcon#*before return 0, iclass 18, count 2 2006.202.00:41:17.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:17.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:17.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.202.00:41:17.73#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:17.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:17.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:17.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:17.85#ibcon#enter wrdev, iclass 18, count 0 2006.202.00:41:17.85#ibcon#first serial, iclass 18, count 0 2006.202.00:41:17.85#ibcon#enter sib2, iclass 18, count 0 2006.202.00:41:17.85#ibcon#flushed, iclass 18, count 0 2006.202.00:41:17.85#ibcon#about to write, iclass 18, count 0 2006.202.00:41:17.85#ibcon#wrote, iclass 18, count 0 2006.202.00:41:17.85#ibcon#about to read 3, iclass 18, count 0 2006.202.00:41:17.87#ibcon#read 3, iclass 18, count 0 2006.202.00:41:17.87#ibcon#about to read 4, iclass 18, count 0 2006.202.00:41:17.87#ibcon#read 4, iclass 18, count 0 2006.202.00:41:17.87#ibcon#about to read 5, iclass 18, count 0 2006.202.00:41:17.87#ibcon#read 5, iclass 18, count 0 2006.202.00:41:17.87#ibcon#about to read 6, iclass 18, count 0 2006.202.00:41:17.87#ibcon#read 6, iclass 18, count 0 2006.202.00:41:17.87#ibcon#end of sib2, iclass 18, count 0 2006.202.00:41:17.87#ibcon#*mode == 0, iclass 18, count 0 2006.202.00:41:17.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.00:41:17.87#ibcon#[25=USB\r\n] 2006.202.00:41:17.87#ibcon#*before write, iclass 18, count 0 2006.202.00:41:17.87#ibcon#enter sib2, iclass 18, count 0 2006.202.00:41:17.87#ibcon#flushed, iclass 18, count 0 2006.202.00:41:17.87#ibcon#about to write, iclass 18, count 0 2006.202.00:41:17.87#ibcon#wrote, iclass 18, count 0 2006.202.00:41:17.87#ibcon#about to read 3, iclass 18, count 0 2006.202.00:41:17.90#ibcon#read 3, iclass 18, count 0 2006.202.00:41:17.90#ibcon#about to read 4, iclass 18, count 0 2006.202.00:41:17.90#ibcon#read 4, iclass 18, count 0 2006.202.00:41:17.90#ibcon#about to read 5, iclass 18, count 0 2006.202.00:41:17.90#ibcon#read 5, iclass 18, count 0 2006.202.00:41:17.90#ibcon#about to read 6, iclass 18, count 0 2006.202.00:41:17.90#ibcon#read 6, iclass 18, count 0 2006.202.00:41:17.90#ibcon#end of sib2, iclass 18, count 0 2006.202.00:41:17.90#ibcon#*after write, iclass 18, count 0 2006.202.00:41:17.90#ibcon#*before return 0, iclass 18, count 0 2006.202.00:41:17.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:17.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:17.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.00:41:17.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.00:41:17.90$vck44/valo=3,564.99 2006.202.00:41:17.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.202.00:41:17.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.202.00:41:17.90#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:17.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.202.00:41:17.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.202.00:41:17.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.202.00:41:17.90#ibcon#enter wrdev, iclass 20, count 0 2006.202.00:41:17.90#ibcon#first serial, iclass 20, count 0 2006.202.00:41:17.90#ibcon#enter sib2, iclass 20, count 0 2006.202.00:41:17.90#ibcon#flushed, iclass 20, count 0 2006.202.00:41:17.90#ibcon#about to write, iclass 20, count 0 2006.202.00:41:17.90#ibcon#wrote, iclass 20, count 0 2006.202.00:41:17.90#ibcon#about to read 3, iclass 20, count 0 2006.202.00:41:17.92#ibcon#read 3, iclass 20, count 0 2006.202.00:41:17.92#ibcon#about to read 4, iclass 20, count 0 2006.202.00:41:17.92#ibcon#read 4, iclass 20, count 0 2006.202.00:41:17.92#ibcon#about to read 5, iclass 20, count 0 2006.202.00:41:17.92#ibcon#read 5, iclass 20, count 0 2006.202.00:41:17.92#ibcon#about to read 6, iclass 20, count 0 2006.202.00:41:17.92#ibcon#read 6, iclass 20, count 0 2006.202.00:41:17.92#ibcon#end of sib2, iclass 20, count 0 2006.202.00:41:17.92#ibcon#*mode == 0, iclass 20, count 0 2006.202.00:41:17.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.00:41:17.92#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.00:41:17.92#ibcon#*before write, iclass 20, count 0 2006.202.00:41:17.92#ibcon#enter sib2, iclass 20, count 0 2006.202.00:41:17.92#ibcon#flushed, iclass 20, count 0 2006.202.00:41:17.92#ibcon#about to write, iclass 20, count 0 2006.202.00:41:17.92#ibcon#wrote, iclass 20, count 0 2006.202.00:41:17.92#ibcon#about to read 3, iclass 20, count 0 2006.202.00:41:17.96#ibcon#read 3, iclass 20, count 0 2006.202.00:41:17.96#ibcon#about to read 4, iclass 20, count 0 2006.202.00:41:17.96#ibcon#read 4, iclass 20, count 0 2006.202.00:41:17.96#ibcon#about to read 5, iclass 20, count 0 2006.202.00:41:17.96#ibcon#read 5, iclass 20, count 0 2006.202.00:41:17.96#ibcon#about to read 6, iclass 20, count 0 2006.202.00:41:17.96#ibcon#read 6, iclass 20, count 0 2006.202.00:41:17.96#ibcon#end of sib2, iclass 20, count 0 2006.202.00:41:17.96#ibcon#*after write, iclass 20, count 0 2006.202.00:41:17.96#ibcon#*before return 0, iclass 20, count 0 2006.202.00:41:17.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.202.00:41:17.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.202.00:41:17.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.00:41:17.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.00:41:17.96$vck44/va=3,8 2006.202.00:41:17.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.202.00:41:17.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.202.00:41:17.96#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:17.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.202.00:41:18.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.202.00:41:18.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.202.00:41:18.02#ibcon#enter wrdev, iclass 22, count 2 2006.202.00:41:18.02#ibcon#first serial, iclass 22, count 2 2006.202.00:41:18.02#ibcon#enter sib2, iclass 22, count 2 2006.202.00:41:18.02#ibcon#flushed, iclass 22, count 2 2006.202.00:41:18.02#ibcon#about to write, iclass 22, count 2 2006.202.00:41:18.02#ibcon#wrote, iclass 22, count 2 2006.202.00:41:18.02#ibcon#about to read 3, iclass 22, count 2 2006.202.00:41:18.04#ibcon#read 3, iclass 22, count 2 2006.202.00:41:18.04#ibcon#about to read 4, iclass 22, count 2 2006.202.00:41:18.04#ibcon#read 4, iclass 22, count 2 2006.202.00:41:18.04#ibcon#about to read 5, iclass 22, count 2 2006.202.00:41:18.04#ibcon#read 5, iclass 22, count 2 2006.202.00:41:18.04#ibcon#about to read 6, iclass 22, count 2 2006.202.00:41:18.04#ibcon#read 6, iclass 22, count 2 2006.202.00:41:18.04#ibcon#end of sib2, iclass 22, count 2 2006.202.00:41:18.04#ibcon#*mode == 0, iclass 22, count 2 2006.202.00:41:18.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.202.00:41:18.04#ibcon#[25=AT03-08\r\n] 2006.202.00:41:18.04#ibcon#*before write, iclass 22, count 2 2006.202.00:41:18.04#ibcon#enter sib2, iclass 22, count 2 2006.202.00:41:18.04#ibcon#flushed, iclass 22, count 2 2006.202.00:41:18.04#ibcon#about to write, iclass 22, count 2 2006.202.00:41:18.04#ibcon#wrote, iclass 22, count 2 2006.202.00:41:18.04#ibcon#about to read 3, iclass 22, count 2 2006.202.00:41:18.07#ibcon#read 3, iclass 22, count 2 2006.202.00:41:18.07#ibcon#about to read 4, iclass 22, count 2 2006.202.00:41:18.07#ibcon#read 4, iclass 22, count 2 2006.202.00:41:18.07#ibcon#about to read 5, iclass 22, count 2 2006.202.00:41:18.07#ibcon#read 5, iclass 22, count 2 2006.202.00:41:18.07#ibcon#about to read 6, iclass 22, count 2 2006.202.00:41:18.07#ibcon#read 6, iclass 22, count 2 2006.202.00:41:18.07#ibcon#end of sib2, iclass 22, count 2 2006.202.00:41:18.07#ibcon#*after write, iclass 22, count 2 2006.202.00:41:18.07#ibcon#*before return 0, iclass 22, count 2 2006.202.00:41:18.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.202.00:41:18.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.202.00:41:18.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.202.00:41:18.07#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:18.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.202.00:41:18.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.202.00:41:18.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.202.00:41:18.19#ibcon#enter wrdev, iclass 22, count 0 2006.202.00:41:18.19#ibcon#first serial, iclass 22, count 0 2006.202.00:41:18.19#ibcon#enter sib2, iclass 22, count 0 2006.202.00:41:18.19#ibcon#flushed, iclass 22, count 0 2006.202.00:41:18.19#ibcon#about to write, iclass 22, count 0 2006.202.00:41:18.19#ibcon#wrote, iclass 22, count 0 2006.202.00:41:18.19#ibcon#about to read 3, iclass 22, count 0 2006.202.00:41:18.21#ibcon#read 3, iclass 22, count 0 2006.202.00:41:18.21#ibcon#about to read 4, iclass 22, count 0 2006.202.00:41:18.21#ibcon#read 4, iclass 22, count 0 2006.202.00:41:18.21#ibcon#about to read 5, iclass 22, count 0 2006.202.00:41:18.21#ibcon#read 5, iclass 22, count 0 2006.202.00:41:18.21#ibcon#about to read 6, iclass 22, count 0 2006.202.00:41:18.21#ibcon#read 6, iclass 22, count 0 2006.202.00:41:18.21#ibcon#end of sib2, iclass 22, count 0 2006.202.00:41:18.21#ibcon#*mode == 0, iclass 22, count 0 2006.202.00:41:18.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.00:41:18.21#ibcon#[25=USB\r\n] 2006.202.00:41:18.21#ibcon#*before write, iclass 22, count 0 2006.202.00:41:18.21#ibcon#enter sib2, iclass 22, count 0 2006.202.00:41:18.21#ibcon#flushed, iclass 22, count 0 2006.202.00:41:18.21#ibcon#about to write, iclass 22, count 0 2006.202.00:41:18.21#ibcon#wrote, iclass 22, count 0 2006.202.00:41:18.21#ibcon#about to read 3, iclass 22, count 0 2006.202.00:41:18.24#ibcon#read 3, iclass 22, count 0 2006.202.00:41:18.24#ibcon#about to read 4, iclass 22, count 0 2006.202.00:41:18.24#ibcon#read 4, iclass 22, count 0 2006.202.00:41:18.24#ibcon#about to read 5, iclass 22, count 0 2006.202.00:41:18.24#ibcon#read 5, iclass 22, count 0 2006.202.00:41:18.24#ibcon#about to read 6, iclass 22, count 0 2006.202.00:41:18.24#ibcon#read 6, iclass 22, count 0 2006.202.00:41:18.24#ibcon#end of sib2, iclass 22, count 0 2006.202.00:41:18.24#ibcon#*after write, iclass 22, count 0 2006.202.00:41:18.24#ibcon#*before return 0, iclass 22, count 0 2006.202.00:41:18.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.202.00:41:18.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.202.00:41:18.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.00:41:18.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.00:41:18.24$vck44/valo=4,624.99 2006.202.00:41:18.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.202.00:41:18.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.202.00:41:18.24#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:18.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:18.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:18.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:18.24#ibcon#enter wrdev, iclass 24, count 0 2006.202.00:41:18.24#ibcon#first serial, iclass 24, count 0 2006.202.00:41:18.24#ibcon#enter sib2, iclass 24, count 0 2006.202.00:41:18.24#ibcon#flushed, iclass 24, count 0 2006.202.00:41:18.24#ibcon#about to write, iclass 24, count 0 2006.202.00:41:18.24#ibcon#wrote, iclass 24, count 0 2006.202.00:41:18.24#ibcon#about to read 3, iclass 24, count 0 2006.202.00:41:18.26#ibcon#read 3, iclass 24, count 0 2006.202.00:41:18.26#ibcon#about to read 4, iclass 24, count 0 2006.202.00:41:18.26#ibcon#read 4, iclass 24, count 0 2006.202.00:41:18.26#ibcon#about to read 5, iclass 24, count 0 2006.202.00:41:18.26#ibcon#read 5, iclass 24, count 0 2006.202.00:41:18.26#ibcon#about to read 6, iclass 24, count 0 2006.202.00:41:18.26#ibcon#read 6, iclass 24, count 0 2006.202.00:41:18.26#ibcon#end of sib2, iclass 24, count 0 2006.202.00:41:18.26#ibcon#*mode == 0, iclass 24, count 0 2006.202.00:41:18.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.00:41:18.26#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.00:41:18.26#ibcon#*before write, iclass 24, count 0 2006.202.00:41:18.26#ibcon#enter sib2, iclass 24, count 0 2006.202.00:41:18.26#ibcon#flushed, iclass 24, count 0 2006.202.00:41:18.26#ibcon#about to write, iclass 24, count 0 2006.202.00:41:18.26#ibcon#wrote, iclass 24, count 0 2006.202.00:41:18.26#ibcon#about to read 3, iclass 24, count 0 2006.202.00:41:18.30#ibcon#read 3, iclass 24, count 0 2006.202.00:41:18.30#ibcon#about to read 4, iclass 24, count 0 2006.202.00:41:18.30#ibcon#read 4, iclass 24, count 0 2006.202.00:41:18.30#ibcon#about to read 5, iclass 24, count 0 2006.202.00:41:18.30#ibcon#read 5, iclass 24, count 0 2006.202.00:41:18.30#ibcon#about to read 6, iclass 24, count 0 2006.202.00:41:18.30#ibcon#read 6, iclass 24, count 0 2006.202.00:41:18.30#ibcon#end of sib2, iclass 24, count 0 2006.202.00:41:18.30#ibcon#*after write, iclass 24, count 0 2006.202.00:41:18.30#ibcon#*before return 0, iclass 24, count 0 2006.202.00:41:18.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:18.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:18.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.00:41:18.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.00:41:18.30$vck44/va=4,7 2006.202.00:41:18.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.202.00:41:18.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.202.00:41:18.30#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:18.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:18.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:18.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:18.36#ibcon#enter wrdev, iclass 26, count 2 2006.202.00:41:18.36#ibcon#first serial, iclass 26, count 2 2006.202.00:41:18.36#ibcon#enter sib2, iclass 26, count 2 2006.202.00:41:18.36#ibcon#flushed, iclass 26, count 2 2006.202.00:41:18.36#ibcon#about to write, iclass 26, count 2 2006.202.00:41:18.36#ibcon#wrote, iclass 26, count 2 2006.202.00:41:18.36#ibcon#about to read 3, iclass 26, count 2 2006.202.00:41:18.38#ibcon#read 3, iclass 26, count 2 2006.202.00:41:18.38#ibcon#about to read 4, iclass 26, count 2 2006.202.00:41:18.38#ibcon#read 4, iclass 26, count 2 2006.202.00:41:18.38#ibcon#about to read 5, iclass 26, count 2 2006.202.00:41:18.38#ibcon#read 5, iclass 26, count 2 2006.202.00:41:18.38#ibcon#about to read 6, iclass 26, count 2 2006.202.00:41:18.38#ibcon#read 6, iclass 26, count 2 2006.202.00:41:18.38#ibcon#end of sib2, iclass 26, count 2 2006.202.00:41:18.38#ibcon#*mode == 0, iclass 26, count 2 2006.202.00:41:18.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.202.00:41:18.38#ibcon#[25=AT04-07\r\n] 2006.202.00:41:18.38#ibcon#*before write, iclass 26, count 2 2006.202.00:41:18.38#ibcon#enter sib2, iclass 26, count 2 2006.202.00:41:18.38#ibcon#flushed, iclass 26, count 2 2006.202.00:41:18.38#ibcon#about to write, iclass 26, count 2 2006.202.00:41:18.38#ibcon#wrote, iclass 26, count 2 2006.202.00:41:18.38#ibcon#about to read 3, iclass 26, count 2 2006.202.00:41:18.41#ibcon#read 3, iclass 26, count 2 2006.202.00:41:18.41#ibcon#about to read 4, iclass 26, count 2 2006.202.00:41:18.41#ibcon#read 4, iclass 26, count 2 2006.202.00:41:18.41#ibcon#about to read 5, iclass 26, count 2 2006.202.00:41:18.41#ibcon#read 5, iclass 26, count 2 2006.202.00:41:18.41#ibcon#about to read 6, iclass 26, count 2 2006.202.00:41:18.41#ibcon#read 6, iclass 26, count 2 2006.202.00:41:18.41#ibcon#end of sib2, iclass 26, count 2 2006.202.00:41:18.41#ibcon#*after write, iclass 26, count 2 2006.202.00:41:18.41#ibcon#*before return 0, iclass 26, count 2 2006.202.00:41:18.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:18.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:18.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.202.00:41:18.41#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:18.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:18.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:18.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:18.53#ibcon#enter wrdev, iclass 26, count 0 2006.202.00:41:18.53#ibcon#first serial, iclass 26, count 0 2006.202.00:41:18.53#ibcon#enter sib2, iclass 26, count 0 2006.202.00:41:18.53#ibcon#flushed, iclass 26, count 0 2006.202.00:41:18.53#ibcon#about to write, iclass 26, count 0 2006.202.00:41:18.53#ibcon#wrote, iclass 26, count 0 2006.202.00:41:18.53#ibcon#about to read 3, iclass 26, count 0 2006.202.00:41:18.55#ibcon#read 3, iclass 26, count 0 2006.202.00:41:18.55#ibcon#about to read 4, iclass 26, count 0 2006.202.00:41:18.55#ibcon#read 4, iclass 26, count 0 2006.202.00:41:18.55#ibcon#about to read 5, iclass 26, count 0 2006.202.00:41:18.55#ibcon#read 5, iclass 26, count 0 2006.202.00:41:18.55#ibcon#about to read 6, iclass 26, count 0 2006.202.00:41:18.55#ibcon#read 6, iclass 26, count 0 2006.202.00:41:18.55#ibcon#end of sib2, iclass 26, count 0 2006.202.00:41:18.55#ibcon#*mode == 0, iclass 26, count 0 2006.202.00:41:18.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.00:41:18.55#ibcon#[25=USB\r\n] 2006.202.00:41:18.55#ibcon#*before write, iclass 26, count 0 2006.202.00:41:18.55#ibcon#enter sib2, iclass 26, count 0 2006.202.00:41:18.55#ibcon#flushed, iclass 26, count 0 2006.202.00:41:18.55#ibcon#about to write, iclass 26, count 0 2006.202.00:41:18.55#ibcon#wrote, iclass 26, count 0 2006.202.00:41:18.55#ibcon#about to read 3, iclass 26, count 0 2006.202.00:41:18.58#ibcon#read 3, iclass 26, count 0 2006.202.00:41:18.58#ibcon#about to read 4, iclass 26, count 0 2006.202.00:41:18.58#ibcon#read 4, iclass 26, count 0 2006.202.00:41:18.58#ibcon#about to read 5, iclass 26, count 0 2006.202.00:41:18.58#ibcon#read 5, iclass 26, count 0 2006.202.00:41:18.58#ibcon#about to read 6, iclass 26, count 0 2006.202.00:41:18.58#ibcon#read 6, iclass 26, count 0 2006.202.00:41:18.58#ibcon#end of sib2, iclass 26, count 0 2006.202.00:41:18.58#ibcon#*after write, iclass 26, count 0 2006.202.00:41:18.58#ibcon#*before return 0, iclass 26, count 0 2006.202.00:41:18.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:18.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:18.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.00:41:18.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.00:41:18.58$vck44/valo=5,734.99 2006.202.00:41:18.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.202.00:41:18.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.202.00:41:18.58#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:18.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:18.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:18.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:18.58#ibcon#enter wrdev, iclass 28, count 0 2006.202.00:41:18.58#ibcon#first serial, iclass 28, count 0 2006.202.00:41:18.58#ibcon#enter sib2, iclass 28, count 0 2006.202.00:41:18.58#ibcon#flushed, iclass 28, count 0 2006.202.00:41:18.58#ibcon#about to write, iclass 28, count 0 2006.202.00:41:18.58#ibcon#wrote, iclass 28, count 0 2006.202.00:41:18.58#ibcon#about to read 3, iclass 28, count 0 2006.202.00:41:18.60#ibcon#read 3, iclass 28, count 0 2006.202.00:41:18.60#ibcon#about to read 4, iclass 28, count 0 2006.202.00:41:18.60#ibcon#read 4, iclass 28, count 0 2006.202.00:41:18.60#ibcon#about to read 5, iclass 28, count 0 2006.202.00:41:18.60#ibcon#read 5, iclass 28, count 0 2006.202.00:41:18.60#ibcon#about to read 6, iclass 28, count 0 2006.202.00:41:18.60#ibcon#read 6, iclass 28, count 0 2006.202.00:41:18.60#ibcon#end of sib2, iclass 28, count 0 2006.202.00:41:18.60#ibcon#*mode == 0, iclass 28, count 0 2006.202.00:41:18.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.00:41:18.60#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.00:41:18.60#ibcon#*before write, iclass 28, count 0 2006.202.00:41:18.60#ibcon#enter sib2, iclass 28, count 0 2006.202.00:41:18.60#ibcon#flushed, iclass 28, count 0 2006.202.00:41:18.60#ibcon#about to write, iclass 28, count 0 2006.202.00:41:18.60#ibcon#wrote, iclass 28, count 0 2006.202.00:41:18.60#ibcon#about to read 3, iclass 28, count 0 2006.202.00:41:18.64#ibcon#read 3, iclass 28, count 0 2006.202.00:41:18.64#ibcon#about to read 4, iclass 28, count 0 2006.202.00:41:18.64#ibcon#read 4, iclass 28, count 0 2006.202.00:41:18.64#ibcon#about to read 5, iclass 28, count 0 2006.202.00:41:18.64#ibcon#read 5, iclass 28, count 0 2006.202.00:41:18.64#ibcon#about to read 6, iclass 28, count 0 2006.202.00:41:18.64#ibcon#read 6, iclass 28, count 0 2006.202.00:41:18.64#ibcon#end of sib2, iclass 28, count 0 2006.202.00:41:18.64#ibcon#*after write, iclass 28, count 0 2006.202.00:41:18.64#ibcon#*before return 0, iclass 28, count 0 2006.202.00:41:18.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:18.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:18.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.00:41:18.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.00:41:18.64$vck44/va=5,4 2006.202.00:41:18.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.202.00:41:18.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.202.00:41:18.64#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:18.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:18.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:18.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:18.70#ibcon#enter wrdev, iclass 30, count 2 2006.202.00:41:18.70#ibcon#first serial, iclass 30, count 2 2006.202.00:41:18.70#ibcon#enter sib2, iclass 30, count 2 2006.202.00:41:18.70#ibcon#flushed, iclass 30, count 2 2006.202.00:41:18.70#ibcon#about to write, iclass 30, count 2 2006.202.00:41:18.70#ibcon#wrote, iclass 30, count 2 2006.202.00:41:18.70#ibcon#about to read 3, iclass 30, count 2 2006.202.00:41:18.72#ibcon#read 3, iclass 30, count 2 2006.202.00:41:18.72#ibcon#about to read 4, iclass 30, count 2 2006.202.00:41:18.72#ibcon#read 4, iclass 30, count 2 2006.202.00:41:18.72#ibcon#about to read 5, iclass 30, count 2 2006.202.00:41:18.72#ibcon#read 5, iclass 30, count 2 2006.202.00:41:18.72#ibcon#about to read 6, iclass 30, count 2 2006.202.00:41:18.72#ibcon#read 6, iclass 30, count 2 2006.202.00:41:18.72#ibcon#end of sib2, iclass 30, count 2 2006.202.00:41:18.72#ibcon#*mode == 0, iclass 30, count 2 2006.202.00:41:18.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.202.00:41:18.72#ibcon#[25=AT05-04\r\n] 2006.202.00:41:18.72#ibcon#*before write, iclass 30, count 2 2006.202.00:41:18.72#ibcon#enter sib2, iclass 30, count 2 2006.202.00:41:18.72#ibcon#flushed, iclass 30, count 2 2006.202.00:41:18.72#ibcon#about to write, iclass 30, count 2 2006.202.00:41:18.72#ibcon#wrote, iclass 30, count 2 2006.202.00:41:18.72#ibcon#about to read 3, iclass 30, count 2 2006.202.00:41:18.75#ibcon#read 3, iclass 30, count 2 2006.202.00:41:18.75#ibcon#about to read 4, iclass 30, count 2 2006.202.00:41:18.75#ibcon#read 4, iclass 30, count 2 2006.202.00:41:18.75#ibcon#about to read 5, iclass 30, count 2 2006.202.00:41:18.75#ibcon#read 5, iclass 30, count 2 2006.202.00:41:18.75#ibcon#about to read 6, iclass 30, count 2 2006.202.00:41:18.75#ibcon#read 6, iclass 30, count 2 2006.202.00:41:18.75#ibcon#end of sib2, iclass 30, count 2 2006.202.00:41:18.75#ibcon#*after write, iclass 30, count 2 2006.202.00:41:18.75#ibcon#*before return 0, iclass 30, count 2 2006.202.00:41:18.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:18.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:18.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.202.00:41:18.75#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:18.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:18.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:18.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:18.87#ibcon#enter wrdev, iclass 30, count 0 2006.202.00:41:18.87#ibcon#first serial, iclass 30, count 0 2006.202.00:41:18.87#ibcon#enter sib2, iclass 30, count 0 2006.202.00:41:18.87#ibcon#flushed, iclass 30, count 0 2006.202.00:41:18.87#ibcon#about to write, iclass 30, count 0 2006.202.00:41:18.87#ibcon#wrote, iclass 30, count 0 2006.202.00:41:18.87#ibcon#about to read 3, iclass 30, count 0 2006.202.00:41:18.89#ibcon#read 3, iclass 30, count 0 2006.202.00:41:18.89#ibcon#about to read 4, iclass 30, count 0 2006.202.00:41:18.89#ibcon#read 4, iclass 30, count 0 2006.202.00:41:18.89#ibcon#about to read 5, iclass 30, count 0 2006.202.00:41:18.89#ibcon#read 5, iclass 30, count 0 2006.202.00:41:18.89#ibcon#about to read 6, iclass 30, count 0 2006.202.00:41:18.89#ibcon#read 6, iclass 30, count 0 2006.202.00:41:18.89#ibcon#end of sib2, iclass 30, count 0 2006.202.00:41:18.89#ibcon#*mode == 0, iclass 30, count 0 2006.202.00:41:18.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.00:41:18.89#ibcon#[25=USB\r\n] 2006.202.00:41:18.89#ibcon#*before write, iclass 30, count 0 2006.202.00:41:18.89#ibcon#enter sib2, iclass 30, count 0 2006.202.00:41:18.89#ibcon#flushed, iclass 30, count 0 2006.202.00:41:18.89#ibcon#about to write, iclass 30, count 0 2006.202.00:41:18.89#ibcon#wrote, iclass 30, count 0 2006.202.00:41:18.89#ibcon#about to read 3, iclass 30, count 0 2006.202.00:41:18.92#ibcon#read 3, iclass 30, count 0 2006.202.00:41:18.92#ibcon#about to read 4, iclass 30, count 0 2006.202.00:41:18.92#ibcon#read 4, iclass 30, count 0 2006.202.00:41:18.92#ibcon#about to read 5, iclass 30, count 0 2006.202.00:41:18.92#ibcon#read 5, iclass 30, count 0 2006.202.00:41:18.92#ibcon#about to read 6, iclass 30, count 0 2006.202.00:41:18.92#ibcon#read 6, iclass 30, count 0 2006.202.00:41:18.92#ibcon#end of sib2, iclass 30, count 0 2006.202.00:41:18.92#ibcon#*after write, iclass 30, count 0 2006.202.00:41:18.92#ibcon#*before return 0, iclass 30, count 0 2006.202.00:41:18.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:18.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:18.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.00:41:18.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.00:41:18.92$vck44/valo=6,814.99 2006.202.00:41:18.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.202.00:41:18.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.202.00:41:18.92#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:18.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:18.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:18.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:18.92#ibcon#enter wrdev, iclass 32, count 0 2006.202.00:41:18.92#ibcon#first serial, iclass 32, count 0 2006.202.00:41:18.92#ibcon#enter sib2, iclass 32, count 0 2006.202.00:41:18.92#ibcon#flushed, iclass 32, count 0 2006.202.00:41:18.92#ibcon#about to write, iclass 32, count 0 2006.202.00:41:18.92#ibcon#wrote, iclass 32, count 0 2006.202.00:41:18.92#ibcon#about to read 3, iclass 32, count 0 2006.202.00:41:18.94#ibcon#read 3, iclass 32, count 0 2006.202.00:41:18.94#ibcon#about to read 4, iclass 32, count 0 2006.202.00:41:18.94#ibcon#read 4, iclass 32, count 0 2006.202.00:41:18.94#ibcon#about to read 5, iclass 32, count 0 2006.202.00:41:18.94#ibcon#read 5, iclass 32, count 0 2006.202.00:41:18.94#ibcon#about to read 6, iclass 32, count 0 2006.202.00:41:18.94#ibcon#read 6, iclass 32, count 0 2006.202.00:41:18.94#ibcon#end of sib2, iclass 32, count 0 2006.202.00:41:18.94#ibcon#*mode == 0, iclass 32, count 0 2006.202.00:41:18.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.00:41:18.94#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.00:41:18.94#ibcon#*before write, iclass 32, count 0 2006.202.00:41:18.94#ibcon#enter sib2, iclass 32, count 0 2006.202.00:41:18.94#ibcon#flushed, iclass 32, count 0 2006.202.00:41:18.94#ibcon#about to write, iclass 32, count 0 2006.202.00:41:18.94#ibcon#wrote, iclass 32, count 0 2006.202.00:41:18.94#ibcon#about to read 3, iclass 32, count 0 2006.202.00:41:18.98#ibcon#read 3, iclass 32, count 0 2006.202.00:41:18.98#ibcon#about to read 4, iclass 32, count 0 2006.202.00:41:18.98#ibcon#read 4, iclass 32, count 0 2006.202.00:41:18.98#ibcon#about to read 5, iclass 32, count 0 2006.202.00:41:18.98#ibcon#read 5, iclass 32, count 0 2006.202.00:41:18.98#ibcon#about to read 6, iclass 32, count 0 2006.202.00:41:18.98#ibcon#read 6, iclass 32, count 0 2006.202.00:41:18.98#ibcon#end of sib2, iclass 32, count 0 2006.202.00:41:18.98#ibcon#*after write, iclass 32, count 0 2006.202.00:41:18.98#ibcon#*before return 0, iclass 32, count 0 2006.202.00:41:18.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:18.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:18.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.00:41:18.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.00:41:18.98$vck44/va=6,5 2006.202.00:41:18.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.202.00:41:18.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.202.00:41:18.98#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:18.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:19.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:19.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:19.04#ibcon#enter wrdev, iclass 34, count 2 2006.202.00:41:19.04#ibcon#first serial, iclass 34, count 2 2006.202.00:41:19.04#ibcon#enter sib2, iclass 34, count 2 2006.202.00:41:19.04#ibcon#flushed, iclass 34, count 2 2006.202.00:41:19.04#ibcon#about to write, iclass 34, count 2 2006.202.00:41:19.04#ibcon#wrote, iclass 34, count 2 2006.202.00:41:19.04#ibcon#about to read 3, iclass 34, count 2 2006.202.00:41:19.06#ibcon#read 3, iclass 34, count 2 2006.202.00:41:19.06#ibcon#about to read 4, iclass 34, count 2 2006.202.00:41:19.06#ibcon#read 4, iclass 34, count 2 2006.202.00:41:19.06#ibcon#about to read 5, iclass 34, count 2 2006.202.00:41:19.06#ibcon#read 5, iclass 34, count 2 2006.202.00:41:19.06#ibcon#about to read 6, iclass 34, count 2 2006.202.00:41:19.06#ibcon#read 6, iclass 34, count 2 2006.202.00:41:19.06#ibcon#end of sib2, iclass 34, count 2 2006.202.00:41:19.06#ibcon#*mode == 0, iclass 34, count 2 2006.202.00:41:19.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.202.00:41:19.06#ibcon#[25=AT06-05\r\n] 2006.202.00:41:19.06#ibcon#*before write, iclass 34, count 2 2006.202.00:41:19.06#ibcon#enter sib2, iclass 34, count 2 2006.202.00:41:19.06#ibcon#flushed, iclass 34, count 2 2006.202.00:41:19.06#ibcon#about to write, iclass 34, count 2 2006.202.00:41:19.06#ibcon#wrote, iclass 34, count 2 2006.202.00:41:19.06#ibcon#about to read 3, iclass 34, count 2 2006.202.00:41:19.09#ibcon#read 3, iclass 34, count 2 2006.202.00:41:19.09#ibcon#about to read 4, iclass 34, count 2 2006.202.00:41:19.09#ibcon#read 4, iclass 34, count 2 2006.202.00:41:19.09#ibcon#about to read 5, iclass 34, count 2 2006.202.00:41:19.09#ibcon#read 5, iclass 34, count 2 2006.202.00:41:19.09#ibcon#about to read 6, iclass 34, count 2 2006.202.00:41:19.09#ibcon#read 6, iclass 34, count 2 2006.202.00:41:19.09#ibcon#end of sib2, iclass 34, count 2 2006.202.00:41:19.09#ibcon#*after write, iclass 34, count 2 2006.202.00:41:19.09#ibcon#*before return 0, iclass 34, count 2 2006.202.00:41:19.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:19.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:19.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.202.00:41:19.09#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:19.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:19.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:19.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:19.21#ibcon#enter wrdev, iclass 34, count 0 2006.202.00:41:19.21#ibcon#first serial, iclass 34, count 0 2006.202.00:41:19.21#ibcon#enter sib2, iclass 34, count 0 2006.202.00:41:19.21#ibcon#flushed, iclass 34, count 0 2006.202.00:41:19.21#ibcon#about to write, iclass 34, count 0 2006.202.00:41:19.21#ibcon#wrote, iclass 34, count 0 2006.202.00:41:19.21#ibcon#about to read 3, iclass 34, count 0 2006.202.00:41:19.23#ibcon#read 3, iclass 34, count 0 2006.202.00:41:19.23#ibcon#about to read 4, iclass 34, count 0 2006.202.00:41:19.23#ibcon#read 4, iclass 34, count 0 2006.202.00:41:19.23#ibcon#about to read 5, iclass 34, count 0 2006.202.00:41:19.23#ibcon#read 5, iclass 34, count 0 2006.202.00:41:19.23#ibcon#about to read 6, iclass 34, count 0 2006.202.00:41:19.23#ibcon#read 6, iclass 34, count 0 2006.202.00:41:19.23#ibcon#end of sib2, iclass 34, count 0 2006.202.00:41:19.23#ibcon#*mode == 0, iclass 34, count 0 2006.202.00:41:19.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.00:41:19.23#ibcon#[25=USB\r\n] 2006.202.00:41:19.23#ibcon#*before write, iclass 34, count 0 2006.202.00:41:19.23#ibcon#enter sib2, iclass 34, count 0 2006.202.00:41:19.23#ibcon#flushed, iclass 34, count 0 2006.202.00:41:19.23#ibcon#about to write, iclass 34, count 0 2006.202.00:41:19.23#ibcon#wrote, iclass 34, count 0 2006.202.00:41:19.23#ibcon#about to read 3, iclass 34, count 0 2006.202.00:41:19.26#ibcon#read 3, iclass 34, count 0 2006.202.00:41:19.26#ibcon#about to read 4, iclass 34, count 0 2006.202.00:41:19.26#ibcon#read 4, iclass 34, count 0 2006.202.00:41:19.26#ibcon#about to read 5, iclass 34, count 0 2006.202.00:41:19.26#ibcon#read 5, iclass 34, count 0 2006.202.00:41:19.26#ibcon#about to read 6, iclass 34, count 0 2006.202.00:41:19.26#ibcon#read 6, iclass 34, count 0 2006.202.00:41:19.26#ibcon#end of sib2, iclass 34, count 0 2006.202.00:41:19.26#ibcon#*after write, iclass 34, count 0 2006.202.00:41:19.26#ibcon#*before return 0, iclass 34, count 0 2006.202.00:41:19.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:19.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:19.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.00:41:19.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.00:41:19.26$vck44/valo=7,864.99 2006.202.00:41:19.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.202.00:41:19.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.202.00:41:19.26#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:19.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:19.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:19.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:19.26#ibcon#enter wrdev, iclass 36, count 0 2006.202.00:41:19.26#ibcon#first serial, iclass 36, count 0 2006.202.00:41:19.26#ibcon#enter sib2, iclass 36, count 0 2006.202.00:41:19.26#ibcon#flushed, iclass 36, count 0 2006.202.00:41:19.26#ibcon#about to write, iclass 36, count 0 2006.202.00:41:19.26#ibcon#wrote, iclass 36, count 0 2006.202.00:41:19.26#ibcon#about to read 3, iclass 36, count 0 2006.202.00:41:19.28#ibcon#read 3, iclass 36, count 0 2006.202.00:41:19.28#ibcon#about to read 4, iclass 36, count 0 2006.202.00:41:19.28#ibcon#read 4, iclass 36, count 0 2006.202.00:41:19.28#ibcon#about to read 5, iclass 36, count 0 2006.202.00:41:19.28#ibcon#read 5, iclass 36, count 0 2006.202.00:41:19.28#ibcon#about to read 6, iclass 36, count 0 2006.202.00:41:19.28#ibcon#read 6, iclass 36, count 0 2006.202.00:41:19.28#ibcon#end of sib2, iclass 36, count 0 2006.202.00:41:19.28#ibcon#*mode == 0, iclass 36, count 0 2006.202.00:41:19.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.00:41:19.28#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.00:41:19.28#ibcon#*before write, iclass 36, count 0 2006.202.00:41:19.28#ibcon#enter sib2, iclass 36, count 0 2006.202.00:41:19.28#ibcon#flushed, iclass 36, count 0 2006.202.00:41:19.28#ibcon#about to write, iclass 36, count 0 2006.202.00:41:19.28#ibcon#wrote, iclass 36, count 0 2006.202.00:41:19.28#ibcon#about to read 3, iclass 36, count 0 2006.202.00:41:19.32#ibcon#read 3, iclass 36, count 0 2006.202.00:41:19.32#ibcon#about to read 4, iclass 36, count 0 2006.202.00:41:19.32#ibcon#read 4, iclass 36, count 0 2006.202.00:41:19.32#ibcon#about to read 5, iclass 36, count 0 2006.202.00:41:19.32#ibcon#read 5, iclass 36, count 0 2006.202.00:41:19.32#ibcon#about to read 6, iclass 36, count 0 2006.202.00:41:19.32#ibcon#read 6, iclass 36, count 0 2006.202.00:41:19.32#ibcon#end of sib2, iclass 36, count 0 2006.202.00:41:19.32#ibcon#*after write, iclass 36, count 0 2006.202.00:41:19.32#ibcon#*before return 0, iclass 36, count 0 2006.202.00:41:19.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:19.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:19.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.00:41:19.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.00:41:19.32$vck44/va=7,5 2006.202.00:41:19.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.202.00:41:19.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.202.00:41:19.32#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:19.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:19.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:19.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:19.38#ibcon#enter wrdev, iclass 38, count 2 2006.202.00:41:19.38#ibcon#first serial, iclass 38, count 2 2006.202.00:41:19.38#ibcon#enter sib2, iclass 38, count 2 2006.202.00:41:19.38#ibcon#flushed, iclass 38, count 2 2006.202.00:41:19.38#ibcon#about to write, iclass 38, count 2 2006.202.00:41:19.38#ibcon#wrote, iclass 38, count 2 2006.202.00:41:19.38#ibcon#about to read 3, iclass 38, count 2 2006.202.00:41:19.40#ibcon#read 3, iclass 38, count 2 2006.202.00:41:19.40#ibcon#about to read 4, iclass 38, count 2 2006.202.00:41:19.40#ibcon#read 4, iclass 38, count 2 2006.202.00:41:19.40#ibcon#about to read 5, iclass 38, count 2 2006.202.00:41:19.40#ibcon#read 5, iclass 38, count 2 2006.202.00:41:19.40#ibcon#about to read 6, iclass 38, count 2 2006.202.00:41:19.40#ibcon#read 6, iclass 38, count 2 2006.202.00:41:19.40#ibcon#end of sib2, iclass 38, count 2 2006.202.00:41:19.40#ibcon#*mode == 0, iclass 38, count 2 2006.202.00:41:19.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.202.00:41:19.40#ibcon#[25=AT07-05\r\n] 2006.202.00:41:19.40#ibcon#*before write, iclass 38, count 2 2006.202.00:41:19.40#ibcon#enter sib2, iclass 38, count 2 2006.202.00:41:19.40#ibcon#flushed, iclass 38, count 2 2006.202.00:41:19.40#ibcon#about to write, iclass 38, count 2 2006.202.00:41:19.40#ibcon#wrote, iclass 38, count 2 2006.202.00:41:19.40#ibcon#about to read 3, iclass 38, count 2 2006.202.00:41:19.43#ibcon#read 3, iclass 38, count 2 2006.202.00:41:19.48#ibcon#about to read 4, iclass 38, count 2 2006.202.00:41:19.48#ibcon#read 4, iclass 38, count 2 2006.202.00:41:19.48#ibcon#about to read 5, iclass 38, count 2 2006.202.00:41:19.48#ibcon#read 5, iclass 38, count 2 2006.202.00:41:19.48#ibcon#about to read 6, iclass 38, count 2 2006.202.00:41:19.48#ibcon#read 6, iclass 38, count 2 2006.202.00:41:19.48#ibcon#end of sib2, iclass 38, count 2 2006.202.00:41:19.48#ibcon#*after write, iclass 38, count 2 2006.202.00:41:19.48#ibcon#*before return 0, iclass 38, count 2 2006.202.00:41:19.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:19.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:19.48#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.202.00:41:19.48#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:19.48#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:19.60#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:19.60#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:19.60#ibcon#enter wrdev, iclass 38, count 0 2006.202.00:41:19.60#ibcon#first serial, iclass 38, count 0 2006.202.00:41:19.60#ibcon#enter sib2, iclass 38, count 0 2006.202.00:41:19.60#ibcon#flushed, iclass 38, count 0 2006.202.00:41:19.60#ibcon#about to write, iclass 38, count 0 2006.202.00:41:19.60#ibcon#wrote, iclass 38, count 0 2006.202.00:41:19.60#ibcon#about to read 3, iclass 38, count 0 2006.202.00:41:19.62#ibcon#read 3, iclass 38, count 0 2006.202.00:41:19.62#ibcon#about to read 4, iclass 38, count 0 2006.202.00:41:19.62#ibcon#read 4, iclass 38, count 0 2006.202.00:41:19.62#ibcon#about to read 5, iclass 38, count 0 2006.202.00:41:19.62#ibcon#read 5, iclass 38, count 0 2006.202.00:41:19.62#ibcon#about to read 6, iclass 38, count 0 2006.202.00:41:19.62#ibcon#read 6, iclass 38, count 0 2006.202.00:41:19.62#ibcon#end of sib2, iclass 38, count 0 2006.202.00:41:19.62#ibcon#*mode == 0, iclass 38, count 0 2006.202.00:41:19.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.00:41:19.62#ibcon#[25=USB\r\n] 2006.202.00:41:19.62#ibcon#*before write, iclass 38, count 0 2006.202.00:41:19.62#ibcon#enter sib2, iclass 38, count 0 2006.202.00:41:19.62#ibcon#flushed, iclass 38, count 0 2006.202.00:41:19.62#ibcon#about to write, iclass 38, count 0 2006.202.00:41:19.62#ibcon#wrote, iclass 38, count 0 2006.202.00:41:19.62#ibcon#about to read 3, iclass 38, count 0 2006.202.00:41:19.65#ibcon#read 3, iclass 38, count 0 2006.202.00:41:19.65#ibcon#about to read 4, iclass 38, count 0 2006.202.00:41:19.65#ibcon#read 4, iclass 38, count 0 2006.202.00:41:19.65#ibcon#about to read 5, iclass 38, count 0 2006.202.00:41:19.65#ibcon#read 5, iclass 38, count 0 2006.202.00:41:19.65#ibcon#about to read 6, iclass 38, count 0 2006.202.00:41:19.65#ibcon#read 6, iclass 38, count 0 2006.202.00:41:19.65#ibcon#end of sib2, iclass 38, count 0 2006.202.00:41:19.65#ibcon#*after write, iclass 38, count 0 2006.202.00:41:19.65#ibcon#*before return 0, iclass 38, count 0 2006.202.00:41:19.65#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:19.65#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:19.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.00:41:19.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.00:41:19.65$vck44/valo=8,884.99 2006.202.00:41:19.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.202.00:41:19.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.202.00:41:19.65#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:19.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:19.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:19.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:19.65#ibcon#enter wrdev, iclass 40, count 0 2006.202.00:41:19.65#ibcon#first serial, iclass 40, count 0 2006.202.00:41:19.65#ibcon#enter sib2, iclass 40, count 0 2006.202.00:41:19.65#ibcon#flushed, iclass 40, count 0 2006.202.00:41:19.65#ibcon#about to write, iclass 40, count 0 2006.202.00:41:19.65#ibcon#wrote, iclass 40, count 0 2006.202.00:41:19.65#ibcon#about to read 3, iclass 40, count 0 2006.202.00:41:19.67#ibcon#read 3, iclass 40, count 0 2006.202.00:41:19.67#ibcon#about to read 4, iclass 40, count 0 2006.202.00:41:19.67#ibcon#read 4, iclass 40, count 0 2006.202.00:41:19.67#ibcon#about to read 5, iclass 40, count 0 2006.202.00:41:19.67#ibcon#read 5, iclass 40, count 0 2006.202.00:41:19.67#ibcon#about to read 6, iclass 40, count 0 2006.202.00:41:19.67#ibcon#read 6, iclass 40, count 0 2006.202.00:41:19.67#ibcon#end of sib2, iclass 40, count 0 2006.202.00:41:19.67#ibcon#*mode == 0, iclass 40, count 0 2006.202.00:41:19.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.00:41:19.67#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.00:41:19.67#ibcon#*before write, iclass 40, count 0 2006.202.00:41:19.67#ibcon#enter sib2, iclass 40, count 0 2006.202.00:41:19.67#ibcon#flushed, iclass 40, count 0 2006.202.00:41:19.67#ibcon#about to write, iclass 40, count 0 2006.202.00:41:19.67#ibcon#wrote, iclass 40, count 0 2006.202.00:41:19.67#ibcon#about to read 3, iclass 40, count 0 2006.202.00:41:19.71#ibcon#read 3, iclass 40, count 0 2006.202.00:41:19.71#ibcon#about to read 4, iclass 40, count 0 2006.202.00:41:19.71#ibcon#read 4, iclass 40, count 0 2006.202.00:41:19.71#ibcon#about to read 5, iclass 40, count 0 2006.202.00:41:19.71#ibcon#read 5, iclass 40, count 0 2006.202.00:41:19.71#ibcon#about to read 6, iclass 40, count 0 2006.202.00:41:19.71#ibcon#read 6, iclass 40, count 0 2006.202.00:41:19.71#ibcon#end of sib2, iclass 40, count 0 2006.202.00:41:19.71#ibcon#*after write, iclass 40, count 0 2006.202.00:41:19.71#ibcon#*before return 0, iclass 40, count 0 2006.202.00:41:19.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:19.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:19.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.00:41:19.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.00:41:19.71$vck44/va=8,4 2006.202.00:41:19.71#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.202.00:41:19.71#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.202.00:41:19.71#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:19.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:19.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:19.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:19.77#ibcon#enter wrdev, iclass 4, count 2 2006.202.00:41:19.77#ibcon#first serial, iclass 4, count 2 2006.202.00:41:19.77#ibcon#enter sib2, iclass 4, count 2 2006.202.00:41:19.77#ibcon#flushed, iclass 4, count 2 2006.202.00:41:19.77#ibcon#about to write, iclass 4, count 2 2006.202.00:41:19.77#ibcon#wrote, iclass 4, count 2 2006.202.00:41:19.77#ibcon#about to read 3, iclass 4, count 2 2006.202.00:41:19.79#ibcon#read 3, iclass 4, count 2 2006.202.00:41:19.79#ibcon#about to read 4, iclass 4, count 2 2006.202.00:41:19.79#ibcon#read 4, iclass 4, count 2 2006.202.00:41:19.79#ibcon#about to read 5, iclass 4, count 2 2006.202.00:41:19.79#ibcon#read 5, iclass 4, count 2 2006.202.00:41:19.79#ibcon#about to read 6, iclass 4, count 2 2006.202.00:41:19.79#ibcon#read 6, iclass 4, count 2 2006.202.00:41:19.79#ibcon#end of sib2, iclass 4, count 2 2006.202.00:41:19.79#ibcon#*mode == 0, iclass 4, count 2 2006.202.00:41:19.79#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.202.00:41:19.79#ibcon#[25=AT08-04\r\n] 2006.202.00:41:19.79#ibcon#*before write, iclass 4, count 2 2006.202.00:41:19.79#ibcon#enter sib2, iclass 4, count 2 2006.202.00:41:19.79#ibcon#flushed, iclass 4, count 2 2006.202.00:41:19.79#ibcon#about to write, iclass 4, count 2 2006.202.00:41:19.79#ibcon#wrote, iclass 4, count 2 2006.202.00:41:19.79#ibcon#about to read 3, iclass 4, count 2 2006.202.00:41:19.82#ibcon#read 3, iclass 4, count 2 2006.202.00:41:19.82#ibcon#about to read 4, iclass 4, count 2 2006.202.00:41:19.82#ibcon#read 4, iclass 4, count 2 2006.202.00:41:19.82#ibcon#about to read 5, iclass 4, count 2 2006.202.00:41:19.82#ibcon#read 5, iclass 4, count 2 2006.202.00:41:19.82#ibcon#about to read 6, iclass 4, count 2 2006.202.00:41:19.82#ibcon#read 6, iclass 4, count 2 2006.202.00:41:19.82#ibcon#end of sib2, iclass 4, count 2 2006.202.00:41:19.82#ibcon#*after write, iclass 4, count 2 2006.202.00:41:19.82#ibcon#*before return 0, iclass 4, count 2 2006.202.00:41:19.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:19.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:19.82#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.202.00:41:19.82#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:19.82#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:19.94#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:19.94#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:19.94#ibcon#enter wrdev, iclass 4, count 0 2006.202.00:41:19.94#ibcon#first serial, iclass 4, count 0 2006.202.00:41:19.94#ibcon#enter sib2, iclass 4, count 0 2006.202.00:41:19.94#ibcon#flushed, iclass 4, count 0 2006.202.00:41:19.94#ibcon#about to write, iclass 4, count 0 2006.202.00:41:19.94#ibcon#wrote, iclass 4, count 0 2006.202.00:41:19.94#ibcon#about to read 3, iclass 4, count 0 2006.202.00:41:19.96#ibcon#read 3, iclass 4, count 0 2006.202.00:41:19.96#ibcon#about to read 4, iclass 4, count 0 2006.202.00:41:19.96#ibcon#read 4, iclass 4, count 0 2006.202.00:41:19.96#ibcon#about to read 5, iclass 4, count 0 2006.202.00:41:19.96#ibcon#read 5, iclass 4, count 0 2006.202.00:41:19.96#ibcon#about to read 6, iclass 4, count 0 2006.202.00:41:19.96#ibcon#read 6, iclass 4, count 0 2006.202.00:41:19.96#ibcon#end of sib2, iclass 4, count 0 2006.202.00:41:19.96#ibcon#*mode == 0, iclass 4, count 0 2006.202.00:41:19.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.00:41:19.96#ibcon#[25=USB\r\n] 2006.202.00:41:19.96#ibcon#*before write, iclass 4, count 0 2006.202.00:41:19.96#ibcon#enter sib2, iclass 4, count 0 2006.202.00:41:19.96#ibcon#flushed, iclass 4, count 0 2006.202.00:41:19.96#ibcon#about to write, iclass 4, count 0 2006.202.00:41:19.96#ibcon#wrote, iclass 4, count 0 2006.202.00:41:19.96#ibcon#about to read 3, iclass 4, count 0 2006.202.00:41:19.99#ibcon#read 3, iclass 4, count 0 2006.202.00:41:19.99#ibcon#about to read 4, iclass 4, count 0 2006.202.00:41:19.99#ibcon#read 4, iclass 4, count 0 2006.202.00:41:19.99#ibcon#about to read 5, iclass 4, count 0 2006.202.00:41:19.99#ibcon#read 5, iclass 4, count 0 2006.202.00:41:19.99#ibcon#about to read 6, iclass 4, count 0 2006.202.00:41:19.99#ibcon#read 6, iclass 4, count 0 2006.202.00:41:19.99#ibcon#end of sib2, iclass 4, count 0 2006.202.00:41:19.99#ibcon#*after write, iclass 4, count 0 2006.202.00:41:19.99#ibcon#*before return 0, iclass 4, count 0 2006.202.00:41:19.99#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:19.99#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:19.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.00:41:19.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.00:41:19.99$vck44/vblo=1,629.99 2006.202.00:41:19.99#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.202.00:41:19.99#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.202.00:41:19.99#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:19.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:19.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:19.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:19.99#ibcon#enter wrdev, iclass 6, count 0 2006.202.00:41:19.99#ibcon#first serial, iclass 6, count 0 2006.202.00:41:19.99#ibcon#enter sib2, iclass 6, count 0 2006.202.00:41:19.99#ibcon#flushed, iclass 6, count 0 2006.202.00:41:19.99#ibcon#about to write, iclass 6, count 0 2006.202.00:41:19.99#ibcon#wrote, iclass 6, count 0 2006.202.00:41:19.99#ibcon#about to read 3, iclass 6, count 0 2006.202.00:41:20.01#ibcon#read 3, iclass 6, count 0 2006.202.00:41:20.01#ibcon#about to read 4, iclass 6, count 0 2006.202.00:41:20.01#ibcon#read 4, iclass 6, count 0 2006.202.00:41:20.01#ibcon#about to read 5, iclass 6, count 0 2006.202.00:41:20.01#ibcon#read 5, iclass 6, count 0 2006.202.00:41:20.01#ibcon#about to read 6, iclass 6, count 0 2006.202.00:41:20.01#ibcon#read 6, iclass 6, count 0 2006.202.00:41:20.01#ibcon#end of sib2, iclass 6, count 0 2006.202.00:41:20.01#ibcon#*mode == 0, iclass 6, count 0 2006.202.00:41:20.01#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.00:41:20.01#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.00:41:20.01#ibcon#*before write, iclass 6, count 0 2006.202.00:41:20.01#ibcon#enter sib2, iclass 6, count 0 2006.202.00:41:20.01#ibcon#flushed, iclass 6, count 0 2006.202.00:41:20.01#ibcon#about to write, iclass 6, count 0 2006.202.00:41:20.01#ibcon#wrote, iclass 6, count 0 2006.202.00:41:20.01#ibcon#about to read 3, iclass 6, count 0 2006.202.00:41:20.05#ibcon#read 3, iclass 6, count 0 2006.202.00:41:20.05#ibcon#about to read 4, iclass 6, count 0 2006.202.00:41:20.05#ibcon#read 4, iclass 6, count 0 2006.202.00:41:20.05#ibcon#about to read 5, iclass 6, count 0 2006.202.00:41:20.05#ibcon#read 5, iclass 6, count 0 2006.202.00:41:20.05#ibcon#about to read 6, iclass 6, count 0 2006.202.00:41:20.05#ibcon#read 6, iclass 6, count 0 2006.202.00:41:20.05#ibcon#end of sib2, iclass 6, count 0 2006.202.00:41:20.05#ibcon#*after write, iclass 6, count 0 2006.202.00:41:20.05#ibcon#*before return 0, iclass 6, count 0 2006.202.00:41:20.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:20.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:20.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.00:41:20.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.00:41:20.05$vck44/vb=1,4 2006.202.00:41:20.05#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.202.00:41:20.05#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.202.00:41:20.05#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:20.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.202.00:41:20.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.202.00:41:20.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.202.00:41:20.05#ibcon#enter wrdev, iclass 10, count 2 2006.202.00:41:20.05#ibcon#first serial, iclass 10, count 2 2006.202.00:41:20.05#ibcon#enter sib2, iclass 10, count 2 2006.202.00:41:20.05#ibcon#flushed, iclass 10, count 2 2006.202.00:41:20.05#ibcon#about to write, iclass 10, count 2 2006.202.00:41:20.05#ibcon#wrote, iclass 10, count 2 2006.202.00:41:20.05#ibcon#about to read 3, iclass 10, count 2 2006.202.00:41:20.07#ibcon#read 3, iclass 10, count 2 2006.202.00:41:20.07#ibcon#about to read 4, iclass 10, count 2 2006.202.00:41:20.07#ibcon#read 4, iclass 10, count 2 2006.202.00:41:20.07#ibcon#about to read 5, iclass 10, count 2 2006.202.00:41:20.07#ibcon#read 5, iclass 10, count 2 2006.202.00:41:20.07#ibcon#about to read 6, iclass 10, count 2 2006.202.00:41:20.07#ibcon#read 6, iclass 10, count 2 2006.202.00:41:20.07#ibcon#end of sib2, iclass 10, count 2 2006.202.00:41:20.07#ibcon#*mode == 0, iclass 10, count 2 2006.202.00:41:20.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.202.00:41:20.07#ibcon#[27=AT01-04\r\n] 2006.202.00:41:20.07#ibcon#*before write, iclass 10, count 2 2006.202.00:41:20.07#ibcon#enter sib2, iclass 10, count 2 2006.202.00:41:20.07#ibcon#flushed, iclass 10, count 2 2006.202.00:41:20.07#ibcon#about to write, iclass 10, count 2 2006.202.00:41:20.07#ibcon#wrote, iclass 10, count 2 2006.202.00:41:20.07#ibcon#about to read 3, iclass 10, count 2 2006.202.00:41:20.10#ibcon#read 3, iclass 10, count 2 2006.202.00:41:20.10#ibcon#about to read 4, iclass 10, count 2 2006.202.00:41:20.10#ibcon#read 4, iclass 10, count 2 2006.202.00:41:20.10#ibcon#about to read 5, iclass 10, count 2 2006.202.00:41:20.10#ibcon#read 5, iclass 10, count 2 2006.202.00:41:20.10#ibcon#about to read 6, iclass 10, count 2 2006.202.00:41:20.10#ibcon#read 6, iclass 10, count 2 2006.202.00:41:20.10#ibcon#end of sib2, iclass 10, count 2 2006.202.00:41:20.10#ibcon#*after write, iclass 10, count 2 2006.202.00:41:20.10#ibcon#*before return 0, iclass 10, count 2 2006.202.00:41:20.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.202.00:41:20.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.202.00:41:20.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.202.00:41:20.10#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:20.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.202.00:41:20.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.202.00:41:20.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.202.00:41:20.22#ibcon#enter wrdev, iclass 10, count 0 2006.202.00:41:20.22#ibcon#first serial, iclass 10, count 0 2006.202.00:41:20.22#ibcon#enter sib2, iclass 10, count 0 2006.202.00:41:20.22#ibcon#flushed, iclass 10, count 0 2006.202.00:41:20.22#ibcon#about to write, iclass 10, count 0 2006.202.00:41:20.22#ibcon#wrote, iclass 10, count 0 2006.202.00:41:20.22#ibcon#about to read 3, iclass 10, count 0 2006.202.00:41:20.24#ibcon#read 3, iclass 10, count 0 2006.202.00:41:20.24#ibcon#about to read 4, iclass 10, count 0 2006.202.00:41:20.24#ibcon#read 4, iclass 10, count 0 2006.202.00:41:20.24#ibcon#about to read 5, iclass 10, count 0 2006.202.00:41:20.24#ibcon#read 5, iclass 10, count 0 2006.202.00:41:20.24#ibcon#about to read 6, iclass 10, count 0 2006.202.00:41:20.24#ibcon#read 6, iclass 10, count 0 2006.202.00:41:20.24#ibcon#end of sib2, iclass 10, count 0 2006.202.00:41:20.24#ibcon#*mode == 0, iclass 10, count 0 2006.202.00:41:20.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.00:41:20.24#ibcon#[27=USB\r\n] 2006.202.00:41:20.24#ibcon#*before write, iclass 10, count 0 2006.202.00:41:20.24#ibcon#enter sib2, iclass 10, count 0 2006.202.00:41:20.24#ibcon#flushed, iclass 10, count 0 2006.202.00:41:20.24#ibcon#about to write, iclass 10, count 0 2006.202.00:41:20.24#ibcon#wrote, iclass 10, count 0 2006.202.00:41:20.24#ibcon#about to read 3, iclass 10, count 0 2006.202.00:41:20.27#ibcon#read 3, iclass 10, count 0 2006.202.00:41:20.27#ibcon#about to read 4, iclass 10, count 0 2006.202.00:41:20.27#ibcon#read 4, iclass 10, count 0 2006.202.00:41:20.27#ibcon#about to read 5, iclass 10, count 0 2006.202.00:41:20.27#ibcon#read 5, iclass 10, count 0 2006.202.00:41:20.27#ibcon#about to read 6, iclass 10, count 0 2006.202.00:41:20.27#ibcon#read 6, iclass 10, count 0 2006.202.00:41:20.27#ibcon#end of sib2, iclass 10, count 0 2006.202.00:41:20.27#ibcon#*after write, iclass 10, count 0 2006.202.00:41:20.27#ibcon#*before return 0, iclass 10, count 0 2006.202.00:41:20.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.202.00:41:20.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.202.00:41:20.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.00:41:20.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.00:41:20.27$vck44/vblo=2,634.99 2006.202.00:41:20.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.202.00:41:20.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.202.00:41:20.27#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:20.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:20.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:20.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:20.27#ibcon#enter wrdev, iclass 12, count 0 2006.202.00:41:20.27#ibcon#first serial, iclass 12, count 0 2006.202.00:41:20.27#ibcon#enter sib2, iclass 12, count 0 2006.202.00:41:20.27#ibcon#flushed, iclass 12, count 0 2006.202.00:41:20.27#ibcon#about to write, iclass 12, count 0 2006.202.00:41:20.27#ibcon#wrote, iclass 12, count 0 2006.202.00:41:20.27#ibcon#about to read 3, iclass 12, count 0 2006.202.00:41:20.29#ibcon#read 3, iclass 12, count 0 2006.202.00:41:20.29#ibcon#about to read 4, iclass 12, count 0 2006.202.00:41:20.29#ibcon#read 4, iclass 12, count 0 2006.202.00:41:20.29#ibcon#about to read 5, iclass 12, count 0 2006.202.00:41:20.29#ibcon#read 5, iclass 12, count 0 2006.202.00:41:20.29#ibcon#about to read 6, iclass 12, count 0 2006.202.00:41:20.29#ibcon#read 6, iclass 12, count 0 2006.202.00:41:20.29#ibcon#end of sib2, iclass 12, count 0 2006.202.00:41:20.29#ibcon#*mode == 0, iclass 12, count 0 2006.202.00:41:20.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.00:41:20.29#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.00:41:20.29#ibcon#*before write, iclass 12, count 0 2006.202.00:41:20.29#ibcon#enter sib2, iclass 12, count 0 2006.202.00:41:20.29#ibcon#flushed, iclass 12, count 0 2006.202.00:41:20.29#ibcon#about to write, iclass 12, count 0 2006.202.00:41:20.29#ibcon#wrote, iclass 12, count 0 2006.202.00:41:20.29#ibcon#about to read 3, iclass 12, count 0 2006.202.00:41:20.33#ibcon#read 3, iclass 12, count 0 2006.202.00:41:20.33#ibcon#about to read 4, iclass 12, count 0 2006.202.00:41:20.33#ibcon#read 4, iclass 12, count 0 2006.202.00:41:20.33#ibcon#about to read 5, iclass 12, count 0 2006.202.00:41:20.33#ibcon#read 5, iclass 12, count 0 2006.202.00:41:20.33#ibcon#about to read 6, iclass 12, count 0 2006.202.00:41:20.33#ibcon#read 6, iclass 12, count 0 2006.202.00:41:20.33#ibcon#end of sib2, iclass 12, count 0 2006.202.00:41:20.33#ibcon#*after write, iclass 12, count 0 2006.202.00:41:20.33#ibcon#*before return 0, iclass 12, count 0 2006.202.00:41:20.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:20.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.202.00:41:20.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.00:41:20.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.00:41:20.33$vck44/vb=2,5 2006.202.00:41:20.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.202.00:41:20.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.202.00:41:20.33#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:20.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:20.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:20.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:20.39#ibcon#enter wrdev, iclass 14, count 2 2006.202.00:41:20.39#ibcon#first serial, iclass 14, count 2 2006.202.00:41:20.39#ibcon#enter sib2, iclass 14, count 2 2006.202.00:41:20.39#ibcon#flushed, iclass 14, count 2 2006.202.00:41:20.39#ibcon#about to write, iclass 14, count 2 2006.202.00:41:20.39#ibcon#wrote, iclass 14, count 2 2006.202.00:41:20.39#ibcon#about to read 3, iclass 14, count 2 2006.202.00:41:20.41#ibcon#read 3, iclass 14, count 2 2006.202.00:41:20.41#ibcon#about to read 4, iclass 14, count 2 2006.202.00:41:20.41#ibcon#read 4, iclass 14, count 2 2006.202.00:41:20.41#ibcon#about to read 5, iclass 14, count 2 2006.202.00:41:20.41#ibcon#read 5, iclass 14, count 2 2006.202.00:41:20.41#ibcon#about to read 6, iclass 14, count 2 2006.202.00:41:20.41#ibcon#read 6, iclass 14, count 2 2006.202.00:41:20.41#ibcon#end of sib2, iclass 14, count 2 2006.202.00:41:20.41#ibcon#*mode == 0, iclass 14, count 2 2006.202.00:41:20.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.202.00:41:20.41#ibcon#[27=AT02-05\r\n] 2006.202.00:41:20.41#ibcon#*before write, iclass 14, count 2 2006.202.00:41:20.41#ibcon#enter sib2, iclass 14, count 2 2006.202.00:41:20.41#ibcon#flushed, iclass 14, count 2 2006.202.00:41:20.41#ibcon#about to write, iclass 14, count 2 2006.202.00:41:20.41#ibcon#wrote, iclass 14, count 2 2006.202.00:41:20.41#ibcon#about to read 3, iclass 14, count 2 2006.202.00:41:20.44#ibcon#read 3, iclass 14, count 2 2006.202.00:41:20.44#ibcon#about to read 4, iclass 14, count 2 2006.202.00:41:20.44#ibcon#read 4, iclass 14, count 2 2006.202.00:41:20.44#ibcon#about to read 5, iclass 14, count 2 2006.202.00:41:20.44#ibcon#read 5, iclass 14, count 2 2006.202.00:41:20.44#ibcon#about to read 6, iclass 14, count 2 2006.202.00:41:20.44#ibcon#read 6, iclass 14, count 2 2006.202.00:41:20.44#ibcon#end of sib2, iclass 14, count 2 2006.202.00:41:20.44#ibcon#*after write, iclass 14, count 2 2006.202.00:41:20.44#ibcon#*before return 0, iclass 14, count 2 2006.202.00:41:20.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:20.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.202.00:41:20.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.202.00:41:20.44#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:20.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:20.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:20.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:20.56#ibcon#enter wrdev, iclass 14, count 0 2006.202.00:41:20.56#ibcon#first serial, iclass 14, count 0 2006.202.00:41:20.56#ibcon#enter sib2, iclass 14, count 0 2006.202.00:41:20.56#ibcon#flushed, iclass 14, count 0 2006.202.00:41:20.56#ibcon#about to write, iclass 14, count 0 2006.202.00:41:20.56#ibcon#wrote, iclass 14, count 0 2006.202.00:41:20.56#ibcon#about to read 3, iclass 14, count 0 2006.202.00:41:20.58#ibcon#read 3, iclass 14, count 0 2006.202.00:41:20.58#ibcon#about to read 4, iclass 14, count 0 2006.202.00:41:20.58#ibcon#read 4, iclass 14, count 0 2006.202.00:41:20.58#ibcon#about to read 5, iclass 14, count 0 2006.202.00:41:20.58#ibcon#read 5, iclass 14, count 0 2006.202.00:41:20.58#ibcon#about to read 6, iclass 14, count 0 2006.202.00:41:20.58#ibcon#read 6, iclass 14, count 0 2006.202.00:41:20.58#ibcon#end of sib2, iclass 14, count 0 2006.202.00:41:20.58#ibcon#*mode == 0, iclass 14, count 0 2006.202.00:41:20.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.00:41:20.58#ibcon#[27=USB\r\n] 2006.202.00:41:20.58#ibcon#*before write, iclass 14, count 0 2006.202.00:41:20.58#ibcon#enter sib2, iclass 14, count 0 2006.202.00:41:20.58#ibcon#flushed, iclass 14, count 0 2006.202.00:41:20.58#ibcon#about to write, iclass 14, count 0 2006.202.00:41:20.58#ibcon#wrote, iclass 14, count 0 2006.202.00:41:20.58#ibcon#about to read 3, iclass 14, count 0 2006.202.00:41:20.61#ibcon#read 3, iclass 14, count 0 2006.202.00:41:20.61#ibcon#about to read 4, iclass 14, count 0 2006.202.00:41:20.61#ibcon#read 4, iclass 14, count 0 2006.202.00:41:20.61#ibcon#about to read 5, iclass 14, count 0 2006.202.00:41:20.61#ibcon#read 5, iclass 14, count 0 2006.202.00:41:20.61#ibcon#about to read 6, iclass 14, count 0 2006.202.00:41:20.61#ibcon#read 6, iclass 14, count 0 2006.202.00:41:20.61#ibcon#end of sib2, iclass 14, count 0 2006.202.00:41:20.61#ibcon#*after write, iclass 14, count 0 2006.202.00:41:20.61#ibcon#*before return 0, iclass 14, count 0 2006.202.00:41:20.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:20.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.202.00:41:20.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.00:41:20.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.00:41:20.61$vck44/vblo=3,649.99 2006.202.00:41:20.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.202.00:41:20.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.202.00:41:20.61#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:20.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:20.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:20.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:20.61#ibcon#enter wrdev, iclass 16, count 0 2006.202.00:41:20.61#ibcon#first serial, iclass 16, count 0 2006.202.00:41:20.61#ibcon#enter sib2, iclass 16, count 0 2006.202.00:41:20.61#ibcon#flushed, iclass 16, count 0 2006.202.00:41:20.61#ibcon#about to write, iclass 16, count 0 2006.202.00:41:20.61#ibcon#wrote, iclass 16, count 0 2006.202.00:41:20.61#ibcon#about to read 3, iclass 16, count 0 2006.202.00:41:20.63#ibcon#read 3, iclass 16, count 0 2006.202.00:41:20.63#ibcon#about to read 4, iclass 16, count 0 2006.202.00:41:20.63#ibcon#read 4, iclass 16, count 0 2006.202.00:41:20.63#ibcon#about to read 5, iclass 16, count 0 2006.202.00:41:20.63#ibcon#read 5, iclass 16, count 0 2006.202.00:41:20.63#ibcon#about to read 6, iclass 16, count 0 2006.202.00:41:20.63#ibcon#read 6, iclass 16, count 0 2006.202.00:41:20.63#ibcon#end of sib2, iclass 16, count 0 2006.202.00:41:20.63#ibcon#*mode == 0, iclass 16, count 0 2006.202.00:41:20.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.00:41:20.63#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.00:41:20.63#ibcon#*before write, iclass 16, count 0 2006.202.00:41:20.63#ibcon#enter sib2, iclass 16, count 0 2006.202.00:41:20.63#ibcon#flushed, iclass 16, count 0 2006.202.00:41:20.63#ibcon#about to write, iclass 16, count 0 2006.202.00:41:20.63#ibcon#wrote, iclass 16, count 0 2006.202.00:41:20.63#ibcon#about to read 3, iclass 16, count 0 2006.202.00:41:20.67#ibcon#read 3, iclass 16, count 0 2006.202.00:41:20.67#ibcon#about to read 4, iclass 16, count 0 2006.202.00:41:20.67#ibcon#read 4, iclass 16, count 0 2006.202.00:41:20.67#ibcon#about to read 5, iclass 16, count 0 2006.202.00:41:20.67#ibcon#read 5, iclass 16, count 0 2006.202.00:41:20.67#ibcon#about to read 6, iclass 16, count 0 2006.202.00:41:20.67#ibcon#read 6, iclass 16, count 0 2006.202.00:41:20.67#ibcon#end of sib2, iclass 16, count 0 2006.202.00:41:20.67#ibcon#*after write, iclass 16, count 0 2006.202.00:41:20.67#ibcon#*before return 0, iclass 16, count 0 2006.202.00:41:20.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:20.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.202.00:41:20.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.00:41:20.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.00:41:20.67$vck44/vb=3,4 2006.202.00:41:20.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.202.00:41:20.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.202.00:41:20.67#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:20.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:20.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:20.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:20.73#ibcon#enter wrdev, iclass 18, count 2 2006.202.00:41:20.73#ibcon#first serial, iclass 18, count 2 2006.202.00:41:20.73#ibcon#enter sib2, iclass 18, count 2 2006.202.00:41:20.73#ibcon#flushed, iclass 18, count 2 2006.202.00:41:20.73#ibcon#about to write, iclass 18, count 2 2006.202.00:41:20.73#ibcon#wrote, iclass 18, count 2 2006.202.00:41:20.73#ibcon#about to read 3, iclass 18, count 2 2006.202.00:41:20.75#ibcon#read 3, iclass 18, count 2 2006.202.00:41:20.75#ibcon#about to read 4, iclass 18, count 2 2006.202.00:41:20.75#ibcon#read 4, iclass 18, count 2 2006.202.00:41:20.75#ibcon#about to read 5, iclass 18, count 2 2006.202.00:41:20.75#ibcon#read 5, iclass 18, count 2 2006.202.00:41:20.75#ibcon#about to read 6, iclass 18, count 2 2006.202.00:41:20.75#ibcon#read 6, iclass 18, count 2 2006.202.00:41:20.75#ibcon#end of sib2, iclass 18, count 2 2006.202.00:41:20.75#ibcon#*mode == 0, iclass 18, count 2 2006.202.00:41:20.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.202.00:41:20.75#ibcon#[27=AT03-04\r\n] 2006.202.00:41:20.75#ibcon#*before write, iclass 18, count 2 2006.202.00:41:20.75#ibcon#enter sib2, iclass 18, count 2 2006.202.00:41:20.75#ibcon#flushed, iclass 18, count 2 2006.202.00:41:20.75#ibcon#about to write, iclass 18, count 2 2006.202.00:41:20.75#ibcon#wrote, iclass 18, count 2 2006.202.00:41:20.75#ibcon#about to read 3, iclass 18, count 2 2006.202.00:41:20.78#ibcon#read 3, iclass 18, count 2 2006.202.00:41:20.78#ibcon#about to read 4, iclass 18, count 2 2006.202.00:41:20.78#ibcon#read 4, iclass 18, count 2 2006.202.00:41:20.78#ibcon#about to read 5, iclass 18, count 2 2006.202.00:41:20.78#ibcon#read 5, iclass 18, count 2 2006.202.00:41:20.78#ibcon#about to read 6, iclass 18, count 2 2006.202.00:41:20.78#ibcon#read 6, iclass 18, count 2 2006.202.00:41:20.78#ibcon#end of sib2, iclass 18, count 2 2006.202.00:41:20.78#ibcon#*after write, iclass 18, count 2 2006.202.00:41:20.78#ibcon#*before return 0, iclass 18, count 2 2006.202.00:41:20.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:20.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.202.00:41:20.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.202.00:41:20.78#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:20.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:20.80#abcon#<5=/03 2.1 4.4 20.401001001.5\r\n> 2006.202.00:41:20.82#abcon#{5=INTERFACE CLEAR} 2006.202.00:41:20.88#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:41:20.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:20.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:20.90#ibcon#enter wrdev, iclass 18, count 0 2006.202.00:41:20.90#ibcon#first serial, iclass 18, count 0 2006.202.00:41:20.90#ibcon#enter sib2, iclass 18, count 0 2006.202.00:41:20.90#ibcon#flushed, iclass 18, count 0 2006.202.00:41:20.90#ibcon#about to write, iclass 18, count 0 2006.202.00:41:20.90#ibcon#wrote, iclass 18, count 0 2006.202.00:41:20.90#ibcon#about to read 3, iclass 18, count 0 2006.202.00:41:20.92#ibcon#read 3, iclass 18, count 0 2006.202.00:41:20.92#ibcon#about to read 4, iclass 18, count 0 2006.202.00:41:20.92#ibcon#read 4, iclass 18, count 0 2006.202.00:41:20.92#ibcon#about to read 5, iclass 18, count 0 2006.202.00:41:20.92#ibcon#read 5, iclass 18, count 0 2006.202.00:41:20.92#ibcon#about to read 6, iclass 18, count 0 2006.202.00:41:20.92#ibcon#read 6, iclass 18, count 0 2006.202.00:41:20.92#ibcon#end of sib2, iclass 18, count 0 2006.202.00:41:20.92#ibcon#*mode == 0, iclass 18, count 0 2006.202.00:41:20.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.00:41:20.92#ibcon#[27=USB\r\n] 2006.202.00:41:20.92#ibcon#*before write, iclass 18, count 0 2006.202.00:41:20.92#ibcon#enter sib2, iclass 18, count 0 2006.202.00:41:20.92#ibcon#flushed, iclass 18, count 0 2006.202.00:41:20.92#ibcon#about to write, iclass 18, count 0 2006.202.00:41:20.92#ibcon#wrote, iclass 18, count 0 2006.202.00:41:20.92#ibcon#about to read 3, iclass 18, count 0 2006.202.00:41:20.95#ibcon#read 3, iclass 18, count 0 2006.202.00:41:20.95#ibcon#about to read 4, iclass 18, count 0 2006.202.00:41:20.95#ibcon#read 4, iclass 18, count 0 2006.202.00:41:20.95#ibcon#about to read 5, iclass 18, count 0 2006.202.00:41:20.95#ibcon#read 5, iclass 18, count 0 2006.202.00:41:20.95#ibcon#about to read 6, iclass 18, count 0 2006.202.00:41:20.95#ibcon#read 6, iclass 18, count 0 2006.202.00:41:20.95#ibcon#end of sib2, iclass 18, count 0 2006.202.00:41:20.95#ibcon#*after write, iclass 18, count 0 2006.202.00:41:20.95#ibcon#*before return 0, iclass 18, count 0 2006.202.00:41:20.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:20.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.202.00:41:20.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.00:41:20.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.00:41:20.95$vck44/vblo=4,679.99 2006.202.00:41:20.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.202.00:41:20.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.202.00:41:20.95#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:20.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:20.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:20.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:20.95#ibcon#enter wrdev, iclass 24, count 0 2006.202.00:41:20.95#ibcon#first serial, iclass 24, count 0 2006.202.00:41:20.95#ibcon#enter sib2, iclass 24, count 0 2006.202.00:41:20.95#ibcon#flushed, iclass 24, count 0 2006.202.00:41:20.95#ibcon#about to write, iclass 24, count 0 2006.202.00:41:20.95#ibcon#wrote, iclass 24, count 0 2006.202.00:41:20.95#ibcon#about to read 3, iclass 24, count 0 2006.202.00:41:20.97#ibcon#read 3, iclass 24, count 0 2006.202.00:41:20.97#ibcon#about to read 4, iclass 24, count 0 2006.202.00:41:20.97#ibcon#read 4, iclass 24, count 0 2006.202.00:41:20.97#ibcon#about to read 5, iclass 24, count 0 2006.202.00:41:20.97#ibcon#read 5, iclass 24, count 0 2006.202.00:41:20.97#ibcon#about to read 6, iclass 24, count 0 2006.202.00:41:20.97#ibcon#read 6, iclass 24, count 0 2006.202.00:41:20.97#ibcon#end of sib2, iclass 24, count 0 2006.202.00:41:20.97#ibcon#*mode == 0, iclass 24, count 0 2006.202.00:41:20.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.00:41:20.97#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.00:41:20.97#ibcon#*before write, iclass 24, count 0 2006.202.00:41:20.97#ibcon#enter sib2, iclass 24, count 0 2006.202.00:41:20.97#ibcon#flushed, iclass 24, count 0 2006.202.00:41:20.97#ibcon#about to write, iclass 24, count 0 2006.202.00:41:20.97#ibcon#wrote, iclass 24, count 0 2006.202.00:41:20.97#ibcon#about to read 3, iclass 24, count 0 2006.202.00:41:21.01#ibcon#read 3, iclass 24, count 0 2006.202.00:41:21.01#ibcon#about to read 4, iclass 24, count 0 2006.202.00:41:21.01#ibcon#read 4, iclass 24, count 0 2006.202.00:41:21.01#ibcon#about to read 5, iclass 24, count 0 2006.202.00:41:21.01#ibcon#read 5, iclass 24, count 0 2006.202.00:41:21.01#ibcon#about to read 6, iclass 24, count 0 2006.202.00:41:21.01#ibcon#read 6, iclass 24, count 0 2006.202.00:41:21.01#ibcon#end of sib2, iclass 24, count 0 2006.202.00:41:21.01#ibcon#*after write, iclass 24, count 0 2006.202.00:41:21.01#ibcon#*before return 0, iclass 24, count 0 2006.202.00:41:21.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:21.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:41:21.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.00:41:21.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.00:41:21.01$vck44/vb=4,5 2006.202.00:41:21.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.202.00:41:21.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.202.00:41:21.01#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:21.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:21.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:21.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:21.07#ibcon#enter wrdev, iclass 26, count 2 2006.202.00:41:21.07#ibcon#first serial, iclass 26, count 2 2006.202.00:41:21.07#ibcon#enter sib2, iclass 26, count 2 2006.202.00:41:21.07#ibcon#flushed, iclass 26, count 2 2006.202.00:41:21.07#ibcon#about to write, iclass 26, count 2 2006.202.00:41:21.07#ibcon#wrote, iclass 26, count 2 2006.202.00:41:21.07#ibcon#about to read 3, iclass 26, count 2 2006.202.00:41:21.09#ibcon#read 3, iclass 26, count 2 2006.202.00:41:21.09#ibcon#about to read 4, iclass 26, count 2 2006.202.00:41:21.09#ibcon#read 4, iclass 26, count 2 2006.202.00:41:21.09#ibcon#about to read 5, iclass 26, count 2 2006.202.00:41:21.09#ibcon#read 5, iclass 26, count 2 2006.202.00:41:21.09#ibcon#about to read 6, iclass 26, count 2 2006.202.00:41:21.09#ibcon#read 6, iclass 26, count 2 2006.202.00:41:21.09#ibcon#end of sib2, iclass 26, count 2 2006.202.00:41:21.09#ibcon#*mode == 0, iclass 26, count 2 2006.202.00:41:21.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.202.00:41:21.09#ibcon#[27=AT04-05\r\n] 2006.202.00:41:21.09#ibcon#*before write, iclass 26, count 2 2006.202.00:41:21.09#ibcon#enter sib2, iclass 26, count 2 2006.202.00:41:21.09#ibcon#flushed, iclass 26, count 2 2006.202.00:41:21.09#ibcon#about to write, iclass 26, count 2 2006.202.00:41:21.09#ibcon#wrote, iclass 26, count 2 2006.202.00:41:21.09#ibcon#about to read 3, iclass 26, count 2 2006.202.00:41:21.12#ibcon#read 3, iclass 26, count 2 2006.202.00:41:21.12#ibcon#about to read 4, iclass 26, count 2 2006.202.00:41:21.12#ibcon#read 4, iclass 26, count 2 2006.202.00:41:21.12#ibcon#about to read 5, iclass 26, count 2 2006.202.00:41:21.12#ibcon#read 5, iclass 26, count 2 2006.202.00:41:21.12#ibcon#about to read 6, iclass 26, count 2 2006.202.00:41:21.12#ibcon#read 6, iclass 26, count 2 2006.202.00:41:21.12#ibcon#end of sib2, iclass 26, count 2 2006.202.00:41:21.12#ibcon#*after write, iclass 26, count 2 2006.202.00:41:21.12#ibcon#*before return 0, iclass 26, count 2 2006.202.00:41:21.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:21.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.202.00:41:21.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.202.00:41:21.12#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:21.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:21.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:21.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:21.24#ibcon#enter wrdev, iclass 26, count 0 2006.202.00:41:21.24#ibcon#first serial, iclass 26, count 0 2006.202.00:41:21.24#ibcon#enter sib2, iclass 26, count 0 2006.202.00:41:21.24#ibcon#flushed, iclass 26, count 0 2006.202.00:41:21.24#ibcon#about to write, iclass 26, count 0 2006.202.00:41:21.24#ibcon#wrote, iclass 26, count 0 2006.202.00:41:21.24#ibcon#about to read 3, iclass 26, count 0 2006.202.00:41:21.26#ibcon#read 3, iclass 26, count 0 2006.202.00:41:21.26#ibcon#about to read 4, iclass 26, count 0 2006.202.00:41:21.26#ibcon#read 4, iclass 26, count 0 2006.202.00:41:21.26#ibcon#about to read 5, iclass 26, count 0 2006.202.00:41:21.26#ibcon#read 5, iclass 26, count 0 2006.202.00:41:21.26#ibcon#about to read 6, iclass 26, count 0 2006.202.00:41:21.26#ibcon#read 6, iclass 26, count 0 2006.202.00:41:21.26#ibcon#end of sib2, iclass 26, count 0 2006.202.00:41:21.26#ibcon#*mode == 0, iclass 26, count 0 2006.202.00:41:21.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.00:41:21.26#ibcon#[27=USB\r\n] 2006.202.00:41:21.26#ibcon#*before write, iclass 26, count 0 2006.202.00:41:21.26#ibcon#enter sib2, iclass 26, count 0 2006.202.00:41:21.26#ibcon#flushed, iclass 26, count 0 2006.202.00:41:21.26#ibcon#about to write, iclass 26, count 0 2006.202.00:41:21.26#ibcon#wrote, iclass 26, count 0 2006.202.00:41:21.26#ibcon#about to read 3, iclass 26, count 0 2006.202.00:41:21.29#ibcon#read 3, iclass 26, count 0 2006.202.00:41:21.29#ibcon#about to read 4, iclass 26, count 0 2006.202.00:41:21.29#ibcon#read 4, iclass 26, count 0 2006.202.00:41:21.29#ibcon#about to read 5, iclass 26, count 0 2006.202.00:41:21.29#ibcon#read 5, iclass 26, count 0 2006.202.00:41:21.29#ibcon#about to read 6, iclass 26, count 0 2006.202.00:41:21.29#ibcon#read 6, iclass 26, count 0 2006.202.00:41:21.29#ibcon#end of sib2, iclass 26, count 0 2006.202.00:41:21.29#ibcon#*after write, iclass 26, count 0 2006.202.00:41:21.29#ibcon#*before return 0, iclass 26, count 0 2006.202.00:41:21.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:21.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.202.00:41:21.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.00:41:21.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.00:41:21.29$vck44/vblo=5,709.99 2006.202.00:41:21.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.202.00:41:21.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.202.00:41:21.29#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:21.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:21.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:21.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:21.29#ibcon#enter wrdev, iclass 28, count 0 2006.202.00:41:21.29#ibcon#first serial, iclass 28, count 0 2006.202.00:41:21.29#ibcon#enter sib2, iclass 28, count 0 2006.202.00:41:21.29#ibcon#flushed, iclass 28, count 0 2006.202.00:41:21.29#ibcon#about to write, iclass 28, count 0 2006.202.00:41:21.29#ibcon#wrote, iclass 28, count 0 2006.202.00:41:21.29#ibcon#about to read 3, iclass 28, count 0 2006.202.00:41:21.31#ibcon#read 3, iclass 28, count 0 2006.202.00:41:21.31#ibcon#about to read 4, iclass 28, count 0 2006.202.00:41:21.31#ibcon#read 4, iclass 28, count 0 2006.202.00:41:21.31#ibcon#about to read 5, iclass 28, count 0 2006.202.00:41:21.31#ibcon#read 5, iclass 28, count 0 2006.202.00:41:21.31#ibcon#about to read 6, iclass 28, count 0 2006.202.00:41:21.31#ibcon#read 6, iclass 28, count 0 2006.202.00:41:21.31#ibcon#end of sib2, iclass 28, count 0 2006.202.00:41:21.31#ibcon#*mode == 0, iclass 28, count 0 2006.202.00:41:21.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.00:41:21.31#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.00:41:21.31#ibcon#*before write, iclass 28, count 0 2006.202.00:41:21.31#ibcon#enter sib2, iclass 28, count 0 2006.202.00:41:21.31#ibcon#flushed, iclass 28, count 0 2006.202.00:41:21.31#ibcon#about to write, iclass 28, count 0 2006.202.00:41:21.31#ibcon#wrote, iclass 28, count 0 2006.202.00:41:21.31#ibcon#about to read 3, iclass 28, count 0 2006.202.00:41:21.35#ibcon#read 3, iclass 28, count 0 2006.202.00:41:21.35#ibcon#about to read 4, iclass 28, count 0 2006.202.00:41:21.35#ibcon#read 4, iclass 28, count 0 2006.202.00:41:21.35#ibcon#about to read 5, iclass 28, count 0 2006.202.00:41:21.35#ibcon#read 5, iclass 28, count 0 2006.202.00:41:21.35#ibcon#about to read 6, iclass 28, count 0 2006.202.00:41:21.35#ibcon#read 6, iclass 28, count 0 2006.202.00:41:21.35#ibcon#end of sib2, iclass 28, count 0 2006.202.00:41:21.35#ibcon#*after write, iclass 28, count 0 2006.202.00:41:21.35#ibcon#*before return 0, iclass 28, count 0 2006.202.00:41:21.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:21.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.202.00:41:21.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.00:41:21.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.00:41:21.35$vck44/vb=5,4 2006.202.00:41:21.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.202.00:41:21.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.202.00:41:21.35#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:21.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:21.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:21.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:21.41#ibcon#enter wrdev, iclass 30, count 2 2006.202.00:41:21.41#ibcon#first serial, iclass 30, count 2 2006.202.00:41:21.41#ibcon#enter sib2, iclass 30, count 2 2006.202.00:41:21.41#ibcon#flushed, iclass 30, count 2 2006.202.00:41:21.41#ibcon#about to write, iclass 30, count 2 2006.202.00:41:21.41#ibcon#wrote, iclass 30, count 2 2006.202.00:41:21.41#ibcon#about to read 3, iclass 30, count 2 2006.202.00:41:21.43#ibcon#read 3, iclass 30, count 2 2006.202.00:41:21.43#ibcon#about to read 4, iclass 30, count 2 2006.202.00:41:21.43#ibcon#read 4, iclass 30, count 2 2006.202.00:41:21.43#ibcon#about to read 5, iclass 30, count 2 2006.202.00:41:21.43#ibcon#read 5, iclass 30, count 2 2006.202.00:41:21.43#ibcon#about to read 6, iclass 30, count 2 2006.202.00:41:21.43#ibcon#read 6, iclass 30, count 2 2006.202.00:41:21.43#ibcon#end of sib2, iclass 30, count 2 2006.202.00:41:21.43#ibcon#*mode == 0, iclass 30, count 2 2006.202.00:41:21.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.202.00:41:21.43#ibcon#[27=AT05-04\r\n] 2006.202.00:41:21.43#ibcon#*before write, iclass 30, count 2 2006.202.00:41:21.43#ibcon#enter sib2, iclass 30, count 2 2006.202.00:41:21.43#ibcon#flushed, iclass 30, count 2 2006.202.00:41:21.43#ibcon#about to write, iclass 30, count 2 2006.202.00:41:21.43#ibcon#wrote, iclass 30, count 2 2006.202.00:41:21.43#ibcon#about to read 3, iclass 30, count 2 2006.202.00:41:21.46#ibcon#read 3, iclass 30, count 2 2006.202.00:41:21.46#ibcon#about to read 4, iclass 30, count 2 2006.202.00:41:21.46#ibcon#read 4, iclass 30, count 2 2006.202.00:41:21.46#ibcon#about to read 5, iclass 30, count 2 2006.202.00:41:21.46#ibcon#read 5, iclass 30, count 2 2006.202.00:41:21.46#ibcon#about to read 6, iclass 30, count 2 2006.202.00:41:21.46#ibcon#read 6, iclass 30, count 2 2006.202.00:41:21.46#ibcon#end of sib2, iclass 30, count 2 2006.202.00:41:21.46#ibcon#*after write, iclass 30, count 2 2006.202.00:41:21.46#ibcon#*before return 0, iclass 30, count 2 2006.202.00:41:21.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:21.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.202.00:41:21.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.202.00:41:21.46#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:21.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:21.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:21.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:21.58#ibcon#enter wrdev, iclass 30, count 0 2006.202.00:41:21.58#ibcon#first serial, iclass 30, count 0 2006.202.00:41:21.58#ibcon#enter sib2, iclass 30, count 0 2006.202.00:41:21.58#ibcon#flushed, iclass 30, count 0 2006.202.00:41:21.58#ibcon#about to write, iclass 30, count 0 2006.202.00:41:21.58#ibcon#wrote, iclass 30, count 0 2006.202.00:41:21.58#ibcon#about to read 3, iclass 30, count 0 2006.202.00:41:21.60#ibcon#read 3, iclass 30, count 0 2006.202.00:41:21.60#ibcon#about to read 4, iclass 30, count 0 2006.202.00:41:21.60#ibcon#read 4, iclass 30, count 0 2006.202.00:41:21.60#ibcon#about to read 5, iclass 30, count 0 2006.202.00:41:21.60#ibcon#read 5, iclass 30, count 0 2006.202.00:41:21.60#ibcon#about to read 6, iclass 30, count 0 2006.202.00:41:21.60#ibcon#read 6, iclass 30, count 0 2006.202.00:41:21.60#ibcon#end of sib2, iclass 30, count 0 2006.202.00:41:21.60#ibcon#*mode == 0, iclass 30, count 0 2006.202.00:41:21.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.00:41:21.60#ibcon#[27=USB\r\n] 2006.202.00:41:21.60#ibcon#*before write, iclass 30, count 0 2006.202.00:41:21.60#ibcon#enter sib2, iclass 30, count 0 2006.202.00:41:21.60#ibcon#flushed, iclass 30, count 0 2006.202.00:41:21.60#ibcon#about to write, iclass 30, count 0 2006.202.00:41:21.60#ibcon#wrote, iclass 30, count 0 2006.202.00:41:21.60#ibcon#about to read 3, iclass 30, count 0 2006.202.00:41:21.63#ibcon#read 3, iclass 30, count 0 2006.202.00:41:21.63#ibcon#about to read 4, iclass 30, count 0 2006.202.00:41:21.63#ibcon#read 4, iclass 30, count 0 2006.202.00:41:21.63#ibcon#about to read 5, iclass 30, count 0 2006.202.00:41:21.63#ibcon#read 5, iclass 30, count 0 2006.202.00:41:21.63#ibcon#about to read 6, iclass 30, count 0 2006.202.00:41:21.63#ibcon#read 6, iclass 30, count 0 2006.202.00:41:21.63#ibcon#end of sib2, iclass 30, count 0 2006.202.00:41:21.63#ibcon#*after write, iclass 30, count 0 2006.202.00:41:21.63#ibcon#*before return 0, iclass 30, count 0 2006.202.00:41:21.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:21.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.202.00:41:21.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.00:41:21.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.00:41:21.63$vck44/vblo=6,719.99 2006.202.00:41:21.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.202.00:41:21.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.202.00:41:21.63#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:21.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:21.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:21.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:21.63#ibcon#enter wrdev, iclass 32, count 0 2006.202.00:41:21.63#ibcon#first serial, iclass 32, count 0 2006.202.00:41:21.63#ibcon#enter sib2, iclass 32, count 0 2006.202.00:41:21.63#ibcon#flushed, iclass 32, count 0 2006.202.00:41:21.63#ibcon#about to write, iclass 32, count 0 2006.202.00:41:21.63#ibcon#wrote, iclass 32, count 0 2006.202.00:41:21.63#ibcon#about to read 3, iclass 32, count 0 2006.202.00:41:21.65#ibcon#read 3, iclass 32, count 0 2006.202.00:41:21.65#ibcon#about to read 4, iclass 32, count 0 2006.202.00:41:21.65#ibcon#read 4, iclass 32, count 0 2006.202.00:41:21.65#ibcon#about to read 5, iclass 32, count 0 2006.202.00:41:21.65#ibcon#read 5, iclass 32, count 0 2006.202.00:41:21.65#ibcon#about to read 6, iclass 32, count 0 2006.202.00:41:21.65#ibcon#read 6, iclass 32, count 0 2006.202.00:41:21.65#ibcon#end of sib2, iclass 32, count 0 2006.202.00:41:21.65#ibcon#*mode == 0, iclass 32, count 0 2006.202.00:41:21.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.00:41:21.65#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.00:41:21.65#ibcon#*before write, iclass 32, count 0 2006.202.00:41:21.65#ibcon#enter sib2, iclass 32, count 0 2006.202.00:41:21.65#ibcon#flushed, iclass 32, count 0 2006.202.00:41:21.65#ibcon#about to write, iclass 32, count 0 2006.202.00:41:21.65#ibcon#wrote, iclass 32, count 0 2006.202.00:41:21.65#ibcon#about to read 3, iclass 32, count 0 2006.202.00:41:21.69#ibcon#read 3, iclass 32, count 0 2006.202.00:41:21.69#ibcon#about to read 4, iclass 32, count 0 2006.202.00:41:21.69#ibcon#read 4, iclass 32, count 0 2006.202.00:41:21.69#ibcon#about to read 5, iclass 32, count 0 2006.202.00:41:21.69#ibcon#read 5, iclass 32, count 0 2006.202.00:41:21.69#ibcon#about to read 6, iclass 32, count 0 2006.202.00:41:21.69#ibcon#read 6, iclass 32, count 0 2006.202.00:41:21.69#ibcon#end of sib2, iclass 32, count 0 2006.202.00:41:21.69#ibcon#*after write, iclass 32, count 0 2006.202.00:41:21.69#ibcon#*before return 0, iclass 32, count 0 2006.202.00:41:21.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:21.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.202.00:41:21.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.00:41:21.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.00:41:21.69$vck44/vb=6,4 2006.202.00:41:21.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.202.00:41:21.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.202.00:41:21.69#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:21.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:21.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:21.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:21.75#ibcon#enter wrdev, iclass 34, count 2 2006.202.00:41:21.75#ibcon#first serial, iclass 34, count 2 2006.202.00:41:21.75#ibcon#enter sib2, iclass 34, count 2 2006.202.00:41:21.75#ibcon#flushed, iclass 34, count 2 2006.202.00:41:21.75#ibcon#about to write, iclass 34, count 2 2006.202.00:41:21.75#ibcon#wrote, iclass 34, count 2 2006.202.00:41:21.75#ibcon#about to read 3, iclass 34, count 2 2006.202.00:41:21.77#ibcon#read 3, iclass 34, count 2 2006.202.00:41:21.77#ibcon#about to read 4, iclass 34, count 2 2006.202.00:41:21.77#ibcon#read 4, iclass 34, count 2 2006.202.00:41:21.77#ibcon#about to read 5, iclass 34, count 2 2006.202.00:41:21.77#ibcon#read 5, iclass 34, count 2 2006.202.00:41:21.77#ibcon#about to read 6, iclass 34, count 2 2006.202.00:41:21.77#ibcon#read 6, iclass 34, count 2 2006.202.00:41:21.77#ibcon#end of sib2, iclass 34, count 2 2006.202.00:41:21.77#ibcon#*mode == 0, iclass 34, count 2 2006.202.00:41:21.77#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.202.00:41:21.77#ibcon#[27=AT06-04\r\n] 2006.202.00:41:21.77#ibcon#*before write, iclass 34, count 2 2006.202.00:41:21.77#ibcon#enter sib2, iclass 34, count 2 2006.202.00:41:21.77#ibcon#flushed, iclass 34, count 2 2006.202.00:41:21.77#ibcon#about to write, iclass 34, count 2 2006.202.00:41:21.77#ibcon#wrote, iclass 34, count 2 2006.202.00:41:21.77#ibcon#about to read 3, iclass 34, count 2 2006.202.00:41:21.80#ibcon#read 3, iclass 34, count 2 2006.202.00:41:21.80#ibcon#about to read 4, iclass 34, count 2 2006.202.00:41:21.80#ibcon#read 4, iclass 34, count 2 2006.202.00:41:21.80#ibcon#about to read 5, iclass 34, count 2 2006.202.00:41:21.80#ibcon#read 5, iclass 34, count 2 2006.202.00:41:21.80#ibcon#about to read 6, iclass 34, count 2 2006.202.00:41:21.80#ibcon#read 6, iclass 34, count 2 2006.202.00:41:21.80#ibcon#end of sib2, iclass 34, count 2 2006.202.00:41:21.80#ibcon#*after write, iclass 34, count 2 2006.202.00:41:21.80#ibcon#*before return 0, iclass 34, count 2 2006.202.00:41:21.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:21.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.202.00:41:21.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.202.00:41:21.80#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:21.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:21.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:21.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:21.92#ibcon#enter wrdev, iclass 34, count 0 2006.202.00:41:21.92#ibcon#first serial, iclass 34, count 0 2006.202.00:41:21.92#ibcon#enter sib2, iclass 34, count 0 2006.202.00:41:21.92#ibcon#flushed, iclass 34, count 0 2006.202.00:41:21.92#ibcon#about to write, iclass 34, count 0 2006.202.00:41:21.92#ibcon#wrote, iclass 34, count 0 2006.202.00:41:21.92#ibcon#about to read 3, iclass 34, count 0 2006.202.00:41:21.94#ibcon#read 3, iclass 34, count 0 2006.202.00:41:21.94#ibcon#about to read 4, iclass 34, count 0 2006.202.00:41:21.94#ibcon#read 4, iclass 34, count 0 2006.202.00:41:21.94#ibcon#about to read 5, iclass 34, count 0 2006.202.00:41:21.94#ibcon#read 5, iclass 34, count 0 2006.202.00:41:21.94#ibcon#about to read 6, iclass 34, count 0 2006.202.00:41:21.94#ibcon#read 6, iclass 34, count 0 2006.202.00:41:21.94#ibcon#end of sib2, iclass 34, count 0 2006.202.00:41:21.94#ibcon#*mode == 0, iclass 34, count 0 2006.202.00:41:21.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.00:41:21.94#ibcon#[27=USB\r\n] 2006.202.00:41:21.94#ibcon#*before write, iclass 34, count 0 2006.202.00:41:21.94#ibcon#enter sib2, iclass 34, count 0 2006.202.00:41:21.94#ibcon#flushed, iclass 34, count 0 2006.202.00:41:21.94#ibcon#about to write, iclass 34, count 0 2006.202.00:41:21.94#ibcon#wrote, iclass 34, count 0 2006.202.00:41:21.94#ibcon#about to read 3, iclass 34, count 0 2006.202.00:41:21.97#ibcon#read 3, iclass 34, count 0 2006.202.00:41:21.97#ibcon#about to read 4, iclass 34, count 0 2006.202.00:41:21.97#ibcon#read 4, iclass 34, count 0 2006.202.00:41:21.97#ibcon#about to read 5, iclass 34, count 0 2006.202.00:41:21.97#ibcon#read 5, iclass 34, count 0 2006.202.00:41:21.97#ibcon#about to read 6, iclass 34, count 0 2006.202.00:41:21.97#ibcon#read 6, iclass 34, count 0 2006.202.00:41:21.97#ibcon#end of sib2, iclass 34, count 0 2006.202.00:41:21.97#ibcon#*after write, iclass 34, count 0 2006.202.00:41:21.97#ibcon#*before return 0, iclass 34, count 0 2006.202.00:41:21.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:21.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.202.00:41:21.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.00:41:21.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.00:41:21.97$vck44/vblo=7,734.99 2006.202.00:41:21.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.202.00:41:21.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.202.00:41:21.97#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:21.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:21.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:21.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:21.97#ibcon#enter wrdev, iclass 36, count 0 2006.202.00:41:21.97#ibcon#first serial, iclass 36, count 0 2006.202.00:41:21.97#ibcon#enter sib2, iclass 36, count 0 2006.202.00:41:21.97#ibcon#flushed, iclass 36, count 0 2006.202.00:41:21.97#ibcon#about to write, iclass 36, count 0 2006.202.00:41:21.97#ibcon#wrote, iclass 36, count 0 2006.202.00:41:21.97#ibcon#about to read 3, iclass 36, count 0 2006.202.00:41:21.99#ibcon#read 3, iclass 36, count 0 2006.202.00:41:21.99#ibcon#about to read 4, iclass 36, count 0 2006.202.00:41:21.99#ibcon#read 4, iclass 36, count 0 2006.202.00:41:21.99#ibcon#about to read 5, iclass 36, count 0 2006.202.00:41:21.99#ibcon#read 5, iclass 36, count 0 2006.202.00:41:21.99#ibcon#about to read 6, iclass 36, count 0 2006.202.00:41:21.99#ibcon#read 6, iclass 36, count 0 2006.202.00:41:21.99#ibcon#end of sib2, iclass 36, count 0 2006.202.00:41:21.99#ibcon#*mode == 0, iclass 36, count 0 2006.202.00:41:21.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.00:41:21.99#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.00:41:21.99#ibcon#*before write, iclass 36, count 0 2006.202.00:41:21.99#ibcon#enter sib2, iclass 36, count 0 2006.202.00:41:21.99#ibcon#flushed, iclass 36, count 0 2006.202.00:41:21.99#ibcon#about to write, iclass 36, count 0 2006.202.00:41:21.99#ibcon#wrote, iclass 36, count 0 2006.202.00:41:21.99#ibcon#about to read 3, iclass 36, count 0 2006.202.00:41:22.03#ibcon#read 3, iclass 36, count 0 2006.202.00:41:22.03#ibcon#about to read 4, iclass 36, count 0 2006.202.00:41:22.03#ibcon#read 4, iclass 36, count 0 2006.202.00:41:22.03#ibcon#about to read 5, iclass 36, count 0 2006.202.00:41:22.03#ibcon#read 5, iclass 36, count 0 2006.202.00:41:22.03#ibcon#about to read 6, iclass 36, count 0 2006.202.00:41:22.03#ibcon#read 6, iclass 36, count 0 2006.202.00:41:22.03#ibcon#end of sib2, iclass 36, count 0 2006.202.00:41:22.03#ibcon#*after write, iclass 36, count 0 2006.202.00:41:22.03#ibcon#*before return 0, iclass 36, count 0 2006.202.00:41:22.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:22.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.202.00:41:22.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.00:41:22.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.00:41:22.03$vck44/vb=7,4 2006.202.00:41:22.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.202.00:41:22.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.202.00:41:22.03#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:22.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:22.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:22.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:22.09#ibcon#enter wrdev, iclass 38, count 2 2006.202.00:41:22.09#ibcon#first serial, iclass 38, count 2 2006.202.00:41:22.09#ibcon#enter sib2, iclass 38, count 2 2006.202.00:41:22.09#ibcon#flushed, iclass 38, count 2 2006.202.00:41:22.09#ibcon#about to write, iclass 38, count 2 2006.202.00:41:22.09#ibcon#wrote, iclass 38, count 2 2006.202.00:41:22.09#ibcon#about to read 3, iclass 38, count 2 2006.202.00:41:22.11#ibcon#read 3, iclass 38, count 2 2006.202.00:41:22.11#ibcon#about to read 4, iclass 38, count 2 2006.202.00:41:22.11#ibcon#read 4, iclass 38, count 2 2006.202.00:41:22.11#ibcon#about to read 5, iclass 38, count 2 2006.202.00:41:22.11#ibcon#read 5, iclass 38, count 2 2006.202.00:41:22.11#ibcon#about to read 6, iclass 38, count 2 2006.202.00:41:22.11#ibcon#read 6, iclass 38, count 2 2006.202.00:41:22.11#ibcon#end of sib2, iclass 38, count 2 2006.202.00:41:22.11#ibcon#*mode == 0, iclass 38, count 2 2006.202.00:41:22.11#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.202.00:41:22.11#ibcon#[27=AT07-04\r\n] 2006.202.00:41:22.11#ibcon#*before write, iclass 38, count 2 2006.202.00:41:22.11#ibcon#enter sib2, iclass 38, count 2 2006.202.00:41:22.11#ibcon#flushed, iclass 38, count 2 2006.202.00:41:22.11#ibcon#about to write, iclass 38, count 2 2006.202.00:41:22.11#ibcon#wrote, iclass 38, count 2 2006.202.00:41:22.11#ibcon#about to read 3, iclass 38, count 2 2006.202.00:41:22.14#ibcon#read 3, iclass 38, count 2 2006.202.00:41:22.14#ibcon#about to read 4, iclass 38, count 2 2006.202.00:41:22.14#ibcon#read 4, iclass 38, count 2 2006.202.00:41:22.14#ibcon#about to read 5, iclass 38, count 2 2006.202.00:41:22.14#ibcon#read 5, iclass 38, count 2 2006.202.00:41:22.14#ibcon#about to read 6, iclass 38, count 2 2006.202.00:41:22.14#ibcon#read 6, iclass 38, count 2 2006.202.00:41:22.14#ibcon#end of sib2, iclass 38, count 2 2006.202.00:41:22.14#ibcon#*after write, iclass 38, count 2 2006.202.00:41:22.14#ibcon#*before return 0, iclass 38, count 2 2006.202.00:41:22.14#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:22.14#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.202.00:41:22.14#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.202.00:41:22.14#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:22.14#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:22.26#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:22.26#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:22.26#ibcon#enter wrdev, iclass 38, count 0 2006.202.00:41:22.26#ibcon#first serial, iclass 38, count 0 2006.202.00:41:22.26#ibcon#enter sib2, iclass 38, count 0 2006.202.00:41:22.26#ibcon#flushed, iclass 38, count 0 2006.202.00:41:22.26#ibcon#about to write, iclass 38, count 0 2006.202.00:41:22.26#ibcon#wrote, iclass 38, count 0 2006.202.00:41:22.26#ibcon#about to read 3, iclass 38, count 0 2006.202.00:41:22.28#ibcon#read 3, iclass 38, count 0 2006.202.00:41:22.28#ibcon#about to read 4, iclass 38, count 0 2006.202.00:41:22.28#ibcon#read 4, iclass 38, count 0 2006.202.00:41:22.28#ibcon#about to read 5, iclass 38, count 0 2006.202.00:41:22.28#ibcon#read 5, iclass 38, count 0 2006.202.00:41:22.28#ibcon#about to read 6, iclass 38, count 0 2006.202.00:41:22.28#ibcon#read 6, iclass 38, count 0 2006.202.00:41:22.28#ibcon#end of sib2, iclass 38, count 0 2006.202.00:41:22.28#ibcon#*mode == 0, iclass 38, count 0 2006.202.00:41:22.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.00:41:22.28#ibcon#[27=USB\r\n] 2006.202.00:41:22.28#ibcon#*before write, iclass 38, count 0 2006.202.00:41:22.28#ibcon#enter sib2, iclass 38, count 0 2006.202.00:41:22.28#ibcon#flushed, iclass 38, count 0 2006.202.00:41:22.28#ibcon#about to write, iclass 38, count 0 2006.202.00:41:22.28#ibcon#wrote, iclass 38, count 0 2006.202.00:41:22.28#ibcon#about to read 3, iclass 38, count 0 2006.202.00:41:22.31#ibcon#read 3, iclass 38, count 0 2006.202.00:41:22.31#ibcon#about to read 4, iclass 38, count 0 2006.202.00:41:22.31#ibcon#read 4, iclass 38, count 0 2006.202.00:41:22.31#ibcon#about to read 5, iclass 38, count 0 2006.202.00:41:22.31#ibcon#read 5, iclass 38, count 0 2006.202.00:41:22.31#ibcon#about to read 6, iclass 38, count 0 2006.202.00:41:22.31#ibcon#read 6, iclass 38, count 0 2006.202.00:41:22.31#ibcon#end of sib2, iclass 38, count 0 2006.202.00:41:22.31#ibcon#*after write, iclass 38, count 0 2006.202.00:41:22.31#ibcon#*before return 0, iclass 38, count 0 2006.202.00:41:22.31#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:22.31#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.202.00:41:22.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.00:41:22.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.00:41:22.31$vck44/vblo=8,744.99 2006.202.00:41:22.31#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.202.00:41:22.31#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.202.00:41:22.31#ibcon#ireg 17 cls_cnt 0 2006.202.00:41:22.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:22.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:22.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:22.31#ibcon#enter wrdev, iclass 40, count 0 2006.202.00:41:22.31#ibcon#first serial, iclass 40, count 0 2006.202.00:41:22.31#ibcon#enter sib2, iclass 40, count 0 2006.202.00:41:22.31#ibcon#flushed, iclass 40, count 0 2006.202.00:41:22.31#ibcon#about to write, iclass 40, count 0 2006.202.00:41:22.31#ibcon#wrote, iclass 40, count 0 2006.202.00:41:22.31#ibcon#about to read 3, iclass 40, count 0 2006.202.00:41:22.33#ibcon#read 3, iclass 40, count 0 2006.202.00:41:22.33#ibcon#about to read 4, iclass 40, count 0 2006.202.00:41:22.33#ibcon#read 4, iclass 40, count 0 2006.202.00:41:22.33#ibcon#about to read 5, iclass 40, count 0 2006.202.00:41:22.33#ibcon#read 5, iclass 40, count 0 2006.202.00:41:22.33#ibcon#about to read 6, iclass 40, count 0 2006.202.00:41:22.33#ibcon#read 6, iclass 40, count 0 2006.202.00:41:22.33#ibcon#end of sib2, iclass 40, count 0 2006.202.00:41:22.33#ibcon#*mode == 0, iclass 40, count 0 2006.202.00:41:22.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.00:41:22.33#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.00:41:22.33#ibcon#*before write, iclass 40, count 0 2006.202.00:41:22.33#ibcon#enter sib2, iclass 40, count 0 2006.202.00:41:22.33#ibcon#flushed, iclass 40, count 0 2006.202.00:41:22.33#ibcon#about to write, iclass 40, count 0 2006.202.00:41:22.33#ibcon#wrote, iclass 40, count 0 2006.202.00:41:22.33#ibcon#about to read 3, iclass 40, count 0 2006.202.00:41:22.37#ibcon#read 3, iclass 40, count 0 2006.202.00:41:22.37#ibcon#about to read 4, iclass 40, count 0 2006.202.00:41:22.37#ibcon#read 4, iclass 40, count 0 2006.202.00:41:22.37#ibcon#about to read 5, iclass 40, count 0 2006.202.00:41:22.37#ibcon#read 5, iclass 40, count 0 2006.202.00:41:22.37#ibcon#about to read 6, iclass 40, count 0 2006.202.00:41:22.37#ibcon#read 6, iclass 40, count 0 2006.202.00:41:22.37#ibcon#end of sib2, iclass 40, count 0 2006.202.00:41:22.37#ibcon#*after write, iclass 40, count 0 2006.202.00:41:22.37#ibcon#*before return 0, iclass 40, count 0 2006.202.00:41:22.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:22.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.202.00:41:22.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.00:41:22.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.00:41:22.37$vck44/vb=8,4 2006.202.00:41:22.37#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.202.00:41:22.37#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.202.00:41:22.37#ibcon#ireg 11 cls_cnt 2 2006.202.00:41:22.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:22.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:22.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:22.43#ibcon#enter wrdev, iclass 4, count 2 2006.202.00:41:22.43#ibcon#first serial, iclass 4, count 2 2006.202.00:41:22.43#ibcon#enter sib2, iclass 4, count 2 2006.202.00:41:22.43#ibcon#flushed, iclass 4, count 2 2006.202.00:41:22.43#ibcon#about to write, iclass 4, count 2 2006.202.00:41:22.43#ibcon#wrote, iclass 4, count 2 2006.202.00:41:22.43#ibcon#about to read 3, iclass 4, count 2 2006.202.00:41:22.45#ibcon#read 3, iclass 4, count 2 2006.202.00:41:22.45#ibcon#about to read 4, iclass 4, count 2 2006.202.00:41:22.45#ibcon#read 4, iclass 4, count 2 2006.202.00:41:22.45#ibcon#about to read 5, iclass 4, count 2 2006.202.00:41:22.45#ibcon#read 5, iclass 4, count 2 2006.202.00:41:22.45#ibcon#about to read 6, iclass 4, count 2 2006.202.00:41:22.45#ibcon#read 6, iclass 4, count 2 2006.202.00:41:22.45#ibcon#end of sib2, iclass 4, count 2 2006.202.00:41:22.45#ibcon#*mode == 0, iclass 4, count 2 2006.202.00:41:22.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.202.00:41:22.45#ibcon#[27=AT08-04\r\n] 2006.202.00:41:22.45#ibcon#*before write, iclass 4, count 2 2006.202.00:41:22.45#ibcon#enter sib2, iclass 4, count 2 2006.202.00:41:22.45#ibcon#flushed, iclass 4, count 2 2006.202.00:41:22.45#ibcon#about to write, iclass 4, count 2 2006.202.00:41:22.45#ibcon#wrote, iclass 4, count 2 2006.202.00:41:22.45#ibcon#about to read 3, iclass 4, count 2 2006.202.00:41:22.48#ibcon#read 3, iclass 4, count 2 2006.202.00:41:22.48#ibcon#about to read 4, iclass 4, count 2 2006.202.00:41:22.48#ibcon#read 4, iclass 4, count 2 2006.202.00:41:22.48#ibcon#about to read 5, iclass 4, count 2 2006.202.00:41:22.48#ibcon#read 5, iclass 4, count 2 2006.202.00:41:22.48#ibcon#about to read 6, iclass 4, count 2 2006.202.00:41:22.48#ibcon#read 6, iclass 4, count 2 2006.202.00:41:22.48#ibcon#end of sib2, iclass 4, count 2 2006.202.00:41:22.48#ibcon#*after write, iclass 4, count 2 2006.202.00:41:22.48#ibcon#*before return 0, iclass 4, count 2 2006.202.00:41:22.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:22.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.202.00:41:22.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.202.00:41:22.48#ibcon#ireg 7 cls_cnt 0 2006.202.00:41:22.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:22.60#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:22.60#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:22.60#ibcon#enter wrdev, iclass 4, count 0 2006.202.00:41:22.60#ibcon#first serial, iclass 4, count 0 2006.202.00:41:22.60#ibcon#enter sib2, iclass 4, count 0 2006.202.00:41:22.60#ibcon#flushed, iclass 4, count 0 2006.202.00:41:22.60#ibcon#about to write, iclass 4, count 0 2006.202.00:41:22.60#ibcon#wrote, iclass 4, count 0 2006.202.00:41:22.60#ibcon#about to read 3, iclass 4, count 0 2006.202.00:41:22.62#ibcon#read 3, iclass 4, count 0 2006.202.00:41:22.62#ibcon#about to read 4, iclass 4, count 0 2006.202.00:41:22.62#ibcon#read 4, iclass 4, count 0 2006.202.00:41:22.62#ibcon#about to read 5, iclass 4, count 0 2006.202.00:41:22.62#ibcon#read 5, iclass 4, count 0 2006.202.00:41:22.62#ibcon#about to read 6, iclass 4, count 0 2006.202.00:41:22.62#ibcon#read 6, iclass 4, count 0 2006.202.00:41:22.62#ibcon#end of sib2, iclass 4, count 0 2006.202.00:41:22.62#ibcon#*mode == 0, iclass 4, count 0 2006.202.00:41:22.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.00:41:22.62#ibcon#[27=USB\r\n] 2006.202.00:41:22.62#ibcon#*before write, iclass 4, count 0 2006.202.00:41:22.62#ibcon#enter sib2, iclass 4, count 0 2006.202.00:41:22.62#ibcon#flushed, iclass 4, count 0 2006.202.00:41:22.62#ibcon#about to write, iclass 4, count 0 2006.202.00:41:22.62#ibcon#wrote, iclass 4, count 0 2006.202.00:41:22.62#ibcon#about to read 3, iclass 4, count 0 2006.202.00:41:22.65#ibcon#read 3, iclass 4, count 0 2006.202.00:41:22.65#ibcon#about to read 4, iclass 4, count 0 2006.202.00:41:22.65#ibcon#read 4, iclass 4, count 0 2006.202.00:41:22.65#ibcon#about to read 5, iclass 4, count 0 2006.202.00:41:22.65#ibcon#read 5, iclass 4, count 0 2006.202.00:41:22.65#ibcon#about to read 6, iclass 4, count 0 2006.202.00:41:22.65#ibcon#read 6, iclass 4, count 0 2006.202.00:41:22.65#ibcon#end of sib2, iclass 4, count 0 2006.202.00:41:22.65#ibcon#*after write, iclass 4, count 0 2006.202.00:41:22.65#ibcon#*before return 0, iclass 4, count 0 2006.202.00:41:22.65#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:22.65#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.202.00:41:22.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.00:41:22.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.00:41:22.65$vck44/vabw=wide 2006.202.00:41:22.65#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.202.00:41:22.65#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.202.00:41:22.65#ibcon#ireg 8 cls_cnt 0 2006.202.00:41:22.65#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:22.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:22.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:22.65#ibcon#enter wrdev, iclass 6, count 0 2006.202.00:41:22.65#ibcon#first serial, iclass 6, count 0 2006.202.00:41:22.65#ibcon#enter sib2, iclass 6, count 0 2006.202.00:41:22.65#ibcon#flushed, iclass 6, count 0 2006.202.00:41:22.65#ibcon#about to write, iclass 6, count 0 2006.202.00:41:22.65#ibcon#wrote, iclass 6, count 0 2006.202.00:41:22.65#ibcon#about to read 3, iclass 6, count 0 2006.202.00:41:22.67#ibcon#read 3, iclass 6, count 0 2006.202.00:41:22.67#ibcon#about to read 4, iclass 6, count 0 2006.202.00:41:22.67#ibcon#read 4, iclass 6, count 0 2006.202.00:41:22.67#ibcon#about to read 5, iclass 6, count 0 2006.202.00:41:22.67#ibcon#read 5, iclass 6, count 0 2006.202.00:41:22.67#ibcon#about to read 6, iclass 6, count 0 2006.202.00:41:22.67#ibcon#read 6, iclass 6, count 0 2006.202.00:41:22.67#ibcon#end of sib2, iclass 6, count 0 2006.202.00:41:22.67#ibcon#*mode == 0, iclass 6, count 0 2006.202.00:41:22.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.00:41:22.67#ibcon#[25=BW32\r\n] 2006.202.00:41:22.67#ibcon#*before write, iclass 6, count 0 2006.202.00:41:22.67#ibcon#enter sib2, iclass 6, count 0 2006.202.00:41:22.67#ibcon#flushed, iclass 6, count 0 2006.202.00:41:22.67#ibcon#about to write, iclass 6, count 0 2006.202.00:41:22.67#ibcon#wrote, iclass 6, count 0 2006.202.00:41:22.67#ibcon#about to read 3, iclass 6, count 0 2006.202.00:41:22.70#ibcon#read 3, iclass 6, count 0 2006.202.00:41:22.70#ibcon#about to read 4, iclass 6, count 0 2006.202.00:41:22.70#ibcon#read 4, iclass 6, count 0 2006.202.00:41:22.70#ibcon#about to read 5, iclass 6, count 0 2006.202.00:41:22.70#ibcon#read 5, iclass 6, count 0 2006.202.00:41:22.70#ibcon#about to read 6, iclass 6, count 0 2006.202.00:41:22.70#ibcon#read 6, iclass 6, count 0 2006.202.00:41:22.70#ibcon#end of sib2, iclass 6, count 0 2006.202.00:41:22.70#ibcon#*after write, iclass 6, count 0 2006.202.00:41:22.70#ibcon#*before return 0, iclass 6, count 0 2006.202.00:41:22.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:22.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.202.00:41:22.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.00:41:22.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.00:41:22.70$vck44/vbbw=wide 2006.202.00:41:22.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.00:41:22.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.00:41:22.71#ibcon#ireg 8 cls_cnt 0 2006.202.00:41:22.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:41:22.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:41:22.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:41:22.77#ibcon#enter wrdev, iclass 10, count 0 2006.202.00:41:22.77#ibcon#first serial, iclass 10, count 0 2006.202.00:41:22.77#ibcon#enter sib2, iclass 10, count 0 2006.202.00:41:22.77#ibcon#flushed, iclass 10, count 0 2006.202.00:41:22.77#ibcon#about to write, iclass 10, count 0 2006.202.00:41:22.77#ibcon#wrote, iclass 10, count 0 2006.202.00:41:22.77#ibcon#about to read 3, iclass 10, count 0 2006.202.00:41:22.79#ibcon#read 3, iclass 10, count 0 2006.202.00:41:22.79#ibcon#about to read 4, iclass 10, count 0 2006.202.00:41:22.79#ibcon#read 4, iclass 10, count 0 2006.202.00:41:22.79#ibcon#about to read 5, iclass 10, count 0 2006.202.00:41:22.79#ibcon#read 5, iclass 10, count 0 2006.202.00:41:22.79#ibcon#about to read 6, iclass 10, count 0 2006.202.00:41:22.79#ibcon#read 6, iclass 10, count 0 2006.202.00:41:22.79#ibcon#end of sib2, iclass 10, count 0 2006.202.00:41:22.79#ibcon#*mode == 0, iclass 10, count 0 2006.202.00:41:22.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.00:41:22.79#ibcon#[27=BW32\r\n] 2006.202.00:41:22.79#ibcon#*before write, iclass 10, count 0 2006.202.00:41:22.79#ibcon#enter sib2, iclass 10, count 0 2006.202.00:41:22.79#ibcon#flushed, iclass 10, count 0 2006.202.00:41:22.79#ibcon#about to write, iclass 10, count 0 2006.202.00:41:22.79#ibcon#wrote, iclass 10, count 0 2006.202.00:41:22.79#ibcon#about to read 3, iclass 10, count 0 2006.202.00:41:22.82#ibcon#read 3, iclass 10, count 0 2006.202.00:41:22.82#ibcon#about to read 4, iclass 10, count 0 2006.202.00:41:22.82#ibcon#read 4, iclass 10, count 0 2006.202.00:41:22.82#ibcon#about to read 5, iclass 10, count 0 2006.202.00:41:22.82#ibcon#read 5, iclass 10, count 0 2006.202.00:41:22.82#ibcon#about to read 6, iclass 10, count 0 2006.202.00:41:22.82#ibcon#read 6, iclass 10, count 0 2006.202.00:41:22.82#ibcon#end of sib2, iclass 10, count 0 2006.202.00:41:22.82#ibcon#*after write, iclass 10, count 0 2006.202.00:41:22.82#ibcon#*before return 0, iclass 10, count 0 2006.202.00:41:22.82#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:41:22.82#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:41:22.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.00:41:22.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.00:41:22.82$setupk4/ifdk4 2006.202.00:41:22.82$ifdk4/lo= 2006.202.00:41:22.82$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.00:41:22.82$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.00:41:22.82$ifdk4/patch= 2006.202.00:41:22.82$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.00:41:22.82$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.00:41:22.82$setupk4/!*+20s 2006.202.00:41:30.97#abcon#<5=/03 2.1 4.4 20.401001001.5\r\n> 2006.202.00:41:30.99#abcon#{5=INTERFACE CLEAR} 2006.202.00:41:31.05#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:41:37.27$setupk4/"tpicd 2006.202.00:41:37.27$setupk4/echo=off 2006.202.00:41:37.27$setupk4/xlog=off 2006.202.00:41:37.27:!2006.202.00:45:08 2006.202.00:42:18.14#trakl#Source acquired 2006.202.00:42:18.14#flagr#flagr/antenna,acquired 2006.202.00:45:08.00:preob 2006.202.00:45:08.14/onsource/TRACKING 2006.202.00:45:08.14:!2006.202.00:45:18 2006.202.00:45:18.00:"tape 2006.202.00:45:18.00:"st=record 2006.202.00:45:18.00:data_valid=on 2006.202.00:45:18.00:midob 2006.202.00:45:18.14/onsource/TRACKING 2006.202.00:45:18.14/wx/20.35,1001.5,100 2006.202.00:45:18.34/cable/+6.4839E-03 2006.202.00:45:19.43/va/01,08,usb,yes,42,44 2006.202.00:45:19.43/va/02,07,usb,yes,45,46 2006.202.00:45:19.43/va/03,08,usb,yes,41,42 2006.202.00:45:19.43/va/04,07,usb,yes,46,49 2006.202.00:45:19.43/va/05,04,usb,yes,41,42 2006.202.00:45:19.43/va/06,05,usb,yes,41,41 2006.202.00:45:19.43/va/07,05,usb,yes,40,42 2006.202.00:45:19.43/va/08,04,usb,yes,40,48 2006.202.00:45:19.66/valo/01,524.99,yes,locked 2006.202.00:45:19.66/valo/02,534.99,yes,locked 2006.202.00:45:19.66/valo/03,564.99,yes,locked 2006.202.00:45:19.66/valo/04,624.99,yes,locked 2006.202.00:45:19.66/valo/05,734.99,yes,locked 2006.202.00:45:19.66/valo/06,814.99,yes,locked 2006.202.00:45:19.66/valo/07,864.99,yes,locked 2006.202.00:45:19.66/valo/08,884.99,yes,locked 2006.202.00:45:20.75/vb/01,04,usb,yes,30,28 2006.202.00:45:20.75/vb/02,05,usb,yes,28,28 2006.202.00:45:20.75/vb/03,04,usb,yes,29,32 2006.202.00:45:20.75/vb/04,05,usb,yes,30,29 2006.202.00:45:20.75/vb/05,04,usb,yes,26,29 2006.202.00:45:20.75/vb/06,04,usb,yes,30,27 2006.202.00:45:20.75/vb/07,04,usb,yes,30,30 2006.202.00:45:20.75/vb/08,04,usb,yes,28,31 2006.202.00:45:20.99/vblo/01,629.99,yes,locked 2006.202.00:45:20.99/vblo/02,634.99,yes,locked 2006.202.00:45:20.99/vblo/03,649.99,yes,locked 2006.202.00:45:20.99/vblo/04,679.99,yes,locked 2006.202.00:45:20.99/vblo/05,709.99,yes,locked 2006.202.00:45:20.99/vblo/06,719.99,yes,locked 2006.202.00:45:20.99/vblo/07,734.99,yes,locked 2006.202.00:45:20.99/vblo/08,744.99,yes,locked 2006.202.00:45:21.14/vabw/8 2006.202.00:45:21.29/vbbw/8 2006.202.00:45:21.38/xfe/off,on,14.7 2006.202.00:45:21.75/ifatt/23,28,28,28 2006.202.00:45:22.07/fmout-gps/S +4.51E-07 2006.202.00:45:22.11:!2006.202.00:46:08 2006.202.00:46:08.00:data_valid=off 2006.202.00:46:08.00:"et 2006.202.00:46:08.00:!+3s 2006.202.00:46:11.02:"tape 2006.202.00:46:11.02:postob 2006.202.00:46:11.21/cable/+6.4830E-03 2006.202.00:46:11.21/wx/20.35,1001.4,100 2006.202.00:46:11.27/fmout-gps/S +4.51E-07 2006.202.00:46:11.27:scan_name=202-0048,jd0607,600 2006.202.00:46:11.27:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.202.00:46:12.14#flagr#flagr/antenna,new-source 2006.202.00:46:12.14:checkk5 2006.202.00:46:12.56/chk_autoobs//k5ts1/ autoobs is running! 2006.202.00:46:12.98/chk_autoobs//k5ts2/ autoobs is running! 2006.202.00:46:13.38/chk_autoobs//k5ts3/ autoobs is running! 2006.202.00:46:13.78/chk_autoobs//k5ts4/ autoobs is running! 2006.202.00:46:14.16/chk_obsdata//k5ts1/T2020045??a.dat file size is correct (nominal:200MB, actual:196MB). 2006.202.00:46:14.56/chk_obsdata//k5ts2/T2020045??b.dat file size is correct (nominal:200MB, actual:196MB). 2006.202.00:46:14.95/chk_obsdata//k5ts3/T2020045??c.dat file size is correct (nominal:200MB, actual:196MB). 2006.202.00:46:15.35/chk_obsdata//k5ts4/T2020045??d.dat file size is correct (nominal:200MB, actual:196MB). 2006.202.00:46:16.06/k5log//k5ts1_log_newline 2006.202.00:46:16.78/k5log//k5ts2_log_newline 2006.202.00:46:17.50/k5log//k5ts3_log_newline 2006.202.00:46:18.20/k5log//k5ts4_log_newline 2006.202.00:46:18.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.00:46:18.23:setupk4=1 2006.202.00:46:18.23$setupk4/echo=on 2006.202.00:46:18.23$setupk4/pcalon 2006.202.00:46:18.23$pcalon/"no phase cal control is implemented here 2006.202.00:46:18.23$setupk4/"tpicd=stop 2006.202.00:46:18.23$setupk4/"rec=synch_on 2006.202.00:46:18.23$setupk4/"rec_mode=128 2006.202.00:46:18.23$setupk4/!* 2006.202.00:46:18.23$setupk4/recpk4 2006.202.00:46:18.23$recpk4/recpatch= 2006.202.00:46:18.23$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.00:46:18.23$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.00:46:18.23$setupk4/vck44 2006.202.00:46:18.23$vck44/valo=1,524.99 2006.202.00:46:18.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.00:46:18.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.00:46:18.23#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:18.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:18.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:18.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:18.23#ibcon#enter wrdev, iclass 23, count 0 2006.202.00:46:18.23#ibcon#first serial, iclass 23, count 0 2006.202.00:46:18.23#ibcon#enter sib2, iclass 23, count 0 2006.202.00:46:18.23#ibcon#flushed, iclass 23, count 0 2006.202.00:46:18.23#ibcon#about to write, iclass 23, count 0 2006.202.00:46:18.23#ibcon#wrote, iclass 23, count 0 2006.202.00:46:18.23#ibcon#about to read 3, iclass 23, count 0 2006.202.00:46:18.25#ibcon#read 3, iclass 23, count 0 2006.202.00:46:18.25#ibcon#about to read 4, iclass 23, count 0 2006.202.00:46:18.25#ibcon#read 4, iclass 23, count 0 2006.202.00:46:18.25#ibcon#about to read 5, iclass 23, count 0 2006.202.00:46:18.25#ibcon#read 5, iclass 23, count 0 2006.202.00:46:18.25#ibcon#about to read 6, iclass 23, count 0 2006.202.00:46:18.25#ibcon#read 6, iclass 23, count 0 2006.202.00:46:18.25#ibcon#end of sib2, iclass 23, count 0 2006.202.00:46:18.25#ibcon#*mode == 0, iclass 23, count 0 2006.202.00:46:18.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.00:46:18.25#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.00:46:18.25#ibcon#*before write, iclass 23, count 0 2006.202.00:46:18.25#ibcon#enter sib2, iclass 23, count 0 2006.202.00:46:18.25#ibcon#flushed, iclass 23, count 0 2006.202.00:46:18.25#ibcon#about to write, iclass 23, count 0 2006.202.00:46:18.25#ibcon#wrote, iclass 23, count 0 2006.202.00:46:18.25#ibcon#about to read 3, iclass 23, count 0 2006.202.00:46:18.30#ibcon#read 3, iclass 23, count 0 2006.202.00:46:18.30#ibcon#about to read 4, iclass 23, count 0 2006.202.00:46:18.30#ibcon#read 4, iclass 23, count 0 2006.202.00:46:18.30#ibcon#about to read 5, iclass 23, count 0 2006.202.00:46:18.30#ibcon#read 5, iclass 23, count 0 2006.202.00:46:18.30#ibcon#about to read 6, iclass 23, count 0 2006.202.00:46:18.30#ibcon#read 6, iclass 23, count 0 2006.202.00:46:18.30#ibcon#end of sib2, iclass 23, count 0 2006.202.00:46:18.30#ibcon#*after write, iclass 23, count 0 2006.202.00:46:18.30#ibcon#*before return 0, iclass 23, count 0 2006.202.00:46:18.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:18.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:18.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.00:46:18.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.00:46:18.30$vck44/va=1,8 2006.202.00:46:18.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.202.00:46:18.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.202.00:46:18.30#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:18.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:18.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:18.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:18.30#ibcon#enter wrdev, iclass 25, count 2 2006.202.00:46:18.30#ibcon#first serial, iclass 25, count 2 2006.202.00:46:18.30#ibcon#enter sib2, iclass 25, count 2 2006.202.00:46:18.30#ibcon#flushed, iclass 25, count 2 2006.202.00:46:18.30#ibcon#about to write, iclass 25, count 2 2006.202.00:46:18.30#ibcon#wrote, iclass 25, count 2 2006.202.00:46:18.30#ibcon#about to read 3, iclass 25, count 2 2006.202.00:46:18.32#ibcon#read 3, iclass 25, count 2 2006.202.00:46:18.32#ibcon#about to read 4, iclass 25, count 2 2006.202.00:46:18.32#ibcon#read 4, iclass 25, count 2 2006.202.00:46:18.32#ibcon#about to read 5, iclass 25, count 2 2006.202.00:46:18.32#ibcon#read 5, iclass 25, count 2 2006.202.00:46:18.32#ibcon#about to read 6, iclass 25, count 2 2006.202.00:46:18.32#ibcon#read 6, iclass 25, count 2 2006.202.00:46:18.32#ibcon#end of sib2, iclass 25, count 2 2006.202.00:46:18.32#ibcon#*mode == 0, iclass 25, count 2 2006.202.00:46:18.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.202.00:46:18.32#ibcon#[25=AT01-08\r\n] 2006.202.00:46:18.32#ibcon#*before write, iclass 25, count 2 2006.202.00:46:18.32#ibcon#enter sib2, iclass 25, count 2 2006.202.00:46:18.32#ibcon#flushed, iclass 25, count 2 2006.202.00:46:18.32#ibcon#about to write, iclass 25, count 2 2006.202.00:46:18.32#ibcon#wrote, iclass 25, count 2 2006.202.00:46:18.32#ibcon#about to read 3, iclass 25, count 2 2006.202.00:46:18.35#ibcon#read 3, iclass 25, count 2 2006.202.00:46:18.35#ibcon#about to read 4, iclass 25, count 2 2006.202.00:46:18.35#ibcon#read 4, iclass 25, count 2 2006.202.00:46:18.35#ibcon#about to read 5, iclass 25, count 2 2006.202.00:46:18.35#ibcon#read 5, iclass 25, count 2 2006.202.00:46:18.35#ibcon#about to read 6, iclass 25, count 2 2006.202.00:46:18.35#ibcon#read 6, iclass 25, count 2 2006.202.00:46:18.35#ibcon#end of sib2, iclass 25, count 2 2006.202.00:46:18.35#ibcon#*after write, iclass 25, count 2 2006.202.00:46:18.35#ibcon#*before return 0, iclass 25, count 2 2006.202.00:46:18.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:18.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:18.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.202.00:46:18.35#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:18.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:18.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:18.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:18.47#ibcon#enter wrdev, iclass 25, count 0 2006.202.00:46:18.47#ibcon#first serial, iclass 25, count 0 2006.202.00:46:18.47#ibcon#enter sib2, iclass 25, count 0 2006.202.00:46:18.47#ibcon#flushed, iclass 25, count 0 2006.202.00:46:18.47#ibcon#about to write, iclass 25, count 0 2006.202.00:46:18.47#ibcon#wrote, iclass 25, count 0 2006.202.00:46:18.47#ibcon#about to read 3, iclass 25, count 0 2006.202.00:46:18.49#ibcon#read 3, iclass 25, count 0 2006.202.00:46:18.49#ibcon#about to read 4, iclass 25, count 0 2006.202.00:46:18.49#ibcon#read 4, iclass 25, count 0 2006.202.00:46:18.49#ibcon#about to read 5, iclass 25, count 0 2006.202.00:46:18.49#ibcon#read 5, iclass 25, count 0 2006.202.00:46:18.49#ibcon#about to read 6, iclass 25, count 0 2006.202.00:46:18.49#ibcon#read 6, iclass 25, count 0 2006.202.00:46:18.49#ibcon#end of sib2, iclass 25, count 0 2006.202.00:46:18.49#ibcon#*mode == 0, iclass 25, count 0 2006.202.00:46:18.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.00:46:18.49#ibcon#[25=USB\r\n] 2006.202.00:46:18.49#ibcon#*before write, iclass 25, count 0 2006.202.00:46:18.49#ibcon#enter sib2, iclass 25, count 0 2006.202.00:46:18.49#ibcon#flushed, iclass 25, count 0 2006.202.00:46:18.49#ibcon#about to write, iclass 25, count 0 2006.202.00:46:18.49#ibcon#wrote, iclass 25, count 0 2006.202.00:46:18.49#ibcon#about to read 3, iclass 25, count 0 2006.202.00:46:18.52#ibcon#read 3, iclass 25, count 0 2006.202.00:46:18.52#ibcon#about to read 4, iclass 25, count 0 2006.202.00:46:18.52#ibcon#read 4, iclass 25, count 0 2006.202.00:46:18.52#ibcon#about to read 5, iclass 25, count 0 2006.202.00:46:18.52#ibcon#read 5, iclass 25, count 0 2006.202.00:46:18.52#ibcon#about to read 6, iclass 25, count 0 2006.202.00:46:18.52#ibcon#read 6, iclass 25, count 0 2006.202.00:46:18.52#ibcon#end of sib2, iclass 25, count 0 2006.202.00:46:18.52#ibcon#*after write, iclass 25, count 0 2006.202.00:46:18.52#ibcon#*before return 0, iclass 25, count 0 2006.202.00:46:18.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:18.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:18.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.00:46:18.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.00:46:18.52$vck44/valo=2,534.99 2006.202.00:46:18.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.202.00:46:18.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.202.00:46:18.52#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:18.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:18.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:18.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:18.52#ibcon#enter wrdev, iclass 27, count 0 2006.202.00:46:18.52#ibcon#first serial, iclass 27, count 0 2006.202.00:46:18.52#ibcon#enter sib2, iclass 27, count 0 2006.202.00:46:18.52#ibcon#flushed, iclass 27, count 0 2006.202.00:46:18.52#ibcon#about to write, iclass 27, count 0 2006.202.00:46:18.52#ibcon#wrote, iclass 27, count 0 2006.202.00:46:18.52#ibcon#about to read 3, iclass 27, count 0 2006.202.00:46:18.54#ibcon#read 3, iclass 27, count 0 2006.202.00:46:18.54#ibcon#about to read 4, iclass 27, count 0 2006.202.00:46:18.54#ibcon#read 4, iclass 27, count 0 2006.202.00:46:18.54#ibcon#about to read 5, iclass 27, count 0 2006.202.00:46:18.54#ibcon#read 5, iclass 27, count 0 2006.202.00:46:18.54#ibcon#about to read 6, iclass 27, count 0 2006.202.00:46:18.54#ibcon#read 6, iclass 27, count 0 2006.202.00:46:18.54#ibcon#end of sib2, iclass 27, count 0 2006.202.00:46:18.54#ibcon#*mode == 0, iclass 27, count 0 2006.202.00:46:18.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.00:46:18.54#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.00:46:18.54#ibcon#*before write, iclass 27, count 0 2006.202.00:46:18.54#ibcon#enter sib2, iclass 27, count 0 2006.202.00:46:18.54#ibcon#flushed, iclass 27, count 0 2006.202.00:46:18.54#ibcon#about to write, iclass 27, count 0 2006.202.00:46:18.54#ibcon#wrote, iclass 27, count 0 2006.202.00:46:18.54#ibcon#about to read 3, iclass 27, count 0 2006.202.00:46:18.58#ibcon#read 3, iclass 27, count 0 2006.202.00:46:18.58#ibcon#about to read 4, iclass 27, count 0 2006.202.00:46:18.58#ibcon#read 4, iclass 27, count 0 2006.202.00:46:18.58#ibcon#about to read 5, iclass 27, count 0 2006.202.00:46:18.58#ibcon#read 5, iclass 27, count 0 2006.202.00:46:18.58#ibcon#about to read 6, iclass 27, count 0 2006.202.00:46:18.58#ibcon#read 6, iclass 27, count 0 2006.202.00:46:18.58#ibcon#end of sib2, iclass 27, count 0 2006.202.00:46:18.58#ibcon#*after write, iclass 27, count 0 2006.202.00:46:18.58#ibcon#*before return 0, iclass 27, count 0 2006.202.00:46:18.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:18.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:18.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.00:46:18.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.00:46:18.58$vck44/va=2,7 2006.202.00:46:18.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.00:46:18.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.00:46:18.58#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:18.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:18.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:18.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:18.64#ibcon#enter wrdev, iclass 29, count 2 2006.202.00:46:18.64#ibcon#first serial, iclass 29, count 2 2006.202.00:46:18.64#ibcon#enter sib2, iclass 29, count 2 2006.202.00:46:18.64#ibcon#flushed, iclass 29, count 2 2006.202.00:46:18.64#ibcon#about to write, iclass 29, count 2 2006.202.00:46:18.64#ibcon#wrote, iclass 29, count 2 2006.202.00:46:18.64#ibcon#about to read 3, iclass 29, count 2 2006.202.00:46:18.66#ibcon#read 3, iclass 29, count 2 2006.202.00:46:18.66#ibcon#about to read 4, iclass 29, count 2 2006.202.00:46:18.66#ibcon#read 4, iclass 29, count 2 2006.202.00:46:18.66#ibcon#about to read 5, iclass 29, count 2 2006.202.00:46:18.66#ibcon#read 5, iclass 29, count 2 2006.202.00:46:18.66#ibcon#about to read 6, iclass 29, count 2 2006.202.00:46:18.66#ibcon#read 6, iclass 29, count 2 2006.202.00:46:18.66#ibcon#end of sib2, iclass 29, count 2 2006.202.00:46:18.66#ibcon#*mode == 0, iclass 29, count 2 2006.202.00:46:18.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.00:46:18.66#ibcon#[25=AT02-07\r\n] 2006.202.00:46:18.66#ibcon#*before write, iclass 29, count 2 2006.202.00:46:18.66#ibcon#enter sib2, iclass 29, count 2 2006.202.00:46:18.66#ibcon#flushed, iclass 29, count 2 2006.202.00:46:18.66#ibcon#about to write, iclass 29, count 2 2006.202.00:46:18.66#ibcon#wrote, iclass 29, count 2 2006.202.00:46:18.66#ibcon#about to read 3, iclass 29, count 2 2006.202.00:46:18.69#ibcon#read 3, iclass 29, count 2 2006.202.00:46:18.69#ibcon#about to read 4, iclass 29, count 2 2006.202.00:46:18.69#ibcon#read 4, iclass 29, count 2 2006.202.00:46:18.69#ibcon#about to read 5, iclass 29, count 2 2006.202.00:46:18.69#ibcon#read 5, iclass 29, count 2 2006.202.00:46:18.69#ibcon#about to read 6, iclass 29, count 2 2006.202.00:46:18.69#ibcon#read 6, iclass 29, count 2 2006.202.00:46:18.69#ibcon#end of sib2, iclass 29, count 2 2006.202.00:46:18.69#ibcon#*after write, iclass 29, count 2 2006.202.00:46:18.69#ibcon#*before return 0, iclass 29, count 2 2006.202.00:46:18.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:18.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:18.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.00:46:18.69#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:18.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:18.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:18.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:18.81#ibcon#enter wrdev, iclass 29, count 0 2006.202.00:46:18.81#ibcon#first serial, iclass 29, count 0 2006.202.00:46:18.81#ibcon#enter sib2, iclass 29, count 0 2006.202.00:46:18.81#ibcon#flushed, iclass 29, count 0 2006.202.00:46:18.81#ibcon#about to write, iclass 29, count 0 2006.202.00:46:18.81#ibcon#wrote, iclass 29, count 0 2006.202.00:46:18.81#ibcon#about to read 3, iclass 29, count 0 2006.202.00:46:18.83#ibcon#read 3, iclass 29, count 0 2006.202.00:46:18.83#ibcon#about to read 4, iclass 29, count 0 2006.202.00:46:18.83#ibcon#read 4, iclass 29, count 0 2006.202.00:46:18.83#ibcon#about to read 5, iclass 29, count 0 2006.202.00:46:18.83#ibcon#read 5, iclass 29, count 0 2006.202.00:46:18.83#ibcon#about to read 6, iclass 29, count 0 2006.202.00:46:18.83#ibcon#read 6, iclass 29, count 0 2006.202.00:46:18.83#ibcon#end of sib2, iclass 29, count 0 2006.202.00:46:18.83#ibcon#*mode == 0, iclass 29, count 0 2006.202.00:46:18.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.00:46:18.83#ibcon#[25=USB\r\n] 2006.202.00:46:18.83#ibcon#*before write, iclass 29, count 0 2006.202.00:46:18.83#ibcon#enter sib2, iclass 29, count 0 2006.202.00:46:18.83#ibcon#flushed, iclass 29, count 0 2006.202.00:46:18.83#ibcon#about to write, iclass 29, count 0 2006.202.00:46:18.83#ibcon#wrote, iclass 29, count 0 2006.202.00:46:18.83#ibcon#about to read 3, iclass 29, count 0 2006.202.00:46:18.86#ibcon#read 3, iclass 29, count 0 2006.202.00:46:18.86#ibcon#about to read 4, iclass 29, count 0 2006.202.00:46:18.86#ibcon#read 4, iclass 29, count 0 2006.202.00:46:18.86#ibcon#about to read 5, iclass 29, count 0 2006.202.00:46:18.86#ibcon#read 5, iclass 29, count 0 2006.202.00:46:18.86#ibcon#about to read 6, iclass 29, count 0 2006.202.00:46:18.86#ibcon#read 6, iclass 29, count 0 2006.202.00:46:18.86#ibcon#end of sib2, iclass 29, count 0 2006.202.00:46:18.86#ibcon#*after write, iclass 29, count 0 2006.202.00:46:18.86#ibcon#*before return 0, iclass 29, count 0 2006.202.00:46:18.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:18.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:18.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.00:46:18.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.00:46:18.86$vck44/valo=3,564.99 2006.202.00:46:18.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.202.00:46:18.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.202.00:46:18.86#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:18.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:18.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:18.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:18.86#ibcon#enter wrdev, iclass 31, count 0 2006.202.00:46:18.86#ibcon#first serial, iclass 31, count 0 2006.202.00:46:18.86#ibcon#enter sib2, iclass 31, count 0 2006.202.00:46:18.86#ibcon#flushed, iclass 31, count 0 2006.202.00:46:18.86#ibcon#about to write, iclass 31, count 0 2006.202.00:46:18.86#ibcon#wrote, iclass 31, count 0 2006.202.00:46:18.86#ibcon#about to read 3, iclass 31, count 0 2006.202.00:46:18.88#ibcon#read 3, iclass 31, count 0 2006.202.00:46:18.88#ibcon#about to read 4, iclass 31, count 0 2006.202.00:46:18.88#ibcon#read 4, iclass 31, count 0 2006.202.00:46:18.88#ibcon#about to read 5, iclass 31, count 0 2006.202.00:46:18.88#ibcon#read 5, iclass 31, count 0 2006.202.00:46:18.88#ibcon#about to read 6, iclass 31, count 0 2006.202.00:46:18.88#ibcon#read 6, iclass 31, count 0 2006.202.00:46:18.88#ibcon#end of sib2, iclass 31, count 0 2006.202.00:46:18.88#ibcon#*mode == 0, iclass 31, count 0 2006.202.00:46:18.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.00:46:18.88#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.00:46:18.88#ibcon#*before write, iclass 31, count 0 2006.202.00:46:18.88#ibcon#enter sib2, iclass 31, count 0 2006.202.00:46:18.88#ibcon#flushed, iclass 31, count 0 2006.202.00:46:18.88#ibcon#about to write, iclass 31, count 0 2006.202.00:46:18.88#ibcon#wrote, iclass 31, count 0 2006.202.00:46:18.88#ibcon#about to read 3, iclass 31, count 0 2006.202.00:46:18.92#ibcon#read 3, iclass 31, count 0 2006.202.00:46:18.92#ibcon#about to read 4, iclass 31, count 0 2006.202.00:46:18.92#ibcon#read 4, iclass 31, count 0 2006.202.00:46:18.92#ibcon#about to read 5, iclass 31, count 0 2006.202.00:46:18.92#ibcon#read 5, iclass 31, count 0 2006.202.00:46:18.92#ibcon#about to read 6, iclass 31, count 0 2006.202.00:46:18.92#ibcon#read 6, iclass 31, count 0 2006.202.00:46:18.92#ibcon#end of sib2, iclass 31, count 0 2006.202.00:46:18.92#ibcon#*after write, iclass 31, count 0 2006.202.00:46:18.92#ibcon#*before return 0, iclass 31, count 0 2006.202.00:46:18.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:18.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:18.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.00:46:18.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.00:46:18.92$vck44/va=3,8 2006.202.00:46:18.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.202.00:46:18.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.202.00:46:18.92#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:18.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:18.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:18.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:18.98#ibcon#enter wrdev, iclass 33, count 2 2006.202.00:46:18.98#ibcon#first serial, iclass 33, count 2 2006.202.00:46:18.98#ibcon#enter sib2, iclass 33, count 2 2006.202.00:46:18.98#ibcon#flushed, iclass 33, count 2 2006.202.00:46:18.98#ibcon#about to write, iclass 33, count 2 2006.202.00:46:18.98#ibcon#wrote, iclass 33, count 2 2006.202.00:46:18.98#ibcon#about to read 3, iclass 33, count 2 2006.202.00:46:19.00#ibcon#read 3, iclass 33, count 2 2006.202.00:46:19.00#ibcon#about to read 4, iclass 33, count 2 2006.202.00:46:19.00#ibcon#read 4, iclass 33, count 2 2006.202.00:46:19.00#ibcon#about to read 5, iclass 33, count 2 2006.202.00:46:19.00#ibcon#read 5, iclass 33, count 2 2006.202.00:46:19.00#ibcon#about to read 6, iclass 33, count 2 2006.202.00:46:19.00#ibcon#read 6, iclass 33, count 2 2006.202.00:46:19.00#ibcon#end of sib2, iclass 33, count 2 2006.202.00:46:19.00#ibcon#*mode == 0, iclass 33, count 2 2006.202.00:46:19.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.202.00:46:19.00#ibcon#[25=AT03-08\r\n] 2006.202.00:46:19.00#ibcon#*before write, iclass 33, count 2 2006.202.00:46:19.00#ibcon#enter sib2, iclass 33, count 2 2006.202.00:46:19.00#ibcon#flushed, iclass 33, count 2 2006.202.00:46:19.00#ibcon#about to write, iclass 33, count 2 2006.202.00:46:19.00#ibcon#wrote, iclass 33, count 2 2006.202.00:46:19.00#ibcon#about to read 3, iclass 33, count 2 2006.202.00:46:19.03#ibcon#read 3, iclass 33, count 2 2006.202.00:46:19.03#ibcon#about to read 4, iclass 33, count 2 2006.202.00:46:19.03#ibcon#read 4, iclass 33, count 2 2006.202.00:46:19.03#ibcon#about to read 5, iclass 33, count 2 2006.202.00:46:19.03#ibcon#read 5, iclass 33, count 2 2006.202.00:46:19.03#ibcon#about to read 6, iclass 33, count 2 2006.202.00:46:19.03#ibcon#read 6, iclass 33, count 2 2006.202.00:46:19.03#ibcon#end of sib2, iclass 33, count 2 2006.202.00:46:19.03#ibcon#*after write, iclass 33, count 2 2006.202.00:46:19.03#ibcon#*before return 0, iclass 33, count 2 2006.202.00:46:19.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:19.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:19.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.202.00:46:19.03#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:19.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:19.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:19.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:19.15#ibcon#enter wrdev, iclass 33, count 0 2006.202.00:46:19.15#ibcon#first serial, iclass 33, count 0 2006.202.00:46:19.15#ibcon#enter sib2, iclass 33, count 0 2006.202.00:46:19.15#ibcon#flushed, iclass 33, count 0 2006.202.00:46:19.15#ibcon#about to write, iclass 33, count 0 2006.202.00:46:19.15#ibcon#wrote, iclass 33, count 0 2006.202.00:46:19.15#ibcon#about to read 3, iclass 33, count 0 2006.202.00:46:19.17#ibcon#read 3, iclass 33, count 0 2006.202.00:46:19.17#ibcon#about to read 4, iclass 33, count 0 2006.202.00:46:19.17#ibcon#read 4, iclass 33, count 0 2006.202.00:46:19.17#ibcon#about to read 5, iclass 33, count 0 2006.202.00:46:19.17#ibcon#read 5, iclass 33, count 0 2006.202.00:46:19.17#ibcon#about to read 6, iclass 33, count 0 2006.202.00:46:19.17#ibcon#read 6, iclass 33, count 0 2006.202.00:46:19.17#ibcon#end of sib2, iclass 33, count 0 2006.202.00:46:19.17#ibcon#*mode == 0, iclass 33, count 0 2006.202.00:46:19.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.00:46:19.17#ibcon#[25=USB\r\n] 2006.202.00:46:19.17#ibcon#*before write, iclass 33, count 0 2006.202.00:46:19.17#ibcon#enter sib2, iclass 33, count 0 2006.202.00:46:19.17#ibcon#flushed, iclass 33, count 0 2006.202.00:46:19.17#ibcon#about to write, iclass 33, count 0 2006.202.00:46:19.17#ibcon#wrote, iclass 33, count 0 2006.202.00:46:19.17#ibcon#about to read 3, iclass 33, count 0 2006.202.00:46:19.20#ibcon#read 3, iclass 33, count 0 2006.202.00:46:19.20#ibcon#about to read 4, iclass 33, count 0 2006.202.00:46:19.20#ibcon#read 4, iclass 33, count 0 2006.202.00:46:19.20#ibcon#about to read 5, iclass 33, count 0 2006.202.00:46:19.20#ibcon#read 5, iclass 33, count 0 2006.202.00:46:19.20#ibcon#about to read 6, iclass 33, count 0 2006.202.00:46:19.20#ibcon#read 6, iclass 33, count 0 2006.202.00:46:19.20#ibcon#end of sib2, iclass 33, count 0 2006.202.00:46:19.20#ibcon#*after write, iclass 33, count 0 2006.202.00:46:19.20#ibcon#*before return 0, iclass 33, count 0 2006.202.00:46:19.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:19.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:19.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.00:46:19.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.00:46:19.20$vck44/valo=4,624.99 2006.202.00:46:19.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.202.00:46:19.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.202.00:46:19.20#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:19.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:19.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:19.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:19.20#ibcon#enter wrdev, iclass 35, count 0 2006.202.00:46:19.20#ibcon#first serial, iclass 35, count 0 2006.202.00:46:19.20#ibcon#enter sib2, iclass 35, count 0 2006.202.00:46:19.20#ibcon#flushed, iclass 35, count 0 2006.202.00:46:19.20#ibcon#about to write, iclass 35, count 0 2006.202.00:46:19.20#ibcon#wrote, iclass 35, count 0 2006.202.00:46:19.20#ibcon#about to read 3, iclass 35, count 0 2006.202.00:46:19.22#ibcon#read 3, iclass 35, count 0 2006.202.00:46:19.22#ibcon#about to read 4, iclass 35, count 0 2006.202.00:46:19.22#ibcon#read 4, iclass 35, count 0 2006.202.00:46:19.22#ibcon#about to read 5, iclass 35, count 0 2006.202.00:46:19.22#ibcon#read 5, iclass 35, count 0 2006.202.00:46:19.22#ibcon#about to read 6, iclass 35, count 0 2006.202.00:46:19.22#ibcon#read 6, iclass 35, count 0 2006.202.00:46:19.22#ibcon#end of sib2, iclass 35, count 0 2006.202.00:46:19.22#ibcon#*mode == 0, iclass 35, count 0 2006.202.00:46:19.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.00:46:19.22#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.00:46:19.22#ibcon#*before write, iclass 35, count 0 2006.202.00:46:19.22#ibcon#enter sib2, iclass 35, count 0 2006.202.00:46:19.22#ibcon#flushed, iclass 35, count 0 2006.202.00:46:19.22#ibcon#about to write, iclass 35, count 0 2006.202.00:46:19.22#ibcon#wrote, iclass 35, count 0 2006.202.00:46:19.22#ibcon#about to read 3, iclass 35, count 0 2006.202.00:46:19.26#ibcon#read 3, iclass 35, count 0 2006.202.00:46:19.26#ibcon#about to read 4, iclass 35, count 0 2006.202.00:46:19.26#ibcon#read 4, iclass 35, count 0 2006.202.00:46:19.26#ibcon#about to read 5, iclass 35, count 0 2006.202.00:46:19.26#ibcon#read 5, iclass 35, count 0 2006.202.00:46:19.26#ibcon#about to read 6, iclass 35, count 0 2006.202.00:46:19.26#ibcon#read 6, iclass 35, count 0 2006.202.00:46:19.26#ibcon#end of sib2, iclass 35, count 0 2006.202.00:46:19.26#ibcon#*after write, iclass 35, count 0 2006.202.00:46:19.26#ibcon#*before return 0, iclass 35, count 0 2006.202.00:46:19.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:19.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:19.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.00:46:19.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.00:46:19.26$vck44/va=4,7 2006.202.00:46:19.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.202.00:46:19.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.202.00:46:19.26#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:19.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:19.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:19.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:19.32#ibcon#enter wrdev, iclass 37, count 2 2006.202.00:46:19.32#ibcon#first serial, iclass 37, count 2 2006.202.00:46:19.32#ibcon#enter sib2, iclass 37, count 2 2006.202.00:46:19.32#ibcon#flushed, iclass 37, count 2 2006.202.00:46:19.32#ibcon#about to write, iclass 37, count 2 2006.202.00:46:19.32#ibcon#wrote, iclass 37, count 2 2006.202.00:46:19.32#ibcon#about to read 3, iclass 37, count 2 2006.202.00:46:19.34#ibcon#read 3, iclass 37, count 2 2006.202.00:46:19.34#ibcon#about to read 4, iclass 37, count 2 2006.202.00:46:19.34#ibcon#read 4, iclass 37, count 2 2006.202.00:46:19.34#ibcon#about to read 5, iclass 37, count 2 2006.202.00:46:19.34#ibcon#read 5, iclass 37, count 2 2006.202.00:46:19.34#ibcon#about to read 6, iclass 37, count 2 2006.202.00:46:19.34#ibcon#read 6, iclass 37, count 2 2006.202.00:46:19.34#ibcon#end of sib2, iclass 37, count 2 2006.202.00:46:19.34#ibcon#*mode == 0, iclass 37, count 2 2006.202.00:46:19.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.202.00:46:19.34#ibcon#[25=AT04-07\r\n] 2006.202.00:46:19.34#ibcon#*before write, iclass 37, count 2 2006.202.00:46:19.34#ibcon#enter sib2, iclass 37, count 2 2006.202.00:46:19.34#ibcon#flushed, iclass 37, count 2 2006.202.00:46:19.34#ibcon#about to write, iclass 37, count 2 2006.202.00:46:19.34#ibcon#wrote, iclass 37, count 2 2006.202.00:46:19.34#ibcon#about to read 3, iclass 37, count 2 2006.202.00:46:19.37#ibcon#read 3, iclass 37, count 2 2006.202.00:46:19.37#ibcon#about to read 4, iclass 37, count 2 2006.202.00:46:19.37#ibcon#read 4, iclass 37, count 2 2006.202.00:46:19.37#ibcon#about to read 5, iclass 37, count 2 2006.202.00:46:19.37#ibcon#read 5, iclass 37, count 2 2006.202.00:46:19.37#ibcon#about to read 6, iclass 37, count 2 2006.202.00:46:19.37#ibcon#read 6, iclass 37, count 2 2006.202.00:46:19.37#ibcon#end of sib2, iclass 37, count 2 2006.202.00:46:19.37#ibcon#*after write, iclass 37, count 2 2006.202.00:46:19.37#ibcon#*before return 0, iclass 37, count 2 2006.202.00:46:19.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:19.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:19.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.202.00:46:19.37#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:19.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:19.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:19.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:19.49#ibcon#enter wrdev, iclass 37, count 0 2006.202.00:46:19.49#ibcon#first serial, iclass 37, count 0 2006.202.00:46:19.49#ibcon#enter sib2, iclass 37, count 0 2006.202.00:46:19.49#ibcon#flushed, iclass 37, count 0 2006.202.00:46:19.49#ibcon#about to write, iclass 37, count 0 2006.202.00:46:19.49#ibcon#wrote, iclass 37, count 0 2006.202.00:46:19.49#ibcon#about to read 3, iclass 37, count 0 2006.202.00:46:19.51#ibcon#read 3, iclass 37, count 0 2006.202.00:46:19.51#ibcon#about to read 4, iclass 37, count 0 2006.202.00:46:19.51#ibcon#read 4, iclass 37, count 0 2006.202.00:46:19.51#ibcon#about to read 5, iclass 37, count 0 2006.202.00:46:19.51#ibcon#read 5, iclass 37, count 0 2006.202.00:46:19.51#ibcon#about to read 6, iclass 37, count 0 2006.202.00:46:19.51#ibcon#read 6, iclass 37, count 0 2006.202.00:46:19.51#ibcon#end of sib2, iclass 37, count 0 2006.202.00:46:19.51#ibcon#*mode == 0, iclass 37, count 0 2006.202.00:46:19.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.00:46:19.51#ibcon#[25=USB\r\n] 2006.202.00:46:19.51#ibcon#*before write, iclass 37, count 0 2006.202.00:46:19.51#ibcon#enter sib2, iclass 37, count 0 2006.202.00:46:19.51#ibcon#flushed, iclass 37, count 0 2006.202.00:46:19.51#ibcon#about to write, iclass 37, count 0 2006.202.00:46:19.51#ibcon#wrote, iclass 37, count 0 2006.202.00:46:19.51#ibcon#about to read 3, iclass 37, count 0 2006.202.00:46:19.54#ibcon#read 3, iclass 37, count 0 2006.202.00:46:19.54#ibcon#about to read 4, iclass 37, count 0 2006.202.00:46:19.54#ibcon#read 4, iclass 37, count 0 2006.202.00:46:19.54#ibcon#about to read 5, iclass 37, count 0 2006.202.00:46:19.54#ibcon#read 5, iclass 37, count 0 2006.202.00:46:19.54#ibcon#about to read 6, iclass 37, count 0 2006.202.00:46:19.54#ibcon#read 6, iclass 37, count 0 2006.202.00:46:19.54#ibcon#end of sib2, iclass 37, count 0 2006.202.00:46:19.54#ibcon#*after write, iclass 37, count 0 2006.202.00:46:19.54#ibcon#*before return 0, iclass 37, count 0 2006.202.00:46:19.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:19.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:19.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.00:46:19.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.00:46:19.54$vck44/valo=5,734.99 2006.202.00:46:19.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.202.00:46:19.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.202.00:46:19.54#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:19.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:19.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:19.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:19.54#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:46:19.54#ibcon#first serial, iclass 39, count 0 2006.202.00:46:19.54#ibcon#enter sib2, iclass 39, count 0 2006.202.00:46:19.54#ibcon#flushed, iclass 39, count 0 2006.202.00:46:19.54#ibcon#about to write, iclass 39, count 0 2006.202.00:46:19.54#ibcon#wrote, iclass 39, count 0 2006.202.00:46:19.54#ibcon#about to read 3, iclass 39, count 0 2006.202.00:46:19.56#ibcon#read 3, iclass 39, count 0 2006.202.00:46:19.56#ibcon#about to read 4, iclass 39, count 0 2006.202.00:46:19.56#ibcon#read 4, iclass 39, count 0 2006.202.00:46:19.56#ibcon#about to read 5, iclass 39, count 0 2006.202.00:46:19.56#ibcon#read 5, iclass 39, count 0 2006.202.00:46:19.56#ibcon#about to read 6, iclass 39, count 0 2006.202.00:46:19.56#ibcon#read 6, iclass 39, count 0 2006.202.00:46:19.56#ibcon#end of sib2, iclass 39, count 0 2006.202.00:46:19.56#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:46:19.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:46:19.56#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.00:46:19.56#ibcon#*before write, iclass 39, count 0 2006.202.00:46:19.56#ibcon#enter sib2, iclass 39, count 0 2006.202.00:46:19.56#ibcon#flushed, iclass 39, count 0 2006.202.00:46:19.56#ibcon#about to write, iclass 39, count 0 2006.202.00:46:19.56#ibcon#wrote, iclass 39, count 0 2006.202.00:46:19.56#ibcon#about to read 3, iclass 39, count 0 2006.202.00:46:19.60#ibcon#read 3, iclass 39, count 0 2006.202.00:46:19.60#ibcon#about to read 4, iclass 39, count 0 2006.202.00:46:19.60#ibcon#read 4, iclass 39, count 0 2006.202.00:46:19.60#ibcon#about to read 5, iclass 39, count 0 2006.202.00:46:19.60#ibcon#read 5, iclass 39, count 0 2006.202.00:46:19.60#ibcon#about to read 6, iclass 39, count 0 2006.202.00:46:19.60#ibcon#read 6, iclass 39, count 0 2006.202.00:46:19.60#ibcon#end of sib2, iclass 39, count 0 2006.202.00:46:19.60#ibcon#*after write, iclass 39, count 0 2006.202.00:46:19.60#ibcon#*before return 0, iclass 39, count 0 2006.202.00:46:19.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:19.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:19.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:46:19.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:46:19.60$vck44/va=5,4 2006.202.00:46:19.60#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.202.00:46:19.60#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.202.00:46:19.60#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:19.60#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:19.66#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:19.66#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:19.66#ibcon#enter wrdev, iclass 2, count 2 2006.202.00:46:19.66#ibcon#first serial, iclass 2, count 2 2006.202.00:46:19.66#ibcon#enter sib2, iclass 2, count 2 2006.202.00:46:19.66#ibcon#flushed, iclass 2, count 2 2006.202.00:46:19.66#ibcon#about to write, iclass 2, count 2 2006.202.00:46:19.66#ibcon#wrote, iclass 2, count 2 2006.202.00:46:19.66#ibcon#about to read 3, iclass 2, count 2 2006.202.00:46:19.68#ibcon#read 3, iclass 2, count 2 2006.202.00:46:19.68#ibcon#about to read 4, iclass 2, count 2 2006.202.00:46:19.68#ibcon#read 4, iclass 2, count 2 2006.202.00:46:19.68#ibcon#about to read 5, iclass 2, count 2 2006.202.00:46:19.68#ibcon#read 5, iclass 2, count 2 2006.202.00:46:19.68#ibcon#about to read 6, iclass 2, count 2 2006.202.00:46:19.68#ibcon#read 6, iclass 2, count 2 2006.202.00:46:19.68#ibcon#end of sib2, iclass 2, count 2 2006.202.00:46:19.68#ibcon#*mode == 0, iclass 2, count 2 2006.202.00:46:19.68#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.202.00:46:19.68#ibcon#[25=AT05-04\r\n] 2006.202.00:46:19.68#ibcon#*before write, iclass 2, count 2 2006.202.00:46:19.68#ibcon#enter sib2, iclass 2, count 2 2006.202.00:46:19.68#ibcon#flushed, iclass 2, count 2 2006.202.00:46:19.68#ibcon#about to write, iclass 2, count 2 2006.202.00:46:19.68#ibcon#wrote, iclass 2, count 2 2006.202.00:46:19.68#ibcon#about to read 3, iclass 2, count 2 2006.202.00:46:19.71#ibcon#read 3, iclass 2, count 2 2006.202.00:46:19.71#ibcon#about to read 4, iclass 2, count 2 2006.202.00:46:19.71#ibcon#read 4, iclass 2, count 2 2006.202.00:46:19.71#ibcon#about to read 5, iclass 2, count 2 2006.202.00:46:19.71#ibcon#read 5, iclass 2, count 2 2006.202.00:46:19.71#ibcon#about to read 6, iclass 2, count 2 2006.202.00:46:19.71#ibcon#read 6, iclass 2, count 2 2006.202.00:46:19.71#ibcon#end of sib2, iclass 2, count 2 2006.202.00:46:19.71#ibcon#*after write, iclass 2, count 2 2006.202.00:46:19.71#ibcon#*before return 0, iclass 2, count 2 2006.202.00:46:19.71#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:19.71#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:19.71#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.202.00:46:19.71#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:19.71#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:19.83#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:19.83#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:19.83#ibcon#enter wrdev, iclass 2, count 0 2006.202.00:46:19.83#ibcon#first serial, iclass 2, count 0 2006.202.00:46:19.83#ibcon#enter sib2, iclass 2, count 0 2006.202.00:46:19.83#ibcon#flushed, iclass 2, count 0 2006.202.00:46:19.83#ibcon#about to write, iclass 2, count 0 2006.202.00:46:19.83#ibcon#wrote, iclass 2, count 0 2006.202.00:46:19.83#ibcon#about to read 3, iclass 2, count 0 2006.202.00:46:19.85#ibcon#read 3, iclass 2, count 0 2006.202.00:46:19.85#ibcon#about to read 4, iclass 2, count 0 2006.202.00:46:19.85#ibcon#read 4, iclass 2, count 0 2006.202.00:46:19.85#ibcon#about to read 5, iclass 2, count 0 2006.202.00:46:19.85#ibcon#read 5, iclass 2, count 0 2006.202.00:46:19.85#ibcon#about to read 6, iclass 2, count 0 2006.202.00:46:19.85#ibcon#read 6, iclass 2, count 0 2006.202.00:46:19.85#ibcon#end of sib2, iclass 2, count 0 2006.202.00:46:19.85#ibcon#*mode == 0, iclass 2, count 0 2006.202.00:46:19.85#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.00:46:19.85#ibcon#[25=USB\r\n] 2006.202.00:46:19.85#ibcon#*before write, iclass 2, count 0 2006.202.00:46:19.85#ibcon#enter sib2, iclass 2, count 0 2006.202.00:46:19.85#ibcon#flushed, iclass 2, count 0 2006.202.00:46:19.85#ibcon#about to write, iclass 2, count 0 2006.202.00:46:19.85#ibcon#wrote, iclass 2, count 0 2006.202.00:46:19.85#ibcon#about to read 3, iclass 2, count 0 2006.202.00:46:19.88#ibcon#read 3, iclass 2, count 0 2006.202.00:46:19.88#ibcon#about to read 4, iclass 2, count 0 2006.202.00:46:19.88#ibcon#read 4, iclass 2, count 0 2006.202.00:46:19.88#ibcon#about to read 5, iclass 2, count 0 2006.202.00:46:19.88#ibcon#read 5, iclass 2, count 0 2006.202.00:46:19.88#ibcon#about to read 6, iclass 2, count 0 2006.202.00:46:19.88#ibcon#read 6, iclass 2, count 0 2006.202.00:46:19.88#ibcon#end of sib2, iclass 2, count 0 2006.202.00:46:19.88#ibcon#*after write, iclass 2, count 0 2006.202.00:46:19.88#ibcon#*before return 0, iclass 2, count 0 2006.202.00:46:19.88#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:19.88#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:19.88#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.00:46:19.88#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.00:46:19.88$vck44/valo=6,814.99 2006.202.00:46:19.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.202.00:46:19.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.202.00:46:19.88#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:19.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:19.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:19.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:19.88#ibcon#enter wrdev, iclass 5, count 0 2006.202.00:46:19.88#ibcon#first serial, iclass 5, count 0 2006.202.00:46:19.88#ibcon#enter sib2, iclass 5, count 0 2006.202.00:46:19.88#ibcon#flushed, iclass 5, count 0 2006.202.00:46:19.88#ibcon#about to write, iclass 5, count 0 2006.202.00:46:19.88#ibcon#wrote, iclass 5, count 0 2006.202.00:46:19.88#ibcon#about to read 3, iclass 5, count 0 2006.202.00:46:19.90#ibcon#read 3, iclass 5, count 0 2006.202.00:46:19.90#ibcon#about to read 4, iclass 5, count 0 2006.202.00:46:19.90#ibcon#read 4, iclass 5, count 0 2006.202.00:46:19.90#ibcon#about to read 5, iclass 5, count 0 2006.202.00:46:19.90#ibcon#read 5, iclass 5, count 0 2006.202.00:46:19.90#ibcon#about to read 6, iclass 5, count 0 2006.202.00:46:19.90#ibcon#read 6, iclass 5, count 0 2006.202.00:46:19.90#ibcon#end of sib2, iclass 5, count 0 2006.202.00:46:19.90#ibcon#*mode == 0, iclass 5, count 0 2006.202.00:46:19.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.00:46:19.90#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.00:46:19.90#ibcon#*before write, iclass 5, count 0 2006.202.00:46:19.90#ibcon#enter sib2, iclass 5, count 0 2006.202.00:46:19.90#ibcon#flushed, iclass 5, count 0 2006.202.00:46:19.90#ibcon#about to write, iclass 5, count 0 2006.202.00:46:19.90#ibcon#wrote, iclass 5, count 0 2006.202.00:46:19.90#ibcon#about to read 3, iclass 5, count 0 2006.202.00:46:19.94#ibcon#read 3, iclass 5, count 0 2006.202.00:46:19.94#ibcon#about to read 4, iclass 5, count 0 2006.202.00:46:19.94#ibcon#read 4, iclass 5, count 0 2006.202.00:46:19.94#ibcon#about to read 5, iclass 5, count 0 2006.202.00:46:19.94#ibcon#read 5, iclass 5, count 0 2006.202.00:46:19.94#ibcon#about to read 6, iclass 5, count 0 2006.202.00:46:19.94#ibcon#read 6, iclass 5, count 0 2006.202.00:46:19.94#ibcon#end of sib2, iclass 5, count 0 2006.202.00:46:19.94#ibcon#*after write, iclass 5, count 0 2006.202.00:46:19.94#ibcon#*before return 0, iclass 5, count 0 2006.202.00:46:19.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:19.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:19.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.00:46:19.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.00:46:19.94$vck44/va=6,5 2006.202.00:46:19.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.202.00:46:19.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.202.00:46:19.94#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:19.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:20.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:20.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:20.00#ibcon#enter wrdev, iclass 7, count 2 2006.202.00:46:20.00#ibcon#first serial, iclass 7, count 2 2006.202.00:46:20.00#ibcon#enter sib2, iclass 7, count 2 2006.202.00:46:20.00#ibcon#flushed, iclass 7, count 2 2006.202.00:46:20.00#ibcon#about to write, iclass 7, count 2 2006.202.00:46:20.00#ibcon#wrote, iclass 7, count 2 2006.202.00:46:20.00#ibcon#about to read 3, iclass 7, count 2 2006.202.00:46:20.02#ibcon#read 3, iclass 7, count 2 2006.202.00:46:20.02#ibcon#about to read 4, iclass 7, count 2 2006.202.00:46:20.02#ibcon#read 4, iclass 7, count 2 2006.202.00:46:20.02#ibcon#about to read 5, iclass 7, count 2 2006.202.00:46:20.02#ibcon#read 5, iclass 7, count 2 2006.202.00:46:20.02#ibcon#about to read 6, iclass 7, count 2 2006.202.00:46:20.02#ibcon#read 6, iclass 7, count 2 2006.202.00:46:20.02#ibcon#end of sib2, iclass 7, count 2 2006.202.00:46:20.02#ibcon#*mode == 0, iclass 7, count 2 2006.202.00:46:20.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.202.00:46:20.02#ibcon#[25=AT06-05\r\n] 2006.202.00:46:20.02#ibcon#*before write, iclass 7, count 2 2006.202.00:46:20.02#ibcon#enter sib2, iclass 7, count 2 2006.202.00:46:20.02#ibcon#flushed, iclass 7, count 2 2006.202.00:46:20.02#ibcon#about to write, iclass 7, count 2 2006.202.00:46:20.02#ibcon#wrote, iclass 7, count 2 2006.202.00:46:20.02#ibcon#about to read 3, iclass 7, count 2 2006.202.00:46:20.05#ibcon#read 3, iclass 7, count 2 2006.202.00:46:20.05#ibcon#about to read 4, iclass 7, count 2 2006.202.00:46:20.05#ibcon#read 4, iclass 7, count 2 2006.202.00:46:20.05#ibcon#about to read 5, iclass 7, count 2 2006.202.00:46:20.05#ibcon#read 5, iclass 7, count 2 2006.202.00:46:20.05#ibcon#about to read 6, iclass 7, count 2 2006.202.00:46:20.05#ibcon#read 6, iclass 7, count 2 2006.202.00:46:20.05#ibcon#end of sib2, iclass 7, count 2 2006.202.00:46:20.05#ibcon#*after write, iclass 7, count 2 2006.202.00:46:20.05#ibcon#*before return 0, iclass 7, count 2 2006.202.00:46:20.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:20.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:20.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.202.00:46:20.05#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:20.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:20.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:20.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:20.17#ibcon#enter wrdev, iclass 7, count 0 2006.202.00:46:20.17#ibcon#first serial, iclass 7, count 0 2006.202.00:46:20.17#ibcon#enter sib2, iclass 7, count 0 2006.202.00:46:20.17#ibcon#flushed, iclass 7, count 0 2006.202.00:46:20.17#ibcon#about to write, iclass 7, count 0 2006.202.00:46:20.17#ibcon#wrote, iclass 7, count 0 2006.202.00:46:20.17#ibcon#about to read 3, iclass 7, count 0 2006.202.00:46:20.19#ibcon#read 3, iclass 7, count 0 2006.202.00:46:20.19#ibcon#about to read 4, iclass 7, count 0 2006.202.00:46:20.19#ibcon#read 4, iclass 7, count 0 2006.202.00:46:20.19#ibcon#about to read 5, iclass 7, count 0 2006.202.00:46:20.19#ibcon#read 5, iclass 7, count 0 2006.202.00:46:20.19#ibcon#about to read 6, iclass 7, count 0 2006.202.00:46:20.19#ibcon#read 6, iclass 7, count 0 2006.202.00:46:20.19#ibcon#end of sib2, iclass 7, count 0 2006.202.00:46:20.19#ibcon#*mode == 0, iclass 7, count 0 2006.202.00:46:20.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.00:46:20.19#ibcon#[25=USB\r\n] 2006.202.00:46:20.19#ibcon#*before write, iclass 7, count 0 2006.202.00:46:20.19#ibcon#enter sib2, iclass 7, count 0 2006.202.00:46:20.19#ibcon#flushed, iclass 7, count 0 2006.202.00:46:20.19#ibcon#about to write, iclass 7, count 0 2006.202.00:46:20.19#ibcon#wrote, iclass 7, count 0 2006.202.00:46:20.19#ibcon#about to read 3, iclass 7, count 0 2006.202.00:46:20.22#ibcon#read 3, iclass 7, count 0 2006.202.00:46:20.22#ibcon#about to read 4, iclass 7, count 0 2006.202.00:46:20.22#ibcon#read 4, iclass 7, count 0 2006.202.00:46:20.22#ibcon#about to read 5, iclass 7, count 0 2006.202.00:46:20.22#ibcon#read 5, iclass 7, count 0 2006.202.00:46:20.22#ibcon#about to read 6, iclass 7, count 0 2006.202.00:46:20.22#ibcon#read 6, iclass 7, count 0 2006.202.00:46:20.22#ibcon#end of sib2, iclass 7, count 0 2006.202.00:46:20.22#ibcon#*after write, iclass 7, count 0 2006.202.00:46:20.22#ibcon#*before return 0, iclass 7, count 0 2006.202.00:46:20.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:20.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:20.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.00:46:20.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.00:46:20.22$vck44/valo=7,864.99 2006.202.00:46:20.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.202.00:46:20.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.202.00:46:20.22#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:20.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:20.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:20.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:20.22#ibcon#enter wrdev, iclass 11, count 0 2006.202.00:46:20.22#ibcon#first serial, iclass 11, count 0 2006.202.00:46:20.22#ibcon#enter sib2, iclass 11, count 0 2006.202.00:46:20.22#ibcon#flushed, iclass 11, count 0 2006.202.00:46:20.22#ibcon#about to write, iclass 11, count 0 2006.202.00:46:20.22#ibcon#wrote, iclass 11, count 0 2006.202.00:46:20.22#ibcon#about to read 3, iclass 11, count 0 2006.202.00:46:20.24#ibcon#read 3, iclass 11, count 0 2006.202.00:46:20.24#ibcon#about to read 4, iclass 11, count 0 2006.202.00:46:20.24#ibcon#read 4, iclass 11, count 0 2006.202.00:46:20.24#ibcon#about to read 5, iclass 11, count 0 2006.202.00:46:20.24#ibcon#read 5, iclass 11, count 0 2006.202.00:46:20.24#ibcon#about to read 6, iclass 11, count 0 2006.202.00:46:20.24#ibcon#read 6, iclass 11, count 0 2006.202.00:46:20.24#ibcon#end of sib2, iclass 11, count 0 2006.202.00:46:20.24#ibcon#*mode == 0, iclass 11, count 0 2006.202.00:46:20.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.00:46:20.24#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.00:46:20.24#ibcon#*before write, iclass 11, count 0 2006.202.00:46:20.24#ibcon#enter sib2, iclass 11, count 0 2006.202.00:46:20.24#ibcon#flushed, iclass 11, count 0 2006.202.00:46:20.24#ibcon#about to write, iclass 11, count 0 2006.202.00:46:20.24#ibcon#wrote, iclass 11, count 0 2006.202.00:46:20.24#ibcon#about to read 3, iclass 11, count 0 2006.202.00:46:20.28#ibcon#read 3, iclass 11, count 0 2006.202.00:46:20.28#ibcon#about to read 4, iclass 11, count 0 2006.202.00:46:20.28#ibcon#read 4, iclass 11, count 0 2006.202.00:46:20.28#ibcon#about to read 5, iclass 11, count 0 2006.202.00:46:20.28#ibcon#read 5, iclass 11, count 0 2006.202.00:46:20.28#ibcon#about to read 6, iclass 11, count 0 2006.202.00:46:20.28#ibcon#read 6, iclass 11, count 0 2006.202.00:46:20.28#ibcon#end of sib2, iclass 11, count 0 2006.202.00:46:20.28#ibcon#*after write, iclass 11, count 0 2006.202.00:46:20.28#ibcon#*before return 0, iclass 11, count 0 2006.202.00:46:20.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:20.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:20.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.00:46:20.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.00:46:20.28$vck44/va=7,5 2006.202.00:46:20.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.202.00:46:20.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.202.00:46:20.28#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:20.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:20.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:20.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:20.34#ibcon#enter wrdev, iclass 13, count 2 2006.202.00:46:20.34#ibcon#first serial, iclass 13, count 2 2006.202.00:46:20.34#ibcon#enter sib2, iclass 13, count 2 2006.202.00:46:20.34#ibcon#flushed, iclass 13, count 2 2006.202.00:46:20.34#ibcon#about to write, iclass 13, count 2 2006.202.00:46:20.34#ibcon#wrote, iclass 13, count 2 2006.202.00:46:20.34#ibcon#about to read 3, iclass 13, count 2 2006.202.00:46:20.36#ibcon#read 3, iclass 13, count 2 2006.202.00:46:20.36#ibcon#about to read 4, iclass 13, count 2 2006.202.00:46:20.36#ibcon#read 4, iclass 13, count 2 2006.202.00:46:20.36#ibcon#about to read 5, iclass 13, count 2 2006.202.00:46:20.36#ibcon#read 5, iclass 13, count 2 2006.202.00:46:20.36#ibcon#about to read 6, iclass 13, count 2 2006.202.00:46:20.36#ibcon#read 6, iclass 13, count 2 2006.202.00:46:20.36#ibcon#end of sib2, iclass 13, count 2 2006.202.00:46:20.36#ibcon#*mode == 0, iclass 13, count 2 2006.202.00:46:20.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.202.00:46:20.36#ibcon#[25=AT07-05\r\n] 2006.202.00:46:20.36#ibcon#*before write, iclass 13, count 2 2006.202.00:46:20.36#ibcon#enter sib2, iclass 13, count 2 2006.202.00:46:20.36#ibcon#flushed, iclass 13, count 2 2006.202.00:46:20.36#ibcon#about to write, iclass 13, count 2 2006.202.00:46:20.36#ibcon#wrote, iclass 13, count 2 2006.202.00:46:20.36#ibcon#about to read 3, iclass 13, count 2 2006.202.00:46:20.39#ibcon#read 3, iclass 13, count 2 2006.202.00:46:20.39#ibcon#about to read 4, iclass 13, count 2 2006.202.00:46:20.39#ibcon#read 4, iclass 13, count 2 2006.202.00:46:20.39#ibcon#about to read 5, iclass 13, count 2 2006.202.00:46:20.39#ibcon#read 5, iclass 13, count 2 2006.202.00:46:20.39#ibcon#about to read 6, iclass 13, count 2 2006.202.00:46:20.39#ibcon#read 6, iclass 13, count 2 2006.202.00:46:20.39#ibcon#end of sib2, iclass 13, count 2 2006.202.00:46:20.39#ibcon#*after write, iclass 13, count 2 2006.202.00:46:20.39#ibcon#*before return 0, iclass 13, count 2 2006.202.00:46:20.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:20.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:20.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.202.00:46:20.39#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:20.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:20.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:20.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:20.51#ibcon#enter wrdev, iclass 13, count 0 2006.202.00:46:20.51#ibcon#first serial, iclass 13, count 0 2006.202.00:46:20.51#ibcon#enter sib2, iclass 13, count 0 2006.202.00:46:20.51#ibcon#flushed, iclass 13, count 0 2006.202.00:46:20.51#ibcon#about to write, iclass 13, count 0 2006.202.00:46:20.51#ibcon#wrote, iclass 13, count 0 2006.202.00:46:20.51#ibcon#about to read 3, iclass 13, count 0 2006.202.00:46:20.53#ibcon#read 3, iclass 13, count 0 2006.202.00:46:20.53#ibcon#about to read 4, iclass 13, count 0 2006.202.00:46:20.53#ibcon#read 4, iclass 13, count 0 2006.202.00:46:20.53#ibcon#about to read 5, iclass 13, count 0 2006.202.00:46:20.53#ibcon#read 5, iclass 13, count 0 2006.202.00:46:20.53#ibcon#about to read 6, iclass 13, count 0 2006.202.00:46:20.53#ibcon#read 6, iclass 13, count 0 2006.202.00:46:20.53#ibcon#end of sib2, iclass 13, count 0 2006.202.00:46:20.53#ibcon#*mode == 0, iclass 13, count 0 2006.202.00:46:20.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.00:46:20.53#ibcon#[25=USB\r\n] 2006.202.00:46:20.53#ibcon#*before write, iclass 13, count 0 2006.202.00:46:20.53#ibcon#enter sib2, iclass 13, count 0 2006.202.00:46:20.53#ibcon#flushed, iclass 13, count 0 2006.202.00:46:20.53#ibcon#about to write, iclass 13, count 0 2006.202.00:46:20.53#ibcon#wrote, iclass 13, count 0 2006.202.00:46:20.53#ibcon#about to read 3, iclass 13, count 0 2006.202.00:46:20.56#ibcon#read 3, iclass 13, count 0 2006.202.00:46:20.56#ibcon#about to read 4, iclass 13, count 0 2006.202.00:46:20.56#ibcon#read 4, iclass 13, count 0 2006.202.00:46:20.56#ibcon#about to read 5, iclass 13, count 0 2006.202.00:46:20.56#ibcon#read 5, iclass 13, count 0 2006.202.00:46:20.56#ibcon#about to read 6, iclass 13, count 0 2006.202.00:46:20.56#ibcon#read 6, iclass 13, count 0 2006.202.00:46:20.56#ibcon#end of sib2, iclass 13, count 0 2006.202.00:46:20.56#ibcon#*after write, iclass 13, count 0 2006.202.00:46:20.56#ibcon#*before return 0, iclass 13, count 0 2006.202.00:46:20.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:20.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:20.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.00:46:20.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.00:46:20.56$vck44/valo=8,884.99 2006.202.00:46:20.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.00:46:20.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.00:46:20.56#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:20.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:20.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:20.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:20.56#ibcon#enter wrdev, iclass 15, count 0 2006.202.00:46:20.56#ibcon#first serial, iclass 15, count 0 2006.202.00:46:20.56#ibcon#enter sib2, iclass 15, count 0 2006.202.00:46:20.56#ibcon#flushed, iclass 15, count 0 2006.202.00:46:20.56#ibcon#about to write, iclass 15, count 0 2006.202.00:46:20.56#ibcon#wrote, iclass 15, count 0 2006.202.00:46:20.56#ibcon#about to read 3, iclass 15, count 0 2006.202.00:46:20.58#ibcon#read 3, iclass 15, count 0 2006.202.00:46:20.58#ibcon#about to read 4, iclass 15, count 0 2006.202.00:46:20.58#ibcon#read 4, iclass 15, count 0 2006.202.00:46:20.58#ibcon#about to read 5, iclass 15, count 0 2006.202.00:46:20.58#ibcon#read 5, iclass 15, count 0 2006.202.00:46:20.58#ibcon#about to read 6, iclass 15, count 0 2006.202.00:46:20.58#ibcon#read 6, iclass 15, count 0 2006.202.00:46:20.58#ibcon#end of sib2, iclass 15, count 0 2006.202.00:46:20.58#ibcon#*mode == 0, iclass 15, count 0 2006.202.00:46:20.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.00:46:20.58#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.00:46:20.58#ibcon#*before write, iclass 15, count 0 2006.202.00:46:20.58#ibcon#enter sib2, iclass 15, count 0 2006.202.00:46:20.58#ibcon#flushed, iclass 15, count 0 2006.202.00:46:20.58#ibcon#about to write, iclass 15, count 0 2006.202.00:46:20.58#ibcon#wrote, iclass 15, count 0 2006.202.00:46:20.58#ibcon#about to read 3, iclass 15, count 0 2006.202.00:46:20.62#ibcon#read 3, iclass 15, count 0 2006.202.00:46:20.62#ibcon#about to read 4, iclass 15, count 0 2006.202.00:46:20.62#ibcon#read 4, iclass 15, count 0 2006.202.00:46:20.62#ibcon#about to read 5, iclass 15, count 0 2006.202.00:46:20.62#ibcon#read 5, iclass 15, count 0 2006.202.00:46:20.62#ibcon#about to read 6, iclass 15, count 0 2006.202.00:46:20.62#ibcon#read 6, iclass 15, count 0 2006.202.00:46:20.62#ibcon#end of sib2, iclass 15, count 0 2006.202.00:46:20.62#ibcon#*after write, iclass 15, count 0 2006.202.00:46:20.62#ibcon#*before return 0, iclass 15, count 0 2006.202.00:46:20.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:20.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:20.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.00:46:20.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.00:46:20.62$vck44/va=8,4 2006.202.00:46:20.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.202.00:46:20.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.202.00:46:20.62#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:20.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:46:20.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:46:20.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:46:20.68#ibcon#enter wrdev, iclass 17, count 2 2006.202.00:46:20.68#ibcon#first serial, iclass 17, count 2 2006.202.00:46:20.68#ibcon#enter sib2, iclass 17, count 2 2006.202.00:46:20.68#ibcon#flushed, iclass 17, count 2 2006.202.00:46:20.68#ibcon#about to write, iclass 17, count 2 2006.202.00:46:20.68#ibcon#wrote, iclass 17, count 2 2006.202.00:46:20.68#ibcon#about to read 3, iclass 17, count 2 2006.202.00:46:20.70#ibcon#read 3, iclass 17, count 2 2006.202.00:46:20.70#ibcon#about to read 4, iclass 17, count 2 2006.202.00:46:20.70#ibcon#read 4, iclass 17, count 2 2006.202.00:46:20.70#ibcon#about to read 5, iclass 17, count 2 2006.202.00:46:20.70#ibcon#read 5, iclass 17, count 2 2006.202.00:46:20.70#ibcon#about to read 6, iclass 17, count 2 2006.202.00:46:20.70#ibcon#read 6, iclass 17, count 2 2006.202.00:46:20.70#ibcon#end of sib2, iclass 17, count 2 2006.202.00:46:20.70#ibcon#*mode == 0, iclass 17, count 2 2006.202.00:46:20.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.202.00:46:20.70#ibcon#[25=AT08-04\r\n] 2006.202.00:46:20.70#ibcon#*before write, iclass 17, count 2 2006.202.00:46:20.70#ibcon#enter sib2, iclass 17, count 2 2006.202.00:46:20.70#ibcon#flushed, iclass 17, count 2 2006.202.00:46:20.70#ibcon#about to write, iclass 17, count 2 2006.202.00:46:20.70#ibcon#wrote, iclass 17, count 2 2006.202.00:46:20.70#ibcon#about to read 3, iclass 17, count 2 2006.202.00:46:20.73#ibcon#read 3, iclass 17, count 2 2006.202.00:46:20.73#ibcon#about to read 4, iclass 17, count 2 2006.202.00:46:20.73#ibcon#read 4, iclass 17, count 2 2006.202.00:46:20.73#ibcon#about to read 5, iclass 17, count 2 2006.202.00:46:20.73#ibcon#read 5, iclass 17, count 2 2006.202.00:46:20.73#ibcon#about to read 6, iclass 17, count 2 2006.202.00:46:20.73#ibcon#read 6, iclass 17, count 2 2006.202.00:46:20.73#ibcon#end of sib2, iclass 17, count 2 2006.202.00:46:20.73#ibcon#*after write, iclass 17, count 2 2006.202.00:46:20.73#ibcon#*before return 0, iclass 17, count 2 2006.202.00:46:20.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:46:20.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.202.00:46:20.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.202.00:46:20.73#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:20.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:46:20.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:46:20.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:46:20.85#ibcon#enter wrdev, iclass 17, count 0 2006.202.00:46:20.85#ibcon#first serial, iclass 17, count 0 2006.202.00:46:20.85#ibcon#enter sib2, iclass 17, count 0 2006.202.00:46:20.85#ibcon#flushed, iclass 17, count 0 2006.202.00:46:20.85#ibcon#about to write, iclass 17, count 0 2006.202.00:46:20.85#ibcon#wrote, iclass 17, count 0 2006.202.00:46:20.85#ibcon#about to read 3, iclass 17, count 0 2006.202.00:46:20.87#ibcon#read 3, iclass 17, count 0 2006.202.00:46:20.87#ibcon#about to read 4, iclass 17, count 0 2006.202.00:46:20.87#ibcon#read 4, iclass 17, count 0 2006.202.00:46:20.87#ibcon#about to read 5, iclass 17, count 0 2006.202.00:46:20.87#ibcon#read 5, iclass 17, count 0 2006.202.00:46:20.87#ibcon#about to read 6, iclass 17, count 0 2006.202.00:46:20.87#ibcon#read 6, iclass 17, count 0 2006.202.00:46:20.87#ibcon#end of sib2, iclass 17, count 0 2006.202.00:46:20.87#ibcon#*mode == 0, iclass 17, count 0 2006.202.00:46:20.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.00:46:20.87#ibcon#[25=USB\r\n] 2006.202.00:46:20.87#ibcon#*before write, iclass 17, count 0 2006.202.00:46:20.87#ibcon#enter sib2, iclass 17, count 0 2006.202.00:46:20.87#ibcon#flushed, iclass 17, count 0 2006.202.00:46:20.87#ibcon#about to write, iclass 17, count 0 2006.202.00:46:20.87#ibcon#wrote, iclass 17, count 0 2006.202.00:46:20.87#ibcon#about to read 3, iclass 17, count 0 2006.202.00:46:20.90#ibcon#read 3, iclass 17, count 0 2006.202.00:46:20.90#ibcon#about to read 4, iclass 17, count 0 2006.202.00:46:20.90#ibcon#read 4, iclass 17, count 0 2006.202.00:46:20.90#ibcon#about to read 5, iclass 17, count 0 2006.202.00:46:20.90#ibcon#read 5, iclass 17, count 0 2006.202.00:46:20.90#ibcon#about to read 6, iclass 17, count 0 2006.202.00:46:20.90#ibcon#read 6, iclass 17, count 0 2006.202.00:46:20.90#ibcon#end of sib2, iclass 17, count 0 2006.202.00:46:20.90#ibcon#*after write, iclass 17, count 0 2006.202.00:46:20.90#ibcon#*before return 0, iclass 17, count 0 2006.202.00:46:20.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:46:20.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.202.00:46:20.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.00:46:20.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.00:46:20.90$vck44/vblo=1,629.99 2006.202.00:46:20.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.202.00:46:20.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.202.00:46:20.90#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:20.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:46:20.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:46:20.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:46:20.90#ibcon#enter wrdev, iclass 19, count 0 2006.202.00:46:20.90#ibcon#first serial, iclass 19, count 0 2006.202.00:46:20.90#ibcon#enter sib2, iclass 19, count 0 2006.202.00:46:20.90#ibcon#flushed, iclass 19, count 0 2006.202.00:46:20.90#ibcon#about to write, iclass 19, count 0 2006.202.00:46:20.90#ibcon#wrote, iclass 19, count 0 2006.202.00:46:20.90#ibcon#about to read 3, iclass 19, count 0 2006.202.00:46:20.92#ibcon#read 3, iclass 19, count 0 2006.202.00:46:20.92#ibcon#about to read 4, iclass 19, count 0 2006.202.00:46:20.92#ibcon#read 4, iclass 19, count 0 2006.202.00:46:20.92#ibcon#about to read 5, iclass 19, count 0 2006.202.00:46:20.92#ibcon#read 5, iclass 19, count 0 2006.202.00:46:20.92#ibcon#about to read 6, iclass 19, count 0 2006.202.00:46:20.92#ibcon#read 6, iclass 19, count 0 2006.202.00:46:20.92#ibcon#end of sib2, iclass 19, count 0 2006.202.00:46:20.92#ibcon#*mode == 0, iclass 19, count 0 2006.202.00:46:20.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.00:46:20.92#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.00:46:20.92#ibcon#*before write, iclass 19, count 0 2006.202.00:46:20.92#ibcon#enter sib2, iclass 19, count 0 2006.202.00:46:20.92#ibcon#flushed, iclass 19, count 0 2006.202.00:46:20.92#ibcon#about to write, iclass 19, count 0 2006.202.00:46:20.92#ibcon#wrote, iclass 19, count 0 2006.202.00:46:20.92#ibcon#about to read 3, iclass 19, count 0 2006.202.00:46:20.96#ibcon#read 3, iclass 19, count 0 2006.202.00:46:20.96#ibcon#about to read 4, iclass 19, count 0 2006.202.00:46:20.96#ibcon#read 4, iclass 19, count 0 2006.202.00:46:20.96#ibcon#about to read 5, iclass 19, count 0 2006.202.00:46:20.96#ibcon#read 5, iclass 19, count 0 2006.202.00:46:20.96#ibcon#about to read 6, iclass 19, count 0 2006.202.00:46:20.96#ibcon#read 6, iclass 19, count 0 2006.202.00:46:20.96#ibcon#end of sib2, iclass 19, count 0 2006.202.00:46:20.96#ibcon#*after write, iclass 19, count 0 2006.202.00:46:20.96#ibcon#*before return 0, iclass 19, count 0 2006.202.00:46:20.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:46:20.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.202.00:46:20.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.00:46:20.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.00:46:20.96$vck44/vb=1,4 2006.202.00:46:20.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.202.00:46:20.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.202.00:46:20.96#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:20.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:46:20.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:46:20.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:46:20.96#ibcon#enter wrdev, iclass 21, count 2 2006.202.00:46:20.96#ibcon#first serial, iclass 21, count 2 2006.202.00:46:20.96#ibcon#enter sib2, iclass 21, count 2 2006.202.00:46:20.96#ibcon#flushed, iclass 21, count 2 2006.202.00:46:20.96#ibcon#about to write, iclass 21, count 2 2006.202.00:46:20.96#ibcon#wrote, iclass 21, count 2 2006.202.00:46:20.96#ibcon#about to read 3, iclass 21, count 2 2006.202.00:46:20.98#ibcon#read 3, iclass 21, count 2 2006.202.00:46:20.98#ibcon#about to read 4, iclass 21, count 2 2006.202.00:46:20.98#ibcon#read 4, iclass 21, count 2 2006.202.00:46:20.98#ibcon#about to read 5, iclass 21, count 2 2006.202.00:46:20.98#ibcon#read 5, iclass 21, count 2 2006.202.00:46:20.98#ibcon#about to read 6, iclass 21, count 2 2006.202.00:46:20.98#ibcon#read 6, iclass 21, count 2 2006.202.00:46:20.98#ibcon#end of sib2, iclass 21, count 2 2006.202.00:46:20.98#ibcon#*mode == 0, iclass 21, count 2 2006.202.00:46:20.98#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.202.00:46:20.98#ibcon#[27=AT01-04\r\n] 2006.202.00:46:20.98#ibcon#*before write, iclass 21, count 2 2006.202.00:46:20.98#ibcon#enter sib2, iclass 21, count 2 2006.202.00:46:20.98#ibcon#flushed, iclass 21, count 2 2006.202.00:46:20.98#ibcon#about to write, iclass 21, count 2 2006.202.00:46:20.98#ibcon#wrote, iclass 21, count 2 2006.202.00:46:20.98#ibcon#about to read 3, iclass 21, count 2 2006.202.00:46:21.01#ibcon#read 3, iclass 21, count 2 2006.202.00:46:21.01#ibcon#about to read 4, iclass 21, count 2 2006.202.00:46:21.01#ibcon#read 4, iclass 21, count 2 2006.202.00:46:21.01#ibcon#about to read 5, iclass 21, count 2 2006.202.00:46:21.01#ibcon#read 5, iclass 21, count 2 2006.202.00:46:21.01#ibcon#about to read 6, iclass 21, count 2 2006.202.00:46:21.01#ibcon#read 6, iclass 21, count 2 2006.202.00:46:21.01#ibcon#end of sib2, iclass 21, count 2 2006.202.00:46:21.01#ibcon#*after write, iclass 21, count 2 2006.202.00:46:21.01#ibcon#*before return 0, iclass 21, count 2 2006.202.00:46:21.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:46:21.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.202.00:46:21.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.202.00:46:21.01#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:21.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:46:21.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:46:21.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:46:21.13#ibcon#enter wrdev, iclass 21, count 0 2006.202.00:46:21.13#ibcon#first serial, iclass 21, count 0 2006.202.00:46:21.13#ibcon#enter sib2, iclass 21, count 0 2006.202.00:46:21.13#ibcon#flushed, iclass 21, count 0 2006.202.00:46:21.13#ibcon#about to write, iclass 21, count 0 2006.202.00:46:21.13#ibcon#wrote, iclass 21, count 0 2006.202.00:46:21.13#ibcon#about to read 3, iclass 21, count 0 2006.202.00:46:21.15#ibcon#read 3, iclass 21, count 0 2006.202.00:46:21.15#ibcon#about to read 4, iclass 21, count 0 2006.202.00:46:21.15#ibcon#read 4, iclass 21, count 0 2006.202.00:46:21.15#ibcon#about to read 5, iclass 21, count 0 2006.202.00:46:21.15#ibcon#read 5, iclass 21, count 0 2006.202.00:46:21.15#ibcon#about to read 6, iclass 21, count 0 2006.202.00:46:21.15#ibcon#read 6, iclass 21, count 0 2006.202.00:46:21.15#ibcon#end of sib2, iclass 21, count 0 2006.202.00:46:21.15#ibcon#*mode == 0, iclass 21, count 0 2006.202.00:46:21.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.00:46:21.15#ibcon#[27=USB\r\n] 2006.202.00:46:21.15#ibcon#*before write, iclass 21, count 0 2006.202.00:46:21.15#ibcon#enter sib2, iclass 21, count 0 2006.202.00:46:21.15#ibcon#flushed, iclass 21, count 0 2006.202.00:46:21.15#ibcon#about to write, iclass 21, count 0 2006.202.00:46:21.15#ibcon#wrote, iclass 21, count 0 2006.202.00:46:21.15#ibcon#about to read 3, iclass 21, count 0 2006.202.00:46:21.18#ibcon#read 3, iclass 21, count 0 2006.202.00:46:21.18#ibcon#about to read 4, iclass 21, count 0 2006.202.00:46:21.18#ibcon#read 4, iclass 21, count 0 2006.202.00:46:21.18#ibcon#about to read 5, iclass 21, count 0 2006.202.00:46:21.18#ibcon#read 5, iclass 21, count 0 2006.202.00:46:21.18#ibcon#about to read 6, iclass 21, count 0 2006.202.00:46:21.18#ibcon#read 6, iclass 21, count 0 2006.202.00:46:21.18#ibcon#end of sib2, iclass 21, count 0 2006.202.00:46:21.18#ibcon#*after write, iclass 21, count 0 2006.202.00:46:21.18#ibcon#*before return 0, iclass 21, count 0 2006.202.00:46:21.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:46:21.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.202.00:46:21.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.00:46:21.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.00:46:21.18$vck44/vblo=2,634.99 2006.202.00:46:21.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.00:46:21.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.00:46:21.18#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:21.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:21.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:21.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:21.18#ibcon#enter wrdev, iclass 23, count 0 2006.202.00:46:21.18#ibcon#first serial, iclass 23, count 0 2006.202.00:46:21.18#ibcon#enter sib2, iclass 23, count 0 2006.202.00:46:21.18#ibcon#flushed, iclass 23, count 0 2006.202.00:46:21.18#ibcon#about to write, iclass 23, count 0 2006.202.00:46:21.18#ibcon#wrote, iclass 23, count 0 2006.202.00:46:21.18#ibcon#about to read 3, iclass 23, count 0 2006.202.00:46:21.20#ibcon#read 3, iclass 23, count 0 2006.202.00:46:21.20#ibcon#about to read 4, iclass 23, count 0 2006.202.00:46:21.20#ibcon#read 4, iclass 23, count 0 2006.202.00:46:21.20#ibcon#about to read 5, iclass 23, count 0 2006.202.00:46:21.20#ibcon#read 5, iclass 23, count 0 2006.202.00:46:21.20#ibcon#about to read 6, iclass 23, count 0 2006.202.00:46:21.20#ibcon#read 6, iclass 23, count 0 2006.202.00:46:21.20#ibcon#end of sib2, iclass 23, count 0 2006.202.00:46:21.20#ibcon#*mode == 0, iclass 23, count 0 2006.202.00:46:21.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.00:46:21.20#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.00:46:21.20#ibcon#*before write, iclass 23, count 0 2006.202.00:46:21.20#ibcon#enter sib2, iclass 23, count 0 2006.202.00:46:21.20#ibcon#flushed, iclass 23, count 0 2006.202.00:46:21.20#ibcon#about to write, iclass 23, count 0 2006.202.00:46:21.20#ibcon#wrote, iclass 23, count 0 2006.202.00:46:21.20#ibcon#about to read 3, iclass 23, count 0 2006.202.00:46:21.24#ibcon#read 3, iclass 23, count 0 2006.202.00:46:21.24#ibcon#about to read 4, iclass 23, count 0 2006.202.00:46:21.24#ibcon#read 4, iclass 23, count 0 2006.202.00:46:21.24#ibcon#about to read 5, iclass 23, count 0 2006.202.00:46:21.24#ibcon#read 5, iclass 23, count 0 2006.202.00:46:21.24#ibcon#about to read 6, iclass 23, count 0 2006.202.00:46:21.24#ibcon#read 6, iclass 23, count 0 2006.202.00:46:21.24#ibcon#end of sib2, iclass 23, count 0 2006.202.00:46:21.24#ibcon#*after write, iclass 23, count 0 2006.202.00:46:21.24#ibcon#*before return 0, iclass 23, count 0 2006.202.00:46:21.24#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:21.24#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.00:46:21.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.00:46:21.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.00:46:21.24$vck44/vb=2,5 2006.202.00:46:21.24#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.202.00:46:21.24#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.202.00:46:21.24#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:21.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:21.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:21.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:21.30#ibcon#enter wrdev, iclass 25, count 2 2006.202.00:46:21.30#ibcon#first serial, iclass 25, count 2 2006.202.00:46:21.30#ibcon#enter sib2, iclass 25, count 2 2006.202.00:46:21.30#ibcon#flushed, iclass 25, count 2 2006.202.00:46:21.30#ibcon#about to write, iclass 25, count 2 2006.202.00:46:21.30#ibcon#wrote, iclass 25, count 2 2006.202.00:46:21.30#ibcon#about to read 3, iclass 25, count 2 2006.202.00:46:21.32#ibcon#read 3, iclass 25, count 2 2006.202.00:46:21.32#ibcon#about to read 4, iclass 25, count 2 2006.202.00:46:21.32#ibcon#read 4, iclass 25, count 2 2006.202.00:46:21.32#ibcon#about to read 5, iclass 25, count 2 2006.202.00:46:21.32#ibcon#read 5, iclass 25, count 2 2006.202.00:46:21.32#ibcon#about to read 6, iclass 25, count 2 2006.202.00:46:21.32#ibcon#read 6, iclass 25, count 2 2006.202.00:46:21.32#ibcon#end of sib2, iclass 25, count 2 2006.202.00:46:21.32#ibcon#*mode == 0, iclass 25, count 2 2006.202.00:46:21.32#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.202.00:46:21.32#ibcon#[27=AT02-05\r\n] 2006.202.00:46:21.32#ibcon#*before write, iclass 25, count 2 2006.202.00:46:21.32#ibcon#enter sib2, iclass 25, count 2 2006.202.00:46:21.32#ibcon#flushed, iclass 25, count 2 2006.202.00:46:21.32#ibcon#about to write, iclass 25, count 2 2006.202.00:46:21.32#ibcon#wrote, iclass 25, count 2 2006.202.00:46:21.32#ibcon#about to read 3, iclass 25, count 2 2006.202.00:46:21.35#ibcon#read 3, iclass 25, count 2 2006.202.00:46:21.35#ibcon#about to read 4, iclass 25, count 2 2006.202.00:46:21.35#ibcon#read 4, iclass 25, count 2 2006.202.00:46:21.35#ibcon#about to read 5, iclass 25, count 2 2006.202.00:46:21.35#ibcon#read 5, iclass 25, count 2 2006.202.00:46:21.35#ibcon#about to read 6, iclass 25, count 2 2006.202.00:46:21.35#ibcon#read 6, iclass 25, count 2 2006.202.00:46:21.35#ibcon#end of sib2, iclass 25, count 2 2006.202.00:46:21.35#ibcon#*after write, iclass 25, count 2 2006.202.00:46:21.35#ibcon#*before return 0, iclass 25, count 2 2006.202.00:46:21.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:21.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.202.00:46:21.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.202.00:46:21.35#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:21.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:21.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:21.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:21.47#ibcon#enter wrdev, iclass 25, count 0 2006.202.00:46:21.47#ibcon#first serial, iclass 25, count 0 2006.202.00:46:21.47#ibcon#enter sib2, iclass 25, count 0 2006.202.00:46:21.47#ibcon#flushed, iclass 25, count 0 2006.202.00:46:21.47#ibcon#about to write, iclass 25, count 0 2006.202.00:46:21.47#ibcon#wrote, iclass 25, count 0 2006.202.00:46:21.47#ibcon#about to read 3, iclass 25, count 0 2006.202.00:46:21.49#ibcon#read 3, iclass 25, count 0 2006.202.00:46:21.49#ibcon#about to read 4, iclass 25, count 0 2006.202.00:46:21.49#ibcon#read 4, iclass 25, count 0 2006.202.00:46:21.49#ibcon#about to read 5, iclass 25, count 0 2006.202.00:46:21.49#ibcon#read 5, iclass 25, count 0 2006.202.00:46:21.49#ibcon#about to read 6, iclass 25, count 0 2006.202.00:46:21.49#ibcon#read 6, iclass 25, count 0 2006.202.00:46:21.49#ibcon#end of sib2, iclass 25, count 0 2006.202.00:46:21.49#ibcon#*mode == 0, iclass 25, count 0 2006.202.00:46:21.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.00:46:21.49#ibcon#[27=USB\r\n] 2006.202.00:46:21.49#ibcon#*before write, iclass 25, count 0 2006.202.00:46:21.49#ibcon#enter sib2, iclass 25, count 0 2006.202.00:46:21.49#ibcon#flushed, iclass 25, count 0 2006.202.00:46:21.49#ibcon#about to write, iclass 25, count 0 2006.202.00:46:21.49#ibcon#wrote, iclass 25, count 0 2006.202.00:46:21.49#ibcon#about to read 3, iclass 25, count 0 2006.202.00:46:21.52#ibcon#read 3, iclass 25, count 0 2006.202.00:46:21.52#ibcon#about to read 4, iclass 25, count 0 2006.202.00:46:21.52#ibcon#read 4, iclass 25, count 0 2006.202.00:46:21.52#ibcon#about to read 5, iclass 25, count 0 2006.202.00:46:21.52#ibcon#read 5, iclass 25, count 0 2006.202.00:46:21.52#ibcon#about to read 6, iclass 25, count 0 2006.202.00:46:21.52#ibcon#read 6, iclass 25, count 0 2006.202.00:46:21.52#ibcon#end of sib2, iclass 25, count 0 2006.202.00:46:21.52#ibcon#*after write, iclass 25, count 0 2006.202.00:46:21.52#ibcon#*before return 0, iclass 25, count 0 2006.202.00:46:21.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:21.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.202.00:46:21.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.00:46:21.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.00:46:21.52$vck44/vblo=3,649.99 2006.202.00:46:21.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.202.00:46:21.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.202.00:46:21.52#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:21.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:21.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:21.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:21.52#ibcon#enter wrdev, iclass 27, count 0 2006.202.00:46:21.52#ibcon#first serial, iclass 27, count 0 2006.202.00:46:21.52#ibcon#enter sib2, iclass 27, count 0 2006.202.00:46:21.52#ibcon#flushed, iclass 27, count 0 2006.202.00:46:21.52#ibcon#about to write, iclass 27, count 0 2006.202.00:46:21.52#ibcon#wrote, iclass 27, count 0 2006.202.00:46:21.52#ibcon#about to read 3, iclass 27, count 0 2006.202.00:46:21.54#ibcon#read 3, iclass 27, count 0 2006.202.00:46:21.54#ibcon#about to read 4, iclass 27, count 0 2006.202.00:46:21.54#ibcon#read 4, iclass 27, count 0 2006.202.00:46:21.54#ibcon#about to read 5, iclass 27, count 0 2006.202.00:46:21.54#ibcon#read 5, iclass 27, count 0 2006.202.00:46:21.54#ibcon#about to read 6, iclass 27, count 0 2006.202.00:46:21.54#ibcon#read 6, iclass 27, count 0 2006.202.00:46:21.54#ibcon#end of sib2, iclass 27, count 0 2006.202.00:46:21.54#ibcon#*mode == 0, iclass 27, count 0 2006.202.00:46:21.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.00:46:21.54#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.00:46:21.54#ibcon#*before write, iclass 27, count 0 2006.202.00:46:21.54#ibcon#enter sib2, iclass 27, count 0 2006.202.00:46:21.54#ibcon#flushed, iclass 27, count 0 2006.202.00:46:21.54#ibcon#about to write, iclass 27, count 0 2006.202.00:46:21.54#ibcon#wrote, iclass 27, count 0 2006.202.00:46:21.54#ibcon#about to read 3, iclass 27, count 0 2006.202.00:46:21.58#ibcon#read 3, iclass 27, count 0 2006.202.00:46:21.58#ibcon#about to read 4, iclass 27, count 0 2006.202.00:46:21.58#ibcon#read 4, iclass 27, count 0 2006.202.00:46:21.58#ibcon#about to read 5, iclass 27, count 0 2006.202.00:46:21.58#ibcon#read 5, iclass 27, count 0 2006.202.00:46:21.58#ibcon#about to read 6, iclass 27, count 0 2006.202.00:46:21.58#ibcon#read 6, iclass 27, count 0 2006.202.00:46:21.58#ibcon#end of sib2, iclass 27, count 0 2006.202.00:46:21.58#ibcon#*after write, iclass 27, count 0 2006.202.00:46:21.58#ibcon#*before return 0, iclass 27, count 0 2006.202.00:46:21.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:21.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.202.00:46:21.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.00:46:21.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.00:46:21.58$vck44/vb=3,4 2006.202.00:46:21.58#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.00:46:21.58#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.00:46:21.58#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:21.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:21.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:21.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:21.64#ibcon#enter wrdev, iclass 29, count 2 2006.202.00:46:21.64#ibcon#first serial, iclass 29, count 2 2006.202.00:46:21.64#ibcon#enter sib2, iclass 29, count 2 2006.202.00:46:21.64#ibcon#flushed, iclass 29, count 2 2006.202.00:46:21.64#ibcon#about to write, iclass 29, count 2 2006.202.00:46:21.64#ibcon#wrote, iclass 29, count 2 2006.202.00:46:21.64#ibcon#about to read 3, iclass 29, count 2 2006.202.00:46:21.66#ibcon#read 3, iclass 29, count 2 2006.202.00:46:21.66#ibcon#about to read 4, iclass 29, count 2 2006.202.00:46:21.66#ibcon#read 4, iclass 29, count 2 2006.202.00:46:21.66#ibcon#about to read 5, iclass 29, count 2 2006.202.00:46:21.66#ibcon#read 5, iclass 29, count 2 2006.202.00:46:21.66#ibcon#about to read 6, iclass 29, count 2 2006.202.00:46:21.66#ibcon#read 6, iclass 29, count 2 2006.202.00:46:21.66#ibcon#end of sib2, iclass 29, count 2 2006.202.00:46:21.66#ibcon#*mode == 0, iclass 29, count 2 2006.202.00:46:21.66#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.00:46:21.66#ibcon#[27=AT03-04\r\n] 2006.202.00:46:21.66#ibcon#*before write, iclass 29, count 2 2006.202.00:46:21.66#ibcon#enter sib2, iclass 29, count 2 2006.202.00:46:21.66#ibcon#flushed, iclass 29, count 2 2006.202.00:46:21.66#ibcon#about to write, iclass 29, count 2 2006.202.00:46:21.66#ibcon#wrote, iclass 29, count 2 2006.202.00:46:21.66#ibcon#about to read 3, iclass 29, count 2 2006.202.00:46:21.69#ibcon#read 3, iclass 29, count 2 2006.202.00:46:21.69#ibcon#about to read 4, iclass 29, count 2 2006.202.00:46:21.69#ibcon#read 4, iclass 29, count 2 2006.202.00:46:21.69#ibcon#about to read 5, iclass 29, count 2 2006.202.00:46:21.69#ibcon#read 5, iclass 29, count 2 2006.202.00:46:21.69#ibcon#about to read 6, iclass 29, count 2 2006.202.00:46:21.69#ibcon#read 6, iclass 29, count 2 2006.202.00:46:21.69#ibcon#end of sib2, iclass 29, count 2 2006.202.00:46:21.69#ibcon#*after write, iclass 29, count 2 2006.202.00:46:21.69#ibcon#*before return 0, iclass 29, count 2 2006.202.00:46:21.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:21.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.00:46:21.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.00:46:21.69#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:21.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:21.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:21.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:21.81#ibcon#enter wrdev, iclass 29, count 0 2006.202.00:46:21.81#ibcon#first serial, iclass 29, count 0 2006.202.00:46:21.81#ibcon#enter sib2, iclass 29, count 0 2006.202.00:46:21.81#ibcon#flushed, iclass 29, count 0 2006.202.00:46:21.81#ibcon#about to write, iclass 29, count 0 2006.202.00:46:21.81#ibcon#wrote, iclass 29, count 0 2006.202.00:46:21.81#ibcon#about to read 3, iclass 29, count 0 2006.202.00:46:21.83#ibcon#read 3, iclass 29, count 0 2006.202.00:46:21.83#ibcon#about to read 4, iclass 29, count 0 2006.202.00:46:21.83#ibcon#read 4, iclass 29, count 0 2006.202.00:46:21.83#ibcon#about to read 5, iclass 29, count 0 2006.202.00:46:21.83#ibcon#read 5, iclass 29, count 0 2006.202.00:46:21.83#ibcon#about to read 6, iclass 29, count 0 2006.202.00:46:21.83#ibcon#read 6, iclass 29, count 0 2006.202.00:46:21.83#ibcon#end of sib2, iclass 29, count 0 2006.202.00:46:21.83#ibcon#*mode == 0, iclass 29, count 0 2006.202.00:46:21.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.00:46:21.83#ibcon#[27=USB\r\n] 2006.202.00:46:21.83#ibcon#*before write, iclass 29, count 0 2006.202.00:46:21.83#ibcon#enter sib2, iclass 29, count 0 2006.202.00:46:21.83#ibcon#flushed, iclass 29, count 0 2006.202.00:46:21.83#ibcon#about to write, iclass 29, count 0 2006.202.00:46:21.83#ibcon#wrote, iclass 29, count 0 2006.202.00:46:21.83#ibcon#about to read 3, iclass 29, count 0 2006.202.00:46:21.86#ibcon#read 3, iclass 29, count 0 2006.202.00:46:21.86#ibcon#about to read 4, iclass 29, count 0 2006.202.00:46:21.86#ibcon#read 4, iclass 29, count 0 2006.202.00:46:21.86#ibcon#about to read 5, iclass 29, count 0 2006.202.00:46:21.86#ibcon#read 5, iclass 29, count 0 2006.202.00:46:21.86#ibcon#about to read 6, iclass 29, count 0 2006.202.00:46:21.86#ibcon#read 6, iclass 29, count 0 2006.202.00:46:21.86#ibcon#end of sib2, iclass 29, count 0 2006.202.00:46:21.86#ibcon#*after write, iclass 29, count 0 2006.202.00:46:21.86#ibcon#*before return 0, iclass 29, count 0 2006.202.00:46:21.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:21.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.00:46:21.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.00:46:21.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.00:46:21.86$vck44/vblo=4,679.99 2006.202.00:46:21.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.202.00:46:21.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.202.00:46:21.86#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:21.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:21.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:21.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:21.86#ibcon#enter wrdev, iclass 31, count 0 2006.202.00:46:21.86#ibcon#first serial, iclass 31, count 0 2006.202.00:46:21.86#ibcon#enter sib2, iclass 31, count 0 2006.202.00:46:21.86#ibcon#flushed, iclass 31, count 0 2006.202.00:46:21.86#ibcon#about to write, iclass 31, count 0 2006.202.00:46:21.86#ibcon#wrote, iclass 31, count 0 2006.202.00:46:21.86#ibcon#about to read 3, iclass 31, count 0 2006.202.00:46:21.88#ibcon#read 3, iclass 31, count 0 2006.202.00:46:21.88#ibcon#about to read 4, iclass 31, count 0 2006.202.00:46:21.88#ibcon#read 4, iclass 31, count 0 2006.202.00:46:21.88#ibcon#about to read 5, iclass 31, count 0 2006.202.00:46:21.88#ibcon#read 5, iclass 31, count 0 2006.202.00:46:21.88#ibcon#about to read 6, iclass 31, count 0 2006.202.00:46:21.88#ibcon#read 6, iclass 31, count 0 2006.202.00:46:21.88#ibcon#end of sib2, iclass 31, count 0 2006.202.00:46:21.88#ibcon#*mode == 0, iclass 31, count 0 2006.202.00:46:21.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.00:46:21.88#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.00:46:21.88#ibcon#*before write, iclass 31, count 0 2006.202.00:46:21.88#ibcon#enter sib2, iclass 31, count 0 2006.202.00:46:21.88#ibcon#flushed, iclass 31, count 0 2006.202.00:46:21.88#ibcon#about to write, iclass 31, count 0 2006.202.00:46:21.88#ibcon#wrote, iclass 31, count 0 2006.202.00:46:21.88#ibcon#about to read 3, iclass 31, count 0 2006.202.00:46:21.92#ibcon#read 3, iclass 31, count 0 2006.202.00:46:21.92#ibcon#about to read 4, iclass 31, count 0 2006.202.00:46:21.92#ibcon#read 4, iclass 31, count 0 2006.202.00:46:21.92#ibcon#about to read 5, iclass 31, count 0 2006.202.00:46:21.92#ibcon#read 5, iclass 31, count 0 2006.202.00:46:21.92#ibcon#about to read 6, iclass 31, count 0 2006.202.00:46:21.92#ibcon#read 6, iclass 31, count 0 2006.202.00:46:21.92#ibcon#end of sib2, iclass 31, count 0 2006.202.00:46:21.92#ibcon#*after write, iclass 31, count 0 2006.202.00:46:21.92#ibcon#*before return 0, iclass 31, count 0 2006.202.00:46:21.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:21.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.202.00:46:21.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.00:46:21.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.00:46:21.92$vck44/vb=4,5 2006.202.00:46:21.92#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.202.00:46:21.92#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.202.00:46:21.92#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:21.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:21.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:21.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:21.98#ibcon#enter wrdev, iclass 33, count 2 2006.202.00:46:21.98#ibcon#first serial, iclass 33, count 2 2006.202.00:46:21.98#ibcon#enter sib2, iclass 33, count 2 2006.202.00:46:21.98#ibcon#flushed, iclass 33, count 2 2006.202.00:46:21.98#ibcon#about to write, iclass 33, count 2 2006.202.00:46:21.98#ibcon#wrote, iclass 33, count 2 2006.202.00:46:21.98#ibcon#about to read 3, iclass 33, count 2 2006.202.00:46:22.00#ibcon#read 3, iclass 33, count 2 2006.202.00:46:22.00#ibcon#about to read 4, iclass 33, count 2 2006.202.00:46:22.00#ibcon#read 4, iclass 33, count 2 2006.202.00:46:22.00#ibcon#about to read 5, iclass 33, count 2 2006.202.00:46:22.00#ibcon#read 5, iclass 33, count 2 2006.202.00:46:22.00#ibcon#about to read 6, iclass 33, count 2 2006.202.00:46:22.00#ibcon#read 6, iclass 33, count 2 2006.202.00:46:22.00#ibcon#end of sib2, iclass 33, count 2 2006.202.00:46:22.00#ibcon#*mode == 0, iclass 33, count 2 2006.202.00:46:22.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.202.00:46:22.00#ibcon#[27=AT04-05\r\n] 2006.202.00:46:22.00#ibcon#*before write, iclass 33, count 2 2006.202.00:46:22.00#ibcon#enter sib2, iclass 33, count 2 2006.202.00:46:22.00#ibcon#flushed, iclass 33, count 2 2006.202.00:46:22.00#ibcon#about to write, iclass 33, count 2 2006.202.00:46:22.00#ibcon#wrote, iclass 33, count 2 2006.202.00:46:22.00#ibcon#about to read 3, iclass 33, count 2 2006.202.00:46:22.03#ibcon#read 3, iclass 33, count 2 2006.202.00:46:22.03#ibcon#about to read 4, iclass 33, count 2 2006.202.00:46:22.03#ibcon#read 4, iclass 33, count 2 2006.202.00:46:22.03#ibcon#about to read 5, iclass 33, count 2 2006.202.00:46:22.03#ibcon#read 5, iclass 33, count 2 2006.202.00:46:22.03#ibcon#about to read 6, iclass 33, count 2 2006.202.00:46:22.03#ibcon#read 6, iclass 33, count 2 2006.202.00:46:22.03#ibcon#end of sib2, iclass 33, count 2 2006.202.00:46:22.03#ibcon#*after write, iclass 33, count 2 2006.202.00:46:22.03#ibcon#*before return 0, iclass 33, count 2 2006.202.00:46:22.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:22.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.202.00:46:22.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.202.00:46:22.03#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:22.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:22.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:22.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:22.15#ibcon#enter wrdev, iclass 33, count 0 2006.202.00:46:22.15#ibcon#first serial, iclass 33, count 0 2006.202.00:46:22.15#ibcon#enter sib2, iclass 33, count 0 2006.202.00:46:22.15#ibcon#flushed, iclass 33, count 0 2006.202.00:46:22.15#ibcon#about to write, iclass 33, count 0 2006.202.00:46:22.15#ibcon#wrote, iclass 33, count 0 2006.202.00:46:22.15#ibcon#about to read 3, iclass 33, count 0 2006.202.00:46:22.17#ibcon#read 3, iclass 33, count 0 2006.202.00:46:22.17#ibcon#about to read 4, iclass 33, count 0 2006.202.00:46:22.17#ibcon#read 4, iclass 33, count 0 2006.202.00:46:22.17#ibcon#about to read 5, iclass 33, count 0 2006.202.00:46:22.17#ibcon#read 5, iclass 33, count 0 2006.202.00:46:22.17#ibcon#about to read 6, iclass 33, count 0 2006.202.00:46:22.17#ibcon#read 6, iclass 33, count 0 2006.202.00:46:22.17#ibcon#end of sib2, iclass 33, count 0 2006.202.00:46:22.17#ibcon#*mode == 0, iclass 33, count 0 2006.202.00:46:22.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.00:46:22.17#ibcon#[27=USB\r\n] 2006.202.00:46:22.17#ibcon#*before write, iclass 33, count 0 2006.202.00:46:22.17#ibcon#enter sib2, iclass 33, count 0 2006.202.00:46:22.17#ibcon#flushed, iclass 33, count 0 2006.202.00:46:22.17#ibcon#about to write, iclass 33, count 0 2006.202.00:46:22.17#ibcon#wrote, iclass 33, count 0 2006.202.00:46:22.17#ibcon#about to read 3, iclass 33, count 0 2006.202.00:46:22.20#ibcon#read 3, iclass 33, count 0 2006.202.00:46:22.20#ibcon#about to read 4, iclass 33, count 0 2006.202.00:46:22.20#ibcon#read 4, iclass 33, count 0 2006.202.00:46:22.20#ibcon#about to read 5, iclass 33, count 0 2006.202.00:46:22.20#ibcon#read 5, iclass 33, count 0 2006.202.00:46:22.20#ibcon#about to read 6, iclass 33, count 0 2006.202.00:46:22.20#ibcon#read 6, iclass 33, count 0 2006.202.00:46:22.20#ibcon#end of sib2, iclass 33, count 0 2006.202.00:46:22.20#ibcon#*after write, iclass 33, count 0 2006.202.00:46:22.20#ibcon#*before return 0, iclass 33, count 0 2006.202.00:46:22.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:22.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.202.00:46:22.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.00:46:22.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.00:46:22.20$vck44/vblo=5,709.99 2006.202.00:46:22.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.202.00:46:22.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.202.00:46:22.20#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:22.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:22.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:22.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:22.20#ibcon#enter wrdev, iclass 35, count 0 2006.202.00:46:22.20#ibcon#first serial, iclass 35, count 0 2006.202.00:46:22.20#ibcon#enter sib2, iclass 35, count 0 2006.202.00:46:22.20#ibcon#flushed, iclass 35, count 0 2006.202.00:46:22.20#ibcon#about to write, iclass 35, count 0 2006.202.00:46:22.20#ibcon#wrote, iclass 35, count 0 2006.202.00:46:22.20#ibcon#about to read 3, iclass 35, count 0 2006.202.00:46:22.22#ibcon#read 3, iclass 35, count 0 2006.202.00:46:22.22#ibcon#about to read 4, iclass 35, count 0 2006.202.00:46:22.22#ibcon#read 4, iclass 35, count 0 2006.202.00:46:22.22#ibcon#about to read 5, iclass 35, count 0 2006.202.00:46:22.22#ibcon#read 5, iclass 35, count 0 2006.202.00:46:22.22#ibcon#about to read 6, iclass 35, count 0 2006.202.00:46:22.22#ibcon#read 6, iclass 35, count 0 2006.202.00:46:22.22#ibcon#end of sib2, iclass 35, count 0 2006.202.00:46:22.22#ibcon#*mode == 0, iclass 35, count 0 2006.202.00:46:22.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.00:46:22.22#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.00:46:22.22#ibcon#*before write, iclass 35, count 0 2006.202.00:46:22.22#ibcon#enter sib2, iclass 35, count 0 2006.202.00:46:22.22#ibcon#flushed, iclass 35, count 0 2006.202.00:46:22.22#ibcon#about to write, iclass 35, count 0 2006.202.00:46:22.22#ibcon#wrote, iclass 35, count 0 2006.202.00:46:22.22#ibcon#about to read 3, iclass 35, count 0 2006.202.00:46:22.26#ibcon#read 3, iclass 35, count 0 2006.202.00:46:22.26#ibcon#about to read 4, iclass 35, count 0 2006.202.00:46:22.26#ibcon#read 4, iclass 35, count 0 2006.202.00:46:22.26#ibcon#about to read 5, iclass 35, count 0 2006.202.00:46:22.26#ibcon#read 5, iclass 35, count 0 2006.202.00:46:22.26#ibcon#about to read 6, iclass 35, count 0 2006.202.00:46:22.26#ibcon#read 6, iclass 35, count 0 2006.202.00:46:22.26#ibcon#end of sib2, iclass 35, count 0 2006.202.00:46:22.26#ibcon#*after write, iclass 35, count 0 2006.202.00:46:22.26#ibcon#*before return 0, iclass 35, count 0 2006.202.00:46:22.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:22.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.202.00:46:22.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.00:46:22.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.00:46:22.26$vck44/vb=5,4 2006.202.00:46:22.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.202.00:46:22.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.202.00:46:22.26#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:22.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:22.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:22.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:22.32#ibcon#enter wrdev, iclass 37, count 2 2006.202.00:46:22.32#ibcon#first serial, iclass 37, count 2 2006.202.00:46:22.32#ibcon#enter sib2, iclass 37, count 2 2006.202.00:46:22.32#ibcon#flushed, iclass 37, count 2 2006.202.00:46:22.32#ibcon#about to write, iclass 37, count 2 2006.202.00:46:22.32#ibcon#wrote, iclass 37, count 2 2006.202.00:46:22.32#ibcon#about to read 3, iclass 37, count 2 2006.202.00:46:22.34#ibcon#read 3, iclass 37, count 2 2006.202.00:46:22.34#ibcon#about to read 4, iclass 37, count 2 2006.202.00:46:22.34#ibcon#read 4, iclass 37, count 2 2006.202.00:46:22.34#ibcon#about to read 5, iclass 37, count 2 2006.202.00:46:22.34#ibcon#read 5, iclass 37, count 2 2006.202.00:46:22.34#ibcon#about to read 6, iclass 37, count 2 2006.202.00:46:22.34#ibcon#read 6, iclass 37, count 2 2006.202.00:46:22.34#ibcon#end of sib2, iclass 37, count 2 2006.202.00:46:22.34#ibcon#*mode == 0, iclass 37, count 2 2006.202.00:46:22.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.202.00:46:22.34#ibcon#[27=AT05-04\r\n] 2006.202.00:46:22.34#ibcon#*before write, iclass 37, count 2 2006.202.00:46:22.34#ibcon#enter sib2, iclass 37, count 2 2006.202.00:46:22.34#ibcon#flushed, iclass 37, count 2 2006.202.00:46:22.34#ibcon#about to write, iclass 37, count 2 2006.202.00:46:22.34#ibcon#wrote, iclass 37, count 2 2006.202.00:46:22.34#ibcon#about to read 3, iclass 37, count 2 2006.202.00:46:22.37#ibcon#read 3, iclass 37, count 2 2006.202.00:46:22.37#ibcon#about to read 4, iclass 37, count 2 2006.202.00:46:22.37#ibcon#read 4, iclass 37, count 2 2006.202.00:46:22.37#ibcon#about to read 5, iclass 37, count 2 2006.202.00:46:22.37#ibcon#read 5, iclass 37, count 2 2006.202.00:46:22.37#ibcon#about to read 6, iclass 37, count 2 2006.202.00:46:22.37#ibcon#read 6, iclass 37, count 2 2006.202.00:46:22.37#ibcon#end of sib2, iclass 37, count 2 2006.202.00:46:22.37#ibcon#*after write, iclass 37, count 2 2006.202.00:46:22.37#ibcon#*before return 0, iclass 37, count 2 2006.202.00:46:22.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:22.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.202.00:46:22.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.202.00:46:22.37#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:22.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:22.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:22.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:22.49#ibcon#enter wrdev, iclass 37, count 0 2006.202.00:46:22.49#ibcon#first serial, iclass 37, count 0 2006.202.00:46:22.49#ibcon#enter sib2, iclass 37, count 0 2006.202.00:46:22.49#ibcon#flushed, iclass 37, count 0 2006.202.00:46:22.49#ibcon#about to write, iclass 37, count 0 2006.202.00:46:22.49#ibcon#wrote, iclass 37, count 0 2006.202.00:46:22.49#ibcon#about to read 3, iclass 37, count 0 2006.202.00:46:22.51#ibcon#read 3, iclass 37, count 0 2006.202.00:46:22.51#ibcon#about to read 4, iclass 37, count 0 2006.202.00:46:22.51#ibcon#read 4, iclass 37, count 0 2006.202.00:46:22.51#ibcon#about to read 5, iclass 37, count 0 2006.202.00:46:22.51#ibcon#read 5, iclass 37, count 0 2006.202.00:46:22.51#ibcon#about to read 6, iclass 37, count 0 2006.202.00:46:22.51#ibcon#read 6, iclass 37, count 0 2006.202.00:46:22.51#ibcon#end of sib2, iclass 37, count 0 2006.202.00:46:22.51#ibcon#*mode == 0, iclass 37, count 0 2006.202.00:46:22.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.00:46:22.51#ibcon#[27=USB\r\n] 2006.202.00:46:22.51#ibcon#*before write, iclass 37, count 0 2006.202.00:46:22.51#ibcon#enter sib2, iclass 37, count 0 2006.202.00:46:22.51#ibcon#flushed, iclass 37, count 0 2006.202.00:46:22.51#ibcon#about to write, iclass 37, count 0 2006.202.00:46:22.51#ibcon#wrote, iclass 37, count 0 2006.202.00:46:22.51#ibcon#about to read 3, iclass 37, count 0 2006.202.00:46:22.54#ibcon#read 3, iclass 37, count 0 2006.202.00:46:22.54#ibcon#about to read 4, iclass 37, count 0 2006.202.00:46:22.54#ibcon#read 4, iclass 37, count 0 2006.202.00:46:22.54#ibcon#about to read 5, iclass 37, count 0 2006.202.00:46:22.54#ibcon#read 5, iclass 37, count 0 2006.202.00:46:22.54#ibcon#about to read 6, iclass 37, count 0 2006.202.00:46:22.54#ibcon#read 6, iclass 37, count 0 2006.202.00:46:22.54#ibcon#end of sib2, iclass 37, count 0 2006.202.00:46:22.54#ibcon#*after write, iclass 37, count 0 2006.202.00:46:22.54#ibcon#*before return 0, iclass 37, count 0 2006.202.00:46:22.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:22.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.202.00:46:22.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.00:46:22.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.00:46:22.54$vck44/vblo=6,719.99 2006.202.00:46:22.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.202.00:46:22.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.202.00:46:22.54#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:22.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:22.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:22.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:22.54#ibcon#enter wrdev, iclass 39, count 0 2006.202.00:46:22.54#ibcon#first serial, iclass 39, count 0 2006.202.00:46:22.54#ibcon#enter sib2, iclass 39, count 0 2006.202.00:46:22.54#ibcon#flushed, iclass 39, count 0 2006.202.00:46:22.54#ibcon#about to write, iclass 39, count 0 2006.202.00:46:22.54#ibcon#wrote, iclass 39, count 0 2006.202.00:46:22.54#ibcon#about to read 3, iclass 39, count 0 2006.202.00:46:22.56#ibcon#read 3, iclass 39, count 0 2006.202.00:46:22.56#ibcon#about to read 4, iclass 39, count 0 2006.202.00:46:22.56#ibcon#read 4, iclass 39, count 0 2006.202.00:46:22.56#ibcon#about to read 5, iclass 39, count 0 2006.202.00:46:22.56#ibcon#read 5, iclass 39, count 0 2006.202.00:46:22.56#ibcon#about to read 6, iclass 39, count 0 2006.202.00:46:22.56#ibcon#read 6, iclass 39, count 0 2006.202.00:46:22.56#ibcon#end of sib2, iclass 39, count 0 2006.202.00:46:22.56#ibcon#*mode == 0, iclass 39, count 0 2006.202.00:46:22.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.00:46:22.56#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.00:46:22.56#ibcon#*before write, iclass 39, count 0 2006.202.00:46:22.56#ibcon#enter sib2, iclass 39, count 0 2006.202.00:46:22.56#ibcon#flushed, iclass 39, count 0 2006.202.00:46:22.56#ibcon#about to write, iclass 39, count 0 2006.202.00:46:22.56#ibcon#wrote, iclass 39, count 0 2006.202.00:46:22.56#ibcon#about to read 3, iclass 39, count 0 2006.202.00:46:22.60#ibcon#read 3, iclass 39, count 0 2006.202.00:46:22.60#ibcon#about to read 4, iclass 39, count 0 2006.202.00:46:22.60#ibcon#read 4, iclass 39, count 0 2006.202.00:46:22.60#ibcon#about to read 5, iclass 39, count 0 2006.202.00:46:22.60#ibcon#read 5, iclass 39, count 0 2006.202.00:46:22.60#ibcon#about to read 6, iclass 39, count 0 2006.202.00:46:22.60#ibcon#read 6, iclass 39, count 0 2006.202.00:46:22.60#ibcon#end of sib2, iclass 39, count 0 2006.202.00:46:22.60#ibcon#*after write, iclass 39, count 0 2006.202.00:46:22.60#ibcon#*before return 0, iclass 39, count 0 2006.202.00:46:22.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:22.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.202.00:46:22.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.00:46:22.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.00:46:22.60$vck44/vb=6,4 2006.202.00:46:22.60#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.202.00:46:22.60#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.202.00:46:22.60#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:22.60#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:22.66#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:22.66#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:22.66#ibcon#enter wrdev, iclass 2, count 2 2006.202.00:46:22.66#ibcon#first serial, iclass 2, count 2 2006.202.00:46:22.66#ibcon#enter sib2, iclass 2, count 2 2006.202.00:46:22.66#ibcon#flushed, iclass 2, count 2 2006.202.00:46:22.66#ibcon#about to write, iclass 2, count 2 2006.202.00:46:22.66#ibcon#wrote, iclass 2, count 2 2006.202.00:46:22.66#ibcon#about to read 3, iclass 2, count 2 2006.202.00:46:22.68#ibcon#read 3, iclass 2, count 2 2006.202.00:46:22.68#ibcon#about to read 4, iclass 2, count 2 2006.202.00:46:22.68#ibcon#read 4, iclass 2, count 2 2006.202.00:46:22.68#ibcon#about to read 5, iclass 2, count 2 2006.202.00:46:22.68#ibcon#read 5, iclass 2, count 2 2006.202.00:46:22.68#ibcon#about to read 6, iclass 2, count 2 2006.202.00:46:22.68#ibcon#read 6, iclass 2, count 2 2006.202.00:46:22.68#ibcon#end of sib2, iclass 2, count 2 2006.202.00:46:22.68#ibcon#*mode == 0, iclass 2, count 2 2006.202.00:46:22.68#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.202.00:46:22.68#ibcon#[27=AT06-04\r\n] 2006.202.00:46:22.68#ibcon#*before write, iclass 2, count 2 2006.202.00:46:22.68#ibcon#enter sib2, iclass 2, count 2 2006.202.00:46:22.68#ibcon#flushed, iclass 2, count 2 2006.202.00:46:22.68#ibcon#about to write, iclass 2, count 2 2006.202.00:46:22.68#ibcon#wrote, iclass 2, count 2 2006.202.00:46:22.68#ibcon#about to read 3, iclass 2, count 2 2006.202.00:46:22.71#ibcon#read 3, iclass 2, count 2 2006.202.00:46:22.71#ibcon#about to read 4, iclass 2, count 2 2006.202.00:46:22.71#ibcon#read 4, iclass 2, count 2 2006.202.00:46:22.71#ibcon#about to read 5, iclass 2, count 2 2006.202.00:46:22.71#ibcon#read 5, iclass 2, count 2 2006.202.00:46:22.71#ibcon#about to read 6, iclass 2, count 2 2006.202.00:46:22.71#ibcon#read 6, iclass 2, count 2 2006.202.00:46:22.71#ibcon#end of sib2, iclass 2, count 2 2006.202.00:46:22.71#ibcon#*after write, iclass 2, count 2 2006.202.00:46:22.71#ibcon#*before return 0, iclass 2, count 2 2006.202.00:46:22.71#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:22.71#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.202.00:46:22.71#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.202.00:46:22.71#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:22.71#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:22.83#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:22.83#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:22.83#ibcon#enter wrdev, iclass 2, count 0 2006.202.00:46:22.83#ibcon#first serial, iclass 2, count 0 2006.202.00:46:22.83#ibcon#enter sib2, iclass 2, count 0 2006.202.00:46:22.83#ibcon#flushed, iclass 2, count 0 2006.202.00:46:22.83#ibcon#about to write, iclass 2, count 0 2006.202.00:46:22.83#ibcon#wrote, iclass 2, count 0 2006.202.00:46:22.83#ibcon#about to read 3, iclass 2, count 0 2006.202.00:46:22.85#ibcon#read 3, iclass 2, count 0 2006.202.00:46:22.85#ibcon#about to read 4, iclass 2, count 0 2006.202.00:46:22.85#ibcon#read 4, iclass 2, count 0 2006.202.00:46:22.85#ibcon#about to read 5, iclass 2, count 0 2006.202.00:46:22.85#ibcon#read 5, iclass 2, count 0 2006.202.00:46:22.85#ibcon#about to read 6, iclass 2, count 0 2006.202.00:46:22.85#ibcon#read 6, iclass 2, count 0 2006.202.00:46:22.85#ibcon#end of sib2, iclass 2, count 0 2006.202.00:46:22.85#ibcon#*mode == 0, iclass 2, count 0 2006.202.00:46:22.85#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.00:46:22.85#ibcon#[27=USB\r\n] 2006.202.00:46:22.85#ibcon#*before write, iclass 2, count 0 2006.202.00:46:22.85#ibcon#enter sib2, iclass 2, count 0 2006.202.00:46:22.85#ibcon#flushed, iclass 2, count 0 2006.202.00:46:22.85#ibcon#about to write, iclass 2, count 0 2006.202.00:46:22.85#ibcon#wrote, iclass 2, count 0 2006.202.00:46:22.85#ibcon#about to read 3, iclass 2, count 0 2006.202.00:46:22.88#ibcon#read 3, iclass 2, count 0 2006.202.00:46:22.88#ibcon#about to read 4, iclass 2, count 0 2006.202.00:46:22.88#ibcon#read 4, iclass 2, count 0 2006.202.00:46:22.88#ibcon#about to read 5, iclass 2, count 0 2006.202.00:46:22.88#ibcon#read 5, iclass 2, count 0 2006.202.00:46:22.88#ibcon#about to read 6, iclass 2, count 0 2006.202.00:46:22.88#ibcon#read 6, iclass 2, count 0 2006.202.00:46:22.88#ibcon#end of sib2, iclass 2, count 0 2006.202.00:46:22.88#ibcon#*after write, iclass 2, count 0 2006.202.00:46:22.88#ibcon#*before return 0, iclass 2, count 0 2006.202.00:46:22.88#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:22.88#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.202.00:46:22.88#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.00:46:22.88#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.00:46:22.88$vck44/vblo=7,734.99 2006.202.00:46:22.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.202.00:46:22.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.202.00:46:22.88#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:22.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:22.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:22.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:22.88#ibcon#enter wrdev, iclass 5, count 0 2006.202.00:46:22.88#ibcon#first serial, iclass 5, count 0 2006.202.00:46:22.88#ibcon#enter sib2, iclass 5, count 0 2006.202.00:46:22.88#ibcon#flushed, iclass 5, count 0 2006.202.00:46:22.88#ibcon#about to write, iclass 5, count 0 2006.202.00:46:22.88#ibcon#wrote, iclass 5, count 0 2006.202.00:46:22.88#ibcon#about to read 3, iclass 5, count 0 2006.202.00:46:22.90#ibcon#read 3, iclass 5, count 0 2006.202.00:46:22.90#ibcon#about to read 4, iclass 5, count 0 2006.202.00:46:22.90#ibcon#read 4, iclass 5, count 0 2006.202.00:46:22.90#ibcon#about to read 5, iclass 5, count 0 2006.202.00:46:22.90#ibcon#read 5, iclass 5, count 0 2006.202.00:46:22.90#ibcon#about to read 6, iclass 5, count 0 2006.202.00:46:22.90#ibcon#read 6, iclass 5, count 0 2006.202.00:46:22.90#ibcon#end of sib2, iclass 5, count 0 2006.202.00:46:22.90#ibcon#*mode == 0, iclass 5, count 0 2006.202.00:46:22.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.00:46:22.90#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.00:46:22.90#ibcon#*before write, iclass 5, count 0 2006.202.00:46:22.90#ibcon#enter sib2, iclass 5, count 0 2006.202.00:46:22.90#ibcon#flushed, iclass 5, count 0 2006.202.00:46:22.90#ibcon#about to write, iclass 5, count 0 2006.202.00:46:22.90#ibcon#wrote, iclass 5, count 0 2006.202.00:46:22.90#ibcon#about to read 3, iclass 5, count 0 2006.202.00:46:22.94#ibcon#read 3, iclass 5, count 0 2006.202.00:46:22.94#ibcon#about to read 4, iclass 5, count 0 2006.202.00:46:22.94#ibcon#read 4, iclass 5, count 0 2006.202.00:46:22.94#ibcon#about to read 5, iclass 5, count 0 2006.202.00:46:22.94#ibcon#read 5, iclass 5, count 0 2006.202.00:46:22.94#ibcon#about to read 6, iclass 5, count 0 2006.202.00:46:22.94#ibcon#read 6, iclass 5, count 0 2006.202.00:46:22.94#ibcon#end of sib2, iclass 5, count 0 2006.202.00:46:22.94#ibcon#*after write, iclass 5, count 0 2006.202.00:46:22.94#ibcon#*before return 0, iclass 5, count 0 2006.202.00:46:22.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:22.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.202.00:46:22.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.00:46:22.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.00:46:22.94$vck44/vb=7,4 2006.202.00:46:22.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.202.00:46:22.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.202.00:46:22.94#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:22.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:23.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:23.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:23.00#ibcon#enter wrdev, iclass 7, count 2 2006.202.00:46:23.00#ibcon#first serial, iclass 7, count 2 2006.202.00:46:23.00#ibcon#enter sib2, iclass 7, count 2 2006.202.00:46:23.00#ibcon#flushed, iclass 7, count 2 2006.202.00:46:23.00#ibcon#about to write, iclass 7, count 2 2006.202.00:46:23.00#ibcon#wrote, iclass 7, count 2 2006.202.00:46:23.00#ibcon#about to read 3, iclass 7, count 2 2006.202.00:46:23.02#ibcon#read 3, iclass 7, count 2 2006.202.00:46:23.02#ibcon#about to read 4, iclass 7, count 2 2006.202.00:46:23.02#ibcon#read 4, iclass 7, count 2 2006.202.00:46:23.02#ibcon#about to read 5, iclass 7, count 2 2006.202.00:46:23.02#ibcon#read 5, iclass 7, count 2 2006.202.00:46:23.02#ibcon#about to read 6, iclass 7, count 2 2006.202.00:46:23.02#ibcon#read 6, iclass 7, count 2 2006.202.00:46:23.02#ibcon#end of sib2, iclass 7, count 2 2006.202.00:46:23.02#ibcon#*mode == 0, iclass 7, count 2 2006.202.00:46:23.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.202.00:46:23.02#ibcon#[27=AT07-04\r\n] 2006.202.00:46:23.02#ibcon#*before write, iclass 7, count 2 2006.202.00:46:23.02#ibcon#enter sib2, iclass 7, count 2 2006.202.00:46:23.02#ibcon#flushed, iclass 7, count 2 2006.202.00:46:23.02#ibcon#about to write, iclass 7, count 2 2006.202.00:46:23.02#ibcon#wrote, iclass 7, count 2 2006.202.00:46:23.02#ibcon#about to read 3, iclass 7, count 2 2006.202.00:46:23.05#ibcon#read 3, iclass 7, count 2 2006.202.00:46:23.05#ibcon#about to read 4, iclass 7, count 2 2006.202.00:46:23.05#ibcon#read 4, iclass 7, count 2 2006.202.00:46:23.05#ibcon#about to read 5, iclass 7, count 2 2006.202.00:46:23.05#ibcon#read 5, iclass 7, count 2 2006.202.00:46:23.05#ibcon#about to read 6, iclass 7, count 2 2006.202.00:46:23.05#ibcon#read 6, iclass 7, count 2 2006.202.00:46:23.05#ibcon#end of sib2, iclass 7, count 2 2006.202.00:46:23.05#ibcon#*after write, iclass 7, count 2 2006.202.00:46:23.05#ibcon#*before return 0, iclass 7, count 2 2006.202.00:46:23.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:23.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.202.00:46:23.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.202.00:46:23.05#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:23.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:23.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:23.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:23.17#ibcon#enter wrdev, iclass 7, count 0 2006.202.00:46:23.17#ibcon#first serial, iclass 7, count 0 2006.202.00:46:23.17#ibcon#enter sib2, iclass 7, count 0 2006.202.00:46:23.17#ibcon#flushed, iclass 7, count 0 2006.202.00:46:23.17#ibcon#about to write, iclass 7, count 0 2006.202.00:46:23.17#ibcon#wrote, iclass 7, count 0 2006.202.00:46:23.17#ibcon#about to read 3, iclass 7, count 0 2006.202.00:46:23.19#ibcon#read 3, iclass 7, count 0 2006.202.00:46:23.19#ibcon#about to read 4, iclass 7, count 0 2006.202.00:46:23.19#ibcon#read 4, iclass 7, count 0 2006.202.00:46:23.19#ibcon#about to read 5, iclass 7, count 0 2006.202.00:46:23.19#ibcon#read 5, iclass 7, count 0 2006.202.00:46:23.19#ibcon#about to read 6, iclass 7, count 0 2006.202.00:46:23.19#ibcon#read 6, iclass 7, count 0 2006.202.00:46:23.19#ibcon#end of sib2, iclass 7, count 0 2006.202.00:46:23.19#ibcon#*mode == 0, iclass 7, count 0 2006.202.00:46:23.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.00:46:23.19#ibcon#[27=USB\r\n] 2006.202.00:46:23.19#ibcon#*before write, iclass 7, count 0 2006.202.00:46:23.19#ibcon#enter sib2, iclass 7, count 0 2006.202.00:46:23.19#ibcon#flushed, iclass 7, count 0 2006.202.00:46:23.19#ibcon#about to write, iclass 7, count 0 2006.202.00:46:23.19#ibcon#wrote, iclass 7, count 0 2006.202.00:46:23.19#ibcon#about to read 3, iclass 7, count 0 2006.202.00:46:23.22#ibcon#read 3, iclass 7, count 0 2006.202.00:46:23.22#ibcon#about to read 4, iclass 7, count 0 2006.202.00:46:23.22#ibcon#read 4, iclass 7, count 0 2006.202.00:46:23.22#ibcon#about to read 5, iclass 7, count 0 2006.202.00:46:23.22#ibcon#read 5, iclass 7, count 0 2006.202.00:46:23.22#ibcon#about to read 6, iclass 7, count 0 2006.202.00:46:23.22#ibcon#read 6, iclass 7, count 0 2006.202.00:46:23.22#ibcon#end of sib2, iclass 7, count 0 2006.202.00:46:23.22#ibcon#*after write, iclass 7, count 0 2006.202.00:46:23.22#ibcon#*before return 0, iclass 7, count 0 2006.202.00:46:23.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:23.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.202.00:46:23.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.00:46:23.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.00:46:23.22$vck44/vblo=8,744.99 2006.202.00:46:23.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.202.00:46:23.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.202.00:46:23.22#ibcon#ireg 17 cls_cnt 0 2006.202.00:46:23.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:23.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:23.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:23.22#ibcon#enter wrdev, iclass 11, count 0 2006.202.00:46:23.22#ibcon#first serial, iclass 11, count 0 2006.202.00:46:23.22#ibcon#enter sib2, iclass 11, count 0 2006.202.00:46:23.22#ibcon#flushed, iclass 11, count 0 2006.202.00:46:23.22#ibcon#about to write, iclass 11, count 0 2006.202.00:46:23.22#ibcon#wrote, iclass 11, count 0 2006.202.00:46:23.22#ibcon#about to read 3, iclass 11, count 0 2006.202.00:46:23.24#ibcon#read 3, iclass 11, count 0 2006.202.00:46:23.24#ibcon#about to read 4, iclass 11, count 0 2006.202.00:46:23.24#ibcon#read 4, iclass 11, count 0 2006.202.00:46:23.24#ibcon#about to read 5, iclass 11, count 0 2006.202.00:46:23.24#ibcon#read 5, iclass 11, count 0 2006.202.00:46:23.24#ibcon#about to read 6, iclass 11, count 0 2006.202.00:46:23.24#ibcon#read 6, iclass 11, count 0 2006.202.00:46:23.24#ibcon#end of sib2, iclass 11, count 0 2006.202.00:46:23.24#ibcon#*mode == 0, iclass 11, count 0 2006.202.00:46:23.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.00:46:23.24#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.00:46:23.24#ibcon#*before write, iclass 11, count 0 2006.202.00:46:23.24#ibcon#enter sib2, iclass 11, count 0 2006.202.00:46:23.24#ibcon#flushed, iclass 11, count 0 2006.202.00:46:23.24#ibcon#about to write, iclass 11, count 0 2006.202.00:46:23.24#ibcon#wrote, iclass 11, count 0 2006.202.00:46:23.24#ibcon#about to read 3, iclass 11, count 0 2006.202.00:46:23.28#ibcon#read 3, iclass 11, count 0 2006.202.00:46:23.28#ibcon#about to read 4, iclass 11, count 0 2006.202.00:46:23.28#ibcon#read 4, iclass 11, count 0 2006.202.00:46:23.28#ibcon#about to read 5, iclass 11, count 0 2006.202.00:46:23.28#ibcon#read 5, iclass 11, count 0 2006.202.00:46:23.28#ibcon#about to read 6, iclass 11, count 0 2006.202.00:46:23.28#ibcon#read 6, iclass 11, count 0 2006.202.00:46:23.28#ibcon#end of sib2, iclass 11, count 0 2006.202.00:46:23.28#ibcon#*after write, iclass 11, count 0 2006.202.00:46:23.28#ibcon#*before return 0, iclass 11, count 0 2006.202.00:46:23.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:23.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.202.00:46:23.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.00:46:23.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.00:46:23.28$vck44/vb=8,4 2006.202.00:46:23.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.202.00:46:23.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.202.00:46:23.28#ibcon#ireg 11 cls_cnt 2 2006.202.00:46:23.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:23.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:23.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:23.34#ibcon#enter wrdev, iclass 13, count 2 2006.202.00:46:23.34#ibcon#first serial, iclass 13, count 2 2006.202.00:46:23.34#ibcon#enter sib2, iclass 13, count 2 2006.202.00:46:23.34#ibcon#flushed, iclass 13, count 2 2006.202.00:46:23.34#ibcon#about to write, iclass 13, count 2 2006.202.00:46:23.34#ibcon#wrote, iclass 13, count 2 2006.202.00:46:23.34#ibcon#about to read 3, iclass 13, count 2 2006.202.00:46:23.36#ibcon#read 3, iclass 13, count 2 2006.202.00:46:23.36#ibcon#about to read 4, iclass 13, count 2 2006.202.00:46:23.36#ibcon#read 4, iclass 13, count 2 2006.202.00:46:23.36#ibcon#about to read 5, iclass 13, count 2 2006.202.00:46:23.36#ibcon#read 5, iclass 13, count 2 2006.202.00:46:23.36#ibcon#about to read 6, iclass 13, count 2 2006.202.00:46:23.36#ibcon#read 6, iclass 13, count 2 2006.202.00:46:23.36#ibcon#end of sib2, iclass 13, count 2 2006.202.00:46:23.36#ibcon#*mode == 0, iclass 13, count 2 2006.202.00:46:23.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.202.00:46:23.36#ibcon#[27=AT08-04\r\n] 2006.202.00:46:23.36#ibcon#*before write, iclass 13, count 2 2006.202.00:46:23.36#ibcon#enter sib2, iclass 13, count 2 2006.202.00:46:23.36#ibcon#flushed, iclass 13, count 2 2006.202.00:46:23.36#ibcon#about to write, iclass 13, count 2 2006.202.00:46:23.36#ibcon#wrote, iclass 13, count 2 2006.202.00:46:23.36#ibcon#about to read 3, iclass 13, count 2 2006.202.00:46:23.39#ibcon#read 3, iclass 13, count 2 2006.202.00:46:23.39#ibcon#about to read 4, iclass 13, count 2 2006.202.00:46:23.39#ibcon#read 4, iclass 13, count 2 2006.202.00:46:23.39#ibcon#about to read 5, iclass 13, count 2 2006.202.00:46:23.39#ibcon#read 5, iclass 13, count 2 2006.202.00:46:23.39#ibcon#about to read 6, iclass 13, count 2 2006.202.00:46:23.39#ibcon#read 6, iclass 13, count 2 2006.202.00:46:23.39#ibcon#end of sib2, iclass 13, count 2 2006.202.00:46:23.39#ibcon#*after write, iclass 13, count 2 2006.202.00:46:23.39#ibcon#*before return 0, iclass 13, count 2 2006.202.00:46:23.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:23.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.202.00:46:23.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.202.00:46:23.39#ibcon#ireg 7 cls_cnt 0 2006.202.00:46:23.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:23.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:23.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:23.51#ibcon#enter wrdev, iclass 13, count 0 2006.202.00:46:23.51#ibcon#first serial, iclass 13, count 0 2006.202.00:46:23.51#ibcon#enter sib2, iclass 13, count 0 2006.202.00:46:23.51#ibcon#flushed, iclass 13, count 0 2006.202.00:46:23.51#ibcon#about to write, iclass 13, count 0 2006.202.00:46:23.51#ibcon#wrote, iclass 13, count 0 2006.202.00:46:23.51#ibcon#about to read 3, iclass 13, count 0 2006.202.00:46:23.53#ibcon#read 3, iclass 13, count 0 2006.202.00:46:23.53#ibcon#about to read 4, iclass 13, count 0 2006.202.00:46:23.53#ibcon#read 4, iclass 13, count 0 2006.202.00:46:23.53#ibcon#about to read 5, iclass 13, count 0 2006.202.00:46:23.53#ibcon#read 5, iclass 13, count 0 2006.202.00:46:23.53#ibcon#about to read 6, iclass 13, count 0 2006.202.00:46:23.53#ibcon#read 6, iclass 13, count 0 2006.202.00:46:23.53#ibcon#end of sib2, iclass 13, count 0 2006.202.00:46:23.53#ibcon#*mode == 0, iclass 13, count 0 2006.202.00:46:23.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.00:46:23.53#ibcon#[27=USB\r\n] 2006.202.00:46:23.53#ibcon#*before write, iclass 13, count 0 2006.202.00:46:23.53#ibcon#enter sib2, iclass 13, count 0 2006.202.00:46:23.53#ibcon#flushed, iclass 13, count 0 2006.202.00:46:23.53#ibcon#about to write, iclass 13, count 0 2006.202.00:46:23.53#ibcon#wrote, iclass 13, count 0 2006.202.00:46:23.53#ibcon#about to read 3, iclass 13, count 0 2006.202.00:46:23.56#ibcon#read 3, iclass 13, count 0 2006.202.00:46:23.56#ibcon#about to read 4, iclass 13, count 0 2006.202.00:46:23.56#ibcon#read 4, iclass 13, count 0 2006.202.00:46:23.56#ibcon#about to read 5, iclass 13, count 0 2006.202.00:46:23.56#ibcon#read 5, iclass 13, count 0 2006.202.00:46:23.56#ibcon#about to read 6, iclass 13, count 0 2006.202.00:46:23.56#ibcon#read 6, iclass 13, count 0 2006.202.00:46:23.56#ibcon#end of sib2, iclass 13, count 0 2006.202.00:46:23.56#ibcon#*after write, iclass 13, count 0 2006.202.00:46:23.56#ibcon#*before return 0, iclass 13, count 0 2006.202.00:46:23.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:23.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.202.00:46:23.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.00:46:23.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.00:46:23.56$vck44/vabw=wide 2006.202.00:46:23.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.00:46:23.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.00:46:23.56#ibcon#ireg 8 cls_cnt 0 2006.202.00:46:23.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:23.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:23.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:23.56#ibcon#enter wrdev, iclass 15, count 0 2006.202.00:46:23.56#ibcon#first serial, iclass 15, count 0 2006.202.00:46:23.56#ibcon#enter sib2, iclass 15, count 0 2006.202.00:46:23.56#ibcon#flushed, iclass 15, count 0 2006.202.00:46:23.56#ibcon#about to write, iclass 15, count 0 2006.202.00:46:23.56#ibcon#wrote, iclass 15, count 0 2006.202.00:46:23.56#ibcon#about to read 3, iclass 15, count 0 2006.202.00:46:23.58#ibcon#read 3, iclass 15, count 0 2006.202.00:46:23.58#ibcon#about to read 4, iclass 15, count 0 2006.202.00:46:23.58#ibcon#read 4, iclass 15, count 0 2006.202.00:46:23.58#ibcon#about to read 5, iclass 15, count 0 2006.202.00:46:23.58#ibcon#read 5, iclass 15, count 0 2006.202.00:46:23.58#ibcon#about to read 6, iclass 15, count 0 2006.202.00:46:23.58#ibcon#read 6, iclass 15, count 0 2006.202.00:46:23.58#ibcon#end of sib2, iclass 15, count 0 2006.202.00:46:23.58#ibcon#*mode == 0, iclass 15, count 0 2006.202.00:46:23.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.00:46:23.58#ibcon#[25=BW32\r\n] 2006.202.00:46:23.58#ibcon#*before write, iclass 15, count 0 2006.202.00:46:23.58#ibcon#enter sib2, iclass 15, count 0 2006.202.00:46:23.58#ibcon#flushed, iclass 15, count 0 2006.202.00:46:23.58#ibcon#about to write, iclass 15, count 0 2006.202.00:46:23.58#ibcon#wrote, iclass 15, count 0 2006.202.00:46:23.58#ibcon#about to read 3, iclass 15, count 0 2006.202.00:46:23.61#ibcon#read 3, iclass 15, count 0 2006.202.00:46:23.61#ibcon#about to read 4, iclass 15, count 0 2006.202.00:46:23.61#ibcon#read 4, iclass 15, count 0 2006.202.00:46:23.61#ibcon#about to read 5, iclass 15, count 0 2006.202.00:46:23.61#ibcon#read 5, iclass 15, count 0 2006.202.00:46:23.61#ibcon#about to read 6, iclass 15, count 0 2006.202.00:46:23.61#ibcon#read 6, iclass 15, count 0 2006.202.00:46:23.61#ibcon#end of sib2, iclass 15, count 0 2006.202.00:46:23.61#ibcon#*after write, iclass 15, count 0 2006.202.00:46:23.61#ibcon#*before return 0, iclass 15, count 0 2006.202.00:46:23.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:23.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.00:46:23.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.00:46:23.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.00:46:23.61$vck44/vbbw=wide 2006.202.00:46:23.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.00:46:23.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.00:46:23.61#ibcon#ireg 8 cls_cnt 0 2006.202.00:46:23.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:46:23.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:46:23.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:46:23.68#ibcon#enter wrdev, iclass 17, count 0 2006.202.00:46:23.68#ibcon#first serial, iclass 17, count 0 2006.202.00:46:23.68#ibcon#enter sib2, iclass 17, count 0 2006.202.00:46:23.68#ibcon#flushed, iclass 17, count 0 2006.202.00:46:23.68#ibcon#about to write, iclass 17, count 0 2006.202.00:46:23.68#ibcon#wrote, iclass 17, count 0 2006.202.00:46:23.68#ibcon#about to read 3, iclass 17, count 0 2006.202.00:46:23.70#ibcon#read 3, iclass 17, count 0 2006.202.00:46:23.70#ibcon#about to read 4, iclass 17, count 0 2006.202.00:46:23.70#ibcon#read 4, iclass 17, count 0 2006.202.00:46:23.70#ibcon#about to read 5, iclass 17, count 0 2006.202.00:46:23.70#ibcon#read 5, iclass 17, count 0 2006.202.00:46:23.70#ibcon#about to read 6, iclass 17, count 0 2006.202.00:46:23.70#ibcon#read 6, iclass 17, count 0 2006.202.00:46:23.70#ibcon#end of sib2, iclass 17, count 0 2006.202.00:46:23.70#ibcon#*mode == 0, iclass 17, count 0 2006.202.00:46:23.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.00:46:23.70#ibcon#[27=BW32\r\n] 2006.202.00:46:23.70#ibcon#*before write, iclass 17, count 0 2006.202.00:46:23.70#ibcon#enter sib2, iclass 17, count 0 2006.202.00:46:23.70#ibcon#flushed, iclass 17, count 0 2006.202.00:46:23.70#ibcon#about to write, iclass 17, count 0 2006.202.00:46:23.70#ibcon#wrote, iclass 17, count 0 2006.202.00:46:23.70#ibcon#about to read 3, iclass 17, count 0 2006.202.00:46:23.73#ibcon#read 3, iclass 17, count 0 2006.202.00:46:23.73#ibcon#about to read 4, iclass 17, count 0 2006.202.00:46:23.73#ibcon#read 4, iclass 17, count 0 2006.202.00:46:23.74#ibcon#about to read 5, iclass 17, count 0 2006.202.00:46:23.74#ibcon#read 5, iclass 17, count 0 2006.202.00:46:23.74#ibcon#about to read 6, iclass 17, count 0 2006.202.00:46:23.74#ibcon#read 6, iclass 17, count 0 2006.202.00:46:23.74#ibcon#end of sib2, iclass 17, count 0 2006.202.00:46:23.74#ibcon#*after write, iclass 17, count 0 2006.202.00:46:23.74#ibcon#*before return 0, iclass 17, count 0 2006.202.00:46:23.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:46:23.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.00:46:23.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.00:46:23.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.00:46:23.74$setupk4/ifdk4 2006.202.00:46:23.74$ifdk4/lo= 2006.202.00:46:23.74$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.00:46:23.74$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.00:46:23.74$ifdk4/patch= 2006.202.00:46:23.74$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.00:46:23.74$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.00:46:23.74$setupk4/!*+20s 2006.202.00:46:26.16#abcon#<5=/03 2.2 4.3 20.351001001.5\r\n> 2006.202.00:46:26.18#abcon#{5=INTERFACE CLEAR} 2006.202.00:46:26.24#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:46:36.33#abcon#<5=/03 2.1 4.3 20.351001001.5\r\n> 2006.202.00:46:36.35#abcon#{5=INTERFACE CLEAR} 2006.202.00:46:36.41#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:46:38.24$setupk4/"tpicd 2006.202.00:46:38.24$setupk4/echo=off 2006.202.00:46:38.24$setupk4/xlog=off 2006.202.00:46:38.24:!2006.202.00:48:24 2006.202.00:46:39.14#trakl#Source acquired 2006.202.00:46:40.14#flagr#flagr/antenna,acquired 2006.202.00:48:24.00:preob 2006.202.00:48:24.13/onsource/TRACKING 2006.202.00:48:24.13:!2006.202.00:48:34 2006.202.00:48:34.00:"tape 2006.202.00:48:34.00:"st=record 2006.202.00:48:34.00:data_valid=on 2006.202.00:48:34.00:midob 2006.202.00:48:34.13/onsource/TRACKING 2006.202.00:48:34.13/wx/20.33,1001.4,100 2006.202.00:48:34.21/cable/+6.4843E-03 2006.202.00:48:35.30/va/01,08,usb,yes,42,45 2006.202.00:48:35.30/va/02,07,usb,yes,45,46 2006.202.00:48:35.30/va/03,08,usb,yes,41,43 2006.202.00:48:35.30/va/04,07,usb,yes,47,49 2006.202.00:48:35.30/va/05,04,usb,yes,41,42 2006.202.00:48:35.30/va/06,05,usb,yes,42,42 2006.202.00:48:35.30/va/07,05,usb,yes,41,42 2006.202.00:48:35.30/va/08,04,usb,yes,40,48 2006.202.00:48:35.53/valo/01,524.99,yes,locked 2006.202.00:48:35.53/valo/02,534.99,yes,locked 2006.202.00:48:35.53/valo/03,564.99,yes,locked 2006.202.00:48:35.53/valo/04,624.99,yes,locked 2006.202.00:48:35.53/valo/05,734.99,yes,locked 2006.202.00:48:35.53/valo/06,814.99,yes,locked 2006.202.00:48:35.53/valo/07,864.99,yes,locked 2006.202.00:48:35.53/valo/08,884.99,yes,locked 2006.202.00:48:36.62/vb/01,04,usb,yes,30,28 2006.202.00:48:36.62/vb/02,05,usb,yes,28,28 2006.202.00:48:36.62/vb/03,04,usb,yes,29,32 2006.202.00:48:36.62/vb/04,05,usb,yes,30,28 2006.202.00:48:36.62/vb/05,04,usb,yes,26,29 2006.202.00:48:36.62/vb/06,04,usb,yes,31,27 2006.202.00:48:36.62/vb/07,04,usb,yes,30,30 2006.202.00:48:36.62/vb/08,04,usb,yes,28,31 2006.202.00:48:36.85/vblo/01,629.99,yes,locked 2006.202.00:48:36.85/vblo/02,634.99,yes,locked 2006.202.00:48:36.85/vblo/03,649.99,yes,locked 2006.202.00:48:36.85/vblo/04,679.99,yes,locked 2006.202.00:48:36.85/vblo/05,709.99,yes,locked 2006.202.00:48:36.85/vblo/06,719.99,yes,locked 2006.202.00:48:36.85/vblo/07,734.99,yes,locked 2006.202.00:48:36.85/vblo/08,744.99,yes,locked 2006.202.00:48:37.00/vabw/8 2006.202.00:48:37.15/vbbw/8 2006.202.00:48:37.24/xfe/off,on,15.0 2006.202.00:48:37.62/ifatt/23,28,28,28 2006.202.00:48:38.07/fmout-gps/S +4.50E-07 2006.202.00:48:38.10:!2006.202.00:58:34 2006.202.00:58:34.00:data_valid=off 2006.202.00:58:34.00:"et 2006.202.00:58:34.00:!+3s 2006.202.00:58:37.01:"tape 2006.202.00:58:37.01:postob 2006.202.00:58:37.21/cable/+6.4830E-03 2006.202.00:58:37.21/wx/20.34,1001.3,100 2006.202.00:58:38.07/fmout-gps/S +4.48E-07 2006.202.00:58:38.07:scan_name=202-0102,jd0607,250 2006.202.00:58:38.07:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.202.00:58:38.13#flagr#flagr/antenna,new-source 2006.202.00:58:39.14:checkk5 2006.202.00:58:39.55/chk_autoobs//k5ts1/ autoobs is running! 2006.202.00:58:39.98/chk_autoobs//k5ts2/ autoobs is running! 2006.202.00:58:40.39/chk_autoobs//k5ts3/ autoobs is running! 2006.202.00:58:40.78/chk_autoobs//k5ts4/ autoobs is running! 2006.202.00:58:41.48/chk_obsdata//k5ts1/T2020048??a.dat file size is correct (nominal:2400MB, actual:2400MB). 2006.202.00:58:42.20/chk_obsdata//k5ts2/T2020048??b.dat file size is correct (nominal:2400MB, actual:2400MB). 2006.202.00:58:42.91/chk_obsdata//k5ts3/T2020048??c.dat file size is correct (nominal:2400MB, actual:2400MB). 2006.202.00:58:43.63/chk_obsdata//k5ts4/T2020048??d.dat file size is correct (nominal:2400MB, actual:2400MB). 2006.202.00:58:44.34/k5log//k5ts1_log_newline 2006.202.00:58:45.06/k5log//k5ts2_log_newline 2006.202.00:58:45.78/k5log//k5ts3_log_newline 2006.202.00:58:46.50/k5log//k5ts4_log_newline 2006.202.00:58:46.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.00:58:46.52:setupk4=1 2006.202.00:58:46.52$setupk4/echo=on 2006.202.00:58:46.52$setupk4/pcalon 2006.202.00:58:46.52$pcalon/"no phase cal control is implemented here 2006.202.00:58:46.52$setupk4/"tpicd=stop 2006.202.00:58:46.52$setupk4/"rec=synch_on 2006.202.00:58:46.52$setupk4/"rec_mode=128 2006.202.00:58:46.52$setupk4/!* 2006.202.00:58:46.52$setupk4/recpk4 2006.202.00:58:46.52$recpk4/recpatch= 2006.202.00:58:46.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.00:58:46.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.00:58:46.53$setupk4/vck44 2006.202.00:58:46.53$vck44/valo=1,524.99 2006.202.00:58:46.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.00:58:46.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.00:58:46.53#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:46.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:46.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:46.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:46.53#ibcon#enter wrdev, iclass 26, count 0 2006.202.00:58:46.53#ibcon#first serial, iclass 26, count 0 2006.202.00:58:46.53#ibcon#enter sib2, iclass 26, count 0 2006.202.00:58:46.53#ibcon#flushed, iclass 26, count 0 2006.202.00:58:46.53#ibcon#about to write, iclass 26, count 0 2006.202.00:58:46.53#ibcon#wrote, iclass 26, count 0 2006.202.00:58:46.53#ibcon#about to read 3, iclass 26, count 0 2006.202.00:58:46.55#ibcon#read 3, iclass 26, count 0 2006.202.00:58:46.55#ibcon#about to read 4, iclass 26, count 0 2006.202.00:58:46.55#ibcon#read 4, iclass 26, count 0 2006.202.00:58:46.55#ibcon#about to read 5, iclass 26, count 0 2006.202.00:58:46.55#ibcon#read 5, iclass 26, count 0 2006.202.00:58:46.55#ibcon#about to read 6, iclass 26, count 0 2006.202.00:58:46.55#ibcon#read 6, iclass 26, count 0 2006.202.00:58:46.55#ibcon#end of sib2, iclass 26, count 0 2006.202.00:58:46.55#ibcon#*mode == 0, iclass 26, count 0 2006.202.00:58:46.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.00:58:46.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.00:58:46.55#ibcon#*before write, iclass 26, count 0 2006.202.00:58:46.55#ibcon#enter sib2, iclass 26, count 0 2006.202.00:58:46.55#ibcon#flushed, iclass 26, count 0 2006.202.00:58:46.55#ibcon#about to write, iclass 26, count 0 2006.202.00:58:46.55#ibcon#wrote, iclass 26, count 0 2006.202.00:58:46.55#ibcon#about to read 3, iclass 26, count 0 2006.202.00:58:46.60#ibcon#read 3, iclass 26, count 0 2006.202.00:58:46.60#ibcon#about to read 4, iclass 26, count 0 2006.202.00:58:46.60#ibcon#read 4, iclass 26, count 0 2006.202.00:58:46.60#ibcon#about to read 5, iclass 26, count 0 2006.202.00:58:46.60#ibcon#read 5, iclass 26, count 0 2006.202.00:58:46.60#ibcon#about to read 6, iclass 26, count 0 2006.202.00:58:46.60#ibcon#read 6, iclass 26, count 0 2006.202.00:58:46.60#ibcon#end of sib2, iclass 26, count 0 2006.202.00:58:46.60#ibcon#*after write, iclass 26, count 0 2006.202.00:58:46.60#ibcon#*before return 0, iclass 26, count 0 2006.202.00:58:46.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:46.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:46.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.00:58:46.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.00:58:46.60$vck44/va=1,8 2006.202.00:58:46.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.00:58:46.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.00:58:46.60#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:46.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:46.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:46.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:46.60#ibcon#enter wrdev, iclass 28, count 2 2006.202.00:58:46.60#ibcon#first serial, iclass 28, count 2 2006.202.00:58:46.60#ibcon#enter sib2, iclass 28, count 2 2006.202.00:58:46.60#ibcon#flushed, iclass 28, count 2 2006.202.00:58:46.60#ibcon#about to write, iclass 28, count 2 2006.202.00:58:46.60#ibcon#wrote, iclass 28, count 2 2006.202.00:58:46.60#ibcon#about to read 3, iclass 28, count 2 2006.202.00:58:46.62#ibcon#read 3, iclass 28, count 2 2006.202.00:58:46.62#ibcon#about to read 4, iclass 28, count 2 2006.202.00:58:46.62#ibcon#read 4, iclass 28, count 2 2006.202.00:58:46.62#ibcon#about to read 5, iclass 28, count 2 2006.202.00:58:46.62#ibcon#read 5, iclass 28, count 2 2006.202.00:58:46.62#ibcon#about to read 6, iclass 28, count 2 2006.202.00:58:46.62#ibcon#read 6, iclass 28, count 2 2006.202.00:58:46.62#ibcon#end of sib2, iclass 28, count 2 2006.202.00:58:46.62#ibcon#*mode == 0, iclass 28, count 2 2006.202.00:58:46.62#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.00:58:46.62#ibcon#[25=AT01-08\r\n] 2006.202.00:58:46.62#ibcon#*before write, iclass 28, count 2 2006.202.00:58:46.62#ibcon#enter sib2, iclass 28, count 2 2006.202.00:58:46.62#ibcon#flushed, iclass 28, count 2 2006.202.00:58:46.62#ibcon#about to write, iclass 28, count 2 2006.202.00:58:46.62#ibcon#wrote, iclass 28, count 2 2006.202.00:58:46.62#ibcon#about to read 3, iclass 28, count 2 2006.202.00:58:46.65#ibcon#read 3, iclass 28, count 2 2006.202.00:58:46.65#ibcon#about to read 4, iclass 28, count 2 2006.202.00:58:46.65#ibcon#read 4, iclass 28, count 2 2006.202.00:58:46.65#ibcon#about to read 5, iclass 28, count 2 2006.202.00:58:46.65#ibcon#read 5, iclass 28, count 2 2006.202.00:58:46.65#ibcon#about to read 6, iclass 28, count 2 2006.202.00:58:46.65#ibcon#read 6, iclass 28, count 2 2006.202.00:58:46.65#ibcon#end of sib2, iclass 28, count 2 2006.202.00:58:46.65#ibcon#*after write, iclass 28, count 2 2006.202.00:58:46.65#ibcon#*before return 0, iclass 28, count 2 2006.202.00:58:46.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:46.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:46.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.00:58:46.65#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:46.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:46.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:46.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:46.77#ibcon#enter wrdev, iclass 28, count 0 2006.202.00:58:46.77#ibcon#first serial, iclass 28, count 0 2006.202.00:58:46.77#ibcon#enter sib2, iclass 28, count 0 2006.202.00:58:46.77#ibcon#flushed, iclass 28, count 0 2006.202.00:58:46.77#ibcon#about to write, iclass 28, count 0 2006.202.00:58:46.77#ibcon#wrote, iclass 28, count 0 2006.202.00:58:46.77#ibcon#about to read 3, iclass 28, count 0 2006.202.00:58:46.79#ibcon#read 3, iclass 28, count 0 2006.202.00:58:46.79#ibcon#about to read 4, iclass 28, count 0 2006.202.00:58:46.79#ibcon#read 4, iclass 28, count 0 2006.202.00:58:46.79#ibcon#about to read 5, iclass 28, count 0 2006.202.00:58:46.79#ibcon#read 5, iclass 28, count 0 2006.202.00:58:46.79#ibcon#about to read 6, iclass 28, count 0 2006.202.00:58:46.79#ibcon#read 6, iclass 28, count 0 2006.202.00:58:46.79#ibcon#end of sib2, iclass 28, count 0 2006.202.00:58:46.79#ibcon#*mode == 0, iclass 28, count 0 2006.202.00:58:46.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.00:58:46.79#ibcon#[25=USB\r\n] 2006.202.00:58:46.79#ibcon#*before write, iclass 28, count 0 2006.202.00:58:46.79#ibcon#enter sib2, iclass 28, count 0 2006.202.00:58:46.79#ibcon#flushed, iclass 28, count 0 2006.202.00:58:46.79#ibcon#about to write, iclass 28, count 0 2006.202.00:58:46.79#ibcon#wrote, iclass 28, count 0 2006.202.00:58:46.79#ibcon#about to read 3, iclass 28, count 0 2006.202.00:58:46.82#ibcon#read 3, iclass 28, count 0 2006.202.00:58:46.82#ibcon#about to read 4, iclass 28, count 0 2006.202.00:58:46.82#ibcon#read 4, iclass 28, count 0 2006.202.00:58:46.82#ibcon#about to read 5, iclass 28, count 0 2006.202.00:58:46.82#ibcon#read 5, iclass 28, count 0 2006.202.00:58:46.82#ibcon#about to read 6, iclass 28, count 0 2006.202.00:58:46.82#ibcon#read 6, iclass 28, count 0 2006.202.00:58:46.82#ibcon#end of sib2, iclass 28, count 0 2006.202.00:58:46.82#ibcon#*after write, iclass 28, count 0 2006.202.00:58:46.82#ibcon#*before return 0, iclass 28, count 0 2006.202.00:58:46.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:46.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:46.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.00:58:46.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.00:58:46.82$vck44/valo=2,534.99 2006.202.00:58:46.82#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.00:58:46.82#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.00:58:46.82#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:46.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:46.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:46.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:46.82#ibcon#enter wrdev, iclass 30, count 0 2006.202.00:58:46.82#ibcon#first serial, iclass 30, count 0 2006.202.00:58:46.82#ibcon#enter sib2, iclass 30, count 0 2006.202.00:58:46.82#ibcon#flushed, iclass 30, count 0 2006.202.00:58:46.82#ibcon#about to write, iclass 30, count 0 2006.202.00:58:46.82#ibcon#wrote, iclass 30, count 0 2006.202.00:58:46.82#ibcon#about to read 3, iclass 30, count 0 2006.202.00:58:46.84#ibcon#read 3, iclass 30, count 0 2006.202.00:58:46.84#ibcon#about to read 4, iclass 30, count 0 2006.202.00:58:46.84#ibcon#read 4, iclass 30, count 0 2006.202.00:58:46.84#ibcon#about to read 5, iclass 30, count 0 2006.202.00:58:46.84#ibcon#read 5, iclass 30, count 0 2006.202.00:58:46.84#ibcon#about to read 6, iclass 30, count 0 2006.202.00:58:46.84#ibcon#read 6, iclass 30, count 0 2006.202.00:58:46.84#ibcon#end of sib2, iclass 30, count 0 2006.202.00:58:46.84#ibcon#*mode == 0, iclass 30, count 0 2006.202.00:58:46.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.00:58:46.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.00:58:46.84#ibcon#*before write, iclass 30, count 0 2006.202.00:58:46.84#ibcon#enter sib2, iclass 30, count 0 2006.202.00:58:46.84#ibcon#flushed, iclass 30, count 0 2006.202.00:58:46.84#ibcon#about to write, iclass 30, count 0 2006.202.00:58:46.84#ibcon#wrote, iclass 30, count 0 2006.202.00:58:46.84#ibcon#about to read 3, iclass 30, count 0 2006.202.00:58:46.88#ibcon#read 3, iclass 30, count 0 2006.202.00:58:46.88#ibcon#about to read 4, iclass 30, count 0 2006.202.00:58:46.88#ibcon#read 4, iclass 30, count 0 2006.202.00:58:46.88#ibcon#about to read 5, iclass 30, count 0 2006.202.00:58:46.88#ibcon#read 5, iclass 30, count 0 2006.202.00:58:46.88#ibcon#about to read 6, iclass 30, count 0 2006.202.00:58:46.88#ibcon#read 6, iclass 30, count 0 2006.202.00:58:46.88#ibcon#end of sib2, iclass 30, count 0 2006.202.00:58:46.88#ibcon#*after write, iclass 30, count 0 2006.202.00:58:46.88#ibcon#*before return 0, iclass 30, count 0 2006.202.00:58:46.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:46.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:46.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.00:58:46.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.00:58:46.88$vck44/va=2,7 2006.202.00:58:46.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.00:58:46.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.00:58:46.88#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:46.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:46.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:46.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:46.94#ibcon#enter wrdev, iclass 32, count 2 2006.202.00:58:46.94#ibcon#first serial, iclass 32, count 2 2006.202.00:58:46.94#ibcon#enter sib2, iclass 32, count 2 2006.202.00:58:46.94#ibcon#flushed, iclass 32, count 2 2006.202.00:58:46.94#ibcon#about to write, iclass 32, count 2 2006.202.00:58:46.94#ibcon#wrote, iclass 32, count 2 2006.202.00:58:46.94#ibcon#about to read 3, iclass 32, count 2 2006.202.00:58:46.96#ibcon#read 3, iclass 32, count 2 2006.202.00:58:46.96#ibcon#about to read 4, iclass 32, count 2 2006.202.00:58:46.96#ibcon#read 4, iclass 32, count 2 2006.202.00:58:46.96#ibcon#about to read 5, iclass 32, count 2 2006.202.00:58:46.96#ibcon#read 5, iclass 32, count 2 2006.202.00:58:46.96#ibcon#about to read 6, iclass 32, count 2 2006.202.00:58:46.96#ibcon#read 6, iclass 32, count 2 2006.202.00:58:46.96#ibcon#end of sib2, iclass 32, count 2 2006.202.00:58:46.96#ibcon#*mode == 0, iclass 32, count 2 2006.202.00:58:46.96#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.00:58:46.96#ibcon#[25=AT02-07\r\n] 2006.202.00:58:46.96#ibcon#*before write, iclass 32, count 2 2006.202.00:58:46.96#ibcon#enter sib2, iclass 32, count 2 2006.202.00:58:46.96#ibcon#flushed, iclass 32, count 2 2006.202.00:58:46.96#ibcon#about to write, iclass 32, count 2 2006.202.00:58:46.96#ibcon#wrote, iclass 32, count 2 2006.202.00:58:46.96#ibcon#about to read 3, iclass 32, count 2 2006.202.00:58:46.99#ibcon#read 3, iclass 32, count 2 2006.202.00:58:46.99#ibcon#about to read 4, iclass 32, count 2 2006.202.00:58:46.99#ibcon#read 4, iclass 32, count 2 2006.202.00:58:46.99#ibcon#about to read 5, iclass 32, count 2 2006.202.00:58:46.99#ibcon#read 5, iclass 32, count 2 2006.202.00:58:46.99#ibcon#about to read 6, iclass 32, count 2 2006.202.00:58:46.99#ibcon#read 6, iclass 32, count 2 2006.202.00:58:46.99#ibcon#end of sib2, iclass 32, count 2 2006.202.00:58:46.99#ibcon#*after write, iclass 32, count 2 2006.202.00:58:46.99#ibcon#*before return 0, iclass 32, count 2 2006.202.00:58:46.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:46.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:46.99#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.00:58:46.99#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:46.99#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:47.11#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:47.11#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:47.11#ibcon#enter wrdev, iclass 32, count 0 2006.202.00:58:47.11#ibcon#first serial, iclass 32, count 0 2006.202.00:58:47.11#ibcon#enter sib2, iclass 32, count 0 2006.202.00:58:47.11#ibcon#flushed, iclass 32, count 0 2006.202.00:58:47.11#ibcon#about to write, iclass 32, count 0 2006.202.00:58:47.11#ibcon#wrote, iclass 32, count 0 2006.202.00:58:47.11#ibcon#about to read 3, iclass 32, count 0 2006.202.00:58:47.13#ibcon#read 3, iclass 32, count 0 2006.202.00:58:47.13#ibcon#about to read 4, iclass 32, count 0 2006.202.00:58:47.13#ibcon#read 4, iclass 32, count 0 2006.202.00:58:47.13#ibcon#about to read 5, iclass 32, count 0 2006.202.00:58:47.13#ibcon#read 5, iclass 32, count 0 2006.202.00:58:47.13#ibcon#about to read 6, iclass 32, count 0 2006.202.00:58:47.13#ibcon#read 6, iclass 32, count 0 2006.202.00:58:47.13#ibcon#end of sib2, iclass 32, count 0 2006.202.00:58:47.13#ibcon#*mode == 0, iclass 32, count 0 2006.202.00:58:47.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.00:58:47.13#ibcon#[25=USB\r\n] 2006.202.00:58:47.13#ibcon#*before write, iclass 32, count 0 2006.202.00:58:47.13#ibcon#enter sib2, iclass 32, count 0 2006.202.00:58:47.13#ibcon#flushed, iclass 32, count 0 2006.202.00:58:47.13#ibcon#about to write, iclass 32, count 0 2006.202.00:58:47.13#ibcon#wrote, iclass 32, count 0 2006.202.00:58:47.13#ibcon#about to read 3, iclass 32, count 0 2006.202.00:58:47.16#ibcon#read 3, iclass 32, count 0 2006.202.00:58:47.16#ibcon#about to read 4, iclass 32, count 0 2006.202.00:58:47.16#ibcon#read 4, iclass 32, count 0 2006.202.00:58:47.16#ibcon#about to read 5, iclass 32, count 0 2006.202.00:58:47.16#ibcon#read 5, iclass 32, count 0 2006.202.00:58:47.16#ibcon#about to read 6, iclass 32, count 0 2006.202.00:58:47.16#ibcon#read 6, iclass 32, count 0 2006.202.00:58:47.16#ibcon#end of sib2, iclass 32, count 0 2006.202.00:58:47.16#ibcon#*after write, iclass 32, count 0 2006.202.00:58:47.16#ibcon#*before return 0, iclass 32, count 0 2006.202.00:58:47.16#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:47.16#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:47.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.00:58:47.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.00:58:47.16$vck44/valo=3,564.99 2006.202.00:58:47.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.00:58:47.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.00:58:47.16#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:47.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:47.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:47.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:47.16#ibcon#enter wrdev, iclass 34, count 0 2006.202.00:58:47.16#ibcon#first serial, iclass 34, count 0 2006.202.00:58:47.16#ibcon#enter sib2, iclass 34, count 0 2006.202.00:58:47.16#ibcon#flushed, iclass 34, count 0 2006.202.00:58:47.16#ibcon#about to write, iclass 34, count 0 2006.202.00:58:47.16#ibcon#wrote, iclass 34, count 0 2006.202.00:58:47.16#ibcon#about to read 3, iclass 34, count 0 2006.202.00:58:47.18#ibcon#read 3, iclass 34, count 0 2006.202.00:58:47.18#ibcon#about to read 4, iclass 34, count 0 2006.202.00:58:47.18#ibcon#read 4, iclass 34, count 0 2006.202.00:58:47.18#ibcon#about to read 5, iclass 34, count 0 2006.202.00:58:47.18#ibcon#read 5, iclass 34, count 0 2006.202.00:58:47.18#ibcon#about to read 6, iclass 34, count 0 2006.202.00:58:47.18#ibcon#read 6, iclass 34, count 0 2006.202.00:58:47.18#ibcon#end of sib2, iclass 34, count 0 2006.202.00:58:47.18#ibcon#*mode == 0, iclass 34, count 0 2006.202.00:58:47.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.00:58:47.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.00:58:47.18#ibcon#*before write, iclass 34, count 0 2006.202.00:58:47.18#ibcon#enter sib2, iclass 34, count 0 2006.202.00:58:47.18#ibcon#flushed, iclass 34, count 0 2006.202.00:58:47.18#ibcon#about to write, iclass 34, count 0 2006.202.00:58:47.18#ibcon#wrote, iclass 34, count 0 2006.202.00:58:47.18#ibcon#about to read 3, iclass 34, count 0 2006.202.00:58:47.22#ibcon#read 3, iclass 34, count 0 2006.202.00:58:47.22#ibcon#about to read 4, iclass 34, count 0 2006.202.00:58:47.22#ibcon#read 4, iclass 34, count 0 2006.202.00:58:47.22#ibcon#about to read 5, iclass 34, count 0 2006.202.00:58:47.22#ibcon#read 5, iclass 34, count 0 2006.202.00:58:47.22#ibcon#about to read 6, iclass 34, count 0 2006.202.00:58:47.22#ibcon#read 6, iclass 34, count 0 2006.202.00:58:47.22#ibcon#end of sib2, iclass 34, count 0 2006.202.00:58:47.22#ibcon#*after write, iclass 34, count 0 2006.202.00:58:47.22#ibcon#*before return 0, iclass 34, count 0 2006.202.00:58:47.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:47.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:47.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.00:58:47.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.00:58:47.22$vck44/va=3,8 2006.202.00:58:47.22#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.00:58:47.22#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.00:58:47.22#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:47.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:47.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:47.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:47.28#ibcon#enter wrdev, iclass 36, count 2 2006.202.00:58:47.28#ibcon#first serial, iclass 36, count 2 2006.202.00:58:47.28#ibcon#enter sib2, iclass 36, count 2 2006.202.00:58:47.28#ibcon#flushed, iclass 36, count 2 2006.202.00:58:47.28#ibcon#about to write, iclass 36, count 2 2006.202.00:58:47.28#ibcon#wrote, iclass 36, count 2 2006.202.00:58:47.28#ibcon#about to read 3, iclass 36, count 2 2006.202.00:58:47.30#ibcon#read 3, iclass 36, count 2 2006.202.00:58:47.30#ibcon#about to read 4, iclass 36, count 2 2006.202.00:58:47.30#ibcon#read 4, iclass 36, count 2 2006.202.00:58:47.30#ibcon#about to read 5, iclass 36, count 2 2006.202.00:58:47.30#ibcon#read 5, iclass 36, count 2 2006.202.00:58:47.30#ibcon#about to read 6, iclass 36, count 2 2006.202.00:58:47.30#ibcon#read 6, iclass 36, count 2 2006.202.00:58:47.30#ibcon#end of sib2, iclass 36, count 2 2006.202.00:58:47.30#ibcon#*mode == 0, iclass 36, count 2 2006.202.00:58:47.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.00:58:47.30#ibcon#[25=AT03-08\r\n] 2006.202.00:58:47.30#ibcon#*before write, iclass 36, count 2 2006.202.00:58:47.30#ibcon#enter sib2, iclass 36, count 2 2006.202.00:58:47.30#ibcon#flushed, iclass 36, count 2 2006.202.00:58:47.30#ibcon#about to write, iclass 36, count 2 2006.202.00:58:47.30#ibcon#wrote, iclass 36, count 2 2006.202.00:58:47.30#ibcon#about to read 3, iclass 36, count 2 2006.202.00:58:47.33#ibcon#read 3, iclass 36, count 2 2006.202.00:58:47.33#ibcon#about to read 4, iclass 36, count 2 2006.202.00:58:47.33#ibcon#read 4, iclass 36, count 2 2006.202.00:58:47.33#ibcon#about to read 5, iclass 36, count 2 2006.202.00:58:47.33#ibcon#read 5, iclass 36, count 2 2006.202.00:58:47.33#ibcon#about to read 6, iclass 36, count 2 2006.202.00:58:47.33#ibcon#read 6, iclass 36, count 2 2006.202.00:58:47.33#ibcon#end of sib2, iclass 36, count 2 2006.202.00:58:47.33#ibcon#*after write, iclass 36, count 2 2006.202.00:58:47.33#ibcon#*before return 0, iclass 36, count 2 2006.202.00:58:47.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:47.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:47.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.00:58:47.33#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:47.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:47.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:47.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:47.45#ibcon#enter wrdev, iclass 36, count 0 2006.202.00:58:47.45#ibcon#first serial, iclass 36, count 0 2006.202.00:58:47.45#ibcon#enter sib2, iclass 36, count 0 2006.202.00:58:47.45#ibcon#flushed, iclass 36, count 0 2006.202.00:58:47.45#ibcon#about to write, iclass 36, count 0 2006.202.00:58:47.45#ibcon#wrote, iclass 36, count 0 2006.202.00:58:47.45#ibcon#about to read 3, iclass 36, count 0 2006.202.00:58:47.47#ibcon#read 3, iclass 36, count 0 2006.202.00:58:47.47#ibcon#about to read 4, iclass 36, count 0 2006.202.00:58:47.47#ibcon#read 4, iclass 36, count 0 2006.202.00:58:47.47#ibcon#about to read 5, iclass 36, count 0 2006.202.00:58:47.47#ibcon#read 5, iclass 36, count 0 2006.202.00:58:47.47#ibcon#about to read 6, iclass 36, count 0 2006.202.00:58:47.47#ibcon#read 6, iclass 36, count 0 2006.202.00:58:47.47#ibcon#end of sib2, iclass 36, count 0 2006.202.00:58:47.47#ibcon#*mode == 0, iclass 36, count 0 2006.202.00:58:47.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.00:58:47.47#ibcon#[25=USB\r\n] 2006.202.00:58:47.47#ibcon#*before write, iclass 36, count 0 2006.202.00:58:47.47#ibcon#enter sib2, iclass 36, count 0 2006.202.00:58:47.47#ibcon#flushed, iclass 36, count 0 2006.202.00:58:47.47#ibcon#about to write, iclass 36, count 0 2006.202.00:58:47.47#ibcon#wrote, iclass 36, count 0 2006.202.00:58:47.47#ibcon#about to read 3, iclass 36, count 0 2006.202.00:58:47.50#ibcon#read 3, iclass 36, count 0 2006.202.00:58:47.50#ibcon#about to read 4, iclass 36, count 0 2006.202.00:58:47.50#ibcon#read 4, iclass 36, count 0 2006.202.00:58:47.50#ibcon#about to read 5, iclass 36, count 0 2006.202.00:58:47.50#ibcon#read 5, iclass 36, count 0 2006.202.00:58:47.50#ibcon#about to read 6, iclass 36, count 0 2006.202.00:58:47.50#ibcon#read 6, iclass 36, count 0 2006.202.00:58:47.50#ibcon#end of sib2, iclass 36, count 0 2006.202.00:58:47.50#ibcon#*after write, iclass 36, count 0 2006.202.00:58:47.50#ibcon#*before return 0, iclass 36, count 0 2006.202.00:58:47.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:47.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:47.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.00:58:47.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.00:58:47.50$vck44/valo=4,624.99 2006.202.00:58:47.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.00:58:47.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.00:58:47.50#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:47.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:47.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:47.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:47.50#ibcon#enter wrdev, iclass 38, count 0 2006.202.00:58:47.50#ibcon#first serial, iclass 38, count 0 2006.202.00:58:47.50#ibcon#enter sib2, iclass 38, count 0 2006.202.00:58:47.50#ibcon#flushed, iclass 38, count 0 2006.202.00:58:47.50#ibcon#about to write, iclass 38, count 0 2006.202.00:58:47.50#ibcon#wrote, iclass 38, count 0 2006.202.00:58:47.50#ibcon#about to read 3, iclass 38, count 0 2006.202.00:58:47.52#ibcon#read 3, iclass 38, count 0 2006.202.00:58:47.52#ibcon#about to read 4, iclass 38, count 0 2006.202.00:58:47.52#ibcon#read 4, iclass 38, count 0 2006.202.00:58:47.52#ibcon#about to read 5, iclass 38, count 0 2006.202.00:58:47.52#ibcon#read 5, iclass 38, count 0 2006.202.00:58:47.52#ibcon#about to read 6, iclass 38, count 0 2006.202.00:58:47.52#ibcon#read 6, iclass 38, count 0 2006.202.00:58:47.52#ibcon#end of sib2, iclass 38, count 0 2006.202.00:58:47.52#ibcon#*mode == 0, iclass 38, count 0 2006.202.00:58:47.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.00:58:47.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.00:58:47.52#ibcon#*before write, iclass 38, count 0 2006.202.00:58:47.52#ibcon#enter sib2, iclass 38, count 0 2006.202.00:58:47.52#ibcon#flushed, iclass 38, count 0 2006.202.00:58:47.52#ibcon#about to write, iclass 38, count 0 2006.202.00:58:47.52#ibcon#wrote, iclass 38, count 0 2006.202.00:58:47.52#ibcon#about to read 3, iclass 38, count 0 2006.202.00:58:47.56#ibcon#read 3, iclass 38, count 0 2006.202.00:58:47.56#ibcon#about to read 4, iclass 38, count 0 2006.202.00:58:47.56#ibcon#read 4, iclass 38, count 0 2006.202.00:58:47.56#ibcon#about to read 5, iclass 38, count 0 2006.202.00:58:47.56#ibcon#read 5, iclass 38, count 0 2006.202.00:58:47.56#ibcon#about to read 6, iclass 38, count 0 2006.202.00:58:47.56#ibcon#read 6, iclass 38, count 0 2006.202.00:58:47.56#ibcon#end of sib2, iclass 38, count 0 2006.202.00:58:47.56#ibcon#*after write, iclass 38, count 0 2006.202.00:58:47.56#ibcon#*before return 0, iclass 38, count 0 2006.202.00:58:47.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:47.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:47.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.00:58:47.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.00:58:47.56$vck44/va=4,7 2006.202.00:58:47.56#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.202.00:58:47.56#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.202.00:58:47.56#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:47.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:47.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:47.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:47.62#ibcon#enter wrdev, iclass 40, count 2 2006.202.00:58:47.62#ibcon#first serial, iclass 40, count 2 2006.202.00:58:47.62#ibcon#enter sib2, iclass 40, count 2 2006.202.00:58:47.62#ibcon#flushed, iclass 40, count 2 2006.202.00:58:47.62#ibcon#about to write, iclass 40, count 2 2006.202.00:58:47.62#ibcon#wrote, iclass 40, count 2 2006.202.00:58:47.62#ibcon#about to read 3, iclass 40, count 2 2006.202.00:58:47.64#ibcon#read 3, iclass 40, count 2 2006.202.00:58:47.64#ibcon#about to read 4, iclass 40, count 2 2006.202.00:58:47.64#ibcon#read 4, iclass 40, count 2 2006.202.00:58:47.64#ibcon#about to read 5, iclass 40, count 2 2006.202.00:58:47.64#ibcon#read 5, iclass 40, count 2 2006.202.00:58:47.64#ibcon#about to read 6, iclass 40, count 2 2006.202.00:58:47.64#ibcon#read 6, iclass 40, count 2 2006.202.00:58:47.64#ibcon#end of sib2, iclass 40, count 2 2006.202.00:58:47.64#ibcon#*mode == 0, iclass 40, count 2 2006.202.00:58:47.64#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.202.00:58:47.64#ibcon#[25=AT04-07\r\n] 2006.202.00:58:47.64#ibcon#*before write, iclass 40, count 2 2006.202.00:58:47.64#ibcon#enter sib2, iclass 40, count 2 2006.202.00:58:47.64#ibcon#flushed, iclass 40, count 2 2006.202.00:58:47.64#ibcon#about to write, iclass 40, count 2 2006.202.00:58:47.64#ibcon#wrote, iclass 40, count 2 2006.202.00:58:47.64#ibcon#about to read 3, iclass 40, count 2 2006.202.00:58:47.67#ibcon#read 3, iclass 40, count 2 2006.202.00:58:47.71#ibcon#about to read 4, iclass 40, count 2 2006.202.00:58:47.71#ibcon#read 4, iclass 40, count 2 2006.202.00:58:47.71#ibcon#about to read 5, iclass 40, count 2 2006.202.00:58:47.71#ibcon#read 5, iclass 40, count 2 2006.202.00:58:47.71#ibcon#about to read 6, iclass 40, count 2 2006.202.00:58:47.71#ibcon#read 6, iclass 40, count 2 2006.202.00:58:47.71#ibcon#end of sib2, iclass 40, count 2 2006.202.00:58:47.71#ibcon#*after write, iclass 40, count 2 2006.202.00:58:47.71#ibcon#*before return 0, iclass 40, count 2 2006.202.00:58:47.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:47.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:47.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.202.00:58:47.71#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:47.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:47.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:47.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:47.83#ibcon#enter wrdev, iclass 40, count 0 2006.202.00:58:47.83#ibcon#first serial, iclass 40, count 0 2006.202.00:58:47.83#ibcon#enter sib2, iclass 40, count 0 2006.202.00:58:47.83#ibcon#flushed, iclass 40, count 0 2006.202.00:58:47.83#ibcon#about to write, iclass 40, count 0 2006.202.00:58:47.83#ibcon#wrote, iclass 40, count 0 2006.202.00:58:47.83#ibcon#about to read 3, iclass 40, count 0 2006.202.00:58:47.85#ibcon#read 3, iclass 40, count 0 2006.202.00:58:47.85#ibcon#about to read 4, iclass 40, count 0 2006.202.00:58:47.85#ibcon#read 4, iclass 40, count 0 2006.202.00:58:47.85#ibcon#about to read 5, iclass 40, count 0 2006.202.00:58:47.85#ibcon#read 5, iclass 40, count 0 2006.202.00:58:47.85#ibcon#about to read 6, iclass 40, count 0 2006.202.00:58:47.85#ibcon#read 6, iclass 40, count 0 2006.202.00:58:47.85#ibcon#end of sib2, iclass 40, count 0 2006.202.00:58:47.85#ibcon#*mode == 0, iclass 40, count 0 2006.202.00:58:47.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.00:58:47.85#ibcon#[25=USB\r\n] 2006.202.00:58:47.85#ibcon#*before write, iclass 40, count 0 2006.202.00:58:47.85#ibcon#enter sib2, iclass 40, count 0 2006.202.00:58:47.85#ibcon#flushed, iclass 40, count 0 2006.202.00:58:47.85#ibcon#about to write, iclass 40, count 0 2006.202.00:58:47.85#ibcon#wrote, iclass 40, count 0 2006.202.00:58:47.85#ibcon#about to read 3, iclass 40, count 0 2006.202.00:58:47.88#ibcon#read 3, iclass 40, count 0 2006.202.00:58:47.88#ibcon#about to read 4, iclass 40, count 0 2006.202.00:58:47.88#ibcon#read 4, iclass 40, count 0 2006.202.00:58:47.88#ibcon#about to read 5, iclass 40, count 0 2006.202.00:58:47.88#ibcon#read 5, iclass 40, count 0 2006.202.00:58:47.88#ibcon#about to read 6, iclass 40, count 0 2006.202.00:58:47.88#ibcon#read 6, iclass 40, count 0 2006.202.00:58:47.88#ibcon#end of sib2, iclass 40, count 0 2006.202.00:58:47.88#ibcon#*after write, iclass 40, count 0 2006.202.00:58:47.88#ibcon#*before return 0, iclass 40, count 0 2006.202.00:58:47.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:47.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:47.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.00:58:47.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.00:58:47.88$vck44/valo=5,734.99 2006.202.00:58:47.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.00:58:47.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.00:58:47.88#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:47.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:47.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:47.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:47.88#ibcon#enter wrdev, iclass 4, count 0 2006.202.00:58:47.88#ibcon#first serial, iclass 4, count 0 2006.202.00:58:47.88#ibcon#enter sib2, iclass 4, count 0 2006.202.00:58:47.88#ibcon#flushed, iclass 4, count 0 2006.202.00:58:47.88#ibcon#about to write, iclass 4, count 0 2006.202.00:58:47.88#ibcon#wrote, iclass 4, count 0 2006.202.00:58:47.88#ibcon#about to read 3, iclass 4, count 0 2006.202.00:58:47.90#ibcon#read 3, iclass 4, count 0 2006.202.00:58:47.90#ibcon#about to read 4, iclass 4, count 0 2006.202.00:58:47.90#ibcon#read 4, iclass 4, count 0 2006.202.00:58:47.90#ibcon#about to read 5, iclass 4, count 0 2006.202.00:58:47.90#ibcon#read 5, iclass 4, count 0 2006.202.00:58:47.90#ibcon#about to read 6, iclass 4, count 0 2006.202.00:58:47.90#ibcon#read 6, iclass 4, count 0 2006.202.00:58:47.90#ibcon#end of sib2, iclass 4, count 0 2006.202.00:58:47.90#ibcon#*mode == 0, iclass 4, count 0 2006.202.00:58:47.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.00:58:47.90#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.00:58:47.90#ibcon#*before write, iclass 4, count 0 2006.202.00:58:47.90#ibcon#enter sib2, iclass 4, count 0 2006.202.00:58:47.90#ibcon#flushed, iclass 4, count 0 2006.202.00:58:47.90#ibcon#about to write, iclass 4, count 0 2006.202.00:58:47.90#ibcon#wrote, iclass 4, count 0 2006.202.00:58:47.90#ibcon#about to read 3, iclass 4, count 0 2006.202.00:58:47.94#ibcon#read 3, iclass 4, count 0 2006.202.00:58:47.94#ibcon#about to read 4, iclass 4, count 0 2006.202.00:58:47.94#ibcon#read 4, iclass 4, count 0 2006.202.00:58:47.94#ibcon#about to read 5, iclass 4, count 0 2006.202.00:58:47.94#ibcon#read 5, iclass 4, count 0 2006.202.00:58:47.94#ibcon#about to read 6, iclass 4, count 0 2006.202.00:58:47.94#ibcon#read 6, iclass 4, count 0 2006.202.00:58:47.94#ibcon#end of sib2, iclass 4, count 0 2006.202.00:58:47.94#ibcon#*after write, iclass 4, count 0 2006.202.00:58:47.94#ibcon#*before return 0, iclass 4, count 0 2006.202.00:58:47.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:47.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:47.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.00:58:47.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.00:58:47.94$vck44/va=5,4 2006.202.00:58:47.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.202.00:58:47.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.202.00:58:47.94#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:47.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:48.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:48.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:48.00#ibcon#enter wrdev, iclass 6, count 2 2006.202.00:58:48.00#ibcon#first serial, iclass 6, count 2 2006.202.00:58:48.00#ibcon#enter sib2, iclass 6, count 2 2006.202.00:58:48.00#ibcon#flushed, iclass 6, count 2 2006.202.00:58:48.00#ibcon#about to write, iclass 6, count 2 2006.202.00:58:48.00#ibcon#wrote, iclass 6, count 2 2006.202.00:58:48.00#ibcon#about to read 3, iclass 6, count 2 2006.202.00:58:48.02#ibcon#read 3, iclass 6, count 2 2006.202.00:58:48.02#ibcon#about to read 4, iclass 6, count 2 2006.202.00:58:48.02#ibcon#read 4, iclass 6, count 2 2006.202.00:58:48.02#ibcon#about to read 5, iclass 6, count 2 2006.202.00:58:48.02#ibcon#read 5, iclass 6, count 2 2006.202.00:58:48.02#ibcon#about to read 6, iclass 6, count 2 2006.202.00:58:48.02#ibcon#read 6, iclass 6, count 2 2006.202.00:58:48.02#ibcon#end of sib2, iclass 6, count 2 2006.202.00:58:48.02#ibcon#*mode == 0, iclass 6, count 2 2006.202.00:58:48.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.202.00:58:48.02#ibcon#[25=AT05-04\r\n] 2006.202.00:58:48.02#ibcon#*before write, iclass 6, count 2 2006.202.00:58:48.02#ibcon#enter sib2, iclass 6, count 2 2006.202.00:58:48.02#ibcon#flushed, iclass 6, count 2 2006.202.00:58:48.02#ibcon#about to write, iclass 6, count 2 2006.202.00:58:48.02#ibcon#wrote, iclass 6, count 2 2006.202.00:58:48.02#ibcon#about to read 3, iclass 6, count 2 2006.202.00:58:48.05#ibcon#read 3, iclass 6, count 2 2006.202.00:58:48.05#ibcon#about to read 4, iclass 6, count 2 2006.202.00:58:48.05#ibcon#read 4, iclass 6, count 2 2006.202.00:58:48.05#ibcon#about to read 5, iclass 6, count 2 2006.202.00:58:48.05#ibcon#read 5, iclass 6, count 2 2006.202.00:58:48.05#ibcon#about to read 6, iclass 6, count 2 2006.202.00:58:48.05#ibcon#read 6, iclass 6, count 2 2006.202.00:58:48.05#ibcon#end of sib2, iclass 6, count 2 2006.202.00:58:48.05#ibcon#*after write, iclass 6, count 2 2006.202.00:58:48.05#ibcon#*before return 0, iclass 6, count 2 2006.202.00:58:48.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:48.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:48.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.202.00:58:48.05#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:48.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:48.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:48.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:48.17#ibcon#enter wrdev, iclass 6, count 0 2006.202.00:58:48.17#ibcon#first serial, iclass 6, count 0 2006.202.00:58:48.17#ibcon#enter sib2, iclass 6, count 0 2006.202.00:58:48.17#ibcon#flushed, iclass 6, count 0 2006.202.00:58:48.17#ibcon#about to write, iclass 6, count 0 2006.202.00:58:48.17#ibcon#wrote, iclass 6, count 0 2006.202.00:58:48.17#ibcon#about to read 3, iclass 6, count 0 2006.202.00:58:48.19#ibcon#read 3, iclass 6, count 0 2006.202.00:58:48.19#ibcon#about to read 4, iclass 6, count 0 2006.202.00:58:48.19#ibcon#read 4, iclass 6, count 0 2006.202.00:58:48.19#ibcon#about to read 5, iclass 6, count 0 2006.202.00:58:48.19#ibcon#read 5, iclass 6, count 0 2006.202.00:58:48.19#ibcon#about to read 6, iclass 6, count 0 2006.202.00:58:48.19#ibcon#read 6, iclass 6, count 0 2006.202.00:58:48.19#ibcon#end of sib2, iclass 6, count 0 2006.202.00:58:48.19#ibcon#*mode == 0, iclass 6, count 0 2006.202.00:58:48.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.00:58:48.19#ibcon#[25=USB\r\n] 2006.202.00:58:48.19#ibcon#*before write, iclass 6, count 0 2006.202.00:58:48.19#ibcon#enter sib2, iclass 6, count 0 2006.202.00:58:48.19#ibcon#flushed, iclass 6, count 0 2006.202.00:58:48.19#ibcon#about to write, iclass 6, count 0 2006.202.00:58:48.19#ibcon#wrote, iclass 6, count 0 2006.202.00:58:48.19#ibcon#about to read 3, iclass 6, count 0 2006.202.00:58:48.22#ibcon#read 3, iclass 6, count 0 2006.202.00:58:48.22#ibcon#about to read 4, iclass 6, count 0 2006.202.00:58:48.22#ibcon#read 4, iclass 6, count 0 2006.202.00:58:48.22#ibcon#about to read 5, iclass 6, count 0 2006.202.00:58:48.22#ibcon#read 5, iclass 6, count 0 2006.202.00:58:48.22#ibcon#about to read 6, iclass 6, count 0 2006.202.00:58:48.22#ibcon#read 6, iclass 6, count 0 2006.202.00:58:48.22#ibcon#end of sib2, iclass 6, count 0 2006.202.00:58:48.22#ibcon#*after write, iclass 6, count 0 2006.202.00:58:48.22#ibcon#*before return 0, iclass 6, count 0 2006.202.00:58:48.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:48.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:48.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.00:58:48.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.00:58:48.22$vck44/valo=6,814.99 2006.202.00:58:48.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.00:58:48.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.00:58:48.22#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:48.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:48.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:48.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:48.22#ibcon#enter wrdev, iclass 10, count 0 2006.202.00:58:48.22#ibcon#first serial, iclass 10, count 0 2006.202.00:58:48.22#ibcon#enter sib2, iclass 10, count 0 2006.202.00:58:48.22#ibcon#flushed, iclass 10, count 0 2006.202.00:58:48.22#ibcon#about to write, iclass 10, count 0 2006.202.00:58:48.22#ibcon#wrote, iclass 10, count 0 2006.202.00:58:48.22#ibcon#about to read 3, iclass 10, count 0 2006.202.00:58:48.24#ibcon#read 3, iclass 10, count 0 2006.202.00:58:48.24#ibcon#about to read 4, iclass 10, count 0 2006.202.00:58:48.24#ibcon#read 4, iclass 10, count 0 2006.202.00:58:48.24#ibcon#about to read 5, iclass 10, count 0 2006.202.00:58:48.24#ibcon#read 5, iclass 10, count 0 2006.202.00:58:48.24#ibcon#about to read 6, iclass 10, count 0 2006.202.00:58:48.24#ibcon#read 6, iclass 10, count 0 2006.202.00:58:48.24#ibcon#end of sib2, iclass 10, count 0 2006.202.00:58:48.24#ibcon#*mode == 0, iclass 10, count 0 2006.202.00:58:48.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.00:58:48.24#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.00:58:48.24#ibcon#*before write, iclass 10, count 0 2006.202.00:58:48.24#ibcon#enter sib2, iclass 10, count 0 2006.202.00:58:48.24#ibcon#flushed, iclass 10, count 0 2006.202.00:58:48.24#ibcon#about to write, iclass 10, count 0 2006.202.00:58:48.24#ibcon#wrote, iclass 10, count 0 2006.202.00:58:48.24#ibcon#about to read 3, iclass 10, count 0 2006.202.00:58:48.28#ibcon#read 3, iclass 10, count 0 2006.202.00:58:48.28#ibcon#about to read 4, iclass 10, count 0 2006.202.00:58:48.28#ibcon#read 4, iclass 10, count 0 2006.202.00:58:48.28#ibcon#about to read 5, iclass 10, count 0 2006.202.00:58:48.28#ibcon#read 5, iclass 10, count 0 2006.202.00:58:48.28#ibcon#about to read 6, iclass 10, count 0 2006.202.00:58:48.28#ibcon#read 6, iclass 10, count 0 2006.202.00:58:48.28#ibcon#end of sib2, iclass 10, count 0 2006.202.00:58:48.28#ibcon#*after write, iclass 10, count 0 2006.202.00:58:48.28#ibcon#*before return 0, iclass 10, count 0 2006.202.00:58:48.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:48.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:48.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.00:58:48.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.00:58:48.28$vck44/va=6,5 2006.202.00:58:48.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.202.00:58:48.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.202.00:58:48.28#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:48.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:48.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:48.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:48.34#ibcon#enter wrdev, iclass 12, count 2 2006.202.00:58:48.34#ibcon#first serial, iclass 12, count 2 2006.202.00:58:48.34#ibcon#enter sib2, iclass 12, count 2 2006.202.00:58:48.34#ibcon#flushed, iclass 12, count 2 2006.202.00:58:48.34#ibcon#about to write, iclass 12, count 2 2006.202.00:58:48.34#ibcon#wrote, iclass 12, count 2 2006.202.00:58:48.34#ibcon#about to read 3, iclass 12, count 2 2006.202.00:58:48.36#ibcon#read 3, iclass 12, count 2 2006.202.00:58:48.36#ibcon#about to read 4, iclass 12, count 2 2006.202.00:58:48.36#ibcon#read 4, iclass 12, count 2 2006.202.00:58:48.36#ibcon#about to read 5, iclass 12, count 2 2006.202.00:58:48.36#ibcon#read 5, iclass 12, count 2 2006.202.00:58:48.36#ibcon#about to read 6, iclass 12, count 2 2006.202.00:58:48.36#ibcon#read 6, iclass 12, count 2 2006.202.00:58:48.36#ibcon#end of sib2, iclass 12, count 2 2006.202.00:58:48.36#ibcon#*mode == 0, iclass 12, count 2 2006.202.00:58:48.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.202.00:58:48.36#ibcon#[25=AT06-05\r\n] 2006.202.00:58:48.36#ibcon#*before write, iclass 12, count 2 2006.202.00:58:48.36#ibcon#enter sib2, iclass 12, count 2 2006.202.00:58:48.36#ibcon#flushed, iclass 12, count 2 2006.202.00:58:48.36#ibcon#about to write, iclass 12, count 2 2006.202.00:58:48.36#ibcon#wrote, iclass 12, count 2 2006.202.00:58:48.36#ibcon#about to read 3, iclass 12, count 2 2006.202.00:58:48.39#ibcon#read 3, iclass 12, count 2 2006.202.00:58:48.39#ibcon#about to read 4, iclass 12, count 2 2006.202.00:58:48.39#ibcon#read 4, iclass 12, count 2 2006.202.00:58:48.39#ibcon#about to read 5, iclass 12, count 2 2006.202.00:58:48.39#ibcon#read 5, iclass 12, count 2 2006.202.00:58:48.39#ibcon#about to read 6, iclass 12, count 2 2006.202.00:58:48.39#ibcon#read 6, iclass 12, count 2 2006.202.00:58:48.39#ibcon#end of sib2, iclass 12, count 2 2006.202.00:58:48.39#ibcon#*after write, iclass 12, count 2 2006.202.00:58:48.39#ibcon#*before return 0, iclass 12, count 2 2006.202.00:58:48.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:48.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:48.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.202.00:58:48.39#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:48.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:48.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:48.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:48.51#ibcon#enter wrdev, iclass 12, count 0 2006.202.00:58:48.51#ibcon#first serial, iclass 12, count 0 2006.202.00:58:48.51#ibcon#enter sib2, iclass 12, count 0 2006.202.00:58:48.51#ibcon#flushed, iclass 12, count 0 2006.202.00:58:48.51#ibcon#about to write, iclass 12, count 0 2006.202.00:58:48.51#ibcon#wrote, iclass 12, count 0 2006.202.00:58:48.51#ibcon#about to read 3, iclass 12, count 0 2006.202.00:58:48.53#ibcon#read 3, iclass 12, count 0 2006.202.00:58:48.53#ibcon#about to read 4, iclass 12, count 0 2006.202.00:58:48.53#ibcon#read 4, iclass 12, count 0 2006.202.00:58:48.53#ibcon#about to read 5, iclass 12, count 0 2006.202.00:58:48.53#ibcon#read 5, iclass 12, count 0 2006.202.00:58:48.53#ibcon#about to read 6, iclass 12, count 0 2006.202.00:58:48.53#ibcon#read 6, iclass 12, count 0 2006.202.00:58:48.53#ibcon#end of sib2, iclass 12, count 0 2006.202.00:58:48.53#ibcon#*mode == 0, iclass 12, count 0 2006.202.00:58:48.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.00:58:48.53#ibcon#[25=USB\r\n] 2006.202.00:58:48.53#ibcon#*before write, iclass 12, count 0 2006.202.00:58:48.53#ibcon#enter sib2, iclass 12, count 0 2006.202.00:58:48.53#ibcon#flushed, iclass 12, count 0 2006.202.00:58:48.53#ibcon#about to write, iclass 12, count 0 2006.202.00:58:48.53#ibcon#wrote, iclass 12, count 0 2006.202.00:58:48.53#ibcon#about to read 3, iclass 12, count 0 2006.202.00:58:48.56#ibcon#read 3, iclass 12, count 0 2006.202.00:58:48.56#ibcon#about to read 4, iclass 12, count 0 2006.202.00:58:48.56#ibcon#read 4, iclass 12, count 0 2006.202.00:58:48.56#ibcon#about to read 5, iclass 12, count 0 2006.202.00:58:48.56#ibcon#read 5, iclass 12, count 0 2006.202.00:58:48.56#ibcon#about to read 6, iclass 12, count 0 2006.202.00:58:48.56#ibcon#read 6, iclass 12, count 0 2006.202.00:58:48.56#ibcon#end of sib2, iclass 12, count 0 2006.202.00:58:48.56#ibcon#*after write, iclass 12, count 0 2006.202.00:58:48.56#ibcon#*before return 0, iclass 12, count 0 2006.202.00:58:48.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:48.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:48.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.00:58:48.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.00:58:48.56$vck44/valo=7,864.99 2006.202.00:58:48.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.00:58:48.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.00:58:48.56#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:48.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:48.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:48.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:48.56#ibcon#enter wrdev, iclass 14, count 0 2006.202.00:58:48.56#ibcon#first serial, iclass 14, count 0 2006.202.00:58:48.56#ibcon#enter sib2, iclass 14, count 0 2006.202.00:58:48.56#ibcon#flushed, iclass 14, count 0 2006.202.00:58:48.56#ibcon#about to write, iclass 14, count 0 2006.202.00:58:48.56#ibcon#wrote, iclass 14, count 0 2006.202.00:58:48.56#ibcon#about to read 3, iclass 14, count 0 2006.202.00:58:48.58#ibcon#read 3, iclass 14, count 0 2006.202.00:58:48.58#ibcon#about to read 4, iclass 14, count 0 2006.202.00:58:48.58#ibcon#read 4, iclass 14, count 0 2006.202.00:58:48.58#ibcon#about to read 5, iclass 14, count 0 2006.202.00:58:48.58#ibcon#read 5, iclass 14, count 0 2006.202.00:58:48.58#ibcon#about to read 6, iclass 14, count 0 2006.202.00:58:48.58#ibcon#read 6, iclass 14, count 0 2006.202.00:58:48.58#ibcon#end of sib2, iclass 14, count 0 2006.202.00:58:48.58#ibcon#*mode == 0, iclass 14, count 0 2006.202.00:58:48.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.00:58:48.58#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.00:58:48.58#ibcon#*before write, iclass 14, count 0 2006.202.00:58:48.58#ibcon#enter sib2, iclass 14, count 0 2006.202.00:58:48.58#ibcon#flushed, iclass 14, count 0 2006.202.00:58:48.58#ibcon#about to write, iclass 14, count 0 2006.202.00:58:48.58#ibcon#wrote, iclass 14, count 0 2006.202.00:58:48.58#ibcon#about to read 3, iclass 14, count 0 2006.202.00:58:48.62#ibcon#read 3, iclass 14, count 0 2006.202.00:58:48.62#ibcon#about to read 4, iclass 14, count 0 2006.202.00:58:48.62#ibcon#read 4, iclass 14, count 0 2006.202.00:58:48.62#ibcon#about to read 5, iclass 14, count 0 2006.202.00:58:48.62#ibcon#read 5, iclass 14, count 0 2006.202.00:58:48.62#ibcon#about to read 6, iclass 14, count 0 2006.202.00:58:48.62#ibcon#read 6, iclass 14, count 0 2006.202.00:58:48.62#ibcon#end of sib2, iclass 14, count 0 2006.202.00:58:48.62#ibcon#*after write, iclass 14, count 0 2006.202.00:58:48.62#ibcon#*before return 0, iclass 14, count 0 2006.202.00:58:48.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:48.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:48.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.00:58:48.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.00:58:48.62$vck44/va=7,5 2006.202.00:58:48.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.00:58:48.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.00:58:48.62#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:48.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:48.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:48.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:48.68#ibcon#enter wrdev, iclass 16, count 2 2006.202.00:58:48.68#ibcon#first serial, iclass 16, count 2 2006.202.00:58:48.68#ibcon#enter sib2, iclass 16, count 2 2006.202.00:58:48.68#ibcon#flushed, iclass 16, count 2 2006.202.00:58:48.68#ibcon#about to write, iclass 16, count 2 2006.202.00:58:48.68#ibcon#wrote, iclass 16, count 2 2006.202.00:58:48.68#ibcon#about to read 3, iclass 16, count 2 2006.202.00:58:48.70#ibcon#read 3, iclass 16, count 2 2006.202.00:58:48.70#ibcon#about to read 4, iclass 16, count 2 2006.202.00:58:48.70#ibcon#read 4, iclass 16, count 2 2006.202.00:58:48.70#ibcon#about to read 5, iclass 16, count 2 2006.202.00:58:48.70#ibcon#read 5, iclass 16, count 2 2006.202.00:58:48.70#ibcon#about to read 6, iclass 16, count 2 2006.202.00:58:48.70#ibcon#read 6, iclass 16, count 2 2006.202.00:58:48.70#ibcon#end of sib2, iclass 16, count 2 2006.202.00:58:48.70#ibcon#*mode == 0, iclass 16, count 2 2006.202.00:58:48.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.00:58:48.70#ibcon#[25=AT07-05\r\n] 2006.202.00:58:48.70#ibcon#*before write, iclass 16, count 2 2006.202.00:58:48.70#ibcon#enter sib2, iclass 16, count 2 2006.202.00:58:48.70#ibcon#flushed, iclass 16, count 2 2006.202.00:58:48.70#ibcon#about to write, iclass 16, count 2 2006.202.00:58:48.70#ibcon#wrote, iclass 16, count 2 2006.202.00:58:48.70#ibcon#about to read 3, iclass 16, count 2 2006.202.00:58:48.70#abcon#<5=/04 2.4 5.2 20.341001001.3\r\n> 2006.202.00:58:48.72#abcon#{5=INTERFACE CLEAR} 2006.202.00:58:48.73#ibcon#read 3, iclass 16, count 2 2006.202.00:58:48.73#ibcon#about to read 4, iclass 16, count 2 2006.202.00:58:48.73#ibcon#read 4, iclass 16, count 2 2006.202.00:58:48.73#ibcon#about to read 5, iclass 16, count 2 2006.202.00:58:48.73#ibcon#read 5, iclass 16, count 2 2006.202.00:58:48.73#ibcon#about to read 6, iclass 16, count 2 2006.202.00:58:48.73#ibcon#read 6, iclass 16, count 2 2006.202.00:58:48.73#ibcon#end of sib2, iclass 16, count 2 2006.202.00:58:48.73#ibcon#*after write, iclass 16, count 2 2006.202.00:58:48.73#ibcon#*before return 0, iclass 16, count 2 2006.202.00:58:48.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:48.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:48.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.00:58:48.73#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:48.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:48.78#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:58:48.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:48.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:48.85#ibcon#enter wrdev, iclass 16, count 0 2006.202.00:58:48.85#ibcon#first serial, iclass 16, count 0 2006.202.00:58:48.85#ibcon#enter sib2, iclass 16, count 0 2006.202.00:58:48.85#ibcon#flushed, iclass 16, count 0 2006.202.00:58:48.85#ibcon#about to write, iclass 16, count 0 2006.202.00:58:48.85#ibcon#wrote, iclass 16, count 0 2006.202.00:58:48.85#ibcon#about to read 3, iclass 16, count 0 2006.202.00:58:48.87#ibcon#read 3, iclass 16, count 0 2006.202.00:58:48.87#ibcon#about to read 4, iclass 16, count 0 2006.202.00:58:48.87#ibcon#read 4, iclass 16, count 0 2006.202.00:58:48.87#ibcon#about to read 5, iclass 16, count 0 2006.202.00:58:48.87#ibcon#read 5, iclass 16, count 0 2006.202.00:58:48.87#ibcon#about to read 6, iclass 16, count 0 2006.202.00:58:48.87#ibcon#read 6, iclass 16, count 0 2006.202.00:58:48.87#ibcon#end of sib2, iclass 16, count 0 2006.202.00:58:48.87#ibcon#*mode == 0, iclass 16, count 0 2006.202.00:58:48.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.00:58:48.87#ibcon#[25=USB\r\n] 2006.202.00:58:48.87#ibcon#*before write, iclass 16, count 0 2006.202.00:58:48.87#ibcon#enter sib2, iclass 16, count 0 2006.202.00:58:48.87#ibcon#flushed, iclass 16, count 0 2006.202.00:58:48.87#ibcon#about to write, iclass 16, count 0 2006.202.00:58:48.87#ibcon#wrote, iclass 16, count 0 2006.202.00:58:48.87#ibcon#about to read 3, iclass 16, count 0 2006.202.00:58:48.90#ibcon#read 3, iclass 16, count 0 2006.202.00:58:48.90#ibcon#about to read 4, iclass 16, count 0 2006.202.00:58:48.90#ibcon#read 4, iclass 16, count 0 2006.202.00:58:48.90#ibcon#about to read 5, iclass 16, count 0 2006.202.00:58:48.90#ibcon#read 5, iclass 16, count 0 2006.202.00:58:48.90#ibcon#about to read 6, iclass 16, count 0 2006.202.00:58:48.90#ibcon#read 6, iclass 16, count 0 2006.202.00:58:48.90#ibcon#end of sib2, iclass 16, count 0 2006.202.00:58:48.90#ibcon#*after write, iclass 16, count 0 2006.202.00:58:48.90#ibcon#*before return 0, iclass 16, count 0 2006.202.00:58:48.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:48.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:48.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.00:58:48.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.00:58:48.90$vck44/valo=8,884.99 2006.202.00:58:48.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.00:58:48.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.00:58:48.90#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:48.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:48.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:48.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:48.90#ibcon#enter wrdev, iclass 22, count 0 2006.202.00:58:48.90#ibcon#first serial, iclass 22, count 0 2006.202.00:58:48.90#ibcon#enter sib2, iclass 22, count 0 2006.202.00:58:48.90#ibcon#flushed, iclass 22, count 0 2006.202.00:58:48.90#ibcon#about to write, iclass 22, count 0 2006.202.00:58:48.90#ibcon#wrote, iclass 22, count 0 2006.202.00:58:48.90#ibcon#about to read 3, iclass 22, count 0 2006.202.00:58:48.92#ibcon#read 3, iclass 22, count 0 2006.202.00:58:48.92#ibcon#about to read 4, iclass 22, count 0 2006.202.00:58:48.92#ibcon#read 4, iclass 22, count 0 2006.202.00:58:48.92#ibcon#about to read 5, iclass 22, count 0 2006.202.00:58:48.92#ibcon#read 5, iclass 22, count 0 2006.202.00:58:48.92#ibcon#about to read 6, iclass 22, count 0 2006.202.00:58:48.92#ibcon#read 6, iclass 22, count 0 2006.202.00:58:48.92#ibcon#end of sib2, iclass 22, count 0 2006.202.00:58:48.92#ibcon#*mode == 0, iclass 22, count 0 2006.202.00:58:48.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.00:58:48.92#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.00:58:48.92#ibcon#*before write, iclass 22, count 0 2006.202.00:58:48.92#ibcon#enter sib2, iclass 22, count 0 2006.202.00:58:48.92#ibcon#flushed, iclass 22, count 0 2006.202.00:58:48.92#ibcon#about to write, iclass 22, count 0 2006.202.00:58:48.92#ibcon#wrote, iclass 22, count 0 2006.202.00:58:48.92#ibcon#about to read 3, iclass 22, count 0 2006.202.00:58:48.96#ibcon#read 3, iclass 22, count 0 2006.202.00:58:48.96#ibcon#about to read 4, iclass 22, count 0 2006.202.00:58:48.96#ibcon#read 4, iclass 22, count 0 2006.202.00:58:48.96#ibcon#about to read 5, iclass 22, count 0 2006.202.00:58:48.96#ibcon#read 5, iclass 22, count 0 2006.202.00:58:48.96#ibcon#about to read 6, iclass 22, count 0 2006.202.00:58:48.96#ibcon#read 6, iclass 22, count 0 2006.202.00:58:48.96#ibcon#end of sib2, iclass 22, count 0 2006.202.00:58:48.96#ibcon#*after write, iclass 22, count 0 2006.202.00:58:48.96#ibcon#*before return 0, iclass 22, count 0 2006.202.00:58:48.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:48.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:48.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.00:58:48.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.00:58:48.96$vck44/va=8,4 2006.202.00:58:48.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.00:58:48.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.00:58:48.96#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:48.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:58:49.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:58:49.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:58:49.02#ibcon#enter wrdev, iclass 24, count 2 2006.202.00:58:49.02#ibcon#first serial, iclass 24, count 2 2006.202.00:58:49.02#ibcon#enter sib2, iclass 24, count 2 2006.202.00:58:49.02#ibcon#flushed, iclass 24, count 2 2006.202.00:58:49.02#ibcon#about to write, iclass 24, count 2 2006.202.00:58:49.02#ibcon#wrote, iclass 24, count 2 2006.202.00:58:49.02#ibcon#about to read 3, iclass 24, count 2 2006.202.00:58:49.04#ibcon#read 3, iclass 24, count 2 2006.202.00:58:49.04#ibcon#about to read 4, iclass 24, count 2 2006.202.00:58:49.04#ibcon#read 4, iclass 24, count 2 2006.202.00:58:49.04#ibcon#about to read 5, iclass 24, count 2 2006.202.00:58:49.04#ibcon#read 5, iclass 24, count 2 2006.202.00:58:49.04#ibcon#about to read 6, iclass 24, count 2 2006.202.00:58:49.04#ibcon#read 6, iclass 24, count 2 2006.202.00:58:49.04#ibcon#end of sib2, iclass 24, count 2 2006.202.00:58:49.04#ibcon#*mode == 0, iclass 24, count 2 2006.202.00:58:49.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.00:58:49.04#ibcon#[25=AT08-04\r\n] 2006.202.00:58:49.04#ibcon#*before write, iclass 24, count 2 2006.202.00:58:49.04#ibcon#enter sib2, iclass 24, count 2 2006.202.00:58:49.04#ibcon#flushed, iclass 24, count 2 2006.202.00:58:49.04#ibcon#about to write, iclass 24, count 2 2006.202.00:58:49.04#ibcon#wrote, iclass 24, count 2 2006.202.00:58:49.04#ibcon#about to read 3, iclass 24, count 2 2006.202.00:58:49.07#ibcon#read 3, iclass 24, count 2 2006.202.00:58:49.07#ibcon#about to read 4, iclass 24, count 2 2006.202.00:58:49.07#ibcon#read 4, iclass 24, count 2 2006.202.00:58:49.07#ibcon#about to read 5, iclass 24, count 2 2006.202.00:58:49.07#ibcon#read 5, iclass 24, count 2 2006.202.00:58:49.07#ibcon#about to read 6, iclass 24, count 2 2006.202.00:58:49.07#ibcon#read 6, iclass 24, count 2 2006.202.00:58:49.07#ibcon#end of sib2, iclass 24, count 2 2006.202.00:58:49.07#ibcon#*after write, iclass 24, count 2 2006.202.00:58:49.07#ibcon#*before return 0, iclass 24, count 2 2006.202.00:58:49.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:58:49.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.00:58:49.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.00:58:49.07#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:49.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:58:49.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:58:49.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:58:49.19#ibcon#enter wrdev, iclass 24, count 0 2006.202.00:58:49.19#ibcon#first serial, iclass 24, count 0 2006.202.00:58:49.19#ibcon#enter sib2, iclass 24, count 0 2006.202.00:58:49.19#ibcon#flushed, iclass 24, count 0 2006.202.00:58:49.19#ibcon#about to write, iclass 24, count 0 2006.202.00:58:49.19#ibcon#wrote, iclass 24, count 0 2006.202.00:58:49.19#ibcon#about to read 3, iclass 24, count 0 2006.202.00:58:49.21#ibcon#read 3, iclass 24, count 0 2006.202.00:58:49.21#ibcon#about to read 4, iclass 24, count 0 2006.202.00:58:49.21#ibcon#read 4, iclass 24, count 0 2006.202.00:58:49.21#ibcon#about to read 5, iclass 24, count 0 2006.202.00:58:49.21#ibcon#read 5, iclass 24, count 0 2006.202.00:58:49.21#ibcon#about to read 6, iclass 24, count 0 2006.202.00:58:49.21#ibcon#read 6, iclass 24, count 0 2006.202.00:58:49.21#ibcon#end of sib2, iclass 24, count 0 2006.202.00:58:49.21#ibcon#*mode == 0, iclass 24, count 0 2006.202.00:58:49.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.00:58:49.21#ibcon#[25=USB\r\n] 2006.202.00:58:49.21#ibcon#*before write, iclass 24, count 0 2006.202.00:58:49.21#ibcon#enter sib2, iclass 24, count 0 2006.202.00:58:49.21#ibcon#flushed, iclass 24, count 0 2006.202.00:58:49.21#ibcon#about to write, iclass 24, count 0 2006.202.00:58:49.21#ibcon#wrote, iclass 24, count 0 2006.202.00:58:49.21#ibcon#about to read 3, iclass 24, count 0 2006.202.00:58:49.24#ibcon#read 3, iclass 24, count 0 2006.202.00:58:49.24#ibcon#about to read 4, iclass 24, count 0 2006.202.00:58:49.24#ibcon#read 4, iclass 24, count 0 2006.202.00:58:49.24#ibcon#about to read 5, iclass 24, count 0 2006.202.00:58:49.24#ibcon#read 5, iclass 24, count 0 2006.202.00:58:49.24#ibcon#about to read 6, iclass 24, count 0 2006.202.00:58:49.24#ibcon#read 6, iclass 24, count 0 2006.202.00:58:49.24#ibcon#end of sib2, iclass 24, count 0 2006.202.00:58:49.24#ibcon#*after write, iclass 24, count 0 2006.202.00:58:49.24#ibcon#*before return 0, iclass 24, count 0 2006.202.00:58:49.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:58:49.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.00:58:49.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.00:58:49.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.00:58:49.24$vck44/vblo=1,629.99 2006.202.00:58:49.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.00:58:49.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.00:58:49.24#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:49.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:49.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:49.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:49.24#ibcon#enter wrdev, iclass 26, count 0 2006.202.00:58:49.24#ibcon#first serial, iclass 26, count 0 2006.202.00:58:49.24#ibcon#enter sib2, iclass 26, count 0 2006.202.00:58:49.24#ibcon#flushed, iclass 26, count 0 2006.202.00:58:49.24#ibcon#about to write, iclass 26, count 0 2006.202.00:58:49.24#ibcon#wrote, iclass 26, count 0 2006.202.00:58:49.24#ibcon#about to read 3, iclass 26, count 0 2006.202.00:58:49.26#ibcon#read 3, iclass 26, count 0 2006.202.00:58:49.26#ibcon#about to read 4, iclass 26, count 0 2006.202.00:58:49.26#ibcon#read 4, iclass 26, count 0 2006.202.00:58:49.26#ibcon#about to read 5, iclass 26, count 0 2006.202.00:58:49.26#ibcon#read 5, iclass 26, count 0 2006.202.00:58:49.26#ibcon#about to read 6, iclass 26, count 0 2006.202.00:58:49.26#ibcon#read 6, iclass 26, count 0 2006.202.00:58:49.26#ibcon#end of sib2, iclass 26, count 0 2006.202.00:58:49.26#ibcon#*mode == 0, iclass 26, count 0 2006.202.00:58:49.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.00:58:49.26#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.00:58:49.26#ibcon#*before write, iclass 26, count 0 2006.202.00:58:49.26#ibcon#enter sib2, iclass 26, count 0 2006.202.00:58:49.26#ibcon#flushed, iclass 26, count 0 2006.202.00:58:49.26#ibcon#about to write, iclass 26, count 0 2006.202.00:58:49.26#ibcon#wrote, iclass 26, count 0 2006.202.00:58:49.26#ibcon#about to read 3, iclass 26, count 0 2006.202.00:58:49.30#ibcon#read 3, iclass 26, count 0 2006.202.00:58:49.30#ibcon#about to read 4, iclass 26, count 0 2006.202.00:58:49.30#ibcon#read 4, iclass 26, count 0 2006.202.00:58:49.30#ibcon#about to read 5, iclass 26, count 0 2006.202.00:58:49.30#ibcon#read 5, iclass 26, count 0 2006.202.00:58:49.30#ibcon#about to read 6, iclass 26, count 0 2006.202.00:58:49.30#ibcon#read 6, iclass 26, count 0 2006.202.00:58:49.30#ibcon#end of sib2, iclass 26, count 0 2006.202.00:58:49.30#ibcon#*after write, iclass 26, count 0 2006.202.00:58:49.30#ibcon#*before return 0, iclass 26, count 0 2006.202.00:58:49.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:49.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.00:58:49.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.00:58:49.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.00:58:49.30$vck44/vb=1,4 2006.202.00:58:49.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.00:58:49.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.00:58:49.30#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:49.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:49.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:49.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:49.30#ibcon#enter wrdev, iclass 28, count 2 2006.202.00:58:49.30#ibcon#first serial, iclass 28, count 2 2006.202.00:58:49.30#ibcon#enter sib2, iclass 28, count 2 2006.202.00:58:49.30#ibcon#flushed, iclass 28, count 2 2006.202.00:58:49.30#ibcon#about to write, iclass 28, count 2 2006.202.00:58:49.30#ibcon#wrote, iclass 28, count 2 2006.202.00:58:49.30#ibcon#about to read 3, iclass 28, count 2 2006.202.00:58:49.32#ibcon#read 3, iclass 28, count 2 2006.202.00:58:49.32#ibcon#about to read 4, iclass 28, count 2 2006.202.00:58:49.32#ibcon#read 4, iclass 28, count 2 2006.202.00:58:49.32#ibcon#about to read 5, iclass 28, count 2 2006.202.00:58:49.32#ibcon#read 5, iclass 28, count 2 2006.202.00:58:49.32#ibcon#about to read 6, iclass 28, count 2 2006.202.00:58:49.32#ibcon#read 6, iclass 28, count 2 2006.202.00:58:49.32#ibcon#end of sib2, iclass 28, count 2 2006.202.00:58:49.32#ibcon#*mode == 0, iclass 28, count 2 2006.202.00:58:49.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.00:58:49.32#ibcon#[27=AT01-04\r\n] 2006.202.00:58:49.32#ibcon#*before write, iclass 28, count 2 2006.202.00:58:49.32#ibcon#enter sib2, iclass 28, count 2 2006.202.00:58:49.32#ibcon#flushed, iclass 28, count 2 2006.202.00:58:49.32#ibcon#about to write, iclass 28, count 2 2006.202.00:58:49.32#ibcon#wrote, iclass 28, count 2 2006.202.00:58:49.32#ibcon#about to read 3, iclass 28, count 2 2006.202.00:58:49.35#ibcon#read 3, iclass 28, count 2 2006.202.00:58:49.35#ibcon#about to read 4, iclass 28, count 2 2006.202.00:58:49.35#ibcon#read 4, iclass 28, count 2 2006.202.00:58:49.35#ibcon#about to read 5, iclass 28, count 2 2006.202.00:58:49.35#ibcon#read 5, iclass 28, count 2 2006.202.00:58:49.35#ibcon#about to read 6, iclass 28, count 2 2006.202.00:58:49.35#ibcon#read 6, iclass 28, count 2 2006.202.00:58:49.35#ibcon#end of sib2, iclass 28, count 2 2006.202.00:58:49.35#ibcon#*after write, iclass 28, count 2 2006.202.00:58:49.35#ibcon#*before return 0, iclass 28, count 2 2006.202.00:58:49.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:49.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.00:58:49.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.00:58:49.35#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:49.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:49.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:49.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:49.47#ibcon#enter wrdev, iclass 28, count 0 2006.202.00:58:49.47#ibcon#first serial, iclass 28, count 0 2006.202.00:58:49.47#ibcon#enter sib2, iclass 28, count 0 2006.202.00:58:49.47#ibcon#flushed, iclass 28, count 0 2006.202.00:58:49.47#ibcon#about to write, iclass 28, count 0 2006.202.00:58:49.47#ibcon#wrote, iclass 28, count 0 2006.202.00:58:49.47#ibcon#about to read 3, iclass 28, count 0 2006.202.00:58:49.49#ibcon#read 3, iclass 28, count 0 2006.202.00:58:49.49#ibcon#about to read 4, iclass 28, count 0 2006.202.00:58:49.49#ibcon#read 4, iclass 28, count 0 2006.202.00:58:49.49#ibcon#about to read 5, iclass 28, count 0 2006.202.00:58:49.49#ibcon#read 5, iclass 28, count 0 2006.202.00:58:49.49#ibcon#about to read 6, iclass 28, count 0 2006.202.00:58:49.49#ibcon#read 6, iclass 28, count 0 2006.202.00:58:49.49#ibcon#end of sib2, iclass 28, count 0 2006.202.00:58:49.49#ibcon#*mode == 0, iclass 28, count 0 2006.202.00:58:49.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.00:58:49.49#ibcon#[27=USB\r\n] 2006.202.00:58:49.49#ibcon#*before write, iclass 28, count 0 2006.202.00:58:49.49#ibcon#enter sib2, iclass 28, count 0 2006.202.00:58:49.49#ibcon#flushed, iclass 28, count 0 2006.202.00:58:49.49#ibcon#about to write, iclass 28, count 0 2006.202.00:58:49.49#ibcon#wrote, iclass 28, count 0 2006.202.00:58:49.49#ibcon#about to read 3, iclass 28, count 0 2006.202.00:58:49.52#ibcon#read 3, iclass 28, count 0 2006.202.00:58:49.52#ibcon#about to read 4, iclass 28, count 0 2006.202.00:58:49.52#ibcon#read 4, iclass 28, count 0 2006.202.00:58:49.52#ibcon#about to read 5, iclass 28, count 0 2006.202.00:58:49.52#ibcon#read 5, iclass 28, count 0 2006.202.00:58:49.52#ibcon#about to read 6, iclass 28, count 0 2006.202.00:58:49.52#ibcon#read 6, iclass 28, count 0 2006.202.00:58:49.52#ibcon#end of sib2, iclass 28, count 0 2006.202.00:58:49.52#ibcon#*after write, iclass 28, count 0 2006.202.00:58:49.52#ibcon#*before return 0, iclass 28, count 0 2006.202.00:58:49.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:49.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.00:58:49.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.00:58:49.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.00:58:49.52$vck44/vblo=2,634.99 2006.202.00:58:49.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.00:58:49.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.00:58:49.52#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:49.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:49.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:49.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:49.52#ibcon#enter wrdev, iclass 30, count 0 2006.202.00:58:49.52#ibcon#first serial, iclass 30, count 0 2006.202.00:58:49.52#ibcon#enter sib2, iclass 30, count 0 2006.202.00:58:49.52#ibcon#flushed, iclass 30, count 0 2006.202.00:58:49.52#ibcon#about to write, iclass 30, count 0 2006.202.00:58:49.52#ibcon#wrote, iclass 30, count 0 2006.202.00:58:49.52#ibcon#about to read 3, iclass 30, count 0 2006.202.00:58:49.54#ibcon#read 3, iclass 30, count 0 2006.202.00:58:49.54#ibcon#about to read 4, iclass 30, count 0 2006.202.00:58:49.54#ibcon#read 4, iclass 30, count 0 2006.202.00:58:49.54#ibcon#about to read 5, iclass 30, count 0 2006.202.00:58:49.54#ibcon#read 5, iclass 30, count 0 2006.202.00:58:49.54#ibcon#about to read 6, iclass 30, count 0 2006.202.00:58:49.54#ibcon#read 6, iclass 30, count 0 2006.202.00:58:49.54#ibcon#end of sib2, iclass 30, count 0 2006.202.00:58:49.54#ibcon#*mode == 0, iclass 30, count 0 2006.202.00:58:49.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.00:58:49.54#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.00:58:49.54#ibcon#*before write, iclass 30, count 0 2006.202.00:58:49.54#ibcon#enter sib2, iclass 30, count 0 2006.202.00:58:49.54#ibcon#flushed, iclass 30, count 0 2006.202.00:58:49.54#ibcon#about to write, iclass 30, count 0 2006.202.00:58:49.54#ibcon#wrote, iclass 30, count 0 2006.202.00:58:49.54#ibcon#about to read 3, iclass 30, count 0 2006.202.00:58:49.58#ibcon#read 3, iclass 30, count 0 2006.202.00:58:49.58#ibcon#about to read 4, iclass 30, count 0 2006.202.00:58:49.58#ibcon#read 4, iclass 30, count 0 2006.202.00:58:49.58#ibcon#about to read 5, iclass 30, count 0 2006.202.00:58:49.58#ibcon#read 5, iclass 30, count 0 2006.202.00:58:49.58#ibcon#about to read 6, iclass 30, count 0 2006.202.00:58:49.58#ibcon#read 6, iclass 30, count 0 2006.202.00:58:49.58#ibcon#end of sib2, iclass 30, count 0 2006.202.00:58:49.58#ibcon#*after write, iclass 30, count 0 2006.202.00:58:49.58#ibcon#*before return 0, iclass 30, count 0 2006.202.00:58:49.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:49.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.00:58:49.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.00:58:49.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.00:58:49.58$vck44/vb=2,5 2006.202.00:58:49.58#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.00:58:49.58#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.00:58:49.58#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:49.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:49.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:49.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:49.64#ibcon#enter wrdev, iclass 32, count 2 2006.202.00:58:49.64#ibcon#first serial, iclass 32, count 2 2006.202.00:58:49.64#ibcon#enter sib2, iclass 32, count 2 2006.202.00:58:49.64#ibcon#flushed, iclass 32, count 2 2006.202.00:58:49.64#ibcon#about to write, iclass 32, count 2 2006.202.00:58:49.64#ibcon#wrote, iclass 32, count 2 2006.202.00:58:49.64#ibcon#about to read 3, iclass 32, count 2 2006.202.00:58:49.66#ibcon#read 3, iclass 32, count 2 2006.202.00:58:49.66#ibcon#about to read 4, iclass 32, count 2 2006.202.00:58:49.66#ibcon#read 4, iclass 32, count 2 2006.202.00:58:49.66#ibcon#about to read 5, iclass 32, count 2 2006.202.00:58:49.66#ibcon#read 5, iclass 32, count 2 2006.202.00:58:49.66#ibcon#about to read 6, iclass 32, count 2 2006.202.00:58:49.66#ibcon#read 6, iclass 32, count 2 2006.202.00:58:49.66#ibcon#end of sib2, iclass 32, count 2 2006.202.00:58:49.66#ibcon#*mode == 0, iclass 32, count 2 2006.202.00:58:49.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.00:58:49.66#ibcon#[27=AT02-05\r\n] 2006.202.00:58:49.66#ibcon#*before write, iclass 32, count 2 2006.202.00:58:49.66#ibcon#enter sib2, iclass 32, count 2 2006.202.00:58:49.66#ibcon#flushed, iclass 32, count 2 2006.202.00:58:49.66#ibcon#about to write, iclass 32, count 2 2006.202.00:58:49.66#ibcon#wrote, iclass 32, count 2 2006.202.00:58:49.66#ibcon#about to read 3, iclass 32, count 2 2006.202.00:58:49.69#ibcon#read 3, iclass 32, count 2 2006.202.00:58:49.69#ibcon#about to read 4, iclass 32, count 2 2006.202.00:58:49.69#ibcon#read 4, iclass 32, count 2 2006.202.00:58:49.69#ibcon#about to read 5, iclass 32, count 2 2006.202.00:58:49.69#ibcon#read 5, iclass 32, count 2 2006.202.00:58:49.69#ibcon#about to read 6, iclass 32, count 2 2006.202.00:58:49.69#ibcon#read 6, iclass 32, count 2 2006.202.00:58:49.69#ibcon#end of sib2, iclass 32, count 2 2006.202.00:58:49.69#ibcon#*after write, iclass 32, count 2 2006.202.00:58:49.69#ibcon#*before return 0, iclass 32, count 2 2006.202.00:58:49.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:49.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.00:58:49.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.00:58:49.69#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:49.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:49.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:49.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:49.81#ibcon#enter wrdev, iclass 32, count 0 2006.202.00:58:49.81#ibcon#first serial, iclass 32, count 0 2006.202.00:58:49.81#ibcon#enter sib2, iclass 32, count 0 2006.202.00:58:49.81#ibcon#flushed, iclass 32, count 0 2006.202.00:58:49.81#ibcon#about to write, iclass 32, count 0 2006.202.00:58:49.81#ibcon#wrote, iclass 32, count 0 2006.202.00:58:49.81#ibcon#about to read 3, iclass 32, count 0 2006.202.00:58:49.83#ibcon#read 3, iclass 32, count 0 2006.202.00:58:49.83#ibcon#about to read 4, iclass 32, count 0 2006.202.00:58:49.83#ibcon#read 4, iclass 32, count 0 2006.202.00:58:49.83#ibcon#about to read 5, iclass 32, count 0 2006.202.00:58:49.83#ibcon#read 5, iclass 32, count 0 2006.202.00:58:49.83#ibcon#about to read 6, iclass 32, count 0 2006.202.00:58:49.83#ibcon#read 6, iclass 32, count 0 2006.202.00:58:49.83#ibcon#end of sib2, iclass 32, count 0 2006.202.00:58:49.83#ibcon#*mode == 0, iclass 32, count 0 2006.202.00:58:49.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.00:58:49.83#ibcon#[27=USB\r\n] 2006.202.00:58:49.83#ibcon#*before write, iclass 32, count 0 2006.202.00:58:49.83#ibcon#enter sib2, iclass 32, count 0 2006.202.00:58:49.83#ibcon#flushed, iclass 32, count 0 2006.202.00:58:49.83#ibcon#about to write, iclass 32, count 0 2006.202.00:58:49.83#ibcon#wrote, iclass 32, count 0 2006.202.00:58:49.83#ibcon#about to read 3, iclass 32, count 0 2006.202.00:58:49.86#ibcon#read 3, iclass 32, count 0 2006.202.00:58:49.86#ibcon#about to read 4, iclass 32, count 0 2006.202.00:58:49.86#ibcon#read 4, iclass 32, count 0 2006.202.00:58:49.86#ibcon#about to read 5, iclass 32, count 0 2006.202.00:58:49.86#ibcon#read 5, iclass 32, count 0 2006.202.00:58:49.86#ibcon#about to read 6, iclass 32, count 0 2006.202.00:58:49.86#ibcon#read 6, iclass 32, count 0 2006.202.00:58:49.86#ibcon#end of sib2, iclass 32, count 0 2006.202.00:58:49.86#ibcon#*after write, iclass 32, count 0 2006.202.00:58:49.86#ibcon#*before return 0, iclass 32, count 0 2006.202.00:58:49.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:49.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.00:58:49.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.00:58:49.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.00:58:49.86$vck44/vblo=3,649.99 2006.202.00:58:49.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.00:58:49.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.00:58:49.86#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:49.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:49.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:49.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:49.86#ibcon#enter wrdev, iclass 34, count 0 2006.202.00:58:49.86#ibcon#first serial, iclass 34, count 0 2006.202.00:58:49.86#ibcon#enter sib2, iclass 34, count 0 2006.202.00:58:49.86#ibcon#flushed, iclass 34, count 0 2006.202.00:58:49.86#ibcon#about to write, iclass 34, count 0 2006.202.00:58:49.86#ibcon#wrote, iclass 34, count 0 2006.202.00:58:49.86#ibcon#about to read 3, iclass 34, count 0 2006.202.00:58:49.88#ibcon#read 3, iclass 34, count 0 2006.202.00:58:49.88#ibcon#about to read 4, iclass 34, count 0 2006.202.00:58:49.88#ibcon#read 4, iclass 34, count 0 2006.202.00:58:49.88#ibcon#about to read 5, iclass 34, count 0 2006.202.00:58:49.88#ibcon#read 5, iclass 34, count 0 2006.202.00:58:49.88#ibcon#about to read 6, iclass 34, count 0 2006.202.00:58:49.88#ibcon#read 6, iclass 34, count 0 2006.202.00:58:49.88#ibcon#end of sib2, iclass 34, count 0 2006.202.00:58:49.88#ibcon#*mode == 0, iclass 34, count 0 2006.202.00:58:49.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.00:58:49.88#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.00:58:49.88#ibcon#*before write, iclass 34, count 0 2006.202.00:58:49.88#ibcon#enter sib2, iclass 34, count 0 2006.202.00:58:49.88#ibcon#flushed, iclass 34, count 0 2006.202.00:58:49.88#ibcon#about to write, iclass 34, count 0 2006.202.00:58:49.88#ibcon#wrote, iclass 34, count 0 2006.202.00:58:49.88#ibcon#about to read 3, iclass 34, count 0 2006.202.00:58:49.92#ibcon#read 3, iclass 34, count 0 2006.202.00:58:49.92#ibcon#about to read 4, iclass 34, count 0 2006.202.00:58:49.92#ibcon#read 4, iclass 34, count 0 2006.202.00:58:49.92#ibcon#about to read 5, iclass 34, count 0 2006.202.00:58:49.92#ibcon#read 5, iclass 34, count 0 2006.202.00:58:49.92#ibcon#about to read 6, iclass 34, count 0 2006.202.00:58:49.92#ibcon#read 6, iclass 34, count 0 2006.202.00:58:49.92#ibcon#end of sib2, iclass 34, count 0 2006.202.00:58:49.92#ibcon#*after write, iclass 34, count 0 2006.202.00:58:49.92#ibcon#*before return 0, iclass 34, count 0 2006.202.00:58:49.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:49.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.00:58:49.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.00:58:49.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.00:58:49.92$vck44/vb=3,4 2006.202.00:58:49.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.00:58:49.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.00:58:49.92#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:49.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:49.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:49.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:49.98#ibcon#enter wrdev, iclass 36, count 2 2006.202.00:58:49.98#ibcon#first serial, iclass 36, count 2 2006.202.00:58:49.98#ibcon#enter sib2, iclass 36, count 2 2006.202.00:58:49.98#ibcon#flushed, iclass 36, count 2 2006.202.00:58:49.98#ibcon#about to write, iclass 36, count 2 2006.202.00:58:49.98#ibcon#wrote, iclass 36, count 2 2006.202.00:58:49.98#ibcon#about to read 3, iclass 36, count 2 2006.202.00:58:50.00#ibcon#read 3, iclass 36, count 2 2006.202.00:58:50.00#ibcon#about to read 4, iclass 36, count 2 2006.202.00:58:50.00#ibcon#read 4, iclass 36, count 2 2006.202.00:58:50.00#ibcon#about to read 5, iclass 36, count 2 2006.202.00:58:50.00#ibcon#read 5, iclass 36, count 2 2006.202.00:58:50.00#ibcon#about to read 6, iclass 36, count 2 2006.202.00:58:50.00#ibcon#read 6, iclass 36, count 2 2006.202.00:58:50.00#ibcon#end of sib2, iclass 36, count 2 2006.202.00:58:50.00#ibcon#*mode == 0, iclass 36, count 2 2006.202.00:58:50.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.00:58:50.00#ibcon#[27=AT03-04\r\n] 2006.202.00:58:50.00#ibcon#*before write, iclass 36, count 2 2006.202.00:58:50.00#ibcon#enter sib2, iclass 36, count 2 2006.202.00:58:50.00#ibcon#flushed, iclass 36, count 2 2006.202.00:58:50.00#ibcon#about to write, iclass 36, count 2 2006.202.00:58:50.00#ibcon#wrote, iclass 36, count 2 2006.202.00:58:50.00#ibcon#about to read 3, iclass 36, count 2 2006.202.00:58:50.03#ibcon#read 3, iclass 36, count 2 2006.202.00:58:50.03#ibcon#about to read 4, iclass 36, count 2 2006.202.00:58:50.03#ibcon#read 4, iclass 36, count 2 2006.202.00:58:50.03#ibcon#about to read 5, iclass 36, count 2 2006.202.00:58:50.03#ibcon#read 5, iclass 36, count 2 2006.202.00:58:50.03#ibcon#about to read 6, iclass 36, count 2 2006.202.00:58:50.03#ibcon#read 6, iclass 36, count 2 2006.202.00:58:50.03#ibcon#end of sib2, iclass 36, count 2 2006.202.00:58:50.03#ibcon#*after write, iclass 36, count 2 2006.202.00:58:50.03#ibcon#*before return 0, iclass 36, count 2 2006.202.00:58:50.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:50.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.00:58:50.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.00:58:50.03#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:50.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:50.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:50.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:50.15#ibcon#enter wrdev, iclass 36, count 0 2006.202.00:58:50.15#ibcon#first serial, iclass 36, count 0 2006.202.00:58:50.15#ibcon#enter sib2, iclass 36, count 0 2006.202.00:58:50.15#ibcon#flushed, iclass 36, count 0 2006.202.00:58:50.15#ibcon#about to write, iclass 36, count 0 2006.202.00:58:50.15#ibcon#wrote, iclass 36, count 0 2006.202.00:58:50.15#ibcon#about to read 3, iclass 36, count 0 2006.202.00:58:50.17#ibcon#read 3, iclass 36, count 0 2006.202.00:58:50.17#ibcon#about to read 4, iclass 36, count 0 2006.202.00:58:50.17#ibcon#read 4, iclass 36, count 0 2006.202.00:58:50.17#ibcon#about to read 5, iclass 36, count 0 2006.202.00:58:50.17#ibcon#read 5, iclass 36, count 0 2006.202.00:58:50.17#ibcon#about to read 6, iclass 36, count 0 2006.202.00:58:50.17#ibcon#read 6, iclass 36, count 0 2006.202.00:58:50.17#ibcon#end of sib2, iclass 36, count 0 2006.202.00:58:50.17#ibcon#*mode == 0, iclass 36, count 0 2006.202.00:58:50.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.00:58:50.17#ibcon#[27=USB\r\n] 2006.202.00:58:50.17#ibcon#*before write, iclass 36, count 0 2006.202.00:58:50.17#ibcon#enter sib2, iclass 36, count 0 2006.202.00:58:50.17#ibcon#flushed, iclass 36, count 0 2006.202.00:58:50.17#ibcon#about to write, iclass 36, count 0 2006.202.00:58:50.17#ibcon#wrote, iclass 36, count 0 2006.202.00:58:50.17#ibcon#about to read 3, iclass 36, count 0 2006.202.00:58:50.20#ibcon#read 3, iclass 36, count 0 2006.202.00:58:50.20#ibcon#about to read 4, iclass 36, count 0 2006.202.00:58:50.20#ibcon#read 4, iclass 36, count 0 2006.202.00:58:50.20#ibcon#about to read 5, iclass 36, count 0 2006.202.00:58:50.20#ibcon#read 5, iclass 36, count 0 2006.202.00:58:50.20#ibcon#about to read 6, iclass 36, count 0 2006.202.00:58:50.20#ibcon#read 6, iclass 36, count 0 2006.202.00:58:50.20#ibcon#end of sib2, iclass 36, count 0 2006.202.00:58:50.20#ibcon#*after write, iclass 36, count 0 2006.202.00:58:50.20#ibcon#*before return 0, iclass 36, count 0 2006.202.00:58:50.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:50.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.00:58:50.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.00:58:50.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.00:58:50.20$vck44/vblo=4,679.99 2006.202.00:58:50.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.00:58:50.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.00:58:50.20#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:50.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:50.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:50.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:50.20#ibcon#enter wrdev, iclass 38, count 0 2006.202.00:58:50.20#ibcon#first serial, iclass 38, count 0 2006.202.00:58:50.20#ibcon#enter sib2, iclass 38, count 0 2006.202.00:58:50.20#ibcon#flushed, iclass 38, count 0 2006.202.00:58:50.20#ibcon#about to write, iclass 38, count 0 2006.202.00:58:50.20#ibcon#wrote, iclass 38, count 0 2006.202.00:58:50.20#ibcon#about to read 3, iclass 38, count 0 2006.202.00:58:50.22#ibcon#read 3, iclass 38, count 0 2006.202.00:58:50.22#ibcon#about to read 4, iclass 38, count 0 2006.202.00:58:50.22#ibcon#read 4, iclass 38, count 0 2006.202.00:58:50.22#ibcon#about to read 5, iclass 38, count 0 2006.202.00:58:50.22#ibcon#read 5, iclass 38, count 0 2006.202.00:58:50.22#ibcon#about to read 6, iclass 38, count 0 2006.202.00:58:50.22#ibcon#read 6, iclass 38, count 0 2006.202.00:58:50.22#ibcon#end of sib2, iclass 38, count 0 2006.202.00:58:50.22#ibcon#*mode == 0, iclass 38, count 0 2006.202.00:58:50.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.00:58:50.22#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.00:58:50.22#ibcon#*before write, iclass 38, count 0 2006.202.00:58:50.22#ibcon#enter sib2, iclass 38, count 0 2006.202.00:58:50.22#ibcon#flushed, iclass 38, count 0 2006.202.00:58:50.22#ibcon#about to write, iclass 38, count 0 2006.202.00:58:50.22#ibcon#wrote, iclass 38, count 0 2006.202.00:58:50.22#ibcon#about to read 3, iclass 38, count 0 2006.202.00:58:50.26#ibcon#read 3, iclass 38, count 0 2006.202.00:58:50.26#ibcon#about to read 4, iclass 38, count 0 2006.202.00:58:50.26#ibcon#read 4, iclass 38, count 0 2006.202.00:58:50.26#ibcon#about to read 5, iclass 38, count 0 2006.202.00:58:50.26#ibcon#read 5, iclass 38, count 0 2006.202.00:58:50.26#ibcon#about to read 6, iclass 38, count 0 2006.202.00:58:50.26#ibcon#read 6, iclass 38, count 0 2006.202.00:58:50.26#ibcon#end of sib2, iclass 38, count 0 2006.202.00:58:50.26#ibcon#*after write, iclass 38, count 0 2006.202.00:58:50.26#ibcon#*before return 0, iclass 38, count 0 2006.202.00:58:50.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:50.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.00:58:50.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.00:58:50.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.00:58:50.26$vck44/vb=4,5 2006.202.00:58:50.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.202.00:58:50.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.202.00:58:50.26#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:50.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:50.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:50.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:50.32#ibcon#enter wrdev, iclass 40, count 2 2006.202.00:58:50.32#ibcon#first serial, iclass 40, count 2 2006.202.00:58:50.32#ibcon#enter sib2, iclass 40, count 2 2006.202.00:58:50.32#ibcon#flushed, iclass 40, count 2 2006.202.00:58:50.32#ibcon#about to write, iclass 40, count 2 2006.202.00:58:50.32#ibcon#wrote, iclass 40, count 2 2006.202.00:58:50.32#ibcon#about to read 3, iclass 40, count 2 2006.202.00:58:50.34#ibcon#read 3, iclass 40, count 2 2006.202.00:58:50.34#ibcon#about to read 4, iclass 40, count 2 2006.202.00:58:50.34#ibcon#read 4, iclass 40, count 2 2006.202.00:58:50.34#ibcon#about to read 5, iclass 40, count 2 2006.202.00:58:50.34#ibcon#read 5, iclass 40, count 2 2006.202.00:58:50.34#ibcon#about to read 6, iclass 40, count 2 2006.202.00:58:50.34#ibcon#read 6, iclass 40, count 2 2006.202.00:58:50.34#ibcon#end of sib2, iclass 40, count 2 2006.202.00:58:50.34#ibcon#*mode == 0, iclass 40, count 2 2006.202.00:58:50.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.202.00:58:50.34#ibcon#[27=AT04-05\r\n] 2006.202.00:58:50.34#ibcon#*before write, iclass 40, count 2 2006.202.00:58:50.34#ibcon#enter sib2, iclass 40, count 2 2006.202.00:58:50.34#ibcon#flushed, iclass 40, count 2 2006.202.00:58:50.34#ibcon#about to write, iclass 40, count 2 2006.202.00:58:50.34#ibcon#wrote, iclass 40, count 2 2006.202.00:58:50.34#ibcon#about to read 3, iclass 40, count 2 2006.202.00:58:50.37#ibcon#read 3, iclass 40, count 2 2006.202.00:58:50.37#ibcon#about to read 4, iclass 40, count 2 2006.202.00:58:50.37#ibcon#read 4, iclass 40, count 2 2006.202.00:58:50.37#ibcon#about to read 5, iclass 40, count 2 2006.202.00:58:50.37#ibcon#read 5, iclass 40, count 2 2006.202.00:58:50.37#ibcon#about to read 6, iclass 40, count 2 2006.202.00:58:50.37#ibcon#read 6, iclass 40, count 2 2006.202.00:58:50.37#ibcon#end of sib2, iclass 40, count 2 2006.202.00:58:50.37#ibcon#*after write, iclass 40, count 2 2006.202.00:58:50.37#ibcon#*before return 0, iclass 40, count 2 2006.202.00:58:50.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:50.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.202.00:58:50.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.202.00:58:50.37#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:50.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:50.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:50.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:50.49#ibcon#enter wrdev, iclass 40, count 0 2006.202.00:58:50.49#ibcon#first serial, iclass 40, count 0 2006.202.00:58:50.49#ibcon#enter sib2, iclass 40, count 0 2006.202.00:58:50.49#ibcon#flushed, iclass 40, count 0 2006.202.00:58:50.49#ibcon#about to write, iclass 40, count 0 2006.202.00:58:50.49#ibcon#wrote, iclass 40, count 0 2006.202.00:58:50.49#ibcon#about to read 3, iclass 40, count 0 2006.202.00:58:50.51#ibcon#read 3, iclass 40, count 0 2006.202.00:58:50.51#ibcon#about to read 4, iclass 40, count 0 2006.202.00:58:50.51#ibcon#read 4, iclass 40, count 0 2006.202.00:58:50.51#ibcon#about to read 5, iclass 40, count 0 2006.202.00:58:50.51#ibcon#read 5, iclass 40, count 0 2006.202.00:58:50.51#ibcon#about to read 6, iclass 40, count 0 2006.202.00:58:50.51#ibcon#read 6, iclass 40, count 0 2006.202.00:58:50.51#ibcon#end of sib2, iclass 40, count 0 2006.202.00:58:50.51#ibcon#*mode == 0, iclass 40, count 0 2006.202.00:58:50.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.00:58:50.51#ibcon#[27=USB\r\n] 2006.202.00:58:50.51#ibcon#*before write, iclass 40, count 0 2006.202.00:58:50.51#ibcon#enter sib2, iclass 40, count 0 2006.202.00:58:50.51#ibcon#flushed, iclass 40, count 0 2006.202.00:58:50.51#ibcon#about to write, iclass 40, count 0 2006.202.00:58:50.51#ibcon#wrote, iclass 40, count 0 2006.202.00:58:50.51#ibcon#about to read 3, iclass 40, count 0 2006.202.00:58:50.54#ibcon#read 3, iclass 40, count 0 2006.202.00:58:50.54#ibcon#about to read 4, iclass 40, count 0 2006.202.00:58:50.54#ibcon#read 4, iclass 40, count 0 2006.202.00:58:50.54#ibcon#about to read 5, iclass 40, count 0 2006.202.00:58:50.54#ibcon#read 5, iclass 40, count 0 2006.202.00:58:50.54#ibcon#about to read 6, iclass 40, count 0 2006.202.00:58:50.54#ibcon#read 6, iclass 40, count 0 2006.202.00:58:50.54#ibcon#end of sib2, iclass 40, count 0 2006.202.00:58:50.54#ibcon#*after write, iclass 40, count 0 2006.202.00:58:50.54#ibcon#*before return 0, iclass 40, count 0 2006.202.00:58:50.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:50.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.202.00:58:50.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.00:58:50.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.00:58:50.54$vck44/vblo=5,709.99 2006.202.00:58:50.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.00:58:50.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.00:58:50.54#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:50.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:50.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:50.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:50.54#ibcon#enter wrdev, iclass 4, count 0 2006.202.00:58:50.54#ibcon#first serial, iclass 4, count 0 2006.202.00:58:50.54#ibcon#enter sib2, iclass 4, count 0 2006.202.00:58:50.54#ibcon#flushed, iclass 4, count 0 2006.202.00:58:50.54#ibcon#about to write, iclass 4, count 0 2006.202.00:58:50.54#ibcon#wrote, iclass 4, count 0 2006.202.00:58:50.54#ibcon#about to read 3, iclass 4, count 0 2006.202.00:58:50.56#ibcon#read 3, iclass 4, count 0 2006.202.00:58:50.56#ibcon#about to read 4, iclass 4, count 0 2006.202.00:58:50.56#ibcon#read 4, iclass 4, count 0 2006.202.00:58:50.56#ibcon#about to read 5, iclass 4, count 0 2006.202.00:58:50.56#ibcon#read 5, iclass 4, count 0 2006.202.00:58:50.56#ibcon#about to read 6, iclass 4, count 0 2006.202.00:58:50.56#ibcon#read 6, iclass 4, count 0 2006.202.00:58:50.56#ibcon#end of sib2, iclass 4, count 0 2006.202.00:58:50.56#ibcon#*mode == 0, iclass 4, count 0 2006.202.00:58:50.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.00:58:50.56#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.00:58:50.56#ibcon#*before write, iclass 4, count 0 2006.202.00:58:50.56#ibcon#enter sib2, iclass 4, count 0 2006.202.00:58:50.56#ibcon#flushed, iclass 4, count 0 2006.202.00:58:50.56#ibcon#about to write, iclass 4, count 0 2006.202.00:58:50.56#ibcon#wrote, iclass 4, count 0 2006.202.00:58:50.56#ibcon#about to read 3, iclass 4, count 0 2006.202.00:58:50.60#ibcon#read 3, iclass 4, count 0 2006.202.00:58:50.60#ibcon#about to read 4, iclass 4, count 0 2006.202.00:58:50.60#ibcon#read 4, iclass 4, count 0 2006.202.00:58:50.60#ibcon#about to read 5, iclass 4, count 0 2006.202.00:58:50.60#ibcon#read 5, iclass 4, count 0 2006.202.00:58:50.60#ibcon#about to read 6, iclass 4, count 0 2006.202.00:58:50.60#ibcon#read 6, iclass 4, count 0 2006.202.00:58:50.60#ibcon#end of sib2, iclass 4, count 0 2006.202.00:58:50.60#ibcon#*after write, iclass 4, count 0 2006.202.00:58:50.60#ibcon#*before return 0, iclass 4, count 0 2006.202.00:58:50.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:50.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.00:58:50.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.00:58:50.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.00:58:50.60$vck44/vb=5,4 2006.202.00:58:50.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.202.00:58:50.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.202.00:58:50.60#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:50.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:50.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:50.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:50.66#ibcon#enter wrdev, iclass 6, count 2 2006.202.00:58:50.66#ibcon#first serial, iclass 6, count 2 2006.202.00:58:50.66#ibcon#enter sib2, iclass 6, count 2 2006.202.00:58:50.66#ibcon#flushed, iclass 6, count 2 2006.202.00:58:50.66#ibcon#about to write, iclass 6, count 2 2006.202.00:58:50.66#ibcon#wrote, iclass 6, count 2 2006.202.00:58:50.66#ibcon#about to read 3, iclass 6, count 2 2006.202.00:58:50.68#ibcon#read 3, iclass 6, count 2 2006.202.00:58:50.68#ibcon#about to read 4, iclass 6, count 2 2006.202.00:58:50.68#ibcon#read 4, iclass 6, count 2 2006.202.00:58:50.68#ibcon#about to read 5, iclass 6, count 2 2006.202.00:58:50.68#ibcon#read 5, iclass 6, count 2 2006.202.00:58:50.68#ibcon#about to read 6, iclass 6, count 2 2006.202.00:58:50.68#ibcon#read 6, iclass 6, count 2 2006.202.00:58:50.68#ibcon#end of sib2, iclass 6, count 2 2006.202.00:58:50.68#ibcon#*mode == 0, iclass 6, count 2 2006.202.00:58:50.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.202.00:58:50.68#ibcon#[27=AT05-04\r\n] 2006.202.00:58:50.68#ibcon#*before write, iclass 6, count 2 2006.202.00:58:50.68#ibcon#enter sib2, iclass 6, count 2 2006.202.00:58:50.68#ibcon#flushed, iclass 6, count 2 2006.202.00:58:50.68#ibcon#about to write, iclass 6, count 2 2006.202.00:58:50.68#ibcon#wrote, iclass 6, count 2 2006.202.00:58:50.68#ibcon#about to read 3, iclass 6, count 2 2006.202.00:58:50.71#ibcon#read 3, iclass 6, count 2 2006.202.00:58:50.71#ibcon#about to read 4, iclass 6, count 2 2006.202.00:58:50.71#ibcon#read 4, iclass 6, count 2 2006.202.00:58:50.71#ibcon#about to read 5, iclass 6, count 2 2006.202.00:58:50.71#ibcon#read 5, iclass 6, count 2 2006.202.00:58:50.71#ibcon#about to read 6, iclass 6, count 2 2006.202.00:58:50.71#ibcon#read 6, iclass 6, count 2 2006.202.00:58:50.71#ibcon#end of sib2, iclass 6, count 2 2006.202.00:58:50.71#ibcon#*after write, iclass 6, count 2 2006.202.00:58:50.71#ibcon#*before return 0, iclass 6, count 2 2006.202.00:58:50.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:50.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.202.00:58:50.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.202.00:58:50.71#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:50.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:50.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:50.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:50.83#ibcon#enter wrdev, iclass 6, count 0 2006.202.00:58:50.83#ibcon#first serial, iclass 6, count 0 2006.202.00:58:50.83#ibcon#enter sib2, iclass 6, count 0 2006.202.00:58:50.83#ibcon#flushed, iclass 6, count 0 2006.202.00:58:50.83#ibcon#about to write, iclass 6, count 0 2006.202.00:58:50.83#ibcon#wrote, iclass 6, count 0 2006.202.00:58:50.83#ibcon#about to read 3, iclass 6, count 0 2006.202.00:58:50.85#ibcon#read 3, iclass 6, count 0 2006.202.00:58:50.85#ibcon#about to read 4, iclass 6, count 0 2006.202.00:58:50.85#ibcon#read 4, iclass 6, count 0 2006.202.00:58:50.85#ibcon#about to read 5, iclass 6, count 0 2006.202.00:58:50.85#ibcon#read 5, iclass 6, count 0 2006.202.00:58:50.85#ibcon#about to read 6, iclass 6, count 0 2006.202.00:58:50.85#ibcon#read 6, iclass 6, count 0 2006.202.00:58:50.85#ibcon#end of sib2, iclass 6, count 0 2006.202.00:58:50.85#ibcon#*mode == 0, iclass 6, count 0 2006.202.00:58:50.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.00:58:50.85#ibcon#[27=USB\r\n] 2006.202.00:58:50.85#ibcon#*before write, iclass 6, count 0 2006.202.00:58:50.85#ibcon#enter sib2, iclass 6, count 0 2006.202.00:58:50.85#ibcon#flushed, iclass 6, count 0 2006.202.00:58:50.85#ibcon#about to write, iclass 6, count 0 2006.202.00:58:50.85#ibcon#wrote, iclass 6, count 0 2006.202.00:58:50.85#ibcon#about to read 3, iclass 6, count 0 2006.202.00:58:50.88#ibcon#read 3, iclass 6, count 0 2006.202.00:58:50.88#ibcon#about to read 4, iclass 6, count 0 2006.202.00:58:50.88#ibcon#read 4, iclass 6, count 0 2006.202.00:58:50.88#ibcon#about to read 5, iclass 6, count 0 2006.202.00:58:50.88#ibcon#read 5, iclass 6, count 0 2006.202.00:58:50.88#ibcon#about to read 6, iclass 6, count 0 2006.202.00:58:50.88#ibcon#read 6, iclass 6, count 0 2006.202.00:58:50.88#ibcon#end of sib2, iclass 6, count 0 2006.202.00:58:50.88#ibcon#*after write, iclass 6, count 0 2006.202.00:58:50.88#ibcon#*before return 0, iclass 6, count 0 2006.202.00:58:50.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:50.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.202.00:58:50.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.00:58:50.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.00:58:50.88$vck44/vblo=6,719.99 2006.202.00:58:50.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.00:58:50.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.00:58:50.88#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:50.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:50.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:50.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:50.88#ibcon#enter wrdev, iclass 10, count 0 2006.202.00:58:50.88#ibcon#first serial, iclass 10, count 0 2006.202.00:58:50.88#ibcon#enter sib2, iclass 10, count 0 2006.202.00:58:50.88#ibcon#flushed, iclass 10, count 0 2006.202.00:58:50.88#ibcon#about to write, iclass 10, count 0 2006.202.00:58:50.88#ibcon#wrote, iclass 10, count 0 2006.202.00:58:50.88#ibcon#about to read 3, iclass 10, count 0 2006.202.00:58:50.90#ibcon#read 3, iclass 10, count 0 2006.202.00:58:50.90#ibcon#about to read 4, iclass 10, count 0 2006.202.00:58:50.90#ibcon#read 4, iclass 10, count 0 2006.202.00:58:50.90#ibcon#about to read 5, iclass 10, count 0 2006.202.00:58:50.90#ibcon#read 5, iclass 10, count 0 2006.202.00:58:50.90#ibcon#about to read 6, iclass 10, count 0 2006.202.00:58:50.90#ibcon#read 6, iclass 10, count 0 2006.202.00:58:50.90#ibcon#end of sib2, iclass 10, count 0 2006.202.00:58:50.90#ibcon#*mode == 0, iclass 10, count 0 2006.202.00:58:50.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.00:58:50.90#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.00:58:50.90#ibcon#*before write, iclass 10, count 0 2006.202.00:58:50.90#ibcon#enter sib2, iclass 10, count 0 2006.202.00:58:50.90#ibcon#flushed, iclass 10, count 0 2006.202.00:58:50.90#ibcon#about to write, iclass 10, count 0 2006.202.00:58:50.90#ibcon#wrote, iclass 10, count 0 2006.202.00:58:50.90#ibcon#about to read 3, iclass 10, count 0 2006.202.00:58:50.94#ibcon#read 3, iclass 10, count 0 2006.202.00:58:50.94#ibcon#about to read 4, iclass 10, count 0 2006.202.00:58:50.94#ibcon#read 4, iclass 10, count 0 2006.202.00:58:50.94#ibcon#about to read 5, iclass 10, count 0 2006.202.00:58:50.94#ibcon#read 5, iclass 10, count 0 2006.202.00:58:50.94#ibcon#about to read 6, iclass 10, count 0 2006.202.00:58:50.94#ibcon#read 6, iclass 10, count 0 2006.202.00:58:50.94#ibcon#end of sib2, iclass 10, count 0 2006.202.00:58:50.94#ibcon#*after write, iclass 10, count 0 2006.202.00:58:50.94#ibcon#*before return 0, iclass 10, count 0 2006.202.00:58:50.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:50.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.00:58:50.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.00:58:50.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.00:58:50.94$vck44/vb=6,4 2006.202.00:58:50.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.202.00:58:50.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.202.00:58:50.94#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:50.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:51.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:51.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:51.00#ibcon#enter wrdev, iclass 12, count 2 2006.202.00:58:51.00#ibcon#first serial, iclass 12, count 2 2006.202.00:58:51.00#ibcon#enter sib2, iclass 12, count 2 2006.202.00:58:51.00#ibcon#flushed, iclass 12, count 2 2006.202.00:58:51.00#ibcon#about to write, iclass 12, count 2 2006.202.00:58:51.00#ibcon#wrote, iclass 12, count 2 2006.202.00:58:51.00#ibcon#about to read 3, iclass 12, count 2 2006.202.00:58:51.02#ibcon#read 3, iclass 12, count 2 2006.202.00:58:51.02#ibcon#about to read 4, iclass 12, count 2 2006.202.00:58:51.02#ibcon#read 4, iclass 12, count 2 2006.202.00:58:51.02#ibcon#about to read 5, iclass 12, count 2 2006.202.00:58:51.02#ibcon#read 5, iclass 12, count 2 2006.202.00:58:51.02#ibcon#about to read 6, iclass 12, count 2 2006.202.00:58:51.02#ibcon#read 6, iclass 12, count 2 2006.202.00:58:51.02#ibcon#end of sib2, iclass 12, count 2 2006.202.00:58:51.02#ibcon#*mode == 0, iclass 12, count 2 2006.202.00:58:51.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.202.00:58:51.02#ibcon#[27=AT06-04\r\n] 2006.202.00:58:51.02#ibcon#*before write, iclass 12, count 2 2006.202.00:58:51.02#ibcon#enter sib2, iclass 12, count 2 2006.202.00:58:51.02#ibcon#flushed, iclass 12, count 2 2006.202.00:58:51.02#ibcon#about to write, iclass 12, count 2 2006.202.00:58:51.02#ibcon#wrote, iclass 12, count 2 2006.202.00:58:51.02#ibcon#about to read 3, iclass 12, count 2 2006.202.00:58:51.05#ibcon#read 3, iclass 12, count 2 2006.202.00:58:51.05#ibcon#about to read 4, iclass 12, count 2 2006.202.00:58:51.10#ibcon#read 4, iclass 12, count 2 2006.202.00:58:51.10#ibcon#about to read 5, iclass 12, count 2 2006.202.00:58:51.10#ibcon#read 5, iclass 12, count 2 2006.202.00:58:51.10#ibcon#about to read 6, iclass 12, count 2 2006.202.00:58:51.10#ibcon#read 6, iclass 12, count 2 2006.202.00:58:51.10#ibcon#end of sib2, iclass 12, count 2 2006.202.00:58:51.10#ibcon#*after write, iclass 12, count 2 2006.202.00:58:51.10#ibcon#*before return 0, iclass 12, count 2 2006.202.00:58:51.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:51.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.202.00:58:51.10#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.202.00:58:51.10#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:51.10#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:51.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:51.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:51.22#ibcon#enter wrdev, iclass 12, count 0 2006.202.00:58:51.22#ibcon#first serial, iclass 12, count 0 2006.202.00:58:51.22#ibcon#enter sib2, iclass 12, count 0 2006.202.00:58:51.22#ibcon#flushed, iclass 12, count 0 2006.202.00:58:51.22#ibcon#about to write, iclass 12, count 0 2006.202.00:58:51.22#ibcon#wrote, iclass 12, count 0 2006.202.00:58:51.22#ibcon#about to read 3, iclass 12, count 0 2006.202.00:58:51.24#ibcon#read 3, iclass 12, count 0 2006.202.00:58:51.24#ibcon#about to read 4, iclass 12, count 0 2006.202.00:58:51.24#ibcon#read 4, iclass 12, count 0 2006.202.00:58:51.24#ibcon#about to read 5, iclass 12, count 0 2006.202.00:58:51.24#ibcon#read 5, iclass 12, count 0 2006.202.00:58:51.24#ibcon#about to read 6, iclass 12, count 0 2006.202.00:58:51.24#ibcon#read 6, iclass 12, count 0 2006.202.00:58:51.24#ibcon#end of sib2, iclass 12, count 0 2006.202.00:58:51.24#ibcon#*mode == 0, iclass 12, count 0 2006.202.00:58:51.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.00:58:51.24#ibcon#[27=USB\r\n] 2006.202.00:58:51.24#ibcon#*before write, iclass 12, count 0 2006.202.00:58:51.24#ibcon#enter sib2, iclass 12, count 0 2006.202.00:58:51.24#ibcon#flushed, iclass 12, count 0 2006.202.00:58:51.24#ibcon#about to write, iclass 12, count 0 2006.202.00:58:51.24#ibcon#wrote, iclass 12, count 0 2006.202.00:58:51.24#ibcon#about to read 3, iclass 12, count 0 2006.202.00:58:51.27#ibcon#read 3, iclass 12, count 0 2006.202.00:58:51.27#ibcon#about to read 4, iclass 12, count 0 2006.202.00:58:51.27#ibcon#read 4, iclass 12, count 0 2006.202.00:58:51.27#ibcon#about to read 5, iclass 12, count 0 2006.202.00:58:51.27#ibcon#read 5, iclass 12, count 0 2006.202.00:58:51.27#ibcon#about to read 6, iclass 12, count 0 2006.202.00:58:51.27#ibcon#read 6, iclass 12, count 0 2006.202.00:58:51.27#ibcon#end of sib2, iclass 12, count 0 2006.202.00:58:51.27#ibcon#*after write, iclass 12, count 0 2006.202.00:58:51.27#ibcon#*before return 0, iclass 12, count 0 2006.202.00:58:51.27#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:51.27#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.202.00:58:51.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.00:58:51.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.00:58:51.27$vck44/vblo=7,734.99 2006.202.00:58:51.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.00:58:51.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.00:58:51.27#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:51.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:51.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:51.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:51.27#ibcon#enter wrdev, iclass 14, count 0 2006.202.00:58:51.27#ibcon#first serial, iclass 14, count 0 2006.202.00:58:51.27#ibcon#enter sib2, iclass 14, count 0 2006.202.00:58:51.27#ibcon#flushed, iclass 14, count 0 2006.202.00:58:51.27#ibcon#about to write, iclass 14, count 0 2006.202.00:58:51.27#ibcon#wrote, iclass 14, count 0 2006.202.00:58:51.27#ibcon#about to read 3, iclass 14, count 0 2006.202.00:58:51.29#ibcon#read 3, iclass 14, count 0 2006.202.00:58:51.29#ibcon#about to read 4, iclass 14, count 0 2006.202.00:58:51.29#ibcon#read 4, iclass 14, count 0 2006.202.00:58:51.29#ibcon#about to read 5, iclass 14, count 0 2006.202.00:58:51.29#ibcon#read 5, iclass 14, count 0 2006.202.00:58:51.29#ibcon#about to read 6, iclass 14, count 0 2006.202.00:58:51.29#ibcon#read 6, iclass 14, count 0 2006.202.00:58:51.29#ibcon#end of sib2, iclass 14, count 0 2006.202.00:58:51.29#ibcon#*mode == 0, iclass 14, count 0 2006.202.00:58:51.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.00:58:51.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.00:58:51.29#ibcon#*before write, iclass 14, count 0 2006.202.00:58:51.29#ibcon#enter sib2, iclass 14, count 0 2006.202.00:58:51.29#ibcon#flushed, iclass 14, count 0 2006.202.00:58:51.29#ibcon#about to write, iclass 14, count 0 2006.202.00:58:51.29#ibcon#wrote, iclass 14, count 0 2006.202.00:58:51.29#ibcon#about to read 3, iclass 14, count 0 2006.202.00:58:51.33#ibcon#read 3, iclass 14, count 0 2006.202.00:58:51.33#ibcon#about to read 4, iclass 14, count 0 2006.202.00:58:51.33#ibcon#read 4, iclass 14, count 0 2006.202.00:58:51.33#ibcon#about to read 5, iclass 14, count 0 2006.202.00:58:51.33#ibcon#read 5, iclass 14, count 0 2006.202.00:58:51.33#ibcon#about to read 6, iclass 14, count 0 2006.202.00:58:51.33#ibcon#read 6, iclass 14, count 0 2006.202.00:58:51.33#ibcon#end of sib2, iclass 14, count 0 2006.202.00:58:51.33#ibcon#*after write, iclass 14, count 0 2006.202.00:58:51.33#ibcon#*before return 0, iclass 14, count 0 2006.202.00:58:51.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:51.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.00:58:51.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.00:58:51.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.00:58:51.33$vck44/vb=7,4 2006.202.00:58:51.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.00:58:51.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.00:58:51.33#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:51.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:51.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:51.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:51.39#ibcon#enter wrdev, iclass 16, count 2 2006.202.00:58:51.39#ibcon#first serial, iclass 16, count 2 2006.202.00:58:51.39#ibcon#enter sib2, iclass 16, count 2 2006.202.00:58:51.39#ibcon#flushed, iclass 16, count 2 2006.202.00:58:51.39#ibcon#about to write, iclass 16, count 2 2006.202.00:58:51.39#ibcon#wrote, iclass 16, count 2 2006.202.00:58:51.39#ibcon#about to read 3, iclass 16, count 2 2006.202.00:58:51.41#ibcon#read 3, iclass 16, count 2 2006.202.00:58:51.41#ibcon#about to read 4, iclass 16, count 2 2006.202.00:58:51.41#ibcon#read 4, iclass 16, count 2 2006.202.00:58:51.41#ibcon#about to read 5, iclass 16, count 2 2006.202.00:58:51.41#ibcon#read 5, iclass 16, count 2 2006.202.00:58:51.41#ibcon#about to read 6, iclass 16, count 2 2006.202.00:58:51.41#ibcon#read 6, iclass 16, count 2 2006.202.00:58:51.41#ibcon#end of sib2, iclass 16, count 2 2006.202.00:58:51.41#ibcon#*mode == 0, iclass 16, count 2 2006.202.00:58:51.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.00:58:51.41#ibcon#[27=AT07-04\r\n] 2006.202.00:58:51.41#ibcon#*before write, iclass 16, count 2 2006.202.00:58:51.41#ibcon#enter sib2, iclass 16, count 2 2006.202.00:58:51.41#ibcon#flushed, iclass 16, count 2 2006.202.00:58:51.41#ibcon#about to write, iclass 16, count 2 2006.202.00:58:51.41#ibcon#wrote, iclass 16, count 2 2006.202.00:58:51.41#ibcon#about to read 3, iclass 16, count 2 2006.202.00:58:51.44#ibcon#read 3, iclass 16, count 2 2006.202.00:58:51.44#ibcon#about to read 4, iclass 16, count 2 2006.202.00:58:51.44#ibcon#read 4, iclass 16, count 2 2006.202.00:58:51.44#ibcon#about to read 5, iclass 16, count 2 2006.202.00:58:51.44#ibcon#read 5, iclass 16, count 2 2006.202.00:58:51.44#ibcon#about to read 6, iclass 16, count 2 2006.202.00:58:51.44#ibcon#read 6, iclass 16, count 2 2006.202.00:58:51.44#ibcon#end of sib2, iclass 16, count 2 2006.202.00:58:51.44#ibcon#*after write, iclass 16, count 2 2006.202.00:58:51.44#ibcon#*before return 0, iclass 16, count 2 2006.202.00:58:51.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:51.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.00:58:51.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.00:58:51.44#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:51.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:51.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:51.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:51.56#ibcon#enter wrdev, iclass 16, count 0 2006.202.00:58:51.56#ibcon#first serial, iclass 16, count 0 2006.202.00:58:51.56#ibcon#enter sib2, iclass 16, count 0 2006.202.00:58:51.56#ibcon#flushed, iclass 16, count 0 2006.202.00:58:51.56#ibcon#about to write, iclass 16, count 0 2006.202.00:58:51.56#ibcon#wrote, iclass 16, count 0 2006.202.00:58:51.56#ibcon#about to read 3, iclass 16, count 0 2006.202.00:58:51.58#ibcon#read 3, iclass 16, count 0 2006.202.00:58:51.58#ibcon#about to read 4, iclass 16, count 0 2006.202.00:58:51.58#ibcon#read 4, iclass 16, count 0 2006.202.00:58:51.58#ibcon#about to read 5, iclass 16, count 0 2006.202.00:58:51.58#ibcon#read 5, iclass 16, count 0 2006.202.00:58:51.58#ibcon#about to read 6, iclass 16, count 0 2006.202.00:58:51.58#ibcon#read 6, iclass 16, count 0 2006.202.00:58:51.58#ibcon#end of sib2, iclass 16, count 0 2006.202.00:58:51.58#ibcon#*mode == 0, iclass 16, count 0 2006.202.00:58:51.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.00:58:51.58#ibcon#[27=USB\r\n] 2006.202.00:58:51.58#ibcon#*before write, iclass 16, count 0 2006.202.00:58:51.58#ibcon#enter sib2, iclass 16, count 0 2006.202.00:58:51.58#ibcon#flushed, iclass 16, count 0 2006.202.00:58:51.58#ibcon#about to write, iclass 16, count 0 2006.202.00:58:51.58#ibcon#wrote, iclass 16, count 0 2006.202.00:58:51.58#ibcon#about to read 3, iclass 16, count 0 2006.202.00:58:51.61#ibcon#read 3, iclass 16, count 0 2006.202.00:58:51.61#ibcon#about to read 4, iclass 16, count 0 2006.202.00:58:51.61#ibcon#read 4, iclass 16, count 0 2006.202.00:58:51.61#ibcon#about to read 5, iclass 16, count 0 2006.202.00:58:51.61#ibcon#read 5, iclass 16, count 0 2006.202.00:58:51.61#ibcon#about to read 6, iclass 16, count 0 2006.202.00:58:51.61#ibcon#read 6, iclass 16, count 0 2006.202.00:58:51.61#ibcon#end of sib2, iclass 16, count 0 2006.202.00:58:51.61#ibcon#*after write, iclass 16, count 0 2006.202.00:58:51.61#ibcon#*before return 0, iclass 16, count 0 2006.202.00:58:51.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:51.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.00:58:51.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.00:58:51.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.00:58:51.61$vck44/vblo=8,744.99 2006.202.00:58:51.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.00:58:51.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.00:58:51.61#ibcon#ireg 17 cls_cnt 0 2006.202.00:58:51.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:58:51.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:58:51.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:58:51.61#ibcon#enter wrdev, iclass 18, count 0 2006.202.00:58:51.61#ibcon#first serial, iclass 18, count 0 2006.202.00:58:51.61#ibcon#enter sib2, iclass 18, count 0 2006.202.00:58:51.61#ibcon#flushed, iclass 18, count 0 2006.202.00:58:51.61#ibcon#about to write, iclass 18, count 0 2006.202.00:58:51.61#ibcon#wrote, iclass 18, count 0 2006.202.00:58:51.61#ibcon#about to read 3, iclass 18, count 0 2006.202.00:58:51.63#ibcon#read 3, iclass 18, count 0 2006.202.00:58:51.63#ibcon#about to read 4, iclass 18, count 0 2006.202.00:58:51.63#ibcon#read 4, iclass 18, count 0 2006.202.00:58:51.63#ibcon#about to read 5, iclass 18, count 0 2006.202.00:58:51.63#ibcon#read 5, iclass 18, count 0 2006.202.00:58:51.63#ibcon#about to read 6, iclass 18, count 0 2006.202.00:58:51.63#ibcon#read 6, iclass 18, count 0 2006.202.00:58:51.63#ibcon#end of sib2, iclass 18, count 0 2006.202.00:58:51.63#ibcon#*mode == 0, iclass 18, count 0 2006.202.00:58:51.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.00:58:51.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.00:58:51.63#ibcon#*before write, iclass 18, count 0 2006.202.00:58:51.63#ibcon#enter sib2, iclass 18, count 0 2006.202.00:58:51.63#ibcon#flushed, iclass 18, count 0 2006.202.00:58:51.63#ibcon#about to write, iclass 18, count 0 2006.202.00:58:51.63#ibcon#wrote, iclass 18, count 0 2006.202.00:58:51.63#ibcon#about to read 3, iclass 18, count 0 2006.202.00:58:51.67#ibcon#read 3, iclass 18, count 0 2006.202.00:58:51.67#ibcon#about to read 4, iclass 18, count 0 2006.202.00:58:51.67#ibcon#read 4, iclass 18, count 0 2006.202.00:58:51.67#ibcon#about to read 5, iclass 18, count 0 2006.202.00:58:51.67#ibcon#read 5, iclass 18, count 0 2006.202.00:58:51.67#ibcon#about to read 6, iclass 18, count 0 2006.202.00:58:51.67#ibcon#read 6, iclass 18, count 0 2006.202.00:58:51.67#ibcon#end of sib2, iclass 18, count 0 2006.202.00:58:51.67#ibcon#*after write, iclass 18, count 0 2006.202.00:58:51.67#ibcon#*before return 0, iclass 18, count 0 2006.202.00:58:51.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:58:51.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.00:58:51.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.00:58:51.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.00:58:51.67$vck44/vb=8,4 2006.202.00:58:51.67#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.00:58:51.67#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.00:58:51.67#ibcon#ireg 11 cls_cnt 2 2006.202.00:58:51.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:58:51.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:58:51.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:58:51.73#ibcon#enter wrdev, iclass 20, count 2 2006.202.00:58:51.73#ibcon#first serial, iclass 20, count 2 2006.202.00:58:51.73#ibcon#enter sib2, iclass 20, count 2 2006.202.00:58:51.73#ibcon#flushed, iclass 20, count 2 2006.202.00:58:51.73#ibcon#about to write, iclass 20, count 2 2006.202.00:58:51.73#ibcon#wrote, iclass 20, count 2 2006.202.00:58:51.73#ibcon#about to read 3, iclass 20, count 2 2006.202.00:58:51.75#ibcon#read 3, iclass 20, count 2 2006.202.00:58:51.75#ibcon#about to read 4, iclass 20, count 2 2006.202.00:58:51.75#ibcon#read 4, iclass 20, count 2 2006.202.00:58:51.75#ibcon#about to read 5, iclass 20, count 2 2006.202.00:58:51.75#ibcon#read 5, iclass 20, count 2 2006.202.00:58:51.75#ibcon#about to read 6, iclass 20, count 2 2006.202.00:58:51.75#ibcon#read 6, iclass 20, count 2 2006.202.00:58:51.75#ibcon#end of sib2, iclass 20, count 2 2006.202.00:58:51.75#ibcon#*mode == 0, iclass 20, count 2 2006.202.00:58:51.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.00:58:51.75#ibcon#[27=AT08-04\r\n] 2006.202.00:58:51.75#ibcon#*before write, iclass 20, count 2 2006.202.00:58:51.75#ibcon#enter sib2, iclass 20, count 2 2006.202.00:58:51.75#ibcon#flushed, iclass 20, count 2 2006.202.00:58:51.75#ibcon#about to write, iclass 20, count 2 2006.202.00:58:51.75#ibcon#wrote, iclass 20, count 2 2006.202.00:58:51.75#ibcon#about to read 3, iclass 20, count 2 2006.202.00:58:51.78#ibcon#read 3, iclass 20, count 2 2006.202.00:58:51.78#ibcon#about to read 4, iclass 20, count 2 2006.202.00:58:51.78#ibcon#read 4, iclass 20, count 2 2006.202.00:58:51.78#ibcon#about to read 5, iclass 20, count 2 2006.202.00:58:51.78#ibcon#read 5, iclass 20, count 2 2006.202.00:58:51.78#ibcon#about to read 6, iclass 20, count 2 2006.202.00:58:51.78#ibcon#read 6, iclass 20, count 2 2006.202.00:58:51.78#ibcon#end of sib2, iclass 20, count 2 2006.202.00:58:51.78#ibcon#*after write, iclass 20, count 2 2006.202.00:58:51.78#ibcon#*before return 0, iclass 20, count 2 2006.202.00:58:51.78#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:58:51.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.00:58:51.78#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.00:58:51.78#ibcon#ireg 7 cls_cnt 0 2006.202.00:58:51.78#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:58:51.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:58:51.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:58:51.90#ibcon#enter wrdev, iclass 20, count 0 2006.202.00:58:51.90#ibcon#first serial, iclass 20, count 0 2006.202.00:58:51.90#ibcon#enter sib2, iclass 20, count 0 2006.202.00:58:51.90#ibcon#flushed, iclass 20, count 0 2006.202.00:58:51.90#ibcon#about to write, iclass 20, count 0 2006.202.00:58:51.90#ibcon#wrote, iclass 20, count 0 2006.202.00:58:51.90#ibcon#about to read 3, iclass 20, count 0 2006.202.00:58:51.92#ibcon#read 3, iclass 20, count 0 2006.202.00:58:51.92#ibcon#about to read 4, iclass 20, count 0 2006.202.00:58:51.92#ibcon#read 4, iclass 20, count 0 2006.202.00:58:51.92#ibcon#about to read 5, iclass 20, count 0 2006.202.00:58:51.92#ibcon#read 5, iclass 20, count 0 2006.202.00:58:51.92#ibcon#about to read 6, iclass 20, count 0 2006.202.00:58:51.92#ibcon#read 6, iclass 20, count 0 2006.202.00:58:51.92#ibcon#end of sib2, iclass 20, count 0 2006.202.00:58:51.92#ibcon#*mode == 0, iclass 20, count 0 2006.202.00:58:51.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.00:58:51.92#ibcon#[27=USB\r\n] 2006.202.00:58:51.92#ibcon#*before write, iclass 20, count 0 2006.202.00:58:51.92#ibcon#enter sib2, iclass 20, count 0 2006.202.00:58:51.92#ibcon#flushed, iclass 20, count 0 2006.202.00:58:51.92#ibcon#about to write, iclass 20, count 0 2006.202.00:58:51.92#ibcon#wrote, iclass 20, count 0 2006.202.00:58:51.92#ibcon#about to read 3, iclass 20, count 0 2006.202.00:58:51.95#ibcon#read 3, iclass 20, count 0 2006.202.00:58:51.95#ibcon#about to read 4, iclass 20, count 0 2006.202.00:58:51.95#ibcon#read 4, iclass 20, count 0 2006.202.00:58:51.95#ibcon#about to read 5, iclass 20, count 0 2006.202.00:58:51.95#ibcon#read 5, iclass 20, count 0 2006.202.00:58:51.95#ibcon#about to read 6, iclass 20, count 0 2006.202.00:58:51.95#ibcon#read 6, iclass 20, count 0 2006.202.00:58:51.95#ibcon#end of sib2, iclass 20, count 0 2006.202.00:58:51.95#ibcon#*after write, iclass 20, count 0 2006.202.00:58:51.95#ibcon#*before return 0, iclass 20, count 0 2006.202.00:58:51.95#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:58:51.95#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.00:58:51.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.00:58:51.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.00:58:51.95$vck44/vabw=wide 2006.202.00:58:51.95#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.00:58:51.95#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.00:58:51.95#ibcon#ireg 8 cls_cnt 0 2006.202.00:58:51.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:51.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:51.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:51.95#ibcon#enter wrdev, iclass 22, count 0 2006.202.00:58:51.95#ibcon#first serial, iclass 22, count 0 2006.202.00:58:51.95#ibcon#enter sib2, iclass 22, count 0 2006.202.00:58:51.95#ibcon#flushed, iclass 22, count 0 2006.202.00:58:51.95#ibcon#about to write, iclass 22, count 0 2006.202.00:58:51.95#ibcon#wrote, iclass 22, count 0 2006.202.00:58:51.95#ibcon#about to read 3, iclass 22, count 0 2006.202.00:58:51.97#ibcon#read 3, iclass 22, count 0 2006.202.00:58:51.97#ibcon#about to read 4, iclass 22, count 0 2006.202.00:58:51.97#ibcon#read 4, iclass 22, count 0 2006.202.00:58:51.97#ibcon#about to read 5, iclass 22, count 0 2006.202.00:58:51.97#ibcon#read 5, iclass 22, count 0 2006.202.00:58:51.97#ibcon#about to read 6, iclass 22, count 0 2006.202.00:58:51.97#ibcon#read 6, iclass 22, count 0 2006.202.00:58:51.97#ibcon#end of sib2, iclass 22, count 0 2006.202.00:58:51.97#ibcon#*mode == 0, iclass 22, count 0 2006.202.00:58:51.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.00:58:51.97#ibcon#[25=BW32\r\n] 2006.202.00:58:51.97#ibcon#*before write, iclass 22, count 0 2006.202.00:58:51.97#ibcon#enter sib2, iclass 22, count 0 2006.202.00:58:51.97#ibcon#flushed, iclass 22, count 0 2006.202.00:58:51.97#ibcon#about to write, iclass 22, count 0 2006.202.00:58:51.97#ibcon#wrote, iclass 22, count 0 2006.202.00:58:51.97#ibcon#about to read 3, iclass 22, count 0 2006.202.00:58:52.00#ibcon#read 3, iclass 22, count 0 2006.202.00:58:52.00#ibcon#about to read 4, iclass 22, count 0 2006.202.00:58:52.00#ibcon#read 4, iclass 22, count 0 2006.202.00:58:52.00#ibcon#about to read 5, iclass 22, count 0 2006.202.00:58:52.00#ibcon#read 5, iclass 22, count 0 2006.202.00:58:52.00#ibcon#about to read 6, iclass 22, count 0 2006.202.00:58:52.00#ibcon#read 6, iclass 22, count 0 2006.202.00:58:52.00#ibcon#end of sib2, iclass 22, count 0 2006.202.00:58:52.00#ibcon#*after write, iclass 22, count 0 2006.202.00:58:52.00#ibcon#*before return 0, iclass 22, count 0 2006.202.00:58:52.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:52.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.00:58:52.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.00:58:52.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.00:58:52.00$vck44/vbbw=wide 2006.202.00:58:52.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.202.00:58:52.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.202.00:58:52.00#ibcon#ireg 8 cls_cnt 0 2006.202.00:58:52.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:58:52.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:58:52.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:58:52.07#ibcon#enter wrdev, iclass 24, count 0 2006.202.00:58:52.07#ibcon#first serial, iclass 24, count 0 2006.202.00:58:52.07#ibcon#enter sib2, iclass 24, count 0 2006.202.00:58:52.07#ibcon#flushed, iclass 24, count 0 2006.202.00:58:52.07#ibcon#about to write, iclass 24, count 0 2006.202.00:58:52.07#ibcon#wrote, iclass 24, count 0 2006.202.00:58:52.07#ibcon#about to read 3, iclass 24, count 0 2006.202.00:58:52.09#ibcon#read 3, iclass 24, count 0 2006.202.00:58:52.09#ibcon#about to read 4, iclass 24, count 0 2006.202.00:58:52.09#ibcon#read 4, iclass 24, count 0 2006.202.00:58:52.09#ibcon#about to read 5, iclass 24, count 0 2006.202.00:58:52.09#ibcon#read 5, iclass 24, count 0 2006.202.00:58:52.09#ibcon#about to read 6, iclass 24, count 0 2006.202.00:58:52.09#ibcon#read 6, iclass 24, count 0 2006.202.00:58:52.09#ibcon#end of sib2, iclass 24, count 0 2006.202.00:58:52.09#ibcon#*mode == 0, iclass 24, count 0 2006.202.00:58:52.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.00:58:52.09#ibcon#[27=BW32\r\n] 2006.202.00:58:52.09#ibcon#*before write, iclass 24, count 0 2006.202.00:58:52.09#ibcon#enter sib2, iclass 24, count 0 2006.202.00:58:52.09#ibcon#flushed, iclass 24, count 0 2006.202.00:58:52.09#ibcon#about to write, iclass 24, count 0 2006.202.00:58:52.09#ibcon#wrote, iclass 24, count 0 2006.202.00:58:52.09#ibcon#about to read 3, iclass 24, count 0 2006.202.00:58:52.12#ibcon#read 3, iclass 24, count 0 2006.202.00:58:52.19#ibcon#about to read 4, iclass 24, count 0 2006.202.00:58:52.19#ibcon#read 4, iclass 24, count 0 2006.202.00:58:52.19#ibcon#about to read 5, iclass 24, count 0 2006.202.00:58:52.19#ibcon#read 5, iclass 24, count 0 2006.202.00:58:52.19#ibcon#about to read 6, iclass 24, count 0 2006.202.00:58:52.19#ibcon#read 6, iclass 24, count 0 2006.202.00:58:52.19#ibcon#end of sib2, iclass 24, count 0 2006.202.00:58:52.19#ibcon#*after write, iclass 24, count 0 2006.202.00:58:52.19#ibcon#*before return 0, iclass 24, count 0 2006.202.00:58:52.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:58:52.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.202.00:58:52.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.00:58:52.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.00:58:52.20$setupk4/ifdk4 2006.202.00:58:52.20$ifdk4/lo= 2006.202.00:58:52.20$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.00:58:52.20$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.00:58:52.20$ifdk4/patch= 2006.202.00:58:52.20$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.00:58:52.20$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.00:58:52.20$setupk4/!*+20s 2006.202.00:58:58.87#abcon#<5=/04 2.4 5.2 20.341001001.3\r\n> 2006.202.00:58:58.89#abcon#{5=INTERFACE CLEAR} 2006.202.00:58:58.95#abcon#[5=S1D000X0/0*\r\n] 2006.202.00:59:06.53$setupk4/"tpicd 2006.202.00:59:06.53$setupk4/echo=off 2006.202.00:59:06.53$setupk4/xlog=off 2006.202.00:59:06.53:!2006.202.01:02:22 2006.202.00:59:12.14#trakl#Source acquired 2006.202.00:59:14.14#flagr#flagr/antenna,acquired 2006.202.01:02:22.00:preob 2006.202.01:02:22.14/onsource/TRACKING 2006.202.01:02:22.14:!2006.202.01:02:32 2006.202.01:02:32.00:"tape 2006.202.01:02:32.00:"st=record 2006.202.01:02:32.00:data_valid=on 2006.202.01:02:32.00:midob 2006.202.01:02:32.14/onsource/TRACKING 2006.202.01:02:32.14/wx/20.35,1001.1,100 2006.202.01:02:32.26/cable/+6.4862E-03 2006.202.01:02:33.35/va/01,08,usb,yes,44,47 2006.202.01:02:33.35/va/02,07,usb,yes,47,48 2006.202.01:02:33.35/va/03,08,usb,yes,43,45 2006.202.01:02:33.35/va/04,07,usb,yes,49,51 2006.202.01:02:33.35/va/05,04,usb,yes,43,44 2006.202.01:02:33.35/va/06,05,usb,yes,44,44 2006.202.01:02:33.35/va/07,05,usb,yes,43,44 2006.202.01:02:33.35/va/08,04,usb,yes,42,50 2006.202.01:02:33.58/valo/01,524.99,yes,locked 2006.202.01:02:33.58/valo/02,534.99,yes,locked 2006.202.01:02:33.58/valo/03,564.99,yes,locked 2006.202.01:02:33.58/valo/04,624.99,yes,locked 2006.202.01:02:33.58/valo/05,734.99,yes,locked 2006.202.01:02:33.58/valo/06,814.99,yes,locked 2006.202.01:02:33.58/valo/07,864.99,yes,locked 2006.202.01:02:33.58/valo/08,884.99,yes,locked 2006.202.01:02:34.67/vb/01,04,usb,yes,31,28 2006.202.01:02:34.67/vb/02,05,usb,yes,29,29 2006.202.01:02:34.67/vb/03,04,usb,yes,30,33 2006.202.01:02:34.67/vb/04,05,usb,yes,30,29 2006.202.01:02:34.67/vb/05,04,usb,yes,27,29 2006.202.01:02:34.67/vb/06,04,usb,yes,31,27 2006.202.01:02:34.67/vb/07,04,usb,yes,31,31 2006.202.01:02:34.67/vb/08,04,usb,yes,28,32 2006.202.01:02:34.90/vblo/01,629.99,yes,locked 2006.202.01:02:34.90/vblo/02,634.99,yes,locked 2006.202.01:02:34.90/vblo/03,649.99,yes,locked 2006.202.01:02:34.90/vblo/04,679.99,yes,locked 2006.202.01:02:34.90/vblo/05,709.99,yes,locked 2006.202.01:02:34.90/vblo/06,719.99,yes,locked 2006.202.01:02:34.90/vblo/07,734.99,yes,locked 2006.202.01:02:34.90/vblo/08,744.99,yes,locked 2006.202.01:02:35.05/vabw/8 2006.202.01:02:35.20/vbbw/8 2006.202.01:02:35.29/xfe/off,on,15.5 2006.202.01:02:35.67/ifatt/23,28,28,28 2006.202.01:02:36.07/fmout-gps/S +4.49E-07 2006.202.01:02:36.11:!2006.202.01:06:42 2006.202.01:06:42.00:data_valid=off 2006.202.01:06:42.00:"et 2006.202.01:06:42.00:!+3s 2006.202.01:06:45.01:"tape 2006.202.01:06:45.01:postob 2006.202.01:06:45.22/cable/+6.4860E-03 2006.202.01:06:45.22/wx/20.38,1001.0,100 2006.202.01:06:46.07/fmout-gps/S +4.50E-07 2006.202.01:06:46.07:scan_name=202-0110,jd0607,540 2006.202.01:06:46.07:source=1308+326,131028.66,322043.8,2000.0,ccw 2006.202.01:06:47.13:checkk5 2006.202.01:06:47.13#flagr#flagr/antenna,new-source 2006.202.01:06:47.54/chk_autoobs//k5ts1/ autoobs is running! 2006.202.01:06:47.94/chk_autoobs//k5ts2/ autoobs is running! 2006.202.01:06:48.35/chk_autoobs//k5ts3/ autoobs is running! 2006.202.01:06:48.74/chk_autoobs//k5ts4/ autoobs is running! 2006.202.01:06:49.12/chk_obsdata//k5ts1/T2020102??a.dat file size is correct (nominal:1000MB, actual:996MB). 2006.202.01:06:49.51/chk_obsdata//k5ts2/T2020102??b.dat file size is correct (nominal:1000MB, actual:996MB). 2006.202.01:06:49.92/chk_obsdata//k5ts3/T2020102??c.dat file size is correct (nominal:1000MB, actual:996MB). 2006.202.01:06:50.32/chk_obsdata//k5ts4/T2020102??d.dat file size is correct (nominal:1000MB, actual:996MB). 2006.202.01:06:51.05/k5log//k5ts1_log_newline 2006.202.01:06:51.75/k5log//k5ts2_log_newline 2006.202.01:06:52.47/k5log//k5ts3_log_newline 2006.202.01:06:53.19/k5log//k5ts4_log_newline 2006.202.01:06:53.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.01:06:53.22:setupk4=1 2006.202.01:06:53.22$setupk4/echo=on 2006.202.01:06:53.22$setupk4/pcalon 2006.202.01:06:53.22$pcalon/"no phase cal control is implemented here 2006.202.01:06:53.22$setupk4/"tpicd=stop 2006.202.01:06:53.22$setupk4/"rec=synch_on 2006.202.01:06:53.22$setupk4/"rec_mode=128 2006.202.01:06:53.22$setupk4/!* 2006.202.01:06:53.22$setupk4/recpk4 2006.202.01:06:53.22$recpk4/recpatch= 2006.202.01:06:53.22$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.01:06:53.22$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.01:06:53.22$setupk4/vck44 2006.202.01:06:53.22$vck44/valo=1,524.99 2006.202.01:06:53.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.202.01:06:53.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.202.01:06:53.22#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:53.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:53.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:53.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:53.22#ibcon#enter wrdev, iclass 37, count 0 2006.202.01:06:53.22#ibcon#first serial, iclass 37, count 0 2006.202.01:06:53.22#ibcon#enter sib2, iclass 37, count 0 2006.202.01:06:53.22#ibcon#flushed, iclass 37, count 0 2006.202.01:06:53.22#ibcon#about to write, iclass 37, count 0 2006.202.01:06:53.22#ibcon#wrote, iclass 37, count 0 2006.202.01:06:53.22#ibcon#about to read 3, iclass 37, count 0 2006.202.01:06:53.24#ibcon#read 3, iclass 37, count 0 2006.202.01:06:53.24#ibcon#about to read 4, iclass 37, count 0 2006.202.01:06:53.24#ibcon#read 4, iclass 37, count 0 2006.202.01:06:53.24#ibcon#about to read 5, iclass 37, count 0 2006.202.01:06:53.24#ibcon#read 5, iclass 37, count 0 2006.202.01:06:53.24#ibcon#about to read 6, iclass 37, count 0 2006.202.01:06:53.24#ibcon#read 6, iclass 37, count 0 2006.202.01:06:53.24#ibcon#end of sib2, iclass 37, count 0 2006.202.01:06:53.24#ibcon#*mode == 0, iclass 37, count 0 2006.202.01:06:53.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.01:06:53.24#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.01:06:53.24#ibcon#*before write, iclass 37, count 0 2006.202.01:06:53.24#ibcon#enter sib2, iclass 37, count 0 2006.202.01:06:53.24#ibcon#flushed, iclass 37, count 0 2006.202.01:06:53.24#ibcon#about to write, iclass 37, count 0 2006.202.01:06:53.24#ibcon#wrote, iclass 37, count 0 2006.202.01:06:53.24#ibcon#about to read 3, iclass 37, count 0 2006.202.01:06:53.29#ibcon#read 3, iclass 37, count 0 2006.202.01:06:53.29#ibcon#about to read 4, iclass 37, count 0 2006.202.01:06:53.29#ibcon#read 4, iclass 37, count 0 2006.202.01:06:53.29#ibcon#about to read 5, iclass 37, count 0 2006.202.01:06:53.29#ibcon#read 5, iclass 37, count 0 2006.202.01:06:53.29#ibcon#about to read 6, iclass 37, count 0 2006.202.01:06:53.29#ibcon#read 6, iclass 37, count 0 2006.202.01:06:53.29#ibcon#end of sib2, iclass 37, count 0 2006.202.01:06:53.29#ibcon#*after write, iclass 37, count 0 2006.202.01:06:53.29#ibcon#*before return 0, iclass 37, count 0 2006.202.01:06:53.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:53.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:53.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.01:06:53.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.01:06:53.29$vck44/va=1,8 2006.202.01:06:53.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.202.01:06:53.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.202.01:06:53.29#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:53.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:53.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:53.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:53.29#ibcon#enter wrdev, iclass 39, count 2 2006.202.01:06:53.29#ibcon#first serial, iclass 39, count 2 2006.202.01:06:53.29#ibcon#enter sib2, iclass 39, count 2 2006.202.01:06:53.29#ibcon#flushed, iclass 39, count 2 2006.202.01:06:53.29#ibcon#about to write, iclass 39, count 2 2006.202.01:06:53.29#ibcon#wrote, iclass 39, count 2 2006.202.01:06:53.29#ibcon#about to read 3, iclass 39, count 2 2006.202.01:06:53.31#ibcon#read 3, iclass 39, count 2 2006.202.01:06:53.31#ibcon#about to read 4, iclass 39, count 2 2006.202.01:06:53.31#ibcon#read 4, iclass 39, count 2 2006.202.01:06:53.31#ibcon#about to read 5, iclass 39, count 2 2006.202.01:06:53.31#ibcon#read 5, iclass 39, count 2 2006.202.01:06:53.31#ibcon#about to read 6, iclass 39, count 2 2006.202.01:06:53.31#ibcon#read 6, iclass 39, count 2 2006.202.01:06:53.31#ibcon#end of sib2, iclass 39, count 2 2006.202.01:06:53.31#ibcon#*mode == 0, iclass 39, count 2 2006.202.01:06:53.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.202.01:06:53.31#ibcon#[25=AT01-08\r\n] 2006.202.01:06:53.31#ibcon#*before write, iclass 39, count 2 2006.202.01:06:53.31#ibcon#enter sib2, iclass 39, count 2 2006.202.01:06:53.31#ibcon#flushed, iclass 39, count 2 2006.202.01:06:53.31#ibcon#about to write, iclass 39, count 2 2006.202.01:06:53.31#ibcon#wrote, iclass 39, count 2 2006.202.01:06:53.31#ibcon#about to read 3, iclass 39, count 2 2006.202.01:06:53.34#ibcon#read 3, iclass 39, count 2 2006.202.01:06:53.34#ibcon#about to read 4, iclass 39, count 2 2006.202.01:06:53.34#ibcon#read 4, iclass 39, count 2 2006.202.01:06:53.34#ibcon#about to read 5, iclass 39, count 2 2006.202.01:06:53.34#ibcon#read 5, iclass 39, count 2 2006.202.01:06:53.34#ibcon#about to read 6, iclass 39, count 2 2006.202.01:06:53.34#ibcon#read 6, iclass 39, count 2 2006.202.01:06:53.34#ibcon#end of sib2, iclass 39, count 2 2006.202.01:06:53.34#ibcon#*after write, iclass 39, count 2 2006.202.01:06:53.34#ibcon#*before return 0, iclass 39, count 2 2006.202.01:06:53.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:53.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:53.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.202.01:06:53.34#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:53.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:53.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:53.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:53.46#ibcon#enter wrdev, iclass 39, count 0 2006.202.01:06:53.46#ibcon#first serial, iclass 39, count 0 2006.202.01:06:53.46#ibcon#enter sib2, iclass 39, count 0 2006.202.01:06:53.46#ibcon#flushed, iclass 39, count 0 2006.202.01:06:53.46#ibcon#about to write, iclass 39, count 0 2006.202.01:06:53.46#ibcon#wrote, iclass 39, count 0 2006.202.01:06:53.46#ibcon#about to read 3, iclass 39, count 0 2006.202.01:06:53.48#ibcon#read 3, iclass 39, count 0 2006.202.01:06:53.48#ibcon#about to read 4, iclass 39, count 0 2006.202.01:06:53.48#ibcon#read 4, iclass 39, count 0 2006.202.01:06:53.48#ibcon#about to read 5, iclass 39, count 0 2006.202.01:06:53.48#ibcon#read 5, iclass 39, count 0 2006.202.01:06:53.48#ibcon#about to read 6, iclass 39, count 0 2006.202.01:06:53.48#ibcon#read 6, iclass 39, count 0 2006.202.01:06:53.48#ibcon#end of sib2, iclass 39, count 0 2006.202.01:06:53.48#ibcon#*mode == 0, iclass 39, count 0 2006.202.01:06:53.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.01:06:53.48#ibcon#[25=USB\r\n] 2006.202.01:06:53.48#ibcon#*before write, iclass 39, count 0 2006.202.01:06:53.48#ibcon#enter sib2, iclass 39, count 0 2006.202.01:06:53.48#ibcon#flushed, iclass 39, count 0 2006.202.01:06:53.48#ibcon#about to write, iclass 39, count 0 2006.202.01:06:53.48#ibcon#wrote, iclass 39, count 0 2006.202.01:06:53.48#ibcon#about to read 3, iclass 39, count 0 2006.202.01:06:53.51#ibcon#read 3, iclass 39, count 0 2006.202.01:06:53.51#ibcon#about to read 4, iclass 39, count 0 2006.202.01:06:53.51#ibcon#read 4, iclass 39, count 0 2006.202.01:06:53.51#ibcon#about to read 5, iclass 39, count 0 2006.202.01:06:53.51#ibcon#read 5, iclass 39, count 0 2006.202.01:06:53.51#ibcon#about to read 6, iclass 39, count 0 2006.202.01:06:53.51#ibcon#read 6, iclass 39, count 0 2006.202.01:06:53.51#ibcon#end of sib2, iclass 39, count 0 2006.202.01:06:53.51#ibcon#*after write, iclass 39, count 0 2006.202.01:06:53.51#ibcon#*before return 0, iclass 39, count 0 2006.202.01:06:53.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:53.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:53.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.01:06:53.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.01:06:53.51$vck44/valo=2,534.99 2006.202.01:06:53.51#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.202.01:06:53.51#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.202.01:06:53.51#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:53.51#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:53.51#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:53.51#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:53.51#ibcon#enter wrdev, iclass 2, count 0 2006.202.01:06:53.51#ibcon#first serial, iclass 2, count 0 2006.202.01:06:53.51#ibcon#enter sib2, iclass 2, count 0 2006.202.01:06:53.51#ibcon#flushed, iclass 2, count 0 2006.202.01:06:53.51#ibcon#about to write, iclass 2, count 0 2006.202.01:06:53.51#ibcon#wrote, iclass 2, count 0 2006.202.01:06:53.51#ibcon#about to read 3, iclass 2, count 0 2006.202.01:06:53.53#ibcon#read 3, iclass 2, count 0 2006.202.01:06:53.53#ibcon#about to read 4, iclass 2, count 0 2006.202.01:06:53.53#ibcon#read 4, iclass 2, count 0 2006.202.01:06:53.53#ibcon#about to read 5, iclass 2, count 0 2006.202.01:06:53.53#ibcon#read 5, iclass 2, count 0 2006.202.01:06:53.53#ibcon#about to read 6, iclass 2, count 0 2006.202.01:06:53.53#ibcon#read 6, iclass 2, count 0 2006.202.01:06:53.53#ibcon#end of sib2, iclass 2, count 0 2006.202.01:06:53.53#ibcon#*mode == 0, iclass 2, count 0 2006.202.01:06:53.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.01:06:53.53#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.01:06:53.53#ibcon#*before write, iclass 2, count 0 2006.202.01:06:53.53#ibcon#enter sib2, iclass 2, count 0 2006.202.01:06:53.53#ibcon#flushed, iclass 2, count 0 2006.202.01:06:53.53#ibcon#about to write, iclass 2, count 0 2006.202.01:06:53.53#ibcon#wrote, iclass 2, count 0 2006.202.01:06:53.53#ibcon#about to read 3, iclass 2, count 0 2006.202.01:06:53.57#ibcon#read 3, iclass 2, count 0 2006.202.01:06:53.57#ibcon#about to read 4, iclass 2, count 0 2006.202.01:06:53.57#ibcon#read 4, iclass 2, count 0 2006.202.01:06:53.57#ibcon#about to read 5, iclass 2, count 0 2006.202.01:06:53.57#ibcon#read 5, iclass 2, count 0 2006.202.01:06:53.57#ibcon#about to read 6, iclass 2, count 0 2006.202.01:06:53.57#ibcon#read 6, iclass 2, count 0 2006.202.01:06:53.57#ibcon#end of sib2, iclass 2, count 0 2006.202.01:06:53.57#ibcon#*after write, iclass 2, count 0 2006.202.01:06:53.57#ibcon#*before return 0, iclass 2, count 0 2006.202.01:06:53.57#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:53.57#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:53.57#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.01:06:53.57#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.01:06:53.57$vck44/va=2,7 2006.202.01:06:53.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.202.01:06:53.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.202.01:06:53.57#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:53.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:53.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:53.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:53.63#ibcon#enter wrdev, iclass 5, count 2 2006.202.01:06:53.63#ibcon#first serial, iclass 5, count 2 2006.202.01:06:53.63#ibcon#enter sib2, iclass 5, count 2 2006.202.01:06:53.63#ibcon#flushed, iclass 5, count 2 2006.202.01:06:53.63#ibcon#about to write, iclass 5, count 2 2006.202.01:06:53.63#ibcon#wrote, iclass 5, count 2 2006.202.01:06:53.63#ibcon#about to read 3, iclass 5, count 2 2006.202.01:06:53.65#ibcon#read 3, iclass 5, count 2 2006.202.01:06:53.65#ibcon#about to read 4, iclass 5, count 2 2006.202.01:06:53.65#ibcon#read 4, iclass 5, count 2 2006.202.01:06:53.65#ibcon#about to read 5, iclass 5, count 2 2006.202.01:06:53.65#ibcon#read 5, iclass 5, count 2 2006.202.01:06:53.65#ibcon#about to read 6, iclass 5, count 2 2006.202.01:06:53.65#ibcon#read 6, iclass 5, count 2 2006.202.01:06:53.65#ibcon#end of sib2, iclass 5, count 2 2006.202.01:06:53.65#ibcon#*mode == 0, iclass 5, count 2 2006.202.01:06:53.65#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.202.01:06:53.65#ibcon#[25=AT02-07\r\n] 2006.202.01:06:53.65#ibcon#*before write, iclass 5, count 2 2006.202.01:06:53.65#ibcon#enter sib2, iclass 5, count 2 2006.202.01:06:53.65#ibcon#flushed, iclass 5, count 2 2006.202.01:06:53.65#ibcon#about to write, iclass 5, count 2 2006.202.01:06:53.65#ibcon#wrote, iclass 5, count 2 2006.202.01:06:53.65#ibcon#about to read 3, iclass 5, count 2 2006.202.01:06:53.68#ibcon#read 3, iclass 5, count 2 2006.202.01:06:53.68#ibcon#about to read 4, iclass 5, count 2 2006.202.01:06:53.68#ibcon#read 4, iclass 5, count 2 2006.202.01:06:53.68#ibcon#about to read 5, iclass 5, count 2 2006.202.01:06:53.68#ibcon#read 5, iclass 5, count 2 2006.202.01:06:53.68#ibcon#about to read 6, iclass 5, count 2 2006.202.01:06:53.68#ibcon#read 6, iclass 5, count 2 2006.202.01:06:53.68#ibcon#end of sib2, iclass 5, count 2 2006.202.01:06:53.68#ibcon#*after write, iclass 5, count 2 2006.202.01:06:53.68#ibcon#*before return 0, iclass 5, count 2 2006.202.01:06:53.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:53.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:53.68#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.202.01:06:53.68#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:53.68#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:53.80#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:53.80#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:53.80#ibcon#enter wrdev, iclass 5, count 0 2006.202.01:06:53.80#ibcon#first serial, iclass 5, count 0 2006.202.01:06:53.80#ibcon#enter sib2, iclass 5, count 0 2006.202.01:06:53.80#ibcon#flushed, iclass 5, count 0 2006.202.01:06:53.80#ibcon#about to write, iclass 5, count 0 2006.202.01:06:53.80#ibcon#wrote, iclass 5, count 0 2006.202.01:06:53.80#ibcon#about to read 3, iclass 5, count 0 2006.202.01:06:53.82#ibcon#read 3, iclass 5, count 0 2006.202.01:06:53.82#ibcon#about to read 4, iclass 5, count 0 2006.202.01:06:53.82#ibcon#read 4, iclass 5, count 0 2006.202.01:06:53.82#ibcon#about to read 5, iclass 5, count 0 2006.202.01:06:53.82#ibcon#read 5, iclass 5, count 0 2006.202.01:06:53.82#ibcon#about to read 6, iclass 5, count 0 2006.202.01:06:53.82#ibcon#read 6, iclass 5, count 0 2006.202.01:06:53.82#ibcon#end of sib2, iclass 5, count 0 2006.202.01:06:53.82#ibcon#*mode == 0, iclass 5, count 0 2006.202.01:06:53.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.01:06:53.82#ibcon#[25=USB\r\n] 2006.202.01:06:53.82#ibcon#*before write, iclass 5, count 0 2006.202.01:06:53.82#ibcon#enter sib2, iclass 5, count 0 2006.202.01:06:53.82#ibcon#flushed, iclass 5, count 0 2006.202.01:06:53.82#ibcon#about to write, iclass 5, count 0 2006.202.01:06:53.82#ibcon#wrote, iclass 5, count 0 2006.202.01:06:53.82#ibcon#about to read 3, iclass 5, count 0 2006.202.01:06:53.85#ibcon#read 3, iclass 5, count 0 2006.202.01:06:53.85#ibcon#about to read 4, iclass 5, count 0 2006.202.01:06:53.85#ibcon#read 4, iclass 5, count 0 2006.202.01:06:53.85#ibcon#about to read 5, iclass 5, count 0 2006.202.01:06:53.85#ibcon#read 5, iclass 5, count 0 2006.202.01:06:53.85#ibcon#about to read 6, iclass 5, count 0 2006.202.01:06:53.85#ibcon#read 6, iclass 5, count 0 2006.202.01:06:53.85#ibcon#end of sib2, iclass 5, count 0 2006.202.01:06:53.85#ibcon#*after write, iclass 5, count 0 2006.202.01:06:53.85#ibcon#*before return 0, iclass 5, count 0 2006.202.01:06:53.85#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:53.85#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:53.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.01:06:53.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.01:06:53.85$vck44/valo=3,564.99 2006.202.01:06:53.85#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.01:06:53.85#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.01:06:53.85#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:53.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:53.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:53.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:53.85#ibcon#enter wrdev, iclass 7, count 0 2006.202.01:06:53.85#ibcon#first serial, iclass 7, count 0 2006.202.01:06:53.85#ibcon#enter sib2, iclass 7, count 0 2006.202.01:06:53.85#ibcon#flushed, iclass 7, count 0 2006.202.01:06:53.85#ibcon#about to write, iclass 7, count 0 2006.202.01:06:53.85#ibcon#wrote, iclass 7, count 0 2006.202.01:06:53.85#ibcon#about to read 3, iclass 7, count 0 2006.202.01:06:53.87#ibcon#read 3, iclass 7, count 0 2006.202.01:06:53.87#ibcon#about to read 4, iclass 7, count 0 2006.202.01:06:53.87#ibcon#read 4, iclass 7, count 0 2006.202.01:06:53.87#ibcon#about to read 5, iclass 7, count 0 2006.202.01:06:53.87#ibcon#read 5, iclass 7, count 0 2006.202.01:06:53.87#ibcon#about to read 6, iclass 7, count 0 2006.202.01:06:53.87#ibcon#read 6, iclass 7, count 0 2006.202.01:06:53.87#ibcon#end of sib2, iclass 7, count 0 2006.202.01:06:53.87#ibcon#*mode == 0, iclass 7, count 0 2006.202.01:06:53.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.01:06:53.87#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.01:06:53.87#ibcon#*before write, iclass 7, count 0 2006.202.01:06:53.87#ibcon#enter sib2, iclass 7, count 0 2006.202.01:06:53.87#ibcon#flushed, iclass 7, count 0 2006.202.01:06:53.87#ibcon#about to write, iclass 7, count 0 2006.202.01:06:53.87#ibcon#wrote, iclass 7, count 0 2006.202.01:06:53.87#ibcon#about to read 3, iclass 7, count 0 2006.202.01:06:53.91#ibcon#read 3, iclass 7, count 0 2006.202.01:06:53.91#ibcon#about to read 4, iclass 7, count 0 2006.202.01:06:53.91#ibcon#read 4, iclass 7, count 0 2006.202.01:06:53.91#ibcon#about to read 5, iclass 7, count 0 2006.202.01:06:53.91#ibcon#read 5, iclass 7, count 0 2006.202.01:06:53.91#ibcon#about to read 6, iclass 7, count 0 2006.202.01:06:53.91#ibcon#read 6, iclass 7, count 0 2006.202.01:06:53.91#ibcon#end of sib2, iclass 7, count 0 2006.202.01:06:53.91#ibcon#*after write, iclass 7, count 0 2006.202.01:06:53.91#ibcon#*before return 0, iclass 7, count 0 2006.202.01:06:53.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:53.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:53.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.01:06:53.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.01:06:53.91$vck44/va=3,8 2006.202.01:06:53.91#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.202.01:06:53.91#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.202.01:06:53.91#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:53.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:53.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:53.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:53.97#ibcon#enter wrdev, iclass 11, count 2 2006.202.01:06:53.97#ibcon#first serial, iclass 11, count 2 2006.202.01:06:53.97#ibcon#enter sib2, iclass 11, count 2 2006.202.01:06:53.97#ibcon#flushed, iclass 11, count 2 2006.202.01:06:53.97#ibcon#about to write, iclass 11, count 2 2006.202.01:06:53.97#ibcon#wrote, iclass 11, count 2 2006.202.01:06:53.97#ibcon#about to read 3, iclass 11, count 2 2006.202.01:06:53.99#ibcon#read 3, iclass 11, count 2 2006.202.01:06:53.99#ibcon#about to read 4, iclass 11, count 2 2006.202.01:06:53.99#ibcon#read 4, iclass 11, count 2 2006.202.01:06:53.99#ibcon#about to read 5, iclass 11, count 2 2006.202.01:06:53.99#ibcon#read 5, iclass 11, count 2 2006.202.01:06:53.99#ibcon#about to read 6, iclass 11, count 2 2006.202.01:06:53.99#ibcon#read 6, iclass 11, count 2 2006.202.01:06:53.99#ibcon#end of sib2, iclass 11, count 2 2006.202.01:06:53.99#ibcon#*mode == 0, iclass 11, count 2 2006.202.01:06:53.99#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.202.01:06:53.99#ibcon#[25=AT03-08\r\n] 2006.202.01:06:53.99#ibcon#*before write, iclass 11, count 2 2006.202.01:06:53.99#ibcon#enter sib2, iclass 11, count 2 2006.202.01:06:53.99#ibcon#flushed, iclass 11, count 2 2006.202.01:06:53.99#ibcon#about to write, iclass 11, count 2 2006.202.01:06:53.99#ibcon#wrote, iclass 11, count 2 2006.202.01:06:53.99#ibcon#about to read 3, iclass 11, count 2 2006.202.01:06:54.02#ibcon#read 3, iclass 11, count 2 2006.202.01:06:54.02#ibcon#about to read 4, iclass 11, count 2 2006.202.01:06:54.02#ibcon#read 4, iclass 11, count 2 2006.202.01:06:54.02#ibcon#about to read 5, iclass 11, count 2 2006.202.01:06:54.02#ibcon#read 5, iclass 11, count 2 2006.202.01:06:54.02#ibcon#about to read 6, iclass 11, count 2 2006.202.01:06:54.02#ibcon#read 6, iclass 11, count 2 2006.202.01:06:54.02#ibcon#end of sib2, iclass 11, count 2 2006.202.01:06:54.02#ibcon#*after write, iclass 11, count 2 2006.202.01:06:54.02#ibcon#*before return 0, iclass 11, count 2 2006.202.01:06:54.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:54.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:54.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.202.01:06:54.02#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:54.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:54.14#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:54.14#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:54.14#ibcon#enter wrdev, iclass 11, count 0 2006.202.01:06:54.14#ibcon#first serial, iclass 11, count 0 2006.202.01:06:54.14#ibcon#enter sib2, iclass 11, count 0 2006.202.01:06:54.14#ibcon#flushed, iclass 11, count 0 2006.202.01:06:54.14#ibcon#about to write, iclass 11, count 0 2006.202.01:06:54.14#ibcon#wrote, iclass 11, count 0 2006.202.01:06:54.14#ibcon#about to read 3, iclass 11, count 0 2006.202.01:06:54.16#ibcon#read 3, iclass 11, count 0 2006.202.01:06:54.16#ibcon#about to read 4, iclass 11, count 0 2006.202.01:06:54.16#ibcon#read 4, iclass 11, count 0 2006.202.01:06:54.16#ibcon#about to read 5, iclass 11, count 0 2006.202.01:06:54.16#ibcon#read 5, iclass 11, count 0 2006.202.01:06:54.16#ibcon#about to read 6, iclass 11, count 0 2006.202.01:06:54.16#ibcon#read 6, iclass 11, count 0 2006.202.01:06:54.16#ibcon#end of sib2, iclass 11, count 0 2006.202.01:06:54.16#ibcon#*mode == 0, iclass 11, count 0 2006.202.01:06:54.16#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.01:06:54.16#ibcon#[25=USB\r\n] 2006.202.01:06:54.16#ibcon#*before write, iclass 11, count 0 2006.202.01:06:54.16#ibcon#enter sib2, iclass 11, count 0 2006.202.01:06:54.16#ibcon#flushed, iclass 11, count 0 2006.202.01:06:54.16#ibcon#about to write, iclass 11, count 0 2006.202.01:06:54.16#ibcon#wrote, iclass 11, count 0 2006.202.01:06:54.16#ibcon#about to read 3, iclass 11, count 0 2006.202.01:06:54.19#ibcon#read 3, iclass 11, count 0 2006.202.01:06:54.19#ibcon#about to read 4, iclass 11, count 0 2006.202.01:06:54.19#ibcon#read 4, iclass 11, count 0 2006.202.01:06:54.19#ibcon#about to read 5, iclass 11, count 0 2006.202.01:06:54.19#ibcon#read 5, iclass 11, count 0 2006.202.01:06:54.19#ibcon#about to read 6, iclass 11, count 0 2006.202.01:06:54.19#ibcon#read 6, iclass 11, count 0 2006.202.01:06:54.19#ibcon#end of sib2, iclass 11, count 0 2006.202.01:06:54.19#ibcon#*after write, iclass 11, count 0 2006.202.01:06:54.19#ibcon#*before return 0, iclass 11, count 0 2006.202.01:06:54.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:54.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:54.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.01:06:54.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.01:06:54.19$vck44/valo=4,624.99 2006.202.01:06:54.19#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.202.01:06:54.19#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.202.01:06:54.19#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:54.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:06:54.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:06:54.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:06:54.19#ibcon#enter wrdev, iclass 13, count 0 2006.202.01:06:54.19#ibcon#first serial, iclass 13, count 0 2006.202.01:06:54.19#ibcon#enter sib2, iclass 13, count 0 2006.202.01:06:54.19#ibcon#flushed, iclass 13, count 0 2006.202.01:06:54.19#ibcon#about to write, iclass 13, count 0 2006.202.01:06:54.19#ibcon#wrote, iclass 13, count 0 2006.202.01:06:54.19#ibcon#about to read 3, iclass 13, count 0 2006.202.01:06:54.21#ibcon#read 3, iclass 13, count 0 2006.202.01:06:54.21#ibcon#about to read 4, iclass 13, count 0 2006.202.01:06:54.21#ibcon#read 4, iclass 13, count 0 2006.202.01:06:54.21#ibcon#about to read 5, iclass 13, count 0 2006.202.01:06:54.21#ibcon#read 5, iclass 13, count 0 2006.202.01:06:54.21#ibcon#about to read 6, iclass 13, count 0 2006.202.01:06:54.21#ibcon#read 6, iclass 13, count 0 2006.202.01:06:54.21#ibcon#end of sib2, iclass 13, count 0 2006.202.01:06:54.21#ibcon#*mode == 0, iclass 13, count 0 2006.202.01:06:54.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.01:06:54.21#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.01:06:54.21#ibcon#*before write, iclass 13, count 0 2006.202.01:06:54.21#ibcon#enter sib2, iclass 13, count 0 2006.202.01:06:54.21#ibcon#flushed, iclass 13, count 0 2006.202.01:06:54.21#ibcon#about to write, iclass 13, count 0 2006.202.01:06:54.21#ibcon#wrote, iclass 13, count 0 2006.202.01:06:54.21#ibcon#about to read 3, iclass 13, count 0 2006.202.01:06:54.25#ibcon#read 3, iclass 13, count 0 2006.202.01:06:54.25#ibcon#about to read 4, iclass 13, count 0 2006.202.01:06:54.25#ibcon#read 4, iclass 13, count 0 2006.202.01:06:54.25#ibcon#about to read 5, iclass 13, count 0 2006.202.01:06:54.25#ibcon#read 5, iclass 13, count 0 2006.202.01:06:54.25#ibcon#about to read 6, iclass 13, count 0 2006.202.01:06:54.25#ibcon#read 6, iclass 13, count 0 2006.202.01:06:54.25#ibcon#end of sib2, iclass 13, count 0 2006.202.01:06:54.25#ibcon#*after write, iclass 13, count 0 2006.202.01:06:54.25#ibcon#*before return 0, iclass 13, count 0 2006.202.01:06:54.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:06:54.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:06:54.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.01:06:54.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.01:06:54.25$vck44/va=4,7 2006.202.01:06:54.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.202.01:06:54.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.202.01:06:54.25#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:54.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:06:54.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:06:54.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:06:54.31#ibcon#enter wrdev, iclass 15, count 2 2006.202.01:06:54.31#ibcon#first serial, iclass 15, count 2 2006.202.01:06:54.31#ibcon#enter sib2, iclass 15, count 2 2006.202.01:06:54.31#ibcon#flushed, iclass 15, count 2 2006.202.01:06:54.31#ibcon#about to write, iclass 15, count 2 2006.202.01:06:54.31#ibcon#wrote, iclass 15, count 2 2006.202.01:06:54.31#ibcon#about to read 3, iclass 15, count 2 2006.202.01:06:54.33#ibcon#read 3, iclass 15, count 2 2006.202.01:06:54.33#ibcon#about to read 4, iclass 15, count 2 2006.202.01:06:54.33#ibcon#read 4, iclass 15, count 2 2006.202.01:06:54.33#ibcon#about to read 5, iclass 15, count 2 2006.202.01:06:54.33#ibcon#read 5, iclass 15, count 2 2006.202.01:06:54.33#ibcon#about to read 6, iclass 15, count 2 2006.202.01:06:54.33#ibcon#read 6, iclass 15, count 2 2006.202.01:06:54.33#ibcon#end of sib2, iclass 15, count 2 2006.202.01:06:54.33#ibcon#*mode == 0, iclass 15, count 2 2006.202.01:06:54.33#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.202.01:06:54.33#ibcon#[25=AT04-07\r\n] 2006.202.01:06:54.33#ibcon#*before write, iclass 15, count 2 2006.202.01:06:54.33#ibcon#enter sib2, iclass 15, count 2 2006.202.01:06:54.33#ibcon#flushed, iclass 15, count 2 2006.202.01:06:54.33#ibcon#about to write, iclass 15, count 2 2006.202.01:06:54.33#ibcon#wrote, iclass 15, count 2 2006.202.01:06:54.33#ibcon#about to read 3, iclass 15, count 2 2006.202.01:06:54.36#ibcon#read 3, iclass 15, count 2 2006.202.01:06:54.36#ibcon#about to read 4, iclass 15, count 2 2006.202.01:06:54.36#ibcon#read 4, iclass 15, count 2 2006.202.01:06:54.36#ibcon#about to read 5, iclass 15, count 2 2006.202.01:06:54.36#ibcon#read 5, iclass 15, count 2 2006.202.01:06:54.36#ibcon#about to read 6, iclass 15, count 2 2006.202.01:06:54.36#ibcon#read 6, iclass 15, count 2 2006.202.01:06:54.36#ibcon#end of sib2, iclass 15, count 2 2006.202.01:06:54.36#ibcon#*after write, iclass 15, count 2 2006.202.01:06:54.36#ibcon#*before return 0, iclass 15, count 2 2006.202.01:06:54.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:06:54.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:06:54.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.202.01:06:54.36#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:54.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:06:54.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:06:54.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:06:54.48#ibcon#enter wrdev, iclass 15, count 0 2006.202.01:06:54.48#ibcon#first serial, iclass 15, count 0 2006.202.01:06:54.48#ibcon#enter sib2, iclass 15, count 0 2006.202.01:06:54.48#ibcon#flushed, iclass 15, count 0 2006.202.01:06:54.48#ibcon#about to write, iclass 15, count 0 2006.202.01:06:54.48#ibcon#wrote, iclass 15, count 0 2006.202.01:06:54.48#ibcon#about to read 3, iclass 15, count 0 2006.202.01:06:54.50#ibcon#read 3, iclass 15, count 0 2006.202.01:06:54.50#ibcon#about to read 4, iclass 15, count 0 2006.202.01:06:54.50#ibcon#read 4, iclass 15, count 0 2006.202.01:06:54.50#ibcon#about to read 5, iclass 15, count 0 2006.202.01:06:54.50#ibcon#read 5, iclass 15, count 0 2006.202.01:06:54.50#ibcon#about to read 6, iclass 15, count 0 2006.202.01:06:54.50#ibcon#read 6, iclass 15, count 0 2006.202.01:06:54.50#ibcon#end of sib2, iclass 15, count 0 2006.202.01:06:54.50#ibcon#*mode == 0, iclass 15, count 0 2006.202.01:06:54.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.01:06:54.50#ibcon#[25=USB\r\n] 2006.202.01:06:54.50#ibcon#*before write, iclass 15, count 0 2006.202.01:06:54.50#ibcon#enter sib2, iclass 15, count 0 2006.202.01:06:54.50#ibcon#flushed, iclass 15, count 0 2006.202.01:06:54.50#ibcon#about to write, iclass 15, count 0 2006.202.01:06:54.50#ibcon#wrote, iclass 15, count 0 2006.202.01:06:54.50#ibcon#about to read 3, iclass 15, count 0 2006.202.01:06:54.53#ibcon#read 3, iclass 15, count 0 2006.202.01:06:54.53#ibcon#about to read 4, iclass 15, count 0 2006.202.01:06:54.53#ibcon#read 4, iclass 15, count 0 2006.202.01:06:54.53#ibcon#about to read 5, iclass 15, count 0 2006.202.01:06:54.53#ibcon#read 5, iclass 15, count 0 2006.202.01:06:54.53#ibcon#about to read 6, iclass 15, count 0 2006.202.01:06:54.53#ibcon#read 6, iclass 15, count 0 2006.202.01:06:54.53#ibcon#end of sib2, iclass 15, count 0 2006.202.01:06:54.53#ibcon#*after write, iclass 15, count 0 2006.202.01:06:54.53#ibcon#*before return 0, iclass 15, count 0 2006.202.01:06:54.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:06:54.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:06:54.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.01:06:54.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.01:06:54.53$vck44/valo=5,734.99 2006.202.01:06:54.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.01:06:54.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.01:06:54.53#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:54.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:54.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:54.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:54.53#ibcon#enter wrdev, iclass 17, count 0 2006.202.01:06:54.53#ibcon#first serial, iclass 17, count 0 2006.202.01:06:54.53#ibcon#enter sib2, iclass 17, count 0 2006.202.01:06:54.53#ibcon#flushed, iclass 17, count 0 2006.202.01:06:54.53#ibcon#about to write, iclass 17, count 0 2006.202.01:06:54.53#ibcon#wrote, iclass 17, count 0 2006.202.01:06:54.53#ibcon#about to read 3, iclass 17, count 0 2006.202.01:06:54.55#ibcon#read 3, iclass 17, count 0 2006.202.01:06:54.55#ibcon#about to read 4, iclass 17, count 0 2006.202.01:06:54.55#ibcon#read 4, iclass 17, count 0 2006.202.01:06:54.55#ibcon#about to read 5, iclass 17, count 0 2006.202.01:06:54.55#ibcon#read 5, iclass 17, count 0 2006.202.01:06:54.55#ibcon#about to read 6, iclass 17, count 0 2006.202.01:06:54.55#ibcon#read 6, iclass 17, count 0 2006.202.01:06:54.55#ibcon#end of sib2, iclass 17, count 0 2006.202.01:06:54.55#ibcon#*mode == 0, iclass 17, count 0 2006.202.01:06:54.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.01:06:54.55#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.01:06:54.55#ibcon#*before write, iclass 17, count 0 2006.202.01:06:54.55#ibcon#enter sib2, iclass 17, count 0 2006.202.01:06:54.55#ibcon#flushed, iclass 17, count 0 2006.202.01:06:54.55#ibcon#about to write, iclass 17, count 0 2006.202.01:06:54.55#ibcon#wrote, iclass 17, count 0 2006.202.01:06:54.55#ibcon#about to read 3, iclass 17, count 0 2006.202.01:06:54.59#ibcon#read 3, iclass 17, count 0 2006.202.01:06:54.59#ibcon#about to read 4, iclass 17, count 0 2006.202.01:06:54.59#ibcon#read 4, iclass 17, count 0 2006.202.01:06:54.59#ibcon#about to read 5, iclass 17, count 0 2006.202.01:06:54.59#ibcon#read 5, iclass 17, count 0 2006.202.01:06:54.59#ibcon#about to read 6, iclass 17, count 0 2006.202.01:06:54.59#ibcon#read 6, iclass 17, count 0 2006.202.01:06:54.59#ibcon#end of sib2, iclass 17, count 0 2006.202.01:06:54.59#ibcon#*after write, iclass 17, count 0 2006.202.01:06:54.59#ibcon#*before return 0, iclass 17, count 0 2006.202.01:06:54.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:54.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:54.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.01:06:54.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.01:06:54.59$vck44/va=5,4 2006.202.01:06:54.59#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.202.01:06:54.59#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.202.01:06:54.59#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:54.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:54.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:54.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:54.65#ibcon#enter wrdev, iclass 19, count 2 2006.202.01:06:54.65#ibcon#first serial, iclass 19, count 2 2006.202.01:06:54.65#ibcon#enter sib2, iclass 19, count 2 2006.202.01:06:54.65#ibcon#flushed, iclass 19, count 2 2006.202.01:06:54.65#ibcon#about to write, iclass 19, count 2 2006.202.01:06:54.65#ibcon#wrote, iclass 19, count 2 2006.202.01:06:54.65#ibcon#about to read 3, iclass 19, count 2 2006.202.01:06:54.67#ibcon#read 3, iclass 19, count 2 2006.202.01:06:54.67#ibcon#about to read 4, iclass 19, count 2 2006.202.01:06:54.67#ibcon#read 4, iclass 19, count 2 2006.202.01:06:54.67#ibcon#about to read 5, iclass 19, count 2 2006.202.01:06:54.67#ibcon#read 5, iclass 19, count 2 2006.202.01:06:54.67#ibcon#about to read 6, iclass 19, count 2 2006.202.01:06:54.67#ibcon#read 6, iclass 19, count 2 2006.202.01:06:54.67#ibcon#end of sib2, iclass 19, count 2 2006.202.01:06:54.67#ibcon#*mode == 0, iclass 19, count 2 2006.202.01:06:54.67#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.202.01:06:54.67#ibcon#[25=AT05-04\r\n] 2006.202.01:06:54.67#ibcon#*before write, iclass 19, count 2 2006.202.01:06:54.67#ibcon#enter sib2, iclass 19, count 2 2006.202.01:06:54.67#ibcon#flushed, iclass 19, count 2 2006.202.01:06:54.67#ibcon#about to write, iclass 19, count 2 2006.202.01:06:54.67#ibcon#wrote, iclass 19, count 2 2006.202.01:06:54.67#ibcon#about to read 3, iclass 19, count 2 2006.202.01:06:54.70#ibcon#read 3, iclass 19, count 2 2006.202.01:06:54.70#ibcon#about to read 4, iclass 19, count 2 2006.202.01:06:54.70#ibcon#read 4, iclass 19, count 2 2006.202.01:06:54.70#ibcon#about to read 5, iclass 19, count 2 2006.202.01:06:54.70#ibcon#read 5, iclass 19, count 2 2006.202.01:06:54.70#ibcon#about to read 6, iclass 19, count 2 2006.202.01:06:54.70#ibcon#read 6, iclass 19, count 2 2006.202.01:06:54.70#ibcon#end of sib2, iclass 19, count 2 2006.202.01:06:54.70#ibcon#*after write, iclass 19, count 2 2006.202.01:06:54.70#ibcon#*before return 0, iclass 19, count 2 2006.202.01:06:54.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:54.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:54.70#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.202.01:06:54.70#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:54.70#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:54.82#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:54.82#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:54.82#ibcon#enter wrdev, iclass 19, count 0 2006.202.01:06:54.82#ibcon#first serial, iclass 19, count 0 2006.202.01:06:54.82#ibcon#enter sib2, iclass 19, count 0 2006.202.01:06:54.82#ibcon#flushed, iclass 19, count 0 2006.202.01:06:54.82#ibcon#about to write, iclass 19, count 0 2006.202.01:06:54.82#ibcon#wrote, iclass 19, count 0 2006.202.01:06:54.82#ibcon#about to read 3, iclass 19, count 0 2006.202.01:06:54.84#ibcon#read 3, iclass 19, count 0 2006.202.01:06:54.84#ibcon#about to read 4, iclass 19, count 0 2006.202.01:06:54.84#ibcon#read 4, iclass 19, count 0 2006.202.01:06:54.84#ibcon#about to read 5, iclass 19, count 0 2006.202.01:06:54.84#ibcon#read 5, iclass 19, count 0 2006.202.01:06:54.84#ibcon#about to read 6, iclass 19, count 0 2006.202.01:06:54.84#ibcon#read 6, iclass 19, count 0 2006.202.01:06:54.84#ibcon#end of sib2, iclass 19, count 0 2006.202.01:06:54.84#ibcon#*mode == 0, iclass 19, count 0 2006.202.01:06:54.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.01:06:54.84#ibcon#[25=USB\r\n] 2006.202.01:06:54.84#ibcon#*before write, iclass 19, count 0 2006.202.01:06:54.84#ibcon#enter sib2, iclass 19, count 0 2006.202.01:06:54.84#ibcon#flushed, iclass 19, count 0 2006.202.01:06:54.84#ibcon#about to write, iclass 19, count 0 2006.202.01:06:54.84#ibcon#wrote, iclass 19, count 0 2006.202.01:06:54.84#ibcon#about to read 3, iclass 19, count 0 2006.202.01:06:54.87#ibcon#read 3, iclass 19, count 0 2006.202.01:06:54.87#ibcon#about to read 4, iclass 19, count 0 2006.202.01:06:54.87#ibcon#read 4, iclass 19, count 0 2006.202.01:06:54.87#ibcon#about to read 5, iclass 19, count 0 2006.202.01:06:54.87#ibcon#read 5, iclass 19, count 0 2006.202.01:06:54.87#ibcon#about to read 6, iclass 19, count 0 2006.202.01:06:54.87#ibcon#read 6, iclass 19, count 0 2006.202.01:06:54.87#ibcon#end of sib2, iclass 19, count 0 2006.202.01:06:54.87#ibcon#*after write, iclass 19, count 0 2006.202.01:06:54.87#ibcon#*before return 0, iclass 19, count 0 2006.202.01:06:54.87#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:54.87#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:54.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.01:06:54.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.01:06:54.87$vck44/valo=6,814.99 2006.202.01:06:54.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.202.01:06:54.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.202.01:06:54.87#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:54.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:54.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:54.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:54.87#ibcon#enter wrdev, iclass 21, count 0 2006.202.01:06:54.87#ibcon#first serial, iclass 21, count 0 2006.202.01:06:54.87#ibcon#enter sib2, iclass 21, count 0 2006.202.01:06:54.87#ibcon#flushed, iclass 21, count 0 2006.202.01:06:54.87#ibcon#about to write, iclass 21, count 0 2006.202.01:06:54.87#ibcon#wrote, iclass 21, count 0 2006.202.01:06:54.87#ibcon#about to read 3, iclass 21, count 0 2006.202.01:06:54.89#ibcon#read 3, iclass 21, count 0 2006.202.01:06:54.89#ibcon#about to read 4, iclass 21, count 0 2006.202.01:06:54.89#ibcon#read 4, iclass 21, count 0 2006.202.01:06:54.89#ibcon#about to read 5, iclass 21, count 0 2006.202.01:06:54.89#ibcon#read 5, iclass 21, count 0 2006.202.01:06:54.89#ibcon#about to read 6, iclass 21, count 0 2006.202.01:06:54.89#ibcon#read 6, iclass 21, count 0 2006.202.01:06:54.89#ibcon#end of sib2, iclass 21, count 0 2006.202.01:06:54.89#ibcon#*mode == 0, iclass 21, count 0 2006.202.01:06:54.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.01:06:54.89#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.01:06:54.89#ibcon#*before write, iclass 21, count 0 2006.202.01:06:54.89#ibcon#enter sib2, iclass 21, count 0 2006.202.01:06:54.89#ibcon#flushed, iclass 21, count 0 2006.202.01:06:54.89#ibcon#about to write, iclass 21, count 0 2006.202.01:06:54.89#ibcon#wrote, iclass 21, count 0 2006.202.01:06:54.89#ibcon#about to read 3, iclass 21, count 0 2006.202.01:06:54.93#ibcon#read 3, iclass 21, count 0 2006.202.01:06:54.93#ibcon#about to read 4, iclass 21, count 0 2006.202.01:06:54.93#ibcon#read 4, iclass 21, count 0 2006.202.01:06:54.93#ibcon#about to read 5, iclass 21, count 0 2006.202.01:06:54.93#ibcon#read 5, iclass 21, count 0 2006.202.01:06:54.93#ibcon#about to read 6, iclass 21, count 0 2006.202.01:06:54.93#ibcon#read 6, iclass 21, count 0 2006.202.01:06:54.93#ibcon#end of sib2, iclass 21, count 0 2006.202.01:06:54.93#ibcon#*after write, iclass 21, count 0 2006.202.01:06:54.93#ibcon#*before return 0, iclass 21, count 0 2006.202.01:06:54.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:54.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:54.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.01:06:54.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.01:06:54.93$vck44/va=6,5 2006.202.01:06:54.93#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.202.01:06:54.93#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.202.01:06:54.93#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:54.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:54.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:54.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:54.99#ibcon#enter wrdev, iclass 23, count 2 2006.202.01:06:54.99#ibcon#first serial, iclass 23, count 2 2006.202.01:06:54.99#ibcon#enter sib2, iclass 23, count 2 2006.202.01:06:54.99#ibcon#flushed, iclass 23, count 2 2006.202.01:06:54.99#ibcon#about to write, iclass 23, count 2 2006.202.01:06:54.99#ibcon#wrote, iclass 23, count 2 2006.202.01:06:54.99#ibcon#about to read 3, iclass 23, count 2 2006.202.01:06:55.01#ibcon#read 3, iclass 23, count 2 2006.202.01:06:55.01#ibcon#about to read 4, iclass 23, count 2 2006.202.01:06:55.01#ibcon#read 4, iclass 23, count 2 2006.202.01:06:55.01#ibcon#about to read 5, iclass 23, count 2 2006.202.01:06:55.01#ibcon#read 5, iclass 23, count 2 2006.202.01:06:55.01#ibcon#about to read 6, iclass 23, count 2 2006.202.01:06:55.01#ibcon#read 6, iclass 23, count 2 2006.202.01:06:55.01#ibcon#end of sib2, iclass 23, count 2 2006.202.01:06:55.01#ibcon#*mode == 0, iclass 23, count 2 2006.202.01:06:55.01#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.202.01:06:55.01#ibcon#[25=AT06-05\r\n] 2006.202.01:06:55.01#ibcon#*before write, iclass 23, count 2 2006.202.01:06:55.01#ibcon#enter sib2, iclass 23, count 2 2006.202.01:06:55.01#ibcon#flushed, iclass 23, count 2 2006.202.01:06:55.01#ibcon#about to write, iclass 23, count 2 2006.202.01:06:55.01#ibcon#wrote, iclass 23, count 2 2006.202.01:06:55.01#ibcon#about to read 3, iclass 23, count 2 2006.202.01:06:55.04#ibcon#read 3, iclass 23, count 2 2006.202.01:06:55.04#ibcon#about to read 4, iclass 23, count 2 2006.202.01:06:55.04#ibcon#read 4, iclass 23, count 2 2006.202.01:06:55.04#ibcon#about to read 5, iclass 23, count 2 2006.202.01:06:55.04#ibcon#read 5, iclass 23, count 2 2006.202.01:06:55.04#ibcon#about to read 6, iclass 23, count 2 2006.202.01:06:55.04#ibcon#read 6, iclass 23, count 2 2006.202.01:06:55.04#ibcon#end of sib2, iclass 23, count 2 2006.202.01:06:55.04#ibcon#*after write, iclass 23, count 2 2006.202.01:06:55.04#ibcon#*before return 0, iclass 23, count 2 2006.202.01:06:55.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:55.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:55.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.202.01:06:55.04#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:55.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:55.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:55.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:55.16#ibcon#enter wrdev, iclass 23, count 0 2006.202.01:06:55.16#ibcon#first serial, iclass 23, count 0 2006.202.01:06:55.16#ibcon#enter sib2, iclass 23, count 0 2006.202.01:06:55.16#ibcon#flushed, iclass 23, count 0 2006.202.01:06:55.16#ibcon#about to write, iclass 23, count 0 2006.202.01:06:55.16#ibcon#wrote, iclass 23, count 0 2006.202.01:06:55.16#ibcon#about to read 3, iclass 23, count 0 2006.202.01:06:55.18#ibcon#read 3, iclass 23, count 0 2006.202.01:06:55.18#ibcon#about to read 4, iclass 23, count 0 2006.202.01:06:55.18#ibcon#read 4, iclass 23, count 0 2006.202.01:06:55.18#ibcon#about to read 5, iclass 23, count 0 2006.202.01:06:55.18#ibcon#read 5, iclass 23, count 0 2006.202.01:06:55.18#ibcon#about to read 6, iclass 23, count 0 2006.202.01:06:55.18#ibcon#read 6, iclass 23, count 0 2006.202.01:06:55.18#ibcon#end of sib2, iclass 23, count 0 2006.202.01:06:55.18#ibcon#*mode == 0, iclass 23, count 0 2006.202.01:06:55.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.01:06:55.18#ibcon#[25=USB\r\n] 2006.202.01:06:55.18#ibcon#*before write, iclass 23, count 0 2006.202.01:06:55.18#ibcon#enter sib2, iclass 23, count 0 2006.202.01:06:55.18#ibcon#flushed, iclass 23, count 0 2006.202.01:06:55.18#ibcon#about to write, iclass 23, count 0 2006.202.01:06:55.18#ibcon#wrote, iclass 23, count 0 2006.202.01:06:55.18#ibcon#about to read 3, iclass 23, count 0 2006.202.01:06:55.21#ibcon#read 3, iclass 23, count 0 2006.202.01:06:55.21#ibcon#about to read 4, iclass 23, count 0 2006.202.01:06:55.21#ibcon#read 4, iclass 23, count 0 2006.202.01:06:55.21#ibcon#about to read 5, iclass 23, count 0 2006.202.01:06:55.21#ibcon#read 5, iclass 23, count 0 2006.202.01:06:55.21#ibcon#about to read 6, iclass 23, count 0 2006.202.01:06:55.21#ibcon#read 6, iclass 23, count 0 2006.202.01:06:55.21#ibcon#end of sib2, iclass 23, count 0 2006.202.01:06:55.21#ibcon#*after write, iclass 23, count 0 2006.202.01:06:55.21#ibcon#*before return 0, iclass 23, count 0 2006.202.01:06:55.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:55.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:55.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.01:06:55.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.01:06:55.21$vck44/valo=7,864.99 2006.202.01:06:55.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.202.01:06:55.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.202.01:06:55.21#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:55.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:55.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:55.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:55.21#ibcon#enter wrdev, iclass 25, count 0 2006.202.01:06:55.21#ibcon#first serial, iclass 25, count 0 2006.202.01:06:55.21#ibcon#enter sib2, iclass 25, count 0 2006.202.01:06:55.21#ibcon#flushed, iclass 25, count 0 2006.202.01:06:55.21#ibcon#about to write, iclass 25, count 0 2006.202.01:06:55.21#ibcon#wrote, iclass 25, count 0 2006.202.01:06:55.21#ibcon#about to read 3, iclass 25, count 0 2006.202.01:06:55.23#ibcon#read 3, iclass 25, count 0 2006.202.01:06:55.23#ibcon#about to read 4, iclass 25, count 0 2006.202.01:06:55.23#ibcon#read 4, iclass 25, count 0 2006.202.01:06:55.23#ibcon#about to read 5, iclass 25, count 0 2006.202.01:06:55.23#ibcon#read 5, iclass 25, count 0 2006.202.01:06:55.23#ibcon#about to read 6, iclass 25, count 0 2006.202.01:06:55.23#ibcon#read 6, iclass 25, count 0 2006.202.01:06:55.23#ibcon#end of sib2, iclass 25, count 0 2006.202.01:06:55.23#ibcon#*mode == 0, iclass 25, count 0 2006.202.01:06:55.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.01:06:55.23#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.01:06:55.23#ibcon#*before write, iclass 25, count 0 2006.202.01:06:55.23#ibcon#enter sib2, iclass 25, count 0 2006.202.01:06:55.23#ibcon#flushed, iclass 25, count 0 2006.202.01:06:55.23#ibcon#about to write, iclass 25, count 0 2006.202.01:06:55.23#ibcon#wrote, iclass 25, count 0 2006.202.01:06:55.23#ibcon#about to read 3, iclass 25, count 0 2006.202.01:06:55.27#ibcon#read 3, iclass 25, count 0 2006.202.01:06:55.27#ibcon#about to read 4, iclass 25, count 0 2006.202.01:06:55.27#ibcon#read 4, iclass 25, count 0 2006.202.01:06:55.27#ibcon#about to read 5, iclass 25, count 0 2006.202.01:06:55.27#ibcon#read 5, iclass 25, count 0 2006.202.01:06:55.27#ibcon#about to read 6, iclass 25, count 0 2006.202.01:06:55.27#ibcon#read 6, iclass 25, count 0 2006.202.01:06:55.27#ibcon#end of sib2, iclass 25, count 0 2006.202.01:06:55.27#ibcon#*after write, iclass 25, count 0 2006.202.01:06:55.27#ibcon#*before return 0, iclass 25, count 0 2006.202.01:06:55.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:55.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:55.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.01:06:55.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.01:06:55.27$vck44/va=7,5 2006.202.01:06:55.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.202.01:06:55.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.202.01:06:55.27#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:55.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:55.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:55.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:55.33#ibcon#enter wrdev, iclass 27, count 2 2006.202.01:06:55.33#ibcon#first serial, iclass 27, count 2 2006.202.01:06:55.33#ibcon#enter sib2, iclass 27, count 2 2006.202.01:06:55.33#ibcon#flushed, iclass 27, count 2 2006.202.01:06:55.33#ibcon#about to write, iclass 27, count 2 2006.202.01:06:55.33#ibcon#wrote, iclass 27, count 2 2006.202.01:06:55.33#ibcon#about to read 3, iclass 27, count 2 2006.202.01:06:55.35#ibcon#read 3, iclass 27, count 2 2006.202.01:06:55.35#ibcon#about to read 4, iclass 27, count 2 2006.202.01:06:55.35#ibcon#read 4, iclass 27, count 2 2006.202.01:06:55.35#ibcon#about to read 5, iclass 27, count 2 2006.202.01:06:55.35#ibcon#read 5, iclass 27, count 2 2006.202.01:06:55.35#ibcon#about to read 6, iclass 27, count 2 2006.202.01:06:55.35#ibcon#read 6, iclass 27, count 2 2006.202.01:06:55.35#ibcon#end of sib2, iclass 27, count 2 2006.202.01:06:55.35#ibcon#*mode == 0, iclass 27, count 2 2006.202.01:06:55.35#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.202.01:06:55.35#ibcon#[25=AT07-05\r\n] 2006.202.01:06:55.35#ibcon#*before write, iclass 27, count 2 2006.202.01:06:55.35#ibcon#enter sib2, iclass 27, count 2 2006.202.01:06:55.35#ibcon#flushed, iclass 27, count 2 2006.202.01:06:55.35#ibcon#about to write, iclass 27, count 2 2006.202.01:06:55.35#ibcon#wrote, iclass 27, count 2 2006.202.01:06:55.35#ibcon#about to read 3, iclass 27, count 2 2006.202.01:06:55.38#ibcon#read 3, iclass 27, count 2 2006.202.01:06:55.38#ibcon#about to read 4, iclass 27, count 2 2006.202.01:06:55.38#ibcon#read 4, iclass 27, count 2 2006.202.01:06:55.38#ibcon#about to read 5, iclass 27, count 2 2006.202.01:06:55.38#ibcon#read 5, iclass 27, count 2 2006.202.01:06:55.38#ibcon#about to read 6, iclass 27, count 2 2006.202.01:06:55.38#ibcon#read 6, iclass 27, count 2 2006.202.01:06:55.38#ibcon#end of sib2, iclass 27, count 2 2006.202.01:06:55.38#ibcon#*after write, iclass 27, count 2 2006.202.01:06:55.38#ibcon#*before return 0, iclass 27, count 2 2006.202.01:06:55.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:55.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:55.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.202.01:06:55.38#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:55.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:55.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:55.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:55.50#ibcon#enter wrdev, iclass 27, count 0 2006.202.01:06:55.50#ibcon#first serial, iclass 27, count 0 2006.202.01:06:55.50#ibcon#enter sib2, iclass 27, count 0 2006.202.01:06:55.50#ibcon#flushed, iclass 27, count 0 2006.202.01:06:55.50#ibcon#about to write, iclass 27, count 0 2006.202.01:06:55.50#ibcon#wrote, iclass 27, count 0 2006.202.01:06:55.50#ibcon#about to read 3, iclass 27, count 0 2006.202.01:06:55.52#ibcon#read 3, iclass 27, count 0 2006.202.01:06:55.52#ibcon#about to read 4, iclass 27, count 0 2006.202.01:06:55.52#ibcon#read 4, iclass 27, count 0 2006.202.01:06:55.52#ibcon#about to read 5, iclass 27, count 0 2006.202.01:06:55.52#ibcon#read 5, iclass 27, count 0 2006.202.01:06:55.52#ibcon#about to read 6, iclass 27, count 0 2006.202.01:06:55.52#ibcon#read 6, iclass 27, count 0 2006.202.01:06:55.52#ibcon#end of sib2, iclass 27, count 0 2006.202.01:06:55.52#ibcon#*mode == 0, iclass 27, count 0 2006.202.01:06:55.52#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.01:06:55.52#ibcon#[25=USB\r\n] 2006.202.01:06:55.52#ibcon#*before write, iclass 27, count 0 2006.202.01:06:55.52#ibcon#enter sib2, iclass 27, count 0 2006.202.01:06:55.52#ibcon#flushed, iclass 27, count 0 2006.202.01:06:55.52#ibcon#about to write, iclass 27, count 0 2006.202.01:06:55.52#ibcon#wrote, iclass 27, count 0 2006.202.01:06:55.52#ibcon#about to read 3, iclass 27, count 0 2006.202.01:06:55.55#ibcon#read 3, iclass 27, count 0 2006.202.01:06:55.55#ibcon#about to read 4, iclass 27, count 0 2006.202.01:06:55.55#ibcon#read 4, iclass 27, count 0 2006.202.01:06:55.55#ibcon#about to read 5, iclass 27, count 0 2006.202.01:06:55.55#ibcon#read 5, iclass 27, count 0 2006.202.01:06:55.55#ibcon#about to read 6, iclass 27, count 0 2006.202.01:06:55.55#ibcon#read 6, iclass 27, count 0 2006.202.01:06:55.55#ibcon#end of sib2, iclass 27, count 0 2006.202.01:06:55.55#ibcon#*after write, iclass 27, count 0 2006.202.01:06:55.55#ibcon#*before return 0, iclass 27, count 0 2006.202.01:06:55.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:55.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:55.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.01:06:55.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.01:06:55.55$vck44/valo=8,884.99 2006.202.01:06:55.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.202.01:06:55.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.202.01:06:55.55#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:55.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:55.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:55.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:55.55#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:06:55.55#ibcon#first serial, iclass 29, count 0 2006.202.01:06:55.55#ibcon#enter sib2, iclass 29, count 0 2006.202.01:06:55.55#ibcon#flushed, iclass 29, count 0 2006.202.01:06:55.55#ibcon#about to write, iclass 29, count 0 2006.202.01:06:55.55#ibcon#wrote, iclass 29, count 0 2006.202.01:06:55.55#ibcon#about to read 3, iclass 29, count 0 2006.202.01:06:55.57#ibcon#read 3, iclass 29, count 0 2006.202.01:06:55.57#ibcon#about to read 4, iclass 29, count 0 2006.202.01:06:55.57#ibcon#read 4, iclass 29, count 0 2006.202.01:06:55.57#ibcon#about to read 5, iclass 29, count 0 2006.202.01:06:55.57#ibcon#read 5, iclass 29, count 0 2006.202.01:06:55.57#ibcon#about to read 6, iclass 29, count 0 2006.202.01:06:55.57#ibcon#read 6, iclass 29, count 0 2006.202.01:06:55.57#ibcon#end of sib2, iclass 29, count 0 2006.202.01:06:55.57#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:06:55.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:06:55.57#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.01:06:55.57#ibcon#*before write, iclass 29, count 0 2006.202.01:06:55.57#ibcon#enter sib2, iclass 29, count 0 2006.202.01:06:55.57#ibcon#flushed, iclass 29, count 0 2006.202.01:06:55.57#ibcon#about to write, iclass 29, count 0 2006.202.01:06:55.57#ibcon#wrote, iclass 29, count 0 2006.202.01:06:55.57#ibcon#about to read 3, iclass 29, count 0 2006.202.01:06:55.61#ibcon#read 3, iclass 29, count 0 2006.202.01:06:55.61#ibcon#about to read 4, iclass 29, count 0 2006.202.01:06:55.61#ibcon#read 4, iclass 29, count 0 2006.202.01:06:55.61#ibcon#about to read 5, iclass 29, count 0 2006.202.01:06:55.61#ibcon#read 5, iclass 29, count 0 2006.202.01:06:55.61#ibcon#about to read 6, iclass 29, count 0 2006.202.01:06:55.61#ibcon#read 6, iclass 29, count 0 2006.202.01:06:55.61#ibcon#end of sib2, iclass 29, count 0 2006.202.01:06:55.61#ibcon#*after write, iclass 29, count 0 2006.202.01:06:55.61#ibcon#*before return 0, iclass 29, count 0 2006.202.01:06:55.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:55.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:55.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:06:55.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:06:55.61$vck44/va=8,4 2006.202.01:06:55.61#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.202.01:06:55.61#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.202.01:06:55.61#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:55.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:55.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:55.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:55.67#ibcon#enter wrdev, iclass 31, count 2 2006.202.01:06:55.67#ibcon#first serial, iclass 31, count 2 2006.202.01:06:55.67#ibcon#enter sib2, iclass 31, count 2 2006.202.01:06:55.67#ibcon#flushed, iclass 31, count 2 2006.202.01:06:55.67#ibcon#about to write, iclass 31, count 2 2006.202.01:06:55.67#ibcon#wrote, iclass 31, count 2 2006.202.01:06:55.67#ibcon#about to read 3, iclass 31, count 2 2006.202.01:06:55.69#ibcon#read 3, iclass 31, count 2 2006.202.01:06:55.69#ibcon#about to read 4, iclass 31, count 2 2006.202.01:06:55.69#ibcon#read 4, iclass 31, count 2 2006.202.01:06:55.69#ibcon#about to read 5, iclass 31, count 2 2006.202.01:06:55.69#ibcon#read 5, iclass 31, count 2 2006.202.01:06:55.69#ibcon#about to read 6, iclass 31, count 2 2006.202.01:06:55.69#ibcon#read 6, iclass 31, count 2 2006.202.01:06:55.69#ibcon#end of sib2, iclass 31, count 2 2006.202.01:06:55.69#ibcon#*mode == 0, iclass 31, count 2 2006.202.01:06:55.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.202.01:06:55.69#ibcon#[25=AT08-04\r\n] 2006.202.01:06:55.69#ibcon#*before write, iclass 31, count 2 2006.202.01:06:55.69#ibcon#enter sib2, iclass 31, count 2 2006.202.01:06:55.69#ibcon#flushed, iclass 31, count 2 2006.202.01:06:55.69#ibcon#about to write, iclass 31, count 2 2006.202.01:06:55.69#ibcon#wrote, iclass 31, count 2 2006.202.01:06:55.69#ibcon#about to read 3, iclass 31, count 2 2006.202.01:06:55.72#ibcon#read 3, iclass 31, count 2 2006.202.01:06:55.72#ibcon#about to read 4, iclass 31, count 2 2006.202.01:06:55.72#ibcon#read 4, iclass 31, count 2 2006.202.01:06:55.72#ibcon#about to read 5, iclass 31, count 2 2006.202.01:06:55.72#ibcon#read 5, iclass 31, count 2 2006.202.01:06:55.72#ibcon#about to read 6, iclass 31, count 2 2006.202.01:06:55.72#ibcon#read 6, iclass 31, count 2 2006.202.01:06:55.72#ibcon#end of sib2, iclass 31, count 2 2006.202.01:06:55.72#ibcon#*after write, iclass 31, count 2 2006.202.01:06:55.72#ibcon#*before return 0, iclass 31, count 2 2006.202.01:06:55.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:55.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:55.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.202.01:06:55.72#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:55.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:55.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:55.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:55.84#ibcon#enter wrdev, iclass 31, count 0 2006.202.01:06:55.84#ibcon#first serial, iclass 31, count 0 2006.202.01:06:55.84#ibcon#enter sib2, iclass 31, count 0 2006.202.01:06:55.84#ibcon#flushed, iclass 31, count 0 2006.202.01:06:55.84#ibcon#about to write, iclass 31, count 0 2006.202.01:06:55.84#ibcon#wrote, iclass 31, count 0 2006.202.01:06:55.84#ibcon#about to read 3, iclass 31, count 0 2006.202.01:06:55.86#ibcon#read 3, iclass 31, count 0 2006.202.01:06:55.86#ibcon#about to read 4, iclass 31, count 0 2006.202.01:06:55.86#ibcon#read 4, iclass 31, count 0 2006.202.01:06:55.86#ibcon#about to read 5, iclass 31, count 0 2006.202.01:06:55.86#ibcon#read 5, iclass 31, count 0 2006.202.01:06:55.86#ibcon#about to read 6, iclass 31, count 0 2006.202.01:06:55.86#ibcon#read 6, iclass 31, count 0 2006.202.01:06:55.86#ibcon#end of sib2, iclass 31, count 0 2006.202.01:06:55.86#ibcon#*mode == 0, iclass 31, count 0 2006.202.01:06:55.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.01:06:55.86#ibcon#[25=USB\r\n] 2006.202.01:06:55.86#ibcon#*before write, iclass 31, count 0 2006.202.01:06:55.86#ibcon#enter sib2, iclass 31, count 0 2006.202.01:06:55.86#ibcon#flushed, iclass 31, count 0 2006.202.01:06:55.86#ibcon#about to write, iclass 31, count 0 2006.202.01:06:55.86#ibcon#wrote, iclass 31, count 0 2006.202.01:06:55.86#ibcon#about to read 3, iclass 31, count 0 2006.202.01:06:55.89#ibcon#read 3, iclass 31, count 0 2006.202.01:06:55.89#ibcon#about to read 4, iclass 31, count 0 2006.202.01:06:55.89#ibcon#read 4, iclass 31, count 0 2006.202.01:06:55.89#ibcon#about to read 5, iclass 31, count 0 2006.202.01:06:55.89#ibcon#read 5, iclass 31, count 0 2006.202.01:06:55.89#ibcon#about to read 6, iclass 31, count 0 2006.202.01:06:55.89#ibcon#read 6, iclass 31, count 0 2006.202.01:06:55.89#ibcon#end of sib2, iclass 31, count 0 2006.202.01:06:55.89#ibcon#*after write, iclass 31, count 0 2006.202.01:06:55.89#ibcon#*before return 0, iclass 31, count 0 2006.202.01:06:55.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:55.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:55.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.01:06:55.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.01:06:55.89$vck44/vblo=1,629.99 2006.202.01:06:55.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.01:06:55.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.01:06:55.89#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:55.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:55.89#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:55.89#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:55.89#ibcon#enter wrdev, iclass 33, count 0 2006.202.01:06:55.89#ibcon#first serial, iclass 33, count 0 2006.202.01:06:55.89#ibcon#enter sib2, iclass 33, count 0 2006.202.01:06:55.89#ibcon#flushed, iclass 33, count 0 2006.202.01:06:55.89#ibcon#about to write, iclass 33, count 0 2006.202.01:06:55.89#ibcon#wrote, iclass 33, count 0 2006.202.01:06:55.89#ibcon#about to read 3, iclass 33, count 0 2006.202.01:06:55.91#ibcon#read 3, iclass 33, count 0 2006.202.01:06:55.91#ibcon#about to read 4, iclass 33, count 0 2006.202.01:06:55.91#ibcon#read 4, iclass 33, count 0 2006.202.01:06:55.91#ibcon#about to read 5, iclass 33, count 0 2006.202.01:06:55.91#ibcon#read 5, iclass 33, count 0 2006.202.01:06:55.91#ibcon#about to read 6, iclass 33, count 0 2006.202.01:06:55.91#ibcon#read 6, iclass 33, count 0 2006.202.01:06:55.91#ibcon#end of sib2, iclass 33, count 0 2006.202.01:06:55.91#ibcon#*mode == 0, iclass 33, count 0 2006.202.01:06:55.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.01:06:55.91#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.01:06:55.91#ibcon#*before write, iclass 33, count 0 2006.202.01:06:55.91#ibcon#enter sib2, iclass 33, count 0 2006.202.01:06:55.91#ibcon#flushed, iclass 33, count 0 2006.202.01:06:55.91#ibcon#about to write, iclass 33, count 0 2006.202.01:06:55.91#ibcon#wrote, iclass 33, count 0 2006.202.01:06:55.91#ibcon#about to read 3, iclass 33, count 0 2006.202.01:06:55.95#ibcon#read 3, iclass 33, count 0 2006.202.01:06:55.95#ibcon#about to read 4, iclass 33, count 0 2006.202.01:06:55.95#ibcon#read 4, iclass 33, count 0 2006.202.01:06:55.95#ibcon#about to read 5, iclass 33, count 0 2006.202.01:06:55.95#ibcon#read 5, iclass 33, count 0 2006.202.01:06:55.95#ibcon#about to read 6, iclass 33, count 0 2006.202.01:06:55.95#ibcon#read 6, iclass 33, count 0 2006.202.01:06:55.95#ibcon#end of sib2, iclass 33, count 0 2006.202.01:06:55.95#ibcon#*after write, iclass 33, count 0 2006.202.01:06:55.95#ibcon#*before return 0, iclass 33, count 0 2006.202.01:06:55.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:55.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:55.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.01:06:55.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.01:06:55.95$vck44/vb=1,4 2006.202.01:06:55.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.202.01:06:55.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.202.01:06:55.95#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:55.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:06:55.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:06:55.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:06:55.95#ibcon#enter wrdev, iclass 35, count 2 2006.202.01:06:55.95#ibcon#first serial, iclass 35, count 2 2006.202.01:06:55.95#ibcon#enter sib2, iclass 35, count 2 2006.202.01:06:55.95#ibcon#flushed, iclass 35, count 2 2006.202.01:06:55.95#ibcon#about to write, iclass 35, count 2 2006.202.01:06:55.95#ibcon#wrote, iclass 35, count 2 2006.202.01:06:55.95#ibcon#about to read 3, iclass 35, count 2 2006.202.01:06:55.97#ibcon#read 3, iclass 35, count 2 2006.202.01:06:55.97#ibcon#about to read 4, iclass 35, count 2 2006.202.01:06:55.97#ibcon#read 4, iclass 35, count 2 2006.202.01:06:55.97#ibcon#about to read 5, iclass 35, count 2 2006.202.01:06:55.97#ibcon#read 5, iclass 35, count 2 2006.202.01:06:55.97#ibcon#about to read 6, iclass 35, count 2 2006.202.01:06:55.97#ibcon#read 6, iclass 35, count 2 2006.202.01:06:55.97#ibcon#end of sib2, iclass 35, count 2 2006.202.01:06:55.97#ibcon#*mode == 0, iclass 35, count 2 2006.202.01:06:55.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.202.01:06:55.97#ibcon#[27=AT01-04\r\n] 2006.202.01:06:55.97#ibcon#*before write, iclass 35, count 2 2006.202.01:06:55.97#ibcon#enter sib2, iclass 35, count 2 2006.202.01:06:55.97#ibcon#flushed, iclass 35, count 2 2006.202.01:06:55.97#ibcon#about to write, iclass 35, count 2 2006.202.01:06:55.97#ibcon#wrote, iclass 35, count 2 2006.202.01:06:55.97#ibcon#about to read 3, iclass 35, count 2 2006.202.01:06:56.00#ibcon#read 3, iclass 35, count 2 2006.202.01:06:56.00#ibcon#about to read 4, iclass 35, count 2 2006.202.01:06:56.00#ibcon#read 4, iclass 35, count 2 2006.202.01:06:56.00#ibcon#about to read 5, iclass 35, count 2 2006.202.01:06:56.00#ibcon#read 5, iclass 35, count 2 2006.202.01:06:56.00#ibcon#about to read 6, iclass 35, count 2 2006.202.01:06:56.00#ibcon#read 6, iclass 35, count 2 2006.202.01:06:56.00#ibcon#end of sib2, iclass 35, count 2 2006.202.01:06:56.00#ibcon#*after write, iclass 35, count 2 2006.202.01:06:56.00#ibcon#*before return 0, iclass 35, count 2 2006.202.01:06:56.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:06:56.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:06:56.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.202.01:06:56.00#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:56.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:06:56.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:06:56.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:06:56.12#ibcon#enter wrdev, iclass 35, count 0 2006.202.01:06:56.12#ibcon#first serial, iclass 35, count 0 2006.202.01:06:56.12#ibcon#enter sib2, iclass 35, count 0 2006.202.01:06:56.12#ibcon#flushed, iclass 35, count 0 2006.202.01:06:56.12#ibcon#about to write, iclass 35, count 0 2006.202.01:06:56.12#ibcon#wrote, iclass 35, count 0 2006.202.01:06:56.12#ibcon#about to read 3, iclass 35, count 0 2006.202.01:06:56.14#ibcon#read 3, iclass 35, count 0 2006.202.01:06:56.14#ibcon#about to read 4, iclass 35, count 0 2006.202.01:06:56.14#ibcon#read 4, iclass 35, count 0 2006.202.01:06:56.14#ibcon#about to read 5, iclass 35, count 0 2006.202.01:06:56.14#ibcon#read 5, iclass 35, count 0 2006.202.01:06:56.14#ibcon#about to read 6, iclass 35, count 0 2006.202.01:06:56.14#ibcon#read 6, iclass 35, count 0 2006.202.01:06:56.14#ibcon#end of sib2, iclass 35, count 0 2006.202.01:06:56.14#ibcon#*mode == 0, iclass 35, count 0 2006.202.01:06:56.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.01:06:56.14#ibcon#[27=USB\r\n] 2006.202.01:06:56.14#ibcon#*before write, iclass 35, count 0 2006.202.01:06:56.14#ibcon#enter sib2, iclass 35, count 0 2006.202.01:06:56.14#ibcon#flushed, iclass 35, count 0 2006.202.01:06:56.14#ibcon#about to write, iclass 35, count 0 2006.202.01:06:56.14#ibcon#wrote, iclass 35, count 0 2006.202.01:06:56.14#ibcon#about to read 3, iclass 35, count 0 2006.202.01:06:56.17#ibcon#read 3, iclass 35, count 0 2006.202.01:06:56.17#ibcon#about to read 4, iclass 35, count 0 2006.202.01:06:56.17#ibcon#read 4, iclass 35, count 0 2006.202.01:06:56.17#ibcon#about to read 5, iclass 35, count 0 2006.202.01:06:56.17#ibcon#read 5, iclass 35, count 0 2006.202.01:06:56.17#ibcon#about to read 6, iclass 35, count 0 2006.202.01:06:56.17#ibcon#read 6, iclass 35, count 0 2006.202.01:06:56.17#ibcon#end of sib2, iclass 35, count 0 2006.202.01:06:56.17#ibcon#*after write, iclass 35, count 0 2006.202.01:06:56.17#ibcon#*before return 0, iclass 35, count 0 2006.202.01:06:56.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:06:56.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:06:56.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.01:06:56.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.01:06:56.17$vck44/vblo=2,634.99 2006.202.01:06:56.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.202.01:06:56.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.202.01:06:56.17#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:56.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:56.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:56.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:56.17#ibcon#enter wrdev, iclass 37, count 0 2006.202.01:06:56.17#ibcon#first serial, iclass 37, count 0 2006.202.01:06:56.17#ibcon#enter sib2, iclass 37, count 0 2006.202.01:06:56.17#ibcon#flushed, iclass 37, count 0 2006.202.01:06:56.17#ibcon#about to write, iclass 37, count 0 2006.202.01:06:56.17#ibcon#wrote, iclass 37, count 0 2006.202.01:06:56.17#ibcon#about to read 3, iclass 37, count 0 2006.202.01:06:56.19#ibcon#read 3, iclass 37, count 0 2006.202.01:06:56.19#ibcon#about to read 4, iclass 37, count 0 2006.202.01:06:56.19#ibcon#read 4, iclass 37, count 0 2006.202.01:06:56.19#ibcon#about to read 5, iclass 37, count 0 2006.202.01:06:56.19#ibcon#read 5, iclass 37, count 0 2006.202.01:06:56.19#ibcon#about to read 6, iclass 37, count 0 2006.202.01:06:56.19#ibcon#read 6, iclass 37, count 0 2006.202.01:06:56.19#ibcon#end of sib2, iclass 37, count 0 2006.202.01:06:56.19#ibcon#*mode == 0, iclass 37, count 0 2006.202.01:06:56.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.01:06:56.19#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.01:06:56.19#ibcon#*before write, iclass 37, count 0 2006.202.01:06:56.19#ibcon#enter sib2, iclass 37, count 0 2006.202.01:06:56.19#ibcon#flushed, iclass 37, count 0 2006.202.01:06:56.19#ibcon#about to write, iclass 37, count 0 2006.202.01:06:56.19#ibcon#wrote, iclass 37, count 0 2006.202.01:06:56.19#ibcon#about to read 3, iclass 37, count 0 2006.202.01:06:56.23#ibcon#read 3, iclass 37, count 0 2006.202.01:06:56.23#ibcon#about to read 4, iclass 37, count 0 2006.202.01:06:56.23#ibcon#read 4, iclass 37, count 0 2006.202.01:06:56.23#ibcon#about to read 5, iclass 37, count 0 2006.202.01:06:56.23#ibcon#read 5, iclass 37, count 0 2006.202.01:06:56.23#ibcon#about to read 6, iclass 37, count 0 2006.202.01:06:56.23#ibcon#read 6, iclass 37, count 0 2006.202.01:06:56.23#ibcon#end of sib2, iclass 37, count 0 2006.202.01:06:56.23#ibcon#*after write, iclass 37, count 0 2006.202.01:06:56.23#ibcon#*before return 0, iclass 37, count 0 2006.202.01:06:56.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:56.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:06:56.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.01:06:56.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.01:06:56.23$vck44/vb=2,5 2006.202.01:06:56.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.202.01:06:56.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.202.01:06:56.23#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:56.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:56.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:56.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:56.29#ibcon#enter wrdev, iclass 39, count 2 2006.202.01:06:56.29#ibcon#first serial, iclass 39, count 2 2006.202.01:06:56.29#ibcon#enter sib2, iclass 39, count 2 2006.202.01:06:56.29#ibcon#flushed, iclass 39, count 2 2006.202.01:06:56.29#ibcon#about to write, iclass 39, count 2 2006.202.01:06:56.29#ibcon#wrote, iclass 39, count 2 2006.202.01:06:56.29#ibcon#about to read 3, iclass 39, count 2 2006.202.01:06:56.31#ibcon#read 3, iclass 39, count 2 2006.202.01:06:56.31#ibcon#about to read 4, iclass 39, count 2 2006.202.01:06:56.31#ibcon#read 4, iclass 39, count 2 2006.202.01:06:56.31#ibcon#about to read 5, iclass 39, count 2 2006.202.01:06:56.31#ibcon#read 5, iclass 39, count 2 2006.202.01:06:56.31#ibcon#about to read 6, iclass 39, count 2 2006.202.01:06:56.31#ibcon#read 6, iclass 39, count 2 2006.202.01:06:56.31#ibcon#end of sib2, iclass 39, count 2 2006.202.01:06:56.31#ibcon#*mode == 0, iclass 39, count 2 2006.202.01:06:56.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.202.01:06:56.31#ibcon#[27=AT02-05\r\n] 2006.202.01:06:56.31#ibcon#*before write, iclass 39, count 2 2006.202.01:06:56.31#ibcon#enter sib2, iclass 39, count 2 2006.202.01:06:56.31#ibcon#flushed, iclass 39, count 2 2006.202.01:06:56.31#ibcon#about to write, iclass 39, count 2 2006.202.01:06:56.31#ibcon#wrote, iclass 39, count 2 2006.202.01:06:56.31#ibcon#about to read 3, iclass 39, count 2 2006.202.01:06:56.34#ibcon#read 3, iclass 39, count 2 2006.202.01:06:56.34#ibcon#about to read 4, iclass 39, count 2 2006.202.01:06:56.34#ibcon#read 4, iclass 39, count 2 2006.202.01:06:56.34#ibcon#about to read 5, iclass 39, count 2 2006.202.01:06:56.34#ibcon#read 5, iclass 39, count 2 2006.202.01:06:56.34#ibcon#about to read 6, iclass 39, count 2 2006.202.01:06:56.34#ibcon#read 6, iclass 39, count 2 2006.202.01:06:56.34#ibcon#end of sib2, iclass 39, count 2 2006.202.01:06:56.34#ibcon#*after write, iclass 39, count 2 2006.202.01:06:56.34#ibcon#*before return 0, iclass 39, count 2 2006.202.01:06:56.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:56.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:06:56.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.202.01:06:56.34#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:56.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:56.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:56.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:56.46#ibcon#enter wrdev, iclass 39, count 0 2006.202.01:06:56.46#ibcon#first serial, iclass 39, count 0 2006.202.01:06:56.46#ibcon#enter sib2, iclass 39, count 0 2006.202.01:06:56.46#ibcon#flushed, iclass 39, count 0 2006.202.01:06:56.46#ibcon#about to write, iclass 39, count 0 2006.202.01:06:56.46#ibcon#wrote, iclass 39, count 0 2006.202.01:06:56.46#ibcon#about to read 3, iclass 39, count 0 2006.202.01:06:56.48#ibcon#read 3, iclass 39, count 0 2006.202.01:06:56.48#ibcon#about to read 4, iclass 39, count 0 2006.202.01:06:56.48#ibcon#read 4, iclass 39, count 0 2006.202.01:06:56.48#ibcon#about to read 5, iclass 39, count 0 2006.202.01:06:56.48#ibcon#read 5, iclass 39, count 0 2006.202.01:06:56.48#ibcon#about to read 6, iclass 39, count 0 2006.202.01:06:56.48#ibcon#read 6, iclass 39, count 0 2006.202.01:06:56.48#ibcon#end of sib2, iclass 39, count 0 2006.202.01:06:56.48#ibcon#*mode == 0, iclass 39, count 0 2006.202.01:06:56.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.01:06:56.48#ibcon#[27=USB\r\n] 2006.202.01:06:56.48#ibcon#*before write, iclass 39, count 0 2006.202.01:06:56.48#ibcon#enter sib2, iclass 39, count 0 2006.202.01:06:56.48#ibcon#flushed, iclass 39, count 0 2006.202.01:06:56.48#ibcon#about to write, iclass 39, count 0 2006.202.01:06:56.48#ibcon#wrote, iclass 39, count 0 2006.202.01:06:56.48#ibcon#about to read 3, iclass 39, count 0 2006.202.01:06:56.51#ibcon#read 3, iclass 39, count 0 2006.202.01:06:56.51#ibcon#about to read 4, iclass 39, count 0 2006.202.01:06:56.51#ibcon#read 4, iclass 39, count 0 2006.202.01:06:56.51#ibcon#about to read 5, iclass 39, count 0 2006.202.01:06:56.51#ibcon#read 5, iclass 39, count 0 2006.202.01:06:56.51#ibcon#about to read 6, iclass 39, count 0 2006.202.01:06:56.51#ibcon#read 6, iclass 39, count 0 2006.202.01:06:56.51#ibcon#end of sib2, iclass 39, count 0 2006.202.01:06:56.51#ibcon#*after write, iclass 39, count 0 2006.202.01:06:56.51#ibcon#*before return 0, iclass 39, count 0 2006.202.01:06:56.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:56.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:06:56.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.01:06:56.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.01:06:56.51$vck44/vblo=3,649.99 2006.202.01:06:56.51#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.202.01:06:56.51#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.202.01:06:56.51#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:56.51#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:56.51#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:56.51#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:56.51#ibcon#enter wrdev, iclass 2, count 0 2006.202.01:06:56.51#ibcon#first serial, iclass 2, count 0 2006.202.01:06:56.51#ibcon#enter sib2, iclass 2, count 0 2006.202.01:06:56.51#ibcon#flushed, iclass 2, count 0 2006.202.01:06:56.51#ibcon#about to write, iclass 2, count 0 2006.202.01:06:56.51#ibcon#wrote, iclass 2, count 0 2006.202.01:06:56.51#ibcon#about to read 3, iclass 2, count 0 2006.202.01:06:56.53#ibcon#read 3, iclass 2, count 0 2006.202.01:06:56.53#ibcon#about to read 4, iclass 2, count 0 2006.202.01:06:56.53#ibcon#read 4, iclass 2, count 0 2006.202.01:06:56.53#ibcon#about to read 5, iclass 2, count 0 2006.202.01:06:56.53#ibcon#read 5, iclass 2, count 0 2006.202.01:06:56.53#ibcon#about to read 6, iclass 2, count 0 2006.202.01:06:56.53#ibcon#read 6, iclass 2, count 0 2006.202.01:06:56.53#ibcon#end of sib2, iclass 2, count 0 2006.202.01:06:56.53#ibcon#*mode == 0, iclass 2, count 0 2006.202.01:06:56.53#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.01:06:56.53#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.01:06:56.53#ibcon#*before write, iclass 2, count 0 2006.202.01:06:56.53#ibcon#enter sib2, iclass 2, count 0 2006.202.01:06:56.53#ibcon#flushed, iclass 2, count 0 2006.202.01:06:56.53#ibcon#about to write, iclass 2, count 0 2006.202.01:06:56.53#ibcon#wrote, iclass 2, count 0 2006.202.01:06:56.53#ibcon#about to read 3, iclass 2, count 0 2006.202.01:06:56.57#ibcon#read 3, iclass 2, count 0 2006.202.01:06:56.57#ibcon#about to read 4, iclass 2, count 0 2006.202.01:06:56.57#ibcon#read 4, iclass 2, count 0 2006.202.01:06:56.57#ibcon#about to read 5, iclass 2, count 0 2006.202.01:06:56.57#ibcon#read 5, iclass 2, count 0 2006.202.01:06:56.57#ibcon#about to read 6, iclass 2, count 0 2006.202.01:06:56.57#ibcon#read 6, iclass 2, count 0 2006.202.01:06:56.57#ibcon#end of sib2, iclass 2, count 0 2006.202.01:06:56.57#ibcon#*after write, iclass 2, count 0 2006.202.01:06:56.57#ibcon#*before return 0, iclass 2, count 0 2006.202.01:06:56.57#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:56.67#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:06:56.67#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.01:06:56.67#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.01:06:56.67$vck44/vb=3,4 2006.202.01:06:56.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.202.01:06:56.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.202.01:06:56.67#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:56.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:56.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:56.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:56.67#ibcon#enter wrdev, iclass 5, count 2 2006.202.01:06:56.67#ibcon#first serial, iclass 5, count 2 2006.202.01:06:56.67#ibcon#enter sib2, iclass 5, count 2 2006.202.01:06:56.67#ibcon#flushed, iclass 5, count 2 2006.202.01:06:56.67#ibcon#about to write, iclass 5, count 2 2006.202.01:06:56.67#ibcon#wrote, iclass 5, count 2 2006.202.01:06:56.67#ibcon#about to read 3, iclass 5, count 2 2006.202.01:06:56.69#ibcon#read 3, iclass 5, count 2 2006.202.01:06:56.69#ibcon#about to read 4, iclass 5, count 2 2006.202.01:06:56.69#ibcon#read 4, iclass 5, count 2 2006.202.01:06:56.69#ibcon#about to read 5, iclass 5, count 2 2006.202.01:06:56.69#ibcon#read 5, iclass 5, count 2 2006.202.01:06:56.69#ibcon#about to read 6, iclass 5, count 2 2006.202.01:06:56.69#ibcon#read 6, iclass 5, count 2 2006.202.01:06:56.69#ibcon#end of sib2, iclass 5, count 2 2006.202.01:06:56.69#ibcon#*mode == 0, iclass 5, count 2 2006.202.01:06:56.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.202.01:06:56.69#ibcon#[27=AT03-04\r\n] 2006.202.01:06:56.69#ibcon#*before write, iclass 5, count 2 2006.202.01:06:56.69#ibcon#enter sib2, iclass 5, count 2 2006.202.01:06:56.69#ibcon#flushed, iclass 5, count 2 2006.202.01:06:56.69#ibcon#about to write, iclass 5, count 2 2006.202.01:06:56.69#ibcon#wrote, iclass 5, count 2 2006.202.01:06:56.69#ibcon#about to read 3, iclass 5, count 2 2006.202.01:06:56.72#ibcon#read 3, iclass 5, count 2 2006.202.01:06:56.72#ibcon#about to read 4, iclass 5, count 2 2006.202.01:06:56.72#ibcon#read 4, iclass 5, count 2 2006.202.01:06:56.72#ibcon#about to read 5, iclass 5, count 2 2006.202.01:06:56.72#ibcon#read 5, iclass 5, count 2 2006.202.01:06:56.72#ibcon#about to read 6, iclass 5, count 2 2006.202.01:06:56.72#ibcon#read 6, iclass 5, count 2 2006.202.01:06:56.72#ibcon#end of sib2, iclass 5, count 2 2006.202.01:06:56.72#ibcon#*after write, iclass 5, count 2 2006.202.01:06:56.72#ibcon#*before return 0, iclass 5, count 2 2006.202.01:06:56.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:56.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:06:56.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.202.01:06:56.72#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:56.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:56.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:56.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:56.84#ibcon#enter wrdev, iclass 5, count 0 2006.202.01:06:56.84#ibcon#first serial, iclass 5, count 0 2006.202.01:06:56.84#ibcon#enter sib2, iclass 5, count 0 2006.202.01:06:56.84#ibcon#flushed, iclass 5, count 0 2006.202.01:06:56.84#ibcon#about to write, iclass 5, count 0 2006.202.01:06:56.84#ibcon#wrote, iclass 5, count 0 2006.202.01:06:56.84#ibcon#about to read 3, iclass 5, count 0 2006.202.01:06:56.86#ibcon#read 3, iclass 5, count 0 2006.202.01:06:56.86#ibcon#about to read 4, iclass 5, count 0 2006.202.01:06:56.86#ibcon#read 4, iclass 5, count 0 2006.202.01:06:56.86#ibcon#about to read 5, iclass 5, count 0 2006.202.01:06:56.86#ibcon#read 5, iclass 5, count 0 2006.202.01:06:56.86#ibcon#about to read 6, iclass 5, count 0 2006.202.01:06:56.86#ibcon#read 6, iclass 5, count 0 2006.202.01:06:56.86#ibcon#end of sib2, iclass 5, count 0 2006.202.01:06:56.86#ibcon#*mode == 0, iclass 5, count 0 2006.202.01:06:56.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.01:06:56.86#ibcon#[27=USB\r\n] 2006.202.01:06:56.86#ibcon#*before write, iclass 5, count 0 2006.202.01:06:56.86#ibcon#enter sib2, iclass 5, count 0 2006.202.01:06:56.86#ibcon#flushed, iclass 5, count 0 2006.202.01:06:56.86#ibcon#about to write, iclass 5, count 0 2006.202.01:06:56.86#ibcon#wrote, iclass 5, count 0 2006.202.01:06:56.86#ibcon#about to read 3, iclass 5, count 0 2006.202.01:06:56.89#ibcon#read 3, iclass 5, count 0 2006.202.01:06:56.89#ibcon#about to read 4, iclass 5, count 0 2006.202.01:06:56.89#ibcon#read 4, iclass 5, count 0 2006.202.01:06:56.89#ibcon#about to read 5, iclass 5, count 0 2006.202.01:06:56.89#ibcon#read 5, iclass 5, count 0 2006.202.01:06:56.89#ibcon#about to read 6, iclass 5, count 0 2006.202.01:06:56.89#ibcon#read 6, iclass 5, count 0 2006.202.01:06:56.89#ibcon#end of sib2, iclass 5, count 0 2006.202.01:06:56.89#ibcon#*after write, iclass 5, count 0 2006.202.01:06:56.89#ibcon#*before return 0, iclass 5, count 0 2006.202.01:06:56.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:56.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:06:56.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.01:06:56.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.01:06:56.89$vck44/vblo=4,679.99 2006.202.01:06:56.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.01:06:56.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.01:06:56.89#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:56.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:56.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:56.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:56.89#ibcon#enter wrdev, iclass 7, count 0 2006.202.01:06:56.89#ibcon#first serial, iclass 7, count 0 2006.202.01:06:56.89#ibcon#enter sib2, iclass 7, count 0 2006.202.01:06:56.89#ibcon#flushed, iclass 7, count 0 2006.202.01:06:56.89#ibcon#about to write, iclass 7, count 0 2006.202.01:06:56.89#ibcon#wrote, iclass 7, count 0 2006.202.01:06:56.89#ibcon#about to read 3, iclass 7, count 0 2006.202.01:06:56.91#ibcon#read 3, iclass 7, count 0 2006.202.01:06:56.91#ibcon#about to read 4, iclass 7, count 0 2006.202.01:06:56.91#ibcon#read 4, iclass 7, count 0 2006.202.01:06:56.91#ibcon#about to read 5, iclass 7, count 0 2006.202.01:06:56.91#ibcon#read 5, iclass 7, count 0 2006.202.01:06:56.91#ibcon#about to read 6, iclass 7, count 0 2006.202.01:06:56.91#ibcon#read 6, iclass 7, count 0 2006.202.01:06:56.91#ibcon#end of sib2, iclass 7, count 0 2006.202.01:06:56.91#ibcon#*mode == 0, iclass 7, count 0 2006.202.01:06:56.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.01:06:56.91#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.01:06:56.91#ibcon#*before write, iclass 7, count 0 2006.202.01:06:56.91#ibcon#enter sib2, iclass 7, count 0 2006.202.01:06:56.91#ibcon#flushed, iclass 7, count 0 2006.202.01:06:56.91#ibcon#about to write, iclass 7, count 0 2006.202.01:06:56.91#ibcon#wrote, iclass 7, count 0 2006.202.01:06:56.91#ibcon#about to read 3, iclass 7, count 0 2006.202.01:06:56.95#ibcon#read 3, iclass 7, count 0 2006.202.01:06:56.95#ibcon#about to read 4, iclass 7, count 0 2006.202.01:06:56.95#ibcon#read 4, iclass 7, count 0 2006.202.01:06:56.95#ibcon#about to read 5, iclass 7, count 0 2006.202.01:06:56.95#ibcon#read 5, iclass 7, count 0 2006.202.01:06:56.95#ibcon#about to read 6, iclass 7, count 0 2006.202.01:06:56.95#ibcon#read 6, iclass 7, count 0 2006.202.01:06:56.95#ibcon#end of sib2, iclass 7, count 0 2006.202.01:06:56.95#ibcon#*after write, iclass 7, count 0 2006.202.01:06:56.95#ibcon#*before return 0, iclass 7, count 0 2006.202.01:06:56.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:56.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:06:56.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.01:06:56.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.01:06:56.95$vck44/vb=4,5 2006.202.01:06:56.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.202.01:06:56.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.202.01:06:56.95#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:56.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:57.01#abcon#<5=/04 2.7 5.4 20.381001000.9\r\n> 2006.202.01:06:57.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:57.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:57.01#ibcon#enter wrdev, iclass 11, count 2 2006.202.01:06:57.01#ibcon#first serial, iclass 11, count 2 2006.202.01:06:57.01#ibcon#enter sib2, iclass 11, count 2 2006.202.01:06:57.01#ibcon#flushed, iclass 11, count 2 2006.202.01:06:57.01#ibcon#about to write, iclass 11, count 2 2006.202.01:06:57.01#ibcon#wrote, iclass 11, count 2 2006.202.01:06:57.01#ibcon#about to read 3, iclass 11, count 2 2006.202.01:06:57.03#abcon#{5=INTERFACE CLEAR} 2006.202.01:06:57.03#ibcon#read 3, iclass 11, count 2 2006.202.01:06:57.03#ibcon#about to read 4, iclass 11, count 2 2006.202.01:06:57.03#ibcon#read 4, iclass 11, count 2 2006.202.01:06:57.03#ibcon#about to read 5, iclass 11, count 2 2006.202.01:06:57.03#ibcon#read 5, iclass 11, count 2 2006.202.01:06:57.03#ibcon#about to read 6, iclass 11, count 2 2006.202.01:06:57.03#ibcon#read 6, iclass 11, count 2 2006.202.01:06:57.03#ibcon#end of sib2, iclass 11, count 2 2006.202.01:06:57.03#ibcon#*mode == 0, iclass 11, count 2 2006.202.01:06:57.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.202.01:06:57.03#ibcon#[27=AT04-05\r\n] 2006.202.01:06:57.03#ibcon#*before write, iclass 11, count 2 2006.202.01:06:57.03#ibcon#enter sib2, iclass 11, count 2 2006.202.01:06:57.03#ibcon#flushed, iclass 11, count 2 2006.202.01:06:57.03#ibcon#about to write, iclass 11, count 2 2006.202.01:06:57.03#ibcon#wrote, iclass 11, count 2 2006.202.01:06:57.03#ibcon#about to read 3, iclass 11, count 2 2006.202.01:06:57.06#ibcon#read 3, iclass 11, count 2 2006.202.01:06:57.06#ibcon#about to read 4, iclass 11, count 2 2006.202.01:06:57.06#ibcon#read 4, iclass 11, count 2 2006.202.01:06:57.06#ibcon#about to read 5, iclass 11, count 2 2006.202.01:06:57.06#ibcon#read 5, iclass 11, count 2 2006.202.01:06:57.06#ibcon#about to read 6, iclass 11, count 2 2006.202.01:06:57.06#ibcon#read 6, iclass 11, count 2 2006.202.01:06:57.06#ibcon#end of sib2, iclass 11, count 2 2006.202.01:06:57.06#ibcon#*after write, iclass 11, count 2 2006.202.01:06:57.06#ibcon#*before return 0, iclass 11, count 2 2006.202.01:06:57.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:57.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:06:57.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.202.01:06:57.06#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:57.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:57.09#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:06:57.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:57.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:57.18#ibcon#enter wrdev, iclass 11, count 0 2006.202.01:06:57.18#ibcon#first serial, iclass 11, count 0 2006.202.01:06:57.18#ibcon#enter sib2, iclass 11, count 0 2006.202.01:06:57.18#ibcon#flushed, iclass 11, count 0 2006.202.01:06:57.18#ibcon#about to write, iclass 11, count 0 2006.202.01:06:57.18#ibcon#wrote, iclass 11, count 0 2006.202.01:06:57.18#ibcon#about to read 3, iclass 11, count 0 2006.202.01:06:57.20#ibcon#read 3, iclass 11, count 0 2006.202.01:06:57.20#ibcon#about to read 4, iclass 11, count 0 2006.202.01:06:57.20#ibcon#read 4, iclass 11, count 0 2006.202.01:06:57.20#ibcon#about to read 5, iclass 11, count 0 2006.202.01:06:57.20#ibcon#read 5, iclass 11, count 0 2006.202.01:06:57.20#ibcon#about to read 6, iclass 11, count 0 2006.202.01:06:57.20#ibcon#read 6, iclass 11, count 0 2006.202.01:06:57.20#ibcon#end of sib2, iclass 11, count 0 2006.202.01:06:57.20#ibcon#*mode == 0, iclass 11, count 0 2006.202.01:06:57.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.01:06:57.20#ibcon#[27=USB\r\n] 2006.202.01:06:57.20#ibcon#*before write, iclass 11, count 0 2006.202.01:06:57.20#ibcon#enter sib2, iclass 11, count 0 2006.202.01:06:57.20#ibcon#flushed, iclass 11, count 0 2006.202.01:06:57.20#ibcon#about to write, iclass 11, count 0 2006.202.01:06:57.20#ibcon#wrote, iclass 11, count 0 2006.202.01:06:57.20#ibcon#about to read 3, iclass 11, count 0 2006.202.01:06:57.23#ibcon#read 3, iclass 11, count 0 2006.202.01:06:57.23#ibcon#about to read 4, iclass 11, count 0 2006.202.01:06:57.23#ibcon#read 4, iclass 11, count 0 2006.202.01:06:57.23#ibcon#about to read 5, iclass 11, count 0 2006.202.01:06:57.23#ibcon#read 5, iclass 11, count 0 2006.202.01:06:57.23#ibcon#about to read 6, iclass 11, count 0 2006.202.01:06:57.23#ibcon#read 6, iclass 11, count 0 2006.202.01:06:57.23#ibcon#end of sib2, iclass 11, count 0 2006.202.01:06:57.23#ibcon#*after write, iclass 11, count 0 2006.202.01:06:57.23#ibcon#*before return 0, iclass 11, count 0 2006.202.01:06:57.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:57.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:06:57.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.01:06:57.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.01:06:57.23$vck44/vblo=5,709.99 2006.202.01:06:57.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.01:06:57.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.01:06:57.23#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:57.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:57.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:57.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:57.23#ibcon#enter wrdev, iclass 17, count 0 2006.202.01:06:57.23#ibcon#first serial, iclass 17, count 0 2006.202.01:06:57.23#ibcon#enter sib2, iclass 17, count 0 2006.202.01:06:57.23#ibcon#flushed, iclass 17, count 0 2006.202.01:06:57.23#ibcon#about to write, iclass 17, count 0 2006.202.01:06:57.23#ibcon#wrote, iclass 17, count 0 2006.202.01:06:57.23#ibcon#about to read 3, iclass 17, count 0 2006.202.01:06:57.25#ibcon#read 3, iclass 17, count 0 2006.202.01:06:57.25#ibcon#about to read 4, iclass 17, count 0 2006.202.01:06:57.25#ibcon#read 4, iclass 17, count 0 2006.202.01:06:57.25#ibcon#about to read 5, iclass 17, count 0 2006.202.01:06:57.25#ibcon#read 5, iclass 17, count 0 2006.202.01:06:57.25#ibcon#about to read 6, iclass 17, count 0 2006.202.01:06:57.25#ibcon#read 6, iclass 17, count 0 2006.202.01:06:57.25#ibcon#end of sib2, iclass 17, count 0 2006.202.01:06:57.25#ibcon#*mode == 0, iclass 17, count 0 2006.202.01:06:57.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.01:06:57.25#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.01:06:57.25#ibcon#*before write, iclass 17, count 0 2006.202.01:06:57.25#ibcon#enter sib2, iclass 17, count 0 2006.202.01:06:57.25#ibcon#flushed, iclass 17, count 0 2006.202.01:06:57.25#ibcon#about to write, iclass 17, count 0 2006.202.01:06:57.25#ibcon#wrote, iclass 17, count 0 2006.202.01:06:57.25#ibcon#about to read 3, iclass 17, count 0 2006.202.01:06:57.29#ibcon#read 3, iclass 17, count 0 2006.202.01:06:57.29#ibcon#about to read 4, iclass 17, count 0 2006.202.01:06:57.29#ibcon#read 4, iclass 17, count 0 2006.202.01:06:57.29#ibcon#about to read 5, iclass 17, count 0 2006.202.01:06:57.29#ibcon#read 5, iclass 17, count 0 2006.202.01:06:57.29#ibcon#about to read 6, iclass 17, count 0 2006.202.01:06:57.29#ibcon#read 6, iclass 17, count 0 2006.202.01:06:57.29#ibcon#end of sib2, iclass 17, count 0 2006.202.01:06:57.29#ibcon#*after write, iclass 17, count 0 2006.202.01:06:57.29#ibcon#*before return 0, iclass 17, count 0 2006.202.01:06:57.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:57.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:06:57.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.01:06:57.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.01:06:57.29$vck44/vb=5,4 2006.202.01:06:57.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.202.01:06:57.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.202.01:06:57.29#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:57.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:57.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:57.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:57.35#ibcon#enter wrdev, iclass 19, count 2 2006.202.01:06:57.35#ibcon#first serial, iclass 19, count 2 2006.202.01:06:57.35#ibcon#enter sib2, iclass 19, count 2 2006.202.01:06:57.35#ibcon#flushed, iclass 19, count 2 2006.202.01:06:57.35#ibcon#about to write, iclass 19, count 2 2006.202.01:06:57.35#ibcon#wrote, iclass 19, count 2 2006.202.01:06:57.35#ibcon#about to read 3, iclass 19, count 2 2006.202.01:06:57.37#ibcon#read 3, iclass 19, count 2 2006.202.01:06:57.37#ibcon#about to read 4, iclass 19, count 2 2006.202.01:06:57.37#ibcon#read 4, iclass 19, count 2 2006.202.01:06:57.37#ibcon#about to read 5, iclass 19, count 2 2006.202.01:06:57.37#ibcon#read 5, iclass 19, count 2 2006.202.01:06:57.37#ibcon#about to read 6, iclass 19, count 2 2006.202.01:06:57.37#ibcon#read 6, iclass 19, count 2 2006.202.01:06:57.37#ibcon#end of sib2, iclass 19, count 2 2006.202.01:06:57.37#ibcon#*mode == 0, iclass 19, count 2 2006.202.01:06:57.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.202.01:06:57.37#ibcon#[27=AT05-04\r\n] 2006.202.01:06:57.37#ibcon#*before write, iclass 19, count 2 2006.202.01:06:57.37#ibcon#enter sib2, iclass 19, count 2 2006.202.01:06:57.37#ibcon#flushed, iclass 19, count 2 2006.202.01:06:57.37#ibcon#about to write, iclass 19, count 2 2006.202.01:06:57.37#ibcon#wrote, iclass 19, count 2 2006.202.01:06:57.37#ibcon#about to read 3, iclass 19, count 2 2006.202.01:06:57.40#ibcon#read 3, iclass 19, count 2 2006.202.01:06:57.40#ibcon#about to read 4, iclass 19, count 2 2006.202.01:06:57.40#ibcon#read 4, iclass 19, count 2 2006.202.01:06:57.40#ibcon#about to read 5, iclass 19, count 2 2006.202.01:06:57.40#ibcon#read 5, iclass 19, count 2 2006.202.01:06:57.40#ibcon#about to read 6, iclass 19, count 2 2006.202.01:06:57.40#ibcon#read 6, iclass 19, count 2 2006.202.01:06:57.40#ibcon#end of sib2, iclass 19, count 2 2006.202.01:06:57.40#ibcon#*after write, iclass 19, count 2 2006.202.01:06:57.40#ibcon#*before return 0, iclass 19, count 2 2006.202.01:06:57.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:57.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:06:57.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.202.01:06:57.40#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:57.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:57.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:57.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:57.52#ibcon#enter wrdev, iclass 19, count 0 2006.202.01:06:57.52#ibcon#first serial, iclass 19, count 0 2006.202.01:06:57.52#ibcon#enter sib2, iclass 19, count 0 2006.202.01:06:57.52#ibcon#flushed, iclass 19, count 0 2006.202.01:06:57.52#ibcon#about to write, iclass 19, count 0 2006.202.01:06:57.52#ibcon#wrote, iclass 19, count 0 2006.202.01:06:57.52#ibcon#about to read 3, iclass 19, count 0 2006.202.01:06:57.54#ibcon#read 3, iclass 19, count 0 2006.202.01:06:57.54#ibcon#about to read 4, iclass 19, count 0 2006.202.01:06:57.54#ibcon#read 4, iclass 19, count 0 2006.202.01:06:57.54#ibcon#about to read 5, iclass 19, count 0 2006.202.01:06:57.54#ibcon#read 5, iclass 19, count 0 2006.202.01:06:57.54#ibcon#about to read 6, iclass 19, count 0 2006.202.01:06:57.54#ibcon#read 6, iclass 19, count 0 2006.202.01:06:57.54#ibcon#end of sib2, iclass 19, count 0 2006.202.01:06:57.54#ibcon#*mode == 0, iclass 19, count 0 2006.202.01:06:57.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.01:06:57.54#ibcon#[27=USB\r\n] 2006.202.01:06:57.54#ibcon#*before write, iclass 19, count 0 2006.202.01:06:57.54#ibcon#enter sib2, iclass 19, count 0 2006.202.01:06:57.54#ibcon#flushed, iclass 19, count 0 2006.202.01:06:57.54#ibcon#about to write, iclass 19, count 0 2006.202.01:06:57.54#ibcon#wrote, iclass 19, count 0 2006.202.01:06:57.54#ibcon#about to read 3, iclass 19, count 0 2006.202.01:06:57.57#ibcon#read 3, iclass 19, count 0 2006.202.01:06:57.57#ibcon#about to read 4, iclass 19, count 0 2006.202.01:06:57.57#ibcon#read 4, iclass 19, count 0 2006.202.01:06:57.57#ibcon#about to read 5, iclass 19, count 0 2006.202.01:06:57.57#ibcon#read 5, iclass 19, count 0 2006.202.01:06:57.57#ibcon#about to read 6, iclass 19, count 0 2006.202.01:06:57.57#ibcon#read 6, iclass 19, count 0 2006.202.01:06:57.57#ibcon#end of sib2, iclass 19, count 0 2006.202.01:06:57.57#ibcon#*after write, iclass 19, count 0 2006.202.01:06:57.57#ibcon#*before return 0, iclass 19, count 0 2006.202.01:06:57.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:57.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:06:57.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.01:06:57.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.01:06:57.57$vck44/vblo=6,719.99 2006.202.01:06:57.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.202.01:06:57.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.202.01:06:57.57#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:57.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:57.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:57.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:57.57#ibcon#enter wrdev, iclass 21, count 0 2006.202.01:06:57.57#ibcon#first serial, iclass 21, count 0 2006.202.01:06:57.57#ibcon#enter sib2, iclass 21, count 0 2006.202.01:06:57.57#ibcon#flushed, iclass 21, count 0 2006.202.01:06:57.57#ibcon#about to write, iclass 21, count 0 2006.202.01:06:57.57#ibcon#wrote, iclass 21, count 0 2006.202.01:06:57.57#ibcon#about to read 3, iclass 21, count 0 2006.202.01:06:57.59#ibcon#read 3, iclass 21, count 0 2006.202.01:06:57.59#ibcon#about to read 4, iclass 21, count 0 2006.202.01:06:57.59#ibcon#read 4, iclass 21, count 0 2006.202.01:06:57.59#ibcon#about to read 5, iclass 21, count 0 2006.202.01:06:57.59#ibcon#read 5, iclass 21, count 0 2006.202.01:06:57.59#ibcon#about to read 6, iclass 21, count 0 2006.202.01:06:57.59#ibcon#read 6, iclass 21, count 0 2006.202.01:06:57.59#ibcon#end of sib2, iclass 21, count 0 2006.202.01:06:57.59#ibcon#*mode == 0, iclass 21, count 0 2006.202.01:06:57.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.01:06:57.59#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.01:06:57.59#ibcon#*before write, iclass 21, count 0 2006.202.01:06:57.59#ibcon#enter sib2, iclass 21, count 0 2006.202.01:06:57.59#ibcon#flushed, iclass 21, count 0 2006.202.01:06:57.59#ibcon#about to write, iclass 21, count 0 2006.202.01:06:57.59#ibcon#wrote, iclass 21, count 0 2006.202.01:06:57.59#ibcon#about to read 3, iclass 21, count 0 2006.202.01:06:57.63#ibcon#read 3, iclass 21, count 0 2006.202.01:06:57.63#ibcon#about to read 4, iclass 21, count 0 2006.202.01:06:57.63#ibcon#read 4, iclass 21, count 0 2006.202.01:06:57.63#ibcon#about to read 5, iclass 21, count 0 2006.202.01:06:57.63#ibcon#read 5, iclass 21, count 0 2006.202.01:06:57.63#ibcon#about to read 6, iclass 21, count 0 2006.202.01:06:57.63#ibcon#read 6, iclass 21, count 0 2006.202.01:06:57.63#ibcon#end of sib2, iclass 21, count 0 2006.202.01:06:57.63#ibcon#*after write, iclass 21, count 0 2006.202.01:06:57.63#ibcon#*before return 0, iclass 21, count 0 2006.202.01:06:57.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:57.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:06:57.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.01:06:57.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.01:06:57.63$vck44/vb=6,4 2006.202.01:06:57.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.202.01:06:57.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.202.01:06:57.63#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:57.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:57.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:57.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:57.69#ibcon#enter wrdev, iclass 23, count 2 2006.202.01:06:57.69#ibcon#first serial, iclass 23, count 2 2006.202.01:06:57.69#ibcon#enter sib2, iclass 23, count 2 2006.202.01:06:57.69#ibcon#flushed, iclass 23, count 2 2006.202.01:06:57.69#ibcon#about to write, iclass 23, count 2 2006.202.01:06:57.69#ibcon#wrote, iclass 23, count 2 2006.202.01:06:57.69#ibcon#about to read 3, iclass 23, count 2 2006.202.01:06:57.71#ibcon#read 3, iclass 23, count 2 2006.202.01:06:57.71#ibcon#about to read 4, iclass 23, count 2 2006.202.01:06:57.71#ibcon#read 4, iclass 23, count 2 2006.202.01:06:57.71#ibcon#about to read 5, iclass 23, count 2 2006.202.01:06:57.71#ibcon#read 5, iclass 23, count 2 2006.202.01:06:57.71#ibcon#about to read 6, iclass 23, count 2 2006.202.01:06:57.71#ibcon#read 6, iclass 23, count 2 2006.202.01:06:57.71#ibcon#end of sib2, iclass 23, count 2 2006.202.01:06:57.71#ibcon#*mode == 0, iclass 23, count 2 2006.202.01:06:57.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.202.01:06:57.71#ibcon#[27=AT06-04\r\n] 2006.202.01:06:57.71#ibcon#*before write, iclass 23, count 2 2006.202.01:06:57.71#ibcon#enter sib2, iclass 23, count 2 2006.202.01:06:57.71#ibcon#flushed, iclass 23, count 2 2006.202.01:06:57.71#ibcon#about to write, iclass 23, count 2 2006.202.01:06:57.71#ibcon#wrote, iclass 23, count 2 2006.202.01:06:57.76#ibcon#about to read 3, iclass 23, count 2 2006.202.01:06:57.76#ibcon#read 3, iclass 23, count 2 2006.202.01:06:57.76#ibcon#about to read 4, iclass 23, count 2 2006.202.01:06:57.76#ibcon#read 4, iclass 23, count 2 2006.202.01:06:57.76#ibcon#about to read 5, iclass 23, count 2 2006.202.01:06:57.76#ibcon#read 5, iclass 23, count 2 2006.202.01:06:57.76#ibcon#about to read 6, iclass 23, count 2 2006.202.01:06:57.76#ibcon#read 6, iclass 23, count 2 2006.202.01:06:57.76#ibcon#end of sib2, iclass 23, count 2 2006.202.01:06:57.76#ibcon#*after write, iclass 23, count 2 2006.202.01:06:57.76#ibcon#*before return 0, iclass 23, count 2 2006.202.01:06:57.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:57.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:06:57.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.202.01:06:57.76#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:57.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:57.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:57.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:57.88#ibcon#enter wrdev, iclass 23, count 0 2006.202.01:06:57.88#ibcon#first serial, iclass 23, count 0 2006.202.01:06:57.88#ibcon#enter sib2, iclass 23, count 0 2006.202.01:06:57.88#ibcon#flushed, iclass 23, count 0 2006.202.01:06:57.88#ibcon#about to write, iclass 23, count 0 2006.202.01:06:57.88#ibcon#wrote, iclass 23, count 0 2006.202.01:06:57.88#ibcon#about to read 3, iclass 23, count 0 2006.202.01:06:57.90#ibcon#read 3, iclass 23, count 0 2006.202.01:06:57.90#ibcon#about to read 4, iclass 23, count 0 2006.202.01:06:57.90#ibcon#read 4, iclass 23, count 0 2006.202.01:06:57.90#ibcon#about to read 5, iclass 23, count 0 2006.202.01:06:57.90#ibcon#read 5, iclass 23, count 0 2006.202.01:06:57.90#ibcon#about to read 6, iclass 23, count 0 2006.202.01:06:57.90#ibcon#read 6, iclass 23, count 0 2006.202.01:06:57.90#ibcon#end of sib2, iclass 23, count 0 2006.202.01:06:57.90#ibcon#*mode == 0, iclass 23, count 0 2006.202.01:06:57.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.01:06:57.90#ibcon#[27=USB\r\n] 2006.202.01:06:57.90#ibcon#*before write, iclass 23, count 0 2006.202.01:06:57.90#ibcon#enter sib2, iclass 23, count 0 2006.202.01:06:57.90#ibcon#flushed, iclass 23, count 0 2006.202.01:06:57.90#ibcon#about to write, iclass 23, count 0 2006.202.01:06:57.90#ibcon#wrote, iclass 23, count 0 2006.202.01:06:57.90#ibcon#about to read 3, iclass 23, count 0 2006.202.01:06:57.93#ibcon#read 3, iclass 23, count 0 2006.202.01:06:57.93#ibcon#about to read 4, iclass 23, count 0 2006.202.01:06:57.93#ibcon#read 4, iclass 23, count 0 2006.202.01:06:57.93#ibcon#about to read 5, iclass 23, count 0 2006.202.01:06:57.93#ibcon#read 5, iclass 23, count 0 2006.202.01:06:57.93#ibcon#about to read 6, iclass 23, count 0 2006.202.01:06:57.93#ibcon#read 6, iclass 23, count 0 2006.202.01:06:57.93#ibcon#end of sib2, iclass 23, count 0 2006.202.01:06:57.93#ibcon#*after write, iclass 23, count 0 2006.202.01:06:57.93#ibcon#*before return 0, iclass 23, count 0 2006.202.01:06:57.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:57.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:06:57.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.01:06:57.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.01:06:57.93$vck44/vblo=7,734.99 2006.202.01:06:57.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.202.01:06:57.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.202.01:06:57.93#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:57.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:57.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:57.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:57.93#ibcon#enter wrdev, iclass 25, count 0 2006.202.01:06:57.93#ibcon#first serial, iclass 25, count 0 2006.202.01:06:57.93#ibcon#enter sib2, iclass 25, count 0 2006.202.01:06:57.93#ibcon#flushed, iclass 25, count 0 2006.202.01:06:57.93#ibcon#about to write, iclass 25, count 0 2006.202.01:06:57.93#ibcon#wrote, iclass 25, count 0 2006.202.01:06:57.93#ibcon#about to read 3, iclass 25, count 0 2006.202.01:06:57.95#ibcon#read 3, iclass 25, count 0 2006.202.01:06:57.95#ibcon#about to read 4, iclass 25, count 0 2006.202.01:06:57.95#ibcon#read 4, iclass 25, count 0 2006.202.01:06:57.95#ibcon#about to read 5, iclass 25, count 0 2006.202.01:06:57.95#ibcon#read 5, iclass 25, count 0 2006.202.01:06:57.95#ibcon#about to read 6, iclass 25, count 0 2006.202.01:06:57.95#ibcon#read 6, iclass 25, count 0 2006.202.01:06:57.95#ibcon#end of sib2, iclass 25, count 0 2006.202.01:06:57.95#ibcon#*mode == 0, iclass 25, count 0 2006.202.01:06:57.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.01:06:57.95#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.01:06:57.95#ibcon#*before write, iclass 25, count 0 2006.202.01:06:57.95#ibcon#enter sib2, iclass 25, count 0 2006.202.01:06:57.95#ibcon#flushed, iclass 25, count 0 2006.202.01:06:57.95#ibcon#about to write, iclass 25, count 0 2006.202.01:06:57.95#ibcon#wrote, iclass 25, count 0 2006.202.01:06:57.95#ibcon#about to read 3, iclass 25, count 0 2006.202.01:06:57.99#ibcon#read 3, iclass 25, count 0 2006.202.01:06:57.99#ibcon#about to read 4, iclass 25, count 0 2006.202.01:06:57.99#ibcon#read 4, iclass 25, count 0 2006.202.01:06:57.99#ibcon#about to read 5, iclass 25, count 0 2006.202.01:06:57.99#ibcon#read 5, iclass 25, count 0 2006.202.01:06:57.99#ibcon#about to read 6, iclass 25, count 0 2006.202.01:06:57.99#ibcon#read 6, iclass 25, count 0 2006.202.01:06:57.99#ibcon#end of sib2, iclass 25, count 0 2006.202.01:06:57.99#ibcon#*after write, iclass 25, count 0 2006.202.01:06:57.99#ibcon#*before return 0, iclass 25, count 0 2006.202.01:06:57.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:57.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:06:57.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.01:06:57.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.01:06:57.99$vck44/vb=7,4 2006.202.01:06:57.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.202.01:06:57.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.202.01:06:57.99#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:57.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:58.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:58.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:58.05#ibcon#enter wrdev, iclass 27, count 2 2006.202.01:06:58.05#ibcon#first serial, iclass 27, count 2 2006.202.01:06:58.05#ibcon#enter sib2, iclass 27, count 2 2006.202.01:06:58.05#ibcon#flushed, iclass 27, count 2 2006.202.01:06:58.05#ibcon#about to write, iclass 27, count 2 2006.202.01:06:58.05#ibcon#wrote, iclass 27, count 2 2006.202.01:06:58.05#ibcon#about to read 3, iclass 27, count 2 2006.202.01:06:58.07#ibcon#read 3, iclass 27, count 2 2006.202.01:06:58.07#ibcon#about to read 4, iclass 27, count 2 2006.202.01:06:58.07#ibcon#read 4, iclass 27, count 2 2006.202.01:06:58.07#ibcon#about to read 5, iclass 27, count 2 2006.202.01:06:58.07#ibcon#read 5, iclass 27, count 2 2006.202.01:06:58.07#ibcon#about to read 6, iclass 27, count 2 2006.202.01:06:58.07#ibcon#read 6, iclass 27, count 2 2006.202.01:06:58.07#ibcon#end of sib2, iclass 27, count 2 2006.202.01:06:58.07#ibcon#*mode == 0, iclass 27, count 2 2006.202.01:06:58.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.202.01:06:58.07#ibcon#[27=AT07-04\r\n] 2006.202.01:06:58.07#ibcon#*before write, iclass 27, count 2 2006.202.01:06:58.07#ibcon#enter sib2, iclass 27, count 2 2006.202.01:06:58.07#ibcon#flushed, iclass 27, count 2 2006.202.01:06:58.07#ibcon#about to write, iclass 27, count 2 2006.202.01:06:58.07#ibcon#wrote, iclass 27, count 2 2006.202.01:06:58.07#ibcon#about to read 3, iclass 27, count 2 2006.202.01:06:58.10#ibcon#read 3, iclass 27, count 2 2006.202.01:06:58.10#ibcon#about to read 4, iclass 27, count 2 2006.202.01:06:58.10#ibcon#read 4, iclass 27, count 2 2006.202.01:06:58.10#ibcon#about to read 5, iclass 27, count 2 2006.202.01:06:58.10#ibcon#read 5, iclass 27, count 2 2006.202.01:06:58.10#ibcon#about to read 6, iclass 27, count 2 2006.202.01:06:58.10#ibcon#read 6, iclass 27, count 2 2006.202.01:06:58.10#ibcon#end of sib2, iclass 27, count 2 2006.202.01:06:58.10#ibcon#*after write, iclass 27, count 2 2006.202.01:06:58.10#ibcon#*before return 0, iclass 27, count 2 2006.202.01:06:58.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:58.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:06:58.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.202.01:06:58.10#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:58.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:58.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:58.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:58.22#ibcon#enter wrdev, iclass 27, count 0 2006.202.01:06:58.22#ibcon#first serial, iclass 27, count 0 2006.202.01:06:58.22#ibcon#enter sib2, iclass 27, count 0 2006.202.01:06:58.22#ibcon#flushed, iclass 27, count 0 2006.202.01:06:58.22#ibcon#about to write, iclass 27, count 0 2006.202.01:06:58.22#ibcon#wrote, iclass 27, count 0 2006.202.01:06:58.22#ibcon#about to read 3, iclass 27, count 0 2006.202.01:06:58.24#ibcon#read 3, iclass 27, count 0 2006.202.01:06:58.24#ibcon#about to read 4, iclass 27, count 0 2006.202.01:06:58.24#ibcon#read 4, iclass 27, count 0 2006.202.01:06:58.24#ibcon#about to read 5, iclass 27, count 0 2006.202.01:06:58.24#ibcon#read 5, iclass 27, count 0 2006.202.01:06:58.24#ibcon#about to read 6, iclass 27, count 0 2006.202.01:06:58.24#ibcon#read 6, iclass 27, count 0 2006.202.01:06:58.24#ibcon#end of sib2, iclass 27, count 0 2006.202.01:06:58.24#ibcon#*mode == 0, iclass 27, count 0 2006.202.01:06:58.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.01:06:58.24#ibcon#[27=USB\r\n] 2006.202.01:06:58.24#ibcon#*before write, iclass 27, count 0 2006.202.01:06:58.24#ibcon#enter sib2, iclass 27, count 0 2006.202.01:06:58.24#ibcon#flushed, iclass 27, count 0 2006.202.01:06:58.24#ibcon#about to write, iclass 27, count 0 2006.202.01:06:58.24#ibcon#wrote, iclass 27, count 0 2006.202.01:06:58.24#ibcon#about to read 3, iclass 27, count 0 2006.202.01:06:58.27#ibcon#read 3, iclass 27, count 0 2006.202.01:06:58.27#ibcon#about to read 4, iclass 27, count 0 2006.202.01:06:58.27#ibcon#read 4, iclass 27, count 0 2006.202.01:06:58.27#ibcon#about to read 5, iclass 27, count 0 2006.202.01:06:58.27#ibcon#read 5, iclass 27, count 0 2006.202.01:06:58.27#ibcon#about to read 6, iclass 27, count 0 2006.202.01:06:58.27#ibcon#read 6, iclass 27, count 0 2006.202.01:06:58.27#ibcon#end of sib2, iclass 27, count 0 2006.202.01:06:58.27#ibcon#*after write, iclass 27, count 0 2006.202.01:06:58.27#ibcon#*before return 0, iclass 27, count 0 2006.202.01:06:58.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:58.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:06:58.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.01:06:58.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.01:06:58.27$vck44/vblo=8,744.99 2006.202.01:06:58.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.202.01:06:58.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.202.01:06:58.27#ibcon#ireg 17 cls_cnt 0 2006.202.01:06:58.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:58.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:58.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:58.27#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:06:58.27#ibcon#first serial, iclass 29, count 0 2006.202.01:06:58.27#ibcon#enter sib2, iclass 29, count 0 2006.202.01:06:58.27#ibcon#flushed, iclass 29, count 0 2006.202.01:06:58.27#ibcon#about to write, iclass 29, count 0 2006.202.01:06:58.27#ibcon#wrote, iclass 29, count 0 2006.202.01:06:58.27#ibcon#about to read 3, iclass 29, count 0 2006.202.01:06:58.29#ibcon#read 3, iclass 29, count 0 2006.202.01:06:58.29#ibcon#about to read 4, iclass 29, count 0 2006.202.01:06:58.29#ibcon#read 4, iclass 29, count 0 2006.202.01:06:58.29#ibcon#about to read 5, iclass 29, count 0 2006.202.01:06:58.29#ibcon#read 5, iclass 29, count 0 2006.202.01:06:58.29#ibcon#about to read 6, iclass 29, count 0 2006.202.01:06:58.29#ibcon#read 6, iclass 29, count 0 2006.202.01:06:58.29#ibcon#end of sib2, iclass 29, count 0 2006.202.01:06:58.29#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:06:58.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:06:58.29#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.01:06:58.29#ibcon#*before write, iclass 29, count 0 2006.202.01:06:58.29#ibcon#enter sib2, iclass 29, count 0 2006.202.01:06:58.29#ibcon#flushed, iclass 29, count 0 2006.202.01:06:58.29#ibcon#about to write, iclass 29, count 0 2006.202.01:06:58.29#ibcon#wrote, iclass 29, count 0 2006.202.01:06:58.29#ibcon#about to read 3, iclass 29, count 0 2006.202.01:06:58.33#ibcon#read 3, iclass 29, count 0 2006.202.01:06:58.33#ibcon#about to read 4, iclass 29, count 0 2006.202.01:06:58.33#ibcon#read 4, iclass 29, count 0 2006.202.01:06:58.33#ibcon#about to read 5, iclass 29, count 0 2006.202.01:06:58.33#ibcon#read 5, iclass 29, count 0 2006.202.01:06:58.33#ibcon#about to read 6, iclass 29, count 0 2006.202.01:06:58.33#ibcon#read 6, iclass 29, count 0 2006.202.01:06:58.33#ibcon#end of sib2, iclass 29, count 0 2006.202.01:06:58.33#ibcon#*after write, iclass 29, count 0 2006.202.01:06:58.33#ibcon#*before return 0, iclass 29, count 0 2006.202.01:06:58.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:58.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:06:58.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:06:58.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:06:58.33$vck44/vb=8,4 2006.202.01:06:58.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.202.01:06:58.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.202.01:06:58.33#ibcon#ireg 11 cls_cnt 2 2006.202.01:06:58.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:58.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:58.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:58.39#ibcon#enter wrdev, iclass 31, count 2 2006.202.01:06:58.39#ibcon#first serial, iclass 31, count 2 2006.202.01:06:58.39#ibcon#enter sib2, iclass 31, count 2 2006.202.01:06:58.39#ibcon#flushed, iclass 31, count 2 2006.202.01:06:58.39#ibcon#about to write, iclass 31, count 2 2006.202.01:06:58.39#ibcon#wrote, iclass 31, count 2 2006.202.01:06:58.39#ibcon#about to read 3, iclass 31, count 2 2006.202.01:06:58.41#ibcon#read 3, iclass 31, count 2 2006.202.01:06:58.41#ibcon#about to read 4, iclass 31, count 2 2006.202.01:06:58.41#ibcon#read 4, iclass 31, count 2 2006.202.01:06:58.41#ibcon#about to read 5, iclass 31, count 2 2006.202.01:06:58.41#ibcon#read 5, iclass 31, count 2 2006.202.01:06:58.41#ibcon#about to read 6, iclass 31, count 2 2006.202.01:06:58.41#ibcon#read 6, iclass 31, count 2 2006.202.01:06:58.41#ibcon#end of sib2, iclass 31, count 2 2006.202.01:06:58.41#ibcon#*mode == 0, iclass 31, count 2 2006.202.01:06:58.41#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.202.01:06:58.41#ibcon#[27=AT08-04\r\n] 2006.202.01:06:58.41#ibcon#*before write, iclass 31, count 2 2006.202.01:06:58.41#ibcon#enter sib2, iclass 31, count 2 2006.202.01:06:58.41#ibcon#flushed, iclass 31, count 2 2006.202.01:06:58.41#ibcon#about to write, iclass 31, count 2 2006.202.01:06:58.41#ibcon#wrote, iclass 31, count 2 2006.202.01:06:58.41#ibcon#about to read 3, iclass 31, count 2 2006.202.01:06:58.44#ibcon#read 3, iclass 31, count 2 2006.202.01:06:58.44#ibcon#about to read 4, iclass 31, count 2 2006.202.01:06:58.44#ibcon#read 4, iclass 31, count 2 2006.202.01:06:58.44#ibcon#about to read 5, iclass 31, count 2 2006.202.01:06:58.44#ibcon#read 5, iclass 31, count 2 2006.202.01:06:58.44#ibcon#about to read 6, iclass 31, count 2 2006.202.01:06:58.44#ibcon#read 6, iclass 31, count 2 2006.202.01:06:58.44#ibcon#end of sib2, iclass 31, count 2 2006.202.01:06:58.44#ibcon#*after write, iclass 31, count 2 2006.202.01:06:58.44#ibcon#*before return 0, iclass 31, count 2 2006.202.01:06:58.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:58.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:06:58.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.202.01:06:58.44#ibcon#ireg 7 cls_cnt 0 2006.202.01:06:58.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:58.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:58.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:58.56#ibcon#enter wrdev, iclass 31, count 0 2006.202.01:06:58.56#ibcon#first serial, iclass 31, count 0 2006.202.01:06:58.56#ibcon#enter sib2, iclass 31, count 0 2006.202.01:06:58.56#ibcon#flushed, iclass 31, count 0 2006.202.01:06:58.56#ibcon#about to write, iclass 31, count 0 2006.202.01:06:58.56#ibcon#wrote, iclass 31, count 0 2006.202.01:06:58.56#ibcon#about to read 3, iclass 31, count 0 2006.202.01:06:58.58#ibcon#read 3, iclass 31, count 0 2006.202.01:06:58.58#ibcon#about to read 4, iclass 31, count 0 2006.202.01:06:58.58#ibcon#read 4, iclass 31, count 0 2006.202.01:06:58.58#ibcon#about to read 5, iclass 31, count 0 2006.202.01:06:58.58#ibcon#read 5, iclass 31, count 0 2006.202.01:06:58.58#ibcon#about to read 6, iclass 31, count 0 2006.202.01:06:58.58#ibcon#read 6, iclass 31, count 0 2006.202.01:06:58.58#ibcon#end of sib2, iclass 31, count 0 2006.202.01:06:58.58#ibcon#*mode == 0, iclass 31, count 0 2006.202.01:06:58.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.01:06:58.58#ibcon#[27=USB\r\n] 2006.202.01:06:58.58#ibcon#*before write, iclass 31, count 0 2006.202.01:06:58.58#ibcon#enter sib2, iclass 31, count 0 2006.202.01:06:58.58#ibcon#flushed, iclass 31, count 0 2006.202.01:06:58.58#ibcon#about to write, iclass 31, count 0 2006.202.01:06:58.58#ibcon#wrote, iclass 31, count 0 2006.202.01:06:58.58#ibcon#about to read 3, iclass 31, count 0 2006.202.01:06:58.61#ibcon#read 3, iclass 31, count 0 2006.202.01:06:58.61#ibcon#about to read 4, iclass 31, count 0 2006.202.01:06:58.61#ibcon#read 4, iclass 31, count 0 2006.202.01:06:58.61#ibcon#about to read 5, iclass 31, count 0 2006.202.01:06:58.61#ibcon#read 5, iclass 31, count 0 2006.202.01:06:58.61#ibcon#about to read 6, iclass 31, count 0 2006.202.01:06:58.61#ibcon#read 6, iclass 31, count 0 2006.202.01:06:58.61#ibcon#end of sib2, iclass 31, count 0 2006.202.01:06:58.61#ibcon#*after write, iclass 31, count 0 2006.202.01:06:58.61#ibcon#*before return 0, iclass 31, count 0 2006.202.01:06:58.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:58.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:06:58.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.01:06:58.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.01:06:58.61$vck44/vabw=wide 2006.202.01:06:58.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.01:06:58.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.01:06:58.61#ibcon#ireg 8 cls_cnt 0 2006.202.01:06:58.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:58.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:58.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:58.61#ibcon#enter wrdev, iclass 33, count 0 2006.202.01:06:58.61#ibcon#first serial, iclass 33, count 0 2006.202.01:06:58.61#ibcon#enter sib2, iclass 33, count 0 2006.202.01:06:58.61#ibcon#flushed, iclass 33, count 0 2006.202.01:06:58.61#ibcon#about to write, iclass 33, count 0 2006.202.01:06:58.61#ibcon#wrote, iclass 33, count 0 2006.202.01:06:58.61#ibcon#about to read 3, iclass 33, count 0 2006.202.01:06:58.63#ibcon#read 3, iclass 33, count 0 2006.202.01:06:58.63#ibcon#about to read 4, iclass 33, count 0 2006.202.01:06:58.63#ibcon#read 4, iclass 33, count 0 2006.202.01:06:58.63#ibcon#about to read 5, iclass 33, count 0 2006.202.01:06:58.63#ibcon#read 5, iclass 33, count 0 2006.202.01:06:58.63#ibcon#about to read 6, iclass 33, count 0 2006.202.01:06:58.63#ibcon#read 6, iclass 33, count 0 2006.202.01:06:58.63#ibcon#end of sib2, iclass 33, count 0 2006.202.01:06:58.63#ibcon#*mode == 0, iclass 33, count 0 2006.202.01:06:58.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.01:06:58.63#ibcon#[25=BW32\r\n] 2006.202.01:06:58.63#ibcon#*before write, iclass 33, count 0 2006.202.01:06:58.63#ibcon#enter sib2, iclass 33, count 0 2006.202.01:06:58.63#ibcon#flushed, iclass 33, count 0 2006.202.01:06:58.63#ibcon#about to write, iclass 33, count 0 2006.202.01:06:58.63#ibcon#wrote, iclass 33, count 0 2006.202.01:06:58.63#ibcon#about to read 3, iclass 33, count 0 2006.202.01:06:58.66#ibcon#read 3, iclass 33, count 0 2006.202.01:06:58.66#ibcon#about to read 4, iclass 33, count 0 2006.202.01:06:58.66#ibcon#read 4, iclass 33, count 0 2006.202.01:06:58.66#ibcon#about to read 5, iclass 33, count 0 2006.202.01:06:58.66#ibcon#read 5, iclass 33, count 0 2006.202.01:06:58.66#ibcon#about to read 6, iclass 33, count 0 2006.202.01:06:58.66#ibcon#read 6, iclass 33, count 0 2006.202.01:06:58.66#ibcon#end of sib2, iclass 33, count 0 2006.202.01:06:58.66#ibcon#*after write, iclass 33, count 0 2006.202.01:06:58.66#ibcon#*before return 0, iclass 33, count 0 2006.202.01:06:58.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:58.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:06:58.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.01:06:58.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.01:06:58.66$vck44/vbbw=wide 2006.202.01:06:58.66#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.202.01:06:58.66#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.202.01:06:58.66#ibcon#ireg 8 cls_cnt 0 2006.202.01:06:58.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:06:58.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:06:58.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:06:58.73#ibcon#enter wrdev, iclass 35, count 0 2006.202.01:06:58.73#ibcon#first serial, iclass 35, count 0 2006.202.01:06:58.73#ibcon#enter sib2, iclass 35, count 0 2006.202.01:06:58.73#ibcon#flushed, iclass 35, count 0 2006.202.01:06:58.73#ibcon#about to write, iclass 35, count 0 2006.202.01:06:58.73#ibcon#wrote, iclass 35, count 0 2006.202.01:06:58.73#ibcon#about to read 3, iclass 35, count 0 2006.202.01:06:58.75#ibcon#read 3, iclass 35, count 0 2006.202.01:06:58.75#ibcon#about to read 4, iclass 35, count 0 2006.202.01:06:58.75#ibcon#read 4, iclass 35, count 0 2006.202.01:06:58.75#ibcon#about to read 5, iclass 35, count 0 2006.202.01:06:58.75#ibcon#read 5, iclass 35, count 0 2006.202.01:06:58.75#ibcon#about to read 6, iclass 35, count 0 2006.202.01:06:58.75#ibcon#read 6, iclass 35, count 0 2006.202.01:06:58.75#ibcon#end of sib2, iclass 35, count 0 2006.202.01:06:58.75#ibcon#*mode == 0, iclass 35, count 0 2006.202.01:06:58.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.01:06:58.75#ibcon#[27=BW32\r\n] 2006.202.01:06:58.75#ibcon#*before write, iclass 35, count 0 2006.202.01:06:58.75#ibcon#enter sib2, iclass 35, count 0 2006.202.01:06:58.75#ibcon#flushed, iclass 35, count 0 2006.202.01:06:58.75#ibcon#about to write, iclass 35, count 0 2006.202.01:06:58.75#ibcon#wrote, iclass 35, count 0 2006.202.01:06:58.75#ibcon#about to read 3, iclass 35, count 0 2006.202.01:06:58.78#ibcon#read 3, iclass 35, count 0 2006.202.01:06:58.78#ibcon#about to read 4, iclass 35, count 0 2006.202.01:06:58.78#ibcon#read 4, iclass 35, count 0 2006.202.01:06:58.78#ibcon#about to read 5, iclass 35, count 0 2006.202.01:06:58.78#ibcon#read 5, iclass 35, count 0 2006.202.01:06:58.78#ibcon#about to read 6, iclass 35, count 0 2006.202.01:06:58.78#ibcon#read 6, iclass 35, count 0 2006.202.01:06:58.78#ibcon#end of sib2, iclass 35, count 0 2006.202.01:06:58.78#ibcon#*after write, iclass 35, count 0 2006.202.01:06:58.88#ibcon#*before return 0, iclass 35, count 0 2006.202.01:06:58.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:06:58.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:06:58.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.01:06:58.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.01:06:58.88$setupk4/ifdk4 2006.202.01:06:58.88$ifdk4/lo= 2006.202.01:06:58.88$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.01:06:58.88$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.01:06:58.88$ifdk4/patch= 2006.202.01:06:58.88$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.01:06:58.88$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.01:06:58.88$setupk4/!*+20s 2006.202.01:07:07.18#abcon#<5=/04 2.7 5.4 20.391001000.9\r\n> 2006.202.01:07:07.20#abcon#{5=INTERFACE CLEAR} 2006.202.01:07:07.26#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:07:13.23$setupk4/"tpicd 2006.202.01:07:13.23$setupk4/echo=off 2006.202.01:07:13.23$setupk4/xlog=off 2006.202.01:07:13.23:!2006.202.01:09:50 2006.202.01:07:54.14#trakl#Source acquired 2006.202.01:07:54.14#flagr#flagr/antenna,acquired 2006.202.01:09:50.00:preob 2006.202.01:09:50.14/onsource/TRACKING 2006.202.01:09:50.14:!2006.202.01:10:00 2006.202.01:10:00.00:"tape 2006.202.01:10:00.00:"st=record 2006.202.01:10:00.00:data_valid=on 2006.202.01:10:00.00:midob 2006.202.01:10:01.14/onsource/TRACKING 2006.202.01:10:01.14/wx/20.42,1000.9,100 2006.202.01:10:01.23/cable/+6.4827E-03 2006.202.01:10:02.32/va/01,08,usb,yes,45,48 2006.202.01:10:02.32/va/02,07,usb,yes,49,50 2006.202.01:10:02.32/va/03,08,usb,yes,44,46 2006.202.01:10:02.32/va/04,07,usb,yes,50,53 2006.202.01:10:02.32/va/05,04,usb,yes,45,46 2006.202.01:10:02.32/va/06,05,usb,yes,45,45 2006.202.01:10:02.32/va/07,05,usb,yes,44,46 2006.202.01:10:02.32/va/08,04,usb,yes,44,52 2006.202.01:10:02.55/valo/01,524.99,yes,locked 2006.202.01:10:02.55/valo/02,534.99,yes,locked 2006.202.01:10:02.55/valo/03,564.99,yes,locked 2006.202.01:10:02.55/valo/04,624.99,yes,locked 2006.202.01:10:02.55/valo/05,734.99,yes,locked 2006.202.01:10:02.55/valo/06,814.99,yes,locked 2006.202.01:10:02.55/valo/07,864.99,yes,locked 2006.202.01:10:02.55/valo/08,884.99,yes,locked 2006.202.01:10:03.64/vb/01,04,usb,yes,32,30 2006.202.01:10:03.64/vb/02,05,usb,yes,30,30 2006.202.01:10:03.64/vb/03,04,usb,yes,31,35 2006.202.01:10:03.64/vb/04,05,usb,yes,32,31 2006.202.01:10:03.64/vb/05,04,usb,yes,28,31 2006.202.01:10:03.64/vb/06,04,usb,yes,33,29 2006.202.01:10:03.64/vb/07,04,usb,yes,33,33 2006.202.01:10:03.64/vb/08,04,usb,yes,30,34 2006.202.01:10:03.88/vblo/01,629.99,yes,locked 2006.202.01:10:03.88/vblo/02,634.99,yes,locked 2006.202.01:10:03.88/vblo/03,649.99,yes,locked 2006.202.01:10:03.88/vblo/04,679.99,yes,locked 2006.202.01:10:03.88/vblo/05,709.99,yes,locked 2006.202.01:10:03.88/vblo/06,719.99,yes,locked 2006.202.01:10:03.88/vblo/07,734.99,yes,locked 2006.202.01:10:03.88/vblo/08,744.99,yes,locked 2006.202.01:10:04.03/vabw/8 2006.202.01:10:04.18/vbbw/8 2006.202.01:10:04.27/xfe/off,on,16.2 2006.202.01:10:04.64/ifatt/23,28,28,28 2006.202.01:10:05.07/fmout-gps/S +4.50E-07 2006.202.01:10:05.11:!2006.202.01:19:00 2006.202.01:11:20.14#trakl#Off source 2006.202.01:11:20.14?ERROR st -7 Antenna off-source! 2006.202.01:11:20.14#trakl#az 57.518 el 10.607 azerr*cos(el) 0.0189 elerr 0.0061 2006.202.01:11:21.14#flagr#flagr/antenna,off-source 2006.202.01:11:26.14#trakl#Source re-acquired 2006.202.01:11:27.14#flagr#flagr/antenna,re-acquired 2006.202.01:19:00.00:data_valid=off 2006.202.01:19:00.00:"et 2006.202.01:19:00.00:!+3s 2006.202.01:19:03.02:"tape 2006.202.01:19:03.02:postob 2006.202.01:19:03.09/cable/+6.4821E-03 2006.202.01:19:03.09/wx/20.44,1000.8,100 2006.202.01:19:03.15/fmout-gps/S +4.51E-07 2006.202.01:19:03.15:scan_name=202-0119,jd0607,190 2006.202.01:19:03.15:source=3c274,123049.42,122328.0,2000.0,ccw 2006.202.01:19:04.14#flagr#flagr/antenna,new-source 2006.202.01:19:04.14:checkk5 2006.202.01:19:04.54/chk_autoobs//k5ts1/ autoobs is running! 2006.202.01:19:04.95/chk_autoobs//k5ts2/ autoobs is running! 2006.202.01:19:05.36/chk_autoobs//k5ts3/ autoobs is running! 2006.202.01:19:05.77/chk_autoobs//k5ts4/ autoobs is running! 2006.202.01:19:06.45/chk_obsdata//k5ts1/T2020110??a.dat file size is correct (nominal:2160MB, actual:2156MB). 2006.202.01:19:07.16/chk_obsdata//k5ts2/T2020110??b.dat file size is correct (nominal:2160MB, actual:2156MB). 2006.202.01:19:07.87/chk_obsdata//k5ts3/T2020110??c.dat file size is correct (nominal:2160MB, actual:2156MB). 2006.202.01:19:08.58/chk_obsdata//k5ts4/T2020110??d.dat file size is correct (nominal:2160MB, actual:2156MB). 2006.202.01:19:09.30/k5log//k5ts1_log_newline 2006.202.01:19:10.03/k5log//k5ts2_log_newline 2006.202.01:19:10.74/k5log//k5ts3_log_newline 2006.202.01:19:11.47/k5log//k5ts4_log_newline 2006.202.01:19:11.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.01:19:11.49:setupk4=1 2006.202.01:19:11.49$setupk4/echo=on 2006.202.01:19:11.49$setupk4/pcalon 2006.202.01:19:11.49$pcalon/"no phase cal control is implemented here 2006.202.01:19:11.49$setupk4/"tpicd=stop 2006.202.01:19:11.49$setupk4/"rec=synch_on 2006.202.01:19:11.49$setupk4/"rec_mode=128 2006.202.01:19:11.49$setupk4/!* 2006.202.01:19:11.49$setupk4/recpk4 2006.202.01:19:11.49$recpk4/recpatch= 2006.202.01:19:11.50$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.01:19:11.50$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.01:19:11.50$setupk4/vck44 2006.202.01:19:11.50$vck44/valo=1,524.99 2006.202.01:19:11.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.01:19:11.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.01:19:11.50#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:11.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:11.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:11.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:11.50#ibcon#enter wrdev, iclass 4, count 0 2006.202.01:19:11.50#ibcon#first serial, iclass 4, count 0 2006.202.01:19:11.50#ibcon#enter sib2, iclass 4, count 0 2006.202.01:19:11.50#ibcon#flushed, iclass 4, count 0 2006.202.01:19:11.50#ibcon#about to write, iclass 4, count 0 2006.202.01:19:11.50#ibcon#wrote, iclass 4, count 0 2006.202.01:19:11.50#ibcon#about to read 3, iclass 4, count 0 2006.202.01:19:11.52#ibcon#read 3, iclass 4, count 0 2006.202.01:19:11.52#ibcon#about to read 4, iclass 4, count 0 2006.202.01:19:11.52#ibcon#read 4, iclass 4, count 0 2006.202.01:19:11.52#ibcon#about to read 5, iclass 4, count 0 2006.202.01:19:11.52#ibcon#read 5, iclass 4, count 0 2006.202.01:19:11.52#ibcon#about to read 6, iclass 4, count 0 2006.202.01:19:11.52#ibcon#read 6, iclass 4, count 0 2006.202.01:19:11.52#ibcon#end of sib2, iclass 4, count 0 2006.202.01:19:11.52#ibcon#*mode == 0, iclass 4, count 0 2006.202.01:19:11.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.01:19:11.52#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.01:19:11.52#ibcon#*before write, iclass 4, count 0 2006.202.01:19:11.52#ibcon#enter sib2, iclass 4, count 0 2006.202.01:19:11.52#ibcon#flushed, iclass 4, count 0 2006.202.01:19:11.52#ibcon#about to write, iclass 4, count 0 2006.202.01:19:11.52#ibcon#wrote, iclass 4, count 0 2006.202.01:19:11.52#ibcon#about to read 3, iclass 4, count 0 2006.202.01:19:11.57#ibcon#read 3, iclass 4, count 0 2006.202.01:19:11.57#ibcon#about to read 4, iclass 4, count 0 2006.202.01:19:11.57#ibcon#read 4, iclass 4, count 0 2006.202.01:19:11.57#ibcon#about to read 5, iclass 4, count 0 2006.202.01:19:11.57#ibcon#read 5, iclass 4, count 0 2006.202.01:19:11.57#ibcon#about to read 6, iclass 4, count 0 2006.202.01:19:11.57#ibcon#read 6, iclass 4, count 0 2006.202.01:19:11.57#ibcon#end of sib2, iclass 4, count 0 2006.202.01:19:11.57#ibcon#*after write, iclass 4, count 0 2006.202.01:19:11.57#ibcon#*before return 0, iclass 4, count 0 2006.202.01:19:11.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:11.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:11.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.01:19:11.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.01:19:11.57$vck44/va=1,8 2006.202.01:19:11.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.202.01:19:11.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.202.01:19:11.57#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:11.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:11.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:11.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:11.57#ibcon#enter wrdev, iclass 6, count 2 2006.202.01:19:11.57#ibcon#first serial, iclass 6, count 2 2006.202.01:19:11.57#ibcon#enter sib2, iclass 6, count 2 2006.202.01:19:11.57#ibcon#flushed, iclass 6, count 2 2006.202.01:19:11.57#ibcon#about to write, iclass 6, count 2 2006.202.01:19:11.57#ibcon#wrote, iclass 6, count 2 2006.202.01:19:11.57#ibcon#about to read 3, iclass 6, count 2 2006.202.01:19:11.59#ibcon#read 3, iclass 6, count 2 2006.202.01:19:11.59#ibcon#about to read 4, iclass 6, count 2 2006.202.01:19:11.59#ibcon#read 4, iclass 6, count 2 2006.202.01:19:11.59#ibcon#about to read 5, iclass 6, count 2 2006.202.01:19:11.59#ibcon#read 5, iclass 6, count 2 2006.202.01:19:11.59#ibcon#about to read 6, iclass 6, count 2 2006.202.01:19:11.59#ibcon#read 6, iclass 6, count 2 2006.202.01:19:11.59#ibcon#end of sib2, iclass 6, count 2 2006.202.01:19:11.59#ibcon#*mode == 0, iclass 6, count 2 2006.202.01:19:11.59#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.202.01:19:11.59#ibcon#[25=AT01-08\r\n] 2006.202.01:19:11.59#ibcon#*before write, iclass 6, count 2 2006.202.01:19:11.59#ibcon#enter sib2, iclass 6, count 2 2006.202.01:19:11.59#ibcon#flushed, iclass 6, count 2 2006.202.01:19:11.59#ibcon#about to write, iclass 6, count 2 2006.202.01:19:11.59#ibcon#wrote, iclass 6, count 2 2006.202.01:19:11.59#ibcon#about to read 3, iclass 6, count 2 2006.202.01:19:11.62#ibcon#read 3, iclass 6, count 2 2006.202.01:19:11.62#ibcon#about to read 4, iclass 6, count 2 2006.202.01:19:11.62#ibcon#read 4, iclass 6, count 2 2006.202.01:19:11.62#ibcon#about to read 5, iclass 6, count 2 2006.202.01:19:11.62#ibcon#read 5, iclass 6, count 2 2006.202.01:19:11.62#ibcon#about to read 6, iclass 6, count 2 2006.202.01:19:11.62#ibcon#read 6, iclass 6, count 2 2006.202.01:19:11.62#ibcon#end of sib2, iclass 6, count 2 2006.202.01:19:11.62#ibcon#*after write, iclass 6, count 2 2006.202.01:19:11.62#ibcon#*before return 0, iclass 6, count 2 2006.202.01:19:11.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:11.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:11.62#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.202.01:19:11.62#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:11.62#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:11.74#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:11.74#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:11.74#ibcon#enter wrdev, iclass 6, count 0 2006.202.01:19:11.74#ibcon#first serial, iclass 6, count 0 2006.202.01:19:11.74#ibcon#enter sib2, iclass 6, count 0 2006.202.01:19:11.74#ibcon#flushed, iclass 6, count 0 2006.202.01:19:11.74#ibcon#about to write, iclass 6, count 0 2006.202.01:19:11.74#ibcon#wrote, iclass 6, count 0 2006.202.01:19:11.74#ibcon#about to read 3, iclass 6, count 0 2006.202.01:19:11.76#ibcon#read 3, iclass 6, count 0 2006.202.01:19:11.76#ibcon#about to read 4, iclass 6, count 0 2006.202.01:19:11.76#ibcon#read 4, iclass 6, count 0 2006.202.01:19:11.76#ibcon#about to read 5, iclass 6, count 0 2006.202.01:19:11.76#ibcon#read 5, iclass 6, count 0 2006.202.01:19:11.76#ibcon#about to read 6, iclass 6, count 0 2006.202.01:19:11.76#ibcon#read 6, iclass 6, count 0 2006.202.01:19:11.76#ibcon#end of sib2, iclass 6, count 0 2006.202.01:19:11.76#ibcon#*mode == 0, iclass 6, count 0 2006.202.01:19:11.76#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.01:19:11.76#ibcon#[25=USB\r\n] 2006.202.01:19:11.76#ibcon#*before write, iclass 6, count 0 2006.202.01:19:11.76#ibcon#enter sib2, iclass 6, count 0 2006.202.01:19:11.76#ibcon#flushed, iclass 6, count 0 2006.202.01:19:11.76#ibcon#about to write, iclass 6, count 0 2006.202.01:19:11.76#ibcon#wrote, iclass 6, count 0 2006.202.01:19:11.76#ibcon#about to read 3, iclass 6, count 0 2006.202.01:19:11.79#ibcon#read 3, iclass 6, count 0 2006.202.01:19:11.79#ibcon#about to read 4, iclass 6, count 0 2006.202.01:19:11.79#ibcon#read 4, iclass 6, count 0 2006.202.01:19:11.79#ibcon#about to read 5, iclass 6, count 0 2006.202.01:19:11.79#ibcon#read 5, iclass 6, count 0 2006.202.01:19:11.79#ibcon#about to read 6, iclass 6, count 0 2006.202.01:19:11.79#ibcon#read 6, iclass 6, count 0 2006.202.01:19:11.79#ibcon#end of sib2, iclass 6, count 0 2006.202.01:19:11.79#ibcon#*after write, iclass 6, count 0 2006.202.01:19:11.79#ibcon#*before return 0, iclass 6, count 0 2006.202.01:19:11.79#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:11.79#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:11.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.01:19:11.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.01:19:11.79$vck44/valo=2,534.99 2006.202.01:19:11.79#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.01:19:11.79#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.01:19:11.79#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:11.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:11.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:11.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:11.79#ibcon#enter wrdev, iclass 10, count 0 2006.202.01:19:11.79#ibcon#first serial, iclass 10, count 0 2006.202.01:19:11.79#ibcon#enter sib2, iclass 10, count 0 2006.202.01:19:11.79#ibcon#flushed, iclass 10, count 0 2006.202.01:19:11.79#ibcon#about to write, iclass 10, count 0 2006.202.01:19:11.79#ibcon#wrote, iclass 10, count 0 2006.202.01:19:11.79#ibcon#about to read 3, iclass 10, count 0 2006.202.01:19:11.81#ibcon#read 3, iclass 10, count 0 2006.202.01:19:11.81#ibcon#about to read 4, iclass 10, count 0 2006.202.01:19:11.81#ibcon#read 4, iclass 10, count 0 2006.202.01:19:11.81#ibcon#about to read 5, iclass 10, count 0 2006.202.01:19:11.81#ibcon#read 5, iclass 10, count 0 2006.202.01:19:11.81#ibcon#about to read 6, iclass 10, count 0 2006.202.01:19:11.81#ibcon#read 6, iclass 10, count 0 2006.202.01:19:11.81#ibcon#end of sib2, iclass 10, count 0 2006.202.01:19:11.81#ibcon#*mode == 0, iclass 10, count 0 2006.202.01:19:11.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.01:19:11.81#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.01:19:11.81#ibcon#*before write, iclass 10, count 0 2006.202.01:19:11.81#ibcon#enter sib2, iclass 10, count 0 2006.202.01:19:11.81#ibcon#flushed, iclass 10, count 0 2006.202.01:19:11.81#ibcon#about to write, iclass 10, count 0 2006.202.01:19:11.81#ibcon#wrote, iclass 10, count 0 2006.202.01:19:11.81#ibcon#about to read 3, iclass 10, count 0 2006.202.01:19:11.85#ibcon#read 3, iclass 10, count 0 2006.202.01:19:11.85#ibcon#about to read 4, iclass 10, count 0 2006.202.01:19:11.85#ibcon#read 4, iclass 10, count 0 2006.202.01:19:11.85#ibcon#about to read 5, iclass 10, count 0 2006.202.01:19:11.85#ibcon#read 5, iclass 10, count 0 2006.202.01:19:11.85#ibcon#about to read 6, iclass 10, count 0 2006.202.01:19:11.85#ibcon#read 6, iclass 10, count 0 2006.202.01:19:11.85#ibcon#end of sib2, iclass 10, count 0 2006.202.01:19:11.85#ibcon#*after write, iclass 10, count 0 2006.202.01:19:11.85#ibcon#*before return 0, iclass 10, count 0 2006.202.01:19:11.85#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:11.85#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:11.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.01:19:11.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.01:19:11.85$vck44/va=2,7 2006.202.01:19:11.85#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.202.01:19:11.85#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.202.01:19:11.85#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:11.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:11.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:11.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:11.91#ibcon#enter wrdev, iclass 12, count 2 2006.202.01:19:11.91#ibcon#first serial, iclass 12, count 2 2006.202.01:19:11.91#ibcon#enter sib2, iclass 12, count 2 2006.202.01:19:11.91#ibcon#flushed, iclass 12, count 2 2006.202.01:19:11.91#ibcon#about to write, iclass 12, count 2 2006.202.01:19:11.91#ibcon#wrote, iclass 12, count 2 2006.202.01:19:11.91#ibcon#about to read 3, iclass 12, count 2 2006.202.01:19:11.93#ibcon#read 3, iclass 12, count 2 2006.202.01:19:11.93#ibcon#about to read 4, iclass 12, count 2 2006.202.01:19:11.93#ibcon#read 4, iclass 12, count 2 2006.202.01:19:11.93#ibcon#about to read 5, iclass 12, count 2 2006.202.01:19:11.93#ibcon#read 5, iclass 12, count 2 2006.202.01:19:11.93#ibcon#about to read 6, iclass 12, count 2 2006.202.01:19:11.93#ibcon#read 6, iclass 12, count 2 2006.202.01:19:11.93#ibcon#end of sib2, iclass 12, count 2 2006.202.01:19:11.93#ibcon#*mode == 0, iclass 12, count 2 2006.202.01:19:11.93#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.202.01:19:11.93#ibcon#[25=AT02-07\r\n] 2006.202.01:19:11.93#ibcon#*before write, iclass 12, count 2 2006.202.01:19:11.93#ibcon#enter sib2, iclass 12, count 2 2006.202.01:19:11.93#ibcon#flushed, iclass 12, count 2 2006.202.01:19:11.93#ibcon#about to write, iclass 12, count 2 2006.202.01:19:11.93#ibcon#wrote, iclass 12, count 2 2006.202.01:19:11.93#ibcon#about to read 3, iclass 12, count 2 2006.202.01:19:11.96#ibcon#read 3, iclass 12, count 2 2006.202.01:19:11.96#ibcon#about to read 4, iclass 12, count 2 2006.202.01:19:11.96#ibcon#read 4, iclass 12, count 2 2006.202.01:19:11.96#ibcon#about to read 5, iclass 12, count 2 2006.202.01:19:11.96#ibcon#read 5, iclass 12, count 2 2006.202.01:19:11.96#ibcon#about to read 6, iclass 12, count 2 2006.202.01:19:11.96#ibcon#read 6, iclass 12, count 2 2006.202.01:19:11.96#ibcon#end of sib2, iclass 12, count 2 2006.202.01:19:11.96#ibcon#*after write, iclass 12, count 2 2006.202.01:19:11.96#ibcon#*before return 0, iclass 12, count 2 2006.202.01:19:11.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:11.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:11.96#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.202.01:19:11.96#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:11.96#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:12.08#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:12.08#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:12.08#ibcon#enter wrdev, iclass 12, count 0 2006.202.01:19:12.08#ibcon#first serial, iclass 12, count 0 2006.202.01:19:12.08#ibcon#enter sib2, iclass 12, count 0 2006.202.01:19:12.08#ibcon#flushed, iclass 12, count 0 2006.202.01:19:12.08#ibcon#about to write, iclass 12, count 0 2006.202.01:19:12.08#ibcon#wrote, iclass 12, count 0 2006.202.01:19:12.08#ibcon#about to read 3, iclass 12, count 0 2006.202.01:19:12.10#ibcon#read 3, iclass 12, count 0 2006.202.01:19:12.10#ibcon#about to read 4, iclass 12, count 0 2006.202.01:19:12.10#ibcon#read 4, iclass 12, count 0 2006.202.01:19:12.10#ibcon#about to read 5, iclass 12, count 0 2006.202.01:19:12.10#ibcon#read 5, iclass 12, count 0 2006.202.01:19:12.10#ibcon#about to read 6, iclass 12, count 0 2006.202.01:19:12.10#ibcon#read 6, iclass 12, count 0 2006.202.01:19:12.10#ibcon#end of sib2, iclass 12, count 0 2006.202.01:19:12.10#ibcon#*mode == 0, iclass 12, count 0 2006.202.01:19:12.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.01:19:12.10#ibcon#[25=USB\r\n] 2006.202.01:19:12.10#ibcon#*before write, iclass 12, count 0 2006.202.01:19:12.10#ibcon#enter sib2, iclass 12, count 0 2006.202.01:19:12.10#ibcon#flushed, iclass 12, count 0 2006.202.01:19:12.10#ibcon#about to write, iclass 12, count 0 2006.202.01:19:12.10#ibcon#wrote, iclass 12, count 0 2006.202.01:19:12.10#ibcon#about to read 3, iclass 12, count 0 2006.202.01:19:12.13#ibcon#read 3, iclass 12, count 0 2006.202.01:19:12.13#ibcon#about to read 4, iclass 12, count 0 2006.202.01:19:12.13#ibcon#read 4, iclass 12, count 0 2006.202.01:19:12.13#ibcon#about to read 5, iclass 12, count 0 2006.202.01:19:12.13#ibcon#read 5, iclass 12, count 0 2006.202.01:19:12.13#ibcon#about to read 6, iclass 12, count 0 2006.202.01:19:12.13#ibcon#read 6, iclass 12, count 0 2006.202.01:19:12.13#ibcon#end of sib2, iclass 12, count 0 2006.202.01:19:12.13#ibcon#*after write, iclass 12, count 0 2006.202.01:19:12.13#ibcon#*before return 0, iclass 12, count 0 2006.202.01:19:12.13#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:12.13#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:12.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.01:19:12.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.01:19:12.13$vck44/valo=3,564.99 2006.202.01:19:12.13#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.01:19:12.13#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.01:19:12.13#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:12.13#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:12.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:12.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:12.13#ibcon#enter wrdev, iclass 14, count 0 2006.202.01:19:12.13#ibcon#first serial, iclass 14, count 0 2006.202.01:19:12.13#ibcon#enter sib2, iclass 14, count 0 2006.202.01:19:12.13#ibcon#flushed, iclass 14, count 0 2006.202.01:19:12.13#ibcon#about to write, iclass 14, count 0 2006.202.01:19:12.13#ibcon#wrote, iclass 14, count 0 2006.202.01:19:12.13#ibcon#about to read 3, iclass 14, count 0 2006.202.01:19:12.15#ibcon#read 3, iclass 14, count 0 2006.202.01:19:12.15#ibcon#about to read 4, iclass 14, count 0 2006.202.01:19:12.15#ibcon#read 4, iclass 14, count 0 2006.202.01:19:12.15#ibcon#about to read 5, iclass 14, count 0 2006.202.01:19:12.15#ibcon#read 5, iclass 14, count 0 2006.202.01:19:12.15#ibcon#about to read 6, iclass 14, count 0 2006.202.01:19:12.15#ibcon#read 6, iclass 14, count 0 2006.202.01:19:12.15#ibcon#end of sib2, iclass 14, count 0 2006.202.01:19:12.15#ibcon#*mode == 0, iclass 14, count 0 2006.202.01:19:12.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.01:19:12.15#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.01:19:12.15#ibcon#*before write, iclass 14, count 0 2006.202.01:19:12.15#ibcon#enter sib2, iclass 14, count 0 2006.202.01:19:12.15#ibcon#flushed, iclass 14, count 0 2006.202.01:19:12.15#ibcon#about to write, iclass 14, count 0 2006.202.01:19:12.15#ibcon#wrote, iclass 14, count 0 2006.202.01:19:12.15#ibcon#about to read 3, iclass 14, count 0 2006.202.01:19:12.19#ibcon#read 3, iclass 14, count 0 2006.202.01:19:12.19#ibcon#about to read 4, iclass 14, count 0 2006.202.01:19:12.19#ibcon#read 4, iclass 14, count 0 2006.202.01:19:12.19#ibcon#about to read 5, iclass 14, count 0 2006.202.01:19:12.19#ibcon#read 5, iclass 14, count 0 2006.202.01:19:12.19#ibcon#about to read 6, iclass 14, count 0 2006.202.01:19:12.19#ibcon#read 6, iclass 14, count 0 2006.202.01:19:12.19#ibcon#end of sib2, iclass 14, count 0 2006.202.01:19:12.19#ibcon#*after write, iclass 14, count 0 2006.202.01:19:12.19#ibcon#*before return 0, iclass 14, count 0 2006.202.01:19:12.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:12.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:12.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.01:19:12.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.01:19:12.19$vck44/va=3,8 2006.202.01:19:12.19#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.01:19:12.19#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.01:19:12.19#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:12.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:12.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:12.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:12.25#ibcon#enter wrdev, iclass 16, count 2 2006.202.01:19:12.25#ibcon#first serial, iclass 16, count 2 2006.202.01:19:12.25#ibcon#enter sib2, iclass 16, count 2 2006.202.01:19:12.25#ibcon#flushed, iclass 16, count 2 2006.202.01:19:12.25#ibcon#about to write, iclass 16, count 2 2006.202.01:19:12.25#ibcon#wrote, iclass 16, count 2 2006.202.01:19:12.25#ibcon#about to read 3, iclass 16, count 2 2006.202.01:19:12.27#ibcon#read 3, iclass 16, count 2 2006.202.01:19:12.27#ibcon#about to read 4, iclass 16, count 2 2006.202.01:19:12.27#ibcon#read 4, iclass 16, count 2 2006.202.01:19:12.27#ibcon#about to read 5, iclass 16, count 2 2006.202.01:19:12.27#ibcon#read 5, iclass 16, count 2 2006.202.01:19:12.27#ibcon#about to read 6, iclass 16, count 2 2006.202.01:19:12.27#ibcon#read 6, iclass 16, count 2 2006.202.01:19:12.27#ibcon#end of sib2, iclass 16, count 2 2006.202.01:19:12.27#ibcon#*mode == 0, iclass 16, count 2 2006.202.01:19:12.27#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.01:19:12.27#ibcon#[25=AT03-08\r\n] 2006.202.01:19:12.27#ibcon#*before write, iclass 16, count 2 2006.202.01:19:12.27#ibcon#enter sib2, iclass 16, count 2 2006.202.01:19:12.27#ibcon#flushed, iclass 16, count 2 2006.202.01:19:12.27#ibcon#about to write, iclass 16, count 2 2006.202.01:19:12.27#ibcon#wrote, iclass 16, count 2 2006.202.01:19:12.27#ibcon#about to read 3, iclass 16, count 2 2006.202.01:19:12.30#ibcon#read 3, iclass 16, count 2 2006.202.01:19:12.30#ibcon#about to read 4, iclass 16, count 2 2006.202.01:19:12.30#ibcon#read 4, iclass 16, count 2 2006.202.01:19:12.30#ibcon#about to read 5, iclass 16, count 2 2006.202.01:19:12.30#ibcon#read 5, iclass 16, count 2 2006.202.01:19:12.30#ibcon#about to read 6, iclass 16, count 2 2006.202.01:19:12.30#ibcon#read 6, iclass 16, count 2 2006.202.01:19:12.30#ibcon#end of sib2, iclass 16, count 2 2006.202.01:19:12.30#ibcon#*after write, iclass 16, count 2 2006.202.01:19:12.30#ibcon#*before return 0, iclass 16, count 2 2006.202.01:19:12.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:12.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:12.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.01:19:12.30#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:12.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:12.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:12.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:12.42#ibcon#enter wrdev, iclass 16, count 0 2006.202.01:19:12.42#ibcon#first serial, iclass 16, count 0 2006.202.01:19:12.42#ibcon#enter sib2, iclass 16, count 0 2006.202.01:19:12.42#ibcon#flushed, iclass 16, count 0 2006.202.01:19:12.42#ibcon#about to write, iclass 16, count 0 2006.202.01:19:12.42#ibcon#wrote, iclass 16, count 0 2006.202.01:19:12.42#ibcon#about to read 3, iclass 16, count 0 2006.202.01:19:12.44#ibcon#read 3, iclass 16, count 0 2006.202.01:19:12.44#ibcon#about to read 4, iclass 16, count 0 2006.202.01:19:12.44#ibcon#read 4, iclass 16, count 0 2006.202.01:19:12.44#ibcon#about to read 5, iclass 16, count 0 2006.202.01:19:12.44#ibcon#read 5, iclass 16, count 0 2006.202.01:19:12.44#ibcon#about to read 6, iclass 16, count 0 2006.202.01:19:12.44#ibcon#read 6, iclass 16, count 0 2006.202.01:19:12.44#ibcon#end of sib2, iclass 16, count 0 2006.202.01:19:12.44#ibcon#*mode == 0, iclass 16, count 0 2006.202.01:19:12.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.01:19:12.44#ibcon#[25=USB\r\n] 2006.202.01:19:12.44#ibcon#*before write, iclass 16, count 0 2006.202.01:19:12.44#ibcon#enter sib2, iclass 16, count 0 2006.202.01:19:12.44#ibcon#flushed, iclass 16, count 0 2006.202.01:19:12.44#ibcon#about to write, iclass 16, count 0 2006.202.01:19:12.44#ibcon#wrote, iclass 16, count 0 2006.202.01:19:12.44#ibcon#about to read 3, iclass 16, count 0 2006.202.01:19:12.47#ibcon#read 3, iclass 16, count 0 2006.202.01:19:12.47#ibcon#about to read 4, iclass 16, count 0 2006.202.01:19:12.47#ibcon#read 4, iclass 16, count 0 2006.202.01:19:12.47#ibcon#about to read 5, iclass 16, count 0 2006.202.01:19:12.47#ibcon#read 5, iclass 16, count 0 2006.202.01:19:12.47#ibcon#about to read 6, iclass 16, count 0 2006.202.01:19:12.47#ibcon#read 6, iclass 16, count 0 2006.202.01:19:12.47#ibcon#end of sib2, iclass 16, count 0 2006.202.01:19:12.47#ibcon#*after write, iclass 16, count 0 2006.202.01:19:12.47#ibcon#*before return 0, iclass 16, count 0 2006.202.01:19:12.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:12.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:12.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.01:19:12.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.01:19:12.47$vck44/valo=4,624.99 2006.202.01:19:12.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.01:19:12.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.01:19:12.47#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:12.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:12.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:12.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:12.47#ibcon#enter wrdev, iclass 18, count 0 2006.202.01:19:12.47#ibcon#first serial, iclass 18, count 0 2006.202.01:19:12.47#ibcon#enter sib2, iclass 18, count 0 2006.202.01:19:12.47#ibcon#flushed, iclass 18, count 0 2006.202.01:19:12.47#ibcon#about to write, iclass 18, count 0 2006.202.01:19:12.47#ibcon#wrote, iclass 18, count 0 2006.202.01:19:12.47#ibcon#about to read 3, iclass 18, count 0 2006.202.01:19:12.49#ibcon#read 3, iclass 18, count 0 2006.202.01:19:12.49#ibcon#about to read 4, iclass 18, count 0 2006.202.01:19:12.49#ibcon#read 4, iclass 18, count 0 2006.202.01:19:12.49#ibcon#about to read 5, iclass 18, count 0 2006.202.01:19:12.49#ibcon#read 5, iclass 18, count 0 2006.202.01:19:12.49#ibcon#about to read 6, iclass 18, count 0 2006.202.01:19:12.49#ibcon#read 6, iclass 18, count 0 2006.202.01:19:12.49#ibcon#end of sib2, iclass 18, count 0 2006.202.01:19:12.49#ibcon#*mode == 0, iclass 18, count 0 2006.202.01:19:12.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.01:19:12.49#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.01:19:12.49#ibcon#*before write, iclass 18, count 0 2006.202.01:19:12.49#ibcon#enter sib2, iclass 18, count 0 2006.202.01:19:12.49#ibcon#flushed, iclass 18, count 0 2006.202.01:19:12.49#ibcon#about to write, iclass 18, count 0 2006.202.01:19:12.49#ibcon#wrote, iclass 18, count 0 2006.202.01:19:12.49#ibcon#about to read 3, iclass 18, count 0 2006.202.01:19:12.53#ibcon#read 3, iclass 18, count 0 2006.202.01:19:12.53#ibcon#about to read 4, iclass 18, count 0 2006.202.01:19:12.53#ibcon#read 4, iclass 18, count 0 2006.202.01:19:12.53#ibcon#about to read 5, iclass 18, count 0 2006.202.01:19:12.53#ibcon#read 5, iclass 18, count 0 2006.202.01:19:12.53#ibcon#about to read 6, iclass 18, count 0 2006.202.01:19:12.53#ibcon#read 6, iclass 18, count 0 2006.202.01:19:12.53#ibcon#end of sib2, iclass 18, count 0 2006.202.01:19:12.53#ibcon#*after write, iclass 18, count 0 2006.202.01:19:12.53#ibcon#*before return 0, iclass 18, count 0 2006.202.01:19:12.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:12.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:12.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.01:19:12.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.01:19:12.53$vck44/va=4,7 2006.202.01:19:12.53#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.01:19:12.53#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.01:19:12.53#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:12.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:12.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:12.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:12.59#ibcon#enter wrdev, iclass 20, count 2 2006.202.01:19:12.59#ibcon#first serial, iclass 20, count 2 2006.202.01:19:12.59#ibcon#enter sib2, iclass 20, count 2 2006.202.01:19:12.59#ibcon#flushed, iclass 20, count 2 2006.202.01:19:12.59#ibcon#about to write, iclass 20, count 2 2006.202.01:19:12.59#ibcon#wrote, iclass 20, count 2 2006.202.01:19:12.59#ibcon#about to read 3, iclass 20, count 2 2006.202.01:19:12.61#ibcon#read 3, iclass 20, count 2 2006.202.01:19:12.61#ibcon#about to read 4, iclass 20, count 2 2006.202.01:19:12.61#ibcon#read 4, iclass 20, count 2 2006.202.01:19:12.61#ibcon#about to read 5, iclass 20, count 2 2006.202.01:19:12.61#ibcon#read 5, iclass 20, count 2 2006.202.01:19:12.61#ibcon#about to read 6, iclass 20, count 2 2006.202.01:19:12.61#ibcon#read 6, iclass 20, count 2 2006.202.01:19:12.61#ibcon#end of sib2, iclass 20, count 2 2006.202.01:19:12.61#ibcon#*mode == 0, iclass 20, count 2 2006.202.01:19:12.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.01:19:12.61#ibcon#[25=AT04-07\r\n] 2006.202.01:19:12.61#ibcon#*before write, iclass 20, count 2 2006.202.01:19:12.61#ibcon#enter sib2, iclass 20, count 2 2006.202.01:19:12.61#ibcon#flushed, iclass 20, count 2 2006.202.01:19:12.61#ibcon#about to write, iclass 20, count 2 2006.202.01:19:12.61#ibcon#wrote, iclass 20, count 2 2006.202.01:19:12.61#ibcon#about to read 3, iclass 20, count 2 2006.202.01:19:12.64#ibcon#read 3, iclass 20, count 2 2006.202.01:19:12.64#ibcon#about to read 4, iclass 20, count 2 2006.202.01:19:12.64#ibcon#read 4, iclass 20, count 2 2006.202.01:19:12.64#ibcon#about to read 5, iclass 20, count 2 2006.202.01:19:12.64#ibcon#read 5, iclass 20, count 2 2006.202.01:19:12.64#ibcon#about to read 6, iclass 20, count 2 2006.202.01:19:12.64#ibcon#read 6, iclass 20, count 2 2006.202.01:19:12.64#ibcon#end of sib2, iclass 20, count 2 2006.202.01:19:12.64#ibcon#*after write, iclass 20, count 2 2006.202.01:19:12.64#ibcon#*before return 0, iclass 20, count 2 2006.202.01:19:12.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:12.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:12.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.01:19:12.64#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:12.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:12.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:12.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:12.76#ibcon#enter wrdev, iclass 20, count 0 2006.202.01:19:12.76#ibcon#first serial, iclass 20, count 0 2006.202.01:19:12.76#ibcon#enter sib2, iclass 20, count 0 2006.202.01:19:12.76#ibcon#flushed, iclass 20, count 0 2006.202.01:19:12.76#ibcon#about to write, iclass 20, count 0 2006.202.01:19:12.76#ibcon#wrote, iclass 20, count 0 2006.202.01:19:12.76#ibcon#about to read 3, iclass 20, count 0 2006.202.01:19:12.78#ibcon#read 3, iclass 20, count 0 2006.202.01:19:12.78#ibcon#about to read 4, iclass 20, count 0 2006.202.01:19:12.78#ibcon#read 4, iclass 20, count 0 2006.202.01:19:12.78#ibcon#about to read 5, iclass 20, count 0 2006.202.01:19:12.78#ibcon#read 5, iclass 20, count 0 2006.202.01:19:12.78#ibcon#about to read 6, iclass 20, count 0 2006.202.01:19:12.78#ibcon#read 6, iclass 20, count 0 2006.202.01:19:12.78#ibcon#end of sib2, iclass 20, count 0 2006.202.01:19:12.78#ibcon#*mode == 0, iclass 20, count 0 2006.202.01:19:12.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.01:19:12.78#ibcon#[25=USB\r\n] 2006.202.01:19:12.78#ibcon#*before write, iclass 20, count 0 2006.202.01:19:12.78#ibcon#enter sib2, iclass 20, count 0 2006.202.01:19:12.78#ibcon#flushed, iclass 20, count 0 2006.202.01:19:12.78#ibcon#about to write, iclass 20, count 0 2006.202.01:19:12.78#ibcon#wrote, iclass 20, count 0 2006.202.01:19:12.78#ibcon#about to read 3, iclass 20, count 0 2006.202.01:19:12.81#ibcon#read 3, iclass 20, count 0 2006.202.01:19:12.81#ibcon#about to read 4, iclass 20, count 0 2006.202.01:19:12.81#ibcon#read 4, iclass 20, count 0 2006.202.01:19:12.81#ibcon#about to read 5, iclass 20, count 0 2006.202.01:19:12.81#ibcon#read 5, iclass 20, count 0 2006.202.01:19:12.81#ibcon#about to read 6, iclass 20, count 0 2006.202.01:19:12.81#ibcon#read 6, iclass 20, count 0 2006.202.01:19:12.81#ibcon#end of sib2, iclass 20, count 0 2006.202.01:19:12.81#ibcon#*after write, iclass 20, count 0 2006.202.01:19:12.81#ibcon#*before return 0, iclass 20, count 0 2006.202.01:19:12.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:12.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:12.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.01:19:12.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.01:19:12.81$vck44/valo=5,734.99 2006.202.01:19:12.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.01:19:12.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.01:19:12.81#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:12.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:12.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:12.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:12.81#ibcon#enter wrdev, iclass 22, count 0 2006.202.01:19:12.81#ibcon#first serial, iclass 22, count 0 2006.202.01:19:12.81#ibcon#enter sib2, iclass 22, count 0 2006.202.01:19:12.81#ibcon#flushed, iclass 22, count 0 2006.202.01:19:12.81#ibcon#about to write, iclass 22, count 0 2006.202.01:19:12.81#ibcon#wrote, iclass 22, count 0 2006.202.01:19:12.81#ibcon#about to read 3, iclass 22, count 0 2006.202.01:19:12.83#ibcon#read 3, iclass 22, count 0 2006.202.01:19:12.83#ibcon#about to read 4, iclass 22, count 0 2006.202.01:19:12.83#ibcon#read 4, iclass 22, count 0 2006.202.01:19:12.83#ibcon#about to read 5, iclass 22, count 0 2006.202.01:19:12.83#ibcon#read 5, iclass 22, count 0 2006.202.01:19:12.83#ibcon#about to read 6, iclass 22, count 0 2006.202.01:19:12.83#ibcon#read 6, iclass 22, count 0 2006.202.01:19:12.83#ibcon#end of sib2, iclass 22, count 0 2006.202.01:19:12.83#ibcon#*mode == 0, iclass 22, count 0 2006.202.01:19:12.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.01:19:12.83#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.01:19:12.83#ibcon#*before write, iclass 22, count 0 2006.202.01:19:12.83#ibcon#enter sib2, iclass 22, count 0 2006.202.01:19:12.83#ibcon#flushed, iclass 22, count 0 2006.202.01:19:12.83#ibcon#about to write, iclass 22, count 0 2006.202.01:19:12.83#ibcon#wrote, iclass 22, count 0 2006.202.01:19:12.83#ibcon#about to read 3, iclass 22, count 0 2006.202.01:19:12.87#ibcon#read 3, iclass 22, count 0 2006.202.01:19:12.87#ibcon#about to read 4, iclass 22, count 0 2006.202.01:19:12.87#ibcon#read 4, iclass 22, count 0 2006.202.01:19:12.87#ibcon#about to read 5, iclass 22, count 0 2006.202.01:19:12.87#ibcon#read 5, iclass 22, count 0 2006.202.01:19:12.87#ibcon#about to read 6, iclass 22, count 0 2006.202.01:19:12.87#ibcon#read 6, iclass 22, count 0 2006.202.01:19:12.87#ibcon#end of sib2, iclass 22, count 0 2006.202.01:19:12.87#ibcon#*after write, iclass 22, count 0 2006.202.01:19:12.87#ibcon#*before return 0, iclass 22, count 0 2006.202.01:19:12.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:12.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:12.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.01:19:12.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.01:19:12.87$vck44/va=5,4 2006.202.01:19:12.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.01:19:12.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.01:19:12.87#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:12.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:12.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:12.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:12.93#ibcon#enter wrdev, iclass 24, count 2 2006.202.01:19:12.93#ibcon#first serial, iclass 24, count 2 2006.202.01:19:12.93#ibcon#enter sib2, iclass 24, count 2 2006.202.01:19:12.93#ibcon#flushed, iclass 24, count 2 2006.202.01:19:12.93#ibcon#about to write, iclass 24, count 2 2006.202.01:19:12.93#ibcon#wrote, iclass 24, count 2 2006.202.01:19:12.93#ibcon#about to read 3, iclass 24, count 2 2006.202.01:19:12.95#ibcon#read 3, iclass 24, count 2 2006.202.01:19:12.95#ibcon#about to read 4, iclass 24, count 2 2006.202.01:19:12.95#ibcon#read 4, iclass 24, count 2 2006.202.01:19:12.95#ibcon#about to read 5, iclass 24, count 2 2006.202.01:19:12.95#ibcon#read 5, iclass 24, count 2 2006.202.01:19:12.95#ibcon#about to read 6, iclass 24, count 2 2006.202.01:19:12.95#ibcon#read 6, iclass 24, count 2 2006.202.01:19:12.95#ibcon#end of sib2, iclass 24, count 2 2006.202.01:19:12.95#ibcon#*mode == 0, iclass 24, count 2 2006.202.01:19:12.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.01:19:12.95#ibcon#[25=AT05-04\r\n] 2006.202.01:19:12.95#ibcon#*before write, iclass 24, count 2 2006.202.01:19:12.95#ibcon#enter sib2, iclass 24, count 2 2006.202.01:19:12.95#ibcon#flushed, iclass 24, count 2 2006.202.01:19:12.95#ibcon#about to write, iclass 24, count 2 2006.202.01:19:12.95#ibcon#wrote, iclass 24, count 2 2006.202.01:19:12.95#ibcon#about to read 3, iclass 24, count 2 2006.202.01:19:12.98#ibcon#read 3, iclass 24, count 2 2006.202.01:19:12.98#ibcon#about to read 4, iclass 24, count 2 2006.202.01:19:12.98#ibcon#read 4, iclass 24, count 2 2006.202.01:19:12.98#ibcon#about to read 5, iclass 24, count 2 2006.202.01:19:12.98#ibcon#read 5, iclass 24, count 2 2006.202.01:19:12.98#ibcon#about to read 6, iclass 24, count 2 2006.202.01:19:12.98#ibcon#read 6, iclass 24, count 2 2006.202.01:19:12.98#ibcon#end of sib2, iclass 24, count 2 2006.202.01:19:12.98#ibcon#*after write, iclass 24, count 2 2006.202.01:19:12.98#ibcon#*before return 0, iclass 24, count 2 2006.202.01:19:12.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:12.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:12.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.01:19:12.98#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:12.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:13.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:13.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:13.10#ibcon#enter wrdev, iclass 24, count 0 2006.202.01:19:13.10#ibcon#first serial, iclass 24, count 0 2006.202.01:19:13.10#ibcon#enter sib2, iclass 24, count 0 2006.202.01:19:13.10#ibcon#flushed, iclass 24, count 0 2006.202.01:19:13.10#ibcon#about to write, iclass 24, count 0 2006.202.01:19:13.10#ibcon#wrote, iclass 24, count 0 2006.202.01:19:13.10#ibcon#about to read 3, iclass 24, count 0 2006.202.01:19:13.12#ibcon#read 3, iclass 24, count 0 2006.202.01:19:13.12#ibcon#about to read 4, iclass 24, count 0 2006.202.01:19:13.12#ibcon#read 4, iclass 24, count 0 2006.202.01:19:13.12#ibcon#about to read 5, iclass 24, count 0 2006.202.01:19:13.12#ibcon#read 5, iclass 24, count 0 2006.202.01:19:13.12#ibcon#about to read 6, iclass 24, count 0 2006.202.01:19:13.12#ibcon#read 6, iclass 24, count 0 2006.202.01:19:13.12#ibcon#end of sib2, iclass 24, count 0 2006.202.01:19:13.12#ibcon#*mode == 0, iclass 24, count 0 2006.202.01:19:13.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.01:19:13.12#ibcon#[25=USB\r\n] 2006.202.01:19:13.12#ibcon#*before write, iclass 24, count 0 2006.202.01:19:13.12#ibcon#enter sib2, iclass 24, count 0 2006.202.01:19:13.12#ibcon#flushed, iclass 24, count 0 2006.202.01:19:13.12#ibcon#about to write, iclass 24, count 0 2006.202.01:19:13.12#ibcon#wrote, iclass 24, count 0 2006.202.01:19:13.12#ibcon#about to read 3, iclass 24, count 0 2006.202.01:19:13.15#ibcon#read 3, iclass 24, count 0 2006.202.01:19:13.15#ibcon#about to read 4, iclass 24, count 0 2006.202.01:19:13.15#ibcon#read 4, iclass 24, count 0 2006.202.01:19:13.15#ibcon#about to read 5, iclass 24, count 0 2006.202.01:19:13.15#ibcon#read 5, iclass 24, count 0 2006.202.01:19:13.15#ibcon#about to read 6, iclass 24, count 0 2006.202.01:19:13.15#ibcon#read 6, iclass 24, count 0 2006.202.01:19:13.15#ibcon#end of sib2, iclass 24, count 0 2006.202.01:19:13.15#ibcon#*after write, iclass 24, count 0 2006.202.01:19:13.15#ibcon#*before return 0, iclass 24, count 0 2006.202.01:19:13.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:13.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:13.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.01:19:13.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.01:19:13.15$vck44/valo=6,814.99 2006.202.01:19:13.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.01:19:13.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.01:19:13.15#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:13.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:13.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:13.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:13.15#ibcon#enter wrdev, iclass 26, count 0 2006.202.01:19:13.15#ibcon#first serial, iclass 26, count 0 2006.202.01:19:13.15#ibcon#enter sib2, iclass 26, count 0 2006.202.01:19:13.15#ibcon#flushed, iclass 26, count 0 2006.202.01:19:13.15#ibcon#about to write, iclass 26, count 0 2006.202.01:19:13.15#ibcon#wrote, iclass 26, count 0 2006.202.01:19:13.15#ibcon#about to read 3, iclass 26, count 0 2006.202.01:19:13.17#ibcon#read 3, iclass 26, count 0 2006.202.01:19:13.17#ibcon#about to read 4, iclass 26, count 0 2006.202.01:19:13.17#ibcon#read 4, iclass 26, count 0 2006.202.01:19:13.17#ibcon#about to read 5, iclass 26, count 0 2006.202.01:19:13.17#ibcon#read 5, iclass 26, count 0 2006.202.01:19:13.17#ibcon#about to read 6, iclass 26, count 0 2006.202.01:19:13.17#ibcon#read 6, iclass 26, count 0 2006.202.01:19:13.17#ibcon#end of sib2, iclass 26, count 0 2006.202.01:19:13.17#ibcon#*mode == 0, iclass 26, count 0 2006.202.01:19:13.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.01:19:13.17#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.01:19:13.17#ibcon#*before write, iclass 26, count 0 2006.202.01:19:13.17#ibcon#enter sib2, iclass 26, count 0 2006.202.01:19:13.17#ibcon#flushed, iclass 26, count 0 2006.202.01:19:13.17#ibcon#about to write, iclass 26, count 0 2006.202.01:19:13.17#ibcon#wrote, iclass 26, count 0 2006.202.01:19:13.17#ibcon#about to read 3, iclass 26, count 0 2006.202.01:19:13.21#ibcon#read 3, iclass 26, count 0 2006.202.01:19:13.21#ibcon#about to read 4, iclass 26, count 0 2006.202.01:19:13.21#ibcon#read 4, iclass 26, count 0 2006.202.01:19:13.21#ibcon#about to read 5, iclass 26, count 0 2006.202.01:19:13.21#ibcon#read 5, iclass 26, count 0 2006.202.01:19:13.21#ibcon#about to read 6, iclass 26, count 0 2006.202.01:19:13.21#ibcon#read 6, iclass 26, count 0 2006.202.01:19:13.21#ibcon#end of sib2, iclass 26, count 0 2006.202.01:19:13.21#ibcon#*after write, iclass 26, count 0 2006.202.01:19:13.21#ibcon#*before return 0, iclass 26, count 0 2006.202.01:19:13.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:13.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:13.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.01:19:13.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.01:19:13.21$vck44/va=6,5 2006.202.01:19:13.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.01:19:13.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.01:19:13.21#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:13.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:13.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:13.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:13.27#ibcon#enter wrdev, iclass 28, count 2 2006.202.01:19:13.27#ibcon#first serial, iclass 28, count 2 2006.202.01:19:13.27#ibcon#enter sib2, iclass 28, count 2 2006.202.01:19:13.27#ibcon#flushed, iclass 28, count 2 2006.202.01:19:13.27#ibcon#about to write, iclass 28, count 2 2006.202.01:19:13.27#ibcon#wrote, iclass 28, count 2 2006.202.01:19:13.27#ibcon#about to read 3, iclass 28, count 2 2006.202.01:19:13.29#ibcon#read 3, iclass 28, count 2 2006.202.01:19:13.29#ibcon#about to read 4, iclass 28, count 2 2006.202.01:19:13.29#ibcon#read 4, iclass 28, count 2 2006.202.01:19:13.29#ibcon#about to read 5, iclass 28, count 2 2006.202.01:19:13.29#ibcon#read 5, iclass 28, count 2 2006.202.01:19:13.29#ibcon#about to read 6, iclass 28, count 2 2006.202.01:19:13.29#ibcon#read 6, iclass 28, count 2 2006.202.01:19:13.29#ibcon#end of sib2, iclass 28, count 2 2006.202.01:19:13.29#ibcon#*mode == 0, iclass 28, count 2 2006.202.01:19:13.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.01:19:13.29#ibcon#[25=AT06-05\r\n] 2006.202.01:19:13.29#ibcon#*before write, iclass 28, count 2 2006.202.01:19:13.29#ibcon#enter sib2, iclass 28, count 2 2006.202.01:19:13.29#ibcon#flushed, iclass 28, count 2 2006.202.01:19:13.29#ibcon#about to write, iclass 28, count 2 2006.202.01:19:13.29#ibcon#wrote, iclass 28, count 2 2006.202.01:19:13.29#ibcon#about to read 3, iclass 28, count 2 2006.202.01:19:13.32#ibcon#read 3, iclass 28, count 2 2006.202.01:19:13.32#ibcon#about to read 4, iclass 28, count 2 2006.202.01:19:13.32#ibcon#read 4, iclass 28, count 2 2006.202.01:19:13.32#ibcon#about to read 5, iclass 28, count 2 2006.202.01:19:13.32#ibcon#read 5, iclass 28, count 2 2006.202.01:19:13.32#ibcon#about to read 6, iclass 28, count 2 2006.202.01:19:13.32#ibcon#read 6, iclass 28, count 2 2006.202.01:19:13.32#ibcon#end of sib2, iclass 28, count 2 2006.202.01:19:13.32#ibcon#*after write, iclass 28, count 2 2006.202.01:19:13.32#ibcon#*before return 0, iclass 28, count 2 2006.202.01:19:13.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:13.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:13.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.01:19:13.32#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:13.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:13.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:13.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:13.44#ibcon#enter wrdev, iclass 28, count 0 2006.202.01:19:13.44#ibcon#first serial, iclass 28, count 0 2006.202.01:19:13.44#ibcon#enter sib2, iclass 28, count 0 2006.202.01:19:13.44#ibcon#flushed, iclass 28, count 0 2006.202.01:19:13.44#ibcon#about to write, iclass 28, count 0 2006.202.01:19:13.44#ibcon#wrote, iclass 28, count 0 2006.202.01:19:13.44#ibcon#about to read 3, iclass 28, count 0 2006.202.01:19:13.46#ibcon#read 3, iclass 28, count 0 2006.202.01:19:13.46#ibcon#about to read 4, iclass 28, count 0 2006.202.01:19:13.46#ibcon#read 4, iclass 28, count 0 2006.202.01:19:13.46#ibcon#about to read 5, iclass 28, count 0 2006.202.01:19:13.46#ibcon#read 5, iclass 28, count 0 2006.202.01:19:13.46#ibcon#about to read 6, iclass 28, count 0 2006.202.01:19:13.46#ibcon#read 6, iclass 28, count 0 2006.202.01:19:13.46#ibcon#end of sib2, iclass 28, count 0 2006.202.01:19:13.46#ibcon#*mode == 0, iclass 28, count 0 2006.202.01:19:13.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.01:19:13.46#ibcon#[25=USB\r\n] 2006.202.01:19:13.46#ibcon#*before write, iclass 28, count 0 2006.202.01:19:13.46#ibcon#enter sib2, iclass 28, count 0 2006.202.01:19:13.46#ibcon#flushed, iclass 28, count 0 2006.202.01:19:13.46#ibcon#about to write, iclass 28, count 0 2006.202.01:19:13.46#ibcon#wrote, iclass 28, count 0 2006.202.01:19:13.46#ibcon#about to read 3, iclass 28, count 0 2006.202.01:19:13.49#ibcon#read 3, iclass 28, count 0 2006.202.01:19:13.49#ibcon#about to read 4, iclass 28, count 0 2006.202.01:19:13.49#ibcon#read 4, iclass 28, count 0 2006.202.01:19:13.49#ibcon#about to read 5, iclass 28, count 0 2006.202.01:19:13.49#ibcon#read 5, iclass 28, count 0 2006.202.01:19:13.49#ibcon#about to read 6, iclass 28, count 0 2006.202.01:19:13.49#ibcon#read 6, iclass 28, count 0 2006.202.01:19:13.49#ibcon#end of sib2, iclass 28, count 0 2006.202.01:19:13.49#ibcon#*after write, iclass 28, count 0 2006.202.01:19:13.49#ibcon#*before return 0, iclass 28, count 0 2006.202.01:19:13.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:13.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:13.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.01:19:13.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.01:19:13.49$vck44/valo=7,864.99 2006.202.01:19:13.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.01:19:13.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.01:19:13.49#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:13.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:13.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:13.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:13.49#ibcon#enter wrdev, iclass 30, count 0 2006.202.01:19:13.49#ibcon#first serial, iclass 30, count 0 2006.202.01:19:13.49#ibcon#enter sib2, iclass 30, count 0 2006.202.01:19:13.49#ibcon#flushed, iclass 30, count 0 2006.202.01:19:13.49#ibcon#about to write, iclass 30, count 0 2006.202.01:19:13.49#ibcon#wrote, iclass 30, count 0 2006.202.01:19:13.49#ibcon#about to read 3, iclass 30, count 0 2006.202.01:19:13.51#ibcon#read 3, iclass 30, count 0 2006.202.01:19:13.51#ibcon#about to read 4, iclass 30, count 0 2006.202.01:19:13.51#ibcon#read 4, iclass 30, count 0 2006.202.01:19:13.51#ibcon#about to read 5, iclass 30, count 0 2006.202.01:19:13.51#ibcon#read 5, iclass 30, count 0 2006.202.01:19:13.51#ibcon#about to read 6, iclass 30, count 0 2006.202.01:19:13.51#ibcon#read 6, iclass 30, count 0 2006.202.01:19:13.51#ibcon#end of sib2, iclass 30, count 0 2006.202.01:19:13.51#ibcon#*mode == 0, iclass 30, count 0 2006.202.01:19:13.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.01:19:13.51#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.01:19:13.51#ibcon#*before write, iclass 30, count 0 2006.202.01:19:13.51#ibcon#enter sib2, iclass 30, count 0 2006.202.01:19:13.51#ibcon#flushed, iclass 30, count 0 2006.202.01:19:13.51#ibcon#about to write, iclass 30, count 0 2006.202.01:19:13.51#ibcon#wrote, iclass 30, count 0 2006.202.01:19:13.51#ibcon#about to read 3, iclass 30, count 0 2006.202.01:19:13.55#ibcon#read 3, iclass 30, count 0 2006.202.01:19:13.55#ibcon#about to read 4, iclass 30, count 0 2006.202.01:19:13.55#ibcon#read 4, iclass 30, count 0 2006.202.01:19:13.55#ibcon#about to read 5, iclass 30, count 0 2006.202.01:19:13.55#ibcon#read 5, iclass 30, count 0 2006.202.01:19:13.55#ibcon#about to read 6, iclass 30, count 0 2006.202.01:19:13.55#ibcon#read 6, iclass 30, count 0 2006.202.01:19:13.55#ibcon#end of sib2, iclass 30, count 0 2006.202.01:19:13.55#ibcon#*after write, iclass 30, count 0 2006.202.01:19:13.55#ibcon#*before return 0, iclass 30, count 0 2006.202.01:19:13.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:13.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:13.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.01:19:13.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.01:19:13.55$vck44/va=7,5 2006.202.01:19:13.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.01:19:13.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.01:19:13.55#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:13.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:13.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:13.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:13.61#ibcon#enter wrdev, iclass 32, count 2 2006.202.01:19:13.61#ibcon#first serial, iclass 32, count 2 2006.202.01:19:13.61#ibcon#enter sib2, iclass 32, count 2 2006.202.01:19:13.61#ibcon#flushed, iclass 32, count 2 2006.202.01:19:13.61#ibcon#about to write, iclass 32, count 2 2006.202.01:19:13.61#ibcon#wrote, iclass 32, count 2 2006.202.01:19:13.61#ibcon#about to read 3, iclass 32, count 2 2006.202.01:19:13.63#ibcon#read 3, iclass 32, count 2 2006.202.01:19:13.63#ibcon#about to read 4, iclass 32, count 2 2006.202.01:19:13.63#ibcon#read 4, iclass 32, count 2 2006.202.01:19:13.63#ibcon#about to read 5, iclass 32, count 2 2006.202.01:19:13.63#ibcon#read 5, iclass 32, count 2 2006.202.01:19:13.63#ibcon#about to read 6, iclass 32, count 2 2006.202.01:19:13.63#ibcon#read 6, iclass 32, count 2 2006.202.01:19:13.63#ibcon#end of sib2, iclass 32, count 2 2006.202.01:19:13.63#ibcon#*mode == 0, iclass 32, count 2 2006.202.01:19:13.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.01:19:13.63#ibcon#[25=AT07-05\r\n] 2006.202.01:19:13.63#ibcon#*before write, iclass 32, count 2 2006.202.01:19:13.63#ibcon#enter sib2, iclass 32, count 2 2006.202.01:19:13.63#ibcon#flushed, iclass 32, count 2 2006.202.01:19:13.63#ibcon#about to write, iclass 32, count 2 2006.202.01:19:13.63#ibcon#wrote, iclass 32, count 2 2006.202.01:19:13.63#ibcon#about to read 3, iclass 32, count 2 2006.202.01:19:13.66#ibcon#read 3, iclass 32, count 2 2006.202.01:19:13.66#ibcon#about to read 4, iclass 32, count 2 2006.202.01:19:13.66#ibcon#read 4, iclass 32, count 2 2006.202.01:19:13.66#ibcon#about to read 5, iclass 32, count 2 2006.202.01:19:13.66#ibcon#read 5, iclass 32, count 2 2006.202.01:19:13.66#ibcon#about to read 6, iclass 32, count 2 2006.202.01:19:13.66#ibcon#read 6, iclass 32, count 2 2006.202.01:19:13.66#ibcon#end of sib2, iclass 32, count 2 2006.202.01:19:13.66#ibcon#*after write, iclass 32, count 2 2006.202.01:19:13.66#ibcon#*before return 0, iclass 32, count 2 2006.202.01:19:13.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:13.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:13.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.01:19:13.66#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:13.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:13.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:13.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:13.78#ibcon#enter wrdev, iclass 32, count 0 2006.202.01:19:13.78#ibcon#first serial, iclass 32, count 0 2006.202.01:19:13.78#ibcon#enter sib2, iclass 32, count 0 2006.202.01:19:13.78#ibcon#flushed, iclass 32, count 0 2006.202.01:19:13.78#ibcon#about to write, iclass 32, count 0 2006.202.01:19:13.78#ibcon#wrote, iclass 32, count 0 2006.202.01:19:13.78#ibcon#about to read 3, iclass 32, count 0 2006.202.01:19:13.80#ibcon#read 3, iclass 32, count 0 2006.202.01:19:13.80#ibcon#about to read 4, iclass 32, count 0 2006.202.01:19:13.80#ibcon#read 4, iclass 32, count 0 2006.202.01:19:13.80#ibcon#about to read 5, iclass 32, count 0 2006.202.01:19:13.80#ibcon#read 5, iclass 32, count 0 2006.202.01:19:13.80#ibcon#about to read 6, iclass 32, count 0 2006.202.01:19:13.80#ibcon#read 6, iclass 32, count 0 2006.202.01:19:13.80#ibcon#end of sib2, iclass 32, count 0 2006.202.01:19:13.80#ibcon#*mode == 0, iclass 32, count 0 2006.202.01:19:13.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.01:19:13.80#ibcon#[25=USB\r\n] 2006.202.01:19:13.80#ibcon#*before write, iclass 32, count 0 2006.202.01:19:13.80#ibcon#enter sib2, iclass 32, count 0 2006.202.01:19:13.80#ibcon#flushed, iclass 32, count 0 2006.202.01:19:13.80#ibcon#about to write, iclass 32, count 0 2006.202.01:19:13.80#ibcon#wrote, iclass 32, count 0 2006.202.01:19:13.80#ibcon#about to read 3, iclass 32, count 0 2006.202.01:19:13.83#ibcon#read 3, iclass 32, count 0 2006.202.01:19:13.83#ibcon#about to read 4, iclass 32, count 0 2006.202.01:19:13.83#ibcon#read 4, iclass 32, count 0 2006.202.01:19:13.83#ibcon#about to read 5, iclass 32, count 0 2006.202.01:19:13.83#ibcon#read 5, iclass 32, count 0 2006.202.01:19:13.83#ibcon#about to read 6, iclass 32, count 0 2006.202.01:19:13.83#ibcon#read 6, iclass 32, count 0 2006.202.01:19:13.83#ibcon#end of sib2, iclass 32, count 0 2006.202.01:19:13.83#ibcon#*after write, iclass 32, count 0 2006.202.01:19:13.83#ibcon#*before return 0, iclass 32, count 0 2006.202.01:19:13.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:13.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:13.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.01:19:13.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.01:19:13.83$vck44/valo=8,884.99 2006.202.01:19:13.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.01:19:13.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.01:19:13.83#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:13.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:13.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:13.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:13.83#ibcon#enter wrdev, iclass 34, count 0 2006.202.01:19:13.83#ibcon#first serial, iclass 34, count 0 2006.202.01:19:13.83#ibcon#enter sib2, iclass 34, count 0 2006.202.01:19:13.83#ibcon#flushed, iclass 34, count 0 2006.202.01:19:13.83#ibcon#about to write, iclass 34, count 0 2006.202.01:19:13.83#ibcon#wrote, iclass 34, count 0 2006.202.01:19:13.83#ibcon#about to read 3, iclass 34, count 0 2006.202.01:19:13.85#ibcon#read 3, iclass 34, count 0 2006.202.01:19:13.85#ibcon#about to read 4, iclass 34, count 0 2006.202.01:19:13.85#ibcon#read 4, iclass 34, count 0 2006.202.01:19:13.85#ibcon#about to read 5, iclass 34, count 0 2006.202.01:19:13.85#ibcon#read 5, iclass 34, count 0 2006.202.01:19:13.85#ibcon#about to read 6, iclass 34, count 0 2006.202.01:19:13.85#ibcon#read 6, iclass 34, count 0 2006.202.01:19:13.85#ibcon#end of sib2, iclass 34, count 0 2006.202.01:19:13.85#ibcon#*mode == 0, iclass 34, count 0 2006.202.01:19:13.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.01:19:13.85#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.01:19:13.85#ibcon#*before write, iclass 34, count 0 2006.202.01:19:13.85#ibcon#enter sib2, iclass 34, count 0 2006.202.01:19:13.85#ibcon#flushed, iclass 34, count 0 2006.202.01:19:13.85#ibcon#about to write, iclass 34, count 0 2006.202.01:19:13.85#ibcon#wrote, iclass 34, count 0 2006.202.01:19:13.85#ibcon#about to read 3, iclass 34, count 0 2006.202.01:19:13.89#ibcon#read 3, iclass 34, count 0 2006.202.01:19:13.89#ibcon#about to read 4, iclass 34, count 0 2006.202.01:19:13.89#ibcon#read 4, iclass 34, count 0 2006.202.01:19:13.89#ibcon#about to read 5, iclass 34, count 0 2006.202.01:19:13.89#ibcon#read 5, iclass 34, count 0 2006.202.01:19:13.89#ibcon#about to read 6, iclass 34, count 0 2006.202.01:19:13.89#ibcon#read 6, iclass 34, count 0 2006.202.01:19:13.89#ibcon#end of sib2, iclass 34, count 0 2006.202.01:19:13.89#ibcon#*after write, iclass 34, count 0 2006.202.01:19:13.89#ibcon#*before return 0, iclass 34, count 0 2006.202.01:19:13.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:13.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:13.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.01:19:13.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.01:19:13.89$vck44/va=8,4 2006.202.01:19:13.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.01:19:13.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.01:19:13.89#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:13.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:19:13.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:19:13.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:19:13.95#ibcon#enter wrdev, iclass 36, count 2 2006.202.01:19:13.95#ibcon#first serial, iclass 36, count 2 2006.202.01:19:13.95#ibcon#enter sib2, iclass 36, count 2 2006.202.01:19:13.95#ibcon#flushed, iclass 36, count 2 2006.202.01:19:13.95#ibcon#about to write, iclass 36, count 2 2006.202.01:19:13.95#ibcon#wrote, iclass 36, count 2 2006.202.01:19:13.95#ibcon#about to read 3, iclass 36, count 2 2006.202.01:19:13.97#ibcon#read 3, iclass 36, count 2 2006.202.01:19:13.97#ibcon#about to read 4, iclass 36, count 2 2006.202.01:19:13.97#ibcon#read 4, iclass 36, count 2 2006.202.01:19:13.97#ibcon#about to read 5, iclass 36, count 2 2006.202.01:19:13.97#ibcon#read 5, iclass 36, count 2 2006.202.01:19:13.97#ibcon#about to read 6, iclass 36, count 2 2006.202.01:19:13.97#ibcon#read 6, iclass 36, count 2 2006.202.01:19:13.97#ibcon#end of sib2, iclass 36, count 2 2006.202.01:19:13.97#ibcon#*mode == 0, iclass 36, count 2 2006.202.01:19:13.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.01:19:13.97#ibcon#[25=AT08-04\r\n] 2006.202.01:19:13.97#ibcon#*before write, iclass 36, count 2 2006.202.01:19:13.97#ibcon#enter sib2, iclass 36, count 2 2006.202.01:19:13.97#ibcon#flushed, iclass 36, count 2 2006.202.01:19:13.97#ibcon#about to write, iclass 36, count 2 2006.202.01:19:13.97#ibcon#wrote, iclass 36, count 2 2006.202.01:19:13.97#ibcon#about to read 3, iclass 36, count 2 2006.202.01:19:14.00#ibcon#read 3, iclass 36, count 2 2006.202.01:19:14.00#ibcon#about to read 4, iclass 36, count 2 2006.202.01:19:14.00#ibcon#read 4, iclass 36, count 2 2006.202.01:19:14.00#ibcon#about to read 5, iclass 36, count 2 2006.202.01:19:14.00#ibcon#read 5, iclass 36, count 2 2006.202.01:19:14.00#ibcon#about to read 6, iclass 36, count 2 2006.202.01:19:14.00#ibcon#read 6, iclass 36, count 2 2006.202.01:19:14.00#ibcon#end of sib2, iclass 36, count 2 2006.202.01:19:14.00#ibcon#*after write, iclass 36, count 2 2006.202.01:19:14.00#ibcon#*before return 0, iclass 36, count 2 2006.202.01:19:14.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:19:14.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:19:14.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.01:19:14.00#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:14.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:19:14.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:19:14.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:19:14.12#ibcon#enter wrdev, iclass 36, count 0 2006.202.01:19:14.12#ibcon#first serial, iclass 36, count 0 2006.202.01:19:14.12#ibcon#enter sib2, iclass 36, count 0 2006.202.01:19:14.12#ibcon#flushed, iclass 36, count 0 2006.202.01:19:14.12#ibcon#about to write, iclass 36, count 0 2006.202.01:19:14.12#ibcon#wrote, iclass 36, count 0 2006.202.01:19:14.12#ibcon#about to read 3, iclass 36, count 0 2006.202.01:19:14.14#ibcon#read 3, iclass 36, count 0 2006.202.01:19:14.14#ibcon#about to read 4, iclass 36, count 0 2006.202.01:19:14.14#ibcon#read 4, iclass 36, count 0 2006.202.01:19:14.14#ibcon#about to read 5, iclass 36, count 0 2006.202.01:19:14.14#ibcon#read 5, iclass 36, count 0 2006.202.01:19:14.14#ibcon#about to read 6, iclass 36, count 0 2006.202.01:19:14.14#ibcon#read 6, iclass 36, count 0 2006.202.01:19:14.14#ibcon#end of sib2, iclass 36, count 0 2006.202.01:19:14.14#ibcon#*mode == 0, iclass 36, count 0 2006.202.01:19:14.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.01:19:14.14#ibcon#[25=USB\r\n] 2006.202.01:19:14.14#ibcon#*before write, iclass 36, count 0 2006.202.01:19:14.14#ibcon#enter sib2, iclass 36, count 0 2006.202.01:19:14.14#ibcon#flushed, iclass 36, count 0 2006.202.01:19:14.14#ibcon#about to write, iclass 36, count 0 2006.202.01:19:14.14#ibcon#wrote, iclass 36, count 0 2006.202.01:19:14.14#ibcon#about to read 3, iclass 36, count 0 2006.202.01:19:14.17#ibcon#read 3, iclass 36, count 0 2006.202.01:19:14.17#ibcon#about to read 4, iclass 36, count 0 2006.202.01:19:14.17#ibcon#read 4, iclass 36, count 0 2006.202.01:19:14.17#ibcon#about to read 5, iclass 36, count 0 2006.202.01:19:14.17#ibcon#read 5, iclass 36, count 0 2006.202.01:19:14.17#ibcon#about to read 6, iclass 36, count 0 2006.202.01:19:14.17#ibcon#read 6, iclass 36, count 0 2006.202.01:19:14.17#ibcon#end of sib2, iclass 36, count 0 2006.202.01:19:14.17#ibcon#*after write, iclass 36, count 0 2006.202.01:19:14.17#ibcon#*before return 0, iclass 36, count 0 2006.202.01:19:14.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:19:14.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:19:14.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.01:19:14.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.01:19:14.17$vck44/vblo=1,629.99 2006.202.01:19:14.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.01:19:14.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.01:19:14.17#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:14.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:19:14.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:19:14.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:19:14.17#ibcon#enter wrdev, iclass 38, count 0 2006.202.01:19:14.17#ibcon#first serial, iclass 38, count 0 2006.202.01:19:14.17#ibcon#enter sib2, iclass 38, count 0 2006.202.01:19:14.17#ibcon#flushed, iclass 38, count 0 2006.202.01:19:14.17#ibcon#about to write, iclass 38, count 0 2006.202.01:19:14.17#ibcon#wrote, iclass 38, count 0 2006.202.01:19:14.17#ibcon#about to read 3, iclass 38, count 0 2006.202.01:19:14.19#ibcon#read 3, iclass 38, count 0 2006.202.01:19:14.19#ibcon#about to read 4, iclass 38, count 0 2006.202.01:19:14.19#ibcon#read 4, iclass 38, count 0 2006.202.01:19:14.19#ibcon#about to read 5, iclass 38, count 0 2006.202.01:19:14.19#ibcon#read 5, iclass 38, count 0 2006.202.01:19:14.19#ibcon#about to read 6, iclass 38, count 0 2006.202.01:19:14.19#ibcon#read 6, iclass 38, count 0 2006.202.01:19:14.19#ibcon#end of sib2, iclass 38, count 0 2006.202.01:19:14.19#ibcon#*mode == 0, iclass 38, count 0 2006.202.01:19:14.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.01:19:14.19#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.01:19:14.19#ibcon#*before write, iclass 38, count 0 2006.202.01:19:14.19#ibcon#enter sib2, iclass 38, count 0 2006.202.01:19:14.19#ibcon#flushed, iclass 38, count 0 2006.202.01:19:14.19#ibcon#about to write, iclass 38, count 0 2006.202.01:19:14.19#ibcon#wrote, iclass 38, count 0 2006.202.01:19:14.19#ibcon#about to read 3, iclass 38, count 0 2006.202.01:19:14.23#ibcon#read 3, iclass 38, count 0 2006.202.01:19:14.23#ibcon#about to read 4, iclass 38, count 0 2006.202.01:19:14.23#ibcon#read 4, iclass 38, count 0 2006.202.01:19:14.23#ibcon#about to read 5, iclass 38, count 0 2006.202.01:19:14.23#ibcon#read 5, iclass 38, count 0 2006.202.01:19:14.23#ibcon#about to read 6, iclass 38, count 0 2006.202.01:19:14.23#ibcon#read 6, iclass 38, count 0 2006.202.01:19:14.23#ibcon#end of sib2, iclass 38, count 0 2006.202.01:19:14.23#ibcon#*after write, iclass 38, count 0 2006.202.01:19:14.23#ibcon#*before return 0, iclass 38, count 0 2006.202.01:19:14.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:19:14.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:19:14.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.01:19:14.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.01:19:14.23$vck44/vb=1,4 2006.202.01:19:14.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.202.01:19:14.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.202.01:19:14.23#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:14.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:19:14.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:19:14.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:19:14.23#ibcon#enter wrdev, iclass 40, count 2 2006.202.01:19:14.23#ibcon#first serial, iclass 40, count 2 2006.202.01:19:14.23#ibcon#enter sib2, iclass 40, count 2 2006.202.01:19:14.23#ibcon#flushed, iclass 40, count 2 2006.202.01:19:14.23#ibcon#about to write, iclass 40, count 2 2006.202.01:19:14.23#ibcon#wrote, iclass 40, count 2 2006.202.01:19:14.23#ibcon#about to read 3, iclass 40, count 2 2006.202.01:19:14.25#ibcon#read 3, iclass 40, count 2 2006.202.01:19:14.25#ibcon#about to read 4, iclass 40, count 2 2006.202.01:19:14.25#ibcon#read 4, iclass 40, count 2 2006.202.01:19:14.25#ibcon#about to read 5, iclass 40, count 2 2006.202.01:19:14.25#ibcon#read 5, iclass 40, count 2 2006.202.01:19:14.25#ibcon#about to read 6, iclass 40, count 2 2006.202.01:19:14.25#ibcon#read 6, iclass 40, count 2 2006.202.01:19:14.25#ibcon#end of sib2, iclass 40, count 2 2006.202.01:19:14.25#ibcon#*mode == 0, iclass 40, count 2 2006.202.01:19:14.25#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.202.01:19:14.25#ibcon#[27=AT01-04\r\n] 2006.202.01:19:14.25#ibcon#*before write, iclass 40, count 2 2006.202.01:19:14.25#ibcon#enter sib2, iclass 40, count 2 2006.202.01:19:14.25#ibcon#flushed, iclass 40, count 2 2006.202.01:19:14.25#ibcon#about to write, iclass 40, count 2 2006.202.01:19:14.25#ibcon#wrote, iclass 40, count 2 2006.202.01:19:14.25#ibcon#about to read 3, iclass 40, count 2 2006.202.01:19:14.28#ibcon#read 3, iclass 40, count 2 2006.202.01:19:14.28#ibcon#about to read 4, iclass 40, count 2 2006.202.01:19:14.28#ibcon#read 4, iclass 40, count 2 2006.202.01:19:14.28#ibcon#about to read 5, iclass 40, count 2 2006.202.01:19:14.28#ibcon#read 5, iclass 40, count 2 2006.202.01:19:14.28#ibcon#about to read 6, iclass 40, count 2 2006.202.01:19:14.28#ibcon#read 6, iclass 40, count 2 2006.202.01:19:14.28#ibcon#end of sib2, iclass 40, count 2 2006.202.01:19:14.28#ibcon#*after write, iclass 40, count 2 2006.202.01:19:14.28#ibcon#*before return 0, iclass 40, count 2 2006.202.01:19:14.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:19:14.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:19:14.28#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.202.01:19:14.28#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:14.28#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:19:14.40#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:19:14.40#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:19:14.40#ibcon#enter wrdev, iclass 40, count 0 2006.202.01:19:14.40#ibcon#first serial, iclass 40, count 0 2006.202.01:19:14.40#ibcon#enter sib2, iclass 40, count 0 2006.202.01:19:14.40#ibcon#flushed, iclass 40, count 0 2006.202.01:19:14.40#ibcon#about to write, iclass 40, count 0 2006.202.01:19:14.40#ibcon#wrote, iclass 40, count 0 2006.202.01:19:14.40#ibcon#about to read 3, iclass 40, count 0 2006.202.01:19:14.42#ibcon#read 3, iclass 40, count 0 2006.202.01:19:14.42#ibcon#about to read 4, iclass 40, count 0 2006.202.01:19:14.42#ibcon#read 4, iclass 40, count 0 2006.202.01:19:14.42#ibcon#about to read 5, iclass 40, count 0 2006.202.01:19:14.42#ibcon#read 5, iclass 40, count 0 2006.202.01:19:14.42#ibcon#about to read 6, iclass 40, count 0 2006.202.01:19:14.42#ibcon#read 6, iclass 40, count 0 2006.202.01:19:14.42#ibcon#end of sib2, iclass 40, count 0 2006.202.01:19:14.42#ibcon#*mode == 0, iclass 40, count 0 2006.202.01:19:14.42#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.01:19:14.42#ibcon#[27=USB\r\n] 2006.202.01:19:14.42#ibcon#*before write, iclass 40, count 0 2006.202.01:19:14.42#ibcon#enter sib2, iclass 40, count 0 2006.202.01:19:14.42#ibcon#flushed, iclass 40, count 0 2006.202.01:19:14.42#ibcon#about to write, iclass 40, count 0 2006.202.01:19:14.42#ibcon#wrote, iclass 40, count 0 2006.202.01:19:14.42#ibcon#about to read 3, iclass 40, count 0 2006.202.01:19:14.45#ibcon#read 3, iclass 40, count 0 2006.202.01:19:14.45#ibcon#about to read 4, iclass 40, count 0 2006.202.01:19:14.45#ibcon#read 4, iclass 40, count 0 2006.202.01:19:14.45#ibcon#about to read 5, iclass 40, count 0 2006.202.01:19:14.45#ibcon#read 5, iclass 40, count 0 2006.202.01:19:14.45#ibcon#about to read 6, iclass 40, count 0 2006.202.01:19:14.45#ibcon#read 6, iclass 40, count 0 2006.202.01:19:14.45#ibcon#end of sib2, iclass 40, count 0 2006.202.01:19:14.45#ibcon#*after write, iclass 40, count 0 2006.202.01:19:14.45#ibcon#*before return 0, iclass 40, count 0 2006.202.01:19:14.45#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:19:14.45#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:19:14.45#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.01:19:14.45#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.01:19:14.45$vck44/vblo=2,634.99 2006.202.01:19:14.45#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.01:19:14.45#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.01:19:14.45#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:14.45#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:14.45#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:14.45#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:14.45#ibcon#enter wrdev, iclass 4, count 0 2006.202.01:19:14.45#ibcon#first serial, iclass 4, count 0 2006.202.01:19:14.45#ibcon#enter sib2, iclass 4, count 0 2006.202.01:19:14.45#ibcon#flushed, iclass 4, count 0 2006.202.01:19:14.45#ibcon#about to write, iclass 4, count 0 2006.202.01:19:14.45#ibcon#wrote, iclass 4, count 0 2006.202.01:19:14.45#ibcon#about to read 3, iclass 4, count 0 2006.202.01:19:14.47#ibcon#read 3, iclass 4, count 0 2006.202.01:19:14.47#ibcon#about to read 4, iclass 4, count 0 2006.202.01:19:14.47#ibcon#read 4, iclass 4, count 0 2006.202.01:19:14.47#ibcon#about to read 5, iclass 4, count 0 2006.202.01:19:14.47#ibcon#read 5, iclass 4, count 0 2006.202.01:19:14.47#ibcon#about to read 6, iclass 4, count 0 2006.202.01:19:14.47#ibcon#read 6, iclass 4, count 0 2006.202.01:19:14.47#ibcon#end of sib2, iclass 4, count 0 2006.202.01:19:14.47#ibcon#*mode == 0, iclass 4, count 0 2006.202.01:19:14.47#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.01:19:14.47#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.01:19:14.47#ibcon#*before write, iclass 4, count 0 2006.202.01:19:14.47#ibcon#enter sib2, iclass 4, count 0 2006.202.01:19:14.47#ibcon#flushed, iclass 4, count 0 2006.202.01:19:14.47#ibcon#about to write, iclass 4, count 0 2006.202.01:19:14.47#ibcon#wrote, iclass 4, count 0 2006.202.01:19:14.47#ibcon#about to read 3, iclass 4, count 0 2006.202.01:19:14.51#ibcon#read 3, iclass 4, count 0 2006.202.01:19:14.51#ibcon#about to read 4, iclass 4, count 0 2006.202.01:19:14.51#ibcon#read 4, iclass 4, count 0 2006.202.01:19:14.51#ibcon#about to read 5, iclass 4, count 0 2006.202.01:19:14.51#ibcon#read 5, iclass 4, count 0 2006.202.01:19:14.51#ibcon#about to read 6, iclass 4, count 0 2006.202.01:19:14.51#ibcon#read 6, iclass 4, count 0 2006.202.01:19:14.51#ibcon#end of sib2, iclass 4, count 0 2006.202.01:19:14.51#ibcon#*after write, iclass 4, count 0 2006.202.01:19:14.51#ibcon#*before return 0, iclass 4, count 0 2006.202.01:19:14.51#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:14.51#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:19:14.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.01:19:14.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.01:19:14.51$vck44/vb=2,5 2006.202.01:19:14.51#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.202.01:19:14.51#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.202.01:19:14.51#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:14.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:14.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:14.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:14.57#ibcon#enter wrdev, iclass 6, count 2 2006.202.01:19:14.57#ibcon#first serial, iclass 6, count 2 2006.202.01:19:14.57#ibcon#enter sib2, iclass 6, count 2 2006.202.01:19:14.57#ibcon#flushed, iclass 6, count 2 2006.202.01:19:14.57#ibcon#about to write, iclass 6, count 2 2006.202.01:19:14.57#ibcon#wrote, iclass 6, count 2 2006.202.01:19:14.57#ibcon#about to read 3, iclass 6, count 2 2006.202.01:19:14.59#ibcon#read 3, iclass 6, count 2 2006.202.01:19:14.59#ibcon#about to read 4, iclass 6, count 2 2006.202.01:19:14.59#ibcon#read 4, iclass 6, count 2 2006.202.01:19:14.59#ibcon#about to read 5, iclass 6, count 2 2006.202.01:19:14.59#ibcon#read 5, iclass 6, count 2 2006.202.01:19:14.59#ibcon#about to read 6, iclass 6, count 2 2006.202.01:19:14.59#ibcon#read 6, iclass 6, count 2 2006.202.01:19:14.59#ibcon#end of sib2, iclass 6, count 2 2006.202.01:19:14.59#ibcon#*mode == 0, iclass 6, count 2 2006.202.01:19:14.59#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.202.01:19:14.59#ibcon#[27=AT02-05\r\n] 2006.202.01:19:14.59#ibcon#*before write, iclass 6, count 2 2006.202.01:19:14.59#ibcon#enter sib2, iclass 6, count 2 2006.202.01:19:14.59#ibcon#flushed, iclass 6, count 2 2006.202.01:19:14.59#ibcon#about to write, iclass 6, count 2 2006.202.01:19:14.59#ibcon#wrote, iclass 6, count 2 2006.202.01:19:14.59#ibcon#about to read 3, iclass 6, count 2 2006.202.01:19:14.62#ibcon#read 3, iclass 6, count 2 2006.202.01:19:14.62#ibcon#about to read 4, iclass 6, count 2 2006.202.01:19:14.62#ibcon#read 4, iclass 6, count 2 2006.202.01:19:14.62#ibcon#about to read 5, iclass 6, count 2 2006.202.01:19:14.62#ibcon#read 5, iclass 6, count 2 2006.202.01:19:14.62#ibcon#about to read 6, iclass 6, count 2 2006.202.01:19:14.62#ibcon#read 6, iclass 6, count 2 2006.202.01:19:14.62#ibcon#end of sib2, iclass 6, count 2 2006.202.01:19:14.62#ibcon#*after write, iclass 6, count 2 2006.202.01:19:14.62#ibcon#*before return 0, iclass 6, count 2 2006.202.01:19:14.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:14.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:19:14.62#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.202.01:19:14.62#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:14.62#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:14.74#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:14.74#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:14.74#ibcon#enter wrdev, iclass 6, count 0 2006.202.01:19:14.74#ibcon#first serial, iclass 6, count 0 2006.202.01:19:14.74#ibcon#enter sib2, iclass 6, count 0 2006.202.01:19:14.74#ibcon#flushed, iclass 6, count 0 2006.202.01:19:14.74#ibcon#about to write, iclass 6, count 0 2006.202.01:19:14.74#ibcon#wrote, iclass 6, count 0 2006.202.01:19:14.74#ibcon#about to read 3, iclass 6, count 0 2006.202.01:19:14.76#ibcon#read 3, iclass 6, count 0 2006.202.01:19:14.76#ibcon#about to read 4, iclass 6, count 0 2006.202.01:19:14.76#ibcon#read 4, iclass 6, count 0 2006.202.01:19:14.76#ibcon#about to read 5, iclass 6, count 0 2006.202.01:19:14.76#ibcon#read 5, iclass 6, count 0 2006.202.01:19:14.76#ibcon#about to read 6, iclass 6, count 0 2006.202.01:19:14.76#ibcon#read 6, iclass 6, count 0 2006.202.01:19:14.76#ibcon#end of sib2, iclass 6, count 0 2006.202.01:19:14.76#ibcon#*mode == 0, iclass 6, count 0 2006.202.01:19:14.76#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.01:19:14.76#ibcon#[27=USB\r\n] 2006.202.01:19:14.76#ibcon#*before write, iclass 6, count 0 2006.202.01:19:14.76#ibcon#enter sib2, iclass 6, count 0 2006.202.01:19:14.76#ibcon#flushed, iclass 6, count 0 2006.202.01:19:14.76#ibcon#about to write, iclass 6, count 0 2006.202.01:19:14.76#ibcon#wrote, iclass 6, count 0 2006.202.01:19:14.76#ibcon#about to read 3, iclass 6, count 0 2006.202.01:19:14.79#ibcon#read 3, iclass 6, count 0 2006.202.01:19:14.79#ibcon#about to read 4, iclass 6, count 0 2006.202.01:19:14.79#ibcon#read 4, iclass 6, count 0 2006.202.01:19:14.79#ibcon#about to read 5, iclass 6, count 0 2006.202.01:19:14.79#ibcon#read 5, iclass 6, count 0 2006.202.01:19:14.79#ibcon#about to read 6, iclass 6, count 0 2006.202.01:19:14.79#ibcon#read 6, iclass 6, count 0 2006.202.01:19:14.79#ibcon#end of sib2, iclass 6, count 0 2006.202.01:19:14.79#ibcon#*after write, iclass 6, count 0 2006.202.01:19:14.79#ibcon#*before return 0, iclass 6, count 0 2006.202.01:19:14.79#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:14.79#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:19:14.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.01:19:14.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.01:19:14.79$vck44/vblo=3,649.99 2006.202.01:19:14.79#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.01:19:14.79#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.01:19:14.79#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:14.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:14.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:14.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:14.79#ibcon#enter wrdev, iclass 10, count 0 2006.202.01:19:14.79#ibcon#first serial, iclass 10, count 0 2006.202.01:19:14.79#ibcon#enter sib2, iclass 10, count 0 2006.202.01:19:14.79#ibcon#flushed, iclass 10, count 0 2006.202.01:19:14.79#ibcon#about to write, iclass 10, count 0 2006.202.01:19:14.79#ibcon#wrote, iclass 10, count 0 2006.202.01:19:14.79#ibcon#about to read 3, iclass 10, count 0 2006.202.01:19:14.81#ibcon#read 3, iclass 10, count 0 2006.202.01:19:14.81#ibcon#about to read 4, iclass 10, count 0 2006.202.01:19:14.81#ibcon#read 4, iclass 10, count 0 2006.202.01:19:14.81#ibcon#about to read 5, iclass 10, count 0 2006.202.01:19:14.81#ibcon#read 5, iclass 10, count 0 2006.202.01:19:14.81#ibcon#about to read 6, iclass 10, count 0 2006.202.01:19:14.81#ibcon#read 6, iclass 10, count 0 2006.202.01:19:14.81#ibcon#end of sib2, iclass 10, count 0 2006.202.01:19:14.81#ibcon#*mode == 0, iclass 10, count 0 2006.202.01:19:14.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.01:19:14.81#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.01:19:14.81#ibcon#*before write, iclass 10, count 0 2006.202.01:19:14.81#ibcon#enter sib2, iclass 10, count 0 2006.202.01:19:14.81#ibcon#flushed, iclass 10, count 0 2006.202.01:19:14.81#ibcon#about to write, iclass 10, count 0 2006.202.01:19:14.81#ibcon#wrote, iclass 10, count 0 2006.202.01:19:14.81#ibcon#about to read 3, iclass 10, count 0 2006.202.01:19:14.85#ibcon#read 3, iclass 10, count 0 2006.202.01:19:14.85#ibcon#about to read 4, iclass 10, count 0 2006.202.01:19:14.85#ibcon#read 4, iclass 10, count 0 2006.202.01:19:14.85#ibcon#about to read 5, iclass 10, count 0 2006.202.01:19:14.85#ibcon#read 5, iclass 10, count 0 2006.202.01:19:14.85#ibcon#about to read 6, iclass 10, count 0 2006.202.01:19:14.88#ibcon#read 6, iclass 10, count 0 2006.202.01:19:14.88#ibcon#end of sib2, iclass 10, count 0 2006.202.01:19:14.88#ibcon#*after write, iclass 10, count 0 2006.202.01:19:14.88#ibcon#*before return 0, iclass 10, count 0 2006.202.01:19:14.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:14.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:19:14.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.01:19:14.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.01:19:14.88$vck44/vb=3,4 2006.202.01:19:14.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.202.01:19:14.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.202.01:19:14.88#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:14.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:14.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:14.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:14.91#ibcon#enter wrdev, iclass 12, count 2 2006.202.01:19:14.91#ibcon#first serial, iclass 12, count 2 2006.202.01:19:14.91#ibcon#enter sib2, iclass 12, count 2 2006.202.01:19:14.91#ibcon#flushed, iclass 12, count 2 2006.202.01:19:14.91#ibcon#about to write, iclass 12, count 2 2006.202.01:19:14.91#ibcon#wrote, iclass 12, count 2 2006.202.01:19:14.91#ibcon#about to read 3, iclass 12, count 2 2006.202.01:19:14.93#ibcon#read 3, iclass 12, count 2 2006.202.01:19:14.93#ibcon#about to read 4, iclass 12, count 2 2006.202.01:19:14.93#ibcon#read 4, iclass 12, count 2 2006.202.01:19:14.93#ibcon#about to read 5, iclass 12, count 2 2006.202.01:19:14.93#ibcon#read 5, iclass 12, count 2 2006.202.01:19:14.93#ibcon#about to read 6, iclass 12, count 2 2006.202.01:19:14.93#ibcon#read 6, iclass 12, count 2 2006.202.01:19:14.93#ibcon#end of sib2, iclass 12, count 2 2006.202.01:19:14.93#ibcon#*mode == 0, iclass 12, count 2 2006.202.01:19:14.93#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.202.01:19:14.93#ibcon#[27=AT03-04\r\n] 2006.202.01:19:14.93#ibcon#*before write, iclass 12, count 2 2006.202.01:19:14.93#ibcon#enter sib2, iclass 12, count 2 2006.202.01:19:14.93#ibcon#flushed, iclass 12, count 2 2006.202.01:19:14.93#ibcon#about to write, iclass 12, count 2 2006.202.01:19:14.93#ibcon#wrote, iclass 12, count 2 2006.202.01:19:14.93#ibcon#about to read 3, iclass 12, count 2 2006.202.01:19:14.96#ibcon#read 3, iclass 12, count 2 2006.202.01:19:14.96#ibcon#about to read 4, iclass 12, count 2 2006.202.01:19:14.96#ibcon#read 4, iclass 12, count 2 2006.202.01:19:14.96#ibcon#about to read 5, iclass 12, count 2 2006.202.01:19:14.96#ibcon#read 5, iclass 12, count 2 2006.202.01:19:14.96#ibcon#about to read 6, iclass 12, count 2 2006.202.01:19:14.96#ibcon#read 6, iclass 12, count 2 2006.202.01:19:14.96#ibcon#end of sib2, iclass 12, count 2 2006.202.01:19:14.96#ibcon#*after write, iclass 12, count 2 2006.202.01:19:14.96#ibcon#*before return 0, iclass 12, count 2 2006.202.01:19:14.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:14.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:19:14.96#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.202.01:19:14.96#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:14.96#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:15.08#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:15.08#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:15.08#ibcon#enter wrdev, iclass 12, count 0 2006.202.01:19:15.08#ibcon#first serial, iclass 12, count 0 2006.202.01:19:15.08#ibcon#enter sib2, iclass 12, count 0 2006.202.01:19:15.08#ibcon#flushed, iclass 12, count 0 2006.202.01:19:15.08#ibcon#about to write, iclass 12, count 0 2006.202.01:19:15.08#ibcon#wrote, iclass 12, count 0 2006.202.01:19:15.08#ibcon#about to read 3, iclass 12, count 0 2006.202.01:19:15.10#ibcon#read 3, iclass 12, count 0 2006.202.01:19:15.10#ibcon#about to read 4, iclass 12, count 0 2006.202.01:19:15.10#ibcon#read 4, iclass 12, count 0 2006.202.01:19:15.10#ibcon#about to read 5, iclass 12, count 0 2006.202.01:19:15.10#ibcon#read 5, iclass 12, count 0 2006.202.01:19:15.10#ibcon#about to read 6, iclass 12, count 0 2006.202.01:19:15.10#ibcon#read 6, iclass 12, count 0 2006.202.01:19:15.10#ibcon#end of sib2, iclass 12, count 0 2006.202.01:19:15.10#ibcon#*mode == 0, iclass 12, count 0 2006.202.01:19:15.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.01:19:15.10#ibcon#[27=USB\r\n] 2006.202.01:19:15.10#ibcon#*before write, iclass 12, count 0 2006.202.01:19:15.10#ibcon#enter sib2, iclass 12, count 0 2006.202.01:19:15.10#ibcon#flushed, iclass 12, count 0 2006.202.01:19:15.10#ibcon#about to write, iclass 12, count 0 2006.202.01:19:15.10#ibcon#wrote, iclass 12, count 0 2006.202.01:19:15.10#ibcon#about to read 3, iclass 12, count 0 2006.202.01:19:15.13#ibcon#read 3, iclass 12, count 0 2006.202.01:19:15.13#ibcon#about to read 4, iclass 12, count 0 2006.202.01:19:15.13#ibcon#read 4, iclass 12, count 0 2006.202.01:19:15.13#ibcon#about to read 5, iclass 12, count 0 2006.202.01:19:15.13#ibcon#read 5, iclass 12, count 0 2006.202.01:19:15.13#ibcon#about to read 6, iclass 12, count 0 2006.202.01:19:15.13#ibcon#read 6, iclass 12, count 0 2006.202.01:19:15.13#ibcon#end of sib2, iclass 12, count 0 2006.202.01:19:15.13#ibcon#*after write, iclass 12, count 0 2006.202.01:19:15.13#ibcon#*before return 0, iclass 12, count 0 2006.202.01:19:15.13#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:15.13#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:19:15.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.01:19:15.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.01:19:15.13$vck44/vblo=4,679.99 2006.202.01:19:15.13#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.01:19:15.13#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.01:19:15.13#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:15.13#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:15.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:15.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:15.13#ibcon#enter wrdev, iclass 14, count 0 2006.202.01:19:15.13#ibcon#first serial, iclass 14, count 0 2006.202.01:19:15.13#ibcon#enter sib2, iclass 14, count 0 2006.202.01:19:15.13#ibcon#flushed, iclass 14, count 0 2006.202.01:19:15.13#ibcon#about to write, iclass 14, count 0 2006.202.01:19:15.13#ibcon#wrote, iclass 14, count 0 2006.202.01:19:15.13#ibcon#about to read 3, iclass 14, count 0 2006.202.01:19:15.15#ibcon#read 3, iclass 14, count 0 2006.202.01:19:15.15#ibcon#about to read 4, iclass 14, count 0 2006.202.01:19:15.15#ibcon#read 4, iclass 14, count 0 2006.202.01:19:15.15#ibcon#about to read 5, iclass 14, count 0 2006.202.01:19:15.15#ibcon#read 5, iclass 14, count 0 2006.202.01:19:15.15#ibcon#about to read 6, iclass 14, count 0 2006.202.01:19:15.15#ibcon#read 6, iclass 14, count 0 2006.202.01:19:15.15#ibcon#end of sib2, iclass 14, count 0 2006.202.01:19:15.15#ibcon#*mode == 0, iclass 14, count 0 2006.202.01:19:15.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.01:19:15.15#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.01:19:15.15#ibcon#*before write, iclass 14, count 0 2006.202.01:19:15.15#ibcon#enter sib2, iclass 14, count 0 2006.202.01:19:15.15#ibcon#flushed, iclass 14, count 0 2006.202.01:19:15.15#ibcon#about to write, iclass 14, count 0 2006.202.01:19:15.15#ibcon#wrote, iclass 14, count 0 2006.202.01:19:15.15#ibcon#about to read 3, iclass 14, count 0 2006.202.01:19:15.19#ibcon#read 3, iclass 14, count 0 2006.202.01:19:15.19#ibcon#about to read 4, iclass 14, count 0 2006.202.01:19:15.19#ibcon#read 4, iclass 14, count 0 2006.202.01:19:15.19#ibcon#about to read 5, iclass 14, count 0 2006.202.01:19:15.19#ibcon#read 5, iclass 14, count 0 2006.202.01:19:15.19#ibcon#about to read 6, iclass 14, count 0 2006.202.01:19:15.19#ibcon#read 6, iclass 14, count 0 2006.202.01:19:15.19#ibcon#end of sib2, iclass 14, count 0 2006.202.01:19:15.19#ibcon#*after write, iclass 14, count 0 2006.202.01:19:15.19#ibcon#*before return 0, iclass 14, count 0 2006.202.01:19:15.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:15.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:19:15.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.01:19:15.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.01:19:15.19$vck44/vb=4,5 2006.202.01:19:15.19#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.01:19:15.19#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.01:19:15.19#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:15.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:15.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:15.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:15.25#ibcon#enter wrdev, iclass 16, count 2 2006.202.01:19:15.25#ibcon#first serial, iclass 16, count 2 2006.202.01:19:15.25#ibcon#enter sib2, iclass 16, count 2 2006.202.01:19:15.25#ibcon#flushed, iclass 16, count 2 2006.202.01:19:15.25#ibcon#about to write, iclass 16, count 2 2006.202.01:19:15.25#ibcon#wrote, iclass 16, count 2 2006.202.01:19:15.25#ibcon#about to read 3, iclass 16, count 2 2006.202.01:19:15.27#ibcon#read 3, iclass 16, count 2 2006.202.01:19:15.27#ibcon#about to read 4, iclass 16, count 2 2006.202.01:19:15.27#ibcon#read 4, iclass 16, count 2 2006.202.01:19:15.27#ibcon#about to read 5, iclass 16, count 2 2006.202.01:19:15.27#ibcon#read 5, iclass 16, count 2 2006.202.01:19:15.27#ibcon#about to read 6, iclass 16, count 2 2006.202.01:19:15.27#ibcon#read 6, iclass 16, count 2 2006.202.01:19:15.27#ibcon#end of sib2, iclass 16, count 2 2006.202.01:19:15.27#ibcon#*mode == 0, iclass 16, count 2 2006.202.01:19:15.27#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.01:19:15.27#ibcon#[27=AT04-05\r\n] 2006.202.01:19:15.27#ibcon#*before write, iclass 16, count 2 2006.202.01:19:15.27#ibcon#enter sib2, iclass 16, count 2 2006.202.01:19:15.27#ibcon#flushed, iclass 16, count 2 2006.202.01:19:15.27#ibcon#about to write, iclass 16, count 2 2006.202.01:19:15.27#ibcon#wrote, iclass 16, count 2 2006.202.01:19:15.27#ibcon#about to read 3, iclass 16, count 2 2006.202.01:19:15.30#ibcon#read 3, iclass 16, count 2 2006.202.01:19:15.30#ibcon#about to read 4, iclass 16, count 2 2006.202.01:19:15.30#ibcon#read 4, iclass 16, count 2 2006.202.01:19:15.30#ibcon#about to read 5, iclass 16, count 2 2006.202.01:19:15.30#ibcon#read 5, iclass 16, count 2 2006.202.01:19:15.30#ibcon#about to read 6, iclass 16, count 2 2006.202.01:19:15.30#ibcon#read 6, iclass 16, count 2 2006.202.01:19:15.30#ibcon#end of sib2, iclass 16, count 2 2006.202.01:19:15.30#ibcon#*after write, iclass 16, count 2 2006.202.01:19:15.30#ibcon#*before return 0, iclass 16, count 2 2006.202.01:19:15.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:15.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:19:15.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.01:19:15.30#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:15.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:15.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:15.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:15.42#ibcon#enter wrdev, iclass 16, count 0 2006.202.01:19:15.42#ibcon#first serial, iclass 16, count 0 2006.202.01:19:15.42#ibcon#enter sib2, iclass 16, count 0 2006.202.01:19:15.42#ibcon#flushed, iclass 16, count 0 2006.202.01:19:15.42#ibcon#about to write, iclass 16, count 0 2006.202.01:19:15.42#ibcon#wrote, iclass 16, count 0 2006.202.01:19:15.42#ibcon#about to read 3, iclass 16, count 0 2006.202.01:19:15.44#ibcon#read 3, iclass 16, count 0 2006.202.01:19:15.44#ibcon#about to read 4, iclass 16, count 0 2006.202.01:19:15.44#ibcon#read 4, iclass 16, count 0 2006.202.01:19:15.44#ibcon#about to read 5, iclass 16, count 0 2006.202.01:19:15.44#ibcon#read 5, iclass 16, count 0 2006.202.01:19:15.44#ibcon#about to read 6, iclass 16, count 0 2006.202.01:19:15.44#ibcon#read 6, iclass 16, count 0 2006.202.01:19:15.44#ibcon#end of sib2, iclass 16, count 0 2006.202.01:19:15.44#ibcon#*mode == 0, iclass 16, count 0 2006.202.01:19:15.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.01:19:15.44#ibcon#[27=USB\r\n] 2006.202.01:19:15.44#ibcon#*before write, iclass 16, count 0 2006.202.01:19:15.44#ibcon#enter sib2, iclass 16, count 0 2006.202.01:19:15.44#ibcon#flushed, iclass 16, count 0 2006.202.01:19:15.44#ibcon#about to write, iclass 16, count 0 2006.202.01:19:15.44#ibcon#wrote, iclass 16, count 0 2006.202.01:19:15.44#ibcon#about to read 3, iclass 16, count 0 2006.202.01:19:15.47#ibcon#read 3, iclass 16, count 0 2006.202.01:19:15.47#ibcon#about to read 4, iclass 16, count 0 2006.202.01:19:15.47#ibcon#read 4, iclass 16, count 0 2006.202.01:19:15.47#ibcon#about to read 5, iclass 16, count 0 2006.202.01:19:15.47#ibcon#read 5, iclass 16, count 0 2006.202.01:19:15.47#ibcon#about to read 6, iclass 16, count 0 2006.202.01:19:15.47#ibcon#read 6, iclass 16, count 0 2006.202.01:19:15.47#ibcon#end of sib2, iclass 16, count 0 2006.202.01:19:15.47#ibcon#*after write, iclass 16, count 0 2006.202.01:19:15.47#ibcon#*before return 0, iclass 16, count 0 2006.202.01:19:15.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:15.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:19:15.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.01:19:15.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.01:19:15.47$vck44/vblo=5,709.99 2006.202.01:19:15.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.01:19:15.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.01:19:15.47#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:15.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:15.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:15.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:15.47#ibcon#enter wrdev, iclass 18, count 0 2006.202.01:19:15.47#ibcon#first serial, iclass 18, count 0 2006.202.01:19:15.47#ibcon#enter sib2, iclass 18, count 0 2006.202.01:19:15.47#ibcon#flushed, iclass 18, count 0 2006.202.01:19:15.47#ibcon#about to write, iclass 18, count 0 2006.202.01:19:15.47#ibcon#wrote, iclass 18, count 0 2006.202.01:19:15.47#ibcon#about to read 3, iclass 18, count 0 2006.202.01:19:15.49#ibcon#read 3, iclass 18, count 0 2006.202.01:19:15.49#ibcon#about to read 4, iclass 18, count 0 2006.202.01:19:15.49#ibcon#read 4, iclass 18, count 0 2006.202.01:19:15.49#ibcon#about to read 5, iclass 18, count 0 2006.202.01:19:15.49#ibcon#read 5, iclass 18, count 0 2006.202.01:19:15.49#ibcon#about to read 6, iclass 18, count 0 2006.202.01:19:15.49#ibcon#read 6, iclass 18, count 0 2006.202.01:19:15.49#ibcon#end of sib2, iclass 18, count 0 2006.202.01:19:15.49#ibcon#*mode == 0, iclass 18, count 0 2006.202.01:19:15.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.01:19:15.49#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.01:19:15.49#ibcon#*before write, iclass 18, count 0 2006.202.01:19:15.49#ibcon#enter sib2, iclass 18, count 0 2006.202.01:19:15.49#ibcon#flushed, iclass 18, count 0 2006.202.01:19:15.49#ibcon#about to write, iclass 18, count 0 2006.202.01:19:15.49#ibcon#wrote, iclass 18, count 0 2006.202.01:19:15.49#ibcon#about to read 3, iclass 18, count 0 2006.202.01:19:15.53#ibcon#read 3, iclass 18, count 0 2006.202.01:19:15.53#ibcon#about to read 4, iclass 18, count 0 2006.202.01:19:15.53#ibcon#read 4, iclass 18, count 0 2006.202.01:19:15.53#ibcon#about to read 5, iclass 18, count 0 2006.202.01:19:15.53#ibcon#read 5, iclass 18, count 0 2006.202.01:19:15.53#ibcon#about to read 6, iclass 18, count 0 2006.202.01:19:15.53#ibcon#read 6, iclass 18, count 0 2006.202.01:19:15.53#ibcon#end of sib2, iclass 18, count 0 2006.202.01:19:15.53#ibcon#*after write, iclass 18, count 0 2006.202.01:19:15.53#ibcon#*before return 0, iclass 18, count 0 2006.202.01:19:15.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:15.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:19:15.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.01:19:15.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.01:19:15.53$vck44/vb=5,4 2006.202.01:19:15.53#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.01:19:15.53#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.01:19:15.53#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:15.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:15.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:15.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:15.59#ibcon#enter wrdev, iclass 20, count 2 2006.202.01:19:15.59#ibcon#first serial, iclass 20, count 2 2006.202.01:19:15.59#ibcon#enter sib2, iclass 20, count 2 2006.202.01:19:15.59#ibcon#flushed, iclass 20, count 2 2006.202.01:19:15.59#ibcon#about to write, iclass 20, count 2 2006.202.01:19:15.59#ibcon#wrote, iclass 20, count 2 2006.202.01:19:15.59#ibcon#about to read 3, iclass 20, count 2 2006.202.01:19:15.61#ibcon#read 3, iclass 20, count 2 2006.202.01:19:15.61#ibcon#about to read 4, iclass 20, count 2 2006.202.01:19:15.61#ibcon#read 4, iclass 20, count 2 2006.202.01:19:15.61#ibcon#about to read 5, iclass 20, count 2 2006.202.01:19:15.61#ibcon#read 5, iclass 20, count 2 2006.202.01:19:15.61#ibcon#about to read 6, iclass 20, count 2 2006.202.01:19:15.61#ibcon#read 6, iclass 20, count 2 2006.202.01:19:15.61#ibcon#end of sib2, iclass 20, count 2 2006.202.01:19:15.61#ibcon#*mode == 0, iclass 20, count 2 2006.202.01:19:15.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.01:19:15.61#ibcon#[27=AT05-04\r\n] 2006.202.01:19:15.61#ibcon#*before write, iclass 20, count 2 2006.202.01:19:15.61#ibcon#enter sib2, iclass 20, count 2 2006.202.01:19:15.61#ibcon#flushed, iclass 20, count 2 2006.202.01:19:15.61#ibcon#about to write, iclass 20, count 2 2006.202.01:19:15.61#ibcon#wrote, iclass 20, count 2 2006.202.01:19:15.61#ibcon#about to read 3, iclass 20, count 2 2006.202.01:19:15.64#ibcon#read 3, iclass 20, count 2 2006.202.01:19:15.64#ibcon#about to read 4, iclass 20, count 2 2006.202.01:19:15.64#ibcon#read 4, iclass 20, count 2 2006.202.01:19:15.64#ibcon#about to read 5, iclass 20, count 2 2006.202.01:19:15.64#ibcon#read 5, iclass 20, count 2 2006.202.01:19:15.64#ibcon#about to read 6, iclass 20, count 2 2006.202.01:19:15.64#ibcon#read 6, iclass 20, count 2 2006.202.01:19:15.64#ibcon#end of sib2, iclass 20, count 2 2006.202.01:19:15.64#ibcon#*after write, iclass 20, count 2 2006.202.01:19:15.64#ibcon#*before return 0, iclass 20, count 2 2006.202.01:19:15.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:15.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:19:15.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.01:19:15.64#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:15.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:15.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:15.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:15.76#ibcon#enter wrdev, iclass 20, count 0 2006.202.01:19:15.76#ibcon#first serial, iclass 20, count 0 2006.202.01:19:15.76#ibcon#enter sib2, iclass 20, count 0 2006.202.01:19:15.76#ibcon#flushed, iclass 20, count 0 2006.202.01:19:15.76#ibcon#about to write, iclass 20, count 0 2006.202.01:19:15.76#ibcon#wrote, iclass 20, count 0 2006.202.01:19:15.76#ibcon#about to read 3, iclass 20, count 0 2006.202.01:19:15.78#ibcon#read 3, iclass 20, count 0 2006.202.01:19:15.78#ibcon#about to read 4, iclass 20, count 0 2006.202.01:19:15.78#ibcon#read 4, iclass 20, count 0 2006.202.01:19:15.78#ibcon#about to read 5, iclass 20, count 0 2006.202.01:19:15.78#ibcon#read 5, iclass 20, count 0 2006.202.01:19:15.78#ibcon#about to read 6, iclass 20, count 0 2006.202.01:19:15.78#ibcon#read 6, iclass 20, count 0 2006.202.01:19:15.78#ibcon#end of sib2, iclass 20, count 0 2006.202.01:19:15.78#ibcon#*mode == 0, iclass 20, count 0 2006.202.01:19:15.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.01:19:15.78#ibcon#[27=USB\r\n] 2006.202.01:19:15.78#ibcon#*before write, iclass 20, count 0 2006.202.01:19:15.78#ibcon#enter sib2, iclass 20, count 0 2006.202.01:19:15.78#ibcon#flushed, iclass 20, count 0 2006.202.01:19:15.78#ibcon#about to write, iclass 20, count 0 2006.202.01:19:15.78#ibcon#wrote, iclass 20, count 0 2006.202.01:19:15.78#ibcon#about to read 3, iclass 20, count 0 2006.202.01:19:15.81#ibcon#read 3, iclass 20, count 0 2006.202.01:19:15.81#ibcon#about to read 4, iclass 20, count 0 2006.202.01:19:15.81#ibcon#read 4, iclass 20, count 0 2006.202.01:19:15.81#ibcon#about to read 5, iclass 20, count 0 2006.202.01:19:15.81#ibcon#read 5, iclass 20, count 0 2006.202.01:19:15.81#ibcon#about to read 6, iclass 20, count 0 2006.202.01:19:15.81#ibcon#read 6, iclass 20, count 0 2006.202.01:19:15.81#ibcon#end of sib2, iclass 20, count 0 2006.202.01:19:15.81#ibcon#*after write, iclass 20, count 0 2006.202.01:19:15.81#ibcon#*before return 0, iclass 20, count 0 2006.202.01:19:15.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:15.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:19:15.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.01:19:15.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.01:19:15.81$vck44/vblo=6,719.99 2006.202.01:19:15.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.01:19:15.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.01:19:15.81#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:15.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:15.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:15.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:15.81#ibcon#enter wrdev, iclass 22, count 0 2006.202.01:19:15.81#ibcon#first serial, iclass 22, count 0 2006.202.01:19:15.81#ibcon#enter sib2, iclass 22, count 0 2006.202.01:19:15.81#ibcon#flushed, iclass 22, count 0 2006.202.01:19:15.81#ibcon#about to write, iclass 22, count 0 2006.202.01:19:15.81#ibcon#wrote, iclass 22, count 0 2006.202.01:19:15.81#ibcon#about to read 3, iclass 22, count 0 2006.202.01:19:15.83#ibcon#read 3, iclass 22, count 0 2006.202.01:19:15.83#ibcon#about to read 4, iclass 22, count 0 2006.202.01:19:15.83#ibcon#read 4, iclass 22, count 0 2006.202.01:19:15.83#ibcon#about to read 5, iclass 22, count 0 2006.202.01:19:15.83#ibcon#read 5, iclass 22, count 0 2006.202.01:19:15.83#ibcon#about to read 6, iclass 22, count 0 2006.202.01:19:15.83#ibcon#read 6, iclass 22, count 0 2006.202.01:19:15.83#ibcon#end of sib2, iclass 22, count 0 2006.202.01:19:15.83#ibcon#*mode == 0, iclass 22, count 0 2006.202.01:19:15.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.01:19:15.83#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.01:19:15.83#ibcon#*before write, iclass 22, count 0 2006.202.01:19:15.83#ibcon#enter sib2, iclass 22, count 0 2006.202.01:19:15.83#ibcon#flushed, iclass 22, count 0 2006.202.01:19:15.83#ibcon#about to write, iclass 22, count 0 2006.202.01:19:15.83#ibcon#wrote, iclass 22, count 0 2006.202.01:19:15.83#ibcon#about to read 3, iclass 22, count 0 2006.202.01:19:15.87#ibcon#read 3, iclass 22, count 0 2006.202.01:19:15.87#ibcon#about to read 4, iclass 22, count 0 2006.202.01:19:15.87#ibcon#read 4, iclass 22, count 0 2006.202.01:19:15.87#ibcon#about to read 5, iclass 22, count 0 2006.202.01:19:15.87#ibcon#read 5, iclass 22, count 0 2006.202.01:19:15.87#ibcon#about to read 6, iclass 22, count 0 2006.202.01:19:15.87#ibcon#read 6, iclass 22, count 0 2006.202.01:19:15.87#ibcon#end of sib2, iclass 22, count 0 2006.202.01:19:15.87#ibcon#*after write, iclass 22, count 0 2006.202.01:19:15.87#ibcon#*before return 0, iclass 22, count 0 2006.202.01:19:15.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:15.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:19:15.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.01:19:15.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.01:19:15.87$vck44/vb=6,4 2006.202.01:19:15.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.01:19:15.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.01:19:15.87#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:15.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:15.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:15.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:15.93#ibcon#enter wrdev, iclass 24, count 2 2006.202.01:19:15.93#ibcon#first serial, iclass 24, count 2 2006.202.01:19:15.93#ibcon#enter sib2, iclass 24, count 2 2006.202.01:19:15.93#ibcon#flushed, iclass 24, count 2 2006.202.01:19:15.93#ibcon#about to write, iclass 24, count 2 2006.202.01:19:15.93#ibcon#wrote, iclass 24, count 2 2006.202.01:19:15.93#ibcon#about to read 3, iclass 24, count 2 2006.202.01:19:15.95#ibcon#read 3, iclass 24, count 2 2006.202.01:19:15.95#ibcon#about to read 4, iclass 24, count 2 2006.202.01:19:15.95#ibcon#read 4, iclass 24, count 2 2006.202.01:19:15.95#ibcon#about to read 5, iclass 24, count 2 2006.202.01:19:15.95#ibcon#read 5, iclass 24, count 2 2006.202.01:19:15.95#ibcon#about to read 6, iclass 24, count 2 2006.202.01:19:15.95#ibcon#read 6, iclass 24, count 2 2006.202.01:19:15.95#ibcon#end of sib2, iclass 24, count 2 2006.202.01:19:15.95#ibcon#*mode == 0, iclass 24, count 2 2006.202.01:19:15.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.01:19:15.95#ibcon#[27=AT06-04\r\n] 2006.202.01:19:15.95#ibcon#*before write, iclass 24, count 2 2006.202.01:19:15.95#ibcon#enter sib2, iclass 24, count 2 2006.202.01:19:15.95#ibcon#flushed, iclass 24, count 2 2006.202.01:19:15.95#ibcon#about to write, iclass 24, count 2 2006.202.01:19:15.95#ibcon#wrote, iclass 24, count 2 2006.202.01:19:15.95#ibcon#about to read 3, iclass 24, count 2 2006.202.01:19:15.98#ibcon#read 3, iclass 24, count 2 2006.202.01:19:15.98#ibcon#about to read 4, iclass 24, count 2 2006.202.01:19:15.98#ibcon#read 4, iclass 24, count 2 2006.202.01:19:15.98#ibcon#about to read 5, iclass 24, count 2 2006.202.01:19:15.98#ibcon#read 5, iclass 24, count 2 2006.202.01:19:15.98#ibcon#about to read 6, iclass 24, count 2 2006.202.01:19:15.98#ibcon#read 6, iclass 24, count 2 2006.202.01:19:15.98#ibcon#end of sib2, iclass 24, count 2 2006.202.01:19:15.98#ibcon#*after write, iclass 24, count 2 2006.202.01:19:15.98#ibcon#*before return 0, iclass 24, count 2 2006.202.01:19:15.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:15.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:19:15.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.01:19:15.98#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:15.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:16.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:16.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:16.10#ibcon#enter wrdev, iclass 24, count 0 2006.202.01:19:16.10#ibcon#first serial, iclass 24, count 0 2006.202.01:19:16.10#ibcon#enter sib2, iclass 24, count 0 2006.202.01:19:16.10#ibcon#flushed, iclass 24, count 0 2006.202.01:19:16.10#ibcon#about to write, iclass 24, count 0 2006.202.01:19:16.10#ibcon#wrote, iclass 24, count 0 2006.202.01:19:16.10#ibcon#about to read 3, iclass 24, count 0 2006.202.01:19:16.12#ibcon#read 3, iclass 24, count 0 2006.202.01:19:16.12#ibcon#about to read 4, iclass 24, count 0 2006.202.01:19:16.12#ibcon#read 4, iclass 24, count 0 2006.202.01:19:16.12#ibcon#about to read 5, iclass 24, count 0 2006.202.01:19:16.12#ibcon#read 5, iclass 24, count 0 2006.202.01:19:16.12#ibcon#about to read 6, iclass 24, count 0 2006.202.01:19:16.12#ibcon#read 6, iclass 24, count 0 2006.202.01:19:16.12#ibcon#end of sib2, iclass 24, count 0 2006.202.01:19:16.12#ibcon#*mode == 0, iclass 24, count 0 2006.202.01:19:16.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.01:19:16.12#ibcon#[27=USB\r\n] 2006.202.01:19:16.12#ibcon#*before write, iclass 24, count 0 2006.202.01:19:16.12#ibcon#enter sib2, iclass 24, count 0 2006.202.01:19:16.12#ibcon#flushed, iclass 24, count 0 2006.202.01:19:16.12#ibcon#about to write, iclass 24, count 0 2006.202.01:19:16.12#ibcon#wrote, iclass 24, count 0 2006.202.01:19:16.12#ibcon#about to read 3, iclass 24, count 0 2006.202.01:19:16.15#ibcon#read 3, iclass 24, count 0 2006.202.01:19:16.15#ibcon#about to read 4, iclass 24, count 0 2006.202.01:19:16.15#ibcon#read 4, iclass 24, count 0 2006.202.01:19:16.15#ibcon#about to read 5, iclass 24, count 0 2006.202.01:19:16.15#ibcon#read 5, iclass 24, count 0 2006.202.01:19:16.15#ibcon#about to read 6, iclass 24, count 0 2006.202.01:19:16.15#ibcon#read 6, iclass 24, count 0 2006.202.01:19:16.15#ibcon#end of sib2, iclass 24, count 0 2006.202.01:19:16.15#ibcon#*after write, iclass 24, count 0 2006.202.01:19:16.15#ibcon#*before return 0, iclass 24, count 0 2006.202.01:19:16.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:16.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:19:16.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.01:19:16.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.01:19:16.15$vck44/vblo=7,734.99 2006.202.01:19:16.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.01:19:16.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.01:19:16.15#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:16.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:16.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:16.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:16.15#ibcon#enter wrdev, iclass 26, count 0 2006.202.01:19:16.15#ibcon#first serial, iclass 26, count 0 2006.202.01:19:16.15#ibcon#enter sib2, iclass 26, count 0 2006.202.01:19:16.15#ibcon#flushed, iclass 26, count 0 2006.202.01:19:16.15#ibcon#about to write, iclass 26, count 0 2006.202.01:19:16.15#ibcon#wrote, iclass 26, count 0 2006.202.01:19:16.15#ibcon#about to read 3, iclass 26, count 0 2006.202.01:19:16.17#ibcon#read 3, iclass 26, count 0 2006.202.01:19:16.17#ibcon#about to read 4, iclass 26, count 0 2006.202.01:19:16.17#ibcon#read 4, iclass 26, count 0 2006.202.01:19:16.17#ibcon#about to read 5, iclass 26, count 0 2006.202.01:19:16.17#ibcon#read 5, iclass 26, count 0 2006.202.01:19:16.17#ibcon#about to read 6, iclass 26, count 0 2006.202.01:19:16.17#ibcon#read 6, iclass 26, count 0 2006.202.01:19:16.17#ibcon#end of sib2, iclass 26, count 0 2006.202.01:19:16.17#ibcon#*mode == 0, iclass 26, count 0 2006.202.01:19:16.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.01:19:16.17#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.01:19:16.17#ibcon#*before write, iclass 26, count 0 2006.202.01:19:16.17#ibcon#enter sib2, iclass 26, count 0 2006.202.01:19:16.17#ibcon#flushed, iclass 26, count 0 2006.202.01:19:16.17#ibcon#about to write, iclass 26, count 0 2006.202.01:19:16.17#ibcon#wrote, iclass 26, count 0 2006.202.01:19:16.17#ibcon#about to read 3, iclass 26, count 0 2006.202.01:19:16.21#ibcon#read 3, iclass 26, count 0 2006.202.01:19:16.21#ibcon#about to read 4, iclass 26, count 0 2006.202.01:19:16.21#ibcon#read 4, iclass 26, count 0 2006.202.01:19:16.21#ibcon#about to read 5, iclass 26, count 0 2006.202.01:19:16.21#ibcon#read 5, iclass 26, count 0 2006.202.01:19:16.21#ibcon#about to read 6, iclass 26, count 0 2006.202.01:19:16.21#ibcon#read 6, iclass 26, count 0 2006.202.01:19:16.21#ibcon#end of sib2, iclass 26, count 0 2006.202.01:19:16.21#ibcon#*after write, iclass 26, count 0 2006.202.01:19:16.21#ibcon#*before return 0, iclass 26, count 0 2006.202.01:19:16.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:16.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:19:16.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.01:19:16.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.01:19:16.21$vck44/vb=7,4 2006.202.01:19:16.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.01:19:16.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.01:19:16.21#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:16.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:16.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:16.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:16.27#ibcon#enter wrdev, iclass 28, count 2 2006.202.01:19:16.27#ibcon#first serial, iclass 28, count 2 2006.202.01:19:16.27#ibcon#enter sib2, iclass 28, count 2 2006.202.01:19:16.27#ibcon#flushed, iclass 28, count 2 2006.202.01:19:16.27#ibcon#about to write, iclass 28, count 2 2006.202.01:19:16.27#ibcon#wrote, iclass 28, count 2 2006.202.01:19:16.27#ibcon#about to read 3, iclass 28, count 2 2006.202.01:19:16.29#ibcon#read 3, iclass 28, count 2 2006.202.01:19:16.29#ibcon#about to read 4, iclass 28, count 2 2006.202.01:19:16.29#ibcon#read 4, iclass 28, count 2 2006.202.01:19:16.29#ibcon#about to read 5, iclass 28, count 2 2006.202.01:19:16.29#ibcon#read 5, iclass 28, count 2 2006.202.01:19:16.29#ibcon#about to read 6, iclass 28, count 2 2006.202.01:19:16.29#ibcon#read 6, iclass 28, count 2 2006.202.01:19:16.29#ibcon#end of sib2, iclass 28, count 2 2006.202.01:19:16.29#ibcon#*mode == 0, iclass 28, count 2 2006.202.01:19:16.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.01:19:16.29#ibcon#[27=AT07-04\r\n] 2006.202.01:19:16.29#ibcon#*before write, iclass 28, count 2 2006.202.01:19:16.29#ibcon#enter sib2, iclass 28, count 2 2006.202.01:19:16.29#ibcon#flushed, iclass 28, count 2 2006.202.01:19:16.29#ibcon#about to write, iclass 28, count 2 2006.202.01:19:16.29#ibcon#wrote, iclass 28, count 2 2006.202.01:19:16.29#ibcon#about to read 3, iclass 28, count 2 2006.202.01:19:16.32#ibcon#read 3, iclass 28, count 2 2006.202.01:19:16.32#ibcon#about to read 4, iclass 28, count 2 2006.202.01:19:16.32#ibcon#read 4, iclass 28, count 2 2006.202.01:19:16.32#ibcon#about to read 5, iclass 28, count 2 2006.202.01:19:16.32#ibcon#read 5, iclass 28, count 2 2006.202.01:19:16.32#ibcon#about to read 6, iclass 28, count 2 2006.202.01:19:16.32#ibcon#read 6, iclass 28, count 2 2006.202.01:19:16.32#ibcon#end of sib2, iclass 28, count 2 2006.202.01:19:16.32#ibcon#*after write, iclass 28, count 2 2006.202.01:19:16.32#ibcon#*before return 0, iclass 28, count 2 2006.202.01:19:16.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:16.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:19:16.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.01:19:16.32#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:16.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:16.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:16.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:16.44#ibcon#enter wrdev, iclass 28, count 0 2006.202.01:19:16.44#ibcon#first serial, iclass 28, count 0 2006.202.01:19:16.44#ibcon#enter sib2, iclass 28, count 0 2006.202.01:19:16.44#ibcon#flushed, iclass 28, count 0 2006.202.01:19:16.44#ibcon#about to write, iclass 28, count 0 2006.202.01:19:16.44#ibcon#wrote, iclass 28, count 0 2006.202.01:19:16.44#ibcon#about to read 3, iclass 28, count 0 2006.202.01:19:16.46#ibcon#read 3, iclass 28, count 0 2006.202.01:19:16.46#ibcon#about to read 4, iclass 28, count 0 2006.202.01:19:16.46#ibcon#read 4, iclass 28, count 0 2006.202.01:19:16.46#ibcon#about to read 5, iclass 28, count 0 2006.202.01:19:16.46#ibcon#read 5, iclass 28, count 0 2006.202.01:19:16.46#ibcon#about to read 6, iclass 28, count 0 2006.202.01:19:16.46#ibcon#read 6, iclass 28, count 0 2006.202.01:19:16.46#ibcon#end of sib2, iclass 28, count 0 2006.202.01:19:16.46#ibcon#*mode == 0, iclass 28, count 0 2006.202.01:19:16.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.01:19:16.46#ibcon#[27=USB\r\n] 2006.202.01:19:16.46#ibcon#*before write, iclass 28, count 0 2006.202.01:19:16.46#ibcon#enter sib2, iclass 28, count 0 2006.202.01:19:16.46#ibcon#flushed, iclass 28, count 0 2006.202.01:19:16.46#ibcon#about to write, iclass 28, count 0 2006.202.01:19:16.46#ibcon#wrote, iclass 28, count 0 2006.202.01:19:16.46#ibcon#about to read 3, iclass 28, count 0 2006.202.01:19:16.49#ibcon#read 3, iclass 28, count 0 2006.202.01:19:16.49#ibcon#about to read 4, iclass 28, count 0 2006.202.01:19:16.49#ibcon#read 4, iclass 28, count 0 2006.202.01:19:16.49#ibcon#about to read 5, iclass 28, count 0 2006.202.01:19:16.49#ibcon#read 5, iclass 28, count 0 2006.202.01:19:16.49#ibcon#about to read 6, iclass 28, count 0 2006.202.01:19:16.49#ibcon#read 6, iclass 28, count 0 2006.202.01:19:16.49#ibcon#end of sib2, iclass 28, count 0 2006.202.01:19:16.49#ibcon#*after write, iclass 28, count 0 2006.202.01:19:16.49#ibcon#*before return 0, iclass 28, count 0 2006.202.01:19:16.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:16.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:19:16.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.01:19:16.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.01:19:16.49$vck44/vblo=8,744.99 2006.202.01:19:16.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.01:19:16.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.01:19:16.49#ibcon#ireg 17 cls_cnt 0 2006.202.01:19:16.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:16.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:16.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:16.49#ibcon#enter wrdev, iclass 30, count 0 2006.202.01:19:16.49#ibcon#first serial, iclass 30, count 0 2006.202.01:19:16.49#ibcon#enter sib2, iclass 30, count 0 2006.202.01:19:16.49#ibcon#flushed, iclass 30, count 0 2006.202.01:19:16.49#ibcon#about to write, iclass 30, count 0 2006.202.01:19:16.49#ibcon#wrote, iclass 30, count 0 2006.202.01:19:16.49#ibcon#about to read 3, iclass 30, count 0 2006.202.01:19:16.51#ibcon#read 3, iclass 30, count 0 2006.202.01:19:16.51#ibcon#about to read 4, iclass 30, count 0 2006.202.01:19:16.51#ibcon#read 4, iclass 30, count 0 2006.202.01:19:16.51#ibcon#about to read 5, iclass 30, count 0 2006.202.01:19:16.51#ibcon#read 5, iclass 30, count 0 2006.202.01:19:16.51#ibcon#about to read 6, iclass 30, count 0 2006.202.01:19:16.51#ibcon#read 6, iclass 30, count 0 2006.202.01:19:16.51#ibcon#end of sib2, iclass 30, count 0 2006.202.01:19:16.51#ibcon#*mode == 0, iclass 30, count 0 2006.202.01:19:16.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.01:19:16.51#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.01:19:16.51#ibcon#*before write, iclass 30, count 0 2006.202.01:19:16.51#ibcon#enter sib2, iclass 30, count 0 2006.202.01:19:16.51#ibcon#flushed, iclass 30, count 0 2006.202.01:19:16.51#ibcon#about to write, iclass 30, count 0 2006.202.01:19:16.51#ibcon#wrote, iclass 30, count 0 2006.202.01:19:16.51#ibcon#about to read 3, iclass 30, count 0 2006.202.01:19:16.55#ibcon#read 3, iclass 30, count 0 2006.202.01:19:16.55#ibcon#about to read 4, iclass 30, count 0 2006.202.01:19:16.55#ibcon#read 4, iclass 30, count 0 2006.202.01:19:16.55#ibcon#about to read 5, iclass 30, count 0 2006.202.01:19:16.55#ibcon#read 5, iclass 30, count 0 2006.202.01:19:16.55#ibcon#about to read 6, iclass 30, count 0 2006.202.01:19:16.55#ibcon#read 6, iclass 30, count 0 2006.202.01:19:16.55#ibcon#end of sib2, iclass 30, count 0 2006.202.01:19:16.55#ibcon#*after write, iclass 30, count 0 2006.202.01:19:16.55#ibcon#*before return 0, iclass 30, count 0 2006.202.01:19:16.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:16.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:19:16.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.01:19:16.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.01:19:16.55$vck44/vb=8,4 2006.202.01:19:16.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.01:19:16.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.01:19:16.55#ibcon#ireg 11 cls_cnt 2 2006.202.01:19:16.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:16.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:16.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:16.61#ibcon#enter wrdev, iclass 32, count 2 2006.202.01:19:16.61#ibcon#first serial, iclass 32, count 2 2006.202.01:19:16.61#ibcon#enter sib2, iclass 32, count 2 2006.202.01:19:16.61#ibcon#flushed, iclass 32, count 2 2006.202.01:19:16.61#ibcon#about to write, iclass 32, count 2 2006.202.01:19:16.61#ibcon#wrote, iclass 32, count 2 2006.202.01:19:16.61#ibcon#about to read 3, iclass 32, count 2 2006.202.01:19:16.63#ibcon#read 3, iclass 32, count 2 2006.202.01:19:16.63#ibcon#about to read 4, iclass 32, count 2 2006.202.01:19:16.63#ibcon#read 4, iclass 32, count 2 2006.202.01:19:16.63#ibcon#about to read 5, iclass 32, count 2 2006.202.01:19:16.63#ibcon#read 5, iclass 32, count 2 2006.202.01:19:16.63#ibcon#about to read 6, iclass 32, count 2 2006.202.01:19:16.63#ibcon#read 6, iclass 32, count 2 2006.202.01:19:16.63#ibcon#end of sib2, iclass 32, count 2 2006.202.01:19:16.63#ibcon#*mode == 0, iclass 32, count 2 2006.202.01:19:16.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.01:19:16.63#ibcon#[27=AT08-04\r\n] 2006.202.01:19:16.63#ibcon#*before write, iclass 32, count 2 2006.202.01:19:16.63#ibcon#enter sib2, iclass 32, count 2 2006.202.01:19:16.63#ibcon#flushed, iclass 32, count 2 2006.202.01:19:16.63#ibcon#about to write, iclass 32, count 2 2006.202.01:19:16.63#ibcon#wrote, iclass 32, count 2 2006.202.01:19:16.63#ibcon#about to read 3, iclass 32, count 2 2006.202.01:19:16.66#ibcon#read 3, iclass 32, count 2 2006.202.01:19:16.66#ibcon#about to read 4, iclass 32, count 2 2006.202.01:19:16.66#ibcon#read 4, iclass 32, count 2 2006.202.01:19:16.66#ibcon#about to read 5, iclass 32, count 2 2006.202.01:19:16.66#ibcon#read 5, iclass 32, count 2 2006.202.01:19:16.66#ibcon#about to read 6, iclass 32, count 2 2006.202.01:19:16.66#ibcon#read 6, iclass 32, count 2 2006.202.01:19:16.66#ibcon#end of sib2, iclass 32, count 2 2006.202.01:19:16.66#ibcon#*after write, iclass 32, count 2 2006.202.01:19:16.66#ibcon#*before return 0, iclass 32, count 2 2006.202.01:19:16.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:16.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:19:16.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.01:19:16.66#ibcon#ireg 7 cls_cnt 0 2006.202.01:19:16.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:16.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:16.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:16.78#ibcon#enter wrdev, iclass 32, count 0 2006.202.01:19:16.78#ibcon#first serial, iclass 32, count 0 2006.202.01:19:16.78#ibcon#enter sib2, iclass 32, count 0 2006.202.01:19:16.78#ibcon#flushed, iclass 32, count 0 2006.202.01:19:16.78#ibcon#about to write, iclass 32, count 0 2006.202.01:19:16.78#ibcon#wrote, iclass 32, count 0 2006.202.01:19:16.78#ibcon#about to read 3, iclass 32, count 0 2006.202.01:19:16.80#ibcon#read 3, iclass 32, count 0 2006.202.01:19:16.80#ibcon#about to read 4, iclass 32, count 0 2006.202.01:19:16.80#ibcon#read 4, iclass 32, count 0 2006.202.01:19:16.80#ibcon#about to read 5, iclass 32, count 0 2006.202.01:19:16.80#ibcon#read 5, iclass 32, count 0 2006.202.01:19:16.80#ibcon#about to read 6, iclass 32, count 0 2006.202.01:19:16.80#ibcon#read 6, iclass 32, count 0 2006.202.01:19:16.80#ibcon#end of sib2, iclass 32, count 0 2006.202.01:19:16.80#ibcon#*mode == 0, iclass 32, count 0 2006.202.01:19:16.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.01:19:16.80#ibcon#[27=USB\r\n] 2006.202.01:19:16.80#ibcon#*before write, iclass 32, count 0 2006.202.01:19:16.80#ibcon#enter sib2, iclass 32, count 0 2006.202.01:19:16.80#ibcon#flushed, iclass 32, count 0 2006.202.01:19:16.80#ibcon#about to write, iclass 32, count 0 2006.202.01:19:16.80#ibcon#wrote, iclass 32, count 0 2006.202.01:19:16.80#ibcon#about to read 3, iclass 32, count 0 2006.202.01:19:16.83#ibcon#read 3, iclass 32, count 0 2006.202.01:19:16.83#ibcon#about to read 4, iclass 32, count 0 2006.202.01:19:16.83#ibcon#read 4, iclass 32, count 0 2006.202.01:19:16.83#ibcon#about to read 5, iclass 32, count 0 2006.202.01:19:16.83#ibcon#read 5, iclass 32, count 0 2006.202.01:19:16.83#ibcon#about to read 6, iclass 32, count 0 2006.202.01:19:16.83#ibcon#read 6, iclass 32, count 0 2006.202.01:19:16.83#ibcon#end of sib2, iclass 32, count 0 2006.202.01:19:16.83#ibcon#*after write, iclass 32, count 0 2006.202.01:19:16.83#ibcon#*before return 0, iclass 32, count 0 2006.202.01:19:16.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:16.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:19:16.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.01:19:16.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.01:19:16.83$vck44/vabw=wide 2006.202.01:19:16.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.01:19:16.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.01:19:16.83#ibcon#ireg 8 cls_cnt 0 2006.202.01:19:16.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:16.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:16.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:16.83#ibcon#enter wrdev, iclass 34, count 0 2006.202.01:19:16.83#ibcon#first serial, iclass 34, count 0 2006.202.01:19:16.83#ibcon#enter sib2, iclass 34, count 0 2006.202.01:19:16.83#ibcon#flushed, iclass 34, count 0 2006.202.01:19:16.83#ibcon#about to write, iclass 34, count 0 2006.202.01:19:16.83#ibcon#wrote, iclass 34, count 0 2006.202.01:19:16.83#ibcon#about to read 3, iclass 34, count 0 2006.202.01:19:16.85#ibcon#read 3, iclass 34, count 0 2006.202.01:19:16.85#ibcon#about to read 4, iclass 34, count 0 2006.202.01:19:16.85#ibcon#read 4, iclass 34, count 0 2006.202.01:19:16.85#ibcon#about to read 5, iclass 34, count 0 2006.202.01:19:16.85#ibcon#read 5, iclass 34, count 0 2006.202.01:19:16.85#ibcon#about to read 6, iclass 34, count 0 2006.202.01:19:16.85#ibcon#read 6, iclass 34, count 0 2006.202.01:19:16.85#ibcon#end of sib2, iclass 34, count 0 2006.202.01:19:16.85#ibcon#*mode == 0, iclass 34, count 0 2006.202.01:19:16.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.01:19:16.85#ibcon#[25=BW32\r\n] 2006.202.01:19:16.85#ibcon#*before write, iclass 34, count 0 2006.202.01:19:16.85#ibcon#enter sib2, iclass 34, count 0 2006.202.01:19:16.85#ibcon#flushed, iclass 34, count 0 2006.202.01:19:16.85#ibcon#about to write, iclass 34, count 0 2006.202.01:19:16.85#ibcon#wrote, iclass 34, count 0 2006.202.01:19:16.85#ibcon#about to read 3, iclass 34, count 0 2006.202.01:19:16.88#ibcon#read 3, iclass 34, count 0 2006.202.01:19:16.88#ibcon#about to read 4, iclass 34, count 0 2006.202.01:19:16.88#ibcon#read 4, iclass 34, count 0 2006.202.01:19:16.88#ibcon#about to read 5, iclass 34, count 0 2006.202.01:19:16.88#ibcon#read 5, iclass 34, count 0 2006.202.01:19:16.88#ibcon#about to read 6, iclass 34, count 0 2006.202.01:19:16.88#ibcon#read 6, iclass 34, count 0 2006.202.01:19:16.88#ibcon#end of sib2, iclass 34, count 0 2006.202.01:19:16.88#ibcon#*after write, iclass 34, count 0 2006.202.01:19:16.88#ibcon#*before return 0, iclass 34, count 0 2006.202.01:19:16.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:16.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:19:16.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.01:19:16.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.01:19:16.88$vck44/vbbw=wide 2006.202.01:19:16.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.202.01:19:16.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.202.01:19:16.88#ibcon#ireg 8 cls_cnt 0 2006.202.01:19:16.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:19:16.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:19:16.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:19:16.95#ibcon#enter wrdev, iclass 36, count 0 2006.202.01:19:16.95#ibcon#first serial, iclass 36, count 0 2006.202.01:19:16.95#ibcon#enter sib2, iclass 36, count 0 2006.202.01:19:16.95#ibcon#flushed, iclass 36, count 0 2006.202.01:19:16.95#ibcon#about to write, iclass 36, count 0 2006.202.01:19:16.95#ibcon#wrote, iclass 36, count 0 2006.202.01:19:16.95#ibcon#about to read 3, iclass 36, count 0 2006.202.01:19:16.97#ibcon#read 3, iclass 36, count 0 2006.202.01:19:16.97#ibcon#about to read 4, iclass 36, count 0 2006.202.01:19:16.97#ibcon#read 4, iclass 36, count 0 2006.202.01:19:16.97#ibcon#about to read 5, iclass 36, count 0 2006.202.01:19:16.97#ibcon#read 5, iclass 36, count 0 2006.202.01:19:16.97#ibcon#about to read 6, iclass 36, count 0 2006.202.01:19:16.97#ibcon#read 6, iclass 36, count 0 2006.202.01:19:16.97#ibcon#end of sib2, iclass 36, count 0 2006.202.01:19:16.97#ibcon#*mode == 0, iclass 36, count 0 2006.202.01:19:16.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.01:19:16.97#ibcon#[27=BW32\r\n] 2006.202.01:19:16.97#ibcon#*before write, iclass 36, count 0 2006.202.01:19:16.97#ibcon#enter sib2, iclass 36, count 0 2006.202.01:19:16.97#ibcon#flushed, iclass 36, count 0 2006.202.01:19:16.97#ibcon#about to write, iclass 36, count 0 2006.202.01:19:16.97#ibcon#wrote, iclass 36, count 0 2006.202.01:19:16.97#ibcon#about to read 3, iclass 36, count 0 2006.202.01:19:17.00#ibcon#read 3, iclass 36, count 0 2006.202.01:19:17.03#ibcon#about to read 4, iclass 36, count 0 2006.202.01:19:17.03#ibcon#read 4, iclass 36, count 0 2006.202.01:19:17.03#ibcon#about to read 5, iclass 36, count 0 2006.202.01:19:17.03#ibcon#read 5, iclass 36, count 0 2006.202.01:19:17.03#ibcon#about to read 6, iclass 36, count 0 2006.202.01:19:17.03#ibcon#read 6, iclass 36, count 0 2006.202.01:19:17.03#ibcon#end of sib2, iclass 36, count 0 2006.202.01:19:17.03#ibcon#*after write, iclass 36, count 0 2006.202.01:19:17.03#ibcon#*before return 0, iclass 36, count 0 2006.202.01:19:17.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:19:17.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:19:17.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.01:19:17.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.01:19:17.04$setupk4/ifdk4 2006.202.01:19:17.04$ifdk4/lo= 2006.202.01:19:17.04$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.01:19:17.04$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.01:19:17.04$ifdk4/patch= 2006.202.01:19:17.04$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.01:19:17.04$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.01:19:17.04$setupk4/!*+20s 2006.202.01:19:19.57#abcon#<5=/04 2.6 4.8 20.451001000.8\r\n> 2006.202.01:19:19.59#abcon#{5=INTERFACE CLEAR} 2006.202.01:19:19.65#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:19:21.14#trakl#Source acquired 2006.202.01:19:23.14#flagr#flagr/antenna,acquired 2006.202.01:19:29.74#abcon#<5=/04 2.6 4.8 20.451001000.8\r\n> 2006.202.01:19:29.76#abcon#{5=INTERFACE CLEAR} 2006.202.01:19:29.82#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:19:31.50$setupk4/"tpicd 2006.202.01:19:31.50$setupk4/echo=off 2006.202.01:19:31.50$setupk4/xlog=off 2006.202.01:19:31.50:!2006.202.01:19:38 2006.202.01:19:38.00:preob 2006.202.01:19:39.14/onsource/TRACKING 2006.202.01:19:39.14:!2006.202.01:19:48 2006.202.01:19:48.00:"tape 2006.202.01:19:48.00:"st=record 2006.202.01:19:48.00:data_valid=on 2006.202.01:19:48.00:midob 2006.202.01:19:48.14/onsource/TRACKING 2006.202.01:19:48.14/wx/20.46,1000.8,100 2006.202.01:19:48.22/cable/+6.4826E-03 2006.202.01:19:49.31/va/01,08,usb,yes,47,51 2006.202.01:19:49.31/va/02,07,usb,yes,51,52 2006.202.01:19:49.31/va/03,08,usb,yes,46,48 2006.202.01:19:49.31/va/04,07,usb,yes,53,55 2006.202.01:19:49.31/va/05,04,usb,yes,47,48 2006.202.01:19:49.31/va/06,05,usb,yes,47,47 2006.202.01:19:49.31/va/07,05,usb,yes,46,48 2006.202.01:19:49.31/va/08,04,usb,yes,46,54 2006.202.01:19:49.54/valo/01,524.99,yes,locked 2006.202.01:19:49.54/valo/02,534.99,yes,locked 2006.202.01:19:49.54/valo/03,564.99,yes,locked 2006.202.01:19:49.54/valo/04,624.99,yes,locked 2006.202.01:19:49.54/valo/05,734.99,yes,locked 2006.202.01:19:49.54/valo/06,814.99,yes,locked 2006.202.01:19:49.54/valo/07,864.99,yes,locked 2006.202.01:19:49.54/valo/08,884.99,yes,locked 2006.202.01:19:50.63/vb/01,04,usb,yes,39,36 2006.202.01:19:50.63/vb/02,05,usb,yes,36,36 2006.202.01:19:50.63/vb/03,04,usb,yes,38,42 2006.202.01:19:50.63/vb/04,05,usb,yes,38,37 2006.202.01:19:50.63/vb/05,04,usb,yes,34,37 2006.202.01:19:50.63/vb/06,04,usb,yes,39,35 2006.202.01:19:50.63/vb/07,04,usb,yes,39,39 2006.202.01:19:50.63/vb/08,04,usb,yes,36,40 2006.202.01:19:50.87/vblo/01,629.99,yes,locked 2006.202.01:19:50.87/vblo/02,634.99,yes,locked 2006.202.01:19:50.87/vblo/03,649.99,yes,locked 2006.202.01:19:50.87/vblo/04,679.99,yes,locked 2006.202.01:19:50.87/vblo/05,709.99,yes,locked 2006.202.01:19:50.87/vblo/06,719.99,yes,locked 2006.202.01:19:50.87/vblo/07,734.99,yes,locked 2006.202.01:19:50.87/vblo/08,744.99,yes,locked 2006.202.01:19:51.02/vabw/8 2006.202.01:19:51.17/vbbw/8 2006.202.01:19:51.26/xfe/off,on,14.7 2006.202.01:19:51.63/ifatt/23,28,28,28 2006.202.01:19:52.07/fmout-gps/S +4.51E-07 2006.202.01:19:52.11:!2006.202.01:22:58 2006.202.01:22:58.00:data_valid=off 2006.202.01:22:58.00:"et 2006.202.01:22:58.00:!+3s 2006.202.01:23:01.02:"tape 2006.202.01:23:01.02:postob 2006.202.01:23:01.14/cable/+6.4825E-03 2006.202.01:23:01.14/wx/20.53,1000.7,100 2006.202.01:23:01.20/fmout-gps/S +4.50E-07 2006.202.01:23:01.20:scan_name=202-0124,jd0607,60 2006.202.01:23:01.20:source=0727-115,073019.11,-114112.6,2000.0,ccw 2006.202.01:23:03.13#flagr#flagr/antenna,new-source 2006.202.01:23:03.13:checkk5 2006.202.01:23:03.56/chk_autoobs//k5ts1/ autoobs is running! 2006.202.01:23:03.96/chk_autoobs//k5ts2/ autoobs is running! 2006.202.01:23:04.37/chk_autoobs//k5ts3/ autoobs is running! 2006.202.01:23:04.76/chk_autoobs//k5ts4/ autoobs is running! 2006.202.01:23:05.16/chk_obsdata//k5ts1/T2020119??a.dat file size is correct (nominal:760MB, actual:756MB). 2006.202.01:23:05.56/chk_obsdata//k5ts2/T2020119??b.dat file size is correct (nominal:760MB, actual:756MB). 2006.202.01:23:05.95/chk_obsdata//k5ts3/T2020119??c.dat file size is correct (nominal:760MB, actual:756MB). 2006.202.01:23:06.36/chk_obsdata//k5ts4/T2020119??d.dat file size is correct (nominal:760MB, actual:756MB). 2006.202.01:23:07.08/k5log//k5ts1_log_newline 2006.202.01:23:07.79/k5log//k5ts2_log_newline 2006.202.01:23:08.50/k5log//k5ts3_log_newline 2006.202.01:23:09.21/k5log//k5ts4_log_newline 2006.202.01:23:09.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.01:23:09.23:setupk4=1 2006.202.01:23:09.23$setupk4/echo=on 2006.202.01:23:09.23$setupk4/pcalon 2006.202.01:23:09.23$pcalon/"no phase cal control is implemented here 2006.202.01:23:09.23$setupk4/"tpicd=stop 2006.202.01:23:09.23$setupk4/"rec=synch_on 2006.202.01:23:09.23$setupk4/"rec_mode=128 2006.202.01:23:09.23$setupk4/!* 2006.202.01:23:09.23$setupk4/recpk4 2006.202.01:23:09.23$recpk4/recpatch= 2006.202.01:23:09.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.01:23:09.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.01:23:09.24$setupk4/vck44 2006.202.01:23:09.24$vck44/valo=1,524.99 2006.202.01:23:09.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.202.01:23:09.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.202.01:23:09.24#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:09.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:09.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:09.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:09.24#ibcon#enter wrdev, iclass 25, count 0 2006.202.01:23:09.24#ibcon#first serial, iclass 25, count 0 2006.202.01:23:09.24#ibcon#enter sib2, iclass 25, count 0 2006.202.01:23:09.24#ibcon#flushed, iclass 25, count 0 2006.202.01:23:09.24#ibcon#about to write, iclass 25, count 0 2006.202.01:23:09.24#ibcon#wrote, iclass 25, count 0 2006.202.01:23:09.24#ibcon#about to read 3, iclass 25, count 0 2006.202.01:23:09.26#ibcon#read 3, iclass 25, count 0 2006.202.01:23:09.26#ibcon#about to read 4, iclass 25, count 0 2006.202.01:23:09.26#ibcon#read 4, iclass 25, count 0 2006.202.01:23:09.26#ibcon#about to read 5, iclass 25, count 0 2006.202.01:23:09.26#ibcon#read 5, iclass 25, count 0 2006.202.01:23:09.26#ibcon#about to read 6, iclass 25, count 0 2006.202.01:23:09.26#ibcon#read 6, iclass 25, count 0 2006.202.01:23:09.26#ibcon#end of sib2, iclass 25, count 0 2006.202.01:23:09.26#ibcon#*mode == 0, iclass 25, count 0 2006.202.01:23:09.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.01:23:09.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.01:23:09.26#ibcon#*before write, iclass 25, count 0 2006.202.01:23:09.26#ibcon#enter sib2, iclass 25, count 0 2006.202.01:23:09.26#ibcon#flushed, iclass 25, count 0 2006.202.01:23:09.26#ibcon#about to write, iclass 25, count 0 2006.202.01:23:09.26#ibcon#wrote, iclass 25, count 0 2006.202.01:23:09.26#ibcon#about to read 3, iclass 25, count 0 2006.202.01:23:09.31#ibcon#read 3, iclass 25, count 0 2006.202.01:23:09.31#ibcon#about to read 4, iclass 25, count 0 2006.202.01:23:09.31#ibcon#read 4, iclass 25, count 0 2006.202.01:23:09.31#ibcon#about to read 5, iclass 25, count 0 2006.202.01:23:09.31#ibcon#read 5, iclass 25, count 0 2006.202.01:23:09.31#ibcon#about to read 6, iclass 25, count 0 2006.202.01:23:09.31#ibcon#read 6, iclass 25, count 0 2006.202.01:23:09.31#ibcon#end of sib2, iclass 25, count 0 2006.202.01:23:09.31#ibcon#*after write, iclass 25, count 0 2006.202.01:23:09.31#ibcon#*before return 0, iclass 25, count 0 2006.202.01:23:09.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:09.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:09.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.01:23:09.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.01:23:09.31$vck44/va=1,8 2006.202.01:23:09.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.202.01:23:09.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.202.01:23:09.31#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:09.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:09.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:09.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:09.31#ibcon#enter wrdev, iclass 27, count 2 2006.202.01:23:09.31#ibcon#first serial, iclass 27, count 2 2006.202.01:23:09.31#ibcon#enter sib2, iclass 27, count 2 2006.202.01:23:09.31#ibcon#flushed, iclass 27, count 2 2006.202.01:23:09.31#ibcon#about to write, iclass 27, count 2 2006.202.01:23:09.31#ibcon#wrote, iclass 27, count 2 2006.202.01:23:09.31#ibcon#about to read 3, iclass 27, count 2 2006.202.01:23:09.33#ibcon#read 3, iclass 27, count 2 2006.202.01:23:09.33#ibcon#about to read 4, iclass 27, count 2 2006.202.01:23:09.33#ibcon#read 4, iclass 27, count 2 2006.202.01:23:09.33#ibcon#about to read 5, iclass 27, count 2 2006.202.01:23:09.33#ibcon#read 5, iclass 27, count 2 2006.202.01:23:09.33#ibcon#about to read 6, iclass 27, count 2 2006.202.01:23:09.33#ibcon#read 6, iclass 27, count 2 2006.202.01:23:09.33#ibcon#end of sib2, iclass 27, count 2 2006.202.01:23:09.33#ibcon#*mode == 0, iclass 27, count 2 2006.202.01:23:09.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.202.01:23:09.33#ibcon#[25=AT01-08\r\n] 2006.202.01:23:09.33#ibcon#*before write, iclass 27, count 2 2006.202.01:23:09.33#ibcon#enter sib2, iclass 27, count 2 2006.202.01:23:09.33#ibcon#flushed, iclass 27, count 2 2006.202.01:23:09.33#ibcon#about to write, iclass 27, count 2 2006.202.01:23:09.33#ibcon#wrote, iclass 27, count 2 2006.202.01:23:09.33#ibcon#about to read 3, iclass 27, count 2 2006.202.01:23:09.36#ibcon#read 3, iclass 27, count 2 2006.202.01:23:09.36#ibcon#about to read 4, iclass 27, count 2 2006.202.01:23:09.36#ibcon#read 4, iclass 27, count 2 2006.202.01:23:09.36#ibcon#about to read 5, iclass 27, count 2 2006.202.01:23:09.36#ibcon#read 5, iclass 27, count 2 2006.202.01:23:09.36#ibcon#about to read 6, iclass 27, count 2 2006.202.01:23:09.36#ibcon#read 6, iclass 27, count 2 2006.202.01:23:09.36#ibcon#end of sib2, iclass 27, count 2 2006.202.01:23:09.36#ibcon#*after write, iclass 27, count 2 2006.202.01:23:09.36#ibcon#*before return 0, iclass 27, count 2 2006.202.01:23:09.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:09.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:09.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.202.01:23:09.36#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:09.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:09.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:09.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:09.48#ibcon#enter wrdev, iclass 27, count 0 2006.202.01:23:09.48#ibcon#first serial, iclass 27, count 0 2006.202.01:23:09.48#ibcon#enter sib2, iclass 27, count 0 2006.202.01:23:09.48#ibcon#flushed, iclass 27, count 0 2006.202.01:23:09.48#ibcon#about to write, iclass 27, count 0 2006.202.01:23:09.48#ibcon#wrote, iclass 27, count 0 2006.202.01:23:09.48#ibcon#about to read 3, iclass 27, count 0 2006.202.01:23:09.50#ibcon#read 3, iclass 27, count 0 2006.202.01:23:09.50#ibcon#about to read 4, iclass 27, count 0 2006.202.01:23:09.50#ibcon#read 4, iclass 27, count 0 2006.202.01:23:09.50#ibcon#about to read 5, iclass 27, count 0 2006.202.01:23:09.50#ibcon#read 5, iclass 27, count 0 2006.202.01:23:09.50#ibcon#about to read 6, iclass 27, count 0 2006.202.01:23:09.50#ibcon#read 6, iclass 27, count 0 2006.202.01:23:09.50#ibcon#end of sib2, iclass 27, count 0 2006.202.01:23:09.50#ibcon#*mode == 0, iclass 27, count 0 2006.202.01:23:09.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.01:23:09.50#ibcon#[25=USB\r\n] 2006.202.01:23:09.50#ibcon#*before write, iclass 27, count 0 2006.202.01:23:09.50#ibcon#enter sib2, iclass 27, count 0 2006.202.01:23:09.50#ibcon#flushed, iclass 27, count 0 2006.202.01:23:09.50#ibcon#about to write, iclass 27, count 0 2006.202.01:23:09.50#ibcon#wrote, iclass 27, count 0 2006.202.01:23:09.50#ibcon#about to read 3, iclass 27, count 0 2006.202.01:23:09.53#ibcon#read 3, iclass 27, count 0 2006.202.01:23:09.53#ibcon#about to read 4, iclass 27, count 0 2006.202.01:23:09.53#ibcon#read 4, iclass 27, count 0 2006.202.01:23:09.53#ibcon#about to read 5, iclass 27, count 0 2006.202.01:23:09.53#ibcon#read 5, iclass 27, count 0 2006.202.01:23:09.53#ibcon#about to read 6, iclass 27, count 0 2006.202.01:23:09.53#ibcon#read 6, iclass 27, count 0 2006.202.01:23:09.53#ibcon#end of sib2, iclass 27, count 0 2006.202.01:23:09.53#ibcon#*after write, iclass 27, count 0 2006.202.01:23:09.53#ibcon#*before return 0, iclass 27, count 0 2006.202.01:23:09.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:09.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:09.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.01:23:09.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.01:23:09.53$vck44/valo=2,534.99 2006.202.01:23:09.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.202.01:23:09.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.202.01:23:09.53#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:09.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:09.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:09.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:09.53#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:23:09.53#ibcon#first serial, iclass 29, count 0 2006.202.01:23:09.53#ibcon#enter sib2, iclass 29, count 0 2006.202.01:23:09.53#ibcon#flushed, iclass 29, count 0 2006.202.01:23:09.53#ibcon#about to write, iclass 29, count 0 2006.202.01:23:09.53#ibcon#wrote, iclass 29, count 0 2006.202.01:23:09.53#ibcon#about to read 3, iclass 29, count 0 2006.202.01:23:09.55#ibcon#read 3, iclass 29, count 0 2006.202.01:23:09.55#ibcon#about to read 4, iclass 29, count 0 2006.202.01:23:09.55#ibcon#read 4, iclass 29, count 0 2006.202.01:23:09.55#ibcon#about to read 5, iclass 29, count 0 2006.202.01:23:09.55#ibcon#read 5, iclass 29, count 0 2006.202.01:23:09.55#ibcon#about to read 6, iclass 29, count 0 2006.202.01:23:09.55#ibcon#read 6, iclass 29, count 0 2006.202.01:23:09.55#ibcon#end of sib2, iclass 29, count 0 2006.202.01:23:09.55#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:23:09.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:23:09.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.01:23:09.55#ibcon#*before write, iclass 29, count 0 2006.202.01:23:09.55#ibcon#enter sib2, iclass 29, count 0 2006.202.01:23:09.55#ibcon#flushed, iclass 29, count 0 2006.202.01:23:09.55#ibcon#about to write, iclass 29, count 0 2006.202.01:23:09.55#ibcon#wrote, iclass 29, count 0 2006.202.01:23:09.55#ibcon#about to read 3, iclass 29, count 0 2006.202.01:23:09.59#ibcon#read 3, iclass 29, count 0 2006.202.01:23:09.59#ibcon#about to read 4, iclass 29, count 0 2006.202.01:23:09.59#ibcon#read 4, iclass 29, count 0 2006.202.01:23:09.59#ibcon#about to read 5, iclass 29, count 0 2006.202.01:23:09.59#ibcon#read 5, iclass 29, count 0 2006.202.01:23:09.59#ibcon#about to read 6, iclass 29, count 0 2006.202.01:23:09.59#ibcon#read 6, iclass 29, count 0 2006.202.01:23:09.59#ibcon#end of sib2, iclass 29, count 0 2006.202.01:23:09.59#ibcon#*after write, iclass 29, count 0 2006.202.01:23:09.59#ibcon#*before return 0, iclass 29, count 0 2006.202.01:23:09.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:09.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:09.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:23:09.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:23:09.59$vck44/va=2,7 2006.202.01:23:09.59#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.202.01:23:09.59#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.202.01:23:09.59#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:09.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:09.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:09.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:09.65#ibcon#enter wrdev, iclass 31, count 2 2006.202.01:23:09.65#ibcon#first serial, iclass 31, count 2 2006.202.01:23:09.65#ibcon#enter sib2, iclass 31, count 2 2006.202.01:23:09.65#ibcon#flushed, iclass 31, count 2 2006.202.01:23:09.65#ibcon#about to write, iclass 31, count 2 2006.202.01:23:09.65#ibcon#wrote, iclass 31, count 2 2006.202.01:23:09.65#ibcon#about to read 3, iclass 31, count 2 2006.202.01:23:09.67#ibcon#read 3, iclass 31, count 2 2006.202.01:23:09.67#ibcon#about to read 4, iclass 31, count 2 2006.202.01:23:09.67#ibcon#read 4, iclass 31, count 2 2006.202.01:23:09.67#ibcon#about to read 5, iclass 31, count 2 2006.202.01:23:09.67#ibcon#read 5, iclass 31, count 2 2006.202.01:23:09.67#ibcon#about to read 6, iclass 31, count 2 2006.202.01:23:09.67#ibcon#read 6, iclass 31, count 2 2006.202.01:23:09.67#ibcon#end of sib2, iclass 31, count 2 2006.202.01:23:09.67#ibcon#*mode == 0, iclass 31, count 2 2006.202.01:23:09.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.202.01:23:09.67#ibcon#[25=AT02-07\r\n] 2006.202.01:23:09.67#ibcon#*before write, iclass 31, count 2 2006.202.01:23:09.67#ibcon#enter sib2, iclass 31, count 2 2006.202.01:23:09.67#ibcon#flushed, iclass 31, count 2 2006.202.01:23:09.67#ibcon#about to write, iclass 31, count 2 2006.202.01:23:09.67#ibcon#wrote, iclass 31, count 2 2006.202.01:23:09.67#ibcon#about to read 3, iclass 31, count 2 2006.202.01:23:09.70#ibcon#read 3, iclass 31, count 2 2006.202.01:23:09.70#ibcon#about to read 4, iclass 31, count 2 2006.202.01:23:09.70#ibcon#read 4, iclass 31, count 2 2006.202.01:23:09.70#ibcon#about to read 5, iclass 31, count 2 2006.202.01:23:09.70#ibcon#read 5, iclass 31, count 2 2006.202.01:23:09.70#ibcon#about to read 6, iclass 31, count 2 2006.202.01:23:09.70#ibcon#read 6, iclass 31, count 2 2006.202.01:23:09.70#ibcon#end of sib2, iclass 31, count 2 2006.202.01:23:09.70#ibcon#*after write, iclass 31, count 2 2006.202.01:23:09.70#ibcon#*before return 0, iclass 31, count 2 2006.202.01:23:09.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:09.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:09.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.202.01:23:09.70#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:09.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:09.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:09.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:09.82#ibcon#enter wrdev, iclass 31, count 0 2006.202.01:23:09.82#ibcon#first serial, iclass 31, count 0 2006.202.01:23:09.82#ibcon#enter sib2, iclass 31, count 0 2006.202.01:23:09.82#ibcon#flushed, iclass 31, count 0 2006.202.01:23:09.82#ibcon#about to write, iclass 31, count 0 2006.202.01:23:09.82#ibcon#wrote, iclass 31, count 0 2006.202.01:23:09.82#ibcon#about to read 3, iclass 31, count 0 2006.202.01:23:09.84#ibcon#read 3, iclass 31, count 0 2006.202.01:23:09.84#ibcon#about to read 4, iclass 31, count 0 2006.202.01:23:09.84#ibcon#read 4, iclass 31, count 0 2006.202.01:23:09.84#ibcon#about to read 5, iclass 31, count 0 2006.202.01:23:09.84#ibcon#read 5, iclass 31, count 0 2006.202.01:23:09.84#ibcon#about to read 6, iclass 31, count 0 2006.202.01:23:09.84#ibcon#read 6, iclass 31, count 0 2006.202.01:23:09.84#ibcon#end of sib2, iclass 31, count 0 2006.202.01:23:09.84#ibcon#*mode == 0, iclass 31, count 0 2006.202.01:23:09.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.01:23:09.84#ibcon#[25=USB\r\n] 2006.202.01:23:09.84#ibcon#*before write, iclass 31, count 0 2006.202.01:23:09.84#ibcon#enter sib2, iclass 31, count 0 2006.202.01:23:09.84#ibcon#flushed, iclass 31, count 0 2006.202.01:23:09.84#ibcon#about to write, iclass 31, count 0 2006.202.01:23:09.84#ibcon#wrote, iclass 31, count 0 2006.202.01:23:09.84#ibcon#about to read 3, iclass 31, count 0 2006.202.01:23:09.87#ibcon#read 3, iclass 31, count 0 2006.202.01:23:09.87#ibcon#about to read 4, iclass 31, count 0 2006.202.01:23:09.87#ibcon#read 4, iclass 31, count 0 2006.202.01:23:09.87#ibcon#about to read 5, iclass 31, count 0 2006.202.01:23:09.87#ibcon#read 5, iclass 31, count 0 2006.202.01:23:09.87#ibcon#about to read 6, iclass 31, count 0 2006.202.01:23:09.87#ibcon#read 6, iclass 31, count 0 2006.202.01:23:09.87#ibcon#end of sib2, iclass 31, count 0 2006.202.01:23:09.87#ibcon#*after write, iclass 31, count 0 2006.202.01:23:09.87#ibcon#*before return 0, iclass 31, count 0 2006.202.01:23:09.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:09.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:09.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.01:23:09.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.01:23:09.87$vck44/valo=3,564.99 2006.202.01:23:09.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.01:23:09.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.01:23:09.87#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:09.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:09.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:09.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:09.87#ibcon#enter wrdev, iclass 33, count 0 2006.202.01:23:09.87#ibcon#first serial, iclass 33, count 0 2006.202.01:23:09.87#ibcon#enter sib2, iclass 33, count 0 2006.202.01:23:09.87#ibcon#flushed, iclass 33, count 0 2006.202.01:23:09.87#ibcon#about to write, iclass 33, count 0 2006.202.01:23:09.87#ibcon#wrote, iclass 33, count 0 2006.202.01:23:09.87#ibcon#about to read 3, iclass 33, count 0 2006.202.01:23:09.89#ibcon#read 3, iclass 33, count 0 2006.202.01:23:09.89#ibcon#about to read 4, iclass 33, count 0 2006.202.01:23:09.89#ibcon#read 4, iclass 33, count 0 2006.202.01:23:09.89#ibcon#about to read 5, iclass 33, count 0 2006.202.01:23:09.89#ibcon#read 5, iclass 33, count 0 2006.202.01:23:09.89#ibcon#about to read 6, iclass 33, count 0 2006.202.01:23:09.89#ibcon#read 6, iclass 33, count 0 2006.202.01:23:09.89#ibcon#end of sib2, iclass 33, count 0 2006.202.01:23:09.89#ibcon#*mode == 0, iclass 33, count 0 2006.202.01:23:09.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.01:23:09.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.01:23:09.89#ibcon#*before write, iclass 33, count 0 2006.202.01:23:09.89#ibcon#enter sib2, iclass 33, count 0 2006.202.01:23:09.89#ibcon#flushed, iclass 33, count 0 2006.202.01:23:09.89#ibcon#about to write, iclass 33, count 0 2006.202.01:23:09.89#ibcon#wrote, iclass 33, count 0 2006.202.01:23:09.89#ibcon#about to read 3, iclass 33, count 0 2006.202.01:23:09.93#ibcon#read 3, iclass 33, count 0 2006.202.01:23:09.93#ibcon#about to read 4, iclass 33, count 0 2006.202.01:23:09.93#ibcon#read 4, iclass 33, count 0 2006.202.01:23:09.93#ibcon#about to read 5, iclass 33, count 0 2006.202.01:23:09.93#ibcon#read 5, iclass 33, count 0 2006.202.01:23:09.93#ibcon#about to read 6, iclass 33, count 0 2006.202.01:23:09.93#ibcon#read 6, iclass 33, count 0 2006.202.01:23:09.93#ibcon#end of sib2, iclass 33, count 0 2006.202.01:23:09.93#ibcon#*after write, iclass 33, count 0 2006.202.01:23:09.93#ibcon#*before return 0, iclass 33, count 0 2006.202.01:23:09.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:09.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:09.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.01:23:09.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.01:23:09.93$vck44/va=3,8 2006.202.01:23:09.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.202.01:23:09.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.202.01:23:09.93#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:09.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:09.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:09.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:09.99#ibcon#enter wrdev, iclass 35, count 2 2006.202.01:23:09.99#ibcon#first serial, iclass 35, count 2 2006.202.01:23:09.99#ibcon#enter sib2, iclass 35, count 2 2006.202.01:23:09.99#ibcon#flushed, iclass 35, count 2 2006.202.01:23:09.99#ibcon#about to write, iclass 35, count 2 2006.202.01:23:09.99#ibcon#wrote, iclass 35, count 2 2006.202.01:23:09.99#ibcon#about to read 3, iclass 35, count 2 2006.202.01:23:10.01#ibcon#read 3, iclass 35, count 2 2006.202.01:23:10.01#ibcon#about to read 4, iclass 35, count 2 2006.202.01:23:10.01#ibcon#read 4, iclass 35, count 2 2006.202.01:23:10.01#ibcon#about to read 5, iclass 35, count 2 2006.202.01:23:10.01#ibcon#read 5, iclass 35, count 2 2006.202.01:23:10.01#ibcon#about to read 6, iclass 35, count 2 2006.202.01:23:10.01#ibcon#read 6, iclass 35, count 2 2006.202.01:23:10.01#ibcon#end of sib2, iclass 35, count 2 2006.202.01:23:10.01#ibcon#*mode == 0, iclass 35, count 2 2006.202.01:23:10.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.202.01:23:10.01#ibcon#[25=AT03-08\r\n] 2006.202.01:23:10.01#ibcon#*before write, iclass 35, count 2 2006.202.01:23:10.01#ibcon#enter sib2, iclass 35, count 2 2006.202.01:23:10.01#ibcon#flushed, iclass 35, count 2 2006.202.01:23:10.01#ibcon#about to write, iclass 35, count 2 2006.202.01:23:10.01#ibcon#wrote, iclass 35, count 2 2006.202.01:23:10.01#ibcon#about to read 3, iclass 35, count 2 2006.202.01:23:10.04#ibcon#read 3, iclass 35, count 2 2006.202.01:23:10.04#ibcon#about to read 4, iclass 35, count 2 2006.202.01:23:10.04#ibcon#read 4, iclass 35, count 2 2006.202.01:23:10.04#ibcon#about to read 5, iclass 35, count 2 2006.202.01:23:10.04#ibcon#read 5, iclass 35, count 2 2006.202.01:23:10.04#ibcon#about to read 6, iclass 35, count 2 2006.202.01:23:10.04#ibcon#read 6, iclass 35, count 2 2006.202.01:23:10.04#ibcon#end of sib2, iclass 35, count 2 2006.202.01:23:10.04#ibcon#*after write, iclass 35, count 2 2006.202.01:23:10.04#ibcon#*before return 0, iclass 35, count 2 2006.202.01:23:10.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:10.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:10.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.202.01:23:10.04#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:10.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:10.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:10.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:10.16#ibcon#enter wrdev, iclass 35, count 0 2006.202.01:23:10.16#ibcon#first serial, iclass 35, count 0 2006.202.01:23:10.16#ibcon#enter sib2, iclass 35, count 0 2006.202.01:23:10.16#ibcon#flushed, iclass 35, count 0 2006.202.01:23:10.16#ibcon#about to write, iclass 35, count 0 2006.202.01:23:10.16#ibcon#wrote, iclass 35, count 0 2006.202.01:23:10.16#ibcon#about to read 3, iclass 35, count 0 2006.202.01:23:10.18#ibcon#read 3, iclass 35, count 0 2006.202.01:23:10.18#ibcon#about to read 4, iclass 35, count 0 2006.202.01:23:10.18#ibcon#read 4, iclass 35, count 0 2006.202.01:23:10.18#ibcon#about to read 5, iclass 35, count 0 2006.202.01:23:10.18#ibcon#read 5, iclass 35, count 0 2006.202.01:23:10.18#ibcon#about to read 6, iclass 35, count 0 2006.202.01:23:10.18#ibcon#read 6, iclass 35, count 0 2006.202.01:23:10.18#ibcon#end of sib2, iclass 35, count 0 2006.202.01:23:10.18#ibcon#*mode == 0, iclass 35, count 0 2006.202.01:23:10.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.01:23:10.18#ibcon#[25=USB\r\n] 2006.202.01:23:10.18#ibcon#*before write, iclass 35, count 0 2006.202.01:23:10.18#ibcon#enter sib2, iclass 35, count 0 2006.202.01:23:10.18#ibcon#flushed, iclass 35, count 0 2006.202.01:23:10.18#ibcon#about to write, iclass 35, count 0 2006.202.01:23:10.18#ibcon#wrote, iclass 35, count 0 2006.202.01:23:10.18#ibcon#about to read 3, iclass 35, count 0 2006.202.01:23:10.21#ibcon#read 3, iclass 35, count 0 2006.202.01:23:10.21#ibcon#about to read 4, iclass 35, count 0 2006.202.01:23:10.21#ibcon#read 4, iclass 35, count 0 2006.202.01:23:10.21#ibcon#about to read 5, iclass 35, count 0 2006.202.01:23:10.21#ibcon#read 5, iclass 35, count 0 2006.202.01:23:10.21#ibcon#about to read 6, iclass 35, count 0 2006.202.01:23:10.21#ibcon#read 6, iclass 35, count 0 2006.202.01:23:10.21#ibcon#end of sib2, iclass 35, count 0 2006.202.01:23:10.21#ibcon#*after write, iclass 35, count 0 2006.202.01:23:10.21#ibcon#*before return 0, iclass 35, count 0 2006.202.01:23:10.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:10.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:10.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.01:23:10.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.01:23:10.21$vck44/valo=4,624.99 2006.202.01:23:10.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.202.01:23:10.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.202.01:23:10.21#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:10.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:10.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:10.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:10.21#ibcon#enter wrdev, iclass 37, count 0 2006.202.01:23:10.21#ibcon#first serial, iclass 37, count 0 2006.202.01:23:10.21#ibcon#enter sib2, iclass 37, count 0 2006.202.01:23:10.21#ibcon#flushed, iclass 37, count 0 2006.202.01:23:10.21#ibcon#about to write, iclass 37, count 0 2006.202.01:23:10.21#ibcon#wrote, iclass 37, count 0 2006.202.01:23:10.21#ibcon#about to read 3, iclass 37, count 0 2006.202.01:23:10.23#ibcon#read 3, iclass 37, count 0 2006.202.01:23:10.23#ibcon#about to read 4, iclass 37, count 0 2006.202.01:23:10.23#ibcon#read 4, iclass 37, count 0 2006.202.01:23:10.23#ibcon#about to read 5, iclass 37, count 0 2006.202.01:23:10.23#ibcon#read 5, iclass 37, count 0 2006.202.01:23:10.23#ibcon#about to read 6, iclass 37, count 0 2006.202.01:23:10.23#ibcon#read 6, iclass 37, count 0 2006.202.01:23:10.23#ibcon#end of sib2, iclass 37, count 0 2006.202.01:23:10.23#ibcon#*mode == 0, iclass 37, count 0 2006.202.01:23:10.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.01:23:10.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.01:23:10.23#ibcon#*before write, iclass 37, count 0 2006.202.01:23:10.23#ibcon#enter sib2, iclass 37, count 0 2006.202.01:23:10.23#ibcon#flushed, iclass 37, count 0 2006.202.01:23:10.23#ibcon#about to write, iclass 37, count 0 2006.202.01:23:10.23#ibcon#wrote, iclass 37, count 0 2006.202.01:23:10.23#ibcon#about to read 3, iclass 37, count 0 2006.202.01:23:10.27#ibcon#read 3, iclass 37, count 0 2006.202.01:23:10.27#ibcon#about to read 4, iclass 37, count 0 2006.202.01:23:10.27#ibcon#read 4, iclass 37, count 0 2006.202.01:23:10.27#ibcon#about to read 5, iclass 37, count 0 2006.202.01:23:10.27#ibcon#read 5, iclass 37, count 0 2006.202.01:23:10.27#ibcon#about to read 6, iclass 37, count 0 2006.202.01:23:10.27#ibcon#read 6, iclass 37, count 0 2006.202.01:23:10.27#ibcon#end of sib2, iclass 37, count 0 2006.202.01:23:10.27#ibcon#*after write, iclass 37, count 0 2006.202.01:23:10.27#ibcon#*before return 0, iclass 37, count 0 2006.202.01:23:10.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:10.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:10.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.01:23:10.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.01:23:10.27$vck44/va=4,7 2006.202.01:23:10.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.202.01:23:10.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.202.01:23:10.27#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:10.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:23:10.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:23:10.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:23:10.33#ibcon#enter wrdev, iclass 39, count 2 2006.202.01:23:10.33#ibcon#first serial, iclass 39, count 2 2006.202.01:23:10.33#ibcon#enter sib2, iclass 39, count 2 2006.202.01:23:10.33#ibcon#flushed, iclass 39, count 2 2006.202.01:23:10.33#ibcon#about to write, iclass 39, count 2 2006.202.01:23:10.33#ibcon#wrote, iclass 39, count 2 2006.202.01:23:10.33#ibcon#about to read 3, iclass 39, count 2 2006.202.01:23:10.35#ibcon#read 3, iclass 39, count 2 2006.202.01:23:10.35#ibcon#about to read 4, iclass 39, count 2 2006.202.01:23:10.35#ibcon#read 4, iclass 39, count 2 2006.202.01:23:10.35#ibcon#about to read 5, iclass 39, count 2 2006.202.01:23:10.35#ibcon#read 5, iclass 39, count 2 2006.202.01:23:10.35#ibcon#about to read 6, iclass 39, count 2 2006.202.01:23:10.35#ibcon#read 6, iclass 39, count 2 2006.202.01:23:10.35#ibcon#end of sib2, iclass 39, count 2 2006.202.01:23:10.35#ibcon#*mode == 0, iclass 39, count 2 2006.202.01:23:10.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.202.01:23:10.35#ibcon#[25=AT04-07\r\n] 2006.202.01:23:10.35#ibcon#*before write, iclass 39, count 2 2006.202.01:23:10.35#ibcon#enter sib2, iclass 39, count 2 2006.202.01:23:10.35#ibcon#flushed, iclass 39, count 2 2006.202.01:23:10.35#ibcon#about to write, iclass 39, count 2 2006.202.01:23:10.35#ibcon#wrote, iclass 39, count 2 2006.202.01:23:10.35#ibcon#about to read 3, iclass 39, count 2 2006.202.01:23:10.38#ibcon#read 3, iclass 39, count 2 2006.202.01:23:10.51#ibcon#about to read 4, iclass 39, count 2 2006.202.01:23:10.51#ibcon#read 4, iclass 39, count 2 2006.202.01:23:10.51#ibcon#about to read 5, iclass 39, count 2 2006.202.01:23:10.51#ibcon#read 5, iclass 39, count 2 2006.202.01:23:10.51#ibcon#about to read 6, iclass 39, count 2 2006.202.01:23:10.51#ibcon#read 6, iclass 39, count 2 2006.202.01:23:10.51#ibcon#end of sib2, iclass 39, count 2 2006.202.01:23:10.51#ibcon#*after write, iclass 39, count 2 2006.202.01:23:10.51#ibcon#*before return 0, iclass 39, count 2 2006.202.01:23:10.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:23:10.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:23:10.51#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.202.01:23:10.51#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:10.51#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:23:10.64#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:23:10.64#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:23:10.64#ibcon#enter wrdev, iclass 39, count 0 2006.202.01:23:10.64#ibcon#first serial, iclass 39, count 0 2006.202.01:23:10.64#ibcon#enter sib2, iclass 39, count 0 2006.202.01:23:10.64#ibcon#flushed, iclass 39, count 0 2006.202.01:23:10.64#ibcon#about to write, iclass 39, count 0 2006.202.01:23:10.64#ibcon#wrote, iclass 39, count 0 2006.202.01:23:10.64#ibcon#about to read 3, iclass 39, count 0 2006.202.01:23:10.66#ibcon#read 3, iclass 39, count 0 2006.202.01:23:10.66#ibcon#about to read 4, iclass 39, count 0 2006.202.01:23:10.66#ibcon#read 4, iclass 39, count 0 2006.202.01:23:10.66#ibcon#about to read 5, iclass 39, count 0 2006.202.01:23:10.66#ibcon#read 5, iclass 39, count 0 2006.202.01:23:10.66#ibcon#about to read 6, iclass 39, count 0 2006.202.01:23:10.66#ibcon#read 6, iclass 39, count 0 2006.202.01:23:10.66#ibcon#end of sib2, iclass 39, count 0 2006.202.01:23:10.66#ibcon#*mode == 0, iclass 39, count 0 2006.202.01:23:10.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.01:23:10.66#ibcon#[25=USB\r\n] 2006.202.01:23:10.66#ibcon#*before write, iclass 39, count 0 2006.202.01:23:10.66#ibcon#enter sib2, iclass 39, count 0 2006.202.01:23:10.66#ibcon#flushed, iclass 39, count 0 2006.202.01:23:10.66#ibcon#about to write, iclass 39, count 0 2006.202.01:23:10.66#ibcon#wrote, iclass 39, count 0 2006.202.01:23:10.66#ibcon#about to read 3, iclass 39, count 0 2006.202.01:23:10.69#ibcon#read 3, iclass 39, count 0 2006.202.01:23:10.69#ibcon#about to read 4, iclass 39, count 0 2006.202.01:23:10.69#ibcon#read 4, iclass 39, count 0 2006.202.01:23:10.69#ibcon#about to read 5, iclass 39, count 0 2006.202.01:23:10.69#ibcon#read 5, iclass 39, count 0 2006.202.01:23:10.69#ibcon#about to read 6, iclass 39, count 0 2006.202.01:23:10.69#ibcon#read 6, iclass 39, count 0 2006.202.01:23:10.69#ibcon#end of sib2, iclass 39, count 0 2006.202.01:23:10.69#ibcon#*after write, iclass 39, count 0 2006.202.01:23:10.69#ibcon#*before return 0, iclass 39, count 0 2006.202.01:23:10.69#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:23:10.69#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:23:10.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.01:23:10.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.01:23:10.69$vck44/valo=5,734.99 2006.202.01:23:10.69#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.202.01:23:10.69#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.202.01:23:10.69#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:10.69#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:23:10.69#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:23:10.69#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:23:10.69#ibcon#enter wrdev, iclass 2, count 0 2006.202.01:23:10.69#ibcon#first serial, iclass 2, count 0 2006.202.01:23:10.69#ibcon#enter sib2, iclass 2, count 0 2006.202.01:23:10.69#ibcon#flushed, iclass 2, count 0 2006.202.01:23:10.69#ibcon#about to write, iclass 2, count 0 2006.202.01:23:10.69#ibcon#wrote, iclass 2, count 0 2006.202.01:23:10.69#ibcon#about to read 3, iclass 2, count 0 2006.202.01:23:10.71#ibcon#read 3, iclass 2, count 0 2006.202.01:23:10.71#ibcon#about to read 4, iclass 2, count 0 2006.202.01:23:10.71#ibcon#read 4, iclass 2, count 0 2006.202.01:23:10.71#ibcon#about to read 5, iclass 2, count 0 2006.202.01:23:10.71#ibcon#read 5, iclass 2, count 0 2006.202.01:23:10.71#ibcon#about to read 6, iclass 2, count 0 2006.202.01:23:10.71#ibcon#read 6, iclass 2, count 0 2006.202.01:23:10.71#ibcon#end of sib2, iclass 2, count 0 2006.202.01:23:10.71#ibcon#*mode == 0, iclass 2, count 0 2006.202.01:23:10.71#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.01:23:10.71#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.01:23:10.71#ibcon#*before write, iclass 2, count 0 2006.202.01:23:10.71#ibcon#enter sib2, iclass 2, count 0 2006.202.01:23:10.71#ibcon#flushed, iclass 2, count 0 2006.202.01:23:10.71#ibcon#about to write, iclass 2, count 0 2006.202.01:23:10.71#ibcon#wrote, iclass 2, count 0 2006.202.01:23:10.71#ibcon#about to read 3, iclass 2, count 0 2006.202.01:23:10.75#ibcon#read 3, iclass 2, count 0 2006.202.01:23:10.75#ibcon#about to read 4, iclass 2, count 0 2006.202.01:23:10.75#ibcon#read 4, iclass 2, count 0 2006.202.01:23:10.75#ibcon#about to read 5, iclass 2, count 0 2006.202.01:23:10.75#ibcon#read 5, iclass 2, count 0 2006.202.01:23:10.75#ibcon#about to read 6, iclass 2, count 0 2006.202.01:23:10.75#ibcon#read 6, iclass 2, count 0 2006.202.01:23:10.75#ibcon#end of sib2, iclass 2, count 0 2006.202.01:23:10.75#ibcon#*after write, iclass 2, count 0 2006.202.01:23:10.75#ibcon#*before return 0, iclass 2, count 0 2006.202.01:23:10.75#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:23:10.75#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:23:10.75#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.01:23:10.75#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.01:23:10.75$vck44/va=5,4 2006.202.01:23:10.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.202.01:23:10.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.202.01:23:10.75#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:10.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:23:10.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:23:10.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:23:10.81#ibcon#enter wrdev, iclass 5, count 2 2006.202.01:23:10.81#ibcon#first serial, iclass 5, count 2 2006.202.01:23:10.81#ibcon#enter sib2, iclass 5, count 2 2006.202.01:23:10.81#ibcon#flushed, iclass 5, count 2 2006.202.01:23:10.81#ibcon#about to write, iclass 5, count 2 2006.202.01:23:10.81#ibcon#wrote, iclass 5, count 2 2006.202.01:23:10.81#ibcon#about to read 3, iclass 5, count 2 2006.202.01:23:10.83#ibcon#read 3, iclass 5, count 2 2006.202.01:23:10.83#ibcon#about to read 4, iclass 5, count 2 2006.202.01:23:10.83#ibcon#read 4, iclass 5, count 2 2006.202.01:23:10.83#ibcon#about to read 5, iclass 5, count 2 2006.202.01:23:10.83#ibcon#read 5, iclass 5, count 2 2006.202.01:23:10.83#ibcon#about to read 6, iclass 5, count 2 2006.202.01:23:10.83#ibcon#read 6, iclass 5, count 2 2006.202.01:23:10.83#ibcon#end of sib2, iclass 5, count 2 2006.202.01:23:10.83#ibcon#*mode == 0, iclass 5, count 2 2006.202.01:23:10.83#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.202.01:23:10.83#ibcon#[25=AT05-04\r\n] 2006.202.01:23:10.83#ibcon#*before write, iclass 5, count 2 2006.202.01:23:10.83#ibcon#enter sib2, iclass 5, count 2 2006.202.01:23:10.83#ibcon#flushed, iclass 5, count 2 2006.202.01:23:10.83#ibcon#about to write, iclass 5, count 2 2006.202.01:23:10.83#ibcon#wrote, iclass 5, count 2 2006.202.01:23:10.83#ibcon#about to read 3, iclass 5, count 2 2006.202.01:23:10.86#ibcon#read 3, iclass 5, count 2 2006.202.01:23:10.86#ibcon#about to read 4, iclass 5, count 2 2006.202.01:23:10.86#ibcon#read 4, iclass 5, count 2 2006.202.01:23:10.86#ibcon#about to read 5, iclass 5, count 2 2006.202.01:23:10.86#ibcon#read 5, iclass 5, count 2 2006.202.01:23:10.86#ibcon#about to read 6, iclass 5, count 2 2006.202.01:23:10.86#ibcon#read 6, iclass 5, count 2 2006.202.01:23:10.86#ibcon#end of sib2, iclass 5, count 2 2006.202.01:23:10.86#ibcon#*after write, iclass 5, count 2 2006.202.01:23:10.86#ibcon#*before return 0, iclass 5, count 2 2006.202.01:23:10.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:23:10.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:23:10.86#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.202.01:23:10.86#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:10.86#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:23:10.98#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:23:10.98#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:23:10.98#ibcon#enter wrdev, iclass 5, count 0 2006.202.01:23:10.98#ibcon#first serial, iclass 5, count 0 2006.202.01:23:10.98#ibcon#enter sib2, iclass 5, count 0 2006.202.01:23:10.98#ibcon#flushed, iclass 5, count 0 2006.202.01:23:10.98#ibcon#about to write, iclass 5, count 0 2006.202.01:23:10.98#ibcon#wrote, iclass 5, count 0 2006.202.01:23:10.98#ibcon#about to read 3, iclass 5, count 0 2006.202.01:23:11.00#ibcon#read 3, iclass 5, count 0 2006.202.01:23:11.00#ibcon#about to read 4, iclass 5, count 0 2006.202.01:23:11.00#ibcon#read 4, iclass 5, count 0 2006.202.01:23:11.00#ibcon#about to read 5, iclass 5, count 0 2006.202.01:23:11.00#ibcon#read 5, iclass 5, count 0 2006.202.01:23:11.00#ibcon#about to read 6, iclass 5, count 0 2006.202.01:23:11.00#ibcon#read 6, iclass 5, count 0 2006.202.01:23:11.00#ibcon#end of sib2, iclass 5, count 0 2006.202.01:23:11.00#ibcon#*mode == 0, iclass 5, count 0 2006.202.01:23:11.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.01:23:11.00#ibcon#[25=USB\r\n] 2006.202.01:23:11.00#ibcon#*before write, iclass 5, count 0 2006.202.01:23:11.00#ibcon#enter sib2, iclass 5, count 0 2006.202.01:23:11.00#ibcon#flushed, iclass 5, count 0 2006.202.01:23:11.00#ibcon#about to write, iclass 5, count 0 2006.202.01:23:11.00#ibcon#wrote, iclass 5, count 0 2006.202.01:23:11.00#ibcon#about to read 3, iclass 5, count 0 2006.202.01:23:11.03#ibcon#read 3, iclass 5, count 0 2006.202.01:23:11.03#ibcon#about to read 4, iclass 5, count 0 2006.202.01:23:11.03#ibcon#read 4, iclass 5, count 0 2006.202.01:23:11.03#ibcon#about to read 5, iclass 5, count 0 2006.202.01:23:11.03#ibcon#read 5, iclass 5, count 0 2006.202.01:23:11.03#ibcon#about to read 6, iclass 5, count 0 2006.202.01:23:11.03#ibcon#read 6, iclass 5, count 0 2006.202.01:23:11.03#ibcon#end of sib2, iclass 5, count 0 2006.202.01:23:11.03#ibcon#*after write, iclass 5, count 0 2006.202.01:23:11.03#ibcon#*before return 0, iclass 5, count 0 2006.202.01:23:11.03#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:23:11.03#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:23:11.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.01:23:11.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.01:23:11.03$vck44/valo=6,814.99 2006.202.01:23:11.03#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.01:23:11.03#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.01:23:11.03#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:11.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:11.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:11.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:11.03#ibcon#enter wrdev, iclass 7, count 0 2006.202.01:23:11.03#ibcon#first serial, iclass 7, count 0 2006.202.01:23:11.03#ibcon#enter sib2, iclass 7, count 0 2006.202.01:23:11.03#ibcon#flushed, iclass 7, count 0 2006.202.01:23:11.03#ibcon#about to write, iclass 7, count 0 2006.202.01:23:11.03#ibcon#wrote, iclass 7, count 0 2006.202.01:23:11.03#ibcon#about to read 3, iclass 7, count 0 2006.202.01:23:11.05#ibcon#read 3, iclass 7, count 0 2006.202.01:23:11.05#ibcon#about to read 4, iclass 7, count 0 2006.202.01:23:11.05#ibcon#read 4, iclass 7, count 0 2006.202.01:23:11.05#ibcon#about to read 5, iclass 7, count 0 2006.202.01:23:11.05#ibcon#read 5, iclass 7, count 0 2006.202.01:23:11.05#ibcon#about to read 6, iclass 7, count 0 2006.202.01:23:11.05#ibcon#read 6, iclass 7, count 0 2006.202.01:23:11.05#ibcon#end of sib2, iclass 7, count 0 2006.202.01:23:11.05#ibcon#*mode == 0, iclass 7, count 0 2006.202.01:23:11.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.01:23:11.05#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.01:23:11.05#ibcon#*before write, iclass 7, count 0 2006.202.01:23:11.05#ibcon#enter sib2, iclass 7, count 0 2006.202.01:23:11.05#ibcon#flushed, iclass 7, count 0 2006.202.01:23:11.05#ibcon#about to write, iclass 7, count 0 2006.202.01:23:11.05#ibcon#wrote, iclass 7, count 0 2006.202.01:23:11.05#ibcon#about to read 3, iclass 7, count 0 2006.202.01:23:11.09#ibcon#read 3, iclass 7, count 0 2006.202.01:23:11.09#ibcon#about to read 4, iclass 7, count 0 2006.202.01:23:11.09#ibcon#read 4, iclass 7, count 0 2006.202.01:23:11.09#ibcon#about to read 5, iclass 7, count 0 2006.202.01:23:11.09#ibcon#read 5, iclass 7, count 0 2006.202.01:23:11.09#ibcon#about to read 6, iclass 7, count 0 2006.202.01:23:11.09#ibcon#read 6, iclass 7, count 0 2006.202.01:23:11.09#ibcon#end of sib2, iclass 7, count 0 2006.202.01:23:11.09#ibcon#*after write, iclass 7, count 0 2006.202.01:23:11.09#ibcon#*before return 0, iclass 7, count 0 2006.202.01:23:11.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:11.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:11.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.01:23:11.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.01:23:11.09$vck44/va=6,5 2006.202.01:23:11.09#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.202.01:23:11.09#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.202.01:23:11.09#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:11.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:11.15#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:11.15#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:11.15#ibcon#enter wrdev, iclass 11, count 2 2006.202.01:23:11.15#ibcon#first serial, iclass 11, count 2 2006.202.01:23:11.15#ibcon#enter sib2, iclass 11, count 2 2006.202.01:23:11.15#ibcon#flushed, iclass 11, count 2 2006.202.01:23:11.15#ibcon#about to write, iclass 11, count 2 2006.202.01:23:11.15#ibcon#wrote, iclass 11, count 2 2006.202.01:23:11.15#ibcon#about to read 3, iclass 11, count 2 2006.202.01:23:11.17#ibcon#read 3, iclass 11, count 2 2006.202.01:23:11.17#ibcon#about to read 4, iclass 11, count 2 2006.202.01:23:11.17#ibcon#read 4, iclass 11, count 2 2006.202.01:23:11.17#ibcon#about to read 5, iclass 11, count 2 2006.202.01:23:11.17#ibcon#read 5, iclass 11, count 2 2006.202.01:23:11.17#ibcon#about to read 6, iclass 11, count 2 2006.202.01:23:11.17#ibcon#read 6, iclass 11, count 2 2006.202.01:23:11.17#ibcon#end of sib2, iclass 11, count 2 2006.202.01:23:11.17#ibcon#*mode == 0, iclass 11, count 2 2006.202.01:23:11.17#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.202.01:23:11.17#ibcon#[25=AT06-05\r\n] 2006.202.01:23:11.17#ibcon#*before write, iclass 11, count 2 2006.202.01:23:11.17#ibcon#enter sib2, iclass 11, count 2 2006.202.01:23:11.17#ibcon#flushed, iclass 11, count 2 2006.202.01:23:11.17#ibcon#about to write, iclass 11, count 2 2006.202.01:23:11.17#ibcon#wrote, iclass 11, count 2 2006.202.01:23:11.17#ibcon#about to read 3, iclass 11, count 2 2006.202.01:23:11.20#ibcon#read 3, iclass 11, count 2 2006.202.01:23:11.20#ibcon#about to read 4, iclass 11, count 2 2006.202.01:23:11.20#ibcon#read 4, iclass 11, count 2 2006.202.01:23:11.20#ibcon#about to read 5, iclass 11, count 2 2006.202.01:23:11.20#ibcon#read 5, iclass 11, count 2 2006.202.01:23:11.20#ibcon#about to read 6, iclass 11, count 2 2006.202.01:23:11.20#ibcon#read 6, iclass 11, count 2 2006.202.01:23:11.20#ibcon#end of sib2, iclass 11, count 2 2006.202.01:23:11.20#ibcon#*after write, iclass 11, count 2 2006.202.01:23:11.20#ibcon#*before return 0, iclass 11, count 2 2006.202.01:23:11.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:11.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:11.20#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.202.01:23:11.20#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:11.20#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:11.32#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:11.32#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:11.32#ibcon#enter wrdev, iclass 11, count 0 2006.202.01:23:11.32#ibcon#first serial, iclass 11, count 0 2006.202.01:23:11.32#ibcon#enter sib2, iclass 11, count 0 2006.202.01:23:11.32#ibcon#flushed, iclass 11, count 0 2006.202.01:23:11.32#ibcon#about to write, iclass 11, count 0 2006.202.01:23:11.32#ibcon#wrote, iclass 11, count 0 2006.202.01:23:11.32#ibcon#about to read 3, iclass 11, count 0 2006.202.01:23:11.34#ibcon#read 3, iclass 11, count 0 2006.202.01:23:11.34#ibcon#about to read 4, iclass 11, count 0 2006.202.01:23:11.34#ibcon#read 4, iclass 11, count 0 2006.202.01:23:11.34#ibcon#about to read 5, iclass 11, count 0 2006.202.01:23:11.34#ibcon#read 5, iclass 11, count 0 2006.202.01:23:11.34#ibcon#about to read 6, iclass 11, count 0 2006.202.01:23:11.34#ibcon#read 6, iclass 11, count 0 2006.202.01:23:11.34#ibcon#end of sib2, iclass 11, count 0 2006.202.01:23:11.34#ibcon#*mode == 0, iclass 11, count 0 2006.202.01:23:11.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.01:23:11.34#ibcon#[25=USB\r\n] 2006.202.01:23:11.34#ibcon#*before write, iclass 11, count 0 2006.202.01:23:11.34#ibcon#enter sib2, iclass 11, count 0 2006.202.01:23:11.34#ibcon#flushed, iclass 11, count 0 2006.202.01:23:11.34#ibcon#about to write, iclass 11, count 0 2006.202.01:23:11.34#ibcon#wrote, iclass 11, count 0 2006.202.01:23:11.34#ibcon#about to read 3, iclass 11, count 0 2006.202.01:23:11.37#ibcon#read 3, iclass 11, count 0 2006.202.01:23:11.37#ibcon#about to read 4, iclass 11, count 0 2006.202.01:23:11.37#ibcon#read 4, iclass 11, count 0 2006.202.01:23:11.37#ibcon#about to read 5, iclass 11, count 0 2006.202.01:23:11.37#ibcon#read 5, iclass 11, count 0 2006.202.01:23:11.37#ibcon#about to read 6, iclass 11, count 0 2006.202.01:23:11.37#ibcon#read 6, iclass 11, count 0 2006.202.01:23:11.37#ibcon#end of sib2, iclass 11, count 0 2006.202.01:23:11.37#ibcon#*after write, iclass 11, count 0 2006.202.01:23:11.37#ibcon#*before return 0, iclass 11, count 0 2006.202.01:23:11.37#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:11.37#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:11.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.01:23:11.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.01:23:11.37$vck44/valo=7,864.99 2006.202.01:23:11.37#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.202.01:23:11.37#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.202.01:23:11.37#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:11.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:11.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:11.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:11.37#ibcon#enter wrdev, iclass 13, count 0 2006.202.01:23:11.37#ibcon#first serial, iclass 13, count 0 2006.202.01:23:11.37#ibcon#enter sib2, iclass 13, count 0 2006.202.01:23:11.37#ibcon#flushed, iclass 13, count 0 2006.202.01:23:11.37#ibcon#about to write, iclass 13, count 0 2006.202.01:23:11.37#ibcon#wrote, iclass 13, count 0 2006.202.01:23:11.37#ibcon#about to read 3, iclass 13, count 0 2006.202.01:23:11.39#ibcon#read 3, iclass 13, count 0 2006.202.01:23:11.39#ibcon#about to read 4, iclass 13, count 0 2006.202.01:23:11.39#ibcon#read 4, iclass 13, count 0 2006.202.01:23:11.39#ibcon#about to read 5, iclass 13, count 0 2006.202.01:23:11.39#ibcon#read 5, iclass 13, count 0 2006.202.01:23:11.39#ibcon#about to read 6, iclass 13, count 0 2006.202.01:23:11.39#ibcon#read 6, iclass 13, count 0 2006.202.01:23:11.39#ibcon#end of sib2, iclass 13, count 0 2006.202.01:23:11.39#ibcon#*mode == 0, iclass 13, count 0 2006.202.01:23:11.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.01:23:11.39#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.01:23:11.39#ibcon#*before write, iclass 13, count 0 2006.202.01:23:11.39#ibcon#enter sib2, iclass 13, count 0 2006.202.01:23:11.39#ibcon#flushed, iclass 13, count 0 2006.202.01:23:11.39#ibcon#about to write, iclass 13, count 0 2006.202.01:23:11.39#ibcon#wrote, iclass 13, count 0 2006.202.01:23:11.39#ibcon#about to read 3, iclass 13, count 0 2006.202.01:23:11.43#ibcon#read 3, iclass 13, count 0 2006.202.01:23:11.43#ibcon#about to read 4, iclass 13, count 0 2006.202.01:23:11.43#ibcon#read 4, iclass 13, count 0 2006.202.01:23:11.43#ibcon#about to read 5, iclass 13, count 0 2006.202.01:23:11.43#ibcon#read 5, iclass 13, count 0 2006.202.01:23:11.43#ibcon#about to read 6, iclass 13, count 0 2006.202.01:23:11.43#ibcon#read 6, iclass 13, count 0 2006.202.01:23:11.43#ibcon#end of sib2, iclass 13, count 0 2006.202.01:23:11.43#ibcon#*after write, iclass 13, count 0 2006.202.01:23:11.43#ibcon#*before return 0, iclass 13, count 0 2006.202.01:23:11.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:11.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:11.43#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.01:23:11.43#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.01:23:11.43$vck44/va=7,5 2006.202.01:23:11.43#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.202.01:23:11.43#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.202.01:23:11.43#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:11.43#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:11.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:11.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:11.49#ibcon#enter wrdev, iclass 15, count 2 2006.202.01:23:11.49#ibcon#first serial, iclass 15, count 2 2006.202.01:23:11.49#ibcon#enter sib2, iclass 15, count 2 2006.202.01:23:11.49#ibcon#flushed, iclass 15, count 2 2006.202.01:23:11.49#ibcon#about to write, iclass 15, count 2 2006.202.01:23:11.49#ibcon#wrote, iclass 15, count 2 2006.202.01:23:11.49#ibcon#about to read 3, iclass 15, count 2 2006.202.01:23:11.51#ibcon#read 3, iclass 15, count 2 2006.202.01:23:11.51#ibcon#about to read 4, iclass 15, count 2 2006.202.01:23:11.51#ibcon#read 4, iclass 15, count 2 2006.202.01:23:11.51#ibcon#about to read 5, iclass 15, count 2 2006.202.01:23:11.51#ibcon#read 5, iclass 15, count 2 2006.202.01:23:11.51#ibcon#about to read 6, iclass 15, count 2 2006.202.01:23:11.51#ibcon#read 6, iclass 15, count 2 2006.202.01:23:11.51#ibcon#end of sib2, iclass 15, count 2 2006.202.01:23:11.51#ibcon#*mode == 0, iclass 15, count 2 2006.202.01:23:11.51#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.202.01:23:11.51#ibcon#[25=AT07-05\r\n] 2006.202.01:23:11.51#ibcon#*before write, iclass 15, count 2 2006.202.01:23:11.51#ibcon#enter sib2, iclass 15, count 2 2006.202.01:23:11.51#ibcon#flushed, iclass 15, count 2 2006.202.01:23:11.51#ibcon#about to write, iclass 15, count 2 2006.202.01:23:11.51#ibcon#wrote, iclass 15, count 2 2006.202.01:23:11.51#ibcon#about to read 3, iclass 15, count 2 2006.202.01:23:11.54#ibcon#read 3, iclass 15, count 2 2006.202.01:23:11.54#ibcon#about to read 4, iclass 15, count 2 2006.202.01:23:11.54#ibcon#read 4, iclass 15, count 2 2006.202.01:23:11.54#ibcon#about to read 5, iclass 15, count 2 2006.202.01:23:11.54#ibcon#read 5, iclass 15, count 2 2006.202.01:23:11.54#ibcon#about to read 6, iclass 15, count 2 2006.202.01:23:11.54#ibcon#read 6, iclass 15, count 2 2006.202.01:23:11.54#ibcon#end of sib2, iclass 15, count 2 2006.202.01:23:11.54#ibcon#*after write, iclass 15, count 2 2006.202.01:23:11.54#ibcon#*before return 0, iclass 15, count 2 2006.202.01:23:11.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:11.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:11.54#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.202.01:23:11.54#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:11.54#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:11.66#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:11.66#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:11.66#ibcon#enter wrdev, iclass 15, count 0 2006.202.01:23:11.66#ibcon#first serial, iclass 15, count 0 2006.202.01:23:11.66#ibcon#enter sib2, iclass 15, count 0 2006.202.01:23:11.66#ibcon#flushed, iclass 15, count 0 2006.202.01:23:11.66#ibcon#about to write, iclass 15, count 0 2006.202.01:23:11.66#ibcon#wrote, iclass 15, count 0 2006.202.01:23:11.66#ibcon#about to read 3, iclass 15, count 0 2006.202.01:23:11.68#ibcon#read 3, iclass 15, count 0 2006.202.01:23:11.68#ibcon#about to read 4, iclass 15, count 0 2006.202.01:23:11.68#ibcon#read 4, iclass 15, count 0 2006.202.01:23:11.68#ibcon#about to read 5, iclass 15, count 0 2006.202.01:23:11.68#ibcon#read 5, iclass 15, count 0 2006.202.01:23:11.68#ibcon#about to read 6, iclass 15, count 0 2006.202.01:23:11.68#ibcon#read 6, iclass 15, count 0 2006.202.01:23:11.68#ibcon#end of sib2, iclass 15, count 0 2006.202.01:23:11.68#ibcon#*mode == 0, iclass 15, count 0 2006.202.01:23:11.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.01:23:11.68#ibcon#[25=USB\r\n] 2006.202.01:23:11.68#ibcon#*before write, iclass 15, count 0 2006.202.01:23:11.68#ibcon#enter sib2, iclass 15, count 0 2006.202.01:23:11.68#ibcon#flushed, iclass 15, count 0 2006.202.01:23:11.68#ibcon#about to write, iclass 15, count 0 2006.202.01:23:11.68#ibcon#wrote, iclass 15, count 0 2006.202.01:23:11.68#ibcon#about to read 3, iclass 15, count 0 2006.202.01:23:11.71#ibcon#read 3, iclass 15, count 0 2006.202.01:23:11.71#ibcon#about to read 4, iclass 15, count 0 2006.202.01:23:11.71#ibcon#read 4, iclass 15, count 0 2006.202.01:23:11.71#ibcon#about to read 5, iclass 15, count 0 2006.202.01:23:11.71#ibcon#read 5, iclass 15, count 0 2006.202.01:23:11.71#ibcon#about to read 6, iclass 15, count 0 2006.202.01:23:11.71#ibcon#read 6, iclass 15, count 0 2006.202.01:23:11.71#ibcon#end of sib2, iclass 15, count 0 2006.202.01:23:11.71#ibcon#*after write, iclass 15, count 0 2006.202.01:23:11.71#ibcon#*before return 0, iclass 15, count 0 2006.202.01:23:11.71#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:11.71#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:11.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.01:23:11.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.01:23:11.71$vck44/valo=8,884.99 2006.202.01:23:11.71#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.01:23:11.71#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.01:23:11.71#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:11.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:11.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:11.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:11.71#ibcon#enter wrdev, iclass 17, count 0 2006.202.01:23:11.71#ibcon#first serial, iclass 17, count 0 2006.202.01:23:11.71#ibcon#enter sib2, iclass 17, count 0 2006.202.01:23:11.71#ibcon#flushed, iclass 17, count 0 2006.202.01:23:11.71#ibcon#about to write, iclass 17, count 0 2006.202.01:23:11.71#ibcon#wrote, iclass 17, count 0 2006.202.01:23:11.71#ibcon#about to read 3, iclass 17, count 0 2006.202.01:23:11.73#ibcon#read 3, iclass 17, count 0 2006.202.01:23:11.73#ibcon#about to read 4, iclass 17, count 0 2006.202.01:23:11.73#ibcon#read 4, iclass 17, count 0 2006.202.01:23:11.73#ibcon#about to read 5, iclass 17, count 0 2006.202.01:23:11.73#ibcon#read 5, iclass 17, count 0 2006.202.01:23:11.73#ibcon#about to read 6, iclass 17, count 0 2006.202.01:23:11.73#ibcon#read 6, iclass 17, count 0 2006.202.01:23:11.73#ibcon#end of sib2, iclass 17, count 0 2006.202.01:23:11.73#ibcon#*mode == 0, iclass 17, count 0 2006.202.01:23:11.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.01:23:11.73#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.01:23:11.73#ibcon#*before write, iclass 17, count 0 2006.202.01:23:11.73#ibcon#enter sib2, iclass 17, count 0 2006.202.01:23:11.73#ibcon#flushed, iclass 17, count 0 2006.202.01:23:11.73#ibcon#about to write, iclass 17, count 0 2006.202.01:23:11.73#ibcon#wrote, iclass 17, count 0 2006.202.01:23:11.73#ibcon#about to read 3, iclass 17, count 0 2006.202.01:23:11.77#ibcon#read 3, iclass 17, count 0 2006.202.01:23:11.77#ibcon#about to read 4, iclass 17, count 0 2006.202.01:23:11.77#ibcon#read 4, iclass 17, count 0 2006.202.01:23:11.77#ibcon#about to read 5, iclass 17, count 0 2006.202.01:23:11.77#ibcon#read 5, iclass 17, count 0 2006.202.01:23:11.77#ibcon#about to read 6, iclass 17, count 0 2006.202.01:23:11.77#ibcon#read 6, iclass 17, count 0 2006.202.01:23:11.77#ibcon#end of sib2, iclass 17, count 0 2006.202.01:23:11.77#ibcon#*after write, iclass 17, count 0 2006.202.01:23:11.77#ibcon#*before return 0, iclass 17, count 0 2006.202.01:23:11.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:11.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:11.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.01:23:11.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.01:23:11.77$vck44/va=8,4 2006.202.01:23:11.77#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.202.01:23:11.77#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.202.01:23:11.77#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:11.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:11.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:11.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:11.83#ibcon#enter wrdev, iclass 19, count 2 2006.202.01:23:11.83#ibcon#first serial, iclass 19, count 2 2006.202.01:23:11.83#ibcon#enter sib2, iclass 19, count 2 2006.202.01:23:11.83#ibcon#flushed, iclass 19, count 2 2006.202.01:23:11.83#ibcon#about to write, iclass 19, count 2 2006.202.01:23:11.83#ibcon#wrote, iclass 19, count 2 2006.202.01:23:11.83#ibcon#about to read 3, iclass 19, count 2 2006.202.01:23:11.85#ibcon#read 3, iclass 19, count 2 2006.202.01:23:11.85#ibcon#about to read 4, iclass 19, count 2 2006.202.01:23:11.85#ibcon#read 4, iclass 19, count 2 2006.202.01:23:11.85#ibcon#about to read 5, iclass 19, count 2 2006.202.01:23:11.85#ibcon#read 5, iclass 19, count 2 2006.202.01:23:11.85#ibcon#about to read 6, iclass 19, count 2 2006.202.01:23:11.85#ibcon#read 6, iclass 19, count 2 2006.202.01:23:11.85#ibcon#end of sib2, iclass 19, count 2 2006.202.01:23:11.85#ibcon#*mode == 0, iclass 19, count 2 2006.202.01:23:11.85#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.202.01:23:11.85#ibcon#[25=AT08-04\r\n] 2006.202.01:23:11.85#ibcon#*before write, iclass 19, count 2 2006.202.01:23:11.85#ibcon#enter sib2, iclass 19, count 2 2006.202.01:23:11.85#ibcon#flushed, iclass 19, count 2 2006.202.01:23:11.85#ibcon#about to write, iclass 19, count 2 2006.202.01:23:11.85#ibcon#wrote, iclass 19, count 2 2006.202.01:23:11.85#ibcon#about to read 3, iclass 19, count 2 2006.202.01:23:11.88#ibcon#read 3, iclass 19, count 2 2006.202.01:23:11.88#ibcon#about to read 4, iclass 19, count 2 2006.202.01:23:11.88#ibcon#read 4, iclass 19, count 2 2006.202.01:23:11.88#ibcon#about to read 5, iclass 19, count 2 2006.202.01:23:11.88#ibcon#read 5, iclass 19, count 2 2006.202.01:23:11.88#ibcon#about to read 6, iclass 19, count 2 2006.202.01:23:11.88#ibcon#read 6, iclass 19, count 2 2006.202.01:23:11.88#ibcon#end of sib2, iclass 19, count 2 2006.202.01:23:11.88#ibcon#*after write, iclass 19, count 2 2006.202.01:23:11.88#ibcon#*before return 0, iclass 19, count 2 2006.202.01:23:11.88#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:11.88#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:11.88#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.202.01:23:11.88#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:11.88#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:12.00#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:12.00#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:12.00#ibcon#enter wrdev, iclass 19, count 0 2006.202.01:23:12.00#ibcon#first serial, iclass 19, count 0 2006.202.01:23:12.00#ibcon#enter sib2, iclass 19, count 0 2006.202.01:23:12.00#ibcon#flushed, iclass 19, count 0 2006.202.01:23:12.00#ibcon#about to write, iclass 19, count 0 2006.202.01:23:12.00#ibcon#wrote, iclass 19, count 0 2006.202.01:23:12.00#ibcon#about to read 3, iclass 19, count 0 2006.202.01:23:12.02#ibcon#read 3, iclass 19, count 0 2006.202.01:23:12.02#ibcon#about to read 4, iclass 19, count 0 2006.202.01:23:12.02#ibcon#read 4, iclass 19, count 0 2006.202.01:23:12.02#ibcon#about to read 5, iclass 19, count 0 2006.202.01:23:12.02#ibcon#read 5, iclass 19, count 0 2006.202.01:23:12.02#ibcon#about to read 6, iclass 19, count 0 2006.202.01:23:12.02#ibcon#read 6, iclass 19, count 0 2006.202.01:23:12.02#ibcon#end of sib2, iclass 19, count 0 2006.202.01:23:12.02#ibcon#*mode == 0, iclass 19, count 0 2006.202.01:23:12.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.01:23:12.02#ibcon#[25=USB\r\n] 2006.202.01:23:12.02#ibcon#*before write, iclass 19, count 0 2006.202.01:23:12.02#ibcon#enter sib2, iclass 19, count 0 2006.202.01:23:12.02#ibcon#flushed, iclass 19, count 0 2006.202.01:23:12.02#ibcon#about to write, iclass 19, count 0 2006.202.01:23:12.02#ibcon#wrote, iclass 19, count 0 2006.202.01:23:12.02#ibcon#about to read 3, iclass 19, count 0 2006.202.01:23:12.05#ibcon#read 3, iclass 19, count 0 2006.202.01:23:12.05#ibcon#about to read 4, iclass 19, count 0 2006.202.01:23:12.05#ibcon#read 4, iclass 19, count 0 2006.202.01:23:12.05#ibcon#about to read 5, iclass 19, count 0 2006.202.01:23:12.05#ibcon#read 5, iclass 19, count 0 2006.202.01:23:12.05#ibcon#about to read 6, iclass 19, count 0 2006.202.01:23:12.05#ibcon#read 6, iclass 19, count 0 2006.202.01:23:12.05#ibcon#end of sib2, iclass 19, count 0 2006.202.01:23:12.05#ibcon#*after write, iclass 19, count 0 2006.202.01:23:12.05#ibcon#*before return 0, iclass 19, count 0 2006.202.01:23:12.05#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:12.05#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:12.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.01:23:12.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.01:23:12.05$vck44/vblo=1,629.99 2006.202.01:23:12.05#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.202.01:23:12.05#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.202.01:23:12.05#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:12.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:12.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:12.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:12.05#ibcon#enter wrdev, iclass 21, count 0 2006.202.01:23:12.05#ibcon#first serial, iclass 21, count 0 2006.202.01:23:12.05#ibcon#enter sib2, iclass 21, count 0 2006.202.01:23:12.05#ibcon#flushed, iclass 21, count 0 2006.202.01:23:12.05#ibcon#about to write, iclass 21, count 0 2006.202.01:23:12.05#ibcon#wrote, iclass 21, count 0 2006.202.01:23:12.05#ibcon#about to read 3, iclass 21, count 0 2006.202.01:23:12.07#ibcon#read 3, iclass 21, count 0 2006.202.01:23:12.07#ibcon#about to read 4, iclass 21, count 0 2006.202.01:23:12.07#ibcon#read 4, iclass 21, count 0 2006.202.01:23:12.07#ibcon#about to read 5, iclass 21, count 0 2006.202.01:23:12.07#ibcon#read 5, iclass 21, count 0 2006.202.01:23:12.07#ibcon#about to read 6, iclass 21, count 0 2006.202.01:23:12.07#ibcon#read 6, iclass 21, count 0 2006.202.01:23:12.07#ibcon#end of sib2, iclass 21, count 0 2006.202.01:23:12.07#ibcon#*mode == 0, iclass 21, count 0 2006.202.01:23:12.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.01:23:12.07#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.01:23:12.07#ibcon#*before write, iclass 21, count 0 2006.202.01:23:12.07#ibcon#enter sib2, iclass 21, count 0 2006.202.01:23:12.07#ibcon#flushed, iclass 21, count 0 2006.202.01:23:12.07#ibcon#about to write, iclass 21, count 0 2006.202.01:23:12.07#ibcon#wrote, iclass 21, count 0 2006.202.01:23:12.07#ibcon#about to read 3, iclass 21, count 0 2006.202.01:23:12.11#ibcon#read 3, iclass 21, count 0 2006.202.01:23:12.11#ibcon#about to read 4, iclass 21, count 0 2006.202.01:23:12.11#ibcon#read 4, iclass 21, count 0 2006.202.01:23:12.11#ibcon#about to read 5, iclass 21, count 0 2006.202.01:23:12.11#ibcon#read 5, iclass 21, count 0 2006.202.01:23:12.11#ibcon#about to read 6, iclass 21, count 0 2006.202.01:23:12.11#ibcon#read 6, iclass 21, count 0 2006.202.01:23:12.11#ibcon#end of sib2, iclass 21, count 0 2006.202.01:23:12.11#ibcon#*after write, iclass 21, count 0 2006.202.01:23:12.11#ibcon#*before return 0, iclass 21, count 0 2006.202.01:23:12.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:12.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:12.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.01:23:12.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.01:23:12.11$vck44/vb=1,4 2006.202.01:23:12.11#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.202.01:23:12.11#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.202.01:23:12.11#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:12.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:23:12.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:23:12.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:23:12.11#ibcon#enter wrdev, iclass 23, count 2 2006.202.01:23:12.11#ibcon#first serial, iclass 23, count 2 2006.202.01:23:12.11#ibcon#enter sib2, iclass 23, count 2 2006.202.01:23:12.11#ibcon#flushed, iclass 23, count 2 2006.202.01:23:12.11#ibcon#about to write, iclass 23, count 2 2006.202.01:23:12.11#ibcon#wrote, iclass 23, count 2 2006.202.01:23:12.11#ibcon#about to read 3, iclass 23, count 2 2006.202.01:23:12.13#ibcon#read 3, iclass 23, count 2 2006.202.01:23:12.13#ibcon#about to read 4, iclass 23, count 2 2006.202.01:23:12.13#ibcon#read 4, iclass 23, count 2 2006.202.01:23:12.13#ibcon#about to read 5, iclass 23, count 2 2006.202.01:23:12.13#ibcon#read 5, iclass 23, count 2 2006.202.01:23:12.13#ibcon#about to read 6, iclass 23, count 2 2006.202.01:23:12.13#ibcon#read 6, iclass 23, count 2 2006.202.01:23:12.13#ibcon#end of sib2, iclass 23, count 2 2006.202.01:23:12.13#ibcon#*mode == 0, iclass 23, count 2 2006.202.01:23:12.13#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.202.01:23:12.13#ibcon#[27=AT01-04\r\n] 2006.202.01:23:12.13#ibcon#*before write, iclass 23, count 2 2006.202.01:23:12.13#ibcon#enter sib2, iclass 23, count 2 2006.202.01:23:12.13#ibcon#flushed, iclass 23, count 2 2006.202.01:23:12.13#ibcon#about to write, iclass 23, count 2 2006.202.01:23:12.13#ibcon#wrote, iclass 23, count 2 2006.202.01:23:12.13#ibcon#about to read 3, iclass 23, count 2 2006.202.01:23:12.16#ibcon#read 3, iclass 23, count 2 2006.202.01:23:12.16#ibcon#about to read 4, iclass 23, count 2 2006.202.01:23:12.16#ibcon#read 4, iclass 23, count 2 2006.202.01:23:12.16#ibcon#about to read 5, iclass 23, count 2 2006.202.01:23:12.16#ibcon#read 5, iclass 23, count 2 2006.202.01:23:12.16#ibcon#about to read 6, iclass 23, count 2 2006.202.01:23:12.16#ibcon#read 6, iclass 23, count 2 2006.202.01:23:12.16#ibcon#end of sib2, iclass 23, count 2 2006.202.01:23:12.16#ibcon#*after write, iclass 23, count 2 2006.202.01:23:12.16#ibcon#*before return 0, iclass 23, count 2 2006.202.01:23:12.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:23:12.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:23:12.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.202.01:23:12.16#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:12.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:23:12.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:23:12.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:23:12.28#ibcon#enter wrdev, iclass 23, count 0 2006.202.01:23:12.28#ibcon#first serial, iclass 23, count 0 2006.202.01:23:12.28#ibcon#enter sib2, iclass 23, count 0 2006.202.01:23:12.28#ibcon#flushed, iclass 23, count 0 2006.202.01:23:12.28#ibcon#about to write, iclass 23, count 0 2006.202.01:23:12.28#ibcon#wrote, iclass 23, count 0 2006.202.01:23:12.28#ibcon#about to read 3, iclass 23, count 0 2006.202.01:23:12.30#ibcon#read 3, iclass 23, count 0 2006.202.01:23:12.30#ibcon#about to read 4, iclass 23, count 0 2006.202.01:23:12.30#ibcon#read 4, iclass 23, count 0 2006.202.01:23:12.30#ibcon#about to read 5, iclass 23, count 0 2006.202.01:23:12.30#ibcon#read 5, iclass 23, count 0 2006.202.01:23:12.30#ibcon#about to read 6, iclass 23, count 0 2006.202.01:23:12.30#ibcon#read 6, iclass 23, count 0 2006.202.01:23:12.30#ibcon#end of sib2, iclass 23, count 0 2006.202.01:23:12.30#ibcon#*mode == 0, iclass 23, count 0 2006.202.01:23:12.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.01:23:12.30#ibcon#[27=USB\r\n] 2006.202.01:23:12.30#ibcon#*before write, iclass 23, count 0 2006.202.01:23:12.30#ibcon#enter sib2, iclass 23, count 0 2006.202.01:23:12.30#ibcon#flushed, iclass 23, count 0 2006.202.01:23:12.30#ibcon#about to write, iclass 23, count 0 2006.202.01:23:12.30#ibcon#wrote, iclass 23, count 0 2006.202.01:23:12.30#ibcon#about to read 3, iclass 23, count 0 2006.202.01:23:12.33#ibcon#read 3, iclass 23, count 0 2006.202.01:23:12.33#ibcon#about to read 4, iclass 23, count 0 2006.202.01:23:12.33#ibcon#read 4, iclass 23, count 0 2006.202.01:23:12.33#ibcon#about to read 5, iclass 23, count 0 2006.202.01:23:12.33#ibcon#read 5, iclass 23, count 0 2006.202.01:23:12.33#ibcon#about to read 6, iclass 23, count 0 2006.202.01:23:12.33#ibcon#read 6, iclass 23, count 0 2006.202.01:23:12.33#ibcon#end of sib2, iclass 23, count 0 2006.202.01:23:12.33#ibcon#*after write, iclass 23, count 0 2006.202.01:23:12.33#ibcon#*before return 0, iclass 23, count 0 2006.202.01:23:12.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:23:12.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:23:12.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.01:23:12.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.01:23:12.33$vck44/vblo=2,634.99 2006.202.01:23:12.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.202.01:23:12.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.202.01:23:12.33#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:12.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:12.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:12.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:12.33#ibcon#enter wrdev, iclass 25, count 0 2006.202.01:23:12.33#ibcon#first serial, iclass 25, count 0 2006.202.01:23:12.33#ibcon#enter sib2, iclass 25, count 0 2006.202.01:23:12.33#ibcon#flushed, iclass 25, count 0 2006.202.01:23:12.33#ibcon#about to write, iclass 25, count 0 2006.202.01:23:12.33#ibcon#wrote, iclass 25, count 0 2006.202.01:23:12.33#ibcon#about to read 3, iclass 25, count 0 2006.202.01:23:12.35#ibcon#read 3, iclass 25, count 0 2006.202.01:23:12.35#ibcon#about to read 4, iclass 25, count 0 2006.202.01:23:12.35#ibcon#read 4, iclass 25, count 0 2006.202.01:23:12.35#ibcon#about to read 5, iclass 25, count 0 2006.202.01:23:12.35#ibcon#read 5, iclass 25, count 0 2006.202.01:23:12.35#ibcon#about to read 6, iclass 25, count 0 2006.202.01:23:12.35#ibcon#read 6, iclass 25, count 0 2006.202.01:23:12.35#ibcon#end of sib2, iclass 25, count 0 2006.202.01:23:12.35#ibcon#*mode == 0, iclass 25, count 0 2006.202.01:23:12.35#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.01:23:12.35#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.01:23:12.35#ibcon#*before write, iclass 25, count 0 2006.202.01:23:12.35#ibcon#enter sib2, iclass 25, count 0 2006.202.01:23:12.35#ibcon#flushed, iclass 25, count 0 2006.202.01:23:12.35#ibcon#about to write, iclass 25, count 0 2006.202.01:23:12.35#ibcon#wrote, iclass 25, count 0 2006.202.01:23:12.35#ibcon#about to read 3, iclass 25, count 0 2006.202.01:23:12.39#ibcon#read 3, iclass 25, count 0 2006.202.01:23:12.39#ibcon#about to read 4, iclass 25, count 0 2006.202.01:23:12.39#ibcon#read 4, iclass 25, count 0 2006.202.01:23:12.39#ibcon#about to read 5, iclass 25, count 0 2006.202.01:23:12.39#ibcon#read 5, iclass 25, count 0 2006.202.01:23:12.39#ibcon#about to read 6, iclass 25, count 0 2006.202.01:23:12.39#ibcon#read 6, iclass 25, count 0 2006.202.01:23:12.39#ibcon#end of sib2, iclass 25, count 0 2006.202.01:23:12.39#ibcon#*after write, iclass 25, count 0 2006.202.01:23:12.39#ibcon#*before return 0, iclass 25, count 0 2006.202.01:23:12.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:12.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:23:12.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.01:23:12.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.01:23:12.39$vck44/vb=2,5 2006.202.01:23:12.39#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.202.01:23:12.39#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.202.01:23:12.39#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:12.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:12.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:12.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:12.45#ibcon#enter wrdev, iclass 27, count 2 2006.202.01:23:12.45#ibcon#first serial, iclass 27, count 2 2006.202.01:23:12.45#ibcon#enter sib2, iclass 27, count 2 2006.202.01:23:12.45#ibcon#flushed, iclass 27, count 2 2006.202.01:23:12.45#ibcon#about to write, iclass 27, count 2 2006.202.01:23:12.45#ibcon#wrote, iclass 27, count 2 2006.202.01:23:12.45#ibcon#about to read 3, iclass 27, count 2 2006.202.01:23:12.47#ibcon#read 3, iclass 27, count 2 2006.202.01:23:12.47#ibcon#about to read 4, iclass 27, count 2 2006.202.01:23:12.47#ibcon#read 4, iclass 27, count 2 2006.202.01:23:12.47#ibcon#about to read 5, iclass 27, count 2 2006.202.01:23:12.47#ibcon#read 5, iclass 27, count 2 2006.202.01:23:12.47#ibcon#about to read 6, iclass 27, count 2 2006.202.01:23:12.47#ibcon#read 6, iclass 27, count 2 2006.202.01:23:12.47#ibcon#end of sib2, iclass 27, count 2 2006.202.01:23:12.47#ibcon#*mode == 0, iclass 27, count 2 2006.202.01:23:12.47#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.202.01:23:12.47#ibcon#[27=AT02-05\r\n] 2006.202.01:23:12.47#ibcon#*before write, iclass 27, count 2 2006.202.01:23:12.47#ibcon#enter sib2, iclass 27, count 2 2006.202.01:23:12.47#ibcon#flushed, iclass 27, count 2 2006.202.01:23:12.47#ibcon#about to write, iclass 27, count 2 2006.202.01:23:12.47#ibcon#wrote, iclass 27, count 2 2006.202.01:23:12.47#ibcon#about to read 3, iclass 27, count 2 2006.202.01:23:12.50#ibcon#read 3, iclass 27, count 2 2006.202.01:23:12.50#ibcon#about to read 4, iclass 27, count 2 2006.202.01:23:12.50#ibcon#read 4, iclass 27, count 2 2006.202.01:23:12.50#ibcon#about to read 5, iclass 27, count 2 2006.202.01:23:12.50#ibcon#read 5, iclass 27, count 2 2006.202.01:23:12.50#ibcon#about to read 6, iclass 27, count 2 2006.202.01:23:12.50#ibcon#read 6, iclass 27, count 2 2006.202.01:23:12.50#ibcon#end of sib2, iclass 27, count 2 2006.202.01:23:12.50#ibcon#*after write, iclass 27, count 2 2006.202.01:23:12.50#ibcon#*before return 0, iclass 27, count 2 2006.202.01:23:12.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:12.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:23:12.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.202.01:23:12.50#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:12.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:12.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:12.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:12.62#ibcon#enter wrdev, iclass 27, count 0 2006.202.01:23:12.62#ibcon#first serial, iclass 27, count 0 2006.202.01:23:12.62#ibcon#enter sib2, iclass 27, count 0 2006.202.01:23:12.62#ibcon#flushed, iclass 27, count 0 2006.202.01:23:12.62#ibcon#about to write, iclass 27, count 0 2006.202.01:23:12.62#ibcon#wrote, iclass 27, count 0 2006.202.01:23:12.62#ibcon#about to read 3, iclass 27, count 0 2006.202.01:23:12.64#ibcon#read 3, iclass 27, count 0 2006.202.01:23:12.64#ibcon#about to read 4, iclass 27, count 0 2006.202.01:23:12.64#ibcon#read 4, iclass 27, count 0 2006.202.01:23:12.64#ibcon#about to read 5, iclass 27, count 0 2006.202.01:23:12.64#ibcon#read 5, iclass 27, count 0 2006.202.01:23:12.64#ibcon#about to read 6, iclass 27, count 0 2006.202.01:23:12.64#ibcon#read 6, iclass 27, count 0 2006.202.01:23:12.64#ibcon#end of sib2, iclass 27, count 0 2006.202.01:23:12.64#ibcon#*mode == 0, iclass 27, count 0 2006.202.01:23:12.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.01:23:12.64#ibcon#[27=USB\r\n] 2006.202.01:23:12.64#ibcon#*before write, iclass 27, count 0 2006.202.01:23:12.64#ibcon#enter sib2, iclass 27, count 0 2006.202.01:23:12.64#ibcon#flushed, iclass 27, count 0 2006.202.01:23:12.64#ibcon#about to write, iclass 27, count 0 2006.202.01:23:12.64#ibcon#wrote, iclass 27, count 0 2006.202.01:23:12.64#ibcon#about to read 3, iclass 27, count 0 2006.202.01:23:12.67#ibcon#read 3, iclass 27, count 0 2006.202.01:23:12.67#ibcon#about to read 4, iclass 27, count 0 2006.202.01:23:12.67#ibcon#read 4, iclass 27, count 0 2006.202.01:23:12.67#ibcon#about to read 5, iclass 27, count 0 2006.202.01:23:12.67#ibcon#read 5, iclass 27, count 0 2006.202.01:23:12.67#ibcon#about to read 6, iclass 27, count 0 2006.202.01:23:12.67#ibcon#read 6, iclass 27, count 0 2006.202.01:23:12.67#ibcon#end of sib2, iclass 27, count 0 2006.202.01:23:12.67#ibcon#*after write, iclass 27, count 0 2006.202.01:23:12.67#ibcon#*before return 0, iclass 27, count 0 2006.202.01:23:12.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:12.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:23:12.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.01:23:12.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.01:23:12.67$vck44/vblo=3,649.99 2006.202.01:23:12.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.202.01:23:12.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.202.01:23:12.67#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:12.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:12.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:12.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:12.67#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:23:12.67#ibcon#first serial, iclass 29, count 0 2006.202.01:23:12.67#ibcon#enter sib2, iclass 29, count 0 2006.202.01:23:12.67#ibcon#flushed, iclass 29, count 0 2006.202.01:23:12.67#ibcon#about to write, iclass 29, count 0 2006.202.01:23:12.67#ibcon#wrote, iclass 29, count 0 2006.202.01:23:12.67#ibcon#about to read 3, iclass 29, count 0 2006.202.01:23:12.69#ibcon#read 3, iclass 29, count 0 2006.202.01:23:12.69#ibcon#about to read 4, iclass 29, count 0 2006.202.01:23:12.69#ibcon#read 4, iclass 29, count 0 2006.202.01:23:12.69#ibcon#about to read 5, iclass 29, count 0 2006.202.01:23:12.69#ibcon#read 5, iclass 29, count 0 2006.202.01:23:12.69#ibcon#about to read 6, iclass 29, count 0 2006.202.01:23:12.69#ibcon#read 6, iclass 29, count 0 2006.202.01:23:12.69#ibcon#end of sib2, iclass 29, count 0 2006.202.01:23:12.69#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:23:12.69#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:23:12.69#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.01:23:12.69#ibcon#*before write, iclass 29, count 0 2006.202.01:23:12.69#ibcon#enter sib2, iclass 29, count 0 2006.202.01:23:12.69#ibcon#flushed, iclass 29, count 0 2006.202.01:23:12.69#ibcon#about to write, iclass 29, count 0 2006.202.01:23:12.69#ibcon#wrote, iclass 29, count 0 2006.202.01:23:12.69#ibcon#about to read 3, iclass 29, count 0 2006.202.01:23:12.73#ibcon#read 3, iclass 29, count 0 2006.202.01:23:12.73#ibcon#about to read 4, iclass 29, count 0 2006.202.01:23:12.73#ibcon#read 4, iclass 29, count 0 2006.202.01:23:12.73#ibcon#about to read 5, iclass 29, count 0 2006.202.01:23:12.73#ibcon#read 5, iclass 29, count 0 2006.202.01:23:12.86#ibcon#about to read 6, iclass 29, count 0 2006.202.01:23:12.86#ibcon#read 6, iclass 29, count 0 2006.202.01:23:12.86#ibcon#end of sib2, iclass 29, count 0 2006.202.01:23:12.86#ibcon#*after write, iclass 29, count 0 2006.202.01:23:12.86#ibcon#*before return 0, iclass 29, count 0 2006.202.01:23:12.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:12.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:23:12.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:23:12.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:23:12.86$vck44/vb=3,4 2006.202.01:23:12.86#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.202.01:23:12.86#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.202.01:23:12.87#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:12.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:12.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:12.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:12.87#ibcon#enter wrdev, iclass 31, count 2 2006.202.01:23:12.87#ibcon#first serial, iclass 31, count 2 2006.202.01:23:12.87#ibcon#enter sib2, iclass 31, count 2 2006.202.01:23:12.87#ibcon#flushed, iclass 31, count 2 2006.202.01:23:12.87#ibcon#about to write, iclass 31, count 2 2006.202.01:23:12.87#ibcon#wrote, iclass 31, count 2 2006.202.01:23:12.87#ibcon#about to read 3, iclass 31, count 2 2006.202.01:23:12.89#ibcon#read 3, iclass 31, count 2 2006.202.01:23:12.89#ibcon#about to read 4, iclass 31, count 2 2006.202.01:23:12.89#ibcon#read 4, iclass 31, count 2 2006.202.01:23:12.89#ibcon#about to read 5, iclass 31, count 2 2006.202.01:23:12.89#ibcon#read 5, iclass 31, count 2 2006.202.01:23:12.89#ibcon#about to read 6, iclass 31, count 2 2006.202.01:23:12.89#ibcon#read 6, iclass 31, count 2 2006.202.01:23:12.89#ibcon#end of sib2, iclass 31, count 2 2006.202.01:23:12.89#ibcon#*mode == 0, iclass 31, count 2 2006.202.01:23:12.89#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.202.01:23:12.89#ibcon#[27=AT03-04\r\n] 2006.202.01:23:12.89#ibcon#*before write, iclass 31, count 2 2006.202.01:23:12.89#ibcon#enter sib2, iclass 31, count 2 2006.202.01:23:12.89#ibcon#flushed, iclass 31, count 2 2006.202.01:23:12.89#ibcon#about to write, iclass 31, count 2 2006.202.01:23:12.89#ibcon#wrote, iclass 31, count 2 2006.202.01:23:12.89#ibcon#about to read 3, iclass 31, count 2 2006.202.01:23:12.92#ibcon#read 3, iclass 31, count 2 2006.202.01:23:12.92#ibcon#about to read 4, iclass 31, count 2 2006.202.01:23:12.92#ibcon#read 4, iclass 31, count 2 2006.202.01:23:12.92#ibcon#about to read 5, iclass 31, count 2 2006.202.01:23:12.92#ibcon#read 5, iclass 31, count 2 2006.202.01:23:12.92#ibcon#about to read 6, iclass 31, count 2 2006.202.01:23:12.92#ibcon#read 6, iclass 31, count 2 2006.202.01:23:12.92#ibcon#end of sib2, iclass 31, count 2 2006.202.01:23:12.92#ibcon#*after write, iclass 31, count 2 2006.202.01:23:12.92#ibcon#*before return 0, iclass 31, count 2 2006.202.01:23:12.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:12.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:23:12.92#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.202.01:23:12.92#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:12.92#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:13.04#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:13.04#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:13.04#ibcon#enter wrdev, iclass 31, count 0 2006.202.01:23:13.04#ibcon#first serial, iclass 31, count 0 2006.202.01:23:13.04#ibcon#enter sib2, iclass 31, count 0 2006.202.01:23:13.04#ibcon#flushed, iclass 31, count 0 2006.202.01:23:13.04#ibcon#about to write, iclass 31, count 0 2006.202.01:23:13.04#ibcon#wrote, iclass 31, count 0 2006.202.01:23:13.04#ibcon#about to read 3, iclass 31, count 0 2006.202.01:23:13.06#ibcon#read 3, iclass 31, count 0 2006.202.01:23:13.06#ibcon#about to read 4, iclass 31, count 0 2006.202.01:23:13.06#ibcon#read 4, iclass 31, count 0 2006.202.01:23:13.06#ibcon#about to read 5, iclass 31, count 0 2006.202.01:23:13.06#ibcon#read 5, iclass 31, count 0 2006.202.01:23:13.06#ibcon#about to read 6, iclass 31, count 0 2006.202.01:23:13.06#ibcon#read 6, iclass 31, count 0 2006.202.01:23:13.06#ibcon#end of sib2, iclass 31, count 0 2006.202.01:23:13.06#ibcon#*mode == 0, iclass 31, count 0 2006.202.01:23:13.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.01:23:13.06#ibcon#[27=USB\r\n] 2006.202.01:23:13.06#ibcon#*before write, iclass 31, count 0 2006.202.01:23:13.06#ibcon#enter sib2, iclass 31, count 0 2006.202.01:23:13.06#ibcon#flushed, iclass 31, count 0 2006.202.01:23:13.06#ibcon#about to write, iclass 31, count 0 2006.202.01:23:13.06#ibcon#wrote, iclass 31, count 0 2006.202.01:23:13.06#ibcon#about to read 3, iclass 31, count 0 2006.202.01:23:13.09#ibcon#read 3, iclass 31, count 0 2006.202.01:23:13.09#ibcon#about to read 4, iclass 31, count 0 2006.202.01:23:13.09#ibcon#read 4, iclass 31, count 0 2006.202.01:23:13.09#ibcon#about to read 5, iclass 31, count 0 2006.202.01:23:13.09#ibcon#read 5, iclass 31, count 0 2006.202.01:23:13.09#ibcon#about to read 6, iclass 31, count 0 2006.202.01:23:13.09#ibcon#read 6, iclass 31, count 0 2006.202.01:23:13.09#ibcon#end of sib2, iclass 31, count 0 2006.202.01:23:13.09#ibcon#*after write, iclass 31, count 0 2006.202.01:23:13.09#ibcon#*before return 0, iclass 31, count 0 2006.202.01:23:13.09#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:13.09#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:23:13.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.01:23:13.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.01:23:13.09$vck44/vblo=4,679.99 2006.202.01:23:13.09#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.01:23:13.09#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.01:23:13.09#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:13.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:13.09#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:13.09#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:13.09#ibcon#enter wrdev, iclass 33, count 0 2006.202.01:23:13.09#ibcon#first serial, iclass 33, count 0 2006.202.01:23:13.09#ibcon#enter sib2, iclass 33, count 0 2006.202.01:23:13.09#ibcon#flushed, iclass 33, count 0 2006.202.01:23:13.09#ibcon#about to write, iclass 33, count 0 2006.202.01:23:13.09#ibcon#wrote, iclass 33, count 0 2006.202.01:23:13.09#ibcon#about to read 3, iclass 33, count 0 2006.202.01:23:13.11#ibcon#read 3, iclass 33, count 0 2006.202.01:23:13.11#ibcon#about to read 4, iclass 33, count 0 2006.202.01:23:13.11#ibcon#read 4, iclass 33, count 0 2006.202.01:23:13.11#ibcon#about to read 5, iclass 33, count 0 2006.202.01:23:13.11#ibcon#read 5, iclass 33, count 0 2006.202.01:23:13.11#ibcon#about to read 6, iclass 33, count 0 2006.202.01:23:13.11#ibcon#read 6, iclass 33, count 0 2006.202.01:23:13.11#ibcon#end of sib2, iclass 33, count 0 2006.202.01:23:13.11#ibcon#*mode == 0, iclass 33, count 0 2006.202.01:23:13.11#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.01:23:13.11#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.01:23:13.11#ibcon#*before write, iclass 33, count 0 2006.202.01:23:13.11#ibcon#enter sib2, iclass 33, count 0 2006.202.01:23:13.11#ibcon#flushed, iclass 33, count 0 2006.202.01:23:13.11#ibcon#about to write, iclass 33, count 0 2006.202.01:23:13.11#ibcon#wrote, iclass 33, count 0 2006.202.01:23:13.11#ibcon#about to read 3, iclass 33, count 0 2006.202.01:23:13.15#ibcon#read 3, iclass 33, count 0 2006.202.01:23:13.15#ibcon#about to read 4, iclass 33, count 0 2006.202.01:23:13.15#ibcon#read 4, iclass 33, count 0 2006.202.01:23:13.15#ibcon#about to read 5, iclass 33, count 0 2006.202.01:23:13.15#ibcon#read 5, iclass 33, count 0 2006.202.01:23:13.15#ibcon#about to read 6, iclass 33, count 0 2006.202.01:23:13.15#ibcon#read 6, iclass 33, count 0 2006.202.01:23:13.15#ibcon#end of sib2, iclass 33, count 0 2006.202.01:23:13.15#ibcon#*after write, iclass 33, count 0 2006.202.01:23:13.15#ibcon#*before return 0, iclass 33, count 0 2006.202.01:23:13.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:13.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:23:13.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.01:23:13.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.01:23:13.15$vck44/vb=4,5 2006.202.01:23:13.15#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.202.01:23:13.15#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.202.01:23:13.15#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:13.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:13.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:13.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:13.21#ibcon#enter wrdev, iclass 35, count 2 2006.202.01:23:13.21#ibcon#first serial, iclass 35, count 2 2006.202.01:23:13.21#ibcon#enter sib2, iclass 35, count 2 2006.202.01:23:13.21#ibcon#flushed, iclass 35, count 2 2006.202.01:23:13.21#ibcon#about to write, iclass 35, count 2 2006.202.01:23:13.21#ibcon#wrote, iclass 35, count 2 2006.202.01:23:13.21#ibcon#about to read 3, iclass 35, count 2 2006.202.01:23:13.23#ibcon#read 3, iclass 35, count 2 2006.202.01:23:13.23#ibcon#about to read 4, iclass 35, count 2 2006.202.01:23:13.23#ibcon#read 4, iclass 35, count 2 2006.202.01:23:13.23#ibcon#about to read 5, iclass 35, count 2 2006.202.01:23:13.23#ibcon#read 5, iclass 35, count 2 2006.202.01:23:13.23#ibcon#about to read 6, iclass 35, count 2 2006.202.01:23:13.23#ibcon#read 6, iclass 35, count 2 2006.202.01:23:13.23#ibcon#end of sib2, iclass 35, count 2 2006.202.01:23:13.23#ibcon#*mode == 0, iclass 35, count 2 2006.202.01:23:13.23#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.202.01:23:13.23#ibcon#[27=AT04-05\r\n] 2006.202.01:23:13.23#ibcon#*before write, iclass 35, count 2 2006.202.01:23:13.23#ibcon#enter sib2, iclass 35, count 2 2006.202.01:23:13.23#ibcon#flushed, iclass 35, count 2 2006.202.01:23:13.23#ibcon#about to write, iclass 35, count 2 2006.202.01:23:13.23#ibcon#wrote, iclass 35, count 2 2006.202.01:23:13.23#ibcon#about to read 3, iclass 35, count 2 2006.202.01:23:13.26#ibcon#read 3, iclass 35, count 2 2006.202.01:23:13.26#ibcon#about to read 4, iclass 35, count 2 2006.202.01:23:13.26#ibcon#read 4, iclass 35, count 2 2006.202.01:23:13.26#ibcon#about to read 5, iclass 35, count 2 2006.202.01:23:13.26#ibcon#read 5, iclass 35, count 2 2006.202.01:23:13.26#ibcon#about to read 6, iclass 35, count 2 2006.202.01:23:13.26#ibcon#read 6, iclass 35, count 2 2006.202.01:23:13.26#ibcon#end of sib2, iclass 35, count 2 2006.202.01:23:13.26#ibcon#*after write, iclass 35, count 2 2006.202.01:23:13.26#ibcon#*before return 0, iclass 35, count 2 2006.202.01:23:13.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:13.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:23:13.26#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.202.01:23:13.26#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:13.26#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:13.38#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:13.38#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:13.38#ibcon#enter wrdev, iclass 35, count 0 2006.202.01:23:13.38#ibcon#first serial, iclass 35, count 0 2006.202.01:23:13.38#ibcon#enter sib2, iclass 35, count 0 2006.202.01:23:13.38#ibcon#flushed, iclass 35, count 0 2006.202.01:23:13.38#ibcon#about to write, iclass 35, count 0 2006.202.01:23:13.38#ibcon#wrote, iclass 35, count 0 2006.202.01:23:13.38#ibcon#about to read 3, iclass 35, count 0 2006.202.01:23:13.40#ibcon#read 3, iclass 35, count 0 2006.202.01:23:13.40#ibcon#about to read 4, iclass 35, count 0 2006.202.01:23:13.40#ibcon#read 4, iclass 35, count 0 2006.202.01:23:13.40#ibcon#about to read 5, iclass 35, count 0 2006.202.01:23:13.40#ibcon#read 5, iclass 35, count 0 2006.202.01:23:13.40#ibcon#about to read 6, iclass 35, count 0 2006.202.01:23:13.40#ibcon#read 6, iclass 35, count 0 2006.202.01:23:13.40#ibcon#end of sib2, iclass 35, count 0 2006.202.01:23:13.40#ibcon#*mode == 0, iclass 35, count 0 2006.202.01:23:13.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.01:23:13.40#ibcon#[27=USB\r\n] 2006.202.01:23:13.40#ibcon#*before write, iclass 35, count 0 2006.202.01:23:13.40#ibcon#enter sib2, iclass 35, count 0 2006.202.01:23:13.40#ibcon#flushed, iclass 35, count 0 2006.202.01:23:13.40#ibcon#about to write, iclass 35, count 0 2006.202.01:23:13.40#ibcon#wrote, iclass 35, count 0 2006.202.01:23:13.40#ibcon#about to read 3, iclass 35, count 0 2006.202.01:23:13.43#ibcon#read 3, iclass 35, count 0 2006.202.01:23:13.43#ibcon#about to read 4, iclass 35, count 0 2006.202.01:23:13.43#ibcon#read 4, iclass 35, count 0 2006.202.01:23:13.43#ibcon#about to read 5, iclass 35, count 0 2006.202.01:23:13.43#ibcon#read 5, iclass 35, count 0 2006.202.01:23:13.43#ibcon#about to read 6, iclass 35, count 0 2006.202.01:23:13.43#ibcon#read 6, iclass 35, count 0 2006.202.01:23:13.43#ibcon#end of sib2, iclass 35, count 0 2006.202.01:23:13.43#ibcon#*after write, iclass 35, count 0 2006.202.01:23:13.43#ibcon#*before return 0, iclass 35, count 0 2006.202.01:23:13.43#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:13.43#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:23:13.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.01:23:13.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.01:23:13.43$vck44/vblo=5,709.99 2006.202.01:23:13.43#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.202.01:23:13.43#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.202.01:23:13.43#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:13.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:13.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:13.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:13.43#ibcon#enter wrdev, iclass 37, count 0 2006.202.01:23:13.43#ibcon#first serial, iclass 37, count 0 2006.202.01:23:13.43#ibcon#enter sib2, iclass 37, count 0 2006.202.01:23:13.43#ibcon#flushed, iclass 37, count 0 2006.202.01:23:13.43#ibcon#about to write, iclass 37, count 0 2006.202.01:23:13.43#ibcon#wrote, iclass 37, count 0 2006.202.01:23:13.43#ibcon#about to read 3, iclass 37, count 0 2006.202.01:23:13.45#ibcon#read 3, iclass 37, count 0 2006.202.01:23:13.45#ibcon#about to read 4, iclass 37, count 0 2006.202.01:23:13.45#ibcon#read 4, iclass 37, count 0 2006.202.01:23:13.45#ibcon#about to read 5, iclass 37, count 0 2006.202.01:23:13.45#ibcon#read 5, iclass 37, count 0 2006.202.01:23:13.45#ibcon#about to read 6, iclass 37, count 0 2006.202.01:23:13.45#ibcon#read 6, iclass 37, count 0 2006.202.01:23:13.45#ibcon#end of sib2, iclass 37, count 0 2006.202.01:23:13.45#ibcon#*mode == 0, iclass 37, count 0 2006.202.01:23:13.45#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.01:23:13.45#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.01:23:13.45#ibcon#*before write, iclass 37, count 0 2006.202.01:23:13.45#ibcon#enter sib2, iclass 37, count 0 2006.202.01:23:13.45#ibcon#flushed, iclass 37, count 0 2006.202.01:23:13.45#ibcon#about to write, iclass 37, count 0 2006.202.01:23:13.45#ibcon#wrote, iclass 37, count 0 2006.202.01:23:13.45#ibcon#about to read 3, iclass 37, count 0 2006.202.01:23:13.48#abcon#<5=/04 2.3 5.3 20.541001000.7\r\n> 2006.202.01:23:13.49#ibcon#read 3, iclass 37, count 0 2006.202.01:23:13.49#ibcon#about to read 4, iclass 37, count 0 2006.202.01:23:13.49#ibcon#read 4, iclass 37, count 0 2006.202.01:23:13.49#ibcon#about to read 5, iclass 37, count 0 2006.202.01:23:13.49#ibcon#read 5, iclass 37, count 0 2006.202.01:23:13.49#ibcon#about to read 6, iclass 37, count 0 2006.202.01:23:13.49#ibcon#read 6, iclass 37, count 0 2006.202.01:23:13.49#ibcon#end of sib2, iclass 37, count 0 2006.202.01:23:13.49#ibcon#*after write, iclass 37, count 0 2006.202.01:23:13.49#ibcon#*before return 0, iclass 37, count 0 2006.202.01:23:13.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:13.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:23:13.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.01:23:13.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.01:23:13.49$vck44/vb=5,4 2006.202.01:23:13.49#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.202.01:23:13.49#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.202.01:23:13.49#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:13.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:23:13.50#abcon#{5=INTERFACE CLEAR} 2006.202.01:23:13.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:23:13.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:23:13.55#ibcon#enter wrdev, iclass 4, count 2 2006.202.01:23:13.55#ibcon#first serial, iclass 4, count 2 2006.202.01:23:13.55#ibcon#enter sib2, iclass 4, count 2 2006.202.01:23:13.55#ibcon#flushed, iclass 4, count 2 2006.202.01:23:13.55#ibcon#about to write, iclass 4, count 2 2006.202.01:23:13.55#ibcon#wrote, iclass 4, count 2 2006.202.01:23:13.55#ibcon#about to read 3, iclass 4, count 2 2006.202.01:23:13.56#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:23:13.57#ibcon#read 3, iclass 4, count 2 2006.202.01:23:13.57#ibcon#about to read 4, iclass 4, count 2 2006.202.01:23:13.57#ibcon#read 4, iclass 4, count 2 2006.202.01:23:13.57#ibcon#about to read 5, iclass 4, count 2 2006.202.01:23:13.57#ibcon#read 5, iclass 4, count 2 2006.202.01:23:13.57#ibcon#about to read 6, iclass 4, count 2 2006.202.01:23:13.57#ibcon#read 6, iclass 4, count 2 2006.202.01:23:13.57#ibcon#end of sib2, iclass 4, count 2 2006.202.01:23:13.57#ibcon#*mode == 0, iclass 4, count 2 2006.202.01:23:13.57#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.202.01:23:13.57#ibcon#[27=AT05-04\r\n] 2006.202.01:23:13.57#ibcon#*before write, iclass 4, count 2 2006.202.01:23:13.57#ibcon#enter sib2, iclass 4, count 2 2006.202.01:23:13.57#ibcon#flushed, iclass 4, count 2 2006.202.01:23:13.57#ibcon#about to write, iclass 4, count 2 2006.202.01:23:13.57#ibcon#wrote, iclass 4, count 2 2006.202.01:23:13.57#ibcon#about to read 3, iclass 4, count 2 2006.202.01:23:13.60#ibcon#read 3, iclass 4, count 2 2006.202.01:23:13.60#ibcon#about to read 4, iclass 4, count 2 2006.202.01:23:13.60#ibcon#read 4, iclass 4, count 2 2006.202.01:23:13.60#ibcon#about to read 5, iclass 4, count 2 2006.202.01:23:13.60#ibcon#read 5, iclass 4, count 2 2006.202.01:23:13.60#ibcon#about to read 6, iclass 4, count 2 2006.202.01:23:13.60#ibcon#read 6, iclass 4, count 2 2006.202.01:23:13.60#ibcon#end of sib2, iclass 4, count 2 2006.202.01:23:13.60#ibcon#*after write, iclass 4, count 2 2006.202.01:23:13.60#ibcon#*before return 0, iclass 4, count 2 2006.202.01:23:13.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:23:13.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:23:13.60#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.202.01:23:13.60#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:13.60#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:23:13.72#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:23:13.72#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:23:13.72#ibcon#enter wrdev, iclass 4, count 0 2006.202.01:23:13.72#ibcon#first serial, iclass 4, count 0 2006.202.01:23:13.72#ibcon#enter sib2, iclass 4, count 0 2006.202.01:23:13.72#ibcon#flushed, iclass 4, count 0 2006.202.01:23:13.72#ibcon#about to write, iclass 4, count 0 2006.202.01:23:13.72#ibcon#wrote, iclass 4, count 0 2006.202.01:23:13.72#ibcon#about to read 3, iclass 4, count 0 2006.202.01:23:13.74#ibcon#read 3, iclass 4, count 0 2006.202.01:23:13.74#ibcon#about to read 4, iclass 4, count 0 2006.202.01:23:13.74#ibcon#read 4, iclass 4, count 0 2006.202.01:23:13.74#ibcon#about to read 5, iclass 4, count 0 2006.202.01:23:13.74#ibcon#read 5, iclass 4, count 0 2006.202.01:23:13.74#ibcon#about to read 6, iclass 4, count 0 2006.202.01:23:13.74#ibcon#read 6, iclass 4, count 0 2006.202.01:23:13.74#ibcon#end of sib2, iclass 4, count 0 2006.202.01:23:13.74#ibcon#*mode == 0, iclass 4, count 0 2006.202.01:23:13.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.01:23:13.74#ibcon#[27=USB\r\n] 2006.202.01:23:13.74#ibcon#*before write, iclass 4, count 0 2006.202.01:23:13.74#ibcon#enter sib2, iclass 4, count 0 2006.202.01:23:13.74#ibcon#flushed, iclass 4, count 0 2006.202.01:23:13.74#ibcon#about to write, iclass 4, count 0 2006.202.01:23:13.74#ibcon#wrote, iclass 4, count 0 2006.202.01:23:13.74#ibcon#about to read 3, iclass 4, count 0 2006.202.01:23:13.77#ibcon#read 3, iclass 4, count 0 2006.202.01:23:13.77#ibcon#about to read 4, iclass 4, count 0 2006.202.01:23:13.77#ibcon#read 4, iclass 4, count 0 2006.202.01:23:13.77#ibcon#about to read 5, iclass 4, count 0 2006.202.01:23:13.77#ibcon#read 5, iclass 4, count 0 2006.202.01:23:13.77#ibcon#about to read 6, iclass 4, count 0 2006.202.01:23:13.77#ibcon#read 6, iclass 4, count 0 2006.202.01:23:13.77#ibcon#end of sib2, iclass 4, count 0 2006.202.01:23:13.77#ibcon#*after write, iclass 4, count 0 2006.202.01:23:13.77#ibcon#*before return 0, iclass 4, count 0 2006.202.01:23:13.77#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:23:13.77#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:23:13.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.01:23:13.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.01:23:13.77$vck44/vblo=6,719.99 2006.202.01:23:13.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.01:23:13.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.01:23:13.77#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:13.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:13.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:13.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:13.77#ibcon#enter wrdev, iclass 7, count 0 2006.202.01:23:13.77#ibcon#first serial, iclass 7, count 0 2006.202.01:23:13.77#ibcon#enter sib2, iclass 7, count 0 2006.202.01:23:13.77#ibcon#flushed, iclass 7, count 0 2006.202.01:23:13.77#ibcon#about to write, iclass 7, count 0 2006.202.01:23:13.77#ibcon#wrote, iclass 7, count 0 2006.202.01:23:13.77#ibcon#about to read 3, iclass 7, count 0 2006.202.01:23:13.79#ibcon#read 3, iclass 7, count 0 2006.202.01:23:13.79#ibcon#about to read 4, iclass 7, count 0 2006.202.01:23:13.79#ibcon#read 4, iclass 7, count 0 2006.202.01:23:13.79#ibcon#about to read 5, iclass 7, count 0 2006.202.01:23:13.79#ibcon#read 5, iclass 7, count 0 2006.202.01:23:13.79#ibcon#about to read 6, iclass 7, count 0 2006.202.01:23:13.79#ibcon#read 6, iclass 7, count 0 2006.202.01:23:13.79#ibcon#end of sib2, iclass 7, count 0 2006.202.01:23:13.79#ibcon#*mode == 0, iclass 7, count 0 2006.202.01:23:13.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.01:23:13.79#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.01:23:13.79#ibcon#*before write, iclass 7, count 0 2006.202.01:23:13.79#ibcon#enter sib2, iclass 7, count 0 2006.202.01:23:13.79#ibcon#flushed, iclass 7, count 0 2006.202.01:23:13.79#ibcon#about to write, iclass 7, count 0 2006.202.01:23:13.79#ibcon#wrote, iclass 7, count 0 2006.202.01:23:13.79#ibcon#about to read 3, iclass 7, count 0 2006.202.01:23:13.83#ibcon#read 3, iclass 7, count 0 2006.202.01:23:13.83#ibcon#about to read 4, iclass 7, count 0 2006.202.01:23:13.83#ibcon#read 4, iclass 7, count 0 2006.202.01:23:13.83#ibcon#about to read 5, iclass 7, count 0 2006.202.01:23:13.83#ibcon#read 5, iclass 7, count 0 2006.202.01:23:13.83#ibcon#about to read 6, iclass 7, count 0 2006.202.01:23:13.83#ibcon#read 6, iclass 7, count 0 2006.202.01:23:13.83#ibcon#end of sib2, iclass 7, count 0 2006.202.01:23:13.83#ibcon#*after write, iclass 7, count 0 2006.202.01:23:13.83#ibcon#*before return 0, iclass 7, count 0 2006.202.01:23:13.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:13.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:23:13.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.01:23:13.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.01:23:13.83$vck44/vb=6,4 2006.202.01:23:13.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.202.01:23:13.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.202.01:23:13.83#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:13.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:13.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:13.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:13.89#ibcon#enter wrdev, iclass 11, count 2 2006.202.01:23:13.89#ibcon#first serial, iclass 11, count 2 2006.202.01:23:13.89#ibcon#enter sib2, iclass 11, count 2 2006.202.01:23:13.89#ibcon#flushed, iclass 11, count 2 2006.202.01:23:13.89#ibcon#about to write, iclass 11, count 2 2006.202.01:23:13.89#ibcon#wrote, iclass 11, count 2 2006.202.01:23:13.89#ibcon#about to read 3, iclass 11, count 2 2006.202.01:23:13.91#ibcon#read 3, iclass 11, count 2 2006.202.01:23:13.91#ibcon#about to read 4, iclass 11, count 2 2006.202.01:23:13.91#ibcon#read 4, iclass 11, count 2 2006.202.01:23:13.91#ibcon#about to read 5, iclass 11, count 2 2006.202.01:23:13.91#ibcon#read 5, iclass 11, count 2 2006.202.01:23:13.91#ibcon#about to read 6, iclass 11, count 2 2006.202.01:23:13.91#ibcon#read 6, iclass 11, count 2 2006.202.01:23:13.91#ibcon#end of sib2, iclass 11, count 2 2006.202.01:23:13.91#ibcon#*mode == 0, iclass 11, count 2 2006.202.01:23:13.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.202.01:23:13.91#ibcon#[27=AT06-04\r\n] 2006.202.01:23:13.91#ibcon#*before write, iclass 11, count 2 2006.202.01:23:13.91#ibcon#enter sib2, iclass 11, count 2 2006.202.01:23:13.91#ibcon#flushed, iclass 11, count 2 2006.202.01:23:13.91#ibcon#about to write, iclass 11, count 2 2006.202.01:23:13.91#ibcon#wrote, iclass 11, count 2 2006.202.01:23:13.91#ibcon#about to read 3, iclass 11, count 2 2006.202.01:23:14.06#ibcon#read 3, iclass 11, count 2 2006.202.01:23:14.06#ibcon#about to read 4, iclass 11, count 2 2006.202.01:23:14.06#ibcon#read 4, iclass 11, count 2 2006.202.01:23:14.06#ibcon#about to read 5, iclass 11, count 2 2006.202.01:23:14.06#ibcon#read 5, iclass 11, count 2 2006.202.01:23:14.06#ibcon#about to read 6, iclass 11, count 2 2006.202.01:23:14.06#ibcon#read 6, iclass 11, count 2 2006.202.01:23:14.06#ibcon#end of sib2, iclass 11, count 2 2006.202.01:23:14.06#ibcon#*after write, iclass 11, count 2 2006.202.01:23:14.06#ibcon#*before return 0, iclass 11, count 2 2006.202.01:23:14.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:14.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:23:14.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.202.01:23:14.06#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:14.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:14.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:14.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:14.19#ibcon#enter wrdev, iclass 11, count 0 2006.202.01:23:14.19#ibcon#first serial, iclass 11, count 0 2006.202.01:23:14.19#ibcon#enter sib2, iclass 11, count 0 2006.202.01:23:14.19#ibcon#flushed, iclass 11, count 0 2006.202.01:23:14.19#ibcon#about to write, iclass 11, count 0 2006.202.01:23:14.19#ibcon#wrote, iclass 11, count 0 2006.202.01:23:14.19#ibcon#about to read 3, iclass 11, count 0 2006.202.01:23:14.21#ibcon#read 3, iclass 11, count 0 2006.202.01:23:14.21#ibcon#about to read 4, iclass 11, count 0 2006.202.01:23:14.21#ibcon#read 4, iclass 11, count 0 2006.202.01:23:14.21#ibcon#about to read 5, iclass 11, count 0 2006.202.01:23:14.21#ibcon#read 5, iclass 11, count 0 2006.202.01:23:14.21#ibcon#about to read 6, iclass 11, count 0 2006.202.01:23:14.21#ibcon#read 6, iclass 11, count 0 2006.202.01:23:14.21#ibcon#end of sib2, iclass 11, count 0 2006.202.01:23:14.21#ibcon#*mode == 0, iclass 11, count 0 2006.202.01:23:14.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.01:23:14.21#ibcon#[27=USB\r\n] 2006.202.01:23:14.21#ibcon#*before write, iclass 11, count 0 2006.202.01:23:14.21#ibcon#enter sib2, iclass 11, count 0 2006.202.01:23:14.21#ibcon#flushed, iclass 11, count 0 2006.202.01:23:14.21#ibcon#about to write, iclass 11, count 0 2006.202.01:23:14.21#ibcon#wrote, iclass 11, count 0 2006.202.01:23:14.21#ibcon#about to read 3, iclass 11, count 0 2006.202.01:23:14.24#ibcon#read 3, iclass 11, count 0 2006.202.01:23:14.24#ibcon#about to read 4, iclass 11, count 0 2006.202.01:23:14.24#ibcon#read 4, iclass 11, count 0 2006.202.01:23:14.24#ibcon#about to read 5, iclass 11, count 0 2006.202.01:23:14.24#ibcon#read 5, iclass 11, count 0 2006.202.01:23:14.24#ibcon#about to read 6, iclass 11, count 0 2006.202.01:23:14.24#ibcon#read 6, iclass 11, count 0 2006.202.01:23:14.24#ibcon#end of sib2, iclass 11, count 0 2006.202.01:23:14.24#ibcon#*after write, iclass 11, count 0 2006.202.01:23:14.24#ibcon#*before return 0, iclass 11, count 0 2006.202.01:23:14.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:14.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:23:14.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.01:23:14.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.01:23:14.24$vck44/vblo=7,734.99 2006.202.01:23:14.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.202.01:23:14.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.202.01:23:14.24#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:14.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:14.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:14.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:14.24#ibcon#enter wrdev, iclass 13, count 0 2006.202.01:23:14.24#ibcon#first serial, iclass 13, count 0 2006.202.01:23:14.24#ibcon#enter sib2, iclass 13, count 0 2006.202.01:23:14.24#ibcon#flushed, iclass 13, count 0 2006.202.01:23:14.24#ibcon#about to write, iclass 13, count 0 2006.202.01:23:14.24#ibcon#wrote, iclass 13, count 0 2006.202.01:23:14.24#ibcon#about to read 3, iclass 13, count 0 2006.202.01:23:14.26#ibcon#read 3, iclass 13, count 0 2006.202.01:23:14.26#ibcon#about to read 4, iclass 13, count 0 2006.202.01:23:14.26#ibcon#read 4, iclass 13, count 0 2006.202.01:23:14.26#ibcon#about to read 5, iclass 13, count 0 2006.202.01:23:14.26#ibcon#read 5, iclass 13, count 0 2006.202.01:23:14.26#ibcon#about to read 6, iclass 13, count 0 2006.202.01:23:14.26#ibcon#read 6, iclass 13, count 0 2006.202.01:23:14.26#ibcon#end of sib2, iclass 13, count 0 2006.202.01:23:14.26#ibcon#*mode == 0, iclass 13, count 0 2006.202.01:23:14.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.01:23:14.26#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.01:23:14.26#ibcon#*before write, iclass 13, count 0 2006.202.01:23:14.26#ibcon#enter sib2, iclass 13, count 0 2006.202.01:23:14.26#ibcon#flushed, iclass 13, count 0 2006.202.01:23:14.26#ibcon#about to write, iclass 13, count 0 2006.202.01:23:14.26#ibcon#wrote, iclass 13, count 0 2006.202.01:23:14.26#ibcon#about to read 3, iclass 13, count 0 2006.202.01:23:14.30#ibcon#read 3, iclass 13, count 0 2006.202.01:23:14.30#ibcon#about to read 4, iclass 13, count 0 2006.202.01:23:14.30#ibcon#read 4, iclass 13, count 0 2006.202.01:23:14.30#ibcon#about to read 5, iclass 13, count 0 2006.202.01:23:14.30#ibcon#read 5, iclass 13, count 0 2006.202.01:23:14.30#ibcon#about to read 6, iclass 13, count 0 2006.202.01:23:14.30#ibcon#read 6, iclass 13, count 0 2006.202.01:23:14.30#ibcon#end of sib2, iclass 13, count 0 2006.202.01:23:14.30#ibcon#*after write, iclass 13, count 0 2006.202.01:23:14.30#ibcon#*before return 0, iclass 13, count 0 2006.202.01:23:14.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:14.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:23:14.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.01:23:14.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.01:23:14.30$vck44/vb=7,4 2006.202.01:23:14.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.202.01:23:14.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.202.01:23:14.30#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:14.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:14.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:14.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:14.36#ibcon#enter wrdev, iclass 15, count 2 2006.202.01:23:14.36#ibcon#first serial, iclass 15, count 2 2006.202.01:23:14.36#ibcon#enter sib2, iclass 15, count 2 2006.202.01:23:14.36#ibcon#flushed, iclass 15, count 2 2006.202.01:23:14.36#ibcon#about to write, iclass 15, count 2 2006.202.01:23:14.36#ibcon#wrote, iclass 15, count 2 2006.202.01:23:14.36#ibcon#about to read 3, iclass 15, count 2 2006.202.01:23:14.38#ibcon#read 3, iclass 15, count 2 2006.202.01:23:14.38#ibcon#about to read 4, iclass 15, count 2 2006.202.01:23:14.38#ibcon#read 4, iclass 15, count 2 2006.202.01:23:14.38#ibcon#about to read 5, iclass 15, count 2 2006.202.01:23:14.38#ibcon#read 5, iclass 15, count 2 2006.202.01:23:14.38#ibcon#about to read 6, iclass 15, count 2 2006.202.01:23:14.38#ibcon#read 6, iclass 15, count 2 2006.202.01:23:14.38#ibcon#end of sib2, iclass 15, count 2 2006.202.01:23:14.38#ibcon#*mode == 0, iclass 15, count 2 2006.202.01:23:14.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.202.01:23:14.38#ibcon#[27=AT07-04\r\n] 2006.202.01:23:14.38#ibcon#*before write, iclass 15, count 2 2006.202.01:23:14.38#ibcon#enter sib2, iclass 15, count 2 2006.202.01:23:14.38#ibcon#flushed, iclass 15, count 2 2006.202.01:23:14.38#ibcon#about to write, iclass 15, count 2 2006.202.01:23:14.38#ibcon#wrote, iclass 15, count 2 2006.202.01:23:14.38#ibcon#about to read 3, iclass 15, count 2 2006.202.01:23:14.41#ibcon#read 3, iclass 15, count 2 2006.202.01:23:14.41#ibcon#about to read 4, iclass 15, count 2 2006.202.01:23:14.41#ibcon#read 4, iclass 15, count 2 2006.202.01:23:14.41#ibcon#about to read 5, iclass 15, count 2 2006.202.01:23:14.41#ibcon#read 5, iclass 15, count 2 2006.202.01:23:14.41#ibcon#about to read 6, iclass 15, count 2 2006.202.01:23:14.41#ibcon#read 6, iclass 15, count 2 2006.202.01:23:14.41#ibcon#end of sib2, iclass 15, count 2 2006.202.01:23:14.41#ibcon#*after write, iclass 15, count 2 2006.202.01:23:14.41#ibcon#*before return 0, iclass 15, count 2 2006.202.01:23:14.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:14.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:23:14.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.202.01:23:14.41#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:14.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:14.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:14.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:14.53#ibcon#enter wrdev, iclass 15, count 0 2006.202.01:23:14.53#ibcon#first serial, iclass 15, count 0 2006.202.01:23:14.53#ibcon#enter sib2, iclass 15, count 0 2006.202.01:23:14.53#ibcon#flushed, iclass 15, count 0 2006.202.01:23:14.53#ibcon#about to write, iclass 15, count 0 2006.202.01:23:14.53#ibcon#wrote, iclass 15, count 0 2006.202.01:23:14.53#ibcon#about to read 3, iclass 15, count 0 2006.202.01:23:14.55#ibcon#read 3, iclass 15, count 0 2006.202.01:23:14.55#ibcon#about to read 4, iclass 15, count 0 2006.202.01:23:14.55#ibcon#read 4, iclass 15, count 0 2006.202.01:23:14.55#ibcon#about to read 5, iclass 15, count 0 2006.202.01:23:14.55#ibcon#read 5, iclass 15, count 0 2006.202.01:23:14.55#ibcon#about to read 6, iclass 15, count 0 2006.202.01:23:14.55#ibcon#read 6, iclass 15, count 0 2006.202.01:23:14.55#ibcon#end of sib2, iclass 15, count 0 2006.202.01:23:14.55#ibcon#*mode == 0, iclass 15, count 0 2006.202.01:23:14.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.01:23:14.55#ibcon#[27=USB\r\n] 2006.202.01:23:14.55#ibcon#*before write, iclass 15, count 0 2006.202.01:23:14.55#ibcon#enter sib2, iclass 15, count 0 2006.202.01:23:14.55#ibcon#flushed, iclass 15, count 0 2006.202.01:23:14.55#ibcon#about to write, iclass 15, count 0 2006.202.01:23:14.55#ibcon#wrote, iclass 15, count 0 2006.202.01:23:14.55#ibcon#about to read 3, iclass 15, count 0 2006.202.01:23:14.58#ibcon#read 3, iclass 15, count 0 2006.202.01:23:14.58#ibcon#about to read 4, iclass 15, count 0 2006.202.01:23:14.58#ibcon#read 4, iclass 15, count 0 2006.202.01:23:14.58#ibcon#about to read 5, iclass 15, count 0 2006.202.01:23:14.58#ibcon#read 5, iclass 15, count 0 2006.202.01:23:14.58#ibcon#about to read 6, iclass 15, count 0 2006.202.01:23:14.58#ibcon#read 6, iclass 15, count 0 2006.202.01:23:14.58#ibcon#end of sib2, iclass 15, count 0 2006.202.01:23:14.58#ibcon#*after write, iclass 15, count 0 2006.202.01:23:14.58#ibcon#*before return 0, iclass 15, count 0 2006.202.01:23:14.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:14.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:23:14.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.01:23:14.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.01:23:14.58$vck44/vblo=8,744.99 2006.202.01:23:14.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.01:23:14.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.01:23:14.58#ibcon#ireg 17 cls_cnt 0 2006.202.01:23:14.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:14.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:14.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:14.58#ibcon#enter wrdev, iclass 17, count 0 2006.202.01:23:14.58#ibcon#first serial, iclass 17, count 0 2006.202.01:23:14.58#ibcon#enter sib2, iclass 17, count 0 2006.202.01:23:14.58#ibcon#flushed, iclass 17, count 0 2006.202.01:23:14.58#ibcon#about to write, iclass 17, count 0 2006.202.01:23:14.58#ibcon#wrote, iclass 17, count 0 2006.202.01:23:14.58#ibcon#about to read 3, iclass 17, count 0 2006.202.01:23:14.60#ibcon#read 3, iclass 17, count 0 2006.202.01:23:14.60#ibcon#about to read 4, iclass 17, count 0 2006.202.01:23:14.60#ibcon#read 4, iclass 17, count 0 2006.202.01:23:14.60#ibcon#about to read 5, iclass 17, count 0 2006.202.01:23:14.60#ibcon#read 5, iclass 17, count 0 2006.202.01:23:14.60#ibcon#about to read 6, iclass 17, count 0 2006.202.01:23:14.60#ibcon#read 6, iclass 17, count 0 2006.202.01:23:14.60#ibcon#end of sib2, iclass 17, count 0 2006.202.01:23:14.60#ibcon#*mode == 0, iclass 17, count 0 2006.202.01:23:14.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.01:23:14.60#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.01:23:14.60#ibcon#*before write, iclass 17, count 0 2006.202.01:23:14.60#ibcon#enter sib2, iclass 17, count 0 2006.202.01:23:14.60#ibcon#flushed, iclass 17, count 0 2006.202.01:23:14.60#ibcon#about to write, iclass 17, count 0 2006.202.01:23:14.60#ibcon#wrote, iclass 17, count 0 2006.202.01:23:14.60#ibcon#about to read 3, iclass 17, count 0 2006.202.01:23:14.64#ibcon#read 3, iclass 17, count 0 2006.202.01:23:14.64#ibcon#about to read 4, iclass 17, count 0 2006.202.01:23:14.64#ibcon#read 4, iclass 17, count 0 2006.202.01:23:14.64#ibcon#about to read 5, iclass 17, count 0 2006.202.01:23:14.64#ibcon#read 5, iclass 17, count 0 2006.202.01:23:14.64#ibcon#about to read 6, iclass 17, count 0 2006.202.01:23:14.64#ibcon#read 6, iclass 17, count 0 2006.202.01:23:14.64#ibcon#end of sib2, iclass 17, count 0 2006.202.01:23:14.64#ibcon#*after write, iclass 17, count 0 2006.202.01:23:14.64#ibcon#*before return 0, iclass 17, count 0 2006.202.01:23:14.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:14.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:23:14.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.01:23:14.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.01:23:14.64$vck44/vb=8,4 2006.202.01:23:14.64#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.202.01:23:14.64#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.202.01:23:14.64#ibcon#ireg 11 cls_cnt 2 2006.202.01:23:14.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:14.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:14.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:14.70#ibcon#enter wrdev, iclass 19, count 2 2006.202.01:23:14.70#ibcon#first serial, iclass 19, count 2 2006.202.01:23:14.70#ibcon#enter sib2, iclass 19, count 2 2006.202.01:23:14.70#ibcon#flushed, iclass 19, count 2 2006.202.01:23:14.70#ibcon#about to write, iclass 19, count 2 2006.202.01:23:14.70#ibcon#wrote, iclass 19, count 2 2006.202.01:23:14.70#ibcon#about to read 3, iclass 19, count 2 2006.202.01:23:14.72#ibcon#read 3, iclass 19, count 2 2006.202.01:23:14.72#ibcon#about to read 4, iclass 19, count 2 2006.202.01:23:14.72#ibcon#read 4, iclass 19, count 2 2006.202.01:23:14.72#ibcon#about to read 5, iclass 19, count 2 2006.202.01:23:14.72#ibcon#read 5, iclass 19, count 2 2006.202.01:23:14.72#ibcon#about to read 6, iclass 19, count 2 2006.202.01:23:14.72#ibcon#read 6, iclass 19, count 2 2006.202.01:23:14.72#ibcon#end of sib2, iclass 19, count 2 2006.202.01:23:14.72#ibcon#*mode == 0, iclass 19, count 2 2006.202.01:23:14.72#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.202.01:23:14.72#ibcon#[27=AT08-04\r\n] 2006.202.01:23:14.72#ibcon#*before write, iclass 19, count 2 2006.202.01:23:14.72#ibcon#enter sib2, iclass 19, count 2 2006.202.01:23:14.72#ibcon#flushed, iclass 19, count 2 2006.202.01:23:14.72#ibcon#about to write, iclass 19, count 2 2006.202.01:23:14.72#ibcon#wrote, iclass 19, count 2 2006.202.01:23:14.72#ibcon#about to read 3, iclass 19, count 2 2006.202.01:23:14.75#ibcon#read 3, iclass 19, count 2 2006.202.01:23:14.75#ibcon#about to read 4, iclass 19, count 2 2006.202.01:23:14.75#ibcon#read 4, iclass 19, count 2 2006.202.01:23:14.75#ibcon#about to read 5, iclass 19, count 2 2006.202.01:23:14.75#ibcon#read 5, iclass 19, count 2 2006.202.01:23:14.75#ibcon#about to read 6, iclass 19, count 2 2006.202.01:23:14.75#ibcon#read 6, iclass 19, count 2 2006.202.01:23:14.75#ibcon#end of sib2, iclass 19, count 2 2006.202.01:23:14.75#ibcon#*after write, iclass 19, count 2 2006.202.01:23:14.75#ibcon#*before return 0, iclass 19, count 2 2006.202.01:23:14.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:14.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:23:14.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.202.01:23:14.75#ibcon#ireg 7 cls_cnt 0 2006.202.01:23:14.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:14.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:14.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:14.87#ibcon#enter wrdev, iclass 19, count 0 2006.202.01:23:14.87#ibcon#first serial, iclass 19, count 0 2006.202.01:23:14.87#ibcon#enter sib2, iclass 19, count 0 2006.202.01:23:14.87#ibcon#flushed, iclass 19, count 0 2006.202.01:23:14.87#ibcon#about to write, iclass 19, count 0 2006.202.01:23:14.87#ibcon#wrote, iclass 19, count 0 2006.202.01:23:14.87#ibcon#about to read 3, iclass 19, count 0 2006.202.01:23:14.89#ibcon#read 3, iclass 19, count 0 2006.202.01:23:14.89#ibcon#about to read 4, iclass 19, count 0 2006.202.01:23:14.89#ibcon#read 4, iclass 19, count 0 2006.202.01:23:14.89#ibcon#about to read 5, iclass 19, count 0 2006.202.01:23:14.89#ibcon#read 5, iclass 19, count 0 2006.202.01:23:14.89#ibcon#about to read 6, iclass 19, count 0 2006.202.01:23:14.89#ibcon#read 6, iclass 19, count 0 2006.202.01:23:14.89#ibcon#end of sib2, iclass 19, count 0 2006.202.01:23:14.89#ibcon#*mode == 0, iclass 19, count 0 2006.202.01:23:14.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.01:23:14.89#ibcon#[27=USB\r\n] 2006.202.01:23:14.89#ibcon#*before write, iclass 19, count 0 2006.202.01:23:14.89#ibcon#enter sib2, iclass 19, count 0 2006.202.01:23:14.89#ibcon#flushed, iclass 19, count 0 2006.202.01:23:14.89#ibcon#about to write, iclass 19, count 0 2006.202.01:23:14.89#ibcon#wrote, iclass 19, count 0 2006.202.01:23:14.89#ibcon#about to read 3, iclass 19, count 0 2006.202.01:23:14.92#ibcon#read 3, iclass 19, count 0 2006.202.01:23:14.92#ibcon#about to read 4, iclass 19, count 0 2006.202.01:23:14.92#ibcon#read 4, iclass 19, count 0 2006.202.01:23:14.92#ibcon#about to read 5, iclass 19, count 0 2006.202.01:23:14.92#ibcon#read 5, iclass 19, count 0 2006.202.01:23:14.92#ibcon#about to read 6, iclass 19, count 0 2006.202.01:23:14.92#ibcon#read 6, iclass 19, count 0 2006.202.01:23:14.92#ibcon#end of sib2, iclass 19, count 0 2006.202.01:23:14.92#ibcon#*after write, iclass 19, count 0 2006.202.01:23:14.92#ibcon#*before return 0, iclass 19, count 0 2006.202.01:23:14.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:14.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:23:14.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.01:23:14.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.01:23:14.92$vck44/vabw=wide 2006.202.01:23:14.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.202.01:23:14.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.202.01:23:14.92#ibcon#ireg 8 cls_cnt 0 2006.202.01:23:14.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:14.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:14.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:14.92#ibcon#enter wrdev, iclass 21, count 0 2006.202.01:23:14.92#ibcon#first serial, iclass 21, count 0 2006.202.01:23:14.92#ibcon#enter sib2, iclass 21, count 0 2006.202.01:23:14.92#ibcon#flushed, iclass 21, count 0 2006.202.01:23:14.92#ibcon#about to write, iclass 21, count 0 2006.202.01:23:14.92#ibcon#wrote, iclass 21, count 0 2006.202.01:23:14.92#ibcon#about to read 3, iclass 21, count 0 2006.202.01:23:14.94#ibcon#read 3, iclass 21, count 0 2006.202.01:23:14.94#ibcon#about to read 4, iclass 21, count 0 2006.202.01:23:14.94#ibcon#read 4, iclass 21, count 0 2006.202.01:23:14.94#ibcon#about to read 5, iclass 21, count 0 2006.202.01:23:14.94#ibcon#read 5, iclass 21, count 0 2006.202.01:23:14.94#ibcon#about to read 6, iclass 21, count 0 2006.202.01:23:14.94#ibcon#read 6, iclass 21, count 0 2006.202.01:23:14.94#ibcon#end of sib2, iclass 21, count 0 2006.202.01:23:14.94#ibcon#*mode == 0, iclass 21, count 0 2006.202.01:23:14.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.01:23:14.94#ibcon#[25=BW32\r\n] 2006.202.01:23:14.94#ibcon#*before write, iclass 21, count 0 2006.202.01:23:14.94#ibcon#enter sib2, iclass 21, count 0 2006.202.01:23:14.94#ibcon#flushed, iclass 21, count 0 2006.202.01:23:14.94#ibcon#about to write, iclass 21, count 0 2006.202.01:23:14.94#ibcon#wrote, iclass 21, count 0 2006.202.01:23:14.94#ibcon#about to read 3, iclass 21, count 0 2006.202.01:23:14.97#ibcon#read 3, iclass 21, count 0 2006.202.01:23:14.97#ibcon#about to read 4, iclass 21, count 0 2006.202.01:23:14.97#ibcon#read 4, iclass 21, count 0 2006.202.01:23:14.97#ibcon#about to read 5, iclass 21, count 0 2006.202.01:23:14.97#ibcon#read 5, iclass 21, count 0 2006.202.01:23:14.97#ibcon#about to read 6, iclass 21, count 0 2006.202.01:23:14.97#ibcon#read 6, iclass 21, count 0 2006.202.01:23:14.97#ibcon#end of sib2, iclass 21, count 0 2006.202.01:23:14.97#ibcon#*after write, iclass 21, count 0 2006.202.01:23:14.97#ibcon#*before return 0, iclass 21, count 0 2006.202.01:23:14.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:14.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:23:14.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.01:23:14.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.01:23:14.97$vck44/vbbw=wide 2006.202.01:23:14.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.01:23:14.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.01:23:14.97#ibcon#ireg 8 cls_cnt 0 2006.202.01:23:14.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:23:15.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:23:15.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:23:15.04#ibcon#enter wrdev, iclass 23, count 0 2006.202.01:23:15.04#ibcon#first serial, iclass 23, count 0 2006.202.01:23:15.04#ibcon#enter sib2, iclass 23, count 0 2006.202.01:23:15.04#ibcon#flushed, iclass 23, count 0 2006.202.01:23:15.04#ibcon#about to write, iclass 23, count 0 2006.202.01:23:15.04#ibcon#wrote, iclass 23, count 0 2006.202.01:23:15.04#ibcon#about to read 3, iclass 23, count 0 2006.202.01:23:15.06#ibcon#read 3, iclass 23, count 0 2006.202.01:23:15.06#ibcon#about to read 4, iclass 23, count 0 2006.202.01:23:15.06#ibcon#read 4, iclass 23, count 0 2006.202.01:23:15.06#ibcon#about to read 5, iclass 23, count 0 2006.202.01:23:15.06#ibcon#read 5, iclass 23, count 0 2006.202.01:23:15.06#ibcon#about to read 6, iclass 23, count 0 2006.202.01:23:15.06#ibcon#read 6, iclass 23, count 0 2006.202.01:23:15.06#ibcon#end of sib2, iclass 23, count 0 2006.202.01:23:15.06#ibcon#*mode == 0, iclass 23, count 0 2006.202.01:23:15.06#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.01:23:15.06#ibcon#[27=BW32\r\n] 2006.202.01:23:15.06#ibcon#*before write, iclass 23, count 0 2006.202.01:23:15.06#ibcon#enter sib2, iclass 23, count 0 2006.202.01:23:15.06#ibcon#flushed, iclass 23, count 0 2006.202.01:23:15.06#ibcon#about to write, iclass 23, count 0 2006.202.01:23:15.06#ibcon#wrote, iclass 23, count 0 2006.202.01:23:15.06#ibcon#about to read 3, iclass 23, count 0 2006.202.01:23:15.09#ibcon#read 3, iclass 23, count 0 2006.202.01:23:15.09#ibcon#about to read 4, iclass 23, count 0 2006.202.01:23:15.09#ibcon#read 4, iclass 23, count 0 2006.202.01:23:15.09#ibcon#about to read 5, iclass 23, count 0 2006.202.01:23:15.09#ibcon#read 5, iclass 23, count 0 2006.202.01:23:15.09#ibcon#about to read 6, iclass 23, count 0 2006.202.01:23:15.09#ibcon#read 6, iclass 23, count 0 2006.202.01:23:15.09#ibcon#end of sib2, iclass 23, count 0 2006.202.01:23:15.09#ibcon#*after write, iclass 23, count 0 2006.202.01:23:15.23#ibcon#*before return 0, iclass 23, count 0 2006.202.01:23:15.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:23:15.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:23:15.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.01:23:15.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.01:23:15.23$setupk4/ifdk4 2006.202.01:23:15.23$ifdk4/lo= 2006.202.01:23:15.23$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.01:23:15.23$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.01:23:15.23$ifdk4/patch= 2006.202.01:23:15.23$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.01:23:15.23$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.01:23:15.23$setupk4/!*+20s 2006.202.01:23:23.65#abcon#<5=/04 2.3 5.3 20.541001000.7\r\n> 2006.202.01:23:23.67#abcon#{5=INTERFACE CLEAR} 2006.202.01:23:23.73#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:23:29.24$setupk4/"tpicd 2006.202.01:23:29.24$setupk4/echo=off 2006.202.01:23:29.24$setupk4/xlog=off 2006.202.01:23:29.24:!2006.202.01:24:38 2006.202.01:23:38.13#trakl#Source acquired 2006.202.01:23:40.13#flagr#flagr/antenna,acquired 2006.202.01:24:38.00:preob 2006.202.01:24:38.14/onsource/TRACKING 2006.202.01:24:38.14:!2006.202.01:24:48 2006.202.01:24:48.00:"tape 2006.202.01:24:48.00:"st=record 2006.202.01:24:48.00:data_valid=on 2006.202.01:24:48.00:midob 2006.202.01:24:49.14/onsource/TRACKING 2006.202.01:24:49.14/wx/20.55,1000.7,100 2006.202.01:24:49.22/cable/+6.4851E-03 2006.202.01:24:50.31/va/01,08,usb,yes,36,39 2006.202.01:24:50.31/va/02,07,usb,yes,39,40 2006.202.01:24:50.31/va/03,08,usb,yes,35,37 2006.202.01:24:50.31/va/04,07,usb,yes,40,42 2006.202.01:24:50.31/va/05,04,usb,yes,36,36 2006.202.01:24:50.31/va/06,05,usb,yes,36,36 2006.202.01:24:50.31/va/07,05,usb,yes,35,36 2006.202.01:24:50.31/va/08,04,usb,yes,35,41 2006.202.01:24:50.54/valo/01,524.99,yes,locked 2006.202.01:24:50.54/valo/02,534.99,yes,locked 2006.202.01:24:50.54/valo/03,564.99,yes,locked 2006.202.01:24:50.54/valo/04,624.99,yes,locked 2006.202.01:24:50.54/valo/05,734.99,yes,locked 2006.202.01:24:50.54/valo/06,814.99,yes,locked 2006.202.01:24:50.54/valo/07,864.99,yes,locked 2006.202.01:24:50.54/valo/08,884.99,yes,locked 2006.202.01:24:51.63/vb/01,04,usb,yes,29,27 2006.202.01:24:51.63/vb/02,05,usb,yes,27,28 2006.202.01:24:51.63/vb/03,04,usb,yes,28,31 2006.202.01:24:51.63/vb/04,05,usb,yes,29,28 2006.202.01:24:51.63/vb/05,04,usb,yes,25,28 2006.202.01:24:51.63/vb/06,04,usb,yes,30,26 2006.202.01:24:51.63/vb/07,04,usb,yes,29,29 2006.202.01:24:51.63/vb/08,04,usb,yes,27,30 2006.202.01:24:51.87/vblo/01,629.99,yes,locked 2006.202.01:24:51.87/vblo/02,634.99,yes,locked 2006.202.01:24:51.87/vblo/03,649.99,yes,locked 2006.202.01:24:51.87/vblo/04,679.99,yes,locked 2006.202.01:24:51.87/vblo/05,709.99,yes,locked 2006.202.01:24:51.87/vblo/06,719.99,yes,locked 2006.202.01:24:51.87/vblo/07,734.99,yes,locked 2006.202.01:24:51.87/vblo/08,744.99,yes,locked 2006.202.01:24:52.02/vabw/8 2006.202.01:24:52.17/vbbw/8 2006.202.01:24:52.26/xfe/off,on,15.5 2006.202.01:24:52.65/ifatt/23,28,28,28 2006.202.01:24:53.07/fmout-gps/S +4.50E-07 2006.202.01:24:53.11:!2006.202.01:25:48 2006.202.01:25:48.00:data_valid=off 2006.202.01:25:48.00:"et 2006.202.01:25:48.00:!+3s 2006.202.01:25:51.02:"tape 2006.202.01:25:51.02:postob 2006.202.01:25:51.14/cable/+6.4846E-03 2006.202.01:25:51.14/wx/20.55,1000.7,100 2006.202.01:25:51.20/fmout-gps/S +4.50E-07 2006.202.01:25:51.20:scan_name=202-0127,jd0607,784 2006.202.01:25:51.20:source=0458-020,050112.81,-015914.3,2000.0,ccw 2006.202.01:25:52.14#flagr#flagr/antenna,new-source 2006.202.01:25:52.14:checkk5 2006.202.01:25:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.202.01:25:52.95/chk_autoobs//k5ts2/ autoobs is running! 2006.202.01:25:53.36/chk_autoobs//k5ts3/ autoobs is running! 2006.202.01:25:53.76/chk_autoobs//k5ts4/ autoobs is running! 2006.202.01:25:54.14/chk_obsdata//k5ts1/T2020124??a.dat file size is correct (nominal:240MB, actual:236MB). 2006.202.01:25:54.54/chk_obsdata//k5ts2/T2020124??b.dat file size is correct (nominal:240MB, actual:236MB). 2006.202.01:25:54.96/chk_obsdata//k5ts3/T2020124??c.dat file size is correct (nominal:240MB, actual:236MB). 2006.202.01:25:55.35/chk_obsdata//k5ts4/T2020124??d.dat file size is correct (nominal:240MB, actual:236MB). 2006.202.01:25:56.07/k5log//k5ts1_log_newline 2006.202.01:25:56.76/k5log//k5ts2_log_newline 2006.202.01:25:57.49/k5log//k5ts3_log_newline 2006.202.01:25:58.21/k5log//k5ts4_log_newline 2006.202.01:25:58.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.01:25:58.23:setupk4=1 2006.202.01:25:58.23$setupk4/echo=on 2006.202.01:25:58.23$setupk4/pcalon 2006.202.01:25:58.23$pcalon/"no phase cal control is implemented here 2006.202.01:25:58.24$setupk4/"tpicd=stop 2006.202.01:25:58.24$setupk4/"rec=synch_on 2006.202.01:25:58.24$setupk4/"rec_mode=128 2006.202.01:25:58.24$setupk4/!* 2006.202.01:25:58.24$setupk4/recpk4 2006.202.01:25:58.24$recpk4/recpatch= 2006.202.01:25:58.24$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.01:25:58.24$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.01:25:58.24$setupk4/vck44 2006.202.01:25:58.24$vck44/valo=1,524.99 2006.202.01:25:58.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.202.01:25:58.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.202.01:25:58.24#ibcon#ireg 17 cls_cnt 0 2006.202.01:25:58.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:25:58.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:25:58.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:25:58.24#ibcon#enter wrdev, iclass 11, count 0 2006.202.01:25:58.24#ibcon#first serial, iclass 11, count 0 2006.202.01:25:58.24#ibcon#enter sib2, iclass 11, count 0 2006.202.01:25:58.24#ibcon#flushed, iclass 11, count 0 2006.202.01:25:58.24#ibcon#about to write, iclass 11, count 0 2006.202.01:25:58.24#ibcon#wrote, iclass 11, count 0 2006.202.01:25:58.24#ibcon#about to read 3, iclass 11, count 0 2006.202.01:25:58.26#ibcon#read 3, iclass 11, count 0 2006.202.01:25:58.26#ibcon#about to read 4, iclass 11, count 0 2006.202.01:25:58.26#ibcon#read 4, iclass 11, count 0 2006.202.01:25:58.26#ibcon#about to read 5, iclass 11, count 0 2006.202.01:25:58.26#ibcon#read 5, iclass 11, count 0 2006.202.01:25:58.26#ibcon#about to read 6, iclass 11, count 0 2006.202.01:25:58.26#ibcon#read 6, iclass 11, count 0 2006.202.01:25:58.26#ibcon#end of sib2, iclass 11, count 0 2006.202.01:25:58.26#ibcon#*mode == 0, iclass 11, count 0 2006.202.01:25:58.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.01:25:58.26#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.01:25:58.26#ibcon#*before write, iclass 11, count 0 2006.202.01:25:58.26#ibcon#enter sib2, iclass 11, count 0 2006.202.01:25:58.26#ibcon#flushed, iclass 11, count 0 2006.202.01:25:58.26#ibcon#about to write, iclass 11, count 0 2006.202.01:25:58.26#ibcon#wrote, iclass 11, count 0 2006.202.01:25:58.26#ibcon#about to read 3, iclass 11, count 0 2006.202.01:25:58.31#ibcon#read 3, iclass 11, count 0 2006.202.01:25:58.31#ibcon#about to read 4, iclass 11, count 0 2006.202.01:25:58.31#ibcon#read 4, iclass 11, count 0 2006.202.01:25:58.31#ibcon#about to read 5, iclass 11, count 0 2006.202.01:25:58.31#ibcon#read 5, iclass 11, count 0 2006.202.01:25:58.31#ibcon#about to read 6, iclass 11, count 0 2006.202.01:25:58.31#ibcon#read 6, iclass 11, count 0 2006.202.01:25:58.31#ibcon#end of sib2, iclass 11, count 0 2006.202.01:25:58.31#ibcon#*after write, iclass 11, count 0 2006.202.01:25:58.31#ibcon#*before return 0, iclass 11, count 0 2006.202.01:25:58.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:25:58.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:25:58.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.01:25:58.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.01:25:58.31$vck44/va=1,8 2006.202.01:25:58.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.202.01:25:58.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.202.01:25:58.31#ibcon#ireg 11 cls_cnt 2 2006.202.01:25:58.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:25:58.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:25:58.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:25:58.31#ibcon#enter wrdev, iclass 13, count 2 2006.202.01:25:58.31#ibcon#first serial, iclass 13, count 2 2006.202.01:25:58.31#ibcon#enter sib2, iclass 13, count 2 2006.202.01:25:58.31#ibcon#flushed, iclass 13, count 2 2006.202.01:25:58.31#ibcon#about to write, iclass 13, count 2 2006.202.01:25:58.31#ibcon#wrote, iclass 13, count 2 2006.202.01:25:58.31#ibcon#about to read 3, iclass 13, count 2 2006.202.01:25:58.33#ibcon#read 3, iclass 13, count 2 2006.202.01:25:58.33#ibcon#about to read 4, iclass 13, count 2 2006.202.01:25:58.33#ibcon#read 4, iclass 13, count 2 2006.202.01:25:58.33#ibcon#about to read 5, iclass 13, count 2 2006.202.01:25:58.33#ibcon#read 5, iclass 13, count 2 2006.202.01:25:58.33#ibcon#about to read 6, iclass 13, count 2 2006.202.01:25:58.33#ibcon#read 6, iclass 13, count 2 2006.202.01:25:58.33#ibcon#end of sib2, iclass 13, count 2 2006.202.01:25:58.33#ibcon#*mode == 0, iclass 13, count 2 2006.202.01:25:58.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.202.01:25:58.33#ibcon#[25=AT01-08\r\n] 2006.202.01:25:58.33#ibcon#*before write, iclass 13, count 2 2006.202.01:25:58.33#ibcon#enter sib2, iclass 13, count 2 2006.202.01:25:58.33#ibcon#flushed, iclass 13, count 2 2006.202.01:25:58.33#ibcon#about to write, iclass 13, count 2 2006.202.01:25:58.33#ibcon#wrote, iclass 13, count 2 2006.202.01:25:58.33#ibcon#about to read 3, iclass 13, count 2 2006.202.01:25:58.36#ibcon#read 3, iclass 13, count 2 2006.202.01:25:58.36#ibcon#about to read 4, iclass 13, count 2 2006.202.01:25:58.36#ibcon#read 4, iclass 13, count 2 2006.202.01:25:58.36#ibcon#about to read 5, iclass 13, count 2 2006.202.01:25:58.36#ibcon#read 5, iclass 13, count 2 2006.202.01:25:58.36#ibcon#about to read 6, iclass 13, count 2 2006.202.01:25:58.36#ibcon#read 6, iclass 13, count 2 2006.202.01:25:58.36#ibcon#end of sib2, iclass 13, count 2 2006.202.01:25:58.36#ibcon#*after write, iclass 13, count 2 2006.202.01:25:58.36#ibcon#*before return 0, iclass 13, count 2 2006.202.01:25:58.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:25:58.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:25:58.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.202.01:25:58.36#ibcon#ireg 7 cls_cnt 0 2006.202.01:25:58.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:25:58.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:25:58.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:25:58.48#ibcon#enter wrdev, iclass 13, count 0 2006.202.01:25:58.48#ibcon#first serial, iclass 13, count 0 2006.202.01:25:58.48#ibcon#enter sib2, iclass 13, count 0 2006.202.01:25:58.48#ibcon#flushed, iclass 13, count 0 2006.202.01:25:58.48#ibcon#about to write, iclass 13, count 0 2006.202.01:25:58.48#ibcon#wrote, iclass 13, count 0 2006.202.01:25:58.48#ibcon#about to read 3, iclass 13, count 0 2006.202.01:25:58.50#ibcon#read 3, iclass 13, count 0 2006.202.01:25:58.50#ibcon#about to read 4, iclass 13, count 0 2006.202.01:25:58.50#ibcon#read 4, iclass 13, count 0 2006.202.01:25:58.50#ibcon#about to read 5, iclass 13, count 0 2006.202.01:25:58.50#ibcon#read 5, iclass 13, count 0 2006.202.01:25:58.50#ibcon#about to read 6, iclass 13, count 0 2006.202.01:25:58.50#ibcon#read 6, iclass 13, count 0 2006.202.01:25:58.50#ibcon#end of sib2, iclass 13, count 0 2006.202.01:25:58.50#ibcon#*mode == 0, iclass 13, count 0 2006.202.01:25:58.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.01:25:58.50#ibcon#[25=USB\r\n] 2006.202.01:25:58.50#ibcon#*before write, iclass 13, count 0 2006.202.01:25:58.50#ibcon#enter sib2, iclass 13, count 0 2006.202.01:25:58.50#ibcon#flushed, iclass 13, count 0 2006.202.01:25:58.50#ibcon#about to write, iclass 13, count 0 2006.202.01:25:58.50#ibcon#wrote, iclass 13, count 0 2006.202.01:25:58.50#ibcon#about to read 3, iclass 13, count 0 2006.202.01:25:58.53#ibcon#read 3, iclass 13, count 0 2006.202.01:25:58.53#ibcon#about to read 4, iclass 13, count 0 2006.202.01:25:58.53#ibcon#read 4, iclass 13, count 0 2006.202.01:25:58.53#ibcon#about to read 5, iclass 13, count 0 2006.202.01:25:58.53#ibcon#read 5, iclass 13, count 0 2006.202.01:25:58.53#ibcon#about to read 6, iclass 13, count 0 2006.202.01:25:58.53#ibcon#read 6, iclass 13, count 0 2006.202.01:25:58.53#ibcon#end of sib2, iclass 13, count 0 2006.202.01:25:58.53#ibcon#*after write, iclass 13, count 0 2006.202.01:25:58.53#ibcon#*before return 0, iclass 13, count 0 2006.202.01:25:58.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:25:58.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:25:58.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.01:25:58.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.01:25:58.53$vck44/valo=2,534.99 2006.202.01:25:58.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.01:25:58.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.01:25:58.53#ibcon#ireg 17 cls_cnt 0 2006.202.01:25:58.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:25:58.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:25:58.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:25:58.53#ibcon#enter wrdev, iclass 15, count 0 2006.202.01:25:58.53#ibcon#first serial, iclass 15, count 0 2006.202.01:25:58.53#ibcon#enter sib2, iclass 15, count 0 2006.202.01:25:58.53#ibcon#flushed, iclass 15, count 0 2006.202.01:25:58.53#ibcon#about to write, iclass 15, count 0 2006.202.01:25:58.53#ibcon#wrote, iclass 15, count 0 2006.202.01:25:58.53#ibcon#about to read 3, iclass 15, count 0 2006.202.01:25:58.55#ibcon#read 3, iclass 15, count 0 2006.202.01:25:58.55#ibcon#about to read 4, iclass 15, count 0 2006.202.01:25:58.55#ibcon#read 4, iclass 15, count 0 2006.202.01:25:58.55#ibcon#about to read 5, iclass 15, count 0 2006.202.01:25:58.55#ibcon#read 5, iclass 15, count 0 2006.202.01:25:58.55#ibcon#about to read 6, iclass 15, count 0 2006.202.01:25:58.55#ibcon#read 6, iclass 15, count 0 2006.202.01:25:58.55#ibcon#end of sib2, iclass 15, count 0 2006.202.01:25:58.55#ibcon#*mode == 0, iclass 15, count 0 2006.202.01:25:58.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.01:25:58.55#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.01:25:58.55#ibcon#*before write, iclass 15, count 0 2006.202.01:25:58.55#ibcon#enter sib2, iclass 15, count 0 2006.202.01:25:58.55#ibcon#flushed, iclass 15, count 0 2006.202.01:25:58.55#ibcon#about to write, iclass 15, count 0 2006.202.01:25:58.55#ibcon#wrote, iclass 15, count 0 2006.202.01:25:58.55#ibcon#about to read 3, iclass 15, count 0 2006.202.01:25:58.59#ibcon#read 3, iclass 15, count 0 2006.202.01:25:58.59#ibcon#about to read 4, iclass 15, count 0 2006.202.01:25:58.59#ibcon#read 4, iclass 15, count 0 2006.202.01:25:58.59#ibcon#about to read 5, iclass 15, count 0 2006.202.01:25:58.59#ibcon#read 5, iclass 15, count 0 2006.202.01:25:58.59#ibcon#about to read 6, iclass 15, count 0 2006.202.01:25:58.59#ibcon#read 6, iclass 15, count 0 2006.202.01:25:58.59#ibcon#end of sib2, iclass 15, count 0 2006.202.01:25:58.59#ibcon#*after write, iclass 15, count 0 2006.202.01:25:58.59#ibcon#*before return 0, iclass 15, count 0 2006.202.01:25:58.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:25:58.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:25:58.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.01:25:58.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.01:25:58.59$vck44/va=2,7 2006.202.01:25:58.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.202.01:25:58.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.202.01:25:58.59#ibcon#ireg 11 cls_cnt 2 2006.202.01:25:58.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:25:58.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:25:58.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:25:58.65#ibcon#enter wrdev, iclass 17, count 2 2006.202.01:25:58.65#ibcon#first serial, iclass 17, count 2 2006.202.01:25:58.65#ibcon#enter sib2, iclass 17, count 2 2006.202.01:25:58.65#ibcon#flushed, iclass 17, count 2 2006.202.01:25:58.65#ibcon#about to write, iclass 17, count 2 2006.202.01:25:58.65#ibcon#wrote, iclass 17, count 2 2006.202.01:25:58.65#ibcon#about to read 3, iclass 17, count 2 2006.202.01:25:58.67#ibcon#read 3, iclass 17, count 2 2006.202.01:25:58.67#ibcon#about to read 4, iclass 17, count 2 2006.202.01:25:58.67#ibcon#read 4, iclass 17, count 2 2006.202.01:25:58.67#ibcon#about to read 5, iclass 17, count 2 2006.202.01:25:58.67#ibcon#read 5, iclass 17, count 2 2006.202.01:25:58.67#ibcon#about to read 6, iclass 17, count 2 2006.202.01:25:58.67#ibcon#read 6, iclass 17, count 2 2006.202.01:25:58.67#ibcon#end of sib2, iclass 17, count 2 2006.202.01:25:58.67#ibcon#*mode == 0, iclass 17, count 2 2006.202.01:25:58.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.202.01:25:58.67#ibcon#[25=AT02-07\r\n] 2006.202.01:25:58.67#ibcon#*before write, iclass 17, count 2 2006.202.01:25:58.67#ibcon#enter sib2, iclass 17, count 2 2006.202.01:25:58.67#ibcon#flushed, iclass 17, count 2 2006.202.01:25:58.67#ibcon#about to write, iclass 17, count 2 2006.202.01:25:58.67#ibcon#wrote, iclass 17, count 2 2006.202.01:25:58.67#ibcon#about to read 3, iclass 17, count 2 2006.202.01:25:58.70#ibcon#read 3, iclass 17, count 2 2006.202.01:25:58.70#ibcon#about to read 4, iclass 17, count 2 2006.202.01:25:58.70#ibcon#read 4, iclass 17, count 2 2006.202.01:25:58.70#ibcon#about to read 5, iclass 17, count 2 2006.202.01:25:58.70#ibcon#read 5, iclass 17, count 2 2006.202.01:25:58.70#ibcon#about to read 6, iclass 17, count 2 2006.202.01:25:58.70#ibcon#read 6, iclass 17, count 2 2006.202.01:25:58.70#ibcon#end of sib2, iclass 17, count 2 2006.202.01:25:58.70#ibcon#*after write, iclass 17, count 2 2006.202.01:25:58.70#ibcon#*before return 0, iclass 17, count 2 2006.202.01:25:58.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:25:58.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:25:58.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.202.01:25:58.70#ibcon#ireg 7 cls_cnt 0 2006.202.01:25:58.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:25:58.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:25:58.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:25:58.82#ibcon#enter wrdev, iclass 17, count 0 2006.202.01:25:58.82#ibcon#first serial, iclass 17, count 0 2006.202.01:25:58.82#ibcon#enter sib2, iclass 17, count 0 2006.202.01:25:58.82#ibcon#flushed, iclass 17, count 0 2006.202.01:25:58.82#ibcon#about to write, iclass 17, count 0 2006.202.01:25:58.82#ibcon#wrote, iclass 17, count 0 2006.202.01:25:58.82#ibcon#about to read 3, iclass 17, count 0 2006.202.01:25:58.84#ibcon#read 3, iclass 17, count 0 2006.202.01:25:58.84#ibcon#about to read 4, iclass 17, count 0 2006.202.01:25:58.84#ibcon#read 4, iclass 17, count 0 2006.202.01:25:58.84#ibcon#about to read 5, iclass 17, count 0 2006.202.01:25:58.84#ibcon#read 5, iclass 17, count 0 2006.202.01:25:58.84#ibcon#about to read 6, iclass 17, count 0 2006.202.01:25:58.84#ibcon#read 6, iclass 17, count 0 2006.202.01:25:58.84#ibcon#end of sib2, iclass 17, count 0 2006.202.01:25:58.84#ibcon#*mode == 0, iclass 17, count 0 2006.202.01:25:58.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.01:25:58.84#ibcon#[25=USB\r\n] 2006.202.01:25:58.84#ibcon#*before write, iclass 17, count 0 2006.202.01:25:58.84#ibcon#enter sib2, iclass 17, count 0 2006.202.01:25:58.84#ibcon#flushed, iclass 17, count 0 2006.202.01:25:58.84#ibcon#about to write, iclass 17, count 0 2006.202.01:25:58.84#ibcon#wrote, iclass 17, count 0 2006.202.01:25:58.84#ibcon#about to read 3, iclass 17, count 0 2006.202.01:25:58.87#ibcon#read 3, iclass 17, count 0 2006.202.01:25:58.87#ibcon#about to read 4, iclass 17, count 0 2006.202.01:25:58.87#ibcon#read 4, iclass 17, count 0 2006.202.01:25:58.87#ibcon#about to read 5, iclass 17, count 0 2006.202.01:25:58.87#ibcon#read 5, iclass 17, count 0 2006.202.01:25:58.87#ibcon#about to read 6, iclass 17, count 0 2006.202.01:25:58.87#ibcon#read 6, iclass 17, count 0 2006.202.01:25:58.87#ibcon#end of sib2, iclass 17, count 0 2006.202.01:25:58.87#ibcon#*after write, iclass 17, count 0 2006.202.01:25:58.87#ibcon#*before return 0, iclass 17, count 0 2006.202.01:25:58.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:25:58.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:25:58.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.01:25:58.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.01:25:58.87$vck44/valo=3,564.99 2006.202.01:25:58.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.202.01:25:58.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.202.01:25:58.87#ibcon#ireg 17 cls_cnt 0 2006.202.01:25:58.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:25:58.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:25:58.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:25:58.87#ibcon#enter wrdev, iclass 19, count 0 2006.202.01:25:58.87#ibcon#first serial, iclass 19, count 0 2006.202.01:25:58.87#ibcon#enter sib2, iclass 19, count 0 2006.202.01:25:58.87#ibcon#flushed, iclass 19, count 0 2006.202.01:25:58.87#ibcon#about to write, iclass 19, count 0 2006.202.01:25:58.87#ibcon#wrote, iclass 19, count 0 2006.202.01:25:58.87#ibcon#about to read 3, iclass 19, count 0 2006.202.01:25:58.89#ibcon#read 3, iclass 19, count 0 2006.202.01:25:58.89#ibcon#about to read 4, iclass 19, count 0 2006.202.01:25:58.89#ibcon#read 4, iclass 19, count 0 2006.202.01:25:58.89#ibcon#about to read 5, iclass 19, count 0 2006.202.01:25:58.89#ibcon#read 5, iclass 19, count 0 2006.202.01:25:58.89#ibcon#about to read 6, iclass 19, count 0 2006.202.01:25:58.89#ibcon#read 6, iclass 19, count 0 2006.202.01:25:58.89#ibcon#end of sib2, iclass 19, count 0 2006.202.01:25:58.89#ibcon#*mode == 0, iclass 19, count 0 2006.202.01:25:58.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.01:25:58.89#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.01:25:58.89#ibcon#*before write, iclass 19, count 0 2006.202.01:25:58.89#ibcon#enter sib2, iclass 19, count 0 2006.202.01:25:58.89#ibcon#flushed, iclass 19, count 0 2006.202.01:25:58.89#ibcon#about to write, iclass 19, count 0 2006.202.01:25:58.89#ibcon#wrote, iclass 19, count 0 2006.202.01:25:58.89#ibcon#about to read 3, iclass 19, count 0 2006.202.01:25:58.93#ibcon#read 3, iclass 19, count 0 2006.202.01:25:58.93#ibcon#about to read 4, iclass 19, count 0 2006.202.01:25:58.93#ibcon#read 4, iclass 19, count 0 2006.202.01:25:58.93#ibcon#about to read 5, iclass 19, count 0 2006.202.01:25:58.93#ibcon#read 5, iclass 19, count 0 2006.202.01:25:58.93#ibcon#about to read 6, iclass 19, count 0 2006.202.01:25:58.93#ibcon#read 6, iclass 19, count 0 2006.202.01:25:58.93#ibcon#end of sib2, iclass 19, count 0 2006.202.01:25:58.93#ibcon#*after write, iclass 19, count 0 2006.202.01:25:58.93#ibcon#*before return 0, iclass 19, count 0 2006.202.01:25:58.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:25:58.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:25:58.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.01:25:58.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.01:25:58.93$vck44/va=3,8 2006.202.01:25:58.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.202.01:25:58.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.202.01:25:58.93#ibcon#ireg 11 cls_cnt 2 2006.202.01:25:58.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:25:58.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:25:58.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:25:58.99#ibcon#enter wrdev, iclass 21, count 2 2006.202.01:25:58.99#ibcon#first serial, iclass 21, count 2 2006.202.01:25:58.99#ibcon#enter sib2, iclass 21, count 2 2006.202.01:25:58.99#ibcon#flushed, iclass 21, count 2 2006.202.01:25:58.99#ibcon#about to write, iclass 21, count 2 2006.202.01:25:58.99#ibcon#wrote, iclass 21, count 2 2006.202.01:25:58.99#ibcon#about to read 3, iclass 21, count 2 2006.202.01:25:59.01#ibcon#read 3, iclass 21, count 2 2006.202.01:25:59.01#ibcon#about to read 4, iclass 21, count 2 2006.202.01:25:59.01#ibcon#read 4, iclass 21, count 2 2006.202.01:25:59.01#ibcon#about to read 5, iclass 21, count 2 2006.202.01:25:59.01#ibcon#read 5, iclass 21, count 2 2006.202.01:25:59.01#ibcon#about to read 6, iclass 21, count 2 2006.202.01:25:59.01#ibcon#read 6, iclass 21, count 2 2006.202.01:25:59.01#ibcon#end of sib2, iclass 21, count 2 2006.202.01:25:59.01#ibcon#*mode == 0, iclass 21, count 2 2006.202.01:25:59.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.202.01:25:59.01#ibcon#[25=AT03-08\r\n] 2006.202.01:25:59.01#ibcon#*before write, iclass 21, count 2 2006.202.01:25:59.01#ibcon#enter sib2, iclass 21, count 2 2006.202.01:25:59.01#ibcon#flushed, iclass 21, count 2 2006.202.01:25:59.01#ibcon#about to write, iclass 21, count 2 2006.202.01:25:59.01#ibcon#wrote, iclass 21, count 2 2006.202.01:25:59.01#ibcon#about to read 3, iclass 21, count 2 2006.202.01:25:59.03#abcon#<5=/04 2.1 5.3 20.551001000.7\r\n> 2006.202.01:25:59.04#ibcon#read 3, iclass 21, count 2 2006.202.01:25:59.04#ibcon#about to read 4, iclass 21, count 2 2006.202.01:25:59.04#ibcon#read 4, iclass 21, count 2 2006.202.01:25:59.04#ibcon#about to read 5, iclass 21, count 2 2006.202.01:25:59.04#ibcon#read 5, iclass 21, count 2 2006.202.01:25:59.04#ibcon#about to read 6, iclass 21, count 2 2006.202.01:25:59.04#ibcon#read 6, iclass 21, count 2 2006.202.01:25:59.04#ibcon#end of sib2, iclass 21, count 2 2006.202.01:25:59.04#ibcon#*after write, iclass 21, count 2 2006.202.01:25:59.04#ibcon#*before return 0, iclass 21, count 2 2006.202.01:25:59.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:25:59.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:25:59.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.202.01:25:59.04#ibcon#ireg 7 cls_cnt 0 2006.202.01:25:59.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:25:59.05#abcon#{5=INTERFACE CLEAR} 2006.202.01:25:59.11#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:25:59.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:25:59.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:25:59.16#ibcon#enter wrdev, iclass 21, count 0 2006.202.01:25:59.16#ibcon#first serial, iclass 21, count 0 2006.202.01:25:59.16#ibcon#enter sib2, iclass 21, count 0 2006.202.01:25:59.16#ibcon#flushed, iclass 21, count 0 2006.202.01:25:59.16#ibcon#about to write, iclass 21, count 0 2006.202.01:25:59.16#ibcon#wrote, iclass 21, count 0 2006.202.01:25:59.16#ibcon#about to read 3, iclass 21, count 0 2006.202.01:25:59.18#ibcon#read 3, iclass 21, count 0 2006.202.01:25:59.18#ibcon#about to read 4, iclass 21, count 0 2006.202.01:25:59.18#ibcon#read 4, iclass 21, count 0 2006.202.01:25:59.18#ibcon#about to read 5, iclass 21, count 0 2006.202.01:25:59.18#ibcon#read 5, iclass 21, count 0 2006.202.01:25:59.18#ibcon#about to read 6, iclass 21, count 0 2006.202.01:25:59.18#ibcon#read 6, iclass 21, count 0 2006.202.01:25:59.18#ibcon#end of sib2, iclass 21, count 0 2006.202.01:25:59.18#ibcon#*mode == 0, iclass 21, count 0 2006.202.01:25:59.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.01:25:59.18#ibcon#[25=USB\r\n] 2006.202.01:25:59.18#ibcon#*before write, iclass 21, count 0 2006.202.01:25:59.18#ibcon#enter sib2, iclass 21, count 0 2006.202.01:25:59.18#ibcon#flushed, iclass 21, count 0 2006.202.01:25:59.18#ibcon#about to write, iclass 21, count 0 2006.202.01:25:59.18#ibcon#wrote, iclass 21, count 0 2006.202.01:25:59.18#ibcon#about to read 3, iclass 21, count 0 2006.202.01:25:59.21#ibcon#read 3, iclass 21, count 0 2006.202.01:25:59.21#ibcon#about to read 4, iclass 21, count 0 2006.202.01:25:59.21#ibcon#read 4, iclass 21, count 0 2006.202.01:25:59.21#ibcon#about to read 5, iclass 21, count 0 2006.202.01:25:59.21#ibcon#read 5, iclass 21, count 0 2006.202.01:25:59.21#ibcon#about to read 6, iclass 21, count 0 2006.202.01:25:59.21#ibcon#read 6, iclass 21, count 0 2006.202.01:25:59.21#ibcon#end of sib2, iclass 21, count 0 2006.202.01:25:59.21#ibcon#*after write, iclass 21, count 0 2006.202.01:25:59.21#ibcon#*before return 0, iclass 21, count 0 2006.202.01:25:59.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:25:59.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:25:59.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.01:25:59.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.01:25:59.21$vck44/valo=4,624.99 2006.202.01:25:59.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.202.01:25:59.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.202.01:25:59.21#ibcon#ireg 17 cls_cnt 0 2006.202.01:25:59.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:25:59.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:25:59.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:25:59.21#ibcon#enter wrdev, iclass 27, count 0 2006.202.01:25:59.21#ibcon#first serial, iclass 27, count 0 2006.202.01:25:59.21#ibcon#enter sib2, iclass 27, count 0 2006.202.01:25:59.21#ibcon#flushed, iclass 27, count 0 2006.202.01:25:59.21#ibcon#about to write, iclass 27, count 0 2006.202.01:25:59.21#ibcon#wrote, iclass 27, count 0 2006.202.01:25:59.21#ibcon#about to read 3, iclass 27, count 0 2006.202.01:25:59.23#ibcon#read 3, iclass 27, count 0 2006.202.01:25:59.23#ibcon#about to read 4, iclass 27, count 0 2006.202.01:25:59.23#ibcon#read 4, iclass 27, count 0 2006.202.01:25:59.23#ibcon#about to read 5, iclass 27, count 0 2006.202.01:25:59.23#ibcon#read 5, iclass 27, count 0 2006.202.01:25:59.23#ibcon#about to read 6, iclass 27, count 0 2006.202.01:25:59.23#ibcon#read 6, iclass 27, count 0 2006.202.01:25:59.23#ibcon#end of sib2, iclass 27, count 0 2006.202.01:25:59.23#ibcon#*mode == 0, iclass 27, count 0 2006.202.01:25:59.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.01:25:59.23#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.01:25:59.23#ibcon#*before write, iclass 27, count 0 2006.202.01:25:59.23#ibcon#enter sib2, iclass 27, count 0 2006.202.01:25:59.23#ibcon#flushed, iclass 27, count 0 2006.202.01:25:59.23#ibcon#about to write, iclass 27, count 0 2006.202.01:25:59.23#ibcon#wrote, iclass 27, count 0 2006.202.01:25:59.23#ibcon#about to read 3, iclass 27, count 0 2006.202.01:25:59.27#ibcon#read 3, iclass 27, count 0 2006.202.01:25:59.27#ibcon#about to read 4, iclass 27, count 0 2006.202.01:25:59.27#ibcon#read 4, iclass 27, count 0 2006.202.01:25:59.27#ibcon#about to read 5, iclass 27, count 0 2006.202.01:25:59.27#ibcon#read 5, iclass 27, count 0 2006.202.01:25:59.27#ibcon#about to read 6, iclass 27, count 0 2006.202.01:25:59.27#ibcon#read 6, iclass 27, count 0 2006.202.01:25:59.27#ibcon#end of sib2, iclass 27, count 0 2006.202.01:25:59.27#ibcon#*after write, iclass 27, count 0 2006.202.01:25:59.27#ibcon#*before return 0, iclass 27, count 0 2006.202.01:25:59.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:25:59.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:25:59.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.01:25:59.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.01:25:59.27$vck44/va=4,7 2006.202.01:25:59.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.01:25:59.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.01:25:59.27#ibcon#ireg 11 cls_cnt 2 2006.202.01:25:59.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:25:59.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:25:59.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:25:59.33#ibcon#enter wrdev, iclass 29, count 2 2006.202.01:25:59.33#ibcon#first serial, iclass 29, count 2 2006.202.01:25:59.33#ibcon#enter sib2, iclass 29, count 2 2006.202.01:25:59.33#ibcon#flushed, iclass 29, count 2 2006.202.01:25:59.33#ibcon#about to write, iclass 29, count 2 2006.202.01:25:59.33#ibcon#wrote, iclass 29, count 2 2006.202.01:25:59.33#ibcon#about to read 3, iclass 29, count 2 2006.202.01:25:59.35#ibcon#read 3, iclass 29, count 2 2006.202.01:25:59.35#ibcon#about to read 4, iclass 29, count 2 2006.202.01:25:59.35#ibcon#read 4, iclass 29, count 2 2006.202.01:25:59.35#ibcon#about to read 5, iclass 29, count 2 2006.202.01:25:59.35#ibcon#read 5, iclass 29, count 2 2006.202.01:25:59.35#ibcon#about to read 6, iclass 29, count 2 2006.202.01:25:59.35#ibcon#read 6, iclass 29, count 2 2006.202.01:25:59.35#ibcon#end of sib2, iclass 29, count 2 2006.202.01:25:59.35#ibcon#*mode == 0, iclass 29, count 2 2006.202.01:25:59.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.01:25:59.35#ibcon#[25=AT04-07\r\n] 2006.202.01:25:59.35#ibcon#*before write, iclass 29, count 2 2006.202.01:25:59.35#ibcon#enter sib2, iclass 29, count 2 2006.202.01:25:59.35#ibcon#flushed, iclass 29, count 2 2006.202.01:25:59.35#ibcon#about to write, iclass 29, count 2 2006.202.01:25:59.49#ibcon#wrote, iclass 29, count 2 2006.202.01:25:59.49#ibcon#about to read 3, iclass 29, count 2 2006.202.01:25:59.53#ibcon#read 3, iclass 29, count 2 2006.202.01:25:59.53#ibcon#about to read 4, iclass 29, count 2 2006.202.01:25:59.53#ibcon#read 4, iclass 29, count 2 2006.202.01:25:59.53#ibcon#about to read 5, iclass 29, count 2 2006.202.01:25:59.53#ibcon#read 5, iclass 29, count 2 2006.202.01:25:59.53#ibcon#about to read 6, iclass 29, count 2 2006.202.01:25:59.53#ibcon#read 6, iclass 29, count 2 2006.202.01:25:59.53#ibcon#end of sib2, iclass 29, count 2 2006.202.01:25:59.53#ibcon#*after write, iclass 29, count 2 2006.202.01:25:59.53#ibcon#*before return 0, iclass 29, count 2 2006.202.01:25:59.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:25:59.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:25:59.53#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.01:25:59.53#ibcon#ireg 7 cls_cnt 0 2006.202.01:25:59.53#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:25:59.65#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:25:59.65#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:25:59.65#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:25:59.65#ibcon#first serial, iclass 29, count 0 2006.202.01:25:59.65#ibcon#enter sib2, iclass 29, count 0 2006.202.01:25:59.65#ibcon#flushed, iclass 29, count 0 2006.202.01:25:59.65#ibcon#about to write, iclass 29, count 0 2006.202.01:25:59.65#ibcon#wrote, iclass 29, count 0 2006.202.01:25:59.65#ibcon#about to read 3, iclass 29, count 0 2006.202.01:25:59.67#ibcon#read 3, iclass 29, count 0 2006.202.01:25:59.67#ibcon#about to read 4, iclass 29, count 0 2006.202.01:25:59.67#ibcon#read 4, iclass 29, count 0 2006.202.01:25:59.67#ibcon#about to read 5, iclass 29, count 0 2006.202.01:25:59.67#ibcon#read 5, iclass 29, count 0 2006.202.01:25:59.67#ibcon#about to read 6, iclass 29, count 0 2006.202.01:25:59.67#ibcon#read 6, iclass 29, count 0 2006.202.01:25:59.67#ibcon#end of sib2, iclass 29, count 0 2006.202.01:25:59.67#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:25:59.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:25:59.67#ibcon#[25=USB\r\n] 2006.202.01:25:59.67#ibcon#*before write, iclass 29, count 0 2006.202.01:25:59.67#ibcon#enter sib2, iclass 29, count 0 2006.202.01:25:59.67#ibcon#flushed, iclass 29, count 0 2006.202.01:25:59.67#ibcon#about to write, iclass 29, count 0 2006.202.01:25:59.67#ibcon#wrote, iclass 29, count 0 2006.202.01:25:59.67#ibcon#about to read 3, iclass 29, count 0 2006.202.01:25:59.70#ibcon#read 3, iclass 29, count 0 2006.202.01:25:59.70#ibcon#about to read 4, iclass 29, count 0 2006.202.01:25:59.70#ibcon#read 4, iclass 29, count 0 2006.202.01:25:59.70#ibcon#about to read 5, iclass 29, count 0 2006.202.01:25:59.70#ibcon#read 5, iclass 29, count 0 2006.202.01:25:59.70#ibcon#about to read 6, iclass 29, count 0 2006.202.01:25:59.70#ibcon#read 6, iclass 29, count 0 2006.202.01:25:59.70#ibcon#end of sib2, iclass 29, count 0 2006.202.01:25:59.70#ibcon#*after write, iclass 29, count 0 2006.202.01:25:59.70#ibcon#*before return 0, iclass 29, count 0 2006.202.01:25:59.70#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:25:59.70#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:25:59.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:25:59.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:25:59.70$vck44/valo=5,734.99 2006.202.01:25:59.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.202.01:25:59.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.202.01:25:59.70#ibcon#ireg 17 cls_cnt 0 2006.202.01:25:59.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:25:59.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:25:59.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:25:59.70#ibcon#enter wrdev, iclass 31, count 0 2006.202.01:25:59.70#ibcon#first serial, iclass 31, count 0 2006.202.01:25:59.70#ibcon#enter sib2, iclass 31, count 0 2006.202.01:25:59.70#ibcon#flushed, iclass 31, count 0 2006.202.01:25:59.70#ibcon#about to write, iclass 31, count 0 2006.202.01:25:59.70#ibcon#wrote, iclass 31, count 0 2006.202.01:25:59.70#ibcon#about to read 3, iclass 31, count 0 2006.202.01:25:59.72#ibcon#read 3, iclass 31, count 0 2006.202.01:25:59.72#ibcon#about to read 4, iclass 31, count 0 2006.202.01:25:59.72#ibcon#read 4, iclass 31, count 0 2006.202.01:25:59.72#ibcon#about to read 5, iclass 31, count 0 2006.202.01:25:59.72#ibcon#read 5, iclass 31, count 0 2006.202.01:25:59.72#ibcon#about to read 6, iclass 31, count 0 2006.202.01:25:59.72#ibcon#read 6, iclass 31, count 0 2006.202.01:25:59.72#ibcon#end of sib2, iclass 31, count 0 2006.202.01:25:59.72#ibcon#*mode == 0, iclass 31, count 0 2006.202.01:25:59.72#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.01:25:59.72#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.01:25:59.72#ibcon#*before write, iclass 31, count 0 2006.202.01:25:59.72#ibcon#enter sib2, iclass 31, count 0 2006.202.01:25:59.72#ibcon#flushed, iclass 31, count 0 2006.202.01:25:59.72#ibcon#about to write, iclass 31, count 0 2006.202.01:25:59.72#ibcon#wrote, iclass 31, count 0 2006.202.01:25:59.72#ibcon#about to read 3, iclass 31, count 0 2006.202.01:25:59.76#ibcon#read 3, iclass 31, count 0 2006.202.01:25:59.76#ibcon#about to read 4, iclass 31, count 0 2006.202.01:25:59.76#ibcon#read 4, iclass 31, count 0 2006.202.01:25:59.76#ibcon#about to read 5, iclass 31, count 0 2006.202.01:25:59.76#ibcon#read 5, iclass 31, count 0 2006.202.01:25:59.76#ibcon#about to read 6, iclass 31, count 0 2006.202.01:25:59.76#ibcon#read 6, iclass 31, count 0 2006.202.01:25:59.76#ibcon#end of sib2, iclass 31, count 0 2006.202.01:25:59.76#ibcon#*after write, iclass 31, count 0 2006.202.01:25:59.76#ibcon#*before return 0, iclass 31, count 0 2006.202.01:25:59.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:25:59.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:25:59.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.01:25:59.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.01:25:59.76$vck44/va=5,4 2006.202.01:25:59.76#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.202.01:25:59.76#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.202.01:25:59.76#ibcon#ireg 11 cls_cnt 2 2006.202.01:25:59.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:25:59.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:25:59.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:25:59.82#ibcon#enter wrdev, iclass 33, count 2 2006.202.01:25:59.82#ibcon#first serial, iclass 33, count 2 2006.202.01:25:59.82#ibcon#enter sib2, iclass 33, count 2 2006.202.01:25:59.82#ibcon#flushed, iclass 33, count 2 2006.202.01:25:59.82#ibcon#about to write, iclass 33, count 2 2006.202.01:25:59.82#ibcon#wrote, iclass 33, count 2 2006.202.01:25:59.82#ibcon#about to read 3, iclass 33, count 2 2006.202.01:25:59.84#ibcon#read 3, iclass 33, count 2 2006.202.01:25:59.84#ibcon#about to read 4, iclass 33, count 2 2006.202.01:25:59.84#ibcon#read 4, iclass 33, count 2 2006.202.01:25:59.84#ibcon#about to read 5, iclass 33, count 2 2006.202.01:25:59.84#ibcon#read 5, iclass 33, count 2 2006.202.01:25:59.84#ibcon#about to read 6, iclass 33, count 2 2006.202.01:25:59.84#ibcon#read 6, iclass 33, count 2 2006.202.01:25:59.84#ibcon#end of sib2, iclass 33, count 2 2006.202.01:25:59.84#ibcon#*mode == 0, iclass 33, count 2 2006.202.01:25:59.84#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.202.01:25:59.84#ibcon#[25=AT05-04\r\n] 2006.202.01:25:59.84#ibcon#*before write, iclass 33, count 2 2006.202.01:25:59.84#ibcon#enter sib2, iclass 33, count 2 2006.202.01:25:59.84#ibcon#flushed, iclass 33, count 2 2006.202.01:25:59.84#ibcon#about to write, iclass 33, count 2 2006.202.01:25:59.84#ibcon#wrote, iclass 33, count 2 2006.202.01:25:59.84#ibcon#about to read 3, iclass 33, count 2 2006.202.01:25:59.87#ibcon#read 3, iclass 33, count 2 2006.202.01:25:59.87#ibcon#about to read 4, iclass 33, count 2 2006.202.01:25:59.87#ibcon#read 4, iclass 33, count 2 2006.202.01:25:59.87#ibcon#about to read 5, iclass 33, count 2 2006.202.01:25:59.87#ibcon#read 5, iclass 33, count 2 2006.202.01:25:59.87#ibcon#about to read 6, iclass 33, count 2 2006.202.01:25:59.87#ibcon#read 6, iclass 33, count 2 2006.202.01:25:59.87#ibcon#end of sib2, iclass 33, count 2 2006.202.01:25:59.87#ibcon#*after write, iclass 33, count 2 2006.202.01:25:59.87#ibcon#*before return 0, iclass 33, count 2 2006.202.01:25:59.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:25:59.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:25:59.87#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.202.01:25:59.87#ibcon#ireg 7 cls_cnt 0 2006.202.01:25:59.87#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:25:59.99#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:25:59.99#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:25:59.99#ibcon#enter wrdev, iclass 33, count 0 2006.202.01:25:59.99#ibcon#first serial, iclass 33, count 0 2006.202.01:25:59.99#ibcon#enter sib2, iclass 33, count 0 2006.202.01:25:59.99#ibcon#flushed, iclass 33, count 0 2006.202.01:25:59.99#ibcon#about to write, iclass 33, count 0 2006.202.01:25:59.99#ibcon#wrote, iclass 33, count 0 2006.202.01:25:59.99#ibcon#about to read 3, iclass 33, count 0 2006.202.01:26:00.01#ibcon#read 3, iclass 33, count 0 2006.202.01:26:00.01#ibcon#about to read 4, iclass 33, count 0 2006.202.01:26:00.01#ibcon#read 4, iclass 33, count 0 2006.202.01:26:00.01#ibcon#about to read 5, iclass 33, count 0 2006.202.01:26:00.01#ibcon#read 5, iclass 33, count 0 2006.202.01:26:00.01#ibcon#about to read 6, iclass 33, count 0 2006.202.01:26:00.01#ibcon#read 6, iclass 33, count 0 2006.202.01:26:00.01#ibcon#end of sib2, iclass 33, count 0 2006.202.01:26:00.01#ibcon#*mode == 0, iclass 33, count 0 2006.202.01:26:00.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.01:26:00.01#ibcon#[25=USB\r\n] 2006.202.01:26:00.01#ibcon#*before write, iclass 33, count 0 2006.202.01:26:00.01#ibcon#enter sib2, iclass 33, count 0 2006.202.01:26:00.01#ibcon#flushed, iclass 33, count 0 2006.202.01:26:00.01#ibcon#about to write, iclass 33, count 0 2006.202.01:26:00.01#ibcon#wrote, iclass 33, count 0 2006.202.01:26:00.01#ibcon#about to read 3, iclass 33, count 0 2006.202.01:26:00.04#ibcon#read 3, iclass 33, count 0 2006.202.01:26:00.04#ibcon#about to read 4, iclass 33, count 0 2006.202.01:26:00.04#ibcon#read 4, iclass 33, count 0 2006.202.01:26:00.04#ibcon#about to read 5, iclass 33, count 0 2006.202.01:26:00.04#ibcon#read 5, iclass 33, count 0 2006.202.01:26:00.04#ibcon#about to read 6, iclass 33, count 0 2006.202.01:26:00.04#ibcon#read 6, iclass 33, count 0 2006.202.01:26:00.04#ibcon#end of sib2, iclass 33, count 0 2006.202.01:26:00.04#ibcon#*after write, iclass 33, count 0 2006.202.01:26:00.04#ibcon#*before return 0, iclass 33, count 0 2006.202.01:26:00.04#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:26:00.04#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:26:00.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.01:26:00.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.01:26:00.04$vck44/valo=6,814.99 2006.202.01:26:00.04#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.202.01:26:00.04#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.202.01:26:00.04#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:00.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:00.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:00.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:00.04#ibcon#enter wrdev, iclass 35, count 0 2006.202.01:26:00.04#ibcon#first serial, iclass 35, count 0 2006.202.01:26:00.04#ibcon#enter sib2, iclass 35, count 0 2006.202.01:26:00.04#ibcon#flushed, iclass 35, count 0 2006.202.01:26:00.04#ibcon#about to write, iclass 35, count 0 2006.202.01:26:00.04#ibcon#wrote, iclass 35, count 0 2006.202.01:26:00.04#ibcon#about to read 3, iclass 35, count 0 2006.202.01:26:00.06#ibcon#read 3, iclass 35, count 0 2006.202.01:26:00.06#ibcon#about to read 4, iclass 35, count 0 2006.202.01:26:00.06#ibcon#read 4, iclass 35, count 0 2006.202.01:26:00.06#ibcon#about to read 5, iclass 35, count 0 2006.202.01:26:00.06#ibcon#read 5, iclass 35, count 0 2006.202.01:26:00.06#ibcon#about to read 6, iclass 35, count 0 2006.202.01:26:00.06#ibcon#read 6, iclass 35, count 0 2006.202.01:26:00.06#ibcon#end of sib2, iclass 35, count 0 2006.202.01:26:00.06#ibcon#*mode == 0, iclass 35, count 0 2006.202.01:26:00.06#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.01:26:00.06#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.01:26:00.06#ibcon#*before write, iclass 35, count 0 2006.202.01:26:00.06#ibcon#enter sib2, iclass 35, count 0 2006.202.01:26:00.06#ibcon#flushed, iclass 35, count 0 2006.202.01:26:00.06#ibcon#about to write, iclass 35, count 0 2006.202.01:26:00.06#ibcon#wrote, iclass 35, count 0 2006.202.01:26:00.06#ibcon#about to read 3, iclass 35, count 0 2006.202.01:26:00.10#ibcon#read 3, iclass 35, count 0 2006.202.01:26:00.10#ibcon#about to read 4, iclass 35, count 0 2006.202.01:26:00.10#ibcon#read 4, iclass 35, count 0 2006.202.01:26:00.10#ibcon#about to read 5, iclass 35, count 0 2006.202.01:26:00.10#ibcon#read 5, iclass 35, count 0 2006.202.01:26:00.10#ibcon#about to read 6, iclass 35, count 0 2006.202.01:26:00.10#ibcon#read 6, iclass 35, count 0 2006.202.01:26:00.10#ibcon#end of sib2, iclass 35, count 0 2006.202.01:26:00.10#ibcon#*after write, iclass 35, count 0 2006.202.01:26:00.10#ibcon#*before return 0, iclass 35, count 0 2006.202.01:26:00.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:00.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:00.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.01:26:00.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.01:26:00.10$vck44/va=6,5 2006.202.01:26:00.10#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.202.01:26:00.10#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.202.01:26:00.10#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:00.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:00.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:00.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:00.16#ibcon#enter wrdev, iclass 37, count 2 2006.202.01:26:00.16#ibcon#first serial, iclass 37, count 2 2006.202.01:26:00.16#ibcon#enter sib2, iclass 37, count 2 2006.202.01:26:00.16#ibcon#flushed, iclass 37, count 2 2006.202.01:26:00.16#ibcon#about to write, iclass 37, count 2 2006.202.01:26:00.16#ibcon#wrote, iclass 37, count 2 2006.202.01:26:00.16#ibcon#about to read 3, iclass 37, count 2 2006.202.01:26:00.18#ibcon#read 3, iclass 37, count 2 2006.202.01:26:00.18#ibcon#about to read 4, iclass 37, count 2 2006.202.01:26:00.18#ibcon#read 4, iclass 37, count 2 2006.202.01:26:00.18#ibcon#about to read 5, iclass 37, count 2 2006.202.01:26:00.18#ibcon#read 5, iclass 37, count 2 2006.202.01:26:00.18#ibcon#about to read 6, iclass 37, count 2 2006.202.01:26:00.18#ibcon#read 6, iclass 37, count 2 2006.202.01:26:00.18#ibcon#end of sib2, iclass 37, count 2 2006.202.01:26:00.18#ibcon#*mode == 0, iclass 37, count 2 2006.202.01:26:00.18#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.202.01:26:00.18#ibcon#[25=AT06-05\r\n] 2006.202.01:26:00.18#ibcon#*before write, iclass 37, count 2 2006.202.01:26:00.18#ibcon#enter sib2, iclass 37, count 2 2006.202.01:26:00.18#ibcon#flushed, iclass 37, count 2 2006.202.01:26:00.18#ibcon#about to write, iclass 37, count 2 2006.202.01:26:00.18#ibcon#wrote, iclass 37, count 2 2006.202.01:26:00.18#ibcon#about to read 3, iclass 37, count 2 2006.202.01:26:00.21#ibcon#read 3, iclass 37, count 2 2006.202.01:26:00.21#ibcon#about to read 4, iclass 37, count 2 2006.202.01:26:00.21#ibcon#read 4, iclass 37, count 2 2006.202.01:26:00.21#ibcon#about to read 5, iclass 37, count 2 2006.202.01:26:00.21#ibcon#read 5, iclass 37, count 2 2006.202.01:26:00.21#ibcon#about to read 6, iclass 37, count 2 2006.202.01:26:00.21#ibcon#read 6, iclass 37, count 2 2006.202.01:26:00.21#ibcon#end of sib2, iclass 37, count 2 2006.202.01:26:00.21#ibcon#*after write, iclass 37, count 2 2006.202.01:26:00.21#ibcon#*before return 0, iclass 37, count 2 2006.202.01:26:00.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:00.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:00.21#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.202.01:26:00.21#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:00.21#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:00.33#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:00.33#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:00.33#ibcon#enter wrdev, iclass 37, count 0 2006.202.01:26:00.33#ibcon#first serial, iclass 37, count 0 2006.202.01:26:00.33#ibcon#enter sib2, iclass 37, count 0 2006.202.01:26:00.33#ibcon#flushed, iclass 37, count 0 2006.202.01:26:00.33#ibcon#about to write, iclass 37, count 0 2006.202.01:26:00.33#ibcon#wrote, iclass 37, count 0 2006.202.01:26:00.33#ibcon#about to read 3, iclass 37, count 0 2006.202.01:26:00.35#ibcon#read 3, iclass 37, count 0 2006.202.01:26:00.35#ibcon#about to read 4, iclass 37, count 0 2006.202.01:26:00.35#ibcon#read 4, iclass 37, count 0 2006.202.01:26:00.35#ibcon#about to read 5, iclass 37, count 0 2006.202.01:26:00.35#ibcon#read 5, iclass 37, count 0 2006.202.01:26:00.35#ibcon#about to read 6, iclass 37, count 0 2006.202.01:26:00.35#ibcon#read 6, iclass 37, count 0 2006.202.01:26:00.35#ibcon#end of sib2, iclass 37, count 0 2006.202.01:26:00.35#ibcon#*mode == 0, iclass 37, count 0 2006.202.01:26:00.35#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.01:26:00.35#ibcon#[25=USB\r\n] 2006.202.01:26:00.35#ibcon#*before write, iclass 37, count 0 2006.202.01:26:00.35#ibcon#enter sib2, iclass 37, count 0 2006.202.01:26:00.35#ibcon#flushed, iclass 37, count 0 2006.202.01:26:00.35#ibcon#about to write, iclass 37, count 0 2006.202.01:26:00.35#ibcon#wrote, iclass 37, count 0 2006.202.01:26:00.35#ibcon#about to read 3, iclass 37, count 0 2006.202.01:26:00.38#ibcon#read 3, iclass 37, count 0 2006.202.01:26:00.38#ibcon#about to read 4, iclass 37, count 0 2006.202.01:26:00.38#ibcon#read 4, iclass 37, count 0 2006.202.01:26:00.38#ibcon#about to read 5, iclass 37, count 0 2006.202.01:26:00.38#ibcon#read 5, iclass 37, count 0 2006.202.01:26:00.38#ibcon#about to read 6, iclass 37, count 0 2006.202.01:26:00.38#ibcon#read 6, iclass 37, count 0 2006.202.01:26:00.38#ibcon#end of sib2, iclass 37, count 0 2006.202.01:26:00.38#ibcon#*after write, iclass 37, count 0 2006.202.01:26:00.38#ibcon#*before return 0, iclass 37, count 0 2006.202.01:26:00.38#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:00.38#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:00.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.01:26:00.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.01:26:00.38$vck44/valo=7,864.99 2006.202.01:26:00.38#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.202.01:26:00.38#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.202.01:26:00.38#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:00.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:00.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:00.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:00.38#ibcon#enter wrdev, iclass 39, count 0 2006.202.01:26:00.38#ibcon#first serial, iclass 39, count 0 2006.202.01:26:00.38#ibcon#enter sib2, iclass 39, count 0 2006.202.01:26:00.38#ibcon#flushed, iclass 39, count 0 2006.202.01:26:00.38#ibcon#about to write, iclass 39, count 0 2006.202.01:26:00.38#ibcon#wrote, iclass 39, count 0 2006.202.01:26:00.38#ibcon#about to read 3, iclass 39, count 0 2006.202.01:26:00.40#ibcon#read 3, iclass 39, count 0 2006.202.01:26:00.40#ibcon#about to read 4, iclass 39, count 0 2006.202.01:26:00.40#ibcon#read 4, iclass 39, count 0 2006.202.01:26:00.40#ibcon#about to read 5, iclass 39, count 0 2006.202.01:26:00.40#ibcon#read 5, iclass 39, count 0 2006.202.01:26:00.40#ibcon#about to read 6, iclass 39, count 0 2006.202.01:26:00.40#ibcon#read 6, iclass 39, count 0 2006.202.01:26:00.40#ibcon#end of sib2, iclass 39, count 0 2006.202.01:26:00.40#ibcon#*mode == 0, iclass 39, count 0 2006.202.01:26:00.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.01:26:00.40#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.01:26:00.40#ibcon#*before write, iclass 39, count 0 2006.202.01:26:00.40#ibcon#enter sib2, iclass 39, count 0 2006.202.01:26:00.40#ibcon#flushed, iclass 39, count 0 2006.202.01:26:00.40#ibcon#about to write, iclass 39, count 0 2006.202.01:26:00.40#ibcon#wrote, iclass 39, count 0 2006.202.01:26:00.40#ibcon#about to read 3, iclass 39, count 0 2006.202.01:26:00.44#ibcon#read 3, iclass 39, count 0 2006.202.01:26:00.44#ibcon#about to read 4, iclass 39, count 0 2006.202.01:26:00.44#ibcon#read 4, iclass 39, count 0 2006.202.01:26:00.44#ibcon#about to read 5, iclass 39, count 0 2006.202.01:26:00.44#ibcon#read 5, iclass 39, count 0 2006.202.01:26:00.44#ibcon#about to read 6, iclass 39, count 0 2006.202.01:26:00.44#ibcon#read 6, iclass 39, count 0 2006.202.01:26:00.44#ibcon#end of sib2, iclass 39, count 0 2006.202.01:26:00.44#ibcon#*after write, iclass 39, count 0 2006.202.01:26:00.44#ibcon#*before return 0, iclass 39, count 0 2006.202.01:26:00.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:00.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:00.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.01:26:00.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.01:26:00.60$vck44/va=7,5 2006.202.01:26:00.60#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.202.01:26:00.60#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.202.01:26:00.60#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:00.60#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:00.60#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:00.60#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:00.60#ibcon#enter wrdev, iclass 2, count 2 2006.202.01:26:00.60#ibcon#first serial, iclass 2, count 2 2006.202.01:26:00.60#ibcon#enter sib2, iclass 2, count 2 2006.202.01:26:00.60#ibcon#flushed, iclass 2, count 2 2006.202.01:26:00.60#ibcon#about to write, iclass 2, count 2 2006.202.01:26:00.60#ibcon#wrote, iclass 2, count 2 2006.202.01:26:00.60#ibcon#about to read 3, iclass 2, count 2 2006.202.01:26:00.62#ibcon#read 3, iclass 2, count 2 2006.202.01:26:00.62#ibcon#about to read 4, iclass 2, count 2 2006.202.01:26:00.62#ibcon#read 4, iclass 2, count 2 2006.202.01:26:00.62#ibcon#about to read 5, iclass 2, count 2 2006.202.01:26:00.62#ibcon#read 5, iclass 2, count 2 2006.202.01:26:00.62#ibcon#about to read 6, iclass 2, count 2 2006.202.01:26:00.62#ibcon#read 6, iclass 2, count 2 2006.202.01:26:00.62#ibcon#end of sib2, iclass 2, count 2 2006.202.01:26:00.62#ibcon#*mode == 0, iclass 2, count 2 2006.202.01:26:00.62#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.202.01:26:00.62#ibcon#[25=AT07-05\r\n] 2006.202.01:26:00.62#ibcon#*before write, iclass 2, count 2 2006.202.01:26:00.62#ibcon#enter sib2, iclass 2, count 2 2006.202.01:26:00.62#ibcon#flushed, iclass 2, count 2 2006.202.01:26:00.62#ibcon#about to write, iclass 2, count 2 2006.202.01:26:00.62#ibcon#wrote, iclass 2, count 2 2006.202.01:26:00.62#ibcon#about to read 3, iclass 2, count 2 2006.202.01:26:00.65#ibcon#read 3, iclass 2, count 2 2006.202.01:26:00.65#ibcon#about to read 4, iclass 2, count 2 2006.202.01:26:00.65#ibcon#read 4, iclass 2, count 2 2006.202.01:26:00.65#ibcon#about to read 5, iclass 2, count 2 2006.202.01:26:00.65#ibcon#read 5, iclass 2, count 2 2006.202.01:26:00.65#ibcon#about to read 6, iclass 2, count 2 2006.202.01:26:00.65#ibcon#read 6, iclass 2, count 2 2006.202.01:26:00.65#ibcon#end of sib2, iclass 2, count 2 2006.202.01:26:00.65#ibcon#*after write, iclass 2, count 2 2006.202.01:26:00.65#ibcon#*before return 0, iclass 2, count 2 2006.202.01:26:00.65#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:00.65#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:00.65#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.202.01:26:00.65#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:00.65#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:00.77#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:00.77#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:00.77#ibcon#enter wrdev, iclass 2, count 0 2006.202.01:26:00.77#ibcon#first serial, iclass 2, count 0 2006.202.01:26:00.77#ibcon#enter sib2, iclass 2, count 0 2006.202.01:26:00.77#ibcon#flushed, iclass 2, count 0 2006.202.01:26:00.77#ibcon#about to write, iclass 2, count 0 2006.202.01:26:00.77#ibcon#wrote, iclass 2, count 0 2006.202.01:26:00.77#ibcon#about to read 3, iclass 2, count 0 2006.202.01:26:00.79#ibcon#read 3, iclass 2, count 0 2006.202.01:26:00.79#ibcon#about to read 4, iclass 2, count 0 2006.202.01:26:00.79#ibcon#read 4, iclass 2, count 0 2006.202.01:26:00.79#ibcon#about to read 5, iclass 2, count 0 2006.202.01:26:00.79#ibcon#read 5, iclass 2, count 0 2006.202.01:26:00.79#ibcon#about to read 6, iclass 2, count 0 2006.202.01:26:00.79#ibcon#read 6, iclass 2, count 0 2006.202.01:26:00.79#ibcon#end of sib2, iclass 2, count 0 2006.202.01:26:00.79#ibcon#*mode == 0, iclass 2, count 0 2006.202.01:26:00.79#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.01:26:00.79#ibcon#[25=USB\r\n] 2006.202.01:26:00.79#ibcon#*before write, iclass 2, count 0 2006.202.01:26:00.79#ibcon#enter sib2, iclass 2, count 0 2006.202.01:26:00.79#ibcon#flushed, iclass 2, count 0 2006.202.01:26:00.79#ibcon#about to write, iclass 2, count 0 2006.202.01:26:00.79#ibcon#wrote, iclass 2, count 0 2006.202.01:26:00.79#ibcon#about to read 3, iclass 2, count 0 2006.202.01:26:00.82#ibcon#read 3, iclass 2, count 0 2006.202.01:26:00.82#ibcon#about to read 4, iclass 2, count 0 2006.202.01:26:00.82#ibcon#read 4, iclass 2, count 0 2006.202.01:26:00.82#ibcon#about to read 5, iclass 2, count 0 2006.202.01:26:00.82#ibcon#read 5, iclass 2, count 0 2006.202.01:26:00.82#ibcon#about to read 6, iclass 2, count 0 2006.202.01:26:00.82#ibcon#read 6, iclass 2, count 0 2006.202.01:26:00.82#ibcon#end of sib2, iclass 2, count 0 2006.202.01:26:00.82#ibcon#*after write, iclass 2, count 0 2006.202.01:26:00.82#ibcon#*before return 0, iclass 2, count 0 2006.202.01:26:00.82#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:00.82#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:00.82#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.01:26:00.82#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.01:26:00.82$vck44/valo=8,884.99 2006.202.01:26:00.82#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.202.01:26:00.82#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.202.01:26:00.82#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:00.82#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:00.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:00.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:00.82#ibcon#enter wrdev, iclass 5, count 0 2006.202.01:26:00.82#ibcon#first serial, iclass 5, count 0 2006.202.01:26:00.82#ibcon#enter sib2, iclass 5, count 0 2006.202.01:26:00.82#ibcon#flushed, iclass 5, count 0 2006.202.01:26:00.82#ibcon#about to write, iclass 5, count 0 2006.202.01:26:00.82#ibcon#wrote, iclass 5, count 0 2006.202.01:26:00.82#ibcon#about to read 3, iclass 5, count 0 2006.202.01:26:00.84#ibcon#read 3, iclass 5, count 0 2006.202.01:26:00.84#ibcon#about to read 4, iclass 5, count 0 2006.202.01:26:00.84#ibcon#read 4, iclass 5, count 0 2006.202.01:26:00.84#ibcon#about to read 5, iclass 5, count 0 2006.202.01:26:00.84#ibcon#read 5, iclass 5, count 0 2006.202.01:26:00.84#ibcon#about to read 6, iclass 5, count 0 2006.202.01:26:00.84#ibcon#read 6, iclass 5, count 0 2006.202.01:26:00.84#ibcon#end of sib2, iclass 5, count 0 2006.202.01:26:00.84#ibcon#*mode == 0, iclass 5, count 0 2006.202.01:26:00.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.01:26:00.84#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.01:26:00.84#ibcon#*before write, iclass 5, count 0 2006.202.01:26:00.84#ibcon#enter sib2, iclass 5, count 0 2006.202.01:26:00.84#ibcon#flushed, iclass 5, count 0 2006.202.01:26:00.84#ibcon#about to write, iclass 5, count 0 2006.202.01:26:00.84#ibcon#wrote, iclass 5, count 0 2006.202.01:26:00.84#ibcon#about to read 3, iclass 5, count 0 2006.202.01:26:00.88#ibcon#read 3, iclass 5, count 0 2006.202.01:26:00.88#ibcon#about to read 4, iclass 5, count 0 2006.202.01:26:00.88#ibcon#read 4, iclass 5, count 0 2006.202.01:26:00.88#ibcon#about to read 5, iclass 5, count 0 2006.202.01:26:00.88#ibcon#read 5, iclass 5, count 0 2006.202.01:26:00.88#ibcon#about to read 6, iclass 5, count 0 2006.202.01:26:00.88#ibcon#read 6, iclass 5, count 0 2006.202.01:26:00.88#ibcon#end of sib2, iclass 5, count 0 2006.202.01:26:00.88#ibcon#*after write, iclass 5, count 0 2006.202.01:26:00.88#ibcon#*before return 0, iclass 5, count 0 2006.202.01:26:00.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:00.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:00.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.01:26:00.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.01:26:00.88$vck44/va=8,4 2006.202.01:26:00.88#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.202.01:26:00.88#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.202.01:26:00.88#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:00.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.01:26:00.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.202.01:26:00.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.01:26:00.94#ibcon#enter wrdev, iclass 7, count 2 2006.202.01:26:00.94#ibcon#first serial, iclass 7, count 2 2006.202.01:26:00.94#ibcon#enter sib2, iclass 7, count 2 2006.202.01:26:00.94#ibcon#flushed, iclass 7, count 2 2006.202.01:26:00.94#ibcon#about to write, iclass 7, count 2 2006.202.01:26:00.94#ibcon#wrote, iclass 7, count 2 2006.202.01:26:00.94#ibcon#about to read 3, iclass 7, count 2 2006.202.01:26:00.96#ibcon#read 3, iclass 7, count 2 2006.202.01:26:00.96#ibcon#about to read 4, iclass 7, count 2 2006.202.01:26:00.96#ibcon#read 4, iclass 7, count 2 2006.202.01:26:00.96#ibcon#about to read 5, iclass 7, count 2 2006.202.01:26:00.96#ibcon#read 5, iclass 7, count 2 2006.202.01:26:00.96#ibcon#about to read 6, iclass 7, count 2 2006.202.01:26:00.96#ibcon#read 6, iclass 7, count 2 2006.202.01:26:00.96#ibcon#end of sib2, iclass 7, count 2 2006.202.01:26:00.96#ibcon#*mode == 0, iclass 7, count 2 2006.202.01:26:00.96#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.202.01:26:00.96#ibcon#[25=AT08-04\r\n] 2006.202.01:26:00.96#ibcon#*before write, iclass 7, count 2 2006.202.01:26:00.96#ibcon#enter sib2, iclass 7, count 2 2006.202.01:26:00.96#ibcon#flushed, iclass 7, count 2 2006.202.01:26:00.96#ibcon#about to write, iclass 7, count 2 2006.202.01:26:00.96#ibcon#wrote, iclass 7, count 2 2006.202.01:26:00.96#ibcon#about to read 3, iclass 7, count 2 2006.202.01:26:00.99#ibcon#read 3, iclass 7, count 2 2006.202.01:26:00.99#ibcon#about to read 4, iclass 7, count 2 2006.202.01:26:00.99#ibcon#read 4, iclass 7, count 2 2006.202.01:26:00.99#ibcon#about to read 5, iclass 7, count 2 2006.202.01:26:00.99#ibcon#read 5, iclass 7, count 2 2006.202.01:26:00.99#ibcon#about to read 6, iclass 7, count 2 2006.202.01:26:00.99#ibcon#read 6, iclass 7, count 2 2006.202.01:26:00.99#ibcon#end of sib2, iclass 7, count 2 2006.202.01:26:00.99#ibcon#*after write, iclass 7, count 2 2006.202.01:26:00.99#ibcon#*before return 0, iclass 7, count 2 2006.202.01:26:00.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.202.01:26:00.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.202.01:26:00.99#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.202.01:26:00.99#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:00.99#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.01:26:01.11#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.202.01:26:01.11#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.01:26:01.11#ibcon#enter wrdev, iclass 7, count 0 2006.202.01:26:01.11#ibcon#first serial, iclass 7, count 0 2006.202.01:26:01.11#ibcon#enter sib2, iclass 7, count 0 2006.202.01:26:01.11#ibcon#flushed, iclass 7, count 0 2006.202.01:26:01.11#ibcon#about to write, iclass 7, count 0 2006.202.01:26:01.11#ibcon#wrote, iclass 7, count 0 2006.202.01:26:01.11#ibcon#about to read 3, iclass 7, count 0 2006.202.01:26:01.13#ibcon#read 3, iclass 7, count 0 2006.202.01:26:01.13#ibcon#about to read 4, iclass 7, count 0 2006.202.01:26:01.13#ibcon#read 4, iclass 7, count 0 2006.202.01:26:01.13#ibcon#about to read 5, iclass 7, count 0 2006.202.01:26:01.13#ibcon#read 5, iclass 7, count 0 2006.202.01:26:01.13#ibcon#about to read 6, iclass 7, count 0 2006.202.01:26:01.13#ibcon#read 6, iclass 7, count 0 2006.202.01:26:01.13#ibcon#end of sib2, iclass 7, count 0 2006.202.01:26:01.13#ibcon#*mode == 0, iclass 7, count 0 2006.202.01:26:01.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.01:26:01.13#ibcon#[25=USB\r\n] 2006.202.01:26:01.13#ibcon#*before write, iclass 7, count 0 2006.202.01:26:01.13#ibcon#enter sib2, iclass 7, count 0 2006.202.01:26:01.13#ibcon#flushed, iclass 7, count 0 2006.202.01:26:01.13#ibcon#about to write, iclass 7, count 0 2006.202.01:26:01.13#ibcon#wrote, iclass 7, count 0 2006.202.01:26:01.13#ibcon#about to read 3, iclass 7, count 0 2006.202.01:26:01.16#ibcon#read 3, iclass 7, count 0 2006.202.01:26:01.16#ibcon#about to read 4, iclass 7, count 0 2006.202.01:26:01.16#ibcon#read 4, iclass 7, count 0 2006.202.01:26:01.16#ibcon#about to read 5, iclass 7, count 0 2006.202.01:26:01.16#ibcon#read 5, iclass 7, count 0 2006.202.01:26:01.16#ibcon#about to read 6, iclass 7, count 0 2006.202.01:26:01.16#ibcon#read 6, iclass 7, count 0 2006.202.01:26:01.16#ibcon#end of sib2, iclass 7, count 0 2006.202.01:26:01.16#ibcon#*after write, iclass 7, count 0 2006.202.01:26:01.16#ibcon#*before return 0, iclass 7, count 0 2006.202.01:26:01.16#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.202.01:26:01.16#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.202.01:26:01.16#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.01:26:01.16#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.01:26:01.16$vck44/vblo=1,629.99 2006.202.01:26:01.16#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.202.01:26:01.16#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.202.01:26:01.16#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:01.16#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:26:01.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:26:01.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:26:01.16#ibcon#enter wrdev, iclass 11, count 0 2006.202.01:26:01.16#ibcon#first serial, iclass 11, count 0 2006.202.01:26:01.16#ibcon#enter sib2, iclass 11, count 0 2006.202.01:26:01.16#ibcon#flushed, iclass 11, count 0 2006.202.01:26:01.16#ibcon#about to write, iclass 11, count 0 2006.202.01:26:01.16#ibcon#wrote, iclass 11, count 0 2006.202.01:26:01.16#ibcon#about to read 3, iclass 11, count 0 2006.202.01:26:01.18#ibcon#read 3, iclass 11, count 0 2006.202.01:26:01.18#ibcon#about to read 4, iclass 11, count 0 2006.202.01:26:01.18#ibcon#read 4, iclass 11, count 0 2006.202.01:26:01.18#ibcon#about to read 5, iclass 11, count 0 2006.202.01:26:01.18#ibcon#read 5, iclass 11, count 0 2006.202.01:26:01.18#ibcon#about to read 6, iclass 11, count 0 2006.202.01:26:01.18#ibcon#read 6, iclass 11, count 0 2006.202.01:26:01.18#ibcon#end of sib2, iclass 11, count 0 2006.202.01:26:01.18#ibcon#*mode == 0, iclass 11, count 0 2006.202.01:26:01.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.01:26:01.18#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.01:26:01.18#ibcon#*before write, iclass 11, count 0 2006.202.01:26:01.18#ibcon#enter sib2, iclass 11, count 0 2006.202.01:26:01.18#ibcon#flushed, iclass 11, count 0 2006.202.01:26:01.18#ibcon#about to write, iclass 11, count 0 2006.202.01:26:01.18#ibcon#wrote, iclass 11, count 0 2006.202.01:26:01.18#ibcon#about to read 3, iclass 11, count 0 2006.202.01:26:01.22#ibcon#read 3, iclass 11, count 0 2006.202.01:26:01.22#ibcon#about to read 4, iclass 11, count 0 2006.202.01:26:01.22#ibcon#read 4, iclass 11, count 0 2006.202.01:26:01.22#ibcon#about to read 5, iclass 11, count 0 2006.202.01:26:01.22#ibcon#read 5, iclass 11, count 0 2006.202.01:26:01.22#ibcon#about to read 6, iclass 11, count 0 2006.202.01:26:01.22#ibcon#read 6, iclass 11, count 0 2006.202.01:26:01.22#ibcon#end of sib2, iclass 11, count 0 2006.202.01:26:01.22#ibcon#*after write, iclass 11, count 0 2006.202.01:26:01.22#ibcon#*before return 0, iclass 11, count 0 2006.202.01:26:01.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:26:01.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.202.01:26:01.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.01:26:01.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.01:26:01.22$vck44/vb=1,4 2006.202.01:26:01.22#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.202.01:26:01.22#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.202.01:26:01.22#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:01.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:26:01.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:26:01.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:26:01.22#ibcon#enter wrdev, iclass 13, count 2 2006.202.01:26:01.22#ibcon#first serial, iclass 13, count 2 2006.202.01:26:01.22#ibcon#enter sib2, iclass 13, count 2 2006.202.01:26:01.22#ibcon#flushed, iclass 13, count 2 2006.202.01:26:01.22#ibcon#about to write, iclass 13, count 2 2006.202.01:26:01.22#ibcon#wrote, iclass 13, count 2 2006.202.01:26:01.22#ibcon#about to read 3, iclass 13, count 2 2006.202.01:26:01.24#ibcon#read 3, iclass 13, count 2 2006.202.01:26:01.24#ibcon#about to read 4, iclass 13, count 2 2006.202.01:26:01.24#ibcon#read 4, iclass 13, count 2 2006.202.01:26:01.24#ibcon#about to read 5, iclass 13, count 2 2006.202.01:26:01.24#ibcon#read 5, iclass 13, count 2 2006.202.01:26:01.24#ibcon#about to read 6, iclass 13, count 2 2006.202.01:26:01.24#ibcon#read 6, iclass 13, count 2 2006.202.01:26:01.24#ibcon#end of sib2, iclass 13, count 2 2006.202.01:26:01.24#ibcon#*mode == 0, iclass 13, count 2 2006.202.01:26:01.24#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.202.01:26:01.24#ibcon#[27=AT01-04\r\n] 2006.202.01:26:01.24#ibcon#*before write, iclass 13, count 2 2006.202.01:26:01.24#ibcon#enter sib2, iclass 13, count 2 2006.202.01:26:01.24#ibcon#flushed, iclass 13, count 2 2006.202.01:26:01.24#ibcon#about to write, iclass 13, count 2 2006.202.01:26:01.24#ibcon#wrote, iclass 13, count 2 2006.202.01:26:01.24#ibcon#about to read 3, iclass 13, count 2 2006.202.01:26:01.27#ibcon#read 3, iclass 13, count 2 2006.202.01:26:01.27#ibcon#about to read 4, iclass 13, count 2 2006.202.01:26:01.27#ibcon#read 4, iclass 13, count 2 2006.202.01:26:01.27#ibcon#about to read 5, iclass 13, count 2 2006.202.01:26:01.27#ibcon#read 5, iclass 13, count 2 2006.202.01:26:01.27#ibcon#about to read 6, iclass 13, count 2 2006.202.01:26:01.27#ibcon#read 6, iclass 13, count 2 2006.202.01:26:01.27#ibcon#end of sib2, iclass 13, count 2 2006.202.01:26:01.27#ibcon#*after write, iclass 13, count 2 2006.202.01:26:01.27#ibcon#*before return 0, iclass 13, count 2 2006.202.01:26:01.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:26:01.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.202.01:26:01.27#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.202.01:26:01.27#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:01.27#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:26:01.39#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:26:01.39#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:26:01.39#ibcon#enter wrdev, iclass 13, count 0 2006.202.01:26:01.39#ibcon#first serial, iclass 13, count 0 2006.202.01:26:01.39#ibcon#enter sib2, iclass 13, count 0 2006.202.01:26:01.39#ibcon#flushed, iclass 13, count 0 2006.202.01:26:01.39#ibcon#about to write, iclass 13, count 0 2006.202.01:26:01.39#ibcon#wrote, iclass 13, count 0 2006.202.01:26:01.39#ibcon#about to read 3, iclass 13, count 0 2006.202.01:26:01.41#ibcon#read 3, iclass 13, count 0 2006.202.01:26:01.41#ibcon#about to read 4, iclass 13, count 0 2006.202.01:26:01.41#ibcon#read 4, iclass 13, count 0 2006.202.01:26:01.41#ibcon#about to read 5, iclass 13, count 0 2006.202.01:26:01.41#ibcon#read 5, iclass 13, count 0 2006.202.01:26:01.41#ibcon#about to read 6, iclass 13, count 0 2006.202.01:26:01.41#ibcon#read 6, iclass 13, count 0 2006.202.01:26:01.41#ibcon#end of sib2, iclass 13, count 0 2006.202.01:26:01.41#ibcon#*mode == 0, iclass 13, count 0 2006.202.01:26:01.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.01:26:01.41#ibcon#[27=USB\r\n] 2006.202.01:26:01.41#ibcon#*before write, iclass 13, count 0 2006.202.01:26:01.41#ibcon#enter sib2, iclass 13, count 0 2006.202.01:26:01.41#ibcon#flushed, iclass 13, count 0 2006.202.01:26:01.41#ibcon#about to write, iclass 13, count 0 2006.202.01:26:01.41#ibcon#wrote, iclass 13, count 0 2006.202.01:26:01.41#ibcon#about to read 3, iclass 13, count 0 2006.202.01:26:01.44#ibcon#read 3, iclass 13, count 0 2006.202.01:26:01.44#ibcon#about to read 4, iclass 13, count 0 2006.202.01:26:01.44#ibcon#read 4, iclass 13, count 0 2006.202.01:26:01.44#ibcon#about to read 5, iclass 13, count 0 2006.202.01:26:01.44#ibcon#read 5, iclass 13, count 0 2006.202.01:26:01.44#ibcon#about to read 6, iclass 13, count 0 2006.202.01:26:01.44#ibcon#read 6, iclass 13, count 0 2006.202.01:26:01.44#ibcon#end of sib2, iclass 13, count 0 2006.202.01:26:01.44#ibcon#*after write, iclass 13, count 0 2006.202.01:26:01.44#ibcon#*before return 0, iclass 13, count 0 2006.202.01:26:01.44#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:26:01.44#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.202.01:26:01.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.01:26:01.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.01:26:01.44$vck44/vblo=2,634.99 2006.202.01:26:01.44#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.202.01:26:01.44#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.202.01:26:01.44#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:01.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:26:01.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:26:01.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:26:01.44#ibcon#enter wrdev, iclass 15, count 0 2006.202.01:26:01.44#ibcon#first serial, iclass 15, count 0 2006.202.01:26:01.44#ibcon#enter sib2, iclass 15, count 0 2006.202.01:26:01.44#ibcon#flushed, iclass 15, count 0 2006.202.01:26:01.44#ibcon#about to write, iclass 15, count 0 2006.202.01:26:01.44#ibcon#wrote, iclass 15, count 0 2006.202.01:26:01.44#ibcon#about to read 3, iclass 15, count 0 2006.202.01:26:01.46#ibcon#read 3, iclass 15, count 0 2006.202.01:26:01.46#ibcon#about to read 4, iclass 15, count 0 2006.202.01:26:01.46#ibcon#read 4, iclass 15, count 0 2006.202.01:26:01.46#ibcon#about to read 5, iclass 15, count 0 2006.202.01:26:01.46#ibcon#read 5, iclass 15, count 0 2006.202.01:26:01.46#ibcon#about to read 6, iclass 15, count 0 2006.202.01:26:01.46#ibcon#read 6, iclass 15, count 0 2006.202.01:26:01.46#ibcon#end of sib2, iclass 15, count 0 2006.202.01:26:01.46#ibcon#*mode == 0, iclass 15, count 0 2006.202.01:26:01.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.01:26:01.46#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.01:26:01.46#ibcon#*before write, iclass 15, count 0 2006.202.01:26:01.46#ibcon#enter sib2, iclass 15, count 0 2006.202.01:26:01.46#ibcon#flushed, iclass 15, count 0 2006.202.01:26:01.46#ibcon#about to write, iclass 15, count 0 2006.202.01:26:01.46#ibcon#wrote, iclass 15, count 0 2006.202.01:26:01.46#ibcon#about to read 3, iclass 15, count 0 2006.202.01:26:01.50#ibcon#read 3, iclass 15, count 0 2006.202.01:26:01.50#ibcon#about to read 4, iclass 15, count 0 2006.202.01:26:01.50#ibcon#read 4, iclass 15, count 0 2006.202.01:26:01.50#ibcon#about to read 5, iclass 15, count 0 2006.202.01:26:01.50#ibcon#read 5, iclass 15, count 0 2006.202.01:26:01.50#ibcon#about to read 6, iclass 15, count 0 2006.202.01:26:01.50#ibcon#read 6, iclass 15, count 0 2006.202.01:26:01.50#ibcon#end of sib2, iclass 15, count 0 2006.202.01:26:01.50#ibcon#*after write, iclass 15, count 0 2006.202.01:26:01.50#ibcon#*before return 0, iclass 15, count 0 2006.202.01:26:01.50#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:26:01.50#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.202.01:26:01.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.01:26:01.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.01:26:01.50$vck44/vb=2,5 2006.202.01:26:01.50#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.202.01:26:01.50#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.202.01:26:01.50#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:01.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:26:01.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:26:01.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:26:01.56#ibcon#enter wrdev, iclass 17, count 2 2006.202.01:26:01.56#ibcon#first serial, iclass 17, count 2 2006.202.01:26:01.56#ibcon#enter sib2, iclass 17, count 2 2006.202.01:26:01.56#ibcon#flushed, iclass 17, count 2 2006.202.01:26:01.56#ibcon#about to write, iclass 17, count 2 2006.202.01:26:01.56#ibcon#wrote, iclass 17, count 2 2006.202.01:26:01.56#ibcon#about to read 3, iclass 17, count 2 2006.202.01:26:01.58#ibcon#read 3, iclass 17, count 2 2006.202.01:26:01.58#ibcon#about to read 4, iclass 17, count 2 2006.202.01:26:01.58#ibcon#read 4, iclass 17, count 2 2006.202.01:26:01.58#ibcon#about to read 5, iclass 17, count 2 2006.202.01:26:01.58#ibcon#read 5, iclass 17, count 2 2006.202.01:26:01.58#ibcon#about to read 6, iclass 17, count 2 2006.202.01:26:01.58#ibcon#read 6, iclass 17, count 2 2006.202.01:26:01.58#ibcon#end of sib2, iclass 17, count 2 2006.202.01:26:01.58#ibcon#*mode == 0, iclass 17, count 2 2006.202.01:26:01.58#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.202.01:26:01.58#ibcon#[27=AT02-05\r\n] 2006.202.01:26:01.58#ibcon#*before write, iclass 17, count 2 2006.202.01:26:01.58#ibcon#enter sib2, iclass 17, count 2 2006.202.01:26:01.58#ibcon#flushed, iclass 17, count 2 2006.202.01:26:01.58#ibcon#about to write, iclass 17, count 2 2006.202.01:26:01.58#ibcon#wrote, iclass 17, count 2 2006.202.01:26:01.58#ibcon#about to read 3, iclass 17, count 2 2006.202.01:26:01.61#ibcon#read 3, iclass 17, count 2 2006.202.01:26:01.61#ibcon#about to read 4, iclass 17, count 2 2006.202.01:26:01.61#ibcon#read 4, iclass 17, count 2 2006.202.01:26:01.61#ibcon#about to read 5, iclass 17, count 2 2006.202.01:26:01.61#ibcon#read 5, iclass 17, count 2 2006.202.01:26:01.61#ibcon#about to read 6, iclass 17, count 2 2006.202.01:26:01.61#ibcon#read 6, iclass 17, count 2 2006.202.01:26:01.61#ibcon#end of sib2, iclass 17, count 2 2006.202.01:26:01.61#ibcon#*after write, iclass 17, count 2 2006.202.01:26:01.61#ibcon#*before return 0, iclass 17, count 2 2006.202.01:26:01.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:26:01.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.202.01:26:01.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.202.01:26:01.74#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:01.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:26:01.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:26:01.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:26:01.86#ibcon#enter wrdev, iclass 17, count 0 2006.202.01:26:01.86#ibcon#first serial, iclass 17, count 0 2006.202.01:26:01.86#ibcon#enter sib2, iclass 17, count 0 2006.202.01:26:01.86#ibcon#flushed, iclass 17, count 0 2006.202.01:26:01.86#ibcon#about to write, iclass 17, count 0 2006.202.01:26:01.86#ibcon#wrote, iclass 17, count 0 2006.202.01:26:01.86#ibcon#about to read 3, iclass 17, count 0 2006.202.01:26:01.88#ibcon#read 3, iclass 17, count 0 2006.202.01:26:01.88#ibcon#about to read 4, iclass 17, count 0 2006.202.01:26:01.88#ibcon#read 4, iclass 17, count 0 2006.202.01:26:01.88#ibcon#about to read 5, iclass 17, count 0 2006.202.01:26:01.88#ibcon#read 5, iclass 17, count 0 2006.202.01:26:01.88#ibcon#about to read 6, iclass 17, count 0 2006.202.01:26:01.88#ibcon#read 6, iclass 17, count 0 2006.202.01:26:01.88#ibcon#end of sib2, iclass 17, count 0 2006.202.01:26:01.88#ibcon#*mode == 0, iclass 17, count 0 2006.202.01:26:01.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.01:26:01.88#ibcon#[27=USB\r\n] 2006.202.01:26:01.88#ibcon#*before write, iclass 17, count 0 2006.202.01:26:01.88#ibcon#enter sib2, iclass 17, count 0 2006.202.01:26:01.88#ibcon#flushed, iclass 17, count 0 2006.202.01:26:01.88#ibcon#about to write, iclass 17, count 0 2006.202.01:26:01.88#ibcon#wrote, iclass 17, count 0 2006.202.01:26:01.88#ibcon#about to read 3, iclass 17, count 0 2006.202.01:26:01.91#ibcon#read 3, iclass 17, count 0 2006.202.01:26:01.91#ibcon#about to read 4, iclass 17, count 0 2006.202.01:26:01.91#ibcon#read 4, iclass 17, count 0 2006.202.01:26:01.91#ibcon#about to read 5, iclass 17, count 0 2006.202.01:26:01.91#ibcon#read 5, iclass 17, count 0 2006.202.01:26:01.91#ibcon#about to read 6, iclass 17, count 0 2006.202.01:26:01.91#ibcon#read 6, iclass 17, count 0 2006.202.01:26:01.91#ibcon#end of sib2, iclass 17, count 0 2006.202.01:26:01.91#ibcon#*after write, iclass 17, count 0 2006.202.01:26:01.91#ibcon#*before return 0, iclass 17, count 0 2006.202.01:26:01.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:26:01.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.202.01:26:01.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.01:26:01.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.01:26:01.91$vck44/vblo=3,649.99 2006.202.01:26:01.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.202.01:26:01.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.202.01:26:01.91#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:01.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:26:01.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:26:01.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:26:01.91#ibcon#enter wrdev, iclass 19, count 0 2006.202.01:26:01.91#ibcon#first serial, iclass 19, count 0 2006.202.01:26:01.91#ibcon#enter sib2, iclass 19, count 0 2006.202.01:26:01.91#ibcon#flushed, iclass 19, count 0 2006.202.01:26:01.91#ibcon#about to write, iclass 19, count 0 2006.202.01:26:01.91#ibcon#wrote, iclass 19, count 0 2006.202.01:26:01.91#ibcon#about to read 3, iclass 19, count 0 2006.202.01:26:01.93#ibcon#read 3, iclass 19, count 0 2006.202.01:26:01.93#ibcon#about to read 4, iclass 19, count 0 2006.202.01:26:01.93#ibcon#read 4, iclass 19, count 0 2006.202.01:26:01.93#ibcon#about to read 5, iclass 19, count 0 2006.202.01:26:01.93#ibcon#read 5, iclass 19, count 0 2006.202.01:26:01.93#ibcon#about to read 6, iclass 19, count 0 2006.202.01:26:01.93#ibcon#read 6, iclass 19, count 0 2006.202.01:26:01.93#ibcon#end of sib2, iclass 19, count 0 2006.202.01:26:01.93#ibcon#*mode == 0, iclass 19, count 0 2006.202.01:26:01.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.01:26:01.93#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.01:26:01.93#ibcon#*before write, iclass 19, count 0 2006.202.01:26:01.93#ibcon#enter sib2, iclass 19, count 0 2006.202.01:26:01.93#ibcon#flushed, iclass 19, count 0 2006.202.01:26:01.93#ibcon#about to write, iclass 19, count 0 2006.202.01:26:01.93#ibcon#wrote, iclass 19, count 0 2006.202.01:26:01.93#ibcon#about to read 3, iclass 19, count 0 2006.202.01:26:01.97#ibcon#read 3, iclass 19, count 0 2006.202.01:26:01.97#ibcon#about to read 4, iclass 19, count 0 2006.202.01:26:01.97#ibcon#read 4, iclass 19, count 0 2006.202.01:26:01.97#ibcon#about to read 5, iclass 19, count 0 2006.202.01:26:01.97#ibcon#read 5, iclass 19, count 0 2006.202.01:26:01.97#ibcon#about to read 6, iclass 19, count 0 2006.202.01:26:01.97#ibcon#read 6, iclass 19, count 0 2006.202.01:26:01.97#ibcon#end of sib2, iclass 19, count 0 2006.202.01:26:01.97#ibcon#*after write, iclass 19, count 0 2006.202.01:26:01.97#ibcon#*before return 0, iclass 19, count 0 2006.202.01:26:01.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:26:01.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.202.01:26:01.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.01:26:01.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.01:26:01.97$vck44/vb=3,4 2006.202.01:26:01.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.202.01:26:01.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.202.01:26:01.97#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:01.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:26:02.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:26:02.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:26:02.03#ibcon#enter wrdev, iclass 21, count 2 2006.202.01:26:02.03#ibcon#first serial, iclass 21, count 2 2006.202.01:26:02.03#ibcon#enter sib2, iclass 21, count 2 2006.202.01:26:02.03#ibcon#flushed, iclass 21, count 2 2006.202.01:26:02.03#ibcon#about to write, iclass 21, count 2 2006.202.01:26:02.03#ibcon#wrote, iclass 21, count 2 2006.202.01:26:02.03#ibcon#about to read 3, iclass 21, count 2 2006.202.01:26:02.05#ibcon#read 3, iclass 21, count 2 2006.202.01:26:02.05#ibcon#about to read 4, iclass 21, count 2 2006.202.01:26:02.05#ibcon#read 4, iclass 21, count 2 2006.202.01:26:02.05#ibcon#about to read 5, iclass 21, count 2 2006.202.01:26:02.05#ibcon#read 5, iclass 21, count 2 2006.202.01:26:02.05#ibcon#about to read 6, iclass 21, count 2 2006.202.01:26:02.05#ibcon#read 6, iclass 21, count 2 2006.202.01:26:02.05#ibcon#end of sib2, iclass 21, count 2 2006.202.01:26:02.05#ibcon#*mode == 0, iclass 21, count 2 2006.202.01:26:02.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.202.01:26:02.05#ibcon#[27=AT03-04\r\n] 2006.202.01:26:02.05#ibcon#*before write, iclass 21, count 2 2006.202.01:26:02.05#ibcon#enter sib2, iclass 21, count 2 2006.202.01:26:02.05#ibcon#flushed, iclass 21, count 2 2006.202.01:26:02.05#ibcon#about to write, iclass 21, count 2 2006.202.01:26:02.05#ibcon#wrote, iclass 21, count 2 2006.202.01:26:02.05#ibcon#about to read 3, iclass 21, count 2 2006.202.01:26:02.08#ibcon#read 3, iclass 21, count 2 2006.202.01:26:02.08#ibcon#about to read 4, iclass 21, count 2 2006.202.01:26:02.08#ibcon#read 4, iclass 21, count 2 2006.202.01:26:02.08#ibcon#about to read 5, iclass 21, count 2 2006.202.01:26:02.08#ibcon#read 5, iclass 21, count 2 2006.202.01:26:02.08#ibcon#about to read 6, iclass 21, count 2 2006.202.01:26:02.08#ibcon#read 6, iclass 21, count 2 2006.202.01:26:02.08#ibcon#end of sib2, iclass 21, count 2 2006.202.01:26:02.08#ibcon#*after write, iclass 21, count 2 2006.202.01:26:02.08#ibcon#*before return 0, iclass 21, count 2 2006.202.01:26:02.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:26:02.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.202.01:26:02.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.202.01:26:02.08#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:02.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:26:02.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:26:02.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:26:02.20#ibcon#enter wrdev, iclass 21, count 0 2006.202.01:26:02.20#ibcon#first serial, iclass 21, count 0 2006.202.01:26:02.20#ibcon#enter sib2, iclass 21, count 0 2006.202.01:26:02.20#ibcon#flushed, iclass 21, count 0 2006.202.01:26:02.20#ibcon#about to write, iclass 21, count 0 2006.202.01:26:02.20#ibcon#wrote, iclass 21, count 0 2006.202.01:26:02.20#ibcon#about to read 3, iclass 21, count 0 2006.202.01:26:02.22#ibcon#read 3, iclass 21, count 0 2006.202.01:26:02.22#ibcon#about to read 4, iclass 21, count 0 2006.202.01:26:02.22#ibcon#read 4, iclass 21, count 0 2006.202.01:26:02.22#ibcon#about to read 5, iclass 21, count 0 2006.202.01:26:02.22#ibcon#read 5, iclass 21, count 0 2006.202.01:26:02.22#ibcon#about to read 6, iclass 21, count 0 2006.202.01:26:02.22#ibcon#read 6, iclass 21, count 0 2006.202.01:26:02.22#ibcon#end of sib2, iclass 21, count 0 2006.202.01:26:02.22#ibcon#*mode == 0, iclass 21, count 0 2006.202.01:26:02.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.01:26:02.22#ibcon#[27=USB\r\n] 2006.202.01:26:02.22#ibcon#*before write, iclass 21, count 0 2006.202.01:26:02.22#ibcon#enter sib2, iclass 21, count 0 2006.202.01:26:02.22#ibcon#flushed, iclass 21, count 0 2006.202.01:26:02.22#ibcon#about to write, iclass 21, count 0 2006.202.01:26:02.22#ibcon#wrote, iclass 21, count 0 2006.202.01:26:02.22#ibcon#about to read 3, iclass 21, count 0 2006.202.01:26:02.25#ibcon#read 3, iclass 21, count 0 2006.202.01:26:02.25#ibcon#about to read 4, iclass 21, count 0 2006.202.01:26:02.25#ibcon#read 4, iclass 21, count 0 2006.202.01:26:02.25#ibcon#about to read 5, iclass 21, count 0 2006.202.01:26:02.25#ibcon#read 5, iclass 21, count 0 2006.202.01:26:02.25#ibcon#about to read 6, iclass 21, count 0 2006.202.01:26:02.25#ibcon#read 6, iclass 21, count 0 2006.202.01:26:02.25#ibcon#end of sib2, iclass 21, count 0 2006.202.01:26:02.25#ibcon#*after write, iclass 21, count 0 2006.202.01:26:02.25#ibcon#*before return 0, iclass 21, count 0 2006.202.01:26:02.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:26:02.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.202.01:26:02.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.01:26:02.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.01:26:02.25$vck44/vblo=4,679.99 2006.202.01:26:02.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.01:26:02.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.01:26:02.25#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:02.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:26:02.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:26:02.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:26:02.25#ibcon#enter wrdev, iclass 23, count 0 2006.202.01:26:02.25#ibcon#first serial, iclass 23, count 0 2006.202.01:26:02.25#ibcon#enter sib2, iclass 23, count 0 2006.202.01:26:02.25#ibcon#flushed, iclass 23, count 0 2006.202.01:26:02.25#ibcon#about to write, iclass 23, count 0 2006.202.01:26:02.25#ibcon#wrote, iclass 23, count 0 2006.202.01:26:02.25#ibcon#about to read 3, iclass 23, count 0 2006.202.01:26:02.27#ibcon#read 3, iclass 23, count 0 2006.202.01:26:02.27#ibcon#about to read 4, iclass 23, count 0 2006.202.01:26:02.27#ibcon#read 4, iclass 23, count 0 2006.202.01:26:02.27#ibcon#about to read 5, iclass 23, count 0 2006.202.01:26:02.27#ibcon#read 5, iclass 23, count 0 2006.202.01:26:02.27#ibcon#about to read 6, iclass 23, count 0 2006.202.01:26:02.27#ibcon#read 6, iclass 23, count 0 2006.202.01:26:02.27#ibcon#end of sib2, iclass 23, count 0 2006.202.01:26:02.27#ibcon#*mode == 0, iclass 23, count 0 2006.202.01:26:02.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.01:26:02.27#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.01:26:02.27#ibcon#*before write, iclass 23, count 0 2006.202.01:26:02.27#ibcon#enter sib2, iclass 23, count 0 2006.202.01:26:02.27#ibcon#flushed, iclass 23, count 0 2006.202.01:26:02.27#ibcon#about to write, iclass 23, count 0 2006.202.01:26:02.27#ibcon#wrote, iclass 23, count 0 2006.202.01:26:02.27#ibcon#about to read 3, iclass 23, count 0 2006.202.01:26:02.31#ibcon#read 3, iclass 23, count 0 2006.202.01:26:02.31#ibcon#about to read 4, iclass 23, count 0 2006.202.01:26:02.31#ibcon#read 4, iclass 23, count 0 2006.202.01:26:02.31#ibcon#about to read 5, iclass 23, count 0 2006.202.01:26:02.31#ibcon#read 5, iclass 23, count 0 2006.202.01:26:02.31#ibcon#about to read 6, iclass 23, count 0 2006.202.01:26:02.31#ibcon#read 6, iclass 23, count 0 2006.202.01:26:02.31#ibcon#end of sib2, iclass 23, count 0 2006.202.01:26:02.31#ibcon#*after write, iclass 23, count 0 2006.202.01:26:02.31#ibcon#*before return 0, iclass 23, count 0 2006.202.01:26:02.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:26:02.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:26:02.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.01:26:02.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.01:26:02.31$vck44/vb=4,5 2006.202.01:26:02.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.202.01:26:02.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.202.01:26:02.31#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:02.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.01:26:02.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.202.01:26:02.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.01:26:02.37#ibcon#enter wrdev, iclass 25, count 2 2006.202.01:26:02.37#ibcon#first serial, iclass 25, count 2 2006.202.01:26:02.37#ibcon#enter sib2, iclass 25, count 2 2006.202.01:26:02.37#ibcon#flushed, iclass 25, count 2 2006.202.01:26:02.37#ibcon#about to write, iclass 25, count 2 2006.202.01:26:02.37#ibcon#wrote, iclass 25, count 2 2006.202.01:26:02.37#ibcon#about to read 3, iclass 25, count 2 2006.202.01:26:02.39#ibcon#read 3, iclass 25, count 2 2006.202.01:26:02.39#ibcon#about to read 4, iclass 25, count 2 2006.202.01:26:02.39#ibcon#read 4, iclass 25, count 2 2006.202.01:26:02.39#ibcon#about to read 5, iclass 25, count 2 2006.202.01:26:02.39#ibcon#read 5, iclass 25, count 2 2006.202.01:26:02.39#ibcon#about to read 6, iclass 25, count 2 2006.202.01:26:02.39#ibcon#read 6, iclass 25, count 2 2006.202.01:26:02.39#ibcon#end of sib2, iclass 25, count 2 2006.202.01:26:02.39#ibcon#*mode == 0, iclass 25, count 2 2006.202.01:26:02.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.202.01:26:02.39#ibcon#[27=AT04-05\r\n] 2006.202.01:26:02.39#ibcon#*before write, iclass 25, count 2 2006.202.01:26:02.39#ibcon#enter sib2, iclass 25, count 2 2006.202.01:26:02.39#ibcon#flushed, iclass 25, count 2 2006.202.01:26:02.39#ibcon#about to write, iclass 25, count 2 2006.202.01:26:02.39#ibcon#wrote, iclass 25, count 2 2006.202.01:26:02.39#ibcon#about to read 3, iclass 25, count 2 2006.202.01:26:02.42#ibcon#read 3, iclass 25, count 2 2006.202.01:26:02.42#ibcon#about to read 4, iclass 25, count 2 2006.202.01:26:02.42#ibcon#read 4, iclass 25, count 2 2006.202.01:26:02.42#ibcon#about to read 5, iclass 25, count 2 2006.202.01:26:02.42#ibcon#read 5, iclass 25, count 2 2006.202.01:26:02.42#ibcon#about to read 6, iclass 25, count 2 2006.202.01:26:02.42#ibcon#read 6, iclass 25, count 2 2006.202.01:26:02.42#ibcon#end of sib2, iclass 25, count 2 2006.202.01:26:02.42#ibcon#*after write, iclass 25, count 2 2006.202.01:26:02.42#ibcon#*before return 0, iclass 25, count 2 2006.202.01:26:02.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.202.01:26:02.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.202.01:26:02.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.202.01:26:02.42#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:02.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.01:26:02.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.202.01:26:02.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.01:26:02.54#ibcon#enter wrdev, iclass 25, count 0 2006.202.01:26:02.54#ibcon#first serial, iclass 25, count 0 2006.202.01:26:02.54#ibcon#enter sib2, iclass 25, count 0 2006.202.01:26:02.54#ibcon#flushed, iclass 25, count 0 2006.202.01:26:02.54#ibcon#about to write, iclass 25, count 0 2006.202.01:26:02.54#ibcon#wrote, iclass 25, count 0 2006.202.01:26:02.54#ibcon#about to read 3, iclass 25, count 0 2006.202.01:26:02.56#ibcon#read 3, iclass 25, count 0 2006.202.01:26:02.56#ibcon#about to read 4, iclass 25, count 0 2006.202.01:26:02.56#ibcon#read 4, iclass 25, count 0 2006.202.01:26:02.56#ibcon#about to read 5, iclass 25, count 0 2006.202.01:26:02.56#ibcon#read 5, iclass 25, count 0 2006.202.01:26:02.56#ibcon#about to read 6, iclass 25, count 0 2006.202.01:26:02.56#ibcon#read 6, iclass 25, count 0 2006.202.01:26:02.56#ibcon#end of sib2, iclass 25, count 0 2006.202.01:26:02.56#ibcon#*mode == 0, iclass 25, count 0 2006.202.01:26:02.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.01:26:02.56#ibcon#[27=USB\r\n] 2006.202.01:26:02.56#ibcon#*before write, iclass 25, count 0 2006.202.01:26:02.56#ibcon#enter sib2, iclass 25, count 0 2006.202.01:26:02.56#ibcon#flushed, iclass 25, count 0 2006.202.01:26:02.56#ibcon#about to write, iclass 25, count 0 2006.202.01:26:02.56#ibcon#wrote, iclass 25, count 0 2006.202.01:26:02.56#ibcon#about to read 3, iclass 25, count 0 2006.202.01:26:02.59#ibcon#read 3, iclass 25, count 0 2006.202.01:26:02.59#ibcon#about to read 4, iclass 25, count 0 2006.202.01:26:02.59#ibcon#read 4, iclass 25, count 0 2006.202.01:26:02.59#ibcon#about to read 5, iclass 25, count 0 2006.202.01:26:02.59#ibcon#read 5, iclass 25, count 0 2006.202.01:26:02.59#ibcon#about to read 6, iclass 25, count 0 2006.202.01:26:02.59#ibcon#read 6, iclass 25, count 0 2006.202.01:26:02.59#ibcon#end of sib2, iclass 25, count 0 2006.202.01:26:02.59#ibcon#*after write, iclass 25, count 0 2006.202.01:26:02.59#ibcon#*before return 0, iclass 25, count 0 2006.202.01:26:02.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.202.01:26:02.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.202.01:26:02.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.01:26:02.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.01:26:02.59$vck44/vblo=5,709.99 2006.202.01:26:02.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.202.01:26:02.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.202.01:26:02.59#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:02.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:26:02.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:26:02.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:26:02.59#ibcon#enter wrdev, iclass 27, count 0 2006.202.01:26:02.59#ibcon#first serial, iclass 27, count 0 2006.202.01:26:02.59#ibcon#enter sib2, iclass 27, count 0 2006.202.01:26:02.59#ibcon#flushed, iclass 27, count 0 2006.202.01:26:02.59#ibcon#about to write, iclass 27, count 0 2006.202.01:26:02.59#ibcon#wrote, iclass 27, count 0 2006.202.01:26:02.59#ibcon#about to read 3, iclass 27, count 0 2006.202.01:26:02.61#ibcon#read 3, iclass 27, count 0 2006.202.01:26:02.61#ibcon#about to read 4, iclass 27, count 0 2006.202.01:26:02.61#ibcon#read 4, iclass 27, count 0 2006.202.01:26:02.61#ibcon#about to read 5, iclass 27, count 0 2006.202.01:26:02.61#ibcon#read 5, iclass 27, count 0 2006.202.01:26:02.61#ibcon#about to read 6, iclass 27, count 0 2006.202.01:26:02.61#ibcon#read 6, iclass 27, count 0 2006.202.01:26:02.61#ibcon#end of sib2, iclass 27, count 0 2006.202.01:26:02.61#ibcon#*mode == 0, iclass 27, count 0 2006.202.01:26:02.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.01:26:02.61#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.01:26:02.61#ibcon#*before write, iclass 27, count 0 2006.202.01:26:02.61#ibcon#enter sib2, iclass 27, count 0 2006.202.01:26:02.61#ibcon#flushed, iclass 27, count 0 2006.202.01:26:02.61#ibcon#about to write, iclass 27, count 0 2006.202.01:26:02.61#ibcon#wrote, iclass 27, count 0 2006.202.01:26:02.61#ibcon#about to read 3, iclass 27, count 0 2006.202.01:26:02.65#ibcon#read 3, iclass 27, count 0 2006.202.01:26:02.65#ibcon#about to read 4, iclass 27, count 0 2006.202.01:26:02.65#ibcon#read 4, iclass 27, count 0 2006.202.01:26:02.65#ibcon#about to read 5, iclass 27, count 0 2006.202.01:26:02.65#ibcon#read 5, iclass 27, count 0 2006.202.01:26:02.65#ibcon#about to read 6, iclass 27, count 0 2006.202.01:26:02.65#ibcon#read 6, iclass 27, count 0 2006.202.01:26:02.65#ibcon#end of sib2, iclass 27, count 0 2006.202.01:26:02.65#ibcon#*after write, iclass 27, count 0 2006.202.01:26:02.65#ibcon#*before return 0, iclass 27, count 0 2006.202.01:26:02.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:26:02.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.202.01:26:02.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.01:26:02.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.01:26:02.65$vck44/vb=5,4 2006.202.01:26:02.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.01:26:02.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.01:26:02.65#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:02.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:26:02.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:26:02.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:26:02.71#ibcon#enter wrdev, iclass 29, count 2 2006.202.01:26:02.71#ibcon#first serial, iclass 29, count 2 2006.202.01:26:02.71#ibcon#enter sib2, iclass 29, count 2 2006.202.01:26:02.71#ibcon#flushed, iclass 29, count 2 2006.202.01:26:02.71#ibcon#about to write, iclass 29, count 2 2006.202.01:26:02.71#ibcon#wrote, iclass 29, count 2 2006.202.01:26:02.71#ibcon#about to read 3, iclass 29, count 2 2006.202.01:26:02.73#ibcon#read 3, iclass 29, count 2 2006.202.01:26:02.73#ibcon#about to read 4, iclass 29, count 2 2006.202.01:26:02.73#ibcon#read 4, iclass 29, count 2 2006.202.01:26:02.73#ibcon#about to read 5, iclass 29, count 2 2006.202.01:26:02.73#ibcon#read 5, iclass 29, count 2 2006.202.01:26:02.73#ibcon#about to read 6, iclass 29, count 2 2006.202.01:26:02.73#ibcon#read 6, iclass 29, count 2 2006.202.01:26:02.73#ibcon#end of sib2, iclass 29, count 2 2006.202.01:26:02.73#ibcon#*mode == 0, iclass 29, count 2 2006.202.01:26:02.73#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.01:26:02.73#ibcon#[27=AT05-04\r\n] 2006.202.01:26:02.73#ibcon#*before write, iclass 29, count 2 2006.202.01:26:02.73#ibcon#enter sib2, iclass 29, count 2 2006.202.01:26:02.73#ibcon#flushed, iclass 29, count 2 2006.202.01:26:02.73#ibcon#about to write, iclass 29, count 2 2006.202.01:26:02.73#ibcon#wrote, iclass 29, count 2 2006.202.01:26:02.73#ibcon#about to read 3, iclass 29, count 2 2006.202.01:26:02.76#ibcon#read 3, iclass 29, count 2 2006.202.01:26:02.76#ibcon#about to read 4, iclass 29, count 2 2006.202.01:26:02.76#ibcon#read 4, iclass 29, count 2 2006.202.01:26:02.76#ibcon#about to read 5, iclass 29, count 2 2006.202.01:26:02.76#ibcon#read 5, iclass 29, count 2 2006.202.01:26:02.76#ibcon#about to read 6, iclass 29, count 2 2006.202.01:26:02.76#ibcon#read 6, iclass 29, count 2 2006.202.01:26:02.76#ibcon#end of sib2, iclass 29, count 2 2006.202.01:26:02.76#ibcon#*after write, iclass 29, count 2 2006.202.01:26:02.76#ibcon#*before return 0, iclass 29, count 2 2006.202.01:26:02.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:26:02.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:26:02.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.01:26:02.76#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:02.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:26:02.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:26:02.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:26:02.88#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:26:02.88#ibcon#first serial, iclass 29, count 0 2006.202.01:26:02.88#ibcon#enter sib2, iclass 29, count 0 2006.202.01:26:02.88#ibcon#flushed, iclass 29, count 0 2006.202.01:26:02.88#ibcon#about to write, iclass 29, count 0 2006.202.01:26:02.88#ibcon#wrote, iclass 29, count 0 2006.202.01:26:02.88#ibcon#about to read 3, iclass 29, count 0 2006.202.01:26:02.90#ibcon#read 3, iclass 29, count 0 2006.202.01:26:02.90#ibcon#about to read 4, iclass 29, count 0 2006.202.01:26:02.90#ibcon#read 4, iclass 29, count 0 2006.202.01:26:02.90#ibcon#about to read 5, iclass 29, count 0 2006.202.01:26:02.90#ibcon#read 5, iclass 29, count 0 2006.202.01:26:02.90#ibcon#about to read 6, iclass 29, count 0 2006.202.01:26:02.90#ibcon#read 6, iclass 29, count 0 2006.202.01:26:02.90#ibcon#end of sib2, iclass 29, count 0 2006.202.01:26:02.90#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:26:02.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:26:02.90#ibcon#[27=USB\r\n] 2006.202.01:26:02.90#ibcon#*before write, iclass 29, count 0 2006.202.01:26:02.90#ibcon#enter sib2, iclass 29, count 0 2006.202.01:26:02.90#ibcon#flushed, iclass 29, count 0 2006.202.01:26:02.90#ibcon#about to write, iclass 29, count 0 2006.202.01:26:02.90#ibcon#wrote, iclass 29, count 0 2006.202.01:26:02.90#ibcon#about to read 3, iclass 29, count 0 2006.202.01:26:02.93#ibcon#read 3, iclass 29, count 0 2006.202.01:26:02.93#ibcon#about to read 4, iclass 29, count 0 2006.202.01:26:02.93#ibcon#read 4, iclass 29, count 0 2006.202.01:26:02.93#ibcon#about to read 5, iclass 29, count 0 2006.202.01:26:02.93#ibcon#read 5, iclass 29, count 0 2006.202.01:26:02.93#ibcon#about to read 6, iclass 29, count 0 2006.202.01:26:02.93#ibcon#read 6, iclass 29, count 0 2006.202.01:26:02.93#ibcon#end of sib2, iclass 29, count 0 2006.202.01:26:02.93#ibcon#*after write, iclass 29, count 0 2006.202.01:26:02.93#ibcon#*before return 0, iclass 29, count 0 2006.202.01:26:02.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:26:02.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:26:02.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:26:02.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:26:02.93$vck44/vblo=6,719.99 2006.202.01:26:02.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.202.01:26:02.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.202.01:26:02.93#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:02.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:26:02.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:26:02.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:26:02.93#ibcon#enter wrdev, iclass 31, count 0 2006.202.01:26:02.93#ibcon#first serial, iclass 31, count 0 2006.202.01:26:02.93#ibcon#enter sib2, iclass 31, count 0 2006.202.01:26:02.93#ibcon#flushed, iclass 31, count 0 2006.202.01:26:02.93#ibcon#about to write, iclass 31, count 0 2006.202.01:26:02.93#ibcon#wrote, iclass 31, count 0 2006.202.01:26:02.93#ibcon#about to read 3, iclass 31, count 0 2006.202.01:26:02.95#ibcon#read 3, iclass 31, count 0 2006.202.01:26:02.95#ibcon#about to read 4, iclass 31, count 0 2006.202.01:26:02.95#ibcon#read 4, iclass 31, count 0 2006.202.01:26:02.95#ibcon#about to read 5, iclass 31, count 0 2006.202.01:26:02.95#ibcon#read 5, iclass 31, count 0 2006.202.01:26:02.95#ibcon#about to read 6, iclass 31, count 0 2006.202.01:26:02.95#ibcon#read 6, iclass 31, count 0 2006.202.01:26:02.95#ibcon#end of sib2, iclass 31, count 0 2006.202.01:26:02.95#ibcon#*mode == 0, iclass 31, count 0 2006.202.01:26:02.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.01:26:02.95#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.01:26:02.95#ibcon#*before write, iclass 31, count 0 2006.202.01:26:02.95#ibcon#enter sib2, iclass 31, count 0 2006.202.01:26:02.95#ibcon#flushed, iclass 31, count 0 2006.202.01:26:02.95#ibcon#about to write, iclass 31, count 0 2006.202.01:26:02.95#ibcon#wrote, iclass 31, count 0 2006.202.01:26:02.95#ibcon#about to read 3, iclass 31, count 0 2006.202.01:26:02.99#ibcon#read 3, iclass 31, count 0 2006.202.01:26:02.99#ibcon#about to read 4, iclass 31, count 0 2006.202.01:26:02.99#ibcon#read 4, iclass 31, count 0 2006.202.01:26:02.99#ibcon#about to read 5, iclass 31, count 0 2006.202.01:26:02.99#ibcon#read 5, iclass 31, count 0 2006.202.01:26:02.99#ibcon#about to read 6, iclass 31, count 0 2006.202.01:26:02.99#ibcon#read 6, iclass 31, count 0 2006.202.01:26:02.99#ibcon#end of sib2, iclass 31, count 0 2006.202.01:26:02.99#ibcon#*after write, iclass 31, count 0 2006.202.01:26:02.99#ibcon#*before return 0, iclass 31, count 0 2006.202.01:26:02.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:26:02.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.202.01:26:02.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.01:26:02.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.01:26:02.99$vck44/vb=6,4 2006.202.01:26:02.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.202.01:26:02.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.202.01:26:02.99#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:02.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:26:03.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:26:03.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:26:03.05#ibcon#enter wrdev, iclass 33, count 2 2006.202.01:26:03.05#ibcon#first serial, iclass 33, count 2 2006.202.01:26:03.05#ibcon#enter sib2, iclass 33, count 2 2006.202.01:26:03.05#ibcon#flushed, iclass 33, count 2 2006.202.01:26:03.05#ibcon#about to write, iclass 33, count 2 2006.202.01:26:03.05#ibcon#wrote, iclass 33, count 2 2006.202.01:26:03.05#ibcon#about to read 3, iclass 33, count 2 2006.202.01:26:03.07#ibcon#read 3, iclass 33, count 2 2006.202.01:26:03.07#ibcon#about to read 4, iclass 33, count 2 2006.202.01:26:03.07#ibcon#read 4, iclass 33, count 2 2006.202.01:26:03.07#ibcon#about to read 5, iclass 33, count 2 2006.202.01:26:03.07#ibcon#read 5, iclass 33, count 2 2006.202.01:26:03.07#ibcon#about to read 6, iclass 33, count 2 2006.202.01:26:03.07#ibcon#read 6, iclass 33, count 2 2006.202.01:26:03.07#ibcon#end of sib2, iclass 33, count 2 2006.202.01:26:03.07#ibcon#*mode == 0, iclass 33, count 2 2006.202.01:26:03.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.202.01:26:03.07#ibcon#[27=AT06-04\r\n] 2006.202.01:26:03.07#ibcon#*before write, iclass 33, count 2 2006.202.01:26:03.07#ibcon#enter sib2, iclass 33, count 2 2006.202.01:26:03.07#ibcon#flushed, iclass 33, count 2 2006.202.01:26:03.07#ibcon#about to write, iclass 33, count 2 2006.202.01:26:03.07#ibcon#wrote, iclass 33, count 2 2006.202.01:26:03.07#ibcon#about to read 3, iclass 33, count 2 2006.202.01:26:03.10#ibcon#read 3, iclass 33, count 2 2006.202.01:26:03.10#ibcon#about to read 4, iclass 33, count 2 2006.202.01:26:03.10#ibcon#read 4, iclass 33, count 2 2006.202.01:26:03.10#ibcon#about to read 5, iclass 33, count 2 2006.202.01:26:03.10#ibcon#read 5, iclass 33, count 2 2006.202.01:26:03.10#ibcon#about to read 6, iclass 33, count 2 2006.202.01:26:03.10#ibcon#read 6, iclass 33, count 2 2006.202.01:26:03.10#ibcon#end of sib2, iclass 33, count 2 2006.202.01:26:03.10#ibcon#*after write, iclass 33, count 2 2006.202.01:26:03.10#ibcon#*before return 0, iclass 33, count 2 2006.202.01:26:03.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:26:03.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.202.01:26:03.10#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.202.01:26:03.10#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:03.10#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:26:03.22#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:26:03.22#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:26:03.22#ibcon#enter wrdev, iclass 33, count 0 2006.202.01:26:03.22#ibcon#first serial, iclass 33, count 0 2006.202.01:26:03.22#ibcon#enter sib2, iclass 33, count 0 2006.202.01:26:03.22#ibcon#flushed, iclass 33, count 0 2006.202.01:26:03.22#ibcon#about to write, iclass 33, count 0 2006.202.01:26:03.22#ibcon#wrote, iclass 33, count 0 2006.202.01:26:03.22#ibcon#about to read 3, iclass 33, count 0 2006.202.01:26:03.24#ibcon#read 3, iclass 33, count 0 2006.202.01:26:03.24#ibcon#about to read 4, iclass 33, count 0 2006.202.01:26:03.24#ibcon#read 4, iclass 33, count 0 2006.202.01:26:03.24#ibcon#about to read 5, iclass 33, count 0 2006.202.01:26:03.24#ibcon#read 5, iclass 33, count 0 2006.202.01:26:03.24#ibcon#about to read 6, iclass 33, count 0 2006.202.01:26:03.24#ibcon#read 6, iclass 33, count 0 2006.202.01:26:03.24#ibcon#end of sib2, iclass 33, count 0 2006.202.01:26:03.24#ibcon#*mode == 0, iclass 33, count 0 2006.202.01:26:03.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.01:26:03.24#ibcon#[27=USB\r\n] 2006.202.01:26:03.24#ibcon#*before write, iclass 33, count 0 2006.202.01:26:03.24#ibcon#enter sib2, iclass 33, count 0 2006.202.01:26:03.24#ibcon#flushed, iclass 33, count 0 2006.202.01:26:03.24#ibcon#about to write, iclass 33, count 0 2006.202.01:26:03.24#ibcon#wrote, iclass 33, count 0 2006.202.01:26:03.24#ibcon#about to read 3, iclass 33, count 0 2006.202.01:26:03.27#ibcon#read 3, iclass 33, count 0 2006.202.01:26:03.27#ibcon#about to read 4, iclass 33, count 0 2006.202.01:26:03.27#ibcon#read 4, iclass 33, count 0 2006.202.01:26:03.27#ibcon#about to read 5, iclass 33, count 0 2006.202.01:26:03.27#ibcon#read 5, iclass 33, count 0 2006.202.01:26:03.27#ibcon#about to read 6, iclass 33, count 0 2006.202.01:26:03.27#ibcon#read 6, iclass 33, count 0 2006.202.01:26:03.27#ibcon#end of sib2, iclass 33, count 0 2006.202.01:26:03.27#ibcon#*after write, iclass 33, count 0 2006.202.01:26:03.27#ibcon#*before return 0, iclass 33, count 0 2006.202.01:26:03.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:26:03.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.202.01:26:03.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.01:26:03.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.01:26:03.27$vck44/vblo=7,734.99 2006.202.01:26:03.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.202.01:26:03.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.202.01:26:03.27#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:03.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:03.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:03.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:03.27#ibcon#enter wrdev, iclass 35, count 0 2006.202.01:26:03.27#ibcon#first serial, iclass 35, count 0 2006.202.01:26:03.27#ibcon#enter sib2, iclass 35, count 0 2006.202.01:26:03.27#ibcon#flushed, iclass 35, count 0 2006.202.01:26:03.27#ibcon#about to write, iclass 35, count 0 2006.202.01:26:03.27#ibcon#wrote, iclass 35, count 0 2006.202.01:26:03.27#ibcon#about to read 3, iclass 35, count 0 2006.202.01:26:03.29#ibcon#read 3, iclass 35, count 0 2006.202.01:26:03.29#ibcon#about to read 4, iclass 35, count 0 2006.202.01:26:03.29#ibcon#read 4, iclass 35, count 0 2006.202.01:26:03.29#ibcon#about to read 5, iclass 35, count 0 2006.202.01:26:03.29#ibcon#read 5, iclass 35, count 0 2006.202.01:26:03.29#ibcon#about to read 6, iclass 35, count 0 2006.202.01:26:03.29#ibcon#read 6, iclass 35, count 0 2006.202.01:26:03.29#ibcon#end of sib2, iclass 35, count 0 2006.202.01:26:03.29#ibcon#*mode == 0, iclass 35, count 0 2006.202.01:26:03.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.01:26:03.29#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.01:26:03.29#ibcon#*before write, iclass 35, count 0 2006.202.01:26:03.29#ibcon#enter sib2, iclass 35, count 0 2006.202.01:26:03.29#ibcon#flushed, iclass 35, count 0 2006.202.01:26:03.29#ibcon#about to write, iclass 35, count 0 2006.202.01:26:03.29#ibcon#wrote, iclass 35, count 0 2006.202.01:26:03.29#ibcon#about to read 3, iclass 35, count 0 2006.202.01:26:03.33#ibcon#read 3, iclass 35, count 0 2006.202.01:26:03.33#ibcon#about to read 4, iclass 35, count 0 2006.202.01:26:03.33#ibcon#read 4, iclass 35, count 0 2006.202.01:26:03.33#ibcon#about to read 5, iclass 35, count 0 2006.202.01:26:03.33#ibcon#read 5, iclass 35, count 0 2006.202.01:26:03.33#ibcon#about to read 6, iclass 35, count 0 2006.202.01:26:03.33#ibcon#read 6, iclass 35, count 0 2006.202.01:26:03.33#ibcon#end of sib2, iclass 35, count 0 2006.202.01:26:03.33#ibcon#*after write, iclass 35, count 0 2006.202.01:26:03.33#ibcon#*before return 0, iclass 35, count 0 2006.202.01:26:03.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:03.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.202.01:26:03.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.01:26:03.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.01:26:03.33$vck44/vb=7,4 2006.202.01:26:03.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.202.01:26:03.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.202.01:26:03.33#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:03.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:03.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:03.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:03.39#ibcon#enter wrdev, iclass 37, count 2 2006.202.01:26:03.39#ibcon#first serial, iclass 37, count 2 2006.202.01:26:03.39#ibcon#enter sib2, iclass 37, count 2 2006.202.01:26:03.39#ibcon#flushed, iclass 37, count 2 2006.202.01:26:03.39#ibcon#about to write, iclass 37, count 2 2006.202.01:26:03.39#ibcon#wrote, iclass 37, count 2 2006.202.01:26:03.39#ibcon#about to read 3, iclass 37, count 2 2006.202.01:26:03.41#ibcon#read 3, iclass 37, count 2 2006.202.01:26:03.41#ibcon#about to read 4, iclass 37, count 2 2006.202.01:26:03.41#ibcon#read 4, iclass 37, count 2 2006.202.01:26:03.41#ibcon#about to read 5, iclass 37, count 2 2006.202.01:26:03.41#ibcon#read 5, iclass 37, count 2 2006.202.01:26:03.41#ibcon#about to read 6, iclass 37, count 2 2006.202.01:26:03.41#ibcon#read 6, iclass 37, count 2 2006.202.01:26:03.41#ibcon#end of sib2, iclass 37, count 2 2006.202.01:26:03.41#ibcon#*mode == 0, iclass 37, count 2 2006.202.01:26:03.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.202.01:26:03.41#ibcon#[27=AT07-04\r\n] 2006.202.01:26:03.41#ibcon#*before write, iclass 37, count 2 2006.202.01:26:03.41#ibcon#enter sib2, iclass 37, count 2 2006.202.01:26:03.41#ibcon#flushed, iclass 37, count 2 2006.202.01:26:03.41#ibcon#about to write, iclass 37, count 2 2006.202.01:26:03.41#ibcon#wrote, iclass 37, count 2 2006.202.01:26:03.41#ibcon#about to read 3, iclass 37, count 2 2006.202.01:26:03.44#ibcon#read 3, iclass 37, count 2 2006.202.01:26:03.44#ibcon#about to read 4, iclass 37, count 2 2006.202.01:26:03.44#ibcon#read 4, iclass 37, count 2 2006.202.01:26:03.44#ibcon#about to read 5, iclass 37, count 2 2006.202.01:26:03.44#ibcon#read 5, iclass 37, count 2 2006.202.01:26:03.44#ibcon#about to read 6, iclass 37, count 2 2006.202.01:26:03.44#ibcon#read 6, iclass 37, count 2 2006.202.01:26:03.44#ibcon#end of sib2, iclass 37, count 2 2006.202.01:26:03.44#ibcon#*after write, iclass 37, count 2 2006.202.01:26:03.44#ibcon#*before return 0, iclass 37, count 2 2006.202.01:26:03.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:03.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.202.01:26:03.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.202.01:26:03.44#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:03.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:03.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:03.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:03.56#ibcon#enter wrdev, iclass 37, count 0 2006.202.01:26:03.56#ibcon#first serial, iclass 37, count 0 2006.202.01:26:03.56#ibcon#enter sib2, iclass 37, count 0 2006.202.01:26:03.56#ibcon#flushed, iclass 37, count 0 2006.202.01:26:03.56#ibcon#about to write, iclass 37, count 0 2006.202.01:26:03.56#ibcon#wrote, iclass 37, count 0 2006.202.01:26:03.56#ibcon#about to read 3, iclass 37, count 0 2006.202.01:26:03.58#ibcon#read 3, iclass 37, count 0 2006.202.01:26:03.58#ibcon#about to read 4, iclass 37, count 0 2006.202.01:26:03.58#ibcon#read 4, iclass 37, count 0 2006.202.01:26:03.58#ibcon#about to read 5, iclass 37, count 0 2006.202.01:26:03.58#ibcon#read 5, iclass 37, count 0 2006.202.01:26:03.58#ibcon#about to read 6, iclass 37, count 0 2006.202.01:26:03.58#ibcon#read 6, iclass 37, count 0 2006.202.01:26:03.58#ibcon#end of sib2, iclass 37, count 0 2006.202.01:26:03.58#ibcon#*mode == 0, iclass 37, count 0 2006.202.01:26:03.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.01:26:03.58#ibcon#[27=USB\r\n] 2006.202.01:26:03.58#ibcon#*before write, iclass 37, count 0 2006.202.01:26:03.58#ibcon#enter sib2, iclass 37, count 0 2006.202.01:26:03.58#ibcon#flushed, iclass 37, count 0 2006.202.01:26:03.58#ibcon#about to write, iclass 37, count 0 2006.202.01:26:03.58#ibcon#wrote, iclass 37, count 0 2006.202.01:26:03.58#ibcon#about to read 3, iclass 37, count 0 2006.202.01:26:03.61#ibcon#read 3, iclass 37, count 0 2006.202.01:26:03.61#ibcon#about to read 4, iclass 37, count 0 2006.202.01:26:03.61#ibcon#read 4, iclass 37, count 0 2006.202.01:26:03.61#ibcon#about to read 5, iclass 37, count 0 2006.202.01:26:03.61#ibcon#read 5, iclass 37, count 0 2006.202.01:26:03.61#ibcon#about to read 6, iclass 37, count 0 2006.202.01:26:03.61#ibcon#read 6, iclass 37, count 0 2006.202.01:26:03.61#ibcon#end of sib2, iclass 37, count 0 2006.202.01:26:03.61#ibcon#*after write, iclass 37, count 0 2006.202.01:26:03.61#ibcon#*before return 0, iclass 37, count 0 2006.202.01:26:03.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:03.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.202.01:26:03.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.01:26:03.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.01:26:03.61$vck44/vblo=8,744.99 2006.202.01:26:03.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.202.01:26:03.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.202.01:26:03.61#ibcon#ireg 17 cls_cnt 0 2006.202.01:26:03.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:03.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:03.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:03.61#ibcon#enter wrdev, iclass 39, count 0 2006.202.01:26:03.61#ibcon#first serial, iclass 39, count 0 2006.202.01:26:03.61#ibcon#enter sib2, iclass 39, count 0 2006.202.01:26:03.61#ibcon#flushed, iclass 39, count 0 2006.202.01:26:03.61#ibcon#about to write, iclass 39, count 0 2006.202.01:26:03.61#ibcon#wrote, iclass 39, count 0 2006.202.01:26:03.61#ibcon#about to read 3, iclass 39, count 0 2006.202.01:26:03.63#ibcon#read 3, iclass 39, count 0 2006.202.01:26:03.63#ibcon#about to read 4, iclass 39, count 0 2006.202.01:26:03.63#ibcon#read 4, iclass 39, count 0 2006.202.01:26:03.63#ibcon#about to read 5, iclass 39, count 0 2006.202.01:26:03.63#ibcon#read 5, iclass 39, count 0 2006.202.01:26:03.63#ibcon#about to read 6, iclass 39, count 0 2006.202.01:26:03.63#ibcon#read 6, iclass 39, count 0 2006.202.01:26:03.63#ibcon#end of sib2, iclass 39, count 0 2006.202.01:26:03.63#ibcon#*mode == 0, iclass 39, count 0 2006.202.01:26:03.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.01:26:03.63#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.01:26:03.63#ibcon#*before write, iclass 39, count 0 2006.202.01:26:03.63#ibcon#enter sib2, iclass 39, count 0 2006.202.01:26:03.63#ibcon#flushed, iclass 39, count 0 2006.202.01:26:03.63#ibcon#about to write, iclass 39, count 0 2006.202.01:26:03.63#ibcon#wrote, iclass 39, count 0 2006.202.01:26:03.63#ibcon#about to read 3, iclass 39, count 0 2006.202.01:26:03.67#ibcon#read 3, iclass 39, count 0 2006.202.01:26:03.67#ibcon#about to read 4, iclass 39, count 0 2006.202.01:26:03.67#ibcon#read 4, iclass 39, count 0 2006.202.01:26:03.67#ibcon#about to read 5, iclass 39, count 0 2006.202.01:26:03.67#ibcon#read 5, iclass 39, count 0 2006.202.01:26:03.67#ibcon#about to read 6, iclass 39, count 0 2006.202.01:26:03.67#ibcon#read 6, iclass 39, count 0 2006.202.01:26:03.67#ibcon#end of sib2, iclass 39, count 0 2006.202.01:26:03.67#ibcon#*after write, iclass 39, count 0 2006.202.01:26:03.67#ibcon#*before return 0, iclass 39, count 0 2006.202.01:26:03.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:03.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.202.01:26:03.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.01:26:03.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.01:26:03.67$vck44/vb=8,4 2006.202.01:26:03.67#ibcon#iclass 2 nclrec 2 cls_cnt 3 2006.202.01:26:03.67#ibcon#iclass 2 iclrec 1 cls_cnt 3 2006.202.01:26:03.67#ibcon#ireg 11 cls_cnt 2 2006.202.01:26:03.67#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:03.73#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:03.73#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:03.73#ibcon#enter wrdev, iclass 2, count 2 2006.202.01:26:03.73#ibcon#first serial, iclass 2, count 2 2006.202.01:26:03.73#ibcon#enter sib2, iclass 2, count 2 2006.202.01:26:03.73#ibcon#flushed, iclass 2, count 2 2006.202.01:26:03.73#ibcon#about to write, iclass 2, count 2 2006.202.01:26:03.73#ibcon#wrote, iclass 2, count 2 2006.202.01:26:03.73#ibcon#about to read 3, iclass 2, count 2 2006.202.01:26:03.75#ibcon#read 3, iclass 2, count 2 2006.202.01:26:03.75#ibcon#about to read 4, iclass 2, count 2 2006.202.01:26:03.75#ibcon#read 4, iclass 2, count 2 2006.202.01:26:03.75#ibcon#about to read 5, iclass 2, count 2 2006.202.01:26:03.75#ibcon#read 5, iclass 2, count 2 2006.202.01:26:03.75#ibcon#about to read 6, iclass 2, count 2 2006.202.01:26:03.75#ibcon#read 6, iclass 2, count 2 2006.202.01:26:03.75#ibcon#end of sib2, iclass 2, count 2 2006.202.01:26:03.75#ibcon#*mode == 0, iclass 2, count 2 2006.202.01:26:03.75#ibcon#*mode == 0 && serial, iclass 2, count 2 2006.202.01:26:03.75#ibcon#[27=AT08-04\r\n] 2006.202.01:26:03.75#ibcon#*before write, iclass 2, count 2 2006.202.01:26:03.75#ibcon#enter sib2, iclass 2, count 2 2006.202.01:26:03.75#ibcon#flushed, iclass 2, count 2 2006.202.01:26:03.75#ibcon#about to write, iclass 2, count 2 2006.202.01:26:03.75#ibcon#wrote, iclass 2, count 2 2006.202.01:26:03.75#ibcon#about to read 3, iclass 2, count 2 2006.202.01:26:03.78#ibcon#read 3, iclass 2, count 2 2006.202.01:26:03.78#ibcon#about to read 4, iclass 2, count 2 2006.202.01:26:03.78#ibcon#read 4, iclass 2, count 2 2006.202.01:26:03.78#ibcon#about to read 5, iclass 2, count 2 2006.202.01:26:03.78#ibcon#read 5, iclass 2, count 2 2006.202.01:26:03.78#ibcon#about to read 6, iclass 2, count 2 2006.202.01:26:03.78#ibcon#read 6, iclass 2, count 2 2006.202.01:26:03.78#ibcon#end of sib2, iclass 2, count 2 2006.202.01:26:03.78#ibcon#*after write, iclass 2, count 2 2006.202.01:26:03.78#ibcon#*before return 0, iclass 2, count 2 2006.202.01:26:03.78#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:03.78#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 2 2006.202.01:26:03.78#ibcon#iclass 2 iclrec 2 cls_cnt 2 2006.202.01:26:03.78#ibcon#ireg 7 cls_cnt 0 2006.202.01:26:03.78#ibcon#before find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:03.90#ibcon#after find_delay mode 2, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:03.90#ibcon#before mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:03.90#ibcon#enter wrdev, iclass 2, count 0 2006.202.01:26:03.90#ibcon#first serial, iclass 2, count 0 2006.202.01:26:03.90#ibcon#enter sib2, iclass 2, count 0 2006.202.01:26:03.90#ibcon#flushed, iclass 2, count 0 2006.202.01:26:03.90#ibcon#about to write, iclass 2, count 0 2006.202.01:26:03.90#ibcon#wrote, iclass 2, count 0 2006.202.01:26:03.90#ibcon#about to read 3, iclass 2, count 0 2006.202.01:26:03.92#ibcon#read 3, iclass 2, count 0 2006.202.01:26:03.92#ibcon#about to read 4, iclass 2, count 0 2006.202.01:26:03.92#ibcon#read 4, iclass 2, count 0 2006.202.01:26:03.92#ibcon#about to read 5, iclass 2, count 0 2006.202.01:26:03.92#ibcon#read 5, iclass 2, count 0 2006.202.01:26:03.92#ibcon#about to read 6, iclass 2, count 0 2006.202.01:26:03.92#ibcon#read 6, iclass 2, count 0 2006.202.01:26:03.92#ibcon#end of sib2, iclass 2, count 0 2006.202.01:26:03.92#ibcon#*mode == 0, iclass 2, count 0 2006.202.01:26:03.92#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.01:26:03.92#ibcon#[27=USB\r\n] 2006.202.01:26:03.92#ibcon#*before write, iclass 2, count 0 2006.202.01:26:03.92#ibcon#enter sib2, iclass 2, count 0 2006.202.01:26:03.92#ibcon#flushed, iclass 2, count 0 2006.202.01:26:03.92#ibcon#about to write, iclass 2, count 0 2006.202.01:26:03.92#ibcon#wrote, iclass 2, count 0 2006.202.01:26:03.92#ibcon#about to read 3, iclass 2, count 0 2006.202.01:26:03.95#ibcon#read 3, iclass 2, count 0 2006.202.01:26:03.95#ibcon#about to read 4, iclass 2, count 0 2006.202.01:26:03.95#ibcon#read 4, iclass 2, count 0 2006.202.01:26:03.95#ibcon#about to read 5, iclass 2, count 0 2006.202.01:26:03.95#ibcon#read 5, iclass 2, count 0 2006.202.01:26:03.95#ibcon#about to read 6, iclass 2, count 0 2006.202.01:26:03.95#ibcon#read 6, iclass 2, count 0 2006.202.01:26:03.95#ibcon#end of sib2, iclass 2, count 0 2006.202.01:26:03.95#ibcon#*after write, iclass 2, count 0 2006.202.01:26:03.95#ibcon#*before return 0, iclass 2, count 0 2006.202.01:26:03.95#ibcon#after mode 2 write, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:03.95#ibcon#end of loop, iclass 2 iclrec 2 cls_cnt 0 2006.202.01:26:03.95#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.01:26:03.95#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.01:26:03.95$vck44/vabw=wide 2006.202.01:26:03.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.202.01:26:03.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.202.01:26:03.95#ibcon#ireg 8 cls_cnt 0 2006.202.01:26:03.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:03.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:03.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:03.95#ibcon#enter wrdev, iclass 5, count 0 2006.202.01:26:03.95#ibcon#first serial, iclass 5, count 0 2006.202.01:26:03.95#ibcon#enter sib2, iclass 5, count 0 2006.202.01:26:03.95#ibcon#flushed, iclass 5, count 0 2006.202.01:26:03.95#ibcon#about to write, iclass 5, count 0 2006.202.01:26:03.95#ibcon#wrote, iclass 5, count 0 2006.202.01:26:03.95#ibcon#about to read 3, iclass 5, count 0 2006.202.01:26:03.97#ibcon#read 3, iclass 5, count 0 2006.202.01:26:03.97#ibcon#about to read 4, iclass 5, count 0 2006.202.01:26:03.97#ibcon#read 4, iclass 5, count 0 2006.202.01:26:03.97#ibcon#about to read 5, iclass 5, count 0 2006.202.01:26:03.97#ibcon#read 5, iclass 5, count 0 2006.202.01:26:03.97#ibcon#about to read 6, iclass 5, count 0 2006.202.01:26:03.97#ibcon#read 6, iclass 5, count 0 2006.202.01:26:03.97#ibcon#end of sib2, iclass 5, count 0 2006.202.01:26:03.97#ibcon#*mode == 0, iclass 5, count 0 2006.202.01:26:03.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.01:26:03.97#ibcon#[25=BW32\r\n] 2006.202.01:26:03.97#ibcon#*before write, iclass 5, count 0 2006.202.01:26:03.97#ibcon#enter sib2, iclass 5, count 0 2006.202.01:26:03.97#ibcon#flushed, iclass 5, count 0 2006.202.01:26:03.97#ibcon#about to write, iclass 5, count 0 2006.202.01:26:03.97#ibcon#wrote, iclass 5, count 0 2006.202.01:26:03.97#ibcon#about to read 3, iclass 5, count 0 2006.202.01:26:04.00#ibcon#read 3, iclass 5, count 0 2006.202.01:26:04.00#ibcon#about to read 4, iclass 5, count 0 2006.202.01:26:04.00#ibcon#read 4, iclass 5, count 0 2006.202.01:26:04.00#ibcon#about to read 5, iclass 5, count 0 2006.202.01:26:04.00#ibcon#read 5, iclass 5, count 0 2006.202.01:26:04.00#ibcon#about to read 6, iclass 5, count 0 2006.202.01:26:04.00#ibcon#read 6, iclass 5, count 0 2006.202.01:26:04.00#ibcon#end of sib2, iclass 5, count 0 2006.202.01:26:04.00#ibcon#*after write, iclass 5, count 0 2006.202.01:26:04.00#ibcon#*before return 0, iclass 5, count 0 2006.202.01:26:04.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:04.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.202.01:26:04.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.01:26:04.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.01:26:04.00$vck44/vbbw=wide 2006.202.01:26:04.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.01:26:04.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.01:26:04.00#ibcon#ireg 8 cls_cnt 0 2006.202.01:26:04.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:26:04.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:26:04.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:26:04.07#ibcon#enter wrdev, iclass 7, count 0 2006.202.01:26:04.07#ibcon#first serial, iclass 7, count 0 2006.202.01:26:04.07#ibcon#enter sib2, iclass 7, count 0 2006.202.01:26:04.07#ibcon#flushed, iclass 7, count 0 2006.202.01:26:04.07#ibcon#about to write, iclass 7, count 0 2006.202.01:26:04.07#ibcon#wrote, iclass 7, count 0 2006.202.01:26:04.07#ibcon#about to read 3, iclass 7, count 0 2006.202.01:26:04.09#ibcon#read 3, iclass 7, count 0 2006.202.01:26:04.09#ibcon#about to read 4, iclass 7, count 0 2006.202.01:26:04.09#ibcon#read 4, iclass 7, count 0 2006.202.01:26:04.09#ibcon#about to read 5, iclass 7, count 0 2006.202.01:26:04.09#ibcon#read 5, iclass 7, count 0 2006.202.01:26:04.09#ibcon#about to read 6, iclass 7, count 0 2006.202.01:26:04.09#ibcon#read 6, iclass 7, count 0 2006.202.01:26:04.09#ibcon#end of sib2, iclass 7, count 0 2006.202.01:26:04.09#ibcon#*mode == 0, iclass 7, count 0 2006.202.01:26:04.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.01:26:04.09#ibcon#[27=BW32\r\n] 2006.202.01:26:04.09#ibcon#*before write, iclass 7, count 0 2006.202.01:26:04.09#ibcon#enter sib2, iclass 7, count 0 2006.202.01:26:04.09#ibcon#flushed, iclass 7, count 0 2006.202.01:26:04.09#ibcon#about to write, iclass 7, count 0 2006.202.01:26:04.09#ibcon#wrote, iclass 7, count 0 2006.202.01:26:04.09#ibcon#about to read 3, iclass 7, count 0 2006.202.01:26:04.12#ibcon#read 3, iclass 7, count 0 2006.202.01:26:04.12#ibcon#about to read 4, iclass 7, count 0 2006.202.01:26:04.12#ibcon#read 4, iclass 7, count 0 2006.202.01:26:04.12#ibcon#about to read 5, iclass 7, count 0 2006.202.01:26:04.12#ibcon#read 5, iclass 7, count 0 2006.202.01:26:04.12#ibcon#about to read 6, iclass 7, count 0 2006.202.01:26:04.12#ibcon#read 6, iclass 7, count 0 2006.202.01:26:04.12#ibcon#end of sib2, iclass 7, count 0 2006.202.01:26:04.12#ibcon#*after write, iclass 7, count 0 2006.202.01:26:04.12#ibcon#*before return 0, iclass 7, count 0 2006.202.01:26:04.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:26:04.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:26:04.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.01:26:04.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.01:26:04.12$setupk4/ifdk4 2006.202.01:26:04.12$ifdk4/lo= 2006.202.01:26:04.12$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.01:26:04.12$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.01:26:04.12$ifdk4/patch= 2006.202.01:26:04.12$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.01:26:04.12$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.01:26:04.12$setupk4/!*+20s 2006.202.01:26:09.20#abcon#<5=/04 2.1 5.3 20.551001000.7\r\n> 2006.202.01:26:09.22#abcon#{5=INTERFACE CLEAR} 2006.202.01:26:09.28#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:26:18.25$setupk4/"tpicd 2006.202.01:26:18.25$setupk4/echo=off 2006.202.01:26:18.25$setupk4/xlog=off 2006.202.01:26:18.25:!2006.202.01:27:45 2006.202.01:26:19.14#trakl#Source acquired 2006.202.01:26:21.14#flagr#flagr/antenna,acquired 2006.202.01:27:45.00:preob 2006.202.01:27:46.14/onsource/TRACKING 2006.202.01:27:46.14:!2006.202.01:27:55 2006.202.01:27:55.00:"tape 2006.202.01:27:55.00:"st=record 2006.202.01:27:55.00:data_valid=on 2006.202.01:27:55.00:midob 2006.202.01:27:55.14/onsource/TRACKING 2006.202.01:27:55.14/wx/20.54,1000.7,100 2006.202.01:27:55.26/cable/+6.4857E-03 2006.202.01:27:56.35/va/01,08,usb,yes,37,40 2006.202.01:27:56.35/va/02,07,usb,yes,40,41 2006.202.01:27:56.35/va/03,08,usb,yes,36,38 2006.202.01:27:56.35/va/04,07,usb,yes,41,43 2006.202.01:27:56.35/va/05,04,usb,yes,37,37 2006.202.01:27:56.35/va/06,05,usb,yes,37,37 2006.202.01:27:56.35/va/07,05,usb,yes,36,37 2006.202.01:27:56.35/va/08,04,usb,yes,36,42 2006.202.01:27:56.58/valo/01,524.99,yes,locked 2006.202.01:27:56.58/valo/02,534.99,yes,locked 2006.202.01:27:56.58/valo/03,564.99,yes,locked 2006.202.01:27:56.58/valo/04,624.99,yes,locked 2006.202.01:27:56.58/valo/05,734.99,yes,locked 2006.202.01:27:56.58/valo/06,814.99,yes,locked 2006.202.01:27:56.58/valo/07,864.99,yes,locked 2006.202.01:27:56.58/valo/08,884.99,yes,locked 2006.202.01:27:57.67/vb/01,04,usb,yes,29,27 2006.202.01:27:57.67/vb/02,05,usb,yes,27,27 2006.202.01:27:57.67/vb/03,04,usb,yes,28,31 2006.202.01:27:57.67/vb/04,05,usb,yes,29,27 2006.202.01:27:57.67/vb/05,04,usb,yes,25,27 2006.202.01:27:57.67/vb/06,04,usb,yes,29,26 2006.202.01:27:57.67/vb/07,04,usb,yes,29,29 2006.202.01:27:57.67/vb/08,04,usb,yes,27,30 2006.202.01:27:57.91/vblo/01,629.99,yes,locked 2006.202.01:27:57.91/vblo/02,634.99,yes,locked 2006.202.01:27:57.91/vblo/03,649.99,yes,locked 2006.202.01:27:57.91/vblo/04,679.99,yes,locked 2006.202.01:27:57.91/vblo/05,709.99,yes,locked 2006.202.01:27:57.91/vblo/06,719.99,yes,locked 2006.202.01:27:57.91/vblo/07,734.99,yes,locked 2006.202.01:27:57.91/vblo/08,744.99,yes,locked 2006.202.01:27:58.06/vabw/8 2006.202.01:27:58.21/vbbw/8 2006.202.01:27:58.30/xfe/off,on,16.0 2006.202.01:27:58.68/ifatt/23,28,28,28 2006.202.01:27:59.08/fmout-gps/S +4.51E-07 2006.202.01:27:59.12:!2006.202.01:40:59 2006.202.01:40:59.00:data_valid=off 2006.202.01:40:59.00:"et 2006.202.01:40:59.00:!+3s 2006.202.01:41:02.01:"tape 2006.202.01:41:02.01:postob 2006.202.01:41:02.10/cable/+6.4830E-03 2006.202.01:41:02.10/wx/20.57,1000.8,100 2006.202.01:41:03.07/fmout-gps/S +4.50E-07 2006.202.01:41:03.07:scan_name=202-0141,jd0607,90 2006.202.01:41:03.07:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.202.01:41:04.14#flagr#flagr/antenna,new-source 2006.202.01:41:04.14:checkk5 2006.202.01:41:04.55/chk_autoobs//k5ts1/ autoobs is running! 2006.202.01:41:04.96/chk_autoobs//k5ts2/ autoobs is running! 2006.202.01:41:05.37/chk_autoobs//k5ts3/ autoobs is running! 2006.202.01:41:05.78/chk_autoobs//k5ts4/ autoobs is running! 2006.202.01:41:06.48/chk_obsdata//k5ts1/T2020127??a.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.202.01:41:07.19/chk_obsdata//k5ts2/T2020127??b.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.202.01:41:07.90/chk_obsdata//k5ts3/T2020127??c.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.202.01:41:08.62/chk_obsdata//k5ts4/T2020127??d.dat file size is correct (nominal:3136MB, actual:3132MB). 2006.202.01:41:09.36/k5log//k5ts1_log_newline 2006.202.01:41:10.06/k5log//k5ts2_log_newline 2006.202.01:41:10.77/k5log//k5ts3_log_newline 2006.202.01:41:11.50/k5log//k5ts4_log_newline 2006.202.01:41:11.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.01:41:11.52:setupk4=1 2006.202.01:41:11.52$setupk4/echo=on 2006.202.01:41:11.52$setupk4/pcalon 2006.202.01:41:11.52$pcalon/"no phase cal control is implemented here 2006.202.01:41:11.52$setupk4/"tpicd=stop 2006.202.01:41:11.52$setupk4/"rec=synch_on 2006.202.01:41:11.52$setupk4/"rec_mode=128 2006.202.01:41:11.52$setupk4/!* 2006.202.01:41:11.52$setupk4/recpk4 2006.202.01:41:11.52$recpk4/recpatch= 2006.202.01:41:11.53$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.01:41:11.53$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.01:41:11.53$setupk4/vck44 2006.202.01:41:11.53$vck44/valo=1,524.99 2006.202.01:41:11.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.202.01:41:11.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.202.01:41:11.53#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:11.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:41:11.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:41:11.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:41:11.53#ibcon#enter wrdev, iclass 10, count 0 2006.202.01:41:11.53#ibcon#first serial, iclass 10, count 0 2006.202.01:41:11.53#ibcon#enter sib2, iclass 10, count 0 2006.202.01:41:11.53#ibcon#flushed, iclass 10, count 0 2006.202.01:41:11.53#ibcon#about to write, iclass 10, count 0 2006.202.01:41:11.53#ibcon#wrote, iclass 10, count 0 2006.202.01:41:11.53#ibcon#about to read 3, iclass 10, count 0 2006.202.01:41:11.55#ibcon#read 3, iclass 10, count 0 2006.202.01:41:11.55#ibcon#about to read 4, iclass 10, count 0 2006.202.01:41:11.55#ibcon#read 4, iclass 10, count 0 2006.202.01:41:11.55#ibcon#about to read 5, iclass 10, count 0 2006.202.01:41:11.55#ibcon#read 5, iclass 10, count 0 2006.202.01:41:11.55#ibcon#about to read 6, iclass 10, count 0 2006.202.01:41:11.55#ibcon#read 6, iclass 10, count 0 2006.202.01:41:11.55#ibcon#end of sib2, iclass 10, count 0 2006.202.01:41:11.55#ibcon#*mode == 0, iclass 10, count 0 2006.202.01:41:11.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.01:41:11.55#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.01:41:11.55#ibcon#*before write, iclass 10, count 0 2006.202.01:41:11.55#ibcon#enter sib2, iclass 10, count 0 2006.202.01:41:11.55#ibcon#flushed, iclass 10, count 0 2006.202.01:41:11.55#ibcon#about to write, iclass 10, count 0 2006.202.01:41:11.55#ibcon#wrote, iclass 10, count 0 2006.202.01:41:11.55#ibcon#about to read 3, iclass 10, count 0 2006.202.01:41:11.60#ibcon#read 3, iclass 10, count 0 2006.202.01:41:11.60#ibcon#about to read 4, iclass 10, count 0 2006.202.01:41:11.60#ibcon#read 4, iclass 10, count 0 2006.202.01:41:11.60#ibcon#about to read 5, iclass 10, count 0 2006.202.01:41:11.60#ibcon#read 5, iclass 10, count 0 2006.202.01:41:11.60#ibcon#about to read 6, iclass 10, count 0 2006.202.01:41:11.60#ibcon#read 6, iclass 10, count 0 2006.202.01:41:11.60#ibcon#end of sib2, iclass 10, count 0 2006.202.01:41:11.60#ibcon#*after write, iclass 10, count 0 2006.202.01:41:11.60#ibcon#*before return 0, iclass 10, count 0 2006.202.01:41:11.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:41:11.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.202.01:41:11.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.01:41:11.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.01:41:11.60$vck44/va=1,8 2006.202.01:41:11.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.202.01:41:11.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.202.01:41:11.60#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:11.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:41:11.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:41:11.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:41:11.60#ibcon#enter wrdev, iclass 12, count 2 2006.202.01:41:11.60#ibcon#first serial, iclass 12, count 2 2006.202.01:41:11.60#ibcon#enter sib2, iclass 12, count 2 2006.202.01:41:11.60#ibcon#flushed, iclass 12, count 2 2006.202.01:41:11.60#ibcon#about to write, iclass 12, count 2 2006.202.01:41:11.60#ibcon#wrote, iclass 12, count 2 2006.202.01:41:11.60#ibcon#about to read 3, iclass 12, count 2 2006.202.01:41:11.62#ibcon#read 3, iclass 12, count 2 2006.202.01:41:11.62#ibcon#about to read 4, iclass 12, count 2 2006.202.01:41:11.62#ibcon#read 4, iclass 12, count 2 2006.202.01:41:11.62#ibcon#about to read 5, iclass 12, count 2 2006.202.01:41:11.62#ibcon#read 5, iclass 12, count 2 2006.202.01:41:11.62#ibcon#about to read 6, iclass 12, count 2 2006.202.01:41:11.62#ibcon#read 6, iclass 12, count 2 2006.202.01:41:11.62#ibcon#end of sib2, iclass 12, count 2 2006.202.01:41:11.62#ibcon#*mode == 0, iclass 12, count 2 2006.202.01:41:11.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.202.01:41:11.62#ibcon#[25=AT01-08\r\n] 2006.202.01:41:11.62#ibcon#*before write, iclass 12, count 2 2006.202.01:41:11.62#ibcon#enter sib2, iclass 12, count 2 2006.202.01:41:11.62#ibcon#flushed, iclass 12, count 2 2006.202.01:41:11.62#ibcon#about to write, iclass 12, count 2 2006.202.01:41:11.62#ibcon#wrote, iclass 12, count 2 2006.202.01:41:11.62#ibcon#about to read 3, iclass 12, count 2 2006.202.01:41:11.65#ibcon#read 3, iclass 12, count 2 2006.202.01:41:11.65#ibcon#about to read 4, iclass 12, count 2 2006.202.01:41:11.65#ibcon#read 4, iclass 12, count 2 2006.202.01:41:11.65#ibcon#about to read 5, iclass 12, count 2 2006.202.01:41:11.65#ibcon#read 5, iclass 12, count 2 2006.202.01:41:11.65#ibcon#about to read 6, iclass 12, count 2 2006.202.01:41:11.65#ibcon#read 6, iclass 12, count 2 2006.202.01:41:11.65#ibcon#end of sib2, iclass 12, count 2 2006.202.01:41:11.65#ibcon#*after write, iclass 12, count 2 2006.202.01:41:11.65#ibcon#*before return 0, iclass 12, count 2 2006.202.01:41:11.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:41:11.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.202.01:41:11.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.202.01:41:11.65#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:11.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:41:11.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:41:11.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:41:11.77#ibcon#enter wrdev, iclass 12, count 0 2006.202.01:41:11.77#ibcon#first serial, iclass 12, count 0 2006.202.01:41:11.77#ibcon#enter sib2, iclass 12, count 0 2006.202.01:41:11.77#ibcon#flushed, iclass 12, count 0 2006.202.01:41:11.77#ibcon#about to write, iclass 12, count 0 2006.202.01:41:11.77#ibcon#wrote, iclass 12, count 0 2006.202.01:41:11.77#ibcon#about to read 3, iclass 12, count 0 2006.202.01:41:11.79#ibcon#read 3, iclass 12, count 0 2006.202.01:41:11.79#ibcon#about to read 4, iclass 12, count 0 2006.202.01:41:11.79#ibcon#read 4, iclass 12, count 0 2006.202.01:41:11.79#ibcon#about to read 5, iclass 12, count 0 2006.202.01:41:11.79#ibcon#read 5, iclass 12, count 0 2006.202.01:41:11.79#ibcon#about to read 6, iclass 12, count 0 2006.202.01:41:11.79#ibcon#read 6, iclass 12, count 0 2006.202.01:41:11.79#ibcon#end of sib2, iclass 12, count 0 2006.202.01:41:11.79#ibcon#*mode == 0, iclass 12, count 0 2006.202.01:41:11.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.01:41:11.79#ibcon#[25=USB\r\n] 2006.202.01:41:11.79#ibcon#*before write, iclass 12, count 0 2006.202.01:41:11.79#ibcon#enter sib2, iclass 12, count 0 2006.202.01:41:11.79#ibcon#flushed, iclass 12, count 0 2006.202.01:41:11.79#ibcon#about to write, iclass 12, count 0 2006.202.01:41:11.79#ibcon#wrote, iclass 12, count 0 2006.202.01:41:11.79#ibcon#about to read 3, iclass 12, count 0 2006.202.01:41:11.82#ibcon#read 3, iclass 12, count 0 2006.202.01:41:11.82#ibcon#about to read 4, iclass 12, count 0 2006.202.01:41:11.82#ibcon#read 4, iclass 12, count 0 2006.202.01:41:11.82#ibcon#about to read 5, iclass 12, count 0 2006.202.01:41:11.82#ibcon#read 5, iclass 12, count 0 2006.202.01:41:11.82#ibcon#about to read 6, iclass 12, count 0 2006.202.01:41:11.82#ibcon#read 6, iclass 12, count 0 2006.202.01:41:11.82#ibcon#end of sib2, iclass 12, count 0 2006.202.01:41:11.82#ibcon#*after write, iclass 12, count 0 2006.202.01:41:11.82#ibcon#*before return 0, iclass 12, count 0 2006.202.01:41:11.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:41:11.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.202.01:41:11.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.01:41:11.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.01:41:11.82$vck44/valo=2,534.99 2006.202.01:41:11.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.202.01:41:11.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.202.01:41:11.82#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:11.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:41:11.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:41:11.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:41:11.82#ibcon#enter wrdev, iclass 14, count 0 2006.202.01:41:11.82#ibcon#first serial, iclass 14, count 0 2006.202.01:41:11.82#ibcon#enter sib2, iclass 14, count 0 2006.202.01:41:11.82#ibcon#flushed, iclass 14, count 0 2006.202.01:41:11.82#ibcon#about to write, iclass 14, count 0 2006.202.01:41:11.82#ibcon#wrote, iclass 14, count 0 2006.202.01:41:11.82#ibcon#about to read 3, iclass 14, count 0 2006.202.01:41:11.84#ibcon#read 3, iclass 14, count 0 2006.202.01:41:11.84#ibcon#about to read 4, iclass 14, count 0 2006.202.01:41:11.84#ibcon#read 4, iclass 14, count 0 2006.202.01:41:11.84#ibcon#about to read 5, iclass 14, count 0 2006.202.01:41:11.84#ibcon#read 5, iclass 14, count 0 2006.202.01:41:11.84#ibcon#about to read 6, iclass 14, count 0 2006.202.01:41:11.84#ibcon#read 6, iclass 14, count 0 2006.202.01:41:11.84#ibcon#end of sib2, iclass 14, count 0 2006.202.01:41:11.84#ibcon#*mode == 0, iclass 14, count 0 2006.202.01:41:11.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.01:41:11.84#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.01:41:11.84#ibcon#*before write, iclass 14, count 0 2006.202.01:41:11.84#ibcon#enter sib2, iclass 14, count 0 2006.202.01:41:11.84#ibcon#flushed, iclass 14, count 0 2006.202.01:41:11.84#ibcon#about to write, iclass 14, count 0 2006.202.01:41:11.84#ibcon#wrote, iclass 14, count 0 2006.202.01:41:11.84#ibcon#about to read 3, iclass 14, count 0 2006.202.01:41:11.88#ibcon#read 3, iclass 14, count 0 2006.202.01:41:11.88#ibcon#about to read 4, iclass 14, count 0 2006.202.01:41:11.88#ibcon#read 4, iclass 14, count 0 2006.202.01:41:11.88#ibcon#about to read 5, iclass 14, count 0 2006.202.01:41:11.88#ibcon#read 5, iclass 14, count 0 2006.202.01:41:11.88#ibcon#about to read 6, iclass 14, count 0 2006.202.01:41:11.88#ibcon#read 6, iclass 14, count 0 2006.202.01:41:11.88#ibcon#end of sib2, iclass 14, count 0 2006.202.01:41:11.88#ibcon#*after write, iclass 14, count 0 2006.202.01:41:11.88#ibcon#*before return 0, iclass 14, count 0 2006.202.01:41:11.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:41:11.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.202.01:41:11.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.01:41:11.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.01:41:11.88$vck44/va=2,7 2006.202.01:41:11.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.01:41:11.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.01:41:11.88#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:11.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:11.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:11.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:11.94#ibcon#enter wrdev, iclass 16, count 2 2006.202.01:41:11.94#ibcon#first serial, iclass 16, count 2 2006.202.01:41:11.94#ibcon#enter sib2, iclass 16, count 2 2006.202.01:41:11.94#ibcon#flushed, iclass 16, count 2 2006.202.01:41:11.94#ibcon#about to write, iclass 16, count 2 2006.202.01:41:11.94#ibcon#wrote, iclass 16, count 2 2006.202.01:41:11.94#ibcon#about to read 3, iclass 16, count 2 2006.202.01:41:11.96#ibcon#read 3, iclass 16, count 2 2006.202.01:41:11.96#ibcon#about to read 4, iclass 16, count 2 2006.202.01:41:11.96#ibcon#read 4, iclass 16, count 2 2006.202.01:41:11.96#ibcon#about to read 5, iclass 16, count 2 2006.202.01:41:11.96#ibcon#read 5, iclass 16, count 2 2006.202.01:41:11.96#ibcon#about to read 6, iclass 16, count 2 2006.202.01:41:11.96#ibcon#read 6, iclass 16, count 2 2006.202.01:41:11.96#ibcon#end of sib2, iclass 16, count 2 2006.202.01:41:11.96#ibcon#*mode == 0, iclass 16, count 2 2006.202.01:41:11.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.01:41:11.96#ibcon#[25=AT02-07\r\n] 2006.202.01:41:11.96#ibcon#*before write, iclass 16, count 2 2006.202.01:41:11.96#ibcon#enter sib2, iclass 16, count 2 2006.202.01:41:11.96#ibcon#flushed, iclass 16, count 2 2006.202.01:41:11.96#ibcon#about to write, iclass 16, count 2 2006.202.01:41:11.96#ibcon#wrote, iclass 16, count 2 2006.202.01:41:11.96#ibcon#about to read 3, iclass 16, count 2 2006.202.01:41:11.99#ibcon#read 3, iclass 16, count 2 2006.202.01:41:11.99#ibcon#about to read 4, iclass 16, count 2 2006.202.01:41:11.99#ibcon#read 4, iclass 16, count 2 2006.202.01:41:11.99#ibcon#about to read 5, iclass 16, count 2 2006.202.01:41:11.99#ibcon#read 5, iclass 16, count 2 2006.202.01:41:11.99#ibcon#about to read 6, iclass 16, count 2 2006.202.01:41:11.99#ibcon#read 6, iclass 16, count 2 2006.202.01:41:11.99#ibcon#end of sib2, iclass 16, count 2 2006.202.01:41:11.99#ibcon#*after write, iclass 16, count 2 2006.202.01:41:11.99#ibcon#*before return 0, iclass 16, count 2 2006.202.01:41:11.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:11.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:11.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.01:41:11.99#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:11.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:12.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:12.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:12.11#ibcon#enter wrdev, iclass 16, count 0 2006.202.01:41:12.11#ibcon#first serial, iclass 16, count 0 2006.202.01:41:12.11#ibcon#enter sib2, iclass 16, count 0 2006.202.01:41:12.11#ibcon#flushed, iclass 16, count 0 2006.202.01:41:12.11#ibcon#about to write, iclass 16, count 0 2006.202.01:41:12.11#ibcon#wrote, iclass 16, count 0 2006.202.01:41:12.11#ibcon#about to read 3, iclass 16, count 0 2006.202.01:41:12.13#ibcon#read 3, iclass 16, count 0 2006.202.01:41:12.13#ibcon#about to read 4, iclass 16, count 0 2006.202.01:41:12.13#ibcon#read 4, iclass 16, count 0 2006.202.01:41:12.13#ibcon#about to read 5, iclass 16, count 0 2006.202.01:41:12.13#ibcon#read 5, iclass 16, count 0 2006.202.01:41:12.13#ibcon#about to read 6, iclass 16, count 0 2006.202.01:41:12.13#ibcon#read 6, iclass 16, count 0 2006.202.01:41:12.13#ibcon#end of sib2, iclass 16, count 0 2006.202.01:41:12.13#ibcon#*mode == 0, iclass 16, count 0 2006.202.01:41:12.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.01:41:12.13#ibcon#[25=USB\r\n] 2006.202.01:41:12.13#ibcon#*before write, iclass 16, count 0 2006.202.01:41:12.13#ibcon#enter sib2, iclass 16, count 0 2006.202.01:41:12.13#ibcon#flushed, iclass 16, count 0 2006.202.01:41:12.13#ibcon#about to write, iclass 16, count 0 2006.202.01:41:12.13#ibcon#wrote, iclass 16, count 0 2006.202.01:41:12.13#ibcon#about to read 3, iclass 16, count 0 2006.202.01:41:12.16#ibcon#read 3, iclass 16, count 0 2006.202.01:41:12.16#ibcon#about to read 4, iclass 16, count 0 2006.202.01:41:12.16#ibcon#read 4, iclass 16, count 0 2006.202.01:41:12.16#ibcon#about to read 5, iclass 16, count 0 2006.202.01:41:12.16#ibcon#read 5, iclass 16, count 0 2006.202.01:41:12.16#ibcon#about to read 6, iclass 16, count 0 2006.202.01:41:12.16#ibcon#read 6, iclass 16, count 0 2006.202.01:41:12.16#ibcon#end of sib2, iclass 16, count 0 2006.202.01:41:12.16#ibcon#*after write, iclass 16, count 0 2006.202.01:41:12.16#ibcon#*before return 0, iclass 16, count 0 2006.202.01:41:12.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:12.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:12.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.01:41:12.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.01:41:12.16$vck44/valo=3,564.99 2006.202.01:41:12.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.01:41:12.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.01:41:12.16#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:12.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:12.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:12.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:12.16#ibcon#enter wrdev, iclass 18, count 0 2006.202.01:41:12.16#ibcon#first serial, iclass 18, count 0 2006.202.01:41:12.16#ibcon#enter sib2, iclass 18, count 0 2006.202.01:41:12.16#ibcon#flushed, iclass 18, count 0 2006.202.01:41:12.16#ibcon#about to write, iclass 18, count 0 2006.202.01:41:12.16#ibcon#wrote, iclass 18, count 0 2006.202.01:41:12.16#ibcon#about to read 3, iclass 18, count 0 2006.202.01:41:12.18#ibcon#read 3, iclass 18, count 0 2006.202.01:41:12.18#ibcon#about to read 4, iclass 18, count 0 2006.202.01:41:12.18#ibcon#read 4, iclass 18, count 0 2006.202.01:41:12.18#ibcon#about to read 5, iclass 18, count 0 2006.202.01:41:12.18#ibcon#read 5, iclass 18, count 0 2006.202.01:41:12.18#ibcon#about to read 6, iclass 18, count 0 2006.202.01:41:12.18#ibcon#read 6, iclass 18, count 0 2006.202.01:41:12.18#ibcon#end of sib2, iclass 18, count 0 2006.202.01:41:12.18#ibcon#*mode == 0, iclass 18, count 0 2006.202.01:41:12.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.01:41:12.18#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.01:41:12.18#ibcon#*before write, iclass 18, count 0 2006.202.01:41:12.18#ibcon#enter sib2, iclass 18, count 0 2006.202.01:41:12.18#ibcon#flushed, iclass 18, count 0 2006.202.01:41:12.18#ibcon#about to write, iclass 18, count 0 2006.202.01:41:12.18#ibcon#wrote, iclass 18, count 0 2006.202.01:41:12.18#ibcon#about to read 3, iclass 18, count 0 2006.202.01:41:12.22#ibcon#read 3, iclass 18, count 0 2006.202.01:41:12.22#ibcon#about to read 4, iclass 18, count 0 2006.202.01:41:12.22#ibcon#read 4, iclass 18, count 0 2006.202.01:41:12.22#ibcon#about to read 5, iclass 18, count 0 2006.202.01:41:12.22#ibcon#read 5, iclass 18, count 0 2006.202.01:41:12.22#ibcon#about to read 6, iclass 18, count 0 2006.202.01:41:12.22#ibcon#read 6, iclass 18, count 0 2006.202.01:41:12.22#ibcon#end of sib2, iclass 18, count 0 2006.202.01:41:12.22#ibcon#*after write, iclass 18, count 0 2006.202.01:41:12.22#ibcon#*before return 0, iclass 18, count 0 2006.202.01:41:12.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:12.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:12.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.01:41:12.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.01:41:12.22$vck44/va=3,8 2006.202.01:41:12.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.01:41:12.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.01:41:12.22#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:12.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:12.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:12.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:12.28#ibcon#enter wrdev, iclass 20, count 2 2006.202.01:41:12.28#ibcon#first serial, iclass 20, count 2 2006.202.01:41:12.28#ibcon#enter sib2, iclass 20, count 2 2006.202.01:41:12.28#ibcon#flushed, iclass 20, count 2 2006.202.01:41:12.28#ibcon#about to write, iclass 20, count 2 2006.202.01:41:12.28#ibcon#wrote, iclass 20, count 2 2006.202.01:41:12.28#ibcon#about to read 3, iclass 20, count 2 2006.202.01:41:12.30#ibcon#read 3, iclass 20, count 2 2006.202.01:41:12.30#ibcon#about to read 4, iclass 20, count 2 2006.202.01:41:12.30#ibcon#read 4, iclass 20, count 2 2006.202.01:41:12.30#ibcon#about to read 5, iclass 20, count 2 2006.202.01:41:12.30#ibcon#read 5, iclass 20, count 2 2006.202.01:41:12.30#ibcon#about to read 6, iclass 20, count 2 2006.202.01:41:12.30#ibcon#read 6, iclass 20, count 2 2006.202.01:41:12.30#ibcon#end of sib2, iclass 20, count 2 2006.202.01:41:12.30#ibcon#*mode == 0, iclass 20, count 2 2006.202.01:41:12.30#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.01:41:12.30#ibcon#[25=AT03-08\r\n] 2006.202.01:41:12.30#ibcon#*before write, iclass 20, count 2 2006.202.01:41:12.30#ibcon#enter sib2, iclass 20, count 2 2006.202.01:41:12.30#ibcon#flushed, iclass 20, count 2 2006.202.01:41:12.30#ibcon#about to write, iclass 20, count 2 2006.202.01:41:12.30#ibcon#wrote, iclass 20, count 2 2006.202.01:41:12.30#ibcon#about to read 3, iclass 20, count 2 2006.202.01:41:12.33#ibcon#read 3, iclass 20, count 2 2006.202.01:41:12.33#ibcon#about to read 4, iclass 20, count 2 2006.202.01:41:12.33#ibcon#read 4, iclass 20, count 2 2006.202.01:41:12.33#ibcon#about to read 5, iclass 20, count 2 2006.202.01:41:12.33#ibcon#read 5, iclass 20, count 2 2006.202.01:41:12.33#ibcon#about to read 6, iclass 20, count 2 2006.202.01:41:12.33#ibcon#read 6, iclass 20, count 2 2006.202.01:41:12.33#ibcon#end of sib2, iclass 20, count 2 2006.202.01:41:12.33#ibcon#*after write, iclass 20, count 2 2006.202.01:41:12.33#ibcon#*before return 0, iclass 20, count 2 2006.202.01:41:12.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:12.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:12.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.01:41:12.33#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:12.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:12.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:12.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:12.45#ibcon#enter wrdev, iclass 20, count 0 2006.202.01:41:12.45#ibcon#first serial, iclass 20, count 0 2006.202.01:41:12.45#ibcon#enter sib2, iclass 20, count 0 2006.202.01:41:12.45#ibcon#flushed, iclass 20, count 0 2006.202.01:41:12.45#ibcon#about to write, iclass 20, count 0 2006.202.01:41:12.45#ibcon#wrote, iclass 20, count 0 2006.202.01:41:12.45#ibcon#about to read 3, iclass 20, count 0 2006.202.01:41:12.47#ibcon#read 3, iclass 20, count 0 2006.202.01:41:12.47#ibcon#about to read 4, iclass 20, count 0 2006.202.01:41:12.47#ibcon#read 4, iclass 20, count 0 2006.202.01:41:12.47#ibcon#about to read 5, iclass 20, count 0 2006.202.01:41:12.47#ibcon#read 5, iclass 20, count 0 2006.202.01:41:12.47#ibcon#about to read 6, iclass 20, count 0 2006.202.01:41:12.47#ibcon#read 6, iclass 20, count 0 2006.202.01:41:12.47#ibcon#end of sib2, iclass 20, count 0 2006.202.01:41:12.47#ibcon#*mode == 0, iclass 20, count 0 2006.202.01:41:12.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.01:41:12.47#ibcon#[25=USB\r\n] 2006.202.01:41:12.47#ibcon#*before write, iclass 20, count 0 2006.202.01:41:12.47#ibcon#enter sib2, iclass 20, count 0 2006.202.01:41:12.47#ibcon#flushed, iclass 20, count 0 2006.202.01:41:12.47#ibcon#about to write, iclass 20, count 0 2006.202.01:41:12.47#ibcon#wrote, iclass 20, count 0 2006.202.01:41:12.47#ibcon#about to read 3, iclass 20, count 0 2006.202.01:41:12.50#ibcon#read 3, iclass 20, count 0 2006.202.01:41:12.50#ibcon#about to read 4, iclass 20, count 0 2006.202.01:41:12.50#ibcon#read 4, iclass 20, count 0 2006.202.01:41:12.50#ibcon#about to read 5, iclass 20, count 0 2006.202.01:41:12.50#ibcon#read 5, iclass 20, count 0 2006.202.01:41:12.50#ibcon#about to read 6, iclass 20, count 0 2006.202.01:41:12.50#ibcon#read 6, iclass 20, count 0 2006.202.01:41:12.50#ibcon#end of sib2, iclass 20, count 0 2006.202.01:41:12.50#ibcon#*after write, iclass 20, count 0 2006.202.01:41:12.50#ibcon#*before return 0, iclass 20, count 0 2006.202.01:41:12.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:12.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:12.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.01:41:12.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.01:41:12.50$vck44/valo=4,624.99 2006.202.01:41:12.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.01:41:12.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.01:41:12.50#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:12.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:12.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:12.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:12.50#ibcon#enter wrdev, iclass 22, count 0 2006.202.01:41:12.50#ibcon#first serial, iclass 22, count 0 2006.202.01:41:12.50#ibcon#enter sib2, iclass 22, count 0 2006.202.01:41:12.50#ibcon#flushed, iclass 22, count 0 2006.202.01:41:12.50#ibcon#about to write, iclass 22, count 0 2006.202.01:41:12.50#ibcon#wrote, iclass 22, count 0 2006.202.01:41:12.50#ibcon#about to read 3, iclass 22, count 0 2006.202.01:41:12.52#ibcon#read 3, iclass 22, count 0 2006.202.01:41:12.52#ibcon#about to read 4, iclass 22, count 0 2006.202.01:41:12.52#ibcon#read 4, iclass 22, count 0 2006.202.01:41:12.52#ibcon#about to read 5, iclass 22, count 0 2006.202.01:41:12.52#ibcon#read 5, iclass 22, count 0 2006.202.01:41:12.52#ibcon#about to read 6, iclass 22, count 0 2006.202.01:41:12.52#ibcon#read 6, iclass 22, count 0 2006.202.01:41:12.52#ibcon#end of sib2, iclass 22, count 0 2006.202.01:41:12.52#ibcon#*mode == 0, iclass 22, count 0 2006.202.01:41:12.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.01:41:12.52#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.01:41:12.52#ibcon#*before write, iclass 22, count 0 2006.202.01:41:12.52#ibcon#enter sib2, iclass 22, count 0 2006.202.01:41:12.52#ibcon#flushed, iclass 22, count 0 2006.202.01:41:12.52#ibcon#about to write, iclass 22, count 0 2006.202.01:41:12.52#ibcon#wrote, iclass 22, count 0 2006.202.01:41:12.52#ibcon#about to read 3, iclass 22, count 0 2006.202.01:41:12.56#ibcon#read 3, iclass 22, count 0 2006.202.01:41:12.56#ibcon#about to read 4, iclass 22, count 0 2006.202.01:41:12.56#ibcon#read 4, iclass 22, count 0 2006.202.01:41:12.56#ibcon#about to read 5, iclass 22, count 0 2006.202.01:41:12.56#ibcon#read 5, iclass 22, count 0 2006.202.01:41:12.56#ibcon#about to read 6, iclass 22, count 0 2006.202.01:41:12.56#ibcon#read 6, iclass 22, count 0 2006.202.01:41:12.56#ibcon#end of sib2, iclass 22, count 0 2006.202.01:41:12.56#ibcon#*after write, iclass 22, count 0 2006.202.01:41:12.56#ibcon#*before return 0, iclass 22, count 0 2006.202.01:41:12.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:12.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:12.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.01:41:12.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.01:41:12.56$vck44/va=4,7 2006.202.01:41:12.56#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.01:41:12.56#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.01:41:12.56#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:12.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:12.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:12.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:12.62#ibcon#enter wrdev, iclass 24, count 2 2006.202.01:41:12.62#ibcon#first serial, iclass 24, count 2 2006.202.01:41:12.62#ibcon#enter sib2, iclass 24, count 2 2006.202.01:41:12.62#ibcon#flushed, iclass 24, count 2 2006.202.01:41:12.62#ibcon#about to write, iclass 24, count 2 2006.202.01:41:12.62#ibcon#wrote, iclass 24, count 2 2006.202.01:41:12.62#ibcon#about to read 3, iclass 24, count 2 2006.202.01:41:12.64#ibcon#read 3, iclass 24, count 2 2006.202.01:41:12.64#ibcon#about to read 4, iclass 24, count 2 2006.202.01:41:12.64#ibcon#read 4, iclass 24, count 2 2006.202.01:41:12.64#ibcon#about to read 5, iclass 24, count 2 2006.202.01:41:12.64#ibcon#read 5, iclass 24, count 2 2006.202.01:41:12.64#ibcon#about to read 6, iclass 24, count 2 2006.202.01:41:12.64#ibcon#read 6, iclass 24, count 2 2006.202.01:41:12.64#ibcon#end of sib2, iclass 24, count 2 2006.202.01:41:12.64#ibcon#*mode == 0, iclass 24, count 2 2006.202.01:41:12.64#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.01:41:12.64#ibcon#[25=AT04-07\r\n] 2006.202.01:41:12.64#ibcon#*before write, iclass 24, count 2 2006.202.01:41:12.64#ibcon#enter sib2, iclass 24, count 2 2006.202.01:41:12.64#ibcon#flushed, iclass 24, count 2 2006.202.01:41:12.64#ibcon#about to write, iclass 24, count 2 2006.202.01:41:12.64#ibcon#wrote, iclass 24, count 2 2006.202.01:41:12.64#ibcon#about to read 3, iclass 24, count 2 2006.202.01:41:12.67#ibcon#read 3, iclass 24, count 2 2006.202.01:41:12.68#ibcon#about to read 4, iclass 24, count 2 2006.202.01:41:12.68#ibcon#read 4, iclass 24, count 2 2006.202.01:41:12.68#ibcon#about to read 5, iclass 24, count 2 2006.202.01:41:12.68#ibcon#read 5, iclass 24, count 2 2006.202.01:41:12.68#ibcon#about to read 6, iclass 24, count 2 2006.202.01:41:12.68#ibcon#read 6, iclass 24, count 2 2006.202.01:41:12.68#ibcon#end of sib2, iclass 24, count 2 2006.202.01:41:12.68#ibcon#*after write, iclass 24, count 2 2006.202.01:41:12.68#ibcon#*before return 0, iclass 24, count 2 2006.202.01:41:12.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:12.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:12.68#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.01:41:12.68#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:12.68#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:12.80#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:12.80#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:12.80#ibcon#enter wrdev, iclass 24, count 0 2006.202.01:41:12.80#ibcon#first serial, iclass 24, count 0 2006.202.01:41:12.80#ibcon#enter sib2, iclass 24, count 0 2006.202.01:41:12.80#ibcon#flushed, iclass 24, count 0 2006.202.01:41:12.80#ibcon#about to write, iclass 24, count 0 2006.202.01:41:12.80#ibcon#wrote, iclass 24, count 0 2006.202.01:41:12.80#ibcon#about to read 3, iclass 24, count 0 2006.202.01:41:12.82#ibcon#read 3, iclass 24, count 0 2006.202.01:41:12.82#ibcon#about to read 4, iclass 24, count 0 2006.202.01:41:12.82#ibcon#read 4, iclass 24, count 0 2006.202.01:41:12.82#ibcon#about to read 5, iclass 24, count 0 2006.202.01:41:12.82#ibcon#read 5, iclass 24, count 0 2006.202.01:41:12.82#ibcon#about to read 6, iclass 24, count 0 2006.202.01:41:12.82#ibcon#read 6, iclass 24, count 0 2006.202.01:41:12.82#ibcon#end of sib2, iclass 24, count 0 2006.202.01:41:12.82#ibcon#*mode == 0, iclass 24, count 0 2006.202.01:41:12.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.01:41:12.82#ibcon#[25=USB\r\n] 2006.202.01:41:12.82#ibcon#*before write, iclass 24, count 0 2006.202.01:41:12.82#ibcon#enter sib2, iclass 24, count 0 2006.202.01:41:12.82#ibcon#flushed, iclass 24, count 0 2006.202.01:41:12.82#ibcon#about to write, iclass 24, count 0 2006.202.01:41:12.82#ibcon#wrote, iclass 24, count 0 2006.202.01:41:12.82#ibcon#about to read 3, iclass 24, count 0 2006.202.01:41:12.85#ibcon#read 3, iclass 24, count 0 2006.202.01:41:12.85#ibcon#about to read 4, iclass 24, count 0 2006.202.01:41:12.85#ibcon#read 4, iclass 24, count 0 2006.202.01:41:12.85#ibcon#about to read 5, iclass 24, count 0 2006.202.01:41:12.85#ibcon#read 5, iclass 24, count 0 2006.202.01:41:12.85#ibcon#about to read 6, iclass 24, count 0 2006.202.01:41:12.85#ibcon#read 6, iclass 24, count 0 2006.202.01:41:12.85#ibcon#end of sib2, iclass 24, count 0 2006.202.01:41:12.85#ibcon#*after write, iclass 24, count 0 2006.202.01:41:12.85#ibcon#*before return 0, iclass 24, count 0 2006.202.01:41:12.85#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:12.85#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:12.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.01:41:12.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.01:41:12.85$vck44/valo=5,734.99 2006.202.01:41:12.85#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.01:41:12.85#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.01:41:12.85#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:12.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:12.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:12.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:12.85#ibcon#enter wrdev, iclass 26, count 0 2006.202.01:41:12.85#ibcon#first serial, iclass 26, count 0 2006.202.01:41:12.85#ibcon#enter sib2, iclass 26, count 0 2006.202.01:41:12.85#ibcon#flushed, iclass 26, count 0 2006.202.01:41:12.85#ibcon#about to write, iclass 26, count 0 2006.202.01:41:12.85#ibcon#wrote, iclass 26, count 0 2006.202.01:41:12.85#ibcon#about to read 3, iclass 26, count 0 2006.202.01:41:12.87#ibcon#read 3, iclass 26, count 0 2006.202.01:41:12.87#ibcon#about to read 4, iclass 26, count 0 2006.202.01:41:12.87#ibcon#read 4, iclass 26, count 0 2006.202.01:41:12.87#ibcon#about to read 5, iclass 26, count 0 2006.202.01:41:12.87#ibcon#read 5, iclass 26, count 0 2006.202.01:41:12.87#ibcon#about to read 6, iclass 26, count 0 2006.202.01:41:12.87#ibcon#read 6, iclass 26, count 0 2006.202.01:41:12.87#ibcon#end of sib2, iclass 26, count 0 2006.202.01:41:12.87#ibcon#*mode == 0, iclass 26, count 0 2006.202.01:41:12.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.01:41:12.87#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.01:41:12.87#ibcon#*before write, iclass 26, count 0 2006.202.01:41:12.87#ibcon#enter sib2, iclass 26, count 0 2006.202.01:41:12.87#ibcon#flushed, iclass 26, count 0 2006.202.01:41:12.87#ibcon#about to write, iclass 26, count 0 2006.202.01:41:12.87#ibcon#wrote, iclass 26, count 0 2006.202.01:41:12.87#ibcon#about to read 3, iclass 26, count 0 2006.202.01:41:12.91#ibcon#read 3, iclass 26, count 0 2006.202.01:41:12.91#ibcon#about to read 4, iclass 26, count 0 2006.202.01:41:12.91#ibcon#read 4, iclass 26, count 0 2006.202.01:41:12.91#ibcon#about to read 5, iclass 26, count 0 2006.202.01:41:12.91#ibcon#read 5, iclass 26, count 0 2006.202.01:41:12.91#ibcon#about to read 6, iclass 26, count 0 2006.202.01:41:12.91#ibcon#read 6, iclass 26, count 0 2006.202.01:41:12.91#ibcon#end of sib2, iclass 26, count 0 2006.202.01:41:12.91#ibcon#*after write, iclass 26, count 0 2006.202.01:41:12.91#ibcon#*before return 0, iclass 26, count 0 2006.202.01:41:12.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:12.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:12.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.01:41:12.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.01:41:12.91$vck44/va=5,4 2006.202.01:41:12.91#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.01:41:12.91#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.01:41:12.91#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:12.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:12.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:12.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:12.97#ibcon#enter wrdev, iclass 28, count 2 2006.202.01:41:12.97#ibcon#first serial, iclass 28, count 2 2006.202.01:41:12.97#ibcon#enter sib2, iclass 28, count 2 2006.202.01:41:12.97#ibcon#flushed, iclass 28, count 2 2006.202.01:41:12.97#ibcon#about to write, iclass 28, count 2 2006.202.01:41:12.97#ibcon#wrote, iclass 28, count 2 2006.202.01:41:12.97#ibcon#about to read 3, iclass 28, count 2 2006.202.01:41:12.99#ibcon#read 3, iclass 28, count 2 2006.202.01:41:12.99#ibcon#about to read 4, iclass 28, count 2 2006.202.01:41:12.99#ibcon#read 4, iclass 28, count 2 2006.202.01:41:12.99#ibcon#about to read 5, iclass 28, count 2 2006.202.01:41:12.99#ibcon#read 5, iclass 28, count 2 2006.202.01:41:12.99#ibcon#about to read 6, iclass 28, count 2 2006.202.01:41:12.99#ibcon#read 6, iclass 28, count 2 2006.202.01:41:12.99#ibcon#end of sib2, iclass 28, count 2 2006.202.01:41:12.99#ibcon#*mode == 0, iclass 28, count 2 2006.202.01:41:12.99#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.01:41:12.99#ibcon#[25=AT05-04\r\n] 2006.202.01:41:12.99#ibcon#*before write, iclass 28, count 2 2006.202.01:41:12.99#ibcon#enter sib2, iclass 28, count 2 2006.202.01:41:12.99#ibcon#flushed, iclass 28, count 2 2006.202.01:41:12.99#ibcon#about to write, iclass 28, count 2 2006.202.01:41:12.99#ibcon#wrote, iclass 28, count 2 2006.202.01:41:12.99#ibcon#about to read 3, iclass 28, count 2 2006.202.01:41:13.02#ibcon#read 3, iclass 28, count 2 2006.202.01:41:13.02#ibcon#about to read 4, iclass 28, count 2 2006.202.01:41:13.02#ibcon#read 4, iclass 28, count 2 2006.202.01:41:13.02#ibcon#about to read 5, iclass 28, count 2 2006.202.01:41:13.02#ibcon#read 5, iclass 28, count 2 2006.202.01:41:13.02#ibcon#about to read 6, iclass 28, count 2 2006.202.01:41:13.02#ibcon#read 6, iclass 28, count 2 2006.202.01:41:13.02#ibcon#end of sib2, iclass 28, count 2 2006.202.01:41:13.02#ibcon#*after write, iclass 28, count 2 2006.202.01:41:13.02#ibcon#*before return 0, iclass 28, count 2 2006.202.01:41:13.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:13.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:13.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.01:41:13.02#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:13.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:13.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:13.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:13.14#ibcon#enter wrdev, iclass 28, count 0 2006.202.01:41:13.14#ibcon#first serial, iclass 28, count 0 2006.202.01:41:13.14#ibcon#enter sib2, iclass 28, count 0 2006.202.01:41:13.14#ibcon#flushed, iclass 28, count 0 2006.202.01:41:13.14#ibcon#about to write, iclass 28, count 0 2006.202.01:41:13.14#ibcon#wrote, iclass 28, count 0 2006.202.01:41:13.14#ibcon#about to read 3, iclass 28, count 0 2006.202.01:41:13.16#ibcon#read 3, iclass 28, count 0 2006.202.01:41:13.16#ibcon#about to read 4, iclass 28, count 0 2006.202.01:41:13.16#ibcon#read 4, iclass 28, count 0 2006.202.01:41:13.16#ibcon#about to read 5, iclass 28, count 0 2006.202.01:41:13.16#ibcon#read 5, iclass 28, count 0 2006.202.01:41:13.16#ibcon#about to read 6, iclass 28, count 0 2006.202.01:41:13.16#ibcon#read 6, iclass 28, count 0 2006.202.01:41:13.16#ibcon#end of sib2, iclass 28, count 0 2006.202.01:41:13.16#ibcon#*mode == 0, iclass 28, count 0 2006.202.01:41:13.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.01:41:13.16#ibcon#[25=USB\r\n] 2006.202.01:41:13.16#ibcon#*before write, iclass 28, count 0 2006.202.01:41:13.16#ibcon#enter sib2, iclass 28, count 0 2006.202.01:41:13.16#ibcon#flushed, iclass 28, count 0 2006.202.01:41:13.16#ibcon#about to write, iclass 28, count 0 2006.202.01:41:13.16#ibcon#wrote, iclass 28, count 0 2006.202.01:41:13.16#ibcon#about to read 3, iclass 28, count 0 2006.202.01:41:13.19#ibcon#read 3, iclass 28, count 0 2006.202.01:41:13.19#ibcon#about to read 4, iclass 28, count 0 2006.202.01:41:13.19#ibcon#read 4, iclass 28, count 0 2006.202.01:41:13.19#ibcon#about to read 5, iclass 28, count 0 2006.202.01:41:13.19#ibcon#read 5, iclass 28, count 0 2006.202.01:41:13.19#ibcon#about to read 6, iclass 28, count 0 2006.202.01:41:13.19#ibcon#read 6, iclass 28, count 0 2006.202.01:41:13.19#ibcon#end of sib2, iclass 28, count 0 2006.202.01:41:13.19#ibcon#*after write, iclass 28, count 0 2006.202.01:41:13.19#ibcon#*before return 0, iclass 28, count 0 2006.202.01:41:13.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:13.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:13.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.01:41:13.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.01:41:13.19$vck44/valo=6,814.99 2006.202.01:41:13.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.01:41:13.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.01:41:13.19#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:13.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:13.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:13.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:13.19#ibcon#enter wrdev, iclass 30, count 0 2006.202.01:41:13.19#ibcon#first serial, iclass 30, count 0 2006.202.01:41:13.19#ibcon#enter sib2, iclass 30, count 0 2006.202.01:41:13.19#ibcon#flushed, iclass 30, count 0 2006.202.01:41:13.19#ibcon#about to write, iclass 30, count 0 2006.202.01:41:13.19#ibcon#wrote, iclass 30, count 0 2006.202.01:41:13.19#ibcon#about to read 3, iclass 30, count 0 2006.202.01:41:13.21#ibcon#read 3, iclass 30, count 0 2006.202.01:41:13.21#ibcon#about to read 4, iclass 30, count 0 2006.202.01:41:13.21#ibcon#read 4, iclass 30, count 0 2006.202.01:41:13.21#ibcon#about to read 5, iclass 30, count 0 2006.202.01:41:13.21#ibcon#read 5, iclass 30, count 0 2006.202.01:41:13.21#ibcon#about to read 6, iclass 30, count 0 2006.202.01:41:13.21#ibcon#read 6, iclass 30, count 0 2006.202.01:41:13.21#ibcon#end of sib2, iclass 30, count 0 2006.202.01:41:13.21#ibcon#*mode == 0, iclass 30, count 0 2006.202.01:41:13.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.01:41:13.21#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.01:41:13.21#ibcon#*before write, iclass 30, count 0 2006.202.01:41:13.21#ibcon#enter sib2, iclass 30, count 0 2006.202.01:41:13.21#ibcon#flushed, iclass 30, count 0 2006.202.01:41:13.21#ibcon#about to write, iclass 30, count 0 2006.202.01:41:13.21#ibcon#wrote, iclass 30, count 0 2006.202.01:41:13.21#ibcon#about to read 3, iclass 30, count 0 2006.202.01:41:13.25#ibcon#read 3, iclass 30, count 0 2006.202.01:41:13.25#ibcon#about to read 4, iclass 30, count 0 2006.202.01:41:13.25#ibcon#read 4, iclass 30, count 0 2006.202.01:41:13.25#ibcon#about to read 5, iclass 30, count 0 2006.202.01:41:13.25#ibcon#read 5, iclass 30, count 0 2006.202.01:41:13.25#ibcon#about to read 6, iclass 30, count 0 2006.202.01:41:13.25#ibcon#read 6, iclass 30, count 0 2006.202.01:41:13.25#ibcon#end of sib2, iclass 30, count 0 2006.202.01:41:13.25#ibcon#*after write, iclass 30, count 0 2006.202.01:41:13.25#ibcon#*before return 0, iclass 30, count 0 2006.202.01:41:13.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:13.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:13.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.01:41:13.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.01:41:13.25$vck44/va=6,5 2006.202.01:41:13.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.01:41:13.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.01:41:13.25#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:13.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:13.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:13.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:13.31#ibcon#enter wrdev, iclass 32, count 2 2006.202.01:41:13.31#ibcon#first serial, iclass 32, count 2 2006.202.01:41:13.31#ibcon#enter sib2, iclass 32, count 2 2006.202.01:41:13.31#ibcon#flushed, iclass 32, count 2 2006.202.01:41:13.31#ibcon#about to write, iclass 32, count 2 2006.202.01:41:13.31#ibcon#wrote, iclass 32, count 2 2006.202.01:41:13.31#ibcon#about to read 3, iclass 32, count 2 2006.202.01:41:13.33#ibcon#read 3, iclass 32, count 2 2006.202.01:41:13.33#ibcon#about to read 4, iclass 32, count 2 2006.202.01:41:13.33#ibcon#read 4, iclass 32, count 2 2006.202.01:41:13.33#ibcon#about to read 5, iclass 32, count 2 2006.202.01:41:13.33#ibcon#read 5, iclass 32, count 2 2006.202.01:41:13.33#ibcon#about to read 6, iclass 32, count 2 2006.202.01:41:13.33#ibcon#read 6, iclass 32, count 2 2006.202.01:41:13.33#ibcon#end of sib2, iclass 32, count 2 2006.202.01:41:13.33#ibcon#*mode == 0, iclass 32, count 2 2006.202.01:41:13.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.01:41:13.33#ibcon#[25=AT06-05\r\n] 2006.202.01:41:13.33#ibcon#*before write, iclass 32, count 2 2006.202.01:41:13.33#ibcon#enter sib2, iclass 32, count 2 2006.202.01:41:13.33#ibcon#flushed, iclass 32, count 2 2006.202.01:41:13.33#ibcon#about to write, iclass 32, count 2 2006.202.01:41:13.33#ibcon#wrote, iclass 32, count 2 2006.202.01:41:13.33#ibcon#about to read 3, iclass 32, count 2 2006.202.01:41:13.36#ibcon#read 3, iclass 32, count 2 2006.202.01:41:13.36#ibcon#about to read 4, iclass 32, count 2 2006.202.01:41:13.36#ibcon#read 4, iclass 32, count 2 2006.202.01:41:13.36#ibcon#about to read 5, iclass 32, count 2 2006.202.01:41:13.36#ibcon#read 5, iclass 32, count 2 2006.202.01:41:13.36#ibcon#about to read 6, iclass 32, count 2 2006.202.01:41:13.36#ibcon#read 6, iclass 32, count 2 2006.202.01:41:13.36#ibcon#end of sib2, iclass 32, count 2 2006.202.01:41:13.36#ibcon#*after write, iclass 32, count 2 2006.202.01:41:13.36#ibcon#*before return 0, iclass 32, count 2 2006.202.01:41:13.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:13.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:13.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.01:41:13.36#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:13.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:13.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:13.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:13.48#ibcon#enter wrdev, iclass 32, count 0 2006.202.01:41:13.48#ibcon#first serial, iclass 32, count 0 2006.202.01:41:13.48#ibcon#enter sib2, iclass 32, count 0 2006.202.01:41:13.48#ibcon#flushed, iclass 32, count 0 2006.202.01:41:13.48#ibcon#about to write, iclass 32, count 0 2006.202.01:41:13.48#ibcon#wrote, iclass 32, count 0 2006.202.01:41:13.48#ibcon#about to read 3, iclass 32, count 0 2006.202.01:41:13.50#ibcon#read 3, iclass 32, count 0 2006.202.01:41:13.50#ibcon#about to read 4, iclass 32, count 0 2006.202.01:41:13.50#ibcon#read 4, iclass 32, count 0 2006.202.01:41:13.50#ibcon#about to read 5, iclass 32, count 0 2006.202.01:41:13.50#ibcon#read 5, iclass 32, count 0 2006.202.01:41:13.50#ibcon#about to read 6, iclass 32, count 0 2006.202.01:41:13.50#ibcon#read 6, iclass 32, count 0 2006.202.01:41:13.50#ibcon#end of sib2, iclass 32, count 0 2006.202.01:41:13.50#ibcon#*mode == 0, iclass 32, count 0 2006.202.01:41:13.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.01:41:13.50#ibcon#[25=USB\r\n] 2006.202.01:41:13.50#ibcon#*before write, iclass 32, count 0 2006.202.01:41:13.50#ibcon#enter sib2, iclass 32, count 0 2006.202.01:41:13.50#ibcon#flushed, iclass 32, count 0 2006.202.01:41:13.50#ibcon#about to write, iclass 32, count 0 2006.202.01:41:13.50#ibcon#wrote, iclass 32, count 0 2006.202.01:41:13.50#ibcon#about to read 3, iclass 32, count 0 2006.202.01:41:13.53#ibcon#read 3, iclass 32, count 0 2006.202.01:41:13.53#ibcon#about to read 4, iclass 32, count 0 2006.202.01:41:13.53#ibcon#read 4, iclass 32, count 0 2006.202.01:41:13.53#ibcon#about to read 5, iclass 32, count 0 2006.202.01:41:13.53#ibcon#read 5, iclass 32, count 0 2006.202.01:41:13.53#ibcon#about to read 6, iclass 32, count 0 2006.202.01:41:13.53#ibcon#read 6, iclass 32, count 0 2006.202.01:41:13.53#ibcon#end of sib2, iclass 32, count 0 2006.202.01:41:13.53#ibcon#*after write, iclass 32, count 0 2006.202.01:41:13.53#ibcon#*before return 0, iclass 32, count 0 2006.202.01:41:13.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:13.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:13.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.01:41:13.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.01:41:13.53$vck44/valo=7,864.99 2006.202.01:41:13.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.01:41:13.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.01:41:13.53#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:13.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:13.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:13.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:13.53#ibcon#enter wrdev, iclass 34, count 0 2006.202.01:41:13.53#ibcon#first serial, iclass 34, count 0 2006.202.01:41:13.53#ibcon#enter sib2, iclass 34, count 0 2006.202.01:41:13.53#ibcon#flushed, iclass 34, count 0 2006.202.01:41:13.53#ibcon#about to write, iclass 34, count 0 2006.202.01:41:13.53#ibcon#wrote, iclass 34, count 0 2006.202.01:41:13.53#ibcon#about to read 3, iclass 34, count 0 2006.202.01:41:13.55#ibcon#read 3, iclass 34, count 0 2006.202.01:41:13.55#ibcon#about to read 4, iclass 34, count 0 2006.202.01:41:13.55#ibcon#read 4, iclass 34, count 0 2006.202.01:41:13.55#ibcon#about to read 5, iclass 34, count 0 2006.202.01:41:13.55#ibcon#read 5, iclass 34, count 0 2006.202.01:41:13.55#ibcon#about to read 6, iclass 34, count 0 2006.202.01:41:13.55#ibcon#read 6, iclass 34, count 0 2006.202.01:41:13.55#ibcon#end of sib2, iclass 34, count 0 2006.202.01:41:13.55#ibcon#*mode == 0, iclass 34, count 0 2006.202.01:41:13.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.01:41:13.55#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.01:41:13.55#ibcon#*before write, iclass 34, count 0 2006.202.01:41:13.55#ibcon#enter sib2, iclass 34, count 0 2006.202.01:41:13.55#ibcon#flushed, iclass 34, count 0 2006.202.01:41:13.55#ibcon#about to write, iclass 34, count 0 2006.202.01:41:13.55#ibcon#wrote, iclass 34, count 0 2006.202.01:41:13.55#ibcon#about to read 3, iclass 34, count 0 2006.202.01:41:13.59#ibcon#read 3, iclass 34, count 0 2006.202.01:41:13.59#ibcon#about to read 4, iclass 34, count 0 2006.202.01:41:13.59#ibcon#read 4, iclass 34, count 0 2006.202.01:41:13.59#ibcon#about to read 5, iclass 34, count 0 2006.202.01:41:13.59#ibcon#read 5, iclass 34, count 0 2006.202.01:41:13.59#ibcon#about to read 6, iclass 34, count 0 2006.202.01:41:13.59#ibcon#read 6, iclass 34, count 0 2006.202.01:41:13.59#ibcon#end of sib2, iclass 34, count 0 2006.202.01:41:13.59#ibcon#*after write, iclass 34, count 0 2006.202.01:41:13.59#ibcon#*before return 0, iclass 34, count 0 2006.202.01:41:13.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:13.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:13.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.01:41:13.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.01:41:13.59$vck44/va=7,5 2006.202.01:41:13.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.01:41:13.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.01:41:13.59#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:13.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:13.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:13.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:13.65#ibcon#enter wrdev, iclass 36, count 2 2006.202.01:41:13.65#ibcon#first serial, iclass 36, count 2 2006.202.01:41:13.65#ibcon#enter sib2, iclass 36, count 2 2006.202.01:41:13.65#ibcon#flushed, iclass 36, count 2 2006.202.01:41:13.65#ibcon#about to write, iclass 36, count 2 2006.202.01:41:13.65#ibcon#wrote, iclass 36, count 2 2006.202.01:41:13.65#ibcon#about to read 3, iclass 36, count 2 2006.202.01:41:13.67#ibcon#read 3, iclass 36, count 2 2006.202.01:41:13.67#ibcon#about to read 4, iclass 36, count 2 2006.202.01:41:13.67#ibcon#read 4, iclass 36, count 2 2006.202.01:41:13.67#ibcon#about to read 5, iclass 36, count 2 2006.202.01:41:13.67#ibcon#read 5, iclass 36, count 2 2006.202.01:41:13.67#ibcon#about to read 6, iclass 36, count 2 2006.202.01:41:13.67#ibcon#read 6, iclass 36, count 2 2006.202.01:41:13.67#ibcon#end of sib2, iclass 36, count 2 2006.202.01:41:13.67#ibcon#*mode == 0, iclass 36, count 2 2006.202.01:41:13.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.01:41:13.67#ibcon#[25=AT07-05\r\n] 2006.202.01:41:13.67#ibcon#*before write, iclass 36, count 2 2006.202.01:41:13.67#ibcon#enter sib2, iclass 36, count 2 2006.202.01:41:13.67#ibcon#flushed, iclass 36, count 2 2006.202.01:41:13.67#ibcon#about to write, iclass 36, count 2 2006.202.01:41:13.67#ibcon#wrote, iclass 36, count 2 2006.202.01:41:13.67#ibcon#about to read 3, iclass 36, count 2 2006.202.01:41:13.70#ibcon#read 3, iclass 36, count 2 2006.202.01:41:13.71#ibcon#about to read 4, iclass 36, count 2 2006.202.01:41:13.71#ibcon#read 4, iclass 36, count 2 2006.202.01:41:13.71#ibcon#about to read 5, iclass 36, count 2 2006.202.01:41:13.71#ibcon#read 5, iclass 36, count 2 2006.202.01:41:13.71#ibcon#about to read 6, iclass 36, count 2 2006.202.01:41:13.71#ibcon#read 6, iclass 36, count 2 2006.202.01:41:13.71#ibcon#end of sib2, iclass 36, count 2 2006.202.01:41:13.71#ibcon#*after write, iclass 36, count 2 2006.202.01:41:13.71#ibcon#*before return 0, iclass 36, count 2 2006.202.01:41:13.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:13.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:13.71#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.01:41:13.71#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:13.71#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:13.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:13.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:13.83#ibcon#enter wrdev, iclass 36, count 0 2006.202.01:41:13.83#ibcon#first serial, iclass 36, count 0 2006.202.01:41:13.83#ibcon#enter sib2, iclass 36, count 0 2006.202.01:41:13.83#ibcon#flushed, iclass 36, count 0 2006.202.01:41:13.83#ibcon#about to write, iclass 36, count 0 2006.202.01:41:13.83#ibcon#wrote, iclass 36, count 0 2006.202.01:41:13.83#ibcon#about to read 3, iclass 36, count 0 2006.202.01:41:13.85#ibcon#read 3, iclass 36, count 0 2006.202.01:41:13.85#ibcon#about to read 4, iclass 36, count 0 2006.202.01:41:13.85#ibcon#read 4, iclass 36, count 0 2006.202.01:41:13.85#ibcon#about to read 5, iclass 36, count 0 2006.202.01:41:13.85#ibcon#read 5, iclass 36, count 0 2006.202.01:41:13.85#ibcon#about to read 6, iclass 36, count 0 2006.202.01:41:13.85#ibcon#read 6, iclass 36, count 0 2006.202.01:41:13.85#ibcon#end of sib2, iclass 36, count 0 2006.202.01:41:13.85#ibcon#*mode == 0, iclass 36, count 0 2006.202.01:41:13.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.01:41:13.85#ibcon#[25=USB\r\n] 2006.202.01:41:13.85#ibcon#*before write, iclass 36, count 0 2006.202.01:41:13.85#ibcon#enter sib2, iclass 36, count 0 2006.202.01:41:13.85#ibcon#flushed, iclass 36, count 0 2006.202.01:41:13.85#ibcon#about to write, iclass 36, count 0 2006.202.01:41:13.85#ibcon#wrote, iclass 36, count 0 2006.202.01:41:13.85#ibcon#about to read 3, iclass 36, count 0 2006.202.01:41:13.88#ibcon#read 3, iclass 36, count 0 2006.202.01:41:13.88#ibcon#about to read 4, iclass 36, count 0 2006.202.01:41:13.88#ibcon#read 4, iclass 36, count 0 2006.202.01:41:13.88#ibcon#about to read 5, iclass 36, count 0 2006.202.01:41:13.88#ibcon#read 5, iclass 36, count 0 2006.202.01:41:13.88#ibcon#about to read 6, iclass 36, count 0 2006.202.01:41:13.88#ibcon#read 6, iclass 36, count 0 2006.202.01:41:13.88#ibcon#end of sib2, iclass 36, count 0 2006.202.01:41:13.88#ibcon#*after write, iclass 36, count 0 2006.202.01:41:13.88#ibcon#*before return 0, iclass 36, count 0 2006.202.01:41:13.88#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:13.88#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:13.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.01:41:13.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.01:41:13.88$vck44/valo=8,884.99 2006.202.01:41:13.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.01:41:13.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.01:41:13.88#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:13.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:13.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:13.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:13.88#ibcon#enter wrdev, iclass 38, count 0 2006.202.01:41:13.88#ibcon#first serial, iclass 38, count 0 2006.202.01:41:13.88#ibcon#enter sib2, iclass 38, count 0 2006.202.01:41:13.88#ibcon#flushed, iclass 38, count 0 2006.202.01:41:13.88#ibcon#about to write, iclass 38, count 0 2006.202.01:41:13.88#ibcon#wrote, iclass 38, count 0 2006.202.01:41:13.88#ibcon#about to read 3, iclass 38, count 0 2006.202.01:41:13.90#ibcon#read 3, iclass 38, count 0 2006.202.01:41:13.90#ibcon#about to read 4, iclass 38, count 0 2006.202.01:41:13.90#ibcon#read 4, iclass 38, count 0 2006.202.01:41:13.90#ibcon#about to read 5, iclass 38, count 0 2006.202.01:41:13.90#ibcon#read 5, iclass 38, count 0 2006.202.01:41:13.90#ibcon#about to read 6, iclass 38, count 0 2006.202.01:41:13.90#ibcon#read 6, iclass 38, count 0 2006.202.01:41:13.90#ibcon#end of sib2, iclass 38, count 0 2006.202.01:41:13.90#ibcon#*mode == 0, iclass 38, count 0 2006.202.01:41:13.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.01:41:13.90#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.01:41:13.90#ibcon#*before write, iclass 38, count 0 2006.202.01:41:13.90#ibcon#enter sib2, iclass 38, count 0 2006.202.01:41:13.90#ibcon#flushed, iclass 38, count 0 2006.202.01:41:13.90#ibcon#about to write, iclass 38, count 0 2006.202.01:41:13.90#ibcon#wrote, iclass 38, count 0 2006.202.01:41:13.90#ibcon#about to read 3, iclass 38, count 0 2006.202.01:41:13.94#ibcon#read 3, iclass 38, count 0 2006.202.01:41:13.94#ibcon#about to read 4, iclass 38, count 0 2006.202.01:41:13.94#ibcon#read 4, iclass 38, count 0 2006.202.01:41:13.94#ibcon#about to read 5, iclass 38, count 0 2006.202.01:41:13.94#ibcon#read 5, iclass 38, count 0 2006.202.01:41:13.94#ibcon#about to read 6, iclass 38, count 0 2006.202.01:41:13.94#ibcon#read 6, iclass 38, count 0 2006.202.01:41:13.94#ibcon#end of sib2, iclass 38, count 0 2006.202.01:41:13.94#ibcon#*after write, iclass 38, count 0 2006.202.01:41:13.94#ibcon#*before return 0, iclass 38, count 0 2006.202.01:41:13.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:13.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:13.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.01:41:13.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.01:41:13.94$vck44/va=8,4 2006.202.01:41:13.94#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.202.01:41:13.94#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.202.01:41:13.94#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:13.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:14.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:14.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:14.00#ibcon#enter wrdev, iclass 40, count 2 2006.202.01:41:14.00#ibcon#first serial, iclass 40, count 2 2006.202.01:41:14.00#ibcon#enter sib2, iclass 40, count 2 2006.202.01:41:14.00#ibcon#flushed, iclass 40, count 2 2006.202.01:41:14.00#ibcon#about to write, iclass 40, count 2 2006.202.01:41:14.00#ibcon#wrote, iclass 40, count 2 2006.202.01:41:14.00#ibcon#about to read 3, iclass 40, count 2 2006.202.01:41:14.02#ibcon#read 3, iclass 40, count 2 2006.202.01:41:14.02#ibcon#about to read 4, iclass 40, count 2 2006.202.01:41:14.02#ibcon#read 4, iclass 40, count 2 2006.202.01:41:14.02#ibcon#about to read 5, iclass 40, count 2 2006.202.01:41:14.02#ibcon#read 5, iclass 40, count 2 2006.202.01:41:14.02#ibcon#about to read 6, iclass 40, count 2 2006.202.01:41:14.02#ibcon#read 6, iclass 40, count 2 2006.202.01:41:14.02#ibcon#end of sib2, iclass 40, count 2 2006.202.01:41:14.02#ibcon#*mode == 0, iclass 40, count 2 2006.202.01:41:14.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.202.01:41:14.02#ibcon#[25=AT08-04\r\n] 2006.202.01:41:14.02#ibcon#*before write, iclass 40, count 2 2006.202.01:41:14.02#ibcon#enter sib2, iclass 40, count 2 2006.202.01:41:14.02#ibcon#flushed, iclass 40, count 2 2006.202.01:41:14.02#ibcon#about to write, iclass 40, count 2 2006.202.01:41:14.02#ibcon#wrote, iclass 40, count 2 2006.202.01:41:14.02#ibcon#about to read 3, iclass 40, count 2 2006.202.01:41:14.05#ibcon#read 3, iclass 40, count 2 2006.202.01:41:14.05#ibcon#about to read 4, iclass 40, count 2 2006.202.01:41:14.05#ibcon#read 4, iclass 40, count 2 2006.202.01:41:14.05#ibcon#about to read 5, iclass 40, count 2 2006.202.01:41:14.05#ibcon#read 5, iclass 40, count 2 2006.202.01:41:14.05#ibcon#about to read 6, iclass 40, count 2 2006.202.01:41:14.05#ibcon#read 6, iclass 40, count 2 2006.202.01:41:14.05#ibcon#end of sib2, iclass 40, count 2 2006.202.01:41:14.05#ibcon#*after write, iclass 40, count 2 2006.202.01:41:14.05#ibcon#*before return 0, iclass 40, count 2 2006.202.01:41:14.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:14.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:14.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.202.01:41:14.05#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:14.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:14.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:14.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:14.17#ibcon#enter wrdev, iclass 40, count 0 2006.202.01:41:14.17#ibcon#first serial, iclass 40, count 0 2006.202.01:41:14.17#ibcon#enter sib2, iclass 40, count 0 2006.202.01:41:14.17#ibcon#flushed, iclass 40, count 0 2006.202.01:41:14.17#ibcon#about to write, iclass 40, count 0 2006.202.01:41:14.17#ibcon#wrote, iclass 40, count 0 2006.202.01:41:14.17#ibcon#about to read 3, iclass 40, count 0 2006.202.01:41:14.19#ibcon#read 3, iclass 40, count 0 2006.202.01:41:14.19#ibcon#about to read 4, iclass 40, count 0 2006.202.01:41:14.19#ibcon#read 4, iclass 40, count 0 2006.202.01:41:14.19#ibcon#about to read 5, iclass 40, count 0 2006.202.01:41:14.19#ibcon#read 5, iclass 40, count 0 2006.202.01:41:14.19#ibcon#about to read 6, iclass 40, count 0 2006.202.01:41:14.19#ibcon#read 6, iclass 40, count 0 2006.202.01:41:14.19#ibcon#end of sib2, iclass 40, count 0 2006.202.01:41:14.19#ibcon#*mode == 0, iclass 40, count 0 2006.202.01:41:14.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.01:41:14.19#ibcon#[25=USB\r\n] 2006.202.01:41:14.19#ibcon#*before write, iclass 40, count 0 2006.202.01:41:14.19#ibcon#enter sib2, iclass 40, count 0 2006.202.01:41:14.19#ibcon#flushed, iclass 40, count 0 2006.202.01:41:14.19#ibcon#about to write, iclass 40, count 0 2006.202.01:41:14.19#ibcon#wrote, iclass 40, count 0 2006.202.01:41:14.19#ibcon#about to read 3, iclass 40, count 0 2006.202.01:41:14.22#ibcon#read 3, iclass 40, count 0 2006.202.01:41:14.22#ibcon#about to read 4, iclass 40, count 0 2006.202.01:41:14.22#ibcon#read 4, iclass 40, count 0 2006.202.01:41:14.22#ibcon#about to read 5, iclass 40, count 0 2006.202.01:41:14.22#ibcon#read 5, iclass 40, count 0 2006.202.01:41:14.22#ibcon#about to read 6, iclass 40, count 0 2006.202.01:41:14.22#ibcon#read 6, iclass 40, count 0 2006.202.01:41:14.22#ibcon#end of sib2, iclass 40, count 0 2006.202.01:41:14.22#ibcon#*after write, iclass 40, count 0 2006.202.01:41:14.22#ibcon#*before return 0, iclass 40, count 0 2006.202.01:41:14.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:14.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:14.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.01:41:14.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.01:41:14.22$vck44/vblo=1,629.99 2006.202.01:41:14.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.01:41:14.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.01:41:14.22#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:14.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:14.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:14.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:14.22#ibcon#enter wrdev, iclass 4, count 0 2006.202.01:41:14.22#ibcon#first serial, iclass 4, count 0 2006.202.01:41:14.22#ibcon#enter sib2, iclass 4, count 0 2006.202.01:41:14.22#ibcon#flushed, iclass 4, count 0 2006.202.01:41:14.22#ibcon#about to write, iclass 4, count 0 2006.202.01:41:14.22#ibcon#wrote, iclass 4, count 0 2006.202.01:41:14.22#ibcon#about to read 3, iclass 4, count 0 2006.202.01:41:14.24#ibcon#read 3, iclass 4, count 0 2006.202.01:41:14.24#ibcon#about to read 4, iclass 4, count 0 2006.202.01:41:14.24#ibcon#read 4, iclass 4, count 0 2006.202.01:41:14.24#ibcon#about to read 5, iclass 4, count 0 2006.202.01:41:14.24#ibcon#read 5, iclass 4, count 0 2006.202.01:41:14.24#ibcon#about to read 6, iclass 4, count 0 2006.202.01:41:14.24#ibcon#read 6, iclass 4, count 0 2006.202.01:41:14.24#ibcon#end of sib2, iclass 4, count 0 2006.202.01:41:14.24#ibcon#*mode == 0, iclass 4, count 0 2006.202.01:41:14.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.01:41:14.24#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.01:41:14.24#ibcon#*before write, iclass 4, count 0 2006.202.01:41:14.24#ibcon#enter sib2, iclass 4, count 0 2006.202.01:41:14.24#ibcon#flushed, iclass 4, count 0 2006.202.01:41:14.24#ibcon#about to write, iclass 4, count 0 2006.202.01:41:14.24#ibcon#wrote, iclass 4, count 0 2006.202.01:41:14.24#ibcon#about to read 3, iclass 4, count 0 2006.202.01:41:14.28#ibcon#read 3, iclass 4, count 0 2006.202.01:41:14.28#ibcon#about to read 4, iclass 4, count 0 2006.202.01:41:14.28#ibcon#read 4, iclass 4, count 0 2006.202.01:41:14.28#ibcon#about to read 5, iclass 4, count 0 2006.202.01:41:14.28#ibcon#read 5, iclass 4, count 0 2006.202.01:41:14.28#ibcon#about to read 6, iclass 4, count 0 2006.202.01:41:14.28#ibcon#read 6, iclass 4, count 0 2006.202.01:41:14.28#ibcon#end of sib2, iclass 4, count 0 2006.202.01:41:14.28#ibcon#*after write, iclass 4, count 0 2006.202.01:41:14.28#ibcon#*before return 0, iclass 4, count 0 2006.202.01:41:14.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:14.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:14.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.01:41:14.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.01:41:14.28$vck44/vb=1,4 2006.202.01:41:14.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.202.01:41:14.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.202.01:41:14.28#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:14.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:41:14.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:41:14.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:41:14.28#ibcon#enter wrdev, iclass 6, count 2 2006.202.01:41:14.28#ibcon#first serial, iclass 6, count 2 2006.202.01:41:14.28#ibcon#enter sib2, iclass 6, count 2 2006.202.01:41:14.28#ibcon#flushed, iclass 6, count 2 2006.202.01:41:14.28#ibcon#about to write, iclass 6, count 2 2006.202.01:41:14.28#ibcon#wrote, iclass 6, count 2 2006.202.01:41:14.28#ibcon#about to read 3, iclass 6, count 2 2006.202.01:41:14.30#ibcon#read 3, iclass 6, count 2 2006.202.01:41:14.30#ibcon#about to read 4, iclass 6, count 2 2006.202.01:41:14.30#ibcon#read 4, iclass 6, count 2 2006.202.01:41:14.30#ibcon#about to read 5, iclass 6, count 2 2006.202.01:41:14.30#ibcon#read 5, iclass 6, count 2 2006.202.01:41:14.30#ibcon#about to read 6, iclass 6, count 2 2006.202.01:41:14.30#ibcon#read 6, iclass 6, count 2 2006.202.01:41:14.30#ibcon#end of sib2, iclass 6, count 2 2006.202.01:41:14.30#ibcon#*mode == 0, iclass 6, count 2 2006.202.01:41:14.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.202.01:41:14.30#ibcon#[27=AT01-04\r\n] 2006.202.01:41:14.30#ibcon#*before write, iclass 6, count 2 2006.202.01:41:14.30#ibcon#enter sib2, iclass 6, count 2 2006.202.01:41:14.30#ibcon#flushed, iclass 6, count 2 2006.202.01:41:14.30#ibcon#about to write, iclass 6, count 2 2006.202.01:41:14.30#ibcon#wrote, iclass 6, count 2 2006.202.01:41:14.30#ibcon#about to read 3, iclass 6, count 2 2006.202.01:41:14.33#ibcon#read 3, iclass 6, count 2 2006.202.01:41:14.33#ibcon#about to read 4, iclass 6, count 2 2006.202.01:41:14.33#ibcon#read 4, iclass 6, count 2 2006.202.01:41:14.33#ibcon#about to read 5, iclass 6, count 2 2006.202.01:41:14.33#ibcon#read 5, iclass 6, count 2 2006.202.01:41:14.33#ibcon#about to read 6, iclass 6, count 2 2006.202.01:41:14.33#ibcon#read 6, iclass 6, count 2 2006.202.01:41:14.33#ibcon#end of sib2, iclass 6, count 2 2006.202.01:41:14.33#ibcon#*after write, iclass 6, count 2 2006.202.01:41:14.33#ibcon#*before return 0, iclass 6, count 2 2006.202.01:41:14.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:41:14.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.202.01:41:14.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.202.01:41:14.33#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:14.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:41:14.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:41:14.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:41:14.45#ibcon#enter wrdev, iclass 6, count 0 2006.202.01:41:14.45#ibcon#first serial, iclass 6, count 0 2006.202.01:41:14.45#ibcon#enter sib2, iclass 6, count 0 2006.202.01:41:14.45#ibcon#flushed, iclass 6, count 0 2006.202.01:41:14.45#ibcon#about to write, iclass 6, count 0 2006.202.01:41:14.45#ibcon#wrote, iclass 6, count 0 2006.202.01:41:14.45#ibcon#about to read 3, iclass 6, count 0 2006.202.01:41:14.47#ibcon#read 3, iclass 6, count 0 2006.202.01:41:14.47#ibcon#about to read 4, iclass 6, count 0 2006.202.01:41:14.47#ibcon#read 4, iclass 6, count 0 2006.202.01:41:14.47#ibcon#about to read 5, iclass 6, count 0 2006.202.01:41:14.47#ibcon#read 5, iclass 6, count 0 2006.202.01:41:14.47#ibcon#about to read 6, iclass 6, count 0 2006.202.01:41:14.47#ibcon#read 6, iclass 6, count 0 2006.202.01:41:14.47#ibcon#end of sib2, iclass 6, count 0 2006.202.01:41:14.47#ibcon#*mode == 0, iclass 6, count 0 2006.202.01:41:14.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.01:41:14.47#ibcon#[27=USB\r\n] 2006.202.01:41:14.47#ibcon#*before write, iclass 6, count 0 2006.202.01:41:14.47#ibcon#enter sib2, iclass 6, count 0 2006.202.01:41:14.47#ibcon#flushed, iclass 6, count 0 2006.202.01:41:14.47#ibcon#about to write, iclass 6, count 0 2006.202.01:41:14.47#ibcon#wrote, iclass 6, count 0 2006.202.01:41:14.47#ibcon#about to read 3, iclass 6, count 0 2006.202.01:41:14.48#abcon#<5=/04 1.7 3.2 20.571001000.8\r\n> 2006.202.01:41:14.50#abcon#{5=INTERFACE CLEAR} 2006.202.01:41:14.50#ibcon#read 3, iclass 6, count 0 2006.202.01:41:14.50#ibcon#about to read 4, iclass 6, count 0 2006.202.01:41:14.50#ibcon#read 4, iclass 6, count 0 2006.202.01:41:14.50#ibcon#about to read 5, iclass 6, count 0 2006.202.01:41:14.50#ibcon#read 5, iclass 6, count 0 2006.202.01:41:14.50#ibcon#about to read 6, iclass 6, count 0 2006.202.01:41:14.50#ibcon#read 6, iclass 6, count 0 2006.202.01:41:14.50#ibcon#end of sib2, iclass 6, count 0 2006.202.01:41:14.50#ibcon#*after write, iclass 6, count 0 2006.202.01:41:14.50#ibcon#*before return 0, iclass 6, count 0 2006.202.01:41:14.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:41:14.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.202.01:41:14.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.01:41:14.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.01:41:14.50$vck44/vblo=2,634.99 2006.202.01:41:14.50#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.202.01:41:14.50#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.202.01:41:14.50#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:14.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:41:14.50#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:41:14.50#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:41:14.50#ibcon#enter wrdev, iclass 13, count 0 2006.202.01:41:14.50#ibcon#first serial, iclass 13, count 0 2006.202.01:41:14.50#ibcon#enter sib2, iclass 13, count 0 2006.202.01:41:14.50#ibcon#flushed, iclass 13, count 0 2006.202.01:41:14.50#ibcon#about to write, iclass 13, count 0 2006.202.01:41:14.50#ibcon#wrote, iclass 13, count 0 2006.202.01:41:14.50#ibcon#about to read 3, iclass 13, count 0 2006.202.01:41:14.52#ibcon#read 3, iclass 13, count 0 2006.202.01:41:14.52#ibcon#about to read 4, iclass 13, count 0 2006.202.01:41:14.52#ibcon#read 4, iclass 13, count 0 2006.202.01:41:14.52#ibcon#about to read 5, iclass 13, count 0 2006.202.01:41:14.52#ibcon#read 5, iclass 13, count 0 2006.202.01:41:14.52#ibcon#about to read 6, iclass 13, count 0 2006.202.01:41:14.52#ibcon#read 6, iclass 13, count 0 2006.202.01:41:14.52#ibcon#end of sib2, iclass 13, count 0 2006.202.01:41:14.52#ibcon#*mode == 0, iclass 13, count 0 2006.202.01:41:14.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.01:41:14.52#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.01:41:14.52#ibcon#*before write, iclass 13, count 0 2006.202.01:41:14.52#ibcon#enter sib2, iclass 13, count 0 2006.202.01:41:14.52#ibcon#flushed, iclass 13, count 0 2006.202.01:41:14.52#ibcon#about to write, iclass 13, count 0 2006.202.01:41:14.52#ibcon#wrote, iclass 13, count 0 2006.202.01:41:14.52#ibcon#about to read 3, iclass 13, count 0 2006.202.01:41:14.56#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:41:14.56#ibcon#read 3, iclass 13, count 0 2006.202.01:41:14.56#ibcon#about to read 4, iclass 13, count 0 2006.202.01:41:14.56#ibcon#read 4, iclass 13, count 0 2006.202.01:41:14.56#ibcon#about to read 5, iclass 13, count 0 2006.202.01:41:14.56#ibcon#read 5, iclass 13, count 0 2006.202.01:41:14.56#ibcon#about to read 6, iclass 13, count 0 2006.202.01:41:14.56#ibcon#read 6, iclass 13, count 0 2006.202.01:41:14.56#ibcon#end of sib2, iclass 13, count 0 2006.202.01:41:14.56#ibcon#*after write, iclass 13, count 0 2006.202.01:41:14.56#ibcon#*before return 0, iclass 13, count 0 2006.202.01:41:14.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:41:14.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:41:14.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.01:41:14.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.01:41:14.56$vck44/vb=2,5 2006.202.01:41:14.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.202.01:41:14.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.202.01:41:14.56#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:14.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:14.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:14.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:14.62#ibcon#enter wrdev, iclass 16, count 2 2006.202.01:41:14.62#ibcon#first serial, iclass 16, count 2 2006.202.01:41:14.62#ibcon#enter sib2, iclass 16, count 2 2006.202.01:41:14.62#ibcon#flushed, iclass 16, count 2 2006.202.01:41:14.62#ibcon#about to write, iclass 16, count 2 2006.202.01:41:14.62#ibcon#wrote, iclass 16, count 2 2006.202.01:41:14.62#ibcon#about to read 3, iclass 16, count 2 2006.202.01:41:14.64#ibcon#read 3, iclass 16, count 2 2006.202.01:41:14.64#ibcon#about to read 4, iclass 16, count 2 2006.202.01:41:14.64#ibcon#read 4, iclass 16, count 2 2006.202.01:41:14.64#ibcon#about to read 5, iclass 16, count 2 2006.202.01:41:14.64#ibcon#read 5, iclass 16, count 2 2006.202.01:41:14.64#ibcon#about to read 6, iclass 16, count 2 2006.202.01:41:14.64#ibcon#read 6, iclass 16, count 2 2006.202.01:41:14.64#ibcon#end of sib2, iclass 16, count 2 2006.202.01:41:14.64#ibcon#*mode == 0, iclass 16, count 2 2006.202.01:41:14.64#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.202.01:41:14.64#ibcon#[27=AT02-05\r\n] 2006.202.01:41:14.64#ibcon#*before write, iclass 16, count 2 2006.202.01:41:14.64#ibcon#enter sib2, iclass 16, count 2 2006.202.01:41:14.64#ibcon#flushed, iclass 16, count 2 2006.202.01:41:14.64#ibcon#about to write, iclass 16, count 2 2006.202.01:41:14.76#ibcon#wrote, iclass 16, count 2 2006.202.01:41:14.76#ibcon#about to read 3, iclass 16, count 2 2006.202.01:41:14.79#ibcon#read 3, iclass 16, count 2 2006.202.01:41:14.79#ibcon#about to read 4, iclass 16, count 2 2006.202.01:41:14.79#ibcon#read 4, iclass 16, count 2 2006.202.01:41:14.79#ibcon#about to read 5, iclass 16, count 2 2006.202.01:41:14.79#ibcon#read 5, iclass 16, count 2 2006.202.01:41:14.79#ibcon#about to read 6, iclass 16, count 2 2006.202.01:41:14.79#ibcon#read 6, iclass 16, count 2 2006.202.01:41:14.79#ibcon#end of sib2, iclass 16, count 2 2006.202.01:41:14.79#ibcon#*after write, iclass 16, count 2 2006.202.01:41:14.79#ibcon#*before return 0, iclass 16, count 2 2006.202.01:41:14.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:14.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.202.01:41:14.79#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.202.01:41:14.79#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:14.79#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:14.91#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:14.91#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:14.91#ibcon#enter wrdev, iclass 16, count 0 2006.202.01:41:14.91#ibcon#first serial, iclass 16, count 0 2006.202.01:41:14.91#ibcon#enter sib2, iclass 16, count 0 2006.202.01:41:14.91#ibcon#flushed, iclass 16, count 0 2006.202.01:41:14.91#ibcon#about to write, iclass 16, count 0 2006.202.01:41:14.91#ibcon#wrote, iclass 16, count 0 2006.202.01:41:14.91#ibcon#about to read 3, iclass 16, count 0 2006.202.01:41:14.93#ibcon#read 3, iclass 16, count 0 2006.202.01:41:14.93#ibcon#about to read 4, iclass 16, count 0 2006.202.01:41:14.93#ibcon#read 4, iclass 16, count 0 2006.202.01:41:14.93#ibcon#about to read 5, iclass 16, count 0 2006.202.01:41:14.93#ibcon#read 5, iclass 16, count 0 2006.202.01:41:14.93#ibcon#about to read 6, iclass 16, count 0 2006.202.01:41:14.93#ibcon#read 6, iclass 16, count 0 2006.202.01:41:14.93#ibcon#end of sib2, iclass 16, count 0 2006.202.01:41:14.93#ibcon#*mode == 0, iclass 16, count 0 2006.202.01:41:14.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.01:41:14.93#ibcon#[27=USB\r\n] 2006.202.01:41:14.93#ibcon#*before write, iclass 16, count 0 2006.202.01:41:14.93#ibcon#enter sib2, iclass 16, count 0 2006.202.01:41:14.93#ibcon#flushed, iclass 16, count 0 2006.202.01:41:14.93#ibcon#about to write, iclass 16, count 0 2006.202.01:41:14.93#ibcon#wrote, iclass 16, count 0 2006.202.01:41:14.93#ibcon#about to read 3, iclass 16, count 0 2006.202.01:41:14.96#ibcon#read 3, iclass 16, count 0 2006.202.01:41:14.96#ibcon#about to read 4, iclass 16, count 0 2006.202.01:41:14.96#ibcon#read 4, iclass 16, count 0 2006.202.01:41:14.96#ibcon#about to read 5, iclass 16, count 0 2006.202.01:41:14.96#ibcon#read 5, iclass 16, count 0 2006.202.01:41:14.96#ibcon#about to read 6, iclass 16, count 0 2006.202.01:41:14.96#ibcon#read 6, iclass 16, count 0 2006.202.01:41:14.96#ibcon#end of sib2, iclass 16, count 0 2006.202.01:41:14.96#ibcon#*after write, iclass 16, count 0 2006.202.01:41:14.96#ibcon#*before return 0, iclass 16, count 0 2006.202.01:41:14.96#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:14.96#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.202.01:41:14.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.01:41:14.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.01:41:14.96$vck44/vblo=3,649.99 2006.202.01:41:14.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.202.01:41:14.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.202.01:41:14.96#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:14.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:14.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:14.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:14.96#ibcon#enter wrdev, iclass 18, count 0 2006.202.01:41:14.96#ibcon#first serial, iclass 18, count 0 2006.202.01:41:14.96#ibcon#enter sib2, iclass 18, count 0 2006.202.01:41:14.96#ibcon#flushed, iclass 18, count 0 2006.202.01:41:14.96#ibcon#about to write, iclass 18, count 0 2006.202.01:41:14.96#ibcon#wrote, iclass 18, count 0 2006.202.01:41:14.96#ibcon#about to read 3, iclass 18, count 0 2006.202.01:41:14.98#ibcon#read 3, iclass 18, count 0 2006.202.01:41:14.98#ibcon#about to read 4, iclass 18, count 0 2006.202.01:41:14.98#ibcon#read 4, iclass 18, count 0 2006.202.01:41:14.98#ibcon#about to read 5, iclass 18, count 0 2006.202.01:41:14.98#ibcon#read 5, iclass 18, count 0 2006.202.01:41:14.98#ibcon#about to read 6, iclass 18, count 0 2006.202.01:41:14.98#ibcon#read 6, iclass 18, count 0 2006.202.01:41:14.98#ibcon#end of sib2, iclass 18, count 0 2006.202.01:41:14.98#ibcon#*mode == 0, iclass 18, count 0 2006.202.01:41:14.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.01:41:14.98#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.01:41:14.98#ibcon#*before write, iclass 18, count 0 2006.202.01:41:14.98#ibcon#enter sib2, iclass 18, count 0 2006.202.01:41:14.98#ibcon#flushed, iclass 18, count 0 2006.202.01:41:14.98#ibcon#about to write, iclass 18, count 0 2006.202.01:41:14.98#ibcon#wrote, iclass 18, count 0 2006.202.01:41:14.98#ibcon#about to read 3, iclass 18, count 0 2006.202.01:41:15.02#ibcon#read 3, iclass 18, count 0 2006.202.01:41:15.02#ibcon#about to read 4, iclass 18, count 0 2006.202.01:41:15.02#ibcon#read 4, iclass 18, count 0 2006.202.01:41:15.02#ibcon#about to read 5, iclass 18, count 0 2006.202.01:41:15.02#ibcon#read 5, iclass 18, count 0 2006.202.01:41:15.02#ibcon#about to read 6, iclass 18, count 0 2006.202.01:41:15.02#ibcon#read 6, iclass 18, count 0 2006.202.01:41:15.02#ibcon#end of sib2, iclass 18, count 0 2006.202.01:41:15.02#ibcon#*after write, iclass 18, count 0 2006.202.01:41:15.02#ibcon#*before return 0, iclass 18, count 0 2006.202.01:41:15.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:15.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.202.01:41:15.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.01:41:15.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.01:41:15.02$vck44/vb=3,4 2006.202.01:41:15.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.202.01:41:15.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.202.01:41:15.02#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:15.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:15.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:15.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:15.08#ibcon#enter wrdev, iclass 20, count 2 2006.202.01:41:15.08#ibcon#first serial, iclass 20, count 2 2006.202.01:41:15.08#ibcon#enter sib2, iclass 20, count 2 2006.202.01:41:15.08#ibcon#flushed, iclass 20, count 2 2006.202.01:41:15.08#ibcon#about to write, iclass 20, count 2 2006.202.01:41:15.08#ibcon#wrote, iclass 20, count 2 2006.202.01:41:15.08#ibcon#about to read 3, iclass 20, count 2 2006.202.01:41:15.10#ibcon#read 3, iclass 20, count 2 2006.202.01:41:15.10#ibcon#about to read 4, iclass 20, count 2 2006.202.01:41:15.10#ibcon#read 4, iclass 20, count 2 2006.202.01:41:15.10#ibcon#about to read 5, iclass 20, count 2 2006.202.01:41:15.10#ibcon#read 5, iclass 20, count 2 2006.202.01:41:15.10#ibcon#about to read 6, iclass 20, count 2 2006.202.01:41:15.10#ibcon#read 6, iclass 20, count 2 2006.202.01:41:15.10#ibcon#end of sib2, iclass 20, count 2 2006.202.01:41:15.10#ibcon#*mode == 0, iclass 20, count 2 2006.202.01:41:15.10#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.202.01:41:15.10#ibcon#[27=AT03-04\r\n] 2006.202.01:41:15.10#ibcon#*before write, iclass 20, count 2 2006.202.01:41:15.10#ibcon#enter sib2, iclass 20, count 2 2006.202.01:41:15.10#ibcon#flushed, iclass 20, count 2 2006.202.01:41:15.10#ibcon#about to write, iclass 20, count 2 2006.202.01:41:15.10#ibcon#wrote, iclass 20, count 2 2006.202.01:41:15.10#ibcon#about to read 3, iclass 20, count 2 2006.202.01:41:15.13#ibcon#read 3, iclass 20, count 2 2006.202.01:41:15.13#ibcon#about to read 4, iclass 20, count 2 2006.202.01:41:15.13#ibcon#read 4, iclass 20, count 2 2006.202.01:41:15.13#ibcon#about to read 5, iclass 20, count 2 2006.202.01:41:15.13#ibcon#read 5, iclass 20, count 2 2006.202.01:41:15.13#ibcon#about to read 6, iclass 20, count 2 2006.202.01:41:15.13#ibcon#read 6, iclass 20, count 2 2006.202.01:41:15.13#ibcon#end of sib2, iclass 20, count 2 2006.202.01:41:15.13#ibcon#*after write, iclass 20, count 2 2006.202.01:41:15.13#ibcon#*before return 0, iclass 20, count 2 2006.202.01:41:15.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:15.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.202.01:41:15.13#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.202.01:41:15.13#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:15.13#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:15.25#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:15.25#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:15.25#ibcon#enter wrdev, iclass 20, count 0 2006.202.01:41:15.25#ibcon#first serial, iclass 20, count 0 2006.202.01:41:15.25#ibcon#enter sib2, iclass 20, count 0 2006.202.01:41:15.25#ibcon#flushed, iclass 20, count 0 2006.202.01:41:15.25#ibcon#about to write, iclass 20, count 0 2006.202.01:41:15.25#ibcon#wrote, iclass 20, count 0 2006.202.01:41:15.25#ibcon#about to read 3, iclass 20, count 0 2006.202.01:41:15.27#ibcon#read 3, iclass 20, count 0 2006.202.01:41:15.27#ibcon#about to read 4, iclass 20, count 0 2006.202.01:41:15.27#ibcon#read 4, iclass 20, count 0 2006.202.01:41:15.27#ibcon#about to read 5, iclass 20, count 0 2006.202.01:41:15.27#ibcon#read 5, iclass 20, count 0 2006.202.01:41:15.27#ibcon#about to read 6, iclass 20, count 0 2006.202.01:41:15.27#ibcon#read 6, iclass 20, count 0 2006.202.01:41:15.27#ibcon#end of sib2, iclass 20, count 0 2006.202.01:41:15.27#ibcon#*mode == 0, iclass 20, count 0 2006.202.01:41:15.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.01:41:15.27#ibcon#[27=USB\r\n] 2006.202.01:41:15.27#ibcon#*before write, iclass 20, count 0 2006.202.01:41:15.27#ibcon#enter sib2, iclass 20, count 0 2006.202.01:41:15.27#ibcon#flushed, iclass 20, count 0 2006.202.01:41:15.27#ibcon#about to write, iclass 20, count 0 2006.202.01:41:15.27#ibcon#wrote, iclass 20, count 0 2006.202.01:41:15.27#ibcon#about to read 3, iclass 20, count 0 2006.202.01:41:15.30#ibcon#read 3, iclass 20, count 0 2006.202.01:41:15.30#ibcon#about to read 4, iclass 20, count 0 2006.202.01:41:15.30#ibcon#read 4, iclass 20, count 0 2006.202.01:41:15.30#ibcon#about to read 5, iclass 20, count 0 2006.202.01:41:15.30#ibcon#read 5, iclass 20, count 0 2006.202.01:41:15.30#ibcon#about to read 6, iclass 20, count 0 2006.202.01:41:15.30#ibcon#read 6, iclass 20, count 0 2006.202.01:41:15.30#ibcon#end of sib2, iclass 20, count 0 2006.202.01:41:15.30#ibcon#*after write, iclass 20, count 0 2006.202.01:41:15.30#ibcon#*before return 0, iclass 20, count 0 2006.202.01:41:15.30#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:15.30#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.202.01:41:15.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.01:41:15.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.01:41:15.30$vck44/vblo=4,679.99 2006.202.01:41:15.30#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.202.01:41:15.30#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.202.01:41:15.30#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:15.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:15.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:15.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:15.30#ibcon#enter wrdev, iclass 22, count 0 2006.202.01:41:15.30#ibcon#first serial, iclass 22, count 0 2006.202.01:41:15.30#ibcon#enter sib2, iclass 22, count 0 2006.202.01:41:15.30#ibcon#flushed, iclass 22, count 0 2006.202.01:41:15.30#ibcon#about to write, iclass 22, count 0 2006.202.01:41:15.30#ibcon#wrote, iclass 22, count 0 2006.202.01:41:15.30#ibcon#about to read 3, iclass 22, count 0 2006.202.01:41:15.32#ibcon#read 3, iclass 22, count 0 2006.202.01:41:15.32#ibcon#about to read 4, iclass 22, count 0 2006.202.01:41:15.32#ibcon#read 4, iclass 22, count 0 2006.202.01:41:15.32#ibcon#about to read 5, iclass 22, count 0 2006.202.01:41:15.32#ibcon#read 5, iclass 22, count 0 2006.202.01:41:15.32#ibcon#about to read 6, iclass 22, count 0 2006.202.01:41:15.32#ibcon#read 6, iclass 22, count 0 2006.202.01:41:15.32#ibcon#end of sib2, iclass 22, count 0 2006.202.01:41:15.32#ibcon#*mode == 0, iclass 22, count 0 2006.202.01:41:15.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.01:41:15.32#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.01:41:15.32#ibcon#*before write, iclass 22, count 0 2006.202.01:41:15.32#ibcon#enter sib2, iclass 22, count 0 2006.202.01:41:15.32#ibcon#flushed, iclass 22, count 0 2006.202.01:41:15.32#ibcon#about to write, iclass 22, count 0 2006.202.01:41:15.32#ibcon#wrote, iclass 22, count 0 2006.202.01:41:15.32#ibcon#about to read 3, iclass 22, count 0 2006.202.01:41:15.36#ibcon#read 3, iclass 22, count 0 2006.202.01:41:15.36#ibcon#about to read 4, iclass 22, count 0 2006.202.01:41:15.36#ibcon#read 4, iclass 22, count 0 2006.202.01:41:15.36#ibcon#about to read 5, iclass 22, count 0 2006.202.01:41:15.36#ibcon#read 5, iclass 22, count 0 2006.202.01:41:15.36#ibcon#about to read 6, iclass 22, count 0 2006.202.01:41:15.36#ibcon#read 6, iclass 22, count 0 2006.202.01:41:15.36#ibcon#end of sib2, iclass 22, count 0 2006.202.01:41:15.36#ibcon#*after write, iclass 22, count 0 2006.202.01:41:15.36#ibcon#*before return 0, iclass 22, count 0 2006.202.01:41:15.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:15.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.202.01:41:15.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.01:41:15.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.01:41:15.36$vck44/vb=4,5 2006.202.01:41:15.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.202.01:41:15.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.202.01:41:15.36#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:15.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:15.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:15.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:15.42#ibcon#enter wrdev, iclass 24, count 2 2006.202.01:41:15.42#ibcon#first serial, iclass 24, count 2 2006.202.01:41:15.42#ibcon#enter sib2, iclass 24, count 2 2006.202.01:41:15.42#ibcon#flushed, iclass 24, count 2 2006.202.01:41:15.42#ibcon#about to write, iclass 24, count 2 2006.202.01:41:15.42#ibcon#wrote, iclass 24, count 2 2006.202.01:41:15.42#ibcon#about to read 3, iclass 24, count 2 2006.202.01:41:15.44#ibcon#read 3, iclass 24, count 2 2006.202.01:41:15.44#ibcon#about to read 4, iclass 24, count 2 2006.202.01:41:15.44#ibcon#read 4, iclass 24, count 2 2006.202.01:41:15.44#ibcon#about to read 5, iclass 24, count 2 2006.202.01:41:15.44#ibcon#read 5, iclass 24, count 2 2006.202.01:41:15.44#ibcon#about to read 6, iclass 24, count 2 2006.202.01:41:15.44#ibcon#read 6, iclass 24, count 2 2006.202.01:41:15.44#ibcon#end of sib2, iclass 24, count 2 2006.202.01:41:15.44#ibcon#*mode == 0, iclass 24, count 2 2006.202.01:41:15.44#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.202.01:41:15.44#ibcon#[27=AT04-05\r\n] 2006.202.01:41:15.44#ibcon#*before write, iclass 24, count 2 2006.202.01:41:15.44#ibcon#enter sib2, iclass 24, count 2 2006.202.01:41:15.44#ibcon#flushed, iclass 24, count 2 2006.202.01:41:15.44#ibcon#about to write, iclass 24, count 2 2006.202.01:41:15.44#ibcon#wrote, iclass 24, count 2 2006.202.01:41:15.44#ibcon#about to read 3, iclass 24, count 2 2006.202.01:41:15.47#ibcon#read 3, iclass 24, count 2 2006.202.01:41:15.47#ibcon#about to read 4, iclass 24, count 2 2006.202.01:41:15.47#ibcon#read 4, iclass 24, count 2 2006.202.01:41:15.47#ibcon#about to read 5, iclass 24, count 2 2006.202.01:41:15.47#ibcon#read 5, iclass 24, count 2 2006.202.01:41:15.47#ibcon#about to read 6, iclass 24, count 2 2006.202.01:41:15.47#ibcon#read 6, iclass 24, count 2 2006.202.01:41:15.47#ibcon#end of sib2, iclass 24, count 2 2006.202.01:41:15.47#ibcon#*after write, iclass 24, count 2 2006.202.01:41:15.47#ibcon#*before return 0, iclass 24, count 2 2006.202.01:41:15.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:15.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.202.01:41:15.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.202.01:41:15.47#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:15.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:15.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:15.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:15.59#ibcon#enter wrdev, iclass 24, count 0 2006.202.01:41:15.59#ibcon#first serial, iclass 24, count 0 2006.202.01:41:15.59#ibcon#enter sib2, iclass 24, count 0 2006.202.01:41:15.59#ibcon#flushed, iclass 24, count 0 2006.202.01:41:15.59#ibcon#about to write, iclass 24, count 0 2006.202.01:41:15.59#ibcon#wrote, iclass 24, count 0 2006.202.01:41:15.59#ibcon#about to read 3, iclass 24, count 0 2006.202.01:41:15.61#ibcon#read 3, iclass 24, count 0 2006.202.01:41:15.61#ibcon#about to read 4, iclass 24, count 0 2006.202.01:41:15.61#ibcon#read 4, iclass 24, count 0 2006.202.01:41:15.61#ibcon#about to read 5, iclass 24, count 0 2006.202.01:41:15.61#ibcon#read 5, iclass 24, count 0 2006.202.01:41:15.61#ibcon#about to read 6, iclass 24, count 0 2006.202.01:41:15.61#ibcon#read 6, iclass 24, count 0 2006.202.01:41:15.61#ibcon#end of sib2, iclass 24, count 0 2006.202.01:41:15.61#ibcon#*mode == 0, iclass 24, count 0 2006.202.01:41:15.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.01:41:15.61#ibcon#[27=USB\r\n] 2006.202.01:41:15.61#ibcon#*before write, iclass 24, count 0 2006.202.01:41:15.61#ibcon#enter sib2, iclass 24, count 0 2006.202.01:41:15.61#ibcon#flushed, iclass 24, count 0 2006.202.01:41:15.61#ibcon#about to write, iclass 24, count 0 2006.202.01:41:15.61#ibcon#wrote, iclass 24, count 0 2006.202.01:41:15.61#ibcon#about to read 3, iclass 24, count 0 2006.202.01:41:15.64#ibcon#read 3, iclass 24, count 0 2006.202.01:41:15.64#ibcon#about to read 4, iclass 24, count 0 2006.202.01:41:15.64#ibcon#read 4, iclass 24, count 0 2006.202.01:41:15.64#ibcon#about to read 5, iclass 24, count 0 2006.202.01:41:15.64#ibcon#read 5, iclass 24, count 0 2006.202.01:41:15.64#ibcon#about to read 6, iclass 24, count 0 2006.202.01:41:15.64#ibcon#read 6, iclass 24, count 0 2006.202.01:41:15.64#ibcon#end of sib2, iclass 24, count 0 2006.202.01:41:15.64#ibcon#*after write, iclass 24, count 0 2006.202.01:41:15.64#ibcon#*before return 0, iclass 24, count 0 2006.202.01:41:15.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:15.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.202.01:41:15.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.01:41:15.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.01:41:15.64$vck44/vblo=5,709.99 2006.202.01:41:15.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.202.01:41:15.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.202.01:41:15.64#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:15.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:15.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:15.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:15.64#ibcon#enter wrdev, iclass 26, count 0 2006.202.01:41:15.64#ibcon#first serial, iclass 26, count 0 2006.202.01:41:15.64#ibcon#enter sib2, iclass 26, count 0 2006.202.01:41:15.64#ibcon#flushed, iclass 26, count 0 2006.202.01:41:15.64#ibcon#about to write, iclass 26, count 0 2006.202.01:41:15.64#ibcon#wrote, iclass 26, count 0 2006.202.01:41:15.64#ibcon#about to read 3, iclass 26, count 0 2006.202.01:41:15.66#ibcon#read 3, iclass 26, count 0 2006.202.01:41:15.66#ibcon#about to read 4, iclass 26, count 0 2006.202.01:41:15.66#ibcon#read 4, iclass 26, count 0 2006.202.01:41:15.66#ibcon#about to read 5, iclass 26, count 0 2006.202.01:41:15.66#ibcon#read 5, iclass 26, count 0 2006.202.01:41:15.66#ibcon#about to read 6, iclass 26, count 0 2006.202.01:41:15.66#ibcon#read 6, iclass 26, count 0 2006.202.01:41:15.66#ibcon#end of sib2, iclass 26, count 0 2006.202.01:41:15.66#ibcon#*mode == 0, iclass 26, count 0 2006.202.01:41:15.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.01:41:15.66#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.01:41:15.66#ibcon#*before write, iclass 26, count 0 2006.202.01:41:15.66#ibcon#enter sib2, iclass 26, count 0 2006.202.01:41:15.66#ibcon#flushed, iclass 26, count 0 2006.202.01:41:15.66#ibcon#about to write, iclass 26, count 0 2006.202.01:41:15.66#ibcon#wrote, iclass 26, count 0 2006.202.01:41:15.66#ibcon#about to read 3, iclass 26, count 0 2006.202.01:41:15.70#ibcon#read 3, iclass 26, count 0 2006.202.01:41:15.70#ibcon#about to read 4, iclass 26, count 0 2006.202.01:41:15.70#ibcon#read 4, iclass 26, count 0 2006.202.01:41:15.70#ibcon#about to read 5, iclass 26, count 0 2006.202.01:41:15.70#ibcon#read 5, iclass 26, count 0 2006.202.01:41:15.70#ibcon#about to read 6, iclass 26, count 0 2006.202.01:41:15.70#ibcon#read 6, iclass 26, count 0 2006.202.01:41:15.70#ibcon#end of sib2, iclass 26, count 0 2006.202.01:41:15.70#ibcon#*after write, iclass 26, count 0 2006.202.01:41:15.70#ibcon#*before return 0, iclass 26, count 0 2006.202.01:41:15.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:15.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.202.01:41:15.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.01:41:15.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.01:41:15.70$vck44/vb=5,4 2006.202.01:41:15.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.202.01:41:15.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.202.01:41:15.70#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:15.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:15.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:15.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:15.76#ibcon#enter wrdev, iclass 28, count 2 2006.202.01:41:15.76#ibcon#first serial, iclass 28, count 2 2006.202.01:41:15.76#ibcon#enter sib2, iclass 28, count 2 2006.202.01:41:15.76#ibcon#flushed, iclass 28, count 2 2006.202.01:41:15.76#ibcon#about to write, iclass 28, count 2 2006.202.01:41:15.76#ibcon#wrote, iclass 28, count 2 2006.202.01:41:15.76#ibcon#about to read 3, iclass 28, count 2 2006.202.01:41:15.78#ibcon#read 3, iclass 28, count 2 2006.202.01:41:15.78#ibcon#about to read 4, iclass 28, count 2 2006.202.01:41:15.78#ibcon#read 4, iclass 28, count 2 2006.202.01:41:15.78#ibcon#about to read 5, iclass 28, count 2 2006.202.01:41:15.78#ibcon#read 5, iclass 28, count 2 2006.202.01:41:15.78#ibcon#about to read 6, iclass 28, count 2 2006.202.01:41:15.78#ibcon#read 6, iclass 28, count 2 2006.202.01:41:15.78#ibcon#end of sib2, iclass 28, count 2 2006.202.01:41:15.78#ibcon#*mode == 0, iclass 28, count 2 2006.202.01:41:15.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.202.01:41:15.78#ibcon#[27=AT05-04\r\n] 2006.202.01:41:15.78#ibcon#*before write, iclass 28, count 2 2006.202.01:41:15.78#ibcon#enter sib2, iclass 28, count 2 2006.202.01:41:15.78#ibcon#flushed, iclass 28, count 2 2006.202.01:41:15.78#ibcon#about to write, iclass 28, count 2 2006.202.01:41:15.78#ibcon#wrote, iclass 28, count 2 2006.202.01:41:15.78#ibcon#about to read 3, iclass 28, count 2 2006.202.01:41:15.81#ibcon#read 3, iclass 28, count 2 2006.202.01:41:15.86#ibcon#about to read 4, iclass 28, count 2 2006.202.01:41:15.86#ibcon#read 4, iclass 28, count 2 2006.202.01:41:15.86#ibcon#about to read 5, iclass 28, count 2 2006.202.01:41:15.86#ibcon#read 5, iclass 28, count 2 2006.202.01:41:15.86#ibcon#about to read 6, iclass 28, count 2 2006.202.01:41:15.86#ibcon#read 6, iclass 28, count 2 2006.202.01:41:15.86#ibcon#end of sib2, iclass 28, count 2 2006.202.01:41:15.86#ibcon#*after write, iclass 28, count 2 2006.202.01:41:15.86#ibcon#*before return 0, iclass 28, count 2 2006.202.01:41:15.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:15.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.202.01:41:15.86#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.202.01:41:15.86#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:15.86#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:15.98#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:15.98#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:15.98#ibcon#enter wrdev, iclass 28, count 0 2006.202.01:41:15.98#ibcon#first serial, iclass 28, count 0 2006.202.01:41:15.98#ibcon#enter sib2, iclass 28, count 0 2006.202.01:41:15.98#ibcon#flushed, iclass 28, count 0 2006.202.01:41:15.98#ibcon#about to write, iclass 28, count 0 2006.202.01:41:15.98#ibcon#wrote, iclass 28, count 0 2006.202.01:41:15.98#ibcon#about to read 3, iclass 28, count 0 2006.202.01:41:16.00#ibcon#read 3, iclass 28, count 0 2006.202.01:41:16.00#ibcon#about to read 4, iclass 28, count 0 2006.202.01:41:16.00#ibcon#read 4, iclass 28, count 0 2006.202.01:41:16.00#ibcon#about to read 5, iclass 28, count 0 2006.202.01:41:16.00#ibcon#read 5, iclass 28, count 0 2006.202.01:41:16.00#ibcon#about to read 6, iclass 28, count 0 2006.202.01:41:16.00#ibcon#read 6, iclass 28, count 0 2006.202.01:41:16.00#ibcon#end of sib2, iclass 28, count 0 2006.202.01:41:16.00#ibcon#*mode == 0, iclass 28, count 0 2006.202.01:41:16.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.01:41:16.00#ibcon#[27=USB\r\n] 2006.202.01:41:16.00#ibcon#*before write, iclass 28, count 0 2006.202.01:41:16.00#ibcon#enter sib2, iclass 28, count 0 2006.202.01:41:16.00#ibcon#flushed, iclass 28, count 0 2006.202.01:41:16.00#ibcon#about to write, iclass 28, count 0 2006.202.01:41:16.00#ibcon#wrote, iclass 28, count 0 2006.202.01:41:16.00#ibcon#about to read 3, iclass 28, count 0 2006.202.01:41:16.03#ibcon#read 3, iclass 28, count 0 2006.202.01:41:16.03#ibcon#about to read 4, iclass 28, count 0 2006.202.01:41:16.03#ibcon#read 4, iclass 28, count 0 2006.202.01:41:16.03#ibcon#about to read 5, iclass 28, count 0 2006.202.01:41:16.03#ibcon#read 5, iclass 28, count 0 2006.202.01:41:16.03#ibcon#about to read 6, iclass 28, count 0 2006.202.01:41:16.03#ibcon#read 6, iclass 28, count 0 2006.202.01:41:16.03#ibcon#end of sib2, iclass 28, count 0 2006.202.01:41:16.03#ibcon#*after write, iclass 28, count 0 2006.202.01:41:16.03#ibcon#*before return 0, iclass 28, count 0 2006.202.01:41:16.03#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:16.03#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.202.01:41:16.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.01:41:16.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.01:41:16.03$vck44/vblo=6,719.99 2006.202.01:41:16.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.202.01:41:16.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.202.01:41:16.03#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:16.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:16.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:16.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:16.03#ibcon#enter wrdev, iclass 30, count 0 2006.202.01:41:16.03#ibcon#first serial, iclass 30, count 0 2006.202.01:41:16.03#ibcon#enter sib2, iclass 30, count 0 2006.202.01:41:16.03#ibcon#flushed, iclass 30, count 0 2006.202.01:41:16.03#ibcon#about to write, iclass 30, count 0 2006.202.01:41:16.03#ibcon#wrote, iclass 30, count 0 2006.202.01:41:16.03#ibcon#about to read 3, iclass 30, count 0 2006.202.01:41:16.05#ibcon#read 3, iclass 30, count 0 2006.202.01:41:16.05#ibcon#about to read 4, iclass 30, count 0 2006.202.01:41:16.05#ibcon#read 4, iclass 30, count 0 2006.202.01:41:16.05#ibcon#about to read 5, iclass 30, count 0 2006.202.01:41:16.05#ibcon#read 5, iclass 30, count 0 2006.202.01:41:16.05#ibcon#about to read 6, iclass 30, count 0 2006.202.01:41:16.05#ibcon#read 6, iclass 30, count 0 2006.202.01:41:16.05#ibcon#end of sib2, iclass 30, count 0 2006.202.01:41:16.05#ibcon#*mode == 0, iclass 30, count 0 2006.202.01:41:16.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.01:41:16.05#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.01:41:16.05#ibcon#*before write, iclass 30, count 0 2006.202.01:41:16.05#ibcon#enter sib2, iclass 30, count 0 2006.202.01:41:16.05#ibcon#flushed, iclass 30, count 0 2006.202.01:41:16.05#ibcon#about to write, iclass 30, count 0 2006.202.01:41:16.05#ibcon#wrote, iclass 30, count 0 2006.202.01:41:16.05#ibcon#about to read 3, iclass 30, count 0 2006.202.01:41:16.09#ibcon#read 3, iclass 30, count 0 2006.202.01:41:16.09#ibcon#about to read 4, iclass 30, count 0 2006.202.01:41:16.09#ibcon#read 4, iclass 30, count 0 2006.202.01:41:16.09#ibcon#about to read 5, iclass 30, count 0 2006.202.01:41:16.09#ibcon#read 5, iclass 30, count 0 2006.202.01:41:16.09#ibcon#about to read 6, iclass 30, count 0 2006.202.01:41:16.09#ibcon#read 6, iclass 30, count 0 2006.202.01:41:16.09#ibcon#end of sib2, iclass 30, count 0 2006.202.01:41:16.09#ibcon#*after write, iclass 30, count 0 2006.202.01:41:16.09#ibcon#*before return 0, iclass 30, count 0 2006.202.01:41:16.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:16.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.202.01:41:16.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.01:41:16.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.01:41:16.09$vck44/vb=6,4 2006.202.01:41:16.09#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.202.01:41:16.09#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.202.01:41:16.09#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:16.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:16.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:16.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:16.15#ibcon#enter wrdev, iclass 32, count 2 2006.202.01:41:16.15#ibcon#first serial, iclass 32, count 2 2006.202.01:41:16.15#ibcon#enter sib2, iclass 32, count 2 2006.202.01:41:16.15#ibcon#flushed, iclass 32, count 2 2006.202.01:41:16.15#ibcon#about to write, iclass 32, count 2 2006.202.01:41:16.15#ibcon#wrote, iclass 32, count 2 2006.202.01:41:16.15#ibcon#about to read 3, iclass 32, count 2 2006.202.01:41:16.17#ibcon#read 3, iclass 32, count 2 2006.202.01:41:16.17#ibcon#about to read 4, iclass 32, count 2 2006.202.01:41:16.17#ibcon#read 4, iclass 32, count 2 2006.202.01:41:16.17#ibcon#about to read 5, iclass 32, count 2 2006.202.01:41:16.17#ibcon#read 5, iclass 32, count 2 2006.202.01:41:16.17#ibcon#about to read 6, iclass 32, count 2 2006.202.01:41:16.17#ibcon#read 6, iclass 32, count 2 2006.202.01:41:16.17#ibcon#end of sib2, iclass 32, count 2 2006.202.01:41:16.17#ibcon#*mode == 0, iclass 32, count 2 2006.202.01:41:16.17#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.202.01:41:16.17#ibcon#[27=AT06-04\r\n] 2006.202.01:41:16.17#ibcon#*before write, iclass 32, count 2 2006.202.01:41:16.17#ibcon#enter sib2, iclass 32, count 2 2006.202.01:41:16.17#ibcon#flushed, iclass 32, count 2 2006.202.01:41:16.17#ibcon#about to write, iclass 32, count 2 2006.202.01:41:16.17#ibcon#wrote, iclass 32, count 2 2006.202.01:41:16.17#ibcon#about to read 3, iclass 32, count 2 2006.202.01:41:16.20#ibcon#read 3, iclass 32, count 2 2006.202.01:41:16.20#ibcon#about to read 4, iclass 32, count 2 2006.202.01:41:16.20#ibcon#read 4, iclass 32, count 2 2006.202.01:41:16.20#ibcon#about to read 5, iclass 32, count 2 2006.202.01:41:16.20#ibcon#read 5, iclass 32, count 2 2006.202.01:41:16.20#ibcon#about to read 6, iclass 32, count 2 2006.202.01:41:16.20#ibcon#read 6, iclass 32, count 2 2006.202.01:41:16.20#ibcon#end of sib2, iclass 32, count 2 2006.202.01:41:16.20#ibcon#*after write, iclass 32, count 2 2006.202.01:41:16.20#ibcon#*before return 0, iclass 32, count 2 2006.202.01:41:16.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:16.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.202.01:41:16.20#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.202.01:41:16.20#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:16.20#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:16.32#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:16.32#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:16.32#ibcon#enter wrdev, iclass 32, count 0 2006.202.01:41:16.32#ibcon#first serial, iclass 32, count 0 2006.202.01:41:16.32#ibcon#enter sib2, iclass 32, count 0 2006.202.01:41:16.32#ibcon#flushed, iclass 32, count 0 2006.202.01:41:16.32#ibcon#about to write, iclass 32, count 0 2006.202.01:41:16.32#ibcon#wrote, iclass 32, count 0 2006.202.01:41:16.32#ibcon#about to read 3, iclass 32, count 0 2006.202.01:41:16.34#ibcon#read 3, iclass 32, count 0 2006.202.01:41:16.34#ibcon#about to read 4, iclass 32, count 0 2006.202.01:41:16.34#ibcon#read 4, iclass 32, count 0 2006.202.01:41:16.34#ibcon#about to read 5, iclass 32, count 0 2006.202.01:41:16.34#ibcon#read 5, iclass 32, count 0 2006.202.01:41:16.34#ibcon#about to read 6, iclass 32, count 0 2006.202.01:41:16.34#ibcon#read 6, iclass 32, count 0 2006.202.01:41:16.34#ibcon#end of sib2, iclass 32, count 0 2006.202.01:41:16.34#ibcon#*mode == 0, iclass 32, count 0 2006.202.01:41:16.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.01:41:16.34#ibcon#[27=USB\r\n] 2006.202.01:41:16.34#ibcon#*before write, iclass 32, count 0 2006.202.01:41:16.34#ibcon#enter sib2, iclass 32, count 0 2006.202.01:41:16.34#ibcon#flushed, iclass 32, count 0 2006.202.01:41:16.34#ibcon#about to write, iclass 32, count 0 2006.202.01:41:16.34#ibcon#wrote, iclass 32, count 0 2006.202.01:41:16.34#ibcon#about to read 3, iclass 32, count 0 2006.202.01:41:16.37#ibcon#read 3, iclass 32, count 0 2006.202.01:41:16.37#ibcon#about to read 4, iclass 32, count 0 2006.202.01:41:16.37#ibcon#read 4, iclass 32, count 0 2006.202.01:41:16.37#ibcon#about to read 5, iclass 32, count 0 2006.202.01:41:16.37#ibcon#read 5, iclass 32, count 0 2006.202.01:41:16.37#ibcon#about to read 6, iclass 32, count 0 2006.202.01:41:16.37#ibcon#read 6, iclass 32, count 0 2006.202.01:41:16.37#ibcon#end of sib2, iclass 32, count 0 2006.202.01:41:16.37#ibcon#*after write, iclass 32, count 0 2006.202.01:41:16.37#ibcon#*before return 0, iclass 32, count 0 2006.202.01:41:16.37#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:16.37#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.202.01:41:16.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.01:41:16.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.01:41:16.37$vck44/vblo=7,734.99 2006.202.01:41:16.37#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.202.01:41:16.37#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.202.01:41:16.37#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:16.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:16.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:16.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:16.37#ibcon#enter wrdev, iclass 34, count 0 2006.202.01:41:16.37#ibcon#first serial, iclass 34, count 0 2006.202.01:41:16.37#ibcon#enter sib2, iclass 34, count 0 2006.202.01:41:16.37#ibcon#flushed, iclass 34, count 0 2006.202.01:41:16.37#ibcon#about to write, iclass 34, count 0 2006.202.01:41:16.37#ibcon#wrote, iclass 34, count 0 2006.202.01:41:16.37#ibcon#about to read 3, iclass 34, count 0 2006.202.01:41:16.39#ibcon#read 3, iclass 34, count 0 2006.202.01:41:16.39#ibcon#about to read 4, iclass 34, count 0 2006.202.01:41:16.39#ibcon#read 4, iclass 34, count 0 2006.202.01:41:16.39#ibcon#about to read 5, iclass 34, count 0 2006.202.01:41:16.39#ibcon#read 5, iclass 34, count 0 2006.202.01:41:16.39#ibcon#about to read 6, iclass 34, count 0 2006.202.01:41:16.39#ibcon#read 6, iclass 34, count 0 2006.202.01:41:16.39#ibcon#end of sib2, iclass 34, count 0 2006.202.01:41:16.39#ibcon#*mode == 0, iclass 34, count 0 2006.202.01:41:16.39#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.01:41:16.39#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.01:41:16.39#ibcon#*before write, iclass 34, count 0 2006.202.01:41:16.39#ibcon#enter sib2, iclass 34, count 0 2006.202.01:41:16.39#ibcon#flushed, iclass 34, count 0 2006.202.01:41:16.39#ibcon#about to write, iclass 34, count 0 2006.202.01:41:16.39#ibcon#wrote, iclass 34, count 0 2006.202.01:41:16.39#ibcon#about to read 3, iclass 34, count 0 2006.202.01:41:16.43#ibcon#read 3, iclass 34, count 0 2006.202.01:41:16.43#ibcon#about to read 4, iclass 34, count 0 2006.202.01:41:16.43#ibcon#read 4, iclass 34, count 0 2006.202.01:41:16.43#ibcon#about to read 5, iclass 34, count 0 2006.202.01:41:16.43#ibcon#read 5, iclass 34, count 0 2006.202.01:41:16.43#ibcon#about to read 6, iclass 34, count 0 2006.202.01:41:16.43#ibcon#read 6, iclass 34, count 0 2006.202.01:41:16.43#ibcon#end of sib2, iclass 34, count 0 2006.202.01:41:16.43#ibcon#*after write, iclass 34, count 0 2006.202.01:41:16.43#ibcon#*before return 0, iclass 34, count 0 2006.202.01:41:16.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:16.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.202.01:41:16.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.01:41:16.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.01:41:16.43$vck44/vb=7,4 2006.202.01:41:16.43#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.202.01:41:16.43#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.202.01:41:16.43#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:16.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:16.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:16.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:16.49#ibcon#enter wrdev, iclass 36, count 2 2006.202.01:41:16.49#ibcon#first serial, iclass 36, count 2 2006.202.01:41:16.49#ibcon#enter sib2, iclass 36, count 2 2006.202.01:41:16.49#ibcon#flushed, iclass 36, count 2 2006.202.01:41:16.49#ibcon#about to write, iclass 36, count 2 2006.202.01:41:16.49#ibcon#wrote, iclass 36, count 2 2006.202.01:41:16.49#ibcon#about to read 3, iclass 36, count 2 2006.202.01:41:16.51#ibcon#read 3, iclass 36, count 2 2006.202.01:41:16.51#ibcon#about to read 4, iclass 36, count 2 2006.202.01:41:16.51#ibcon#read 4, iclass 36, count 2 2006.202.01:41:16.51#ibcon#about to read 5, iclass 36, count 2 2006.202.01:41:16.51#ibcon#read 5, iclass 36, count 2 2006.202.01:41:16.51#ibcon#about to read 6, iclass 36, count 2 2006.202.01:41:16.51#ibcon#read 6, iclass 36, count 2 2006.202.01:41:16.51#ibcon#end of sib2, iclass 36, count 2 2006.202.01:41:16.51#ibcon#*mode == 0, iclass 36, count 2 2006.202.01:41:16.51#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.202.01:41:16.51#ibcon#[27=AT07-04\r\n] 2006.202.01:41:16.51#ibcon#*before write, iclass 36, count 2 2006.202.01:41:16.51#ibcon#enter sib2, iclass 36, count 2 2006.202.01:41:16.51#ibcon#flushed, iclass 36, count 2 2006.202.01:41:16.51#ibcon#about to write, iclass 36, count 2 2006.202.01:41:16.51#ibcon#wrote, iclass 36, count 2 2006.202.01:41:16.51#ibcon#about to read 3, iclass 36, count 2 2006.202.01:41:16.54#ibcon#read 3, iclass 36, count 2 2006.202.01:41:16.54#ibcon#about to read 4, iclass 36, count 2 2006.202.01:41:16.54#ibcon#read 4, iclass 36, count 2 2006.202.01:41:16.54#ibcon#about to read 5, iclass 36, count 2 2006.202.01:41:16.54#ibcon#read 5, iclass 36, count 2 2006.202.01:41:16.54#ibcon#about to read 6, iclass 36, count 2 2006.202.01:41:16.54#ibcon#read 6, iclass 36, count 2 2006.202.01:41:16.54#ibcon#end of sib2, iclass 36, count 2 2006.202.01:41:16.54#ibcon#*after write, iclass 36, count 2 2006.202.01:41:16.54#ibcon#*before return 0, iclass 36, count 2 2006.202.01:41:16.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:16.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.202.01:41:16.54#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.202.01:41:16.54#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:16.54#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:16.66#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:16.66#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:16.66#ibcon#enter wrdev, iclass 36, count 0 2006.202.01:41:16.66#ibcon#first serial, iclass 36, count 0 2006.202.01:41:16.66#ibcon#enter sib2, iclass 36, count 0 2006.202.01:41:16.66#ibcon#flushed, iclass 36, count 0 2006.202.01:41:16.66#ibcon#about to write, iclass 36, count 0 2006.202.01:41:16.66#ibcon#wrote, iclass 36, count 0 2006.202.01:41:16.66#ibcon#about to read 3, iclass 36, count 0 2006.202.01:41:16.68#ibcon#read 3, iclass 36, count 0 2006.202.01:41:16.68#ibcon#about to read 4, iclass 36, count 0 2006.202.01:41:16.68#ibcon#read 4, iclass 36, count 0 2006.202.01:41:16.68#ibcon#about to read 5, iclass 36, count 0 2006.202.01:41:16.68#ibcon#read 5, iclass 36, count 0 2006.202.01:41:16.68#ibcon#about to read 6, iclass 36, count 0 2006.202.01:41:16.68#ibcon#read 6, iclass 36, count 0 2006.202.01:41:16.68#ibcon#end of sib2, iclass 36, count 0 2006.202.01:41:16.68#ibcon#*mode == 0, iclass 36, count 0 2006.202.01:41:16.68#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.01:41:16.68#ibcon#[27=USB\r\n] 2006.202.01:41:16.68#ibcon#*before write, iclass 36, count 0 2006.202.01:41:16.68#ibcon#enter sib2, iclass 36, count 0 2006.202.01:41:16.68#ibcon#flushed, iclass 36, count 0 2006.202.01:41:16.68#ibcon#about to write, iclass 36, count 0 2006.202.01:41:16.68#ibcon#wrote, iclass 36, count 0 2006.202.01:41:16.68#ibcon#about to read 3, iclass 36, count 0 2006.202.01:41:16.71#ibcon#read 3, iclass 36, count 0 2006.202.01:41:16.71#ibcon#about to read 4, iclass 36, count 0 2006.202.01:41:16.71#ibcon#read 4, iclass 36, count 0 2006.202.01:41:16.71#ibcon#about to read 5, iclass 36, count 0 2006.202.01:41:16.71#ibcon#read 5, iclass 36, count 0 2006.202.01:41:16.71#ibcon#about to read 6, iclass 36, count 0 2006.202.01:41:16.71#ibcon#read 6, iclass 36, count 0 2006.202.01:41:16.71#ibcon#end of sib2, iclass 36, count 0 2006.202.01:41:16.71#ibcon#*after write, iclass 36, count 0 2006.202.01:41:16.71#ibcon#*before return 0, iclass 36, count 0 2006.202.01:41:16.71#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:16.71#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.202.01:41:16.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.01:41:16.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.01:41:16.71$vck44/vblo=8,744.99 2006.202.01:41:16.71#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.01:41:16.71#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.01:41:16.71#ibcon#ireg 17 cls_cnt 0 2006.202.01:41:16.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:16.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:16.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:16.71#ibcon#enter wrdev, iclass 38, count 0 2006.202.01:41:16.71#ibcon#first serial, iclass 38, count 0 2006.202.01:41:16.71#ibcon#enter sib2, iclass 38, count 0 2006.202.01:41:16.71#ibcon#flushed, iclass 38, count 0 2006.202.01:41:16.71#ibcon#about to write, iclass 38, count 0 2006.202.01:41:16.71#ibcon#wrote, iclass 38, count 0 2006.202.01:41:16.71#ibcon#about to read 3, iclass 38, count 0 2006.202.01:41:16.73#ibcon#read 3, iclass 38, count 0 2006.202.01:41:16.73#ibcon#about to read 4, iclass 38, count 0 2006.202.01:41:16.73#ibcon#read 4, iclass 38, count 0 2006.202.01:41:16.73#ibcon#about to read 5, iclass 38, count 0 2006.202.01:41:16.73#ibcon#read 5, iclass 38, count 0 2006.202.01:41:16.73#ibcon#about to read 6, iclass 38, count 0 2006.202.01:41:16.73#ibcon#read 6, iclass 38, count 0 2006.202.01:41:16.73#ibcon#end of sib2, iclass 38, count 0 2006.202.01:41:16.73#ibcon#*mode == 0, iclass 38, count 0 2006.202.01:41:16.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.01:41:16.73#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.01:41:16.73#ibcon#*before write, iclass 38, count 0 2006.202.01:41:16.73#ibcon#enter sib2, iclass 38, count 0 2006.202.01:41:16.73#ibcon#flushed, iclass 38, count 0 2006.202.01:41:16.73#ibcon#about to write, iclass 38, count 0 2006.202.01:41:16.73#ibcon#wrote, iclass 38, count 0 2006.202.01:41:16.73#ibcon#about to read 3, iclass 38, count 0 2006.202.01:41:16.77#ibcon#read 3, iclass 38, count 0 2006.202.01:41:16.77#ibcon#about to read 4, iclass 38, count 0 2006.202.01:41:16.77#ibcon#read 4, iclass 38, count 0 2006.202.01:41:16.77#ibcon#about to read 5, iclass 38, count 0 2006.202.01:41:16.77#ibcon#read 5, iclass 38, count 0 2006.202.01:41:16.77#ibcon#about to read 6, iclass 38, count 0 2006.202.01:41:16.77#ibcon#read 6, iclass 38, count 0 2006.202.01:41:16.77#ibcon#end of sib2, iclass 38, count 0 2006.202.01:41:16.77#ibcon#*after write, iclass 38, count 0 2006.202.01:41:16.77#ibcon#*before return 0, iclass 38, count 0 2006.202.01:41:16.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:16.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:41:16.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.01:41:16.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.01:41:16.77$vck44/vb=8,4 2006.202.01:41:16.77#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.202.01:41:16.77#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.202.01:41:16.77#ibcon#ireg 11 cls_cnt 2 2006.202.01:41:16.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:16.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:16.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:16.83#ibcon#enter wrdev, iclass 40, count 2 2006.202.01:41:16.83#ibcon#first serial, iclass 40, count 2 2006.202.01:41:16.83#ibcon#enter sib2, iclass 40, count 2 2006.202.01:41:16.83#ibcon#flushed, iclass 40, count 2 2006.202.01:41:16.83#ibcon#about to write, iclass 40, count 2 2006.202.01:41:16.83#ibcon#wrote, iclass 40, count 2 2006.202.01:41:16.83#ibcon#about to read 3, iclass 40, count 2 2006.202.01:41:16.85#ibcon#read 3, iclass 40, count 2 2006.202.01:41:16.85#ibcon#about to read 4, iclass 40, count 2 2006.202.01:41:16.85#ibcon#read 4, iclass 40, count 2 2006.202.01:41:16.85#ibcon#about to read 5, iclass 40, count 2 2006.202.01:41:16.85#ibcon#read 5, iclass 40, count 2 2006.202.01:41:16.85#ibcon#about to read 6, iclass 40, count 2 2006.202.01:41:16.85#ibcon#read 6, iclass 40, count 2 2006.202.01:41:16.85#ibcon#end of sib2, iclass 40, count 2 2006.202.01:41:16.85#ibcon#*mode == 0, iclass 40, count 2 2006.202.01:41:16.85#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.202.01:41:16.85#ibcon#[27=AT08-04\r\n] 2006.202.01:41:16.85#ibcon#*before write, iclass 40, count 2 2006.202.01:41:16.85#ibcon#enter sib2, iclass 40, count 2 2006.202.01:41:16.85#ibcon#flushed, iclass 40, count 2 2006.202.01:41:16.85#ibcon#about to write, iclass 40, count 2 2006.202.01:41:16.85#ibcon#wrote, iclass 40, count 2 2006.202.01:41:16.85#ibcon#about to read 3, iclass 40, count 2 2006.202.01:41:16.88#ibcon#read 3, iclass 40, count 2 2006.202.01:41:16.94#ibcon#about to read 4, iclass 40, count 2 2006.202.01:41:16.94#ibcon#read 4, iclass 40, count 2 2006.202.01:41:16.94#ibcon#about to read 5, iclass 40, count 2 2006.202.01:41:16.94#ibcon#read 5, iclass 40, count 2 2006.202.01:41:16.94#ibcon#about to read 6, iclass 40, count 2 2006.202.01:41:16.94#ibcon#read 6, iclass 40, count 2 2006.202.01:41:16.94#ibcon#end of sib2, iclass 40, count 2 2006.202.01:41:16.94#ibcon#*after write, iclass 40, count 2 2006.202.01:41:16.94#ibcon#*before return 0, iclass 40, count 2 2006.202.01:41:16.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:16.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.202.01:41:16.94#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.202.01:41:16.94#ibcon#ireg 7 cls_cnt 0 2006.202.01:41:16.94#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:17.07#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:17.07#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:17.07#ibcon#enter wrdev, iclass 40, count 0 2006.202.01:41:17.07#ibcon#first serial, iclass 40, count 0 2006.202.01:41:17.07#ibcon#enter sib2, iclass 40, count 0 2006.202.01:41:17.07#ibcon#flushed, iclass 40, count 0 2006.202.01:41:17.07#ibcon#about to write, iclass 40, count 0 2006.202.01:41:17.07#ibcon#wrote, iclass 40, count 0 2006.202.01:41:17.07#ibcon#about to read 3, iclass 40, count 0 2006.202.01:41:17.09#ibcon#read 3, iclass 40, count 0 2006.202.01:41:17.09#ibcon#about to read 4, iclass 40, count 0 2006.202.01:41:17.09#ibcon#read 4, iclass 40, count 0 2006.202.01:41:17.09#ibcon#about to read 5, iclass 40, count 0 2006.202.01:41:17.09#ibcon#read 5, iclass 40, count 0 2006.202.01:41:17.09#ibcon#about to read 6, iclass 40, count 0 2006.202.01:41:17.09#ibcon#read 6, iclass 40, count 0 2006.202.01:41:17.09#ibcon#end of sib2, iclass 40, count 0 2006.202.01:41:17.09#ibcon#*mode == 0, iclass 40, count 0 2006.202.01:41:17.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.01:41:17.09#ibcon#[27=USB\r\n] 2006.202.01:41:17.09#ibcon#*before write, iclass 40, count 0 2006.202.01:41:17.09#ibcon#enter sib2, iclass 40, count 0 2006.202.01:41:17.09#ibcon#flushed, iclass 40, count 0 2006.202.01:41:17.09#ibcon#about to write, iclass 40, count 0 2006.202.01:41:17.09#ibcon#wrote, iclass 40, count 0 2006.202.01:41:17.09#ibcon#about to read 3, iclass 40, count 0 2006.202.01:41:17.12#ibcon#read 3, iclass 40, count 0 2006.202.01:41:17.12#ibcon#about to read 4, iclass 40, count 0 2006.202.01:41:17.12#ibcon#read 4, iclass 40, count 0 2006.202.01:41:17.12#ibcon#about to read 5, iclass 40, count 0 2006.202.01:41:17.12#ibcon#read 5, iclass 40, count 0 2006.202.01:41:17.12#ibcon#about to read 6, iclass 40, count 0 2006.202.01:41:17.12#ibcon#read 6, iclass 40, count 0 2006.202.01:41:17.12#ibcon#end of sib2, iclass 40, count 0 2006.202.01:41:17.12#ibcon#*after write, iclass 40, count 0 2006.202.01:41:17.12#ibcon#*before return 0, iclass 40, count 0 2006.202.01:41:17.12#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:17.12#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.202.01:41:17.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.01:41:17.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.01:41:17.12$vck44/vabw=wide 2006.202.01:41:17.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.202.01:41:17.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.202.01:41:17.12#ibcon#ireg 8 cls_cnt 0 2006.202.01:41:17.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:17.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:17.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:17.12#ibcon#enter wrdev, iclass 4, count 0 2006.202.01:41:17.12#ibcon#first serial, iclass 4, count 0 2006.202.01:41:17.12#ibcon#enter sib2, iclass 4, count 0 2006.202.01:41:17.12#ibcon#flushed, iclass 4, count 0 2006.202.01:41:17.12#ibcon#about to write, iclass 4, count 0 2006.202.01:41:17.12#ibcon#wrote, iclass 4, count 0 2006.202.01:41:17.12#ibcon#about to read 3, iclass 4, count 0 2006.202.01:41:17.14#ibcon#read 3, iclass 4, count 0 2006.202.01:41:17.14#ibcon#about to read 4, iclass 4, count 0 2006.202.01:41:17.14#ibcon#read 4, iclass 4, count 0 2006.202.01:41:17.14#ibcon#about to read 5, iclass 4, count 0 2006.202.01:41:17.14#ibcon#read 5, iclass 4, count 0 2006.202.01:41:17.14#ibcon#about to read 6, iclass 4, count 0 2006.202.01:41:17.14#ibcon#read 6, iclass 4, count 0 2006.202.01:41:17.14#ibcon#end of sib2, iclass 4, count 0 2006.202.01:41:17.14#ibcon#*mode == 0, iclass 4, count 0 2006.202.01:41:17.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.01:41:17.14#ibcon#[25=BW32\r\n] 2006.202.01:41:17.14#ibcon#*before write, iclass 4, count 0 2006.202.01:41:17.14#ibcon#enter sib2, iclass 4, count 0 2006.202.01:41:17.14#ibcon#flushed, iclass 4, count 0 2006.202.01:41:17.14#ibcon#about to write, iclass 4, count 0 2006.202.01:41:17.14#ibcon#wrote, iclass 4, count 0 2006.202.01:41:17.14#ibcon#about to read 3, iclass 4, count 0 2006.202.01:41:17.17#ibcon#read 3, iclass 4, count 0 2006.202.01:41:17.17#ibcon#about to read 4, iclass 4, count 0 2006.202.01:41:17.17#ibcon#read 4, iclass 4, count 0 2006.202.01:41:17.17#ibcon#about to read 5, iclass 4, count 0 2006.202.01:41:17.17#ibcon#read 5, iclass 4, count 0 2006.202.01:41:17.17#ibcon#about to read 6, iclass 4, count 0 2006.202.01:41:17.17#ibcon#read 6, iclass 4, count 0 2006.202.01:41:17.17#ibcon#end of sib2, iclass 4, count 0 2006.202.01:41:17.17#ibcon#*after write, iclass 4, count 0 2006.202.01:41:17.17#ibcon#*before return 0, iclass 4, count 0 2006.202.01:41:17.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:17.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.202.01:41:17.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.01:41:17.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.01:41:17.17$vck44/vbbw=wide 2006.202.01:41:17.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.202.01:41:17.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.202.01:41:17.17#ibcon#ireg 8 cls_cnt 0 2006.202.01:41:17.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:41:17.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:41:17.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:41:17.24#ibcon#enter wrdev, iclass 6, count 0 2006.202.01:41:17.24#ibcon#first serial, iclass 6, count 0 2006.202.01:41:17.24#ibcon#enter sib2, iclass 6, count 0 2006.202.01:41:17.24#ibcon#flushed, iclass 6, count 0 2006.202.01:41:17.24#ibcon#about to write, iclass 6, count 0 2006.202.01:41:17.24#ibcon#wrote, iclass 6, count 0 2006.202.01:41:17.24#ibcon#about to read 3, iclass 6, count 0 2006.202.01:41:17.26#ibcon#read 3, iclass 6, count 0 2006.202.01:41:17.26#ibcon#about to read 4, iclass 6, count 0 2006.202.01:41:17.26#ibcon#read 4, iclass 6, count 0 2006.202.01:41:17.26#ibcon#about to read 5, iclass 6, count 0 2006.202.01:41:17.26#ibcon#read 5, iclass 6, count 0 2006.202.01:41:17.26#ibcon#about to read 6, iclass 6, count 0 2006.202.01:41:17.26#ibcon#read 6, iclass 6, count 0 2006.202.01:41:17.26#ibcon#end of sib2, iclass 6, count 0 2006.202.01:41:17.26#ibcon#*mode == 0, iclass 6, count 0 2006.202.01:41:17.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.01:41:17.26#ibcon#[27=BW32\r\n] 2006.202.01:41:17.26#ibcon#*before write, iclass 6, count 0 2006.202.01:41:17.26#ibcon#enter sib2, iclass 6, count 0 2006.202.01:41:17.26#ibcon#flushed, iclass 6, count 0 2006.202.01:41:17.26#ibcon#about to write, iclass 6, count 0 2006.202.01:41:17.26#ibcon#wrote, iclass 6, count 0 2006.202.01:41:17.26#ibcon#about to read 3, iclass 6, count 0 2006.202.01:41:17.29#ibcon#read 3, iclass 6, count 0 2006.202.01:41:17.29#ibcon#about to read 4, iclass 6, count 0 2006.202.01:41:17.29#ibcon#read 4, iclass 6, count 0 2006.202.01:41:17.29#ibcon#about to read 5, iclass 6, count 0 2006.202.01:41:17.29#ibcon#read 5, iclass 6, count 0 2006.202.01:41:17.29#ibcon#about to read 6, iclass 6, count 0 2006.202.01:41:17.29#ibcon#read 6, iclass 6, count 0 2006.202.01:41:17.29#ibcon#end of sib2, iclass 6, count 0 2006.202.01:41:17.29#ibcon#*after write, iclass 6, count 0 2006.202.01:41:17.29#ibcon#*before return 0, iclass 6, count 0 2006.202.01:41:17.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:41:17.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:41:17.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.01:41:17.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.01:41:17.29$setupk4/ifdk4 2006.202.01:41:17.29$ifdk4/lo= 2006.202.01:41:17.29$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.01:41:17.29$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.01:41:17.29$ifdk4/patch= 2006.202.01:41:17.29$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.01:41:17.29$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.01:41:17.29$setupk4/!*+20s 2006.202.01:41:20.14#trakl#Source acquired 2006.202.01:41:20.14#flagr#flagr/antenna,acquired 2006.202.01:41:24.65#abcon#<5=/04 1.6 3.2 20.571001000.8\r\n> 2006.202.01:41:24.67#abcon#{5=INTERFACE CLEAR} 2006.202.01:41:24.73#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:41:31.53$setupk4/"tpicd 2006.202.01:41:31.53$setupk4/echo=off 2006.202.01:41:31.53$setupk4/xlog=off 2006.202.01:41:31.53:!2006.202.01:41:36 2006.202.01:41:36.00:preob 2006.202.01:41:36.14/onsource/TRACKING 2006.202.01:41:36.14:!2006.202.01:41:46 2006.202.01:41:46.00:"tape 2006.202.01:41:46.00:"st=record 2006.202.01:41:46.00:data_valid=on 2006.202.01:41:46.00:midob 2006.202.01:41:47.14/onsource/TRACKING 2006.202.01:41:47.14/wx/20.57,1000.8,100 2006.202.01:41:47.20/cable/+6.4830E-03 2006.202.01:41:48.29/va/01,08,usb,yes,44,47 2006.202.01:41:48.29/va/02,07,usb,yes,47,48 2006.202.01:41:48.29/va/03,08,usb,yes,43,45 2006.202.01:41:48.29/va/04,07,usb,yes,49,51 2006.202.01:41:48.29/va/05,04,usb,yes,43,44 2006.202.01:41:48.29/va/06,05,usb,yes,43,44 2006.202.01:41:48.29/va/07,05,usb,yes,43,44 2006.202.01:41:48.29/va/08,04,usb,yes,42,50 2006.202.01:41:48.52/valo/01,524.99,yes,locked 2006.202.01:41:48.52/valo/02,534.99,yes,locked 2006.202.01:41:48.52/valo/03,564.99,yes,locked 2006.202.01:41:48.52/valo/04,624.99,yes,locked 2006.202.01:41:48.52/valo/05,734.99,yes,locked 2006.202.01:41:48.52/valo/06,814.99,yes,locked 2006.202.01:41:48.52/valo/07,864.99,yes,locked 2006.202.01:41:48.52/valo/08,884.99,yes,locked 2006.202.01:41:49.61/vb/01,04,usb,yes,30,27 2006.202.01:41:49.61/vb/02,05,usb,yes,28,28 2006.202.01:41:49.61/vb/03,04,usb,yes,29,32 2006.202.01:41:49.61/vb/04,05,usb,yes,29,28 2006.202.01:41:49.61/vb/05,04,usb,yes,26,28 2006.202.01:41:49.61/vb/06,04,usb,yes,30,26 2006.202.01:41:49.61/vb/07,04,usb,yes,30,30 2006.202.01:41:49.61/vb/08,04,usb,yes,28,31 2006.202.01:41:49.84/vblo/01,629.99,yes,locked 2006.202.01:41:49.84/vblo/02,634.99,yes,locked 2006.202.01:41:49.84/vblo/03,649.99,yes,locked 2006.202.01:41:49.84/vblo/04,679.99,yes,locked 2006.202.01:41:49.84/vblo/05,709.99,yes,locked 2006.202.01:41:49.84/vblo/06,719.99,yes,locked 2006.202.01:41:49.84/vblo/07,734.99,yes,locked 2006.202.01:41:49.84/vblo/08,744.99,yes,locked 2006.202.01:41:49.99/vabw/8 2006.202.01:41:50.14/vbbw/8 2006.202.01:41:50.23/xfe/off,on,15.0 2006.202.01:41:50.61/ifatt/23,28,28,28 2006.202.01:41:51.07/fmout-gps/S +4.50E-07 2006.202.01:41:51.11:!2006.202.01:43:16 2006.202.01:43:16.00:data_valid=off 2006.202.01:43:16.00:"et 2006.202.01:43:16.00:!+3s 2006.202.01:43:19.01:"tape 2006.202.01:43:19.01:postob 2006.202.01:43:19.17/cable/+6.4844E-03 2006.202.01:43:19.17/wx/20.55,1000.7,100 2006.202.01:43:20.07/fmout-gps/S +4.50E-07 2006.202.01:43:20.07:scan_name=202-0146,jd0607,230 2006.202.01:43:20.07:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.202.01:43:20.14#flagr#flagr/antenna,new-source 2006.202.01:43:21.14:checkk5 2006.202.01:43:21.75/chk_autoobs//k5ts1/ autoobs is running! 2006.202.01:43:22.19/chk_autoobs//k5ts2/ autoobs is running! 2006.202.01:43:22.57/chk_autoobs//k5ts3/ autoobs is running! 2006.202.01:43:23.14/chk_autoobs//k5ts4/ autoobs is running! 2006.202.01:43:23.76/chk_obsdata//k5ts1/T2020141??a.dat file size is correct (nominal:360MB, actual:356MB). 2006.202.01:43:24.19/chk_obsdata//k5ts2/T2020141??b.dat file size is correct (nominal:360MB, actual:356MB). 2006.202.01:43:24.57/chk_obsdata//k5ts3/T2020141??c.dat file size is correct (nominal:360MB, actual:356MB). 2006.202.01:43:25.00/chk_obsdata//k5ts4/T2020141??d.dat file size is correct (nominal:360MB, actual:356MB). 2006.202.01:43:25.82/k5log//k5ts1_log_newline 2006.202.01:43:26.58/k5log//k5ts2_log_newline 2006.202.01:43:27.39/k5log//k5ts3_log_newline 2006.202.01:43:28.22/k5log//k5ts4_log_newline 2006.202.01:43:28.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.01:43:28.25:setupk4=1 2006.202.01:43:28.25$setupk4/echo=on 2006.202.01:43:28.25$setupk4/pcalon 2006.202.01:43:28.25$pcalon/"no phase cal control is implemented here 2006.202.01:43:28.25$setupk4/"tpicd=stop 2006.202.01:43:28.25$setupk4/"rec=synch_on 2006.202.01:43:28.25$setupk4/"rec_mode=128 2006.202.01:43:28.25$setupk4/!* 2006.202.01:43:28.25$setupk4/recpk4 2006.202.01:43:28.25$recpk4/recpatch= 2006.202.01:43:28.25$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.01:43:28.25$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.01:43:28.25$setupk4/vck44 2006.202.01:43:28.25$vck44/valo=1,524.99 2006.202.01:43:28.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.202.01:43:28.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.202.01:43:28.25#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:28.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:28.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:28.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:28.25#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:43:28.25#ibcon#first serial, iclass 29, count 0 2006.202.01:43:28.25#ibcon#enter sib2, iclass 29, count 0 2006.202.01:43:28.25#ibcon#flushed, iclass 29, count 0 2006.202.01:43:28.25#ibcon#about to write, iclass 29, count 0 2006.202.01:43:28.25#ibcon#wrote, iclass 29, count 0 2006.202.01:43:28.25#ibcon#about to read 3, iclass 29, count 0 2006.202.01:43:28.30#ibcon#read 3, iclass 29, count 0 2006.202.01:43:28.30#ibcon#about to read 4, iclass 29, count 0 2006.202.01:43:28.30#ibcon#read 4, iclass 29, count 0 2006.202.01:43:28.30#ibcon#about to read 5, iclass 29, count 0 2006.202.01:43:28.30#ibcon#read 5, iclass 29, count 0 2006.202.01:43:28.30#ibcon#about to read 6, iclass 29, count 0 2006.202.01:43:28.30#ibcon#read 6, iclass 29, count 0 2006.202.01:43:28.30#ibcon#end of sib2, iclass 29, count 0 2006.202.01:43:28.30#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:43:28.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:43:28.30#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.01:43:28.30#ibcon#*before write, iclass 29, count 0 2006.202.01:43:28.30#ibcon#enter sib2, iclass 29, count 0 2006.202.01:43:28.30#ibcon#flushed, iclass 29, count 0 2006.202.01:43:28.30#ibcon#about to write, iclass 29, count 0 2006.202.01:43:28.30#ibcon#wrote, iclass 29, count 0 2006.202.01:43:28.30#ibcon#about to read 3, iclass 29, count 0 2006.202.01:43:28.35#ibcon#read 3, iclass 29, count 0 2006.202.01:43:28.35#ibcon#about to read 4, iclass 29, count 0 2006.202.01:43:28.35#ibcon#read 4, iclass 29, count 0 2006.202.01:43:28.35#ibcon#about to read 5, iclass 29, count 0 2006.202.01:43:28.35#ibcon#read 5, iclass 29, count 0 2006.202.01:43:28.35#ibcon#about to read 6, iclass 29, count 0 2006.202.01:43:28.35#ibcon#read 6, iclass 29, count 0 2006.202.01:43:28.35#ibcon#end of sib2, iclass 29, count 0 2006.202.01:43:28.35#ibcon#*after write, iclass 29, count 0 2006.202.01:43:28.35#ibcon#*before return 0, iclass 29, count 0 2006.202.01:43:28.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:28.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:28.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:43:28.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:43:28.35$vck44/va=1,8 2006.202.01:43:28.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.202.01:43:28.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.202.01:43:28.35#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:28.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:28.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:28.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:28.35#ibcon#enter wrdev, iclass 31, count 2 2006.202.01:43:28.35#ibcon#first serial, iclass 31, count 2 2006.202.01:43:28.35#ibcon#enter sib2, iclass 31, count 2 2006.202.01:43:28.35#ibcon#flushed, iclass 31, count 2 2006.202.01:43:28.35#ibcon#about to write, iclass 31, count 2 2006.202.01:43:28.35#ibcon#wrote, iclass 31, count 2 2006.202.01:43:28.35#ibcon#about to read 3, iclass 31, count 2 2006.202.01:43:28.37#ibcon#read 3, iclass 31, count 2 2006.202.01:43:28.37#ibcon#about to read 4, iclass 31, count 2 2006.202.01:43:28.37#ibcon#read 4, iclass 31, count 2 2006.202.01:43:28.37#ibcon#about to read 5, iclass 31, count 2 2006.202.01:43:28.37#ibcon#read 5, iclass 31, count 2 2006.202.01:43:28.37#ibcon#about to read 6, iclass 31, count 2 2006.202.01:43:28.37#ibcon#read 6, iclass 31, count 2 2006.202.01:43:28.37#ibcon#end of sib2, iclass 31, count 2 2006.202.01:43:28.37#ibcon#*mode == 0, iclass 31, count 2 2006.202.01:43:28.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.202.01:43:28.37#ibcon#[25=AT01-08\r\n] 2006.202.01:43:28.37#ibcon#*before write, iclass 31, count 2 2006.202.01:43:28.37#ibcon#enter sib2, iclass 31, count 2 2006.202.01:43:28.37#ibcon#flushed, iclass 31, count 2 2006.202.01:43:28.37#ibcon#about to write, iclass 31, count 2 2006.202.01:43:28.37#ibcon#wrote, iclass 31, count 2 2006.202.01:43:28.37#ibcon#about to read 3, iclass 31, count 2 2006.202.01:43:28.40#ibcon#read 3, iclass 31, count 2 2006.202.01:43:28.40#ibcon#about to read 4, iclass 31, count 2 2006.202.01:43:28.40#ibcon#read 4, iclass 31, count 2 2006.202.01:43:28.40#ibcon#about to read 5, iclass 31, count 2 2006.202.01:43:28.40#ibcon#read 5, iclass 31, count 2 2006.202.01:43:28.40#ibcon#about to read 6, iclass 31, count 2 2006.202.01:43:28.40#ibcon#read 6, iclass 31, count 2 2006.202.01:43:28.40#ibcon#end of sib2, iclass 31, count 2 2006.202.01:43:28.40#ibcon#*after write, iclass 31, count 2 2006.202.01:43:28.40#ibcon#*before return 0, iclass 31, count 2 2006.202.01:43:28.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:28.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:28.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.202.01:43:28.40#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:28.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:28.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:28.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:28.52#ibcon#enter wrdev, iclass 31, count 0 2006.202.01:43:28.52#ibcon#first serial, iclass 31, count 0 2006.202.01:43:28.52#ibcon#enter sib2, iclass 31, count 0 2006.202.01:43:28.52#ibcon#flushed, iclass 31, count 0 2006.202.01:43:28.52#ibcon#about to write, iclass 31, count 0 2006.202.01:43:28.52#ibcon#wrote, iclass 31, count 0 2006.202.01:43:28.52#ibcon#about to read 3, iclass 31, count 0 2006.202.01:43:28.54#ibcon#read 3, iclass 31, count 0 2006.202.01:43:28.54#ibcon#about to read 4, iclass 31, count 0 2006.202.01:43:28.54#ibcon#read 4, iclass 31, count 0 2006.202.01:43:28.54#ibcon#about to read 5, iclass 31, count 0 2006.202.01:43:28.54#ibcon#read 5, iclass 31, count 0 2006.202.01:43:28.54#ibcon#about to read 6, iclass 31, count 0 2006.202.01:43:28.54#ibcon#read 6, iclass 31, count 0 2006.202.01:43:28.54#ibcon#end of sib2, iclass 31, count 0 2006.202.01:43:28.54#ibcon#*mode == 0, iclass 31, count 0 2006.202.01:43:28.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.01:43:28.54#ibcon#[25=USB\r\n] 2006.202.01:43:28.54#ibcon#*before write, iclass 31, count 0 2006.202.01:43:28.54#ibcon#enter sib2, iclass 31, count 0 2006.202.01:43:28.54#ibcon#flushed, iclass 31, count 0 2006.202.01:43:28.54#ibcon#about to write, iclass 31, count 0 2006.202.01:43:28.54#ibcon#wrote, iclass 31, count 0 2006.202.01:43:28.54#ibcon#about to read 3, iclass 31, count 0 2006.202.01:43:28.57#ibcon#read 3, iclass 31, count 0 2006.202.01:43:28.57#ibcon#about to read 4, iclass 31, count 0 2006.202.01:43:28.57#ibcon#read 4, iclass 31, count 0 2006.202.01:43:28.57#ibcon#about to read 5, iclass 31, count 0 2006.202.01:43:28.57#ibcon#read 5, iclass 31, count 0 2006.202.01:43:28.57#ibcon#about to read 6, iclass 31, count 0 2006.202.01:43:28.57#ibcon#read 6, iclass 31, count 0 2006.202.01:43:28.57#ibcon#end of sib2, iclass 31, count 0 2006.202.01:43:28.57#ibcon#*after write, iclass 31, count 0 2006.202.01:43:28.57#ibcon#*before return 0, iclass 31, count 0 2006.202.01:43:28.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:28.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:28.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.01:43:28.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.01:43:28.57$vck44/valo=2,534.99 2006.202.01:43:28.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.01:43:28.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.01:43:28.57#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:28.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:28.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:28.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:28.57#ibcon#enter wrdev, iclass 33, count 0 2006.202.01:43:28.57#ibcon#first serial, iclass 33, count 0 2006.202.01:43:28.57#ibcon#enter sib2, iclass 33, count 0 2006.202.01:43:28.57#ibcon#flushed, iclass 33, count 0 2006.202.01:43:28.57#ibcon#about to write, iclass 33, count 0 2006.202.01:43:28.57#ibcon#wrote, iclass 33, count 0 2006.202.01:43:28.57#ibcon#about to read 3, iclass 33, count 0 2006.202.01:43:28.59#ibcon#read 3, iclass 33, count 0 2006.202.01:43:28.59#ibcon#about to read 4, iclass 33, count 0 2006.202.01:43:28.59#ibcon#read 4, iclass 33, count 0 2006.202.01:43:28.59#ibcon#about to read 5, iclass 33, count 0 2006.202.01:43:28.59#ibcon#read 5, iclass 33, count 0 2006.202.01:43:28.59#ibcon#about to read 6, iclass 33, count 0 2006.202.01:43:28.59#ibcon#read 6, iclass 33, count 0 2006.202.01:43:28.59#ibcon#end of sib2, iclass 33, count 0 2006.202.01:43:28.59#ibcon#*mode == 0, iclass 33, count 0 2006.202.01:43:28.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.01:43:28.59#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.01:43:28.59#ibcon#*before write, iclass 33, count 0 2006.202.01:43:28.59#ibcon#enter sib2, iclass 33, count 0 2006.202.01:43:28.59#ibcon#flushed, iclass 33, count 0 2006.202.01:43:28.59#ibcon#about to write, iclass 33, count 0 2006.202.01:43:28.59#ibcon#wrote, iclass 33, count 0 2006.202.01:43:28.59#ibcon#about to read 3, iclass 33, count 0 2006.202.01:43:28.63#ibcon#read 3, iclass 33, count 0 2006.202.01:43:28.63#ibcon#about to read 4, iclass 33, count 0 2006.202.01:43:28.63#ibcon#read 4, iclass 33, count 0 2006.202.01:43:28.63#ibcon#about to read 5, iclass 33, count 0 2006.202.01:43:28.63#ibcon#read 5, iclass 33, count 0 2006.202.01:43:28.63#ibcon#about to read 6, iclass 33, count 0 2006.202.01:43:28.63#ibcon#read 6, iclass 33, count 0 2006.202.01:43:28.63#ibcon#end of sib2, iclass 33, count 0 2006.202.01:43:28.63#ibcon#*after write, iclass 33, count 0 2006.202.01:43:28.63#ibcon#*before return 0, iclass 33, count 0 2006.202.01:43:28.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:28.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:28.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.01:43:28.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.01:43:28.63$vck44/va=2,7 2006.202.01:43:28.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.202.01:43:28.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.202.01:43:28.63#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:28.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:28.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:28.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:28.69#ibcon#enter wrdev, iclass 35, count 2 2006.202.01:43:28.69#ibcon#first serial, iclass 35, count 2 2006.202.01:43:28.69#ibcon#enter sib2, iclass 35, count 2 2006.202.01:43:28.69#ibcon#flushed, iclass 35, count 2 2006.202.01:43:28.69#ibcon#about to write, iclass 35, count 2 2006.202.01:43:28.69#ibcon#wrote, iclass 35, count 2 2006.202.01:43:28.69#ibcon#about to read 3, iclass 35, count 2 2006.202.01:43:28.71#ibcon#read 3, iclass 35, count 2 2006.202.01:43:28.71#ibcon#about to read 4, iclass 35, count 2 2006.202.01:43:28.71#ibcon#read 4, iclass 35, count 2 2006.202.01:43:28.71#ibcon#about to read 5, iclass 35, count 2 2006.202.01:43:28.71#ibcon#read 5, iclass 35, count 2 2006.202.01:43:28.71#ibcon#about to read 6, iclass 35, count 2 2006.202.01:43:28.71#ibcon#read 6, iclass 35, count 2 2006.202.01:43:28.71#ibcon#end of sib2, iclass 35, count 2 2006.202.01:43:28.71#ibcon#*mode == 0, iclass 35, count 2 2006.202.01:43:28.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.202.01:43:28.71#ibcon#[25=AT02-07\r\n] 2006.202.01:43:28.71#ibcon#*before write, iclass 35, count 2 2006.202.01:43:28.71#ibcon#enter sib2, iclass 35, count 2 2006.202.01:43:28.71#ibcon#flushed, iclass 35, count 2 2006.202.01:43:28.71#ibcon#about to write, iclass 35, count 2 2006.202.01:43:28.71#ibcon#wrote, iclass 35, count 2 2006.202.01:43:28.71#ibcon#about to read 3, iclass 35, count 2 2006.202.01:43:28.74#ibcon#read 3, iclass 35, count 2 2006.202.01:43:28.74#ibcon#about to read 4, iclass 35, count 2 2006.202.01:43:28.74#ibcon#read 4, iclass 35, count 2 2006.202.01:43:28.74#ibcon#about to read 5, iclass 35, count 2 2006.202.01:43:28.74#ibcon#read 5, iclass 35, count 2 2006.202.01:43:28.74#ibcon#about to read 6, iclass 35, count 2 2006.202.01:43:28.74#ibcon#read 6, iclass 35, count 2 2006.202.01:43:28.74#ibcon#end of sib2, iclass 35, count 2 2006.202.01:43:28.74#ibcon#*after write, iclass 35, count 2 2006.202.01:43:28.74#ibcon#*before return 0, iclass 35, count 2 2006.202.01:43:28.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:28.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:28.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.202.01:43:28.74#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:28.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:28.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:28.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:28.86#ibcon#enter wrdev, iclass 35, count 0 2006.202.01:43:28.86#ibcon#first serial, iclass 35, count 0 2006.202.01:43:28.86#ibcon#enter sib2, iclass 35, count 0 2006.202.01:43:28.86#ibcon#flushed, iclass 35, count 0 2006.202.01:43:28.86#ibcon#about to write, iclass 35, count 0 2006.202.01:43:28.86#ibcon#wrote, iclass 35, count 0 2006.202.01:43:28.86#ibcon#about to read 3, iclass 35, count 0 2006.202.01:43:28.88#ibcon#read 3, iclass 35, count 0 2006.202.01:43:28.88#ibcon#about to read 4, iclass 35, count 0 2006.202.01:43:28.88#ibcon#read 4, iclass 35, count 0 2006.202.01:43:28.88#ibcon#about to read 5, iclass 35, count 0 2006.202.01:43:28.88#ibcon#read 5, iclass 35, count 0 2006.202.01:43:28.88#ibcon#about to read 6, iclass 35, count 0 2006.202.01:43:28.88#ibcon#read 6, iclass 35, count 0 2006.202.01:43:28.88#ibcon#end of sib2, iclass 35, count 0 2006.202.01:43:28.88#ibcon#*mode == 0, iclass 35, count 0 2006.202.01:43:28.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.01:43:28.88#ibcon#[25=USB\r\n] 2006.202.01:43:28.88#ibcon#*before write, iclass 35, count 0 2006.202.01:43:28.88#ibcon#enter sib2, iclass 35, count 0 2006.202.01:43:28.88#ibcon#flushed, iclass 35, count 0 2006.202.01:43:28.88#ibcon#about to write, iclass 35, count 0 2006.202.01:43:28.88#ibcon#wrote, iclass 35, count 0 2006.202.01:43:28.88#ibcon#about to read 3, iclass 35, count 0 2006.202.01:43:28.91#ibcon#read 3, iclass 35, count 0 2006.202.01:43:28.91#ibcon#about to read 4, iclass 35, count 0 2006.202.01:43:28.91#ibcon#read 4, iclass 35, count 0 2006.202.01:43:28.91#ibcon#about to read 5, iclass 35, count 0 2006.202.01:43:28.91#ibcon#read 5, iclass 35, count 0 2006.202.01:43:28.91#ibcon#about to read 6, iclass 35, count 0 2006.202.01:43:28.91#ibcon#read 6, iclass 35, count 0 2006.202.01:43:28.91#ibcon#end of sib2, iclass 35, count 0 2006.202.01:43:28.91#ibcon#*after write, iclass 35, count 0 2006.202.01:43:28.91#ibcon#*before return 0, iclass 35, count 0 2006.202.01:43:28.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:28.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:28.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.01:43:28.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.01:43:28.91$vck44/valo=3,564.99 2006.202.01:43:28.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.202.01:43:28.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.202.01:43:28.91#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:28.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:28.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:28.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:28.91#ibcon#enter wrdev, iclass 37, count 0 2006.202.01:43:28.91#ibcon#first serial, iclass 37, count 0 2006.202.01:43:28.91#ibcon#enter sib2, iclass 37, count 0 2006.202.01:43:28.91#ibcon#flushed, iclass 37, count 0 2006.202.01:43:28.91#ibcon#about to write, iclass 37, count 0 2006.202.01:43:28.91#ibcon#wrote, iclass 37, count 0 2006.202.01:43:28.91#ibcon#about to read 3, iclass 37, count 0 2006.202.01:43:28.93#ibcon#read 3, iclass 37, count 0 2006.202.01:43:28.93#ibcon#about to read 4, iclass 37, count 0 2006.202.01:43:28.93#ibcon#read 4, iclass 37, count 0 2006.202.01:43:28.93#ibcon#about to read 5, iclass 37, count 0 2006.202.01:43:28.93#ibcon#read 5, iclass 37, count 0 2006.202.01:43:28.93#ibcon#about to read 6, iclass 37, count 0 2006.202.01:43:28.93#ibcon#read 6, iclass 37, count 0 2006.202.01:43:28.93#ibcon#end of sib2, iclass 37, count 0 2006.202.01:43:28.93#ibcon#*mode == 0, iclass 37, count 0 2006.202.01:43:28.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.01:43:28.93#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.01:43:28.93#ibcon#*before write, iclass 37, count 0 2006.202.01:43:28.93#ibcon#enter sib2, iclass 37, count 0 2006.202.01:43:28.93#ibcon#flushed, iclass 37, count 0 2006.202.01:43:28.93#ibcon#about to write, iclass 37, count 0 2006.202.01:43:28.93#ibcon#wrote, iclass 37, count 0 2006.202.01:43:28.93#ibcon#about to read 3, iclass 37, count 0 2006.202.01:43:28.97#ibcon#read 3, iclass 37, count 0 2006.202.01:43:28.97#ibcon#about to read 4, iclass 37, count 0 2006.202.01:43:28.97#ibcon#read 4, iclass 37, count 0 2006.202.01:43:28.97#ibcon#about to read 5, iclass 37, count 0 2006.202.01:43:28.97#ibcon#read 5, iclass 37, count 0 2006.202.01:43:28.97#ibcon#about to read 6, iclass 37, count 0 2006.202.01:43:28.97#ibcon#read 6, iclass 37, count 0 2006.202.01:43:28.97#ibcon#end of sib2, iclass 37, count 0 2006.202.01:43:28.97#ibcon#*after write, iclass 37, count 0 2006.202.01:43:28.97#ibcon#*before return 0, iclass 37, count 0 2006.202.01:43:28.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:28.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:28.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.01:43:28.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.01:43:28.97$vck44/va=3,8 2006.202.01:43:28.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.202.01:43:28.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.202.01:43:28.97#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:28.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:29.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:29.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:29.03#ibcon#enter wrdev, iclass 39, count 2 2006.202.01:43:29.03#ibcon#first serial, iclass 39, count 2 2006.202.01:43:29.03#ibcon#enter sib2, iclass 39, count 2 2006.202.01:43:29.03#ibcon#flushed, iclass 39, count 2 2006.202.01:43:29.03#ibcon#about to write, iclass 39, count 2 2006.202.01:43:29.03#ibcon#wrote, iclass 39, count 2 2006.202.01:43:29.03#ibcon#about to read 3, iclass 39, count 2 2006.202.01:43:29.05#ibcon#read 3, iclass 39, count 2 2006.202.01:43:29.05#ibcon#about to read 4, iclass 39, count 2 2006.202.01:43:29.05#ibcon#read 4, iclass 39, count 2 2006.202.01:43:29.05#ibcon#about to read 5, iclass 39, count 2 2006.202.01:43:29.05#ibcon#read 5, iclass 39, count 2 2006.202.01:43:29.05#ibcon#about to read 6, iclass 39, count 2 2006.202.01:43:29.05#ibcon#read 6, iclass 39, count 2 2006.202.01:43:29.05#ibcon#end of sib2, iclass 39, count 2 2006.202.01:43:29.05#ibcon#*mode == 0, iclass 39, count 2 2006.202.01:43:29.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.202.01:43:29.05#ibcon#[25=AT03-08\r\n] 2006.202.01:43:29.05#ibcon#*before write, iclass 39, count 2 2006.202.01:43:29.05#ibcon#enter sib2, iclass 39, count 2 2006.202.01:43:29.05#ibcon#flushed, iclass 39, count 2 2006.202.01:43:29.05#ibcon#about to write, iclass 39, count 2 2006.202.01:43:29.05#ibcon#wrote, iclass 39, count 2 2006.202.01:43:29.05#ibcon#about to read 3, iclass 39, count 2 2006.202.01:43:29.08#ibcon#read 3, iclass 39, count 2 2006.202.01:43:29.08#ibcon#about to read 4, iclass 39, count 2 2006.202.01:43:29.08#ibcon#read 4, iclass 39, count 2 2006.202.01:43:29.08#ibcon#about to read 5, iclass 39, count 2 2006.202.01:43:29.08#ibcon#read 5, iclass 39, count 2 2006.202.01:43:29.08#ibcon#about to read 6, iclass 39, count 2 2006.202.01:43:29.08#ibcon#read 6, iclass 39, count 2 2006.202.01:43:29.08#ibcon#end of sib2, iclass 39, count 2 2006.202.01:43:29.08#ibcon#*after write, iclass 39, count 2 2006.202.01:43:29.08#ibcon#*before return 0, iclass 39, count 2 2006.202.01:43:29.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:29.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:29.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.202.01:43:29.08#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:29.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:29.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:29.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:29.20#ibcon#enter wrdev, iclass 39, count 0 2006.202.01:43:29.20#ibcon#first serial, iclass 39, count 0 2006.202.01:43:29.20#ibcon#enter sib2, iclass 39, count 0 2006.202.01:43:29.20#ibcon#flushed, iclass 39, count 0 2006.202.01:43:29.20#ibcon#about to write, iclass 39, count 0 2006.202.01:43:29.20#ibcon#wrote, iclass 39, count 0 2006.202.01:43:29.20#ibcon#about to read 3, iclass 39, count 0 2006.202.01:43:29.22#ibcon#read 3, iclass 39, count 0 2006.202.01:43:29.22#ibcon#about to read 4, iclass 39, count 0 2006.202.01:43:29.22#ibcon#read 4, iclass 39, count 0 2006.202.01:43:29.22#ibcon#about to read 5, iclass 39, count 0 2006.202.01:43:29.22#ibcon#read 5, iclass 39, count 0 2006.202.01:43:29.22#ibcon#about to read 6, iclass 39, count 0 2006.202.01:43:29.22#ibcon#read 6, iclass 39, count 0 2006.202.01:43:29.22#ibcon#end of sib2, iclass 39, count 0 2006.202.01:43:29.22#ibcon#*mode == 0, iclass 39, count 0 2006.202.01:43:29.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.01:43:29.22#ibcon#[25=USB\r\n] 2006.202.01:43:29.22#ibcon#*before write, iclass 39, count 0 2006.202.01:43:29.22#ibcon#enter sib2, iclass 39, count 0 2006.202.01:43:29.22#ibcon#flushed, iclass 39, count 0 2006.202.01:43:29.22#ibcon#about to write, iclass 39, count 0 2006.202.01:43:29.22#ibcon#wrote, iclass 39, count 0 2006.202.01:43:29.22#ibcon#about to read 3, iclass 39, count 0 2006.202.01:43:29.25#ibcon#read 3, iclass 39, count 0 2006.202.01:43:29.25#ibcon#about to read 4, iclass 39, count 0 2006.202.01:43:29.25#ibcon#read 4, iclass 39, count 0 2006.202.01:43:29.25#ibcon#about to read 5, iclass 39, count 0 2006.202.01:43:29.25#ibcon#read 5, iclass 39, count 0 2006.202.01:43:29.25#ibcon#about to read 6, iclass 39, count 0 2006.202.01:43:29.25#ibcon#read 6, iclass 39, count 0 2006.202.01:43:29.25#ibcon#end of sib2, iclass 39, count 0 2006.202.01:43:29.25#ibcon#*after write, iclass 39, count 0 2006.202.01:43:29.25#ibcon#*before return 0, iclass 39, count 0 2006.202.01:43:29.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:29.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:29.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.01:43:29.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.01:43:29.25$vck44/valo=4,624.99 2006.202.01:43:29.25#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.202.01:43:29.25#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.202.01:43:29.25#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:29.25#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:29.25#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:29.25#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:29.25#ibcon#enter wrdev, iclass 2, count 0 2006.202.01:43:29.25#ibcon#first serial, iclass 2, count 0 2006.202.01:43:29.25#ibcon#enter sib2, iclass 2, count 0 2006.202.01:43:29.25#ibcon#flushed, iclass 2, count 0 2006.202.01:43:29.25#ibcon#about to write, iclass 2, count 0 2006.202.01:43:29.25#ibcon#wrote, iclass 2, count 0 2006.202.01:43:29.25#ibcon#about to read 3, iclass 2, count 0 2006.202.01:43:29.27#ibcon#read 3, iclass 2, count 0 2006.202.01:43:29.27#ibcon#about to read 4, iclass 2, count 0 2006.202.01:43:29.27#ibcon#read 4, iclass 2, count 0 2006.202.01:43:29.27#ibcon#about to read 5, iclass 2, count 0 2006.202.01:43:29.27#ibcon#read 5, iclass 2, count 0 2006.202.01:43:29.27#ibcon#about to read 6, iclass 2, count 0 2006.202.01:43:29.27#ibcon#read 6, iclass 2, count 0 2006.202.01:43:29.27#ibcon#end of sib2, iclass 2, count 0 2006.202.01:43:29.27#ibcon#*mode == 0, iclass 2, count 0 2006.202.01:43:29.27#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.01:43:29.27#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.01:43:29.27#ibcon#*before write, iclass 2, count 0 2006.202.01:43:29.27#ibcon#enter sib2, iclass 2, count 0 2006.202.01:43:29.27#ibcon#flushed, iclass 2, count 0 2006.202.01:43:29.27#ibcon#about to write, iclass 2, count 0 2006.202.01:43:29.27#ibcon#wrote, iclass 2, count 0 2006.202.01:43:29.27#ibcon#about to read 3, iclass 2, count 0 2006.202.01:43:29.31#ibcon#read 3, iclass 2, count 0 2006.202.01:43:29.31#ibcon#about to read 4, iclass 2, count 0 2006.202.01:43:29.31#ibcon#read 4, iclass 2, count 0 2006.202.01:43:29.31#ibcon#about to read 5, iclass 2, count 0 2006.202.01:43:29.31#ibcon#read 5, iclass 2, count 0 2006.202.01:43:29.31#ibcon#about to read 6, iclass 2, count 0 2006.202.01:43:29.31#ibcon#read 6, iclass 2, count 0 2006.202.01:43:29.31#ibcon#end of sib2, iclass 2, count 0 2006.202.01:43:29.31#ibcon#*after write, iclass 2, count 0 2006.202.01:43:29.31#ibcon#*before return 0, iclass 2, count 0 2006.202.01:43:29.31#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:29.31#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:29.31#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.01:43:29.31#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.01:43:29.31$vck44/va=4,7 2006.202.01:43:29.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.202.01:43:29.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.202.01:43:29.31#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:29.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:29.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:29.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:29.37#ibcon#enter wrdev, iclass 5, count 2 2006.202.01:43:29.37#ibcon#first serial, iclass 5, count 2 2006.202.01:43:29.37#ibcon#enter sib2, iclass 5, count 2 2006.202.01:43:29.37#ibcon#flushed, iclass 5, count 2 2006.202.01:43:29.37#ibcon#about to write, iclass 5, count 2 2006.202.01:43:29.37#ibcon#wrote, iclass 5, count 2 2006.202.01:43:29.37#ibcon#about to read 3, iclass 5, count 2 2006.202.01:43:29.39#ibcon#read 3, iclass 5, count 2 2006.202.01:43:29.39#ibcon#about to read 4, iclass 5, count 2 2006.202.01:43:29.39#ibcon#read 4, iclass 5, count 2 2006.202.01:43:29.39#ibcon#about to read 5, iclass 5, count 2 2006.202.01:43:29.39#ibcon#read 5, iclass 5, count 2 2006.202.01:43:29.39#ibcon#about to read 6, iclass 5, count 2 2006.202.01:43:29.39#ibcon#read 6, iclass 5, count 2 2006.202.01:43:29.39#ibcon#end of sib2, iclass 5, count 2 2006.202.01:43:29.39#ibcon#*mode == 0, iclass 5, count 2 2006.202.01:43:29.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.202.01:43:29.39#ibcon#[25=AT04-07\r\n] 2006.202.01:43:29.39#ibcon#*before write, iclass 5, count 2 2006.202.01:43:29.39#ibcon#enter sib2, iclass 5, count 2 2006.202.01:43:29.39#ibcon#flushed, iclass 5, count 2 2006.202.01:43:29.39#ibcon#about to write, iclass 5, count 2 2006.202.01:43:29.39#ibcon#wrote, iclass 5, count 2 2006.202.01:43:29.39#ibcon#about to read 3, iclass 5, count 2 2006.202.01:43:29.42#ibcon#read 3, iclass 5, count 2 2006.202.01:43:29.42#ibcon#about to read 4, iclass 5, count 2 2006.202.01:43:29.42#ibcon#read 4, iclass 5, count 2 2006.202.01:43:29.42#ibcon#about to read 5, iclass 5, count 2 2006.202.01:43:29.42#ibcon#read 5, iclass 5, count 2 2006.202.01:43:29.42#ibcon#about to read 6, iclass 5, count 2 2006.202.01:43:29.42#ibcon#read 6, iclass 5, count 2 2006.202.01:43:29.42#ibcon#end of sib2, iclass 5, count 2 2006.202.01:43:29.42#ibcon#*after write, iclass 5, count 2 2006.202.01:43:29.42#ibcon#*before return 0, iclass 5, count 2 2006.202.01:43:29.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:29.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:29.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.202.01:43:29.42#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:29.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:29.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:29.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:29.54#ibcon#enter wrdev, iclass 5, count 0 2006.202.01:43:29.54#ibcon#first serial, iclass 5, count 0 2006.202.01:43:29.54#ibcon#enter sib2, iclass 5, count 0 2006.202.01:43:29.54#ibcon#flushed, iclass 5, count 0 2006.202.01:43:29.54#ibcon#about to write, iclass 5, count 0 2006.202.01:43:29.54#ibcon#wrote, iclass 5, count 0 2006.202.01:43:29.54#ibcon#about to read 3, iclass 5, count 0 2006.202.01:43:29.56#ibcon#read 3, iclass 5, count 0 2006.202.01:43:29.56#ibcon#about to read 4, iclass 5, count 0 2006.202.01:43:29.56#ibcon#read 4, iclass 5, count 0 2006.202.01:43:29.56#ibcon#about to read 5, iclass 5, count 0 2006.202.01:43:29.56#ibcon#read 5, iclass 5, count 0 2006.202.01:43:29.56#ibcon#about to read 6, iclass 5, count 0 2006.202.01:43:29.56#ibcon#read 6, iclass 5, count 0 2006.202.01:43:29.56#ibcon#end of sib2, iclass 5, count 0 2006.202.01:43:29.56#ibcon#*mode == 0, iclass 5, count 0 2006.202.01:43:29.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.01:43:29.56#ibcon#[25=USB\r\n] 2006.202.01:43:29.56#ibcon#*before write, iclass 5, count 0 2006.202.01:43:29.56#ibcon#enter sib2, iclass 5, count 0 2006.202.01:43:29.56#ibcon#flushed, iclass 5, count 0 2006.202.01:43:29.56#ibcon#about to write, iclass 5, count 0 2006.202.01:43:29.56#ibcon#wrote, iclass 5, count 0 2006.202.01:43:29.56#ibcon#about to read 3, iclass 5, count 0 2006.202.01:43:29.59#ibcon#read 3, iclass 5, count 0 2006.202.01:43:29.59#ibcon#about to read 4, iclass 5, count 0 2006.202.01:43:29.59#ibcon#read 4, iclass 5, count 0 2006.202.01:43:29.59#ibcon#about to read 5, iclass 5, count 0 2006.202.01:43:29.59#ibcon#read 5, iclass 5, count 0 2006.202.01:43:29.59#ibcon#about to read 6, iclass 5, count 0 2006.202.01:43:29.59#ibcon#read 6, iclass 5, count 0 2006.202.01:43:29.59#ibcon#end of sib2, iclass 5, count 0 2006.202.01:43:29.59#ibcon#*after write, iclass 5, count 0 2006.202.01:43:29.59#ibcon#*before return 0, iclass 5, count 0 2006.202.01:43:29.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:29.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:29.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.01:43:29.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.01:43:29.59$vck44/valo=5,734.99 2006.202.01:43:29.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.01:43:29.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.01:43:29.59#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:29.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:29.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:29.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:29.59#ibcon#enter wrdev, iclass 7, count 0 2006.202.01:43:29.59#ibcon#first serial, iclass 7, count 0 2006.202.01:43:29.59#ibcon#enter sib2, iclass 7, count 0 2006.202.01:43:29.59#ibcon#flushed, iclass 7, count 0 2006.202.01:43:29.59#ibcon#about to write, iclass 7, count 0 2006.202.01:43:29.59#ibcon#wrote, iclass 7, count 0 2006.202.01:43:29.59#ibcon#about to read 3, iclass 7, count 0 2006.202.01:43:29.61#ibcon#read 3, iclass 7, count 0 2006.202.01:43:29.61#ibcon#about to read 4, iclass 7, count 0 2006.202.01:43:29.61#ibcon#read 4, iclass 7, count 0 2006.202.01:43:29.61#ibcon#about to read 5, iclass 7, count 0 2006.202.01:43:29.61#ibcon#read 5, iclass 7, count 0 2006.202.01:43:29.61#ibcon#about to read 6, iclass 7, count 0 2006.202.01:43:29.61#ibcon#read 6, iclass 7, count 0 2006.202.01:43:29.61#ibcon#end of sib2, iclass 7, count 0 2006.202.01:43:29.61#ibcon#*mode == 0, iclass 7, count 0 2006.202.01:43:29.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.01:43:29.61#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.01:43:29.61#ibcon#*before write, iclass 7, count 0 2006.202.01:43:29.61#ibcon#enter sib2, iclass 7, count 0 2006.202.01:43:29.61#ibcon#flushed, iclass 7, count 0 2006.202.01:43:29.61#ibcon#about to write, iclass 7, count 0 2006.202.01:43:29.61#ibcon#wrote, iclass 7, count 0 2006.202.01:43:29.61#ibcon#about to read 3, iclass 7, count 0 2006.202.01:43:29.65#ibcon#read 3, iclass 7, count 0 2006.202.01:43:29.65#ibcon#about to read 4, iclass 7, count 0 2006.202.01:43:29.65#ibcon#read 4, iclass 7, count 0 2006.202.01:43:29.65#ibcon#about to read 5, iclass 7, count 0 2006.202.01:43:29.65#ibcon#read 5, iclass 7, count 0 2006.202.01:43:29.65#ibcon#about to read 6, iclass 7, count 0 2006.202.01:43:29.65#ibcon#read 6, iclass 7, count 0 2006.202.01:43:29.65#ibcon#end of sib2, iclass 7, count 0 2006.202.01:43:29.65#ibcon#*after write, iclass 7, count 0 2006.202.01:43:29.65#ibcon#*before return 0, iclass 7, count 0 2006.202.01:43:29.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:29.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:29.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.01:43:29.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.01:43:29.65$vck44/va=5,4 2006.202.01:43:29.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.202.01:43:29.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.202.01:43:29.65#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:29.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:29.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:29.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:29.71#ibcon#enter wrdev, iclass 11, count 2 2006.202.01:43:29.71#ibcon#first serial, iclass 11, count 2 2006.202.01:43:29.71#ibcon#enter sib2, iclass 11, count 2 2006.202.01:43:29.71#ibcon#flushed, iclass 11, count 2 2006.202.01:43:29.71#ibcon#about to write, iclass 11, count 2 2006.202.01:43:29.71#ibcon#wrote, iclass 11, count 2 2006.202.01:43:29.71#ibcon#about to read 3, iclass 11, count 2 2006.202.01:43:29.73#ibcon#read 3, iclass 11, count 2 2006.202.01:43:29.73#ibcon#about to read 4, iclass 11, count 2 2006.202.01:43:29.73#ibcon#read 4, iclass 11, count 2 2006.202.01:43:29.73#ibcon#about to read 5, iclass 11, count 2 2006.202.01:43:29.73#ibcon#read 5, iclass 11, count 2 2006.202.01:43:29.73#ibcon#about to read 6, iclass 11, count 2 2006.202.01:43:29.73#ibcon#read 6, iclass 11, count 2 2006.202.01:43:29.73#ibcon#end of sib2, iclass 11, count 2 2006.202.01:43:29.73#ibcon#*mode == 0, iclass 11, count 2 2006.202.01:43:29.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.202.01:43:29.73#ibcon#[25=AT05-04\r\n] 2006.202.01:43:29.73#ibcon#*before write, iclass 11, count 2 2006.202.01:43:29.73#ibcon#enter sib2, iclass 11, count 2 2006.202.01:43:29.73#ibcon#flushed, iclass 11, count 2 2006.202.01:43:29.73#ibcon#about to write, iclass 11, count 2 2006.202.01:43:29.73#ibcon#wrote, iclass 11, count 2 2006.202.01:43:29.73#ibcon#about to read 3, iclass 11, count 2 2006.202.01:43:29.76#ibcon#read 3, iclass 11, count 2 2006.202.01:43:29.76#ibcon#about to read 4, iclass 11, count 2 2006.202.01:43:29.76#ibcon#read 4, iclass 11, count 2 2006.202.01:43:29.76#ibcon#about to read 5, iclass 11, count 2 2006.202.01:43:29.76#ibcon#read 5, iclass 11, count 2 2006.202.01:43:29.76#ibcon#about to read 6, iclass 11, count 2 2006.202.01:43:29.76#ibcon#read 6, iclass 11, count 2 2006.202.01:43:29.76#ibcon#end of sib2, iclass 11, count 2 2006.202.01:43:29.76#ibcon#*after write, iclass 11, count 2 2006.202.01:43:29.76#ibcon#*before return 0, iclass 11, count 2 2006.202.01:43:29.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:29.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:29.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.202.01:43:29.76#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:29.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:29.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:29.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:29.88#ibcon#enter wrdev, iclass 11, count 0 2006.202.01:43:29.88#ibcon#first serial, iclass 11, count 0 2006.202.01:43:29.88#ibcon#enter sib2, iclass 11, count 0 2006.202.01:43:29.88#ibcon#flushed, iclass 11, count 0 2006.202.01:43:29.88#ibcon#about to write, iclass 11, count 0 2006.202.01:43:29.88#ibcon#wrote, iclass 11, count 0 2006.202.01:43:29.88#ibcon#about to read 3, iclass 11, count 0 2006.202.01:43:29.90#ibcon#read 3, iclass 11, count 0 2006.202.01:43:29.90#ibcon#about to read 4, iclass 11, count 0 2006.202.01:43:29.90#ibcon#read 4, iclass 11, count 0 2006.202.01:43:29.90#ibcon#about to read 5, iclass 11, count 0 2006.202.01:43:29.90#ibcon#read 5, iclass 11, count 0 2006.202.01:43:29.90#ibcon#about to read 6, iclass 11, count 0 2006.202.01:43:29.90#ibcon#read 6, iclass 11, count 0 2006.202.01:43:29.90#ibcon#end of sib2, iclass 11, count 0 2006.202.01:43:29.90#ibcon#*mode == 0, iclass 11, count 0 2006.202.01:43:29.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.01:43:29.90#ibcon#[25=USB\r\n] 2006.202.01:43:29.90#ibcon#*before write, iclass 11, count 0 2006.202.01:43:29.90#ibcon#enter sib2, iclass 11, count 0 2006.202.01:43:29.90#ibcon#flushed, iclass 11, count 0 2006.202.01:43:29.90#ibcon#about to write, iclass 11, count 0 2006.202.01:43:29.90#ibcon#wrote, iclass 11, count 0 2006.202.01:43:29.90#ibcon#about to read 3, iclass 11, count 0 2006.202.01:43:29.93#ibcon#read 3, iclass 11, count 0 2006.202.01:43:29.93#ibcon#about to read 4, iclass 11, count 0 2006.202.01:43:29.93#ibcon#read 4, iclass 11, count 0 2006.202.01:43:29.93#ibcon#about to read 5, iclass 11, count 0 2006.202.01:43:29.93#ibcon#read 5, iclass 11, count 0 2006.202.01:43:29.93#ibcon#about to read 6, iclass 11, count 0 2006.202.01:43:29.93#ibcon#read 6, iclass 11, count 0 2006.202.01:43:29.93#ibcon#end of sib2, iclass 11, count 0 2006.202.01:43:29.93#ibcon#*after write, iclass 11, count 0 2006.202.01:43:29.93#ibcon#*before return 0, iclass 11, count 0 2006.202.01:43:29.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:29.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:29.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.01:43:29.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.01:43:29.93$vck44/valo=6,814.99 2006.202.01:43:29.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.202.01:43:29.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.202.01:43:29.93#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:29.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:29.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:29.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:29.93#ibcon#enter wrdev, iclass 13, count 0 2006.202.01:43:29.93#ibcon#first serial, iclass 13, count 0 2006.202.01:43:29.93#ibcon#enter sib2, iclass 13, count 0 2006.202.01:43:29.93#ibcon#flushed, iclass 13, count 0 2006.202.01:43:29.93#ibcon#about to write, iclass 13, count 0 2006.202.01:43:29.93#ibcon#wrote, iclass 13, count 0 2006.202.01:43:29.93#ibcon#about to read 3, iclass 13, count 0 2006.202.01:43:29.95#ibcon#read 3, iclass 13, count 0 2006.202.01:43:29.95#ibcon#about to read 4, iclass 13, count 0 2006.202.01:43:29.95#ibcon#read 4, iclass 13, count 0 2006.202.01:43:29.95#ibcon#about to read 5, iclass 13, count 0 2006.202.01:43:29.95#ibcon#read 5, iclass 13, count 0 2006.202.01:43:29.95#ibcon#about to read 6, iclass 13, count 0 2006.202.01:43:29.95#ibcon#read 6, iclass 13, count 0 2006.202.01:43:29.95#ibcon#end of sib2, iclass 13, count 0 2006.202.01:43:29.95#ibcon#*mode == 0, iclass 13, count 0 2006.202.01:43:29.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.01:43:29.95#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.01:43:29.95#ibcon#*before write, iclass 13, count 0 2006.202.01:43:29.95#ibcon#enter sib2, iclass 13, count 0 2006.202.01:43:29.95#ibcon#flushed, iclass 13, count 0 2006.202.01:43:29.95#ibcon#about to write, iclass 13, count 0 2006.202.01:43:29.95#ibcon#wrote, iclass 13, count 0 2006.202.01:43:29.95#ibcon#about to read 3, iclass 13, count 0 2006.202.01:43:29.99#ibcon#read 3, iclass 13, count 0 2006.202.01:43:29.99#ibcon#about to read 4, iclass 13, count 0 2006.202.01:43:29.99#ibcon#read 4, iclass 13, count 0 2006.202.01:43:29.99#ibcon#about to read 5, iclass 13, count 0 2006.202.01:43:29.99#ibcon#read 5, iclass 13, count 0 2006.202.01:43:29.99#ibcon#about to read 6, iclass 13, count 0 2006.202.01:43:29.99#ibcon#read 6, iclass 13, count 0 2006.202.01:43:29.99#ibcon#end of sib2, iclass 13, count 0 2006.202.01:43:29.99#ibcon#*after write, iclass 13, count 0 2006.202.01:43:29.99#ibcon#*before return 0, iclass 13, count 0 2006.202.01:43:29.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:29.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:29.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.01:43:29.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.01:43:29.99$vck44/va=6,5 2006.202.01:43:29.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.202.01:43:29.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.202.01:43:29.99#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:29.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:30.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:30.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:30.05#ibcon#enter wrdev, iclass 15, count 2 2006.202.01:43:30.05#ibcon#first serial, iclass 15, count 2 2006.202.01:43:30.05#ibcon#enter sib2, iclass 15, count 2 2006.202.01:43:30.05#ibcon#flushed, iclass 15, count 2 2006.202.01:43:30.05#ibcon#about to write, iclass 15, count 2 2006.202.01:43:30.05#ibcon#wrote, iclass 15, count 2 2006.202.01:43:30.05#ibcon#about to read 3, iclass 15, count 2 2006.202.01:43:30.07#ibcon#read 3, iclass 15, count 2 2006.202.01:43:30.07#ibcon#about to read 4, iclass 15, count 2 2006.202.01:43:30.07#ibcon#read 4, iclass 15, count 2 2006.202.01:43:30.07#ibcon#about to read 5, iclass 15, count 2 2006.202.01:43:30.07#ibcon#read 5, iclass 15, count 2 2006.202.01:43:30.07#ibcon#about to read 6, iclass 15, count 2 2006.202.01:43:30.07#ibcon#read 6, iclass 15, count 2 2006.202.01:43:30.07#ibcon#end of sib2, iclass 15, count 2 2006.202.01:43:30.07#ibcon#*mode == 0, iclass 15, count 2 2006.202.01:43:30.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.202.01:43:30.07#ibcon#[25=AT06-05\r\n] 2006.202.01:43:30.07#ibcon#*before write, iclass 15, count 2 2006.202.01:43:30.07#ibcon#enter sib2, iclass 15, count 2 2006.202.01:43:30.07#ibcon#flushed, iclass 15, count 2 2006.202.01:43:30.07#ibcon#about to write, iclass 15, count 2 2006.202.01:43:30.07#ibcon#wrote, iclass 15, count 2 2006.202.01:43:30.07#ibcon#about to read 3, iclass 15, count 2 2006.202.01:43:30.10#ibcon#read 3, iclass 15, count 2 2006.202.01:43:30.10#ibcon#about to read 4, iclass 15, count 2 2006.202.01:43:30.10#ibcon#read 4, iclass 15, count 2 2006.202.01:43:30.10#ibcon#about to read 5, iclass 15, count 2 2006.202.01:43:30.10#ibcon#read 5, iclass 15, count 2 2006.202.01:43:30.10#ibcon#about to read 6, iclass 15, count 2 2006.202.01:43:30.10#ibcon#read 6, iclass 15, count 2 2006.202.01:43:30.10#ibcon#end of sib2, iclass 15, count 2 2006.202.01:43:30.10#ibcon#*after write, iclass 15, count 2 2006.202.01:43:30.10#ibcon#*before return 0, iclass 15, count 2 2006.202.01:43:30.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:30.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:30.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.202.01:43:30.10#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:30.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:30.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:30.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:30.22#ibcon#enter wrdev, iclass 15, count 0 2006.202.01:43:30.22#ibcon#first serial, iclass 15, count 0 2006.202.01:43:30.22#ibcon#enter sib2, iclass 15, count 0 2006.202.01:43:30.22#ibcon#flushed, iclass 15, count 0 2006.202.01:43:30.22#ibcon#about to write, iclass 15, count 0 2006.202.01:43:30.22#ibcon#wrote, iclass 15, count 0 2006.202.01:43:30.22#ibcon#about to read 3, iclass 15, count 0 2006.202.01:43:30.24#ibcon#read 3, iclass 15, count 0 2006.202.01:43:30.24#ibcon#about to read 4, iclass 15, count 0 2006.202.01:43:30.24#ibcon#read 4, iclass 15, count 0 2006.202.01:43:30.24#ibcon#about to read 5, iclass 15, count 0 2006.202.01:43:30.24#ibcon#read 5, iclass 15, count 0 2006.202.01:43:30.24#ibcon#about to read 6, iclass 15, count 0 2006.202.01:43:30.24#ibcon#read 6, iclass 15, count 0 2006.202.01:43:30.24#ibcon#end of sib2, iclass 15, count 0 2006.202.01:43:30.24#ibcon#*mode == 0, iclass 15, count 0 2006.202.01:43:30.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.01:43:30.24#ibcon#[25=USB\r\n] 2006.202.01:43:30.24#ibcon#*before write, iclass 15, count 0 2006.202.01:43:30.24#ibcon#enter sib2, iclass 15, count 0 2006.202.01:43:30.24#ibcon#flushed, iclass 15, count 0 2006.202.01:43:30.24#ibcon#about to write, iclass 15, count 0 2006.202.01:43:30.24#ibcon#wrote, iclass 15, count 0 2006.202.01:43:30.24#ibcon#about to read 3, iclass 15, count 0 2006.202.01:43:30.27#ibcon#read 3, iclass 15, count 0 2006.202.01:43:30.27#ibcon#about to read 4, iclass 15, count 0 2006.202.01:43:30.27#ibcon#read 4, iclass 15, count 0 2006.202.01:43:30.27#ibcon#about to read 5, iclass 15, count 0 2006.202.01:43:30.27#ibcon#read 5, iclass 15, count 0 2006.202.01:43:30.27#ibcon#about to read 6, iclass 15, count 0 2006.202.01:43:30.27#ibcon#read 6, iclass 15, count 0 2006.202.01:43:30.27#ibcon#end of sib2, iclass 15, count 0 2006.202.01:43:30.27#ibcon#*after write, iclass 15, count 0 2006.202.01:43:30.27#ibcon#*before return 0, iclass 15, count 0 2006.202.01:43:30.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:30.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:30.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.01:43:30.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.01:43:30.27$vck44/valo=7,864.99 2006.202.01:43:30.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.01:43:30.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.01:43:30.27#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:30.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:30.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:30.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:30.27#ibcon#enter wrdev, iclass 17, count 0 2006.202.01:43:30.27#ibcon#first serial, iclass 17, count 0 2006.202.01:43:30.27#ibcon#enter sib2, iclass 17, count 0 2006.202.01:43:30.27#ibcon#flushed, iclass 17, count 0 2006.202.01:43:30.27#ibcon#about to write, iclass 17, count 0 2006.202.01:43:30.27#ibcon#wrote, iclass 17, count 0 2006.202.01:43:30.27#ibcon#about to read 3, iclass 17, count 0 2006.202.01:43:30.29#ibcon#read 3, iclass 17, count 0 2006.202.01:43:30.29#ibcon#about to read 4, iclass 17, count 0 2006.202.01:43:30.29#ibcon#read 4, iclass 17, count 0 2006.202.01:43:30.29#ibcon#about to read 5, iclass 17, count 0 2006.202.01:43:30.29#ibcon#read 5, iclass 17, count 0 2006.202.01:43:30.29#ibcon#about to read 6, iclass 17, count 0 2006.202.01:43:30.29#ibcon#read 6, iclass 17, count 0 2006.202.01:43:30.29#ibcon#end of sib2, iclass 17, count 0 2006.202.01:43:30.29#ibcon#*mode == 0, iclass 17, count 0 2006.202.01:43:30.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.01:43:30.29#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.01:43:30.29#ibcon#*before write, iclass 17, count 0 2006.202.01:43:30.29#ibcon#enter sib2, iclass 17, count 0 2006.202.01:43:30.29#ibcon#flushed, iclass 17, count 0 2006.202.01:43:30.29#ibcon#about to write, iclass 17, count 0 2006.202.01:43:30.29#ibcon#wrote, iclass 17, count 0 2006.202.01:43:30.29#ibcon#about to read 3, iclass 17, count 0 2006.202.01:43:30.33#ibcon#read 3, iclass 17, count 0 2006.202.01:43:30.33#ibcon#about to read 4, iclass 17, count 0 2006.202.01:43:30.33#ibcon#read 4, iclass 17, count 0 2006.202.01:43:30.33#ibcon#about to read 5, iclass 17, count 0 2006.202.01:43:30.33#ibcon#read 5, iclass 17, count 0 2006.202.01:43:30.33#ibcon#about to read 6, iclass 17, count 0 2006.202.01:43:30.33#ibcon#read 6, iclass 17, count 0 2006.202.01:43:30.33#ibcon#end of sib2, iclass 17, count 0 2006.202.01:43:30.33#ibcon#*after write, iclass 17, count 0 2006.202.01:43:30.33#ibcon#*before return 0, iclass 17, count 0 2006.202.01:43:30.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:30.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:30.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.01:43:30.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.01:43:30.33$vck44/va=7,5 2006.202.01:43:30.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.202.01:43:30.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.202.01:43:30.33#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:30.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:30.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:30.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:30.39#ibcon#enter wrdev, iclass 19, count 2 2006.202.01:43:30.39#ibcon#first serial, iclass 19, count 2 2006.202.01:43:30.39#ibcon#enter sib2, iclass 19, count 2 2006.202.01:43:30.39#ibcon#flushed, iclass 19, count 2 2006.202.01:43:30.39#ibcon#about to write, iclass 19, count 2 2006.202.01:43:30.39#ibcon#wrote, iclass 19, count 2 2006.202.01:43:30.39#ibcon#about to read 3, iclass 19, count 2 2006.202.01:43:30.41#ibcon#read 3, iclass 19, count 2 2006.202.01:43:30.41#ibcon#about to read 4, iclass 19, count 2 2006.202.01:43:30.41#ibcon#read 4, iclass 19, count 2 2006.202.01:43:30.41#ibcon#about to read 5, iclass 19, count 2 2006.202.01:43:30.41#ibcon#read 5, iclass 19, count 2 2006.202.01:43:30.41#ibcon#about to read 6, iclass 19, count 2 2006.202.01:43:30.41#ibcon#read 6, iclass 19, count 2 2006.202.01:43:30.41#ibcon#end of sib2, iclass 19, count 2 2006.202.01:43:30.41#ibcon#*mode == 0, iclass 19, count 2 2006.202.01:43:30.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.202.01:43:30.41#ibcon#[25=AT07-05\r\n] 2006.202.01:43:30.41#ibcon#*before write, iclass 19, count 2 2006.202.01:43:30.41#ibcon#enter sib2, iclass 19, count 2 2006.202.01:43:30.41#ibcon#flushed, iclass 19, count 2 2006.202.01:43:30.41#ibcon#about to write, iclass 19, count 2 2006.202.01:43:30.41#ibcon#wrote, iclass 19, count 2 2006.202.01:43:30.41#ibcon#about to read 3, iclass 19, count 2 2006.202.01:43:30.44#ibcon#read 3, iclass 19, count 2 2006.202.01:43:30.44#ibcon#about to read 4, iclass 19, count 2 2006.202.01:43:30.44#ibcon#read 4, iclass 19, count 2 2006.202.01:43:30.44#ibcon#about to read 5, iclass 19, count 2 2006.202.01:43:30.44#ibcon#read 5, iclass 19, count 2 2006.202.01:43:30.44#ibcon#about to read 6, iclass 19, count 2 2006.202.01:43:30.44#ibcon#read 6, iclass 19, count 2 2006.202.01:43:30.44#ibcon#end of sib2, iclass 19, count 2 2006.202.01:43:30.44#ibcon#*after write, iclass 19, count 2 2006.202.01:43:30.44#ibcon#*before return 0, iclass 19, count 2 2006.202.01:43:30.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:30.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:30.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.202.01:43:30.44#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:30.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:30.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:30.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:30.56#ibcon#enter wrdev, iclass 19, count 0 2006.202.01:43:30.56#ibcon#first serial, iclass 19, count 0 2006.202.01:43:30.56#ibcon#enter sib2, iclass 19, count 0 2006.202.01:43:30.56#ibcon#flushed, iclass 19, count 0 2006.202.01:43:30.56#ibcon#about to write, iclass 19, count 0 2006.202.01:43:30.56#ibcon#wrote, iclass 19, count 0 2006.202.01:43:30.56#ibcon#about to read 3, iclass 19, count 0 2006.202.01:43:30.58#ibcon#read 3, iclass 19, count 0 2006.202.01:43:30.58#ibcon#about to read 4, iclass 19, count 0 2006.202.01:43:30.58#ibcon#read 4, iclass 19, count 0 2006.202.01:43:30.58#ibcon#about to read 5, iclass 19, count 0 2006.202.01:43:30.58#ibcon#read 5, iclass 19, count 0 2006.202.01:43:30.58#ibcon#about to read 6, iclass 19, count 0 2006.202.01:43:30.58#ibcon#read 6, iclass 19, count 0 2006.202.01:43:30.58#ibcon#end of sib2, iclass 19, count 0 2006.202.01:43:30.58#ibcon#*mode == 0, iclass 19, count 0 2006.202.01:43:30.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.01:43:30.58#ibcon#[25=USB\r\n] 2006.202.01:43:30.58#ibcon#*before write, iclass 19, count 0 2006.202.01:43:30.58#ibcon#enter sib2, iclass 19, count 0 2006.202.01:43:30.58#ibcon#flushed, iclass 19, count 0 2006.202.01:43:30.58#ibcon#about to write, iclass 19, count 0 2006.202.01:43:30.58#ibcon#wrote, iclass 19, count 0 2006.202.01:43:30.58#ibcon#about to read 3, iclass 19, count 0 2006.202.01:43:30.61#ibcon#read 3, iclass 19, count 0 2006.202.01:43:30.61#ibcon#about to read 4, iclass 19, count 0 2006.202.01:43:30.61#ibcon#read 4, iclass 19, count 0 2006.202.01:43:30.61#ibcon#about to read 5, iclass 19, count 0 2006.202.01:43:30.61#ibcon#read 5, iclass 19, count 0 2006.202.01:43:30.61#ibcon#about to read 6, iclass 19, count 0 2006.202.01:43:30.61#ibcon#read 6, iclass 19, count 0 2006.202.01:43:30.61#ibcon#end of sib2, iclass 19, count 0 2006.202.01:43:30.61#ibcon#*after write, iclass 19, count 0 2006.202.01:43:30.61#ibcon#*before return 0, iclass 19, count 0 2006.202.01:43:30.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:30.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:30.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.01:43:30.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.01:43:30.61$vck44/valo=8,884.99 2006.202.01:43:30.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.202.01:43:30.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.202.01:43:30.61#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:30.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:30.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:30.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:30.61#ibcon#enter wrdev, iclass 21, count 0 2006.202.01:43:30.61#ibcon#first serial, iclass 21, count 0 2006.202.01:43:30.61#ibcon#enter sib2, iclass 21, count 0 2006.202.01:43:30.61#ibcon#flushed, iclass 21, count 0 2006.202.01:43:30.61#ibcon#about to write, iclass 21, count 0 2006.202.01:43:30.61#ibcon#wrote, iclass 21, count 0 2006.202.01:43:30.61#ibcon#about to read 3, iclass 21, count 0 2006.202.01:43:30.63#ibcon#read 3, iclass 21, count 0 2006.202.01:43:30.63#ibcon#about to read 4, iclass 21, count 0 2006.202.01:43:30.63#ibcon#read 4, iclass 21, count 0 2006.202.01:43:30.63#ibcon#about to read 5, iclass 21, count 0 2006.202.01:43:30.63#ibcon#read 5, iclass 21, count 0 2006.202.01:43:30.63#ibcon#about to read 6, iclass 21, count 0 2006.202.01:43:30.63#ibcon#read 6, iclass 21, count 0 2006.202.01:43:30.63#ibcon#end of sib2, iclass 21, count 0 2006.202.01:43:30.63#ibcon#*mode == 0, iclass 21, count 0 2006.202.01:43:30.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.01:43:30.63#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.01:43:30.63#ibcon#*before write, iclass 21, count 0 2006.202.01:43:30.63#ibcon#enter sib2, iclass 21, count 0 2006.202.01:43:30.63#ibcon#flushed, iclass 21, count 0 2006.202.01:43:30.63#ibcon#about to write, iclass 21, count 0 2006.202.01:43:30.63#ibcon#wrote, iclass 21, count 0 2006.202.01:43:30.63#ibcon#about to read 3, iclass 21, count 0 2006.202.01:43:30.67#ibcon#read 3, iclass 21, count 0 2006.202.01:43:30.67#ibcon#about to read 4, iclass 21, count 0 2006.202.01:43:30.67#ibcon#read 4, iclass 21, count 0 2006.202.01:43:30.67#ibcon#about to read 5, iclass 21, count 0 2006.202.01:43:30.67#ibcon#read 5, iclass 21, count 0 2006.202.01:43:30.67#ibcon#about to read 6, iclass 21, count 0 2006.202.01:43:30.67#ibcon#read 6, iclass 21, count 0 2006.202.01:43:30.67#ibcon#end of sib2, iclass 21, count 0 2006.202.01:43:30.67#ibcon#*after write, iclass 21, count 0 2006.202.01:43:30.67#ibcon#*before return 0, iclass 21, count 0 2006.202.01:43:30.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:30.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:30.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.01:43:30.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.01:43:30.67$vck44/va=8,4 2006.202.01:43:30.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.202.01:43:30.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.202.01:43:30.67#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:30.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:43:30.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:43:30.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:43:30.73#ibcon#enter wrdev, iclass 23, count 2 2006.202.01:43:30.73#ibcon#first serial, iclass 23, count 2 2006.202.01:43:30.73#ibcon#enter sib2, iclass 23, count 2 2006.202.01:43:30.73#ibcon#flushed, iclass 23, count 2 2006.202.01:43:30.73#ibcon#about to write, iclass 23, count 2 2006.202.01:43:30.73#ibcon#wrote, iclass 23, count 2 2006.202.01:43:30.73#ibcon#about to read 3, iclass 23, count 2 2006.202.01:43:30.75#ibcon#read 3, iclass 23, count 2 2006.202.01:43:30.75#ibcon#about to read 4, iclass 23, count 2 2006.202.01:43:30.75#ibcon#read 4, iclass 23, count 2 2006.202.01:43:30.75#ibcon#about to read 5, iclass 23, count 2 2006.202.01:43:30.75#ibcon#read 5, iclass 23, count 2 2006.202.01:43:30.75#ibcon#about to read 6, iclass 23, count 2 2006.202.01:43:30.75#ibcon#read 6, iclass 23, count 2 2006.202.01:43:30.75#ibcon#end of sib2, iclass 23, count 2 2006.202.01:43:30.75#ibcon#*mode == 0, iclass 23, count 2 2006.202.01:43:30.75#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.202.01:43:30.75#ibcon#[25=AT08-04\r\n] 2006.202.01:43:30.75#ibcon#*before write, iclass 23, count 2 2006.202.01:43:30.75#ibcon#enter sib2, iclass 23, count 2 2006.202.01:43:30.75#ibcon#flushed, iclass 23, count 2 2006.202.01:43:30.75#ibcon#about to write, iclass 23, count 2 2006.202.01:43:30.75#ibcon#wrote, iclass 23, count 2 2006.202.01:43:30.75#ibcon#about to read 3, iclass 23, count 2 2006.202.01:43:30.78#ibcon#read 3, iclass 23, count 2 2006.202.01:43:30.78#ibcon#about to read 4, iclass 23, count 2 2006.202.01:43:30.78#ibcon#read 4, iclass 23, count 2 2006.202.01:43:30.78#ibcon#about to read 5, iclass 23, count 2 2006.202.01:43:30.78#ibcon#read 5, iclass 23, count 2 2006.202.01:43:30.78#ibcon#about to read 6, iclass 23, count 2 2006.202.01:43:30.78#ibcon#read 6, iclass 23, count 2 2006.202.01:43:30.78#ibcon#end of sib2, iclass 23, count 2 2006.202.01:43:30.78#ibcon#*after write, iclass 23, count 2 2006.202.01:43:30.78#ibcon#*before return 0, iclass 23, count 2 2006.202.01:43:30.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:43:30.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.202.01:43:30.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.202.01:43:30.78#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:30.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:43:30.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:43:30.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:43:30.90#ibcon#enter wrdev, iclass 23, count 0 2006.202.01:43:30.90#ibcon#first serial, iclass 23, count 0 2006.202.01:43:30.90#ibcon#enter sib2, iclass 23, count 0 2006.202.01:43:30.90#ibcon#flushed, iclass 23, count 0 2006.202.01:43:30.90#ibcon#about to write, iclass 23, count 0 2006.202.01:43:30.90#ibcon#wrote, iclass 23, count 0 2006.202.01:43:30.90#ibcon#about to read 3, iclass 23, count 0 2006.202.01:43:30.92#ibcon#read 3, iclass 23, count 0 2006.202.01:43:30.92#ibcon#about to read 4, iclass 23, count 0 2006.202.01:43:30.92#ibcon#read 4, iclass 23, count 0 2006.202.01:43:30.92#ibcon#about to read 5, iclass 23, count 0 2006.202.01:43:30.92#ibcon#read 5, iclass 23, count 0 2006.202.01:43:30.92#ibcon#about to read 6, iclass 23, count 0 2006.202.01:43:30.92#ibcon#read 6, iclass 23, count 0 2006.202.01:43:30.92#ibcon#end of sib2, iclass 23, count 0 2006.202.01:43:30.92#ibcon#*mode == 0, iclass 23, count 0 2006.202.01:43:30.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.01:43:30.92#ibcon#[25=USB\r\n] 2006.202.01:43:30.92#ibcon#*before write, iclass 23, count 0 2006.202.01:43:30.92#ibcon#enter sib2, iclass 23, count 0 2006.202.01:43:30.92#ibcon#flushed, iclass 23, count 0 2006.202.01:43:30.92#ibcon#about to write, iclass 23, count 0 2006.202.01:43:30.92#ibcon#wrote, iclass 23, count 0 2006.202.01:43:30.92#ibcon#about to read 3, iclass 23, count 0 2006.202.01:43:30.95#ibcon#read 3, iclass 23, count 0 2006.202.01:43:30.95#ibcon#about to read 4, iclass 23, count 0 2006.202.01:43:30.95#ibcon#read 4, iclass 23, count 0 2006.202.01:43:30.95#ibcon#about to read 5, iclass 23, count 0 2006.202.01:43:30.95#ibcon#read 5, iclass 23, count 0 2006.202.01:43:30.95#ibcon#about to read 6, iclass 23, count 0 2006.202.01:43:30.95#ibcon#read 6, iclass 23, count 0 2006.202.01:43:30.95#ibcon#end of sib2, iclass 23, count 0 2006.202.01:43:30.95#ibcon#*after write, iclass 23, count 0 2006.202.01:43:30.95#ibcon#*before return 0, iclass 23, count 0 2006.202.01:43:30.95#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:43:30.95#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.202.01:43:30.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.01:43:30.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.01:43:30.95$vck44/vblo=1,629.99 2006.202.01:43:30.95#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.202.01:43:30.95#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.202.01:43:30.95#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:30.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:43:30.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:43:30.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:43:30.95#ibcon#enter wrdev, iclass 25, count 0 2006.202.01:43:30.95#ibcon#first serial, iclass 25, count 0 2006.202.01:43:30.95#ibcon#enter sib2, iclass 25, count 0 2006.202.01:43:30.95#ibcon#flushed, iclass 25, count 0 2006.202.01:43:30.95#ibcon#about to write, iclass 25, count 0 2006.202.01:43:30.95#ibcon#wrote, iclass 25, count 0 2006.202.01:43:30.95#ibcon#about to read 3, iclass 25, count 0 2006.202.01:43:30.97#ibcon#read 3, iclass 25, count 0 2006.202.01:43:30.97#ibcon#about to read 4, iclass 25, count 0 2006.202.01:43:30.97#ibcon#read 4, iclass 25, count 0 2006.202.01:43:30.97#ibcon#about to read 5, iclass 25, count 0 2006.202.01:43:30.97#ibcon#read 5, iclass 25, count 0 2006.202.01:43:30.97#ibcon#about to read 6, iclass 25, count 0 2006.202.01:43:30.97#ibcon#read 6, iclass 25, count 0 2006.202.01:43:30.97#ibcon#end of sib2, iclass 25, count 0 2006.202.01:43:30.97#ibcon#*mode == 0, iclass 25, count 0 2006.202.01:43:30.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.202.01:43:30.97#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.01:43:30.97#ibcon#*before write, iclass 25, count 0 2006.202.01:43:30.97#ibcon#enter sib2, iclass 25, count 0 2006.202.01:43:30.97#ibcon#flushed, iclass 25, count 0 2006.202.01:43:30.97#ibcon#about to write, iclass 25, count 0 2006.202.01:43:30.97#ibcon#wrote, iclass 25, count 0 2006.202.01:43:30.97#ibcon#about to read 3, iclass 25, count 0 2006.202.01:43:31.01#ibcon#read 3, iclass 25, count 0 2006.202.01:43:31.01#ibcon#about to read 4, iclass 25, count 0 2006.202.01:43:31.01#ibcon#read 4, iclass 25, count 0 2006.202.01:43:31.01#ibcon#about to read 5, iclass 25, count 0 2006.202.01:43:31.01#ibcon#read 5, iclass 25, count 0 2006.202.01:43:31.01#ibcon#about to read 6, iclass 25, count 0 2006.202.01:43:31.01#ibcon#read 6, iclass 25, count 0 2006.202.01:43:31.01#ibcon#end of sib2, iclass 25, count 0 2006.202.01:43:31.01#ibcon#*after write, iclass 25, count 0 2006.202.01:43:31.01#ibcon#*before return 0, iclass 25, count 0 2006.202.01:43:31.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:43:31.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.202.01:43:31.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.202.01:43:31.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.202.01:43:31.01$vck44/vb=1,4 2006.202.01:43:31.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.202.01:43:31.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.202.01:43:31.01#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:31.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:43:31.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:43:31.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:43:31.01#ibcon#enter wrdev, iclass 27, count 2 2006.202.01:43:31.01#ibcon#first serial, iclass 27, count 2 2006.202.01:43:31.01#ibcon#enter sib2, iclass 27, count 2 2006.202.01:43:31.01#ibcon#flushed, iclass 27, count 2 2006.202.01:43:31.01#ibcon#about to write, iclass 27, count 2 2006.202.01:43:31.01#ibcon#wrote, iclass 27, count 2 2006.202.01:43:31.01#ibcon#about to read 3, iclass 27, count 2 2006.202.01:43:31.03#ibcon#read 3, iclass 27, count 2 2006.202.01:43:31.03#ibcon#about to read 4, iclass 27, count 2 2006.202.01:43:31.03#ibcon#read 4, iclass 27, count 2 2006.202.01:43:31.03#ibcon#about to read 5, iclass 27, count 2 2006.202.01:43:31.03#ibcon#read 5, iclass 27, count 2 2006.202.01:43:31.03#ibcon#about to read 6, iclass 27, count 2 2006.202.01:43:31.03#ibcon#read 6, iclass 27, count 2 2006.202.01:43:31.03#ibcon#end of sib2, iclass 27, count 2 2006.202.01:43:31.03#ibcon#*mode == 0, iclass 27, count 2 2006.202.01:43:31.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.202.01:43:31.03#ibcon#[27=AT01-04\r\n] 2006.202.01:43:31.03#ibcon#*before write, iclass 27, count 2 2006.202.01:43:31.03#ibcon#enter sib2, iclass 27, count 2 2006.202.01:43:31.03#ibcon#flushed, iclass 27, count 2 2006.202.01:43:31.03#ibcon#about to write, iclass 27, count 2 2006.202.01:43:31.03#ibcon#wrote, iclass 27, count 2 2006.202.01:43:31.03#ibcon#about to read 3, iclass 27, count 2 2006.202.01:43:31.06#ibcon#read 3, iclass 27, count 2 2006.202.01:43:31.06#ibcon#about to read 4, iclass 27, count 2 2006.202.01:43:31.06#ibcon#read 4, iclass 27, count 2 2006.202.01:43:31.06#ibcon#about to read 5, iclass 27, count 2 2006.202.01:43:31.06#ibcon#read 5, iclass 27, count 2 2006.202.01:43:31.06#ibcon#about to read 6, iclass 27, count 2 2006.202.01:43:31.06#ibcon#read 6, iclass 27, count 2 2006.202.01:43:31.06#ibcon#end of sib2, iclass 27, count 2 2006.202.01:43:31.06#ibcon#*after write, iclass 27, count 2 2006.202.01:43:31.06#ibcon#*before return 0, iclass 27, count 2 2006.202.01:43:31.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:43:31.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.202.01:43:31.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.202.01:43:31.06#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:31.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:43:31.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:43:31.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:43:31.18#ibcon#enter wrdev, iclass 27, count 0 2006.202.01:43:31.18#ibcon#first serial, iclass 27, count 0 2006.202.01:43:31.18#ibcon#enter sib2, iclass 27, count 0 2006.202.01:43:31.18#ibcon#flushed, iclass 27, count 0 2006.202.01:43:31.18#ibcon#about to write, iclass 27, count 0 2006.202.01:43:31.18#ibcon#wrote, iclass 27, count 0 2006.202.01:43:31.18#ibcon#about to read 3, iclass 27, count 0 2006.202.01:43:31.20#ibcon#read 3, iclass 27, count 0 2006.202.01:43:31.20#ibcon#about to read 4, iclass 27, count 0 2006.202.01:43:31.20#ibcon#read 4, iclass 27, count 0 2006.202.01:43:31.20#ibcon#about to read 5, iclass 27, count 0 2006.202.01:43:31.20#ibcon#read 5, iclass 27, count 0 2006.202.01:43:31.20#ibcon#about to read 6, iclass 27, count 0 2006.202.01:43:31.20#ibcon#read 6, iclass 27, count 0 2006.202.01:43:31.20#ibcon#end of sib2, iclass 27, count 0 2006.202.01:43:31.20#ibcon#*mode == 0, iclass 27, count 0 2006.202.01:43:31.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.202.01:43:31.20#ibcon#[27=USB\r\n] 2006.202.01:43:31.20#ibcon#*before write, iclass 27, count 0 2006.202.01:43:31.20#ibcon#enter sib2, iclass 27, count 0 2006.202.01:43:31.20#ibcon#flushed, iclass 27, count 0 2006.202.01:43:31.20#ibcon#about to write, iclass 27, count 0 2006.202.01:43:31.20#ibcon#wrote, iclass 27, count 0 2006.202.01:43:31.20#ibcon#about to read 3, iclass 27, count 0 2006.202.01:43:31.23#ibcon#read 3, iclass 27, count 0 2006.202.01:43:31.23#ibcon#about to read 4, iclass 27, count 0 2006.202.01:43:31.23#ibcon#read 4, iclass 27, count 0 2006.202.01:43:31.23#ibcon#about to read 5, iclass 27, count 0 2006.202.01:43:31.23#ibcon#read 5, iclass 27, count 0 2006.202.01:43:31.23#ibcon#about to read 6, iclass 27, count 0 2006.202.01:43:31.23#ibcon#read 6, iclass 27, count 0 2006.202.01:43:31.23#ibcon#end of sib2, iclass 27, count 0 2006.202.01:43:31.23#ibcon#*after write, iclass 27, count 0 2006.202.01:43:31.23#ibcon#*before return 0, iclass 27, count 0 2006.202.01:43:31.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:43:31.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.202.01:43:31.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.202.01:43:31.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.202.01:43:31.23$vck44/vblo=2,634.99 2006.202.01:43:31.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.202.01:43:31.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.202.01:43:31.23#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:31.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:31.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:31.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:31.23#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:43:31.23#ibcon#first serial, iclass 29, count 0 2006.202.01:43:31.23#ibcon#enter sib2, iclass 29, count 0 2006.202.01:43:31.23#ibcon#flushed, iclass 29, count 0 2006.202.01:43:31.23#ibcon#about to write, iclass 29, count 0 2006.202.01:43:31.23#ibcon#wrote, iclass 29, count 0 2006.202.01:43:31.23#ibcon#about to read 3, iclass 29, count 0 2006.202.01:43:31.25#ibcon#read 3, iclass 29, count 0 2006.202.01:43:31.25#ibcon#about to read 4, iclass 29, count 0 2006.202.01:43:31.25#ibcon#read 4, iclass 29, count 0 2006.202.01:43:31.25#ibcon#about to read 5, iclass 29, count 0 2006.202.01:43:31.25#ibcon#read 5, iclass 29, count 0 2006.202.01:43:31.25#ibcon#about to read 6, iclass 29, count 0 2006.202.01:43:31.25#ibcon#read 6, iclass 29, count 0 2006.202.01:43:31.25#ibcon#end of sib2, iclass 29, count 0 2006.202.01:43:31.25#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:43:31.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:43:31.25#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.01:43:31.25#ibcon#*before write, iclass 29, count 0 2006.202.01:43:31.25#ibcon#enter sib2, iclass 29, count 0 2006.202.01:43:31.25#ibcon#flushed, iclass 29, count 0 2006.202.01:43:31.25#ibcon#about to write, iclass 29, count 0 2006.202.01:43:31.25#ibcon#wrote, iclass 29, count 0 2006.202.01:43:31.25#ibcon#about to read 3, iclass 29, count 0 2006.202.01:43:31.29#ibcon#read 3, iclass 29, count 0 2006.202.01:43:31.29#ibcon#about to read 4, iclass 29, count 0 2006.202.01:43:31.29#ibcon#read 4, iclass 29, count 0 2006.202.01:43:31.29#ibcon#about to read 5, iclass 29, count 0 2006.202.01:43:31.29#ibcon#read 5, iclass 29, count 0 2006.202.01:43:31.29#ibcon#about to read 6, iclass 29, count 0 2006.202.01:43:31.29#ibcon#read 6, iclass 29, count 0 2006.202.01:43:31.29#ibcon#end of sib2, iclass 29, count 0 2006.202.01:43:31.29#ibcon#*after write, iclass 29, count 0 2006.202.01:43:31.29#ibcon#*before return 0, iclass 29, count 0 2006.202.01:43:31.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:31.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.202.01:43:31.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:43:31.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:43:31.29$vck44/vb=2,5 2006.202.01:43:31.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.202.01:43:31.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.202.01:43:31.29#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:31.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:31.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:31.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:31.35#ibcon#enter wrdev, iclass 31, count 2 2006.202.01:43:31.35#ibcon#first serial, iclass 31, count 2 2006.202.01:43:31.35#ibcon#enter sib2, iclass 31, count 2 2006.202.01:43:31.35#ibcon#flushed, iclass 31, count 2 2006.202.01:43:31.35#ibcon#about to write, iclass 31, count 2 2006.202.01:43:31.35#ibcon#wrote, iclass 31, count 2 2006.202.01:43:31.35#ibcon#about to read 3, iclass 31, count 2 2006.202.01:43:31.37#ibcon#read 3, iclass 31, count 2 2006.202.01:43:31.37#ibcon#about to read 4, iclass 31, count 2 2006.202.01:43:31.37#ibcon#read 4, iclass 31, count 2 2006.202.01:43:31.37#ibcon#about to read 5, iclass 31, count 2 2006.202.01:43:31.37#ibcon#read 5, iclass 31, count 2 2006.202.01:43:31.37#ibcon#about to read 6, iclass 31, count 2 2006.202.01:43:31.37#ibcon#read 6, iclass 31, count 2 2006.202.01:43:31.37#ibcon#end of sib2, iclass 31, count 2 2006.202.01:43:31.37#ibcon#*mode == 0, iclass 31, count 2 2006.202.01:43:31.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.202.01:43:31.37#ibcon#[27=AT02-05\r\n] 2006.202.01:43:31.37#ibcon#*before write, iclass 31, count 2 2006.202.01:43:31.37#ibcon#enter sib2, iclass 31, count 2 2006.202.01:43:31.37#ibcon#flushed, iclass 31, count 2 2006.202.01:43:31.37#ibcon#about to write, iclass 31, count 2 2006.202.01:43:31.37#ibcon#wrote, iclass 31, count 2 2006.202.01:43:31.37#ibcon#about to read 3, iclass 31, count 2 2006.202.01:43:31.40#ibcon#read 3, iclass 31, count 2 2006.202.01:43:31.40#ibcon#about to read 4, iclass 31, count 2 2006.202.01:43:31.40#ibcon#read 4, iclass 31, count 2 2006.202.01:43:31.40#ibcon#about to read 5, iclass 31, count 2 2006.202.01:43:31.40#ibcon#read 5, iclass 31, count 2 2006.202.01:43:31.40#ibcon#about to read 6, iclass 31, count 2 2006.202.01:43:31.40#ibcon#read 6, iclass 31, count 2 2006.202.01:43:31.40#ibcon#end of sib2, iclass 31, count 2 2006.202.01:43:31.40#ibcon#*after write, iclass 31, count 2 2006.202.01:43:31.40#ibcon#*before return 0, iclass 31, count 2 2006.202.01:43:31.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:31.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.202.01:43:31.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.202.01:43:31.40#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:31.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:31.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:31.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:31.52#ibcon#enter wrdev, iclass 31, count 0 2006.202.01:43:31.52#ibcon#first serial, iclass 31, count 0 2006.202.01:43:31.52#ibcon#enter sib2, iclass 31, count 0 2006.202.01:43:31.52#ibcon#flushed, iclass 31, count 0 2006.202.01:43:31.52#ibcon#about to write, iclass 31, count 0 2006.202.01:43:31.52#ibcon#wrote, iclass 31, count 0 2006.202.01:43:31.52#ibcon#about to read 3, iclass 31, count 0 2006.202.01:43:31.54#ibcon#read 3, iclass 31, count 0 2006.202.01:43:31.54#ibcon#about to read 4, iclass 31, count 0 2006.202.01:43:31.54#ibcon#read 4, iclass 31, count 0 2006.202.01:43:31.54#ibcon#about to read 5, iclass 31, count 0 2006.202.01:43:31.54#ibcon#read 5, iclass 31, count 0 2006.202.01:43:31.54#ibcon#about to read 6, iclass 31, count 0 2006.202.01:43:31.54#ibcon#read 6, iclass 31, count 0 2006.202.01:43:31.54#ibcon#end of sib2, iclass 31, count 0 2006.202.01:43:31.54#ibcon#*mode == 0, iclass 31, count 0 2006.202.01:43:31.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.202.01:43:31.54#ibcon#[27=USB\r\n] 2006.202.01:43:31.54#ibcon#*before write, iclass 31, count 0 2006.202.01:43:31.54#ibcon#enter sib2, iclass 31, count 0 2006.202.01:43:31.54#ibcon#flushed, iclass 31, count 0 2006.202.01:43:31.54#ibcon#about to write, iclass 31, count 0 2006.202.01:43:31.54#ibcon#wrote, iclass 31, count 0 2006.202.01:43:31.54#ibcon#about to read 3, iclass 31, count 0 2006.202.01:43:31.57#ibcon#read 3, iclass 31, count 0 2006.202.01:43:31.57#ibcon#about to read 4, iclass 31, count 0 2006.202.01:43:31.57#ibcon#read 4, iclass 31, count 0 2006.202.01:43:31.57#ibcon#about to read 5, iclass 31, count 0 2006.202.01:43:31.57#ibcon#read 5, iclass 31, count 0 2006.202.01:43:31.57#ibcon#about to read 6, iclass 31, count 0 2006.202.01:43:31.57#ibcon#read 6, iclass 31, count 0 2006.202.01:43:31.57#ibcon#end of sib2, iclass 31, count 0 2006.202.01:43:31.57#ibcon#*after write, iclass 31, count 0 2006.202.01:43:31.57#ibcon#*before return 0, iclass 31, count 0 2006.202.01:43:31.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:31.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.202.01:43:31.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.202.01:43:31.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.202.01:43:31.57$vck44/vblo=3,649.99 2006.202.01:43:31.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.202.01:43:31.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.202.01:43:31.57#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:31.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:31.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:31.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:31.57#ibcon#enter wrdev, iclass 33, count 0 2006.202.01:43:31.57#ibcon#first serial, iclass 33, count 0 2006.202.01:43:31.57#ibcon#enter sib2, iclass 33, count 0 2006.202.01:43:31.57#ibcon#flushed, iclass 33, count 0 2006.202.01:43:31.57#ibcon#about to write, iclass 33, count 0 2006.202.01:43:31.57#ibcon#wrote, iclass 33, count 0 2006.202.01:43:31.57#ibcon#about to read 3, iclass 33, count 0 2006.202.01:43:31.59#ibcon#read 3, iclass 33, count 0 2006.202.01:43:31.59#ibcon#about to read 4, iclass 33, count 0 2006.202.01:43:31.59#ibcon#read 4, iclass 33, count 0 2006.202.01:43:31.59#ibcon#about to read 5, iclass 33, count 0 2006.202.01:43:31.59#ibcon#read 5, iclass 33, count 0 2006.202.01:43:31.59#ibcon#about to read 6, iclass 33, count 0 2006.202.01:43:31.59#ibcon#read 6, iclass 33, count 0 2006.202.01:43:31.59#ibcon#end of sib2, iclass 33, count 0 2006.202.01:43:31.59#ibcon#*mode == 0, iclass 33, count 0 2006.202.01:43:31.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.202.01:43:31.59#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.01:43:31.59#ibcon#*before write, iclass 33, count 0 2006.202.01:43:31.59#ibcon#enter sib2, iclass 33, count 0 2006.202.01:43:31.59#ibcon#flushed, iclass 33, count 0 2006.202.01:43:31.59#ibcon#about to write, iclass 33, count 0 2006.202.01:43:31.59#ibcon#wrote, iclass 33, count 0 2006.202.01:43:31.59#ibcon#about to read 3, iclass 33, count 0 2006.202.01:43:31.63#ibcon#read 3, iclass 33, count 0 2006.202.01:43:31.63#ibcon#about to read 4, iclass 33, count 0 2006.202.01:43:31.63#ibcon#read 4, iclass 33, count 0 2006.202.01:43:31.63#ibcon#about to read 5, iclass 33, count 0 2006.202.01:43:31.63#ibcon#read 5, iclass 33, count 0 2006.202.01:43:31.63#ibcon#about to read 6, iclass 33, count 0 2006.202.01:43:31.63#ibcon#read 6, iclass 33, count 0 2006.202.01:43:31.63#ibcon#end of sib2, iclass 33, count 0 2006.202.01:43:31.63#ibcon#*after write, iclass 33, count 0 2006.202.01:43:31.63#ibcon#*before return 0, iclass 33, count 0 2006.202.01:43:31.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:31.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.202.01:43:31.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.202.01:43:31.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.202.01:43:31.63$vck44/vb=3,4 2006.202.01:43:31.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.202.01:43:31.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.202.01:43:31.63#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:31.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:31.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:31.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:31.69#ibcon#enter wrdev, iclass 35, count 2 2006.202.01:43:31.69#ibcon#first serial, iclass 35, count 2 2006.202.01:43:31.69#ibcon#enter sib2, iclass 35, count 2 2006.202.01:43:31.69#ibcon#flushed, iclass 35, count 2 2006.202.01:43:31.69#ibcon#about to write, iclass 35, count 2 2006.202.01:43:31.69#ibcon#wrote, iclass 35, count 2 2006.202.01:43:31.69#ibcon#about to read 3, iclass 35, count 2 2006.202.01:43:31.71#ibcon#read 3, iclass 35, count 2 2006.202.01:43:31.71#ibcon#about to read 4, iclass 35, count 2 2006.202.01:43:31.71#ibcon#read 4, iclass 35, count 2 2006.202.01:43:31.71#ibcon#about to read 5, iclass 35, count 2 2006.202.01:43:31.71#ibcon#read 5, iclass 35, count 2 2006.202.01:43:31.71#ibcon#about to read 6, iclass 35, count 2 2006.202.01:43:31.71#ibcon#read 6, iclass 35, count 2 2006.202.01:43:31.71#ibcon#end of sib2, iclass 35, count 2 2006.202.01:43:31.71#ibcon#*mode == 0, iclass 35, count 2 2006.202.01:43:31.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.202.01:43:31.71#ibcon#[27=AT03-04\r\n] 2006.202.01:43:31.71#ibcon#*before write, iclass 35, count 2 2006.202.01:43:31.71#ibcon#enter sib2, iclass 35, count 2 2006.202.01:43:31.71#ibcon#flushed, iclass 35, count 2 2006.202.01:43:31.71#ibcon#about to write, iclass 35, count 2 2006.202.01:43:31.71#ibcon#wrote, iclass 35, count 2 2006.202.01:43:31.71#ibcon#about to read 3, iclass 35, count 2 2006.202.01:43:31.74#ibcon#read 3, iclass 35, count 2 2006.202.01:43:31.74#ibcon#about to read 4, iclass 35, count 2 2006.202.01:43:31.74#ibcon#read 4, iclass 35, count 2 2006.202.01:43:31.74#ibcon#about to read 5, iclass 35, count 2 2006.202.01:43:31.74#ibcon#read 5, iclass 35, count 2 2006.202.01:43:31.74#ibcon#about to read 6, iclass 35, count 2 2006.202.01:43:31.74#ibcon#read 6, iclass 35, count 2 2006.202.01:43:31.74#ibcon#end of sib2, iclass 35, count 2 2006.202.01:43:31.74#ibcon#*after write, iclass 35, count 2 2006.202.01:43:31.74#ibcon#*before return 0, iclass 35, count 2 2006.202.01:43:31.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:31.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.202.01:43:31.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.202.01:43:31.74#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:31.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:31.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:31.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:31.86#ibcon#enter wrdev, iclass 35, count 0 2006.202.01:43:31.86#ibcon#first serial, iclass 35, count 0 2006.202.01:43:31.86#ibcon#enter sib2, iclass 35, count 0 2006.202.01:43:31.86#ibcon#flushed, iclass 35, count 0 2006.202.01:43:31.86#ibcon#about to write, iclass 35, count 0 2006.202.01:43:31.86#ibcon#wrote, iclass 35, count 0 2006.202.01:43:31.86#ibcon#about to read 3, iclass 35, count 0 2006.202.01:43:31.88#ibcon#read 3, iclass 35, count 0 2006.202.01:43:31.88#ibcon#about to read 4, iclass 35, count 0 2006.202.01:43:31.88#ibcon#read 4, iclass 35, count 0 2006.202.01:43:31.88#ibcon#about to read 5, iclass 35, count 0 2006.202.01:43:31.88#ibcon#read 5, iclass 35, count 0 2006.202.01:43:31.88#ibcon#about to read 6, iclass 35, count 0 2006.202.01:43:31.88#ibcon#read 6, iclass 35, count 0 2006.202.01:43:31.88#ibcon#end of sib2, iclass 35, count 0 2006.202.01:43:31.88#ibcon#*mode == 0, iclass 35, count 0 2006.202.01:43:31.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.202.01:43:31.88#ibcon#[27=USB\r\n] 2006.202.01:43:31.88#ibcon#*before write, iclass 35, count 0 2006.202.01:43:31.88#ibcon#enter sib2, iclass 35, count 0 2006.202.01:43:31.88#ibcon#flushed, iclass 35, count 0 2006.202.01:43:31.88#ibcon#about to write, iclass 35, count 0 2006.202.01:43:31.88#ibcon#wrote, iclass 35, count 0 2006.202.01:43:31.88#ibcon#about to read 3, iclass 35, count 0 2006.202.01:43:31.91#ibcon#read 3, iclass 35, count 0 2006.202.01:43:31.91#ibcon#about to read 4, iclass 35, count 0 2006.202.01:43:31.91#ibcon#read 4, iclass 35, count 0 2006.202.01:43:31.91#ibcon#about to read 5, iclass 35, count 0 2006.202.01:43:31.91#ibcon#read 5, iclass 35, count 0 2006.202.01:43:31.91#ibcon#about to read 6, iclass 35, count 0 2006.202.01:43:31.91#ibcon#read 6, iclass 35, count 0 2006.202.01:43:31.91#ibcon#end of sib2, iclass 35, count 0 2006.202.01:43:31.91#ibcon#*after write, iclass 35, count 0 2006.202.01:43:31.91#ibcon#*before return 0, iclass 35, count 0 2006.202.01:43:31.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:31.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.202.01:43:31.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.202.01:43:31.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.202.01:43:31.91$vck44/vblo=4,679.99 2006.202.01:43:31.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.202.01:43:31.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.202.01:43:31.91#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:31.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:31.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:31.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:31.91#ibcon#enter wrdev, iclass 37, count 0 2006.202.01:43:31.91#ibcon#first serial, iclass 37, count 0 2006.202.01:43:31.91#ibcon#enter sib2, iclass 37, count 0 2006.202.01:43:31.91#ibcon#flushed, iclass 37, count 0 2006.202.01:43:31.91#ibcon#about to write, iclass 37, count 0 2006.202.01:43:31.91#ibcon#wrote, iclass 37, count 0 2006.202.01:43:31.91#ibcon#about to read 3, iclass 37, count 0 2006.202.01:43:31.93#ibcon#read 3, iclass 37, count 0 2006.202.01:43:31.93#ibcon#about to read 4, iclass 37, count 0 2006.202.01:43:31.93#ibcon#read 4, iclass 37, count 0 2006.202.01:43:31.93#ibcon#about to read 5, iclass 37, count 0 2006.202.01:43:31.93#ibcon#read 5, iclass 37, count 0 2006.202.01:43:31.93#ibcon#about to read 6, iclass 37, count 0 2006.202.01:43:31.93#ibcon#read 6, iclass 37, count 0 2006.202.01:43:31.93#ibcon#end of sib2, iclass 37, count 0 2006.202.01:43:31.93#ibcon#*mode == 0, iclass 37, count 0 2006.202.01:43:31.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.202.01:43:31.93#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.01:43:31.93#ibcon#*before write, iclass 37, count 0 2006.202.01:43:31.93#ibcon#enter sib2, iclass 37, count 0 2006.202.01:43:31.93#ibcon#flushed, iclass 37, count 0 2006.202.01:43:31.93#ibcon#about to write, iclass 37, count 0 2006.202.01:43:31.93#ibcon#wrote, iclass 37, count 0 2006.202.01:43:31.93#ibcon#about to read 3, iclass 37, count 0 2006.202.01:43:31.97#ibcon#read 3, iclass 37, count 0 2006.202.01:43:31.97#ibcon#about to read 4, iclass 37, count 0 2006.202.01:43:31.97#ibcon#read 4, iclass 37, count 0 2006.202.01:43:31.97#ibcon#about to read 5, iclass 37, count 0 2006.202.01:43:31.97#ibcon#read 5, iclass 37, count 0 2006.202.01:43:31.97#ibcon#about to read 6, iclass 37, count 0 2006.202.01:43:31.97#ibcon#read 6, iclass 37, count 0 2006.202.01:43:31.97#ibcon#end of sib2, iclass 37, count 0 2006.202.01:43:31.97#ibcon#*after write, iclass 37, count 0 2006.202.01:43:31.97#ibcon#*before return 0, iclass 37, count 0 2006.202.01:43:31.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:31.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.202.01:43:31.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.202.01:43:31.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.202.01:43:31.97$vck44/vb=4,5 2006.202.01:43:31.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.202.01:43:31.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.202.01:43:31.97#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:31.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:32.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:32.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:32.03#ibcon#enter wrdev, iclass 39, count 2 2006.202.01:43:32.03#ibcon#first serial, iclass 39, count 2 2006.202.01:43:32.03#ibcon#enter sib2, iclass 39, count 2 2006.202.01:43:32.03#ibcon#flushed, iclass 39, count 2 2006.202.01:43:32.03#ibcon#about to write, iclass 39, count 2 2006.202.01:43:32.03#ibcon#wrote, iclass 39, count 2 2006.202.01:43:32.03#ibcon#about to read 3, iclass 39, count 2 2006.202.01:43:32.05#ibcon#read 3, iclass 39, count 2 2006.202.01:43:32.05#ibcon#about to read 4, iclass 39, count 2 2006.202.01:43:32.05#ibcon#read 4, iclass 39, count 2 2006.202.01:43:32.05#ibcon#about to read 5, iclass 39, count 2 2006.202.01:43:32.05#ibcon#read 5, iclass 39, count 2 2006.202.01:43:32.05#ibcon#about to read 6, iclass 39, count 2 2006.202.01:43:32.05#ibcon#read 6, iclass 39, count 2 2006.202.01:43:32.05#ibcon#end of sib2, iclass 39, count 2 2006.202.01:43:32.05#ibcon#*mode == 0, iclass 39, count 2 2006.202.01:43:32.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.202.01:43:32.05#ibcon#[27=AT04-05\r\n] 2006.202.01:43:32.05#ibcon#*before write, iclass 39, count 2 2006.202.01:43:32.05#ibcon#enter sib2, iclass 39, count 2 2006.202.01:43:32.05#ibcon#flushed, iclass 39, count 2 2006.202.01:43:32.05#ibcon#about to write, iclass 39, count 2 2006.202.01:43:32.05#ibcon#wrote, iclass 39, count 2 2006.202.01:43:32.05#ibcon#about to read 3, iclass 39, count 2 2006.202.01:43:32.08#ibcon#read 3, iclass 39, count 2 2006.202.01:43:32.08#ibcon#about to read 4, iclass 39, count 2 2006.202.01:43:32.08#ibcon#read 4, iclass 39, count 2 2006.202.01:43:32.08#ibcon#about to read 5, iclass 39, count 2 2006.202.01:43:32.08#ibcon#read 5, iclass 39, count 2 2006.202.01:43:32.08#ibcon#about to read 6, iclass 39, count 2 2006.202.01:43:32.08#ibcon#read 6, iclass 39, count 2 2006.202.01:43:32.08#ibcon#end of sib2, iclass 39, count 2 2006.202.01:43:32.08#ibcon#*after write, iclass 39, count 2 2006.202.01:43:32.08#ibcon#*before return 0, iclass 39, count 2 2006.202.01:43:32.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:32.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.202.01:43:32.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.202.01:43:32.08#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:32.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:32.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:32.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:32.20#ibcon#enter wrdev, iclass 39, count 0 2006.202.01:43:32.20#ibcon#first serial, iclass 39, count 0 2006.202.01:43:32.20#ibcon#enter sib2, iclass 39, count 0 2006.202.01:43:32.20#ibcon#flushed, iclass 39, count 0 2006.202.01:43:32.20#ibcon#about to write, iclass 39, count 0 2006.202.01:43:32.20#ibcon#wrote, iclass 39, count 0 2006.202.01:43:32.20#ibcon#about to read 3, iclass 39, count 0 2006.202.01:43:32.22#ibcon#read 3, iclass 39, count 0 2006.202.01:43:32.22#ibcon#about to read 4, iclass 39, count 0 2006.202.01:43:32.22#ibcon#read 4, iclass 39, count 0 2006.202.01:43:32.22#ibcon#about to read 5, iclass 39, count 0 2006.202.01:43:32.22#ibcon#read 5, iclass 39, count 0 2006.202.01:43:32.22#ibcon#about to read 6, iclass 39, count 0 2006.202.01:43:32.22#ibcon#read 6, iclass 39, count 0 2006.202.01:43:32.22#ibcon#end of sib2, iclass 39, count 0 2006.202.01:43:32.22#ibcon#*mode == 0, iclass 39, count 0 2006.202.01:43:32.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.202.01:43:32.22#ibcon#[27=USB\r\n] 2006.202.01:43:32.22#ibcon#*before write, iclass 39, count 0 2006.202.01:43:32.22#ibcon#enter sib2, iclass 39, count 0 2006.202.01:43:32.22#ibcon#flushed, iclass 39, count 0 2006.202.01:43:32.22#ibcon#about to write, iclass 39, count 0 2006.202.01:43:32.22#ibcon#wrote, iclass 39, count 0 2006.202.01:43:32.22#ibcon#about to read 3, iclass 39, count 0 2006.202.01:43:32.25#ibcon#read 3, iclass 39, count 0 2006.202.01:43:32.25#ibcon#about to read 4, iclass 39, count 0 2006.202.01:43:32.25#ibcon#read 4, iclass 39, count 0 2006.202.01:43:32.25#ibcon#about to read 5, iclass 39, count 0 2006.202.01:43:32.25#ibcon#read 5, iclass 39, count 0 2006.202.01:43:32.25#ibcon#about to read 6, iclass 39, count 0 2006.202.01:43:32.25#ibcon#read 6, iclass 39, count 0 2006.202.01:43:32.25#ibcon#end of sib2, iclass 39, count 0 2006.202.01:43:32.25#ibcon#*after write, iclass 39, count 0 2006.202.01:43:32.25#ibcon#*before return 0, iclass 39, count 0 2006.202.01:43:32.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:32.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.202.01:43:32.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.202.01:43:32.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.202.01:43:32.25$vck44/vblo=5,709.99 2006.202.01:43:32.25#ibcon#iclass 2 nclrec 1 cls_cnt 2 2006.202.01:43:32.25#ibcon#iclass 2 iclrec 1 cls_cnt 2 2006.202.01:43:32.25#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:32.25#ibcon#before find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:32.25#ibcon#after find_delay mode 2, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:32.25#ibcon#before mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:32.25#ibcon#enter wrdev, iclass 2, count 0 2006.202.01:43:32.25#ibcon#first serial, iclass 2, count 0 2006.202.01:43:32.25#ibcon#enter sib2, iclass 2, count 0 2006.202.01:43:32.25#ibcon#flushed, iclass 2, count 0 2006.202.01:43:32.25#ibcon#about to write, iclass 2, count 0 2006.202.01:43:32.25#ibcon#wrote, iclass 2, count 0 2006.202.01:43:32.25#ibcon#about to read 3, iclass 2, count 0 2006.202.01:43:32.27#ibcon#read 3, iclass 2, count 0 2006.202.01:43:32.27#ibcon#about to read 4, iclass 2, count 0 2006.202.01:43:32.27#ibcon#read 4, iclass 2, count 0 2006.202.01:43:32.27#ibcon#about to read 5, iclass 2, count 0 2006.202.01:43:32.27#ibcon#read 5, iclass 2, count 0 2006.202.01:43:32.27#ibcon#about to read 6, iclass 2, count 0 2006.202.01:43:32.27#ibcon#read 6, iclass 2, count 0 2006.202.01:43:32.27#ibcon#end of sib2, iclass 2, count 0 2006.202.01:43:32.27#ibcon#*mode == 0, iclass 2, count 0 2006.202.01:43:32.27#ibcon#*mode == 0 && serial, iclass 2, count 0 2006.202.01:43:32.27#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.01:43:32.27#ibcon#*before write, iclass 2, count 0 2006.202.01:43:32.27#ibcon#enter sib2, iclass 2, count 0 2006.202.01:43:32.27#ibcon#flushed, iclass 2, count 0 2006.202.01:43:32.27#ibcon#about to write, iclass 2, count 0 2006.202.01:43:32.27#ibcon#wrote, iclass 2, count 0 2006.202.01:43:32.27#ibcon#about to read 3, iclass 2, count 0 2006.202.01:43:32.31#ibcon#read 3, iclass 2, count 0 2006.202.01:43:32.31#ibcon#about to read 4, iclass 2, count 0 2006.202.01:43:32.31#ibcon#read 4, iclass 2, count 0 2006.202.01:43:32.31#ibcon#about to read 5, iclass 2, count 0 2006.202.01:43:32.31#ibcon#read 5, iclass 2, count 0 2006.202.01:43:32.31#ibcon#about to read 6, iclass 2, count 0 2006.202.01:43:32.31#ibcon#read 6, iclass 2, count 0 2006.202.01:43:32.31#ibcon#end of sib2, iclass 2, count 0 2006.202.01:43:32.31#ibcon#*after write, iclass 2, count 0 2006.202.01:43:32.31#ibcon#*before return 0, iclass 2, count 0 2006.202.01:43:32.31#ibcon#after mode 2 write, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:32.31#ibcon#end of loop, iclass 2 iclrec 1 cls_cnt 0 2006.202.01:43:32.31#ibcon#about to clear, iclass 2 cls_cnt 0 2006.202.01:43:32.31#ibcon#cleared, iclass 2 cls_cnt 0 2006.202.01:43:32.31$vck44/vb=5,4 2006.202.01:43:32.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.202.01:43:32.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.202.01:43:32.31#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:32.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:32.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:32.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:32.37#ibcon#enter wrdev, iclass 5, count 2 2006.202.01:43:32.37#ibcon#first serial, iclass 5, count 2 2006.202.01:43:32.37#ibcon#enter sib2, iclass 5, count 2 2006.202.01:43:32.37#ibcon#flushed, iclass 5, count 2 2006.202.01:43:32.37#ibcon#about to write, iclass 5, count 2 2006.202.01:43:32.37#ibcon#wrote, iclass 5, count 2 2006.202.01:43:32.37#ibcon#about to read 3, iclass 5, count 2 2006.202.01:43:32.40#ibcon#read 3, iclass 5, count 2 2006.202.01:43:32.40#ibcon#about to read 4, iclass 5, count 2 2006.202.01:43:32.40#ibcon#read 4, iclass 5, count 2 2006.202.01:43:32.40#ibcon#about to read 5, iclass 5, count 2 2006.202.01:43:32.40#ibcon#read 5, iclass 5, count 2 2006.202.01:43:32.40#ibcon#about to read 6, iclass 5, count 2 2006.202.01:43:32.40#ibcon#read 6, iclass 5, count 2 2006.202.01:43:32.40#ibcon#end of sib2, iclass 5, count 2 2006.202.01:43:32.40#ibcon#*mode == 0, iclass 5, count 2 2006.202.01:43:32.40#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.202.01:43:32.40#ibcon#[27=AT05-04\r\n] 2006.202.01:43:32.40#ibcon#*before write, iclass 5, count 2 2006.202.01:43:32.40#ibcon#enter sib2, iclass 5, count 2 2006.202.01:43:32.40#ibcon#flushed, iclass 5, count 2 2006.202.01:43:32.40#ibcon#about to write, iclass 5, count 2 2006.202.01:43:32.40#ibcon#wrote, iclass 5, count 2 2006.202.01:43:32.40#ibcon#about to read 3, iclass 5, count 2 2006.202.01:43:32.44#ibcon#read 3, iclass 5, count 2 2006.202.01:43:32.44#ibcon#about to read 4, iclass 5, count 2 2006.202.01:43:32.44#ibcon#read 4, iclass 5, count 2 2006.202.01:43:32.44#ibcon#about to read 5, iclass 5, count 2 2006.202.01:43:32.44#ibcon#read 5, iclass 5, count 2 2006.202.01:43:32.44#ibcon#about to read 6, iclass 5, count 2 2006.202.01:43:32.44#ibcon#read 6, iclass 5, count 2 2006.202.01:43:32.44#ibcon#end of sib2, iclass 5, count 2 2006.202.01:43:32.44#ibcon#*after write, iclass 5, count 2 2006.202.01:43:32.44#ibcon#*before return 0, iclass 5, count 2 2006.202.01:43:32.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:32.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.202.01:43:32.44#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.202.01:43:32.44#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:32.44#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:32.56#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:32.56#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:32.56#ibcon#enter wrdev, iclass 5, count 0 2006.202.01:43:32.56#ibcon#first serial, iclass 5, count 0 2006.202.01:43:32.56#ibcon#enter sib2, iclass 5, count 0 2006.202.01:43:32.56#ibcon#flushed, iclass 5, count 0 2006.202.01:43:32.56#ibcon#about to write, iclass 5, count 0 2006.202.01:43:32.56#ibcon#wrote, iclass 5, count 0 2006.202.01:43:32.56#ibcon#about to read 3, iclass 5, count 0 2006.202.01:43:32.58#ibcon#read 3, iclass 5, count 0 2006.202.01:43:32.58#ibcon#about to read 4, iclass 5, count 0 2006.202.01:43:32.58#ibcon#read 4, iclass 5, count 0 2006.202.01:43:32.58#ibcon#about to read 5, iclass 5, count 0 2006.202.01:43:32.58#ibcon#read 5, iclass 5, count 0 2006.202.01:43:32.58#ibcon#about to read 6, iclass 5, count 0 2006.202.01:43:32.58#ibcon#read 6, iclass 5, count 0 2006.202.01:43:32.58#ibcon#end of sib2, iclass 5, count 0 2006.202.01:43:32.58#ibcon#*mode == 0, iclass 5, count 0 2006.202.01:43:32.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.202.01:43:32.58#ibcon#[27=USB\r\n] 2006.202.01:43:32.58#ibcon#*before write, iclass 5, count 0 2006.202.01:43:32.58#ibcon#enter sib2, iclass 5, count 0 2006.202.01:43:32.58#ibcon#flushed, iclass 5, count 0 2006.202.01:43:32.58#ibcon#about to write, iclass 5, count 0 2006.202.01:43:32.58#ibcon#wrote, iclass 5, count 0 2006.202.01:43:32.58#ibcon#about to read 3, iclass 5, count 0 2006.202.01:43:32.61#ibcon#read 3, iclass 5, count 0 2006.202.01:43:32.61#ibcon#about to read 4, iclass 5, count 0 2006.202.01:43:32.61#ibcon#read 4, iclass 5, count 0 2006.202.01:43:32.61#ibcon#about to read 5, iclass 5, count 0 2006.202.01:43:32.61#ibcon#read 5, iclass 5, count 0 2006.202.01:43:32.61#ibcon#about to read 6, iclass 5, count 0 2006.202.01:43:32.61#ibcon#read 6, iclass 5, count 0 2006.202.01:43:32.61#ibcon#end of sib2, iclass 5, count 0 2006.202.01:43:32.61#ibcon#*after write, iclass 5, count 0 2006.202.01:43:32.61#ibcon#*before return 0, iclass 5, count 0 2006.202.01:43:32.61#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:32.61#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.202.01:43:32.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.202.01:43:32.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.202.01:43:32.61$vck44/vblo=6,719.99 2006.202.01:43:32.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.202.01:43:32.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.202.01:43:32.61#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:32.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:32.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:32.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:32.61#ibcon#enter wrdev, iclass 7, count 0 2006.202.01:43:32.61#ibcon#first serial, iclass 7, count 0 2006.202.01:43:32.61#ibcon#enter sib2, iclass 7, count 0 2006.202.01:43:32.61#ibcon#flushed, iclass 7, count 0 2006.202.01:43:32.61#ibcon#about to write, iclass 7, count 0 2006.202.01:43:32.61#ibcon#wrote, iclass 7, count 0 2006.202.01:43:32.61#ibcon#about to read 3, iclass 7, count 0 2006.202.01:43:32.63#ibcon#read 3, iclass 7, count 0 2006.202.01:43:32.63#ibcon#about to read 4, iclass 7, count 0 2006.202.01:43:32.63#ibcon#read 4, iclass 7, count 0 2006.202.01:43:32.63#ibcon#about to read 5, iclass 7, count 0 2006.202.01:43:32.63#ibcon#read 5, iclass 7, count 0 2006.202.01:43:32.63#ibcon#about to read 6, iclass 7, count 0 2006.202.01:43:32.63#ibcon#read 6, iclass 7, count 0 2006.202.01:43:32.63#ibcon#end of sib2, iclass 7, count 0 2006.202.01:43:32.63#ibcon#*mode == 0, iclass 7, count 0 2006.202.01:43:32.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.202.01:43:32.63#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.01:43:32.63#ibcon#*before write, iclass 7, count 0 2006.202.01:43:32.63#ibcon#enter sib2, iclass 7, count 0 2006.202.01:43:32.63#ibcon#flushed, iclass 7, count 0 2006.202.01:43:32.63#ibcon#about to write, iclass 7, count 0 2006.202.01:43:32.63#ibcon#wrote, iclass 7, count 0 2006.202.01:43:32.63#ibcon#about to read 3, iclass 7, count 0 2006.202.01:43:32.67#ibcon#read 3, iclass 7, count 0 2006.202.01:43:32.67#ibcon#about to read 4, iclass 7, count 0 2006.202.01:43:32.67#ibcon#read 4, iclass 7, count 0 2006.202.01:43:32.67#ibcon#about to read 5, iclass 7, count 0 2006.202.01:43:32.67#ibcon#read 5, iclass 7, count 0 2006.202.01:43:32.67#ibcon#about to read 6, iclass 7, count 0 2006.202.01:43:32.67#ibcon#read 6, iclass 7, count 0 2006.202.01:43:32.67#ibcon#end of sib2, iclass 7, count 0 2006.202.01:43:32.67#ibcon#*after write, iclass 7, count 0 2006.202.01:43:32.67#ibcon#*before return 0, iclass 7, count 0 2006.202.01:43:32.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:32.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.202.01:43:32.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.202.01:43:32.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.202.01:43:32.67$vck44/vb=6,4 2006.202.01:43:32.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.202.01:43:32.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.202.01:43:32.67#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:32.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:32.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:32.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:32.73#ibcon#enter wrdev, iclass 11, count 2 2006.202.01:43:32.73#ibcon#first serial, iclass 11, count 2 2006.202.01:43:32.73#ibcon#enter sib2, iclass 11, count 2 2006.202.01:43:32.73#ibcon#flushed, iclass 11, count 2 2006.202.01:43:32.73#ibcon#about to write, iclass 11, count 2 2006.202.01:43:32.73#ibcon#wrote, iclass 11, count 2 2006.202.01:43:32.73#ibcon#about to read 3, iclass 11, count 2 2006.202.01:43:32.75#ibcon#read 3, iclass 11, count 2 2006.202.01:43:32.75#ibcon#about to read 4, iclass 11, count 2 2006.202.01:43:32.75#ibcon#read 4, iclass 11, count 2 2006.202.01:43:32.75#ibcon#about to read 5, iclass 11, count 2 2006.202.01:43:32.75#ibcon#read 5, iclass 11, count 2 2006.202.01:43:32.75#ibcon#about to read 6, iclass 11, count 2 2006.202.01:43:32.75#ibcon#read 6, iclass 11, count 2 2006.202.01:43:32.75#ibcon#end of sib2, iclass 11, count 2 2006.202.01:43:32.75#ibcon#*mode == 0, iclass 11, count 2 2006.202.01:43:32.75#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.202.01:43:32.75#ibcon#[27=AT06-04\r\n] 2006.202.01:43:32.75#ibcon#*before write, iclass 11, count 2 2006.202.01:43:32.75#ibcon#enter sib2, iclass 11, count 2 2006.202.01:43:32.75#ibcon#flushed, iclass 11, count 2 2006.202.01:43:32.75#ibcon#about to write, iclass 11, count 2 2006.202.01:43:32.75#ibcon#wrote, iclass 11, count 2 2006.202.01:43:32.75#ibcon#about to read 3, iclass 11, count 2 2006.202.01:43:32.78#ibcon#read 3, iclass 11, count 2 2006.202.01:43:32.78#ibcon#about to read 4, iclass 11, count 2 2006.202.01:43:32.78#ibcon#read 4, iclass 11, count 2 2006.202.01:43:32.78#ibcon#about to read 5, iclass 11, count 2 2006.202.01:43:32.78#ibcon#read 5, iclass 11, count 2 2006.202.01:43:32.78#ibcon#about to read 6, iclass 11, count 2 2006.202.01:43:32.78#ibcon#read 6, iclass 11, count 2 2006.202.01:43:32.78#ibcon#end of sib2, iclass 11, count 2 2006.202.01:43:32.78#ibcon#*after write, iclass 11, count 2 2006.202.01:43:32.78#ibcon#*before return 0, iclass 11, count 2 2006.202.01:43:32.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:32.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.202.01:43:32.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.202.01:43:32.78#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:32.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:32.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:32.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:32.90#ibcon#enter wrdev, iclass 11, count 0 2006.202.01:43:32.90#ibcon#first serial, iclass 11, count 0 2006.202.01:43:32.90#ibcon#enter sib2, iclass 11, count 0 2006.202.01:43:32.90#ibcon#flushed, iclass 11, count 0 2006.202.01:43:32.90#ibcon#about to write, iclass 11, count 0 2006.202.01:43:32.90#ibcon#wrote, iclass 11, count 0 2006.202.01:43:32.90#ibcon#about to read 3, iclass 11, count 0 2006.202.01:43:32.92#ibcon#read 3, iclass 11, count 0 2006.202.01:43:32.92#ibcon#about to read 4, iclass 11, count 0 2006.202.01:43:32.92#ibcon#read 4, iclass 11, count 0 2006.202.01:43:32.92#ibcon#about to read 5, iclass 11, count 0 2006.202.01:43:32.92#ibcon#read 5, iclass 11, count 0 2006.202.01:43:32.92#ibcon#about to read 6, iclass 11, count 0 2006.202.01:43:32.92#ibcon#read 6, iclass 11, count 0 2006.202.01:43:32.92#ibcon#end of sib2, iclass 11, count 0 2006.202.01:43:32.92#ibcon#*mode == 0, iclass 11, count 0 2006.202.01:43:32.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.202.01:43:32.92#ibcon#[27=USB\r\n] 2006.202.01:43:32.92#ibcon#*before write, iclass 11, count 0 2006.202.01:43:32.92#ibcon#enter sib2, iclass 11, count 0 2006.202.01:43:32.92#ibcon#flushed, iclass 11, count 0 2006.202.01:43:32.92#ibcon#about to write, iclass 11, count 0 2006.202.01:43:32.92#ibcon#wrote, iclass 11, count 0 2006.202.01:43:32.92#ibcon#about to read 3, iclass 11, count 0 2006.202.01:43:32.95#ibcon#read 3, iclass 11, count 0 2006.202.01:43:32.95#ibcon#about to read 4, iclass 11, count 0 2006.202.01:43:32.95#ibcon#read 4, iclass 11, count 0 2006.202.01:43:32.95#ibcon#about to read 5, iclass 11, count 0 2006.202.01:43:32.95#ibcon#read 5, iclass 11, count 0 2006.202.01:43:32.95#ibcon#about to read 6, iclass 11, count 0 2006.202.01:43:32.95#ibcon#read 6, iclass 11, count 0 2006.202.01:43:32.95#ibcon#end of sib2, iclass 11, count 0 2006.202.01:43:32.95#ibcon#*after write, iclass 11, count 0 2006.202.01:43:32.95#ibcon#*before return 0, iclass 11, count 0 2006.202.01:43:32.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:32.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.202.01:43:32.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.202.01:43:32.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.202.01:43:32.95$vck44/vblo=7,734.99 2006.202.01:43:32.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.202.01:43:32.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.202.01:43:32.95#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:32.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:32.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:32.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:32.95#ibcon#enter wrdev, iclass 13, count 0 2006.202.01:43:32.95#ibcon#first serial, iclass 13, count 0 2006.202.01:43:32.95#ibcon#enter sib2, iclass 13, count 0 2006.202.01:43:32.95#ibcon#flushed, iclass 13, count 0 2006.202.01:43:32.95#ibcon#about to write, iclass 13, count 0 2006.202.01:43:32.95#ibcon#wrote, iclass 13, count 0 2006.202.01:43:32.95#ibcon#about to read 3, iclass 13, count 0 2006.202.01:43:32.97#ibcon#read 3, iclass 13, count 0 2006.202.01:43:32.97#ibcon#about to read 4, iclass 13, count 0 2006.202.01:43:32.97#ibcon#read 4, iclass 13, count 0 2006.202.01:43:32.97#ibcon#about to read 5, iclass 13, count 0 2006.202.01:43:32.97#ibcon#read 5, iclass 13, count 0 2006.202.01:43:32.97#ibcon#about to read 6, iclass 13, count 0 2006.202.01:43:32.97#ibcon#read 6, iclass 13, count 0 2006.202.01:43:32.97#ibcon#end of sib2, iclass 13, count 0 2006.202.01:43:32.97#ibcon#*mode == 0, iclass 13, count 0 2006.202.01:43:32.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.202.01:43:32.97#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.01:43:32.97#ibcon#*before write, iclass 13, count 0 2006.202.01:43:32.97#ibcon#enter sib2, iclass 13, count 0 2006.202.01:43:32.97#ibcon#flushed, iclass 13, count 0 2006.202.01:43:32.97#ibcon#about to write, iclass 13, count 0 2006.202.01:43:32.97#ibcon#wrote, iclass 13, count 0 2006.202.01:43:32.97#ibcon#about to read 3, iclass 13, count 0 2006.202.01:43:33.01#ibcon#read 3, iclass 13, count 0 2006.202.01:43:33.01#ibcon#about to read 4, iclass 13, count 0 2006.202.01:43:33.01#ibcon#read 4, iclass 13, count 0 2006.202.01:43:33.01#ibcon#about to read 5, iclass 13, count 0 2006.202.01:43:33.01#ibcon#read 5, iclass 13, count 0 2006.202.01:43:33.01#ibcon#about to read 6, iclass 13, count 0 2006.202.01:43:33.01#ibcon#read 6, iclass 13, count 0 2006.202.01:43:33.01#ibcon#end of sib2, iclass 13, count 0 2006.202.01:43:33.01#ibcon#*after write, iclass 13, count 0 2006.202.01:43:33.01#ibcon#*before return 0, iclass 13, count 0 2006.202.01:43:33.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:33.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.202.01:43:33.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.202.01:43:33.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.202.01:43:33.01$vck44/vb=7,4 2006.202.01:43:33.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.202.01:43:33.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.202.01:43:33.01#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:33.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:33.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:33.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:33.07#ibcon#enter wrdev, iclass 15, count 2 2006.202.01:43:33.07#ibcon#first serial, iclass 15, count 2 2006.202.01:43:33.07#ibcon#enter sib2, iclass 15, count 2 2006.202.01:43:33.07#ibcon#flushed, iclass 15, count 2 2006.202.01:43:33.07#ibcon#about to write, iclass 15, count 2 2006.202.01:43:33.07#ibcon#wrote, iclass 15, count 2 2006.202.01:43:33.07#ibcon#about to read 3, iclass 15, count 2 2006.202.01:43:33.09#ibcon#read 3, iclass 15, count 2 2006.202.01:43:33.09#ibcon#about to read 4, iclass 15, count 2 2006.202.01:43:33.09#ibcon#read 4, iclass 15, count 2 2006.202.01:43:33.09#ibcon#about to read 5, iclass 15, count 2 2006.202.01:43:33.09#ibcon#read 5, iclass 15, count 2 2006.202.01:43:33.09#ibcon#about to read 6, iclass 15, count 2 2006.202.01:43:33.09#ibcon#read 6, iclass 15, count 2 2006.202.01:43:33.09#ibcon#end of sib2, iclass 15, count 2 2006.202.01:43:33.09#ibcon#*mode == 0, iclass 15, count 2 2006.202.01:43:33.09#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.202.01:43:33.09#ibcon#[27=AT07-04\r\n] 2006.202.01:43:33.09#ibcon#*before write, iclass 15, count 2 2006.202.01:43:33.09#ibcon#enter sib2, iclass 15, count 2 2006.202.01:43:33.09#ibcon#flushed, iclass 15, count 2 2006.202.01:43:33.09#ibcon#about to write, iclass 15, count 2 2006.202.01:43:33.09#ibcon#wrote, iclass 15, count 2 2006.202.01:43:33.09#ibcon#about to read 3, iclass 15, count 2 2006.202.01:43:33.12#ibcon#read 3, iclass 15, count 2 2006.202.01:43:33.12#ibcon#about to read 4, iclass 15, count 2 2006.202.01:43:33.12#ibcon#read 4, iclass 15, count 2 2006.202.01:43:33.12#ibcon#about to read 5, iclass 15, count 2 2006.202.01:43:33.12#ibcon#read 5, iclass 15, count 2 2006.202.01:43:33.12#ibcon#about to read 6, iclass 15, count 2 2006.202.01:43:33.12#ibcon#read 6, iclass 15, count 2 2006.202.01:43:33.12#ibcon#end of sib2, iclass 15, count 2 2006.202.01:43:33.12#ibcon#*after write, iclass 15, count 2 2006.202.01:43:33.12#ibcon#*before return 0, iclass 15, count 2 2006.202.01:43:33.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:33.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.202.01:43:33.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.202.01:43:33.12#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:33.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:33.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:33.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:33.24#ibcon#enter wrdev, iclass 15, count 0 2006.202.01:43:33.24#ibcon#first serial, iclass 15, count 0 2006.202.01:43:33.24#ibcon#enter sib2, iclass 15, count 0 2006.202.01:43:33.24#ibcon#flushed, iclass 15, count 0 2006.202.01:43:33.24#ibcon#about to write, iclass 15, count 0 2006.202.01:43:33.24#ibcon#wrote, iclass 15, count 0 2006.202.01:43:33.24#ibcon#about to read 3, iclass 15, count 0 2006.202.01:43:33.26#ibcon#read 3, iclass 15, count 0 2006.202.01:43:33.26#ibcon#about to read 4, iclass 15, count 0 2006.202.01:43:33.26#ibcon#read 4, iclass 15, count 0 2006.202.01:43:33.26#ibcon#about to read 5, iclass 15, count 0 2006.202.01:43:33.26#ibcon#read 5, iclass 15, count 0 2006.202.01:43:33.26#ibcon#about to read 6, iclass 15, count 0 2006.202.01:43:33.26#ibcon#read 6, iclass 15, count 0 2006.202.01:43:33.26#ibcon#end of sib2, iclass 15, count 0 2006.202.01:43:33.26#ibcon#*mode == 0, iclass 15, count 0 2006.202.01:43:33.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.202.01:43:33.26#ibcon#[27=USB\r\n] 2006.202.01:43:33.26#ibcon#*before write, iclass 15, count 0 2006.202.01:43:33.26#ibcon#enter sib2, iclass 15, count 0 2006.202.01:43:33.26#ibcon#flushed, iclass 15, count 0 2006.202.01:43:33.26#ibcon#about to write, iclass 15, count 0 2006.202.01:43:33.26#ibcon#wrote, iclass 15, count 0 2006.202.01:43:33.26#ibcon#about to read 3, iclass 15, count 0 2006.202.01:43:33.29#ibcon#read 3, iclass 15, count 0 2006.202.01:43:33.29#ibcon#about to read 4, iclass 15, count 0 2006.202.01:43:33.29#ibcon#read 4, iclass 15, count 0 2006.202.01:43:33.29#ibcon#about to read 5, iclass 15, count 0 2006.202.01:43:33.29#ibcon#read 5, iclass 15, count 0 2006.202.01:43:33.29#ibcon#about to read 6, iclass 15, count 0 2006.202.01:43:33.29#ibcon#read 6, iclass 15, count 0 2006.202.01:43:33.29#ibcon#end of sib2, iclass 15, count 0 2006.202.01:43:33.29#ibcon#*after write, iclass 15, count 0 2006.202.01:43:33.29#ibcon#*before return 0, iclass 15, count 0 2006.202.01:43:33.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:33.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.202.01:43:33.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.202.01:43:33.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.202.01:43:33.29$vck44/vblo=8,744.99 2006.202.01:43:33.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.202.01:43:33.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.202.01:43:33.29#ibcon#ireg 17 cls_cnt 0 2006.202.01:43:33.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:33.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:33.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:33.29#ibcon#enter wrdev, iclass 17, count 0 2006.202.01:43:33.29#ibcon#first serial, iclass 17, count 0 2006.202.01:43:33.29#ibcon#enter sib2, iclass 17, count 0 2006.202.01:43:33.29#ibcon#flushed, iclass 17, count 0 2006.202.01:43:33.29#ibcon#about to write, iclass 17, count 0 2006.202.01:43:33.29#ibcon#wrote, iclass 17, count 0 2006.202.01:43:33.29#ibcon#about to read 3, iclass 17, count 0 2006.202.01:43:33.31#ibcon#read 3, iclass 17, count 0 2006.202.01:43:33.31#ibcon#about to read 4, iclass 17, count 0 2006.202.01:43:33.31#ibcon#read 4, iclass 17, count 0 2006.202.01:43:33.31#ibcon#about to read 5, iclass 17, count 0 2006.202.01:43:33.31#ibcon#read 5, iclass 17, count 0 2006.202.01:43:33.31#ibcon#about to read 6, iclass 17, count 0 2006.202.01:43:33.31#ibcon#read 6, iclass 17, count 0 2006.202.01:43:33.31#ibcon#end of sib2, iclass 17, count 0 2006.202.01:43:33.31#ibcon#*mode == 0, iclass 17, count 0 2006.202.01:43:33.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.202.01:43:33.31#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.01:43:33.31#ibcon#*before write, iclass 17, count 0 2006.202.01:43:33.31#ibcon#enter sib2, iclass 17, count 0 2006.202.01:43:33.31#ibcon#flushed, iclass 17, count 0 2006.202.01:43:33.31#ibcon#about to write, iclass 17, count 0 2006.202.01:43:33.31#ibcon#wrote, iclass 17, count 0 2006.202.01:43:33.31#ibcon#about to read 3, iclass 17, count 0 2006.202.01:43:33.35#ibcon#read 3, iclass 17, count 0 2006.202.01:43:33.35#ibcon#about to read 4, iclass 17, count 0 2006.202.01:43:33.35#ibcon#read 4, iclass 17, count 0 2006.202.01:43:33.35#ibcon#about to read 5, iclass 17, count 0 2006.202.01:43:33.35#ibcon#read 5, iclass 17, count 0 2006.202.01:43:33.35#ibcon#about to read 6, iclass 17, count 0 2006.202.01:43:33.35#ibcon#read 6, iclass 17, count 0 2006.202.01:43:33.35#ibcon#end of sib2, iclass 17, count 0 2006.202.01:43:33.35#ibcon#*after write, iclass 17, count 0 2006.202.01:43:33.35#ibcon#*before return 0, iclass 17, count 0 2006.202.01:43:33.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:33.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.202.01:43:33.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.202.01:43:33.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.202.01:43:33.35$vck44/vb=8,4 2006.202.01:43:33.35#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.202.01:43:33.35#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.202.01:43:33.35#ibcon#ireg 11 cls_cnt 2 2006.202.01:43:33.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:33.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:33.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:33.41#ibcon#enter wrdev, iclass 19, count 2 2006.202.01:43:33.41#ibcon#first serial, iclass 19, count 2 2006.202.01:43:33.41#ibcon#enter sib2, iclass 19, count 2 2006.202.01:43:33.41#ibcon#flushed, iclass 19, count 2 2006.202.01:43:33.41#ibcon#about to write, iclass 19, count 2 2006.202.01:43:33.41#ibcon#wrote, iclass 19, count 2 2006.202.01:43:33.41#ibcon#about to read 3, iclass 19, count 2 2006.202.01:43:33.43#ibcon#read 3, iclass 19, count 2 2006.202.01:43:33.43#ibcon#about to read 4, iclass 19, count 2 2006.202.01:43:33.43#ibcon#read 4, iclass 19, count 2 2006.202.01:43:33.43#ibcon#about to read 5, iclass 19, count 2 2006.202.01:43:33.43#ibcon#read 5, iclass 19, count 2 2006.202.01:43:33.43#ibcon#about to read 6, iclass 19, count 2 2006.202.01:43:33.43#ibcon#read 6, iclass 19, count 2 2006.202.01:43:33.43#ibcon#end of sib2, iclass 19, count 2 2006.202.01:43:33.43#ibcon#*mode == 0, iclass 19, count 2 2006.202.01:43:33.43#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.202.01:43:33.43#ibcon#[27=AT08-04\r\n] 2006.202.01:43:33.43#ibcon#*before write, iclass 19, count 2 2006.202.01:43:33.43#ibcon#enter sib2, iclass 19, count 2 2006.202.01:43:33.43#ibcon#flushed, iclass 19, count 2 2006.202.01:43:33.43#ibcon#about to write, iclass 19, count 2 2006.202.01:43:33.43#ibcon#wrote, iclass 19, count 2 2006.202.01:43:33.43#ibcon#about to read 3, iclass 19, count 2 2006.202.01:43:33.46#ibcon#read 3, iclass 19, count 2 2006.202.01:43:33.46#ibcon#about to read 4, iclass 19, count 2 2006.202.01:43:33.46#ibcon#read 4, iclass 19, count 2 2006.202.01:43:33.46#ibcon#about to read 5, iclass 19, count 2 2006.202.01:43:33.46#ibcon#read 5, iclass 19, count 2 2006.202.01:43:33.46#ibcon#about to read 6, iclass 19, count 2 2006.202.01:43:33.46#ibcon#read 6, iclass 19, count 2 2006.202.01:43:33.46#ibcon#end of sib2, iclass 19, count 2 2006.202.01:43:33.46#ibcon#*after write, iclass 19, count 2 2006.202.01:43:33.46#ibcon#*before return 0, iclass 19, count 2 2006.202.01:43:33.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:33.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.202.01:43:33.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.202.01:43:33.46#ibcon#ireg 7 cls_cnt 0 2006.202.01:43:33.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:33.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:33.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:33.58#ibcon#enter wrdev, iclass 19, count 0 2006.202.01:43:33.58#ibcon#first serial, iclass 19, count 0 2006.202.01:43:33.58#ibcon#enter sib2, iclass 19, count 0 2006.202.01:43:33.58#ibcon#flushed, iclass 19, count 0 2006.202.01:43:33.58#ibcon#about to write, iclass 19, count 0 2006.202.01:43:33.58#ibcon#wrote, iclass 19, count 0 2006.202.01:43:33.58#ibcon#about to read 3, iclass 19, count 0 2006.202.01:43:33.60#ibcon#read 3, iclass 19, count 0 2006.202.01:43:33.60#ibcon#about to read 4, iclass 19, count 0 2006.202.01:43:33.60#ibcon#read 4, iclass 19, count 0 2006.202.01:43:33.60#ibcon#about to read 5, iclass 19, count 0 2006.202.01:43:33.60#ibcon#read 5, iclass 19, count 0 2006.202.01:43:33.60#ibcon#about to read 6, iclass 19, count 0 2006.202.01:43:33.60#ibcon#read 6, iclass 19, count 0 2006.202.01:43:33.60#ibcon#end of sib2, iclass 19, count 0 2006.202.01:43:33.60#ibcon#*mode == 0, iclass 19, count 0 2006.202.01:43:33.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.202.01:43:33.60#ibcon#[27=USB\r\n] 2006.202.01:43:33.60#ibcon#*before write, iclass 19, count 0 2006.202.01:43:33.60#ibcon#enter sib2, iclass 19, count 0 2006.202.01:43:33.60#ibcon#flushed, iclass 19, count 0 2006.202.01:43:33.60#ibcon#about to write, iclass 19, count 0 2006.202.01:43:33.60#ibcon#wrote, iclass 19, count 0 2006.202.01:43:33.60#ibcon#about to read 3, iclass 19, count 0 2006.202.01:43:33.63#ibcon#read 3, iclass 19, count 0 2006.202.01:43:33.63#ibcon#about to read 4, iclass 19, count 0 2006.202.01:43:33.63#ibcon#read 4, iclass 19, count 0 2006.202.01:43:33.63#ibcon#about to read 5, iclass 19, count 0 2006.202.01:43:33.63#ibcon#read 5, iclass 19, count 0 2006.202.01:43:33.63#ibcon#about to read 6, iclass 19, count 0 2006.202.01:43:33.63#ibcon#read 6, iclass 19, count 0 2006.202.01:43:33.63#ibcon#end of sib2, iclass 19, count 0 2006.202.01:43:33.63#ibcon#*after write, iclass 19, count 0 2006.202.01:43:33.63#ibcon#*before return 0, iclass 19, count 0 2006.202.01:43:33.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:33.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.202.01:43:33.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.202.01:43:33.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.202.01:43:33.63$vck44/vabw=wide 2006.202.01:43:33.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.202.01:43:33.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.202.01:43:33.63#ibcon#ireg 8 cls_cnt 0 2006.202.01:43:33.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:33.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:33.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:33.63#ibcon#enter wrdev, iclass 21, count 0 2006.202.01:43:33.63#ibcon#first serial, iclass 21, count 0 2006.202.01:43:33.63#ibcon#enter sib2, iclass 21, count 0 2006.202.01:43:33.63#ibcon#flushed, iclass 21, count 0 2006.202.01:43:33.63#ibcon#about to write, iclass 21, count 0 2006.202.01:43:33.63#ibcon#wrote, iclass 21, count 0 2006.202.01:43:33.63#ibcon#about to read 3, iclass 21, count 0 2006.202.01:43:33.65#ibcon#read 3, iclass 21, count 0 2006.202.01:43:33.65#ibcon#about to read 4, iclass 21, count 0 2006.202.01:43:33.65#ibcon#read 4, iclass 21, count 0 2006.202.01:43:33.65#ibcon#about to read 5, iclass 21, count 0 2006.202.01:43:33.65#ibcon#read 5, iclass 21, count 0 2006.202.01:43:33.65#ibcon#about to read 6, iclass 21, count 0 2006.202.01:43:33.65#ibcon#read 6, iclass 21, count 0 2006.202.01:43:33.65#ibcon#end of sib2, iclass 21, count 0 2006.202.01:43:33.65#ibcon#*mode == 0, iclass 21, count 0 2006.202.01:43:33.65#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.202.01:43:33.65#ibcon#[25=BW32\r\n] 2006.202.01:43:33.65#ibcon#*before write, iclass 21, count 0 2006.202.01:43:33.65#ibcon#enter sib2, iclass 21, count 0 2006.202.01:43:33.65#ibcon#flushed, iclass 21, count 0 2006.202.01:43:33.65#ibcon#about to write, iclass 21, count 0 2006.202.01:43:33.65#ibcon#wrote, iclass 21, count 0 2006.202.01:43:33.65#ibcon#about to read 3, iclass 21, count 0 2006.202.01:43:33.68#ibcon#read 3, iclass 21, count 0 2006.202.01:43:33.68#ibcon#about to read 4, iclass 21, count 0 2006.202.01:43:33.68#ibcon#read 4, iclass 21, count 0 2006.202.01:43:33.68#ibcon#about to read 5, iclass 21, count 0 2006.202.01:43:33.68#ibcon#read 5, iclass 21, count 0 2006.202.01:43:33.68#ibcon#about to read 6, iclass 21, count 0 2006.202.01:43:33.68#ibcon#read 6, iclass 21, count 0 2006.202.01:43:33.68#ibcon#end of sib2, iclass 21, count 0 2006.202.01:43:33.68#ibcon#*after write, iclass 21, count 0 2006.202.01:43:33.68#ibcon#*before return 0, iclass 21, count 0 2006.202.01:43:33.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:33.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.202.01:43:33.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.202.01:43:33.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.202.01:43:33.68$vck44/vbbw=wide 2006.202.01:43:33.68#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.202.01:43:33.68#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.202.01:43:33.68#ibcon#ireg 8 cls_cnt 0 2006.202.01:43:33.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:43:33.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:43:33.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:43:33.75#ibcon#enter wrdev, iclass 23, count 0 2006.202.01:43:33.75#ibcon#first serial, iclass 23, count 0 2006.202.01:43:33.75#ibcon#enter sib2, iclass 23, count 0 2006.202.01:43:33.75#ibcon#flushed, iclass 23, count 0 2006.202.01:43:33.75#ibcon#about to write, iclass 23, count 0 2006.202.01:43:33.75#ibcon#wrote, iclass 23, count 0 2006.202.01:43:33.75#ibcon#about to read 3, iclass 23, count 0 2006.202.01:43:33.77#ibcon#read 3, iclass 23, count 0 2006.202.01:43:33.77#ibcon#about to read 4, iclass 23, count 0 2006.202.01:43:33.77#ibcon#read 4, iclass 23, count 0 2006.202.01:43:33.77#ibcon#about to read 5, iclass 23, count 0 2006.202.01:43:33.77#ibcon#read 5, iclass 23, count 0 2006.202.01:43:33.77#ibcon#about to read 6, iclass 23, count 0 2006.202.01:43:33.77#ibcon#read 6, iclass 23, count 0 2006.202.01:43:33.77#ibcon#end of sib2, iclass 23, count 0 2006.202.01:43:33.77#ibcon#*mode == 0, iclass 23, count 0 2006.202.01:43:33.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.202.01:43:33.77#ibcon#[27=BW32\r\n] 2006.202.01:43:33.77#ibcon#*before write, iclass 23, count 0 2006.202.01:43:33.77#ibcon#enter sib2, iclass 23, count 0 2006.202.01:43:33.77#ibcon#flushed, iclass 23, count 0 2006.202.01:43:33.77#ibcon#about to write, iclass 23, count 0 2006.202.01:43:33.77#ibcon#wrote, iclass 23, count 0 2006.202.01:43:33.77#ibcon#about to read 3, iclass 23, count 0 2006.202.01:43:33.80#ibcon#read 3, iclass 23, count 0 2006.202.01:43:33.80#ibcon#about to read 4, iclass 23, count 0 2006.202.01:43:33.80#ibcon#read 4, iclass 23, count 0 2006.202.01:43:33.80#ibcon#about to read 5, iclass 23, count 0 2006.202.01:43:33.80#ibcon#read 5, iclass 23, count 0 2006.202.01:43:33.80#ibcon#about to read 6, iclass 23, count 0 2006.202.01:43:33.80#ibcon#read 6, iclass 23, count 0 2006.202.01:43:33.80#ibcon#end of sib2, iclass 23, count 0 2006.202.01:43:33.80#ibcon#*after write, iclass 23, count 0 2006.202.01:43:33.80#ibcon#*before return 0, iclass 23, count 0 2006.202.01:43:33.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:43:33.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.202.01:43:33.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.202.01:43:33.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.202.01:43:33.80$setupk4/ifdk4 2006.202.01:43:33.80$ifdk4/lo= 2006.202.01:43:33.80$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.01:43:33.80$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.01:43:33.80$ifdk4/patch= 2006.202.01:43:33.80$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.01:43:33.80$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.01:43:33.80$setupk4/!*+20s 2006.202.01:43:37.00#abcon#<5=/04 1.8 3.4 20.551001000.7\r\n> 2006.202.01:43:37.02#abcon#{5=INTERFACE CLEAR} 2006.202.01:43:37.09#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:43:47.18#abcon#<5=/04 1.8 3.4 20.541001000.7\r\n> 2006.202.01:43:47.20#abcon#{5=INTERFACE CLEAR} 2006.202.01:43:47.26#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:43:48.26$setupk4/"tpicd 2006.202.01:43:48.26$setupk4/echo=off 2006.202.01:43:48.26$setupk4/xlog=off 2006.202.01:43:48.26:!2006.202.01:45:58 2006.202.01:44:01.14#trakl#Source acquired 2006.202.01:44:02.14#flagr#flagr/antenna,acquired 2006.202.01:45:58.00:preob 2006.202.01:45:58.14/onsource/TRACKING 2006.202.01:45:58.14:!2006.202.01:46:08 2006.202.01:46:08.00:"tape 2006.202.01:46:08.00:"st=record 2006.202.01:46:08.00:data_valid=on 2006.202.01:46:08.00:midob 2006.202.01:46:08.14/onsource/TRACKING 2006.202.01:46:08.14/wx/20.54,1000.7,100 2006.202.01:46:08.34/cable/+6.4838E-03 2006.202.01:46:09.43/va/01,08,usb,yes,46,49 2006.202.01:46:09.43/va/02,07,usb,yes,50,51 2006.202.01:46:09.43/va/03,08,usb,yes,45,47 2006.202.01:46:09.43/va/04,07,usb,yes,51,54 2006.202.01:46:09.43/va/05,04,usb,yes,46,47 2006.202.01:46:09.43/va/06,05,usb,yes,46,46 2006.202.01:46:09.43/va/07,05,usb,yes,45,47 2006.202.01:46:09.43/va/08,04,usb,yes,45,53 2006.202.01:46:09.66/valo/01,524.99,yes,locked 2006.202.01:46:09.66/valo/02,534.99,yes,locked 2006.202.01:46:09.66/valo/03,564.99,yes,locked 2006.202.01:46:09.66/valo/04,624.99,yes,locked 2006.202.01:46:09.66/valo/05,734.99,yes,locked 2006.202.01:46:09.66/valo/06,814.99,yes,locked 2006.202.01:46:09.66/valo/07,864.99,yes,locked 2006.202.01:46:09.66/valo/08,884.99,yes,locked 2006.202.01:46:10.75/vb/01,04,usb,yes,31,29 2006.202.01:46:10.75/vb/02,05,usb,yes,29,29 2006.202.01:46:10.75/vb/03,04,usb,yes,30,33 2006.202.01:46:10.75/vb/04,05,usb,yes,31,29 2006.202.01:46:10.75/vb/05,04,usb,yes,27,30 2006.202.01:46:10.75/vb/06,04,usb,yes,32,28 2006.202.01:46:10.75/vb/07,04,usb,yes,31,31 2006.202.01:46:10.75/vb/08,04,usb,yes,29,32 2006.202.01:46:10.98/vblo/01,629.99,yes,locked 2006.202.01:46:10.98/vblo/02,634.99,yes,locked 2006.202.01:46:10.98/vblo/03,649.99,yes,locked 2006.202.01:46:10.98/vblo/04,679.99,yes,locked 2006.202.01:46:10.98/vblo/05,709.99,yes,locked 2006.202.01:46:10.98/vblo/06,719.99,yes,locked 2006.202.01:46:10.98/vblo/07,734.99,yes,locked 2006.202.01:46:10.98/vblo/08,744.99,yes,locked 2006.202.01:46:11.13/vabw/8 2006.202.01:46:11.28/vbbw/8 2006.202.01:46:11.42/xfe/off,on,15.0 2006.202.01:46:11.80/ifatt/23,28,28,28 2006.202.01:46:12.07/fmout-gps/S +4.50E-07 2006.202.01:46:12.11:!2006.202.01:49:58 2006.202.01:49:58.00:data_valid=off 2006.202.01:49:58.00:"et 2006.202.01:49:58.00:!+3s 2006.202.01:50:01.02:"tape 2006.202.01:50:01.02:postob 2006.202.01:50:01.10/cable/+6.4841E-03 2006.202.01:50:01.10/wx/20.60,1000.8,100 2006.202.01:50:01.16/fmout-gps/S +4.48E-07 2006.202.01:50:01.16:scan_name=202-0154,jd0607,40 2006.202.01:50:01.16:source=0537-441,053850.36,-440508.9,2000.0,ccw 2006.202.01:50:02.14#flagr#flagr/antenna,new-source 2006.202.01:50:02.14:checkk5 2006.202.01:50:02.66/chk_autoobs//k5ts1/ autoobs is running! 2006.202.01:50:03.09/chk_autoobs//k5ts2/ autoobs is running! 2006.202.01:50:03.51/chk_autoobs//k5ts3/ autoobs is running! 2006.202.01:50:03.97/chk_autoobs//k5ts4/ autoobs is running! 2006.202.01:50:04.38/chk_obsdata//k5ts1/T2020146??a.dat file size is correct (nominal:920MB, actual:916MB). 2006.202.01:50:04.79/chk_obsdata//k5ts2/T2020146??b.dat file size is correct (nominal:920MB, actual:916MB). 2006.202.01:50:05.20/chk_obsdata//k5ts3/T2020146??c.dat file size is correct (nominal:920MB, actual:916MB). 2006.202.01:50:05.59/chk_obsdata//k5ts4/T2020146??d.dat file size is correct (nominal:920MB, actual:916MB). 2006.202.01:50:06.37/k5log//k5ts1_log_newline 2006.202.01:50:07.14/k5log//k5ts2_log_newline 2006.202.01:50:07.86/k5log//k5ts3_log_newline 2006.202.01:50:08.89/k5log//k5ts4_log_newline 2006.202.01:50:08.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.01:50:08.91:setupk4=1 2006.202.01:50:08.91$setupk4/echo=on 2006.202.01:50:08.91$setupk4/pcalon 2006.202.01:50:08.91$pcalon/"no phase cal control is implemented here 2006.202.01:50:08.91$setupk4/"tpicd=stop 2006.202.01:50:08.91$setupk4/"rec=synch_on 2006.202.01:50:08.91$setupk4/"rec_mode=128 2006.202.01:50:08.91$setupk4/!* 2006.202.01:50:08.91$setupk4/recpk4 2006.202.01:50:08.91$recpk4/recpatch= 2006.202.01:50:08.92$recpk4/recpatch=1,a1u,2,a2u,3,a3u,4,a4u,5,a5u,6,a6u,7,a7u,8,a8u,9,b1u 2006.202.01:50:08.92$recpk4/recpatch=10,b2u,11,b3u,12,b4u,13,b5u,14,b6u,15,b7u,16,b8u 2006.202.01:50:08.92$setupk4/vck44 2006.202.01:50:08.92$vck44/valo=1,524.99 2006.202.01:50:08.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.202.01:50:08.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.202.01:50:08.92#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:08.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:08.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:08.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:08.92#ibcon#enter wrdev, iclass 40, count 0 2006.202.01:50:08.92#ibcon#first serial, iclass 40, count 0 2006.202.01:50:08.92#ibcon#enter sib2, iclass 40, count 0 2006.202.01:50:08.92#ibcon#flushed, iclass 40, count 0 2006.202.01:50:08.92#ibcon#about to write, iclass 40, count 0 2006.202.01:50:08.92#ibcon#wrote, iclass 40, count 0 2006.202.01:50:08.92#ibcon#about to read 3, iclass 40, count 0 2006.202.01:50:08.96#ibcon#read 3, iclass 40, count 0 2006.202.01:50:08.96#ibcon#about to read 4, iclass 40, count 0 2006.202.01:50:08.96#ibcon#read 4, iclass 40, count 0 2006.202.01:50:08.96#ibcon#about to read 5, iclass 40, count 0 2006.202.01:50:08.96#ibcon#read 5, iclass 40, count 0 2006.202.01:50:08.96#ibcon#about to read 6, iclass 40, count 0 2006.202.01:50:08.96#ibcon#read 6, iclass 40, count 0 2006.202.01:50:08.96#ibcon#end of sib2, iclass 40, count 0 2006.202.01:50:08.96#ibcon#*mode == 0, iclass 40, count 0 2006.202.01:50:08.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.01:50:08.96#ibcon#[26=FRQ=01,524.99\r\n] 2006.202.01:50:08.96#ibcon#*before write, iclass 40, count 0 2006.202.01:50:08.96#ibcon#enter sib2, iclass 40, count 0 2006.202.01:50:08.96#ibcon#flushed, iclass 40, count 0 2006.202.01:50:08.96#ibcon#about to write, iclass 40, count 0 2006.202.01:50:08.96#ibcon#wrote, iclass 40, count 0 2006.202.01:50:08.96#ibcon#about to read 3, iclass 40, count 0 2006.202.01:50:09.01#ibcon#read 3, iclass 40, count 0 2006.202.01:50:09.01#ibcon#about to read 4, iclass 40, count 0 2006.202.01:50:09.01#ibcon#read 4, iclass 40, count 0 2006.202.01:50:09.01#ibcon#about to read 5, iclass 40, count 0 2006.202.01:50:09.01#ibcon#read 5, iclass 40, count 0 2006.202.01:50:09.01#ibcon#about to read 6, iclass 40, count 0 2006.202.01:50:09.01#ibcon#read 6, iclass 40, count 0 2006.202.01:50:09.01#ibcon#end of sib2, iclass 40, count 0 2006.202.01:50:09.01#ibcon#*after write, iclass 40, count 0 2006.202.01:50:09.01#ibcon#*before return 0, iclass 40, count 0 2006.202.01:50:09.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:09.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:09.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.01:50:09.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.01:50:09.01$vck44/va=1,8 2006.202.01:50:09.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.202.01:50:09.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.202.01:50:09.01#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:09.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:09.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:09.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:09.01#ibcon#enter wrdev, iclass 4, count 2 2006.202.01:50:09.01#ibcon#first serial, iclass 4, count 2 2006.202.01:50:09.01#ibcon#enter sib2, iclass 4, count 2 2006.202.01:50:09.01#ibcon#flushed, iclass 4, count 2 2006.202.01:50:09.01#ibcon#about to write, iclass 4, count 2 2006.202.01:50:09.01#ibcon#wrote, iclass 4, count 2 2006.202.01:50:09.01#ibcon#about to read 3, iclass 4, count 2 2006.202.01:50:09.03#ibcon#read 3, iclass 4, count 2 2006.202.01:50:09.03#ibcon#about to read 4, iclass 4, count 2 2006.202.01:50:09.03#ibcon#read 4, iclass 4, count 2 2006.202.01:50:09.03#ibcon#about to read 5, iclass 4, count 2 2006.202.01:50:09.03#ibcon#read 5, iclass 4, count 2 2006.202.01:50:09.03#ibcon#about to read 6, iclass 4, count 2 2006.202.01:50:09.03#ibcon#read 6, iclass 4, count 2 2006.202.01:50:09.03#ibcon#end of sib2, iclass 4, count 2 2006.202.01:50:09.03#ibcon#*mode == 0, iclass 4, count 2 2006.202.01:50:09.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.202.01:50:09.03#ibcon#[25=AT01-08\r\n] 2006.202.01:50:09.03#ibcon#*before write, iclass 4, count 2 2006.202.01:50:09.03#ibcon#enter sib2, iclass 4, count 2 2006.202.01:50:09.03#ibcon#flushed, iclass 4, count 2 2006.202.01:50:09.03#ibcon#about to write, iclass 4, count 2 2006.202.01:50:09.03#ibcon#wrote, iclass 4, count 2 2006.202.01:50:09.03#ibcon#about to read 3, iclass 4, count 2 2006.202.01:50:09.06#ibcon#read 3, iclass 4, count 2 2006.202.01:50:09.06#ibcon#about to read 4, iclass 4, count 2 2006.202.01:50:09.06#ibcon#read 4, iclass 4, count 2 2006.202.01:50:09.06#ibcon#about to read 5, iclass 4, count 2 2006.202.01:50:09.06#ibcon#read 5, iclass 4, count 2 2006.202.01:50:09.06#ibcon#about to read 6, iclass 4, count 2 2006.202.01:50:09.06#ibcon#read 6, iclass 4, count 2 2006.202.01:50:09.06#ibcon#end of sib2, iclass 4, count 2 2006.202.01:50:09.06#ibcon#*after write, iclass 4, count 2 2006.202.01:50:09.06#ibcon#*before return 0, iclass 4, count 2 2006.202.01:50:09.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:09.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:09.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.202.01:50:09.06#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:09.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:09.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:09.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:09.18#ibcon#enter wrdev, iclass 4, count 0 2006.202.01:50:09.18#ibcon#first serial, iclass 4, count 0 2006.202.01:50:09.18#ibcon#enter sib2, iclass 4, count 0 2006.202.01:50:09.18#ibcon#flushed, iclass 4, count 0 2006.202.01:50:09.18#ibcon#about to write, iclass 4, count 0 2006.202.01:50:09.18#ibcon#wrote, iclass 4, count 0 2006.202.01:50:09.18#ibcon#about to read 3, iclass 4, count 0 2006.202.01:50:09.20#ibcon#read 3, iclass 4, count 0 2006.202.01:50:09.20#ibcon#about to read 4, iclass 4, count 0 2006.202.01:50:09.20#ibcon#read 4, iclass 4, count 0 2006.202.01:50:09.20#ibcon#about to read 5, iclass 4, count 0 2006.202.01:50:09.20#ibcon#read 5, iclass 4, count 0 2006.202.01:50:09.20#ibcon#about to read 6, iclass 4, count 0 2006.202.01:50:09.20#ibcon#read 6, iclass 4, count 0 2006.202.01:50:09.20#ibcon#end of sib2, iclass 4, count 0 2006.202.01:50:09.20#ibcon#*mode == 0, iclass 4, count 0 2006.202.01:50:09.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.01:50:09.20#ibcon#[25=USB\r\n] 2006.202.01:50:09.20#ibcon#*before write, iclass 4, count 0 2006.202.01:50:09.20#ibcon#enter sib2, iclass 4, count 0 2006.202.01:50:09.20#ibcon#flushed, iclass 4, count 0 2006.202.01:50:09.20#ibcon#about to write, iclass 4, count 0 2006.202.01:50:09.20#ibcon#wrote, iclass 4, count 0 2006.202.01:50:09.20#ibcon#about to read 3, iclass 4, count 0 2006.202.01:50:09.23#ibcon#read 3, iclass 4, count 0 2006.202.01:50:09.23#ibcon#about to read 4, iclass 4, count 0 2006.202.01:50:09.23#ibcon#read 4, iclass 4, count 0 2006.202.01:50:09.23#ibcon#about to read 5, iclass 4, count 0 2006.202.01:50:09.23#ibcon#read 5, iclass 4, count 0 2006.202.01:50:09.23#ibcon#about to read 6, iclass 4, count 0 2006.202.01:50:09.23#ibcon#read 6, iclass 4, count 0 2006.202.01:50:09.23#ibcon#end of sib2, iclass 4, count 0 2006.202.01:50:09.23#ibcon#*after write, iclass 4, count 0 2006.202.01:50:09.23#ibcon#*before return 0, iclass 4, count 0 2006.202.01:50:09.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:09.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:09.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.01:50:09.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.01:50:09.23$vck44/valo=2,534.99 2006.202.01:50:09.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.202.01:50:09.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.202.01:50:09.23#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:09.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:09.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:09.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:09.23#ibcon#enter wrdev, iclass 6, count 0 2006.202.01:50:09.23#ibcon#first serial, iclass 6, count 0 2006.202.01:50:09.23#ibcon#enter sib2, iclass 6, count 0 2006.202.01:50:09.23#ibcon#flushed, iclass 6, count 0 2006.202.01:50:09.23#ibcon#about to write, iclass 6, count 0 2006.202.01:50:09.23#ibcon#wrote, iclass 6, count 0 2006.202.01:50:09.23#ibcon#about to read 3, iclass 6, count 0 2006.202.01:50:09.25#ibcon#read 3, iclass 6, count 0 2006.202.01:50:09.25#ibcon#about to read 4, iclass 6, count 0 2006.202.01:50:09.25#ibcon#read 4, iclass 6, count 0 2006.202.01:50:09.25#ibcon#about to read 5, iclass 6, count 0 2006.202.01:50:09.25#ibcon#read 5, iclass 6, count 0 2006.202.01:50:09.25#ibcon#about to read 6, iclass 6, count 0 2006.202.01:50:09.25#ibcon#read 6, iclass 6, count 0 2006.202.01:50:09.25#ibcon#end of sib2, iclass 6, count 0 2006.202.01:50:09.25#ibcon#*mode == 0, iclass 6, count 0 2006.202.01:50:09.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.01:50:09.25#ibcon#[26=FRQ=02,534.99\r\n] 2006.202.01:50:09.25#ibcon#*before write, iclass 6, count 0 2006.202.01:50:09.25#ibcon#enter sib2, iclass 6, count 0 2006.202.01:50:09.25#ibcon#flushed, iclass 6, count 0 2006.202.01:50:09.25#ibcon#about to write, iclass 6, count 0 2006.202.01:50:09.25#ibcon#wrote, iclass 6, count 0 2006.202.01:50:09.25#ibcon#about to read 3, iclass 6, count 0 2006.202.01:50:09.29#ibcon#read 3, iclass 6, count 0 2006.202.01:50:09.29#ibcon#about to read 4, iclass 6, count 0 2006.202.01:50:09.29#ibcon#read 4, iclass 6, count 0 2006.202.01:50:09.29#ibcon#about to read 5, iclass 6, count 0 2006.202.01:50:09.29#ibcon#read 5, iclass 6, count 0 2006.202.01:50:09.29#ibcon#about to read 6, iclass 6, count 0 2006.202.01:50:09.29#ibcon#read 6, iclass 6, count 0 2006.202.01:50:09.29#ibcon#end of sib2, iclass 6, count 0 2006.202.01:50:09.29#ibcon#*after write, iclass 6, count 0 2006.202.01:50:09.29#ibcon#*before return 0, iclass 6, count 0 2006.202.01:50:09.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:09.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:09.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.01:50:09.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.01:50:09.29$vck44/va=2,7 2006.202.01:50:09.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.202.01:50:09.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.202.01:50:09.29#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:09.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:09.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:09.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:09.35#ibcon#enter wrdev, iclass 10, count 2 2006.202.01:50:09.35#ibcon#first serial, iclass 10, count 2 2006.202.01:50:09.35#ibcon#enter sib2, iclass 10, count 2 2006.202.01:50:09.35#ibcon#flushed, iclass 10, count 2 2006.202.01:50:09.35#ibcon#about to write, iclass 10, count 2 2006.202.01:50:09.35#ibcon#wrote, iclass 10, count 2 2006.202.01:50:09.35#ibcon#about to read 3, iclass 10, count 2 2006.202.01:50:09.37#ibcon#read 3, iclass 10, count 2 2006.202.01:50:09.37#ibcon#about to read 4, iclass 10, count 2 2006.202.01:50:09.37#ibcon#read 4, iclass 10, count 2 2006.202.01:50:09.37#ibcon#about to read 5, iclass 10, count 2 2006.202.01:50:09.37#ibcon#read 5, iclass 10, count 2 2006.202.01:50:09.37#ibcon#about to read 6, iclass 10, count 2 2006.202.01:50:09.37#ibcon#read 6, iclass 10, count 2 2006.202.01:50:09.37#ibcon#end of sib2, iclass 10, count 2 2006.202.01:50:09.37#ibcon#*mode == 0, iclass 10, count 2 2006.202.01:50:09.37#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.202.01:50:09.37#ibcon#[25=AT02-07\r\n] 2006.202.01:50:09.37#ibcon#*before write, iclass 10, count 2 2006.202.01:50:09.37#ibcon#enter sib2, iclass 10, count 2 2006.202.01:50:09.37#ibcon#flushed, iclass 10, count 2 2006.202.01:50:09.37#ibcon#about to write, iclass 10, count 2 2006.202.01:50:09.37#ibcon#wrote, iclass 10, count 2 2006.202.01:50:09.37#ibcon#about to read 3, iclass 10, count 2 2006.202.01:50:09.40#ibcon#read 3, iclass 10, count 2 2006.202.01:50:09.40#ibcon#about to read 4, iclass 10, count 2 2006.202.01:50:09.40#ibcon#read 4, iclass 10, count 2 2006.202.01:50:09.40#ibcon#about to read 5, iclass 10, count 2 2006.202.01:50:09.40#ibcon#read 5, iclass 10, count 2 2006.202.01:50:09.40#ibcon#about to read 6, iclass 10, count 2 2006.202.01:50:09.40#ibcon#read 6, iclass 10, count 2 2006.202.01:50:09.40#ibcon#end of sib2, iclass 10, count 2 2006.202.01:50:09.40#ibcon#*after write, iclass 10, count 2 2006.202.01:50:09.40#ibcon#*before return 0, iclass 10, count 2 2006.202.01:50:09.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:09.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:09.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.202.01:50:09.40#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:09.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:09.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:09.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:09.52#ibcon#enter wrdev, iclass 10, count 0 2006.202.01:50:09.52#ibcon#first serial, iclass 10, count 0 2006.202.01:50:09.52#ibcon#enter sib2, iclass 10, count 0 2006.202.01:50:09.52#ibcon#flushed, iclass 10, count 0 2006.202.01:50:09.52#ibcon#about to write, iclass 10, count 0 2006.202.01:50:09.52#ibcon#wrote, iclass 10, count 0 2006.202.01:50:09.52#ibcon#about to read 3, iclass 10, count 0 2006.202.01:50:09.54#ibcon#read 3, iclass 10, count 0 2006.202.01:50:09.54#ibcon#about to read 4, iclass 10, count 0 2006.202.01:50:09.54#ibcon#read 4, iclass 10, count 0 2006.202.01:50:09.54#ibcon#about to read 5, iclass 10, count 0 2006.202.01:50:09.54#ibcon#read 5, iclass 10, count 0 2006.202.01:50:09.54#ibcon#about to read 6, iclass 10, count 0 2006.202.01:50:09.54#ibcon#read 6, iclass 10, count 0 2006.202.01:50:09.54#ibcon#end of sib2, iclass 10, count 0 2006.202.01:50:09.54#ibcon#*mode == 0, iclass 10, count 0 2006.202.01:50:09.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.01:50:09.54#ibcon#[25=USB\r\n] 2006.202.01:50:09.54#ibcon#*before write, iclass 10, count 0 2006.202.01:50:09.54#ibcon#enter sib2, iclass 10, count 0 2006.202.01:50:09.54#ibcon#flushed, iclass 10, count 0 2006.202.01:50:09.54#ibcon#about to write, iclass 10, count 0 2006.202.01:50:09.54#ibcon#wrote, iclass 10, count 0 2006.202.01:50:09.54#ibcon#about to read 3, iclass 10, count 0 2006.202.01:50:09.57#ibcon#read 3, iclass 10, count 0 2006.202.01:50:09.57#ibcon#about to read 4, iclass 10, count 0 2006.202.01:50:09.57#ibcon#read 4, iclass 10, count 0 2006.202.01:50:09.57#ibcon#about to read 5, iclass 10, count 0 2006.202.01:50:09.57#ibcon#read 5, iclass 10, count 0 2006.202.01:50:09.57#ibcon#about to read 6, iclass 10, count 0 2006.202.01:50:09.57#ibcon#read 6, iclass 10, count 0 2006.202.01:50:09.57#ibcon#end of sib2, iclass 10, count 0 2006.202.01:50:09.57#ibcon#*after write, iclass 10, count 0 2006.202.01:50:09.57#ibcon#*before return 0, iclass 10, count 0 2006.202.01:50:09.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:09.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:09.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.01:50:09.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.01:50:09.57$vck44/valo=3,564.99 2006.202.01:50:09.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.202.01:50:09.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.202.01:50:09.57#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:09.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:09.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:09.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:09.57#ibcon#enter wrdev, iclass 12, count 0 2006.202.01:50:09.57#ibcon#first serial, iclass 12, count 0 2006.202.01:50:09.57#ibcon#enter sib2, iclass 12, count 0 2006.202.01:50:09.57#ibcon#flushed, iclass 12, count 0 2006.202.01:50:09.57#ibcon#about to write, iclass 12, count 0 2006.202.01:50:09.57#ibcon#wrote, iclass 12, count 0 2006.202.01:50:09.57#ibcon#about to read 3, iclass 12, count 0 2006.202.01:50:09.59#ibcon#read 3, iclass 12, count 0 2006.202.01:50:09.59#ibcon#about to read 4, iclass 12, count 0 2006.202.01:50:09.59#ibcon#read 4, iclass 12, count 0 2006.202.01:50:09.59#ibcon#about to read 5, iclass 12, count 0 2006.202.01:50:09.59#ibcon#read 5, iclass 12, count 0 2006.202.01:50:09.59#ibcon#about to read 6, iclass 12, count 0 2006.202.01:50:09.59#ibcon#read 6, iclass 12, count 0 2006.202.01:50:09.59#ibcon#end of sib2, iclass 12, count 0 2006.202.01:50:09.59#ibcon#*mode == 0, iclass 12, count 0 2006.202.01:50:09.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.01:50:09.59#ibcon#[26=FRQ=03,564.99\r\n] 2006.202.01:50:09.59#ibcon#*before write, iclass 12, count 0 2006.202.01:50:09.59#ibcon#enter sib2, iclass 12, count 0 2006.202.01:50:09.59#ibcon#flushed, iclass 12, count 0 2006.202.01:50:09.59#ibcon#about to write, iclass 12, count 0 2006.202.01:50:09.59#ibcon#wrote, iclass 12, count 0 2006.202.01:50:09.59#ibcon#about to read 3, iclass 12, count 0 2006.202.01:50:09.63#ibcon#read 3, iclass 12, count 0 2006.202.01:50:09.63#ibcon#about to read 4, iclass 12, count 0 2006.202.01:50:09.63#ibcon#read 4, iclass 12, count 0 2006.202.01:50:09.63#ibcon#about to read 5, iclass 12, count 0 2006.202.01:50:09.63#ibcon#read 5, iclass 12, count 0 2006.202.01:50:09.63#ibcon#about to read 6, iclass 12, count 0 2006.202.01:50:09.63#ibcon#read 6, iclass 12, count 0 2006.202.01:50:09.63#ibcon#end of sib2, iclass 12, count 0 2006.202.01:50:09.63#ibcon#*after write, iclass 12, count 0 2006.202.01:50:09.63#ibcon#*before return 0, iclass 12, count 0 2006.202.01:50:09.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:09.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:09.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.01:50:09.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.01:50:09.63$vck44/va=3,8 2006.202.01:50:09.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.202.01:50:09.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.202.01:50:09.63#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:09.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:09.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:09.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:09.69#ibcon#enter wrdev, iclass 14, count 2 2006.202.01:50:09.69#ibcon#first serial, iclass 14, count 2 2006.202.01:50:09.69#ibcon#enter sib2, iclass 14, count 2 2006.202.01:50:09.69#ibcon#flushed, iclass 14, count 2 2006.202.01:50:09.69#ibcon#about to write, iclass 14, count 2 2006.202.01:50:09.69#ibcon#wrote, iclass 14, count 2 2006.202.01:50:09.69#ibcon#about to read 3, iclass 14, count 2 2006.202.01:50:09.71#ibcon#read 3, iclass 14, count 2 2006.202.01:50:09.71#ibcon#about to read 4, iclass 14, count 2 2006.202.01:50:09.71#ibcon#read 4, iclass 14, count 2 2006.202.01:50:09.71#ibcon#about to read 5, iclass 14, count 2 2006.202.01:50:09.71#ibcon#read 5, iclass 14, count 2 2006.202.01:50:09.71#ibcon#about to read 6, iclass 14, count 2 2006.202.01:50:09.71#ibcon#read 6, iclass 14, count 2 2006.202.01:50:09.71#ibcon#end of sib2, iclass 14, count 2 2006.202.01:50:09.71#ibcon#*mode == 0, iclass 14, count 2 2006.202.01:50:09.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.202.01:50:09.71#ibcon#[25=AT03-08\r\n] 2006.202.01:50:09.71#ibcon#*before write, iclass 14, count 2 2006.202.01:50:09.71#ibcon#enter sib2, iclass 14, count 2 2006.202.01:50:09.71#ibcon#flushed, iclass 14, count 2 2006.202.01:50:09.71#ibcon#about to write, iclass 14, count 2 2006.202.01:50:09.71#ibcon#wrote, iclass 14, count 2 2006.202.01:50:09.71#ibcon#about to read 3, iclass 14, count 2 2006.202.01:50:09.74#ibcon#read 3, iclass 14, count 2 2006.202.01:50:09.74#ibcon#about to read 4, iclass 14, count 2 2006.202.01:50:09.74#ibcon#read 4, iclass 14, count 2 2006.202.01:50:09.74#ibcon#about to read 5, iclass 14, count 2 2006.202.01:50:09.74#ibcon#read 5, iclass 14, count 2 2006.202.01:50:09.74#ibcon#about to read 6, iclass 14, count 2 2006.202.01:50:09.74#ibcon#read 6, iclass 14, count 2 2006.202.01:50:09.74#ibcon#end of sib2, iclass 14, count 2 2006.202.01:50:09.74#ibcon#*after write, iclass 14, count 2 2006.202.01:50:09.74#ibcon#*before return 0, iclass 14, count 2 2006.202.01:50:09.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:09.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:09.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.202.01:50:09.74#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:09.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:09.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:09.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:09.86#ibcon#enter wrdev, iclass 14, count 0 2006.202.01:50:09.86#ibcon#first serial, iclass 14, count 0 2006.202.01:50:09.86#ibcon#enter sib2, iclass 14, count 0 2006.202.01:50:09.86#ibcon#flushed, iclass 14, count 0 2006.202.01:50:09.86#ibcon#about to write, iclass 14, count 0 2006.202.01:50:09.86#ibcon#wrote, iclass 14, count 0 2006.202.01:50:09.86#ibcon#about to read 3, iclass 14, count 0 2006.202.01:50:09.88#ibcon#read 3, iclass 14, count 0 2006.202.01:50:09.88#ibcon#about to read 4, iclass 14, count 0 2006.202.01:50:09.88#ibcon#read 4, iclass 14, count 0 2006.202.01:50:09.88#ibcon#about to read 5, iclass 14, count 0 2006.202.01:50:09.88#ibcon#read 5, iclass 14, count 0 2006.202.01:50:09.88#ibcon#about to read 6, iclass 14, count 0 2006.202.01:50:09.88#ibcon#read 6, iclass 14, count 0 2006.202.01:50:09.88#ibcon#end of sib2, iclass 14, count 0 2006.202.01:50:09.88#ibcon#*mode == 0, iclass 14, count 0 2006.202.01:50:09.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.01:50:09.88#ibcon#[25=USB\r\n] 2006.202.01:50:09.88#ibcon#*before write, iclass 14, count 0 2006.202.01:50:09.88#ibcon#enter sib2, iclass 14, count 0 2006.202.01:50:09.88#ibcon#flushed, iclass 14, count 0 2006.202.01:50:09.88#ibcon#about to write, iclass 14, count 0 2006.202.01:50:09.88#ibcon#wrote, iclass 14, count 0 2006.202.01:50:09.88#ibcon#about to read 3, iclass 14, count 0 2006.202.01:50:09.91#ibcon#read 3, iclass 14, count 0 2006.202.01:50:09.91#ibcon#about to read 4, iclass 14, count 0 2006.202.01:50:09.91#ibcon#read 4, iclass 14, count 0 2006.202.01:50:09.91#ibcon#about to read 5, iclass 14, count 0 2006.202.01:50:09.91#ibcon#read 5, iclass 14, count 0 2006.202.01:50:09.91#ibcon#about to read 6, iclass 14, count 0 2006.202.01:50:09.91#ibcon#read 6, iclass 14, count 0 2006.202.01:50:09.91#ibcon#end of sib2, iclass 14, count 0 2006.202.01:50:09.91#ibcon#*after write, iclass 14, count 0 2006.202.01:50:09.91#ibcon#*before return 0, iclass 14, count 0 2006.202.01:50:09.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:09.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:09.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.01:50:09.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.01:50:09.91$vck44/valo=4,624.99 2006.202.01:50:09.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.202.01:50:09.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.202.01:50:09.91#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:09.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:09.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:09.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:09.91#ibcon#enter wrdev, iclass 16, count 0 2006.202.01:50:09.91#ibcon#first serial, iclass 16, count 0 2006.202.01:50:09.91#ibcon#enter sib2, iclass 16, count 0 2006.202.01:50:09.91#ibcon#flushed, iclass 16, count 0 2006.202.01:50:09.91#ibcon#about to write, iclass 16, count 0 2006.202.01:50:09.91#ibcon#wrote, iclass 16, count 0 2006.202.01:50:09.91#ibcon#about to read 3, iclass 16, count 0 2006.202.01:50:09.93#ibcon#read 3, iclass 16, count 0 2006.202.01:50:09.93#ibcon#about to read 4, iclass 16, count 0 2006.202.01:50:09.93#ibcon#read 4, iclass 16, count 0 2006.202.01:50:09.93#ibcon#about to read 5, iclass 16, count 0 2006.202.01:50:09.93#ibcon#read 5, iclass 16, count 0 2006.202.01:50:09.93#ibcon#about to read 6, iclass 16, count 0 2006.202.01:50:09.93#ibcon#read 6, iclass 16, count 0 2006.202.01:50:09.93#ibcon#end of sib2, iclass 16, count 0 2006.202.01:50:09.93#ibcon#*mode == 0, iclass 16, count 0 2006.202.01:50:09.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.01:50:09.93#ibcon#[26=FRQ=04,624.99\r\n] 2006.202.01:50:09.93#ibcon#*before write, iclass 16, count 0 2006.202.01:50:09.93#ibcon#enter sib2, iclass 16, count 0 2006.202.01:50:09.93#ibcon#flushed, iclass 16, count 0 2006.202.01:50:09.93#ibcon#about to write, iclass 16, count 0 2006.202.01:50:09.93#ibcon#wrote, iclass 16, count 0 2006.202.01:50:09.93#ibcon#about to read 3, iclass 16, count 0 2006.202.01:50:09.97#ibcon#read 3, iclass 16, count 0 2006.202.01:50:09.97#ibcon#about to read 4, iclass 16, count 0 2006.202.01:50:09.97#ibcon#read 4, iclass 16, count 0 2006.202.01:50:09.97#ibcon#about to read 5, iclass 16, count 0 2006.202.01:50:09.97#ibcon#read 5, iclass 16, count 0 2006.202.01:50:09.97#ibcon#about to read 6, iclass 16, count 0 2006.202.01:50:09.97#ibcon#read 6, iclass 16, count 0 2006.202.01:50:09.97#ibcon#end of sib2, iclass 16, count 0 2006.202.01:50:09.97#ibcon#*after write, iclass 16, count 0 2006.202.01:50:09.97#ibcon#*before return 0, iclass 16, count 0 2006.202.01:50:09.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:09.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:09.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.01:50:09.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.01:50:09.97$vck44/va=4,7 2006.202.01:50:09.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.202.01:50:09.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.202.01:50:09.97#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:09.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:10.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:10.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:10.03#ibcon#enter wrdev, iclass 18, count 2 2006.202.01:50:10.03#ibcon#first serial, iclass 18, count 2 2006.202.01:50:10.03#ibcon#enter sib2, iclass 18, count 2 2006.202.01:50:10.03#ibcon#flushed, iclass 18, count 2 2006.202.01:50:10.03#ibcon#about to write, iclass 18, count 2 2006.202.01:50:10.03#ibcon#wrote, iclass 18, count 2 2006.202.01:50:10.03#ibcon#about to read 3, iclass 18, count 2 2006.202.01:50:10.05#ibcon#read 3, iclass 18, count 2 2006.202.01:50:10.05#ibcon#about to read 4, iclass 18, count 2 2006.202.01:50:10.05#ibcon#read 4, iclass 18, count 2 2006.202.01:50:10.05#ibcon#about to read 5, iclass 18, count 2 2006.202.01:50:10.05#ibcon#read 5, iclass 18, count 2 2006.202.01:50:10.05#ibcon#about to read 6, iclass 18, count 2 2006.202.01:50:10.05#ibcon#read 6, iclass 18, count 2 2006.202.01:50:10.05#ibcon#end of sib2, iclass 18, count 2 2006.202.01:50:10.05#ibcon#*mode == 0, iclass 18, count 2 2006.202.01:50:10.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.202.01:50:10.05#ibcon#[25=AT04-07\r\n] 2006.202.01:50:10.05#ibcon#*before write, iclass 18, count 2 2006.202.01:50:10.05#ibcon#enter sib2, iclass 18, count 2 2006.202.01:50:10.05#ibcon#flushed, iclass 18, count 2 2006.202.01:50:10.05#ibcon#about to write, iclass 18, count 2 2006.202.01:50:10.05#ibcon#wrote, iclass 18, count 2 2006.202.01:50:10.05#ibcon#about to read 3, iclass 18, count 2 2006.202.01:50:10.08#ibcon#read 3, iclass 18, count 2 2006.202.01:50:10.08#ibcon#about to read 4, iclass 18, count 2 2006.202.01:50:10.08#ibcon#read 4, iclass 18, count 2 2006.202.01:50:10.08#ibcon#about to read 5, iclass 18, count 2 2006.202.01:50:10.08#ibcon#read 5, iclass 18, count 2 2006.202.01:50:10.08#ibcon#about to read 6, iclass 18, count 2 2006.202.01:50:10.08#ibcon#read 6, iclass 18, count 2 2006.202.01:50:10.08#ibcon#end of sib2, iclass 18, count 2 2006.202.01:50:10.08#ibcon#*after write, iclass 18, count 2 2006.202.01:50:10.08#ibcon#*before return 0, iclass 18, count 2 2006.202.01:50:10.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:10.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:10.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.202.01:50:10.08#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:10.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:10.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:10.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:10.20#ibcon#enter wrdev, iclass 18, count 0 2006.202.01:50:10.20#ibcon#first serial, iclass 18, count 0 2006.202.01:50:10.20#ibcon#enter sib2, iclass 18, count 0 2006.202.01:50:10.20#ibcon#flushed, iclass 18, count 0 2006.202.01:50:10.20#ibcon#about to write, iclass 18, count 0 2006.202.01:50:10.20#ibcon#wrote, iclass 18, count 0 2006.202.01:50:10.20#ibcon#about to read 3, iclass 18, count 0 2006.202.01:50:10.22#ibcon#read 3, iclass 18, count 0 2006.202.01:50:10.22#ibcon#about to read 4, iclass 18, count 0 2006.202.01:50:10.22#ibcon#read 4, iclass 18, count 0 2006.202.01:50:10.22#ibcon#about to read 5, iclass 18, count 0 2006.202.01:50:10.22#ibcon#read 5, iclass 18, count 0 2006.202.01:50:10.22#ibcon#about to read 6, iclass 18, count 0 2006.202.01:50:10.22#ibcon#read 6, iclass 18, count 0 2006.202.01:50:10.22#ibcon#end of sib2, iclass 18, count 0 2006.202.01:50:10.22#ibcon#*mode == 0, iclass 18, count 0 2006.202.01:50:10.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.01:50:10.22#ibcon#[25=USB\r\n] 2006.202.01:50:10.22#ibcon#*before write, iclass 18, count 0 2006.202.01:50:10.22#ibcon#enter sib2, iclass 18, count 0 2006.202.01:50:10.22#ibcon#flushed, iclass 18, count 0 2006.202.01:50:10.22#ibcon#about to write, iclass 18, count 0 2006.202.01:50:10.22#ibcon#wrote, iclass 18, count 0 2006.202.01:50:10.22#ibcon#about to read 3, iclass 18, count 0 2006.202.01:50:10.25#ibcon#read 3, iclass 18, count 0 2006.202.01:50:10.25#ibcon#about to read 4, iclass 18, count 0 2006.202.01:50:10.25#ibcon#read 4, iclass 18, count 0 2006.202.01:50:10.25#ibcon#about to read 5, iclass 18, count 0 2006.202.01:50:10.25#ibcon#read 5, iclass 18, count 0 2006.202.01:50:10.25#ibcon#about to read 6, iclass 18, count 0 2006.202.01:50:10.25#ibcon#read 6, iclass 18, count 0 2006.202.01:50:10.25#ibcon#end of sib2, iclass 18, count 0 2006.202.01:50:10.25#ibcon#*after write, iclass 18, count 0 2006.202.01:50:10.25#ibcon#*before return 0, iclass 18, count 0 2006.202.01:50:10.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:10.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:10.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.01:50:10.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.01:50:10.25$vck44/valo=5,734.99 2006.202.01:50:10.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.202.01:50:10.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.202.01:50:10.25#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:10.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:10.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:10.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:10.25#ibcon#enter wrdev, iclass 20, count 0 2006.202.01:50:10.25#ibcon#first serial, iclass 20, count 0 2006.202.01:50:10.25#ibcon#enter sib2, iclass 20, count 0 2006.202.01:50:10.25#ibcon#flushed, iclass 20, count 0 2006.202.01:50:10.25#ibcon#about to write, iclass 20, count 0 2006.202.01:50:10.25#ibcon#wrote, iclass 20, count 0 2006.202.01:50:10.25#ibcon#about to read 3, iclass 20, count 0 2006.202.01:50:10.27#ibcon#read 3, iclass 20, count 0 2006.202.01:50:10.27#ibcon#about to read 4, iclass 20, count 0 2006.202.01:50:10.27#ibcon#read 4, iclass 20, count 0 2006.202.01:50:10.27#ibcon#about to read 5, iclass 20, count 0 2006.202.01:50:10.27#ibcon#read 5, iclass 20, count 0 2006.202.01:50:10.27#ibcon#about to read 6, iclass 20, count 0 2006.202.01:50:10.27#ibcon#read 6, iclass 20, count 0 2006.202.01:50:10.27#ibcon#end of sib2, iclass 20, count 0 2006.202.01:50:10.27#ibcon#*mode == 0, iclass 20, count 0 2006.202.01:50:10.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.01:50:10.27#ibcon#[26=FRQ=05,734.99\r\n] 2006.202.01:50:10.27#ibcon#*before write, iclass 20, count 0 2006.202.01:50:10.27#ibcon#enter sib2, iclass 20, count 0 2006.202.01:50:10.27#ibcon#flushed, iclass 20, count 0 2006.202.01:50:10.27#ibcon#about to write, iclass 20, count 0 2006.202.01:50:10.27#ibcon#wrote, iclass 20, count 0 2006.202.01:50:10.27#ibcon#about to read 3, iclass 20, count 0 2006.202.01:50:10.31#ibcon#read 3, iclass 20, count 0 2006.202.01:50:10.31#ibcon#about to read 4, iclass 20, count 0 2006.202.01:50:10.31#ibcon#read 4, iclass 20, count 0 2006.202.01:50:10.31#ibcon#about to read 5, iclass 20, count 0 2006.202.01:50:10.31#ibcon#read 5, iclass 20, count 0 2006.202.01:50:10.31#ibcon#about to read 6, iclass 20, count 0 2006.202.01:50:10.31#ibcon#read 6, iclass 20, count 0 2006.202.01:50:10.31#ibcon#end of sib2, iclass 20, count 0 2006.202.01:50:10.31#ibcon#*after write, iclass 20, count 0 2006.202.01:50:10.31#ibcon#*before return 0, iclass 20, count 0 2006.202.01:50:10.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:10.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:10.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.01:50:10.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.01:50:10.31$vck44/va=5,4 2006.202.01:50:10.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.202.01:50:10.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.202.01:50:10.31#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:10.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:10.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:10.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:10.37#ibcon#enter wrdev, iclass 22, count 2 2006.202.01:50:10.37#ibcon#first serial, iclass 22, count 2 2006.202.01:50:10.37#ibcon#enter sib2, iclass 22, count 2 2006.202.01:50:10.37#ibcon#flushed, iclass 22, count 2 2006.202.01:50:10.37#ibcon#about to write, iclass 22, count 2 2006.202.01:50:10.37#ibcon#wrote, iclass 22, count 2 2006.202.01:50:10.37#ibcon#about to read 3, iclass 22, count 2 2006.202.01:50:10.39#ibcon#read 3, iclass 22, count 2 2006.202.01:50:10.39#ibcon#about to read 4, iclass 22, count 2 2006.202.01:50:10.39#ibcon#read 4, iclass 22, count 2 2006.202.01:50:10.39#ibcon#about to read 5, iclass 22, count 2 2006.202.01:50:10.39#ibcon#read 5, iclass 22, count 2 2006.202.01:50:10.39#ibcon#about to read 6, iclass 22, count 2 2006.202.01:50:10.39#ibcon#read 6, iclass 22, count 2 2006.202.01:50:10.39#ibcon#end of sib2, iclass 22, count 2 2006.202.01:50:10.39#ibcon#*mode == 0, iclass 22, count 2 2006.202.01:50:10.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.202.01:50:10.39#ibcon#[25=AT05-04\r\n] 2006.202.01:50:10.39#ibcon#*before write, iclass 22, count 2 2006.202.01:50:10.39#ibcon#enter sib2, iclass 22, count 2 2006.202.01:50:10.39#ibcon#flushed, iclass 22, count 2 2006.202.01:50:10.39#ibcon#about to write, iclass 22, count 2 2006.202.01:50:10.39#ibcon#wrote, iclass 22, count 2 2006.202.01:50:10.39#ibcon#about to read 3, iclass 22, count 2 2006.202.01:50:10.42#ibcon#read 3, iclass 22, count 2 2006.202.01:50:10.42#ibcon#about to read 4, iclass 22, count 2 2006.202.01:50:10.42#ibcon#read 4, iclass 22, count 2 2006.202.01:50:10.42#ibcon#about to read 5, iclass 22, count 2 2006.202.01:50:10.42#ibcon#read 5, iclass 22, count 2 2006.202.01:50:10.42#ibcon#about to read 6, iclass 22, count 2 2006.202.01:50:10.42#ibcon#read 6, iclass 22, count 2 2006.202.01:50:10.42#ibcon#end of sib2, iclass 22, count 2 2006.202.01:50:10.42#ibcon#*after write, iclass 22, count 2 2006.202.01:50:10.42#ibcon#*before return 0, iclass 22, count 2 2006.202.01:50:10.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:10.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:10.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.202.01:50:10.42#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:10.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:10.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:10.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:10.54#ibcon#enter wrdev, iclass 22, count 0 2006.202.01:50:10.54#ibcon#first serial, iclass 22, count 0 2006.202.01:50:10.54#ibcon#enter sib2, iclass 22, count 0 2006.202.01:50:10.54#ibcon#flushed, iclass 22, count 0 2006.202.01:50:10.54#ibcon#about to write, iclass 22, count 0 2006.202.01:50:10.54#ibcon#wrote, iclass 22, count 0 2006.202.01:50:10.54#ibcon#about to read 3, iclass 22, count 0 2006.202.01:50:10.56#ibcon#read 3, iclass 22, count 0 2006.202.01:50:10.56#ibcon#about to read 4, iclass 22, count 0 2006.202.01:50:10.56#ibcon#read 4, iclass 22, count 0 2006.202.01:50:10.56#ibcon#about to read 5, iclass 22, count 0 2006.202.01:50:10.56#ibcon#read 5, iclass 22, count 0 2006.202.01:50:10.56#ibcon#about to read 6, iclass 22, count 0 2006.202.01:50:10.56#ibcon#read 6, iclass 22, count 0 2006.202.01:50:10.56#ibcon#end of sib2, iclass 22, count 0 2006.202.01:50:10.56#ibcon#*mode == 0, iclass 22, count 0 2006.202.01:50:10.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.01:50:10.56#ibcon#[25=USB\r\n] 2006.202.01:50:10.56#ibcon#*before write, iclass 22, count 0 2006.202.01:50:10.56#ibcon#enter sib2, iclass 22, count 0 2006.202.01:50:10.56#ibcon#flushed, iclass 22, count 0 2006.202.01:50:10.56#ibcon#about to write, iclass 22, count 0 2006.202.01:50:10.56#ibcon#wrote, iclass 22, count 0 2006.202.01:50:10.56#ibcon#about to read 3, iclass 22, count 0 2006.202.01:50:10.59#ibcon#read 3, iclass 22, count 0 2006.202.01:50:10.59#ibcon#about to read 4, iclass 22, count 0 2006.202.01:50:10.59#ibcon#read 4, iclass 22, count 0 2006.202.01:50:10.59#ibcon#about to read 5, iclass 22, count 0 2006.202.01:50:10.59#ibcon#read 5, iclass 22, count 0 2006.202.01:50:10.59#ibcon#about to read 6, iclass 22, count 0 2006.202.01:50:10.59#ibcon#read 6, iclass 22, count 0 2006.202.01:50:10.59#ibcon#end of sib2, iclass 22, count 0 2006.202.01:50:10.59#ibcon#*after write, iclass 22, count 0 2006.202.01:50:10.59#ibcon#*before return 0, iclass 22, count 0 2006.202.01:50:10.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:10.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:10.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.01:50:10.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.01:50:10.59$vck44/valo=6,814.99 2006.202.01:50:10.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.202.01:50:10.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.202.01:50:10.59#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:10.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:10.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:10.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:10.59#ibcon#enter wrdev, iclass 24, count 0 2006.202.01:50:10.59#ibcon#first serial, iclass 24, count 0 2006.202.01:50:10.59#ibcon#enter sib2, iclass 24, count 0 2006.202.01:50:10.59#ibcon#flushed, iclass 24, count 0 2006.202.01:50:10.59#ibcon#about to write, iclass 24, count 0 2006.202.01:50:10.59#ibcon#wrote, iclass 24, count 0 2006.202.01:50:10.59#ibcon#about to read 3, iclass 24, count 0 2006.202.01:50:10.61#ibcon#read 3, iclass 24, count 0 2006.202.01:50:10.61#ibcon#about to read 4, iclass 24, count 0 2006.202.01:50:10.61#ibcon#read 4, iclass 24, count 0 2006.202.01:50:10.61#ibcon#about to read 5, iclass 24, count 0 2006.202.01:50:10.61#ibcon#read 5, iclass 24, count 0 2006.202.01:50:10.61#ibcon#about to read 6, iclass 24, count 0 2006.202.01:50:10.61#ibcon#read 6, iclass 24, count 0 2006.202.01:50:10.61#ibcon#end of sib2, iclass 24, count 0 2006.202.01:50:10.61#ibcon#*mode == 0, iclass 24, count 0 2006.202.01:50:10.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.01:50:10.61#ibcon#[26=FRQ=06,814.99\r\n] 2006.202.01:50:10.61#ibcon#*before write, iclass 24, count 0 2006.202.01:50:10.61#ibcon#enter sib2, iclass 24, count 0 2006.202.01:50:10.61#ibcon#flushed, iclass 24, count 0 2006.202.01:50:10.61#ibcon#about to write, iclass 24, count 0 2006.202.01:50:10.61#ibcon#wrote, iclass 24, count 0 2006.202.01:50:10.61#ibcon#about to read 3, iclass 24, count 0 2006.202.01:50:10.65#ibcon#read 3, iclass 24, count 0 2006.202.01:50:10.65#ibcon#about to read 4, iclass 24, count 0 2006.202.01:50:10.65#ibcon#read 4, iclass 24, count 0 2006.202.01:50:10.65#ibcon#about to read 5, iclass 24, count 0 2006.202.01:50:10.65#ibcon#read 5, iclass 24, count 0 2006.202.01:50:10.65#ibcon#about to read 6, iclass 24, count 0 2006.202.01:50:10.65#ibcon#read 6, iclass 24, count 0 2006.202.01:50:10.65#ibcon#end of sib2, iclass 24, count 0 2006.202.01:50:10.65#ibcon#*after write, iclass 24, count 0 2006.202.01:50:10.65#ibcon#*before return 0, iclass 24, count 0 2006.202.01:50:10.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:10.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:10.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.01:50:10.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.01:50:10.65$vck44/va=6,5 2006.202.01:50:10.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.202.01:50:10.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.202.01:50:10.65#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:10.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.202.01:50:10.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.202.01:50:10.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.202.01:50:10.71#ibcon#enter wrdev, iclass 26, count 2 2006.202.01:50:10.71#ibcon#first serial, iclass 26, count 2 2006.202.01:50:10.71#ibcon#enter sib2, iclass 26, count 2 2006.202.01:50:10.71#ibcon#flushed, iclass 26, count 2 2006.202.01:50:10.71#ibcon#about to write, iclass 26, count 2 2006.202.01:50:10.71#ibcon#wrote, iclass 26, count 2 2006.202.01:50:10.71#ibcon#about to read 3, iclass 26, count 2 2006.202.01:50:10.73#ibcon#read 3, iclass 26, count 2 2006.202.01:50:10.73#ibcon#about to read 4, iclass 26, count 2 2006.202.01:50:10.73#ibcon#read 4, iclass 26, count 2 2006.202.01:50:10.73#ibcon#about to read 5, iclass 26, count 2 2006.202.01:50:10.73#ibcon#read 5, iclass 26, count 2 2006.202.01:50:10.73#ibcon#about to read 6, iclass 26, count 2 2006.202.01:50:10.73#ibcon#read 6, iclass 26, count 2 2006.202.01:50:10.73#ibcon#end of sib2, iclass 26, count 2 2006.202.01:50:10.73#ibcon#*mode == 0, iclass 26, count 2 2006.202.01:50:10.73#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.202.01:50:10.73#ibcon#[25=AT06-05\r\n] 2006.202.01:50:10.73#ibcon#*before write, iclass 26, count 2 2006.202.01:50:10.73#ibcon#enter sib2, iclass 26, count 2 2006.202.01:50:10.73#ibcon#flushed, iclass 26, count 2 2006.202.01:50:10.73#ibcon#about to write, iclass 26, count 2 2006.202.01:50:10.73#ibcon#wrote, iclass 26, count 2 2006.202.01:50:10.73#ibcon#about to read 3, iclass 26, count 2 2006.202.01:50:10.76#ibcon#read 3, iclass 26, count 2 2006.202.01:50:10.76#ibcon#about to read 4, iclass 26, count 2 2006.202.01:50:10.76#ibcon#read 4, iclass 26, count 2 2006.202.01:50:10.76#ibcon#about to read 5, iclass 26, count 2 2006.202.01:50:10.76#ibcon#read 5, iclass 26, count 2 2006.202.01:50:10.76#ibcon#about to read 6, iclass 26, count 2 2006.202.01:50:10.76#ibcon#read 6, iclass 26, count 2 2006.202.01:50:10.76#ibcon#end of sib2, iclass 26, count 2 2006.202.01:50:10.76#ibcon#*after write, iclass 26, count 2 2006.202.01:50:10.76#ibcon#*before return 0, iclass 26, count 2 2006.202.01:50:10.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.202.01:50:10.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.202.01:50:10.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.202.01:50:10.76#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:10.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.202.01:50:10.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.202.01:50:10.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.202.01:50:10.88#ibcon#enter wrdev, iclass 26, count 0 2006.202.01:50:10.88#ibcon#first serial, iclass 26, count 0 2006.202.01:50:10.88#ibcon#enter sib2, iclass 26, count 0 2006.202.01:50:10.88#ibcon#flushed, iclass 26, count 0 2006.202.01:50:10.88#ibcon#about to write, iclass 26, count 0 2006.202.01:50:10.88#ibcon#wrote, iclass 26, count 0 2006.202.01:50:10.88#ibcon#about to read 3, iclass 26, count 0 2006.202.01:50:10.90#ibcon#read 3, iclass 26, count 0 2006.202.01:50:10.90#ibcon#about to read 4, iclass 26, count 0 2006.202.01:50:10.90#ibcon#read 4, iclass 26, count 0 2006.202.01:50:10.90#ibcon#about to read 5, iclass 26, count 0 2006.202.01:50:10.90#ibcon#read 5, iclass 26, count 0 2006.202.01:50:10.90#ibcon#about to read 6, iclass 26, count 0 2006.202.01:50:10.90#ibcon#read 6, iclass 26, count 0 2006.202.01:50:10.90#ibcon#end of sib2, iclass 26, count 0 2006.202.01:50:10.90#ibcon#*mode == 0, iclass 26, count 0 2006.202.01:50:10.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.202.01:50:10.90#ibcon#[25=USB\r\n] 2006.202.01:50:10.90#ibcon#*before write, iclass 26, count 0 2006.202.01:50:10.90#ibcon#enter sib2, iclass 26, count 0 2006.202.01:50:10.90#ibcon#flushed, iclass 26, count 0 2006.202.01:50:10.90#ibcon#about to write, iclass 26, count 0 2006.202.01:50:10.90#ibcon#wrote, iclass 26, count 0 2006.202.01:50:10.90#ibcon#about to read 3, iclass 26, count 0 2006.202.01:50:10.93#ibcon#read 3, iclass 26, count 0 2006.202.01:50:10.93#ibcon#about to read 4, iclass 26, count 0 2006.202.01:50:10.93#ibcon#read 4, iclass 26, count 0 2006.202.01:50:10.93#ibcon#about to read 5, iclass 26, count 0 2006.202.01:50:10.93#ibcon#read 5, iclass 26, count 0 2006.202.01:50:10.93#ibcon#about to read 6, iclass 26, count 0 2006.202.01:50:10.93#ibcon#read 6, iclass 26, count 0 2006.202.01:50:10.93#ibcon#end of sib2, iclass 26, count 0 2006.202.01:50:10.93#ibcon#*after write, iclass 26, count 0 2006.202.01:50:10.93#ibcon#*before return 0, iclass 26, count 0 2006.202.01:50:10.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.202.01:50:10.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.202.01:50:10.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.202.01:50:10.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.202.01:50:10.93$vck44/valo=7,864.99 2006.202.01:50:10.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.202.01:50:10.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.202.01:50:10.93#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:10.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.202.01:50:10.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.202.01:50:10.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.202.01:50:10.93#ibcon#enter wrdev, iclass 28, count 0 2006.202.01:50:10.93#ibcon#first serial, iclass 28, count 0 2006.202.01:50:10.93#ibcon#enter sib2, iclass 28, count 0 2006.202.01:50:10.93#ibcon#flushed, iclass 28, count 0 2006.202.01:50:10.93#ibcon#about to write, iclass 28, count 0 2006.202.01:50:10.93#ibcon#wrote, iclass 28, count 0 2006.202.01:50:10.93#ibcon#about to read 3, iclass 28, count 0 2006.202.01:50:10.95#ibcon#read 3, iclass 28, count 0 2006.202.01:50:10.95#ibcon#about to read 4, iclass 28, count 0 2006.202.01:50:10.95#ibcon#read 4, iclass 28, count 0 2006.202.01:50:10.95#ibcon#about to read 5, iclass 28, count 0 2006.202.01:50:10.95#ibcon#read 5, iclass 28, count 0 2006.202.01:50:10.95#ibcon#about to read 6, iclass 28, count 0 2006.202.01:50:10.95#ibcon#read 6, iclass 28, count 0 2006.202.01:50:10.95#ibcon#end of sib2, iclass 28, count 0 2006.202.01:50:10.95#ibcon#*mode == 0, iclass 28, count 0 2006.202.01:50:10.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.202.01:50:10.95#ibcon#[26=FRQ=07,864.99\r\n] 2006.202.01:50:10.95#ibcon#*before write, iclass 28, count 0 2006.202.01:50:10.95#ibcon#enter sib2, iclass 28, count 0 2006.202.01:50:10.95#ibcon#flushed, iclass 28, count 0 2006.202.01:50:10.95#ibcon#about to write, iclass 28, count 0 2006.202.01:50:10.95#ibcon#wrote, iclass 28, count 0 2006.202.01:50:10.95#ibcon#about to read 3, iclass 28, count 0 2006.202.01:50:10.99#ibcon#read 3, iclass 28, count 0 2006.202.01:50:10.99#ibcon#about to read 4, iclass 28, count 0 2006.202.01:50:10.99#ibcon#read 4, iclass 28, count 0 2006.202.01:50:10.99#ibcon#about to read 5, iclass 28, count 0 2006.202.01:50:10.99#ibcon#read 5, iclass 28, count 0 2006.202.01:50:10.99#ibcon#about to read 6, iclass 28, count 0 2006.202.01:50:10.99#ibcon#read 6, iclass 28, count 0 2006.202.01:50:10.99#ibcon#end of sib2, iclass 28, count 0 2006.202.01:50:10.99#ibcon#*after write, iclass 28, count 0 2006.202.01:50:10.99#ibcon#*before return 0, iclass 28, count 0 2006.202.01:50:10.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.202.01:50:10.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.202.01:50:10.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.202.01:50:10.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.202.01:50:10.99$vck44/va=7,5 2006.202.01:50:10.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.202.01:50:10.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.202.01:50:10.99#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:10.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.202.01:50:11.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.202.01:50:11.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.202.01:50:11.05#ibcon#enter wrdev, iclass 30, count 2 2006.202.01:50:11.05#ibcon#first serial, iclass 30, count 2 2006.202.01:50:11.05#ibcon#enter sib2, iclass 30, count 2 2006.202.01:50:11.05#ibcon#flushed, iclass 30, count 2 2006.202.01:50:11.05#ibcon#about to write, iclass 30, count 2 2006.202.01:50:11.05#ibcon#wrote, iclass 30, count 2 2006.202.01:50:11.05#ibcon#about to read 3, iclass 30, count 2 2006.202.01:50:11.07#ibcon#read 3, iclass 30, count 2 2006.202.01:50:11.07#ibcon#about to read 4, iclass 30, count 2 2006.202.01:50:11.07#ibcon#read 4, iclass 30, count 2 2006.202.01:50:11.07#ibcon#about to read 5, iclass 30, count 2 2006.202.01:50:11.07#ibcon#read 5, iclass 30, count 2 2006.202.01:50:11.07#ibcon#about to read 6, iclass 30, count 2 2006.202.01:50:11.07#ibcon#read 6, iclass 30, count 2 2006.202.01:50:11.07#ibcon#end of sib2, iclass 30, count 2 2006.202.01:50:11.07#ibcon#*mode == 0, iclass 30, count 2 2006.202.01:50:11.07#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.202.01:50:11.07#ibcon#[25=AT07-05\r\n] 2006.202.01:50:11.07#ibcon#*before write, iclass 30, count 2 2006.202.01:50:11.07#ibcon#enter sib2, iclass 30, count 2 2006.202.01:50:11.07#ibcon#flushed, iclass 30, count 2 2006.202.01:50:11.07#ibcon#about to write, iclass 30, count 2 2006.202.01:50:11.07#ibcon#wrote, iclass 30, count 2 2006.202.01:50:11.07#ibcon#about to read 3, iclass 30, count 2 2006.202.01:50:11.10#ibcon#read 3, iclass 30, count 2 2006.202.01:50:11.10#ibcon#about to read 4, iclass 30, count 2 2006.202.01:50:11.10#ibcon#read 4, iclass 30, count 2 2006.202.01:50:11.10#ibcon#about to read 5, iclass 30, count 2 2006.202.01:50:11.10#ibcon#read 5, iclass 30, count 2 2006.202.01:50:11.10#ibcon#about to read 6, iclass 30, count 2 2006.202.01:50:11.10#ibcon#read 6, iclass 30, count 2 2006.202.01:50:11.10#ibcon#end of sib2, iclass 30, count 2 2006.202.01:50:11.10#ibcon#*after write, iclass 30, count 2 2006.202.01:50:11.10#ibcon#*before return 0, iclass 30, count 2 2006.202.01:50:11.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.202.01:50:11.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.202.01:50:11.10#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.202.01:50:11.10#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:11.10#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.202.01:50:11.22#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.202.01:50:11.22#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.202.01:50:11.22#ibcon#enter wrdev, iclass 30, count 0 2006.202.01:50:11.22#ibcon#first serial, iclass 30, count 0 2006.202.01:50:11.22#ibcon#enter sib2, iclass 30, count 0 2006.202.01:50:11.22#ibcon#flushed, iclass 30, count 0 2006.202.01:50:11.22#ibcon#about to write, iclass 30, count 0 2006.202.01:50:11.22#ibcon#wrote, iclass 30, count 0 2006.202.01:50:11.22#ibcon#about to read 3, iclass 30, count 0 2006.202.01:50:11.24#ibcon#read 3, iclass 30, count 0 2006.202.01:50:11.24#ibcon#about to read 4, iclass 30, count 0 2006.202.01:50:11.24#ibcon#read 4, iclass 30, count 0 2006.202.01:50:11.24#ibcon#about to read 5, iclass 30, count 0 2006.202.01:50:11.24#ibcon#read 5, iclass 30, count 0 2006.202.01:50:11.24#ibcon#about to read 6, iclass 30, count 0 2006.202.01:50:11.24#ibcon#read 6, iclass 30, count 0 2006.202.01:50:11.24#ibcon#end of sib2, iclass 30, count 0 2006.202.01:50:11.24#ibcon#*mode == 0, iclass 30, count 0 2006.202.01:50:11.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.202.01:50:11.24#ibcon#[25=USB\r\n] 2006.202.01:50:11.24#ibcon#*before write, iclass 30, count 0 2006.202.01:50:11.24#ibcon#enter sib2, iclass 30, count 0 2006.202.01:50:11.24#ibcon#flushed, iclass 30, count 0 2006.202.01:50:11.24#ibcon#about to write, iclass 30, count 0 2006.202.01:50:11.24#ibcon#wrote, iclass 30, count 0 2006.202.01:50:11.24#ibcon#about to read 3, iclass 30, count 0 2006.202.01:50:11.27#ibcon#read 3, iclass 30, count 0 2006.202.01:50:11.27#ibcon#about to read 4, iclass 30, count 0 2006.202.01:50:11.27#ibcon#read 4, iclass 30, count 0 2006.202.01:50:11.27#ibcon#about to read 5, iclass 30, count 0 2006.202.01:50:11.27#ibcon#read 5, iclass 30, count 0 2006.202.01:50:11.27#ibcon#about to read 6, iclass 30, count 0 2006.202.01:50:11.27#ibcon#read 6, iclass 30, count 0 2006.202.01:50:11.27#ibcon#end of sib2, iclass 30, count 0 2006.202.01:50:11.27#ibcon#*after write, iclass 30, count 0 2006.202.01:50:11.27#ibcon#*before return 0, iclass 30, count 0 2006.202.01:50:11.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.202.01:50:11.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.202.01:50:11.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.202.01:50:11.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.202.01:50:11.27$vck44/valo=8,884.99 2006.202.01:50:11.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.202.01:50:11.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.202.01:50:11.27#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:11.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:11.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:11.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:11.27#ibcon#enter wrdev, iclass 32, count 0 2006.202.01:50:11.27#ibcon#first serial, iclass 32, count 0 2006.202.01:50:11.27#ibcon#enter sib2, iclass 32, count 0 2006.202.01:50:11.27#ibcon#flushed, iclass 32, count 0 2006.202.01:50:11.27#ibcon#about to write, iclass 32, count 0 2006.202.01:50:11.27#ibcon#wrote, iclass 32, count 0 2006.202.01:50:11.27#ibcon#about to read 3, iclass 32, count 0 2006.202.01:50:11.29#ibcon#read 3, iclass 32, count 0 2006.202.01:50:11.29#ibcon#about to read 4, iclass 32, count 0 2006.202.01:50:11.29#ibcon#read 4, iclass 32, count 0 2006.202.01:50:11.29#ibcon#about to read 5, iclass 32, count 0 2006.202.01:50:11.29#ibcon#read 5, iclass 32, count 0 2006.202.01:50:11.29#ibcon#about to read 6, iclass 32, count 0 2006.202.01:50:11.29#ibcon#read 6, iclass 32, count 0 2006.202.01:50:11.29#ibcon#end of sib2, iclass 32, count 0 2006.202.01:50:11.29#ibcon#*mode == 0, iclass 32, count 0 2006.202.01:50:11.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.01:50:11.29#ibcon#[26=FRQ=08,884.99\r\n] 2006.202.01:50:11.29#ibcon#*before write, iclass 32, count 0 2006.202.01:50:11.29#ibcon#enter sib2, iclass 32, count 0 2006.202.01:50:11.29#ibcon#flushed, iclass 32, count 0 2006.202.01:50:11.29#ibcon#about to write, iclass 32, count 0 2006.202.01:50:11.29#ibcon#wrote, iclass 32, count 0 2006.202.01:50:11.29#ibcon#about to read 3, iclass 32, count 0 2006.202.01:50:11.33#ibcon#read 3, iclass 32, count 0 2006.202.01:50:11.33#ibcon#about to read 4, iclass 32, count 0 2006.202.01:50:11.33#ibcon#read 4, iclass 32, count 0 2006.202.01:50:11.33#ibcon#about to read 5, iclass 32, count 0 2006.202.01:50:11.33#ibcon#read 5, iclass 32, count 0 2006.202.01:50:11.33#ibcon#about to read 6, iclass 32, count 0 2006.202.01:50:11.33#ibcon#read 6, iclass 32, count 0 2006.202.01:50:11.33#ibcon#end of sib2, iclass 32, count 0 2006.202.01:50:11.33#ibcon#*after write, iclass 32, count 0 2006.202.01:50:11.33#ibcon#*before return 0, iclass 32, count 0 2006.202.01:50:11.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:11.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:11.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.01:50:11.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.01:50:11.33$vck44/va=8,4 2006.202.01:50:11.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.202.01:50:11.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.202.01:50:11.33#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:11.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:11.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:11.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:11.39#ibcon#enter wrdev, iclass 34, count 2 2006.202.01:50:11.39#ibcon#first serial, iclass 34, count 2 2006.202.01:50:11.39#ibcon#enter sib2, iclass 34, count 2 2006.202.01:50:11.39#ibcon#flushed, iclass 34, count 2 2006.202.01:50:11.39#ibcon#about to write, iclass 34, count 2 2006.202.01:50:11.39#ibcon#wrote, iclass 34, count 2 2006.202.01:50:11.39#ibcon#about to read 3, iclass 34, count 2 2006.202.01:50:11.41#ibcon#read 3, iclass 34, count 2 2006.202.01:50:11.41#ibcon#about to read 4, iclass 34, count 2 2006.202.01:50:11.41#ibcon#read 4, iclass 34, count 2 2006.202.01:50:11.41#ibcon#about to read 5, iclass 34, count 2 2006.202.01:50:11.41#ibcon#read 5, iclass 34, count 2 2006.202.01:50:11.41#ibcon#about to read 6, iclass 34, count 2 2006.202.01:50:11.41#ibcon#read 6, iclass 34, count 2 2006.202.01:50:11.41#ibcon#end of sib2, iclass 34, count 2 2006.202.01:50:11.41#ibcon#*mode == 0, iclass 34, count 2 2006.202.01:50:11.41#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.202.01:50:11.41#ibcon#[25=AT08-04\r\n] 2006.202.01:50:11.41#ibcon#*before write, iclass 34, count 2 2006.202.01:50:11.41#ibcon#enter sib2, iclass 34, count 2 2006.202.01:50:11.41#ibcon#flushed, iclass 34, count 2 2006.202.01:50:11.41#ibcon#about to write, iclass 34, count 2 2006.202.01:50:11.41#ibcon#wrote, iclass 34, count 2 2006.202.01:50:11.41#ibcon#about to read 3, iclass 34, count 2 2006.202.01:50:11.44#ibcon#read 3, iclass 34, count 2 2006.202.01:50:11.44#ibcon#about to read 4, iclass 34, count 2 2006.202.01:50:11.44#ibcon#read 4, iclass 34, count 2 2006.202.01:50:11.44#ibcon#about to read 5, iclass 34, count 2 2006.202.01:50:11.44#ibcon#read 5, iclass 34, count 2 2006.202.01:50:11.44#ibcon#about to read 6, iclass 34, count 2 2006.202.01:50:11.44#ibcon#read 6, iclass 34, count 2 2006.202.01:50:11.44#ibcon#end of sib2, iclass 34, count 2 2006.202.01:50:11.44#ibcon#*after write, iclass 34, count 2 2006.202.01:50:11.44#ibcon#*before return 0, iclass 34, count 2 2006.202.01:50:11.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:11.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:11.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.202.01:50:11.44#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:11.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:11.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:11.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:11.56#ibcon#enter wrdev, iclass 34, count 0 2006.202.01:50:11.56#ibcon#first serial, iclass 34, count 0 2006.202.01:50:11.56#ibcon#enter sib2, iclass 34, count 0 2006.202.01:50:11.56#ibcon#flushed, iclass 34, count 0 2006.202.01:50:11.56#ibcon#about to write, iclass 34, count 0 2006.202.01:50:11.56#ibcon#wrote, iclass 34, count 0 2006.202.01:50:11.56#ibcon#about to read 3, iclass 34, count 0 2006.202.01:50:11.58#ibcon#read 3, iclass 34, count 0 2006.202.01:50:11.58#ibcon#about to read 4, iclass 34, count 0 2006.202.01:50:11.58#ibcon#read 4, iclass 34, count 0 2006.202.01:50:11.58#ibcon#about to read 5, iclass 34, count 0 2006.202.01:50:11.58#ibcon#read 5, iclass 34, count 0 2006.202.01:50:11.58#ibcon#about to read 6, iclass 34, count 0 2006.202.01:50:11.58#ibcon#read 6, iclass 34, count 0 2006.202.01:50:11.58#ibcon#end of sib2, iclass 34, count 0 2006.202.01:50:11.58#ibcon#*mode == 0, iclass 34, count 0 2006.202.01:50:11.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.01:50:11.58#ibcon#[25=USB\r\n] 2006.202.01:50:11.58#ibcon#*before write, iclass 34, count 0 2006.202.01:50:11.58#ibcon#enter sib2, iclass 34, count 0 2006.202.01:50:11.58#ibcon#flushed, iclass 34, count 0 2006.202.01:50:11.58#ibcon#about to write, iclass 34, count 0 2006.202.01:50:11.58#ibcon#wrote, iclass 34, count 0 2006.202.01:50:11.58#ibcon#about to read 3, iclass 34, count 0 2006.202.01:50:11.61#ibcon#read 3, iclass 34, count 0 2006.202.01:50:11.61#ibcon#about to read 4, iclass 34, count 0 2006.202.01:50:11.61#ibcon#read 4, iclass 34, count 0 2006.202.01:50:11.61#ibcon#about to read 5, iclass 34, count 0 2006.202.01:50:11.61#ibcon#read 5, iclass 34, count 0 2006.202.01:50:11.61#ibcon#about to read 6, iclass 34, count 0 2006.202.01:50:11.61#ibcon#read 6, iclass 34, count 0 2006.202.01:50:11.61#ibcon#end of sib2, iclass 34, count 0 2006.202.01:50:11.61#ibcon#*after write, iclass 34, count 0 2006.202.01:50:11.61#ibcon#*before return 0, iclass 34, count 0 2006.202.01:50:11.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:11.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:11.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.01:50:11.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.01:50:11.61$vck44/vblo=1,629.99 2006.202.01:50:11.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.202.01:50:11.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.202.01:50:11.61#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:11.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:11.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:11.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:11.61#ibcon#enter wrdev, iclass 36, count 0 2006.202.01:50:11.61#ibcon#first serial, iclass 36, count 0 2006.202.01:50:11.61#ibcon#enter sib2, iclass 36, count 0 2006.202.01:50:11.61#ibcon#flushed, iclass 36, count 0 2006.202.01:50:11.61#ibcon#about to write, iclass 36, count 0 2006.202.01:50:11.61#ibcon#wrote, iclass 36, count 0 2006.202.01:50:11.61#ibcon#about to read 3, iclass 36, count 0 2006.202.01:50:11.63#ibcon#read 3, iclass 36, count 0 2006.202.01:50:11.63#ibcon#about to read 4, iclass 36, count 0 2006.202.01:50:11.63#ibcon#read 4, iclass 36, count 0 2006.202.01:50:11.63#ibcon#about to read 5, iclass 36, count 0 2006.202.01:50:11.63#ibcon#read 5, iclass 36, count 0 2006.202.01:50:11.63#ibcon#about to read 6, iclass 36, count 0 2006.202.01:50:11.63#ibcon#read 6, iclass 36, count 0 2006.202.01:50:11.63#ibcon#end of sib2, iclass 36, count 0 2006.202.01:50:11.63#ibcon#*mode == 0, iclass 36, count 0 2006.202.01:50:11.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.01:50:11.63#ibcon#[28=FRQ=01,629.99\r\n] 2006.202.01:50:11.63#ibcon#*before write, iclass 36, count 0 2006.202.01:50:11.63#ibcon#enter sib2, iclass 36, count 0 2006.202.01:50:11.63#ibcon#flushed, iclass 36, count 0 2006.202.01:50:11.63#ibcon#about to write, iclass 36, count 0 2006.202.01:50:11.63#ibcon#wrote, iclass 36, count 0 2006.202.01:50:11.63#ibcon#about to read 3, iclass 36, count 0 2006.202.01:50:11.67#ibcon#read 3, iclass 36, count 0 2006.202.01:50:11.67#ibcon#about to read 4, iclass 36, count 0 2006.202.01:50:11.67#ibcon#read 4, iclass 36, count 0 2006.202.01:50:11.67#ibcon#about to read 5, iclass 36, count 0 2006.202.01:50:11.67#ibcon#read 5, iclass 36, count 0 2006.202.01:50:11.67#ibcon#about to read 6, iclass 36, count 0 2006.202.01:50:11.67#ibcon#read 6, iclass 36, count 0 2006.202.01:50:11.67#ibcon#end of sib2, iclass 36, count 0 2006.202.01:50:11.67#ibcon#*after write, iclass 36, count 0 2006.202.01:50:11.67#ibcon#*before return 0, iclass 36, count 0 2006.202.01:50:11.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:11.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:11.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.01:50:11.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.01:50:11.67$vck44/vb=1,4 2006.202.01:50:11.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.202.01:50:11.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.202.01:50:11.67#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:11.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.202.01:50:11.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.202.01:50:11.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.202.01:50:11.67#ibcon#enter wrdev, iclass 38, count 2 2006.202.01:50:11.67#ibcon#first serial, iclass 38, count 2 2006.202.01:50:11.67#ibcon#enter sib2, iclass 38, count 2 2006.202.01:50:11.67#ibcon#flushed, iclass 38, count 2 2006.202.01:50:11.67#ibcon#about to write, iclass 38, count 2 2006.202.01:50:11.67#ibcon#wrote, iclass 38, count 2 2006.202.01:50:11.67#ibcon#about to read 3, iclass 38, count 2 2006.202.01:50:11.69#ibcon#read 3, iclass 38, count 2 2006.202.01:50:11.69#ibcon#about to read 4, iclass 38, count 2 2006.202.01:50:11.69#ibcon#read 4, iclass 38, count 2 2006.202.01:50:11.69#ibcon#about to read 5, iclass 38, count 2 2006.202.01:50:11.69#ibcon#read 5, iclass 38, count 2 2006.202.01:50:11.69#ibcon#about to read 6, iclass 38, count 2 2006.202.01:50:11.69#ibcon#read 6, iclass 38, count 2 2006.202.01:50:11.69#ibcon#end of sib2, iclass 38, count 2 2006.202.01:50:11.69#ibcon#*mode == 0, iclass 38, count 2 2006.202.01:50:11.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.202.01:50:11.69#ibcon#[27=AT01-04\r\n] 2006.202.01:50:11.69#ibcon#*before write, iclass 38, count 2 2006.202.01:50:11.69#ibcon#enter sib2, iclass 38, count 2 2006.202.01:50:11.69#ibcon#flushed, iclass 38, count 2 2006.202.01:50:11.69#ibcon#about to write, iclass 38, count 2 2006.202.01:50:11.69#ibcon#wrote, iclass 38, count 2 2006.202.01:50:11.69#ibcon#about to read 3, iclass 38, count 2 2006.202.01:50:11.72#ibcon#read 3, iclass 38, count 2 2006.202.01:50:11.72#ibcon#about to read 4, iclass 38, count 2 2006.202.01:50:11.72#ibcon#read 4, iclass 38, count 2 2006.202.01:50:11.72#ibcon#about to read 5, iclass 38, count 2 2006.202.01:50:11.72#ibcon#read 5, iclass 38, count 2 2006.202.01:50:11.72#ibcon#about to read 6, iclass 38, count 2 2006.202.01:50:11.72#ibcon#read 6, iclass 38, count 2 2006.202.01:50:11.72#ibcon#end of sib2, iclass 38, count 2 2006.202.01:50:11.72#ibcon#*after write, iclass 38, count 2 2006.202.01:50:11.72#ibcon#*before return 0, iclass 38, count 2 2006.202.01:50:11.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.202.01:50:11.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.202.01:50:11.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.202.01:50:11.72#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:11.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.202.01:50:11.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.202.01:50:11.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.202.01:50:11.84#ibcon#enter wrdev, iclass 38, count 0 2006.202.01:50:11.84#ibcon#first serial, iclass 38, count 0 2006.202.01:50:11.84#ibcon#enter sib2, iclass 38, count 0 2006.202.01:50:11.84#ibcon#flushed, iclass 38, count 0 2006.202.01:50:11.84#ibcon#about to write, iclass 38, count 0 2006.202.01:50:11.84#ibcon#wrote, iclass 38, count 0 2006.202.01:50:11.84#ibcon#about to read 3, iclass 38, count 0 2006.202.01:50:11.86#ibcon#read 3, iclass 38, count 0 2006.202.01:50:11.86#ibcon#about to read 4, iclass 38, count 0 2006.202.01:50:11.86#ibcon#read 4, iclass 38, count 0 2006.202.01:50:11.86#ibcon#about to read 5, iclass 38, count 0 2006.202.01:50:11.86#ibcon#read 5, iclass 38, count 0 2006.202.01:50:11.86#ibcon#about to read 6, iclass 38, count 0 2006.202.01:50:11.86#ibcon#read 6, iclass 38, count 0 2006.202.01:50:11.86#ibcon#end of sib2, iclass 38, count 0 2006.202.01:50:11.86#ibcon#*mode == 0, iclass 38, count 0 2006.202.01:50:11.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.01:50:11.86#ibcon#[27=USB\r\n] 2006.202.01:50:11.86#ibcon#*before write, iclass 38, count 0 2006.202.01:50:11.86#ibcon#enter sib2, iclass 38, count 0 2006.202.01:50:11.86#ibcon#flushed, iclass 38, count 0 2006.202.01:50:11.86#ibcon#about to write, iclass 38, count 0 2006.202.01:50:11.86#ibcon#wrote, iclass 38, count 0 2006.202.01:50:11.86#ibcon#about to read 3, iclass 38, count 0 2006.202.01:50:11.89#ibcon#read 3, iclass 38, count 0 2006.202.01:50:11.89#ibcon#about to read 4, iclass 38, count 0 2006.202.01:50:11.89#ibcon#read 4, iclass 38, count 0 2006.202.01:50:11.89#ibcon#about to read 5, iclass 38, count 0 2006.202.01:50:11.89#ibcon#read 5, iclass 38, count 0 2006.202.01:50:11.89#ibcon#about to read 6, iclass 38, count 0 2006.202.01:50:11.89#ibcon#read 6, iclass 38, count 0 2006.202.01:50:11.89#ibcon#end of sib2, iclass 38, count 0 2006.202.01:50:11.89#ibcon#*after write, iclass 38, count 0 2006.202.01:50:11.89#ibcon#*before return 0, iclass 38, count 0 2006.202.01:50:11.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.202.01:50:11.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.202.01:50:11.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.01:50:11.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.01:50:11.89$vck44/vblo=2,634.99 2006.202.01:50:11.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.202.01:50:11.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.202.01:50:11.89#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:11.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:11.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:11.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:11.89#ibcon#enter wrdev, iclass 40, count 0 2006.202.01:50:11.89#ibcon#first serial, iclass 40, count 0 2006.202.01:50:11.89#ibcon#enter sib2, iclass 40, count 0 2006.202.01:50:11.89#ibcon#flushed, iclass 40, count 0 2006.202.01:50:11.89#ibcon#about to write, iclass 40, count 0 2006.202.01:50:11.89#ibcon#wrote, iclass 40, count 0 2006.202.01:50:11.89#ibcon#about to read 3, iclass 40, count 0 2006.202.01:50:11.91#ibcon#read 3, iclass 40, count 0 2006.202.01:50:11.91#ibcon#about to read 4, iclass 40, count 0 2006.202.01:50:11.91#ibcon#read 4, iclass 40, count 0 2006.202.01:50:11.91#ibcon#about to read 5, iclass 40, count 0 2006.202.01:50:11.91#ibcon#read 5, iclass 40, count 0 2006.202.01:50:11.91#ibcon#about to read 6, iclass 40, count 0 2006.202.01:50:11.91#ibcon#read 6, iclass 40, count 0 2006.202.01:50:11.91#ibcon#end of sib2, iclass 40, count 0 2006.202.01:50:11.91#ibcon#*mode == 0, iclass 40, count 0 2006.202.01:50:11.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.202.01:50:11.91#ibcon#[28=FRQ=02,634.99\r\n] 2006.202.01:50:11.91#ibcon#*before write, iclass 40, count 0 2006.202.01:50:11.91#ibcon#enter sib2, iclass 40, count 0 2006.202.01:50:11.91#ibcon#flushed, iclass 40, count 0 2006.202.01:50:11.91#ibcon#about to write, iclass 40, count 0 2006.202.01:50:11.91#ibcon#wrote, iclass 40, count 0 2006.202.01:50:11.91#ibcon#about to read 3, iclass 40, count 0 2006.202.01:50:11.95#ibcon#read 3, iclass 40, count 0 2006.202.01:50:11.95#ibcon#about to read 4, iclass 40, count 0 2006.202.01:50:11.95#ibcon#read 4, iclass 40, count 0 2006.202.01:50:11.95#ibcon#about to read 5, iclass 40, count 0 2006.202.01:50:11.95#ibcon#read 5, iclass 40, count 0 2006.202.01:50:11.95#ibcon#about to read 6, iclass 40, count 0 2006.202.01:50:11.95#ibcon#read 6, iclass 40, count 0 2006.202.01:50:11.95#ibcon#end of sib2, iclass 40, count 0 2006.202.01:50:11.95#ibcon#*after write, iclass 40, count 0 2006.202.01:50:11.95#ibcon#*before return 0, iclass 40, count 0 2006.202.01:50:11.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:11.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.202.01:50:11.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.202.01:50:11.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.202.01:50:11.95$vck44/vb=2,5 2006.202.01:50:11.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.202.01:50:11.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.202.01:50:11.95#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:11.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:12.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:12.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:12.03#ibcon#enter wrdev, iclass 4, count 2 2006.202.01:50:12.03#ibcon#first serial, iclass 4, count 2 2006.202.01:50:12.03#ibcon#enter sib2, iclass 4, count 2 2006.202.01:50:12.03#ibcon#flushed, iclass 4, count 2 2006.202.01:50:12.03#ibcon#about to write, iclass 4, count 2 2006.202.01:50:12.03#ibcon#wrote, iclass 4, count 2 2006.202.01:50:12.03#ibcon#about to read 3, iclass 4, count 2 2006.202.01:50:12.05#ibcon#read 3, iclass 4, count 2 2006.202.01:50:12.05#ibcon#about to read 4, iclass 4, count 2 2006.202.01:50:12.05#ibcon#read 4, iclass 4, count 2 2006.202.01:50:12.05#ibcon#about to read 5, iclass 4, count 2 2006.202.01:50:12.05#ibcon#read 5, iclass 4, count 2 2006.202.01:50:12.05#ibcon#about to read 6, iclass 4, count 2 2006.202.01:50:12.05#ibcon#read 6, iclass 4, count 2 2006.202.01:50:12.05#ibcon#end of sib2, iclass 4, count 2 2006.202.01:50:12.05#ibcon#*mode == 0, iclass 4, count 2 2006.202.01:50:12.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.202.01:50:12.05#ibcon#[27=AT02-05\r\n] 2006.202.01:50:12.05#ibcon#*before write, iclass 4, count 2 2006.202.01:50:12.05#ibcon#enter sib2, iclass 4, count 2 2006.202.01:50:12.05#ibcon#flushed, iclass 4, count 2 2006.202.01:50:12.05#ibcon#about to write, iclass 4, count 2 2006.202.01:50:12.05#ibcon#wrote, iclass 4, count 2 2006.202.01:50:12.05#ibcon#about to read 3, iclass 4, count 2 2006.202.01:50:12.08#ibcon#read 3, iclass 4, count 2 2006.202.01:50:12.08#ibcon#about to read 4, iclass 4, count 2 2006.202.01:50:12.08#ibcon#read 4, iclass 4, count 2 2006.202.01:50:12.08#ibcon#about to read 5, iclass 4, count 2 2006.202.01:50:12.08#ibcon#read 5, iclass 4, count 2 2006.202.01:50:12.08#ibcon#about to read 6, iclass 4, count 2 2006.202.01:50:12.08#ibcon#read 6, iclass 4, count 2 2006.202.01:50:12.08#ibcon#end of sib2, iclass 4, count 2 2006.202.01:50:12.08#ibcon#*after write, iclass 4, count 2 2006.202.01:50:12.08#ibcon#*before return 0, iclass 4, count 2 2006.202.01:50:12.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:12.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.202.01:50:12.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.202.01:50:12.08#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:12.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:12.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:12.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:12.20#ibcon#enter wrdev, iclass 4, count 0 2006.202.01:50:12.20#ibcon#first serial, iclass 4, count 0 2006.202.01:50:12.20#ibcon#enter sib2, iclass 4, count 0 2006.202.01:50:12.20#ibcon#flushed, iclass 4, count 0 2006.202.01:50:12.20#ibcon#about to write, iclass 4, count 0 2006.202.01:50:12.20#ibcon#wrote, iclass 4, count 0 2006.202.01:50:12.20#ibcon#about to read 3, iclass 4, count 0 2006.202.01:50:12.22#ibcon#read 3, iclass 4, count 0 2006.202.01:50:12.22#ibcon#about to read 4, iclass 4, count 0 2006.202.01:50:12.22#ibcon#read 4, iclass 4, count 0 2006.202.01:50:12.22#ibcon#about to read 5, iclass 4, count 0 2006.202.01:50:12.22#ibcon#read 5, iclass 4, count 0 2006.202.01:50:12.22#ibcon#about to read 6, iclass 4, count 0 2006.202.01:50:12.22#ibcon#read 6, iclass 4, count 0 2006.202.01:50:12.22#ibcon#end of sib2, iclass 4, count 0 2006.202.01:50:12.22#ibcon#*mode == 0, iclass 4, count 0 2006.202.01:50:12.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.202.01:50:12.22#ibcon#[27=USB\r\n] 2006.202.01:50:12.22#ibcon#*before write, iclass 4, count 0 2006.202.01:50:12.22#ibcon#enter sib2, iclass 4, count 0 2006.202.01:50:12.22#ibcon#flushed, iclass 4, count 0 2006.202.01:50:12.22#ibcon#about to write, iclass 4, count 0 2006.202.01:50:12.22#ibcon#wrote, iclass 4, count 0 2006.202.01:50:12.22#ibcon#about to read 3, iclass 4, count 0 2006.202.01:50:12.25#ibcon#read 3, iclass 4, count 0 2006.202.01:50:12.25#ibcon#about to read 4, iclass 4, count 0 2006.202.01:50:12.25#ibcon#read 4, iclass 4, count 0 2006.202.01:50:12.25#ibcon#about to read 5, iclass 4, count 0 2006.202.01:50:12.25#ibcon#read 5, iclass 4, count 0 2006.202.01:50:12.25#ibcon#about to read 6, iclass 4, count 0 2006.202.01:50:12.25#ibcon#read 6, iclass 4, count 0 2006.202.01:50:12.25#ibcon#end of sib2, iclass 4, count 0 2006.202.01:50:12.25#ibcon#*after write, iclass 4, count 0 2006.202.01:50:12.25#ibcon#*before return 0, iclass 4, count 0 2006.202.01:50:12.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:12.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.202.01:50:12.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.202.01:50:12.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.202.01:50:12.25$vck44/vblo=3,649.99 2006.202.01:50:12.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.202.01:50:12.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.202.01:50:12.25#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:12.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:12.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:12.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:12.25#ibcon#enter wrdev, iclass 6, count 0 2006.202.01:50:12.25#ibcon#first serial, iclass 6, count 0 2006.202.01:50:12.25#ibcon#enter sib2, iclass 6, count 0 2006.202.01:50:12.25#ibcon#flushed, iclass 6, count 0 2006.202.01:50:12.25#ibcon#about to write, iclass 6, count 0 2006.202.01:50:12.25#ibcon#wrote, iclass 6, count 0 2006.202.01:50:12.25#ibcon#about to read 3, iclass 6, count 0 2006.202.01:50:12.27#ibcon#read 3, iclass 6, count 0 2006.202.01:50:12.27#ibcon#about to read 4, iclass 6, count 0 2006.202.01:50:12.27#ibcon#read 4, iclass 6, count 0 2006.202.01:50:12.27#ibcon#about to read 5, iclass 6, count 0 2006.202.01:50:12.27#ibcon#read 5, iclass 6, count 0 2006.202.01:50:12.27#ibcon#about to read 6, iclass 6, count 0 2006.202.01:50:12.27#ibcon#read 6, iclass 6, count 0 2006.202.01:50:12.27#ibcon#end of sib2, iclass 6, count 0 2006.202.01:50:12.27#ibcon#*mode == 0, iclass 6, count 0 2006.202.01:50:12.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.202.01:50:12.27#ibcon#[28=FRQ=03,649.99\r\n] 2006.202.01:50:12.27#ibcon#*before write, iclass 6, count 0 2006.202.01:50:12.27#ibcon#enter sib2, iclass 6, count 0 2006.202.01:50:12.27#ibcon#flushed, iclass 6, count 0 2006.202.01:50:12.27#ibcon#about to write, iclass 6, count 0 2006.202.01:50:12.27#ibcon#wrote, iclass 6, count 0 2006.202.01:50:12.27#ibcon#about to read 3, iclass 6, count 0 2006.202.01:50:12.31#ibcon#read 3, iclass 6, count 0 2006.202.01:50:12.31#ibcon#about to read 4, iclass 6, count 0 2006.202.01:50:12.31#ibcon#read 4, iclass 6, count 0 2006.202.01:50:12.31#ibcon#about to read 5, iclass 6, count 0 2006.202.01:50:12.31#ibcon#read 5, iclass 6, count 0 2006.202.01:50:12.31#ibcon#about to read 6, iclass 6, count 0 2006.202.01:50:12.31#ibcon#read 6, iclass 6, count 0 2006.202.01:50:12.31#ibcon#end of sib2, iclass 6, count 0 2006.202.01:50:12.31#ibcon#*after write, iclass 6, count 0 2006.202.01:50:12.31#ibcon#*before return 0, iclass 6, count 0 2006.202.01:50:12.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:12.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.202.01:50:12.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.202.01:50:12.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.202.01:50:12.31$vck44/vb=3,4 2006.202.01:50:12.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.202.01:50:12.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.202.01:50:12.31#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:12.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:12.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:12.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:12.37#ibcon#enter wrdev, iclass 10, count 2 2006.202.01:50:12.37#ibcon#first serial, iclass 10, count 2 2006.202.01:50:12.37#ibcon#enter sib2, iclass 10, count 2 2006.202.01:50:12.37#ibcon#flushed, iclass 10, count 2 2006.202.01:50:12.37#ibcon#about to write, iclass 10, count 2 2006.202.01:50:12.37#ibcon#wrote, iclass 10, count 2 2006.202.01:50:12.37#ibcon#about to read 3, iclass 10, count 2 2006.202.01:50:12.39#ibcon#read 3, iclass 10, count 2 2006.202.01:50:12.39#ibcon#about to read 4, iclass 10, count 2 2006.202.01:50:12.39#ibcon#read 4, iclass 10, count 2 2006.202.01:50:12.39#ibcon#about to read 5, iclass 10, count 2 2006.202.01:50:12.39#ibcon#read 5, iclass 10, count 2 2006.202.01:50:12.39#ibcon#about to read 6, iclass 10, count 2 2006.202.01:50:12.39#ibcon#read 6, iclass 10, count 2 2006.202.01:50:12.39#ibcon#end of sib2, iclass 10, count 2 2006.202.01:50:12.39#ibcon#*mode == 0, iclass 10, count 2 2006.202.01:50:12.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.202.01:50:12.39#ibcon#[27=AT03-04\r\n] 2006.202.01:50:12.39#ibcon#*before write, iclass 10, count 2 2006.202.01:50:12.39#ibcon#enter sib2, iclass 10, count 2 2006.202.01:50:12.39#ibcon#flushed, iclass 10, count 2 2006.202.01:50:12.39#ibcon#about to write, iclass 10, count 2 2006.202.01:50:12.39#ibcon#wrote, iclass 10, count 2 2006.202.01:50:12.39#ibcon#about to read 3, iclass 10, count 2 2006.202.01:50:12.42#ibcon#read 3, iclass 10, count 2 2006.202.01:50:12.42#ibcon#about to read 4, iclass 10, count 2 2006.202.01:50:12.42#ibcon#read 4, iclass 10, count 2 2006.202.01:50:12.42#ibcon#about to read 5, iclass 10, count 2 2006.202.01:50:12.42#ibcon#read 5, iclass 10, count 2 2006.202.01:50:12.42#ibcon#about to read 6, iclass 10, count 2 2006.202.01:50:12.42#ibcon#read 6, iclass 10, count 2 2006.202.01:50:12.42#ibcon#end of sib2, iclass 10, count 2 2006.202.01:50:12.42#ibcon#*after write, iclass 10, count 2 2006.202.01:50:12.42#ibcon#*before return 0, iclass 10, count 2 2006.202.01:50:12.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:12.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.202.01:50:12.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.202.01:50:12.42#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:12.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:12.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:12.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:12.54#ibcon#enter wrdev, iclass 10, count 0 2006.202.01:50:12.54#ibcon#first serial, iclass 10, count 0 2006.202.01:50:12.54#ibcon#enter sib2, iclass 10, count 0 2006.202.01:50:12.54#ibcon#flushed, iclass 10, count 0 2006.202.01:50:12.54#ibcon#about to write, iclass 10, count 0 2006.202.01:50:12.54#ibcon#wrote, iclass 10, count 0 2006.202.01:50:12.54#ibcon#about to read 3, iclass 10, count 0 2006.202.01:50:12.56#ibcon#read 3, iclass 10, count 0 2006.202.01:50:12.56#ibcon#about to read 4, iclass 10, count 0 2006.202.01:50:12.56#ibcon#read 4, iclass 10, count 0 2006.202.01:50:12.56#ibcon#about to read 5, iclass 10, count 0 2006.202.01:50:12.56#ibcon#read 5, iclass 10, count 0 2006.202.01:50:12.56#ibcon#about to read 6, iclass 10, count 0 2006.202.01:50:12.56#ibcon#read 6, iclass 10, count 0 2006.202.01:50:12.56#ibcon#end of sib2, iclass 10, count 0 2006.202.01:50:12.56#ibcon#*mode == 0, iclass 10, count 0 2006.202.01:50:12.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.202.01:50:12.56#ibcon#[27=USB\r\n] 2006.202.01:50:12.56#ibcon#*before write, iclass 10, count 0 2006.202.01:50:12.56#ibcon#enter sib2, iclass 10, count 0 2006.202.01:50:12.56#ibcon#flushed, iclass 10, count 0 2006.202.01:50:12.56#ibcon#about to write, iclass 10, count 0 2006.202.01:50:12.56#ibcon#wrote, iclass 10, count 0 2006.202.01:50:12.56#ibcon#about to read 3, iclass 10, count 0 2006.202.01:50:12.59#ibcon#read 3, iclass 10, count 0 2006.202.01:50:12.59#ibcon#about to read 4, iclass 10, count 0 2006.202.01:50:12.59#ibcon#read 4, iclass 10, count 0 2006.202.01:50:12.59#ibcon#about to read 5, iclass 10, count 0 2006.202.01:50:12.59#ibcon#read 5, iclass 10, count 0 2006.202.01:50:12.59#ibcon#about to read 6, iclass 10, count 0 2006.202.01:50:12.59#ibcon#read 6, iclass 10, count 0 2006.202.01:50:12.59#ibcon#end of sib2, iclass 10, count 0 2006.202.01:50:12.59#ibcon#*after write, iclass 10, count 0 2006.202.01:50:12.59#ibcon#*before return 0, iclass 10, count 0 2006.202.01:50:12.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:12.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.202.01:50:12.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.202.01:50:12.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.202.01:50:12.59$vck44/vblo=4,679.99 2006.202.01:50:12.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.202.01:50:12.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.202.01:50:12.59#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:12.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:12.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:12.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:12.59#ibcon#enter wrdev, iclass 12, count 0 2006.202.01:50:12.59#ibcon#first serial, iclass 12, count 0 2006.202.01:50:12.59#ibcon#enter sib2, iclass 12, count 0 2006.202.01:50:12.59#ibcon#flushed, iclass 12, count 0 2006.202.01:50:12.59#ibcon#about to write, iclass 12, count 0 2006.202.01:50:12.59#ibcon#wrote, iclass 12, count 0 2006.202.01:50:12.59#ibcon#about to read 3, iclass 12, count 0 2006.202.01:50:12.61#ibcon#read 3, iclass 12, count 0 2006.202.01:50:12.61#ibcon#about to read 4, iclass 12, count 0 2006.202.01:50:12.61#ibcon#read 4, iclass 12, count 0 2006.202.01:50:12.61#ibcon#about to read 5, iclass 12, count 0 2006.202.01:50:12.61#ibcon#read 5, iclass 12, count 0 2006.202.01:50:12.61#ibcon#about to read 6, iclass 12, count 0 2006.202.01:50:12.61#ibcon#read 6, iclass 12, count 0 2006.202.01:50:12.61#ibcon#end of sib2, iclass 12, count 0 2006.202.01:50:12.61#ibcon#*mode == 0, iclass 12, count 0 2006.202.01:50:12.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.202.01:50:12.61#ibcon#[28=FRQ=04,679.99\r\n] 2006.202.01:50:12.61#ibcon#*before write, iclass 12, count 0 2006.202.01:50:12.61#ibcon#enter sib2, iclass 12, count 0 2006.202.01:50:12.61#ibcon#flushed, iclass 12, count 0 2006.202.01:50:12.61#ibcon#about to write, iclass 12, count 0 2006.202.01:50:12.61#ibcon#wrote, iclass 12, count 0 2006.202.01:50:12.61#ibcon#about to read 3, iclass 12, count 0 2006.202.01:50:12.65#ibcon#read 3, iclass 12, count 0 2006.202.01:50:12.65#ibcon#about to read 4, iclass 12, count 0 2006.202.01:50:12.65#ibcon#read 4, iclass 12, count 0 2006.202.01:50:12.65#ibcon#about to read 5, iclass 12, count 0 2006.202.01:50:12.65#ibcon#read 5, iclass 12, count 0 2006.202.01:50:12.65#ibcon#about to read 6, iclass 12, count 0 2006.202.01:50:12.65#ibcon#read 6, iclass 12, count 0 2006.202.01:50:12.65#ibcon#end of sib2, iclass 12, count 0 2006.202.01:50:12.65#ibcon#*after write, iclass 12, count 0 2006.202.01:50:12.65#ibcon#*before return 0, iclass 12, count 0 2006.202.01:50:12.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:12.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.202.01:50:12.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.202.01:50:12.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.202.01:50:12.65$vck44/vb=4,5 2006.202.01:50:12.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.202.01:50:12.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.202.01:50:12.65#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:12.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:12.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:12.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:12.71#ibcon#enter wrdev, iclass 14, count 2 2006.202.01:50:12.71#ibcon#first serial, iclass 14, count 2 2006.202.01:50:12.71#ibcon#enter sib2, iclass 14, count 2 2006.202.01:50:12.71#ibcon#flushed, iclass 14, count 2 2006.202.01:50:12.71#ibcon#about to write, iclass 14, count 2 2006.202.01:50:12.71#ibcon#wrote, iclass 14, count 2 2006.202.01:50:12.71#ibcon#about to read 3, iclass 14, count 2 2006.202.01:50:12.73#ibcon#read 3, iclass 14, count 2 2006.202.01:50:12.73#ibcon#about to read 4, iclass 14, count 2 2006.202.01:50:12.73#ibcon#read 4, iclass 14, count 2 2006.202.01:50:12.73#ibcon#about to read 5, iclass 14, count 2 2006.202.01:50:12.73#ibcon#read 5, iclass 14, count 2 2006.202.01:50:12.73#ibcon#about to read 6, iclass 14, count 2 2006.202.01:50:12.73#ibcon#read 6, iclass 14, count 2 2006.202.01:50:12.73#ibcon#end of sib2, iclass 14, count 2 2006.202.01:50:12.73#ibcon#*mode == 0, iclass 14, count 2 2006.202.01:50:12.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.202.01:50:12.73#ibcon#[27=AT04-05\r\n] 2006.202.01:50:12.73#ibcon#*before write, iclass 14, count 2 2006.202.01:50:12.73#ibcon#enter sib2, iclass 14, count 2 2006.202.01:50:12.73#ibcon#flushed, iclass 14, count 2 2006.202.01:50:12.73#ibcon#about to write, iclass 14, count 2 2006.202.01:50:12.73#ibcon#wrote, iclass 14, count 2 2006.202.01:50:12.73#ibcon#about to read 3, iclass 14, count 2 2006.202.01:50:12.76#ibcon#read 3, iclass 14, count 2 2006.202.01:50:12.76#ibcon#about to read 4, iclass 14, count 2 2006.202.01:50:12.76#ibcon#read 4, iclass 14, count 2 2006.202.01:50:12.76#ibcon#about to read 5, iclass 14, count 2 2006.202.01:50:12.76#ibcon#read 5, iclass 14, count 2 2006.202.01:50:12.76#ibcon#about to read 6, iclass 14, count 2 2006.202.01:50:12.76#ibcon#read 6, iclass 14, count 2 2006.202.01:50:12.76#ibcon#end of sib2, iclass 14, count 2 2006.202.01:50:12.76#ibcon#*after write, iclass 14, count 2 2006.202.01:50:12.76#ibcon#*before return 0, iclass 14, count 2 2006.202.01:50:12.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:12.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.202.01:50:12.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.202.01:50:12.76#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:12.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:12.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:12.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:12.88#ibcon#enter wrdev, iclass 14, count 0 2006.202.01:50:12.88#ibcon#first serial, iclass 14, count 0 2006.202.01:50:12.88#ibcon#enter sib2, iclass 14, count 0 2006.202.01:50:12.88#ibcon#flushed, iclass 14, count 0 2006.202.01:50:12.88#ibcon#about to write, iclass 14, count 0 2006.202.01:50:12.88#ibcon#wrote, iclass 14, count 0 2006.202.01:50:12.88#ibcon#about to read 3, iclass 14, count 0 2006.202.01:50:12.90#ibcon#read 3, iclass 14, count 0 2006.202.01:50:12.90#ibcon#about to read 4, iclass 14, count 0 2006.202.01:50:12.90#ibcon#read 4, iclass 14, count 0 2006.202.01:50:12.90#ibcon#about to read 5, iclass 14, count 0 2006.202.01:50:12.90#ibcon#read 5, iclass 14, count 0 2006.202.01:50:12.90#ibcon#about to read 6, iclass 14, count 0 2006.202.01:50:12.90#ibcon#read 6, iclass 14, count 0 2006.202.01:50:12.90#ibcon#end of sib2, iclass 14, count 0 2006.202.01:50:12.90#ibcon#*mode == 0, iclass 14, count 0 2006.202.01:50:12.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.202.01:50:12.90#ibcon#[27=USB\r\n] 2006.202.01:50:12.90#ibcon#*before write, iclass 14, count 0 2006.202.01:50:12.90#ibcon#enter sib2, iclass 14, count 0 2006.202.01:50:12.90#ibcon#flushed, iclass 14, count 0 2006.202.01:50:12.90#ibcon#about to write, iclass 14, count 0 2006.202.01:50:12.90#ibcon#wrote, iclass 14, count 0 2006.202.01:50:12.90#ibcon#about to read 3, iclass 14, count 0 2006.202.01:50:12.93#ibcon#read 3, iclass 14, count 0 2006.202.01:50:12.93#ibcon#about to read 4, iclass 14, count 0 2006.202.01:50:12.93#ibcon#read 4, iclass 14, count 0 2006.202.01:50:12.93#ibcon#about to read 5, iclass 14, count 0 2006.202.01:50:12.93#ibcon#read 5, iclass 14, count 0 2006.202.01:50:12.93#ibcon#about to read 6, iclass 14, count 0 2006.202.01:50:12.93#ibcon#read 6, iclass 14, count 0 2006.202.01:50:12.93#ibcon#end of sib2, iclass 14, count 0 2006.202.01:50:12.93#ibcon#*after write, iclass 14, count 0 2006.202.01:50:12.93#ibcon#*before return 0, iclass 14, count 0 2006.202.01:50:12.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:12.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.202.01:50:12.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.202.01:50:12.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.202.01:50:12.93$vck44/vblo=5,709.99 2006.202.01:50:12.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.202.01:50:12.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.202.01:50:12.93#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:12.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:12.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:12.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:12.93#ibcon#enter wrdev, iclass 16, count 0 2006.202.01:50:12.93#ibcon#first serial, iclass 16, count 0 2006.202.01:50:12.93#ibcon#enter sib2, iclass 16, count 0 2006.202.01:50:12.93#ibcon#flushed, iclass 16, count 0 2006.202.01:50:12.93#ibcon#about to write, iclass 16, count 0 2006.202.01:50:12.93#ibcon#wrote, iclass 16, count 0 2006.202.01:50:12.93#ibcon#about to read 3, iclass 16, count 0 2006.202.01:50:12.95#ibcon#read 3, iclass 16, count 0 2006.202.01:50:12.95#ibcon#about to read 4, iclass 16, count 0 2006.202.01:50:12.95#ibcon#read 4, iclass 16, count 0 2006.202.01:50:12.95#ibcon#about to read 5, iclass 16, count 0 2006.202.01:50:12.95#ibcon#read 5, iclass 16, count 0 2006.202.01:50:12.95#ibcon#about to read 6, iclass 16, count 0 2006.202.01:50:12.95#ibcon#read 6, iclass 16, count 0 2006.202.01:50:12.95#ibcon#end of sib2, iclass 16, count 0 2006.202.01:50:12.95#ibcon#*mode == 0, iclass 16, count 0 2006.202.01:50:12.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.202.01:50:12.95#ibcon#[28=FRQ=05,709.99\r\n] 2006.202.01:50:12.95#ibcon#*before write, iclass 16, count 0 2006.202.01:50:12.95#ibcon#enter sib2, iclass 16, count 0 2006.202.01:50:12.95#ibcon#flushed, iclass 16, count 0 2006.202.01:50:12.95#ibcon#about to write, iclass 16, count 0 2006.202.01:50:12.95#ibcon#wrote, iclass 16, count 0 2006.202.01:50:12.95#ibcon#about to read 3, iclass 16, count 0 2006.202.01:50:12.99#ibcon#read 3, iclass 16, count 0 2006.202.01:50:12.99#ibcon#about to read 4, iclass 16, count 0 2006.202.01:50:12.99#ibcon#read 4, iclass 16, count 0 2006.202.01:50:12.99#ibcon#about to read 5, iclass 16, count 0 2006.202.01:50:12.99#ibcon#read 5, iclass 16, count 0 2006.202.01:50:12.99#ibcon#about to read 6, iclass 16, count 0 2006.202.01:50:12.99#ibcon#read 6, iclass 16, count 0 2006.202.01:50:12.99#ibcon#end of sib2, iclass 16, count 0 2006.202.01:50:12.99#ibcon#*after write, iclass 16, count 0 2006.202.01:50:12.99#ibcon#*before return 0, iclass 16, count 0 2006.202.01:50:12.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:12.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.202.01:50:12.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.202.01:50:12.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.202.01:50:12.99$vck44/vb=5,4 2006.202.01:50:12.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.202.01:50:12.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.202.01:50:12.99#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:12.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:13.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:13.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:13.05#ibcon#enter wrdev, iclass 18, count 2 2006.202.01:50:13.05#ibcon#first serial, iclass 18, count 2 2006.202.01:50:13.05#ibcon#enter sib2, iclass 18, count 2 2006.202.01:50:13.05#ibcon#flushed, iclass 18, count 2 2006.202.01:50:13.05#ibcon#about to write, iclass 18, count 2 2006.202.01:50:13.05#ibcon#wrote, iclass 18, count 2 2006.202.01:50:13.05#ibcon#about to read 3, iclass 18, count 2 2006.202.01:50:13.07#ibcon#read 3, iclass 18, count 2 2006.202.01:50:13.07#ibcon#about to read 4, iclass 18, count 2 2006.202.01:50:13.07#ibcon#read 4, iclass 18, count 2 2006.202.01:50:13.07#ibcon#about to read 5, iclass 18, count 2 2006.202.01:50:13.07#ibcon#read 5, iclass 18, count 2 2006.202.01:50:13.07#ibcon#about to read 6, iclass 18, count 2 2006.202.01:50:13.07#ibcon#read 6, iclass 18, count 2 2006.202.01:50:13.07#ibcon#end of sib2, iclass 18, count 2 2006.202.01:50:13.07#ibcon#*mode == 0, iclass 18, count 2 2006.202.01:50:13.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.202.01:50:13.07#ibcon#[27=AT05-04\r\n] 2006.202.01:50:13.07#ibcon#*before write, iclass 18, count 2 2006.202.01:50:13.07#ibcon#enter sib2, iclass 18, count 2 2006.202.01:50:13.07#ibcon#flushed, iclass 18, count 2 2006.202.01:50:13.07#ibcon#about to write, iclass 18, count 2 2006.202.01:50:13.07#ibcon#wrote, iclass 18, count 2 2006.202.01:50:13.07#ibcon#about to read 3, iclass 18, count 2 2006.202.01:50:13.10#ibcon#read 3, iclass 18, count 2 2006.202.01:50:13.10#ibcon#about to read 4, iclass 18, count 2 2006.202.01:50:13.10#ibcon#read 4, iclass 18, count 2 2006.202.01:50:13.10#ibcon#about to read 5, iclass 18, count 2 2006.202.01:50:13.10#ibcon#read 5, iclass 18, count 2 2006.202.01:50:13.10#ibcon#about to read 6, iclass 18, count 2 2006.202.01:50:13.10#ibcon#read 6, iclass 18, count 2 2006.202.01:50:13.10#ibcon#end of sib2, iclass 18, count 2 2006.202.01:50:13.10#ibcon#*after write, iclass 18, count 2 2006.202.01:50:13.10#ibcon#*before return 0, iclass 18, count 2 2006.202.01:50:13.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:13.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.202.01:50:13.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.202.01:50:13.10#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:13.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:13.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:13.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:13.22#ibcon#enter wrdev, iclass 18, count 0 2006.202.01:50:13.22#ibcon#first serial, iclass 18, count 0 2006.202.01:50:13.22#ibcon#enter sib2, iclass 18, count 0 2006.202.01:50:13.22#ibcon#flushed, iclass 18, count 0 2006.202.01:50:13.22#ibcon#about to write, iclass 18, count 0 2006.202.01:50:13.22#ibcon#wrote, iclass 18, count 0 2006.202.01:50:13.22#ibcon#about to read 3, iclass 18, count 0 2006.202.01:50:13.24#ibcon#read 3, iclass 18, count 0 2006.202.01:50:13.24#ibcon#about to read 4, iclass 18, count 0 2006.202.01:50:13.24#ibcon#read 4, iclass 18, count 0 2006.202.01:50:13.24#ibcon#about to read 5, iclass 18, count 0 2006.202.01:50:13.24#ibcon#read 5, iclass 18, count 0 2006.202.01:50:13.24#ibcon#about to read 6, iclass 18, count 0 2006.202.01:50:13.24#ibcon#read 6, iclass 18, count 0 2006.202.01:50:13.24#ibcon#end of sib2, iclass 18, count 0 2006.202.01:50:13.24#ibcon#*mode == 0, iclass 18, count 0 2006.202.01:50:13.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.202.01:50:13.24#ibcon#[27=USB\r\n] 2006.202.01:50:13.24#ibcon#*before write, iclass 18, count 0 2006.202.01:50:13.24#ibcon#enter sib2, iclass 18, count 0 2006.202.01:50:13.24#ibcon#flushed, iclass 18, count 0 2006.202.01:50:13.24#ibcon#about to write, iclass 18, count 0 2006.202.01:50:13.24#ibcon#wrote, iclass 18, count 0 2006.202.01:50:13.24#ibcon#about to read 3, iclass 18, count 0 2006.202.01:50:13.27#ibcon#read 3, iclass 18, count 0 2006.202.01:50:13.27#ibcon#about to read 4, iclass 18, count 0 2006.202.01:50:13.27#ibcon#read 4, iclass 18, count 0 2006.202.01:50:13.27#ibcon#about to read 5, iclass 18, count 0 2006.202.01:50:13.27#ibcon#read 5, iclass 18, count 0 2006.202.01:50:13.27#ibcon#about to read 6, iclass 18, count 0 2006.202.01:50:13.27#ibcon#read 6, iclass 18, count 0 2006.202.01:50:13.27#ibcon#end of sib2, iclass 18, count 0 2006.202.01:50:13.27#ibcon#*after write, iclass 18, count 0 2006.202.01:50:13.27#ibcon#*before return 0, iclass 18, count 0 2006.202.01:50:13.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:13.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.202.01:50:13.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.202.01:50:13.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.202.01:50:13.27$vck44/vblo=6,719.99 2006.202.01:50:13.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.202.01:50:13.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.202.01:50:13.27#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:13.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:13.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:13.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:13.27#ibcon#enter wrdev, iclass 20, count 0 2006.202.01:50:13.27#ibcon#first serial, iclass 20, count 0 2006.202.01:50:13.27#ibcon#enter sib2, iclass 20, count 0 2006.202.01:50:13.27#ibcon#flushed, iclass 20, count 0 2006.202.01:50:13.27#ibcon#about to write, iclass 20, count 0 2006.202.01:50:13.27#ibcon#wrote, iclass 20, count 0 2006.202.01:50:13.27#ibcon#about to read 3, iclass 20, count 0 2006.202.01:50:13.29#ibcon#read 3, iclass 20, count 0 2006.202.01:50:13.29#ibcon#about to read 4, iclass 20, count 0 2006.202.01:50:13.29#ibcon#read 4, iclass 20, count 0 2006.202.01:50:13.29#ibcon#about to read 5, iclass 20, count 0 2006.202.01:50:13.29#ibcon#read 5, iclass 20, count 0 2006.202.01:50:13.29#ibcon#about to read 6, iclass 20, count 0 2006.202.01:50:13.29#ibcon#read 6, iclass 20, count 0 2006.202.01:50:13.29#ibcon#end of sib2, iclass 20, count 0 2006.202.01:50:13.29#ibcon#*mode == 0, iclass 20, count 0 2006.202.01:50:13.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.202.01:50:13.29#ibcon#[28=FRQ=06,719.99\r\n] 2006.202.01:50:13.29#ibcon#*before write, iclass 20, count 0 2006.202.01:50:13.29#ibcon#enter sib2, iclass 20, count 0 2006.202.01:50:13.29#ibcon#flushed, iclass 20, count 0 2006.202.01:50:13.29#ibcon#about to write, iclass 20, count 0 2006.202.01:50:13.29#ibcon#wrote, iclass 20, count 0 2006.202.01:50:13.29#ibcon#about to read 3, iclass 20, count 0 2006.202.01:50:13.33#ibcon#read 3, iclass 20, count 0 2006.202.01:50:13.33#ibcon#about to read 4, iclass 20, count 0 2006.202.01:50:13.33#ibcon#read 4, iclass 20, count 0 2006.202.01:50:13.33#ibcon#about to read 5, iclass 20, count 0 2006.202.01:50:13.33#ibcon#read 5, iclass 20, count 0 2006.202.01:50:13.33#ibcon#about to read 6, iclass 20, count 0 2006.202.01:50:13.33#ibcon#read 6, iclass 20, count 0 2006.202.01:50:13.33#ibcon#end of sib2, iclass 20, count 0 2006.202.01:50:13.33#ibcon#*after write, iclass 20, count 0 2006.202.01:50:13.33#ibcon#*before return 0, iclass 20, count 0 2006.202.01:50:13.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:13.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.202.01:50:13.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.202.01:50:13.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.202.01:50:13.33$vck44/vb=6,4 2006.202.01:50:13.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.202.01:50:13.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.202.01:50:13.33#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:13.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:13.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:13.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:13.39#ibcon#enter wrdev, iclass 22, count 2 2006.202.01:50:13.39#ibcon#first serial, iclass 22, count 2 2006.202.01:50:13.39#ibcon#enter sib2, iclass 22, count 2 2006.202.01:50:13.39#ibcon#flushed, iclass 22, count 2 2006.202.01:50:13.39#ibcon#about to write, iclass 22, count 2 2006.202.01:50:13.39#ibcon#wrote, iclass 22, count 2 2006.202.01:50:13.39#ibcon#about to read 3, iclass 22, count 2 2006.202.01:50:13.41#ibcon#read 3, iclass 22, count 2 2006.202.01:50:13.41#ibcon#about to read 4, iclass 22, count 2 2006.202.01:50:13.41#ibcon#read 4, iclass 22, count 2 2006.202.01:50:13.41#ibcon#about to read 5, iclass 22, count 2 2006.202.01:50:13.41#ibcon#read 5, iclass 22, count 2 2006.202.01:50:13.41#ibcon#about to read 6, iclass 22, count 2 2006.202.01:50:13.41#ibcon#read 6, iclass 22, count 2 2006.202.01:50:13.41#ibcon#end of sib2, iclass 22, count 2 2006.202.01:50:13.41#ibcon#*mode == 0, iclass 22, count 2 2006.202.01:50:13.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.202.01:50:13.41#ibcon#[27=AT06-04\r\n] 2006.202.01:50:13.41#ibcon#*before write, iclass 22, count 2 2006.202.01:50:13.41#ibcon#enter sib2, iclass 22, count 2 2006.202.01:50:13.41#ibcon#flushed, iclass 22, count 2 2006.202.01:50:13.41#ibcon#about to write, iclass 22, count 2 2006.202.01:50:13.41#ibcon#wrote, iclass 22, count 2 2006.202.01:50:13.41#ibcon#about to read 3, iclass 22, count 2 2006.202.01:50:13.44#ibcon#read 3, iclass 22, count 2 2006.202.01:50:13.44#ibcon#about to read 4, iclass 22, count 2 2006.202.01:50:13.44#ibcon#read 4, iclass 22, count 2 2006.202.01:50:13.44#ibcon#about to read 5, iclass 22, count 2 2006.202.01:50:13.44#ibcon#read 5, iclass 22, count 2 2006.202.01:50:13.44#ibcon#about to read 6, iclass 22, count 2 2006.202.01:50:13.44#ibcon#read 6, iclass 22, count 2 2006.202.01:50:13.44#ibcon#end of sib2, iclass 22, count 2 2006.202.01:50:13.44#ibcon#*after write, iclass 22, count 2 2006.202.01:50:13.44#ibcon#*before return 0, iclass 22, count 2 2006.202.01:50:13.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:13.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.202.01:50:13.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.202.01:50:13.44#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:13.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:13.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:13.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:13.56#ibcon#enter wrdev, iclass 22, count 0 2006.202.01:50:13.56#ibcon#first serial, iclass 22, count 0 2006.202.01:50:13.56#ibcon#enter sib2, iclass 22, count 0 2006.202.01:50:13.56#ibcon#flushed, iclass 22, count 0 2006.202.01:50:13.56#ibcon#about to write, iclass 22, count 0 2006.202.01:50:13.56#ibcon#wrote, iclass 22, count 0 2006.202.01:50:13.56#ibcon#about to read 3, iclass 22, count 0 2006.202.01:50:13.58#ibcon#read 3, iclass 22, count 0 2006.202.01:50:13.58#ibcon#about to read 4, iclass 22, count 0 2006.202.01:50:13.58#ibcon#read 4, iclass 22, count 0 2006.202.01:50:13.58#ibcon#about to read 5, iclass 22, count 0 2006.202.01:50:13.58#ibcon#read 5, iclass 22, count 0 2006.202.01:50:13.58#ibcon#about to read 6, iclass 22, count 0 2006.202.01:50:13.58#ibcon#read 6, iclass 22, count 0 2006.202.01:50:13.58#ibcon#end of sib2, iclass 22, count 0 2006.202.01:50:13.58#ibcon#*mode == 0, iclass 22, count 0 2006.202.01:50:13.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.202.01:50:13.58#ibcon#[27=USB\r\n] 2006.202.01:50:13.58#ibcon#*before write, iclass 22, count 0 2006.202.01:50:13.58#ibcon#enter sib2, iclass 22, count 0 2006.202.01:50:13.58#ibcon#flushed, iclass 22, count 0 2006.202.01:50:13.58#ibcon#about to write, iclass 22, count 0 2006.202.01:50:13.58#ibcon#wrote, iclass 22, count 0 2006.202.01:50:13.58#ibcon#about to read 3, iclass 22, count 0 2006.202.01:50:13.61#ibcon#read 3, iclass 22, count 0 2006.202.01:50:13.61#ibcon#about to read 4, iclass 22, count 0 2006.202.01:50:13.61#ibcon#read 4, iclass 22, count 0 2006.202.01:50:13.61#ibcon#about to read 5, iclass 22, count 0 2006.202.01:50:13.61#ibcon#read 5, iclass 22, count 0 2006.202.01:50:13.61#ibcon#about to read 6, iclass 22, count 0 2006.202.01:50:13.61#ibcon#read 6, iclass 22, count 0 2006.202.01:50:13.61#ibcon#end of sib2, iclass 22, count 0 2006.202.01:50:13.61#ibcon#*after write, iclass 22, count 0 2006.202.01:50:13.61#ibcon#*before return 0, iclass 22, count 0 2006.202.01:50:13.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:13.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.202.01:50:13.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.202.01:50:13.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.202.01:50:13.61$vck44/vblo=7,734.99 2006.202.01:50:13.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.202.01:50:13.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.202.01:50:13.61#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:13.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:13.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:13.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:13.61#ibcon#enter wrdev, iclass 24, count 0 2006.202.01:50:13.61#ibcon#first serial, iclass 24, count 0 2006.202.01:50:13.61#ibcon#enter sib2, iclass 24, count 0 2006.202.01:50:13.61#ibcon#flushed, iclass 24, count 0 2006.202.01:50:13.61#ibcon#about to write, iclass 24, count 0 2006.202.01:50:13.61#ibcon#wrote, iclass 24, count 0 2006.202.01:50:13.61#ibcon#about to read 3, iclass 24, count 0 2006.202.01:50:13.63#ibcon#read 3, iclass 24, count 0 2006.202.01:50:13.63#ibcon#about to read 4, iclass 24, count 0 2006.202.01:50:13.63#ibcon#read 4, iclass 24, count 0 2006.202.01:50:13.63#ibcon#about to read 5, iclass 24, count 0 2006.202.01:50:13.63#ibcon#read 5, iclass 24, count 0 2006.202.01:50:13.63#ibcon#about to read 6, iclass 24, count 0 2006.202.01:50:13.63#ibcon#read 6, iclass 24, count 0 2006.202.01:50:13.63#ibcon#end of sib2, iclass 24, count 0 2006.202.01:50:13.63#ibcon#*mode == 0, iclass 24, count 0 2006.202.01:50:13.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.202.01:50:13.63#ibcon#[28=FRQ=07,734.99\r\n] 2006.202.01:50:13.63#ibcon#*before write, iclass 24, count 0 2006.202.01:50:13.63#ibcon#enter sib2, iclass 24, count 0 2006.202.01:50:13.63#ibcon#flushed, iclass 24, count 0 2006.202.01:50:13.63#ibcon#about to write, iclass 24, count 0 2006.202.01:50:13.63#ibcon#wrote, iclass 24, count 0 2006.202.01:50:13.63#ibcon#about to read 3, iclass 24, count 0 2006.202.01:50:13.66#abcon#<5=/04 1.8 3.5 20.601001000.8\r\n> 2006.202.01:50:13.67#ibcon#read 3, iclass 24, count 0 2006.202.01:50:13.67#ibcon#about to read 4, iclass 24, count 0 2006.202.01:50:13.67#ibcon#read 4, iclass 24, count 0 2006.202.01:50:13.67#ibcon#about to read 5, iclass 24, count 0 2006.202.01:50:13.67#ibcon#read 5, iclass 24, count 0 2006.202.01:50:13.67#ibcon#about to read 6, iclass 24, count 0 2006.202.01:50:13.67#ibcon#read 6, iclass 24, count 0 2006.202.01:50:13.67#ibcon#end of sib2, iclass 24, count 0 2006.202.01:50:13.67#ibcon#*after write, iclass 24, count 0 2006.202.01:50:13.67#ibcon#*before return 0, iclass 24, count 0 2006.202.01:50:13.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:13.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.202.01:50:13.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.202.01:50:13.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.202.01:50:13.67$vck44/vb=7,4 2006.202.01:50:13.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.202.01:50:13.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.202.01:50:13.67#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:13.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:50:13.68#abcon#{5=INTERFACE CLEAR} 2006.202.01:50:13.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:50:13.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:50:13.73#ibcon#enter wrdev, iclass 29, count 2 2006.202.01:50:13.73#ibcon#first serial, iclass 29, count 2 2006.202.01:50:13.73#ibcon#enter sib2, iclass 29, count 2 2006.202.01:50:13.73#ibcon#flushed, iclass 29, count 2 2006.202.01:50:13.73#ibcon#about to write, iclass 29, count 2 2006.202.01:50:13.73#ibcon#wrote, iclass 29, count 2 2006.202.01:50:13.73#ibcon#about to read 3, iclass 29, count 2 2006.202.01:50:13.74#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:50:13.75#ibcon#read 3, iclass 29, count 2 2006.202.01:50:13.75#ibcon#about to read 4, iclass 29, count 2 2006.202.01:50:13.75#ibcon#read 4, iclass 29, count 2 2006.202.01:50:13.75#ibcon#about to read 5, iclass 29, count 2 2006.202.01:50:13.75#ibcon#read 5, iclass 29, count 2 2006.202.01:50:13.75#ibcon#about to read 6, iclass 29, count 2 2006.202.01:50:13.75#ibcon#read 6, iclass 29, count 2 2006.202.01:50:13.75#ibcon#end of sib2, iclass 29, count 2 2006.202.01:50:13.75#ibcon#*mode == 0, iclass 29, count 2 2006.202.01:50:13.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.202.01:50:13.75#ibcon#[27=AT07-04\r\n] 2006.202.01:50:13.75#ibcon#*before write, iclass 29, count 2 2006.202.01:50:13.75#ibcon#enter sib2, iclass 29, count 2 2006.202.01:50:13.75#ibcon#flushed, iclass 29, count 2 2006.202.01:50:13.75#ibcon#about to write, iclass 29, count 2 2006.202.01:50:13.75#ibcon#wrote, iclass 29, count 2 2006.202.01:50:13.75#ibcon#about to read 3, iclass 29, count 2 2006.202.01:50:13.78#ibcon#read 3, iclass 29, count 2 2006.202.01:50:13.78#ibcon#about to read 4, iclass 29, count 2 2006.202.01:50:13.78#ibcon#read 4, iclass 29, count 2 2006.202.01:50:13.78#ibcon#about to read 5, iclass 29, count 2 2006.202.01:50:13.78#ibcon#read 5, iclass 29, count 2 2006.202.01:50:13.78#ibcon#about to read 6, iclass 29, count 2 2006.202.01:50:13.78#ibcon#read 6, iclass 29, count 2 2006.202.01:50:13.78#ibcon#end of sib2, iclass 29, count 2 2006.202.01:50:13.78#ibcon#*after write, iclass 29, count 2 2006.202.01:50:13.78#ibcon#*before return 0, iclass 29, count 2 2006.202.01:50:13.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:50:13.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.202.01:50:13.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.202.01:50:13.78#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:13.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:50:13.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:50:13.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:50:13.90#ibcon#enter wrdev, iclass 29, count 0 2006.202.01:50:13.90#ibcon#first serial, iclass 29, count 0 2006.202.01:50:13.90#ibcon#enter sib2, iclass 29, count 0 2006.202.01:50:13.90#ibcon#flushed, iclass 29, count 0 2006.202.01:50:13.90#ibcon#about to write, iclass 29, count 0 2006.202.01:50:13.90#ibcon#wrote, iclass 29, count 0 2006.202.01:50:13.90#ibcon#about to read 3, iclass 29, count 0 2006.202.01:50:13.92#ibcon#read 3, iclass 29, count 0 2006.202.01:50:13.92#ibcon#about to read 4, iclass 29, count 0 2006.202.01:50:13.92#ibcon#read 4, iclass 29, count 0 2006.202.01:50:13.92#ibcon#about to read 5, iclass 29, count 0 2006.202.01:50:13.92#ibcon#read 5, iclass 29, count 0 2006.202.01:50:13.92#ibcon#about to read 6, iclass 29, count 0 2006.202.01:50:13.92#ibcon#read 6, iclass 29, count 0 2006.202.01:50:13.92#ibcon#end of sib2, iclass 29, count 0 2006.202.01:50:13.92#ibcon#*mode == 0, iclass 29, count 0 2006.202.01:50:13.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.202.01:50:13.92#ibcon#[27=USB\r\n] 2006.202.01:50:13.92#ibcon#*before write, iclass 29, count 0 2006.202.01:50:13.92#ibcon#enter sib2, iclass 29, count 0 2006.202.01:50:13.92#ibcon#flushed, iclass 29, count 0 2006.202.01:50:13.92#ibcon#about to write, iclass 29, count 0 2006.202.01:50:13.92#ibcon#wrote, iclass 29, count 0 2006.202.01:50:13.92#ibcon#about to read 3, iclass 29, count 0 2006.202.01:50:13.95#ibcon#read 3, iclass 29, count 0 2006.202.01:50:13.95#ibcon#about to read 4, iclass 29, count 0 2006.202.01:50:13.95#ibcon#read 4, iclass 29, count 0 2006.202.01:50:13.95#ibcon#about to read 5, iclass 29, count 0 2006.202.01:50:13.95#ibcon#read 5, iclass 29, count 0 2006.202.01:50:13.95#ibcon#about to read 6, iclass 29, count 0 2006.202.01:50:13.95#ibcon#read 6, iclass 29, count 0 2006.202.01:50:13.95#ibcon#end of sib2, iclass 29, count 0 2006.202.01:50:13.95#ibcon#*after write, iclass 29, count 0 2006.202.01:50:13.95#ibcon#*before return 0, iclass 29, count 0 2006.202.01:50:13.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:50:13.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.202.01:50:13.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.202.01:50:13.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.202.01:50:13.95$vck44/vblo=8,744.99 2006.202.01:50:13.95#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.202.01:50:13.95#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.202.01:50:13.95#ibcon#ireg 17 cls_cnt 0 2006.202.01:50:13.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:13.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:13.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:13.95#ibcon#enter wrdev, iclass 32, count 0 2006.202.01:50:13.95#ibcon#first serial, iclass 32, count 0 2006.202.01:50:13.95#ibcon#enter sib2, iclass 32, count 0 2006.202.01:50:13.95#ibcon#flushed, iclass 32, count 0 2006.202.01:50:13.95#ibcon#about to write, iclass 32, count 0 2006.202.01:50:13.95#ibcon#wrote, iclass 32, count 0 2006.202.01:50:13.95#ibcon#about to read 3, iclass 32, count 0 2006.202.01:50:13.97#ibcon#read 3, iclass 32, count 0 2006.202.01:50:13.97#ibcon#about to read 4, iclass 32, count 0 2006.202.01:50:13.97#ibcon#read 4, iclass 32, count 0 2006.202.01:50:13.97#ibcon#about to read 5, iclass 32, count 0 2006.202.01:50:13.97#ibcon#read 5, iclass 32, count 0 2006.202.01:50:13.97#ibcon#about to read 6, iclass 32, count 0 2006.202.01:50:13.97#ibcon#read 6, iclass 32, count 0 2006.202.01:50:13.97#ibcon#end of sib2, iclass 32, count 0 2006.202.01:50:13.97#ibcon#*mode == 0, iclass 32, count 0 2006.202.01:50:13.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.202.01:50:13.97#ibcon#[28=FRQ=08,744.99\r\n] 2006.202.01:50:13.97#ibcon#*before write, iclass 32, count 0 2006.202.01:50:13.97#ibcon#enter sib2, iclass 32, count 0 2006.202.01:50:13.97#ibcon#flushed, iclass 32, count 0 2006.202.01:50:13.97#ibcon#about to write, iclass 32, count 0 2006.202.01:50:13.97#ibcon#wrote, iclass 32, count 0 2006.202.01:50:13.97#ibcon#about to read 3, iclass 32, count 0 2006.202.01:50:14.01#ibcon#read 3, iclass 32, count 0 2006.202.01:50:14.01#ibcon#about to read 4, iclass 32, count 0 2006.202.01:50:14.01#ibcon#read 4, iclass 32, count 0 2006.202.01:50:14.01#ibcon#about to read 5, iclass 32, count 0 2006.202.01:50:14.01#ibcon#read 5, iclass 32, count 0 2006.202.01:50:14.01#ibcon#about to read 6, iclass 32, count 0 2006.202.01:50:14.01#ibcon#read 6, iclass 32, count 0 2006.202.01:50:14.01#ibcon#end of sib2, iclass 32, count 0 2006.202.01:50:14.01#ibcon#*after write, iclass 32, count 0 2006.202.01:50:14.01#ibcon#*before return 0, iclass 32, count 0 2006.202.01:50:14.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:14.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.202.01:50:14.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.202.01:50:14.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.202.01:50:14.01$vck44/vb=8,4 2006.202.01:50:14.01#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.202.01:50:14.01#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.202.01:50:14.01#ibcon#ireg 11 cls_cnt 2 2006.202.01:50:14.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:14.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:14.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:14.07#ibcon#enter wrdev, iclass 34, count 2 2006.202.01:50:14.07#ibcon#first serial, iclass 34, count 2 2006.202.01:50:14.07#ibcon#enter sib2, iclass 34, count 2 2006.202.01:50:14.07#ibcon#flushed, iclass 34, count 2 2006.202.01:50:14.07#ibcon#about to write, iclass 34, count 2 2006.202.01:50:14.07#ibcon#wrote, iclass 34, count 2 2006.202.01:50:14.07#ibcon#about to read 3, iclass 34, count 2 2006.202.01:50:14.10#ibcon#read 3, iclass 34, count 2 2006.202.01:50:14.10#ibcon#about to read 4, iclass 34, count 2 2006.202.01:50:14.10#ibcon#read 4, iclass 34, count 2 2006.202.01:50:14.10#ibcon#about to read 5, iclass 34, count 2 2006.202.01:50:14.10#ibcon#read 5, iclass 34, count 2 2006.202.01:50:14.10#ibcon#about to read 6, iclass 34, count 2 2006.202.01:50:14.10#ibcon#read 6, iclass 34, count 2 2006.202.01:50:14.10#ibcon#end of sib2, iclass 34, count 2 2006.202.01:50:14.10#ibcon#*mode == 0, iclass 34, count 2 2006.202.01:50:14.10#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.202.01:50:14.10#ibcon#[27=AT08-04\r\n] 2006.202.01:50:14.10#ibcon#*before write, iclass 34, count 2 2006.202.01:50:14.10#ibcon#enter sib2, iclass 34, count 2 2006.202.01:50:14.10#ibcon#flushed, iclass 34, count 2 2006.202.01:50:14.10#ibcon#about to write, iclass 34, count 2 2006.202.01:50:14.10#ibcon#wrote, iclass 34, count 2 2006.202.01:50:14.10#ibcon#about to read 3, iclass 34, count 2 2006.202.01:50:14.14#ibcon#read 3, iclass 34, count 2 2006.202.01:50:14.14#ibcon#about to read 4, iclass 34, count 2 2006.202.01:50:14.14#ibcon#read 4, iclass 34, count 2 2006.202.01:50:14.14#ibcon#about to read 5, iclass 34, count 2 2006.202.01:50:14.14#ibcon#read 5, iclass 34, count 2 2006.202.01:50:14.14#ibcon#about to read 6, iclass 34, count 2 2006.202.01:50:14.14#ibcon#read 6, iclass 34, count 2 2006.202.01:50:14.14#ibcon#end of sib2, iclass 34, count 2 2006.202.01:50:14.14#ibcon#*after write, iclass 34, count 2 2006.202.01:50:14.14#ibcon#*before return 0, iclass 34, count 2 2006.202.01:50:14.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:14.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.202.01:50:14.14#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.202.01:50:14.14#ibcon#ireg 7 cls_cnt 0 2006.202.01:50:14.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:14.26#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:14.26#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:14.26#ibcon#enter wrdev, iclass 34, count 0 2006.202.01:50:14.26#ibcon#first serial, iclass 34, count 0 2006.202.01:50:14.26#ibcon#enter sib2, iclass 34, count 0 2006.202.01:50:14.26#ibcon#flushed, iclass 34, count 0 2006.202.01:50:14.26#ibcon#about to write, iclass 34, count 0 2006.202.01:50:14.26#ibcon#wrote, iclass 34, count 0 2006.202.01:50:14.26#ibcon#about to read 3, iclass 34, count 0 2006.202.01:50:14.28#ibcon#read 3, iclass 34, count 0 2006.202.01:50:14.28#ibcon#about to read 4, iclass 34, count 0 2006.202.01:50:14.28#ibcon#read 4, iclass 34, count 0 2006.202.01:50:14.28#ibcon#about to read 5, iclass 34, count 0 2006.202.01:50:14.28#ibcon#read 5, iclass 34, count 0 2006.202.01:50:14.28#ibcon#about to read 6, iclass 34, count 0 2006.202.01:50:14.28#ibcon#read 6, iclass 34, count 0 2006.202.01:50:14.28#ibcon#end of sib2, iclass 34, count 0 2006.202.01:50:14.28#ibcon#*mode == 0, iclass 34, count 0 2006.202.01:50:14.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.202.01:50:14.28#ibcon#[27=USB\r\n] 2006.202.01:50:14.28#ibcon#*before write, iclass 34, count 0 2006.202.01:50:14.28#ibcon#enter sib2, iclass 34, count 0 2006.202.01:50:14.28#ibcon#flushed, iclass 34, count 0 2006.202.01:50:14.28#ibcon#about to write, iclass 34, count 0 2006.202.01:50:14.28#ibcon#wrote, iclass 34, count 0 2006.202.01:50:14.28#ibcon#about to read 3, iclass 34, count 0 2006.202.01:50:14.31#ibcon#read 3, iclass 34, count 0 2006.202.01:50:14.31#ibcon#about to read 4, iclass 34, count 0 2006.202.01:50:14.31#ibcon#read 4, iclass 34, count 0 2006.202.01:50:14.31#ibcon#about to read 5, iclass 34, count 0 2006.202.01:50:14.31#ibcon#read 5, iclass 34, count 0 2006.202.01:50:14.31#ibcon#about to read 6, iclass 34, count 0 2006.202.01:50:14.31#ibcon#read 6, iclass 34, count 0 2006.202.01:50:14.31#ibcon#end of sib2, iclass 34, count 0 2006.202.01:50:14.31#ibcon#*after write, iclass 34, count 0 2006.202.01:50:14.31#ibcon#*before return 0, iclass 34, count 0 2006.202.01:50:14.31#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:14.31#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.202.01:50:14.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.202.01:50:14.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.202.01:50:14.31$vck44/vabw=wide 2006.202.01:50:14.31#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.202.01:50:14.31#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.202.01:50:14.31#ibcon#ireg 8 cls_cnt 0 2006.202.01:50:14.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:14.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:14.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:14.31#ibcon#enter wrdev, iclass 36, count 0 2006.202.01:50:14.31#ibcon#first serial, iclass 36, count 0 2006.202.01:50:14.31#ibcon#enter sib2, iclass 36, count 0 2006.202.01:50:14.31#ibcon#flushed, iclass 36, count 0 2006.202.01:50:14.31#ibcon#about to write, iclass 36, count 0 2006.202.01:50:14.31#ibcon#wrote, iclass 36, count 0 2006.202.01:50:14.31#ibcon#about to read 3, iclass 36, count 0 2006.202.01:50:14.33#ibcon#read 3, iclass 36, count 0 2006.202.01:50:14.33#ibcon#about to read 4, iclass 36, count 0 2006.202.01:50:14.33#ibcon#read 4, iclass 36, count 0 2006.202.01:50:14.33#ibcon#about to read 5, iclass 36, count 0 2006.202.01:50:14.33#ibcon#read 5, iclass 36, count 0 2006.202.01:50:14.33#ibcon#about to read 6, iclass 36, count 0 2006.202.01:50:14.33#ibcon#read 6, iclass 36, count 0 2006.202.01:50:14.33#ibcon#end of sib2, iclass 36, count 0 2006.202.01:50:14.33#ibcon#*mode == 0, iclass 36, count 0 2006.202.01:50:14.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.202.01:50:14.33#ibcon#[25=BW32\r\n] 2006.202.01:50:14.33#ibcon#*before write, iclass 36, count 0 2006.202.01:50:14.33#ibcon#enter sib2, iclass 36, count 0 2006.202.01:50:14.33#ibcon#flushed, iclass 36, count 0 2006.202.01:50:14.33#ibcon#about to write, iclass 36, count 0 2006.202.01:50:14.33#ibcon#wrote, iclass 36, count 0 2006.202.01:50:14.33#ibcon#about to read 3, iclass 36, count 0 2006.202.01:50:14.36#ibcon#read 3, iclass 36, count 0 2006.202.01:50:14.36#ibcon#about to read 4, iclass 36, count 0 2006.202.01:50:14.36#ibcon#read 4, iclass 36, count 0 2006.202.01:50:14.36#ibcon#about to read 5, iclass 36, count 0 2006.202.01:50:14.36#ibcon#read 5, iclass 36, count 0 2006.202.01:50:14.36#ibcon#about to read 6, iclass 36, count 0 2006.202.01:50:14.36#ibcon#read 6, iclass 36, count 0 2006.202.01:50:14.36#ibcon#end of sib2, iclass 36, count 0 2006.202.01:50:14.36#ibcon#*after write, iclass 36, count 0 2006.202.01:50:14.36#ibcon#*before return 0, iclass 36, count 0 2006.202.01:50:14.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:14.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.202.01:50:14.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.202.01:50:14.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.202.01:50:14.36$vck44/vbbw=wide 2006.202.01:50:14.36#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.202.01:50:14.36#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.202.01:50:14.36#ibcon#ireg 8 cls_cnt 0 2006.202.01:50:14.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:50:14.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:50:14.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:50:14.43#ibcon#enter wrdev, iclass 38, count 0 2006.202.01:50:14.43#ibcon#first serial, iclass 38, count 0 2006.202.01:50:14.43#ibcon#enter sib2, iclass 38, count 0 2006.202.01:50:14.43#ibcon#flushed, iclass 38, count 0 2006.202.01:50:14.43#ibcon#about to write, iclass 38, count 0 2006.202.01:50:14.43#ibcon#wrote, iclass 38, count 0 2006.202.01:50:14.43#ibcon#about to read 3, iclass 38, count 0 2006.202.01:50:14.45#ibcon#read 3, iclass 38, count 0 2006.202.01:50:14.45#ibcon#about to read 4, iclass 38, count 0 2006.202.01:50:14.45#ibcon#read 4, iclass 38, count 0 2006.202.01:50:14.45#ibcon#about to read 5, iclass 38, count 0 2006.202.01:50:14.45#ibcon#read 5, iclass 38, count 0 2006.202.01:50:14.45#ibcon#about to read 6, iclass 38, count 0 2006.202.01:50:14.45#ibcon#read 6, iclass 38, count 0 2006.202.01:50:14.45#ibcon#end of sib2, iclass 38, count 0 2006.202.01:50:14.45#ibcon#*mode == 0, iclass 38, count 0 2006.202.01:50:14.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.202.01:50:14.45#ibcon#[27=BW32\r\n] 2006.202.01:50:14.45#ibcon#*before write, iclass 38, count 0 2006.202.01:50:14.45#ibcon#enter sib2, iclass 38, count 0 2006.202.01:50:14.45#ibcon#flushed, iclass 38, count 0 2006.202.01:50:14.45#ibcon#about to write, iclass 38, count 0 2006.202.01:50:14.45#ibcon#wrote, iclass 38, count 0 2006.202.01:50:14.45#ibcon#about to read 3, iclass 38, count 0 2006.202.01:50:14.48#ibcon#read 3, iclass 38, count 0 2006.202.01:50:14.48#ibcon#about to read 4, iclass 38, count 0 2006.202.01:50:14.48#ibcon#read 4, iclass 38, count 0 2006.202.01:50:14.48#ibcon#about to read 5, iclass 38, count 0 2006.202.01:50:14.48#ibcon#read 5, iclass 38, count 0 2006.202.01:50:14.48#ibcon#about to read 6, iclass 38, count 0 2006.202.01:50:14.48#ibcon#read 6, iclass 38, count 0 2006.202.01:50:14.48#ibcon#end of sib2, iclass 38, count 0 2006.202.01:50:14.48#ibcon#*after write, iclass 38, count 0 2006.202.01:50:14.48#ibcon#*before return 0, iclass 38, count 0 2006.202.01:50:14.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:50:14.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.202.01:50:14.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.202.01:50:14.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.202.01:50:14.48$setupk4/ifdk4 2006.202.01:50:14.48$ifdk4/lo= 2006.202.01:50:14.48$ifdk4/lo=lo1,7680.00,usb,rcp,1 2006.202.01:50:14.48$ifdk4/lo=lo2,1600.00,usb,rcp,1 2006.202.01:50:14.48$ifdk4/patch= 2006.202.01:50:14.48$ifdk4/patch=lo1,a1,a2,a3,a4,a5,a6,a7,a8 2006.202.01:50:14.48$ifdk4/patch=lo2,b1,b2,b3,b4,b5,b6,b7,b8 2006.202.01:50:14.48$setupk4/!*+20s 2006.202.01:50:23.83#abcon#<5=/04 1.8 3.4 20.611001000.8\r\n> 2006.202.01:50:23.85#abcon#{5=INTERFACE CLEAR} 2006.202.01:50:23.91#abcon#[5=S1D000X0/0*\r\n] 2006.202.01:50:28.92$setupk4/"tpicd 2006.202.01:50:28.92$setupk4/echo=off 2006.202.01:50:28.92$setupk4/xlog=off 2006.202.01:50:28.92:!2006.202.01:53:59 2006.202.01:50:52.14#trakl#Source acquired 2006.202.01:50:54.14#flagr#flagr/antenna,acquired 2006.202.01:53:59.00:preob 2006.202.01:53:59.14/onsource/TRACKING 2006.202.01:53:59.14:!2006.202.01:54:09 2006.202.01:54:09.00:"tape 2006.202.01:54:09.00:"st=record 2006.202.01:54:09.00:data_valid=on 2006.202.01:54:09.00:midob 2006.202.01:54:09.14/onsource/TRACKING 2006.202.01:54:09.14/wx/20.57,1000.9,100 2006.202.01:54:09.19/cable/+6.4848E-03 2006.202.01:54:10.28/va/01,08,usb,yes,49,52 2006.202.01:54:10.28/va/02,07,usb,yes,53,54 2006.202.01:54:10.28/va/03,08,usb,yes,48,50 2006.202.01:54:10.28/va/04,07,usb,yes,54,57 2006.202.01:54:10.28/va/05,04,usb,yes,49,50 2006.202.01:54:10.28/va/06,05,usb,yes,49,49 2006.202.01:54:10.28/va/07,05,usb,yes,48,49 2006.202.01:54:10.28/va/08,04,usb,yes,47,56 2006.202.01:54:10.51/valo/01,524.99,yes,locked 2006.202.01:54:10.51/valo/02,534.99,yes,locked 2006.202.01:54:10.51/valo/03,564.99,yes,locked 2006.202.01:54:10.51/valo/04,624.99,yes,locked 2006.202.01:54:10.51/valo/05,734.99,yes,locked 2006.202.01:54:10.51/valo/06,814.99,yes,locked 2006.202.01:54:10.51/valo/07,864.99,yes,locked 2006.202.01:54:10.51/valo/08,884.99,yes,locked 2006.202.01:54:11.60/vb/01,04,usb,yes,34,31 2006.202.01:54:11.60/vb/02,05,usb,yes,32,32 2006.202.01:54:11.60/vb/03,04,usb,yes,33,37 2006.202.01:54:11.60/vb/04,05,usb,yes,34,32 2006.202.01:54:11.60/vb/05,04,usb,yes,32,33 2006.202.01:54:11.60/vb/06,04,usb,yes,35,33 2006.202.01:54:11.60/vb/07,04,usb,yes,35,35 2006.202.01:54:11.60/vb/08,04,usb,yes,32,36 2006.202.01:54:11.83/vblo/01,629.99,yes,locked 2006.202.01:54:11.83/vblo/02,634.99,yes,locked 2006.202.01:54:11.83/vblo/03,649.99,yes,locked 2006.202.01:54:11.83/vblo/04,679.99,yes,locked 2006.202.01:54:11.83/vblo/05,709.99,yes,locked 2006.202.01:54:11.83/vblo/06,719.99,yes,locked 2006.202.01:54:11.83/vblo/07,734.99,yes,locked 2006.202.01:54:11.83/vblo/08,744.99,yes,locked 2006.202.01:54:11.98/vabw/8 2006.202.01:54:12.13/vbbw/8 2006.202.01:54:12.22/xfe/off,on,16.0 2006.202.01:54:12.61/ifatt/23,28,28,28 2006.202.01:54:13.07/fmout-gps/S +4.49E-07 2006.202.01:54:13.11:!2006.202.01:54:49 2006.202.01:54:49.00:data_valid=off 2006.202.01:54:49.00:"et 2006.202.01:54:49.00:!+3s 2006.202.01:54:52.02:"tape 2006.202.01:54:52.02:postob 2006.202.01:54:52.14/cable/+6.4846E-03 2006.202.01:54:52.14/wx/20.56,1000.8,100 2006.202.01:54:52.22/fmout-gps/S +4.48E-07 2006.202.01:54:52.23:"unlod=1 2006.202.01:54:52.23:sched_end 2006.202.01:54:52.23&sched_end/stopcheck 2006.202.01:54:52.24&stopcheck/sy=killall check_fsrun.pl 2006.202.01:54:52.24&stopcheck/" sy=killall chmem.sh 2006.202.01:54:52.31:checkk5last 2006.202.01:54:52.31&checkk5last/chk_obsdata=1 2006.202.01:54:52.32&checkk5last/chk_obsdata=2 2006.202.01:54:52.32&checkk5last/chk_obsdata=3 2006.202.01:54:52.33&checkk5last/chk_obsdata=4 2006.202.01:54:52.33&checkk5last/k5log=1 2006.202.01:54:52.33&checkk5last/k5log=2 2006.202.01:54:52.34&checkk5last/k5log=3 2006.202.01:54:52.34&checkk5last/k5log=4 2006.202.01:54:52.34&checkk5last/obsinfo 2006.202.01:54:52.83/chk_obsdata//k5ts1/T2020154??a.dat file size is correct (nominal:160MB, actual:156MB). 2006.202.01:54:53.31/chk_obsdata//k5ts2/T2020154??b.dat file size is correct (nominal:160MB, actual:156MB). 2006.202.01:54:53.72/chk_obsdata//k5ts3/T2020154??c.dat file size is correct (nominal:160MB, actual:156MB). 2006.202.01:54:54.15/chk_obsdata//k5ts4/T2020154??d.dat file size is correct (nominal:160MB, actual:156MB). 2006.202.01:54:54.98/k5log//k5ts1_log_newline 2006.202.01:54:55.80/k5log//k5ts2_log_newline 2006.202.01:54:56.60/k5log//k5ts3_log_newline 2006.202.01:54:57.38/k5log//k5ts4_log_newline 2006.202.01:54:57.41/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.202.01:54:57.41:checkk5hdd 2006.202.01:54:57.41&checkk5hdd/chk_hdd=1 2006.202.01:54:57.41&checkk5hdd/chk_hdd=2 2006.202.01:54:57.41&checkk5hdd/chk_hdd=3 2006.202.01:54:57.41&checkk5hdd/chk_hdd=4 2006.202.01:55:01.22/chk_hdd//k5ts1/GSI00275:T201020000a.dat~T202015409a.dat[144744316928Byte] 2006.202.01:55:04.56/chk_hdd//k5ts2/GSI00290:T201020000b.dat~T202015409b.dat[144744316928Byte] 2006.202.01:55:08.05/chk_hdd//k5ts3/GSI00278:T201020000c.dat~T202015409c.dat[144744316928Byte] 2006.202.01:55:12.11/chk_hdd//k5ts4/GSI00220:T201020000d.dat~T202015409d.dat[144744316928Byte] 2006.202.01:55:12.11:sy=cp /usr2/log/jd0607ts.log /usr2/log_backup/ 2006.202.01:55:12.33:*end of schedule 2006.202.01:56:42.35;cable 2006.202.01:56:42.53/cable/+6.4852E-03 2006.202.01:57:53.68;cablelong 2006.202.01:57:53.85/cablelong/+7.0417E-03 2006.202.01:57:56.16;cablediff 2006.202.01:57:56.21/cablediff/556.5e-6,+ 2006.202.01:58:39.33;cable 2006.202.01:58:39.50/cable/+6.4860E-03 2006.202.01:59:55.19;wx 2006.202.01:59:55.19/wx/20.55,1001.0,100 2006.202.02:00:03.12;"Sky is rainy. 2006.202.02:00:06.95;xfe 2006.202.02:00:07.05/xfe/off,on,14.7 2006.202.02:00:10.59;clockoff 2006.202.02:00:11.07/fmout-gps/S +4.46E-07 2006.202.02:01:34.48;proc=point 2006.202.02:01:36.35;initp 2006.202.02:01:36.35&initp/"setup 2006.202.02:01:36.36&initp/abib=p2,pr 2006.202.02:01:36.36&initp/abib=p1,pr 2006.202.02:01:36.36&initp/!+1s 2006.202.02:01:36.37&initp/abib=p2,ln 2006.202.02:01:36.37&initp/abib=p2,rm3en 2006.202.02:01:36.37&initp/abib=p2,fm2en 2006.202.02:01:36.38&initp/abib=p2,ap 2006.202.02:01:36.38&initp/abib=p2 2006.202.02:01:36.38&initp/abib=p1,ln 2006.202.02:01:36.39&initp/abib=p1,rm3en 2006.202.02:01:36.39&initp/abib=p1,fm2en 2006.202.02:01:36.39&initp/"meter 1 (u6) has s band 2006.202.02:01:36.39&initp/abib=p1,ap 2006.202.02:01:36.39&initp/abib=p1 2006.202.02:01:36.39&initp/caloff 2006.202.02:01:36.39&initp/user_device=u5,7680,usb,rcp,750 2006.202.02:01:36.39&initp/user_device=u6,1600,usb,rcp,750 2006.202.02:01:36.39&initp/sigon 2006.202.02:01:36.39&initp/"sample fivept set-up for azel antenna with mark iii/iv rack 2006.202.02:01:36.39&initp/"fivept=azel,-2,9,.4,1,i1,120 2006.202.02:01:36.39&initp/"sample fivept set-up for xyns antenna with vlba/4 rack 2006.202.02:01:36.39&initp/"fivept=xyns,-2,9,.4,1,ia,120 2006.202.02:01:36.39&initp/" for tsukuba 2006.202.02:01:36.39&initp/"fivept=azel,-2,9,.4,1,u5,120 2006.202.02:01:36.39&initp/fivept=azel,-2,7,.3,1,u5,120 2006.202.02:01:36.39&initp/" sample onoff set-up for mark iii/iv 2006.202.02:01:36.39&initp/"onoff=2,1,75,3,120,all 2006.202.02:01:36.39&initp/" sample onoff set-up for vlba/4 2006.202.02:01:36.39&initp/"onoff=2,1,75,3,120,allu,ia,ib,ic 2006.202.02:01:36.39&initp/" for tsukuba 2006.202.02:01:36.39&initp/"onoff=2,1,75,3,120,u5,u6 2006.202.02:01:36.39&initp/" changed wait time into 60 sec (04-jun-2004 -sk-) 2006.202.02:01:36.39&initp/onoff=2,1,75,3,60,u5,u6 2006.202.02:01:36.39&initp/check= 2006.202.02:01:36.39&initp/sy=go aquir & 2006.202.02:01:38.41/abib/+0.1350E-03 2006.202.02:01:39.31/abib/+0.0580E-03 2006.202.02:01:39.31&caloff/"rx=*,*,*,*,*,*,off 2006.202.02:01:39.31&sigon/ifatt=23,28,28,28 2006.202.02:01:39.31&sigon/!+2s 2006.202.02:02:12.17;taurusa 2006.202.02:02:12.22&taurusa/source=taurusa,053432.,+220058,2000. 2006.202.02:02:13.14#flagr#flagr/antenna,new-source 2006.202.02:02:42.14#trakl#Source acquired 2006.202.02:02:42.14#flagr#flagr/antenna,acquired 2006.202.02:02:46.75;onoff 2006.202.02:02:46.76?ERROR q1 -307 WARNING: Source structure correction greater than 20% for detector u5. 2006.202.02:02:46.76#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.202.02:02:46.76#onoff#APR u5 8430.00 -100. 357.5 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.202.02:02:46.76#onoff#APR u6 2350.00 -100. 773.7 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.202.02:02:47.14#onoff#ORIG 7367.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.202.02:02:48.37#onoff#ONSO 1.2 0.00000 0.00000 u5 145 u6 123 2006.202.02:02:59.42#onoff#OFFS 12.3 1.96060 0.00000 u5 85 u6 43 2006.202.02:02:59.42;sigoffnf 2006.202.02:02:59.42&sigoffnf/sigoff 2006.202.02:02:59.43&sigoffnf/sy=go onoff & 2006.202.02:02:59.43&sigoff/ifatt=81,81,81,81 2006.202.02:02:59.43&sigoff/!+2s 2006.202.02:03:02.81;sigonnf 2006.202.02:03:02.81&sigonnf/sigon 2006.202.02:03:02.81&sigonnf/sy=go onoff & 2006.202.02:03:05.00#onoff#ZERO 15.7 1.96060 0.00000 u5 0 u6 0 2006.202.02:03:15.37#onoff#ONSO 28.2 0.00000 0.00000 u5 146 u6 124 2006.202.02:03:26.42#onoff#OFFS 39.3 -1.96060 -0.00000 u5 87 u6 43 2006.202.02:03:38.37#onoff#ONSO 51.2 0.00000 0.00000 u5 148 u6 126 2006.202.02:03:38.37#onoff#SIG u5 0.00 0.00 22.4 0.000 0.000 0.00 2006.202.02:03:38.37#onoff#SIG u6 0.00 0.00 6.3 0.000 0.000 0.00 2006.202.02:03:38.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.202.02:03:38.37#onoff#VAL taurusa 244.9 63.6 u5 5 r 8430.00 1.0000 -100. 509.6 0.000 0.0000 2006.202.02:03:38.37?ERROR nf -7 WARNING: Source structure correction greater than 20% for detector u5. 2006.202.02:03:38.37#onoff#VAL taurusa 244.9 63.6 u6 6 r 2350.00 1.0000 -100. 409.0 0.000 0.0000 2006.202.02:03:38.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.202.02:04:23.59;oriona 2006.202.02:04:23.59&oriona/source=oriona,053516.,-052322.,2000. 2006.202.02:04:24.13#flagr#flagr/antenna,new-source 2006.202.02:04:44.13#trakl#Source acquired 2006.202.02:04:44.13#flagr#flagr/antenna,acquired 2006.202.02:04:53.58;onoff 2006.202.02:04:53.58?ERROR q1 -307 WARNING: Source structure correction greater than 20% for detector u5. 2006.202.02:04:53.58#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.202.02:04:53.58#onoff#APR u5 8430.00 -100. 195.8 0.167000 1.00000 0.167000 7680.00 p 0.07768 2006.202.02:04:53.58#onoff#APR u6 2350.00 -100. 416.2 0.209000 1.00000 0.209000 1600.00 p 0.27867 2006.202.02:04:54.13#onoff#ORIG 7494.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.202.02:04:55.36#onoff#ONSO 1.2 0.00000 0.00000 u5 130 u6 90 2006.202.02:05:11.41#onoff#OFFS 17.3 1.15363 0.00000 u5 99 u6 44 2006.202.02:05:11.41;sigoffnf 2006.202.02:05:14.83;sigonnf 2006.202.02:05:17.00#onoff#ZERO 20.7 1.15363 0.00000 u5 0 u6 0 2006.202.02:05:34.36#onoff#ONSO 40.2 0.00000 0.00000 u5 137 u6 89 2006.202.02:05:51.41#onoff#OFFS 57.3 -1.15363 -0.00000 u5 103 u6 46 2006.202.02:06:08.41#onoff#ONSO 74.3 0.00000 0.00000 u5 139 u6 88 2006.202.02:06:08.41#onoff#SIG u5 0.00 0.00 84.8 0.000 0.000 0.00 2006.202.02:06:08.41#onoff#SIG u6 0.00 0.00 28.1 0.000 0.000 0.00 2006.202.02:06:08.41#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.202.02:06:08.41#onoff#VAL oriona 216.0 41.8 u5 5 r 8430.00 1.0000 -100. 576.0 0.000 0.0000 2006.202.02:06:08.41?ERROR nf -7 WARNING: Source structure correction greater than 20% for detector u5. 2006.202.02:06:08.41#onoff#VAL oriona 216.0 41.8 u6 6 r 2350.00 1.0000 -100. 425.6 0.000 0.0000 2006.202.02:06:08.41#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.202.02:07:14.68;source=azel,0d,60d 2006.202.02:07:15.14#flagr#flagr/antenna,new-source 2006.202.02:08:10.14#trakl#Source acquired 2006.202.02:08:11.14#flagr#flagr/antenna,acquired 2006.202.02:08:29.95;caltsys 2006.202.02:08:29.95&caltsys/xfe=on,off 2006.202.02:08:29.95&caltsys/fe=off,,,,noise 2006.202.02:08:29.95&caltsys/tpi=u5,u6 2006.202.02:08:29.95&caltsys/ifatt=max,max,max,max 2006.202.02:08:29.95&caltsys/tpzero=u5,u6 2006.202.02:08:29.95&caltsys/ifatt=old,old,old,old 2006.202.02:08:29.95&caltsys/xfe=on,on 2006.202.02:08:29.95&caltsys/fe=on,,,,noise 2006.202.02:08:29.95&caltsys/tpical=u5,u6 2006.202.02:08:29.95&caltsys/tpdiff=u5,u6 2006.202.02:08:29.95&caltsys/xfe=off,off 2006.202.02:08:29.95&caltsys/fe=on,,,,pcal 2006.202.02:08:29.95&caltsys/user_device=u5,7681,usb,rcp,750 2006.202.02:08:29.95&caltsys/user_device=u6,1601,usb,rcp,750 2006.202.02:08:29.95&caltsys/caltemp=u5,u6 2006.202.02:08:29.95&caltsys/tsys=u5,u6 2006.202.02:08:31.70/tpi/u5,120 2006.202.02:08:31.70/tpi/u6,45 2006.202.02:08:33.42/tpzero/u5,0 2006.202.02:08:33.42/tpzero/u6,0 2006.202.02:08:35.26/tpical/u5,198 2006.202.02:08:35.26/tpical/u6,89 2006.202.02:08:35.26/tpdiff/u5,78 2006.202.02:08:35.26/tpdiff/u6,44 2006.202.02:08:35.72/caltemp/u5,69.580 2006.202.02:08:35.72/caltemp/u6,70.400 2006.202.02:08:35.72/tsys/u5,107.0 2006.202.02:08:35.72/tsys/u6,72.0 2006.202.02:11:28.11?ERROR st -97 Trouble decoding pressure data 2006.202.02:11:28.11#wxget#04 1.7 3.1 20.481001000.5 2006.202.02:11:41.50;caltsys 2006.202.02:11:43.38/tpi/u5,170 2006.202.02:11:43.38/tpi/u6,49 2006.202.02:11:44.73/tpzero/u5,0 2006.202.02:11:44.73/tpzero/u6,0 2006.202.02:11:46.59/tpical/u5,246 2006.202.02:11:46.59/tpical/u6,91 2006.202.02:11:46.59/tpdiff/u5,76 2006.202.02:11:46.59/tpdiff/u6,42 2006.202.02:11:47.05/caltemp/u5,69.580 2006.202.02:11:47.05/caltemp/u6,70.400 2006.202.02:11:47.05/tsys/u5,155.6 2006.202.02:11:47.05/tsys/u6,82.1 2006.202.02:12:11.27;caltsys 2006.202.02:12:13.42/tpi/u5,168 2006.202.02:12:13.42/tpi/u6,49 2006.202.02:12:14.81/tpzero/u5,0 2006.202.02:12:14.81/tpzero/u6,0 2006.202.02:12:16.65/tpical/u5,243 2006.202.02:12:16.65/tpical/u6,92 2006.202.02:12:16.65/tpdiff/u5,75 2006.202.02:12:16.65/tpdiff/u6,43 2006.202.02:12:17.11/caltemp/u5,69.580 2006.202.02:12:17.11/caltemp/u6,70.400 2006.202.02:12:17.11/tsys/u5,155.9 2006.202.02:12:17.11/tsys/u6,80.2 2006.202.02:13:44.73;stow 2006.202.02:13:44.73&stow/source=idle 2006.202.02:13:44.73&stow/"this is stow command. 2006.202.02:13:44.73&stow/antenna=m3 2006.202.02:13:46.13#flagr#flagr/antenna,new-source 2006.202.02:15:13.16;standby 2006.202.02:15:13.16&standby/"this is standby command. 2006.202.02:15:13.16&standby/antenna=m0 2006.202.02:15:15.88;terminate 2006.202.02:15:15.88:*boss terminated